diff --git a/qcom/opensource/dataipa/BUILD.bazel b/qcom/opensource/dataipa/BUILD.bazel new file mode 100644 index 0000000000..453167b881 --- /dev/null +++ b/qcom/opensource/dataipa/BUILD.bazel @@ -0,0 +1,116 @@ +load(":define_modules.bzl", "define_modules") +load("//build/kernel/kleaf:kernel.bzl", "ddk_headers") + +define_modules("pineapple", "consolidate") + +define_modules("pineapple", "gki") + +define_modules("blair", "consolidate") + +define_modules("blair", "gki") + +define_modules("monaco", "consolidate") + +define_modules("monaco", "gki") + +define_modules("pitti", "consolidate") + +define_modules("pitti", "gki") + +define_modules("volcano", "consolidate") + +define_modules("volcano", "gki") + +define_modules("niobe", "consolidate") + +define_modules("niobe", "gki") +package( + default_visibility = [ + "//visibility:public", + ], +) + +ddk_headers( + name = "include_headers", + hdrs = glob([ + "drivers/platform/msm/include/linux/*.h", + "drivers/platform/msm/include/uapi/linux/*.h", + ]), + includes = [ + "drivers/platform/msm/include", + "drivers/platform/msm/include/linux", + "drivers/platform/msm/include/uapi", + ], +) + +ddk_headers( + name = "gsi_headers", + hdrs = glob([ + "drivers/platform/msm/gsi/*.h", + "drivers/platform/msm/gsi/gsihal/*.h", + ]), + includes = [ + "drivers/platform/msm/gsi", + "drivers/platform/msm/gsi/gsihal", + ], +) + +ddk_headers( + name = "ipa_headers", + hdrs = glob([ + "drivers/platform/msm/ipa/*.h", + "drivers/platform/msm/ipa/ipa_test_module/*.h", + "drivers/platform/msm/ipa/ipa_v3/*.h", + "drivers/platform/msm/ipa/ipa_v3/ipahal/*.h", + ]), + includes = [ + "drivers/platform/msm/ipa", + "drivers/platform/msm/ipa/ipa_test_module", + "drivers/platform/msm/ipa/ipa_v3", + "drivers/platform/msm/ipa/ipa_v3/ipahal", + ], +) + +ddk_headers( + name = "ipa_clients", + hdrs = glob([ + "drivers/platform/msm/ipa/ipa_clients/*.h", + ]), + includes = ["drivers/platform/msm/ipa/ipa_clients"], +) + +ddk_headers( + name = "consolidate_config_headers", + hdrs = [ + "config/dataipa_debug.h", + "config/dataipa_vendor.h", + ], + includes = ["config"], +) + +ddk_headers( + name = "gki_config_headers", + hdrs = [ + "config/dataipa_vendor.h", + ], + includes = ["config"], +) + +genrule( + name = "consolidate_defconfig", + srcs = [ + "config/dataipa_GKI_consolidate.conf", + "config/dataipa_GKI.conf", + ], + outs = ["consolidate_defconfig.conf"], + cmd = "cat $(SRCS) | sed -e 's/^export //g' > $@", +) + +genrule( + name = "gki_defconfig", + srcs = [ + "config/dataipa_GKI.conf", + ], + outs = ["gki_defconfig.conf"], + cmd = "cat $(SRCS) | sed -e 's/^export //g' > $@", +) diff --git a/qcom/opensource/dataipa/Makefile b/qcom/opensource/dataipa/Makefile new file mode 100644 index 0000000000..a92554b5b3 --- /dev/null +++ b/qcom/opensource/dataipa/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only + +obj-$(CONFIG_ARCH_QCOM) += drivers/platform/msm/ diff --git a/qcom/opensource/dataipa/config/Kconfig b/qcom/opensource/dataipa/config/Kconfig new file mode 100644 index 0000000000..73455dc51c --- /dev/null +++ b/qcom/opensource/dataipa/config/Kconfig @@ -0,0 +1,68 @@ +config GSI + tristate "Short description of export GSI" + help + Long description of export GSI + +config IPA_CLIENTS_MANAGER + tristate "Short description of export IPA_CLIENTS_MANAGER" + help + Long description of export IPA_CLIENTS_MANAGER +config IPA_WDI_UNIFIED_API + bool "Short description of export IPA_WDI_UNIFIED_API" + help + Long description of export IPA_WDI_UNIFIED_API + +config RMNET_IPA3 + bool "Short description of export RMNET_IPA3" + help + Long description of export RMNET_IPA3 + +config RNDIS_IPA + tristate "Short description of export RNDIS_IPA" + help + Long description of export RNDIS_IPA + +config IPA3_REGDUMP + bool "Short description of export IPA3_REGDUMP" + help + Long description of export IPA3_REGDUMP + +config IPA3_REGDUMP_IPA_5_5 + bool "Short description of export IPA3_REGDUMP_IPA_5_5" + help + Long description of export IPA3_REGDUMP_IPA_5_5 + +config IPA_KERNEL_TESTS_MODULE + tristate "Short description of export IPA_KERNEL_TESTS_MODULE" + help + Long description of export IPA_KERNEL_TESTS_MODULE + +config IPA3_MHI_PRIME_MANAGER + bool "Short description of export IPA_KERNEL_TESTS_MODULE" + help + Long description of export IPA_KERNEL_TESTS_MODULE + +config IPA_TSP + bool "Short description of export IPA_TSP" + help + Long description of export IPA_TSP + +config ECM_IPA + bool "Short description of export CONFIG_ECM_IPA" + help + Long description of export CONFIG_ECM_IPA + +config IPA_EMULATION + bool "Short description of export CONFIG_IPA_EMULATION" + help + Long description of export CONFIG_IPA_EMULATION + +config IPA_DEBUG + bool "Short description of export IPA_DEBUG" + help + Long description of export IPA_DEBUG + +config IPA_UT + bool "Short description of export CONFIG_IPA_UT" + help + Long description of export CONFIG_IPA_UT diff --git a/qcom/opensource/dataipa/config/LICENSE b/qcom/opensource/dataipa/config/LICENSE new file mode 100644 index 0000000000..ecbc059373 --- /dev/null +++ b/qcom/opensource/dataipa/config/LICENSE @@ -0,0 +1,339 @@ + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. By contrast, the GNU General Public +License is intended to guarantee your freedom to share and change free +software--to make sure the software is free for all its users. This +General Public License applies to most of the Free Software +Foundation's software and to any other program whose authors commit to +using it. (Some other Free Software Foundation software is covered by +the GNU Lesser General Public License instead.) You can apply it to +your programs, too. + + When we speak of free software, we are referring to freedom, not +price. Our General Public Licenses are designed to make sure that you +have the freedom to distribute copies of free software (and charge for +this service if you wish), that you receive source code or can get it +if you want it, that you can change the software or use pieces of it +in new free programs; and that you know you can do these things. + + To protect your rights, we need to make restrictions that forbid +anyone to deny you these rights or to ask you to surrender the rights. +These restrictions translate to certain responsibilities for you if you +distribute copies of the software, or if you modify it. + + For example, if you distribute copies of such a program, whether +gratis or for a fee, you must give the recipients all the rights that +you have. You must make sure that they, too, receive or can get the +source code. And you must show them these terms so they know their +rights. + + We protect your rights with two steps: (1) copyright the software, and +(2) offer you this license which gives you legal permission to copy, +distribute and/or modify the software. + + Also, for each author's protection and ours, we want to make certain +that everyone understands that there is no warranty for this free +software. If the software is modified by someone else and passed on, we +want its recipients to know that what they have is not the original, so +that any problems introduced by others will not reflect on the original +authors' reputations. + + Finally, any free program is threatened constantly by software +patents. We wish to avoid the danger that redistributors of a free +program will individually obtain patent licenses, in effect making the +program proprietary. To prevent this, we have made it clear that any +patent must be licensed for everyone's free use or not licensed at all. + + The precise terms and conditions for copying, distribution and +modification follow. + + GNU GENERAL PUBLIC LICENSE + TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION + + 0. This License applies to any program or other work which contains +a notice placed by the copyright holder saying it may be distributed +under the terms of this General Public License. The "Program", below, +refers to any such program or work, and a "work based on the Program" +means either the Program or any derivative work under copyright law: +that is to say, a work containing the Program or a portion of it, +either verbatim or with modifications and/or translated into another +language. (Hereinafter, translation is included without limitation in +the term "modification".) Each licensee is addressed as "you". + +Activities other than copying, distribution and modification are not +covered by this License; they are outside its scope. The act of +running the Program is not restricted, and the output from the Program +is covered only if its contents constitute a work based on the +Program (independent of having been made by running the Program). +Whether that is true depends on what the Program does. + + 1. You may copy and distribute verbatim copies of the Program's +source code as you receive it, in any medium, provided that you +conspicuously and appropriately publish on each copy an appropriate +copyright notice and disclaimer of warranty; keep intact all the +notices that refer to this License and to the absence of any warranty; +and give any other recipients of the Program a copy of this License +along with the Program. + +You may charge a fee for the physical act of transferring a copy, and +you may at your option offer warranty protection in exchange for a fee. + + 2. You may modify your copy or copies of the Program or any portion +of it, thus forming a work based on the Program, and copy and +distribute such modifications or work under the terms of Section 1 +above, provided that you also meet all of these conditions: + + a) You must cause the modified files to carry prominent notices + stating that you changed the files and the date of any change. + + b) You must cause any work that you distribute or publish, that in + whole or in part contains or is derived from the Program or any + part thereof, to be licensed as a whole at no charge to all third + parties under the terms of this License. + + c) If the modified program normally reads commands interactively + when run, you must cause it, when started running for such + interactive use in the most ordinary way, to print or display an + announcement including an appropriate copyright notice and a + notice that there is no warranty (or else, saying that you provide + a warranty) and that users may redistribute the program under + these conditions, and telling the user how to view a copy of this + License. (Exception: if the Program itself is interactive but + does not normally print such an announcement, your work based on + the Program is not required to print an announcement.) + +These requirements apply to the modified work as a whole. If +identifiable sections of that work are not derived from the Program, +and can be reasonably considered independent and separate works in +themselves, then this License, and its terms, do not apply to those +sections when you distribute them as separate works. But when you +distribute the same sections as part of a whole which is a work based +on the Program, the distribution of the whole must be on the terms of +this License, whose permissions for other licensees extend to the +entire whole, and thus to each and every part regardless of who wrote it. + +Thus, it is not the intent of this section to claim rights or contest +your rights to work written entirely by you; rather, the intent is to +exercise the right to control the distribution of derivative or +collective works based on the Program. + +In addition, mere aggregation of another work not based on the Program +with the Program (or with a work based on the Program) on a volume of +a storage or distribution medium does not bring the other work under +the scope of this License. + + 3. You may copy and distribute the Program (or a work based on it, +under Section 2) in object code or executable form under the terms of +Sections 1 and 2 above provided that you also do one of the following: + + a) Accompany it with the complete corresponding machine-readable + source code, which must be distributed under the terms of Sections + 1 and 2 above on a medium customarily used for software interchange; or, + + b) Accompany it with a written offer, valid for at least three + years, to give any third party, for a charge no more than your + cost of physically performing source distribution, a complete + machine-readable copy of the corresponding source code, to be + distributed under the terms of Sections 1 and 2 above on a medium + customarily used for software interchange; or, + + c) Accompany it with the information you received as to the offer + to distribute corresponding source code. (This alternative is + allowed only for noncommercial distribution and only if you + received the program in object code or executable form with such + an offer, in accord with Subsection b above.) + +The source code for a work means the preferred form of the work for +making modifications to it. For an executable work, complete source +code means all the source code for all modules it contains, plus any +associated interface definition files, plus the scripts used to +control compilation and installation of the executable. However, as a +special exception, the source code distributed need not include +anything that is normally distributed (in either source or binary +form) with the major components (compiler, kernel, and so on) of the +operating system on which the executable runs, unless that component +itself accompanies the executable. + +If distribution of executable or object code is made by offering +access to copy from a designated place, then offering equivalent +access to copy the source code from the same place counts as +distribution of the source code, even though third parties are not +compelled to copy the source along with the object code. + + 4. You may not copy, modify, sublicense, or distribute the Program +except as expressly provided under this License. Any attempt +otherwise to copy, modify, sublicense or distribute the Program is +void, and will automatically terminate your rights under this License. +However, parties who have received copies, or rights, from you under +this License will not have their licenses terminated so long as such +parties remain in full compliance. + + 5. You are not required to accept this License, since you have not +signed it. However, nothing else grants you permission to modify or +distribute the Program or its derivative works. These actions are +prohibited by law if you do not accept this License. Therefore, by +modifying or distributing the Program (or any work based on the +Program), you indicate your acceptance of this License to do so, and +all its terms and conditions for copying, distributing or modifying +the Program or works based on it. + + 6. Each time you redistribute the Program (or any work based on the +Program), the recipient automatically receives a license from the +original licensor to copy, distribute or modify the Program subject to +these terms and conditions. You may not impose any further +restrictions on the recipients' exercise of the rights granted herein. +You are not responsible for enforcing compliance by third parties to +this License. + + 7. If, as a consequence of a court judgment or allegation of patent +infringement or for any other reason (not limited to patent issues), +conditions are imposed on you (whether by court order, agreement or +otherwise) that contradict the conditions of this License, they do not +excuse you from the conditions of this License. If you cannot +distribute so as to satisfy simultaneously your obligations under this +License and any other pertinent obligations, then as a consequence you +may not distribute the Program at all. For example, if a patent +license would not permit royalty-free redistribution of the Program by +all those who receive copies directly or indirectly through you, then +the only way you could satisfy both it and this License would be to +refrain entirely from distribution of the Program. + +If any portion of this section is held invalid or unenforceable under +any particular circumstance, the balance of the section is intended to +apply and the section as a whole is intended to apply in other +circumstances. + +It is not the purpose of this section to induce you to infringe any +patents or other property right claims or to contest validity of any +such claims; this section has the sole purpose of protecting the +integrity of the free software distribution system, which is +implemented by public license practices. Many people have made +generous contributions to the wide range of software distributed +through that system in reliance on consistent application of that +system; it is up to the author/donor to decide if he or she is willing +to distribute software through any other system and a licensee cannot +impose that choice. + +This section is intended to make thoroughly clear what is believed to +be a consequence of the rest of this License. + + 8. If the distribution and/or use of the Program is restricted in +certain countries either by patents or by copyrighted interfaces, the +original copyright holder who places the Program under this License +may add an explicit geographical distribution limitation excluding +those countries, so that distribution is permitted only in or among +countries not thus excluded. In such case, this License incorporates +the limitation as if written in the body of this License. + + 9. The Free Software Foundation may publish revised and/or new versions +of the General Public License from time to time. Such new versions will +be similar in spirit to the present version, but may differ in detail to +address new problems or concerns. + +Each version is given a distinguishing version number. If the Program +specifies a version number of this License which applies to it and "any +later version", you have the option of following the terms and conditions +either of that version or of any later version published by the Free +Software Foundation. If the Program does not specify a version number of +this License, you may choose any version ever published by the Free Software +Foundation. + + 10. If you wish to incorporate parts of the Program into other free +programs whose distribution conditions are different, write to the author +to ask for permission. For software which is copyrighted by the Free +Software Foundation, write to the Free Software Foundation; we sometimes +make exceptions for this. Our decision will be guided by the two goals +of preserving the free status of all derivatives of our free software and +of promoting the sharing and reuse of software generally. + + NO WARRANTY + + 11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY +FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN +OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES +PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED +OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS +TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE +PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, +REPAIR OR CORRECTION. + + 12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING +WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR +REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, +INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING +OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED +TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY +YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER +PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE +POSSIBILITY OF SUCH DAMAGES. + + END OF TERMS AND CONDITIONS + + How to Apply These Terms to Your New Programs + + If you develop a new program, and you want it to be of the greatest +possible use to the public, the best way to achieve this is to make it +free software which everyone can redistribute and change under these terms. + + To do so, attach the following notices to the program. It is safest +to attach them to the start of each source file to most effectively +convey the exclusion of warranty; and each file should have at least +the "copyright" line and a pointer to where the full notice is found. + + + Copyright (C) + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + +Also add information on how to contact you by electronic and paper mail. + +If the program is interactive, make it output a short notice like this +when it starts in an interactive mode: + + Gnomovision version 69, Copyright (C) year name of author + Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, the commands you use may +be called something other than `show w' and `show c'; they could even be +mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the program, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the program + `Gnomovision' (which makes passes at compilers) written by James Hacker. + + , 1 April 1989 + Ty Coon, President of Vice + +This General Public License does not permit incorporating your program into +proprietary programs. If your program is a subroutine library, you may +consider it more useful to permit linking proprietary applications with the +library. If this is what you want to do, use the GNU Lesser General +Public License instead of this License. \ No newline at end of file diff --git a/qcom/opensource/dataipa/config/NOTICE b/qcom/opensource/dataipa/config/NOTICE new file mode 100644 index 0000000000..5a30e9af65 --- /dev/null +++ b/qcom/opensource/dataipa/config/NOTICE @@ -0,0 +1,10 @@ +Copyright (c) 2021 The Linux Foundation. All rights reserved. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License version 2 and +only version 2 as published by the Free Software Foundation. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. \ No newline at end of file diff --git a/qcom/opensource/dataipa/config/dataipa.h b/qcom/opensource/dataipa/config/dataipa.h new file mode 100644 index 0000000000..c8bfa483da --- /dev/null +++ b/qcom/opensource/dataipa/config/dataipa.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* +* Copyright (c) 2020, The Linux Foundation. All rights reserved. +* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. +*/ + +#define CONFIG_GSI 1 +#define CONFIG_RMNET_IPA3 1 +#define CONFIG_RNDIS_IPA 1 +#define CONFIG_IPA_WDI_UNIFIED_API 1 +#define CONFIG_ECM_IPA 1 +#define CONFIG_IPA3_REGDUMP 1 +#define CONFIG_IPA3_REGDUMP_IPA_5_5 1 diff --git a/qcom/opensource/dataipa/config/dataipa_GKI.conf b/qcom/opensource/dataipa/config/dataipa_GKI.conf new file mode 100644 index 0000000000..67a564e5e8 --- /dev/null +++ b/qcom/opensource/dataipa/config/dataipa_GKI.conf @@ -0,0 +1,8 @@ +export CONFIG_GSI=m +export CONFIG_IPA_CLIENTS_MANAGER=m +export CONFIG_IPA_WDI_UNIFIED_API=y +export CONFIG_RMNET_IPA3=y +export CONFIG_RNDIS_IPA=m +export CONFIG_IPA3_REGDUMP=y +export CONFIG_IPA3_REGDUMP_IPA_5_5=y +export CONFIG_IPA_KERNEL_TESTS_MODULE=m diff --git a/qcom/opensource/dataipa/config/dataipa_GKI_consolidate.conf b/qcom/opensource/dataipa/config/dataipa_GKI_consolidate.conf new file mode 100644 index 0000000000..4aad364440 --- /dev/null +++ b/qcom/opensource/dataipa/config/dataipa_GKI_consolidate.conf @@ -0,0 +1,2 @@ +export CONFIG_IPA_DEBUG=y +export CONFIG_IPA_UT=y diff --git a/qcom/opensource/dataipa/config/dataipa_GKI_ipav4.conf b/qcom/opensource/dataipa/config/dataipa_GKI_ipav4.conf new file mode 100644 index 0000000000..075a7198f2 --- /dev/null +++ b/qcom/opensource/dataipa/config/dataipa_GKI_ipav4.conf @@ -0,0 +1,5 @@ +export CONFIG_GSI=m +export CONFIG_IPA_CLIENTS_MANAGER=m +export CONFIG_IPA_WDI_UNIFIED_API=y +export CONFIG_RMNET_IPA3=y +export CONFIG_RNDIS_IPA=m diff --git a/qcom/opensource/dataipa/config/dataipa_QGKI.conf b/qcom/opensource/dataipa/config/dataipa_QGKI.conf new file mode 100644 index 0000000000..b782fe5cc9 --- /dev/null +++ b/qcom/opensource/dataipa/config/dataipa_QGKI.conf @@ -0,0 +1,8 @@ +export CONFIG_GSI=y +export CONFIG_IPA_CLIENTS_MANAGER=y +export CONFIG_IPA_WDI_UNIFIED_API=y +export CONFIG_RMNET_IPA3=y +export CONFIG_RNDIS_IPA=y +export CONFIG_ECM_IPA=y +export CONFIG_IPA3_REGDUMP=y +export CONFIG_IPA3_REGDUMP_IPA_5_5=y diff --git a/qcom/opensource/dataipa/config/dataipa_debug.conf b/qcom/opensource/dataipa/config/dataipa_debug.conf new file mode 100644 index 0000000000..2c999cde21 --- /dev/null +++ b/qcom/opensource/dataipa/config/dataipa_debug.conf @@ -0,0 +1,3 @@ +export CONFIG_IPA_DEBUG=y +export CONFIG_IPA_UT=y +export CONFIG_IPA_KERNEL_TESTS_MODULE=y diff --git a/qcom/opensource/dataipa/config/dataipa_debug.h b/qcom/opensource/dataipa/config/dataipa_debug.h new file mode 100644 index 0000000000..7b2cc4bc77 --- /dev/null +++ b/qcom/opensource/dataipa/config/dataipa_debug.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* +* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. +*/ + +#define CONFIG_IPA_DEBUG 1 +#define CONFIG_IPA_UT 1 +#define CONFIG_IPA_KERNEL_TESTS_MODULE 1 diff --git a/qcom/opensource/dataipa/config/dataipa_vendor.h b/qcom/opensource/dataipa/config/dataipa_vendor.h new file mode 100644 index 0000000000..907f45a8a8 --- /dev/null +++ b/qcom/opensource/dataipa/config/dataipa_vendor.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* +* Copyright (c) 2021, The Linux Foundation. All rights reserved. +* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. +*/ + +#define CONFIG_GSI 1 +#define CONFIG_RMNET_IPA3 1 +#define CONFIG_RNDIS_IPA 1 +#define CONFIG_IPA_WDI_UNIFIED_API 1 +#define CONFIG_IPA_VENDOR_DLKM 1 +#define CONFIG_IPA3_REGDUMP 1 +#define CONFIG_IPA3_REGDUMP_IPA_5_5 1 +#define CONFIG_IPA_KERNEL_TESTS_MODULE 1 diff --git a/qcom/opensource/dataipa/config/dataipa_vendor_ipav4.h b/qcom/opensource/dataipa/config/dataipa_vendor_ipav4.h new file mode 100644 index 0000000000..6616a91045 --- /dev/null +++ b/qcom/opensource/dataipa/config/dataipa_vendor_ipav4.h @@ -0,0 +1,10 @@ +/* +* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. +*/ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define CONFIG_GSI 1 +#define CONFIG_RMNET_IPA3 1 +#define CONFIG_RNDIS_IPA 1 +#define CONFIG_IPA_WDI_UNIFIED_API 1 +#define CONFIG_IPA_VENDOR_DLKM 1 diff --git a/qcom/opensource/dataipa/config/sa410mdataipa.h b/qcom/opensource/dataipa/config/sa410mdataipa.h new file mode 100644 index 0000000000..296153f1bd --- /dev/null +++ b/qcom/opensource/dataipa/config/sa410mdataipa.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* +* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. +*/ + +#define CONFIG_GSI 1 +#define CONFIG_RMNET_IPA3 1 +#define CONFIG_RNDIS_IPA 1 +#define CONFIG_ECM_IPA 1 +#define CONFIG_IPA_WDI_UNIFIED_API 1 diff --git a/qcom/opensource/dataipa/config/sa410mdataipa_QGKI.conf b/qcom/opensource/dataipa/config/sa410mdataipa_QGKI.conf new file mode 100644 index 0000000000..718f6b953a --- /dev/null +++ b/qcom/opensource/dataipa/config/sa410mdataipa_QGKI.conf @@ -0,0 +1,6 @@ +export CONFIG_GSI=y +export CONFIG_IPA_CLIENTS_MANAGER=y +export CONFIG_IPA_WDI_UNIFIED_API=y +export CONFIG_RMNET_IPA3=y +export CONFIG_RNDIS_IPA=y +export CONFIG_ECM_IPA=y diff --git a/qcom/opensource/dataipa/config/sdx12dataipa.h b/qcom/opensource/dataipa/config/sdx12dataipa.h new file mode 100644 index 0000000000..1efb54b23d --- /dev/null +++ b/qcom/opensource/dataipa/config/sdx12dataipa.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* +* Copyright (c) 2020, The Linux Foundation. All rights reserved. +*/ + +#define CONFIG_GSI 1 +#define CONFIG_RMNET_IPA3 1 +#define CONFIG_RNDIS_IPA 1 +#define CONFIG_ECM_IPA 1 + diff --git a/qcom/opensource/dataipa/config/sdx12dataipa_QGKI.conf b/qcom/opensource/dataipa/config/sdx12dataipa_QGKI.conf new file mode 100644 index 0000000000..9ae50f8c38 --- /dev/null +++ b/qcom/opensource/dataipa/config/sdx12dataipa_QGKI.conf @@ -0,0 +1,5 @@ +export CONFIG_GSI=y +export CONFIG_IPA_CLIENTS_MANAGER=y +export CONFIG_RMNET_IPA3=y +export CONFIG_RNDIS_IPA=y +export CONFIG_ECM_IPA=y diff --git a/qcom/opensource/dataipa/dataipa_binary_vendor_product.mk b/qcom/opensource/dataipa/dataipa_binary_vendor_product.mk new file mode 100644 index 0000000000..4b4fc99db7 --- /dev/null +++ b/qcom/opensource/dataipa/dataipa_binary_vendor_product.mk @@ -0,0 +1,4 @@ +ifeq ($(CONFIG_LOCALVERSION), "-gki-consolidate") +PRODUCT_PACKAGES += ipa-kernel-tests +$(warning "added ipa-kernel-tests") +endif diff --git a/qcom/opensource/dataipa/dataipa_dlkm_vendor_board.mk b/qcom/opensource/dataipa/dataipa_dlkm_vendor_board.mk new file mode 100644 index 0000000000..d3e1ca70b8 --- /dev/null +++ b/qcom/opensource/dataipa/dataipa_dlkm_vendor_board.mk @@ -0,0 +1,23 @@ +#Build ipa +TARGET_DATAIPA_DLKM_ENABLE := false +ifeq ($(TARGET_KERNEL_DLKM_DISABLE), true) + ifeq ($(TARGET_KERNEL_DLKM_DATAIPA_OVERRIDE), true) + TARGET_DATAIPA_DLKM_ENABLE := true + endif +else + TARGET_DATAIPA_DLKM_ENABLE := true +endif + +ifeq ($(TARGET_DATAIPA_DLKM_ENABLE), true) +DATA_DLKM_BOARD_PLATFORMS_LIST := taro kalama bengal monaco pineapple blair holi cliffs pitti volcano niobe +ifneq ($(TARGET_BOARD_AUTO),true) +ifeq ($(call is-board-platform-in-list,$(DATA_DLKM_BOARD_PLATFORMS_LIST)),true) +BOARD_VENDOR_KERNEL_MODULES += $(KERNEL_MODULES_OUT)/gsim.ko +BOARD_VENDOR_KERNEL_MODULES += $(KERNEL_MODULES_OUT)/ipam.ko +BOARD_VENDOR_KERNEL_MODULES += $(KERNEL_MODULES_OUT)/ipanetm.ko +ifeq ($(CONFIG_LOCALVERSION), "-gki-consolidate") +BOARD_VENDOR_KERNEL_MODULES += $(KERNEL_MODULES_OUT)/ipatestm.ko +endif +endif +endif +endif diff --git a/qcom/opensource/dataipa/dataipa_dlkm_vendor_product.mk b/qcom/opensource/dataipa/dataipa_dlkm_vendor_product.mk new file mode 100644 index 0000000000..5a4e3b030c --- /dev/null +++ b/qcom/opensource/dataipa/dataipa_dlkm_vendor_product.mk @@ -0,0 +1,6 @@ +PRODUCT_PACKAGES += gsim.ko +PRODUCT_PACKAGES += ipam.ko +PRODUCT_PACKAGES += ipanetm.ko +ifeq ($(CONFIG_LOCALVERSION), "-gki-consolidate") +PRODUCT_PACKAGES += ipatestm.ko +endif diff --git a/qcom/opensource/dataipa/define_modules.bzl b/qcom/opensource/dataipa/define_modules.bzl new file mode 100644 index 0000000000..84b89ef8ea --- /dev/null +++ b/qcom/opensource/dataipa/define_modules.bzl @@ -0,0 +1,296 @@ +load("//build/bazel_common_rules/dist:dist.bzl", "copy_to_dist_dir") +load("//msm-kernel:target_variants.bzl", "get_all_variants") +load("//build/kernel/kleaf:kernel.bzl", "ddk_module") + +def define_modules(target, variant): + kernel_build_variant = "{}_{}".format(target, variant) + include_base = "../../../{}".format(native.package_name()) + + #The below will take care of the defconfig + include_defconfig = ":{}_defconfig".format(variant) + + mod_list = [] + ipam_deps_list = [] + ipam_local_defines = [] + if target != "niobe": + ipam_deps_list.append( + "//vendor/qcom/opensource/datarmnet-ext/mem:{}_rmnet_mem".format(kernel_build_variant), + ) + ipam_local_defines.append( + "CONFIG_IPA_RMNET_MEM=y".format(include_base), + ) + if target == "niobe": + ipam_deps_list.extend([ + "//vendor/qcom/opensource/synx-kernel:synx_headers", + "//vendor/qcom/opensource/synx-kernel:{}_modules".format(kernel_build_variant), + ]) + ipam_local_defines.append( + "CONFIG_IPA_RTP=y".format(include_base), + ) + + ddk_module( + name = "{}_gsim".format(kernel_build_variant), + out = "gsim.ko", + srcs = [ + "drivers/platform/msm/gsi/gsi.c", + "drivers/platform/msm/gsi/gsi.h", + "drivers/platform/msm/gsi/gsi_dbg.c", + "drivers/platform/msm/gsi/gsi_emulation.h", + "drivers/platform/msm/gsi/gsi_emulation_stubs.h", + "drivers/platform/msm/gsi/gsi_trace.h", + "drivers/platform/msm/gsi/gsihal/gsihal.c", + "drivers/platform/msm/gsi/gsihal/gsihal.h", + "drivers/platform/msm/gsi/gsihal/gsihal_i.h", + "drivers/platform/msm/gsi/gsihal/gsihal_reg.c", + "drivers/platform/msm/gsi/gsihal/gsihal_reg.h", + "drivers/platform/msm/gsi/gsihal/gsihal_reg_i.h", + ], + kconfig = "config/Kconfig", + defconfig = include_defconfig, + conditional_srcs = { + "CONFIG_IPA_EMULATION": { + True: [ + "drivers/platform/msm/gsi/gsi_emulation.c", + ], + }, + }, + local_defines = [ + "GSI_TRACE_INCLUDE_PATH={}/drivers/platform/msm/gsi".format(include_base), + ], + kernel_build = "//msm-kernel:{}".format(kernel_build_variant), + deps = [ + ":gsi_headers", + ":include_headers", + "//msm-kernel:all_headers", + ], + ) + mod_list.append("{}_gsim".format(kernel_build_variant)) + + ddk_module( + name = "{}_ipam".format(kernel_build_variant), + out = "ipam.ko", + srcs = [ + "drivers/platform/msm/ipa/ipa_v3/ipa.c", + "drivers/platform/msm/ipa/ipa_v3/ipa_client.c", + "drivers/platform/msm/ipa/ipa_v3/ipa_debugfs.c", + "drivers/platform/msm/ipa/ipa_v3/ipa_defs.h", + "drivers/platform/msm/ipa/ipa_v3/ipa_dma.c", + "drivers/platform/msm/ipa/ipa_v3/ipa_dp.c", + "drivers/platform/msm/ipa/ipa_v3/ipa_emulation_stubs.h", + "drivers/platform/msm/ipa/ipa_v3/ipa_eth_i.c", + "drivers/platform/msm/ipa/ipa_v3/ipa_flt.c", + "drivers/platform/msm/ipa/ipa_v3/ipa_hdr.c", + "drivers/platform/msm/ipa/ipa_v3/ipa_hw_stats.c", + "drivers/platform/msm/ipa/ipa_v3/ipa_i.h", + "drivers/platform/msm/ipa/ipa_v3/ipa_interrupts.c", + "drivers/platform/msm/ipa/ipa_v3/ipa_intf.c", + "drivers/platform/msm/ipa/ipa_v3/ipa_mhi.c", + "drivers/platform/msm/ipa/ipa_v3/ipa_nat.c", + "drivers/platform/msm/ipa/ipa_v3/ipa_odl.c", + "drivers/platform/msm/ipa/ipa_v3/ipa_odl.h", + "drivers/platform/msm/ipa/ipa_v3/ipa_pm.c", + "drivers/platform/msm/ipa/ipa_v3/ipa_pm.h", + "drivers/platform/msm/ipa/ipa_v3/ipa_qdss.c", + "drivers/platform/msm/ipa/ipa_v3/ipa_qmi_service.c", + "drivers/platform/msm/ipa/ipa_v3/ipa_qmi_service.h", + "drivers/platform/msm/ipa/ipa_v3/ipa_qmi_service_v01.c", + "drivers/platform/msm/ipa/ipa_v3/ipa_rt.c", + "drivers/platform/msm/ipa/ipa_v3/ipa_stats.c", + "drivers/platform/msm/ipa/ipa_v3/ipa_stats.h", + "drivers/platform/msm/ipa/ipa_v3/ipa_trace.h", + "drivers/platform/msm/ipa/ipa_v3/ipa_uc.c", + "drivers/platform/msm/ipa/ipa_v3/ipa_uc_holb_monitor.c", + "drivers/platform/msm/ipa/ipa_v3/ipa_uc_holb_monitor.h", + "drivers/platform/msm/ipa/ipa_v3/ipa_uc_mhi.c", + "drivers/platform/msm/ipa/ipa_v3/ipa_uc_ntn.c", + "drivers/platform/msm/ipa/ipa_v3/ipa_uc_offload_i.h", + "drivers/platform/msm/ipa/ipa_v3/ipa_uc_wdi.c", + "drivers/platform/msm/ipa/ipa_v3/ipa_utils.c", + "drivers/platform/msm/ipa/ipa_v3/ipa_wdi3_i.c", + "drivers/platform/msm/ipa/ipa_v3/ipa_wigig_i.c", + "drivers/platform/msm/ipa/ipa_v3/rmnet_ctl_ipa.c", + "drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c", + "drivers/platform/msm/ipa/ipa_v3/rmnet_ipa_fd_ioctl.c", + "drivers/platform/msm/ipa/ipa_v3/rmnet_ll_ipa.c", + "drivers/platform/msm/ipa/ipa_v3/teth_bridge.c", + "drivers/platform/msm/ipa/ipa_clients/ipa_eth.c", + "drivers/platform/msm/ipa/ipa_clients/ipa_gsb.c", + "drivers/platform/msm/ipa/ipa_clients/ipa_mhi_client.c", + "drivers/platform/msm/ipa/ipa_clients/ipa_uc_offload.c", + "drivers/platform/msm/ipa/ipa_clients/ipa_usb.c", + "drivers/platform/msm/ipa/ipa_clients/ipa_wdi3.c", + "drivers/platform/msm/ipa/ipa_clients/ipa_wigig.c", + "drivers/platform/msm/ipa/ipa_clients/rndis_ipa.h", + "drivers/platform/msm/ipa/ipa_clients/rndis_ipa_trace.h", + "drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal.c", + "drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal.h", + "drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_fltrt.c", + "drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_fltrt.h", + "drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_fltrt_i.h", + "drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_hw_stats.c", + "drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_hw_stats.h", + "drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_hw_stats_i.h", + "drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_i.h", + "drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_nat.c", + "drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_nat.h", + "drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_nat_i.h", + "drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.c", + "drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.h", + "drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg_i.h", + "drivers/platform/msm/ipa/ipa_v3/ipa_tsp.h", + "drivers/platform/msm/ipa/ipa_clients/ecm_ipa.h", + "drivers/platform/msm/ipa/ipa_v3/dump/ipa5.5/gsi_hwio.h", + "drivers/platform/msm/ipa/ipa_v3/dump/ipa5.5/gsi_hwio_def.h", + "drivers/platform/msm/ipa/ipa_v3/dump/ipa5.5/ipa_access_control.h", + "drivers/platform/msm/ipa/ipa_v3/dump/ipa5.5/ipa_gcc_hwio.h", + "drivers/platform/msm/ipa/ipa_v3/dump/ipa5.5/ipa_gcc_hwio_def.h", + "drivers/platform/msm/ipa/ipa_v3/dump/ipa5.5/ipa_hw_common_ex.h", + "drivers/platform/msm/ipa/ipa_v3/dump/ipa5.5/ipa_hwio.h", + "drivers/platform/msm/ipa/ipa_v3/dump/ipa5.5/ipa_hwio_def.h", + "drivers/platform/msm/ipa/ipa_v3/dump/ipa5.5/ipa_pkt_cntxt.h", + "drivers/platform/msm/ipa/ipa_v3/dump/ipa5.5/ipa_reg_dump.c", + "drivers/platform/msm/ipa/ipa_v3/dump/ipa5.5/ipa_reg_dump.h", + "drivers/platform/msm/ipa/ipa_common_i.h", + "drivers/platform/msm/ipa/ipa_rm.c", + "drivers/platform/msm/ipa/ipa_rm_dependency_graph.c", + "drivers/platform/msm/ipa/ipa_rm_dependency_graph.h", + "drivers/platform/msm/ipa/ipa_rm_i.h", + "drivers/platform/msm/ipa/ipa_rm_inactivity_timer.c", + "drivers/platform/msm/ipa/ipa_rm_peers_list.c", + "drivers/platform/msm/ipa/ipa_rm_peers_list.h", + "drivers/platform/msm/ipa/ipa_rm_resource.c", + "drivers/platform/msm/ipa/ipa_rm_resource.h", + "drivers/platform/msm/ipa/ipa_uc_offload_common_i.h", + ], + kconfig = "config/Kconfig", + defconfig = include_defconfig, + conditional_srcs = { + "CONFIG_IPA3_MHI_PRIME_MANAGER": { + True: [ + "drivers/platform/msm/ipa/ipa_v3/ipa_mpm.c", + ], + }, + "CONFIG_IPA3_MHI_PROXY": { + True: [ + "drivers/platform/msm/ipa/ipa_v3/ipa_mhi_proxy.h", + "drivers/platform/msm/ipa/ipa_v3/ipa_mhi_proxy.c", + ], + }, + "CONFIG_IPA_TSP": { + True: [ + "drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_tsp.c", + "drivers/platform/msm/ipa/ipa_v3/ipa_tsp.c", + ], + }, + "CONFIG_ECM_IPA": { + True: [ + "drivers/platform/msm/ipa/ipa_clients/ecm_ipa.c", + ], + }, + "CONFIG_RNDIS_IPA": { + True: [ + "drivers/platform/msm/ipa/ipa_clients/rndis_ipa.c", + ], + }, + "CONFIG_IPA_UT": { + True: [ + "drivers/platform/msm/ipa/test/ipa_ut_framework.c", + "drivers/platform/msm/ipa/test/ipa_ut_framework.h", + "drivers/platform/msm/ipa/test/ipa_ut_i.h", + "drivers/platform/msm/ipa/test/ipa_ut_suite_list.h", + "drivers/platform/msm/ipa/test/ipa_test_example.c", + "drivers/platform/msm/ipa/test/ipa_test_mhi.c", + "drivers/platform/msm/ipa/test/ipa_test_dma.c", + "drivers/platform/msm/ipa/test/ipa_test_hw_stats.c", + "drivers/platform/msm/ipa/test/ipa_pm_ut.c", + "drivers/platform/msm/ipa/test/ipa_test_wdi3.c", + "drivers/platform/msm/ipa/test/ipa_test_ntn.c", + ], + }, + "CONFIG_ARCH_NIOBE": { + True: [ + "drivers/platform/msm/ipa/ipa_v3/ipa_rtp_genl.h", + "drivers/platform/msm/ipa/ipa_v3/ipa_rtp_genl.c", + "drivers/platform/msm/ipa/ipa_v3/ipa_uc_rtp.c", + ], + }, + }, + local_defines = [ + "GSI_TRACE_INCLUDE_PATH={}/drivers/platform/msm/gsi".format(include_base), + "IPA_TRACE_INCLUDE_PATH={}/drivers/platform/msm/ipa/ipa_v3".format(include_base), + "RNDIS_TRACE_INCLUDE_PATH={}/drivers/platform/msm/ipa/ipa_clients".format(include_base), + ] + ipam_local_defines, + kernel_build = "//msm-kernel:{}".format(kernel_build_variant), + deps = [ + ":{}_config_headers".format(variant), + ":gsi_headers", + ":include_headers", + ":ipa_headers", + ":ipa_clients", + "//msm-kernel:all_headers", + ":{}_gsim".format(kernel_build_variant), + ] + ipam_deps_list, + ) + mod_list.append("{}_ipam".format(kernel_build_variant)) + + ddk_module( + name = "{}_ipanetm".format(kernel_build_variant), + out = "ipanetm.ko", + srcs = [ + "drivers/platform/msm/ipa/ipa_v3/ipa_net.c", + ], + kconfig = "config/Kconfig", + defconfig = include_defconfig, + kernel_build = "//msm-kernel:{}".format(kernel_build_variant), + local_defines = [ + "RNDIS_TRACE_INCLUDE_PATH={}/drivers/platform/msm/ipa/ipa_clients".format(include_base), + ], + deps = [ + ":{}_config_headers".format(variant), + ":{}_ipam".format(kernel_build_variant), + ":gsi_headers", + ":include_headers", + ":ipa_headers", + ":ipa_clients", + "//msm-kernel:all_headers", + ], + ) + mod_list.append("{}_ipanetm".format(kernel_build_variant)) + + if variant == "consolidate": + ddk_module( + name = "{}_ipatestm".format(kernel_build_variant), + out = "ipatestm.ko", + srcs = [ + "drivers/platform/msm/ipa/ipa_test_module/ipa_rm_ut.c", + "drivers/platform/msm/ipa/ipa_test_module/ipa_rm_ut.h", + "drivers/platform/msm/ipa/ipa_test_module/ipa_test_module.h", + "drivers/platform/msm/ipa/ipa_test_module/ipa_test_module_impl.c", + "drivers/platform/msm/ipa/ipa_test_module/ipa_test_module_tsp.h", + ], + kconfig = "config/Kconfig", + defconfig = include_defconfig, + kernel_build = "//msm-kernel:{}".format(kernel_build_variant), + deps = [ + ":consolidate_config_headers", + ":{}_ipam".format(kernel_build_variant), + ":gsi_headers", + ":include_headers", + ":ipa_headers", + ":ipa_clients", + "//msm-kernel:all_headers", + ":{}_gsim".format(kernel_build_variant), + ], + ) + mod_list.append("{}_ipatestm".format(kernel_build_variant)) + + copy_to_dist_dir( + name = "{}_modules_dist".format(kernel_build_variant), + data = mod_list, + dist_dir = "out/target/product/{}/dlkm/lib/modules/".format(target), + flat = True, + wipe_dist_dir = False, + allow_duplicate_filenames = False, + mode_overrides = {"**/*": "644"}, + log = "info", + ) diff --git a/qcom/opensource/dataipa/drivers/LICENSE b/qcom/opensource/dataipa/drivers/LICENSE new file mode 100644 index 0000000000..ecbc059373 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/LICENSE @@ -0,0 +1,339 @@ + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. By contrast, the GNU General Public +License is intended to guarantee your freedom to share and change free +software--to make sure the software is free for all its users. This +General Public License applies to most of the Free Software +Foundation's software and to any other program whose authors commit to +using it. (Some other Free Software Foundation software is covered by +the GNU Lesser General Public License instead.) You can apply it to +your programs, too. + + When we speak of free software, we are referring to freedom, not +price. Our General Public Licenses are designed to make sure that you +have the freedom to distribute copies of free software (and charge for +this service if you wish), that you receive source code or can get it +if you want it, that you can change the software or use pieces of it +in new free programs; and that you know you can do these things. + + To protect your rights, we need to make restrictions that forbid +anyone to deny you these rights or to ask you to surrender the rights. +These restrictions translate to certain responsibilities for you if you +distribute copies of the software, or if you modify it. + + For example, if you distribute copies of such a program, whether +gratis or for a fee, you must give the recipients all the rights that +you have. You must make sure that they, too, receive or can get the +source code. And you must show them these terms so they know their +rights. + + We protect your rights with two steps: (1) copyright the software, and +(2) offer you this license which gives you legal permission to copy, +distribute and/or modify the software. + + Also, for each author's protection and ours, we want to make certain +that everyone understands that there is no warranty for this free +software. If the software is modified by someone else and passed on, we +want its recipients to know that what they have is not the original, so +that any problems introduced by others will not reflect on the original +authors' reputations. + + Finally, any free program is threatened constantly by software +patents. We wish to avoid the danger that redistributors of a free +program will individually obtain patent licenses, in effect making the +program proprietary. To prevent this, we have made it clear that any +patent must be licensed for everyone's free use or not licensed at all. + + The precise terms and conditions for copying, distribution and +modification follow. + + GNU GENERAL PUBLIC LICENSE + TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION + + 0. This License applies to any program or other work which contains +a notice placed by the copyright holder saying it may be distributed +under the terms of this General Public License. The "Program", below, +refers to any such program or work, and a "work based on the Program" +means either the Program or any derivative work under copyright law: +that is to say, a work containing the Program or a portion of it, +either verbatim or with modifications and/or translated into another +language. (Hereinafter, translation is included without limitation in +the term "modification".) Each licensee is addressed as "you". + +Activities other than copying, distribution and modification are not +covered by this License; they are outside its scope. The act of +running the Program is not restricted, and the output from the Program +is covered only if its contents constitute a work based on the +Program (independent of having been made by running the Program). +Whether that is true depends on what the Program does. + + 1. You may copy and distribute verbatim copies of the Program's +source code as you receive it, in any medium, provided that you +conspicuously and appropriately publish on each copy an appropriate +copyright notice and disclaimer of warranty; keep intact all the +notices that refer to this License and to the absence of any warranty; +and give any other recipients of the Program a copy of this License +along with the Program. + +You may charge a fee for the physical act of transferring a copy, and +you may at your option offer warranty protection in exchange for a fee. + + 2. You may modify your copy or copies of the Program or any portion +of it, thus forming a work based on the Program, and copy and +distribute such modifications or work under the terms of Section 1 +above, provided that you also meet all of these conditions: + + a) You must cause the modified files to carry prominent notices + stating that you changed the files and the date of any change. + + b) You must cause any work that you distribute or publish, that in + whole or in part contains or is derived from the Program or any + part thereof, to be licensed as a whole at no charge to all third + parties under the terms of this License. + + c) If the modified program normally reads commands interactively + when run, you must cause it, when started running for such + interactive use in the most ordinary way, to print or display an + announcement including an appropriate copyright notice and a + notice that there is no warranty (or else, saying that you provide + a warranty) and that users may redistribute the program under + these conditions, and telling the user how to view a copy of this + License. (Exception: if the Program itself is interactive but + does not normally print such an announcement, your work based on + the Program is not required to print an announcement.) + +These requirements apply to the modified work as a whole. If +identifiable sections of that work are not derived from the Program, +and can be reasonably considered independent and separate works in +themselves, then this License, and its terms, do not apply to those +sections when you distribute them as separate works. But when you +distribute the same sections as part of a whole which is a work based +on the Program, the distribution of the whole must be on the terms of +this License, whose permissions for other licensees extend to the +entire whole, and thus to each and every part regardless of who wrote it. + +Thus, it is not the intent of this section to claim rights or contest +your rights to work written entirely by you; rather, the intent is to +exercise the right to control the distribution of derivative or +collective works based on the Program. + +In addition, mere aggregation of another work not based on the Program +with the Program (or with a work based on the Program) on a volume of +a storage or distribution medium does not bring the other work under +the scope of this License. + + 3. You may copy and distribute the Program (or a work based on it, +under Section 2) in object code or executable form under the terms of +Sections 1 and 2 above provided that you also do one of the following: + + a) Accompany it with the complete corresponding machine-readable + source code, which must be distributed under the terms of Sections + 1 and 2 above on a medium customarily used for software interchange; or, + + b) Accompany it with a written offer, valid for at least three + years, to give any third party, for a charge no more than your + cost of physically performing source distribution, a complete + machine-readable copy of the corresponding source code, to be + distributed under the terms of Sections 1 and 2 above on a medium + customarily used for software interchange; or, + + c) Accompany it with the information you received as to the offer + to distribute corresponding source code. (This alternative is + allowed only for noncommercial distribution and only if you + received the program in object code or executable form with such + an offer, in accord with Subsection b above.) + +The source code for a work means the preferred form of the work for +making modifications to it. For an executable work, complete source +code means all the source code for all modules it contains, plus any +associated interface definition files, plus the scripts used to +control compilation and installation of the executable. However, as a +special exception, the source code distributed need not include +anything that is normally distributed (in either source or binary +form) with the major components (compiler, kernel, and so on) of the +operating system on which the executable runs, unless that component +itself accompanies the executable. + +If distribution of executable or object code is made by offering +access to copy from a designated place, then offering equivalent +access to copy the source code from the same place counts as +distribution of the source code, even though third parties are not +compelled to copy the source along with the object code. + + 4. You may not copy, modify, sublicense, or distribute the Program +except as expressly provided under this License. Any attempt +otherwise to copy, modify, sublicense or distribute the Program is +void, and will automatically terminate your rights under this License. +However, parties who have received copies, or rights, from you under +this License will not have their licenses terminated so long as such +parties remain in full compliance. + + 5. You are not required to accept this License, since you have not +signed it. However, nothing else grants you permission to modify or +distribute the Program or its derivative works. These actions are +prohibited by law if you do not accept this License. Therefore, by +modifying or distributing the Program (or any work based on the +Program), you indicate your acceptance of this License to do so, and +all its terms and conditions for copying, distributing or modifying +the Program or works based on it. + + 6. Each time you redistribute the Program (or any work based on the +Program), the recipient automatically receives a license from the +original licensor to copy, distribute or modify the Program subject to +these terms and conditions. You may not impose any further +restrictions on the recipients' exercise of the rights granted herein. +You are not responsible for enforcing compliance by third parties to +this License. + + 7. If, as a consequence of a court judgment or allegation of patent +infringement or for any other reason (not limited to patent issues), +conditions are imposed on you (whether by court order, agreement or +otherwise) that contradict the conditions of this License, they do not +excuse you from the conditions of this License. If you cannot +distribute so as to satisfy simultaneously your obligations under this +License and any other pertinent obligations, then as a consequence you +may not distribute the Program at all. For example, if a patent +license would not permit royalty-free redistribution of the Program by +all those who receive copies directly or indirectly through you, then +the only way you could satisfy both it and this License would be to +refrain entirely from distribution of the Program. + +If any portion of this section is held invalid or unenforceable under +any particular circumstance, the balance of the section is intended to +apply and the section as a whole is intended to apply in other +circumstances. + +It is not the purpose of this section to induce you to infringe any +patents or other property right claims or to contest validity of any +such claims; this section has the sole purpose of protecting the +integrity of the free software distribution system, which is +implemented by public license practices. Many people have made +generous contributions to the wide range of software distributed +through that system in reliance on consistent application of that +system; it is up to the author/donor to decide if he or she is willing +to distribute software through any other system and a licensee cannot +impose that choice. + +This section is intended to make thoroughly clear what is believed to +be a consequence of the rest of this License. + + 8. If the distribution and/or use of the Program is restricted in +certain countries either by patents or by copyrighted interfaces, the +original copyright holder who places the Program under this License +may add an explicit geographical distribution limitation excluding +those countries, so that distribution is permitted only in or among +countries not thus excluded. In such case, this License incorporates +the limitation as if written in the body of this License. + + 9. The Free Software Foundation may publish revised and/or new versions +of the General Public License from time to time. Such new versions will +be similar in spirit to the present version, but may differ in detail to +address new problems or concerns. + +Each version is given a distinguishing version number. If the Program +specifies a version number of this License which applies to it and "any +later version", you have the option of following the terms and conditions +either of that version or of any later version published by the Free +Software Foundation. If the Program does not specify a version number of +this License, you may choose any version ever published by the Free Software +Foundation. + + 10. If you wish to incorporate parts of the Program into other free +programs whose distribution conditions are different, write to the author +to ask for permission. For software which is copyrighted by the Free +Software Foundation, write to the Free Software Foundation; we sometimes +make exceptions for this. Our decision will be guided by the two goals +of preserving the free status of all derivatives of our free software and +of promoting the sharing and reuse of software generally. + + NO WARRANTY + + 11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY +FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN +OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES +PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED +OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS +TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE +PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, +REPAIR OR CORRECTION. + + 12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING +WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR +REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, +INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING +OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED +TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY +YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER +PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE +POSSIBILITY OF SUCH DAMAGES. + + END OF TERMS AND CONDITIONS + + How to Apply These Terms to Your New Programs + + If you develop a new program, and you want it to be of the greatest +possible use to the public, the best way to achieve this is to make it +free software which everyone can redistribute and change under these terms. + + To do so, attach the following notices to the program. It is safest +to attach them to the start of each source file to most effectively +convey the exclusion of warranty; and each file should have at least +the "copyright" line and a pointer to where the full notice is found. + + + Copyright (C) + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + +Also add information on how to contact you by electronic and paper mail. + +If the program is interactive, make it output a short notice like this +when it starts in an interactive mode: + + Gnomovision version 69, Copyright (C) year name of author + Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, the commands you use may +be called something other than `show w' and `show c'; they could even be +mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the program, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the program + `Gnomovision' (which makes passes at compilers) written by James Hacker. + + , 1 April 1989 + Ty Coon, President of Vice + +This General Public License does not permit incorporating your program into +proprietary programs. If your program is a subroutine library, you may +consider it more useful to permit linking proprietary applications with the +library. If this is what you want to do, use the GNU Lesser General +Public License instead of this License. \ No newline at end of file diff --git a/qcom/opensource/dataipa/drivers/NOTICE b/qcom/opensource/dataipa/drivers/NOTICE new file mode 100644 index 0000000000..5a30e9af65 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/NOTICE @@ -0,0 +1,10 @@ +Copyright (c) 2021 The Linux Foundation. All rights reserved. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License version 2 and +only version 2 as published by the Free Software Foundation. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. \ No newline at end of file diff --git a/qcom/opensource/dataipa/drivers/platform/msm/Android.bp b/qcom/opensource/dataipa/drivers/platform/msm/Android.bp new file mode 100644 index 0000000000..d6f2cc0eab --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/Android.bp @@ -0,0 +1,72 @@ +headers_src = [ + "include/uapi/linux/*.h", +] + +test_headers_src = [ + "ipa/ipa_test_module/ipa_test_module.h", +] + +ipa_headers_out = [ + "linux/msm_ipa.h", + "linux/ipa_qmi_service_v01.h", + "linux/rmnet_ipa_fd_ioctl.h", +] + +ipa_test_headers_out = [ + "ipa_test_module.h", +] + +ipa_kernel_headers_verbose = "--verbose " +ipa_test_kernel_headers_verbose = "--verbose " + +genrule { + name: "qti_generate_ipa_kernel_headers", + tools: ["headers_install.sh", + "unifdef" + ], + tool_files: [ + "ipa_kernel_headers.py", + ], + srcs: headers_src, + cmd: "python3 -u $(location ipa_kernel_headers.py) " + + ipa_kernel_headers_verbose + + "--gen_dir $(genDir) " + + "--ipa_include_uapi $(locations include/uapi/linux/*.h) " + + "--unifdef $(location unifdef) " + + "--headers_install $(location headers_install.sh)", + out: ipa_headers_out, +} + +genrule { + name: "qti_generate_ipa_test_kernel_headers", + tools: ["headers_install.sh", + "unifdef" + ], + tool_files: [ + "ipa_test_kernel_headers.py", + ], + srcs: test_headers_src, + cmd: "python3 -u $(location ipa_test_kernel_headers.py) " + + ipa_test_kernel_headers_verbose + + "--gen_dir $(genDir) " + + "--ipa_test_include_uapi $(locations ipa/ipa_test_module/ipa_test_module.h) " + + "--unifdef $(location unifdef) " + + "--headers_install $(location headers_install.sh)", + out: ipa_test_headers_out, +} + +cc_library_headers { + name: "qti_ipa_kernel_headers", + generated_headers: ["qti_generate_ipa_kernel_headers"], + export_generated_headers: ["qti_generate_ipa_kernel_headers"], + vendor: true, + recovery_available: true +} + +cc_library_headers { + name: "qti_ipa_test_kernel_headers", + generated_headers: ["qti_generate_ipa_test_kernel_headers"], + export_generated_headers: ["qti_generate_ipa_test_kernel_headers"], + vendor: true, + recovery_available: true +} diff --git a/qcom/opensource/dataipa/drivers/platform/msm/Android.mk b/qcom/opensource/dataipa/drivers/platform/msm/Android.mk new file mode 100644 index 0000000000..90f791918e --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/Android.mk @@ -0,0 +1,74 @@ +ifeq ($(TARGET_DATAIPA_DLKM_ENABLE), true) +ifneq ($(TARGET_BOARD_PLATFORM),qssi) + +GSI_DLKM_PLATFORMS_LIST := taro kalama bengal monaco pineapple blair holi cliffs pitti volcano niobe + +#Enabling BAZEL +LOCAL_MODULE_DDK_BUILD := true +LOCAL_MODULE_KO_DIRS := gsi/gsim.ko +LOCAL_MODULE_KO_DIRS += ipa/ipam.ko +LOCAL_MODULE_KO_DIRS += ipa/ipanetm.ko +ifeq ($(CONFIG_LOCALVERSION), "-gki-consolidate") +LOCAL_MODULE_KO_DIRS += ipa/ipatestm.ko +endif + +ifeq ($(call is-board-platform-in-list, $(GSI_DLKM_PLATFORMS_LIST)),true) +#Make file to create GSI DLKM + +BOARD_COMMON_DIR ?= device/qcom/common +DLKM_DIR := $(TOP)/$(BOARD_COMMON_DIR)/dlkm +LOCAL_PATH := $(call my-dir) +include $(CLEAR_VARS) + +LOCAL_CFLAGS := -Wno-macro-redefined -Wno-unused-function -Wall -Werror +LOCAL_CLANG :=true + + +KBUILD_OPTIONS += MODNAME=gsim +LOCAL_SRC_FILES := $(wildcard $(LOCAL_PATH)/**/*) $(wildcard $(LOCAL_PATH)/*) +LOCAL_MODULE := gsim.ko +LOCAL_MODULE_KBUILD_NAME := gsi/gsim.ko +LOCAL_MODULE_DEBUG_ENABLE := true +LOCAL_MODULE_PATH := $(KERNEL_MODULES_OUT) +$(warning $(DLKM_DIR)) +include $(DLKM_DIR)/Build_external_kernelmodule.mk + + +include $(CLEAR_VARS) +KBUILD_OPTIONS += MODNAME=ipam +LOCAL_SRC_FILES := $(wildcard $(LOCAL_PATH)/**/*) $(wildcard $(LOCAL_PATH)/*) +LOCAL_MODULE := ipam.ko +LOCAL_MODULE_KBUILD_NAME := ipa/ipam.ko +LOCAL_MODULE_DEBUG_ENABLE := true +LOCAL_EXPORT_KO_INCLUDE_DIRS := $(LOCAL_PATH)/include +LOCAL_EXPORT_KO_INCLUDE_DIRS += $(LOCAL_PATH)/include/uapi +LOCAL_MODULE_PATH := $(KERNEL_MODULES_OUT) +$(warning $(DLKM_DIR)) +include $(DLKM_DIR)/Build_external_kernelmodule.mk + +include $(CLEAR_VARS) +KBUILD_OPTIONS += MODNAME=ipanetm +LOCAL_SRC_FILES := $(wildcard $(LOCAL_PATH)/**/*) $(wildcard $(LOCAL_PATH)/*) +LOCAL_MODULE := ipanetm.ko +LOCAL_MODULE_KBUILD_NAME := ipa/ipanetm.ko +LOCAL_MODULE_DEBUG_ENABLE := true +LOCAL_MODULE_PATH := $(KERNEL_MODULES_OUT) +$(warning $(DLKM_DIR)) +include $(DLKM_DIR)/Build_external_kernelmodule.mk + +ifeq ($(CONFIG_LOCALVERSION), "-gki-consolidate") +include $(CLEAR_VARS) +KBUILD_OPTIONS += MODNAME=ipatestm +LOCAL_SRC_FILES := $(wildcard $(LOCAL_PATH)/**/*) $(wildcard $(LOCAL_PATH)/*) +LOCAL_MODULE := ipatestm.ko +LOCAL_MODULE_KBUILD_NAME := ipa/ipatestm.ko +LOCAL_MODULE_DEBUG_ENABLE := true +LOCAL_HEADER_LIBRARIES := ipa_test_kernel_headers +LOCAL_MODULE_PATH := $(KERNEL_MODULES_OUT) +$(warning $(DLKM_DIR)) +include $(DLKM_DIR)/Build_external_kernelmodule.mk +endif + +endif #End of Check for target +endif #End of Check for qssi target +endif #DLKM diff --git a/qcom/opensource/dataipa/drivers/platform/msm/Kbuild b/qcom/opensource/dataipa/drivers/platform/msm/Kbuild new file mode 100644 index 0000000000..bcb5a196e6 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/Kbuild @@ -0,0 +1,100 @@ +# SPDX-License-Identifier: GPL-2.0-only +DATAIPADRVTOP = $(srctree)/techpack/dataipa/drivers/platform/msm + +#MSMs - GKI +ifeq ($(CONFIG_ARCH_LAHAINA), y) +LINUXINCLUDE += -include $(srctree)/techpack/dataipa/config/dataipa.h +ifeq ($(CONFIG_QGKI),y) +include $(srctree)/techpack/dataipa/config/dataipa_QGKI.conf +ifeq ($(CONFIG_LOCALVERSION), "-qgki-debug") +include $(srctree)/techpack/dataipa/config/dataipa_debug.conf +LINUXINCLUDE += -include $(srctree)/techpack/dataipa/config/dataipa_debug.h +endif +else +include $(srctree)/techpack/dataipa/config/dataipa_GKI.conf +endif +endif + +#MSM - Vendor SI +ifeq ($(filter $(CONFIG_ARCH_WAIPIO) $(CONFIG_ARCH_KALAMA) $(CONFIG_ARCH_PINEAPPLE) $(CONFIG_ARCH_CLIFFS) $(CONFIG_ARCH_PITTI) $(CONFIG_ARCH_VOLCANO), y),y) +DATAIPADRVTOP = $(srctree)/../../vendor/qcom/opensource/dataipa/drivers/platform/msm +LINUXINCLUDE += -include $(srctree)/../../vendor/qcom/opensource/dataipa/config/dataipa_vendor.h +include $(srctree)/../../vendor/qcom/opensource/dataipa/config/dataipa_GKI.conf +ifeq ($(CONFIG_LOCALVERSION), "-gki-consolidate") +include $(srctree)/../../vendor/qcom/opensource/dataipa/config/dataipa_GKI_consolidate.conf +LINUXINCLUDE += -include $(srctree)/../../vendor/qcom/opensource/dataipa/config/dataipa_debug.h +endif +endif + +ifeq ($(filter $(CONFIG_ARCH_KHAJE) $(CONFIG_ARCH_BLAIR) $(CONFIG_ARCH_HOLI) $(CONFIG_ARCH_MONACO), y), y) +DATAIPADRVTOP = $(srctree)/../../vendor/qcom/opensource/dataipa/drivers/platform/msm +LINUXINCLUDE += -include $(srctree)/../../vendor/qcom/opensource/dataipa/config/dataipa_vendor_ipav4.h +include $(srctree)/../../vendor/qcom/opensource/dataipa/config/dataipa_GKI_ipav4.conf +ifeq ($(CONFIG_LOCALVERSION), "-gki-consolidate") +include $(srctree)/../../vendor/qcom/opensource/dataipa/config/dataipa_GKI_consolidate.conf +LINUXINCLUDE += -include $(srctree)/../../vendor/qcom/opensource/dataipa/config/dataipa_debug.h +endif +endif + +#MDMs +ifeq ($(CONFIG_ARCH_SDXLEMUR), y) +LINUXINCLUDE += -include $(srctree)/techpack/dataipa/config/dataipa.h +include $(srctree)/techpack/dataipa/config/dataipa_QGKI.conf +ifneq ($(CONFIG_LOCALVERSION), "-perf") +include $(srctree)/techpack/dataipa/config/dataipa_debug.conf +LINUXINCLUDE += -include $(srctree)/techpack/dataipa/config/dataipa_debug.h +endif +endif + +ifeq ($(CONFIG_ARCH_SDXNIGHTJAR), y) +LINUXINCLUDE += -include $(srctree)/techpack/dataipa/config/sdx12dataipa.h +include $(srctree)/techpack/dataipa/config/sdx12dataipa_QGKI.conf +ifneq ($(CONFIG_LOCALVERSION), "-perf") +include $(srctree)/techpack/dataipa/config/dataipa_debug.conf +LINUXINCLUDE += -include $(srctree)/techpack/dataipa/config/dataipa_debug.h +endif +endif + +ifeq ($(CONFIG_ARCH_SCUBA), y) +LINUXINCLUDE += -include $(srctree)/techpack/dataipa/config/sa410mdataipa.h +include $(srctree)/techpack/dataipa/config/sa410mdataipa_QGKI.conf +ifneq ($(CONFIG_LOCALVERSION), "-perf") +include $(srctree)/techpack/dataipa/config/dataipa_debug.conf +LINUXINCLUDE += -include $(srctree)/techpack/dataipa/config/dataipa_debug.h +endif +endif + +ifneq (,$(filter $(CONFIG_IPA3) $(CONFIG_GSI),y m)) +LINUXINCLUDE += -I$(DATAIPADRVTOP)/include +LINUXINCLUDE += -I$(DATAIPADRVTOP)/include/linux +LINUXINCLUDE += -I$(DATAIPADRVTOP)/include/uapi +LINUXINCLUDE += -I$(DATAIPADRVTOP)/gsi +LINUXINCLUDE += -I$(DATAIPADRVTOP)/gsi/gsihal +LINUXINCLUDE += -I$(DATAIPADRVTOP)/ipa +LINUXINCLUDE += -I$(DATAIPADRVTOP)/ipa/ipa_v3 +LINUXINCLUDE += -I$(DATAIPADRVTOP)/ipa/ipa_v3/ipahal +LINUXINCLUDE += -I$(DATAIPADRVTOP)/ipa/ipa_clients +ifneq (,$(filter $(CONFIG_IPA_KERNEL_TESTS_MODULE),y m)) +LINUXINCLUDE += -I$(DATAIPADRVTOP)/ipa/ipa_test_module +endif +endif + +ifneq (,$(filter $(CONFIG_IPA3_REGDUMP),y m)) +LINUXINCLUDE += -I$(DATAIPADRVTOP)/ipa/ipa_v3/dump +endif + +ifneq (,$(filter $(CONFIG_IPA3_REGDUMP_IPA_4_5),y m)) +LINUXINCLUDE += -I$(DATAIPADRVTOP)/ipa/ipa_v3/dump/ipa4.5 +endif + +ifneq (,$(filter $(CONFIG_IPA3_REGDUMP_IPA_5_0),y m)) +LINUXINCLUDE += -I$(DATAIPADRVTOP)/ipa/ipa_v3/dump/ipa5.0 +endif + +ifneq (,$(filter $(CONFIG_IPA3_REGDUMP_IPA_5_5),y m)) +LINUXINCLUDE += -I$(DATAIPADRVTOP)/ipa/ipa_v3/dump/ipa5.5 +endif + + +obj-$(CONFIG_GSI) += gsi/ +obj-$(CONFIG_IPA3) += ipa/ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/Makefile b/qcom/opensource/dataipa/drivers/platform/msm/Makefile new file mode 100644 index 0000000000..ef1cc3333a --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/Makefile @@ -0,0 +1,13 @@ +ifeq ($(KP_MODULE_ROOT),) +KP_MODULE_ROOT=$(KERNEL_SRC)/$(M) +endif + +KBUILD_OPTIONS+=KBUILD_DTC_INCLUDE=$(KP_MODULE_ROOT) + +all: modules # dtbs + +clean: + $(MAKE) -C $(KERNEL_SRC) M=$(M) clean + +%: + $(MAKE) -C $(KERNEL_SRC) M=$(M) $@ $(KBUILD_OPTIONS) diff --git a/qcom/opensource/dataipa/drivers/platform/msm/gsi/Kbuild b/qcom/opensource/dataipa/drivers/platform/msm/gsi/Kbuild new file mode 100644 index 0000000000..e1a7a599ab --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/gsi/Kbuild @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-only + +obj-$(CONFIG_GSI) += gsim.o + +gsim-objs := gsi.o gsihal/gsihal.o gsihal/gsihal_reg.o + +gsim-$(CONFIG_DEBUG_FS) += gsi_dbg.o + +gsim-$(CONFIG_IPA_EMULATION) += gsi_emulation.o diff --git a/qcom/opensource/dataipa/drivers/platform/msm/gsi/gsi.c b/qcom/opensource/dataipa/drivers/platform/msm/gsi/gsi.c new file mode 100644 index 0000000000..2c475b23d6 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/gsi/gsi.c @@ -0,0 +1,5973 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "gsi.h" +#include "gsi_emulation.h" +#include "gsihal.h" + +#include +#include +#include +#include +#include +#include +#include +#include + +#define CREATE_TRACE_POINTS +#include "gsi_trace.h" + +#define GSI_CMD_TIMEOUT (5*HZ) +#define GSI_FC_CMD_TIMEOUT (2*GSI_CMD_TIMEOUT) +#define GSI_START_CMD_TIMEOUT_MS 1000 +#define GSI_CMD_POLL_CNT 5 +#define GSI_STOP_CMD_TIMEOUT_MS 200 +#define GSI_MAX_CH_LOW_WEIGHT 15 +#define GSI_IRQ_STORM_THR 5 +#define GSI_FC_MAX_TIMEOUT 5 + +#define GSI_STOP_CMD_POLL_CNT 4 +#define GSI_STOP_IN_PROC_CMD_POLL_CNT 2 + +#define GSI_RESET_WA_MIN_SLEEP 1000 +#define GSI_RESET_WA_MAX_SLEEP 2000 +#define GSI_CHNL_STATE_MAX_RETRYCNT 10 + +#define GSI_STTS_REG_BITS 32 +#define GSI_MSB_MASK 0xFFFFFFFF00000000ULL +#define GSI_LSB_MASK 0x00000000FFFFFFFFULL +#define GSI_MSB(num) ((u32)((num & GSI_MSB_MASK) >> 32)) +#define GSI_LSB(num) ((u32)(num & GSI_LSB_MASK)) + +#define GSI_FC_NUM_WORDS_PER_CHNL_SHRAM (20) +#define GSI_FC_STATE_INDEX_SHRAM (7) +#define GSI_FC_PENDING_MASK (0x00080000) + +#define GSI_NTN3_PENDING_DB_AFTER_RB_MASK 18 +#define GSI_NTN3_PENDING_DB_AFTER_RB_SHIFT 1 +/* FOR_SEQ_HIGH channel scratch: (((8 * (pipe_id * ctx_size + offset_lines)) + 4) / 4) */ +#define GSI_GSI_SHRAM_n_EP_FOR_SEQ_HIGH_N_GET(ep_id) (((8 * (ep_id * 10 + 9)) + 4) / 4) + +#ifndef CONFIG_DEBUG_FS +void gsi_debugfs_init(void) +{ +} +#endif + +static const struct of_device_id msm_gsi_match[] = { + { .compatible = "qcom,msm_gsi", }, + { }, +}; + + +#if defined(CONFIG_IPA_EMULATION) +static bool running_emulation = true; +#else +static bool running_emulation; +#endif + +struct gsi_ctx *gsi_ctx; + +static union __packed gsi_channel_scratch __gsi_update_mhi_channel_scratch( + unsigned long chan_hdl, struct __packed gsi_mhi_channel_scratch mscr); + +static void __gsi_config_type_irq(int ee, uint32_t mask, uint32_t val) +{ + uint32_t curr; + + curr = gsihal_read_reg_n(GSI_EE_n_CNTXT_TYPE_IRQ_MSK, ee); + + gsihal_write_reg_n(GSI_EE_n_CNTXT_TYPE_IRQ_MSK, ee, + (curr & ~mask) | (val & mask)); +} + +static void __gsi_config_ch_irq(int ee, uint32_t mask, uint32_t val) +{ + uint32_t curr; + + curr = gsihal_read_reg_n(GSI_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK, ee); + + gsihal_write_reg_n(GSI_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK, ee, + (curr & ~mask) | (val & mask)); +} + +static void __gsi_config_all_ch_irq(int ee, uint32_t mask, uint32_t val) +{ + uint32_t curr, k, max_k; + + max_k = gsihal_get_bit_map_array_size(); + for (k = 0; k < max_k; k++) + { + curr = gsihal_read_reg_nk(GSI_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k, ee, k); + + gsihal_write_reg_nk(GSI_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k, ee, k, + (curr & ~mask) | (val & mask)); + } +} + +static void __gsi_config_evt_irq(int ee, uint32_t mask, uint32_t val) +{ + uint32_t curr; + + curr = gsihal_read_reg_n(GSI_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK, ee); + + gsihal_write_reg_n(GSI_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK, ee, + (curr & ~mask) | (val & mask)); +} + +static void __gsi_config_all_evt_irq(int ee, uint32_t mask, uint32_t val) +{ + uint32_t curr, k, max_k; + + max_k = gsihal_get_bit_map_array_size(); + for (k = 0; k < max_k; k++) + { + curr = gsihal_read_reg_nk(GSI_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k, ee, k); + + gsihal_write_reg_nk(GSI_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k, ee, k, + (curr & ~mask) | (val & mask)); + } +} + +static void __gsi_config_ieob_irq(int ee, uint32_t mask, uint32_t val) +{ + uint32_t curr; + + curr = gsihal_read_reg_n(GSI_EE_n_CNTXT_SRC_IEOB_IRQ_MSK, ee); + + gsihal_write_reg_n(GSI_EE_n_CNTXT_SRC_IEOB_IRQ_MSK, ee, + (curr & ~mask) | (val & mask)); + + GSIDBG("current IEO_IRQ_MSK: 0x%x, change to: 0x%x\n", + curr, ((curr & ~mask) | (val & mask))); +} + +static void __gsi_config_all_ieob_irq(int ee, uint32_t mask, uint32_t val) +{ + uint32_t curr, k, max_k; + + max_k = gsihal_get_bit_map_array_size(); + for (k = 0; k < max_k; k++) + { + curr = gsihal_read_reg_nk(GSI_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k, ee, k); + + gsihal_write_reg_nk(GSI_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k, ee, k, + (curr & ~mask) | (val & mask)); + GSIDBG("current IEO_IRQ_MSK: 0x%x, change to: 0x%x\n", + curr, ((curr & ~mask) | (val & mask))); + } +} + +static void __gsi_config_ieob_irq_k(int ee, uint32_t k, uint32_t mask, uint32_t val) +{ + uint32_t curr; + + curr = gsihal_read_reg_nk(GSI_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k, ee, k); + + gsihal_write_reg_nk(GSI_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k, ee, k, + (curr & ~mask) | (val & mask)); + GSIDBG("current IEO_IRQ_MSK: 0x%x, change to: 0x%x\n", + curr, ((curr & ~mask) | (val & mask))); +} + +static void __gsi_config_glob_irq(int ee, uint32_t mask, uint32_t val) +{ + uint32_t curr; + + curr = gsihal_read_reg_n(GSI_EE_n_CNTXT_GLOB_IRQ_EN, ee); + + gsihal_write_reg_n(GSI_EE_n_CNTXT_GLOB_IRQ_EN, ee, + (curr & ~mask) | (val & mask)); +} + +static void __gsi_config_gen_irq(int ee, uint32_t mask, uint32_t val) +{ + uint32_t curr; + + curr = gsihal_read_reg_n(GSI_EE_n_CNTXT_GSI_IRQ_EN, ee); + + gsihal_write_reg_n(GSI_EE_n_CNTXT_GSI_IRQ_EN, ee, + (curr & ~mask) | (val & mask)); +} + +static void gsi_channel_state_change_wait(unsigned long chan_hdl, + struct gsi_chan_ctx *ctx, + uint32_t tm, enum gsi_ch_cmd_opcode op) +{ + int poll_cnt; + int gsi_pending_intr; + int res; + struct gsihal_reg_ctx_type_irq type; + struct gsihal_reg_ch_k_cntxt_0 ch_k_cntxt_0; + int ee = gsi_ctx->per.ee; + enum gsi_chan_state curr_state = GSI_CHAN_STATE_NOT_ALLOCATED; + int stop_in_proc_retry = 0; + int stop_retry = 0; + + /* + * Start polling the GSI channel for + * duration = tm * GSI_CMD_POLL_CNT. + * We need to do polling of gsi state for improving debugability + * of gsi hw state. + */ + + for (poll_cnt = 0; + poll_cnt < GSI_CMD_POLL_CNT; + poll_cnt++) { + res = wait_for_completion_timeout(&ctx->compl, + msecs_to_jiffies(tm)); + + /* Interrupt received, return */ + if (res != 0) + return; + + gsihal_read_reg_n_fields(GSI_EE_n_CNTXT_TYPE_IRQ, ee, &type); + if (gsi_ctx->per.ver >= GSI_VER_3_0) { + gsi_pending_intr = gsihal_read_reg_nk( + GSI_EE_n_CNTXT_SRC_GSI_CH_IRQ_k, + ee, gsihal_get_ch_reg_idx(chan_hdl)); + } else { + gsi_pending_intr = gsihal_read_reg_n( + GSI_EE_n_CNTXT_SRC_GSI_CH_IRQ, ee); + } + + if (gsi_ctx->per.ver == GSI_VER_1_0) { + gsihal_read_reg_nk_fields(GSI_EE_n_GSI_CH_k_CNTXT_0, + ee, chan_hdl, &ch_k_cntxt_0); + curr_state = ch_k_cntxt_0.chstate; + } + + /* Update the channel state only if interrupt was raised + * on particular channel and also checking global interrupt + * is raised for channel control. + */ + if ((type.ch_ctrl) && + (gsi_pending_intr & gsihal_get_ch_reg_mask(chan_hdl))) { + /* + * Check channel state here in case the channel is + * already started but interrupt is not yet received. + */ + + gsihal_read_reg_nk_fields(GSI_EE_n_GSI_CH_k_CNTXT_0, + ee, chan_hdl, &ch_k_cntxt_0); + curr_state = ch_k_cntxt_0.chstate; + } + + if (op == GSI_CH_START) { + if (curr_state == GSI_CHAN_STATE_STARTED || + curr_state == GSI_CHAN_STATE_FLOW_CONTROL) { + ctx->state = curr_state; + return; + } + } + + if (op == GSI_CH_STOP) { + if (curr_state == GSI_CHAN_STATE_STOPPED) + stop_retry++; + else if (curr_state == GSI_CHAN_STATE_STOP_IN_PROC) + stop_in_proc_retry++; + } + + /* if interrupt marked reg after poll count reaching to max + * keep loop to continue reach max stop proc and max stop count. + */ + if (stop_retry == 1 || stop_in_proc_retry == 1) + poll_cnt = 0; + + /* If stop channel retry reached to max count + * clear the pending interrupt, if channel already stopped. + */ + if (stop_retry == GSI_STOP_CMD_POLL_CNT) { + if (gsi_ctx->per.ver >= GSI_VER_3_0) { + gsihal_write_reg_nk(GSI_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_k, + ee, gsihal_get_ch_reg_idx(chan_hdl), + gsi_pending_intr); + } + else { + gsihal_write_reg_n(GSI_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR, + ee, + gsi_pending_intr); + } + ctx->state = curr_state; + return; + } + + /* If channel state stop in progress case no need + * to wait for long time. + */ + if (stop_in_proc_retry == GSI_STOP_IN_PROC_CMD_POLL_CNT) { + ctx->state = curr_state; + return; + } + + GSIDBG("GSI wait on chan_hld=%lu irqtyp=%u state=%u intr=%u\n", + chan_hdl, + type, + ctx->state, + gsi_pending_intr); + } + + GSIDBG("invalidating the channel state when timeout happens\n"); + ctx->state = curr_state; +} + +static void gsi_handle_ch_ctrl(int ee) +{ + uint32_t ch; + int i, k, max_k; + uint32_t ch_hdl; + struct gsihal_reg_ch_k_cntxt_0 ch_k_cntxt_0; + struct gsi_chan_ctx *ctx; + + if (gsi_ctx->per.ver >= GSI_VER_3_0) { + max_k = gsihal_get_bit_map_array_size(); + for (k = 0; k < max_k; k++) { + ch = gsihal_read_reg_nk(GSI_EE_n_CNTXT_SRC_GSI_CH_IRQ_k, ee, k); + gsihal_write_reg_nk(GSI_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_k, ee, k, ch); + + GSIDBG("ch %x\n", ch); + for (i = 0; i < GSI_STTS_REG_BITS; i++) { + if ((1 << i) & ch) { + ch_hdl = i + (GSI_STTS_REG_BITS * k); + if (ch_hdl >= gsi_ctx->max_ch || + ch_hdl >= GSI_CHAN_MAX) { + GSIERR("invalid channel %d\n", + ch_hdl); + break; + } + + ctx = &gsi_ctx->chan[ch_hdl]; + gsihal_read_reg_nk_fields(GSI_EE_n_GSI_CH_k_CNTXT_0, + ee, ch_hdl, &ch_k_cntxt_0); + ctx->state = ch_k_cntxt_0.chstate; + + GSIDBG("ch %u state updated to %u\n", + ch_hdl, ctx->state); + complete(&ctx->compl); + gsi_ctx->ch_dbg[ch_hdl].cmd_completed++; + } + } + } + } else { + ch = gsihal_read_reg_n(GSI_EE_n_CNTXT_SRC_GSI_CH_IRQ, ee); + gsihal_write_reg_n(GSI_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR, ee, ch); + + GSIDBG("ch %x\n", ch); + for (i = 0; i < GSI_STTS_REG_BITS; i++) { + if ((1 << i) & ch) { + if (i >= gsi_ctx->max_ch || + i >= GSI_CHAN_MAX) { + GSIERR("invalid channel %d\n", i); + break; + } + + ctx = &gsi_ctx->chan[i]; + gsihal_read_reg_nk_fields(GSI_EE_n_GSI_CH_k_CNTXT_0, + ee, i, &ch_k_cntxt_0); + ctx->state = ch_k_cntxt_0.chstate; + + GSIDBG("ch %u state updated to %u\n", i, + ctx->state); + complete(&ctx->compl); + gsi_ctx->ch_dbg[i].cmd_completed++; + } + } + } +} + +static void gsi_handle_ev_ctrl(int ee) +{ + uint32_t ch; + int i, k; + uint32_t evt_hdl, max_k; + struct gsi_evt_ctx *ctx; + struct gsihal_reg_ev_ch_k_cntxt_0 ev_ch_k_cntxt_0; + + if (gsi_ctx->per.ver >= GSI_VER_3_0) { + max_k = gsihal_get_bit_map_array_size(); + for (k = 0; k < max_k; k++) { + ch = gsihal_read_reg_nk(GSI_EE_n_CNTXT_SRC_EV_CH_IRQ_k, ee, k); + gsihal_write_reg_nk(GSI_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_k, ee, k, ch); + + GSIDBG("ev %x\n", ch); + for (i = 0; i < GSI_STTS_REG_BITS; i++) { + if ((1 << i) & ch) { + evt_hdl = i + (GSI_STTS_REG_BITS * k); + if (evt_hdl >= gsi_ctx->max_ev || + evt_hdl >= GSI_EVT_RING_MAX) { + GSIERR("invalid event %d\n", + evt_hdl); + break; + } + + ctx = &gsi_ctx->evtr[evt_hdl]; + gsihal_read_reg_nk_fields(GSI_EE_n_EV_CH_k_CNTXT_0, + ee, evt_hdl, &ev_ch_k_cntxt_0); + ctx->state = ev_ch_k_cntxt_0.chstate; + + GSIDBG("evt %u state updated to %u\n", + evt_hdl, ctx->state); + complete(&ctx->compl); + } + } + } + } else { + ch = gsihal_read_reg_n(GSI_EE_n_CNTXT_SRC_EV_CH_IRQ, ee); + gsihal_write_reg_n(GSI_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR, ee, ch); + + GSIDBG("ev %x\n", ch); + for (i = 0; i < GSI_STTS_REG_BITS; i++) { + if ((1 << i) & ch) { + if (i >= gsi_ctx->max_ev || + i >= GSI_EVT_RING_MAX) { + GSIERR("invalid event %d\n", i); + break; + } + + ctx = &gsi_ctx->evtr[i]; + gsihal_read_reg_nk_fields(GSI_EE_n_EV_CH_k_CNTXT_0, + ee, i, &ev_ch_k_cntxt_0); + ctx->state = ev_ch_k_cntxt_0.chstate; + + GSIDBG("evt %u state updated to %u\n", i, + ctx->state); + complete(&ctx->compl); + } + } + } +} + +static void gsi_handle_glob_err(uint32_t err) +{ + struct gsi_log_err *log; + struct gsi_chan_ctx *ch; + struct gsi_evt_ctx *ev; + struct gsi_chan_err_notify chan_notify; + struct gsi_evt_err_notify evt_notify; + struct gsi_per_notify per_notify; + enum gsi_err_type err_type; + struct gsihal_reg_ch_k_cntxt_0 ch_k_cntxt_0; + + log = (struct gsi_log_err *)&err; + GSIERR("log err_type=%u ee=%u idx=%u\n", log->err_type, log->ee, + log->virt_idx); + GSIERR("code=%u arg1=%u arg2=%u arg3=%u\n", log->code, log->arg1, + log->arg2, log->arg3); + + err_type = log->err_type; + /* + * These are errors thrown by hardware. We need + * BUG_ON() to capture the hardware state right + * when it is unexpected. + */ + switch (err_type) { + case GSI_ERR_TYPE_GLOB: + per_notify.evt_id = GSI_PER_EVT_GLOB_ERROR; + per_notify.user_data = gsi_ctx->per.user_data; + per_notify.data.err_desc = err & 0xFFFF; + gsi_ctx->per.notify_cb(&per_notify); + break; + case GSI_ERR_TYPE_CHAN: + if (WARN_ON(log->virt_idx >= gsi_ctx->max_ch)) { + GSIERR("Unexpected ch %d\n", log->virt_idx); + return; + } + + ch = &gsi_ctx->chan[log->virt_idx]; + chan_notify.chan_user_data = ch->props.chan_user_data; + chan_notify.err_desc = err & 0xFFFF; + if (log->code == GSI_INVALID_TRE_ERR) { + if (log->ee != gsi_ctx->per.ee) { + GSIERR("unexpected EE in event %d\n", log->ee); + GSI_ASSERT(); + } + + gsihal_read_reg_nk_fields(GSI_EE_n_GSI_CH_k_CNTXT_0, + gsi_ctx->per.ee, log->virt_idx, &ch_k_cntxt_0); + ch->state = ch_k_cntxt_0.chstate; + GSIDBG("ch %u state updated to %u\n", log->virt_idx, + ch->state); + ch->stats.invalid_tre_error++; + if (ch->state == GSI_CHAN_STATE_ERROR) { + GSIERR("Unexpected channel state %d\n", + ch->state); + GSI_ASSERT(); + } + chan_notify.evt_id = GSI_CHAN_INVALID_TRE_ERR; + } else if (log->code == GSI_OUT_OF_BUFFERS_ERR) { + if (log->ee != gsi_ctx->per.ee) { + GSIERR("unexpected EE in event %d\n", log->ee); + GSI_ASSERT(); + } + chan_notify.evt_id = GSI_CHAN_OUT_OF_BUFFERS_ERR; + } else if (log->code == GSI_OUT_OF_RESOURCES_ERR) { + if (log->ee != gsi_ctx->per.ee) { + GSIERR("unexpected EE in event %d\n", log->ee); + GSI_ASSERT(); + } + chan_notify.evt_id = GSI_CHAN_OUT_OF_RESOURCES_ERR; + complete(&ch->compl); + } else if (log->code == GSI_UNSUPPORTED_INTER_EE_OP_ERR) { + chan_notify.evt_id = + GSI_CHAN_UNSUPPORTED_INTER_EE_OP_ERR; + } else if (log->code == GSI_NON_ALLOCATED_EVT_ACCESS_ERR) { + if (log->ee != gsi_ctx->per.ee) { + GSIERR("unexpected EE in event %d\n", log->ee); + GSI_ASSERT(); + } + chan_notify.evt_id = + GSI_CHAN_NON_ALLOCATED_EVT_ACCESS_ERR; + } else if (log->code == GSI_HWO_1_ERR) { + if (log->ee != gsi_ctx->per.ee) { + GSIERR("unexpected EE in event %d\n", log->ee); + GSI_ASSERT(); + } + chan_notify.evt_id = GSI_CHAN_HWO_1_ERR; + } else { + GSIERR("unexpected event log code %d\n", log->code); + GSI_ASSERT(); + } + ch->props.err_cb(&chan_notify); + break; + case GSI_ERR_TYPE_EVT: + if (WARN_ON(log->virt_idx >= gsi_ctx->max_ev)) { + GSIERR("Unexpected ev %d\n", log->virt_idx); + return; + } + + ev = &gsi_ctx->evtr[log->virt_idx]; + evt_notify.user_data = ev->props.user_data; + evt_notify.err_desc = err & 0xFFFF; + if (log->code == GSI_OUT_OF_BUFFERS_ERR) { + if (log->ee != gsi_ctx->per.ee) { + GSIERR("unexpected EE in event %d\n", log->ee); + GSI_ASSERT(); + } + evt_notify.evt_id = GSI_EVT_OUT_OF_BUFFERS_ERR; + } else if (log->code == GSI_OUT_OF_RESOURCES_ERR) { + if (log->ee != gsi_ctx->per.ee) { + GSIERR("unexpected EE in event %d\n", log->ee); + GSI_ASSERT(); + } + evt_notify.evt_id = GSI_EVT_OUT_OF_RESOURCES_ERR; + complete(&ev->compl); + } else if (log->code == GSI_UNSUPPORTED_INTER_EE_OP_ERR) { + evt_notify.evt_id = GSI_EVT_UNSUPPORTED_INTER_EE_OP_ERR; + } else if (log->code == GSI_EVT_RING_EMPTY_ERR) { + if (log->ee != gsi_ctx->per.ee) { + GSIERR("unexpected EE in event %d\n", log->ee); + GSI_ASSERT(); + } + evt_notify.evt_id = GSI_EVT_EVT_RING_EMPTY_ERR; + } else { + GSIERR("unexpected event log code %d\n", log->code); + GSI_ASSERT(); + } + ev->props.err_cb(&evt_notify); + break; + } +} + +static void gsi_handle_gp_int1(void) +{ + complete(&gsi_ctx->gen_ee_cmd_compl); +} + +static void gsi_handle_glob_ee(int ee) +{ + uint32_t val; + uint32_t err; + struct gsi_per_notify notify; + uint32_t clr = ~0; + struct gsihal_reg_cntxt_glob_irq_stts cntxt_glob_irq_stts; + + val = gsihal_read_reg_n_fields(GSI_EE_n_CNTXT_GLOB_IRQ_STTS, + ee, &cntxt_glob_irq_stts); + + notify.user_data = gsi_ctx->per.user_data; + + if(cntxt_glob_irq_stts.error_int) { + err = gsihal_read_reg_n(GSI_EE_n_ERROR_LOG, ee); + if (gsi_ctx->per.ver >= GSI_VER_1_2) + gsihal_write_reg_n(GSI_EE_n_ERROR_LOG, ee, 0); + gsihal_write_reg_n(GSI_EE_n_ERROR_LOG_CLR, ee, clr); + gsi_handle_glob_err(err); + } + + if (cntxt_glob_irq_stts.gp_int1) + gsi_handle_gp_int1(); + + if (cntxt_glob_irq_stts.gp_int2) { + notify.evt_id = GSI_PER_EVT_GLOB_GP2; + gsi_ctx->per.notify_cb(¬ify); + } + + if (cntxt_glob_irq_stts.gp_int3) { + notify.evt_id = GSI_PER_EVT_GLOB_GP3; + gsi_ctx->per.notify_cb(¬ify); + } + + gsihal_write_reg_n(GSI_EE_n_CNTXT_GLOB_IRQ_CLR, ee, val); +} + +static void gsi_incr_ring_wp(struct gsi_ring_ctx *ctx) +{ + ctx->wp_local += ctx->elem_sz; + if (ctx->wp_local == ctx->end) + ctx->wp_local = ctx->base; +} + +static void gsi_incr_ring_rp(struct gsi_ring_ctx *ctx) +{ + ctx->rp_local += ctx->elem_sz; + if (ctx->rp_local == ctx->end) + ctx->rp_local = ctx->base; +} + +uint16_t gsi_find_idx_from_addr(struct gsi_ring_ctx *ctx, uint64_t addr) +{ + WARN_ON(addr < ctx->base || addr >= ctx->end); + return (uint32_t)(addr - ctx->base) / ctx->elem_sz; +} + +static uint16_t gsi_get_complete_num(struct gsi_ring_ctx *ctx, uint64_t addr1, + uint64_t addr2) +{ + uint32_t addr_diff; + + GSIDBG_LOW("gsi base addr 0x%llx end addr 0x%llx\n", + ctx->base, ctx->end); + + if (addr1 < ctx->base || addr1 >= ctx->end) { + GSIERR("address = 0x%llx not in range\n", addr1); + GSI_ASSERT(); + } + + if (addr2 < ctx->base || addr2 >= ctx->end) { + GSIERR("address = 0x%llx not in range\n", addr2); + GSI_ASSERT(); + } + + addr_diff = (uint32_t)(addr2 - addr1); + if (addr1 < addr2) + return addr_diff / ctx->elem_sz; + else + return (addr_diff + ctx->len) / ctx->elem_sz; +} + +static void gsi_process_chan(struct gsi_xfer_compl_evt *evt, + struct gsi_chan_xfer_notify *notify, bool callback) +{ + uint32_t ch_id; + struct gsi_chan_ctx *ch_ctx; + uint16_t rp_idx; + uint64_t rp; + + ch_id = evt->chid; + if (WARN_ON(ch_id >= gsi_ctx->max_ch)) { + GSIERR("Unexpected ch %d\n", ch_id); + return; + } + + ch_ctx = &gsi_ctx->chan[ch_id]; + if (WARN_ON(ch_ctx->props.prot != GSI_CHAN_PROT_GPI && + ch_ctx->props.prot != GSI_CHAN_PROT_GCI)) + return; + + if (evt->type != GSI_XFER_COMPL_TYPE_GCI) { + rp = evt->xfer_ptr; + + if (ch_ctx->ring.rp_local != rp) { + ch_ctx->stats.completed += + gsi_get_complete_num(&ch_ctx->ring, + ch_ctx->ring.rp_local, rp); + ch_ctx->ring.rp_local = rp; + } + + /* + * Increment RP local only in polling context to avoid + * sys len mismatch. + */ + if (!callback || (ch_ctx->props.dir == GSI_CHAN_DIR_TO_GSI && + !ch_ctx->props.tx_poll)) + /* the element at RP is also processed */ + gsi_incr_ring_rp(&ch_ctx->ring); + + ch_ctx->ring.rp = ch_ctx->ring.rp_local; + rp_idx = gsi_find_idx_from_addr(&ch_ctx->ring, rp); + notify->veid = GSI_VEID_DEFAULT; + } else { + rp_idx = evt->cookie; + notify->veid = evt->veid; + } + + + WARN_ON(!ch_ctx->user_data[rp_idx].valid); + notify->xfer_user_data = ch_ctx->user_data[rp_idx].p; + /* + * In suspend just before stopping the channel possible to receive + * the IEOB interrupt and xfer pointer will not be processed in this + * mode and moving channel poll mode. In resume after starting the + * channel will receive the IEOB interrupt and xfer pointer will be + * overwritten. To avoid this process all data in polling context. + */ + if (!callback || (ch_ctx->props.dir == GSI_CHAN_DIR_TO_GSI && + !ch_ctx->props.tx_poll)) { + ch_ctx->stats.completed++; + ch_ctx->user_data[rp_idx].valid = false; + } + + notify->chan_user_data = ch_ctx->props.chan_user_data; + notify->evt_id = evt->code; + notify->bytes_xfered = evt->len; + + if (callback) { + if (atomic_read(&ch_ctx->poll_mode)) { + GSIERR("Calling client callback in polling mode\n"); + WARN_ON(1); + } + ch_ctx->props.xfer_cb(notify); + } +} + +static void gsi_process_evt_re(struct gsi_evt_ctx *ctx, + struct gsi_chan_xfer_notify *notify, bool callback) +{ + struct gsi_xfer_compl_evt *evt; + struct gsi_chan_ctx *ch_ctx; + + evt = (struct gsi_xfer_compl_evt *)(ctx->ring.base_va + + ctx->ring.rp_local - ctx->ring.base); + gsi_process_chan(evt, notify, callback); + /* + * Increment RP local only in polling context to avoid + * sys len mismatch. + */ + ch_ctx = &gsi_ctx->chan[evt->chid]; + if (callback && (ch_ctx->props.dir == GSI_CHAN_DIR_FROM_GSI || + ch_ctx->props.tx_poll)) + return; + gsi_incr_ring_rp(&ctx->ring); + /* recycle this element */ + gsi_incr_ring_wp(&ctx->ring); + ctx->stats.completed++; +} + +static void gsi_ring_evt_doorbell(struct gsi_evt_ctx *ctx) +{ + uint32_t val; + + ctx->ring.wp = ctx->ring.wp_local; + val = GSI_LSB(ctx->ring.wp_local); + gsihal_write_reg_nk(GSI_EE_n_EV_CH_k_DOORBELL_0, + gsi_ctx->per.ee, ctx->id, val); +} + +void gsi_ring_evt_doorbell_polling_mode(unsigned long chan_hdl) { + struct gsi_evt_ctx *ctx; + + ctx = gsi_ctx->chan[chan_hdl].evtr; + gsi_ring_evt_doorbell(ctx); +} +EXPORT_SYMBOL(gsi_ring_evt_doorbell_polling_mode); + +static void gsi_ring_chan_doorbell(struct gsi_chan_ctx *ctx) +{ + uint32_t val; + + /* + * allocate new events for this channel first + * before submitting the new TREs. + * for TO_GSI channels the event ring doorbell is rang as part of + * interrupt handling. + */ + if (ctx->evtr && ctx->props.dir == GSI_CHAN_DIR_FROM_GSI) + gsi_ring_evt_doorbell(ctx->evtr); + ctx->ring.wp = ctx->ring.wp_local; + + val = GSI_LSB(ctx->ring.wp_local); + gsihal_write_reg_nk(GSI_EE_n_GSI_CH_k_DOORBELL_0, + gsi_ctx->per.ee, ctx->props.ch_id, val); +} + +static bool check_channel_polling(struct gsi_evt_ctx* ctx) { + /* For shared event rings both channels will be marked */ + return atomic_read(&ctx->chan[0]->poll_mode); +} + +static void gsi_handle_ieob(int ee) +{ + uint32_t ch, evt_hdl; + int i, k, max_k; + uint64_t rp; + struct gsi_evt_ctx *ctx; + struct gsi_chan_xfer_notify notify; + unsigned long flags; + unsigned long cntr; + uint32_t msk; + bool empty; + + if (gsi_ctx->per.ver >= GSI_VER_3_0) { + max_k = gsihal_get_bit_map_array_size(); + for (k = 0; k < max_k; k++) { + ch = gsihal_read_reg_nk(GSI_EE_n_CNTXT_SRC_IEOB_IRQ_k, ee, k); + msk = gsihal_read_reg_nk(GSI_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k, ee, k); + gsihal_write_reg_nk(GSI_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_k, ee, k, ch & msk); + + if (trace_gsi_qtimer_enabled()) + { + uint64_t qtimer = 0; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) + qtimer = arch_timer_read_cntpct_el0(); +#endif + trace_gsi_qtimer(qtimer, false, 0, ch, msk); + } + + for (i = 0; i < GSI_STTS_REG_BITS; i++) { + if ((1 << i) & ch & msk) { + evt_hdl = i + (GSI_STTS_REG_BITS * k); + if (evt_hdl >= gsi_ctx->max_ev || + evt_hdl >= GSI_EVT_RING_MAX) { + GSIERR("invalid event %d\n", + evt_hdl); + break; + } + ctx = &gsi_ctx->evtr[evt_hdl]; + + /* + * Don't handle MSI interrupts, only handle IEOB + * IRQs + */ + if (ctx->props.intr == GSI_INTR_MSI) + continue; + + if (ctx->props.intf != + GSI_EVT_CHTYPE_GPI_EV) { + GSIERR("Unexpected irq intf %d\n", + ctx->props.intf); + GSI_ASSERT(); + } + spin_lock_irqsave(&ctx->ring.slock, + flags); +check_again_v3_0: + cntr = 0; + empty = true; + rp = ctx->props.gsi_read_event_ring_rp( + &ctx->props, ctx->id, ee); + rp |= ctx->ring.rp & GSI_MSB_MASK; + + ctx->ring.rp = rp; + while (ctx->ring.rp_local != rp) { + ++cntr; + if (check_channel_polling(ctx)) { + cntr = 0; + break; + } + gsi_process_evt_re(ctx, ¬ify, + true); + empty = false; + } + if (!empty) + gsi_ring_evt_doorbell(ctx); + if (cntr != 0) + goto check_again_v3_0; + spin_unlock_irqrestore(&ctx->ring.slock, + flags); + } + } + } + } else { + ch = gsihal_read_reg_n(GSI_EE_n_CNTXT_SRC_IEOB_IRQ, ee); + msk = gsihal_read_reg_n(GSI_EE_n_CNTXT_SRC_IEOB_IRQ_MSK, ee); + gsihal_write_reg_n(GSI_EE_n_CNTXT_SRC_IEOB_IRQ_CLR, ee, ch & msk); + + for (i = 0; i < GSI_STTS_REG_BITS; i++) { + if ((1 << i) & ch & msk) { + if (i >= gsi_ctx->max_ev || + i >= GSI_EVT_RING_MAX) { + GSIERR("invalid event %d\n", i); + break; + } + ctx = &gsi_ctx->evtr[i]; + + /* + * Don't handle MSI interrupts, only handle IEOB + * IRQs + */ + if (ctx->props.intr == GSI_INTR_MSI) + continue; + + if (ctx->props.intf != GSI_EVT_CHTYPE_GPI_EV) { + GSIERR("Unexpected irq intf %d\n", + ctx->props.intf); + GSI_ASSERT(); + } + spin_lock_irqsave(&ctx->ring.slock, flags); + check_again: + cntr = 0; + empty = true; + rp = ctx->props.gsi_read_event_ring_rp( + &ctx->props, ctx->id, ee); + rp |= ctx->ring.rp & GSI_MSB_MASK; + + ctx->ring.rp = rp; + while (ctx->ring.rp_local != rp) { + ++cntr; + if (check_channel_polling(ctx)) { + cntr = 0; + break; + } + gsi_process_evt_re(ctx, ¬ify, true); + empty = false; + } + if (!empty) + gsi_ring_evt_doorbell(ctx); + if (cntr != 0) + goto check_again; + spin_unlock_irqrestore(&ctx->ring.slock, flags); + } + } + } +} + +static void gsi_handle_inter_ee_ch_ctrl(int ee) +{ + uint32_t ch, ch_hdl; + int i, k, max_k; + + if (gsi_ctx->per.ver >= GSI_VER_3_0) { + max_k = gsihal_get_bit_map_array_size(); + for (k = 0; k < max_k; k++) { + ch = gsihal_read_reg_nk(GSI_INTER_EE_n_SRC_GSI_CH_IRQ_k, ee, k); + gsihal_write_reg_nk(GSI_INTER_EE_n_SRC_GSI_CH_IRQ_k, ee, k, ch); + + for (i = 0; i < GSI_STTS_REG_BITS; i++) { + if ((1 << i) & ch) { + ch_hdl = i + (GSI_STTS_REG_BITS * k); + /* not currently expected */ + GSIERR("ch %u was inter-EE changed\n", ch_hdl); + } + } + } + } else { + ch = gsihal_read_reg_n(GSI_INTER_EE_n_SRC_GSI_CH_IRQ, ee); + gsihal_write_reg_n(GSI_INTER_EE_n_SRC_GSI_CH_IRQ, ee, ch); + + for (i = 0; i < GSI_STTS_REG_BITS; i++) { + if ((1 << i) & ch) { + /* not currently expected */ + GSIERR("ch %u was inter-EE changed\n", i); + } + } + } +} + +static void gsi_handle_inter_ee_ev_ctrl(int ee) +{ + uint32_t ch, evt_hdl; + int i, k, max_k; + + if (gsi_ctx->per.ver >= GSI_VER_3_0) { + max_k = gsihal_get_bit_map_array_size(); + for (k = 0; k < max_k; k++) { + ch = gsihal_read_reg_nk(GSI_INTER_EE_n_SRC_EV_CH_IRQ_k, ee, k); + gsihal_write_reg_nk(GSI_INTER_EE_n_SRC_EV_CH_IRQ_CLR_k, ee, k, ch); + + for (i = 0; i < GSI_STTS_REG_BITS; i++) { + if ((1 << i) & ch) { + evt_hdl = i + (GSI_STTS_REG_BITS * k); + /* not currently expected */ + GSIERR("evt %u was inter-EE changed\n", + evt_hdl); + } + } + } + } else { + ch = gsihal_read_reg_n(GSI_INTER_EE_n_SRC_EV_CH_IRQ, ee); + gsihal_write_reg_n(GSI_INTER_EE_n_SRC_EV_CH_IRQ_CLR, ee, ch); + + for (i = 0; i < GSI_STTS_REG_BITS; i++) { + if ((1 << i) & ch) { + /* not currently expected */ + GSIERR("evt %u was inter-EE changed\n", i); + } + } + } +} + +static void gsi_handle_general(int ee) +{ + uint32_t val; + struct gsi_per_notify notify; + struct gsihal_reg_cntxt_gsi_irq_stts gsi_irq_stts; + + val = gsihal_read_reg_n_fields(GSI_EE_n_CNTXT_GSI_IRQ_STTS, + ee, &gsi_irq_stts); + + notify.user_data = gsi_ctx->per.user_data; + + if (gsi_irq_stts.gsi_mcs_stack_ovrflow) + notify.evt_id = GSI_PER_EVT_GENERAL_MCS_STACK_OVERFLOW; + + if (gsi_irq_stts.gsi_cmd_fifo_ovrflow) + notify.evt_id = GSI_PER_EVT_GENERAL_CMD_FIFO_OVERFLOW; + + if (gsi_irq_stts.gsi_bus_error) + notify.evt_id = GSI_PER_EVT_GENERAL_BUS_ERROR; + + if (gsi_irq_stts.gsi_break_point) + notify.evt_id = GSI_PER_EVT_GENERAL_BREAK_POINT; + + if (gsi_ctx->per.notify_cb) + gsi_ctx->per.notify_cb(¬ify); + + gsihal_write_reg_n(GSI_EE_n_CNTXT_GSI_IRQ_CLR, ee, val); +} + +static void gsi_handle_irq(void) +{ + uint32_t type; + int ee = gsi_ctx->per.ee; + int index; + struct gsihal_reg_ctx_type_irq ctx_type_irq; + + while (1) { + if (!gsi_ctx->per.clk_status_cb()) + break; + type = gsihal_read_reg_n_fields(GSI_EE_n_CNTXT_TYPE_IRQ, + ee, &ctx_type_irq); + + if (!type) + break; + + GSIDBG_LOW("type 0x%x\n", type); + index = gsi_ctx->gsi_isr_cache_index; + gsi_ctx->gsi_isr_cache[index].timestamp = + sched_clock(); + gsi_ctx->gsi_isr_cache[index].qtimer = + __arch_counter_get_cntvct(); + gsi_ctx->gsi_isr_cache[index].interrupt_type = type; + gsi_ctx->gsi_isr_cache_index++; + if (gsi_ctx->gsi_isr_cache_index == GSI_ISR_CACHE_MAX) + gsi_ctx->gsi_isr_cache_index = 0; + + if(ctx_type_irq.ch_ctrl) { + gsi_handle_ch_ctrl(ee); + break; + } + + if (ctx_type_irq.ev_ctrl) { + gsi_handle_ev_ctrl(ee); + break; + } + + if (ctx_type_irq.glob_ee) + gsi_handle_glob_ee(ee); + + if (ctx_type_irq.ieob) + gsi_handle_ieob(ee); + + if (ctx_type_irq.inter_ee_ch_ctrl) + gsi_handle_inter_ee_ch_ctrl(ee); + + if (ctx_type_irq.inter_ee_ev_ctrl) + gsi_handle_inter_ee_ev_ctrl(ee); + + if (ctx_type_irq.general) + gsi_handle_general(ee); + + } +} + +static irqreturn_t gsi_isr(int irq, void *ctxt) +{ + if (gsi_ctx->per.req_clk_cb) { + bool granted = false; + + gsi_ctx->per.req_clk_cb(gsi_ctx->per.user_data, &granted); + if (granted) { + gsi_handle_irq(); + gsi_ctx->per.rel_clk_cb(gsi_ctx->per.user_data); + } + } else if (!gsi_ctx->per.clk_status_cb()) { + /* we only want to capture the gsi isr storm here */ + if (atomic_read(&gsi_ctx->num_unclock_irq) == + GSI_IRQ_STORM_THR) + gsi_ctx->per.enable_clk_bug_on(); + atomic_inc(&gsi_ctx->num_unclock_irq); + return IRQ_HANDLED; + } else { + atomic_set(&gsi_ctx->num_unclock_irq, 0); + gsi_handle_irq(); + } + return IRQ_HANDLED; +} + +static irqreturn_t gsi_msi_isr(int irq, void *ctxt) +{ + int ee = gsi_ctx->per.ee; + uint64_t rp; + struct gsi_chan_xfer_notify notify; + unsigned long flags; + unsigned long cntr; + bool empty; + uint8_t evt; + unsigned long msi; + struct gsi_evt_ctx *evt_ctxt; + + /* Determine which event channel to handle */ + for (msi = 0; msi < gsi_ctx->msi.num; msi++) { + if (gsi_ctx->msi.irq[msi] == irq) + break; + } + + evt = gsi_ctx->msi.evt[msi]; + evt_ctxt = &gsi_ctx->evtr[evt]; + + if (trace_gsi_qtimer_enabled()) { + uint64_t qtimer = 0; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) + qtimer = arch_timer_read_cntpct_el0(); +#endif + trace_gsi_qtimer(qtimer, true, evt, 0, 0); + } + + if (evt_ctxt->props.intf != GSI_EVT_CHTYPE_GPI_EV) { + GSIERR("Unexpected irq intf %d\n", + evt_ctxt->props.intf); + GSI_ASSERT(); + } + + /* Clearing IEOB irq if there are any genereated for MSI channel */ + gsihal_write_reg_nk(GSI_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_k, ee, + gsihal_get_ch_reg_idx(evt_ctxt->id), + gsihal_get_ch_reg_mask(evt_ctxt->id)); + spin_lock_irqsave(&evt_ctxt->ring.slock, flags); +check_again: + cntr = 0; + empty = true; + rp = evt_ctxt->props.gsi_read_event_ring_rp(&evt_ctxt->props, + evt_ctxt->id, ee); + rp |= evt_ctxt->ring.rp & 0xFFFFFFFF00000000; + + evt_ctxt->ring.rp = rp; + while (evt_ctxt->ring.rp_local != rp) { + ++cntr; + if (evt_ctxt->props.exclusive && + atomic_read(&evt_ctxt->chan[0]->poll_mode)) { + cntr = 0; + break; + } + gsi_process_evt_re(evt_ctxt, ¬ify, true); + empty = false; + } + if (!empty) + gsi_ring_evt_doorbell(evt_ctxt); + if (cntr != 0) + goto check_again; + spin_unlock_irqrestore(&evt_ctxt->ring.slock, flags); + return IRQ_HANDLED; +} + +static uint32_t gsi_get_max_channels(enum gsi_ver ver) +{ + uint32_t max_ch = 0; + struct gsihal_reg_hw_param hw_param; + struct gsihal_reg_hw_param2 hw_param2; + + switch (ver) { + case GSI_VER_ERR: + case GSI_VER_MAX: + GSIERR("GSI version is not supported %d\n", ver); + WARN_ON(1); + break; + case GSI_VER_1_0: + gsihal_read_reg_n_fields(GSI_EE_n_GSI_HW_PARAM, + gsi_ctx->per.ee, &hw_param); + max_ch = hw_param.gsi_ch_num; + break; + case GSI_VER_1_2: + gsihal_read_reg_n_fields(GSI_EE_n_GSI_HW_PARAM_0, + gsi_ctx->per.ee, &hw_param); + max_ch = hw_param.gsi_ch_num; + break; + default: + gsihal_read_reg_n_fields(GSI_EE_n_GSI_HW_PARAM_2, + gsi_ctx->per.ee, &hw_param2); + max_ch = hw_param2.gsi_num_ch_per_ee; + break; + } + + GSIDBG("max channels %d\n", max_ch); + + return max_ch; +} + +static uint32_t gsi_get_max_event_rings(enum gsi_ver ver) +{ + uint32_t max_ev = 0; + struct gsihal_reg_hw_param hw_param; + struct gsihal_reg_hw_param2 hw_param2; + struct gsihal_reg_hw_param4 hw_param4; + + switch (ver) { + case GSI_VER_ERR: + case GSI_VER_MAX: + GSIERR("GSI version is not supported %d\n", ver); + WARN_ON(1); + break; + case GSI_VER_1_0: + gsihal_read_reg_n_fields(GSI_EE_n_GSI_HW_PARAM, + gsi_ctx->per.ee, &hw_param); + max_ev = hw_param.gsi_ev_ch_num; + break; + case GSI_VER_1_2: + gsihal_read_reg_n_fields(GSI_EE_n_GSI_HW_PARAM_0, + gsi_ctx->per.ee, &hw_param); + max_ev = hw_param.gsi_ev_ch_num; + break; + case GSI_VER_3_0: + case GSI_VER_5_2: + case GSI_VER_5_5: + gsihal_read_reg_n_fields(GSI_EE_n_GSI_HW_PARAM_4, + gsi_ctx->per.ee, &hw_param4); + max_ev = hw_param4.gsi_num_ev_per_ee; + break; + default: + gsihal_read_reg_n_fields(GSI_EE_n_GSI_HW_PARAM_2, + gsi_ctx->per.ee, &hw_param2); + max_ev = hw_param2.gsi_num_ev_per_ee; + break; + } + + GSIDBG("max event rings %d\n", max_ev); + + return max_ev; +} +int gsi_complete_clk_grant(unsigned long dev_hdl) +{ + unsigned long flags; + + if (!gsi_ctx) { + pr_err("%s:%d gsi context not allocated\n", __func__, __LINE__); + return -GSI_STATUS_NODEV; + } + + if (!gsi_ctx->per_registered) { + GSIERR("no client registered\n"); + return -GSI_STATUS_INVALID_PARAMS; + } + + if (dev_hdl != (uintptr_t)gsi_ctx) { + GSIERR("bad params dev_hdl=0x%lx gsi_ctx=0x%pK\n", dev_hdl, + gsi_ctx); + return -GSI_STATUS_INVALID_PARAMS; + } + + spin_lock_irqsave(&gsi_ctx->slock, flags); + gsi_handle_irq(); + gsi_ctx->per.rel_clk_cb(gsi_ctx->per.user_data); + spin_unlock_irqrestore(&gsi_ctx->slock, flags); + + return GSI_STATUS_SUCCESS; +} +EXPORT_SYMBOL(gsi_complete_clk_grant); + +int gsi_map_base(phys_addr_t gsi_base_addr, u32 gsi_size, enum gsi_ver ver) +{ + if (!gsi_ctx) { + pr_err("%s:%d gsi context not allocated\n", __func__, __LINE__); + return -GSI_STATUS_NODEV; + } + + gsi_ctx->base = devm_ioremap( + gsi_ctx->dev, gsi_base_addr, gsi_size); + + if (!gsi_ctx->base) { + GSIERR("failed to map access to GSI HW\n"); + return -GSI_STATUS_RES_ALLOC_FAILURE; + } + + GSIDBG("GSI base(%pa) mapped to (%pK) with len (0x%x)\n", + &gsi_base_addr, + gsi_ctx->base, + gsi_size); + + /* initialize HAL before accessing any register */ + gsihal_init(ver, gsi_ctx->base); + + return 0; +} +EXPORT_SYMBOL(gsi_map_base); + +int gsi_unmap_base(void) +{ + if (!gsi_ctx) { + pr_err("%s:%d gsi context not allocated\n", __func__, __LINE__); + return -GSI_STATUS_NODEV; + } + + if (!gsi_ctx->base) { + GSIERR("access to GSI HW has not been mapped\n"); + return -GSI_STATUS_INVALID_PARAMS; + } + + devm_iounmap(gsi_ctx->dev, gsi_ctx->base); + + gsi_ctx->base = NULL; + + return 0; +} +EXPORT_SYMBOL(gsi_unmap_base); + +static void __gsi_msi_write_msg(struct msi_desc *desc, struct msi_msg *msg) +{ + u16 msi = 0; + + if (IS_ERR_OR_NULL(desc) || IS_ERR_OR_NULL(msg) || IS_ERR_OR_NULL(gsi_ctx)) + BUG(); + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 18, 0)) + msi = desc->msi_index; +#else + msi = desc->platform.msi_index; +#endif + + /* MSI should be valid and unallocated */ + if ((msi >= gsi_ctx->msi.num) || (test_bit(msi, gsi_ctx->msi.allocated))) + BUG(); + + /* Save the message for later use */ + memcpy(&gsi_ctx->msi.msg[msi], msg, sizeof(*msg)); + + dev_notice(gsi_ctx->dev, + "saved msi %u msg data %u addr 0x%08x%08x\n", msi, + msg->data, msg->address_hi, msg->address_lo); + + /* Single MSI control is used. So MSI address will be same. */ + if (!gsi_ctx->msi_addr_set) { + gsi_ctx->msi_addr = gsi_ctx->msi.msg[msi].address_hi; + gsi_ctx->msi_addr = (gsi_ctx->msi_addr << 32) | + gsi_ctx->msi.msg[msi].address_lo; + gsi_ctx->msi_addr_set = true; + } + + GSIDBG("saved msi %u msg data %u addr 0x%08x%08x, MSI:0x%lx\n", msi, + msg->data, msg->address_hi, msg->address_lo, gsi_ctx->msi_addr); +} + +static int __gsi_request_msi_irq(unsigned long msi) +{ + int result = 0; + + /* Ensure this is not already allocated */ + if (test_bit((int)msi, gsi_ctx->msi.allocated)) { + GSIERR("MSI %lu already allocated\n", msi); + return -GSI_STATUS_ERROR; + } + + /* Request MSI IRQ + * NOTE: During the call to devm_request_irq, the + * __gsi_msi_write_msg callback is triggered. + */ + result = devm_request_irq(gsi_ctx->dev, gsi_ctx->msi.irq[msi], + (irq_handler_t)gsi_msi_isr, IRQF_TRIGGER_NONE, + "gsi_msi", gsi_ctx); + + if (result) { + GSIERR("failed to register msi irq %u idx %lu\n", + gsi_ctx->msi.irq[msi], msi); + return -GSI_STATUS_ERROR; + } + + set_bit(msi, gsi_ctx->msi.allocated); + return result; +} + +static int __gsi_allocate_msis(void) +{ + int result = 0; +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 18, 0)) + struct msi_desc *desc = NULL; +#endif + size_t size = 0; + + /* Allocate all MSIs */ + GSIDBG("gsi_ctx->dev = %lu, gsi_ctx->msi.num = %d", gsi_ctx->dev, gsi_ctx->msi.num); + result = platform_msi_domain_alloc_irqs(gsi_ctx->dev, gsi_ctx->msi.num, + __gsi_msi_write_msg); + if (result) { + GSIERR("error allocating platform MSIs - %d\n", result); + return -GSI_STATUS_ERROR; + } + GSIDBG("MSI allocating is succesful\n"); + + /* Loop through the allocated MSIs and save the info, then + * request the IRQ. + */ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 18, 0)) + for (unsigned long msi = 0; msi < gsi_ctx->msi.num; msi++) { + /* Save IRQ */ + gsi_ctx->msi.irq[msi] = msi_get_virq(gsi_ctx->dev, msi); +#else + for_each_msi_entry(desc, gsi_ctx->dev) { + unsigned long msi = desc->platform.msi_index; + + /* Ensure a valid index */ + if (msi >= gsi_ctx->msi.num) { + GSIERR("error invalid MSI %lu\n", msi); + result = -GSI_STATUS_ERROR; + goto err_free_msis; + } + + /* Save IRQ */ + gsi_ctx->msi.irq[msi] = desc->irq; + GSIDBG("desc->irq =%d\n", desc->irq); +#endif + /* Request the IRQ */ + if (__gsi_request_msi_irq(msi)) { + GSIERR("error requesting IRQ for MSI %lu\n", + msi); + result = -GSI_STATUS_ERROR; + goto err_free_msis; + } + GSIDBG("Requesting IRQ succesful\n"); + } + + return result; + +err_free_msis: + size = sizeof(unsigned long) * BITS_TO_LONGS(gsi_ctx->msi.num); + platform_msi_domain_free_irqs(gsi_ctx->dev); + memset(gsi_ctx->msi.allocated, 0, size); + + return result; +} + +int gsi_register_device(struct gsi_per_props *props, unsigned long *dev_hdl) +{ + int res; + int result = GSI_STATUS_SUCCESS; + struct gsihal_reg_gsi_status gsi_status; + struct gsihal_reg_gsi_ee_n_cntxt_gsi_irq gen_irq; + + if (!gsi_ctx) { + pr_err("%s:%d gsi context not allocated\n", __func__, __LINE__); + return -GSI_STATUS_NODEV; + } + + if (!props || !dev_hdl) { + GSIERR("bad params props=%pK dev_hdl=%pK\n", props, dev_hdl); + return -GSI_STATUS_INVALID_PARAMS; + } + + if (props->ver <= GSI_VER_ERR || props->ver >= GSI_VER_MAX) { + GSIERR("bad params gsi_ver=%d\n", props->ver); + return -GSI_STATUS_INVALID_PARAMS; + } + + if (!props->notify_cb) { + GSIERR("notify callback must be provided\n"); + return -GSI_STATUS_INVALID_PARAMS; + } + + if (props->req_clk_cb && !props->rel_clk_cb) { + GSIERR("rel callback must be provided\n"); + return -GSI_STATUS_INVALID_PARAMS; + } + + if (gsi_ctx->per_registered) { + GSIERR("per already registered\n"); + return -GSI_STATUS_UNSUPPORTED_OP; + } + + spin_lock_init(&gsi_ctx->slock); + gsi_ctx->per = *props; + if (props->intr == GSI_INTR_IRQ) { + if (!props->irq) { + GSIERR("bad irq specified %u\n", props->irq); + return -GSI_STATUS_INVALID_PARAMS; + } + /* + * On a real UE, there are two separate interrupt + * vectors that get directed toward the GSI/IPA + * drivers. They are handled by gsi_isr() and + * (ipa_isr() or ipa3_isr()) respectively. In the + * emulation environment, this is not the case; + * instead, interrupt vectors are routed to the + * emualation hardware's interrupt controller, which + * in turn, forwards a single interrupt to the GSI/IPA + * driver. When the new interrupt vector is received, + * the driver needs to probe the interrupt + * controller's registers so see if one, the other, or + * both interrupts have occurred. Given the above, we + * now need to handle both situations, namely: the + * emulator's and the real UE. + */ + if (running_emulation) { + /* + * New scheme involving the emulator's + * interrupt controller. + */ + res = devm_request_threaded_irq( + gsi_ctx->dev, + props->irq, + /* top half handler to follow */ + emulator_hard_irq_isr, + /* threaded bottom half handler to follow */ + emulator_soft_irq_isr, + IRQF_SHARED, + "emulator_intcntrlr", + gsi_ctx); + } else { + /* + * Traditional scheme used on the real UE. + */ + res = devm_request_irq(gsi_ctx->dev, props->irq, + gsi_isr, + props->req_clk_cb ? IRQF_TRIGGER_RISING : + IRQF_TRIGGER_HIGH, + "gsi", + gsi_ctx); + } + if (res) { + GSIERR( + "failed to register isr for %u\n", + props->irq); + return -GSI_STATUS_ERROR; + } + GSIDBG( + "succeeded to register isr for %u\n", + props->irq); + + res = enable_irq_wake(props->irq); + if (res) + GSIERR("failed to enable wake irq %u\n", props->irq); + else + GSIERR("GSI irq is wake enabled %u\n", props->irq); + + } else { + GSIERR("do not support interrupt type %u\n", props->intr); + return -GSI_STATUS_UNSUPPORTED_OP; + } + + /* If MSIs are enabled, make sure they are set up */ + if (gsi_ctx->msi.num) { + if (__gsi_allocate_msis()) { + GSIERR("failed to allocate MSIs\n"); + goto err_free_irq; + } + } + + /* + * If base not previously mapped via gsi_map_base(), map it + * now... + */ + if (!gsi_ctx->base) { + res = gsi_map_base(props->phys_addr, props->size, props->ver); + if (res) { + result = res; + goto err_free_msis; + } + } + + if (running_emulation) { + GSIDBG("GSI SW ver register value 0x%x\n", + gsihal_read_reg_n(GSI_EE_n_GSI_SW_VERSION, 0)); + gsi_ctx->intcntrlr_mem_size = + props->emulator_intcntrlr_size; + gsi_ctx->intcntrlr_base = +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 6, 0)) + devm_ioremap( +#else + devm_ioremap_nocache( +#endif + gsi_ctx->dev, + props->emulator_intcntrlr_addr, + props->emulator_intcntrlr_size); + if (!gsi_ctx->intcntrlr_base) { + GSIERR( + "failed to remap emulator's interrupt controller HW\n"); + gsi_unmap_base(); + devm_free_irq(gsi_ctx->dev, props->irq, gsi_ctx); + result = -GSI_STATUS_RES_ALLOC_FAILURE; + goto err_iounmap; + } + + GSIDBG( + "Emulator's interrupt controller base(%pa) mapped to (%pK) with len (0x%lx)\n", + &(props->emulator_intcntrlr_addr), + gsi_ctx->intcntrlr_base, + props->emulator_intcntrlr_size); + + gsi_ctx->intcntrlr_gsi_isr = gsi_isr; + gsi_ctx->intcntrlr_client_isr = + props->emulator_intcntrlr_client_isr; + } + + gsi_ctx->per_registered = true; + mutex_init(&gsi_ctx->mlock); + atomic_set(&gsi_ctx->num_chan, 0); + atomic_set(&gsi_ctx->num_evt_ring, 0); + gsi_ctx->max_ch = gsi_get_max_channels(gsi_ctx->per.ver); + if (gsi_ctx->max_ch == 0) { + gsi_unmap_base(); + if (running_emulation) + devm_iounmap(gsi_ctx->dev, gsi_ctx->intcntrlr_base); + gsi_ctx->base = gsi_ctx->intcntrlr_base = NULL; + devm_free_irq(gsi_ctx->dev, props->irq, gsi_ctx); + GSIERR("failed to get max channels\n"); + result = -GSI_STATUS_ERROR; + goto err_iounmap; + } + gsi_ctx->max_ev = gsi_get_max_event_rings(gsi_ctx->per.ver); + if (gsi_ctx->max_ev == 0) { + gsi_unmap_base(); + if (running_emulation) + devm_iounmap(gsi_ctx->dev, gsi_ctx->intcntrlr_base); + gsi_ctx->base = gsi_ctx->intcntrlr_base = NULL; + devm_free_irq(gsi_ctx->dev, props->irq, gsi_ctx); + GSIERR("failed to get max event rings\n"); + result = -GSI_STATUS_ERROR; + goto err_iounmap; + } + + if (gsi_ctx->max_ev > GSI_EVT_RING_MAX) { + GSIERR("max event rings are beyond absolute maximum\n"); + result = -GSI_STATUS_ERROR; + goto err_iounmap; + } + + if (props->mhi_er_id_limits_valid && + props->mhi_er_id_limits[0] > (gsi_ctx->max_ev - 1)) { + gsi_unmap_base(); + if (running_emulation) + devm_iounmap(gsi_ctx->dev, gsi_ctx->intcntrlr_base); + gsi_ctx->base = gsi_ctx->intcntrlr_base = NULL; + devm_free_irq(gsi_ctx->dev, props->irq, gsi_ctx); + GSIERR("MHI event ring start id %u is beyond max %u\n", + props->mhi_er_id_limits[0], gsi_ctx->max_ev); + result = -GSI_STATUS_ERROR; + goto err_iounmap; + } + + gsi_ctx->evt_bmap = ~((((unsigned long)1) << gsi_ctx->max_ev) - 1); + + /* exclude reserved mhi events */ + if (props->mhi_er_id_limits_valid) + gsi_ctx->evt_bmap |= + ((1 << (props->mhi_er_id_limits[1] + 1)) - 1) ^ + ((1 << (props->mhi_er_id_limits[0])) - 1); + + /* + * enable all interrupts but GSI_BREAK_POINT. + * Inter EE commands / interrupt are no supported. + */ + __gsi_config_type_irq(props->ee, ~0, ~0); + if (gsi_ctx->per.ver >= GSI_VER_3_0) { + __gsi_config_all_ch_irq(props->ee, ~0, ~0); + __gsi_config_all_evt_irq(props->ee, ~0, ~0); + __gsi_config_all_ieob_irq(props->ee, ~0, ~0); + } + else { + __gsi_config_ch_irq(props->ee, ~0, ~0); + __gsi_config_evt_irq(props->ee, ~0, ~0); + __gsi_config_ieob_irq(props->ee, ~0, ~0); + } + __gsi_config_glob_irq(props->ee, ~0, ~0); + + /* + * Disabling global INT1 interrupt by default and enable it + * onlt when sending the generic command. + */ + __gsi_config_glob_irq(props->ee, + gsihal_get_glob_irq_en_gp_int1_mask(), 0); + + gen_irq.gsi_mcs_stack_ovrflow = 1; + gen_irq.gsi_cmd_fifo_ovrflow = 1; + gen_irq.gsi_bus_error = 1; + gen_irq.gsi_break_point = 0; + gsihal_write_reg_n_fields(GSI_EE_n_CNTXT_GSI_IRQ_EN, + gsi_ctx->per.ee, &gen_irq); + + gsihal_write_reg_n(GSI_EE_n_CNTXT_INTSET, gsi_ctx->per.ee, props->intr); + /* set GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB/MSB to 0 */ + if ((gsi_ctx->per.ver >= GSI_VER_2_0) && + (props->intr != GSI_INTR_MSI)) { + gsihal_write_reg_n( + GSI_EE_n_CNTXT_MSI_BASE_LSB, gsi_ctx->per.ee, 0); + gsihal_write_reg_n( + GSI_EE_n_CNTXT_MSI_BASE_MSB, gsi_ctx->per.ee, 0); + } + + gsihal_read_reg_n_fields(GSI_EE_n_GSI_STATUS, + gsi_ctx->per.ee, &gsi_status); + if (gsi_status.enabled) + gsi_ctx->enabled = true; + else + GSIERR("Manager EE has not enabled GSI, GSI un-usable\n"); + + if (gsi_ctx->per.ver >= GSI_VER_1_2) + gsihal_write_reg_n(GSI_EE_n_ERROR_LOG, gsi_ctx->per.ee, 0); + + if (running_emulation) { + /* + * Set up the emulator's interrupt controller... + */ + res = setup_emulator_cntrlr( + gsi_ctx->intcntrlr_base, gsi_ctx->intcntrlr_mem_size); + if (res != 0) { + GSIERR("setup_emulator_cntrlr() failed\n"); + result = res; + goto err_iounmap; + } + } + + *dev_hdl = (uintptr_t)gsi_ctx; + gsi_ctx->gsi_isr_cache_index = 0; + + return result; +err_iounmap: + gsi_unmap_base(); + if (running_emulation && gsi_ctx->intcntrlr_base != NULL) + devm_iounmap(gsi_ctx->dev, gsi_ctx->intcntrlr_base); + gsi_ctx->base = gsi_ctx->intcntrlr_base = NULL; + +err_free_msis: + if (gsi_ctx->msi.num) { + size_t size = + sizeof(unsigned long) * BITS_TO_LONGS(gsi_ctx->msi.num); + platform_msi_domain_free_irqs(gsi_ctx->dev); + memset(gsi_ctx->msi.allocated, 0, size); + } + +err_free_irq: + devm_free_irq(gsi_ctx->dev, props->irq, gsi_ctx); + + return result; +} +EXPORT_SYMBOL(gsi_register_device); + +int gsi_write_device_scratch(unsigned long dev_hdl, + struct gsi_device_scratch *val) +{ + unsigned int max_usb_pkt_size = 0; + + if (!gsi_ctx) { + pr_err("%s:%d gsi context not allocated\n", __func__, __LINE__); + return -GSI_STATUS_NODEV; + } + + if (!gsi_ctx->per_registered) { + GSIERR("no client registered\n"); + return -GSI_STATUS_INVALID_PARAMS; + } + + if (dev_hdl != (uintptr_t)gsi_ctx) { + GSIERR("bad params dev_hdl=0x%lx gsi_ctx=0x%pK\n", dev_hdl, + gsi_ctx); + return -GSI_STATUS_INVALID_PARAMS; + } + + if (val->max_usb_pkt_size_valid && + val->max_usb_pkt_size != 1024 && + val->max_usb_pkt_size != 512 && + val->max_usb_pkt_size != 64) { + GSIERR("bad USB max pkt size dev_hdl=0x%lx sz=%u\n", dev_hdl, + val->max_usb_pkt_size); + return -GSI_STATUS_INVALID_PARAMS; + } + + mutex_lock(&gsi_ctx->mlock); + if (val->mhi_base_chan_idx_valid) + gsi_ctx->scratch.word0.s.mhi_base_chan_idx = + val->mhi_base_chan_idx; + + if (val->max_usb_pkt_size_valid) { + max_usb_pkt_size = 2; + if (val->max_usb_pkt_size > 64) + max_usb_pkt_size = + (val->max_usb_pkt_size == 1024) ? 1 : 0; + gsi_ctx->scratch.word0.s.max_usb_pkt_size = max_usb_pkt_size; + } + + gsihal_write_reg_n(GSI_EE_n_CNTXT_SCRATCH_0, + gsi_ctx->per.ee, gsi_ctx->scratch.word0.val); + mutex_unlock(&gsi_ctx->mlock); + + return GSI_STATUS_SUCCESS; +} +EXPORT_SYMBOL(gsi_write_device_scratch); + +int gsi_deregister_device(unsigned long dev_hdl, bool force) +{ + if (!gsi_ctx) { + pr_err("%s:%d gsi context not allocated\n", __func__, __LINE__); + return -GSI_STATUS_NODEV; + } + + if (!gsi_ctx->per_registered) { + GSIERR("no client registered\n"); + return -GSI_STATUS_INVALID_PARAMS; + } + + if (dev_hdl != (uintptr_t)gsi_ctx) { + GSIERR("bad params dev_hdl=0x%lx gsi_ctx=0x%pK\n", dev_hdl, + gsi_ctx); + return -GSI_STATUS_INVALID_PARAMS; + } + + if (!force && atomic_read(&gsi_ctx->num_chan)) { + GSIERR("cannot deregister %u channels are still connected\n", + atomic_read(&gsi_ctx->num_chan)); + return -GSI_STATUS_UNSUPPORTED_OP; + } + + if (!force && atomic_read(&gsi_ctx->num_evt_ring)) { + GSIERR("cannot deregister %u events are still connected\n", + atomic_read(&gsi_ctx->num_evt_ring)); + return -GSI_STATUS_UNSUPPORTED_OP; + } + + /* disable all interrupts */ + __gsi_config_type_irq(gsi_ctx->per.ee, ~0, 0); + if (gsi_ctx->per.ver >= GSI_VER_3_0) { + __gsi_config_all_ch_irq(gsi_ctx->per.ee, ~0, 0); + __gsi_config_all_evt_irq(gsi_ctx->per.ee, ~0, 0); + __gsi_config_all_ieob_irq(gsi_ctx->per.ee, ~0, 0); + } + else { + __gsi_config_ch_irq(gsi_ctx->per.ee, ~0, 0); + __gsi_config_evt_irq(gsi_ctx->per.ee, ~0, 0); + __gsi_config_ieob_irq(gsi_ctx->per.ee, ~0, 0); + } + __gsi_config_glob_irq(gsi_ctx->per.ee, ~0, 0); + __gsi_config_gen_irq(gsi_ctx->per.ee, ~0, 0); + + if (gsi_ctx->msi.num) + platform_msi_domain_free_irqs(gsi_ctx->dev); + + devm_free_irq(gsi_ctx->dev, gsi_ctx->per.irq, gsi_ctx); + gsihal_destroy(); + gsi_unmap_base(); + gsi_ctx->per_registered = false; + return GSI_STATUS_SUCCESS; +} +EXPORT_SYMBOL(gsi_deregister_device); + +static void gsi_program_evt_ring_ctx(struct gsi_evt_ring_props *props, + uint8_t evt_id, unsigned int ee) +{ + struct gsihal_reg_ev_ch_k_cntxt_0 ev_ch_k_cntxt_0; + struct gsihal_reg_ev_ch_k_cntxt_1 ev_ch_k_cntxt_1; + struct gsihal_reg_ev_ch_k_cntxt_2 ev_ch_k_cntxt_2; + struct gsihal_reg_ev_ch_k_cntxt_3 ev_ch_k_cntxt_3; + struct gsihal_reg_ev_ch_k_cntxt_8 ev_ch_k_cntxt_8; + struct gsihal_reg_ev_ch_k_cntxt_9 ev_ch_k_cntxt_9; + union gsihal_reg_ev_ch_k_cntxt_10 ev_ch_k_cntxt_10; + union gsihal_reg_ev_ch_k_cntxt_11 ev_ch_k_cntxt_11; + struct gsihal_reg_ev_ch_k_cntxt_12 ev_ch_k_cntxt_12; + struct gsihal_reg_ev_ch_k_cntxt_13 ev_ch_k_cntxt_13; + + GSIDBG("intf=%u intr=%u re=%u\n", props->intf, props->intr, + props->re_size); + ev_ch_k_cntxt_0.chtype = props->intf; + ev_ch_k_cntxt_0.intype = props->intr; + ev_ch_k_cntxt_0.element_size = props->re_size; + gsihal_write_reg_nk_fields(GSI_EE_n_EV_CH_k_CNTXT_0, + ee, evt_id, &ev_ch_k_cntxt_0); + + ev_ch_k_cntxt_1.r_length = props->ring_len; + gsihal_write_reg_nk_fields(GSI_EE_n_EV_CH_k_CNTXT_1, + ee, evt_id, + &ev_ch_k_cntxt_1); + + ev_ch_k_cntxt_2.r_base_addr_lsbs = GSI_LSB(props->ring_base_addr); + gsihal_write_reg_nk_fields(GSI_EE_n_EV_CH_k_CNTXT_2, + ee, evt_id, + &ev_ch_k_cntxt_2); + + ev_ch_k_cntxt_3.r_base_addr_msbs = GSI_MSB(props->ring_base_addr); + gsihal_write_reg_nk_fields(GSI_EE_n_EV_CH_k_CNTXT_3, + ee, evt_id, + &ev_ch_k_cntxt_3); + + ev_ch_k_cntxt_8.int_modt = props->int_modt; + ev_ch_k_cntxt_8.int_modc = props->int_modc; + gsihal_write_reg_nk_fields(GSI_EE_n_EV_CH_k_CNTXT_8, + ee, evt_id, + &ev_ch_k_cntxt_8); + + ev_ch_k_cntxt_9.intvec = props->intvec; + gsihal_write_reg_nk_fields(GSI_EE_n_EV_CH_k_CNTXT_9, + ee, evt_id, + &ev_ch_k_cntxt_9); + + if(props->intf != GSI_EVT_CHTYPE_WDI3_V2_EV) { + ev_ch_k_cntxt_10.msi_addr_lsb = GSI_LSB(props->msi_addr); + gsihal_write_reg_nk_fields(GSI_EE_n_EV_CH_k_CNTXT_10, + ee, evt_id, + &ev_ch_k_cntxt_10); + + ev_ch_k_cntxt_11.msi_addr_msb = GSI_MSB(props->msi_addr); + gsihal_write_reg_nk_fields(GSI_EE_n_EV_CH_k_CNTXT_11, + ee, evt_id, + &ev_ch_k_cntxt_11); + + + ev_ch_k_cntxt_12.rp_update_addr_lsb = GSI_LSB(props->rp_update_addr); + gsihal_write_reg_nk_fields(GSI_EE_n_EV_CH_k_CNTXT_12, + ee, evt_id, + &ev_ch_k_cntxt_12); + + ev_ch_k_cntxt_13.rp_update_addr_msb = GSI_MSB(props->rp_update_addr); + gsihal_write_reg_nk_fields(GSI_EE_n_EV_CH_k_CNTXT_13, + ee, evt_id, + &ev_ch_k_cntxt_13); + } + else { + ev_ch_k_cntxt_10.rp_addr_lsb = GSI_LSB(props->rp_update_addr); + gsihal_write_reg_nk_fields(GSI_EE_n_EV_CH_k_CNTXT_10, + ee, evt_id, + &ev_ch_k_cntxt_10); + + ev_ch_k_cntxt_11.rp_addr_msb = GSI_MSB(props->rp_update_addr); + gsihal_write_reg_nk_fields(GSI_EE_n_EV_CH_k_CNTXT_11, + ee, evt_id, + &ev_ch_k_cntxt_11); + } + + +} + +static void gsi_init_evt_ring(struct gsi_evt_ring_props *props, + struct gsi_ring_ctx *ctx) +{ + ctx->base_va = (uintptr_t)props->ring_base_vaddr; + ctx->base = props->ring_base_addr; + ctx->wp = ctx->base; + ctx->rp = ctx->base; + ctx->wp_local = ctx->base; + ctx->rp_local = ctx->base; + ctx->len = props->ring_len; + ctx->elem_sz = props->re_size; + ctx->max_num_elem = ctx->len / ctx->elem_sz - 1; + ctx->end = ctx->base + (ctx->max_num_elem + 1) * ctx->elem_sz; + + if (props->rp_update_vaddr) + *(uint64_t *)(props->rp_update_vaddr) = ctx->rp_local; +} + +static void gsi_prime_evt_ring(struct gsi_evt_ctx *ctx) +{ + unsigned long flags; + struct gsihal_reg_gsi_ee_n_ev_ch_k_doorbell_1 db; + + spin_lock_irqsave(&ctx->ring.slock, flags); + memset((void *)ctx->ring.base_va, 0, ctx->ring.len); + ctx->ring.wp_local = ctx->ring.base + + ctx->ring.max_num_elem * ctx->ring.elem_sz; + + /* write order MUST be MSB followed by LSB */ + db.write_ptr_msb = GSI_MSB(ctx->ring.wp_local); + gsihal_write_reg_nk_fields(GSI_EE_n_EV_CH_k_DOORBELL_1, + gsi_ctx->per.ee, ctx->id, &db); + + gsi_ring_evt_doorbell(ctx); + spin_unlock_irqrestore(&ctx->ring.slock, flags); +} + +static void gsi_prime_evt_ring_wdi(struct gsi_evt_ctx *ctx) +{ + unsigned long flags; + + spin_lock_irqsave(&ctx->ring.slock, flags); + if (ctx->ring.base_va) + memset((void *)ctx->ring.base_va, 0, ctx->ring.len); + ctx->ring.wp_local = ctx->ring.base + + ((ctx->ring.max_num_elem + 2) * ctx->ring.elem_sz); + gsi_ring_evt_doorbell(ctx); + spin_unlock_irqrestore(&ctx->ring.slock, flags); +} + +static int gsi_validate_evt_ring_props(struct gsi_evt_ring_props *props) +{ + uint64_t ra; + + if ((props->re_size == GSI_EVT_RING_RE_SIZE_4B && + props->ring_len % 4) || + (props->re_size == GSI_EVT_RING_RE_SIZE_8B && + props->ring_len % 8) || + (props->re_size == GSI_EVT_RING_RE_SIZE_16B && + props->ring_len % 16) || + (props->re_size == GSI_EVT_RING_RE_SIZE_32B && + props->ring_len % 32)) { + GSIERR("bad params ring_len %u not a multiple of RE size %u\n", + props->ring_len, props->re_size); + return -GSI_STATUS_INVALID_PARAMS; + } + + if (!gsihal_check_ring_length_valid(props->ring_len, props->re_size)) + return -GSI_STATUS_INVALID_PARAMS; + + ra = props->ring_base_addr; + do_div(ra, roundup_pow_of_two(props->ring_len)); + + if (props->ring_base_addr != ra * roundup_pow_of_two(props->ring_len)) { + GSIERR("bad params ring base not aligned 0x%llx align 0x%lx\n", + props->ring_base_addr, + roundup_pow_of_two(props->ring_len)); + return -GSI_STATUS_INVALID_PARAMS; + } + + if (props->intf == GSI_EVT_CHTYPE_GPI_EV && + !props->ring_base_vaddr) { + GSIERR("protocol %u requires ring base VA\n", props->intf); + return -GSI_STATUS_INVALID_PARAMS; + } + + if (props->intf == GSI_EVT_CHTYPE_MHI_EV && + (!props->evchid_valid || + props->evchid > gsi_ctx->per.mhi_er_id_limits[1] || + props->evchid < gsi_ctx->per.mhi_er_id_limits[0])) { + GSIERR("MHI requires evchid valid=%d val=%u\n", + props->evchid_valid, props->evchid); + return -GSI_STATUS_INVALID_PARAMS; + } + + if (props->intf != GSI_EVT_CHTYPE_MHI_EV && + props->evchid_valid) { + GSIERR("protocol %u cannot specify evchid\n", props->intf); + return -GSI_STATUS_INVALID_PARAMS; + } + + if (!props->err_cb) { + GSIERR("err callback must be provided\n"); + return -GSI_STATUS_INVALID_PARAMS; + } + + return GSI_STATUS_SUCCESS; +} + +/** + * gsi_cleanup_xfer_user_data: cleanup the user data array using callback passed + * by IPA driver. Need to do this in GSI since only GSI knows which TRE + * are being used or not. However, IPA is the one that does cleaning, + * therefore we pass a callback from IPA and call it using params from GSI + * + * @chan_hdl: hdl of the gsi channel user data array to be cleaned + * @cleanup_cb: callback used to clean the user data array. takes 2 inputs + * @chan_user_data: ipa_sys_context of the gsi_channel + * @xfer_uder_data: user data array element (rx_pkt wrapper) + * + * Returns: 0 on success, negative on failure + */ +static int gsi_cleanup_xfer_user_data(unsigned long chan_hdl, + void (*cleanup_cb)(void *chan_user_data, void *xfer_user_data)) +{ + struct gsi_chan_ctx *ctx; + uint64_t i; + uint16_t rp_idx; + + ctx = &gsi_ctx->chan[chan_hdl]; + if (ctx->state != GSI_CHAN_STATE_ALLOCATED) { + GSIERR("bad state %d\n", ctx->state); + return -GSI_STATUS_UNSUPPORTED_OP; + } + + /* for coalescing, traverse the whole array */ + if (ctx->props.prot == GSI_CHAN_PROT_GCI) { + size_t user_data_size = + ctx->ring.max_num_elem + 1 + GSI_VEID_MAX; + for (i = 0; i < user_data_size; i++) { + if (ctx->user_data[i].valid) + cleanup_cb(ctx->props.chan_user_data, + ctx->user_data[i].p); + } + } else { + /* for non-coalescing, clean between RP and WP */ + while (ctx->ring.rp_local != ctx->ring.wp_local) { + rp_idx = gsi_find_idx_from_addr(&ctx->ring, + ctx->ring.rp_local); + WARN_ON(!ctx->user_data[rp_idx].valid); + cleanup_cb(ctx->props.chan_user_data, + ctx->user_data[rp_idx].p); + gsi_incr_ring_rp(&ctx->ring); + } + } + return 0; +} + +/** + * gsi_read_event_ring_rp_ddr - function returns the RP value of the event + * ring read from the ring context register. + * + * @props: Props structere of the event channel + * @id: Event channel index + * @ee: EE + * + * @Return pointer to the read pointer + */ +static inline uint64_t gsi_read_event_ring_rp_ddr(struct gsi_evt_ring_props* props, + uint8_t id, int ee) +{ + return readl_relaxed(props->rp_update_vaddr); +} + +/** + * gsi_read_event_ring_rp_reg - function returns the RP value of the event ring + * read from the DDR. + * + * @props: Props structere of the event channel + * @id: Event channel index + * @ee: EE + * + * @Return pointer to the read pointer + */ +static inline uint64_t gsi_read_event_ring_rp_reg(struct gsi_evt_ring_props* props, + uint8_t id, int ee) +{ + uint64_t rp; + + rp = gsihal_read_reg_nk(GSI_EE_n_EV_CH_k_CNTXT_4, ee, id); + rp |= ((uint64_t)gsihal_read_reg_nk(GSI_EE_n_EV_CH_k_CNTXT_5, ee, id)) << 32; + + return rp; +} + +static int __gsi_pair_msi(struct gsi_evt_ctx *ctx, + struct gsi_evt_ring_props *props) +{ + int result = GSI_STATUS_SUCCESS; + unsigned long msi = 0; + + if (IS_ERR_OR_NULL(ctx) || IS_ERR_OR_NULL(props) || IS_ERR_OR_NULL(gsi_ctx)) + BUG(); + + /* Find the first unused MSI */ + msi = find_first_zero_bit(gsi_ctx->msi.used, gsi_ctx->msi.num); + if (msi >= gsi_ctx->msi.num) { + GSIERR("No free MSIs for evt %u\n", ctx->id); + return -GSI_STATUS_ERROR; + } + + /* Ensure it's been allocated */ + if (!test_bit((int)msi, gsi_ctx->msi.allocated)) { + GSIDBG("MSI %lu not allocated\n", msi); + return -GSI_STATUS_ERROR; + } + + /* Save the event ID for later lookup */ + gsi_ctx->msi.evt[msi] = ctx->id; + + /* Add this event to the IRQ mask */ + set_bit((int)ctx->id, &gsi_ctx->msi.mask); + + props->intvec = gsi_ctx->msi.msg[msi].data; + props->msi_addr = (uint64_t)gsi_ctx->msi.msg[msi].address_hi << 32 | + (uint64_t)gsi_ctx->msi.msg[msi].address_lo; + + GSIDBG("props->intvec = %d, props->msi_addr = %lu\n", props->intvec, props->msi_addr); + + if (props->msi_addr == 0) + BUG(); + + /* Mark MSI as used */ + set_bit(msi, gsi_ctx->msi.used); + + return result; +} + +int gsi_alloc_evt_ring(struct gsi_evt_ring_props *props, unsigned long dev_hdl, + unsigned long *evt_ring_hdl) +{ + unsigned long evt_id; + enum gsi_evt_ch_cmd_opcode op = GSI_EVT_ALLOCATE; + struct gsihal_reg_ee_n_ev_ch_cmd ev_ch_cmd; + struct gsi_evt_ctx *ctx; + int res = 0; + int ee; + unsigned long flags; + + if (!gsi_ctx) { + pr_err("%s:%d gsi context not allocated\n", __func__, __LINE__); + return -GSI_STATUS_NODEV; + } + + if (!props || !evt_ring_hdl || dev_hdl != (uintptr_t)gsi_ctx) { + GSIERR("bad params props=%pK dev_hdl=0x%lx evt_ring_hdl=%pK\n", + props, dev_hdl, evt_ring_hdl); + return -GSI_STATUS_INVALID_PARAMS; + } + + if (gsi_validate_evt_ring_props(props)) { + GSIERR("invalid params\n"); + return -GSI_STATUS_INVALID_PARAMS; + } + + if (!props->evchid_valid) { + mutex_lock(&gsi_ctx->mlock); + evt_id = find_first_zero_bit(&gsi_ctx->evt_bmap, + sizeof(unsigned long) * BITS_PER_BYTE); + if (evt_id == sizeof(unsigned long) * BITS_PER_BYTE) { + GSIERR("failed to alloc event ID\n"); + mutex_unlock(&gsi_ctx->mlock); + return -GSI_STATUS_RES_ALLOC_FAILURE; + } + set_bit(evt_id, &gsi_ctx->evt_bmap); + mutex_unlock(&gsi_ctx->mlock); + } else { + evt_id = props->evchid; + } + GSIDBG("Using %lu as virt evt id\n", evt_id); + + if (props->rp_update_addr != 0) { + GSIDBG("Using DDR to read event RP for virt evt id: %lu\n", + evt_id); + props->gsi_read_event_ring_rp = + gsi_read_event_ring_rp_ddr; + } + else { + GSIDBG("Using CONTEXT reg to read event RP for virt evt id: %lu\n", + evt_id); + props->gsi_read_event_ring_rp = + gsi_read_event_ring_rp_reg; + } + + ctx = &gsi_ctx->evtr[evt_id]; + memset(ctx, 0, sizeof(*ctx)); + mutex_init(&ctx->mlock); + init_completion(&ctx->compl); + atomic_set(&ctx->chan_ref_cnt, 0); + ctx->num_of_chan_allocated = 0; + ctx->id = evt_id; + + mutex_lock(&gsi_ctx->mlock); + /* Pair an MSI with this event if this is an MSI and GPI event channel + * NOTE: This modifies props, so must be before props are saved to ctx. + */ + if (props->intf == GSI_EVT_CHTYPE_GPI_EV && + props->intr == GSI_INTR_MSI) { + if (__gsi_pair_msi(ctx, props)) { + GSIERR("evt_id=%lu failed to pair MSI\n", evt_id); + if (!props->evchid_valid) + clear_bit(evt_id, &gsi_ctx->evt_bmap); + mutex_unlock(&gsi_ctx->mlock); + return -GSI_STATUS_NODEV; + } + GSIDBG("evt_id=%lu pair MSI succesful\n", evt_id); + } + ctx->props = *props; + + ee = gsi_ctx->per.ee; + ev_ch_cmd.opcode = op; + ev_ch_cmd.chid = evt_id; + gsihal_write_reg_n_fields(GSI_EE_n_EV_CH_CMD, ee, &ev_ch_cmd); + res = wait_for_completion_timeout(&ctx->compl, GSI_CMD_TIMEOUT); + if (res == 0) { + GSIERR("evt_id=%lu timed out\n", evt_id); + if (!props->evchid_valid) + clear_bit(evt_id, &gsi_ctx->evt_bmap); + mutex_unlock(&gsi_ctx->mlock); + return -GSI_STATUS_TIMED_OUT; + } + + if (ctx->state != GSI_EVT_RING_STATE_ALLOCATED) { + GSIERR("evt_id=%lu allocation failed state=%u\n", + evt_id, ctx->state); + if (!props->evchid_valid) + clear_bit(evt_id, &gsi_ctx->evt_bmap); + mutex_unlock(&gsi_ctx->mlock); + return -GSI_STATUS_RES_ALLOC_FAILURE; + } + + gsi_program_evt_ring_ctx(props, evt_id, gsi_ctx->per.ee); + + spin_lock_init(&ctx->ring.slock); + gsi_init_evt_ring(props, &ctx->ring); + + ctx->id = evt_id; + *evt_ring_hdl = evt_id; + atomic_inc(&gsi_ctx->num_evt_ring); + if (props->intf == GSI_EVT_CHTYPE_GPI_EV) + gsi_prime_evt_ring(ctx); + else if (props->intf == GSI_EVT_CHTYPE_WDI2_EV) + gsi_prime_evt_ring_wdi(ctx); + mutex_unlock(&gsi_ctx->mlock); + + spin_lock_irqsave(&gsi_ctx->slock, flags); + if (gsi_ctx->per.ver >= GSI_VER_3_0) { + gsihal_write_reg_nk(GSI_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_k, ee, + gsihal_get_ch_reg_idx(evt_id), gsihal_get_ch_reg_mask(evt_id)); + } + else { + gsihal_write_reg_n(GSI_EE_n_CNTXT_SRC_IEOB_IRQ_CLR, ee, 1 << evt_id); + } + + /* enable ieob interrupts for GPI, enable MSI interrupts */ + if (gsi_ctx->per.ver >= GSI_VER_3_0) { + if ((props->intf != GSI_EVT_CHTYPE_GPI_EV) && + (props->intr != GSI_INTR_MSI)) + __gsi_config_ieob_irq_k(gsi_ctx->per.ee, gsihal_get_ch_reg_idx(evt_id), + gsihal_get_ch_reg_mask(evt_id), + 0); + else + __gsi_config_ieob_irq_k(gsi_ctx->per.ee, gsihal_get_ch_reg_idx(evt_id), + gsihal_get_ch_reg_mask(evt_id), + ~0); + } + else { + if ((props->intf != GSI_EVT_CHTYPE_GPI_EV) && + (props->intr != GSI_INTR_MSI)) + __gsi_config_ieob_irq(gsi_ctx->per.ee, 1 << evt_id, 0); + else + __gsi_config_ieob_irq(gsi_ctx->per.ee, 1 << ctx->id, ~0); + } + spin_unlock_irqrestore(&gsi_ctx->slock, flags); + + return GSI_STATUS_SUCCESS; +} +EXPORT_SYMBOL(gsi_alloc_evt_ring); + +static void __gsi_write_evt_ring_scratch(unsigned long evt_ring_hdl, + union __packed gsi_evt_scratch val) +{ + gsihal_write_reg_nk(GSI_EE_n_EV_CH_k_SCRATCH_0, + gsi_ctx->per.ee, evt_ring_hdl, val.data.word1); + gsihal_write_reg_nk(GSI_EE_n_EV_CH_k_SCRATCH_1, + gsi_ctx->per.ee, evt_ring_hdl, val.data.word2); +} + +int gsi_write_evt_ring_scratch(unsigned long evt_ring_hdl, + union __packed gsi_evt_scratch val) +{ + struct gsi_evt_ctx *ctx; + + if (!gsi_ctx) { + pr_err("%s:%d gsi context not allocated\n", __func__, __LINE__); + return -GSI_STATUS_NODEV; + } + + if (evt_ring_hdl >= gsi_ctx->max_ev) { + GSIERR("bad params evt_ring_hdl=%lu\n", evt_ring_hdl); + return -GSI_STATUS_INVALID_PARAMS; + } + + ctx = &gsi_ctx->evtr[evt_ring_hdl]; + + if (ctx->state != GSI_EVT_RING_STATE_ALLOCATED) { + GSIERR("bad state %d\n", + gsi_ctx->evtr[evt_ring_hdl].state); + return -GSI_STATUS_UNSUPPORTED_OP; + } + + mutex_lock(&ctx->mlock); + ctx->scratch = val; + __gsi_write_evt_ring_scratch(evt_ring_hdl, val); + mutex_unlock(&ctx->mlock); + + return GSI_STATUS_SUCCESS; +} +EXPORT_SYMBOL(gsi_write_evt_ring_scratch); + +int gsi_dealloc_evt_ring(unsigned long evt_ring_hdl) +{ + struct gsihal_reg_ee_n_ev_ch_cmd ev_ch_cmd; + enum gsi_evt_ch_cmd_opcode op = GSI_EVT_DE_ALLOC; + struct gsi_evt_ctx *ctx; + int res = 0; + u32 msi; + + if (!gsi_ctx) { + pr_err("%s:%d gsi context not allocated\n", __func__, __LINE__); + return -GSI_STATUS_NODEV; + } + + if (evt_ring_hdl >= gsi_ctx->max_ev || + evt_ring_hdl >= GSI_EVT_RING_MAX) { + GSIERR("bad params evt_ring_hdl=%lu\n", evt_ring_hdl); + return -GSI_STATUS_INVALID_PARAMS; + } + + ctx = &gsi_ctx->evtr[evt_ring_hdl]; + + if (atomic_read(&ctx->chan_ref_cnt)) { + GSIERR("%d channels still using this event ring\n", + atomic_read(&ctx->chan_ref_cnt)); + return -GSI_STATUS_UNSUPPORTED_OP; + } + + if (ctx->state != GSI_EVT_RING_STATE_ALLOCATED) { + GSIERR("bad state %d\n", ctx->state); + return -GSI_STATUS_UNSUPPORTED_OP; + } + + /* Unpair the MSI */ + if (ctx->props.intf == GSI_EVT_CHTYPE_GPI_EV && + ctx->props.intr == GSI_INTR_MSI) { + GSIERR("Interrupt dereg for msi_irq = %d\n", ctx->props.msi_irq); + + for (msi = 0; msi < gsi_ctx->msi.num; msi++) { + if (gsi_ctx->msi.msg[msi].data == ctx->props.intvec) { + mutex_lock(&gsi_ctx->mlock); + clear_bit(msi, gsi_ctx->msi.used); + gsi_ctx->msi.evt[msi] = 0; + clear_bit(evt_ring_hdl, &gsi_ctx->msi.mask); + mutex_unlock(&gsi_ctx->mlock); + } + } + } + + mutex_lock(&gsi_ctx->mlock); + reinit_completion(&ctx->compl); + ev_ch_cmd.chid = evt_ring_hdl; + ev_ch_cmd.opcode = op; + gsihal_write_reg_n_fields(GSI_EE_n_EV_CH_CMD, + gsi_ctx->per.ee, &ev_ch_cmd); + res = wait_for_completion_timeout(&ctx->compl, GSI_CMD_TIMEOUT); + if (res == 0) { + GSIERR("evt_id=%lu timed out\n", evt_ring_hdl); + mutex_unlock(&gsi_ctx->mlock); + return -GSI_STATUS_TIMED_OUT; + } + + if (ctx->state != GSI_EVT_RING_STATE_NOT_ALLOCATED) { + GSIERR("evt_id=%lu unexpected state=%u\n", evt_ring_hdl, + ctx->state); + /* + * IPA Hardware returned GSI RING not allocated, which is + * unexpected hardware state. + */ + GSI_ASSERT(); + } + mutex_unlock(&gsi_ctx->mlock); + + if (!ctx->props.evchid_valid) { + mutex_lock(&gsi_ctx->mlock); + clear_bit(evt_ring_hdl, &gsi_ctx->evt_bmap); + mutex_unlock(&gsi_ctx->mlock); + } + atomic_dec(&gsi_ctx->num_evt_ring); + + return GSI_STATUS_SUCCESS; +} +EXPORT_SYMBOL(gsi_dealloc_evt_ring); + +int gsi_query_evt_ring_db_addr(unsigned long evt_ring_hdl, + uint32_t *db_addr_wp_lsb, uint32_t *db_addr_wp_msb) +{ + struct gsi_evt_ctx *ctx; + + if (!gsi_ctx) { + pr_err("%s:%d gsi context not allocated\n", __func__, __LINE__); + return -GSI_STATUS_NODEV; + } + + if (!db_addr_wp_msb || !db_addr_wp_lsb) { + GSIERR("bad params msb=%pK lsb=%pK\n", db_addr_wp_msb, + db_addr_wp_lsb); + return -GSI_STATUS_INVALID_PARAMS; + } + + if (evt_ring_hdl >= gsi_ctx->max_ev) { + GSIERR("bad params evt_ring_hdl=%lu\n", evt_ring_hdl); + return -GSI_STATUS_INVALID_PARAMS; + } + + ctx = &gsi_ctx->evtr[evt_ring_hdl]; + + if (ctx->state != GSI_EVT_RING_STATE_ALLOCATED) { + GSIERR("bad state %d\n", + gsi_ctx->evtr[evt_ring_hdl].state); + return -GSI_STATUS_UNSUPPORTED_OP; + } + + *db_addr_wp_lsb = gsi_ctx->per.phys_addr + gsihal_get_reg_nk_ofst( + GSI_EE_n_EV_CH_k_DOORBELL_0, gsi_ctx->per.ee, evt_ring_hdl); + + *db_addr_wp_msb = gsi_ctx->per.phys_addr + gsihal_get_reg_nk_ofst( + GSI_EE_n_EV_CH_k_DOORBELL_1, gsi_ctx->per.ee, evt_ring_hdl); + + return GSI_STATUS_SUCCESS; +} +EXPORT_SYMBOL(gsi_query_evt_ring_db_addr); + +int gsi_ring_evt_ring_db(unsigned long evt_ring_hdl, uint64_t value) +{ + struct gsi_evt_ctx *ctx; + + if (!gsi_ctx) { + pr_err("%s:%d gsi context not allocated\n", __func__, __LINE__); + return -GSI_STATUS_NODEV; + } + + if (evt_ring_hdl >= gsi_ctx->max_ev) { + GSIERR("bad params evt_ring_hdl=%lu\n", evt_ring_hdl); + return -GSI_STATUS_INVALID_PARAMS; + } + + ctx = &gsi_ctx->evtr[evt_ring_hdl]; + + if (ctx->state != GSI_EVT_RING_STATE_ALLOCATED) { + GSIERR("bad state %d\n", + gsi_ctx->evtr[evt_ring_hdl].state); + return -GSI_STATUS_UNSUPPORTED_OP; + } + + ctx->ring.wp_local = value; + gsi_ring_evt_doorbell(ctx); + + return GSI_STATUS_SUCCESS; +} +EXPORT_SYMBOL(gsi_ring_evt_ring_db); + +int gsi_ring_ch_ring_db(unsigned long chan_hdl, uint64_t value) +{ + struct gsi_chan_ctx *ctx; + + if (!gsi_ctx) { + pr_err("%s:%d gsi context not allocated\n", __func__, __LINE__); + return -GSI_STATUS_NODEV; + } + + if (chan_hdl >= gsi_ctx->max_ch) { + GSIERR("bad chan_hdl=%lu\n", chan_hdl); + return -GSI_STATUS_INVALID_PARAMS; + } + + ctx = &gsi_ctx->chan[chan_hdl]; + + if (ctx->state != GSI_CHAN_STATE_STARTED) { + GSIERR("bad state %d\n", ctx->state); + return -GSI_STATUS_UNSUPPORTED_OP; + } + + ctx->ring.wp_local = value; + + /* write MSB first */ + gsihal_write_reg_nk(GSI_EE_n_GSI_CH_k_DOORBELL_1, + gsi_ctx->per.ee, ctx->props.ch_id, GSI_MSB(ctx->ring.wp_local)); + + gsi_ring_chan_doorbell(ctx); + + return GSI_STATUS_SUCCESS; +} +EXPORT_SYMBOL(gsi_ring_ch_ring_db); + +int gsi_reset_evt_ring(unsigned long evt_ring_hdl) +{ + struct gsihal_reg_ee_n_ev_ch_cmd ev_ch_cmd; + enum gsi_evt_ch_cmd_opcode op = GSI_EVT_RESET; + struct gsi_evt_ctx *ctx; + int res; + + if (!gsi_ctx) { + pr_err("%s:%d gsi context not allocated\n", __func__, __LINE__); + return -GSI_STATUS_NODEV; + } + + if (evt_ring_hdl >= gsi_ctx->max_ev) { + GSIERR("bad params evt_ring_hdl=%lu\n", evt_ring_hdl); + return -GSI_STATUS_INVALID_PARAMS; + } + + ctx = &gsi_ctx->evtr[evt_ring_hdl]; + + if (ctx->state != GSI_EVT_RING_STATE_ALLOCATED) { + GSIERR("bad state %d\n", ctx->state); + return -GSI_STATUS_UNSUPPORTED_OP; + } + + mutex_lock(&gsi_ctx->mlock); + reinit_completion(&ctx->compl); + ev_ch_cmd.chid = evt_ring_hdl; + ev_ch_cmd.opcode = op; + gsihal_write_reg_n_fields(GSI_EE_n_EV_CH_CMD, + gsi_ctx->per.ee, &ev_ch_cmd); + res = wait_for_completion_timeout(&ctx->compl, GSI_CMD_TIMEOUT); + if (res == 0) { + GSIERR("evt_id=%lu timed out\n", evt_ring_hdl); + mutex_unlock(&gsi_ctx->mlock); + return -GSI_STATUS_TIMED_OUT; + } + + if (ctx->state != GSI_EVT_RING_STATE_ALLOCATED) { + GSIERR("evt_id=%lu unexpected state=%u\n", evt_ring_hdl, + ctx->state); + /* + * IPA Hardware returned GSI RING not allocated, which is + * unexpected. Indicates hardware instability. + */ + GSI_ASSERT(); + } + + gsi_program_evt_ring_ctx(&ctx->props, evt_ring_hdl, gsi_ctx->per.ee); + gsi_init_evt_ring(&ctx->props, &ctx->ring); + + /* restore scratch */ + __gsi_write_evt_ring_scratch(evt_ring_hdl, ctx->scratch); + + if (ctx->props.intf == GSI_EVT_CHTYPE_GPI_EV) + gsi_prime_evt_ring(ctx); + if (ctx->props.intf == GSI_EVT_CHTYPE_WDI2_EV) + gsi_prime_evt_ring_wdi(ctx); + mutex_unlock(&gsi_ctx->mlock); + + return GSI_STATUS_SUCCESS; +} +EXPORT_SYMBOL(gsi_reset_evt_ring); + +int gsi_get_evt_ring_cfg(unsigned long evt_ring_hdl, + struct gsi_evt_ring_props *props, union gsi_evt_scratch *scr) +{ + struct gsi_evt_ctx *ctx; + + if (!gsi_ctx) { + pr_err("%s:%d gsi context not allocated\n", __func__, __LINE__); + return -GSI_STATUS_NODEV; + } + + if (!props || !scr) { + GSIERR("bad params props=%pK scr=%pK\n", props, scr); + return -GSI_STATUS_INVALID_PARAMS; + } + + if (evt_ring_hdl >= gsi_ctx->max_ev) { + GSIERR("bad params evt_ring_hdl=%lu\n", evt_ring_hdl); + return -GSI_STATUS_INVALID_PARAMS; + } + + ctx = &gsi_ctx->evtr[evt_ring_hdl]; + + if (ctx->state == GSI_EVT_RING_STATE_NOT_ALLOCATED) { + GSIERR("bad state %d\n", ctx->state); + return -GSI_STATUS_UNSUPPORTED_OP; + } + + mutex_lock(&ctx->mlock); + *props = ctx->props; + *scr = ctx->scratch; + mutex_unlock(&ctx->mlock); + + return GSI_STATUS_SUCCESS; +} +EXPORT_SYMBOL(gsi_get_evt_ring_cfg); + +int gsi_set_evt_ring_cfg(unsigned long evt_ring_hdl, + struct gsi_evt_ring_props *props, union gsi_evt_scratch *scr) +{ + struct gsi_evt_ctx *ctx; + + if (!gsi_ctx) { + pr_err("%s:%d gsi context not allocated\n", __func__, __LINE__); + return -GSI_STATUS_NODEV; + } + + if (!props || gsi_validate_evt_ring_props(props)) { + GSIERR("bad params props=%pK\n", props); + return -GSI_STATUS_INVALID_PARAMS; + } + + if (evt_ring_hdl >= gsi_ctx->max_ev) { + GSIERR("bad params evt_ring_hdl=%lu\n", evt_ring_hdl); + return -GSI_STATUS_INVALID_PARAMS; + } + + ctx = &gsi_ctx->evtr[evt_ring_hdl]; + + if (ctx->state != GSI_EVT_RING_STATE_ALLOCATED) { + GSIERR("bad state %d\n", ctx->state); + return -GSI_STATUS_UNSUPPORTED_OP; + } + + if (ctx->props.exclusive != props->exclusive) { + GSIERR("changing immutable fields not supported\n"); + return -GSI_STATUS_UNSUPPORTED_OP; + } + + mutex_lock(&ctx->mlock); + ctx->props = *props; + if (scr) + ctx->scratch = *scr; + mutex_unlock(&ctx->mlock); + + return gsi_reset_evt_ring(evt_ring_hdl); +} +EXPORT_SYMBOL(gsi_set_evt_ring_cfg); + +static void gsi_program_chan_ctx_qos(struct gsi_chan_props *props, + unsigned int ee) +{ + struct gsihal_reg_gsi_ee_n_gsi_ch_k_qos ch_k_qos; + + ch_k_qos.wrr_weight = props->low_weight; + ch_k_qos.max_prefetch = props->max_prefetch; + ch_k_qos.use_db_eng = props->use_db_eng; + + if (gsi_ctx->per.ver >= GSI_VER_2_0) { + if (gsi_ctx->per.ver < GSI_VER_2_5) { + ch_k_qos.use_escape_buf_only = props->prefetch_mode; + } else { + ch_k_qos.prefetch_mode = props->prefetch_mode; + ch_k_qos.empty_lvl_thrshold = + props->empty_lvl_threshold; + if (gsi_ctx->per.ver >= GSI_VER_2_9) + ch_k_qos.db_in_bytes = props->db_in_bytes; + if (gsi_ctx->per.ver >= GSI_VER_3_0) + ch_k_qos.low_latency_en = props->low_latency_en; + } + } + gsihal_write_reg_nk_fields(GSI_EE_n_GSI_CH_k_QOS, + ee, props->ch_id, &ch_k_qos); +} + +static void gsi_program_chan_ctx(struct gsi_chan_props *props, unsigned int ee, + uint8_t erindex) +{ + struct gsihal_reg_ch_k_cntxt_0 ch_k_cntxt_0; + struct gsihal_reg_ch_k_cntxt_1 ch_k_cntxt_1; + + switch (props->prot) { + case GSI_CHAN_PROT_MHI: + case GSI_CHAN_PROT_XHCI: + case GSI_CHAN_PROT_GPI: + case GSI_CHAN_PROT_XDCI: + case GSI_CHAN_PROT_WDI2: + case GSI_CHAN_PROT_WDI3: + case GSI_CHAN_PROT_GCI: + case GSI_CHAN_PROT_MHIP: + case GSI_CHAN_PROT_WDI3_V2: + ch_k_cntxt_0.chtype_protocol_msb = 0; + break; + case GSI_CHAN_PROT_AQC: + case GSI_CHAN_PROT_11AD: + case GSI_CHAN_PROT_RTK: + case GSI_CHAN_PROT_QDSS: + case GSI_CHAN_PROT_NTN: + ch_k_cntxt_0.chtype_protocol_msb = 1; + break; + default: + GSIERR("Unsupported protocol %d\n", props->prot); + WARN_ON(1); + return; + } + + ch_k_cntxt_0.chtype_protocol = props->prot; + ch_k_cntxt_0.chtype_dir = props->dir; + if (gsi_ctx->per.ver >= GSI_VER_3_0) { + ch_k_cntxt_1.erindex = erindex; + } else { + ch_k_cntxt_0.erindex = erindex; + } + ch_k_cntxt_0.element_size = props->re_size; + gsihal_write_reg_nk_fields(GSI_EE_n_GSI_CH_k_CNTXT_0, + ee, props->ch_id, &ch_k_cntxt_0); + + ch_k_cntxt_1.r_length = props->ring_len; + gsihal_write_reg_nk_fields(GSI_EE_n_GSI_CH_k_CNTXT_1, + ee, props->ch_id, &ch_k_cntxt_1); + + gsihal_write_reg_nk(GSI_EE_n_GSI_CH_k_CNTXT_2, + ee, props->ch_id, GSI_LSB(props->ring_base_addr)); + gsihal_write_reg_nk(GSI_EE_n_GSI_CH_k_CNTXT_3, + ee, props->ch_id, GSI_MSB(props->ring_base_addr)); + + gsi_program_chan_ctx_qos(props, ee); +} + +static void gsi_init_chan_ring(struct gsi_chan_props *props, + struct gsi_ring_ctx *ctx) +{ + ctx->base_va = (uintptr_t)props->ring_base_vaddr; + ctx->base = props->ring_base_addr; + ctx->wp = ctx->base; + ctx->rp = ctx->base; + ctx->wp_local = ctx->base; + ctx->rp_local = ctx->base; + ctx->len = props->ring_len; + ctx->elem_sz = props->re_size; + ctx->max_num_elem = ctx->len / ctx->elem_sz - 1; + ctx->end = ctx->base + (ctx->max_num_elem + 1) * + ctx->elem_sz; +} + +static int gsi_validate_channel_props(struct gsi_chan_props *props) +{ + uint64_t ra; + uint64_t last; + + if (props->ch_id >= gsi_ctx->max_ch) { + GSIERR("ch_id %u invalid\n", props->ch_id); + return -GSI_STATUS_INVALID_PARAMS; + } + + if ((props->re_size == GSI_CHAN_RE_SIZE_4B && + props->ring_len % 4) || + (props->re_size == GSI_CHAN_RE_SIZE_8B && + props->ring_len % 8) || + (props->re_size == GSI_CHAN_RE_SIZE_16B && + props->ring_len % 16) || + (props->re_size == GSI_CHAN_RE_SIZE_32B && + props->ring_len % 32) || + (props->re_size == GSI_CHAN_RE_SIZE_64B && + props->ring_len % 64)) { + GSIERR("bad params ring_len %u not a multiple of re size %u\n", + props->ring_len, props->re_size); + return -GSI_STATUS_INVALID_PARAMS; + } + + if (!gsihal_check_ring_length_valid(props->ring_len, props->re_size)) + return -GSI_STATUS_INVALID_PARAMS; + + ra = props->ring_base_addr; + do_div(ra, roundup_pow_of_two(props->ring_len)); + + if (props->ring_base_addr != ra * roundup_pow_of_two(props->ring_len)) { + GSIERR("bad params ring base not aligned 0x%llx align 0x%lx\n", + props->ring_base_addr, + roundup_pow_of_two(props->ring_len)); + return -GSI_STATUS_INVALID_PARAMS; + } + + last = props->ring_base_addr + props->ring_len - props->re_size; + + /* MSB should stay same within the ring */ + if ((props->ring_base_addr & 0xFFFFFFFF00000000ULL) != + (last & 0xFFFFFFFF00000000ULL)) { + GSIERR("MSB is not fixed on ring base 0x%llx size 0x%x\n", + props->ring_base_addr, + props->ring_len); + return -GSI_STATUS_INVALID_PARAMS; + } + + if (props->prot == GSI_CHAN_PROT_GPI && + !props->ring_base_vaddr) { + GSIERR("protocol %u requires ring base VA\n", props->prot); + return -GSI_STATUS_INVALID_PARAMS; + } + + if (props->low_weight > GSI_MAX_CH_LOW_WEIGHT) { + GSIERR("invalid channel low weight %u\n", props->low_weight); + return -GSI_STATUS_INVALID_PARAMS; + } + + if (props->prot == GSI_CHAN_PROT_GPI && !props->xfer_cb) { + GSIERR("xfer callback must be provided\n"); + return -GSI_STATUS_INVALID_PARAMS; + } + + if (!props->err_cb) { + GSIERR("err callback must be provided\n"); + return -GSI_STATUS_INVALID_PARAMS; + } + + return GSI_STATUS_SUCCESS; +} + +int gsi_alloc_channel(struct gsi_chan_props *props, unsigned long dev_hdl, + unsigned long *chan_hdl) +{ + struct gsi_chan_ctx *ctx; + int res; + int ee; + enum gsi_ch_cmd_opcode op = GSI_CH_ALLOCATE; + uint8_t erindex; + struct gsi_user_data *user_data; + size_t user_data_size; + + if (!gsi_ctx) { + pr_err("%s:%d gsi context not allocated\n", __func__, __LINE__); + return -GSI_STATUS_NODEV; + } + + if (!props || !chan_hdl || dev_hdl != (uintptr_t)gsi_ctx) { + GSIERR("bad params props=%pK dev_hdl=0x%lx chan_hdl=%pK\n", + props, dev_hdl, chan_hdl); + return -GSI_STATUS_INVALID_PARAMS; + } + + if (gsi_validate_channel_props(props)) { + GSIERR("bad params\n"); + return -GSI_STATUS_INVALID_PARAMS; + } + + if (props->evt_ring_hdl != ~0) { + if (props->evt_ring_hdl >= gsi_ctx->max_ev) { + GSIERR("invalid evt ring=%lu\n", props->evt_ring_hdl); + return -GSI_STATUS_INVALID_PARAMS; + } + + if (atomic_read( + &gsi_ctx->evtr[props->evt_ring_hdl].chan_ref_cnt) && + gsi_ctx->evtr[props->evt_ring_hdl].props.exclusive && + gsi_ctx->evtr[props->evt_ring_hdl].chan[0]->props.prot != + GSI_CHAN_PROT_GCI) { + GSIERR("evt ring=%lu exclusively used by ch_hdl=%pK\n", + props->evt_ring_hdl, chan_hdl); + return -GSI_STATUS_UNSUPPORTED_OP; + } + } + + ctx = &gsi_ctx->chan[props->ch_id]; + if (ctx->allocated) { + GSIERR("chan %d already allocated\n", props->ch_id); + return -GSI_STATUS_NODEV; + } + memset(ctx, 0, sizeof(*ctx)); + + /* For IPA offloaded WDI channels not required user_data pointer */ + if (props->prot != GSI_CHAN_PROT_WDI2 && + props->prot != GSI_CHAN_PROT_WDI3 && + props->prot != GSI_CHAN_PROT_WDI3_V2) + user_data_size = props->ring_len / props->re_size; + else + user_data_size = props->re_size; + /* + * GCI channels might have OOO event completions up to GSI_VEID_MAX. + * user_data needs to be large enough to accommodate those. + * TODO: increase user data size if GSI_VEID_MAX is not enough + */ + if (props->prot == GSI_CHAN_PROT_GCI) + user_data_size += GSI_VEID_MAX; + + user_data = devm_kzalloc(gsi_ctx->dev, + user_data_size * sizeof(*user_data), + GFP_KERNEL); + if (user_data == NULL) { + GSIERR("context not allocated\n"); + return -GSI_STATUS_RES_ALLOC_FAILURE; + } + + mutex_init(&ctx->mlock); + init_completion(&ctx->compl); + atomic_set(&ctx->poll_mode, GSI_CHAN_MODE_CALLBACK); + ctx->props = *props; + + if (gsi_ctx->per.ver != GSI_VER_2_2) { + struct gsihal_reg_ee_n_gsi_ch_cmd ch_cmd; + + mutex_lock(&gsi_ctx->mlock); + ee = gsi_ctx->per.ee; + gsi_ctx->ch_dbg[props->ch_id].ch_allocate++; + ch_cmd.chid = props->ch_id; + ch_cmd.opcode = op; + gsihal_write_reg_n_fields(GSI_EE_n_GSI_CH_CMD, ee, &ch_cmd); + res = wait_for_completion_timeout(&ctx->compl, GSI_CMD_TIMEOUT); + if (res == 0) { + GSIERR("chan_hdl=%u timed out\n", props->ch_id); + mutex_unlock(&gsi_ctx->mlock); + devm_kfree(gsi_ctx->dev, user_data); + return -GSI_STATUS_TIMED_OUT; + } + if (ctx->state != GSI_CHAN_STATE_ALLOCATED) { + GSIERR("chan_hdl=%u allocation failed state=%d\n", + props->ch_id, ctx->state); + mutex_unlock(&gsi_ctx->mlock); + devm_kfree(gsi_ctx->dev, user_data); + return -GSI_STATUS_RES_ALLOC_FAILURE; + } + mutex_unlock(&gsi_ctx->mlock); + } else { + mutex_lock(&gsi_ctx->mlock); + ctx->state = GSI_CHAN_STATE_ALLOCATED; + mutex_unlock(&gsi_ctx->mlock); + } + erindex = props->evt_ring_hdl != ~0 ? props->evt_ring_hdl : + GSI_NO_EVT_ERINDEX; + if (erindex != GSI_NO_EVT_ERINDEX && erindex >= GSI_EVT_RING_MAX) { + GSIERR("invalid erindex %u\n", erindex); + devm_kfree(gsi_ctx->dev, user_data); + return -GSI_STATUS_INVALID_PARAMS; + } + + if (erindex < GSI_EVT_RING_MAX) { + ctx->evtr = &gsi_ctx->evtr[erindex]; + if(ctx->evtr->num_of_chan_allocated + >= MAX_CHANNELS_SHARING_EVENT_RING) { + GSIERR( + "too many channels sharing the same event ring %u\n", + erindex); + GSI_ASSERT(); + } + if (props->prot != GSI_CHAN_PROT_GCI) { + atomic_inc(&ctx->evtr->chan_ref_cnt); + if (ctx->evtr->props.exclusive) { + if (atomic_read(&ctx->evtr->chan_ref_cnt) == 1) + ctx->evtr->chan + [ctx->evtr->num_of_chan_allocated++] = ctx; + } + else { + ctx->evtr->chan[ctx->evtr->num_of_chan_allocated++] + = ctx; + } + } + } + + gsi_program_chan_ctx(props, gsi_ctx->per.ee, erindex); + + spin_lock_init(&ctx->ring.slock); + gsi_init_chan_ring(props, &ctx->ring); + if (!props->max_re_expected) + ctx->props.max_re_expected = ctx->ring.max_num_elem; + ctx->user_data = user_data; + *chan_hdl = props->ch_id; + ctx->allocated = true; + ctx->stats.dp.last_timestamp = jiffies_to_msecs(jiffies); + atomic_inc(&gsi_ctx->num_chan); + + if (props->prot == GSI_CHAN_PROT_GCI) { + gsi_ctx->coal_info.ch_id = props->ch_id; + gsi_ctx->coal_info.evchid = props->evt_ring_hdl; + } + + return GSI_STATUS_SUCCESS; +} +EXPORT_SYMBOL(gsi_alloc_channel); + +static int gsi_alloc_ap_channel(unsigned int chan_hdl) +{ + struct gsi_chan_ctx *ctx; + struct gsihal_reg_ee_n_gsi_ch_cmd ch_cmd; + int res; + int ee; + enum gsi_ch_cmd_opcode op = GSI_CH_ALLOCATE; + + if (!gsi_ctx) { + pr_err("%s:%d gsi context not allocated\n", __func__, __LINE__); + return -GSI_STATUS_NODEV; + } + + ctx = &gsi_ctx->chan[chan_hdl]; + if (ctx->allocated) { + GSIERR("chan %d already allocated\n", chan_hdl); + return -GSI_STATUS_NODEV; + } + + memset(ctx, 0, sizeof(*ctx)); + + mutex_init(&ctx->mlock); + init_completion(&ctx->compl); + atomic_set(&ctx->poll_mode, GSI_CHAN_MODE_CALLBACK); + + mutex_lock(&gsi_ctx->mlock); + ee = gsi_ctx->per.ee; + gsi_ctx->ch_dbg[chan_hdl].ch_allocate++; + ch_cmd.chid = chan_hdl; + ch_cmd.opcode = op; + gsihal_write_reg_n_fields(GSI_EE_n_GSI_CH_CMD, ee, &ch_cmd); + res = wait_for_completion_timeout(&ctx->compl, GSI_CMD_TIMEOUT); + if (res == 0) { + GSIERR("chan_hdl=%u timed out\n", chan_hdl); + mutex_unlock(&gsi_ctx->mlock); + return -GSI_STATUS_TIMED_OUT; + } + if (ctx->state != GSI_CHAN_STATE_ALLOCATED) { + GSIERR("chan_hdl=%u allocation failed state=%d\n", + chan_hdl, ctx->state); + mutex_unlock(&gsi_ctx->mlock); + return -GSI_STATUS_RES_ALLOC_FAILURE; + } + mutex_unlock(&gsi_ctx->mlock); + + return GSI_STATUS_SUCCESS; +} + +static void __gsi_write_channel_scratch(unsigned long chan_hdl, + union __packed gsi_channel_scratch val) +{ + gsihal_write_reg_nk(GSI_EE_n_GSI_CH_k_SCRATCH_0, + gsi_ctx->per.ee, chan_hdl, val.data.word1); + gsihal_write_reg_nk(GSI_EE_n_GSI_CH_k_SCRATCH_1, + gsi_ctx->per.ee, chan_hdl, val.data.word2); + gsihal_write_reg_nk(GSI_EE_n_GSI_CH_k_SCRATCH_2, + gsi_ctx->per.ee, chan_hdl, val.data.word3); + gsihal_write_reg_nk(GSI_EE_n_GSI_CH_k_SCRATCH_3, + gsi_ctx->per.ee, chan_hdl, val.data.word4); +} + +static void __gsi_write_wdi3_channel_scratch2_reg(unsigned long chan_hdl, + union __packed gsi_wdi3_channel_scratch2_reg val) +{ + gsihal_write_reg_nk(GSI_EE_n_GSI_CH_k_SCRATCH_2, + gsi_ctx->per.ee, chan_hdl, val.data.word1); +} + + +int gsi_write_channel_scratch3_reg(unsigned long chan_hdl, + union __packed gsi_wdi_channel_scratch3_reg val) +{ + struct gsi_chan_ctx *ctx; + + if (!gsi_ctx) { + pr_err("%s:%d gsi context not allocated\n", __func__, __LINE__); + return -GSI_STATUS_NODEV; + } + + if (chan_hdl >= gsi_ctx->max_ch) { + GSIERR("bad params chan_hdl=%lu\n", chan_hdl); + return -GSI_STATUS_INVALID_PARAMS; + } + + ctx = &gsi_ctx->chan[chan_hdl]; + + mutex_lock(&ctx->mlock); + + ctx->scratch.wdi.endp_metadatareg_offset = + val.wdi.endp_metadatareg_offset; + ctx->scratch.wdi.qmap_id = val.wdi.qmap_id; + gsihal_write_reg_nk(GSI_EE_n_GSI_CH_k_SCRATCH_3, + gsi_ctx->per.ee, chan_hdl, val.data.word1); + mutex_unlock(&ctx->mlock); + return GSI_STATUS_SUCCESS; +} +EXPORT_SYMBOL(gsi_write_channel_scratch3_reg); + +int gsi_write_channel_scratch2_reg(unsigned long chan_hdl, + union __packed gsi_wdi2_channel_scratch2_reg val) +{ + struct gsi_chan_ctx *ctx; + + if (!gsi_ctx) { + pr_err("%s:%d gsi context not allocated\n", __func__, __LINE__); + return -GSI_STATUS_NODEV; + } + + if (chan_hdl >= gsi_ctx->max_ch) { + GSIERR("bad params chan_hdl=%lu\n", chan_hdl); + return -GSI_STATUS_INVALID_PARAMS; + } + + ctx = &gsi_ctx->chan[chan_hdl]; + + mutex_lock(&ctx->mlock); + + ctx->scratch.wdi2_new.endp_metadatareg_offset = + val.wdi.endp_metadatareg_offset; + ctx->scratch.wdi2_new.qmap_id = val.wdi.qmap_id; + val.wdi.update_ri_moderation_threshold = + ctx->scratch.wdi2_new.update_ri_moderation_threshold; + gsihal_write_reg_nk(GSI_EE_n_GSI_CH_k_SCRATCH_2, + gsi_ctx->per.ee, chan_hdl, val.data.word1); + mutex_unlock(&ctx->mlock); + return GSI_STATUS_SUCCESS; +} +EXPORT_SYMBOL(gsi_write_channel_scratch2_reg); + +static void __gsi_read_channel_scratch(unsigned long chan_hdl, + union __packed gsi_channel_scratch * val) +{ + val->data.word1 = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_SCRATCH_0, + gsi_ctx->per.ee, chan_hdl); + val->data.word2 = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_SCRATCH_1, + gsi_ctx->per.ee, chan_hdl); + val->data.word3 = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_SCRATCH_2, + gsi_ctx->per.ee, chan_hdl); + val->data.word4 = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_SCRATCH_3, + gsi_ctx->per.ee, chan_hdl); +} + +static void __gsi_read_wdi3_channel_scratch2_reg(unsigned long chan_hdl, + union __packed gsi_wdi3_channel_scratch2_reg * val) +{ + val->data.word1 = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_SCRATCH_2, + gsi_ctx->per.ee, chan_hdl); + +} + +int gsi_write_channel_scratch(unsigned long chan_hdl, + union __packed gsi_channel_scratch val) +{ + struct gsi_chan_ctx *ctx; + + if (!gsi_ctx) { + pr_err("%s:%d gsi context not allocated\n", __func__, __LINE__); + return -GSI_STATUS_NODEV; + } + + if (chan_hdl >= gsi_ctx->max_ch) { + GSIERR("bad params chan_hdl=%lu\n", chan_hdl); + return -GSI_STATUS_INVALID_PARAMS; + } + + if (gsi_ctx->chan[chan_hdl].state != GSI_CHAN_STATE_ALLOCATED && + gsi_ctx->chan[chan_hdl].state != GSI_CHAN_STATE_STOPPED) { + GSIERR("bad state %d\n", + gsi_ctx->chan[chan_hdl].state); + return -GSI_STATUS_UNSUPPORTED_OP; + } + + ctx = &gsi_ctx->chan[chan_hdl]; + + mutex_lock(&ctx->mlock); + ctx->scratch = val; + __gsi_write_channel_scratch(chan_hdl, val); + mutex_unlock(&ctx->mlock); + + return GSI_STATUS_SUCCESS; +} +EXPORT_SYMBOL(gsi_write_channel_scratch); + +int gsi_write_wdi3_channel_scratch2_reg(unsigned long chan_hdl, + union __packed gsi_wdi3_channel_scratch2_reg val) +{ + struct gsi_chan_ctx *ctx; + + if (!gsi_ctx) { + pr_err("%s:%d gsi context not allocated\n", __func__, __LINE__); + return -GSI_STATUS_NODEV; + } + + if (chan_hdl >= gsi_ctx->max_ch) { + GSIERR("bad params chan_hdl=%lu\n", chan_hdl); + return -GSI_STATUS_INVALID_PARAMS; + } + + if (gsi_ctx->chan[chan_hdl].state != GSI_CHAN_STATE_ALLOCATED && + gsi_ctx->chan[chan_hdl].state != GSI_CHAN_STATE_STARTED && + gsi_ctx->chan[chan_hdl].state != GSI_CHAN_STATE_STOPPED) { + GSIERR("bad state %d\n", + gsi_ctx->chan[chan_hdl].state); + return -GSI_STATUS_UNSUPPORTED_OP; + } + + ctx = &gsi_ctx->chan[chan_hdl]; + + mutex_lock(&ctx->mlock); + ctx->scratch.data.word3 = val.data.word1; + __gsi_write_wdi3_channel_scratch2_reg(chan_hdl, val); + mutex_unlock(&ctx->mlock); + + return GSI_STATUS_SUCCESS; +} +EXPORT_SYMBOL(gsi_write_wdi3_channel_scratch2_reg); + + +int gsi_read_channel_scratch(unsigned long chan_hdl, + union __packed gsi_channel_scratch *val) +{ + struct gsi_chan_ctx *ctx; + + if (!gsi_ctx) { + pr_err("%s:%d gsi context not allocated\n", __func__, __LINE__); + return -GSI_STATUS_NODEV; + } + + if (chan_hdl >= gsi_ctx->max_ch) { + GSIERR("bad params chan_hdl=%lu\n", chan_hdl); + return -GSI_STATUS_INVALID_PARAMS; + } + + if (gsi_ctx->chan[chan_hdl].state != GSI_CHAN_STATE_ALLOCATED && + gsi_ctx->chan[chan_hdl].state != GSI_CHAN_STATE_STARTED && + gsi_ctx->chan[chan_hdl].state != GSI_CHAN_STATE_STOPPED) { + GSIERR("bad state %d\n", + gsi_ctx->chan[chan_hdl].state); + return -GSI_STATUS_UNSUPPORTED_OP; + } + + ctx = &gsi_ctx->chan[chan_hdl]; + + mutex_lock(&ctx->mlock); + __gsi_read_channel_scratch(chan_hdl, val); + mutex_unlock(&ctx->mlock); + + return GSI_STATUS_SUCCESS; +} +EXPORT_SYMBOL(gsi_read_channel_scratch); + +int gsi_read_wdi3_channel_scratch2_reg(unsigned long chan_hdl, + union __packed gsi_wdi3_channel_scratch2_reg * val) +{ + struct gsi_chan_ctx *ctx; + + if (!gsi_ctx) { + pr_err("%s:%d gsi context not allocated\n", __func__, __LINE__); + return -GSI_STATUS_NODEV; + } + + if (chan_hdl >= gsi_ctx->max_ch) { + GSIERR("bad params chan_hdl=%lu\n", chan_hdl); + return -GSI_STATUS_INVALID_PARAMS; + } + + if (gsi_ctx->chan[chan_hdl].state != GSI_CHAN_STATE_ALLOCATED && + gsi_ctx->chan[chan_hdl].state != GSI_CHAN_STATE_STARTED && + gsi_ctx->chan[chan_hdl].state != GSI_CHAN_STATE_STOPPED) { + GSIERR("bad state %d\n", + gsi_ctx->chan[chan_hdl].state); + return -GSI_STATUS_UNSUPPORTED_OP; + } + + ctx = &gsi_ctx->chan[chan_hdl]; + + mutex_lock(&ctx->mlock); + __gsi_read_wdi3_channel_scratch2_reg(chan_hdl, val); + mutex_unlock(&ctx->mlock); + + return GSI_STATUS_SUCCESS; +} +EXPORT_SYMBOL(gsi_read_wdi3_channel_scratch2_reg); + + +int gsi_update_mhi_channel_scratch(unsigned long chan_hdl, + struct __packed gsi_mhi_channel_scratch mscr) +{ + struct gsi_chan_ctx *ctx; + + if (!gsi_ctx) { + pr_err("%s:%d gsi context not allocated\n", __func__, __LINE__); + return -GSI_STATUS_NODEV; + } + + if (chan_hdl >= gsi_ctx->max_ch) { + GSIERR("bad params chan_hdl=%lu\n", chan_hdl); + return -GSI_STATUS_INVALID_PARAMS; + } + + if (gsi_ctx->chan[chan_hdl].state != GSI_CHAN_STATE_ALLOCATED && + gsi_ctx->chan[chan_hdl].state != GSI_CHAN_STATE_STOPPED) { + GSIERR("bad state %d\n", + gsi_ctx->chan[chan_hdl].state); + return -GSI_STATUS_UNSUPPORTED_OP; + } + + ctx = &gsi_ctx->chan[chan_hdl]; + + mutex_lock(&ctx->mlock); + ctx->scratch = __gsi_update_mhi_channel_scratch(chan_hdl, mscr); + mutex_unlock(&ctx->mlock); + + return GSI_STATUS_SUCCESS; +} +EXPORT_SYMBOL(gsi_update_mhi_channel_scratch); + +int gsi_query_channel_db_addr(unsigned long chan_hdl, + uint32_t *db_addr_wp_lsb, uint32_t *db_addr_wp_msb) +{ + if (!gsi_ctx) { + pr_err("%s:%d gsi context not allocated\n", __func__, __LINE__); + return -GSI_STATUS_NODEV; + } + + if (!db_addr_wp_msb || !db_addr_wp_lsb) { + GSIERR("bad params msb=%pK lsb=%pK\n", db_addr_wp_msb, + db_addr_wp_lsb); + return -GSI_STATUS_INVALID_PARAMS; + } + + if (chan_hdl >= gsi_ctx->max_ch) { + GSIERR("bad params chan_hdl=%lu\n", chan_hdl); + return -GSI_STATUS_INVALID_PARAMS; + } + + if (gsi_ctx->chan[chan_hdl].state == GSI_CHAN_STATE_NOT_ALLOCATED) { + GSIERR("bad state %d\n", + gsi_ctx->chan[chan_hdl].state); + return -GSI_STATUS_UNSUPPORTED_OP; + } + + *db_addr_wp_lsb = gsi_ctx->per.phys_addr + + gsihal_get_reg_nk_ofst(GSI_EE_n_GSI_CH_k_DOORBELL_0, + gsi_ctx->per.ee, chan_hdl); + *db_addr_wp_msb = gsi_ctx->per.phys_addr + + gsihal_get_reg_nk_ofst(GSI_EE_n_GSI_CH_k_DOORBELL_1, + gsi_ctx->per.ee, chan_hdl); + + return GSI_STATUS_SUCCESS; +} +EXPORT_SYMBOL(gsi_query_channel_db_addr); + +int gsi_pending_irq_type(void) +{ + int ee = gsi_ctx->per.ee; + + return gsihal_read_reg_n(GSI_EE_n_CNTXT_TYPE_IRQ, ee); +} +EXPORT_SYMBOL(gsi_pending_irq_type); + +int gsi_start_channel(unsigned long chan_hdl) +{ + enum gsi_ch_cmd_opcode op = GSI_CH_START; + uint32_t val; + struct gsihal_reg_ee_n_gsi_ch_cmd ch_cmd; + struct gsi_chan_ctx *ctx; + + if (!gsi_ctx) { + pr_err("%s:%d gsi context not allocated\n", __func__, __LINE__); + return -GSI_STATUS_NODEV; + } + + if (chan_hdl >= gsi_ctx->max_ch) { + GSIERR("bad params chan_hdl=%lu\n", chan_hdl); + return -GSI_STATUS_INVALID_PARAMS; + } + + ctx = &gsi_ctx->chan[chan_hdl]; + + if (ctx->state == GSI_CHAN_STATE_STARTED) { + GSIDBG("chan_hdl=%lu already in started state\n", chan_hdl); + return GSI_STATUS_SUCCESS; + } + + if (ctx->state != GSI_CHAN_STATE_ALLOCATED && + ctx->state != GSI_CHAN_STATE_STOP_IN_PROC && + ctx->state != GSI_CHAN_STATE_STOPPED) { + GSIERR("bad state %d\n", ctx->state); + return -GSI_STATUS_UNSUPPORTED_OP; + } + + mutex_lock(&gsi_ctx->mlock); + reinit_completion(&ctx->compl); + + /* check if INTSET is in IRQ mode for GPI channel */ + val = gsihal_read_reg_n(GSI_EE_n_CNTXT_INTSET, gsi_ctx->per.ee); + if (ctx->evtr && + ctx->evtr->props.intf == GSI_EVT_CHTYPE_GPI_EV && + val != GSI_INTR_IRQ) { + GSIERR("GSI_EE_n_CNTXT_INTSET %d\n", val); + BUG(); + } + + gsi_ctx->ch_dbg[chan_hdl].ch_start++; + ch_cmd.chid = chan_hdl; + ch_cmd.opcode = op; + gsihal_write_reg_n_fields(GSI_EE_n_GSI_CH_CMD, + gsi_ctx->per.ee, &ch_cmd); + GSIDBG("GSI Channel Start, waiting for completion\n"); + gsi_channel_state_change_wait(chan_hdl, + ctx, + GSI_START_CMD_TIMEOUT_MS, op); + + if (ctx->state != GSI_CHAN_STATE_STARTED && + ctx->state != GSI_CHAN_STATE_FLOW_CONTROL) { + /* + * Hardware returned unexpected status, unexpected + * hardware state. + */ + GSIERR("chan=%lu timed out, unexpected state=%u\n", + chan_hdl, ctx->state); + gsi_dump_ch_info(chan_hdl); + GSI_ASSERT(); + } + + GSIDBG("GSI Channel=%lu Start success\n", chan_hdl); + + /* write order MUST be MSB followed by LSB */ + gsihal_write_reg_nk(GSI_EE_n_GSI_CH_k_DOORBELL_1, + gsi_ctx->per.ee, ctx->props.ch_id, GSI_MSB(ctx->ring.wp_local)); + + mutex_unlock(&gsi_ctx->mlock); + + return GSI_STATUS_SUCCESS; +} +EXPORT_SYMBOL(gsi_start_channel); + +void gsi_dump_ch_info(unsigned long chan_hdl) +{ + uint32_t val; + + if (!gsi_ctx) { + pr_err("%s:%d gsi context not allocated\n", __func__, __LINE__); + return; + } + + if (chan_hdl >= gsi_ctx->max_ch) { + GSIDBG("invalid chan id %u\n", chan_hdl); + return; + } + + val = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_CNTXT_0, + gsi_ctx->per.ee, chan_hdl); + GSIERR("CH%2d CTX0 0x%x\n", chan_hdl, val); + val = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_CNTXT_1, + gsi_ctx->per.ee, chan_hdl); + GSIERR("CH%2d CTX1 0x%x\n", chan_hdl, val); + val = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_CNTXT_2, + gsi_ctx->per.ee, chan_hdl); + GSIERR("CH%2d CTX2 0x%x\n", chan_hdl, val); + val = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_CNTXT_3, + gsi_ctx->per.ee, chan_hdl); + GSIERR("CH%2d CTX3 0x%x\n", chan_hdl, val); + val = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_CNTXT_4, + gsi_ctx->per.ee, chan_hdl); + GSIERR("CH%2d CTX4 0x%x\n", chan_hdl, val); + val = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_CNTXT_5, + gsi_ctx->per.ee, chan_hdl); + GSIERR("CH%2d CTX5 0x%x\n", chan_hdl, val); + val = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_CNTXT_6, + gsi_ctx->per.ee, chan_hdl); + GSIERR("CH%2d CTX6 0x%x\n", chan_hdl, val); + val = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_CNTXT_7, + gsi_ctx->per.ee, chan_hdl); + GSIERR("CH%2d CTX7 0x%x\n", chan_hdl, val); + if (gsi_ctx->per.ver >= GSI_VER_3_0) { + val = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_CNTXT_8, + gsi_ctx->per.ee, chan_hdl); + GSIERR("CH%2d CTX8 0x%x\n", chan_hdl, val); + } + val = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_RE_FETCH_READ_PTR, + gsi_ctx->per.ee, chan_hdl); + GSIERR("CH%2d REFRP 0x%x\n", chan_hdl, val); + val = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR, + gsi_ctx->per.ee, chan_hdl); + GSIERR("CH%2d REFWP 0x%x\n", chan_hdl, val); + val = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_QOS, + gsi_ctx->per.ee, chan_hdl); + GSIERR("CH%2d QOS 0x%x\n", chan_hdl, val); + val = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_SCRATCH_0, + gsi_ctx->per.ee, chan_hdl); + GSIERR("CH%2d SCR0 0x%x\n", chan_hdl, val); + val = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_SCRATCH_1, + gsi_ctx->per.ee, chan_hdl); + GSIERR("CH%2d SCR1 0x%x\n", chan_hdl, val); + val = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_SCRATCH_2, + gsi_ctx->per.ee, chan_hdl); + GSIERR("CH%2d SCR2 0x%x\n", chan_hdl, val); + val = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_SCRATCH_3, + gsi_ctx->per.ee, chan_hdl); + GSIERR("CH%2d SCR3 0x%x\n", chan_hdl, val); + if (gsi_ctx->per.ver >= GSI_VER_3_0) { + val = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_SCRATCH_4, + gsi_ctx->per.ee, chan_hdl); + GSIERR("CH%2d SCR4 0x%x\n", chan_hdl, val); + val = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_SCRATCH_5, + gsi_ctx->per.ee, chan_hdl); + GSIERR("CH%2d SCR5 0x%x\n", chan_hdl, val); + val = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_SCRATCH_6, + gsi_ctx->per.ee, chan_hdl); + GSIERR("CH%2d SCR6 0x%x\n", chan_hdl, val); + val = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_SCRATCH_7, + gsi_ctx->per.ee, chan_hdl); + GSIERR("CH%2d SCR7 0x%x\n", chan_hdl, val); + val = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_SCRATCH_8, + gsi_ctx->per.ee, chan_hdl); + GSIERR("CH%2d SCR8 0x%x\n", chan_hdl, val); + val = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_SCRATCH_9, + gsi_ctx->per.ee, chan_hdl); + GSIERR("CH%2d SCR9 0x%x\n", chan_hdl, val); + } + + return; +} +EXPORT_SYMBOL(gsi_dump_ch_info); + +int gsi_stop_channel(unsigned long chan_hdl) +{ + enum gsi_ch_cmd_opcode op = GSI_CH_STOP; + int res; + uint32_t val; + struct gsihal_reg_ee_n_gsi_ch_cmd ch_cmd; + struct gsi_chan_ctx *ctx; + unsigned long flags; + + if (!gsi_ctx) { + pr_err("%s:%d gsi context not allocated\n", __func__, __LINE__); + return -GSI_STATUS_NODEV; + } + + if (chan_hdl >= gsi_ctx->max_ch) { + GSIERR("bad params chan_hdl=%lu\n", chan_hdl); + return -GSI_STATUS_INVALID_PARAMS; + } + + ctx = &gsi_ctx->chan[chan_hdl]; + + if (ctx->state == GSI_CHAN_STATE_STOPPED) { + GSIDBG("chan_hdl=%lu already stopped\n", chan_hdl); + return GSI_STATUS_SUCCESS; + } + + if (ctx->state != GSI_CHAN_STATE_STARTED && + ctx->state != GSI_CHAN_STATE_STOP_IN_PROC && + ctx->state != GSI_CHAN_STATE_ERROR) { + GSIERR("bad state %d\n", ctx->state); + return -GSI_STATUS_UNSUPPORTED_OP; + } + + mutex_lock(&gsi_ctx->mlock); + reinit_completion(&ctx->compl); + + /* check if INTSET is in IRQ mode for GPI channel */ + val = gsihal_read_reg_n(GSI_EE_n_CNTXT_INTSET, gsi_ctx->per.ee); + if (ctx->evtr && + ctx->evtr->props.intf == GSI_EVT_CHTYPE_GPI_EV && + val != GSI_INTR_IRQ) { + GSIERR("GSI_EE_n_CNTXT_INTSET %d\n", val); + BUG(); + } + + gsi_ctx->ch_dbg[chan_hdl].ch_stop++; + ch_cmd.chid = chan_hdl; + ch_cmd.opcode = op; + gsihal_write_reg_n_fields(GSI_EE_n_GSI_CH_CMD, + gsi_ctx->per.ee, &ch_cmd); + + GSIDBG("GSI Channel Stop, waiting for completion: 0x%x\n", val); + gsi_channel_state_change_wait(chan_hdl, + ctx, + GSI_STOP_CMD_TIMEOUT_MS, op); + + if (ctx->state != GSI_CHAN_STATE_STOPPED && + ctx->state != GSI_CHAN_STATE_STOP_IN_PROC) { + GSIERR("chan=%lu unexpected state=%u\n", chan_hdl, ctx->state); + gsi_dump_ch_info(chan_hdl); + res = -GSI_STATUS_BAD_STATE; + BUG(); + goto free_lock; + } + + if (ctx->state == GSI_CHAN_STATE_STOP_IN_PROC) { + GSIERR("chan=%lu busy try again\n", chan_hdl); + res = -GSI_STATUS_AGAIN; + goto free_lock; + } + + /* If channel is stopped succesfully and has an event with IRQ type MSI + - clear IEOB */ + if (ctx->evtr && ctx->evtr->props.intr == GSI_INTR_MSI) { + spin_lock_irqsave(&ctx->evtr->ring.slock, flags); + if (gsi_ctx->per.ver >= GSI_VER_3_0) { + gsihal_write_reg_nk(GSI_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_k, + gsi_ctx->per.ee, gsihal_get_ch_reg_idx(ctx->evtr->id), + gsihal_get_ch_reg_mask(ctx->evtr->id)); + } else { + gsihal_write_reg_n(GSI_EE_n_CNTXT_SRC_IEOB_IRQ_CLR, + gsi_ctx->per.ee, 1 << ctx->evtr->id); + } + spin_unlock_irqrestore(&ctx->evtr->ring.slock, flags); + } + + res = GSI_STATUS_SUCCESS; + +free_lock: + mutex_unlock(&gsi_ctx->mlock); + return res; +} +EXPORT_SYMBOL(gsi_stop_channel); + +int gsi_stop_db_channel(unsigned long chan_hdl) +{ + enum gsi_ch_cmd_opcode op = GSI_CH_DB_STOP; + int res; + struct gsihal_reg_ee_n_gsi_ch_cmd ch_cmd; + struct gsi_chan_ctx *ctx; + + if (!gsi_ctx) { + pr_err("%s:%d gsi context not allocated\n", __func__, __LINE__); + return -GSI_STATUS_NODEV; + } + + if (chan_hdl >= gsi_ctx->max_ch) { + GSIERR("bad params chan_hdl=%lu\n", chan_hdl); + return -GSI_STATUS_INVALID_PARAMS; + } + + ctx = &gsi_ctx->chan[chan_hdl]; + + if (ctx->state == GSI_CHAN_STATE_STOPPED) { + GSIDBG("chan_hdl=%lu already stopped\n", chan_hdl); + return GSI_STATUS_SUCCESS; + } + + if (ctx->state != GSI_CHAN_STATE_STARTED && + ctx->state != GSI_CHAN_STATE_STOP_IN_PROC) { + GSIERR("bad state %d\n", ctx->state); + return -GSI_STATUS_UNSUPPORTED_OP; + } + + mutex_lock(&gsi_ctx->mlock); + reinit_completion(&ctx->compl); + + gsi_ctx->ch_dbg[chan_hdl].ch_db_stop++; + ch_cmd.chid = chan_hdl; + ch_cmd.opcode = op; + gsihal_write_reg_n_fields(GSI_EE_n_GSI_CH_CMD, + gsi_ctx->per.ee, &ch_cmd); + res = wait_for_completion_timeout(&ctx->compl, + msecs_to_jiffies(GSI_STOP_CMD_TIMEOUT_MS)); + if (res == 0) { + GSIERR("chan_hdl=%lu timed out\n", chan_hdl); + res = -GSI_STATUS_TIMED_OUT; + goto free_lock; + } + + if (ctx->state != GSI_CHAN_STATE_STOPPED && + ctx->state != GSI_CHAN_STATE_STOP_IN_PROC) { + GSIERR("chan=%lu unexpected state=%u\n", chan_hdl, ctx->state); + res = -GSI_STATUS_BAD_STATE; + goto free_lock; + } + + if (ctx->state == GSI_CHAN_STATE_STOP_IN_PROC) { + GSIERR("chan=%lu busy try again\n", chan_hdl); + res = -GSI_STATUS_AGAIN; + goto free_lock; + } + + res = GSI_STATUS_SUCCESS; + +free_lock: + mutex_unlock(&gsi_ctx->mlock); + return res; +} +EXPORT_SYMBOL(gsi_stop_db_channel); + +int gsi_reset_channel(unsigned long chan_hdl) +{ + enum gsi_ch_cmd_opcode op = GSI_CH_RESET; + int res; + struct gsihal_reg_ee_n_gsi_ch_cmd ch_cmd; + struct gsi_chan_ctx *ctx; + bool reset_done = false; + uint32_t retry_cnt = 0; + + if (!gsi_ctx) { + pr_err("%s:%d gsi context not allocated\n", __func__, __LINE__); + return -GSI_STATUS_NODEV; + } + + if (chan_hdl >= gsi_ctx->max_ch) { + GSIERR("bad params chan_hdl=%lu\n", chan_hdl); + return -GSI_STATUS_INVALID_PARAMS; + } + + ctx = &gsi_ctx->chan[chan_hdl]; + + /* + * In WDI3 case, if SAP enabled but no client connected, + * GSI will be in allocated state. When SAP disabled, + * gsi_reset_channel will be called and reset is needed. + */ + if (ctx->state != GSI_CHAN_STATE_STOPPED && + ctx->state != GSI_CHAN_STATE_ALLOCATED) { + GSIERR("bad state %d\n", ctx->state); + return -GSI_STATUS_UNSUPPORTED_OP; + } + + mutex_lock(&gsi_ctx->mlock); + +reset: + reinit_completion(&ctx->compl); + gsi_ctx->ch_dbg[chan_hdl].ch_reset++; + ch_cmd.chid = chan_hdl; + ch_cmd.opcode = op; + gsihal_write_reg_n_fields(GSI_EE_n_GSI_CH_CMD, + gsi_ctx->per.ee, &ch_cmd); + res = wait_for_completion_timeout(&ctx->compl, GSI_CMD_TIMEOUT); + if (res == 0) { + GSIERR("chan_hdl=%lu timed out\n", chan_hdl); + mutex_unlock(&gsi_ctx->mlock); + return -GSI_STATUS_TIMED_OUT; + } + +revrfy_chnlstate: + if (ctx->state != GSI_CHAN_STATE_ALLOCATED) { + GSIERR("chan_hdl=%lu unexpected state=%u\n", chan_hdl, + ctx->state); + /* GSI register update state not sync with gsi channel + * context state not sync, need to wait for 1ms to sync. + */ + retry_cnt++; + if (retry_cnt <= GSI_CHNL_STATE_MAX_RETRYCNT) { + usleep_range(GSI_RESET_WA_MIN_SLEEP, + GSI_RESET_WA_MAX_SLEEP); + goto revrfy_chnlstate; + } + /* + * Hardware returned incorrect state, unexpected + * hardware state. + */ + GSI_ASSERT(); + } + + /* Hardware issue fixed from GSI 2.0 and no need for the WA */ + if (gsi_ctx->per.ver >= GSI_VER_2_0) + reset_done = true; + + /* workaround: reset GSI producers again */ + if (ctx->props.dir == GSI_CHAN_DIR_FROM_GSI && !reset_done) { + usleep_range(GSI_RESET_WA_MIN_SLEEP, GSI_RESET_WA_MAX_SLEEP); + reset_done = true; + goto reset; + } + + if (ctx->props.cleanup_cb) + gsi_cleanup_xfer_user_data(chan_hdl, ctx->props.cleanup_cb); + + gsi_program_chan_ctx(&ctx->props, gsi_ctx->per.ee, + ctx->evtr ? ctx->evtr->id : GSI_NO_EVT_ERINDEX); + gsi_init_chan_ring(&ctx->props, &ctx->ring); + + /* restore scratch */ + __gsi_write_channel_scratch(chan_hdl, ctx->scratch); + + mutex_unlock(&gsi_ctx->mlock); + + return GSI_STATUS_SUCCESS; +} +EXPORT_SYMBOL(gsi_reset_channel); + +int gsi_dealloc_channel(unsigned long chan_hdl) +{ + enum gsi_ch_cmd_opcode op = GSI_CH_DE_ALLOC; + int res; + struct gsihal_reg_ee_n_gsi_ch_cmd ch_cmd; + struct gsi_chan_ctx *ctx; + + if (!gsi_ctx) { + pr_err("%s:%d gsi context not allocated\n", __func__, __LINE__); + return -GSI_STATUS_NODEV; + } + + if (chan_hdl >= gsi_ctx->max_ch) { + GSIERR("bad params chan_hdl=%lu\n", chan_hdl); + return -GSI_STATUS_INVALID_PARAMS; + } + + ctx = &gsi_ctx->chan[chan_hdl]; + + if (ctx->state != GSI_CHAN_STATE_ALLOCATED) { + GSIERR("bad state %d\n", ctx->state); + return -GSI_STATUS_UNSUPPORTED_OP; + } + + /*In GSI_VER_2_2 version deallocation channel not supported*/ + if (gsi_ctx->per.ver != GSI_VER_2_2) { + mutex_lock(&gsi_ctx->mlock); + reinit_completion(&ctx->compl); + + gsi_ctx->ch_dbg[chan_hdl].ch_de_alloc++; + ch_cmd.chid = chan_hdl; + ch_cmd.opcode = op; + gsihal_write_reg_n_fields(GSI_EE_n_GSI_CH_CMD, + gsi_ctx->per.ee, &ch_cmd); + res = wait_for_completion_timeout(&ctx->compl, GSI_CMD_TIMEOUT); + if (res == 0) { + GSIERR("chan_hdl=%lu timed out\n", chan_hdl); + mutex_unlock(&gsi_ctx->mlock); + return -GSI_STATUS_TIMED_OUT; + } + if (ctx->state != GSI_CHAN_STATE_NOT_ALLOCATED) { + GSIERR("chan_hdl=%lu unexpected state=%u\n", chan_hdl, + ctx->state); + /* Hardware returned incorrect value */ + GSI_ASSERT(); + } + + mutex_unlock(&gsi_ctx->mlock); + } else { + mutex_lock(&gsi_ctx->mlock); + GSIDBG("In GSI_VER_2_2 channel deallocation not supported\n"); + ctx->state = GSI_CHAN_STATE_NOT_ALLOCATED; + GSIDBG("chan_hdl=%lu Channel state = %u\n", chan_hdl, + ctx->state); + mutex_unlock(&gsi_ctx->mlock); + } + devm_kfree(gsi_ctx->dev, ctx->user_data); + ctx->allocated = false; + if (ctx->evtr && (ctx->props.prot != GSI_CHAN_PROT_GCI)) { + atomic_dec(&ctx->evtr->chan_ref_cnt); + ctx->evtr->num_of_chan_allocated--; + } + atomic_dec(&gsi_ctx->num_chan); + + if (ctx->props.prot == GSI_CHAN_PROT_GCI) { + gsi_ctx->coal_info.ch_id = GSI_CHAN_MAX; + gsi_ctx->coal_info.evchid = GSI_EVT_RING_MAX; + } + return GSI_STATUS_SUCCESS; +} +EXPORT_SYMBOL(gsi_dealloc_channel); + +void gsi_update_ch_dp_stats(struct gsi_chan_ctx *ctx, uint16_t used) +{ + unsigned long now = jiffies_to_msecs(jiffies); + unsigned long elapsed; + + if (used == 0) { + elapsed = now - ctx->stats.dp.last_timestamp; + if (ctx->stats.dp.empty_time < elapsed) + ctx->stats.dp.empty_time = elapsed; + } + + if (used <= ctx->props.max_re_expected / 3) + ++ctx->stats.dp.ch_below_lo; + else if (used <= 2 * ctx->props.max_re_expected / 3) + ++ctx->stats.dp.ch_below_hi; + else + ++ctx->stats.dp.ch_above_hi; + ctx->stats.dp.last_timestamp = now; +} + +static void __gsi_query_channel_free_re(struct gsi_chan_ctx *ctx, + uint16_t *num_free_re) +{ + uint16_t start; + uint16_t end; + uint64_t rp; + int ee = gsi_ctx->per.ee; + uint16_t used; + + WARN_ON(ctx->props.prot != GSI_CHAN_PROT_GPI); + + if (!ctx->evtr) { + rp = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_CNTXT_4, + ee, ctx->props.ch_id); + rp |= ctx->ring.rp & GSI_MSB_MASK; + ctx->ring.rp = rp; + } else { + rp = ctx->ring.rp_local; + } + + start = gsi_find_idx_from_addr(&ctx->ring, rp); + end = gsi_find_idx_from_addr(&ctx->ring, ctx->ring.wp_local); + + if (end >= start) + used = end - start; + else + used = ctx->ring.max_num_elem + 1 - (start - end); + + *num_free_re = ctx->ring.max_num_elem - used; +} + +int gsi_query_channel_info(unsigned long chan_hdl, + struct gsi_chan_info *info) +{ + struct gsi_chan_ctx *ctx; + spinlock_t *slock; + unsigned long flags; + uint64_t rp; + uint64_t wp; + int ee; + + if (!gsi_ctx) { + pr_err("%s:%d gsi context not allocated\n", __func__, __LINE__); + return -GSI_STATUS_NODEV; + } + + if (chan_hdl >= gsi_ctx->max_ch || !info) { + GSIERR("bad params chan_hdl=%lu info=%pK\n", chan_hdl, info); + return -GSI_STATUS_INVALID_PARAMS; + } + + ctx = &gsi_ctx->chan[chan_hdl]; + if (ctx->evtr) { + slock = &ctx->evtr->ring.slock; + info->evt_valid = true; + } else { + slock = &ctx->ring.slock; + info->evt_valid = false; + } + + spin_lock_irqsave(slock, flags); + + ee = gsi_ctx->per.ee; + rp = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_CNTXT_4, + ee, ctx->props.ch_id); + rp |= ((uint64_t)gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_CNTXT_5, + ee, ctx->props.ch_id)) << 32; + ctx->ring.rp = rp; + info->rp = rp; + + wp = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_CNTXT_6, + ee, ctx->props.ch_id); + wp |= ((uint64_t)gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_CNTXT_7, + ee, ctx->props.ch_id)) << 32; + ctx->ring.wp = wp; + info->wp = wp; + + if (info->evt_valid) { + rp = gsihal_read_reg_nk(GSI_EE_n_EV_CH_k_CNTXT_4, + ee, ctx->evtr->id); + rp |= ((uint64_t)gsihal_read_reg_nk(GSI_EE_n_EV_CH_k_CNTXT_5, + ee, ctx->evtr->id)) << 32; + info->evt_rp = rp; + + wp = gsihal_read_reg_nk(GSI_EE_n_EV_CH_k_CNTXT_6, + ee, ctx->evtr->id); + wp |= ((uint64_t)gsihal_read_reg_nk(GSI_EE_n_EV_CH_k_CNTXT_7, + ee, ctx->evtr->id)) << 32; + info->evt_wp = wp; + } + + spin_unlock_irqrestore(slock, flags); + + GSIDBG("ch=%lu RP=0x%llx WP=0x%llx ev_valid=%d ERP=0x%llx EWP=0x%llx\n", + chan_hdl, info->rp, info->wp, + info->evt_valid, info->evt_rp, info->evt_wp); + + return GSI_STATUS_SUCCESS; +} +EXPORT_SYMBOL(gsi_query_channel_info); + +int gsi_is_channel_empty(unsigned long chan_hdl, bool *is_empty) +{ + struct gsi_chan_ctx *ctx; + struct gsi_evt_ctx *ev_ctx; + spinlock_t *slock; + unsigned long flags; + uint64_t rp; + uint64_t wp; + uint64_t rp_local; + int ee; + + if (!gsi_ctx) { + pr_err("%s:%d gsi context not allocated\n", __func__, __LINE__); + return -GSI_STATUS_NODEV; + } + + if (chan_hdl >= gsi_ctx->max_ch || !is_empty) { + GSIERR("bad params chan_hdl=%lu is_empty=%pK\n", + chan_hdl, is_empty); + return -GSI_STATUS_INVALID_PARAMS; + } + + ctx = &gsi_ctx->chan[chan_hdl]; + ee = gsi_ctx->per.ee; + + if (ctx->props.prot != GSI_CHAN_PROT_GPI && + ctx->props.prot != GSI_CHAN_PROT_GCI) { + GSIERR("op not supported for protocol %u\n", ctx->props.prot); + return -GSI_STATUS_UNSUPPORTED_OP; + } + + if (ctx->evtr) + slock = &ctx->evtr->ring.slock; + else + slock = &ctx->ring.slock; + + spin_lock_irqsave(slock, flags); + + if (ctx->props.dir == GSI_CHAN_DIR_FROM_GSI && ctx->evtr) { + ev_ctx = &gsi_ctx->evtr[ctx->evtr->id]; + /* Read the event ring rp from DDR to avoid mismatch */ + rp = ev_ctx->props.gsi_read_event_ring_rp(&ev_ctx->props, + ev_ctx->id, ee); + + rp |= ctx->evtr->ring.rp & GSI_MSB_MASK; + ctx->evtr->ring.rp = rp; + + wp = gsihal_read_reg_nk(GSI_EE_n_EV_CH_k_CNTXT_6, + ee, ctx->evtr->id); + wp |= ctx->evtr->ring.wp & GSI_MSB_MASK; + ctx->evtr->ring.wp = wp; + + rp_local = ctx->evtr->ring.rp_local; + } else { + rp = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_CNTXT_4, + ee, ctx->props.ch_id); + rp |= ctx->ring.rp & GSI_MSB_MASK; + ctx->ring.rp = rp; + + wp = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_CNTXT_6, + ee, ctx->props.ch_id); + wp |= ctx->ring.wp & GSI_MSB_MASK; + ctx->ring.wp = wp; + + rp_local = ctx->ring.rp_local; + } + + if (ctx->props.dir == GSI_CHAN_DIR_FROM_GSI) + *is_empty = (rp_local == rp) ? true : false; + else + *is_empty = (wp == rp) ? true : false; + + spin_unlock_irqrestore(slock, flags); + + if (ctx->props.dir == GSI_CHAN_DIR_FROM_GSI && ctx->evtr) + GSIDBG("ch=%ld ev=%d RP=0x%llx WP=0x%llx RP_LOCAL=0x%llx\n", + chan_hdl, ctx->evtr->id, rp, wp, rp_local); + else + GSIDBG("ch=%lu RP=0x%llx WP=0x%llx RP_LOCAL=0x%llx\n", + chan_hdl, rp, wp, rp_local); + + return GSI_STATUS_SUCCESS; +} +EXPORT_SYMBOL(gsi_is_channel_empty); + +bool gsi_is_event_pending(unsigned long chan_hdl) { + struct gsi_chan_ctx *ctx; + uint64_t rp; + uint64_t rp_local; + int ee; + + if (chan_hdl >= gsi_ctx->max_ch) { + GSIERR("bad params chan_hdl=%lu\n", chan_hdl); + return false; + } + + ctx = &gsi_ctx->chan[chan_hdl]; + ee = gsi_ctx->per.ee; + + /* read only, updating will be handled in NAPI context if needed */ + rp = ctx->evtr->props.gsi_read_event_ring_rp( + &ctx->evtr->props, ctx->evtr->id, ee); + rp |= ctx->evtr->ring.rp & GSI_MSB_MASK; + rp_local = ctx->evtr->ring.rp_local; + + return rp != rp_local; +} +EXPORT_SYMBOL(gsi_is_event_pending); + +int __gsi_get_gci_cookie(struct gsi_chan_ctx *ctx, uint16_t idx) +{ + int i; + int end; + + if (!ctx->user_data[idx].valid) { + ctx->user_data[idx].valid = true; + return idx; + } + + /* + * at this point we need to find an "escape buffer" for the cookie + * as the userdata in this spot is in use. This happens if the TRE at + * idx is not completed yet and it is getting reused by a new TRE. + */ + ctx->stats.userdata_in_use++; + end = ctx->ring.max_num_elem + 1; + for (i = 0; i < GSI_VEID_MAX; i++) { + if (!ctx->user_data[end + i].valid) { + ctx->user_data[end + i].valid = true; + return end + i; + } + } + + /* Go over original userdata when escape buffer is full (costly) */ + GSIDBG("escape buffer is full\n"); + for (i = 0; i < end; i++) { + if (!ctx->user_data[i].valid) { + ctx->user_data[i].valid = true; + return i; + } + } + + /* Everything is full (possibly a stall) */ + GSIERR("both userdata array and escape buffer is full\n"); + BUG(); + return 0xFFFF; +} + +int __gsi_populate_gci_tre(struct gsi_chan_ctx *ctx, + struct gsi_xfer_elem *xfer) +{ + struct gsi_gci_tre gci_tre; + struct gsi_gci_tre *tre_gci_ptr; + uint16_t idx; + + memset(&gci_tre, 0, sizeof(gci_tre)); + if (xfer->addr & 0xFFFFFF0000000000) { + GSIERR("chan_hdl=%u add too large=%llx\n", + ctx->props.ch_id, xfer->addr); + return -EINVAL; + } + + if (xfer->type != GSI_XFER_ELEM_DATA) { + GSIERR("chan_hdl=%u bad RE type=%u\n", ctx->props.ch_id, + xfer->type); + return -EINVAL; + } + + idx = gsi_find_idx_from_addr(&ctx->ring, ctx->ring.wp_local); + tre_gci_ptr = (struct gsi_gci_tre *)(ctx->ring.base_va + + idx * ctx->ring.elem_sz); + + gci_tre.buffer_ptr = xfer->addr; + gci_tre.buf_len = xfer->len; + gci_tre.re_type = GSI_RE_COAL; + gci_tre.cookie = __gsi_get_gci_cookie(ctx, idx); + if (gci_tre.cookie > (ctx->ring.max_num_elem + GSI_VEID_MAX)) + return -EPERM; + + /* write the TRE to ring */ + *tre_gci_ptr = gci_tre; + ctx->user_data[gci_tre.cookie].p = xfer->xfer_user_data; + + return 0; +} + +int __gsi_populate_tre(struct gsi_chan_ctx *ctx, + struct gsi_xfer_elem *xfer) +{ + struct gsi_tre tre; + struct gsi_tre *tre_ptr; + uint16_t idx; + + memset(&tre, 0, sizeof(tre)); + tre.buffer_ptr = xfer->addr; + tre.buf_len = xfer->len; + if (xfer->type == GSI_XFER_ELEM_DATA) { + tre.re_type = GSI_RE_XFER; + } else if (xfer->type == GSI_XFER_ELEM_IMME_CMD) { + tre.re_type = GSI_RE_IMMD_CMD; + } else if (xfer->type == GSI_XFER_ELEM_NOP) { + tre.re_type = GSI_RE_NOP; + } else { + GSIERR("chan_hdl=%u bad RE type=%u\n", ctx->props.ch_id, + xfer->type); + return -EINVAL; + } + + tre.bei = (xfer->flags & GSI_XFER_FLAG_BEI) ? 1 : 0; + tre.ieot = (xfer->flags & GSI_XFER_FLAG_EOT) ? 1 : 0; + tre.ieob = (xfer->flags & GSI_XFER_FLAG_EOB) ? 1 : 0; + tre.chain = (xfer->flags & GSI_XFER_FLAG_CHAIN) ? 1 : 0; + + if (unlikely(ctx->state == GSI_CHAN_STATE_NOT_ALLOCATED)) { + GSIERR("bad state %d\n", ctx->state); + return -GSI_STATUS_UNSUPPORTED_OP; + } + + idx = gsi_find_idx_from_addr(&ctx->ring, ctx->ring.wp_local); + tre_ptr = (struct gsi_tre *)(ctx->ring.base_va + + idx * ctx->ring.elem_sz); + + /* write the TRE to ring */ + *tre_ptr = tre; + ctx->user_data[idx].valid = true; + ctx->user_data[idx].p = xfer->xfer_user_data; + + return 0; +} + +int gsi_queue_xfer(unsigned long chan_hdl, uint16_t num_xfers, + struct gsi_xfer_elem *xfer, bool ring_db) +{ + struct gsi_chan_ctx *ctx; + uint16_t free; + uint64_t wp_rollback; + int i; + spinlock_t *slock; + unsigned long flags; + + if (!gsi_ctx) { + pr_err("%s:%d gsi context not allocated\n", __func__, __LINE__); + return -GSI_STATUS_NODEV; + } + + if (chan_hdl >= gsi_ctx->max_ch || (num_xfers && !xfer)) { + GSIERR("bad params chan_hdl=%lu num_xfers=%u xfer=%pK\n", + chan_hdl, num_xfers, xfer); + return -GSI_STATUS_INVALID_PARAMS; + } + + if (unlikely(gsi_ctx->chan[chan_hdl].state + == GSI_CHAN_STATE_NOT_ALLOCATED)) { + GSIERR("bad state %d\n", + gsi_ctx->chan[chan_hdl].state); + return -GSI_STATUS_UNSUPPORTED_OP; + } + + + ctx = &gsi_ctx->chan[chan_hdl]; + + if (ctx->props.prot != GSI_CHAN_PROT_GPI && + ctx->props.prot != GSI_CHAN_PROT_GCI) { + GSIERR("op not supported for protocol %u\n", ctx->props.prot); + return -GSI_STATUS_UNSUPPORTED_OP; + } + + if (ctx->evtr) + slock = &ctx->evtr->ring.slock; + else + slock = &ctx->ring.slock; + + spin_lock_irqsave(slock, flags); + + /* allow only ring doorbell */ + if (!num_xfers) + goto ring_doorbell; + + /* + * for GCI channels the responsibility is on the caller to make sure + * there is enough room in the TRE. + */ + if (ctx->props.prot != GSI_CHAN_PROT_GCI) { + __gsi_query_channel_free_re(ctx, &free); + if (num_xfers > free) { + GSIERR_RL("chan_hdl=%lu num_xfers=%u free=%u\n", + chan_hdl, num_xfers, free); + spin_unlock_irqrestore(slock, flags); + return -GSI_STATUS_RING_INSUFFICIENT_SPACE; + } + } + + wp_rollback = ctx->ring.wp_local; + for (i = 0; i < num_xfers; i++) { + if (ctx->props.prot == GSI_CHAN_PROT_GCI) { + if (__gsi_populate_gci_tre(ctx, &xfer[i])) + break; + } else { + if (__gsi_populate_tre(ctx, &xfer[i])) + break; + } + gsi_incr_ring_wp(&ctx->ring); + } + + if (i != num_xfers) { + /* reject all the xfers */ + ctx->ring.wp_local = wp_rollback; + spin_unlock_irqrestore(slock, flags); + return -GSI_STATUS_INVALID_PARAMS; + } + + ctx->stats.queued += num_xfers; + +ring_doorbell: + if (ring_db) { + /* ensure TRE is set before ringing doorbell */ + wmb(); + gsi_ring_chan_doorbell(ctx); + } + + spin_unlock_irqrestore(slock, flags); + + return GSI_STATUS_SUCCESS; +} +EXPORT_SYMBOL(gsi_queue_xfer); + +int gsi_start_xfer(unsigned long chan_hdl) +{ + struct gsi_chan_ctx *ctx; + + if (!gsi_ctx) { + pr_err("%s:%d gsi context not allocated\n", __func__, __LINE__); + return -GSI_STATUS_NODEV; + } + + if (chan_hdl >= gsi_ctx->max_ch) { + GSIERR("bad params chan_hdl=%lu\n", chan_hdl); + return -GSI_STATUS_INVALID_PARAMS; + } + + ctx = &gsi_ctx->chan[chan_hdl]; + + if (ctx->props.prot != GSI_CHAN_PROT_GPI && + ctx->props.prot != GSI_CHAN_PROT_GCI) { + GSIERR("op not supported for protocol %u\n", ctx->props.prot); + return -GSI_STATUS_UNSUPPORTED_OP; + } + + if (ctx->state == GSI_CHAN_STATE_NOT_ALLOCATED) { + GSIERR("bad state %d\n", ctx->state); + return -GSI_STATUS_UNSUPPORTED_OP; + } + + if (ctx->ring.wp == ctx->ring.wp_local) + return GSI_STATUS_SUCCESS; + + gsi_ring_chan_doorbell(ctx); + + return GSI_STATUS_SUCCESS; +}; +EXPORT_SYMBOL(gsi_start_xfer); + +int gsi_poll_channel(unsigned long chan_hdl, + struct gsi_chan_xfer_notify *notify) +{ + int unused_var; + + return gsi_poll_n_channel(chan_hdl, notify, 1, &unused_var); +} +EXPORT_SYMBOL(gsi_poll_channel); + +int gsi_poll_n_channel(unsigned long chan_hdl, + struct gsi_chan_xfer_notify *notify, + int expected_num, int *actual_num) +{ + struct gsi_chan_ctx *ctx; + uint64_t rp; + int ee; + int i; + unsigned long flags; + + if (!gsi_ctx) { + pr_err("%s:%d gsi context not allocated\n", __func__, __LINE__); + return -GSI_STATUS_NODEV; + } + + if (chan_hdl >= gsi_ctx->max_ch || !notify || + !actual_num || expected_num <= 0) { + GSIERR("bad params chan_hdl=%lu notify=%pK\n", + chan_hdl, notify); + GSIERR("actual_num=%pK expected_num=%d\n", + actual_num, expected_num); + return -GSI_STATUS_INVALID_PARAMS; + } + + ctx = &gsi_ctx->chan[chan_hdl]; + ee = gsi_ctx->per.ee; + + if (ctx->props.prot != GSI_CHAN_PROT_GPI && + ctx->props.prot != GSI_CHAN_PROT_GCI) { + GSIERR("op not supported for protocol %u\n", ctx->props.prot); + return -GSI_STATUS_UNSUPPORTED_OP; + } + + /* Before going to poll packet make sure it was in allocated state */ + if (unlikely(ctx->state == GSI_CHAN_STATE_NOT_ALLOCATED)) { + GSIERR("bad state %d\n", ctx->state); + return -GSI_STATUS_UNSUPPORTED_OP; + } + + if (!ctx->evtr) { + GSIERR("no event ring associated chan_hdl=%lu\n", chan_hdl); + return -GSI_STATUS_UNSUPPORTED_OP; + } + + spin_lock_irqsave(&ctx->evtr->ring.slock, flags); + if (ctx->evtr->ring.rp == ctx->evtr->ring.rp_local) { + /* update rp to see of we have anything new to process */ + rp = ctx->evtr->props.gsi_read_event_ring_rp( + &ctx->evtr->props, ctx->evtr->id, ee); + rp |= ctx->evtr->ring.rp & GSI_MSB_MASK; + + ctx->evtr->ring.rp = rp; + /* read gsi event ring rp again if last read is empty */ + if (rp == ctx->evtr->ring.rp_local) { + /* event ring is empty */ + if (gsi_ctx->per.ver >= GSI_VER_3_0) { + gsihal_write_reg_nk(GSI_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_k, + ee, gsihal_get_ch_reg_idx(ctx->evtr->id), + gsihal_get_ch_reg_mask(ctx->evtr->id)); + } + else { + gsihal_write_reg_n(GSI_EE_n_CNTXT_SRC_IEOB_IRQ_CLR, + ee, 1 << ctx->evtr->id); + } + /* do another read to close a small window */ + __iowmb(); + rp = ctx->evtr->props.gsi_read_event_ring_rp( + &ctx->evtr->props, ctx->evtr->id, ee); + rp |= ctx->evtr->ring.rp & GSI_MSB_MASK; + ctx->evtr->ring.rp = rp; + if (rp == ctx->evtr->ring.rp_local) { + spin_unlock_irqrestore( + &ctx->evtr->ring.slock, + flags); + ctx->stats.poll_empty++; + return GSI_STATUS_POLL_EMPTY; + } + } + } + + *actual_num = gsi_get_complete_num(&ctx->evtr->ring, + ctx->evtr->ring.rp_local, ctx->evtr->ring.rp); + + if (*actual_num > expected_num) + *actual_num = expected_num; + + for (i = 0; i < *actual_num; i++) + gsi_process_evt_re(ctx->evtr, notify + i, false); + + spin_unlock_irqrestore(&ctx->evtr->ring.slock, flags); + ctx->stats.poll_ok++; + + return GSI_STATUS_SUCCESS; +} +EXPORT_SYMBOL(gsi_poll_n_channel); + +int gsi_config_channel_mode(unsigned long chan_hdl, enum gsi_chan_mode mode) +{ + struct gsi_chan_ctx *ctx, *coal_ctx; + enum gsi_chan_mode curr; + unsigned long flags; + enum gsi_chan_mode chan_mode; + int i; + + if (!gsi_ctx) { + pr_err("%s:%d gsi context not allocated\n", __func__, __LINE__); + return -GSI_STATUS_NODEV; + } + + if (chan_hdl >= gsi_ctx->max_ch) { + GSIERR("bad params chan_hdl=%lu mode=%u\n", chan_hdl, mode); + return -GSI_STATUS_INVALID_PARAMS; + } + + ctx = &gsi_ctx->chan[chan_hdl]; + + if (ctx->props.prot != GSI_CHAN_PROT_GPI && + ctx->props.prot != GSI_CHAN_PROT_GCI) { + GSIERR("op not supported for protocol %u\n", ctx->props.prot); + return -GSI_STATUS_UNSUPPORTED_OP; + } + + if (!ctx->evtr) { + GSIERR("cannot configure mode on chan_hdl=%lu\n", + chan_hdl); + return -GSI_STATUS_UNSUPPORTED_OP; + } + + if (atomic_read(&ctx->poll_mode)) + curr = GSI_CHAN_MODE_POLL; + else + curr = GSI_CHAN_MODE_CALLBACK; + + if (mode == curr) { + GSIDBG("already in requested mode %u chan_hdl=%lu\n", + curr, chan_hdl); + return -GSI_STATUS_UNSUPPORTED_OP; + } + spin_lock_irqsave(&gsi_ctx->slock, flags); + if (curr == GSI_CHAN_MODE_CALLBACK && + mode == GSI_CHAN_MODE_POLL) { + if (gsi_ctx->per.ver >= GSI_VER_3_0) { + if (ctx->evtr->props.intr != GSI_INTR_MSI) { + __gsi_config_ieob_irq_k(gsi_ctx->per.ee, + gsihal_get_ch_reg_idx(ctx->evtr->id), + gsihal_get_ch_reg_mask(ctx->evtr->id), + 0); + } + } + else { + __gsi_config_ieob_irq(gsi_ctx->per.ee, 1 << ctx->evtr->id, 0); + } + if (gsi_ctx->per.ver >= GSI_VER_3_0) { + gsihal_write_reg_nk(GSI_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_k, + gsi_ctx->per.ee, gsihal_get_ch_reg_idx(ctx->evtr->id), + gsihal_get_ch_reg_mask(ctx->evtr->id)); + } + else { + gsihal_write_reg_n(GSI_EE_n_CNTXT_SRC_IEOB_IRQ_CLR, + gsi_ctx->per.ee, 1 << ctx->evtr->id); + } + atomic_set(&ctx->poll_mode, mode); + for(i = 0; i < ctx->evtr->num_of_chan_allocated; i++) { + atomic_set(&ctx->evtr->chan[i]->poll_mode, mode); + } + if ((ctx->props.prot == GSI_CHAN_PROT_GCI) && *ctx->evtr->chan) { + atomic_set(&ctx->evtr->chan[0]->poll_mode, mode); + } else if (gsi_ctx->coal_info.evchid == ctx->evtr->id) { + coal_ctx = &gsi_ctx->chan[gsi_ctx->coal_info.ch_id]; + if (coal_ctx != NULL) + atomic_set(&coal_ctx->poll_mode, mode); + } + + GSIDBG("set gsi_ctx evtr_id %d to %d mode\n", + ctx->evtr->id, mode); + ctx->stats.callback_to_poll++; + } + + if (curr == GSI_CHAN_MODE_POLL && + mode == GSI_CHAN_MODE_CALLBACK) { + atomic_set(&ctx->poll_mode, mode); + for(i = 0; i < ctx->evtr->num_of_chan_allocated; i++) { + atomic_set(&ctx->evtr->chan[i]->poll_mode, mode); + } + if ((ctx->props.prot == GSI_CHAN_PROT_GCI) && *ctx->evtr->chan) { + atomic_set(&ctx->evtr->chan[0]->poll_mode, mode); + } else if (gsi_ctx->coal_info.evchid == ctx->evtr->id) { + coal_ctx = &gsi_ctx->chan[gsi_ctx->coal_info.ch_id]; + if (coal_ctx != NULL) + atomic_set(&coal_ctx->poll_mode, mode); + } + if (gsi_ctx->per.ver >= GSI_VER_3_0) { + if (ctx->evtr->props.intr != GSI_INTR_MSI) { + __gsi_config_ieob_irq_k(gsi_ctx->per.ee, + gsihal_get_ch_reg_idx(ctx->evtr->id), + gsihal_get_ch_reg_mask(ctx->evtr->id), + ~0); + } + } + else { + __gsi_config_ieob_irq(gsi_ctx->per.ee, 1 << ctx->evtr->id, ~0); + } + GSIDBG("set gsi_ctx evtr_id %d to %d mode\n", + ctx->evtr->id, mode); + + /* + * In GSI 2.2 and 2.5 there is a limitation that can lead + * to losing an interrupt. For these versions an + * explicit check is needed after enabling the interrupt + */ + if ((gsi_ctx->per.ver == GSI_VER_2_2 || + gsi_ctx->per.ver == GSI_VER_2_5) && + !gsi_ctx->per.skip_ieob_mask_wa) { + u32 src = gsihal_read_reg_n( + GSI_EE_n_CNTXT_SRC_IEOB_IRQ, + gsi_ctx->per.ee); + if (src & (1 << ctx->evtr->id)) { + if (gsi_ctx->per.ver >= GSI_VER_3_0) { + __gsi_config_ieob_irq_k(gsi_ctx->per.ee, + gsihal_get_ch_reg_idx(ctx->evtr->id), + gsihal_get_ch_reg_mask(ctx->evtr->id), + 0); + gsihal_write_reg_nk( + GSI_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_k, + gsi_ctx->per.ee, + gsihal_get_ch_reg_idx(ctx->evtr->id), + gsihal_get_ch_reg_mask(ctx->evtr->id)); + } + else { + __gsi_config_ieob_irq(gsi_ctx->per.ee, 1 << + ctx->evtr->id, 0); + gsihal_write_reg_n( + GSI_EE_n_CNTXT_SRC_IEOB_IRQ_CLR, + gsi_ctx->per.ee, + 1 << ctx->evtr->id); + } + spin_unlock_irqrestore(&gsi_ctx->slock, flags); + spin_lock_irqsave(&ctx->evtr->ring.slock, + flags); + chan_mode = atomic_xchg(&ctx->poll_mode, + GSI_CHAN_MODE_POLL); + spin_unlock_irqrestore( + &ctx->evtr->ring.slock, flags); + ctx->stats.poll_pending_irq++; + GSIDBG("IEOB WA pnd cnt = %ld prvmode = %d\n", + ctx->stats.poll_pending_irq, + chan_mode); + if (chan_mode == GSI_CHAN_MODE_POLL) + return GSI_STATUS_SUCCESS; + else + return -GSI_STATUS_PENDING_IRQ; + } + } + ctx->stats.poll_to_callback++; + } + spin_unlock_irqrestore(&gsi_ctx->slock, flags); + return GSI_STATUS_SUCCESS; +} +EXPORT_SYMBOL(gsi_config_channel_mode); + +int gsi_get_channel_cfg(unsigned long chan_hdl, struct gsi_chan_props *props, + union gsi_channel_scratch *scr) +{ + struct gsi_chan_ctx *ctx; + + if (!gsi_ctx) { + pr_err("%s:%d gsi context not allocated\n", __func__, __LINE__); + return -GSI_STATUS_NODEV; + } + + if (!props || !scr) { + GSIERR("bad params props=%pK scr=%pK\n", props, scr); + return -GSI_STATUS_INVALID_PARAMS; + } + + if (chan_hdl >= gsi_ctx->max_ch) { + GSIERR("bad params chan_hdl=%lu\n", chan_hdl); + return -GSI_STATUS_INVALID_PARAMS; + } + + ctx = &gsi_ctx->chan[chan_hdl]; + + if (ctx->state == GSI_CHAN_STATE_NOT_ALLOCATED) { + GSIERR("bad state %d\n", ctx->state); + return -GSI_STATUS_UNSUPPORTED_OP; + } + + mutex_lock(&ctx->mlock); + *props = ctx->props; + *scr = ctx->scratch; + mutex_unlock(&ctx->mlock); + + return GSI_STATUS_SUCCESS; +} +EXPORT_SYMBOL(gsi_get_channel_cfg); + +int gsi_set_channel_cfg(unsigned long chan_hdl, struct gsi_chan_props *props, + union gsi_channel_scratch *scr) +{ + struct gsi_chan_ctx *ctx; + + if (!gsi_ctx) { + pr_err("%s:%d gsi context not allocated\n", __func__, __LINE__); + return -GSI_STATUS_NODEV; + } + + if (!props || gsi_validate_channel_props(props)) { + GSIERR("bad params props=%pK\n", props); + return -GSI_STATUS_INVALID_PARAMS; + } + + if (chan_hdl >= gsi_ctx->max_ch) { + GSIERR("bad params chan_hdl=%lu\n", chan_hdl); + return -GSI_STATUS_INVALID_PARAMS; + } + + ctx = &gsi_ctx->chan[chan_hdl]; + + if (ctx->state != GSI_CHAN_STATE_ALLOCATED) { + GSIERR("bad state %d\n", ctx->state); + return -GSI_STATUS_UNSUPPORTED_OP; + } + + if (ctx->props.ch_id != props->ch_id || + ctx->props.evt_ring_hdl != props->evt_ring_hdl) { + GSIERR("changing immutable fields not supported\n"); + return -GSI_STATUS_UNSUPPORTED_OP; + } + + mutex_lock(&ctx->mlock); + ctx->props = *props; + if (scr) + ctx->scratch = *scr; + gsi_program_chan_ctx(&ctx->props, gsi_ctx->per.ee, + ctx->evtr ? ctx->evtr->id : GSI_NO_EVT_ERINDEX); + gsi_init_chan_ring(&ctx->props, &ctx->ring); + + /* restore scratch */ + __gsi_write_channel_scratch(chan_hdl, ctx->scratch); + mutex_unlock(&ctx->mlock); + + return GSI_STATUS_SUCCESS; +} +EXPORT_SYMBOL(gsi_set_channel_cfg); + +static void gsi_configure_ieps(enum gsi_ver ver) +{ + gsihal_write_reg(GSI_GSI_IRAM_PTR_CH_CMD, 1); + gsihal_write_reg(GSI_GSI_IRAM_PTR_CH_DB, 2); + gsihal_write_reg(GSI_GSI_IRAM_PTR_CH_DIS_COMP, 3); + gsihal_write_reg(GSI_GSI_IRAM_PTR_CH_EMPTY, 4); + gsihal_write_reg(GSI_GSI_IRAM_PTR_EE_GENERIC_CMD, 5); + gsihal_write_reg(GSI_GSI_IRAM_PTR_EVENT_GEN_COMP, 6); + gsihal_write_reg(GSI_GSI_IRAM_PTR_INT_MOD_STOPPED, 7); + gsihal_write_reg(GSI_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0, 8); + gsihal_write_reg(GSI_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2, 9); + gsihal_write_reg(GSI_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1, 10); + gsihal_write_reg(GSI_GSI_IRAM_PTR_NEW_RE, 11); + gsihal_write_reg(GSI_GSI_IRAM_PTR_READ_ENG_COMP, 12); + gsihal_write_reg(GSI_GSI_IRAM_PTR_TIMER_EXPIRED, 13); + gsihal_write_reg(GSI_GSI_IRAM_PTR_EV_DB, 14); + gsihal_write_reg(GSI_GSI_IRAM_PTR_UC_GP_INT, 15); + gsihal_write_reg(GSI_GSI_IRAM_PTR_WRITE_ENG_COMP, 16); + + if (ver >= GSI_VER_2_5) + gsihal_write_reg( + GSI_GSI_IRAM_PTR_TLV_CH_NOT_FULL, + 17); + + if (ver >= GSI_VER_2_11) + gsihal_write_reg( + GSI_GSI_IRAM_PTR_MSI_DB, + 18); + if (ver >= GSI_VER_3_0) + gsihal_write_reg( + GSI_GSI_IRAM_PTR_INT_NOTIFY_MCS, + 19); +} + +static void gsi_configure_bck_prs_matrix(void) +{ + /* + * For now, these are default values. In the future, GSI FW image will + * produce optimized back-pressure values based on the FW image. + */ + gsihal_write_reg(GSI_IC_DISABLE_CHNL_BCK_PRS_LSB, 0xfffffffe); + gsihal_write_reg(GSI_IC_DISABLE_CHNL_BCK_PRS_MSB, 0xffffffff); + gsihal_write_reg(GSI_IC_GEN_EVNT_BCK_PRS_LSB, 0xffffffbf); + gsihal_write_reg(GSI_IC_GEN_EVNT_BCK_PRS_MSB, 0xffffffff); + gsihal_write_reg(GSI_IC_GEN_INT_BCK_PRS_LSB, 0xffffefff); + gsihal_write_reg(GSI_IC_GEN_INT_BCK_PRS_MSB, 0xffffffff); + gsihal_write_reg(GSI_IC_STOP_INT_MOD_BCK_PRS_LSB, 0xffffefff); + gsihal_write_reg(GSI_IC_STOP_INT_MOD_BCK_PRS_MSB, 0xffffffff); + gsihal_write_reg(GSI_IC_PROCESS_DESC_BCK_PRS_LSB, 0x00000000); + gsihal_write_reg(GSI_IC_PROCESS_DESC_BCK_PRS_MSB, 0x00000000); + gsihal_write_reg(GSI_IC_TLV_STOP_BCK_PRS_LSB, 0xf9ffffff); + gsihal_write_reg(GSI_IC_TLV_STOP_BCK_PRS_MSB, 0xffffffff); + gsihal_write_reg(GSI_IC_TLV_RESET_BCK_PRS_LSB, 0xf9ffffff); + gsihal_write_reg(GSI_IC_TLV_RESET_BCK_PRS_MSB, 0xffffffff); + gsihal_write_reg(GSI_IC_RGSTR_TIMER_BCK_PRS_LSB, 0xffffffff); + gsihal_write_reg(GSI_IC_RGSTR_TIMER_BCK_PRS_MSB, 0xfffffffe); + gsihal_write_reg(GSI_IC_READ_BCK_PRS_LSB, 0xffffffff); + gsihal_write_reg(GSI_IC_READ_BCK_PRS_MSB, 0xffffefff); + gsihal_write_reg(GSI_IC_WRITE_BCK_PRS_LSB, 0xffffffff); + gsihal_write_reg(GSI_IC_WRITE_BCK_PRS_MSB, 0xffffdfff); + gsihal_write_reg(GSI_IC_UCONTROLLER_GPR_BCK_PRS_LSB, 0xffffffff); + gsihal_write_reg(GSI_IC_UCONTROLLER_GPR_BCK_PRS_MSB, 0xff03ffff); +} + +int gsi_configure_regs(phys_addr_t per_base_addr, enum gsi_ver ver) +{ + if (!gsi_ctx) { + pr_err("%s:%d gsi context not allocated\n", __func__, __LINE__); + return -GSI_STATUS_NODEV; + } + + if (!gsi_ctx->base) { + GSIERR("access to GSI HW has not been mapped\n"); + return -GSI_STATUS_INVALID_PARAMS; + } + + if (ver <= GSI_VER_ERR || ver >= GSI_VER_MAX) { + GSIERR("Incorrect version %d\n", ver); + return -GSI_STATUS_ERROR; + } + + gsihal_write_reg(GSI_GSI_PERIPH_BASE_ADDR_MSB, 0); + gsihal_write_reg(GSI_GSI_PERIPH_BASE_ADDR_LSB, per_base_addr); + gsi_configure_bck_prs_matrix(); + gsi_configure_ieps(ver); + + return 0; +} +EXPORT_SYMBOL(gsi_configure_regs); + +int gsi_enable_fw(phys_addr_t gsi_base_addr, u32 gsi_size, enum gsi_ver ver) +{ + struct gsihal_reg_gsi_cfg gsi_cfg; + + if (ver <= GSI_VER_ERR || ver >= GSI_VER_MAX) { + GSIERR("Incorrect version %d\n", ver); + return -GSI_STATUS_ERROR; + } + + /* Enable the MCS and set to x2 clocks */ + gsi_cfg.gsi_enable = 1; + gsi_cfg.double_mcs_clk_freq = 1; + gsi_cfg.uc_is_mcs = 0; + gsi_cfg.gsi_pwr_clps = 0; + gsi_cfg.bp_mtrix_disable = 0; + if (ver >= GSI_VER_1_2) { + gsihal_write_reg(GSI_GSI_MCS_CFG, 1); + + gsi_cfg.mcs_enable = 0; + + } else { + gsi_cfg.mcs_enable = 1; + } + + /* GSI frequency is peripheral frequency divided by 3 (2+1) */ + if (ver >= GSI_VER_2_5) + gsi_cfg.sleep_clk_div = 2; + gsihal_write_reg_fields(GSI_GSI_CFG, &gsi_cfg); + + return 0; + +} +EXPORT_SYMBOL(gsi_enable_fw); + +void gsi_get_inst_ram_offset_and_size(unsigned long *base_offset, + unsigned long *size, enum gsi_ver ver) +{ + if (!gsi_ctx) { + pr_err("%s:%d gsi context not allocated\n", __func__, __LINE__); + return; + } + + if (size) + *size = gsihal_get_inst_ram_size(); + + if (base_offset) { + *base_offset = gsihal_get_reg_n_ofst(GSI_GSI_INST_RAM_n, 0); + } +} +EXPORT_SYMBOL(gsi_get_inst_ram_offset_and_size); + +/* + * Dumping the Debug registers for halt issue debugging. + */ +static void gsi_dump_halt_debug_reg(unsigned int chan_idx, unsigned int ee) +{ + struct gsihal_reg_ch_k_cntxt_0 ch_k_cntxt_0; + + GSIERR("DEBUG_PC_FOR_DEBUG = 0x%x\n", + gsihal_read_reg(GSI_EE_n_GSI_DEBUG_PC_FOR_DEBUG)); + + GSIERR("GSI_DEBUG_BUSY_REG 0x%x\n", + gsihal_read_reg(GSI_EE_n_GSI_DEBUG_BUSY_REG)); + + GSIERR("GSI_EE_n_CNTXT_GLOB_IRQ_EN_OFFS = 0x%x\n", + gsihal_read_reg_n(GSI_EE_n_CNTXT_GLOB_IRQ_EN, gsi_ctx->per.ee)); + + GSIERR("GSI_EE_n_CNTXT_GLOB_IRQ_STTS_OFFS IRQ type = 0x%x\n", + gsihal_read_reg_n(GSI_EE_n_CNTXT_GLOB_IRQ_EN, gsi_ctx->per.ee)); + + GSIERR("GSI_EE_n_CNTXT_SCRATCH_0_OFFS = 0x%x\n", + gsihal_read_reg_n(GSI_EE_n_CNTXT_SCRATCH_0, gsi_ctx->per.ee)); + if (gsi_ctx->per.ver >= GSI_VER_2_9) + GSIERR("GSI_EE_n_GSI_CH_k_SCRATCH_4 = 0x%x\n", + gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_SCRATCH_4, ee, chan_idx)); + + gsihal_read_reg_nk_fields(GSI_EE_n_GSI_CH_k_CNTXT_0, ee, chan_idx, &ch_k_cntxt_0); + GSIERR("Q6 channel [%d] state = %d\n", chan_idx, ch_k_cntxt_0.chstate); +} + +int gsi_halt_channel_ee(unsigned int chan_idx, unsigned int ee, int *code) +{ + enum gsi_generic_ee_cmd_opcode op = GSI_GEN_EE_CMD_HALT_CHANNEL; + struct gsihal_reg_gsi_ee_generic_cmd cmd; + int res; + + if (!gsi_ctx) { + pr_err("%s:%d gsi context not allocated\n", __func__, __LINE__); + return -GSI_STATUS_NODEV; + } + + if (chan_idx >= gsi_ctx->max_ch || !code) { + GSIERR("bad params chan_idx=%d\n", chan_idx); + return -GSI_STATUS_INVALID_PARAMS; + } + + mutex_lock(&gsi_ctx->mlock); + __gsi_config_glob_irq(gsi_ctx->per.ee, + gsihal_get_glob_irq_en_gp_int1_mask(), ~0); + reinit_completion(&gsi_ctx->gen_ee_cmd_compl); + + /* invalidate the response */ + gsi_ctx->scratch.word0.val = gsihal_read_reg_n( + GSI_EE_n_CNTXT_SCRATCH_0, gsi_ctx->per.ee); + gsi_ctx->scratch.word0.s.generic_ee_cmd_return_code = 0; + gsihal_write_reg_n(GSI_EE_n_CNTXT_SCRATCH_0, + gsi_ctx->per.ee, gsi_ctx->scratch.word0.val); + + gsi_ctx->gen_ee_cmd_dbg.halt_channel++; + cmd.opcode = op; + cmd.virt_chan_idx = chan_idx; + cmd.ee = ee; + gsihal_write_reg_n_fields(GSI_EE_n_GSI_EE_GENERIC_CMD, gsi_ctx->per.ee, &cmd); + res = wait_for_completion_timeout(&gsi_ctx->gen_ee_cmd_compl, + msecs_to_jiffies(GSI_CMD_TIMEOUT)); + if (res == 0) { + GSIERR("chan_idx=%u ee=%u timed out\n", chan_idx, ee); + res = -GSI_STATUS_TIMED_OUT; + goto free_lock; + } + + gsi_ctx->scratch.word0.val = gsihal_read_reg_n(GSI_EE_n_CNTXT_SCRATCH_0, + gsi_ctx->per.ee); + if (gsi_ctx->scratch.word0.s.generic_ee_cmd_return_code == + GSI_GEN_EE_CMD_RETURN_CODE_RETRY) { + GSIDBG("chan_idx=%u ee=%u busy try again\n", chan_idx, ee); + *code = GSI_GEN_EE_CMD_RETURN_CODE_RETRY; + res = -GSI_STATUS_AGAIN; + goto free_lock; + } + if (gsi_ctx->scratch.word0.s.generic_ee_cmd_return_code == 0) { + GSIERR("No response received\n"); + gsi_dump_halt_debug_reg(chan_idx, ee); + usleep_range(GSI_RESET_WA_MIN_SLEEP, GSI_RESET_WA_MAX_SLEEP); + GSIERR("Reading after usleep scratch 0 reg\n"); + gsi_ctx->scratch.word0.val = gsihal_read_reg_n(GSI_EE_n_CNTXT_SCRATCH_0, + gsi_ctx->per.ee); + if (gsi_ctx->scratch.word0.s.generic_ee_cmd_return_code == 0) { + GSIERR("No response received second attempt\n"); + gsi_dump_halt_debug_reg(chan_idx, ee); + res = -GSI_STATUS_ERROR; + goto free_lock; + } + } + + res = GSI_STATUS_SUCCESS; + *code = gsi_ctx->scratch.word0.s.generic_ee_cmd_return_code; +free_lock: + __gsi_config_glob_irq(gsi_ctx->per.ee, + gsihal_get_glob_irq_en_gp_int1_mask(), 0); + mutex_unlock(&gsi_ctx->mlock); + + return res; +} +EXPORT_SYMBOL(gsi_halt_channel_ee); + +int gsi_alloc_channel_ee(unsigned int chan_idx, unsigned int ee, int *code) +{ + enum gsi_generic_ee_cmd_opcode op = GSI_GEN_EE_CMD_ALLOC_CHANNEL; + struct gsi_chan_ctx *ctx; + struct gsihal_reg_gsi_ee_generic_cmd cmd; + int res; + + if (chan_idx >= gsi_ctx->max_ch || !code) { + GSIERR("bad params chan_idx=%d\n", chan_idx); + return -GSI_STATUS_INVALID_PARAMS; + } + + if (ee == 0) + return gsi_alloc_ap_channel(chan_idx); + + mutex_lock(&gsi_ctx->mlock); + __gsi_config_glob_irq(gsi_ctx->per.ee, + gsihal_get_glob_irq_en_gp_int1_mask(), ~0); + reinit_completion(&gsi_ctx->gen_ee_cmd_compl); + + /* invalidate the response */ + gsi_ctx->scratch.word0.val = gsihal_read_reg_n(GSI_EE_n_CNTXT_SCRATCH_0, + gsi_ctx->per.ee); + gsi_ctx->scratch.word0.s.generic_ee_cmd_return_code = 0; + gsihal_write_reg_n(GSI_EE_n_CNTXT_SCRATCH_0, + gsi_ctx->per.ee, gsi_ctx->scratch.word0.val); + + cmd.opcode = op; + cmd.virt_chan_idx = chan_idx; + cmd.ee = ee; + gsihal_write_reg_n_fields( + GSI_EE_n_GSI_EE_GENERIC_CMD, gsi_ctx->per.ee, &cmd); + res = wait_for_completion_timeout(&gsi_ctx->gen_ee_cmd_compl, + msecs_to_jiffies(GSI_CMD_TIMEOUT)); + if (res == 0) { + GSIERR("chan_idx=%u ee=%u timed out\n", chan_idx, ee); + res = -GSI_STATUS_TIMED_OUT; + goto free_lock; + } + + gsi_ctx->scratch.word0.val = gsihal_read_reg_n(GSI_EE_n_CNTXT_SCRATCH_0, + gsi_ctx->per.ee); + if (gsi_ctx->scratch.word0.s.generic_ee_cmd_return_code == + GSI_GEN_EE_CMD_RETURN_CODE_OUT_OF_RESOURCES) { + GSIDBG("chan_idx=%u ee=%u out of resources\n", chan_idx, ee); + *code = GSI_GEN_EE_CMD_RETURN_CODE_OUT_OF_RESOURCES; + res = -GSI_STATUS_RES_ALLOC_FAILURE; + goto free_lock; + } + if (gsi_ctx->scratch.word0.s.generic_ee_cmd_return_code == 0) { + GSIERR("No response received\n"); + res = -GSI_STATUS_ERROR; + goto free_lock; + } + if (ee == 0) { + ctx = &gsi_ctx->chan[chan_idx]; + gsi_ctx->ch_dbg[chan_idx].ch_allocate++; + } + res = GSI_STATUS_SUCCESS; + *code = gsi_ctx->scratch.word0.s.generic_ee_cmd_return_code; +free_lock: + __gsi_config_glob_irq(gsi_ctx->per.ee, + gsihal_get_glob_irq_en_gp_int1_mask(), 0); + mutex_unlock(&gsi_ctx->mlock); + + return res; +} +EXPORT_SYMBOL(gsi_alloc_channel_ee); + +int gsi_enable_flow_control_ee(unsigned int chan_idx, unsigned int ee, + int *code) +{ + enum gsi_generic_ee_cmd_opcode op = GSI_GEN_EE_CMD_ENABLE_FLOW_CHANNEL; + struct gsihal_reg_ch_k_cntxt_0 ch_k_cntxt_0; + struct gsihal_reg_gsi_ee_generic_cmd cmd; + enum gsi_chan_state curr_state = GSI_CHAN_STATE_NOT_ALLOCATED; + int res; + + if (!gsi_ctx) { + pr_err("%s:%d gsi context not allocated\n", __func__, __LINE__); + return -GSI_STATUS_NODEV; + } + + if (chan_idx >= gsi_ctx->max_ch || !code) { + GSIERR("bad params chan_idx=%d\n", chan_idx); + return -GSI_STATUS_INVALID_PARAMS; + } + + mutex_lock(&gsi_ctx->mlock); + __gsi_config_glob_irq(gsi_ctx->per.ee, + gsihal_get_glob_irq_en_gp_int1_mask(), ~0); + reinit_completion(&gsi_ctx->gen_ee_cmd_compl); + + /* invalidate the response */ + gsi_ctx->scratch.word0.val = gsihal_read_reg_n(GSI_EE_n_CNTXT_SCRATCH_0, + gsi_ctx->per.ee); + gsi_ctx->scratch.word0.s.generic_ee_cmd_return_code = 0; + gsihal_write_reg_n(GSI_EE_n_CNTXT_SCRATCH_0, + gsi_ctx->per.ee, gsi_ctx->scratch.word0.val); + + gsi_ctx->gen_ee_cmd_dbg.flow_ctrl_channel++; + cmd.opcode = op; + cmd.virt_chan_idx = chan_idx; + cmd.ee = ee; + gsihal_write_reg_n_fields( + GSI_EE_n_GSI_EE_GENERIC_CMD, gsi_ctx->per.ee, &cmd); + + res = wait_for_completion_timeout(&gsi_ctx->gen_ee_cmd_compl, + msecs_to_jiffies(GSI_CMD_TIMEOUT)); + if (res == 0) { + GSIERR("chan_idx=%u ee=%u timed out\n", chan_idx, ee); + res = -GSI_STATUS_TIMED_OUT; + goto free_lock; + } + + gsi_ctx->scratch.word0.val = gsihal_read_reg_n(GSI_EE_n_CNTXT_SCRATCH_0, + gsi_ctx->per.ee); + if (gsi_ctx->scratch.word0.s.generic_ee_cmd_return_code == + GSI_GEN_EE_CMD_RETURN_CODE_CHANNEL_NOT_RUNNING) { + GSIDBG("chan_idx=%u ee=%u not in correct state\n", + chan_idx, ee); + *code = GSI_GEN_EE_CMD_RETURN_CODE_CHANNEL_NOT_RUNNING; + res = -GSI_STATUS_RES_ALLOC_FAILURE; + goto free_lock; + } else if (gsi_ctx->scratch.word0.s.generic_ee_cmd_return_code == + GSI_GEN_EE_CMD_RETURN_CODE_INCORRECT_CHANNEL_TYPE || + gsi_ctx->scratch.word0.s.generic_ee_cmd_return_code == + GSI_GEN_EE_CMD_RETURN_CODE_INCORRECT_CHANNEL_INDEX) { + GSIERR("chan_idx=%u ee=%u not in correct state\n", + chan_idx, ee); + GSI_ASSERT(); + } + if (gsi_ctx->scratch.word0.s.generic_ee_cmd_return_code == 0) { + GSIERR("No response received\n"); + res = -GSI_STATUS_ERROR; + goto free_lock; + } + + /*Reading current channel state*/ + gsihal_read_reg_nk_fields(GSI_EE_n_GSI_CH_k_CNTXT_0, + gsi_ctx->per.ee, chan_idx, &ch_k_cntxt_0); + curr_state = ch_k_cntxt_0.chstate; + if (curr_state == GSI_CHAN_STATE_FLOW_CONTROL) { + GSIDBG("ch %u state updated to %u\n", chan_idx, curr_state); + res = GSI_STATUS_SUCCESS; + } else { + GSIERR("ch %u state updated to %u incorrect state\n", + chan_idx, curr_state); + res = -GSI_STATUS_ERROR; + } + *code = gsi_ctx->scratch.word0.s.generic_ee_cmd_return_code; +free_lock: + __gsi_config_glob_irq(gsi_ctx->per.ee, + gsihal_get_glob_irq_en_gp_int1_mask(), 0); + mutex_unlock(&gsi_ctx->mlock); + + return res; +} +EXPORT_SYMBOL(gsi_enable_flow_control_ee); + +int gsi_flow_control_ee(unsigned int chan_idx, int ep_id, unsigned int ee, + bool enable, bool prmy_scnd_fc, int *code) +{ + struct gsihal_reg_gsi_ee_generic_cmd cmd; + enum gsi_generic_ee_cmd_opcode op = enable ? + GSI_GEN_EE_CMD_ENABLE_FLOW_CHANNEL : + GSI_GEN_EE_CMD_DISABLE_FLOW_CHANNEL; + int res; + int wait_due_pending = 0; + uint32_t fc_pending = 0; + + if (!gsi_ctx) { + pr_err("%s:%d gsi context not allocated\n", __func__, __LINE__); + return -GSI_STATUS_NODEV; + } + + if (chan_idx >= gsi_ctx->max_ch || !code) { + GSIERR("bad params chan_idx=%d\n", chan_idx); + return -GSI_STATUS_INVALID_PARAMS; + } + + GSIDBG("GSI flow control opcode=%d, ch_id=%d\n", op, chan_idx); + + mutex_lock(&gsi_ctx->mlock); + __gsi_config_glob_irq(gsi_ctx->per.ee, + gsihal_get_glob_irq_en_gp_int1_mask(), ~0); + reinit_completion(&gsi_ctx->gen_ee_cmd_compl); + + /* invalidate the response */ + gsi_ctx->scratch.word0.val = gsihal_read_reg_n(GSI_EE_n_CNTXT_SCRATCH_0, + gsi_ctx->per.ee); + + gsi_ctx->scratch.word0.s.generic_ee_cmd_return_code = 0; + gsihal_write_reg_n(GSI_EE_n_CNTXT_SCRATCH_0, + gsi_ctx->per.ee, gsi_ctx->scratch.word0.val); + + gsi_ctx->gen_ee_cmd_dbg.flow_ctrl_channel++; + cmd.opcode = op; + cmd.virt_chan_idx = chan_idx; + cmd.ee = ee; + cmd.prmy_scnd_fc = prmy_scnd_fc; + gsihal_write_reg_n_fields( + GSI_EE_n_GSI_EE_GENERIC_CMD, gsi_ctx->per.ee, &cmd); + +wait_again: + fc_pending = gsihal_read_reg_n(GSI_GSI_SHRAM_n, + (ep_id * GSI_FC_NUM_WORDS_PER_CHNL_SHRAM) + GSI_FC_STATE_INDEX_SHRAM) & + GSI_FC_PENDING_MASK; + res = wait_for_completion_timeout(&gsi_ctx->gen_ee_cmd_compl, + msecs_to_jiffies(GSI_FC_CMD_TIMEOUT)); + if (res == 0) { + GSIERR("chan_idx=%u ee=%u timed out\n", chan_idx, ee); + if (op == GSI_GEN_EE_CMD_ENABLE_FLOW_CHANNEL && + wait_due_pending < GSI_FC_MAX_TIMEOUT && + fc_pending) { + wait_due_pending++; + goto wait_again; + } + GSIERR("GSI_EE_n_CNTXT_GLOB_IRQ_EN_OFFS = 0x%x\n", + gsihal_read_reg_n(GSI_EE_n_CNTXT_GLOB_IRQ_EN, gsi_ctx->per.ee)); + GSIERR("GSI_EE_n_CNTXT_GLOB_IRQ_STTS_OFFS IRQ type = 0x%x\n", + gsihal_read_reg_n(GSI_EE_n_CNTXT_GLOB_IRQ_STTS, gsi_ctx->per.ee)); + } + + gsi_ctx->scratch.word0.val = gsihal_read_reg_n(GSI_EE_n_CNTXT_SCRATCH_0, + gsi_ctx->per.ee); + + GSIDBG( + "Flow control command response GENERIC_CMD_RESPONSE_CODE = %u, val = %u\n", + gsi_ctx->scratch.word0.s.generic_ee_cmd_return_code, + gsi_ctx->scratch.word0.val); + + if (gsi_ctx->scratch.word0.s.generic_ee_cmd_return_code == + GSI_GEN_EE_CMD_RETURN_CODE_CHANNEL_NOT_RUNNING) { + GSIDBG("chan_idx=%u ee=%u not in correct state\n", + chan_idx, ee); + *code = GSI_GEN_EE_CMD_RETURN_CODE_CHANNEL_NOT_RUNNING; + res = -GSI_STATUS_RES_ALLOC_FAILURE; + goto free_lock; + } else if (gsi_ctx->scratch.word0.s.generic_ee_cmd_return_code == + GSI_GEN_EE_CMD_RETURN_CODE_INCORRECT_CHANNEL_TYPE) { + GSIERR("chan_idx=%u ee=%u not in correct state\n", + chan_idx, ee); + GSI_ASSERT(); + } else if (gsi_ctx->scratch.word0.s.generic_ee_cmd_return_code == + GSI_GEN_EE_CMD_RETURN_CODE_INCORRECT_CHANNEL_INDEX) { + GSIERR("Channel ID = %u ee = %u not allocated\n", chan_idx, ee); + } + + if (gsi_ctx->scratch.word0.s.generic_ee_cmd_return_code == 0) { + GSIERR("No response received\n"); + res = -GSI_STATUS_ERROR; + GSI_ASSERT(); + goto free_lock; + } + + *code = gsi_ctx->scratch.word0.s.generic_ee_cmd_return_code; + res = GSI_STATUS_SUCCESS; +free_lock: + __gsi_config_glob_irq(gsi_ctx->per.ee, + gsihal_get_glob_irq_en_gp_int1_mask(), 0); + mutex_unlock(&gsi_ctx->mlock); + + return res; +} +EXPORT_SYMBOL(gsi_flow_control_ee); + +int gsi_query_flow_control_state_ee(unsigned int chan_idx, unsigned int ee, + bool prmy_scnd_fc, int *code) +{ + struct gsihal_reg_gsi_ee_generic_cmd cmd; + enum gsi_generic_ee_cmd_opcode op = GSI_GEN_EE_CMD_QUERY_FLOW_CHANNEL; + int res; + + if (!gsi_ctx) { + pr_err("%s:%d gsi context not allocated\n", __func__, __LINE__); + return -GSI_STATUS_NODEV; + } + + if (chan_idx >= gsi_ctx->max_ch || !code) { + GSIERR("bad params chan_idx=%d\n", chan_idx); + return -GSI_STATUS_INVALID_PARAMS; + } + + mutex_lock(&gsi_ctx->mlock); + __gsi_config_glob_irq(gsi_ctx->per.ee, + gsihal_get_glob_irq_en_gp_int1_mask(), ~0); + reinit_completion(&gsi_ctx->gen_ee_cmd_compl); + + /* invalidate the response */ + gsi_ctx->scratch.word0.val = gsihal_read_reg_n(GSI_EE_n_CNTXT_SCRATCH_0, + gsi_ctx->per.ee); + gsi_ctx->scratch.word0.s.generic_ee_cmd_return_code = 0; + gsihal_write_reg_n(GSI_EE_n_CNTXT_SCRATCH_0, + gsi_ctx->per.ee, gsi_ctx->scratch.word0.val); + + gsi_ctx->gen_ee_cmd_dbg.flow_ctrl_channel++; + cmd.opcode = op; + cmd.virt_chan_idx = chan_idx; + cmd.ee = ee; + cmd.prmy_scnd_fc = prmy_scnd_fc; + gsihal_write_reg_n_fields( + GSI_EE_n_GSI_EE_GENERIC_CMD, gsi_ctx->per.ee, &cmd); + + res = wait_for_completion_timeout(&gsi_ctx->gen_ee_cmd_compl, + msecs_to_jiffies(GSI_CMD_TIMEOUT)); + if (res == 0) { + GSIERR("chan_idx=%u ee=%u timed out\n", chan_idx, ee); + res = -GSI_STATUS_TIMED_OUT; + goto free_lock; + } + + gsi_ctx->scratch.word0.val = gsihal_read_reg_n(GSI_EE_n_CNTXT_SCRATCH_0, + gsi_ctx->per.ee); + + *code = gsi_ctx->scratch.word0.s.generic_ee_cmd_return_val; + + if (prmy_scnd_fc) + res = (gsi_ctx->scratch.word0.s.generic_ee_cmd_return_val == + GSI_GEN_EE_CMD_RETURN_VAL_FLOW_CONTROL_SECONDARY)? + GSI_STATUS_SUCCESS:-GSI_STATUS_ERROR; + else + res = (gsi_ctx->scratch.word0.s.generic_ee_cmd_return_val == + GSI_GEN_EE_CMD_RETURN_VAL_FLOW_CONTROL_PRIMARY)? + GSI_STATUS_SUCCESS:-GSI_STATUS_ERROR; + +free_lock: + __gsi_config_glob_irq(gsi_ctx->per.ee, + gsihal_get_glob_irq_en_gp_int1_mask(), 0); + mutex_unlock(&gsi_ctx->mlock); + + return res; +} +EXPORT_SYMBOL(gsi_query_flow_control_state_ee); + + +int gsi_map_virtual_ch_to_per_ep(u32 ee, u32 chan_num, u32 per_ep_index) +{ + if (!gsi_ctx) { + pr_err("%s:%d gsi context not allocated\n", __func__, __LINE__); + return -GSI_STATUS_NODEV; + } + + if (!gsi_ctx->base) { + GSIERR("access to GSI HW has not been mapped\n"); + return -GSI_STATUS_INVALID_PARAMS; + } + + gsihal_write_reg_nk(GSI_MAP_EE_n_CH_k_VP_TABLE, + ee, chan_num, per_ep_index); + + return 0; +} +EXPORT_SYMBOL(gsi_map_virtual_ch_to_per_ep); + +void gsi_wdi3_write_evt_ring_db(unsigned long evt_ring_hdl, + uint32_t db_addr_low, uint32_t db_addr_high) +{ + if (!gsi_ctx) { + pr_err("%s:%d gsi context not allocated\n", __func__, __LINE__); + return; + } + + if (gsi_ctx->per.ver >= GSI_VER_2_9) { + gsihal_write_reg_nk(GSI_EE_n_EV_CH_k_CNTXT_10, + gsi_ctx->per.ee, evt_ring_hdl, db_addr_low); + + gsihal_write_reg_nk(GSI_EE_n_EV_CH_k_CNTXT_11, + gsi_ctx->per.ee, evt_ring_hdl, db_addr_high); + } else { + gsihal_write_reg_nk(GSI_EE_n_EV_CH_k_CNTXT_12, + gsi_ctx->per.ee, evt_ring_hdl, db_addr_low); + + gsihal_write_reg_nk(GSI_EE_n_EV_CH_k_CNTXT_13, + gsi_ctx->per.ee, evt_ring_hdl, db_addr_high); + } +} +EXPORT_SYMBOL(gsi_wdi3_write_evt_ring_db); + +int gsi_get_refetch_reg(unsigned long chan_hdl, bool is_rp) +{ + if (is_rp) { + return gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_RE_FETCH_READ_PTR, + gsi_ctx->per.ee, chan_hdl); + } else { + return gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR, + gsi_ctx->per.ee, chan_hdl); + } +} +EXPORT_SYMBOL(gsi_get_refetch_reg); + +/* + * ; +------------------------------------------------------+ + * ; | NTN3 Rx Channel Scratch | + * ; +-------------+--------------------------------+-------+ + * ; | 32-bit word | Field | Bits | + * ; +-------------+--------------------------------+-------+ + * ; | 4 | NTN_PENDING_DB_AFTER_ROLLBACK | 18-18 | + * ; +-------------+--------------------------------+-------+ + * ; | 5 | NTN_MSI_DB_INDEX_VALUE | 0-31 | + * ; +-------------+--------------------------------+-------+ + * ; | 6 | NTN_RX_CHAIN_COUNTER | 0-31 | + * ; +-------------+--------------------------------+-------+ + * ; | 7 | NTN_RX_ERR_COUNTER | 0-31 | + * ; +-------------+--------------------------------+-------+ + * ; | 8 | NTN_ACCUMULATED_TRES_HANDLED | 0-31 | + * ; +-------------+--------------------------------+-------+ + * ; | 9 | NTN_ROLLBACKS_COUNTER | 0-31 | + * ; +-------------+--------------------------------+-------+ + * ; | FOR_SEQ_HIGH| NTN_MSI_DB_COUNT | 0-31 | + * ; +-------------+--------------------------------+-------+ + * + * ; +------------------------------------------------------+ + * ; | NTN3 Tx Channel Scratch | + * ; +-------------+--------------------------------+-------+ + * ; | 32-bit word | Field | Bits | + * ; +-------------+--------------------------------+-------+ + * ; | 4 | NTN_PENDING_DB_AFTER_ROLLBACK | 18-18 | + * ; +-------------+--------------------------------+-------+ + * ; | 5 | NTN_MSI_DB_INDEX_VALUE | 0-31 | + * ; +-------------+--------------------------------+-------+ + * ; | 6 | TX_DERR_COUNTER | 0-31 | + * ; +-------------+--------------------------------+-------+ + * ; | 7 | NTN_TX_OOB_COUNTER | 0-31 | + * ; +-------------+--------------------------------+-------+ + * ; | 8 | NTN_ACCUMULATED_TRES_HANDLED | 0-31 | + * ; +-------------+--------------------------------+-------+ + * ; | 9 | NTN_ROLLBACKS_COUNTER | 0-31 | + * ; +-------------+--------------------------------+-------+ + * ; | FOR_SEQ_HIGH| NTN_MSI_DB_COUNT | 0-31 | + * ; +-------------+--------------------------------+-------+ + */ +int gsi_ntn3_client_stats_get(unsigned ep_id, int scratch_id, unsigned chan_hdl) +{ + switch (scratch_id) { + case -1: + return gsihal_read_reg_n(GSI_GSI_SHRAM_n, GSI_GSI_SHRAM_n_EP_FOR_SEQ_HIGH_N_GET(ep_id)); + case 4: + return (gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_SCRATCH_4, gsi_ctx->per.ee, + chan_hdl) >> GSI_NTN3_PENDING_DB_AFTER_RB_MASK) & + GSI_NTN3_PENDING_DB_AFTER_RB_SHIFT; + break; + case 5: + return gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_SCRATCH_5, gsi_ctx->per.ee, chan_hdl); + break; + case 6: + return gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_SCRATCH_6, gsi_ctx->per.ee, chan_hdl); + break; + case 7: + return gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_SCRATCH_7, gsi_ctx->per.ee, chan_hdl); + break; + case 8: + return gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_SCRATCH_8, gsi_ctx->per.ee, chan_hdl); + break; + case 9: + return gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_SCRATCH_9, gsi_ctx->per.ee, chan_hdl); + break; + default: + GSIERR("invalid scratch id %d\n", scratch_id); + return 0; + } + return 0; +} +EXPORT_SYMBOL(gsi_ntn3_client_stats_get); + +int gsi_get_drop_stats(unsigned long ep_id, int scratch_id, + unsigned long chan_hdl) +{ +#define GSI_RTK_ERR_STATS_MASK 0xFFFF +#define GSI_NTN_ERR_STATS_MASK 0xFFFFFFFF +#define GSI_AQC_RX_STATUS_MASK 0x1FFF +#define GSI_AQC_RX_STATUS_SHIFT 0 +#define GSI_AQC_RDM_ERR_MASK 0x1FFF0000 +#define GSI_AQC_RDM_ERR_SHIFT 16 + + uint16_t rx_status; + uint16_t rdm_err; + uint32_t val; + + /* on newer versions we can read the ch scratch directly from reg */ + if (gsi_ctx->per.ver >= GSI_VER_3_0) { + switch (scratch_id) { + case 5: + return gsihal_read_reg_nk( + GSI_EE_n_GSI_CH_k_SCRATCH_5, + gsi_ctx->per.ee, + chan_hdl) & GSI_RTK_ERR_STATS_MASK; + break; + case 6: + return gsihal_read_reg_nk( + GSI_EE_n_GSI_CH_k_SCRATCH_6, + gsi_ctx->per.ee, + chan_hdl) & GSI_NTN_ERR_STATS_MASK; + break; + case 7: + val = gsihal_read_reg_nk( + GSI_EE_n_GSI_CH_k_SCRATCH_7, + gsi_ctx->per.ee, + chan_hdl); + rx_status = (val & GSI_AQC_RX_STATUS_MASK) + >> GSI_AQC_RX_STATUS_SHIFT; + rdm_err = (val & GSI_AQC_RDM_ERR_MASK) + >> (GSI_AQC_RDM_ERR_SHIFT); + return rx_status + rdm_err; + break; + default: + GSIERR("invalid scratch id %d\n", scratch_id); + return 0; + } + + /* on older versions we need to read the scratch from SHRAM */ + } else { + /* RTK use scratch 5 */ + if (scratch_id == 5) { + /* + * each channel context is 6 lines of 8 bytes, but n in + * SHRAM_n is in 4 bytes offsets, so multiplying ep_id + * by 6*2=12 will give the beginning of the required + * channel context, and then need to add 7 since the + * channel context layout has the ring rbase (8 bytes) + * + channel scratch 0-4 (20 bytes) so adding + * additional 28/4 = 7 to get to scratch 5 of the + * required channel. + */ + return gsihal_read_reg_n( + GSI_GSI_SHRAM_n, + ep_id * 12 + 7) & GSI_RTK_ERR_STATS_MASK; + } + } + return 0; +} +EXPORT_SYMBOL(gsi_get_drop_stats); + +int gsi_get_wp(unsigned long chan_hdl) +{ + return gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_CNTXT_6, gsi_ctx->per.ee, + chan_hdl); +} +EXPORT_SYMBOL(gsi_get_wp); + +void gsi_wdi3_dump_register(unsigned long chan_hdl) +{ + uint32_t val; + + if (!gsi_ctx) { + pr_err("%s:%d gsi context not allocated\n", __func__, __LINE__); + return; + } + GSIDBG("reg dump ch id %ld\n", chan_hdl); + val = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_CNTXT_0, + gsi_ctx->per.ee, chan_hdl); + GSIDBG("GSI_EE_n_GSI_CH_k_CNTXT_0 0x%x\n", val); + val = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_CNTXT_1, + gsi_ctx->per.ee, chan_hdl); + GSIDBG("GSI_EE_n_GSI_CH_k_CNTXT_1 0x%x\n", val); + val = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_CNTXT_2, + gsi_ctx->per.ee, chan_hdl); + GSIDBG("GSI_EE_n_GSI_CH_k_CNTXT_2 0x%x\n", val); + val = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_CNTXT_3, + gsi_ctx->per.ee, chan_hdl); + GSIDBG("GSI_EE_n_GSI_CH_k_CNTXT_3 0x%x\n", val); + val = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_CNTXT_4, + gsi_ctx->per.ee, chan_hdl); + GSIDBG("GSI_EE_n_GSI_CH_k_CNTXT_4 0x%x\n", val); + val = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_CNTXT_5, + gsi_ctx->per.ee, chan_hdl); + GSIDBG("GSI_EE_n_GSI_CH_k_CNTXT_5 0x%x\n", val); + val = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_CNTXT_6, + gsi_ctx->per.ee, chan_hdl); + GSIDBG("GSI_EE_n_GSI_CH_k_CNTXT_6 0x%x\n", val); + val = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_CNTXT_7, + gsi_ctx->per.ee, chan_hdl); + GSIDBG("GSI_EE_n_GSI_CH_k_CNTXT_7 0x%x\n", val); + + val = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_RE_FETCH_READ_PTR, + gsi_ctx->per.ee, chan_hdl); + GSIDBG("GSI_EE_n_GSI_CH_k_RE_FETCH_READ_PTR 0x%x\n", val); + val = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR, + gsi_ctx->per.ee, chan_hdl); + GSIDBG("GSI_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR 0x%x\n", val); + val = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_QOS, + gsi_ctx->per.ee, chan_hdl); + GSIDBG("GSI_EE_n_GSI_CH_k_QOS 0x%x\n", val); + val = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_SCRATCH_0, + gsi_ctx->per.ee, chan_hdl); + GSIDBG("GSI_EE_n_GSI_CH_k_SCRATCH_0 0x%x\n", val); + val = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_SCRATCH_1, + gsi_ctx->per.ee, chan_hdl); + GSIDBG("GSI_EE_n_GSI_CH_k_SCRATCH_1 0x%x\n", val); + val = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_SCRATCH_2, + gsi_ctx->per.ee, chan_hdl); + GSIDBG("GSI_EE_n_GSI_CH_k_SCRATCH_2 0x%x\n", val); + val = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_SCRATCH_3, + gsi_ctx->per.ee, chan_hdl); + GSIDBG("GSI_EE_n_GSI_CH_k_SCRATCH_3 0x%x\n", val); +} +EXPORT_SYMBOL(gsi_wdi3_dump_register); + +int gsi_query_msi_addr(unsigned long chan_hdl, phys_addr_t *addr) +{ + if (!gsi_ctx) { + pr_err("%s:%d gsi context not allocated\n", __func__, __LINE__); + return -GSI_STATUS_NODEV; + } + + if (chan_hdl >= gsi_ctx->max_ch) { + GSIERR("bad params chan_hdl=%lu\n", chan_hdl); + return -GSI_STATUS_INVALID_PARAMS; + } + + if (gsi_ctx->chan[chan_hdl].state == GSI_CHAN_STATE_NOT_ALLOCATED) { + GSIERR("bad state %d\n", + gsi_ctx->chan[chan_hdl].state); + return -GSI_STATUS_UNSUPPORTED_OP; + } + + *addr = (phys_addr_t)(gsi_ctx->per.phys_addr + + gsihal_get_reg_nk_ofst(GSI_EE_n_GSI_CH_k_CNTXT_8, + gsi_ctx->per.ee, chan_hdl)); + + return 0; +} +EXPORT_SYMBOL(gsi_query_msi_addr); + +int gsi_query_device_msi_addr(u64 *addr) +{ + if (!gsi_ctx) { + pr_err("%s:%d gsi context not allocated\n", __func__, __LINE__); + return -GSI_STATUS_NODEV; + } + + if (gsi_ctx->msi_addr_set) + *addr = gsi_ctx->msi_addr; + else + *addr = 0; + + GSIDBG("Device MSI Addr: 0x%lx", *addr); + return 0; +} +EXPORT_SYMBOL(gsi_query_device_msi_addr); + + +uint64_t gsi_read_event_ring_wp(int evtr_id, int ee) +{ + uint64_t wp; + + wp = gsihal_read_reg_nk(GSI_EE_n_EV_CH_k_CNTXT_6, + ee, evtr_id); + wp |= ((uint64_t)gsihal_read_reg_nk(GSI_EE_n_EV_CH_k_CNTXT_7, + ee, evtr_id)) << 32; + + return wp; +} +EXPORT_SYMBOL(gsi_read_event_ring_wp); + +uint64_t gsi_read_event_ring_bp(int evt_hdl) +{ + return gsi_ctx->evtr[evt_hdl].ring.base; +} +EXPORT_SYMBOL(gsi_read_event_ring_bp); + +uint64_t gsi_get_evt_ring_rp(int evt_hdl) +{ + return gsi_ctx->evtr[evt_hdl].props.gsi_read_event_ring_rp( + &gsi_ctx->evtr[evt_hdl].props, evt_hdl, gsi_ctx->per.ee); +} +EXPORT_SYMBOL(gsi_get_evt_ring_rp); + +uint64_t gsi_read_chan_ring_rp(int chan_id, int ee) +{ + uint64_t rp; + + rp = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_CNTXT_4, + ee, chan_id); + rp |= ((uint64_t)gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_CNTXT_5, + ee, chan_id)) << 32; + + return rp; +} +EXPORT_SYMBOL(gsi_read_chan_ring_rp); + +uint64_t gsi_read_chan_ring_wp(int chan_id, int ee) +{ + uint64_t wp; + + wp = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_CNTXT_6, + ee, chan_id); + wp |= ((uint64_t)gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_CNTXT_7, + ee, chan_id)) << 32; + + return wp; +} +EXPORT_SYMBOL(gsi_read_chan_ring_wp); + +uint64_t gsi_read_chan_ring_bp(int chan_hdl) +{ + return gsi_ctx->chan[chan_hdl].ring.base; +} +EXPORT_SYMBOL(gsi_read_chan_ring_bp); + +uint64_t gsi_read_chan_ring_re_fetch_wp(int chan_id, int ee) +{ + uint64_t wp; + + wp = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR, + ee, chan_id); + + return wp; +} +EXPORT_SYMBOL(gsi_read_chan_ring_re_fetch_wp); + +enum gsi_chan_prot gsi_get_chan_prot_type(int chan_hdl) +{ + return gsi_ctx->chan[chan_hdl].props.prot; +} +EXPORT_SYMBOL(gsi_get_chan_prot_type); + +enum gsi_chan_state gsi_get_chan_state(int chan_hdl) +{ + return gsi_ctx->chan[chan_hdl].state; +} +EXPORT_SYMBOL(gsi_get_chan_state); + +int gsi_get_chan_poll_mode(int chan_hdl) +{ + return atomic_read(&gsi_ctx->chan[chan_hdl].poll_mode); +} +EXPORT_SYMBOL(gsi_get_chan_poll_mode); + +uint32_t gsi_get_ring_len(int chan_hdl) +{ + return gsi_ctx->chan[chan_hdl].ring.len; +} +EXPORT_SYMBOL(gsi_get_ring_len); + +uint8_t gsi_get_chan_props_db_in_bytes(int chan_hdl) +{ + return gsi_ctx->chan[chan_hdl].props.db_in_bytes; +} +EXPORT_SYMBOL(gsi_get_chan_props_db_in_bytes); + +int gsi_get_peripheral_ee(void) +{ + return gsi_ctx->per.ee; +} +EXPORT_SYMBOL(gsi_get_peripheral_ee); + +uint32_t gsi_get_chan_stop_stm(int chan_id, int ee) +{ + uint32_t ch_scratch; + ch_scratch = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_SCRATCH_4, ee, chan_id); + /* Only bits 28 - 31 for STM */ + return ((ch_scratch & 0xF0000000) >> 24); +} +EXPORT_SYMBOL(gsi_get_chan_stop_stm); + +enum gsi_evt_ring_elem_size gsi_get_evt_ring_re_size(int evt_hdl) +{ + return gsi_ctx->evtr[evt_hdl].props.re_size; +} +EXPORT_SYMBOL(gsi_get_evt_ring_re_size); + +uint32_t gsi_get_evt_ring_len(int evt_hdl) +{ + return gsi_ctx->evtr[evt_hdl].ring.len; +} +EXPORT_SYMBOL(gsi_get_evt_ring_len); + +void gsi_update_almst_empty_thrshold(unsigned long chan_hdl, unsigned short threshold) +{ + gsihal_write_reg_nk(GSI_EE_n_CH_k_CH_ALMST_EMPTY_THRSHOLD, + gsi_ctx->per.ee, chan_hdl, threshold); +} +EXPORT_SYMBOL(gsi_update_almst_empty_thrshold); + +static union __packed gsi_channel_scratch __gsi_update_mhi_channel_scratch( + unsigned long chan_hdl, struct __packed gsi_mhi_channel_scratch mscr) +{ + union __packed gsi_channel_scratch scr; + + /* below sequence is not atomic. assumption is sequencer specific fields + * will remain unchanged across this sequence + */ + + /* READ */ + scr.data.word1 = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_SCRATCH_0, + gsi_ctx->per.ee, chan_hdl); + scr.data.word2 = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_SCRATCH_1, + gsi_ctx->per.ee, chan_hdl); + scr.data.word3 = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_SCRATCH_2, + gsi_ctx->per.ee, chan_hdl); + scr.data.word4 = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_SCRATCH_3, + gsi_ctx->per.ee, chan_hdl); + + /* UPDATE */ + scr.mhi.polling_mode = mscr.polling_mode; + + if (gsi_ctx->per.ver < GSI_VER_2_5) { + scr.mhi.max_outstanding_tre = mscr.max_outstanding_tre; + scr.mhi.outstanding_threshold = mscr.outstanding_threshold; + } + + /* WRITE */ + gsihal_write_reg_nk(GSI_EE_n_GSI_CH_k_SCRATCH_0, + gsi_ctx->per.ee, chan_hdl, scr.data.word1); + gsihal_write_reg_nk(GSI_EE_n_GSI_CH_k_SCRATCH_1, + gsi_ctx->per.ee, chan_hdl, scr.data.word2); + gsihal_write_reg_nk(GSI_EE_n_GSI_CH_k_SCRATCH_2, + gsi_ctx->per.ee, chan_hdl, scr.data.word3); + gsihal_write_reg_nk(GSI_EE_n_GSI_CH_k_SCRATCH_3, + gsi_ctx->per.ee, chan_hdl, scr.data.word4); + + return scr; +} +/** + * gsi_get_hw_profiling_stats() - Query GSI HW profiling stats + * @stats: [out] stats blob from client populated by driver + * + * Returns: 0 on success, negative on failure + * + */ +int gsi_get_hw_profiling_stats(struct gsi_hw_profiling_data *stats) +{ + if (stats == NULL) { + GSIERR("bad parms NULL stats == NULL\n"); + return -EINVAL; + } + + stats->bp_cnt = (u64)gsihal_read_reg( + GSI_GSI_MCS_PROFILING_BP_CNT_LSB) + + ((u64)gsihal_read_reg( + GSI_GSI_MCS_PROFILING_BP_CNT_MSB) << 32); + stats->bp_and_pending_cnt = (u64)gsihal_read_reg( + GSI_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB) + + ((u64)gsihal_read_reg( + GSI_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB) << 32); + stats->mcs_busy_cnt = (u64)gsihal_read_reg( + GSI_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB) + + ((u64)gsihal_read_reg( + GSI_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB) << 32); + stats->mcs_idle_cnt = (u64)gsihal_read_reg( + GSI_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB) + + ((u64)gsihal_read_reg( + GSI_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB) << 32); + + return 0; +} + +/** + * gsi_get_fw_version() - Query GSI FW version + * @ver: [out] ver blob from client populated by driver + * + * Returns: 0 on success, negative on failure + * + */ +int gsi_get_fw_version(struct gsi_fw_version *ver) +{ + u32 raw = 0; + + if (ver == NULL) { + GSIERR("bad parms: ver == NULL\n"); + return -EINVAL; + } + + if (gsi_ctx->per.ver < GSI_VER_3_0) + raw = gsihal_read_reg_n(GSI_GSI_INST_RAM_n, + GSI_INST_RAM_FW_VER_OFFSET); + else + raw = gsihal_read_reg_n(GSI_GSI_INST_RAM_n, + GSI_INST_RAM_FW_VER_GSI_3_0_OFFSET); + + ver->hw = (raw & GSI_INST_RAM_FW_VER_HW_MASK) >> + GSI_INST_RAM_FW_VER_HW_SHIFT; + ver->flavor = (raw & GSI_INST_RAM_FW_VER_FLAVOR_MASK) >> + GSI_INST_RAM_FW_VER_FLAVOR_SHIFT; + ver->fw = (raw & GSI_INST_RAM_FW_VER_FW_MASK) >> + GSI_INST_RAM_FW_VER_FW_SHIFT; + + return 0; +} + +#if IS_ENABLED(CONFIG_QCOM_VA_MINIDUMP) +static int qcom_va_md_gsi_notif_handler(struct notifier_block *this, + unsigned long event, void *ptr) +{ + struct va_md_entry entry; + + strlcpy(entry.owner, "gsi_mini", sizeof(entry.owner)); + entry.vaddr = (unsigned long)gsi_ctx; + entry.size = sizeof(struct gsi_ctx); + qcom_va_md_add_region(&entry); + return NOTIFY_OK; +} + +static struct notifier_block qcom_va_md_gsi_notif_blk = { + .notifier_call = qcom_va_md_gsi_notif_handler, + .priority = INT_MAX, +}; +#endif + +static int msm_gsi_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + int result; + + pr_debug("gsi_probe\n"); + gsi_ctx = devm_kzalloc(dev, sizeof(*gsi_ctx), GFP_KERNEL); + if (!gsi_ctx) { + dev_err(dev, "failed to allocated gsi context\n"); + return -ENOMEM; + } + + gsi_ctx->ipc_logbuf = ipc_log_context_create(GSI_IPC_LOG_PAGES, + "gsi", MINIDUMP_MASK); + if (gsi_ctx->ipc_logbuf == NULL) + GSIERR("failed to create IPC log, continue...\n"); + + result = of_property_read_u32(pdev->dev.of_node, "qcom,num-msi", + &gsi_ctx->msi.num); + if (result) + GSIERR("No MSIs configured\n"); + else { + if (gsi_ctx->msi.num > GSI_MAX_NUM_MSI) { + GSIERR("Num MSIs %u larger than max %u, normalizing\n", + gsi_ctx->msi.num, + GSI_MAX_NUM_MSI); + gsi_ctx->msi.num = GSI_MAX_NUM_MSI; + } else GSIDBG("Num MSIs=%u\n", gsi_ctx->msi.num); + } + + gsi_ctx->dev = dev; + init_completion(&gsi_ctx->gen_ee_cmd_compl); + gsi_debugfs_init(); + +#if IS_ENABLED(CONFIG_QCOM_VA_MINIDUMP) + result = qcom_va_md_register("gsi_mini", &qcom_va_md_gsi_notif_blk); + + if(result) + GSIERR("gsi mini qcom_va_md_register failed = %d\n", result); + else + GSIDBG("gsi mini qcom_va_md_register success\n"); +#endif + + return 0; +} + +static struct platform_driver msm_gsi_driver = { + .probe = msm_gsi_probe, + .driver = { + .name = "gsi", + .of_match_table = msm_gsi_match, + }, +}; + +static struct platform_device *pdev; + +/** + * Module Init. + */ +static int __init gsi_init(void) +{ + int ret; + + pr_debug("%s\n", __func__); + + ret = platform_driver_register(&msm_gsi_driver); + if (ret < 0) + goto out; + + if (running_emulation) { + pdev = platform_device_register_simple("gsi", -1, NULL, 0); + if (IS_ERR(pdev)) { + ret = PTR_ERR(pdev); + platform_driver_unregister(&msm_gsi_driver); + goto out; + } + } + +out: + return ret; +} +arch_initcall(gsi_init); + +/* + * Module exit. + */ +static void __exit gsi_exit(void) +{ + if (running_emulation && pdev) + platform_device_unregister(pdev); + platform_driver_unregister(&msm_gsi_driver); +} +module_exit(gsi_exit); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("Generic Software Interface (GSI)"); diff --git a/qcom/opensource/dataipa/drivers/platform/msm/gsi/gsi.h b/qcom/opensource/dataipa/drivers/platform/msm/gsi/gsi.h new file mode 100644 index 0000000000..4476a37122 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/gsi/gsi.h @@ -0,0 +1,2582 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved. + * + * Copyright (c) 2022, 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef GSI_H +#define GSI_H + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * The following for adding code (ie. for EMULATION) not found on x86. + */ +#if defined(CONFIG_IPA_EMULATION) +# include "gsi_emulation_stubs.h" +#endif + +#define GSI_ASSERT() \ + BUG() + +#define GSI_CHAN_MAX 36 +#define GSI_EVT_RING_MAX 31 +#define GSI_NO_EVT_ERINDEX 255 +#define GSI_ISR_CACHE_MAX 20 +#define MAX_CHANNELS_SHARING_EVENT_RING 2 +#define MINIDUMP_MASK 0x10000 + +#define GSI_INST_RAM_FW_VER_OFFSET (0) +#define GSI_INST_RAM_FW_VER_GSI_3_0_OFFSET (64) +#define GSI_INST_RAM_FW_VER_GSI_5_5_OFFSET (66) +#define GSI_INST_RAM_FW_VER_HW_MASK (0xFC00) +#define GSI_INST_RAM_FW_VER_HW_SHIFT (10) +#define GSI_INST_RAM_FW_VER_FLAVOR_MASK (0x380) +#define GSI_INST_RAM_FW_VER_FLAVOR_SHIFT (7) +#define GSI_INST_RAM_FW_VER_FW_MASK (0x7f) +#define GSI_INST_RAM_FW_VER_FW_SHIFT (0) + +#define GSI_IPC_LOGGING(buf, fmt, args...) \ + do { \ + if (buf) \ + ipc_log_string((buf), fmt, __func__, __LINE__, \ + ## args); \ + } while (0) + +#define GSIDBG(fmt, args...) \ + do { \ + dev_dbg(gsi_ctx->dev, "%s:%d " fmt, __func__, __LINE__, \ + ## args);\ + if (gsi_ctx) { \ + GSI_IPC_LOGGING(gsi_ctx->ipc_logbuf, \ + "%s:%d " fmt, ## args); \ + GSI_IPC_LOGGING(gsi_ctx->ipc_logbuf_low, \ + "%s:%d " fmt, ## args); \ + } \ + } while (0) + +#define GSIDBG_LOW(fmt, args...) \ + do { \ + dev_dbg(gsi_ctx->dev, "%s:%d " fmt, __func__, __LINE__, \ + ## args);\ + if (gsi_ctx) { \ + GSI_IPC_LOGGING(gsi_ctx->ipc_logbuf_low, \ + "%s:%d " fmt, ## args); \ + } \ + } while (0) + +#define GSIERR(fmt, args...) \ + do { \ + dev_err(gsi_ctx->dev, "%s:%d " fmt, __func__, __LINE__, \ + ## args);\ + if (gsi_ctx) { \ + GSI_IPC_LOGGING(gsi_ctx->ipc_logbuf, \ + "%s:%d " fmt, ## args); \ + GSI_IPC_LOGGING(gsi_ctx->ipc_logbuf_low, \ + "%s:%d " fmt, ## args); \ + } \ + } while (0) + +#define GSIERR_RL(fmt, args...) \ + do { \ + dev_err_ratelimited(gsi_ctx->dev, "%s:%d " fmt, __func__, __LINE__, \ + ## args);\ + if (gsi_ctx) { \ + GSI_IPC_LOGGING(gsi_ctx->ipc_logbuf, \ + "%s:%d " fmt, ## args); \ + GSI_IPC_LOGGING(gsi_ctx->ipc_logbuf_low, \ + "%s:%d " fmt, ## args); \ + } \ + } while (0) + +#define GSI_IPC_LOG_PAGES 50 +#define GSI_MAX_NUM_MSI 2 + +enum gsi_ver { + GSI_VER_ERR = 0, + GSI_VER_1_0 = 1, + GSI_VER_1_2 = 2, + GSI_VER_1_3 = 3, + GSI_VER_2_0 = 4, + GSI_VER_2_2 = 5, + GSI_VER_2_5 = 6, + GSI_VER_2_7 = 7, + GSI_VER_2_9 = 8, + GSI_VER_2_11 = 9, + GSI_VER_3_0 = 10, + GSI_VER_5_2 = 11, + GSI_VER_5_5 = 12, + GSI_VER_6_0 = 13, + GSI_VER_MAX, +}; + +enum gsi_status { + GSI_STATUS_SUCCESS = 0, + GSI_STATUS_ERROR = 1, + GSI_STATUS_RING_INSUFFICIENT_SPACE = 2, + GSI_STATUS_RING_EMPTY = 3, + GSI_STATUS_RES_ALLOC_FAILURE = 4, + GSI_STATUS_BAD_STATE = 5, + GSI_STATUS_INVALID_PARAMS = 6, + GSI_STATUS_UNSUPPORTED_OP = 7, + GSI_STATUS_NODEV = 8, + GSI_STATUS_POLL_EMPTY = 9, + GSI_STATUS_EVT_RING_INCOMPATIBLE = 10, + GSI_STATUS_TIMED_OUT = 11, + GSI_STATUS_AGAIN = 12, + GSI_STATUS_PENDING_IRQ = 13, +}; + +enum gsi_intr_type { + GSI_INTR_MSI = 0x0, + GSI_INTR_IRQ = 0x1 +}; + +enum gsi_evt_err { + GSI_EVT_OUT_OF_BUFFERS_ERR = 0x0, + GSI_EVT_OUT_OF_RESOURCES_ERR = 0x1, + GSI_EVT_UNSUPPORTED_INTER_EE_OP_ERR = 0x2, + GSI_EVT_EVT_RING_EMPTY_ERR = 0x3, +}; + +/** + * gsi_evt_err_notify - event ring error callback info + * + * @user_data: cookie supplied in gsi_alloc_evt_ring + * @evt_id: type of error + * @err_desc: more info about the error + * + */ +struct gsi_evt_err_notify { + void *user_data; + enum gsi_evt_err evt_id; + uint16_t err_desc; +}; + +enum gsi_evt_chtype { + GSI_EVT_CHTYPE_MHI_EV = 0x0, + GSI_EVT_CHTYPE_XHCI_EV = 0x1, + GSI_EVT_CHTYPE_GPI_EV = 0x2, + GSI_EVT_CHTYPE_XDCI_EV = 0x3, + GSI_EVT_CHTYPE_WDI2_EV = 0x4, + GSI_EVT_CHTYPE_GCI_EV = 0x5, + GSI_EVT_CHTYPE_WDI3_EV = 0x6, + GSI_EVT_CHTYPE_MHIP_EV = 0x7, + GSI_EVT_CHTYPE_AQC_EV = 0x8, + GSI_EVT_CHTYPE_11AD_EV = 0x9, + GSI_EVT_CHTYPE_RTK_EV = 0xC, + GSI_EVT_CHTYPE_NTN_EV = 0xD, + GSI_EVT_CHTYPE_WDI3_V2_EV = 0XF, +}; + +enum gsi_evt_ring_elem_size { + GSI_EVT_RING_RE_SIZE_4B = 4, + GSI_EVT_RING_RE_SIZE_8B = 8, + GSI_EVT_RING_RE_SIZE_16B = 16, + GSI_EVT_RING_RE_SIZE_32B = 32, +}; + +/** + * gsi_evt_ring_props - Event ring related properties + * + * @intf: interface type (of the associated channel) + * @intr: interrupt type + * @re_size: size of event ring element + * @ring_len: length of ring in bytes (must be integral multiple of + * re_size) + * @ring_base_addr: physical base address of ring. Address must be aligned to + * ring_len rounded to power of two + * @ring_base_vaddr: virtual base address of ring (set to NULL when not + * applicable) + * @int_modt: cycles base interrupt moderation (32KHz clock) + * @int_modc: interrupt moderation packet counter + * @intvec: write data for MSI write + * @msi_irq: MSI irq number + * @msi_addr: MSI address, APSS_GICA_SETSPI_NSR reg address + * @msi_clear_addr: MSI address, APSS_GICA_CLRSPI_NSR reg address + * @rp_update_addr: physical address to which event read pointer should be + * written on every event generation. must be set to 0 when + * no update is desdired + * @rp_update_vaddr: virtual address of event ring read pointer (set to NULL + * when not applicable) + * @exclusive: if true, only one GSI channel can be associated with this + * event ring. if false, the event ring can be shared among + * multiple GSI channels but in that case no polling + * (GSI_CHAN_MODE_POLL) is supported on any of those channels + * @err_cb: error notification callback + * @user_data: cookie used for error notifications + * @evchid_valid: is evchid valid? + * @evchid: the event ID that is being specifically requested (this is + * relevant for MHI where doorbell routing requires ERs to be + * physically contiguous) + * @gsi_read_event_ring_rp: function reads the value of the event ring RP. + */ +struct gsi_evt_ring_props { + enum gsi_evt_chtype intf; + enum gsi_intr_type intr; + enum gsi_evt_ring_elem_size re_size; + uint32_t ring_len; + uint64_t ring_base_addr; + void *ring_base_vaddr; + uint16_t int_modt; + uint8_t int_modc; + uint32_t intvec; + uint32_t msi_irq; + uint64_t msi_addr; + uint64_t msi_addr_iore_mapped; + uint64_t msi_clear_addr; + uint64_t rp_update_addr; + void *rp_update_vaddr; + bool exclusive; + void (*err_cb)(struct gsi_evt_err_notify *notify); + void *user_data; + bool evchid_valid; + uint8_t evchid; + uint64_t (*gsi_read_event_ring_rp)(struct gsi_evt_ring_props *props, + uint8_t id, int ee); +}; + +enum gsi_chan_mode { + GSI_CHAN_MODE_CALLBACK = 0x0, + GSI_CHAN_MODE_POLL = 0x1, +}; + +enum gsi_chan_prot { + GSI_CHAN_PROT_MHI = 0x0, + GSI_CHAN_PROT_XHCI = 0x1, + GSI_CHAN_PROT_GPI = 0x2, + GSI_CHAN_PROT_XDCI = 0x3, + GSI_CHAN_PROT_WDI2 = 0x4, + GSI_CHAN_PROT_GCI = 0x5, + GSI_CHAN_PROT_WDI3 = 0x6, + GSI_CHAN_PROT_MHIP = 0x7, + GSI_CHAN_PROT_AQC = 0x8, + GSI_CHAN_PROT_11AD = 0x9, + GSI_CHAN_PROT_MHIC = 0xA, + GSI_CHAN_PROT_QDSS = 0xB, + GSI_CHAN_PROT_RTK = 0xC, + GSI_CHAN_PROT_NTN = 0xD, + GSI_CHAN_PROT_WDI3_V2 = 0XF, +}; + +enum gsi_max_prefetch { + GSI_ONE_PREFETCH_SEG = 0x0, + GSI_TWO_PREFETCH_SEG = 0x1 +}; + +enum gsi_per_evt { + GSI_PER_EVT_GLOB_ERROR, + GSI_PER_EVT_GLOB_GP1, + GSI_PER_EVT_GLOB_GP2, + GSI_PER_EVT_GLOB_GP3, + GSI_PER_EVT_GENERAL_BREAK_POINT, + GSI_PER_EVT_GENERAL_BUS_ERROR, + GSI_PER_EVT_GENERAL_CMD_FIFO_OVERFLOW, + GSI_PER_EVT_GENERAL_MCS_STACK_OVERFLOW, +}; +/** + * gsi_per_notify - Peripheral callback info + * + * @user_data: cookie supplied in gsi_register_device + * @evt_id: type of notification + * @err_desc: error related information + * + */ +struct gsi_per_notify { + void *user_data; + enum gsi_per_evt evt_id; + union { + uint16_t err_desc; + } data; +}; + + +/** + * gsi_per_props - Peripheral related properties + * + * @gsi: GSI core version + * @ee: EE where this driver and peripheral driver runs + * @intr: control interrupt type + * @intvec: write data for MSI write + * @msi_addr: MSI address + * @irq: IRQ number + * @phys_addr: physical address of GSI block + * @size: register size of GSI block + * @emulator_intcntrlr_addr: the location of emulator's interrupt control block + * @emulator_intcntrlr_size: the sise of emulator_intcntrlr_addr + * @emulator_intcntrlr_client_isr: client's isr. Called by the emulator's isr + * @mhi_er_id_limits_valid: valid flag for mhi_er_id_limits + * @mhi_er_id_limits: MHI event ring start and end ids + * @notify_cb: general notification callback + * @req_clk_cb: callback to request peripheral clock + * granted should be set to true if request is completed + * synchronously, false otherwise (peripheral needs + * to call gsi_complete_clk_grant later when request is + * completed) + * if this callback is not provided, then GSI will assume + * peripheral is clocked at all times + * @rel_clk_cb: callback to release peripheral clock + * @user_data: cookie used for notifications + * @clk_status_cb: callback to update the current msm bus clock vote + * @enable_clk_bug_on: enable IPA clock for dump saving before assert + * @skip_ieob_mask_wa: flag for skipping ieob_mask_wa + * All the callbacks are in interrupt context + * @tx_poll: propagate to relevant gsi channels that tx polling feature is on + * + */ +struct gsi_per_props { + enum gsi_ver ver; + unsigned int ee; + enum gsi_intr_type intr; + uint32_t intvec; + uint64_t msi_addr; + unsigned int irq; + phys_addr_t phys_addr; + unsigned long size; + phys_addr_t emulator_intcntrlr_addr; + unsigned long emulator_intcntrlr_size; + irq_handler_t emulator_intcntrlr_client_isr; + bool mhi_er_id_limits_valid; + uint32_t mhi_er_id_limits[2]; + void (*notify_cb)(struct gsi_per_notify *notify); + void (*req_clk_cb)(void *user_data, bool *granted); + int (*rel_clk_cb)(void *user_data); + void *user_data; + int (*clk_status_cb)(void); + void (*enable_clk_bug_on)(void); + void (*vote_clk_cb)(void); + void (*unvote_clk_cb)(void); + bool skip_ieob_mask_wa; + bool tx_poll; +}; + +enum gsi_chan_evt { + GSI_CHAN_EVT_INVALID = 0x0, + GSI_CHAN_EVT_SUCCESS = 0x1, + GSI_CHAN_EVT_EOT = 0x2, + GSI_CHAN_EVT_OVERFLOW = 0x3, + GSI_CHAN_EVT_EOB = 0x4, + GSI_CHAN_EVT_OOB = 0x5, + GSI_CHAN_EVT_DB_MODE = 0x6, + GSI_CHAN_EVT_UNDEFINED = 0x10, + GSI_CHAN_EVT_RE_ERROR = 0x11, +}; + +/** + * gsi_chan_xfer_veid - Virtual Channel ID + * + * @GSI_VEID_0: transfer completed for VEID 0 + * @GSI_VEID_1: transfer completed for VEID 1 + * @GSI_VEID_2: transfer completed for VEID 2 + * @GSI_VEID_3: transfer completed for VEID 3 + * @GSI_VEID_4: transfer completed for VEID 4 + * @GSI_VEID_5: transfer completed for VEID 5 + * @GSI_VEID_6: transfer completed for VEID 6 + * @GSI_VEID_7: transfer completed for VEID 7 + * @GSI_VEID_8: transfer completed for VEID 8 + * @GSI_VEID_9: transfer completed for VEID 9 + * @GSI_VEID_10: transfer completed for VEID 10 + * @GSI_VEID_11: transfer completed for VEID 11 + * @GSI_VEID_12: transfer completed for VEID 12 + * @GSI_VEID_13: transfer completed for VEID 13 + * @GSI_VEID_14: transfer completed for VEID 14 + * @GSI_VEID_15: transfer completed for VEID 15 + * @GSI_VEID_DEFAULT: used when veid is invalid + */ +enum gsi_chan_xfer_veid { + GSI_VEID_0 = 0, + GSI_VEID_1 = 1, + GSI_VEID_2 = 2, + GSI_VEID_3 = 3, + GSI_VEID_4 = 4, + GSI_VEID_5 = 5, + GSI_VEID_6 = 6, + GSI_VEID_7 = 7, + GSI_VEID_8 = 8, + GSI_VEID_9 = 9, + GSI_VEID_10 = 10, + GSI_VEID_11 = 11, + GSI_VEID_12 = 12, + GSI_VEID_13 = 13, + GSI_VEID_14 = 14, + GSI_VEID_15 = 15, + GSI_VEID_DEFAULT, + GSI_VEID_MAX +}; + +/** + * gsi_chan_xfer_notify - Channel callback info + * + * @chan_user_data: cookie supplied in gsi_alloc_channel + * @xfer_user_data: cookie of the gsi_xfer_elem that caused the + * event to be generated + * @evt_id: type of event triggered by the associated TRE + * (corresponding to xfer_user_data) + * @bytes_xfered: number of bytes transferred by the associated TRE + * (corresponding to xfer_user_data) + * @veid: virtual endpoint id. Valid for GCI completions only + * + */ +struct gsi_chan_xfer_notify { + void *chan_user_data; + void *xfer_user_data; + enum gsi_chan_evt evt_id; + uint16_t bytes_xfered; + uint8_t veid; +}; + +enum gsi_chan_err { + GSI_CHAN_INVALID_TRE_ERR = 0x0, + GSI_CHAN_NON_ALLOCATED_EVT_ACCESS_ERR = 0x1, + GSI_CHAN_OUT_OF_BUFFERS_ERR = 0x2, + GSI_CHAN_OUT_OF_RESOURCES_ERR = 0x3, + GSI_CHAN_UNSUPPORTED_INTER_EE_OP_ERR = 0x4, + GSI_CHAN_HWO_1_ERR = 0x5 +}; + +/** + * gsi_chan_err_notify - Channel general callback info + * + * @chan_user_data: cookie supplied in gsi_alloc_channel + * @evt_id: type of error + * @err_desc: more info about the error + * + */ +struct gsi_chan_err_notify { + void *chan_user_data; + enum gsi_chan_err evt_id; + uint16_t err_desc; +}; + +enum gsi_chan_ring_elem_size { + GSI_CHAN_RE_SIZE_4B = 4, + GSI_CHAN_RE_SIZE_8B = 8, + GSI_CHAN_RE_SIZE_16B = 16, + GSI_CHAN_RE_SIZE_32B = 32, + GSI_CHAN_RE_SIZE_64B = 64, +}; + +enum gsi_chan_use_db_eng { + GSI_CHAN_DIRECT_MODE = 0x0, + GSI_CHAN_DB_MODE = 0x1, +}; + +/** + * gsi_chan_props - Channel related properties + * + * @prot: interface type + * @dir: channel direction + * @ch_id: virtual channel ID + * @evt_ring_hdl: handle of associated event ring. set to ~0 if no + * event ring associated + * @re_size: size of channel ring element + * @ring_len: length of ring in bytes (must be integral multiple of + * re_size) + * @max_re_expected: maximal number of ring elements expected to be queued. + * used for data path statistics gathering. if 0 provided + * ring_len / re_size will be used. + * @ring_base_addr: physical base address of ring. Address must be aligned to + * ring_len rounded to power of two + * @ring_base_vaddr: virtual base address of ring (set to NULL when not + * applicable) + * @use_db_eng: 0 => direct mode (doorbells are written directly to RE + * engine) + * 1 => DB mode (doorbells are written to DB engine) + * @max_prefetch: limit number of pre-fetch segments for channel + * @low_weight: low channel weight (priority of channel for RE engine + * round robin algorithm); must be >= 1 + * @empty_lvl_threshold: + * The thershold number of free entries available in the + * receiving fifos of GSI-peripheral. If Smart PF mode + * is used, REE will fetch/send new TRE to peripheral only + * if peripheral's empty_level_count is higher than + * EMPTY_LVL_THRSHOLD defined for this channel + * @tx_poll: channel process completions in NAPI context + * @xfer_cb: transfer notification callback, this callback happens + * on event boundaries + * + * e.g. 1 + * + * out TD with 3 REs + * + * RE1: EOT=0, EOB=0, CHAIN=1; + * RE2: EOT=0, EOB=0, CHAIN=1; + * RE3: EOT=1, EOB=0, CHAIN=0; + * + * the callback will be triggered for RE3 using the + * xfer_user_data of that RE + * + * e.g. 2 + * + * in REs + * + * RE1: EOT=1, EOB=0, CHAIN=0; + * RE2: EOT=1, EOB=0, CHAIN=0; + * RE3: EOT=1, EOB=0, CHAIN=0; + * + * received packet consumes all of RE1, RE2 and part of RE3 + * for EOT condition. there will be three callbacks in below + * order + * + * callback for RE1 using GSI_CHAN_EVT_OVERFLOW + * callback for RE2 using GSI_CHAN_EVT_OVERFLOW + * callback for RE3 using GSI_CHAN_EVT_EOT + * + * @err_cb: error notification callback + * @cleanup_cb; cleanup rx-pkt/skb callback + * @chan_user_data: cookie used for notifications + * + * All the callbacks are in interrupt context + * + */ +struct gsi_chan_props { + enum gsi_chan_prot prot; + enum gsi_chan_dir dir; + uint8_t ch_id; + unsigned long evt_ring_hdl; + enum gsi_chan_ring_elem_size re_size; + uint32_t ring_len; + uint16_t max_re_expected; + uint64_t ring_base_addr; + uint8_t db_in_bytes; + uint8_t low_latency_en; + void *ring_base_vaddr; + enum gsi_chan_use_db_eng use_db_eng; + enum gsi_max_prefetch max_prefetch; + uint8_t low_weight; + enum gsi_prefetch_mode prefetch_mode; + uint8_t empty_lvl_threshold; + bool tx_poll; + void (*xfer_cb)(struct gsi_chan_xfer_notify *notify); + void (*err_cb)(struct gsi_chan_err_notify *notify); + void (*cleanup_cb)(void *chan_user_data, void *xfer_user_data); + void *chan_user_data; +}; + +enum gsi_xfer_flag { + GSI_XFER_FLAG_CHAIN = 0x1, + GSI_XFER_FLAG_EOB = 0x100, + GSI_XFER_FLAG_EOT = 0x200, + GSI_XFER_FLAG_BEI = 0x400 +}; + +enum gsi_xfer_elem_type { + GSI_XFER_ELEM_DATA, + GSI_XFER_ELEM_IMME_CMD, + GSI_XFER_ELEM_NOP, +}; + +/** + * gsi_gpi_channel_scratch - GPI protocol SW config area of + * channel scratch + * + * @dl_nlo_channel: Whether this is DL NLO Channel or not? Relevant for + * GSI 2.5 and above where DL NLO introduced. + * @max_outstanding_tre: Used for the prefetch management sequence by the + * sequencer. Defines the maximum number of allowed + * outstanding TREs in IPA/GSI (in Bytes). RE engine + * prefetch will be limited by this configuration. It + * is suggested to configure this value to IPA_IF + * channel TLV queue size times element size. To disable + * the feature in doorbell mode (DB Mode=1). Maximum + * outstanding TREs should be set to 64KB + * (or any value larger or equal to ring length . RLEN) + * The field is irrelevant starting GSI 2.5 where smart + * prefetch implemented by the H/W. + * @outstanding_threshold: Used for the prefetch management sequence by the + * sequencer. Defines the threshold (in Bytes) as to when + * to update the channel doorbell. Should be smaller than + * Maximum outstanding TREs. value. It is suggested to + * configure this value to 2 * element size. + * The field is irrelevant starting GSI 2.5 where smart + * prefetch implemented by the H/W. + */ +struct __packed gsi_gpi_channel_scratch { + uint64_t dl_nlo_channel:1; /* Relevant starting GSI 2.5 */ + uint64_t resvd1:63; + uint32_t resvd2:16; + uint32_t max_outstanding_tre:16; /* Not relevant starting GSI 2.5 */ + uint32_t resvd3:16; + uint32_t outstanding_threshold:16; /* Not relevant starting GSI 2.5 */ +}; + +/** + * gsi_mhi_channel_scratch - MHI protocol SW config area of + * channel scratch + * + * @mhi_host_wp_addr: Valid only when UL/DL Sync En is asserted. Defines + * address in host from which channel write pointer + * should be read in polling mode + * @assert_bit40: 1: bit #41 in address should be asserted upon + * IPA_IF.ProcessDescriptor routine (for MHI over PCIe + * transfers) + * 0: bit #41 in address should be deasserted upon + * IPA_IF.ProcessDescriptor routine (for non-MHI over + * PCIe transfers) + * @polling_configuration: Uplink channels: Defines timer to poll on MHI + * context. Range: 1 to 31 milliseconds. + * Downlink channel: Defines transfer ring buffer + * availability threshold to poll on MHI context in + * multiple of 8. Range: 0 to 31, meaning 0 to 258 ring + * elements. E.g., value of 2 indicates 16 ring elements. + * Valid only when Burst Mode Enabled is set to 1 + * @burst_mode_enabled: 0: Burst mode is disabled for this channel + * 1: Burst mode is enabled for this channel + * @polling_mode: 0: the channel is not in polling mode, meaning the + * host should ring DBs. + * 1: the channel is in polling mode, meaning the host + * @oob_mod_threshold: Defines OOB moderation threshold. Units are in 8 + * ring elements. + * should not ring DBs until notified of DB mode/OOB mode + * @max_outstanding_tre: Used for the prefetch management sequence by the + * sequencer. Defines the maximum number of allowed + * outstanding TREs in IPA/GSI (in Bytes). RE engine + * prefetch will be limited by this configuration. It + * is suggested to configure this value to IPA_IF + * channel TLV queue size times element size. + * To disable the feature in doorbell mode (DB Mode=1). + * Maximum outstanding TREs should be set to 64KB + * (or any value larger or equal to ring length . RLEN) + * The field is irrelevant starting GSI 2.5 where smart + * prefetch implemented by the H/W. + * @outstanding_threshold: Used for the prefetch management sequence by the + * sequencer. Defines the threshold (in Bytes) as to when + * to update the channel doorbell. Should be smaller than + * Maximum outstanding TREs. value. It is suggested to + * configure this value to min(TLV_FIFO_SIZE/2,8) * + * element size. + * The field is irrelevant starting GSI 2.5 where smart + * prefetch implemented by the H/W. + */ +struct __packed gsi_mhi_channel_scratch { + uint64_t mhi_host_wp_addr; + uint32_t rsvd1:1; + uint32_t assert_bit40:1; + uint32_t polling_configuration:5; + uint32_t burst_mode_enabled:1; + uint32_t polling_mode:1; + uint32_t oob_mod_threshold:5; + uint32_t resvd2:2; + uint32_t max_outstanding_tre:16; /* Not relevant starting GSI 2.5 */ + uint32_t resvd3:16; + uint32_t outstanding_threshold:16; /* Not relevant starting GSI 2.5 */ +}; + +/** + * gsi_mhi_channel_scratch_v2 - MHI protocol SW config area of + * channel scratch + * + * @mhi_host_wp_addr_lo: Valid only when UL/DL Sync En is asserted. Defines + * address in host from which channel write pointer + * should be read in polling mode + * @mhi_host_wp_addr_hi: Valid only when UL/DL Sync En is asserted. Defines + * address in host from which channel write pointer + * should be read in polling mode + * @assert_bit40: 1: bit #41 in address should be asserted upon + * IPA_IF.ProcessDescriptor routine (for MHI over PCIe + * transfers) + * 0: bit #41 in address should be deasserted upon + * IPA_IF.ProcessDescriptor routine (for non-MHI over + * PCIe transfers) + * @polling_configuration: Uplink channels: Defines timer to poll on MHI + * context. Range: 1 to 31 milliseconds. + * Downlink channel: Defines transfer ring buffer + * availability threshold to poll on MHI context in + * multiple of 8. Range: 0 to 31, meaning 0 to 258 ring + * elements. E.g., value of 2 indicates 16 ring elements. + * Valid only when Burst Mode Enabled is set to 1 + * @burst_mode_enabled: 0: Burst mode is disabled for this channel + * 1: Burst mode is enabled for this channel + * @polling_mode: 0: the channel is not in polling mode, meaning the + * host should ring DBs. + * 1: the channel is in polling mode, meaning the host + * @oob_mod_threshold: Defines OOB moderation threshold. Units are in 8 + * ring elements. + * should not ring DBs until notified of DB mode/OOB mode + */ +struct __packed gsi_mhi_channel_scratch_v2 { + uint32_t mhi_host_wp_addr_lo; + uint32_t mhi_host_wp_addr_hi : 9; + uint32_t polling_configuration : 5; + uint32_t rsvd1 : 18; + uint32_t rsvd2 : 1; + uint32_t assert_bit40 : 1; + uint32_t resvd3 : 5; + uint32_t burst_mode_enabled : 1; + uint32_t polling_mode : 1; + uint32_t oob_mod_threshold : 5; + uint32_t resvd4 : 18; /* Not configured by AP */ + uint32_t resvd5; /* Not configured by AP */ +}; + +/** + * gsi_xdci_channel_scratch - xDCI protocol SW config area of + * channel scratch + * + * @const_buffer_size: TRB buffer size in KB (similar to IPA aggregationi + * configuration). Must be aligned to Max USB Packet Size + * @xferrscidx: Transfer Resource Index (XferRscIdx). The hardware-assigned + * transfer resource index for the transfer, which was + * returned in response to the Start Transfer command. + * This field is used for "Update Transfer" command + * @last_trb_addr: Address (LSB - based on alignment restrictions) of + * last TRB in queue. Used to identify rollover case + * @depcmd_low_addr: Used to generate "Update Transfer" command + * @max_outstanding_tre: Used for the prefetch management sequence by the + * sequencer. Defines the maximum number of allowed + * outstanding TREs in IPA/GSI (in Bytes). RE engine + * prefetch will be limited by this configuration. It + * is suggested to configure this value to IPA_IF + * channel TLV queue size times element size. + * To disable the feature in doorbell mode (DB Mode=1) + * Maximum outstanding TREs should be set to 64KB + * (or any value larger or equal to ring length . RLEN) + * The field is irrelevant starting GSI 2.5 where smart + * prefetch implemented by the H/W. + * @depcmd_hi_addr: Used to generate "Update Transfer" command + * @outstanding_threshold: Used for the prefetch management sequence by the + * sequencer. Defines the threshold (in Bytes) as to when + * to update the channel doorbell. Should be smaller than + * Maximum outstanding TREs. value. It is suggested to + * configure this value to 2 * element size. for MBIM the + * suggested configuration is the element size. + * The field is irrelevant starting GSI 2.5 where smart + * prefetch implemented by the H/W. + */ +struct __packed gsi_xdci_channel_scratch { + uint32_t last_trb_addr:16; + uint32_t resvd1:4; + uint32_t xferrscidx:7; + uint32_t const_buffer_size:5; + uint32_t depcmd_low_addr; + uint32_t depcmd_hi_addr:8; + uint32_t resvd2:8; + uint32_t max_outstanding_tre:16; /* Not relevant starting GSI 2.5 */ + uint32_t resvd3:16; + uint32_t outstanding_threshold:16; /* Not relevant starting GSI 2.5 */ +}; + +/** + * gsi_wdi_channel_scratch - WDI protocol SW config area of + * channel scratch + * + * @wifi_rx_ri_addr_low: Low 32 bits of Transfer ring Read Index address. + * @wifi_rx_ri_addr_high: High 32 bits of Transfer ring Read Index address. + * @update_ri_moderation_threshold: Threshold N for Transfer ring Read Index + * N is the number of packets that IPA will + * process before Wifi transfer ring Ri will + * be updated. + * @update_ri_moderation_counter: This field is incremented with each TRE + * processed in MCS. + * @wdi_rx_tre_proc_in_progress: It is set if IPA IF returned BECAME FULL + * status after MCS submitted an inline immediate + * command to update the metadata. It allows MCS + * to know that it has to retry sending the TRE + * to IPA. + * @wdi_rx_vdev_id: Rx only. Initialized to 0xFF by SW after allocating channel + * and before starting it. Both FW_DESC and VDEV_ID are part + * of a scratch word that is Read/Write for both MCS and SW. + * To avoid race conditions, SW should not update this field + * after starting the channel. + * @wdi_rx_fw_desc: Rx only. Initialized to 0xFF by SW after allocating channel + * and before starting it. After Start, this is a Read only + * field for SW. + * @endp_metadatareg_offset: Rx only, the offset of IPA_ENDP_INIT_HDR_METADATA + * of the corresponding endpoint in 4B words from IPA + * base address. Read only field for MCS. + * Write for SW. + * @qmap_id: Rx only, used for setting metadata register in IPA. Read only field + * for MCS. Write for SW. + * @wdi_rx_pkt_length: If WDI_RX_TRE_PROC_IN_PROGRESS is set, this field is + * valid and contains the packet length of the TRE that + * needs to be submitted to IPA. + * @resv1: reserved bits. + * @pkt_comp_count: It is incremented on each AOS received. When event ring + * Write index is updated, it is decremented by the same + * amount. + * @stop_in_progress_stm: If a Stop request is in progress, this will indicate + * the current stage of processing of the stop within MCS + * @resv2: reserved bits. + * wdi_rx_qmap_id_internal: Initialized to 0 by MCS when the channel is + * allocated. It is updated to the current value of SW + * QMAP ID that is being written by MCS to the IPA + * metadata register. + */ +struct __packed gsi_wdi_channel_scratch { + uint32_t wifi_rx_ri_addr_low; + uint32_t wifi_rx_ri_addr_high; + uint32_t update_ri_moderation_threshold:5; + uint32_t update_ri_moderation_counter:6; + uint32_t wdi_rx_tre_proc_in_progress:1; + uint32_t resv1:4; + uint32_t wdi_rx_vdev_id:8; + uint32_t wdi_rx_fw_desc:8; + uint32_t endp_metadatareg_offset:16; + uint32_t qmap_id:16; + uint32_t wdi_rx_pkt_length:16; + uint32_t resv2:2; + uint32_t pkt_comp_count:11; + uint32_t stop_in_progress_stm:3; + uint32_t resv3:16; + uint32_t wdi_rx_qmap_id_internal:16; +}; + +/** + * gsi_wdi2_channel_scratch_lito - WDI protocol SW config area of + * channel scratch + * + * @wifi_rx_ri_addr_low: Low 32 bits of Transfer ring Read Index address. + * @wifi_rx_ri_addr_high: High 32 bits of Transfer ring Read Index address. + * @update_ri_moderation_threshold: Threshold N for Transfer ring Read Index + * N is the number of packets that IPA will + * process before Wifi transfer ring Ri will + * be updated. + * @qmap_id: Rx only, used for setting metadata register in IPA. Read only field + * for MCS. Write for SW. + * @endp_metadatareg_offset: Rx only, the offset of IPA_ENDP_INIT_HDR_METADATA + * of the corresponding endpoint in 4B words from IPA + * base address. Read only field for MCS. + * Write for SW. + * @wdi_rx_vdev_id: Rx only. Initialized to 0xFF by SW after allocating channel + * and before starting it. Both FW_DESC and VDEV_ID are part + * of a scratch word that is Read/Write for both MCS and SW. + * To avoid race conditions, SW should not update this field + * after starting the channel. + * @wdi_rx_fw_desc: Rx only. Initialized to 0xFF by SW after allocating channel + * and before starting it. After Start, this is a Read only + * field for SW. + * @update_ri_moderation_counter: This field is incremented with each TRE + * processed in MCS. + * @wdi_rx_tre_proc_in_progress: It is set if IPA IF returned BECAME FULL + * status after MCS submitted an inline immediate + * command to update the metadata. It allows MCS + * to know that it has to retry sending the TRE + * to IPA. + * @outstanding_tlvs_counter: It is the count of outstanding TLVs submitted to + * IPA by MCS and waiting for AOS completion from IPA. + * @wdi_rx_pkt_length: If WDI_RX_TRE_PROC_IN_PROGRESS is set, this field is + * valid and contains the packet length of the TRE that + * needs to be submitted to IPA. + * @resv1: reserved bits. + * @pkt_comp_count: It is incremented on each AOS received. When event ring + * Write index is updated, it is decremented by the same + * amount. + * @stop_in_progress_stm: If a Stop request is in progress, this will indicate + * the current stage of processing of the stop within MCS + * @resv2: reserved bits. + * wdi_rx_qmap_id_internal: Initialized to 0 by MCS when the channel is + * allocated. It is updated to the current value of SW + * QMAP ID that is being written by MCS to the IPA + * metadata register. + */ +struct __packed gsi_wdi2_channel_scratch_new { + uint32_t wifi_rx_ri_addr_low; + uint32_t wifi_rx_ri_addr_high; + uint32_t update_ri_moderation_threshold:5; + uint32_t qmap_id:8; + uint32_t resv1:3; + uint32_t endp_metadatareg_offset:16; + uint32_t wdi_rx_vdev_id:8; + uint32_t wdi_rx_fw_desc:8; + uint32_t update_ri_moderation_counter:6; + uint32_t wdi_rx_tre_proc_in_progress:1; + uint32_t resv4:1; + uint32_t outstanding_tlvs_counter:8; + uint32_t wdi_rx_pkt_length:16; + uint32_t resv2:2; + uint32_t pkt_comp_count:11; + uint32_t stop_in_progress_stm:3; + uint32_t resv3:16; + uint32_t wdi_rx_qmap_id_internal:16; +}; +/** + * gsi_mhip_channel_scratch - MHI PRIME protocol SW config area of + * channel scratch + * @assert_bit_40: Valid only for non-host channels. + * Set to 1 for MHI’ channels when running over PCIe. + * @host_channel: Set to 1 for MHIP channel running on host. + * + */ +struct __packed gsi_mhip_channel_scratch { + uint32_t assert_bit_40:1; + uint32_t host_channel:1; + uint32_t resvd1:30; +}; + +/** + * gsi_11ad_rx_channel_scratch - 11AD protocol SW config area of + * RX channel scratch + * + * @status_ring_hwtail_address_lsb: Low 32 bits of status ring hwtail address. + * @status_ring_hwtail_address_msb: High 32 bits of status ring hwtail address. + * @data_buffers_base_address_lsb: Low 32 bits of the data buffers address. + * @data_buffers_base_address_msb: High 32 bits of the data buffers address. + * @fixed_data_buffer_size: the fixed buffer size (> MTU). + * @resv1: reserved bits. + */ +struct __packed gsi_11ad_rx_channel_scratch { + uint32_t status_ring_hwtail_address_lsb; + uint32_t status_ring_hwtail_address_msb; + uint32_t data_buffers_base_address_lsb; + uint32_t data_buffers_base_address_msb:8; + uint32_t fixed_data_buffer_size_pow_2:16; + uint32_t resv1:8; +}; + +/** + * gsi_11ad_tx_channel_scratch - 11AD protocol SW config area of + * TX channel scratch + * + * @status_ring_hwtail_address_lsb: Low 32 bits of status ring hwtail address. + * @status_ring_hwhead_address_lsb: Low 32 bits of status ring hwhead address. + * @status_ring_hwhead_hwtail_8_msb: higher 8 msbs of status ring + * hwhead\hwtail addresses (should be identical). + * @update_status_hwtail_mod_threshold: The threshold in (32B) elements for + * updating descriptor ring 11ad HWTAIL pointer moderation. + * @status_ring_num_elem - the number of elements in the status ring. + * @resv1: reserved bits. + * @fixed_data_buffer_size_pow_2: the fixed buffer size power of 2 (> MTU). + * @resv2: reserved bits. + */ +struct __packed gsi_11ad_tx_channel_scratch { + uint32_t status_ring_hwtail_address_lsb; + uint32_t status_ring_hwhead_address_lsb; + uint32_t status_ring_hwhead_hwtail_8_msb:8; + uint32_t update_status_hwtail_mod_threshold:8; + uint32_t status_ring_num_elem:16; + uint32_t resv1:8; + uint32_t fixed_data_buffer_size_pow_2:16; + uint32_t resv2:8; +}; +/** + * gsi_wdi3_hamilton_channel_scratch - WDI 3 protocol, hamilton chipset + * SW config area of channel scratch + * + * @wifi_rx_ri_addr_low: Low 32 bits of Transfer ring Read Index address. + * @wifi_rx_ri_addr_high: High 32 bits of Transer ring Read Index address. + * @update_ri_moderation_threshold: Threshold N for Transfer ring Read Index + N is the number of packets that IPA will + process before wifi transfer ring Ri will + be updated. + * @endp_metadata_reg_offset: Rx only, the offset of IPA_ENDP_INIT_HDR_METADATA_n + of the corresponding endpoint in 4B words from IPA + base address. + * @qmap_id: Rx only, used for setting metadata register in IPA, Read only field + for MCS, Write for SW + */ + +struct __packed gsi_wdi3_v2_channel_scratch { + uint32_t wifi_rp_address_low; + uint32_t wifi_rp_address_high; + uint32_t update_rp_moderation_threshold : 5; + uint32_t qmap_id : 8; + uint32_t reserved1 : 3; + uint32_t endp_metadata_reg_offset : 16; + uint32_t rx_pkt_offset : 16; + uint32_t reserved2 : 6; + uint32_t bank_id : 6; + uint32_t reserved3: 4; +}; + +/** + * gsi_wdi3_channel_scratch - WDI protocol 3 SW config area of + * channel scratch + * + * @wifi_rx_ri_addr_low: Low 32 bits of Transfer ring Read Index address. + * @wifi_rx_ri_addr_high: High 32 bits of Transfer ring Read Index address. + * @update_ri_moderation_threshold: Threshold N for Transfer ring Read Index + * N is the number of packets that IPA will + * process before Wifi transfer ring Ri will + * be updated. + * @qmap_id: Rx only, used for setting metadata register in IPA. Read only field + * for MCS. Write for SW. + * @resv: reserved bits. + * @endp_metadata_reg_offset: Rx only, the offset of + * IPA_ENDP_INIT_HDR_METADATA_n of the + * corresponding endpoint in 4B words from IPA + * base address. + * @rx_pkt_offset: Rx only, Since Rx header length is not fixed, + * WLAN host will pass this information to IPA. + * @resv: reserved bits. + */ +struct __packed gsi_wdi3_channel_scratch { + uint32_t wifi_rp_address_low; + uint32_t wifi_rp_address_high; + uint32_t update_rp_moderation_threshold : 5; + uint32_t qmap_id : 8; + uint32_t reserved1 : 3; + uint32_t endp_metadata_reg_offset : 16; + uint32_t rx_pkt_offset : 16; + uint32_t reserved2 : 16; +}; + +/** + * gsi_qdss_channel_scratch - QDSS SW config area of + * channel scratch + * + * @bam_p_evt_dest_addr: equivalent to event_ring_doorbell_pa + * physical address of the doorbell that IPA uC + * will update the headpointer of the event ring. + * QDSS should send BAM_P_EVNT_REG address in this var + * Configured with the GSI Doorbell Address. + * GSI sends Update RP by doing a write to this address + * @data_fifo_base_addr: Base address of the data FIFO used by BAM + * @data_fifo_size: Size of the data FIFO + * @bam_p_evt_threshold: Threshold level of how many bytes consumed + * @override_eot: if override EOT==1, it doesn't check the EOT bit in + * the descriptor + */ +struct __packed gsi_qdss_channel_scratch { + uint32_t bam_p_evt_dest_addr; + uint32_t data_fifo_base_addr; + uint32_t data_fifo_size : 16; + uint32_t bam_p_evt_threshold : 16; + uint32_t reserved1 : 2; + uint32_t override_eot : 1; + uint32_t reserved2 : 29; +}; + +/** + * gsi_wdi3_channel_scratch2 - WDI3 protocol SW config area of + * channel scratch2 + * + * @update_ri_moderation_threshold: Threshold N for Transfer ring Read Index + * N is the number of packets that IPA will + * process before Wifi transfer ring Ri will + * be updated. + * @qmap_id: Rx only, used for setting metadata register in IPA. Read only + * field for MCS. Write for SW. + * @resv: reserved bits. + * @endp_metadata_reg_offset: Rx only, the offset of + * IPA_ENDP_INIT_HDR_METADATA_n of the + * corresponding endpoint in 4B words from IPA + * base address. + */ + +struct __packed gsi_wdi3_channel_scratch2 { + uint32_t update_rp_moderation_threshold : 5; + uint32_t qmap_id : 8; + uint32_t reserved1 : 3; + uint32_t endp_metadata_reg_offset : 16; +}; + +/** + * gsi_wdi3_channel_scratch2_reg - channel scratch2 SW config area + * + */ + +union __packed gsi_wdi3_channel_scratch2_reg { + struct __packed gsi_wdi3_channel_scratch2 wdi; + struct __packed { + uint32_t word1; + } data; +}; + +/** + * gsi_rtk_channel_scratch - Realtek SW config area of + * channel scratch + * + * @rtk_bar_low: Realtek bar address LSB + * @rtk_bar_high: Realtek bar address MSB + * @queue_number: dma channel number in rtk + * @fix_buff_size: buff size in KB + * @rtk_buff_addr_high: buffer addr where TRE points to + * @rtk_buff_addr_low: buffer addr where TRE points to + * the descriptor + */ + struct __packed gsi_rtk_channel_scratch { + uint32_t rtk_bar_low; + uint32_t rtk_bar_high : 9; + uint32_t queue_number : 5; + uint32_t fix_buff_size : 4; + uint32_t reserved1 : 6; + uint32_t rtk_buff_addr_high : 8; + uint32_t rtk_buff_addr_low; + uint32_t reserved2; +}; + +/** + * gsi_aqc_channel_scratch - AQC SW config area of + * channel scratch + * + * @buff_addr_lsb: AQC buffer address LSB (RX) + * @buff_addr_msb: AQC buffer address MSB (RX) + * @fix_buff_size: buff size in log2 + * @head_ptr_lsb: head pointer address LSB (RX) + * @head_ptr_msb: head pointer address MSB (RX) + */ + struct __packed gsi_aqc_channel_scratch { + uint32_t buff_addr_lsb; + uint32_t buff_addr_msb : 8; + uint32_t reserved1 : 8; + unsigned fix_buff_size : 16; + uint32_t head_ptr_lsb; + uint32_t head_ptr_msb : 9; + uint32_t reserved2 : 23; + }; + + /** + * gsi_ntn_channel_scratch - NTN SW config area of + * channel scratch + * + * @buff_addr_lsb: NTN buffer address LSB + * @buff_addr_msb: NTN buffer address MSB + * @fix_buff_size: buff size in log2 + * @ioc_mod_threshold: the threshold for IOC moderation (TX) + */ + struct __packed gsi_ntn_channel_scratch { + uint32_t buff_addr_lsb; + uint32_t buff_addr_msb : 8; + uint32_t fix_buff_size : 4; + uint32_t reserved1 : 20; + uint32_t ioc_mod_threshold : 16; + uint32_t reserved2 : 16; + uint32_t reserved3; + uint32_t reserved4; + }; + +/** + * gsi_channel_scratch - channel scratch SW config area + * + */ +union __packed gsi_channel_scratch { + struct __packed gsi_gpi_channel_scratch gpi; + struct __packed gsi_mhi_channel_scratch mhi; + struct __packed gsi_mhi_channel_scratch_v2 mhi_v2; + struct __packed gsi_xdci_channel_scratch xdci; + struct __packed gsi_wdi_channel_scratch wdi; + struct __packed gsi_11ad_rx_channel_scratch rx_11ad; + struct __packed gsi_11ad_tx_channel_scratch tx_11ad; + struct __packed gsi_wdi3_channel_scratch wdi3; + struct __packed gsi_wdi3_v2_channel_scratch wdi3_v2; + struct __packed gsi_mhip_channel_scratch mhip; + struct __packed gsi_wdi2_channel_scratch_new wdi2_new; + struct __packed gsi_aqc_channel_scratch aqc; + struct __packed gsi_rtk_channel_scratch rtk; + struct __packed gsi_ntn_channel_scratch ntn; + struct __packed gsi_qdss_channel_scratch qdss; + struct __packed { + uint32_t word1; + uint32_t word2; + uint32_t word3; + uint32_t word4; + } data; +}; + +/** + * gsi_wdi_channel_scratch3 - WDI protocol SW config area of + * channel scratch3 + */ + +struct __packed gsi_wdi_channel_scratch3 { + uint32_t endp_metadatareg_offset:16; + uint32_t qmap_id:16; +}; + +/** + * gsi_wdi_channel_scratch3_reg - channel scratch3 SW config area + * + */ + +union __packed gsi_wdi_channel_scratch3_reg { + struct __packed gsi_wdi_channel_scratch3 wdi; + struct __packed { + uint32_t word1; + } data; +}; + +/** + * gsi_wdi2_channel_scratch2 - WDI protocol SW config area of + * channel scratch2 + */ + +struct __packed gsi_wdi2_channel_scratch2 { + uint32_t update_ri_moderation_threshold:5; + uint32_t qmap_id:8; + uint32_t resv1:3; + uint32_t endp_metadatareg_offset:16; +}; + +/** + * gsi_wdi_channel_scratch2_reg - channel scratch2 SW config area + * + */ + +union __packed gsi_wdi2_channel_scratch2_reg { + struct __packed gsi_wdi2_channel_scratch2 wdi; + struct __packed { + uint32_t word1; + } data; +}; + +/** + * gsi_mhi_evt_scratch - MHI protocol SW config area of + * event scratch + */ +struct __packed gsi_mhi_evt_scratch { + uint32_t resvd1; + uint32_t resvd2; +}; + +/** + * gsi_mhip_evt_scratch - MHI PRIME protocol SW config area of + * event scratch + */ +struct __packed gsi_mhip_evt_scratch { + uint32_t rp_mod_threshold:8; + uint32_t rp_mod_timer:4; + uint32_t rp_mod_counter:8; + uint32_t rp_mod_timer_id:4; + uint32_t rp_mod_timer_running:1; + uint32_t resvd1:7; + uint32_t fixed_buffer_sz:16; + uint32_t resvd2:16; +}; + + +/** + * gsi_xdci_evt_scratch - xDCI protocol SW config area of + * event scratch + * + */ +struct __packed gsi_xdci_evt_scratch { + uint32_t gevntcount_low_addr; + uint32_t gevntcount_hi_addr:8; + uint32_t resvd1:24; +}; + +/** + * gsi_wdi_evt_scratch - WDI protocol SW config area of + * event scratch + * + */ + +struct __packed gsi_wdi_evt_scratch { + uint32_t update_ri_moderation_config:8; + uint32_t resvd1:8; + uint32_t update_ri_mod_timer_running:1; + uint32_t evt_comp_count:14; + uint32_t resvd2:1; + uint32_t last_update_ri:16; + uint32_t resvd3:16; +}; + +/** + * gsi_11ad_evt_scratch - 11AD protocol SW config area of + * event scratch + * + */ +struct __packed gsi_11ad_evt_scratch { + uint32_t update_status_hwtail_mod_threshold : 8; + uint32_t resvd1:8; + uint32_t resvd2:16; + uint32_t resvd3; +}; + +/** + * gsi_wdi3_evt_scratch - wdi3 protocol SW config area of + * event scratch + * @update_ri_moderation_threshold: Threshold N for Transfer ring Read Index + * N is the number of packets that IPA will + * process before Wifi transfer ring Ri will + * be updated. + * @reserved1: reserve bit. + * @reserved2: reserve bit. + */ +struct __packed gsi_wdi3_evt_scratch { + uint32_t update_rp_moderation_config : 8; + uint32_t reserved1 : 24; + uint32_t reserved2; +}; + +/** + * gsi_rtk_evt_scratch - realtek protocol SW config area of + * event scratch + * @reserved1: reserve bit. + * @reserved2: reserve bit. + */ +struct __packed gsi_rtk_evt_scratch { + uint32_t reserved1; + uint32_t reserved2; +}; + +/** + * gsi_aqc_evt_scratch - AQC protocol SW config area of + * event scratch + * @head_ptr_wrb_mod_threshold: head pointer write-back moderation threshold + * @reserved1-3: reserve bit. + */ +struct __packed gsi_aqc_evt_scratch { + uint8_t head_ptr_wrb_mod_threshold; + uint8_t reserved1; + uint16_t reserved2; + uint32_t reserved3; +}; + +/** + * gsi_evt_scratch - event scratch SW config area + * + */ +union __packed gsi_evt_scratch { + struct __packed gsi_mhi_evt_scratch mhi; + struct __packed gsi_xdci_evt_scratch xdci; + struct __packed gsi_wdi_evt_scratch wdi; + struct __packed gsi_11ad_evt_scratch w11ad; + struct __packed gsi_wdi3_evt_scratch wdi3; + struct __packed gsi_mhip_evt_scratch mhip; + struct __packed gsi_aqc_evt_scratch aqc; + struct __packed gsi_rtk_evt_scratch rtk; + struct __packed { + uint32_t word1; + uint32_t word2; + } data; +}; + +/** + * gsi_device_scratch - EE scratch config parameters + * + * @mhi_base_chan_idx_valid: is mhi_base_chan_idx valid? + * @mhi_base_chan_idx: base index of IPA MHI channel indexes. + * IPA MHI channel index = GSI channel ID + + * MHI base channel index + * @max_usb_pkt_size_valid: is max_usb_pkt_size valid? + * @max_usb_pkt_size: max USB packet size in bytes (valid values are + * 64, 512 and 1024) + */ +struct gsi_device_scratch { + bool mhi_base_chan_idx_valid; + uint8_t mhi_base_chan_idx; + bool max_usb_pkt_size_valid; + uint16_t max_usb_pkt_size; +}; + +/** + * gsi_chan_info - information about channel occupancy + * + * @wp: channel write pointer (physical address) + * @rp: channel read pointer (physical address) + * @evt_valid: is evt* info valid? + * @evt_wp: event ring write pointer (physical address) + * @evt_rp: event ring read pointer (physical address) + */ +struct gsi_chan_info { + uint64_t wp; + uint64_t rp; + bool evt_valid; + uint64_t evt_wp; + uint64_t evt_rp; +}; + + +enum gsi_evt_ring_state { + GSI_EVT_RING_STATE_NOT_ALLOCATED = 0x0, + GSI_EVT_RING_STATE_ALLOCATED = 0x1, + GSI_EVT_RING_STATE_ERROR = 0xf +}; + +enum gsi_chan_state { + GSI_CHAN_STATE_NOT_ALLOCATED = 0x0, + GSI_CHAN_STATE_ALLOCATED = 0x1, + GSI_CHAN_STATE_STARTED = 0x2, + GSI_CHAN_STATE_STOPPED = 0x3, + GSI_CHAN_STATE_STOP_IN_PROC = 0x4, + GSI_CHAN_STATE_FLOW_CONTROL = 0x5, + GSI_CHAN_STATE_ERROR = 0xf +}; + +struct gsi_ring_ctx { + spinlock_t slock; + unsigned long base_va; + uint64_t base; + uint64_t wp; + uint64_t rp; + uint64_t wp_local; + uint64_t rp_local; + uint32_t len; + uint8_t elem_sz; + uint16_t max_num_elem; + uint64_t end; +}; + +struct gsi_chan_dp_stats { + unsigned long ch_below_lo; + unsigned long ch_below_hi; + unsigned long ch_above_hi; + unsigned long empty_time; + unsigned long last_timestamp; +}; + +struct gsi_chan_stats { + unsigned long queued; + unsigned long completed; + unsigned long callback_to_poll; + unsigned long poll_to_callback; + unsigned long poll_pending_irq; + unsigned long invalid_tre_error; + unsigned long poll_ok; + unsigned long poll_empty; + unsigned long userdata_in_use; + struct gsi_chan_dp_stats dp; +}; + +/** + * struct gsi_user_data - user_data element pointed by the TRE + * @valid: valid to be cleaned. if its true that means it is being used. + * false means its free to overwrite + * @p: pointer to the user data array element + */ +struct gsi_user_data { + bool valid; + void *p; +}; + +struct gsi_chan_ctx { + struct gsi_chan_props props; + enum gsi_chan_state state; + struct gsi_ring_ctx ring; + struct gsi_user_data *user_data; + struct gsi_evt_ctx *evtr; + struct mutex mlock; + struct completion compl; + bool allocated; + atomic_t poll_mode; + union __packed gsi_channel_scratch scratch; + struct gsi_chan_stats stats; + bool enable_dp_stats; + bool print_dp_stats; +}; + +struct gsi_evt_stats { + unsigned long completed; +}; + +struct gsi_evt_ctx { + struct gsi_evt_ring_props props; + enum gsi_evt_ring_state state; + uint8_t id; + struct gsi_ring_ctx ring; + struct mutex mlock; + struct completion compl; + struct gsi_chan_ctx *chan[MAX_CHANNELS_SHARING_EVENT_RING]; + uint8_t num_of_chan_allocated; + atomic_t chan_ref_cnt; + union __packed gsi_evt_scratch scratch; + struct gsi_evt_stats stats; +}; + +struct gsi_ee_scratch { + union __packed { + struct { + uint32_t inter_ee_cmd_return_code:3; + uint32_t resvd1:2; + uint32_t generic_ee_cmd_return_code:3; + uint32_t resvd2:2; + uint32_t generic_ee_cmd_return_val:3; + uint32_t resvd4:2; + uint32_t max_usb_pkt_size:1; + uint32_t resvd3:8; + uint32_t mhi_base_chan_idx:8; + } s; + uint32_t val; + } word0; + uint32_t word1; +}; + +struct ch_debug_stats { + unsigned long ch_allocate; + unsigned long ch_start; + unsigned long ch_stop; + unsigned long ch_reset; + unsigned long ch_de_alloc; + unsigned long ch_db_stop; + unsigned long cmd_completed; +}; + +struct gsi_generic_ee_cmd_debug_stats { + unsigned long halt_channel; + unsigned long flow_ctrl_channel; +}; + +struct gsi_coal_chan_info { + uint8_t ch_id; + uint8_t evchid; +}; + +struct gsi_log_ts { + u64 timestamp; + u64 qtimer; + u32 interrupt_type; +}; + +struct gsi_msi { + u32 num; + DECLARE_BITMAP(allocated, GSI_MAX_NUM_MSI); + DECLARE_BITMAP(used, GSI_MAX_NUM_MSI); + struct msi_msg msg[GSI_MAX_NUM_MSI]; + u32 irq[GSI_MAX_NUM_MSI]; + u32 evt[GSI_MAX_NUM_MSI]; + unsigned long mask; +}; + +struct gsi_ctx { + void __iomem *base; + struct device *dev; + struct gsi_per_props per; + bool per_registered; + struct gsi_chan_ctx chan[GSI_CHAN_MAX]; + struct ch_debug_stats ch_dbg[GSI_CHAN_MAX]; + struct gsi_evt_ctx evtr[GSI_EVT_RING_MAX]; + struct gsi_generic_ee_cmd_debug_stats gen_ee_cmd_dbg; + struct mutex mlock; + spinlock_t slock; + unsigned long evt_bmap; + bool enabled; + atomic_t num_chan; + atomic_t num_evt_ring; + struct gsi_ee_scratch scratch; + int num_ch_dp_stats; + struct workqueue_struct *dp_stat_wq; + u32 max_ch; + u32 max_ev; + struct completion gen_ee_cmd_compl; + void *ipc_logbuf; + void *ipc_logbuf_low; + struct gsi_coal_chan_info coal_info; + bool msi_addr_set; + uint64_t msi_addr; + struct gsi_msi msi; + /* + * The following used only on emulation systems. + */ + void __iomem *intcntrlr_base; + u32 intcntrlr_mem_size; + irq_handler_t intcntrlr_gsi_isr; + irq_handler_t intcntrlr_client_isr; + struct gsi_log_ts gsi_isr_cache[GSI_ISR_CACHE_MAX]; + int gsi_isr_cache_index; + + atomic_t num_unclock_irq; +}; + +enum gsi_re_type { + GSI_RE_XFER = 0x2, + GSI_RE_IMMD_CMD = 0x3, + GSI_RE_NOP = 0x4, + GSI_RE_COAL = 0x8, +}; + +struct __packed gsi_tre { + uint64_t buffer_ptr; + uint16_t buf_len; + uint16_t resvd1; + uint16_t chain:1; + uint16_t resvd4:7; + uint16_t ieob:1; + uint16_t ieot:1; + uint16_t bei:1; + uint16_t resvd3:5; + uint8_t re_type; + uint8_t resvd2; +}; + +struct __packed gsi_gci_tre { + uint64_t buffer_ptr:41; + uint64_t resvd1:7; + uint64_t buf_len:16; + uint64_t cookie:40; + uint64_t resvd2:8; + uint64_t re_type:8; + uint64_t resvd3:8; +}; + +#define GSI_XFER_COMPL_TYPE_GCI 0x28 + +struct __packed gsi_xfer_compl_evt { + union { + uint64_t xfer_ptr; + struct { + uint64_t cookie:40; + uint64_t resvd1:24; + }; + }; + uint16_t len; + uint8_t veid; + uint8_t code; /* see gsi_chan_evt */ + uint16_t resvd; + uint8_t type; + uint8_t chid; +}; + +enum gsi_err_type { + GSI_ERR_TYPE_GLOB = 0x1, + GSI_ERR_TYPE_CHAN = 0x2, + GSI_ERR_TYPE_EVT = 0x3, +}; + +enum gsi_err_code { + GSI_INVALID_TRE_ERR = 0x1, + GSI_OUT_OF_BUFFERS_ERR = 0x2, + GSI_OUT_OF_RESOURCES_ERR = 0x3, + GSI_UNSUPPORTED_INTER_EE_OP_ERR = 0x4, + GSI_EVT_RING_EMPTY_ERR = 0x5, + GSI_NON_ALLOCATED_EVT_ACCESS_ERR = 0x6, + GSI_HWO_1_ERR = 0x8 +}; + +struct __packed gsi_log_err { + uint32_t arg3:4; + uint32_t arg2:4; + uint32_t arg1:4; + uint32_t code:4; + uint32_t resvd:3; + uint32_t virt_idx:5; + uint32_t err_type:4; + uint32_t ee:4; +}; + +enum gsi_ch_cmd_opcode { + GSI_CH_ALLOCATE = 0x0, + GSI_CH_START = 0x1, + GSI_CH_STOP = 0x2, + GSI_CH_RESET = 0x9, + GSI_CH_DE_ALLOC = 0xa, + GSI_CH_DB_STOP = 0xb, +}; + +enum gsi_evt_ch_cmd_opcode { + GSI_EVT_ALLOCATE = 0x0, + GSI_EVT_RESET = 0x9, + GSI_EVT_DE_ALLOC = 0xa, +}; + +enum gsi_generic_ee_cmd_opcode { + GSI_GEN_EE_CMD_HALT_CHANNEL = 0x1, + GSI_GEN_EE_CMD_ALLOC_CHANNEL = 0x2, + GSI_GEN_EE_CMD_ENABLE_FLOW_CHANNEL = 0x3, + GSI_GEN_EE_CMD_DISABLE_FLOW_CHANNEL = 0x4, + GSI_GEN_EE_CMD_QUERY_FLOW_CHANNEL = 0x5, +}; + +enum gsi_generic_ee_cmd_return_code { + GSI_GEN_EE_CMD_RETURN_CODE_SUCCESS = 0x1, + GSI_GEN_EE_CMD_RETURN_CODE_CHANNEL_NOT_RUNNING = 0x2, + GSI_GEN_EE_CMD_RETURN_CODE_INCORRECT_DIRECTION = 0x3, + GSI_GEN_EE_CMD_RETURN_CODE_INCORRECT_CHANNEL_TYPE = 0x4, + GSI_GEN_EE_CMD_RETURN_CODE_INCORRECT_CHANNEL_INDEX = 0x5, + GSI_GEN_EE_CMD_RETURN_CODE_RETRY = 0x6, + GSI_GEN_EE_CMD_RETURN_CODE_OUT_OF_RESOURCES = 0x7, +}; + +/** + * struct gsi_hw_profiling_data - GSI profiling data + * @bp_cnt: Back Pressure occurences count + * @bp_and_pending_cnt: Back Pressure with pending back pressure count + * @mcs_busy_cnt: Cycle count for MCS busy + * @mcs_idle_cnt: Cycle count for MCS idle + */ +struct gsi_hw_profiling_data { + u64 bp_cnt; + u64 bp_and_pending_cnt; + u64 mcs_busy_cnt; + u64 mcs_idle_cnt; +}; + +/** + * struct gsi_fw_version - GSI fw version data + * @hw: HW version + * @flavor: Flavor identifier + * @fw: FW version + */ +struct gsi_fw_version { + u32 hw; + u32 flavor; + u32 fw; +}; + +enum gsi_generic_ee_cmd_query_retun_val { + GSI_GEN_EE_CMD_RETURN_VAL_FLOW_CONTROL_PRIMARY = 0, + GSI_GEN_EE_CMD_RETURN_VAL_FLOW_CONTROL_SECONDARY = 1, + GSI_GEN_EE_CMD_RETURN_VAL_FLOW_CONTROL_PENDING = 2, +}; +extern struct gsi_ctx *gsi_ctx; + +/** + * gsi_xfer_elem - Metadata about a single transfer + * + * @addr: physical address of buffer + * @len: size of buffer for GSI_XFER_ELEM_DATA: + * for outbound transfers this is the number of bytes to + * transfer. + * for inbound transfers, this is the maximum number of + * bytes the host expects from device in this transfer + * + * immediate command opcode for GSI_XFER_ELEM_IMME_CMD + * @flags: transfer flags, OR of all the applicable flags + * + * GSI_XFER_FLAG_BEI: Block event interrupt + * 1: Event generated by this ring element must not assert + * an interrupt to the host + * 0: Event generated by this ring element must assert an + * interrupt to the host + * + * GSI_XFER_FLAG_EOT: Interrupt on end of transfer + * 1: If an EOT condition is encountered when processing + * this ring element, an event is generated by the device + * with its completion code set to EOT. + * 0: If an EOT condition is encountered for this ring + * element, a completion event is not be generated by the + * device, unless IEOB is 1 + * + * GSI_XFER_FLAG_EOB: Interrupt on end of block + * 1: Device notifies host after processing this ring element + * by sending a completion event + * 0: Completion event is not required after processing this + * ring element + * + * GSI_XFER_FLAG_CHAIN: Chain bit that identifies the ring + * elements in a TD + * + * @type: transfer type + * + * GSI_XFER_ELEM_DATA: for all data transfers + * GSI_XFER_ELEM_IMME_CMD: for IPA immediate commands + * GSI_XFER_ELEM_NOP: for event generation only + * + * @xfer_user_data: cookie used in xfer_cb + * + */ +struct gsi_xfer_elem { + uint64_t addr; + uint16_t len; + uint16_t flags; + enum gsi_xfer_elem_type type; + void *xfer_user_data; +}; + +/** + * gsi_alloc_evt_ring - Peripheral should call this function to + * allocate an event ring + * + * @props: Event ring properties + * @dev_hdl: Client handle previously obtained from + * gsi_register_device + * @evt_ring_hdl: Handle populated by GSI, opaque to client + * + * This function can sleep + * + * @Return gsi_status + */ +int gsi_alloc_evt_ring(struct gsi_evt_ring_props *props, unsigned long dev_hdl, + unsigned long *evt_ring_hdl); + +/** + * gsi_dealloc_evt_ring - Peripheral should call this function to + * de-allocate an event ring. There should not exist any active + * channels using this event ring + * + * @evt_ring_hdl: Client handle previously obtained from + * gsi_alloc_evt_ring + * + * This function can sleep + * + * @Return gsi_status + */ +int gsi_dealloc_evt_ring(unsigned long evt_ring_hdl); + +/** + * gsi_alloc_channel - Peripheral should call this function to + * allocate a channel + * + * @props: Channel properties + * @dev_hdl: Client handle previously obtained from + * gsi_register_device + * @chan_hdl: Handle populated by GSI, opaque to client + * + * This function can sleep + * + * @Return gsi_status + */ +int gsi_alloc_channel(struct gsi_chan_props *props, unsigned long dev_hdl, + unsigned long *chan_hdl); + +/** + * gsi_start_channel - Peripheral should call this function to + * start a channel i.e put into running state + * + * @chan_hdl: Client handle previously obtained from + * gsi_alloc_channel + * + * This function can sleep + * + * @Return gsi_status + */ +int gsi_start_channel(unsigned long chan_hdl); + +/** + * gsi_reset_channel - Peripheral should call this function to + * reset a channel to recover from error state + * + * @chan_hdl: Client handle previously obtained from + * gsi_alloc_channel + * + * This function can sleep + * + * @Return gsi_status + */ +int gsi_reset_channel(unsigned long chan_hdl); + +/** + * gsi_dealloc_channel - Peripheral should call this function to + * de-allocate a channel + * + * @chan_hdl: Client handle previously obtained from + * gsi_alloc_channel + * + * This function can sleep + * + * @Return gsi_status + */ +int gsi_dealloc_channel(unsigned long chan_hdl); + +/** + * gsi_poll_channel - Peripheral should call this function to query for + * completed transfer descriptors. + * + * @chan_hdl: Client handle previously obtained from + * gsi_alloc_channel + * @notify: Information about the completed transfer if any + * + * @Return gsi_status (GSI_STATUS_POLL_EMPTY is returned if no transfers + * completed) + */ +int gsi_poll_channel(unsigned long chan_hdl, + struct gsi_chan_xfer_notify *notify); + +/** + * gsi_ring_evt_doorbell_napi - doorbell from NAPI context + * @chan_hdl: Client handle previously obtained from + * gsi_alloc_channel + * + */ +void gsi_ring_evt_doorbell_polling_mode(unsigned long chan_hdl); + +/** + * gsi_config_channel_mode - Peripheral should call this function + * to configure the channel mode. + * + * @chan_hdl: Client handle previously obtained from + * gsi_alloc_channel + * @mode: Mode to move the channel into + * + * @Return gsi_status + */ +int gsi_config_channel_mode(unsigned long chan_hdl, enum gsi_chan_mode mode); + +/** + * gsi_queue_xfer - Peripheral should call this function + * to queue transfers on the given channel + * + * @chan_hdl: Client handle previously obtained from + * gsi_alloc_channel + * @num_xfers: Number of transfer in the array @ xfer + * @xfer: Array of num_xfers transfer descriptors + * @ring_db: If true, tell HW about these queued xfers + * If false, do not notify HW at this time + * + * @Return gsi_status + */ +int gsi_queue_xfer(unsigned long chan_hdl, uint16_t num_xfers, + struct gsi_xfer_elem *xfer, bool ring_db); + +void gsi_debugfs_init(void); +uint16_t gsi_find_idx_from_addr(struct gsi_ring_ctx *ctx, uint64_t addr); +void gsi_update_ch_dp_stats(struct gsi_chan_ctx *ctx, uint16_t used); + +/** + * gsi_register_device - Peripheral should call this function to + * register itself with GSI before invoking any other APIs + * + * @props: Peripheral properties + * @dev_hdl: Handle populated by GSI, opaque to client + * + * @Return -GSI_STATUS_AGAIN if request should be re-tried later + * other error codes for failure + */ +int gsi_register_device(struct gsi_per_props *props, unsigned long *dev_hdl); + +/** + * gsi_complete_clk_grant - Peripheral should call this function to + * grant the clock resource requested by GSI previously that could not + * be granted synchronously. GSI will release the clock resource using + * the rel_clk_cb when appropriate + * + * @dev_hdl: Client handle previously obtained from + * gsi_register_device + * + * @Return gsi_status + */ +int gsi_complete_clk_grant(unsigned long dev_hdl); + +/** + * gsi_write_device_scratch - Peripheral should call this function to + * write to the EE scratch area + * + * @dev_hdl: Client handle previously obtained from + * gsi_register_device + * @val: Value to write + * + * @Return gsi_status + */ +int gsi_write_device_scratch(unsigned long dev_hdl, + struct gsi_device_scratch *val); + +/** + * gsi_deregister_device - Peripheral should call this function to + * de-register itself with GSI + * + * @dev_hdl: Client handle previously obtained from + * gsi_register_device + * @force: When set to true, cleanup is performed even if there + * are in use resources like channels, event rings, etc. + * this would be used after GSI reset to recover from some + * fatal error + * When set to false, there must not exist any allocated + * channels and event rings. + * + * @Return gsi_status + */ +int gsi_deregister_device(unsigned long dev_hdl, bool force); + +/** + * gsi_write_evt_ring_scratch - Peripheral should call this function to + * write to the scratch area of the event ring context + * + * @evt_ring_hdl: Client handle previously obtained from + * gsi_alloc_evt_ring + * @val: Value to write + * + * @Return gsi_status + */ +int gsi_write_evt_ring_scratch(unsigned long evt_ring_hdl, + union __packed gsi_evt_scratch val); + +/** + * gsi_query_evt_ring_db_addr - Peripheral should call this function to + * query the physical addresses of the event ring doorbell registers + * + * @evt_ring_hdl: Client handle previously obtained from + * gsi_alloc_evt_ring + * @db_addr_wp_lsb: Physical address of doorbell register where the 32 + * LSBs of the doorbell value should be written + * @db_addr_wp_msb: Physical address of doorbell register where the 32 + * MSBs of the doorbell value should be written + * + * @Return gsi_status + */ +int gsi_query_evt_ring_db_addr(unsigned long evt_ring_hdl, + uint32_t *db_addr_wp_lsb, uint32_t *db_addr_wp_msb); + +/** + * gsi_ring_evt_ring_db - Peripheral should call this function for + * ringing the event ring doorbell with given value + * + * @evt_ring_hdl: Client handle previously obtained from + * gsi_alloc_evt_ring + * @value: The value to be used for ringing the doorbell + * + * @Return gsi_status + */ +int gsi_ring_evt_ring_db(unsigned long evt_ring_hdl, uint64_t value); + +/** + * gsi_ring_ch_ring_db - Peripheral should call this function for + * ringing the channel ring doorbell with given value + * + * @chan_hdl: Client handle previously obtained from + * gsi_alloc_channel + * @value: The value to be used for ringing the doorbell + * + * @Return gsi_status + */ +int gsi_ring_ch_ring_db(unsigned long chan_hdl, uint64_t value); + +/** + * gsi_reset_evt_ring - Peripheral should call this function to + * reset an event ring to recover from error state + * + * @evt_ring_hdl: Client handle previously obtained from + * gsi_alloc_evt_ring + * + * This function can sleep + * + * @Return gsi_status + */ +int gsi_reset_evt_ring(unsigned long evt_ring_hdl); + +/** + * gsi_get_evt_ring_cfg - This function returns the current config + * of the specified event ring + * + * @evt_ring_hdl: Client handle previously obtained from + * gsi_alloc_evt_ring + * @props: where to copy properties to + * @scr: where to copy scratch info to + * + * @Return gsi_status + */ +int gsi_get_evt_ring_cfg(unsigned long evt_ring_hdl, + struct gsi_evt_ring_props *props, union gsi_evt_scratch *scr); + +/** + * gsi_set_evt_ring_cfg - This function applies the supplied config + * to the specified event ring. + * + * exclusive property of the event ring cannot be changed after + * gsi_alloc_evt_ring + * + * @evt_ring_hdl: Client handle previously obtained from + * gsi_alloc_evt_ring + * @props: the properties to apply + * @scr: the scratch info to apply + * + * @Return gsi_status + */ +int gsi_set_evt_ring_cfg(unsigned long evt_ring_hdl, + struct gsi_evt_ring_props *props, union gsi_evt_scratch *scr); + +/** + * gsi_write_channel_scratch - Peripheral should call this function to + * write to the scratch area of the channel context + * + * @chan_hdl: Client handle previously obtained from + * gsi_alloc_channel + * @val: Value to write + * + * @Return gsi_status + */ +int gsi_write_channel_scratch(unsigned long chan_hdl, + union __packed gsi_channel_scratch val); + +/** + * gsi_write_channel_scratch3_reg - Peripheral should call this function to + * write to the scratch3 reg area of the channel context + * + * @chan_hdl: Client handle previously obtained from + * gsi_alloc_channel + * @val: Value to write + * + * @Return gsi_status + */ +int gsi_write_channel_scratch3_reg(unsigned long chan_hdl, + union __packed gsi_wdi_channel_scratch3_reg val); + +/** + * gsi_write_channel_scratch2_reg - Peripheral should call this function to + * write to the scratch2 reg area of the channel context + * + * @chan_hdl: Client handle previously obtained from + * gsi_alloc_channel + * @val: Value to write + * + * @Return gsi_status + */ +int gsi_write_channel_scratch2_reg(unsigned long chan_hdl, + union __packed gsi_wdi2_channel_scratch2_reg val); + +/** + * gsi_write_wdi3_channel_scratch2_reg - Peripheral should call this function + * to write to the WDI3 scratch 3 register area of the channel context + * + * @chan_hdl: Client handle previously obtained from + * gsi_alloc_channel + * @val: Read value + * + * @Return gsi_status + */ +int gsi_write_wdi3_channel_scratch2_reg(unsigned long chan_hdl, + union __packed gsi_wdi3_channel_scratch2_reg val); + +/** + * gsi_read_channel_scratch - Peripheral should call this function to + * read to the scratch area of the channel context + * + * @chan_hdl: Client handle previously obtained from + * gsi_alloc_channel + * @val: Read value + * + * @Return gsi_status + */ +int gsi_read_channel_scratch(unsigned long chan_hdl, + union __packed gsi_channel_scratch *val); + +/** + * gsi_read_wdi3_channel_scratch2_reg - Peripheral should call this function to + * read to the WDI3 scratch 2 register area of the channel context + * + * @chan_hdl: Client handle previously obtained from + * gsi_alloc_channel + * @val: Read value + * + * @Return gsi_status + */ +int gsi_read_wdi3_channel_scratch2_reg(unsigned long chan_hdl, + union __packed gsi_wdi3_channel_scratch2_reg *val); + +/* + * gsi_pending_irq_type - Peripheral should call this function to + * check if there is any pending irq + * + * This function can sleep + * + * @Return gsi_irq_type + */ +int gsi_pending_irq_type(void); + +/** + * gsi_update_mhi_channel_scratch - MHI Peripheral should call this + * function to update the scratch area of the channel context. Updating + * will be by read-modify-write method, so non SWI fields will not be + * affected + * + * @chan_hdl: Client handle previously obtained from + * gsi_alloc_channel + * @mscr: MHI Channel Scratch value + * + * @Return gsi_status + */ +int gsi_update_mhi_channel_scratch(unsigned long chan_hdl, + struct __packed gsi_mhi_channel_scratch mscr); + +/** + * gsi_stop_channel - Peripheral should call this function to + * stop a channel. Stop will happen on a packet boundary + * + * @chan_hdl: Client handle previously obtained from + * gsi_alloc_channel + * + * This function can sleep + * + * @Return -GSI_STATUS_AGAIN if client should call stop/stop_db again + * other error codes for failure + */ +int gsi_stop_channel(unsigned long chan_hdl); + +/** + * gsi_stop_db_channel - Peripheral should call this function to + * stop a channel when all transfer elements till the doorbell + * have been processed + * + * @chan_hdl: Client handle previously obtained from + * gsi_alloc_channel + * + * This function can sleep + * + * @Return -GSI_STATUS_AGAIN if client should call stop/stop_db again + * other error codes for failure + */ +int gsi_stop_db_channel(unsigned long chan_hdl); + +/** + * gsi_query_channel_db_addr - Peripheral should call this function to + * query the physical addresses of the channel doorbell registers + * + * @chan_hdl: Client handle previously obtained from + * gsi_alloc_channel + * @db_addr_wp_lsb: Physical address of doorbell register where the 32 + * LSBs of the doorbell value should be written + * @db_addr_wp_msb: Physical address of doorbell register where the 32 + * MSBs of the doorbell value should be written + * + * @Return gsi_status + */ +int gsi_query_channel_db_addr(unsigned long chan_hdl, + uint32_t *db_addr_wp_lsb, uint32_t *db_addr_wp_msb); + +/** + * gsi_query_channel_info - Peripheral can call this function to query the + * channel and associated event ring (if any) status. + * + * @chan_hdl: Client handle previously obtained from + * gsi_alloc_channel + * @info: Where to read the values into + * + * @Return gsi_status + */ +int gsi_query_channel_info(unsigned long chan_hdl, + struct gsi_chan_info *info); + +/** + * gsi_is_channel_empty - Peripheral can call this function to query if + * the channel is empty. This is only applicable to GPI. "Empty" means + * GSI has consumed all descriptors for a TO_GSI channel and SW has + * processed all completed descriptors for a FROM_GSI channel. + * + * @chan_hdl: Client handle previously obtained from gsi_alloc_channel + * @is_empty: set by GSI based on channel emptiness + * + * @Return gsi_status + */ +int gsi_is_channel_empty(unsigned long chan_hdl, bool *is_empty); + +/** + * gsi_is_event_pending - Returns true if there is at least one event in the + * provided event ring which wasn't processed. + * + * @chan_hdl: Client handle previously obtained from gsi_alloc_channel + * + * @Return true if an event is pending, else false + */ +bool gsi_is_event_pending(unsigned long chan_hdl); +/** + * gsi_get_channel_cfg - This function returns the current config + * of the specified channel + * + * @chan_hdl: Client handle previously obtained from + * gsi_alloc_channel + * @props: where to copy properties to + * @scr: where to copy scratch info to + * + * @Return gsi_status + */ +int gsi_get_channel_cfg(unsigned long chan_hdl, struct gsi_chan_props *props, + union gsi_channel_scratch *scr); + +/** + * gsi_set_channel_cfg - This function applies the supplied config + * to the specified channel + * + * ch_id and evt_ring_hdl of the channel cannot be changed after + * gsi_alloc_channel + * + * @chan_hdl: Client handle previously obtained from + * gsi_alloc_channel + * @props: the properties to apply + * @scr: the scratch info to apply + * + * @Return gsi_status + */ +int gsi_set_channel_cfg(unsigned long chan_hdl, struct gsi_chan_props *props, + union gsi_channel_scratch *scr); + + +/** + * gsi_poll_n_channel - Peripheral should call this function to query for + * completed transfer descriptors. + * + * @chan_hdl: Client handle previously obtained from + * gsi_alloc_channel + * @notify: Information about the completed transfer if any + * @expected_num: Number of descriptor we want to poll each time. + * @actual_num: Actual number of descriptor we polled successfully. + * + * @Return gsi_status (GSI_STATUS_POLL_EMPTY is returned if no transfers + * completed) + */ +int gsi_poll_n_channel(unsigned long chan_hdl, + struct gsi_chan_xfer_notify *notify, + int expected_num, int *actual_num); + +/** + * gsi_start_xfer - Peripheral should call this function to + * inform HW about queued xfers + * + * @chan_hdl: Client handle previously obtained from + * gsi_alloc_channel + * + * @Return gsi_status + */ +int gsi_start_xfer(unsigned long chan_hdl); + +/** + * gsi_configure_regs - Peripheral should call this function + * to configure the GSI registers before/after the FW is + * loaded but before it is enabled. + * + * @per_base_addr: Base address of the peripheral using GSI + * @ver: GSI core version + * + * @Return gsi_status + */ +int gsi_configure_regs(phys_addr_t per_base_addr, enum gsi_ver ver); + +/** + * gsi_enable_fw - Peripheral should call this function + * to enable the GSI FW after the FW has been loaded to the SRAM. + * + * @gsi_base_addr: Base address of GSI register space + * @gsi_size: Mapping size of the GSI register space + * @ver: GSI core version + + * @Return gsi_status + */ +int gsi_enable_fw(phys_addr_t gsi_base_addr, u32 gsi_size, enum gsi_ver ver); + +/** + * gsi_get_inst_ram_offset_and_size - Peripheral should call this function + * to get instruction RAM base address offset and size. Peripheral typically + * uses this info to load GSI FW into the IRAM. + * + * @base_offset:[OUT] - IRAM base offset address + * @size: [OUT] - IRAM size + * @ver: GSI core version + + * @Return none + */ +void gsi_get_inst_ram_offset_and_size(unsigned long *base_offset, + unsigned long *size, enum gsi_ver ver); + +/** + * gsi_halt_channel_ee - Peripheral should call this function + * to stop other EE's channel. This is usually used in SSR clean + * + * @chan_idx: Virtual channel index + * @ee: EE + * @code: [out] response code for operation + + * @Return gsi_status + */ +int gsi_halt_channel_ee(unsigned int chan_idx, unsigned int ee, int *code); + +/** + * gsi_wdi3_write_evt_ring_db - write event ring doorbell address + * + * @chan_hdl: gsi channel handle + * @Return gsi_status + */ +void gsi_wdi3_write_evt_ring_db(unsigned long chan_hdl, uint32_t db_addr_low, + uint32_t db_addr_high); + +/** + * gsi_get_refetch_reg - get WP/RP value from re_fetch register + * + * @chan_hdl: gsi channel handle + * @is_rp: rp or wp + */ +int gsi_get_refetch_reg(unsigned long chan_hdl, bool is_rp); + +/** + * gsi_ntn3_client_stats_get - get ntn3 stats + * + * @ep_id: ep index + * @scratch_id: scratch register number + * @chan_hdl: gsi channel handle + */ +int gsi_ntn3_client_stats_get(unsigned ep_id, int scratch_id, unsigned chan_hdl); + +/** + * gsi_get_drop_stats - get drop stats by GSI + * + * @ep_id: ep index + * @scratch_id: drop stats on which scratch register + * @chan_hdl: gsi channel handle + */ +int gsi_get_drop_stats(unsigned long ep_id, int scratch_id, + unsigned long chan_hdl); + +/** +* gsi_get_wp - get channel write pointer for stats +* +* @chan_hdl: gsi channel handle +*/ +int gsi_get_wp(unsigned long chan_hdl); + +/** + * gsi_wdi3_dump_register - dump wdi3 related gsi registers + * + * @chan_hdl: gsi channel handle + */ +void gsi_wdi3_dump_register(unsigned long chan_hdl); + + +/** + * gsi_map_base - Peripheral should call this function to configure + * access to the GSI registers. + + * @gsi_base_addr: Base address of GSI register space + * @gsi_size: Mapping size of the GSI register space + * @ver: The appropriate GSI version enum + * + * @Return gsi_status + */ +int gsi_map_base(phys_addr_t gsi_base_addr, u32 gsi_size, enum gsi_ver ver); + +/** + * gsi_unmap_base - Peripheral should call this function to undo the + * effects of gsi_map_base + * + * @Return gsi_status + */ +int gsi_unmap_base(void); + +/** + * gsi_map_virtual_ch_to_per_ep - Peripheral should call this function + * to configure each GSI virtual channel with the per endpoint index. + * + * @ee: The ee to be used + * @chan_num: The channel to be used + * @per_ep_index: value to assign + * + * @Return gsi_status + */ +int gsi_map_virtual_ch_to_per_ep(u32 ee, u32 chan_num, u32 per_ep_index); + +/** + * gsi_alloc_channel_ee - Peripheral should call this function + * to alloc other EE's channel. This is usually done in bootup to allocate all + * chnnels. + * + * @chan_idx: Virtual channel index + * @ee: EE + * @code: [out] response code for operation + + * @Return gsi_status + */ +int gsi_alloc_channel_ee(unsigned int chan_idx, unsigned int ee, int *code); + +/** + * gsi_enable_flow_control_ee - Peripheral should call this function + * to enable flow control other EE's channel. This is usually done in USB + * connent and SSR scenarios. + * + * @chan_idx: Virtual channel index + * @ee: EE + * @code: [out] response code for operation + + * @Return gsi_status + */ +int gsi_enable_flow_control_ee(unsigned int chan_idx, unsigned int ee, + int *code); + +/** +* gsi_query_msi_addr - get gsi channel msi address +* +* @chan_id: channel id +* @addr: [out] channel msi address +* +* @Return gsi_status +*/ +int gsi_query_msi_addr(unsigned long chan_hdl, phys_addr_t *addr); + +/** +* gsi_query_device_msi_addr - get gsi device msi address +* +* @addr: [out] msi address +* +* @Return gsi_status +*/ +int gsi_query_device_msi_addr(u64 *addr); + +/** +* gsi_update_almst_empty_thrshold - update almst_empty_thrshold +* +* @chan_id: channel id +* @threshold: Threshold value for channel almost empty indication to MCS. +* +*/ +void gsi_update_almst_empty_thrshold(unsigned long chan_hdl, unsigned short threshold); + +/** +* gsi_dump_ch_info - channel information. +* +* @chan_id: channel id +* +* @Return void +*/ +void gsi_dump_ch_info(unsigned long chan_hdl); + +/** + * gsi_get_hw_profiling_stats() - Query GSI HW profiling stats + * @stats: [out] stats blob from client populated by driver + * + * Returns: 0 on success, negative on failure + * + */ +int gsi_get_hw_profiling_stats(struct gsi_hw_profiling_data *stats); + +/** + * gsi_get_fw_version() - Query GSI FW version + * @ver: [out] ver blob from client populated by driver + * + * Returns: 0 on success, negative on failure + * + */ +int gsi_get_fw_version(struct gsi_fw_version *ver); + +int gsi_flow_control_ee(unsigned int chan_idx, int ep_id, unsigned int ee, + bool enable, bool prmy_scnd_fc, int *code); +int gsi_query_flow_control_state_ee(unsigned int chan_idx, unsigned int ee, + bool prmy_scnd_fc, int *code); +/* + * Here is a typical sequence of calls + * + * gsi_register_device + * + * gsi_write_device_scratch (if the protocol needs this) + * + * gsi_alloc_evt_ring (for as many event rings as needed) + * gsi_write_evt_ring_scratch + * + * gsi_alloc_channel (for as many channels as needed; channels can have + * no event ring, an exclusive event ring or a shared event ring) + * gsi_write_channel_scratch + * gsi_read_channel_scratch + * gsi_start_channel + * gsi_queue_xfer/gsi_start_xfer + * gsi_config_channel_mode/gsi_poll_channel (if clients wants to poll on + * xfer completions) + * gsi_stop_db_channel/gsi_stop_channel + * + * gsi_dealloc_channel + * + * gsi_dealloc_evt_ring + * + * gsi_deregister_device + * + */ + +/** + * These APIs are mostly for the ipa_stats module + */ +uint64_t gsi_read_event_ring_wp(int evtr_id, int ee); + +uint64_t gsi_read_event_ring_bp(int evt_hdl); + +uint64_t gsi_get_evt_ring_rp(int evt_hdl); + +uint64_t gsi_read_chan_ring_wp(int chan_id, int ee); + +uint64_t gsi_read_chan_ring_rp(int chan_id, int ee); + +uint64_t gsi_read_chan_ring_bp(int chan_hdl); + +uint64_t gsi_read_chan_ring_re_fetch_wp(int chan_id, int ee); + +enum gsi_chan_prot gsi_get_chan_prot_type(int chan_hdl); + +enum gsi_chan_state gsi_get_chan_state(int chan_hdl); + +int gsi_get_chan_poll_mode(int chan_hdl); + +uint32_t gsi_get_ring_len(int chan_hdl); + +uint8_t gsi_get_chan_props_db_in_bytes(int chan_hdl); + +enum gsi_evt_ring_elem_size gsi_get_evt_ring_re_size(int evt_hdl); + +uint32_t gsi_get_evt_ring_len(int evt_hdl); + +int gsi_get_peripheral_ee(void); + +uint32_t gsi_get_chan_stop_stm(int chan_id, int ee); + +#endif diff --git a/qcom/opensource/dataipa/drivers/platform/msm/gsi/gsi_dbg.c b/qcom/opensource/dataipa/drivers/platform/msm/gsi/gsi_dbg.c new file mode 100644 index 0000000000..ba811cd2ca --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/gsi/gsi_dbg.c @@ -0,0 +1,808 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include "gsi.h" +#include "gsihal.h" + +#define GSI_MAX_MSG_LEN 4096 + +#define TERR(fmt, args...) \ + pr_err("%s:%d " fmt, __func__, __LINE__, ## args) +#define TDBG(fmt, args...) \ + pr_debug("%s:%d " fmt, __func__, __LINE__, ## args) +#define PRT_STAT(fmt, args...) \ + pr_err(fmt, ## args) + +static struct dentry *dent; +static char dbg_buff[GSI_MAX_MSG_LEN]; +static void *gsi_ipc_logbuf_low; + +static void gsi_wq_print_dp_stats(struct work_struct *work); +static DECLARE_DELAYED_WORK(gsi_print_dp_stats_work, gsi_wq_print_dp_stats); +static void gsi_wq_update_dp_stats(struct work_struct *work); +static DECLARE_DELAYED_WORK(gsi_update_dp_stats_work, gsi_wq_update_dp_stats); + +static ssize_t gsi_dump_evt(struct file *file, + const char __user *buf, size_t count, loff_t *ppos) +{ + u32 arg1; + u32 arg2; + unsigned long missing; + char *sptr, *token; + uint32_t val; + struct gsi_evt_ctx *ctx; + uint16_t i; + + if (count >= sizeof(dbg_buff)) + return -EINVAL; + + missing = copy_from_user(dbg_buff, buf, count); + if (missing) + return -EFAULT; + + dbg_buff[count] = '\0'; + + sptr = dbg_buff; + + token = strsep(&sptr, " "); + if (!token) + return -EINVAL; + if (kstrtou32(token, 0, &arg1)) + return -EINVAL; + + token = strsep(&sptr, " "); + if (!token) + return -EINVAL; + if (kstrtou32(token, 0, &arg2)) + return -EINVAL; + + TDBG("arg1=%u arg2=%u\n", arg1, arg2); + + if (arg1 >= gsi_ctx->max_ev) { + TERR("invalid evt ring id %u\n", arg1); + return -EINVAL; + } + + gsi_ctx->per.vote_clk_cb(); + + val = gsihal_read_reg_nk(GSI_EE_n_EV_CH_k_CNTXT_0, + gsi_ctx->per.ee, arg1); + TERR("EV%2d CTX0 0x%x\n", arg1, val); + val = gsihal_read_reg_nk(GSI_EE_n_EV_CH_k_CNTXT_1, + gsi_ctx->per.ee, arg1); + TERR("EV%2d CTX1 0x%x\n", arg1, val); + val = gsihal_read_reg_nk(GSI_EE_n_EV_CH_k_CNTXT_2, + gsi_ctx->per.ee, arg1); + TERR("EV%2d CTX2 0x%x\n", arg1, val); + val = gsihal_read_reg_nk(GSI_EE_n_EV_CH_k_CNTXT_3, + gsi_ctx->per.ee, arg1); + TERR("EV%2d CTX3 0x%x\n", arg1, val); + val = gsihal_read_reg_nk(GSI_EE_n_EV_CH_k_CNTXT_4, + gsi_ctx->per.ee, arg1); + TERR("EV%2d CTX4 0x%x\n", arg1, val); + val = gsihal_read_reg_nk(GSI_EE_n_EV_CH_k_CNTXT_5, + gsi_ctx->per.ee, arg1); + TERR("EV%2d CTX5 0x%x\n", arg1, val); + val = gsihal_read_reg_nk(GSI_EE_n_EV_CH_k_CNTXT_6, + gsi_ctx->per.ee, arg1); + TERR("EV%2d CTX6 0x%x\n", arg1, val); + val = gsihal_read_reg_nk(GSI_EE_n_EV_CH_k_CNTXT_7, + gsi_ctx->per.ee, arg1); + TERR("EV%2d CTX7 0x%x\n", arg1, val); + val = gsihal_read_reg_nk(GSI_EE_n_EV_CH_k_CNTXT_8, + gsi_ctx->per.ee, arg1); + TERR("EV%2d CTX8 0x%x\n", arg1, val); + val = gsihal_read_reg_nk(GSI_EE_n_EV_CH_k_CNTXT_9, + gsi_ctx->per.ee, arg1); + TERR("EV%2d CTX9 0x%x\n", arg1, val); + val = gsihal_read_reg_nk(GSI_EE_n_EV_CH_k_CNTXT_10, + gsi_ctx->per.ee, arg1); + TERR("EV%2d CTX10 0x%x\n", arg1, val); + val = gsihal_read_reg_nk(GSI_EE_n_EV_CH_k_CNTXT_11, + gsi_ctx->per.ee, arg1); + TERR("EV%2d CTX11 0x%x\n", arg1, val); + val = gsihal_read_reg_nk(GSI_EE_n_EV_CH_k_CNTXT_12, + gsi_ctx->per.ee, arg1); + TERR("EV%2d CTX12 0x%x\n", arg1, val); + val = gsihal_read_reg_nk(GSI_EE_n_EV_CH_k_CNTXT_13, + gsi_ctx->per.ee, arg1); + TERR("EV%2d CTX13 0x%x\n", arg1, val); + val = gsihal_read_reg_nk(GSI_EE_n_EV_CH_k_SCRATCH_0, + gsi_ctx->per.ee, arg1); + TERR("EV%2d SCR0 0x%x\n", arg1, val); + val = gsihal_read_reg_nk(GSI_EE_n_EV_CH_k_SCRATCH_1, + gsi_ctx->per.ee, arg1); + TERR("EV%2d SCR1 0x%x\n", arg1, val); + + gsi_ctx->per.unvote_clk_cb(); + + if (arg2) { + ctx = &gsi_ctx->evtr[arg1]; + + if (ctx->props.ring_base_vaddr) { + for (i = 0; i < ctx->props.ring_len / 16; i++) + TERR("EV%2d (0x%08llx) %08x %08x %08x %08x\n", + arg1, ctx->props.ring_base_addr + i * 16, + *(u32 *)((u8 *)ctx->props.ring_base_vaddr + + i * 16 + 0), + *(u32 *)((u8 *)ctx->props.ring_base_vaddr + + i * 16 + 4), + *(u32 *)((u8 *)ctx->props.ring_base_vaddr + + i * 16 + 8), + *(u32 *)((u8 *)ctx->props.ring_base_vaddr + + i * 16 + 12)); + } else { + TERR("No VA supplied for event ring id %u\n", arg1); + } + } + + return count; +} + +static ssize_t gsi_dump_ch(struct file *file, + const char __user *buf, size_t count, loff_t *ppos) +{ + u32 arg1; + u32 arg2; + unsigned long missing; + char *sptr, *token; + struct gsi_chan_ctx *ctx; + uint16_t i; + + if (count >= sizeof(dbg_buff)) + return -EINVAL; + + missing = copy_from_user(dbg_buff, buf, count); + if (missing) + return -EFAULT; + + dbg_buff[count] = '\0'; + + sptr = dbg_buff; + + token = strsep(&sptr, " "); + if (!token) + return -EINVAL; + if (kstrtou32(token, 0, &arg1)) + return -EINVAL; + + token = strsep(&sptr, " "); + if (!token) + return -EINVAL; + if (kstrtou32(token, 0, &arg2)) + return -EINVAL; + + TDBG("arg1=%u arg2=%u\n", arg1, arg2); + + if (arg1 >= gsi_ctx->max_ch) { + TERR("invalid chan id %u\n", arg1); + return -EINVAL; + } + + gsi_ctx->per.vote_clk_cb(); + gsi_dump_ch_info(arg1); + gsi_ctx->per.unvote_clk_cb(); + + if (arg2) { + ctx = &gsi_ctx->chan[arg1]; + + if (ctx->props.ring_base_vaddr) { + for (i = 0; i < ctx->props.ring_len / 16; i++) + TERR("CH%2d (0x%08llx) %08x %08x %08x %08x\n", + arg1, ctx->props.ring_base_addr + i * 16, + *(u32 *)((u8 *)ctx->props.ring_base_vaddr + + i * 16 + 0), + *(u32 *)((u8 *)ctx->props.ring_base_vaddr + + i * 16 + 4), + *(u32 *)((u8 *)ctx->props.ring_base_vaddr + + i * 16 + 8), + *(u32 *)((u8 *)ctx->props.ring_base_vaddr + + i * 16 + 12)); + } else { + TERR("No VA supplied for chan id %u\n", arg1); + } + } + + return count; +} + +static void gsi_dump_ch_stats(struct gsi_chan_ctx *ctx) +{ + if (!ctx->allocated) + return; + + PRT_STAT("CH%2d:\n", ctx->props.ch_id); + PRT_STAT("queued=%lu compl=%lu\n", + ctx->stats.queued, + ctx->stats.completed); + PRT_STAT("cb->poll=%lu poll->cb=%lu poll_pend_irq=%lu\n", + ctx->stats.callback_to_poll, + ctx->stats.poll_to_callback, + ctx->stats.poll_pending_irq); + PRT_STAT("invalid_tre_error=%lu\n", + ctx->stats.invalid_tre_error); + PRT_STAT("poll_ok=%lu poll_empty=%lu\n", + ctx->stats.poll_ok, ctx->stats.poll_empty); + if (ctx->evtr) + PRT_STAT("compl_evt=%lu\n", + ctx->evtr->stats.completed); + PRT_STAT("userdata_in_use=%lu\n", ctx->stats.userdata_in_use); + + PRT_STAT("ch_below_lo=%lu\n", ctx->stats.dp.ch_below_lo); + PRT_STAT("ch_below_hi=%lu\n", ctx->stats.dp.ch_below_hi); + PRT_STAT("ch_above_hi=%lu\n", ctx->stats.dp.ch_above_hi); + PRT_STAT("time_empty=%lums\n", ctx->stats.dp.empty_time); + PRT_STAT("\n"); +} + +static ssize_t gsi_dump_stats(struct file *file, + const char __user *buf, size_t count, loff_t *ppos) +{ + int ch_id; + int min, max, ret; + + ret = kstrtos32_from_user(buf, count, 0, &ch_id); + if (ret) + return ret; + + if (ch_id == -1) { + min = 0; + max = gsi_ctx->max_ch; + } else if (ch_id < 0 || ch_id >= gsi_ctx->max_ch || + !gsi_ctx->chan[ch_id].allocated) { + goto error; + } else { + min = ch_id; + max = ch_id + 1; + } + + for (ch_id = min; ch_id < max; ch_id++) + gsi_dump_ch_stats(&gsi_ctx->chan[ch_id]); + + return count; +error: + TERR("Usage: echo ch_id > stats. Use -1 for all\n"); + return -EINVAL; +} + +static int gsi_dbg_create_stats_wq(void) +{ + gsi_ctx->dp_stat_wq = + create_singlethread_workqueue("gsi_stat"); + if (!gsi_ctx->dp_stat_wq) { + TERR("failed create workqueue\n"); + return -ENOMEM; + } + + return 0; +} + +static void gsi_dbg_destroy_stats_wq(void) +{ + cancel_delayed_work_sync(&gsi_update_dp_stats_work); + cancel_delayed_work_sync(&gsi_print_dp_stats_work); + flush_workqueue(gsi_ctx->dp_stat_wq); + destroy_workqueue(gsi_ctx->dp_stat_wq); + gsi_ctx->dp_stat_wq = NULL; +} + +static ssize_t gsi_enable_dp_stats(struct file *file, + const char __user *buf, size_t count, loff_t *ppos) +{ + int ch_id; + bool enable; + int ret; + + if (count >= sizeof(dbg_buff)) + goto error; + + if (copy_from_user(dbg_buff, buf, count)) + goto error; + + dbg_buff[count] = '\0'; + + if (dbg_buff[0] != '+' && dbg_buff[0] != '-') + goto error; + + enable = (dbg_buff[0] == '+'); + + if (kstrtos32(dbg_buff + 1, 0, &ch_id)) + goto error; + + if (ch_id < 0 || ch_id >= gsi_ctx->max_ch || + !gsi_ctx->chan[ch_id].allocated) { + goto error; + } + + if (gsi_ctx->chan[ch_id].enable_dp_stats == enable) { + TERR("ch_%d: already enabled/disabled\n", ch_id); + return -EINVAL; + } + gsi_ctx->chan[ch_id].enable_dp_stats = enable; + + if (enable) + gsi_ctx->num_ch_dp_stats++; + else + gsi_ctx->num_ch_dp_stats--; + + if (enable) { + if (gsi_ctx->num_ch_dp_stats == 1) { + ret = gsi_dbg_create_stats_wq(); + if (ret) + return ret; + } + cancel_delayed_work_sync(&gsi_update_dp_stats_work); + queue_delayed_work(gsi_ctx->dp_stat_wq, + &gsi_update_dp_stats_work, msecs_to_jiffies(10)); + } else if (!enable && gsi_ctx->num_ch_dp_stats == 0) { + gsi_dbg_destroy_stats_wq(); + } + + return count; +error: + TERR("Usage: echo [+-]ch_id > enable_dp_stats\n"); + return -EINVAL; +} + +static ssize_t gsi_set_max_elem_dp_stats(struct file *file, + const char __user *buf, size_t count, loff_t *ppos) +{ + u32 ch_id; + u32 max_elem; + unsigned long missing; + char *sptr, *token; + + if (count >= sizeof(dbg_buff)) + goto error; + + missing = copy_from_user(dbg_buff, buf, count); + if (missing) + goto error; + + dbg_buff[count] = '\0'; + + sptr = dbg_buff; + + token = strsep(&sptr, " "); + if (!token) { + TERR("\n"); + goto error; + } + + if (kstrtou32(token, 0, &ch_id)) { + TERR("\n"); + goto error; + } + + token = strsep(&sptr, " "); + if (!token) { + /* get */ + if (kstrtou32(dbg_buff, 0, &ch_id)) + goto error; + if (ch_id >= gsi_ctx->max_ch) + goto error; + PRT_STAT("ch %d: max_re_expected=%d\n", ch_id, + gsi_ctx->chan[ch_id].props.max_re_expected); + return count; + } + if (kstrtou32(token, 0, &max_elem)) { + TERR("\n"); + goto error; + } + + TDBG("ch_id=%u max_elem=%u\n", ch_id, max_elem); + + if (ch_id >= gsi_ctx->max_ch) { + TERR("invalid chan id %u\n", ch_id); + goto error; + } + + gsi_ctx->chan[ch_id].props.max_re_expected = max_elem; + + return count; + +error: + TERR("Usage: (set) echo > max_elem_dp_stats\n"); + TERR("Usage: (get) echo > max_elem_dp_stats\n"); + return -EINVAL; +} + +static void gsi_wq_print_dp_stats(struct work_struct *work) +{ + int ch_id; + + for (ch_id = 0; ch_id < gsi_ctx->max_ch; ch_id++) { + if (gsi_ctx->chan[ch_id].print_dp_stats) + gsi_dump_ch_stats(&gsi_ctx->chan[ch_id]); + } + + queue_delayed_work(gsi_ctx->dp_stat_wq, &gsi_print_dp_stats_work, + msecs_to_jiffies(1000)); +} + +static void gsi_dbg_update_ch_dp_stats(struct gsi_chan_ctx *ctx) +{ + uint16_t start_hw; + uint16_t end_hw; + uint64_t rp_hw; + uint64_t wp_hw; + int ee = gsi_ctx->per.ee; + uint16_t used_hw; + + gsi_ctx->per.vote_clk_cb(); + + rp_hw = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_CNTXT_4, + ee, ctx->props.ch_id); + rp_hw |= ((uint64_t)gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_CNTXT_5, + ee, ctx->props.ch_id)) << 32; + + wp_hw = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_CNTXT_6, + ee, ctx->props.ch_id); + wp_hw |= ((uint64_t)gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_CNTXT_7, + ee, ctx->props.ch_id)) << 32; + + gsi_ctx->per.unvote_clk_cb(); + + start_hw = gsi_find_idx_from_addr(&ctx->ring, rp_hw); + end_hw = gsi_find_idx_from_addr(&ctx->ring, wp_hw); + + if (end_hw >= start_hw) + used_hw = end_hw - start_hw; + else + used_hw = ctx->ring.max_num_elem + 1 - (start_hw - end_hw); + + TDBG("ch %d used %d\n", ctx->props.ch_id, used_hw); + gsi_update_ch_dp_stats(ctx, used_hw); +} + +static void gsi_wq_update_dp_stats(struct work_struct *work) +{ + int ch_id; + + for (ch_id = 0; ch_id < gsi_ctx->max_ch; ch_id++) { + if (gsi_ctx->chan[ch_id].allocated && + gsi_ctx->chan[ch_id].enable_dp_stats) + gsi_dbg_update_ch_dp_stats(&gsi_ctx->chan[ch_id]); + } + + queue_delayed_work(gsi_ctx->dp_stat_wq, &gsi_update_dp_stats_work, + msecs_to_jiffies(10)); +} + + +static ssize_t gsi_rst_stats(struct file *file, + const char __user *buf, size_t count, loff_t *ppos) +{ + int ch_id; + int min, max, ret; + + ret = kstrtos32_from_user(buf, count, 0, &ch_id); + if (ret) + return ret; + + if (ch_id == -1) { + min = 0; + max = gsi_ctx->max_ch; + } else if (ch_id < 0 || ch_id >= gsi_ctx->max_ch || + !gsi_ctx->chan[ch_id].allocated) { + goto error; + } else { + min = ch_id; + max = ch_id + 1; + } + + for (ch_id = min; ch_id < max; ch_id++) + memset(&gsi_ctx->chan[ch_id].stats, 0, + sizeof(gsi_ctx->chan[ch_id].stats)); + + return count; +error: + TERR("Usage: echo ch_id > rst_stats. Use -1 for all\n"); + return -EINVAL; +} + +static ssize_t gsi_print_dp_stats(struct file *file, + const char __user *buf, size_t count, loff_t *ppos) +{ + int ch_id; + bool enable; + int ret; + + if (count >= sizeof(dbg_buff)) + goto error; + + if (copy_from_user(dbg_buff, buf, count)) + goto error; + + dbg_buff[count] = '\0'; + + if (dbg_buff[0] != '+' && dbg_buff[0] != '-') + goto error; + + enable = (dbg_buff[0] == '+'); + + if (kstrtos32(dbg_buff + 1, 0, &ch_id)) + goto error; + + if (ch_id < 0 || ch_id >= gsi_ctx->max_ch || + !gsi_ctx->chan[ch_id].allocated) { + goto error; + } + + if (gsi_ctx->chan[ch_id].print_dp_stats == enable) { + TERR("ch_%d: already enabled/disabled\n", ch_id); + return -EINVAL; + } + gsi_ctx->chan[ch_id].print_dp_stats = enable; + + if (enable) + gsi_ctx->num_ch_dp_stats++; + else + gsi_ctx->num_ch_dp_stats--; + + if (enable) { + if (gsi_ctx->num_ch_dp_stats == 1) { + ret = gsi_dbg_create_stats_wq(); + if (ret) + return ret; + } + cancel_delayed_work_sync(&gsi_print_dp_stats_work); + queue_delayed_work(gsi_ctx->dp_stat_wq, + &gsi_print_dp_stats_work, msecs_to_jiffies(10)); + } else if (!enable && gsi_ctx->num_ch_dp_stats == 0) { + gsi_dbg_destroy_stats_wq(); + } + + return count; +error: + TERR("Usage: echo [+-]ch_id > print_dp_stats\n"); + return -EINVAL; +} + +static ssize_t gsi_enable_ipc_low(struct file *file, + const char __user *ubuf, size_t count, loff_t *ppos) +{ + s8 option = 0; + int ret; + + ret = kstrtos8_from_user(ubuf, count, 0, &option); + if (ret) + return ret; + + mutex_lock(&gsi_ctx->mlock); + if (option) { + if (!gsi_ipc_logbuf_low) { + gsi_ipc_logbuf_low = + ipc_log_context_create(GSI_IPC_LOG_PAGES, + "gsi_low", MINIDUMP_MASK); + if (gsi_ipc_logbuf_low == NULL) + TERR("failed to get ipc_logbuf_low\n"); + } + gsi_ctx->ipc_logbuf_low = gsi_ipc_logbuf_low; + } else { + gsi_ctx->ipc_logbuf_low = NULL; + } + mutex_unlock(&gsi_ctx->mlock); + + return count; +} + +static ssize_t gsi_read_gsi_hw_profiling_stats(struct file *file, + char __user *buf, size_t count, loff_t *ppos) +{ + struct gsi_hw_profiling_data stats; + int ret, nbytes, cnt = 0; + u64 totalCycles = 0, util = 0; + + if (gsi_ctx->per.ver < GSI_VER_2_9) { + nbytes = scnprintf(dbg_buff, GSI_MAX_MSG_LEN, + "This feature only support on GSI2.9+\n"); + cnt += nbytes; + goto done; + } + + gsi_ctx->per.vote_clk_cb(); + ret = gsi_get_hw_profiling_stats(&stats); + gsi_ctx->per.unvote_clk_cb(); + + if (!ret) { + totalCycles = stats.mcs_busy_cnt + stats.mcs_idle_cnt + + stats.bp_and_pending_cnt; + if (totalCycles != 0) + util = div_u64( + 100 * (stats.mcs_busy_cnt + stats.bp_and_pending_cnt), + totalCycles); + else + util = 0; + + nbytes = scnprintf(dbg_buff, GSI_MAX_MSG_LEN, + "bp_count=0x%llx\n" + "bp_and_pending_count=0x%llx\n" + "mcs_busy=0x%llx\n" + "mcs_idle=0x%llx\n" + "total_cycle_count=0x%llx\n" + "utilization_percentage=%llu%%\n", + stats.bp_cnt, + stats.bp_and_pending_cnt, + stats.mcs_busy_cnt, + stats.mcs_idle_cnt, + totalCycles, + util); + cnt += nbytes; + } else { + nbytes = scnprintf(dbg_buff, GSI_MAX_MSG_LEN, + "Fail to read GSI HW Profiling stats\n"); + cnt += nbytes; + } +done: + return simple_read_from_buffer(buf, count, ppos, dbg_buff, cnt); +} + +static ssize_t gsi_read_gsi_fw_version(struct file *file, + char __user *buf, size_t count, loff_t *ppos) +{ + struct gsi_fw_version ver; + int ret, nbytes, cnt = 0; + + if (gsi_ctx->per.ver < GSI_VER_2_9) { + nbytes = scnprintf(dbg_buff, GSI_MAX_MSG_LEN, + "This feature only support on GSI2.9+\n"); + cnt += nbytes; + goto done; + } + + gsi_ctx->per.vote_clk_cb(); + ret = gsi_get_fw_version(&ver); + gsi_ctx->per.unvote_clk_cb(); + + if (!ret) { + nbytes = scnprintf(dbg_buff, GSI_MAX_MSG_LEN, + "hw=%d\nflavor=%d\nfw=%d\n", + ver.hw, + ver.flavor, + ver.fw); + cnt += nbytes; + } else { + nbytes = scnprintf(dbg_buff, GSI_MAX_MSG_LEN, + "Fail to read GSI FW version\n"); + cnt += nbytes; + } +done: + return simple_read_from_buffer(buf, count, ppos, dbg_buff, cnt); +} + +static const struct file_operations gsi_ev_dump_ops = { + .write = gsi_dump_evt, +}; + +static const struct file_operations gsi_ch_dump_ops = { + .write = gsi_dump_ch, +}; + +static const struct file_operations gsi_stats_ops = { + .write = gsi_dump_stats, +}; + +static const struct file_operations gsi_enable_dp_stats_ops = { + .write = gsi_enable_dp_stats, +}; + +static const struct file_operations gsi_max_elem_dp_stats_ops = { + .write = gsi_set_max_elem_dp_stats, +}; + +static const struct file_operations gsi_rst_stats_ops = { + .write = gsi_rst_stats, +}; + +static const struct file_operations gsi_print_dp_stats_ops = { + .write = gsi_print_dp_stats, +}; + +static const struct file_operations gsi_ipc_low_ops = { + .write = gsi_enable_ipc_low, +}; + +static const struct file_operations gsi_hw_profiling_ops = { + .read = gsi_read_gsi_hw_profiling_stats, +}; + +static const struct file_operations gsi_ver_ops = { + .read = gsi_read_gsi_fw_version, +}; + +void gsi_debugfs_init(void) +{ + static struct dentry *dfile; + const mode_t write_only_mode = 0220; + const mode_t read_only_mode = 0440; + + dent = debugfs_create_dir("gsi", 0); + if (IS_ERR(dent)) { + TERR("fail to create dir\n"); + return; + } + + dfile = debugfs_create_file("ev_dump", write_only_mode, + dent, 0, &gsi_ev_dump_ops); + if (!dfile || IS_ERR(dfile)) { + TERR("fail to create ev_dump file\n"); + goto fail; + } + + dfile = debugfs_create_file("ch_dump", write_only_mode, + dent, 0, &gsi_ch_dump_ops); + if (!dfile || IS_ERR(dfile)) { + TERR("fail to create ch_dump file\n"); + goto fail; + } + + dfile = debugfs_create_file("stats", write_only_mode, dent, + 0, &gsi_stats_ops); + if (!dfile || IS_ERR(dfile)) { + TERR("fail to create stats file\n"); + goto fail; + } + + dfile = debugfs_create_file("enable_dp_stats", write_only_mode, dent, + 0, &gsi_enable_dp_stats_ops); + if (!dfile || IS_ERR(dfile)) { + TERR("fail to create stats file\n"); + goto fail; + } + + dfile = debugfs_create_file("max_elem_dp_stats", write_only_mode, + dent, 0, &gsi_max_elem_dp_stats_ops); + if (!dfile || IS_ERR(dfile)) { + TERR("fail to create stats file\n"); + goto fail; + } + + dfile = debugfs_create_file("rst_stats", write_only_mode, + dent, 0, &gsi_rst_stats_ops); + if (!dfile || IS_ERR(dfile)) { + TERR("fail to create stats file\n"); + goto fail; + } + + dfile = debugfs_create_file("print_dp_stats", + write_only_mode, dent, 0, &gsi_print_dp_stats_ops); + if (!dfile || IS_ERR(dfile)) { + TERR("fail to create stats file\n"); + goto fail; + } + + dfile = debugfs_create_file("ipc_low", write_only_mode, + dent, 0, &gsi_ipc_low_ops); + if (!dfile || IS_ERR(dfile)) { + TERR("could not create ipc_low\n"); + goto fail; + } + + dfile = debugfs_create_file("gsi_hw_profiling_stats", read_only_mode, + dent, 0, &gsi_hw_profiling_ops); + if (!dfile || IS_ERR(dfile)) { + TERR("could not create gsi_hw_profiling_stats\n"); + goto fail; + } + + dfile = debugfs_create_file("gsi_fw_version", read_only_mode, dent, 0, + &gsi_ver_ops); + if (!dfile || IS_ERR(dfile)) { + TERR("could not create gsi_fw_version\n"); + goto fail; + } + + return; + +fail: + debugfs_remove_recursive(dent); +} diff --git a/qcom/opensource/dataipa/drivers/platform/msm/gsi/gsi_emulation.c b/qcom/opensource/dataipa/drivers/platform/msm/gsi/gsi_emulation.c new file mode 100644 index 0000000000..90019a3b40 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/gsi/gsi_emulation.c @@ -0,0 +1,227 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + */ + +#include "gsi_emulation.h" + +/* + * ***************************************************************************** + * The following used to set up the EMULATION interrupt controller... + * ***************************************************************************** + */ +int setup_emulator_cntrlr( + void __iomem *intcntrlr_base, + u32 intcntrlr_mem_size) +{ + uint32_t val, ver, intrCnt, rangeCnt, range; + + val = gsi_emu_readl(intcntrlr_base + GE_INT_CTL_VER_CNT); + + intrCnt = val & 0xFFFF; + ver = (val >> 16) & 0xFFFF; + rangeCnt = intrCnt / 32; + + GSIDBG( + "CTL_VER_CNT reg val(0x%x) intr cnt(%u) cntrlr ver(0x%x) rangeCnt(%u)\n", + val, intrCnt, ver, rangeCnt); + + /* + * Verify the interrupt controller version + */ + if (ver == 0 || ver == 0xFFFF || ver < DEO_IC_INT_CTL_VER_MIN) { + GSIERR( + "Error: invalid interrupt controller version 0x%x\n", + ver); + return -GSI_STATUS_INVALID_PARAMS; + } + + /* + * Verify the interrupt count + * + * NOTE: intrCnt must be at least one block and multiple of 32 + */ + if ((intrCnt % 32) != 0) { + GSIERR( + "Invalid interrupt count read from HW 0x%04x\n", + intrCnt); + return -GSI_STATUS_ERROR; + } + + /* + * Calculate number of ranges used, each range handles 32 int lines + */ + if (rangeCnt > DEO_IC_MAX_RANGE_CNT) { + GSIERR( + "SW interrupt limit(%u) passed, increase DEO_IC_MAX_RANGE_CNT(%u)\n", + rangeCnt, + DEO_IC_MAX_RANGE_CNT); + return -GSI_STATUS_ERROR; + } + + /* + * Let's take the last register offset minus the first + * register offset (ie. range) and compare it to the interrupt + * controller's dtsi defined memory size. The range better + * fit within the size. + */ + val = GE_SOFT_INT_n(rangeCnt-1) - GE_INT_CTL_VER_CNT; + if (val > intcntrlr_mem_size) { + GSIERR( + "Interrupt controller register range (%u) exceeds dtsi provisioned size (%u)\n", + val, intcntrlr_mem_size); + return -GSI_STATUS_ERROR; + } + + /* + * The following will disable the emulators interrupt controller, + * so that we can config it... + */ + GSIDBG("Writing GE_INT_MASTER_ENABLE\n"); + gsi_emu_writel( + 0x0, + intcntrlr_base + GE_INT_MASTER_ENABLE); + + /* + * Init register maps of all ranges + */ + for (range = 0; range < rangeCnt; range++) { + /* + * Disable all int sources by setting all enable clear bits + */ + GSIDBG("Writing GE_INT_ENABLE_CLEAR_n(%u)\n", range); + gsi_emu_writel( + 0xFFFFFFFF, + intcntrlr_base + GE_INT_ENABLE_CLEAR_n(range)); + + /* + * Clear all raw statuses + */ + GSIDBG("Writing GE_INT_CLEAR_n(%u)\n", range); + gsi_emu_writel( + 0xFFFFFFFF, + intcntrlr_base + GE_INT_CLEAR_n(range)); + + /* + * Init all int types + */ + GSIDBG("Writing GE_INT_TYPE_n(%u)\n", range); + gsi_emu_writel( + 0x0, + intcntrlr_base + GE_INT_TYPE_n(range)); + } + + /* + * The following tells the interrupt controller to interrupt us + * when it sees interrupts from ipa and/or gsi. + * + * Interrupts: + * =================================================================== + * DUT0 [ 63 : 16 ] + * ipa_irq [ 3 : 0 ] <---HERE + * ipa_gsi_bam_irq [ 7 : 4 ] <---HERE + * ipa_bam_apu_sec_error_irq [ 8 ] + * ipa_bam_apu_non_sec_error_irq [ 9 ] + * ipa_bam_xpu2_msa_intr [ 10 ] + * ipa_vmidmt_nsgcfgirpt [ 11 ] + * ipa_vmidmt_nsgirpt [ 12 ] + * ipa_vmidmt_gcfgirpt [ 13 ] + * ipa_vmidmt_girpt [ 14 ] + * bam_xpu3_qad_non_secure_intr_sp [ 15 ] + */ + GSIDBG("Writing GE_INT_ENABLE_n(0)\n"); + gsi_emu_writel( + 0x00FF, /* See <---HERE above */ + intcntrlr_base + GE_INT_ENABLE_n(0)); + + /* + * The following will enable the IC post config... + */ + GSIDBG("Writing GE_INT_MASTER_ENABLE\n"); + gsi_emu_writel( + 0x1, + intcntrlr_base + GE_INT_MASTER_ENABLE); + + return 0; +} + +/* + * ***************************************************************************** + * The following for EMULATION hard irq... + * ***************************************************************************** + */ +irqreturn_t emulator_hard_irq_isr( + int irq, + void *ctxt) +{ + struct gsi_ctx *gsi_ctx_ptr = (struct gsi_ctx *) ctxt; + + uint32_t val; + + val = gsi_emu_readl(gsi_ctx_ptr->intcntrlr_base + GE_INT_MASTER_STATUS); + + /* + * If bit zero is set, interrupt is for us, hence return IRQ_NONE + * when it's not set... + */ + if (!(val & 0x00000001)) + return IRQ_NONE; + + /* + * The following will mask (ie. turn off) future interrupts from + * the emulator's interrupt controller. It wil stay this way until + * we turn back on...which will be done in the bottom half + * (ie. emulator_soft_irq_isr)... + */ + gsi_emu_writel( + 0x0, + gsi_ctx_ptr->intcntrlr_base + GE_INT_OUT_ENABLE); + + return IRQ_WAKE_THREAD; +} + +/* + * ***************************************************************************** + * The following for EMULATION soft irq... + * ***************************************************************************** + */ +irqreturn_t emulator_soft_irq_isr( + int irq, + void *ctxt) +{ + struct gsi_ctx *gsi_ctx_ptr = (struct gsi_ctx *) ctxt; + + irqreturn_t retVal = IRQ_HANDLED; + uint32_t val; + + val = gsi_emu_readl(gsi_ctx_ptr->intcntrlr_base + GE_IRQ_STATUS_n(0)); + + GSIDBG("Got irq(%d) with status(0x%08X)\n", irq, val); + + if (val & 0xF0 && gsi_ctx_ptr->intcntrlr_gsi_isr) { + GSIDBG("Got gsi interrupt\n"); + retVal = gsi_ctx_ptr->intcntrlr_gsi_isr(irq, ctxt); + } + + if (val & 0x0F && gsi_ctx_ptr->intcntrlr_client_isr) { + GSIDBG("Got ipa interrupt\n"); + retVal = gsi_ctx_ptr->intcntrlr_client_isr(irq, 0); + } + + /* + * The following will clear the interrupts... + */ + gsi_emu_writel( + 0xFFFFFFFF, + gsi_ctx_ptr->intcntrlr_base + GE_INT_CLEAR_n(0)); + + /* + * The following will unmask (ie. turn on) future interrupts from + * the emulator's interrupt controller... + */ + gsi_emu_writel( + 0x1, + gsi_ctx_ptr->intcntrlr_base + GE_INT_OUT_ENABLE); + + return retVal; +} diff --git a/qcom/opensource/dataipa/drivers/platform/msm/gsi/gsi_emulation.h b/qcom/opensource/dataipa/drivers/platform/msm/gsi/gsi_emulation.h new file mode 100644 index 0000000000..b97750d34c --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/gsi/gsi_emulation.h @@ -0,0 +1,188 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + */ + +#if !defined(_GSI_EMULATION_H_) +# define _GSI_EMULATION_H_ + +# include + +# include "gsi.h" + +#if defined(CONFIG_IPA_EMULATION) +# include "gsi_emulation_stubs.h" +#endif + +# define gsi_emu_readl(c) (readl_relaxed(c)) +# define gsi_emu_writel(v, c) ({ __iowmb(); writel_relaxed((v), (c)); }) + +# define CNTRLR_BASE 0 + +/* + * The following file contains definitions and declarations that are + * germane only to the IPA emulation system, which is run from an X86 + * environment. Declaration's for non-X86 (ie. arm) are merely stubs + * to facilitate compile and link. + * + * Interrupt controller registers. + * Descriptions taken from the EMULATION interrupt controller SWI. + * - There is only one Master Enable register + * - Each group of 32 interrupt lines (range) is controlled by 8 registers, + * which are consecutive in memory: + * GE_INT_ENABLE_n + * GE_INT_ENABLE_CLEAR_n + * GE_INT_ENABLE_SET_n + * GE_INT_TYPE_n + * GE_IRQ_STATUS_n + * GE_RAW_STATUS_n + * GE_INT_CLEAR_n + * GE_SOFT_INT_n + * - After the above 8 registers, there are the registers of the next + * group (range) of 32 interrupt lines, and so on. + */ + +/** @brief The interrupt controller version and interrupt count register. + * Specifies interrupt controller version (upper 16 bits) and the + * number of interrupt lines supported by HW (lower 16 bits). + */ +# define GE_INT_CTL_VER_CNT \ + (CNTRLR_BASE + 0x0000) + +/** @brief Enable or disable physical IRQ output signal to the system, + * not affecting any status registers. + * + * 0x0 : DISABLE IRQ output disabled + * 0x1 : ENABLE IRQ output enabled + */ +# define GE_INT_OUT_ENABLE \ + (CNTRLR_BASE + 0x0004) + +/** @brief The IRQ master enable register. + * Bit #0: IRQ_ENABLE, set 0 to disable, 1 to enable. + */ +# define GE_INT_MASTER_ENABLE \ + (CNTRLR_BASE + 0x0008) + +# define GE_INT_MASTER_STATUS \ + (CNTRLR_BASE + 0x000C) + +/** @brief Each bit disables (bit=0, default) or enables (bit=1) the + * corresponding interrupt source + */ +# define GE_INT_ENABLE_n(n) \ + (CNTRLR_BASE + 0x0010 + 0x20 * (n)) + +/** @brief Write bit=1 to clear (to 0) the corresponding bit(s) in INT_ENABLE. + * Does nothing for bit=0 + */ +# define GE_INT_ENABLE_CLEAR_n(n) \ + (CNTRLR_BASE + 0x0014 + 0x20 * (n)) + +/** @brief Write bit=1 to set (to 1) the corresponding bit(s) in INT_ENABLE. + * Does nothing for bit=0 + */ +# define GE_INT_ENABLE_SET_n(n) \ + (CNTRLR_BASE + 0x0018 + 0x20 * (n)) + +/** @brief Select level (bit=0, default) or edge (bit=1) sensitive input + * detection logic for each corresponding interrupt source + */ +# define GE_INT_TYPE_n(n) \ + (CNTRLR_BASE + 0x001C + 0x20 * (n)) + +/** @brief Shows the interrupt sources captured in RAW_STATUS that have been + * steered to irq_n by INT_SELECT. Interrupts must also be enabled by + * INT_ENABLE and MASTER_ENABLE. Read only register. + * Bit values: 1=active, 0=inactive + */ +# define GE_IRQ_STATUS_n(n) \ + (CNTRLR_BASE + 0x0020 + 0x20 * (n)) + +/** @brief Shows the interrupt sources that have been latched by the input + * logic of the Interrupt Controller. Read only register. + * Bit values: 1=active, 0=inactive + */ +# define GE_RAW_STATUS_n(n) \ + (CNTRLR_BASE + 0x0024 + 0x20 * (n)) + +/** @brief Write bit=1 to clear the corresponding bit(s) in RAW_STATUS. + * Does nothing for bit=0 + */ +# define GE_INT_CLEAR_n(n) \ + (CNTRLR_BASE + 0x0028 + 0x20 * (n)) + +/** @brief Write bit=1 to set the corresponding bit(s) in RAW_STATUS. + * Does nothing for bit=0. + * @note Only functional for edge detected interrupts + */ +# define GE_SOFT_INT_n(n) \ + (CNTRLR_BASE + 0x002C + 0x20 * (n)) + +/** @brief Maximal number of ranges in SW. Each range supports 32 interrupt + * lines. If HW is extended considerably, increase this value + */ +# define DEO_IC_MAX_RANGE_CNT 8 + +/** @brief Size of the registers of one range in memory, in bytes */ +# define DEO_IC_RANGE_MEM_SIZE 32 /* SWI: 8 registers, no gaps */ + +/** @brief Minimal Interrupt controller HW version */ +# define DEO_IC_INT_CTL_VER_MIN 0x0102 + + +#if defined(CONFIG_IPA_EMULATION) /* declarations to follow */ + +/* + * ***************************************************************************** + * The following used to set up the EMULATION interrupt controller... + * ***************************************************************************** + */ +int setup_emulator_cntrlr( + void __iomem *intcntrlr_base, + u32 intcntrlr_mem_size); + +/* + * ***************************************************************************** + * The following for EMULATION hard irq... + * ***************************************************************************** + */ +irqreturn_t emulator_hard_irq_isr( + int irq, + void *ctxt); + +/* + * ***************************************************************************** + * The following for EMULATION soft irq... + * ***************************************************************************** + */ +irqreturn_t emulator_soft_irq_isr( + int irq, + void *ctxt); + +# else /* #if !defined(CONFIG_IPA_EMULATION) then definitions to follow */ + +static inline int setup_emulator_cntrlr( + void __iomem *intcntrlr_base, + u32 intcntrlr_mem_size) +{ + return 0; +} + +static inline irqreturn_t emulator_hard_irq_isr( + int irq, + void *ctxt) +{ + return IRQ_NONE; +} + +static inline irqreturn_t emulator_soft_irq_isr( + int irq, + void *ctxt) +{ + return IRQ_HANDLED; +} + +# endif /* #if defined(CONFIG_IPA_EMULATION) */ + +#endif /* #if !defined(_GSI_EMULATION_H_) */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/gsi/gsi_emulation_stubs.h b/qcom/opensource/dataipa/drivers/platform/msm/gsi/gsi_emulation_stubs.h new file mode 100644 index 0000000000..e6064bc058 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/gsi/gsi_emulation_stubs.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + */ + +#if !defined(_GSI_EMULATION_STUBS_H_) +# define _GSI_EMULATION_STUBS_H_ + +# include +# define __iowmb() wmb() /* used in gsi.h */ + +#endif /* #if !defined(_GSI_EMULATION_STUBS_H_) */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/gsi/gsi_trace.h b/qcom/opensource/dataipa/drivers/platform/msm/gsi/gsi_trace.h new file mode 100644 index 0000000000..3b481fec3c --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/gsi/gsi_trace.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#undef TRACE_SYSTEM +#define TRACE_SYSTEM gsi +#define TRACE_INCLUDE_FILE gsi_trace + +#if !defined(_GSI_TRACE_H) || defined(TRACE_HEADER_MULTI_READ) +#define _GSI_TRACE_H + +#include + + +TRACE_EVENT( + gsi_qtimer, + + TP_PROTO(u64 qtimer, bool is_ll, uint8_t evt, uint32_t ch, uint32_t msk), + + TP_ARGS(qtimer, is_ll, evt, ch, msk), + + TP_STRUCT__entry( + __field(u64, qtimer) + __field(bool, is_ll) + __field(uint8_t, evt) + __field(uint32_t, ch) + __field(uint32_t, msk) + ), + + TP_fast_assign( + __entry->qtimer = qtimer; + __entry->is_ll = is_ll; + __entry->evt = evt; + __entry->ch = ch; + __entry->msk = msk; + ), + + TP_printk("qtimer=%llu is_ll=%s, evt=%u, ch=0x%x, msk=0x%x", + __entry->qtimer, + __entry->is_ll ? "true" : "false", + __entry->evt, + __entry->ch, + __entry->msk) +); + +#endif /* _GSI_TRACE_H */ + +/* This part must be outside protection */ +#ifndef GSI_TRACE_INCLUDE_PATH +#ifdef CONFIG_IPA_VENDOR_DLKM +#define GSI_TRACE_INCLUDE_PATH ../../../../vendor/qcom/opensource/dataipa/drivers/platform/msm/gsi +#else +#define GSI_TRACE_INCLUDE_PATH ../../techpack/dataipa/drivers/platform/msm/gsi +#endif +#endif + +#define TRACE_INCLUDE_PATH GSI_TRACE_INCLUDE_PATH +#include diff --git a/qcom/opensource/dataipa/drivers/platform/msm/gsi/gsihal/gsihal.c b/qcom/opensource/dataipa/drivers/platform/msm/gsi/gsihal/gsihal.c new file mode 100644 index 0000000000..8cd571e626 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/gsi/gsihal/gsihal.c @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* +* Copyright (c) 2020, The Linux Foundation. All rights reserved. +*/ + +#include "gsihal_i.h" +#include "gsihal_reg.h" + +struct gsihal_context *gsihal_ctx; + +int gsihal_init(enum gsi_ver gsi_ver, void __iomem *base) +{ + int result = 0; + + GSIDBG("initializing GSI HAL, GSI ver %d, base = %pK\n", + gsi_ver, base); + + if (gsihal_ctx) { + GSIDBG("gsihal already initialized\n"); + if (base != gsihal_ctx->base) { + GSIERR( + "base address of early init is differnet.\n" + ); + WARN_ON(1); + } + result = -EEXIST; + goto bail_err_exit; + } + + if (gsi_ver < GSI_VER_1_0 || gsi_ver >= GSI_VER_MAX) { + GSIERR("invalid GSI version %d\n", gsi_ver); + result = -EINVAL; + goto bail_err_exit; + } + + if (!base) { + GSIERR("invalid memory io mapping addr\n"); + result = -EINVAL; + goto bail_err_exit; + } + + gsihal_ctx = kzalloc(sizeof(*gsihal_ctx), GFP_KERNEL); + if (!gsihal_ctx) { + GSIERR("kzalloc err for gsihal_ctx\n"); + result = -ENOMEM; + goto bail_err_exit; + } + + gsihal_ctx->gsi_ver = gsi_ver; + gsihal_ctx->base = base; + + if (gsihal_reg_init(gsi_ver)) { + GSIERR("failed to initialize gsihal regs\n"); + result = -EINVAL; + goto bail_free_ctx; + } + + return 0; +bail_free_ctx: + kfree(gsihal_ctx); + gsihal_ctx = NULL; +bail_err_exit: + return result; +} + +void gsihal_destroy(void) +{ + GSIDBG("Entry\n"); + kfree(gsihal_ctx); + gsihal_ctx = NULL; +} diff --git a/qcom/opensource/dataipa/drivers/platform/msm/gsi/gsihal/gsihal.h b/qcom/opensource/dataipa/drivers/platform/msm/gsi/gsihal/gsihal.h new file mode 100644 index 0000000000..bb5af17c6b --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/gsi/gsihal/gsihal.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* +* Copyright (c) 2030, The Linux Foundation. All rights reserved. +*/ + +#ifndef _GSIHAL_H_ +#define _GSIHAL_H_ + +#include "gsihal_reg.h" + +int gsihal_init(enum gsi_ver gsi_ver, void __iomem *base); +void gsihal_destroy(void); + +#endif /* _GSIHAL_H_ */ \ No newline at end of file diff --git a/qcom/opensource/dataipa/drivers/platform/msm/gsi/gsihal/gsihal_i.h b/qcom/opensource/dataipa/drivers/platform/msm/gsi/gsihal/gsihal_i.h new file mode 100644 index 0000000000..eece338f51 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/gsi/gsihal/gsihal_i.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* +* Copyright (c) 2020, The Linux Foundation. All rights reserved. +*/ + +#ifndef _GSIHAL_I_H_ +#define _GSIHAL_I_H_ + +#include "../gsi.h" +#include +#include + +struct gsihal_context { + enum gsi_ver gsi_ver; + void __iomem *base; +}; + +extern struct gsihal_context *gsihal_ctx; +#endif /* _GSIHAL_I_H_ */ \ No newline at end of file diff --git a/qcom/opensource/dataipa/drivers/platform/msm/gsi/gsihal/gsihal_reg.c b/qcom/opensource/dataipa/drivers/platform/msm/gsi/gsihal/gsihal_reg.c new file mode 100644 index 0000000000..7ef8cc6294 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/gsi/gsihal/gsihal_reg.c @@ -0,0 +1,2527 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* +* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. +* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. +*/ + +#include "gsihal_i.h" +#include "gsihal_reg_i.h" +#include "gsihal_reg.h" + +/* +* GSI_CH_BIT_MAP_ARR_SIZE - The number of cells in bit map +* registers for GSI channels. +* This is taken from the k range +* of each bit map register. +*/ +#define GSI_CH_BIT_MAP_ARR_SIZE (1) + +/* Utility macros to use with bit map arrays*/ +#define GSI_CH_BIT_MAP_CELL_NUM(num) ((num) >> 5) +#define GSI_BIT_MAP_CELL_MSK(num) (1 << (num - (GSI_CH_BIT_MAP_CELL_NUM(num) << 5))) + +#define gsi_readl(c) (readl_relaxed(c)) +#define gsi_writel(v, c) ({ __iowmb(); writel_relaxed((v), (c)); }) + +static const char *gsireg_name_to_str[GSI_REG_MAX] = { + __stringify(GSI_EE_n_CNTXT_TYPE_IRQ_MSK), + __stringify(GSI_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK), + __stringify(GSI_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK), + __stringify(GSI_EE_n_CNTXT_SRC_IEOB_IRQ_MSK), + __stringify(GSI_EE_n_CNTXT_GLOB_IRQ_EN), + __stringify(GSI_EE_n_CNTXT_GSI_IRQ_EN), + __stringify(GSI_EE_n_CNTXT_TYPE_IRQ), + __stringify(GSI_EE_n_CNTXT_SRC_GSI_CH_IRQ), + __stringify(GSI_EE_n_GSI_CH_k_CNTXT_0), + __stringify(GSI_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR), + __stringify(GSI_EE_n_CNTXT_SRC_EV_CH_IRQ), + __stringify(GSI_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR), + __stringify(GSI_EE_n_EV_CH_k_CNTXT_0), + __stringify(GSI_EE_n_CNTXT_GLOB_IRQ_STTS), + __stringify(GSI_EE_n_ERROR_LOG), + __stringify(GSI_EE_n_ERROR_LOG_CLR), + __stringify(GSI_EE_n_CNTXT_GLOB_IRQ_CLR), + __stringify(GSI_EE_n_EV_CH_k_DOORBELL_0), + __stringify(GSI_EE_n_GSI_CH_k_DOORBELL_0), + __stringify(GSI_EE_n_CNTXT_SRC_IEOB_IRQ), + __stringify(GSI_EE_n_CNTXT_SRC_IEOB_IRQ_CLR), + __stringify(GSI_INTER_EE_n_SRC_GSI_CH_IRQ), + __stringify(GSI_INTER_EE_n_SRC_GSI_CH_IRQ_CLR), + __stringify(GSI_INTER_EE_n_SRC_EV_CH_IRQ), + __stringify(GSI_INTER_EE_n_SRC_EV_CH_IRQ_CLR), + __stringify(GSI_EE_n_CNTXT_GSI_IRQ_STTS), + __stringify(GSI_EE_n_CNTXT_GSI_IRQ_CLR), + __stringify(GSI_EE_n_GSI_HW_PARAM), + __stringify(GSI_EE_n_GSI_HW_PARAM_0), + __stringify(GSI_EE_n_GSI_HW_PARAM_2), + __stringify(GSI_EE_n_GSI_HW_PARAM_4), + __stringify(GSI_EE_n_GSI_SW_VERSION), + __stringify(GSI_EE_n_CNTXT_INTSET), + __stringify(GSI_EE_n_CNTXT_MSI_BASE_LSB), + __stringify(GSI_EE_n_CNTXT_MSI_BASE_MSB), + __stringify(GSI_EE_n_GSI_STATUS), + __stringify(GSI_EE_n_CNTXT_SCRATCH_0), + __stringify(GSI_EE_n_EV_CH_k_CNTXT_1), + __stringify(GSI_EE_n_EV_CH_k_CNTXT_2), + __stringify(GSI_EE_n_EV_CH_k_CNTXT_3), + __stringify(GSI_EE_n_EV_CH_k_CNTXT_8), + __stringify(GSI_EE_n_EV_CH_k_CNTXT_9), + __stringify(GSI_EE_n_EV_CH_k_CNTXT_10), + __stringify(GSI_EE_n_EV_CH_k_CNTXT_11), + __stringify(GSI_EE_n_EV_CH_k_CNTXT_12), + __stringify(GSI_EE_n_EV_CH_k_CNTXT_13), + __stringify(GSI_EE_n_EV_CH_k_DOORBELL_1), + __stringify(GSI_EE_n_EV_CH_CMD), + __stringify(GSI_EE_n_EV_CH_k_SCRATCH_0), + __stringify(GSI_EE_n_EV_CH_k_SCRATCH_1), + __stringify(GSI_EE_n_GSI_CH_k_DOORBELL_1), + __stringify(GSI_EE_n_GSI_CH_k_QOS), + __stringify(GSI_EE_n_GSI_CH_k_CNTXT_1), + __stringify(GSI_EE_n_GSI_CH_k_CNTXT_2), + __stringify(GSI_EE_n_GSI_CH_k_CNTXT_3), + __stringify(GSI_EE_n_GSI_CH_CMD), + __stringify(GSI_EE_n_GSI_CH_k_SCRATCH_0), + __stringify(GSI_EE_n_GSI_CH_k_SCRATCH_1), + __stringify(GSI_EE_n_GSI_CH_k_SCRATCH_2), + __stringify(GSI_EE_n_GSI_CH_k_SCRATCH_3), + __stringify(GSI_EE_n_GSI_CH_k_SCRATCH_4), + __stringify(GSI_EE_n_GSI_CH_k_SCRATCH_5), + __stringify(GSI_EE_n_GSI_CH_k_SCRATCH_6), + __stringify(GSI_EE_n_GSI_CH_k_SCRATCH_7), + __stringify(GSI_EE_n_GSI_CH_k_SCRATCH_8), + __stringify(GSI_EE_n_GSI_CH_k_SCRATCH_9), + __stringify(GSI_EE_n_GSI_CH_k_CNTXT_4), + __stringify(GSI_EE_n_GSI_CH_k_CNTXT_5), + __stringify(GSI_EE_n_GSI_CH_k_CNTXT_6), + __stringify(GSI_EE_n_GSI_CH_k_CNTXT_7), + __stringify(GSI_EE_n_GSI_CH_k_CNTXT_8), + __stringify(GSI_EE_n_EV_CH_k_CNTXT_4), + __stringify(GSI_EE_n_EV_CH_k_CNTXT_5), + __stringify(GSI_EE_n_EV_CH_k_CNTXT_6), + __stringify(GSI_EE_n_EV_CH_k_CNTXT_7), + __stringify(GSI_GSI_IRAM_PTR_CH_CMD), + __stringify(GSI_GSI_IRAM_PTR_CH_DB), + __stringify(GSI_GSI_IRAM_PTR_CH_DIS_COMP), + __stringify(GSI_GSI_IRAM_PTR_CH_EMPTY), + __stringify(GSI_GSI_IRAM_PTR_EE_GENERIC_CMD), + __stringify(GSI_GSI_IRAM_PTR_EVENT_GEN_COMP), + __stringify(GSI_GSI_IRAM_PTR_INT_MOD_STOPPED), + __stringify(GSI_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0), + __stringify(GSI_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2), + __stringify(GSI_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1), + __stringify(GSI_GSI_IRAM_PTR_NEW_RE), + __stringify(GSI_GSI_IRAM_PTR_READ_ENG_COMP), + __stringify(GSI_GSI_IRAM_PTR_TIMER_EXPIRED), + __stringify(GSI_GSI_IRAM_PTR_EV_DB), + __stringify(GSI_GSI_IRAM_PTR_UC_GP_INT), + __stringify(GSI_GSI_IRAM_PTR_WRITE_ENG_COMP), + __stringify(GSI_GSI_IRAM_PTR_TLV_CH_NOT_FULL), + __stringify(GSI_IC_DISABLE_CHNL_BCK_PRS_LSB), + __stringify(GSI_IC_DISABLE_CHNL_BCK_PRS_MSB), + __stringify(GSI_IC_GEN_EVNT_BCK_PRS_LSB), + __stringify(GSI_IC_GEN_EVNT_BCK_PRS_MSB), + __stringify(GSI_IC_GEN_INT_BCK_PRS_LSB), + __stringify(GSI_IC_GEN_INT_BCK_PRS_MSB), + __stringify(GSI_IC_STOP_INT_MOD_BCK_PRS_LSB), + __stringify(GSI_IC_STOP_INT_MOD_BCK_PRS_MSB), + __stringify(GSI_IC_PROCESS_DESC_BCK_PRS_LSB), + __stringify(GSI_IC_PROCESS_DESC_BCK_PRS_MSB), + __stringify(GSI_IC_TLV_STOP_BCK_PRS_LSB), + __stringify(GSI_IC_TLV_STOP_BCK_PRS_MSB), + __stringify(GSI_IC_TLV_RESET_BCK_PRS_LSB), + __stringify(GSI_IC_TLV_RESET_BCK_PRS_MSB), + __stringify(GSI_IC_RGSTR_TIMER_BCK_PRS_LSB), + __stringify(GSI_IC_RGSTR_TIMER_BCK_PRS_MSB), + __stringify(GSI_IC_READ_BCK_PRS_LSB), + __stringify(GSI_IC_READ_BCK_PRS_MSB), + __stringify(GSI_IC_WRITE_BCK_PRS_LSB), + __stringify(GSI_IC_WRITE_BCK_PRS_MSB), + __stringify(GSI_IC_UCONTROLLER_GPR_BCK_PRS_LSB), + __stringify(GSI_IC_UCONTROLLER_GPR_BCK_PRS_MSB), + __stringify(GSI_GSI_PERIPH_BASE_ADDR_MSB), + __stringify(GSI_GSI_PERIPH_BASE_ADDR_LSB), + __stringify(GSI_GSI_MCS_CFG), + __stringify(GSI_GSI_CFG), + __stringify(GSI_EE_n_GSI_EE_GENERIC_CMD), + __stringify(GSI_MAP_EE_n_CH_k_VP_TABLE), + __stringify(GSI_EE_n_GSI_CH_k_RE_FETCH_READ_PTR), + __stringify(GSI_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR), + __stringify(GSI_GSI_INST_RAM_n), + __stringify(GSI_GSI_IRAM_PTR_MSI_DB), + __stringify(GSI_GSI_IRAM_PTR_INT_NOTIFY_MCS), + __stringify(GSI_EE_n_CNTXT_SRC_GSI_CH_IRQ_k), + __stringify(GSI_EE_n_CNTXT_SRC_EV_CH_IRQ_k), + __stringify(GSI_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k), + __stringify(GSI_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k), + __stringify(GSI_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_k), + __stringify(GSI_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_k), + __stringify(GSI_EE_n_CNTXT_SRC_IEOB_IRQ_k), + __stringify(GSI_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k), + __stringify(GSI_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_k), + __stringify(GSI_INTER_EE_n_SRC_GSI_CH_IRQ_k), + __stringify(GSI_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_k), + __stringify(GSI_INTER_EE_n_SRC_EV_CH_IRQ_k), + __stringify(GSI_INTER_EE_n_SRC_EV_CH_IRQ_CLR_k), + __stringify(GSI_GSI_SHRAM_n), + __stringify(GSI_GSI_MCS_PROFILING_BP_CNT_LSB), + __stringify(GSI_GSI_MCS_PROFILING_BP_CNT_MSB), + __stringify(GSI_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB), + __stringify(GSI_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB), + __stringify(GSI_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB), + __stringify(GSI_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB), + __stringify(GSI_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB), + __stringify(GSI_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB), + __stringify(GSI_EE_n_CH_k_CH_ALMST_EMPTY_THRSHOLD), + __stringify(GSI_EE_n_GSI_DEBUG_PC_FOR_DEBUG), + __stringify(GSI_EE_n_GSI_DEBUG_BUSY_REG), +}; + +/* +* gsihal_reg_name_str() - returns string that represent the register +* @reg_name: [in] register name +*/ +const char *gsihal_reg_name_str(enum gsihal_reg_name reg_name) +{ + if (reg_name < 0 || reg_name >= GSI_REG_MAX) { + GSIERR("requested name of invalid reg=%d\n", reg_name); + return "Invalid Register"; + } + + return gsireg_name_to_str[reg_name]; +} + +static void gsireg_construct_dummy(enum gsihal_reg_name reg, + const void *fields, u32 *val) +{ + GSIERR("No construct function for %s\n", + gsihal_reg_name_str(reg)); + WARN(1, "invalid register operation"); +} + +static void gsireg_parse_dummy(enum gsihal_reg_name reg, + void *fields, u32 val) +{ + GSIERR("No parse function for %s\n", + gsihal_reg_name_str(reg)); + WARN(1, "invalid register operation"); + +} + +/* +* struct gsihal_reg_obj - Register H/W information for specific GSI version +* @construct - CB to construct register value from abstracted structure +* @parse - CB to parse register value to abstracted structure +* @offset - register offset relative to base address +* @n_ofst - N parameterized register sub-offset +* @k_ofst - K parameterized register sub-offset +*/ +struct gsihal_reg_obj { + void(*construct)(enum gsihal_reg_name reg, const void *fields, + u32 *val); + void(*parse)(enum gsihal_reg_name reg, void *fields, + u32 val); + u32 offset; + u32 n_ofst; + u32 k_ofst; +}; + +static void gsireg_parse_ctx_type_irq(enum gsihal_reg_name reg, void *fields, + u32 val) +{ + struct gsihal_reg_ctx_type_irq *ctx = (struct gsihal_reg_ctx_type_irq *)fields; + + ctx->ch_ctrl = GSI_GETFIELD_FROM_REG(val, + GSI_EE_n_CNTXT_TYPE_IRQ_CH_CTRL_SHFT, + GSI_EE_n_CNTXT_TYPE_IRQ_CH_CTRL_BMSK); + ctx->ev_ctrl = GSI_GETFIELD_FROM_REG(val, + GSI_EE_n_CNTXT_TYPE_IRQ_EV_CTRL_SHFT, + GSI_EE_n_CNTXT_TYPE_IRQ_EV_CTRL_BMSK); + ctx->glob_ee = GSI_GETFIELD_FROM_REG(val, + GSI_EE_n_CNTXT_TYPE_IRQ_GLOB_EE_SHFT, + GSI_EE_n_CNTXT_TYPE_IRQ_GLOB_EE_BMSK); + ctx->ieob = GSI_GETFIELD_FROM_REG(val, + GSI_EE_n_CNTXT_TYPE_IRQ_IEOB_SHFT, + GSI_EE_n_CNTXT_TYPE_IRQ_IEOB_BMSK); + ctx->inter_ee_ch_ctrl = GSI_GETFIELD_FROM_REG(val, + GSI_EE_n_CNTXT_TYPE_IRQ_INTER_EE_CH_CTRL_SHFT, + GSI_EE_n_CNTXT_TYPE_IRQ_INTER_EE_CH_CTRL_BMSK); + ctx->inter_ee_ev_ctrl = GSI_GETFIELD_FROM_REG(val, + GSI_EE_n_CNTXT_TYPE_IRQ_INTER_EE_EV_CTRL_SHFT, + GSI_EE_n_CNTXT_TYPE_IRQ_INTER_EE_EV_CTRL_BMSK); + ctx->general = GSI_GETFIELD_FROM_REG(val, + GSI_EE_n_CNTXT_TYPE_IRQ_GENERAL_SHFT, + GSI_EE_n_CNTXT_TYPE_IRQ_GENERAL_BMSK); +} + +static void gsireg_parse_ch_k_cntxt_0(enum gsihal_reg_name reg, void *fields, + u32 val) +{ + struct gsihal_reg_ch_k_cntxt_0 *ch_k_ctxt = + (struct gsihal_reg_ch_k_cntxt_0 *) fields; + + ch_k_ctxt->element_size = GSI_GETFIELD_FROM_REG(val, + GSI_EE_n_GSI_CH_k_CNTXT_0_ELEMENT_SIZE_SHFT, + GSI_EE_n_GSI_CH_k_CNTXT_0_ELEMENT_SIZE_BMSK); + ch_k_ctxt->chstate = GSI_GETFIELD_FROM_REG(val, + GSI_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_SHFT, + GSI_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_BMSK); + ch_k_ctxt->erindex = GSI_GETFIELD_FROM_REG(val, + GSI_EE_n_GSI_CH_k_CNTXT_0_ERINDEX_SHFT, + GSI_EE_n_GSI_CH_k_CNTXT_0_ERINDEX_BMSK); + ch_k_ctxt->chid = GSI_GETFIELD_FROM_REG(val, + GSI_EE_n_GSI_CH_k_CNTXT_0_CHID_SHFT, + GSI_EE_n_GSI_CH_k_CNTXT_0_CHID_BMSK); + ch_k_ctxt->ee = GSI_GETFIELD_FROM_REG(val, + GSI_EE_n_GSI_CH_k_CNTXT_0_EE_SHFT, + GSI_EE_n_GSI_CH_k_CNTXT_0_EE_BMSK); + ch_k_ctxt->chtype_dir = GSI_GETFIELD_FROM_REG(val, + GSI_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_DIR_SHFT, + GSI_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_DIR_BMSK); + ch_k_ctxt->chtype_protocol = GSI_GETFIELD_FROM_REG(val, + GSI_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_SHFT, + GSI_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_BMSK); +} + +static void gsireg_parse_ch_k_cntxt_0_v2_5(enum gsihal_reg_name reg, + void *fields, u32 val) +{ + struct gsihal_reg_ch_k_cntxt_0 *ch_k_ctxt = + (struct gsihal_reg_ch_k_cntxt_0 *) fields; + + gsireg_parse_ch_k_cntxt_0(reg, fields, val); + ch_k_ctxt->chtype_protocol_msb = GSI_GETFIELD_FROM_REG(val, + GSI_V2_5_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_MSB_SHFT, + GSI_V2_5_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_MSB_BMSK); +} + +static void gsireg_parse_ch_k_cntxt_0_v3_0(enum gsihal_reg_name reg, + void *fields, u32 val) +{ + struct gsihal_reg_ch_k_cntxt_0 *ch_k_ctxt = + (struct gsihal_reg_ch_k_cntxt_0 *) fields; + + ch_k_ctxt->element_size = GSI_GETFIELD_FROM_REG(val, + GSI_EE_n_GSI_CH_k_CNTXT_0_ELEMENT_SIZE_SHFT, + GSI_EE_n_GSI_CH_k_CNTXT_0_ELEMENT_SIZE_BMSK); + ch_k_ctxt->chstate = GSI_GETFIELD_FROM_REG(val, + GSI_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_SHFT, + GSI_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_BMSK); + ch_k_ctxt->chid = GSI_GETFIELD_FROM_REG(val, + GSI_V3_0_EE_n_GSI_CH_k_CNTXT_0_CHID_SHFT, + GSI_V3_0_EE_n_GSI_CH_k_CNTXT_0_CHID_BMSK); + ch_k_ctxt->ee = GSI_GETFIELD_FROM_REG(val, + GSI_V3_0_EE_n_GSI_CH_k_CNTXT_0_EE_SHFT, + GSI_V3_0_EE_n_GSI_CH_k_CNTXT_0_EE_BMSK); + ch_k_ctxt->chtype_dir = GSI_GETFIELD_FROM_REG(val, + GSI_V3_0_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_DIR_SHFT, + GSI_V3_0_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_DIR_BMSK); + ch_k_ctxt->chtype_protocol = GSI_GETFIELD_FROM_REG(val, + GSI_V3_0_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_SHFT, + GSI_V3_0_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_BMSK); +} + +static void gsireg_parse_ch_k_cntxt_1_v3_0(enum gsihal_reg_name reg, + void *fields, u32 val) +{ + struct gsihal_reg_ch_k_cntxt_1 *ch_k_ctxt = + (struct gsihal_reg_ch_k_cntxt_1 *) fields; + + ch_k_ctxt->r_length = GSI_GETFIELD_FROM_REG(val, + GSI_V3_0_EE_n_GSI_CH_k_CNTXT_1_R_LENGTH_SHFT, + GSI_V3_0_EE_n_GSI_CH_k_CNTXT_1_R_LENGTH_BMSK); + ch_k_ctxt->erindex = GSI_GETFIELD_FROM_REG(val, + GSI_V3_0_EE_n_GSI_CH_k_CNTXT_1_ERINDEX_SHFT, + GSI_V3_0_EE_n_GSI_CH_k_CNTXT_1_ERINDEX_BMSK); +} + +static void gsireg_parse_ev_ch_k_cntxt_0_common(enum gsihal_reg_name reg, void *fields, + u32 val) +{ + struct gsihal_reg_ev_ch_k_cntxt_0 *ev_ch_k_ctxt = + (struct gsihal_reg_ev_ch_k_cntxt_0 *) fields; + + ev_ch_k_ctxt->element_size = GSI_GETFIELD_FROM_REG(val, + GSI_EE_n_EV_CH_k_CNTXT_0_ELEMENT_SIZE_SHFT, + GSI_EE_n_EV_CH_k_CNTXT_0_ELEMENT_SIZE_BMSK); + ev_ch_k_ctxt->chstate = GSI_GETFIELD_FROM_REG(val, + GSI_EE_n_EV_CH_k_CNTXT_0_CHSTATE_SHFT, + GSI_EE_n_EV_CH_k_CNTXT_0_CHSTATE_BMSK); + ev_ch_k_ctxt->evchid = GSI_GETFIELD_FROM_REG(val, + GSI_EE_n_EV_CH_k_CNTXT_0_EVCHID_SHFT, + GSI_EE_n_EV_CH_k_CNTXT_0_EVCHID_BMSK); +} + +static void gsireg_parse_ev_ch_k_cntxt_0(enum gsihal_reg_name reg, void *fields, + u32 val) +{ + struct gsihal_reg_ev_ch_k_cntxt_0 *ev_ch_k_ctxt = + (struct gsihal_reg_ev_ch_k_cntxt_0 *) fields; + + gsireg_parse_ev_ch_k_cntxt_0_common(reg, fields, val); + + ev_ch_k_ctxt->intype = GSI_GETFIELD_FROM_REG(val, + GSI_EE_n_EV_CH_k_CNTXT_0_INTYPE_SHFT, + GSI_EE_n_EV_CH_k_CNTXT_0_INTYPE_BMSK); + ev_ch_k_ctxt->ee = GSI_GETFIELD_FROM_REG(val, + GSI_EE_n_EV_CH_k_CNTXT_0_EE_SHFT, + GSI_EE_n_EV_CH_k_CNTXT_0_EE_BMSK); + ev_ch_k_ctxt->chtype = GSI_GETFIELD_FROM_REG(val, + GSI_EE_n_EV_CH_k_CNTXT_0_CHTYPE_SHFT, + GSI_EE_n_EV_CH_k_CNTXT_0_CHTYPE_BMSK); +} + +static void gsireg_parse_ev_ch_k_cntxt_0_v3_0(enum gsihal_reg_name reg, void *fields, + u32 val) +{ + struct gsihal_reg_ev_ch_k_cntxt_0 *ev_ch_k_ctxt = + (struct gsihal_reg_ev_ch_k_cntxt_0 *) fields; + + gsireg_parse_ev_ch_k_cntxt_0_common(reg, fields, val); + + ev_ch_k_ctxt->ee = GSI_GETFIELD_FROM_REG(val, + GSI_V3_0_EE_n_EV_CH_k_CNTXT_0_EE_SHFT, + GSI_V3_0_EE_n_EV_CH_k_CNTXT_0_EE_BMSK); + ev_ch_k_ctxt->intype = GSI_GETFIELD_FROM_REG(val, + GSI_V3_0_EE_n_EV_CH_k_CNTXT_0_INTYPE_SHFT, + GSI_V3_0_EE_n_EV_CH_k_CNTXT_0_INTYPE_BMSK); + ev_ch_k_ctxt->chtype = GSI_GETFIELD_FROM_REG(val, + GSI_V3_0_EE_n_EV_CH_k_CNTXT_0_CHTYPE_SHFT, + GSI_V3_0_EE_n_EV_CH_k_CNTXT_0_CHTYPE_BMSK); +} + +static void gsireg_construct_ev_ch_k_cntxt_0_common(enum gsihal_reg_name reg, + const void *fields, u32 *val) +{ + struct gsihal_reg_ev_ch_k_cntxt_0 *ctxt = + (struct gsihal_reg_ev_ch_k_cntxt_0 *)fields; + + GSI_SETFIELD_IN_REG(*val, ctxt->element_size, + GSI_EE_n_EV_CH_k_CNTXT_0_ELEMENT_SIZE_SHFT, + GSI_EE_n_EV_CH_k_CNTXT_0_ELEMENT_SIZE_BMSK); + GSI_SETFIELD_IN_REG(*val, ctxt->chstate, + GSI_EE_n_EV_CH_k_CNTXT_0_CHSTATE_SHFT, + GSI_EE_n_EV_CH_k_CNTXT_0_CHSTATE_BMSK); + GSI_SETFIELD_IN_REG(*val, ctxt->evchid, + GSI_EE_n_EV_CH_k_CNTXT_0_EVCHID_SHFT, + GSI_EE_n_EV_CH_k_CNTXT_0_EVCHID_BMSK); +} + +static void gsireg_construct_ev_ch_k_cntxt_0(enum gsihal_reg_name reg, + const void *fields, u32 *val) +{ + struct gsihal_reg_ev_ch_k_cntxt_0 *ctxt = + (struct gsihal_reg_ev_ch_k_cntxt_0 *)fields; + + gsireg_construct_ev_ch_k_cntxt_0_common(reg, fields, val); + + GSI_SETFIELD_IN_REG(*val, ctxt->intype, + GSI_EE_n_EV_CH_k_CNTXT_0_INTYPE_SHFT, + GSI_EE_n_EV_CH_k_CNTXT_0_INTYPE_BMSK); + GSI_SETFIELD_IN_REG(*val, ctxt->ee, + GSI_EE_n_EV_CH_k_CNTXT_0_EE_SHFT, + GSI_EE_n_EV_CH_k_CNTXT_0_EE_BMSK); + GSI_SETFIELD_IN_REG(*val, ctxt->chtype, + GSI_EE_n_EV_CH_k_CNTXT_0_CHTYPE_SHFT, + GSI_EE_n_EV_CH_k_CNTXT_0_CHTYPE_BMSK); +} + +static void gsireg_construct_ev_ch_k_cntxt_0_v3_0(enum gsihal_reg_name reg, + const void *fields, u32 *val) +{ + struct gsihal_reg_ev_ch_k_cntxt_0 *ctxt = + (struct gsihal_reg_ev_ch_k_cntxt_0 *)fields; + + gsireg_construct_ev_ch_k_cntxt_0_common(reg, fields, val); + + GSI_SETFIELD_IN_REG(*val, ctxt->ee, + GSI_V3_0_EE_n_EV_CH_k_CNTXT_0_EE_SHFT, + GSI_V3_0_EE_n_EV_CH_k_CNTXT_0_EE_BMSK); + GSI_SETFIELD_IN_REG(*val, ctxt->intype, + GSI_V3_0_EE_n_EV_CH_k_CNTXT_0_INTYPE_SHFT, + GSI_V3_0_EE_n_EV_CH_k_CNTXT_0_INTYPE_BMSK); + GSI_SETFIELD_IN_REG(*val, ctxt->chtype, + GSI_V3_0_EE_n_EV_CH_k_CNTXT_0_CHTYPE_SHFT, + GSI_V3_0_EE_n_EV_CH_k_CNTXT_0_CHTYPE_BMSK); +} + +static void gsireg_parse_cntxt_glob_irq_stts(enum gsihal_reg_name reg, + void *fields, u32 val) +{ + struct gsihal_reg_cntxt_glob_irq_stts *glob_irq_stts = + (struct gsihal_reg_cntxt_glob_irq_stts *) fields; + + glob_irq_stts->gp_int3 = GSI_GETFIELD_FROM_REG(val, + GSI_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT3_SHFT, + GSI_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT3_BMSK); + glob_irq_stts->gp_int2 = GSI_GETFIELD_FROM_REG(val, + GSI_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT2_SHFT, + GSI_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT2_BMSK); + glob_irq_stts->gp_int1 = GSI_GETFIELD_FROM_REG(val, + GSI_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT1_SHFT, + GSI_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT1_BMSK); + glob_irq_stts->error_int = GSI_GETFIELD_FROM_REG(val, + GSI_EE_n_CNTXT_GLOB_IRQ_STTS_ERROR_INT_SHFT, + GSI_EE_n_CNTXT_GLOB_IRQ_STTS_ERROR_INT_BMSK); +} + +static void gsireg_parse_cntxt_gsi_irq_stts(enum gsihal_reg_name reg, + void *fields, u32 val) +{ + struct gsihal_reg_cntxt_gsi_irq_stts *gsi_irq_stts = + (struct gsihal_reg_cntxt_gsi_irq_stts *) fields; + + gsi_irq_stts->gsi_mcs_stack_ovrflow = GSI_GETFIELD_FROM_REG(val, + GSI_EE_n_CNTXT_GSI_IRQ_STTS_GSI_MCS_STACK_OVRFLOW_SHFT, + GSI_EE_n_CNTXT_GSI_IRQ_STTS_GSI_MCS_STACK_OVRFLOW_BMSK); + gsi_irq_stts->gsi_cmd_fifo_ovrflow = GSI_GETFIELD_FROM_REG(val, + GSI_EE_n_CNTXT_GSI_IRQ_STTS_GSI_CMD_FIFO_OVRFLOW_SHFT, + GSI_EE_n_CNTXT_GSI_IRQ_STTS_GSI_CMD_FIFO_OVRFLOW_BMSK); + gsi_irq_stts->gsi_bus_error = GSI_GETFIELD_FROM_REG(val, + GSI_EE_n_CNTXT_GSI_IRQ_STTS_GSI_BUS_ERROR_SHFT, + GSI_EE_n_CNTXT_GSI_IRQ_STTS_GSI_BUS_ERROR_BMSK); + gsi_irq_stts->gsi_break_point = GSI_GETFIELD_FROM_REG(val, + GSI_EE_n_CNTXT_GSI_IRQ_STTS_GSI_BREAK_POINT_SHFT, + GSI_EE_n_CNTXT_GSI_IRQ_STTS_GSI_BREAK_POINT_BMSK); +} + +static void gsireg_parse_hw_param(enum gsihal_reg_name reg, + void *fields, u32 val) +{ + struct gsihal_reg_hw_param *hw_param = + (struct gsihal_reg_hw_param *) fields; + + hw_param->periph_sec_grp = GSI_GETFIELD_FROM_REG(val, + GSI_V1_0_EE_n_GSI_HW_PARAM_PERIPH_SEC_GRP_SHFT, + GSI_V1_0_EE_n_GSI_HW_PARAM_PERIPH_SEC_GRP_BMSK); + hw_param->use_axi_m = GSI_GETFIELD_FROM_REG(val, + GSI_V1_0_EE_n_GSI_HW_PARAM_USE_AXI_M_SHFT, + GSI_V1_0_EE_n_GSI_HW_PARAM_USE_AXI_M_BMSK); + hw_param->periph_conf_addr_bus_w = GSI_GETFIELD_FROM_REG(val, + GSI_V1_0_EE_n_GSI_HW_PARAM_PERIPH_CONF_ADDR_BUS_W_SHFT, + GSI_V1_0_EE_n_GSI_HW_PARAM_PERIPH_CONF_ADDR_BUS_W_BMSK); + hw_param->num_ees = GSI_GETFIELD_FROM_REG(val, + GSI_V1_0_EE_n_GSI_HW_PARAM_NUM_EES_SHFT, + GSI_V1_0_EE_n_GSI_HW_PARAM_NUM_EES_BMSK); + hw_param->gsi_ch_num = GSI_GETFIELD_FROM_REG(val, + GSI_V1_0_EE_n_GSI_HW_PARAM_GSI_CH_NUM_SHFT, + GSI_V1_0_EE_n_GSI_HW_PARAM_GSI_CH_NUM_BMSK); + hw_param->gsi_ev_ch_num = GSI_GETFIELD_FROM_REG(val, + GSI_V1_0_EE_n_GSI_HW_PARAM_GSI_EV_CH_NUM_SHFT, + GSI_V1_0_EE_n_GSI_HW_PARAM_GSI_EV_CH_NUM_BMSK); +} + +static void gsireg_parse_hw_param0(enum gsihal_reg_name reg, + void *fields, u32 val) +{ + struct gsihal_reg_hw_param *hw_param = + (struct gsihal_reg_hw_param *) fields; + + hw_param->periph_sec_grp = GSI_GETFIELD_FROM_REG(val, + GSI_V1_2_EE_n_GSI_HW_PARAM_0_PERIPH_SEC_GRP_SHFT, + GSI_V1_2_EE_n_GSI_HW_PARAM_0_PERIPH_SEC_GRP_BMSK); + hw_param->use_axi_m = GSI_GETFIELD_FROM_REG(val, + GSI_V1_2_EE_n_GSI_HW_PARAM_0_USE_AXI_M_SHFT, + GSI_V1_2_EE_n_GSI_HW_PARAM_0_USE_AXI_M_BMSK); + hw_param->periph_conf_addr_bus_w = GSI_GETFIELD_FROM_REG(val, + GSI_V1_2_EE_n_GSI_HW_PARAM_0_PERIPH_CONF_ADDR_BUS_W_SHFT, + GSI_V1_2_EE_n_GSI_HW_PARAM_0_PERIPH_CONF_ADDR_BUS_W_BMSK); + hw_param->num_ees = GSI_GETFIELD_FROM_REG(val, + GSI_V1_2_EE_n_GSI_HW_PARAM_0_NUM_EES_SHFT, + GSI_V1_2_EE_n_GSI_HW_PARAM_0_NUM_EES_BMSK); + hw_param->gsi_ch_num = GSI_GETFIELD_FROM_REG(val, + GSI_V1_2_EE_n_GSI_HW_PARAM_0_GSI_CH_NUM_SHFT, + GSI_V1_2_EE_n_GSI_HW_PARAM_0_GSI_CH_NUM_BMSK); + hw_param->gsi_ev_ch_num = GSI_GETFIELD_FROM_REG(val, + GSI_V1_2_EE_n_GSI_HW_PARAM_0_GSI_EV_CH_NUM_SHFT, + GSI_V1_2_EE_n_GSI_HW_PARAM_0_GSI_EV_CH_NUM_BMSK); +} + +static void gsireg_parse_hw_param2(enum gsihal_reg_name reg, + void *fields, u32 val) +{ + struct gsihal_reg_hw_param2 *hw_param = + (struct gsihal_reg_hw_param2 *) fields; + + hw_param->gsi_ch_full_logic = GSI_GETFIELD_FROM_REG(val, + GSI_V1_3_EE_n_GSI_HW_PARAM_2_GSI_CH_FULL_LOGIC_SHFT, + GSI_V1_3_EE_n_GSI_HW_PARAM_2_GSI_CH_FULL_LOGIC_BMSK); + hw_param->gsi_ch_pend_translate = GSI_GETFIELD_FROM_REG(val, + GSI_V1_3_EE_n_GSI_HW_PARAM_2_GSI_CH_PEND_TRANSLATE_SHFT, + GSI_V1_3_EE_n_GSI_HW_PARAM_2_GSI_CH_PEND_TRANSLATE_BMSK); + hw_param->gsi_num_ev_per_ee = GSI_GETFIELD_FROM_REG(val, + GSI_V1_3_EE_n_GSI_HW_PARAM_2_GSI_NUM_EV_PER_EE_SHFT, + GSI_V1_3_EE_n_GSI_HW_PARAM_2_GSI_NUM_EV_PER_EE_BMSK); + hw_param->gsi_num_ch_per_ee = GSI_GETFIELD_FROM_REG(val, + GSI_V1_3_EE_n_GSI_HW_PARAM_2_GSI_NUM_CH_PER_EE_SHFT, + GSI_V1_3_EE_n_GSI_HW_PARAM_2_GSI_NUM_CH_PER_EE_BMSK); + hw_param->gsi_iram_size = GSI_GETFIELD_FROM_REG(val, + GSI_V1_3_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_SHFT, + GSI_V1_3_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_BMSK); +} + +static void gsireg_parse_hw_param2_v2_0(enum gsihal_reg_name reg, + void *fields, u32 val) +{ + struct gsihal_reg_hw_param2 *hw_param = + (struct gsihal_reg_hw_param2 *) fields; + + gsireg_parse_hw_param2(reg, fields, val); + + hw_param->gsi_sdma_n_iovec = GSI_GETFIELD_FROM_REG(val, + GSI_V2_0_EE_n_GSI_HW_PARAM_2_GSI_SDMA_N_IOVEC_SHFT, + GSI_V2_0_EE_n_GSI_HW_PARAM_2_GSI_SDMA_N_IOVEC_BMSK); + hw_param->gsi_sdma_max_burst = GSI_GETFIELD_FROM_REG(val, + GSI_V2_0_EE_n_GSI_HW_PARAM_2_GSI_SDMA_MAX_BURST_SHFT, + GSI_V2_0_EE_n_GSI_HW_PARAM_2_GSI_SDMA_MAX_BURST_BMSK); + hw_param->gsi_sdma_n_int = GSI_GETFIELD_FROM_REG(val, + GSI_V2_0_EE_n_GSI_HW_PARAM_2_GSI_SDMA_N_INT_SHFT, + GSI_V2_0_EE_n_GSI_HW_PARAM_2_GSI_SDMA_N_INT_BMSK); + hw_param->gsi_use_sdma = GSI_GETFIELD_FROM_REG(val, + GSI_V2_0_EE_n_GSI_HW_PARAM_2_GSI_USE_SDMA_SHFT, + GSI_V2_0_EE_n_GSI_HW_PARAM_2_GSI_USE_SDMA_BMSK); + +} + +static void gsireg_parse_hw_param2_v2_2(enum gsihal_reg_name reg, + void *fields, u32 val) +{ + struct gsihal_reg_hw_param2 *hw_param = + (struct gsihal_reg_hw_param2 *) fields; + + gsireg_parse_hw_param2_v2_0(reg, fields, val); + + hw_param->gsi_use_inter_ee = GSI_GETFIELD_FROM_REG(val, + GSI_V2_2_EE_n_GSI_HW_PARAM_2_GSI_USE_INTER_EE_SHFT, + GSI_V2_2_EE_n_GSI_HW_PARAM_2_GSI_USE_INTER_EE_BMSK); + hw_param->gsi_use_rd_wr_eng = GSI_GETFIELD_FROM_REG(val, + GSI_V2_2_EE_n_GSI_HW_PARAM_2_GSI_USE_RD_WR_ENG_SHFT, + GSI_V2_2_EE_n_GSI_HW_PARAM_2_GSI_USE_RD_WR_ENG_BMSK); +} + +static void gsireg_parse_hw_param2_v3_0(enum gsihal_reg_name reg, + void *fields, u32 val) +{ + struct gsihal_reg_hw_param2 *hw_param = + (struct gsihal_reg_hw_param2 *) fields; + + hw_param->gsi_ch_full_logic = GSI_GETFIELD_FROM_REG(val, + GSI_V1_3_EE_n_GSI_HW_PARAM_2_GSI_CH_FULL_LOGIC_SHFT, + GSI_V1_3_EE_n_GSI_HW_PARAM_2_GSI_CH_FULL_LOGIC_BMSK); + hw_param->gsi_ch_pend_translate = GSI_GETFIELD_FROM_REG(val, + GSI_V1_3_EE_n_GSI_HW_PARAM_2_GSI_CH_PEND_TRANSLATE_SHFT, + GSI_V1_3_EE_n_GSI_HW_PARAM_2_GSI_CH_PEND_TRANSLATE_BMSK); + hw_param->gsi_num_ch_per_ee = GSI_GETFIELD_FROM_REG(val, + GSI_V3_0_EE_n_GSI_HW_PARAM_2_GSI_NUM_CH_PER_EE_SHFT, + GSI_V3_0_EE_n_GSI_HW_PARAM_2_GSI_NUM_CH_PER_EE_BMSK); + hw_param->gsi_iram_size = GSI_GETFIELD_FROM_REG(val, + GSI_V3_0_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_SHFT, + GSI_V3_0_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_BMSK); + hw_param->gsi_sdma_n_iovec = GSI_GETFIELD_FROM_REG(val, + GSI_V2_0_EE_n_GSI_HW_PARAM_2_GSI_SDMA_N_IOVEC_SHFT, + GSI_V2_0_EE_n_GSI_HW_PARAM_2_GSI_SDMA_N_IOVEC_BMSK); + hw_param->gsi_sdma_max_burst = GSI_GETFIELD_FROM_REG(val, + GSI_V2_0_EE_n_GSI_HW_PARAM_2_GSI_SDMA_MAX_BURST_SHFT, + GSI_V2_0_EE_n_GSI_HW_PARAM_2_GSI_SDMA_MAX_BURST_BMSK); + hw_param->gsi_sdma_n_int = GSI_GETFIELD_FROM_REG(val, + GSI_V2_0_EE_n_GSI_HW_PARAM_2_GSI_SDMA_N_INT_SHFT, + GSI_V2_0_EE_n_GSI_HW_PARAM_2_GSI_SDMA_N_INT_BMSK); + hw_param->gsi_use_sdma = GSI_GETFIELD_FROM_REG(val, + GSI_V2_0_EE_n_GSI_HW_PARAM_2_GSI_USE_SDMA_SHFT, + GSI_V2_0_EE_n_GSI_HW_PARAM_2_GSI_USE_SDMA_BMSK); + hw_param->gsi_use_inter_ee = GSI_GETFIELD_FROM_REG(val, + GSI_V2_2_EE_n_GSI_HW_PARAM_2_GSI_USE_INTER_EE_SHFT, + GSI_V2_2_EE_n_GSI_HW_PARAM_2_GSI_USE_INTER_EE_BMSK); + hw_param->gsi_use_rd_wr_eng = GSI_GETFIELD_FROM_REG(val, + GSI_V2_2_EE_n_GSI_HW_PARAM_2_GSI_USE_RD_WR_ENG_SHFT, + GSI_V2_2_EE_n_GSI_HW_PARAM_2_GSI_USE_RD_WR_ENG_BMSK); +} + +static void gsireg_parse_hw_param4_v3_0(enum gsihal_reg_name reg, + void *fields, u32 val) +{ + struct gsihal_reg_hw_param4 *hw_param = + (struct gsihal_reg_hw_param4 *) fields; + + hw_param->gsi_iram_protcol_cnt = GSI_GETFIELD_FROM_REG(val, + GSI_V3_0_EE_n_GSI_HW_PARAM_4_GSI_IRAM_PROTCOL_CNT_SHFT, + GSI_V3_0_EE_n_GSI_HW_PARAM_4_GSI_IRAM_PROTCOL_CNT_BMSK); + hw_param->gsi_num_ev_per_ee = GSI_GETFIELD_FROM_REG(val, + GSI_V3_0_EE_n_GSI_HW_PARAM_4_GSI_NUM_EV_PER_EE_SHFT, + GSI_V3_0_EE_n_GSI_HW_PARAM_4_GSI_NUM_EV_PER_EE_BMSK); +} + +static void gsireg_parse_gsi_status(enum gsihal_reg_name reg, + void *fields, u32 val) +{ + struct gsihal_reg_gsi_status *gsi_status = + (struct gsihal_reg_gsi_status *) fields; + + gsi_status->enabled = GSI_GETFIELD_FROM_REG(val, + GSI_EE_n_GSI_STATUS_ENABLED_SHFT, + GSI_EE_n_GSI_STATUS_ENABLED_BMSK); +} + +static void gsireg_construct_ev_ch_k_cntxt_1(enum gsihal_reg_name reg, + const void *fields, u32 *val) +{ + struct gsihal_reg_ev_ch_k_cntxt_1 *ctxt = + (struct gsihal_reg_ev_ch_k_cntxt_1 *)fields; + + GSI_SETFIELD_IN_REG(*val, ctxt->r_length, + GSI_EE_n_EV_CH_k_CNTXT_1_R_LENGTH_SHFT, + GSI_EE_n_EV_CH_k_CNTXT_1_R_LENGTH_BMSK); +} + +static void gsireg_construct_ev_ch_k_cntxt_1_v2_9(enum gsihal_reg_name reg, + const void *fields, u32 *val) +{ + struct gsihal_reg_ev_ch_k_cntxt_1 *ctxt = + (struct gsihal_reg_ev_ch_k_cntxt_1 *)fields; + + GSI_SETFIELD_IN_REG(*val, ctxt->r_length, + GSI_V2_9_EE_n_EV_CH_k_CNTXT_1_R_LENGTH_SHFT, + GSI_V2_9_EE_n_EV_CH_k_CNTXT_1_R_LENGTH_BMSK); +} + +static void gsireg_construct_ev_ch_k_cntxt_1_v3_0(enum gsihal_reg_name reg, + const void *fields, u32 *val) +{ + struct gsihal_reg_ev_ch_k_cntxt_1 *ctxt = + (struct gsihal_reg_ev_ch_k_cntxt_1 *)fields; + + GSI_SETFIELD_IN_REG(*val, ctxt->r_length, + GSI_V3_0_EE_n_EV_CH_k_CNTXT_1_R_LENGTH_SHFT, + GSI_V3_0_EE_n_EV_CH_k_CNTXT_1_R_LENGTH_BMSK); +} + +static void gsireg_construct_ev_ch_k_cntxt_2(enum gsihal_reg_name reg, + const void *fields, u32 *val) +{ + struct gsihal_reg_ev_ch_k_cntxt_2 *ctxt = + (struct gsihal_reg_ev_ch_k_cntxt_2 *)fields; + + GSI_SETFIELD_IN_REG(*val, ctxt->r_base_addr_lsbs, + GSI_EE_n_EV_CH_k_CNTXT_2_R_BASE_ADDR_LSBS_SHFT, + GSI_EE_n_EV_CH_k_CNTXT_2_R_BASE_ADDR_LSBS_BMSK); +} + +static void gsireg_construct_ev_ch_k_cntxt_3(enum gsihal_reg_name reg, + const void *fields, u32 *val) +{ + struct gsihal_reg_ev_ch_k_cntxt_3 *ctxt = + (struct gsihal_reg_ev_ch_k_cntxt_3 *)fields; + + GSI_SETFIELD_IN_REG(*val, ctxt->r_base_addr_msbs, + GSI_EE_n_EV_CH_k_CNTXT_3_R_BASE_ADDR_MSBS_SHFT, + GSI_EE_n_EV_CH_k_CNTXT_3_R_BASE_ADDR_MSBS_BMSK); +} + +static void gsireg_construct_ev_ch_k_cntxt_8(enum gsihal_reg_name reg, + const void *fields, u32 *val) +{ + struct gsihal_reg_ev_ch_k_cntxt_8 *ctxt = + (struct gsihal_reg_ev_ch_k_cntxt_8 *)fields; + + GSI_SETFIELD_IN_REG(*val, ctxt->int_mod_cnt, + GSI_EE_n_EV_CH_k_CNTXT_8_INT_MOD_CNT_SHFT, + GSI_EE_n_EV_CH_k_CNTXT_8_INT_MOD_CNT_BMSK); + GSI_SETFIELD_IN_REG(*val, ctxt->int_modc, + GSI_EE_n_EV_CH_k_CNTXT_8_INT_MODC_SHFT, + GSI_EE_n_EV_CH_k_CNTXT_8_INT_MODC_BMSK); + GSI_SETFIELD_IN_REG(*val, ctxt->int_modt, + GSI_EE_n_EV_CH_k_CNTXT_8_INT_MODT_SHFT, + GSI_EE_n_EV_CH_k_CNTXT_8_INT_MODT_BMSK); +} + +static void gsireg_construct_ev_ch_k_cntxt_9(enum gsihal_reg_name reg, + const void *fields, u32 *val) +{ + struct gsihal_reg_ev_ch_k_cntxt_9 *ctxt = + (struct gsihal_reg_ev_ch_k_cntxt_9 *)fields; + + GSI_SETFIELD_IN_REG(*val, ctxt->intvec, + GSI_EE_n_EV_CH_k_CNTXT_9_INTVEC_SHFT, + GSI_EE_n_EV_CH_k_CNTXT_9_INTVEC_BMSK); +} + +static void gsireg_construct_ev_ch_k_cntxt_10(enum gsihal_reg_name reg, + const void *fields, u32 *val) +{ + union gsihal_reg_ev_ch_k_cntxt_10 *ctxt = + (union gsihal_reg_ev_ch_k_cntxt_10 *)fields; + + GSI_SETFIELD_IN_REG(*val, ctxt->msi_addr_lsb, + GSI_EE_n_EV_CH_k_CNTXT_10_ADDR_LSB_SHFT, + GSI_EE_n_EV_CH_k_CNTXT_10_ADDR_LSB_BMSK); +} + +static void gsireg_construct_ev_ch_k_cntxt_11(enum gsihal_reg_name reg, + const void *fields, u32 *val) +{ + union gsihal_reg_ev_ch_k_cntxt_11 *ctxt = + (union gsihal_reg_ev_ch_k_cntxt_11 *)fields; + + GSI_SETFIELD_IN_REG(*val, ctxt->msi_addr_msb, + GSI_EE_n_EV_CH_k_CNTXT_11_ADDR_MSB_SHFT, + GSI_EE_n_EV_CH_k_CNTXT_11_ADDR_MSB_BMSK); +} + +static void gsireg_construct_ev_ch_k_cntxt_12(enum gsihal_reg_name reg, + const void *fields, u32 *val) +{ + struct gsihal_reg_ev_ch_k_cntxt_12 *ctxt = + (struct gsihal_reg_ev_ch_k_cntxt_12 *)fields; + + GSI_SETFIELD_IN_REG(*val, ctxt->rp_update_addr_lsb, + GSI_EE_n_EV_CH_k_CNTXT_12_RP_UPDATE_ADDR_LSB_SHFT, + GSI_EE_n_EV_CH_k_CNTXT_12_RP_UPDATE_ADDR_LSB_BMSK); +} + +static void gsireg_construct_ev_ch_k_cntxt_13(enum gsihal_reg_name reg, + const void *fields, u32 *val) +{ + struct gsihal_reg_ev_ch_k_cntxt_13 *ctxt = + (struct gsihal_reg_ev_ch_k_cntxt_13 *)fields; + + GSI_SETFIELD_IN_REG(*val, ctxt->rp_update_addr_msb, + GSI_EE_n_EV_CH_k_CNTXT_13_RP_UPDATE_ADDR_MSB_SHFT, + GSI_EE_n_EV_CH_k_CNTXT_13_RP_UPDATE_ADDR_MSB_BMSK); +} + +static void gsireg_construct_ev_ch_k_doorbell_1(enum gsihal_reg_name reg, + const void *fields, u32 *val) +{ + struct gsihal_reg_gsi_ee_n_ev_ch_k_doorbell_1 *db = + (struct gsihal_reg_gsi_ee_n_ev_ch_k_doorbell_1 *)fields; + + GSI_SETFIELD_IN_REG(*val, db->write_ptr_msb, + GSI_EE_n_EV_CH_k_DOORBELL_1_WRITE_PTR_MSB_SHFT, + GSI_EE_n_EV_CH_k_DOORBELL_1_WRITE_PTR_MSB_BMSK); +} + +static void gsireg_construct_ee_n_ev_ch_cmd(enum gsihal_reg_name reg, + const void *fields, u32 *val) +{ + struct gsihal_reg_ee_n_ev_ch_cmd *ev_ch_cmd = + (struct gsihal_reg_ee_n_ev_ch_cmd *)fields; + + GSI_SETFIELD_IN_REG(*val, ev_ch_cmd->opcode, + GSI_EE_n_EV_CH_CMD_OPCODE_SHFT, + GSI_EE_n_EV_CH_CMD_OPCODE_BMSK); + GSI_SETFIELD_IN_REG(*val, ev_ch_cmd->chid, + GSI_EE_n_EV_CH_CMD_CHID_SHFT, + GSI_EE_n_EV_CH_CMD_CHID_BMSK); +} + +static void gsireg_construct_ee_n_gsi_ch_k_qos(enum gsihal_reg_name reg, + const void *fields, u32 *val) +{ + struct gsihal_reg_gsi_ee_n_gsi_ch_k_qos *ch_qos = + (struct gsihal_reg_gsi_ee_n_gsi_ch_k_qos *)fields; + + GSI_SETFIELD_IN_REG(*val, !!ch_qos->use_db_eng, + GSI_EE_n_GSI_CH_k_QOS_USE_DB_ENG_SHFT, + GSI_EE_n_GSI_CH_k_QOS_USE_DB_ENG_BMSK); + GSI_SETFIELD_IN_REG(*val, !!ch_qos->max_prefetch, + GSI_EE_n_GSI_CH_k_QOS_MAX_PREFETCH_SHFT, + GSI_EE_n_GSI_CH_k_QOS_MAX_PREFETCH_BMSK); + GSI_SETFIELD_IN_REG(*val, ch_qos->wrr_weight, + GSI_EE_n_GSI_CH_k_QOS_WRR_WEIGHT_SHFT, + GSI_EE_n_GSI_CH_k_QOS_WRR_WEIGHT_BMSK); +} + +static void gsireg_construct_ee_n_gsi_ch_k_qos_v1_2(enum gsihal_reg_name reg, + const void *fields, u32 *val) +{ + struct gsihal_reg_gsi_ee_n_gsi_ch_k_qos *ch_qos = + (struct gsihal_reg_gsi_ee_n_gsi_ch_k_qos *)fields; + + gsireg_construct_ee_n_gsi_ch_k_qos(reg, fields, val); + + GSI_SETFIELD_IN_REG(*val, !!ch_qos->use_escape_buf_only, + GSI_V2_0_EE_n_GSI_CH_k_QOS_USE_ESCAPE_BUF_ONLY_SHFT, + GSI_V2_0_EE_n_GSI_CH_k_QOS_USE_ESCAPE_BUF_ONLY_BMSK); +} + +static void gsireg_construct_ee_n_gsi_ch_k_qos_v2_5(enum gsihal_reg_name reg, + const void *fields, u32 *val) +{ + struct gsihal_reg_gsi_ee_n_gsi_ch_k_qos *ch_qos = + (struct gsihal_reg_gsi_ee_n_gsi_ch_k_qos *)fields; + + gsireg_construct_ee_n_gsi_ch_k_qos(reg, fields, val); + + GSI_SETFIELD_IN_REG(*val, ch_qos->empty_lvl_thrshold, + GSI_V2_5_EE_n_GSI_CH_k_QOS_EMPTY_LVL_THRSHOLD_SHFT, + GSI_V2_9_EE_n_GSI_CH_k_QOS_EMPTY_LVL_THRSHOLD_BMSK); + + GSI_SETFIELD_IN_REG(*val, ch_qos->prefetch_mode, + GSI_V2_5_EE_n_GSI_CH_k_QOS_PREFETCH_MODE_SHFT, + GSI_V2_5_EE_n_GSI_CH_k_QOS_PREFETCH_MODE_BMSK); +} + +static void gsireg_construct_ee_n_gsi_ch_k_qos_v2_9(enum gsihal_reg_name reg, + const void *fields, u32 *val) +{ + struct gsihal_reg_gsi_ee_n_gsi_ch_k_qos *ch_qos = + (struct gsihal_reg_gsi_ee_n_gsi_ch_k_qos *)fields; + + gsireg_construct_ee_n_gsi_ch_k_qos_v2_5(reg, fields, val); + + GSI_SETFIELD_IN_REG(*val, !!ch_qos->db_in_bytes, + GSI_V2_9_EE_n_GSI_CH_k_QOS_DB_IN_BYTES_SHFT, + GSI_V2_9_EE_n_GSI_CH_k_QOS_DB_IN_BYTES_BMSK); +} + +static void gsireg_construct_ee_n_gsi_ch_k_qos_v3_0(enum gsihal_reg_name reg, + const void *fields, u32 *val) +{ + struct gsihal_reg_gsi_ee_n_gsi_ch_k_qos *ch_qos = + (struct gsihal_reg_gsi_ee_n_gsi_ch_k_qos *)fields; + + gsireg_construct_ee_n_gsi_ch_k_qos_v2_9(reg, fields, val); + + GSI_SETFIELD_IN_REG(*val, !!ch_qos->low_latency_en, + GSI_V3_0_EE_n_GSI_CH_k_QOS_LOW_LATENCY_EN_SHFT, + GSI_V3_0_EE_n_GSI_CH_k_QOS_LOW_LATENCY_EN_BMSK); +} + +static void gsireg_construct_ch_k_cntxt_0_common(enum gsihal_reg_name reg, + const void *fields, u32 *val) +{ + struct gsihal_reg_ch_k_cntxt_0 *ch_cntxt = + (struct gsihal_reg_ch_k_cntxt_0 *)fields; + + GSI_SETFIELD_IN_REG(*val, ch_cntxt->element_size, + GSI_EE_n_GSI_CH_k_CNTXT_0_ELEMENT_SIZE_SHFT, + GSI_EE_n_GSI_CH_k_CNTXT_0_ELEMENT_SIZE_BMSK); + GSI_SETFIELD_IN_REG(*val, ch_cntxt->chstate, + GSI_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_SHFT, + GSI_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_BMSK); +} + +static void gsireg_construct_ch_k_cntxt_0(enum gsihal_reg_name reg, + const void *fields, u32 *val) +{ + struct gsihal_reg_ch_k_cntxt_0 *ch_cntxt = + (struct gsihal_reg_ch_k_cntxt_0 *)fields; + + gsireg_construct_ch_k_cntxt_0_common(reg, fields, val); + + GSI_SETFIELD_IN_REG(*val, ch_cntxt->erindex, + GSI_EE_n_GSI_CH_k_CNTXT_0_ERINDEX_SHFT, + GSI_EE_n_GSI_CH_k_CNTXT_0_ERINDEX_BMSK); + GSI_SETFIELD_IN_REG(*val, ch_cntxt->chid, + GSI_EE_n_GSI_CH_k_CNTXT_0_CHID_SHFT, + GSI_EE_n_GSI_CH_k_CNTXT_0_CHID_BMSK); + GSI_SETFIELD_IN_REG(*val, ch_cntxt->ee, + GSI_EE_n_GSI_CH_k_CNTXT_0_EE_SHFT, + GSI_EE_n_GSI_CH_k_CNTXT_0_EE_BMSK); + GSI_SETFIELD_IN_REG(*val, !!ch_cntxt->chtype_dir, + GSI_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_DIR_SHFT, + GSI_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_DIR_BMSK); + GSI_SETFIELD_IN_REG(*val, ch_cntxt->chtype_protocol, + GSI_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_SHFT, + GSI_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_BMSK); +} + +static void gsireg_construct_ch_k_cntxt_0_v2_5(enum gsihal_reg_name reg, + const void *fields, u32 *val) +{ + struct gsihal_reg_ch_k_cntxt_0 *ch_cntxt = + (struct gsihal_reg_ch_k_cntxt_0 *)fields; + + gsireg_construct_ch_k_cntxt_0(reg, fields, val); + + GSI_SETFIELD_IN_REG(*val, !!ch_cntxt->chtype_protocol_msb, + GSI_V2_5_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_MSB_SHFT, + GSI_V2_5_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_MSB_BMSK); +} + +static void gsireg_construct_ch_k_cntxt_0_v3_0(enum gsihal_reg_name reg, + const void *fields, u32 *val) +{ + struct gsihal_reg_ch_k_cntxt_0 *ch_cntxt = + (struct gsihal_reg_ch_k_cntxt_0 *)fields; + + gsireg_construct_ch_k_cntxt_0_common(reg, fields, val); + + GSI_SETFIELD_IN_REG(*val, ch_cntxt->chid, + GSI_V3_0_EE_n_GSI_CH_k_CNTXT_0_CHID_SHFT, + GSI_V3_0_EE_n_GSI_CH_k_CNTXT_0_CHID_BMSK); + GSI_SETFIELD_IN_REG(*val, ch_cntxt->ee, + GSI_V3_0_EE_n_GSI_CH_k_CNTXT_0_EE_SHFT, + GSI_V3_0_EE_n_GSI_CH_k_CNTXT_0_EE_BMSK); + GSI_SETFIELD_IN_REG(*val, !!ch_cntxt->chtype_dir, + GSI_V3_0_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_DIR_SHFT, + GSI_V3_0_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_DIR_BMSK); + GSI_SETFIELD_IN_REG(*val, ch_cntxt->chtype_protocol, + GSI_V3_0_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_SHFT, + GSI_V3_0_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_BMSK); +} + +static void gsireg_construct_ch_k_cntxt_1(enum gsihal_reg_name reg, + const void *fields, u32 *val) +{ + struct gsihal_reg_ch_k_cntxt_1 *ch_cntxt = + (struct gsihal_reg_ch_k_cntxt_1 *)fields; + + GSI_SETFIELD_IN_REG(*val, ch_cntxt->r_length, + GSI_EE_n_GSI_CH_k_CNTXT_1_R_LENGTH_SHFT, + GSI_EE_n_GSI_CH_k_CNTXT_1_R_LENGTH_BMSK); +} + +static void gsireg_construct_ch_k_cntxt_1_v2_9(enum gsihal_reg_name reg, + const void *fields, u32 *val) +{ + struct gsihal_reg_ch_k_cntxt_1 *ch_cntxt = + (struct gsihal_reg_ch_k_cntxt_1 *)fields; + + GSI_SETFIELD_IN_REG(*val, ch_cntxt->r_length, + GSI_V2_9_EE_n_GSI_CH_k_CNTXT_1_R_LENGTH_SHFT, + GSI_V2_9_EE_n_GSI_CH_k_CNTXT_1_R_LENGTH_BMSK); +} + +static void gsireg_construct_ch_k_cntxt_1_v3_0(enum gsihal_reg_name reg, + const void *fields, u32 *val) +{ + struct gsihal_reg_ch_k_cntxt_1 *ch_cntxt = + (struct gsihal_reg_ch_k_cntxt_1 *)fields; + + GSI_SETFIELD_IN_REG(*val, ch_cntxt->r_length, + GSI_V3_0_EE_n_GSI_CH_k_CNTXT_1_R_LENGTH_SHFT, + GSI_V3_0_EE_n_GSI_CH_k_CNTXT_1_R_LENGTH_BMSK); + GSI_SETFIELD_IN_REG(*val, ch_cntxt->erindex, + GSI_V3_0_EE_n_GSI_CH_k_CNTXT_1_ERINDEX_SHFT, + GSI_V3_0_EE_n_GSI_CH_k_CNTXT_1_ERINDEX_BMSK); +} + +static void gsireg_construct_ee_n_gsi_ch_cmd(enum gsihal_reg_name reg, + const void *fields, u32 *val) +{ + struct gsihal_reg_ee_n_gsi_ch_cmd *ev_ch_cmd = + (struct gsihal_reg_ee_n_gsi_ch_cmd *)fields; + + GSI_SETFIELD_IN_REG(*val, ev_ch_cmd->opcode, + GSI_EE_n_GSI_CH_CMD_OPCODE_SHFT, + GSI_EE_n_GSI_CH_CMD_OPCODE_BMSK); + GSI_SETFIELD_IN_REG(*val, ev_ch_cmd->chid, + GSI_EE_n_GSI_CH_CMD_CHID_SHFT, + GSI_EE_n_GSI_CH_CMD_CHID_BMSK); +} + +static void gsireg_construct_gsi_cfg(enum gsihal_reg_name reg, + const void *fields, u32 *val) +{ + struct gsihal_reg_gsi_cfg *gsi_cfg = + (struct gsihal_reg_gsi_cfg *)fields; + + GSI_SETFIELD_IN_REG(*val, !!gsi_cfg->bp_mtrix_disable, + GSI_GSI_CFG_BP_MTRIX_DISABLE_SHFT, + GSI_GSI_CFG_BP_MTRIX_DISABLE_BMSK); + GSI_SETFIELD_IN_REG(*val, !!gsi_cfg->gsi_pwr_clps, + GSI_GSI_CFG_GSI_PWR_CLPS_SHFT, + GSI_GSI_CFG_GSI_PWR_CLPS_BMSK); + GSI_SETFIELD_IN_REG(*val, !!gsi_cfg->uc_is_mcs, + GSI_GSI_CFG_UC_IS_MCS_SHFT, + GSI_GSI_CFG_UC_IS_MCS_BMSK); + GSI_SETFIELD_IN_REG(*val, !!gsi_cfg->double_mcs_clk_freq, + GSI_GSI_CFG_DOUBLE_MCS_CLK_FREQ_SHFT, + GSI_GSI_CFG_DOUBLE_MCS_CLK_FREQ_BMSK); + GSI_SETFIELD_IN_REG(*val, !!gsi_cfg->mcs_enable, + GSI_GSI_CFG_MCS_ENABLE_SHFT, + GSI_GSI_CFG_MCS_ENABLE_BMSK); + GSI_SETFIELD_IN_REG(*val, !!gsi_cfg->gsi_enable, + GSI_GSI_CFG_GSI_ENABLE_SHFT, + GSI_GSI_CFG_GSI_ENABLE_BMSK); +} + +static void gsireg_construct_gsi_cfg_v2_5(enum gsihal_reg_name reg, + const void *fields, u32 *val) +{ + struct gsihal_reg_gsi_cfg *gsi_cfg = + (struct gsihal_reg_gsi_cfg *)fields; + + gsireg_construct_gsi_cfg(reg, fields, val); + GSI_SETFIELD_IN_REG(*val, gsi_cfg->sleep_clk_div, + GSI_V2_5_GSI_CFG_SLEEP_CLK_DIV_SHFT, + GSI_V2_5_GSI_CFG_SLEEP_CLK_DIV_BMSK); +} + +static void gsireg_construct_gsi_ee_generic_cmd(enum gsihal_reg_name reg, + const void *fields, u32 *val) +{ + struct gsihal_reg_gsi_ee_generic_cmd *cmd = + (struct gsihal_reg_gsi_ee_generic_cmd *)fields; + + GSI_SETFIELD_IN_REG(*val, cmd->opcode, + GSI_EE_n_GSI_EE_GENERIC_CMD_OPCODE_SHFT, + GSI_EE_n_GSI_EE_GENERIC_CMD_OPCODE_BMSK); + GSI_SETFIELD_IN_REG(*val, cmd->virt_chan_idx, + GSI_EE_n_GSI_EE_GENERIC_CMD_VIRT_CHAN_IDX_SHFT, + GSI_EE_n_GSI_EE_GENERIC_CMD_VIRT_CHAN_IDX_BMSK); + GSI_SETFIELD_IN_REG(*val, cmd->ee, + GSI_EE_n_GSI_EE_GENERIC_CMD_EE_SHFT, + GSI_EE_n_GSI_EE_GENERIC_CMD_EE_BMSK); +} + +static void gsireg_construct_gsi_ee_generic_cmd_v3_0(enum gsihal_reg_name reg, + const void *fields, u32 *val) +{ + struct gsihal_reg_gsi_ee_generic_cmd *cmd = + (struct gsihal_reg_gsi_ee_generic_cmd *)fields; + + GSI_SETFIELD_IN_REG(*val, cmd->opcode, + GSI_EE_n_GSI_EE_GENERIC_CMD_OPCODE_SHFT, + GSI_EE_n_GSI_EE_GENERIC_CMD_OPCODE_BMSK); + GSI_SETFIELD_IN_REG(*val, cmd->virt_chan_idx, + GSI_V3_0_EE_n_GSI_EE_GENERIC_CMD_VIRT_CHAN_IDX_SHFT, + GSI_V3_0_EE_n_GSI_EE_GENERIC_CMD_VIRT_CHAN_IDX_BMSK); + GSI_SETFIELD_IN_REG(*val, cmd->ee, + GSI_V3_0_EE_n_GSI_EE_GENERIC_CMD_EE_SHFT, + GSI_V3_0_EE_n_GSI_EE_GENERIC_CMD_EE_BMSK); + GSI_SETFIELD_IN_REG(*val, cmd->prmy_scnd_fc, + GSI_V3_0_EE_n_GSI_EE_GENERIC_CMD_PARAM_SHFT, + GSI_V3_0_EE_n_GSI_EE_GENERIC_CMD_PARAM_BMSK); +} + +static void gsireg_construct_cntxt_gsi_irq_en(enum gsihal_reg_name reg, + const void *fields, u32 *val) +{ + struct gsihal_reg_gsi_ee_n_cntxt_gsi_irq *irq = + (struct gsihal_reg_gsi_ee_n_cntxt_gsi_irq *)fields; + + GSI_SETFIELD_IN_REG(*val, !!irq->gsi_mcs_stack_ovrflow, + GSI_EE_n_CNTXT_GSI_IRQ_EN_GSI_MCS_STACK_OVRFLOW_SHFT, + GSI_EE_n_CNTXT_GSI_IRQ_EN_GSI_MCS_STACK_OVRFLOW_BMSK); + GSI_SETFIELD_IN_REG(*val, !!irq->gsi_cmd_fifo_ovrflow, + GSI_EE_n_CNTXT_GSI_IRQ_EN_GSI_CMD_FIFO_OVRFLOW_SHFT, + GSI_EE_n_CNTXT_GSI_IRQ_EN_GSI_CMD_FIFO_OVRFLOW_BMSK); + GSI_SETFIELD_IN_REG(*val, !!irq->gsi_bus_error, + GSI_EE_n_CNTXT_GSI_IRQ_EN_GSI_BUS_ERROR_SHFT, + GSI_EE_n_CNTXT_GSI_IRQ_EN_GSI_BUS_ERROR_BMSK); + GSI_SETFIELD_IN_REG(*val, !!irq->gsi_break_point, + GSI_EE_n_CNTXT_GSI_IRQ_EN_GSI_BREAK_POINT_SHFT, + GSI_EE_n_CNTXT_GSI_IRQ_EN_GSI_BREAK_POINT_BMSK); +} + +/* +* This table contains the info regarding each register for GSI1.0 and later. +* Information like: offset and construct/parse functions. +* All the information on the register on GSI are statically defined below. +* If information is missing regarding some register on some GSI version, +* the init function will fill it with the information from the previous +* GSI version. +* Information is considered missing if all of the fields are 0. +* If offset is -1, this means that the register is removed on the +* specific version. +*/ +static struct gsihal_reg_obj gsihal_reg_objs[GSI_VER_MAX][GSI_REG_MAX] = { + /* GSIv1_0 */ + [GSI_VER_1_0][GSI_EE_n_CNTXT_TYPE_IRQ_MSK] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0001f088, 0x4000, 0}, + [GSI_VER_1_0][GSI_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0001f098, 0x4000, 0}, + [GSI_VER_1_0][GSI_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0001f09c, 0x4000, 0}, + [GSI_VER_1_0][GSI_EE_n_CNTXT_SRC_IEOB_IRQ_MSK] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0001f0b8, 0x4000, 0}, + [GSI_VER_1_0][GSI_EE_n_CNTXT_GLOB_IRQ_EN] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0001f108, 0x4000, 0}, + [GSI_VER_1_0][GSI_EE_n_CNTXT_GSI_IRQ_EN] = { + gsireg_construct_cntxt_gsi_irq_en, gsireg_parse_dummy, + 0x0001f120, 0x4000, 0}, + [GSI_VER_1_0][GSI_EE_n_CNTXT_TYPE_IRQ] = { + gsireg_construct_dummy, gsireg_parse_ctx_type_irq, + 0x0001f080, 0x4000, 0}, + [GSI_VER_1_0][GSI_EE_n_CNTXT_SRC_GSI_CH_IRQ] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0001f090, 0x4000, 0}, + [GSI_VER_1_0][GSI_EE_n_GSI_CH_k_CNTXT_0] = { + gsireg_construct_ch_k_cntxt_0, gsireg_parse_ch_k_cntxt_0, + 0x0001c000, 0x4000, 0x80}, + [GSI_VER_1_0][GSI_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0001f0a0, 0x4000, 0}, + [GSI_VER_1_0][GSI_EE_n_CNTXT_SRC_EV_CH_IRQ] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0001f094, 0x4000, 0}, + [GSI_VER_1_0][GSI_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0001f0a4, 0x4000, 0}, + [GSI_VER_1_0][GSI_EE_n_EV_CH_k_CNTXT_0] = { + gsireg_construct_ev_ch_k_cntxt_0, gsireg_parse_ev_ch_k_cntxt_0, + 0x0001d000, 0x4000, 0x80}, + [GSI_VER_1_0][GSI_EE_n_CNTXT_GLOB_IRQ_STTS] = { + gsireg_construct_dummy, gsireg_parse_cntxt_glob_irq_stts, + 0x0001f100, 0x4000, 0}, + [GSI_VER_1_0][GSI_EE_n_ERROR_LOG] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0001f200, 0x4000, 0}, + [GSI_VER_1_0][GSI_EE_n_ERROR_LOG_CLR] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0001f210, 0x4000, 0}, + [GSI_VER_1_0][GSI_EE_n_CNTXT_GLOB_IRQ_CLR] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0001f110, 0x4000, 0}, + [GSI_VER_1_0][GSI_EE_n_EV_CH_k_DOORBELL_0] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0001e100, 0x4000, 0x8}, + [GSI_VER_1_0][GSI_EE_n_GSI_CH_k_DOORBELL_0] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0001e000, 0x4000, 0x8 }, + [GSI_VER_1_0][GSI_EE_n_CNTXT_SRC_IEOB_IRQ] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0001f0b0, 0x4000, 0}, + [GSI_VER_1_0][GSI_EE_n_CNTXT_SRC_IEOB_IRQ_CLR] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0001f0c0, 0x4000, 0}, + [GSI_VER_1_0][GSI_INTER_EE_n_SRC_GSI_CH_IRQ] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0000c018, 0x1000, 0}, + [GSI_VER_1_0][GSI_INTER_EE_n_SRC_GSI_CH_IRQ_CLR] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0000c028, 0x1000, 0}, + [GSI_VER_1_0][GSI_INTER_EE_n_SRC_EV_CH_IRQ] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0000c01c, 0x1000, 0}, + [GSI_VER_1_0][GSI_INTER_EE_n_SRC_EV_CH_IRQ_CLR] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0000c02c, 0x1000, 0}, + [GSI_VER_1_0][GSI_EE_n_CNTXT_GSI_IRQ_STTS] = { + gsireg_construct_dummy, gsireg_parse_cntxt_gsi_irq_stts, + 0x0001f118, 0x4000, 0}, + [GSI_VER_1_0][GSI_EE_n_CNTXT_GSI_IRQ_CLR] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0001f128, 0x4000, 0}, + [GSI_VER_1_0][GSI_EE_n_GSI_HW_PARAM] = { + gsireg_construct_dummy, gsireg_parse_hw_param, + 0x0001f040, 0x4000, 0}, + [GSI_VER_1_0][GSI_EE_n_GSI_SW_VERSION] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0001f044, 0x4000, 0}, + [GSI_VER_1_0][GSI_EE_n_CNTXT_INTSET] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0001f180, 0x4000, 0}, + [GSI_VER_1_0][GSI_EE_n_CNTXT_MSI_BASE_LSB] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0001f188, 0x4000, 0}, + [GSI_VER_1_0][GSI_EE_n_CNTXT_MSI_BASE_MSB] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0001f18c, 0x4000, 0}, + [GSI_VER_1_0][GSI_EE_n_GSI_STATUS] = { + gsireg_construct_dummy, gsireg_parse_gsi_status, + 0x0001f000, 0x4000, 0}, + [GSI_VER_1_0][GSI_EE_n_CNTXT_SCRATCH_0] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0001f400, 0x4000, 0}, + [GSI_VER_1_0][GSI_EE_n_EV_CH_k_CNTXT_1] = { + gsireg_construct_ev_ch_k_cntxt_1, gsireg_parse_dummy, + 0x0001d004, 0x4000, 0x80}, + [GSI_VER_1_0][GSI_EE_n_EV_CH_k_CNTXT_2] = { + gsireg_construct_ev_ch_k_cntxt_2, gsireg_parse_dummy, + 0x0001d008, 0x4000, 0x80}, + [GSI_VER_1_0][GSI_EE_n_EV_CH_k_CNTXT_3] = { + gsireg_construct_ev_ch_k_cntxt_3, gsireg_parse_dummy, + 0x0001d00c, 0x4000, 0x80}, + [GSI_VER_1_0][GSI_EE_n_EV_CH_k_CNTXT_8] = { + gsireg_construct_ev_ch_k_cntxt_8, gsireg_parse_dummy, + 0x0001d020, 0x4000, 0x80}, + [GSI_VER_1_0][GSI_EE_n_EV_CH_k_CNTXT_9] = { + gsireg_construct_ev_ch_k_cntxt_9, gsireg_parse_dummy, + 0x0001d024, 0x4000, 0x80}, + [GSI_VER_1_0][GSI_EE_n_EV_CH_k_CNTXT_10] = { + gsireg_construct_ev_ch_k_cntxt_10, gsireg_parse_dummy, + 0x0001d028, 0x4000, 0x80}, + [GSI_VER_1_0][GSI_EE_n_EV_CH_k_CNTXT_11] = { + gsireg_construct_ev_ch_k_cntxt_11, gsireg_parse_dummy, + 0x0001d02c, 0x4000, 0x80}, + [GSI_VER_1_0][GSI_EE_n_EV_CH_k_CNTXT_12] = { + gsireg_construct_ev_ch_k_cntxt_12, gsireg_parse_dummy, + 0x0001d030, 0x4000, 0x80}, + [GSI_VER_1_0][GSI_EE_n_EV_CH_k_CNTXT_13] = { + gsireg_construct_ev_ch_k_cntxt_13, gsireg_parse_dummy, + 0x0001d034, 0x4000, 0x80}, + [GSI_VER_1_0][GSI_EE_n_EV_CH_k_DOORBELL_1] = { + gsireg_construct_ev_ch_k_doorbell_1, gsireg_parse_dummy, + 0x0001e104, 0x4000, 0x8}, + [GSI_VER_1_0][GSI_EE_n_EV_CH_CMD] = { + gsireg_construct_ee_n_ev_ch_cmd, gsireg_parse_dummy, + 0x0001f010, 0x4000, 0}, + [GSI_VER_1_0][GSI_EE_n_EV_CH_k_SCRATCH_0] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0001d048, 0x4000, 0x80}, + [GSI_VER_1_0][GSI_EE_n_EV_CH_k_SCRATCH_1] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0001d04c, 0x4000, 0x80}, + [GSI_VER_1_0][GSI_EE_n_GSI_CH_k_DOORBELL_1] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0001e004, 0x4000, 0x8}, + [GSI_VER_1_0][GSI_EE_n_GSI_CH_k_QOS] = { + gsireg_construct_ee_n_gsi_ch_k_qos, gsireg_parse_dummy, + 0x0001c05c, 0x4000, 0x80}, + [GSI_VER_1_0][GSI_EE_n_GSI_CH_k_CNTXT_1] = { + gsireg_construct_ch_k_cntxt_1, gsireg_parse_dummy, + 0x0001c004, 0x4000, 0x80}, + [GSI_VER_1_0][GSI_EE_n_GSI_CH_k_CNTXT_2] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0001c008, 0x4000, 0x80}, + [GSI_VER_1_0][GSI_EE_n_GSI_CH_k_CNTXT_3] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0001c00c, 0x4000, 0x80}, + [GSI_VER_1_0][GSI_EE_n_GSI_CH_CMD] = { + gsireg_construct_ee_n_gsi_ch_cmd, gsireg_parse_dummy, + 0x0001f008, 0x4000, 0}, + [GSI_VER_1_0][GSI_EE_n_GSI_CH_k_SCRATCH_0] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0001c060, 0x4000, 0x80}, + [GSI_VER_1_0][GSI_EE_n_GSI_CH_k_SCRATCH_1] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0001c064, 0x4000, 0x80}, + [GSI_VER_1_0][GSI_EE_n_GSI_CH_k_SCRATCH_2] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0001c068, 0x4000, 0x80}, + [GSI_VER_1_0][GSI_EE_n_GSI_CH_k_SCRATCH_3] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0001c06c, 0x4000, 0x80}, + [GSI_VER_1_0][GSI_EE_n_GSI_CH_k_CNTXT_4] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0001c010, 0x4000, 0x80}, + [GSI_VER_1_0][GSI_EE_n_GSI_CH_k_CNTXT_5] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0001c014, 0x4000, 0x80}, + [GSI_VER_1_0][GSI_EE_n_GSI_CH_k_CNTXT_6] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0001c018, 0x4000, 0x80}, + [GSI_VER_1_0][GSI_EE_n_GSI_CH_k_CNTXT_7] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0001c01c, 0x4000, 0x80}, + [GSI_VER_1_0][GSI_EE_n_EV_CH_k_CNTXT_4] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0001d010, 0x4000, 0x80}, + [GSI_VER_1_0][GSI_EE_n_EV_CH_k_CNTXT_5] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0001d014, 0x4000, 0x80}, + [GSI_VER_1_0][GSI_EE_n_EV_CH_k_CNTXT_6] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0001d018, 0x4000, 0x80}, + [GSI_VER_1_0][GSI_EE_n_EV_CH_k_CNTXT_7] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0001d01c, 0x4000, 0x80}, + [GSI_VER_1_0][GSI_GSI_IRAM_PTR_CH_CMD] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00000400, 0, 0}, + [GSI_VER_1_0][GSI_GSI_IRAM_PTR_CH_DB] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00000418, 0, 0}, + [GSI_VER_1_0][GSI_GSI_IRAM_PTR_CH_DIS_COMP] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00000424, 0, 0}, + [GSI_VER_1_0][GSI_GSI_IRAM_PTR_CH_EMPTY] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00000428, 0, 0}, + [GSI_VER_1_0][GSI_GSI_IRAM_PTR_EE_GENERIC_CMD] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00000404, 0, 0}, + [GSI_VER_1_0][GSI_GSI_IRAM_PTR_EVENT_GEN_COMP] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0000042c, 0, 0}, + [GSI_VER_1_0][GSI_GSI_IRAM_PTR_INT_MOD_STOPPED] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0000044c, 0, 0}, + [GSI_VER_1_0][GSI_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00000430, 0, 0}, + [GSI_VER_1_0][GSI_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00000434, 0, 0}, + [GSI_VER_1_0][GSI_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00000438, 0, 0}, + [GSI_VER_1_0][GSI_GSI_IRAM_PTR_NEW_RE] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00000420, 0, 0}, + [GSI_VER_1_0][GSI_GSI_IRAM_PTR_READ_ENG_COMP] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00000444, 0, 0}, + [GSI_VER_1_0][GSI_GSI_IRAM_PTR_TIMER_EXPIRED] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0000043c, 0, 0}, + [GSI_VER_1_0][GSI_GSI_IRAM_PTR_EV_DB] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0000041c, 0, 0}, + [GSI_VER_1_0][GSI_GSI_IRAM_PTR_UC_GP_INT] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00000448, 0, 0}, + [GSI_VER_1_0][GSI_GSI_IRAM_PTR_WRITE_ENG_COMP] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00000440, 0, 0}, + [GSI_VER_1_0][GSI_IC_DISABLE_CHNL_BCK_PRS_LSB] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x000000a0, 0, 0}, + [GSI_VER_1_0][GSI_IC_DISABLE_CHNL_BCK_PRS_MSB] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x000000a4, 0, 0}, + [GSI_VER_1_0][GSI_IC_GEN_EVNT_BCK_PRS_LSB] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x000000a8, 0, 0}, + [GSI_VER_1_0][GSI_IC_GEN_EVNT_BCK_PRS_MSB] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x000000ac, 0, 0}, + [GSI_VER_1_0][GSI_IC_GEN_INT_BCK_PRS_LSB] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x000000b0, 0, 0}, + [GSI_VER_1_0][GSI_IC_GEN_INT_BCK_PRS_MSB] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x000000b4, 0, 0}, + [GSI_VER_1_0][GSI_IC_STOP_INT_MOD_BCK_PRS_LSB] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x000000b8, 0, 0 }, + [GSI_VER_1_0][GSI_IC_STOP_INT_MOD_BCK_PRS_MSB] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x000000bc, 0, 0}, + [GSI_VER_1_0][GSI_IC_PROCESS_DESC_BCK_PRS_LSB] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x000000c0, 0, 0}, + [GSI_VER_1_0][GSI_IC_PROCESS_DESC_BCK_PRS_MSB] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x000000c4, 0, 0}, + [GSI_VER_1_0][GSI_IC_TLV_STOP_BCK_PRS_LSB] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x000000c8, 0, 0}, + [GSI_VER_1_0][GSI_IC_TLV_STOP_BCK_PRS_MSB] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x000000cc, 0, 0}, + [GSI_VER_1_0][GSI_IC_TLV_RESET_BCK_PRS_LSB] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x000000d0, 0, 0}, + [GSI_VER_1_0][GSI_IC_TLV_RESET_BCK_PRS_MSB] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x000000d4, 0, 0}, + [GSI_VER_1_0][GSI_IC_RGSTR_TIMER_BCK_PRS_LSB] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x000000d8, 0, 0}, + [GSI_VER_1_0][GSI_IC_RGSTR_TIMER_BCK_PRS_MSB] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x000000dc, 0, 0}, + [GSI_VER_1_0][GSI_IC_READ_BCK_PRS_LSB] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x000000e0, 0, 0}, + [GSI_VER_1_0][GSI_IC_READ_BCK_PRS_MSB] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x000000e4, 0, 0}, + [GSI_VER_1_0][GSI_IC_WRITE_BCK_PRS_LSB] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x000000e8, 0, 0}, + [GSI_VER_1_0][GSI_IC_WRITE_BCK_PRS_MSB] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x000000ec, 0, 0}, + [GSI_VER_1_0][GSI_IC_UCONTROLLER_GPR_BCK_PRS_LSB] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x000000f0, 0, 0}, + [GSI_VER_1_0][GSI_IC_UCONTROLLER_GPR_BCK_PRS_MSB] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x000000f4, 0, 0}, + [GSI_VER_1_0][GSI_GSI_PERIPH_BASE_ADDR_MSB] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0000001c, 0, 0}, + [GSI_VER_1_0][GSI_GSI_PERIPH_BASE_ADDR_LSB] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00000018, 0, 0}, + [GSI_VER_1_0][GSI_GSI_CFG] = { + gsireg_construct_gsi_cfg, gsireg_parse_dummy, + 0x00000000, 0, 0}, + [GSI_VER_1_0][GSI_EE_n_GSI_EE_GENERIC_CMD] = { + gsireg_construct_gsi_ee_generic_cmd, gsireg_parse_dummy, + 0x0001f018, 0x4000, 0}, + [GSI_VER_1_0][GSI_EE_n_GSI_CH_k_RE_FETCH_READ_PTR] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0001c054, 0x4000, 0x80}, + [GSI_VER_1_0][GSI_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0001c058, 0x4000, 0x80}, + [GSI_VER_1_0][GSI_GSI_INST_RAM_n] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00004000, GSI_GSI_INST_RAM_n_WORD_SZ, 0}, + [GSI_VER_1_0][GSI_EE_n_GSI_DEBUG_BUSY_REG] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00001010, 0, 0}, + [GSI_VER_1_0][GSI_EE_n_GSI_DEBUG_PC_FOR_DEBUG] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00001048, 0, 0}, + + /* GSIv1_2 */ + [GSI_VER_1_2][GSI_EE_n_GSI_HW_PARAM] = { + gsireg_construct_dummy, gsireg_parse_dummy, + -1, 0, 0}, + [GSI_VER_1_2][GSI_EE_n_GSI_HW_PARAM_0] = { + gsireg_construct_dummy, gsireg_parse_hw_param0, + 0x0001f038, 0x4000, 0}, + [GSI_VER_1_2][GSI_EE_n_GSI_CH_k_QOS] = { + gsireg_construct_ee_n_gsi_ch_k_qos_v1_2, gsireg_parse_dummy, + 0x0001c05c, 0x4000, 0x80}, + [GSI_VER_1_2][GSI_GSI_MCS_CFG] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0000B000, 0, 0}, + + /* GSIv1_3 */ + [GSI_VER_1_3][GSI_EE_n_GSI_HW_PARAM_2] = { + gsireg_construct_dummy, gsireg_parse_hw_param2, + 0x0001f040, 0x4000, 0}, + + /* GSIv2_0 */ + [GSI_VER_2_0][GSI_EE_n_GSI_HW_PARAM_2] = { + gsireg_construct_dummy, gsireg_parse_hw_param2_v2_0, + 0x0001f040, 0x4000, 0}, + + /* GSIv2_2 */ + [GSI_VER_2_2][GSI_EE_n_GSI_HW_PARAM_2] = { + gsireg_construct_dummy, gsireg_parse_hw_param2_v2_2, + 0x0001f040, 0x4000, 0 }, + + /* GSIv2_5 */ + [GSI_VER_2_5][GSI_EE_n_CNTXT_TYPE_IRQ_MSK] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00012088, 0x4000, 0}, + [GSI_VER_2_5][GSI_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00012098, 0x4000, 0}, + [GSI_VER_2_5][GSI_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0001209c, 0x4000, 0}, + [GSI_VER_2_5][GSI_EE_n_CNTXT_SRC_IEOB_IRQ_MSK] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x000120b8, 0x4000, 0}, + [GSI_VER_2_5][GSI_EE_n_CNTXT_GLOB_IRQ_EN] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00012108, 0x4000, 0}, + [GSI_VER_2_5][GSI_EE_n_CNTXT_GSI_IRQ_EN] = { + gsireg_construct_cntxt_gsi_irq_en, gsireg_parse_dummy, + 0x00012120, 0x4000, 0}, + [GSI_VER_2_5][GSI_EE_n_CNTXT_TYPE_IRQ] = { + gsireg_construct_dummy, gsireg_parse_ctx_type_irq, + 0x00012080, 0x4000, 0}, + [GSI_VER_2_5][GSI_EE_n_CNTXT_SRC_GSI_CH_IRQ] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00012090, 0x4000, 0}, + [GSI_VER_2_5][GSI_EE_n_GSI_CH_k_CNTXT_0] = { + gsireg_construct_ch_k_cntxt_0_v2_5, gsireg_parse_ch_k_cntxt_0_v2_5, + 0x0000f000, 0x4000, 0x80}, + [GSI_VER_2_5][GSI_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x000120a0, 0x4000, 0}, + [GSI_VER_2_5][GSI_EE_n_CNTXT_SRC_EV_CH_IRQ] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00012094, 0x4000, 0}, + [GSI_VER_2_5][GSI_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x000120a4, 0x4000, 0}, + [GSI_VER_2_5][GSI_EE_n_EV_CH_k_CNTXT_0] = { + gsireg_construct_ev_ch_k_cntxt_0, gsireg_parse_ev_ch_k_cntxt_0, + 0x00010000, 0x4000, 0x80}, + [GSI_VER_2_5][GSI_EE_n_CNTXT_GLOB_IRQ_STTS] = { + gsireg_construct_dummy, gsireg_parse_cntxt_glob_irq_stts, + 0x00012100, 0x4000, 0}, + [GSI_VER_2_5][GSI_EE_n_ERROR_LOG] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00012200, 0x4000, 0}, + [GSI_VER_2_5][GSI_EE_n_ERROR_LOG_CLR] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00012210, 0x4000, 0}, + [GSI_VER_2_5][GSI_EE_n_CNTXT_GLOB_IRQ_CLR] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00012110, 0x4000, 0}, + [GSI_VER_2_5][GSI_EE_n_EV_CH_k_DOORBELL_0] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00011100, 0x4000, 0x8}, + [GSI_VER_2_5][GSI_EE_n_GSI_CH_k_DOORBELL_0] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00011000, 0x4000, 0x8}, + [GSI_VER_2_5][GSI_EE_n_CNTXT_SRC_IEOB_IRQ] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x000120b0, 0x4000, 0}, + [GSI_VER_2_5][GSI_EE_n_CNTXT_SRC_IEOB_IRQ_CLR] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x000120c0, 0x4000, 0}, + [GSI_VER_2_5][GSI_EE_n_CNTXT_GSI_IRQ_STTS] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00012118, 0x4000, 0}, + [GSI_VER_2_5][GSI_EE_n_CNTXT_GSI_IRQ_CLR] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00012128, 0x4000, 0}, + [GSI_VER_2_5][GSI_EE_n_GSI_HW_PARAM_2] = { + gsireg_construct_dummy, gsireg_parse_hw_param2_v2_2, + 0x00012040, 0x4000, 0}, + [GSI_VER_2_5][GSI_EE_n_GSI_SW_VERSION] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00012044, 0x4000, 0 }, + [GSI_VER_2_5][GSI_EE_n_CNTXT_INTSET] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00012180, 0x4000, 0}, + [GSI_VER_2_5][GSI_EE_n_CNTXT_MSI_BASE_LSB] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00012188, 0x4000, 0}, + [GSI_VER_2_5][GSI_EE_n_CNTXT_MSI_BASE_MSB] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0001218c, 0x4000, 0}, + [GSI_VER_2_5][GSI_EE_n_GSI_STATUS] = { + gsireg_construct_dummy, gsireg_parse_gsi_status, + 0x00012000, 0x4000, 0}, + [GSI_VER_2_5][GSI_EE_n_CNTXT_SCRATCH_0] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00012400, 0x4000, 0}, + [GSI_VER_2_5][GSI_EE_n_EV_CH_k_CNTXT_1] = { + gsireg_construct_ev_ch_k_cntxt_1, gsireg_parse_dummy, + 0x00010004, 0x4000, 0x80}, + [GSI_VER_2_5][GSI_EE_n_EV_CH_k_CNTXT_2] = { + gsireg_construct_ev_ch_k_cntxt_2, gsireg_parse_dummy, + 0x00010008, 0x4000, 0x80 }, + [GSI_VER_2_5][GSI_EE_n_EV_CH_k_CNTXT_3] = { + gsireg_construct_ev_ch_k_cntxt_3, gsireg_parse_dummy, + 0x0001000c, 0x4000, 0x80 }, + [GSI_VER_2_5][GSI_EE_n_EV_CH_k_CNTXT_8] = { + gsireg_construct_ev_ch_k_cntxt_8, gsireg_parse_dummy, + 0x00010020, 0x4000, 0x80 }, + [GSI_VER_2_5][GSI_EE_n_EV_CH_k_CNTXT_9] = { + gsireg_construct_ev_ch_k_cntxt_9, gsireg_parse_dummy, + 0x00010024, 0x4000, 0x80 }, + [GSI_VER_2_5][GSI_EE_n_EV_CH_k_CNTXT_10] = { + gsireg_construct_ev_ch_k_cntxt_10, gsireg_parse_dummy, + 0x00010028, 0x4000, 0x80 }, + [GSI_VER_2_5][GSI_EE_n_EV_CH_k_CNTXT_11] = { + gsireg_construct_ev_ch_k_cntxt_11, gsireg_parse_dummy, + 0x0001002c, 0x4000, 0x80 }, + [GSI_VER_2_5][GSI_EE_n_EV_CH_k_CNTXT_12] = { + gsireg_construct_ev_ch_k_cntxt_12, gsireg_parse_dummy, + 0x00010030, 0x4000, 0x80 }, + [GSI_VER_2_5][GSI_EE_n_EV_CH_k_CNTXT_13] = { + gsireg_construct_ev_ch_k_cntxt_13, gsireg_parse_dummy, + 0x00010034, 0x4000, 0x80 }, + [GSI_VER_2_5][GSI_EE_n_EV_CH_k_DOORBELL_1] = { + gsireg_construct_ev_ch_k_doorbell_1, gsireg_parse_dummy, + 0x00011104, 0x4000, 0x8}, + [GSI_VER_2_5][GSI_EE_n_EV_CH_CMD] = { + gsireg_construct_ee_n_ev_ch_cmd, gsireg_parse_dummy, + 0x00012010, 0x4000, 0}, + [GSI_VER_2_5][GSI_EE_n_EV_CH_k_SCRATCH_0] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00010048, 0x4000, 0x80}, + [GSI_VER_2_5][GSI_EE_n_EV_CH_k_SCRATCH_1] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0001004c, 0x4000, 0x80}, + [GSI_VER_2_5][GSI_EE_n_GSI_CH_k_DOORBELL_1] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00011004, 0x4000, 0x8}, + [GSI_VER_2_5][GSI_EE_n_GSI_CH_k_QOS] = { + gsireg_construct_ee_n_gsi_ch_k_qos_v2_5, gsireg_parse_dummy, + 0x0000f05c, 0x4000, 0x80}, + [GSI_VER_2_5][GSI_EE_n_GSI_CH_k_CNTXT_1] = { + gsireg_construct_ch_k_cntxt_1, gsireg_parse_dummy, + 0x0000f004, 0x4000, 0x80}, + [GSI_VER_2_5][GSI_EE_n_GSI_CH_k_CNTXT_2] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0000f008, 0x4000, 0x80}, + [GSI_VER_2_5][GSI_EE_n_GSI_CH_k_CNTXT_3] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0000f00c, 0x4000, 0x80}, + [GSI_VER_2_5][GSI_EE_n_GSI_CH_CMD] = { + gsireg_construct_ee_n_gsi_ch_cmd, gsireg_parse_dummy, + 0x00012008, 0x4000, 0}, + [GSI_VER_2_5][GSI_EE_n_GSI_CH_k_SCRATCH_0] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0000f060, 0x4000, 0x80}, + [GSI_VER_2_5][GSI_EE_n_GSI_CH_k_SCRATCH_1] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0000f064, 0x4000, 0x80}, + [GSI_VER_2_5][GSI_EE_n_GSI_CH_k_SCRATCH_2] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0000f068, 0x4000, 0x80}, + [GSI_VER_2_5][GSI_EE_n_GSI_CH_k_SCRATCH_3] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0000f06c, 0x4000, 0x80}, + [GSI_VER_2_5][GSI_EE_n_GSI_CH_k_CNTXT_4] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0000f010, 0x4000, 0x80}, + [GSI_VER_2_5][GSI_EE_n_GSI_CH_k_CNTXT_5] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0000f014, 0x4000, 0x80}, + [GSI_VER_2_5][GSI_EE_n_GSI_CH_k_CNTXT_6] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0000f018, 0x4000, 0x80}, + [GSI_VER_2_5][GSI_EE_n_GSI_CH_k_CNTXT_7] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0000f01c, 0x4000, 0x80}, + [GSI_VER_2_5][GSI_EE_n_EV_CH_k_CNTXT_4] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00010010, 0x4000, 0x80}, + [GSI_VER_2_5][GSI_EE_n_EV_CH_k_CNTXT_5] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00010014, 0x4000, 0x80}, + [GSI_VER_2_5][GSI_EE_n_EV_CH_k_CNTXT_6] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00010018, 0x4000, 0x80}, + [GSI_VER_2_5][GSI_EE_n_EV_CH_k_CNTXT_7] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0001001c, 0x4000, 0x80}, + [GSI_VER_2_5][GSI_GSI_IRAM_PTR_TLV_CH_NOT_FULL] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00000408, 0, 0}, + [GSI_VER_2_5][GSI_GSI_CFG] = { + gsireg_construct_gsi_cfg_v2_5, gsireg_parse_dummy, + 0x00000000, 0, 0}, + [GSI_VER_2_5][GSI_EE_n_GSI_EE_GENERIC_CMD] = { + gsireg_construct_gsi_ee_generic_cmd, gsireg_parse_dummy, + 0x00012018, 0x4000, 0}, + [GSI_VER_2_5][GSI_MAP_EE_n_CH_k_VP_TABLE] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00003800, 0x80, 0x4 }, + [GSI_VER_2_5][GSI_GSI_INST_RAM_n] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0001b000, GSI_GSI_INST_RAM_n_WORD_SZ, 0}, + [GSI_VER_2_5][GSI_GSI_SHRAM_n] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00002000, GSI_GSI_SHRAM_n_WORD_SZ, 0 }, + + /* GSIv2_9 */ + [GSI_VER_2_9][GSI_EE_n_EV_CH_k_CNTXT_1] = { + gsireg_construct_ev_ch_k_cntxt_1_v2_9, gsireg_parse_dummy, + 0x00010004, 0x4000, 0x80}, + [GSI_VER_2_9][GSI_EE_n_GSI_CH_k_QOS] = { + gsireg_construct_ee_n_gsi_ch_k_qos_v2_9, gsireg_parse_dummy, + 0x0000f05c, 0x4000, 0x80}, + [GSI_VER_2_9][GSI_EE_n_GSI_CH_k_CNTXT_1] = { + gsireg_construct_ch_k_cntxt_1_v2_9, gsireg_parse_dummy, + 0x0000f004, 0x4000, 0x80}, + [GSI_VER_2_9][GSI_GSI_MCS_PROFILING_BP_CNT_LSB] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0000185c, 0, 0 }, + [GSI_VER_2_9][GSI_GSI_MCS_PROFILING_BP_CNT_MSB] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00001860, 0, 0 }, + [GSI_VER_2_9][GSI_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00001864, 0, 0 }, + [GSI_VER_2_9][GSI_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00001868, 0, 0 }, + [GSI_VER_2_9][GSI_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0000186c, 0, 0 }, + [GSI_VER_2_9][GSI_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00001870, 0, 0 }, + [GSI_VER_2_9][GSI_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00001874, 0, 0 }, + [GSI_VER_2_9][GSI_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00001878, 0, 0 }, + [GSI_VER_2_9][GSI_EE_n_GSI_CH_k_SCRATCH_4] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0000f040, 0x4000, 0x80 }, + + /* GSIv2_11 */ + [GSI_VER_2_11][GSI_GSI_IRAM_PTR_MSI_DB] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00000414, 0, 0 }, + + /* GSIv3_0 */ + [GSI_VER_3_0][GSI_GSI_IRAM_PTR_INT_NOTIFY_MCS] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00000470, 0, 0 }, + [GSI_VER_3_0][GSI_GSI_INST_RAM_n] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x000a4000, GSI_GSI_INST_RAM_n_WORD_SZ, 0}, + [GSI_VER_3_0][GSI_EE_n_GSI_CH_k_CNTXT_0] = { + gsireg_construct_ch_k_cntxt_0_v3_0, gsireg_parse_ch_k_cntxt_0_v3_0, + 0x00014000, 0x12000, 0x80 }, + [GSI_VER_3_0][GSI_EE_n_GSI_CH_k_CNTXT_1] = { + gsireg_construct_ch_k_cntxt_1_v3_0, gsireg_parse_ch_k_cntxt_1_v3_0, + 0x00014004, 0x12000, 0x80 }, + [GSI_VER_3_0][GSI_EE_n_GSI_CH_k_CNTXT_2] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00014008, 0x12000, 0x80 }, + [GSI_VER_3_0][GSI_EE_n_GSI_CH_k_CNTXT_3] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0001400c, 0x12000, 0x80 }, + [GSI_VER_3_0][GSI_EE_n_GSI_CH_k_CNTXT_4] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00014010, 0x12000, 0x80 }, + [GSI_VER_3_0][GSI_EE_n_GSI_CH_k_CNTXT_5] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00014014, 0x12000, 0x80 }, + [GSI_VER_3_0][GSI_EE_n_GSI_CH_k_CNTXT_6] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00014018, 0x12000, 0x80 }, + [GSI_VER_3_0][GSI_EE_n_GSI_CH_k_CNTXT_7] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0001401c, 0x12000, 0x80 }, + [GSI_VER_3_0][GSI_EE_n_GSI_CH_k_CNTXT_8] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00014020, 0x12000, 0x80 }, + [GSI_VER_3_0][GSI_EE_n_CH_k_CH_ALMST_EMPTY_THRSHOLD] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00014028, 0x12000, 0x80 }, + [GSI_VER_3_0][GSI_EE_n_GSI_CH_k_RE_FETCH_READ_PTR] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00014040, 0x12000, 0x80 }, + [GSI_VER_3_0][GSI_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00014044, 0x12000, 0x80 }, + [GSI_VER_3_0][GSI_EE_n_GSI_CH_k_QOS] = { + gsireg_construct_ee_n_gsi_ch_k_qos_v3_0, gsireg_parse_dummy, + 0x00014048, 0x12000, 0x80 }, + [GSI_VER_3_0][GSI_EE_n_GSI_CH_k_SCRATCH_0] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0001404c, 0x12000, 0x80 }, + [GSI_VER_3_0][GSI_EE_n_GSI_CH_k_SCRATCH_1] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00014050, 0x12000, 0x80 }, + [GSI_VER_3_0][GSI_EE_n_GSI_CH_k_SCRATCH_2] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00014054, 0x12000, 0x80 }, + [GSI_VER_3_0][GSI_EE_n_GSI_CH_k_SCRATCH_3] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00014058, 0x12000, 0x80 }, + [GSI_VER_3_0][GSI_EE_n_GSI_CH_k_SCRATCH_4] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0001405c, 0x12000, 0x80 }, + [GSI_VER_3_0][GSI_EE_n_GSI_CH_k_SCRATCH_5] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00014060, 0x12000, 0x80 }, + [GSI_VER_3_0][GSI_EE_n_GSI_CH_k_SCRATCH_6] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00014064, 0x12000, 0x80 }, + [GSI_VER_3_0][GSI_EE_n_GSI_CH_k_SCRATCH_7] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00014068, 0x12000, 0x80 }, + [GSI_VER_3_0][GSI_EE_n_GSI_CH_k_SCRATCH_8] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0001406c, 0x12000, 0x80 }, + [GSI_VER_3_0][GSI_EE_n_GSI_CH_k_SCRATCH_9] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00014070, 0x12000, 0x80 }, + [GSI_VER_3_0][GSI_EE_n_EV_CH_k_CNTXT_0] = { + gsireg_construct_ev_ch_k_cntxt_0_v3_0, gsireg_parse_ev_ch_k_cntxt_0_v3_0, + 0x0001c000, 0x12000, 0x80 }, + [GSI_VER_3_0][GSI_EE_n_EV_CH_k_CNTXT_1] = { + gsireg_construct_ev_ch_k_cntxt_1_v3_0, gsireg_parse_dummy, + 0x0001c004, 0x12000, 0x80 }, + [GSI_VER_3_0][GSI_EE_n_EV_CH_k_CNTXT_2] = { + gsireg_construct_ev_ch_k_cntxt_2, gsireg_parse_dummy, + 0x0001c008, 0x12000, 0x80 }, + [GSI_VER_3_0][GSI_EE_n_EV_CH_k_CNTXT_3] = { + gsireg_construct_ev_ch_k_cntxt_3, gsireg_parse_dummy, + 0x0001c00c, 0x12000, 0x80 }, + [GSI_VER_3_0][GSI_EE_n_EV_CH_k_CNTXT_4] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0001c010, 0x12000, 0x80 }, + [GSI_VER_3_0][GSI_EE_n_EV_CH_k_CNTXT_5] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0001c014, 0x12000, 0x80 }, + [GSI_VER_3_0][GSI_EE_n_EV_CH_k_CNTXT_6] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0001c018, 0x12000, 0x80 }, + [GSI_VER_3_0][GSI_EE_n_EV_CH_k_CNTXT_7] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0001c01c, 0x12000, 0x80 }, + [GSI_VER_3_0][GSI_EE_n_EV_CH_k_CNTXT_8] = { + gsireg_construct_ev_ch_k_cntxt_8, gsireg_parse_dummy, + 0x0001c020, 0x12000, 0x80 }, + [GSI_VER_3_0][GSI_EE_n_EV_CH_k_CNTXT_9] = { + gsireg_construct_ev_ch_k_cntxt_9, gsireg_parse_dummy, + 0x0001c024, 0x12000, 0x80 }, + [GSI_VER_3_0][GSI_EE_n_EV_CH_k_CNTXT_10] = { + gsireg_construct_ev_ch_k_cntxt_10, gsireg_parse_dummy, + 0x0001c028, 0x12000, 0x80 }, + [GSI_VER_3_0][GSI_EE_n_EV_CH_k_CNTXT_11] = { + gsireg_construct_ev_ch_k_cntxt_11, gsireg_parse_dummy, + 0x0001c02c, 0x12000, 0x80 }, + [GSI_VER_3_0][GSI_EE_n_EV_CH_k_CNTXT_12] = { + gsireg_construct_ev_ch_k_cntxt_12, gsireg_parse_dummy, + 0x0001c030, 0x12000, 0x80 }, + [GSI_VER_3_0][GSI_EE_n_EV_CH_k_CNTXT_13] = { + gsireg_construct_ev_ch_k_cntxt_13, gsireg_parse_dummy, + 0x0001c034, 0x12000, 0x80 }, + [GSI_VER_3_0][GSI_EE_n_EV_CH_k_SCRATCH_0] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0001c048, 0x12000, 0x80 }, + [GSI_VER_3_0][GSI_EE_n_EV_CH_k_SCRATCH_1] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0001c04c, 0x12000, 0x80 }, + [GSI_VER_3_0][GSI_EE_n_GSI_CH_k_DOORBELL_0] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00024000, 0x12000, 0x8 }, + [GSI_VER_3_0][GSI_EE_n_GSI_CH_k_DOORBELL_1] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00024004, 0x12000, 0x8 }, + [GSI_VER_3_0][GSI_EE_n_EV_CH_k_DOORBELL_0] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00024800, 0x12000, 0x8 }, + [GSI_VER_3_0][GSI_EE_n_EV_CH_k_DOORBELL_1] = { + gsireg_construct_ev_ch_k_doorbell_1, gsireg_parse_dummy, + 0x00024804, 0x12000, 0x8 }, + [GSI_VER_3_0][GSI_EE_n_GSI_STATUS] = { + gsireg_construct_dummy, gsireg_parse_gsi_status, + 0x00025000, 0x12000, 0 }, + [GSI_VER_3_0][GSI_EE_n_GSI_CH_CMD] = { + gsireg_construct_ee_n_gsi_ch_cmd, gsireg_parse_dummy, + 0x00025008, 0x12000, 0 }, + [GSI_VER_3_0][GSI_EE_n_EV_CH_CMD] = { + gsireg_construct_ee_n_ev_ch_cmd, gsireg_parse_dummy, + 0x00025010, 0x12000, 0 }, + [GSI_VER_3_0][GSI_EE_n_GSI_EE_GENERIC_CMD] = { + gsireg_construct_gsi_ee_generic_cmd_v3_0, gsireg_parse_dummy, + 0x00025018, 0x12000, 0 }, + [GSI_VER_3_0][GSI_EE_n_GSI_HW_PARAM_2] = { + gsireg_construct_dummy, gsireg_parse_hw_param2_v3_0, + 0x00025040, 0x12000, 0 }, + [GSI_VER_3_0][GSI_EE_n_GSI_HW_PARAM_4] = { + gsireg_construct_dummy, gsireg_parse_hw_param4_v3_0, + 0x00025050, 0x12000, 0 }, + [GSI_VER_3_0][GSI_EE_n_GSI_SW_VERSION] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00025044, 0x12000, 0 }, + [GSI_VER_3_0][GSI_EE_n_CNTXT_TYPE_IRQ] = { + gsireg_construct_dummy, gsireg_parse_ctx_type_irq, + 0x00025080, 0x12000, 0 }, + [GSI_VER_3_0][GSI_EE_n_CNTXT_TYPE_IRQ_MSK] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00025088, 0x12000, 0 }, + [GSI_VER_3_0][GSI_EE_n_CNTXT_SRC_GSI_CH_IRQ_k] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00025090, 0x12000, 0x24 }, + [GSI_VER_3_0][GSI_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00025094, 0x12000, 0x24 }, + [GSI_VER_3_0][GSI_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_k] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00025098, 0x12000, 0x24 }, + [GSI_VER_3_0][GSI_EE_n_CNTXT_SRC_EV_CH_IRQ_k] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0002509c, 0x12000, 0x24 }, + [GSI_VER_3_0][GSI_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x000250a0, 0x12000, 0x24 }, + [GSI_VER_3_0][GSI_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_k] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x000250a4, 0x12000, 0x24 }, + [GSI_VER_3_0][GSI_EE_n_CNTXT_SRC_IEOB_IRQ_k] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x000250a8, 0x12000, 0x24 }, + [GSI_VER_3_0][GSI_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x000250ac, 0x12000, 0x24 }, + [GSI_VER_3_0][GSI_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_k] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x000250b0, 0x12000, 0x24 }, + [GSI_VER_3_0][GSI_EE_n_CNTXT_GLOB_IRQ_STTS] = { + gsireg_construct_dummy, gsireg_parse_cntxt_glob_irq_stts, + 0x00025200, 0x12000, 0 }, + [GSI_VER_3_0][GSI_EE_n_CNTXT_GLOB_IRQ_EN] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00025204, 0x12000, 0 }, + [GSI_VER_3_0][GSI_EE_n_CNTXT_GLOB_IRQ_CLR] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00025208, 0x12000, 0 }, + [GSI_VER_3_0][GSI_EE_n_CNTXT_GSI_IRQ_STTS] = { + gsireg_construct_dummy, gsireg_parse_cntxt_gsi_irq_stts, + 0x0002520c, 0x12000, 0 }, + [GSI_VER_3_0][GSI_EE_n_CNTXT_GSI_IRQ_EN] = { + gsireg_construct_cntxt_gsi_irq_en, gsireg_parse_dummy, + 0x00025210, 0x12000, 0 }, + [GSI_VER_3_0][GSI_EE_n_CNTXT_GSI_IRQ_CLR] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00025214, 0x12000, 0 }, + [GSI_VER_3_0][GSI_EE_n_CNTXT_MSI_BASE_LSB] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00025230, 0x12000, 0 }, + [GSI_VER_3_0][GSI_EE_n_CNTXT_MSI_BASE_MSB] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00025234, 0x12000, 0 }, + [GSI_VER_3_0][GSI_EE_n_CNTXT_INTSET] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00025220, 0x12000, 0 }, + [GSI_VER_3_0][GSI_EE_n_ERROR_LOG] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00025240, 0x12000, 0 }, + [GSI_VER_3_0][GSI_EE_n_ERROR_LOG_CLR] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00025244, 0x12000, 0 }, + [GSI_VER_3_0][GSI_EE_n_CNTXT_SCRATCH_0] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00025400, 0x12000, 0}, + [GSI_VER_3_0][GSI_INTER_EE_n_SRC_GSI_CH_IRQ_k] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0000c018, 0x1000, 0x18 }, + [GSI_VER_3_0][GSI_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_k] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0000c020, 0x1000, 0x18 }, + [GSI_VER_3_0][GSI_INTER_EE_n_SRC_EV_CH_IRQ_k] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0000c024, 0x1000, 0x18 }, + [GSI_VER_3_0][GSI_INTER_EE_n_SRC_EV_CH_IRQ_CLR_k] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x0000c02c, 0x1000, 0x18 }, + [GSI_VER_3_0][GSI_MAP_EE_n_CH_k_VP_TABLE] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00009000, 0x400, 0x4 }, + [GSI_VER_3_0][GSI_GSI_MCS_PROFILING_BP_CNT_LSB] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00001a5c, 0, 0 }, + [GSI_VER_3_0][GSI_GSI_MCS_PROFILING_BP_CNT_MSB] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00001a60, 0, 0 }, + [GSI_VER_3_0][GSI_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00001a64, 0, 0 }, + [GSI_VER_3_0][GSI_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00001a68, 0, 0 }, + [GSI_VER_3_0][GSI_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00001a6c, 0, 0 }, + [GSI_VER_3_0][GSI_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00001a70, 0, 0 }, + [GSI_VER_3_0][GSI_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00001a74, 0, 0 }, + [GSI_VER_3_0][GSI_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB] = { + gsireg_construct_dummy, gsireg_parse_dummy, + 0x00001a78, 0, 0 }, +}; + +/* + * gsihal_read_reg_nk() - Get nk parameterized reg value + */ +u32 gsihal_read_reg_nk(enum gsihal_reg_name reg, u32 n, u32 k) +{ + u32 offset; + + if (!gsihal_ctx) { + GSIERR("gsihal_ctx mpt initialized"); + return -EPERM; + } + + if (reg >= GSI_REG_MAX) { + GSIERR("Invalid register reg=%u\n", reg); + WARN_ON(1); + return -EINVAL; + } + + GSIDBG_LOW("read %s k=%u n=%u\n", + gsihal_reg_name_str(reg), k, n); + offset = gsihal_reg_objs[gsihal_ctx->gsi_ver][reg].offset; + if (offset == -1) { + GSIERR("Read access to obsolete reg=%s\n", + gsihal_reg_name_str(reg)); + WARN_ON_ONCE(1); + return -EPERM; + } + + offset += gsihal_reg_objs[gsihal_ctx->gsi_ver][reg].k_ofst * k; + offset += gsihal_reg_objs[gsihal_ctx->gsi_ver][reg].n_ofst * n; + return gsi_readl(gsihal_ctx->base + offset); +} + +/* +* gsihal_write_reg_nk() - Write to n/k parameterized reg a raw value +*/ +void gsihal_write_reg_nk(enum gsihal_reg_name reg, u32 n, u32 k, u32 val) +{ + u32 offset; + + if (reg >= GSI_REG_MAX) { + GSIERR("Invalid register reg=%u\n", reg); + WARN_ON(1); + return; + } + + GSIDBG_LOW("write to %s k=%u n=%u val=%u\n", + gsihal_reg_name_str(reg), k, n, val); + offset = gsihal_reg_objs[gsihal_ctx->gsi_ver][reg].offset; + if (offset == -1) { + GSIERR("Write access to obsolete reg=%s\n", + gsihal_reg_name_str(reg)); + WARN_ON(1); + return; + } + + offset += gsihal_reg_objs[gsihal_ctx->gsi_ver][reg].k_ofst * k; + offset += gsihal_reg_objs[gsihal_ctx->gsi_ver][reg].n_ofst * n; + gsi_writel(val, gsihal_ctx->base + offset); +} +EXPORT_SYMBOL(gsihal_write_reg_nk); + +/* + * gsihal_write_reg_fields() - Write to reg a prased value + */ +void gsihal_write_reg_fields(enum gsihal_reg_name reg, const void *fields) +{ + u32 val = 0; + u32 offset; + + if (!fields) { + GSIERR("Input error fields=%pK\n", fields); + WARN_ON(1); + return; + } + + if (reg >= GSI_REG_MAX) { + GSIERR("Invalid register reg=%u\n", reg); + WARN_ON(1); + return; + } + + GSIDBG_LOW("write to %s after constructing it\n", + gsihal_reg_name_str(reg)); + offset = gsihal_reg_objs[gsihal_ctx->gsi_ver][reg].offset; + if (offset == -1) { + GSIERR("Write access to obsolete reg=%s\n", + gsihal_reg_name_str(reg)); + WARN_ON(1); + return; + } + gsihal_reg_objs[gsihal_ctx->gsi_ver][reg].construct(reg, fields, &val); + + gsi_writel(val, gsihal_ctx->base + offset); +} + +/* + * gsihal_read_reg_fields() - Get the parsed value of reg + */ +u32 gsihal_read_reg_fields(enum gsihal_reg_name reg, void *fields) +{ + u32 val = 0; + u32 offset; + + if (!fields) { + GSIERR("Input error fields\n"); + WARN_ON(1); + return -EINVAL; + } + + if (reg >= GSI_REG_MAX) { + GSIERR("Invalid register reg=%u\n", reg); + WARN_ON(1); + return -EINVAL; + } + + GSIDBG_LOW("read from %s and parse it\n", + gsihal_reg_name_str(reg)); + offset = gsihal_reg_objs[gsihal_ctx->gsi_ver][reg].offset; + if (offset == -1) { + GSIERR("Read access to obsolete reg=%s\n", + gsihal_reg_name_str(reg)); + WARN_ON(1); + return -EPERM; + } + val = gsi_readl(gsihal_ctx->base + offset); + gsihal_reg_objs[gsihal_ctx->gsi_ver][reg].parse(reg, fields, val); + + return val; +} + +/* + * gsihal_write_reg_n_fields() - Write to n parameterized reg a prased value + */ +void gsihal_write_reg_n_fields(enum gsihal_reg_name reg, u32 n, + const void *fields) +{ + u32 val = 0; + u32 offset; + + if (!fields) { + GSIERR("Input error fields=%pK\n", fields); + WARN_ON(1); + return; + } + + if (reg >= GSI_REG_MAX) { + GSIERR("Invalid register reg=%u\n", reg); + WARN_ON(1); + return; + } + + GSIDBG_LOW("write to %s n=%u after constructing it\n", + gsihal_reg_name_str(reg), n); + offset = gsihal_reg_objs[gsihal_ctx->gsi_ver][reg].offset; + if (offset == -1) { + GSIERR("Write access to obsolete reg=%s\n", + gsihal_reg_name_str(reg)); + WARN_ON(1); + return; + } + offset += gsihal_reg_objs[gsihal_ctx->gsi_ver][reg].n_ofst * n; + gsihal_reg_objs[gsihal_ctx->gsi_ver][reg].construct(reg, fields, &val); + + gsi_writel(val, gsihal_ctx->base + offset); +} + +/* + * gsihal_read_reg_n_fields() - Get the parsed value of n parameterized reg + */ +u32 gsihal_read_reg_n_fields(enum gsihal_reg_name reg, u32 n, void *fields) +{ + u32 val = 0; + u32 offset; + + if (!fields) { + GSIERR("Input error fields\n"); + WARN_ON(1); + return -EINVAL; + } + + if (reg >= GSI_REG_MAX) { + GSIERR("Invalid register reg=%u\n", reg); + WARN_ON(1); + return -EINVAL; + } + + GSIDBG_LOW("read from %s n=%u and parse it\n", + gsihal_reg_name_str(reg), n); + offset = gsihal_reg_objs[gsihal_ctx->gsi_ver][reg].offset; + if (offset == -1) { + GSIERR("Read access to obsolete reg=%s\n", + gsihal_reg_name_str(reg)); + WARN_ON(1); + return -EPERM; + } + offset += gsihal_reg_objs[gsihal_ctx->gsi_ver][reg].n_ofst * n; + val = gsi_readl(gsihal_ctx->base + offset); + gsihal_reg_objs[gsihal_ctx->gsi_ver][reg].parse(reg, fields, val); + + return val; +} + +/* + * gsihal_read_reg_nk_fields() - Get the parsed value of nk parameterized reg + */ +u32 gsihal_read_reg_nk_fields(enum gsihal_reg_name reg, + u32 n, u32 k, void *fields) +{ + u32 val = 0; + u32 offset; + + if (!fields) { + GSIERR("Input error fields\n"); + WARN_ON(1); + return -EINVAL; + } + + if (reg >= GSI_REG_MAX) { + GSIERR("Invalid register reg=%u\n", reg); + WARN_ON(1); + return -EINVAL; + } + + GSIDBG_LOW("read from %s n=%u k= %u and parse it\n", + gsihal_reg_name_str(reg), n, k); + offset = gsihal_reg_objs[gsihal_ctx->gsi_ver][reg].offset; + if (offset == -1) { + GSIERR("Read access to obsolete reg=%s\n", + gsihal_reg_name_str(reg)); + WARN_ON(1); + return -EPERM; + } + offset += gsihal_reg_objs[gsihal_ctx->gsi_ver][reg].n_ofst * n; + offset += gsihal_reg_objs[gsihal_ctx->gsi_ver][reg].k_ofst * k; + val = gsi_readl(gsihal_ctx->base + offset); + gsihal_reg_objs[gsihal_ctx->gsi_ver][reg].parse(reg, fields, val); + + return val; +} + +/* + * gsihal_write_reg_nk_fields() - Write to nk parameterized reg a prased value + */ +void gsihal_write_reg_nk_fields(enum gsihal_reg_name reg, u32 n, u32 k, + const void *fields) +{ + u32 val = 0; + u32 offset; + + if (!fields) { + GSIERR("Input error fields=%pK\n", fields); + WARN_ON(1); + return; + } + + if (reg >= GSI_REG_MAX) { + GSIERR("Invalid register reg=%u\n", reg); + WARN_ON(1); + return; + } + + GSIDBG_LOW("write to %s n=%u after constructing it\n", + gsihal_reg_name_str(reg), n); + offset = gsihal_reg_objs[gsihal_ctx->gsi_ver][reg].offset; + if (offset == -1) { + GSIERR("Write access to obsolete reg=%s\n", + gsihal_reg_name_str(reg)); + WARN_ON(1); + return; + } + offset += gsihal_reg_objs[gsihal_ctx->gsi_ver][reg].n_ofst * n; + offset += gsihal_reg_objs[gsihal_ctx->gsi_ver][reg].k_ofst * k; + gsihal_reg_objs[gsihal_ctx->gsi_ver][reg].construct(reg, fields, &val); + + gsi_writel(val, gsihal_ctx->base + offset); +} + +/* + * Get the offset of a nk parameterized register + */ +u32 gsihal_get_reg_nk_ofst(enum gsihal_reg_name reg, u32 n, u32 k) +{ + u32 offset; + + if (reg >= GSI_REG_MAX) { + GSIERR("Invalid register reg=%u\n", reg); + WARN_ON(1); + return -EINVAL; + } + + GSIDBG_LOW("get offset of %s k=%u n=%u\n", + gsihal_reg_name_str(reg), k, n); + offset = gsihal_reg_objs[gsihal_ctx->gsi_ver][reg].offset; + if (offset == -1) { + GSIERR("Access to obsolete reg=%s\n", + gsihal_reg_name_str(reg)); + WARN_ON(1); + return -EPERM; + } + + offset += gsihal_reg_objs[gsihal_ctx->gsi_ver][reg].n_ofst * n; + offset += gsihal_reg_objs[gsihal_ctx->gsi_ver][reg].k_ofst * k; + + return offset; +} +EXPORT_SYMBOL(gsihal_get_reg_nk_ofst); + +/* +* gsihal_get_bit_map_array_size() - Get the size of the bit map +* array size according to the +* GSI version. +*/ +u32 gsihal_get_bit_map_array_size(void) +{ + return GSI_CH_BIT_MAP_ARR_SIZE; +} + +/* +* gsihal_read_ch_reg() - Get the raw value of a ch reg +*/ +u32 gsihal_read_ch_reg(enum gsihal_reg_name reg, u32 ch_num) +{ + return gsihal_read_reg_n(reg, GSI_CH_BIT_MAP_CELL_NUM(ch_num)); +} + +/* + * gsihal_test_ch_bit() - return true if a ch bit is set + */ +bool gsihal_test_ch_bit(u32 reg_val, u32 ch_num) +{ + return !!(reg_val & GSI_BIT_MAP_CELL_MSK(ch_num)); +} + +/* + * gsihal_get_ch_bit() - get ch bit set in the right offset + */ +u32 gsihal_get_ch_bit(u32 ch_num) +{ + return GSI_BIT_MAP_CELL_MSK(ch_num); +} + +/* + * gsihal_get_ch_reg_idx() - get ch reg index according to ch num + */ +u32 gsihal_get_ch_reg_idx(u32 ch_num) +{ + return GSI_CH_BIT_MAP_CELL_NUM(ch_num); +} + +/* + * gsihal_get_ch_reg_mask() - get ch reg mask according to ch num + */ +u32 gsihal_get_ch_reg_mask(u32 ch_num) +{ + return GSI_BIT_MAP_CELL_MSK(ch_num); +} + +/* + * Get the offset of a ch register according to ch index + */ +u32 gsihal_get_ch_reg_offset(enum gsihal_reg_name reg, u32 ch_num) +{ + return gsihal_get_reg_nk_ofst(reg, 0, GSI_CH_BIT_MAP_CELL_NUM(ch_num)); +} + +/* +* Get the offset of a ch n register according to ch index and n +*/ +u32 gsihal_get_ch_reg_n_offset(enum gsihal_reg_name reg, u32 n, u32 ch_num) +{ + return gsihal_get_reg_nk_ofst(reg, GSI_CH_BIT_MAP_CELL_NUM(ch_num), n); +} + +/* + * gsihal_write_ch_bit_map_reg_n() - Write mask to ch reg a raw value + */ +void gsihal_write_ch_bit_map_reg_n(enum gsihal_reg_name reg, u32 n, u32 ch_num, + u32 mask) +{ + gsihal_write_reg_nk(reg, n, GSI_CH_BIT_MAP_CELL_NUM(ch_num), mask); +} + +/* + * gsihal_write_set_ch_bit_map_reg_n() - Set ch bit in reg a raw value + */ +void gsihal_write_set_ch_bit_map_reg_n(enum gsihal_reg_name reg, u32 n, + u32 ch_num) +{ + gsihal_write_reg_nk(reg, n, GSI_CH_BIT_MAP_CELL_NUM(ch_num), + GSI_BIT_MAP_CELL_MSK(ch_num)); +} + +/* + * Get GSI instruction ram MAX size + */ +unsigned long gsihal_get_inst_ram_size(void) +{ + unsigned long maxn; + unsigned long size; + + switch (gsihal_ctx->gsi_ver) { + case GSI_VER_1_0: + case GSI_VER_1_2: + case GSI_VER_1_3: + maxn = GSI_GSI_INST_RAM_n_MAXn; + break; + case GSI_VER_2_0: + maxn = GSI_V2_0_GSI_INST_RAM_n_MAXn; + break; + case GSI_VER_2_2: + maxn = GSI_V2_2_GSI_INST_RAM_n_MAXn; + break; + case GSI_VER_2_5: + maxn = GSI_V2_5_GSI_INST_RAM_n_MAXn; + break; + case GSI_VER_2_7: + maxn = GSI_V2_7_GSI_INST_RAM_n_MAXn; + break; + case GSI_VER_2_9: + maxn = GSI_V2_9_GSI_INST_RAM_n_MAXn; + break; + case GSI_VER_3_0: + maxn = GSI_V3_0_GSI_INST_RAM_n_MAXn; + break; + case GSI_VER_5_2: + maxn = GSI_V5_2_GSI_INST_RAM_n_MAXn; + break; + case GSI_VER_ERR: + case GSI_VER_MAX: + default: + GSIERR("GSI version is not supported %d\n", + gsihal_ctx->gsi_ver); + WARN_ON(1); + return 0; + } + size = GSI_GSI_INST_RAM_n_WORD_SZ * (maxn + 1); + + return size; +} + +int gsihal_reg_init(enum gsi_ver gsi_ver) +{ + int i; + int j; + struct gsihal_reg_obj zero_obj; + + GSIDBG_LOW("Entry - GSI ver = %d\n", gsi_ver); + + if ((gsi_ver < GSI_VER_1_0) || (gsi_ver >= GSI_VER_MAX)) { + GSIERR("invalid GSI HW type (%d)\n", gsi_ver); + return -EINVAL; + } + + memset(&zero_obj, 0, sizeof(zero_obj)); + for (i = GSI_VER_1_0; i < gsi_ver; i++) { + for (j = 0; j < GSI_REG_MAX; j++) { + if (!memcmp(&gsihal_reg_objs[i + 1][j], &zero_obj, + sizeof(struct gsihal_reg_obj))) { + memcpy(&gsihal_reg_objs[i + 1][j], + &gsihal_reg_objs[i][j], + sizeof(struct gsihal_reg_obj)); + } else { + /* + * explicitly overridden register. + * Check validity + */ + if (j != GSI_GSI_CFG && !gsihal_reg_objs[i + 1][j].offset) { + GSIERR( + "reg=%s with zero offset gsi_ver=%d\n", + gsihal_reg_name_str(j), i + 1); + WARN_ON(1); + } + if (!gsihal_reg_objs[i + 1][j].construct) { + GSIERR( + "reg=%s with NULL construct func gsi_ver=%d\n", + gsihal_reg_name_str(j), i + 1); + WARN_ON(1); + } + if (!gsihal_reg_objs[i + 1][j].parse) { + GSIERR( + "reg=%s with NULL parse func gsi_ver=%d\n", + gsihal_reg_name_str(j), i + 1); + WARN_ON(1); + } + } + } + } + return 0; +} + +/* + * Check that ring length is valid + */ +bool gsihal_check_ring_length_valid(u32 r_len, u32 elem_size) +{ + if (gsihal_ctx->gsi_ver >= GSI_VER_3_0) { + if (r_len & ~GSI_V3_0_EE_n_GSI_CH_k_CNTXT_1_R_LENGTH_BMSK) { + GSIERR("bad params ring_len %u is out of bounds\n", r_len); + return false; + } + if (r_len / elem_size >= GSI_V3_0_MAX_ELEMENTS_PER_RING) { + GSIERR("bad params ring_len %u / re_size %u > 64k elements \n", + r_len, elem_size); + return false; + } + } else if (gsihal_ctx->gsi_ver >= GSI_VER_2_9) { + if (r_len & ~GSI_V2_9_EE_n_GSI_CH_k_CNTXT_1_R_LENGTH_BMSK) { + GSIERR("bad params ring_len %u is out of bounds\n", r_len); + return false; + } + } else { + if (r_len & ~GSI_EE_n_GSI_CH_k_CNTXT_1_R_LENGTH_BMSK) { + GSIERR("bad params ring_len %u is out of bounds\n", r_len); + return false; + } + } + + return true; +} + +/* + * Get mask for GP_int1 + */ +u32 gsihal_get_glob_irq_en_gp_int1_mask(void) +{ + return GSI_EE_n_CNTXT_GLOB_IRQ_EN_GP_INT1_BMSK; +} diff --git a/qcom/opensource/dataipa/drivers/platform/msm/gsi/gsihal/gsihal_reg.h b/qcom/opensource/dataipa/drivers/platform/msm/gsi/gsihal/gsihal_reg.h new file mode 100644 index 0000000000..bd02a28e74 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/gsi/gsihal/gsihal_reg.h @@ -0,0 +1,511 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* +* Copyright (c) 2030, The Linux Foundation. All rights reserved. +*/ + +#ifndef _GSIHAL_REG_H_ +#define _GSIHAL_REG_H_ + +/* + * Registers names + * + * NOTE:: Any change to this enum, need to change to gsireg_name_to_str + * array as well. + */ +enum gsihal_reg_name { + GSI_EE_n_CNTXT_TYPE_IRQ_MSK, + GSI_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK, + GSI_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK, + GSI_EE_n_CNTXT_SRC_IEOB_IRQ_MSK, + GSI_EE_n_CNTXT_GLOB_IRQ_EN, + GSI_EE_n_CNTXT_GSI_IRQ_EN, + GSI_EE_n_CNTXT_TYPE_IRQ, + GSI_EE_n_CNTXT_SRC_GSI_CH_IRQ, + GSI_EE_n_GSI_CH_k_CNTXT_0, + GSI_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR, + GSI_EE_n_CNTXT_SRC_EV_CH_IRQ, + GSI_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR, + GSI_EE_n_EV_CH_k_CNTXT_0, + GSI_EE_n_CNTXT_GLOB_IRQ_STTS, + GSI_EE_n_ERROR_LOG, + GSI_EE_n_ERROR_LOG_CLR, + GSI_EE_n_CNTXT_GLOB_IRQ_CLR, + GSI_EE_n_EV_CH_k_DOORBELL_0, + GSI_EE_n_GSI_CH_k_DOORBELL_0, + GSI_EE_n_CNTXT_SRC_IEOB_IRQ, + GSI_EE_n_CNTXT_SRC_IEOB_IRQ_CLR, + GSI_INTER_EE_n_SRC_GSI_CH_IRQ, + GSI_INTER_EE_n_SRC_GSI_CH_IRQ_CLR, + GSI_INTER_EE_n_SRC_EV_CH_IRQ, + GSI_INTER_EE_n_SRC_EV_CH_IRQ_CLR, + GSI_EE_n_CNTXT_GSI_IRQ_STTS, + GSI_EE_n_CNTXT_GSI_IRQ_CLR, + GSI_EE_n_GSI_HW_PARAM, + GSI_EE_n_GSI_HW_PARAM_0, + GSI_EE_n_GSI_HW_PARAM_2, + GSI_EE_n_GSI_HW_PARAM_4, + GSI_EE_n_GSI_SW_VERSION, + GSI_EE_n_CNTXT_INTSET, + GSI_EE_n_CNTXT_MSI_BASE_LSB, + GSI_EE_n_CNTXT_MSI_BASE_MSB, + GSI_EE_n_GSI_STATUS, + GSI_EE_n_CNTXT_SCRATCH_0, + GSI_EE_n_EV_CH_k_CNTXT_1, + GSI_EE_n_EV_CH_k_CNTXT_2, + GSI_EE_n_EV_CH_k_CNTXT_3, + GSI_EE_n_EV_CH_k_CNTXT_8, + GSI_EE_n_EV_CH_k_CNTXT_9, + GSI_EE_n_EV_CH_k_CNTXT_10, + GSI_EE_n_EV_CH_k_CNTXT_11, + GSI_EE_n_EV_CH_k_CNTXT_12, + GSI_EE_n_EV_CH_k_CNTXT_13, + GSI_EE_n_EV_CH_k_DOORBELL_1, + GSI_EE_n_EV_CH_CMD, + GSI_EE_n_EV_CH_k_SCRATCH_0, + GSI_EE_n_EV_CH_k_SCRATCH_1, + GSI_EE_n_GSI_CH_k_DOORBELL_1, + GSI_EE_n_GSI_CH_k_QOS, + GSI_EE_n_GSI_CH_k_CNTXT_1, + GSI_EE_n_GSI_CH_k_CNTXT_2, + GSI_EE_n_GSI_CH_k_CNTXT_3, + GSI_EE_n_GSI_CH_CMD, + GSI_EE_n_GSI_CH_k_SCRATCH_0, + GSI_EE_n_GSI_CH_k_SCRATCH_1, + GSI_EE_n_GSI_CH_k_SCRATCH_2, + GSI_EE_n_GSI_CH_k_SCRATCH_3, + GSI_EE_n_GSI_CH_k_SCRATCH_4, + GSI_EE_n_GSI_CH_k_SCRATCH_5, + GSI_EE_n_GSI_CH_k_SCRATCH_6, + GSI_EE_n_GSI_CH_k_SCRATCH_7, + GSI_EE_n_GSI_CH_k_SCRATCH_8, + GSI_EE_n_GSI_CH_k_SCRATCH_9, + GSI_EE_n_GSI_CH_k_CNTXT_4, + GSI_EE_n_GSI_CH_k_CNTXT_5, + GSI_EE_n_GSI_CH_k_CNTXT_6, + GSI_EE_n_GSI_CH_k_CNTXT_7, + GSI_EE_n_GSI_CH_k_CNTXT_8, + GSI_EE_n_EV_CH_k_CNTXT_4, + GSI_EE_n_EV_CH_k_CNTXT_5, + GSI_EE_n_EV_CH_k_CNTXT_6, + GSI_EE_n_EV_CH_k_CNTXT_7, + GSI_GSI_IRAM_PTR_CH_CMD, + GSI_GSI_IRAM_PTR_CH_DB, + GSI_GSI_IRAM_PTR_CH_DIS_COMP, + GSI_GSI_IRAM_PTR_CH_EMPTY, + GSI_GSI_IRAM_PTR_EE_GENERIC_CMD, + GSI_GSI_IRAM_PTR_EVENT_GEN_COMP, + GSI_GSI_IRAM_PTR_INT_MOD_STOPPED, + GSI_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0, + GSI_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2, + GSI_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1, + GSI_GSI_IRAM_PTR_NEW_RE, + GSI_GSI_IRAM_PTR_READ_ENG_COMP, + GSI_GSI_IRAM_PTR_TIMER_EXPIRED, + GSI_GSI_IRAM_PTR_EV_DB, + GSI_GSI_IRAM_PTR_UC_GP_INT, + GSI_GSI_IRAM_PTR_WRITE_ENG_COMP, + GSI_GSI_IRAM_PTR_TLV_CH_NOT_FULL, + GSI_IC_DISABLE_CHNL_BCK_PRS_LSB, + GSI_IC_DISABLE_CHNL_BCK_PRS_MSB, + GSI_IC_GEN_EVNT_BCK_PRS_LSB, + GSI_IC_GEN_EVNT_BCK_PRS_MSB, + GSI_IC_GEN_INT_BCK_PRS_LSB, + GSI_IC_GEN_INT_BCK_PRS_MSB, + GSI_IC_STOP_INT_MOD_BCK_PRS_LSB, + GSI_IC_STOP_INT_MOD_BCK_PRS_MSB, + GSI_IC_PROCESS_DESC_BCK_PRS_LSB, + GSI_IC_PROCESS_DESC_BCK_PRS_MSB, + GSI_IC_TLV_STOP_BCK_PRS_LSB, + GSI_IC_TLV_STOP_BCK_PRS_MSB, + GSI_IC_TLV_RESET_BCK_PRS_LSB, + GSI_IC_TLV_RESET_BCK_PRS_MSB, + GSI_IC_RGSTR_TIMER_BCK_PRS_LSB, + GSI_IC_RGSTR_TIMER_BCK_PRS_MSB, + GSI_IC_READ_BCK_PRS_LSB, + GSI_IC_READ_BCK_PRS_MSB, + GSI_IC_WRITE_BCK_PRS_LSB, + GSI_IC_WRITE_BCK_PRS_MSB, + GSI_IC_UCONTROLLER_GPR_BCK_PRS_LSB, + GSI_IC_UCONTROLLER_GPR_BCK_PRS_MSB, + GSI_GSI_PERIPH_BASE_ADDR_MSB, + GSI_GSI_PERIPH_BASE_ADDR_LSB, + GSI_GSI_MCS_CFG, + GSI_GSI_CFG, + GSI_EE_n_GSI_EE_GENERIC_CMD, + GSI_MAP_EE_n_CH_k_VP_TABLE, + GSI_EE_n_GSI_CH_k_RE_FETCH_READ_PTR, + GSI_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR, + GSI_GSI_INST_RAM_n, + GSI_GSI_IRAM_PTR_MSI_DB, + GSI_GSI_IRAM_PTR_INT_NOTIFY_MCS, + GSI_EE_n_CNTXT_SRC_GSI_CH_IRQ_k, + GSI_EE_n_CNTXT_SRC_EV_CH_IRQ_k, + GSI_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k, + GSI_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k, + GSI_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_k, + GSI_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_k, + GSI_EE_n_CNTXT_SRC_IEOB_IRQ_k, + GSI_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k, + GSI_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_k, + GSI_INTER_EE_n_SRC_GSI_CH_IRQ_k, + GSI_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_k, + GSI_INTER_EE_n_SRC_EV_CH_IRQ_k, + GSI_INTER_EE_n_SRC_EV_CH_IRQ_CLR_k, + GSI_GSI_SHRAM_n, + GSI_GSI_MCS_PROFILING_BP_CNT_LSB, + GSI_GSI_MCS_PROFILING_BP_CNT_MSB, + GSI_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB, + GSI_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB, + GSI_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB, + GSI_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB, + GSI_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB, + GSI_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB, + GSI_EE_n_CH_k_CH_ALMST_EMPTY_THRSHOLD, + GSI_EE_n_GSI_DEBUG_PC_FOR_DEBUG, + GSI_EE_n_GSI_DEBUG_BUSY_REG, + GSI_REG_MAX +}; + +struct gsihal_reg_ctx_type_irq { + uint32_t general; + uint32_t inter_ee_ev_ctrl; + uint32_t inter_ee_ch_ctrl; + uint32_t ieob; + uint32_t glob_ee; + uint32_t ev_ctrl; + uint32_t ch_ctrl; +}; + +struct gsihal_reg_ch_k_cntxt_0 { + uint32_t element_size; + uint32_t chstate; + uint32_t erindex; + uint32_t chtype_protocol_msb; + uint32_t chid; + uint32_t ee; + uint32_t chtype_dir; + uint32_t chtype_protocol; +}; + +struct gsihal_reg_cntxt_glob_irq_stts { + uint8_t gp_int3; + uint8_t gp_int2; + uint8_t gp_int1; + uint8_t error_int; +}; + +struct gsihal_reg_cntxt_gsi_irq_stts { + uint8_t gsi_mcs_stack_ovrflow; + uint8_t gsi_cmd_fifo_ovrflow; + uint8_t gsi_bus_error; + uint8_t gsi_break_point; +}; + +struct gsihal_reg_hw_param { + uint32_t periph_sec_grp; + uint32_t use_axi_m; + uint32_t periph_conf_addr_bus_w; + uint32_t num_ees; + uint32_t gsi_ch_num; + uint32_t gsi_ev_ch_num; +}; + +struct gsihal_reg_hw_param2 { + uint32_t gsi_use_inter_ee; + uint32_t gsi_use_rd_wr_eng; + uint32_t gsi_sdma_n_iovec; + uint32_t gsi_sdma_max_burst; + uint32_t gsi_sdma_n_int; + uint32_t gsi_use_sdma; + uint32_t gsi_ch_full_logic; + uint32_t gsi_ch_pend_translate; + uint32_t gsi_num_ev_per_ee; + uint32_t gsi_num_ch_per_ee; + uint32_t gsi_iram_size; +}; + +struct gsihal_reg_hw_param4 { + uint32_t gsi_iram_protcol_cnt; + uint32_t gsi_num_ev_per_ee; +}; + +struct gsihal_reg_gsi_status { + uint8_t enabled; +}; + +struct gsihal_reg_ev_ch_k_cntxt_0 { + uint32_t element_size; + uint32_t chstate; + uint32_t intype; + uint32_t evchid; + uint32_t ee; + uint32_t chtype; + +}; +struct gsihal_reg_ev_ch_k_cntxt_1 { + uint32_t r_length; +}; + +struct gsihal_reg_ev_ch_k_cntxt_2 { + uint32_t r_base_addr_lsbs; +}; + +struct gsihal_reg_ev_ch_k_cntxt_3 { + uint32_t r_base_addr_msbs; +}; + +struct gsihal_reg_ev_ch_k_cntxt_8 { + uint32_t int_mod_cnt; + uint32_t int_modc; + uint32_t int_modt; +}; + +struct gsihal_reg_ev_ch_k_cntxt_9 { + uint32_t intvec; +}; + +union gsihal_reg_ev_ch_k_cntxt_10 { + uint32_t msi_addr_lsb; + uint32_t rp_addr_lsb; +}; + +union gsihal_reg_ev_ch_k_cntxt_11 { + uint32_t msi_addr_msb; + uint32_t rp_addr_msb; +}; + +struct gsihal_reg_ev_ch_k_cntxt_12 { + uint32_t rp_update_addr_lsb; +}; + +struct gsihal_reg_ev_ch_k_cntxt_13 { + uint32_t rp_update_addr_msb; +}; + +struct gsihal_reg_gsi_ee_n_ev_ch_k_doorbell_1 { + uint32_t write_ptr_msb; +}; + +struct gsihal_reg_ee_n_ev_ch_cmd { + uint32_t opcode; + uint32_t chid; +}; + +struct gsihal_reg_ee_n_gsi_ch_cmd { + uint32_t opcode; + uint32_t chid; +}; + +struct gsihal_reg_gsi_ee_n_gsi_ch_k_qos { + uint32_t low_latency_en; //3.0 + uint32_t db_in_bytes; //2.9 + uint32_t empty_lvl_thrshold; + uint32_t prefetch_mode; + uint32_t use_escape_buf_only; //stringray + uint32_t use_db_eng; //mclaren + uint32_t max_prefetch; + uint32_t wrr_weight; +}; + +struct gsihal_reg_ch_k_cntxt_1 { + uint32_t r_length; + uint32_t erindex; +}; + +struct gsihal_reg_gsi_cfg { + uint32_t sleep_clk_div; + uint32_t bp_mtrix_disable; + uint32_t gsi_pwr_clps; + uint32_t uc_is_mcs; + uint32_t double_mcs_clk_freq; + uint32_t mcs_enable; + uint32_t gsi_enable; +}; + +struct gsihal_reg_gsi_ee_generic_cmd { + uint32_t opcode; + uint32_t virt_chan_idx; + uint32_t ee; + bool prmy_scnd_fc; +}; + +struct gsihal_reg_gsi_ee_n_cntxt_gsi_irq { + uint8_t gsi_mcs_stack_ovrflow; + uint8_t gsi_cmd_fifo_ovrflow; + uint8_t gsi_bus_error; + uint8_t gsi_break_point; +}; + +/* + * gsihal_reg_init() - intialize gsihal regsiters module + */ +int gsihal_reg_init(enum gsi_ver gsi_ver); + +/* + * gsihal_read_reg_nk() - Get nk parameterized reg value + */ +u32 gsihal_read_reg_nk(enum gsihal_reg_name reg, u32 n, u32 k); + +/* + * gsihal_read_reg_n() - Get n parameterized reg value + */ +static inline u32 gsihal_read_reg_n(enum gsihal_reg_name reg, u32 n) +{ + return gsihal_read_reg_nk(reg, n, 0); +} + +/* + * gsihal_read_reg() - Get reg value + */ +static inline u32 gsihal_read_reg(enum gsihal_reg_name reg) +{ + return gsihal_read_reg_nk(reg, 0, 0); +} + +/* + * gsihal_write_reg_nk() - Write to n/k parameterized reg a raw value + */ +void gsihal_write_reg_nk(enum gsihal_reg_name reg, u32 n, u32 k, u32 val); + +/* + * gsihal_write_reg_n() - Write to n parameterized reg a raw value + */ +static inline void gsihal_write_reg_n(enum gsihal_reg_name reg, u32 n, u32 val) +{ + gsihal_write_reg_nk(reg, n, 0, val); +} + +/* + * gsihal_write_reg() - Write to reg a raw value + */ +static inline void gsihal_write_reg(enum gsihal_reg_name reg, u32 val) +{ + gsihal_write_reg_nk(reg, 0, 0, val); +} + +/* + * gsihal_read_reg_nk_fields() - Get the parsed value of nk parameterized reg + */ +u32 gsihal_read_reg_nk_fields(enum gsihal_reg_name reg, + u32 n, u32 k, void *fields); + +/* + * gsihal_write_reg_nk_fields() - Write to nk parameterized reg a prased value + */ +void gsihal_write_reg_nk_fields(enum gsihal_reg_name reg, u32 n, u32 k, + const void *fields); + +/* +* gsihal_read_reg_n_fields() - Get the parsed value of n parameterized reg +*/ +u32 gsihal_read_reg_n_fields(enum gsihal_reg_name reg, u32 n, void *fields); + +/* + * gsihal_write_reg_n_fields() - Write to n parameterized reg a prased value + */ +void gsihal_write_reg_n_fields(enum gsihal_reg_name reg, u32 n, + const void *fields); + +/* + * gsihal_write_reg_fields() - Write to reg a prased value + */ +void gsihal_write_reg_fields(enum gsihal_reg_name reg, const void *fields); + +/* + * gsihal_read_reg_fields() - Get the parsed value of reg + */ +u32 gsihal_read_reg_fields(enum gsihal_reg_name reg, void *fields); + +/* +* gsihal_get_bit_map_array_size() - Get the size of the bit map +* array size according to the +* GSI version. +*/ +u32 gsihal_get_bit_map_array_size(void); + +/* +* gsihal_read_ch_reg() - Get the raw value of a ch reg +*/ +u32 gsihal_read_ch_reg(enum gsihal_reg_name reg, u32 ch_num); + +/* + * gsihal_test_ch_bit() - return true if a ch bit is set + */ +bool gsihal_test_ch_bit(u32 reg_val, u32 ch_num); + +/* + * gsihal_get_ch_bit() - get ch bit set in the right offset + */ +u32 gsihal_get_ch_bit(u32 ch_num); + +/* + * gsihal_get_ch_reg_idx() - get ch reg index according to ch num + */ +u32 gsihal_get_ch_reg_idx(u32 ch_num); + +/* + * gsihal_get_ch_reg_mask() - get ch reg mask according to ch num + */ +u32 gsihal_get_ch_reg_mask(u32 ch_num); + +/* + * gsihal_get_ch_reg_offset() - Get the offset of a ch register according to + * ch index + */ +u32 gsihal_get_ch_reg_offset(enum gsihal_reg_name reg, u32 ch_num); + +/* + * gsihal_get_ch_reg_n_offset() - Get the offset of a ch n register according + * to ch index and n + */ +u32 gsihal_get_ch_reg_n_offset(enum gsihal_reg_name reg, u32 n, u32 ch_num); + +/* + * gsihal_write_ch_bit_map_reg_n() - Write mask to ch reg a raw value + */ +void gsihal_write_ch_bit_map_reg_n(enum gsihal_reg_name reg, u32 n, u32 ch_num, + u32 mask); + +/* + * gsihal_write_set_ch_bit_map_reg_n() - Set ch bit in reg a raw value + */ +void gsihal_write_set_ch_bit_map_reg_n(enum gsihal_reg_name reg, u32 n, + u32 ch_num); + +/* + * Get the offset of a nk parameterized register + */ +u32 gsihal_get_reg_nk_ofst(enum gsihal_reg_name reg, u32 n, u32 k); + +/* + * Check that ring length is valid + */ +bool gsihal_check_ring_length_valid(u32 r_len, u32 elem_size); + +/* + * Get the offset of a n parameterized register + */ +static inline u32 gsihal_get_reg_n_ofst(enum gsihal_reg_name reg, u32 n) +{ + return gsihal_get_reg_nk_ofst(reg, n, 0); +} + +/* + * Get the offset of a register + */ +static inline u32 gsihal_get_reg_ofst(enum gsihal_reg_name reg) +{ + return gsihal_get_reg_nk_ofst(reg, 0, 0); +} + +/* + * Get GSI instruction ram MAX size + */ +unsigned long gsihal_get_inst_ram_size(void); + +/* + * Get mask for GP_int1 + */ +u32 gsihal_get_glob_irq_en_gp_int1_mask(void); + +#endif /* _GSIHAL_REG_H_ */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/gsi/gsihal/gsihal_reg_i.h b/qcom/opensource/dataipa/drivers/platform/msm/gsi/gsihal/gsihal_reg_i.h new file mode 100644 index 0000000000..6196a5986f --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/gsi/gsihal/gsihal_reg_i.h @@ -0,0 +1,352 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* +* Copyright (c) 2020, The Linux Foundation. All rights reserved. +* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. +*/ + +#ifndef _GSIHAL_REG_I_H_ +#define _GSIHAL_REG_I_H_ + +#define GSI_SETFIELD(val, shift, mask) (((val) << (shift)) & (mask)) +#define GSI_SETFIELD_IN_REG(reg, val, shift, mask) \ + (reg |= ((val) << (shift)) & (mask)) +#define GSI_GETFIELD_FROM_REG(reg, shift, mask) \ + (((reg) & (mask)) >> (shift)) + +/* GSI_GSI_INST_RAM_n */ +#define GSI_GSI_INST_RAM_n_WORD_SZ 0x4 + +/* GSI_GSI_SHRAM_n */ +#define GSI_GSI_SHRAM_n_WORD_SZ 0x4 + +#define GSI_GSI_INST_RAM_n_MAXn 4095 +#define GSI_V2_0_GSI_INST_RAM_n_MAXn 6143 +#define GSI_V2_2_GSI_INST_RAM_n_MAXn 4095 +#define GSI_V2_5_GSI_INST_RAM_n_MAXn 8191 +#define GSI_V2_7_GSI_INST_RAM_n_MAXn 5119 +#define GSI_V2_9_GSI_INST_RAM_n_MAXn 6143 +#define GSI_V3_0_GSI_INST_RAM_n_MAXn 8255 +#define GSI_V5_2_GSI_INST_RAM_n_MAXn 6207 + +/* GSI_EE_n_CNTXT_TYPE_IRQ */ +#define GSI_EE_n_CNTXT_TYPE_IRQ_GENERAL_BMSK 0x40 +#define GSI_EE_n_CNTXT_TYPE_IRQ_GENERAL_SHFT 0x6 +#define GSI_EE_n_CNTXT_TYPE_IRQ_INTER_EE_EV_CTRL_BMSK 0x20 +#define GSI_EE_n_CNTXT_TYPE_IRQ_INTER_EE_EV_CTRL_SHFT 0x5 +#define GSI_EE_n_CNTXT_TYPE_IRQ_INTER_EE_CH_CTRL_BMSK 0x10 +#define GSI_EE_n_CNTXT_TYPE_IRQ_INTER_EE_CH_CTRL_SHFT 0x4 +#define GSI_EE_n_CNTXT_TYPE_IRQ_IEOB_BMSK 0x8 +#define GSI_EE_n_CNTXT_TYPE_IRQ_IEOB_SHFT 0x3 +#define GSI_EE_n_CNTXT_TYPE_IRQ_GLOB_EE_BMSK 0x4 +#define GSI_EE_n_CNTXT_TYPE_IRQ_GLOB_EE_SHFT 0x2 +#define GSI_EE_n_CNTXT_TYPE_IRQ_EV_CTRL_BMSK 0x2 +#define GSI_EE_n_CNTXT_TYPE_IRQ_EV_CTRL_SHFT 0x1 +#define GSI_EE_n_CNTXT_TYPE_IRQ_CH_CTRL_BMSK 0x1 +#define GSI_EE_n_CNTXT_TYPE_IRQ_CH_CTRL_SHFT 0x0 + +/* GSI_EE_n_GSI_CH_k_CNTXT_0 */ +#define GSI_EE_n_GSI_CH_k_CNTXT_0_ELEMENT_SIZE_BMSK 0xff000000 +#define GSI_EE_n_GSI_CH_k_CNTXT_0_ELEMENT_SIZE_SHFT 0x18 +#define GSI_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_BMSK 0xf00000 +#define GSI_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_SHFT 0x14 +#define GSI_EE_n_GSI_CH_k_CNTXT_0_ERINDEX_BMSK 0x7c000 +#define GSI_EE_n_GSI_CH_k_CNTXT_0_ERINDEX_SHFT 0xe +#define GSI_EE_n_GSI_CH_k_CNTXT_0_CHID_BMSK 0x1f00 +#define GSI_EE_n_GSI_CH_k_CNTXT_0_CHID_SHFT 0x8 +#define GSI_EE_n_GSI_CH_k_CNTXT_0_EE_BMSK 0xf0 +#define GSI_EE_n_GSI_CH_k_CNTXT_0_EE_SHFT 0x4 +#define GSI_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_DIR_BMSK 0x8 +#define GSI_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_DIR_SHFT 0x3 +#define GSI_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_BMSK 0x7 +#define GSI_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_SHFT 0x0 + +#define GSI_V2_5_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_MSB_BMSK 0x2000 +#define GSI_V2_5_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_MSB_SHFT 0xd + +#define GSI_V3_0_EE_n_GSI_CH_k_CNTXT_0_CHID_BMSK 0xff000 +#define GSI_V3_0_EE_n_GSI_CH_k_CNTXT_0_CHID_SHFT 0xc +#define GSI_V3_0_EE_n_GSI_CH_k_CNTXT_0_EE_BMSK 0xf00 +#define GSI_V3_0_EE_n_GSI_CH_k_CNTXT_0_EE_SHFT 0x8 +#define GSI_V3_0_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_DIR_BMSK 0x80 +#define GSI_V3_0_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_DIR_SHFT 0x7 +#define GSI_V3_0_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_BMSK 0x7f +#define GSI_V3_0_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_SHFT 0x0 + +/* GSI_EE_n_EV_CH_k_CNTXT_0 */ +#define GSI_EE_n_EV_CH_k_CNTXT_0_ELEMENT_SIZE_BMSK 0xff000000 +#define GSI_EE_n_EV_CH_k_CNTXT_0_ELEMENT_SIZE_SHFT 0x18 +#define GSI_EE_n_EV_CH_k_CNTXT_0_CHSTATE_BMSK 0xf00000 +#define GSI_EE_n_EV_CH_k_CNTXT_0_CHSTATE_SHFT 0x14 +#define GSI_EE_n_EV_CH_k_CNTXT_0_INTYPE_BMSK 0x10000 +#define GSI_EE_n_EV_CH_k_CNTXT_0_INTYPE_SHFT 0x10 +#define GSI_EE_n_EV_CH_k_CNTXT_0_EVCHID_BMSK 0xff00 +#define GSI_EE_n_EV_CH_k_CNTXT_0_EVCHID_SHFT 0x8 +#define GSI_EE_n_EV_CH_k_CNTXT_0_EE_BMSK 0xf0 +#define GSI_EE_n_EV_CH_k_CNTXT_0_EE_SHFT 0x4 +#define GSI_EE_n_EV_CH_k_CNTXT_0_CHTYPE_BMSK 0xf +#define GSI_EE_n_EV_CH_k_CNTXT_0_CHTYPE_SHFT 0x0 + +#define GSI_V3_0_EE_n_EV_CH_k_CNTXT_0_EE_BMSK 0xf0000 +#define GSI_V3_0_EE_n_EV_CH_k_CNTXT_0_EE_SHFT 0x10 +#define GSI_V3_0_EE_n_EV_CH_k_CNTXT_0_INTYPE_BMSK 0x80 +#define GSI_V3_0_EE_n_EV_CH_k_CNTXT_0_INTYPE_SHFT 0x7 +#define GSI_V3_0_EE_n_EV_CH_k_CNTXT_0_CHTYPE_BMSK 0x7f +#define GSI_V3_0_EE_n_EV_CH_k_CNTXT_0_CHTYPE_SHFT 0x0 + +/* GSI_EE_n_CNTXT_GLOB_IRQ_STTS */ +#define GSI_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT3_BMSK 0x8 +#define GSI_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT3_SHFT 0x3 +#define GSI_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT2_BMSK 0x4 +#define GSI_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT2_SHFT 0x2 +#define GSI_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT1_BMSK 0x2 +#define GSI_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT1_SHFT 0x1 +#define GSI_EE_n_CNTXT_GLOB_IRQ_STTS_ERROR_INT_BMSK 0x1 +#define GSI_EE_n_CNTXT_GLOB_IRQ_STTS_ERROR_INT_SHFT 0x0 + +/* GSI_EE_n_CNTXT_GLOB_IRQ_EN */ +#define GSI_EE_n_CNTXT_GLOB_IRQ_EN_GP_INT3_BMSK 0x8 +#define GSI_EE_n_CNTXT_GLOB_IRQ_EN_GP_INT3_SHFT 0x3 +#define GSI_EE_n_CNTXT_GLOB_IRQ_EN_GP_INT2_BMSK 0x4 +#define GSI_EE_n_CNTXT_GLOB_IRQ_EN_GP_INT2_SHFT 0x2 +#define GSI_EE_n_CNTXT_GLOB_IRQ_EN_GP_INT1_BMSK 0x2 +#define GSI_EE_n_CNTXT_GLOB_IRQ_EN_GP_INT1_SHFT 0x1 +#define GSI_EE_n_CNTXT_GLOB_IRQ_EN_ERROR_INT_BMSK 0x1 +#define GSI_EE_n_CNTXT_GLOB_IRQ_EN_ERROR_INT_SHFT 0x0 + +/* GSI_EE_n_CNTXT_GSI_IRQ_STTS */ +#define GSI_EE_n_CNTXT_GSI_IRQ_STTS_GSI_MCS_STACK_OVRFLOW_BMSK 0x8 +#define GSI_EE_n_CNTXT_GSI_IRQ_STTS_GSI_MCS_STACK_OVRFLOW_SHFT 0x3 +#define GSI_EE_n_CNTXT_GSI_IRQ_STTS_GSI_CMD_FIFO_OVRFLOW_BMSK 0x4 +#define GSI_EE_n_CNTXT_GSI_IRQ_STTS_GSI_CMD_FIFO_OVRFLOW_SHFT 0x2 +#define GSI_EE_n_CNTXT_GSI_IRQ_STTS_GSI_BUS_ERROR_BMSK 0x2 +#define GSI_EE_n_CNTXT_GSI_IRQ_STTS_GSI_BUS_ERROR_SHFT 0x1 +#define GSI_EE_n_CNTXT_GSI_IRQ_STTS_GSI_BREAK_POINT_BMSK 0x1 +#define GSI_EE_n_CNTXT_GSI_IRQ_STTS_GSI_BREAK_POINT_SHFT 0x0 + +/* GSI_EE_n_CNTXT_TYPE_IRQ */ +#define GSI_EE_n_CNTXT_TYPE_IRQ_GENERAL_BMSK 0x40 +#define GSI_EE_n_CNTXT_TYPE_IRQ_GENERAL_SHFT 0x6 +#define GSI_EE_n_CNTXT_TYPE_IRQ_INTER_EE_EV_CTRL_BMSK 0x20 +#define GSI_EE_n_CNTXT_TYPE_IRQ_INTER_EE_EV_CTRL_SHFT 0x5 +#define GSI_EE_n_CNTXT_TYPE_IRQ_INTER_EE_CH_CTRL_BMSK 0x10 +#define GSI_EE_n_CNTXT_TYPE_IRQ_INTER_EE_CH_CTRL_SHFT 0x4 +#define GSI_EE_n_CNTXT_TYPE_IRQ_IEOB_BMSK 0x8 +#define GSI_EE_n_CNTXT_TYPE_IRQ_IEOB_SHFT 0x3 +#define GSI_EE_n_CNTXT_TYPE_IRQ_GLOB_EE_BMSK 0x4 +#define GSI_EE_n_CNTXT_TYPE_IRQ_GLOB_EE_SHFT 0x2 +#define GSI_EE_n_CNTXT_TYPE_IRQ_EV_CTRL_BMSK 0x2 +#define GSI_EE_n_CNTXT_TYPE_IRQ_EV_CTRL_SHFT 0x1 +#define GSI_EE_n_CNTXT_TYPE_IRQ_CH_CTRL_BMSK 0x1 +#define GSI_EE_n_CNTXT_TYPE_IRQ_CH_CTRL_SHFT 0x0 + +/* GSI_EE_n_GSI_HW_PARAM */ +#define GSI_V1_0_EE_n_GSI_HW_PARAM_PERIPH_SEC_GRP_BMSK 0x7c000000 +#define GSI_V1_0_EE_n_GSI_HW_PARAM_PERIPH_SEC_GRP_SHFT 0x1a +#define GSI_V1_0_EE_n_GSI_HW_PARAM_USE_AXI_M_BMSK 0x2000000 +#define GSI_V1_0_EE_n_GSI_HW_PARAM_USE_AXI_M_SHFT 0x19 +#define GSI_V1_0_EE_n_GSI_HW_PARAM_PERIPH_CONF_ADDR_BUS_W_BMSK 0x1f00000 +#define GSI_V1_0_EE_n_GSI_HW_PARAM_PERIPH_CONF_ADDR_BUS_W_SHFT 0x14 +#define GSI_V1_0_EE_n_GSI_HW_PARAM_NUM_EES_BMSK 0xf0000 +#define GSI_V1_0_EE_n_GSI_HW_PARAM_NUM_EES_SHFT 0x10 +#define GSI_V1_0_EE_n_GSI_HW_PARAM_GSI_CH_NUM_BMSK 0xff00 +#define GSI_V1_0_EE_n_GSI_HW_PARAM_GSI_CH_NUM_SHFT 0x8 +#define GSI_V1_0_EE_n_GSI_HW_PARAM_GSI_EV_CH_NUM_BMSK 0xff +#define GSI_V1_0_EE_n_GSI_HW_PARAM_GSI_EV_CH_NUM_SHFT 0x0 + +/* GSI_EE_n_GSI_HW_PARAM_0 */ +#define GSI_V1_2_EE_n_GSI_HW_PARAM_0_USE_AXI_M_BMSK 0x80000000 +#define GSI_V1_2_EE_n_GSI_HW_PARAM_0_USE_AXI_M_SHFT 0x1f +#define GSI_V1_2_EE_n_GSI_HW_PARAM_0_PERIPH_SEC_GRP_BMSK 0x7c000000 +#define GSI_V1_2_EE_n_GSI_HW_PARAM_0_PERIPH_SEC_GRP_SHFT 0x1a +#define GSI_V1_2_EE_n_GSI_HW_PARAM_0_PERIPH_CONF_ADDR_BUS_W_BMSK 0x3e00000 +#define GSI_V1_2_EE_n_GSI_HW_PARAM_0_PERIPH_CONF_ADDR_BUS_W_SHFT 0x15 +#define GSI_V1_2_EE_n_GSI_HW_PARAM_0_NUM_EES_BMSK 0x1f0000 +#define GSI_V1_2_EE_n_GSI_HW_PARAM_0_NUM_EES_SHFT 0x10 +#define GSI_V1_2_EE_n_GSI_HW_PARAM_0_GSI_CH_NUM_BMSK 0xff00 +#define GSI_V1_2_EE_n_GSI_HW_PARAM_0_GSI_CH_NUM_SHFT 0x8 +#define GSI_V1_2_EE_n_GSI_HW_PARAM_0_GSI_EV_CH_NUM_BMSK 0xff +#define GSI_V1_2_EE_n_GSI_HW_PARAM_0_GSI_EV_CH_NUM_SHFT 0x0 + +/* GSI_EE_n_GSI_HW_PARAM_2 */ +#define GSI_V1_3_EE_n_GSI_HW_PARAM_2_GSI_CH_FULL_LOGIC_BMSK 0x4000 +#define GSI_V1_3_EE_n_GSI_HW_PARAM_2_GSI_CH_FULL_LOGIC_SHFT 0xe +#define GSI_V1_3_EE_n_GSI_HW_PARAM_2_GSI_CH_PEND_TRANSLATE_BMSK 0x2000 +#define GSI_V1_3_EE_n_GSI_HW_PARAM_2_GSI_CH_PEND_TRANSLATE_SHFT 0xd +#define GSI_V1_3_EE_n_GSI_HW_PARAM_2_GSI_NUM_EV_PER_EE_BMSK 0x1f00 +#define GSI_V1_3_EE_n_GSI_HW_PARAM_2_GSI_NUM_EV_PER_EE_SHFT 0x8 +#define GSI_V1_3_EE_n_GSI_HW_PARAM_2_GSI_NUM_CH_PER_EE_BMSK 0xf8 +#define GSI_V1_3_EE_n_GSI_HW_PARAM_2_GSI_NUM_CH_PER_EE_SHFT 0x3 +#define GSI_V1_3_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_BMSK 0x7 +#define GSI_V1_3_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_SHFT 0x0 + +#define GSI_V2_0_EE_n_GSI_HW_PARAM_2_GSI_SDMA_N_IOVEC_BMSK 0x38000000 +#define GSI_V2_0_EE_n_GSI_HW_PARAM_2_GSI_SDMA_N_IOVEC_SHFT 0x1b +#define GSI_V2_0_EE_n_GSI_HW_PARAM_2_GSI_SDMA_MAX_BURST_BMSK 0x7F80000 +#define GSI_V2_0_EE_n_GSI_HW_PARAM_2_GSI_SDMA_MAX_BURST_SHFT 0x13 +#define GSI_V2_0_EE_n_GSI_HW_PARAM_2_GSI_SDMA_N_INT_BMSK 0x70000 +#define GSI_V2_0_EE_n_GSI_HW_PARAM_2_GSI_SDMA_N_INT_SHFT 0x10 +#define GSI_V2_0_EE_n_GSI_HW_PARAM_2_GSI_USE_SDMA_BMSK 0x8000 +#define GSI_V2_0_EE_n_GSI_HW_PARAM_2_GSI_USE_SDMA_SHFT 0xf + +#define GSI_V2_2_EE_n_GSI_HW_PARAM_2_GSI_USE_INTER_EE_BMSK 0x80000000 +#define GSI_V2_2_EE_n_GSI_HW_PARAM_2_GSI_USE_INTER_EE_SHFT 0x1f +#define GSI_V2_2_EE_n_GSI_HW_PARAM_2_GSI_USE_RD_WR_ENG_BMSK 0x40000000 +#define GSI_V2_2_EE_n_GSI_HW_PARAM_2_GSI_USE_RD_WR_ENG_SHFT 0x1E + +#define GSI_V3_0_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_BMSK 0x1f00 +#define GSI_V3_0_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_SHFT 0x8 +#define GSI_V3_0_EE_n_GSI_HW_PARAM_2_GSI_NUM_CH_PER_EE_BMSK 0xff +#define GSI_V3_0_EE_n_GSI_HW_PARAM_2_GSI_NUM_CH_PER_EE_SHFT 0x0 + +/* GSI_EE_n_GSI_HW_PARAM_4 */ +#define GSI_V3_0_EE_n_GSI_HW_PARAM_4_GSI_IRAM_PROTCOL_CNT_BMSK 0xff00 +#define GSI_V3_0_EE_n_GSI_HW_PARAM_4_GSI_IRAM_PROTCOL_CNT_SHFT 0x8 +#define GSI_V3_0_EE_n_GSI_HW_PARAM_4_GSI_NUM_EV_PER_EE_BMSK 0xff +#define GSI_V3_0_EE_n_GSI_HW_PARAM_4_GSI_NUM_EV_PER_EE_SHFT 0x0 + +/* GSI_EE_n_GSI_STATUS */ +#define GSI_EE_n_GSI_STATUS_ENABLED_BMSK 0x1 +#define GSI_EE_n_GSI_STATUS_ENABLED_SHFT 0x0 + +/* GSI_EE_n_EV_CH_k_CNTXT_1 */ +#define GSI_EE_n_EV_CH_k_CNTXT_1_R_LENGTH_BMSK 0xffff +#define GSI_EE_n_EV_CH_k_CNTXT_1_R_LENGTH_SHFT 0x0 + +#define GSI_V2_9_EE_n_EV_CH_k_CNTXT_1_R_LENGTH_BMSK 0xfffff +#define GSI_V2_9_EE_n_EV_CH_k_CNTXT_1_R_LENGTH_SHFT 0x0 + +#define GSI_V3_0_EE_n_EV_CH_k_CNTXT_1_R_LENGTH_BMSK 0xffffff +#define GSI_V3_0_EE_n_EV_CH_k_CNTXT_1_R_LENGTH_SHFT 0x0 + +/* GSI_EE_n_EV_CH_k_CNTXT_2 */ +#define GSI_EE_n_EV_CH_k_CNTXT_2_R_BASE_ADDR_LSBS_BMSK 0xffffffff +#define GSI_EE_n_EV_CH_k_CNTXT_2_R_BASE_ADDR_LSBS_SHFT 0x0 + +/* GSI_EE_n_EV_CH_k_CNTXT_3 */ +#define GSI_EE_n_EV_CH_k_CNTXT_3_R_BASE_ADDR_MSBS_BMSK 0xffffffff +#define GSI_EE_n_EV_CH_k_CNTXT_3_R_BASE_ADDR_MSBS_SHFT 0x0 + +/* GSI_EE_n_EV_CH_k_CNTXT_8 */ +#define GSI_EE_n_EV_CH_k_CNTXT_8_INT_MOD_CNT_BMSK 0xff000000 +#define GSI_EE_n_EV_CH_k_CNTXT_8_INT_MOD_CNT_SHFT 0x18 +#define GSI_EE_n_EV_CH_k_CNTXT_8_INT_MODC_BMSK 0xff0000 +#define GSI_EE_n_EV_CH_k_CNTXT_8_INT_MODC_SHFT 0x10 +#define GSI_EE_n_EV_CH_k_CNTXT_8_INT_MODT_BMSK 0xffff +#define GSI_EE_n_EV_CH_k_CNTXT_8_INT_MODT_SHFT 0x0 + +/* GSI_EE_n_EV_CH_k_CNTXT_9 */ +#define GSI_EE_n_EV_CH_k_CNTXT_9_INTVEC_BMSK 0xffffffff +#define GSI_EE_n_EV_CH_k_CNTXT_9_INTVEC_SHFT 0x0 + +/* GSI_EE_n_EV_CH_k_CNTXT_10 */ +#define GSI_EE_n_EV_CH_k_CNTXT_10_ADDR_LSB_BMSK 0xffffffff +#define GSI_EE_n_EV_CH_k_CNTXT_10_ADDR_LSB_SHFT 0x0 + +/* GSI_EE_n_EV_CH_k_CNTXT_11 */ +#define GSI_EE_n_EV_CH_k_CNTXT_11_ADDR_MSB_BMSK 0xffffffff +#define GSI_EE_n_EV_CH_k_CNTXT_11_ADDR_MSB_SHFT 0x0 + +/* GSI_EE_n_EV_CH_k_CNTXT_12 */ +#define GSI_EE_n_EV_CH_k_CNTXT_12_RP_UPDATE_ADDR_LSB_BMSK 0xffffffff +#define GSI_EE_n_EV_CH_k_CNTXT_12_RP_UPDATE_ADDR_LSB_SHFT 0x0 + +/* GSI_EE_n_EV_CH_k_CNTXT_13 */ +#define GSI_EE_n_EV_CH_k_CNTXT_13_RP_UPDATE_ADDR_MSB_BMSK 0xffffffff +#define GSI_EE_n_EV_CH_k_CNTXT_13_RP_UPDATE_ADDR_MSB_SHFT 0x0 + +/* GSI_EE_n_EV_CH_k_DOORBELL_1 */ +#define GSI_EE_n_EV_CH_k_DOORBELL_1_WRITE_PTR_MSB_BMSK 0xffffffff +#define GSI_EE_n_EV_CH_k_DOORBELL_1_WRITE_PTR_MSB_SHFT 0x0 + +/* GSI_EE_n_EV_CH_CMD */ +#define GSI_EE_n_EV_CH_CMD_OPCODE_BMSK 0xff000000 +#define GSI_EE_n_EV_CH_CMD_OPCODE_SHFT 0x18 +#define GSI_EE_n_EV_CH_CMD_CHID_BMSK 0xff +#define GSI_EE_n_EV_CH_CMD_CHID_SHFT 0x0 + +/* GSI_EE_n_GSI_CH_k_QOS */ +#define GSI_EE_n_GSI_CH_k_QOS_USE_DB_ENG_BMSK 0x200 +#define GSI_EE_n_GSI_CH_k_QOS_USE_DB_ENG_SHFT 0x9 +#define GSI_EE_n_GSI_CH_k_QOS_MAX_PREFETCH_BMSK 0x100 +#define GSI_EE_n_GSI_CH_k_QOS_MAX_PREFETCH_SHFT 0x8 +#define GSI_EE_n_GSI_CH_k_QOS_WRR_WEIGHT_BMSK 0xf +#define GSI_EE_n_GSI_CH_k_QOS_WRR_WEIGHT_SHFT 0x0 + +#define GSI_V2_0_EE_n_GSI_CH_k_QOS_USE_ESCAPE_BUF_ONLY_BMSK 0x400 +#define GSI_V2_0_EE_n_GSI_CH_k_QOS_USE_ESCAPE_BUF_ONLY_SHFT 0xa + +#define GSI_V2_5_EE_n_GSI_CH_k_QOS_EMPTY_LVL_THRSHOLD_SHFT 0x10 +#define GSI_V2_9_EE_n_GSI_CH_k_QOS_EMPTY_LVL_THRSHOLD_BMSK 0xff0000 +#define GSI_V2_5_EE_n_GSI_CH_k_QOS_PREFETCH_MODE_BMSK 0x3c00 +#define GSI_V2_5_EE_n_GSI_CH_k_QOS_PREFETCH_MODE_SHFT 0xa + +#define GSI_V2_9_EE_n_GSI_CH_k_QOS_DB_IN_BYTES_BMSK 0x1000000 +#define GSI_V2_9_EE_n_GSI_CH_k_QOS_DB_IN_BYTES_SHFT 0x18 + +#define GSI_V3_0_EE_n_GSI_CH_k_QOS_LOW_LATENCY_EN_BMSK 0x2000000 +#define GSI_V3_0_EE_n_GSI_CH_k_QOS_LOW_LATENCY_EN_SHFT 0x19 + +/* GSI_EE_n_GSI_CH_k_CNTXT_1 */ +#define GSI_EE_n_GSI_CH_k_CNTXT_1_R_LENGTH_BMSK 0xffff +#define GSI_EE_n_GSI_CH_k_CNTXT_1_R_LENGTH_SHFT 0x0 + +#define GSI_V2_9_EE_n_GSI_CH_k_CNTXT_1_R_LENGTH_BMSK 0xfffff +#define GSI_V2_9_EE_n_GSI_CH_k_CNTXT_1_R_LENGTH_SHFT 0x0 + +#define GSI_V3_0_EE_n_GSI_CH_k_CNTXT_1_ERINDEX_BMSK 0xff000000 +#define GSI_V3_0_EE_n_GSI_CH_k_CNTXT_1_ERINDEX_SHFT 0x18 +#define GSI_V3_0_EE_n_GSI_CH_k_CNTXT_1_R_LENGTH_BMSK 0xffffff +#define GSI_V3_0_EE_n_GSI_CH_k_CNTXT_1_R_LENGTH_SHFT 0x0 + +/* For GSI 3.0 each ring has maximum of 64 * 1024 elements */ +#define GSI_V3_0_MAX_ELEMENTS_PER_RING (65536) + +/* GSI_EE_n_GSI_CH_CMD */ +#define GSI_EE_n_GSI_CH_CMD_OPCODE_BMSK 0xff000000 +#define GSI_EE_n_GSI_CH_CMD_OPCODE_SHFT 0x18 +#define GSI_EE_n_GSI_CH_CMD_CHID_BMSK 0xff +#define GSI_EE_n_GSI_CH_CMD_CHID_SHFT 0x0 + +/* GSI_GSI_CFG */ +#define GSI_GSI_CFG_BP_MTRIX_DISABLE_BMSK 0x20 +#define GSI_GSI_CFG_BP_MTRIX_DISABLE_SHFT 0x5 +#define GSI_GSI_CFG_GSI_PWR_CLPS_BMSK 0x10 +#define GSI_GSI_CFG_GSI_PWR_CLPS_SHFT 0x4 +#define GSI_GSI_CFG_UC_IS_MCS_BMSK 0x8 +#define GSI_GSI_CFG_UC_IS_MCS_SHFT 0x3 +#define GSI_GSI_CFG_DOUBLE_MCS_CLK_FREQ_BMSK 0x4 +#define GSI_GSI_CFG_DOUBLE_MCS_CLK_FREQ_SHFT 0x2 +#define GSI_GSI_CFG_MCS_ENABLE_BMSK 0x2 +#define GSI_GSI_CFG_MCS_ENABLE_SHFT 0x1 +#define GSI_GSI_CFG_GSI_ENABLE_BMSK 0x1 +#define GSI_GSI_CFG_GSI_ENABLE_SHFT 0x0 + +#define GSI_V2_5_GSI_CFG_SLEEP_CLK_DIV_BMSK 0xf00 +#define GSI_V2_5_GSI_CFG_SLEEP_CLK_DIV_SHFT 0x8 + +/* GSI_EE_n_GSI_EE_GENERIC_CMD */ +#define GSI_EE_n_GSI_EE_GENERIC_CMD_OPCODE_BMSK 0x1f +#define GSI_EE_n_GSI_EE_GENERIC_CMD_OPCODE_SHFT 0x0 +#define GSI_EE_n_GSI_EE_GENERIC_CMD_VIRT_CHAN_IDX_BMSK 0x3e0 +#define GSI_EE_n_GSI_EE_GENERIC_CMD_VIRT_CHAN_IDX_SHFT 0x5 +#define GSI_EE_n_GSI_EE_GENERIC_CMD_EE_BMSK 0x3c00 +#define GSI_EE_n_GSI_EE_GENERIC_CMD_EE_SHFT 0xa + +#define GSI_V3_0_EE_n_GSI_EE_GENERIC_CMD_VIRT_CHAN_IDX_BMSK 0x1fe0 +#define GSI_V3_0_EE_n_GSI_EE_GENERIC_CMD_VIRT_CHAN_IDX_SHFT 0x5 +#define GSI_V3_0_EE_n_GSI_EE_GENERIC_CMD_EE_BMSK 0x1e000 +#define GSI_V3_0_EE_n_GSI_EE_GENERIC_CMD_EE_SHFT 0xd +#define GSI_V3_0_EE_n_GSI_EE_GENERIC_CMD_PARAM_BMSK 0xff000000 +#define GSI_V3_0_EE_n_GSI_EE_GENERIC_CMD_PARAM_SHFT 0x18 + +/* GSI_EE_n_CNTXT_GSI_IRQ_EN */ +#define GSI_EE_n_CNTXT_GSI_IRQ_EN_GSI_MCS_STACK_OVRFLOW_BMSK 0x8 +#define GSI_EE_n_CNTXT_GSI_IRQ_EN_GSI_MCS_STACK_OVRFLOW_SHFT 0x3 +#define GSI_EE_n_CNTXT_GSI_IRQ_EN_GSI_CMD_FIFO_OVRFLOW_BMSK 0x4 +#define GSI_EE_n_CNTXT_GSI_IRQ_EN_GSI_CMD_FIFO_OVRFLOW_SHFT 0x2 +#define GSI_EE_n_CNTXT_GSI_IRQ_EN_GSI_BUS_ERROR_BMSK 0x2 +#define GSI_EE_n_CNTXT_GSI_IRQ_EN_GSI_BUS_ERROR_SHFT 0x1 +#define GSI_EE_n_CNTXT_GSI_IRQ_EN_GSI_BREAK_POINT_BMSK 0x1 +#define GSI_EE_n_CNTXT_GSI_IRQ_EN_GSI_BREAK_POINT_SHFT 0x0 + +#endif /* _GSIHAL_REG_I_H_ */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/include/linux/ipa.h b/qcom/opensource/dataipa/drivers/platform/msm/include/linux/ipa.h new file mode 100644 index 0000000000..280817ecfb --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/include/linux/ipa.h @@ -0,0 +1,2450 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _IPA_H_ +#define _IPA_H_ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define IPA_APPS_MAX_BW_IN_MBPS 700 +#define IPA_BW_THRESHOLD_MAX 3 + +#define IPA_MAX_CH_STATS_SUPPORTED 5 +#define IPA_EP_ARR_SIZE 2 +#define IPA_EP_PER_REG 32 + +/* Notifiers for rmnet driver */ +#define BUFF_ABOVE_HIGH_THRESHOLD_FOR_DEFAULT_PIPE 1 +#define BUFF_ABOVE_HIGH_THRESHOLD_FOR_COAL_PIPE 2 +#define BUFF_BELOW_LOW_THRESHOLD_FOR_DEFAULT_PIPE 3 +#define BUFF_BELOW_LOW_THRESHOLD_FOR_COAL_PIPE 4 +#define BUFF_ABOVE_HIGH_THRESHOLD_FOR_LL_PIPE 5 +#define BUFF_BELOW_LOW_THRESHOLD_FOR_LL_PIPE 6 +#define FREE_PAGE_TASK_SCHEDULED 7 +#define FREE_PAGE_TASK_SCHEDULED_LL 8 + +/** + * the attributes of the socksv5 options + */ +#define IPA_SOCKSv5_ENTRY_VALID (1ul << 0) +#define IPA_SOCKSv5_IPV4 (1ul << 1) +#define IPA_SOCKSv5_IPV6 (1ul << 2) +#define IPA_SOCKSv5_OPT_TS (1ul << 3) +#define IPA_SOCKSv5_OPT_SACK (1ul << 4) +#define IPA_SOCKSv5_OPT_WS_STC (1ul << 5) +#define IPA_SOCKSv5_OPT_WS_DMC (1ul << 6) + +#define IPA_SOCKsv5_ADD_COM_ID 15 +#define IPA_SOCKsv5_ADD_V6_V4_COM_PM 1 +#define IPA_SOCKsv5_ADD_V4_V6_COM_PM 2 +#define IPA_SOCKsv5_ADD_V6_V6_COM_PM 3 + +/** + * enum ipa_transport_type + * transport type: either GSI or SPS + */ +enum ipa_transport_type { + IPA_TRANSPORT_TYPE_SPS, + IPA_TRANSPORT_TYPE_GSI +}; + +/** + * enum ipa_nat_en_type - NAT setting type in IPA end-point + */ +enum ipa_nat_en_type { + IPA_BYPASS_NAT, + IPA_SRC_NAT, + IPA_DST_NAT, +}; + +/** + * enum ipa_ipv6ct_en_type - IPv6CT setting type in IPA end-point + */ +enum ipa_ipv6ct_en_type { + IPA_BYPASS_IPV6CT, + IPA_ENABLE_IPV6CT, +}; + +/** + * enum ipa_mode_type - mode setting type in IPA end-point + * @BASIC: basic mode + * @ENABLE_FRAMING_HDLC: not currently supported + * @ENABLE_DEFRAMING_HDLC: not currently supported + * @DMA: all data arriving IPA will not go through IPA logic blocks, this + * allows IPA to work as DMA for specific pipes. + */ +enum ipa_mode_type { + IPA_BASIC, + IPA_ENABLE_FRAMING_HDLC, + IPA_ENABLE_DEFRAMING_HDLC, + IPA_DMA, +}; + +/** + * enum ipa_aggr_en_type - aggregation setting type in IPA + * end-point + */ +enum ipa_aggr_en_type { + IPA_BYPASS_AGGR, + IPA_ENABLE_AGGR, + IPA_ENABLE_DEAGGR, +}; + +/** + * enum ipa_aggr_type - type of aggregation in IPA end-point + */ +enum ipa_aggr_type { + IPA_MBIM_16 = 0, + IPA_HDLC = 1, + IPA_TLP = 2, + IPA_RNDIS = 3, + IPA_GENERIC = 4, + IPA_COALESCE = 5, + IPA_QCMAP = 6, +}; + +/** + * enum ipa_aggr_mode - global aggregation mode + */ +enum ipa_aggr_mode { + IPA_MBIM_AGGR, + IPA_QCNCM_AGGR, +}; + +/** + * enum ipa_dp_evt_type - type of event client callback is + * invoked for on data path + * @IPA_RECEIVE: data is struct sk_buff + * @IPA_WRITE_DONE: data is struct sk_buff + */ +enum ipa_dp_evt_type { + IPA_RECEIVE, + IPA_WRITE_DONE, +}; + +/** + * enum hdr_total_len_or_pad_type - type of value held by TOTAL_LEN_OR_PAD + * field in header configuration register. + * @IPA_HDR_PAD: field is used as padding length + * @IPA_HDR_TOTAL_LEN: field is used as total length + */ +enum hdr_total_len_or_pad_type { + IPA_HDR_PAD = 0, + IPA_HDR_TOTAL_LEN = 1, +}; + +/** + * struct ipa_ep_cfg_nat - NAT configuration in IPA end-point + * @nat_en: This defines the default NAT mode for the pipe: in case of + * filter miss - the default NAT mode defines the NATing operation + * on the packet. Valid for Input Pipes only (IPA consumer) + * @nat_exc_suppress: 1 - NAT exception is supressed and packet will be + * routed using configured routing tables. + * 0 - NAT exception is allowed and packets will be routed to exception + * pipe. Valid for input pipes only (IPA consumer) + */ +struct ipa_ep_cfg_nat { + enum ipa_nat_en_type nat_en; + bool nat_exc_suppress; +}; + +/** + * struct ipa_ep_cfg_conn_track - IPv6 Connection tracking configuration in + * IPA end-point + * @conn_track_en: Defines speculative conn_track action, means if specific + * pipe needs to have UL/DL IPv6 Connection Tracking or Bypass + * IPv6 Connection Tracking. 0: Bypass IPv6 Connection Tracking + * 1: IPv6 UL/DL Connection Tracking. + * Valid for Input Pipes only (IPA consumer) + */ +struct ipa_ep_cfg_conn_track { + enum ipa_ipv6ct_en_type conn_track_en; +}; + +/** + * struct ipa_ep_cfg_hdr - header configuration in IPA end-point + * + * @hdr_len:Header length in bytes to be added/removed. Assuming + * header len is constant per endpoint. Valid for + * both Input and Output Pipes + * @hdr_ofst_metadata_valid: 0: Metadata_Ofst value is invalid, i.e., no + * metadata within header. + * 1: Metadata_Ofst value is valid, i.e., metadata + * within header is in offset Metadata_Ofst Valid + * for Input Pipes only (IPA Consumer) (for output + * pipes, metadata already set within the header) + * @hdr_ofst_metadata: Offset within header in which metadata resides + * Size of metadata - 4bytes + * Example - Stream ID/SSID/mux ID. + * Valid for Input Pipes only (IPA Consumer) (for output + * pipes, metadata already set within the header) + * @hdr_additional_const_len: Defines the constant length that should be added + * to the payload length in order for IPA to update + * correctly the length field within the header + * (valid only in case Hdr_Ofst_Pkt_Size_Valid=1) + * Valid for Output Pipes (IPA Producer) + * Starting IPA4.5, this field in H/W requires more bits + * to support larger range, but no spare bits to use. + * So the MSB part is done thourgh the EXT register. + * When accessing this register, need to access the EXT + * register as well. + * @hdr_ofst_pkt_size_valid: 0: Hdr_Ofst_Pkt_Size value is invalid, i.e., no + * length field within the inserted header + * 1: Hdr_Ofst_Pkt_Size value is valid, i.e., a + * packet length field resides within the header + * Valid for Output Pipes (IPA Producer) + * @hdr_ofst_pkt_size: Offset within header in which packet size reside. Upon + * Header Insertion, IPA will update this field within the + * header with the packet length . Assumption is that + * header length field size is constant and is 2Bytes + * Valid for Output Pipes (IPA Producer) + * Starting IPA4.5, this field in H/W requires more bits + * to support larger range, but no spare bits to use. + * So the MSB part is done thourgh the EXT register. + * When accessing this register, need to access the EXT + * register as well. + * @hdr_a5_mux: Determines whether A5 Mux header should be added to the packet. + * This bit is valid only when Hdr_En=01(Header Insertion) + * SW should set this bit for IPA-to-A5 pipes. + * 0: Do not insert A5 Mux Header + * 1: Insert A5 Mux Header + * Valid for Output Pipes (IPA Producer) + * @hdr_remove_additional: bool switch, remove more of the header + * based on the aggregation configuration (register + * HDR_LEN_INC_DEAGG_HDR) + * @hdr_metadata_reg_valid: bool switch, metadata from + * register INIT_HDR_METADATA_n is valid. + * (relevant only for IPA Consumer pipes) + * Starting IPA4.5, this parameter is irrelevant and H/W + * assumes it is always valid. + */ +struct ipa_ep_cfg_hdr { + u32 hdr_len; + u32 hdr_ofst_metadata_valid; + u32 hdr_ofst_metadata; + u32 hdr_additional_const_len; + u32 hdr_ofst_pkt_size_valid; + u32 hdr_ofst_pkt_size; + u32 hdr_a5_mux; + u32 hdr_remove_additional; + u32 hdr_metadata_reg_valid; +}; + +/** + * struct ipa_ep_cfg_hdr_ext - extended header configuration in IPA end-point + * @hdr_pad_to_alignment: Pad packet to specified alignment + * (2^pad to alignment value), i.e. value of 3 means pad to 2^3 = 8 bytes + * alignment. Alignment is to 0,2 up to 32 bytes (IPAv2 does not support 64 + * byte alignment). Valid for Output Pipes only (IPA Producer). + * @hdr_total_len_or_pad_offset: Offset to length field containing either + * total length or pad length, per hdr_total_len_or_pad config + * @hdr_payload_len_inc_padding: 0-IPA_ENDP_INIT_HDR_n's + * HDR_OFST_PKT_SIZE does + * not includes padding bytes size, payload_len = packet length, + * 1-IPA_ENDP_INIT_HDR_n's HDR_OFST_PKT_SIZE includes + * padding bytes size, payload_len = packet length + padding + * @hdr_total_len_or_pad: field is used as PAD length ot as Total length + * (header + packet + padding) + * @hdr_total_len_or_pad_valid: 0-Ignore TOTAL_LEN_OR_PAD field, 1-Process + * TOTAL_LEN_OR_PAD field + * @hdr_little_endian: 0-Big Endian, 1-Little Endian + * @hdr: The header structure. Used starting IPA4.5 where part of the info + * at the header structure is implemented via the EXT register at the H/W + * @hdr_bytes_to_remove_valid: 0-Ignore hdr_bytes_to_remove field, 1-Process + * hdr_bytes_to_remove field + * @hdr_bytes_to_remove: desired bytes to remove from top of the packet for + * partial L2 header retention + */ +struct ipa_ep_cfg_hdr_ext { + u32 hdr_pad_to_alignment; + u32 hdr_total_len_or_pad_offset; + bool hdr_payload_len_inc_padding; + enum hdr_total_len_or_pad_type hdr_total_len_or_pad; + bool hdr_total_len_or_pad_valid; + bool hdr_little_endian; + struct ipa_ep_cfg_hdr *hdr; + bool hdr_bytes_to_remove_valid; + u32 hdr_bytes_to_remove; +}; + +/** + * struct ipa_ep_cfg_mode - mode configuration in IPA end-point + * @mode: Valid for Input Pipes only (IPA Consumer) + * @dst: This parameter specifies the output pipe to which the packets + * will be routed to. + * This parameter is valid for Mode=DMA and not valid for + * Mode=Basic + * Valid for Input Pipes only (IPA Consumer) + */ +struct ipa_ep_cfg_mode { + enum ipa_mode_type mode; + enum ipa_client_type dst; +}; + +/** + * struct ipa_ep_cfg_aggr - aggregation configuration in IPA end-point + * + * @aggr_en: Valid for both Input and Output Pipes + * @aggr: aggregation type (Valid for both Input and Output Pipes) + * @aggr_byte_limit: Limit of aggregated packet size in KB (<=32KB) When set + * to 0, there is no size limitation on the aggregation. + * When both, Aggr_Byte_Limit and Aggr_Time_Limit are set + * to 0, there is no aggregation, every packet is sent + * independently according to the aggregation structure + * Valid for Output Pipes only (IPA Producer ) + * @aggr_time_limit: Timer to close aggregated packet When set to 0, + * there is no time limitation on the aggregation. When + * both, Aggr_Byte_Limit and Aggr_Time_Limit are set to 0, + * there is no aggregation, every packet is sent + * independently according to the aggregation structure + * Valid for Output Pipes only (IPA Producer). + * Time unit is -->> usec <<-- + * @aggr_pkt_limit: Defines if EOF close aggregation or not. if set to false + * HW closes aggregation (sends EOT) only based on its + * aggregation config (byte/time limit, etc). if set to + * true EOF closes aggregation in addition to HW based + * aggregation closure. Valid for Output Pipes only (IPA + * Producer). EOF affects only Pipes configured for + * generic aggregation. + * @aggr_hard_byte_limit_en: If set to 1, byte-limit aggregation for this + * pipe will apply a hard-limit behavior which will not + * allow frames to be closed with more than byte-limit + * bytes. If set to 0, previous byte-limit behavior + * will apply - frames close once a packet causes the + * accumulated byte-count to cross the byte-limit + * threshold (closed frame will contain that packet). + * @aggr_sw_eof_active: 0: EOF does not close aggregation. HW closes aggregation + * (sends EOT) only based on its aggregation config + * (byte/time limit, etc). + * 1: EOF closes aggregation in addition to HW based + * aggregation closure. Valid for Output Pipes only (IPA + * Producer). EOF affects only Pipes configured for generic + * aggregation. + * @pulse_generator: Pulse generator number to be used. + * For internal use. + * Supported starting IPA4.5. + * @scaled_time: Time limit in accordance to the pulse generator + * granularity. + * For internal use + * Supported starting IPA4.5 + * @aggr_coal_l2: enable L2 coalescing on the specifid dest pipe, + * work only if AGGR_TYPE set to AGGR_TYPE_COALESCING. + * Supported starting IPA5.5 + */ +struct ipa_ep_cfg_aggr { + enum ipa_aggr_en_type aggr_en; + enum ipa_aggr_type aggr; + u32 aggr_byte_limit; + u32 aggr_time_limit; + u32 aggr_pkt_limit; + u32 aggr_hard_byte_limit_en; + bool aggr_sw_eof_active; + u8 pulse_generator; + u8 scaled_time; + bool aggr_coal_l2; +}; + +/** + * struct ipa_ep_cfg_route - route configuration in IPA end-point + * @rt_tbl_hdl: Defines the default routing table index to be used in case there + * is no filter rule matching, valid for Input Pipes only (IPA + * Consumer). Clients should set this to 0 which will cause default + * v4 and v6 routes setup internally by IPA driver to be used for + * this end-point + */ +struct ipa_ep_cfg_route { + u32 rt_tbl_hdl; +}; + +/** + * struct ipa_ep_cfg_holb - head of line blocking configuration in IPA end-point + * @en: enable(1 => ok to drop pkt)/disable(0 => never drop pkt) + * @tmr_val: duration in units of 128 IPA clk clock cyles [0,511], 1 clk=1.28us + * IPAv2.5 support 32 bit HOLB timeout value, previous versions + * supports 16 bit + * IPAv4.2: splitting timer value into 2 fields. Timer value is: + * BASE_VALUE * (2^SCALE) + * IPA4.5: tmr_val is in -->>msec<<--. Range is dynamic based + * on H/W configuration. (IPA4.5 absolute maximum is 0.65535*31 -> ~20sec). + * @base_val : IPA4.2 only field. base value of the timer. + * @scale : IPA4.2 only field. scale value for timer. + * @pulse_generator: Pulse generator number to be used. + * For internal use. + * Supported starting IPA4.5. + * @scaled_time: Time limit in accordance to the pulse generator granularity + * For internal use + * Supported starting IPA4.5 + */ +struct ipa_ep_cfg_holb { + u32 tmr_val; + u32 base_val; + u32 scale; + u16 en; + u8 pulse_generator; + u8 scaled_time; +}; + +/** + * struct ipa_ep_cfg_deaggr - deaggregation configuration in IPA end-point + * @deaggr_hdr_len: Deaggregation Header length in bytes. Valid only for Input + * Pipes, which are configured for 'Generic' deaggregation. + * @syspipe_err_detection - If set to 1, enables error detection for + * de-aggregration. Valid only for Input Pipes, which are configured + * for 'Generic' deaggregation. + * Note: if this bit is set, de-aggregated frames must be contiguous + * in memory. + * @packet_offset_valid: - 0: PACKET_OFFSET is not used, 1: PACKET_OFFSET is + * used. + * @packet_offset_location: Location of packet offset field, which specifies + * the offset to the packet from the start of the packet offset field. + * @ignore_min_pkt_err - Ignore packets smaller than header. This is intended + * for use in RNDIS de-aggregated pipes, to silently ignore a redundant + * 1-byte trailer in MSFT implementation. + * @max_packet_len: DEAGGR Max Packet Length in Bytes. A Packet with higher + * size wil be treated as an error. 0 - Packet Length is not Bound, + * IPA should not check for a Max Packet Length. + */ +struct ipa_ep_cfg_deaggr { + u32 deaggr_hdr_len; + bool syspipe_err_detection; + bool packet_offset_valid; + u32 packet_offset_location; + bool ignore_min_pkt_err; + u32 max_packet_len; +}; + +/** + * enum ipa_cs_offload - checksum offload setting + */ +enum ipa_cs_offload { + IPA_DISABLE_CS_OFFLOAD, + /* + * For enum value = 1, we check the csum required/valid bit which is the + * same bit used for both DL and UL but have different meanings. + * For UL pipe, HW checks if it needs to perform Csum caluclation. + * For DL pipe, HW checks if the csum is valid or invalid + */ + IPA_ENABLE_CS_OFFLOAD_UL, + IPA_ENABLE_CS_DL_QMAP = IPA_ENABLE_CS_OFFLOAD_UL, + IPA_ENABLE_CS_OFFLOAD_DL, + IPA_CS_RSVD +}; + +/** + * struct ipa_ep_cfg_cfg - IPA ENDP_INIT Configuration register + * @frag_offload_en: - 0 - IP packet fragment handling is disabled. IP packet + * fragments should be sent to SW. SW is responsible for + * configuring filter rules, and IP packet filter exception should be + * used to send all fragments to SW. 1 - IP packet fragment + * handling is enabled. IPA checks for fragments and uses frag + * rules table for processing fragments. Valid only for Input Pipes + * (IPA Consumer) + * @cs_offload_en: Checksum offload enable: 00: Disable checksum offload, 01: + * Enable checksum calculation offload (UL) - For output pipe + * (IPA producer) specifies that checksum trailer is to be added. + * For input pipe (IPA consumer) specifies presence of checksum + * header and IPA checksum calculation accordingly. 10: Enable + * checksum calculation offload (DL) - For output pipe (IPA + * producer) specifies that checksum trailer is to be added. For + * input pipe (IPA consumer) specifies IPA checksum calculation. + * 11: Reserved + * @cs_metadata_hdr_offset: Offset in Words (4 bytes) within header in which + * checksum metadata info header (4 bytes) starts (UL). Values are 0-15, which + * mean 0 - 60 byte checksum header offset. Valid for input + * pipes only (IPA consumer) + * @gen_qmb_master_sel: Select bit for ENDP GEN-QMB master. This is used to + * separate DDR & PCIe transactions in-order to limit them as + * a group (using MAX_WRITES/READS limiation). Valid for input and + * output pipes (IPA consumer+producer) + * @pipe_replicate_en: 1 - For consumer pipe - consumer DPL will be active. + * For producer pipe - producer DPL will be active. + * 0 - packet replication disabled for both consumer and producer pipe. + * Supported from IPA5.5 onwards. + */ +struct ipa_ep_cfg_cfg { + bool frag_offload_en; + enum ipa_cs_offload cs_offload_en; + u8 cs_metadata_hdr_offset; + u8 gen_qmb_master_sel; + u8 tx_instance; + bool pipe_replicate_en; +}; + +/** + * struct ipa_ep_cfg_prod_cfg - IPA ENDP_INIT Producer Configuration register + * @tx_instance: - 0 - select TX_0 instance. + * 1 - select TX_1 instance. + * @tsp_enable: boolean to indicate TSP-enablement per producer pipe. + * @max_output_size_drop_enable: enable policing by max output size for TSP + * feature. In case of TSP_ENABLE == 1 + valid egress_tc, max output size + * policing will be valid regardless to this bit. + * @tsp_idx: TSP producer-index. Controls pointer to producer-rate database. + * Valid only when TSP_ENABLE field is set. Value should be unique. + * @max_output_size: max output size allowed per producer. Value is in 64-byte + * resolution for TSP feature + * @egress_tc_lowest: Lowest egress traffic-class index assignes to this + * producer. + * @egress_tc_highest: Highest egress traffic-class index assignes to this + * producer. + */ +struct ipa_ep_cfg_prod_cfg { + u8 tx_instance; + bool tsp_enable; + bool max_output_size_drop_enable; + u8 tsp_idx; + u8 max_output_size; + u8 egress_tc_lowest; + u8 egress_tc_highest; +}; + +/** + * struct ipa_ep_cfg_metadata_mask - Endpoint initialization hdr metadata mask + * @metadata_mask: Mask specifying which metadata bits to write to + * IPA_ENDP_INIT_HDR_n.s HDR_OFST_METADATA. Only + * masked metadata bits (set to 1) will be written. Valid for Output + * Pipes only (IPA Producer) + */ +struct ipa_ep_cfg_metadata_mask { + u32 metadata_mask; +}; + +/** + * struct ipa_ep_cfg_metadata - Metadata configuration in IPA end-point + * @md: This defines the metadata from tx data descriptor + * @qmap_id: qmap id + */ +struct ipa_ep_cfg_metadata { + u32 qmap_id; +}; + +/** + * struct ipa_ep_cfg_seq - HPS/DPS sequencer type configuration in IPA end-point + * @set_dynamic: 0 - HPS/DPS seq type is configured statically, + * 1 - HPS/DPS seq type is set to seq_type + * @seq_type: HPS/DPS sequencer type configuration + */ +struct ipa_ep_cfg_seq { + bool set_dynamic; + int seq_type; +}; + +/** + * struct ipa_ep_cfg_ulso - ULSO configurations + * @ipid_min_max_idx: A value in the range [0, 2]. Determines the registers + * pair from which to read the minimum and maximum of IPv4 packets ID. It + * is set to 0 as this range is platform specific and there is no need for + * more than one pair values for this range. The minimum and maximum values + * are taken from the device tree in pre_init and are stored in dedicated + * registers. + * @is_ulso_pipe: Indicates whether the pipe is in ulso operation mode. + */ +struct ipa_ep_cfg_ulso { + int ipid_min_max_idx; + bool is_ulso_pipe; +}; + +/** + * struct ipa_ep_cfg - configuration of IPA end-point + * @nat: NAT parameters + * @conn_track: IPv6CT parameters + * @hdr: Header parameters + * @hdr_ext: Extended header parameters + * @mode: Mode parameters + * @aggr: Aggregation parameters + * @deaggr: Deaggregation params + * @route: Routing parameters + * @cfg: Configuration register data + * @metadata_mask: Hdr metadata mask + * @meta: Metadata + * @seq: HPS/DPS sequencers configuration + * @ulso: ULSO configuration + * @prod_cfg: Producer specific Configuration register data + */ +struct ipa_ep_cfg { + struct ipa_ep_cfg_nat nat; + struct ipa_ep_cfg_conn_track conn_track; + struct ipa_ep_cfg_hdr hdr; + struct ipa_ep_cfg_hdr_ext hdr_ext; + struct ipa_ep_cfg_mode mode; + struct ipa_ep_cfg_aggr aggr; + struct ipa_ep_cfg_deaggr deaggr; + struct ipa_ep_cfg_route route; + struct ipa_ep_cfg_cfg cfg; + struct ipa_ep_cfg_metadata_mask metadata_mask; + struct ipa_ep_cfg_metadata meta; + struct ipa_ep_cfg_seq seq; + struct ipa_ep_cfg_ulso ulso; + struct ipa_ep_cfg_prod_cfg prod_cfg; +}; + +/** + * struct ipa_ep_cfg_ctrl - Control configuration in IPA end-point + * @ipa_ep_suspend: 0 - ENDP is enabled, 1 - ENDP is suspended (disabled). + * Valid for PROD Endpoints + * @ipa_ep_delay: 0 - ENDP is free-running, 1 - ENDP is delayed. + * SW controls the data flow of an endpoint usind this bit. + * Valid for CONS Endpoints + */ +struct ipa_ep_cfg_ctrl { + bool ipa_ep_suspend; + bool ipa_ep_delay; +}; + +/** + * x should be in bytes + */ +#define IPA_NUM_OF_FIFO_DESC(x) (x/sizeof(struct sps_iovec)) +typedef void (*ipa_notify_cb)(void *priv, enum ipa_dp_evt_type evt, + unsigned long data); + +/** + * enum ipa_wdi_meter_evt_type - type of event client callback is + * for AP+STA mode metering + * @IPA_GET_WDI_SAP_STATS: get IPA_stats betwen SAP and STA - + * use ipa_get_wdi_sap_stats structure + * @IPA_SET_WIFI_QUOTA: set quota limit on STA - + * use ipa_set_wifi_quota structure + * @IPA_SET_WLAN_BW: set wlan BW - + * use ipa_set_wlan_bw structure + */ +enum ipa_wdi_meter_evt_type { + IPA_GET_WDI_SAP_STATS, + IPA_SET_WIFI_QUOTA, + IPA_INFORM_WLAN_BW, +}; + +struct ipa_get_wdi_sap_stats { + /* indicate to reset stats after query */ + uint8_t reset_stats; + /* indicate valid stats from wlan-fw */ + uint8_t stats_valid; + /* Tx: SAP->STA */ + uint64_t ipv4_tx_packets; + uint64_t ipv4_tx_bytes; + /* Rx: STA->SAP */ + uint64_t ipv4_rx_packets; + uint64_t ipv4_rx_bytes; + uint64_t ipv6_tx_packets; + uint64_t ipv6_tx_bytes; + uint64_t ipv6_rx_packets; + uint64_t ipv6_rx_bytes; +}; + +/** + * struct ipa_set_wifi_quota - structure used for + * IPA_SET_WIFI_QUOTA. + * + * @quota_bytes: Quota (in bytes) for the STA interface. + * @set_quota: Indicate whether to set the quota (use 1) or + * unset the quota. + * + */ +struct ipa_set_wifi_quota { + uint64_t quota_bytes; + uint8_t set_quota; + /* indicate valid quota set from wlan-fw */ + uint8_t set_valid; +}; + +/** + * struct ipa_inform_wlan_bw - structure used for + * IPA_INFORM_WLAN_BW. + * + * @index: Indicate which bw-index hit + * @throughput: throughput usage + * + */ +struct ipa_inform_wlan_bw { + uint8_t index; + uint64_t throughput; +}; + +typedef void (*ipa_wdi_meter_notifier_cb)(enum ipa_wdi_meter_evt_type evt, + void *data); + + +/** + * struct ipa_tx_intf - interface tx properties + * @num_props: number of tx properties + * @prop: the tx properties array + */ +struct ipa_tx_intf { + u32 num_props; + struct ipa_ioc_tx_intf_prop *prop; +}; + +/** + * struct ipa_rx_intf - interface rx properties + * @num_props: number of rx properties + * @prop: the rx properties array + */ +struct ipa_rx_intf { + u32 num_props; + struct ipa_ioc_rx_intf_prop *prop; +}; + +/** + * struct ipa_ext_intf - interface ext properties + * @excp_pipe_valid: is next field valid? + * @excp_pipe: exception packets should be routed to this pipe + * @num_props: number of ext properties + * @prop: the ext properties array + */ +struct ipa_ext_intf { + bool excp_pipe_valid; + enum ipa_client_type excp_pipe; + u32 num_props; + struct ipa_ioc_ext_intf_prop *prop; +}; + +/** + * struct ipa_sys_connect_params - information needed to setup an IPA end-point + * in system-BAM mode + * @ipa_ep_cfg: IPA EP configuration + * @client: the type of client who "owns" the EP + * @desc_fifo_sz: size of desc FIFO. This number is used to allocate the desc + * fifo for BAM. For GSI, this size is used by IPA driver as a + * baseline to calculate the GSI ring size in the following way: + * For PROD pipes, GSI ring is 4 * desc_fifo_sz. + For PROD pipes, GSI ring is 2 * desc_fifo_sz. + * @priv: callback cookie + * @notify: callback + * priv - callback cookie + * evt - type of event + * data - data relevant to event. May not be valid. See event_type + * enum for valid cases. + * @skip_ep_cfg: boolean field that determines if EP should be configured + * by IPA driver + * @keep_ipa_awake: when true, IPA will not be clock gated + * @napi_enabled: when true, IPA call client callback to start polling + * @bypass_agg: when true, IPA bypasses the aggregation + * @int_modt: GSI event ring interrupt moderation time + * cycles base interrupt moderation (32KHz clock) + * @int_modc: GSI event ring interrupt moderation packet counter + * @buff_size: Actual buff size of rx_pkt + * @ext_ioctl_v2: Flag to determine whether ioctl_v2 received + */ +struct ipa_sys_connect_params { + struct ipa_ep_cfg ipa_ep_cfg; + enum ipa_client_type client; + u32 desc_fifo_sz; + void *priv; + ipa_notify_cb notify; + bool skip_ep_cfg; + bool keep_ipa_awake; + struct napi_struct *napi_obj; + bool recycle_enabled; + bool bypass_agg; + u32 int_modt; + u32 int_modc; + u32 buff_size; + bool ext_ioctl_v2; +}; + +/** + * struct ipa_tx_meta - metadata for the TX packet + * @dma_address: dma mapped address of TX packet + * @dma_address_valid: is above field valid? + */ +struct ipa_tx_meta { + u8 pkt_init_dst_ep; + bool pkt_init_dst_ep_valid; + bool pkt_init_dst_ep_remote; + dma_addr_t dma_address; + bool dma_address_valid; +}; + +/** + * typedef ipa_msg_free_fn - callback function + * @param buff - [in] the message payload to free + * @param len - [in] size of message payload + * @param type - [in] the message type + * + * Message callback registered by kernel client with IPA driver to + * free message payload after IPA driver processing is complete + * + * No return value + */ +typedef void (*ipa_msg_free_fn)(void *buff, u32 len, u32 type); + +/** + * typedef ipa_msg_pull_fn - callback function + * @param buff - [in] where to copy message payload + * @param len - [in] size of buffer to copy payload into + * @param type - [in] the message type + * + * Message callback registered by kernel client with IPA driver for + * IPA driver to pull messages from the kernel client upon demand from + * user-space + * + * Returns how many bytes were copied into the buffer. + */ +typedef int (*ipa_msg_pull_fn)(void *buff, u32 len, u32 type); + +/** + * enum ipa_voltage_level - IPA Voltage levels + */ +enum ipa_voltage_level { + IPA_VOLTAGE_UNSPECIFIED, + IPA_VOLTAGE_SVS2 = IPA_VOLTAGE_UNSPECIFIED, + IPA_VOLTAGE_SVS, + IPA_VOLTAGE_NOMINAL, + IPA_VOLTAGE_TURBO, + IPA_VOLTAGE_MAX, +}; + +/** + * enum ipa_rm_event - IPA RM events + * + * Indicate the resource state change + */ +enum ipa_rm_event { + IPA_RM_RESOURCE_GRANTED, + IPA_RM_RESOURCE_RELEASED +}; + +typedef void (*ipa_rm_notify_cb)(void *user_data, + enum ipa_rm_event event, + unsigned long data); +/** + * struct ipa_rm_register_params - information needed to + * register IPA RM client with IPA RM + * + * @user_data: IPA RM client provided information + * to be passed to notify_cb callback below + * @notify_cb: callback which is called by resource + * to notify the IPA RM client about its state + * change IPA RM client is expected to perform non + * blocking operations only in notify_cb and + * release notification context as soon as + * possible. + */ +struct ipa_rm_register_params { + void *user_data; + ipa_rm_notify_cb notify_cb; +}; + +/** + * struct ipa_rm_create_params - information needed to initialize + * the resource + * @name: resource name + * @floor_voltage: floor voltage needed for client to operate in maximum + * bandwidth. + * @reg_params: register parameters, contains are ignored + * for consumer resource NULL should be provided + * for consumer resource + * @request_resource: function which should be called to request resource, + * NULL should be provided for producer resource + * @release_resource: function which should be called to release resource, + * NULL should be provided for producer resource + * + * IPA RM client is expected to perform non blocking operations only + * in request_resource and release_resource functions and + * release notification context as soon as possible. + */ +struct ipa_rm_create_params { + enum ipa_rm_resource_name name; + enum ipa_voltage_level floor_voltage; + struct ipa_rm_register_params reg_params; + int (*request_resource)(void); + int (*release_resource)(void); +}; + +/** + * struct ipa_rm_perf_profile - information regarding IPA RM client performance + * profile + * + * @max_bandwidth_mbps: maximum bandwidth need of the client in Mbps + */ +struct ipa_rm_perf_profile { + u32 max_supported_bandwidth_mbps; +}; + +#define A2_MUX_HDR_NAME_V4_PREF "dmux_hdr_v4_" +#define A2_MUX_HDR_NAME_V6_PREF "dmux_hdr_v6_" + +/** + * struct ipa_tx_data_desc - information needed + * to send data packet to HW link: link to data descriptors + * priv: client specific private data + * @pyld_buffer: pointer to the data buffer that holds frame + * @pyld_len: length of the data packet + */ +struct ipa_tx_data_desc { + struct list_head link; + void *priv; + void *pyld_buffer; + u16 pyld_len; +}; + +/** + * struct ipa_rx_data - information needed + * to send to wlan driver on receiving data from ipa hw + * @skb: skb + * @dma_addr: DMA address of this Rx packet + */ +struct ipa_rx_data { + struct sk_buff *skb; + dma_addr_t dma_addr; +}; + +/** + * enum ipa_irq_type - IPA Interrupt Type + * Used to register handlers for IPA interrupts + * + * Below enum is a logical mapping and not the actual interrupt bit in HW + */ +enum ipa_irq_type { + IPA_BAD_SNOC_ACCESS_IRQ, + IPA_UC_IRQ_0, + IPA_UC_IRQ_1, + IPA_UC_IRQ_2, + IPA_UC_IRQ_3, + IPA_UC_IN_Q_NOT_EMPTY_IRQ, + IPA_UC_RX_CMD_Q_NOT_FULL_IRQ, + IPA_PROC_TO_UC_ACK_Q_NOT_EMPTY_IRQ, + IPA_RX_ERR_IRQ, + IPA_DEAGGR_ERR_IRQ, + IPA_TX_ERR_IRQ, + IPA_STEP_MODE_IRQ, + IPA_PROC_ERR_IRQ, + IPA_TX_SUSPEND_IRQ, + IPA_TX_HOLB_DROP_IRQ, + IPA_BAM_GSI_IDLE_IRQ, + IPA_PIPE_YELLOW_MARKER_BELOW_IRQ, + IPA_PIPE_RED_MARKER_BELOW_IRQ, + IPA_PIPE_YELLOW_MARKER_ABOVE_IRQ, + IPA_PIPE_RED_MARKER_ABOVE_IRQ, + IPA_UCP_IRQ, + IPA_DCMP_IRQ, + IPA_GSI_EE_IRQ, + IPA_GSI_IPA_IF_TLV_RCVD_IRQ, + IPA_GSI_UC_IRQ, + IPA_TLV_LEN_MIN_DSM_IRQ, + IPA_DRBIP_PKT_EXCEED_MAX_SIZE_IRQ, + IPA_DRBIP_DATA_SCTR_CFG_ERROR_IRQ, + IPA_DRBIP_IMM_CMD_NO_FLSH_HZRD_IRQ, + IPA_IRQ_MAX +}; + +/** + * typedef ipa_irq_handler_t - irq handler/callback type + * @param ipa_irq_type - [in] interrupt type + * @param private_data - [in, out] the client private data + * @param interrupt_data - [out] interrupt information data + * + * callback registered by ipa_add_interrupt_handler function to + * handle a specific interrupt type + * + * No return value + */ +typedef void (*ipa_irq_handler_t)(enum ipa_irq_type interrupt, + void *private_data, + void *interrupt_data); + +/** + * struct IpaHwBamStats_t - Structure holding the BAM statistics + * + * @bamFifoFull : Number of times Bam Fifo got full - For In Ch: Good, + * For Out Ch: Bad + * @bamFifoEmpty : Number of times Bam Fifo got empty - For In Ch: Bad, + * For Out Ch: Good + * @bamFifoUsageHigh : Number of times Bam fifo usage went above 75% - + * For In Ch: Good, For Out Ch: Bad + * @bamFifoUsageLow : Number of times Bam fifo usage went below 25% - + * For In Ch: Bad, For Out Ch: Good + */ +struct IpaHwBamStats_t { + u32 bamFifoFull; + u32 bamFifoEmpty; + u32 bamFifoUsageHigh; + u32 bamFifoUsageLow; + u32 bamUtilCount; +} __packed; + +/** + * struct IpaHwRingStats_t - Structure holding the Ring statistics + * + * @ringFull : Number of times Transfer Ring got full - For In Ch: Good, + * For Out Ch: Bad + * @ringEmpty : Number of times Transfer Ring got empty - For In Ch: Bad, + * For Out Ch: Good + * @ringUsageHigh : Number of times Transfer Ring usage went above 75% - + * For In Ch: Good, For Out Ch: Bad + * @ringUsageLow : Number of times Transfer Ring usage went below 25% - + * For In Ch: Bad, For Out Ch: Good + */ +struct IpaHwRingStats_t { + u32 ringFull; + u32 ringEmpty; + u32 ringUsageHigh; + u32 ringUsageLow; + u32 RingUtilCount; +} __packed; + +/** + * struct ipa_uc_dbg_rtk_ring_stats - uC dbg stats info for RTK + * offloading protocol + * @commStats: common stats + * @trCount: transfer ring count + * @erCount: event ring count + * @totalAosCount: total AoS completion count + * @busyTime: total busy time + */ +struct ipa_uc_dbg_rtk_ring_stats { + struct IpaHwRingStats_t commStats; + u32 trCount; + u32 erCount; + u32 totalAosCount; + u64 busyTime; +} __packed; + +/** + * struct IpaHwStatsWDIRxInfoData_t - Structure holding the WDI Rx channel + * structures + * + * @max_outstanding_pkts : Number of outstanding packets in Rx Ring + * @num_pkts_processed : Number of packets processed - cumulative + * @rx_ring_rp_value : Read pointer last advertized to the WLAN FW + * @rx_ind_ring_stats : Ring info + * @bam_stats : BAM info + * @num_bam_int_handled : Number of Bam Interrupts handled by FW + * @num_db : Number of times the doorbell was rung + * @num_unexpected_db : Number of unexpected doorbells + * @num_pkts_in_dis_uninit_state : number of completions we + * received in disabled or uninitialized state + * @num_ic_inj_vdev_change : Number of times the Imm Cmd is + * injected due to vdev_id change + * @num_ic_inj_fw_desc_change : Number of times the Imm Cmd is + * injected due to fw_desc change + * @num_qmb_int_handled : Number of QMB interrupts handled + */ +struct IpaHwStatsWDIRxInfoData_t { + u32 max_outstanding_pkts; + u32 num_pkts_processed; + u32 rx_ring_rp_value; + struct IpaHwRingStats_t rx_ind_ring_stats; + struct IpaHwBamStats_t bam_stats; + u32 num_bam_int_handled; + u32 num_db; + u32 num_unexpected_db; + u32 num_pkts_in_dis_uninit_state; + u32 num_ic_inj_vdev_change; + u32 num_ic_inj_fw_desc_change; + u32 num_qmb_int_handled; + u32 reserved1; + u32 reserved2; +} __packed; + +/** + * struct IpaHwStatsWDITxInfoData_t - Structure holding the WDI Tx channel + * structures + * + * @num_pkts_processed : Number of packets processed - cumulative + * @copy_engine_doorbell_value : latest value of doorbell written to copy engine + * @num_db_fired : Number of DB from uC FW to Copy engine + * @tx_comp_ring_stats : ring info + * @bam_stats : BAM info + * @num_db : Number of times the doorbell was rung + * @num_unexpected_db : Number of unexpected doorbells + * @num_bam_int_handled : Number of Bam Interrupts handled by FW + * @num_bam_int_in_non_running_state : Number of Bam interrupts while not in + * Running state + * @num_qmb_int_handled : Number of QMB interrupts handled + */ +struct IpaHwStatsWDITxInfoData_t { + u32 num_pkts_processed; + u32 copy_engine_doorbell_value; + u32 num_db_fired; + struct IpaHwRingStats_t tx_comp_ring_stats; + struct IpaHwBamStats_t bam_stats; + u32 num_db; + u32 num_unexpected_db; + u32 num_bam_int_handled; + u32 num_bam_int_in_non_running_state; + u32 num_qmb_int_handled; + u32 num_bam_int_handled_while_wait_for_bam; +} __packed; + +/** + * struct IpaHwStatsWDIInfoData_t - Structure holding the WDI channel structures + * + * @rx_ch_stats : RX stats + * @tx_ch_stats : TX stats + */ +struct IpaHwStatsWDIInfoData_t { + struct IpaHwStatsWDIRxInfoData_t rx_ch_stats; + struct IpaHwStatsWDITxInfoData_t tx_ch_stats; +} __packed; + + +/** + * struct ipa_wdi_ul_params - WDI_RX configuration + * @rdy_ring_base_pa: physical address of the base of the Rx ring (containing + * Rx buffers) + * @rdy_ring_size: size of the Rx ring in bytes + * @rdy_ring_rp_pa: physical address of the location through which IPA uc is + * reading (WDI-1.0) + * @rdy_comp_ring_base_pa: physical address of the base of the Rx completion + * ring (WDI-2.0) + * @rdy_comp_ring_wp_pa: physical address of the location through which IPA + * uc is writing (WDI-2.0) + * @rdy_comp_ring_size: size of the Rx_completion ring in bytes + * expected to communicate about the Read pointer into the Rx Ring + */ +struct ipa_wdi_ul_params { + phys_addr_t rdy_ring_base_pa; + u32 rdy_ring_size; + phys_addr_t rdy_ring_rp_pa; + phys_addr_t rdy_comp_ring_base_pa; + phys_addr_t rdy_comp_ring_wp_pa; + u32 rdy_comp_ring_size; + u32 *rdy_ring_rp_va; + u32 *rdy_comp_ring_wp_va; + bool is_txr_rn_db_pcie_addr; + bool is_evt_rn_db_pcie_addr; +}; + +/** + * struct ipa_wdi_ul_params_smmu - WDI_RX configuration (with WLAN SMMU) + * @rdy_ring: SG table describing the Rx ring (containing Rx buffers) + * @rdy_ring_size: size of the Rx ring in bytes + * @rdy_ring_rp_pa: physical address of the location through which IPA uc is + * expected to communicate about the Read pointer into the Rx Ring + */ +struct ipa_wdi_ul_params_smmu { + struct sg_table rdy_ring; + u32 rdy_ring_size; + phys_addr_t rdy_ring_rp_pa; + struct sg_table rdy_comp_ring; + phys_addr_t rdy_comp_ring_wp_pa; + u32 rdy_comp_ring_size; + u32 *rdy_ring_rp_va; + u32 *rdy_comp_ring_wp_va; + bool is_txr_rn_db_pcie_addr; + bool is_evt_rn_db_pcie_addr; +}; + +/** + * struct ipa_wdi_dl_params - WDI_TX configuration + * @comp_ring_base_pa: physical address of the base of the Tx completion ring + * @comp_ring_size: size of the Tx completion ring in bytes + * @ce_ring_base_pa: physical address of the base of the Copy Engine Source + * Ring + * @ce_door_bell_pa: physical address of the doorbell that the IPA uC has to + * write into to trigger the copy engine + * @ce_ring_size: Copy Engine Ring size in bytes + * @num_tx_buffers: Number of pkt buffers allocated + */ +struct ipa_wdi_dl_params { + phys_addr_t comp_ring_base_pa; + u32 comp_ring_size; + phys_addr_t ce_ring_base_pa; + phys_addr_t ce_door_bell_pa; + u32 ce_ring_size; + u32 num_tx_buffers; + bool is_txr_rn_db_pcie_addr; + bool is_evt_rn_db_pcie_addr; +}; + +/** + * struct ipa_wdi_dl_params_smmu - WDI_TX configuration (with WLAN SMMU) + * @comp_ring: SG table describing the Tx completion ring + * @comp_ring_size: size of the Tx completion ring in bytes + * @ce_ring: SG table describing the Copy Engine Source Ring + * @ce_door_bell_pa: physical address of the doorbell that the IPA uC has to + * write into to trigger the copy engine + * @ce_ring_size: Copy Engine Ring size in bytes + * @num_tx_buffers: Number of pkt buffers allocated + */ +struct ipa_wdi_dl_params_smmu { + struct sg_table comp_ring; + u32 comp_ring_size; + struct sg_table ce_ring; + phys_addr_t ce_door_bell_pa; + u32 ce_ring_size; + u32 num_tx_buffers; + bool is_txr_rn_db_pcie_addr; + bool is_evt_rn_db_pcie_addr; +}; + +/** + * struct ipa_wdi_in_params - information provided by WDI client + * @sys: IPA EP configuration info + * @ul: WDI_RX configuration info + * @dl: WDI_TX configuration info + * @ul_smmu: WDI_RX configuration info when WLAN uses SMMU + * @dl_smmu: WDI_TX configuration info when WLAN uses SMMU + * @smmu_enabled: true if WLAN uses SMMU + * @ipa_wdi_meter_notifier_cb: Get WDI stats and quato info + */ +struct ipa_wdi_in_params { + struct ipa_sys_connect_params sys; + union { + struct ipa_wdi_ul_params ul; + struct ipa_wdi_dl_params dl; + struct ipa_wdi_ul_params_smmu ul_smmu; + struct ipa_wdi_dl_params_smmu dl_smmu; + } u; + bool smmu_enabled; +#ifdef IPA_WAN_MSG_IPv6_ADDR_GW_LEN + ipa_wdi_meter_notifier_cb wdi_notify; +#endif +}; + +enum ipa_upstream_type { + IPA_UPSTEAM_MODEM = 1, + IPA_UPSTEAM_WLAN, + IPA_UPSTEAM_MAX +}; + +/** + * struct ipa_wdi_out_params - information provided to WDI client + * @uc_door_bell_pa: physical address of IPA uc doorbell + * @clnt_hdl: opaque handle assigned to client + */ +struct ipa_wdi_out_params { + phys_addr_t uc_door_bell_pa; + u32 clnt_hdl; +}; + +/** + * struct ipa_wdi_db_params - information provided to retrieve + * physical address of uC doorbell + * @client: type of "client" (IPA_CLIENT_WLAN#_PROD/CONS) + * @uc_door_bell_pa: physical address of IPA uc doorbell + */ +struct ipa_wdi_db_params { + enum ipa_client_type client; + phys_addr_t uc_door_bell_pa; +}; + +/** + * struct ipa_wdi_uc_ready_params - uC ready CB parameters + * @is_uC_ready: uC loaded or not + * @priv : callback cookie + * @notify: callback + */ +typedef void (*ipa_uc_ready_cb)(void *priv); +struct ipa_wdi_uc_ready_params { + bool is_uC_ready; + void *priv; + ipa_uc_ready_cb notify; +}; + +/** + * struct ipa_wdi_buffer_info - address info of a WLAN allocated buffer + * @pa: physical address of the buffer + * @iova: IOVA of the buffer as embedded inside the WDI descriptors + * @size: size in bytes of the buffer + * @result: result of map or unmap operations (out param) + * + * IPA driver will create/release IOMMU mapping in IPA SMMU from iova->pa + */ +struct ipa_wdi_buffer_info { + phys_addr_t pa; + unsigned long iova; + size_t size; + int result; +}; + +/** + * struct ipa_wdi_bw_info - address info of a WLAN allocated buffer + * @threshold: throughput wants to be monitored + * @num: number of threshold entries + * @stop: true to stop monitoring + * + * IPA driver will create/release IOMMU mapping in IPA SMMU from iova->pa + */ +struct ipa_wdi_bw_info { + uint64_t threshold[IPA_BW_THRESHOLD_MAX]; + int num; + bool stop; +}; + +/** + * struct ipa_wdi_tx_info - sw tx info from WLAN + * @sta_tx: sw tx stats on sta interface + * @ap_tx: sw tx stats on ap interface + * + * IPA driver will create/release IOMMU mapping in IPA SMMU from iova->pa + */ +struct ipa_wdi_tx_info { + uint64_t sta_tx; + uint64_t ap_tx; +}; + +/** + * struct ipa_gsi_ep_config - IPA GSI endpoint configurations + * + * @ipa_ep_num: IPA EP pipe number + * @ipa_gsi_chan_num: GSI channel number + * @ipa_if_tlv: number of IPA_IF TLV + * @ipa_if_aos: number of IPA_IF AOS + * @ee: Execution environment + * @prefetch_mode: Prefetch mode to be used + * @prefetch_threshold: Prefetch empty level threshold. + * relevant for smart and free prefetch modes + */ +struct ipa_gsi_ep_config { + int ipa_ep_num; + int ipa_gsi_chan_num; + int ipa_if_tlv; + int ipa_if_aos; + int ee; + enum gsi_prefetch_mode prefetch_mode; + uint8_t prefetch_threshold; +}; + +/** + * struct ipa_smmu_in_params - information provided from client + * @ipa_smmu_client_type: clinet requesting for the smmu info. + */ + +enum ipa_smmu_client_type { + IPA_SMMU_WLAN_CLIENT, + IPA_SMMU_AP_CLIENT, + IPA_SMMU_WIGIG_CLIENT, + IPA_SMMU_WLAN1_CLIENT, + IPA_SMMU_ETH_CLIENT, + IPA_SMMU_ETH1_CLIENT, + IPA_SMMU_CLIENT_MAX +}; + +struct ipa_smmu_in_params { + enum ipa_smmu_client_type smmu_client; +}; + +/** + * struct ipa_smmu_out_params - information provided to IPA client + * @smmu_enable: IPA S1 SMMU enable/disable status + * @shared_cb: is client CB shared (mappings should be done by client only) + */ +struct ipa_smmu_out_params { + bool smmu_enable; + bool shared_cb; +}; + +struct iphdr_rsv { + struct iphdr ipv4_temp; /* 20 bytes */ + uint32_t rsv1; + uint32_t rsv2; + uint32_t rsv3; + uint32_t rsv4; + uint32_t rsv5; +} __packed; + +union ip_hdr_temp { + struct iphdr_rsv ipv4_rsv; /* 40 bytes */ + struct ipv6hdr ipv6_temp; /* 40 bytes */ +} __packed; + +struct ipa_socksv5_uc_tmpl { + uint16_t cmd_id; + uint16_t rsv; + uint32_t cmd_param; + uint16_t pkt_count; + uint16_t rsv2; + uint32_t byte_count; + union ip_hdr_temp ip_hdr; + /* 2B src/dst port */ + uint16_t src_port; + uint16_t dst_port; + + /* attribute mask */ + uint32_t ipa_sockv5_mask; + + /* reqquired update 4B/4B Seq/Ack/SACK */ + uint32_t out_irs; + uint32_t out_iss; + uint32_t in_irs; + uint32_t in_iss; + + /* option 10B: time-stamp */ + uint32_t out_ircv_tsval; + uint32_t in_ircv_tsecr; + uint32_t out_ircv_tsecr; + uint32_t in_ircv_tsval; + + /* option 2B: window-scaling/dynamic */ + uint16_t in_isnd_wscale:4; + uint16_t out_isnd_wscale:4; + uint16_t in_ircv_wscale:4; + uint16_t out_ircv_wscale:4; + uint16_t MAX_WINDOW_SIZE; + /* 11*4 + 40 bytes = 84 bytes */ + uint32_t rsv3; + uint32_t rsv4; + uint32_t rsv5; + uint32_t rsv6; + uint32_t rsv7; + uint32_t rsv8; + uint32_t rsv9; +} __packed; +/*reserve 16 bytes : 16 bytes+ 40 bytes + 44 bytes = 100 bytes (28 bytes left)*/ + +struct ipa_socksv5_info { + /* ipa-uc info */ + struct ipa_socksv5_uc_tmpl ul_out; + struct ipa_socksv5_uc_tmpl dl_out; + + /* ipacm info */ + struct ipacm_socksv5_info ul_in; + struct ipacm_socksv5_info dl_in; + + /* output: handle (index) */ + uint16_t handle; +}; + +struct ipa_ipv6_nat_uc_tmpl { + uint16_t cmd_id; + uint16_t rsv; + uint32_t cmd_param; + uint16_t pkt_count; + uint16_t rsv2; + uint32_t byte_count; + uint64_t private_address_lsb; + uint64_t private_address_msb; + uint64_t public_address_lsb; + uint64_t public_address_msb; + uint16_t private_port; + uint16_t public_port; + uint32_t rsv3; + uint64_t rsv4; + uint64_t rsv5; + uint64_t rsv6; + uint64_t rsv7; + uint64_t rsv8; + uint64_t rsv9; + uint64_t rsv10; + uint64_t rsv11; + uint64_t rsv12; +} __packed; + +#if IS_ENABLED(CONFIG_IPA3) +/* + * Configuration + */ + +/** + * ipa_cfg_ep_ctrl() - IPA end-point Control configuration + * @clnt_hdl: [in] opaque client handle assigned by IPA to client + * @ipa_ep_cfg_ctrl: [in] IPA end-point configuration params + * + * Returns: 0 on success, negative on failure + */ +int ipa_cfg_ep_ctrl(u32 clnt_hdl, const struct ipa_ep_cfg_ctrl *ep_ctrl); + +/* + * Routing + */ + +/** + * ipa_add_rt_rule() - Add the specified routing rules to SW and optionally + * commit to IPA HW + * @rules: [inout] set of routing rules to add + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa_add_rt_rule(struct ipa_ioc_add_rt_rule *rules); + +/** + * ipa_put_rt_tbl() - Release the specified routing table handle + * @rt_tbl_hdl: [in] the routing table handle to release + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa_put_rt_tbl(u32 rt_tbl_hdl); + +/* + * Interface + */ +int ipa_register_intf(const char *name, + const struct ipa_tx_intf *tx, + const struct ipa_rx_intf *rx); +int ipa_deregister_intf(const char *name); + +/* + * Aggregation + */ + +/** + * ipa_set_aggr_mode() - Set the aggregation mode which is a global setting + * @mode: [in] the desired aggregation mode for e.g. straight MBIM, QCNCM, + * etc + * + * Returns: 0 on success + */ + +int ipa_set_aggr_mode(enum ipa_aggr_mode mode); + +/** + * ipa_set_qcncm_ndp_sig() - Set the NDP signature used for QCNCM aggregation + * mode + * @sig: [in] the first 3 bytes of QCNCM NDP signature (expected to be + * "QND") + * + * Set the NDP signature used for QCNCM aggregation mode. The fourth byte + * (expected to be 'P') needs to be set using the header addition mechanism + * + * Returns: 0 on success, negative on failure + */ +int ipa_set_qcncm_ndp_sig(char sig[3]); + +/** + * ipa_set_single_ndp_per_mbim() - Enable/disable single NDP per MBIM frame + * configuration + * @enable: [in] true for single NDP/MBIM; false otherwise + * + * Returns: 0 on success + */ +int ipa_set_single_ndp_per_mbim(bool enable); + +/* + * interrupts + */ + +/** + * ipa_add_interrupt_handler() - Adds handler to an interrupt type + * @interrupt: Interrupt type + * @handler: The handler to be added + * @deferred_flag: whether the handler processing should be deferred in + * a workqueue + * @private_data: the client's private data + * + * Adds handler to an interrupt type and enable the specific bit + * in IRQ_EN register, associated interrupt in IRQ_STTS register will be enabled + */ + +int ipa_add_interrupt_handler(enum ipa_irq_type interrupt, + ipa_irq_handler_t handler, + bool deferred_flag, + void *private_data); + +/** + * ipa_restore_suspend_handler() - restores the original suspend IRQ handler + * as it was registered in the IPA init sequence. + * Return codes: + * 0: success + * -EPERM: failed to remove current handler or failed to add original handler + */ +int ipa_restore_suspend_handler(void); + +/* + * Messaging + */ + +/** + * ipa_send_msg() - Send "message" from kernel client to IPA driver + * @metadata: [in] message metadata + * @buff: [in] the payload for message + * @callback: [in] free callback + * + * Client supplies the message metadata and payload which IPA driver buffers + * till read by user-space. After read from user space IPA driver invokes the + * callback supplied to free the message payload. Client must not touch/free + * the message payload after calling this API. + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa_send_msg(struct ipa_msg_meta *metadata, void *buff, + ipa_msg_free_fn callback); + +/* + * Data path + */ + +/** + * ipa_tx_dp() - Data-path tx handler + * @dst: [in] which IPA destination to route tx packets to + * @skb: [in] the packet to send + * @metadata: [in] TX packet metadata + * + * Data-path tx handler, this is used for both SW data-path which by-passes most + * IPA HW blocks AND the regular HW data-path for WLAN AMPDU traffic only. If + * dst is a "valid" CONS type, then SW data-path is used. If dst is the + * WLAN_AMPDU PROD type, then HW data-path for WLAN AMPDU is used. Anything else + * is an error. For errors, client needs to free the skb as needed. For success, + * IPA driver will later invoke client callback if one was supplied. That + * callback should free the skb. If no callback supplied, IPA driver will free + * the skb internally + * + * The function will use two descriptors for this send command + * (for A5_WLAN_AMPDU_PROD only one desciprtor will be sent), + * the first descriptor will be used to inform the IPA hardware that + * apps need to push data into the IPA (IP_PACKET_INIT immediate command). + * Once this send was done from SPS point-of-view the IPA driver will + * get notified by the supplied callback - ipa_sps_irq_tx_comp() + * + * ipa_sps_irq_tx_comp will call to the user supplied + * callback (from ipa_connect) + * + * Returns: 0 on success, negative on failure + */ +int ipa_tx_dp(enum ipa_client_type dst, struct sk_buff *skb, + struct ipa_tx_meta *metadata); + +/* + * ipa_rmnet_ctl_xmit - QMAP Flow control TX + * + * @skb - tx QMAP control packet + * + * Note: This need to be called after client receive rmnet_ctl_ + * ready_cb and want to send TX flow control message. + * + * This funciton will return 0 on success, -EAGAIN if pipe if full. + */ +int ipa_rmnet_ctl_xmit(struct sk_buff *skb); + +/* + * ipa_rmnet_ll_xmit - Low lat data Tx + * + * @skb - tx low lat data packet + * + * Note: This need to be called after client receive rmnet_ll_ + * ready_cb and want to send TX ll data message. + * + * This funciton will return 0 on success, -EAGAIN if pipe if full. + */ +int ipa_rmnet_ll_xmit(struct sk_buff *skb); + +/* + * ipa_register_notifier - Register for IPA atomic notifier + * + * @fn_ptr - Function pointer to get the notification + * + * This funciton will return 0 on success, -EAGAIN if reg fails. + */ +int ipa_register_notifier(void *fn_ptr); + +/* + * ipa_unregister_notifier - Unregister for IPA atomic notifier + * + * @fn_ptr - Same function pointer used to get the notification + * + * This funciton will return 0 on success, -EAGAIN if reg fails. + */ +int ipa_unregister_notifier(void *fn_ptr); + +void ipa_free_skb(struct ipa_rx_data *data); + +/* + * System pipes + */ + +/** + * ipa_setup_sys_pipe() - Setup an IPA end-point in system-BAM mode and perform + * IPA EP configuration + * @sys_in: [in] input needed to setup BAM pipe and configure EP + * @clnt_hdl: [out] client handle + * + * - configure the end-point registers with the supplied + * parameters from the user. + * - call SPS APIs to create a system-to-bam connection with IPA. + * - allocate descriptor FIFO + * - register callback function(ipa_sps_irq_rx_notify or + * ipa_sps_irq_tx_notify - depends on client type) in case the driver is + * not configured to pulling mode + * + * Returns: 0 on success, negative on failure + */ +int ipa_setup_sys_pipe(struct ipa_sys_connect_params *sys_in, u32 *clnt_hdl); + +/** + * ipa_teardown_sys_pipe() - Teardown the system-BAM pipe and cleanup IPA EP + * @clnt_hdl: [in] the handle obtained from ipa_setup_sys_pipe + * + * Returns: 0 on success, negative on failure + */ +int ipa_teardown_sys_pipe(u32 clnt_hdl); + +int ipa_connect_wdi_pipe(struct ipa_wdi_in_params *in, + struct ipa_wdi_out_params *out); +int ipa_disconnect_wdi_pipe(u32 clnt_hdl); +int ipa_enable_wdi_pipe(u32 clnt_hdl); +int ipa_disable_wdi_pipe(u32 clnt_hdl); +int ipa_resume_wdi_pipe(u32 clnt_hdl); +int ipa_suspend_wdi_pipe(u32 clnt_hdl); +int ipa_reg_uc_rdyCB(struct ipa_wdi_uc_ready_params *param); +int ipa_dereg_uc_rdyCB(void); +int ipa_add_hdr(struct ipa_ioc_add_hdr *hdrs); +int ipa_del_hdr(struct ipa_ioc_del_hdr *hdls); +int ipa_get_hdr(struct ipa_ioc_get_hdr *lookup); +/** + * ipa_get_wdi_stats() - Query WDI statistics from uc + * @stats: [inout] stats blob from client populated by driver + * + * Returns: 0 on success, negative on failure + * + * @note Cannot be called from atomic context + * + */ +int ipa_get_wdi_stats(struct IpaHwStatsWDIInfoData_t *stats); +int ipa_uc_bw_monitor(struct ipa_wdi_bw_info *info); + +/** + * ipa_broadcast_wdi_quota_reach_ind() - quota reach + * @uint32_t fid: [in] input netdev ID + * @uint64_t num_bytes: [in] used bytes + * + * Returns: 0 on success, negative on failure + */ +int ipa_broadcast_wdi_quota_reach_ind(uint32_t fid, + uint64_t num_bytes); + +/* + * To retrieve doorbell physical address of + * wlan pipes + */ +int ipa_uc_wdi_get_dbpa(struct ipa_wdi_db_params *out); + +/* + * IPADMA + */ + /** + * ipa_dma_init() -Initialize IPADMA. + * + * This function initialize all IPADMA internal data and connect in dma: + * MEMCPY_DMA_SYNC_PROD ->MEMCPY_DMA_SYNC_CONS + * MEMCPY_DMA_ASYNC_PROD->MEMCPY_DMA_SYNC_CONS + * + * Return codes: 0: success + * -EFAULT: IPADMA is already initialized + * -ENOMEM: allocating memory error + * -EPERM: pipe connection failed + */ +int ipa_dma_init(void); + +/** + * ipa_dma_enable() -Vote for IPA clocks. + * + *Return codes: 0: success + * -EINVAL: IPADMA is not initialized + * -EPERM: Operation not permitted as ipa_dma is already + * enabled + */ +int ipa_dma_enable(void); + +/** + * ipa_dma_disable()- Unvote for IPA clocks. + * + * enter to power save mode. + * + * Return codes: 0: success + * -EINVAL: IPADMA is not initialized + * -EPERM: Operation not permitted as ipa_dma is already + * disabled + * -EFAULT: can not disable ipa_dma as there are pending + * memcopy works + */ +int ipa_dma_disable(void); + +/** + * ipa_dma_sync_memcpy()- Perform synchronous memcpy using IPA. + * + * @dest: physical address to store the copied data. + * @src: physical address of the source data to copy. + * @len: number of bytes to copy. + * + * Return codes: 0: success + * -EINVAL: invalid params + * -EPERM: operation not permitted as ipa_dma isn't enable or + * initialized + * -SPS_ERROR: on sps faliures + * -EFAULT: other + */ +int ipa_dma_sync_memcpy(u64 dest, u64 src, int len); + +/** + * ipa_dma_async_memcpy()- Perform asynchronous memcpy using IPA. + * + * @dest: physical address to store the copied data. + * @src: physical address of the source data to copy. + * @len: number of bytes to copy. + * @user_cb: callback function to notify the client when the copy was done. + * @user_param: cookie for user_cb. + * + * Return codes: 0: success + * -EINVAL: invalid params + * -EPERM: operation not permitted as ipa_dma isn't enable or + * initialized + * -SPS_ERROR: on sps faliures + * -EFAULT: descr fifo is full. + */ +int ipa_dma_async_memcpy(u64 dest, u64 src, int len, + void (*user_cb)(void *user1), void *user_param); + + +/** + * ipa_dma_destroy() -teardown IPADMA pipes and release ipadma. + * + * this is a blocking function, returns just after destroying IPADMA. + */ +void ipa_dma_destroy(void); + +/* + * Miscellaneous + */ +void ipa_bam_reg_dump(void); + +int ipa_get_ep_mapping(enum ipa_client_type client); + +bool ipa_is_ready(void); + +void ipa_proxy_clk_vote(void); +void ipa_proxy_clk_unvote(void); + +enum ipa_hw_type ipa_get_hw_type(void); + +const struct ipa_gsi_ep_config *ipa_get_gsi_ep_info( + enum ipa_client_type client); + +int ipa_stop_gsi_channel(u32 clnt_hdl); + +typedef void (*ipa_ready_cb)(void *user_data); + +typedef void (*ipa_rmnet_ctl_ready_cb)(void *user_data); + +typedef void (*ipa_rmnet_ctl_stop_cb)(void *user_data); + +typedef void (*ipa_rmnet_ctl_rx_notify_cb)(void *user_data, void *rx_data); + +typedef void (*ipa_rmnet_ll_ready_cb)(void *user_data); + +typedef void (*ipa_rmnet_ll_stop_cb)(void *user_data); + +typedef void (*ipa_rmnet_ll_rx_notify_cb)(void *user_data, void *rx_data); + +int ipa_get_default_aggr_time_limit(enum ipa_client_type client, + u32 *default_aggr_time_limit); + +/** + * ipa_register_ipa_ready_cb() - register a callback to be invoked + * when IPA core driver initialization is complete. + * + * @ipa_ready_cb: CB to be triggered. + * @user_data: Data to be sent to the originator of the CB. + * + * Note: This function is expected to be utilized when ipa_is_ready + * function returns false. + * An IPA client may also use this function directly rather than + * calling ipa_is_ready beforehand, as if this API returns -EEXIST, + * this means IPA initialization is complete (and no callback will + * be triggered). + * When the callback is triggered, the client MUST perform his + * operations in a different context. + * + * The function will return 0 on success, -ENOMEM on memory issues and + * -EEXIST if IPA initialization is complete already. + */ +int ipa_register_ipa_ready_cb(void (*ipa_ready_cb)(void *user_data), + void *user_data); + +/** + * ipa_register_rmnet_ctl_cb() - register callbacks to be invoked + * to rmnet_ctl for qmap flow control pipes setup/teardown/rx_notify. + * + * @ipa_rmnet_ctl_ready_cb: CB to be called when pipes setup. + * @user_data1: user_data for ipa_rmnet_ctl_ready_cb. + * @ipa_rmnet_ctl_stop_cb: CB to be called when pipes teardown. + * @user_data2: user_data for ipa_rmnet_ctl_stop_cb. + * @ipa_rmnet_ctl_rx_notify_cb: CB to be called when receive rx pkts. + * @user_data3: user_data for ipa_rmnet_ctl_rx_notify_cb. + * @rx_data: RX data buffer. + * + * Note: This function is expected to be utilized for rmnet_ctl + * module when new qmap flow control is enabled. + * + * The function will return 0 on success, -EAGAIN if IPA not ready, + * -ENXIO is feature is not enabled, -EEXIST if already called. + */ +int ipa_register_rmnet_ctl_cb( + void (*ipa_rmnet_ctl_ready_cb)(void *user_data1), + void *user_data1, + void (*ipa_rmnet_ctl_stop_cb)(void *user_data2), + void *user_data2, + void (*ipa_rmnet_ctl_rx_notify_cb)(void *user_data3, void *rx_data), + void *user_data3); + +/** + * ipa_unregister_rmnet_ctl_cb() - unregister callbacks to be + * invoked to rmnet_ctl for qmap flow control pipes + * setup/teardown/rx_notify. + * + * Note: This function is expected to be utilized for rmnet_ctl + * module when new qmap flow control is enabled. + * + * The function will return 0 on success, -EAGAIN if IPA not ready, + * -ENXIO is feature is not enabled. + */ +int ipa_unregister_rmnet_ctl_cb(void); + +/** + * ipa_register_rmnet_ll_cb() - register callbacks to be invoked + * to rmnet_ll for low latency data pipes setup/teardown/rx_notify. + * + * @ipa_rmnet_ll_ready_cb: CB to be called when pipes setup. + * @user_data1: user_data for ipa_rmnet_ctl_ready_cb. + * @ipa_rmnet_ll_stop_cb: CB to be called when pipes teardown. + * @user_data2: user_data for ipa_rmnet_ctl_stop_cb. + * @ipa_rmnet_ll_rx_notify_cb: CB to be called when receive rx pkts. + * @user_data3: user_data for ipa_rmnet_ctl_rx_notify_cb. + * @rx_data: RX data buffer. + * + * Note: This function is expected to be utilized for rmnet_ll + * module. + * + * The function will return 0 on success, -EAGAIN if IPA not ready, + * -ENXIO is feature is not enabled, -EEXIST if already called. + */ +int ipa_register_rmnet_ll_cb( + void (*ipa_rmnet_ll_ready_cb)(void *user_data1), + void *user_data1, + void (*ipa_rmnet_ll_stop_cb)(void *user_data2), + void *user_data2, + void (*ipa_rmnet_ll_rx_notify_cb)(void *user_data3, void *rx_data), + void *user_data3); + +/** + * ipa_unregister_rmnet_ll_cb() - unregister callbacks to be + * invoked to rmnet_ll for low lat data pipes + * setup/teardown/rx_notify. + * + * Note: This function is expected to be utilized for rmnet_ll + * module. + * + * The function will return 0 on success, -EAGAIN if IPA not ready, + * -ENXIO is feature is not enabled. + */ +int ipa_unregister_rmnet_ll_cb(void); + +int ipa_get_smmu_params(struct ipa_smmu_in_params *in, + struct ipa_smmu_out_params *out); +/** + * ipa_is_vlan_mode - check if a LAN driver should load in VLAN mode + * @iface - type of vlan capable device + * @res - query result: true for vlan mode, false for non vlan mode + * + * API must be called after ipa_is_ready() returns true, otherwise it will fail + * + * Returns: 0 on success, negative on failure + */ +int ipa_is_vlan_mode(enum ipa_vlan_ifaces iface, bool *res); + +/** + * ipa_get_lan_rx_napi - returns true if NAPI is enabled in the LAN RX dp + */ +bool ipa_get_lan_rx_napi(void); +/* + * ipa_add_socksv5_conn - add socksv5 info to ipa driver + */ +int ipa_add_socksv5_conn(struct ipa_socksv5_info *info); + +/* + * ipa_del_socksv5_conn - del socksv5 info to ipa driver + */ +int ipa_del_socksv5_conn(uint32_t handle); + +int ipa_mhi_handle_ipa_config_req(struct ipa_config_req_msg_v01 *config_req); +int ipa_wigig_save_regs(void); + +#else /* IS_ENABLED(CONFIG_IPA3) */ + +/* + * Configuration + */ +static inline int ipa_cfg_ep_ctrl(u32 clnt_hdl, + const struct ipa_ep_cfg_ctrl *ep_ctrl) +{ + return -EPERM; +} + +/* + * Routing + */ +static inline int ipa_add_rt_rule(struct ipa_ioc_add_rt_rule *rules) +{ + return -EPERM; +} + +static inline int ipa_put_rt_tbl(u32 rt_tbl_hdl) +{ + return -EPERM; +} + +/* + * Interface + */ +static inline int ipa_register_intf(const char *name, + const struct ipa_tx_intf *tx, + const struct ipa_rx_intf *rx) +{ + return -EPERM; +} + +/* + * Aggregation + */ +static inline int ipa_set_aggr_mode(enum ipa_aggr_mode mode) +{ + return -EPERM; +} + +static inline int ipa_set_qcncm_ndp_sig(char sig[3]) +{ + return -EPERM; +} + +static inline int ipa_set_single_ndp_per_mbim(bool enable) +{ + return -EPERM; +} + +/* + * interrupts + */ +static inline int ipa_add_interrupt_handler(enum ipa_irq_type interrupt, + ipa_irq_handler_t handler, + bool deferred_flag, + void *private_data) +{ + return -EPERM; +} + +static inline int ipa_restore_suspend_handler(void) +{ + return -EPERM; +} + +/* + * Messaging + */ +static inline int ipa_send_msg(struct ipa_msg_meta *metadata, void *buff, + ipa_msg_free_fn callback) +{ + return -EPERM; +} + +/* + * Data path + */ +static inline int ipa_tx_dp(enum ipa_client_type dst, struct sk_buff *skb, + struct ipa_tx_meta *metadata) +{ + return -EPERM; +} + +/* + * QMAP Flow control TX + */ +static inline int ipa_rmnet_ctl_xmit(struct sk_buff *skb) +{ + return -EPERM; +} + +/* + * Low Latency data Tx + */ +static inline int ipa_rmnet_ll_xmit(struct sk_buff *skb) +{ + return -EPERM; +} + +/* + * Yellow water mark notifier register + */ +static inline int ipa_register_notifier(void *fn_ptr) +{ + return -EPERM; +} + +/* + * Yellow water mark notifier unregister + */ +static inline int ipa_unregister_notifier(void *fn_ptr) +{ + return -EPERM; +} + +static inline void ipa_free_skb(struct ipa_rx_data *rx_in) +{ +} + +/* + * System pipes + */ + +static inline int ipa_setup_sys_pipe(struct ipa_sys_connect_params *sys_in, + u32 *clnt_hdl) +{ + return -EPERM; +} + +static inline int ipa_teardown_sys_pipe(u32 clnt_hdl) +{ + return -EPERM; +} + +static inline int ipa_connect_wdi_pipe(struct ipa_wdi_in_params *in, + struct ipa_wdi_out_params *out) +{ + return -EPERM; +} + +static inline int ipa_disconnect_wdi_pipe(u32 clnt_hdl) +{ + return -EPERM; +} + +static inline int ipa_enable_wdi_pipe(u32 clnt_hdl) +{ + return -EPERM; +} + +static inline int ipa_disable_wdi_pipe(u32 clnt_hdl) +{ + return -EPERM; +} + +static inline int ipa_resume_wdi_pipe(u32 clnt_hdl) +{ + return -EPERM; +} + +static inline int ipa_suspend_wdi_pipe(u32 clnt_hdl) +{ + return -EPERM; +} + +static inline int ipa_broadcast_wdi_quota_reach_ind(uint32_t fid, + uint64_t num_bytes) +{ + return -EPERM; +} + +static inline int ipa_uc_wdi_get_dbpa( + struct ipa_wdi_db_params *out) +{ + return -EPERM; +} + +/* + * IPADMA + */ +static inline int ipa_dma_init(void) +{ + return -EPERM; +} + +static inline int ipa_dma_enable(void) +{ + return -EPERM; +} + +static inline int ipa_dma_disable(void) +{ + return -EPERM; +} + +static inline int ipa_dma_sync_memcpy(phys_addr_t dest, phys_addr_t src + , int len) +{ + return -EPERM; +} + +static inline int ipa_dma_async_memcpy(phys_addr_t dest, phys_addr_t src + , int len, void (*user_cb)(void *user1), + void *user_param) +{ + return -EPERM; +} + +static inline void ipa_dma_destroy(void) +{ +} + +/* + * Miscellaneous + */ + +static inline int ipa_get_wdi_stats(struct IpaHwStatsWDIInfoData_t *stats) +{ + return -EPERM; +} + +static inline int ipa_uc_bw_monitor(struct ipa_wdi_bw_info *info) +{ + return -EPERM; +} + +static inline int ipa_get_ep_mapping(enum ipa_client_type client) +{ + return -EPERM; +} + +static inline bool ipa_is_ready(void) +{ + return false; +} + +static inline enum ipa_hw_type ipa_get_hw_type(void) +{ + return IPA_HW_None; +} + +static inline int ipa_register_ipa_ready_cb( + void (*ipa_ready_cb)(void *user_data), + void *user_data) +{ + return -EPERM; +} + +static inline int ipa_is_vlan_mode(enum ipa_vlan_ifaces iface, bool *res) +{ + return -EPERM; +} + +static inline bool ipa_get_lan_rx_napi(void) +{ + return false; +} + +static inline int ipa_add_socksv5_conn(struct ipa_socksv5_info *info) +{ + return -EPERM; +} + +static inline int ipa_del_socksv5_conn(uint32_t handle) +{ + return -EPERM; +} + +static inline const struct ipa_gsi_ep_config *ipa_get_gsi_ep_info( + enum ipa_client_type client) +{ + return NULL; +} + +static inline int ipa_stop_gsi_channel(u32 clnt_hdl) +{ + return -EPERM; +} + +static inline int ipa_register_rmnet_ctl_cb( + void (*ipa_rmnet_ctl_ready_cb)(void *user_data1), + void *user_data1, + void (*ipa_rmnet_ctl_stop_cb)(void *user_data2), + void *user_data2, + void (*ipa_rmnet_ctl_rx_notify_cb)(void *user_data3, void *rx_data), + void *user_data3) +{ + return -EPERM; +} + +static inline int ipa_unregister_rmnet_ctl_cb(void) +{ + return -EPERM; +} + +static inline int ipa3_uc_reg_rdyCB( + struct ipa_wdi_uc_ready_params *inout) +{ + return -EPERM; +} + +static inline int ipa_register_rmnet_ll_cb( + void (*ipa_rmnet_ll_ready_cb)(void *user_data1), + void *user_data1, + void (*ipa_rmnet_ll_stop_cb)(void *user_data2), + void *user_data2, + void (*ipa_rmnet_ll_rx_notify_cb)(void *user_data3, void *rx_data), + void *user_data3) +{ + return -EPERM; +} + +static inline int ipa_get_default_aggr_time_limit(enum ipa_client_type client, + u32 *default_aggr_time_limit) +{ + return -EPERM; +} + +static inline int ipa_unregister_rmnet_ll_cb(void) +{ + return -EPERM; +} + +#endif /* IS_ENABLED(CONFIG_IPA3) */ + +/* stubs - to be removed once dependent drivers remove references */ +static inline int ipa_reset_endpoint(u32 clnt_hdl) +{ + return -EPERM; +} + +static inline int ipa_clear_endpoint_delay(u32 clnt_hdl) +{ + return -EPERM; +} + +static inline int ipa_commit_hdr(void) +{ + return -EPERM; +} + +static inline int ipa_put_hdr(u32 hdr_hdl) +{ + return -EPERM; +} + +static inline int ipa_deregister_pull_msg(struct ipa_msg_meta *metadata) +{ + return -EPERM; +} + +/* + * Miscellaneous + */ +static inline int ipa_rm_delete_resource( + enum ipa_rm_resource_name resource_name) +{ + return -EPERM; +} + +static inline int ipa_rm_deregister( + enum ipa_rm_resource_name resource_name, + struct ipa_rm_register_params *reg_params) +{ + return -EPERM; +} + +static inline int ipa_rm_set_perf_profile( + enum ipa_rm_resource_name resource_name, + struct ipa_rm_perf_profile *profile) +{ + return -EPERM; +} + +static inline int ipa_rm_add_dependency( + enum ipa_rm_resource_name resource_name, + enum ipa_rm_resource_name depends_on_name) +{ + return -EPERM; +} + +static inline int ipa_rm_add_dependency_sync( + enum ipa_rm_resource_name resource_name, + enum ipa_rm_resource_name depends_on_name) +{ + return -EPERM; +} + +static inline int ipa_rm_delete_dependency( + enum ipa_rm_resource_name resource_name, + enum ipa_rm_resource_name depends_on_name) +{ + return -EPERM; +} + +static inline int ipa_rm_request_resource( + enum ipa_rm_resource_name resource_name) +{ + return -EPERM; +} + +static inline int ipa_rm_inactivity_timer_init( + enum ipa_rm_resource_name resource_name, + unsigned long msecs) +{ + return -EPERM; +} + +static inline int ipa_rm_release_resource( + enum ipa_rm_resource_name resource_name) +{ + return -EPERM; +} + +static inline int ipa_rm_notify_completion(enum ipa_rm_event event, + enum ipa_rm_resource_name resource_name) +{ + return -EPERM; +} + +static inline int ipa_rm_inactivity_timer_destroy( + enum ipa_rm_resource_name resource_name) +{ + return -EPERM; +} + +static inline int ipa_rm_inactivity_timer_request_resource( + enum ipa_rm_resource_name resource_name) +{ + return -EPERM; +} + +static inline int ipa_rm_inactivity_timer_release_resource( + enum ipa_rm_resource_name resource_name) +{ + return -EPERM; +} + +static inline enum ipa_rm_resource_name ipa_get_rm_resource_from_ep( + int pipe_idx) +{ + return -EPERM; +} + +static inline bool ipa_is_client_handle_valid(u32 clnt_hdl) +{ + return false; +} + +static inline enum ipa_client_type ipa_get_client_mapping(int pipe_idx) +{ + return -EPERM; +} + +static inline bool ipa_get_modem_cfg_emb_pipe_flt(void) +{ + return false; +} + +static inline enum ipa_transport_type ipa_get_transport_type(void) +{ + return IPA_TRANSPORT_TYPE_GSI; +} + +static inline struct device *ipa_get_dma_dev(void) +{ + return NULL; +} + +static inline struct iommu_domain *ipa_get_smmu_domain(void) +{ + return NULL; +} + +static inline int ipa_disable_apps_wan_cons_deaggr( + uint32_t agg_size, uint32_t agg_count) +{ + return -EPERM; +} + +#endif /* _IPA_H_ */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/include/linux/ipa_eth.h b/qcom/opensource/dataipa/drivers/platform/msm/include/linux/ipa_eth.h new file mode 100644 index 0000000000..ad42975bb0 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/include/linux/ipa_eth.h @@ -0,0 +1,278 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _IPA_ETH_H_ +#define _IPA_ETH_H_ + +#include "ipa.h" +#include +#include + +/* New architecture prototypes */ + +typedef void (*ipa_eth_ready_cb)(void *user_data); +typedef u32 ipa_eth_hdl_t; + +/** + * struct ipa_eth_ready_cb - eth readiness parameters + * + * @notify: ipa_eth client ready callback notifier + * @userdata: userdata for ipa_eth ready cb + * @is_eth_ready: true if ipa_eth client is already ready + */ +struct ipa_eth_ready { + ipa_eth_ready_cb notify; + void *userdata; + + /* out params */ + bool is_eth_ready; +}; + +/** + * enum ipa_eth_client_type - names for the various IPA + * eth "clients". + */ +enum ipa_eth_client_type { + IPA_ETH_CLIENT_AQC107, + IPA_ETH_CLIENT_AQC113, + IPA_ETH_CLIENT_RTK8111K, + IPA_ETH_CLIENT_RTK8125B, + IPA_ETH_CLIENT_NTN, + IPA_ETH_CLIENT_EMAC, + IPA_ETH_CLIENT_MAX, +}; + +/** + * enum ipa_eth_pipe_traffic_type - traffic type for the various IPA + * eth "pipes". + */ +enum ipa_eth_pipe_traffic_type { + IPA_ETH_PIPE_BEST_EFFORT, + IPA_ETH_PIPE_LOW_LATENCY, + IPA_ETH_PIPE_TRAFFIC_TYPE_MAX, +}; + +/** + * enum ipa_eth_pipe_direction - pipe direcitons for same + * ethernet client. + */ +enum ipa_eth_pipe_direction { + IPA_ETH_PIPE_DIR_TX, + IPA_ETH_PIPE_DIR_RX, + IPA_ETH_PIPE_DIR_MAX, +}; + +#define IPA_ETH_INST_ID_MAX (2) + +/** + * struct ipa_eth_ntn_setup_info - parameters for ntn ethernet + * offloading + * + * @bar_addr: bar PA to access NTN register + * @tail_ptr_offs: tail ptr offset + * @ioc_mod_threshold: Descriptors # per interrupt request from + * NTN3 HW via descriptor bit as part of the protocol. + */ +struct ipa_eth_ntn_setup_info { + phys_addr_t bar_addr; + phys_addr_t tail_ptr_offs; + uint16_t ioc_mod_threshold; +}; + +/** + * struct ipa_eth_aqc_setup_info - parameters for aqc ethernet + * offloading + * + * @bar_addr: bar PA to access AQC register + * @head_ptr_offs: head ptr offset + * @aqc_ch: AQC ch number + * @dest_tail_ptr_offs: tail ptr offset + */ +struct ipa_eth_aqc_setup_info { + phys_addr_t bar_addr; + phys_addr_t head_ptr_offs; + u8 aqc_ch; + phys_addr_t dest_tail_ptr_offs; +}; + + +/** + * struct ipa_eth_realtek_setup_info - parameters for realtek ethernet + * offloading + * + * @bar_addr: bar PA to access RTK register + * @bar_size: bar region size + * @queue_number: Which RTK queue to check the status on + * @dest_tail_ptr_offs: tail ptr offset + */ +struct ipa_eth_realtek_setup_info { + phys_addr_t bar_addr; + u32 bar_size; + u8 queue_number; + phys_addr_t dest_tail_ptr_offs; +}; + +/** + * struct ipa_eth_buff_smmu_map - IPA iova->pa SMMU mapping + * @iova: virtual address of the data buffer + * @pa: physical address of the data buffer + */ +struct ipa_eth_buff_smmu_map { + dma_addr_t iova; + phys_addr_t pa; +}; + +/** + * struct ipa_eth_pipe_setup_info - info needed for IPA setups + * @is_transfer_ring_valid: if transfer ring is needed + * @transfer_ring_base: the base of the transfer ring + * @transfer_ring_sgt: sgtable of transfer ring + * @transfer_ring_size: size of the transfer ring + * @is_buffer_pool_valid: if buffer pool is needed + * @buffer_pool_base_addr: base of buffer pool address + * @buffer_pool_base_sgt: sgtable of buffer pool + * @data_buff_list_size: number of buffers + * @data_buff_list: array of data buffer list + * @fix_buffer_size: buffer size + * @notify: callback for exception/embedded packets + * @priv: priv for exception callback + * @client_info: vendor specific pipe setup info + * @db_pa: doorbell physical address + * @db_val: doorbell value ethernet HW need to ring + */ +struct ipa_eth_pipe_setup_info { + /* transfer ring info */ + bool is_transfer_ring_valid; + dma_addr_t transfer_ring_base; + struct sg_table *transfer_ring_sgt; + u32 transfer_ring_size; + + /* buffer pool info */ + bool is_buffer_pool_valid; + dma_addr_t buffer_pool_base_addr; + struct sg_table *buffer_pool_base_sgt; + + /* buffer info */ + u32 data_buff_list_size; + struct ipa_eth_buff_smmu_map *data_buff_list; + u32 fix_buffer_size; + + /* client notify cb */ + ipa_notify_cb notify; + void *priv; + + /* vendor specific info */ + union { + struct ipa_eth_aqc_setup_info aqc; + struct ipa_eth_realtek_setup_info rtk; + struct ipa_eth_ntn_setup_info ntn; + } client_info; + + /* output params */ + phys_addr_t db_pa; + u32 db_val; +}; + +/** + * struct ipa_eth_client_pipe_info - ETH pipe/gsi related configuration + * @link: link of ep for different client function on same ethernet HW + * @dir: TX or RX direction + * @info: tx/rx pipe setup info + * @client_info: client the pipe belongs to + * @pipe_hdl: output params, pipe handle + */ +struct ipa_eth_client_pipe_info { + struct list_head link; + enum ipa_eth_pipe_direction dir; + struct ipa_eth_pipe_setup_info info; + struct ipa_eth_client *client_info; + + /* output params */ + ipa_eth_hdl_t pipe_hdl; +}; + +/** + * struct ipa_eth_client - client info per traffic type + * provided by offload client + * @client_type: ethernet client type + * @inst_id: instance id for dual NIC support + * @traffic_type: traffic type + * @pipe_list: list of pipes with same traffic type + * @priv: private data for client + * @test: is test client + */ +struct ipa_eth_client { + /* vendor driver */ + enum ipa_eth_client_type client_type; + u8 inst_id; + + /* traffic type */ + enum ipa_eth_pipe_traffic_type traffic_type; + struct list_head pipe_list; + + /* client specific priv data*/ + void *priv; + bool test; +}; + +/** + * struct ipa_eth_perf_profile - To set BandWidth profile + * + * @max_supported_bw_mbps: maximum bandwidth needed (in Mbps) + */ +struct ipa_eth_perf_profile { + u32 max_supported_bw_mbps; +}; + +/** + * struct ipa_eth_hdr_info - Header to install on IPA HW + * + * @hdr: header to install on IPA HW + * @hdr_len: length of header + * @dst_mac_addr_offset: destination mac address offset + * @hdr_type: layer two header type + */ +struct ipa_eth_hdr_info { + u8 *hdr; + u8 hdr_len; + u8 dst_mac_addr_offset; + enum ipa_hdr_l2_type hdr_type; +}; + +/** + * struct ipa_eth_intf_info - parameters for ipa offload + * interface registration + * + * @netdev_name: network interface name + * @hdr: hdr for ipv4/ipv6 + * @pipe_hdl_list_size: number of pipes prop needed for this interface + * @pipe_hdl_list: array of pipes used for this interface + */ +struct ipa_eth_intf_info { + const char *netdev_name; + struct ipa_eth_hdr_info hdr[IPA_IP_MAX]; + + /* tx/rx pipes for same netdev */ + int pipe_hdl_list_size; + ipa_eth_hdl_t *pipe_hdl_list; +}; + +int ipa_eth_register_ready_cb(struct ipa_eth_ready *ready_info); +int ipa_eth_unregister_ready_cb(struct ipa_eth_ready *ready_info); +int ipa_eth_client_conn_pipes(struct ipa_eth_client *client); +int ipa_eth_client_disconn_pipes(struct ipa_eth_client *client); +int ipa_eth_client_reg_intf(struct ipa_eth_intf_info *intf); +int ipa_eth_client_unreg_intf(struct ipa_eth_intf_info *intf); +int ipa_eth_client_set_perf_profile(struct ipa_eth_client *client, + struct ipa_eth_perf_profile *profile); +int ipa_eth_client_conn_evt(struct ipa_ecm_msg *msg); +int ipa_eth_client_disconn_evt(struct ipa_ecm_msg *msg); +enum ipa_client_type ipa_eth_get_ipa_client_type_from_eth_type( + enum ipa_eth_client_type eth_client_type, enum ipa_eth_pipe_direction dir); +bool ipa_eth_client_exist( + enum ipa_eth_client_type eth_client_type, int inst_id); + +#endif // _IPA_ETH_H_ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/include/linux/ipa_mhi.h b/qcom/opensource/dataipa/drivers/platform/msm/include/linux/ipa_mhi.h new file mode 100644 index 0000000000..dbb1cace27 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/include/linux/ipa_mhi.h @@ -0,0 +1,170 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef IPA_MHI_H_ +#define IPA_MHI_H_ + +#include +#include + +/** + * enum ipa_mhi_event_type - event type for mhi callback + * + * @IPA_MHI_EVENT_READY: IPA MHI is ready and IPA uC is loaded. After getting + * this event MHI client is expected to call to ipa_mhi_start() API + * @IPA_MHI_EVENT_DATA_AVAILABLE: downlink data available on MHI channel + */ +enum ipa_mhi_event_type { + IPA_MHI_EVENT_READY, + IPA_MHI_EVENT_DATA_AVAILABLE, + IPA_MHI_EVENT_MAX, +}; + +enum ipa_mhi_mstate { + IPA_MHI_STATE_M0, + IPA_MHI_STATE_M1, + IPA_MHI_STATE_M2, + IPA_MHI_STATE_M3, + IPA_MHI_STATE_M_MAX +}; + +typedef void (*mhi_client_cb)(void *priv, enum ipa_mhi_event_type event, + unsigned long data); + +/** + * struct ipa_mhi_msi_info - parameters for MSI (Message Signaled Interrupts) + * @addr_low: MSI lower base physical address + * @addr_hi: MSI higher base physical address + * @data: Data Pattern to use when generating the MSI + * @mask: Mask indicating number of messages assigned by the host to device + * + * msi value is written according to this formula: + * ((data & ~mask) | (mmio.msiVec & mask)) + */ +struct ipa_mhi_msi_info { + u32 addr_low; + u32 addr_hi; + u32 data; + u32 mask; +}; + +/** + * struct ipa_mhi_init_params - parameters for IPA MHI initialization API + * + * @msi: MSI (Message Signaled Interrupts) parameters + * @mmio_addr: MHI MMIO physical address + * @first_ch_idx: First channel ID for hardware accelerated channels. + * @first_er_idx: First event ring ID for hardware accelerated channels. + * @assert_bit40: should assert bit 40 in order to access host space. + * if PCIe iATU is configured then not need to assert bit40 + * @notify: client callback + * @priv: client private data to be provided in client callback + * @test_mode: flag to indicate if IPA MHI is in unit test mode + */ +struct ipa_mhi_init_params { + struct ipa_mhi_msi_info msi; + u32 mmio_addr; + u32 first_ch_idx; + u32 first_er_idx; + bool assert_bit40; + mhi_client_cb notify; + void *priv; + bool test_mode; +}; + +/** + * struct ipa_mhi_start_params - parameters for IPA MHI start API + * + * @host_ctrl_addr: Base address of MHI control data structures + * @host_data_addr: Base address of MHI data buffers + * @channel_context_addr: channel context array address in host address space + * @event_context_addr: event context array address in host address space + */ +struct ipa_mhi_start_params { + u32 host_ctrl_addr; + u32 host_data_addr; + u64 channel_context_array_addr; + u64 event_context_array_addr; +}; + +/** + * struct ipa_mhi_connect_params - parameters for IPA MHI channel connect API + * + * @sys: IPA EP configuration info + * @channel_id: MHI channel id + */ +struct ipa_mhi_connect_params { + struct ipa_sys_connect_params sys; + u8 channel_id; +}; + +/* bit #40 in address should be asserted for MHI transfers over pcie */ +#define IPA_MHI_HOST_ADDR(addr) ((addr) | BIT_ULL(40)) + +#if IS_ENABLED(CONFIG_IPA3) + +int ipa_mhi_init(struct ipa_mhi_init_params *params); + +int ipa_mhi_start(struct ipa_mhi_start_params *params); + +int ipa_mhi_connect_pipe(struct ipa_mhi_connect_params *in, u32 *clnt_hdl); + +int ipa_mhi_disconnect_pipe(u32 clnt_hdl); + +int ipa_mhi_suspend(bool force); + +int ipa_mhi_resume(void); + +void ipa_mhi_destroy(void); + +int ipa_mhi_update_mstate(enum ipa_mhi_mstate mstate_info); + +#else /* IS_ENABLED(CONFIG_IPA3) */ + +static inline int ipa_mhi_init(struct ipa_mhi_init_params *params) +{ + return -EPERM; +} + +static inline int ipa_mhi_start(struct ipa_mhi_start_params *params) +{ + return -EPERM; +} + +static inline int ipa_mhi_connect_pipe(struct ipa_mhi_connect_params *in, + u32 *clnt_hdl) +{ + return -EPERM; +} + +static inline int ipa_mhi_disconnect_pipe(u32 clnt_hdl) +{ + return -EPERM; +} + +static inline int ipa_mhi_suspend(bool force) +{ + return -EPERM; +} + +static inline int ipa_mhi_resume(void) +{ + return -EPERM; +} + +static inline void ipa_mhi_destroy(void) +{ + +} + +static inline int ipa_mhi_update_mstate + (enum ipa_mhi_mstate mstate_info) +{ + return -EPERM; +} + +#endif /* IS_ENABLED(CONFIG_IPA3) */ + +#endif /* IPA_MHI_H_ */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/include/linux/ipa_odu_bridge.h b/qcom/opensource/dataipa/drivers/platform/msm/include/linux/ipa_odu_bridge.h new file mode 100644 index 0000000000..08658ecee4 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/include/linux/ipa_odu_bridge.h @@ -0,0 +1,141 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _IPA_ODO_BRIDGE_H_ +#define _IPA_ODO_BRIDGE_H_ + +#include "ipa.h" + +/** + * struct odu_bridge_params - parameters for odu bridge initialization API + * + * @netdev_name: network interface name + * @priv: private data that will be supplied to client's callback + * @tx_dp_notify: callback for handling SKB. the following event are supported: + * IPA_WRITE_DONE: will be called after client called to odu_bridge_tx_dp() + * Client is expected to free the skb. + * IPA_RECEIVE: will be called for delivering skb to APPS. + * Client is expected to deliver the skb to network stack. + * @send_dl_skb: callback for sending skb on downlink direction to adapter. + * Client is expected to free the skb. + * @device_ethaddr: device Ethernet address in network order. + * @ipa_desc_size: IPA Sys Pipe Desc Size + */ +struct odu_bridge_params { + const char *netdev_name; + void *priv; + ipa_notify_cb tx_dp_notify; + int (*send_dl_skb)(void *priv, struct sk_buff *skb); + u8 device_ethaddr[ETH_ALEN]; + u32 ipa_desc_size; +}; + +/** + * struct ipa_bridge_init_params - parameters for IPA bridge initialization API + * + * @info: structure contains initialization information + * @wakeup_request: callback to client to indicate there is downlink data + * available. Client is expected to call ipa_bridge_resume() to start + * receiving data + */ +struct ipa_bridge_init_params { + struct odu_bridge_params info; + void (*wakeup_request)(void *cl_priv); +}; + +#if IS_ENABLED(CONFIG_IPA3) + +int ipa_bridge_init(struct ipa_bridge_init_params *params, u32 *hdl); + +int ipa_bridge_connect(u32 hdl); + +int ipa_bridge_set_perf_profile(u32 hdl, u32 bandwidth); + +int ipa_bridge_disconnect(u32 hdl); + +int ipa_bridge_suspend(u32 hdl); + +int ipa_bridge_resume(u32 hdl); + +int ipa_bridge_tx_dp(u32 hdl, struct sk_buff *skb, + struct ipa_tx_meta *metadata); + +int ipa_bridge_cleanup(u32 hdl); + +#else /* IS_ENABLED(CONFIG_IPA3) */ + +static inline int ipa_bridge_init(struct odu_bridge_params *params, u32 *hdl) +{ + return -EPERM; +} + +static inline int ipa_bridge_connect(u32 hdl) +{ + return -EPERM; +} + +static inline int ipa_bridge_set_perf_profile(u32 hdl, u32 bandwidth) +{ + return -EPERM; +} + +static inline int ipa_bridge_disconnect(u32 hdl) +{ + return -EPERM; +} + +static inline int ipa_bridge_suspend(u32 hdl) +{ + return -EPERM; +} + +static inline int ipa_bridge_resume(u32 hdl) +{ + return -EPERM; +} + +static inline int ipa_bridge_tx_dp(u32 hdl, struct sk_buff *skb, +struct ipa_tx_meta *metadata) +{ + return -EPERM; +} + +static inline int ipa_bridge_cleanup(u32 hdl) +{ + return -EPERM; +} + +#endif /* IS_ENABLED(CONFIG_IPA3) */ + +/* Below API is deprecated. Please use the API above */ + +static inline int odu_bridge_init(struct odu_bridge_params *params) +{ + return -EPERM; +} + +static inline int odu_bridge_disconnect(void) +{ + return -EPERM; +} + +static inline int odu_bridge_connect(void) +{ + return -EPERM; +} + +static inline int odu_bridge_tx_dp(struct sk_buff *skb, + struct ipa_tx_meta *metadata) +{ + return -EPERM; +} + +static inline int odu_bridge_cleanup(void) +{ + return -EPERM; +} + +#endif /* _IPA_ODO_BRIDGE_H */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/include/linux/ipa_qdss.h b/qcom/opensource/dataipa/drivers/platform/msm/include/linux/ipa_qdss.h new file mode 100644 index 0000000000..8a5204d00a --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/include/linux/ipa_qdss.h @@ -0,0 +1,101 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _IPA_QDSS_H_ +#define _IPA_QDSS_H_ + +#include "ipa.h" + +/** + * enum ipa_qdss_notify - these are the only return items + * @IPA_QDSS_SUCCESS: will be returned as it is for both conn + * and disconn + * @IPA_QDSS_PIPE_CONN_FAILURE: will be returned as negative value + * @IPA_QDSS_PIPE_DISCONN_FAILURE: will be returned as negative value + */ +enum ipa_qdss_notify { + IPA_QDSS_SUCCESS, + IPA_QDSS_PIPE_CONN_FAILURE, + IPA_QDSS_PIPE_DISCONN_FAILURE, +}; + +/** + * struct ipa_qdss_conn_in_params - QDSS -> IPA TX configuration + * @data_fifo_base_addr: Base address of the data FIFO used by BAM + * @data_fifo_size: Size of the data FIFO + * @desc_fifo_base_addr: Base address of the descriptor FIFO by BAM + * @desc_fifo_size: Should be configured to 1 by QDSS + * @bam_p_evt_dest_addr: equivalent to event_ring_doorbell_pa + * physical address of the doorbell that IPA uC + * will update the headpointer of the event ring. + * QDSS should send BAM_P_EVNT_REG address in this var + * Configured with the GSI Doorbell Address. + * GSI sends Update RP by doing a write to this address + * @bam_p_evt_threshold: Threshold level of how many bytes consumed + * @override_eot: if override EOT==1, it doesn't check the EOT bit in + * the descriptor + */ +struct ipa_qdss_conn_in_params { + phys_addr_t data_fifo_base_addr; + u32 data_fifo_size; + phys_addr_t desc_fifo_base_addr; + u32 desc_fifo_size; + phys_addr_t bam_p_evt_dest_addr; + u32 bam_p_evt_threshold; + u32 override_eot; +}; + +/** + * struct ipa_qdss_conn_out_params - information provided + * to QDSS driver + * @rx_db_pa: physical address of IPA doorbell for RX (QDSS->IPA transactions) + * QDSS to take this address and assign it to BAM_P_EVENT_DEST_ADDR + */ +struct ipa_qdss_conn_out_params { + phys_addr_t ipa_rx_db_pa; +}; + +#if IS_ENABLED(CONFIG_IPA3) + +/** + * ipa_qdss_conn_pipes - Client should call this + * function to connect QDSS -> IPA pipe + * + * @in: [in] input parameters from client + * @out: [out] output params to client + * + * Note: Should not be called from atomic context + * + * @Return 0 on success, negative on failure + */ +int ipa_qdss_conn_pipes(struct ipa_qdss_conn_in_params *in, + struct ipa_qdss_conn_out_params *out); + +/** + * ipa_qdss_disconn_pipes() - Client should call this + * function to disconnect pipes + * + * Note: Should not be called from atomic context + * + * Returns: 0 on success, negative on failure + */ +int ipa_qdss_disconn_pipes(void); + +#else /* CONFIG_IPA3 */ + +static inline int ipa_qdss_conn_pipes(struct ipa_qdss_conn_in_params *in, + struct ipa_qdss_conn_out_params *out) +{ + return -IPA_QDSS_PIPE_CONN_FAILURE; +} + +static inline int ipa_qdss_disconn_pipes(void) +{ + return -IPA_QDSS_PIPE_DISCONN_FAILURE; +} + +#endif /* CONFIG_IPA3 */ +#endif /* _IPA_QDSS_H_ */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/include/linux/ipa_uc_offload.h b/qcom/opensource/dataipa/drivers/platform/msm/include/linux/ipa_uc_offload.h new file mode 100644 index 0000000000..e43b903ac1 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/include/linux/ipa_uc_offload.h @@ -0,0 +1,326 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _IPA_UC_OFFLOAD_H_ +#define _IPA_UC_OFFLOAD_H_ + +#include "ipa.h" + +/** + * enum ipa_uc_offload_proto + * Protocol type: either WDI or Neutrino + * + * @IPA_UC_WDI: wdi Protocol + * @IPA_UC_NTN: Neutrino Protocol + */ +enum ipa_uc_offload_proto { + IPA_UC_INVALID = 0, + IPA_UC_WDI = 1, + IPA_UC_NTN = 2, + IPA_UC_NTN_V2X = 3, + IPA_UC_MAX_PROT_SIZE +}; + +/** + * struct ipa_hdr_info - Header to install on IPA HW + * + * @hdr: header to install on IPA HW + * @hdr_len: length of header + * @dst_mac_addr_offset: destination mac address offset + * @hdr_type: layer two header type + */ +struct ipa_hdr_info { + u8 *hdr; + u8 hdr_len; + u8 dst_mac_addr_offset; + enum ipa_hdr_l2_type hdr_type; +}; + +/** + * struct ipa_uc_offload_intf_params - parameters for uC offload + * interface registration + * + * @netdev_name: network interface name + * @notify: callback for exception/embedded packets + * @priv: callback cookie + * @hdr_info: header information + * @meta_data: metadata if any + * @meta_data_mask: metadata mask + * @proto: uC offload protocol type + * @alt_dst_pipe: alternate routing output pipe + */ +struct ipa_uc_offload_intf_params { + const char *netdev_name; + ipa_notify_cb notify; + void *priv; + struct ipa_hdr_info hdr_info[IPA_IP_MAX]; + u8 is_meta_data_valid; + u32 meta_data; + u32 meta_data_mask; + enum ipa_uc_offload_proto proto; + enum ipa_client_type alt_dst_pipe; +}; + +/** + * struct ntn_buff_smmu_map - IPA iova->pa SMMU mapping + * @iova: virtual address of the data buffer + * @pa: physical address of the data buffer + */ +struct ntn_buff_smmu_map { + dma_addr_t iova; + phys_addr_t pa; +}; + +/** + * struct ipa_ntn_setup_info - NTN TX/Rx configuration + * @client: type of "client" (IPA_CLIENT_ODU#_PROD/CONS) + * @smmu_enabled: SMMU is enabled for uC or not + * @ring_base_pa: physical address of the base of the Tx/Rx ring + * @ring_base_iova: virtual address of the base of the Tx/Rx ring + * @ring_base_sgt:Scatter table for ntn_rings,contains valid non NULL + * value when ENAC S1-SMMU enabed, else NULL. + * @ntn_ring_size: size of the Tx/Rx ring (in terms of elements) + * @buff_pool_base_pa: physical address of the base of the Tx/Rx buffer pool + * @buff_pool_base_iova: virtual address of the base of the Tx/Rx buffer pool + * @buff_pool_base_sgt: Scatter table for buffer pools,contains valid + * non NULL value. When NULL, do continuosly + * pa to iova mapping (SMMU disable, pa == iova). + * @num_buffers: Rx/Tx buffer pool size (in terms of elements) + * @data_buff_size: size of the each data buffer allocated in DDR + * @ntn_reg_base_ptr_pa: physical address of the Tx/Rx NTN Ring's + * @u8 db_mode: 0 means irq mode, 1 means db mode + * tail pointer + */ +struct ipa_ntn_setup_info { + enum ipa_client_type client; + bool smmu_enabled; + phys_addr_t ring_base_pa; + dma_addr_t ring_base_iova; + struct sg_table *ring_base_sgt; + + u32 ntn_ring_size; + + phys_addr_t buff_pool_base_pa; + dma_addr_t buff_pool_base_iova; + struct sg_table *buff_pool_base_sgt; + + struct ntn_buff_smmu_map *data_buff_list; + + u32 num_buffers; + + u32 data_buff_size; + + phys_addr_t ntn_reg_base_ptr_pa; + + u8 db_mode; +}; + +/** + * struct ipa_uc_offload_out_params - out parameters for uC offload + * + * @clnt_hndl: Handle that client need to pass during + * further operations + */ +struct ipa_uc_offload_out_params { + u32 clnt_hndl; +}; + +/** + * struct ipa_ntn_conn_in_params - NTN TX/Rx connect parameters + * @ul: parameters to connect UL pipe(from Neutrino to IPA) + * @dl: parameters to connect DL pipe(from IPA to Neutrino) + */ +struct ipa_ntn_conn_in_params { + struct ipa_ntn_setup_info ul; + struct ipa_ntn_setup_info dl; +}; + +/** + * struct ipa_ntn_conn_out_params - information provided + * to uC offload client + * @ul_uc_db_pa: physical address of IPA uc doorbell for UL + * @dl_uc_db_pa: physical address of IPA uc doorbell for DL + * @clnt_hdl: opaque handle assigned to offload client + * @ul_uc_db_iomem: iomem address of IPA uc doorbell for UL + * @dl_uc_db_iomem: iomem address of IPA uc doorbell for DL + */ +struct ipa_ntn_conn_out_params { + phys_addr_t ul_uc_db_pa; + phys_addr_t dl_uc_db_pa; + void __iomem *ul_uc_db_iomem; + void __iomem *dl_uc_db_iomem; +}; + +/** + * struct ipa_uc_offload_conn_in_params - information provided by + * uC offload client + * @clnt_hndl: Handle that return as part of reg interface + * @proto: Protocol to use for offload data path + * @ntn: uC RX/Tx configuration info + */ +struct ipa_uc_offload_conn_in_params { + u32 clnt_hndl; + union { + struct ipa_ntn_conn_in_params ntn; + } u; +}; + +/** + * struct ipa_uc_offload_conn_out_params - information provided + * to uC offload client + * @ul_uc_db_pa: physical address of IPA uc doorbell for UL + * @dl_uc_db_pa: physical address of IPA uc doorbell for DL + * @clnt_hdl: opaque handle assigned to offload client + */ +struct ipa_uc_offload_conn_out_params { + union { + struct ipa_ntn_conn_out_params ntn; + } u; +}; + +/** + * struct ipa_perf_profile - To set BandWidth profile + * + * @client: type of "client" (IPA_CLIENT_ODU#_PROD/CONS) + * @proto: uC offload protocol type + * @max_supported_bw_mbps: maximum bandwidth needed (in Mbps) + */ +struct ipa_perf_profile { + enum ipa_client_type client; + enum ipa_uc_offload_proto proto; + u32 max_supported_bw_mbps; +}; + +/** + * struct ipa_uc_ready_params - uC ready CB parameters + * @is_uC_ready: uC loaded or not + * @priv : callback cookie + * @notify: callback + * @proto: uC offload protocol type + */ +struct ipa_uc_ready_params { + bool is_uC_ready; + void *priv; + ipa_uc_ready_cb notify; + enum ipa_uc_offload_proto proto; +}; + +#if IS_ENABLED(CONFIG_IPA3) + +/** + * ipa_uc_offload_reg_intf - Client should call this function to + * init uC offload data path + * + * @init: [in] initialization parameters + * + * Note: Should not be called from atomic context and only + * after checking IPA readiness using ipa_register_ipa_ready_cb() + * + * @Return 0 on success, negative on failure + */ +int ipa_uc_offload_reg_intf( + struct ipa_uc_offload_intf_params *in, + struct ipa_uc_offload_out_params *out); + +/** + * ipa_uc_offload_cleanup - Client Driver should call this + * function before unload and after disconnect + * + * @Return 0 on success, negative on failure + */ +int ipa_uc_offload_cleanup(u32 clnt_hdl); + +/** + * ipa_uc_offload_conn_pipes - Client should call this + * function to connect uC pipe for offload data path + * + * @in: [in] input parameters from client + * @out: [out] output params to client + * + * Note: Should not be called from atomic context and only + * after checking IPA readiness using ipa_register_ipa_ready_cb() + * + * @Return 0 on success, negative on failure + */ +int ipa_uc_offload_conn_pipes(struct ipa_uc_offload_conn_in_params *in, + struct ipa_uc_offload_conn_out_params *out); + +/** + * ipa_uc_offload_disconn_pipes() - Client should call this + * function to disconnect uC pipe to disable offload data path + * @clnt_hdl: [in] opaque client handle assigned by IPA to client + * + * Note: Should not be called from atomic context + * + * Returns: 0 on success, negative on failure + */ +int ipa_uc_offload_disconn_pipes(u32 clnt_hdl); + +/** + * ipa_set_perf_profile() - Client should call this function to + * set IPA clock Band Width based on data rates + * @profile: [in] BandWidth profile to use + * + * Returns: 0 on success, negative on failure + */ +int ipa_set_perf_profile(struct ipa_perf_profile *profile); + + +/* + * To register uC ready callback if uC not ready + * and also check uC readiness + * if uC not ready only, register callback + */ +int ipa_uc_offload_reg_rdyCB(struct ipa_uc_ready_params *param); + +/* + * To de-register uC ready callback + */ +void ipa_uc_offload_dereg_rdyCB(enum ipa_uc_offload_proto proto); + +#else /* IS_ENABLED(CONFIG_IPA3) */ + +static inline int ipa_uc_offload_reg_intf( + struct ipa_uc_offload_intf_params *in, + struct ipa_uc_offload_out_params *out) +{ + return -EPERM; +} + +static inline int ipa_uC_offload_cleanup(u32 clnt_hdl) +{ + return -EPERM; +} + +static inline int ipa_uc_offload_conn_pipes( + struct ipa_uc_offload_conn_in_params *in, + struct ipa_uc_offload_conn_out_params *out) +{ + return -EPERM; +} + +static inline int ipa_uc_offload_disconn_pipes(u32 clnt_hdl) +{ + return -EPERM; +} + +static inline int ipa_set_perf_profile(struct ipa_perf_profile *profile) +{ + return -EPERM; +} + +static inline int ipa_uc_offload_reg_rdyCB(struct ipa_uc_ready_params *param) +{ + return -EPERM; +} + +static inline void ipa_uc_offload_dereg_rdyCB(enum ipa_uc_offload_proto proto) +{ +} + +#endif /* CONFIG_IPA3 */ + +#endif /* _IPA_UC_OFFLOAD_H_ */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/include/linux/ipa_wdi3.h b/qcom/opensource/dataipa/drivers/platform/msm/include/linux/ipa_wdi3.h new file mode 100644 index 0000000000..54b2c2421d --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/include/linux/ipa_wdi3.h @@ -0,0 +1,1004 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2018 - 2021, The Linux Foundation. All rights reserved. + * + * Copyright (c) 2021-2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _IPA_WDI3_H_ +#define _IPA_WDI3_H_ + +#include + +#define IPA_HW_WDI3_TCL_DATA_CMD_ER_DESC_SIZE 32 +#define IPA_HW_WDI3_IPA2FW_ER_DESC_SIZE 8 + +#define IPA_HW_WDI3_MAX_ER_DESC_SIZE \ + (((IPA_HW_WDI3_TCL_DATA_CMD_ER_DESC_SIZE) > \ + (IPA_HW_WDI3_IPA2FW_ER_DESC_SIZE)) ? \ + (IPA_HW_WDI3_TCL_DATA_CMD_ER_DESC_SIZE) : \ + (IPA_HW_WDI3_IPA2FW_ER_DESC_SIZE)) + +#define IPA_WDI_MAX_SUPPORTED_SYS_PIPE 3 +#define IPA_WDI_MAX_FILTER_INFO_COUNT 5 + +typedef u32 ipa_wdi_hdl_t; + +enum ipa_wdi_version { + IPA_WDI_1, + IPA_WDI_2, + IPA_WDI_3, + IPA_WDI_3_V2, + IPA_WDI_VER_MAX +}; + +#define IPA_WDI3_TX_DIR 1 +#define IPA_WDI3_TX1_DIR 2 +#define IPA_WDI3_RX_DIR 3 +#define IPA_WDI_INST_MAX (2) + +/** + * struct ipa_wdi_init_in_params - wdi init input parameters + * + * @wdi_version: wdi version + * @notify: uc ready callback + * @priv: uc ready callback cookie + */ +struct ipa_wdi_init_in_params { + enum ipa_wdi_version wdi_version; + ipa_uc_ready_cb notify; + void *priv; +#ifdef IPA_WAN_MSG_IPv6_ADDR_GW_LEN + ipa_wdi_meter_notifier_cb wdi_notify; +#endif + int inst_id; +}; + +/** + * struct ipa_wdi_init_out_params - wdi init output parameters + * + * @is_uC_ready: is uC ready. No API should be called until uC + is ready. + * @is_smmu_enable: is smmu enabled + * @is_over_gsi: is wdi over GSI or uC + * @opt_wdi_dpath: is optimized data path enabled. + */ +struct ipa_wdi_init_out_params { + bool is_uC_ready; + bool is_smmu_enabled; + bool is_over_gsi; + ipa_wdi_hdl_t hdl; + bool opt_wdi_dpath; +}; +/** + * struct filter_tuple_info - Properties of filters installed with WLAN + * + * @version: IP version, 0 - IPv4, 1 - IPv6 + * @ipv4_saddr: IPV4 source address + * @ipv4_daddr: IPV4 destination address + * @ipv6_saddr: IPV6 source address + * @ipv6_daddr: IPV6 destination address + * @ipv4_addr: IPV4 address + * @ipv6_addr: IPV6 address + * @protocol: trasport protocol being used + * @sport: source port + * @dport: destination port + * @out_hdl: handle given by WLAN for filter installation + */ + +struct filter_tuple_info { + u8 version; + union { + struct { + __be32 ipv4_saddr; + __be32 ipv4_daddr; + } ipv4_addr; + struct { + __be32 ipv6_saddr[4]; + __be32 ipv6_daddr[4]; + } ipv6_addr; + }; + u8 protocol; + __be16 sport; + __be16 dport; + u32 out_hdl; +}; + +/** + * struct ipa_wdi_opt_dpath_flt_add_cb_params - wdi filter add callback parameters + * + * @num_tuples: Number of filter tuples + * @ip_addr_port_tuple: IP info (source/destination IP, source/destination port) + */ +struct ipa_wdi_opt_dpath_flt_add_cb_params { + u8 num_tuples; + struct filter_tuple_info flt_info[IPA_WDI_MAX_FILTER_INFO_COUNT]; +}; + +/** + * struct ipa_wdi_opt_dpath_flt_rem_cb_params - wdi filter remove callback parameters + * + * @num_tuples: Number of filters to be removed + * @hdl_info: array of handles of filters to be removed + */ +struct ipa_wdi_opt_dpath_flt_rem_cb_params { + u8 num_tuples; + u32 hdl_info[IPA_WDI_MAX_FILTER_INFO_COUNT]; +}; + +/** + * struct ipa_wdi_opt_dpath_flt_rsrv_cb_params - wdi filter reserve callback parameters + * + * @num_filters: number of filters to be reserved + * @rsrv_timeout: reservation timeout in milliseconds + */ +struct ipa_wdi_opt_dpath_flt_rsrv_cb_params { + u8 num_filters; + u32 rsrv_timeout; +}; + +typedef int (*ipa_wdi_opt_dpath_flt_rsrv_cb) + (void *priv, struct ipa_wdi_opt_dpath_flt_rsrv_cb_params *in); + +typedef int (*ipa_wdi_opt_dpath_flt_rsrv_rel_cb) + (void *priv); + +typedef int (*ipa_wdi_opt_dpath_flt_add_cb) + (void *priv, struct ipa_wdi_opt_dpath_flt_add_cb_params *in_out); + +typedef int (*ipa_wdi_opt_dpath_flt_rem_cb) + (void *priv, struct ipa_wdi_opt_dpath_flt_rem_cb_params *in); + +/** + * struct ipa_wdi_hdr_info - Header to install on IPA HW + * + * @hdr: header to install on IPA HW + * @hdr_len: length of header + * @dst_mac_addr_offset: destination mac address offset + * @hdr_type: layer two header type + */ +struct ipa_wdi_hdr_info { + u8 *hdr; + u8 hdr_len; + u8 dst_mac_addr_offset; + enum ipa_hdr_l2_type hdr_type; +}; + +/** + * struct ipa_wdi_reg_intf_in_params - parameters for uC offload + * interface registration + * + * @netdev_name: network interface name + * @hdr_info: header information + * @is_meta_data_valid: if metadata is valid + * @meta_data: metadata if any + * @meta_data_mask: metadata mask + * @is_tx1_used: to indicate whether 2.4g or 5g iface + */ +struct ipa_wdi_reg_intf_in_params { + const char *netdev_name; + struct ipa_wdi_hdr_info hdr_info[IPA_IP_MAX]; + enum ipa_client_type alt_dst_pipe; + u8 is_meta_data_valid; + u32 meta_data; + u32 meta_data_mask; + u8 is_tx1_used; + ipa_wdi_hdl_t hdl; +}; + +/** + * struct ipa_wdi_pipe_setup_info - WDI TX/Rx configuration + * @ipa_ep_cfg: ipa endpoint configuration + * @client: type of "client" + * @transfer_ring_base_pa: physical address of the base of the transfer ring + * @transfer_ring_size: size of the transfer ring + * @transfer_ring_doorbell_pa: physical address of the doorbell that + IPA uC will update the tailpointer of the transfer ring + * @is_txr_rn_db_pcie_addr: Bool indicated txr ring DB is pcie or not + * @event_ring_base_pa: physical address of the base of the event ring + * @event_ring_size: event ring size + * @event_ring_doorbell_pa: physical address of the doorbell that IPA uC + will update the headpointer of the event ring + * @is_evt_rn_db_pcie_addr: Bool indicated evt ring DB is pcie or not + * @num_pkt_buffers: Number of pkt buffers allocated. The size of the event + ring and the transfer ring has to be at least ( num_pkt_buffers + 1) + * @pkt_offset: packet offset (wdi header length) + * @desc_format_template[IPA_HW_WDI3_MAX_ER_DESC_SIZE]: Holds a cached + template of the desc format + * @rx_bank_id: value used to perform TCL HW setting + + */ +struct ipa_wdi_pipe_setup_info { + struct ipa_ep_cfg ipa_ep_cfg; + enum ipa_client_type client; + phys_addr_t transfer_ring_base_pa; + u32 transfer_ring_size; + phys_addr_t transfer_ring_doorbell_pa; + bool is_txr_rn_db_pcie_addr; + + phys_addr_t event_ring_base_pa; + u32 event_ring_size; + phys_addr_t event_ring_doorbell_pa; + bool is_evt_rn_db_pcie_addr; + u16 num_pkt_buffers; + + u16 pkt_offset; + + u32 desc_format_template[IPA_HW_WDI3_MAX_ER_DESC_SIZE]; + u8 rx_bank_id; +}; + +/** + * struct ipa_wdi_pipe_setup_info_smmu - WDI TX/Rx configuration + * @ipa_ep_cfg: ipa endpoint configuration + * @client: type of "client" + * @transfer_ring_base_pa: physical address of the base of the transfer ring + * @transfer_ring_size: size of the transfer ring + * @transfer_ring_doorbell_pa: physical address of the doorbell that + IPA uC will update the tailpointer of the transfer ring + * @is_txr_rn_db_pcie_addr: Bool indicated txr ring DB is pcie or not + * @event_ring_base_pa: physical address of the base of the event ring + * @event_ring_size: event ring size + * @event_ring_doorbell_pa: physical address of the doorbell that IPA uC + will update the headpointer of the event ring + * @is_evt_rn_db_pcie_addr: Bool indicated evt ring DB is pcie or not + * @num_pkt_buffers: Number of pkt buffers allocated. The size of the event + ring and the transfer ring has to be at least ( num_pkt_buffers + 1) + * @pkt_offset: packet offset (wdi header length) + * @desc_format_template[IPA_HW_WDI3_MAX_ER_DESC_SIZE]: Holds a cached + template of the desc format + * @rx_bank_id: value used to perform TCL HW setting + + */ +struct ipa_wdi_pipe_setup_info_smmu { + struct ipa_ep_cfg ipa_ep_cfg; + enum ipa_client_type client; + struct sg_table transfer_ring_base; + u32 transfer_ring_size; + phys_addr_t transfer_ring_doorbell_pa; + bool is_txr_rn_db_pcie_addr; + + struct sg_table event_ring_base; + u32 event_ring_size; + phys_addr_t event_ring_doorbell_pa; + bool is_evt_rn_db_pcie_addr; + u16 num_pkt_buffers; + + u16 pkt_offset; + + u32 desc_format_template[IPA_HW_WDI3_MAX_ER_DESC_SIZE]; + u8 rx_bank_id; +}; + +/** + * struct ipa_wdi_conn_in_params - information provided by + * uC offload client + * @notify: client callback function + * @priv: client cookie + * @is_smmu_enabled: if smmu is enabled + * @num_sys_pipe_needed: number of sys pipe needed + * @sys_in: parameters to setup sys pipe in mcc mode + * @tx: parameters to connect TX pipe(from IPA to WLAN) + * @tx_smmu: smmu parameters to connect TX pipe(from IPA to WLAN) + * @rx: parameters to connect RX pipe(from WLAN to IPA) + * @rx_smmu: smmu parameters to connect RX pipe(from WLAN to IPA) + * @is_tx1_used: to notify extra pipe required/not + * @tx1: parameters to connect TX1 pipe(from IPA to WLAN second pipe) + * @tx1_smmu: smmu parameters to connect TX1 pipe(from IPA to WLAN second pipe) + */ +struct ipa_wdi_conn_in_params { + ipa_notify_cb notify; + void *priv; + bool is_smmu_enabled; + u8 num_sys_pipe_needed; + struct ipa_sys_connect_params sys_in[IPA_WDI_MAX_SUPPORTED_SYS_PIPE]; + union { + struct ipa_wdi_pipe_setup_info tx; + struct ipa_wdi_pipe_setup_info_smmu tx_smmu; + } u_tx; + union { + struct ipa_wdi_pipe_setup_info rx; + struct ipa_wdi_pipe_setup_info_smmu rx_smmu; + } u_rx; + bool is_tx1_used; + union { + struct ipa_wdi_pipe_setup_info tx; + struct ipa_wdi_pipe_setup_info_smmu tx_smmu; + } u_tx1; + ipa_wdi_hdl_t hdl; +}; + +/** + * struct ipa_wdi_conn_out_params - information provided + * to WLAN driver + * @tx_uc_db_pa: physical address of IPA uC doorbell for TX + * @rx_uc_db_pa: physical address of IPA uC doorbell for RX + * @tx1_uc_db_pa: physical address of IPA uC doorbell for TX1 + * @is_ddr_mapped: flag set to true if address is from DDR + */ +struct ipa_wdi_conn_out_params { + phys_addr_t tx_uc_db_pa; + phys_addr_t rx_uc_db_pa; + phys_addr_t tx1_uc_db_pa; + bool is_ddr_mapped; +}; + +/** + * struct ipa_wdi_perf_profile - To set BandWidth profile + * + * @client: type of client + * @max_supported_bw_mbps: maximum bandwidth needed (in Mbps) + */ +struct ipa_wdi_perf_profile { + enum ipa_client_type client; + u32 max_supported_bw_mbps; +}; + + +/** + * struct ipa_wdi_capabilities - wdi capability parameters + * + * @num_of_instances: Number of WLAN instances supported. + */ +struct ipa_wdi_capabilities_out_params { + u8 num_of_instances; +}; + +#if IS_ENABLED(CONFIG_IPA3) + +/** + * ipa_wdi_get_capabilities - Client should call this function to + * know the WDI capabilities + * + * Note: Should not be called from atomic context and only + * after checking IPA readiness using ipa_register_ipa_ready_cb() + * + * @Return 0 on success, negative on failure + */ +int ipa_wdi_get_capabilities( + struct ipa_wdi_capabilities_out_params *out); + +/** + * ipa_wdi_init - Client should call this function to + * init WDI IPA offload data path + * + * Note: Should not be called from atomic context and only + * after checking IPA readiness using ipa_register_ipa_ready_cb() + * + * @Return 0 on success, negative on failure + */ +int ipa_wdi_init(struct ipa_wdi_init_in_params *in, + struct ipa_wdi_init_out_params *out); + +/** + * ipa_wdi_opt_dpath_register_flt_cb_per_inst - Client should call this function to + * register filter reservation/release and filter addition/deletion callbacks + * + * + * @Return 0 on success, negative on failure + */ +int ipa_wdi_opt_dpath_register_flt_cb_per_inst( + ipa_wdi_hdl_t hdl, + ipa_wdi_opt_dpath_flt_rsrv_cb flt_rsrv_cb, + ipa_wdi_opt_dpath_flt_rsrv_rel_cb flt_rsrv_rel_cb, + ipa_wdi_opt_dpath_flt_add_cb flt_add_cb, + ipa_wdi_opt_dpath_flt_rem_cb flt_rem_cb); + +/** + * ipa_wdi_opt_dpath_notify_flt_rsvd_per_inst - Client should call this function to + * notify filter reservation event to IPA + * + * + * @Return 0 on success, negative on failure + */ +int ipa_wdi_opt_dpath_notify_flt_rsvd_per_inst(ipa_wdi_hdl_t hdl, + bool is_success); +/** + * ipa_wdi_opt_dpath_notify_flt_rlsd_per_inst - Client should call this function to + * notify filter deletion event to IPA + * + * + * @Return 0 on success, negative on failure + */ +int ipa_wdi_opt_dpath_notify_flt_rlsd_per_inst(ipa_wdi_hdl_t hdl, + bool is_success); + +/** + * ipa_wdi_opt_dpath_rsrv_filter_req - Client should call this function to + * send filter reservation request to wlan + * + * + * @Return 0 on success, negative on failure + */ +int ipa_wdi_opt_dpath_rsrv_filter_req( + struct ipa_wlan_opt_dp_rsrv_filter_req_msg_v01 *req, + struct ipa_wlan_opt_dp_rsrv_filter_resp_msg_v01 *resp); + +/** + * ipa_wdi_opt_dpath_add_filter_req - Client should call this function to + * send filter add request to wlan + * + * + * @Return 0 on success, negative on failure + */ +int ipa_wdi_opt_dpath_add_filter_req( + struct ipa_wlan_opt_dp_add_filter_req_msg_v01 *req, + struct ipa_wlan_opt_dp_add_filter_complt_ind_msg_v01 *ind); + +/** + * ipa_wdi_opt_dpath_remove_filter_req - Client should call this function to + * send filter remove request to wlan + * + * + * @Return 0 on success, negative on failure + */ +int ipa_wdi_opt_dpath_remove_filter_req( + struct ipa_wlan_opt_dp_remove_filter_req_msg_v01 *req, + struct ipa_wlan_opt_dp_remove_filter_complt_ind_msg_v01 *ind); + +/** + * ipa_wdi_opt_dpath_remove_filter_req - Client should call this function to + * send release reservation request to wlan + * + * + * @Return 0 on success, negative on failure + */ +int ipa_wdi_opt_dpath_remove_all_filter_req( + struct ipa_wlan_opt_dp_remove_all_filter_req_msg_v01 *req, + struct ipa_wlan_opt_dp_remove_all_filter_resp_msg_v01 *resp); + +/** + * ipa_xr_wdi_opt_dpath_rsrv_filter_req - Client should call this function to + * send filter reservation request to wlan + * + * + * @Return 0 on success, negative on failure + */ +int ipa_xr_wdi_opt_dpath_rsrv_filter_req(void); + +/** + * ipa_xr_wdi_opt_dpath_add_filter_req - Client should call this function to + * send filter add request to wlan + * + * + * @Return 0 on success, negative on failure + */ +int ipa_xr_wdi_opt_dpath_add_filter_req(struct ipa_wdi_opt_dpath_flt_add_cb_params *req, + u32 stream_id); + +/** + * ipa_xr_wdi_opt_dpath_remove_filter_req - Client should call this function to + * send filter remove request to wlan + * + * + * @Return 0 on success, negative on failure + */ +int ipa_xr_wdi_opt_dpath_remove_filter_req(u32 stream_id); + +/** + * ipa_xr_wdi_opt_dpath_remove_all_filter_req - Client should call this function to + * send release reservation request to wlan + * + * + * @Return 0 on success, negative on failure + */ +int ipa_xr_wdi_opt_dpath_remove_all_filter_req(void); + +/** ipa_get_wdi_version - return wdi version + * + * @Return void + */ +int ipa_get_wdi_version(void); + +/** ipa_wdi_is_tx1_used - return if DBS mode is active + * + * @Return bool + */ +bool ipa_wdi_is_tx1_used(void); + +/** + * ipa_wdi_init_per_inst - Client should call this function to + * init WDI IPA offload data path + * + * Note: Should not be called from atomic context and only + * after checking IPA readiness using ipa_register_ipa_ready_cb() + * + * @Return 0 on success, negative on failure + */ +int ipa_wdi_init_per_inst(struct ipa_wdi_init_in_params *in, + struct ipa_wdi_init_out_params *out); + +/** + * ipa_wdi_cleanup - Client should call this function to + * clean up WDI IPA offload data path + * + * @Return 0 on success, negative on failure + */ +int ipa_wdi_cleanup(void); + +/** + * ipa_wdi_cleanup_per_inst - Client should call this function to + * clean up WDI IPA offload data path + * + * @hdl: hdl to wdi client + * + * @Return 0 on success, negative on failure + */ +int ipa_wdi_cleanup_per_inst(ipa_wdi_hdl_t hdl); + + +/** + * ipa_wdi_reg_intf - Client should call this function to + * register interface + * + * Note: Should not be called from atomic context + * + * @Return 0 on success, negative on failure + */ +int ipa_wdi_reg_intf( + struct ipa_wdi_reg_intf_in_params *in); + +/** + * ipa_wdi_reg_intf_per_inst - Client should call this function to + * register interface + * + * Note: Should not be called from atomic context + * + * @Return 0 on success, negative on failure + */ +int ipa_wdi_reg_intf_per_inst( + struct ipa_wdi_reg_intf_in_params *in); + +/** + * ipa_wdi_dereg_intf - Client Driver should call this + * function to deregister before unload and after disconnect + * + * @Return 0 on success, negative on failure + */ +int ipa_wdi_dereg_intf(const char *netdev_name); + +/** + * ipa_wdi_dereg_intf_per_inst - Client Driver should call this + * function to deregister before unload and after disconnect + * + * @Return 0 on success, negative on failure + */ +int ipa_wdi_dereg_intf_per_inst(const char *netdev_name, ipa_wdi_hdl_t hdl); + +/** + * ipa_wdi_conn_pipes - Client should call this + * function to connect pipes + * + * @in: [in] input parameters from client + * @out: [out] output params to client + * + * Note: Should not be called from atomic context + * + * @Return 0 on success, negative on failure + */ +int ipa_wdi_conn_pipes(struct ipa_wdi_conn_in_params *in, + struct ipa_wdi_conn_out_params *out); + +/** + * ipa_wdi_conn_pipes_per_inst - Client should call this + * function to connect pipes + * + * @in: [in] input parameters from client + * @out: [out] output params to client + * + * Note: Should not be called from atomic context + * + * @Return 0 on success, negative on failure + */ +int ipa_wdi_conn_pipes_per_inst(struct ipa_wdi_conn_in_params *in, + struct ipa_wdi_conn_out_params *out); + +/** + * ipa_wdi_disconn_pipes() - Client should call this + * function to disconnect pipes + * + * Note: Should not be called from atomic context + * + * Returns: 0 on success, negative on failure + */ +int ipa_wdi_disconn_pipes(void); + +/** + * ipa_wdi_disconn_pipes_per_inst() - Client should call this + * function to disconnect pipes + * + * @hdl: hdl to wdi client + * Note: Should not be called from atomic context + * + * Returns: 0 on success, negative on failure + */ +int ipa_wdi_disconn_pipes_per_inst(ipa_wdi_hdl_t hdl); + +/** + * ipa_wdi_enable_pipes() - Client should call this + * function to enable IPA offload data path + * + * Note: Should not be called from atomic context + * + * Returns: 0 on success, negative on failure + */ +int ipa_wdi_enable_pipes(void); + +/** + * ipa_wdi_enable_pipes_per_inst() - Client should call this + * function to enable IPA offload data path + * + * @hdl: hdl to wdi client + * Note: Should not be called from atomic context + * + * Returns: 0 on success, negative on failure + */ +int ipa_wdi_enable_pipes_per_inst(ipa_wdi_hdl_t hdl); + +/** + * ipa_wdi_disable_pipes() - Client should call this + * function to disable IPA offload data path + * + * Note: Should not be called from atomic context + * + * Returns: 0 on success, negative on failure + */ +int ipa_wdi_disable_pipes(void); + +/** + * ipa_wdi_disable_pipes_per_inst() - Client should call this + * function to disable IPA offload data path + * + * @hdl: hdl to wdi client + * Note: Should not be called from atomic context + * + * Returns: 0 on success, negative on failure + */ +int ipa_wdi_disable_pipes_per_inst(ipa_wdi_hdl_t hdl); + +/** + * ipa_wdi_set_perf_profile() - Client should call this function to + * set IPA clock bandwidth based on data rates + * + * @profile: [in] BandWidth profile to use + * + * Returns: 0 on success, negative on failure + */ +int ipa_wdi_set_perf_profile(struct ipa_wdi_perf_profile *profile); + +/** + * ipa_wdi_set_perf_profile_per_inst() - Client should call this function to + * set IPA clock bandwidth based on data rates + * + * @hdl: hdl to wdi client + * @profile: [in] BandWidth profile to use + * + * Returns: 0 on success, negative on failure + */ +int ipa_wdi_set_perf_profile_per_inst(ipa_wdi_hdl_t hdl, + struct ipa_wdi_perf_profile *profile); + +/** + * ipa_wdi_create_smmu_mapping() - Create smmu mapping + * + * @num_buffers: number of buffers + * + * @info: wdi buffer info + */ +int ipa_wdi_create_smmu_mapping(u32 num_buffers, + struct ipa_wdi_buffer_info *info); + +/** + * ipa_wdi_create_smmu_mapping_per_inst() - Create smmu mapping + * + * @hdl: hdl to wdi client + * @num_buffers: number of buffers + * @info: wdi buffer info + */ +int ipa_wdi_create_smmu_mapping_per_inst(ipa_wdi_hdl_t hdl, + u32 num_buffers, + struct ipa_wdi_buffer_info *info); + +/** + * ipa_wdi_release_smmu_mapping() - Release smmu mapping + * + * @num_buffers: number of buffers + * + * @info: wdi buffer info + */ +int ipa_wdi_release_smmu_mapping(u32 num_buffers, + struct ipa_wdi_buffer_info *info); + +/** + * ipa_wdi_release_smmu_mapping_per_inst() - Release smmu mapping + * + * @hdl: hdl to wdi client + * @num_buffers: number of buffers + * + * @info: wdi buffer info + */ +int ipa_wdi_release_smmu_mapping_per_inst(ipa_wdi_hdl_t hdl, + u32 num_buffers, + struct ipa_wdi_buffer_info *info); + +/** + * ipa_wdi_get_stats() - Query WDI statistics + * @stats: [inout] stats blob from client populated by driver + * + * Returns: 0 on success, negative on failure + * + * @note Cannot be called from atomic context + * + */ +int ipa_wdi_get_stats(struct IpaHwStatsWDIInfoData_t *stats); + + +/** + * ipa_wdi_bw_monitor() - set wdi BW monitoring + * @info: [inout] info blob from client populated by driver + * + * Returns: 0 on success, negative on failure + * + * @note Cannot be called from atomic context + * + */ +int ipa_wdi_bw_monitor(struct ipa_wdi_bw_info *info); + +/** + * ipa_wdi_sw_stats() - set wdi BW monitoring + * @info: [inout] info blob from client populated by driver + * + * Returns: 0 on success, negative on failure + * + * @note Cannot be called from atomic context + * + */ +int ipa_wdi_sw_stats(struct ipa_wdi_tx_info *info); + +#else /* IS_ENABLED(CONFIG_IPA3) */ + +/** + * ipa_wdi_get_capabilities - Client should call this function to + * know the WDI capabilities + * + * Note: Should not be called from atomic context and only + * after checking IPA readiness using ipa_register_ipa_ready_cb() + * + * @Return 0 on success, negative on failure + */ +int ipa_wdi_get_capabilities( + struct ipa_wdi_capabilities_out_params *out) +{ + return -EPERM; +} + +static inline int ipa_wdi_init(struct ipa_wdi_init_in_params *in, + struct ipa_wdi_init_out_params *out) +{ + return -EPERM; +} + +static inline int ipa_wdi_init_per_inst( + struct ipa_wdi_init_in_params *in, + struct ipa_wdi_init_out_params *out) +{ + return -EPERM; +} + +static inline int ipa_get_wdi_version(void) +{ + return -EPERM; +} + +static inline int ipa_wdi_is_tx1_used(void) +{ + return -EPERM; +} + +static inline int ipa_wdi_cleanup(void) +{ + return -EPERM; +} + +static inline int ipa_wdi_cleanup_per_inst(ipa_wdi_hdl_t hdl) +{ + return -EPERM; +} + +static inline int ipa_wdi_reg_intf( + struct ipa_wdi_reg_intf_in_params *in) +{ + return -EPERM; +} + +static inline int ipa_wdi_reg_intf_per_inst( + struct ipa_wdi_reg_intf_in_params *in) +{ + return -EPERM; +} + +static inline int ipa_wdi_dereg_intf(const char *netdev_name) +{ + return -EPERM; +} + +static inline int ipa_wdi_dereg_intf_per_inst(const char *netdev_name, + ipa_wdi_hdl_t hdl) +{ + return -EPERM; +} + +static inline int ipa_wdi_conn_pipes(struct ipa_wdi_conn_in_params *in, + struct ipa_wdi_conn_out_params *out) +{ + return -EPERM; +} + +static inline int ipa_wdi_conn_pipes_per_inst( + struct ipa_wdi_conn_in_params *in, + struct ipa_wdi_conn_out_params *out) +{ + return -EPERM; +} + +static inline int ipa_wdi_disconn_pipes(void) +{ + return -EPERM; +} + +static inline int ipa_wdi_disconn_pipes_per_inst(ipa_wdi_hdl_t hdl) +{ + return -EPERM; +} + + +static inline int ipa_wdi_enable_pipes(void) +{ + return -EPERM; +} + +static inline int ipa_wdi_enable_pipes_per_inst(ipa_wdi_hdl_t hdl) +{ + return -EPERM; +} + +static inline int ipa_wdi_disable_pipes(void) +{ + return -EPERM; +} + +static inline int ipa_wdi_disable_pipes_per_inst(ipa_wdi_hdl_t hdl) +{ + return -EPERM; +} + +static inline int ipa_wdi_set_perf_profile( + struct ipa_wdi_perf_profile *profile) +{ + return -EPERM; +} + +static inline int ipa_wdi_set_perf_profile_per_inst( + ipa_wdi_hdl_t hdl, + struct ipa_wdi_perf_profile *profile) +{ + return -EPERM; +} + +static inline int ipa_wdi_create_smmu_mapping(u32 num_buffers, + struct ipa_wdi_buffer_info *info) +{ + return -EPERM; +} + +static inline int ipa_wdi_create_smmu_mapping_per_inst( + ipa_wdi_hdl_t hdl, + u32 num_buffers, + struct ipa_wdi_buffer_info *info) +{ + return -EPERM; +} + +static inline int ipa_wdi_release_smmu_mapping(u32 num_buffers, + struct ipa_wdi_buffer_info *info) +{ + return -EPERM; +} + +static inline int ipa_wdi_release_smmu_mapping_per_inst( + ipa_wdi_hdl_t hdl, + u32 num_buffers, + struct ipa_wdi_buffer_info *info) +{ + return -EPERM; +} + +static inline int ipa_wdi_get_stats(struct IpaHwStatsWDIInfoData_t *stats) +{ + return -EPERM; +} + +static inline int ipa_wdi_bw_monitor(struct ipa_wdi_bw_info *info) +{ + return -EPERM; +} + +static inline int ipa_wdi_sw_stats(struct ipa_wdi_tx_info *info) +{ + return -EPERM; +} + +static inline int ipa_wdi_opt_dpath_register_flt_cb_per_inst( + ipa_wdi_hdl_t hdl, + ipa_wdi_opt_dpath_flt_rsrv_cb flt_rsrv_cb, + ipa_wdi_opt_dpath_flt_rsrv_rel_cb flt_rsrv_rel_cb, + ipa_wdi_opt_dpath_flt_add_cb flt_add_cb, + ipa_wdi_opt_dpath_flt_rem_cb flt_rem_cb) +{ + return -EPERM; +} + +static inline int ipa_wdi_opt_dpath_notify_flt_rsvd_per_inst(ipa_wdi_hdl_t hdl, + bool is_success) +{ + return -EPERM; +} + +static inline int ipa_wdi_opt_dpath_notify_flt_rlsd_per_inst(ipa_wdi_hdl_t hdl, + bool is_success) +{ + return -EPERM; +} + +static int ipa_wdi_opt_dpath_rsrv_filter_req( + struct ipa_wlan_opt_dp_rsrv_filter_req_msg_v01 *req, + struct ipa_wlan_opt_dp_rsrv_filter_resp_msg_v01 *resp) +{ + return -EPERM; +} + +static int ipa_wdi_opt_dpath_add_filter_req( + struct ipa_wlan_opt_dp_add_filter_req_msg_v01 *req, + struct ipa_wlan_opt_dp_add_filter_complt_ind_msg_v01 *ind) +{ + return -EPERM; +} + +static int ipa_wdi_opt_dpath_remove_filter_req( + struct ipa_wlan_opt_dp_remove_filter_req_msg_v01 *req, + struct ipa_wlan_opt_dp_remove_filter_complt_ind_msg_v01 *ind) +{ + return -EPERM; +} + +static int ipa_wdi_opt_dpath_remove_all_filter_req( + struct ipa_wlan_opt_dp_remove_all_filter_req_msg_v01 *req, + struct ipa_wlan_opt_dp_remove_all_filter_resp_msg_v01 *resp) +{ + return -EPERM; +} + +static int ipa_xr_wdi_opt_dpath_rsrv_filter_req(void) +{ + return -EPERM; +} + +static int ipa_xr_wdi_opt_dpath_add_filter_req(struct ipa_wdi_opt_dpath_flt_add_cb_params *req, + u32 stream_id) +{ + return -EPERM; +} + +static int ipa_xr_wdi_opt_dpath_remove_filter_req(u32 stream_id) +{ + return -EPERM; +} + +static int ipa_xr_wdi_opt_dpath_remove_all_filter_req(void) +{ + return -EPERM; +} + +#endif /* IS_ENABLED(CONFIG_IPA3) */ + +#endif /* _IPA_WDI3_H_ */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/include/linux/ipa_wigig.h b/qcom/opensource/dataipa/drivers/platform/msm/include/linux/ipa_wigig.h new file mode 100644 index 0000000000..d0e57d4aa5 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/include/linux/ipa_wigig.h @@ -0,0 +1,487 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _IPA_WIGIG_H_ +#define _IPA_WIGIG_H_ + +#include +#include "ipa.h" + +typedef void (*ipa_wigig_misc_int_cb)(void *priv); + +/* + * struct ipa_wigig_init_in_params - wigig init input parameters + * + * @periph_baddr_pa: physical address of wigig HW base + * @pseudo_cause_pa: physical address of wigig HW pseudo_cause register + * @int_gen_tx_pa: physical address of wigig HW int_gen_tx register + * @int_gen_rx_pa: physical address of wigig HW int_gen_rx register + * @dma_ep_misc_pa: physical address of wigig HW dma_ep_misc register + * @notify: uc ready callback + * @int_notify: wigig misc interrupt callback + * @priv: uc ready callback cookie + */ +struct ipa_wigig_init_in_params { + phys_addr_t periph_baddr_pa; + phys_addr_t pseudo_cause_pa; + phys_addr_t int_gen_tx_pa; + phys_addr_t int_gen_rx_pa; + phys_addr_t dma_ep_misc_pa; + ipa_uc_ready_cb notify; + ipa_wigig_misc_int_cb int_notify; + void *priv; +}; + +/* + * struct ipa_wigig_init_out_params - wigig init output parameters + * + * @is_uC_ready: is uC ready. No API should be called until uC is ready. + * @uc_db_pa: physical address of IPA uC doorbell + * @lan_rx_napi_enable: if we use NAPI in the LAN rx + */ +struct ipa_wigig_init_out_params { + bool is_uc_ready; + phys_addr_t uc_db_pa; + bool lan_rx_napi_enable; +}; + +/* + * struct ipa_wigig_hdr_info - Header to install on IPA HW + * + * @hdr: header to install on IPA HW + * @hdr_len: length of header + * @dst_mac_addr_offset: destination mac address offset + * @hdr_type: layer two header type + */ +struct ipa_wigig_hdr_info { + u8 *hdr; + u8 hdr_len; + u8 dst_mac_addr_offset; + enum ipa_hdr_l2_type hdr_type; +}; + +/* + * struct ipa_wigig_reg_intf_in_params - parameters for offload interface + * registration + * + * @netdev_name: network interface name + * @netdev_mac: netdev mac address + * @hdr_info: header information + */ +struct ipa_wigig_reg_intf_in_params { + const char *netdev_name; + u8 netdev_mac[IPA_MAC_ADDR_SIZE]; + struct ipa_wigig_hdr_info hdr_info[IPA_IP_MAX]; +}; + +/* + * struct ipa_wigig_pipe_setup_info - WIGIG TX/Rx configuration + * @desc_ring_base_pa: physical address of the base of the descriptor ring + * @desc_ring_size: size of the descriptor ring in bytes + * @desc_ring_HWHEAD_pa: physical address of the wigig descriptor ring HWHEAD + * @desc_ring_HWTAIL_pa: physical address of the wigig descriptor ring HWTAIL + * @status_ring_base_pa: physical address of the base of the status ring + * @status_ring_size: status ring size in bytes + * @desc_ring_HWHEAD_pa: physical address of the wigig descriptor ring HWHEAD + * @desc_ring_HWTAIL_pa: physical address of the wigig descriptor ring HWTAIL + */ +struct ipa_wigig_pipe_setup_info { + phys_addr_t desc_ring_base_pa; + u16 desc_ring_size; + phys_addr_t desc_ring_HWHEAD_pa; + phys_addr_t desc_ring_HWTAIL_pa; + + phys_addr_t status_ring_base_pa; + u16 status_ring_size; + phys_addr_t status_ring_HWHEAD_pa; + phys_addr_t status_ring_HWTAIL_pa; +}; + +/* + * struct ipa_wigig_pipe_setup_info_smmu - WIGIG TX/Rx configuration smmu mode + * @desc_ring_base: sg_table of the base of the descriptor ring + * @desc_ring_base_iova: IO virtual address mapped to physical base address + * @desc_ring_size: size of the descriptor ring in bytes + * @desc_ring_HWHEAD_pa: physical address of the wigig descriptor ring HWHEAD + * @desc_ring_HWTAIL_pa: physical address of the wigig descriptor ring HWTAIL + * @status_ring_base: sg_table of the base of the status ring + * @status_ring_base_iova: IO virtual address mapped to physical base address + * @status_ring_size: status ring size in bytes + * @desc_ring_HWHEAD_pa: physical address of the wigig descriptor ring HWHEAD + * @desc_ring_HWTAIL_pa: physical address of the wigig descriptor ring HWTAIL + */ +struct ipa_wigig_pipe_setup_info_smmu { + struct sg_table desc_ring_base; + u64 desc_ring_base_iova; + u16 desc_ring_size; + phys_addr_t desc_ring_HWHEAD_pa; + phys_addr_t desc_ring_HWTAIL_pa; + + struct sg_table status_ring_base; + u64 status_ring_base_iova; + u16 status_ring_size; + phys_addr_t status_ring_HWHEAD_pa; + phys_addr_t status_ring_HWTAIL_pa; +}; + +/* + * struct ipa_wigig_rx_pipe_data_buffer_info - WIGIG Rx data buffer + * configuration + * @data_buffer_base_pa: physical address of the physically contiguous + * Rx data buffer + * @data_buffer_size: size of the data buffer + */ +struct ipa_wigig_rx_pipe_data_buffer_info { + phys_addr_t data_buffer_base_pa; + u32 data_buffer_size; +}; + +/* + * struct ipa_wigig_rx_pipe_data_buffer_info_smmu - WIGIG Rx data buffer + * configuration smmu mode + * @data_buffer_base: sg_table of the physically contiguous + * Rx data buffer + * @data_buffer_base_iova: IO virtual address mapped to physical base address + * @data_buffer_size: size of the data buffer + */ +struct ipa_wigig_rx_pipe_data_buffer_info_smmu { + struct sg_table data_buffer_base; + u64 data_buffer_base_iova; + u32 data_buffer_size; +}; + +/* + * struct ipa_wigig_conn_rx_in_params - information provided by + * WIGIG offload client for Rx pipe + * @notify: client callback function + * @priv: client cookie + * @pipe: parameters to connect Rx pipe (WIGIG to IPA) + * @dbuff: Rx data buffer info + */ +struct ipa_wigig_conn_rx_in_params { + ipa_notify_cb notify; + void *priv; + struct ipa_wigig_pipe_setup_info pipe; + struct ipa_wigig_rx_pipe_data_buffer_info dbuff; +}; + +/* + * struct ipa_wigig_conn_rx_in_params_smmu - information provided by + * WIGIG offload client for Rx pipe + * @notify: client callback function + * @priv: client cookie + * @pipe_smmu: parameters to connect Rx pipe (WIGIG to IPA) smmu mode + * @dbuff_smmu: Rx data buffer info smmu mode + */ +struct ipa_wigig_conn_rx_in_params_smmu { + ipa_notify_cb notify; + void *priv; + struct ipa_wigig_pipe_setup_info_smmu pipe_smmu; + struct ipa_wigig_rx_pipe_data_buffer_info_smmu dbuff_smmu; +}; + +/* + * struct ipa_wigig_conn_out_params - information provided + * to WIGIG driver + * @client: client type allocated by IPA driver + */ +struct ipa_wigig_conn_out_params { + enum ipa_client_type client; +}; + +/* + * struct ipa_wigig_tx_pipe_data_buffer_info - WIGIG Tx data buffer + * configuration + * @data_buffer_size: size of a single data buffer + */ +struct ipa_wigig_tx_pipe_data_buffer_info { + u32 data_buffer_size; +}; + +/* + * struct ipa_wigig_tx_pipe_data_buffer_info_smmu - WIGIG Tx data buffer + * configuration smmu mode + * @data_buffer_base_pa: sg_tables of the Tx data buffers + * @data_buffer_base_iova: IO virtual address mapped to physical base address + * @num_buffers: number of buffers + * @data_buffer_size: size of a single data buffer + */ +struct ipa_wigig_tx_pipe_data_buffer_info_smmu { + struct sg_table *data_buffer_base; + u64 *data_buffer_base_iova; + u32 num_buffers; + u32 data_buffer_size; +}; + +/* + * struct ipa_wigig_conn_tx_in_params - information provided by + * wigig offload client for Tx pipe + * @pipe: parameters to connect Tx pipe (IPA to WIGIG) + * @dbuff: Tx data buffer info + * @int_gen_tx_bit_num: bit in int_gen_tx register associated with this client + * @client_mac: MAC address of client to be connected + */ +struct ipa_wigig_conn_tx_in_params { + struct ipa_wigig_pipe_setup_info pipe; + struct ipa_wigig_tx_pipe_data_buffer_info dbuff; + u8 int_gen_tx_bit_num; + u8 client_mac[IPA_MAC_ADDR_SIZE]; +}; + +/* + * struct ipa_wigig_conn_tx_in_params_smmu - information provided by + * wigig offload client for Tx pipe + * @pipe_smmu: parameters to connect Tx pipe (IPA to WIGIG) smmu mode + * @dbuff_smmu: Tx data buffer info smmu mode + * @int_gen_tx_bit_num: bit in int_gen_tx register associated with this client + * @client_mac: MAC address of client to be connected + */ +struct ipa_wigig_conn_tx_in_params_smmu { + struct ipa_wigig_pipe_setup_info_smmu pipe_smmu; + struct ipa_wigig_tx_pipe_data_buffer_info_smmu dbuff_smmu; + u8 int_gen_tx_bit_num; + u8 client_mac[IPA_MAC_ADDR_SIZE]; +}; + +#if IS_ENABLED(CONFIG_IPA3) + +/* + * ipa_wigig_init - Client should call this function to + * init WIGIG IPA offload data path + * + * Note: Should not be called from atomic context + * + * @Return 0 on success, negative on failure + */ +int ipa_wigig_init(struct ipa_wigig_init_in_params *in, + struct ipa_wigig_init_out_params *out); + +/* + * ipa_wigig_cleanup - Client should call this function to + * clean up WIGIG IPA offload data path + * + * @Return 0 on success, negative on failure + */ +int ipa_wigig_cleanup(void); + +/* + * ipa_wigig_is_smmu_enabled - get smmu state + * + * @Return true if smmu is enabled, false if disabled + */ +bool ipa_wigig_is_smmu_enabled(void); + +/* + * ipa_wigig_reg_intf - Client should call this function to + * register interface + * + * Note: Should not be called from atomic context + * + * @Return 0 on success, negative on failure + */ +int ipa_wigig_reg_intf(struct ipa_wigig_reg_intf_in_params *in); + +/* + * ipa_wigig_dereg_intf - Client Driver should call this + * function to deregister before unload and after disconnect + * + * @Return 0 on success, negative on failure + */ +int ipa_wigig_dereg_intf(const char *netdev_name); + +/* + * ipa_wigig_conn_rx_pipe - Client should call this + * function to connect the rx (UL) pipe + * + * @in: [in] input parameters from client + * @out: [out] output params to client + * + * Note: Non SMMU mode only, Should not be called from atomic context + * + * @Return 0 on success, negative on failure + */ +int ipa_wigig_conn_rx_pipe(struct ipa_wigig_conn_rx_in_params *in, + struct ipa_wigig_conn_out_params *out); + +/* + * ipa_wigig_conn_rx_pipe_smmu - Client should call this + * function to connect the rx (UL) pipe + * + * @in: [in] input parameters from client + * @out: [out] output params to client + * + * Note: SMMU mode only, Should not be called from atomic context + * + * @Return 0 on success, negative on failure + */ +int ipa_wigig_conn_rx_pipe_smmu(struct ipa_wigig_conn_rx_in_params_smmu *in, + struct ipa_wigig_conn_out_params *out); + +/* + * ipa_wigig_conn_client - Client should call this + * function to connect one of the tx (DL) pipes when a WIGIG client connects + * + * @in: [in] input parameters from client + * @out: [out] output params to client + * + * Note: Non SMMU mode only, Should not be called from atomic context + * + * @Return 0 on success, negative on failure + */ +int ipa_wigig_conn_client(struct ipa_wigig_conn_tx_in_params *in, + struct ipa_wigig_conn_out_params *out); + +/* + * ipa_wigig_conn_client_smmu - Client should call this + * function to connect one of the tx (DL) pipes when a WIGIG client connects + * + * @in: [in] input parameters from client + * @out: [out] output params to client + * + * Note: SMMU mode only, Should not be called from atomic context + * + * @Return 0 on success, negative on failure + */ +int ipa_wigig_conn_client_smmu(struct ipa_wigig_conn_tx_in_params_smmu *in, + struct ipa_wigig_conn_out_params *out); + +/* + * ipa_wigig_disconn_pipe() - Client should call this + * function to disconnect a pipe + * + * @client: [in] pipe to be disconnected + * + * Note: Should not be called from atomic context + * + * Returns: 0 on success, negative on failure + */ +int ipa_wigig_disconn_pipe(enum ipa_client_type client); + +/* + * ipa_wigig_enable_pipe() - Client should call this + * function to enable IPA offload data path + * + * @client: [in] pipe to be enabled + * Note: Should not be called from atomic context + * + * Returns: 0 on success, negative on failure + */ + +int ipa_wigig_enable_pipe(enum ipa_client_type client); + +/* + * ipa_wigig_disable_pipe() - Client should call this + * function to disable IPA offload data path + * + * @client: [in] pipe to be disabled + * Note: Should not be called from atomic context + * + * Returns: 0 on success, negative on failure + */ +int ipa_wigig_disable_pipe(enum ipa_client_type client); + +/* + * ipa_wigig_tx_dp() - transmit tx packet through IPA to 11ad HW + * + * @dst: [in] destination ipa client pipe to be used + * @skb: [in] skb to be transmitted + * + * Returns: 0 on success, negative on failure + */ +int ipa_wigig_tx_dp(enum ipa_client_type dst, struct sk_buff *skb); + +/** + * ipa_wigig_set_perf_profile() - Client should call this function to + * set IPA clock bandwidth based on data rates + * + * @max_supported_bw_mbps: [in] maximum bandwidth needed (in Mbps) + * + * Returns: 0 on success, negative on failure + */ +int ipa_wigig_set_perf_profile(u32 max_supported_bw_mbps); + +#else /* IS_ENABLED(CONFIG_IPA3) */ +static inline int ipa_wigig_init(struct ipa_wigig_init_in_params *in, + struct ipa_wigig_init_out_params *out) +{ + return -EPERM; +} + +static inline int ipa_wigig_cleanup(void) +{ + return -EPERM; +} + +static inline bool ipa_wigig_is_smmu_enabled(void) +{ + return -EPERM; +} + +static inline int ipa_wigig_reg_intf(struct ipa_wigig_reg_intf_in_params *in) +{ + return -EPERM; +} + +static inline int ipa_wigig_dereg_intf(const char *netdev_name) +{ + return -EPERM; +} + +static inline int ipa_wigig_conn_rx_pipe( + struct ipa_wigig_conn_rx_in_params *in, + struct ipa_wigig_conn_out_params *out) +{ + return -EPERM; +} + +static inline int ipa_wigig_conn_rx_pipe_smmu( + struct ipa_wigig_conn_rx_in_params_smmu *in, + struct ipa_wigig_conn_out_params *out) +{ + return -EPERM; +} + +static inline int ipa_wigig_conn_client( + struct ipa_wigig_conn_tx_in_params *in, + struct ipa_wigig_conn_out_params *out) +{ + return -EPERM; +} + +static inline int ipa_wigig_conn_client_smmu( + struct ipa_wigig_conn_tx_in_params_smmu *in, + struct ipa_wigig_conn_out_params *out) +{ + return -EPERM; +} + +static inline int ipa_wigig_disconn_pipe(enum ipa_client_type client) +{ + return -EPERM; +} + +static inline int ipa_wigig_enable_pipe(enum ipa_client_type client) +{ + return -EPERM; +} + +static inline int ipa_wigig_disable_pipe(enum ipa_client_type client) +{ + return -EPERM; +} + +static inline int ipa_wigig_tx_dp(enum ipa_client_type dst, + struct sk_buff *skb) +{ + return -EPERM; +} + +static inline int ipa_wigig_set_perf_profile(u32 max_supported_bw_mbps) +{ + return -EPERM; +} +#endif /* IS_ENABLED(CONFIG_IPA3) */ +#endif /* _IPA_WIGIG_H_ */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/include/linux/msm_gsi.h b/qcom/opensource/dataipa/drivers/platform/msm/include/linux/msm_gsi.h new file mode 100644 index 0000000000..0779fd7b2d --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/include/linux/msm_gsi.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef MSM_GSI_H +#define MSM_GSI_H +#include +#include + +enum gsi_chan_dir { + GSI_CHAN_DIR_FROM_GSI = 0x0, + GSI_CHAN_DIR_TO_GSI = 0x1 +}; + +/** + * @GSI_USE_PREFETCH_BUFS: Channel will use normal prefetch buffers if possible + * @GSI_ESCAPE_BUF_ONLY: Channel will always use escape buffers only + * @GSI_SMART_PRE_FETCH: Channel will work in smart prefetch mode. + * relevant starting GSI 2.5 + * @GSI_FREE_PRE_FETCH: Channel will work in free prefetch mode. + * relevant starting GSI 2.5 + */ +enum gsi_prefetch_mode { + GSI_USE_PREFETCH_BUFS = 0x0, + GSI_ESCAPE_BUF_ONLY = 0x1, + GSI_SMART_PRE_FETCH = 0x2, + GSI_FREE_PRE_FETCH = 0x3, +}; + +#endif diff --git a/qcom/opensource/dataipa/drivers/platform/msm/include/uapi/linux/ipa_qmi_service_v01.h b/qcom/opensource/dataipa/drivers/platform/msm/include/uapi/linux/ipa_qmi_service_v01.h new file mode 100644 index 0000000000..b962654e11 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/include/uapi/linux/ipa_qmi_service_v01.h @@ -0,0 +1,3236 @@ +/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ +/* + * Copyright (c) 2013-2021, The Linux Foundation. All rights reserved. + * + * Copyright (c) 2021-2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/* + * This header file defines the types and structures that were defined in + * ipa. It contains the constant values defined, enums, structures, + * messages, and service message IDs (in that order) Structures that were + * defined in the IDL as messages contain mandatory elements, optional + * elements, a combination of mandatory and optional elements (mandatory + * always come before optionals in the structure), or nothing (null message) + + * An optional element in a message is preceded by a __u8 value that must be + * set to true if the element is going to be included. When decoding a received + * message, the __u8 values will be set to true or false by the decode + * routine, and should be checked before accessing the values that they + * correspond to. + + * Variable sized arrays are defined as static sized arrays with an unsigned + * integer (32 bit) preceding it that must be set to the number of elements + * in the array that are valid. For Example: + + * __u32 test_opaque_len; + * __u8 test_opaque[16]; + + * If only 4 elements are added to test_opaque[] then test_opaque_len must be + * set to 4 before sending the message. When decoding, the _len value is set + * by the decode routine and should be checked so that the correct number of + * elements in the array will be accessed. + */ +#ifndef IPA_QMI_SERVICE_V01_H +#define IPA_QMI_SERVICE_V01_H + +#include + +#define QMI_IPA_REMOTE_MHI_CHANNELS_NUM_MAX_V01 6 +#define QMI_IPA_MAX_FILTERS_EX_V01 128 +#define QMI_IPA_MAX_FILTERS_EX2_V01 256 +#define QMI_IPA_IPFLTR_NUM_IHL_RANGE_16_EQNS_V01 2 +#define QMI_IPA_MAX_FILTERS_V01 64 +#define QMI_IPA_IPFLTR_NUM_MEQ_128_EQNS_V01 2 +#define QMI_IPA_MAX_IPV4_ADD_LEN_V01 34 +#define QMI_IPA_MAX_IPV6_ADD_LEN_V01 35 +#define QMI_IPA_IPV6_WORD_ADDR_LEN_V01 4 +#define QMI_IPA_MAX_ETH_HDR_SIZE_V01 64 +#define QMI_IPA_ENDP_DESC_NUM_MAX_V01 31 +#define QMI_IPA_MAX_APN_V01 8 +/* Currently max we can use is only 1. But for scalability purpose + * we are having max value as 8. + */ +#define QMI_IPA_MAX_CLIENT_DST_PIPES_V01 8 +#define QMI_IPA_IPFLTR_NUM_IHL_MEQ_32_EQNS_V01 2 +#define QMI_IPA_MAX_UL_FIREWALL_RULES_V01 64 +#define QMI_IPA_REMOTE_MHI_MEMORY_MAPPING_NUM_MAX_V01 6 +#define QMI_IPA_IPFLTR_NUM_MEQ_32_EQNS_V01 2 +#define QMI_IPA_MAX_PIPES_V01 20 +#define QMI_IPA_MAX_PER_CLIENTS_V01 64 + +/* + * Indicates presence of newly added member to support HW stats. + */ +#define IPA_QMI_SUPPORTS_STATS +#define IPA_QMI_SUPPORT_MHI_DEFAULT + +#define IPA_INT_MAX ((int)(~0U>>1)) +#define IPA_INT_MIN (-IPA_INT_MAX - 1) + +/* IPA definition as msm_qmi_interface.h */ + +enum ipa_qmi_result_type_v01 { + /* To force a 32 bit signed enum. Do not change or use*/ + IPA_QMI_RESULT_TYPE_MIN_ENUM_VAL_V01 = IPA_INT_MIN, + IPA_QMI_RESULT_SUCCESS_V01 = 0, + IPA_QMI_RESULT_FAILURE_V01 = 1, + IPA_QMI_RESULT_TYPE_MAX_ENUM_VAL_V01 = IPA_INT_MAX, +}; + +enum ipa_qmi_error_type_v01 { + /* To force a 32 bit signed enum. Do not change or use*/ + IPA_QMI_ERROR_TYPE_MIN_ENUM_VAL_V01 = IPA_INT_MIN, + IPA_QMI_ERR_NONE_V01 = 0x0000, + IPA_QMI_ERR_MALFORMED_MSG_V01 = 0x0001, + IPA_QMI_ERR_NO_MEMORY_V01 = 0x0002, + IPA_QMI_ERR_INTERNAL_V01 = 0x0003, + IPA_QMI_ERR_CLIENT_IDS_EXHAUSTED_V01 = 0x0005, + IPA_QMI_ERR_INVALID_ID_V01 = 0x0029, + IPA_QMI_ERR_ENCODING_V01 = 0x003A, + IPA_QMI_ERR_INCOMPATIBLE_STATE_V01 = 0x005A, + IPA_QMI_ERR_NOT_SUPPORTED_V01 = 0x005E, + IPA_QMI_ERROR_TYPE_MAX_ENUM_VAL_V01 = IPA_INT_MAX, +}; + +struct ipa_qmi_response_type_v01 { + __u16 result; + __u16 error; +}; + +enum ipa_platform_type_enum_v01 { + IPA_PLATFORM_TYPE_ENUM_MIN_ENUM_VAL_V01 = + -2147483647, /* To force a 32 bit signed enum. Do not change or use */ + QMI_IPA_PLATFORM_TYPE_INVALID_V01 = 0, + /* Invalid platform identifier */ + QMI_IPA_PLATFORM_TYPE_TN_V01 = 1, + /* Platform identifier - Data card device */ + QMI_IPA_PLATFORM_TYPE_LE_V01 = 2, + /* Platform identifier - Data router device */ + QMI_IPA_PLATFORM_TYPE_MSM_ANDROID_V01 = 3, + /* Platform identifier - MSM device with Android HLOS */ + QMI_IPA_PLATFORM_TYPE_MSM_WINDOWS_V01 = 4, + /* Platform identifier - MSM device with Windows HLOS */ + QMI_IPA_PLATFORM_TYPE_MSM_QNX_V01 = 5, + /* Platform identifier - MDM device with LE HLOS, MHI data router */ + QMI_IPA_PLATFORM_TYPE_LE_MHI_V01 = 6, + /* Platform identifier - MSM device with QNX HLOS */ + IPA_PLATFORM_TYPE_ENUM_MAX_ENUM_VAL_V01 = 2147483647 + /* To force a 32 bit signed enum. Do not change or use */ +}; + +#define QMI_IPA_PLATFORM_TYPE_LE_MHI_V01 \ + QMI_IPA_PLATFORM_TYPE_LE_MHI_V01 + +struct ipa_hdr_tbl_info_type_v01 { + __u32 modem_offset_start; + /* Offset from the start of IPA Shared memory from which + * modem driver may insert header table entries. + */ + __u32 modem_offset_end; + /* Offset from the start of IPA shared mem beyond which modem + * driver shall not insert header table entries. The space + * available for the modem driver shall include the + * modem_offset_start and modem_offset_end. + */ +}; /* Type */ + +struct ipa_route_tbl_info_type_v01 { + __u32 route_tbl_start_addr; + /* Identifies the start of the routing table. Denotes the offset + * from the start of the IPA Shared Mem + */ + + __u32 num_indices; + /* Number of indices (starting from 0) that is being allocated to + * the modem. The number indicated here is also included in the + * allocation. The value of num_indices shall not exceed 31 + * (5 bits used to specify the routing table index), unless there + * is a change in the hardware. + */ +}; /* Type */ + +#define IPA_RQOS_FILTER_STATS_INFO +struct ipa_filter_stats_info_type_v01 { + __u32 hw_filter_stats_start_addr; + /* Identifies the start of the filter stats. Denotes the offset + * from the start of the IPA Shared Mem + */ + + __u32 hw_filter_stats_size; + /* Identifies size in bytes of the HW filter statistics table. */ + + __u8 hw_filter_stats_start_index; + /* Identifies the start index of the modem driver managed + * indices in the hw filter statistics table. + */ + + __u8 hw_filter_stats_end_index; + /* Identifies the end index os the modem driver managed + * indices in the hw filter statistics table. + */ +}; /* Type */ + +struct ipa_modem_mem_info_type_v01 { + + __u32 block_start_addr; + /* Identifies the start of the memory block allocated for the + * modem. Denotes the offset from the start of the IPA Shared Mem + */ + + __u32 size; + /* Size of the block allocated for the modem driver */ +}; /* Type */ + +struct ipa_hdr_proc_ctx_tbl_info_type_v01 { + + __u32 modem_offset_start; + /* Offset from the start of IPA shared memory from which the modem + * driver may insert header processing context table entries. + */ + + __u32 modem_offset_end; + /* Offset from the start of IPA shared memory beyond which the modem + * driver may not insert header proc table entries. The space + * available for the modem driver includes modem_offset_start and + * modem_offset_end. + */ +}; /* Type */ + +struct ipa_zip_tbl_info_type_v01 { + + __u32 modem_offset_start; + /* Offset from the start of IPA shared memory from which the modem + * driver may insert compression/decompression command entries. + */ + + __u32 modem_offset_end; + /* Offset from the start of IPA shared memory beyond which the modem + * driver may not insert compression/decompression command entries. + * The space available for the modem driver includes + * modem_offset_start and modem_offset_end. + */ +}; /* Type */ + +/** + * Request Message; Requests the modem IPA driver + * to perform initialization + */ +struct ipa_init_modem_driver_req_msg_v01 { + + /* Optional */ + /* Platform info */ + __u8 platform_type_valid; + /* Must be set to true if platform_type is being passed */ + enum ipa_platform_type_enum_v01 platform_type; + /* Provides information about the platform (ex. TN/MN/LE/MSM,etc) */ + + /* Optional */ + /* Header table info */ + __u8 hdr_tbl_info_valid; + /* Must be set to true if hdr_tbl_info is being passed */ + struct ipa_hdr_tbl_info_type_v01 hdr_tbl_info; + /* Provides information about the header table */ + + /* Optional */ + /* IPV4 Routing table info */ + __u8 v4_route_tbl_info_valid; + /* Must be set to true if v4_route_tbl_info is being passed */ + struct ipa_route_tbl_info_type_v01 v4_route_tbl_info; + /* Provides information about the IPV4 routing table */ + + /* Optional */ + /* IPV6 Routing table info */ + __u8 v6_route_tbl_info_valid; + /* Must be set to true if v6_route_tbl_info is being passed */ + struct ipa_route_tbl_info_type_v01 v6_route_tbl_info; + /* Provides information about the IPV6 routing table */ + + /* Optional */ + /* IPV4 Filter table start address */ + __u8 v4_filter_tbl_start_addr_valid; + /* Must be set to true if v4_filter_tbl_start_addr is being passed */ + __u32 v4_filter_tbl_start_addr; + /* Provides information about the starting address of IPV4 filter + * table in IPAv2 or non-hashable IPv4 filter table in IPAv3. + * Denotes the offset from the start of the IPA Shared Mem + */ + + /* Optional */ + /* IPV6 Filter table start address */ + __u8 v6_filter_tbl_start_addr_valid; + /* Must be set to true if v6_filter_tbl_start_addr is being passed */ + __u32 v6_filter_tbl_start_addr; + /* Provides information about the starting address of IPV6 filter + * table in IPAv2 or non-hashable IPv6 filter table in IPAv3. + * Denotes the offset from the start of the IPA Shared Mem + */ + + /* Optional */ + /* Modem memory block */ + __u8 modem_mem_info_valid; + /* Must be set to true if modem_mem_info is being passed */ + struct ipa_modem_mem_info_type_v01 modem_mem_info; + /* Provides information about the start address and the size of + * the memory block that is being allocated to the modem driver. + * Denotes the physical address + */ + + /* Optional */ + /* Destination end point for control commands from modem */ + __u8 ctrl_comm_dest_end_pt_valid; + /* Must be set to true if ctrl_comm_dest_end_pt is being passed */ + __u32 ctrl_comm_dest_end_pt; + /* Provides information about the destination end point on the + * application processor to which the modem driver can send + * control commands. The value of this parameter cannot exceed + * 19 since IPA only supports 20 end points. + */ + + /* Optional */ + /* Modem Bootup Information */ + __u8 is_ssr_bootup_valid; + /* Must be set to true if is_ssr_bootup is being passed */ + __u8 is_ssr_bootup; + /* Specifies whether the modem is booting up after a modem only + * sub-system restart or not. This will let the modem driver + * know that it doesn't have to reinitialize some of the HW + * blocks because IPA has not been reset since the previous + * initialization. + */ + + /* Optional */ + /* Header Processing Context Table Information */ + __u8 hdr_proc_ctx_tbl_info_valid; + /* Must be set to true if hdr_proc_ctx_tbl_info is being passed */ + struct ipa_hdr_proc_ctx_tbl_info_type_v01 hdr_proc_ctx_tbl_info; + /* Provides information about the header processing context table. + */ + + /* Optional */ + /* Compression Decompression Table Information */ + __u8 zip_tbl_info_valid; + /* Must be set to true if zip_tbl_info is being passed */ + struct ipa_zip_tbl_info_type_v01 zip_tbl_info; + /* Provides information about the zip table. + */ + + /* Optional */ + /* IPv4 Hashable Routing Table Information */ + /** Must be set to true if v4_hash_route_tbl_info is being passed */ + __u8 v4_hash_route_tbl_info_valid; + struct ipa_route_tbl_info_type_v01 v4_hash_route_tbl_info; + + /* Optional */ + /* IPv6 Hashable Routing Table Information */ + /** Must be set to true if v6_hash_route_tbl_info is being passed */ + __u8 v6_hash_route_tbl_info_valid; + struct ipa_route_tbl_info_type_v01 v6_hash_route_tbl_info; + + /* + * Optional + * IPv4 Hashable Filter Table Start Address + * Must be set to true if v4_hash_filter_tbl_start_addr + * is being passed + */ + __u8 v4_hash_filter_tbl_start_addr_valid; + __u32 v4_hash_filter_tbl_start_addr; + /* Identifies the starting address of the IPv4 hashable filter + * table in IPAv3 onwards. Denotes the offset from the start of + * the IPA shared memory. + */ + + /* Optional + * IPv6 Hashable Filter Table Start Address + * Must be set to true if v6_hash_filter_tbl_start_addr + * is being passed + */ + __u8 v6_hash_filter_tbl_start_addr_valid; + __u32 v6_hash_filter_tbl_start_addr; + /* Identifies the starting address of the IPv6 hashable filter + * table in IPAv3 onwards. Denotes the offset from the start of + * the IPA shared memory. + */ + + /* Optional + * Modem HW Stats Quota Base address + * Must be set to true if hw_stats_quota_base_addr + * is being passed + */ + __u8 hw_stats_quota_base_addr_valid; + __u32 hw_stats_quota_base_addr; + + /* Optional + * Modem HW Stats Quota Size + * Must be set to true if hw_stats_quota_size + * is being passed + */ + __u8 hw_stats_quota_size_valid; + __u32 hw_stats_quota_size; + + /* Optional + * Modem HW Drop Stats Table Start Address + * Must be set to true if hw_drop_stats_base_addr + * is being passed + */ + __u8 hw_drop_stats_base_addr_valid; + __u32 hw_drop_stats_base_addr; + + /* Optional + * Modem HW Drop Stats Table size + * Must be set to true if hw_drop_stats_table_size + * is being passed + */ + __u8 hw_drop_stats_table_size_valid; + __u32 hw_drop_stats_table_size; + + /* optional + * Modem HW flt stats info + * Must be set to true if filter_stats_info + * is being passed + */ + __u8 hw_fiter_stats_info_valid; + struct ipa_filter_stats_info_type_v01 hw_filter_stats_info; + + /* optional + * Filter table smem info + * Must be set to true if smem_info + * is being passed(Currently not using it) + */ + __u8 smem_info_valid; + struct ipa_modem_mem_info_type_v01 smem_info; + + /* optional + * IPA Peripheral stats info + * Must be set to true if per_stats_info + * is being passed + */ + __u8 per_stats_smem_info_valid; + struct ipa_modem_mem_info_type_v01 per_stats_smem_info; +}; /* Message */ + +/* Response Message; Requests the modem IPA driver about initialization */ +struct ipa_init_modem_driver_resp_msg_v01 { + /* Mandatory */ + /* Result Code */ + struct ipa_qmi_response_type_v01 resp; + /* Standard response type.*/ + + /* Optional */ + /* Destination end point for control commands from master driver */ + __u8 ctrl_comm_dest_end_pt_valid; + /* Must be set to true if ctrl_comm_dest_ep is being passed */ + __u32 ctrl_comm_dest_end_pt; + /* Provides information about the destination end point on the + * modem processor to which the master driver can send control + * commands. The value of this parameter cannot exceed 19 since + * IPA only supports 20 end points. This field is looked at only + * if the result in TLV RESULT_CODE is QMI_RESULT_SUCCESS + */ + + /* Optional */ + /* Default end point */ + __u8 default_end_pt_valid; + /* Must be set to true if default_end_pt is being passed */ + __u32 default_end_pt; + /* Provides information about the default end point. The master + * driver may or may not set the register in the hardware with + * this value. The value of this parameter cannot exceed 19 + * since IPA only supports 20 end points. This field is looked + * at only if the result in TLV RESULT_CODE is QMI_RESULT_SUCCESS + */ + + /* Optional */ + /* Modem Driver Initialization Pending */ + __u8 modem_driver_init_pending_valid; + /* Must be set to true if modem_driver_init_pending is being passed */ + __u8 modem_driver_init_pending; + /* + * Identifies if second level message handshake is needed + * between drivers to indicate when IPA HWP loading is completed. + * If this is set by modem driver, AP driver will need to wait + * for a INIT_MODEM_DRIVER_CMPLT message before communicating with + * IPA HWP. + */ +}; /* Message */ + +/* + * Request Message; Request from Modem IPA driver to indicate + * modem driver init completion + */ +struct ipa_init_modem_driver_cmplt_req_msg_v01 { + /* Mandatory */ + /* Modem Driver init complete status; */ + __u8 status; + /* + * Specifies whether the modem driver initialization is complete + * including the micro controller image loading. + */ +}; /* Message */ + +/* + * Response Message; Request from Modem IPA driver to indicate + * modem driver init completion + */ +struct ipa_init_modem_driver_cmplt_resp_msg_v01 { + /* Mandatory */ + /* Result Code */ + struct ipa_qmi_response_type_v01 resp; + /**< Standard response type.*/ +}; /* Message */ + +/* Request Message; This is the message that is exchanged between the + * control point and the service in order to register for indications. + */ +struct ipa_indication_reg_req_msg_v01 { + /* Optional */ + /* Master driver initialization completion */ + __u8 master_driver_init_complete_valid; + /* Must be set to true if master_driver_init_complete is being passed */ + __u8 master_driver_init_complete; + /* If set to TRUE, this field indicates that the client is + * interested in getting indications about the completion + * of the initialization sequence of the master driver. + * Setting this field in the request message makes sense + * only when the QMI_IPA_INDICATION_REGISTER_REQ is being + * originated from the modem driver + */ + + /* Optional */ + /* Data Usage Quota Reached */ + __u8 data_usage_quota_reached_valid; + /* Must be set to true if data_usage_quota_reached is being passed */ + __u8 data_usage_quota_reached; + /* If set to TRUE, this field indicates that the client wants to + * receive indications about reaching the data usage quota that + * previously set via QMI_IPA_SET_DATA_USAGE_QUOTA. Setting this field + * in the request message makes sense only when the + * QMI_IPA_INDICATION_REGISTER_REQ is being originated from the Master + * driver + */ + + /* Optional */ + /* IPA MHI Ready Indication */ + __u8 ipa_mhi_ready_ind_valid; + /* Must be set to true if ipa_mhi_ready_ind is being passed */ + __u8 ipa_mhi_ready_ind; + /* + * If set to TRUE, this field indicates that the client wants to + * receive indications about MHI ready for Channel allocations. + */ + + /* Optional */ + /* Endpoint Desc Info Indication */ + __u8 endpoint_desc_ind_valid; + /* Must be set to true if endpoint_desc_ind is being passed */ + __u8 endpoint_desc_ind; + /* + * If set to TRUE, this field indicates that the client wants to + * receive indications for Endpoint descriptor information via + * QMI_IPA_ENDP_DESC_INDICATION. Setting this field in the request + * message makes sense only when the QMI_IPA_INDICATION_REGISTER_REQ + * is being originated from the master driver. + */ + + /* Optional */ + /* BW CHANGE Indication */ + __u8 bw_change_ind_valid; + /* Must be set to true if bw_change_ind is being passed */ + __u8 bw_change_ind; + /* + * If set to TRUE, this field indicates that the client wants to + * receive indications for BW change information via + * QMI_IPA_BW_CHANGE_INDICATION. Setting this field in the request + * message makes sense only when the QMI_IPA_INDICATION_REGISTER_REQ + * is being originated from the master driver. + */ +}; /* Message */ + + +/* Response Message; This is the message that is exchanged between the + * control point and the service in order to register for indications. + */ +struct ipa_indication_reg_resp_msg_v01 { + /* Mandatory */ + /* Result Code */ + struct ipa_qmi_response_type_v01 resp; + /**< Standard response type.*/ +}; /* Message */ + + +/* Indication Message; Indication sent to the Modem IPA driver from + * master IPA driver about initialization being complete. + */ +struct ipa_master_driver_init_complt_ind_msg_v01 { + /* Mandatory */ + /* Master driver initialization completion status */ + struct ipa_qmi_response_type_v01 master_driver_init_status; + /* Indicates the status of initialization. If everything went + * as expected, this field is set to SUCCESS. ERROR is set + * otherwise. Extended error info may be used to convey + * additional information about the error + */ +}; /* Message */ + +struct ipa_ipfltr_range_eq_16_type_v01 { + __u8 offset; + /* Specifies the offset from the IHL (Internet Header length) */ + + __u16 range_low; + /* Specifies the lower bound of the range */ + + __u16 range_high; + /* Specifies the upper bound of the range */ +}; /* Type */ + +struct ipa_ipfltr_mask_eq_32_type_v01 { + __u8 offset; + /* Specifies the offset either from IHL or from the start of + * the IP packet. This depends on the equation that this structure + * is used in. + */ + + __u32 mask; + /* Specifies the mask that has to be used in the comparison. + * The field is ANDed with the mask and compared against the value. + */ + + __u32 value; + /* Specifies the 32 bit value that used in the comparison. */ +}; /* Type */ + +struct ipa_ipfltr_eq_16_type_v01 { + __u8 offset; + /* Specifies the offset into the packet */ + + __u16 value; + /* Specifies the 16 bit value that should be used in the comparison. */ +}; /* Type */ + +struct ipa_ipfltr_eq_32_type_v01 { + __u8 offset; + /* Specifies the offset into the packet */ + + __u32 value; + /* Specifies the 32 bit value that should be used in the comparison. */ +}; /* Type */ + +struct ipa_ipfltr_mask_eq_128_type_v01 { + __u8 offset; + /* Specifies the offset into the packet */ + + __u8 mask[16]; + /* Specifies the mask that has to be used in the comparison. + * The field is ANDed with the mask and compared against the value. + */ + + __u8 value[16]; + /* Specifies the 128 bit value that should be used in the comparison. */ +}; /* Type */ + + +struct ipa_filter_rule_type_v01 { + __u16 rule_eq_bitmap; + /* 16-bit Bitmask to indicate how many eqs are valid in this rule */ + + __u8 tos_eq_present; + /* + * tos_eq_present field has two meanings: + * IPA ver < 4.5: + * specifies if a type of service check rule is present + * (as the field name reveals). + * IPA ver >= 4.5: + * specifies if a tcp pure ack check rule is present + */ + + __u8 tos_eq; + /* The value to check against the type of service (ipv4) field */ + + __u8 protocol_eq_present; + /* Specifies if a protocol check rule is present */ + + __u8 protocol_eq; + /* The value to check against the protocol field */ + + __u8 num_ihl_offset_range_16; + /* The number of 16 bit range check rules at the location + * determined by IP header length plus a given offset + * in this rule. See the definition of the ipa_filter_range_eq_16 + * for better understanding. The value of this field cannot exceed + * IPA_IPFLTR_NUM_IHL_RANGE_16_EQNS which is set as 2 + */ + + struct ipa_ipfltr_range_eq_16_type_v01 + ihl_offset_range_16[QMI_IPA_IPFLTR_NUM_IHL_RANGE_16_EQNS_V01]; + /* Array of the registered IP header length offset 16 bit range + * check rules. + */ + + __u8 num_offset_meq_32; + /* The number of 32 bit masked comparison rules present + * in this rule + */ + + struct ipa_ipfltr_mask_eq_32_type_v01 + offset_meq_32[QMI_IPA_IPFLTR_NUM_MEQ_32_EQNS_V01]; + /* An array of all the possible 32bit masked comparison rules + * in this rule + */ + + __u8 tc_eq_present; + /* Specifies if the traffic class rule is present in this rule */ + + __u8 tc_eq; + /* The value against which the IPV4 traffic class field has to + * be checked + */ + + __u8 flow_eq_present; + /* Specifies if the "flow equals" rule is present in this rule */ + + __u32 flow_eq; + /* The value against which the IPV6 flow field has to be checked */ + + __u8 ihl_offset_eq_16_present; + /* Specifies if there is a 16 bit comparison required at the + * location in the packet determined by "Intenet Header length + * + specified offset" + */ + + struct ipa_ipfltr_eq_16_type_v01 ihl_offset_eq_16; + /* The 16 bit comparison equation */ + + __u8 ihl_offset_eq_32_present; + /* Specifies if there is a 32 bit comparison required at the + * location in the packet determined by "Intenet Header length + * + specified offset" + */ + + struct ipa_ipfltr_eq_32_type_v01 ihl_offset_eq_32; + /* The 32 bit comparison equation */ + + __u8 num_ihl_offset_meq_32; + /* The number of 32 bit masked comparison equations in this + * rule. The location of the packet to be compared is + * determined by the IP Header length + the give offset + */ + + struct ipa_ipfltr_mask_eq_32_type_v01 + ihl_offset_meq_32[QMI_IPA_IPFLTR_NUM_IHL_MEQ_32_EQNS_V01]; + /* Array of 32 bit masked comparison equations. + */ + + __u8 num_offset_meq_128; + /* The number of 128 bit comparison equations in this rule */ + + struct ipa_ipfltr_mask_eq_128_type_v01 + offset_meq_128[QMI_IPA_IPFLTR_NUM_MEQ_128_EQNS_V01]; + /* Array of 128 bit comparison equations. The location in the + * packet is determined by the specified offset + */ + + __u8 metadata_meq32_present; + /* Boolean indicating if the 32 bit masked comparison equation + * is present or not. Comparison is done against the metadata + * in IPA. Metadata can either be extracted from the packet + * header or from the "metadata" register. + */ + + struct ipa_ipfltr_mask_eq_32_type_v01 + metadata_meq32; + /* The metadata 32 bit masked comparison equation */ + + __u8 ipv4_frag_eq_present; + /* Specifies if the IPv4 Fragment equation is present in this rule */ +}; /* Type */ + + +struct ipa_filter_rule_req2_type_v01 { + __u16 rule_eq_bitmap; + /* 16-bit Bitmask to indicate how many eqs are valid in this rule */ + + __u8 pure_ack_eq_present; + /* + * specifies if a tcp pure ack check rule is present + */ + + __u8 pure_ack_eq; + /* The value to check against the type of service (ipv4) field */ + + __u8 protocol_eq_present; + /* Specifies if a protocol check rule is present */ + + __u8 protocol_eq; + /* The value to check against the protocol field */ + + __u8 num_ihl_offset_range_16; + /* The number of 16 bit range check rules at the location + * determined by IP header length plus a given offset + * in this rule. See the definition of the ipa_filter_range_eq_16 + * for better understanding. The value of this field cannot exceed + * IPA_IPFLTR_NUM_IHL_RANGE_16_EQNS which is set as 2 + */ + + struct ipa_ipfltr_range_eq_16_type_v01 + ihl_offset_range_16[QMI_IPA_IPFLTR_NUM_IHL_RANGE_16_EQNS_V01]; + /* Array of the registered IP header length offset 16 bit range + * check rules. + */ + + __u8 num_offset_meq_32; + /* The number of 32 bit masked comparison rules present + * in this rule + */ + + struct ipa_ipfltr_mask_eq_32_type_v01 + offset_meq_32[QMI_IPA_IPFLTR_NUM_MEQ_32_EQNS_V01]; + /* An array of all the possible 32bit masked comparison rules + * in this rule + */ + + __u8 tc_eq_present; + /* Specifies if the traffic class rule is present in this rule */ + + __u8 tc_eq; + /* The value against which the IPV4 traffic class field has to + * be checked + */ + + __u8 flow_eq_present; + /* Specifies if the "flow equals" rule is present in this rule */ + + __u32 flow_eq; + /* The value against which the IPV6 flow field has to be checked */ + + __u8 ihl_offset_eq_16_present; + /* Specifies if there is a 16 bit comparison required at the + * location in the packet determined by "Intenet Header length + * + specified offset" + */ + + struct ipa_ipfltr_eq_16_type_v01 ihl_offset_eq_16; + /* The 16 bit comparison equation */ + + __u8 ihl_offset_eq_32_present; + /* Specifies if there is a 32 bit comparison required at the + * location in the packet determined by "Intenet Header length + * + specified offset" + */ + + struct ipa_ipfltr_eq_32_type_v01 ihl_offset_eq_32; + /* The 32 bit comparison equation */ + + __u8 num_ihl_offset_meq_32; + /* The number of 32 bit masked comparison equations in this + * rule. The location of the packet to be compared is + * determined by the IP Header length + the give offset + */ + + struct ipa_ipfltr_mask_eq_32_type_v01 + ihl_offset_meq_32[QMI_IPA_IPFLTR_NUM_IHL_MEQ_32_EQNS_V01]; + /* Array of 32 bit masked comparison equations. + */ + + __u8 num_offset_meq_128; + /* The number of 128 bit comparison equations in this rule */ + + struct ipa_ipfltr_mask_eq_128_type_v01 + offset_meq_128[QMI_IPA_IPFLTR_NUM_MEQ_128_EQNS_V01]; + /* Array of 128 bit comparison equations. The location in the + * packet is determined by the specified offset + */ + + __u8 metadata_meq32_present; + /* Boolean indicating if the 32 bit masked comparison equation + * is present or not. Comparison is done against the metadata + * in IPA. Metadata can either be extracted from the packet + * header or from the "metadata" register. + */ + + struct ipa_ipfltr_mask_eq_32_type_v01 + metadata_meq32; + /* The metadata 32 bit masked comparison equation */ + + __u8 ipv4_frag_eq_present; + /* Specifies if the IPv4 Fragment equation is present in this rule */ +}; /* Type */ + +enum ipa_ip_type_enum_v01 { + IPA_IP_TYPE_ENUM_MIN_ENUM_VAL_V01 = -2147483647, + /* To force a 32 bit signed enum. Do not change or use*/ + QMI_IPA_IP_TYPE_INVALID_V01 = 0, + /* Invalid IP type identifier */ + QMI_IPA_IP_TYPE_V4_V01 = 1, + /* IP V4 type */ + QMI_IPA_IP_TYPE_V6_V01 = 2, + /* IP V6 type */ + QMI_IPA_IP_TYPE_V4V6_V01 = 3, + /* Applies to both IP types */ + IPA_IP_TYPE_ENUM_MAX_ENUM_VAL_V01 = 2147483647 + /* To force a 32 bit signed enum. Do not change or use*/ +}; + + +enum ipa_filter_action_enum_v01 { + IPA_FILTER_ACTION_ENUM_MIN_ENUM_VAL_V01 = -2147483647, + /* To force a 32 bit signed enum. Do not change or use */ + QMI_IPA_FILTER_ACTION_INVALID_V01 = 0, + /* Invalid action on filter hit */ + QMI_IPA_FILTER_ACTION_SRC_NAT_V01 = 1, + /* Pass packet to NAT block for Source NAT */ + QMI_IPA_FILTER_ACTION_DST_NAT_V01 = 2, + /* Pass packet to NAT block for Destination NAT */ + QMI_IPA_FILTER_ACTION_ROUTING_V01 = 3, + /* Pass packet to Routing block */ + QMI_IPA_FILTER_ACTION_EXCEPTION_V01 = 4, + /* Treat packet as exception and send to exception pipe */ + IPA_FILTER_ACTION_ENUM_MAX_ENUM_VAL_V01 = 2147483647 + /* To force a 32 bit signed enum. Do not change or use*/ +}; + +struct ipa_filter_spec_type_v01 { + __u32 filter_spec_identifier; + /* This field is used to identify a filter spec in the list + * of filter specs being sent from the client. This field + * is applicable only in the filter install request and response. + */ + + enum ipa_ip_type_enum_v01 ip_type; + /* This field identifies the IP type for which this rule is + * applicable. The driver needs to identify the filter table + * (V6 or V4) and this field is essential for that + */ + + struct ipa_filter_rule_type_v01 filter_rule; + /* This field specifies the rules in the filter spec. These rules + * are the ones that are matched against fields in the packet. + */ + + enum ipa_filter_action_enum_v01 filter_action; + /* This field specifies the action to be taken when a filter match + * occurs. The remote side should install this information into the + * hardware along with the filter equations. + */ + + __u8 is_routing_table_index_valid; + /* Specifies whether the routing table index is present or not. + * If the action is "QMI_IPA_FILTER_ACTION_EXCEPTION", this + * parameter need not be provided. + */ + + __u32 route_table_index; + /* This is the index in the routing table that should be used + * to route the packets if the filter rule is hit + */ + + __u8 is_mux_id_valid; + /* Specifies whether the mux_id is valid */ + + __u32 mux_id; + /* This field identifies the QMAP MUX ID. As a part of QMAP + * protocol, several data calls may be multiplexed over the + * same physical transport channel. This identifier is used to + * identify one such data call. The maximum value for this + * identifier is 255. + */ +}; /* Type */ + +struct ipa_filter_spec_ex_type_v01 { + enum ipa_ip_type_enum_v01 ip_type; + /* This field identifies the IP type for which this rule is + * applicable. The driver needs to identify the filter table + * (V6 or V4) and this field is essential for that + */ + + struct ipa_filter_rule_type_v01 filter_rule; + /* This field specifies the rules in the filter spec. These rules + * are the ones that are matched against fields in the packet. + */ + + enum ipa_filter_action_enum_v01 filter_action; + /* This field specifies the action to be taken when a filter match + * occurs. The remote side should install this information into the + * hardware along with the filter equations. + */ + + __u8 is_routing_table_index_valid; + /* Specifies whether the routing table index is present or not. + * If the action is "QMI_IPA_FILTER_ACTION_EXCEPTION", this + * parameter need not be provided. + */ + + __u32 route_table_index; + /* This is the index in the routing table that should be used + * to route the packets if the filter rule is hit + */ + + __u8 is_mux_id_valid; + /* Specifies whether the mux_id is valid */ + + __u32 mux_id; + /* This field identifies the QMAP MUX ID. As a part of QMAP + * protocol, several data calls may be multiplexed over the + * same physical transport channel. This identifier is used to + * identify one such data call. The maximum value for this + * identifier is 255. + */ + + __u32 rule_id; + /* Rule Id of the given filter. The Rule Id is populated in the rule + * header when installing the rule in IPA. + */ + + __u8 is_rule_hashable; + /** Specifies whether the given rule is hashable. + */ +}; /* Type */ + +struct ipa_filter_spec_ex2_type_v01 { + enum ipa_ip_type_enum_v01 ip_type; + /* This field identifies the IP type for which this rule is + * applicable. The driver needs to identify the filter table + * (V6 or V4) and this field is essential for that + */ + + struct ipa_filter_rule_req2_type_v01 filter_rule; + /* This field specifies the rules in the filter spec. These rules + * are the ones that are matched against fields in the packet. + */ + + enum ipa_filter_action_enum_v01 filter_action; + /* This field specifies the action to be taken when a filter match + * occurs. The remote side should install this information into the + * hardware along with the filter equations. + */ + + __u8 is_routing_table_index_valid; + /* Specifies whether the routing table index is present or not. + * If the action is "QMI_IPA_FILTER_ACTION_EXCEPTION", this + * parameter need not be provided. + */ + + __u32 route_table_index; + /* This is the index in the routing table that should be used + * to route the packets if the filter rule is hit + */ + + __u8 is_mux_id_valid; + /* Specifies whether the mux_id is valid */ + + __u32 mux_id; + /* This field identifies the QMAP MUX ID. As a part of QMAP + * protocol, several data calls may be multiplexed over the + * same physical transport channel. This identifier is used to + * identify one such data call. The maximum value for this + * identifier is 255. + */ + + __u32 rule_id; + /* Rule Id of the given filter. The Rule Id is populated in the rule + * header when installing the rule in IPA. + */ + + __u8 is_rule_hashable; + /** Specifies whether the given rule is hashable. + */ +}; /* Type */ + +/* Request Message; This is the message that is exchanged between the + * control point and the service in order to request the installation + * of filtering rules in the hardware block by the remote side. + */ +struct ipa_install_fltr_rule_req_msg_v01 { + /* Optional + * IP type that this rule applies to + * Filter specification to be installed in the hardware + */ + __u8 filter_spec_list_valid; + /* Must be set to true if filter_spec_list is being passed */ + __u32 filter_spec_list_len; + /* Must be set to # of elements in filter_spec_list */ + struct ipa_filter_spec_type_v01 + filter_spec_list[QMI_IPA_MAX_FILTERS_V01]; + /* This structure defines the list of filters that have + * to be installed in the hardware. The driver installing + * these rules shall do so in the same order as specified + * in this list. + */ + + /* Optional */ + /* Pipe index to intall rule */ + __u8 source_pipe_index_valid; + /* Must be set to true if source_pipe_index is being passed */ + __u32 source_pipe_index; + /* This is the source pipe on which the filter rule is to be + * installed. The requestor may always not know the pipe + * indices. If not specified, the receiver shall install + * this rule on all the pipes that it controls through + * which data may be fed into IPA. + */ + + /* Optional */ + /* Total number of IPv4 filters in the filter spec list */ + __u8 num_ipv4_filters_valid; + /* Must be set to true if num_ipv4_filters is being passed */ + __u32 num_ipv4_filters; + /* Number of IPv4 rules included in filter spec list */ + + /* Optional */ + /* Total number of IPv6 filters in the filter spec list */ + __u8 num_ipv6_filters_valid; + /* Must be set to true if num_ipv6_filters is being passed */ + __u32 num_ipv6_filters; + /* Number of IPv6 rules included in filter spec list */ + + /* Optional */ + /* List of XLAT filter indices in the filter spec list */ + __u8 xlat_filter_indices_list_valid; + /* Must be set to true if xlat_filter_indices_list + * is being passed + */ + __u32 xlat_filter_indices_list_len; + /* Must be set to # of elements in xlat_filter_indices_list */ + __u32 xlat_filter_indices_list[QMI_IPA_MAX_FILTERS_V01]; + /* List of XLAT filter indices. Filter rules at specified indices + * will need to be modified by the receiver if the PDN is XLAT + * before installing them on the associated IPA consumer pipe. + */ + + /* Optional */ + /* Extended Filter Specification */ + __u8 filter_spec_ex_list_valid; + /* Must be set to true if filter_spec_ex_list is being passed */ + __u32 filter_spec_ex_list_len; + /* Must be set to # of elements in filter_spec_ex_list */ + struct ipa_filter_spec_ex_type_v01 + filter_spec_ex_list[QMI_IPA_MAX_FILTERS_V01]; + /* + * List of filter specifications of filters that must be installed in + * the IPAv3.x hardware. + * The driver installing these rules must do so in the same + * order as specified in this list. + */ + + /* Optional */ + /* Extended Type 2 Filter Specification */ + __u8 filter_spec_ex2_list_valid; + /* Must be set to true if filter_spec_ex2_list is being passed */ + __u32 filter_spec_ex2_list_len; + /* Must be set to # of elements in filter_spec_ex2_list */ + struct ipa_filter_spec_ex2_type_v01 + filter_spec_ex2_list[QMI_IPA_MAX_FILTERS_V01]; + + /* Optional */ + /* List of modem UL Filters in the Spec List which need be to + * replicated with AP UL firewall filters + */ + __u8 ul_firewall_indices_list_valid; + /* Must be set to # of elements in ul_firewall_indices_list */ + __u32 ul_firewall_indices_list_len; + __u32 ul_firewall_indices_list[QMI_IPA_MAX_FILTERS_V01]; + /* List of UL firewall filter indices. + * Filter rules at specified indices must be replicated across + * the firewall filters by the receiver and installed on the + * associated IPA consumer pipe. + */ +}; /* Message */ + +struct ipa_filter_rule_identifier_to_handle_map_v01 { + __u32 filter_spec_identifier; + /* This field is used to identify a filter spec in the list of + * filter specs being sent from the client. This field is + * applicable only in the filter install request and response. + */ + __u32 filter_handle; + /* This field is used to identify a rule in any subsequent message. + * This is a value that is provided by the server to the control + * point + */ +}; /* Type */ + +/* Response Message; This is the message that is exchanged between the + * control point and the service in order to request the + * installation of filtering rules in the hardware block by + * the remote side. + */ +struct ipa_install_fltr_rule_resp_msg_v01 { + /* Mandatory */ + /* Result Code */ + struct ipa_qmi_response_type_v01 resp; + /* Standard response type. + * Standard response type. Contains the following data members: + * - qmi_result_type -- QMI_RESULT_SUCCESS or QMI_RESULT_FAILURE + * - qmi_error_type -- Error code. Possible error code values are + * described in the error codes section of each message definition. + */ + + /* Optional */ + /* Filter Handle List */ + __u8 filter_handle_list_valid; + /* Must be set to true if filter_handle_list is being passed */ + __u32 filter_handle_list_len; + /* Must be set to # of elements in filter_handle_list */ + struct ipa_filter_rule_identifier_to_handle_map_v01 + filter_handle_list[QMI_IPA_MAX_FILTERS_V01]; + /* + * List of handles returned to the control point. Each handle is + * mapped to the rule identifier that was specified in the + * request message. Any further reference to the rule is done + * using the filter handle. + */ + + /* Optional */ + /* Rule id List */ + __u8 rule_id_valid; + /* Must be set to true if rule_id is being passed */ + __u32 rule_id_len; + /* Must be set to # of elements in rule_id */ + __u32 rule_id[QMI_IPA_MAX_FILTERS_V01]; + /* + * List of rule ids returned to the control point. + * Any further reference to the rule is done using the + * filter rule id specified in this list. + */ +}; /* Message */ + +struct ipa_filter_handle_to_index_map_v01 { + __u32 filter_handle; + /* This is a handle that was given to the remote client that + * requested the rule addition. + */ + __u32 filter_index; + /* This index denotes the location in a filter table, where the + * filter rule has been installed. The maximum value of this + * field is 64. + */ +}; /* Type */ + +/* Request Message; This is the message that is exchanged between the + * control point and the service in order to notify the remote driver + * of the installation of the filter rule supplied earlier by the + * remote driver. + */ +struct ipa_fltr_installed_notif_req_msg_v01 { + /* Mandatory */ + /* Pipe index */ + __u32 source_pipe_index; + /* This is the source pipe on which the filter rule has been + * installed or was attempted to be installed + */ + + /* Mandatory */ + /* Installation Status */ + enum ipa_qmi_result_type_v01 install_status; + /* This is the status of installation. If this indicates + * SUCCESS, other optional fields carry additional + * information + */ + + /* Mandatory */ + /* List of Filter Indices */ + __u32 filter_index_list_len; + /* Must be set to # of elements in filter_index_list */ + struct ipa_filter_handle_to_index_map_v01 + filter_index_list[QMI_IPA_MAX_FILTERS_V01]; + /* + * Provides the list of filter indices and the corresponding + * filter handle. If the installation_status indicates a + * failure, the filter indices must be set to a reserve + * index (255). + */ + + /* Optional */ + /* Embedded pipe index */ + __u8 embedded_pipe_index_valid; + /* Must be set to true if embedded_pipe_index is being passed */ + __u32 embedded_pipe_index; + /* This index denotes the embedded pipe number on which a call to + * the same PDN has been made. If this field is set, it denotes + * that this is a use case where PDN sharing is happening. The + * embedded pipe is used to send data from the embedded client + * in the device + */ + + /* Optional */ + /* Retain Header Configuration */ + __u8 retain_header_valid; + /* Must be set to true if retain_header is being passed */ + __u8 retain_header; + /* This field indicates if the driver installing the rule has + * turned on the "retain header" bit. If this is true, the + * header that is removed by IPA is reinserted after the + * packet processing is completed. + */ + + /* Optional */ + /* Embedded call Mux Id */ + __u8 embedded_call_mux_id_valid; + /**< Must be set to true if embedded_call_mux_id is being passed */ + __u32 embedded_call_mux_id; + /* This identifies one of the many calls that have been originated + * on the embedded pipe. This is how we identify the PDN gateway + * to which traffic from the source pipe has to flow. + */ + + /* Optional */ + /* Total number of IPv4 filters in the filter index list */ + __u8 num_ipv4_filters_valid; + /* Must be set to true if num_ipv4_filters is being passed */ + __u32 num_ipv4_filters; + /* Number of IPv4 rules included in filter index list */ + + /* Optional */ + /* Total number of IPv6 filters in the filter index list */ + __u8 num_ipv6_filters_valid; + /* Must be set to true if num_ipv6_filters is being passed */ + __u32 num_ipv6_filters; + /* Number of IPv6 rules included in filter index list */ + + /* Optional */ + /* Start index on IPv4 filters installed on source pipe */ + __u8 start_ipv4_filter_idx_valid; + /* Must be set to true if start_ipv4_filter_idx is being passed */ + __u32 start_ipv4_filter_idx; + /* Start index of IPv4 rules in filter index list */ + + /* Optional */ + /* Start index on IPv6 filters installed on source pipe */ + __u8 start_ipv6_filter_idx_valid; + /* Must be set to true if start_ipv6_filter_idx is being passed */ + __u32 start_ipv6_filter_idx; + /* Start index of IPv6 rules in filter index list */ + + /* Optional */ + /* List of Rule Ids */ + __u8 rule_id_valid; + /* Must be set to true if rule_id is being passed */ + __u32 rule_id_len; + /* Must be set to # of elements in rule_id */ + __u32 rule_id[QMI_IPA_MAX_FILTERS_V01]; + /* + * Provides the list of Rule Ids of rules added in IPA on the given + * source pipe index. If the install_status TLV indicates a + * failure, the Rule Ids in this list must be set to a reserved + * index (255). + */ + + /* Optional */ + /* List of destination pipe IDs. */ + __u8 dst_pipe_id_valid; + /* Must be set to true if dst_pipe_id is being passed. */ + __u32 dst_pipe_id_len; + /* Must be set to # of elements in dst_pipe_id. */ + __u32 dst_pipe_id[QMI_IPA_MAX_CLIENT_DST_PIPES_V01]; + /* Provides the list of destination pipe IDs for a source pipe. */ + + /* Optional */ + /* List of Rule IDs extended */ + __u8 rule_id_ex_valid; + /* Must be set to true if rule_id_ex is being passed. */ + __u32 rule_id_ex_len; + /* Must be set to # of elements in rule_id_ex */ + __u32 rule_id_ex[QMI_IPA_MAX_FILTERS_EX2_V01]; + /* Provides the list of Rule IDs of rules added in IPA on the + * given source pipe index. If the install_status TLV indicates + * a failure, the Rule IDs in this list must be set to a + * reserved index (255). + */ +}; /* Message */ + +/* Response Message; This is the message that is exchanged between the + * control point and the service in order to notify the remote driver + * of the installation of the filter rule supplied earlier by the + * remote driver. + */ +struct ipa_fltr_installed_notif_resp_msg_v01 { + /* Mandatory */ + /* Result Code */ + struct ipa_qmi_response_type_v01 resp; + /* Standard response type */ +}; /* Message */ + +/* Request Message; Notifies the remote driver of the need to clear the data + * path to prevent the IPA from being blocked at the head of the processing + * pipeline + */ +struct ipa_enable_force_clear_datapath_req_msg_v01 { + /* Mandatory */ + /* Pipe Mask */ + __u32 source_pipe_bitmask; + /* Set of consumer (source) pipes that must be clear of + * active data transfers. + */ + + /* Mandatory */ + /* Request ID */ + __u32 request_id; + /* Identifies the ID of the request that is sent to the server + * The same request ID is used in the message to remove the force_clear + * request. The server is expected to keep track of the request ID and + * the source_pipe_bitmask so that it can revert as needed + */ + + /* Optional */ + /* Source Throttle State */ + __u8 throttle_source_valid; + /* Must be set to true if throttle_source is being passed */ + __u8 throttle_source; + /* Specifies whether the server is to throttle the data from + * these consumer (source) pipes after clearing the exisiting + * data present in the IPA that were pulled from these pipes + * The server is expected to put all the source pipes in the + * source_pipe_bitmask in the same state + */ + + /* Optional */ + /* Pipe Mask Ext State */ + __u8 source_pipe_bitmask_ext_valid; + /* Pipe Mask Ext */ + __u32 source_pipe_bitmask_ext[4]; + /* Set of consumer (source) pipes that must be clear of + * active data transfers. + * The extended mask supports up to 128 endpoints to accommodate newer + * architectures, which use more than 32 endpoints. + * If this new field is used, the old field source_pipe_bitmask + * shall be ignored. + */ +}; /* Message */ + +/* Response Message; Notifies the remote driver of the need to clear the + * data path to prevent the IPA from being blocked at the head of the + * processing pipeline + */ +struct ipa_enable_force_clear_datapath_resp_msg_v01 { + /* Mandatory */ + /* Result Code */ + struct ipa_qmi_response_type_v01 resp; + /* Standard response type */ +}; /* Message */ + +/* Request Message; Notifies the remote driver that the forceful clearing + * of the data path can be lifted + */ +struct ipa_disable_force_clear_datapath_req_msg_v01 { + /* Mandatory */ + /* Request ID */ + __u32 request_id; + /* Identifies the request that was sent to the server to + * forcibly clear the data path. This request simply undoes + * the operation done in that request + */ +}; /* Message */ + +/* Response Message; Notifies the remote driver that the forceful clearing + * of the data path can be lifted + */ +struct ipa_disable_force_clear_datapath_resp_msg_v01 { + /* Mandatory */ + /* Result Code */ + struct ipa_qmi_response_type_v01 resp; + /* Standard response type */ +}; /* Message */ + +enum ipa_peripheral_speed_enum_v01 { + IPA_PERIPHERAL_SPEED_ENUM_MIN_ENUM_VAL_V01 = -2147483647, + /* To force a 32 bit signed enum. Do not change or use */ + QMI_IPA_PER_USB_FS_V01 = 1, + /* Full-speed USB connection */ + QMI_IPA_PER_USB_HS_V01 = 2, + /* High-speed USB connection */ + QMI_IPA_PER_USB_SS_V01 = 3, + /* Super-speed USB connection */ + QMI_IPA_PER_WLAN_V01 = 4, + /* WLAN connection */ + IPA_PERIPHERAL_SPEED_ENUM_MAX_ENUM_VAL_V01 = 2147483647 + /* To force a 32 bit signed enum. Do not change or use*/ +}; + +enum ipa_pipe_mode_enum_v01 { + IPA_PIPE_MODE_ENUM_MIN_ENUM_VAL_V01 = -2147483647, + /* To force a 32 bit signed enum. Do not change or use */ + QMI_IPA_PIPE_MODE_HW_V01 = 1, + /* Pipe is connected with a hardware block */ + QMI_IPA_PIPE_MODE_SW_V01 = 2, + /* Pipe is controlled by the software */ + IPA_PIPE_MODE_ENUM_MAX_ENUM_VAL_V01 = 2147483647 + /* To force a 32 bit signed enum. Do not change or use */ +}; + +enum ipa_peripheral_type_enum_v01 { + IPA_PERIPHERAL_TYPE_ENUM_MIN_ENUM_VAL_V01 = -2147483647, + /* To force a 32 bit signed enum. Do not change or use */ + QMI_IPA_PERIPHERAL_USB_V01 = 1, + /* Specifies a USB peripheral */ + QMI_IPA_PERIPHERAL_HSIC_V01 = 2, + /* Specifies an HSIC peripheral */ + QMI_IPA_PERIPHERAL_PCIE_V01 = 3, + /* Specifies a PCIe peripheral */ + IPA_PERIPHERAL_TYPE_ENUM_MAX_ENUM_VAL_V01 = 2147483647 + /* To force a 32 bit signed enum. Do not change or use */ +}; + +struct ipa_config_req_msg_v01 { + /* Optional */ + /* Peripheral Type */ + __u8 peripheral_type_valid; + /* Must be set to true if peripheral_type is being passed */ + enum ipa_peripheral_type_enum_v01 peripheral_type; + /* Informs the remote driver about the perhipheral for + * which this configuration information is relevant. Values: + * - QMI_IPA_PERIPHERAL_USB (1) -- Specifies a USB peripheral + * - QMI_IPA_PERIPHERAL_HSIC(2) -- Specifies an HSIC peripheral + * - QMI_IPA_PERIPHERAL_PCIE(3) -- Specifies a PCIe peripheral + */ + + /* Optional */ + /* HW Deaggregation Support */ + __u8 hw_deaggr_supported_valid; + /* Must be set to true if hw_deaggr_supported is being passed */ + __u8 hw_deaggr_supported; + /* Informs the remote driver whether the local IPA driver + * allows de-aggregation to be performed in the hardware + */ + + /* Optional */ + /* Maximum Aggregation Frame Size */ + __u8 max_aggr_frame_size_valid; + /* Must be set to true if max_aggr_frame_size is being passed */ + __u32 max_aggr_frame_size; + /* Specifies the maximum size of the aggregated frame that + * the remote driver can expect from this execution environment + * - Valid range: 128 bytes to 32768 bytes + */ + + /* Optional */ + /* IPA Ingress Pipe Mode */ + __u8 ipa_ingress_pipe_mode_valid; + /* Must be set to true if ipa_ingress_pipe_mode is being passed */ + + enum ipa_pipe_mode_enum_v01 ipa_ingress_pipe_mode; + /* Indicates to the remote driver if the ingress pipe into the + * IPA is in direct connection with another hardware block or + * if the producer of data to this ingress pipe is a software + * module. Values: + * -QMI_IPA_PIPE_MODE_HW(1) --Pipe is connected with hardware block + * -QMI_IPA_PIPE_MODE_SW(2) --Pipe is controlled by the software + */ + + /* Optional */ + /* Peripheral Speed Info */ + __u8 peripheral_speed_info_valid; + /* Must be set to true if peripheral_speed_info is being passed */ + + enum ipa_peripheral_speed_enum_v01 peripheral_speed_info; + /* Indicates the speed that the peripheral connected to the IPA supports + * Values: + * - QMI_IPA_PER_USB_FS (1) -- Full-speed USB connection + * - QMI_IPA_PER_USB_HS (2) -- High-speed USB connection + * - QMI_IPA_PER_USB_SS (3) -- Super-speed USB connection + * - QMI_IPA_PER_WLAN (4) -- WLAN connection + */ + + /* Optional */ + /* Downlink Accumulation Time limit */ + __u8 dl_accumulation_time_limit_valid; + /* Must be set to true if dl_accumulation_time_limit is being passed */ + __u32 dl_accumulation_time_limit; + /* Informs the remote driver about the time for which data + * is accumulated in the downlink direction before it is pushed into the + * IPA (downlink is with respect to the WWAN air interface) + * - Units: milliseconds + * - Maximum value: 255 + */ + + /* Optional */ + /* Downlink Accumulation Packet limit */ + __u8 dl_accumulation_pkt_limit_valid; + /* Must be set to true if dl_accumulation_pkt_limit is being passed */ + __u32 dl_accumulation_pkt_limit; + /* Informs the remote driver about the number of packets + * that are to be accumulated in the downlink direction before it is + * pushed into the IPA - Maximum value: 1023 + */ + + /* Optional */ + /* Downlink Accumulation Byte Limit */ + __u8 dl_accumulation_byte_limit_valid; + /* Must be set to true if dl_accumulation_byte_limit is being passed */ + __u32 dl_accumulation_byte_limit; + /* Inform the remote driver about the number of bytes + * that are to be accumulated in the downlink direction before it + * is pushed into the IPA - Maximum value: TBD + */ + + /* Optional */ + /* Uplink Accumulation Time Limit */ + __u8 ul_accumulation_time_limit_valid; + /* Must be set to true if ul_accumulation_time_limit is being passed */ + __u32 ul_accumulation_time_limit; + /* Inform thes remote driver about the time for which data + * is to be accumulated in the uplink direction before it is pushed into + * the IPA (downlink is with respect to the WWAN air interface). + * - Units: milliseconds + * - Maximum value: 255 + */ + + /* Optional */ + /* HW Control Flags */ + __u8 hw_control_flags_valid; + /* Must be set to true if hw_control_flags is being passed */ + __u32 hw_control_flags; + /* Informs the remote driver about the hardware control flags: + * - Bit 0: IPA_HW_FLAG_HALT_SYSTEM_ON_NON_TERMINAL_FAILURE -- + * Indicates to the hardware that it must not continue with + * any subsequent operation even if the failure is not terminal + * - Bit 1: IPA_HW_FLAG_NO_REPORT_MHI_CHANNEL_ERORR -- + * Indicates to the hardware that it is not required to report + * channel errors to the host. + * - Bit 2: IPA_HW_FLAG_NO_REPORT_MHI_CHANNEL_WAKE_UP -- + * Indicates to the hardware that it is not required to generate + * wake-up events to the host. + * - Bit 4: IPA_HW_FLAG_WORK_OVER_DDR -- + * Indicates to the hardware that it is accessing addresses in + * the DDR and not over PCIe + * - Bit 5: IPA_HW_FLAG_INTERRUPT_MODE_CTRL_FLAG -- + * Indicates whether the device must + * raise an event to let the host know that it is going into an + * interrupt mode (no longer polling for data/buffer availability) + */ + + /* Optional */ + /* Uplink MSI Event Threshold */ + __u8 ul_msi_event_threshold_valid; + /* Must be set to true if ul_msi_event_threshold is being passed */ + __u32 ul_msi_event_threshold; + /* Informs the remote driver about the threshold that will + * cause an interrupt (MSI) to be fired to the host. This ensures + * that the remote driver does not accumulate an excesive number of + * events before firing an interrupt. + * This threshold is applicable for data moved in the UL direction. + * - Maximum value: 65535 + */ + + /* Optional */ + /* Downlink MSI Event Threshold */ + __u8 dl_msi_event_threshold_valid; + /* Must be set to true if dl_msi_event_threshold is being passed */ + __u32 dl_msi_event_threshold; + /* Informs the remote driver about the threshold that will + * cause an interrupt (MSI) to be fired to the host. This ensures + * that the remote driver does not accumulate an excesive number of + * events before firing an interrupt + * This threshold is applicable for data that is moved in the + * DL direction - Maximum value: 65535 + */ + + /* Optional */ + /* Uplink Fifo Size */ + __u8 ul_fifo_size_valid; + /* Must be set to true if ul_fifo_size is being passed */ + __u32 ul_fifo_size; + /* + * Informs the remote driver about the total Uplink xDCI + * buffer size that holds the complete aggregated frame + * or BAM data fifo size of the peripheral channel/pipe(in Bytes). + * This deprecates the max_aggr_frame_size field. This TLV + * deprecates max_aggr_frame_size TLV from version 1.9 onwards + * and the max_aggr_frame_size TLV will be ignored in the presence + * of this TLV. + */ + + /* Optional */ + /* Downlink Fifo Size */ + __u8 dl_fifo_size_valid; + /* Must be set to true if dl_fifo_size is being passed */ + __u32 dl_fifo_size; + /* + * Informs the remote driver about the total Downlink xDCI buffering + * capacity or BAM data fifo size of the peripheral channel/pipe. + * (In Bytes). dl_fifo_size = n * dl_buf_size. This deprecates the + * max_aggr_frame_size field. If this value is set + * max_aggr_frame_size is ignored. + */ + + /* Optional */ + /* Downlink Buffer Size */ + __u8 dl_buf_size_valid; + /* Must be set to true if dl_buf_size is being passed */ + __u32 dl_buf_size; + /* Informs the remote driver about the single xDCI buffer size. + * This is applicable only in GSI mode(in Bytes).\n + */ +}; /* Message */ + +/* Response Message; Notifies the remote driver of the configuration + * information + */ +struct ipa_config_resp_msg_v01 { + /* Mandatory */ + /* Result Code */ + struct ipa_qmi_response_type_v01 resp; + /**< Standard response type.*/ +}; /* Message */ + +enum ipa_stats_type_enum_v01 { + IPA_STATS_TYPE_ENUM_MIN_ENUM_VAL_V01 = -2147483647, + /* To force a 32 bit signed enum. Do not change or use */ + QMI_IPA_STATS_TYPE_INVALID_V01 = 0, + /* Invalid stats type identifier */ + QMI_IPA_STATS_TYPE_PIPE_V01 = 1, + /* Pipe stats type */ + QMI_IPA_STATS_TYPE_FILTER_RULES_V01 = 2, + /* Filter rule stats type */ + IPA_STATS_TYPE_ENUM_MAX_ENUM_VAL_V01 = 2147483647 + /* To force a 32 bit signed enum. Do not change or use */ +}; + +struct ipa_pipe_stats_info_type_v01 { + __u32 pipe_index; + /* Pipe index for statistics to be retrieved. */ + + __u64 num_ipv4_packets; + /* Accumulated number of IPv4 packets over this pipe. */ + + __u64 num_ipv4_bytes; + /* Accumulated number of IPv4 bytes over this pipe. */ + + __u64 num_ipv6_packets; + /* Accumulated number of IPv6 packets over this pipe. */ + + __u64 num_ipv6_bytes; + /* Accumulated number of IPv6 bytes over this pipe. */ +}; + +struct ipa_stats_type_filter_rule_v01 { + __u32 filter_rule_index; + /* Filter rule index for statistics to be retrieved. */ + + __u64 num_packets; + /* Accumulated number of packets over this filter rule. */ +}; + +/* Request Message; Retrieve the data statistics collected on modem + * IPA driver. + */ +struct ipa_get_data_stats_req_msg_v01 { + /* Mandatory */ + /* Stats Type */ + enum ipa_stats_type_enum_v01 ipa_stats_type; + /* Indicates the type of statistics to be retrieved. */ + + /* Optional */ + /* Reset Statistics */ + __u8 reset_stats_valid; + /* Must be set to true if reset_stats is being passed */ + __u8 reset_stats; + /* Option to reset the specific type of data statistics + * currently collected. + */ +}; /* Message */ + +/* Response Message; Retrieve the data statistics collected + * on modem IPA driver. + */ +struct ipa_get_data_stats_resp_msg_v01 { + /* Mandatory */ + /* Result Code */ + struct ipa_qmi_response_type_v01 resp; + /* Standard response type. */ + + /* Optional */ + /* Stats Type */ + __u8 ipa_stats_type_valid; + /* Must be set to true if ipa_stats_type is passed */ + enum ipa_stats_type_enum_v01 ipa_stats_type; + /* Indicates the type of statistics that are retrieved. */ + + /* Optional */ + /* Uplink Source Pipe Statistics List */ + __u8 ul_src_pipe_stats_list_valid; + /* Must be set to true if ul_src_pipe_stats_list is being passed */ + __u32 ul_src_pipe_stats_list_len; + /* Must be set to # of elements in ul_src_pipe_stats_list */ + struct ipa_pipe_stats_info_type_v01 + ul_src_pipe_stats_list[QMI_IPA_MAX_PIPES_V01]; + /* List of all Uplink pipe statistics that are retrieved. */ + + /* Optional */ + /* Downlink Destination Pipe Statistics List */ + __u8 dl_dst_pipe_stats_list_valid; + /* Must be set to true if dl_dst_pipe_stats_list is being passed */ + __u32 dl_dst_pipe_stats_list_len; + /* Must be set to # of elements in dl_dst_pipe_stats_list */ + struct ipa_pipe_stats_info_type_v01 + dl_dst_pipe_stats_list[QMI_IPA_MAX_PIPES_V01]; + /* List of all Downlink pipe statistics that are retrieved. */ + + /* Optional */ + /* Downlink Filter Rule Stats List */ + __u8 dl_filter_rule_stats_list_valid; + /* Must be set to true if dl_filter_rule_stats_list is being passed */ + __u32 dl_filter_rule_stats_list_len; + /* Must be set to # of elements in dl_filter_rule_stats_list */ + struct ipa_stats_type_filter_rule_v01 + dl_filter_rule_stats_list[QMI_IPA_MAX_FILTERS_V01]; + /* List of all Downlink filter rule statistics retrieved. */ +}; /* Message */ + +struct ipa_apn_data_stats_info_type_v01 { + __u32 mux_id; + /* Indicates the MUX ID associated with the APN for which the data + * usage statistics is queried + */ + + __u64 num_ul_packets; + /* Accumulated number of uplink packets corresponding to + * this Mux ID + */ + + __u64 num_ul_bytes; + /* Accumulated number of uplink bytes corresponding to + * this Mux ID + */ + + __u64 num_dl_packets; + /* Accumulated number of downlink packets corresponding + * to this Mux ID + */ + + __u64 num_dl_bytes; + /* Accumulated number of downlink bytes corresponding to + * this Mux ID + */ +}; /* Type */ + +/* Request Message; Retrieve the APN data statistics collected from modem */ +struct ipa_get_apn_data_stats_req_msg_v01 { + /* Optional */ + /* Mux ID List */ + __u8 mux_id_list_valid; + /* Must be set to true if mux_id_list is being passed */ + __u32 mux_id_list_len; + /* Must be set to # of elements in mux_id_list */ + __u32 mux_id_list[QMI_IPA_MAX_APN_V01]; + /* The list of MUX IDs associated with APNs for which the data usage + * statistics is being retrieved + */ +}; /* Message */ + +/* Response Message; Retrieve the APN data statistics collected from modem */ +struct ipa_get_apn_data_stats_resp_msg_v01 { + /* Mandatory */ + /* Result Code */ + struct ipa_qmi_response_type_v01 resp; + /* Standard response type.*/ + + /* Optional */ + /* APN Data Statistics List */ + __u8 apn_data_stats_list_valid; + /* Must be set to true if apn_data_stats_list is being passed */ + __u32 apn_data_stats_list_len; + /* Must be set to # of elements in apn_data_stats_list */ + struct ipa_apn_data_stats_info_type_v01 + apn_data_stats_list[QMI_IPA_MAX_APN_V01]; + /* List of APN data retrieved as per request on mux_id. + * For now, only one APN monitoring is supported on modem driver. + * Making this as list for expandability to support more APNs in future. + */ +}; /* Message */ + +struct ipa_data_usage_quota_info_type_v01 { + __u32 mux_id; + /* Indicates the MUX ID associated with the APN for which the data usage + * quota needs to be set + */ + + __u64 num_Mbytes; + /* Number of Mega-bytes of quota value to be set on this APN associated + * with this Mux ID. + */ +}; /* Type */ + +#define IPA_DATA_WARNING_QUOTA + +/* Request Message; Master driver sets a data usage quota value on + * modem driver + */ +struct ipa_set_data_usage_quota_req_msg_v01 { + /* Optional */ + /* APN Quota List */ + __u8 apn_quota_list_valid; + /* Must be set to true if apn_quota_list is being passed */ + __u32 apn_quota_list_len; + /* Must be set to # of elements in apn_quota_list */ + struct ipa_data_usage_quota_info_type_v01 + apn_quota_list[QMI_IPA_MAX_APN_V01]; + /* The list of APNs on which a data usage quota to be set on modem + * driver. For now, only one APN monitoring is supported on modem + * driver. Making this as list for expandability to support more + * APNs in future. + */ + + /* Optional */ + /* APN Warning List */ + __u8 apn_warning_list_valid; + /* Must be set to true if apn_warning_list is being passed */ + __u32 apn_warning_list_len; + /* Must be set to # of elements in apn_warning_list */ + struct ipa_data_usage_quota_info_type_v01 + apn_warning_list[QMI_IPA_MAX_APN_V01]; + /* The list of APNs on which a data usage warning to be set on modem + * driver. For now, only one APN monitoring is supported on modem + * driver. Making this as list for expandability to support more + * APNs in future. + */ + +}; /* Message */ + +/* Response Message; Master driver sets a data usage on modem driver. */ +struct ipa_set_data_usage_quota_resp_msg_v01 { + /* Mandatory */ + /* Result Code */ + struct ipa_qmi_response_type_v01 resp; + /* Standard response type.*/ +}; /* Message */ + +/* Indication Message; Modem driver sends this indication to master + * driver when the data usage quota is reached + */ +struct ipa_data_usage_quota_reached_ind_msg_v01 { + /* Mandatory */ + /* APN Quota List */ + struct ipa_data_usage_quota_info_type_v01 apn; + /* This message indicates which APN has the previously set quota + * or warning reached. For now, only one APN monitoring is supported + * on modem driver. + */ + /* Optional */ + /* Warning Limit reached indication */ + /* Must be set to true if is_warning_limit is being passed */ + __u8 is_warning_limit_valid; + __u8 is_warning_limit; + /* If set to TRUE, Warning Limit is reached. + * If set to FALSE, Quota Limit is reached. + */ +}; /* Message */ + +/* Request Message; Master driver request modem driver to terminate + * the current data usage quota monitoring session. + */ +struct ipa_stop_data_usage_quota_req_msg_v01 { + /* Optional */ + /* Stop monitoring Quota Limit */ + /* Must be set to true if is_quota_limit is being passed */ + __u8 is_quota_limit_valid; + __u8 is_quota_limit; + /* If set to TRUE, Quota Limit will not be monitored */ + + /* Optional */ + /* Stop monitoring Warning Limit */ + /* Must be set to true if is_warning_limit is being passed */ + __u8 is_warning_limit_valid; + __u8 is_warning_limit; + /* If set to TRUE, Warning Limit will not be monitored */ +}; /* Message */ + +/* Response Message; Master driver request modem driver to terminate + * the current quota or warning limit monitoring session. + */ +struct ipa_stop_data_usage_quota_resp_msg_v01 { + /* Mandatory */ + /* Result Code */ + struct ipa_qmi_response_type_v01 resp; + /**< Standard response type.*/ +}; /* Message */ + +/* Request Message; Request from Modem IPA driver to set DPL peripheral pipe */ +struct ipa_install_fltr_rule_req_ex_msg_v01 { + + /* Optional */ + /* Extended Filter Specification */ + __u8 filter_spec_ex_list_valid; + __u32 filter_spec_ex_list_len; + struct ipa_filter_spec_ex_type_v01 + filter_spec_ex_list[QMI_IPA_MAX_FILTERS_EX_V01]; + /* List of filter specifications of filters that must be installed in + * the IPAv3.x hardware. + * The driver installing these rules must do so in the same order as + * specified in this list. + */ + + /* Optional */ + /* Pipe Index to Install Rule */ + __u8 source_pipe_index_valid; + __u32 source_pipe_index; + /* Pipe index to install the filter rule. + * The requester may not always know the pipe indices. If not specified, + * the receiver must install this rule on all pipes that it controls, + * through which data may be fed into the IPA. + */ + + /* Optional */ + /* Total Number of IPv4 Filters in the Filter Spec List */ + __u8 num_ipv4_filters_valid; + __u32 num_ipv4_filters; + /* Number of IPv4 rules included in the filter specification list. */ + + /* Optional */ + /* Total Number of IPv6 Filters in the Filter Spec List */ + __u8 num_ipv6_filters_valid; + __u32 num_ipv6_filters; + /* Number of IPv6 rules included in the filter specification list. */ + + /* Optional */ + /* List of XLAT Filter Indices in the Filter Spec List */ + __u8 xlat_filter_indices_list_valid; + __u32 xlat_filter_indices_list_len; + __u32 xlat_filter_indices_list[QMI_IPA_MAX_FILTERS_EX_V01]; + /* List of XLAT filter indices. + * Filter rules at specified indices must be modified by the + * receiver if the PDN is XLAT before installing them on the associated + * IPA consumer pipe. + */ + + /* Optional */ + /* Extended Type 2 Filter Specification */ + __u8 filter_spec_ex2_list_valid; + /* Must be set to true if filter_spec_ex2_list is being passed */ + __u32 filter_spec_ex2_list_len; + /* Must be set to # of elements in filter_spec_ex2_list */ + struct ipa_filter_spec_ex2_type_v01 + filter_spec_ex2_list[QMI_IPA_MAX_FILTERS_V01]; + /* Optional */ + /* List of modem UL Filters in the Spec List which need be to + * replicated with AP UL firewall filters + */ + __u8 ul_firewall_indices_list_valid; + /* Must be set to # of elements in ul_firewall_indices_list */ + __u32 ul_firewall_indices_list_len; + __u32 ul_firewall_indices_list[QMI_IPA_MAX_FILTERS_V01]; + /* List of UL firewall filter indices. + * Filter rules at specified indices must be replicated across + * the firewall filters by the receiver and installed on the + * associated IPA consumer pipe. + */ +}; /* Message */ + +/* Response Message; Requests installation of filtering rules in the hardware + * block on the remote side. + */ +struct ipa_install_fltr_rule_resp_ex_msg_v01 { + /* Mandatory */ + /* Result Code */ + struct ipa_qmi_response_type_v01 resp; + /* Standard response type. + * Standard response type. Contains the following data members: + * - qmi_result_type -- QMI_RESULT_SUCCESS or QMI_RESULT_FAILURE + * - qmi_error_type -- Error code. Possible error code values are + * described in the error codes + * section of each message + * definition. + */ + + /* Optional */ + /* Rule ID List */ + __u8 rule_id_valid; + __u32 rule_id_len; + __u32 rule_id[QMI_IPA_MAX_FILTERS_EX_V01]; + /* List of rule IDs returned to the control point. + * Any further reference to the rule is done using the filter rule ID + * specified in this list. + */ +}; /* Message */ + +/* + * Request Message; Requests the modem IPA driver to enable or + * disable collection of per client statistics. + */ +struct ipa_enable_per_client_stats_req_msg_v01 { + + /* Mandatory */ + /* Collect statistics per client; */ + __u8 enable_per_client_stats; + /* + * Indicates whether to start or stop collecting + * per client statistics. + */ +}; /* Message */ + +/* + * Response Message; Requests the modem IPA driver to enable or disable + * collection of per client statistics. + */ +struct ipa_enable_per_client_stats_resp_msg_v01 { + + /* Mandatory */ + /* Result Code */ + struct ipa_qmi_response_type_v01 resp; + /* Standard response type. */ +}; /* Message */ + +struct ipa_per_client_stats_info_type_v01 { + + __u32 client_id; + /* + * Id of the client on APPS processor side for which Modem processor + * needs to send uplink/downlink statistics. + */ + + __u32 src_pipe_id; + /* + * IPA consumer pipe on which client on APPS side sent uplink + * data to modem. + */ + + __u64 num_ul_ipv4_bytes; + /* + * Accumulated number of uplink IPv4 bytes for a client. + */ + + __u64 num_ul_ipv6_bytes; + /* + * Accumulated number of uplink IPv6 bytes for a client. + */ + + __u64 num_dl_ipv4_bytes; + /* + * Accumulated number of downlink IPv4 bytes for a client. + */ + + __u64 num_dl_ipv6_bytes; + /* + * Accumulated number of downlink IPv6 byes for a client. + */ + + + __u32 num_ul_ipv4_pkts; + /* + * Accumulated number of uplink IPv4 packets for a client. + */ + + __u32 num_ul_ipv6_pkts; + /* + * Accumulated number of uplink IPv6 packets for a client. + */ + + __u32 num_dl_ipv4_pkts; + /* + * Accumulated number of downlink IPv4 packets for a client. + */ + + __u32 num_dl_ipv6_pkts; + /* + * Accumulated number of downlink IPv6 packets for a client. + */ +}; /* Type */ + +/* + * Request Message; Requests the modem IPA driver to provide statistics + * for a givenclient. + */ +struct ipa_get_stats_per_client_req_msg_v01 { + + /* Mandatory */ + /* Client id */ + __u32 client_id; + /* + * Id of the client on APPS processor side for which Modem processor + * needs to send uplink/downlink statistics. if client id is specified + * as 0xffffffff, then Q6 will send the stats for all the clients of + * the specified source pipe. + */ + + /* Mandatory */ + /* Source pipe id */ + __u32 src_pipe_id; + /* + * IPA consumer pipe on which client on APPS side sent uplink + * data to modem. In future, this implementation can be extended + * to provide 0xffffffff as the source pipe id, where Q6 will send + * the stats of all the clients across all different tethered-pipes. + */ + + /* Optional */ + /* Reset client statistics. */ + __u8 reset_stats_valid; + /* Must be set to true if reset_stats is being passed. */ + __u8 reset_stats; + /* + * Option to reset the statistics currently collected by modem for this + * particular client. + */ +}; /* Message */ + +/* + * Response Message; Requests the modem IPA driver to provide statistics + * for a given client. + */ +struct ipa_get_stats_per_client_resp_msg_v01 { + + /* Mandatory */ + /* Result Code */ + struct ipa_qmi_response_type_v01 resp; + /* Standard response type. */ + + /* Optional */ + /* Per clients Statistics List */ + __u8 per_client_stats_list_valid; + /* Must be set to true if per_client_stats_list is being passed. */ + __u32 per_client_stats_list_len; + /* Must be set to # of elements in per_client_stats_list. */ + struct ipa_per_client_stats_info_type_v01 + per_client_stats_list[QMI_IPA_MAX_PER_CLIENTS_V01]; + /* + * List of all per client statistics that are retrieved. + */ +}; /* Message */ + +struct ipa_ul_firewall_rule_type_v01 { + + enum ipa_ip_type_enum_v01 ip_type; + /* + * IP type for which this rule is applicable. + * The driver must identify the filter table (v6 or v4), and this + * field is essential for that. Values: + * - QMI_IPA_IP_TYPE_INVALID (0) -- Invalid IP type identifier + * - QMI_IPA_IP_TYPE_V4 (1) -- IPv4 type + * - QMI_IPA_IP_TYPE_V6 (2) -- IPv6 type + */ + + struct ipa_filter_rule_type_v01 filter_rule; + /* + * Rules in the filter specification. These rules are the + * ones that are matched against fields in the packet. + * Currently we only send IPv6 whitelist rules to Q6. + */ +}; /* Type */ + +/* + * Request Message; Requestes remote IPA driver to install uplink + * firewall rules. + */ +struct ipa_configure_ul_firewall_rules_req_msg_v01 { + + /* Optional */ + /* Uplink Firewall Specification */ + __u32 firewall_rules_list_len; + /* Must be set to # of elements in firewall_rules_list. */ + struct ipa_ul_firewall_rule_type_v01 + firewall_rules_list[QMI_IPA_MAX_UL_FIREWALL_RULES_V01]; + /* + * List of uplink firewall specifications of filters that must be + * installed. + */ + + __u32 mux_id; + /* + * QMAP Mux ID. As a part of the QMAP protocol, + * several data calls may be multiplexed over the same physical + * transport channel. This identifier is used to identify one + * such data call. The maximum value for this identifier is 255. + */ + + /* Optional */ + __u8 disable_valid; + /* Must be set to true if enable is being passed. */ + __u8 disable; + /* + * Indicates whether uplink firewall needs to be enabled or disabled. + */ + + /* Optional */ + __u8 are_blacklist_filters_valid; + /* Must be set to true if are_blacklist_filters is being passed. */ + __u8 are_blacklist_filters; + /* + * Indicates whether the filters received as part of this message are + * blacklist filters. i.e. drop uplink packets matching these rules. + */ +}; /* Message */ + +/* + * Response Message; Requestes remote IPA driver to install + * uplink firewall rules. + */ +struct ipa_configure_ul_firewall_rules_resp_msg_v01 { + + /* Mandatory */ + /* Result Code */ + struct ipa_qmi_response_type_v01 resp; + /* + * Standard response type. + * Standard response type. Contains the following data members: + * qmi_result_type -- QMI_RESULT_SUCCESS or QMI_RESULT_FAILURE + * qmi_error_type -- Error code. Possible error code values are + * described in the error codes section of each message definition. + */ +}; /* Message */ + +enum ipa_ul_firewall_status_enum_v01 { + IPA_UL_FIREWALL_STATUS_ENUM_MIN_ENUM_VAL_V01 = -2147483647, + /* To force a 32 bit signed enum. Do not change or use*/ + QMI_IPA_UL_FIREWALL_STATUS_SUCCESS_V01 = 0, + /* Indicates that the uplink firewall rules + * are configured successfully. + */ + QMI_IPA_UL_FIREWALL_STATUS_FAILURE_V01 = 1, + /* Indicates that the uplink firewall rules + * are not configured successfully. + */ + IPA_UL_FIREWALL_STATUS_ENUM_MAX_ENUM_VAL_V01 = 2147483647 + /* To force a 32 bit signed enum. Do not change or use*/ +}; + +struct ipa_ul_firewall_config_result_type_v01 { + + enum ipa_ul_firewall_status_enum_v01 is_success; + /* + * Indicates whether the uplink firewall rules are configured + * successfully. + */ + + __u32 mux_id; + /* + * QMAP Mux ID. As a part of the QMAP protocol, + * several data calls may be multiplexed over the same physical + * transport channel. This identifier is used to identify one + * such data call. The maximum value for this identifier is 255. + */ +}; + +/* + * Indication Message; Requestes remote IPA driver to install + * uplink firewall rules. + */ +struct ipa_configure_ul_firewall_rules_ind_msg_v01 { + struct ipa_ul_firewall_config_result_type_v01 result; +}; /* Message */ + + +struct ipa_mhi_ch_init_info_type_v01 { + __u8 ch_id; + /* Remote MHI channel ID */ + + __u8 er_id; + /* Remote MHI Event ring ID */ + + __u32 ch_doorbell_addr; + /* TR Channel Doorbell addr */ + + __u32 er_doorbell_addr; + /* Event ring Doorbell addr */ + + __u32 direction_type; + /* Direction type */ +}; + +struct ipa_mhi_smmu_info_type_v01 { + __u64 iova_ctl_base_addr; + /* IOVA mapped Control Region base address */ + + __u64 iova_ctl_size; + /* IOVA Control region size */ + + __u64 iova_data_base_addr; + /* IOVA mapped Data Region base address */ + + __u64 iova_data_size; + /* IOVA Data Region size */ +}; + +struct ipa_mhi_ready_indication_msg_v01 { + /* Mandatory */ + __u32 ch_info_arr_len; + /* Must be set to # of elements in ch_info_arr. */ + struct ipa_mhi_ch_init_info_type_v01 + ch_info_arr[QMI_IPA_REMOTE_MHI_CHANNELS_NUM_MAX_V01]; + /* Channel Information array */ + + /* Mandatory */ + __u8 smmu_info_valid; + /* Must be set to true if smmu_info is being passed. */ + struct ipa_mhi_smmu_info_type_v01 smmu_info; + /* SMMU enabled indication */ +}; +#define IPA_MHI_READY_INDICATION_MSG_V01_MAX_MSG_LEN 123 + +struct ipa_mhi_mem_addr_info_type_v01 { + __u64 pa; + /* Memory region start physical addr */ + + __u64 iova; + /* Memory region start iova mapped addr */ + + __u64 size; + /* Memory region size */ +}; + +enum ipa_mhi_brst_mode_enum_v01 { + IPA_MHI_BRST_MODE_ENUM_MIN_VAL_V01 = IPA_INT_MIN, + + QMI_IPA_BURST_MODE_DEFAULT_V01 = 0, + /* + * Default - burst mode enabled for hardware channels, + * disabled for software channels + */ + + QMI_IPA_BURST_MODE_ENABLED_V01 = 1, + /* Burst mode is enabled for this channel */ + + QMI_IPA_BURST_MODE_DISABLED_V01 = 2, + /* Burst mode is disabled for this channel */ + + IPA_MHI_BRST_MODE_ENUM_MAX_VAL_V01 = IPA_INT_MAX, +}; + +struct ipa_mhi_tr_info_type_v01 { + __u8 ch_id; + /* TR Channel ID */ + + __u16 poll_cfg; + /* + * Poll Configuration - Default or timer to poll the + * MHI context in milliseconds + */ + + enum ipa_mhi_brst_mode_enum_v01 brst_mode_type; + /* Burst mode configuration */ + + __u64 ring_iova; + /* IOVA mapped ring base address */ + + __u64 ring_len; + /* Ring Length in bytes */ + + __u64 rp; + /* IOVA mapped Read pointer address */ + + __u64 wp; + /* IOVA mapped write pointer address */ +}; + +struct ipa_mhi_er_info_type_v01 { + __u8 er_id; + /* Event ring ID */ + + __u32 intmod_cycles; + /* Interrupt moderation cycles */ + + __u32 intmod_count; + /* Interrupt moderation count */ + + __u32 msi_addr; + /* IOVA mapped MSI address for this ER */ + + __u64 ring_iova; + /* IOVA mapped ring base address */ + + __u64 ring_len; + /* Ring length in bytes */ + + __u64 rp; + /* IOVA mapped Read pointer address */ + + __u64 wp; + /* IOVA mapped Write pointer address */ +}; + +struct ipa_mhi_alloc_channel_req_msg_v01 { + /* Mandatory */ + __u32 tr_info_arr_len; + /* Must be set to # of elements in tr_info_arr. */ + struct ipa_mhi_tr_info_type_v01 + tr_info_arr[QMI_IPA_REMOTE_MHI_CHANNELS_NUM_MAX_V01]; + /* Array of TR context information for Remote MHI channels */ + + /* Mandatory */ + __u32 er_info_arr_len; + /* Must be set to # of elements in er_info_arr. */ + struct ipa_mhi_er_info_type_v01 + er_info_arr[QMI_IPA_REMOTE_MHI_CHANNELS_NUM_MAX_V01]; + /* Array of ER context information for Remote MHI channels */ + + /* Mandatory */ + __u32 ctrl_addr_map_info_len; + /* Must be set to # of elements in ctrl_addr_map_info. */ + + struct ipa_mhi_mem_addr_info_type_v01 + ctrl_addr_map_info[QMI_IPA_REMOTE_MHI_MEMORY_MAPPING_NUM_MAX_V01]; + /* + * List of PA-IOVA address mappings for control regions + * used by Modem + */ + + /* Mandatory */ + __u32 data_addr_map_info_len; + /* Must be set to # of elements in data_addr_map_info. */ + struct ipa_mhi_mem_addr_info_type_v01 + data_addr_map_info[QMI_IPA_REMOTE_MHI_MEMORY_MAPPING_NUM_MAX_V01]; + /* List of PA-IOVA address mappings for data regions used by Modem */ +}; +#define IPA_MHI_ALLOC_CHANNEL_REQ_MSG_V01_MAX_MSG_LEN 808 + +struct ipa_mhi_ch_alloc_resp_type_v01 { + __u8 ch_id; + /* Remote MHI channel ID */ + + __u8 is_success; + /* Channel Allocation Status */ +}; + +struct ipa_mhi_alloc_channel_resp_msg_v01 { + /* Mandatory */ + struct ipa_qmi_response_type_v01 resp; + /* Standard response type. Contains the following data members: + * - qmi_result_type -- QMI_RESULT_SUCCESS or QMI_RESULT_FAILURE + * - qmi_error_type -- Error code. Possible error code values + * are described in the error codes section + * of each message definition. + */ + + /* Optional */ + __u8 alloc_resp_arr_valid; + /* Must be set to true if alloc_resp_arr is being passed. */ + __u32 alloc_resp_arr_len; + /* Must be set to # of elements in alloc_resp_arr. */ + struct ipa_mhi_ch_alloc_resp_type_v01 + alloc_resp_arr[QMI_IPA_REMOTE_MHI_CHANNELS_NUM_MAX_V01]; + /* MHI channel allocation response array */ +}; +#define IPA_MHI_ALLOC_CHANNEL_RESP_MSG_V01_MAX_MSG_LEN 23 + +enum ipa_clock_rate_enum_v01 { + IPA_CLOCK_RATE_ENUM_MIN_ENUM_VAL_V01 = IPA_INT_MIN, + + QMI_IPA_CLOCK_RATE_INVALID_V01 = 0, + + QMI_IPA_CLOCK_RATE_LOW_SVS_V01 = 1, + + QMI_IPA_CLOCK_RATE_SVS_V01 = 2, + + QMI_IPA_CLOCK_RATE_NOMINAL_V01 = 3, + + QMI_IPA_CLOCK_RATE_TURBO_V01 = 4, + + IPA_CLOCK_RATE_ENUM_MAX_ENUM_VAL_V01 = IPA_INT_MAX, +}; + +struct ipa_mhi_clk_vote_req_msg_v01 { + /* Mandatory */ + __u8 mhi_vote; + /* + * MHI vote request + * TRUE - ON + * FALSE - OFF + */ + /* Optional */ + /* Throughput Value */ + __u8 tput_value_valid; + __u32 tput_value; + + /* Optional */ + /* IPA Clock Rate */ + __u8 clk_rate_valid; + enum ipa_clock_rate_enum_v01 clk_rate; +}; +#define IPA_MHI_CLK_VOTE_REQ_MSG_V01_MAX_MSG_LEN 18 + +struct ipa_mhi_clk_vote_resp_msg_v01 { + /* Mandatory */ + struct ipa_qmi_response_type_v01 resp; + /* Standard response type. Contains the following data members: + * - qmi_result_type -- QMI_RESULT_SUCCESS or QMI_RESULT_FAILURE + * - qmi_error_type -- Error code. Possible error code values + * are described in the error codes section + * of each message definition. + */ +}; +#define IPA_MHI_CLK_VOTE_RESP_MSG_V01_MAX_MSG_LEN 7 + +struct ipa_mhi_cleanup_req_msg_v01 { + /* Optional */ + __u8 cleanup_valid; + /* Must be set to true if cleanup is being passed. */ + __u8 cleanup; + /* + * a Flag to indicate the type of action + * 1 - Cleanup Request + */ +}; +#define IPA_MHI_CLEANUP_REQ_MSG_V01_MAX_MSG_LEN 4 + +struct ipa_mhi_cleanup_resp_msg_v01 { + /* Mandatory */ + struct ipa_qmi_response_type_v01 resp; + /* Standard response type. Contains the following data members: + * - qmi_result_type -- QMI_RESULT_SUCCESS or QMI_RESULT_FAILURE + * - qmi_error_type -- Error code. Possible error code values + * are described in the error codes section + * of each message definition. + */ +}; +#define IPA_MHI_CLEANUP_RESP_MSG_V01_MAX_MSG_LEN 7 + +enum ipa_ep_desc_type_enum_v01 { + /* To force a 32 bit signed enum. Do not change or use*/ + IPA_EP_DESC_TYPE_ENUM_MIN_VAL_V01 = IPA_INT_MIN, + DATA_EP_DESC_TYPE_RESERVED_V01 = 0x00, + DATA_EP_DESC_TYPE_EMB_CONS_V01 = 0x01, + DATA_EP_DESC_TYPE_EMB_PROD_V01 = 0x02, + DATA_EP_DESC_TYPE_RSC_PROD_V01 = 0x03, + DATA_EP_DESC_TYPE_QDSS_PROD_V01 = 0x04, + DATA_EP_DESC_TYPE_DPL_PROD_V01 = 0x05, + DATA_EP_DESC_TYPE_TETH_CONS_V01 = 0x06, + DATA_EP_DESC_TYPE_TETH_PROD_V01 = 0x07, + DATA_EP_DESC_TYPE_TETH_RMNET_CONS_V01 = 0x08, + DATA_EP_DESC_TYPE_TETH_RMNET_PROD_V01 = 0x09, + DATA_EP_DESC_TYPE_EMB_FLOW_CTL_CONS_V01 = 0x0A, + DATA_EP_DESC_TYPE_EMB_FLOW_CTL_PROD_V01 = 0x0B, + IPA_EP_DESC_TYPE_ENUM_MAX_VAL_V01 = IPA_INT_MAX, +}; + +enum ipa_ic_type_enum_v01 { + /* To force a 32 bit signed enum. Do not change or use*/ + IPA_IC_TYPE_ENUM_MIN_VAL_V01 = IPA_INT_MIN, + DATA_IC_TYPE_RESERVED_V01 = 0x00, + DATA_IC_TYPE_MHI_V01 = 0x01, + DATA_IC_TYPE_MHI_PRIME_V01 = 0x02, + DATA_IC_TYPE_USB_V01 = 0x03, + DATA_IC_TYPE_AP_V01 = 0x04, + DATA_IC_TYPE_Q6_V01 = 0x05, + DATA_IC_TYPE_UC_V01 = 0x06, + IPA_IC_TYPE_ENUM_MAX_VAL_V01 = IPA_INT_MAX, +}; + +enum ipa_ep_status_type_v01 { + /* To force a 32 bit signed enum. Do not change or use*/ + IPA_EP_STATUS_TYPE_MIN_VAL_V01 = IPA_INT_MIN, + DATA_EP_STATUS_RESERVED_V01 = 0x00, + DATA_EP_STATUS_STATIC_V01 = 0x01, + DATA_EP_STATUS_CONNECTED_V01 = 0x02, + DATA_EP_STATUS_DISCONNECTED_V01 = 0x03, + IPA_EP_STATUS_TYPE_MAX_VAL_V01 = IPA_INT_MAX, +}; + +struct ipa_ep_id_type_v01 { + /* Interconnect type. See ipa_ic_desc_type_enum type */ + enum ipa_ic_type_enum_v01 ic_type; + /* Peripheral end point type */ + enum ipa_ep_desc_type_enum_v01 ep_type; + /* Peripheral interface number */ + __u32 ep_id; + /* Status of endpoint */ + enum ipa_ep_status_type_v01 ep_status; +}; + +struct ipa_endp_desc_indication_msg_v01 { + /* Optional */ + __u8 ep_info_valid; + /* Must be set to true if type_arr is being passed */ + __u32 ep_info_len; + /* Must be set to # of elements in type_arr */ + struct ipa_ep_id_type_v01 ep_info[QMI_IPA_ENDP_DESC_NUM_MAX_V01]; + /* Optional */ + __u8 num_eps_valid; + /* Must be set to true if num_of_eps is being passed */ + /* Must be set to # of elements of num_of_eps */ + __u32 num_eps; +}; /* Message */ +#define IPA_ENDP_DESC_INDICATION_MSG_V01_MAX_MSG_LEN 507 + +enum ipa_aggr_enum_type_v01 { + IPA_AGGR_ENUM_TYPE_MIN_VAL_V01 = IPA_INT_MIN, + DATA_AGGR_TYPE_RESERVED_V01 = 0x00, + DATA_AGGR_TYPE_QMAP_V01 = 0x01, + DATA_AGGR_TYPE_QMAPv5_V01 = 0x02, + DATA_AGGR_TYPE_INHERITED_V01 = 0x03, + IPA_AGGR_ENUM_TYPE_MAX_VAL_V01 = IPA_INT_MAX, +}; + +struct ipa_mhi_prime_aggr_info_type_v01 { + enum ipa_ic_type_enum_v01 ic_type; + /* Peripheral end point type */ + enum ipa_ep_desc_type_enum_v01 ep_type; + /* Bytes count in KB */ + __u32 bytes_count; + /* packet count */ + __u32 pkt_count; + /* aggr_type */ + enum ipa_aggr_enum_type_v01 aggr_type; +}; /* Message */ +#define IPA_MHI_PRIME_AGGR_INFO_REQ_MSG_V01_MAX_MSG_LEN 631 + +struct ipa_mhi_prime_aggr_info_req_msg_v01 { + /* optional */ + __u8 aggr_info_valid; + /* Aggregration info for MHI prime */ + /* Must be set to true if aggr_info is being passed*/ + __u32 aggr_info_len; + /* Must be set to # of elements in aggr_info */ + struct ipa_mhi_prime_aggr_info_type_v01 + aggr_info[QMI_IPA_ENDP_DESC_NUM_MAX_V01]; + /* optional */ + /* Must be set to true if num_eps_valid is being passed*/ + __u8 num_eps_valid; + /* Must be set to # of num_eps */ + __u32 num_eps; +}; /* Message */ +#define IPA_MHI_PRIME_AGGR_INFO_RESP_MSG_V01_MAX_MSG_LEN 7 + +struct ipa_mhi_prime_aggr_info_resp_msg_v01 { + /* Result Code */ + struct ipa_qmi_response_type_v01 resp; +}; /* Message */ + +struct ipa_add_offload_connection_req_msg_v01 { + /* optional */ + /* Must be set to true if num_ipv4_filters is being passed*/ + __u8 num_ipv4_filters_valid; + /* Must be set to # of ipv4_filters*/ + __u32 num_ipv4_filters; + /* optional */ + /* Must be set to true if num_ipv6_filters is being passed*/ + __u8 num_ipv6_filters_valid; + /* Must be set to # of ipv6_filters*/ + __u32 num_ipv6_filters; + /* optional */ + __u8 xlat_filter_indices_list_valid; + /* Must be set to true if xlat_filter_indices_list is being passed*/ + __u32 xlat_filter_indices_list_len; + /* Must be set to # of xlat_filter_indices_list*/ + __u32 xlat_filter_indices_list[QMI_IPA_MAX_FILTERS_V01]; + /* optional */ + /* Must be set to true if filter_spec_ex_list is being passed*/ + __u8 filter_spec_ex2_list_valid; + /* Must be set to # of filter_spec_ex_list*/ + __u32 filter_spec_ex2_list_len; + struct ipa_filter_spec_ex2_type_v01 + filter_spec_ex2_list[QMI_IPA_MAX_FILTERS_V01]; + /* Optional */ + /* Mux ID for embedded call */ + __u8 embedded_call_mux_id_valid; + /* Must be set to true if embedded_call_mux_id is being passed */ + __u32 embedded_call_mux_id; + /* Mux ID for the new embedded call */ + /* Optional */ + /* Default MHI path */ + __u8 default_mhi_path_valid; + /* Must be set to true if default_mhi_path is being passed */ + __u8 default_mhi_path; + /* Default MHI path */ +}; /* Message */ +#define IPA_ADD_OFFLOAD_CONNECTION_REQ_MSG_V01_MAX_MSG_LEN 11361 + +struct ipa_add_offload_connection_resp_msg_v01 { + /* Result Code */ + struct ipa_qmi_response_type_v01 resp; + /* optional */ + /* Must be set to true if filter_handle_list is being passed*/ + __u8 filter_handle_list_valid; + /* Must be set to # of filter_handle_list*/ + __u32 filter_handle_list_len; + struct ipa_filter_rule_identifier_to_handle_map_v01 + filter_handle_list[QMI_IPA_MAX_FILTERS_V01]; +}; /* Message */ +#define IPA_ADD_OFFLOAD_CONNECTION_RESP_MSG_V01_MAX_MSG_LEN 523 + +struct ipa_remove_offload_connection_req_msg_v01 { + /* optional */ + /* Must be set to true if filter_handle_list is being passed*/ + __u8 filter_handle_list_valid; + /* Must be set to # of filter_handle_list*/ + __u32 filter_handle_list_len; + struct ipa_filter_rule_identifier_to_handle_map_v01 + filter_handle_list[QMI_IPA_MAX_FILTERS_V01]; + /* Optional */ + /* Clean All rules */ + __u8 clean_all_rules_valid; + /* Must be set to true if clean_all_rules is being passed */ + __u8 clean_all_rules; + /* Clean All rules */ +}; /* Message */ +#define IPA_REMOVE_OFFLOAD_CONNECTION_REQ_MSG_V01_MAX_MSG_LEN 520 + +struct ipa_remove_offload_connection_resp_msg_v01 { + /* optional */ + /* Must be set to true if filter_handle_list is being passed*/ + __u8 resp_valid; + /* Result Code */ + struct ipa_qmi_response_type_v01 resp; +}; /* Message */ +#define IPA_REMOVE_OFFLOAD_CONNECTION_RESP_MSG_V01_MAX_MSG_LEN 7 + +struct ipa_bw_change_ind_msg_v01 { + /* optional */ + /* Must be set to true if peak_bw_ul is being passed*/ + __u8 peak_bw_ul_valid; + /* Must be set to true if peak_bw_dl is being passed*/ + __u8 peak_bw_dl_valid; + /* Kbps */ + __u32 peak_bw_ul; + /* Kbps */ + __u32 peak_bw_dl; +}; /* Message */ +#define IPA_BW_CHANGE_IND_MSG_V01_MAX_MSG_LEN 14 + +enum ipa_move_nat_type_enum_v01 { + QMI_IPA_MOVE_NAT_TO_DDR_V01 = 0, + QMI_IPA_MOVE_NAT_TO_SRAM_V01 = 1, +}; + +/* + * Request Message; Requestes remote IPA driver to move IPA NAT table + * according to requested direction TO_DDR\TO_SRAM. + */ +struct ipa_move_nat_req_msg_v01 { + enum ipa_move_nat_type_enum_v01 nat_move_direction; +}; +#define IPA_MOVE_NAT_REQ_MSG_V01_MAX_MSG_LEN 8 + +/* + * Response Message; Requestes remote IPA driver to move IPA NAT table + * according to requested direction TO_DDR\TO_SRAM. + */ +struct ipa_move_nat_resp_msg_v01 { + + /* Mandatory */ + /* Result Code */ + struct ipa_qmi_response_type_v01 resp; + /* + * Standard response type. + * Standard response type. Contains the following data members: + * qmi_result_type -- QMI_RESULT_SUCCESS or QMI_RESULT_FAILURE + * qmi_error_type -- Error code. Possible error code values are + * described in the error codes section of each message definition. + */ +}; /* Message */ +#define IPA_MOVE_NAT_RESP_MSG_V01_MAX_MSG_LEN 7 + + /* Indication Message; Indication sent to the Modem IPA driver from + * master IPA driver about NAT table move result. + */ +struct ipa_move_nat_table_complt_ind_msg_v01 { + /* Mandatory */ + /* Master driver initialization completion status */ + struct ipa_qmi_response_type_v01 nat_table_move_status; + /* Indicates the status of nat table mvoe. If everything went + * as expected, this field is set to SUCCESS. ERROR is set + * otherwise. Extended error info may be used to convey + * additional information about the error + */ +}; /* Message */ +#define QMI_IPA_NAT_TABLE_MOVE_COMPLETE_IND_MAX_MSG_LEN_V01 7 + +/* + * Request Message; Sends IPA WLAN OPT DATA PATH RESERVED FILTER REQUEST + */ +struct ipa_wlan_opt_dp_rsrv_filter_req_msg_v01 { + + /* Mandatory */ + /* Number of filters */ + __u8 num_filters; + /* Mandatory */ + /* Timeout value in milisecond */ + __u32 timeout_val_ms; + /* Mandatory */ + /* Q6 routing table index */ + __u32 q6_rtng_table_index; + +}; +#define IPA_WLAN_OPT_DP_RSRV_FILTER_REQ_MSG_V01_MAX_MSG_LEN 18 + +/* + * Response Message; Sent for IPA WLAN OPT DATA PATH RESERVED FILTER REQUEST + */ +struct ipa_wlan_opt_dp_rsrv_filter_resp_msg_v01 { + + /* Mandatory */ + /* Result Code */ + struct ipa_qmi_response_type_v01 resp; + /* + * Standard response type. + * Standard response type. Contains the following data members: + * qmi_result_type -- QMI_RESULT_SUCCESS or QMI_RESULT_FAILURE + * qmi_error_type -- Error code. Possible error code values are + * described in the error codes section of each message definition. + */ +}; +#define IPA_WLAN_OPT_DP_RSRV_FILTER_RESP_MSG_V01_MAX_MSG_LEN 7 + +/* + * Response Message; Indicates completion of reserve filter status + * Apps driver sends indication to the modem driver that filter reservation + * was successful. + */ +struct ipa_wlan_opt_dp_rsrv_filter_complt_ind_msg_v01 { + + /* Mandatory */ + /* Result Code */ + struct ipa_qmi_response_type_v01 rsrv_filter_status; + /* + * Standard response type. + * Standard response type. Contains the following data members: + * qmi_result_type -- QMI_RESULT_SUCCESS or QMI_RESULT_FAILURE + * qmi_error_type -- Error code. Possible error code values are + * described in the error codes section of each message definition. + */ +}; +#define IPA_WLAN_OPT_DP_RSRV_FILTER_COMPLT_IND_MSG_V01_MAX_MSG_LEN 7 + +struct ip_hdr_v4_address_info_v01 { + /* V4 source IP address */ + __u32 source; + /* V4 destination IP address */ + __u32 dest; +}; + +struct ip_hdr_v6_address_info_v01 { + /* V6 source IP address */ + __u32 source[QMI_IPA_IPV6_WORD_ADDR_LEN_V01]; + /* V6 destination IP address */ + __u32 dest[QMI_IPA_IPV6_WORD_ADDR_LEN_V01]; +}; + +/** Request Message; Sends QMI_IPA_WLAN_OPT_DATAPATH_ADD_FILTER_REQ */ +struct ipa_wlan_opt_dp_add_filter_req_msg_v01 { + /* Mandatory */ + /* filter index */ + __u32 filter_idx; + /* Mandatory */ + /* IP type */ + enum ipa_ip_type_enum_v01 ip_type; + /* Optional */ + __u8 v4_addr_valid; /**< Must be set to true if v4_addr is being passed */ + /* IPv4 address */ + struct ip_hdr_v4_address_info_v01 v4_addr; + __u8 v6_addr_valid; /**< Must be set to true if v6_addr is being passed */ + /* IPv6 address */ + struct ip_hdr_v6_address_info_v01 v6_addr; +}; +#define IPA_WLAN_OPT_DP_ADD_FILTER_REQ_MSG_V01_MAX_MSG_LEN 60 + +/* + * Response Message; Indicates completion of add filter status + * Apps driver sends indication to the modem driver that filter addition + * was successful. + */ + +struct ipa_wlan_opt_dp_add_filter_resp_msg_v01 { + + /* Mandatory */ + /* Result Code */ + struct ipa_qmi_response_type_v01 resp; + /* + * Standard response type. + * Standard response type. Contains the following data members: + * qmi_result_type -- QMI_RESULT_SUCCESS or QMI_RESULT_FAILURE + * qmi_error_type -- Error code. Possible error code values are + * described in the error codes section of each message definition. + */ +}; +#define IPA_WLAN_OPT_DP_ADD_FILTER_RESP_MSG_V01_MAX_MSG_LEN 7 + +/* + * Indication Message; Indicates completion of add filter request + * Apps driver sends indication to the modem driver that filter addition + * was successful. + */ +struct ipa_wlan_opt_dp_add_filter_complt_ind_msg_v01 { + /* Mandatory */ + /* Filter removal status */ + struct ipa_qmi_response_type_v01 filter_add_status; + /* + * Standard response type. + * Standard response type. Contains the following data members: + * qmi_result_type -- QMI_RESULT_SUCCESS or QMI_RESULT_FAILURE + * qmi_error_type -- Error code. Possible error code values are + * described in the error codes section of each message definition. + */ + + /* Mandatory */ + /* filter index */ + __u32 filter_idx; + + /* Optional */ + __u8 filter_handle_valid; /**< Must be set to true if filter_handle is being passed */ + + /* filter handle */ + __u32 filter_handle; +}; +#define IPA_WLAN_OPT_DP_ADD_FILTER_COMPLT_IND_MSG_V01_MAX_MSG_LEN 21 + +/* + * Request Message; Sends QMI_IPA_WLAN_OPT_DATAPATH_REMOVE_FILTER_REQ + */ +struct ipa_wlan_opt_dp_remove_filter_req_msg_v01 { + /* Mandatory */ + /* filter index */ + __u32 filter_idx; + + /* Mandatory */ + /* filter handle */ + __u32 filter_handle; +}; +#define IPA_WLAN_OPT_DP_REMOVE_FILTER_REQ_MSG_V01_MAX_MSG_LEN 14 + +/* + * Response Message; Indicates completion of remove filter status + * Apps driver sends indication to the modem driver that filter removal + * was successful. + */ + +struct ipa_wlan_opt_dp_remove_filter_resp_msg_v01 { + + /* Mandatory */ + /* Result Code */ + struct ipa_qmi_response_type_v01 resp; + /* + * Standard response type. + * Standard response type. Contains the following data members: + * qmi_result_type -- QMI_RESULT_SUCCESS or QMI_RESULT_FAILURE + * qmi_error_type -- Error code. Possible error code values are + * described in the error codes section of each message definition. + */ +}; +#define IPA_WLAN_OPT_DP_REMOVE_FILTER_RESP_MSG_V01_MAX_MSG_LEN 7 + +struct ipa_wlan_opt_dp_remove_filter_complt_ind_msg_v01 { + /* Mandatory */ + /* Filter removal status */ + struct ipa_qmi_response_type_v01 filter_removal_status; + /* + * Standard response type. + * Standard response type. Contains the following data members: + * qmi_result_type -- QMI_RESULT_SUCCESS or QMI_RESULT_FAILURE + * qmi_error_type -- Error code. Possible error code values are + * described in the error codes section of each message definition. + */ + + /* Mandatory */ + /* filter index */ + __u32 filter_idx; +}; +#define IPA_WLAN_OPT_DP_REM_FILTER_COMPLT_IND_MSG_V01_MAX_MSG_LEN 14 + +/** Request Message; Sends QMI_IPA_WLAN_OPT_DATAPATH_REMOVE_ALL_FILTER_REQ */ +struct ipa_wlan_opt_dp_remove_all_filter_req_msg_v01 { + + /* Optional */ + /* REMOVE ALL FILTER */ + __u8 reserved_valid; /**< Must be set to true if reserved is being passed */ + __u8 reserved; + +}; +#define IPA_WLAN_OPT_DP_REM_ALL_FILTER_REQ_MSG_V01_MAX_MSG_LEN 4 +/* + * Response Message; Indicates completion of remove filter status + * Apps driver sends indication to the modem driver that filter removal + * was successful. + */ + +struct ipa_wlan_opt_dp_remove_all_filter_resp_msg_v01 { + + /* Mandatory */ + /* Result Code */ + struct ipa_qmi_response_type_v01 resp; + /* + * Standard response type. + * Standard response type. Contains the following data members: + * qmi_result_type -- QMI_RESULT_SUCCESS or QMI_RESULT_FAILURE + * qmi_error_type -- Error code. Possible error code values are + * described in the error codes section of each message definition. + */ +}; +#define IPA_WLAN_OPT_DP_REMOVE_ALL_FILTER_RESP_MSG_V01_MAX_MSG_LEN 7 + +struct ipa_wlan_opt_dp_remove_all_filter_complt_ind_msg_v01 { + + /* Mandatory */ + /* Filter removal status */ + struct ipa_qmi_response_type_v01 filter_removal_all_status; + /* + * Standard response type. + * Standard response type. Contains the following data members: + * qmi_result_type -- QMI_RESULT_SUCCESS or QMI_RESULT_FAILURE + * qmi_error_type -- Error code. Possible error code values are + * described in the error codes section of each message definition. + */ + +}; +#define IPA_WLAN_OPT_DP_REM_ALL_FILTER_COMPLT_IND_MSG_V01_MAX_MSG_LEN 7 + + +struct ipa_wlan_opt_dp_set_wlan_per_info_req_msg_v01 { + + /* Mandatory */ + /* Source WLAN EP ID */ + __u32 src_wlan_endp_id; + /* Mandatory */ + /* Destination WLAN EP ID */ + __u32 dest_wlan_endp_id; + /* Mandatory */ + /* Destination APPS EP ID */ + __u32 dest_apps_endp_id; + /* Mandatory */ + /* HDR LEN */ + __u32 hdr_len; + /* Mandatory */ + /* ETH HDR Offset */ + __u32 eth_hdr_offset; + /* Mandatory */ + /* PARTIAL HDR INFO */ + __u8 hdr_info[QMI_IPA_MAX_ETH_HDR_SIZE_V01]; +}; +#define IPA_WLAN_OPT_DP_SET_WLAN_PER_INFO_REQ_MSG_V1_MAX_MSG_LEN 102 + +/** Response Message; Sends QMI_IPA_WLAN_OPT_DATAPATH_SET_WLAN_PER_INFO_REQ */ +struct ipa_wlan_opt_dp_set_wlan_per_info_resp_msg_v01 { + + /* Mandatory */ + /* Result Code */ + struct ipa_qmi_response_type_v01 resp; + /* + * Standard response type. + * Standard response type. Contains the following data members: + * qmi_result_type -- QMI_RESULT_SUCCESS or QMI_RESULT_FAILURE + * qmi_error_type -- Error code. Possible error code values are + * described in the error codes section of each message definition. + */ + +}; +#define IPA_WLAN_OPT_DP_SET_WLAN_PER_INFO_RESP_MSG_V1_MAX_MSG_LEN 7 + + +/*Service Message Definition*/ +#define QMI_IPA_INDICATION_REGISTER_REQ_V01 0x0020 +#define QMI_IPA_INDICATION_REGISTER_RESP_V01 0x0020 +#define QMI_IPA_INIT_MODEM_DRIVER_REQ_V01 0x0021 +#define QMI_IPA_INIT_MODEM_DRIVER_RESP_V01 0x0021 +#define QMI_IPA_MASTER_DRIVER_INIT_COMPLETE_IND_V01 0x0022 +#define QMI_IPA_INSTALL_FILTER_RULE_REQ_V01 0x0023 +#define QMI_IPA_INSTALL_FILTER_RULE_RESP_V01 0x0023 +#define QMI_IPA_FILTER_INSTALLED_NOTIF_REQ_V01 0x0024 +#define QMI_IPA_FILTER_INSTALLED_NOTIF_RESP_V01 0x0024 +#define QMI_IPA_ENABLE_FORCE_CLEAR_DATAPATH_REQ_V01 0x0025 +#define QMI_IPA_ENABLE_FORCE_CLEAR_DATAPATH_RESP_V01 0x0025 +#define QMI_IPA_DISABLE_FORCE_CLEAR_DATAPATH_REQ_V01 0x0026 +#define QMI_IPA_DISABLE_FORCE_CLEAR_DATAPATH_RESP_V01 0x0026 +#define QMI_IPA_CONFIG_REQ_V01 0x0027 +#define QMI_IPA_CONFIG_RESP_V01 0x0027 +#define QMI_IPA_DISABLE_LINK_LOW_PWR_STATE_REQ_V01 0x0028 +#define QMI_IPA_DISABLE_LINK_LOW_PWR_STATE_RESP_V01 0x0028 +#define QMI_IPA_ENABLE_LINK_LOW_PWR_STATE_REQ_V01 0x0029 +#define QMI_IPA_ENABLE_LINK_LOW_PWR_STATE_RESP_V01 0x0029 +#define QMI_IPA_GET_DATA_STATS_REQ_V01 0x0030 +#define QMI_IPA_GET_DATA_STATS_RESP_V01 0x0030 +#define QMI_IPA_GET_APN_DATA_STATS_REQ_V01 0x0031 +#define QMI_IPA_GET_APN_DATA_STATS_RESP_V01 0x0031 +#define QMI_IPA_SET_DATA_USAGE_QUOTA_REQ_V01 0x0032 +#define QMI_IPA_SET_DATA_USAGE_QUOTA_RESP_V01 0x0032 +#define QMI_IPA_DATA_USAGE_QUOTA_REACHED_IND_V01 0x0033 +#define QMI_IPA_STOP_DATA_USAGE_QUOTA_REQ_V01 0x0034 +#define QMI_IPA_STOP_DATA_USAGE_QUOTA_RESP_V01 0x0034 +#define QMI_IPA_INIT_MODEM_DRIVER_CMPLT_REQ_V01 0x0035 +#define QMI_IPA_INIT_MODEM_DRIVER_CMPLT_RESP_V01 0x0035 +#define QMI_IPA_INSTALL_FILTER_RULE_EX_REQ_V01 0x0037 +#define QMI_IPA_INSTALL_FILTER_RULE_EX_RESP_V01 0x0037 +#define QMI_IPA_ENABLE_PER_CLIENT_STATS_REQ_V01 0x0038 +#define QMI_IPA_ENABLE_PER_CLIENT_STATS_RESP_V01 0x0038 +#define QMI_IPA_GET_STATS_PER_CLIENT_REQ_V01 0x0039 +#define QMI_IPA_GET_STATS_PER_CLIENT_RESP_V01 0x0039 +#define QMI_IPA_INSTALL_UL_FIREWALL_RULES_REQ_V01 0x003A +#define QMI_IPA_INSTALL_UL_FIREWALL_RULES_RESP_V01 0x003A +#define QMI_IPA_INSTALL_UL_FIREWALL_RULES_IND_V01 0x003A +#define QMI_IPA_MHI_CLK_VOTE_REQ_V01 0x003B +#define QMI_IPA_MHI_CLK_VOTE_RESP_V01 0x003B +#define QMI_IPA_MHI_READY_IND_V01 0x003C +#define QMI_IPA_MHI_ALLOC_CHANNEL_REQ_V01 0x003D +#define QMI_IPA_MHI_ALLOC_CHANNEL_RESP_V01 0x003D +#define QMI_IPA_MHI_CLEANUP_REQ_V01 0x003E +#define QMI_IPA_MHI_CLEANUP_RESP_V01 0x003E +#define QMI_IPA_ENDP_DESC_INDICATION_V01 0x003F +#define QMI_IPA_MHI_PRIME_AGGR_INFO_REQ_V01 0x0040 +#define QMI_IPA_MHI_PRIME_AGGR_INFO_RESP_V01 0x0040 +#define QMI_IPA_ADD_OFFLOAD_CONNECTION_REQ_V01 0x0041 +#define QMI_IPA_ADD_OFFLOAD_CONNECTION_RESP_V01 0x0041 +#define QMI_IPA_REMOVE_OFFLOAD_CONNECTION_REQ_V01 0x0042 +#define QMI_IPA_REMOVE_OFFLOAD_CONNECTION_RESP_V01 0x0042 +#define QMI_IPA_BW_CHANGE_INDICATION_V01 0x0044 +#define QMI_IPA_MOVE_NAT_REQ_V01 0x0046 +#define QMI_IPA_MOVE_NAT_RESP_V01 0x0046 +#define QMI_IPA_MOVE_NAT_COMPLETE_IND_V01 0x0046 +#define QMI_IPA_WLAN_OPT_DATAPATH_RSRV_FILTER_REQ_V01 0x0049 +#define QMI_IPA_WLAN_OPT_DATAPATH_RSRV_FILTER_RESP_V01 0x0049 +#define QMI_IPA_WLAN_OPT_DATAPATH_RSRV_FILTER_COMPLT_IND_V01 0x0049 +#define QMI_IPA_WLAN_OPT_DATAPATH_ADD_FILTER_REQ_V01 0x004A +#define QMI_IPA_WLAN_OPT_DATAPATH_ADD_FILTER_RESP_V01 0x004A +#define QMI_IPA_WLAN_OPT_DATAPATH_ADD_FILTER_COMPLT_IND_V01 0x004A +#define QMI_IPA_WLAN_OPT_DATAPATH_REMOVE_FILTER_REQ_V01 0x004B +#define QMI_IPA_WLAN_OPT_DATAPATH_REMOVE_FILTER_RESP_V01 0x004B +#define QMI_IPA_WLAN_OPT_DATAPATH_REMOVE_FILTER_COMPLT_IND_V01 0x004B +#define QMI_IPA_WLAN_OPT_DATAPATH_REMOVE_ALL_FILTER_REQ_V01 0x004C +#define QMI_IPA_WLAN_OPT_DATAPATH_REMOVE_ALL_FILTER_RESP_V01 0x004C +#define QMI_IPA_WLAN_OPT_DATAPATH_REMOVE_ALL_FILTER_COMPLT_IND_V01 0x004C +#define QMI_IPA_WLAN_OPT_DATAPATH_SET_WLAN_PER_INFO_REQ_V01 0x004D +#define QMI_IPA_WLAN_OPT_DATAPATH_SET_WLAN_PER_INFO_RESP_V01 0x004D + + +/* add for max length*/ +#define QMI_IPA_INIT_MODEM_DRIVER_REQ_MAX_MSG_LEN_V01 197 +#define QMI_IPA_INIT_MODEM_DRIVER_RESP_MAX_MSG_LEN_V01 25 +#define QMI_IPA_INDICATION_REGISTER_REQ_MAX_MSG_LEN_V01 16 +#define QMI_IPA_INDICATION_REGISTER_RESP_MAX_MSG_LEN_V01 7 +#define QMI_IPA_INSTALL_FILTER_RULE_REQ_MAX_MSG_LEN_V01 33705 +#define QMI_IPA_INSTALL_FILTER_RULE_RESP_MAX_MSG_LEN_V01 783 +#define QMI_IPA_FILTER_INSTALLED_NOTIF_REQ_MAX_MSG_LEN_V01 1899 +#define QMI_IPA_FILTER_INSTALLED_NOTIF_RESP_MAX_MSG_LEN_V01 7 +#define QMI_IPA_MASTER_DRIVER_INIT_COMPLETE_IND_MAX_MSG_LEN_V01 7 +#define QMI_IPA_DATA_USAGE_QUOTA_REACHED_IND_MAX_MSG_LEN_V01 19 + + +#define QMI_IPA_ENABLE_FORCE_CLEAR_DATAPATH_REQ_MAX_MSG_LEN_V01 37 +#define QMI_IPA_DISABLE_FORCE_CLEAR_DATAPATH_REQ_MAX_MSG_LEN_V01 7 +#define QMI_IPA_ENABLE_FORCE_CLEAR_DATAPATH_RESP_MAX_MSG_LEN_V01 7 +#define QMI_IPA_DISABLE_FORCE_CLEAR_DATAPATH_RESP_MAX_MSG_LEN_V01 7 + + +#define QMI_IPA_CONFIG_REQ_MAX_MSG_LEN_V01 102 +#define QMI_IPA_CONFIG_RESP_MAX_MSG_LEN_V01 7 +#define QMI_IPA_DISABLE_LINK_LOW_PWR_STATE_REQ_MAX_MSG_LEN_V01 18 +#define QMI_IPA_DISABLE_LINK_LOW_PWR_STATE_RESP_MAX_MSG_LEN_V01 7 +#define QMI_IPA_ENABLE_LINK_LOW_PWR_STATE_REQ_MAX_MSG_LEN_V01 7 +#define QMI_IPA_ENABLE_LINK_LOW_PWR_STATE_RESP_MAX_MSG_LEN_V01 7 +#define QMI_IPA_GET_DATA_STATS_REQ_MAX_MSG_LEN_V01 11 +#define QMI_IPA_GET_DATA_STATS_RESP_MAX_MSG_LEN_V01 2234 +#define QMI_IPA_GET_APN_DATA_STATS_REQ_MAX_MSG_LEN_V01 36 +#define QMI_IPA_GET_APN_DATA_STATS_RESP_MAX_MSG_LEN_V01 299 +#define QMI_IPA_SET_DATA_USAGE_QUOTA_REQ_MAX_MSG_LEN_V01 200 +#define QMI_IPA_SET_DATA_USAGE_QUOTA_RESP_MAX_MSG_LEN_V01 7 +#define QMI_IPA_STOP_DATA_USAGE_QUOTA_REQ_MAX_MSG_LEN_V01 8 +#define QMI_IPA_STOP_DATA_USAGE_QUOTA_RESP_MAX_MSG_LEN_V01 7 + +#define QMI_IPA_INIT_MODEM_DRIVER_CMPLT_REQ_MAX_MSG_LEN_V01 4 +#define QMI_IPA_INIT_MODEM_DRIVER_CMPLT_RESP_MAX_MSG_LEN_V01 7 + +#define QMI_IPA_INSTALL_FILTER_RULE_EX_REQ_MAX_MSG_LEN_V01 34021 +#define QMI_IPA_INSTALL_FILTER_RULE_EX_RESP_MAX_MSG_LEN_V01 523 + +#define QMI_IPA_ENABLE_PER_CLIENT_STATS_REQ_MAX_MSG_LEN_V01 4 +#define QMI_IPA_ENABLE_PER_CLIENT_STATS_RESP_MAX_MSG_LEN_V01 7 + +#define QMI_IPA_GET_STATS_PER_CLIENT_REQ_MAX_MSG_LEN_V01 18 +#define QMI_IPA_GET_STATS_PER_CLIENT_RESP_MAX_MSG_LEN_V01 3595 + +#define QMI_IPA_INSTALL_UL_FIREWALL_RULES_REQ_MAX_MSG_LEN_V01 9875 +#define QMI_IPA_INSTALL_UL_FIREWALL_RULES_RESP_MAX_MSG_LEN_V01 7 +#define QMI_IPA_INSTALL_UL_FIREWALL_RULES_IND_MAX_MSG_LEN_V01 11 +/* Service Object Accessor */ + +/* This is the largest MAX_MSG_LEN we have for all the messages + * we expect to receive. This argument will be used in + * qmi_handle_init to allocate a receive buffer for the socket + * associated with our qmi_handle + */ +#define QMI_IPA_MAX_MSG_LEN 22685 + +#endif/* IPA_QMI_SERVICE_V01_H */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/include/uapi/linux/msm_ipa.h b/qcom/opensource/dataipa/drivers/platform/msm/include/uapi/linux/msm_ipa.h new file mode 100644 index 0000000000..0c9ffd639b --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/include/uapi/linux/msm_ipa.h @@ -0,0 +1,4015 @@ +/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ +/* + * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2021-2022, 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _UAPI_MSM_IPA_H_ +#define _UAPI_MSM_IPA_H_ + +#ifndef __KERNEL__ +#include +#include +#include +#include +#endif +#include +#include +#include + +/** + * unique magic number of the IPA device + */ +#define IPA_IOC_MAGIC 0xCF + +/** + * IPA device full path + */ +#define IPA_DEV_NAME "/dev/ipa" + +/** + * IPA NAT table character device name + */ +#define IPA_NAT_DEV_NAME "ipaNatTable" + +/** + * IPA IPv6CT table character device name + */ +#define IPA_IPV6CT_DEV_NAME "ipaIpv6CTTable" + +/** + * name of the default routing tables for v4 and v6 + */ +#define IPA_DFLT_RT_TBL_NAME "ipa_dflt_rt" + +/** + * name for default value of invalid protocol of NAT + */ +#define IPAHAL_NAT_INVALID_PROTOCOL 0xFF + +/** + * commands supported by IPA driver + */ +#define IPA_IOCTL_ADD_HDR 0 +#define IPA_IOCTL_DEL_HDR 1 +#define IPA_IOCTL_ADD_RT_RULE 2 +#define IPA_IOCTL_DEL_RT_RULE 3 +#define IPA_IOCTL_ADD_FLT_RULE 4 +#define IPA_IOCTL_DEL_FLT_RULE 5 +#define IPA_IOCTL_COMMIT_HDR 6 +#define IPA_IOCTL_RESET_HDR 7 +#define IPA_IOCTL_COMMIT_RT 8 +#define IPA_IOCTL_RESET_RT 9 +#define IPA_IOCTL_COMMIT_FLT 10 +#define IPA_IOCTL_RESET_FLT 11 +#define IPA_IOCTL_DUMP 12 +#define IPA_IOCTL_GET_RT_TBL 13 +#define IPA_IOCTL_PUT_RT_TBL 14 +#define IPA_IOCTL_COPY_HDR 15 +#define IPA_IOCTL_QUERY_INTF 16 +#define IPA_IOCTL_QUERY_INTF_TX_PROPS 17 +#define IPA_IOCTL_QUERY_INTF_RX_PROPS 18 +#define IPA_IOCTL_GET_HDR 19 +#define IPA_IOCTL_PUT_HDR 20 +#define IPA_IOCTL_SET_FLT 21 +#define IPA_IOCTL_ALLOC_NAT_MEM 22 +#define IPA_IOCTL_V4_INIT_NAT 23 +#define IPA_IOCTL_TABLE_DMA_CMD 24 +#define IPA_IOCTL_NAT_DMA IPA_IOCTL_TABLE_DMA_CMD +#define IPA_IOCTL_INIT_IPV6CT_TABLE 25 +#define IPA_IOCTL_V4_DEL_NAT 26 +#define IPA_IOCTL_PULL_MSG 27 +#define IPA_IOCTL_GET_NAT_OFFSET 28 +#define IPA_IOCTL_RM_ADD_DEPENDENCY 29 +#define IPA_IOCTL_RM_DEL_DEPENDENCY 30 +#define IPA_IOCTL_GENERATE_FLT_EQ 31 +#define IPA_IOCTL_QUERY_INTF_EXT_PROPS 32 +#define IPA_IOCTL_QUERY_EP_MAPPING 33 +#define IPA_IOCTL_QUERY_RT_TBL_INDEX 34 +#define IPA_IOCTL_WRITE_QMAPID 35 +#define IPA_IOCTL_MDFY_FLT_RULE 36 +#define IPA_IOCTL_NOTIFY_WAN_UPSTREAM_ROUTE_ADD 37 +#define IPA_IOCTL_NOTIFY_WAN_UPSTREAM_ROUTE_DEL 38 +#define IPA_IOCTL_NOTIFY_WAN_EMBMS_CONNECTED 39 +#define IPA_IOCTL_ADD_HDR_PROC_CTX 40 +#define IPA_IOCTL_DEL_HDR_PROC_CTX 41 +#define IPA_IOCTL_MDFY_RT_RULE 42 +#define IPA_IOCTL_ADD_RT_RULE_AFTER 43 +#define IPA_IOCTL_ADD_FLT_RULE_AFTER 44 +#define IPA_IOCTL_GET_HW_VERSION 45 +#define IPA_IOCTL_ADD_RT_RULE_EXT 46 +#define IPA_IOCTL_ADD_VLAN_IFACE 47 +#define IPA_IOCTL_DEL_VLAN_IFACE 48 +#define IPA_IOCTL_ADD_L2TP_VLAN_MAPPING 49 +#define IPA_IOCTL_DEL_L2TP_VLAN_MAPPING 50 +#define IPA_IOCTL_NAT_MODIFY_PDN 51 +#define IPA_IOCTL_ALLOC_NAT_TABLE 52 +#define IPA_IOCTL_ALLOC_IPV6CT_TABLE 53 +#define IPA_IOCTL_DEL_NAT_TABLE 54 +#define IPA_IOCTL_DEL_IPV6CT_TABLE 55 +#define IPA_IOCTL_CLEANUP 56 +#define IPA_IOCTL_QUERY_WLAN_CLIENT 57 +#define IPA_IOCTL_GET_VLAN_MODE 58 +#define IPA_IOCTL_ADD_BRIDGE_VLAN_MAPPING 59 +#define IPA_IOCTL_DEL_BRIDGE_VLAN_MAPPING 60 +#define IPA_IOCTL_ODL_QUERY_ADAPL_EP_INFO 61 +#define IPA_IOCTL_ODL_GET_AGG_BYTE_LIMIT 62 +#define IPA_IOCTL_ODL_QUERY_MODEM_CONFIG 63 +#define IPA_IOCTL_GSB_CONNECT 64 +#define IPA_IOCTL_GSB_DISCONNECT 65 +#define IPA_IOCTL_WIGIG_FST_SWITCH 66 +#define IPA_IOCTL_ADD_RT_RULE_V2 67 +#define IPA_IOCTL_ADD_RT_RULE_EXT_V2 68 +#define IPA_IOCTL_ADD_RT_RULE_AFTER_V2 69 +#define IPA_IOCTL_MDFY_RT_RULE_V2 70 +#define IPA_IOCTL_ADD_FLT_RULE_V2 71 +#define IPA_IOCTL_ADD_FLT_RULE_AFTER_V2 72 +#define IPA_IOCTL_MDFY_FLT_RULE_V2 73 +#define IPA_IOCTL_FNR_COUNTER_ALLOC 74 +#define IPA_IOCTL_FNR_COUNTER_DEALLOC 75 +#define IPA_IOCTL_FNR_COUNTER_QUERY 76 +#define IPA_IOCTL_SET_FNR_COUNTER_INFO 77 +#define IPA_IOCTL_GET_NAT_IN_SRAM_INFO 78 +#define IPA_IOCTL_APP_CLOCK_VOTE 79 +#define IPA_IOCTL_PDN_CONFIG 80 +#define IPA_IOCTL_SET_MAC_FLT 81 +#define IPA_IOCTL_GET_PHERIPHERAL_EP_INFO 82 +#define IPA_IOCTL_ADD_UC_ACT_ENTRY 83 +#define IPA_IOCTL_DEL_UC_ACT_ENTRY 84 +#define IPA_IOCTL_SET_SW_FLT 85 +#define IPA_IOCTL_SET_PKT_THRESHOLD 87 +#define IPA_IOCTL_ADD_EoGRE_MAPPING 88 +#define IPA_IOCTL_DEL_EoGRE_MAPPING 89 +#define IPA_IOCTL_SET_IPPT_SW_FLT 90 +#define IPA_IOCTL_ADD_MACSEC_MAPPING 92 +#define IPA_IOCTL_DEL_MACSEC_MAPPING 93 +#define IPA_IOCTL_SET_NAT_EXC_RT_TBL_IDX 94 +#define IPA_IOCTL_SET_CONN_TRACK_EXC_RT_TBL_IDX 95 +#define IPA_IOCTL_COAL_EVICT_POLICY 96 +#define IPA_IOCTL_SET_EXT_ROUTER_MODE 97 +/** + * max size of the header to be inserted + */ +#define IPA_HDR_MAX_SIZE 255 + +/** + * max size of the name of the resource (routing table, header) + */ +#define IPA_RESOURCE_NAME_MAX 32 + +/** + * max number of interface properties + */ +#define IPA_NUM_PROPS_MAX 35 + +/** + * size of the mac address + */ +#define IPA_MAC_ADDR_SIZE 6 + +/** + * max number of mbim streams + */ +#define IPA_MBIM_MAX_STREAM_NUM 8 + +/** + * size of the ipv6 address + */ +#define IPA_WAN_MSG_IPv6_ADDR_GW_LEN 4 + +/** + * max number of lan clients supported per device type + * for LAN stats via HW. + */ +#define IPA_MAX_NUM_HW_PATH_CLIENTS 16 + +/** + * max number of destination pipes possible for a client. + */ +#define QMI_IPA_MAX_CLIENT_DST_PIPES 4 + +/** + * Max number of clients supported for mac based exception + */ + +#define IPA_MAX_NUM_MAC_FLT 32 +#define IPA_MAX_NUM_IPv4_SEGS_FLT 16 +#define IPA_MAX_NUM_IFACE_FLT 4 + + +/** + * MAX number of the FLT_RT stats counter supported. + */ +#define IPA_MAX_FLT_RT_CNT_INDEX (128) +#define IPA_FLT_RT_HW_COUNTER (120) +#define IPA_FLT_RT_SW_COUNTER \ + (IPA_MAX_FLT_RT_CNT_INDEX - IPA_FLT_RT_HW_COUNTER) +#define IPA_MAX_FLT_RT_CLIENTS 60 + +/** + * Max number of ports/IPs IPPT exception + */ + +#define IPA_MAX_IPPT_NUM_PORT_FLT 5 + +/** + * New feature flag for CV2X config. + */ + +#define IPA_CV2X_SUPPORT + +/** + * the attributes of the rule (routing or filtering) + */ +#define IPA_FLT_TOS (1ul << 0) +#define IPA_FLT_PROTOCOL (1ul << 1) +#define IPA_FLT_SRC_ADDR (1ul << 2) +#define IPA_FLT_DST_ADDR (1ul << 3) +#define IPA_FLT_SRC_PORT_RANGE (1ul << 4) +#define IPA_FLT_DST_PORT_RANGE (1ul << 5) +#define IPA_FLT_TYPE (1ul << 6) +#define IPA_FLT_CODE (1ul << 7) +#define IPA_FLT_SPI (1ul << 8) +#define IPA_FLT_SRC_PORT (1ul << 9) +#define IPA_FLT_DST_PORT (1ul << 10) +#define IPA_FLT_TC (1ul << 11) +#define IPA_FLT_FLOW_LABEL (1ul << 12) +#define IPA_FLT_NEXT_HDR (1ul << 13) +#define IPA_FLT_META_DATA (1ul << 14) +#define IPA_FLT_FRAGMENT (1ul << 15) +#define IPA_FLT_TOS_MASKED (1ul << 16) +#define IPA_FLT_MAC_SRC_ADDR_ETHER_II (1ul << 17) +#define IPA_FLT_MAC_DST_ADDR_ETHER_II (1ul << 18) +#define IPA_FLT_MAC_SRC_ADDR_802_3 (1ul << 19) +#define IPA_FLT_MAC_DST_ADDR_802_3 (1ul << 20) +#define IPA_FLT_MAC_ETHER_TYPE (1ul << 21) +#define IPA_FLT_MAC_DST_ADDR_L2TP (1ul << 22) +#define IPA_FLT_TCP_SYN (1ul << 23) +#define IPA_FLT_TCP_SYN_L2TP (1ul << 24) +#define IPA_FLT_L2TP_INNER_IP_TYPE (1ul << 25) +#define IPA_FLT_L2TP_INNER_IPV4_DST_ADDR (1ul << 26) +#define IPA_FLT_IS_PURE_ACK (1ul << 27) +#define IPA_FLT_VLAN_ID (1ul << 28) +#define IPA_FLT_MAC_SRC_ADDR_802_1Q (1ul << 29) +#define IPA_FLT_MAC_DST_ADDR_802_1Q (1ul << 30) +#define IPA_FLT_L2TP_UDP_INNER_MAC_DST_ADDR (1ul << 31) + +/* Extended attributes for the rule (routing or filtering) */ +#define IPA_FLT_EXT_L2TP_UDP_TCP_SYN (1ul << 0) +#define IPA_FLT_EXT_L2TP_UDP_INNER_ETHER_TYPE (1ul << 1) +#define IPA_FLT_EXT_MTU (1ul << 2) +#define IPA_FLT_EXT_L2TP_UDP_INNER_NEXT_HDR (1ul << 3) +#define IPA_FLT_EXT_NEXT_HDR (1ul << 4) + + +/** + * maximal number of NAT PDNs in the PDN config table + */ +#define IPA_MAX_PDN_NUM 16 +#define IPA_MAX_PDN_NUM_v4 5 + +/** + * Macros duplicated from ipa_lnx_spearhead_stats.h and + * ipa_lnx_stats.h. All three macros should match. + * This needs to be updated whenever the header file structure + * and structure length macros are updated to match exactly + * the same. This is done to overcome backward and forward + * compatibility between userspace and driver spearhead structures. + */ +/* IPA Linux basic stats structure macros */ +#define IPA_LNX_PG_RECYCLE_STATS_STRUCT_LEN 32 +#define IPA_LNX_EXCEPTION_STATS_STRUCT_LEN 40 +#define IPA_LNX_ODL_EP_STATS_STRUCT_LEN 16 +#define IPA_LNX_HOLB_DISCARD_STATS_STRUCT_LEN 16 +#define IPA_LNX_HOLB_MONITOR_STATS_STRUCT_LEN 16 +#define IPA_LNX_HOLB_DROP_AND_MON_STATS_STRUCT_LEN (8 + 16 + 16) +#define IPA_LNX_GENERIC_STATS_STRUCT_LEN (40 + 32 + 40 + 16 + 40) +/* IPA Linux clock stats structures */ +#define IPA_LNX_PM_CLIENT_STATS_STRUCT_LEN 24 +#define IPA_LNX_CLOCK_STATS_STRUCT_LEN (24 + 24) +/* Generic instance structures */ +#define IPA_LNX_GSI_RX_DEBUG_STATS_STRUCT_LEN 48 +#define IPA_LNX_GSI_TX_DEBUG_STATS_STRUCT_LEN 56 +#define IPA_LNX_GSI_DEBUG_STATS_STRUCT_LEN (8 + 48 + 56) +#define IPA_LNX_PIPE_INFO_STATS_STRUCT_LEN 120 +/* IPA Linux wlan instance stats structures */ +#define IPA_LNX_WLAN_INSTANCE_INFO_STRUCT_LEN (32 + 112 + 120) +#define IPA_LNX_WLAN_INST_STATS_STRUCT_LEN (8 + 264) +/* IPA Linux eth instance stats structures */ +#define IPA_LNX_ETH_INSTANCE_INFO_STRUCT_LEN (16 + 112 + 120) +#define IPA_LNX_ETH_INST_STATS_STRUCT_LEN (8 + 248) +/* IPA Linux usb instance stats structures */ +#define IPA_LNX_USB_INSTANCE_INFO_STRUCT_LEN (16 + 112 + 120) +#define IPA_LNX_USB_INST_STATS_STRUCT_LEN (8 + 248) +/* IPA Linux mhip instance stats structures */ +#define IPA_LNX_MHIP_INSTANCE_INFO_STRUCT_LEN (16 + 112 + 120) +#define IPA_LNX_MHIP_INST_STATS_STRUCT_LEN (8 + 248) +/* IPA Linux consolidated stats structure */ +#define IPA_LNX_CONSOLIDATED_STATS_STRUCT_LEN (8 + 48) +/* IPA Linux Instance allocation info structures */ +#define IPA_LNX_EACH_INST_ALLOC_INFO_STRUCT_LEN (24 + 12 + 12 + 16) +#define IPA_LNX_STATS_ALL_INFO_STRUCT_LEN (32 + 128 + 128 + 128) +#define IPA_LNX_STATS_SPEARHEAD_CTX_STRUCT_LEN (8 + 4 + 416) + +/** + * enum ipa_client_type - names for the various IPA "clients" + * these are from the perspective of the clients, for e.g. + * HSIC1_PROD means HSIC client is the producer and IPA is the + * consumer. + * PROD clients are always even, and CONS clients are always odd. + * Add new clients in the end of the list or replace reserved one, + * update IPA_CLIENT_MAX and update the strings array ipa_clients_strings[] + * while keeping the ordering of the clients the same + */ +enum ipa_client_type { + IPA_CLIENT_HSIC1_PROD = 0, + IPA_CLIENT_HSIC1_CONS = 1, + + IPA_CLIENT_HSIC2_PROD = 2, + IPA_CLIENT_HSIC2_CONS = 3, + + IPA_CLIENT_HSIC3_PROD = 4, + IPA_CLIENT_HSIC3_CONS = 5, + + IPA_CLIENT_HSIC4_PROD = 6, + IPA_CLIENT_HSIC4_CONS = 7, + + IPA_CLIENT_HSIC5_PROD = 8, + IPA_CLIENT_HSIC5_CONS = 9, + + IPA_CLIENT_WLAN1_PROD = 10, + IPA_CLIENT_WLAN1_CONS = 11, + + IPA_CLIENT_A5_WLAN_AMPDU_PROD = 12, + IPA_CLIENT_WLAN2_CONS = 13, + + IPA_CLIENT_WLAN3_PROD = 14, + IPA_CLIENT_WLAN3_CONS = 15, + + /* RESERVED PROD = 16, */ + IPA_CLIENT_WLAN4_CONS = 17, + + IPA_CLIENT_USB_PROD = 18, + IPA_CLIENT_USB_CONS = 19, + + IPA_CLIENT_USB2_PROD = 20, + IPA_CLIENT_USB2_CONS = 21, + + IPA_CLIENT_USB3_PROD = 22, + IPA_CLIENT_USB3_CONS = 23, + + IPA_CLIENT_USB4_PROD = 24, + IPA_CLIENT_USB4_CONS = 25, + + IPA_CLIENT_UC_USB_PROD = 26, + IPA_CLIENT_USB_DPL_CONS = 27, + + IPA_CLIENT_A2_EMBEDDED_PROD = 28, + IPA_CLIENT_A2_EMBEDDED_CONS = 29, + + IPA_CLIENT_A2_TETHERED_PROD = 30, + IPA_CLIENT_A2_TETHERED_CONS = 31, + + IPA_CLIENT_APPS_LAN_PROD = 32, + IPA_CLIENT_APPS_LAN_CONS = 33, + + IPA_CLIENT_APPS_WAN_PROD = 34, + IPA_CLIENT_APPS_LAN_WAN_PROD = IPA_CLIENT_APPS_WAN_PROD, + IPA_CLIENT_APPS_WAN_CONS = 35, + + IPA_CLIENT_APPS_CMD_PROD = 36, + IPA_CLIENT_A5_LAN_WAN_CONS = 37, + + IPA_CLIENT_ODU_PROD = 38, + IPA_CLIENT_ODU_EMB_CONS = 39, + + /* RESERVED PROD = 40, */ + IPA_CLIENT_ODU_TETH_CONS = 41, + + IPA_CLIENT_MHI_PROD = 42, + IPA_CLIENT_MHI_CONS = 43, + + IPA_CLIENT_MEMCPY_DMA_SYNC_PROD = 44, + IPA_CLIENT_MEMCPY_DMA_SYNC_CONS = 45, + + IPA_CLIENT_MEMCPY_DMA_ASYNC_PROD = 46, + IPA_CLIENT_MEMCPY_DMA_ASYNC_CONS = 47, + + IPA_CLIENT_ETHERNET_PROD = 48, + IPA_CLIENT_ETHERNET_CONS = 49, + + IPA_CLIENT_Q6_LAN_PROD = 50, + IPA_CLIENT_Q6_LAN_CONS = 51, + + IPA_CLIENT_Q6_WAN_PROD = 52, + IPA_CLIENT_Q6_WAN_CONS = 53, + + IPA_CLIENT_Q6_CMD_PROD = 54, + IPA_CLIENT_Q6_DUN_CONS = 55, + + IPA_CLIENT_Q6_DECOMP_PROD = 56, + IPA_CLIENT_Q6_DECOMP_CONS = 57, + + IPA_CLIENT_Q6_DECOMP2_PROD = 58, + IPA_CLIENT_Q6_DECOMP2_CONS = 59, + + /* RESERVED PROD = 60, */ + IPA_CLIENT_Q6_LTE_WIFI_AGGR_CONS = 61, + + IPA_CLIENT_TEST_PROD = 62, + IPA_CLIENT_TEST_CONS = 63, + + IPA_CLIENT_TEST1_PROD = 64, + IPA_CLIENT_TEST1_CONS = 65, + + IPA_CLIENT_TEST2_PROD = 66, + IPA_CLIENT_TEST2_CONS = 67, + + IPA_CLIENT_TEST3_PROD = 68, + IPA_CLIENT_TEST3_CONS = 69, + + IPA_CLIENT_TEST4_PROD = 70, + IPA_CLIENT_TEST4_CONS = 71, + + /* RESERVED PROD = 72, */ + IPA_CLIENT_DUMMY_CONS = 73, + + IPA_CLIENT_Q6_DL_NLO_DATA_PROD = 74, + IPA_CLIENT_Q6_UL_NLO_DATA_CONS = 75, + + /* RESERVERD PROD = 76, */ + IPA_CLIENT_Q6_UL_NLO_ACK_CONS = 77, + + /* RESERVERD PROD = 78, */ + IPA_CLIENT_Q6_QBAP_STATUS_CONS = 79, + + /* RESERVERD PROD = 80, */ + IPA_CLIENT_MHI_DPL_CONS = 81, + + /* RESERVERD PROD = 82, */ + IPA_CLIENT_ODL_DPL_CONS = 83, + + IPA_CLIENT_Q6_AUDIO_DMA_MHI_PROD = 84, + IPA_CLIENT_Q6_AUDIO_DMA_MHI_CONS = 85, + + IPA_CLIENT_WIGIG_PROD = 86, + IPA_CLIENT_WIGIG1_CONS = 87, + + /* RESERVERD PROD = 88, */ + IPA_CLIENT_WIGIG2_CONS = 89, + + /* RESERVERD PROD = 90, */ + IPA_CLIENT_WIGIG3_CONS = 91, + + /* RESERVERD PROD = 92, */ + IPA_CLIENT_WIGIG4_CONS = 93, + + /* RESERVED PROD = 94, */ + IPA_CLIENT_APPS_WAN_COAL_CONS = 95, + + IPA_CLIENT_MHI_PRIME_TETH_PROD = 96, + IPA_CLIENT_MHI_PRIME_TETH_CONS = 97, + + IPA_CLIENT_MHI_PRIME_RMNET_PROD = 98, + IPA_CLIENT_MHI_PRIME_RMNET_CONS = 99, + + IPA_CLIENT_MHI_PRIME_DPL_PROD = 100, + IPA_CLIENT_MHI_COAL_CONS = 101, + + IPA_CLIENT_AQC_ETHERNET_PROD = 102, + IPA_CLIENT_AQC_ETHERNET_CONS = 103, + + IPA_CLIENT_APPS_WAN_LOW_LAT_PROD = 104, + IPA_CLIENT_APPS_WAN_LOW_LAT_CONS = 105, + + IPA_CLIENT_QDSS_PROD = 106, + IPA_CLIENT_MHI_QDSS_CONS = 107, + + IPA_CLIENT_RTK_ETHERNET_PROD = 108, + IPA_CLIENT_RTK_ETHERNET_CONS = 109, + + IPA_CLIENT_MHI_LOW_LAT_PROD = 110, + IPA_CLIENT_MHI_LOW_LAT_CONS = 111, + + IPA_CLIENT_MHI2_PROD = 112, + IPA_CLIENT_MHI2_CONS = 113, + + IPA_CLIENT_Q6_CV2X_PROD = 114, + IPA_CLIENT_Q6_CV2X_CONS = 115, + + IPA_CLIENT_ETHERNET2_PROD = 116, + IPA_CLIENT_ETHERNET2_CONS = 117, + + /* RESERVED PROD = 118, */ + IPA_CLIENT_WLAN2_CONS1 = 119, + + IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_PROD = 120, + IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_CONS = 121, + + IPA_CLIENT_Q6_DL_NLO_LL_DATA_PROD = 122, + /* RESERVED CONS = 123, */ + + /* RESERVED PROD = 124, */ + IPA_CLIENT_TPUT_CONS = 125, + + /* RESERVED PROD = 126, */ + IPA_CLIENT_APPS_LAN_COAL_CONS = 127, + + IPA_CLIENT_IPSEC_DECAP_PROD = 128, + IPA_CLIENT_IPSEC_DECAP_RECOVERABLE_ERR_CONS = 129, + + IPA_CLIENT_IPSEC_ENCAP_PROD = 130, + IPA_CLIENT_IPSEC_DECAP_NON_RECOVERABLE_ERR_CONS = 131, + + IPA_CLIENT_Q6_DL_NLO_DATA_XLAT_PROD = 132, + IPA_CLIENT_IPSEC_ENCAP_ERR_CONS = 133, + + /* RESERVED PROD = 134, */ + IPA_CLIENT_UC_RTP1_CONS = 135, + + /* RESERVED PROD = 136, */ + IPA_CLIENT_UC_RTP2_CONS = 137, + + /* RESERVED PROD = 138, */ + IPA_CLIENT_UC_RTP3_CONS = 139, + + /* RESERVED PROD = 140, */ + IPA_CLIENT_UC_RTP4_CONS = 141, +}; + +#define IPA_CLIENT_MAX (IPA_CLIENT_UC_RTP4_CONS + 1) + +#define IPA_CLIENT_WLAN2_PROD IPA_CLIENT_A5_WLAN_AMPDU_PROD +#define IPA_CLIENT_Q6_DL_NLO_DATA_PROD IPA_CLIENT_Q6_DL_NLO_DATA_PROD +#define IPA_CLIENT_Q6_UL_NLO_ACK_CONS IPA_CLIENT_Q6_UL_NLO_ACK_CONS +#define IPA_CLIENT_Q6_QBAP_STATUS_CONS IPA_CLIENT_Q6_QBAP_STATUS_CONS +#define IPA_CLIENT_MHI_DPL_CONS IPA_CLIENT_MHI_DPL_CONS +#define IPA_CLIENT_Q6_AUDIO_DMA_MHI_PROD IPA_CLIENT_Q6_AUDIO_DMA_MHI_PROD +#define IPA_CLIENT_Q6_AUDIO_DMA_MHI_CONS IPA_CLIENT_Q6_AUDIO_DMA_MHI_CONS +#define IPA_CLIENT_WIGIG_PROD IPA_CLIENT_WIGIG_PROD +#define IPA_CLIENT_WIGIG1_CONS IPA_CLIENT_WIGIG1_CONS +#define IPA_CLIENT_WIGIG2_CONS IPA_CLIENT_WIGIG2_CONS +#define IPA_CLIENT_WIGIG3_CONS IPA_CLIENT_WIGIG3_CONS +#define IPA_CLIENT_WIGIG4_CONS IPA_CLIENT_WIGIG4_CONS +#define IPA_CLIENT_APPS_WAN_COAL_CONS IPA_CLIENT_APPS_WAN_COAL_CONS +#define IPA_CLIENT_MHI_PRIME_TETH_PROD IPA_CLIENT_MHI_PRIME_TETH_PROD +#define IPA_CLIENT_MHI_PRIME_TETH_CONS IPA_CLIENT_MHI_PRIME_TETH_CONS +#define IPA_CLIENT_MHI_PRIME_RMNET_PROD IPA_CLIENT_MHI_PRIME_RMNET_PROD +#define IPA_CLIENT_MHI_PRIME_RMNET_CONS IPA_CLIENT_MHI_PRIME_RMNET_CONS +#define IPA_CLIENT_MHI_PRIME_DPL_PROD IPA_CLIENT_MHI_PRIME_DPL_PROD +#define IPA_CLIENT_AQC_ETHERNET_PROD IPA_CLIENT_AQC_ETHERNET_PROD +#define IPA_CLIENT_AQC_ETHERNET_CONS IPA_CLIENT_AQC_ETHERNET_CONS +#define IPA_CLIENT_MHI_QDSS_CONS IPA_CLIENT_MHI_QDSS_CONS +#define IPA_CLIENT_QDSS_PROD IPA_CLIENT_QDSS_PROD +#define IPA_CLIENT_WLAN2_CONS1 IPA_CLIENT_WLAN2_CONS1 +#define IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_PROD IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_PROD +#define IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_CONS IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_CONS +#define IPA_CLIENT_Q6_DL_NLO_LL_DATA_PROD IPA_CLIENT_Q6_DL_NLO_LL_DATA_PROD +#define IPA_CLIENT_APPS_LAN_COAL_CONS IPA_CLIENT_APPS_LAN_COAL_CONS +#define IPA_CLIENT_MHI_COAL_CONS IPA_CLIENT_MHI_COAL_CONS +#define IPA_CLIENT_IPSEC_DECAP_PROD IPA_CLIENT_IPSEC_DECAP_PROD +#define IPA_CLIENT_IPSEC_ENCAP_PROD IPA_CLIENT_IPSEC_ENCAP_PROD +#define IPA_CLIENT_Q6_DL_NLO_DATA_XLAT_PROD IPA_CLIENT_Q6_DL_NLO_DATA_XLAT_PROD +#define IPA_CLIENT_IPSEC_DECAP_RECOVERABLE_ERR_CONS IPA_CLIENT_IPSEC_DECAP_RECOVERABLE_ERR_CONS +#define IPA_CLIENT_IPSEC_DECAP_NON_RECOVERABLE_ERR_CONS \ + IPA_CLIENT_IPSEC_DECAP_NON_RECOVERABLE_ERR_CONS +#define IPA_CLIENT_IPSEC_ENCAP_ERR_CONS IPA_CLIENT_IPSEC_ENCAP_ERR_CONS + +#define IPA_CLIENT_IS_APPS_CONS(client) \ + ((client) == IPA_CLIENT_APPS_LAN_CONS || \ + (client) == IPA_CLIENT_APPS_LAN_COAL_CONS || \ + (client) == IPA_CLIENT_APPS_WAN_CONS || \ + (client) == IPA_CLIENT_APPS_WAN_COAL_CONS || \ + (client) == IPA_CLIENT_APPS_WAN_LOW_LAT_CONS || \ + (client) == IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_CONS) + +#define IPA_CLIENT_IS_APPS_PROD(client) \ + ((client) == IPA_CLIENT_APPS_LAN_PROD || \ + (client) == IPA_CLIENT_APPS_WAN_PROD || \ + (client) == IPA_CLIENT_APPS_WAN_LOW_LAT_PROD || \ + (client) == IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_PROD) + +#define IPA_CLIENT_IS_USB_CONS(client) \ + ((client) == IPA_CLIENT_USB_CONS || \ + (client) == IPA_CLIENT_USB2_CONS || \ + (client) == IPA_CLIENT_USB3_CONS || \ + (client) == IPA_CLIENT_USB_DPL_CONS || \ + (client) == IPA_CLIENT_USB4_CONS) + +#define IPA_CLIENT_IS_WAN_CONS(client) \ + ((client) == IPA_CLIENT_APPS_WAN_CONS || \ + (client) == IPA_CLIENT_APPS_WAN_COAL_CONS) + +#define IPA_CLIENT_IS_LAN_CONS(client) \ + ((client) == IPA_CLIENT_APPS_LAN_CONS || \ + (client) == IPA_CLIENT_APPS_LAN_COAL_CONS) + +#define IPA_CLIENT_IS_LAN_or_WAN_CONS(client) \ + ((client) == IPA_CLIENT_APPS_LAN_CONS || \ + (client) == IPA_CLIENT_APPS_WAN_CONS) + +#define IPA_CLIENT_IS_APPS_COAL_CONS(client) \ + ((client) == IPA_CLIENT_APPS_LAN_COAL_CONS || \ + (client) == IPA_CLIENT_APPS_WAN_COAL_CONS) + +#define IPA_CLIENT_IS_LOW_LAT_CONS(client) \ + ((client) == IPA_CLIENT_APPS_WAN_LOW_LAT_CONS) + +#define IPA_CLIENT_IS_WLAN_CONS(client) \ + ((client) == IPA_CLIENT_WLAN1_CONS || \ + (client) == IPA_CLIENT_WLAN2_CONS || \ + (client) == IPA_CLIENT_WLAN3_CONS || \ + (client) == IPA_CLIENT_WLAN2_CONS1 || \ + (client) == IPA_CLIENT_WLAN4_CONS) + +#define IPA_CLIENT_IS_ODU_CONS(client) \ + ((client) == IPA_CLIENT_ODU_EMB_CONS || \ + (client) == IPA_CLIENT_ODU_TETH_CONS) + +#define IPA_CLIENT_IS_Q6_CONS(client) \ + ((client) == IPA_CLIENT_Q6_LAN_CONS || \ + (client) == IPA_CLIENT_Q6_WAN_CONS || \ + (client) == IPA_CLIENT_Q6_DUN_CONS || \ + (client) == IPA_CLIENT_Q6_DECOMP_CONS || \ + (client) == IPA_CLIENT_Q6_DECOMP2_CONS || \ + (client) == IPA_CLIENT_Q6_LTE_WIFI_AGGR_CONS || \ + (client) == IPA_CLIENT_Q6_UL_NLO_DATA_CONS || \ + (client) == IPA_CLIENT_Q6_UL_NLO_ACK_CONS || \ + (client) == IPA_CLIENT_Q6_QBAP_STATUS_CONS || \ + (client) == IPA_CLIENT_Q6_CV2X_CONS || \ + (client) == IPA_CLIENT_Q6_AUDIO_DMA_MHI_CONS) + +#define IPA_CLIENT_IS_Q6_PROD(client) \ + ((client) == IPA_CLIENT_Q6_LAN_PROD || \ + (client) == IPA_CLIENT_Q6_WAN_PROD || \ + (client) == IPA_CLIENT_Q6_CMD_PROD || \ + (client) == IPA_CLIENT_Q6_DECOMP_PROD || \ + (client) == IPA_CLIENT_Q6_DECOMP2_PROD || \ + (client) == IPA_CLIENT_Q6_DL_NLO_LL_DATA_PROD || \ + (client) == IPA_CLIENT_Q6_DL_NLO_DATA_PROD || \ + (client) == IPA_CLIENT_Q6_CV2X_PROD || \ + (client) == IPA_CLIENT_Q6_AUDIO_DMA_MHI_PROD) + +#define IPA_CLIENT_IS_Q6_NON_ZIP_CONS(client) \ + ((client) == IPA_CLIENT_Q6_LAN_CONS || \ + (client) == IPA_CLIENT_Q6_WAN_CONS || \ + (client) == IPA_CLIENT_Q6_DUN_CONS || \ + (client) == IPA_CLIENT_Q6_LTE_WIFI_AGGR_CONS || \ + (client) == IPA_CLIENT_Q6_UL_NLO_DATA_CONS || \ + (client) == IPA_CLIENT_Q6_UL_NLO_ACK_CONS || \ + (client) == IPA_CLIENT_Q6_QBAP_STATUS_CONS || \ + (client) == IPA_CLIENT_Q6_CV2X_CONS || \ + (client) == IPA_CLIENT_Q6_AUDIO_DMA_MHI_CONS) + +#define IPA_CLIENT_IS_Q6_ZIP_CONS(client) \ + ((client) == IPA_CLIENT_Q6_DECOMP_CONS || \ + (client) == IPA_CLIENT_Q6_DECOMP2_CONS) + +#define IPA_CLIENT_IS_Q6_NON_ZIP_PROD(client) \ + ((client) == IPA_CLIENT_Q6_LAN_PROD || \ + (client) == IPA_CLIENT_Q6_WAN_PROD || \ + (client) == IPA_CLIENT_Q6_CMD_PROD || \ + (client) == IPA_CLIENT_Q6_DL_NLO_DATA_PROD || \ + (client) == IPA_CLIENT_Q6_DL_NLO_LL_DATA_PROD || \ + (client) == IPA_CLIENT_Q6_CV2X_PROD || \ + (client) == IPA_CLIENT_Q6_AUDIO_DMA_MHI_PROD) + +#define IPA_CLIENT_IS_Q6_ZIP_PROD(client) \ + ((client) == IPA_CLIENT_Q6_DECOMP_PROD || \ + (client) == IPA_CLIENT_Q6_DECOMP2_PROD) + +#define IPA_CLIENT_IS_MEMCPY_DMA_CONS(client) \ + ((client) == IPA_CLIENT_MEMCPY_DMA_SYNC_CONS || \ + (client) == IPA_CLIENT_MEMCPY_DMA_ASYNC_CONS) + +#define IPA_CLIENT_IS_MEMCPY_DMA_PROD(client) \ + ((client) == IPA_CLIENT_MEMCPY_DMA_SYNC_PROD || \ + (client) == IPA_CLIENT_MEMCPY_DMA_ASYNC_PROD) + +#define IPA_CLIENT_IS_MHI(client) \ + ((client) == IPA_CLIENT_MHI_CONS || \ + (client) == IPA_CLIENT_MHI_PROD || \ + (client) == IPA_CLIENT_MHI2_PROD || \ + (client) == IPA_CLIENT_MHI2_CONS || \ + (client) == IPA_CLIENT_MHI_DPL_CONS || \ + (client) == IPA_CLIENT_MHI_LOW_LAT_CONS || \ + (client) == IPA_CLIENT_MHI_LOW_LAT_PROD || \ + (client) == IPA_CLIENT_MHI_QDSS_CONS || \ + (client) == IPA_CLIENT_MHI_COAL_CONS) + +#define IPA_CLIENT_IS_TEST_PROD(client) \ + ((client) == IPA_CLIENT_TEST_PROD || \ + (client) == IPA_CLIENT_TEST1_PROD || \ + (client) == IPA_CLIENT_TEST2_PROD || \ + (client) == IPA_CLIENT_TEST3_PROD || \ + (client) == IPA_CLIENT_TEST4_PROD) + +#define IPA_CLIENT_IS_TEST_CONS(client) \ + ((client) == IPA_CLIENT_TEST_CONS || \ + (client) == IPA_CLIENT_TEST1_CONS || \ + (client) == IPA_CLIENT_TEST2_CONS || \ + (client) == IPA_CLIENT_TEST3_CONS || \ + (client) == IPA_CLIENT_TEST4_CONS) + +#define IPA_CLIENT_IS_TEST(client) \ + (IPA_CLIENT_IS_TEST_PROD(client) || IPA_CLIENT_IS_TEST_CONS(client)) + +/** + * The following is used to describe the types of memory NAT can + * reside in. + * + * PLEASE KEEP THE FOLLOWING IN SYNC WITH ipa3_nat_mem_in_as_str() + * BELOW. + */ +enum ipa3_nat_mem_in { + IPA_NAT_MEM_IN_DDR = 0, + IPA_NAT_MEM_IN_SRAM = 1, + + IPA_NAT_MEM_IN_MAX +}; + +#define IPA_VALID_NAT_MEM_IN(t) \ + ((t) >= IPA_NAT_MEM_IN_DDR && (t) < IPA_NAT_MEM_IN_MAX) + +/** + * enum ipa_ip_type - Address family: IPv4 or IPv6 + * + * PLEASE KEEP THE FOLLOWING IN SYNC WITH ipa_ip_type_as_str() + * BELOW. + */ +enum ipa_ip_type { + IPA_IP_v4, + IPA_IP_v6, + IPA_IP_MAX +}; + +#define VALID_IPA_IP_TYPE(t) \ + ((t) >= IPA_IP_v4 && (t) < IPA_IP_MAX) + +/** + * enum ipa_rule_type - Type of routing or filtering rule + * Hashable: Rule will be located at the hashable tables + * Non_Hashable: Rule will be located at the non-hashable tables + */ +enum ipa_rule_type { + IPA_RULE_HASHABLE, + IPA_RULE_NON_HASHABLE, +}; +#define IPA_RULE_TYPE_MAX (IPA_RULE_NON_HASHABLE + 1) + +/** + * enum ipa_flt_action - action field of filtering rule + * + * Pass to routing: 5'd0 + * Pass to source NAT: 5'd1 + * Pass to destination NAT: 5'd2 + * Pass to default output pipe (e.g., Apps or Modem): 5'd3 + */ +enum ipa_flt_action { + IPA_PASS_TO_ROUTING, + IPA_PASS_TO_SRC_NAT, + IPA_PASS_TO_DST_NAT, + IPA_PASS_TO_EXCEPTION +}; + +/** + * enum ipa_wlan_event - Events for wlan client + * + * wlan client connect: New wlan client connected + * wlan client disconnect: wlan client disconnected + * wlan client power save: wlan client moved to power save + * wlan client normal: wlan client moved out of power save + * sw routing enable: ipa routing is disabled + * sw routing disable: ipa routing is enabled + * wlan ap connect: wlan AP(access point) is up + * wlan ap disconnect: wlan AP(access point) is down + * wlan sta connect: wlan STA(station) is up + * wlan sta disconnect: wlan STA(station) is down + * wlan client connect ex: new wlan client connected + * wlan scc switch: wlan interfaces in scc mode + * wlan mcc switch: wlan interfaces in mcc mode + * wlan wdi enable: wdi data path completed + * wlan wdi disable: wdi data path teardown + */ +enum ipa_wlan_event { + WLAN_CLIENT_CONNECT, + WLAN_CLIENT_DISCONNECT, + WLAN_CLIENT_POWER_SAVE_MODE, + WLAN_CLIENT_NORMAL_MODE, + SW_ROUTING_ENABLE, + SW_ROUTING_DISABLE, + WLAN_AP_CONNECT, + WLAN_AP_DISCONNECT, + WLAN_STA_CONNECT, + WLAN_STA_DISCONNECT, + WLAN_CLIENT_CONNECT_EX, + WLAN_SWITCH_TO_SCC, + WLAN_SWITCH_TO_MCC, + WLAN_WDI_ENABLE, + WLAN_WDI_DISABLE, + IPA_WLAN_EVENT_MAX +}; + +/** + * enum ipa_wan_event - Events for wan client + * + * wan default route add/del + * wan embms connect: New wan embms interface connected + */ +enum ipa_wan_event { + WAN_UPSTREAM_ROUTE_ADD = IPA_WLAN_EVENT_MAX, + WAN_UPSTREAM_ROUTE_DEL, + WAN_EMBMS_CONNECT, + WAN_XLAT_CONNECT, + IPA_WAN_EVENT_MAX +}; + +enum ipa_ecm_event { + ECM_CONNECT = IPA_WAN_EVENT_MAX, + ECM_DISCONNECT, + IPA_ECM_EVENT_MAX, +}; + +enum ipa_tethering_stats_event { + IPA_TETHERING_STATS_UPDATE_STATS = IPA_ECM_EVENT_MAX, + IPA_TETHERING_STATS_UPDATE_NETWORK_STATS, + IPA_TETHERING_STATS_EVENT_MAX, +}; + + +enum ipa_quota_event { + IPA_QUOTA_REACH = IPA_TETHERING_STATS_EVENT_MAX, + IPA_QUOTA_EVENT_MAX, +}; + +enum ipa_ssr_event { + IPA_SSR_BEFORE_SHUTDOWN = IPA_QUOTA_EVENT_MAX, + IPA_SSR_AFTER_POWERUP, + IPA_SSR_EVENT_MAX, +}; + +enum ipa_vlan_l2tp_event { + ADD_VLAN_IFACE = IPA_SSR_EVENT_MAX, + DEL_VLAN_IFACE, + ADD_L2TP_VLAN_MAPPING, + DEL_L2TP_VLAN_MAPPING, + IPA_VLAN_L2TP_EVENT_MAX, +}; + +enum ipa_per_client_stats_event { + IPA_PER_CLIENT_STATS_CONNECT_EVENT = IPA_VLAN_L2TP_EVENT_MAX, + IPA_PER_CLIENT_STATS_DISCONNECT_EVENT, + IPA_PER_CLIENT_STATS_EVENT_MAX, +}; + +enum ipa_vlan_bridge_event { + ADD_BRIDGE_VLAN_MAPPING = IPA_PER_CLIENT_STATS_EVENT_MAX, + DEL_BRIDGE_VLAN_MAPPING, + BRIDGE_VLAN_MAPPING_MAX, +}; + +enum ipa_wlan_fw_ssr_event { + WLAN_FWR_SSR_BEFORE_SHUTDOWN = BRIDGE_VLAN_MAPPING_MAX, + IPA_WLAN_FW_SSR_EVENT_MAX, +#define IPA_WLAN_FW_SSR_EVENT_MAX IPA_WLAN_FW_SSR_EVENT_MAX +}; + +enum ipa_gsb_event { + IPA_GSB_CONNECT = IPA_WLAN_FW_SSR_EVENT_MAX, + IPA_GSB_DISCONNECT, + IPA_GSB_EVENT_MAX, +}; + +enum ipa_coalesce_event { + IPA_COALESCE_ENABLE = IPA_GSB_EVENT_MAX, + IPA_COALESCE_DISABLE, + IPA_COALESCE_EVENT_MAX +#define IPA_COALESCE_EVENT_MAX IPA_COALESCE_EVENT_MAX +}; + +enum ipa_mtu_event { + IPA_SET_MTU = IPA_COALESCE_EVENT_MAX, + IPA_MTU_EVENT_MAX +#define IPA_MTU_EVENT_MAX IPA_MTU_EVENT_MAX +}; + +enum ipa_peripheral_event { + IPA_PERIPHERAL_CONNECT = ECM_CONNECT, + IPA_PERIPHERAL_DISCONNECT = ECM_DISCONNECT +}; + +#define WIGIG_CLIENT_CONNECT (IPA_MTU_EVENT_MAX) +#define WIGIG_FST_SWITCH (WIGIG_CLIENT_CONNECT + 1) +#define WIGIG_EVENT_MAX (WIGIG_FST_SWITCH + 1) + +enum ipa_pdn_config_event { + IPA_PDN_DEFAULT_MODE_CONFIG = WIGIG_EVENT_MAX, /* Default mode. */ + IPA_PDN_IP_COLLISION_MODE_CONFIG, /* IP Collision detected. */ + IPA_PDN_IP_PASSTHROUGH_MODE_CONFIG, /* IP Passthrough mode. */ + IPA_PDN_CONFIG_EVENT_MAX +#define IPA_PDN_CONFIG_EVENT_MAX IPA_PDN_CONFIG_EVENT_MAX +}; + +enum ipa_mac_flt_event { + IPA_MAC_FLT_EVENT = IPA_PDN_CONFIG_EVENT_MAX, + IPA_MAC_FLT_EVENT_MAX +#define IPA_MAC_FLT_EVENT_MAX IPA_MAC_FLT_EVENT_MAX +}; + +enum ipa_sockv5_event { + IPA_SOCKV5_ADD = IPA_MAC_FLT_EVENT_MAX, + IPA_SOCKV5_DEL, + IPA_SOCKV5_EVENT_MAX +#define IPA_SOCKV5_EVENT_MAX IPA_SOCKV5_EVENT_MAX +}; + +enum ipa_warning_limit_event { + IPA_WARNING_LIMIT_REACHED = IPA_SOCKV5_EVENT_MAX, + IPA_WARNING_LIMIT_EVENT_MAX, +#define IPA_WARNING_LIMIT_EVENT_MAX IPA_WARNING_LIMIT_EVENT_MAX +}; + +enum ipa_sw_flt_event { + IPA_SW_FLT_EVENT = IPA_WARNING_LIMIT_EVENT_MAX, + IPA_SW_FLT_EVENT_MAX +#define IPA_SW_FLT_EVENT_MAX IPA_SW_FLT_EVENT_MAX +}; + +enum ipa_pkt_threshold_event { + IPA_PKT_THRESHOLD_EVENT = IPA_SW_FLT_EVENT_MAX, + IPA_PKT_THRESHOLD_EVENT_MAX +#define IPA_PKT_THRESHOLD_EVENT_MAX IPA_PKT_THRESHOLD_EVENT_MAX +}; + + +enum ipa_move_nat_table_event { + IPA_MOVE_NAT_TABLE = IPA_PKT_THRESHOLD_EVENT_MAX, + IPA_MOVE_NAT_EVENT_MAX +#define IPA_MOVE_NAT_EVENT_MAX IPA_MOVE_NAT_EVENT_MAX +}; + +enum ipa_eogre_event { + IPA_EoGRE_UP_EVENT = IPA_MOVE_NAT_EVENT_MAX, + IPA_EoGRE_DOWN_EVENT, + IPA_EoGRE_EVENT_MAX +#define IPA_EoGRE_EVENT_MAX IPA_EoGRE_EVENT_MAX +}; + +enum ipa_ippt_sw_flt_event { + IPA_IPPT_SW_FLT_EVENT = IPA_EoGRE_EVENT_MAX, + IPA_IPPT_SW_FLT_EVENT_MAX +#define IPA_IPPT_SW_FLT_EVENT_MAX IPA_IPPT_SW_FLT_EVENT_MAX +}; + +enum ipa_macsec_event { + IPA_MACSEC_ADD_EVENT = IPA_IPPT_SW_FLT_EVENT_MAX, + IPA_MACSEC_DEL_EVENT, + IPA_MACSEC_EVENT_MAX +#define IPA_MACSEC_EVENT_MAX IPA_MACSEC_EVENT_MAX +}; + +enum ipa_ext_route_evt { + IPA_SET_EXT_ROUTER_MODE_EVENT = IPA_MACSEC_EVENT_MAX, + IPA_SET_EXT_ROUTER_MODE_EVENT_MAX +#define IPA_SET_EXT_ROUTER_MODE_EVENT_MAX IPA_SET_EXT_ROUTER_MODE_EVENT_MAX +}; + +#define IPA_EVENT_MAX_NUM (IPA_SET_EXT_ROUTER_MODE_EVENT_MAX) +#define IPA_EVENT_MAX ((int)IPA_EVENT_MAX_NUM) + +/** + * enum ipa_rm_resource_name - IPA RM clients identification names + * + * PROD resources are always even, and CONS resources are always odd. + * Add new clients in the end of the list and update IPA_RM_RESOURCE_MAX + */ +enum ipa_rm_resource_name { + IPA_RM_RESOURCE_Q6_PROD = 0, + IPA_RM_RESOURCE_Q6_CONS = 1, + + IPA_RM_RESOURCE_USB_PROD = 2, + IPA_RM_RESOURCE_USB_CONS = 3, + + IPA_RM_RESOURCE_USB_DPL_DUMMY_PROD = 4, + IPA_RM_RESOURCE_USB_DPL_CONS = 5, + + IPA_RM_RESOURCE_HSIC_PROD = 6, + IPA_RM_RESOURCE_HSIC_CONS = 7, + + IPA_RM_RESOURCE_STD_ECM_PROD = 8, + IPA_RM_RESOURCE_APPS_CONS = 9, + + IPA_RM_RESOURCE_RNDIS_PROD = 10, + /* RESERVED CONS = 11, */ + + IPA_RM_RESOURCE_WWAN_0_PROD = 12, + /* RESERVED CONS = 13, */ + + IPA_RM_RESOURCE_WLAN_PROD = 14, + IPA_RM_RESOURCE_WLAN_CONS = 15, + + IPA_RM_RESOURCE_ODU_ADAPT_PROD = 16, + IPA_RM_RESOURCE_ODU_ADAPT_CONS = 17, + + IPA_RM_RESOURCE_MHI_PROD = 18, + IPA_RM_RESOURCE_MHI_CONS = 19, + + IPA_RM_RESOURCE_ETHERNET_PROD = 20, + IPA_RM_RESOURCE_ETHERNET_CONS = 21, +}; +#define IPA_RM_RESOURCE_MAX (IPA_RM_RESOURCE_ETHERNET_CONS + 1) + +/** + * enum ipa_hw_type - IPA hardware version type + * @IPA_HW_None: IPA hardware version not defined + * @IPA_HW_v1_0: IPA hardware version 1.0 + * @IPA_HW_v1_1: IPA hardware version 1.1 + * @IPA_HW_v2_0: IPA hardware version 2.0 + * @IPA_HW_v2_1: IPA hardware version 2.1 + * @IPA_HW_v2_5: IPA hardware version 2.5 + * @IPA_HW_v2_6: IPA hardware version 2.6 + * @IPA_HW_v2_6L: IPA hardware version 2.6L + * @IPA_HW_v3_0: IPA hardware version 3.0 + * @IPA_HW_v3_1: IPA hardware version 3.1 + * @IPA_HW_v3_5: IPA hardware version 3.5 + * @IPA_HW_v3_5_1: IPA hardware version 3.5.1 + * @IPA_HW_v4_0: IPA hardware version 4.0 + * @IPA_HW_v4_1: IPA hardware version 4.1 + * @IPA_HW_v4_2: IPA hardware version 4.2 + * @IPA_HW_v4_5: IPA hardware version 4.5 + * @IPA_HW_v4_7: IPA hardware version 4.7 + * @IPA_HW_v4_9: IPA hardware version 4.9 + * @IPA_HW_v4_11: IPA hardware version 4.11 + * @IPA_HW_v5_0: IPA hardware version 5.0 + * @IPA_HW_v5_1: IPA hardware version 5.1 + * @IPA_HW_v5_2: IPA hardware version 5.2 + * @IPA_HW_v5_5: IPA hardware version 5.5 + * @IPA_HW_v6_0: IPA hardware version 6.0 + */ +enum ipa_hw_type { + IPA_HW_None = 0, + IPA_HW_v1_0 = 1, + IPA_HW_v1_1 = 2, + IPA_HW_v2_0 = 3, + IPA_HW_v2_1 = 4, + IPA_HW_v2_5 = 5, + IPA_HW_v2_6 = IPA_HW_v2_5, + IPA_HW_v2_6L = 6, + IPA_HW_v3_0 = 10, + IPA_HW_v3_1 = 11, + IPA_HW_v3_5 = 12, + IPA_HW_v3_5_1 = 13, + IPA_HW_v4_0 = 14, + IPA_HW_v4_1 = 15, + IPA_HW_v4_2 = 16, + IPA_HW_v4_5 = 17, + IPA_HW_v4_7 = 18, + IPA_HW_v4_9 = 19, + IPA_HW_v4_11 = 20, + IPA_HW_v5_0 = 21, + IPA_HW_v5_1 = 22, + IPA_HW_v5_2 = 23, + IPA_HW_v5_5 = 24, + IPA_HW_v6_0 = 25, +}; + +#define IPA_HW_MAX (IPA_HW_v6_0 + 1) + +#define IPA_HW_v4_0 IPA_HW_v4_0 +#define IPA_HW_v4_1 IPA_HW_v4_1 +#define IPA_HW_v4_2 IPA_HW_v4_2 +#define IPA_HW_v4_5 IPA_HW_v4_5 +#define IPA_HW_v4_7 IPA_HW_v4_7 +#define IPA_HW_v4_9 IPA_HW_v4_9 +#define IPA_HW_v4_11 IPA_HW_v4_11 +#define IPA_HW_v5_0 IPA_HW_v5_0 +#define IPA_HW_v5_1 IPA_HW_v5_1 +#define IPA_HW_v5_2 IPA_HW_v5_2 +#define IPA_HW_v5_5 IPA_HW_v5_5 +#define IPA_HW_v6_0 IPA_HW_v6_0 + +/** + * struct ipa_rule_attrib - attributes of a routing/filtering + * rule, all in LE + * @attrib_mask: what attributes are valid + * @src_port_lo: low port of src port range + * @src_port_hi: high port of src port range + * @dst_port_lo: low port of dst port range + * @dst_port_hi: high port of dst port range + * @type: ICMP/IGMP type + * @code: ICMP/IGMP code + * @spi: IPSec SPI + * @src_port: exact src port + * @dst_port: exact dst port + * @meta_data: metadata val + * @meta_data_mask: metadata mask + * @u.v4.tos: type of service + * @u.v4.protocol: protocol + * @u.v4.src_addr: src address value + * @u.v4.src_addr_mask: src address mask + * @u.v4.dst_addr: dst address value + * @u.v4.dst_addr_mask: dst address mask + * @u.v6.tc: traffic class + * @u.v6.flow_label: flow label + * @u.v6.next_hdr: next header + * @u.v6.src_addr: src address val + * @u.v6.src_addr_mask: src address mask + * @u.v6.dst_addr: dst address val + * @u.v6.dst_addr_mask: dst address mask + * @vlan_id: vlan id value + * @payload_length: Payload length. + * @ext_attrib_mask: Extended attributes. + * @l2tp_udp_next_hdr: next header in L2TP tunneling + * @frag_encoding: is-frag equation + */ +struct ipa_rule_attrib { + uint32_t attrib_mask; + uint16_t src_port_lo; + uint16_t src_port_hi; + uint16_t dst_port_lo; + uint16_t dst_port_hi; + uint8_t type; + uint8_t code; + uint8_t tos_value; + uint8_t tos_mask; + uint32_t spi; + uint16_t src_port; + uint16_t dst_port; + uint32_t meta_data; + uint32_t meta_data_mask; + uint8_t src_mac_addr[ETH_ALEN]; + uint8_t src_mac_addr_mask[ETH_ALEN]; + uint8_t dst_mac_addr[ETH_ALEN]; + uint8_t dst_mac_addr_mask[ETH_ALEN]; + uint16_t ether_type; + union { + struct { + uint8_t tos; + uint8_t protocol; + uint32_t src_addr; + uint32_t src_addr_mask; + uint32_t dst_addr; + uint32_t dst_addr_mask; + } v4; + struct { + uint8_t tc; + uint32_t flow_label; + uint8_t next_hdr; + uint32_t src_addr[4]; + uint32_t src_addr_mask[4]; + uint32_t dst_addr[4]; + uint32_t dst_addr_mask[4]; + } v6; + } u; + __u16 vlan_id; + __u16 payload_length; + __u32 ext_attrib_mask; + __u8 l2tp_udp_next_hdr; + __u8 is_frag_encoding; + __u32 padding2; +}; + + +/*! @brief The maximum number of Mask Equal 32 Eqns */ +#define IPA_IPFLTR_NUM_MEQ_32_EQNS 2 + +/*! @brief The maximum number of IHL offset Mask Equal 32 Eqns */ +#define IPA_IPFLTR_NUM_IHL_MEQ_32_EQNS 2 + +/*! @brief The maximum number of Mask Equal 128 Eqns */ +#define IPA_IPFLTR_NUM_MEQ_128_EQNS 2 + +/*! @brief The maximum number of IHL offset Range Check 16 Eqns */ +#define IPA_IPFLTR_NUM_IHL_RANGE_16_EQNS 2 + +/*! @brief Offset and 16 bit comparison equation */ +struct ipa_ipfltr_eq_16 { + int8_t offset; + uint16_t value; +}; + +/*! @brief Offset and 32 bit comparison equation */ +struct ipa_ipfltr_eq_32 { + int8_t offset; + uint32_t value; +}; + +/*! @brief Offset and 128 bit masked comparison equation */ +struct ipa_ipfltr_mask_eq_128 { + int8_t offset; + uint8_t mask[16]; + uint8_t value[16]; +}; + +/*! @brief Offset and 32 bit masked comparison equation */ +struct ipa_ipfltr_mask_eq_32 { + int8_t offset; + uint32_t mask; + uint32_t value; +}; + +/*! @brief Equation for identifying a range. Ranges are inclusive */ +struct ipa_ipfltr_range_eq_16 { + int8_t offset; + uint16_t range_low; + uint16_t range_high; +}; + +/*! @brief Rule equations which are set according to DS filter installation */ +struct ipa_ipfltri_rule_eq { + /*! 16-bit Bitmask to indicate how many eqs are valid in this rule */ + uint16_t rule_eq_bitmap; + + /* + * tos_eq_present field has two meanings: + * IPA ver < 4.5: + * specifies if a type of service check rule is present + * (as the field name reveals). + * IPA ver >= 4.5: + * specifies if a tcp pure ack check rule is present + */ + uint8_t tos_eq_present; + /*! The value to check against the type of service (ipv4) field */ + uint8_t tos_eq; + /*! Specifies if a protocol check rule is present */ + uint8_t protocol_eq_present; + /*! The value to check against the protocol (ipv6) field */ + uint8_t protocol_eq; + /*! The number of ip header length offset 16 bit range check + * rules in this rule + */ + uint8_t num_ihl_offset_range_16; + /*! An array of the registered ip header length offset 16 bit + * range check rules + */ + struct ipa_ipfltr_range_eq_16 + ihl_offset_range_16[IPA_IPFLTR_NUM_IHL_RANGE_16_EQNS]; + /*! The number of mask equal 32 rules present in this rule */ + uint8_t num_offset_meq_32; + /*! An array of all the possible mask equal 32 rules in this rule */ + struct ipa_ipfltr_mask_eq_32 + offset_meq_32[IPA_IPFLTR_NUM_MEQ_32_EQNS]; + /*! Specifies if the traffic class rule is present in this rule */ + uint8_t tc_eq_present; + /*! The value to check the traffic class (ipv4) field against */ + uint8_t tc_eq; + /*! Specifies if the flow equals rule is present in this rule */ + uint8_t fl_eq_present; + /*! The value to check the flow (ipv6) field against */ + uint32_t fl_eq; + /*! The number of ip header length offset 16 bit equations in this + * rule + */ + uint8_t ihl_offset_eq_16_present; + /*! The ip header length offset 16 bit equation */ + struct ipa_ipfltr_eq_16 ihl_offset_eq_16; + /*! The number of ip header length offset 32 bit equations in this + * rule + */ + uint8_t ihl_offset_eq_32_present; + /*! The ip header length offset 32 bit equation */ + struct ipa_ipfltr_eq_32 ihl_offset_eq_32; + /*! The number of ip header length offset 32 bit mask equations in + * this rule + */ + uint8_t num_ihl_offset_meq_32; + /*! The ip header length offset 32 bit mask equation */ + struct ipa_ipfltr_mask_eq_32 + ihl_offset_meq_32[IPA_IPFLTR_NUM_IHL_MEQ_32_EQNS]; + /*! The number of ip header length offset 128 bit equations in this + * rule + */ + uint8_t num_offset_meq_128; + /*! The ip header length offset 128 bit equation */ + struct ipa_ipfltr_mask_eq_128 + offset_meq_128[IPA_IPFLTR_NUM_MEQ_128_EQNS]; + /*! The metadata 32 bit masked comparison equation present or not */ + /* Metadata based rules are added internally by IPA driver */ + uint8_t metadata_meq32_present; + /*! The metadata 32 bit masked comparison equation */ + struct ipa_ipfltr_mask_eq_32 metadata_meq32; + /*! Specifies if the Fragment equation is present in this rule */ + uint8_t ipv4_frag_eq_present; + /*! The IS-FRAG equation enhancement change since IPA6.0 + * values: IS-FRAG-0, Is-Primary-1, Is-Secondary-2, Not-Frag-3 + */ + uint8_t is_frag_encoding; +}; + +/** + * struct ipa_flt_rule - attributes of a filtering rule + * @retain_hdr: bool switch to instruct IPA core to add back to the packet + * the header removed as part of header removal + * @to_uc: bool switch to pass packet to micro-controller + * @action: action field + * @rt_tbl_hdl: handle of table from "get" + * @attrib: attributes of the rule + * @eq_attrib: attributes of the rule in equation form (valid when + * eq_attrib_type is true) + * @rt_tbl_idx: index of RT table referred to by filter rule (valid when + * eq_attrib_type is true and non-exception action) + * @eq_attrib_type: true if equation level form used to specify attributes + * @max_prio: bool switch. is this rule with Max priority? meaning on rule hit, + * IPA will use the rule and will not look for other rules that may have + * higher priority + * @hashable: bool switch. is this rule hashable or not? + * ipa uses hashable rules to cache their hit results to be used in + * consecutive packets + * @rule_id: rule_id to be assigned to the filter rule. In case client specifies + * rule_id as 0 the driver will assign a new rule_id + * @set_metadata: bool switch. should metadata replacement at the NAT block + * take place? + * @pdn_idx: if action is "pass to source\destination NAT" then a comparison + * against the PDN index in the matching PDN entry will take place as an + * additional condition for NAT hit. + */ +struct ipa_flt_rule { + uint8_t retain_hdr; + uint8_t to_uc; + enum ipa_flt_action action; + uint32_t rt_tbl_hdl; + struct ipa_rule_attrib attrib; + struct ipa_ipfltri_rule_eq eq_attrib; + uint32_t rt_tbl_idx; + uint8_t eq_attrib_type; + uint8_t max_prio; + uint8_t hashable; + uint16_t rule_id; + uint8_t set_metadata; + uint8_t pdn_idx; +}; + +#define IPA_FLTRT_TTL_UPDATE + +/** + * struct ipa_flt_rule_v2 - attributes of a filtering rule + * @retain_hdr: bool switch to instruct IPA core to add back to the packet + * the header removed as part of header removal + * @to_uc: bool switch to pass packet to micro-controller + * @action: action field + * @rt_tbl_hdl: handle of table from "get" + * @attrib: attributes of the rule + * @eq_attrib: attributes of the rule in equation form (valid when + * eq_attrib_type is true) + * @rt_tbl_idx: index of RT table referred to by filter rule (valid when + * eq_attrib_type is true and non-exception action) + * @eq_attrib_type: true if equation level form used to specify attributes + * @max_prio: bool switch. is this rule with Max priority? meaning on rule hit, + * IPA will use the rule and will not look for other rules that may have + * higher priority + * @hashable: bool switch. is this rule hashable or not? + * ipa uses hashable rules to cache their hit results to be used in + * consecutive packets + * @rule_id: rule_id to be assigned to the filter rule. In case client specifies + * rule_id as 0 the driver will assign a new rule_id + * @set_metadata: bool switch. should metadata replacement at the NAT block + * take place? + * @pdn_idx: if action is "pass to source\destination NAT" then a comparison + * against the PDN index in the matching PDN entry will take place as an + * additional condition for NAT hit. + * @enable_stats: is true when we want to enable stats for this + * flt rule. + * @cnt_idx: if 0 means disable, otherwise use for index. + * will be assigned by ipa driver. + * @close_aggr_irq_mod: close aggregation/coalescing and close GSI + * interrupt moderation + * @ttl_update: bool to indicate whether TTL update is needed or not. + * @qos_class: QOS classification value. + */ +struct ipa_flt_rule_v2 { + uint8_t retain_hdr; + uint8_t to_uc; + enum ipa_flt_action action; + uint32_t rt_tbl_hdl; + struct ipa_rule_attrib attrib; + struct ipa_ipfltri_rule_eq eq_attrib; + uint32_t rt_tbl_idx; + uint8_t eq_attrib_type; + uint8_t max_prio; + uint8_t hashable; + uint16_t rule_id; + uint8_t set_metadata; + uint8_t pdn_idx; + uint8_t enable_stats; + uint8_t cnt_idx; + uint8_t close_aggr_irq_mod; + uint8_t ttl_update; + uint8_t qos_class; +}; + +/** + * enum ipa_hdr_l2_type - L2 header type + * IPA_HDR_L2_NONE: L2 header which isn't Ethernet II and isn't 802_3 + * IPA_HDR_L2_ETHERNET_II: L2 header of type Ethernet II + * IPA_HDR_L2_802_3: L2 header of type 802_3 + * IPA_HDR_L2_802_1Q: L2 header of type 802_1Q + */ +enum ipa_hdr_l2_type { + IPA_HDR_L2_NONE, + IPA_HDR_L2_ETHERNET_II, + IPA_HDR_L2_802_3, + IPA_HDR_L2_802_1Q, +}; +#define IPA_HDR_L2_MAX (IPA_HDR_L2_802_1Q + 1) + +#define IPA_HDR_L2_802_1Q IPA_HDR_L2_802_1Q + +/** + * enum ipa_hdr_l2_type - Processing context type + * + * IPA_HDR_PROC_NONE: No processing context + * IPA_HDR_PROC_ETHII_TO_ETHII: Process Ethernet II to Ethernet II + * IPA_HDR_PROC_ETHII_TO_802_3: Process Ethernet II to 802_3 + * IPA_HDR_PROC_802_3_TO_ETHII: Process 802_3 to Ethernet II + * IPA_HDR_PROC_802_3_TO_802_3: Process 802_3 to 802_3 + * IPA_HDR_PROC_L2TP_HEADER_ADD: + * IPA_HDR_PROC_L2TP_HEADER_REMOVE: + * IPA_HDR_PROC_ETHII_TO_ETHII_EX: Process Ethernet II to Ethernet II with + * generic lengths of src and dst headers + * IPA_HDR_PROC_L2TP_UDP_HEADER_ADD: Process WLAN To Ethernet packets to + * add L2TP UDP header. + * IPA_HDR_PROC_L2TP_UDP_HEADER_REMOVE: Process Ethernet To WLAN packets to + * remove L2TP UDP header. + * IPA_HDR_PROC_SET_DSCP: + * IPA_HDR_PROC_EoGRE_HEADER_ADD: Add IPV[46] GRE header + * IPA_HDR_PROC_EoGRE_HEADER_REMOVE: Remove IPV[46] GRE header + * IPA_HDR_PROC_RTP_METADATA_STREAM: Process RTP Frames at uCP + */ +enum ipa_hdr_proc_type { + IPA_HDR_PROC_NONE, + IPA_HDR_PROC_ETHII_TO_ETHII, + IPA_HDR_PROC_ETHII_TO_802_3, + IPA_HDR_PROC_802_3_TO_ETHII, + IPA_HDR_PROC_802_3_TO_802_3, + IPA_HDR_PROC_L2TP_HEADER_ADD, + IPA_HDR_PROC_L2TP_HEADER_REMOVE, + IPA_HDR_PROC_ETHII_TO_ETHII_EX, + IPA_HDR_PROC_L2TP_UDP_HEADER_ADD, + IPA_HDR_PROC_L2TP_UDP_HEADER_REMOVE, + IPA_HDR_PROC_SET_DSCP, + IPA_HDR_PROC_EoGRE_HEADER_ADD, + IPA_HDR_PROC_EoGRE_HEADER_REMOVE, + IPA_HDR_PROC_RTP_METADATA_STREAM0, + IPA_HDR_PROC_RTP_METADATA_STREAM1, + IPA_HDR_PROC_RTP_METADATA_STREAM2, + IPA_HDR_PROC_RTP_METADATA_STREAM3, +}; +#define IPA_HDR_PROC_MAX (IPA_HDR_PROC_RTP_METADATA_STREAM3 + 1) + +/** + * struct ipa_rt_rule - attributes of a routing rule + * @dst: dst "client" + * @hdr_hdl: handle to the dynamic header + it is not an index or an offset + * @hdr_proc_ctx_hdl: handle to header processing context. if it is provided + hdr_hdl shall be 0 + * @attrib: attributes of the rule + * @max_prio: bool switch. is this rule with Max priority? meaning on rule hit, + * IPA will use the rule and will not look for other rules that may have + * higher priority + * @hashable: bool switch. is this rule hashable or not? + * ipa uses hashable rules to cache their hit results to be used in + * consecutive packets + * @retain_hdr: bool switch to instruct IPA core to add back to the packet + * the header removed as part of header removal + * @coalesce: bool to decide whether packets should be coalesced or not + */ +struct ipa_rt_rule { + enum ipa_client_type dst; + uint32_t hdr_hdl; + uint32_t hdr_proc_ctx_hdl; + struct ipa_rule_attrib attrib; + uint8_t max_prio; + uint8_t hashable; + uint8_t retain_hdr; + uint8_t coalesce; +}; +#define IPA_RT_SUPPORT_COAL + +/** + * struct ipa_rt_rule_v2 - attributes of a routing rule + * @dst: dst "client" + * @hdr_hdl: handle to the dynamic header + it is not an index or an offset + * @hdr_proc_ctx_hdl: handle to header processing context. if it is provided + hdr_hdl shall be 0 + * @attrib: attributes of the rule + * @max_prio: bool switch. is this rule with Max priority? meaning on rule hit, + * IPA will use the rule and will not look for other rules that may have + * higher priority + * @hashable: bool switch. is this rule hashable or not? + * ipa uses hashable rules to cache their hit results to be used in + * consecutive packets + * @retain_hdr: bool switch to instruct IPA core to add back to the packet + * the header removed as part of header removal + * @coalesce: bool to decide whether packets should be coalesced or not + * @enable_stats: is true when we want to enable stats for this + * rt rule. + * @cnt_idx: if enable_stats is 1 and cnt_idx is 0, then cnt_idx + * will be assigned by ipa driver. + * @close_aggr_irq_mod: close aggregation/coalescing and close GSI + * interrupt moderation + * @ttl_update: bool to indicate whether TTL update is needed or not. + * @qos_class: QOS classification value. + * @skip_ingress: bool to skip ingress policing. + */ +struct ipa_rt_rule_v2 { + enum ipa_client_type dst; + uint32_t hdr_hdl; + uint32_t hdr_proc_ctx_hdl; + struct ipa_rule_attrib attrib; + uint8_t max_prio; + uint8_t hashable; + uint8_t retain_hdr; + uint8_t coalesce; + uint8_t enable_stats; + uint8_t cnt_idx; + uint8_t close_aggr_irq_mod; + uint8_t ttl_update; + uint8_t qos_class; + uint8_t skip_ingress; +}; + +/** + * struct ipa_hdr_add - header descriptor includes in and out + * parameters + * @name: name of the header + * @hdr: actual header to be inserted + * @hdr_len: size of above header + * @type: l2 header type + * @is_partial: header not fully specified + * @hdr_hdl: out parameter, handle to header, valid when status is 0 + * @status: out parameter, status of header add operation, + * 0 for success, + * -1 for failure + * @is_eth2_ofst_valid: is eth2_ofst field valid? + * @eth2_ofst: offset to start of Ethernet-II/802.3 header + */ +struct ipa_hdr_add { + char name[IPA_RESOURCE_NAME_MAX]; + uint8_t hdr[IPA_HDR_MAX_SIZE]; + uint8_t hdr_len; + enum ipa_hdr_l2_type type; + uint8_t is_partial; + uint32_t hdr_hdl; + int status; + uint8_t is_eth2_ofst_valid; + uint16_t eth2_ofst; +}; + +/** + * struct ipa_ioc_add_hdr - header addition parameters (support + * multiple headers and commit) + * @commit: should headers be written to IPA HW also? + * @num_hdrs: num of headers that follow + * @ipa_hdr_add hdr: all headers need to go here back to + * back, no pointers + */ +struct ipa_ioc_add_hdr { + uint8_t commit; + uint8_t num_hdrs; + struct ipa_hdr_add hdr[0]; +}; + +/** + * struct ipa_l2tp_header_add_procparams - + * @eth_hdr_retained: Specifies if Ethernet header is retained or not + * @input_ip_version: Specifies if Input header is IPV4(0) or IPV6(1) + * @output_ip_version: Specifies if template header is IPV4(0) or IPV6(1) + * @single_pass: Specifies if second pass is required or not + */ +struct ipa_l2tp_header_add_procparams { + __u32 eth_hdr_retained:1; + __u32 input_ip_version:1; + __u32 output_ip_version:1; + __u32 second_pass:1; + __u32 reserved:28; + __u32 padding; +}; + +/** + * struct ipa_l2tp_header_remove_procparams - + * @hdr_len_remove: Specifies how much of the header needs to + be removed in bytes + * @eth_hdr_retained: Specifies if Ethernet header is retained or not + * @hdr_ofst_pkt_size_valid: Specifies if the Header offset is valid + * @hdr_ofst_pkt_size: If hdr_ofst_pkt_size_valid =1, this indicates where the + packet size field (2bytes) resides + * @hdr_endianness: 0:little endian, 1:big endian + */ +struct ipa_l2tp_header_remove_procparams { + uint32_t hdr_len_remove:8; + uint32_t eth_hdr_retained:1; + /* Following fields are valid if eth_hdr_retained =1 ( bridge mode) */ + uint32_t hdr_ofst_pkt_size_valid:1; + uint32_t hdr_ofst_pkt_size:6; + uint32_t hdr_endianness:1; + uint32_t reserved:15; +}; + +/** + * struct ipa_l2tp_hdr_proc_ctx_params - + * @hdr_add_param: parameters for header add + * @hdr_remove_param: parameters for header remove + * @is_dst_pipe_valid: if dst pipe is valid + * @dst_pipe: destination pipe + */ +struct ipa_l2tp_hdr_proc_ctx_params { + struct ipa_l2tp_header_add_procparams hdr_add_param; + struct ipa_l2tp_header_remove_procparams hdr_remove_param; + uint8_t is_dst_pipe_valid; + enum ipa_client_type dst_pipe; +}; + +#define IPA_EoGRE_MAX_PCP_IDX 8 /* From 802.1Q tag format (reflects IEEE P802.1p) */ +#define IPA_EoGRE_MAX_VLAN 8 /* Our supported number of VLAN id's */ + +/* vlan 12 bits + pcp 3 bites <-> dscp 6 bits */ +struct IpaDscpVlanPcpMap_t { + /* + * valid only lower 12 bits + */ + uint16_t vlan[IPA_EoGRE_MAX_VLAN]; + /* + * dscp[vlan][pcp], valid only lower 6 bits, using pcp as index + */ + uint8_t dscp[IPA_EoGRE_MAX_VLAN][IPA_EoGRE_MAX_PCP_IDX]; + uint8_t num_vlan; /* indicate how many vlans valid */ + uint8_t reserved0; +} __packed; + +struct ipa_ipgre_info { + /* ip address type */ + enum ipa_ip_type iptype; + /* ipv4 */ + uint32_t ipv4_src; + uint32_t ipv4_dst; + /* ipv6 */ + uint32_t ipv6_src[4]; + uint32_t ipv6_dst[4]; + /* gre header info */ + uint16_t gre_protocol; +}; + +struct ipa_ioc_eogre_info { + /* ip and gre info */ + struct ipa_ipgre_info ipgre_info; + /* mapping info */ + struct IpaDscpVlanPcpMap_t map_info; +}; + +/** + * struct ipa_eogre_header_add_procparams - + * @eth_hdr_retained: Specifies if Ethernet header is retained or not + * @input_ip_version: Specifies if Input header is IPV4(0) or IPV6(1) + * @output_ip_version: Specifies if template header's outer IP is IPV4(0) or IPV6(1) + * @second_pass: Specifies if the data should be processed again. + */ +struct ipa_eogre_header_add_procparams { + uint32_t eth_hdr_retained :1; + uint32_t input_ip_version :1; + uint32_t output_ip_version :1; + uint32_t second_pass :1; + uint32_t reserved :28; +}; + +/** + * struct ipa_eogre_header_remove_procparams - + * @hdr_len_remove: Specifies how much (in bytes) of the header needs + * to be removed + */ +struct ipa_eogre_header_remove_procparams { + uint32_t hdr_len_remove:8; /* 44 bytes for IPV6, 24 for IPV4 */ + uint32_t reserved:24; +}; + +/** + * struct ipa_eogre_hdr_proc_ctx_params - + * @hdr_add_param: parameters for header add + * @hdr_remove_param: parameters for header remove + */ +struct ipa_eogre_hdr_proc_ctx_params { + struct ipa_eogre_header_add_procparams hdr_add_param; + struct ipa_eogre_header_remove_procparams hdr_remove_param; +}; + +/** + * struct ipa_eth_II_to_eth_II_ex_procparams - + * @input_ethhdr_negative_offset: Specifies where the ethernet hdr offset is + * (in bytes) from the start of the input IP hdr + * @output_ethhdr_negative_offset: Specifies where the ethernet hdr offset is + * (in bytes) from the end of the template hdr + * @reserved: for future use + */ +struct ipa_eth_II_to_eth_II_ex_procparams { + uint32_t input_ethhdr_negative_offset : 8; + uint32_t output_ethhdr_negative_offset : 8; + uint32_t reserved : 16; +}; + +#define L2TP_USER_SPACE_SPECIFY_DST_PIPE + +/** + * struct ipa_hdr_proc_ctx_add - processing context descriptor includes + * in and out parameters + * @type: processing context type + * @hdr_hdl: in parameter, handle to header + * @l2tp_params: l2tp parameters + * @eogre_params: eogre parameters + * @generic_params: generic proc_ctx params + * @proc_ctx_hdl: out parameter, handle to proc_ctx, valid when status is 0 + * @status: out parameter, status of header add operation, + * 0 for success, + * -1 for failure + */ +struct ipa_hdr_proc_ctx_add { + enum ipa_hdr_proc_type type; + uint32_t hdr_hdl; + uint32_t proc_ctx_hdl; + int status; + struct ipa_l2tp_hdr_proc_ctx_params l2tp_params; + struct ipa_eogre_hdr_proc_ctx_params eogre_params; + struct ipa_eth_II_to_eth_II_ex_procparams generic_params; +}; + +#define IPA_L2TP_HDR_PROC_SUPPORT + +/** + * struct ipa_ioc_add_hdr - processing context addition parameters (support + * multiple processing context and commit) + * @commit: should processing context be written to IPA HW also? + * @num_proc_ctxs: num of processing context that follow + * @proc_ctx: all processing context need to go here back to + * back, no pointers + */ +struct ipa_ioc_add_hdr_proc_ctx { + uint8_t commit; + uint8_t num_proc_ctxs; + struct ipa_hdr_proc_ctx_add proc_ctx[0]; +}; + +/** + * struct ipa_ioc_copy_hdr - retrieve a copy of the specified + * header - caller can then derive the complete header + * @name: name of the header resource + * @hdr: out parameter, contents of specified header, + * valid only when ioctl return val is non-negative + * @hdr_len: out parameter, size of above header + * valid only when ioctl return val is non-negative + * @type: l2 header type + * valid only when ioctl return val is non-negative + * @is_partial: out parameter, indicates whether specified header is partial + * valid only when ioctl return val is non-negative + * @is_eth2_ofst_valid: is eth2_ofst field valid? + * @eth2_ofst: offset to start of Ethernet-II/802.3 header + */ +struct ipa_ioc_copy_hdr { + char name[IPA_RESOURCE_NAME_MAX]; + uint8_t hdr[IPA_HDR_MAX_SIZE]; + uint8_t hdr_len; + enum ipa_hdr_l2_type type; + uint8_t is_partial; + uint8_t is_eth2_ofst_valid; + uint16_t eth2_ofst; +}; + +/** + * struct ipa_ioc_get_hdr - header entry lookup parameters, if lookup was + * successful caller must call put to release the reference count when done + * @name: name of the header resource + * @hdl: out parameter, handle of header entry + * valid only when ioctl return val is non-negative + */ +struct ipa_ioc_get_hdr { + char name[IPA_RESOURCE_NAME_MAX]; + uint32_t hdl; +}; + +/** + * struct ipa_hdr_del - header descriptor includes in and out + * parameters + * + * @hdl: handle returned from header add operation + * @status: out parameter, status of header remove operation, + * 0 for success, + * -1 for failure + */ +struct ipa_hdr_del { + uint32_t hdl; + int status; +}; + +/** + * struct ipa_ioc_del_hdr - header deletion parameters (support + * multiple headers and commit) + * @commit: should headers be removed from IPA HW also? + * @num_hdls: num of headers being removed + * @ipa_hdr_del hdl: all handles need to go here back to back, no pointers + */ +struct ipa_ioc_del_hdr { + uint8_t commit; + uint8_t num_hdls; + struct ipa_hdr_del hdl[0]; +}; + +/** + * struct ipa_hdr_proc_ctx_del - processing context descriptor includes + * in and out parameters + * @hdl: handle returned from processing context add operation + * @status: out parameter, status of header remove operation, + * 0 for success, + * -1 for failure + */ +struct ipa_hdr_proc_ctx_del { + uint32_t hdl; + int status; +}; + +/** + * ipa_ioc_del_hdr_proc_ctx - processing context deletion parameters (support + * multiple headers and commit) + * @commit: should processing contexts be removed from IPA HW also? + * @num_hdls: num of processing contexts being removed + * @ipa_hdr_proc_ctx_del hdl: all handles need to go here back to back, + * no pointers + */ +struct ipa_ioc_del_hdr_proc_ctx { + uint8_t commit; + uint8_t num_hdls; + struct ipa_hdr_proc_ctx_del hdl[0]; +}; + +/** + * struct ipa_rt_rule_add - routing rule descriptor includes in + * and out parameters + * @rule: actual rule to be added + * @at_rear: add at back of routing table, it is NOT possible to add rules at + * the rear of the "default" routing tables + * @rt_rule_hdl: output parameter, handle to rule, valid when status is 0 + * @status: output parameter, status of routing rule add operation, + * 0 for success, + * -1 for failure + */ +struct ipa_rt_rule_add { + struct ipa_rt_rule rule; + uint8_t at_rear; + uint32_t rt_rule_hdl; + int status; +}; + +/** + * struct ipa_rt_rule_add_v2 - routing rule descriptor includes + * in and out parameters + * @rule: actual rule to be added + * @at_rear: add at back of routing table, it is NOT possible to add rules at + * the rear of the "default" routing tables + * @rt_rule_hdl: output parameter, handle to rule, valid when status is 0 + * @status: output parameter, status of routing rule add operation, + * 0 for success, + * -1 for failure + */ +struct ipa_rt_rule_add_v2 { + uint8_t at_rear; + uint32_t rt_rule_hdl; + int status; + struct ipa_rt_rule_v2 rule; +}; + + +/** + * struct ipa_ioc_add_rt_rule - routing rule addition parameters (supports + * multiple rules and commit); + * + * all rules MUST be added to same table + * @commit: should rules be written to IPA HW also? + * @ip: IP family of rule + * @rt_tbl_name: name of routing table resource + * @num_rules: number of routing rules that follow + * @ipa_rt_rule_add rules: all rules need to go back to back here, no pointers + */ +struct ipa_ioc_add_rt_rule { + uint8_t commit; + enum ipa_ip_type ip; + char rt_tbl_name[IPA_RESOURCE_NAME_MAX]; + uint8_t num_rules; + struct ipa_rt_rule_add rules[0]; +}; + +/** + * struct ipa_ioc_add_rt_rule_v2 - routing rule addition + * parameters (supports multiple rules and commit); + * + * all rules MUST be added to same table + * @commit: should rules be written to IPA HW also? + * @ip: IP family of rule + * @rt_tbl_name: name of routing table resource + * @num_rules: number of routing rules that follow + * @rule_add_size: sizeof(struct ipa_rt_rule_add_v2) + * @reserved1: reserved bits for alignment + * @reserved2: reserved bits for alignment + * @ipa_rt_rule_add rules: all rules need to go back to back here, no pointers + */ +struct ipa_ioc_add_rt_rule_v2 { + uint8_t commit; + enum ipa_ip_type ip; + char rt_tbl_name[IPA_RESOURCE_NAME_MAX]; + uint8_t num_rules; + uint32_t rule_add_size; + uint32_t reserved1; + uint8_t reserved2; + uint64_t rules; +}; + +/** + * struct ipa_ioc_add_rt_rule_after - routing rule addition after a specific + * rule parameters(supports multiple rules and commit); + * + * all rules MUST be added to same table + * @commit: should rules be written to IPA HW also? + * @ip: IP family of rule + * @rt_tbl_name: name of routing table resource + * @num_rules: number of routing rules that follow + * @add_after_hdl: the rules will be added after this specific rule + * @ipa_rt_rule_add rules: all rules need to go back to back here, no pointers + * at_rear field will be ignored when using this IOCTL + */ +struct ipa_ioc_add_rt_rule_after { + uint8_t commit; + enum ipa_ip_type ip; + char rt_tbl_name[IPA_RESOURCE_NAME_MAX]; + uint8_t num_rules; + uint32_t add_after_hdl; + struct ipa_rt_rule_add rules[0]; +}; + +/** + * struct ipa_ioc_add_rt_rule_after_v2 - routing rule addition + * after a specific rule parameters(supports multiple rules and + * commit); + * + * all rules MUST be added to same table + * @commit: should rules be written to IPA HW also? + * @ip: IP family of rule + * @rt_tbl_name: name of routing table resource + * @num_rules: number of routing rules that follow + * @add_after_hdl: the rules will be added after this specific rule + * @rule_add_size: sizeof(struct ipa_rt_rule_add_v2) + * @reserved: reserved bits for alignment + * @ipa_rt_rule_add rules: all rules need to go back to back here, no pointers + * at_rear field will be ignored when using this IOCTL + */ +struct ipa_ioc_add_rt_rule_after_v2 { + uint8_t commit; + enum ipa_ip_type ip; + char rt_tbl_name[IPA_RESOURCE_NAME_MAX]; + uint8_t num_rules; + uint32_t add_after_hdl; + uint32_t rule_add_size; + uint8_t reserved; + uint64_t rules; +}; + +/** + * struct ipa_rt_rule_mdfy - routing rule descriptor includes + * in and out parameters + * @rule: actual rule to be added + * @rt_rule_hdl: handle to rule which supposed to modify + * @status: output parameter, status of routing rule modify operation, + * 0 for success, + * -1 for failure + * + */ +struct ipa_rt_rule_mdfy { + struct ipa_rt_rule rule; + uint32_t rt_rule_hdl; + int status; +}; + +/** + * struct ipa_rt_rule_mdfy_v2 - routing rule descriptor includes + * in and out parameters + * @rule: actual rule to be added + * @rt_rule_hdl: handle to rule which supposed to modify + * @status: output parameter, status of routing rule modify operation, + * 0 for success, + * -1 for failure + * + */ +struct ipa_rt_rule_mdfy_v2 { + uint32_t rt_rule_hdl; + int status; + struct ipa_rt_rule_v2 rule; +}; + +/** + * struct ipa_ioc_mdfy_rt_rule - routing rule modify parameters (supports + * multiple rules and commit) + * @commit: should rules be written to IPA HW also? + * @ip: IP family of rule + * @num_rules: number of routing rules that follow + * @rules: all rules need to go back to back here, no pointers + */ +struct ipa_ioc_mdfy_rt_rule { + uint8_t commit; + enum ipa_ip_type ip; + uint8_t num_rules; + struct ipa_rt_rule_mdfy rules[0]; +}; + +/** + * struct ipa_ioc_mdfy_rt_rule_v2 - routing rule modify + * parameters (supports multiple rules and commit) + * @commit: should rules be written to IPA HW also? + * @ip: IP family of rule + * @num_rules: number of routing rules that follow + * @rule_mdfy_size: sizeof(struct ipa_rt_rule_mdfy_v2) + * @reserved: reserved bits for alignment + * @rules: all rules need to go back to back here, no pointers + */ +struct ipa_ioc_mdfy_rt_rule_v2 { + uint8_t commit; + enum ipa_ip_type ip; + uint8_t num_rules; + uint32_t rule_mdfy_size; + uint8_t reserved; + uint64_t rules; +}; + +/** + * struct ipa_rt_rule_del - routing rule descriptor includes in + * and out parameters + * @hdl: handle returned from route rule add operation + * @status: output parameter, status of route rule delete operation, + * 0 for success, + * -1 for failure + */ +struct ipa_rt_rule_del { + uint32_t hdl; + int status; +}; + +/** + * struct ipa_rt_rule_add_ext - routing rule descriptor includes in + * and out parameters + * @rule: actual rule to be added + * @at_rear: add at back of routing table, it is NOT possible to add rules at + * the rear of the "default" routing tables + * @rt_rule_hdl: output parameter, handle to rule, valid when status is 0 + * @status: output parameter, status of routing rule add operation, + * @rule_id: rule_id to be assigned to the routing rule. In case client + * specifies rule_id as 0 the driver will assign a new rule_id + * 0 for success, + * -1 for failure + */ +struct ipa_rt_rule_add_ext { + struct ipa_rt_rule rule; + uint8_t at_rear; + uint32_t rt_rule_hdl; + int status; + uint16_t rule_id; +}; + +/** + * struct ipa_rt_rule_add_ext_v2 - routing rule descriptor + * includes in and out parameters + * @rule: actual rule to be added + * @at_rear: add at back of routing table, it is NOT possible to add rules at + * the rear of the "default" routing tables + * @rt_rule_hdl: output parameter, handle to rule, valid when status is 0 + * @status: output parameter, status of routing rule add operation, + * @rule_id: rule_id to be assigned to the routing rule. In case client + * specifies rule_id as 0 the driver will assign a new rule_id + * 0 for success, + * -1 for failure + */ +struct ipa_rt_rule_add_ext_v2 { + uint8_t at_rear; + uint32_t rt_rule_hdl; + int status; + uint16_t rule_id; + struct ipa_rt_rule_v2 rule; +}; + +/** + * struct ipa_ioc_add_rt_rule_ext - routing rule addition + * parameters (supports multiple rules and commit with rule_id); + * + * all rules MUST be added to same table + * @commit: should rules be written to IPA HW also? + * @ip: IP family of rule + * @rt_tbl_name: name of routing table resource + * @num_rules: number of routing rules that follow + * @ipa_rt_rule_add_ext rules: all rules need to go back to back here, + * no pointers + */ +struct ipa_ioc_add_rt_rule_ext { + uint8_t commit; + enum ipa_ip_type ip; + char rt_tbl_name[IPA_RESOURCE_NAME_MAX]; + uint8_t num_rules; + struct ipa_rt_rule_add_ext rules[0]; +}; + +/** + * struct ipa_ioc_add_rt_rule_ext_v2 - routing rule addition + * parameters (supports multiple rules and commit with rule_id); + * + * all rules MUST be added to same table + * @commit: should rules be written to IPA HW also? + * @ip: IP family of rule + * @rt_tbl_name: name of routing table resource + * @num_rules: number of routing rules that follow + * @rule_add_ext_size: sizeof(struct ipa_rt_rule_add_ext_v2) + * @reserved1: reserved bits for alignment + * @reserved2: reserved bits for alignment + * @ipa_rt_rule_add_ext rules: all rules need to go back to back here, + * no pointers + */ +struct ipa_ioc_add_rt_rule_ext_v2 { + uint8_t commit; + enum ipa_ip_type ip; + char rt_tbl_name[IPA_RESOURCE_NAME_MAX]; + uint8_t num_rules; + uint32_t rule_add_ext_size; + uint32_t reserved1; + uint8_t reserved2; + uint64_t rules; +}; + + +/** + * struct ipa_ioc_del_rt_rule - routing rule deletion parameters (supports + * multiple headers and commit) + * @commit: should rules be removed from IPA HW also? + * @ip: IP family of rules + * @num_hdls: num of rules being removed + * @ipa_rt_rule_del hdl: all handles need to go back to back here, no pointers + */ +struct ipa_ioc_del_rt_rule { + uint8_t commit; + enum ipa_ip_type ip; + uint8_t num_hdls; + struct ipa_rt_rule_del hdl[0]; +}; + +/** + * struct ipa_ioc_get_rt_tbl_indx - routing table index lookup parameters + * @ip: IP family of table + * @name: name of routing table resource + * @index: output parameter, routing table index, valid only when ioctl + * return val is non-negative + */ +struct ipa_ioc_get_rt_tbl_indx { + enum ipa_ip_type ip; + char name[IPA_RESOURCE_NAME_MAX]; + uint32_t idx; +}; + +/** + * struct ipa_flt_rule_add - filtering rule descriptor includes + * in and out parameters + * @rule: actual rule to be added + * @at_rear: add at back of filtering table? + * @flt_rule_hdl: out parameter, handle to rule, valid when status is 0 + * @status: output parameter, status of filtering rule add operation, + * 0 for success, + * -1 for failure + * + */ +struct ipa_flt_rule_add { + struct ipa_flt_rule rule; + uint8_t at_rear; + uint32_t flt_rule_hdl; + int status; +}; + +/** + * struct ipa_flt_rule_add_v2 - filtering rule descriptor + * includes in and out parameters + * @rule: actual rule to be added + * @at_rear: add at back of filtering table? + * @flt_rule_hdl: out parameter, handle to rule, valid when status is 0 + * @status: output parameter, status of filtering rule add operation, + * 0 for success, + * -1 for failure + * + */ +struct ipa_flt_rule_add_v2 { + uint8_t at_rear; + uint32_t flt_rule_hdl; + int status; + struct ipa_flt_rule_v2 rule; +}; + +/** + * struct ipa_ioc_add_flt_rule - filtering rule addition parameters (supports + * multiple rules and commit) + * all rules MUST be added to same table + * @commit: should rules be written to IPA HW also? + * @ip: IP family of rule + * @ep: which "clients" pipe does this rule apply to? + * valid only when global is 0 + * @global: does this apply to global filter table of specific IP family + * @num_rules: number of filtering rules that follow + * @rules: all rules need to go back to back here, no pointers + */ +struct ipa_ioc_add_flt_rule { + uint8_t commit; + enum ipa_ip_type ip; + enum ipa_client_type ep; + uint8_t global; + uint8_t num_rules; + struct ipa_flt_rule_add rules[0]; +}; + +/** + * struct ipa_ioc_add_flt_rule_v2 - filtering rule addition + * parameters (supports multiple rules and commit) + * all rules MUST be added to same table + * @commit: should rules be written to IPA HW also? + * @ip: IP family of rule + * @ep: which "clients" pipe does this rule apply to? + * valid only when global is 0 + * @global: does this apply to global filter table of specific IP family + * @num_rules: number of filtering rules that follow + * @flt_rule_size: sizeof(struct ipa_flt_rule_add_v2) + * @reserved1: reserved bits for alignment + * @reserved2: reserved bits for alignment + * @reserved3: reserved bits for alignment + * @rules: all rules need to go back to back here, no pointers + */ +struct ipa_ioc_add_flt_rule_v2 { + uint8_t commit; + enum ipa_ip_type ip; + enum ipa_client_type ep; + uint8_t global; + uint8_t num_rules; + uint32_t flt_rule_size; + uint32_t reserved1; + uint16_t reserved2; + uint8_t reserved3; + uint64_t rules; +}; + + +/** + * struct ipa_ioc_add_flt_rule_after - filtering rule addition after specific + * rule parameters (supports multiple rules and commit) + * all rules MUST be added to same table + * @commit: should rules be written to IPA HW also? + * @ip: IP family of rule + * @ep: which "clients" pipe does this rule apply to? + * @num_rules: number of filtering rules that follow + * @add_after_hdl: rules will be added after the rule with this handle + * @rules: all rules need to go back to back here, no pointers. at rear field + * is ignored when using this IOCTL + */ +struct ipa_ioc_add_flt_rule_after { + uint8_t commit; + enum ipa_ip_type ip; + enum ipa_client_type ep; + uint8_t num_rules; + uint32_t add_after_hdl; + struct ipa_flt_rule_add rules[0]; +}; + +/** + * struct ipa_ioc_add_flt_rule_after_v2 - filtering rule + * addition after specific rule parameters (supports multiple + * rules and commit) all rules MUST be added to same table + * @commit: should rules be written to IPA HW also? + * @ip: IP family of rule + * @ep: which "clients" pipe does this rule apply to? + * @num_rules: number of filtering rules that follow + * @add_after_hdl: rules will be added after the rule with this handle + * @flt_rule_size: sizeof(struct ipa_flt_rule_add_v2) + * @reserved: reserved bits for alignment + * @rules: all rules need to go back to back here, no pointers. at rear field + * is ignored when using this IOCTL + */ +struct ipa_ioc_add_flt_rule_after_v2 { + uint8_t commit; + enum ipa_ip_type ip; + enum ipa_client_type ep; + uint8_t num_rules; + uint32_t add_after_hdl; + uint32_t flt_rule_size; + uint32_t reserved; + uint64_t rules; +}; + +/** + * struct ipa_flt_rule_mdfy - filtering rule descriptor includes + * in and out parameters + * @rule: actual rule to be added + * @flt_rule_hdl: handle to rule + * @status: output parameter, status of filtering rule modify operation, + * 0 for success, + * -1 for failure + * + */ +struct ipa_flt_rule_mdfy { + struct ipa_flt_rule rule; + uint32_t rule_hdl; + int status; +}; + +/** + * struct ipa_flt_rule_mdfy_v2 - filtering rule descriptor + * includes in and out parameters + * @rule: actual rule to be added + * @flt_rule_hdl: handle to rule + * @status: output parameter, status of filtering rule modify operation, + * 0 for success, + * -1 for failure + * + */ +struct ipa_flt_rule_mdfy_v2 { + uint32_t rule_hdl; + int status; + struct ipa_flt_rule_v2 rule; +}; + +/** + * struct ipa_ioc_mdfy_flt_rule - filtering rule modify parameters (supports + * multiple rules and commit) + * @commit: should rules be written to IPA HW also? + * @ip: IP family of rule + * @num_rules: number of filtering rules that follow + * @rules: all rules need to go back to back here, no pointers + */ +struct ipa_ioc_mdfy_flt_rule { + uint8_t commit; + enum ipa_ip_type ip; + uint8_t num_rules; + struct ipa_flt_rule_mdfy rules[0]; +}; + +/** + * struct ipa_ioc_mdfy_flt_rule_v2 - filtering rule modify + * parameters (supports multiple rules and commit) + * @commit: should rules be written to IPA HW also? + * @ip: IP family of rule + * @num_rules: number of filtering rules that follow + * @rule_mdfy_size: sizeof(struct ipa_flt_rule_mdfy_v2) + * @reserved: reserved bits for alignment + * @rules: all rules need to go back to back here, no pointers + */ +struct ipa_ioc_mdfy_flt_rule_v2 { + uint8_t commit; + enum ipa_ip_type ip; + uint8_t num_rules; + uint32_t rule_mdfy_size; + uint8_t reserved; + uint64_t rules; +}; + +/** + * struct ipa_flt_rule_del - filtering rule descriptor includes + * in and out parameters + * + * @hdl: handle returned from filtering rule add operation + * @status: output parameter, status of filtering rule delete operation, + * 0 for success, + * -1 for failure + */ +struct ipa_flt_rule_del { + uint32_t hdl; + int status; +}; + +/** + * struct ipa_ioc_del_flt_rule - filtering rule deletion parameters (supports + * multiple headers and commit) + * @commit: should rules be removed from IPA HW also? + * @ip: IP family of rules + * @num_hdls: num of rules being removed + * @hdl: all handles need to go back to back here, no pointers + */ +struct ipa_ioc_del_flt_rule { + uint8_t commit; + enum ipa_ip_type ip; + uint8_t num_hdls; + struct ipa_flt_rule_del hdl[0]; +}; + +/** + * struct ipa_ioc_get_rt_tbl - routing table lookup parameters, if lookup was + * successful caller must call put to release the reference + * count when done + * @ip: IP family of table + * @name: name of routing table resource + * @htl: output parameter, handle of routing table, valid only when ioctl + * return val is non-negative + */ +struct ipa_ioc_get_rt_tbl { + enum ipa_ip_type ip; + char name[IPA_RESOURCE_NAME_MAX]; + uint32_t hdl; +}; + +/** + * struct ipa_ioc_query_intf - used to lookup number of tx and + * rx properties of interface + * @name: name of interface + * @num_tx_props: output parameter, number of tx properties + * valid only when ioctl return val is non-negative + * @num_rx_props: output parameter, number of rx properties + * valid only when ioctl return val is non-negative + * @num_ext_props: output parameter, number of ext properties + * valid only when ioctl return val is non-negative + * @excp_pipe: exception packets of this interface should be + * routed to this pipe + */ +struct ipa_ioc_query_intf { + char name[IPA_RESOURCE_NAME_MAX]; + uint32_t num_tx_props; + uint32_t num_rx_props; + uint32_t num_ext_props; + enum ipa_client_type excp_pipe; +}; + +/** + * struct ipa_ioc_tx_intf_prop - interface tx property + * @ip: IP family of routing rule + * @attrib: routing rule + * @dst_pipe: routing output pipe + * @alt_dst_pipe: alternate routing output pipe + * @hdr_name: name of associated header if any, empty string when no header + * @hdr_l2_type: type of associated header if any, use NONE when no header + */ +struct ipa_ioc_tx_intf_prop { + enum ipa_ip_type ip; + struct ipa_rule_attrib attrib; + enum ipa_client_type dst_pipe; + enum ipa_client_type alt_dst_pipe; + char hdr_name[IPA_RESOURCE_NAME_MAX]; + enum ipa_hdr_l2_type hdr_l2_type; +}; + +/** + * struct ipa_ioc_query_intf_tx_props - interface tx propertie + * @name: name of interface + * @num_tx_props: number of TX properties + * @tx[0]: output parameter, the tx properties go here back to back + */ +struct ipa_ioc_query_intf_tx_props { + char name[IPA_RESOURCE_NAME_MAX]; + uint32_t num_tx_props; + struct ipa_ioc_tx_intf_prop tx[0]; +}; + +/** + * struct ipa_ioc_ext_intf_prop - interface extended property + * @ip: IP family of routing rule + * @eq_attrib: attributes of the rule in equation form + * @action: action field + * @rt_tbl_idx: index of RT table referred to by filter rule + * @mux_id: MUX_ID + * @filter_hdl: handle of filter (as specified by provider of filter rule) + * @is_xlat_rule: it is xlat flt rule or not + */ +struct ipa_ioc_ext_intf_prop { + enum ipa_ip_type ip; + struct ipa_ipfltri_rule_eq eq_attrib; + enum ipa_flt_action action; + uint32_t rt_tbl_idx; + uint8_t mux_id; + uint32_t filter_hdl; + uint8_t is_xlat_rule; + uint32_t rule_id; + uint8_t is_rule_hashable; +#define IPA_V6_UL_WL_FIREWALL_HANDLE + uint8_t replicate_needed; +}; + +/** + * struct ipa_ioc_query_intf_ext_props - interface ext propertie + * @name: name of interface + * @num_ext_props: number of EXT properties + * @ext[0]: output parameter, the ext properties go here back to back + */ +struct ipa_ioc_query_intf_ext_props { + char name[IPA_RESOURCE_NAME_MAX]; + uint32_t num_ext_props; + struct ipa_ioc_ext_intf_prop ext[0]; +}; + +/** + * struct ipa_ioc_rx_intf_prop - interface rx property + * @ip: IP family of filtering rule + * @attrib: filtering rule + * @src_pipe: input pipe + * @hdr_l2_type: type of associated header if any, use NONE when no header + */ +struct ipa_ioc_rx_intf_prop { + enum ipa_ip_type ip; + struct ipa_rule_attrib attrib; + enum ipa_client_type src_pipe; + enum ipa_hdr_l2_type hdr_l2_type; +}; + +/** + * struct ipa_ioc_query_intf_rx_props - interface rx propertie + * @name: name of interface + * @num_rx_props: number of RX properties + * @rx: output parameter, the rx properties go here back to back + */ +struct ipa_ioc_query_intf_rx_props { + char name[IPA_RESOURCE_NAME_MAX]; + uint32_t num_rx_props; + struct ipa_ioc_rx_intf_prop rx[0]; +}; + +/** + * struct ipa_ioc_nat_alloc_mem - nat table memory allocation + * properties + * @dev_name: input parameter, the name of table + * @size: input parameter, size of table in bytes + * @offset: output parameter, offset into page in case of system memory + */ +struct ipa_ioc_nat_alloc_mem { + char dev_name[IPA_RESOURCE_NAME_MAX]; + size_t size; + __kernel_off_t offset; +}; + +/** + * struct ipa_ioc_nat_ipv6ct_table_alloc - NAT/IPv6CT table memory allocation + * properties + * @size: input parameter, size of table in bytes + * @offset: output parameter, offset into page in case of system memory + */ +struct ipa_ioc_nat_ipv6ct_table_alloc { + size_t size; + __kernel_off_t offset; +}; + +/** + * struct ipa_ioc_v4_nat_init - nat table initialization parameters + * @tbl_index: input parameter, index of the table + * @ipv4_rules_offset: input parameter, ipv4 rules address offset + * @expn_rules_offset: input parameter, ipv4 expansion rules address offset + * @index_offset: input parameter, index rules offset + * @index_expn_offset: input parameter, index expansion rules offset + * @table_entries: input parameter, ipv4 rules table number of entries + * @expn_table_entries: input parameter, ipv4 expansion rules table number of + * entries + * @ip_addr: input parameter, public ip address + * @mem_type: input parameter, type of memory the table resides in + * @focus_change: input parameter, are we moving to/from sram or ddr + */ +struct ipa_ioc_v4_nat_init { + uint8_t tbl_index; + uint32_t ipv4_rules_offset; + uint32_t expn_rules_offset; + + uint32_t index_offset; + uint32_t index_expn_offset; + + uint16_t table_entries; + uint16_t expn_table_entries; + uint32_t ip_addr; + + uint8_t mem_type; + uint8_t focus_change; +}; + +/** + * struct ipa_ioc_ipv6ct_init - IPv6CT table initialization parameters + * @base_table_offset: input parameter, IPv6CT base table address offset + * @expn_table_offset: input parameter, IPv6CT expansion table address offset + * @table_entries: input parameter, IPv6CT table number of entries + * @expn_table_entries: input parameter, IPv6CT expansion table number of + * entries + * @tbl_index: input parameter, index of the table + */ +struct ipa_ioc_ipv6ct_init { + uint32_t base_table_offset; + uint32_t expn_table_offset; + uint16_t table_entries; + uint16_t expn_table_entries; + uint8_t tbl_index; +}; + +/** + * struct ipa_ioc_v4_nat_del - nat table delete parameter + * @table_index: input parameter, index of the table + * @public_ip_addr: input parameter, public ip address + */ +struct ipa_ioc_v4_nat_del { + uint8_t table_index; + uint32_t public_ip_addr; +}; + +/** + * struct ipa_ioc_nat_ipv6ct_table_del - NAT/IPv6CT table delete parameter + * @table_index: input parameter, index of the table + * @mem_type: input parameter, type of memory the table resides in + */ +struct ipa_ioc_nat_ipv6ct_table_del { + uint8_t table_index; + uint8_t mem_type; +}; + +/** + * struct ipa_ioc_nat_dma_one - nat/ipv6ct dma command parameter + * @table_index: input parameter, index of the table + * @base_addr: type of table, from which the base address of the table + * can be inferred + * @offset: destination offset within the NAT table + * @data: data to be written. + */ +struct ipa_ioc_nat_dma_one { + uint8_t table_index; + uint8_t base_addr; + + uint32_t offset; + uint16_t data; + +}; + +/** + * struct ipa_ioc_nat_dma_cmd - To hold multiple nat/ipv6ct dma commands + * @entries: number of dma commands in use + * @dma: data pointer to the dma commands + * @mem_type: input parameter, type of memory the table resides in + */ +struct ipa_ioc_nat_dma_cmd { + uint8_t entries; + uint8_t mem_type; + struct ipa_ioc_nat_dma_one dma[0]; +}; + +/** + * struct ipa_ioc_nat_pdn_entry - PDN entry modification data + * @pdn_index: index of the entry in the PDN config table to be changed + * @public_ip: PDN's public ip + * @src_metadata: PDN's source NAT metadata for metadata replacement + * @dst_metadata: PDN's destination NAT metadata for metadata replacement + */ +struct ipa_ioc_nat_pdn_entry { + uint8_t pdn_index; + uint32_t public_ip; + uint32_t src_metadata; + uint32_t dst_metadata; +}; + +/** + * struct ipa_ioc_vlan_iface_info - add vlan interface + * @name: interface name + * @vlan_id: VLAN ID + */ +struct ipa_ioc_vlan_iface_info { + char name[IPA_RESOURCE_NAME_MAX]; + uint8_t vlan_id; +}; + +/** + * enum ipa_l2tp_tunnel_type - IP or UDP + */ +enum ipa_l2tp_tunnel_type { + IPA_L2TP_TUNNEL_IP = 1, + IPA_L2TP_TUNNEL_UDP = 2 +#define IPA_L2TP_TUNNEL_UDP IPA_L2TP_TUNNEL_UDP +}; + +/** + * struct ipa_ioc_l2tp_vlan_mapping_info - l2tp->vlan mapping info + * @iptype: l2tp tunnel IP type + * @l2tp_iface_name: l2tp interface name + * @l2tp_session_id: l2tp session id + * @vlan_iface_name: vlan interface name + * @tunnel_type: l2tp tunnel type + * @src_port: UDP source port + * @dst_port: UDP destination port + * @mtu: MTU of the L2TP interface + */ +struct ipa_ioc_l2tp_vlan_mapping_info { + enum ipa_ip_type iptype; + char l2tp_iface_name[IPA_RESOURCE_NAME_MAX]; + uint8_t l2tp_session_id; + char vlan_iface_name[IPA_RESOURCE_NAME_MAX]; + enum ipa_l2tp_tunnel_type tunnel_type; + __u16 src_port; + __u16 dst_port; + __u16 mtu; + __u8 padding; +}; + +/** + * struct ipa_ioc_gsb_info - connect/disconnect + * @name: interface name + */ +struct ipa_ioc_gsb_info { + char name[IPA_RESOURCE_NAME_MAX]; +}; + +#define QUERY_MAX_EP_PAIRS 2 + +#define IPA_USB0_EP_ID 11 +#define IPA_USB1_EP_ID 12 + +#define IPA_PCIE0_EP_ID 21 +#define IPA_PCIE1_EP_ID 22 + +#define IPA_ETH0_EP_ID 31 +#define IPA_ETH1_EP_ID 32 + +enum ipa_peripheral_ep_type { + IPA_DATA_EP_TYP_RESERVED = 0, + IPA_DATA_EP_TYP_HSIC = 1, + IPA_DATA_EP_TYP_HSUSB = 2, + IPA_DATA_EP_TYP_PCIE = 3, + IPA_DATA_EP_TYP_EMBEDDED = 4, + IPA_DATA_EP_TYP_BAM_DMUX = 5, + IPA_DATA_EP_TYP_ETH, +}; + +enum ipa_data_ep_prot_type { + IPA_PROT_RMNET = 0, + IPA_PROT_RMNET_CV2X = 1, + IPA_PROT_MAX +}; + +struct ipa_ep_pair_info { + __u32 consumer_pipe_num; + __u32 producer_pipe_num; + __u32 ep_id; + __u32 padding; +}; + +/** + * struct ipa_ioc_get_ep_info - query usb/pcie ep info + * @ep_type: type USB/PCIE - i/p param + * @max_ep_pairs: max number of ep_pairs (constant), + (QUERY_MAX_EP_PAIRS) + * @num_ep_pairs: number of ep_pairs - o/p param + * @ep_pair_size: sizeof(ipa_ep_pair_info) * max_ep_pairs + * @info: structure contains ep pair info + * @teth_prot : RMNET/CV2X --i/p param + * @teth_prot_valid - validity of i/p param protocol + */ +struct ipa_ioc_get_ep_info { + enum ipa_peripheral_ep_type ep_type; + __u32 ep_pair_size; + __u8 max_ep_pairs; + __u8 num_ep_pairs; + __u16 padding; + __u64 info; + enum ipa_data_ep_prot_type teth_prot; + __u8 teth_prot_valid; +}; + +/** + * struct ipa_set_pkt_threshold + * @pkt_threshold_enable: indicate pkt_thr enable or not + * @pkt_threshold: if pkt_threshold_enable = true, given the values + */ +struct ipa_set_pkt_threshold { + uint8_t pkt_threshold_enable; + int pkt_threshold; +}; + +/** + * struct ipa_ioc_set_pkt_threshold + * @ioctl_ptr: has to be typecasted to (__u64)(uintptr_t) + * @ioctl_data_size: + * Eg: For ipa_set_pkt_threshold = sizeof(ipa_set_pkt_threshold) + */ +struct ipa_ioc_set_pkt_threshold { + __u64 ioctl_ptr; + __u32 ioctl_data_size; + __u32 padding; +}; + +/** + * struct ipa_ioc_wigig_fst_switch - switch between wigig and wlan + * @netdev_name: wigig interface name + * @client_mac_addr: client to switch between netdevs + * @to_wigig: shall wlan client switch to wigig or the opposite? + */ +struct ipa_ioc_wigig_fst_switch { + uint8_t netdev_name[IPA_RESOURCE_NAME_MAX]; + uint8_t client_mac_addr[IPA_MAC_ADDR_SIZE]; + int to_wigig; +}; + +/** + * struct ipa_msg_meta - Format of the message metadata. + * @msg_type: the type of the message + * @rsvd: reserved bits for future use. + * @msg_len: the length of the message in bytes + * + * For push model: + * Client in user-space should issue a read on the device (/dev/ipa) with a + * sufficiently large buffer in a continuous loop, call will block when there is + * no message to read. Upon return, client can read the ipa_msg_meta from start + * of buffer to find out type and length of message + * size of buffer supplied >= (size of largest message + size of metadata) + * + * For pull model: + * Client in user-space can also issue a pull msg IOCTL to device (/dev/ipa) + * with a payload containing space for the ipa_msg_meta and the message specific + * payload length. + * size of buffer supplied == (len of specific message + size of metadata) + */ +struct ipa_msg_meta { + uint8_t msg_type; + uint8_t rsvd; + uint16_t msg_len; +}; + +/** + * struct ipa_wlan_msg - To hold information about wlan client + * @name: name of the wlan interface + * @mac_addr: mac address of wlan client + * @if_index: netdev interface index + * + * wlan drivers need to pass name of wlan iface and mac address of + * wlan client along with ipa_wlan_event, whenever a wlan client is + * connected/disconnected/moved to power save/come out of power save + */ +struct ipa_wlan_msg { + char name[IPA_RESOURCE_NAME_MAX]; + uint8_t mac_addr[IPA_MAC_ADDR_SIZE]; + int16_t if_index; +}; + +/** + * enum ipa_wlan_hdr_attrib_type - attribute type + * in wlan client header + * + * WLAN_HDR_ATTRIB_MAC_ADDR: attrib type mac address + * WLAN_HDR_ATTRIB_STA_ID: attrib type station id + */ +enum ipa_wlan_hdr_attrib_type { + WLAN_HDR_ATTRIB_MAC_ADDR, + WLAN_HDR_ATTRIB_STA_ID +}; + +/** + * struct ipa_wlan_hdr_attrib_val - header attribute value + * @attrib_type: type of attribute + * @offset: offset of attribute within header + * @u.mac_addr: mac address + * @u.sta_id: station id + */ +struct ipa_wlan_hdr_attrib_val { + enum ipa_wlan_hdr_attrib_type attrib_type; + uint8_t offset; + union { + uint8_t mac_addr[IPA_MAC_ADDR_SIZE]; + uint8_t sta_id; + } u; +}; + +/** + * struct ipa_wlan_msg_ex - To hold information about wlan client + * @name: name of the wlan interface + * @num_of_attribs: number of attributes + * @attrib_val: holds attribute values + * + * wlan drivers need to pass name of wlan iface and mac address + * of wlan client or station id along with ipa_wlan_event, + * whenever a wlan client is connected/disconnected/moved to + * power save/come out of power save + */ +struct ipa_wlan_msg_ex { + char name[IPA_RESOURCE_NAME_MAX]; + uint8_t num_of_attribs; + struct ipa_wlan_hdr_attrib_val attribs[0]; +}; + +/** + * struct ipa_wigig_msg- To hold information about wigig event + * @name: name of the wigig interface + * @client_mac_addr: the relevant wigig client mac address + * @ipa_client: TX pipe associated with the wigig client in case of connect + * @to_wigig: FST switch direction wlan->wigig? + */ +struct ipa_wigig_msg { + char name[IPA_RESOURCE_NAME_MAX]; + uint8_t client_mac_addr[IPA_MAC_ADDR_SIZE]; + union { + enum ipa_client_type ipa_client; + uint8_t to_wigig; + } u; +}; + +struct ipa_ecm_msg { + char name[IPA_RESOURCE_NAME_MAX]; + int ifindex; +}; + +/** + * struct ipa_wan_msg - To hold information about wan client + * @name: name of the wan interface + * + * CnE need to pass the name of default wan iface when connected/disconnected. + * CNE need to pass the gw info in wlan AP+STA mode. + * netmgr need to pass the name of wan eMBMS iface when connected. + */ +struct ipa_wan_msg { + char upstream_ifname[IPA_RESOURCE_NAME_MAX]; + char tethered_ifname[IPA_RESOURCE_NAME_MAX]; + enum ipa_ip_type ip; + uint32_t ipv4_addr_gw; + uint32_t ipv6_addr_gw[IPA_WAN_MSG_IPv6_ADDR_GW_LEN]; +}; + +/* uc activation command Ids */ +#define IPA_SOCKSV5_ADD_COM_ID 15 +#define IPA_IPv6_NAT_COM_ID 16 + +/** + * ipa_kernel_tests_socksv5_uc_tmpl - uc activation entry info + * @cmd_id: uc command id + * @cmd_param: uC command param + * @ipa_kernel_tests_ip_hdr_temp: ip header + * @src_port: source port + * @dst_port: destination port + * @ipa_sockv5_mask: uc attribute mask for options/etc + * @out_irs: 4B/4B Seq/Ack/SACK + * @out_iss + * @in_irs + * @in_iss + * @out_ircv_tsval: timestamp attributes + * @in_ircv_tsecr + * @out_ircv_tsecr + * @in_ircv_tsval + * @in_isnd_wscale: window scale attributes + * @out_isnd_wscale + * @in_ircv_wscale + * @out_ircv_wscale + * @direction: 1 for UL 0 for DL + * @handle: uc activation table index + */ +struct ipa_kernel_tests_socksv5_uc_tmpl { + /* direction 1 = UL, 0 = DL */ + __u8 direction; + __u8 padding1; + /* output: handle (index) */ + __u16 handle; + __u16 cmd_id; + __u16 padding2; + __u32 cmd_param; + + __be32 ip_src_addr; + __be32 ip_dst_addr; + __be32 ipv6_src_addr[4]; + __be32 ipv6_dst_addr[4]; + + /* 2B src/dst port */ + __u16 src_port; + __u16 dst_port; + + /* attribute mask */ + __u32 ipa_sockv5_mask; + + /* required update 4B/4B Seq/Ack/SACK */ + __u32 out_irs; + __u32 out_iss; + __u32 in_irs; + __u32 in_iss; + + /* option 10B: time-stamp */ + __u32 out_ircv_tsval; + __u32 in_ircv_tsecr; + __u32 out_ircv_tsecr; + __u32 in_ircv_tsval; + + /* option 2B: window-scaling/dynamic */ + __u16 in_isnd_wscale : 4; + __u16 out_isnd_wscale : 4; + __u16 in_ircv_wscale : 4; + __u16 out_ircv_wscale : 4; + __u32 padding3; + +}; + +/** + * struct ipacm_socksv5_info - To hold information about socksv5 connections + * @ip_type: ip type + * @ipv4_src: ipv4 src address + * @ipv4_dst: ipv4 dst address + * @ipv6_src: ipv6 src address + * @ipv6_dst: ipv6 dst address + * @src_port: src port number + * @dst_port: dst port number + * @index: the uc activation tbl index + */ + +struct ipacm_socksv5_info { + /* ip-type */ + enum ipa_ip_type ip_type; + + /* ipv4 */ + __u32 ipv4_src; + __u32 ipv4_dst; + + /* ipv6 */ + __u32 ipv6_src[4]; + __u32 ipv6_dst[4]; + + /* 2B src/dst port */ + __u16 src_port; + __u16 dst_port; + + /* uc-tbl index */ + __u16 index; + __u16 padding; +}; + +/** + * struct ipa_socksv5_msg - To hold information about socksv5 client + * @ul_in: uplink connection info + * @dl_in: downlink connection info + * @handle: used for ipacm to distinguish connections + * + * CnE need to pass the name of default wan iface when connected/disconnected. + * CNE need to pass the gw info in wlan AP+STA mode. + * netmgr need to pass the name of wan eMBMS iface when connected. + */ +struct ipa_socksv5_msg { + struct ipacm_socksv5_info ul_in; + struct ipacm_socksv5_info dl_in; + + /* handle (index) */ + __u16 handle; + __u16 padding; +}; + +/** + * struct ipa_ioc_ipv6_nat_uc_act_entry - To hold information about IPv6 NAT + * uC entry + * @cmd_id[in]: IPv6 NAT uC CMD ID - used for identifying uc activation type + * @private_address_lsb[in]: client private address lsb + * @private_address_msb[in]: client private address msbst + * @public_address_lsb[in]: client public address lsb + * @public_address_msb[in]: client public address msb + * @private_port[in]: client private port + * @public_port[in]: client public port + * @index[out]: uC activation entry index + */ +struct ipa_ioc_ipv6_nat_uc_act_entry { + __u16 cmd_id; + __u16 index; + __u32 padding; + __u32 private_port; + __u32 public_port; + __u64 private_address_lsb; + __u64 private_address_msb; + __u64 public_address_lsb; + __u64 public_address_msb; +}; + +/** + * union ipa_ioc_uc_activation_entry - To hold information about uC activation + * entry + * @socks[in]: fill here if entry is Socksv5 entry + * @ipv6_nat[in]: fill here if entry is IPv6 NAT entry + */ +union ipa_ioc_uc_activation_entry { + struct ipa_kernel_tests_socksv5_uc_tmpl socks; + struct ipa_ioc_ipv6_nat_uc_act_entry ipv6_nat; +}; + +/** + * struct ipa_ioc_rm_dependency - parameters for add/delete dependency + * @resource_name: name of dependent resource + * @depends_on_name: name of its dependency + */ +struct ipa_ioc_rm_dependency { + enum ipa_rm_resource_name resource_name; + enum ipa_rm_resource_name depends_on_name; +}; + +struct ipa_ioc_generate_flt_eq { + enum ipa_ip_type ip; + struct ipa_rule_attrib attrib; + struct ipa_ipfltri_rule_eq eq_attrib; +}; + +/** + * struct ipa_ioc_write_qmapid - to write mux id to endpoint metadata register + * @mux_id: mux id of wan + */ +struct ipa_ioc_write_qmapid { + enum ipa_client_type client; + uint8_t qmap_id; +}; + +/** + * struct ipa_flt_rt_counter_alloc - flt/rt counter id allocation + * @num_counters: input param, num of counters need to be allocated + * @allow_less: input param, if true, success even few counter than request + * @start_id: output param, allocated start_id, 0 when allocation fails + * @end_id: output param, allocated start_id, 0 when allocation fails + */ +struct ipa_flt_rt_counter_alloc { + uint8_t num_counters; + uint8_t allow_less; + uint8_t start_id; + uint8_t end_id; +}; + +/** + * struct ipa_ioc_flt_rt_counter_alloc - flt/rt counter id allocation ioctl + * @hdl: output param, hdl used for deallocation, negative if allocation fails + * @hw_counter: HW counters for HW process + * @sw_counter: SW counters for uC / non-HW process + */ +struct ipa_ioc_flt_rt_counter_alloc { + int hdl; + struct ipa_flt_rt_counter_alloc hw_counter; + struct ipa_flt_rt_counter_alloc sw_counter; +}; + +/** + * struct ipa_flt_rt_stats - flt/rt stats info + * @num_pkts: number of packets + * @num_pkts_hash: number of packets in hash entry + * @num_bytes: number of bytes + */ +struct ipa_flt_rt_stats { + uint32_t num_pkts; + uint32_t num_pkts_hash; + uint64_t num_bytes; +}; + +/** + * struct ipa_ioc_flt_rt_query - flt/rt counter id query + * @start_id: start counter id for query + * @end_id: end counter id for query + * @reset: this query need hw counter to be reset or not + * @stats_size: sizeof(ipa_flt_rt_stats) + * @reserved: reserved bits for alignment + * @stats: structure contains the query result + */ +struct ipa_ioc_flt_rt_query { + uint8_t start_id; + uint8_t end_id; + uint8_t reset; + uint32_t stats_size; + uint8_t reserved; + uint64_t stats; +}; + +enum ipacm_client_enum { + IPACM_CLIENT_USB = 1, + IPACM_CLIENT_WLAN, + IPACM_CLIENT_MAX +}; + +#define IPACM_SUPPORT_OF_LAN_STATS_FOR_ODU_CLIENTS + +enum ipacm_per_client_device_type { + IPACM_CLIENT_DEVICE_TYPE_USB = 0, + IPACM_CLIENT_DEVICE_TYPE_WLAN = 1, + IPACM_CLIENT_DEVICE_TYPE_ETH = 2, + IPACM_CLIENT_DEVICE_TYPE_ODU = 3, + IPACM_CLIENT_DEVICE_MAX +}; + +/** + * max number of device types supported. + */ +#define IPACM_MAX_CLIENT_DEVICE_TYPES IPACM_CLIENT_DEVICE_MAX + +/** + * @lanIface - Name of the lan interface + * @mac: Mac address of the client. + */ +struct ipa_lan_client_msg { + char lanIface[IPA_RESOURCE_NAME_MAX]; + uint8_t mac[IPA_MAC_ADDR_SIZE]; +}; + +/** + * struct ipa_lan_client - lan client data + * @mac: MAC Address of the client. + * @client_idx: Client Index. + * @inited: Bool to indicate whether client info is set. + */ +struct ipa_lan_client { + uint8_t mac[IPA_MAC_ADDR_SIZE]; + int8_t client_idx; + uint8_t inited; +}; + +/** + * struct ipa_lan_client_cntr_index + * @ul_cnt_idx: H/w counter index for uplink stats + * @dl_cnt_idx: H/w counter index for downlink stats + */ +struct ipa_lan_client_cntr_index { + __u8 ul_cnt_idx; + __u8 dl_cnt_idx; +}; + +/** + * struct ipa_tether_device_info - tether device info indicated from IPACM + * @ul_src_pipe: Source pipe of the lan client. + * @hdr_len: Header length of the client. + * @num_clients: Number of clients connected. + */ +struct ipa_tether_device_info { + __s32 ul_src_pipe; + __u8 hdr_len; + __u8 padding1; + __u16 padding2; + __u32 num_clients; + struct ipa_lan_client lan_client[IPA_MAX_NUM_HW_PATH_CLIENTS]; + struct ipa_lan_client_cntr_index + lan_client_indices[IPA_MAX_NUM_HW_PATH_CLIENTS]; +}; + +/** + * enum ipa_vlan_ifaces - vlan interfaces types + */ +enum ipa_vlan_ifaces { + IPA_VLAN_IF_ETH, + IPA_VLAN_IF_ETH0, + IPA_VLAN_IF_ETH1, + IPA_VLAN_IF_RNDIS, + IPA_VLAN_IF_ECM +}; + +#define IPA_VLAN_IF_EMAC IPA_VLAN_IF_ETH +#define IPA_VLAN_IF_MAX (IPA_VLAN_IF_ECM + 1) + +/** + * struct ipa_get_vlan_mode - get vlan mode of a Lan interface + * @iface: Lan interface type to be queried. + * @is_vlan_mode: output parameter, is interface in vlan mode, valid only when + * ioctl return val is non-negative + */ +struct ipa_ioc_get_vlan_mode { + enum ipa_vlan_ifaces iface; + uint32_t is_vlan_mode; +}; + +/** + * struct ipa_ioc_bridge_vlan_mapping_info - vlan to bridge mapping info + * @bridge_name: bridge interface name + * @vlan_id: vlan ID bridge is mapped to + * @bridge_ipv4: bridge interface ipv4 address + * @subnet_mask: bridge interface subnet mask + * @lan2lan_sw: indicate lan2lan traffic take sw-path or not + */ +struct ipa_ioc_bridge_vlan_mapping_info { + char bridge_name[IPA_RESOURCE_NAME_MAX]; + uint8_t lan2lan_sw; + uint16_t vlan_id; + uint32_t bridge_ipv4; + uint32_t subnet_mask; +}; + +struct ipa_coalesce_info { + uint8_t qmap_id; + uint8_t tcp_enable; + uint8_t udp_enable; +}; + +struct ipa_mtu_info { + char if_name[IPA_RESOURCE_NAME_MAX]; + enum ipa_ip_type ip_type; + uint16_t mtu_v4; + uint16_t mtu_v6; +}; + +struct ipa_odl_ep_info { + __u32 cons_pipe_num; + __u32 prod_pipe_num; + __u32 peripheral_iface_id; + __u32 ep_type; +}; + +struct odl_agg_pipe_info { + __u16 agg_byte_limit; +}; + +struct ipa_odl_modem_config { + __u8 config_status; +}; + +struct ipa_ioc_fnr_index_info { + uint8_t hw_counter_offset; + uint8_t sw_counter_offset; +}; + +enum ipacm_hw_index_counter_type { + UL_HW = 0, + DL_HW, + DL_ALL, + UL_ALL, +}; + +enum ipacm_hw_index_counter_virtual_type { + UL_HW_CACHE = 0, + DL_HW_CACHE, + UL_WLAN_TX, + DL_WLAN_TX +}; + +/** + * struct ipa_ioc_pdn_config - provide pdn configuration + * @dev_name: PDN interface name + * @pdn_cfg_type: type of the pdn config applied. + * @enable: enable/disable pdn config type. + * @u.collison_cfg.pdn_ip_addr: pdn_ip_address used in collision config. + * @u.passthrough_cfg.pdn_ip_addr: pdn_ip_address used in passthrough config. + * @u.passthrough_cfg.device_type: Device type of the client. + * @u.passthrough_cfg.vlan_id: VLAN ID of the client. + * @u.passthrough_cfg.client_mac_addr: client mac for which passthough + *» is enabled. + * @u.passthrough_cfg.skip_nat: skip NAT processing. + * @default_pdn: bool to indicate the config is for default pdn. + */ +struct ipa_ioc_pdn_config { + char dev_name[IPA_RESOURCE_NAME_MAX]; + enum ipa_pdn_config_event pdn_cfg_type; + __u8 enable; + union { + struct ipa_pdn_ip_collision_cfg { + __u32 pdn_ip_addr; + } collison_cfg; + + struct ipa_pdn_ip_passthrough_cfg { + __u32 pdn_ip_addr; + enum ipacm_per_client_device_type device_type; + __u16 vlan_id; + __u8 client_mac_addr[IPA_MAC_ADDR_SIZE]; + __u8 skip_nat; + } passthrough_cfg; + } u; + __u8 default_pdn; +}; + +/** + * struct ipa_ioc_mac_client_list_type- mac addr exception list + * @mac_addr: an array to hold clients mac addrs + * @num_of_clients: holds num of clients to blacklist or whitelist + * @flt_state: true to block current mac addrs and false to clean + * up all previous mac addrs + */ +struct ipa_ioc_mac_client_list_type { + int num_of_clients; + __u8 mac_addr[IPA_MAX_NUM_MAC_FLT][IPA_MAC_ADDR_SIZE]; + __u8 flt_state; + __u8 padding; +}; + +/** + * struct ipa_sw_flt_list_type- exception list + * @mac_enable: true to block current mac addrs and false to clean + * up all previous mac addrs + * @num_of_mac: holds num of clients to blacklist + * @mac_addr: an array to hold clients mac addrs + * @ipv4_segs_enable: true to block current ipv4 addrs and false to clean + * up all previous ipv4 addrs + * @ipv4_segs_ipv6_offload: reserved flexibility for future use. + * true will indicate ipv6 could be still offloaded and + * default is set to false as sw-path for ipv6 as well. + * @num_of_ipv4_segs: holds num of ipv4 segs to blacklist + * @ipv4_segs: an array to hold clients ipv4 segs addrs + * @iface_enable: true to block current ifaces and false to clean + * up all previous ifaces + * @num_of_iface: holds num of ifaces to blacklist + * @iface: an array to hold netdev ifaces + */ +struct ipa_sw_flt_list_type { + uint8_t mac_enable; + int num_of_mac; + uint8_t mac_addr[IPA_MAX_NUM_MAC_FLT][IPA_MAC_ADDR_SIZE]; + uint8_t ipv4_segs_enable; + uint8_t ipv4_segs_ipv6_offload; + int num_of_ipv4_segs; + uint32_t ipv4_segs[IPA_MAX_NUM_IPv4_SEGS_FLT][2]; + uint8_t iface_enable; + int num_of_iface; + char iface[IPA_MAX_NUM_IFACE_FLT][IPA_RESOURCE_NAME_MAX]; +}; + +/** + * struct ipa_ippt_sw_flt_list_type- exception list + * @ipv4_enable: true to block ipv4 addrs given below and false to clean + * up all previous ipv4 addrs + * @num_of_ipv4: holds num of ipv4 to SW-exception + * @ipv4: an array to hold ipv4 addrs to SW-exception + * @port_enable: true to block current ports and false to clean + * up all previous ports + * @num_of_port: holds num of ports to SW-exception + * @port: an array to hold connection ports to SW-exception + */ + +struct ipa_ippt_sw_flt_list_type { + uint8_t ipv4_enable; + int num_of_ipv4; + uint32_t ipv4[IPA_MAX_PDN_NUM]; + uint8_t port_enable; + int num_of_port; + uint16_t port[IPA_MAX_IPPT_NUM_PORT_FLT]; +}; + +/** + * struct ipa_ioc_sw_flt_list_type + * @ioctl_ptr: has to be typecasted to (__u64)(uintptr_t) + * @ioctl_data_size: + * Eg: For ipa_sw_flt_list_type = sizeof(ipa_sw_flt_list_type) + * Eg: For ipa_ippt_sw_flt_list_type = sizeof(ipa_ippt_sw_flt_list_type) + */ +struct ipa_ioc_sw_flt_list_type { + __u64 ioctl_ptr; + __u32 ioctl_data_size; + __u32 padding; +}; + +/** + * struct ipa_macsec_map - mapping between ethX to macsecY + * @phy_name: name of the physical NIC (ethX) + * - must be equal to an existing physical NIC name + * @macsec_name: name of the macsec NIC (macsecY) + */ +struct ipa_macsec_map { + char phy_name[IPA_RESOURCE_NAME_MAX]; + char macsec_name[IPA_RESOURCE_NAME_MAX]; +}; + +/** + * struct ipa_ioc_macsec_info - provide macsec info + * @ioctl_ptr: has to be typecasted to (__u64)(uintptr_t) + * @ioctl_data_size: + * Eg: For ipa_macsec_map = sizeof(ipa_macsec_map) + */ +struct ipa_ioc_macsec_info { + __u64 ioctl_ptr; + __u32 ioctl_data_size; + __u32 padding; +}; + + +enum ipa_ext_router_mode { + IPA_PREFIX_DISABLED = 0, + IPA_PREFIX_SHARING, + IPA_PREFIX_DELEGATION +}; + +/** + * struct ipa_ioc_ext_router_info - provide ext_router info + * @ipa_ext_router_mode: prefix sharing, prefix delegation, or disabled mode + * @pdn_name: PDN interface name + * @ipv6_addr: the prefix addr used for dummy or delegated prefixes + * @ipv6_mask: the ipv6 mask used to mask above addr to get the correct prefix + */ +struct ipa_ioc_ext_router_info { + enum ipa_ext_router_mode mode; + char pdn_name[IPA_RESOURCE_NAME_MAX]; + uint32_t ipv6_addr[4]; + uint32_t ipv6_mask[4]; +}; + +/** + * actual IOCTLs supported by IPA driver + */ +#define IPA_IOC_COAL_EVICT_POLICY _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_COAL_EVICT_POLICY, \ + struct ipa_ioc_coal_evict_policy *) +#define IPA_IOC_ADD_HDR _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_ADD_HDR, \ + struct ipa_ioc_add_hdr *) +#define IPA_IOC_DEL_HDR _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_DEL_HDR, \ + struct ipa_ioc_del_hdr *) +#define IPA_IOC_ADD_RT_RULE _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_ADD_RT_RULE, \ + struct ipa_ioc_add_rt_rule *) +#define IPA_IOC_ADD_RT_RULE_V2 _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_ADD_RT_RULE_V2, \ + struct ipa_ioc_add_rt_rule_v2 *) +#define IPA_IOC_ADD_RT_RULE_EXT _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_ADD_RT_RULE_EXT, \ + struct ipa_ioc_add_rt_rule_ext *) +#define IPA_IOC_ADD_RT_RULE_EXT_V2 _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_ADD_RT_RULE_EXT_V2, \ + struct ipa_ioc_add_rt_rule_ext_v2 *) +#define IPA_IOC_ADD_RT_RULE_AFTER _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_ADD_RT_RULE_AFTER, \ + struct ipa_ioc_add_rt_rule_after *) +#define IPA_IOC_ADD_RT_RULE_AFTER_V2 _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_ADD_RT_RULE_AFTER_V2, \ + struct ipa_ioc_add_rt_rule_after_v2 *) +#define IPA_IOC_DEL_RT_RULE _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_DEL_RT_RULE, \ + struct ipa_ioc_del_rt_rule *) +#define IPA_IOC_ADD_FLT_RULE _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_ADD_FLT_RULE, \ + struct ipa_ioc_add_flt_rule *) +#define IPA_IOC_ADD_FLT_RULE_V2 _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_ADD_FLT_RULE_V2, \ + struct ipa_ioc_add_flt_rule_v2 *) +#define IPA_IOC_ADD_FLT_RULE_AFTER _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_ADD_FLT_RULE_AFTER, \ + struct ipa_ioc_add_flt_rule_after *) +#define IPA_IOC_ADD_FLT_RULE_AFTER_V2 _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_ADD_FLT_RULE_AFTER_V2, \ + struct ipa_ioc_add_flt_rule_after_v2 *) +#define IPA_IOC_DEL_FLT_RULE _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_DEL_FLT_RULE, \ + struct ipa_ioc_del_flt_rule *) +#define IPA_IOC_COMMIT_HDR _IO(IPA_IOC_MAGIC,\ + IPA_IOCTL_COMMIT_HDR) +#define IPA_IOC_RESET_HDR _IO(IPA_IOC_MAGIC,\ + IPA_IOCTL_RESET_HDR) +#define IPA_IOC_COMMIT_RT _IOW(IPA_IOC_MAGIC, \ + IPA_IOCTL_COMMIT_RT, \ + enum ipa_ip_type) +#define IPA_IOC_RESET_RT _IOW(IPA_IOC_MAGIC, \ + IPA_IOCTL_RESET_RT, \ + enum ipa_ip_type) +#define IPA_IOC_COMMIT_FLT _IOW(IPA_IOC_MAGIC, \ + IPA_IOCTL_COMMIT_FLT, \ + enum ipa_ip_type) +#define IPA_IOC_RESET_FLT _IOW(IPA_IOC_MAGIC, \ + IPA_IOCTL_RESET_FLT, \ + enum ipa_ip_type) +#define IPA_IOC_DUMP _IO(IPA_IOC_MAGIC, \ + IPA_IOCTL_DUMP) +#define IPA_IOC_GET_RT_TBL _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_GET_RT_TBL, \ + struct ipa_ioc_get_rt_tbl *) +#define IPA_IOC_PUT_RT_TBL _IOW(IPA_IOC_MAGIC, \ + IPA_IOCTL_PUT_RT_TBL, \ + uint32_t) +#define IPA_IOC_COPY_HDR _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_COPY_HDR, \ + struct ipa_ioc_copy_hdr *) +#define IPA_IOC_QUERY_INTF _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_QUERY_INTF, \ + struct ipa_ioc_query_intf *) +#define IPA_IOC_QUERY_INTF_TX_PROPS _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_QUERY_INTF_TX_PROPS, \ + struct ipa_ioc_query_intf_tx_props *) +#define IPA_IOC_QUERY_INTF_RX_PROPS _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_QUERY_INTF_RX_PROPS, \ + struct ipa_ioc_query_intf_rx_props *) +#define IPA_IOC_QUERY_INTF_EXT_PROPS _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_QUERY_INTF_EXT_PROPS, \ + struct ipa_ioc_query_intf_ext_props *) +#define IPA_IOC_GET_HDR _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_GET_HDR, \ + struct ipa_ioc_get_hdr *) +#define IPA_IOC_PUT_HDR _IOW(IPA_IOC_MAGIC, \ + IPA_IOCTL_PUT_HDR, \ + uint32_t) +#define IPA_IOC_ALLOC_NAT_MEM _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_ALLOC_NAT_MEM, \ + struct ipa_ioc_nat_alloc_mem *) +#define IPA_IOC_ALLOC_NAT_TABLE _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_ALLOC_NAT_TABLE, \ + struct ipa_ioc_nat_ipv6ct_table_alloc *) +#define IPA_IOC_ALLOC_IPV6CT_TABLE _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_ALLOC_IPV6CT_TABLE, \ + struct ipa_ioc_nat_ipv6ct_table_alloc *) +#define IPA_IOC_V4_INIT_NAT _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_V4_INIT_NAT, \ + struct ipa_ioc_v4_nat_init *) +#define IPA_IOC_INIT_IPV6CT_TABLE _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_INIT_IPV6CT_TABLE, \ + struct ipa_ioc_ipv6ct_init *) +#define IPA_IOC_NAT_DMA _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_NAT_DMA, \ + struct ipa_ioc_nat_dma_cmd *) +#define IPA_IOC_TABLE_DMA_CMD _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_TABLE_DMA_CMD, \ + struct ipa_ioc_nat_dma_cmd *) +#define IPA_IOC_V4_DEL_NAT _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_V4_DEL_NAT, \ + struct ipa_ioc_v4_nat_del *) +#define IPA_IOC_DEL_NAT_TABLE _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_DEL_NAT_TABLE, \ + struct ipa_ioc_nat_ipv6ct_table_del *) +#define IPA_IOC_DEL_IPV6CT_TABLE _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_DEL_IPV6CT_TABLE, \ + struct ipa_ioc_nat_ipv6ct_table_del *) +#define IPA_IOC_GET_NAT_OFFSET _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_GET_NAT_OFFSET, \ + uint32_t *) +#define IPA_IOC_NAT_MODIFY_PDN _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_NAT_MODIFY_PDN, \ + struct ipa_ioc_nat_pdn_entry *) +#define IPA_IOC_SET_FLT _IOW(IPA_IOC_MAGIC, \ + IPA_IOCTL_SET_FLT, \ + uint32_t) +#define IPA_IOC_PULL_MSG _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_PULL_MSG, \ + struct ipa_msg_meta *) +#define IPA_IOC_RM_ADD_DEPENDENCY _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_RM_ADD_DEPENDENCY, \ + struct ipa_ioc_rm_dependency *) +#define IPA_IOC_RM_DEL_DEPENDENCY _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_RM_DEL_DEPENDENCY, \ + struct ipa_ioc_rm_dependency *) +#define IPA_IOC_GENERATE_FLT_EQ _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_GENERATE_FLT_EQ, \ + struct ipa_ioc_generate_flt_eq *) +#define IPA_IOC_QUERY_EP_MAPPING _IOR(IPA_IOC_MAGIC, \ + IPA_IOCTL_QUERY_EP_MAPPING, \ + uint32_t) +#define IPA_IOC_QUERY_RT_TBL_INDEX _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_QUERY_RT_TBL_INDEX, \ + struct ipa_ioc_get_rt_tbl_indx *) +#define IPA_IOC_WRITE_QMAPID _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_WRITE_QMAPID, \ + struct ipa_ioc_write_qmapid *) +#define IPA_IOC_MDFY_FLT_RULE _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_MDFY_FLT_RULE, \ + struct ipa_ioc_mdfy_flt_rule *) +#define IPA_IOC_MDFY_FLT_RULE_V2 _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_MDFY_FLT_RULE_V2, \ + struct ipa_ioc_mdfy_flt_rule_v2 *) +#define IPA_IOC_MDFY_RT_RULE _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_MDFY_RT_RULE, \ + struct ipa_ioc_mdfy_rt_rule *) +#define IPA_IOC_MDFY_RT_RULE_V2 _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_MDFY_RT_RULE_V2, \ + struct ipa_ioc_mdfy_rt_rule_v2 *) + +#define IPA_IOC_NOTIFY_WAN_UPSTREAM_ROUTE_ADD _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_NOTIFY_WAN_UPSTREAM_ROUTE_ADD, \ + struct ipa_wan_msg *) + +#define IPA_IOC_NOTIFY_WAN_UPSTREAM_ROUTE_DEL _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_NOTIFY_WAN_UPSTREAM_ROUTE_DEL, \ + struct ipa_wan_msg *) +#define IPA_IOC_NOTIFY_WAN_EMBMS_CONNECTED _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_NOTIFY_WAN_EMBMS_CONNECTED, \ + struct ipa_wan_msg *) +#define IPA_IOC_ADD_HDR_PROC_CTX _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_ADD_HDR_PROC_CTX, \ + struct ipa_ioc_add_hdr_proc_ctx *) +#define IPA_IOC_DEL_HDR_PROC_CTX _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_DEL_HDR_PROC_CTX, \ + struct ipa_ioc_del_hdr_proc_ctx *) + +#define IPA_IOC_GET_HW_VERSION _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_GET_HW_VERSION, \ + enum ipa_hw_type *) + +#define IPA_IOC_ADD_VLAN_IFACE _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_ADD_VLAN_IFACE, \ + struct ipa_ioc_vlan_iface_info *) + +#define IPA_IOC_DEL_VLAN_IFACE _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_DEL_VLAN_IFACE, \ + struct ipa_ioc_vlan_iface_info *) + +#define IPA_IOC_ADD_L2TP_VLAN_MAPPING _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_ADD_L2TP_VLAN_MAPPING, \ + struct ipa_ioc_l2tp_vlan_mapping_info *) + +#define IPA_IOC_DEL_L2TP_VLAN_MAPPING _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_DEL_L2TP_VLAN_MAPPING, \ + struct ipa_ioc_l2tp_vlan_mapping_info *) +#define IPA_IOC_GET_VLAN_MODE _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_GET_VLAN_MODE, \ + struct ipa_ioc_get_vlan_mode *) +#define IPA_IOC_ADD_BRIDGE_VLAN_MAPPING _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_ADD_BRIDGE_VLAN_MAPPING, \ + struct ipa_ioc_bridge_vlan_mapping_info) + +#define IPA_IOC_DEL_BRIDGE_VLAN_MAPPING _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_DEL_BRIDGE_VLAN_MAPPING, \ + struct ipa_ioc_bridge_vlan_mapping_info) +#define IPA_IOC_CLEANUP _IO(IPA_IOC_MAGIC,\ + IPA_IOCTL_CLEANUP) +#define IPA_IOC_QUERY_WLAN_CLIENT _IO(IPA_IOC_MAGIC,\ + IPA_IOCTL_QUERY_WLAN_CLIENT) + +#define IPA_IOC_ODL_QUERY_ADAPL_EP_INFO _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_ODL_QUERY_ADAPL_EP_INFO, \ + struct ipa_odl_ep_info) +#define IPA_IOC_ODL_GET_AGG_BYTE_LIMIT _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_ODL_GET_AGG_BYTE_LIMIT, \ + struct odl_agg_pipe_info) + +#define IPA_IOC_ODL_QUERY_MODEM_CONFIG _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_ODL_QUERY_MODEM_CONFIG, \ + struct ipa_odl_modem_config) + +#define IPA_IOC_GSB_CONNECT _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_GSB_CONNECT, \ + struct ipa_ioc_gsb_info) + +#define IPA_IOC_GSB_DISCONNECT _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_GSB_DISCONNECT, \ + struct ipa_ioc_gsb_info) + +#define IPA_IOC_WIGIG_FST_SWITCH _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_WIGIG_FST_SWITCH, \ + struct ipa_ioc_wigig_fst_switch) + +#define IPA_IOC_FNR_COUNTER_ALLOC _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_FNR_COUNTER_ALLOC, \ + struct ipa_ioc_flt_rt_counter_alloc) + +#define IPA_IOC_FNR_COUNTER_DEALLOC _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_FNR_COUNTER_DEALLOC, \ + int) + +#define IPA_IOC_FNR_COUNTER_QUERY _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_FNR_COUNTER_QUERY, \ + struct ipa_ioc_flt_rt_query) + +#define IPA_IOC_SET_FNR_COUNTER_INFO _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_SET_FNR_COUNTER_INFO, \ + struct ipa_ioc_fnr_index_info) + +#define IPA_IOC_GET_NAT_IN_SRAM_INFO _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_GET_NAT_IN_SRAM_INFO, \ + struct ipa_nat_in_sram_info) + +#define IPA_IOC_APP_CLOCK_VOTE _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_APP_CLOCK_VOTE, \ + uint32_t) + +#define IPA_IOC_PDN_CONFIG _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_PDN_CONFIG, \ + struct ipa_ioc_pdn_config) + +#define IPA_IOC_SET_MAC_FLT _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_SET_MAC_FLT, \ + struct ipa_ioc_mac_client_list_type) + +#define IPA_IOC_GET_PHERIPHERAL_EP_INFO _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_GET_PHERIPHERAL_EP_INFO, \ + struct ipa_ioc_get_ep_info) + +#define IPA_IOC_ADD_UC_ACT_ENTRY _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_ADD_UC_ACT_ENTRY, \ + union ipa_ioc_uc_activation_entry) + +#define IPA_IOC_DEL_UC_ACT_ENTRY _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_DEL_UC_ACT_ENTRY, \ + __u16) + +#define IPA_IOC_SET_SW_FLT _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_SET_SW_FLT, \ + struct ipa_ioc_sw_flt_list_type) + +#define IPA_IOC_SET_PKT_THRESHOLD _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_SET_PKT_THRESHOLD, \ + struct ipa_ioc_set_pkt_threshold) + +#define IPA_IOC_ADD_EoGRE_MAPPING _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_ADD_EoGRE_MAPPING, \ + struct ipa_ioc_eogre_info) +#define IPA_IOC_DEL_EoGRE_MAPPING _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_DEL_EoGRE_MAPPING, \ + struct ipa_ioc_eogre_info) + +#define IPA_IOC_SET_IPPT_SW_FLT _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_SET_IPPT_SW_FLT, \ + struct ipa_ioc_sw_flt_list_type) + +#define IPA_IOC_ADD_MACSEC_MAPPING _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_ADD_MACSEC_MAPPING, \ + struct ipa_ioc_macsec_info) +#define IPA_IOC_DEL_MACSEC_MAPPING _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_DEL_MACSEC_MAPPING, \ + struct ipa_ioc_macsec_info) + +#define IPA_IOC_SET_NAT_EXC_RT_TBL_IDX _IOW(IPA_IOC_MAGIC, \ + IPA_IOCTL_SET_NAT_EXC_RT_TBL_IDX, \ + uint32_t) + +#define IPA_IOC_SET_CONN_TRACK_EXC_RT_TBL_IDX _IOW(IPA_IOC_MAGIC, \ + IPA_IOCTL_SET_CONN_TRACK_EXC_RT_TBL_IDX, \ + uint32_t) + +#define IPA_IOC_SET_EXT_ROUTER_MODE _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_SET_EXT_ROUTER_MODE, \ + struct ipa_ioc_ext_router_info) +/* + * unique magic number of the Tethering bridge ioctls + */ +#define TETH_BRIDGE_IOC_MAGIC 0xCE + +/* + * Ioctls supported by Tethering bridge driver + */ +#define TETH_BRIDGE_IOCTL_SET_BRIDGE_MODE 0 +#define TETH_BRIDGE_IOCTL_SET_AGGR_PARAMS 1 +#define TETH_BRIDGE_IOCTL_GET_AGGR_PARAMS 2 +#define TETH_BRIDGE_IOCTL_GET_AGGR_CAPABILITIES 3 +#define TETH_BRIDGE_IOCTL_MAX 4 + + +/** + * enum teth_link_protocol_type - link protocol (IP / Ethernet) + */ +enum teth_link_protocol_type { + TETH_LINK_PROTOCOL_IP, + TETH_LINK_PROTOCOL_ETHERNET, + TETH_LINK_PROTOCOL_MAX, +}; + +/** + * enum teth_aggr_protocol_type - Aggregation protocol (MBIM / TLP) + */ +enum teth_aggr_protocol_type { + TETH_AGGR_PROTOCOL_NONE, + TETH_AGGR_PROTOCOL_MBIM, + TETH_AGGR_PROTOCOL_TLP, + TETH_AGGR_PROTOCOL_MAX, +}; + +/** + * struct teth_aggr_params_link - Aggregation parameters for uplink/downlink + * @aggr_prot: Aggregation protocol (MBIM / TLP) + * @max_transfer_size_byte: Maximal size of aggregated packet in bytes. + * Default value is 16*1024. + * @max_datagrams: Maximal number of IP packets in an aggregated + * packet. Default value is 16 + */ +struct teth_aggr_params_link { + enum teth_aggr_protocol_type aggr_prot; + uint32_t max_transfer_size_byte; + uint32_t max_datagrams; +}; + + +/** + * struct teth_aggr_params - Aggregation parmeters + * @ul: Uplink parameters + * @dl: Downlink parmaeters + */ +struct teth_aggr_params { + struct teth_aggr_params_link ul; + struct teth_aggr_params_link dl; +}; + +/** + * struct teth_aggr_capabilities - Aggregation capabilities + * @num_protocols: Number of protocols described in the array + * @prot_caps[]: Array of aggregation capabilities per protocol + */ +struct teth_aggr_capabilities { + uint16_t num_protocols; + struct teth_aggr_params_link prot_caps[0]; +}; + +/** + * struct teth_ioc_set_bridge_mode + * @link_protocol: link protocol (IP / Ethernet) + * @lcid: logical channel number + */ +struct teth_ioc_set_bridge_mode { + enum teth_link_protocol_type link_protocol; + uint16_t lcid; +}; + +/** + * struct teth_ioc_set_aggr_params + * @aggr_params: Aggregation parmeters + * @lcid: logical channel number + */ +struct teth_ioc_aggr_params { + struct teth_aggr_params aggr_params; + uint16_t lcid; +}; + +/** + * struct ipa_ioc_coal_evict_policy - + * + * Structure used with the IPA_IOCTL_COAL_EVICT_POLICY ioctl to + * control TCP/UDP eviction policy. + * + * @coal_vp_thrshld: + * + * Connection that is opened below this val will not get + * evicted. valid till v5_2. + * + * @coal_eviction_en: + * + * bool -> Enable eviction + * + * @coal_vp_gran_sel: + * + * Select the appropriate time granularity: four possible values (0-3) + * Valid from v5_5. + * + * @coal_vp_udp_thrshld: + * + * Coalescing eviction threshold. LRU VP stickness/inactivity + * defined by this threshold fot UDP connectiom. 0 mean all UDP's + * non sticky. Valid from v5_5. + * + * @coal_vp_tcp_thrshld: + * + * Coalescing eviction threshold. LRU VP stickness/inactivity + * defined by this threshold fot TCP connection. 0 mean all TCP's + * non sticky. Valid from v5_5. + * + * @coal_vp_udp_thrshld_en: + * + * bool -> Coalescing eviction enable for UDP connections when UDP + * pacjet arrived. 0-disable these evictions. Valid from v5_5. + * + * @coal_vp_tcp_thrshld_en: + * + * bool -> Coalescing eviction enable for TCP connections when TCP + * pacjet arrived. 0-disable these evictions. Valid from v5_5. + * + * @coal_vp_tcp_num: + * + * Configured TCP NUM value. SW define when TCP/UDP will treat as + * excess during eviction process. Valid from v5_5. + */ +struct ipa_ioc_coal_evict_policy { + uint32_t coal_vp_thrshld; + uint32_t reserved1; /* reserved bits for alignment */ + uint8_t coal_eviction_en; + uint8_t coal_vp_gran_sel; + uint8_t coal_vp_udp_thrshld; + uint8_t coal_vp_tcp_thrshld; + uint8_t coal_vp_udp_thrshld_en; + uint8_t coal_vp_tcp_thrshld_en; + uint8_t coal_vp_tcp_num; + uint8_t reserved2; /* reserved bits for alignment */ +}; + +/** + * struct ipa_nat_in_sram_info - query for nat in sram particulars + * @sram_mem_available_for_nat: Amount SRAM available to fit nat table + * @nat_table_offset_into_mmap: Offset into mmap'd vm where table will be + * @best_nat_in_sram_size_rqst: The size to request for mmap + * + * The last two elements above are required to deal with situations + * where the SRAM's physical address and size don't play nice with + * mmap'ings page size and boundary attributes. + */ +struct ipa_nat_in_sram_info { + uint32_t sram_mem_available_for_nat; + uint32_t nat_table_offset_into_mmap; + uint32_t best_nat_in_sram_size_rqst; +}; + +/** + * enum ipa_app_clock_vote_type + * + * The types of votes that can be accepted by the + * IPA_IOC_APP_CLOCK_VOTE ioctl + */ +enum ipa_app_clock_vote_type { + IPA_APP_CLK_DEVOTE = 0, + IPA_APP_CLK_VOTE = 1, + IPA_APP_CLK_RESET_VOTE = 2, +}; + +#define TETH_BRIDGE_IOC_SET_BRIDGE_MODE _IOW(TETH_BRIDGE_IOC_MAGIC, \ + TETH_BRIDGE_IOCTL_SET_BRIDGE_MODE, \ + struct teth_ioc_set_bridge_mode *) +#define TETH_BRIDGE_IOC_SET_AGGR_PARAMS _IOW(TETH_BRIDGE_IOC_MAGIC, \ + TETH_BRIDGE_IOCTL_SET_AGGR_PARAMS, \ + struct teth_ioc_aggr_params *) +#define TETH_BRIDGE_IOC_GET_AGGR_PARAMS _IOR(TETH_BRIDGE_IOC_MAGIC, \ + TETH_BRIDGE_IOCTL_GET_AGGR_PARAMS, \ + struct teth_ioc_aggr_params *) +#define TETH_BRIDGE_IOC_GET_AGGR_CAPABILITIES _IOWR(TETH_BRIDGE_IOC_MAGIC, \ + TETH_BRIDGE_IOCTL_GET_AGGR_CAPABILITIES, \ + struct teth_aggr_capabilities *) + +/* + * unique magic number of the ODU bridge ioctls + */ +#define ODU_BRIDGE_IOC_MAGIC 0xCD + +/* + * Ioctls supported by ODU bridge driver + */ +#define ODU_BRIDGE_IOCTL_SET_MODE 0 +#define ODU_BRIDGE_IOCTL_SET_LLV6_ADDR 1 +#define ODU_BRIDGE_IOCTL_MAX 2 + + +/** + * enum odu_bridge_mode - bridge mode + * (ROUTER MODE / BRIDGE MODE) + */ +enum odu_bridge_mode { + ODU_BRIDGE_MODE_ROUTER, + ODU_BRIDGE_MODE_BRIDGE, + ODU_BRIDGE_MODE_MAX, +}; + +#define ODU_BRIDGE_IOC_SET_MODE _IOW(ODU_BRIDGE_IOC_MAGIC, \ + ODU_BRIDGE_IOCTL_SET_MODE, \ + enum odu_bridge_mode) + +#define ODU_BRIDGE_IOC_SET_LLV6_ADDR _IOW(ODU_BRIDGE_IOC_MAGIC, \ + ODU_BRIDGE_IOCTL_SET_LLV6_ADDR, \ + struct in6_addr *) + +#endif /* _UAPI_MSM_IPA_H_ */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/include/uapi/linux/rmnet_ipa_fd_ioctl.h b/qcom/opensource/dataipa/drivers/platform/msm/include/uapi/linux/rmnet_ipa_fd_ioctl.h new file mode 100644 index 0000000000..12aa9a1ba3 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/include/uapi/linux/rmnet_ipa_fd_ioctl.h @@ -0,0 +1,314 @@ +/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ +/* + * Copyright (c) 2013-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _RMNET_IPA_FD_IOCTL_H +#define _RMNET_IPA_FD_IOCTL_H + +#include +#include +#include + +/** + * unique magic number of the IPA_WAN device + */ +#define WAN_IOC_MAGIC 0x69 + +#define WAN_IOCTL_ADD_FLT_RULE 0 +#define WAN_IOCTL_ADD_FLT_INDEX 1 +#define WAN_IOCTL_VOTE_FOR_BW_MBPS 2 +#define WAN_IOCTL_POLL_TETHERING_STATS 3 +#define WAN_IOCTL_SET_DATA_QUOTA 4 +#define WAN_IOCTL_SET_TETHER_CLIENT_PIPE 5 +#define WAN_IOCTL_QUERY_TETHER_STATS 6 +#define WAN_IOCTL_RESET_TETHER_STATS 7 +#define WAN_IOCTL_QUERY_DL_FILTER_STATS 8 +#define WAN_IOCTL_ADD_FLT_RULE_EX 9 +#define WAN_IOCTL_QUERY_TETHER_STATS_ALL 10 +#define WAN_IOCTL_NOTIFY_WAN_STATE 11 +#define WAN_IOCTL_ADD_UL_FLT_RULE 12 +#define WAN_IOCTL_ENABLE_PER_CLIENT_STATS 13 +#define WAN_IOCTL_QUERY_PER_CLIENT_STATS 14 +#define WAN_IOCTL_SET_LAN_CLIENT_INFO 15 +#define WAN_IOCTL_CLEAR_LAN_CLIENT_INFO 16 +#define WAN_IOCTL_SEND_LAN_CLIENT_MSG 17 +#define WAN_IOCTL_ADD_OFFLOAD_CONNECTION 18 +#define WAN_IOCTL_RMV_OFFLOAD_CONNECTION 19 +#define WAN_IOCTL_GET_WAN_MTU 20 +#define WAN_IOCTL_SET_DATA_QUOTA_WARNING 21 +#define WAN_IOCTL_NOTIFY_NAT_MOVE_RES 22 + +/* User space may not have this defined. */ +#ifndef IFNAMSIZ +#define IFNAMSIZ 16 +#endif + +/** + * struct wan_ioctl_poll_tethering_stats - structure used for + * WAN_IOCTL_POLL_TETHERING_STATS IOCTL. + * + * @polling_interval_secs: Polling interval in seconds. + * @reset_stats: Indicate whether to reset the stats (use 1) or not. + * + * The structure to be used by the user space in order to request for the + * tethering stats to be polled. Setting the interval to 0 indicates to stop + * the polling process. + */ +struct wan_ioctl_poll_tethering_stats { + uint64_t polling_interval_secs; + uint8_t reset_stats; +}; + +/** + * struct wan_ioctl_set_data_quota - structure used for + * WAN_IOCTL_SET_DATA_QUOTA IOCTL. + * + * @interface_name: Name of the interface on which to set the quota. + * @quota_mbytes: Quota (in Mbytes) for the above interface. + * @set_quota: Indicate whether to set the quota (use 1) or + * unset the quota. + * + * The structure to be used by the user space in order to request + * a quota to be set on a specific interface (by specifying its name). + */ +struct wan_ioctl_set_data_quota { + char interface_name[IFNAMSIZ]; + uint64_t quota_mbytes; + uint8_t set_quota; +}; + +/** + * struct wan_ioctl_set_data_quota_warning - structure used for + * WAN_IOCTL_SET_DATA_QUOTA_WARNING IOCTL. + * + * @interface_name: Name of the interface on which to set the quota or + * warning. + * @quota_mbytes: Quota (in Mbytes) for the above interface. + * @set_quota: Indicate whether to set the quota/warning (use 1) or + * unset the quota/warning. + * @set_warning: Indicate whether to set the quota/warning (use 1) or + * unset the quota/warning. + * @warning_mbytes: Warning (in Mbytes) for the above interface. + * @set_warning: Indicate whether to set the warning (use 1) or + * unset the warning. + * + * The structure to be used by the user space in order to request + * a quota to be set on a specific interface (by specifying its name). + */ +struct wan_ioctl_set_data_quota_warning { + char interface_name[IFNAMSIZ]; + uint64_t quota_mbytes; + uint8_t set_quota; + uint8_t set_warning; + uint16_t padding2; + uint64_t warning_mbytes; +}; + +struct wan_ioctl_set_tether_client_pipe { + /* enum of tether interface */ + enum ipacm_client_enum ipa_client; + uint8_t reset_client; + uint32_t ul_src_pipe_len; + uint32_t ul_src_pipe_list[QMI_IPA_MAX_PIPES_V01]; + uint32_t dl_dst_pipe_len; + uint32_t dl_dst_pipe_list[QMI_IPA_MAX_PIPES_V01]; +}; + +struct wan_ioctl_query_tether_stats { + /* Name of the upstream interface */ + char upstreamIface[IFNAMSIZ]; + /* Name of the tethered interface */ + char tetherIface[IFNAMSIZ]; + /* enum of tether interface */ + enum ipacm_client_enum ipa_client; + uint64_t ipv4_tx_packets; + uint64_t ipv4_tx_bytes; + uint64_t ipv4_rx_packets; + uint64_t ipv4_rx_bytes; + uint64_t ipv6_tx_packets; + uint64_t ipv6_tx_bytes; + uint64_t ipv6_rx_packets; + uint64_t ipv6_rx_bytes; +}; + +struct wan_ioctl_query_tether_stats_all { + /* Name of the upstream interface */ + char upstreamIface[IFNAMSIZ]; + /* enum of tether interface */ + enum ipacm_client_enum ipa_client; + uint8_t reset_stats; + uint64_t tx_bytes; + uint64_t rx_bytes; +}; + +struct wan_ioctl_reset_tether_stats { + /* Name of the upstream interface, not support now */ + char upstreamIface[IFNAMSIZ]; + /* Indicate whether to reset the stats (use 1) or not */ + uint8_t reset_stats; +}; + +struct wan_ioctl_query_dl_filter_stats { + /* Indicate whether to reset the filter stats (use 1) or not*/ + uint8_t reset_stats; + /* Modem response QMI */ + struct ipa_get_data_stats_resp_msg_v01 stats_resp; + /* provide right index to 1st firewall rule */ + uint32_t index; +}; + +struct wan_ioctl_notify_wan_state { + uint8_t up; + /* Name of the upstream interface */ + char upstreamIface[IFNAMSIZ]; +#define WAN_IOCTL_NOTIFY_WAN_INTF_NAME WAN_IOCTL_NOTIFY_WAN_INTF_NAME +}; +struct wan_ioctl_send_lan_client_msg { + /* Lan client info. */ + struct ipa_lan_client_msg lan_client; + /* Event to indicate whether client is + * connected or disconnected. + */ + enum ipa_per_client_stats_event client_event; +}; + +struct wan_ioctl_lan_client_info { + /* Device type of the client. */ + enum ipacm_per_client_device_type device_type; + /* MAC Address of the client. */ + uint8_t mac[IPA_MAC_ADDR_SIZE]; + /* Init client. */ + uint8_t client_init; + /* Client Index */ + int8_t client_idx; + /* Header length of the client. */ + uint8_t hdr_len; + /* Source pipe of the lan client. */ + enum ipa_client_type ul_src_pipe; + /* Counter indices for h/w fnr stats */ +#define IPA_HW_FNR_STATS + uint8_t ul_cnt_idx; + uint8_t dl_cnt_idx; +}; + +struct wan_ioctl_per_client_info { + /* MAC Address of the client. */ + uint8_t mac[IPA_MAC_ADDR_SIZE]; + /* Ipv4 UL traffic bytes. */ + uint64_t ipv4_tx_bytes; + /* Ipv4 DL traffic bytes. */ + uint64_t ipv4_rx_bytes; + /* Ipv6 UL traffic bytes. */ + uint64_t ipv6_tx_bytes; + /* Ipv6 DL traffic bytes. */ + uint64_t ipv6_rx_bytes; +}; + +struct wan_ioctl_query_per_client_stats { + /* Device type of the client. */ + enum ipacm_per_client_device_type device_type; + /* Indicate whether to reset the stats (use 1) or not */ + uint8_t reset_stats; + /* Indicates whether client is disconnected. */ + uint8_t disconnect_clnt; + /* Number of clients. */ + uint8_t num_clients; + /* Client information. */ + struct wan_ioctl_per_client_info + client_info[IPA_MAX_NUM_HW_PATH_CLIENTS]; +}; + +#define WAN_IOC_ADD_FLT_RULE _IOWR(WAN_IOC_MAGIC, \ + WAN_IOCTL_ADD_FLT_RULE, \ + struct ipa_install_fltr_rule_req_msg_v01 *) + +#define WAN_IOC_ADD_FLT_RULE_INDEX _IOWR(WAN_IOC_MAGIC, \ + WAN_IOCTL_ADD_FLT_INDEX, \ + struct ipa_fltr_installed_notif_req_msg_v01 *) + +#define WAN_IOC_VOTE_FOR_BW_MBPS _IOWR(WAN_IOC_MAGIC, \ + WAN_IOCTL_VOTE_FOR_BW_MBPS, \ + uint32_t *) + +#define WAN_IOC_POLL_TETHERING_STATS _IOWR(WAN_IOC_MAGIC, \ + WAN_IOCTL_POLL_TETHERING_STATS, \ + struct wan_ioctl_poll_tethering_stats *) + +#define WAN_IOC_SET_DATA_QUOTA _IOWR(WAN_IOC_MAGIC, \ + WAN_IOCTL_SET_DATA_QUOTA, \ + struct wan_ioctl_set_data_quota *) + +#define WAN_IOC_SET_TETHER_CLIENT_PIPE _IOWR(WAN_IOC_MAGIC, \ + WAN_IOCTL_SET_TETHER_CLIENT_PIPE, \ + struct wan_ioctl_set_tether_client_pipe *) + +#define WAN_IOC_QUERY_TETHER_STATS _IOWR(WAN_IOC_MAGIC, \ + WAN_IOCTL_QUERY_TETHER_STATS, \ + struct wan_ioctl_query_tether_stats *) + +#define WAN_IOC_RESET_TETHER_STATS _IOWR(WAN_IOC_MAGIC, \ + WAN_IOCTL_RESET_TETHER_STATS, \ + struct wan_ioctl_reset_tether_stats *) + +#define WAN_IOC_QUERY_DL_FILTER_STATS _IOWR(WAN_IOC_MAGIC, \ + WAN_IOCTL_QUERY_DL_FILTER_STATS, \ + struct wan_ioctl_query_dl_filter_stats *) + +#define WAN_IOC_ADD_FLT_RULE_EX _IOWR(WAN_IOC_MAGIC, \ + WAN_IOCTL_ADD_FLT_RULE_EX, \ + struct ipa_install_fltr_rule_req_ex_msg_v01 *) + +#define WAN_IOC_QUERY_TETHER_STATS_ALL _IOWR(WAN_IOC_MAGIC, \ + WAN_IOCTL_QUERY_TETHER_STATS_ALL, \ + struct wan_ioctl_query_tether_stats_all *) + +#define WAN_IOC_NOTIFY_WAN_STATE _IOWR(WAN_IOC_MAGIC, \ + WAN_IOCTL_NOTIFY_WAN_STATE, \ + struct wan_ioctl_notify_wan_state *) + +#define WAN_IOC_ADD_UL_FLT_RULE _IOWR(WAN_IOC_MAGIC, \ + WAN_IOCTL_ADD_UL_FLT_RULE, \ + struct ipa_configure_ul_firewall_rules_req_msg_v01 *) + +#define WAN_IOC_ENABLE_PER_CLIENT_STATS _IOWR(WAN_IOC_MAGIC, \ + WAN_IOCTL_ENABLE_PER_CLIENT_STATS, \ + bool *) + +#define WAN_IOC_QUERY_PER_CLIENT_STATS _IOWR(WAN_IOC_MAGIC, \ + WAN_IOCTL_QUERY_PER_CLIENT_STATS, \ + struct wan_ioctl_query_per_client_stats *) + +#define WAN_IOC_SET_LAN_CLIENT_INFO _IOWR(WAN_IOC_MAGIC, \ + WAN_IOCTL_SET_LAN_CLIENT_INFO, \ + struct wan_ioctl_lan_client_info *) + +#define WAN_IOC_SEND_LAN_CLIENT_MSG _IOWR(WAN_IOC_MAGIC, \ + WAN_IOCTL_SEND_LAN_CLIENT_MSG, \ + struct wan_ioctl_send_lan_client_msg *) + +#define WAN_IOC_CLEAR_LAN_CLIENT_INFO _IOWR(WAN_IOC_MAGIC, \ + WAN_IOCTL_CLEAR_LAN_CLIENT_INFO, \ + struct wan_ioctl_lan_client_info *) + +#define WAN_IOC_ADD_OFFLOAD_CONNECTION _IOWR(WAN_IOC_MAGIC, \ + WAN_IOCTL_ADD_OFFLOAD_CONNECTION, \ + struct ipa_add_offload_connection_req_msg_v01 *) + +#define WAN_IOC_RMV_OFFLOAD_CONNECTION _IOWR(WAN_IOC_MAGIC, \ + WAN_IOCTL_RMV_OFFLOAD_CONNECTION, \ + struct ipa_remove_offload_connection_req_msg_v01 *) + +#define WAN_IOC_GET_WAN_MTU _IOWR(WAN_IOC_MAGIC, \ + WAN_IOCTL_GET_WAN_MTU, \ + struct ipa_mtu_info *) + +#define WAN_IOC_SET_DATA_QUOTA_WARNING _IOWR(WAN_IOC_MAGIC, \ + WAN_IOCTL_SET_DATA_QUOTA_WARNING, \ + struct wan_ioctl_set_data_quota_warning) + +#define WAN_IOC_NOTIFY_NAT_MOVE_RES _IOWR(WAN_IOC_MAGIC, \ + WAN_IOCTL_NOTIFY_NAT_MOVE_RES, \ + bool) +#endif /* _RMNET_IPA_FD_IOCTL_H */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/Kbuild b/qcom/opensource/dataipa/drivers/platform/msm/ipa/Kbuild new file mode 100644 index 0000000000..a595e4cf6f --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/Kbuild @@ -0,0 +1,88 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ipam-y += \ + ipa_rm.o ipa_rm_dependency_graph.o ipa_rm_peers_list.o ipa_rm_resource.o ipa_rm_inactivity_timer.o \ + ipa_v3/ipa.o \ + ipa_v3/ipa_debugfs.o \ + ipa_v3/ipa_hdr.o \ + ipa_v3/ipa_flt.o \ + ipa_v3/ipa_rt.o \ + ipa_v3/ipa_dp.o \ + ipa_v3/ipa_client.o \ + ipa_v3/ipa_utils.o \ + ipa_v3/ipa_nat.o \ + ipa_v3/ipa_intf.o \ + ipa_v3/teth_bridge.o \ + ipa_v3/ipa_interrupts.o \ + ipa_v3/ipa_uc.o \ + ipa_v3/ipa_uc_wdi.o \ + ipa_v3/ipa_dma.o \ + ipa_v3/ipa_uc_mhi.o \ + ipa_v3/ipa_mhi.o \ + ipa_v3/ipa_uc_ntn.o \ + ipa_v3/ipa_hw_stats.o \ + ipa_v3/ipa_pm.o \ + ipa_v3/ipa_wdi3_i.o \ + ipa_v3/ipa_odl.o \ + ipa_v3/ipa_wigig_i.o \ + ipa_v3/ipa_qdss.o \ + ipa_v3/ipa_uc_holb_monitor.o \ + ipa_v3/ipahal/ipahal.o \ + ipa_v3/ipahal/ipahal_reg.o \ + ipa_v3/ipahal/ipahal_fltrt.o \ + ipa_v3/ipahal/ipahal_hw_stats.o \ + ipa_v3/ipahal/ipahal_nat.o \ + ipa_v3/ipa_eth_i.o \ + ipa_v3/ipa_stats.o + +ipam-$(CONFIG_IPA_TSP) += ipa_v3/ipa_tsp.o \ + ipa_v3/ipahal/ipahal_tsp.o + +ipam-$(CONFIG_RMNET_IPA3) += ipa_v3/rmnet_ipa.o ipa_v3/ipa_qmi_service_v01.o \ + ipa_v3/ipa_qmi_service.o ipa_v3/rmnet_ctl_ipa.o \ + ipa_v3/rmnet_ipa_fd_ioctl.o ipa_v3/rmnet_ll_ipa.o + +ipam-$(CONFIG_IPA_CLIENTS_MANAGER) += ipa_clients/ipa_usb.o \ + ipa_clients/ipa_wdi3.o \ + ipa_clients/ipa_gsb.o \ + ipa_clients/ipa_uc_offload.o \ + ipa_clients/ipa_wigig.o \ + ipa_clients/ipa_mhi_client.o \ + ipa_clients/ipa_eth.o + +ipam-$(CONFIG_RNDIS_IPA) += ipa_clients/rndis_ipa.o + +ipam-$(CONFIG_IPA3_MHI_PRIME_MANAGER) += ipa_v3/ipa_mpm.o + +ipam-$(CONFIG_IPA3_MHI_PROXY) += ipa_v3/ipa_mhi_proxy.o +ipam-$(CONFIG_IPA_EMULATION) += ipa_v3/ipa_dt_replacement.o + +ifneq (,$(filter $(CONFIG_IPA3_REGDUMP_IPA_4_5),y m)) +ipam-$(CONFIG_IPA3_REGDUMP) += ipa_v3/dump/ipa4.5/ipa_reg_dump.o +endif + +ifneq (,$(filter $(CONFIG_IPA3_REGDUMP_IPA_5_0),y m)) +ipam-$(CONFIG_IPA3_REGDUMP) += ipa_v3/dump/ipa5.0/ipa_reg_dump.o +endif + +ifneq (,$(filter $(CONFIG_IPA3_REGDUMP_IPA_5_5),y m)) +ipam-$(CONFIG_IPA3_REGDUMP) += ipa_v3/dump/ipa5.5/ipa_reg_dump.o +endif + +ipam-$(CONFIG_IPA_UT) += test/ipa_ut_framework.o test/ipa_test_example.o \ + test/ipa_test_mhi.o test/ipa_test_dma.o \ + test/ipa_test_hw_stats.o test/ipa_pm_ut.o \ + test/ipa_test_wdi3.o test/ipa_test_ntn.o + +ipatestm-$(CONFIG_IPA_KERNEL_TESTS_MODULE) += \ + ipa_test_module/ipa_test_module_impl.o \ + ipa_test_module/ipa_rm_ut.o + +ipanetm-y += ipa_v3/ipa_net.o + +obj-$(CONFIG_IPA3) += ipam.o +obj-$(CONFIG_IPA3) += ipanetm.o +obj-$(CONFIG_IPA_KERNEL_TESTS_MODULE) += ipatestm.o + +obj-y += ipa_v3/ ipa_clients/ + diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_clients/Kbuild b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_clients/Kbuild new file mode 100644 index 0000000000..28b307b09e --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_clients/Kbuild @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + +obj-$(CONFIG_ECM_IPA) += ecmipam.o +ecmipam-objs := ecm_ipa.o + diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_clients/ecm_ipa.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_clients/ecm_ipa.c new file mode 100644 index 0000000000..7064a8732e --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_clients/ecm_ipa.c @@ -0,0 +1,1649 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2013-2021, The Linux Foundation. All rights reserved. + * + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ecm_ipa.h" +#include "../ipa_common_i.h" +#include "../ipa_pm.h" +#include "../ipa_v3/ipa_i.h" + +#define DRIVER_NAME "ecm_ipa" +#define ECM_IPA_IPV4_HDR_NAME "ecm_eth_ipv4" +#define ECM_IPA_IPV6_HDR_NAME "ecm_eth_ipv6" +#define EMPTY_HDR_NAME "empty" +#define INACTIVITY_MSEC_DELAY 100 +#define DEFAULT_OUTSTANDING_HIGH 64 +#define DEFAULT_OUTSTANDING_LOW 32 +#define DEBUGFS_TEMP_BUF_SIZE 4 +#define TX_TIMEOUT (5 * HZ) +#define ULSO_MAX_SIZE 64000 + +#define IPA_ECM_IPC_LOG_PAGES 50 + +#define IPA_ECM_IPC_LOGGING(buf, fmt, args...) \ + do { \ + if (buf) \ + ipc_log_string((buf), fmt, __func__, __LINE__, \ + ## args); \ + } while (0) + +static void *ipa_ecm_logbuf; + +#define ECM_IPA_DEBUG(fmt, args...) \ + do { \ + pr_debug(DRIVER_NAME " %s:%d "\ + fmt, __func__, __LINE__, ## args);\ + if (ipa_ecm_logbuf) { \ + IPA_ECM_IPC_LOGGING(ipa_ecm_logbuf, \ + DRIVER_NAME " %s:%d " fmt, ## args); \ + } \ + } while (0) + +#define ECM_IPA_DEBUG_XMIT(fmt, args...) \ + pr_debug(DRIVER_NAME " %s:%d " fmt, __func__, __LINE__, ## args) + +#define ECM_IPA_INFO(fmt, args...) \ + do { \ + pr_info(DRIVER_NAME "@%s@%d@ctx:%s: "\ + fmt, __func__, __LINE__, current->comm, ## args);\ + if (ipa_ecm_logbuf) { \ + IPA_ECM_IPC_LOGGING(ipa_ecm_logbuf, \ + DRIVER_NAME " %s:%d " fmt, ## args); \ + } \ + } while (0) + +#define ECM_IPA_ERROR(fmt, args...) \ + do { \ + pr_err(DRIVER_NAME "@%s@%d@ctx:%s: "\ + fmt, __func__, __LINE__, current->comm, ## args);\ + if (ipa_ecm_logbuf) { \ + IPA_ECM_IPC_LOGGING(ipa_ecm_logbuf, \ + DRIVER_NAME " %s:%d " fmt, ## args); \ + } \ + } while (0) + +#define NULL_CHECK(ptr) \ + do { \ + if (!(ptr)) { \ + ECM_IPA_ERROR("null pointer #ptr\n"); \ + ret = -EINVAL; \ + } \ + } \ + while (0) + +#define ECM_IPA_LOG_ENTRY() ECM_IPA_DEBUG("begin\n") +#define ECM_IPA_LOG_EXIT() ECM_IPA_DEBUG("end\n") + +#define IPV4_IS_TCP(iph) ((iph)->protocol == IPPROTO_TCP) +#define IPV4_IS_UDP(iph) ((iph)->protocol == IPPROTO_UDP) +#define IPV6_IS_TCP(iph) (((struct ipv6hdr *)iph)->nexthdr == IPPROTO_TCP) +#define IPV6_IS_UDP(iph) (((struct ipv6hdr *)iph)->nexthdr == IPPROTO_UDP) +#define IPV4_DELTA 40 +#define IPV6_DELTA 60 + +static struct qmap_hdr qmap_template_hdr = { + .pad = 0, + .next_hdr = 1,/* Followed by a qmap header extension */ + .cd = 0,/* data */ + .mux_id = 0, + .packet_len_with_pad = 0, + .ext_next_hdr = 0, + .hdr_type = 0x3,/* ulso header type */ + .additional_hdr_size = 0,/* added to hdr_len ep cfg */ + .reserved = 0, + .zero_checksum = 0,/* calculate checksum */ + .ip_id_cfg = 0,/* increment ip id for segments */ + .segment_size = 0,/* max segment size for segmentation */ +}; + +/** + * enum ecm_ipa_state - specify the current driver internal state + * which is guarded by a state machine. + * + * The driver internal state changes due to its external API usage. + * The driver saves its internal state to guard from caller illegal + * call sequence. + * states: + * UNLOADED is the first state which is the default one and is also the state + * after the driver gets unloaded(cleanup). + * INITIALIZED is the driver state once it finished registering + * the network device and all internal data struct were initialized + * CONNECTED is the driver state once the USB pipes were connected to IPA + * UP is the driver state after the interface mode was set to UP but the + * pipes are not connected yet - this state is meta-stable state. + * CONNECTED_AND_UP is the driver state when the pipe were connected and + * the interface got UP request from the network stack. this is the driver + * idle operation state which allows it to transmit/receive data. + * INVALID is a state which is not allowed. + */ +enum ecm_ipa_state { + ECM_IPA_UNLOADED = 0, + ECM_IPA_INITIALIZED, + ECM_IPA_CONNECTED, + ECM_IPA_UP, + ECM_IPA_CONNECTED_AND_UP, + ECM_IPA_INVALID, +}; + +/** + * enum ecm_ipa_operation - enumerations used to describe the API operation + * + * Those enums are used as input for the driver state machine. + */ +enum ecm_ipa_operation { + ECM_IPA_INITIALIZE, + ECM_IPA_CONNECT, + ECM_IPA_OPEN, + ECM_IPA_STOP, + ECM_IPA_DISCONNECT, + ECM_IPA_CLEANUP, +}; + +#define ECM_IPA_STATE_DEBUG(ecm_ipa_ctx) \ + ECM_IPA_DEBUG("Driver state - %s\n",\ + ecm_ipa_state_string((ecm_ipa_ctx)->state)) + +/** + * struct ecm_ipa_dev - main driver context parameters + * @net: network interface struct implemented by this driver + * @directory: debugfs directory for various debuging switches + * @eth_ipv4_hdr_hdl: saved handle for ipv4 header-insertion table + * @eth_ipv6_hdr_hdl: saved handle for ipv6 header-insertion table + * @usb_to_ipa_hdl: save handle for IPA pipe operations + * @ipa_to_usb_hdl: save handle for IPA pipe operations + * @outstanding_pkts: number of packets sent to IPA without TX complete ACKed + * @outstanding_high: number of outstanding packets allowed + * @outstanding_low: number of outstanding packets which shall cause + * to netdev queue start (after stopped due to outstanding_high reached) + * @state: current state of ecm_ipa driver + * @device_ready_notify: callback supplied by USB core driver + * This callback shall be called by the Netdev once the Netdev internal + * state is changed to ECM_IPA_CONNECTED_AND_UP + * @ipa_to_usb_client: consumer client + * @usb_to_ipa_client: producer client + * @pm_hdl: handle for IPA PM + * @is_vlan_mode: does the driver need to work in VLAN mode? + * @netif_rx_function: holds the correct network stack API, needed for NAPI + * @is_ulso_mode: indicator for ulso support + * @empty_hdr_hdl: header handle of empty header + */ +struct ecm_ipa_dev { + struct net_device *net; + struct dentry *directory; + u32 eth_ipv4_hdr_hdl; + u32 eth_ipv6_hdr_hdl; + u32 usb_to_ipa_hdl; + u32 ipa_to_usb_hdl; + atomic_t outstanding_pkts; + u8 outstanding_high; + u8 outstanding_low; + enum ecm_ipa_state state; + void (*device_ready_notify)(void); + enum ipa_client_type ipa_to_usb_client; + enum ipa_client_type usb_to_ipa_client; + u32 pm_hdl; + bool is_vlan_mode; + int (*netif_rx_function)(struct sk_buff *skb); + bool is_ulso_mode; + u32 empty_hdr_hdl; +}; + +static int ecm_ipa_open(struct net_device *net); +static void ecm_ipa_packet_receive_notify + (void *priv, enum ipa_dp_evt_type evt, unsigned long data); +static void ecm_ipa_tx_complete_notify + (void *priv, enum ipa_dp_evt_type evt, unsigned long data); + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 6, 0)) +static void ecm_ipa_tx_timeout(struct net_device *net, + unsigned int txqueue); +#else /* Legacy API. */ +static void ecm_ipa_tx_timeout(struct net_device *net); +#endif + +static int ecm_ipa_stop(struct net_device *net); +static void ecm_ipa_enable_data_path(struct ecm_ipa_dev *ecm_ipa_ctx); +static int ecm_ipa_rules_cfg + (struct ecm_ipa_dev *ecm_ipa_ctx, const void *dst_mac, + const void *src_mac); +static void ecm_ipa_rules_destroy(struct ecm_ipa_dev *ecm_ipa_ctx); +static int ecm_ipa_register_properties(struct ecm_ipa_dev *ecm_ipa_ctx); +static int ecm_ipa_hdrs_hpc_cfg(struct ecm_ipa_dev *ecm_ipa_ctx);; +static void ecm_ipa_deregister_properties(void); +static struct net_device_stats *ecm_ipa_get_stats(struct net_device *net); +static int ecm_ipa_register_pm_client(struct ecm_ipa_dev *ecm_ipa_ctx); +static void ecm_ipa_deregister_pm_client(struct ecm_ipa_dev *ecm_ipa_ctx); +static netdev_tx_t ecm_ipa_start_xmit + (struct sk_buff *skb, struct net_device *net); +static int ecm_ipa_debugfs_atomic_open(struct inode *inode, struct file *file); +static ssize_t ecm_ipa_debugfs_atomic_read + (struct file *file, char __user *ubuf, size_t count, loff_t *ppos); +static void ecm_ipa_debugfs_init(struct ecm_ipa_dev *ecm_ipa_ctx); +static void ecm_ipa_debugfs_destroy(struct ecm_ipa_dev *ecm_ipa_ctx); +static int ecm_ipa_ep_registers_cfg(u32 usb_to_ipa_hdl, u32 ipa_to_usb_hdl, + bool is_vlan_mode); +static int ecm_ipa_set_device_ethernet_addr + (struct net_device *net, u8 device_ethaddr[]); +static enum ecm_ipa_state ecm_ipa_next_state + (enum ecm_ipa_state current_state, enum ecm_ipa_operation operation); +static const char *ecm_ipa_state_string(enum ecm_ipa_state state); +static int ecm_ipa_init_module(void); +static void ecm_ipa_cleanup_module(void); + +static const struct net_device_ops ecm_ipa_netdev_ops = { + .ndo_open = ecm_ipa_open, + .ndo_stop = ecm_ipa_stop, + .ndo_start_xmit = ecm_ipa_start_xmit, + .ndo_set_mac_address = eth_mac_addr, + .ndo_tx_timeout = ecm_ipa_tx_timeout, + .ndo_get_stats = ecm_ipa_get_stats, +}; + +static const struct file_operations ecm_ipa_debugfs_atomic_ops = { + .open = ecm_ipa_debugfs_atomic_open, + .read = ecm_ipa_debugfs_atomic_read, +}; + +static void ecm_ipa_msg_free_cb(void *buff, u32 len, u32 type) +{ + kfree(buff); +} + +/** + * ecm_ipa_init() - create network device and initializes internal + * data structures + * @params: in/out parameters required for ecm_ipa initialization + * + * Shall be called prior to pipe connection. + * The out parameters (the callbacks) shall be supplied to ipa_connect. + * Detailed description: + * - allocate the network device + * - set default values for driver internals + * - create debugfs folder and files + * - add header insertion rules for IPA driver (based on host/device + * Ethernet addresses given in input params) + * - register tx/rx properties to IPA driver (will be later used + * by IPA configuration manager to configure reset of the IPA rules) + * - set the carrier state to "off" (until ecm_ipa_connect is called) + * - register the network device + * - set the out parameters + * + * Returns negative errno, or zero on success + */ +int ecm_ipa_init(struct ecm_ipa_params *params) +{ + int result = 0; + struct net_device *net; + struct ecm_ipa_dev *ecm_ipa_ctx; + int ret; + + ECM_IPA_LOG_ENTRY(); + + ECM_IPA_DEBUG("%s initializing\n", DRIVER_NAME); + ret = 0; + NULL_CHECK(params); + if (ret) + return ret; + + ECM_IPA_DEBUG + ("host_ethaddr=%pM, device_ethaddr=%pM\n", + params->host_ethaddr, + params->device_ethaddr); + + net = alloc_etherdev(sizeof(struct ecm_ipa_dev)); + if (!net) { + result = -ENOMEM; + ECM_IPA_ERROR("fail to allocate etherdev\n"); + goto fail_alloc_etherdev; + } + ECM_IPA_DEBUG("network device was successfully allocated\n"); + + ecm_ipa_ctx = netdev_priv(net); + if (!ecm_ipa_ctx) { + ECM_IPA_ERROR("fail to extract netdev priv\n"); + result = -ENOMEM; + goto fail_netdev_priv; + } + memset(ecm_ipa_ctx, 0, sizeof(*ecm_ipa_ctx)); + ECM_IPA_DEBUG("ecm_ipa_ctx (private) = %pK\n", ecm_ipa_ctx); + + ecm_ipa_ctx->net = net; + ecm_ipa_ctx->outstanding_high = DEFAULT_OUTSTANDING_HIGH; + ecm_ipa_ctx->outstanding_low = DEFAULT_OUTSTANDING_LOW; + atomic_set(&ecm_ipa_ctx->outstanding_pkts, 0); + snprintf(net->name, sizeof(net->name), "%s%%d", "ecm"); + net->netdev_ops = &ecm_ipa_netdev_ops; + net->watchdog_timeo = TX_TIMEOUT; + if (ipa_get_lan_rx_napi()) { + ecm_ipa_ctx->netif_rx_function = netif_receive_skb; + ECM_IPA_DEBUG("LAN RX NAPI enabled = True"); + } else { +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 18, 0)) + ecm_ipa_ctx->netif_rx_function = netif_rx_ni; +#else + ecm_ipa_ctx->netif_rx_function = netif_rx; +#endif + ECM_IPA_DEBUG("LAN RX NAPI enabled = False"); + } + ECM_IPA_DEBUG("internal data structures were initialized\n"); + + if (!params->device_ready_notify) + ECM_IPA_DEBUG("device_ready_notify() was not supplied"); + ecm_ipa_ctx->device_ready_notify = params->device_ready_notify; + + ecm_ipa_debugfs_init(ecm_ipa_ctx); + + result = ecm_ipa_set_device_ethernet_addr + (net, params->device_ethaddr); + if (result) { + ECM_IPA_ERROR("set device MAC failed\n"); + goto fail_set_device_ethernet; + } + ECM_IPA_DEBUG("Device Ethernet address set %pM\n", net->dev_addr); + + if (ipa_is_vlan_mode(IPA_VLAN_IF_ECM, &ecm_ipa_ctx->is_vlan_mode)) { + ECM_IPA_ERROR("couldn't acquire vlan mode, is ipa ready?\n"); + goto fail_get_vlan_mode; + } + ECM_IPA_DEBUG("is vlan mode %d\n", ecm_ipa_ctx->is_vlan_mode); + + ecm_ipa_ctx->is_ulso_mode = ipa3_is_ulso_supported(); + ECM_IPA_DEBUG("is_ulso_mode=%d\n", ecm_ipa_ctx->is_ulso_mode); + + result = ecm_ipa_rules_cfg + (ecm_ipa_ctx, params->host_ethaddr, params->device_ethaddr); + if (result) { + ECM_IPA_ERROR("fail on ipa rules set\n"); + goto fail_rules_cfg; + } + ECM_IPA_DEBUG("Ethernet header insertion set\n"); + + if (ecm_ipa_ctx->is_ulso_mode){ + result = ecm_ipa_hdrs_hpc_cfg(ecm_ipa_ctx); + if (result) { + ECM_IPA_ERROR("fail on ipa hdrs hpc set\n"); + goto fail_hdrs_hpc_add; + } + ECM_IPA_DEBUG("IPA header-insertion configured for ECM\n"); + + ecm_ipa_ctx->net->hw_features = NETIF_F_RXCSUM; + ecm_ipa_ctx->net->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; + ecm_ipa_ctx->net->hw_features |= NETIF_F_SG; + ecm_ipa_ctx->net->hw_features |= NETIF_F_GRO_HW; + ecm_ipa_ctx->net->hw_features |= NETIF_F_GSO_UDP_L4; + ecm_ipa_ctx->net->hw_features |= NETIF_F_ALL_TSO; + ecm_ipa_ctx->net->gso_max_size = ULSO_MAX_SIZE; + } + + netif_carrier_off(net); + ECM_IPA_DEBUG("netif_carrier_off() was called\n"); + + netif_stop_queue(ecm_ipa_ctx->net); + ECM_IPA_DEBUG("netif_stop_queue() was called"); + + result = register_netdev(net); + if (result) { + ECM_IPA_ERROR("register_netdev failed: %d\n", result); + goto fail_register_netdev; + } + ECM_IPA_DEBUG("register_netdev succeeded\n"); + + if (ecm_ipa_ctx->is_vlan_mode) + qmap_template_hdr.additional_hdr_size = + VLAN_ETH_HLEN - ETH_HLEN; + + params->ecm_ipa_rx_dp_notify = ecm_ipa_packet_receive_notify; + params->ecm_ipa_tx_dp_notify = ecm_ipa_tx_complete_notify; + params->private = (void *)ecm_ipa_ctx; + params->skip_ep_cfg = false; + ecm_ipa_ctx->state = ECM_IPA_INITIALIZED; + ECM_IPA_STATE_DEBUG(ecm_ipa_ctx); + + ECM_IPA_INFO("ECM_IPA was initialized successfully\n"); + + ECM_IPA_LOG_EXIT(); + + return 0; + +fail_register_netdev: +if (ecm_ipa_ctx->is_ulso_mode) + ipa_hdrs_hpc_destroy(ecm_ipa_ctx->empty_hdr_hdl); +fail_hdrs_hpc_add: + ecm_ipa_rules_destroy(ecm_ipa_ctx); +fail_rules_cfg: +fail_get_vlan_mode: +fail_set_device_ethernet: + ecm_ipa_debugfs_destroy(ecm_ipa_ctx); +fail_netdev_priv: + free_netdev(net); +fail_alloc_etherdev: + return result; +} +EXPORT_SYMBOL(ecm_ipa_init); + +/** + * ecm_ipa_connect() - notify ecm_ipa for IPA<->USB pipes connection + * @usb_to_ipa_hdl: handle of IPA driver client for USB->IPA + * @ipa_to_usb_hdl: handle of IPA driver client for IPA->USB + * @priv: same value that was set by ecm_ipa_init(), this + * parameter holds the network device pointer. + * + * Once USB driver finishes the pipe connection between IPA core + * and USB core this method shall be called in order to + * allow ecm_ipa complete the data path configurations. + * Caller should make sure that it is calling this function + * from a context that allows it to handle device_ready_notify(). + * Detailed description: + * - configure the IPA end-points register + * - notify the Linux kernel for "carrier_on" + * After this function is done the driver state changes to "Connected". + * This API is expected to be called after ecm_ipa_init() or + * after a call to ecm_ipa_disconnect. + */ +int ecm_ipa_connect(u32 usb_to_ipa_hdl, u32 ipa_to_usb_hdl, void *priv) +{ + struct ecm_ipa_dev *ecm_ipa_ctx = priv; + int next_state; + struct ipa_ecm_msg *ecm_msg; + struct ipa_msg_meta msg_meta; + int retval; + int ret; + + ECM_IPA_LOG_ENTRY(); + ret = 0; + NULL_CHECK(priv); + if (ret) + return ret; + ECM_IPA_DEBUG("usb_to_ipa_hdl = %d, ipa_to_usb_hdl = %d, priv=0x%pK\n", + usb_to_ipa_hdl, ipa_to_usb_hdl, priv); + + next_state = ecm_ipa_next_state(ecm_ipa_ctx->state, ECM_IPA_CONNECT); + if (next_state == ECM_IPA_INVALID) { + ECM_IPA_ERROR("can't call connect before calling initialize\n"); + return -EPERM; + } + ecm_ipa_ctx->state = next_state; + ECM_IPA_STATE_DEBUG(ecm_ipa_ctx); + + if (!ipa3_is_client_handle_valid(usb_to_ipa_hdl)) { + ECM_IPA_ERROR + ("usb_to_ipa_hdl(%d) is not a valid ipa handle\n", + usb_to_ipa_hdl); + return -EINVAL; + } + if (!ipa3_is_client_handle_valid(ipa_to_usb_hdl)) { + ECM_IPA_ERROR + ("ipa_to_usb_hdl(%d) is not a valid ipa handle\n", + ipa_to_usb_hdl); + return -EINVAL; + } + + ecm_ipa_ctx->ipa_to_usb_hdl = ipa_to_usb_hdl; + ecm_ipa_ctx->usb_to_ipa_hdl = usb_to_ipa_hdl; + + ecm_ipa_ctx->ipa_to_usb_client = ipa3_get_client_mapping(ipa_to_usb_hdl); + if (ecm_ipa_ctx->ipa_to_usb_client < 0) { + ECM_IPA_ERROR( + "Error getting IPA->USB client from handle %d\n", + ecm_ipa_ctx->ipa_to_usb_client); + return -EINVAL; + } + ECM_IPA_DEBUG("ipa_to_usb_client = %d\n", + ecm_ipa_ctx->ipa_to_usb_client); + + ecm_ipa_ctx->usb_to_ipa_client = ipa3_get_client_mapping(usb_to_ipa_hdl); + if (ecm_ipa_ctx->usb_to_ipa_client < 0) { + ECM_IPA_ERROR( + "Error getting USB->IPA client from handle %d\n", + ecm_ipa_ctx->usb_to_ipa_client); + return -EINVAL; + } + ECM_IPA_DEBUG("usb_to_ipa_client = %d\n", + ecm_ipa_ctx->usb_to_ipa_client); + + retval = ecm_ipa_register_pm_client(ecm_ipa_ctx); + + if (retval) { + ECM_IPA_ERROR("fail register PM client\n"); + return retval; + } + ECM_IPA_DEBUG("PM client registered\n"); + + retval = ecm_ipa_register_properties(ecm_ipa_ctx); + if (retval) { + ECM_IPA_ERROR("fail on properties set\n"); + goto fail_register_pm; + } + ECM_IPA_DEBUG("ecm_ipa 2 Tx and 2 Rx properties were registered\n"); + + retval = ecm_ipa_ep_registers_cfg(usb_to_ipa_hdl, ipa_to_usb_hdl, + ecm_ipa_ctx->is_vlan_mode); + if (retval) { + ECM_IPA_ERROR("fail on ep cfg\n"); + goto fail; + } + ECM_IPA_DEBUG("end-point configured\n"); + + netif_carrier_on(ecm_ipa_ctx->net); + + ecm_msg = kzalloc(sizeof(*ecm_msg), GFP_KERNEL); + if (!ecm_msg) { + retval = -ENOMEM; + goto fail; + } + + memset(&msg_meta, 0, sizeof(struct ipa_msg_meta)); + msg_meta.msg_type = ECM_CONNECT; + msg_meta.msg_len = sizeof(struct ipa_ecm_msg); + strlcpy(ecm_msg->name, ecm_ipa_ctx->net->name, + IPA_RESOURCE_NAME_MAX); + ecm_msg->ifindex = ecm_ipa_ctx->net->ifindex; + + retval = ipa_send_msg(&msg_meta, ecm_msg, ecm_ipa_msg_free_cb); + if (retval) { + ECM_IPA_ERROR("fail to send ECM_CONNECT message\n"); + kfree(ecm_msg); + goto fail; + } + + if (!netif_carrier_ok(ecm_ipa_ctx->net)) { + ECM_IPA_ERROR("netif_carrier_ok error\n"); + retval = -EBUSY; + goto fail; + } + ECM_IPA_DEBUG("carrier_on notified\n"); + + if (ecm_ipa_ctx->state == ECM_IPA_CONNECTED_AND_UP) + ecm_ipa_enable_data_path(ecm_ipa_ctx); + else + ECM_IPA_DEBUG("data path was not enabled yet\n"); + + ECM_IPA_INFO("ECM_IPA was connected successfully\n"); + + ECM_IPA_LOG_EXIT(); + + return 0; + +fail: + ecm_ipa_deregister_properties(); +fail_register_pm: + ecm_ipa_deregister_pm_client(ecm_ipa_ctx); + return retval; +} +EXPORT_SYMBOL(ecm_ipa_connect); + +/** + * ecm_ipa_open() - notify Linux network stack to start sending packets + * @net: the network interface supplied by the network stack + * + * Linux uses this API to notify the driver that the network interface + * transitions to the up state. + * The driver will instruct the Linux network stack to start + * delivering data packets. + */ +static int ecm_ipa_open(struct net_device *net) +{ + struct ecm_ipa_dev *ecm_ipa_ctx; + int next_state; + + ECM_IPA_LOG_ENTRY(); + + ecm_ipa_ctx = netdev_priv(net); + + next_state = ecm_ipa_next_state(ecm_ipa_ctx->state, ECM_IPA_OPEN); + if (next_state == ECM_IPA_INVALID) { + ECM_IPA_ERROR("can't bring driver up before initialize\n"); + return -EPERM; + } + ecm_ipa_ctx->state = next_state; + ECM_IPA_STATE_DEBUG(ecm_ipa_ctx); + + if (ecm_ipa_ctx->state == ECM_IPA_CONNECTED_AND_UP) + ecm_ipa_enable_data_path(ecm_ipa_ctx); + else + ECM_IPA_DEBUG("data path was not enabled yet\n"); + + ECM_IPA_LOG_EXIT(); + + return 0; +} + +/** + * ecm_ipa_start_xmit() - send data from APPs to USB core via IPA core + * @skb: packet received from Linux network stack + * @net: the network device being used to send this packet + * + * Several conditions needed in order to send the packet to IPA: + * - Transmit queue for the network driver is currently + * in "send" state + * - The driver internal state is in "UP" state. + * - Filter Tx switch is turned off + * - Outstanding high boundary did not reach. + * + * In case all of the above conditions are met, the network driver will + * send the packet by using the IPA API for Tx. + * In case the outstanding packet high boundary is reached, the driver will + * stop the send queue until enough packet were proceeded by the IPA core. + */ +static netdev_tx_t ecm_ipa_start_xmit + (struct sk_buff *skb, struct net_device *net) +{ + int ret; + netdev_tx_t status = NETDEV_TX_BUSY; + struct ecm_ipa_dev *ecm_ipa_ctx = netdev_priv(net); + + netif_trans_update(net); + + ECM_IPA_DEBUG_XMIT + ("Tx, len=%d, skb->protocol=%d, outstanding=%d\n", + skb->len, skb->protocol, + atomic_read(&ecm_ipa_ctx->outstanding_pkts)); + + if (unlikely(netif_queue_stopped(net))) { + ECM_IPA_ERROR("interface queue is stopped\n"); + goto out; + } + + if (unlikely(ecm_ipa_ctx->state != ECM_IPA_CONNECTED_AND_UP)) { + ECM_IPA_ERROR("Missing pipe connected and/or iface up\n"); + return NETDEV_TX_BUSY; + } + + ret = ipa_pm_activate(ecm_ipa_ctx->pm_hdl); + if (ret) { + ECM_IPA_DEBUG("Failed to activate PM client\n"); + netif_stop_queue(net); + goto fail_pm_activate; + } + + if (atomic_read(&ecm_ipa_ctx->outstanding_pkts) >= + ecm_ipa_ctx->outstanding_high) { + ECM_IPA_DEBUG + ("outstanding high (%d)- stopping\n", + ecm_ipa_ctx->outstanding_high); + netif_stop_queue(net); + status = NETDEV_TX_BUSY; + goto out; + } + + if (ecm_ipa_ctx->is_vlan_mode) + if (unlikely(skb->protocol != htons(ETH_P_8021Q))) + ECM_IPA_DEBUG("ether_type != ETH_P_8021Q && vlan, prot = 0x%X\n", + skb->protocol); + + if (ecm_ipa_ctx->is_ulso_mode && + (net->features & (NETIF_F_ALL_TSO | NETIF_F_GSO_UDP_L4))){ + struct iphdr *iph = NULL; + + if (ntohs(skb->protocol) == ETH_P_IP) { + iph = ip_hdr(skb); + if (IPV4_IS_TCP(iph) || IPV4_IS_UDP(iph)) { + skb = qmap_encapsulate_skb(skb, &qmap_template_hdr); + skb_shinfo(skb)->gso_size = + net->mtu - IPV4_DELTA; + } + } else if (ntohs(skb->protocol) == ETH_P_IPV6) { + iph = ip_hdr(skb); + if (IPV6_IS_TCP(iph) || IPV6_IS_UDP(iph)) { + skb = qmap_encapsulate_skb(skb, &qmap_template_hdr); + skb_shinfo(skb)->gso_size = + net->mtu - IPV6_DELTA; + } + } + } + ret = ipa_tx_dp(ecm_ipa_ctx->ipa_to_usb_client, skb, NULL); + if (ret) { + ECM_IPA_ERROR("ipa transmit failed (%d)\n", ret); + goto fail_tx_packet; + } + + atomic_inc(&ecm_ipa_ctx->outstanding_pkts); + + status = NETDEV_TX_OK; + goto out; + +fail_tx_packet: +out: + if (atomic_read(&ecm_ipa_ctx->outstanding_pkts) == 0) + ipa_pm_deferred_deactivate(ecm_ipa_ctx->pm_hdl); +fail_pm_activate: + return status; +} + +/** + * ecm_ipa_packet_receive_notify() - Rx notify + * + * @priv: ecm driver context + * @evt: event type + * @data: data provided with event + * + * IPA will pass a packet to the Linux network stack with skb->data pointing + * to Ethernet packet frame. + */ +static void ecm_ipa_packet_receive_notify + (void *priv, enum ipa_dp_evt_type evt, unsigned long data) +{ + struct sk_buff *skb = (struct sk_buff *)data; + struct ecm_ipa_dev *ecm_ipa_ctx = priv; + unsigned int packet_len; + + if (!skb) { + ECM_IPA_ERROR("Bad SKB received from IPA driver\n"); + return; + } + + packet_len = skb->len; + ECM_IPA_DEBUG("packet RX, len=%d\n", skb->len); + + if (unlikely(ecm_ipa_ctx == NULL)) { + ECM_IPA_DEBUG("Private context is NULL. Drop SKB.\n"); + dev_kfree_skb_any(skb); + return; + } + + if (unlikely(ecm_ipa_ctx->state != ECM_IPA_CONNECTED_AND_UP)) { + ECM_IPA_DEBUG("Missing pipe connected and/or iface up\n"); + dev_kfree_skb_any(skb); + return; + } + + if (unlikely(evt != IPA_RECEIVE)) { + ECM_IPA_ERROR("A none IPA_RECEIVE event in ecm_ipa_receive\n"); + dev_kfree_skb_any(skb); + return; + } + + skb->dev = ecm_ipa_ctx->net; + skb->protocol = eth_type_trans(skb, ecm_ipa_ctx->net); + + ecm_ipa_ctx->netif_rx_function(skb); + + ecm_ipa_ctx->net->stats.rx_packets++; + ecm_ipa_ctx->net->stats.rx_bytes += packet_len; +} + +/** ecm_ipa_stop() - called when network device transitions to the down + * state. + * @net: the network device being stopped. + * + * This API is used by Linux network stack to notify the network driver that + * its state was changed to "down" + * The driver will stop the "send" queue and change its internal + * state to "Connected". + */ +static int ecm_ipa_stop(struct net_device *net) +{ + struct ecm_ipa_dev *ecm_ipa_ctx = netdev_priv(net); + int next_state; + + ECM_IPA_LOG_ENTRY(); + + next_state = ecm_ipa_next_state(ecm_ipa_ctx->state, ECM_IPA_STOP); + if (next_state == ECM_IPA_INVALID) { + ECM_IPA_ERROR("can't do network interface down without up\n"); + return -EPERM; + } + ecm_ipa_ctx->state = next_state; + ECM_IPA_STATE_DEBUG(ecm_ipa_ctx); + + netif_stop_queue(net); + ECM_IPA_DEBUG("network device stopped\n"); + + ECM_IPA_LOG_EXIT(); + return 0; +} + +/** ecm_ipa_disconnect() - called when the USB cable is unplugged. + * @priv: same value that was set by ecm_ipa_init(), this + * parameter holds the network device pointer. + * + * Once the USB cable is unplugged the USB driver will notify the network + * interface driver. + * The internal driver state will returned to its initialized state and + * Linux network stack will be informed for carrier off and the send queue + * will be stopped. + */ +int ecm_ipa_disconnect(void *priv) +{ + struct ecm_ipa_dev *ecm_ipa_ctx = priv; + int next_state; + struct ipa_ecm_msg *ecm_msg; + struct ipa_msg_meta msg_meta; + int retval; + int outstanding_dropped_pkts; + int ret; + + ECM_IPA_LOG_ENTRY(); + ret = 0; + NULL_CHECK(ecm_ipa_ctx); + if (ret) + return ret; + ECM_IPA_DEBUG("priv=0x%pK\n", priv); + + next_state = ecm_ipa_next_state(ecm_ipa_ctx->state, ECM_IPA_DISCONNECT); + if (next_state == ECM_IPA_INVALID) { + ECM_IPA_ERROR("can't disconnect before connect\n"); + return -EPERM; + } + ecm_ipa_ctx->state = next_state; + ECM_IPA_STATE_DEBUG(ecm_ipa_ctx); + + netif_carrier_off(ecm_ipa_ctx->net); + ECM_IPA_DEBUG("carrier_off notifcation was sent\n"); + + ecm_msg = kzalloc(sizeof(*ecm_msg), GFP_KERNEL); + if (!ecm_msg) + return -ENOMEM; + + memset(&msg_meta, 0, sizeof(struct ipa_msg_meta)); + msg_meta.msg_type = ECM_DISCONNECT; + msg_meta.msg_len = sizeof(struct ipa_ecm_msg); + strlcpy(ecm_msg->name, ecm_ipa_ctx->net->name, + IPA_RESOURCE_NAME_MAX); + ecm_msg->ifindex = ecm_ipa_ctx->net->ifindex; + + retval = ipa_send_msg(&msg_meta, ecm_msg, ecm_ipa_msg_free_cb); + if (retval) { + ECM_IPA_ERROR("fail to send ECM_DISCONNECT message\n"); + kfree(ecm_msg); + return -EPERM; + } + + netif_stop_queue(ecm_ipa_ctx->net); + ECM_IPA_DEBUG("queue stopped\n"); + + ecm_ipa_deregister_pm_client(ecm_ipa_ctx); + + outstanding_dropped_pkts = + atomic_read(&ecm_ipa_ctx->outstanding_pkts); + ecm_ipa_ctx->net->stats.tx_errors += outstanding_dropped_pkts; + atomic_set(&ecm_ipa_ctx->outstanding_pkts, 0); + + ECM_IPA_INFO("ECM_IPA was disconnected successfully\n"); + + ECM_IPA_LOG_EXIT(); + + return 0; +} +EXPORT_SYMBOL(ecm_ipa_disconnect); + +/** + * ecm_ipa_cleanup() - unregister the network interface driver and free + * internal data structs. + * @priv: same value that was set by ecm_ipa_init(), this + * parameter holds the network device pointer. + * + * This function shall be called once the network interface is not + * needed anymore, e.g: when the USB composition does not support ECM. + * This function shall be called after the pipes were disconnected. + * Detailed description: + * - remove the debugfs entries + * - deregister the network interface from Linux network stack + * - free all internal data structs + */ +void ecm_ipa_cleanup(void *priv) +{ + struct ecm_ipa_dev *ecm_ipa_ctx = priv; + int next_state; + + ECM_IPA_LOG_ENTRY(); + + ECM_IPA_DEBUG("priv=0x%pK\n", priv); + + if (!ecm_ipa_ctx) { + ECM_IPA_ERROR("ecm_ipa_ctx NULL pointer\n"); + return; + } + + next_state = ecm_ipa_next_state(ecm_ipa_ctx->state, ECM_IPA_CLEANUP); + if (next_state == ECM_IPA_INVALID) { + ECM_IPA_ERROR("can't clean driver without cable disconnect\n"); + return; + } + ecm_ipa_ctx->state = next_state; + ECM_IPA_STATE_DEBUG(ecm_ipa_ctx); + + if (ecm_ipa_ctx->is_ulso_mode) + ipa_hdrs_hpc_destroy(ecm_ipa_ctx->empty_hdr_hdl); + + ecm_ipa_rules_destroy(ecm_ipa_ctx); + ecm_ipa_debugfs_destroy(ecm_ipa_ctx); + + unregister_netdev(ecm_ipa_ctx->net); + free_netdev(ecm_ipa_ctx->net); + + ECM_IPA_INFO("ECM_IPA was destroyed successfully\n"); + + ECM_IPA_LOG_EXIT(); +} +EXPORT_SYMBOL(ecm_ipa_cleanup); + +static void ecm_ipa_enable_data_path(struct ecm_ipa_dev *ecm_ipa_ctx) +{ + if (ecm_ipa_ctx->device_ready_notify) { + ecm_ipa_ctx->device_ready_notify(); + ECM_IPA_DEBUG("USB device_ready_notify() was called\n"); + } else { + ECM_IPA_DEBUG("device_ready_notify() not supplied\n"); + } + + qmap_template_hdr.segment_size = htons(ecm_ipa_ctx->net->mtu - + sizeof(qmap_template_hdr)); + + netif_start_queue(ecm_ipa_ctx->net); + ECM_IPA_DEBUG("queue started\n"); +} + +static void ecm_ipa_prepare_header_insertion( + int eth_type, + const char *hdr_name, struct ipa_hdr_add *add_hdr, + const void *dst_mac, const void *src_mac, bool is_vlan_mode) +{ + struct ethhdr *eth_hdr; + struct vlan_ethhdr *eth_vlan_hdr; + + ECM_IPA_LOG_ENTRY(); + + add_hdr->is_partial = 0; + strlcpy(add_hdr->name, hdr_name, IPA_RESOURCE_NAME_MAX); + add_hdr->is_eth2_ofst_valid = true; + add_hdr->eth2_ofst = 0; + + if (is_vlan_mode) { + eth_vlan_hdr = (struct vlan_ethhdr *)add_hdr->hdr; + memcpy(eth_vlan_hdr->h_dest, dst_mac, ETH_ALEN); + memcpy(eth_vlan_hdr->h_source, src_mac, ETH_ALEN); + eth_vlan_hdr->h_vlan_encapsulated_proto = + htons(eth_type); + eth_vlan_hdr->h_vlan_proto = htons(ETH_P_8021Q); + add_hdr->hdr_len = VLAN_ETH_HLEN; + add_hdr->type = IPA_HDR_L2_802_1Q; + } else { + eth_hdr = (struct ethhdr *)add_hdr->hdr; + memcpy(eth_hdr->h_dest, dst_mac, ETH_ALEN); + memcpy(eth_hdr->h_source, src_mac, ETH_ALEN); + eth_hdr->h_proto = htons(eth_type); + add_hdr->hdr_len = ETH_HLEN; + add_hdr->type = IPA_HDR_L2_ETHERNET_II; + } + ECM_IPA_LOG_EXIT(); +} + +static int ecm_ipa_hdrs_hpc_cfg(struct ecm_ipa_dev *ecm_ipa_ctx) +{ + struct ipa_ioc_add_hdr *hdrs; + struct ipa_hdr_add *empty_hdr; + struct ipa_pkt_init_ex_hdr_ofst_set lookup; + int result = 0; + + ECM_IPA_LOG_ENTRY(); + + hdrs = kzalloc(sizeof(*hdrs) + sizeof(*empty_hdr), GFP_KERNEL); + if (!hdrs) { + result = -ENOMEM; + goto fail_mem; + } + empty_hdr = &hdrs->hdr[0]; + strlcpy(empty_hdr->name, EMPTY_HDR_NAME, sizeof(empty_hdr->name)); + empty_hdr->hdr_len = 0; + empty_hdr->hdr_hdl = -1; + empty_hdr->is_partial = false; + empty_hdr->status = -1; + hdrs->num_hdrs = 1; + hdrs->commit = 1; + + result = ipa3_add_hdr_hpc(hdrs); + if (result) { + ECM_IPA_ERROR("Fail on Header-Insertion(%d)\n", result); + goto fail_add_hdr; + } + if (empty_hdr->status) { + ECM_IPA_ERROR("Fail on Header-Insertion ecm(%d)\n", + empty_hdr->status); + result = empty_hdr->status; + goto fail_add_hdr; + } + + ecm_ipa_ctx->empty_hdr_hdl = empty_hdr->hdr_hdl; + lookup.ep = IPA_CLIENT_USB_CONS; + strlcpy(lookup.name, EMPTY_HDR_NAME, sizeof(lookup.name)); + if (ipa_set_pkt_init_ex_hdr_ofst(&lookup, true)) + goto fail_add_hdr; + + ECM_IPA_LOG_EXIT(); + +fail_add_hdr: + kfree(hdrs); +fail_mem: + return result; +} + +/** + * ecm_ipa_rules_cfg() - set header insertion and register Tx/Rx properties + * Headers will be committed to HW + * @ecm_ipa_ctx: main driver context parameters + * @dst_mac: destination MAC address + * @src_mac: source MAC address + * + * Returns negative errno, or zero on success + */ +static int ecm_ipa_rules_cfg(struct ecm_ipa_dev *ecm_ipa_ctx, + const void *dst_mac, const void *src_mac) +{ + struct ipa_ioc_add_hdr *hdrs; + struct ipa_hdr_add *ipv4_hdr; + struct ipa_hdr_add *ipv6_hdr; + int result = 0; + + ECM_IPA_LOG_ENTRY(); + hdrs = kzalloc(sizeof(*hdrs) + sizeof(*ipv4_hdr) + sizeof(*ipv6_hdr), + GFP_KERNEL); + if (!hdrs) { + result = -ENOMEM; + goto out; + } + + ipv4_hdr = &hdrs->hdr[0]; + ecm_ipa_prepare_header_insertion(ETH_P_IP, ECM_IPA_IPV4_HDR_NAME, + ipv4_hdr, dst_mac, src_mac, ecm_ipa_ctx->is_vlan_mode); + + ipv6_hdr = &hdrs->hdr[1]; + ecm_ipa_prepare_header_insertion(ETH_P_IPV6, ECM_IPA_IPV6_HDR_NAME, + ipv6_hdr, dst_mac, src_mac, ecm_ipa_ctx->is_vlan_mode); + + hdrs->commit = 1; + hdrs->num_hdrs = 2; + result = ipa_add_hdr(hdrs); + if (result) { + ECM_IPA_ERROR("Fail on Header-Insertion(%d)\n", result); + goto out_free_mem; + } + if (ipv4_hdr->status) { + ECM_IPA_ERROR("Fail on Header-Insertion ipv4(%d)\n", + ipv4_hdr->status); + result = ipv4_hdr->status; + goto out_free_mem; + } + if (ipv6_hdr->status) { + ECM_IPA_ERROR("Fail on Header-Insertion ipv6(%d)\n", + ipv6_hdr->status); + result = ipv6_hdr->status; + goto out_free_mem; + } + ecm_ipa_ctx->eth_ipv4_hdr_hdl = ipv4_hdr->hdr_hdl; + ecm_ipa_ctx->eth_ipv6_hdr_hdl = ipv6_hdr->hdr_hdl; + + ECM_IPA_LOG_EXIT(); +out_free_mem: + kfree(hdrs); +out: + return result; +} + +/** + * ecm_ipa_rules_destroy() - remove the IPA core configuration done for + * the driver data path. + * @ecm_ipa_ctx: the driver context + * + * Revert the work done on ecm_ipa_rules_cfg. + */ +static void ecm_ipa_rules_destroy(struct ecm_ipa_dev *ecm_ipa_ctx) +{ + struct ipa_ioc_del_hdr *del_hdr; + struct ipa_hdr_del *ipv4; + struct ipa_hdr_del *ipv6; + int result; + + del_hdr = kzalloc(sizeof(*del_hdr) + sizeof(*ipv4) + sizeof(*ipv6), + GFP_KERNEL); + if (!del_hdr) + return; + + del_hdr->commit = 1; + del_hdr->num_hdls = 2; + ipv4 = &del_hdr->hdl[0]; + ipv4->hdl = ecm_ipa_ctx->eth_ipv4_hdr_hdl; + ipv6 = &del_hdr->hdl[1]; + ipv6->hdl = ecm_ipa_ctx->eth_ipv6_hdr_hdl; + + result = ipa_del_hdr(del_hdr); + if (result || ipv4->status || ipv6->status) + ECM_IPA_ERROR("ipa_del_hdr failed\n"); + kfree(del_hdr); +} + +/* ecm_ipa_register_properties() - set Tx/Rx properties for ipacm + * + * Register ecm0 interface with 2 Tx properties and 2 Rx properties: + * The 2 Tx properties are for data flowing from IPA to USB, they + * have Header-Insertion properties both for Ipv4 and Ipv6 Ethernet framing. + * The 2 Rx properties are for data flowing from USB to IPA, they have + * simple rule which always "hit". + * + */ +static int ecm_ipa_register_properties(struct ecm_ipa_dev *ecm_ipa_ctx) +{ + struct ipa_tx_intf tx_properties = {0}; + struct ipa_ioc_tx_intf_prop properties[2] = { {0}, {0} }; + struct ipa_ioc_tx_intf_prop *ipv4_property; + struct ipa_ioc_tx_intf_prop *ipv6_property; + struct ipa_ioc_rx_intf_prop rx_ioc_properties[2] = { {0}, {0} }; + struct ipa_rx_intf rx_properties = {0}; + struct ipa_ioc_rx_intf_prop *rx_ipv4_property; + struct ipa_ioc_rx_intf_prop *rx_ipv6_property; + enum ipa_hdr_l2_type hdr_l2_type = IPA_HDR_L2_ETHERNET_II; + int result = 0; + + ECM_IPA_LOG_ENTRY(); + + if (ecm_ipa_ctx->is_vlan_mode) + hdr_l2_type = IPA_HDR_L2_802_1Q; + + tx_properties.prop = properties; + ipv4_property = &tx_properties.prop[0]; + ipv4_property->ip = IPA_IP_v4; + ipv4_property->dst_pipe = ecm_ipa_ctx->ipa_to_usb_client; + strlcpy + (ipv4_property->hdr_name, ECM_IPA_IPV4_HDR_NAME, + IPA_RESOURCE_NAME_MAX); + ipv4_property->hdr_l2_type = hdr_l2_type; + ipv6_property = &tx_properties.prop[1]; + ipv6_property->ip = IPA_IP_v6; + ipv6_property->dst_pipe = ecm_ipa_ctx->ipa_to_usb_client; + ipv6_property->hdr_l2_type = hdr_l2_type; + strlcpy + (ipv6_property->hdr_name, ECM_IPA_IPV6_HDR_NAME, + IPA_RESOURCE_NAME_MAX); + tx_properties.num_props = 2; + + rx_properties.prop = rx_ioc_properties; + rx_ipv4_property = &rx_properties.prop[0]; + rx_ipv4_property->ip = IPA_IP_v4; + rx_ipv4_property->attrib.attrib_mask = 0; + rx_ipv4_property->src_pipe = ecm_ipa_ctx->usb_to_ipa_client; + rx_ipv4_property->hdr_l2_type = hdr_l2_type; + rx_ipv6_property = &rx_properties.prop[1]; + rx_ipv6_property->ip = IPA_IP_v6; + rx_ipv6_property->attrib.attrib_mask = 0; + rx_ipv6_property->src_pipe = ecm_ipa_ctx->usb_to_ipa_client; + rx_ipv6_property->hdr_l2_type = hdr_l2_type; + rx_properties.num_props = 2; + + result = ipa_register_intf("ecm0", &tx_properties, &rx_properties); + if (result) + ECM_IPA_ERROR("fail on Tx/Rx properties registration\n"); + + ECM_IPA_LOG_EXIT(); + + return result; +} + +static void ecm_ipa_deregister_properties(void) +{ + int result; + + ECM_IPA_LOG_ENTRY(); + result = ipa_deregister_intf("ecm0"); + if (result) + ECM_IPA_DEBUG("Fail on Tx prop deregister\n"); + ECM_IPA_LOG_EXIT(); +} + +/** + * ecm_ipa_configure() - make IPA core end-point specific configuration + * @usb_to_ipa_hdl: handle of usb_to_ipa end-point for IPA driver + * @ipa_to_usb_hdl: handle of ipa_to_usb end-point for IPA driver + * @host_ethaddr: host Ethernet address in network order + * @device_ethaddr: device Ethernet address in network order + * + * Configure the usb_to_ipa and ipa_to_usb end-point registers + * - USB->IPA end-point: disable de-aggregation, enable link layer + * header removal (Ethernet removal), source NATing and default routing. + * - IPA->USB end-point: disable aggregation, add link layer header (Ethernet) + * - allocate Ethernet device + * - register to Linux network stack + * + * Returns negative errno, or zero on success + */ + +static struct net_device_stats *ecm_ipa_get_stats(struct net_device *net) +{ + return &net->stats; +} + +static void ecm_ipa_pm_cb(void *p, enum ipa_pm_cb_event event) +{ + struct ecm_ipa_dev *ecm_ipa_ctx = p; + + ECM_IPA_LOG_ENTRY(); + if (event != IPA_PM_CLIENT_ACTIVATED) { + ECM_IPA_ERROR("unexpected event %d\n", event); + WARN_ON(1); + return; + } + + if (netif_queue_stopped(ecm_ipa_ctx->net)) { + ECM_IPA_DEBUG("Resource Granted - starting queue\n"); + netif_start_queue(ecm_ipa_ctx->net); + } + ECM_IPA_LOG_EXIT(); +} + +static int ecm_ipa_register_pm_client(struct ecm_ipa_dev *ecm_ipa_ctx) +{ + int result; + struct ipa_pm_register_params pm_reg; + + memset(&pm_reg, 0, sizeof(pm_reg)); + pm_reg.name = ecm_ipa_ctx->net->name; + pm_reg.user_data = ecm_ipa_ctx; + pm_reg.callback = ecm_ipa_pm_cb; + pm_reg.group = IPA_PM_GROUP_APPS; + result = ipa_pm_register(&pm_reg, &ecm_ipa_ctx->pm_hdl); + if (result) { + ECM_IPA_ERROR("failed to create IPA PM client %d\n", result); + return result; + } + return 0; +} + +static void ecm_ipa_deregister_pm_client(struct ecm_ipa_dev *ecm_ipa_ctx) +{ + ipa_pm_deactivate_sync(ecm_ipa_ctx->pm_hdl); + ipa_pm_deregister(ecm_ipa_ctx->pm_hdl); + ecm_ipa_ctx->pm_hdl = ~0; +} + +/** + * ecm_ipa_tx_complete_notify() - Rx notify + * + * @priv: ecm driver context + * @evt: event type + * @data: data provided with event + * + * Check that the packet is the one we sent and release it + * This function will be called in defered context in IPA wq. + */ +static void ecm_ipa_tx_complete_notify + (void *priv, + enum ipa_dp_evt_type evt, + unsigned long data) +{ + struct sk_buff *skb = (struct sk_buff *)data; + struct ecm_ipa_dev *ecm_ipa_ctx = priv; + + if (!skb) { + ECM_IPA_ERROR("Bad SKB received from IPA driver\n"); + return; + } + + if (!ecm_ipa_ctx) { + ECM_IPA_ERROR("ecm_ipa_ctx is NULL pointer\n"); + return; + } + + ECM_IPA_DEBUG + ("Tx-complete, len=%d, skb->prot=%d, outstanding=%d\n", + skb->len, skb->protocol, + atomic_read(&ecm_ipa_ctx->outstanding_pkts)); + + if (evt != IPA_WRITE_DONE) { + ECM_IPA_ERROR("unsupported event on Tx callback\n"); + return; + } + + if (unlikely(ecm_ipa_ctx->state != ECM_IPA_CONNECTED_AND_UP)) { + ECM_IPA_DEBUG + ("dropping Tx-complete pkt, state=%s", + ecm_ipa_state_string(ecm_ipa_ctx->state)); + goto out; + } + + ecm_ipa_ctx->net->stats.tx_packets++; + ecm_ipa_ctx->net->stats.tx_bytes += skb->len; + + if (atomic_read(&ecm_ipa_ctx->outstanding_pkts) > 0) + atomic_dec(&ecm_ipa_ctx->outstanding_pkts); + + if + (netif_queue_stopped(ecm_ipa_ctx->net) && + netif_carrier_ok(ecm_ipa_ctx->net) && + atomic_read(&ecm_ipa_ctx->outstanding_pkts) + < (ecm_ipa_ctx->outstanding_low)) { + ECM_IPA_DEBUG + ("outstanding low (%d) - waking up queue\n", + ecm_ipa_ctx->outstanding_low); + netif_wake_queue(ecm_ipa_ctx->net); + } + + if (atomic_read(&ecm_ipa_ctx->outstanding_pkts) == 0) + ipa_pm_deferred_deactivate(ecm_ipa_ctx->pm_hdl); +out: + dev_kfree_skb_any(skb); +} + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 6, 0)) +static void ecm_ipa_tx_timeout(struct net_device *net, + unsigned int txqueue) +#else /* Legacy API */ +static void ecm_ipa_tx_timeout(struct net_device *net) +#endif +{ + struct ecm_ipa_dev *ecm_ipa_ctx = netdev_priv(net); + + ECM_IPA_ERROR + ("possible IPA stall was detected, %d outstanding", + atomic_read(&ecm_ipa_ctx->outstanding_pkts)); + + net->stats.tx_errors++; +} + +static int ecm_ipa_debugfs_atomic_open(struct inode *inode, struct file *file) +{ + struct ecm_ipa_dev *ecm_ipa_ctx = inode->i_private; + + ECM_IPA_LOG_ENTRY(); + file->private_data = &ecm_ipa_ctx->outstanding_pkts; + ECM_IPA_LOG_EXIT(); + return 0; +} + +static ssize_t ecm_ipa_debugfs_atomic_read + (struct file *file, char __user *ubuf, size_t count, loff_t *ppos) +{ + int nbytes; + u8 atomic_str[DEBUGFS_TEMP_BUF_SIZE] = {0}; + atomic_t *atomic_var = file->private_data; + + nbytes = scnprintf + (atomic_str, sizeof(atomic_str), "%d\n", + atomic_read(atomic_var)); + return simple_read_from_buffer(ubuf, count, ppos, atomic_str, nbytes); +} + +#ifdef CONFIG_DEBUG_FS + +static void ecm_ipa_debugfs_init(struct ecm_ipa_dev *ecm_ipa_ctx) +{ + const mode_t flags_read_write = 0666; + const mode_t flags_read_only = 0444; + struct dentry *file; + + ECM_IPA_LOG_ENTRY(); + + if (!ecm_ipa_ctx) + return; + + ecm_ipa_ctx->directory = debugfs_create_dir("ecm_ipa", NULL); + if (!ecm_ipa_ctx->directory) { + ECM_IPA_ERROR("could not create debugfs directory entry\n"); + goto fail_directory; + } + debugfs_create_u8 + ("outstanding_high", flags_read_write, + ecm_ipa_ctx->directory, &ecm_ipa_ctx->outstanding_high); + debugfs_create_u8 + ("outstanding_low", flags_read_write, + ecm_ipa_ctx->directory, &ecm_ipa_ctx->outstanding_low); + file = debugfs_create_file + ("outstanding", flags_read_only, + ecm_ipa_ctx->directory, + ecm_ipa_ctx, &ecm_ipa_debugfs_atomic_ops); + if (!file) { + ECM_IPA_ERROR("could not create outstanding file\n"); + goto fail_file; + } + + file = debugfs_create_bool("is_vlan_mode", flags_read_only, + ecm_ipa_ctx->directory, &ecm_ipa_ctx->is_vlan_mode); + if (!file) { + ECM_IPA_ERROR("could not create is_vlan_mode file\n"); + goto fail_file; + } + + ECM_IPA_DEBUG("debugfs entries were created\n"); + ECM_IPA_LOG_EXIT(); + + return; +fail_file: + debugfs_remove_recursive(ecm_ipa_ctx->directory); +fail_directory: + return; +} + +static void ecm_ipa_debugfs_destroy(struct ecm_ipa_dev *ecm_ipa_ctx) +{ + debugfs_remove_recursive(ecm_ipa_ctx->directory); +} + +#else /* !CONFIG_DEBUG_FS*/ + +static void ecm_ipa_debugfs_init(struct ecm_ipa_dev *ecm_ipa_ctx) {} + +static void ecm_ipa_debugfs_destroy(struct ecm_ipa_dev *ecm_ipa_ctx) {} + +#endif /* CONFIG_DEBUG_FS */ + +/** + * ecm_ipa_ep_cfg() - configure the USB endpoints for ECM + * + * @usb_to_ipa_hdl: handle received from ipa_connect + * @ipa_to_usb_hdl: handle received from ipa_connect + * @is_vlan_mode - should driver work in vlan mode? + * + * USB to IPA pipe: + * - No de-aggregation + * - Remove Ethernet header + * - SRC NAT + * - Default routing(0) + * IPA to USB Pipe: + * - No aggregation + * - Add Ethernet header + */ +static int ecm_ipa_ep_registers_cfg(u32 usb_to_ipa_hdl, u32 ipa_to_usb_hdl, + bool is_vlan_mode) +{ + int result = 0; + struct ipa_ep_cfg usb_to_ipa_ep_cfg; + struct ipa_ep_cfg ipa_to_usb_ep_cfg; + uint8_t hdr_add = 0; + + + ECM_IPA_LOG_ENTRY(); + if (is_vlan_mode) + hdr_add = VLAN_HLEN; + memset(&usb_to_ipa_ep_cfg, 0, sizeof(struct ipa_ep_cfg)); + usb_to_ipa_ep_cfg.aggr.aggr_en = IPA_BYPASS_AGGR; + usb_to_ipa_ep_cfg.hdr.hdr_len = ETH_HLEN + hdr_add; + usb_to_ipa_ep_cfg.nat.nat_en = IPA_SRC_NAT; + usb_to_ipa_ep_cfg.route.rt_tbl_hdl = 0; + usb_to_ipa_ep_cfg.mode.dst = IPA_CLIENT_A5_LAN_WAN_CONS; + usb_to_ipa_ep_cfg.mode.mode = IPA_BASIC; + + /* enable hdr_metadata_reg_valid */ + usb_to_ipa_ep_cfg.hdr.hdr_metadata_reg_valid = true; + /*xlat config in vlan mode */ + if (is_vlan_mode) { + usb_to_ipa_ep_cfg.hdr.hdr_ofst_metadata_valid = 1; + usb_to_ipa_ep_cfg.hdr.hdr_ofst_metadata = ETH_HLEN; + usb_to_ipa_ep_cfg.hdr.hdr_metadata_reg_valid = false; + qmap_template_hdr.additional_hdr_size = + VLAN_ETH_HLEN - ETH_HLEN; + } + + result = ipa3_cfg_ep(usb_to_ipa_hdl, &usb_to_ipa_ep_cfg); + if (result) { + ECM_IPA_ERROR("failed to configure USB to IPA point\n"); + goto out; + } + memset(&ipa_to_usb_ep_cfg, 0, sizeof(struct ipa_ep_cfg)); + ipa_to_usb_ep_cfg.aggr.aggr_en = IPA_BYPASS_AGGR; + ipa_to_usb_ep_cfg.hdr.hdr_len = ETH_HLEN + hdr_add; + ipa_to_usb_ep_cfg.nat.nat_en = IPA_BYPASS_NAT; + ipa_to_usb_ep_cfg.ulso.is_ulso_pipe = ipa3_is_ulso_supported(); + result = ipa3_cfg_ep(ipa_to_usb_hdl, &ipa_to_usb_ep_cfg); + if (result) { + ECM_IPA_ERROR("failed to configure IPA to USB end-point\n"); + goto out; + } + ECM_IPA_DEBUG("end-point registers successfully configured\n"); +out: + ECM_IPA_LOG_EXIT(); + return result; +} + +/** + * ecm_ipa_set_device_ethernet_addr() - set device etherenet address + * @dev_ethaddr: device etherenet address + * + * Returns 0 for success, negative otherwise + */ +static int ecm_ipa_set_device_ethernet_addr + (struct net_device *net, u8 device_ethaddr[]) +{ + if (!is_valid_ether_addr(device_ethaddr)) + return -EINVAL; + +#if (LINUX_VERSION_CODE > KERNEL_VERSION(5, 15, 0)) + net->addr_len = ETH_ALEN; + dev_addr_set(net, device_ethaddr); +#else + memcpy((u8 *)net->dev_addr, device_ethaddr, ETH_ALEN); + ECM_IPA_DEBUG("device ethernet address: %pM\n", (u8 *)net->dev_addr); +#endif + return 0; +} + +/** ecm_ipa_next_state - return the next state of the driver + * @current_state: the current state of the driver + * @operation: an enum which represent the operation being made on the driver + * by its API. + * + * This function implements the driver internal state machine. + * Its decisions are based on the driver current state and the operation + * being made. + * In case the operation is invalid this state machine will return + * the value ECM_IPA_INVALID to inform the caller for a forbidden sequence. + */ +static enum ecm_ipa_state ecm_ipa_next_state + (enum ecm_ipa_state current_state, enum ecm_ipa_operation operation) +{ + int next_state = ECM_IPA_INVALID; + + switch (current_state) { + case ECM_IPA_UNLOADED: + if (operation == ECM_IPA_INITIALIZE) + next_state = ECM_IPA_INITIALIZED; + break; + case ECM_IPA_INITIALIZED: + if (operation == ECM_IPA_CONNECT) + next_state = ECM_IPA_CONNECTED; + else if (operation == ECM_IPA_OPEN) + next_state = ECM_IPA_UP; + else if (operation == ECM_IPA_CLEANUP) + next_state = ECM_IPA_UNLOADED; + break; + case ECM_IPA_CONNECTED: + if (operation == ECM_IPA_DISCONNECT) + next_state = ECM_IPA_INITIALIZED; + else if (operation == ECM_IPA_OPEN) + next_state = ECM_IPA_CONNECTED_AND_UP; + break; + case ECM_IPA_UP: + if (operation == ECM_IPA_STOP) + next_state = ECM_IPA_INITIALIZED; + else if (operation == ECM_IPA_CONNECT) + next_state = ECM_IPA_CONNECTED_AND_UP; + else if (operation == ECM_IPA_CLEANUP) + next_state = ECM_IPA_UNLOADED; + break; + case ECM_IPA_CONNECTED_AND_UP: + if (operation == ECM_IPA_STOP) + next_state = ECM_IPA_CONNECTED; + else if (operation == ECM_IPA_DISCONNECT) + next_state = ECM_IPA_UP; + break; + default: + ECM_IPA_ERROR("State is not supported\n"); + break; + } + + ECM_IPA_DEBUG + ("state transition ( %s -> %s )- %s\n", + ecm_ipa_state_string(current_state), + ecm_ipa_state_string(next_state), + next_state == ECM_IPA_INVALID ? "Forbidden" : "Allowed"); + + return next_state; +} + +/** + * ecm_ipa_state_string - return the state string representation + * @state: enum which describe the state + */ +static const char *ecm_ipa_state_string(enum ecm_ipa_state state) +{ + switch (state) { + case ECM_IPA_UNLOADED: + return "ECM_IPA_UNLOADED"; + case ECM_IPA_INITIALIZED: + return "ECM_IPA_INITIALIZED"; + case ECM_IPA_CONNECTED: + return "ECM_IPA_CONNECTED"; + case ECM_IPA_UP: + return "ECM_IPA_UP"; + case ECM_IPA_CONNECTED_AND_UP: + return "ECM_IPA_CONNECTED_AND_UP"; + default: + return "Not supported"; + } +} + +/** + * ecm_ipa_init_module() - module initialization + * + */ +static int __init ecm_ipa_init_module(void) +{ + ECM_IPA_LOG_ENTRY(); + pr_info("ecm driver init\n"); + ipa_ecm_logbuf = ipc_log_context_create(IPA_ECM_IPC_LOG_PAGES, + "ipa_ecm", MINIDUMP_MASK); + if (ipa_ecm_logbuf == NULL) + ECM_IPA_DEBUG("failed to create IPC log, continue...\n"); + ECM_IPA_LOG_EXIT(); + return 0; +} + +/** + * ecm_ipa_cleanup_module() - module cleanup + * + */ +static void __exit ecm_ipa_cleanup_module(void) +{ + ECM_IPA_LOG_ENTRY(); + if (ipa_ecm_logbuf) + ipc_log_context_destroy(ipa_ecm_logbuf); + ipa_ecm_logbuf = NULL; + ECM_IPA_LOG_EXIT(); +} + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("ECM IPA network interface"); + +late_initcall(ecm_ipa_init_module); +module_exit(ecm_ipa_cleanup_module); diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_clients/ecm_ipa.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_clients/ecm_ipa.h new file mode 100644 index 0000000000..8bf2055d90 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_clients/ecm_ipa.h @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2013-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _ECM_IPA_H_ +#define _ECM_IPA_H_ + +#include "ipa.h" + +/* + * @priv: private data given upon ipa_connect + * @evt: event enum, should be IPA_WRITE_DONE + * @data: for tx path the data field is the sent socket buffer. + */ +typedef void (*ecm_ipa_callback)(void *priv, + enum ipa_dp_evt_type evt, + unsigned long data); + +/* + * struct ecm_ipa_params - parameters for ecm_ipa initialization API + * + * @device_ready_notify: callback supplied by USB core driver. + * This callback shall be called by the Netdev once the device + * is ready to receive data from tethered PC. + * @ecm_ipa_rx_dp_notify: ecm_ipa will set this callback (out parameter). + * this callback shall be supplied for ipa_connect upon pipe + * connection (USB->IPA), once IPA driver receive data packets + * from USB pipe destined for Apps this callback will be called. + * @ecm_ipa_tx_dp_notify: ecm_ipa will set this callback (out parameter). + * this callback shall be supplied for ipa_connect upon pipe + * connection (IPA->USB), once IPA driver send packets destined + * for USB, IPA BAM will notify for Tx-complete. + * @priv: ecm_ipa will set this pointer (out parameter). + * This pointer will hold the network device for later interaction + * with ecm_ipa APIs + * @host_ethaddr: host Ethernet address in network order + * @device_ethaddr: device Ethernet address in network order + * @skip_ep_cfg: boolean field that determines if Apps-processor + * should or should not configure this end-point. + */ +struct ecm_ipa_params { + void (*device_ready_notify)(void); + ecm_ipa_callback ecm_ipa_rx_dp_notify; + ecm_ipa_callback ecm_ipa_tx_dp_notify; + u8 host_ethaddr[ETH_ALEN]; + u8 device_ethaddr[ETH_ALEN]; + void *private; + bool skip_ep_cfg; +}; + + +#if IS_ENABLED(CONFIG_ECM_IPA) + +int ecm_ipa_init(struct ecm_ipa_params *params); + +int ecm_ipa_connect(u32 usb_to_ipa_hdl, u32 ipa_to_usb_hdl, + void *priv); + +int ecm_ipa_disconnect(void *priv); + +void ecm_ipa_cleanup(void *priv); + +#else /* IS_ENABLED(CONFIG_ECM_IPA) */ + +static inline int ecm_ipa_init(struct ecm_ipa_params *params) +{ + return 0; +} + +static inline int ecm_ipa_connect(u32 usb_to_ipa_hdl, u32 ipa_to_usb_hdl, + void *priv) +{ + return 0; +} + +static inline int ecm_ipa_disconnect(void *priv) +{ + return 0; +} + +static inline void ecm_ipa_cleanup(void *priv) +{ + +} +#endif /* IS_ENABLED(CONFIG_ECM_IPA) */ + +#endif /* _ECM_IPA_H_ */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_clients/ipa_eth.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_clients/ipa_eth.c new file mode 100644 index 0000000000..3b5c61b94b --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_clients/ipa_eth.c @@ -0,0 +1,1260 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +#include +#include "../ipa_common_i.h" +#include "../ipa_v3/ipa_pm.h" +#include "../ipa_v3/ipa_i.h" +#include "ipa_eth.h" + +#define OFFLOAD_DRV_NAME "ipa_eth" +#define IPA_ETH_DBG(fmt, args...) \ + do { \ + pr_debug(OFFLOAD_DRV_NAME " %s:%d " fmt, \ + __func__, __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf(), \ + OFFLOAD_DRV_NAME " %s:%d " fmt, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf_low(), \ + OFFLOAD_DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) + +#define IPA_ETH_DBG_LOW(fmt, args...) \ + do { \ + pr_debug(OFFLOAD_DRV_NAME " %s:%d " fmt, \ + __func__, __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf_low(), \ + OFFLOAD_DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) + +#define IPA_ETH_ERR(fmt, args...) \ + do { \ + pr_err(OFFLOAD_DRV_NAME " %s:%d " fmt, \ + __func__, __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf(), \ + OFFLOAD_DRV_NAME " %s:%d " fmt, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf_low(), \ + OFFLOAD_DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) + +#define IPA_ETH_PIPES_NO 8 + +struct ipa_eth_ready_cb_wrapper { + struct list_head link; + struct ipa_eth_ready *info; +}; + +struct ipa_eth_per_client_info { + u32 pm_hdl; + atomic_t ref_cnt; + bool existed; +}; + +struct ipa_eth_intf { + struct list_head link; + char netdev_name[IPA_RESOURCE_NAME_MAX]; + u8 hdr_len; + u32 partial_hdr_hdl[IPA_IP_MAX]; +}; + +struct ipa_eth_context { + struct list_head ready_cb_list; + struct completion completion; + struct ipa_eth_per_client_info + client[IPA_ETH_CLIENT_MAX][IPA_ETH_INST_ID_MAX]; + struct mutex lock; + struct workqueue_struct *wq; + bool is_eth_ready; + struct idr idr; + spinlock_t idr_lock; + struct list_head head_intf_list; + void *client_priv; +}; + +static struct ipa_eth_context *ipa_eth_ctx; + +static int ipa_eth_uc_rdy_cb(struct notifier_block *nb, + unsigned long action, void *data); + +static void ipa_eth_ready_notify_work(struct work_struct *work); + +static struct notifier_block uc_rdy_cb = { + .notifier_call = ipa_eth_uc_rdy_cb, +}; + +static DECLARE_WORK(ipa_eth_ready_notify, ipa_eth_ready_notify_work); + +static bool pipe_connected[IPA_ETH_PIPES_NO]; + +static u8 client_to_pipe_index(enum ipa_client_type client_type) +{ + switch (client_type) { + case IPA_CLIENT_ETHERNET_CONS: + return 0; + break; + case IPA_CLIENT_ETHERNET_PROD: + return 1; + break; + case IPA_CLIENT_RTK_ETHERNET_CONS: + return 2; + break; + case IPA_CLIENT_RTK_ETHERNET_PROD: + return 3; + break; + case IPA_CLIENT_AQC_ETHERNET_CONS: + return 4; + break; + case IPA_CLIENT_AQC_ETHERNET_PROD: + return 5; + break; + case IPA_CLIENT_ETHERNET2_CONS: + return 6; + break; + case IPA_CLIENT_ETHERNET2_PROD: + return 7; + break; + default: + IPAERR("invalid eth client_type\n"); + ipa_assert(); + } + return 0; +} + +static int ipa_eth_init_internal(void) +{ + char buff[IPA_RESOURCE_NAME_MAX]; + int i, j; + + /* already initialized */ + if (ipa_eth_ctx) + return 0; + + ipa_eth_ctx = kzalloc(sizeof(*ipa_eth_ctx), GFP_KERNEL); + if (ipa_eth_ctx == NULL) { + IPA_ETH_ERR("fail to alloc eth ctx\n"); + return -ENOMEM; + } + + snprintf(buff, IPA_RESOURCE_NAME_MAX, "ipa_eth_wq"); + ipa_eth_ctx->wq = alloc_workqueue(buff, + WQ_MEM_RECLAIM | WQ_UNBOUND | WQ_SYSFS, 1); + if (!ipa_eth_ctx->wq) { + goto wq_err; + } + mutex_init(&ipa_eth_ctx->lock); + INIT_LIST_HEAD(&ipa_eth_ctx->ready_cb_list); + ipa_eth_ctx->is_eth_ready = false; + for (i = 0; i < IPA_ETH_CLIENT_MAX; i++) { + for (j = 0; j < IPA_ETH_INST_ID_MAX; j++) { + ipa_eth_ctx->client[i][j].pm_hdl = 0; + ipa_eth_ctx->client[i][j].existed = false; + atomic_set(&ipa_eth_ctx->client[i][j].ref_cnt, 0); + } + } + idr_init(&ipa_eth_ctx->idr); + spin_lock_init(&ipa_eth_ctx->idr_lock); + INIT_LIST_HEAD(&ipa_eth_ctx->head_intf_list); + ipa_eth_ctx->client_priv = NULL; + ipa3_eth_debugfs_init(); + return 0; + +wq_err: + kfree(ipa_eth_ctx); + ipa_eth_ctx = NULL; + return -ENOMEM; +} + +static int ipa_eth_cleanup_internal(void) +{ + struct ipa_eth_intf *entry; + struct ipa_eth_intf *next; + + /* already deinitialized */ + if (!ipa_eth_ctx) + return 0; + /* clear interface list */ + list_for_each_entry_safe(entry, next, + &ipa_eth_ctx->head_intf_list, link) { + list_del(&entry->link); + kfree(entry); + } + mutex_destroy(&ipa_eth_ctx->lock); + destroy_workqueue(ipa_eth_ctx->wq); + kfree(ipa_eth_ctx); + ipa_eth_ctx = NULL; + return 0; +} + +static int ipa_eth_uc_rdy_cb(struct notifier_block *nb, + unsigned long action, void *data) +{ + IPA_ETH_DBG("IPA uC is ready for eth"); + queue_work(ipa_eth_ctx->wq, &ipa_eth_ready_notify); + return NOTIFY_OK; +} + +static void ipa_eth_ready_notify_work(struct work_struct *work) +{ + struct ipa_eth_ready_cb_wrapper *entry; + struct ipa_eth_ready_cb_wrapper *next; + + IPA_ETH_DBG("ipa_eth ready notify\n"); + mutex_lock(&ipa_eth_ctx->lock); + ipa_eth_ctx->is_eth_ready = true; + list_for_each_entry_safe(entry, next, + &ipa_eth_ctx->ready_cb_list, link) { + if (entry->info && entry->info->notify) + entry->info->notify(entry->info->userdata); + /* remove from list once notify is done */ + list_del(&entry->link); + kfree(entry); + } + mutex_unlock(&ipa_eth_ctx->lock); +} + +int ipa_eth_register_ready_cb(struct ipa_eth_ready *ready_info) +{ + int rc; + struct ipa_eth_ready_cb_wrapper *ready_cb; + + /* validate user input */ + if (!ready_info) { + IPA_ETH_ERR("null ready_info"); + return -EFAULT; + } + + if (!ipa_eth_ctx) { + rc = ipa_eth_init_internal(); + if (rc) { + /* it is not normal to fail here */ + IPA_ETH_ERR("initialization failure\n"); + return rc; + } + IPA_ETH_DBG("ipa_eth register ready cb\n"); + mutex_lock(&ipa_eth_ctx->lock); + ready_cb = kmalloc(sizeof(struct ipa_eth_ready_cb_wrapper), + GFP_KERNEL); + if (!ready_cb) { + mutex_unlock(&ipa_eth_ctx->lock); + ipa_eth_cleanup_internal(); + return -ENOMEM; + } + ready_cb->info = ready_info; + list_add_tail(&ready_cb->link, &ipa_eth_ctx->ready_cb_list); + mutex_unlock(&ipa_eth_ctx->lock); + /* rely on uC ready callback, only register once */ + rc = ipa3_uc_register_ready_cb(&uc_rdy_cb); + if (rc) { + IPA_ETH_ERR("Failed to register ready cb\n"); + goto err_uc; + } + } else { + /* assume only IOSS could register for cb */ + IPA_ETH_ERR("multiple eth register happens\n"); + mutex_lock(&ipa_eth_ctx->lock); + ready_cb = kmalloc(sizeof(struct ipa_eth_ready_cb_wrapper), + GFP_KERNEL); + if (!ready_cb) { + mutex_unlock(&ipa_eth_ctx->lock); + return -ENOMEM; + } + ready_cb->info = ready_info; + list_add_tail(&ready_cb->link, &ipa_eth_ctx->ready_cb_list); + /* if already ready, directly callback from wq */ + if (ipa3_uc_loaded_check()) + queue_work(ipa_eth_ctx->wq, &ipa_eth_ready_notify); + mutex_unlock(&ipa_eth_ctx->lock); + } + + /* if uc is already ready, set the output param to true */ + if (ipa3_uc_loaded_check()) + ready_info->is_eth_ready = true; + + return 0; + +err_uc: + list_del(&ready_cb->link); + ipa_eth_cleanup_internal(); + return rc; +} +EXPORT_SYMBOL(ipa_eth_register_ready_cb); + +int ipa_eth_unregister_ready_cb(struct ipa_eth_ready *ready_info) +{ + struct ipa_eth_ready_cb_wrapper *entry; + bool find_ready_info = false; + + /* validate user input */ + if (!ready_info) { + IPA_ETH_ERR("null ready_info"); + return -EFAULT; + } + + if (!ipa_eth_ctx) { + IPA_ETH_ERR("unregister called before register\n"); + return -EFAULT; + } + + IPA_ETH_DBG("ipa_eth unregister ready cb\n"); + mutex_lock(&ipa_eth_ctx->lock); + list_for_each_entry(entry, &ipa_eth_ctx->ready_cb_list, + link) { + if (!entry) + break; + if (entry->info == ready_info) { + list_del(&entry->link); + find_ready_info = true; + break; + } + } + if (!find_ready_info) { + IPA_ETH_ERR("unable to unregsiter, no ready_info\n"); + mutex_unlock(&ipa_eth_ctx->lock); + return -EFAULT; + } + if (list_empty(&ipa_eth_ctx->ready_cb_list)) { + mutex_unlock(&ipa_eth_ctx->lock); + ipa_eth_cleanup_internal(); + return 0; + } + + ready_info->is_eth_ready = false; + mutex_unlock(&ipa_eth_ctx->lock); + return 0; +} +EXPORT_SYMBOL(ipa_eth_unregister_ready_cb); + +static u32 ipa_eth_pipe_hdl_alloc(void *ptr) +{ + ipa_eth_hdl_t hdl; + + idr_preload(GFP_KERNEL); + spin_lock(&ipa_eth_ctx->idr_lock); + hdl = idr_alloc(&ipa_eth_ctx->idr, ptr, 0, 0, GFP_NOWAIT); + spin_unlock(&ipa_eth_ctx->idr_lock); + idr_preload_end(); + + return hdl; +} + +static void ipa_eth_pipe_hdl_remove(ipa_eth_hdl_t hdl) +{ + spin_lock(&ipa_eth_ctx->idr_lock); + idr_remove(&ipa_eth_ctx->idr, hdl); + spin_unlock(&ipa_eth_ctx->idr_lock); +} + +static enum ipa_client_type + ipa_eth_get_ipa_client_type_from_pipe( + struct ipa_eth_client_pipe_info *pipe) +{ + struct ipa_eth_client *client; + int ipa_client_type = IPA_CLIENT_MAX; + + if (!pipe) { + IPA_ETH_ERR("invalid pipe\n"); + return ipa_client_type; + } + + client = pipe->client_info; + if (!client) { + IPA_ETH_ERR("invalid client\n"); + return ipa_client_type; + } + switch (client->client_type) { + case IPA_ETH_CLIENT_AQC107: + case IPA_ETH_CLIENT_AQC113: + if (client->traffic_type == + IPA_ETH_PIPE_BEST_EFFORT && + client->inst_id == 0) { + if (pipe->dir == IPA_ETH_PIPE_DIR_TX) { + ipa_client_type = + IPA_CLIENT_AQC_ETHERNET_CONS; + } else { + ipa_client_type = + IPA_CLIENT_AQC_ETHERNET_PROD; + } + } + break; + case IPA_ETH_CLIENT_RTK8111K: + case IPA_ETH_CLIENT_RTK8125B: + if (client->traffic_type == + IPA_ETH_PIPE_BEST_EFFORT && + client->inst_id == 0) { + if (pipe->dir == IPA_ETH_PIPE_DIR_TX) { + ipa_client_type = + IPA_CLIENT_RTK_ETHERNET_CONS; + } else { + ipa_client_type = + IPA_CLIENT_RTK_ETHERNET_PROD; + } + } + break; + case IPA_ETH_CLIENT_NTN: + case IPA_ETH_CLIENT_EMAC: + if (client->traffic_type == + IPA_ETH_PIPE_BEST_EFFORT && + client->inst_id == 0) { + if (pipe->dir == IPA_ETH_PIPE_DIR_TX) { + ipa_client_type = + IPA_CLIENT_ETHERNET_CONS; + } else { + ipa_client_type = + IPA_CLIENT_ETHERNET_PROD; + } + } + break; +#if IPA_ETH_API_VER >= 2 + case IPA_ETH_CLIENT_NTN3: + if (client->traffic_type == IPA_ETH_PIPE_BEST_EFFORT) { + if (client->inst_id == 0) { + if (pipe->dir == IPA_ETH_PIPE_DIR_TX) { + ipa_client_type = IPA_CLIENT_ETHERNET_CONS; + } else { + ipa_client_type = IPA_CLIENT_ETHERNET_PROD; + } + } else if (client->inst_id == 1) { + if (pipe->dir == IPA_ETH_PIPE_DIR_TX) { + ipa_client_type = IPA_CLIENT_ETHERNET2_CONS; + } else { + ipa_client_type = IPA_CLIENT_ETHERNET2_PROD; + } + } + } + break; +#endif + default: + IPA_ETH_ERR("invalid client type%d\n", + client->client_type); + } + return ipa_client_type; +} + +static struct ipa_eth_client_pipe_info + *ipa_eth_get_pipe_from_hdl(ipa_eth_hdl_t hdl) +{ + struct ipa_eth_client_pipe_info *pipe; + + spin_lock(&ipa_eth_ctx->idr_lock); + pipe = idr_find(&ipa_eth_ctx->idr, hdl); + spin_unlock(&ipa_eth_ctx->idr_lock); + + return pipe; +} + + +static int ipa_eth_client_connect_pipe( + struct ipa_eth_client_pipe_info *pipe) +{ + enum ipa_client_type client_type; + struct ipa_eth_client *client; + int ret; + + if (!pipe) { + IPA_ETH_ERR("invalid pipe\n"); + return -EFAULT; + } + client = pipe->client_info; + if (!client) { + IPA_ETH_ERR("invalid client\n"); + return -EFAULT; + } + client_type = + ipa_eth_get_ipa_client_type_from_pipe(pipe); + if (client_type == IPA_CLIENT_MAX) { + IPA_ETH_ERR("invalid client type\n"); + return -EFAULT; + } + + if (pipe_connected[client_to_pipe_index(client_type)]) { + IPA_ETH_ERR("client already connected\n"); + return -EFAULT; + } + + pipe->pipe_hdl = ipa_eth_pipe_hdl_alloc((void *)pipe); + + ret = ipa3_eth_connect(pipe, client_type); + if (!ret) { + pipe_connected[client_to_pipe_index(client_type)] = true; + } + + return ret; +} + +static int ipa_eth_client_disconnect_pipe( + struct ipa_eth_client_pipe_info *pipe) +{ + enum ipa_client_type client_type; + struct ipa_eth_client *client; + int result; + + if (!pipe) { + IPA_ETH_ERR("invalid pipe\n"); + return -EFAULT; + } + + client = pipe->client_info; + if (!client) { + IPA_ETH_ERR("invalid client\n"); + return -EFAULT; + } + client_type = + ipa_eth_get_ipa_client_type_from_pipe(pipe); + if (client_type == IPA_CLIENT_MAX) { + IPA_ETH_ERR("invalid client type\n"); + return -EFAULT; + } + + if (!pipe_connected[client_to_pipe_index(client_type)]) { + IPA_ETH_ERR("client not connected\n"); + return -EFAULT; + } + + result = ipa3_eth_disconnect(pipe, client_type); + if (result) + return result; + + pipe_connected[client_to_pipe_index(client_type)] = false; + + ipa_eth_pipe_hdl_remove(pipe->pipe_hdl); + return 0; +} + + +static int ipa_eth_commit_partial_hdr( + struct ipa_ioc_add_hdr *hdr, + const char *netdev_name, + struct ipa_eth_hdr_info *hdr_info) +{ + int i; + + if (!hdr || !hdr_info || !netdev_name) { + IPA_ETH_ERR("Invalid input\n"); + return -EINVAL; + } + + hdr->commit = 0; + hdr->num_hdrs = 2; + + snprintf(hdr->hdr[0].name, sizeof(hdr->hdr[0].name), + "%s_ipv4", netdev_name); + snprintf(hdr->hdr[1].name, sizeof(hdr->hdr[1].name), + "%s_ipv6", netdev_name); + for (i = IPA_IP_v4; i < IPA_IP_MAX; i++) { + hdr->hdr[i].hdr_len = hdr_info[i].hdr_len; + memcpy(hdr->hdr[i].hdr, hdr_info[i].hdr, hdr->hdr[i].hdr_len); + hdr->hdr[i].type = hdr_info[i].hdr_type; + hdr->hdr[i].is_partial = 1; + hdr->hdr[i].is_eth2_ofst_valid = 1; + hdr->hdr[i].eth2_ofst = hdr_info[i].dst_mac_addr_offset; + } + + if (ipa_add_hdr(hdr)) { + IPA_ETH_ERR("fail to add partial headers\n"); + return -EFAULT; + } + + return 0; +} + + +static void ipa_eth_pm_cb(void *p, enum ipa_pm_cb_event event) +{ + IPA_ETH_ERR("received pm event %d\n", event); +} + +static int ipa_eth_pm_register(struct ipa_eth_client *client) +{ + struct ipa_pm_register_params pm_params; + int client_type, inst_id; + char name[IPA_RESOURCE_NAME_MAX]; + struct ipa_eth_client_pipe_info *pipe; + int rc; + + /* validate user input */ + if (!client || (client->client_type >= IPA_ETH_CLIENT_MAX)) { + IPA_ETH_ERR("null client or eth client doesn't exist"); + return -EFAULT; + } + client_type = client->client_type; + inst_id = client->inst_id; + + if (atomic_read( + &ipa_eth_ctx->client[client_type][inst_id].ref_cnt)) + goto add_pipe_list; + + memset(&pm_params, 0, sizeof(pm_params)); + snprintf(name, IPA_RESOURCE_NAME_MAX, + "ipa_eth_%d_%d", client_type, inst_id); + pm_params.name = name; + pm_params.callback = ipa_eth_pm_cb; + pm_params.user_data = NULL; + pm_params.group = IPA_PM_GROUP_DEFAULT; + if (ipa_pm_register(&pm_params, + &ipa_eth_ctx->client[client_type][inst_id].pm_hdl)) { + IPA_ETH_ERR("fail to register ipa pm\n"); + return -EFAULT; + } + /* vote IPA clock on */ + rc = ipa_pm_activate_sync( + ipa_eth_ctx->client[client_type][inst_id].pm_hdl); + if (rc) { + IPA_ETH_ERR("fail to activate ipa pm\n"); + return -EFAULT; + } +add_pipe_list: + list_for_each_entry(pipe, &client->pipe_list, + link) { + if (pipe->dir == IPA_ETH_PIPE_DIR_RX) + continue; + rc = ipa_pm_associate_ipa_cons_to_client( + ipa_eth_ctx->client[client_type][inst_id].pm_hdl, + ipa_eth_get_ipa_client_type_from_pipe(pipe)); + if (rc) { + IPA_ETH_ERR("fail to associate cons with PM %d\n", rc); + ipa_pm_deregister( + ipa_eth_ctx->client[client_type][inst_id].pm_hdl); + ipa_eth_ctx->client[client_type][inst_id].pm_hdl = 0; + ipa_assert(); + return rc; + } + } + atomic_inc( + &ipa_eth_ctx->client[client_type][inst_id].ref_cnt); + return 0; +} + +static int ipa_eth_pm_deregister(struct ipa_eth_client *client) +{ + int rc; + int client_type, inst_id; + + /* validate user input */ + if (!client || (client->client_type >= IPA_ETH_CLIENT_MAX)) { + IPA_ETH_ERR("null client or client type not defined"); + return -EFAULT; + } + client_type = client->client_type; + inst_id = client->inst_id; + if (atomic_read( + &ipa_eth_ctx->client[client_type][inst_id].ref_cnt) + == 1) { + rc = ipa_pm_deactivate_sync( + ipa_eth_ctx->client[client_type][inst_id].pm_hdl); + if (rc) { + IPA_ETH_ERR("fail to deactivate ipa pm\n"); + return -EFAULT; + } + if (ipa_pm_deregister( + ipa_eth_ctx->client[client_type][inst_id].pm_hdl)) { + IPA_ETH_ERR("fail to deregister ipa pm\n"); + return -EFAULT; + } + } + atomic_dec(&ipa_eth_ctx->client[client_type][inst_id].ref_cnt); + return 0; +} + +int ipa_eth_client_conn_pipes(struct ipa_eth_client *client) +{ + struct ipa_eth_client_pipe_info *pipe; + int rc; + int client_type, inst_id, traff_type; + + /* validate user input */ + if (!client || (client->client_type >= IPA_ETH_CLIENT_MAX)) { + IPA_ETH_ERR("null client or client type not defined"); + return -EFAULT; + } + if (!ipa_eth_ctx) { + IPA_ETH_ERR("connect called before register readiness\n"); + return -EFAULT; + } + + if (!ipa_eth_ctx->is_eth_ready) { + IPA_ETH_ERR("conn called before IPA eth ready\n"); + return -EFAULT; + } + ipa_eth_ctx->client_priv = client->priv; + client_type = client->client_type; + inst_id = client->inst_id; + traff_type = client->traffic_type; + IPA_ETH_DBG("ipa_eth conn client %d inst %d, traffic %d\n", + client_type, inst_id, traff_type); + mutex_lock(&ipa_eth_ctx->lock); + rc = ipa_eth_pm_register(client); + if (rc) { + IPA_ETH_ERR("pm register failed\n"); + mutex_unlock(&ipa_eth_ctx->lock); + return -EFAULT; + } + list_for_each_entry(pipe, &client->pipe_list, + link) { + rc = ipa_eth_client_connect_pipe(pipe); + if (rc) { + IPA_ETH_ERR("pipe connect fails\n"); + ipa_assert(); + } + } + if (!ipa_eth_ctx->client[client_type][inst_id].existed) { + ipa3_eth_debugfs_add_node(client); + ipa_eth_ctx->client[client_type][inst_id].existed = true; + } + mutex_unlock(&ipa_eth_ctx->lock); + return 0; +} +EXPORT_SYMBOL(ipa_eth_client_conn_pipes); + +int ipa_eth_client_disconn_pipes(struct ipa_eth_client *client) +{ + int rc; + struct ipa_eth_client_pipe_info *pipe; + struct ipa_ep_cfg_holb holb; + + /* validate user input */ + if (!client) { + IPA_ETH_ERR("null client"); + return -EFAULT; + } + + if (!ipa_eth_ctx) { + IPA_ETH_ERR("disconn called before register readiness\n"); + return -EFAULT; + } + + if (!ipa_eth_ctx->is_eth_ready) { + IPA_ETH_ERR("disconn called before IPA eth ready\n"); + return -EFAULT; + } + IPA_ETH_DBG("ipa_eth disconn client %d inst %d, traffic %d\n", + client->client_type, client->inst_id, + client->traffic_type); + mutex_lock(&ipa_eth_ctx->lock); + + /* set holb on tx pipes first */ + list_for_each_entry(pipe, &client->pipe_list, + link) { + if (pipe->dir == IPA_ETH_PIPE_DIR_TX) + { + IPA_ETH_DBG("Set holb on pipe = %d, pipe->dir = %d \n", + ipa_get_ep_mapping(ipa_eth_get_ipa_client_type_from_pipe(pipe)), + pipe->dir); + holb.en = 1; + holb.tmr_val = 0; + ipa3_cfg_ep_holb(ipa_get_ep_mapping( + ipa_eth_get_ipa_client_type_from_pipe(pipe)), &holb); + } + } + + list_for_each_entry(pipe, &client->pipe_list, + link) { + rc = ipa_eth_client_disconnect_pipe(pipe); + if (rc) { + IPA_ETH_ERR("pipe connect fails\n"); + ipa_assert(); + } + } + if (ipa_eth_pm_deregister(client)) { + IPA_ETH_ERR("pm deregister failed\n"); + mutex_unlock(&ipa_eth_ctx->lock); + return -EFAULT; + } + mutex_unlock(&ipa_eth_ctx->lock); + return 0; +} +EXPORT_SYMBOL(ipa_eth_client_disconn_pipes); + +static void ipa_eth_msg_free_cb(void *buff, u32 len, u32 type) +{ + kfree(buff); +} + +int ipa_eth_client_conn_evt(struct ipa_ecm_msg *msg) +{ + struct ipa_msg_meta msg_meta; + struct ipa_ecm_msg *eth_msg; + int ret; + + IPA_ETH_DBG("enter\n"); + + eth_msg = kzalloc(sizeof(*eth_msg), GFP_KERNEL); + if (eth_msg == NULL) + return -ENOMEM; + memcpy(eth_msg, msg, sizeof(struct ipa_ecm_msg)); + memset(&msg_meta, 0, sizeof(struct ipa_msg_meta)); + msg_meta.msg_len = sizeof(struct ipa_ecm_msg); + msg_meta.msg_type = IPA_PERIPHERAL_CONNECT; + + IPA_ETH_DBG("send IPA_PERIPHERAL_CONNECT, len:%d, buff %pK", msg_meta.msg_len, eth_msg); + ret = ipa_send_msg(&msg_meta, eth_msg, ipa_eth_msg_free_cb); + + IPA_ETH_DBG("exit\n"); + + return ret; +} +EXPORT_SYMBOL(ipa_eth_client_conn_evt); + +int ipa_eth_client_disconn_evt(struct ipa_ecm_msg *msg) +{ + struct ipa_msg_meta msg_meta; + struct ipa_ecm_msg *eth_msg; + int ret; + + IPA_ETH_DBG("enter\n"); + + eth_msg = kzalloc(sizeof(*eth_msg), GFP_KERNEL); + if (eth_msg == NULL) + return -ENOMEM; + memcpy(eth_msg, msg, sizeof(struct ipa_ecm_msg)); + memset(&msg_meta, 0, sizeof(struct ipa_msg_meta)); + msg_meta.msg_len = sizeof(struct ipa_ecm_msg); + msg_meta.msg_type = IPA_PERIPHERAL_DISCONNECT; + + IPA_ETH_DBG("send PERIPHERAL_DISCONNECT, len:%d, buff %pK", msg_meta.msg_len, eth_msg); + ret = ipa_send_msg(&msg_meta, eth_msg, ipa_eth_msg_free_cb); + + IPA_ETH_DBG("exit\n"); + + return ret; +} +EXPORT_SYMBOL(ipa_eth_client_disconn_evt); + +int ipa_eth_client_reg_intf(struct ipa_eth_intf_info *intf) +{ + struct ipa_eth_intf *new_intf; + struct ipa_eth_intf *entry; + struct ipa_ioc_add_hdr *hdr; + struct ipa_tx_intf tx; + struct ipa_rx_intf rx; + enum ipa_client_type tx_client[IPA_CLIENT_MAX] = {0}; + enum ipa_client_type rx_client[IPA_CLIENT_MAX] = {0}; + struct ipa_ioc_tx_intf_prop *tx_prop = NULL; + struct ipa_ioc_rx_intf_prop *rx_prop = NULL; + struct ipa_eth_client_pipe_info *pipe; + u32 len; + int ret = 0, i; +#if IPA_ETH_API_VER >= 2 + struct ipa_ecm_msg msg; + bool vlan_mode = false; + struct ipa_eth_hdr_info intf_hdr[IPA_IP_MAX]; + struct ethhdr l_ethhdr[IPA_IP_MAX] = { 0 }; + struct vlan_ethhdr l_vlan_ethhdr[IPA_IP_MAX] = { 0 }; +#endif + + if (intf == NULL) { + IPA_ETH_ERR("invalid params intf=%pK\n", intf); + return -EINVAL; + } + if (!ipa_eth_ctx) { + IPA_ETH_ERR("disconn called before register readiness\n"); + return -EFAULT; + } +#if IPA_ETH_API_VER >= 2 + if (!intf->client) { + IPA_ETH_ERR("invalid intf->client\n"); + return -EFAULT; + } + if (!intf->client->net_dev) { + IPA_ETH_ERR("invalid netdev\n"); + return -EFAULT; + } + if (!intf->net_dev) + intf->net_dev = intf->client->net_dev; + + IPA_ETH_DBG("register interface for netdev %s\n", intf->net_dev->name); + /* multiple attach support */ + if (strnstr(intf->net_dev->name, STR_ETH0_IFACE, strlen(intf->net_dev->name))) { + ret = ipa_is_vlan_mode(IPA_VLAN_IF_ETH0, &vlan_mode); + if (ret) { + IPA_ETH_ERR("Could not determine IPA VLAN mode\n"); + return ret; + } + } else if (strnstr(intf->net_dev->name, STR_ETH1_IFACE, strlen(intf->net_dev->name))) { + ret = ipa_is_vlan_mode(IPA_VLAN_IF_ETH1, &vlan_mode); + if (ret) { + IPA_ETH_ERR("Could not determine IPA VLAN mode\n"); + return ret; + } + } else { + ret = ipa_is_vlan_mode(IPA_VLAN_IF_ETH, &vlan_mode); + if (ret) { + IPA_ETH_ERR("Could not determine IPA VLAN mode\n"); + return ret; + } + } +#else + IPA_ETH_DBG("register interface for netdev %s\n", + intf->netdev_name); +#endif + mutex_lock(&ipa_eth_ctx->lock); + list_for_each_entry(entry, &ipa_eth_ctx->head_intf_list, link) +#if IPA_ETH_API_VER >= 2 + if (strcmp(entry->netdev_name, intf->net_dev->name) == 0) { +#else + if (strcmp(entry->netdev_name, intf->netdev_name) == 0) { +#endif + IPA_ETH_DBG("intf was added before.\n"); + mutex_unlock(&ipa_eth_ctx->lock); + return 0; + } +#if IPA_ETH_API_VER >= 2 + memset(intf_hdr, 0, sizeof(intf_hdr)); + if (!vlan_mode) { + struct ethhdr *eth_h; + + intf_hdr[0].hdr = (u8 *)&l_ethhdr[0]; + eth_h = (struct ethhdr *) intf_hdr[0].hdr; + memcpy(ð_h->h_source, intf->net_dev->dev_addr, ETH_ALEN); + eth_h->h_proto = htons(ETH_P_IP); + intf_hdr[0].hdr_len = ETH_HLEN; + intf_hdr[0].hdr_type = IPA_HDR_L2_ETHERNET_II; + + intf_hdr[1].hdr = (u8 *)&l_ethhdr[1]; + eth_h = (struct ethhdr *) intf_hdr[1].hdr; + memcpy(ð_h->h_source, intf->net_dev->dev_addr, ETH_ALEN); + eth_h->h_proto = htons(ETH_P_IPV6); + intf_hdr[1].hdr_len = ETH_HLEN; + intf_hdr[1].hdr_type = IPA_HDR_L2_ETHERNET_II; + } else { + struct vlan_ethhdr *vlan_eth_h; + + intf_hdr[0].hdr = (u8 *)&l_vlan_ethhdr[0]; + vlan_eth_h = (struct vlan_ethhdr *) intf_hdr[0].hdr; + memcpy(&vlan_eth_h->h_source, intf->net_dev->dev_addr, ETH_ALEN); + vlan_eth_h->h_vlan_proto = htons(ETH_P_8021Q); + vlan_eth_h->h_vlan_encapsulated_proto = htons(ETH_P_IP); + intf_hdr[0].hdr_len = VLAN_ETH_HLEN; + intf_hdr[0].hdr_type = IPA_HDR_L2_802_1Q; + + intf_hdr[1].hdr = (u8 *)&l_vlan_ethhdr[1]; + vlan_eth_h = (struct vlan_ethhdr *) intf_hdr[1].hdr; + memcpy(&vlan_eth_h->h_source, intf->net_dev->dev_addr, ETH_ALEN); + vlan_eth_h->h_vlan_proto = htons(ETH_P_8021Q); + vlan_eth_h->h_vlan_encapsulated_proto = htons(ETH_P_IPV6); + intf_hdr[1].hdr_len = VLAN_ETH_HLEN; + intf_hdr[1].hdr_type = IPA_HDR_L2_802_1Q;; + } +#endif + new_intf = kzalloc(sizeof(*new_intf), GFP_KERNEL); + if (new_intf == NULL) { + IPA_ETH_ERR("fail to alloc new intf\n"); + mutex_unlock(&ipa_eth_ctx->lock); + return -ENOMEM; + } + INIT_LIST_HEAD(&new_intf->link); +#if IPA_ETH_API_VER >= 2 + strlcpy(new_intf->netdev_name, intf->net_dev->name, sizeof(new_intf->netdev_name)); + new_intf->hdr_len = intf_hdr[0].hdr_len; +#else + strlcpy(new_intf->netdev_name, intf->netdev_name, + sizeof(new_intf->netdev_name)); + new_intf->hdr_len = intf->hdr[0].hdr_len; +#endif + /* add partial header */ + len = sizeof(struct ipa_ioc_add_hdr) + 2 * sizeof(struct ipa_hdr_add); + hdr = kzalloc(len, GFP_KERNEL); + if (hdr == NULL) { + IPA_ETH_ERR("fail to alloc %d bytes\n", len); + ret = -EFAULT; + goto fail_alloc_hdr; + } +#if IPA_ETH_API_VER >= 2 + if (ipa_eth_commit_partial_hdr(hdr, intf->net_dev->name, (struct ipa_eth_hdr_info *)intf_hdr)) { +#else + if (ipa_eth_commit_partial_hdr(hdr, + intf->netdev_name, intf->hdr)) { +#endif + IPA_ETH_ERR("fail to commit partial headers\n"); + ret = -EFAULT; + goto fail_commit_hdr; + } + + new_intf->partial_hdr_hdl[IPA_IP_v4] = hdr->hdr[IPA_IP_v4].hdr_hdl; + new_intf->partial_hdr_hdl[IPA_IP_v6] = hdr->hdr[IPA_IP_v6].hdr_hdl; + IPA_ETH_DBG("IPv4 hdr hdl: %d IPv6 hdr hdl: %d\n", + hdr->hdr[IPA_IP_v4].hdr_hdl, hdr->hdr[IPA_IP_v6].hdr_hdl); + + memset(&tx, 0, sizeof(struct ipa_tx_intf)); + memset(&rx, 0, sizeof(struct ipa_rx_intf)); +#if IPA_ETH_API_VER >= 2 + list_for_each_entry(pipe, &intf->client->pipe_list, link) { +#else + for (i = 0; i < intf->pipe_hdl_list_size; i++) { + pipe = ipa_eth_get_pipe_from_hdl(intf->pipe_hdl_list[i]); +#endif + if (pipe->dir == IPA_ETH_PIPE_DIR_TX) { + tx_client[tx.num_props] = + ipa_eth_get_ipa_client_type_from_pipe(pipe); + tx.num_props++; + } else { + rx_client[rx.num_props] = + ipa_eth_get_ipa_client_type_from_pipe(pipe); + rx.num_props++; + } + } + /* populate tx prop */ + if (tx.num_props) { + tx_prop = kmalloc( + sizeof(*tx_prop) * tx.num_props * + IPA_IP_MAX, GFP_KERNEL); + if (!tx_prop) { + IPAERR("failed to allocate memory\n"); + ret = -ENOMEM; + goto fail_commit_hdr; + } + memset(tx_prop, 0, sizeof(*tx_prop) * + tx.num_props * IPA_IP_MAX); + tx.prop = tx_prop; + for (i = 0; i < tx.num_props; i++) { + tx_prop[i].ip = IPA_IP_v4; + tx_prop[i].dst_pipe = tx_client[i]; +#if IPA_ETH_API_VER >= 2 + tx_prop[i].hdr_l2_type = intf_hdr[0].hdr_type; +#else + tx_prop[i].hdr_l2_type = intf->hdr[0].hdr_type; +#endif + strlcpy(tx_prop[i].hdr_name, hdr->hdr[IPA_IP_v4].name, + sizeof(tx_prop[i].hdr_name)); + + tx_prop[i+1].ip = IPA_IP_v6; + tx_prop[i+1].dst_pipe = tx_client[i]; +#if IPA_ETH_API_VER >= 2 + tx_prop[i+1].hdr_l2_type = intf_hdr[1].hdr_type; +#else + tx_prop[i+1].hdr_l2_type = intf->hdr[1].hdr_type; +#endif + strlcpy(tx_prop[i+1].hdr_name, hdr->hdr[IPA_IP_v6].name, + sizeof(tx_prop[i+1].hdr_name)); + } + } + /* populate rx prop */ + if (rx.num_props) { + rx_prop = kmalloc( + sizeof(*rx_prop) * rx.num_props * + IPA_IP_MAX, GFP_KERNEL); + if (!rx_prop) { + IPAERR("failed to allocate memory\n"); + ret = -ENOMEM; + goto fail_commit_hdr; + } + memset(rx_prop, 0, sizeof(*rx_prop) * + rx.num_props * IPA_IP_MAX); + rx.prop = rx_prop; + for (i = 0; i < rx.num_props; i++) { + rx_prop[i].ip = IPA_IP_v4; + rx_prop[i].src_pipe = rx_client[i]; +#if IPA_ETH_API_VER >= 2 + rx_prop[i].hdr_l2_type = intf_hdr[0].hdr_type; +#else + rx_prop[i].hdr_l2_type = intf->hdr[0].hdr_type; +#endif + rx_prop[i+1].ip = IPA_IP_v6; + rx_prop[i+1].src_pipe = rx_client[i]; +#if IPA_ETH_API_VER >= 2 + rx_prop[i+1].hdr_l2_type = intf_hdr[1].hdr_type; +#else + rx_prop[i+1].hdr_l2_type = intf->hdr[1].hdr_type; +#endif + } + tx.num_props *= IPA_IP_MAX; + rx.num_props *= IPA_IP_MAX; + } +#if IPA_ETH_API_VER >= 2 + if (ipa_register_intf(intf->net_dev->name, &tx, &rx)) { +#else + if (ipa_register_intf(intf->netdev_name, &tx, &rx)) { +#endif + IPA_ETH_ERR("fail to add interface prop\n"); + ret = -EFAULT; + goto fail_commit_hdr; + } + + list_add(&new_intf->link, &ipa_eth_ctx->head_intf_list); + + kfree(hdr); + kfree(tx_prop); + kfree(rx_prop); + mutex_unlock(&ipa_eth_ctx->lock); + +#if IPA_ETH_API_VER >= 2 + if (intf->is_conn_evt) { + strlcpy(msg.name, intf->net_dev->name, sizeof(msg.name)); + msg.ifindex = intf->net_dev->ifindex; + ipa_eth_client_conn_evt_internal(&msg); + } +#endif + return 0; +fail_commit_hdr: + kfree(hdr); + kfree(tx_prop); + kfree(rx_prop); +fail_alloc_hdr: + kfree(new_intf); + mutex_unlock(&ipa_eth_ctx->lock); + return ret; +} +EXPORT_SYMBOL(ipa_eth_client_reg_intf); + +int ipa_eth_client_unreg_intf(struct ipa_eth_intf_info *intf) +{ + int len, ret = 0; + struct ipa_ioc_del_hdr *hdr = NULL; + struct ipa_eth_intf *entry; + struct ipa_eth_intf *next; +#if IPA_ETH_API_VER >= 2 + struct ipa_ecm_msg msg; +#endif + + if (intf == NULL) { + IPA_ETH_ERR("invalid params intf=%pK\n", intf); + return -EINVAL; + } + if (!ipa_eth_ctx) { + IPA_ETH_ERR("disconn called before register readiness\n"); + return -EFAULT; + } +#if IPA_ETH_API_VER >= 2 + if (!intf->net_dev) { + IPA_ETH_ERR("invalid netdev\n"); + return -EFAULT; + } + IPA_ETH_DBG("unregister interface for netdev %s\n", intf->net_dev->name); +#else + IPA_ETH_DBG("unregister interface for netdev %s\n", + intf->netdev_name); +#endif + mutex_lock(&ipa_eth_ctx->lock); + list_for_each_entry_safe(entry, next, &ipa_eth_ctx->head_intf_list, + link) +#if IPA_ETH_API_VER >= 2 + if (strcmp(entry->netdev_name, intf->net_dev->name) == 0) { +#else + if (strcmp(entry->netdev_name, intf->netdev_name) == 0) { +#endif + len = sizeof(struct ipa_ioc_del_hdr) + + IPA_IP_MAX * sizeof(struct ipa_hdr_del); + hdr = kzalloc(len, GFP_KERNEL); + if (hdr == NULL) { + IPA_ETH_ERR("fail to alloc %d bytes\n", len); + mutex_unlock(&ipa_eth_ctx->lock); + return -ENOMEM; + } + + hdr->commit = 1; + hdr->num_hdls = 2; + hdr->hdl[0].hdl = entry->partial_hdr_hdl[0]; + hdr->hdl[1].hdl = entry->partial_hdr_hdl[1]; + IPA_ETH_DBG("IPv4 hdr hdl: %d IPv6 hdr hdl: %d\n", + hdr->hdl[0].hdl, hdr->hdl[1].hdl); + + if (ipa_del_hdr(hdr)) { + IPA_ETH_ERR("fail to delete partial header\n"); + ret = -EFAULT; + goto fail; + } + + if (ipa_deregister_intf(entry->netdev_name)) { + IPA_ETH_ERR("fail to del interface props\n"); + ret = -EFAULT; + goto fail; + } + + list_del(&entry->link); + kfree(entry); + + break; + } +fail: + kfree(hdr); + mutex_unlock(&ipa_eth_ctx->lock); +#if IPA_ETH_API_VER >= 2 + if (intf->is_conn_evt) { + strlcpy(msg.name, intf->net_dev->name, sizeof(msg.name)); + msg.ifindex = intf->net_dev->ifindex; + ipa_eth_client_disconn_evt_internal(&msg); + } +#endif + return ret; + +} +EXPORT_SYMBOL(ipa_eth_client_unreg_intf); + +int ipa_eth_client_set_perf_profile(struct ipa_eth_client *client, + struct ipa_eth_perf_profile *profile) +{ + int client_type, inst_id; + + if ((!profile) || (!client) || (client->client_type >= IPA_ETH_CLIENT_MAX)) { + IPA_ETH_ERR("Invalid input\n"); + return -EINVAL; + } + + client_type = client->client_type; + inst_id = client->inst_id; + + if (ipa_pm_set_throughput( + ipa_eth_ctx->client[client_type][inst_id].pm_hdl, + profile->max_supported_bw_mbps)) { + IPA_ETH_ERR("fail to set pm throughput\n"); + return -EFAULT; + } + + return 0; +} +EXPORT_SYMBOL(ipa_eth_client_set_perf_profile); + +enum ipa_client_type ipa_eth_get_ipa_client_type_from_eth_type( + enum ipa_eth_client_type eth_client_type, enum ipa_eth_pipe_direction dir) +{ + int ipa_client_type = IPA_CLIENT_MAX; + + switch (eth_client_type) { + case IPA_ETH_CLIENT_AQC107: + case IPA_ETH_CLIENT_AQC113: + if (dir == IPA_ETH_PIPE_DIR_TX) { + ipa_client_type = + IPA_CLIENT_AQC_ETHERNET_CONS; + } else { + ipa_client_type = + IPA_CLIENT_AQC_ETHERNET_PROD; + } + break; + case IPA_ETH_CLIENT_RTK8111K: + case IPA_ETH_CLIENT_RTK8125B: + if (dir == IPA_ETH_PIPE_DIR_TX) { + ipa_client_type = + IPA_CLIENT_RTK_ETHERNET_CONS; + } else { + ipa_client_type = + IPA_CLIENT_RTK_ETHERNET_PROD; + } + break; + case IPA_ETH_CLIENT_NTN: + case IPA_ETH_CLIENT_EMAC: +#if IPA_ETH_API_VER >= 2 + case IPA_ETH_CLIENT_NTN3: +#endif + if (dir == IPA_ETH_PIPE_DIR_TX) { + ipa_client_type = + IPA_CLIENT_ETHERNET_CONS; + } else { + ipa_client_type = + IPA_CLIENT_ETHERNET_PROD; + } + break; + default: + IPA_ETH_ERR("invalid client type%d\n", + eth_client_type); + } + return ipa_client_type; +} +EXPORT_SYMBOL(ipa_eth_get_ipa_client_type_from_eth_type); + +bool ipa_eth_client_exist(enum ipa_eth_client_type eth_client_type, int inst_id) +{ + if (ipa_eth_ctx) + return ipa_eth_ctx->client[eth_client_type][inst_id].existed; + else return false; +} +EXPORT_SYMBOL(ipa_eth_client_exist); diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_clients/ipa_gsb.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_clients/ipa_gsb.c new file mode 100644 index 0000000000..d34a4f2424 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_clients/ipa_gsb.c @@ -0,0 +1,1240 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ipa.h" +#include +#include "ipa_odu_bridge.h" +#include "ipa_common_i.h" +#include "ipa_pm.h" +#include "ipa_i.h" + +#define IPA_GSB_DRV_NAME "ipa_gsb" + +#define MAX_SUPPORTED_IFACE 5 + +#define IPA_GSB_DBG(fmt, args...) \ + do { \ + pr_debug(IPA_GSB_DRV_NAME " %s:%d " fmt, \ + __func__, __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf(), \ + IPA_GSB_DRV_NAME " %s:%d " fmt, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf_low(), \ + IPA_GSB_DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) + +#define IPA_GSB_DBG_LOW(fmt, args...) \ + do { \ + pr_debug(IPA_GSB_DRV_NAME " %s:%d " fmt, \ + __func__, __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf_low(), \ + IPA_GSB_DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) + +#define IPA_GSB_ERR(fmt, args...) \ + do { \ + pr_err(IPA_GSB_DRV_NAME " %s:%d " fmt, \ + __func__, __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf(), \ + IPA_GSB_DRV_NAME " %s:%d " fmt, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf_low(), \ + IPA_GSB_DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) + +#define IPA_GSB_ERR_RL(fmt, args...) \ + do { \ + pr_err_ratelimited_ipa(IPA_GSB_DRV_NAME " %s:%d " fmt, \ + __func__, __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf(), \ + IPA_GSB_DRV_NAME " %s:%d " fmt, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf_low(), \ + IPA_GSB_DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) + +#define IPA_GSB_MAX_MSG_LEN 512 + +#ifdef CONFIG_DEBUG_FS +static struct dentry *dent; +static struct dentry *dfile_stats; +static char dbg_buff[IPA_GSB_MAX_MSG_LEN]; +#endif + +#define IPA_GSB_SKB_HEADROOM 256 +#define IPA_GSB_SKB_DUMMY_HEADER 42 +#define IPA_GSB_AGGR_BYTE_LIMIT 14 +#define IPA_GSB_AGGR_TIME_LIMIT 1000 /* 1000 us */ + + +/** + * struct stats - driver statistics, + * @num_ul_packets: number of uplink packets + * @num_dl_packets: number of downlink packets + * @num_insufficient_headroom_packets: number of + packets with insufficient headroom + */ +struct stats { + u64 num_ul_packets; + u64 num_dl_packets; + u64 num_insufficient_headroom_packets; +}; + +/** + * struct ipa_gsb_mux_hdr - ipa gsb mux header, + * @iface_hdl: interface handle + * @qmap_id: qmap id + * @pkt_size: packet size + */ +struct ipa_gsb_mux_hdr { + u8 iface_hdl; + u8 qmap_id; + u16 pkt_size; +}; + +/** + * struct ipa_gsb_iface_info - GSB interface information + * @netdev_name: network interface name + * @device_ethaddr: network interface ethernet address + * @priv: client's private data. to be used in client's callbacks + * @tx_dp_notify: client callback for handling IPA ODU_PROD callback + * @send_dl_skb: client callback for sending skb in downlink direction + * @iface_stats: statistics, how many packets were transmitted + * using the SW bridge. + * @partial_hdr_hdl: handle for partial header + * @wakeup_request: client callback to wakeup + * @is_conencted: is interface connected ? + * @is_resumed: is interface resumed ? + * @iface_hdl: interface handle + */ +struct ipa_gsb_iface_info { + char netdev_name[IPA_RESOURCE_NAME_MAX]; + u8 device_ethaddr[ETH_ALEN]; + void *priv; + ipa_notify_cb tx_dp_notify; + int (*send_dl_skb)(void *priv, struct sk_buff *skb); + struct stats iface_stats; + uint32_t partial_hdr_hdl[IPA_IP_MAX]; + void (*wakeup_request)(void *cl_priv); + bool is_connected; + bool is_resumed; + u8 iface_hdl; +}; + +/** + * struct ipa_gsb_context - GSB driver context information + * @logbuf: buffer of ipc logging + * @logbuf_low: buffer of ipc logging (low priority) + * @lock: global mutex lock for global variables + * @prod_hdl: handle for prod pipe + * @cons_hdl: handle for cons pipe + * @ipa_sys_desc_size: sys pipe desc size + * @num_iface: number of interface + * @iface_hdl: interface handles + * @num_connected_iface: number of connected interface + * @num_resumed_iface: number of resumed interface + * @iface: interface information + * @iface_lock: interface mutex lock for control path + * @iface_spinlock: interface spinlock for data path + * @pm_hdl: IPA PM handle + */ +struct ipa_gsb_context { + void *logbuf; + void *logbuf_low; + struct mutex lock; + u32 prod_hdl; + u32 cons_hdl; + u32 ipa_sys_desc_size; + int num_iface; + bool iface_hdl[MAX_SUPPORTED_IFACE]; + int num_connected_iface; + int num_resumed_iface; + struct ipa_gsb_iface_info *iface[MAX_SUPPORTED_IFACE]; + struct mutex iface_lock[MAX_SUPPORTED_IFACE]; + spinlock_t iface_spinlock[MAX_SUPPORTED_IFACE]; + u32 pm_hdl; + atomic_t disconnect_in_progress; + atomic_t suspend_in_progress; +}; + +static struct ipa_gsb_context *ipa_gsb_ctx; + +#ifdef CONFIG_DEBUG_FS +static ssize_t ipa_gsb_debugfs_stats(struct file *file, + char __user *ubuf, + size_t count, + loff_t *ppos) +{ + int i, nbytes = 0; + struct ipa_gsb_iface_info *iface = NULL; + struct stats iface_stats; + + for (i = 0; i < MAX_SUPPORTED_IFACE; i++) { + iface = ipa_gsb_ctx->iface[i]; + if (iface != NULL) { + iface_stats = iface->iface_stats; + nbytes += scnprintf(&dbg_buff[nbytes], + IPA_GSB_MAX_MSG_LEN - nbytes, + "netdev: %s\n", + iface->netdev_name); + + nbytes += scnprintf(&dbg_buff[nbytes], + IPA_GSB_MAX_MSG_LEN - nbytes, + "UL packets: %lld\n", + iface_stats.num_ul_packets); + + nbytes += scnprintf(&dbg_buff[nbytes], + IPA_GSB_MAX_MSG_LEN - nbytes, + "DL packets: %lld\n", + iface_stats.num_dl_packets); + + nbytes += scnprintf(&dbg_buff[nbytes], + IPA_GSB_MAX_MSG_LEN - nbytes, + "packets with insufficient headroom: %lld\n", + iface_stats.num_insufficient_headroom_packets); + } + } + return simple_read_from_buffer(ubuf, count, ppos, dbg_buff, nbytes); +} + +static const struct file_operations ipa_gsb_stats_ops = { + .read = ipa_gsb_debugfs_stats, +}; + +static void ipa_gsb_debugfs_init(void) +{ + const mode_t read_only_mode = 00444; + + dent = debugfs_create_dir("ipa_gsb", NULL); + if (!dent) { + IPA_GSB_ERR("fail to create folder ipa_gsb\n"); + return; + } + + dfile_stats = + debugfs_create_file("stats", read_only_mode, dent, + NULL, &ipa_gsb_stats_ops); + if (!dfile_stats || IS_ERR(dfile_stats)) { + IPA_GSB_ERR("fail to create file stats\n"); + goto fail; + } + + return; + +fail: + debugfs_remove_recursive(dent); +} + +static void ipa_gsb_debugfs_destroy(void) +{ + debugfs_remove_recursive(dent); +} +#else +static void ipa_gsb_debugfs_init(void) +{ +} + +static void ipa_gsb_debugfs_destroy(void) +{ +} +#endif + +static int ipa_gsb_driver_init(struct odu_bridge_params *params) +{ + int i; + + if (!ipa_is_ready()) { + IPA_GSB_ERR("IPA is not ready\n"); + return -EFAULT; + } + + ipa_gsb_ctx = kzalloc(sizeof(*ipa_gsb_ctx), + GFP_KERNEL); + + if (!ipa_gsb_ctx) + return -ENOMEM; + + mutex_init(&ipa_gsb_ctx->lock); + for (i = 0; i < MAX_SUPPORTED_IFACE; i++) { + mutex_init(&ipa_gsb_ctx->iface_lock[i]); + spin_lock_init(&ipa_gsb_ctx->iface_spinlock[i]); + } + ipa_gsb_debugfs_init(); + + return 0; +} + +static int ipa_gsb_commit_partial_hdr(struct ipa_gsb_iface_info *iface_info) +{ + int i; + struct ipa_ioc_add_hdr *hdr; + + if (!iface_info) { + IPA_GSB_ERR("invalid input\n"); + return -EINVAL; + } + + hdr = kzalloc(sizeof(struct ipa_ioc_add_hdr) + + 2 * sizeof(struct ipa_hdr_add), GFP_KERNEL); + if (!hdr) + return -ENOMEM; + + hdr->commit = 0; + hdr->num_hdrs = 2; + + snprintf(hdr->hdr[0].name, sizeof(hdr->hdr[0].name), + "%s_ipv4", iface_info->netdev_name); + snprintf(hdr->hdr[1].name, sizeof(hdr->hdr[1].name), + "%s_ipv6", iface_info->netdev_name); + /* + * partial header: + * [hdl][QMAP ID][pkt size][Dummy Header][ETH header] + */ + for (i = IPA_IP_v4; i < IPA_IP_MAX; i++) { + /* + * Optimization: add dummy header to reserve space + * for rndis header, so we can do the skb_clone + * instead of deep copy. + */ + hdr->hdr[i].hdr_len = ETH_HLEN + + sizeof(struct ipa_gsb_mux_hdr) + + IPA_GSB_SKB_DUMMY_HEADER; + hdr->hdr[i].type = IPA_HDR_L2_ETHERNET_II; + hdr->hdr[i].is_partial = 1; + hdr->hdr[i].is_eth2_ofst_valid = 1; + hdr->hdr[i].eth2_ofst = sizeof(struct ipa_gsb_mux_hdr) + + IPA_GSB_SKB_DUMMY_HEADER; + /* populate iface handle */ + hdr->hdr[i].hdr[0] = iface_info->iface_hdl; + /* populate src ETH address */ + memcpy(&hdr->hdr[i].hdr[10 + IPA_GSB_SKB_DUMMY_HEADER], + iface_info->device_ethaddr, 6); + /* populate Ethertype */ + if (i == IPA_IP_v4) + *(u16 *)(hdr->hdr[i].hdr + 16 + + IPA_GSB_SKB_DUMMY_HEADER) = htons(ETH_P_IP); + else + *(u16 *)(hdr->hdr[i].hdr + 16 + + IPA_GSB_SKB_DUMMY_HEADER) = htons(ETH_P_IPV6); + } + + if (ipa_add_hdr(hdr)) { + IPA_GSB_ERR("fail to add partial headers\n"); + kfree(hdr); + return -EFAULT; + } + + for (i = IPA_IP_v4; i < IPA_IP_MAX; i++) + iface_info->partial_hdr_hdl[i] = + hdr->hdr[i].hdr_hdl; + + IPA_GSB_DBG("added partial hdr hdl for ipv4: %d\n", + iface_info->partial_hdr_hdl[IPA_IP_v4]); + IPA_GSB_DBG("added partial hdr hdl for ipv6: %d\n", + iface_info->partial_hdr_hdl[IPA_IP_v6]); + + kfree(hdr); + return 0; +} + +static void ipa_gsb_delete_partial_hdr(struct ipa_gsb_iface_info *iface_info) +{ + struct ipa_ioc_del_hdr *del_hdr; + + del_hdr = kzalloc(sizeof(struct ipa_ioc_del_hdr) + + 2 * sizeof(struct ipa_hdr_del), GFP_KERNEL); + if (!del_hdr) + return; + + del_hdr->commit = 1; + del_hdr->num_hdls = 2; + del_hdr->hdl[IPA_IP_v4].hdl = iface_info->partial_hdr_hdl[IPA_IP_v4]; + del_hdr->hdl[IPA_IP_v6].hdl = iface_info->partial_hdr_hdl[IPA_IP_v6]; + + if (ipa_del_hdr(del_hdr) != 0) + IPA_GSB_ERR("failed to delete partial hdr\n"); + + IPA_GSB_DBG("deleted partial hdr hdl for ipv4: %d\n", + iface_info->partial_hdr_hdl[IPA_IP_v4]); + IPA_GSB_DBG("deleted partial hdr hdl for ipv6: %d\n", + iface_info->partial_hdr_hdl[IPA_IP_v6]); + + kfree(del_hdr); +} + +static int ipa_gsb_reg_intf_props(struct ipa_gsb_iface_info *iface_info) +{ + struct ipa_tx_intf tx; + struct ipa_rx_intf rx; + struct ipa_ioc_tx_intf_prop tx_prop[2]; + struct ipa_ioc_rx_intf_prop rx_prop[2]; + + /* populate tx prop */ + tx.num_props = 2; + tx.prop = tx_prop; + + memset(tx_prop, 0, sizeof(tx_prop)); + tx_prop[0].ip = IPA_IP_v4; + tx_prop[0].dst_pipe = IPA_CLIENT_ODU_EMB_CONS; + tx_prop[0].hdr_l2_type = IPA_HDR_L2_ETHERNET_II; + snprintf(tx_prop[0].hdr_name, sizeof(tx_prop[0].hdr_name), + "%s_ipv4", iface_info->netdev_name); + + tx_prop[1].ip = IPA_IP_v6; + tx_prop[1].dst_pipe = IPA_CLIENT_ODU_EMB_CONS; + tx_prop[1].hdr_l2_type = IPA_HDR_L2_ETHERNET_II; + snprintf(tx_prop[1].hdr_name, sizeof(tx_prop[1].hdr_name), + "%s_ipv6", iface_info->netdev_name); + + /* populate rx prop */ + rx.num_props = 2; + rx.prop = rx_prop; + + memset(rx_prop, 0, sizeof(rx_prop)); + rx_prop[0].ip = IPA_IP_v4; + rx_prop[0].src_pipe = IPA_CLIENT_ODU_PROD; + rx_prop[0].hdr_l2_type = IPA_HDR_L2_ETHERNET_II; + rx_prop[0].attrib.attrib_mask |= IPA_FLT_META_DATA; + rx_prop[0].attrib.meta_data = iface_info->iface_hdl; + rx_prop[0].attrib.meta_data_mask = 0xFF; + + rx_prop[1].ip = IPA_IP_v6; + rx_prop[1].src_pipe = IPA_CLIENT_ODU_PROD; + rx_prop[1].hdr_l2_type = IPA_HDR_L2_ETHERNET_II; + rx_prop[1].attrib.attrib_mask |= IPA_FLT_META_DATA; + rx_prop[1].attrib.meta_data = iface_info->iface_hdl; + rx_prop[1].attrib.meta_data_mask = 0xFF; + + if (ipa_register_intf(iface_info->netdev_name, &tx, &rx)) { + IPA_GSB_ERR("fail to add interface prop\n"); + return -EFAULT; + } + + return 0; +} + +static void ipa_gsb_dereg_intf_props(struct ipa_gsb_iface_info *iface_info) +{ + if (ipa_deregister_intf(iface_info->netdev_name) != 0) + IPA_GSB_ERR("fail to dereg intf props\n"); + + IPA_GSB_DBG("deregistered iface props for %s\n", + iface_info->netdev_name); +} + +static void ipa_gsb_pm_cb(void *user_data, enum ipa_pm_cb_event event) +{ + int i; + + if (event != IPA_PM_REQUEST_WAKEUP) { + IPA_GSB_ERR("Unexpected event %d\n", event); + WARN_ON(1); + return; + } + + IPA_GSB_DBG_LOW("wake up clients\n"); + for (i = 0; i < MAX_SUPPORTED_IFACE; i++) + if (ipa_gsb_ctx->iface[i] != NULL) + ipa_gsb_ctx->iface[i]->wakeup_request( + ipa_gsb_ctx->iface[i]->priv); +} + +static int ipa_gsb_register_pm(void) +{ + struct ipa_pm_register_params reg_params; + int ret; + + memset(®_params, 0, sizeof(reg_params)); + reg_params.name = "ipa_gsb"; + reg_params.callback = ipa_gsb_pm_cb; + reg_params.user_data = NULL; + reg_params.group = IPA_PM_GROUP_DEFAULT; + + ret = ipa_pm_register(®_params, + &ipa_gsb_ctx->pm_hdl); + if (ret) { + IPA_GSB_ERR("fail to register with PM %d\n", ret); + goto fail_pm_reg; + } + IPA_GSB_DBG("ipa pm hdl: %d\n", ipa_gsb_ctx->pm_hdl); + + ret = ipa_pm_associate_ipa_cons_to_client(ipa_gsb_ctx->pm_hdl, + IPA_CLIENT_ODU_EMB_CONS); + if (ret) { + IPA_GSB_ERR("fail to associate cons with PM %d\n", ret); + goto fail_pm_cons; + } + + return 0; + +fail_pm_cons: + ipa_pm_deregister(ipa_gsb_ctx->pm_hdl); + ipa_gsb_ctx->pm_hdl = ~0; +fail_pm_reg: + return ret; +} + +int ipa_bridge_init(struct ipa_bridge_init_params *params, u32 *hdl) +{ + int i, ret; + struct ipa_gsb_iface_info *new_intf; + + if (!params || !params->wakeup_request || !hdl || + !params->info.netdev_name || !params->info.tx_dp_notify || + !params->info.send_dl_skb) { + IPA_GSB_ERR("Invalid parameters\n"); + return -EINVAL; + } + + IPA_GSB_DBG("netdev_name: %s\n", params->info.netdev_name); + + if (ipa_gsb_ctx == NULL) { + ret = ipa_gsb_driver_init(¶ms->info); + if (ret) { + IPA_GSB_ERR("fail to init ipa gsb driver\n"); + return -EFAULT; + } + ipa_gsb_ctx->ipa_sys_desc_size = + params->info.ipa_desc_size; + IPA_GSB_DBG("desc size: %d\n", ipa_gsb_ctx->ipa_sys_desc_size); + } + + mutex_lock(&ipa_gsb_ctx->lock); + + if (params->info.ipa_desc_size != ipa_gsb_ctx->ipa_sys_desc_size) { + IPA_GSB_ERR("unmatch: orig desc size %d, new desc size %d\n", + ipa_gsb_ctx->ipa_sys_desc_size, + params->info.ipa_desc_size); + mutex_unlock(&ipa_gsb_ctx->lock); + return -EFAULT; + } + + for (i = 0; i < MAX_SUPPORTED_IFACE; i++) + if (ipa_gsb_ctx->iface[i] != NULL && + strnlen(ipa_gsb_ctx->iface[i]->netdev_name, + IPA_RESOURCE_NAME_MAX) == + strnlen(params->info.netdev_name, + IPA_RESOURCE_NAME_MAX) && + strcmp(ipa_gsb_ctx->iface[i]->netdev_name, + params->info.netdev_name) == 0) { + IPA_GSB_ERR("intf was added before.\n"); + mutex_unlock(&ipa_gsb_ctx->lock); + return -EFAULT; + } + + if (ipa_gsb_ctx->num_iface == MAX_SUPPORTED_IFACE) { + IPA_GSB_ERR("reached maximum supported interfaces"); + mutex_unlock(&ipa_gsb_ctx->lock); + return -EFAULT; + } + + for (i = 0; i < MAX_SUPPORTED_IFACE; i++) + if (!ipa_gsb_ctx->iface_hdl[i]) { + ipa_gsb_ctx->iface_hdl[i] = true; + *hdl = i; + IPA_GSB_DBG("iface hdl: %d\n", *hdl); + break; + } + + IPA_GSB_DBG("intf was not added before, proceed.\n"); + new_intf = kzalloc(sizeof(*new_intf), GFP_KERNEL); + if (new_intf == NULL) { + ret = -ENOMEM; + goto fail_alloc_mem; + } + + strlcpy(new_intf->netdev_name, params->info.netdev_name, + sizeof(new_intf->netdev_name)); + new_intf->wakeup_request = params->wakeup_request; + new_intf->priv = params->info.priv; + new_intf->tx_dp_notify = params->info.tx_dp_notify; + new_intf->send_dl_skb = params->info.send_dl_skb; + new_intf->iface_hdl = *hdl; + memcpy(new_intf->device_ethaddr, params->info.device_ethaddr, + sizeof(new_intf->device_ethaddr)); + + if (ipa_gsb_commit_partial_hdr(new_intf) != 0) { + IPA_GSB_ERR("fail to commit partial hdrs\n"); + ret = -EFAULT; + goto fail_partial_hdr; + } + + if (ipa_gsb_reg_intf_props(new_intf) != 0) { + IPA_GSB_ERR("fail to register interface props\n"); + ret = -EFAULT; + goto fail_reg_intf_props; + } + + if (ipa_gsb_ctx->num_iface == 0) { + ret = ipa_gsb_register_pm(); + if (ret) { + IPA_GSB_ERR("fail to register with IPA PM %d\n", ret); + ret = -EFAULT; + goto fail_register_pm; + } + } + + ipa_gsb_ctx->iface[*hdl] = new_intf; + ipa_gsb_ctx->num_iface++; + IPA_GSB_DBG("num_iface %d\n", ipa_gsb_ctx->num_iface); + mutex_unlock(&ipa_gsb_ctx->lock); + return 0; + +fail_register_pm: + ipa_gsb_dereg_intf_props(new_intf); +fail_reg_intf_props: + ipa_gsb_delete_partial_hdr(new_intf); +fail_partial_hdr: + kfree(new_intf); +fail_alloc_mem: + ipa_gsb_ctx->iface_hdl[*hdl] = false; + mutex_unlock(&ipa_gsb_ctx->lock); + return ret; +} +EXPORT_SYMBOL(ipa_bridge_init); + +static void ipa_gsb_deregister_pm(void) +{ + IPA_GSB_DBG("deregister ipa pm hdl: %d\n", ipa_gsb_ctx->pm_hdl); + ipa_pm_deactivate_sync(ipa_gsb_ctx->pm_hdl); + ipa_pm_deregister(ipa_gsb_ctx->pm_hdl); + ipa_gsb_ctx->pm_hdl = ~0; +} + +int ipa_bridge_cleanup(u32 hdl) +{ + int i; + + if (!ipa_gsb_ctx) { + IPA_GSB_ERR("ipa_gsb_ctx was not initialized\n"); + return -EFAULT; + } + + if (hdl >= MAX_SUPPORTED_IFACE) { + IPA_GSB_ERR("invalid hdl: %d\n", hdl); + return -EINVAL; + } + + mutex_lock(&ipa_gsb_ctx->iface_lock[hdl]); + if (!ipa_gsb_ctx->iface[hdl]) { + IPA_GSB_ERR("fail to find interface, hdl: %d\n", hdl); + mutex_unlock(&ipa_gsb_ctx->iface_lock[hdl]); + return -EFAULT; + } + + IPA_GSB_DBG("client hdl: %d\n", hdl); + + if (ipa_gsb_ctx->iface[hdl]->is_connected) { + IPA_GSB_ERR("cannot cleanup when iface is connected\n"); + mutex_unlock(&ipa_gsb_ctx->iface_lock[hdl]); + return -EFAULT; + } + ipa_gsb_dereg_intf_props(ipa_gsb_ctx->iface[hdl]); + ipa_gsb_delete_partial_hdr(ipa_gsb_ctx->iface[hdl]); + spin_lock_bh(&ipa_gsb_ctx->iface_spinlock[hdl]); + kfree(ipa_gsb_ctx->iface[hdl]); + ipa_gsb_ctx->iface[hdl] = NULL; + ipa_gsb_ctx->iface_hdl[hdl] = false; + spin_unlock_bh(&ipa_gsb_ctx->iface_spinlock[hdl]); + mutex_unlock(&ipa_gsb_ctx->iface_lock[hdl]); + mutex_lock(&ipa_gsb_ctx->lock); + ipa_gsb_ctx->num_iface--; + IPA_GSB_DBG("num_iface %d\n", ipa_gsb_ctx->num_iface); + if (ipa_gsb_ctx->num_iface == 0) { + ipa_gsb_deregister_pm(); + ipa_gsb_debugfs_destroy(); + ipc_log_context_destroy(ipa_gsb_ctx->logbuf); + ipc_log_context_destroy(ipa_gsb_ctx->logbuf_low); + mutex_unlock(&ipa_gsb_ctx->lock); + mutex_destroy(&ipa_gsb_ctx->lock); + for (i = 0; i < MAX_SUPPORTED_IFACE; i++) + mutex_destroy(&ipa_gsb_ctx->iface_lock[i]); + kfree(ipa_gsb_ctx); + ipa_gsb_ctx = NULL; + return 0; + } + mutex_unlock(&ipa_gsb_ctx->lock); + return 0; +} +EXPORT_SYMBOL(ipa_bridge_cleanup); + +static void ipa_gsb_cons_cb(void *priv, enum ipa_dp_evt_type evt, + unsigned long data) +{ + struct sk_buff *skb; + struct sk_buff *skb2; + struct ipa_gsb_mux_hdr *mux_hdr; + u16 pkt_size, pad_byte; + u8 hdl; + + if (evt != IPA_RECEIVE) { + IPA_GSB_ERR("unexpected event\n"); + WARN_ON(1); + return; + } + + skb = (struct sk_buff *)data; + + if (skb == NULL) { + IPA_GSB_ERR("unexpected NULL data\n"); + WARN_ON(1); + return; + } + + while (skb->len) { + mux_hdr = (struct ipa_gsb_mux_hdr *)skb->data; + pkt_size = mux_hdr->pkt_size; + /* 4-byte padding */ + pad_byte = ((pkt_size + sizeof(*mux_hdr) + ETH_HLEN + + 3 + IPA_GSB_SKB_DUMMY_HEADER) & ~3) - + (pkt_size + sizeof(*mux_hdr) + + ETH_HLEN + IPA_GSB_SKB_DUMMY_HEADER); + hdl = mux_hdr->iface_hdl; + if (hdl >= MAX_SUPPORTED_IFACE) { + IPA_GSB_ERR("invalid hdl: %d\n", hdl); + break; + } + IPA_GSB_DBG_LOW("pkt_size: %d, pad_byte: %d, hdl: %d\n", + pkt_size, pad_byte, hdl); + + /* remove 4 byte mux header AND dummy header*/ + skb_pull(skb, sizeof(*mux_hdr) + IPA_GSB_SKB_DUMMY_HEADER); + + skb2 = skb_clone(skb, GFP_KERNEL); + if (!skb2) { + IPA_GSB_ERR("skb_clone failed\n"); + WARN_ON(1); + break; + } + skb_trim(skb2, pkt_size + ETH_HLEN); + spin_lock_bh(&ipa_gsb_ctx->iface_spinlock[hdl]); + if (ipa_gsb_ctx->iface[hdl] != NULL) { + ipa_gsb_ctx->iface[hdl]->send_dl_skb( + ipa_gsb_ctx->iface[hdl]->priv, skb2); + ipa_gsb_ctx->iface[hdl]->iface_stats.num_dl_packets++; + spin_unlock_bh(&ipa_gsb_ctx->iface_spinlock[hdl]); + skb_pull(skb, pkt_size + ETH_HLEN + pad_byte); + } else { + IPA_GSB_ERR("Invalid hdl: %d, drop the skb\n", hdl); + spin_unlock_bh(&ipa_gsb_ctx->iface_spinlock[hdl]); + dev_kfree_skb_any(skb2); + break; + } + } + + if (skb) { + dev_kfree_skb_any(skb); + skb = NULL; + } +} + +static void ipa_gsb_tx_dp_notify(void *priv, enum ipa_dp_evt_type evt, + unsigned long data) +{ + struct sk_buff *skb; + struct ipa_gsb_mux_hdr *mux_hdr; + u8 hdl; + + skb = (struct sk_buff *)data; + + if (skb == NULL) { + IPA_GSB_ERR("unexpected NULL data\n"); + WARN_ON(1); + return; + } + + if (evt != IPA_WRITE_DONE && evt != IPA_RECEIVE) { + IPA_GSB_ERR("unexpected event: %d\n", evt); + dev_kfree_skb_any(skb); + return; + } + + /* fetch iface handle from header */ + mux_hdr = (struct ipa_gsb_mux_hdr *)skb->data; + /* change to host order */ + *(u32 *)mux_hdr = ntohl(*(u32 *)mux_hdr); + hdl = mux_hdr->iface_hdl; + if ((hdl < 0) || (hdl >= MAX_SUPPORTED_IFACE) || + !ipa_gsb_ctx->iface[hdl]) { + IPA_GSB_ERR("invalid hdl: %d and cb, drop the skb\n", hdl); + dev_kfree_skb_any(skb); + return; + } + IPA_GSB_DBG_LOW("evt: %d, hdl in tx_dp_notify: %d\n", evt, hdl); + + /* remove 4 byte mux header */ + skb_pull(skb, sizeof(struct ipa_gsb_mux_hdr)); + ipa_gsb_ctx->iface[hdl]->tx_dp_notify( + ipa_gsb_ctx->iface[hdl]->priv, evt, + (unsigned long)skb); +} + +static int ipa_gsb_connect_sys_pipe(void) +{ + struct ipa_sys_connect_params prod_params; + struct ipa_sys_connect_params cons_params; + int res; + + memset(&prod_params, 0, sizeof(prod_params)); + memset(&cons_params, 0, sizeof(cons_params)); + + /* configure RX EP */ + prod_params.client = IPA_CLIENT_ODU_PROD; + prod_params.ipa_ep_cfg.hdr.hdr_len = + ETH_HLEN + sizeof(struct ipa_gsb_mux_hdr); + prod_params.ipa_ep_cfg.nat.nat_en = IPA_SRC_NAT; + prod_params.ipa_ep_cfg.hdr.hdr_ofst_metadata_valid = 1; + prod_params.ipa_ep_cfg.hdr.hdr_ofst_metadata = 0; + prod_params.desc_fifo_sz = ipa_gsb_ctx->ipa_sys_desc_size; + prod_params.priv = NULL; + prod_params.notify = ipa_gsb_tx_dp_notify; + res = ipa_setup_sys_pipe(&prod_params, + &ipa_gsb_ctx->prod_hdl); + if (res) { + IPA_GSB_ERR("fail to setup prod sys pipe %d\n", res); + goto fail_prod; + } + + /* configure TX EP */ + cons_params.client = IPA_CLIENT_ODU_EMB_CONS; + cons_params.ipa_ep_cfg.hdr.hdr_len = + ETH_HLEN + sizeof(struct ipa_gsb_mux_hdr) + + IPA_GSB_SKB_DUMMY_HEADER; + cons_params.ipa_ep_cfg.hdr.hdr_ofst_pkt_size_valid = 1; + cons_params.ipa_ep_cfg.hdr.hdr_ofst_pkt_size = 2; + cons_params.ipa_ep_cfg.hdr_ext.hdr_pad_to_alignment = 2; + cons_params.ipa_ep_cfg.hdr_ext.hdr_little_endian = true; + cons_params.ipa_ep_cfg.nat.nat_en = IPA_BYPASS_NAT; + /* setup aggregation */ + cons_params.ipa_ep_cfg.aggr.aggr_en = IPA_ENABLE_AGGR; + cons_params.ipa_ep_cfg.aggr.aggr = IPA_GENERIC; + cons_params.ipa_ep_cfg.aggr.aggr_time_limit = + IPA_GSB_AGGR_TIME_LIMIT; + cons_params.ipa_ep_cfg.aggr.aggr_byte_limit = + IPA_GSB_AGGR_BYTE_LIMIT; + cons_params.desc_fifo_sz = ipa_gsb_ctx->ipa_sys_desc_size; + cons_params.priv = NULL; + cons_params.notify = ipa_gsb_cons_cb; + res = ipa_setup_sys_pipe(&cons_params, + &ipa_gsb_ctx->cons_hdl); + if (res) { + IPA_GSB_ERR("fail to setup cons sys pipe %d\n", res); + goto fail_cons; + } + + IPA_GSB_DBG("prod_hdl = %d, cons_hdl = %d\n", + ipa_gsb_ctx->prod_hdl, ipa_gsb_ctx->cons_hdl); + + return 0; + +fail_cons: + ipa_teardown_sys_pipe(ipa_gsb_ctx->prod_hdl); + ipa_gsb_ctx->prod_hdl = 0; +fail_prod: + return res; +} + +int ipa_bridge_connect(u32 hdl) +{ + int ret; + + if (!ipa_gsb_ctx) { + IPA_GSB_ERR("ipa_gsb_ctx was not initialized\n"); + return -EFAULT; + } + + if (hdl >= MAX_SUPPORTED_IFACE) { + IPA_GSB_ERR("invalid hdl: %d\n", hdl); + return -EINVAL; + } + + IPA_GSB_DBG("client hdl: %d\n", hdl); + + mutex_lock(&ipa_gsb_ctx->iface_lock[hdl]); + if (!ipa_gsb_ctx->iface[hdl]) { + IPA_GSB_ERR("fail to find interface, hdl: %d\n", hdl); + mutex_unlock(&ipa_gsb_ctx->iface_lock[hdl]); + return -EFAULT; + } + + if (ipa_gsb_ctx->iface[hdl]->is_connected) { + IPA_GSB_DBG("iface was already connected\n"); + mutex_unlock(&ipa_gsb_ctx->iface_lock[hdl]); + return 0; + } + + mutex_lock(&ipa_gsb_ctx->lock); + if (ipa_gsb_ctx->num_connected_iface == 0) { + ret = ipa_pm_activate_sync(ipa_gsb_ctx->pm_hdl); + if (ret) { + IPA_GSB_ERR("failed to activate ipa pm\n"); + mutex_unlock(&ipa_gsb_ctx->lock); + mutex_unlock(&ipa_gsb_ctx->iface_lock[hdl]); + return ret; + } + ret = ipa_gsb_connect_sys_pipe(); + if (ret) { + IPA_GSB_ERR("fail to connect pipe\n"); + mutex_unlock(&ipa_gsb_ctx->lock); + mutex_unlock(&ipa_gsb_ctx->iface_lock[hdl]); + return ret; + } + } + + /* connect = connect + resume */ + ipa_gsb_ctx->iface[hdl]->is_connected = true; + ipa_gsb_ctx->iface[hdl]->is_resumed = true; + + ipa_gsb_ctx->num_connected_iface++; + IPA_GSB_DBG("connected iface: %d\n", + ipa_gsb_ctx->num_connected_iface); + ipa_gsb_ctx->num_resumed_iface++; + IPA_GSB_DBG("num resumed iface: %d\n", + ipa_gsb_ctx->num_resumed_iface); + mutex_unlock(&ipa_gsb_ctx->lock); + mutex_unlock(&ipa_gsb_ctx->iface_lock[hdl]); + return 0; +} +EXPORT_SYMBOL(ipa_bridge_connect); + +static int ipa_gsb_disconnect_sys_pipe(void) +{ + int ret; + + IPA_GSB_DBG("prod_hdl = %d, cons_hdl = %d\n", + ipa_gsb_ctx->prod_hdl, ipa_gsb_ctx->cons_hdl); + + ret = ipa_teardown_sys_pipe(ipa_gsb_ctx->prod_hdl); + if (ret) { + IPA_GSB_ERR("failed to tear down prod pipe\n"); + return -EFAULT; + } + ipa_gsb_ctx->prod_hdl = 0; + + ret = ipa_teardown_sys_pipe(ipa_gsb_ctx->cons_hdl); + if (ret) { + IPA_GSB_ERR("failed to tear down cons pipe\n"); + return -EFAULT; + } + ipa_gsb_ctx->cons_hdl = 0; + + return 0; +} + +int ipa_bridge_disconnect(u32 hdl) +{ + int ret = 0; + + if (!ipa_gsb_ctx) { + IPA_GSB_ERR("ipa_gsb_ctx was not initialized\n"); + return -EFAULT; + } + + if (hdl >= MAX_SUPPORTED_IFACE) { + IPA_GSB_ERR("invalid hdl: %d\n", hdl); + return -EINVAL; + } + + IPA_GSB_DBG("client hdl: %d\n", hdl); + + mutex_lock(&ipa_gsb_ctx->iface_lock[hdl]); + atomic_set(&ipa_gsb_ctx->disconnect_in_progress, 1); + + if (!ipa_gsb_ctx->iface[hdl]) { + IPA_GSB_ERR("fail to find interface, hdl: %d\n", hdl); + ret = -EFAULT; + goto fail; + } + + if (!ipa_gsb_ctx->iface[hdl]->is_connected) { + IPA_GSB_DBG("iface was not connected\n"); + ret = 0; + goto fail; + } + + mutex_lock(&ipa_gsb_ctx->lock); + if (ipa_gsb_ctx->num_connected_iface == 1) { + ret = ipa_gsb_disconnect_sys_pipe(); + if (ret) { + IPA_GSB_ERR("fail to discon pipes\n"); + ret = -EFAULT; + goto fail; + } + + ret = ipa_pm_deactivate_sync(ipa_gsb_ctx->pm_hdl); + if (ret) { + IPA_GSB_ERR("failed to deactivate ipa pm\n"); + ret = -EFAULT; + goto fail; + } + } + + /* disconnect = suspend + disconnect */ + ipa_gsb_ctx->iface[hdl]->is_connected = false; + ipa_gsb_ctx->num_connected_iface--; + IPA_GSB_DBG("connected iface: %d\n", + ipa_gsb_ctx->num_connected_iface); + + if (ipa_gsb_ctx->iface[hdl]->is_resumed) { + ipa_gsb_ctx->iface[hdl]->is_resumed = false; + ipa_gsb_ctx->num_resumed_iface--; + IPA_GSB_DBG("num resumed iface: %d\n", + ipa_gsb_ctx->num_resumed_iface); + } + +fail: + mutex_unlock(&ipa_gsb_ctx->lock); + atomic_set(&ipa_gsb_ctx->disconnect_in_progress, 0); + mutex_unlock(&ipa_gsb_ctx->iface_lock[hdl]); + return ret; +} +EXPORT_SYMBOL(ipa_bridge_disconnect); + +int ipa_bridge_resume(u32 hdl) +{ + int ret; + + if (!ipa_gsb_ctx) { + IPA_GSB_ERR("ipa_gsb_ctx was not initialized\n"); + return -EFAULT; + } + + if (hdl >= MAX_SUPPORTED_IFACE) { + IPA_GSB_ERR("invalid hdl: %d\n", hdl); + return -EINVAL; + } + + IPA_GSB_DBG_LOW("client hdl: %d\n", hdl); + + mutex_lock(&ipa_gsb_ctx->iface_lock[hdl]); + if (!ipa_gsb_ctx->iface[hdl]) { + IPA_GSB_ERR("fail to find interface, hdl: %d\n", hdl); + mutex_unlock(&ipa_gsb_ctx->iface_lock[hdl]); + return -EFAULT; + } + + if (!ipa_gsb_ctx->iface[hdl]->is_connected) { + IPA_GSB_ERR("iface is not connected\n"); + mutex_unlock(&ipa_gsb_ctx->iface_lock[hdl]); + return -EFAULT; + } + + if (ipa_gsb_ctx->iface[hdl]->is_resumed) { + IPA_GSB_DBG_LOW("iface was already resumed\n"); + mutex_unlock(&ipa_gsb_ctx->iface_lock[hdl]); + return 0; + } + + mutex_lock(&ipa_gsb_ctx->lock); + if (ipa_gsb_ctx->num_resumed_iface == 0) { + ret = ipa_pm_activate_sync(ipa_gsb_ctx->pm_hdl); + if (ret) { + IPA_GSB_ERR("fail to activate ipa pm\n"); + mutex_unlock(&ipa_gsb_ctx->lock); + mutex_unlock(&ipa_gsb_ctx->iface_lock[hdl]); + return ret; + } + + ret = ipa3_start_gsi_channel( + ipa_gsb_ctx->cons_hdl); + if (ret) { + IPA_GSB_ERR( + "fail to start con ep %d\n", + ret); + mutex_unlock(&ipa_gsb_ctx->lock); + mutex_unlock(&ipa_gsb_ctx->iface_lock[hdl]); + return ret; + } + } + + ipa_gsb_ctx->iface[hdl]->is_resumed = true; + ipa_gsb_ctx->num_resumed_iface++; + IPA_GSB_DBG_LOW("num resumed iface: %d\n", + ipa_gsb_ctx->num_resumed_iface); + + mutex_unlock(&ipa_gsb_ctx->lock); + mutex_unlock(&ipa_gsb_ctx->iface_lock[hdl]); + return 0; +} +EXPORT_SYMBOL(ipa_bridge_resume); + +int ipa_bridge_suspend(u32 hdl) +{ + int ret; + + if (!ipa_gsb_ctx) { + IPA_GSB_ERR("ipa_gsb_ctx was not initialized\n"); + return -EFAULT; + } + + if (hdl >= MAX_SUPPORTED_IFACE) { + IPA_GSB_ERR("invalid hdl: %d\n", hdl); + return -EINVAL; + } + + IPA_GSB_DBG_LOW("client hdl: %d\n", hdl); + + mutex_lock(&ipa_gsb_ctx->iface_lock[hdl]); + atomic_set(&ipa_gsb_ctx->suspend_in_progress, 1); + if (!ipa_gsb_ctx->iface[hdl]) { + IPA_GSB_ERR("fail to find interface, hdl: %d\n", hdl); + atomic_set(&ipa_gsb_ctx->suspend_in_progress, 0); + mutex_unlock(&ipa_gsb_ctx->iface_lock[hdl]); + return -EFAULT; + } + + if (!ipa_gsb_ctx->iface[hdl]->is_connected) { + IPA_GSB_ERR("iface is not connected\n"); + atomic_set(&ipa_gsb_ctx->suspend_in_progress, 0); + mutex_unlock(&ipa_gsb_ctx->iface_lock[hdl]); + return -EFAULT; + } + + if (!ipa_gsb_ctx->iface[hdl]->is_resumed) { + IPA_GSB_DBG_LOW("iface was already suspended\n"); + atomic_set(&ipa_gsb_ctx->suspend_in_progress, 0); + mutex_unlock(&ipa_gsb_ctx->iface_lock[hdl]); + return 0; + } + + mutex_lock(&ipa_gsb_ctx->lock); + if (ipa_gsb_ctx->num_resumed_iface == 1) { + ret = ipa_stop_gsi_channel( + ipa_gsb_ctx->cons_hdl); + if (ret) { + IPA_GSB_ERR( + "fail to stop cons ep %d\n", + ret); + atomic_set(&ipa_gsb_ctx->suspend_in_progress, 0); + mutex_unlock(&ipa_gsb_ctx->lock); + mutex_unlock(&ipa_gsb_ctx->iface_lock[hdl]); + return ret; + } + + ret = ipa_pm_deactivate_sync(ipa_gsb_ctx->pm_hdl); + if (ret) { + IPA_GSB_ERR("fail to deactivate ipa pm\n"); + ipa3_start_gsi_channel(ipa_gsb_ctx->cons_hdl); + atomic_set(&ipa_gsb_ctx->suspend_in_progress, 0); + mutex_unlock(&ipa_gsb_ctx->lock); + mutex_unlock(&ipa_gsb_ctx->iface_lock[hdl]); + return ret; + } + } + + ipa_gsb_ctx->iface[hdl]->is_resumed = false; + ipa_gsb_ctx->num_resumed_iface--; + IPA_GSB_DBG_LOW("num resumed iface: %d\n", + ipa_gsb_ctx->num_resumed_iface); + atomic_set(&ipa_gsb_ctx->suspend_in_progress, 0); + mutex_unlock(&ipa_gsb_ctx->lock); + mutex_unlock(&ipa_gsb_ctx->iface_lock[hdl]); + return 0; +} +EXPORT_SYMBOL(ipa_bridge_suspend); + +int ipa_bridge_set_perf_profile(u32 hdl, u32 bandwidth) +{ + int ret; + + if (!ipa_gsb_ctx) { + IPA_GSB_ERR("ipa_gsb_ctx was not initialized\n"); + return -EFAULT; + } + + if (hdl >= MAX_SUPPORTED_IFACE) { + IPA_GSB_ERR("invalid hdl: %d\n", hdl); + return -EINVAL; + } + + IPA_GSB_DBG("client hdl: %d, BW: %d\n", hdl, bandwidth); + + mutex_lock(&ipa_gsb_ctx->iface_lock[hdl]); + + ret = ipa_pm_set_throughput(ipa_gsb_ctx->pm_hdl, + bandwidth); + if (ret) + IPA_GSB_ERR("fail to set perf profile\n"); + + mutex_unlock(&ipa_gsb_ctx->iface_lock[hdl]); + return ret; +} +EXPORT_SYMBOL(ipa_bridge_set_perf_profile); + +int ipa_bridge_tx_dp(u32 hdl, struct sk_buff *skb, + struct ipa_tx_meta *metadata) +{ + struct ipa_gsb_mux_hdr *mux_hdr; + struct sk_buff *skb2; + struct stats iface_stats; + int ret; + + IPA_GSB_DBG_LOW("client hdl: %d\n", hdl); + + iface_stats = ipa_gsb_ctx->iface[hdl]->iface_stats; + if (!ipa_gsb_ctx->iface[hdl]) { + IPA_GSB_ERR("fail to find interface, hdl: %d\n", hdl); + return -EFAULT; + } + + if (unlikely(atomic_read(&ipa_gsb_ctx->disconnect_in_progress))) { + IPA_GSB_ERR("ipa bridge disconnect_in_progress\n"); + return -EFAULT; + } + + if (unlikely(atomic_read(&ipa_gsb_ctx->suspend_in_progress))) { + IPA_GSB_ERR("ipa bridge suspend_in_progress\n"); + return -EFAULT; + } + + if (unlikely(!ipa_gsb_ctx->iface[hdl]->is_resumed)) { + IPA_GSB_ERR_RL("iface %d was suspended\n", hdl); + return -EFAULT; + } + + /* make sure skb has enough headroom */ + if (unlikely(skb_headroom(skb) < sizeof(struct ipa_gsb_mux_hdr))) { + IPA_GSB_DBG_LOW("skb doesn't have enough headroom\n"); + skb2 = skb_copy_expand(skb, sizeof(struct ipa_gsb_mux_hdr), + 0, GFP_ATOMIC); + if (!skb2) { + dev_kfree_skb_any(skb); + return -ENOMEM; + } + dev_kfree_skb_any(skb); + skb = skb2; + iface_stats.num_insufficient_headroom_packets++; + } + + /* add 4 byte header for mux */ + mux_hdr = (struct ipa_gsb_mux_hdr *)skb_push(skb, + sizeof(struct ipa_gsb_mux_hdr)); + mux_hdr->iface_hdl = (u8)hdl; + /* change to network order */ + *(u32 *)mux_hdr = htonl(*(u32 *)mux_hdr); + + ret = ipa_tx_dp(IPA_CLIENT_ODU_PROD, skb, metadata); + if (ret) { + IPA_GSB_ERR("tx dp failed %d\n", ret); + return -EFAULT; + } + ipa_gsb_ctx->iface[hdl]->iface_stats.num_ul_packets++; + + return 0; +} +EXPORT_SYMBOL(ipa_bridge_tx_dp); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("ipa gsb driver"); diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_clients/ipa_mhi_client.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_clients/ipa_mhi_client.c new file mode 100644 index 0000000000..f1b29e8229 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_clients/ipa_mhi_client.c @@ -0,0 +1,2439 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include "ipa.h" +#include +#include +#include "gsi.h" +#include "ipa_common_i.h" +#include "ipa_pm.h" +#include "ipa_i.h" +#include "ipahal.h" + +#define IPA_MHI_DRV_NAME "ipa_mhi_client" + +#define IPA_MHI_DBG(fmt, args...) \ + do { \ + pr_debug(IPA_MHI_DRV_NAME " %s:%d " fmt, \ + __func__, __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf(), \ + IPA_MHI_DRV_NAME " %s:%d " fmt, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf_low(), \ + IPA_MHI_DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) + +#define IPA_MHI_DBG_LOW(fmt, args...) \ + do { \ + pr_debug(IPA_MHI_DRV_NAME " %s:%d " fmt, \ + __func__, __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf_low(), \ + IPA_MHI_DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) + + +#define IPA_MHI_ERR(fmt, args...) \ + do { \ + pr_err(IPA_MHI_DRV_NAME " %s:%d " fmt, \ + __func__, __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf(), \ + IPA_MHI_DRV_NAME " %s:%d " fmt, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf_low(), \ + IPA_MHI_DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) + +#define IPA_MHI_FUNC_ENTRY() \ + IPA_MHI_DBG("ENTRY\n") +#define IPA_MHI_FUNC_EXIT() \ + IPA_MHI_DBG("EXIT\n") + +#define IPA_MHI_CH_EMPTY_TIMEOUT_MSEC 10 + +#define IPA_MHI_SUSPEND_SLEEP_MIN 900 +#define IPA_MHI_SUSPEND_SLEEP_MAX 1100 + +#define IPA_MHI_MAX_UL_CHANNELS 2 +#define IPA_MHI_MAX_DL_CHANNELS 4 + +/* bit #40 in address should be asserted for MHI transfers over pcie */ +#define IPA_MHI_CLIENT_HOST_ADDR_COND(addr) \ + ((ipa_mhi_client_ctx->assert_bit40)?(IPA_MHI_HOST_ADDR(addr)):(addr)) + +#define IPA_MHI_CLIENT_IP_HW_0_OUT 100 +#define IPA_MHI_CLIENT_IP_HW_0_IN 101 +#define IPA_MHI_CLIENT_ADPL_IN 102 +#define IPA_MHI_CLIENT_IP_HW_QDSS 103 +#define IPA_MHI_CLIENT_IP_HW_1_OUT 105 +#define IPA_MHI_CLIENT_IP_HW_1_IN 106 +#define IPA_MHI_CLIENT_QMAP_FLOW_CTRL_OUT 109 +#define IPA_MHI_CLIENT_QMAP_FLOW_CTRL_IN 110 + +enum ipa_mhi_rm_state { + IPA_MHI_RM_STATE_RELEASED, + IPA_MHI_RM_STATE_REQUESTED, + IPA_MHI_RM_STATE_GRANTED, + IPA_MHI_RM_STATE_MAX +}; + +static char *ipa_mhi_state_str[] = { + __stringify(IPA_MHI_STATE_INITIALIZED), + __stringify(IPA_MHI_STATE_READY), + __stringify(IPA_MHI_STATE_STARTED), + __stringify(IPA_MHI_STATE_SUSPEND_IN_PROGRESS), + __stringify(IPA_MHI_STATE_SUSPENDED), + __stringify(IPA_MHI_STATE_RESUME_IN_PROGRESS), +}; + +#define MHI_STATE_STR(state) \ + (((state) >= 0 && (state) < IPA_MHI_STATE_MAX) ? \ + ipa_mhi_state_str[(state)] : \ + "INVALID") + +enum ipa_mhi_dma_dir { + IPA_MHI_DMA_TO_HOST, + IPA_MHI_DMA_FROM_HOST, +}; + +/** + * struct ipa_mhi_channel_ctx - MHI Channel context + * @valid: entry is valid + * @id: MHI channel ID + * @hdl: channel handle for uC + * @client: IPA Client + * @state: Channel state + */ +struct ipa_mhi_channel_ctx { + bool valid; + u8 id; + u8 index; + enum ipa_client_type client; + enum ipa_hw_mhi_channel_states state; + bool stop_in_proc; + struct gsi_chan_info ch_info; + u64 channel_context_addr; + struct ipa_mhi_ch_ctx ch_ctx_host; + u64 event_context_addr; + struct ipa_mhi_ev_ctx ev_ctx_host; + bool brstmode_enabled; + union __packed gsi_channel_scratch ch_scratch; + unsigned long cached_gsi_evt_ring_hdl; +}; + +struct ipa_mhi_client_ctx { + enum ipa_mhi_state state; + spinlock_t state_lock; + mhi_client_cb cb_notify; + void *cb_priv; + bool trigger_wakeup; + bool wakeup_notified; + struct workqueue_struct *wq; + struct ipa_mhi_channel_ctx ul_channels[IPA_MHI_MAX_UL_CHANNELS]; + struct ipa_mhi_channel_ctx dl_channels[IPA_MHI_MAX_DL_CHANNELS]; + u32 total_channels; + struct ipa_mhi_msi_info msi; + u32 mmio_addr; + u32 first_ch_idx; + u32 first_er_idx; + u32 host_ctrl_addr; + u32 host_data_addr; + u64 channel_context_array_addr; + u64 event_context_array_addr; + u32 qmi_req_id; + u32 use_ipadma; + bool assert_bit40; + bool test_mode; + u32 pm_hdl; + u32 modem_pm_hdl; + enum ipa_mhi_mstate mhi_mstate; +}; + +static struct ipa_mhi_client_ctx *ipa_mhi_client_ctx; +static DEFINE_MUTEX(mhi_client_general_mutex); + +static char *ipa_mhi_channel_state_str[] = { + __stringify(IPA_HW_MHI_CHANNEL_STATE_DISABLE), + __stringify(IPA_HW_MHI_CHANNEL_STATE_ENABLE), + __stringify(IPA_HW_MHI_CHANNEL_STATE_RUN), + __stringify(IPA_HW_MHI_CHANNEL_STATE_SUSPEND), + __stringify(IPA_HW_MHI_CHANNEL_STATE_STOP), + __stringify(IPA_HW_MHI_CHANNEL_STATE_ERROR), +}; + +#define MHI_CH_STATE_STR(state) \ + (((state) >= 0 && (state) <= IPA_HW_MHI_CHANNEL_STATE_ERROR) ? \ + ipa_mhi_channel_state_str[(state)] : \ + "INVALID") + +static int ipa_mhi_set_lock_unlock(bool is_lock) +{ + IPA_MHI_DBG("entry\n"); + if (is_lock) + mutex_lock(&mhi_client_general_mutex); + else + mutex_unlock(&mhi_client_general_mutex); + IPA_MHI_DBG("exit\n"); + + return 0; +} + +static int ipa_mhi_read_write_host(enum ipa_mhi_dma_dir dir, void *dev_addr, + u64 host_addr, int size) +{ + struct ipa_mem_buffer mem; + int res; + struct device *pdev; + + IPA_MHI_FUNC_ENTRY(); + + if (ipa_mhi_client_ctx->use_ipadma) { + pdev = ipa3_get_dma_dev(); + host_addr = IPA_MHI_CLIENT_HOST_ADDR_COND(host_addr); + + mem.size = size; + if (pdev) + mem.base = dma_alloc_coherent(pdev, mem.size, + &mem.phys_base, GFP_KERNEL); + else { + IPA_MHI_ERR("platform dev is not valid"); + return -EFAULT; + } + if (!mem.base) { + IPA_MHI_ERR( + "dma_alloc_coherent failed, DMA buff size %d\n" + , mem.size); + return -ENOMEM; + } + + res = ipa_dma_enable(); + if (res) { + IPA_MHI_ERR("failed to enable IPA DMA rc=%d\n", res); + goto fail_dma_enable; + } + + if (dir == IPA_MHI_DMA_FROM_HOST) { + res = ipa_dma_sync_memcpy(mem.phys_base, host_addr, + size); + if (res) { + IPA_MHI_ERR( + "ipa_dma_sync_memcpy from host fail%d\n" + , res); + goto fail_memcopy; + } + memcpy(dev_addr, mem.base, size); + } else { + memcpy(mem.base, dev_addr, size); + res = ipa_dma_sync_memcpy(host_addr, mem.phys_base, + size); + if (res) { + IPA_MHI_ERR( + "ipa_dma_sync_memcpy to host fail %d\n" + , res); + goto fail_memcopy; + } + } + goto dma_succeed; + } else { + void *host_ptr; + + if (!ipa_mhi_client_ctx->test_mode) + host_ptr = ioremap(host_addr, size); + else + host_ptr = phys_to_virt(host_addr); + if (!host_ptr) { + IPA_MHI_ERR("ioremap failed for 0x%llx\n", host_addr); + return -EFAULT; + } + if (dir == IPA_MHI_DMA_FROM_HOST) + memcpy(dev_addr, host_ptr, size); + else + memcpy(host_ptr, dev_addr, size); + if (!ipa_mhi_client_ctx->test_mode) + iounmap(host_ptr); + } + + IPA_MHI_FUNC_EXIT(); + return 0; + +dma_succeed: + IPA_MHI_FUNC_EXIT(); + res = 0; +fail_memcopy: + if (ipa_dma_disable()) + IPA_MHI_ERR("failed to disable IPA DMA\n"); +fail_dma_enable: + dma_free_coherent(pdev, mem.size, mem.base, mem.phys_base); + return res; +} + +#ifdef CONFIG_DEBUG_FS +#define IPA_MHI_MAX_MSG_LEN 512 +static char dbg_buff[IPA_MHI_MAX_MSG_LEN]; +static struct dentry *dent; + +static int ipa_mhi_print_channel_info(struct ipa_mhi_channel_ctx *channel, + char *buff, int len) +{ + int nbytes = 0; + + if (channel->valid) { + nbytes += scnprintf(&buff[nbytes], + len - nbytes, + "channel idx=%d ch_id=%d client=%d state=%s\n", + channel->index, channel->id, channel->client, + MHI_CH_STATE_STR(channel->state)); + + nbytes += scnprintf(&buff[nbytes], + len - nbytes, + " ch_ctx=%llx\n", + channel->channel_context_addr); + + nbytes += scnprintf(&buff[nbytes], + len - nbytes, + " gsi_evt_ring_hdl=%ld ev_ctx=%llx\n", + channel->cached_gsi_evt_ring_hdl, + channel->event_context_addr); + } + return nbytes; +} + +static int ipa_mhi_print_host_channel_ctx_info( + struct ipa_mhi_channel_ctx *channel, char *buff, int len) +{ + int res, nbytes = 0; + struct ipa_mhi_ch_ctx ch_ctx_host; + + memset(&ch_ctx_host, 0, sizeof(ch_ctx_host)); + + /* reading ch context from host */ + res = ipa_mhi_read_write_host(IPA_MHI_DMA_FROM_HOST, + &ch_ctx_host, channel->channel_context_addr, + sizeof(ch_ctx_host)); + if (res) { + nbytes += scnprintf(&buff[nbytes], len - nbytes, + "Failed to read from host %d\n", res); + return nbytes; + } + + nbytes += scnprintf(&buff[nbytes], len - nbytes, + "ch_id: %d\n", channel->id); + nbytes += scnprintf(&buff[nbytes], len - nbytes, + "chstate: 0x%x\n", ch_ctx_host.chstate); + nbytes += scnprintf(&buff[nbytes], len - nbytes, + "brstmode: 0x%x\n", ch_ctx_host.brstmode); + nbytes += scnprintf(&buff[nbytes], len - nbytes, + "chtype: 0x%x\n", ch_ctx_host.chtype); + nbytes += scnprintf(&buff[nbytes], len - nbytes, + "erindex: 0x%x\n", ch_ctx_host.erindex); + nbytes += scnprintf(&buff[nbytes], len - nbytes, + "rbase: 0x%llx\n", ch_ctx_host.rbase); + nbytes += scnprintf(&buff[nbytes], len - nbytes, + "rlen: 0x%llx\n", ch_ctx_host.rlen); + nbytes += scnprintf(&buff[nbytes], len - nbytes, + "rp: 0x%llx\n", ch_ctx_host.rp); + nbytes += scnprintf(&buff[nbytes], len - nbytes, + "wp: 0x%llx\n", ch_ctx_host.wp); + + return nbytes; +} + +static ssize_t ipa_mhi_debugfs_stats(struct file *file, + char __user *ubuf, + size_t count, + loff_t *ppos) +{ + int nbytes = 0; + int i; + struct ipa_mhi_channel_ctx *channel; + + nbytes += scnprintf(&dbg_buff[nbytes], + IPA_MHI_MAX_MSG_LEN - nbytes, + "IPA MHI state: %s\n", + MHI_STATE_STR(ipa_mhi_client_ctx->state)); + + for (i = 0; i < IPA_MHI_MAX_UL_CHANNELS; i++) { + channel = &ipa_mhi_client_ctx->ul_channels[i]; + nbytes += ipa_mhi_print_channel_info(channel, + &dbg_buff[nbytes], IPA_MHI_MAX_MSG_LEN - nbytes); + } + + for (i = 0; i < IPA_MHI_MAX_DL_CHANNELS; i++) { + channel = &ipa_mhi_client_ctx->dl_channels[i]; + nbytes += ipa_mhi_print_channel_info(channel, + &dbg_buff[nbytes], IPA_MHI_MAX_MSG_LEN - nbytes); + } + + return simple_read_from_buffer(ubuf, count, ppos, dbg_buff, nbytes); +} + +static ssize_t ipa_mhi_debugfs_dump_host_ch_ctx_arr(struct file *file, + char __user *ubuf, + size_t count, + loff_t *ppos) +{ + int i, nbytes = 0; + struct ipa_mhi_channel_ctx *channel; + + if (ipa_mhi_client_ctx->state == IPA_MHI_STATE_INITIALIZED || + ipa_mhi_client_ctx->state == IPA_MHI_STATE_READY) { + nbytes += scnprintf(&dbg_buff[nbytes], + IPA_MHI_MAX_MSG_LEN - nbytes, + "Cannot dump host channel context "); + nbytes += scnprintf(&dbg_buff[nbytes], + IPA_MHI_MAX_MSG_LEN - nbytes, + "before IPA MHI was STARTED\n"); + return simple_read_from_buffer(ubuf, count, ppos, + dbg_buff, nbytes); + } + if (ipa_mhi_client_ctx->state == IPA_MHI_STATE_SUSPENDED) { + nbytes += scnprintf(&dbg_buff[nbytes], + IPA_MHI_MAX_MSG_LEN - nbytes, + "IPA MHI is suspended, cannot dump channel ctx array"); + nbytes += scnprintf(&dbg_buff[nbytes], + IPA_MHI_MAX_MSG_LEN - nbytes, + " from host -PCIe can be in D3 state\n"); + return simple_read_from_buffer(ubuf, count, ppos, + dbg_buff, nbytes); + } + + nbytes += scnprintf(&dbg_buff[nbytes], + IPA_MHI_MAX_MSG_LEN - nbytes, + "channel contex array - dump from host\n"); + nbytes += scnprintf(&dbg_buff[nbytes], + IPA_MHI_MAX_MSG_LEN - nbytes, + "***** UL channels *******\n"); + + for (i = 0; i < IPA_MHI_MAX_UL_CHANNELS; i++) { + channel = &ipa_mhi_client_ctx->ul_channels[i]; + if (!channel->valid) + continue; + nbytes += ipa_mhi_print_host_channel_ctx_info(channel, + &dbg_buff[nbytes], + IPA_MHI_MAX_MSG_LEN - nbytes); + } + + nbytes += scnprintf(&dbg_buff[nbytes], + IPA_MHI_MAX_MSG_LEN - nbytes, + "\n***** DL channels *******\n"); + + for (i = 0; i < IPA_MHI_MAX_DL_CHANNELS; i++) { + channel = &ipa_mhi_client_ctx->dl_channels[i]; + if (!channel->valid) + continue; + nbytes += ipa_mhi_print_host_channel_ctx_info(channel, + &dbg_buff[nbytes], IPA_MHI_MAX_MSG_LEN - nbytes); + } + + return simple_read_from_buffer(ubuf, count, ppos, dbg_buff, nbytes); +} + +const struct file_operations ipa_mhi_stats_ops = { + .read = ipa_mhi_debugfs_stats, +}; + +const struct file_operations ipa_mhi_dump_host_ch_ctx_ops = { + .read = ipa_mhi_debugfs_dump_host_ch_ctx_arr, +}; + + +static void ipa_mhi_debugfs_init(void) +{ + const mode_t read_only_mode = 0444; + const mode_t read_write_mode = 0664; + struct dentry *file; + + IPA_MHI_FUNC_ENTRY(); + + dent = debugfs_create_dir("ipa_mhi", 0); + if (IS_ERR(dent)) { + IPA_MHI_ERR("fail to create folder ipa_mhi\n"); + return; + } + + file = debugfs_create_file("stats", read_only_mode, dent, + 0, &ipa_mhi_stats_ops); + if (!file || IS_ERR(file)) { + IPA_MHI_ERR("fail to create file stats\n"); + goto fail; + } + + debugfs_create_u32("use_ipadma", read_write_mode, dent, + &ipa_mhi_client_ctx->use_ipadma); + + file = debugfs_create_file("dump_host_channel_ctx_array", + read_only_mode, dent, 0, &ipa_mhi_dump_host_ch_ctx_ops); + if (!file || IS_ERR(file)) { + IPA_MHI_ERR("fail to create file dump_host_channel_ctx_arr\n"); + goto fail; + } + + IPA_MHI_FUNC_EXIT(); + return; +fail: + debugfs_remove_recursive(dent); +} + +#else +static void ipa_mhi_debugfs_init(void) {} +static void ipa_mhi_debugfs_destroy(void) {} +#endif /* CONFIG_DEBUG_FS */ + +static union IpaHwMhiDlUlSyncCmdData_t ipa_cached_dl_ul_sync_info; + +static void ipa_mhi_wq_notify_wakeup(struct work_struct *work); +static DECLARE_WORK(ipa_mhi_notify_wakeup_work, ipa_mhi_wq_notify_wakeup); + +static void ipa_mhi_wq_notify_ready(struct work_struct *work); +static DECLARE_WORK(ipa_mhi_notify_ready_work, ipa_mhi_wq_notify_ready); + +/** + * ipa_mhi_notify_wakeup() - Schedule work to notify data available + * + * This function will schedule a work to notify data available event. + * In case this function is called more than once, only one notification will + * be sent to MHI client driver. No further notifications will be sent until + * IPA MHI state will become STARTED. + */ +static void ipa_mhi_notify_wakeup(void) +{ + IPA_MHI_FUNC_ENTRY(); + if (ipa_mhi_client_ctx->wakeup_notified) { + IPA_MHI_DBG("wakeup already called\n"); + return; + } + queue_work(ipa_mhi_client_ctx->wq, &ipa_mhi_notify_wakeup_work); + ipa_mhi_client_ctx->wakeup_notified = true; + IPA_MHI_FUNC_EXIT(); +} + +/** + * ipa_mhi_wq_notify_wakeup() - Notify MHI client on data available + * + * This function is called from IPA MHI workqueue to notify + * MHI client driver on data available event. + */ +static void ipa_mhi_wq_notify_wakeup(struct work_struct *work) +{ + IPA_MHI_FUNC_ENTRY(); + ipa_mhi_client_ctx->cb_notify(ipa_mhi_client_ctx->cb_priv, + IPA_MHI_EVENT_DATA_AVAILABLE, 0); + IPA_MHI_FUNC_EXIT(); +} + +/** + * ipa_mhi_wq_notify_ready() - Notify MHI client on ready + * + * This function is called from IPA MHI workqueue to notify + * MHI client driver on ready event when IPA uC is loaded + */ +static void ipa_mhi_wq_notify_ready(struct work_struct *work) +{ + IPA_MHI_FUNC_ENTRY(); + ipa_mhi_client_ctx->cb_notify(ipa_mhi_client_ctx->cb_priv, + IPA_MHI_EVENT_READY, 0); + IPA_MHI_FUNC_EXIT(); +} + +/** + * ipa_mhi_notify_ready() - Schedule work to notify ready + * + * This function will schedule a work to notify ready event. + */ +static void ipa_mhi_notify_ready(void) +{ + IPA_MHI_FUNC_ENTRY(); + queue_work(ipa_mhi_client_ctx->wq, &ipa_mhi_notify_ready_work); + IPA_MHI_FUNC_EXIT(); +} + +/** + * ipa_mhi_set_state() - Set new state to IPA MHI + * @state: new state + * + * Sets a new state to IPA MHI if possible according to IPA MHI state machine. + * In some state transitions a wakeup request will be triggered. + * + * Returns: 0 on success, -1 otherwise + */ +static int ipa_mhi_set_state(enum ipa_mhi_state new_state) +{ + unsigned long flags; + int res = -EPERM; + + spin_lock_irqsave(&ipa_mhi_client_ctx->state_lock, flags); + IPA_MHI_DBG("Current state: %s\n", + MHI_STATE_STR(ipa_mhi_client_ctx->state)); + + switch (ipa_mhi_client_ctx->state) { + case IPA_MHI_STATE_INITIALIZED: + if (new_state == IPA_MHI_STATE_READY) { + ipa_mhi_notify_ready(); + res = 0; + } + break; + + case IPA_MHI_STATE_READY: + if (new_state == IPA_MHI_STATE_READY) + res = 0; + if (new_state == IPA_MHI_STATE_STARTED) + res = 0; + break; + + case IPA_MHI_STATE_STARTED: + if (new_state == IPA_MHI_STATE_INITIALIZED) + res = 0; + else if (new_state == IPA_MHI_STATE_SUSPEND_IN_PROGRESS) + res = 0; + break; + + case IPA_MHI_STATE_SUSPEND_IN_PROGRESS: + if (new_state == IPA_MHI_STATE_SUSPENDED) { + if (ipa_mhi_client_ctx->trigger_wakeup) { + ipa_mhi_client_ctx->trigger_wakeup = false; + ipa_mhi_notify_wakeup(); + } + res = 0; + } else if (new_state == IPA_MHI_STATE_STARTED) { + ipa_mhi_client_ctx->wakeup_notified = false; + ipa_mhi_client_ctx->trigger_wakeup = false; + res = 0; + } + break; + + case IPA_MHI_STATE_SUSPENDED: + if (new_state == IPA_MHI_STATE_RESUME_IN_PROGRESS) + res = 0; + break; + + case IPA_MHI_STATE_RESUME_IN_PROGRESS: + if (new_state == IPA_MHI_STATE_SUSPENDED) { + if (ipa_mhi_client_ctx->trigger_wakeup) { + ipa_mhi_client_ctx->trigger_wakeup = false; + ipa_mhi_notify_wakeup(); + } + res = 0; + } else if (new_state == IPA_MHI_STATE_STARTED) { + ipa_mhi_client_ctx->trigger_wakeup = false; + ipa_mhi_client_ctx->wakeup_notified = false; + res = 0; + } + break; + + default: + IPA_MHI_ERR("Invalid state %d\n", ipa_mhi_client_ctx->state); + WARN_ON(1); + } + + if (res) + IPA_MHI_ERR("Invalid state change to %s\n", + MHI_STATE_STR(new_state)); + else { + IPA_MHI_DBG("New state change to %s\n", + MHI_STATE_STR(new_state)); + ipa_mhi_client_ctx->state = new_state; + } + spin_unlock_irqrestore(&ipa_mhi_client_ctx->state_lock, flags); + return res; +} + +/** + * ipa_mhi_start() - Start IPA MHI engine + * @params: pcie addresses for MHI + * + * This function is called by MHI client driver on MHI engine start for + * handling MHI accelerated channels. This function is called after + * ipa_mhi_init() was called and can be called after MHI reset to restart MHI + * engine. When this function returns device can move to M0 state. + * + * Return codes: 0 : success + * negative : error + */ +int ipa_mhi_start(struct ipa_mhi_start_params *params) +{ + int res; + struct ipa_mhi_init_engine init_params; + + IPA_MHI_FUNC_ENTRY(); + + if (!params) { + IPA_MHI_ERR("null args\n"); + return -EINVAL; + } + + if (!ipa_mhi_client_ctx) { + IPA_MHI_ERR("not initialized\n"); + return -EPERM; + } + + res = ipa_mhi_set_state(IPA_MHI_STATE_STARTED); + if (res) { + IPA_MHI_ERR("ipa_mhi_set_state %d\n", res); + return res; + } + + ipa_mhi_client_ctx->host_ctrl_addr = params->host_ctrl_addr; + ipa_mhi_client_ctx->host_data_addr = params->host_data_addr; + ipa_mhi_client_ctx->channel_context_array_addr = + params->channel_context_array_addr; + ipa_mhi_client_ctx->event_context_array_addr = + params->event_context_array_addr; + IPA_MHI_DBG("host_ctrl_addr 0x%x\n", + ipa_mhi_client_ctx->host_ctrl_addr); + IPA_MHI_DBG("host_data_addr 0x%x\n", + ipa_mhi_client_ctx->host_data_addr); + IPA_MHI_DBG("channel_context_array_addr 0x%llx\n", + ipa_mhi_client_ctx->channel_context_array_addr); + IPA_MHI_DBG("event_context_array_addr 0x%llx\n", + ipa_mhi_client_ctx->event_context_array_addr); + + res = ipa_pm_activate_sync(ipa_mhi_client_ctx->pm_hdl); + if (res) { + IPA_MHI_ERR("failed activate client %d\n", res); + goto fail_pm_activate; + } + res = ipa_pm_activate_sync(ipa_mhi_client_ctx->modem_pm_hdl); + if (res) { + IPA_MHI_ERR("failed activate modem client %d\n", res); + goto fail_pm_activate_modem; + } + + /* gsi params */ + init_params.gsi.first_ch_idx = + ipa_mhi_client_ctx->first_ch_idx; + /* uC params */ + init_params.uC.first_ch_idx = + ipa_mhi_client_ctx->first_ch_idx; + init_params.uC.first_er_idx = + ipa_mhi_client_ctx->first_er_idx; + init_params.uC.host_ctrl_addr = params->host_ctrl_addr; + init_params.uC.host_data_addr = params->host_data_addr; + init_params.uC.mmio_addr = ipa_mhi_client_ctx->mmio_addr; + init_params.uC.msi = &ipa_mhi_client_ctx->msi; + init_params.uC.ipa_cached_dl_ul_sync_info = + &ipa_cached_dl_ul_sync_info; + + res = ipa3_mhi_init_engine(&init_params); + if (res) { + IPA_MHI_ERR("IPA core failed to start MHI %d\n", res); + goto fail_init_engine; + } + + IPA_MHI_FUNC_EXIT(); + return 0; + +fail_init_engine: + ipa_pm_deactivate_sync(ipa_mhi_client_ctx->modem_pm_hdl); +fail_pm_activate_modem: + ipa_pm_deactivate_sync(ipa_mhi_client_ctx->pm_hdl); +fail_pm_activate: + ipa_mhi_set_state(IPA_MHI_STATE_INITIALIZED); + return res; +} +EXPORT_SYMBOL(ipa_mhi_start); + +/** + * ipa_mhi_get_channel_context() - Get corresponding channel context + * @ep: IPA ep + * @channel_id: Channel ID + * + * This function will return the corresponding channel context or allocate new + * one in case channel context for channel does not exist. + */ +static struct ipa_mhi_channel_ctx *ipa_mhi_get_channel_context( + enum ipa_client_type client, u8 channel_id) +{ + int ch_idx; + struct ipa_mhi_channel_ctx *channels; + int max_channels; + + if (IPA_CLIENT_IS_PROD(client)) { + channels = ipa_mhi_client_ctx->ul_channels; + max_channels = IPA_MHI_MAX_UL_CHANNELS; + } else { + channels = ipa_mhi_client_ctx->dl_channels; + max_channels = IPA_MHI_MAX_DL_CHANNELS; + } + + /* find the channel context according to channel id */ + for (ch_idx = 0; ch_idx < max_channels; ch_idx++) { + if (channels[ch_idx].valid && + channels[ch_idx].id == channel_id) + return &channels[ch_idx]; + } + + /* channel context does not exists, allocate a new one */ + for (ch_idx = 0; ch_idx < max_channels; ch_idx++) { + if (!channels[ch_idx].valid) + break; + } + + if (ch_idx == max_channels) { + IPA_MHI_ERR("no more channels available\n"); + return NULL; + } + + channels[ch_idx].valid = true; + channels[ch_idx].id = channel_id; + channels[ch_idx].index = ipa_mhi_client_ctx->total_channels++; + channels[ch_idx].client = client; + channels[ch_idx].state = IPA_HW_MHI_CHANNEL_STATE_INVALID; + + return &channels[ch_idx]; +} + +/** + * ipa_mhi_get_channel_context_by_clnt_hdl() - Get corresponding channel + * context + * @clnt_hdl: client handle as provided in ipa_mhi_connect_pipe() + * + * This function will return the corresponding channel context or NULL in case + * that channel does not exist. + */ +static struct ipa_mhi_channel_ctx *ipa_mhi_get_channel_context_by_clnt_hdl( + u32 clnt_hdl) +{ + int ch_idx; + + for (ch_idx = 0; ch_idx < IPA_MHI_MAX_UL_CHANNELS; ch_idx++) { + if (ipa_mhi_client_ctx->ul_channels[ch_idx].valid && + ipa_get_ep_mapping( + ipa_mhi_client_ctx->ul_channels[ch_idx].client) + == clnt_hdl) + return &ipa_mhi_client_ctx->ul_channels[ch_idx]; + } + + for (ch_idx = 0; ch_idx < IPA_MHI_MAX_DL_CHANNELS; ch_idx++) { + if (ipa_mhi_client_ctx->dl_channels[ch_idx].valid && + ipa_get_ep_mapping( + ipa_mhi_client_ctx->dl_channels[ch_idx].client) + == clnt_hdl) + return &ipa_mhi_client_ctx->dl_channels[ch_idx]; + } + + return NULL; +} + +static void ipa_mhi_dump_ch_ctx(struct ipa_mhi_channel_ctx *channel) +{ + IPA_MHI_DBG("ch_id %d\n", channel->id); + IPA_MHI_DBG("chstate 0x%x\n", channel->ch_ctx_host.chstate); + IPA_MHI_DBG("brstmode 0x%x\n", channel->ch_ctx_host.brstmode); + IPA_MHI_DBG("pollcfg 0x%x\n", channel->ch_ctx_host.pollcfg); + IPA_MHI_DBG("chtype 0x%x\n", channel->ch_ctx_host.chtype); + IPA_MHI_DBG("erindex 0x%x\n", channel->ch_ctx_host.erindex); + IPA_MHI_DBG("rbase 0x%llx\n", channel->ch_ctx_host.rbase); + IPA_MHI_DBG("rlen 0x%llx\n", channel->ch_ctx_host.rlen); + IPA_MHI_DBG("rp 0x%llx\n", channel->ch_ctx_host.rp); + IPA_MHI_DBG("wp 0x%llx\n", channel->ch_ctx_host.wp); +} + +static void ipa_mhi_dump_ev_ctx(struct ipa_mhi_channel_ctx *channel) +{ + IPA_MHI_DBG("ch_id %d event id %d\n", channel->id, + channel->ch_ctx_host.erindex); + + IPA_MHI_DBG("intmodc 0x%x\n", channel->ev_ctx_host.intmodc); + IPA_MHI_DBG("intmodt 0x%x\n", channel->ev_ctx_host.intmodt); + IPA_MHI_DBG("ertype 0x%x\n", channel->ev_ctx_host.ertype); + IPA_MHI_DBG("msivec 0x%x\n", channel->ev_ctx_host.msivec); + IPA_MHI_DBG("rbase 0x%llx\n", channel->ev_ctx_host.rbase); + IPA_MHI_DBG("rlen 0x%llx\n", channel->ev_ctx_host.rlen); + IPA_MHI_DBG("rp 0x%llx\n", channel->ev_ctx_host.rp); + IPA_MHI_DBG("wp 0x%llx\n", channel->ev_ctx_host.wp); +} + +static int ipa_mhi_read_ch_ctx(struct ipa_mhi_channel_ctx *channel) +{ + int res; + + res = ipa_mhi_read_write_host(IPA_MHI_DMA_FROM_HOST, + &channel->ch_ctx_host, channel->channel_context_addr, + sizeof(channel->ch_ctx_host)); + if (res) { + IPA_MHI_ERR("ipa_mhi_read_write_host failed %d\n", res); + return res; + + } + ipa_mhi_dump_ch_ctx(channel); + + channel->event_context_addr = + ipa_mhi_client_ctx->event_context_array_addr + + channel->ch_ctx_host.erindex * sizeof(struct ipa_mhi_ev_ctx); + IPA_MHI_DBG("ch %d event_context_addr 0x%llx\n", channel->id, + channel->event_context_addr); + + res = ipa_mhi_read_write_host(IPA_MHI_DMA_FROM_HOST, + &channel->ev_ctx_host, channel->event_context_addr, + sizeof(channel->ev_ctx_host)); + if (res) { + IPA_MHI_ERR("ipa_mhi_read_write_host failed %d\n", res); + return res; + + } + ipa_mhi_dump_ev_ctx(channel); + + return 0; +} + +static void ipa_mhi_gsi_ev_err_cb(struct gsi_evt_err_notify *notify) +{ + struct ipa_mhi_channel_ctx *channel = notify->user_data; + + IPA_MHI_ERR("channel id=%d client=%d state=%d\n", + channel->id, channel->client, channel->state); + switch (notify->evt_id) { + case GSI_EVT_OUT_OF_BUFFERS_ERR: + IPA_MHI_ERR("Received GSI_EVT_OUT_OF_BUFFERS_ERR\n"); + break; + case GSI_EVT_OUT_OF_RESOURCES_ERR: + IPA_MHI_ERR("Received GSI_EVT_OUT_OF_RESOURCES_ERR\n"); + break; + case GSI_EVT_UNSUPPORTED_INTER_EE_OP_ERR: + IPA_MHI_ERR("Received GSI_EVT_UNSUPPORTED_INTER_EE_OP_ERR\n"); + break; + case GSI_EVT_EVT_RING_EMPTY_ERR: + IPA_MHI_ERR("Received GSI_EVT_EVT_RING_EMPTY_ERR\n"); + break; + default: + IPA_MHI_ERR("Unexpected err evt: %d\n", notify->evt_id); + } + IPA_MHI_ERR("err_desc=0x%x\n", notify->err_desc); + ipa_assert(); +} + +static void ipa_mhi_gsi_ch_err_cb(struct gsi_chan_err_notify *notify) +{ + struct ipa_mhi_channel_ctx *channel = notify->chan_user_data; + + IPA_MHI_ERR("channel id=%d client=%d state=%d\n", + channel->id, channel->client, channel->state); + switch (notify->evt_id) { + case GSI_CHAN_INVALID_TRE_ERR: + IPA_MHI_ERR("Received GSI_CHAN_INVALID_TRE_ERR\n"); + break; + case GSI_CHAN_NON_ALLOCATED_EVT_ACCESS_ERR: + IPA_MHI_ERR("Received GSI_CHAN_NON_ALLOCATED_EVT_ACCESS_ERR\n"); + break; + case GSI_CHAN_OUT_OF_BUFFERS_ERR: + IPA_MHI_ERR("Received GSI_CHAN_OUT_OF_BUFFERS_ERR\n"); + break; + case GSI_CHAN_OUT_OF_RESOURCES_ERR: + IPA_MHI_ERR("Received GSI_CHAN_OUT_OF_RESOURCES_ERR\n"); + break; + case GSI_CHAN_UNSUPPORTED_INTER_EE_OP_ERR: + IPA_MHI_ERR("Received GSI_CHAN_UNSUPPORTED_INTER_EE_OP_ERR\n"); + break; + case GSI_CHAN_HWO_1_ERR: + IPA_MHI_ERR("Received GSI_CHAN_HWO_1_ERR\n"); + break; + default: + IPA_MHI_ERR("Unexpected err evt: %d\n", notify->evt_id); + } + IPA_MHI_ERR("err_desc=0x%x\n", notify->err_desc); + ipa_assert(); +} + + +static bool ipa_mhi_gsi_channel_empty(struct ipa_mhi_channel_ctx *channel) +{ + IPA_MHI_FUNC_ENTRY(); + + if (!channel->stop_in_proc) { + IPA_MHI_DBG("Channel is not in STOP_IN_PROC\n"); + return true; + } + + if (ipa3_mhi_stop_gsi_channel(channel->client)) { + channel->stop_in_proc = false; + return true; + } + + return false; +} + +/** + * ipa_mhi_wait_for_ul_empty_timeout() - wait for pending packets in uplink + * @msecs: timeout to wait + * + * This function will poll until there are no packets pending in uplink channels + * or timeout occurred. + * + * Return code: true - no pending packets in uplink channels + * false - timeout occurred + */ +static bool ipa_mhi_wait_for_ul_empty_timeout(unsigned int msecs) +{ + unsigned long jiffies_timeout = msecs_to_jiffies(msecs); + unsigned long jiffies_start = jiffies; + bool empty = false; + int i; + + IPA_MHI_FUNC_ENTRY(); + while (!empty) { + empty = true; + for (i = 0; i < IPA_MHI_MAX_UL_CHANNELS; i++) { + if (!ipa_mhi_client_ctx->ul_channels[i].valid) + continue; + empty &= ipa_mhi_gsi_channel_empty( + &ipa_mhi_client_ctx->ul_channels[i]); + } + + if (time_after(jiffies, jiffies_start + jiffies_timeout)) { + IPA_MHI_DBG("finished waiting for UL empty\n"); + break; + } + + if (IPA_MHI_MAX_UL_CHANNELS == 1) + usleep_range(IPA_GSI_CHANNEL_STOP_SLEEP_MIN_USEC, + IPA_GSI_CHANNEL_STOP_SLEEP_MAX_USEC); + } + + IPA_MHI_DBG("IPA UL is %s\n", (empty) ? "empty" : "not empty"); + + IPA_MHI_FUNC_EXIT(); + return empty; +} + +static int ipa_mhi_enable_force_clear(u32 request_id, bool throttle_source) +{ + struct ipa_enable_force_clear_datapath_req_msg_v01 req; + int i; + int res; + u32 source_pipe_bitmask = 0; + u32 source_pipe_reg_idx = 0; + enum ipa_client_type client; + + IPA_MHI_FUNC_ENTRY(); + memset(&req, 0, sizeof(req)); + req.request_id = request_id; + for (i = 0; i < IPA_MHI_MAX_UL_CHANNELS; i++) { + if (!ipa_mhi_client_ctx->ul_channels[i].valid) + continue; + client = ipa_mhi_client_ctx->ul_channels[i].client; + source_pipe_bitmask = ipahal_get_ep_bit(client); + source_pipe_reg_idx = ipahal_get_ep_reg_idx(client); + if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0) { + WARN_ON(source_pipe_reg_idx); + req.source_pipe_bitmask |= source_pipe_bitmask; + } else { + req.source_pipe_bitmask_ext_valid = 1; + req.source_pipe_bitmask_ext[source_pipe_reg_idx] |= + source_pipe_bitmask; + } + } + if (throttle_source) { + req.throttle_source_valid = 1; + req.throttle_source = 1; + } + IPA_MHI_DBG("req_id=0x%x src_pipe_btmk=0x%x,0x%x,0x%x,0x%x throt_src=%d\n", + req.request_id, + req.source_pipe_bitmask_ext[0], + req.source_pipe_bitmask_ext[1], + req.source_pipe_bitmask_ext[2], + req.source_pipe_bitmask_ext[3], + req.throttle_source); + res = ipa3_qmi_enable_force_clear_datapath_send(&req); + if (res) { + IPA_MHI_ERR( + "ipa_qmi_enable_force_clear_datapath_send failed %d\n" + , res); + return res; + } + + IPA_MHI_FUNC_EXIT(); + return 0; +} + +static int ipa_mhi_disable_force_clear(u32 request_id) +{ + struct ipa_disable_force_clear_datapath_req_msg_v01 req; + int res; + + IPA_MHI_FUNC_ENTRY(); + memset(&req, 0, sizeof(req)); + req.request_id = request_id; + IPA_MHI_DBG("req_id=0x%x\n", req.request_id); + res = ipa3_qmi_disable_force_clear_datapath_send(&req); + if (res) { + IPA_MHI_ERR( + "ipa3_qmi_disable_force_clear_datapath_send failed %d\n" + , res); + return res; + } + + IPA_MHI_FUNC_EXIT(); + return 0; +} + +static int ipa_mhi_suspend_gsi_channel(struct ipa_mhi_channel_ctx *channel) +{ + int clnt_hdl; + int res; + + IPA_MHI_FUNC_ENTRY(); + clnt_hdl = ipa_get_ep_mapping(channel->client); + if (clnt_hdl < 0) + return -EFAULT; + + res = ipa_stop_gsi_channel(clnt_hdl); + if (res != 0 && res != -GSI_STATUS_AGAIN && + res != -GSI_STATUS_TIMED_OUT) { + IPA_MHI_ERR("GSI stop channel failed %d\n", res); + return -EFAULT; + } + + /* check if channel was stopped completely */ + if (res) + channel->stop_in_proc = true; + + IPA_MHI_DBG("GSI channel is %s\n", (channel->stop_in_proc) ? + "STOP_IN_PROC" : "STOP"); + + IPA_MHI_FUNC_EXIT(); + return 0; +} + +static int ipa_mhi_reset_ul_channel(struct ipa_mhi_channel_ctx *channel) +{ + int res; + bool empty; + + IPA_MHI_FUNC_ENTRY(); + + res = ipa_mhi_suspend_gsi_channel(channel); + if (res) { + IPA_MHI_ERR("ipa_mhi_suspend_gsi_channel failed %d\n", + res); + return res; + } + + empty = ipa_mhi_wait_for_ul_empty_timeout( + IPA_MHI_CH_EMPTY_TIMEOUT_MSEC); + if (!empty) { + IPA_MHI_DBG("not empty\n"); + res = ipa_mhi_enable_force_clear( + ipa_mhi_client_ctx->qmi_req_id, false); + if (res) { + IPA_MHI_ERR("ipa_mhi_enable_force_clear failed %d\n", + res); + ipa_assert(); + return res; + } + + empty = ipa_mhi_wait_for_ul_empty_timeout( + IPA_MHI_CH_EMPTY_TIMEOUT_MSEC); + IPA_MHI_DBG("empty=%d\n", empty); + + res = + ipa_mhi_disable_force_clear(ipa_mhi_client_ctx->qmi_req_id); + if (res) { + IPA_MHI_ERR("ipa_mhi_disable_force_clear failed %d\n", + res); + ipa_assert(); + return res; + } + ipa_mhi_client_ctx->qmi_req_id++; + } + + res = ipa3_mhi_reset_channel_internal(channel->client); + if (res) { + IPA_MHI_ERR("ipa_mhi_reset_ul_channel_internal failed %d\n" + , res); + return res; + } + + IPA_MHI_FUNC_EXIT(); + + return 0; +} + +static int ipa_mhi_reset_dl_channel(struct ipa_mhi_channel_ctx *channel) +{ + int res; + + IPA_MHI_FUNC_ENTRY(); + res = ipa_mhi_suspend_gsi_channel(channel); + if (res) { + IPA_MHI_ERR("ipa_mhi_suspend_gsi_channel failed %d\n" + , res); + return res; + } + + res = ipa3_mhi_reset_channel_internal(channel->client); + if (res) { + IPA_MHI_ERR( + "ipa_mhi_reset_ul_channel_internal failed %d\n" + , res); + return res; + } + + IPA_MHI_FUNC_EXIT(); + return 0; +} + +static int ipa_mhi_reset_channel(struct ipa_mhi_channel_ctx *channel, + bool update_state) +{ + int res; + + IPA_MHI_FUNC_ENTRY(); + if (IPA_CLIENT_IS_PROD(channel->client)) + res = ipa_mhi_reset_ul_channel(channel); + else + res = ipa_mhi_reset_dl_channel(channel); + if (res) { + IPA_MHI_ERR("failed to reset channel error %d\n", res); + return res; + } + + channel->state = IPA_HW_MHI_CHANNEL_STATE_DISABLE; + + if (update_state) { + res = ipa_mhi_read_write_host(IPA_MHI_DMA_TO_HOST, + &channel->state, channel->channel_context_addr + + offsetof(struct ipa_mhi_ch_ctx, chstate), + sizeof(((struct ipa_mhi_ch_ctx *)0)->chstate)); + if (res) { + IPA_MHI_ERR("ipa_mhi_read_write_host failed %d\n", res); + return res; + } + } + + IPA_MHI_FUNC_EXIT(); + return 0; +} + +static enum ipa_client_type ipa3_mhi_get_client_by_chid(u32 chid) +{ + enum ipa_client_type client; + + switch (chid) { + case IPA_MHI_CLIENT_ADPL_IN: + client = IPA_CLIENT_MHI_DPL_CONS; + break; + case IPA_MHI_CLIENT_IP_HW_QDSS: + client = IPA_CLIENT_MHI_QDSS_CONS; + break; + case IPA_MHI_CLIENT_IP_HW_0_OUT: + client = IPA_CLIENT_MHI_PROD; + break; + case IPA_MHI_CLIENT_IP_HW_0_IN: + client = IPA_CLIENT_MHI_CONS; + break; + case IPA_MHI_CLIENT_IP_HW_1_OUT: + /* >=IPA4.5 non-auto, use mhi ch105 for qmap flow control */ + if (!ipa3_ctx->ipa_config_is_auto && + ipa3_ctx->ipa_hw_type >= IPA_HW_v4_5) + client = IPA_CLIENT_MHI_LOW_LAT_PROD; + else + client = IPA_CLIENT_MHI2_PROD; + break; + case IPA_MHI_CLIENT_IP_HW_1_IN: + /* >=IPA4.5 non-auto, use mhi ch106 for qmap flow control */ + if (!ipa3_ctx->ipa_config_is_auto && + ipa3_ctx->ipa_hw_type >= IPA_HW_v4_5) + client = IPA_CLIENT_MHI_LOW_LAT_CONS; + else + client = IPA_CLIENT_MHI2_CONS; + break; + case IPA_MHI_CLIENT_QMAP_FLOW_CTRL_OUT: + client = IPA_CLIENT_MHI_LOW_LAT_PROD; + break; + case IPA_MHI_CLIENT_QMAP_FLOW_CTRL_IN: + client = IPA_CLIENT_MHI_LOW_LAT_CONS; + break; + default: + IPA_MHI_ERR("Invalid channel = 0x%X\n", chid); + client = IPA_CLIENT_MAX; + } + + return client; +} + +/** + * ipa_mhi_connect_pipe() - Connect pipe to IPA and start corresponding + * MHI channel + * @in: connect parameters + * @clnt_hdl: [out] client handle for this pipe + * + * This function is called by MHI client driver on MHI channel start. + * This function is called after MHI engine was started. + * + * Return codes: 0 : success + * negative : error + */ +int ipa_mhi_connect_pipe(struct ipa_mhi_connect_params *in, u32 *clnt_hdl) +{ + int res; + unsigned long flags; + struct ipa_mhi_channel_ctx *channel = NULL; + struct ipa_mhi_connect_params_internal internal; + + IPA_MHI_FUNC_ENTRY(); + + if (!in || !clnt_hdl) { + IPA_MHI_ERR("NULL args\n"); + return -EINVAL; + } + + IPA_MHI_DBG("channel=%d\n", in->channel_id); + in->sys.client = ipa3_mhi_get_client_by_chid(in->channel_id); + + if (in->sys.client >= IPA_CLIENT_MAX) { + IPA_MHI_ERR("bad param client:%d\n", in->sys.client); + return -EINVAL; + } + + if (!IPA_CLIENT_IS_MHI(in->sys.client)) { + IPA_MHI_ERR( + "Invalid MHI client, client: %d\n", in->sys.client); + return -EINVAL; + } + + spin_lock_irqsave(&ipa_mhi_client_ctx->state_lock, flags); + if (!ipa_mhi_client_ctx || + ipa_mhi_client_ctx->state != IPA_MHI_STATE_STARTED) { + IPA_MHI_ERR("IPA MHI was not started\n"); + spin_unlock_irqrestore(&ipa_mhi_client_ctx->state_lock, flags); + return -EINVAL; + } + spin_unlock_irqrestore(&ipa_mhi_client_ctx->state_lock, flags); + + channel = ipa_mhi_get_channel_context(in->sys.client, in->channel_id); + if (!channel) { + IPA_MHI_ERR("ipa_mhi_get_channel_context failed\n"); + return -EINVAL; + } + + if (channel->state != IPA_HW_MHI_CHANNEL_STATE_INVALID && + channel->state != IPA_HW_MHI_CHANNEL_STATE_DISABLE) { + IPA_MHI_ERR("Invalid channel state %d\n", channel->state); + return -EFAULT; + } + + channel->channel_context_addr = + ipa_mhi_client_ctx->channel_context_array_addr + + channel->id * sizeof(struct ipa_mhi_ch_ctx); + + /* for event context address index needs to read from host */ + + IPA_MHI_DBG("client %d channelIndex %d channelID %d, state %d\n", + channel->client, channel->index, channel->id, channel->state); + IPA_MHI_DBG("channel_context_addr 0x%llx cached_gsi_evt_ring_hdl %lu\n", + channel->channel_context_addr, + channel->cached_gsi_evt_ring_hdl); + + IPA_ACTIVE_CLIENTS_INC_EP(in->sys.client); + + mutex_lock(&mhi_client_general_mutex); + + IPA_MHI_DBG("reading ch/ev context from host\n"); + res = ipa_mhi_read_ch_ctx(channel); + if (res) { + IPA_MHI_ERR("ipa_mhi_read_ch_ctx failed %d\n", res); + goto fail_start_channel; + } + + internal.channel_id = in->channel_id; + internal.sys = &in->sys; + internal.start.gsi.state = channel->state; + internal.start.gsi.msi = &ipa_mhi_client_ctx->msi; + internal.start.gsi.ev_ctx_host = &channel->ev_ctx_host; + internal.start.gsi.event_context_addr = + channel->event_context_addr; + internal.start.gsi.ch_ctx_host = &channel->ch_ctx_host; + internal.start.gsi.channel_context_addr = + channel->channel_context_addr; + internal.start.gsi.ch_err_cb = ipa_mhi_gsi_ch_err_cb; + internal.start.gsi.channel = (void *)channel; + internal.start.gsi.ev_err_cb = ipa_mhi_gsi_ev_err_cb; + internal.start.gsi.assert_bit40 = + ipa_mhi_client_ctx->assert_bit40; + internal.start.gsi.mhi = &channel->ch_scratch.mhi; + internal.start.gsi.cached_gsi_evt_ring_hdl = + &channel->cached_gsi_evt_ring_hdl; + internal.start.gsi.evchid = channel->index; + + res = ipa3_connect_mhi_pipe(&internal, clnt_hdl); + if (res) { + IPA_MHI_ERR("ipa_connect_mhi_pipe failed %d\n", res); + goto fail_connect_pipe; + } + channel->state = IPA_HW_MHI_CHANNEL_STATE_RUN; + channel->brstmode_enabled = + channel->ch_scratch.mhi.burst_mode_enabled; + + res = ipa_mhi_read_write_host(IPA_MHI_DMA_TO_HOST, + &channel->state, channel->channel_context_addr + + offsetof(struct ipa_mhi_ch_ctx, chstate), + sizeof(((struct ipa_mhi_ch_ctx *)0)->chstate)); + if (res) { + IPA_MHI_ERR("ipa_mhi_read_write_host failed\n"); + mutex_unlock(&mhi_client_general_mutex); + IPA_ACTIVE_CLIENTS_DEC_EP(in->sys.client); + return res; + + } + + if (in->sys.client == IPA_CLIENT_MHI_LOW_LAT_PROD) + ipa3_update_mhi_ctrl_state(IPA_MHI_CTRL_UL_SETUP, true); + else if (in->sys.client == IPA_CLIENT_MHI_LOW_LAT_CONS) + ipa3_update_mhi_ctrl_state(IPA_MHI_CTRL_DL_SETUP, true); + + mutex_unlock(&mhi_client_general_mutex); + + if (!in->sys.keep_ipa_awake) + IPA_ACTIVE_CLIENTS_DEC_EP(in->sys.client); + + IPA_MHI_FUNC_EXIT(); + + return 0; +fail_connect_pipe: + ipa_mhi_reset_channel(channel, true); +fail_start_channel: + mutex_unlock(&mhi_client_general_mutex); + IPA_ACTIVE_CLIENTS_DEC_EP(in->sys.client); + return -EPERM; +} +EXPORT_SYMBOL(ipa_mhi_connect_pipe); + +/** + * ipa_mhi_disconnect_pipe() - Disconnect pipe from IPA and reset corresponding + * MHI channel + * @clnt_hdl: client handle for this pipe + * + * This function is called by MHI client driver on MHI channel reset. + * This function is called after MHI channel was started. + * This function is doing the following: + * - Send command to uC/GSI to reset corresponding MHI channel + * - Configure IPA EP control + * + * Return codes: 0 : success + * negative : error + */ +int ipa_mhi_disconnect_pipe(u32 clnt_hdl) +{ + int res; + enum ipa_client_type client; + static struct ipa_mhi_channel_ctx *channel; + + IPA_MHI_FUNC_ENTRY(); + + if (!ipa_mhi_client_ctx) { + IPA_MHI_ERR("IPA MHI was not initialized\n"); + return -EINVAL; + } + + client = ipa3_get_client_mapping(clnt_hdl); + + if (!IPA_CLIENT_IS_MHI(client)) { + IPA_MHI_ERR("invalid IPA MHI client, client: %d\n", client); + return -EINVAL; + } + + channel = ipa_mhi_get_channel_context_by_clnt_hdl(clnt_hdl); + if (!channel) { + IPA_MHI_ERR("invalid clnt index\n"); + return -EINVAL; + } + + if (client == IPA_CLIENT_MHI_LOW_LAT_PROD) + ipa3_update_mhi_ctrl_state(IPA_MHI_CTRL_UL_SETUP, false); + else if (client == IPA_CLIENT_MHI_LOW_LAT_CONS) + ipa3_update_mhi_ctrl_state(IPA_MHI_CTRL_DL_SETUP, false); + IPA_ACTIVE_CLIENTS_INC_EP(client); + + res = ipa_mhi_reset_channel(channel, false); + if (res) { + IPA_MHI_ERR("ipa_mhi_reset_channel failed %d\n", res); + goto fail_reset_channel; + } + + mutex_lock(&mhi_client_general_mutex); + res = ipa3_disconnect_mhi_pipe(clnt_hdl); + if (res) { + IPA_MHI_ERR( + "IPA core driver failed to disconnect the pipe hdl %d, res %d" + , clnt_hdl, res); + goto fail_disconnect_pipe; + } + mutex_unlock(&mhi_client_general_mutex); + + IPA_ACTIVE_CLIENTS_DEC_EP(client); + + IPA_MHI_DBG("client (ep: %d) disconnected\n", clnt_hdl); + IPA_MHI_FUNC_EXIT(); + return 0; +fail_disconnect_pipe: + mutex_unlock(&mhi_client_general_mutex); +fail_reset_channel: + IPA_ACTIVE_CLIENTS_DEC_EP(client); + return res; +} +EXPORT_SYMBOL(ipa_mhi_disconnect_pipe); + +static int ipa_mhi_suspend_channels(struct ipa_mhi_channel_ctx *channels, + int max_channels) +{ + int i; + int res; + + IPA_MHI_FUNC_ENTRY(); + for (i = 0; i < max_channels; i++) { + if (!channels[i].valid) + continue; + if (channels[i].state != + IPA_HW_MHI_CHANNEL_STATE_RUN) + continue; + IPA_MHI_DBG("suspending channel %d\n", + channels[i].id); + + res = ipa_mhi_suspend_gsi_channel(&channels[i]); + + if (res) { + IPA_MHI_ERR("failed to suspend channel %d error %d\n", + i, res); + return res; + } + channels[i].state = + IPA_HW_MHI_CHANNEL_STATE_SUSPEND; + } + + IPA_MHI_FUNC_EXIT(); + return 0; +} + +static int ipa_mhi_stop_event_update_channels( + struct ipa_mhi_channel_ctx *channels, int max_channels) +{ + return 0; +} + +static bool ipa_mhi_check_pending_packets_from_host(void) +{ + int i; + int res; + struct ipa_mhi_channel_ctx *channel; + + IPA_MHI_FUNC_ENTRY(); + for (i = 0; i < IPA_MHI_MAX_UL_CHANNELS; i++) { + channel = &ipa_mhi_client_ctx->ul_channels[i]; + if (!channel->valid) + continue; + + res = ipa3_mhi_query_ch_info(channel->client, + &channel->ch_info); + if (res) { + IPA_MHI_ERR("gsi_query_channel_info failed\n"); + return true; + } + res = ipa_mhi_read_ch_ctx(channel); + if (res) { + IPA_MHI_ERR("ipa_mhi_read_ch_ctx failed %d\n", res); + return true; + } + + if (channel->ch_info.rp != channel->ch_ctx_host.wp) { + IPA_MHI_DBG("There are pending packets from host\n"); + IPA_MHI_DBG("device rp 0x%llx host 0x%llx\n", + channel->ch_info.rp, channel->ch_ctx_host.wp); + + return true; + } + } + + IPA_MHI_FUNC_EXIT(); + return false; +} + +static int ipa_mhi_resume_channels(bool LPTransitionRejected, + struct ipa_mhi_channel_ctx *channels, int max_channels) +{ + int i; + int res = 0; + bool is_switch_to_dbmode; + struct ipa_mhi_channel_ctx *channel; + + IPA_MHI_FUNC_ENTRY(); + for (i = 0; i < max_channels; i++) { + if (!channels[i].valid) + continue; + if (channels[i].state != IPA_HW_MHI_CHANNEL_STATE_SUSPEND && + !channels[i].stop_in_proc) + continue; + channel = &channels[i]; + mutex_lock(&mhi_client_general_mutex); + IPA_MHI_DBG("resuming channel %d, mstate = %d\n", + channel->id, ipa_mhi_client_ctx->mhi_mstate); + switch (ipa_mhi_client_ctx->mhi_mstate) { + case IPA_MHI_STATE_M3: + is_switch_to_dbmode = true; + break; + case IPA_MHI_STATE_M2: + case IPA_MHI_STATE_M1: + is_switch_to_dbmode = false; + break; + case IPA_MHI_STATE_M0: + IPA_MHI_ERR("Resume in M0 - not expected\n"); + res = -EINVAL; + break; + case IPA_MHI_STATE_M_MAX: + IPA_MHI_ERR("No knowledge of M state\n"); + res = -EINVAL; + break; + default: + IPA_MHI_ERR("Unknown Mstart %d\n", + ipa_mhi_client_ctx->mhi_mstate); + res = -EINVAL; + break; + } + mutex_unlock(&mhi_client_general_mutex); + + if (res) + return res; + + IPA_MHI_DBG("is DB mode? %d\n", is_switch_to_dbmode); + res = ipa3_mhi_resume_channels_internal(channel->client, + LPTransitionRejected, channel->brstmode_enabled, + channel->ch_scratch, channel->index, + is_switch_to_dbmode); + + if (res) { + IPA_MHI_ERR("failed to resume channel %d error %d\n", + i, res); + return res; + } + + channel->stop_in_proc = false; + channel->state = IPA_HW_MHI_CHANNEL_STATE_RUN; + } + + IPA_MHI_FUNC_EXIT(); + return 0; +} + +/** + * ipa_mhi_suspend_ul() - Suspend MHI accelerated up link channels + * @force: + * false: in case of data pending in IPA, MHI channels will not be + * suspended and function will fail. + * true: in case of data pending in IPA, make sure no further access from + * IPA to PCIe is possible. In this case suspend cannot fail. + * + * + * This function is called by MHI client driver on MHI suspend. + * This function is called after MHI channel was started. + * When this function returns device can move to M1/M2/M3/D3cold state. + * + * Return codes: 0 : success + * negative : error + */ +static int ipa_mhi_suspend_ul(bool force, bool *empty, bool *force_clear) +{ + int res; + + *force_clear = false; + + res = ipa_mhi_suspend_channels(ipa_mhi_client_ctx->ul_channels, + IPA_MHI_MAX_UL_CHANNELS); + if (res) { + IPA_MHI_ERR("ipa_mhi_suspend_ul_channels failed %d\n", res); + goto fail_suspend_ul_channel; + } + + *empty = ipa_mhi_wait_for_ul_empty_timeout( + IPA_MHI_CH_EMPTY_TIMEOUT_MSEC); + + if (!*empty) { + if (force) { + res = ipa_mhi_enable_force_clear( + ipa_mhi_client_ctx->qmi_req_id, false); + if (res) { + IPA_MHI_ERR("failed to enable force clear\n"); + ipa_assert(); + return res; + } + *force_clear = true; + IPA_MHI_DBG("force clear datapath enabled\n"); + + *empty = ipa_mhi_wait_for_ul_empty_timeout( + IPA_MHI_CH_EMPTY_TIMEOUT_MSEC); + IPA_MHI_DBG("empty=%d\n", *empty); + if (!*empty) { + IPA_MHI_ERR("Failed to suspend UL channels\n"); + if (ipa_mhi_client_ctx->test_mode) { + res = -EAGAIN; + goto fail_suspend_ul_channel; + } + + ipa_assert(); + } + } else { + IPA_MHI_DBG("IPA not empty\n"); + res = -EAGAIN; + goto fail_suspend_ul_channel; + } + } + + if (*force_clear) { + res = + ipa_mhi_disable_force_clear(ipa_mhi_client_ctx->qmi_req_id); + if (res) { + IPA_MHI_ERR("failed to disable force clear\n"); + ipa_assert(); + return res; + } + IPA_MHI_DBG("force clear datapath disabled\n"); + ipa_mhi_client_ctx->qmi_req_id++; + } + + if (!force) { + if (ipa_mhi_check_pending_packets_from_host()) { + res = -EAGAIN; + goto fail_suspend_ul_channel; + } + } + + res = ipa_mhi_stop_event_update_channels( + ipa_mhi_client_ctx->ul_channels, IPA_MHI_MAX_UL_CHANNELS); + if (res) { + IPA_MHI_ERR( + "ipa_mhi_stop_event_update_ul_channels failed %d\n", + res); + goto fail_suspend_ul_channel; + } + + return 0; + +fail_suspend_ul_channel: + return res; +} + +static bool ipa_mhi_has_open_aggr_frame(void) +{ + struct ipa_mhi_channel_ctx *channel; + int i; + + for (i = 0; i < IPA_MHI_MAX_DL_CHANNELS; i++) { + channel = &ipa_mhi_client_ctx->dl_channels[i]; + + if (!channel->valid) + continue; + + if (ipa3_has_open_aggr_frame(channel->client)) + return true; + } + + return false; +} + +static void ipa_mhi_update_host_ch_state(bool update_rp) +{ + int i; + int res; + struct ipa_mhi_channel_ctx *channel; + + for (i = 0; i < IPA_MHI_MAX_UL_CHANNELS; i++) { + channel = &ipa_mhi_client_ctx->ul_channels[i]; + if (!channel->valid) + continue; + + if (update_rp) { + res = ipa3_mhi_query_ch_info(channel->client, + &channel->ch_info); + if (res) { + IPA_MHI_ERR("gsi_query_channel_info failed\n"); + ipa_assert(); + return; + } + + res = ipa_mhi_read_write_host(IPA_MHI_DMA_TO_HOST, + &channel->ch_info.rp, + channel->channel_context_addr + + offsetof(struct ipa_mhi_ch_ctx, rp), + sizeof(channel->ch_info.rp)); + if (res) { + IPA_MHI_ERR("ipa_mhi_read_write_host failed\n"); + ipa_assert(); + return; + } + } + + res = ipa_mhi_read_write_host(IPA_MHI_DMA_TO_HOST, + &channel->state, channel->channel_context_addr + + offsetof(struct ipa_mhi_ch_ctx, chstate), + sizeof(((struct ipa_mhi_ch_ctx *)0)->chstate)); + if (res) { + IPA_MHI_ERR("ipa_mhi_read_write_host failed\n"); + ipa_assert(); + return; + } + IPA_MHI_DBG("Updated UL CH=%d state to %s on host\n", + i, MHI_CH_STATE_STR(channel->state)); + } + + for (i = 0; i < IPA_MHI_MAX_DL_CHANNELS; i++) { + channel = &ipa_mhi_client_ctx->dl_channels[i]; + if (!channel->valid) + continue; + + if (update_rp) { + res = ipa3_mhi_query_ch_info(channel->client, + &channel->ch_info); + if (res) { + IPA_MHI_ERR("gsi_query_channel_info failed\n"); + ipa_assert(); + return; + } + + res = ipa_mhi_read_write_host(IPA_MHI_DMA_TO_HOST, + &channel->ch_info.rp, + channel->channel_context_addr + + offsetof(struct ipa_mhi_ch_ctx, rp), + sizeof(channel->ch_info.rp)); + if (res) { + IPA_MHI_ERR("ipa_mhi_read_write_host failed\n"); + ipa_assert(); + return; + } + } + + res = ipa_mhi_read_write_host(IPA_MHI_DMA_TO_HOST, + &channel->state, channel->channel_context_addr + + offsetof(struct ipa_mhi_ch_ctx, chstate), + sizeof(((struct ipa_mhi_ch_ctx *)0)->chstate)); + if (res) { + IPA_MHI_ERR("ipa_mhi_read_write_host failed\n"); + ipa_assert(); + return; + } + IPA_MHI_DBG("Updated DL CH=%d state to %s on host\n", + i, MHI_CH_STATE_STR(channel->state)); + } +} + +static int ipa_mhi_suspend_dl(bool force) +{ + int res; + + res = ipa_mhi_suspend_channels(ipa_mhi_client_ctx->dl_channels, + IPA_MHI_MAX_DL_CHANNELS); + if (res) { + IPA_MHI_ERR( + "ipa_mhi_suspend_channels for dl failed %d\n", res); + goto fail_suspend_dl_channel; + } + + res = ipa_mhi_stop_event_update_channels + (ipa_mhi_client_ctx->dl_channels, + IPA_MHI_MAX_DL_CHANNELS); + if (res) { + IPA_MHI_ERR("failed to stop event update on DL %d\n", res); + goto fail_stop_event_update_dl_channel; + } + + if (ipa_mhi_has_open_aggr_frame()) { + IPA_MHI_DBG("There is an open aggr frame\n"); + if (force) { + ipa_mhi_client_ctx->trigger_wakeup = true; + } else { + res = -EAGAIN; + goto fail_stop_event_update_dl_channel; + } + } + + return 0; + +fail_stop_event_update_dl_channel: + ipa_mhi_resume_channels(true, + ipa_mhi_client_ctx->dl_channels, + IPA_MHI_MAX_DL_CHANNELS); +fail_suspend_dl_channel: + return res; +} + +/** + * ipa_mhi_suspend() - Suspend MHI accelerated channels + * @force: + * false: in case of data pending in IPA, MHI channels will not be + * suspended and function will fail. + * true: in case of data pending in IPA, make sure no further access from + * IPA to PCIe is possible. In this case suspend cannot fail. + * + * This function is called by MHI client driver on MHI suspend. + * This function is called after MHI channel was started. + * When this function returns device can move to M1/M2/M3/D3cold state. + * + * Return codes: 0 : success + * negative : error + */ +int ipa_mhi_suspend(bool force) +{ + int res; + bool empty; + bool force_clear; + + IPA_MHI_FUNC_ENTRY(); + + res = ipa_mhi_set_state(IPA_MHI_STATE_SUSPEND_IN_PROGRESS); + if (res) { + IPA_MHI_ERR("ipa_mhi_set_state failed %d\n", res); + return res; + } + + res = ipa_mhi_suspend_dl(force); + if (res) { + IPA_MHI_ERR("ipa_mhi_suspend_dl failed %d\n", res); + goto fail_suspend_dl_channel; + } + + usleep_range(IPA_MHI_SUSPEND_SLEEP_MIN, IPA_MHI_SUSPEND_SLEEP_MAX); + + res = ipa_mhi_suspend_ul(force, &empty, &force_clear); + if (res) { + IPA_MHI_ERR("ipa_mhi_suspend_ul failed %d\n", res); + goto fail_suspend_ul_channel; + } + + ipa_mhi_update_host_ch_state(true); + + /* + * hold IPA clocks and release them after all + * IPA PM clients are deactivated to make sure tag process + * will not start + */ + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + + res = ipa_pm_deactivate_sync(ipa_mhi_client_ctx->pm_hdl); + if (res) { + IPA_MHI_ERR("fail to deactivate client %d\n", res); + goto fail_deactivate_pm; + } + res = ipa_pm_deactivate_sync(ipa_mhi_client_ctx->modem_pm_hdl); + if (res) { + IPA_MHI_ERR("fail to deactivate client %d\n", res); + goto fail_deactivate_modem_pm; + } + usleep_range(IPA_MHI_SUSPEND_SLEEP_MIN, IPA_MHI_SUSPEND_SLEEP_MAX); + + if (!empty) + ipa3_set_tag_process_before_gating(false); + + res = ipa_mhi_set_state(IPA_MHI_STATE_SUSPENDED); + if (res) { + IPA_MHI_ERR("ipa_mhi_set_state failed %d\n", res); + goto fail_release_cons; + } + + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + IPA_MHI_FUNC_EXIT(); + return 0; + +fail_release_cons: + ipa_pm_activate_sync(ipa_mhi_client_ctx->modem_pm_hdl); +fail_deactivate_modem_pm: + ipa_pm_activate_sync(ipa_mhi_client_ctx->pm_hdl); +fail_deactivate_pm: + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); +fail_suspend_ul_channel: + ipa_mhi_resume_channels(true, ipa_mhi_client_ctx->ul_channels, + IPA_MHI_MAX_UL_CHANNELS); + if (force_clear) { + if ( + ipa_mhi_disable_force_clear(ipa_mhi_client_ctx->qmi_req_id)) { + IPA_MHI_ERR("failed to disable force clear\n"); + ipa_assert(); + } + IPA_MHI_DBG("force clear datapath disabled\n"); + ipa_mhi_client_ctx->qmi_req_id++; + } +fail_suspend_dl_channel: + ipa_mhi_resume_channels(true, ipa_mhi_client_ctx->dl_channels, + IPA_MHI_MAX_DL_CHANNELS); + ipa_mhi_set_state(IPA_MHI_STATE_STARTED); + return res; +} +EXPORT_SYMBOL(ipa_mhi_suspend); + +/** + * ipa_mhi_resume() - Resume MHI accelerated channels + * + * This function is called by MHI client driver on MHI resume. + * This function is called after MHI channel was suspended. + * When this function returns device can move to M0 state. + * This function is doing the following: + * - Send command to uC/GSI to resume corresponding MHI channel + * - Activate PM clients + * - Resume data to IPA + * + * Return codes: 0 : success + * negative : error + */ +int ipa_mhi_resume(void) +{ + int res; + + IPA_MHI_FUNC_ENTRY(); + + res = ipa_mhi_set_state(IPA_MHI_STATE_RESUME_IN_PROGRESS); + if (res) { + IPA_MHI_ERR("ipa_mhi_set_state failed %d\n", res); + return res; + } + + res = ipa_pm_activate_sync(ipa_mhi_client_ctx->pm_hdl); + if (res) { + IPA_MHI_ERR("fail to activate client %d\n", res); + goto fail_pm_activate; + } + + res = ipa_pm_activate_sync(ipa_mhi_client_ctx->modem_pm_hdl); + if (res) { + IPA_MHI_ERR("fail to activate client %d\n", res); + goto fail_pm_activate_modem; + } + + /* resume all UL channels */ + res = ipa_mhi_resume_channels(false, + ipa_mhi_client_ctx->ul_channels, + IPA_MHI_MAX_UL_CHANNELS); + if (res) { + IPA_MHI_ERR("ipa_mhi_resume_ul_channels failed %d\n", res); + goto fail_resume_ul_channels; + } + + res = ipa_mhi_resume_channels(false, + ipa_mhi_client_ctx->dl_channels, + IPA_MHI_MAX_DL_CHANNELS); + if (res) { + IPA_MHI_ERR("ipa_mhi_resume_dl_channels failed %d\n", + res); + goto fail_resume_dl_channels; + } + + ipa_mhi_update_host_ch_state(false); + + res = ipa_mhi_set_state(IPA_MHI_STATE_STARTED); + if (res) { + IPA_MHI_ERR("ipa_mhi_set_state failed %d\n", res); + goto fail_set_state; + } + + IPA_MHI_FUNC_EXIT(); + return 0; + +fail_set_state: + ipa_mhi_suspend_channels(ipa_mhi_client_ctx->dl_channels, + IPA_MHI_MAX_DL_CHANNELS); +fail_resume_dl_channels: + ipa_mhi_suspend_channels(ipa_mhi_client_ctx->ul_channels, + IPA_MHI_MAX_UL_CHANNELS); +fail_resume_ul_channels: + ipa_pm_deactivate_sync(ipa_mhi_client_ctx->modem_pm_hdl); +fail_pm_activate_modem: + ipa_pm_deactivate_sync(ipa_mhi_client_ctx->pm_hdl); +fail_pm_activate: + ipa_mhi_set_state(IPA_MHI_STATE_SUSPENDED); + return res; +} +EXPORT_SYMBOL(ipa_mhi_resume); + + +static int ipa_mhi_destroy_channels(struct ipa_mhi_channel_ctx *channels, + int num_of_channels) +{ + struct ipa_mhi_channel_ctx *channel; + int i, res; + u32 clnt_hdl; + + for (i = 0; i < num_of_channels; i++) { + channel = &channels[i]; + if (!channel->valid) + continue; + if (channel->state == IPA_HW_MHI_CHANNEL_STATE_INVALID) + continue; + if (channel->state != IPA_HW_MHI_CHANNEL_STATE_DISABLE) { + clnt_hdl = ipa_get_ep_mapping(channel->client); + IPA_MHI_DBG("disconnect pipe (ep: %d)\n", clnt_hdl); + res = ipa_mhi_disconnect_pipe(clnt_hdl); + if (res) { + IPA_MHI_ERR( + "failed to disconnect pipe %d, err %d\n" + , clnt_hdl, res); + goto fail; + } + } + res = ipa3_mhi_destroy_channel(channel->client); + if (res) { + IPA_MHI_ERR( + "ipa3_mhi_destroy_channel failed %d" + , res); + goto fail; + } + } + return 0; +fail: + return res; +} + +/** + * ipa_mhi_destroy_all_channels() - Destroy MHI IPA channels + * + * This function is called by IPA MHI client driver on MHI reset to destroy all + * IPA MHI channels. + */ +int ipa_mhi_destroy_all_channels(void) +{ + int res; + + IPA_MHI_FUNC_ENTRY(); + /* reset all UL and DL acc channels and its accociated event rings */ + res = ipa_mhi_destroy_channels(ipa_mhi_client_ctx->ul_channels, + IPA_MHI_MAX_UL_CHANNELS); + if (res) { + IPA_MHI_ERR("ipa_mhi_destroy_channels(ul_channels) failed %d\n", + res); + return -EPERM; + } + IPA_MHI_DBG("All UL channels are disconnected\n"); + + res = ipa_mhi_destroy_channels(ipa_mhi_client_ctx->dl_channels, + IPA_MHI_MAX_DL_CHANNELS); + if (res) { + IPA_MHI_ERR("ipa_mhi_destroy_channels(dl_channels) failed %d\n", + res); + return -EPERM; + } + IPA_MHI_DBG("All DL channels are disconnected\n"); + + IPA_MHI_FUNC_EXIT(); + return 0; +} + +#ifdef CONFIG_DEBUG_FS +static void ipa_mhi_debugfs_destroy(void) +{ + debugfs_remove_recursive(dent); +} +#endif + +static void ipa_mhi_deregister_pm(void) +{ + ipa_pm_deactivate_sync(ipa_mhi_client_ctx->pm_hdl); + ipa_pm_deregister(ipa_mhi_client_ctx->pm_hdl); + ipa_mhi_client_ctx->pm_hdl = ~0; + + ipa_pm_deactivate_sync(ipa_mhi_client_ctx->modem_pm_hdl); + ipa_pm_deregister(ipa_mhi_client_ctx->modem_pm_hdl); + ipa_mhi_client_ctx->modem_pm_hdl = ~0; +} + +/** + * ipa_mhi_destroy() - Destroy MHI IPA + * + * This function is called by MHI client driver on MHI reset to destroy all IPA + * MHI resources. + * When this function returns ipa_mhi can re-initialize. + */ +void ipa_mhi_destroy(void) +{ + int res; + + IPA_MHI_FUNC_ENTRY(); + if (!ipa_mhi_client_ctx) { + IPA_MHI_DBG("IPA MHI was not initialized, already destroyed\n"); + return; + } + + ipa3_deregister_client_callback(IPA_CLIENT_MHI_PROD); + + /* reset all UL and DL acc channels and its accociated event rings */ + res = ipa_mhi_destroy_all_channels(); + if (res) { + IPA_MHI_ERR("ipa_mhi_destroy_all_channels failed %d\n", + res); + goto fail; + } + IPA_MHI_DBG("All channels are disconnected\n"); + + ipa_mhi_deregister_pm(); + ipa_dma_destroy(); + ipa_mhi_debugfs_destroy(); + destroy_workqueue(ipa_mhi_client_ctx->wq); + kfree(ipa_mhi_client_ctx); + ipa_mhi_client_ctx = NULL; + IPA_MHI_DBG("IPA MHI was reset, ready for re-init\n"); + + IPA_MHI_FUNC_EXIT(); + return; +fail: + ipa_assert(); +} +EXPORT_SYMBOL(ipa_mhi_destroy); + +static void ipa_mhi_pm_cb(void *p, enum ipa_pm_cb_event event) +{ + unsigned long flags; + + IPA_MHI_FUNC_ENTRY(); + + if (event != IPA_PM_REQUEST_WAKEUP) { + IPA_MHI_ERR("Unexpected event %d\n", event); + WARN_ON(1); + return; + } + + IPA_MHI_DBG("%s\n", MHI_STATE_STR(ipa_mhi_client_ctx->state)); + spin_lock_irqsave(&ipa_mhi_client_ctx->state_lock, flags); + if (ipa_mhi_client_ctx->state == IPA_MHI_STATE_SUSPENDED) { + ipa_mhi_notify_wakeup(); + } else if (ipa_mhi_client_ctx->state == + IPA_MHI_STATE_SUSPEND_IN_PROGRESS) { + /* wakeup event will be trigger after suspend finishes */ + ipa_mhi_client_ctx->trigger_wakeup = true; + } + spin_unlock_irqrestore(&ipa_mhi_client_ctx->state_lock, flags); + IPA_MHI_DBG("EXIT"); +} + +static int ipa_mhi_register_pm(void) +{ + int res; + struct ipa_pm_register_params params; + + memset(¶ms, 0, sizeof(params)); + params.name = "MHI"; + params.callback = ipa_mhi_pm_cb; + params.group = IPA_PM_GROUP_DEFAULT; + res = ipa_pm_register(¶ms, &ipa_mhi_client_ctx->pm_hdl); + if (res) { + IPA_MHI_ERR("fail to register with PM %d\n", res); + return res; + } + + res = ipa_pm_associate_ipa_cons_to_client(ipa_mhi_client_ctx->pm_hdl, + IPA_CLIENT_MHI_CONS); + if (res) { + IPA_MHI_ERR("fail to associate cons with PM %d\n", res); + goto fail_pm_cons; + } + + res = ipa_pm_associate_ipa_cons_to_client(ipa_mhi_client_ctx->pm_hdl, + IPA_CLIENT_MHI_LOW_LAT_CONS); + if (res) { + IPA_MHI_ERR("fail to associate low_lat_cons with PM %d\n", res); + goto fail_pm_cons; + } + + res = ipa_pm_set_throughput(ipa_mhi_client_ctx->pm_hdl, 1000); + if (res) { + IPA_MHI_ERR("fail to set perf profile to PM %d\n", res); + goto fail_pm_cons; + } + + /* create a modem client for clock scaling */ + memset(¶ms, 0, sizeof(params)); + params.name = "MODEM (MHI)"; + params.group = IPA_PM_GROUP_MODEM; + params.skip_clk_vote = true; + res = ipa_pm_register(¶ms, &ipa_mhi_client_ctx->modem_pm_hdl); + if (res) { + IPA_MHI_ERR("fail to register with PM %d\n", res); + goto fail_pm_cons; + } + + return 0; + +fail_pm_cons: + ipa_pm_deregister(ipa_mhi_client_ctx->pm_hdl); + ipa_mhi_client_ctx->pm_hdl = ~0; + return res; +} + +/** + * ipa_mhi_init() - Initialize IPA MHI driver + * @params: initialization params + * + * This function is called by MHI client driver on boot to initialize IPA MHI + * Driver. When this function returns device can move to READY state. + * This function is doing the following: + * - Initialize MHI IPA internal data structures + * - Register with PM + * - Initialize debugfs + * + * Return codes: 0 : success + * negative : error + */ +int ipa_mhi_init(struct ipa_mhi_init_params *params) +{ + int res; + + IPA_MHI_FUNC_ENTRY(); + + if (!params) { + IPA_MHI_ERR("null args\n"); + return -EINVAL; + } + + if (!params->notify) { + IPA_MHI_ERR("null notify function\n"); + return -EINVAL; + } + + if (ipa_mhi_client_ctx) { + IPA_MHI_ERR("already initialized\n"); + return -EPERM; + } + + IPA_MHI_DBG("notify = %pS priv = %pK\n", params->notify, params->priv); + IPA_MHI_DBG("msi: addr_lo = 0x%x addr_hi = 0x%x\n", + params->msi.addr_low, params->msi.addr_hi); + IPA_MHI_DBG("msi: data = 0x%x mask = 0x%x\n", + params->msi.data, params->msi.mask); + IPA_MHI_DBG("mmio_addr = 0x%x\n", params->mmio_addr); + IPA_MHI_DBG("first_ch_idx = 0x%x\n", params->first_ch_idx); + IPA_MHI_DBG("first_er_idx = 0x%x\n", params->first_er_idx); + IPA_MHI_DBG("assert_bit40=%d\n", params->assert_bit40); + IPA_MHI_DBG("test_mode=%d\n", params->test_mode); + + /* Initialize context */ + ipa_mhi_client_ctx = kzalloc(sizeof(*ipa_mhi_client_ctx), GFP_KERNEL); + if (!ipa_mhi_client_ctx) { + res = -EFAULT; + goto fail_alloc_ctx; + } + + ipa_mhi_client_ctx->state = IPA_MHI_STATE_INITIALIZED; + ipa_mhi_client_ctx->cb_notify = params->notify; + ipa_mhi_client_ctx->cb_priv = params->priv; + spin_lock_init(&ipa_mhi_client_ctx->state_lock); + ipa_mhi_client_ctx->msi = params->msi; + ipa_mhi_client_ctx->mmio_addr = params->mmio_addr; + ipa_mhi_client_ctx->first_ch_idx = params->first_ch_idx; + ipa_mhi_client_ctx->first_er_idx = params->first_er_idx; + ipa_mhi_client_ctx->qmi_req_id = 0; + ipa_mhi_client_ctx->use_ipadma = true; + ipa_mhi_client_ctx->assert_bit40 = !!params->assert_bit40; + ipa_mhi_client_ctx->test_mode = params->test_mode; + ipa_mhi_client_ctx->mhi_mstate = IPA_MHI_STATE_M0; + + ipa_mhi_client_ctx->wq = create_singlethread_workqueue("ipa_mhi_wq"); + if (!ipa_mhi_client_ctx->wq) { + IPA_MHI_ERR("failed to create workqueue\n"); + res = -EFAULT; + goto fail_create_wq; + } + + res = ipa_dma_init(); + if (res) { + IPA_MHI_ERR("failed to init ipa dma %d\n", res); + goto fail_dma_init; + } + + res = ipa_mhi_register_pm(); + if (res) { + IPA_MHI_ERR("failed to create PM resources\n"); + res = -EFAULT; + goto fail_pm; + } + + ipa_mhi_set_state(IPA_MHI_STATE_READY); + + ipa3_register_client_callback(&ipa_mhi_set_lock_unlock, NULL, + IPA_CLIENT_MHI_PROD); + + /* Initialize debugfs */ + ipa_mhi_debugfs_init(); + + IPA_MHI_FUNC_EXIT(); + return 0; + +fail_pm: + ipa_dma_destroy(); +fail_dma_init: + destroy_workqueue(ipa_mhi_client_ctx->wq); +fail_create_wq: + kfree(ipa_mhi_client_ctx); + ipa_mhi_client_ctx = NULL; +fail_alloc_ctx: + return res; +} +EXPORT_SYMBOL(ipa_mhi_init); + +/** + * ipa_mhi_handle_ipa_config_req() - hanle IPA CONFIG QMI message + * + * This function is called by by IPA QMI service to indicate that IPA CONFIG + * message was sent from modem. IPA MHI will update this information to IPA uC + * or will cache it until IPA MHI will be initialized. + * + * Return codes: 0 : success + * negative : error + */ +int ipa_mhi_handle_ipa_config_req(struct ipa_config_req_msg_v01 *config_req) +{ + IPA_MHI_FUNC_ENTRY(); + IPA_MHI_FUNC_EXIT(); + return 0; +} +EXPORT_SYMBOL(ipa_mhi_handle_ipa_config_req); + +int ipa_mhi_is_using_dma(bool *flag) +{ + IPA_MHI_FUNC_ENTRY(); + + if (!ipa_mhi_client_ctx) { + IPA_MHI_ERR("not initialized\n"); + return -EPERM; + } + + *flag = ipa_mhi_client_ctx->use_ipadma ? true : false; + + IPA_MHI_FUNC_EXIT(); + return 0; +} + +/** + * ipa_mhi_update_mstate() - Provides M state info + * @mstate_info: + * state_m0: in case of resume happening because of mhi going + * into M0 state. + * state_m2: in case of suspend/resume happening because of mhi going + * into M2 state. + * state_m3: in case of suspend/resume happening because of mhi going + * into M3 state. + * + * This function is called by MHI client driver before MHI suspend/ resume. + * This function is called before MHI suspend or after MHI resume. + * When this function returns device can move to M1/M2/M3/D3cold state. + * + * Return codes: 0 : success + * negative : error + */ +int ipa_mhi_update_mstate(enum ipa_mhi_mstate mstate_info) +{ + IPA_MHI_FUNC_ENTRY(); + + if (!ipa_mhi_client_ctx) { + IPA_MHI_ERR("ipa_mhi_client_ctx not created yet %d mstate\n", + mstate_info); + return -EPERM; + } + + IPA_MHI_DBG("Req update mstate to %d\n", mstate_info); + mutex_lock(&mhi_client_general_mutex); + ipa_mhi_client_ctx->mhi_mstate = mstate_info; + mutex_unlock(&mhi_client_general_mutex); + IPA_MHI_FUNC_EXIT(); + return 0; +} +EXPORT_SYMBOL(ipa_mhi_update_mstate); + + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("IPA MHI client driver"); diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_clients/ipa_uc_offload.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_clients/ipa_uc_offload.c new file mode 100644 index 0000000000..09b2e66481 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_clients/ipa_uc_offload.c @@ -0,0 +1,733 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved. + */ + +#include "ipa_uc_offload.h" +#include +#include +#include "ipa_common_i.h" +#include "ipa_pm.h" + +#define IPA_NTN_DMA_POOL_ALIGNMENT 8 +#define OFFLOAD_DRV_NAME "ipa_uc_offload" +#define IPA_UC_OFFLOAD_DBG(fmt, args...) \ + do { \ + pr_debug(OFFLOAD_DRV_NAME " %s:%d " fmt, \ + __func__, __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf(), \ + OFFLOAD_DRV_NAME " %s:%d " fmt, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf_low(), \ + OFFLOAD_DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) + +#define IPA_UC_OFFLOAD_LOW(fmt, args...) \ + do { \ + pr_debug(OFFLOAD_DRV_NAME " %s:%d " fmt, \ + __func__, __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf_low(), \ + OFFLOAD_DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) + +#define IPA_UC_OFFLOAD_ERR(fmt, args...) \ + do { \ + pr_err(OFFLOAD_DRV_NAME " %s:%d " fmt, \ + __func__, __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf(), \ + OFFLOAD_DRV_NAME " %s:%d " fmt, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf_low(), \ + OFFLOAD_DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) + +#define IPA_UC_OFFLOAD_INFO(fmt, args...) \ + do { \ + pr_info(OFFLOAD_DRV_NAME " %s:%d " fmt, \ + __func__, __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf(), \ + OFFLOAD_DRV_NAME " %s:%d " fmt, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf_low(), \ + OFFLOAD_DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) + +enum ipa_uc_offload_state { + IPA_UC_OFFLOAD_STATE_INVALID, + IPA_UC_OFFLOAD_STATE_INITIALIZED, + IPA_UC_OFFLOAD_STATE_UP, +}; + +struct ipa_uc_offload_ctx { + enum ipa_uc_offload_proto proto; + enum ipa_uc_offload_state state; + void *priv; + u8 hdr_len; + u32 partial_hdr_hdl[IPA_IP_MAX]; + char netdev_name[IPA_RESOURCE_NAME_MAX]; + ipa_notify_cb notify; + struct completion ntn_completion; + u32 pm_hdl; + struct ipa_ntn_conn_in_params conn; +}; + +static struct ipa_uc_offload_ctx *ipa_uc_offload_ctx[IPA_UC_MAX_PROT_SIZE]; + + +static int ipa_commit_partial_hdr( + struct ipa_ioc_add_hdr *hdr, + const char *netdev_name, + struct ipa_hdr_info *hdr_info) +{ + int i; + + if (hdr == NULL || hdr_info == NULL) { + IPA_UC_OFFLOAD_ERR("Invalid input\n"); + return -EINVAL; + } + + hdr->commit = 0; + hdr->num_hdrs = 2; + + snprintf(hdr->hdr[0].name, sizeof(hdr->hdr[0].name), + "%s_ipv4", netdev_name); + snprintf(hdr->hdr[1].name, sizeof(hdr->hdr[1].name), + "%s_ipv6", netdev_name); + for (i = IPA_IP_v4; i < IPA_IP_MAX; i++) { + hdr->hdr[i].hdr_len = hdr_info[i].hdr_len; + memcpy(hdr->hdr[i].hdr, hdr_info[i].hdr, hdr->hdr[i].hdr_len); + hdr->hdr[i].type = hdr_info[i].hdr_type; + hdr->hdr[i].is_partial = 1; + hdr->hdr[i].is_eth2_ofst_valid = 1; + hdr->hdr[i].eth2_ofst = hdr_info[i].dst_mac_addr_offset; + } + + if (ipa_add_hdr(hdr)) { + IPA_UC_OFFLOAD_ERR("fail to add partial headers\n"); + return -EFAULT; + } + + return 0; +} + +static void ipa_uc_offload_ntn_pm_cb(void *p, enum ipa_pm_cb_event event) +{ + /* suspend/resume is not supported */ + IPA_UC_OFFLOAD_DBG("event = %d\n", event); +} + +static int ipa_uc_offload_ntn_register_pm_client( + struct ipa_uc_offload_ctx *ntn_ctx) +{ + int res; + struct ipa_pm_register_params params; + + memset(¶ms, 0, sizeof(params)); + + if (ntn_ctx->proto == IPA_UC_NTN_V2X) + params.name = "ETH_v2x"; + else + params.name = "ETH"; + params.callback = ipa_uc_offload_ntn_pm_cb; + params.user_data = ntn_ctx; + params.group = IPA_PM_GROUP_DEFAULT; + res = ipa_pm_register(¶ms, &ntn_ctx->pm_hdl); + if (res) { + IPA_UC_OFFLOAD_ERR("fail to register with PM %d\n", res); + return res; + } + if (ntn_ctx->proto == IPA_UC_NTN_V2X) + res = ipa_pm_associate_ipa_cons_to_client(ntn_ctx->pm_hdl, + IPA_CLIENT_ETHERNET2_CONS); + else + res = ipa_pm_associate_ipa_cons_to_client(ntn_ctx->pm_hdl, + IPA_CLIENT_ETHERNET_CONS); + if (res) { + IPA_UC_OFFLOAD_ERR("fail to associate. PM (%d) Prot: %d\n", + res, ntn_ctx->proto); + ipa_pm_deregister(ntn_ctx->pm_hdl); + ntn_ctx->pm_hdl = ~0; + return res; + } + + return 0; +} + +static void ipa_uc_offload_ntn_deregister_pm_client( + struct ipa_uc_offload_ctx *ntn_ctx) +{ + ipa_pm_deactivate_sync(ntn_ctx->pm_hdl); + ipa_pm_deregister(ntn_ctx->pm_hdl); +} + +static int ipa_uc_offload_ntn_reg_intf( + struct ipa_uc_offload_intf_params *inp, + struct ipa_uc_offload_out_params *outp, + struct ipa_uc_offload_ctx *ntn_ctx) +{ + struct ipa_ioc_add_hdr *hdr = NULL; + struct ipa_tx_intf tx; + struct ipa_rx_intf rx; + struct ipa_ioc_tx_intf_prop tx_prop[2]; + struct ipa_ioc_rx_intf_prop rx_prop[2]; + int ret = 0; + u32 len; + bool is_vlan_mode; + + IPA_UC_OFFLOAD_DBG("register interface for netdev %s\n", + inp->netdev_name); + ret = ipa_uc_offload_ntn_register_pm_client(ntn_ctx); + if (ret) { + IPA_UC_OFFLOAD_ERR("fail to register PM client\n"); + return -EFAULT; + } + memcpy(ntn_ctx->netdev_name, inp->netdev_name, IPA_RESOURCE_NAME_MAX); + ntn_ctx->hdr_len = inp->hdr_info[0].hdr_len; + ntn_ctx->notify = inp->notify; + ntn_ctx->priv = inp->priv; + + /* add partial header */ + len = sizeof(struct ipa_ioc_add_hdr) + 2 * sizeof(struct ipa_hdr_add); + hdr = kzalloc(len, GFP_KERNEL); + if (hdr == NULL) { + ret = -ENOMEM; + goto fail_alloc; + } + + ret = ipa_is_vlan_mode(IPA_VLAN_IF_ETH, &is_vlan_mode); + if (ret) { + IPA_UC_OFFLOAD_ERR("get vlan mode failed\n"); + goto fail; + } + + if (is_vlan_mode) { + if ((inp->hdr_info[0].hdr_type != IPA_HDR_L2_802_1Q) || + (inp->hdr_info[1].hdr_type != IPA_HDR_L2_802_1Q)) { + IPA_UC_OFFLOAD_ERR( + "hdr_type mismatch in vlan mode\n"); + WARN_ON_RATELIMIT_IPA(1); + ret = -EFAULT; + goto fail; + } + IPA_UC_OFFLOAD_DBG("vlan HEADER type compatible\n"); + + if ((inp->hdr_info[0].hdr_len < + (ETH_HLEN + VLAN_HLEN)) || + (inp->hdr_info[1].hdr_len < + (ETH_HLEN + VLAN_HLEN))) { + IPA_UC_OFFLOAD_ERR( + "hdr_len shorter than vlan len (%u) (%u)\n" + , inp->hdr_info[0].hdr_len + , inp->hdr_info[1].hdr_len); + WARN_ON_RATELIMIT_IPA(1); + ret = -EFAULT; + goto fail; + } + + IPA_UC_OFFLOAD_DBG("vlan HEADER len compatible (%u) (%u)\n", + inp->hdr_info[0].hdr_len, + inp->hdr_info[1].hdr_len); + } + + if (ipa_commit_partial_hdr(hdr, ntn_ctx->netdev_name, inp->hdr_info)) { + IPA_UC_OFFLOAD_ERR("fail to commit partial headers\n"); + ret = -EFAULT; + goto fail; + } + + /* populate tx prop */ + tx.num_props = 2; + tx.prop = tx_prop; + + memset(tx_prop, 0, sizeof(tx_prop)); + tx_prop[0].ip = IPA_IP_v4; + tx_prop[0].dst_pipe = IPA_CLIENT_ETHERNET_CONS; + tx_prop[0].hdr_l2_type = inp->hdr_info[0].hdr_type; + memcpy(tx_prop[0].hdr_name, hdr->hdr[IPA_IP_v4].name, + sizeof(tx_prop[0].hdr_name)); + + tx_prop[1].ip = IPA_IP_v6; + tx_prop[1].dst_pipe = IPA_CLIENT_ETHERNET_CONS; + tx_prop[1].hdr_l2_type = inp->hdr_info[1].hdr_type; + memcpy(tx_prop[1].hdr_name, hdr->hdr[IPA_IP_v6].name, + sizeof(tx_prop[1].hdr_name)); + + /* populate rx prop */ + rx.num_props = 2; + rx.prop = rx_prop; + + memset(rx_prop, 0, sizeof(rx_prop)); + rx_prop[0].ip = IPA_IP_v4; + rx_prop[0].src_pipe = IPA_CLIENT_ETHERNET_PROD; + rx_prop[0].hdr_l2_type = inp->hdr_info[0].hdr_type; + if (inp->is_meta_data_valid) { + rx_prop[0].attrib.attrib_mask |= IPA_FLT_META_DATA; + rx_prop[0].attrib.meta_data = inp->meta_data; + rx_prop[0].attrib.meta_data_mask = inp->meta_data_mask; + } + + rx_prop[1].ip = IPA_IP_v6; + rx_prop[1].src_pipe = IPA_CLIENT_ETHERNET_PROD; + rx_prop[1].hdr_l2_type = inp->hdr_info[1].hdr_type; + if (inp->is_meta_data_valid) { + rx_prop[1].attrib.attrib_mask |= IPA_FLT_META_DATA; + rx_prop[1].attrib.meta_data = inp->meta_data; + rx_prop[1].attrib.meta_data_mask = inp->meta_data_mask; + } + + if (ipa_register_intf(inp->netdev_name, &tx, &rx)) { + IPA_UC_OFFLOAD_ERR("fail to add interface prop\n"); + memset(ntn_ctx, 0, sizeof(*ntn_ctx)); + ret = -EFAULT; + goto fail; + } + + ntn_ctx->partial_hdr_hdl[IPA_IP_v4] = hdr->hdr[IPA_IP_v4].hdr_hdl; + ntn_ctx->partial_hdr_hdl[IPA_IP_v6] = hdr->hdr[IPA_IP_v6].hdr_hdl; + init_completion(&ntn_ctx->ntn_completion); + ntn_ctx->state = IPA_UC_OFFLOAD_STATE_INITIALIZED; + + kfree(hdr); + return ret; + +fail: + kfree(hdr); +fail_alloc: + ipa_uc_offload_ntn_deregister_pm_client(ntn_ctx); + return ret; +} + +int ipa_uc_offload_reg_intf( + struct ipa_uc_offload_intf_params *inp, + struct ipa_uc_offload_out_params *outp) +{ + struct ipa_uc_offload_ctx *ctx; + int ret = 0; + + if (inp == NULL || outp == NULL) { + IPA_UC_OFFLOAD_ERR("invalid params in=%pK out=%pK\n", + inp, outp); + return -EINVAL; + } + + if (inp->proto <= IPA_UC_INVALID || + inp->proto >= IPA_UC_MAX_PROT_SIZE) { + IPA_UC_OFFLOAD_ERR("invalid proto %d\n", inp->proto); + return -EINVAL; + } + + if (!ipa_uc_offload_ctx[inp->proto]) { + ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); + if (ctx == NULL) { + IPA_UC_OFFLOAD_ERR("fail to alloc uc offload ctx\n"); + return -EFAULT; + } + ipa_uc_offload_ctx[inp->proto] = ctx; + ctx->proto = inp->proto; + } else + ctx = ipa_uc_offload_ctx[inp->proto]; + + if (ctx->state != IPA_UC_OFFLOAD_STATE_INVALID) { + IPA_UC_OFFLOAD_ERR("Already Initialized\n"); + return -EINVAL; + } + + /* only register IPA properties for uc_ntn */ + if (ctx->proto == IPA_UC_NTN) { + ret = ipa_uc_offload_ntn_reg_intf(inp, outp, ctx); + if (!ret) + outp->clnt_hndl = IPA_UC_NTN; + } + + /* only register IPA-pm for uc_ntn_v2x */ + if (ctx->proto == IPA_UC_NTN_V2X) { + /* always in vlan mode */ + IPA_UC_OFFLOAD_INFO("v2x hdr_len %d\n", + inp->hdr_info[0].hdr_len); + ctx->hdr_len = inp->hdr_info[0].hdr_len; + ret = ipa_uc_offload_ntn_register_pm_client(ctx); + if (!ret) + outp->clnt_hndl = IPA_UC_NTN_V2X; + else + IPA_UC_OFFLOAD_ERR("fail to create pm resource\n"); + /* set to initialized state */ + ctx->state = IPA_UC_OFFLOAD_STATE_INITIALIZED; + } + + return ret; +} +EXPORT_SYMBOL(ipa_uc_offload_reg_intf); + + +static int ipa_uc_ntn_alloc_conn_smmu_info(struct ipa_ntn_setup_info *dest, + struct ipa_ntn_setup_info *source) +{ + int result; + + IPA_UC_OFFLOAD_DBG("Allocating smmu info\n"); + + memcpy(dest, source, sizeof(struct ipa_ntn_setup_info)); + + dest->data_buff_list = + kcalloc(dest->num_buffers, sizeof(struct ntn_buff_smmu_map), + GFP_KERNEL); + if (dest->data_buff_list == NULL) { + IPA_UC_OFFLOAD_ERR("failed to alloc smmu info\n"); + return -ENOMEM; + } + + memcpy(dest->data_buff_list, source->data_buff_list, + sizeof(struct ntn_buff_smmu_map) * dest->num_buffers); + + result = ipa_smmu_store_sgt(&dest->buff_pool_base_sgt, + source->buff_pool_base_sgt); + if (result) { + kfree(dest->data_buff_list); + dest->data_buff_list = NULL; + return result; + } + + result = ipa_smmu_store_sgt(&dest->ring_base_sgt, + source->ring_base_sgt); + if (result) { + kfree(dest->data_buff_list); + dest->data_buff_list = NULL; + ipa_smmu_free_sgt(&dest->buff_pool_base_sgt); + return result; + } + + return 0; +} + +static void ipa_uc_ntn_free_conn_smmu_info(struct ipa_ntn_setup_info *params) +{ + kfree(params->data_buff_list); + params->data_buff_list = NULL; + ipa_smmu_free_sgt(¶ms->buff_pool_base_sgt); + ipa_smmu_free_sgt(¶ms->ring_base_sgt); +} + +int ipa_uc_ntn_conn_pipes(struct ipa_ntn_conn_in_params *inp, + struct ipa_ntn_conn_out_params *outp, + struct ipa_uc_offload_ctx *ntn_ctx) +{ + int result = 0; + enum ipa_uc_offload_state prev_state; + + if (ntn_ctx->conn.dl.smmu_enabled != ntn_ctx->conn.ul.smmu_enabled) { + IPA_UC_OFFLOAD_ERR("ul and dl smmu enablement do not match\n"); + return -EINVAL; + } + + prev_state = ntn_ctx->state; + if (inp->dl.ring_base_pa % IPA_NTN_DMA_POOL_ALIGNMENT || + inp->dl.buff_pool_base_pa % IPA_NTN_DMA_POOL_ALIGNMENT) { + IPA_UC_OFFLOAD_ERR("alignment failure on TX\n"); + return -EINVAL; + } + if (inp->ul.ring_base_pa % IPA_NTN_DMA_POOL_ALIGNMENT || + inp->ul.buff_pool_base_pa % IPA_NTN_DMA_POOL_ALIGNMENT) { + IPA_UC_OFFLOAD_ERR("alignment failure on RX\n"); + return -EINVAL; + } + + result = ipa_pm_activate_sync(ntn_ctx->pm_hdl); + if (result) { + IPA_UC_OFFLOAD_ERR("fail to activate: %d\n", result); + return result; + } + + ntn_ctx->state = IPA_UC_OFFLOAD_STATE_UP; + result = ipa3_setup_uc_ntn_pipes(inp, ntn_ctx->notify, + ntn_ctx->priv, ntn_ctx->hdr_len, outp); + if (result) { + IPA_UC_OFFLOAD_ERR("fail to setup uc offload pipes: %d\n", + result); + ntn_ctx->state = prev_state; + result = -EFAULT; + goto fail; + } + + if (ntn_ctx->conn.dl.smmu_enabled) { + result = ipa_uc_ntn_alloc_conn_smmu_info(&ntn_ctx->conn.dl, + &inp->dl); + if (result) { + IPA_UC_OFFLOAD_ERR("alloc failure on TX\n"); + goto fail; + } + result = ipa_uc_ntn_alloc_conn_smmu_info(&ntn_ctx->conn.ul, + &inp->ul); + if (result) { + ipa_uc_ntn_free_conn_smmu_info(&ntn_ctx->conn.dl); + IPA_UC_OFFLOAD_ERR("alloc failure on RX\n"); + goto fail; + } + } + +fail: + return result; +} + +int ipa_uc_offload_conn_pipes(struct ipa_uc_offload_conn_in_params *inp, + struct ipa_uc_offload_conn_out_params *outp) +{ + int ret = 0; + struct ipa_uc_offload_ctx *offload_ctx; + + if (!(inp && outp)) { + IPA_UC_OFFLOAD_ERR("bad parm. in=%pK out=%pK\n", inp, outp); + return -EINVAL; + } + + if (inp->clnt_hndl <= IPA_UC_INVALID || + inp->clnt_hndl >= IPA_UC_MAX_PROT_SIZE) { + IPA_UC_OFFLOAD_ERR("invalid client handle %d\n", + inp->clnt_hndl); + return -EINVAL; + } + + offload_ctx = ipa_uc_offload_ctx[inp->clnt_hndl]; + if (!offload_ctx) { + IPA_UC_OFFLOAD_ERR("Invalid ctx %d\n", inp->clnt_hndl); + return -EINVAL; + } + + if (offload_ctx->state != IPA_UC_OFFLOAD_STATE_INITIALIZED) { + IPA_UC_OFFLOAD_ERR("Invalid state %d\n", offload_ctx->state); + return -EPERM; + } + + switch (offload_ctx->proto) { + case IPA_UC_NTN_V2X: + case IPA_UC_NTN: + ret = ipa_uc_ntn_conn_pipes(&inp->u.ntn, &outp->u.ntn, + offload_ctx); + break; + + default: + IPA_UC_OFFLOAD_ERR("Invalid Proto :%d\n", offload_ctx->proto); + ret = -EINVAL; + break; + } + + return ret; +} +EXPORT_SYMBOL(ipa_uc_offload_conn_pipes); + +static int ipa_uc_ntn_disconn_pipes(struct ipa_uc_offload_ctx *ntn_ctx) +{ + int ipa_ep_idx_ul, ipa_ep_idx_dl; + int ret = 0; + + if (ntn_ctx->conn.dl.smmu_enabled != ntn_ctx->conn.ul.smmu_enabled) { + IPA_UC_OFFLOAD_ERR("ul and dl smmu enablement do not match\n"); + return -EINVAL; + } + + ntn_ctx->state = IPA_UC_OFFLOAD_STATE_INITIALIZED; + ret = ipa_pm_deactivate_sync(ntn_ctx->pm_hdl); + if (ret) { + IPA_UC_OFFLOAD_ERR("fail to deactivate res: %d\n", + ret); + return -EFAULT; + } + + if (ntn_ctx->proto == IPA_UC_NTN_V2X) { + ipa_ep_idx_ul = ipa_get_ep_mapping(IPA_CLIENT_ETHERNET2_PROD); + ipa_ep_idx_dl = ipa_get_ep_mapping(IPA_CLIENT_ETHERNET2_CONS); + } else { + ipa_ep_idx_ul = ipa_get_ep_mapping(IPA_CLIENT_ETHERNET_PROD); + ipa_ep_idx_dl = ipa_get_ep_mapping(IPA_CLIENT_ETHERNET_CONS); + } + ret = ipa3_tear_down_uc_offload_pipes(ipa_ep_idx_ul, ipa_ep_idx_dl, + &ntn_ctx->conn); + if (ret) { + IPA_UC_OFFLOAD_ERR("fail to tear down ntn offload pipes, %d\n", + ret); + return -EFAULT; + } + if (ntn_ctx->conn.dl.smmu_enabled) { + ipa_uc_ntn_free_conn_smmu_info(&ntn_ctx->conn.dl); + ipa_uc_ntn_free_conn_smmu_info(&ntn_ctx->conn.ul); + } + + return ret; +} + +int ipa_uc_offload_disconn_pipes(u32 clnt_hdl) +{ + struct ipa_uc_offload_ctx *offload_ctx; + int ret = 0; + + if (clnt_hdl <= IPA_UC_INVALID || + clnt_hdl >= IPA_UC_MAX_PROT_SIZE) { + IPA_UC_OFFLOAD_ERR("Invalid client handle %d\n", clnt_hdl); + return -EINVAL; + } + + offload_ctx = ipa_uc_offload_ctx[clnt_hdl]; + if (!offload_ctx) { + IPA_UC_OFFLOAD_ERR("Invalid client Handle\n"); + return -EINVAL; + } + + if (offload_ctx->state != IPA_UC_OFFLOAD_STATE_UP) { + IPA_UC_OFFLOAD_ERR("Invalid state\n"); + return -EINVAL; + } + + switch (offload_ctx->proto) { + case IPA_UC_NTN_V2X: + case IPA_UC_NTN: + ret = ipa_uc_ntn_disconn_pipes(offload_ctx); + break; + + default: + IPA_UC_OFFLOAD_ERR("Invalid Proto :%d\n", clnt_hdl); + ret = -EINVAL; + break; + } + + return ret; +} +EXPORT_SYMBOL(ipa_uc_offload_disconn_pipes); + +static int ipa_uc_ntn_cleanup(struct ipa_uc_offload_ctx *ntn_ctx) +{ + int len, result = 0; + struct ipa_ioc_del_hdr *hdr; + + ipa_uc_offload_ntn_deregister_pm_client(ntn_ctx); + + len = sizeof(struct ipa_ioc_del_hdr) + 2 * sizeof(struct ipa_hdr_del); + hdr = kzalloc(len, GFP_KERNEL); + if (hdr == NULL) + return -ENOMEM; + + hdr->commit = 1; + hdr->num_hdls = 2; + hdr->hdl[0].hdl = ntn_ctx->partial_hdr_hdl[0]; + hdr->hdl[1].hdl = ntn_ctx->partial_hdr_hdl[1]; + + if (ipa_del_hdr(hdr)) { + IPA_UC_OFFLOAD_ERR("fail to delete partial header\n"); + result = -EFAULT; + goto fail; + } + + if (ipa_deregister_intf(ntn_ctx->netdev_name)) { + IPA_UC_OFFLOAD_ERR("fail to delete interface prop\n"); + result = -EFAULT; + goto fail; + } + +fail: + kfree(hdr); + return result; +} + +int ipa_uc_offload_cleanup(u32 clnt_hdl) +{ + struct ipa_uc_offload_ctx *offload_ctx; + int ret = 0; + + if (clnt_hdl <= IPA_UC_INVALID || + clnt_hdl >= IPA_UC_MAX_PROT_SIZE) { + IPA_UC_OFFLOAD_ERR("Invalid client handle %d\n", clnt_hdl); + return -EINVAL; + } + + offload_ctx = ipa_uc_offload_ctx[clnt_hdl]; + if (!offload_ctx) { + IPA_UC_OFFLOAD_ERR("Invalid client handle %d\n", clnt_hdl); + return -EINVAL; + } + + if (offload_ctx->state != IPA_UC_OFFLOAD_STATE_INITIALIZED) { + IPA_UC_OFFLOAD_ERR("Invalid State %d\n", offload_ctx->state); + return -EINVAL; + } + + switch (offload_ctx->proto) { + case IPA_UC_NTN: + ret = ipa_uc_ntn_cleanup(offload_ctx); + break; + + case IPA_UC_NTN_V2X: + /* only clean-up pm_handle */ + ipa_uc_offload_ntn_deregister_pm_client(offload_ctx); + break; + + default: + IPA_UC_OFFLOAD_ERR("Invalid Proto :%d\n", clnt_hdl); + ret = -EINVAL; + break; + } + + if (!ret) { + kfree(offload_ctx); + offload_ctx = NULL; + ipa_uc_offload_ctx[clnt_hdl] = NULL; + } + + return ret; +} +EXPORT_SYMBOL(ipa_uc_offload_cleanup); + +/** + * ipa_uc_offload_uc_rdyCB() - To register uC ready CB if uC not + * ready + * @inout: [in/out] input/output parameters + * from/to client + * + * Returns: 0 on success, negative on failure + * + */ +int ipa_uc_offload_reg_rdyCB(struct ipa_uc_ready_params *inp) +{ + int ret = 0; + + if (!inp) { + IPA_UC_OFFLOAD_ERR("Invalid input\n"); + return -EINVAL; + } + + if (inp->proto == IPA_UC_NTN || inp->proto == IPA_UC_NTN_V2X) + ret = ipa3_ntn_uc_reg_rdyCB(inp->notify, inp->priv); + + if (ret == -EEXIST) { + inp->is_uC_ready = true; + ret = 0; + } else + inp->is_uC_ready = false; + + return ret; +} +EXPORT_SYMBOL(ipa_uc_offload_reg_rdyCB); + +void ipa_uc_offload_dereg_rdyCB(enum ipa_uc_offload_proto proto) +{ + if (proto == IPA_UC_NTN || proto == IPA_UC_NTN_V2X) + ipa3_ntn_uc_dereg_rdyCB(); +} +EXPORT_SYMBOL(ipa_uc_offload_dereg_rdyCB); + +int ipa_set_perf_profile(struct ipa_perf_profile *profile) +{ + if (!profile) { + IPA_UC_OFFLOAD_ERR("Invalid input\n"); + return -EINVAL; + } + + if (profile->client != IPA_CLIENT_ETHERNET_PROD && + profile->client != IPA_CLIENT_ETHERNET_CONS) { + IPA_UC_OFFLOAD_ERR("not supported\n"); + return -EINVAL; + } + + IPA_UC_OFFLOAD_DBG("setting throughput to %d\n", + profile->max_supported_bw_mbps); + + return ipa_pm_set_throughput( + ipa_uc_offload_ctx[IPA_UC_NTN]->pm_hdl, + profile->max_supported_bw_mbps); +} +EXPORT_SYMBOL(ipa_set_perf_profile); + diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_clients/ipa_usb.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_clients/ipa_usb.c new file mode 100644 index 0000000000..53d9b4f27a --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_clients/ipa_usb.c @@ -0,0 +1,2782 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved. + * + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include "ipa.h" +#include +#include "rndis_ipa.h" +#include "ecm_ipa.h" +#include "ipa_i.h" +#include "ipa_rm_i.h" + +#define IPA_USB_DEV_READY_TIMEOUT_MSEC 10000 + +/* GSI channels weights */ +#define IPA_USB_DL_CHAN_LOW_WEIGHT 0x5 +#define IPA_USB_UL_CHAN_LOW_WEIGHT 0x4 + +#define IPA_USB_MAX_MSG_LEN 4096 + +#define IPA_USB_DRV_NAME "ipa_usb" + +#define IPA_USB_DBG(fmt, args...) \ + do { \ + pr_debug(IPA_USB_DRV_NAME " %s:%d " fmt, \ + __func__, __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf(), \ + IPA_USB_DRV_NAME " %s:%d " fmt, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf_low(), \ + IPA_USB_DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) + +#define IPA_USB_DBG_LOW(fmt, args...) \ + do { \ + pr_debug(IPA_USB_DRV_NAME " %s:%d " fmt, \ + __func__, __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf_low(), \ + IPA_USB_DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) + +#define IPA_USB_ERR(fmt, args...) \ + do { \ + pr_err(IPA_USB_DRV_NAME " %s:%d " fmt, \ + __func__, __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf(), \ + IPA_USB_DRV_NAME " %s:%d " fmt, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf_low(), \ + IPA_USB_DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) + +#define IPA_USB_INFO(fmt, args...) \ + do { \ + pr_info(IPA_USB_DRV_NAME " %s:%d " fmt, \ + __func__, __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf(), \ + IPA_USB_DRV_NAME " %s:%d " fmt, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf_low(), \ + IPA_USB_DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) + +enum ipa_usb_direction { + IPA_USB_DIR_UL, + IPA_USB_DIR_DL, +}; + +struct ipa_usb_xdci_connect_params_internal { + enum ipa_usb_max_usb_packet_size max_pkt_size; + u32 ipa_to_usb_clnt_hdl; + u8 ipa_to_usb_xferrscidx; + bool ipa_to_usb_xferrscidx_valid; + u32 usb_to_ipa_clnt_hdl; + u8 usb_to_ipa_xferrscidx; + bool usb_to_ipa_xferrscidx_valid; + enum ipa_usb_teth_prot teth_prot; + struct ipa_usb_teth_prot_params teth_prot_params; + u32 max_supported_bandwidth_mbps; +}; + +enum ipa3_usb_teth_prot_state { + IPA_USB_TETH_PROT_INITIALIZED, + IPA_USB_TETH_PROT_CONNECTED, + IPA_USB_TETH_PROT_INVALID +}; + +struct ipa3_usb_teth_prot_context { + union { + struct ipa_usb_init_params rndis; + struct ecm_ipa_params ecm; + struct teth_bridge_init_params teth_bridge; + } teth_prot_params; + enum ipa3_usb_teth_prot_state state; + void *user_data; +}; + +struct ipa3_usb_pm_context { + struct ipa_pm_register_params reg_params; + struct work_struct *remote_wakeup_work; + u32 hdl; +}; + +enum ipa3_usb_state { + IPA_USB_INVALID, + IPA_USB_INITIALIZED, + IPA_USB_CONNECTED, + IPA_USB_STOPPED, + IPA_USB_SUSPEND_REQUESTED, + IPA_USB_SUSPENDED, + IPA_USB_SUSPENDED_NO_RWAKEUP, + IPA_USB_RESUME_IN_PROGRESS +}; + +enum ipa3_usb_transport_type { + IPA_USB_TRANSPORT_TETH, + IPA_USB_TRANSPORT_DPL, + IPA_USB_TRANSPORT_TETH_2, + IPA_USB_TRANSPORT_MAX +}; + +/* Get transport type from tethering protocol */ +#define IPA3_USB_GET_TTYPE(__teth_prot) \ + (((__teth_prot) == IPA_USB_DIAG) ? \ + IPA_USB_TRANSPORT_DPL : (((__teth_prot) == IPA_USB_RMNET_CV2X) ? \ + IPA_USB_TRANSPORT_TETH_2 : IPA_USB_TRANSPORT_TETH)) + +/* Does the given transport type is DPL? */ +#define IPA3_USB_IS_TTYPE_DPL(__ttype) \ + ((__ttype) == IPA_USB_TRANSPORT_DPL) + +struct ipa3_usb_teth_prot_conn_params { + u32 usb_to_ipa_clnt_hdl; + u32 ipa_to_usb_clnt_hdl; + struct ipa_usb_teth_prot_params params; +}; + +/** + * Transport type - could be either data tethering or DPL + * Each transport has it's own PM resources and statuses + */ +struct ipa3_usb_transport_type_ctx { + struct ipa3_usb_pm_context pm_ctx; + int (*ipa_usb_notify_cb)(enum ipa_usb_notify_event, void *user_data); + void *user_data; + enum ipa3_usb_state state; + bool rwakeup_pending; + struct ipa_usb_xdci_chan_params ul_ch_params; + struct ipa_usb_xdci_chan_params dl_ch_params; + struct ipa3_usb_teth_prot_conn_params teth_conn_params; +}; + +struct ipa3_usb_smmu_reg_map { + int cnt; + phys_addr_t addr; +}; + +/* + * Relevant for IPA4.5 on sdx55v1 and Kona. + */ +static const bool teth_type_switch_tbl_ipa45 + [IPA_USB_MAX_TETH_PROT_SIZE][IPA_USB_MAX_TETH_PROT_SIZE] = { + [IPA_USB_RNDIS] = {true, false, true, false, false}, + [IPA_USB_ECM] = {false, true, false, false, false}, + [IPA_USB_RMNET] = {true, false, true, false, false}, + [IPA_USB_MBIM] = {true, true, true, true, false}, + [IPA_USB_DIAG] = {false, false, false, false, true}, + }; + +struct ipa3_usb_teth_type_switch { + bool valid; + enum ipa_usb_teth_prot teth; +}; + +struct ipa3_usb_context { + struct ipa3_usb_teth_prot_context + teth_prot_ctx[IPA_USB_MAX_TETH_PROT_SIZE]; + int num_init_prot; /* without dpl */ + struct teth_bridge_init_params teth_bridge_params[IPA_TETH_BRIDGE_MAX]; + struct completion dev_ready_comp; + u32 qmi_req_id; + spinlock_t state_lock; + bool dl_data_pending; + struct workqueue_struct *wq; + struct mutex general_mutex; + struct ipa3_usb_transport_type_ctx + ttype_ctx[IPA_USB_TRANSPORT_MAX]; + struct dentry *dfile_state_info; + struct dentry *dent; + struct ipa3_usb_smmu_reg_map smmu_reg_map; + struct ipa3_usb_teth_type_switch prev_teth; +}; + +enum ipa3_usb_op { + IPA_USB_OP_INIT_TETH_PROT, + IPA_USB_OP_REQUEST_CHANNEL, + IPA_USB_OP_CONNECT, + IPA_USB_OP_DISCONNECT, + IPA_USB_OP_RELEASE_CHANNEL, + IPA_USB_OP_DEINIT_TETH_PROT, + IPA_USB_OP_SUSPEND, + IPA_USB_OP_SUSPEND_NO_RWAKEUP, + IPA_USB_OP_RESUME +}; + +struct ipa3_usb_status_dbg_info { + const char *teth_state; + const char *dpl_state; + int num_init_prot; + const char *inited_prots[IPA_USB_MAX_TETH_PROT_SIZE]; + const char *teth_connected_prot; + const char *dpl_connected_prot; +}; + +static void ipa3_usb_wq_notify_remote_wakeup(struct work_struct *work); +static void ipa3_usb_wq_dpl_notify_remote_wakeup(struct work_struct *work); +static DECLARE_WORK(ipa3_usb_notify_remote_wakeup_work, + ipa3_usb_wq_notify_remote_wakeup); +static DECLARE_WORK(ipa3_usb_dpl_notify_remote_wakeup_work, + ipa3_usb_wq_dpl_notify_remote_wakeup); + +static struct ipa3_usb_context *ipa3_usb_ctx; + +static char *ipa3_usb_op_to_string(enum ipa3_usb_op op) +{ + switch (op) { + case IPA_USB_OP_INIT_TETH_PROT: + return "IPA_USB_OP_INIT_TETH_PROT"; + case IPA_USB_OP_REQUEST_CHANNEL: + return "IPA_USB_OP_REQUEST_CHANNEL"; + case IPA_USB_OP_CONNECT: + return "IPA_USB_OP_CONNECT"; + case IPA_USB_OP_DISCONNECT: + return "IPA_USB_OP_DISCONNECT"; + case IPA_USB_OP_RELEASE_CHANNEL: + return "IPA_USB_OP_RELEASE_CHANNEL"; + case IPA_USB_OP_DEINIT_TETH_PROT: + return "IPA_USB_OP_DEINIT_TETH_PROT"; + case IPA_USB_OP_SUSPEND: + return "IPA_USB_OP_SUSPEND"; + case IPA_USB_OP_SUSPEND_NO_RWAKEUP: + return "IPA_USB_OP_SUSPEND_NO_RWAKEUP"; + case IPA_USB_OP_RESUME: + return "IPA_USB_OP_RESUME"; + } + + return "UNSUPPORTED"; +} + +static char *ipa3_usb_state_to_string(enum ipa3_usb_state state) +{ + switch (state) { + case IPA_USB_INVALID: + return "IPA_USB_INVALID"; + case IPA_USB_INITIALIZED: + return "IPA_USB_INITIALIZED"; + case IPA_USB_CONNECTED: + return "IPA_USB_CONNECTED"; + case IPA_USB_STOPPED: + return "IPA_USB_STOPPED"; + case IPA_USB_SUSPEND_REQUESTED: + return "IPA_USB_SUSPEND_REQUESTED"; + case IPA_USB_SUSPENDED: + return "IPA_USB_SUSPENDED"; + case IPA_USB_SUSPENDED_NO_RWAKEUP: + return "IPA_USB_SUSPENDED_NO_RWAKEUP"; + case IPA_USB_RESUME_IN_PROGRESS: + return "IPA_USB_RESUME_IN_PROGRESS"; + } + + return "UNSUPPORTED"; +} + +static char *ipa3_usb_notify_event_to_string(enum ipa_usb_notify_event event) +{ + switch (event) { + case IPA_USB_DEVICE_READY: + return "IPA_USB_DEVICE_READY"; + case IPA_USB_REMOTE_WAKEUP: + return "IPA_USB_REMOTE_WAKEUP"; + case IPA_USB_SUSPEND_COMPLETED: + return "IPA_USB_SUSPEND_COMPLETED"; + } + + return "UNSUPPORTED"; +} + +static bool ipa3_usb_get_teth_port_state(void) +{ + if (ipa3_usb_ctx == NULL) + return false; + if (ipa3_usb_ctx->ttype_ctx[IPA_USB_TRANSPORT_TETH].state == + IPA_USB_CONNECTED) + return true; + else + return false; +} + +static bool ipa3_usb_set_state(enum ipa3_usb_state new_state, bool err_permit, + enum ipa3_usb_transport_type ttype) +{ + unsigned long flags; + int state_legal = false; + enum ipa3_usb_state state; + bool rwakeup_pending; + + spin_lock_irqsave(&ipa3_usb_ctx->state_lock, flags); + state = ipa3_usb_ctx->ttype_ctx[ttype].state; + rwakeup_pending = ipa3_usb_ctx->ttype_ctx[ttype].rwakeup_pending; + switch (new_state) { + case IPA_USB_INVALID: + if (state == IPA_USB_INITIALIZED) + state_legal = true; + break; + case IPA_USB_INITIALIZED: + if (state == IPA_USB_STOPPED || state == IPA_USB_INVALID || + ((!IPA3_USB_IS_TTYPE_DPL(ttype)) && + (state == IPA_USB_INITIALIZED))) + state_legal = true; + break; + case IPA_USB_CONNECTED: + if (state == IPA_USB_INITIALIZED || + state == IPA_USB_STOPPED || + state == IPA_USB_RESUME_IN_PROGRESS || + state == IPA_USB_SUSPENDED_NO_RWAKEUP || + /* + * In case of failure during suspend request + * handling, state is reverted to connected. + */ + (err_permit && state == IPA_USB_SUSPEND_REQUESTED)) + state_legal = true; + break; + case IPA_USB_STOPPED: + if (state == IPA_USB_CONNECTED || + state == IPA_USB_SUSPENDED || + state == IPA_USB_SUSPENDED_NO_RWAKEUP) + state_legal = true; + break; + case IPA_USB_SUSPEND_REQUESTED: + if (state == IPA_USB_CONNECTED) + state_legal = true; + break; + case IPA_USB_SUSPENDED: + if (state == IPA_USB_SUSPEND_REQUESTED || + /* + * In case of failure during resume, state is reverted + * to original, which could be suspended. Allow it + */ + (err_permit && state == IPA_USB_RESUME_IN_PROGRESS)) { + state_legal = true; + rwakeup_pending = false; + } + break; + case IPA_USB_SUSPENDED_NO_RWAKEUP: + if (state == IPA_USB_CONNECTED) + state_legal = true; + break; + case IPA_USB_RESUME_IN_PROGRESS: + if (state == IPA_USB_SUSPENDED) + state_legal = true; + break; + default: + state_legal = false; + break; + + } + if (state_legal) { + if (state != new_state) { + IPA_USB_DBG("ipa_usb %s state changed %s -> %s\n", + IPA3_USB_IS_TTYPE_DPL(ttype) ? "DPL" : "", + ipa3_usb_state_to_string(state), + ipa3_usb_state_to_string(new_state)); + ipa3_usb_ctx->ttype_ctx[ttype].state = new_state; + ipa3_usb_ctx->ttype_ctx[ttype].rwakeup_pending = + rwakeup_pending; + } + } else { + IPA_USB_ERR("invalid state change %s -> %s\n", + ipa3_usb_state_to_string(state), + ipa3_usb_state_to_string(new_state)); + } + + spin_unlock_irqrestore(&ipa3_usb_ctx->state_lock, flags); + return state_legal; +} + +static bool ipa3_usb_check_legal_op(enum ipa3_usb_op op, + enum ipa3_usb_transport_type ttype) +{ + unsigned long flags; + bool is_legal = false; + enum ipa3_usb_state state; + bool is_dpl; + + if (ipa3_usb_ctx == NULL) { + IPA_USB_ERR("ipa_usb_ctx is not initialized!\n"); + return false; + } + + is_dpl = IPA3_USB_IS_TTYPE_DPL(ttype); + + spin_lock_irqsave(&ipa3_usb_ctx->state_lock, flags); + state = ipa3_usb_ctx->ttype_ctx[ttype].state; + switch (op) { + case IPA_USB_OP_INIT_TETH_PROT: + if (state == IPA_USB_INVALID || + (!is_dpl && state == IPA_USB_INITIALIZED)) + is_legal = true; + break; + case IPA_USB_OP_REQUEST_CHANNEL: + if (state == IPA_USB_INITIALIZED) + is_legal = true; + break; + case IPA_USB_OP_CONNECT: + if (state == IPA_USB_INITIALIZED || state == IPA_USB_STOPPED) + is_legal = true; + break; + case IPA_USB_OP_DISCONNECT: + if (state == IPA_USB_CONNECTED || + state == IPA_USB_SUSPENDED || + state == IPA_USB_SUSPENDED_NO_RWAKEUP) + is_legal = true; + break; + case IPA_USB_OP_RELEASE_CHANNEL: + /* when releasing 1st channel state will be changed already */ + if (state == IPA_USB_STOPPED || + (!is_dpl && state == IPA_USB_INITIALIZED)) + is_legal = true; + break; + case IPA_USB_OP_DEINIT_TETH_PROT: + /* + * For data tethering we should allow deinit an inited protocol + * always. E.g. rmnet is inited and rndis is connected. + * USB can deinit rmnet first and then disconnect rndis + * on cable disconnect. + */ + if (!is_dpl || state == IPA_USB_INITIALIZED) + is_legal = true; + break; + case IPA_USB_OP_SUSPEND: + if (state == IPA_USB_CONNECTED) + is_legal = true; + break; + case IPA_USB_OP_SUSPEND_NO_RWAKEUP: + if (state == IPA_USB_CONNECTED) + is_legal = true; + break; + case IPA_USB_OP_RESUME: + if (state == IPA_USB_SUSPENDED || + state == IPA_USB_SUSPENDED_NO_RWAKEUP) + is_legal = true; + break; + default: + is_legal = false; + break; + } + + if (!is_legal) { + IPA_USB_ERR("Illegal %s operation: state=%s operation=%s\n", + is_dpl ? "DPL" : "", + ipa3_usb_state_to_string(state), + ipa3_usb_op_to_string(op)); + } + + spin_unlock_irqrestore(&ipa3_usb_ctx->state_lock, flags); + return is_legal; +} + +static void ipa3_usb_notify_do(enum ipa3_usb_transport_type ttype, + enum ipa_usb_notify_event event) +{ + int (*cb)(enum ipa_usb_notify_event, void *user_data); + void *user_data; + int res; + + IPA_USB_DBG("Trying to notify USB with %s\n", + ipa3_usb_notify_event_to_string(event)); + + cb = ipa3_usb_ctx->ttype_ctx[ttype].ipa_usb_notify_cb; + user_data = ipa3_usb_ctx->ttype_ctx[ttype].user_data; + + if (cb) { + res = cb(event, user_data); + IPA_USB_DBG("Notified USB with %s. is_dpl=%d result=%d\n", + ipa3_usb_notify_event_to_string(event), + IPA3_USB_IS_TTYPE_DPL(ttype), res); + } +} + +/* + * This call-back is called from ECM or RNDIS drivers. + * Both drivers are data tethering drivers and not DPL + */ +static void ipa3_usb_device_ready_notify_cb(void) +{ + IPA_USB_DBG_LOW("entry\n"); + ipa3_usb_notify_do(IPA_USB_TRANSPORT_TETH, + IPA_USB_DEVICE_READY); + IPA_USB_DBG_LOW("exit\n"); +} + +static void ipa3_usb_wq_notify_remote_wakeup(struct work_struct *work) +{ + bool rwakeup_pending; + unsigned long flags; + enum ipa3_usb_transport_type ttype = + IPA_USB_TRANSPORT_TETH; + + + spin_lock_irqsave(&ipa3_usb_ctx->state_lock, flags); + rwakeup_pending = + ipa3_usb_ctx->ttype_ctx[ttype].rwakeup_pending; + if (!rwakeup_pending) { + rwakeup_pending = true; + ipa3_usb_notify_do(ttype, + IPA_USB_REMOTE_WAKEUP); + } + ipa3_usb_ctx->ttype_ctx[ttype].rwakeup_pending = + rwakeup_pending; + spin_unlock_irqrestore(&ipa3_usb_ctx->state_lock, flags); +} + +static void ipa3_usb_wq_dpl_notify_remote_wakeup(struct work_struct *work) +{ + bool rwakeup_pending; + unsigned long flags; + enum ipa3_usb_transport_type ttype = + IPA_USB_TRANSPORT_DPL; + + spin_lock_irqsave(&ipa3_usb_ctx->state_lock, flags); + rwakeup_pending = + ipa3_usb_ctx->ttype_ctx[ttype].rwakeup_pending; + if (!rwakeup_pending) { + rwakeup_pending = true; + ipa3_usb_notify_do(ttype, + IPA_USB_REMOTE_WAKEUP); + } + ipa3_usb_ctx->ttype_ctx[ttype].rwakeup_pending = + rwakeup_pending; + spin_unlock_irqrestore(&ipa3_usb_ctx->state_lock, flags); +} + + +static void ipa3_usb_pm_cb(void *p, enum ipa_pm_cb_event event) +{ + struct ipa3_usb_transport_type_ctx *ttype_ctx = + (struct ipa3_usb_transport_type_ctx *)p; + unsigned long flags; + + IPA_USB_DBG_LOW("entry\n"); + + if (event != IPA_PM_REQUEST_WAKEUP) { + IPA_USB_ERR("Unexpected event %d\n", event); + WARN_ON(1); + return; + } + + spin_lock_irqsave(&ipa3_usb_ctx->state_lock, flags); + IPA_USB_DBG("state is %s\n", + ipa3_usb_state_to_string(ttype_ctx->state)); + if (ttype_ctx->state == IPA_USB_SUSPENDED) + queue_work(ipa3_usb_ctx->wq, + ttype_ctx->pm_ctx.remote_wakeup_work); + spin_unlock_irqrestore(&ipa3_usb_ctx->state_lock, flags); + IPA_USB_DBG_LOW("exit\n"); +} + +static char *ipa3_usb_teth_prot_to_string(enum ipa_usb_teth_prot teth_prot) +{ + switch (teth_prot) { + case IPA_USB_RNDIS: + return "rndis_ipa"; + case IPA_USB_ECM: + return "ecm_ipa"; + case IPA_USB_RMNET: + case IPA_USB_MBIM: + return "teth_bridge"; + case IPA_USB_RMNET_CV2X: + return "teth_bridge_cv2x"; + case IPA_USB_DIAG: + return "dpl"; + default: + break; + } + + return "unsupported"; +} + +static char *ipa3_usb_teth_bridge_prot_to_string( + enum ipa_usb_teth_prot teth_prot) +{ + switch (teth_prot) { + case IPA_USB_RMNET: + return "rmnet"; + case IPA_USB_RMNET_CV2X: + return "rmnet_cv2x"; + case IPA_USB_MBIM: + return "mbim"; + default: + break; + } + + return "unsupported"; +} + +static int ipa3_usb_init_teth_bridge(enum ipa_usb_teth_prot teth_prot) +{ + int result; + + if (teth_prot == IPA_USB_RMNET_CV2X) + result = + ipa3_teth_bridge_init( + &ipa3_usb_ctx->teth_bridge_params[IPA_TETH_BRIDGE_2]); + else + result = + ipa3_teth_bridge_init( + &ipa3_usb_ctx->teth_bridge_params[IPA_TETH_BRIDGE_1]); + if (result) { + IPA_USB_ERR("Failed to initialize teth_bridge\n"); + return result; + } + + return 0; +} + +static int ipa3_usb_register_pm(enum ipa3_usb_transport_type ttype) +{ + struct ipa3_usb_transport_type_ctx *ttype_ctx = + &ipa3_usb_ctx->ttype_ctx[ttype]; + int result; + enum ipa_client_type consumer; + + /* + * One PM resource for teth1, + * One PM resource for teth2 (CV2X), + * One for DPL, + */ + + if (!IPA3_USB_IS_TTYPE_DPL(ttype) && (ipa3_usb_ctx->num_init_prot > 0) + && (ttype != IPA_USB_TRANSPORT_TETH_2)) + return 0; + + memset(&ttype_ctx->pm_ctx.reg_params, 0, + sizeof(ttype_ctx->pm_ctx.reg_params)); + ttype_ctx->pm_ctx.reg_params.name = + (ttype == IPA_USB_TRANSPORT_DPL) ? + "USB DPL" : + (ttype == IPA_USB_TRANSPORT_TETH_2) ? + "USB2" : "USB"; + + ttype_ctx->pm_ctx.reg_params.callback = ipa3_usb_pm_cb; + ttype_ctx->pm_ctx.reg_params.user_data = ttype_ctx; + ttype_ctx->pm_ctx.reg_params.group = IPA_PM_GROUP_DEFAULT; + + result = ipa_pm_register(&ttype_ctx->pm_ctx.reg_params, + &ttype_ctx->pm_ctx.hdl); + if (result) { + IPA_USB_ERR("fail to register with PM %d\n", result); + goto fail_pm_reg; + } + + consumer = (ttype == IPA_USB_TRANSPORT_DPL) ? + IPA_CLIENT_USB_DPL_CONS : + (ttype == IPA_USB_TRANSPORT_TETH_2) ? + IPA_CLIENT_USB2_CONS : IPA_CLIENT_USB_CONS; + result = ipa_pm_associate_ipa_cons_to_client(ttype_ctx->pm_ctx.hdl, + consumer); + if (result) { + IPA_USB_ERR("fail to associate cons with PM %d\n", result); + goto fail_pm_cons; + } + + return 0; + +fail_pm_cons: + ipa_pm_deregister(ttype_ctx->pm_ctx.hdl); +fail_pm_reg: + memset(&ttype_ctx->pm_ctx.reg_params, 0, + sizeof(ttype_ctx->pm_ctx.reg_params)); + return result; +} + +static int ipa3_usb_deregister_pm(enum ipa3_usb_transport_type ttype) +{ + struct ipa3_usb_pm_context *pm_ctx = + &ipa3_usb_ctx->ttype_ctx[ttype].pm_ctx; + int result; + + result = ipa_pm_deregister(pm_ctx->hdl); + if (result) + return result; + + memset(&pm_ctx->reg_params, 0, sizeof(pm_ctx->reg_params)); + return 0; +} + +static bool ipa3_usb_is_teth_switch_valid(enum ipa_usb_teth_prot new_teth) +{ + enum ipa_usb_teth_prot old_teth; + u32 ipa_r_rev; + + IPA_USB_DBG("Start new_teth=%s\n", + ipa3_usb_teth_prot_to_string(new_teth)); + + if (IPA3_USB_IS_TTYPE_DPL(IPA3_USB_GET_TTYPE(new_teth))) + return true; + + if (ipa_get_hw_type() != IPA_HW_v4_5) + return true; + + ipa_r_rev = ipa3_get_r_rev_version(); + IPA_USB_DBG("ipa_r_rev=%u\n", ipa_r_rev); + + /* issue relevant for IPA4.5v1 */ + if (ipa_r_rev != 10 && ipa_r_rev != 13) + return true; + + if (ipa3_usb_ctx == NULL) { + IPA_USB_ERR("Invalid context"); + return false; + } + + if (new_teth < 0 || new_teth >= IPA_USB_MAX_TETH_PROT_SIZE) { + IPA_USB_ERR("Invalid new_teth %d\n", new_teth); + return false; + } + + if (!ipa3_usb_ctx->prev_teth.valid) { + ipa3_usb_ctx->prev_teth.teth = new_teth; + ipa3_usb_ctx->prev_teth.valid = true; + return true; + } + + old_teth = ipa3_usb_ctx->prev_teth.teth; + if (teth_type_switch_tbl_ipa45[old_teth][new_teth]) { + ipa3_usb_ctx->prev_teth.teth = new_teth; + return true; + } + + IPA_USB_DBG("Invalid teth switch %s -> %s\n", + ipa3_usb_teth_prot_to_string(old_teth), + ipa3_usb_teth_prot_to_string(new_teth)); + return false; +} + + +static int ipa_usb_set_lock_unlock(bool is_lock) +{ + IPA_USB_DBG("entry\n"); + if (is_lock) + mutex_lock(&ipa3_usb_ctx->general_mutex); + else + mutex_unlock(&ipa3_usb_ctx->general_mutex); + IPA_USB_DBG("exit\n"); + + return 0; +} + +int ipa_usb_init_teth_prot(enum ipa_usb_teth_prot teth_prot, + struct ipa_usb_teth_params *teth_params, + int (*ipa_usb_notify_cb)(enum ipa_usb_notify_event, + void *), + void *user_data) +{ + int result = -EFAULT; + enum ipa3_usb_transport_type ttype; + struct ipa3_usb_teth_prot_context *teth_prot_ptr; + + mutex_lock(&ipa3_usb_ctx->general_mutex); + IPA_USB_DBG_LOW("entry\n"); + if (teth_prot < 0 || teth_prot >= IPA_USB_MAX_TETH_PROT_SIZE || + ((teth_prot == IPA_USB_RNDIS || teth_prot == IPA_USB_ECM) && + teth_params == NULL) || ipa_usb_notify_cb == NULL || + user_data == NULL) { + IPA_USB_ERR("bad parameters\n"); + result = -EINVAL; + goto bad_params; + } + + ttype = IPA3_USB_GET_TTYPE(teth_prot); + + if (!ipa3_usb_check_legal_op(IPA_USB_OP_INIT_TETH_PROT, ttype)) { + IPA_USB_ERR("Illegal operation\n"); + result = -EPERM; + goto bad_params; + } + + /* Register with IPA PM */ + teth_prot_ptr = &ipa3_usb_ctx->teth_prot_ctx[teth_prot]; + result = ipa3_usb_register_pm(ttype); + if (result) { + IPA_USB_ERR("Failed registering IPA PM\n"); + goto bad_params; + } + + if (!ipa3_usb_ctx->ttype_ctx[ttype].ipa_usb_notify_cb) { + ipa3_usb_ctx->ttype_ctx[ttype].ipa_usb_notify_cb = + ipa_usb_notify_cb; + } else if (!IPA3_USB_IS_TTYPE_DPL(ttype)) { + if (ipa3_usb_ctx->ttype_ctx[ttype].ipa_usb_notify_cb != + ipa_usb_notify_cb) { + IPA_USB_ERR("Got different notify_cb\n"); + result = -EINVAL; + goto bad_params; + } + } else { + IPA_USB_ERR("Already has dpl_notify_cb\n"); + result = -EINVAL; + goto bad_params; + } + + /* Initialize tethering protocol */ + switch (teth_prot) { + case IPA_USB_RNDIS: + case IPA_USB_ECM: + if (ipa3_usb_ctx->teth_prot_ctx[teth_prot].state != + IPA_USB_TETH_PROT_INVALID) { + IPA_USB_DBG("%s already initialized\n", + ipa3_usb_teth_prot_to_string(teth_prot)); + result = -EPERM; + goto bad_params; + } + ipa3_usb_ctx->teth_prot_ctx[teth_prot].user_data = user_data; + if (teth_prot == IPA_USB_RNDIS) { + struct ipa_usb_init_params *rndis_ptr = + &teth_prot_ptr->teth_prot_params.rndis; + + rndis_ptr->device_ready_notify = + ipa3_usb_device_ready_notify_cb; + memcpy(rndis_ptr->host_ethaddr, + teth_params->host_ethaddr, + sizeof(teth_params->host_ethaddr)); + memcpy(rndis_ptr->device_ethaddr, + teth_params->device_ethaddr, + sizeof(teth_params->device_ethaddr)); + + result = rndis_ipa_init(rndis_ptr); + if (result) { + IPA_USB_ERR("Failed to initialize %s\n", + ipa3_usb_teth_prot_to_string( + teth_prot)); + goto teth_prot_init_fail; + } + } else { + struct ecm_ipa_params *ecm_ptr = + &teth_prot_ptr->teth_prot_params.ecm; + + ecm_ptr->device_ready_notify = + ipa3_usb_device_ready_notify_cb; + memcpy(ecm_ptr->host_ethaddr, + teth_params->host_ethaddr, + sizeof(teth_params->host_ethaddr)); + memcpy(ecm_ptr->device_ethaddr, + teth_params->device_ethaddr, + sizeof(teth_params->device_ethaddr)); + + result = ecm_ipa_init(ecm_ptr); + if (result) { + IPA_USB_ERR("Failed to initialize %s\n", + ipa3_usb_teth_prot_to_string( + teth_prot)); + goto teth_prot_init_fail; + } + } + teth_prot_ptr->state = + IPA_USB_TETH_PROT_INITIALIZED; + ipa3_usb_ctx->num_init_prot++; + IPA_USB_DBG("initialized %s\n", + ipa3_usb_teth_prot_to_string(teth_prot)); + break; + case IPA_USB_RMNET: + case IPA_USB_MBIM: + if (ipa3_usb_ctx->teth_prot_ctx[teth_prot].state != + IPA_USB_TETH_PROT_INVALID) { + IPA_USB_DBG("%s already initialized\n", + ipa3_usb_teth_prot_to_string(teth_prot)); + result = -EPERM; + goto bad_params; + } + ipa3_usb_ctx->teth_prot_ctx[teth_prot].user_data = user_data; + + result = ipa3_usb_init_teth_bridge(teth_prot); + if (result) + goto teth_prot_init_fail; + + ipa3_usb_ctx->teth_prot_ctx[teth_prot].state = + IPA_USB_TETH_PROT_INITIALIZED; + ipa3_usb_ctx->num_init_prot++; + IPA_USB_DBG("initialized %s %s\n", + ipa3_usb_teth_prot_to_string(teth_prot), + ipa3_usb_teth_bridge_prot_to_string(teth_prot)); + /* + * Register for xdci lock/unlock callback with ipa core driver. + * As per use case, only register for IPA_CONS end point now. + * If needed we can include the same for IPA_PROD ep. + * For IPA_USB_DIAG/DPL config there will not be any UL ep. + */ + ipa3_register_client_callback(&ipa_usb_set_lock_unlock, + &ipa3_usb_get_teth_port_state, IPA_CLIENT_USB_PROD); + break; + case IPA_USB_RMNET_CV2X: + if (ipa3_usb_ctx->teth_prot_ctx[teth_prot].state != + IPA_USB_TETH_PROT_INVALID) { + IPA_USB_DBG("%s already initialized\n", + ipa3_usb_teth_prot_to_string(teth_prot)); + result = -EPERM; + goto bad_params; + } + ipa3_usb_ctx->teth_prot_ctx[teth_prot].user_data = user_data; + + result = ipa3_usb_init_teth_bridge(teth_prot); + if (result) + goto teth_prot_init_fail; + + ipa3_usb_ctx->teth_prot_ctx[teth_prot].state = + IPA_USB_TETH_PROT_INITIALIZED; + IPA_USB_DBG("initialized %s %s\n", + ipa3_usb_teth_prot_to_string(teth_prot), + ipa3_usb_teth_bridge_prot_to_string(teth_prot)); + break; + case IPA_USB_DIAG: + if (ipa3_usb_ctx->teth_prot_ctx[teth_prot].state != + IPA_USB_TETH_PROT_INVALID) { + IPA_USB_DBG("DPL already initialized\n"); + result = -EPERM; + goto bad_params; + } + ipa3_usb_ctx->teth_prot_ctx[teth_prot].user_data = user_data; + ipa3_usb_ctx->teth_prot_ctx[teth_prot].state = + IPA_USB_TETH_PROT_INITIALIZED; + IPA_USB_DBG("initialized DPL\n"); + break; + default: + IPA_USB_ERR("unexpected tethering protocol\n"); + result = -EINVAL; + goto bad_params; + } + + if (!ipa3_usb_set_state(IPA_USB_INITIALIZED, false, ttype)) + IPA_USB_ERR("failed to change state to initialized\n"); + + IPA_USB_DBG_LOW("exit\n"); + mutex_unlock(&ipa3_usb_ctx->general_mutex); + return 0; + +teth_prot_init_fail: + if ((IPA3_USB_IS_TTYPE_DPL(ttype)) + || (ipa3_usb_ctx->num_init_prot == 0) + || (teth_prot == IPA_USB_RMNET_CV2X)) { + ipa3_usb_deregister_pm(ttype); + } +bad_params: + mutex_unlock(&ipa3_usb_ctx->general_mutex); + return result; +} +EXPORT_SYMBOL(ipa_usb_init_teth_prot); + +static void ipa3_usb_gsi_evt_err_cb(struct gsi_evt_err_notify *notify) +{ + IPA_USB_DBG_LOW("entry\n"); + if (!notify) + return; + IPA_USB_ERR("Received event error %d, description: %d\n", + notify->evt_id, notify->err_desc); + IPA_USB_DBG_LOW("exit\n"); +} + +static void ipa3_usb_gsi_chan_err_cb(struct gsi_chan_err_notify *notify) +{ + IPA_USB_DBG_LOW("entry\n"); + if (!notify) + return; + IPA_USB_ERR("Received channel error %d, description: %d\n", + notify->evt_id, notify->err_desc); + IPA_USB_DBG_LOW("exit\n"); +} + +static bool ipa3_usb_check_chan_params(struct ipa_usb_xdci_chan_params *params) +{ + IPA_USB_DBG_LOW("gevntcount_low_addr = %x\n", + params->gevntcount_low_addr); + IPA_USB_DBG_LOW("gevntcount_hi_addr = %x\n", + params->gevntcount_hi_addr); + IPA_USB_DBG_LOW("dir = %d\n", params->dir); + IPA_USB_DBG_LOW("xfer_ring_len = %d\n", params->xfer_ring_len); + IPA_USB_DBG_LOW("last_trb_addr_iova = %x\n", + params->xfer_scratch.last_trb_addr_iova); + IPA_USB_DBG_LOW("const_buffer_size = %d\n", + params->xfer_scratch.const_buffer_size); + IPA_USB_DBG_LOW("depcmd_low_addr = %x\n", + params->xfer_scratch.depcmd_low_addr); + IPA_USB_DBG_LOW("depcmd_hi_addr = %x\n", + params->xfer_scratch.depcmd_hi_addr); + + if (params->teth_prot < 0 || + params->teth_prot >= IPA_USB_MAX_TETH_PROT_SIZE || + params->xfer_ring_len % GSI_CHAN_RE_SIZE_16B || + params->xfer_scratch.const_buffer_size < 1 || + params->xfer_scratch.const_buffer_size > 31) { + IPA_USB_ERR("Invalid params\n"); + return false; + } + switch (params->teth_prot) { + case IPA_USB_DIAG: + fallthrough; + case IPA_USB_RNDIS: + fallthrough; + case IPA_USB_ECM: + if (ipa3_usb_ctx->teth_prot_ctx[params->teth_prot].state == + IPA_USB_TETH_PROT_INVALID) { + IPA_USB_ERR("%s is not initialized\n", + ipa3_usb_teth_prot_to_string( + params->teth_prot)); + return false; + } + break; + case IPA_USB_RMNET: + fallthrough; + case IPA_USB_RMNET_CV2X: + fallthrough; + case IPA_USB_MBIM: + if (ipa3_usb_ctx->teth_prot_ctx[params->teth_prot].state == + IPA_USB_TETH_PROT_INVALID) { + IPA_USB_ERR("%s is not initialized\n", + ipa3_usb_teth_bridge_prot_to_string( + params->teth_prot)); + return false; + } + break; + default: + IPA_USB_ERR("Unknown tethering protocol (%d)\n", + params->teth_prot); + return false; + } + return true; +} + +static int ipa3_usb_smmu_map_xdci_channel( + struct ipa_usb_xdci_chan_params *params, bool map) +{ + int result; + u32 gevntcount_r = rounddown(params->gevntcount_low_addr, PAGE_SIZE); + u32 xfer_scratch_r = + rounddown(params->xfer_scratch.depcmd_low_addr, PAGE_SIZE); + + if (gevntcount_r != xfer_scratch_r) { + IPA_USB_ERR("No support more than 1 page map for USB regs\n"); + WARN_ON(1); + return -EINVAL; + } + + if (map) { + if (ipa3_usb_ctx->smmu_reg_map.cnt == 0) { + ipa3_usb_ctx->smmu_reg_map.addr = gevntcount_r; + result = ipa3_smmu_map_peer_reg( + ipa3_usb_ctx->smmu_reg_map.addr, true, + IPA_SMMU_CB_AP); + if (result) { + IPA_USB_ERR("failed to map USB regs %d\n", + result); + return result; + } + } else { + if (gevntcount_r != ipa3_usb_ctx->smmu_reg_map.addr) { + IPA_USB_ERR( + "No support for map different reg\n"); + return -EINVAL; + } + } + ipa3_usb_ctx->smmu_reg_map.cnt++; + } else { + if (gevntcount_r != ipa3_usb_ctx->smmu_reg_map.addr) { + IPA_USB_ERR( + "No support for map different reg\n"); + return -EINVAL; + } + + if (ipa3_usb_ctx->smmu_reg_map.cnt == 1) { + result = ipa3_smmu_map_peer_reg( + ipa3_usb_ctx->smmu_reg_map.addr, false, + IPA_SMMU_CB_AP); + if (result) { + IPA_USB_ERR("failed to unmap USB regs %d\n", + result); + return result; + } + } + ipa3_usb_ctx->smmu_reg_map.cnt--; + } + + result = ipa3_smmu_map_peer_buff(params->xfer_ring_base_addr_iova, + params->xfer_ring_len, map, params->sgt_xfer_rings, + IPA_SMMU_CB_AP); + if (result) { + IPA_USB_ERR("failed to map Xfer ring %d\n", result); + return result; + } + + result = ipa3_smmu_map_peer_buff(params->data_buff_base_addr_iova, + params->data_buff_base_len, map, params->sgt_data_buff, + IPA_SMMU_CB_AP); + if (result) { + IPA_USB_ERR("failed to map TRBs buff %d\n", result); + return result; + } + + return 0; +} + +static int ipa3_usb_request_xdci_channel( + struct ipa_usb_xdci_chan_params *params, + enum ipa_usb_direction dir, + struct ipa_req_chan_out_params *out_params) +{ + int result = -EFAULT; + struct ipa_request_gsi_channel_params chan_params; + enum ipa3_usb_transport_type ttype; + enum ipa_usb_teth_prot teth_prot; + struct ipa_usb_init_params *rndis_ptr; + struct ecm_ipa_params *ecm_ptr; + struct ipa_usb_xdci_chan_params *xdci_ch_params; + + IPA_USB_DBG_LOW("entry\n"); + if (params == NULL || out_params == NULL || + !ipa3_usb_check_chan_params(params)) { + IPA_USB_ERR("bad parameters\n"); + return -EINVAL; + } + + ttype = IPA3_USB_GET_TTYPE(params->teth_prot); + teth_prot = params->teth_prot; + + if (!ipa3_usb_check_legal_op(IPA_USB_OP_REQUEST_CHANNEL, ttype)) { + IPA_USB_ERR("Illegal operation\n"); + return -EPERM; + } + + rndis_ptr = + &ipa3_usb_ctx->teth_prot_ctx[teth_prot].teth_prot_params.rndis; + ecm_ptr = + &ipa3_usb_ctx->teth_prot_ctx[teth_prot].teth_prot_params.ecm; + + memset(&chan_params, 0, sizeof(struct ipa_request_gsi_channel_params)); + chan_params.ipa_ep_cfg.mode.mode = IPA_BASIC; + if (params->dir == GSI_CHAN_DIR_TO_GSI) + chan_params.client = IPA_CLIENT_USB_PROD; + else + chan_params.client = (params->teth_prot == IPA_USB_DIAG) ? + IPA_CLIENT_USB_DPL_CONS : IPA_CLIENT_USB_CONS; + switch (params->teth_prot) { + case IPA_USB_RNDIS: + chan_params.priv = rndis_ptr->private; + if (params->dir == GSI_CHAN_DIR_FROM_GSI) + chan_params.notify = rndis_ptr->ipa_tx_notify; + else + chan_params.notify = rndis_ptr->ipa_rx_notify; + chan_params.skip_ep_cfg = rndis_ptr->skip_ep_cfg; + break; + case IPA_USB_ECM: + chan_params.priv = ecm_ptr->private; + if (params->dir == GSI_CHAN_DIR_FROM_GSI) + chan_params.notify = ecm_ptr->ecm_ipa_tx_dp_notify; + else + chan_params.notify = ecm_ptr->ecm_ipa_rx_dp_notify; + chan_params.skip_ep_cfg = ecm_ptr->skip_ep_cfg; + break; + case IPA_USB_RMNET: + case IPA_USB_MBIM: + chan_params.priv = + ipa3_usb_ctx->teth_bridge_params[IPA_TETH_BRIDGE_1].private_data; + chan_params.notify = + ipa3_usb_ctx->teth_bridge_params[IPA_TETH_BRIDGE_1].usb_notify_cb; + chan_params.skip_ep_cfg = + ipa3_usb_ctx->teth_bridge_params[IPA_TETH_BRIDGE_1].skip_ep_cfg; + break; + case IPA_USB_RMNET_CV2X: + chan_params.priv = + ipa3_usb_ctx->teth_bridge_params[IPA_TETH_BRIDGE_2].private_data; + chan_params.notify = + ipa3_usb_ctx->teth_bridge_params[IPA_TETH_BRIDGE_2].usb_notify_cb; + chan_params.skip_ep_cfg = + ipa3_usb_ctx->teth_bridge_params[IPA_TETH_BRIDGE_2].skip_ep_cfg; + break; + case IPA_USB_DIAG: + chan_params.priv = NULL; + chan_params.notify = NULL; + chan_params.skip_ep_cfg = true; + break; + default: + break; + } + + result = ipa3_usb_smmu_map_xdci_channel(params, true); + if (result) { + IPA_USB_ERR("failed to smmu map %d\n", result); + return result; + } + + /* store channel params for SMMU unmap */ + if (dir == IPA_USB_DIR_UL) + xdci_ch_params = &ipa3_usb_ctx->ttype_ctx[ttype].ul_ch_params; + else + xdci_ch_params = &ipa3_usb_ctx->ttype_ctx[ttype].dl_ch_params; + + *xdci_ch_params = *params; + result = ipa_smmu_store_sgt( + &xdci_ch_params->sgt_xfer_rings, + params->sgt_xfer_rings); + if (result) + return result; + + result = ipa_smmu_store_sgt( + &xdci_ch_params->sgt_data_buff, + params->sgt_data_buff); + if (result) { + ipa_smmu_free_sgt(&xdci_ch_params->sgt_xfer_rings); + return result; + } + chan_params.keep_ipa_awake = params->keep_ipa_awake; + chan_params.evt_ring_params.intf = GSI_EVT_CHTYPE_XDCI_EV; + chan_params.evt_ring_params.intr = GSI_INTR_MSI; + chan_params.evt_ring_params.re_size = GSI_EVT_RING_RE_SIZE_16B; + chan_params.evt_ring_params.ring_len = params->xfer_ring_len - + chan_params.evt_ring_params.re_size; + chan_params.evt_ring_params.ring_base_addr = + params->xfer_ring_base_addr_iova; + chan_params.evt_ring_params.ring_base_vaddr = NULL; + chan_params.evt_ring_params.int_modt = 0; + chan_params.evt_ring_params.int_modt = 0; + chan_params.evt_ring_params.intvec = 0; + chan_params.evt_ring_params.msi_addr = + ((uint64_t)params->xfer_scratch.depcmd_low_addr) + + (((uint64_t)params->xfer_scratch.depcmd_hi_addr) << 32); + chan_params.evt_ring_params.rp_update_addr = 0; + chan_params.evt_ring_params.exclusive = true; + chan_params.evt_ring_params.err_cb = ipa3_usb_gsi_evt_err_cb; + chan_params.evt_ring_params.user_data = NULL; + chan_params.evt_scratch.xdci.gevntcount_low_addr = + params->gevntcount_low_addr; + chan_params.evt_scratch.xdci.gevntcount_hi_addr = + params->gevntcount_hi_addr; + chan_params.chan_params.prot = GSI_CHAN_PROT_XDCI; + chan_params.chan_params.dir = (enum gsi_chan_dir)(params->dir); + /* chan_id is set in ipa3_request_gsi_channel() */ + chan_params.chan_params.re_size = GSI_CHAN_RE_SIZE_16B; + chan_params.chan_params.ring_len = params->xfer_ring_len; + chan_params.chan_params.ring_base_addr = + params->xfer_ring_base_addr_iova; + chan_params.chan_params.ring_base_vaddr = NULL; + if (ipa_get_hw_type() >= IPA_HW_v4_0) + chan_params.chan_params.use_db_eng = GSI_CHAN_DIRECT_MODE; + else + chan_params.chan_params.use_db_eng = GSI_CHAN_DB_MODE; + chan_params.chan_params.db_in_bytes = 1; + chan_params.chan_params.max_prefetch = GSI_ONE_PREFETCH_SEG; + if (params->dir == GSI_CHAN_DIR_FROM_GSI) + chan_params.chan_params.low_weight = + IPA_USB_DL_CHAN_LOW_WEIGHT; + else + chan_params.chan_params.low_weight = + IPA_USB_UL_CHAN_LOW_WEIGHT; + chan_params.chan_params.xfer_cb = NULL; + chan_params.chan_params.err_cb = ipa3_usb_gsi_chan_err_cb; + chan_params.chan_params.chan_user_data = NULL; + chan_params.chan_scratch.xdci.last_trb_addr = + params->xfer_scratch.last_trb_addr_iova; + /* xferrscidx will be updated later */ + chan_params.chan_scratch.xdci.xferrscidx = 0; + chan_params.chan_scratch.xdci.const_buffer_size = + params->xfer_scratch.const_buffer_size; + chan_params.chan_scratch.xdci.depcmd_low_addr = + params->xfer_scratch.depcmd_low_addr; + chan_params.chan_scratch.xdci.depcmd_hi_addr = + params->xfer_scratch.depcmd_hi_addr; + + /* + * Update scratch for MCS smart prefetch: + * Starting IPA4.5, smart prefetch implemented by H/W. + * At IPA 4.0/4.1/4.2, we do not use MCS smart prefetch + * so keep the fields zero. + */ + if (ipa_get_hw_type() < IPA_HW_v4_0) { + chan_params.chan_scratch.xdci.outstanding_threshold = + ((params->teth_prot == IPA_USB_MBIM) ? 1 : 2) * + chan_params.chan_params.re_size; + } + /* max_outstanding_tre is set in ipa3_request_gsi_channel() */ + + result = ipa3_request_gsi_channel(&chan_params, out_params); + if (result) { + IPA_USB_ERR("failed to allocate GSI channel\n"); + ipa3_usb_smmu_map_xdci_channel(params, false); + return result; + } + + IPA_USB_DBG_LOW("exit\n"); + return 0; +} + +static int ipa3_usb_release_xdci_channel(u32 clnt_hdl, + enum ipa_usb_direction dir, + enum ipa3_usb_transport_type ttype) +{ + int result = 0; + struct ipa_usb_xdci_chan_params *xdci_ch_params; + + IPA_USB_DBG_LOW("entry\n"); + if (ttype < 0 || ttype >= IPA_USB_TRANSPORT_MAX) { + IPA_USB_ERR("bad parameter\n"); + return -EINVAL; + } + + if (!ipa3_usb_check_legal_op(IPA_USB_OP_RELEASE_CHANNEL, ttype)) { + IPA_USB_ERR("Illegal operation\n"); + return -EPERM; + } + + /* Release channel */ + result = ipa3_release_gsi_channel(clnt_hdl); + if (result) { + IPA_USB_ERR("failed to deallocate channel\n"); + return result; + } + + if (dir == IPA_USB_DIR_UL) + xdci_ch_params = &ipa3_usb_ctx->ttype_ctx[ttype].ul_ch_params; + else + xdci_ch_params = &ipa3_usb_ctx->ttype_ctx[ttype].dl_ch_params; + + result = ipa3_usb_smmu_map_xdci_channel(xdci_ch_params, false); + + if (xdci_ch_params->sgt_xfer_rings != NULL) + ipa_smmu_free_sgt(&xdci_ch_params->sgt_xfer_rings); + if (xdci_ch_params->sgt_data_buff != NULL) + ipa_smmu_free_sgt(&xdci_ch_params->sgt_data_buff); + + /* Change ipa_usb state to INITIALIZED */ + if (!ipa3_usb_set_state(IPA_USB_INITIALIZED, false, ttype)) + IPA_USB_ERR("failed to change state to initialized\n"); + + IPA_USB_DBG_LOW("exit\n"); + return 0; +} + + +static bool ipa3_usb_check_connect_params( + struct ipa_usb_xdci_connect_params_internal *params) +{ + IPA_USB_DBG_LOW("ul xferrscidx = %d\n", params->usb_to_ipa_xferrscidx); + IPA_USB_DBG_LOW("dl xferrscidx = %d\n", params->ipa_to_usb_xferrscidx); + IPA_USB_DBG_LOW("max_supported_bandwidth_mbps = %d\n", + params->max_supported_bandwidth_mbps); + + if (params->max_pkt_size < IPA_USB_FULL_SPEED_64B || + params->max_pkt_size > IPA_USB_SUPER_SPEED_1024B || + params->ipa_to_usb_xferrscidx > 127 || + (params->teth_prot != IPA_USB_DIAG && + (params->usb_to_ipa_xferrscidx > 127)) || + params->teth_prot < 0 || + params->teth_prot >= IPA_USB_MAX_TETH_PROT_SIZE) { + IPA_USB_ERR("Invalid params\n"); + return false; + } + + if (ipa3_usb_ctx->teth_prot_ctx[params->teth_prot].state == + IPA_USB_TETH_PROT_INVALID) { + IPA_USB_ERR("%s is not initialized\n", + ipa3_usb_teth_prot_to_string( + params->teth_prot)); + return false; + } + + return true; +} + +static int ipa3_usb_connect_teth_bridge( + struct teth_bridge_connect_params *params) +{ + int result; + + result = ipa3_teth_bridge_connect(params); + if (result) { + IPA_USB_ERR("failed to connect teth_bridge (%s)\n", + params->tethering_mode == TETH_TETHERING_MODE_RMNET ? + "rmnet" : "mbim"); + return result; + } + + return 0; +} + +static int ipa3_get_tethering_mode(enum ipa_usb_teth_prot teth_prot) +{ + if (teth_prot == IPA_USB_RMNET) + return TETH_TETHERING_MODE_RMNET; + else if (teth_prot == IPA_USB_RMNET_CV2X) + return TETH_TETHERING_MODE_RMNET_2; + else + return TETH_TETHERING_MODE_MBIM; +} + +static int ipa3_usb_connect_teth_prot(enum ipa_usb_teth_prot teth_prot) +{ + int result; + struct teth_bridge_connect_params teth_bridge_params; + struct ipa3_usb_teth_prot_conn_params *teth_conn_params; + enum ipa3_usb_transport_type ttype; + struct ipa3_usb_teth_prot_context *teth_prot_ptr = + &ipa3_usb_ctx->teth_prot_ctx[teth_prot]; + + IPA_USB_DBG("connecting protocol = %s\n", + ipa3_usb_teth_prot_to_string(teth_prot)); + + ttype = IPA3_USB_GET_TTYPE(teth_prot); + + teth_conn_params = &(ipa3_usb_ctx->ttype_ctx[ttype].teth_conn_params); + + switch (teth_prot) { + case IPA_USB_RNDIS: + if (teth_prot_ptr->state == + IPA_USB_TETH_PROT_CONNECTED) { + IPA_USB_DBG("%s is already connected\n", + ipa3_usb_teth_prot_to_string(teth_prot)); + break; + } + ipa3_usb_ctx->ttype_ctx[ttype].user_data = + teth_prot_ptr->user_data; + result = rndis_ipa_pipe_connect_notify( + teth_conn_params->usb_to_ipa_clnt_hdl, + teth_conn_params->ipa_to_usb_clnt_hdl, + teth_conn_params->params.max_xfer_size_bytes_to_dev, + teth_conn_params->params.max_packet_number_to_dev, + teth_conn_params->params.max_xfer_size_bytes_to_host, + teth_prot_ptr->teth_prot_params.rndis.private); + if (result) { + IPA_USB_ERR("failed to connect %s\n", + ipa3_usb_teth_prot_to_string(teth_prot)); + ipa3_usb_ctx->ttype_ctx[ttype].user_data = NULL; + return result; + } + teth_prot_ptr->state = + IPA_USB_TETH_PROT_CONNECTED; + IPA_USB_DBG("%s is connected\n", + ipa3_usb_teth_prot_to_string(teth_prot)); + break; + case IPA_USB_ECM: + if (teth_prot_ptr->state == + IPA_USB_TETH_PROT_CONNECTED) { + IPA_USB_DBG("%s is already connected\n", + ipa3_usb_teth_prot_to_string(teth_prot)); + break; + } + ipa3_usb_ctx->ttype_ctx[ttype].user_data = + teth_prot_ptr->user_data; + result = ecm_ipa_connect(teth_conn_params->usb_to_ipa_clnt_hdl, + teth_conn_params->ipa_to_usb_clnt_hdl, + teth_prot_ptr->teth_prot_params.ecm.private); + if (result) { + IPA_USB_ERR("failed to connect %s\n", + ipa3_usb_teth_prot_to_string(teth_prot)); + ipa3_usb_ctx->ttype_ctx[ttype].user_data = NULL; + return result; + } + teth_prot_ptr->state = + IPA_USB_TETH_PROT_CONNECTED; + IPA_USB_DBG("%s is connected\n", + ipa3_usb_teth_prot_to_string(teth_prot)); + break; + case IPA_USB_RMNET: + case IPA_USB_RMNET_CV2X: + case IPA_USB_MBIM: + if (teth_prot_ptr->state == + IPA_USB_TETH_PROT_CONNECTED) { + IPA_USB_DBG("%s is already connected\n", + ipa3_usb_teth_prot_to_string(teth_prot)); + break; + } + + result = ipa3_usb_init_teth_bridge(teth_prot); + if (result) + return result; + + ipa3_usb_ctx->ttype_ctx[ttype].user_data = + teth_prot_ptr->user_data; + teth_bridge_params.ipa_usb_pipe_hdl = + teth_conn_params->ipa_to_usb_clnt_hdl; + teth_bridge_params.usb_ipa_pipe_hdl = + teth_conn_params->usb_to_ipa_clnt_hdl; + teth_bridge_params.tethering_mode = + ipa3_get_tethering_mode(teth_prot); + + if (teth_prot == IPA_USB_RMNET_CV2X) + teth_bridge_params.client_type = IPA_CLIENT_USB2_PROD; + else + teth_bridge_params.client_type = IPA_CLIENT_USB_PROD; + + result = ipa3_usb_connect_teth_bridge(&teth_bridge_params); + if (result) { + ipa3_usb_ctx->ttype_ctx[ttype].user_data = NULL; + return result; + } + + ipa3_usb_ctx->teth_prot_ctx[teth_prot].state = + IPA_USB_TETH_PROT_CONNECTED; + ipa3_usb_notify_do(ttype, IPA_USB_DEVICE_READY); + IPA_USB_DBG("%s (%s) is connected\n", + ipa3_usb_teth_prot_to_string(teth_prot), + ipa3_usb_teth_bridge_prot_to_string(teth_prot)); + break; + case IPA_USB_DIAG: + if (ipa3_usb_ctx->teth_prot_ctx[IPA_USB_DIAG].state == + IPA_USB_TETH_PROT_CONNECTED) { + IPA_USB_DBG("%s is already connected\n", + ipa3_usb_teth_prot_to_string(teth_prot)); + break; + } + + ipa3_usb_ctx->ttype_ctx[ttype].user_data = + ipa3_usb_ctx->teth_prot_ctx[teth_prot].user_data; + ipa3_usb_ctx->teth_prot_ctx[IPA_USB_DIAG].state = + IPA_USB_TETH_PROT_CONNECTED; + ipa3_usb_notify_do(ttype, IPA_USB_DEVICE_READY); + IPA_USB_DBG("%s is connected\n", + ipa3_usb_teth_prot_to_string(teth_prot)); + break; + default: + IPA_USB_ERR("Invalid tethering protocol\n"); + return -EFAULT; + } + + return 0; +} + +static int ipa3_usb_disconnect_teth_bridge(enum ipa_usb_teth_prot teth_prot) +{ + int result; + + if (teth_prot == IPA_USB_RMNET_CV2X) + result = ipa3_teth_bridge_disconnect(IPA_CLIENT_USB2_PROD); + else + result = ipa3_teth_bridge_disconnect(IPA_CLIENT_USB_PROD); + + if (result) { + IPA_USB_ERR("failed to disconnect teth_bridge\n"); + return result; + } + + return 0; +} + +static int ipa3_usb_disconnect_teth_prot(enum ipa_usb_teth_prot teth_prot) +{ + int result = 0; + enum ipa3_usb_transport_type ttype; + struct ipa3_usb_teth_prot_context *teth_prot_ptr = + &ipa3_usb_ctx->teth_prot_ctx[teth_prot]; + + ttype = IPA3_USB_GET_TTYPE(teth_prot); + + switch (teth_prot) { + case IPA_USB_RNDIS: + case IPA_USB_ECM: + if (ipa3_usb_ctx->teth_prot_ctx[teth_prot].state != + IPA_USB_TETH_PROT_CONNECTED) { + IPA_USB_DBG("%s is not connected\n", + ipa3_usb_teth_prot_to_string(teth_prot)); + return -EPERM; + } + if (teth_prot == IPA_USB_RNDIS) { + result = rndis_ipa_pipe_disconnect_notify( + teth_prot_ptr->teth_prot_params.rndis.private); + } else { + result = ecm_ipa_disconnect( + teth_prot_ptr->teth_prot_params.ecm.private); + } + if (result) { + IPA_USB_ERR("failed to disconnect %s\n", + ipa3_usb_teth_prot_to_string(teth_prot)); + break; + } + teth_prot_ptr->state = IPA_USB_TETH_PROT_INITIALIZED; + IPA_USB_DBG("disconnected %s\n", + ipa3_usb_teth_prot_to_string(teth_prot)); + break; + case IPA_USB_RMNET: + case IPA_USB_RMNET_CV2X: + case IPA_USB_MBIM: + if (teth_prot_ptr->state != IPA_USB_TETH_PROT_CONNECTED) { + IPA_USB_DBG("%s (%s) is not connected\n", + ipa3_usb_teth_prot_to_string(teth_prot), + ipa3_usb_teth_bridge_prot_to_string(teth_prot)); + return -EPERM; + } + + result = ipa3_usb_disconnect_teth_bridge(teth_prot); + if (result) + break; + + teth_prot_ptr->state = IPA_USB_TETH_PROT_INITIALIZED; + IPA_USB_DBG("disconnected %s (%s)\n", + ipa3_usb_teth_prot_to_string(teth_prot), + ipa3_usb_teth_bridge_prot_to_string(teth_prot)); + break; + case IPA_USB_DIAG: + if (teth_prot_ptr->state != IPA_USB_TETH_PROT_CONNECTED) { + IPA_USB_DBG("%s is not connected\n", + ipa3_usb_teth_prot_to_string(teth_prot)); + return -EPERM; + } + teth_prot_ptr->state = IPA_USB_TETH_PROT_INITIALIZED; + IPA_USB_DBG("disconnected %s\n", + ipa3_usb_teth_prot_to_string(teth_prot)); + break; + default: + break; + } + + ipa3_usb_ctx->ttype_ctx[ttype].user_data = NULL; + return result; +} + +static int ipa3_usb_xdci_connect_internal( + struct ipa_usb_xdci_connect_params_internal *params) +{ + int result = -EFAULT; + enum ipa3_usb_transport_type ttype; + struct ipa3_usb_teth_prot_conn_params *teth_prot_ptr; + + IPA_USB_DBG_LOW("entry\n"); + if (params == NULL || !ipa3_usb_check_connect_params(params)) { + IPA_USB_ERR("bad parameters\n"); + return -EINVAL; + } + + ttype = IPA3_USB_GET_TTYPE(params->teth_prot); + + if (!ipa3_usb_check_legal_op(IPA_USB_OP_CONNECT, ttype)) { + IPA_USB_ERR("Illegal operation\n"); + return -EPERM; + } + + teth_prot_ptr = &ipa3_usb_ctx->ttype_ctx[ttype].teth_conn_params; + teth_prot_ptr->ipa_to_usb_clnt_hdl = params->ipa_to_usb_clnt_hdl; + + if (!IPA3_USB_IS_TTYPE_DPL(ttype)) + teth_prot_ptr->usb_to_ipa_clnt_hdl = + params->usb_to_ipa_clnt_hdl; + teth_prot_ptr->params = params->teth_prot_params; + + /* Set EE xDCI specific scratch */ + result = ipa3_set_usb_max_packet_size(params->max_pkt_size); + if (result) { + IPA_USB_ERR("failed setting xDCI EE scratch field\n"); + return result; + } + /* perf profile is not set on USB DPL pipe */ + if (ttype != IPA_USB_TRANSPORT_DPL) { + result = ipa_pm_set_throughput( + ipa3_usb_ctx->ttype_ctx[ttype].pm_ctx.hdl, + params->max_supported_bandwidth_mbps); + if (result) { + IPA_USB_ERR("failed to set pm throughput\n"); + return result; + } + } + + result = ipa_pm_activate_sync( + ipa3_usb_ctx->ttype_ctx[ttype].pm_ctx.hdl); + if (result) { + IPA_USB_ERR("failed to activate pm\n"); + return result; + } + + /* Start MHIP UL channel before starting USB UL channel + * DL channel will be started when voting for PCIe -> LPM Exit. + */ + if (ipa3_is_mhip_offload_enabled()) { + result = ipa_mpm_mhip_xdci_pipe_enable(params->teth_prot); + if (result) { + IPA_USB_ERR("failed to enable MHIP UL channel\n"); + goto connect_fail; + } + } + + if (params->teth_prot != IPA_USB_DIAG) { + /* Start UL channel */ + result = ipa3_xdci_start(params->usb_to_ipa_clnt_hdl, + params->usb_to_ipa_xferrscidx, + params->usb_to_ipa_xferrscidx_valid); + if (result) { + IPA_USB_ERR("failed to connect UL channel\n"); + goto connect_ul_fail; + } + } + + /* Start DL/DPL channel */ + result = ipa3_xdci_start(params->ipa_to_usb_clnt_hdl, + params->ipa_to_usb_xferrscidx, + params->ipa_to_usb_xferrscidx_valid); + if (result) { + IPA_USB_ERR("failed to connect DL/DPL channel\n"); + goto connect_dl_fail; + } + + /* Connect tethering protocol */ + result = ipa3_usb_connect_teth_prot(params->teth_prot); + if (result) { + IPA_USB_ERR("failed to connect teth protocol\n"); + goto connect_teth_prot_fail; + } + + if (!ipa3_usb_set_state(IPA_USB_CONNECTED, false, ttype)) { + IPA_USB_ERR( + "failed to change state to connected\n"); + goto state_change_connected_fail; + } + + IPA_USB_DBG_LOW("exit\n"); + return 0; + +state_change_connected_fail: + ipa3_usb_disconnect_teth_prot(params->teth_prot); +connect_teth_prot_fail: + ipa3_xdci_disconnect(params->ipa_to_usb_clnt_hdl, false, -1); + ipa3_reset_gsi_channel(params->ipa_to_usb_clnt_hdl); + ipa3_reset_gsi_event_ring(params->ipa_to_usb_clnt_hdl); +connect_dl_fail: + if (params->teth_prot != IPA_USB_DIAG) { + ipa3_xdci_disconnect(params->usb_to_ipa_clnt_hdl, false, -1); + ipa3_reset_gsi_channel(params->usb_to_ipa_clnt_hdl); + ipa3_reset_gsi_event_ring(params->usb_to_ipa_clnt_hdl); + } +connect_ul_fail: + if (ipa3_is_mhip_offload_enabled()) + ipa_mpm_mhip_xdci_pipe_disable(params->teth_prot); +connect_fail: + ipa_pm_deactivate_sync( + ipa3_usb_ctx->ttype_ctx[ttype].pm_ctx.hdl); + + return result; +} + +#ifdef CONFIG_DEBUG_FS +static char dbg_buff[IPA_USB_MAX_MSG_LEN]; + +static int ipa3_usb_get_status_dbg_info(struct ipa3_usb_status_dbg_info *status) +{ + int res; + int i; + unsigned long flags; + + IPA_USB_DBG_LOW("entry\n"); + + if (ipa3_usb_ctx == NULL) { + IPA_USB_ERR("IPA USB was not inited yet\n"); + return -EFAULT; + } + + mutex_lock(&ipa3_usb_ctx->general_mutex); + + if (!status) { + IPA_USB_ERR("Invalid input\n"); + res = -EINVAL; + goto bail; + } + + memset(status, 0, sizeof(struct ipa3_usb_status_dbg_info)); + + spin_lock_irqsave(&ipa3_usb_ctx->state_lock, flags); + status->teth_state = ipa3_usb_state_to_string( + ipa3_usb_ctx->ttype_ctx[IPA_USB_TRANSPORT_TETH].state); + status->dpl_state = ipa3_usb_state_to_string( + ipa3_usb_ctx->ttype_ctx[IPA_USB_TRANSPORT_DPL].state); + spin_unlock_irqrestore(&ipa3_usb_ctx->state_lock, flags); + + for (i = 0 ; i < IPA_USB_MAX_TETH_PROT_SIZE ; i++) { + if (ipa3_usb_ctx->teth_prot_ctx[i].state == + IPA_USB_TETH_PROT_INITIALIZED) { + if ((i == IPA_USB_RMNET) || + (i == IPA_USB_MBIM) || + (i == IPA_USB_RMNET_CV2X)) + status->inited_prots[status->num_init_prot++] = + ipa3_usb_teth_bridge_prot_to_string(i); + else + status->inited_prots[status->num_init_prot++] = + ipa3_usb_teth_prot_to_string(i); + } else if (ipa3_usb_ctx->teth_prot_ctx[i].state == + IPA_USB_TETH_PROT_CONNECTED) { + switch (i) { + case IPA_USB_RMNET: + case IPA_USB_RMNET_CV2X: + case IPA_USB_MBIM: + status->teth_connected_prot = + ipa3_usb_teth_bridge_prot_to_string(i); + break; + case IPA_USB_DIAG: + status->dpl_connected_prot = + ipa3_usb_teth_prot_to_string(i); + break; + default: + status->teth_connected_prot = + ipa3_usb_teth_prot_to_string(i); + } + } + } + + res = 0; + IPA_USB_DBG_LOW("exit\n"); +bail: + mutex_unlock(&ipa3_usb_ctx->general_mutex); + return res; +} + +static ssize_t ipa3_read_usb_state_info(struct file *file, char __user *ubuf, + size_t count, loff_t *ppos) +{ + struct ipa3_usb_status_dbg_info status; + int result; + int nbytes; + int cnt = 0; + int i; + + result = ipa3_usb_get_status_dbg_info(&status); + if (result) { + nbytes = scnprintf(dbg_buff, IPA_USB_MAX_MSG_LEN, + "Fail to read IPA USB status\n"); + cnt += nbytes; + } else { + nbytes = scnprintf(dbg_buff, IPA_USB_MAX_MSG_LEN, + "Tethering Data State: %s\n" + "DPL State: %s\n" + "Protocols in Initialized State: ", + status.teth_state, + status.dpl_state); + cnt += nbytes; + + for (i = 0 ; i < status.num_init_prot ; i++) { + nbytes = scnprintf(dbg_buff + cnt, + IPA_USB_MAX_MSG_LEN - cnt, + "%s ", status.inited_prots[i]); + cnt += nbytes; + } + nbytes = scnprintf(dbg_buff + cnt, IPA_USB_MAX_MSG_LEN - cnt, + status.num_init_prot ? "\n" : "None\n"); + cnt += nbytes; + + nbytes = scnprintf(dbg_buff + cnt, IPA_USB_MAX_MSG_LEN - cnt, + "Protocols in Connected State: "); + cnt += nbytes; + if (status.teth_connected_prot) { + nbytes = scnprintf(dbg_buff + cnt, + IPA_USB_MAX_MSG_LEN - cnt, + "%s ", status.teth_connected_prot); + cnt += nbytes; + } + if (status.dpl_connected_prot) { + nbytes = scnprintf(dbg_buff + cnt, + IPA_USB_MAX_MSG_LEN - cnt, + "%s ", status.dpl_connected_prot); + cnt += nbytes; + } + nbytes = scnprintf(dbg_buff + cnt, IPA_USB_MAX_MSG_LEN - cnt, + (status.teth_connected_prot || + status.dpl_connected_prot) ? "\n" : "None\n"); + cnt += nbytes; + } + + return simple_read_from_buffer(ubuf, count, ppos, dbg_buff, cnt); +} + +static const struct file_operations ipa3_ipa_usb_ops = { + .read = ipa3_read_usb_state_info, +}; + +static void ipa_usb_debugfs_init(void) +{ + const mode_t read_only_mode = 0444; + + ipa3_usb_ctx->dent = debugfs_create_dir("ipa_usb", 0); + if (IS_ERR(ipa3_usb_ctx->dent)) { + pr_err("fail to create folder in debug_fs\n"); + return; + } + + ipa3_usb_ctx->dfile_state_info = debugfs_create_file("state_info", + read_only_mode, ipa3_usb_ctx->dent, 0, + &ipa3_ipa_usb_ops); + if (!ipa3_usb_ctx->dfile_state_info || + IS_ERR(ipa3_usb_ctx->dfile_state_info)) { + pr_err("failed to create file for state_info\n"); + goto fail; + } + + return; + +fail: + debugfs_remove_recursive(ipa3_usb_ctx->dent); + ipa3_usb_ctx->dent = NULL; +} + +static void ipa_usb_debugfs_remove(void) +{ + if (IS_ERR(ipa3_usb_ctx->dent)) { + IPA_USB_ERR("ipa_usb debugfs folder was not created\n"); + return; + } + + debugfs_remove_recursive(ipa3_usb_ctx->dent); +} +#else /* CONFIG_DEBUG_FS */ +static void ipa_usb_debugfs_init(void){} +static void ipa_usb_debugfs_remove(void){} +#endif /* CONFIG_DEBUG_FS */ + +int ipa_usb_xdci_connect(struct ipa_usb_xdci_chan_params *ul_chan_params, + struct ipa_usb_xdci_chan_params *dl_chan_params, + struct ipa_req_chan_out_params *ul_out_params, + struct ipa_req_chan_out_params *dl_out_params, + struct ipa_usb_xdci_connect_params *connect_params) +{ + int result = -EFAULT; + struct ipa_usb_xdci_connect_params_internal conn_params; + + mutex_lock(&ipa3_usb_ctx->general_mutex); + IPA_USB_DBG_LOW("entry\n"); + if (connect_params == NULL || dl_chan_params == NULL || + dl_out_params == NULL || + (connect_params->teth_prot != IPA_USB_DIAG && + (ul_chan_params == NULL || ul_out_params == NULL))) { + IPA_USB_ERR("bad parameters\n"); + result = -EINVAL; + goto bad_params; + } + + if (!ipa3_usb_is_teth_switch_valid(connect_params->teth_prot)) { + IPA_USB_ERR("Invalid teth type switch\n"); + goto bad_params; + } + + if (connect_params->teth_prot != IPA_USB_DIAG) { + result = ipa3_usb_request_xdci_channel(ul_chan_params, + IPA_USB_DIR_UL, ul_out_params); + if (result) { + IPA_USB_ERR("failed to allocate UL channel\n"); + goto bad_params; + } + } + + result = ipa3_usb_request_xdci_channel(dl_chan_params, IPA_USB_DIR_DL, + dl_out_params); + if (result) { + IPA_USB_ERR("failed to allocate DL/DPL channel\n"); + goto alloc_dl_chan_fail; + } + + memset(&conn_params, 0, + sizeof(struct ipa_usb_xdci_connect_params_internal)); + conn_params.max_pkt_size = connect_params->max_pkt_size; + conn_params.ipa_to_usb_clnt_hdl = dl_out_params->clnt_hdl; + conn_params.ipa_to_usb_xferrscidx = + connect_params->ipa_to_usb_xferrscidx; + conn_params.ipa_to_usb_xferrscidx_valid = + connect_params->ipa_to_usb_xferrscidx_valid; + if (connect_params->teth_prot != IPA_USB_DIAG) { + conn_params.usb_to_ipa_clnt_hdl = ul_out_params->clnt_hdl; + conn_params.usb_to_ipa_xferrscidx = + connect_params->usb_to_ipa_xferrscidx; + conn_params.usb_to_ipa_xferrscidx_valid = + connect_params->usb_to_ipa_xferrscidx_valid; + } + conn_params.teth_prot = connect_params->teth_prot; + conn_params.teth_prot_params = connect_params->teth_prot_params; + conn_params.max_supported_bandwidth_mbps = + connect_params->max_supported_bandwidth_mbps; + result = ipa3_usb_xdci_connect_internal(&conn_params); + if (result) { + IPA_USB_ERR("failed to connect\n"); + goto connect_fail; + } + + IPA_USB_DBG_LOW("exit\n"); + mutex_unlock(&ipa3_usb_ctx->general_mutex); + return 0; + +connect_fail: + ipa3_usb_release_xdci_channel(dl_out_params->clnt_hdl, IPA_USB_DIR_DL, + IPA3_USB_GET_TTYPE(dl_chan_params->teth_prot)); +alloc_dl_chan_fail: + if (connect_params->teth_prot != IPA_USB_DIAG) + ipa3_usb_release_xdci_channel(ul_out_params->clnt_hdl, + IPA_USB_DIR_UL, + IPA3_USB_GET_TTYPE(ul_chan_params->teth_prot)); +bad_params: + mutex_unlock(&ipa3_usb_ctx->general_mutex); + return result; +} +EXPORT_SYMBOL(ipa_usb_xdci_connect); + +static int ipa3_usb_check_disconnect_prot(enum ipa_usb_teth_prot teth_prot) +{ + if (teth_prot < 0 || teth_prot >= IPA_USB_MAX_TETH_PROT_SIZE) { + IPA_USB_ERR("bad parameter\n"); + return -EFAULT; + } + + if (ipa3_usb_ctx->teth_prot_ctx[teth_prot].state != + IPA_USB_TETH_PROT_CONNECTED) { + IPA_USB_ERR("%s is not connected\n", + ipa3_usb_teth_prot_to_string(teth_prot)); + return -EFAULT; + } + + return 0; +} + +/* Assumes lock already acquired */ +static int ipa_usb_xdci_dismiss_channels(u32 ul_clnt_hdl, u32 dl_clnt_hdl, + enum ipa_usb_teth_prot teth_prot) +{ + int result = 0; + enum ipa3_usb_transport_type ttype; + + ttype = IPA3_USB_GET_TTYPE(teth_prot); + + IPA_USB_DBG_LOW("entry\n"); + + /* Reset DL channel */ + result = ipa3_reset_gsi_channel(dl_clnt_hdl); + if (result) { + IPA_USB_ERR("failed to reset DL channel\n"); + return result; + } + + /* Reset DL event ring */ + result = ipa3_reset_gsi_event_ring(dl_clnt_hdl); + if (result) { + IPA_USB_ERR("failed to reset DL event ring\n"); + return result; + } + + if (!IPA3_USB_IS_TTYPE_DPL(ttype)) { + ipa3_xdci_ep_delay_rm(ul_clnt_hdl); /* Remove ep_delay if set */ + /* Reset UL channel */ + result = ipa3_reset_gsi_channel(ul_clnt_hdl); + if (result) { + IPA_USB_ERR("failed to reset UL channel\n"); + return result; + } + + /* Reset UL event ring */ + result = ipa3_reset_gsi_event_ring(ul_clnt_hdl); + if (result) { + IPA_USB_ERR("failed to reset UL event ring\n"); + return result; + } + } + + /* Change state to STOPPED */ + if (!ipa3_usb_set_state(IPA_USB_STOPPED, false, ttype)) + IPA_USB_ERR("failed to change state to stopped\n"); + + if (!IPA3_USB_IS_TTYPE_DPL(ttype)) { + result = ipa3_usb_release_xdci_channel(ul_clnt_hdl, + IPA_USB_DIR_UL, ttype); + if (result) { + IPA_USB_ERR("failed to release UL channel\n"); + return result; + } + } + + result = ipa3_usb_release_xdci_channel(dl_clnt_hdl, + IPA_USB_DIR_DL, ttype); + if (result) { + IPA_USB_ERR("failed to release DL channel\n"); + return result; + } + + IPA_USB_DBG_LOW("exit\n"); + + return 0; +} + +int ipa_usb_xdci_disconnect(u32 ul_clnt_hdl, u32 dl_clnt_hdl, + enum ipa_usb_teth_prot teth_prot) +{ + int result = 0; + struct ipa_ep_cfg_holb holb_cfg; + unsigned long flags; + enum ipa3_usb_state orig_state; + enum ipa3_usb_transport_type ttype; + + mutex_lock(&ipa3_usb_ctx->general_mutex); + IPA_USB_DBG_LOW("entry\n"); + + ttype = IPA3_USB_GET_TTYPE(teth_prot); + + if (!ipa3_usb_check_legal_op(IPA_USB_OP_DISCONNECT, ttype)) { + IPA_USB_ERR("Illegal operation\n"); + result = -EPERM; + goto bad_params; + } + + spin_lock_irqsave(&ipa3_usb_ctx->state_lock, flags); + if (ipa3_usb_ctx->ttype_ctx[ttype].state == + IPA_USB_SUSPENDED_NO_RWAKEUP) { + spin_unlock_irqrestore(&ipa3_usb_ctx->state_lock, flags); + result = ipa_usb_xdci_dismiss_channels(ul_clnt_hdl, dl_clnt_hdl, + teth_prot); + mutex_unlock(&ipa3_usb_ctx->general_mutex); + return result; + } + + if (ipa3_usb_check_disconnect_prot(teth_prot)) { + spin_unlock_irqrestore(&ipa3_usb_ctx->state_lock, flags); + result = -EINVAL; + goto bad_params; + } + + if (ipa3_usb_ctx->ttype_ctx[ttype].state != IPA_USB_SUSPENDED) { + spin_unlock_irqrestore(&ipa3_usb_ctx->state_lock, flags); + /* Stop DL/DPL channel */ + result = ipa3_xdci_disconnect(dl_clnt_hdl, false, -1); + if (result) { + IPA_USB_ERR("failed to disconnect DL/DPL channel\n"); + goto bad_params; + } + } else { + spin_unlock_irqrestore(&ipa3_usb_ctx->state_lock, flags); + memset(&holb_cfg, 0, sizeof(holb_cfg)); + holb_cfg.en = IPA_HOLB_TMR_EN; + holb_cfg.tmr_val = 0; + ipa3_cfg_ep_holb(dl_clnt_hdl, &holb_cfg); + } + + spin_lock_irqsave(&ipa3_usb_ctx->state_lock, flags); + orig_state = ipa3_usb_ctx->ttype_ctx[ttype].state; + if (!IPA3_USB_IS_TTYPE_DPL(ttype)) { + if (orig_state != IPA_USB_SUSPENDED) { + spin_unlock_irqrestore(&ipa3_usb_ctx->state_lock, + flags); + /* Stop UL channel */ + result = ipa3_xdci_disconnect(ul_clnt_hdl, + true, + ipa3_usb_ctx->qmi_req_id); + if (result) { + IPA_USB_ERR("failed disconnect UL channel\n"); + goto bad_params; + } + ipa3_usb_ctx->qmi_req_id++; + } else + spin_unlock_irqrestore(&ipa3_usb_ctx->state_lock, + flags); + } else + spin_unlock_irqrestore(&ipa3_usb_ctx->state_lock, flags); + + /* Stop UL/DL MHIP channels */ + if (ipa3_is_mhip_offload_enabled()) { + result = ipa_mpm_mhip_xdci_pipe_disable(teth_prot); + if (result) { + IPA_USB_ERR("failed to disconnect MHIP pipe\n"); + goto bad_params; + } + } + + result = ipa_usb_xdci_dismiss_channels(ul_clnt_hdl, dl_clnt_hdl, + teth_prot); + if (result) + goto bad_params; + + /* Disconnect tethering protocol */ + result = ipa3_usb_disconnect_teth_prot(teth_prot); + if (result) + goto bad_params; + + if (orig_state != IPA_USB_SUSPENDED) { + result = ipa_pm_deactivate_sync( + ipa3_usb_ctx->ttype_ctx[ttype].pm_ctx.hdl); + if (result) { + IPA_USB_ERR("failed to deactivate PM\n"); + goto bad_params; + } + } + + IPA_USB_DBG_LOW("exit\n"); + mutex_unlock(&ipa3_usb_ctx->general_mutex); + return 0; + +bad_params: + mutex_unlock(&ipa3_usb_ctx->general_mutex); + return result; + +} +EXPORT_SYMBOL(ipa_usb_xdci_disconnect); + +int ipa_usb_deinit_teth_prot(enum ipa_usb_teth_prot teth_prot) +{ + int result = -EFAULT; + enum ipa3_usb_transport_type ttype; + struct ipa3_usb_teth_prot_context *teth_prot_ptr; + + mutex_lock(&ipa3_usb_ctx->general_mutex); + IPA_USB_DBG_LOW("entry\n"); + if (teth_prot < 0 || teth_prot >= IPA_USB_MAX_TETH_PROT_SIZE) { + IPA_USB_ERR("bad parameters\n"); + result = -EINVAL; + goto bad_params; + } + + ttype = IPA3_USB_GET_TTYPE(teth_prot); + + if (!ipa3_usb_check_legal_op(IPA_USB_OP_DEINIT_TETH_PROT, ttype)) { + IPA_USB_ERR("Illegal operation\n"); + result = -EPERM; + goto bad_params; + } + + /* Clean-up tethering protocol */ + teth_prot_ptr = &ipa3_usb_ctx->teth_prot_ctx[teth_prot]; + + switch (teth_prot) { + case IPA_USB_RNDIS: + case IPA_USB_ECM: + if (teth_prot_ptr->state != + IPA_USB_TETH_PROT_INITIALIZED) { + IPA_USB_ERR("%s is not initialized\n", + ipa3_usb_teth_prot_to_string(teth_prot)); + result = -EINVAL; + goto bad_params; + } + if (teth_prot == IPA_USB_RNDIS) + rndis_ipa_cleanup( + teth_prot_ptr->teth_prot_params.rndis.private); + else + ecm_ipa_cleanup( + teth_prot_ptr->teth_prot_params.ecm.private); + teth_prot_ptr->user_data = NULL; + teth_prot_ptr->state = IPA_USB_TETH_PROT_INVALID; + ipa3_usb_ctx->num_init_prot--; + IPA_USB_DBG("deinitialized %s\n", + ipa3_usb_teth_prot_to_string(teth_prot)); + break; + case IPA_USB_RMNET: + case IPA_USB_MBIM: + if (teth_prot_ptr->state != + IPA_USB_TETH_PROT_INITIALIZED) { + IPA_USB_ERR("%s (%s) is not initialized\n", + ipa3_usb_teth_prot_to_string(teth_prot), + ipa3_usb_teth_bridge_prot_to_string(teth_prot)); + result = -EINVAL; + goto bad_params; + } + + teth_prot_ptr->user_data = NULL; + teth_prot_ptr->state = IPA_USB_TETH_PROT_INVALID; + ipa3_usb_ctx->num_init_prot--; + IPA_USB_DBG("deinitialized %s (%s)\n", + ipa3_usb_teth_prot_to_string(teth_prot), + ipa3_usb_teth_bridge_prot_to_string(teth_prot)); + break; + case IPA_USB_RMNET_CV2X: + if (ipa3_usb_ctx->teth_prot_ctx[teth_prot].state != + IPA_USB_TETH_PROT_INITIALIZED) { + IPA_USB_ERR("%s (%s) is not initialized\n", + ipa3_usb_teth_prot_to_string(teth_prot), + ipa3_usb_teth_bridge_prot_to_string(teth_prot)); + result = -EINVAL; + goto bad_params; + } + + ipa3_usb_ctx->teth_prot_ctx[teth_prot].user_data = + NULL; + ipa3_usb_ctx->teth_prot_ctx[teth_prot].state = + IPA_USB_TETH_PROT_INVALID; + IPA_USB_DBG("deinitialized %s (%s)\n", + ipa3_usb_teth_prot_to_string(teth_prot), + ipa3_usb_teth_bridge_prot_to_string(teth_prot)); + break; + case IPA_USB_DIAG: + if (teth_prot_ptr->state != + IPA_USB_TETH_PROT_INITIALIZED) { + IPA_USB_ERR("%s is not initialized\n", + ipa3_usb_teth_prot_to_string(teth_prot)); + result = -EINVAL; + goto bad_params; + } + teth_prot_ptr->user_data = NULL; + teth_prot_ptr->state = IPA_USB_TETH_PROT_INVALID; + IPA_USB_DBG("deinitialized %s\n", + ipa3_usb_teth_prot_to_string(teth_prot)); + break; + default: + IPA_USB_ERR("unexpected tethering protocol\n"); + result = -EINVAL; + goto bad_params; + } + + if (IPA3_USB_IS_TTYPE_DPL(ttype) || + (ipa3_usb_ctx->num_init_prot == 0) || + (teth_prot == IPA_USB_RMNET_CV2X)) { + if (!ipa3_usb_set_state(IPA_USB_INVALID, false, ttype)) + IPA_USB_ERR( + "failed to change state to invalid\n"); + ipa3_usb_deregister_pm(ttype); + ipa3_usb_ctx->ttype_ctx[ttype].ipa_usb_notify_cb = NULL; + } + + IPA_USB_DBG_LOW("exit\n"); + mutex_unlock(&ipa3_usb_ctx->general_mutex); + return 0; + +bad_params: + mutex_unlock(&ipa3_usb_ctx->general_mutex); + return result; +} +EXPORT_SYMBOL(ipa_usb_deinit_teth_prot); + +/* Assumes lock already acquired */ +static int ipa3_usb_suspend_no_remote_wakeup(u32 ul_clnt_hdl, u32 dl_clnt_hdl, + enum ipa_usb_teth_prot teth_prot) +{ + int result = 0; + enum ipa3_usb_transport_type ttype; + + ttype = IPA3_USB_GET_TTYPE(teth_prot); + + if (!ipa3_usb_check_legal_op(IPA_USB_OP_SUSPEND_NO_RWAKEUP, ttype)) { + IPA_USB_ERR("Illegal operation\n"); + result = -EPERM; + goto fail_exit; + } + + IPA_USB_DBG("Start suspend with no remote wakeup sequence: %s\n", + IPA3_USB_IS_TTYPE_DPL(ttype) ? + "DPL channel":"Data Tethering channels"); + + if (ipa3_usb_check_disconnect_prot(teth_prot)) { + result = -EINVAL; + goto fail_exit; + } + + /* Stop DL/DPL channel */ + result = ipa3_xdci_disconnect(dl_clnt_hdl, false, -1); + if (result) { + IPA_USB_ERR("failed to disconnect DL/DPL channel\n"); + goto fail_exit; + } + + if (!IPA3_USB_IS_TTYPE_DPL(ttype)) { + /* Stop UL channel */ + result = ipa3_xdci_disconnect(ul_clnt_hdl, true, + ipa3_usb_ctx->qmi_req_id); + if (result) { + IPA_USB_ERR("failed disconnect UL channel\n"); + goto start_dl; + } + ipa3_usb_ctx->qmi_req_id++; + } + + /* Stop MHIP channel */ + if (ipa3_is_mhip_offload_enabled()) { + result = ipa_mpm_mhip_xdci_pipe_disable(teth_prot); + if (result) { + IPA_USB_ERR("failed to disconnect MHIP pipe\n"); + goto start_ul; + } + } + + /* Disconnect tethering protocol */ + result = ipa3_usb_disconnect_teth_prot(teth_prot); + if (result) + goto enable_mhip; + + result = ipa_pm_deactivate_sync( + ipa3_usb_ctx->ttype_ctx[ttype].pm_ctx.hdl); + if (result) { + IPA_USB_ERR("failed to deactivate PM\n"); + goto connect_teth; + } + + /* Change ipa_usb state to SUSPENDED_NO_RWAKEUP */ + if (!ipa3_usb_set_state(IPA_USB_SUSPENDED_NO_RWAKEUP, false, ttype)) + IPA_USB_ERR("failed to change state to suspend no rwakeup\n"); + + IPA_USB_DBG_LOW("exit\n"); + return 0; + +connect_teth: + (void)ipa3_usb_connect_teth_prot(teth_prot); +enable_mhip: + if (ipa3_is_mhip_offload_enabled()) + (void)ipa_mpm_mhip_xdci_pipe_enable(teth_prot); +start_ul: + if (!IPA3_USB_IS_TTYPE_DPL(ttype)) + (void)ipa3_xdci_connect(ul_clnt_hdl); +start_dl: + (void)ipa3_xdci_connect(dl_clnt_hdl); +fail_exit: + return result; +} + +int ipa_usb_xdci_suspend(u32 ul_clnt_hdl, u32 dl_clnt_hdl, + enum ipa_usb_teth_prot teth_prot, bool with_remote_wakeup) +{ + int result = 0; + enum ipa3_usb_transport_type ttype; + + mutex_lock(&ipa3_usb_ctx->general_mutex); + IPA_USB_DBG_LOW("entry\n"); + + if (teth_prot < 0 || teth_prot >= IPA_USB_MAX_TETH_PROT_SIZE) { + IPA_USB_ERR("bad parameters\n"); + result = -EINVAL; + goto bad_params; + } + + if (!with_remote_wakeup) { + result = ipa3_usb_suspend_no_remote_wakeup(ul_clnt_hdl, + dl_clnt_hdl, teth_prot); + mutex_unlock(&ipa3_usb_ctx->general_mutex); + return result; + } + + ttype = IPA3_USB_GET_TTYPE(teth_prot); + + if (!ipa3_usb_check_legal_op(IPA_USB_OP_SUSPEND, ttype)) { + IPA_USB_ERR("Illegal operation\n"); + result = -EPERM; + goto bad_params; + } + + IPA_USB_DBG("Start suspend sequence: %s\n", + IPA3_USB_IS_TTYPE_DPL(ttype) ? + "DPL channel":"Data Tethering channels"); + + /* Change state to SUSPEND_REQUESTED */ + if (!ipa3_usb_set_state(IPA_USB_SUSPEND_REQUESTED, false, ttype)) { + IPA_USB_ERR( + "fail changing state to suspend_req\n"); + result = -EFAULT; + goto bad_params; + } + + /* Stop UL channel & suspend DL/DPL EP */ + result = ipa3_xdci_suspend(ul_clnt_hdl, dl_clnt_hdl, + true, + ipa3_usb_ctx->qmi_req_id, IPA3_USB_IS_TTYPE_DPL(ttype)); + if (result) { + IPA_USB_ERR("failed to suspend\n"); + goto suspend_fail; + } + ipa3_usb_ctx->qmi_req_id++; + + result = ipa_pm_deactivate_sync( + ipa3_usb_ctx->ttype_ctx[ttype].pm_ctx.hdl); + if (result) { + IPA_USB_ERR("failed to deactivate PM IPA client\n"); + goto pm_deactivate_fail; + } + + /* Change state to SUSPENDED */ + if (!ipa3_usb_set_state(IPA_USB_SUSPENDED, false, ttype)) + IPA_USB_ERR("failed to change state to suspended\n"); + + + IPA_USB_DBG_LOW("exit\n"); + mutex_unlock(&ipa3_usb_ctx->general_mutex); + return 0; + +pm_deactivate_fail: + ipa3_xdci_resume(ul_clnt_hdl, dl_clnt_hdl, + IPA3_USB_IS_TTYPE_DPL(ttype)); +suspend_fail: + /* Change state back to CONNECTED */ + if (!ipa3_usb_set_state(IPA_USB_CONNECTED, true, ttype)) + IPA_USB_ERR("failed to change state back to connected\n"); +bad_params: + mutex_unlock(&ipa3_usb_ctx->general_mutex); + return result; +} +EXPORT_SYMBOL(ipa_usb_xdci_suspend); + +/* Assumes lock already acquired */ +static int ipa3_usb_resume_no_remote_wakeup(u32 ul_clnt_hdl, u32 dl_clnt_hdl, + enum ipa_usb_teth_prot teth_prot) +{ + int result = -EFAULT; + enum ipa3_usb_transport_type ttype; + + ttype = IPA3_USB_GET_TTYPE(teth_prot); + + IPA_USB_DBG("Start resume with no remote wakeup sequence: %s\n", + IPA3_USB_IS_TTYPE_DPL(ttype) ? + "DPL channel":"Data Tethering channels"); + + /* Activate PM */ + result = ipa_pm_activate_sync( + ipa3_usb_ctx->ttype_ctx[ttype].pm_ctx.hdl); + if (result) + goto fail_exit; + + /* Connect tethering protocol */ + result = ipa3_usb_connect_teth_prot(teth_prot); + if (result) { + IPA_USB_ERR("failed to connect teth protocol\n"); + goto release_prod; + } + + if (!IPA3_USB_IS_TTYPE_DPL(ttype)) { + /* Start UL channel */ + result = ipa3_xdci_connect(ul_clnt_hdl); + if (result) { + IPA_USB_ERR("failed to start UL channel\n"); + goto disconn_teth; + } + } + + /* Start DL/DPL channel */ + result = ipa3_xdci_connect(dl_clnt_hdl); + if (result) { + IPA_USB_ERR("failed to start DL/DPL channel\n"); + goto stop_ul; + } + + /* Start MHIP channel */ + if (ipa3_is_mhip_offload_enabled()) { + result = ipa_mpm_mhip_xdci_pipe_enable(teth_prot); + if (result) { + IPA_USB_ERR("failed to enable MHIP pipe\n"); + goto stop_dl; + } + } + /* Change state to CONNECTED */ + if (!ipa3_usb_set_state(IPA_USB_CONNECTED, false, ttype)) { + IPA_USB_ERR("failed to change state to connected\n"); + result = -EFAULT; + goto stop_mhip; + } + + return 0; +stop_mhip: + if (ipa3_is_mhip_offload_enabled()) + (void)ipa_mpm_mhip_xdci_pipe_disable(teth_prot); +stop_dl: + (void)ipa3_xdci_disconnect(dl_clnt_hdl, false, -1); +stop_ul: + if (!IPA3_USB_IS_TTYPE_DPL(ttype)) { + (void)ipa3_xdci_disconnect(ul_clnt_hdl, true, + ipa3_usb_ctx->qmi_req_id); + ipa3_usb_ctx->qmi_req_id++; + } +disconn_teth: + (void)ipa3_usb_disconnect_teth_prot(teth_prot); +release_prod: + (void)ipa_pm_deactivate_sync( + ipa3_usb_ctx->ttype_ctx[ttype].pm_ctx.hdl); +fail_exit: + return result; +} + +int ipa_usb_xdci_resume(u32 ul_clnt_hdl, u32 dl_clnt_hdl, + enum ipa_usb_teth_prot teth_prot) +{ + int result = -EFAULT; + enum ipa3_usb_state prev_state; + unsigned long flags; + enum ipa3_usb_transport_type ttype; + struct ipa_ep_cfg_ctrl ep_cfg_ctrl; + + mutex_lock(&ipa3_usb_ctx->general_mutex); + IPA_USB_DBG_LOW("entry\n"); + + if (teth_prot < 0 || teth_prot >= IPA_USB_MAX_TETH_PROT_SIZE) { + IPA_USB_ERR("bad parameters\n"); + result = -EINVAL; + goto bad_params; + } + + ttype = IPA3_USB_GET_TTYPE(teth_prot); + + if (!ipa3_usb_check_legal_op(IPA_USB_OP_RESUME, ttype)) { + IPA_USB_ERR("Illegal operation\n"); + result = -EPERM; + goto bad_params; + } + + spin_lock_irqsave(&ipa3_usb_ctx->state_lock, flags); + prev_state = ipa3_usb_ctx->ttype_ctx[ttype].state; + spin_unlock_irqrestore(&ipa3_usb_ctx->state_lock, flags); + if (prev_state == IPA_USB_SUSPENDED_NO_RWAKEUP) { + result = ipa3_usb_resume_no_remote_wakeup(ul_clnt_hdl, + dl_clnt_hdl, teth_prot); + goto bad_params; + } + + IPA_USB_DBG("Start resume sequence: %s\n", + IPA3_USB_IS_TTYPE_DPL(ttype) ? + "DPL channel" : "Data Tethering channels"); + + /* Change state to RESUME_IN_PROGRESS */ + if (!ipa3_usb_set_state(IPA_USB_RESUME_IN_PROGRESS, false, ttype)) { + IPA_USB_ERR("failed to change state to resume_in_progress\n"); + result = -EFAULT; + goto bad_params; + } + + /* Activate PM */ + result = ipa_pm_activate_sync( + ipa3_usb_ctx->ttype_ctx[ttype].pm_ctx.hdl); + if (result) + goto activate_pm_fail; + + if (ipa3_ctx->ipa_hw_type < IPA_HW_v4_0) { + /* Unsuspend the DL/DPL EP */ + memset(&ep_cfg_ctrl, 0, sizeof(struct ipa_ep_cfg_ctrl)); + ep_cfg_ctrl.ipa_ep_suspend = false; + ipa_cfg_ep_ctrl(dl_clnt_hdl, &ep_cfg_ctrl); + } + + if (!IPA3_USB_IS_TTYPE_DPL(ttype)) { + /* Start UL channel */ + result = ipa3_start_gsi_channel(ul_clnt_hdl); + if (result) { + IPA_USB_ERR("failed to start UL channel\n"); + goto start_ul_fail; + } + } + + /* Start DL/DPL channel */ + result = ipa3_start_gsi_channel(dl_clnt_hdl); + if (result) { + IPA_USB_ERR("failed to start DL/DPL channel\n"); + goto start_dl_fail; + } + + /* Change state to CONNECTED */ + if (!ipa3_usb_set_state(IPA_USB_CONNECTED, false, ttype)) { + IPA_USB_ERR("failed to change state to connected\n"); + result = -EFAULT; + goto state_change_connected_fail; + } + + IPA_USB_DBG_LOW("exit\n"); + mutex_unlock(&ipa3_usb_ctx->general_mutex); + return 0; + +state_change_connected_fail: + result = ipa_stop_gsi_channel(dl_clnt_hdl); + if (result) + IPA_USB_ERR("Error stopping DL/DPL channel: %d\n", + result); +start_dl_fail: + if (!IPA3_USB_IS_TTYPE_DPL(ttype)) { + result = ipa_stop_gsi_channel(ul_clnt_hdl); + if (result) + IPA_USB_ERR("Error stopping UL channel: %d\n", result); + } +start_ul_fail: + ipa_pm_deactivate_sync( + ipa3_usb_ctx->ttype_ctx[ttype].pm_ctx.hdl); +activate_pm_fail: + /* Change state back to prev_state */ + if (!ipa3_usb_set_state(prev_state, true, ttype)) + IPA_USB_ERR("failed to change state back to %s\n", + ipa3_usb_state_to_string(prev_state)); +bad_params: + mutex_unlock(&ipa3_usb_ctx->general_mutex); + return result; +} +EXPORT_SYMBOL(ipa_usb_xdci_resume); + +bool ipa_usb_is_teth_prot_connected(enum ipa_usb_teth_prot usb_teth_prot) +{ + if (ipa3_usb_ctx) + if (ipa3_usb_ctx->teth_prot_ctx[usb_teth_prot].state == IPA_USB_TETH_PROT_CONNECTED) + return true; + return false; +} +EXPORT_SYMBOL(ipa_usb_is_teth_prot_connected); + +static struct ipa_usb_ops usb_ops = { + ipa_usb_init_teth_prot, + ipa_usb_xdci_connect, + ipa_usb_xdci_disconnect, + ipa_usb_deinit_teth_prot, + ipa_usb_xdci_suspend, + ipa_usb_xdci_resume, + ipa_usb_is_teth_prot_connected, +}; + +int ipa3_usb_init(void) +{ + int i; + unsigned long flags; + int res; + struct ipa3_usb_pm_context *pm_ctx; + + pr_info("ipa_usb driver init\n"); + + ipa3_usb_ctx = kzalloc(sizeof(struct ipa3_usb_context), GFP_KERNEL); + if (ipa3_usb_ctx == NULL) { + pr_err(":ipa_usb init failed\n"); + return -ENOMEM; + } + memset(ipa3_usb_ctx, 0, sizeof(struct ipa3_usb_context)); + + for (i = 0; i < IPA_USB_MAX_TETH_PROT_SIZE; i++) + ipa3_usb_ctx->teth_prot_ctx[i].state = + IPA_USB_TETH_PROT_INVALID; + ipa3_usb_ctx->num_init_prot = 0; + init_completion(&ipa3_usb_ctx->dev_ready_comp); + ipa3_usb_ctx->qmi_req_id = 0; + spin_lock_init(&ipa3_usb_ctx->state_lock); + ipa3_usb_ctx->dl_data_pending = false; + mutex_init(&ipa3_usb_ctx->general_mutex); + + /* init PM related members */ + pm_ctx = &ipa3_usb_ctx->ttype_ctx[IPA_USB_TRANSPORT_TETH].pm_ctx; + pm_ctx->hdl = ~0; + pm_ctx->remote_wakeup_work = &ipa3_usb_notify_remote_wakeup_work; + pm_ctx = &ipa3_usb_ctx->ttype_ctx[IPA_USB_TRANSPORT_TETH_2].pm_ctx; + pm_ctx->hdl = ~0; + pm_ctx->remote_wakeup_work = &ipa3_usb_notify_remote_wakeup_work; + pm_ctx = &ipa3_usb_ctx->ttype_ctx[IPA_USB_TRANSPORT_DPL].pm_ctx; + pm_ctx->hdl = ~0; + pm_ctx->remote_wakeup_work = &ipa3_usb_dpl_notify_remote_wakeup_work; + + for (i = 0; i < IPA_USB_TRANSPORT_MAX; i++) + ipa3_usb_ctx->ttype_ctx[i].user_data = NULL; + + spin_lock_irqsave(&ipa3_usb_ctx->state_lock, flags); + for (i = 0; i < IPA_USB_TRANSPORT_MAX; i++) + ipa3_usb_ctx->ttype_ctx[i].state = IPA_USB_INVALID; + + spin_unlock_irqrestore(&ipa3_usb_ctx->state_lock, flags); + + ipa3_usb_ctx->wq = create_singlethread_workqueue("ipa_usb_wq"); + if (!ipa3_usb_ctx->wq) { + pr_err("failed to create workqueue\n"); + res = -EFAULT; + goto ipa_usb_workqueue_fail; + } + + ipa_usb_debugfs_init(); + + res = ipa_register_ipa_ready_cb(ipa_ready_callback, (void *)&usb_ops); + if (res < 0) { + pr_err("failed to register USB ops CB\n"); + goto ipa_usb_workqueue_fail; + } + pr_err("ILIA: ipa_ready_callback registered\n"); + + pr_info("exit: IPA_USB init success!\n"); + + return 0; + +ipa_usb_workqueue_fail: + pr_err("init failed (%d)\n", -res); + kfree(ipa3_usb_ctx); + return res; +} + +void ipa3_usb_exit(void) +{ + IPA_USB_DBG_LOW("IPA_USB exit\n"); + + /* + * Deregister for xdci lock/unlock callback from ipa core driver. + * As per use case, only deregister for IPA_CONS end point for now. + * If needed we can include the same for IPA_PROD ep. + * For IPA_USB_DIAG/DPL config there will not be any UL config. + */ + ipa3_deregister_client_callback(IPA_CLIENT_USB_PROD); + +#if IS_ENABLED(CONFIG_DEEPSLEEP) + ipa_exit_callback(); +#endif + ipa_usb_debugfs_remove(); + kfree(ipa3_usb_ctx); +} diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_clients/ipa_wdi3.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_clients/ipa_wdi3.c new file mode 100644 index 0000000000..4a2a94b271 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_clients/ipa_wdi3.c @@ -0,0 +1,1991 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. + * + * Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ipa_wdi3.h" +#include +#include +#include +#include +#include "ipa_common_i.h" +#include "ipa_pm.h" +#include "ipa_i.h" + +#define OFFLOAD_DRV_NAME "ipa_wdi" +#define IPA_WDI_DBG(fmt, args...) \ + do { \ + pr_debug(OFFLOAD_DRV_NAME " %s:%d " fmt, \ + __func__, __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf(), \ + OFFLOAD_DRV_NAME " %s:%d " fmt, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf_low(), \ + OFFLOAD_DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) + +#define IPA_WDI_DBG_LOW(fmt, args...) \ + do { \ + pr_debug(OFFLOAD_DRV_NAME " %s:%d " fmt, \ + __func__, __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf_low(), \ + OFFLOAD_DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) + +#define IPA_WDI_ERR(fmt, args...) \ + do { \ + pr_err(OFFLOAD_DRV_NAME " %s:%d " fmt, \ + __func__, __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf(), \ + OFFLOAD_DRV_NAME " %s:%d " fmt, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf_low(), \ + OFFLOAD_DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) + +#define IPA_CLIENT_IS_WLAN0_INSTANCE(inst_id) \ + (inst_id == 0 || inst_id == -1) +#define IPA_CLIENT_IS_WLAN1_INSTANCE(inst_id) \ + (inst_id == 1) +#define DEFAULT_INSTANCE_ID (-1) +#define INVALID_INSTANCE_ID (-2) + +/** + * Time delay value for delayed queue. + */ +#define QUEUE_DELAY_TIME 100 + +/** + * No. of filters reserving at wlan for IPA-XR usecase. + */ +#define NO_OF_FILTERS 2 +#define IPA_WDI_FLT_RSRV_TIMEOUT_MS 200 + +struct ipa_wdi_intf_info { + char netdev_name[IPA_RESOURCE_NAME_MAX]; + u8 hdr_len; + u32 partial_hdr_hdl[IPA_IP_MAX]; + struct list_head link; +}; +struct ipa_wdi_opt_dpath_info { + ipa_wdi_opt_dpath_flt_rsrv_cb flt_rsrv_cb; + ipa_wdi_opt_dpath_flt_rsrv_rel_cb flt_rsrv_rel_cb; + ipa_wdi_opt_dpath_flt_add_cb flt_add_cb; + ipa_wdi_opt_dpath_flt_rem_cb flt_rem_cb; + u32 q6_rtng_table_index; + u32 hdr_len; + atomic_t rsrv_req; + atomic_t is_opt_dp_cb_registered; + atomic_t is_xr_opt_dp_cb_registered; + void *priv; + int ipa_ep_idx_tx, ipa_ep_idx_rx; + u32 ipa_pm_hdl; +}; + +struct ipa_wdi_context { + struct list_head head_intf_list; + struct completion wdi_completion; + struct mutex lock; + enum ipa_wdi_version wdi_version; + u8 is_smmu_enabled; + u32 tx_pipe_hdl; + u32 rx_pipe_hdl; + u8 num_sys_pipe_needed; + bool is_tx1_used; + u32 sys_pipe_hdl[IPA_WDI_MAX_SUPPORTED_SYS_PIPE]; + u32 ipa_pm_hdl; + int inst_id; +#ifdef IPA_WAN_MSG_IPv6_ADDR_GW_LEN + ipa_wdi_meter_notifier_cb wdi_notify; +#endif +}; + +struct ipa_wdi_opt_dpath_add_flt_handle { + uint64_t filter_handle; +}; + +struct ipa_wdi_opt_dpath_add_flt_handle add_flt_hndl[MAX_STREAMS]; + +/** + * opt_dpath_info contains fn callbacks which are set by WLAN context and + * accessed by QMI context. To avoid race condition between these 2, + * callback info has to be mainitained as a separate global variable, + * outside of wdi context + * + */ + +struct ipa_wdi_opt_dpath_info opt_dpath_info[IPA_WDI_INST_MAX]; + + +static struct ipa_wdi_context *ipa_wdi_ctx_list[IPA_WDI_INST_MAX]; + +/** + * function to Assign Handle for instance + * + * Note: If it is called for Old API then + * max one handle is allowed. + * + * @Return handle on success, negative on failure + */ +static int assign_hdl_for_inst(int inst_id) +{ + int hdl; + + IPA_WDI_DBG("Assigning handle for instance id %d\n", inst_id); + if (inst_id <= INVALID_INSTANCE_ID) { + IPA_WDI_ERR("Invalid instance id %d\n", inst_id); + return -EINVAL; + } + else if (ipa_wdi_ctx_list[0] && (inst_id == DEFAULT_INSTANCE_ID || + ipa_wdi_ctx_list[0]->inst_id == DEFAULT_INSTANCE_ID)) { + IPA_WDI_ERR("Invalid instance id %d\n", inst_id); + return -EINVAL; + } + else { + for (hdl = 0; hdl < IPA_WDI_INST_MAX; hdl++) { + if (!ipa_wdi_ctx_list[hdl]) + break; + } + } + if (hdl == IPA_WDI_INST_MAX) { + IPA_WDI_ERR("Already Maximum Instance Registered\n"); + return -EINVAL; + } + + return hdl; +} + +int ipa_get_wdi_version(void) +{ + if (ipa_wdi_ctx_list[0]) + return ipa_wdi_ctx_list[0]->wdi_version; + /* default version is IPA_WDI_3 */ + return IPA_WDI_3; +} +EXPORT_SYMBOL(ipa_get_wdi_version); + +bool ipa_wdi_is_tx1_used(void) +{ + if (ipa_wdi_ctx_list[0]) + return ipa_wdi_ctx_list[0]->is_tx1_used; + return 0; +} +EXPORT_SYMBOL(ipa_wdi_is_tx1_used); + +static void ipa_wdi_pm_cb(void *p, enum ipa_pm_cb_event event) +{ + IPA_WDI_DBG("received pm event %d\n", event); +} + +static int ipa_wdi_commit_partial_hdr( + struct ipa_ioc_add_hdr *hdr, + const char *netdev_name, + struct ipa_wdi_hdr_info *hdr_info) +{ + int i; + + if (!hdr || !hdr_info || !netdev_name) { + IPA_WDI_ERR("Invalid input\n"); + return -EINVAL; + } + + hdr->commit = 0; + hdr->num_hdrs = 2; + + snprintf(hdr->hdr[0].name, sizeof(hdr->hdr[0].name), + "%s_ipv4", netdev_name); + snprintf(hdr->hdr[1].name, sizeof(hdr->hdr[1].name), + "%s_ipv6", netdev_name); + for (i = IPA_IP_v4; i < IPA_IP_MAX; i++) { + hdr->hdr[i].hdr_len = hdr_info[i].hdr_len; + memcpy(hdr->hdr[i].hdr, hdr_info[i].hdr, hdr->hdr[i].hdr_len); + hdr->hdr[i].type = hdr_info[i].hdr_type; + hdr->hdr[i].is_partial = 1; + hdr->hdr[i].is_eth2_ofst_valid = 1; + hdr->hdr[i].eth2_ofst = hdr_info[i].dst_mac_addr_offset; + } + + if (ipa_add_hdr(hdr)) { + IPA_WDI_ERR("fail to add partial headers\n"); + return -EFAULT; + } + + return 0; +} + +/** + * function to know the WDI capabilities + * + * Note: Should not be called from atomic context and only + * after checking IPA readiness using ipa_register_ipa_ready_cb() + * + * @Return 0 on success, negative on failure + */ +int ipa_wdi_get_capabilities( + struct ipa_wdi_capabilities_out_params *out) +{ + if (out == NULL) { + IPA_WDI_ERR("invalid params out=%pK\n", out); + return -EINVAL; + } + + out->num_of_instances = IPA_WDI_INST_MAX; + IPA_WDI_DBG("Wdi Capability: %d\n", out->num_of_instances); + return 0; +} +EXPORT_SYMBOL(ipa_wdi_get_capabilities); + +/** + * function to init WDI IPA offload data path + * + * Note: Should not be called from atomic context and only + * after checking IPA readiness using ipa_register_ipa_ready_cb() + * + * @Return 0 on success, negative on failure + */ +int ipa_wdi_init_per_inst(struct ipa_wdi_init_in_params *in, + struct ipa_wdi_init_out_params *out) +{ + struct ipa_wdi_uc_ready_params uc_ready_params; + struct ipa_smmu_in_params smmu_in; + struct ipa_smmu_out_params smmu_out; + int hdl; + + if (!(in && out)) { + IPA_WDI_ERR("empty parameters. in=%pK out=%pK\n", in, out); + return -EINVAL; + } + + if (in->wdi_version > IPA_WDI_3_V2 || in->wdi_version < IPA_WDI_1) { + IPA_WDI_ERR("wrong wdi version: %d\n", in->wdi_version); + return -EFAULT; + } + + hdl = assign_hdl_for_inst(in->inst_id); + if (hdl < 0) { + IPA_WDI_ERR("Error assigning hdl\n"); + return hdl; + } + + IPA_WDI_DBG("Assigned Handle %d\n",hdl); + ipa_wdi_ctx_list[hdl] = kzalloc(sizeof(struct ipa_wdi_context), GFP_KERNEL); + if (ipa_wdi_ctx_list[hdl] == NULL) { + IPA_WDI_ERR("fail to alloc wdi ctx\n"); + return -ENOMEM; + } + mutex_init(&ipa_wdi_ctx_list[hdl]->lock); + init_completion(&ipa_wdi_ctx_list[hdl]->wdi_completion); + INIT_LIST_HEAD(&ipa_wdi_ctx_list[hdl]->head_intf_list); + + ipa_wdi_ctx_list[hdl]->inst_id = in->inst_id; + ipa_wdi_ctx_list[hdl]->wdi_version = in->wdi_version; + opt_dpath_info[hdl].priv = in->priv; + uc_ready_params.notify = in->notify; + uc_ready_params.priv = in->priv; + + if (ipa3_uc_reg_rdyCB(&uc_ready_params) != 0) { + mutex_destroy(&ipa_wdi_ctx_list[hdl]->lock); + kfree(ipa_wdi_ctx_list[hdl]); + ipa_wdi_ctx_list[hdl] = NULL; + return -EFAULT; + } + + out->is_uC_ready = uc_ready_params.is_uC_ready; + + if (IPA_CLIENT_IS_WLAN0_INSTANCE(ipa_wdi_ctx_list[hdl]->inst_id)) + smmu_in.smmu_client = IPA_SMMU_WLAN_CLIENT; + else + smmu_in.smmu_client = IPA_SMMU_WLAN1_CLIENT; + + if (ipa_get_smmu_params(&smmu_in, &smmu_out)) + out->is_smmu_enabled = false; + else + out->is_smmu_enabled = smmu_out.smmu_enable; + + ipa_wdi_ctx_list[hdl]->is_smmu_enabled = out->is_smmu_enabled; + + if (IPA_WDI2_OVER_GSI() || (in->wdi_version >= IPA_WDI_3)) + out->is_over_gsi = true; + else + out->is_over_gsi = false; + + if (ipa3_ctx->ipa_wdi_opt_dpath) + out->opt_wdi_dpath = true; + else + out->opt_wdi_dpath = false; + + IPA_WDI_DBG("opt_wdi_dpath enabled: %d, hdl: %d\n", out->opt_wdi_dpath, hdl); + + out->hdl = hdl; + + return 0; +} +EXPORT_SYMBOL(ipa_wdi_init_per_inst); + +/** + * function to register interface + * + * Note: Should not be called from atomic context + * + * @Return 0 on success, negative on failure + */ +int ipa_wdi_reg_intf_per_inst( + struct ipa_wdi_reg_intf_in_params *in) +{ + struct ipa_ioc_add_hdr *hdr; + struct ipa_wdi_intf_info *new_intf; + struct ipa_wdi_intf_info *entry; + struct ipa_tx_intf tx; + struct ipa_rx_intf rx; + struct ipa_ioc_tx_intf_prop tx_prop[2]; + struct ipa_ioc_rx_intf_prop rx_prop[2]; + u32 len; + int ret = 0; + + if (in == NULL) { + IPA_WDI_ERR("invalid params in=%pK\n", in); + return -EINVAL; + } + + if (in->hdl < 0 || in->hdl >=IPA_WDI_INST_MAX) { + IPA_WDI_ERR("Invalid handle =%d\n", in->hdl); + return -EINVAL; + } + + if (!ipa_wdi_ctx_list[in->hdl]) { + IPA_WDI_ERR("wdi ctx is not initialized\n"); + return -EPERM; + } + + if (ipa_wdi_ctx_list[in->hdl]->wdi_version >= IPA_WDI_1 && + ipa_wdi_ctx_list[in->hdl]->wdi_version < IPA_WDI_3 && + in->hdl > 0) { + IPA_WDI_ERR("More than one instance not supported for WDI ver = %d\n", + ipa_wdi_ctx_list[in->hdl]->wdi_version); + return -EPERM; + } + + IPA_WDI_DBG("register interface for netdev %s\n", + in->netdev_name); + + mutex_lock(&ipa_wdi_ctx_list[in->hdl]->lock); + list_for_each_entry(entry, &ipa_wdi_ctx_list[in->hdl]->head_intf_list, link) + if (strcmp(entry->netdev_name, in->netdev_name) == 0) { + IPA_WDI_DBG("intf was added before.\n"); + mutex_unlock(&ipa_wdi_ctx_list[in->hdl]->lock); + return 0; + } + + if (ipa3_ctx->ipa_wdi3_over_gsi && + in->is_tx1_used && !ipa3_ctx->is_wdi3_tx1_needed) { + IPA_WDI_DBG( + "tx1 reg intr not sprtd, adng it to default pipe\n"); + } + + IPA_WDI_DBG("intf was not added before, proceed.\n"); + new_intf = kzalloc(sizeof(*new_intf), GFP_KERNEL); + if (new_intf == NULL) { + IPA_WDI_ERR("fail to alloc new intf\n"); + mutex_unlock(&ipa_wdi_ctx_list[in->hdl]->lock); + return -ENOMEM; + } + + INIT_LIST_HEAD(&new_intf->link); + strlcpy(new_intf->netdev_name, in->netdev_name, + sizeof(new_intf->netdev_name)); + new_intf->hdr_len = in->hdr_info[0].hdr_len; + if (ipa3_ctx->ipa_wdi_opt_dpath) + opt_dpath_info[in->hdl].hdr_len = + new_intf->hdr_len; + /* add partial header */ + len = sizeof(struct ipa_ioc_add_hdr) + 2 * sizeof(struct ipa_hdr_add); + hdr = kzalloc(len, GFP_KERNEL); + if (hdr == NULL) { + IPA_WDI_ERR("fail to alloc %d bytes\n", len); + ret = -EFAULT; + goto fail_alloc_hdr; + } + + if (ipa_wdi_commit_partial_hdr(hdr, in->netdev_name, in->hdr_info)) { + IPA_WDI_ERR("fail to commit partial headers\n"); + ret = -EFAULT; + goto fail_commit_hdr; + } + + new_intf->partial_hdr_hdl[IPA_IP_v4] = hdr->hdr[IPA_IP_v4].hdr_hdl; + new_intf->partial_hdr_hdl[IPA_IP_v6] = hdr->hdr[IPA_IP_v6].hdr_hdl; + IPA_WDI_DBG("IPv4 hdr hdl: %d IPv6 hdr hdl: %d\n", + hdr->hdr[IPA_IP_v4].hdr_hdl, hdr->hdr[IPA_IP_v6].hdr_hdl); + + /* populate tx prop */ + tx.num_props = 2; + tx.prop = tx_prop; + IPA_WDI_DBG("Setting tx/rx props\n"); + memset(tx_prop, 0, sizeof(tx_prop)); + tx_prop[0].ip = IPA_IP_v4; + if (ipa3_get_ctx()->ipa_wdi3_over_gsi) { + if (in->is_tx1_used && ipa3_ctx->is_wdi3_tx1_needed) + tx_prop[0].dst_pipe = IPA_CLIENT_WLAN2_CONS1; + else if (IPA_CLIENT_IS_WLAN0_INSTANCE(ipa_wdi_ctx_list[in->hdl]->inst_id)) + tx_prop[0].dst_pipe = IPA_CLIENT_WLAN2_CONS; + else + tx_prop[0].dst_pipe = IPA_CLIENT_WLAN4_CONS; + } + else + tx_prop[0].dst_pipe = IPA_CLIENT_WLAN1_CONS; + tx_prop[0].alt_dst_pipe = in->alt_dst_pipe; + tx_prop[0].hdr_l2_type = in->hdr_info[0].hdr_type; + strlcpy(tx_prop[0].hdr_name, hdr->hdr[IPA_IP_v4].name, + sizeof(tx_prop[0].hdr_name)); + + tx_prop[1].ip = IPA_IP_v6; + if (ipa3_get_ctx()->ipa_wdi3_over_gsi) { + if (in->is_tx1_used && ipa3_ctx->is_wdi3_tx1_needed) + tx_prop[1].dst_pipe = IPA_CLIENT_WLAN2_CONS1; + else if (IPA_CLIENT_IS_WLAN0_INSTANCE(ipa_wdi_ctx_list[in->hdl]->inst_id)) + tx_prop[1].dst_pipe = IPA_CLIENT_WLAN2_CONS; + else + tx_prop[1].dst_pipe = IPA_CLIENT_WLAN4_CONS; + } + else + tx_prop[1].dst_pipe = IPA_CLIENT_WLAN1_CONS; + tx_prop[1].alt_dst_pipe = in->alt_dst_pipe; + tx_prop[1].hdr_l2_type = in->hdr_info[1].hdr_type; + strlcpy(tx_prop[1].hdr_name, hdr->hdr[IPA_IP_v6].name, + sizeof(tx_prop[1].hdr_name)); + + /* populate rx prop */ + rx.num_props = 2; + rx.prop = rx_prop; + memset(rx_prop, 0, sizeof(rx_prop)); + rx_prop[0].ip = IPA_IP_v4; + if (ipa_wdi_ctx_list[in->hdl]->wdi_version >= IPA_WDI_3) { + if (IPA_CLIENT_IS_WLAN0_INSTANCE(ipa_wdi_ctx_list[in->hdl]->inst_id)) + rx_prop[0].src_pipe = IPA_CLIENT_WLAN2_PROD; + else + rx_prop[0].src_pipe = IPA_CLIENT_WLAN3_PROD; + } else { + rx_prop[0].src_pipe = IPA_CLIENT_WLAN1_PROD; + } + rx_prop[0].hdr_l2_type = in->hdr_info[0].hdr_type; + if (in->is_meta_data_valid) { + rx_prop[0].attrib.attrib_mask |= IPA_FLT_META_DATA; + rx_prop[0].attrib.meta_data = in->meta_data; + rx_prop[0].attrib.meta_data_mask = in->meta_data_mask; + } + + rx_prop[1].ip = IPA_IP_v6; + if (ipa_wdi_ctx_list[in->hdl]->wdi_version >= IPA_WDI_3) { + if (IPA_CLIENT_IS_WLAN0_INSTANCE(ipa_wdi_ctx_list[in->hdl]->inst_id)) + rx_prop[1].src_pipe = IPA_CLIENT_WLAN2_PROD; + else + rx_prop[1].src_pipe = IPA_CLIENT_WLAN3_PROD; + } else { + rx_prop[1].src_pipe = IPA_CLIENT_WLAN1_PROD; + } + rx_prop[1].hdr_l2_type = in->hdr_info[1].hdr_type; + if (in->is_meta_data_valid) { + rx_prop[1].attrib.attrib_mask |= IPA_FLT_META_DATA; + rx_prop[1].attrib.meta_data = in->meta_data; + rx_prop[1].attrib.meta_data_mask = in->meta_data_mask; + } + if (ipa_register_intf(in->netdev_name, &tx, &rx)) { + IPA_WDI_ERR("fail to add interface prop\n"); + ret = -EFAULT; + } + IPA_WDI_DBG("Done Register Interface\n"); + list_add(&new_intf->link, &ipa_wdi_ctx_list[in->hdl]->head_intf_list); + init_completion(&ipa_wdi_ctx_list[in->hdl]->wdi_completion); + + kfree(hdr); + mutex_unlock(&ipa_wdi_ctx_list[in->hdl]->lock); + return 0; + +fail_commit_hdr: + kfree(hdr); +fail_alloc_hdr: + kfree(new_intf); + mutex_unlock(&ipa_wdi_ctx_list[in->hdl]->lock); + return ret; +} +EXPORT_SYMBOL(ipa_wdi_reg_intf_per_inst); + +/** + * function to connect pipes + * + * @in: [in] input parameters from client + * @out: [out] output params to client + * + * Note: Should not be called from atomic context + * + * @Return 0 on success, negative on failure + */ +int ipa_wdi_conn_pipes_per_inst(struct ipa_wdi_conn_in_params *in, + struct ipa_wdi_conn_out_params *out) +{ + int i, j, ret = 0; + struct ipa_pm_register_params pm_params; + struct ipa_wdi_in_params in_tx; + struct ipa_wdi_in_params in_rx; + struct ipa_wdi_out_params out_tx; + struct ipa_wdi_out_params out_rx; + int ipa_ep_idx_tx1 = IPA_EP_NOT_ALLOCATED; + + if (!(in && out)) { + IPA_WDI_ERR("empty parameters. in=%pK out=%pK\n", in, out); + return -EINVAL; + } + + if (in->hdl < 0 || in->hdl >= IPA_WDI_INST_MAX) { + IPA_WDI_ERR("Invalid handle %d \n", in->hdl); + return -EINVAL; + } + + if (!ipa_wdi_ctx_list[in->hdl]) { + IPA_WDI_ERR("wdi ctx is not initialized\n"); + return -EPERM; + } + + if (ipa_wdi_ctx_list[in->hdl]->wdi_version >= IPA_WDI_1 && + ipa_wdi_ctx_list[in->hdl]->wdi_version < IPA_WDI_3 && + in->hdl > 0) { + IPA_WDI_ERR("More than one instance not supported for WDI ver = %d\n", + ipa_wdi_ctx_list[in->hdl]->wdi_version); + return -EPERM; + } + + if (in->num_sys_pipe_needed > IPA_WDI_MAX_SUPPORTED_SYS_PIPE) { + IPA_WDI_ERR("ipa can only support up to %d sys pipe\n", + IPA_WDI_MAX_SUPPORTED_SYS_PIPE); + return -EINVAL; + } + ipa_wdi_ctx_list[in->hdl]->num_sys_pipe_needed = in->num_sys_pipe_needed; + IPA_WDI_DBG("number of sys pipe %d\n", in->num_sys_pipe_needed); + ipa_ep_idx_tx1 = ipa_get_ep_mapping(IPA_CLIENT_WLAN2_CONS1); + if ((ipa_ep_idx_tx1 != IPA_EP_NOT_ALLOCATED) && + (ipa_ep_idx_tx1 < IPA3_MAX_NUM_PIPES) && + ipa3_ctx->is_wdi3_tx1_needed) { + ipa_wdi_ctx_list[in->hdl]->is_tx1_used = in->is_tx1_used; + } else + ipa_wdi_ctx_list[in->hdl]->is_tx1_used = false; + IPA_WDI_DBG("number of sys pipe %d,Tx1 asked=%d,Tx1 supported=%d\n", + in->num_sys_pipe_needed, in->is_tx1_used, + ipa3_ctx->is_wdi3_tx1_needed); + + /* setup sys pipe when needed */ + for (i = 0; i < in->num_sys_pipe_needed; i++) { + ret = ipa_setup_sys_pipe(&in->sys_in[i], + &ipa_wdi_ctx_list[in->hdl]->sys_pipe_hdl[i]); + if (ret) { + IPA_WDI_ERR("fail to setup sys pipe %d\n", i); + ret = -EFAULT; + goto fail_setup_sys_pipe; + } + } + + memset(&pm_params, 0, sizeof(pm_params)); + if (IPA_CLIENT_IS_WLAN0_INSTANCE(ipa_wdi_ctx_list[in->hdl]->inst_id)) + pm_params.name = "wdi"; + else + pm_params.name = "wdi1"; + pm_params.callback = ipa_wdi_pm_cb; + pm_params.user_data = NULL; + pm_params.group = IPA_PM_GROUP_DEFAULT; + if (ipa_pm_register(&pm_params, &ipa_wdi_ctx_list[in->hdl]->ipa_pm_hdl)) { + IPA_WDI_ERR("fail to register ipa pm\n"); + ret = -EFAULT; + goto fail_setup_sys_pipe; + } + IPA_WDI_DBG("PM handle Registered\n"); + opt_dpath_info[in->hdl].ipa_pm_hdl = ipa_wdi_ctx_list[in->hdl]->ipa_pm_hdl; + if (ipa_wdi_ctx_list[in->hdl]->wdi_version >= IPA_WDI_3) { + if (ipa3_conn_wdi3_pipes(in, out, ipa_wdi_ctx_list[in->hdl]->wdi_notify)) { + IPA_WDI_ERR("fail to setup wdi pipes\n"); + ret = -EFAULT; + goto fail_connect_pipe; + } + } else { + memset(&in_tx, 0, sizeof(in_tx)); + memset(&in_rx, 0, sizeof(in_rx)); + memset(&out_tx, 0, sizeof(out_tx)); + memset(&out_rx, 0, sizeof(out_rx)); +#ifdef IPA_WAN_MSG_IPv6_ADDR_GW_LEN + in_rx.wdi_notify = ipa_wdi_ctx_list[in->hdl]->wdi_notify; +#endif + if (in->is_smmu_enabled == false) { + /* firsr setup rx pipe */ + in_rx.sys.ipa_ep_cfg = in->u_rx.rx.ipa_ep_cfg; + in_rx.sys.client = in->u_rx.rx.client; + in_rx.sys.notify = in->notify; + in_rx.sys.priv = in->priv; + in_rx.smmu_enabled = in->is_smmu_enabled; + in_rx.u.ul.rdy_ring_base_pa = + in->u_rx.rx.transfer_ring_base_pa; + in_rx.u.ul.rdy_ring_size = + in->u_rx.rx.transfer_ring_size; + in_rx.u.ul.rdy_ring_rp_pa = + in->u_rx.rx.transfer_ring_doorbell_pa; + in_rx.u.ul.rdy_comp_ring_base_pa = + in->u_rx.rx.event_ring_base_pa; + in_rx.u.ul.rdy_comp_ring_wp_pa = + in->u_rx.rx.event_ring_doorbell_pa; + in_rx.u.ul.rdy_comp_ring_size = + in->u_rx.rx.event_ring_size; + in_rx.u.ul.is_txr_rn_db_pcie_addr = + in->u_rx.rx.is_txr_rn_db_pcie_addr; + in_rx.u.ul.is_evt_rn_db_pcie_addr = + in->u_rx.rx.is_evt_rn_db_pcie_addr; + if (ipa_connect_wdi_pipe(&in_rx, &out_rx)) { + IPA_WDI_ERR("fail to setup rx pipe\n"); + ret = -EFAULT; + goto fail_connect_pipe; + } + ipa_wdi_ctx_list[in->hdl]->rx_pipe_hdl = out_rx.clnt_hdl; + out->rx_uc_db_pa = out_rx.uc_door_bell_pa; + IPA_WDI_DBG("rx uc db pa: 0x%pad\n", &out->rx_uc_db_pa); + + /* then setup tx pipe */ + in_tx.sys.ipa_ep_cfg = in->u_tx.tx.ipa_ep_cfg; + in_tx.sys.client = in->u_tx.tx.client; + in_tx.smmu_enabled = in->is_smmu_enabled; + in_tx.u.dl.comp_ring_base_pa = + in->u_tx.tx.transfer_ring_base_pa; + in_tx.u.dl.comp_ring_size = + in->u_tx.tx.transfer_ring_size; + in_tx.u.dl.ce_ring_base_pa = + in->u_tx.tx.event_ring_base_pa; + in_tx.u.dl.ce_door_bell_pa = + in->u_tx.tx.event_ring_doorbell_pa; + in_tx.u.dl.ce_ring_size = + in->u_tx.tx.event_ring_size; + in_tx.u.dl.num_tx_buffers = + in->u_tx.tx.num_pkt_buffers; + in_tx.u.dl.is_txr_rn_db_pcie_addr = + in->u_tx.tx.is_txr_rn_db_pcie_addr; + in_tx.u.dl.is_evt_rn_db_pcie_addr = + in->u_tx.tx.is_evt_rn_db_pcie_addr; + if (ipa_connect_wdi_pipe(&in_tx, &out_tx)) { + IPA_WDI_ERR("fail to setup tx pipe\n"); + ret = -EFAULT; + goto fail; + } + ipa_wdi_ctx_list[in->hdl]->tx_pipe_hdl = out_tx.clnt_hdl; + out->tx_uc_db_pa = out_tx.uc_door_bell_pa; + IPA_WDI_DBG("tx uc db pa: 0x%pad\n", &out->tx_uc_db_pa); + } else { /* smmu is enabled */ + /* firsr setup rx pipe */ + in_rx.sys.ipa_ep_cfg = in->u_rx.rx_smmu.ipa_ep_cfg; + in_rx.sys.client = in->u_rx.rx_smmu.client; + in_rx.sys.notify = in->notify; + in_rx.sys.priv = in->priv; + in_rx.smmu_enabled = in->is_smmu_enabled; + in_rx.u.ul_smmu.rdy_ring = + in->u_rx.rx_smmu.transfer_ring_base; + in_rx.u.ul_smmu.rdy_ring_size = + in->u_rx.rx_smmu.transfer_ring_size; + in_rx.u.ul_smmu.rdy_ring_rp_pa = + in->u_rx.rx_smmu.transfer_ring_doorbell_pa; + in_rx.u.ul_smmu.rdy_comp_ring = + in->u_rx.rx_smmu.event_ring_base; + in_rx.u.ul_smmu.rdy_comp_ring_wp_pa = + in->u_rx.rx_smmu.event_ring_doorbell_pa; + in_rx.u.ul_smmu.rdy_comp_ring_size = + in->u_rx.rx_smmu.event_ring_size; + in_rx.u.ul_smmu.is_txr_rn_db_pcie_addr = + in->u_rx.rx_smmu.is_txr_rn_db_pcie_addr; + in_rx.u.ul_smmu.is_evt_rn_db_pcie_addr = + in->u_rx.rx_smmu.is_evt_rn_db_pcie_addr; + if (ipa_connect_wdi_pipe(&in_rx, &out_rx)) { + IPA_WDI_ERR("fail to setup rx pipe\n"); + ret = -EFAULT; + goto fail_connect_pipe; + } + ipa_wdi_ctx_list[in->hdl]->rx_pipe_hdl = out_rx.clnt_hdl; + out->rx_uc_db_pa = out_rx.uc_door_bell_pa; + IPA_WDI_DBG("rx uc db pa: 0x%pad\n", &out->rx_uc_db_pa); + + /* then setup tx pipe */ + in_tx.sys.ipa_ep_cfg = in->u_tx.tx_smmu.ipa_ep_cfg; + in_tx.sys.client = in->u_tx.tx_smmu.client; + in_tx.smmu_enabled = in->is_smmu_enabled; + in_tx.u.dl_smmu.comp_ring = + in->u_tx.tx_smmu.transfer_ring_base; + in_tx.u.dl_smmu.comp_ring_size = + in->u_tx.tx_smmu.transfer_ring_size; + in_tx.u.dl_smmu.ce_ring = + in->u_tx.tx_smmu.event_ring_base; + in_tx.u.dl_smmu.ce_door_bell_pa = + in->u_tx.tx_smmu.event_ring_doorbell_pa; + in_tx.u.dl_smmu.ce_ring_size = + in->u_tx.tx_smmu.event_ring_size; + in_tx.u.dl_smmu.num_tx_buffers = + in->u_tx.tx_smmu.num_pkt_buffers; + in_tx.u.dl_smmu.is_txr_rn_db_pcie_addr = + in->u_tx.tx_smmu.is_txr_rn_db_pcie_addr; + in_tx.u.dl_smmu.is_evt_rn_db_pcie_addr = + in->u_tx.tx_smmu.is_evt_rn_db_pcie_addr; + if (ipa_connect_wdi_pipe(&in_tx, &out_tx)) { + IPA_WDI_ERR("fail to setup tx pipe\n"); + ret = -EFAULT; + goto fail; + } + ipa_wdi_ctx_list[in->hdl]->tx_pipe_hdl = out_tx.clnt_hdl; + out->tx_uc_db_pa = out_tx.uc_door_bell_pa; + ret = ipa_pm_associate_ipa_cons_to_client(ipa_wdi_ctx_list[in->hdl]->ipa_pm_hdl, + in_tx.sys.client); + if (ret) { + IPA_WDI_ERR("fail to associate cons with PM %d\n", ret); + goto fail; + } + IPA_WDI_DBG("tx uc db pa: 0x%pad\n", &out->tx_uc_db_pa); + } + IPA_WDI_DBG("conn pipes done\n"); + } + if (ipa3_ctx->ipa_wdi_opt_dpath) { + if (ipa_wdi_ctx_list[in->hdl]->wdi_version >= IPA_WDI_3) { + if (IPA_CLIENT_IS_WLAN0_INSTANCE(ipa_wdi_ctx_list[in->hdl]->inst_id)) { + opt_dpath_info[in->hdl].ipa_ep_idx_rx = + ipa_get_ep_mapping(IPA_CLIENT_WLAN2_PROD); + opt_dpath_info[in->hdl].ipa_ep_idx_tx = + ipa_get_ep_mapping(IPA_CLIENT_WLAN2_CONS); + } else { + opt_dpath_info[in->hdl].ipa_ep_idx_rx = + ipa_get_ep_mapping(IPA_CLIENT_WLAN3_PROD); + opt_dpath_info[in->hdl].ipa_ep_idx_tx = + ipa_get_ep_mapping(IPA_CLIENT_WLAN4_CONS); + } + } else { + opt_dpath_info[in->hdl].ipa_ep_idx_rx = + ipa_get_ep_mapping(IPA_CLIENT_WLAN1_PROD); + opt_dpath_info[in->hdl].ipa_ep_idx_tx = + ipa_get_ep_mapping(IPA_CLIENT_WLAN1_CONS); + } + } + + return 0; + +fail: + ipa_disconnect_wdi_pipe(ipa_wdi_ctx_list[in->hdl]->rx_pipe_hdl); +fail_connect_pipe: + ipa_pm_deregister(ipa_wdi_ctx_list[in->hdl]->ipa_pm_hdl); + +fail_setup_sys_pipe: + for (j = 0; j < i; j++) + ipa_teardown_sys_pipe(ipa_wdi_ctx_list[in->hdl]->sys_pipe_hdl[j]); + return ret; +} +EXPORT_SYMBOL(ipa_wdi_conn_pipes_per_inst); + +/** + * function to enable IPA offload data path + * + * @hdl: hdl to wdi client + * Note: Should not be called from atomic context + * + * Returns: 0 on success, negative on failure + */ +int ipa_wdi_enable_pipes_per_inst(ipa_wdi_hdl_t hdl) +{ + int ret; + int ipa_ep_idx_tx, ipa_ep_idx_rx; + int ipa_ep_idx_tx1 = IPA_EP_NOT_ALLOCATED; + + if (hdl < 0 || hdl >= IPA_WDI_INST_MAX) { + IPA_WDI_ERR("Invalid handle %d\n", hdl); + } + + if (!ipa_wdi_ctx_list[hdl]) { + IPA_WDI_ERR("wdi ctx is not initialized.\n"); + return -EPERM; + } + + if (ipa_wdi_ctx_list[hdl]->wdi_version >= IPA_WDI_1 && + ipa_wdi_ctx_list[hdl]->wdi_version < IPA_WDI_3 && + hdl > 0) { + IPA_WDI_ERR("More than one instance not supported for WDI ver = %d\n", + ipa_wdi_ctx_list[hdl]->wdi_version); + return -EPERM; + } + + if (ipa_wdi_ctx_list[hdl]->wdi_version >= IPA_WDI_3) { + if (IPA_CLIENT_IS_WLAN0_INSTANCE(ipa_wdi_ctx_list[hdl]->inst_id)) { + ipa_ep_idx_rx = ipa_get_ep_mapping(IPA_CLIENT_WLAN2_PROD); + ipa_ep_idx_tx = ipa_get_ep_mapping(IPA_CLIENT_WLAN2_CONS); + } else { + ipa_ep_idx_rx = ipa_get_ep_mapping(IPA_CLIENT_WLAN3_PROD); + ipa_ep_idx_tx = ipa_get_ep_mapping(IPA_CLIENT_WLAN4_CONS); + } + if (ipa_wdi_ctx_list[hdl]->is_tx1_used) + ipa_ep_idx_tx1 = + ipa_get_ep_mapping(IPA_CLIENT_WLAN2_CONS1); + } else { + ipa_ep_idx_rx = ipa_get_ep_mapping(IPA_CLIENT_WLAN1_PROD); + ipa_ep_idx_tx = ipa_get_ep_mapping(IPA_CLIENT_WLAN1_CONS); + } + + if (ipa_ep_idx_tx <= 0 || ipa_ep_idx_rx <= 0) + return -EFAULT; + ret = ipa_pm_activate_sync(ipa_wdi_ctx_list[hdl]->ipa_pm_hdl); + if (ret) { + IPA_WDI_ERR("fail to activate ipa pm\n"); + return -EFAULT; + } + IPA_WDI_DBG("Enable WDI pipes\n"); + if (ipa_wdi_ctx_list[hdl]->wdi_version >= IPA_WDI_3) { + if (ipa3_enable_wdi3_pipes( + ipa_ep_idx_tx, ipa_ep_idx_rx, ipa_ep_idx_tx1)) { + IPA_WDI_ERR("fail to enable wdi pipes\n"); + return -EFAULT; + } + } else { + if ((ipa_wdi_ctx_list[hdl]->tx_pipe_hdl >= IPA3_MAX_NUM_PIPES) || + (ipa_wdi_ctx_list[hdl]->tx_pipe_hdl < 0) || + (ipa_wdi_ctx_list[hdl]->rx_pipe_hdl >= IPA3_MAX_NUM_PIPES) || + (ipa_wdi_ctx_list[hdl]->rx_pipe_hdl < 0)) { + IPA_WDI_ERR("pipe handle not valid\n"); + return -EFAULT; + } + if (ipa_enable_wdi_pipe(ipa_wdi_ctx_list[hdl]->tx_pipe_hdl)) { + IPA_WDI_ERR("fail to enable wdi tx pipe\n"); + return -EFAULT; + } + if (ipa_resume_wdi_pipe(ipa_wdi_ctx_list[hdl]->tx_pipe_hdl)) { + IPA_WDI_ERR("fail to resume wdi tx pipe\n"); + return -EFAULT; + } + if (ipa_enable_wdi_pipe(ipa_wdi_ctx_list[hdl]->rx_pipe_hdl)) { + IPA_WDI_ERR("fail to enable wdi rx pipe\n"); + return -EFAULT; + } + if (ipa_resume_wdi_pipe(ipa_wdi_ctx_list[hdl]->rx_pipe_hdl)) { + IPA_WDI_ERR("fail to resume wdi rx pipe\n"); + return -EFAULT; + } + } + + if (ipa3_ctx->ipa_wdi_opt_dpath){ + ret = ipa_pm_deferred_deactivate(ipa_wdi_ctx_list[hdl]->ipa_pm_hdl); + if (ret) { + IPA_WDI_DBG("fail to deactivate ipa pm\n"); + return -EFAULT; + } + } + + return 0; +} +EXPORT_SYMBOL(ipa_wdi_enable_pipes_per_inst); + +/** + * set IPA clock bandwidth based on data rates + * + * @hdl: hdl to wdi client + * @profile: [in] BandWidth profile to use + * + * Returns: 0 on success, negative on failure + */ +int ipa_wdi_set_perf_profile_per_inst(ipa_wdi_hdl_t hdl, + struct ipa_wdi_perf_profile *profile) +{ + int res = 0; + if (profile == NULL) { + IPA_WDI_ERR("Invalid input\n"); + return -EINVAL; + } + + if (hdl < 0 || hdl >= IPA_WDI_INST_MAX) { + IPA_WDI_ERR("Invalid Handle %d\n",hdl); + return -EFAULT; + } + + if (!ipa_wdi_ctx_list[hdl]) { + IPA_WDI_ERR("wdi ctx is not initialized.\n"); + return -EPERM; + } + + if (ipa_wdi_ctx_list[hdl]->wdi_version >= IPA_WDI_1 && + ipa_wdi_ctx_list[hdl]->wdi_version < IPA_WDI_3 && + hdl > 0) { + IPA_WDI_ERR("More than one instance not supported for WDI ver = %d\n", + ipa_wdi_ctx_list[hdl]->wdi_version); + return -EPERM; + } + + if (ipa3_ctx->use_pm_wrapper) { + res = ipa_pm_wrapper_wdi_set_perf_profile_internal(profile); + } else { + res = ipa_pm_set_throughput(ipa_wdi_ctx_list[hdl]->ipa_pm_hdl, + profile->max_supported_bw_mbps); + } + + if (res) { + IPA_WDI_ERR("fail to set pm throughput\n"); + return -EFAULT; + } + + return res; +} +EXPORT_SYMBOL(ipa_wdi_set_perf_profile_per_inst); + +/** + * function to create smmu mapping + * + * @hdl: hdl to wdi client + * @num_buffers: number of buffers + * @info: wdi buffer info + */ +int ipa_wdi_create_smmu_mapping_per_inst(ipa_wdi_hdl_t hdl, + u32 num_buffers, + struct ipa_wdi_buffer_info *info) +{ + struct ipa_smmu_cb_ctx *cb; + int i; + int ret = 0; + int prot = IOMMU_READ | IOMMU_WRITE; + + if (!info) { + IPAERR_RL("info = %pK\n", info); + return -EINVAL; + } + + if (hdl < 0 || hdl >= IPA_WDI_INST_MAX) { + IPA_WDI_ERR("Invalid Handle %d\n",hdl); + return -EFAULT; + } + + if (!ipa_wdi_ctx_list[hdl]) { + IPA_WDI_ERR("wdi ctx is not initialized.\n"); + return -EPERM; + } + + if (IPA_CLIENT_IS_WLAN0_INSTANCE(ipa_wdi_ctx_list[hdl]->inst_id)) + cb = ipa3_get_smmu_ctx(IPA_SMMU_CB_WLAN); + else + cb = ipa3_get_smmu_ctx(IPA_SMMU_CB_WLAN1); + + if (!cb->valid) { + IPA_WDI_ERR("No SMMU CB setup\n"); + return -EINVAL; + } + + if ((IPA_CLIENT_IS_WLAN0_INSTANCE(ipa_wdi_ctx_list[hdl]->inst_id) && + ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_WLAN]) || + (IPA_CLIENT_IS_WLAN1_INSTANCE(ipa_wdi_ctx_list[hdl]->inst_id) && + ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_WLAN1])) { + IPA_WDI_ERR("IPA SMMU not enabled\n"); + return -EINVAL; + } + + for (i = 0; i < num_buffers; i++) { + IPA_WDI_DBG_LOW("i=%d pa=0x%pa iova=0x%lx sz=0x%zx\n", i, + &info[i].pa, info[i].iova, info[i].size); + info[i].result = ipa3_iommu_map(cb->iommu_domain, + rounddown(info[i].iova, PAGE_SIZE), + rounddown(info[i].pa, PAGE_SIZE), + roundup(info[i].size + info[i].pa - + rounddown(info[i].pa, PAGE_SIZE), PAGE_SIZE), + prot); + } + + return ret; +} +EXPORT_SYMBOL(ipa_wdi_create_smmu_mapping_per_inst); + + +/** + * function to release smmu mapping + * + * @hdl: hdl to wdi client + * @num_buffers: number of buffers + * + * @info: wdi buffer info + */ +int ipa_wdi_release_smmu_mapping_per_inst(ipa_wdi_hdl_t hdl, + u32 num_buffers, + struct ipa_wdi_buffer_info *info) +{ + struct ipa_smmu_cb_ctx *cb; + int i; + int ret = 0; + + if (!info) { + IPAERR_RL("info = %pK\n", info); + return -EINVAL; + } + + if (hdl < 0 || hdl >= IPA_WDI_INST_MAX) { + IPA_WDI_ERR("Invalid Handle %d\n",hdl); + return -EFAULT; + } + + if (!ipa_wdi_ctx_list[hdl]) { + IPA_WDI_ERR("wdi ctx is not initialized.\n"); + return -EPERM; + } + + if (IPA_CLIENT_IS_WLAN0_INSTANCE(ipa_wdi_ctx_list[hdl]->inst_id)) + cb = ipa3_get_smmu_ctx(IPA_SMMU_CB_WLAN); + else + cb = ipa3_get_smmu_ctx(IPA_SMMU_CB_WLAN1); + + if (!cb->valid) { + IPA_WDI_ERR("No SMMU CB setup\n"); + return -EINVAL; + } + + for (i = 0; i < num_buffers; i++) { + IPA_WDI_DBG_LOW("i=%d pa=0x%pa iova=0x%lx sz=0x%zx\n", i, + &info[i].pa, info[i].iova, info[i].size); + info[i].result = iommu_unmap(cb->iommu_domain, + rounddown(info[i].iova, PAGE_SIZE), + roundup(info[i].size + info[i].pa - + rounddown(info[i].pa, PAGE_SIZE), PAGE_SIZE)); + } + + return ret; +} +EXPORT_SYMBOL(ipa_wdi_release_smmu_mapping_per_inst); + + +/** + * ipa_wdi_opt_dpath_register_flt_cb_per_inst - Client should call this function to + * register filter reservation/release and filter addition/deletion callbacks + * + * + * @Return 0 on success, negative on failure + */ +int ipa_wdi_opt_dpath_register_flt_cb_per_inst( + ipa_wdi_hdl_t hdl, + ipa_wdi_opt_dpath_flt_rsrv_cb flt_rsrv_cb, + ipa_wdi_opt_dpath_flt_rsrv_rel_cb flt_rsrv_rel_cb, + ipa_wdi_opt_dpath_flt_add_cb flt_add_cb, + ipa_wdi_opt_dpath_flt_rem_cb flt_rem_cb) +{ + int ret = 0; + + if (hdl < 0 || hdl >= IPA_WDI_INST_MAX) { + IPA_WDI_ERR("Invalid Handle %d\n",hdl); + return -EFAULT; + } + + if (!ipa_wdi_ctx_list[hdl]) { + IPA_WDI_ERR("wdi ctx is not initialized.\n"); + return -EPERM; + } + + opt_dpath_info[hdl].flt_rsrv_cb = flt_rsrv_cb; + opt_dpath_info[hdl].flt_rsrv_rel_cb = flt_rsrv_rel_cb; + opt_dpath_info[hdl].flt_add_cb = flt_add_cb; + opt_dpath_info[hdl].flt_rem_cb = flt_rem_cb; + + if (ipa3_ctx->platform_type == IPA_PLAT_TYPE_XR) { + IPADBG("wdi_xr_opt_dpath_register_flt_cb: callbacks registered.\n"); + atomic_set(&opt_dpath_info[hdl].is_xr_opt_dp_cb_registered, 1); + return ret; + } + + atomic_set(&opt_dpath_info[hdl].is_opt_dp_cb_registered, 1); + + IPADBG("wdi_opt_dpath_register_flt_cb: callbacks registered.\n"); + + return ret; + +} +EXPORT_SYMBOL(ipa_wdi_opt_dpath_register_flt_cb_per_inst); + +/** + * ipa_wdi_opt_dpath_notify_flt_rsvd_per_inst_internal - Client should call this function to + * notify filter reservation event to IPA + * + * + * @Return 0 on success, negative on failure + */ +int ipa_wdi_opt_dpath_notify_flt_rsvd_per_inst + (ipa_wdi_hdl_t hdl, bool is_success) +{ + int ret = 0; + int flt_rsv_status = 0; + struct ipa_wlan_opt_dp_rsrv_filter_complt_ind_msg_v01 ind; + + if (hdl < 0 || hdl >= IPA_WDI_INST_MAX) { + IPA_WDI_ERR("Invalid Handle %d\n",hdl); + return -EFAULT; + } + + if (!ipa_wdi_ctx_list[hdl]) { + IPA_WDI_ERR("wdi ctx is not initialized.\n"); + return -EPERM; + } + + if (ipa_wdi_ctx_list[hdl]->wdi_version >= IPA_WDI_1 && + ipa_wdi_ctx_list[hdl]->wdi_version < IPA_WDI_3 && + hdl > 0) { + IPA_WDI_ERR("More than one instance not supported for WDI ver = %d\n", + ipa_wdi_ctx_list[hdl]->wdi_version); + return -EPERM; + } + + if (ipa3_ctx->platform_type == IPA_PLAT_TYPE_XR) { + IPA_WDI_DBG("Received wlan flt rsv status %d\n", is_success); + flt_rsv_status = is_success ? 1 : 0; + atomic_set(&ipa3_ctx->ipa_xr_wdi_flt_rsv_status, flt_rsv_status); + complete(&ipa3_ctx->ipa_xr_wdi_flt_rsrv_success); + return ret; + } + + memset(&ind, 0, sizeof(ind)); + ind.rsrv_filter_status.result = (is_success == true) ? IPA_QMI_RESULT_SUCCESS_V01:IPA_QMI_RESULT_FAILURE_V01; + ind.rsrv_filter_status.error = IPA_QMI_ERR_NONE_V01; + ret = ipa3_qmi_send_wdi_opt_dpath_rsrv_flt_ind(&ind); + + return ret; +} +EXPORT_SYMBOL(ipa_wdi_opt_dpath_notify_flt_rsvd_per_inst); + + +/** + * ipa_wdi_opt_dpath_notify_flt_rlsd_per_inst_internal - Client should call this function to + * notify filter release event to IPA + * + * + * @Return 0 on success, negative on failure + */ +int ipa_wdi_opt_dpath_notify_flt_rlsd_per_inst + (ipa_wdi_hdl_t hdl, bool is_success) +{ + int ret = 0; + int flt_rsv_status = 0; + struct ipa_wlan_opt_dp_remove_all_filter_complt_ind_msg_v01 ind; + + if (hdl < 0 || hdl >= IPA_WDI_INST_MAX) { + IPA_WDI_ERR("Invalid Handle %d\n",hdl); + return -EFAULT; + } + + if (!ipa_wdi_ctx_list[hdl]) { + IPA_WDI_ERR("wdi ctx is not initialized.\n"); + return -EPERM; + } + + ret = ipa_pm_deferred_deactivate(ipa_wdi_ctx_list[0]->ipa_pm_hdl); + + if (ipa3_ctx->platform_type == IPA_PLAT_TYPE_XR) { + IPA_WDI_DBG("Received wlan flt rlsd status %d\n", is_success); + flt_rsv_status = is_success ? 0 : 1; + atomic_set(&ipa3_ctx->ipa_xr_wdi_flt_rsv_status, flt_rsv_status); + return ret; + } + + memset(&ind, 0, sizeof(ind)); + ind.filter_removal_all_status.result = + (is_success == true) ? IPA_QMI_RESULT_SUCCESS_V01:IPA_QMI_RESULT_FAILURE_V01; + ind.filter_removal_all_status.error = IPA_QMI_ERR_NONE_V01; + ret = ipa3_qmi_send_wdi_opt_dpath_rmv_all_flt_ind(&ind); + + return ret; +} +EXPORT_SYMBOL(ipa_wdi_opt_dpath_notify_flt_rlsd_per_inst); + + +/** + * ipa_wdi_opt_dpath_rsrv_filter_req_internal() - Sends WLAN DP filter reservation + * from IPA Q6 to WLAN + * @req: [in] filter reservation parameters from IPA Q6 + * + * Returns: 0 on success, negative on failure + * + * + */ +int ipa_wdi_opt_dpath_rsrv_filter_req( + struct ipa_wlan_opt_dp_rsrv_filter_req_msg_v01 *req, + struct ipa_wlan_opt_dp_rsrv_filter_resp_msg_v01 *resp) +{ + int ret = 0, ret1 =0; + struct ipa_wdi_opt_dpath_flt_rsrv_cb_params rsrv_filter_req; + struct ipa_wlan_opt_dp_set_wlan_per_info_req_msg_v01 set_wlan_ep_req; + + memset(resp, 0, sizeof(struct ipa_wlan_opt_dp_rsrv_filter_resp_msg_v01)); + memset(&rsrv_filter_req, 0, sizeof(struct ipa_wdi_opt_dpath_flt_rsrv_cb_params)); + memset(&set_wlan_ep_req, 0, sizeof(struct ipa_wlan_opt_dp_set_wlan_per_info_req_msg_v01)); + + if (!atomic_read(&opt_dpath_info[0].is_opt_dp_cb_registered)) + { + IPAERR("filter reserve cb not registered"); + resp->resp.result = IPA_QMI_RESULT_FAILURE_V01; + resp->resp.error = IPA_QMI_ERR_INTERNAL_V01; + return -EPERM; + } + + if (opt_dpath_info[0].ipa_ep_idx_tx <= 0 || opt_dpath_info[0].ipa_ep_idx_rx <= 0) { + IPA_WDI_ERR("Either TX/RX ep is not configured. \n"); + resp->resp.result = IPA_QMI_RESULT_FAILURE_V01; + resp->resp.error = IPA_QMI_ERR_INTERNAL_V01; + return -EPERM; + } + + IPADBG("ep_tx = %d\n", opt_dpath_info[0].ipa_ep_idx_tx); + IPADBG("ep_rx = %d\n", opt_dpath_info[0].ipa_ep_idx_rx); + + set_wlan_ep_req.dest_wlan_endp_id = opt_dpath_info[0].ipa_ep_idx_tx; + set_wlan_ep_req.src_wlan_endp_id = opt_dpath_info[0].ipa_ep_idx_rx; + set_wlan_ep_req.dest_apps_endp_id = ipa_get_ep_mapping(IPA_CLIENT_APPS_LAN_CONS); + set_wlan_ep_req.hdr_len = ((opt_dpath_info[0].hdr_len) ? + opt_dpath_info[0].hdr_len : + ETH_HLEN); + + ret = ipa_pm_activate_sync(opt_dpath_info[0].ipa_pm_hdl); + if (ret) { + IPA_WDI_DBG("fail to activate ipa pm\n"); + resp->resp.result = IPA_QMI_RESULT_FAILURE_V01; + resp->resp.error = IPA_QMI_ERR_INTERNAL_V01; + return -EFAULT; + } + + + ipa3_qmi_send_wdi_opt_dpath_ep_info(&set_wlan_ep_req); + + rsrv_filter_req.num_filters = req->num_filters; + rsrv_filter_req.rsrv_timeout = req->timeout_val_ms; + ret = + opt_dpath_info[0].flt_rsrv_cb( + opt_dpath_info[0].priv, &rsrv_filter_req); + + if (!ret) { + + atomic_set(&opt_dpath_info[0].rsrv_req, 1); + + opt_dpath_info[0].q6_rtng_table_index = + req->q6_rtng_table_index; + + ipa3_enable_wdi3_opt_dpath(opt_dpath_info[0].ipa_ep_idx_rx, + opt_dpath_info[0].ipa_ep_idx_tx, + opt_dpath_info[0].q6_rtng_table_index); + } else { + ret1 = ipa_pm_deferred_deactivate(opt_dpath_info[0].ipa_pm_hdl); + if (ret1) { + IPA_WDI_DBG("fail to deactivate ipa pm\n"); + } + } + + resp->resp.result = ret; + resp->resp.error = IPA_QMI_ERR_NONE_V01; + + return ret; + +} +EXPORT_SYMBOL(ipa_wdi_opt_dpath_rsrv_filter_req); + + +/** + * ipa_wdi_opt_dpath_add_filter_req_internal() - Sends WLAN DP filter info + * from IPA Q6 to WLAN + * @req: [in] filter add parameters from IPA Q6 + * + * Returns: 0 on success, negative on failure + * + * + */ + +int ipa_wdi_opt_dpath_add_filter_req( + struct ipa_wlan_opt_dp_add_filter_req_msg_v01 *req, + struct ipa_wlan_opt_dp_add_filter_complt_ind_msg_v01 *ind) +{ + int ret = 0; + + struct ipa_wdi_opt_dpath_flt_add_cb_params flt_add_req; + + memset(ind, 0, sizeof(struct ipa_wlan_opt_dp_add_filter_complt_ind_msg_v01)); + memset(&flt_add_req, 0, sizeof(struct ipa_wdi_opt_dpath_flt_add_cb_params)); + + if (!atomic_read(&opt_dpath_info[0].is_opt_dp_cb_registered)) { + IPAERR("filter add cb not registered"); + ind->filter_add_status.result = IPA_QMI_RESULT_FAILURE_V01; + ind->filter_add_status.error = IPA_QMI_ERR_INTERNAL_V01; + ind->filter_idx = req->filter_idx; + return -EPERM; + } + + if (req->ip_type != QMI_IPA_IP_TYPE_V4_V01 && + req->ip_type != QMI_IPA_IP_TYPE_V6_V01) { + IPAERR("Invalid IP Type: %d\n", req->ip_type); + ind->filter_add_status.result = IPA_QMI_RESULT_FAILURE_V01; + ind->filter_add_status.error = IPA_QMI_ERR_INTERNAL_V01; + ind->filter_idx = req->filter_idx; + return -1; + } + + flt_add_req.num_tuples = 1; + flt_add_req.flt_info[0].version = (req->ip_type == QMI_IPA_IP_TYPE_V4_V01) ? 0 : 1; + if (!flt_add_req.flt_info[0].version) { + flt_add_req.flt_info[0].ipv4_addr.ipv4_saddr = req->v4_addr.source; + flt_add_req.flt_info[0].ipv4_addr.ipv4_daddr = req->v4_addr.dest; + IPADBG("IPv4 saddr:0x%x, daddr:0x%x\n", + flt_add_req.flt_info[0].ipv4_addr.ipv4_saddr, + flt_add_req.flt_info[0].ipv4_addr.ipv4_daddr); + } else { + memcpy(flt_add_req.flt_info[0].ipv6_addr.ipv6_saddr, + req->v6_addr.source, + sizeof(req->v6_addr.source)); + memcpy(flt_add_req.flt_info[0].ipv6_addr.ipv6_daddr, + req->v6_addr.dest, + sizeof(req->v6_addr.dest)); + IPADBG("IPv6 saddr:0x%x:%x:%x:%x, daddr:0x%x:%x:%x:%x\n", + flt_add_req.flt_info[0].ipv6_addr.ipv6_saddr[0], + flt_add_req.flt_info[0].ipv6_addr.ipv6_saddr[1], + flt_add_req.flt_info[0].ipv6_addr.ipv6_saddr[2], + flt_add_req.flt_info[0].ipv6_addr.ipv6_saddr[3], + flt_add_req.flt_info[0].ipv6_addr.ipv6_daddr[0], + flt_add_req.flt_info[0].ipv6_addr.ipv6_daddr[1], + flt_add_req.flt_info[0].ipv6_addr.ipv6_daddr[2], + flt_add_req.flt_info[0].ipv6_addr.ipv6_daddr[3]); + } + + ret = + opt_dpath_info[0].flt_add_cb + (opt_dpath_info[0].priv, &flt_add_req); + + ind->filter_idx = req->filter_idx; + ind->filter_handle_valid = true; + ind->filter_handle = flt_add_req.flt_info[0].out_hdl; + ind->filter_add_status.result = ret; + ind->filter_add_status.error = IPA_QMI_ERR_NONE_V01; + + return ret; + +} +EXPORT_SYMBOL(ipa_wdi_opt_dpath_add_filter_req); + +/** + * ipa_wdi_opt_dpath_remove_filter_req_internal() - Sends WLAN DP filter info + * from IPA Q6 to WLAN + * @req: [in] filter removal parameters from IPA Q6 + * + * Returns: 0 on success, negative on failure + * + * + */ + +int ipa_wdi_opt_dpath_remove_filter_req( + struct ipa_wlan_opt_dp_remove_filter_req_msg_v01 *req, + struct ipa_wlan_opt_dp_remove_filter_complt_ind_msg_v01 *ind) +{ + int ret = 0; + + struct ipa_wdi_opt_dpath_flt_rem_cb_params flt_rem_req; + + memset(ind, 0, sizeof(struct ipa_wlan_opt_dp_remove_filter_complt_ind_msg_v01)); + memset(&flt_rem_req, 0, sizeof(struct ipa_wdi_opt_dpath_flt_rem_cb_params)); + + if (!atomic_read(&opt_dpath_info[0].is_opt_dp_cb_registered)) + { + IPAERR("filter remove cb not registered"); + ind->filter_removal_status.result = IPA_QMI_RESULT_SUCCESS_V01; + ind->filter_removal_status.error = IPA_QMI_ERR_NONE_V01; + ind->filter_idx = req->filter_idx; + return -EPERM; + } + + flt_rem_req.num_tuples = 1; + flt_rem_req.hdl_info[0] = req->filter_handle; + + ret = + opt_dpath_info[0].flt_rem_cb + (opt_dpath_info[0].priv, &flt_rem_req); + + ind->filter_idx = req->filter_idx; + ind->filter_removal_status.result = ret; + ind->filter_removal_status.error = IPA_QMI_ERR_NONE_V01; + + return ret; + +} +EXPORT_SYMBOL(ipa_wdi_opt_dpath_remove_filter_req); + + + +/** + * ipa_wdi_opt_dpath_remove_all_filter_req() - Sends WLAN DP filter info + * from IPA Q6 to WLAN + * @req: [in] filter removal parameters from IPA Q6 + * + * Returns: 0 on success, negative on failure + * + * + */ + +int ipa_wdi_opt_dpath_remove_all_filter_req( + struct ipa_wlan_opt_dp_remove_all_filter_req_msg_v01 *req, + struct ipa_wlan_opt_dp_remove_all_filter_resp_msg_v01 *resp) +{ + int ret = 0; + + memset(resp, 0, sizeof(struct ipa_wlan_opt_dp_remove_all_filter_resp_msg_v01)); + + if (!atomic_read(&opt_dpath_info[0].is_opt_dp_cb_registered)) + { + IPAERR("filter release cb not registered"); + return -EPERM; + } + + if (!atomic_read(&opt_dpath_info[0].rsrv_req)) + { + IPAERR("Reservation request not sent. IGNORE"); + return 0; + } + + atomic_set(&opt_dpath_info[0].rsrv_req, 0); + + ret = + opt_dpath_info[0].flt_rsrv_rel_cb( + opt_dpath_info[0].priv); + + if (opt_dpath_info[0].ipa_ep_idx_rx <= 0 || opt_dpath_info[0].ipa_ep_idx_tx <= 0) { + IPA_WDI_ERR("Either RX ep or TX ep is not configured. \n"); + return 0; + } + + ipa3_disable_wdi3_opt_dpath(opt_dpath_info[0].ipa_ep_idx_rx, + opt_dpath_info[0].ipa_ep_idx_tx); + + resp->resp.result = ret; + resp->resp.error = IPA_QMI_ERR_NONE_V01; + + return ret; + +} +EXPORT_SYMBOL(ipa_wdi_opt_dpath_remove_all_filter_req); + + +/** + * ipa_xr_wdi_opt_dpath_rsrv_filter_req() - Sends WLAN DP filter reservation + * from IPA Driver to WLAN + * + * Returns: 0 on success, negative on failure + * + */ +int ipa_xr_wdi_opt_dpath_rsrv_filter_req(void) +{ + int ret = 0; + struct ipa_wdi_opt_dpath_flt_rsrv_cb_params rsrv_filter_req; + int rsrv_completed; + + memset(&rsrv_filter_req, 0, sizeof(struct ipa_wdi_opt_dpath_flt_rsrv_cb_params)); + if (!atomic_read(&opt_dpath_info[0].is_xr_opt_dp_cb_registered)) { + IPAERR("filter reserve cb not registered"); + return -EPERM; + } + + if (opt_dpath_info[0].ipa_ep_idx_tx <= 0 || opt_dpath_info[0].ipa_ep_idx_rx <= 0) { + IPA_WDI_ERR("Either TX/RX ep is not configured.\n"); + return -EPERM; + } + + ret = ipa_pm_activate_sync(opt_dpath_info[0].ipa_pm_hdl); + if (ret) { + IPA_WDI_DBG("fail to activate ipa pm\n"); + return -EFAULT; + } + + init_completion(&ipa3_ctx->ipa_xr_wdi_flt_rsrv_success); + rsrv_filter_req.num_filters = NO_OF_FILTERS; + ret = opt_dpath_info[0].flt_rsrv_cb( + opt_dpath_info[0].priv, &rsrv_filter_req); + if (!ret) { + atomic_set(&opt_dpath_info[0].rsrv_req, 1); + } else { + if (ipa_pm_deferred_deactivate(opt_dpath_info[0].ipa_pm_hdl)) + IPA_WDI_DBG("fail to deactivate ipa pm\n"); + } + + IPA_WDI_DBG("reserved filter callbacks called.\n"); + rsrv_completed = wait_for_completion_timeout(&ipa3_ctx->ipa_xr_wdi_flt_rsrv_success, + msecs_to_jiffies(IPA_WDI_FLT_RSRV_TIMEOUT_MS)); + if (!rsrv_completed) { + IPADBG("Timed out waiting for filter reservation notification from WLAN\n"); + return -EPERM; + } + return ret; +} +EXPORT_SYMBOL_GPL(ipa_xr_wdi_opt_dpath_rsrv_filter_req); + +/** + * ipa_xr_wdi_opt_dpath_add_filter_req() - Sends WLAN DP filter info + * from IPA Driver to WLAN + * @req: [in] filter add parameters from IPA Driver + * + * Returns: 0 on success, negative on failure + * + * + */ + +int ipa_xr_wdi_opt_dpath_add_filter_req(struct ipa_wdi_opt_dpath_flt_add_cb_params *req, + u32 stream_id) +{ + int ret = 0; + + if (!atomic_read(&opt_dpath_info[0].is_xr_opt_dp_cb_registered)) { + IPAERR("filter add cb not registered"); + return -EPERM; + } + + ret = + opt_dpath_info[0].flt_add_cb + (opt_dpath_info[0].priv, req); + IPA_WDI_DBG("Add filter callbacks called for stream id %d\n", stream_id); + if (!ret) + add_flt_hndl[stream_id].filter_handle = req->flt_info[0].out_hdl; + return ret; +} +EXPORT_SYMBOL_GPL(ipa_xr_wdi_opt_dpath_add_filter_req); + +/** + * ipa_xr_wdi_opt_dpath_remove_filter_req() - Sends WLAN DP filter info + * from IPA Driver to WLAN + * + * Returns: 0 on success, negative on failure + * + * + */ + +int ipa_xr_wdi_opt_dpath_remove_filter_req(u32 stream_id) +{ + int ret = 0; + struct ipa_wdi_opt_dpath_flt_rem_cb_params flt_rem_req; + + memset(&flt_rem_req, 0, sizeof(struct ipa_wdi_opt_dpath_flt_rem_cb_params)); + if (!atomic_read(&opt_dpath_info[0].is_xr_opt_dp_cb_registered)) { + IPAERR("filter remove cb not registered"); + return -EPERM; + } + + flt_rem_req.num_tuples = 1; + flt_rem_req.hdl_info[0] = add_flt_hndl[stream_id].filter_handle; + + ret = opt_dpath_info[0].flt_rem_cb + (opt_dpath_info[0].priv, &flt_rem_req); + IPA_WDI_DBG("Remove filter callbacks called for stream id %d\n", stream_id); + if (!ret) + add_flt_hndl[stream_id].filter_handle = 0; + return ret; +} +EXPORT_SYMBOL_GPL(ipa_xr_wdi_opt_dpath_remove_filter_req); + +/** + * ipa_xr_wdi_opt_dpath_remove_all_filter_req() - Sends WLAN DP filter info + * from IPAs to WLAN + * + * Returns: 0 on success, negative on failure + * + * + */ + +int ipa_xr_wdi_opt_dpath_remove_all_filter_req(void) +{ + int ret = 0; + + if (!atomic_read(&opt_dpath_info[0].is_xr_opt_dp_cb_registered)) { + IPAERR("filter release cb not registered"); + return -EPERM; + } + + if (!atomic_read(&opt_dpath_info[0].rsrv_req)) { + IPAERR("Reservation request not sent. IGNORE"); + return 0; + } + + atomic_set(&opt_dpath_info[0].rsrv_req, 0); + + ret = opt_dpath_info[0].flt_rsrv_rel_cb( + opt_dpath_info[0].priv); + + if (opt_dpath_info[0].ipa_ep_idx_rx <= 0 || opt_dpath_info[0].ipa_ep_idx_tx <= 0) { + IPA_WDI_ERR("Either RX ep or TX ep is not configured.\n"); + return 0; + } + + IPA_WDI_DBG("remove all filter callbacks called.\n"); + return ret; +} +EXPORT_SYMBOL_GPL(ipa_xr_wdi_opt_dpath_remove_all_filter_req); + +/** + * clean up WDI IPA offload data path + * + * @hdl: hdl to wdi client + * + * @Return 0 on success, negative on failure + */ +int ipa_wdi_cleanup_per_inst(ipa_wdi_hdl_t hdl) +{ + struct ipa_wdi_intf_info *entry; + struct ipa_wdi_intf_info *next; + + IPA_WDI_DBG("client hdl = %d, Instance = %d\n", hdl,ipa_wdi_ctx_list[hdl]->inst_id); + if (hdl < 0 || hdl >= IPA_WDI_INST_MAX) { + IPA_WDI_ERR("Invalid Handle %d\n",hdl); + return -EFAULT; + } + + if (!ipa_wdi_ctx_list[hdl]) { + IPA_WDI_ERR("wdi ctx is not initialized.\n"); + return -EPERM; + } + + if (ipa_wdi_ctx_list[hdl]->wdi_version >= IPA_WDI_1 && + ipa_wdi_ctx_list[hdl]->wdi_version < IPA_WDI_3 && + hdl > 0) { + IPA_WDI_ERR("More than one instance not supported for WDI ver = %d\n", + ipa_wdi_ctx_list[hdl]->wdi_version); + return -EPERM; + } + + /* clear interface list */ + list_for_each_entry_safe(entry, next, + &ipa_wdi_ctx_list[hdl]->head_intf_list, link) { + list_del(&entry->link); + kfree(entry); + } + mutex_destroy(&ipa_wdi_ctx_list[hdl]->lock); + kfree(ipa_wdi_ctx_list[hdl]); + atomic_set(&opt_dpath_info[hdl].is_xr_opt_dp_cb_registered, 0); + atomic_set(&opt_dpath_info[hdl].is_opt_dp_cb_registered, 0); + opt_dpath_info[0].ipa_ep_idx_rx = 0; + opt_dpath_info[0].ipa_ep_idx_tx = 0; + ipa_wdi_ctx_list[hdl] = NULL; + return 0; +} +EXPORT_SYMBOL(ipa_wdi_cleanup_per_inst); + +/** + * function to deregister before unload and after disconnect + * + * @Return 0 on success, negative on failure + */ +int ipa_wdi_dereg_intf_per_inst(const char *netdev_name,ipa_wdi_hdl_t hdl) +{ + int len, ret = 0; + struct ipa_ioc_del_hdr *hdr = NULL; + struct ipa_wdi_intf_info *entry; + struct ipa_wdi_intf_info *next; + + if (!netdev_name) { + IPA_WDI_ERR("no netdev name.\n"); + return -EINVAL; + } + + if (hdl < 0 || hdl >= IPA_WDI_INST_MAX) { + IPA_WDI_ERR("Invalid Handle %d\n",hdl); + return -EFAULT; + } + + if (!ipa_wdi_ctx_list[hdl]) { + IPA_WDI_ERR("wdi ctx is not initialized.\n"); + return -EPERM; + } + + + if (ipa_wdi_ctx_list[hdl]->wdi_version >= IPA_WDI_1 && + ipa_wdi_ctx_list[hdl]->wdi_version < IPA_WDI_3 && + hdl > 0) { + IPA_WDI_ERR("More than one instance not supported for WDI ver = %d\n", + ipa_wdi_ctx_list[hdl]->wdi_version); + return -EPERM; + } + + if (!ipa_wdi_ctx_list[hdl]) { + IPA_WDI_ERR("wdi ctx is not initialized.\n"); + return -EPERM; + } + IPA_WDI_DBG("Deregister Instance hdl %d\n",hdl); + mutex_lock(&ipa_wdi_ctx_list[hdl]->lock); + list_for_each_entry_safe(entry, next, &ipa_wdi_ctx_list[hdl]->head_intf_list, + link) + if (strcmp(entry->netdev_name, netdev_name) == 0) { + len = sizeof(struct ipa_ioc_del_hdr) + + 2 * sizeof(struct ipa_hdr_del); + hdr = kzalloc(len, GFP_KERNEL); + if (hdr == NULL) { + IPA_WDI_ERR("fail to alloc %d bytes\n", len); + mutex_unlock(&ipa_wdi_ctx_list[hdl]->lock); + return -ENOMEM; + } + + hdr->commit = 1; + hdr->num_hdls = 2; + hdr->hdl[0].hdl = entry->partial_hdr_hdl[0]; + hdr->hdl[1].hdl = entry->partial_hdr_hdl[1]; + IPA_WDI_DBG("IPv4 hdr hdl: %d IPv6 hdr hdl: %d\n", + hdr->hdl[0].hdl, hdr->hdl[1].hdl); + + if (ipa_del_hdr(hdr)) { + IPA_WDI_ERR("fail to delete partial header\n"); + ret = -EFAULT; + goto fail; + } + + if (ipa_deregister_intf(entry->netdev_name)) { + IPA_WDI_ERR("fail to del interface props\n"); + ret = -EFAULT; + goto fail; + } + + list_del(&entry->link); + kfree(entry); + + break; + } + +fail: + kfree(hdr); + mutex_unlock(&ipa_wdi_ctx_list[hdl]->lock); + return ret; +} +EXPORT_SYMBOL(ipa_wdi_dereg_intf_per_inst); + +/** + * function to disconnect pipes + * + * @hdl: hdl to wdi client + * Note: Should not be called from atomic context + * + * Returns: 0 on success, negative on failure + */ +int ipa_wdi_disconn_pipes_per_inst(ipa_wdi_hdl_t hdl) +{ + int i, ipa_ep_idx_rx, ipa_ep_idx_tx; + int ipa_ep_idx_tx1 = IPA_EP_NOT_ALLOCATED; + + if (hdl < 0 || hdl >= IPA_WDI_INST_MAX) { + IPA_WDI_ERR("Invalid Handle %d\n",hdl); + return -EFAULT; + } + + if (!ipa_wdi_ctx_list[hdl]) { + IPA_WDI_ERR("wdi ctx is not initialized.\n"); + return -EPERM; + } + + if (ipa_wdi_ctx_list[hdl]->wdi_version >= IPA_WDI_1 && + ipa_wdi_ctx_list[hdl]->wdi_version < IPA_WDI_3 && + hdl > 0) { + IPA_WDI_ERR("More than one instance not supported for WDI ver = %d\n", + ipa_wdi_ctx_list[hdl]->wdi_version); + return -EPERM; + } + + IPA_WDI_DBG("Disconnect pipes for hdl %d\n",hdl); + /* tear down sys pipe if needed */ + for (i = 0; i < ipa_wdi_ctx_list[hdl]->num_sys_pipe_needed; i++) { + if (ipa_teardown_sys_pipe(ipa_wdi_ctx_list[hdl]->sys_pipe_hdl[i])) { + IPA_WDI_ERR("fail to tear down sys pipe %d\n", i); + return -EFAULT; + } + } + + if (ipa_wdi_ctx_list[hdl]->wdi_version >= IPA_WDI_3) { + if (IPA_CLIENT_IS_WLAN0_INSTANCE(ipa_wdi_ctx_list[hdl]->inst_id)) { + ipa_ep_idx_rx = ipa_get_ep_mapping(IPA_CLIENT_WLAN2_PROD); + ipa_ep_idx_tx = ipa_get_ep_mapping(IPA_CLIENT_WLAN2_CONS); + } else { + ipa_ep_idx_rx = ipa_get_ep_mapping(IPA_CLIENT_WLAN3_PROD); + ipa_ep_idx_tx = ipa_get_ep_mapping(IPA_CLIENT_WLAN4_CONS); + } + + if (ipa_wdi_ctx_list[hdl]->is_tx1_used) + ipa_ep_idx_tx1 = + ipa_get_ep_mapping(IPA_CLIENT_WLAN2_CONS1); + } else { + ipa_ep_idx_rx = ipa_get_ep_mapping(IPA_CLIENT_WLAN1_PROD); + ipa_ep_idx_tx = ipa_get_ep_mapping(IPA_CLIENT_WLAN1_CONS); + } + + if (ipa_wdi_ctx_list[hdl]->wdi_version >= IPA_WDI_3) { + if (ipa3_disconn_wdi3_pipes( + ipa_ep_idx_tx, ipa_ep_idx_rx, ipa_ep_idx_tx1)) { + IPA_WDI_ERR("fail to tear down wdi pipes\n"); + return -EFAULT; + } + } else { + if (ipa_disconnect_wdi_pipe(ipa_wdi_ctx_list[hdl]->tx_pipe_hdl)) { + IPA_WDI_ERR("fail to tear down wdi tx pipes\n"); + return -EFAULT; + } + if (ipa_disconnect_wdi_pipe(ipa_wdi_ctx_list[hdl]->rx_pipe_hdl)) { + IPA_WDI_ERR("fail to tear down wdi rx pipes\n"); + return -EFAULT; + } + } + + if (ipa_pm_deregister(ipa_wdi_ctx_list[hdl]->ipa_pm_hdl)) { + IPA_WDI_ERR("fail to deregister ipa pm\n"); + return -EFAULT; + } + + return 0; +} +EXPORT_SYMBOL(ipa_wdi_disconn_pipes_per_inst); + +/** + * function to disable IPA offload data path + * + * @hdl: hdl to wdi client + * Note: Should not be called from atomic context + * + * Returns: 0 on success, negative on failure + */ +int ipa_wdi_disable_pipes_per_inst(ipa_wdi_hdl_t hdl) +{ + int ret; + int ipa_ep_idx_tx, ipa_ep_idx_rx; + int ipa_ep_idx_tx1 = IPA_EP_NOT_ALLOCATED; + + + if (hdl < 0 || hdl >= IPA_WDI_INST_MAX) { + IPA_WDI_ERR("Invalid Handle %d\n",hdl); + return -EFAULT; + } + + if (!ipa_wdi_ctx_list[hdl]) { + IPA_WDI_ERR("wdi ctx is not initialized.\n"); + return -EPERM; + } + + if (ipa_wdi_ctx_list[hdl]->wdi_version >= IPA_WDI_1 && + ipa_wdi_ctx_list[hdl]->wdi_version < IPA_WDI_3 && + hdl > 0) { + IPA_WDI_ERR("More than one instance not supported for WDI ver = %d\n", + ipa_wdi_ctx_list[hdl]->wdi_version); + return -EPERM; + } + + if (ipa_wdi_ctx_list[hdl]->wdi_version >= IPA_WDI_3) { + if (IPA_CLIENT_IS_WLAN0_INSTANCE(ipa_wdi_ctx_list[hdl]->inst_id)) { + ipa_ep_idx_rx = ipa_get_ep_mapping(IPA_CLIENT_WLAN2_PROD); + ipa_ep_idx_tx = ipa_get_ep_mapping(IPA_CLIENT_WLAN2_CONS); + } else { + ipa_ep_idx_rx = ipa_get_ep_mapping(IPA_CLIENT_WLAN3_PROD); + ipa_ep_idx_tx = ipa_get_ep_mapping(IPA_CLIENT_WLAN4_CONS); + } + + if (ipa_wdi_ctx_list[hdl]->is_tx1_used) + ipa_ep_idx_tx1 = + ipa_get_ep_mapping(IPA_CLIENT_WLAN2_CONS1); + } else { + ipa_ep_idx_rx = ipa_get_ep_mapping(IPA_CLIENT_WLAN1_PROD); + ipa_ep_idx_tx = ipa_get_ep_mapping(IPA_CLIENT_WLAN1_CONS); + } + + if (ipa_wdi_ctx_list[hdl]->wdi_version >= IPA_WDI_3) { + if (ipa3_disable_wdi3_pipes( + ipa_ep_idx_tx, ipa_ep_idx_rx, ipa_ep_idx_tx1)) { + IPA_WDI_ERR("fail to disable wdi pipes\n"); + return -EFAULT; + } + } else { + if (ipa_suspend_wdi_pipe(ipa_wdi_ctx_list[hdl]->tx_pipe_hdl)) { + IPA_WDI_ERR("fail to suspend wdi tx pipe\n"); + return -EFAULT; + } + if (ipa_disable_wdi_pipe(ipa_wdi_ctx_list[hdl]->tx_pipe_hdl)) { + IPA_WDI_ERR("fail to disable wdi tx pipe\n"); + return -EFAULT; + } + if (ipa_suspend_wdi_pipe(ipa_wdi_ctx_list[hdl]->rx_pipe_hdl)) { + IPA_WDI_ERR("fail to suspend wdi rx pipe\n"); + return -EFAULT; + } + if (ipa_disable_wdi_pipe(ipa_wdi_ctx_list[hdl]->rx_pipe_hdl)) { + IPA_WDI_ERR("fail to disable wdi rx pipe\n"); + return -EFAULT; + } + } + + ret = ipa_pm_deactivate_sync(ipa_wdi_ctx_list[hdl]->ipa_pm_hdl); + if (ret) { + IPA_WDI_ERR("fail to deactivate ipa pm\n"); + return -EFAULT; + } + + if (ipa3_ctx->platform_type == IPA_PLAT_TYPE_XR) + atomic_set(&ipa3_ctx->ipa_xr_wdi_flt_rsv_status, 0); + return 0; +} +EXPORT_SYMBOL(ipa_wdi_disable_pipes_per_inst); + +int ipa_wdi_init(struct ipa_wdi_init_in_params *in, + struct ipa_wdi_init_out_params *out) +{ + if (in == NULL) { + IPA_WDI_ERR("invalid params in=%pK\n", in); + return -EINVAL; + } + + in->inst_id = DEFAULT_INSTANCE_ID; + return ipa_wdi_init_per_inst(in, out); +} +EXPORT_SYMBOL(ipa_wdi_init); + +int ipa_wdi_cleanup(void) +{ + return ipa_wdi_cleanup_per_inst(0); +} +EXPORT_SYMBOL(ipa_wdi_cleanup); + +int ipa_wdi_reg_intf(struct ipa_wdi_reg_intf_in_params *in) +{ + if (in == NULL) { + IPA_WDI_ERR("invalid params in=%pK\n", in); + return -EINVAL; + } + in->hdl = 0; + return ipa_wdi_reg_intf_per_inst(in); +} +EXPORT_SYMBOL(ipa_wdi_reg_intf); + +int ipa_wdi_dereg_intf(const char *netdev_name) +{ + return ipa_wdi_dereg_intf_per_inst(netdev_name, 0); +} +EXPORT_SYMBOL(ipa_wdi_dereg_intf); + +int ipa_wdi_conn_pipes(struct ipa_wdi_conn_in_params *in, + struct ipa_wdi_conn_out_params *out) +{ + if (!(in && out)) { + IPA_WDI_ERR("empty parameters. in=%pK out=%pK\n", in, out); + return -EINVAL; + } + + in->hdl = 0; + return ipa_wdi_conn_pipes_per_inst(in, out); +} +EXPORT_SYMBOL(ipa_wdi_conn_pipes); + +int ipa_wdi_disconn_pipes(void) +{ + return ipa_wdi_disconn_pipes_per_inst(0); +} +EXPORT_SYMBOL(ipa_wdi_disconn_pipes); + +int ipa_wdi_enable_pipes(void) +{ + return ipa_wdi_enable_pipes_per_inst(0); +} +EXPORT_SYMBOL(ipa_wdi_enable_pipes); + +int ipa_wdi_disable_pipes(void) +{ + return ipa_wdi_disable_pipes_per_inst(0); +} +EXPORT_SYMBOL(ipa_wdi_disable_pipes); + +int ipa_wdi_set_perf_profile(struct ipa_wdi_perf_profile *profile) +{ + if (profile == NULL) { + IPA_WDI_ERR("Invalid input\n"); + return -EINVAL; + } + + return ipa_wdi_set_perf_profile_per_inst(0, profile); +} +EXPORT_SYMBOL(ipa_wdi_set_perf_profile); + diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_clients/ipa_wigig.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_clients/ipa_wigig.c new file mode 100644 index 0000000000..4defa57fa4 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_clients/ipa_wigig.c @@ -0,0 +1,2065 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. + */ + +#include "ipa_wigig.h" +#include +#include +#include "ipa_common_i.h" +#include "ipa_pm.h" + +#define OFFLOAD_DRV_NAME "ipa_wigig" +#define IPA_WIGIG_DBG(fmt, args...) \ + do { \ + pr_debug(OFFLOAD_DRV_NAME " %s:%d " fmt, \ + __func__, __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf(), \ + OFFLOAD_DRV_NAME " %s:%d " fmt, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf_low(), \ + OFFLOAD_DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) + +#define IPA_WIGIG_DBG_LOW(fmt, args...) \ + do { \ + pr_debug(OFFLOAD_DRV_NAME " %s:%d " fmt, \ + __func__, __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf_low(), \ + OFFLOAD_DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) + +#define IPA_WIGIG_ERR(fmt, args...) \ + do { \ + pr_err(OFFLOAD_DRV_NAME " %s:%d " fmt, \ + __func__, __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf(), \ + OFFLOAD_DRV_NAME " %s:%d " fmt, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf_low(), \ + OFFLOAD_DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) + +#define IPA_WIGIG_ERR_RL(fmt, args...) \ + do { \ + pr_err_ratelimited_ipa( \ + OFFLOAD_DRV_NAME " %s:%d " fmt, __func__,\ + __LINE__, ## args);\ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf_low(), \ + OFFLOAD_DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) + + +#define IPA_WIGIG_TX_PIPE_NUM 4 + +enum ipa_wigig_pipes_idx { + IPA_CLIENT_WIGIG_PROD_IDX = 0, + IPA_CLIENT_WIGIG1_CONS_IDX = 1, + IPA_CLIENT_WIGIG2_CONS_IDX = 2, + IPA_CLIENT_WIGIG3_CONS_IDX = 3, + IPA_CLIENT_WIGIG4_CONS_IDX = 4, + IPA_WIGIG_MAX_PIPES +}; + +struct ipa_wigig_intf_info { + char netdev_name[IPA_RESOURCE_NAME_MAX]; + u8 netdev_mac[IPA_MAC_ADDR_SIZE]; + u8 hdr_len; + u32 partial_hdr_hdl[IPA_IP_MAX]; + struct list_head link; +}; + +struct ipa_wigig_pipe_values { + uint8_t dir; + uint8_t tx_ring_id; + uint32_t desc_ring_HWHEAD; + uint16_t desc_ring_HWHEAD_masked; + uint32_t desc_ring_HWTAIL; + uint32_t status_ring_HWHEAD; + uint16_t status_ring_HWHEAD_masked; + uint32_t status_ring_HWTAIL; +}; + +struct ipa_wigig_regs_save { + struct ipa_wigig_pipe_values pipes_val[IPA_WIGIG_MAX_PIPES]; + u32 int_gen_tx_val; + u32 int_gen_rx_val; +}; + +struct ipa_wigig_context { + struct list_head head_intf_list; + struct mutex lock; + u32 ipa_pm_hdl; + phys_addr_t periph_baddr_pa; + phys_addr_t pseudo_cause_pa; + phys_addr_t int_gen_tx_pa; + phys_addr_t int_gen_rx_pa; + phys_addr_t dma_ep_misc_pa; + ipa_notify_cb tx_notify; + void *priv; + union pipes { + struct ipa_wigig_pipe_setup_info flat[IPA_WIGIG_MAX_PIPES]; + struct ipa_wigig_pipe_setup_info_smmu + smmu[IPA_WIGIG_MAX_PIPES]; + } pipes; + struct ipa_wigig_rx_pipe_data_buffer_info_smmu rx_buff_smmu; + struct ipa_wigig_tx_pipe_data_buffer_info_smmu + tx_buff_smmu[IPA_WIGIG_TX_PIPE_NUM]; + char clients_mac[IPA_WIGIG_TX_PIPE_NUM][IPA_MAC_ADDR_SIZE]; + struct ipa_wigig_regs_save regs_save; + bool smmu_en; + bool shared_cb; + u8 conn_pipes; + struct dentry *parent; + struct dentry *dent_conn_clients; + struct dentry *dent_smmu; +}; + +static struct ipa_wigig_context *ipa_wigig_ctx; + +#ifdef CONFIG_DEBUG_FS +static int ipa_wigig_init_debugfs(struct dentry *parent); +static inline void ipa_wigig_deinit_debugfs(void); +#else +static int ipa_wigig_init_debugfs(struct dentry *parent) { return 0; } +static inline void ipa_wigig_deinit_debugfs(void) { } +#endif + +int ipa_wigig_init(struct ipa_wigig_init_in_params *in, + struct ipa_wigig_init_out_params *out) +{ + struct ipa_wdi_uc_ready_params inout; + + if (!in || !out) { + IPA_WIGIG_ERR("invalid params in=%pK, out %pK\n", in, out); + return -EINVAL; + } + + IPA_WIGIG_DBG("\n"); + if (ipa_wigig_ctx) { + IPA_WIGIG_ERR("ipa_wigig_ctx was initialized before\n"); + return -EINVAL; + } + + ipa_wigig_ctx = kzalloc(sizeof(*ipa_wigig_ctx), GFP_KERNEL); + if (ipa_wigig_ctx == NULL) + return -ENOMEM; + + mutex_init(&ipa_wigig_ctx->lock); + INIT_LIST_HEAD(&ipa_wigig_ctx->head_intf_list); + + ipa_wigig_ctx->pseudo_cause_pa = in->pseudo_cause_pa; + ipa_wigig_ctx->int_gen_tx_pa = in->int_gen_tx_pa; + ipa_wigig_ctx->int_gen_rx_pa = in->int_gen_rx_pa; + ipa_wigig_ctx->dma_ep_misc_pa = in->dma_ep_misc_pa; + ipa_wigig_ctx->periph_baddr_pa = in->periph_baddr_pa; + + IPA_WIGIG_DBG( + "periph_baddr_pa 0x%pa pseudo_cause_pa 0x%pa, int_gen_tx_pa 0x%pa, int_gen_rx_pa 0x%pa, dma_ep_misc_pa 0x%pa" + , &ipa_wigig_ctx->periph_baddr_pa, + &ipa_wigig_ctx->pseudo_cause_pa, + &ipa_wigig_ctx->int_gen_tx_pa, + &ipa_wigig_ctx->int_gen_rx_pa, + &ipa_wigig_ctx->dma_ep_misc_pa); + + inout.notify = in->notify; + inout.priv = in->priv; + if (ipa3_wigig_internal_init(&inout, in->int_notify, + &out->uc_db_pa)) { + kfree(ipa_wigig_ctx); + ipa_wigig_ctx = NULL; + return -EFAULT; + } + + IPA_WIGIG_DBG("uc_db_pa 0x%pa\n", &out->uc_db_pa); + + out->is_uc_ready = inout.is_uC_ready; + + out->lan_rx_napi_enable = ipa_get_lan_rx_napi(); + IPA_WIGIG_DBG("LAN RX NAPI enabled = %s\n", + out->lan_rx_napi_enable ? "True" : "False"); + + IPA_WIGIG_DBG("exit\n"); + + return 0; +} +EXPORT_SYMBOL(ipa_wigig_init); + +int ipa_wigig_cleanup(void) +{ + struct ipa_wigig_intf_info *entry; + struct ipa_wigig_intf_info *next; + + IPA_WIGIG_DBG("\n"); + + if (!ipa_wigig_ctx) + return -ENODEV; + + /* clear interface list */ + list_for_each_entry_safe(entry, next, + &ipa_wigig_ctx->head_intf_list, link) { + list_del(&entry->link); + kfree(entry); + } + + mutex_destroy(&ipa_wigig_ctx->lock); + + ipa_wigig_deinit_debugfs(); + + kfree(ipa_wigig_ctx); + ipa_wigig_ctx = NULL; + + IPA_WIGIG_DBG("exit\n"); + return 0; +} +EXPORT_SYMBOL(ipa_wigig_cleanup); + +bool ipa_wigig_is_smmu_enabled(void) +{ + struct ipa_smmu_in_params in; + struct ipa_smmu_out_params out; + + IPA_WIGIG_DBG("\n"); + + in.smmu_client = IPA_SMMU_WIGIG_CLIENT; + ipa_get_smmu_params(&in, &out); + + IPA_WIGIG_DBG("exit (%d)\n", out.smmu_enable); + + return out.smmu_enable; +} +EXPORT_SYMBOL(ipa_wigig_is_smmu_enabled); + +static int ipa_wigig_init_smmu_params(void) +{ + struct ipa_smmu_in_params in; + struct ipa_smmu_out_params out; + int ret; + + IPA_WIGIG_DBG("\n"); + + in.smmu_client = IPA_SMMU_WIGIG_CLIENT; + ret = ipa_get_smmu_params(&in, &out); + if (ret) { + IPA_WIGIG_ERR("couldn't get SMMU params %d\n", ret); + return ret; + } + ipa_wigig_ctx->smmu_en = out.smmu_enable; + ipa_wigig_ctx->shared_cb = out.shared_cb; + IPA_WIGIG_DBG("SMMU (%s), 11ad CB (%s)\n", + out.smmu_enable ? "enabled" : "disabled", + out.shared_cb ? "shared" : "not shared"); + + return 0; +} + +static int ipa_wigig_commit_partial_hdr( + struct ipa_ioc_add_hdr *hdr, + const char *netdev_name, + struct ipa_wigig_hdr_info *hdr_info) +{ + int i; + + IPA_WIGIG_DBG("\n"); + + if (!netdev_name) { + IPA_WIGIG_ERR("Invalid input\n"); + return -EINVAL; + } + + IPA_WIGIG_DBG("dst_mac_addr_offset %d hdr_len %d hdr_type %d\n", + hdr_info->dst_mac_addr_offset, + hdr_info->hdr_len, + hdr_info->hdr_type); + + hdr->commit = 0; + hdr->num_hdrs = 2; + + snprintf(hdr->hdr[0].name, sizeof(hdr->hdr[0].name), + "%s_ipv4", netdev_name); + snprintf(hdr->hdr[1].name, sizeof(hdr->hdr[1].name), + "%s_ipv6", netdev_name); + for (i = IPA_IP_v4; i < IPA_IP_MAX; i++) { + hdr->hdr[i].hdr_len = hdr_info[i].hdr_len; + memcpy(hdr->hdr[i].hdr, hdr_info[i].hdr, hdr->hdr[i].hdr_len); + hdr->hdr[i].type = hdr_info[i].hdr_type; + hdr->hdr[i].is_partial = 1; + hdr->hdr[i].is_eth2_ofst_valid = 1; + hdr->hdr[i].eth2_ofst = hdr_info[i].dst_mac_addr_offset; + } + + if (ipa_add_hdr(hdr)) { + IPA_WIGIG_ERR("fail to add partial headers\n"); + return -EFAULT; + } + + IPA_WIGIG_DBG("exit\n"); + + return 0; +} + +static int ipa_wigig_get_devname(char *netdev_name) +{ + struct ipa_wigig_intf_info *entry; + + mutex_lock(&ipa_wigig_ctx->lock); + + if (!list_is_singular(&ipa_wigig_ctx->head_intf_list)) { + IPA_WIGIG_DBG("list is not singular, was an IF registered?\n"); + mutex_unlock(&ipa_wigig_ctx->lock); + return -EFAULT; + } + entry = list_first_entry(&ipa_wigig_ctx->head_intf_list, + struct ipa_wigig_intf_info, + link); + strlcpy(netdev_name, entry->netdev_name, IPA_RESOURCE_NAME_MAX); + + mutex_unlock(&ipa_wigig_ctx->lock); + + return 0; +} + +int ipa_wigig_reg_intf( + struct ipa_wigig_reg_intf_in_params *in) +{ + struct ipa_wigig_intf_info *new_intf; + struct ipa_wigig_intf_info *entry; + struct ipa_tx_intf tx; + struct ipa_rx_intf rx; + struct ipa_ioc_tx_intf_prop tx_prop[2]; + struct ipa_ioc_rx_intf_prop rx_prop[2]; + struct ipa_ioc_add_hdr *hdr; + struct ipa_ioc_del_hdr *del_hdr = NULL; + u32 len; + int ret = 0; + + IPA_WIGIG_DBG("\n"); + + if (in == NULL) { + IPA_WIGIG_ERR("invalid params in=%pK\n", in); + return -EINVAL; + } + + if (!ipa_wigig_ctx) { + IPA_WIGIG_ERR("wigig ctx is not initialized\n"); + return -EPERM; + } + + IPA_WIGIG_DBG( + "register interface for netdev %s, MAC 0x[%X][%X][%X][%X][%X][%X]\n" + , in->netdev_name, + in->netdev_mac[0], in->netdev_mac[1], in->netdev_mac[2], + in->netdev_mac[3], in->netdev_mac[4], in->netdev_mac[5]); + + mutex_lock(&ipa_wigig_ctx->lock); + list_for_each_entry(entry, &ipa_wigig_ctx->head_intf_list, link) + if (strcmp(entry->netdev_name, in->netdev_name) == 0) { + IPA_WIGIG_DBG("intf was added before.\n"); + mutex_unlock(&ipa_wigig_ctx->lock); + return 0; + } + + IPA_WIGIG_DBG("intf was not added before, proceed.\n"); + new_intf = kzalloc(sizeof(*new_intf), GFP_KERNEL); + if (new_intf == NULL) { + ret = -ENOMEM; + goto fail; + } + + INIT_LIST_HEAD(&new_intf->link); + strlcpy(new_intf->netdev_name, in->netdev_name, + sizeof(new_intf->netdev_name)); + new_intf->hdr_len = in->hdr_info[0].hdr_len; + memcpy(new_intf->netdev_mac, in->netdev_mac, IPA_MAC_ADDR_SIZE); + + /* add partial header */ + len = sizeof(struct ipa_ioc_add_hdr) + 2 * sizeof(struct ipa_hdr_add); + hdr = kzalloc(len, GFP_KERNEL); + if (hdr == NULL) { + ret = -EFAULT; + goto fail_alloc_hdr; + } + + if (ipa_wigig_commit_partial_hdr(hdr, + in->netdev_name, + in->hdr_info)) { + IPA_WIGIG_ERR("fail to commit partial headers\n"); + ret = -EFAULT; + goto fail_commit_hdr; + } + + new_intf->partial_hdr_hdl[IPA_IP_v4] = hdr->hdr[IPA_IP_v4].hdr_hdl; + new_intf->partial_hdr_hdl[IPA_IP_v6] = hdr->hdr[IPA_IP_v6].hdr_hdl; + IPA_WIGIG_DBG("IPv4 hdr hdl: %d IPv6 hdr hdl: %d\n", + hdr->hdr[IPA_IP_v4].hdr_hdl, hdr->hdr[IPA_IP_v6].hdr_hdl); + + /* populate tx prop */ + tx.num_props = 2; + tx.prop = tx_prop; + + memset(tx_prop, 0, sizeof(tx_prop)); + tx_prop[0].ip = IPA_IP_v4; + /* + * for consumers, we register a default pipe, but IPACM will determine + * the actual pipe according to the relevant client MAC + */ + tx_prop[0].dst_pipe = IPA_CLIENT_WIGIG1_CONS; + tx_prop[0].hdr_l2_type = in->hdr_info[0].hdr_type; + strlcpy(tx_prop[0].hdr_name, hdr->hdr[IPA_IP_v4].name, + sizeof(tx_prop[0].hdr_name)); + + tx_prop[1].ip = IPA_IP_v6; + tx_prop[1].dst_pipe = IPA_CLIENT_WIGIG1_CONS; + tx_prop[1].hdr_l2_type = in->hdr_info[1].hdr_type; + strlcpy(tx_prop[1].hdr_name, hdr->hdr[IPA_IP_v6].name, + sizeof(tx_prop[1].hdr_name)); + + /* populate rx prop */ + rx.num_props = 2; + rx.prop = rx_prop; + + memset(rx_prop, 0, sizeof(rx_prop)); + rx_prop[0].ip = IPA_IP_v4; + rx_prop[0].src_pipe = IPA_CLIENT_WIGIG_PROD; + rx_prop[0].hdr_l2_type = in->hdr_info[0].hdr_type; + + rx_prop[1].ip = IPA_IP_v6; + rx_prop[1].src_pipe = IPA_CLIENT_WIGIG_PROD; + rx_prop[1].hdr_l2_type = in->hdr_info[1].hdr_type; + + if (ipa_register_intf(in->netdev_name, &tx, &rx)) { + IPA_WIGIG_ERR("fail to add interface prop\n"); + ret = -EFAULT; + goto fail_register; + } + + if (ipa_wigig_send_wlan_msg(WLAN_AP_CONNECT, + in->netdev_name, + in->netdev_mac)) { + IPA_WIGIG_ERR("couldn't send msg to IPACM\n"); + ret = -EFAULT; + goto fail_sendmsg; + } + + list_add(&new_intf->link, &ipa_wigig_ctx->head_intf_list); + + kfree(hdr); + mutex_unlock(&ipa_wigig_ctx->lock); + + IPA_WIGIG_DBG("exit\n"); + return 0; +fail_sendmsg: + ipa_deregister_intf(in->netdev_name); +fail_register: + del_hdr = kzalloc(sizeof(struct ipa_ioc_del_hdr) + + 2 * sizeof(struct ipa_hdr_del), GFP_KERNEL); + if (del_hdr) { + del_hdr->commit = 1; + del_hdr->num_hdls = 2; + del_hdr->hdl[0].hdl = new_intf->partial_hdr_hdl[IPA_IP_v4]; + del_hdr->hdl[1].hdl = new_intf->partial_hdr_hdl[IPA_IP_v6]; + ipa_del_hdr(del_hdr); + kfree(del_hdr); + } + new_intf->partial_hdr_hdl[IPA_IP_v4] = 0; + new_intf->partial_hdr_hdl[IPA_IP_v6] = 0; +fail_commit_hdr: + kfree(hdr); +fail_alloc_hdr: + kfree(new_intf); +fail: + mutex_unlock(&ipa_wigig_ctx->lock); + return ret; +} +EXPORT_SYMBOL(ipa_wigig_reg_intf); + +int ipa_wigig_dereg_intf(const char *netdev_name) +{ + int len, ret; + struct ipa_ioc_del_hdr *hdr = NULL; + struct ipa_wigig_intf_info *entry; + struct ipa_wigig_intf_info *next; + + if (!netdev_name) { + IPA_WIGIG_ERR("no netdev name\n"); + return -EINVAL; + } + + IPA_WIGIG_DBG("netdev %s\n", netdev_name); + + if (!ipa_wigig_ctx) { + IPA_WIGIG_ERR("wigig ctx is not initialized\n"); + return -EPERM; + } + + mutex_lock(&ipa_wigig_ctx->lock); + + ret = -EFAULT; + + list_for_each_entry_safe(entry, next, &ipa_wigig_ctx->head_intf_list, + link) + if (strcmp(entry->netdev_name, netdev_name) == 0) { + len = sizeof(struct ipa_ioc_del_hdr) + + 2 * sizeof(struct ipa_hdr_del); + hdr = kzalloc(len, GFP_KERNEL); + if (hdr == NULL) { + mutex_unlock(&ipa_wigig_ctx->lock); + return -ENOMEM; + } + + hdr->commit = 1; + hdr->num_hdls = 2; + hdr->hdl[0].hdl = entry->partial_hdr_hdl[0]; + hdr->hdl[1].hdl = entry->partial_hdr_hdl[1]; + IPA_WIGIG_DBG("IPv4 hdr hdl: %d IPv6 hdr hdl: %d\n", + hdr->hdl[0].hdl, hdr->hdl[1].hdl); + + if (ipa_del_hdr(hdr)) { + IPA_WIGIG_ERR( + "fail to delete partial header\n"); + ret = -EFAULT; + goto fail; + } + + if (ipa_deregister_intf(entry->netdev_name)) { + IPA_WIGIG_ERR("fail to del interface props\n"); + ret = -EFAULT; + goto fail; + } + + if (ipa_wigig_send_wlan_msg(WLAN_AP_DISCONNECT, + entry->netdev_name, + entry->netdev_mac)) { + IPA_WIGIG_ERR("couldn't send msg to IPACM\n"); + ret = -EFAULT; + goto fail; + } + + list_del(&entry->link); + kfree(entry); + + ret = 0; + break; + } + + IPA_WIGIG_DBG("exit\n"); +fail: + kfree(hdr); + mutex_unlock(&ipa_wigig_ctx->lock); + return ret; +} +EXPORT_SYMBOL(ipa_wigig_dereg_intf); + +static void ipa_wigig_pm_cb(void *p, enum ipa_pm_cb_event event) +{ + IPA_WIGIG_DBG("received pm event %d\n", event); +} + +static int ipa_wigig_store_pipe_info(struct ipa_wigig_pipe_setup_info *pipe, + unsigned int idx) +{ + IPA_WIGIG_DBG( + "idx %d: desc_ring HWHEAD_pa %pa, HWTAIL_pa %pa, status_ring HWHEAD_pa %pa, HWTAIL_pa %pa\n", + idx, + &pipe->desc_ring_HWHEAD_pa, + &pipe->desc_ring_HWTAIL_pa, + &pipe->status_ring_HWHEAD_pa, + &pipe->status_ring_HWTAIL_pa); + + /* store regs */ + ipa_wigig_ctx->pipes.flat[idx].desc_ring_HWHEAD_pa = + pipe->desc_ring_HWHEAD_pa; + ipa_wigig_ctx->pipes.flat[idx].desc_ring_HWTAIL_pa = + pipe->desc_ring_HWTAIL_pa; + + ipa_wigig_ctx->pipes.flat[idx].status_ring_HWHEAD_pa = + pipe->status_ring_HWHEAD_pa; + + ipa_wigig_ctx->pipes.flat[idx].status_ring_HWTAIL_pa = + pipe->status_ring_HWTAIL_pa; + + IPA_WIGIG_DBG("exit\n"); + + return 0; +} + +static u8 ipa_wigig_pipe_to_bit_val(int client) +{ + u8 shift_val; + + switch (client) { + case IPA_CLIENT_WIGIG_PROD: + shift_val = 0x1 << IPA_CLIENT_WIGIG_PROD_IDX; + break; + case IPA_CLIENT_WIGIG1_CONS: + shift_val = 0x1 << IPA_CLIENT_WIGIG1_CONS_IDX; + break; + case IPA_CLIENT_WIGIG2_CONS: + shift_val = 0x1 << IPA_CLIENT_WIGIG2_CONS_IDX; + break; + case IPA_CLIENT_WIGIG3_CONS: + shift_val = 0x1 << IPA_CLIENT_WIGIG3_CONS_IDX; + break; + case IPA_CLIENT_WIGIG4_CONS: + shift_val = 0x1 << IPA_CLIENT_WIGIG4_CONS_IDX; + break; + default: + IPA_WIGIG_ERR("invalid pipe %d\n", client); + return 1; + } + + return shift_val; +} + +int ipa_wigig_conn_rx_pipe(struct ipa_wigig_conn_rx_in_params *in, + struct ipa_wigig_conn_out_params *out) +{ + int ret; + struct ipa_pm_register_params pm_params; + + IPA_WIGIG_DBG("\n"); + + if (!in || !out) { + IPA_WIGIG_ERR("empty parameters. in=%pK out=%pK\n", in, out); + return -EINVAL; + } + + if (!ipa_wigig_ctx) { + IPA_WIGIG_ERR("wigig ctx is not initialized\n"); + return -EPERM; + } + + ret = ipa3_uc_state_check(); + if (ret) { + IPA_WIGIG_ERR("uC not ready\n"); + return ret; + } + + if (ipa_wigig_init_smmu_params()) + return -EINVAL; + + if (ipa_wigig_ctx->smmu_en) { + IPA_WIGIG_ERR("IPA SMMU is enabled, wrong API used\n"); + return -EFAULT; + } + + memset(&pm_params, 0, sizeof(pm_params)); + pm_params.name = "wigig"; + pm_params.callback = ipa_wigig_pm_cb; + pm_params.user_data = NULL; + pm_params.group = IPA_PM_GROUP_DEFAULT; + if (ipa_pm_register(&pm_params, &ipa_wigig_ctx->ipa_pm_hdl)) { + IPA_WIGIG_ERR("fail to register ipa pm\n"); + ret = -EFAULT; + goto fail_pm; + } + IPA_WIGIG_DBG("pm hdl %d\n", ipa_wigig_ctx->ipa_pm_hdl); + + ret = ipa3_wigig_uc_msi_init(true, + ipa_wigig_ctx->periph_baddr_pa, + ipa_wigig_ctx->pseudo_cause_pa, + ipa_wigig_ctx->int_gen_tx_pa, + ipa_wigig_ctx->int_gen_rx_pa, + ipa_wigig_ctx->dma_ep_misc_pa); + if (ret) { + IPA_WIGIG_ERR("failed configuring msi regs at uC\n"); + ret = -EFAULT; + goto fail_msi; + } + + if (ipa3_conn_wigig_rx_pipe_i(in, out, &ipa_wigig_ctx->parent)) { + IPA_WIGIG_ERR("fail to connect rx pipe\n"); + ret = -EFAULT; + goto fail_connect_pipe; + } + + ipa_wigig_ctx->tx_notify = in->notify; + ipa_wigig_ctx->priv = in->priv; + + if (ipa_wigig_ctx->parent) + ipa_wigig_init_debugfs(ipa_wigig_ctx->parent); + + ipa_wigig_store_pipe_info(ipa_wigig_ctx->pipes.flat, + IPA_CLIENT_WIGIG_PROD_IDX); + + ipa_wigig_ctx->conn_pipes |= + ipa_wigig_pipe_to_bit_val(IPA_CLIENT_WIGIG_PROD); + + IPA_WIGIG_DBG("exit\n"); + + return 0; + +fail_connect_pipe: + ipa3_wigig_uc_msi_init(false, + ipa_wigig_ctx->periph_baddr_pa, + ipa_wigig_ctx->pseudo_cause_pa, + ipa_wigig_ctx->int_gen_tx_pa, + ipa_wigig_ctx->int_gen_rx_pa, + ipa_wigig_ctx->dma_ep_misc_pa); +fail_msi: + ipa_pm_deregister(ipa_wigig_ctx->ipa_pm_hdl); +fail_pm: + return ret; +} +EXPORT_SYMBOL(ipa_wigig_conn_rx_pipe); + +static int ipa_wigig_client_to_idx(enum ipa_client_type client, + unsigned int *idx) +{ + switch (client) { + case IPA_CLIENT_WIGIG1_CONS: + *idx = 1; + break; + case IPA_CLIENT_WIGIG2_CONS: + *idx = 2; + break; + case IPA_CLIENT_WIGIG3_CONS: + *idx = 3; + break; + case IPA_CLIENT_WIGIG4_CONS: + *idx = 4; + break; + default: + IPA_WIGIG_ERR("invalid client %d\n", client); + return -EINVAL; + } + + return 0; +} + +static int ipa_wigig_clean_pipe_info(unsigned int idx) +{ + IPA_WIGIG_DBG("cleaning pipe %d info\n", idx); + + if (idx >= IPA_WIGIG_MAX_PIPES) { + IPA_WIGIG_ERR("invalid index %d\n", idx); + return -EINVAL; + } + + if (ipa_wigig_ctx->smmu_en) { + sg_free_table( + &ipa_wigig_ctx->pipes.smmu[idx].desc_ring_base); + sg_free_table( + &ipa_wigig_ctx->pipes.smmu[idx].status_ring_base); + + memset(ipa_wigig_ctx->pipes.smmu + idx, + 0, + sizeof(ipa_wigig_ctx->pipes.smmu[idx])); + } else { + memset(ipa_wigig_ctx->pipes.flat + idx, 0, + sizeof(ipa_wigig_ctx->pipes.flat[idx])); + } + + IPA_WIGIG_DBG("exit\n"); + + return 0; +} + +static int ipa_wigig_clone_sg_table(struct sg_table *source, + struct sg_table *dst) +{ + struct scatterlist *next, *s, *sglist; + int i, nents = source->nents; + + if (sg_alloc_table(dst, nents, GFP_KERNEL)) + return -EINVAL; + next = dst->sgl; + sglist = source->sgl; + for_each_sg(sglist, s, nents, i) { + *next = *s; + next = sg_next(next); + } + + dst->nents = nents; + dst->orig_nents = source->orig_nents; + + return 0; +} + +static int ipa_wigig_store_pipe_smmu_info + (struct ipa_wigig_pipe_setup_info_smmu *pipe_smmu, unsigned int idx) +{ + int ret; + + IPA_WIGIG_DBG( + "idx %d: desc_ring HWHEAD_pa %pa, HWTAIL_pa %pa, status_ring HWHEAD_pa %pa, HWTAIL_pa %pa, desc_ring_base 0x%llx, status_ring_base 0x%llx\n", + idx, + &pipe_smmu->desc_ring_HWHEAD_pa, + &pipe_smmu->desc_ring_HWTAIL_pa, + &pipe_smmu->status_ring_HWHEAD_pa, + &pipe_smmu->status_ring_HWTAIL_pa, + (unsigned long long)pipe_smmu->desc_ring_base_iova, + (unsigned long long)pipe_smmu->status_ring_base_iova); + + /* store regs */ + ipa_wigig_ctx->pipes.smmu[idx].desc_ring_HWHEAD_pa = + pipe_smmu->desc_ring_HWHEAD_pa; + ipa_wigig_ctx->pipes.smmu[idx].desc_ring_HWTAIL_pa = + pipe_smmu->desc_ring_HWTAIL_pa; + + ipa_wigig_ctx->pipes.smmu[idx].status_ring_HWHEAD_pa = + pipe_smmu->status_ring_HWHEAD_pa; + ipa_wigig_ctx->pipes.smmu[idx].status_ring_HWTAIL_pa = + pipe_smmu->status_ring_HWTAIL_pa; + + /* store rings IOVAs */ + ipa_wigig_ctx->pipes.smmu[idx].desc_ring_base_iova = + pipe_smmu->desc_ring_base_iova; + ipa_wigig_ctx->pipes.smmu[idx].status_ring_base_iova = + pipe_smmu->status_ring_base_iova; + + /* copy sgt */ + ret = ipa_wigig_clone_sg_table( + &pipe_smmu->desc_ring_base, + &ipa_wigig_ctx->pipes.smmu[idx].desc_ring_base); + if (ret) + goto fail_desc; + + ret = ipa_wigig_clone_sg_table( + &pipe_smmu->status_ring_base, + &ipa_wigig_ctx->pipes.smmu[idx].status_ring_base); + if (ret) + goto fail_stat; + + IPA_WIGIG_DBG("exit\n"); + + return 0; +fail_stat: + sg_free_table(&ipa_wigig_ctx->pipes.smmu[idx].desc_ring_base); + memset(&ipa_wigig_ctx->pipes.smmu[idx].desc_ring_base, 0, + sizeof(ipa_wigig_ctx->pipes.smmu[idx].desc_ring_base)); +fail_desc: + return ret; +} + +static int ipa_wigig_get_pipe_smmu_info( + struct ipa_wigig_pipe_setup_info_smmu **pipe_smmu, unsigned int idx) +{ + if (idx >= IPA_WIGIG_MAX_PIPES) { + IPA_WIGIG_ERR("exceeded pipe num %d > %d\n", + idx, IPA_WIGIG_MAX_PIPES); + return -EINVAL; + } + + *pipe_smmu = &ipa_wigig_ctx->pipes.smmu[idx]; + + return 0; +} + +static int ipa_wigig_get_pipe_info( + struct ipa_wigig_pipe_setup_info **pipe, unsigned int idx) +{ + if (idx >= IPA_WIGIG_MAX_PIPES) { + IPA_WIGIG_ERR("exceeded pipe num %d >= %d\n", idx, + IPA_WIGIG_MAX_PIPES); + return -EINVAL; + } + + *pipe = &ipa_wigig_ctx->pipes.flat[idx]; + + return 0; +} + +static int ipa_wigig_get_regs_addr( + void __iomem **desc_ring_h, void __iomem **desc_ring_t, + void __iomem **status_ring_h, void __iomem **status_ring_t, + unsigned int idx) +{ + struct ipa_wigig_pipe_setup_info *pipe; + struct ipa_wigig_pipe_setup_info_smmu *pipe_smmu; + int ret = 0; + + IPA_WIGIG_DBG("\n"); + + if (idx >= IPA_WIGIG_MAX_PIPES) { + IPA_WIGIG_DBG("exceeded pipe num %d >= %d\n", idx, + IPA_WIGIG_MAX_PIPES); + return -EINVAL; + } + + if (!ipa_wigig_ctx) { + IPA_WIGIG_DBG("wigig ctx is not initialized\n"); + return -EPERM; + } + + if (!(ipa_wigig_ctx->conn_pipes & + ipa_wigig_pipe_to_bit_val(IPA_CLIENT_WIGIG_PROD))) { + IPA_WIGIG_DBG( + "must connect rx pipe before connecting any client\n"); + return -EINVAL; + } + + if (ipa_wigig_ctx->smmu_en) { + ret = ipa_wigig_get_pipe_smmu_info(&pipe_smmu, idx); + if (ret) + return -EINVAL; + + *desc_ring_h = + ioremap(pipe_smmu->desc_ring_HWHEAD_pa, sizeof(u32)); + if (!*desc_ring_h) { + IPA_WIGIG_DBG( + "couldn't ioremap desc ring head address\n"); + ret = -EINVAL; + goto fail_map_desc_h; + } + *desc_ring_t = + ioremap(pipe_smmu->desc_ring_HWTAIL_pa, sizeof(u32)); + if (!*desc_ring_t) { + IPA_WIGIG_DBG( + "couldn't ioremap desc ring tail address\n"); + ret = -EINVAL; + goto fail_map_desc_t; + } + *status_ring_h = + ioremap(pipe_smmu->status_ring_HWHEAD_pa, sizeof(u32)); + if (!*status_ring_h) { + IPA_WIGIG_DBG( + "couldn't ioremap status ring head address\n"); + ret = -EINVAL; + goto fail_map_status_h; + } + *status_ring_t = + ioremap(pipe_smmu->status_ring_HWTAIL_pa, sizeof(u32)); + if (!*status_ring_t) { + IPA_WIGIG_DBG( + "couldn't ioremap status ring tail address\n"); + ret = -EINVAL; + goto fail_map_status_t; + } + } else { + ret = ipa_wigig_get_pipe_info(&pipe, idx); + if (ret) + return -EINVAL; + + *desc_ring_h = ioremap(pipe->desc_ring_HWHEAD_pa, sizeof(u32)); + if (!*desc_ring_h) { + IPA_WIGIG_DBG( + "couldn't ioremap desc ring head address\n"); + ret = -EINVAL; + goto fail_map_desc_h; + } + *desc_ring_t = ioremap(pipe->desc_ring_HWTAIL_pa, sizeof(u32)); + if (!*desc_ring_t) { + IPA_WIGIG_DBG( + "couldn't ioremap desc ring tail address\n"); + ret = -EINVAL; + goto fail_map_desc_t; + } + *status_ring_h = + ioremap(pipe->status_ring_HWHEAD_pa, sizeof(u32)); + if (!*status_ring_h) { + IPA_WIGIG_DBG( + "couldn't ioremap status ring head address\n"); + ret = -EINVAL; + goto fail_map_status_h; + } + *status_ring_t = + ioremap(pipe->status_ring_HWTAIL_pa, sizeof(u32)); + if (!*status_ring_t) { + IPA_WIGIG_DBG( + "couldn't ioremap status ring tail address\n"); + ret = -EINVAL; + goto fail_map_status_t; + } + } + + IPA_WIGIG_DBG("exit\n"); + return 0; + +fail_map_status_t: + iounmap(*status_ring_h); +fail_map_status_h: + iounmap(*desc_ring_t); +fail_map_desc_t: + iounmap(*desc_ring_h); +fail_map_desc_h: + IPA_WIGIG_DBG("couldn't get regs information idx %d\n", idx); + return ret; +} + +int ipa_wigig_save_regs(void) +{ + void __iomem *desc_ring_h = NULL, *desc_ring_t = NULL, + *status_ring_h = NULL, *status_ring_t = NULL, + *int_gen_rx_pa = NULL, *int_gen_tx_pa = NULL; + uint32_t readval; + u8 pipe_connected; + int i, ret = 0; + + IPA_WIGIG_DBG("Start collecting pipes information\n"); + + if (!ipa_wigig_ctx) { + IPA_WIGIG_ERR("wigig ctx is not initialized\n"); + return -EPERM; + } + if (!(ipa_wigig_ctx->conn_pipes & + ipa_wigig_pipe_to_bit_val(IPA_CLIENT_WIGIG_PROD))) { + IPA_WIGIG_ERR( + "must connect rx pipe before connecting any client\n"); + return -EINVAL; + } + + for (i = 0; i < IPA_WIGIG_MAX_PIPES; i++) { + pipe_connected = (ipa_wigig_ctx->conn_pipes & (0x1 << i)); + if (pipe_connected) { + uint32_t mask; + uint8_t shift; + + ret = ipa_wigig_get_regs_addr( + &desc_ring_h, &desc_ring_t, + &status_ring_h, &status_ring_t, i); + + if (ret) { + IPA_WIGIG_ERR( + "couldn't get registers information on client %d\n", + i); + return -EINVAL; + } + + IPA_WIGIG_DBG("collecting pipe info of index %d\n", i); + if (i == IPA_CLIENT_WIGIG_PROD_IDX) { + ipa_wigig_ctx->regs_save.pipes_val[i].dir = 0; + } else { + ipa_wigig_ctx->regs_save.pipes_val[i].dir = 1; + /* TX ids start from 2 */ + ipa_wigig_ctx->regs_save.pipes_val[i] + .tx_ring_id = i + 1; + } + + readval = readl_relaxed(desc_ring_h); + ipa_wigig_ctx->regs_save.pipes_val[i].desc_ring_HWHEAD = + readval; + /* HWHEAD LSbs are for even IDs, MSbs for odd IDs */ + if (i != IPA_CLIENT_WIGIG_PROD_IDX) { + mask = 0xFFFF0000; + shift = 16; + + if ((ipa_wigig_ctx->regs_save.pipes_val[i] + .tx_ring_id % 2) == 0) { + mask = 0x0000FFFF; + shift = 0; + } + ipa_wigig_ctx->regs_save.pipes_val[i] + .desc_ring_HWHEAD_masked = + (readval & mask) >> shift; + } + readval = readl_relaxed(desc_ring_t); + ipa_wigig_ctx->regs_save.pipes_val[i].desc_ring_HWTAIL = + readval; + readval = readl_relaxed(status_ring_h); + ipa_wigig_ctx->regs_save.pipes_val[i] + .status_ring_HWHEAD = readval; + /* two status rings, MSbs for RX LSbs for TX */ + if (i == IPA_CLIENT_WIGIG_PROD_IDX) { + mask = 0xFFFF0000; + shift = 16; + } else { + mask = 0x0000FFFF; + shift = 0; + } + ipa_wigig_ctx->regs_save.pipes_val[i] + .status_ring_HWHEAD_masked = + (readval & mask) >> shift; + + readval = readl_relaxed(status_ring_t); + ipa_wigig_ctx->regs_save.pipes_val[i] + .status_ring_HWTAIL = readval; + /* unmap all regs */ + iounmap(desc_ring_h); + iounmap(desc_ring_t); + iounmap(status_ring_h); + iounmap(status_ring_t); + } + } + int_gen_rx_pa = ioremap(ipa_wigig_ctx->int_gen_rx_pa, sizeof(u32)); + if (!int_gen_rx_pa) { + IPA_WIGIG_ERR("couldn't ioremap gen rx address\n"); + ret = -EINVAL; + goto fail_map_gen_rx; + } + int_gen_tx_pa = ioremap(ipa_wigig_ctx->int_gen_tx_pa, sizeof(u32)); + if (!int_gen_tx_pa) { + IPA_WIGIG_ERR("couldn't ioremap gen tx address\n"); + ret = -EINVAL; + goto fail_map_gen_tx; + } + + IPA_WIGIG_DBG("collecting int_gen_rx_pa info\n"); + readval = readl_relaxed(int_gen_rx_pa); + ipa_wigig_ctx->regs_save.int_gen_rx_val = readval; + + IPA_WIGIG_DBG("collecting int_gen_tx_pa info\n"); + readval = readl_relaxed(int_gen_tx_pa); + ipa_wigig_ctx->regs_save.int_gen_tx_val = readval; + + IPA_WIGIG_DBG("Finish collecting pipes info\n"); + IPA_WIGIG_DBG("exit\n"); + + iounmap(int_gen_tx_pa); +fail_map_gen_tx: + iounmap(int_gen_rx_pa); +fail_map_gen_rx: + return ret; +} +EXPORT_SYMBOL(ipa_wigig_save_regs); + +static void ipa_wigig_clean_rx_buff_smmu_info(void) +{ + IPA_WIGIG_DBG("clearing rx buff smmu info\n"); + + sg_free_table(&ipa_wigig_ctx->rx_buff_smmu.data_buffer_base); + memset(&ipa_wigig_ctx->rx_buff_smmu, + 0, + sizeof(ipa_wigig_ctx->rx_buff_smmu)); + + IPA_WIGIG_DBG("\n"); +} + +static int ipa_wigig_store_rx_buff_smmu_info( + struct ipa_wigig_rx_pipe_data_buffer_info_smmu *dbuff_smmu) +{ + IPA_WIGIG_DBG("\n"); + if (ipa_wigig_clone_sg_table(&dbuff_smmu->data_buffer_base, + &ipa_wigig_ctx->rx_buff_smmu.data_buffer_base)) + return -EINVAL; + + ipa_wigig_ctx->rx_buff_smmu.data_buffer_base_iova = + dbuff_smmu->data_buffer_base_iova; + ipa_wigig_ctx->rx_buff_smmu.data_buffer_size = + dbuff_smmu->data_buffer_size; + + IPA_WIGIG_DBG("exit\n"); + + return 0; +} + +static int ipa_wigig_get_rx_buff_smmu_info( + struct ipa_wigig_rx_pipe_data_buffer_info_smmu **dbuff_smmu) +{ + IPA_WIGIG_DBG("\n"); + + *dbuff_smmu = &ipa_wigig_ctx->rx_buff_smmu; + + IPA_WIGIG_DBG("exit\n"); + + return 0; +} + +static int ipa_wigig_store_tx_buff_smmu_info( + struct ipa_wigig_tx_pipe_data_buffer_info_smmu *dbuff_smmu, + unsigned int idx) +{ + int result, i; + struct ipa_wigig_tx_pipe_data_buffer_info_smmu *tx_buff_smmu; + + IPA_WIGIG_DBG("\n"); + + if (idx > (IPA_WIGIG_TX_PIPE_NUM - 1)) { + IPA_WIGIG_ERR("invalid tx index %d\n", idx); + return -EINVAL; + } + + tx_buff_smmu = ipa_wigig_ctx->tx_buff_smmu + idx; + + tx_buff_smmu->data_buffer_base = + kcalloc(dbuff_smmu->num_buffers, + sizeof(struct sg_table), + GFP_KERNEL); + if (!tx_buff_smmu->data_buffer_base) + return -ENOMEM; + + tx_buff_smmu->data_buffer_base_iova = + kcalloc(dbuff_smmu->num_buffers, sizeof(u64), GFP_KERNEL); + if (!tx_buff_smmu->data_buffer_base_iova) { + result = -ENOMEM; + goto fail_iova; + } + + for (i = 0; i < dbuff_smmu->num_buffers; i++) { + result = ipa_wigig_clone_sg_table( + dbuff_smmu->data_buffer_base + i, + tx_buff_smmu->data_buffer_base + i); + if (result) + goto fail_sg_clone; + + tx_buff_smmu->data_buffer_base_iova[i] = + dbuff_smmu->data_buffer_base_iova[i]; + } + tx_buff_smmu->num_buffers = dbuff_smmu->num_buffers; + tx_buff_smmu->data_buffer_size = + dbuff_smmu->data_buffer_size; + + IPA_WIGIG_DBG("exit\n"); + + return 0; +fail_sg_clone: + i--; + for (; i >= 0; i--) + sg_free_table(tx_buff_smmu->data_buffer_base + i); + kfree(tx_buff_smmu->data_buffer_base_iova); + tx_buff_smmu->data_buffer_base_iova = NULL; +fail_iova: + kfree(tx_buff_smmu->data_buffer_base); + tx_buff_smmu->data_buffer_base = NULL; + return result; +} + +static int ipa_wigig_clean_tx_buff_smmu_info(unsigned int idx) +{ + unsigned int i; + struct ipa_wigig_tx_pipe_data_buffer_info_smmu *dbuff_smmu; + + IPA_WIGIG_DBG("\n"); + + if (idx > (IPA_WIGIG_TX_PIPE_NUM - 1)) { + IPA_WIGIG_ERR("invalid tx index %d\n", idx); + return -EINVAL; + } + + dbuff_smmu = &ipa_wigig_ctx->tx_buff_smmu[idx]; + + if (!dbuff_smmu->data_buffer_base) { + IPA_WIGIG_ERR("no pa has been allocated\n"); + return -EFAULT; + } + + for (i = 0; i < dbuff_smmu->num_buffers; i++) + sg_free_table(dbuff_smmu->data_buffer_base + i); + + kfree(dbuff_smmu->data_buffer_base); + dbuff_smmu->data_buffer_base = NULL; + + kfree(dbuff_smmu->data_buffer_base_iova); + dbuff_smmu->data_buffer_base_iova = NULL; + + dbuff_smmu->data_buffer_size = 0; + dbuff_smmu->num_buffers = 0; + + IPA_WIGIG_DBG("exit\n"); + + return 0; +} + +static int ipa_wigig_get_tx_buff_smmu_info( +struct ipa_wigig_tx_pipe_data_buffer_info_smmu **dbuff_smmu, + unsigned int idx) +{ + if (idx > (IPA_WIGIG_TX_PIPE_NUM - 1)) { + IPA_WIGIG_ERR("invalid tx index %d\n", idx); + return -EINVAL; + } + + *dbuff_smmu = &ipa_wigig_ctx->tx_buff_smmu[idx]; + + return 0; +} + +static int ipa_wigig_store_rx_smmu_info + (struct ipa_wigig_conn_rx_in_params_smmu *in) +{ + int ret; + + IPA_WIGIG_DBG("\n"); + + ret = ipa_wigig_store_pipe_smmu_info(&in->pipe_smmu, + IPA_CLIENT_WIGIG_PROD_IDX); + if (ret) + return ret; + + if (!ipa_wigig_ctx->shared_cb) { + ret = ipa_wigig_store_rx_buff_smmu_info(&in->dbuff_smmu); + if (ret) + goto fail_buff; + } + + IPA_WIGIG_DBG("exit\n"); + + return 0; + +fail_buff: + ipa_wigig_clean_pipe_info(IPA_CLIENT_WIGIG_PROD_IDX); + return ret; +} + +static int ipa_wigig_store_client_smmu_info +(struct ipa_wigig_conn_tx_in_params_smmu *in, enum ipa_client_type client) +{ + int ret; + unsigned int idx; + + IPA_WIGIG_DBG("\n"); + + ret = ipa_wigig_client_to_idx(client, &idx); + if (ret) + return ret; + + ret = ipa_wigig_store_pipe_smmu_info(&in->pipe_smmu, idx); + if (ret) + return ret; + + if (!ipa_wigig_ctx->shared_cb) { + ret = ipa_wigig_store_tx_buff_smmu_info( + &in->dbuff_smmu, idx - 1); + if (ret) + goto fail_buff; + } + + IPA_WIGIG_DBG("exit\n"); + + return 0; + +fail_buff: + ipa_wigig_clean_pipe_info(IPA_CLIENT_WIGIG_PROD_IDX); + return ret; +} + +static int ipa_wigig_get_rx_smmu_info( + struct ipa_wigig_pipe_setup_info_smmu **pipe_smmu, + struct ipa_wigig_rx_pipe_data_buffer_info_smmu **dbuff_smmu) +{ + int ret; + + ret = ipa_wigig_get_pipe_smmu_info(pipe_smmu, + IPA_CLIENT_WIGIG_PROD_IDX); + if (ret) + return ret; + + ret = ipa_wigig_get_rx_buff_smmu_info(dbuff_smmu); + if (ret) + return ret; + + return 0; +} + +static int ipa_wigig_get_tx_smmu_info( + struct ipa_wigig_pipe_setup_info_smmu **pipe_smmu, + struct ipa_wigig_tx_pipe_data_buffer_info_smmu **dbuff_smmu, + enum ipa_client_type client) +{ + unsigned int idx; + int ret; + + ret = ipa_wigig_client_to_idx(client, &idx); + if (ret) + return ret; + + ret = ipa_wigig_get_pipe_smmu_info(pipe_smmu, idx); + if (ret) + return ret; + + ret = ipa_wigig_get_tx_buff_smmu_info(dbuff_smmu, idx - 1); + if (ret) + return ret; + + return 0; +} + +static int ipa_wigig_clean_smmu_info(enum ipa_client_type client) +{ + int ret; + + if (client == IPA_CLIENT_WIGIG_PROD) { + ret = ipa_wigig_clean_pipe_info(IPA_CLIENT_WIGIG_PROD_IDX); + if (ret) + return ret; + if (!ipa_wigig_ctx->shared_cb) + ipa_wigig_clean_rx_buff_smmu_info(); + } else { + unsigned int idx; + + ret = ipa_wigig_client_to_idx(client, &idx); + if (ret) + return ret; + + ret = ipa_wigig_clean_pipe_info(idx); + if (ret) + return ret; + + if (!ipa_wigig_ctx->shared_cb) { + ret = ipa_wigig_clean_tx_buff_smmu_info(idx - 1); + if (ret) { + IPA_WIGIG_ERR( + "cleaned tx pipe info but wasn't able to clean buff info, client %d\n" + , client); + WARN_ON(1); + return ret; + } + } + } + + return 0; +} +int ipa_wigig_conn_rx_pipe_smmu( + struct ipa_wigig_conn_rx_in_params_smmu *in, + struct ipa_wigig_conn_out_params *out) +{ + int ret; + struct ipa_pm_register_params pm_params; + + IPA_WIGIG_DBG("\n"); + + if (!in || !out) { + IPA_WIGIG_ERR("empty parameters. in=%pK out=%pK\n", in, out); + return -EINVAL; + } + + if (!ipa_wigig_ctx) { + IPA_WIGIG_ERR("wigig ctx is not initialized\n"); + return -EPERM; + } + + ret = ipa3_uc_state_check(); + if (ret) { + IPA_WIGIG_ERR("uC not ready\n"); + return ret; + } + + if (ipa_wigig_init_smmu_params()) + return -EINVAL; + + if (!ipa_wigig_ctx->smmu_en) { + IPA_WIGIG_ERR("IPA SMMU is disabled, wrong API used\n"); + return -EFAULT; + } + + memset(&pm_params, 0, sizeof(pm_params)); + pm_params.name = "wigig"; + pm_params.callback = ipa_wigig_pm_cb; + pm_params.user_data = NULL; + pm_params.group = IPA_PM_GROUP_DEFAULT; + if (ipa_pm_register(&pm_params, &ipa_wigig_ctx->ipa_pm_hdl)) { + IPA_WIGIG_ERR("fail to register ipa pm\n"); + ret = -EFAULT; + goto fail_pm; + } + + ret = ipa3_wigig_uc_msi_init(true, + ipa_wigig_ctx->periph_baddr_pa, + ipa_wigig_ctx->pseudo_cause_pa, + ipa_wigig_ctx->int_gen_tx_pa, + ipa_wigig_ctx->int_gen_rx_pa, + ipa_wigig_ctx->dma_ep_misc_pa); + if (ret) { + IPA_WIGIG_ERR("failed configuring msi regs at uC\n"); + ret = -EFAULT; + goto fail_msi; + } + + if (ipa3_conn_wigig_rx_pipe_i(in, out, &ipa_wigig_ctx->parent)) { + IPA_WIGIG_ERR("fail to connect rx pipe\n"); + ret = -EFAULT; + goto fail_connect_pipe; + } + + if (ipa_wigig_ctx->parent) + ipa_wigig_init_debugfs(ipa_wigig_ctx->parent); + + if (ipa_wigig_store_rx_smmu_info(in)) { + IPA_WIGIG_ERR("fail to store smmu data for rx pipe\n"); + ret = -EFAULT; + goto fail_smmu_store; + } + + ipa_wigig_ctx->tx_notify = in->notify; + ipa_wigig_ctx->priv = in->priv; + + ipa_wigig_ctx->conn_pipes |= + ipa_wigig_pipe_to_bit_val(IPA_CLIENT_WIGIG_PROD); + + IPA_WIGIG_DBG("exit\n"); + + return 0; + +fail_smmu_store: + ipa3_disconn_wigig_pipe_i(IPA_CLIENT_WIGIG_PROD, + &in->pipe_smmu, + &in->dbuff_smmu); +fail_connect_pipe: + ipa3_wigig_uc_msi_init(false, + ipa_wigig_ctx->periph_baddr_pa, + ipa_wigig_ctx->pseudo_cause_pa, + ipa_wigig_ctx->int_gen_tx_pa, + ipa_wigig_ctx->int_gen_rx_pa, + ipa_wigig_ctx->dma_ep_misc_pa); +fail_msi: + ipa_pm_deregister(ipa_wigig_ctx->ipa_pm_hdl); +fail_pm: + return ret; +} +EXPORT_SYMBOL(ipa_wigig_conn_rx_pipe_smmu); + +int ipa_wigig_set_perf_profile(u32 max_supported_bw_mbps) +{ + IPA_WIGIG_DBG("setting throughput to %d\n", max_supported_bw_mbps); + + if (!ipa_wigig_ctx) { + IPA_WIGIG_ERR("wigig ctx is not initialized\n"); + return -EPERM; + } + + IPA_WIGIG_DBG("ipa_pm handle %d\n", ipa_wigig_ctx->ipa_pm_hdl); + if (ipa_pm_set_throughput(ipa_wigig_ctx->ipa_pm_hdl, + max_supported_bw_mbps)) { + IPA_WIGIG_ERR("fail to setup pm perf profile\n"); + return -EFAULT; + } + IPA_WIGIG_DBG("exit\n"); + + return 0; +} +EXPORT_SYMBOL(ipa_wigig_set_perf_profile); + +static int ipa_wigig_store_client_mac(enum ipa_client_type client, + const char *mac) +{ + unsigned int idx; + + if (ipa_wigig_client_to_idx(client, &idx)) { + IPA_WIGIG_ERR("couldn't acquire idx\n"); + return -EFAULT; + } + memcpy(ipa_wigig_ctx->clients_mac[idx - 1], mac, IPA_MAC_ADDR_SIZE); + return 0; +} + +static int ipa_wigig_get_client_mac(enum ipa_client_type client, char *mac) +{ + unsigned int idx; + + if (ipa_wigig_client_to_idx(client, &idx)) { + IPA_WIGIG_ERR("couldn't acquire idx\n"); + return -EFAULT; + } + memcpy(mac, ipa_wigig_ctx->clients_mac[idx - 1], IPA_MAC_ADDR_SIZE); + return 0; +} + +static int ipa_wigig_clean_client_mac(enum ipa_client_type client) +{ + char zero_mac[IPA_MAC_ADDR_SIZE] = { 0 }; + + return ipa_wigig_store_client_mac(client, zero_mac); +} + +int ipa_wigig_conn_client(struct ipa_wigig_conn_tx_in_params *in, + struct ipa_wigig_conn_out_params *out) +{ + char dev_name[IPA_RESOURCE_NAME_MAX]; + unsigned int idx; + + IPA_WIGIG_DBG("\n"); + + if (!in || !out) { + IPA_WIGIG_ERR("empty parameters. in=%pK out=%pK\n", in, out); + return -EINVAL; + } + + if (!ipa_wigig_ctx) { + IPA_WIGIG_ERR("wigig ctx is not initialized\n"); + return -EPERM; + } + + if (!(ipa_wigig_ctx->conn_pipes & + ipa_wigig_pipe_to_bit_val(IPA_CLIENT_WIGIG_PROD))) { + IPA_WIGIG_ERR( + "must connect rx pipe before connecting any client\n" + ); + return -EINVAL; + } + + if (ipa_wigig_ctx->smmu_en) { + IPA_WIGIG_ERR("IPA SMMU is enabled, wrong API used\n"); + return -EFAULT; + } + + if (ipa3_uc_state_check()) { + IPA_WIGIG_ERR("uC not ready\n"); + return -EFAULT; + } + + if (ipa_wigig_get_devname(dev_name)) { + IPA_WIGIG_ERR("couldn't get dev name\n"); + return -EFAULT; + } + + if (ipa3_conn_wigig_client_i(in, out, ipa_wigig_ctx->tx_notify, + ipa_wigig_ctx->priv)) { + IPA_WIGIG_ERR( + "fail to connect client. MAC [%X][%X][%X][%X][%X][%X]\n" + , in->client_mac[0], in->client_mac[1], in->client_mac[2] + , in->client_mac[3], in->client_mac[4], in->client_mac[5]); + return -EFAULT; + } + + if (ipa_wigig_client_to_idx(out->client, &idx)) { + IPA_WIGIG_ERR("couldn't acquire idx\n"); + goto fail_convert_client_to_idx; + } + + ipa_wigig_store_pipe_info(&in->pipe, idx); + + if (ipa_wigig_send_msg(WIGIG_CLIENT_CONNECT, + dev_name, + in->client_mac, out->client, false)) { + IPA_WIGIG_ERR("couldn't send msg to IPACM\n"); + goto fail_sendmsg; + } + + /* update connected clients */ + ipa_wigig_ctx->conn_pipes |= + ipa_wigig_pipe_to_bit_val(out->client); + + ipa_wigig_store_client_mac(out->client, in->client_mac); + + IPA_WIGIG_DBG("exit\n"); + return 0; + +fail_sendmsg: + ipa_wigig_clean_pipe_info(idx); +fail_convert_client_to_idx: + ipa3_disconn_wigig_pipe_i(out->client, NULL, NULL); + return -EINVAL; +} +EXPORT_SYMBOL(ipa_wigig_conn_client); + +int ipa_wigig_conn_client_smmu( + struct ipa_wigig_conn_tx_in_params_smmu *in, + struct ipa_wigig_conn_out_params *out) +{ + char netdev_name[IPA_RESOURCE_NAME_MAX]; + int ret; + + IPA_WIGIG_DBG("\n"); + + if (!in || !out) { + IPA_WIGIG_ERR("empty parameters. in=%pK out=%pK\n", in, out); + return -EINVAL; + } + + if (!ipa_wigig_ctx) { + IPA_WIGIG_ERR("wigig ctx is not initialized\n"); + return -EPERM; + } + + if (!(ipa_wigig_ctx->conn_pipes & + ipa_wigig_pipe_to_bit_val(IPA_CLIENT_WIGIG_PROD))) { + IPA_WIGIG_ERR( + "must connect rx pipe before connecting any client\n" + ); + return -EINVAL; + } + + if (!ipa_wigig_ctx->smmu_en) { + IPA_WIGIG_ERR("IPA SMMU is disabled, wrong API used\n"); + return -EFAULT; + } + + ret = ipa3_uc_state_check(); + if (ret) { + IPA_WIGIG_ERR("uC not ready\n"); + return ret; + } + + if (ipa_wigig_get_devname(netdev_name)) { + IPA_WIGIG_ERR("couldn't get dev name\n"); + return -EFAULT; + } + + if (ipa3_conn_wigig_client_i(in, out, ipa_wigig_ctx->tx_notify, + ipa_wigig_ctx->priv)) { + IPA_WIGIG_ERR( + "fail to connect client. MAC [%X][%X][%X][%X][%X][%X]\n" + , in->client_mac[0], in->client_mac[1] + , in->client_mac[2], in->client_mac[3] + , in->client_mac[4], in->client_mac[5]); + return -EFAULT; + } + + if (ipa_wigig_send_msg(WIGIG_CLIENT_CONNECT, + netdev_name, + in->client_mac, out->client, false)) { + IPA_WIGIG_ERR("couldn't send msg to IPACM\n"); + ret = -EFAULT; + goto fail_sendmsg; + } + + ret = ipa_wigig_store_client_smmu_info(in, out->client); + if (ret) + goto fail_smmu; + + /* update connected clients */ + ipa_wigig_ctx->conn_pipes |= + ipa_wigig_pipe_to_bit_val(out->client); + + ipa_wigig_store_client_mac(out->client, in->client_mac); + + IPA_WIGIG_DBG("exit\n"); + return 0; + +fail_smmu: + /* + * wigig clients are disconnected with legacy message since there is + * no need to send ep, client MAC is sufficient for disconnect + */ + ipa_wigig_send_wlan_msg(WLAN_CLIENT_DISCONNECT, netdev_name, + in->client_mac); +fail_sendmsg: + ipa3_disconn_wigig_pipe_i(out->client, &in->pipe_smmu, &in->dbuff_smmu); + return ret; +} +EXPORT_SYMBOL(ipa_wigig_conn_client_smmu); + +static inline int ipa_wigig_validate_client_type(enum ipa_client_type client) +{ + switch (client) { + case IPA_CLIENT_WIGIG_PROD: + case IPA_CLIENT_WIGIG1_CONS: + case IPA_CLIENT_WIGIG2_CONS: + case IPA_CLIENT_WIGIG3_CONS: + case IPA_CLIENT_WIGIG4_CONS: + break; + default: + IPA_WIGIG_ERR_RL("invalid client type %d\n", client); + return -EINVAL; + } + + return 0; +} + +int ipa_wigig_disconn_pipe(enum ipa_client_type client) +{ + int ret; + char dev_name[IPA_RESOURCE_NAME_MAX]; + char client_mac[IPA_MAC_ADDR_SIZE]; + + IPA_WIGIG_DBG("\n"); + + ret = ipa_wigig_validate_client_type(client); + if (ret) + return ret; + + if (client != IPA_CLIENT_WIGIG_PROD) { + if (ipa_wigig_get_devname(dev_name)) { + IPA_WIGIG_ERR("couldn't get dev name\n"); + return -EFAULT; + } + + if (ipa_wigig_get_client_mac(client, client_mac)) { + IPA_WIGIG_ERR("couldn't get client mac\n"); + return -EFAULT; + } + } + + IPA_WIGIG_DBG("disconnecting ipa_client_type %d\n", client); + + if (ipa_wigig_is_smmu_enabled()) { + struct ipa_wigig_pipe_setup_info_smmu *pipe_smmu; + struct ipa_wigig_rx_pipe_data_buffer_info_smmu *rx_dbuff_smmu; + struct ipa_wigig_tx_pipe_data_buffer_info_smmu *tx_dbuff_smmu; + + if (client == IPA_CLIENT_WIGIG_PROD) { + ret = ipa_wigig_get_rx_smmu_info(&pipe_smmu, + &rx_dbuff_smmu); + if (ret) + return ret; + + ret = ipa3_disconn_wigig_pipe_i(client, + pipe_smmu, + rx_dbuff_smmu); + } else { + ret = ipa_wigig_get_tx_smmu_info(&pipe_smmu, + &tx_dbuff_smmu, client); + if (ret) + return ret; + + ret = ipa3_disconn_wigig_pipe_i(client, + pipe_smmu, + tx_dbuff_smmu); + } + + } else { + ret = ipa3_disconn_wigig_pipe_i(client, NULL, NULL); + } + + if (ret) { + IPA_WIGIG_ERR("couldn't disconnect client %d\n", client); + return ret; + } + + /* RX will be disconnected last, deinit uC msi config */ + if (client == IPA_CLIENT_WIGIG_PROD) { + IPA_WIGIG_DBG("Rx pipe disconnected, deIniting uc\n"); + ret = ipa3_wigig_uc_msi_init(false, + ipa_wigig_ctx->periph_baddr_pa, + ipa_wigig_ctx->pseudo_cause_pa, + ipa_wigig_ctx->int_gen_tx_pa, + ipa_wigig_ctx->int_gen_rx_pa, + ipa_wigig_ctx->dma_ep_misc_pa); + if (ret) { + IPA_WIGIG_ERR("failed unmapping msi regs\n"); + WARN_ON(1); + } + + ret = ipa_pm_deregister(ipa_wigig_ctx->ipa_pm_hdl); + if (ret) { + IPA_WIGIG_ERR("failed dereg pm\n"); + WARN_ON(1); + } + + ipa_wigig_ctx->conn_pipes &= + ~ipa_wigig_pipe_to_bit_val(IPA_CLIENT_WIGIG_PROD); + WARN_ON(ipa_wigig_ctx->conn_pipes); + } else { + /* + * wigig clients are disconnected with legacy message since + * there is no need to send ep, client MAC is sufficient for + * disconnect. + */ + ipa_wigig_send_wlan_msg(WLAN_CLIENT_DISCONNECT, dev_name, + client_mac); + ipa_wigig_clean_client_mac(client); + + ipa_wigig_ctx->conn_pipes &= + ~ipa_wigig_pipe_to_bit_val(client); + } + if (ipa_wigig_is_smmu_enabled()) + ipa_wigig_clean_smmu_info(client); + + IPA_WIGIG_DBG("exit\n"); + return 0; +} +EXPORT_SYMBOL(ipa_wigig_disconn_pipe); + +int ipa_wigig_enable_pipe(enum ipa_client_type client) +{ + int ret; + + IPA_WIGIG_DBG("\n"); + + ret = ipa_wigig_validate_client_type(client); + if (ret) + return ret; + + IPA_WIGIG_DBG("enabling pipe %d\n", client); + + ret = ipa3_enable_wigig_pipe_i(client); + if (ret) + return ret; + + /* do only when Rx pipe is enabled */ + if (client == IPA_CLIENT_WIGIG_PROD) { + ret = ipa_pm_activate_sync(ipa_wigig_ctx->ipa_pm_hdl); + if (ret) { + IPA_WIGIG_ERR("fail to activate ipa pm\n"); + ret = -EFAULT; + goto fail_pm_active; + } + } + + IPA_WIGIG_DBG("exit\n"); + return 0; + +fail_pm_active: + ipa3_disable_wigig_pipe_i(client); + return ret; +} +EXPORT_SYMBOL(ipa_wigig_enable_pipe); + +int ipa_wigig_disable_pipe(enum ipa_client_type client) +{ + int ret; + + IPA_WIGIG_DBG("\n"); + + ret = ipa_wigig_validate_client_type(client); + if (ret) + return ret; + + ret = ipa3_disable_wigig_pipe_i(client); + if (ret) + return ret; + + /* do only when Rx pipe is disabled */ + if (client == IPA_CLIENT_WIGIG_PROD) { + ret = ipa_pm_deactivate_sync(ipa_wigig_ctx->ipa_pm_hdl); + if (ret) { + IPA_WIGIG_ERR("fail to deactivate ipa pm\n"); + return -EFAULT; + } + } + + IPA_WIGIG_DBG("exit\n"); + return 0; +} +EXPORT_SYMBOL(ipa_wigig_disable_pipe); + +int ipa_wigig_tx_dp(enum ipa_client_type dst, struct sk_buff *skb) +{ + int ret; + + IPA_WIGIG_DBG_LOW("\n"); + + ret = ipa_wigig_validate_client_type(dst); + if (unlikely(ret)) + return ret; + + ret = ipa_tx_dp(dst, skb, NULL); + if (unlikely(ret)) + return ret; + + IPA_WIGIG_DBG_LOW("exit\n"); + return 0; +} +EXPORT_SYMBOL(ipa_wigig_tx_dp); + + +#ifdef CONFIG_DEBUG_FS +#define IPA_MAX_MSG_LEN 4096 + +static ssize_t ipa_wigig_read_conn_clients(struct file *file, + char __user *ubuf, size_t count, loff_t *ppos) +{ + int i; + int nbytes = 0; + u8 pipe_connected; + char *dbg_buff; + ssize_t ret; + + dbg_buff = kzalloc(IPA_MAX_MSG_LEN, GFP_KERNEL); + if (!dbg_buff) + return -ENOMEM; + + if (!ipa_wigig_ctx) { + nbytes += scnprintf(dbg_buff + nbytes, + IPA_MAX_MSG_LEN - nbytes, + "IPA WIGIG not initialized\n"); + goto finish; + } + + if (!ipa_wigig_ctx->conn_pipes) { + nbytes += scnprintf(dbg_buff + nbytes, + IPA_MAX_MSG_LEN - nbytes, + "no WIGIG pipes connected\n"); + goto finish; + } + + for (i = 0; i < IPA_WIGIG_MAX_PIPES; i++) { + pipe_connected = (ipa_wigig_ctx->conn_pipes & (0x1 << i)); + switch (i) { + case 0: + nbytes += scnprintf(dbg_buff + nbytes, + IPA_MAX_MSG_LEN - nbytes, + "IPA_CLIENT_WIGIG_PROD"); + break; + case 1: + case 2: + case 3: + case 4: + nbytes += scnprintf(dbg_buff + nbytes, + IPA_MAX_MSG_LEN - nbytes, + "IPA_CLIENT_WIGIG%d_CONS", + i); + break; + default: + IPA_WIGIG_ERR("invalid pipe %d\n", i); + nbytes += scnprintf(dbg_buff + nbytes, + IPA_MAX_MSG_LEN - nbytes, + "invalid pipe %d", + i); + break; + } + nbytes += scnprintf(dbg_buff + nbytes, + IPA_MAX_MSG_LEN - nbytes, + " %s connected\n", pipe_connected ? "is" : "not"); + } + +finish: + ret = simple_read_from_buffer( + ubuf, count, ppos, dbg_buff, nbytes); + kfree(dbg_buff); + return ret; +} + +static ssize_t ipa_wigig_read_smmu_status(struct file *file, + char __user *ubuf, size_t count, loff_t *ppos) +{ + int nbytes = 0; + char *dbg_buff; + ssize_t ret; + + dbg_buff = kzalloc(IPA_MAX_MSG_LEN, GFP_KERNEL); + if (!dbg_buff) + return -ENOMEM; + + if (!ipa_wigig_ctx) { + nbytes += scnprintf(dbg_buff + nbytes, + IPA_MAX_MSG_LEN - nbytes, + "IPA WIGIG not initialized\n"); + goto finish; + } + + if (ipa_wigig_ctx->smmu_en) { + nbytes += scnprintf(dbg_buff + nbytes, + IPA_MAX_MSG_LEN - nbytes, + "SMMU enabled\n"); + + if (ipa_wigig_ctx->shared_cb) { + nbytes += scnprintf(dbg_buff + nbytes, + IPA_MAX_MSG_LEN - nbytes, + "CB shared\n"); + } else { + nbytes += scnprintf(dbg_buff + nbytes, + IPA_MAX_MSG_LEN - nbytes, + "CB not shared\n"); + } + } else { + nbytes += scnprintf(dbg_buff + nbytes, + IPA_MAX_MSG_LEN - nbytes, + "SMMU in S1 bypass\n"); + } +finish: + ret = simple_read_from_buffer( + ubuf, count, ppos, dbg_buff, nbytes); + kfree(dbg_buff); + return ret; +} +static const struct file_operations ipa_wigig_conn_clients_ops = { + .read = ipa_wigig_read_conn_clients, +}; + +static const struct file_operations ipa_wigig_smmu_ops = { + .read = ipa_wigig_read_smmu_status, +}; + +static inline void ipa_wigig_deinit_debugfs(void) +{ + debugfs_remove(ipa_wigig_ctx->dent_conn_clients); + debugfs_remove(ipa_wigig_ctx->dent_smmu); +} + +static int ipa_wigig_init_debugfs(struct dentry *parent) +{ + const mode_t read_only_mode = 0444; + + ipa_wigig_ctx->dent_conn_clients = + debugfs_create_file("conn_clients", read_only_mode, parent, + NULL, &ipa_wigig_conn_clients_ops); + if (IS_ERR_OR_NULL(ipa_wigig_ctx->dent_conn_clients)) { + IPA_WIGIG_ERR("fail to create file %s\n", "conn_clients"); + goto fail_conn_clients; + } + + ipa_wigig_ctx->dent_smmu = + debugfs_create_file("smmu", read_only_mode, parent, NULL, + &ipa_wigig_smmu_ops); + if (IS_ERR_OR_NULL(ipa_wigig_ctx->dent_smmu)) { + IPA_WIGIG_ERR("fail to create file %s\n", "smmu"); + goto fail_smmu; + } + + return 0; +fail_smmu: + debugfs_remove(ipa_wigig_ctx->dent_conn_clients); +fail_conn_clients: + return -EFAULT; +} +#endif + diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_clients/rndis_ipa.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_clients/rndis_ipa.c new file mode 100644 index 0000000000..d471026687 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_clients/rndis_ipa.c @@ -0,0 +1,2596 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2013-2021, The Linux Foundation. All rights reserved. + * + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ipa.h" +#include +#include +#include +#include "rndis_ipa.h" +#include "ipa_common_i.h" +#include "ipa_pm.h" + +#define CREATE_TRACE_POINTS +#include "rndis_ipa_trace.h" + +#define DRV_NAME "RNDIS_IPA" +#define DEBUGFS_DIR_NAME "rndis_ipa" +#define DEBUGFS_AGGR_DIR_NAME "rndis_ipa_aggregation" +#define NETDEV_NAME "rndis" +#define IPV4_HDR_NAME "rndis_eth_ipv4" +#define IPV6_HDR_NAME "rndis_eth_ipv6" +#define RNDIS_HDR_NAME "rndis" +#define ULSO_MAX_SIZE 64000 +#define IPA_TO_USB_CLIENT IPA_CLIENT_USB_CONS +#define INACTIVITY_MSEC_DELAY 100 +#define DEFAULT_OUTSTANDING_HIGH 64 +#define DEFAULT_OUTSTANDING_LOW 32 +#define DEBUGFS_TEMP_BUF_SIZE 4 +#define RNDIS_IPA_PKT_TYPE 0x00000001 +#define RNDIS_IPA_DFLT_RT_HDL 0 +#define FROM_IPA_TO_USB_BAMDMA 4 +#define FROM_USB_TO_IPA_BAMDMA 5 +#define BAM_DMA_MAX_PKT_NUMBER 10 +#define BAM_DMA_DATA_FIFO_SIZE \ + (BAM_DMA_MAX_PKT_NUMBER * \ + (ETH_FRAME_LEN + sizeof(struct rndis_pkt_hdr))) +#define BAM_DMA_DESC_FIFO_SIZE \ + (BAM_DMA_MAX_PKT_NUMBER * (sizeof(struct sps_iovec))) +#define TX_TIMEOUT (5 * HZ) +#define MIN_TX_ERROR_SLEEP_PERIOD 500 +#define DEFAULT_AGGR_TIME_LIMIT 1000 /* 1ms */ +#define DEFAULT_AGGR_PKT_LIMIT 0 + +#define IPA_RNDIS_IPC_LOG_PAGES 50 + +#define IPA_RNDIS_IPC_LOGGING(buf, fmt, args...) \ + do { \ + if (buf) \ + ipc_log_string((buf), fmt, __func__, __LINE__, \ + ## args); \ + } while (0) + +static void *ipa_rndis_logbuf; + +#define RNDIS_IPA_DEBUG(fmt, args...) \ + do { \ + pr_debug(DRV_NAME " %s:%d " fmt, __func__, __LINE__, ## args);\ + if (ipa_rndis_logbuf) { \ + IPA_RNDIS_IPC_LOGGING(ipa_rndis_logbuf, \ + DRV_NAME " %s:%d " fmt, ## args); \ + } \ + } while (0) + +#define RNDIS_IPA_DEBUG_XMIT(fmt, args...) \ + pr_debug(DRV_NAME " %s:%d " fmt, __func__, __LINE__, ## args) + +#define RNDIS_IPA_ERROR(fmt, args...) \ + do { \ + pr_err(DRV_NAME "@%s@%d@ctx:%s: "\ + fmt, __func__, __LINE__, current->comm, ## args);\ + if (ipa_rndis_logbuf) { \ + IPA_RNDIS_IPC_LOGGING(ipa_rndis_logbuf, \ + DRV_NAME " %s:%d " fmt, ## args); \ + } \ + } while (0) + +#define RNDIS_IPA_ERROR_RL(fmt, args...) \ + do { \ + pr_err_ratelimited_ipa(DRV_NAME "@%s@%d@ctx:%s: "\ + fmt, __func__, __LINE__, current->comm, ## args);\ + if (ipa_rndis_logbuf) { \ + IPA_RNDIS_IPC_LOGGING(ipa_rndis_logbuf, \ + DRV_NAME " %s:%d " fmt, ## args); \ + } \ + } while (0) + +#define NULL_CHECK_RETVAL(ptr) \ + do { \ + if (!(ptr)) { \ + RNDIS_IPA_ERROR("null pointer #ptr\n"); \ + ret = -EINVAL; \ + } \ + } \ + while (0) + +#define RNDIS_HDR_OFST(field) offsetof(struct rndis_pkt_hdr, field) +#define RNDIS_IPA_LOG_ENTRY() RNDIS_IPA_DEBUG("begin\n") +#define RNDIS_IPA_LOG_EXIT() RNDIS_IPA_DEBUG("end\n") + +#define IPV4_IS_TCP(iph) ((iph)->protocol == IPPROTO_TCP) +#define IPV4_IS_UDP(iph) ((iph)->protocol == IPPROTO_UDP) +#define IPV6_IS_TCP(iph) (((struct ipv6hdr *)iph)->nexthdr == IPPROTO_TCP) +#define IPV6_IS_UDP(iph) (((struct ipv6hdr *)iph)->nexthdr == IPPROTO_UDP) +#define IPV4_DELTA 40 +#define IPV6_DELTA 60 + +/** + * enum rndis_ipa_state - specify the current driver internal state + * which is guarded by a state machine. + * + * The driver internal state changes due to its external API usage. + * The driver saves its internal state to guard from caller illegal + * call sequence. + * states: + * UNLOADED is the first state which is the default one and is also the state + * after the driver gets unloaded(cleanup). + * INITIALIZED is the driver state once it finished registering + * the network device and all internal data struct were initialized + * CONNECTED is the driver state once the USB pipes were connected to IPA + * UP is the driver state after the interface mode was set to UP but the + * pipes are not connected yet - this state is meta-stable state. + * CONNECTED_AND_UP is the driver state when the pipe were connected and + * the interface got UP request from the network stack. this is the driver + * idle operation state which allows it to transmit/receive data. + * INVALID is a state which is not allowed. + */ +enum rndis_ipa_state { + RNDIS_IPA_UNLOADED = 0, + RNDIS_IPA_INITIALIZED = 1, + RNDIS_IPA_CONNECTED = 2, + RNDIS_IPA_UP = 3, + RNDIS_IPA_CONNECTED_AND_UP = 4, + RNDIS_IPA_INVALID = 5, +}; + +/** + * enum rndis_ipa_operation - enumerations used to describe the API operation + * + * Those enums are used as input for the driver state machine. + */ +enum rndis_ipa_operation { + RNDIS_IPA_INITIALIZE, + RNDIS_IPA_CONNECT, + RNDIS_IPA_OPEN, + RNDIS_IPA_STOP, + RNDIS_IPA_DISCONNECT, + RNDIS_IPA_CLEANUP, +}; + +#define RNDIS_IPA_STATE_DEBUG(ctx) \ + RNDIS_IPA_DEBUG("Driver state: %s\n",\ + rndis_ipa_state_string((ctx)->state)) + + +/** + * struct rndis_ipa_dev - main driver context parameters + * + * @net: network interface struct implemented by this driver + * @directory: debugfs directory for various debugging switches + * @tx_filter: flag that enable/disable Tx path to continue to IPA + * @tx_dropped: number of filtered out Tx packets + * @tx_dump_enable: dump all Tx packets + * @rx_filter: flag that enable/disable Rx path to continue to IPA + * @rx_dropped: number of filtered out Rx packets + * @rx_dump_enable: dump all Rx packets + * @icmp_filter: allow all ICMP packet to pass through the filters + * @deaggregation_enable: enable/disable IPA HW deaggregation logic + * @during_xmit_error: flags that indicate that the driver is in a middle + * of error handling in Tx path + * @directory: holds all debug flags used by the driver to allow cleanup + * for driver unload + * @eth_ipv4_hdr_hdl: saved handle for ipv4 header-insertion table + * @eth_ipv6_hdr_hdl: saved handle for ipv6 header-insertion table + * @usb_to_ipa_hdl: save handle for IPA pipe operations + * @ipa_to_usb_hdl: save handle for IPA pipe operations + * @outstanding_pkts: number of packets sent to IPA without TX complete ACKed + * @outstanding_high: number of outstanding packets allowed + * @outstanding_low: number of outstanding packets which shall cause + * to netdev queue start (after stopped due to outstanding_high reached) + * @error_msec_sleep_time: number of msec for sleeping in case of Tx error + * @state: current state of the driver + * @host_ethaddr: holds the tethered PC ethernet address + * @device_ethaddr: holds the device ethernet address + * @device_ready_notify: callback supplied by USB core driver + * This callback shall be called by the Netdev once the Netdev internal + * state is changed to RNDIS_IPA_CONNECTED_AND_UP + * @xmit_error_delayed_work: work item for cases where IPA driver Tx fails + * @state_lock: used to protect the state variable. + * @pm_hdl: handle for IPA PM framework + * @is_vlan_mode: should driver work in vlan mode? + * @netif_rx_function: holds the correct network stack API, needed for NAPI + * @is_ulso_mode: indicator for ulso support + * @rndis_hdr_hdl: hdr handle of rndis header + */ +struct rndis_ipa_dev { + struct net_device *net; + bool tx_filter; + u32 tx_dropped; + bool tx_dump_enable; + bool rx_filter; + u32 rx_dropped; + bool rx_dump_enable; + bool icmp_filter; + bool deaggregation_enable; + bool during_xmit_error; + struct dentry *directory; + u32 eth_ipv4_hdr_hdl; + u32 eth_ipv6_hdr_hdl; + u32 usb_to_ipa_hdl; + u32 ipa_to_usb_hdl; + atomic_t outstanding_pkts; + u32 outstanding_high; + u32 outstanding_low; + u32 error_msec_sleep_time; + enum rndis_ipa_state state; + u8 host_ethaddr[ETH_ALEN]; + u8 device_ethaddr[ETH_ALEN]; + void (*device_ready_notify)(void); + struct delayed_work xmit_error_delayed_work; + spinlock_t state_lock; /* Spinlock for the state variable.*/ + u32 pm_hdl; + bool is_vlan_mode; + int (*netif_rx_function)(struct sk_buff *skb); + bool is_ulso_mode; + u32 rndis_hdr_hdl; +}; + +/** + * rndis_pkt_hdr - RNDIS_IPA representation of REMOTE_NDIS_PACKET_MSG + * @msg_type: for REMOTE_NDIS_PACKET_MSG this value should be 1 + * @msg_len: total message length in bytes, including RNDIS header an payload + * @data_ofst: offset in bytes from start of the data_ofst to payload + * @data_len: payload size in bytes + * @zeroes: OOB place holder - not used for RNDIS_IPA. + */ +struct rndis_pkt_hdr { + __le32 msg_type; + __le32 msg_len; + __le32 data_ofst; + __le32 data_len; + __le32 zeroes[7]; +} __packed__; + +static int rndis_ipa_open(struct net_device *net); +static void rndis_ipa_packet_receive_notify + (void *private, enum ipa_dp_evt_type evt, unsigned long data); +static void rndis_ipa_tx_complete_notify + (void *private, enum ipa_dp_evt_type evt, unsigned long data); + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 6, 0)) +static void rndis_ipa_tx_timeout(struct net_device *net, + unsigned int txqueue); +#else /* Legacy API. */ +static void rndis_ipa_tx_timeout(struct net_device *net); +#endif + +static int rndis_ipa_stop(struct net_device *net); +static void rndis_ipa_enable_data_path(struct rndis_ipa_dev *rndis_ipa_ctx); +static struct sk_buff *rndis_encapsulate_skb(struct sk_buff *skb, + struct rndis_ipa_dev *rndis_ipa_ctx); +static void rndis_ipa_xmit_error(struct sk_buff *skb); +static void rndis_ipa_xmit_error_aftercare_wq(struct work_struct *work); +static void rndis_ipa_prepare_header_insertion + (int eth_type, + const char *hdr_name, struct ipa_hdr_add *add_hdr, + const void *dst_mac, const void *src_mac, bool is_vlan_mode); +static int rndis_ipa_hdrs_cfg(struct rndis_ipa_dev *rndis_ipa_ctx, + const void *dst_mac, const void *src_mac); +static int rndis_ipa_hdrs_hpc_cfg(struct rndis_ipa_dev *rndis_ipa_ctx); +static int rndis_ipa_hdrs_destroy(struct rndis_ipa_dev *rndis_ipa_ctx); +static struct net_device_stats *rndis_ipa_get_stats(struct net_device *net); +static int rndis_ipa_register_properties(char *netdev_name, bool is_vlan_mode); +static int rndis_ipa_deregister_properties(char *netdev_name); +static int rndis_ipa_register_pm_client(struct rndis_ipa_dev *rndis_ipa_ctx); +static int rndis_ipa_deregister_pm_client(struct rndis_ipa_dev *rndis_ipa_ctx); +static bool rx_filter(struct sk_buff *skb); +static bool tx_filter(struct sk_buff *skb); +static netdev_tx_t rndis_ipa_start_xmit + (struct sk_buff *skb, struct net_device *net); +static int rndis_ipa_debugfs_atomic_open + (struct inode *inode, struct file *file); +static int rndis_ipa_debugfs_aggr_open + (struct inode *inode, struct file *file); +static ssize_t rndis_ipa_debugfs_aggr_write + (struct file *file, + const char __user *buf, size_t count, loff_t *ppos); +static ssize_t rndis_ipa_debugfs_atomic_read + (struct file *file, + char __user *ubuf, size_t count, loff_t *ppos); +static void rndis_ipa_dump_skb(struct sk_buff *skb); +static void rndis_ipa_debugfs_init(struct rndis_ipa_dev *rndis_ipa_ctx); +static void rndis_ipa_debugfs_destroy(struct rndis_ipa_dev *rndis_ipa_ctx); +static int rndis_ipa_ep_registers_cfg + (u32 usb_to_ipa_hdl, + u32 ipa_to_usb_hdl, u32 max_xfer_size_bytes_to_dev, + u32 max_xfer_size_bytes_to_host, u32 mtu, + bool deaggr_enable, + bool is_vlan_mode); +static int rndis_ipa_set_device_ethernet_addr + (struct net_device *net, + u8 device_ethaddr[]); +static enum rndis_ipa_state rndis_ipa_next_state + (enum rndis_ipa_state current_state, + enum rndis_ipa_operation operation); +static const char *rndis_ipa_state_string(enum rndis_ipa_state state); + +static struct rndis_ipa_dev *rndis_ipa; + +static const struct net_device_ops rndis_ipa_netdev_ops = { + .ndo_open = rndis_ipa_open, + .ndo_stop = rndis_ipa_stop, + .ndo_start_xmit = rndis_ipa_start_xmit, + .ndo_tx_timeout = rndis_ipa_tx_timeout, + .ndo_get_stats = rndis_ipa_get_stats, + .ndo_set_mac_address = eth_mac_addr, +}; + +static const struct file_operations rndis_ipa_debugfs_atomic_ops = { + .open = rndis_ipa_debugfs_atomic_open, + .read = rndis_ipa_debugfs_atomic_read, +}; + +static const struct file_operations rndis_ipa_aggr_ops = { + .open = rndis_ipa_debugfs_aggr_open, + .write = rndis_ipa_debugfs_aggr_write, +}; + +static struct ipa_ep_cfg ipa_to_usb_ep_cfg = { + .mode = { + .mode = IPA_BASIC, + .dst = IPA_CLIENT_APPS_LAN_CONS, + }, + .hdr = { + .hdr_len = ETH_HLEN + sizeof(struct rndis_pkt_hdr), + .hdr_ofst_metadata_valid = false, + .hdr_ofst_metadata = 0, + .hdr_additional_const_len = ETH_HLEN, + .hdr_ofst_pkt_size_valid = true, + .hdr_ofst_pkt_size = offsetof(struct rndis_pkt_hdr, data_len), + .hdr_a5_mux = false, + .hdr_remove_additional = false, + .hdr_metadata_reg_valid = false, + }, + .hdr_ext = { + .hdr_pad_to_alignment = 0, + .hdr_total_len_or_pad_offset = offsetof(struct rndis_pkt_hdr, msg_len), + .hdr_payload_len_inc_padding = false, + .hdr_total_len_or_pad = IPA_HDR_TOTAL_LEN, + .hdr_total_len_or_pad_valid = true, + .hdr_little_endian = true, + }, + .aggr = { + .aggr_en = IPA_ENABLE_AGGR, + .aggr = IPA_GENERIC, + .aggr_byte_limit = 4, + .aggr_time_limit = DEFAULT_AGGR_TIME_LIMIT, + .aggr_pkt_limit = DEFAULT_AGGR_PKT_LIMIT, + }, + .deaggr = { + .deaggr_hdr_len = 0, + .packet_offset_valid = 0, + .packet_offset_location = 0, + .max_packet_len = 0, + }, + .route = { + .rt_tbl_hdl = RNDIS_IPA_DFLT_RT_HDL, + }, + .nat = { + .nat_en = IPA_SRC_NAT, + }, +}; + +static struct ipa_ep_cfg usb_to_ipa_ep_cfg_deaggr_dis = { + .mode = { + .mode = IPA_BASIC, + .dst = IPA_CLIENT_APPS_LAN_CONS, + }, + .hdr = { + .hdr_len = ETH_HLEN + sizeof(struct rndis_pkt_hdr), + .hdr_ofst_metadata_valid = false, + .hdr_ofst_metadata = 0, + .hdr_additional_const_len = 0, + .hdr_ofst_pkt_size_valid = true, + .hdr_ofst_pkt_size = 3 * sizeof(u32) + + sizeof(struct rndis_pkt_hdr), + .hdr_a5_mux = false, + .hdr_remove_additional = false, + .hdr_metadata_reg_valid = true, + }, + .hdr_ext = { + .hdr_pad_to_alignment = 0, + .hdr_total_len_or_pad_offset = 1 * sizeof(u32), + .hdr_payload_len_inc_padding = false, + .hdr_total_len_or_pad = IPA_HDR_TOTAL_LEN, + .hdr_total_len_or_pad_valid = true, + .hdr_little_endian = true, + }, + + .aggr = { + .aggr_en = IPA_BYPASS_AGGR, + .aggr = 0, + .aggr_byte_limit = 0, + .aggr_time_limit = 0, + .aggr_pkt_limit = 0, + }, + .deaggr = { + .deaggr_hdr_len = 0, + .packet_offset_valid = false, + .packet_offset_location = 0, + .max_packet_len = 0, + }, + + .route = { + .rt_tbl_hdl = RNDIS_IPA_DFLT_RT_HDL, + }, + .nat = { + .nat_en = IPA_BYPASS_NAT, + }, +}; + +static struct ipa_ep_cfg usb_to_ipa_ep_cfg_deaggr_en = { + .mode = { + .mode = IPA_BASIC, + .dst = IPA_CLIENT_APPS_LAN_CONS, + }, + .hdr = { + .hdr_len = ETH_HLEN, + .hdr_ofst_metadata_valid = false, + .hdr_ofst_metadata = 0, + .hdr_additional_const_len = 0, + .hdr_ofst_pkt_size_valid = true, + .hdr_ofst_pkt_size = 3 * sizeof(u32), + .hdr_a5_mux = false, + .hdr_remove_additional = false, + .hdr_metadata_reg_valid = true, + }, + .hdr_ext = { + .hdr_pad_to_alignment = 0, + .hdr_total_len_or_pad_offset = 1 * sizeof(u32), + .hdr_payload_len_inc_padding = false, + .hdr_total_len_or_pad = IPA_HDR_TOTAL_LEN, + .hdr_total_len_or_pad_valid = true, + .hdr_little_endian = true, + }, + .aggr = { + .aggr_en = IPA_ENABLE_DEAGGR, + .aggr = IPA_GENERIC, + .aggr_byte_limit = 0, + .aggr_time_limit = 0, + .aggr_pkt_limit = 0, + }, + .deaggr = { + .deaggr_hdr_len = sizeof(struct rndis_pkt_hdr), + .syspipe_err_detection = true, + .packet_offset_valid = true, + .packet_offset_location = 8, + .ignore_min_pkt_err = true, + .max_packet_len = 8192, /* Will be overridden*/ + }, + .route = { + .rt_tbl_hdl = RNDIS_IPA_DFLT_RT_HDL, + }, + .nat = { + .nat_en = IPA_BYPASS_NAT, + }, +}; + +/** + * rndis_template_hdr - RNDIS template structure for RNDIS_IPA SW insertion + * @msg_type: set for REMOTE_NDIS_PACKET_MSG (0x00000001) + * this value will be used for all data packets + * @msg_len: will add the skb length to get final size + * @data_ofst: this field value will not be changed + * @data_len: set as skb length to get final size + * @zeroes: make sure all OOB data is not used + */ +static struct rndis_pkt_hdr rndis_template_hdr = { + .msg_type = RNDIS_IPA_PKT_TYPE, + .msg_len = sizeof(struct rndis_pkt_hdr), + .data_ofst = sizeof(struct rndis_pkt_hdr) - RNDIS_HDR_OFST(data_ofst), + .data_len = 0, + .zeroes = {0}, +}; + +/** + * qmap_template_hdr - QMAP template structure for RNDIS_IPA SW insertion + * @pad: Set to 0 + * @next_hdr: extension header exists - 1 + * @cd: Data packet - 0 + * @mux_id: Always 0 + * @packet_len_with_pad: Set dynamically + * @ext_next_hdr: Always 0 + * @hdr_type: Set to ULSO - 0x3 + * @additional_hdr_size: - Set to VLAN tag size + * @zero_checksum: Always compute checksum - 0 + * @ip_id_cfg: Always run up ip id per segment - 0 + * @segment_size: Set dynamically + */ +static struct qmap_hdr qmap_template_hdr = { + .pad = 0, + .next_hdr = 1, + .cd = 0, + .mux_id = 0, + .packet_len_with_pad = 0, + .ext_next_hdr = 0, + .hdr_type = 0x3, + .additional_hdr_size = 0, + .reserved = 0, + .zero_checksum = 0, + .ip_id_cfg = 0, + .segment_size = 0, +}; + +static void rndis_ipa_msg_free_cb(void *buff, u32 len, u32 type) +{ + kfree(buff); +} + +/** + * rndis_ipa_init() - create network device and initialize internal + * data structures + * @params: in/out parameters required for initialization, + * see "struct ipa_usb_init_params" for more details + * + * Shall be called prior to pipe connection. + * Detailed description: + * - allocate the network device + * - set default values for driver internal switches and stash them inside + * the netdev private field + * - set needed headroom for RNDIS header + * - create debugfs folder and files + * - create IPA resource manager client + * - set the ethernet address for the netdev to be added on SW Tx path + * - add header insertion rules for IPA driver (based on host/device Ethernet + * addresses given in input params and on RNDIS data template struct) + * - register tx/rx properties to IPA driver (will be later used + * by IPA configuration manager to configure rest of the IPA rules) + * - set the carrier state to "off" (until connect is called) + * - register the network device + * - set the out parameters + * - change driver internal state to INITIALIZED + * + * Returns negative errno, or zero on success + */ +int rndis_ipa_init(struct ipa_usb_init_params *params) +{ + int result = 0; + struct net_device *net; + struct rndis_ipa_dev *rndis_ipa_ctx; + int ret; + + RNDIS_IPA_LOG_ENTRY(); + RNDIS_IPA_DEBUG("%s initializing\n", DRV_NAME); + ret = 0; + NULL_CHECK_RETVAL(params); + if (ret) + return ret; + + RNDIS_IPA_DEBUG + ("host_ethaddr=%pM, device_ethaddr=%pM\n", + params->host_ethaddr, + params->device_ethaddr); + + net = alloc_etherdev(sizeof(struct rndis_ipa_dev)); + if (!net) { + result = -ENOMEM; + RNDIS_IPA_ERROR("fail to allocate Ethernet device\n"); + goto fail_alloc_etherdev; + } + RNDIS_IPA_DEBUG("network device was successfully allocated\n"); + + rndis_ipa_ctx = netdev_priv(net); + if (!rndis_ipa_ctx) { + result = -ENOMEM; + RNDIS_IPA_ERROR("fail to extract netdev priv\n"); + goto fail_netdev_priv; + } + memset(rndis_ipa_ctx, 0, sizeof(*rndis_ipa_ctx)); + RNDIS_IPA_DEBUG("rndis_ipa_ctx (private)=%pK\n", rndis_ipa_ctx); + + spin_lock_init(&rndis_ipa_ctx->state_lock); + + rndis_ipa_ctx->net = net; + rndis_ipa_ctx->tx_filter = false; + rndis_ipa_ctx->rx_filter = false; + rndis_ipa_ctx->icmp_filter = true; + rndis_ipa_ctx->tx_dropped = 0; + rndis_ipa_ctx->rx_dropped = 0; + rndis_ipa_ctx->tx_dump_enable = false; + rndis_ipa_ctx->rx_dump_enable = false; + rndis_ipa_ctx->deaggregation_enable = false; + rndis_ipa_ctx->outstanding_high = DEFAULT_OUTSTANDING_HIGH; + rndis_ipa_ctx->outstanding_low = DEFAULT_OUTSTANDING_LOW; + atomic_set(&rndis_ipa_ctx->outstanding_pkts, 0); + memcpy + (rndis_ipa_ctx->device_ethaddr, params->device_ethaddr, + sizeof(rndis_ipa_ctx->device_ethaddr)); + memcpy + (rndis_ipa_ctx->host_ethaddr, params->host_ethaddr, + sizeof(rndis_ipa_ctx->host_ethaddr)); + INIT_DELAYED_WORK + (&rndis_ipa_ctx->xmit_error_delayed_work, + rndis_ipa_xmit_error_aftercare_wq); + rndis_ipa_ctx->error_msec_sleep_time = + MIN_TX_ERROR_SLEEP_PERIOD; + RNDIS_IPA_DEBUG("internal data structures were set\n"); + + if (!params->device_ready_notify) + RNDIS_IPA_DEBUG("device_ready_notify() was not supplied\n"); + rndis_ipa_ctx->device_ready_notify = params->device_ready_notify; + + snprintf(net->name, sizeof(net->name), "%s%%d", NETDEV_NAME); + RNDIS_IPA_DEBUG + ("Setting network interface driver name to: %s\n", + net->name); + + net->netdev_ops = &rndis_ipa_netdev_ops; + net->watchdog_timeo = TX_TIMEOUT; + + net->needed_headroom = sizeof(rndis_template_hdr); + RNDIS_IPA_DEBUG + ("Needed headroom for RNDIS header set to %d\n", + net->needed_headroom); + + rndis_ipa_debugfs_init(rndis_ipa_ctx); + + result = rndis_ipa_set_device_ethernet_addr + (net, rndis_ipa_ctx->device_ethaddr); + if (result) { + RNDIS_IPA_ERROR("set device MAC failed\n"); + goto fail_set_device_ethernet; + } + RNDIS_IPA_DEBUG("Device Ethernet address set %pM\n", net->dev_addr); + + if (ipa_is_vlan_mode(IPA_VLAN_IF_RNDIS, + &rndis_ipa_ctx->is_vlan_mode)) { + RNDIS_IPA_ERROR_RL("couldn't acquire vlan mode, is ipa ready?\n"); + goto fail_get_vlan_mode; + } + RNDIS_IPA_DEBUG("is_vlan_mode %d\n", rndis_ipa_ctx->is_vlan_mode); + + rndis_ipa_ctx->is_ulso_mode = ipa3_is_ulso_supported(); + RNDIS_IPA_DEBUG("is_ulso_mode=%d\n", rndis_ipa_ctx->is_ulso_mode); + + result = rndis_ipa_hdrs_cfg(rndis_ipa_ctx, params->host_ethaddr, + params->device_ethaddr); + if (result) { + RNDIS_IPA_ERROR("fail on ipa hdrs set\n"); + goto fail_hdrs_cfg; + } + RNDIS_IPA_DEBUG("IPA header-insertion configured for Ethernet\n"); + + if (rndis_ipa_ctx->is_ulso_mode) { + result = rndis_ipa_hdrs_hpc_cfg(rndis_ipa_ctx); + if (result) { + RNDIS_IPA_ERROR("fail on ipa hdrs hpc set\n"); + goto fail_add_hdrs_hpc; + } + RNDIS_IPA_DEBUG("IPA header-insertion configured for RNDIS\n"); + + rndis_ipa_ctx->net->hw_features = NETIF_F_RXCSUM; + rndis_ipa_ctx->net->hw_features |= + NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; + rndis_ipa_ctx->net->hw_features |= NETIF_F_SG; + rndis_ipa_ctx->net->hw_features |= NETIF_F_GRO_HW; + rndis_ipa_ctx->net->hw_features |= NETIF_F_GSO_UDP_L4; + rndis_ipa_ctx->net->hw_features |= NETIF_F_ALL_TSO; + rndis_ipa_ctx->net->gso_max_size = ULSO_MAX_SIZE; + } + + result = rndis_ipa_register_properties(net->name, + rndis_ipa_ctx->is_vlan_mode); + if (result) { + RNDIS_IPA_ERROR("fail on properties set\n"); + goto fail_register_tx; + } + RNDIS_IPA_DEBUG("2 TX and 2 RX properties were registered\n"); + + netif_carrier_off(net); + RNDIS_IPA_DEBUG("set carrier off until pipes are connected\n"); + + result = register_netdev(net); + if (result) { + RNDIS_IPA_ERROR("register_netdev failed: %d\n", result); + goto fail_register_netdev; + } + RNDIS_IPA_DEBUG + ("netdev:%s registration succeeded, index=%d\n", + net->name, net->ifindex); + + if (ipa_get_lan_rx_napi()) { + rndis_ipa_ctx->netif_rx_function = netif_receive_skb; + RNDIS_IPA_DEBUG("LAN RX NAPI enabled = True"); + } else { +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 18, 0)) + rndis_ipa_ctx->netif_rx_function = netif_rx_ni; +#else + rndis_ipa_ctx->netif_rx_function = netif_rx; +#endif + RNDIS_IPA_DEBUG("LAN RX NAPI enabled = False"); + } + + if (rndis_ipa_ctx->is_vlan_mode) + qmap_template_hdr.additional_hdr_size = + VLAN_ETH_HLEN - ETH_HLEN; + + rndis_ipa = rndis_ipa_ctx; + params->ipa_rx_notify = rndis_ipa_packet_receive_notify; + params->ipa_tx_notify = rndis_ipa_tx_complete_notify; + params->private = rndis_ipa_ctx; + params->skip_ep_cfg = false; + rndis_ipa_ctx->state = RNDIS_IPA_INITIALIZED; + RNDIS_IPA_STATE_DEBUG(rndis_ipa_ctx); + pr_info("RNDIS_IPA NetDev was initialized\n"); + + RNDIS_IPA_LOG_EXIT(); + + return 0; + +fail_register_netdev: + rndis_ipa_deregister_properties(net->name); +fail_register_tx: + if (rndis_ipa_ctx->is_ulso_mode) + ipa_hdrs_hpc_destroy(rndis_ipa_ctx->rndis_hdr_hdl); +fail_add_hdrs_hpc: + rndis_ipa_hdrs_destroy(rndis_ipa_ctx); +fail_hdrs_cfg: +fail_get_vlan_mode: +fail_set_device_ethernet: + rndis_ipa_debugfs_destroy(rndis_ipa_ctx); +fail_netdev_priv: + free_netdev(net); +fail_alloc_etherdev: + return result; +} +EXPORT_SYMBOL(rndis_ipa_init); + +/** + * rndis_ipa_pipe_connect_notify() - notify rndis_ipa Netdev that the USB pipes + * were connected + * @usb_to_ipa_hdl: handle from IPA driver client for USB->IPA + * @ipa_to_usb_hdl: handle from IPA driver client for IPA->USB + * @private: same value that was set by init(), this parameter holds the + * network device pointer. + * @max_transfer_byte_size: RNDIS protocol specific, the maximum size that + * the host expect + * @max_packet_number: RNDIS protocol specific, the maximum packet number + * that the host expects + * + * Once USB driver finishes the pipe connection between IPA core + * and USB core this method shall be called in order to + * allow the driver to complete the data path configurations. + * Detailed description: + * - configure the IPA end-points register + * - notify the Linux kernel for "carrier_on" + * - change the driver internal state + * + * After this function is done the driver state changes to "Connected" or + * Connected and Up. + * This API is expected to be called after initialization() or + * after a call to disconnect(). + * + * Returns negative errno, or zero on success + */ +int rndis_ipa_pipe_connect_notify( + u32 usb_to_ipa_hdl, + u32 ipa_to_usb_hdl, + u32 max_xfer_size_bytes_to_dev, + u32 max_packet_number_to_dev, + u32 max_xfer_size_bytes_to_host, + void *private) +{ + struct rndis_ipa_dev *rndis_ipa_ctx = private; + int next_state; + int result; + int ret; + unsigned long flags; + struct ipa_ecm_msg *rndis_msg; + struct ipa_msg_meta msg_meta; + + RNDIS_IPA_LOG_ENTRY(); + + ret = 0; + NULL_CHECK_RETVAL(private); + + if (ret) + return ret; + + RNDIS_IPA_DEBUG + ("usb_to_ipa_hdl=%d, ipa_to_usb_hdl=%d, private=0x%pK\n", + usb_to_ipa_hdl, ipa_to_usb_hdl, private); + RNDIS_IPA_DEBUG + ("max_xfer_sz_to_dev=%d, max_pkt_num_to_dev=%d\n", + max_xfer_size_bytes_to_dev, + max_packet_number_to_dev); + RNDIS_IPA_DEBUG + ("max_xfer_sz_to_host=%d\n", + max_xfer_size_bytes_to_host); + + spin_lock_irqsave(&rndis_ipa_ctx->state_lock, flags); + next_state = rndis_ipa_next_state + (rndis_ipa_ctx->state, + RNDIS_IPA_CONNECT); + if (next_state == RNDIS_IPA_INVALID) { + spin_unlock_irqrestore(&rndis_ipa_ctx->state_lock, flags); + RNDIS_IPA_ERROR("use init()/disconnect() before connect()\n"); + return -EPERM; + } + spin_unlock_irqrestore(&rndis_ipa_ctx->state_lock, flags); + + if (usb_to_ipa_hdl >= IPA_CLIENT_MAX) { + RNDIS_IPA_ERROR_RL + ("usb_to_ipa_hdl(%d) - not valid ipa handle\n", + usb_to_ipa_hdl); + return -EINVAL; + } + if (ipa_to_usb_hdl >= IPA_CLIENT_MAX) { + RNDIS_IPA_ERROR_RL + ("ipa_to_usb_hdl(%d) - not valid ipa handle\n", + ipa_to_usb_hdl); + return -EINVAL; + } + + result = rndis_ipa_register_pm_client(rndis_ipa_ctx); + if (result) { + RNDIS_IPA_ERROR("fail on PM register\n"); + goto fail_register_pm; + } + RNDIS_IPA_DEBUG("PM client was registered\n"); + + rndis_ipa_ctx->ipa_to_usb_hdl = ipa_to_usb_hdl; + rndis_ipa_ctx->usb_to_ipa_hdl = usb_to_ipa_hdl; + if (max_packet_number_to_dev > 1) + rndis_ipa_ctx->deaggregation_enable = true; + else + rndis_ipa_ctx->deaggregation_enable = false; + result = rndis_ipa_ep_registers_cfg + (usb_to_ipa_hdl, + ipa_to_usb_hdl, + max_xfer_size_bytes_to_dev, + max_xfer_size_bytes_to_host, + rndis_ipa_ctx->net->mtu, + rndis_ipa_ctx->deaggregation_enable, + rndis_ipa_ctx->is_vlan_mode); + if (result) { + RNDIS_IPA_ERROR("fail on ep cfg\n"); + goto fail; + } + RNDIS_IPA_DEBUG("end-points configured\n"); + + netif_stop_queue(rndis_ipa_ctx->net); + RNDIS_IPA_DEBUG("netif_stop_queue() was called\n"); + + netif_carrier_on(rndis_ipa_ctx->net); + if (!netif_carrier_ok(rndis_ipa_ctx->net)) { + RNDIS_IPA_ERROR_RL("netif_carrier_ok error\n"); + result = -EBUSY; + goto fail; + } + RNDIS_IPA_DEBUG("netif_carrier_on() was called\n"); + + rndis_msg = kzalloc(sizeof(*rndis_msg), GFP_KERNEL); + if (!rndis_msg) { + result = -ENOMEM; + goto fail; + } + + memset(&msg_meta, 0, sizeof(struct ipa_msg_meta)); + msg_meta.msg_type = ECM_CONNECT; + msg_meta.msg_len = sizeof(struct ipa_ecm_msg); + strlcpy(rndis_msg->name, rndis_ipa_ctx->net->name, + IPA_RESOURCE_NAME_MAX); + rndis_msg->ifindex = rndis_ipa_ctx->net->ifindex; + + result = ipa_send_msg(&msg_meta, rndis_msg, rndis_ipa_msg_free_cb); + if (result) { + RNDIS_IPA_ERROR("fail to send ECM_CONNECT for rndis\n"); + kfree(rndis_msg); + goto fail; + } + + spin_lock_irqsave(&rndis_ipa_ctx->state_lock, flags); + next_state = rndis_ipa_next_state(rndis_ipa_ctx->state, + RNDIS_IPA_CONNECT); + if (next_state == RNDIS_IPA_INVALID) { + spin_unlock_irqrestore(&rndis_ipa_ctx->state_lock, flags); + RNDIS_IPA_ERROR_RL("use init()/disconnect() before connect()\n"); + return -EPERM; + } + rndis_ipa_ctx->state = next_state; + spin_unlock_irqrestore(&rndis_ipa_ctx->state_lock, flags); + + RNDIS_IPA_STATE_DEBUG(rndis_ipa_ctx); + + if (next_state == RNDIS_IPA_CONNECTED_AND_UP) + rndis_ipa_enable_data_path(rndis_ipa_ctx); + else + RNDIS_IPA_DEBUG("queue shall be started after open()\n"); + + pr_info("RNDIS_IPA NetDev pipes were connected\n"); + + RNDIS_IPA_LOG_EXIT(); + + return 0; + +fail: + rndis_ipa_deregister_pm_client(rndis_ipa_ctx); +fail_register_pm: + return result; +} +EXPORT_SYMBOL(rndis_ipa_pipe_connect_notify); + +/** + * rndis_ipa_open() - notify Linux network stack to start sending packets + * @net: the network interface supplied by the network stack + * + * Linux uses this API to notify the driver that the network interface + * transitions to the up state. + * The driver will instruct the Linux network stack to start + * delivering data packets. + * The driver internal state shall be changed to Up or Connected and Up + * + * Returns negative errno, or zero on success + */ +static int rndis_ipa_open(struct net_device *net) +{ + struct rndis_ipa_dev *rndis_ipa_ctx; + int next_state; + unsigned long flags; + + RNDIS_IPA_LOG_ENTRY(); + + rndis_ipa_ctx = netdev_priv(net); + + spin_lock_irqsave(&rndis_ipa_ctx->state_lock, flags); + + next_state = rndis_ipa_next_state(rndis_ipa_ctx->state, RNDIS_IPA_OPEN); + if (next_state == RNDIS_IPA_INVALID) { + spin_unlock_irqrestore(&rndis_ipa_ctx->state_lock, flags); + RNDIS_IPA_ERROR_RL("can't bring driver up before initialize\n"); + return -EPERM; + } + + rndis_ipa_ctx->state = next_state; + + spin_unlock_irqrestore(&rndis_ipa_ctx->state_lock, flags); + + RNDIS_IPA_STATE_DEBUG(rndis_ipa_ctx); + + if (next_state == RNDIS_IPA_CONNECTED_AND_UP) + rndis_ipa_enable_data_path(rndis_ipa_ctx); + else + RNDIS_IPA_DEBUG("queue shall be started after connect()\n"); + + pr_info("RNDIS_IPA NetDev was opened\n"); + + RNDIS_IPA_LOG_EXIT(); + + return 0; +} + +/** + * rndis_ipa_start_xmit() - send data from APPs to USB core via IPA core + * using SW path (Tx data path) + * Tx path for this Netdev is Apps-processor->IPA->USB + * @skb: packet received from Linux network stack destined for tethered PC + * @net: the network device being used to send this packet (rndis0) + * + * Several conditions needed in order to send the packet to IPA: + * - Transmit queue for the network driver is currently + * in "started" state + * - The driver internal state is in Connected and Up state. + * - Filters Tx switch are turned off + * - The IPA resource manager state for the driver producer client + * is "Granted" which implies that all the resources in the dependency + * graph are valid for data flow. + * - outstanding high boundary was not reached. + * + * In case the outstanding packets high boundary is reached, the driver will + * stop the send queue until enough packets are processed by + * the IPA core (based on calls to rndis_ipa_tx_complete_notify). + * + * In case all of the conditions are met, the network driver shall: + * - encapsulate the Ethernet packet with RNDIS header (REMOTE_NDIS_PACKET_MSG) + * - send the packet by using IPA Driver SW path (IP_PACKET_INIT) + * - Netdev status fields shall be updated based on the current Tx packet + * + * Returns NETDEV_TX_BUSY if retry should be made later, + * or NETDEV_TX_OK on success. + */ +static netdev_tx_t rndis_ipa_start_xmit(struct sk_buff *skb, + struct net_device *net) +{ + int ret; + netdev_tx_t status = NETDEV_TX_BUSY; + struct rndis_ipa_dev *rndis_ipa_ctx = netdev_priv(net); + unsigned int skb_len = skb->len; + + netif_trans_update(net); + + RNDIS_IPA_DEBUG_XMIT + ("Tx, len=%d, skb->protocol=%d, outstanding=%d\n", + skb->len, skb->protocol, + atomic_read(&rndis_ipa_ctx->outstanding_pkts)); + + if (unlikely(netif_queue_stopped(net))) { + RNDIS_IPA_ERROR_RL("interface queue is stopped\n"); + goto out; + } + + if (unlikely(rndis_ipa_ctx->tx_dump_enable)) + rndis_ipa_dump_skb(skb); + + if (unlikely(rndis_ipa_ctx->state != RNDIS_IPA_CONNECTED_AND_UP)) { + RNDIS_IPA_ERROR_RL("Missing pipe connected and/or iface up\n"); + return NETDEV_TX_BUSY; + } + + if (unlikely(tx_filter(skb))) { + dev_kfree_skb_any(skb); + RNDIS_IPA_DEBUG("packet got filtered out on Tx path\n"); + rndis_ipa_ctx->tx_dropped++; + status = NETDEV_TX_OK; + goto out; + } + + ret = ipa_pm_activate(rndis_ipa_ctx->pm_hdl); + if (ret) { + RNDIS_IPA_DEBUG("Failed activate PM client\n"); + netif_stop_queue(net); + goto fail_pm_activate; + } + + if (atomic_read(&rndis_ipa_ctx->outstanding_pkts) >= + rndis_ipa_ctx->outstanding_high) { + RNDIS_IPA_DEBUG("Outstanding high boundary reached (%d)\n", + rndis_ipa_ctx->outstanding_high); + netif_stop_queue(net); + RNDIS_IPA_DEBUG("send queue was stopped\n"); + status = NETDEV_TX_BUSY; + goto out; + } + + if (rndis_ipa_ctx->is_ulso_mode && + (net->features & (NETIF_F_ALL_TSO | NETIF_F_GSO_UDP_L4))){ + struct iphdr *iph = NULL; + /* + * gso_size must be set here because tx feature must be on + * meanning that in case of a small packet its checksum will + * not be computed and we must compute it using the hardware + * and thus marking it as gso packet, and the way to do it is to + * set gso_size to non 0 value. It is only used internally by + * the ipa driver so, there is no significance which non-0 value + * is set. + */ + if (ntohs(skb->protocol) == ETH_P_IP) { + iph = ip_hdr(skb); + if (IPV4_IS_TCP(iph) || IPV4_IS_UDP(iph)) { + skb = qmap_encapsulate_skb(skb, &qmap_template_hdr); + skb_shinfo(skb)->gso_size = + net->mtu - IPV4_DELTA; + } + } else if (ntohs(skb->protocol) == ETH_P_IPV6) { + iph = ip_hdr(skb); + if (IPV6_IS_TCP(iph) || IPV6_IS_UDP(iph)) { + skb = qmap_encapsulate_skb(skb, &qmap_template_hdr); + skb_shinfo(skb)->gso_size = + net->mtu - IPV6_DELTA; + } + } + } else { + skb = rndis_encapsulate_skb(skb, rndis_ipa_ctx); + } + /* This indicates no encapsulation was done - ulso mode with bad skb*/ + if (unlikely(skb_len == skb->len)) { + skb_shinfo(skb)->gso_size = 0; + skb = rndis_encapsulate_skb(skb, rndis_ipa_ctx); + } + trace_rndis_tx_dp(skb->protocol); + ret = ipa_tx_dp(IPA_TO_USB_CLIENT, skb, NULL); + if (ret) { + RNDIS_IPA_ERROR("ipa transmit failed (%d)\n", ret); + goto fail_tx_packet; + } + + atomic_inc(&rndis_ipa_ctx->outstanding_pkts); + + status = NETDEV_TX_OK; + goto out; + +fail_tx_packet: + rndis_ipa_xmit_error(skb); +out: + if (atomic_read(&rndis_ipa_ctx->outstanding_pkts) == 0) + ipa_pm_deferred_deactivate(rndis_ipa_ctx->pm_hdl); +fail_pm_activate: + + RNDIS_IPA_DEBUG + ("packet Tx done - %s\n", + (status == NETDEV_TX_OK) ? "OK" : "FAIL"); + + return status; +} + +/** + * rndis_ipa_tx_complete_notify() - notification for Netdev that the + * last packet was successfully sent + * @private: driver context stashed by IPA driver upon pipe connect + * @evt: event type (expected to be write-done event) + * @data: data provided with event (this is actually the skb that + * holds the sent packet) + * + * This function will be called on interrupt bottom halve deferred context. + * outstanding packets counter shall be decremented. + * Network stack send queue will be re-started in case low outstanding + * boundary is reached and queue was stopped before. + * At the end the skb shall be freed. + */ +static void rndis_ipa_tx_complete_notify( + void *private, + enum ipa_dp_evt_type evt, + unsigned long data) +{ + struct sk_buff *skb = (struct sk_buff *)data; + struct rndis_ipa_dev *rndis_ipa_ctx = private; + int ret; + + ret = 0; + NULL_CHECK_RETVAL(private); + if (ret) + return; + + trace_rndis_status_rcvd(skb->protocol); + + RNDIS_IPA_DEBUG + ("Tx-complete, len=%d, skb->prot=%d, outstanding=%d\n", + skb->len, skb->protocol, + atomic_read(&rndis_ipa_ctx->outstanding_pkts)); + + if (unlikely((evt != IPA_WRITE_DONE))) { + RNDIS_IPA_ERROR_RL("unsupported event on TX call-back\n"); + return; + } + + if (unlikely(rndis_ipa_ctx->state != RNDIS_IPA_CONNECTED_AND_UP)) { + RNDIS_IPA_DEBUG + ("dropping Tx-complete pkt, state=%s\n", + rndis_ipa_state_string(rndis_ipa_ctx->state)); + goto out; + } + + rndis_ipa_ctx->net->stats.tx_packets++; + rndis_ipa_ctx->net->stats.tx_bytes += skb->len; + + if (atomic_read(&rndis_ipa_ctx->outstanding_pkts) > 0) + atomic_dec(&rndis_ipa_ctx->outstanding_pkts); + + if + (netif_queue_stopped(rndis_ipa_ctx->net) && + netif_carrier_ok(rndis_ipa_ctx->net) && + atomic_read(&rndis_ipa_ctx->outstanding_pkts) < + (rndis_ipa_ctx->outstanding_low)) { + RNDIS_IPA_DEBUG("outstanding low boundary reached (%d)n", + rndis_ipa_ctx->outstanding_low); + netif_wake_queue(rndis_ipa_ctx->net); + RNDIS_IPA_DEBUG("send queue was awaken\n"); + } + + /*Release resource only when outstanding packets are zero*/ + if (atomic_read(&rndis_ipa_ctx->outstanding_pkts) == 0) + ipa_pm_deferred_deactivate(rndis_ipa_ctx->pm_hdl); + +out: + dev_kfree_skb_any(skb); +} + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 6, 0)) +static void rndis_ipa_tx_timeout(struct net_device *net, + unsigned int txqueue) +#else /* Legacy API. */ +static void rndis_ipa_tx_timeout(struct net_device *net) +#endif +{ + struct rndis_ipa_dev *rndis_ipa_ctx = netdev_priv(net); + int outstanding = atomic_read(&rndis_ipa_ctx->outstanding_pkts); + + RNDIS_IPA_ERROR + ("possible IPA stall was detected, %d outstanding\n", + outstanding); + + net->stats.tx_errors++; +} + +/** + * rndis_ipa_packet_receive_notify() - Rx notify for packet sent from + * tethered PC (USB->IPA). + * is USB->IPA->Apps-processor + * @private: driver context + * @evt: event type + * @data: data provided with event + * + * Once IPA driver receives a packet from USB client this callback will be + * called from bottom-half interrupt handling context (ipa Rx workqueue). + * + * Packets that shall be sent to Apps processor may be of two types: + * 1) Packets that are destined for Apps (e.g: WEBSERVER running on Apps) + * 2) Exception packets that need special handling (based on IPA core + * configuration, e.g: new TCP session or any other packets that IPA core + * can't handle) + * If the next conditions are met, the packet shall be sent up to the + * Linux network stack: + * - Driver internal state is Connected and Up + * - Notification received from IPA driver meets the expected type + * for Rx packet + * -Filters Rx switch are turned off + * + * Prior to the sending to the network stack: + * - Netdev struct shall be stashed to the skb as required by the network stack + * - Ethernet header shall be removed (skb->data shall point to the Ethernet + * payload, Ethernet still stashed under MAC header). + * - The skb->pkt_protocol shall be set based on the ethernet destination + * address, Can be Broadcast, Multicast or Other-Host, The later + * pkt-types packets shall be dropped in case the Netdev is not + * in promisc mode. + * - Set the skb protocol field based on the EtherType field + * + * Netdev status fields shall be updated based on the current Rx packet + */ +static void rndis_ipa_packet_receive_notify( + void *private, + enum ipa_dp_evt_type evt, + unsigned long data) +{ + struct sk_buff *skb = (struct sk_buff *)data; + struct rndis_ipa_dev *rndis_ipa_ctx = private; + unsigned int packet_len = skb->len; + + RNDIS_IPA_DEBUG + ("packet Rx, len=%d\n", + skb->len); + + if (unlikely(rndis_ipa_ctx == NULL)) { + RNDIS_IPA_DEBUG("Private context is NULL. Drop SKB.\n"); + dev_kfree_skb_any(skb); + return; + } + + if (unlikely(rndis_ipa_ctx->rx_dump_enable)) + rndis_ipa_dump_skb(skb); + + if (unlikely(rndis_ipa_ctx->state != RNDIS_IPA_CONNECTED_AND_UP)) { + RNDIS_IPA_DEBUG("use connect()/up() before receive()\n"); + RNDIS_IPA_DEBUG("packet dropped (length=%d)\n", + skb->len); + rndis_ipa_ctx->rx_dropped++; + dev_kfree_skb_any(skb); + return; + } + + if (evt != IPA_RECEIVE) { + RNDIS_IPA_ERROR_RL("a none IPA_RECEIVE event in driver RX\n"); + rndis_ipa_ctx->rx_dropped++; + dev_kfree_skb_any(skb); + return; + } + + if (!rndis_ipa_ctx->deaggregation_enable) + skb_pull(skb, sizeof(struct rndis_pkt_hdr)); + + skb->dev = rndis_ipa_ctx->net; + skb->protocol = eth_type_trans(skb, rndis_ipa_ctx->net); + + if (rx_filter(skb)) { + RNDIS_IPA_DEBUG("packet got filtered out on RX path\n"); + rndis_ipa_ctx->rx_dropped++; + dev_kfree_skb_any(skb); + return; + } + + trace_rndis_netif_ni(skb->protocol); + rndis_ipa_ctx->netif_rx_function(skb); + + rndis_ipa_ctx->net->stats.rx_packets++; + rndis_ipa_ctx->net->stats.rx_bytes += packet_len; +} + +/** rndis_ipa_stop() - notify the network interface to stop + * sending/receiving data + * @net: the network device being stopped. + * + * This API is used by Linux network stack to notify the network driver that + * its state was changed to "down" + * The driver will stop the "send" queue and change its internal + * state to "Connected". + * The Netdev shall be returned to be "Up" after rndis_ipa_open(). + */ +static int rndis_ipa_stop(struct net_device *net) +{ + struct rndis_ipa_dev *rndis_ipa_ctx = netdev_priv(net); + int next_state; + unsigned long flags; + + RNDIS_IPA_LOG_ENTRY(); + + spin_lock_irqsave(&rndis_ipa_ctx->state_lock, flags); + + next_state = rndis_ipa_next_state(rndis_ipa_ctx->state, RNDIS_IPA_STOP); + if (next_state == RNDIS_IPA_INVALID) { + spin_unlock_irqrestore(&rndis_ipa_ctx->state_lock, flags); + RNDIS_IPA_DEBUG("can't do network interface down without up\n"); + return -EPERM; + } + + rndis_ipa_ctx->state = next_state; + + spin_unlock_irqrestore(&rndis_ipa_ctx->state_lock, flags); + + netif_stop_queue(net); + pr_info("RNDIS_IPA NetDev queue is stopped\n"); + + RNDIS_IPA_STATE_DEBUG(rndis_ipa_ctx); + + RNDIS_IPA_LOG_EXIT(); + + return 0; +} + +/** rndis_ipa_disconnect() - notify rndis_ipa Netdev that the USB pipes + * were disconnected + * @private: same value that was set by init(), this parameter holds the + * network device pointer. + * + * USB shall notify the Netdev after disconnecting the pipe. + * - The internal driver state shall returned to its previous + * state (Up or Initialized). + * - Linux network stack shall be informed for carrier off to notify + * user space for pipe disconnect + * - send queue shall be stopped + * During the transition between the pipe disconnection to + * the Netdev notification packets + * are expected to be dropped by IPA driver or IPA core. + */ +int rndis_ipa_pipe_disconnect_notify(void *private) +{ + struct rndis_ipa_dev *rndis_ipa_ctx = private; + int next_state; + int outstanding_dropped_pkts; + int retval; + int ret; + unsigned long flags; + struct ipa_ecm_msg *rndis_msg; + struct ipa_msg_meta msg_meta; + + RNDIS_IPA_LOG_ENTRY(); + + ret = 0; + NULL_CHECK_RETVAL(rndis_ipa_ctx); + if (ret) + return ret; + RNDIS_IPA_DEBUG("private=0x%pK\n", private); + + spin_lock_irqsave(&rndis_ipa_ctx->state_lock, flags); + + next_state = rndis_ipa_next_state + (rndis_ipa_ctx->state, + RNDIS_IPA_DISCONNECT); + if (next_state == RNDIS_IPA_INVALID) { + spin_unlock_irqrestore(&rndis_ipa_ctx->state_lock, flags); + RNDIS_IPA_ERROR_RL("can't disconnect before connect\n"); + return -EPERM; + } + spin_unlock_irqrestore(&rndis_ipa_ctx->state_lock, flags); + + if (rndis_ipa_ctx->during_xmit_error) { + RNDIS_IPA_DEBUG("canceling xmit-error delayed work\n"); + cancel_delayed_work_sync( + &rndis_ipa_ctx->xmit_error_delayed_work); + rndis_ipa_ctx->during_xmit_error = false; + } + + netif_carrier_off(rndis_ipa_ctx->net); + RNDIS_IPA_DEBUG("carrier_off notification was sent\n"); + + rndis_msg = kzalloc(sizeof(*rndis_msg), GFP_KERNEL); + if (!rndis_msg) + return -ENOMEM; + + memset(&msg_meta, 0, sizeof(struct ipa_msg_meta)); + msg_meta.msg_type = ECM_DISCONNECT; + msg_meta.msg_len = sizeof(struct ipa_ecm_msg); + strlcpy(rndis_msg->name, rndis_ipa_ctx->net->name, + IPA_RESOURCE_NAME_MAX); + rndis_msg->ifindex = rndis_ipa_ctx->net->ifindex; + + retval = ipa_send_msg(&msg_meta, rndis_msg, rndis_ipa_msg_free_cb); + if (retval) { + RNDIS_IPA_ERROR("fail to send ECM_DISCONNECT for rndis\n"); + kfree(rndis_msg); + return -EPERM; + } + + netif_stop_queue(rndis_ipa_ctx->net); + RNDIS_IPA_DEBUG("queue stopped\n"); + + outstanding_dropped_pkts = + atomic_read(&rndis_ipa_ctx->outstanding_pkts); + + rndis_ipa_ctx->net->stats.tx_dropped += outstanding_dropped_pkts; + atomic_set(&rndis_ipa_ctx->outstanding_pkts, 0); + + retval = rndis_ipa_deregister_pm_client(rndis_ipa_ctx); + if (retval) { + RNDIS_IPA_ERROR("Fail to deregister PM\n"); + return retval; + } + RNDIS_IPA_DEBUG("PM was successfully deregistered\n"); + + spin_lock_irqsave(&rndis_ipa_ctx->state_lock, flags); + next_state = rndis_ipa_next_state(rndis_ipa_ctx->state, + RNDIS_IPA_DISCONNECT); + if (next_state == RNDIS_IPA_INVALID) { + spin_unlock_irqrestore(&rndis_ipa_ctx->state_lock, flags); + RNDIS_IPA_ERROR_RL("can't disconnect before connect\n"); + return -EPERM; + } + rndis_ipa_ctx->state = next_state; + spin_unlock_irqrestore(&rndis_ipa_ctx->state_lock, flags); + + RNDIS_IPA_STATE_DEBUG(rndis_ipa_ctx); + + pr_info("RNDIS_IPA NetDev pipes disconnected (%d outstanding clr)\n", + outstanding_dropped_pkts); + + RNDIS_IPA_LOG_EXIT(); + + return 0; +} +EXPORT_SYMBOL(rndis_ipa_pipe_disconnect_notify); + +/** + * rndis_ipa_cleanup() - unregister the network interface driver and free + * internal data structs. + * @private: same value that was set by init(), this + * parameter holds the network device pointer. + * + * This function shall be called once the network interface is not + * needed anymore, e.g: when the USB composition does not support it. + * This function shall be called after the pipes were disconnected. + * Detailed description: + * - remove header-insertion headers from IPA core + * - delete the driver dependency defined for IPA resource manager and + * destroy the producer resource. + * - remove the debugfs entries + * - deregister the network interface from Linux network stack + * - free all internal data structs + * + * It is assumed that no packets shall be sent through HW bridging + * during cleanup to avoid packets trying to add an header that is + * removed during cleanup (IPA configuration manager should have + * removed them at this point) + */ +void rndis_ipa_cleanup(void *private) +{ + struct rndis_ipa_dev *rndis_ipa_ctx = private; + int next_state; + int ret; + unsigned long flags; + + RNDIS_IPA_LOG_ENTRY(); + + RNDIS_IPA_DEBUG("private=0x%pK\n", private); + + ret = 0; + NULL_CHECK_RETVAL(rndis_ipa_ctx); + if (ret) + return; + + spin_lock_irqsave(&rndis_ipa_ctx->state_lock, flags); + next_state = rndis_ipa_next_state + (rndis_ipa_ctx->state, + RNDIS_IPA_CLEANUP); + if (next_state == RNDIS_IPA_INVALID) { + spin_unlock_irqrestore(&rndis_ipa_ctx->state_lock, flags); + RNDIS_IPA_ERROR_RL("use disconnect()before clean()\n"); + return; + } + spin_unlock_irqrestore(&rndis_ipa_ctx->state_lock, flags); + + RNDIS_IPA_STATE_DEBUG(rndis_ipa_ctx); + + ret = rndis_ipa_deregister_properties(rndis_ipa_ctx->net->name); + if (ret) { + RNDIS_IPA_ERROR("Fail to deregister Tx/Rx properties\n"); + return; + } + RNDIS_IPA_DEBUG("deregister Tx/Rx properties was successful\n"); + + if (rndis_ipa_ctx->is_ulso_mode) { + ret = ipa_hdrs_hpc_destroy(rndis_ipa_ctx->rndis_hdr_hdl); + if (ret) + RNDIS_IPA_ERROR("ipa_hdrs_hpc_destroy failed\n"); + else + RNDIS_IPA_DEBUG("ipa_hdrs_hpc_destroy success\n"); + } + + ret = rndis_ipa_hdrs_destroy(rndis_ipa_ctx); + if (ret) + RNDIS_IPA_ERROR( + "Failed removing RNDIS headers from IPA core. Continue anyway\n"); + else + RNDIS_IPA_DEBUG("RNDIS headers were removed from IPA core\n"); + + rndis_ipa_debugfs_destroy(rndis_ipa_ctx); + RNDIS_IPA_DEBUG("debugfs remove was done\n"); + + unregister_netdev(rndis_ipa_ctx->net); + RNDIS_IPA_DEBUG("netdev unregistered\n"); + + spin_lock_irqsave(&rndis_ipa_ctx->state_lock, flags); + next_state = rndis_ipa_next_state(rndis_ipa_ctx->state, + RNDIS_IPA_CLEANUP); + if (next_state == RNDIS_IPA_INVALID) { + spin_unlock_irqrestore(&rndis_ipa_ctx->state_lock, flags); + RNDIS_IPA_ERROR_RL("use disconnect()before clean()\n"); + return; + } + rndis_ipa_ctx->state = next_state; + spin_unlock_irqrestore(&rndis_ipa_ctx->state_lock, flags); + free_netdev(rndis_ipa_ctx->net); + pr_info("RNDIS_IPA NetDev was cleaned\n"); + + RNDIS_IPA_LOG_EXIT(); +} +EXPORT_SYMBOL(rndis_ipa_cleanup); + +static void rndis_ipa_enable_data_path(struct rndis_ipa_dev *rndis_ipa_ctx) +{ + if (rndis_ipa_ctx->device_ready_notify) { + rndis_ipa_ctx->device_ready_notify(); + RNDIS_IPA_DEBUG("USB device_ready_notify() was called\n"); + } else { + RNDIS_IPA_DEBUG("device_ready_notify() not supplied\n"); + } + + qmap_template_hdr.segment_size = htons(rndis_ipa_ctx->net->mtu - + sizeof(qmap_template_hdr)); + netif_start_queue(rndis_ipa_ctx->net); + RNDIS_IPA_DEBUG("netif_start_queue() was called\n"); +} + +static void rndis_ipa_xmit_error(struct sk_buff *skb) +{ + bool retval; + struct rndis_ipa_dev *rndis_ipa_ctx = netdev_priv(skb->dev); + unsigned long delay_jiffies; + u8 rand_dealy_msec; + + RNDIS_IPA_LOG_ENTRY(); + + RNDIS_IPA_DEBUG("starting Tx-queue backoff\n"); + + netif_stop_queue(rndis_ipa_ctx->net); + RNDIS_IPA_DEBUG("netif_stop_queue was called\n"); + + skb_pull(skb, sizeof(rndis_template_hdr)); + rndis_ipa_ctx->net->stats.tx_errors++; + + get_random_bytes(&rand_dealy_msec, sizeof(rand_dealy_msec)); + delay_jiffies = msecs_to_jiffies( + rndis_ipa_ctx->error_msec_sleep_time + rand_dealy_msec); + + retval = schedule_delayed_work( + &rndis_ipa_ctx->xmit_error_delayed_work, delay_jiffies); + if (!retval) { + RNDIS_IPA_ERROR("fail to schedule delayed work\n"); + netif_start_queue(rndis_ipa_ctx->net); + } else { + RNDIS_IPA_DEBUG + ("work scheduled to start Tx-queue in %d msec\n", + rndis_ipa_ctx->error_msec_sleep_time + + rand_dealy_msec); + rndis_ipa_ctx->during_xmit_error = true; + } + + RNDIS_IPA_LOG_EXIT(); +} + +static void rndis_ipa_xmit_error_aftercare_wq(struct work_struct *work) +{ + struct rndis_ipa_dev *rndis_ipa_ctx; + struct delayed_work *delayed_work; + + RNDIS_IPA_LOG_ENTRY(); + + RNDIS_IPA_DEBUG("Starting queue after xmit error\n"); + + delayed_work = to_delayed_work(work); + rndis_ipa_ctx = container_of + (delayed_work, struct rndis_ipa_dev, + xmit_error_delayed_work); + + if (unlikely(rndis_ipa_ctx->state != RNDIS_IPA_CONNECTED_AND_UP)) { + RNDIS_IPA_ERROR_RL + ("error aftercare handling in bad state (%d)", + rndis_ipa_ctx->state); + return; + } + + rndis_ipa_ctx->during_xmit_error = false; + + netif_start_queue(rndis_ipa_ctx->net); + RNDIS_IPA_DEBUG("netif_start_queue() was called\n"); + + RNDIS_IPA_LOG_EXIT(); +} + +/** + * rndis_ipa_prepare_header_insertion() - prepare the header insertion request + * for IPA driver + * eth_type: the Ethernet type for this header-insertion header + * hdr_name: string that shall represent this header in IPA data base + * add_hdr: output for caller to be used with ipa_add_hdr() to configure + * the IPA core + * dst_mac: tethered PC MAC (Ethernet) address to be added to packets + * for IPA->USB pipe + * src_mac: device MAC (Ethernet) address to be added to packets + * for IPA->USB pipe + * is_vlan_mode: should driver work in vlan mode? + * + * This function shall build the header-insertion block request for a + * single Ethernet+RNDIS header) + * this header shall be inserted for packets processed by IPA + * and destined for USB client. + * This header shall be used for HW bridging for packets destined for + * tethered PC. + * For SW data-path, this header won't be used. + */ +static void rndis_ipa_prepare_header_insertion( + int eth_type, + const char *hdr_name, struct ipa_hdr_add *add_hdr, + const void *dst_mac, const void *src_mac, bool is_vlan_mode) +{ + struct ethhdr *eth_hdr; + struct vlan_ethhdr *eth_vlan_hdr; + + add_hdr->hdr_len = sizeof(rndis_template_hdr); + add_hdr->is_partial = false; + strlcpy(add_hdr->name, hdr_name, IPA_RESOURCE_NAME_MAX); + + memcpy(add_hdr->hdr, &rndis_template_hdr, sizeof(rndis_template_hdr)); + add_hdr->is_eth2_ofst_valid = true; + add_hdr->eth2_ofst = sizeof(rndis_template_hdr); + + if (is_vlan_mode) { + eth_vlan_hdr = (struct vlan_ethhdr *)(add_hdr->hdr + + sizeof(rndis_template_hdr)); + memcpy(eth_vlan_hdr->h_dest, dst_mac, ETH_ALEN); + memcpy(eth_vlan_hdr->h_source, src_mac, ETH_ALEN); + eth_vlan_hdr->h_vlan_encapsulated_proto = htons(eth_type); + eth_vlan_hdr->h_vlan_proto = htons(ETH_P_8021Q); + add_hdr->hdr_len += VLAN_ETH_HLEN; + add_hdr->type = IPA_HDR_L2_802_1Q; + } else { + eth_hdr = (struct ethhdr *)(add_hdr->hdr + + sizeof(rndis_template_hdr)); + memcpy(eth_hdr->h_dest, dst_mac, ETH_ALEN); + memcpy(eth_hdr->h_source, src_mac, ETH_ALEN); + eth_hdr->h_proto = htons(eth_type); + add_hdr->hdr_len += ETH_HLEN; + add_hdr->type = IPA_HDR_L2_ETHERNET_II; + } +} + +/** + * rndis_ipa_hdrs_hpc_cfg() - configure hpc header insertion in IPA core + * @rndis_ipa_ctx: main driver context + * + * This function adds headers that are used by the hpc header insertion + * mechanism. + * + * Returns negative errno, or zero on success + */ +static int rndis_ipa_hdrs_hpc_cfg(struct rndis_ipa_dev *rndis_ipa_ctx) +{ + struct ipa_ioc_add_hdr *hdrs; + struct ipa_hdr_add *rndis_hdr; + struct ipa_pkt_init_ex_hdr_ofst_set lookup; + int result = 0; + + RNDIS_IPA_LOG_ENTRY(); + + hdrs = kzalloc(sizeof(*hdrs) + sizeof(*rndis_hdr), GFP_KERNEL); + if (!hdrs) { + result = -ENOMEM; + goto fail_mem; + } + rndis_hdr = &hdrs->hdr[0]; + strlcpy(rndis_hdr->name, RNDIS_HDR_NAME, sizeof(rndis_hdr->name)); + memcpy(rndis_hdr->hdr, &rndis_template_hdr, sizeof(rndis_template_hdr)); + rndis_hdr->hdr_len = sizeof(rndis_template_hdr); + rndis_hdr->hdr_hdl = -1; + rndis_hdr->is_partial = false; + rndis_hdr->status = -1; + hdrs->num_hdrs = 1; + hdrs->commit = 1; + + result = ipa3_add_hdr_hpc(hdrs); + if (result) { + RNDIS_IPA_ERROR("Fail on Header-Insertion(%d)\n", result); + goto fail_add_hdr; + } + if (rndis_hdr->status) { + RNDIS_IPA_ERROR("Fail on Header-Insertion rndis(%d)\n", + rndis_hdr->status); + result = rndis_hdr->status; + goto fail_add_hdr; + } + + rndis_ipa_ctx->rndis_hdr_hdl = rndis_hdr->hdr_hdl; + lookup.ep = IPA_TO_USB_CLIENT; + strlcpy(lookup.name, RNDIS_HDR_NAME, sizeof(lookup.name)); + if (ipa_set_pkt_init_ex_hdr_ofst(&lookup, true)) + goto fail_add_hdr; + + RNDIS_IPA_LOG_EXIT(); + +fail_add_hdr: + kfree(hdrs); +fail_mem: + return result; +} + +/** + * rndis_ipa_hdrs_cfg() - configure header insertion block in IPA core + * to allow HW bridging + * @rndis_ipa_ctx: main driver context + * @dst_mac: destination MAC address (tethered PC) + * @src_mac: source MAC address (MDM device) + * + * This function shall add 2 headers. + * One header for Ipv4 and one header for Ipv6. + * Both headers shall contain Ethernet header and RNDIS header, the only + * difference shall be in the EtherTye field. + * Headers will be committed to HW + * + * Returns negative errno, or zero on success + */ +static int rndis_ipa_hdrs_cfg( + struct rndis_ipa_dev *rndis_ipa_ctx, + const void *dst_mac, const void *src_mac) +{ + struct ipa_ioc_add_hdr *hdrs; + struct ipa_hdr_add *ipv4_hdr; + struct ipa_hdr_add *ipv6_hdr; + int result = 0; + + RNDIS_IPA_LOG_ENTRY(); + + hdrs = kzalloc(sizeof(*hdrs) + sizeof(*ipv4_hdr) + sizeof(*ipv6_hdr), + GFP_KERNEL); + if (!hdrs) { + result = -ENOMEM; + goto fail_mem; + } + + ipv4_hdr = &hdrs->hdr[0]; + ipv6_hdr = &hdrs->hdr[1]; + rndis_ipa_prepare_header_insertion(ETH_P_IP, IPV4_HDR_NAME, + ipv4_hdr, dst_mac, src_mac, rndis_ipa_ctx->is_vlan_mode); + rndis_ipa_prepare_header_insertion(ETH_P_IPV6, IPV6_HDR_NAME, + ipv6_hdr, dst_mac, src_mac, rndis_ipa_ctx->is_vlan_mode); + + hdrs->num_hdrs = 2; + hdrs->commit = 1; + result = ipa_add_hdr(hdrs); + if (result) { + RNDIS_IPA_ERROR("Fail on Header-Insertion(%d)\n", result); + goto fail_add_hdr; + } + if (ipv4_hdr->status) { + RNDIS_IPA_ERROR("Fail on Header-Insertion ipv4(%d)\n", + ipv4_hdr->status); + result = ipv4_hdr->status; + goto fail_add_hdr; + } + if (ipv6_hdr->status) { + RNDIS_IPA_ERROR("Fail on Header-Insertion ipv6(%d)\n", + ipv6_hdr->status); + result = ipv6_hdr->status; + goto fail_add_hdr; + } + rndis_ipa_ctx->eth_ipv4_hdr_hdl = ipv4_hdr->hdr_hdl; + rndis_ipa_ctx->eth_ipv6_hdr_hdl = ipv6_hdr->hdr_hdl; + + RNDIS_IPA_LOG_EXIT(); + +fail_add_hdr: + kfree(hdrs); +fail_mem: + return result; +} + +/** + * rndis_ipa_hdrs_destroy() - remove the IPA core configuration done for + * the driver data path bridging. + * @rndis_ipa_ctx: the driver context + * + * Revert the work done on rndis_ipa_hdrs_cfg(), which is, + * remove 2 headers for Ethernet+RNDIS. + */ +static int rndis_ipa_hdrs_destroy(struct rndis_ipa_dev *rndis_ipa_ctx) +{ + struct ipa_ioc_del_hdr *del_hdr; + struct ipa_hdr_del *ipv4; + struct ipa_hdr_del *ipv6; + int result; + + del_hdr = kzalloc(sizeof(*del_hdr) + sizeof(*ipv4) + + sizeof(*ipv6), GFP_KERNEL); + if (!del_hdr) + return -ENOMEM; + + del_hdr->commit = 1; + del_hdr->num_hdls = 2; + ipv4 = &del_hdr->hdl[0]; + ipv4->hdl = rndis_ipa_ctx->eth_ipv4_hdr_hdl; + ipv6 = &del_hdr->hdl[1]; + ipv6->hdl = rndis_ipa_ctx->eth_ipv6_hdr_hdl; + + result = ipa_del_hdr(del_hdr); + if (result || ipv4->status || ipv6->status) + RNDIS_IPA_ERROR("ipa_del_hdr failed\n"); + else + RNDIS_IPA_DEBUG("hdrs deletion done\n"); + + kfree(del_hdr); + return result; +} + +static struct net_device_stats *rndis_ipa_get_stats(struct net_device *net) +{ + return &net->stats; +} + +/** + * rndis_ipa_register_properties() - set Tx/Rx properties needed + * by IPA configuration manager + * @netdev_name: a string with the name of the network interface device + * @is_vlan_mode: should driver work in vlan mode? + * + * Register Tx/Rx properties to allow user space configuration (IPA + * Configuration Manager): + * + * - Two Tx properties (IPA->USB): specify the header names and pipe number + * that shall be used by user space for header-addition configuration + * for ipv4/ipv6 packets flowing from IPA to USB for HW bridging data. + * That header-addition header is added by the Netdev and used by user + * space to close the the HW bridge by adding filtering and routing rules + * that point to this header. + * + * - Two Rx properties (USB->IPA): these properties shall be used by user space + * to configure the IPA core to identify the packets destined + * for Apps-processor by configuring the unicast rules destined for + * the Netdev IP address. + * This rules shall be added based on the attribute mask supplied at + * this function, that is, always hit rule. + */ +static int rndis_ipa_register_properties(char *netdev_name, bool is_vlan_mode) +{ + struct ipa_tx_intf tx_properties = {0}; + struct ipa_ioc_tx_intf_prop properties[2] = { {0}, {0} }; + struct ipa_ioc_tx_intf_prop *ipv4_property; + struct ipa_ioc_tx_intf_prop *ipv6_property; + struct ipa_ioc_rx_intf_prop rx_ioc_properties[2] = { {0}, {0} }; + struct ipa_rx_intf rx_properties = {0}; + struct ipa_ioc_rx_intf_prop *rx_ipv4_property; + struct ipa_ioc_rx_intf_prop *rx_ipv6_property; + enum ipa_hdr_l2_type hdr_l2_type = IPA_HDR_L2_ETHERNET_II; + int result = 0; + + RNDIS_IPA_LOG_ENTRY(); + + if (is_vlan_mode) + hdr_l2_type = IPA_HDR_L2_802_1Q; + + tx_properties.prop = properties; + ipv4_property = &tx_properties.prop[0]; + ipv4_property->ip = IPA_IP_v4; + ipv4_property->dst_pipe = IPA_TO_USB_CLIENT; + strlcpy + (ipv4_property->hdr_name, IPV4_HDR_NAME, + IPA_RESOURCE_NAME_MAX); + ipv4_property->hdr_l2_type = hdr_l2_type; + ipv6_property = &tx_properties.prop[1]; + ipv6_property->ip = IPA_IP_v6; + ipv6_property->dst_pipe = IPA_TO_USB_CLIENT; + strlcpy + (ipv6_property->hdr_name, IPV6_HDR_NAME, + IPA_RESOURCE_NAME_MAX); + ipv6_property->hdr_l2_type = hdr_l2_type; + tx_properties.num_props = 2; + + rx_properties.prop = rx_ioc_properties; + rx_ipv4_property = &rx_properties.prop[0]; + rx_ipv4_property->ip = IPA_IP_v4; + rx_ipv4_property->attrib.attrib_mask = 0; + rx_ipv4_property->src_pipe = IPA_CLIENT_USB_PROD; + rx_ipv4_property->hdr_l2_type = hdr_l2_type; + rx_ipv6_property = &rx_properties.prop[1]; + rx_ipv6_property->ip = IPA_IP_v6; + rx_ipv6_property->attrib.attrib_mask = 0; + rx_ipv6_property->src_pipe = IPA_CLIENT_USB_PROD; + rx_ipv6_property->hdr_l2_type = hdr_l2_type; + rx_properties.num_props = 2; + + result = ipa_register_intf("rndis0", &tx_properties, &rx_properties); + if (result) + RNDIS_IPA_ERROR("fail on Tx/Rx properties registration\n"); + else + RNDIS_IPA_DEBUG("Tx/Rx properties registration done\n"); + + RNDIS_IPA_LOG_EXIT(); + + return result; +} + +/** + * rndis_ipa_deregister_properties() - remove the 2 Tx and 2 Rx properties + * @netdev_name: a string with the name of the network interface device + * + * This function revert the work done on rndis_ipa_register_properties(). + */ +static int rndis_ipa_deregister_properties(char *netdev_name) +{ + int result; + + RNDIS_IPA_LOG_ENTRY(); + + result = ipa_deregister_intf(netdev_name); + if (result) { + RNDIS_IPA_DEBUG("Fail on Tx prop deregister\n"); + return result; + } + RNDIS_IPA_LOG_EXIT(); + + return 0; +} + +static void rndis_ipa_pm_cb(void *p, enum ipa_pm_cb_event event) +{ + struct rndis_ipa_dev *rndis_ipa_ctx = p; + + RNDIS_IPA_LOG_ENTRY(); + + if (event != IPA_PM_CLIENT_ACTIVATED) { + RNDIS_IPA_ERROR_RL("unexpected event %d\n", event); + WARN_ON(1); + return; + } + RNDIS_IPA_DEBUG("Resource Granted\n"); + + if (netif_queue_stopped(rndis_ipa_ctx->net)) { + RNDIS_IPA_DEBUG("starting queue\n"); + netif_start_queue(rndis_ipa_ctx->net); + } else { + RNDIS_IPA_DEBUG("queue already awake\n"); + } + + RNDIS_IPA_LOG_EXIT(); +} + +static int rndis_ipa_register_pm_client(struct rndis_ipa_dev *rndis_ipa_ctx) +{ + int result; + struct ipa_pm_register_params pm_reg; + + memset(&pm_reg, 0, sizeof(pm_reg)); + + pm_reg.name = rndis_ipa_ctx->net->name; + pm_reg.user_data = rndis_ipa_ctx; + pm_reg.callback = rndis_ipa_pm_cb; + pm_reg.group = IPA_PM_GROUP_APPS; + result = ipa_pm_register(&pm_reg, &rndis_ipa_ctx->pm_hdl); + if (result) { + RNDIS_IPA_ERROR("failed to create IPA PM client %d\n", result); + return result; + } + return 0; +} + +static int rndis_ipa_deregister_pm_client(struct rndis_ipa_dev *rndis_ipa_ctx) +{ + ipa_pm_deactivate_sync(rndis_ipa_ctx->pm_hdl); + ipa_pm_deregister(rndis_ipa_ctx->pm_hdl); + rndis_ipa_ctx->pm_hdl = ~0; + return 0; +} + +/** + * rndis_encapsulate_skb() - encapsulate the given Ethernet skb with + * an RNDIS header + * @skb: packet to be encapsulated with the RNDIS header + * @rndis_ipa_ctx: main driver context + * + * Shall use a template header for RNDIS and update it with the given + * skb values. + * Ethernet 2 header should already be encapsulated in the packet. + */ +static struct sk_buff *rndis_encapsulate_skb(struct sk_buff *skb, + struct rndis_ipa_dev *rndis_ipa_ctx) +{ + struct rndis_pkt_hdr *rndis_hdr; + int payload_byte_len = skb->len; + + /* if there is no room in this skb, allocate a new one */ + if (unlikely(skb_headroom(skb) < sizeof(rndis_template_hdr))) { + struct sk_buff *new_skb = skb_copy_expand(skb, + sizeof(rndis_template_hdr), 0, GFP_ATOMIC); + + if (!new_skb) { + RNDIS_IPA_ERROR_RL("no memory for skb expand\n"); + return skb; + } + RNDIS_IPA_DEBUG("skb expanded. old %pK new %pK\n", + skb, new_skb); + dev_kfree_skb_any(skb); + skb = new_skb; + } + + if (rndis_ipa_ctx->is_vlan_mode) + if (unlikely(skb->protocol != htons(ETH_P_8021Q))) + RNDIS_IPA_DEBUG( + "ether_type != ETH_P_8021Q && vlan, prot = 0x%X\n" + , skb->protocol); + + /* make room at the head of the SKB to put the RNDIS header */ + rndis_hdr = (struct rndis_pkt_hdr *)skb_push(skb, + sizeof(rndis_template_hdr)); + + memcpy(rndis_hdr, &rndis_template_hdr, sizeof(*rndis_hdr)); + rndis_hdr->msg_len += payload_byte_len; + rndis_hdr->data_len += payload_byte_len; + + return skb; +} + +/** + * rx_filter() - logic that decide if the current skb is to be filtered out + * @skb: skb that may be sent up to the network stack + * + * This function shall do Rx packet filtering on the Netdev level. + */ +static bool rx_filter(struct sk_buff *skb) +{ + struct rndis_ipa_dev *rndis_ipa_ctx = netdev_priv(skb->dev); + + return rndis_ipa_ctx->rx_filter; +} + +/** + * tx_filter() - logic that decide if the current skb is to be filtered out + * @skb: skb that may be sent to the USB core + * + * This function shall do Tx packet filtering on the Netdev level. + * ICMP filter bypass is possible to allow only ICMP packet to be + * sent (pings and etc) + */ + +static bool tx_filter(struct sk_buff *skb) +{ + struct rndis_ipa_dev *rndis_ipa_ctx = netdev_priv(skb->dev); + bool is_icmp; + + if (likely(!rndis_ipa_ctx->tx_filter)) + return false; + + is_icmp = (skb->protocol == htons(ETH_P_IP) && + ip_hdr(skb)->protocol == IPPROTO_ICMP); + + if ((!rndis_ipa_ctx->icmp_filter) && is_icmp) + return false; + + return true; +} + + +/** + * rndis_ipa_ep_registers_cfg() - configure the USB endpoints + * @usb_to_ipa_hdl: handle received from ipa_connect which represents + * the USB to IPA end-point + * @ipa_to_usb_hdl: handle received from ipa_connect which represents + * the IPA to USB end-point + * @max_xfer_size_bytes_to_dev: the maximum size, in bytes, that the device + * expects to receive from the host. supplied on REMOTE_NDIS_INITIALIZE_CMPLT. + * @max_xfer_size_bytes_to_host: the maximum size, in bytes, that the host + * expects to receive from the device. supplied on REMOTE_NDIS_INITIALIZE_MSG. + * @mtu: the netdev MTU size, in bytes + * @deaggr_enable: should deaggregation be enabled? + * @is_vlan_mode: should driver work in vlan mode? + * + * USB to IPA pipe: + * - de-aggregation + * - Remove Ethernet header + * - Remove RNDIS header + * - SRC NAT + * - Default routing(0) + * IPA to USB Pipe: + * - aggregation + * - Add Ethernet header + * - Add RNDIS header + */ +static int rndis_ipa_ep_registers_cfg( + u32 usb_to_ipa_hdl, + u32 ipa_to_usb_hdl, + u32 max_xfer_size_bytes_to_dev, + u32 max_xfer_size_bytes_to_host, + u32 mtu, + bool deaggr_enable, + bool is_vlan_mode) +{ + int result; + struct ipa_ep_cfg *usb_to_ipa_ep_cfg; + int add = 0; + + if (deaggr_enable) { + usb_to_ipa_ep_cfg = &usb_to_ipa_ep_cfg_deaggr_en; + RNDIS_IPA_DEBUG("deaggregation enabled\n"); + } else { + usb_to_ipa_ep_cfg = &usb_to_ipa_ep_cfg_deaggr_dis; + RNDIS_IPA_DEBUG("deaggregation disabled\n"); + add = sizeof(struct rndis_pkt_hdr); + } + + if (is_vlan_mode) { + usb_to_ipa_ep_cfg->hdr.hdr_len = VLAN_ETH_HLEN + add; + ipa_to_usb_ep_cfg.hdr.hdr_len = + VLAN_ETH_HLEN + sizeof(struct rndis_pkt_hdr); + ipa_to_usb_ep_cfg.hdr.hdr_additional_const_len = VLAN_ETH_HLEN; + qmap_template_hdr.additional_hdr_size = + VLAN_ETH_HLEN - ETH_HLEN; + } else { + usb_to_ipa_ep_cfg->hdr.hdr_len = ETH_HLEN + add; + ipa_to_usb_ep_cfg.hdr.hdr_len = + ETH_HLEN + sizeof(struct rndis_pkt_hdr); + ipa_to_usb_ep_cfg.hdr.hdr_additional_const_len = ETH_HLEN; + } + + usb_to_ipa_ep_cfg->deaggr.max_packet_len = max_xfer_size_bytes_to_dev; + + result = ipa3_cfg_ep(usb_to_ipa_hdl, usb_to_ipa_ep_cfg); + if (result) { + pr_err("failed to configure USB to IPA point\n"); + return result; + } + RNDIS_IPA_DEBUG("IPA<-USB end-point configured\n"); + + ipa_to_usb_ep_cfg.aggr.aggr_byte_limit = + (max_xfer_size_bytes_to_host - mtu) / 1024; + + if (ipa_to_usb_ep_cfg.aggr.aggr_byte_limit == 0) { + ipa_to_usb_ep_cfg.aggr.aggr_time_limit = 0; + ipa_to_usb_ep_cfg.aggr.aggr_pkt_limit = 1; + } else { + ipa_to_usb_ep_cfg.aggr.aggr_time_limit = + DEFAULT_AGGR_TIME_LIMIT; + ipa_to_usb_ep_cfg.aggr.aggr_pkt_limit = DEFAULT_AGGR_PKT_LIMIT; + } + + RNDIS_IPA_DEBUG( + "RNDIS aggregation param: en=%d byte_limit=%d time_limit=%d pkt_limit=%d\n" + , ipa_to_usb_ep_cfg.aggr.aggr_en, + ipa_to_usb_ep_cfg.aggr.aggr_byte_limit, + ipa_to_usb_ep_cfg.aggr.aggr_time_limit, + ipa_to_usb_ep_cfg.aggr.aggr_pkt_limit); + + /* enable hdr_metadata_reg_valid */ + usb_to_ipa_ep_cfg->hdr.hdr_metadata_reg_valid = true; + + if (ipa3_is_ulso_supported()) + ipa_to_usb_ep_cfg.ulso.is_ulso_pipe = true; + + /*xlat config in vlan mode */ + if (is_vlan_mode) { + usb_to_ipa_ep_cfg->hdr.hdr_ofst_metadata_valid = 1; + usb_to_ipa_ep_cfg->hdr.hdr_ofst_metadata = + sizeof(struct rndis_pkt_hdr) + ETH_HLEN; + usb_to_ipa_ep_cfg->hdr.hdr_metadata_reg_valid = false; + } + + result = ipa3_cfg_ep(ipa_to_usb_hdl, &ipa_to_usb_ep_cfg); + if (result) { + pr_err("failed to configure IPA to USB end-point\n"); + return result; + } + RNDIS_IPA_DEBUG("IPA->USB end-point configured\n"); + + return 0; +} + +/** + * rndis_ipa_set_device_ethernet_addr() - set device Ethernet address + * @dev_ethaddr: device Ethernet address + * + * Returns 0 for success, negative otherwise + */ +static int rndis_ipa_set_device_ethernet_addr( + struct net_device *net, + u8 device_ethaddr[]) +{ + if (!is_valid_ether_addr(device_ethaddr)) + return -EINVAL; + +#if (LINUX_VERSION_CODE > KERNEL_VERSION(5, 15, 0)) + net->addr_len = ETH_ALEN; + dev_addr_set(net, device_ethaddr); +#else + memcpy((u8 *)net->dev_addr, device_ethaddr, ETH_ALEN); +#endif + + return 0; +} + +/** rndis_ipa_next_state - return the next state of the driver + * @current_state: the current state of the driver + * @operation: an enum which represent the operation being made on the driver + * by its API. + * + * This function implements the driver internal state machine. + * Its decisions are based on the driver current state and the operation + * being made. + * In case the operation is invalid this state machine will return + * the value RNDIS_IPA_INVALID to inform the caller for a forbidden sequence. + */ +static enum rndis_ipa_state rndis_ipa_next_state( + enum rndis_ipa_state current_state, + enum rndis_ipa_operation operation) +{ + int next_state = RNDIS_IPA_INVALID; + + switch (current_state) { + case RNDIS_IPA_UNLOADED: + if (operation == RNDIS_IPA_INITIALIZE) + next_state = RNDIS_IPA_INITIALIZED; + break; + case RNDIS_IPA_INITIALIZED: + if (operation == RNDIS_IPA_CONNECT) + next_state = RNDIS_IPA_CONNECTED; + else if (operation == RNDIS_IPA_OPEN) + next_state = RNDIS_IPA_UP; + else if (operation == RNDIS_IPA_CLEANUP) + next_state = RNDIS_IPA_UNLOADED; + break; + case RNDIS_IPA_CONNECTED: + if (operation == RNDIS_IPA_DISCONNECT) + next_state = RNDIS_IPA_INITIALIZED; + else if (operation == RNDIS_IPA_OPEN) + next_state = RNDIS_IPA_CONNECTED_AND_UP; + break; + case RNDIS_IPA_UP: + if (operation == RNDIS_IPA_STOP) + next_state = RNDIS_IPA_INITIALIZED; + else if (operation == RNDIS_IPA_CONNECT) + next_state = RNDIS_IPA_CONNECTED_AND_UP; + else if (operation == RNDIS_IPA_CLEANUP) + next_state = RNDIS_IPA_UNLOADED; + break; + case RNDIS_IPA_CONNECTED_AND_UP: + if (operation == RNDIS_IPA_STOP) + next_state = RNDIS_IPA_CONNECTED; + else if (operation == RNDIS_IPA_DISCONNECT) + next_state = RNDIS_IPA_UP; + break; + default: + RNDIS_IPA_ERROR_RL("State is not supported\n"); + break; + } + + RNDIS_IPA_DEBUG + ("state transition ( %s -> %s )- %s\n", + rndis_ipa_state_string(current_state), + rndis_ipa_state_string(next_state), + next_state == RNDIS_IPA_INVALID ? + "Forbidden" : "Allowed"); + + return next_state; +} + +/** + * rndis_ipa_state_string - return the state string representation + * @state: enum which describe the state + */ +static const char *rndis_ipa_state_string(enum rndis_ipa_state state) +{ + switch (state) { + case RNDIS_IPA_UNLOADED: + return "RNDIS_IPA_UNLOADED"; + case RNDIS_IPA_INITIALIZED: + return "RNDIS_IPA_INITIALIZED"; + case RNDIS_IPA_CONNECTED: + return "RNDIS_IPA_CONNECTED"; + case RNDIS_IPA_UP: + return "RNDIS_IPA_UP"; + case RNDIS_IPA_CONNECTED_AND_UP: + return "RNDIS_IPA_CONNECTED_AND_UP"; + default: + return "Not supported"; + } +} + +static void rndis_ipa_dump_skb(struct sk_buff *skb) +{ + int i; + u32 *cur = (u32 *)skb->data; + u8 *byte; + + RNDIS_IPA_DEBUG + ("packet dump start for skb->len=%d\n", + skb->len); + + for (i = 0; i < (skb->len / 4); i++) { + byte = (u8 *)(cur + i); + pr_info + ("%2d %08x %02x %02x %02x %02x\n", + i, *(cur + i), + byte[0], byte[1], byte[2], byte[3]); + } + RNDIS_IPA_DEBUG + ("packet dump ended for skb->len=%d\n", skb->len); +} + +#ifdef CONFIG_DEBUG_FS +/** + * Creates the root folder for the driver + */ +static void rndis_ipa_debugfs_init(struct rndis_ipa_dev *rndis_ipa_ctx) +{ + const mode_t flags_read_write = 0666; + const mode_t flags_read_only = 0444; + const mode_t flags_write_only = 0222; + struct dentry *file; + struct dentry *aggr_directory; + + RNDIS_IPA_LOG_ENTRY(); + + if (!rndis_ipa_ctx) + return; + + rndis_ipa_ctx->directory = debugfs_create_dir(DEBUGFS_DIR_NAME, NULL); + if (!rndis_ipa_ctx->directory) { + RNDIS_IPA_ERROR("could not create debugfs directory entry\n"); + goto fail_directory; + } + + debugfs_create_bool + ("tx_filter", flags_read_write, + rndis_ipa_ctx->directory, &rndis_ipa_ctx->tx_filter); + + debugfs_create_bool + ("rx_filter", flags_read_write, + rndis_ipa_ctx->directory, &rndis_ipa_ctx->rx_filter); + + debugfs_create_bool + ("icmp_filter", flags_read_write, + rndis_ipa_ctx->directory, &rndis_ipa_ctx->icmp_filter); + + debugfs_create_u32 + ("outstanding_high", flags_read_write, + rndis_ipa_ctx->directory, + &rndis_ipa_ctx->outstanding_high); + + debugfs_create_u32 + ("outstanding_low", flags_read_write, + rndis_ipa_ctx->directory, + &rndis_ipa_ctx->outstanding_low); + + file = debugfs_create_file + ("outstanding", flags_read_only, + rndis_ipa_ctx->directory, + rndis_ipa_ctx, &rndis_ipa_debugfs_atomic_ops); + if (!file) { + RNDIS_IPA_ERROR("could not create outstanding file\n"); + goto fail_file; + } + + debugfs_create_u8 + ("state", flags_read_only, + rndis_ipa_ctx->directory, (u8 *)&rndis_ipa_ctx->state); + + debugfs_create_u32 + ("tx_dropped", flags_read_only, + rndis_ipa_ctx->directory, &rndis_ipa_ctx->tx_dropped); + + debugfs_create_u32 + ("rx_dropped", flags_read_only, + rndis_ipa_ctx->directory, &rndis_ipa_ctx->rx_dropped); + + aggr_directory = debugfs_create_dir + (DEBUGFS_AGGR_DIR_NAME, + rndis_ipa_ctx->directory); + if (!aggr_directory) { + RNDIS_IPA_ERROR("could not create debugfs aggr entry\n"); + goto fail_directory; + } + + file = debugfs_create_file + ("aggr_value_set", flags_write_only, + aggr_directory, + rndis_ipa_ctx, &rndis_ipa_aggr_ops); + if (!file) { + RNDIS_IPA_ERROR("could not create aggr_value_set file\n"); + goto fail_file; + } + + debugfs_create_u8 + ("aggr_enable", flags_read_write, + aggr_directory, (u8 *)&ipa_to_usb_ep_cfg.aggr.aggr_en); + + debugfs_create_u8 + ("aggr_type", flags_read_write, + aggr_directory, (u8 *)&ipa_to_usb_ep_cfg.aggr.aggr); + + debugfs_create_u32 + ("aggr_byte_limit", flags_read_write, + aggr_directory, + &ipa_to_usb_ep_cfg.aggr.aggr_byte_limit); + + debugfs_create_u32 + ("aggr_time_limit", flags_read_write, + aggr_directory, + &ipa_to_usb_ep_cfg.aggr.aggr_time_limit); + + debugfs_create_u32 + ("aggr_pkt_limit", flags_read_write, + aggr_directory, + &ipa_to_usb_ep_cfg.aggr.aggr_pkt_limit); + + debugfs_create_bool + ("tx_dump_enable", flags_read_write, + rndis_ipa_ctx->directory, + &rndis_ipa_ctx->tx_dump_enable); + + debugfs_create_bool + ("rx_dump_enable", flags_read_write, + rndis_ipa_ctx->directory, + &rndis_ipa_ctx->rx_dump_enable); + + debugfs_create_bool + ("deaggregation_enable", flags_read_write, + rndis_ipa_ctx->directory, + &rndis_ipa_ctx->deaggregation_enable); + + debugfs_create_u32 + ("error_msec_sleep_time", flags_read_write, + rndis_ipa_ctx->directory, + &rndis_ipa_ctx->error_msec_sleep_time); + + debugfs_create_bool + ("during_xmit_error", flags_read_only, + rndis_ipa_ctx->directory, + &rndis_ipa_ctx->during_xmit_error); + + debugfs_create_bool("is_vlan_mode", flags_read_only, + rndis_ipa_ctx->directory, + &rndis_ipa_ctx->is_vlan_mode); + + RNDIS_IPA_DEBUG("debugfs entries were created\n"); + RNDIS_IPA_LOG_EXIT(); + + return; +fail_file: + debugfs_remove_recursive(rndis_ipa_ctx->directory); +fail_directory: + return; +} + +static void rndis_ipa_debugfs_destroy(struct rndis_ipa_dev *rndis_ipa_ctx) +{ + debugfs_remove_recursive(rndis_ipa_ctx->directory); +} + +#else /* !CONFIG_DEBUG_FS */ + +static void rndis_ipa_debugfs_init(struct rndis_ipa_dev *rndis_ipa_ctx) {} + +static void rndis_ipa_debugfs_destroy(struct rndis_ipa_dev *rndis_ipa_ctx) {} + +#endif /* CONFIG_DEBUG_FS*/ + +static int rndis_ipa_debugfs_aggr_open + (struct inode *inode, + struct file *file) +{ + struct rndis_ipa_dev *rndis_ipa_ctx = inode->i_private; + + file->private_data = rndis_ipa_ctx; + + return 0; +} + +static ssize_t rndis_ipa_debugfs_aggr_write + (struct file *file, + const char __user *buf, size_t count, loff_t *ppos) +{ + struct rndis_ipa_dev *rndis_ipa_ctx = NULL; + int result; + + if (file == NULL) + return -EFAULT; + rndis_ipa_ctx = file->private_data; + + result = ipa3_cfg_ep(rndis_ipa_ctx->usb_to_ipa_hdl, &ipa_to_usb_ep_cfg); + if (result) { + pr_err("failed to re-configure USB to IPA point\n"); + return result; + } + pr_info("IPA<-USB end-point re-configured\n"); + + return count; +} + +static int rndis_ipa_debugfs_atomic_open(struct inode *inode, struct file *file) +{ + struct rndis_ipa_dev *rndis_ipa_ctx = inode->i_private; + + RNDIS_IPA_LOG_ENTRY(); + + file->private_data = &rndis_ipa_ctx->outstanding_pkts; + + RNDIS_IPA_LOG_EXIT(); + + return 0; +} + +static ssize_t rndis_ipa_debugfs_atomic_read + (struct file *file, char __user *ubuf, size_t count, loff_t *ppos) +{ + int nbytes; + u8 atomic_str[DEBUGFS_TEMP_BUF_SIZE] = {0}; + atomic_t *atomic_var = file->private_data; + + RNDIS_IPA_LOG_ENTRY(); + + nbytes = scnprintf + (atomic_str, sizeof(atomic_str), "%d\n", + atomic_read(atomic_var)); + + RNDIS_IPA_LOG_EXIT(); + + return simple_read_from_buffer(ubuf, count, ppos, atomic_str, nbytes); +} + +int rndis_ipa_init_module(void) +{ + ipa_rndis_logbuf = ipc_log_context_create(IPA_RNDIS_IPC_LOG_PAGES, + "ipa_rndis", MINIDUMP_MASK); + if (ipa_rndis_logbuf == NULL) + RNDIS_IPA_ERROR("failed to create IPC log, continue...\n"); + + pr_info("RNDIS_IPA module is loaded.\n"); + return 0; +} +EXPORT_SYMBOL(rndis_ipa_init_module); + +void rndis_ipa_cleanup_module(void) +{ + if (ipa_rndis_logbuf) + ipc_log_context_destroy(ipa_rndis_logbuf); + ipa_rndis_logbuf = NULL; + + pr_info("RNDIS_IPA module is unloaded.\n"); +} +EXPORT_SYMBOL(rndis_ipa_cleanup_module); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("RNDIS_IPA network interface"); + +//late_initcall(rndis_ipa_init_module); +//module_exit(rndis_ipa_cleanup_module); diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_clients/rndis_ipa.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_clients/rndis_ipa.h new file mode 100644 index 0000000000..cc1808ed02 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_clients/rndis_ipa.h @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2013-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _RNDIS_IPA_H_ +#define _RNDIS_IPA_H_ + +#include "ipa.h" + +/* + * @priv: private data given upon ipa_connect + * @evt: event enum, should be IPA_WRITE_DONE + * @data: for tx path the data field is the sent socket buffer. + */ +typedef void (*ipa_callback)(void *priv, + enum ipa_dp_evt_type evt, + unsigned long data); + +/* + * struct ipa_usb_init_params - parameters for driver initialization API + * + * @device_ready_notify: callback supplied by USB core driver + * This callback shall be called by the Netdev once the device + * is ready to receive data from tethered PC. + * @ipa_rx_notify: The network driver will set this callback (out parameter). + * this callback shall be supplied for ipa_connect upon pipe + * connection (USB->IPA), once IPA driver receive data packets + * from USB pipe destined for Apps this callback will be called. + * @ipa_tx_notify: The network driver will set this callback (out parameter). + * this callback shall be supplied for ipa_connect upon pipe + * connection (IPA->USB), once IPA driver send packets destined + * for USB, IPA BAM will notify for Tx-complete. + * @host_ethaddr: host Ethernet address in network order + * @device_ethaddr: device Ethernet address in network order + * @private: The network driver will set this pointer (out parameter). + * This pointer will hold the network device for later interaction + * with between USB driver and the network driver. + * @skip_ep_cfg: boolean field that determines if Apps-processor + * should or should not configure this end-point. + */ +struct ipa_usb_init_params { + void (*device_ready_notify)(void); + ipa_callback ipa_rx_notify; + ipa_callback ipa_tx_notify; + u8 host_ethaddr[ETH_ALEN]; + u8 device_ethaddr[ETH_ALEN]; + void *private; + bool skip_ep_cfg; +}; + +#if IS_ENABLED(CONFIG_RNDIS_IPA) + +int rndis_ipa_init(struct ipa_usb_init_params *params); + +int rndis_ipa_pipe_connect_notify(u32 usb_to_ipa_hdl, + u32 ipa_to_usb_hdl, + u32 max_xfer_size_bytes_to_dev, + u32 max_packet_number_to_dev, + u32 max_xfer_size_bytes_to_host, + void *private); + +int rndis_ipa_pipe_disconnect_notify(void *private); + +void rndis_ipa_cleanup(void *private); + +int rndis_ipa_init_module(void); +void rndis_ipa_cleanup_module(void); + +#else /* IS_ENABLED(CONFIG_RNDIS_IPA) */ + +static inline int rndis_ipa_init(struct ipa_usb_init_params *params) +{ + return -ENOMEM; +} + +static inline int rndis_ipa_pipe_connect_notify(u32 usb_to_ipa_hdl, + u32 ipa_to_usb_hdl, + u32 max_xfer_size_bytes_to_dev, + u32 max_packet_number_to_dev, + u32 max_xfer_size_bytes_to_host, + void *private) +{ + return -ENOMEM; +} + +static inline int rndis_ipa_pipe_disconnect_notify(void *private) +{ + return -ENOMEM; +} + +static inline void rndis_ipa_cleanup(void *private) +{ +} + +#endif /* IS_ENABLED(CONFIG_RNDIS_IPA) */ + +#endif /* _RNDIS_IPA_H_ */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_clients/rndis_ipa_trace.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_clients/rndis_ipa_trace.h new file mode 100644 index 0000000000..7eb499f646 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_clients/rndis_ipa_trace.h @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#undef TRACE_SYSTEM +#define TRACE_SYSTEM rndis_ipa +#define TRACE_INCLUDE_FILE rndis_ipa_trace + +#if !defined(_RNDIS_IPA_TRACE_H) || defined(TRACE_HEADER_MULTI_READ) +#define _RNDIS_IPA_TRACE_H + +#include + +TRACE_EVENT( + rndis_netif_ni, + + TP_PROTO(unsigned long proto), + + TP_ARGS(proto), + + TP_STRUCT__entry( + __field(unsigned long, proto) + ), + + TP_fast_assign( + __entry->proto = proto; + ), + + TP_printk("proto =%lu\n", __entry->proto) +); + +TRACE_EVENT( + rndis_tx_dp, + + TP_PROTO(unsigned long proto), + + TP_ARGS(proto), + + TP_STRUCT__entry( + __field(unsigned long, proto) + ), + + TP_fast_assign( + __entry->proto = proto; + ), + + TP_printk("proto =%lu\n", __entry->proto) +); + +TRACE_EVENT( + rndis_status_rcvd, + + TP_PROTO(unsigned long proto), + + TP_ARGS(proto), + + TP_STRUCT__entry( + __field(unsigned long, proto) + ), + + TP_fast_assign( + __entry->proto = proto; + ), + + TP_printk("proto =%lu\n", __entry->proto) +); + +#endif /* _RNDIS_IPA_TRACE_H */ + +/* This part must be outside protection */ +#ifndef RNDIS_TRACE_INCLUDE_PATH +#ifdef CONFIG_IPA_VENDOR_DLKM +#define RNDIS_TRACE_INCLUDE_PATH ../../../../vendor/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_clients +#else +#define RNDIS_TRACE_INCLUDE_PATH ../../techpack/dataipa/drivers/platform/msm/ipa/ipa_clients +#endif +#endif + +#define TRACE_INCLUDE_PATH RNDIS_TRACE_INCLUDE_PATH +#include diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_common_i.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_common_i.h new file mode 100644 index 0000000000..6f4a215f22 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_common_i.h @@ -0,0 +1,951 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. + * + * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _IPA_COMMON_I_H_ +#define _IPA_COMMON_I_H_ +#include +#include +#include +#include "ipa.h" +#include "ipa_uc_offload.h" +#include "ipa_wdi3.h" +#include "ipa_wigig.h" +#include "ipa_eth.h" +#include +#include +#include +#include "ipa_stats.h" +#include "gsi.h" + +#ifndef IPA_ETH_API_VER +#define IPA_ETH_API_VER 1 +#endif + +#define WARNON_RATELIMIT_BURST 1 +#define IPA_RATELIMIT_BURST 1 +#define IPA_EP_ARR_SIZE 2 +#define IPA_EP_PER_REG 32 + +#define __FILENAME__ \ + (strrchr(__FILE__, '/') ? strrchr(__FILE__, '/') + 1 : __FILE__) + +#define IPA_ACTIVE_CLIENTS_PREP_EP(log_info, client) \ + log_info.file = __FILENAME__; \ + log_info.line = __LINE__; \ + log_info.type = EP; \ + log_info.id_string = (client < 0 || client >= IPA_CLIENT_MAX) \ + ? "Invalid Client" : ipa_clients_strings[client] + +#define IPA_ACTIVE_CLIENTS_PREP_SIMPLE(log_info) \ + log_info.file = __FILENAME__; \ + log_info.line = __LINE__; \ + log_info.type = SIMPLE; \ + log_info.id_string = __func__ + +#define IPA_ACTIVE_CLIENTS_PREP_RESOURCE(log_info, resource_name) \ + log_info.file = __FILENAME__; \ + log_info.line = __LINE__; \ + log_info.type = RESOURCE; \ + log_info.id_string = resource_name + +#define IPA_ACTIVE_CLIENTS_PREP_SPECIAL(log_info, id_str) \ + log_info.file = __FILENAME__; \ + log_info.line = __LINE__; \ + log_info.type = SPECIAL; \ + log_info.id_string = id_str + +#define IPA_ACTIVE_CLIENTS_INC_EP(client) \ + do { \ + struct ipa_active_client_logging_info log_info; \ + IPA_ACTIVE_CLIENTS_PREP_EP(log_info, client); \ + ipa3_inc_client_enable_clks(&log_info); \ + } while (0) + +#define IPA_ACTIVE_CLIENTS_DEC_EP(client) \ + do { \ + struct ipa_active_client_logging_info log_info; \ + IPA_ACTIVE_CLIENTS_PREP_EP(log_info, client); \ + ipa3_dec_client_disable_clks(&log_info); \ + } while (0) + +#define IPA_ACTIVE_CLIENTS_INC_SIMPLE() \ + do { \ + struct ipa_active_client_logging_info log_info; \ + IPA_ACTIVE_CLIENTS_PREP_SIMPLE(log_info); \ + ipa3_inc_client_enable_clks(&log_info); \ + } while (0) + +#define IPA_ACTIVE_CLIENTS_DEC_SIMPLE() \ + do { \ + struct ipa_active_client_logging_info log_info; \ + IPA_ACTIVE_CLIENTS_PREP_SIMPLE(log_info); \ + ipa3_dec_client_disable_clks(&log_info); \ + } while (0) + +#define IPA_ACTIVE_CLIENTS_INC_RESOURCE(resource_name) \ + do { \ + struct ipa_active_client_logging_info log_info; \ + IPA_ACTIVE_CLIENTS_PREP_RESOURCE(log_info, resource_name); \ + ipa3_inc_client_enable_clks(&log_info); \ + } while (0) + +#define IPA_ACTIVE_CLIENTS_DEC_RESOURCE(resource_name) \ + do { \ + struct ipa_active_client_logging_info log_info; \ + IPA_ACTIVE_CLIENTS_PREP_RESOURCE(log_info, resource_name); \ + ipa3_dec_client_disable_clks(&log_info); \ + } while (0) + +#define IPA_ACTIVE_CLIENTS_INC_SPECIAL(id_str) \ + do { \ + struct ipa_active_client_logging_info log_info; \ + IPA_ACTIVE_CLIENTS_PREP_SPECIAL(log_info, id_str); \ + ipa3_inc_client_enable_clks(&log_info); \ + } while (0) + +#define IPA_ACTIVE_CLIENTS_DEC_SPECIAL(id_str) \ + do { \ + struct ipa_active_client_logging_info log_info; \ + IPA_ACTIVE_CLIENTS_PREP_SPECIAL(log_info, id_str); \ + ipa3_dec_client_disable_clks(&log_info); \ + } while (0) + +#define IPA_ACTIVE_CLIENTS_INC_EP_NO_BLOCK(client) ({\ + int __ret = 0; \ + do { \ + struct ipa_active_client_logging_info log_info; \ + IPA_ACTIVE_CLIENTS_PREP_EP(log_info, client); \ + __ret = ipa3_inc_client_enable_clks_no_block(&log_info); \ + } while (0); \ + (__ret); \ +}) + +#define IPA_ACTIVE_CLIENTS_DEC_EP_NO_BLOCK(client) \ + do { \ + struct ipa_active_client_logging_info log_info; \ + IPA_ACTIVE_CLIENTS_PREP_EP(log_info, client); \ + ipa3_dec_client_disable_clks_no_block(&log_info); \ + } while (0) + +#ifdef IPA_DEBUG +/* + * Printing one warning message in 5 seconds if multiple warning messages + * are coming back to back. + */ + +#define WARN_ON_RATELIMIT_IPA(condition) \ +({ \ + static DEFINE_RATELIMIT_STATE(_rs, \ + DEFAULT_RATELIMIT_INTERVAL, \ + WARNON_RATELIMIT_BURST); \ + int rtn = !!(condition); \ + \ + if (unlikely(rtn && __ratelimit(&_rs))) \ + WARN_ON(rtn); \ +}) +#else +#define WARN_ON_RATELIMIT_IPA(condition) ((void)0) +#endif + +/* + * Printing one error message in 5 seconds if multiple error messages + * are coming back to back. + */ + +#define pr_err_ratelimited_ipa(fmt, args...) \ +({ \ + static DEFINE_RATELIMIT_STATE(_rs, \ + DEFAULT_RATELIMIT_INTERVAL, \ + IPA_RATELIMIT_BURST); \ + \ + if (__ratelimit(&_rs)) \ + pr_err(fmt, ## args); \ +}) + +#define ipa_assert_on(condition)\ +do {\ + if (unlikely(condition))\ + ipa_assert();\ +} while (0) + +#define IPA_CLIENT_IS_PROD(x) \ + (x < IPA_CLIENT_MAX && (x & 0x1) == 0) +#define IPA_CLIENT_IS_CONS(x) \ + (x < IPA_CLIENT_MAX && (x & 0x1) == 1) +/* + * The following macro does two things: + * 1) It checks to see if client x is allocated, and + * 2) It assigns a value to index idx + */ +#define IPA_CLIENT_IS_MAPPED(x, idx) \ + ((idx = ipa_get_ep_mapping(x)) != IPA_EP_NOT_ALLOCATED) +/* + * Same behavior as the macro above; but in addition, determines if + * the client is valid as well. + */ +#define IPA_CLIENT_IS_MAPPED_VALID(x, idx) \ + (IPA_CLIENT_IS_MAPPED(x, idx) && ipa3_ctx->ep[idx].valid == 1) +#define IPA_CLIENT_IS_ETH_PROD(x) \ + ((x == ipa_get_ep_mapping(IPA_CLIENT_ETHERNET_PROD)) || \ + (x == ipa_get_ep_mapping(IPA_CLIENT_ETHERNET2_PROD)) || \ + (x == ipa_get_ep_mapping(IPA_CLIENT_AQC_ETHERNET_PROD)) || \ + (x == ipa_get_ep_mapping(IPA_CLIENT_RTK_ETHERNET_PROD))) + +#define IPA_GSI_CHANNEL_STOP_SLEEP_MIN_USEC (1000) +#define IPA_GSI_CHANNEL_STOP_SLEEP_MAX_USEC (2000) + +#define STR_ETH_IFACE "eth" +#define STR_ETH0_IFACE "eth0" +#define STR_ETH1_IFACE "eth1" +#define STR_RNDIS_IFACE "rndis" +#define STR_ECM_IFACE "ecm" + +#define MINIDUMP_MASK 0x10000 +/** + * qmap_hdr - + * @next_hdr: 1 - there is a qmap extension header, 0 - opposite + * @cd: 0 - data, 1 - command + * @packet_len: length excluding qmap header + * @ext_next_hdr: always zero + * @hdr_type: type of extension header + * @additional_hdr_size: distance between end of qmap header to start of ip + * header + * @zero_checksum: 0 - compute checksum, 1 - zero checksum + * @ip_id_cfg: 0 - running ip id per segment, 1 - constant ip id + * @segment_size: maximum segment size for the segmentation operation + */ +struct qmap_hdr { + u16 pad: 6; + u16 next_hdr: 1; + u16 cd: 1; + u16 mux_id: 8; + u16 packet_len_with_pad: 16; + u16 ext_next_hdr: 1; + u16 hdr_type: 7; + u16 additional_hdr_size: 5; + u16 reserved: 1; + u16 zero_checksum: 1; + u16 ip_id_cfg: 1; + u16 segment_size: 16; +} __packed; + +/** + * struct ipa_pkt_init_ex_hdr_ofst_set - header entry lookup parameters, if + * lookup was successful than the ep's pkt_init_ex offset will be set. + * @name: name of the header resource + * @ep: [out] - the endpoint number to set the IC header offset + */ +struct ipa_pkt_init_ex_hdr_ofst_set { + char name[IPA_RESOURCE_NAME_MAX]; + enum ipa_client_type ep; +}; + +enum ipa_active_client_log_type { + EP, + SIMPLE, + RESOURCE, + SPECIAL, + INVALID +}; + +struct ipa_active_client_logging_info { + const char *id_string; + char *file; + int line; + enum ipa_active_client_log_type type; +}; + +/** + * struct ipa_mem_buffer - IPA memory buffer + * @base: base + * @phys_base: physical base address + * @size: size of memory buffer + */ +struct ipa_mem_buffer { + void *base; + dma_addr_t phys_base; + u32 size; +}; + +/** + * enum ipa3_mhi_burst_mode - MHI channel burst mode state + * + * Values are according to MHI specification + * @IPA_MHI_BURST_MODE_DEFAULT: burst mode enabled for HW channels, + * disabled for SW channels + * @IPA_MHI_BURST_MODE_RESERVED: + * @IPA_MHI_BURST_MODE_DISABLE: Burst mode is disabled for this channel + * @IPA_MHI_BURST_MODE_ENABLE: Burst mode is enabled for this channel + * + */ +enum ipa3_mhi_burst_mode { + IPA_MHI_BURST_MODE_DEFAULT, + IPA_MHI_BURST_MODE_RESERVED, + IPA_MHI_BURST_MODE_DISABLE, + IPA_MHI_BURST_MODE_ENABLE, +}; + +/** + * enum ipa_hw_mhi_channel_states - MHI channel state machine + * + * Values are according to MHI specification + * @IPA_HW_MHI_CHANNEL_STATE_DISABLE: Channel is disabled and not processed by + * the host or device. + * @IPA_HW_MHI_CHANNEL_STATE_ENABLE: A channel is enabled after being + * initialized and configured by host, including its channel context and + * associated transfer ring. While this state, the channel is not active + * and the device does not process transfer. + * @IPA_HW_MHI_CHANNEL_STATE_RUN: The device processes transfers and doorbell + * for channels. + * @IPA_HW_MHI_CHANNEL_STATE_SUSPEND: Used to halt operations on the channel. + * The device does not process transfers for the channel in this state. + * This state is typically used to synchronize the transition to low power + * modes. + * @IPA_HW_MHI_CHANNEL_STATE_STOP: Used to halt operations on the channel. + * The device does not process transfers for the channel in this state. + * @IPA_HW_MHI_CHANNEL_STATE_ERROR: The device detected an error in an element + * from the transfer ring associated with the channel. + * @IPA_HW_MHI_CHANNEL_STATE_INVALID: Invalid state. Shall not be in use in + * operational scenario. + */ +enum ipa_hw_mhi_channel_states { + IPA_HW_MHI_CHANNEL_STATE_DISABLE = 0, + IPA_HW_MHI_CHANNEL_STATE_ENABLE = 1, + IPA_HW_MHI_CHANNEL_STATE_RUN = 2, + IPA_HW_MHI_CHANNEL_STATE_SUSPEND = 3, + IPA_HW_MHI_CHANNEL_STATE_STOP = 4, + IPA_HW_MHI_CHANNEL_STATE_ERROR = 5, + IPA_HW_MHI_CHANNEL_STATE_INVALID = 0xFF +}; + +enum ipa_mhi_state { + IPA_MHI_STATE_INITIALIZED, + IPA_MHI_STATE_READY, + IPA_MHI_STATE_STARTED, + IPA_MHI_STATE_SUSPEND_IN_PROGRESS, + IPA_MHI_STATE_SUSPENDED, + IPA_MHI_STATE_RESUME_IN_PROGRESS, + IPA_MHI_STATE_MAX +}; + +/** + * Structure holding the parameters for IPA_CPU_2_HW_CMD_MHI_DL_UL_SYNC_INFO + * command. Parameters are sent as 32b immediate parameters. + * @isDlUlSyncEnabled: Flag to indicate if DL UL Syncronization is enabled + * @UlAccmVal: UL Timer Accumulation value (Period after which device will poll + * for UL data) + * @ulMsiEventThreshold: Threshold at which HW fires MSI to host for UL events + * @dlMsiEventThreshold: Threshold at which HW fires MSI to host for DL events + */ +union IpaHwMhiDlUlSyncCmdData_t { + struct IpaHwMhiDlUlSyncCmdParams_t { + u32 isDlUlSyncEnabled:8; + u32 UlAccmVal:8; + u32 ulMsiEventThreshold:8; + u32 dlMsiEventThreshold:8; + } params; + u32 raw32b; +}; + +struct ipa_mhi_ch_ctx { + u8 chstate;/*0-7*/ + u8 brstmode:2;/*8-9*/ + u8 pollcfg:6;/*10-15*/ + u16 rsvd;/*16-31*/ + u32 chtype; + u32 erindex; + u64 rbase; + u64 rlen; + u64 rp; + u64 wp; +} __packed; + +struct ipa_mhi_ev_ctx { + u32 intmodc:16; + u32 intmodt:16; + u32 ertype; + u32 msivec; + u64 rbase; + u64 rlen; + u64 rp; + u64 wp; +} __packed; + +struct ipa_mhi_init_uc_engine { + struct ipa_mhi_msi_info *msi; + u32 mmio_addr; + u32 host_ctrl_addr; + u32 host_data_addr; + u32 first_ch_idx; + u32 first_er_idx; + union IpaHwMhiDlUlSyncCmdData_t *ipa_cached_dl_ul_sync_info; +}; + +struct ipa_mhi_init_gsi_engine { + u32 first_ch_idx; +}; + +struct ipa_mhi_init_engine { + struct ipa_mhi_init_uc_engine uC; + struct ipa_mhi_init_gsi_engine gsi; +}; + +struct start_gsi_channel { + enum ipa_hw_mhi_channel_states state; + struct ipa_mhi_msi_info *msi; + struct ipa_mhi_ev_ctx *ev_ctx_host; + u64 event_context_addr; + struct ipa_mhi_ch_ctx *ch_ctx_host; + u64 channel_context_addr; + void (*ch_err_cb)(struct gsi_chan_err_notify *notify); + void (*ev_err_cb)(struct gsi_evt_err_notify *notify); + void *channel; + bool assert_bit40; + struct gsi_mhi_channel_scratch *mhi; + unsigned long *cached_gsi_evt_ring_hdl; + uint8_t evchid; +}; + +struct start_uc_channel { + enum ipa_hw_mhi_channel_states state; + u8 index; + u8 id; +}; + +struct start_mhi_channel { + struct start_uc_channel uC; + struct start_gsi_channel gsi; +}; + +struct ipa_mhi_connect_params_internal { + struct ipa_sys_connect_params *sys; + u8 channel_id; + struct start_mhi_channel start; +}; + +/** + * struct ipa_hdr_offset_entry - IPA header offset entry + * @link: entry's link in global header offset entries list + * @offset: the offset + * @bin: bin + * @ipacm_installed: indicate if installed by ipacm + */ +struct ipa_hdr_offset_entry { + struct list_head link; + u32 offset; + u32 bin; + bool ipacm_installed; +}; + +/** + * enum teth_tethering_mode - Tethering mode (Rmnet / MBIM) + */ +enum teth_tethering_mode { + TETH_TETHERING_MODE_RMNET, + TETH_TETHERING_MODE_MBIM, + TETH_TETHERING_MODE_RMNET_2, + TETH_TETHERING_MODE_MAX, +}; + +/** + * teth_bridge_init_params - Parameters used for in/out USB API + * @usb_notify_cb: Callback function which should be used by the caller. + * Output parameter. + * @private_data: Data for the callback function. Should be used by the + * caller. Output parameter. + * @skip_ep_cfg: boolean field that determines if Apps-processor + * should or should not confiugre this end-point. + */ +struct teth_bridge_init_params { + ipa_notify_cb usb_notify_cb; + void *private_data; + enum ipa_client_type client; + bool skip_ep_cfg; +}; + +/** + * struct teth_bridge_connect_params - Parameters used in teth_bridge_connect() + * @ipa_usb_pipe_hdl: IPA to USB pipe handle, returned from ipa_connect() + * @usb_ipa_pipe_hdl: USB to IPA pipe handle, returned from ipa_connect() + * @tethering_mode: Rmnet or MBIM + * @ipa_client_type: IPA "client" name (IPA_CLIENT_USB#_PROD) + */ +struct teth_bridge_connect_params { + u32 ipa_usb_pipe_hdl; + u32 usb_ipa_pipe_hdl; + enum teth_tethering_mode tethering_mode; + enum ipa_client_type client_type; +}; + +/** + * struct IpaOffloadStatschannel_info - channel info for uC + * stats + * @dir: Direction of the channel ID DIR_CONSUMER =0, + * DIR_PRODUCER = 1 + * @ch_id: GSI ch_id of the IPA endpoint for which stats need + * to be calculated, 0xFF means invalid channel or disable stats + * on already stats enabled channel + */ +struct IpaOffloadStatschannel_info { + u8 dir; + u8 ch_id; +} __packed; + +/** + * struct IpaHwOffloadStatsAllocCmdData_t - protocol info for uC + * stats start + * @protocol: Enum that indicates the protocol type + * @ch_id_info: GSI ch_id and dir of the IPA endpoint for which stats + * need to be calculated + */ +struct IpaHwOffloadStatsAllocCmdData_t { + u32 protocol; + struct IpaOffloadStatschannel_info + ch_id_info[IPA_MAX_CH_STATS_SUPPORTED]; +} __packed; + +/** + * struct ipa_uc_dbg_ring_stats - uC dbg stats info for each + * offloading protocol + * @ring: ring stats for each channel + * @ch_num: number of ch supported for given protocol + */ +struct ipa_uc_dbg_ring_stats { + union { + struct IpaHwRingStats_t ring[IPA_MAX_CH_STATS_SUPPORTED]; + struct ipa_uc_dbg_rtk_ring_stats + rtk[IPA_MAX_CH_STATS_SUPPORTED]; + } u; + u8 num_ch; +}; + +/** + * struct ipa_tz_unlock_reg_info - Used in order unlock regions of memory by TZ + * @reg_addr - Physical address of the start of the region + * @size - Size of the region in bytes + */ +struct ipa_tz_unlock_reg_info { + u64 reg_addr; + u64 size; +}; + +/** + * struct ipa_tx_suspend_irq_data - interrupt data for IPA_TX_SUSPEND_IRQ + * @endpoints: bitmask of endpoints which case IPA_TX_SUSPEND_IRQ interrupt + * @dma_addr: DMA address of this Rx packet + */ +struct ipa_tx_suspend_irq_data { + u32 endpoints[IPA_EP_ARR_SIZE]; +}; + +/** + * struct ipa_rtp_header_add_procparams + * @input_ip_version: Specifies if Input header is IPV4(0) or IPV6(1) + * @reserved: for future use + */ + +struct ipa_rtp_header_add_procparams { + uint32_t input_ip_version:1; + uint32_t reserved:31; +}; + +struct ipa_rtp_hdr_proc_ctx_params { + struct ipa_rtp_header_add_procparams hdr_add_param; +}; + +extern const char *ipa_clients_strings[]; + +#define IPA_IPC_LOGGING(buf, fmt, args...) \ + do { \ + if (buf) \ + ipc_log_string((buf), fmt, __func__, __LINE__, \ + ## args); \ + } while (0) + +void ipa3_inc_client_enable_clks(struct ipa_active_client_logging_info *id); +void ipa3_dec_client_disable_clks(struct ipa_active_client_logging_info *id); +int ipa3_inc_client_enable_clks_no_block( + struct ipa_active_client_logging_info *id); +int ipa3_suspend_resource_no_block(enum ipa_rm_resource_name resource); +int ipa3_resume_resource(enum ipa_rm_resource_name name); +int ipa3_suspend_resource_sync(enum ipa_rm_resource_name resource); +int ipa3_set_required_perf_profile(enum ipa_voltage_level floor_voltage, + u32 bandwidth_mbps); +void *ipa3_get_ipc_logbuf(void); +void *ipa3_get_ipc_logbuf_low(void); +void ipa_assert(void); + +/* MHI */ +int ipa3_mhi_init_engine(struct ipa_mhi_init_engine *params); +int ipa3_connect_mhi_pipe(struct ipa_mhi_connect_params_internal *in, + u32 *clnt_hdl); +int ipa3_disconnect_mhi_pipe(u32 clnt_hdl); +bool ipa3_mhi_stop_gsi_channel(enum ipa_client_type client); +int ipa3_qmi_enable_force_clear_datapath_send( + struct ipa_enable_force_clear_datapath_req_msg_v01 *req); +int ipa3_qmi_disable_force_clear_datapath_send( + struct ipa_disable_force_clear_datapath_req_msg_v01 *req); +int ipa3_generate_tag_process(void); +int ipa3_disable_sps_pipe(enum ipa_client_type client); +int ipa3_mhi_reset_channel_internal(enum ipa_client_type client); +int ipa3_mhi_start_channel_internal(enum ipa_client_type client); +bool ipa3_mhi_sps_channel_empty(enum ipa_client_type client); +int ipa3_mhi_resume_channels_internal(enum ipa_client_type client, + bool LPTransitionRejected, bool brstmode_enabled, + union __packed gsi_channel_scratch ch_scratch, u8 index, + bool is_switch_to_dbmode); +int ipa3_mhi_query_ch_info(enum ipa_client_type client, + struct gsi_chan_info *ch_info); +int ipa3_mhi_destroy_channel(enum ipa_client_type client); +int ipa_mhi_is_using_dma(bool *flag); + +/* MHI uC */ +int ipa3_uc_mhi_send_dl_ul_sync_info(union IpaHwMhiDlUlSyncCmdData_t *cmd); +int ipa3_uc_mhi_init + (void (*ready_cb)(void), void (*wakeup_request_cb)(void)); +void ipa3_uc_mhi_cleanup(void); +int ipa3_uc_mhi_reset_channel(int channelHandle); +int ipa3_uc_mhi_suspend_channel(int channelHandle); +int ipa3_uc_mhi_stop_event_update_channel(int channelHandle); +int ipa3_uc_mhi_print_stats(char *dbg_buff, int size); + +/* uC */ +int ipa3_uc_state_check(void); + +/* general */ +void ipa3_get_holb(int ep_idx, struct ipa_ep_cfg_holb *holb); +void ipa3_set_tag_process_before_gating(bool val); +bool ipa3_has_open_aggr_frame(enum ipa_client_type client); +int ipa3_setup_uc_ntn_pipes(struct ipa_ntn_conn_in_params *in, + ipa_notify_cb notify, void *priv, u8 hdr_len, + struct ipa_ntn_conn_out_params *outp); + +int ipa3_tear_down_uc_offload_pipes(int ipa_ep_idx_ul, int ipa_ep_idx_dl, + struct ipa_ntn_conn_in_params *params); +u8 *ipa_write_64(u64 w, u8 *dest); +u8 *ipa_write_32(u32 w, u8 *dest); +u8 *ipa_write_16(u16 hw, u8 *dest); +u8 *ipa_write_8(u8 b, u8 *dest); +u8 *ipa_pad_to_64(u8 *dest); +u8 *ipa_pad_to_32(u8 *dest); +int ipa3_ntn_uc_reg_rdyCB(void (*ipauc_ready_cb)(void *user_data), + void *user_data); +void ipa3_ntn_uc_dereg_rdyCB(void); + +int ipa3_conn_wdi3_pipes(struct ipa_wdi_conn_in_params *in, + struct ipa_wdi_conn_out_params *out, + ipa_wdi_meter_notifier_cb wdi_notify); + +int ipa3_disconn_wdi3_pipes(int ipa_ep_idx_tx, int ipa_ep_idx_rx, + int ipa_ep_idx_tx1); + +int ipa3_enable_wdi3_pipes(int ipa_ep_idx_tx, int ipa_ep_idx_rx, + int ipa_ep_idx_tx1); + +int ipa3_disable_wdi3_pipes(int ipa_ep_idx_tx, int ipa_ep_idx_rx, + int ipa_ep_idx_tx1); + +int ipa3_enable_wdi3_opt_dpath(int ipa_ep_idx_rx, int ipa_ep_idx_tx, + u32 rt_tbl_idx); +int ipa3_disable_wdi3_opt_dpath(int ipa_ep_idx_rx, int ipa_ep_idx_tx); + +const char *ipa_get_version_string(enum ipa_hw_type ver); +int ipa3_start_gsi_channel(u32 clnt_hdl); + +int ipa_smmu_store_sgt(struct sg_table **out_ch_ptr, + struct sg_table *in_sgt_ptr); +int ipa_smmu_free_sgt(struct sg_table **out_sgt_ptr); + +#ifdef CONFIG_IPA_UT +int ipa_ut_module_init(void); +void ipa_ut_module_exit(void); +#else +static inline int ipa_ut_module_init(void) +{ + return -EPERM; +} +static inline void ipa_ut_module_exit(void) +{ +} +#endif + +int ipa3_wigig_internal_init( + struct ipa_wdi_uc_ready_params *inout, + ipa_wigig_misc_int_cb int_notify, + phys_addr_t *uc_db_pa); + +int ipa3_conn_wigig_rx_pipe_i(void *in, struct ipa_wigig_conn_out_params *out, + struct dentry **parent); + +int ipa3_conn_wigig_client_i(void *in, struct ipa_wigig_conn_out_params *out, + ipa_notify_cb tx_notify, + void *priv); + +int ipa3_wigig_uc_msi_init( + bool init, + phys_addr_t periph_baddr_pa, + phys_addr_t pseudo_cause_pa, + phys_addr_t int_gen_tx_pa, + phys_addr_t int_gen_rx_pa, + phys_addr_t dma_ep_misc_pa); + +int ipa3_disconn_wigig_pipe_i(enum ipa_client_type client, + struct ipa_wigig_pipe_setup_info_smmu *pipe_smmu, + void *dbuff); + +int ipa3_enable_wigig_pipe_i(enum ipa_client_type client); + +int ipa3_disable_wigig_pipe_i(enum ipa_client_type client); + +int ipa_wigig_send_msg(int msg_type, + const char *netdev_name, u8 *mac, + enum ipa_client_type client, bool to_wigig); + +int ipa_wigig_send_wlan_msg(enum ipa_wlan_event msg_type, + const char *netdev_name, u8 *mac); + +void ipa3_register_client_callback(int (*client_cb)(bool is_lock), + bool (*teth_port_state)(void), u32 ipa_ep_idx); + +void ipa3_deregister_client_callback(u32 ipa_ep_idx); + +/* +* Configuration +*/ +int ipa3_cfg_ep(u32 clnt_hdl, const struct ipa_ep_cfg *ipa_ep_cfg); + +int ipa3_cfg_ep_nat(u32 clnt_hdl, const struct ipa_ep_cfg_nat *ipa_ep_cfg); + +int ipa3_cfg_ep_conn_track(u32 clnt_hdl, + const struct ipa_ep_cfg_conn_track *ep_conn_track); + +int ipa_cfg_ep_hdr(u32 clnt_hdl, const struct ipa_ep_cfg_hdr *ipa_ep_cfg); + +int ipa_cfg_ep_hdr_ext(u32 clnt_hdl, + const struct ipa_ep_cfg_hdr_ext *ipa_ep_cfg); + +int ipa_cfg_ep_mode(u32 clnt_hdl, const struct ipa_ep_cfg_mode *ipa_ep_cfg); + +int ipa_cfg_ep_aggr(u32 clnt_hdl, const struct ipa_ep_cfg_aggr *ipa_ep_cfg); + +int ipa_cfg_ep_deaggr(u32 clnt_hdl, + const struct ipa_ep_cfg_deaggr *ipa_ep_cfg); + +int ipa_cfg_ep_route(u32 clnt_hdl, const struct ipa_ep_cfg_route *ipa_ep_cfg); + +int ipa_cfg_ep_holb(u32 clnt_hdl, const struct ipa_ep_cfg_holb *ipa_ep_cfg); + +int ipa_cfg_ep_cfg(u32 clnt_hdl, const struct ipa_ep_cfg_cfg *ipa_ep_cfg); + +int ipa_cfg_ep_metadata_mask(u32 clnt_hdl, const struct ipa_ep_cfg_metadata_mask + *ipa_ep_cfg); + +int ipa_cfg_ep_holb_by_client(enum ipa_client_type client, + const struct ipa_ep_cfg_holb *ipa_ep_cfg); + +/* +* Header removal / addition +*/ +int ipa3_add_hdr_hpc(struct ipa_ioc_add_hdr *hdrs); + +int ipa3_add_hdr_hpc_usr(struct ipa_ioc_add_hdr *hdrs, bool user_only); + +int ipa3_del_hdr_hpc(struct ipa_ioc_del_hdr *hdrs); + +int ipa3_add_hdr_usr(struct ipa_ioc_add_hdr *hdrs, bool user_only); + +int ipa3_reset_hdr(bool user_only); + +/* +* Header Processing Context +*/ +int ipa3_add_hdr_proc_ctx(struct ipa_ioc_add_hdr_proc_ctx *proc_ctxs, + bool user_only); + +int ipa3_add_rtp_hdr_proc_ctx(struct ipa_ioc_add_hdr_proc_ctx *proc_ctxs, + struct ipa_rtp_hdr_proc_ctx_params rtp_params, bool user_only); + +int ipa3_del_hdr_proc_ctx(struct ipa_ioc_del_hdr_proc_ctx *hdls); + +/* +* Routing +*/ + +int ipa3_add_rt_rule_v2(struct ipa_ioc_add_rt_rule_v2 *rules); + +int ipa3_add_rt_rule_usr(struct ipa_ioc_add_rt_rule *rules, bool user_only); + +int ipa3_add_rt_rule_usr_v2(struct ipa_ioc_add_rt_rule_v2 *rules, + bool user_only); + +int ipa3_del_rt_rule(struct ipa_ioc_del_rt_rule *hdls); + +int ipa3_commit_rt(enum ipa_ip_type ip); + +int ipa3_reset_rt(enum ipa_ip_type ip, bool user_only); + +/* +* Filtering +*/ + +int ipa3_del_flt_rule(struct ipa_ioc_del_flt_rule *hdls); + +int ipa3_mdfy_flt_rule(struct ipa_ioc_mdfy_flt_rule *rules); + +int ipa3_mdfy_flt_rule_v2(struct ipa_ioc_mdfy_flt_rule_v2 *rules); + +int ipa3_reset_flt(enum ipa_ip_type ip, bool user_only); + +/* +* NAT\IPv6CT +*/ +int ipa3_allocate_nat_device(struct ipa_ioc_nat_alloc_mem *mem); +int ipa3_allocate_nat_table(struct ipa_ioc_nat_ipv6ct_table_alloc *table_alloc); +int ipa3_allocate_ipv6ct_table( + struct ipa_ioc_nat_ipv6ct_table_alloc *table_alloc); + +int ipa3_nat_init_cmd(struct ipa_ioc_v4_nat_init *init); +int ipa3_ipv6ct_init_cmd(struct ipa_ioc_ipv6ct_init *init); + +int ipa3_nat_dma_cmd(struct ipa_ioc_nat_dma_cmd *dma); +int ipa3_table_dma_cmd(struct ipa_ioc_nat_dma_cmd *dma); + +int ipa3_nat_del_cmd(struct ipa_ioc_v4_nat_del *del); +int ipa3_del_nat_table(struct ipa_ioc_nat_ipv6ct_table_del *del); +int ipa3_del_ipv6ct_table(struct ipa_ioc_nat_ipv6ct_table_del *del); + +int ipa3_nat_mdfy_pdn(struct ipa_ioc_nat_pdn_entry *mdfy_pdn); + +/* +* Data path +*/ +int ipa3_rx_poll(u32 clnt_hdl, int budget); +void ipa3_recycle_wan_skb(struct sk_buff *skb); + +/* + * Low lat data path + */ +int ipa3_low_lat_rx_poll(u32 clnt_hdl, int budget); + +/* +* System pipes +*/ +int ipa3_set_wlan_tx_info(struct ipa_wdi_tx_info *info); + +/* +* Tethering bridge (Rmnet / MBIM) +*/ +int ipa3_teth_bridge_init(struct teth_bridge_init_params *params); + +int ipa3_teth_bridge_disconnect(enum ipa_client_type client); + +int ipa3_teth_bridge_connect(struct teth_bridge_connect_params *connect_params); + +/* +* Tethering client info +*/ +void ipa3_set_client(int index, enum ipacm_client_enum client, bool uplink); + +enum ipacm_client_enum ipa3_get_client(int pipe_idx); + +bool ipa3_get_client_uplink(int pipe_idx); + +/* +* mux id +*/ +int ipa3_write_qmap_id(struct ipa_ioc_write_qmapid *param_in); + +/* +* interrupts +*/ + +int ipa3_remove_interrupt_handler(enum ipa_irq_type interrupt); + +/* +* Interface +*/ +int ipa3_register_intf_ext(const char *name, const struct ipa_tx_intf *tx, + const struct ipa_rx_intf *rx, + const struct ipa_ext_intf *ext); + +/* +* Miscellaneous +*/ + +int ipa3_uc_debug_stats_alloc( + struct IpaHwOffloadStatsAllocCmdData_t cmdinfo); +int ipa3_uc_debug_stats_dealloc(uint32_t protocol); +void ipa3_get_gsi_stats(int prot_id, + struct ipa_uc_dbg_ring_stats *stats); +int ipa3_get_prot_id(enum ipa_client_type client); + +/** +* ipa_tz_unlock_reg - Unlocks memory regions so that they become accessible +* from AP. +* @reg_info - Pointer to array of memory regions to unlock +* @num_regs - Number of elements in the array +* +* Converts the input array of regions to a struct that TZ understands and +* issues an SCM call. +* Also flushes the memory cache to DDR in order to make sure that TZ sees the +* correct data structure. +* +* Returns: 0 on success, negative on failure +*/ +int ipa3_tz_unlock_reg(struct ipa_tz_unlock_reg_info *reg_info, u16 num_regs); + +int ipa_eth_rtk_connect( + struct ipa_eth_client_pipe_info *pipe, + enum ipa_client_type client_type); + +int ipa_eth_aqc_connect( + struct ipa_eth_client_pipe_info *pipe, + enum ipa_client_type client_type); + +int ipa_eth_emac_connect( + struct ipa_eth_client_pipe_info *pipe, + enum ipa_client_type client_type); + +int ipa_eth_rtk_disconnect( + struct ipa_eth_client_pipe_info *pipe, + enum ipa_client_type client_type); + +int ipa_eth_aqc_disconnect( + struct ipa_eth_client_pipe_info *pipe, + enum ipa_client_type client_type); + +int ipa_eth_emac_disconnect( + struct ipa_eth_client_pipe_info *pipe, + enum ipa_client_type client_type); + +#if IPA_ETH_API_VER < 2 +int ipa_eth_client_conn_evt(struct ipa_ecm_msg *msg); + +int ipa_eth_client_disconn_evt(struct ipa_ecm_msg *msg); + +#endif + +/* ULSO mode Query */ +bool ipa3_is_ulso_supported(void); + +/* IPA_PACKET_INIT_EX IC to pipe API */ +int ipa_set_pkt_init_ex_hdr_ofst( + struct ipa_pkt_init_ex_hdr_ofst_set *lookup, bool proc_ctx); + +/* IPA stats pm functions */ +int ipa_pm_get_scaling_bw_levels(struct ipa_lnx_clock_stats *clock_stats); +int ipa_pm_get_aggregated_throughput(void); +int ipa_pm_get_current_clk_vote(void); +bool ipa_get_pm_client_stats_filled(struct pm_client_stats *pm_stats_ptr, + int pm_client_index); +int ipa_pm_get_pm_clnt_throughput(enum ipa_client_type client_type); + +struct sk_buff* qmap_encapsulate_skb(struct sk_buff *skb, const struct qmap_hdr *qh); + +int ipa_hdrs_hpc_destroy(u32 hdr_hdl); + +#endif /* _IPA_COMMON_I_H_ */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_rm.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_rm.c new file mode 100644 index 0000000000..7956cb0dd4 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_rm.c @@ -0,0 +1,757 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2013-2019, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include "ipa.h" +#include "ipa_rm_dependency_graph.h" +#include "ipa_rm_i.h" +#include "ipa_common_i.h" + +static const char *resource_name_to_str[IPA_RM_RESOURCE_MAX] = { + __stringify(IPA_RM_RESOURCE_Q6_PROD), + __stringify(IPA_RM_RESOURCE_Q6_CONS), + __stringify(IPA_RM_RESOURCE_USB_PROD), + __stringify(IPA_RM_RESOURCE_USB_CONS), + __stringify(IPA_RM_RESOURCE_USB_DPL_DUMMY_PROD), + __stringify(IPA_RM_RESOURCE_USB_DPL_CONS), + __stringify(IPA_RM_RESOURCE_HSIC_PROD), + __stringify(IPA_RM_RESOURCE_HSIC_CONS), + __stringify(IPA_RM_RESOURCE_STD_ECM_PROD), + __stringify(IPA_RM_RESOURCE_APPS_CONS), + __stringify(IPA_RM_RESOURCE_RNDIS_PROD), + __stringify(RESERVED_CONS_11), + __stringify(IPA_RM_RESOURCE_WWAN_0_PROD), + __stringify(RESERVED_CONS_13), + __stringify(IPA_RM_RESOURCE_WLAN_PROD), + __stringify(IPA_RM_RESOURCE_WLAN_CONS), + __stringify(IPA_RM_RESOURCE_ODU_ADAPT_PROD), + __stringify(IPA_RM_RESOURCE_ODU_ADAPT_CONS), + __stringify(IPA_RM_RESOURCE_MHI_PROD), + __stringify(IPA_RM_RESOURCE_MHI_CONS), + __stringify(IPA_RM_RESOURCE_ETHERNET_PROD), + __stringify(IPA_RM_RESOURCE_ETHERNET_CONS), +}; + +struct ipa_rm_profile_vote_type { + enum ipa_voltage_level volt[IPA_RM_RESOURCE_MAX]; + enum ipa_voltage_level curr_volt; + u32 bw_resources[IPA_RM_RESOURCE_MAX]; + u32 curr_bw; +}; + +struct ipa_rm_context_type { + struct ipa_rm_dep_graph *dep_graph; + struct workqueue_struct *ipa_rm_wq; + spinlock_t ipa_rm_lock; + struct ipa_rm_profile_vote_type prof_vote; +}; +static struct ipa_rm_context_type *ipa_rm_ctx; + +struct ipa_rm_notify_ipa_work_type { + struct work_struct work; + enum ipa_voltage_level volt; + u32 bandwidth_mbps; +}; + +static int _ipa_rm_add_dependency(enum ipa_rm_resource_name resource_name, + enum ipa_rm_resource_name depends_on_name, + bool userspace_dep) +{ + unsigned long flags; + int result; + + if (unlikely(!ipa_rm_ctx)) { + IPA_RM_ERR("IPA RM was not initialized\n"); + return -EINVAL; + } + + IPA_RM_DBG("%s -> %s\n", ipa_rm_resource_str(resource_name), + ipa_rm_resource_str(depends_on_name)); + spin_lock_irqsave(&ipa_rm_ctx->ipa_rm_lock, flags); + result = ipa_rm_dep_graph_add_dependency( + ipa_rm_ctx->dep_graph, + resource_name, + depends_on_name, + userspace_dep); + spin_unlock_irqrestore(&ipa_rm_ctx->ipa_rm_lock, flags); + IPA_RM_DBG("EXIT with %d\n", result); + + return result; +} + +/** + * ipa_rm_add_dependency_from_ioctl() - create dependency between 2 resources + * @resource_name: name of dependent resource + * @depends_on_name: name of its dependency + * + * This function is expected to be called from IOCTL and the dependency will be + * marked as is was added by the userspace. + * + * Returns: 0 on success, negative on failure + * + * Side effects: IPA_RM_RESORCE_GRANTED could be generated + * in case client registered with IPA RM + */ +int ipa_rm_add_dependency_from_ioctl(enum ipa_rm_resource_name resource_name, + enum ipa_rm_resource_name depends_on_name) +{ + return _ipa_rm_add_dependency(resource_name, depends_on_name, true); +} + +static int _ipa_rm_add_dependency_sync(enum ipa_rm_resource_name resource_name, + enum ipa_rm_resource_name depends_on_name, + bool userspsace_dep) +{ + int result; + struct ipa_rm_resource *consumer; + unsigned long time; + unsigned long flags; + + if (unlikely(!ipa_rm_ctx)) { + IPA_RM_ERR("IPA RM was not initialized\n"); + return -EINVAL; + } + + IPA_RM_DBG("%s -> %s\n", ipa_rm_resource_str(resource_name), + ipa_rm_resource_str(depends_on_name)); + spin_lock_irqsave(&ipa_rm_ctx->ipa_rm_lock, flags); + result = ipa_rm_dep_graph_add_dependency( + ipa_rm_ctx->dep_graph, + resource_name, + depends_on_name, + userspsace_dep); + spin_unlock_irqrestore(&ipa_rm_ctx->ipa_rm_lock, flags); + if (result == -EINPROGRESS) { + ipa_rm_dep_graph_get_resource(ipa_rm_ctx->dep_graph, + depends_on_name, + &consumer); + IPA_RM_DBG("%s waits for GRANT of %s.\n", + ipa_rm_resource_str(resource_name), + ipa_rm_resource_str(depends_on_name)); + time = wait_for_completion_timeout( + &((struct ipa_rm_resource_cons *)consumer)-> + request_consumer_in_progress, + HZ * 5); + result = 0; + if (!time) { + IPA_RM_ERR("TIMEOUT waiting for %s GRANT event.", + ipa_rm_resource_str(depends_on_name)); + result = -ETIME; + } else { + IPA_RM_DBG("%s waited for %s GRANT %lu time.\n", + ipa_rm_resource_str(resource_name), + ipa_rm_resource_str(depends_on_name), + time); + } + } + IPA_RM_DBG("EXIT with %d\n", result); + + return result; +} + +/** + * ipa_rm_add_dependency_sync_from_ioctl() - Create a dependency between 2 + * resources in a synchronized fashion. In case a producer resource is in + * GRANTED state and the newly added consumer resource is in RELEASED state, + * the consumer entity will be requested and the function will block until + * the consumer is granted. + * @resource_name: name of dependent resource + * @depends_on_name: name of its dependency + * + * Returns: 0 on success, negative on failure + * + * Side effects: May block. See documentation above. + */ +int ipa_rm_add_dependency_sync_from_ioctl( + enum ipa_rm_resource_name resource_name, + enum ipa_rm_resource_name depends_on_name) +{ + return _ipa_rm_add_dependency_sync(resource_name, depends_on_name, + true); +} + +static int _ipa_rm_delete_dependency(enum ipa_rm_resource_name resource_name, + enum ipa_rm_resource_name depends_on_name, + bool userspace_dep) +{ + unsigned long flags; + int result; + + if (unlikely(!ipa_rm_ctx)) { + IPA_RM_ERR("IPA RM was not initialized\n"); + return -EINVAL; + } + + IPA_RM_DBG("%s -> %s\n", ipa_rm_resource_str(resource_name), + ipa_rm_resource_str(depends_on_name)); + spin_lock_irqsave(&ipa_rm_ctx->ipa_rm_lock, flags); + result = ipa_rm_dep_graph_delete_dependency( + ipa_rm_ctx->dep_graph, + resource_name, + depends_on_name, + userspace_dep); + spin_unlock_irqrestore(&ipa_rm_ctx->ipa_rm_lock, flags); + IPA_RM_DBG("EXIT with %d\n", result); + + return result; +} + +/** + * ipa_rm_delete_dependency_fron_ioctl() - delete dependency between 2 resources + * @resource_name: name of dependent resource + * @depends_on_name: name of its dependency + * + * This function is expected to be called from IOCTL and the dependency will be + * marked as is was added by the userspace. + * + * Returns: 0 on success, negative on failure + * + * Side effects: IPA_RM_RESORCE_GRANTED could be generated + * in case client registered with IPA RM + */ +int ipa_rm_delete_dependency_from_ioctl(enum ipa_rm_resource_name resource_name, + enum ipa_rm_resource_name depends_on_name) +{ + return _ipa_rm_delete_dependency(resource_name, depends_on_name, true); +} + +void delayed_release_work_func(struct work_struct *work) +{ + unsigned long flags; + struct ipa_rm_resource *resource; + struct ipa_rm_delayed_release_work_type *rwork = container_of( + to_delayed_work(work), + struct ipa_rm_delayed_release_work_type, + work); + + if (!IPA_RM_RESORCE_IS_CONS(rwork->resource_name)) { + IPA_RM_ERR("can be called on CONS only\n"); + kfree(rwork); + return; + } + spin_lock_irqsave(&ipa_rm_ctx->ipa_rm_lock, flags); + if (ipa_rm_dep_graph_get_resource(ipa_rm_ctx->dep_graph, + rwork->resource_name, + &resource) != 0) { + IPA_RM_ERR("resource does not exists\n"); + goto bail; + } + + ipa_rm_resource_consumer_release( + (struct ipa_rm_resource_cons *)resource, rwork->needed_bw, + rwork->dec_usage_count); + +bail: + spin_unlock_irqrestore(&ipa_rm_ctx->ipa_rm_lock, flags); + kfree(rwork); + +} + +/** + * ipa_rm_request_resource_with_timer() - requests the specified consumer + * resource and releases it after 1 second + * @resource_name: name of the requested resource + * + * Returns: 0 on success, negative on failure + */ +int ipa_rm_request_resource_with_timer(enum ipa_rm_resource_name resource_name) +{ + unsigned long flags; + struct ipa_rm_resource *resource; + struct ipa_rm_delayed_release_work_type *release_work; + int result; + + if (!IPA_RM_RESORCE_IS_CONS(resource_name)) { + IPA_RM_ERR("can be called on CONS only\n"); + return -EINVAL; + } + + spin_lock_irqsave(&ipa_rm_ctx->ipa_rm_lock, flags); + if (ipa_rm_dep_graph_get_resource(ipa_rm_ctx->dep_graph, + resource_name, + &resource) != 0) { + IPA_RM_ERR("resource does not exists\n"); + result = -EPERM; + goto bail; + } + result = ipa_rm_resource_consumer_request( + (struct ipa_rm_resource_cons *)resource, 0, false, true); + if (result != 0 && result != -EINPROGRESS) { + IPA_RM_ERR("consumer request returned error %d\n", result); + result = -EPERM; + goto bail; + } + + release_work = kzalloc(sizeof(*release_work), GFP_ATOMIC); + if (!release_work) { + result = -ENOMEM; + goto bail; + } + release_work->resource_name = resource->name; + release_work->needed_bw = 0; + release_work->dec_usage_count = false; + INIT_DELAYED_WORK(&release_work->work, delayed_release_work_func); + schedule_delayed_work(&release_work->work, + msecs_to_jiffies(IPA_RM_RELEASE_DELAY_IN_MSEC)); + result = 0; +bail: + spin_unlock_irqrestore(&ipa_rm_ctx->ipa_rm_lock, flags); + + return result; +} + +static void ipa_rm_wq_handler(struct work_struct *work) +{ + unsigned long flags; + struct ipa_rm_resource *resource; + struct ipa_rm_wq_work_type *ipa_rm_work = + container_of(work, + struct ipa_rm_wq_work_type, + work); + IPA_RM_DBG_LOW("%s cmd=%d event=%d notify_registered_only=%d\n", + ipa_rm_resource_str(ipa_rm_work->resource_name), + ipa_rm_work->wq_cmd, + ipa_rm_work->event, + ipa_rm_work->notify_registered_only); + switch (ipa_rm_work->wq_cmd) { + case IPA_RM_WQ_NOTIFY_PROD: + if (!IPA_RM_RESORCE_IS_PROD(ipa_rm_work->resource_name)) { + IPA_RM_ERR("resource is not PROD\n"); + goto free_work; + } + spin_lock_irqsave(&ipa_rm_ctx->ipa_rm_lock, flags); + if (ipa_rm_dep_graph_get_resource(ipa_rm_ctx->dep_graph, + ipa_rm_work->resource_name, + &resource) != 0){ + IPA_RM_ERR("resource does not exists\n"); + spin_unlock_irqrestore(&ipa_rm_ctx->ipa_rm_lock, flags); + goto free_work; + } + ipa_rm_resource_producer_notify_clients( + (struct ipa_rm_resource_prod *)resource, + ipa_rm_work->event, + ipa_rm_work->notify_registered_only); + spin_unlock_irqrestore(&ipa_rm_ctx->ipa_rm_lock, flags); + break; + case IPA_RM_WQ_NOTIFY_CONS: + break; + case IPA_RM_WQ_RESOURCE_CB: + spin_lock_irqsave(&ipa_rm_ctx->ipa_rm_lock, flags); + if (ipa_rm_dep_graph_get_resource(ipa_rm_ctx->dep_graph, + ipa_rm_work->resource_name, + &resource) != 0){ + IPA_RM_ERR("resource does not exists\n"); + spin_unlock_irqrestore(&ipa_rm_ctx->ipa_rm_lock, flags); + goto free_work; + } + ipa_rm_resource_consumer_handle_cb( + (struct ipa_rm_resource_cons *)resource, + ipa_rm_work->event); + spin_unlock_irqrestore(&ipa_rm_ctx->ipa_rm_lock, flags); + break; + default: + break; + } + +free_work: + kfree((void *) work); +} + +static void ipa_rm_wq_resume_handler(struct work_struct *work) +{ + unsigned long flags; + struct ipa_rm_resource *resource; + struct ipa_rm_wq_suspend_resume_work_type *ipa_rm_work = + container_of(work, + struct ipa_rm_wq_suspend_resume_work_type, + work); + IPA_RM_DBG_LOW("resume work handler: %s", + ipa_rm_resource_str(ipa_rm_work->resource_name)); + + if (!IPA_RM_RESORCE_IS_CONS(ipa_rm_work->resource_name)) { + IPA_RM_ERR("resource is not CONS\n"); + return; + } + IPA_ACTIVE_CLIENTS_INC_RESOURCE(ipa_rm_resource_str( + ipa_rm_work->resource_name)); + spin_lock_irqsave(&ipa_rm_ctx->ipa_rm_lock, flags); + if (ipa_rm_dep_graph_get_resource(ipa_rm_ctx->dep_graph, + ipa_rm_work->resource_name, + &resource) != 0){ + IPA_RM_ERR("resource does not exists\n"); + spin_unlock_irqrestore(&ipa_rm_ctx->ipa_rm_lock, flags); + IPA_ACTIVE_CLIENTS_DEC_RESOURCE(ipa_rm_resource_str( + ipa_rm_work->resource_name)); + goto bail; + } + ipa_rm_resource_consumer_request_work( + (struct ipa_rm_resource_cons *)resource, + ipa_rm_work->prev_state, ipa_rm_work->needed_bw, true, + ipa_rm_work->inc_usage_count); + spin_unlock_irqrestore(&ipa_rm_ctx->ipa_rm_lock, flags); +bail: + kfree(ipa_rm_work); +} + + +static void ipa_rm_wq_suspend_handler(struct work_struct *work) +{ + unsigned long flags; + struct ipa_rm_resource *resource; + struct ipa_rm_wq_suspend_resume_work_type *ipa_rm_work = + container_of(work, + struct ipa_rm_wq_suspend_resume_work_type, + work); + IPA_RM_DBG_LOW("suspend work handler: %s", + ipa_rm_resource_str(ipa_rm_work->resource_name)); + + if (!IPA_RM_RESORCE_IS_CONS(ipa_rm_work->resource_name)) { + IPA_RM_ERR("resource is not CONS\n"); + return; + } + ipa3_suspend_resource_sync(ipa_rm_work->resource_name); + spin_lock_irqsave(&ipa_rm_ctx->ipa_rm_lock, flags); + if (ipa_rm_dep_graph_get_resource(ipa_rm_ctx->dep_graph, + ipa_rm_work->resource_name, + &resource) != 0){ + IPA_RM_ERR("resource does not exists\n"); + spin_unlock_irqrestore(&ipa_rm_ctx->ipa_rm_lock, flags); + return; + } + ipa_rm_resource_consumer_release_work( + (struct ipa_rm_resource_cons *)resource, + ipa_rm_work->prev_state, + true); + spin_unlock_irqrestore(&ipa_rm_ctx->ipa_rm_lock, flags); + + kfree(ipa_rm_work); +} + +/** + * ipa_rm_wq_send_cmd() - send a command for deferred work + * @wq_cmd: command that should be executed + * @resource_name: resource on which command should be executed + * @notify_registered_only: notify only clients registered by + * ipa_rm_register() + * + * Returns: 0 on success, negative otherwise + */ +int ipa_rm_wq_send_cmd(enum ipa_rm_wq_cmd wq_cmd, + enum ipa_rm_resource_name resource_name, + enum ipa_rm_event event, + bool notify_registered_only) +{ + int result = -ENOMEM; + struct ipa_rm_wq_work_type *work = kzalloc(sizeof(*work), GFP_ATOMIC); + + if (work) { + INIT_WORK((struct work_struct *)work, ipa_rm_wq_handler); + work->wq_cmd = wq_cmd; + work->resource_name = resource_name; + work->event = event; + work->notify_registered_only = notify_registered_only; + result = queue_work(ipa_rm_ctx->ipa_rm_wq, + (struct work_struct *)work); + } + + return result; +} + +int ipa_rm_wq_send_suspend_cmd(enum ipa_rm_resource_name resource_name, + enum ipa_rm_resource_state prev_state, + u32 needed_bw) +{ + int result = -ENOMEM; + struct ipa_rm_wq_suspend_resume_work_type *work = kzalloc(sizeof(*work), + GFP_ATOMIC); + if (work) { + INIT_WORK((struct work_struct *)work, + ipa_rm_wq_suspend_handler); + work->resource_name = resource_name; + work->prev_state = prev_state; + work->needed_bw = needed_bw; + result = queue_work(ipa_rm_ctx->ipa_rm_wq, + (struct work_struct *)work); + } + + return result; +} + +int ipa_rm_wq_send_resume_cmd(enum ipa_rm_resource_name resource_name, + enum ipa_rm_resource_state prev_state, + u32 needed_bw, + bool inc_usage_count) +{ + int result = -ENOMEM; + struct ipa_rm_wq_suspend_resume_work_type *work = kzalloc(sizeof(*work), + GFP_ATOMIC); + if (work) { + INIT_WORK((struct work_struct *)work, ipa_rm_wq_resume_handler); + work->resource_name = resource_name; + work->prev_state = prev_state; + work->needed_bw = needed_bw; + work->inc_usage_count = inc_usage_count; + result = queue_work(ipa_rm_ctx->ipa_rm_wq, + (struct work_struct *)work); + } else { + IPA_RM_ERR("no mem\n"); + } + + return result; +} +/** + * ipa_rm_initialize() - initialize IPA RM component + * + * Returns: 0 on success, negative otherwise + */ +int ipa_rm_initialize(void) +{ + int result; + + ipa_rm_ctx = kzalloc(sizeof(*ipa_rm_ctx), GFP_KERNEL); + if (!ipa_rm_ctx) { + IPA_RM_ERR("no mem\n"); + result = -ENOMEM; + goto bail; + } + ipa_rm_ctx->ipa_rm_wq = create_singlethread_workqueue("ipa_rm_wq"); + if (!ipa_rm_ctx->ipa_rm_wq) { + IPA_RM_ERR("create workqueue failed\n"); + result = -ENOMEM; + goto create_wq_fail; + } + result = ipa_rm_dep_graph_create(&(ipa_rm_ctx->dep_graph)); + if (result) { + IPA_RM_ERR("create dependency graph failed\n"); + goto graph_alloc_fail; + } + spin_lock_init(&ipa_rm_ctx->ipa_rm_lock); + IPA_RM_DBG("SUCCESS\n"); + + return 0; +graph_alloc_fail: + destroy_workqueue(ipa_rm_ctx->ipa_rm_wq); +create_wq_fail: + kfree(ipa_rm_ctx); +bail: + return result; +} + +/** + * ipa_rm_stat() - print RM stat + * @buf: [in] The user buff used to print + * @size: [in] The size of buf + * Returns: number of bytes used on success, negative on failure + * + * This function is called by ipa_debugfs in order to receive + * a full picture of the current state of the RM + */ + +int ipa_rm_stat(char *buf, int size) +{ + unsigned long flags; + int i, cnt = 0, result = EINVAL; + struct ipa_rm_resource *resource = NULL; + u32 sum_bw_prod = 0; + u32 sum_bw_cons = 0; + + if (!buf || size < 0) + return result; + + spin_lock_irqsave(&ipa_rm_ctx->ipa_rm_lock, flags); + for (i = 0; i < IPA_RM_RESOURCE_MAX; ++i) { + if (!IPA_RM_RESORCE_IS_PROD(i)) + continue; + result = ipa_rm_dep_graph_get_resource( + ipa_rm_ctx->dep_graph, + i, + &resource); + if (!result) { + result = ipa_rm_resource_producer_print_stat( + resource, buf + cnt, + size-cnt); + if (result < 0) + goto bail; + cnt += result; + } + } + + for (i = 0; i < IPA_RM_RESOURCE_MAX; i++) { + if (IPA_RM_RESORCE_IS_PROD(i)) + sum_bw_prod += ipa_rm_ctx->prof_vote.bw_resources[i]; + else + sum_bw_cons += ipa_rm_ctx->prof_vote.bw_resources[i]; + } + + result = scnprintf(buf + cnt, size - cnt, + "All prod bandwidth: %d, All cons bandwidth: %d\n", + sum_bw_prod, sum_bw_cons); + cnt += result; + + result = scnprintf(buf + cnt, size - cnt, + "Voting: voltage %d, bandwidth %d\n", + ipa_rm_ctx->prof_vote.curr_volt, + ipa_rm_ctx->prof_vote.curr_bw); + cnt += result; + + result = cnt; +bail: + spin_unlock_irqrestore(&ipa_rm_ctx->ipa_rm_lock, flags); + + return result; +} + +/** + * ipa_rm_resource_str() - returns string that represent the resource + * @resource_name: [in] resource name + */ +const char *ipa_rm_resource_str(enum ipa_rm_resource_name resource_name) +{ + if (resource_name < 0 || resource_name >= IPA_RM_RESOURCE_MAX) + return "INVALID RESOURCE"; + + return resource_name_to_str[resource_name]; +}; + +static void ipa_rm_perf_profile_notify_to_ipa_work(struct work_struct *work) +{ + struct ipa_rm_notify_ipa_work_type *notify_work = container_of(work, + struct ipa_rm_notify_ipa_work_type, + work); + int res; + + IPA_RM_DBG_LOW("calling to IPA driver. voltage %d bandwidth %d\n", + notify_work->volt, notify_work->bandwidth_mbps); + + res = ipa3_set_required_perf_profile(notify_work->volt, + notify_work->bandwidth_mbps); + if (res) { + IPA_RM_ERR("ipa3_set_required_perf_profile failed %d\n", res); + goto bail; + } + + IPA_RM_DBG_LOW("IPA driver notified\n"); +bail: + kfree(notify_work); +} + +static void ipa_rm_perf_profile_notify_to_ipa(enum ipa_voltage_level volt, + u32 bandwidth) +{ + struct ipa_rm_notify_ipa_work_type *work; + + work = kzalloc(sizeof(*work), GFP_ATOMIC); + if (!work) + return; + + INIT_WORK(&work->work, ipa_rm_perf_profile_notify_to_ipa_work); + work->volt = volt; + work->bandwidth_mbps = bandwidth; + queue_work(ipa_rm_ctx->ipa_rm_wq, &work->work); +} + +/** + * ipa_rm_perf_profile_change() - change performance profile vote for resource + * @resource_name: [in] resource name + * + * change bandwidth and voltage vote based on resource state. + */ +void ipa_rm_perf_profile_change(enum ipa_rm_resource_name resource_name) +{ + enum ipa_voltage_level old_volt; + u32 *bw_ptr; + u32 old_bw; + struct ipa_rm_resource *resource; + int i; + u32 sum_bw_prod = 0; + u32 sum_bw_cons = 0; + + IPA_RM_DBG_LOW("%s\n", ipa_rm_resource_str(resource_name)); + + if (ipa_rm_dep_graph_get_resource(ipa_rm_ctx->dep_graph, + resource_name, + &resource) != 0) { + IPA_RM_ERR("resource does not exists\n"); + WARN_ON(1); + return; + } + + old_volt = ipa_rm_ctx->prof_vote.curr_volt; + old_bw = ipa_rm_ctx->prof_vote.curr_bw; + + bw_ptr = &ipa_rm_ctx->prof_vote.bw_resources[resource_name]; + + switch (resource->state) { + case IPA_RM_GRANTED: + case IPA_RM_REQUEST_IN_PROGRESS: + IPA_RM_DBG_LOW("max_bw = %d, needed_bw = %d\n", + resource->max_bw, resource->needed_bw); + *bw_ptr = min(resource->max_bw, resource->needed_bw); + ipa_rm_ctx->prof_vote.volt[resource_name] = + resource->floor_voltage; + break; + + case IPA_RM_RELEASE_IN_PROGRESS: + case IPA_RM_RELEASED: + *bw_ptr = 0; + ipa_rm_ctx->prof_vote.volt[resource_name] = 0; + break; + + default: + IPA_RM_ERR("unknown state %d\n", resource->state); + WARN_ON(1); + return; + } + IPA_RM_DBG_LOW("resource bandwidth: %d voltage: %d\n", *bw_ptr, + resource->floor_voltage); + + ipa_rm_ctx->prof_vote.curr_volt = IPA_VOLTAGE_UNSPECIFIED; + for (i = 0; i < IPA_RM_RESOURCE_MAX; i++) { + if (ipa_rm_ctx->prof_vote.volt[i] > + ipa_rm_ctx->prof_vote.curr_volt) { + ipa_rm_ctx->prof_vote.curr_volt = + ipa_rm_ctx->prof_vote.volt[i]; + } + } + + for (i = 0; i < IPA_RM_RESOURCE_MAX; i++) { + if (IPA_RM_RESORCE_IS_PROD(i)) + sum_bw_prod += ipa_rm_ctx->prof_vote.bw_resources[i]; + else + sum_bw_cons += ipa_rm_ctx->prof_vote.bw_resources[i]; + } + + IPA_RM_DBG_LOW("all prod bandwidth: %d all cons bandwidth: %d\n", + sum_bw_prod, sum_bw_cons); + ipa_rm_ctx->prof_vote.curr_bw = min(sum_bw_prod, sum_bw_cons); + + if (ipa_rm_ctx->prof_vote.curr_volt == old_volt && + ipa_rm_ctx->prof_vote.curr_bw == old_bw) { + IPA_RM_DBG_LOW("same voting\n"); + return; + } + + IPA_RM_DBG_LOW("new voting: voltage %d bandwidth %d\n", + ipa_rm_ctx->prof_vote.curr_volt, + ipa_rm_ctx->prof_vote.curr_bw); + + ipa_rm_perf_profile_notify_to_ipa(ipa_rm_ctx->prof_vote.curr_volt, + ipa_rm_ctx->prof_vote.curr_bw); + + return; +}; +/** + * ipa_rm_exit() - free all IPA RM resources + */ +void ipa_rm_exit(void) +{ + IPA_RM_DBG("ENTER\n"); + ipa_rm_dep_graph_delete(ipa_rm_ctx->dep_graph); + destroy_workqueue(ipa_rm_ctx->ipa_rm_wq); + kfree(ipa_rm_ctx); + ipa_rm_ctx = NULL; + IPA_RM_DBG("EXIT\n"); +} diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_rm_dependency_graph.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_rm_dependency_graph.c new file mode 100644 index 0000000000..9fb8b7afe4 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_rm_dependency_graph.c @@ -0,0 +1,240 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2013-2019, The Linux Foundation. All rights reserved. + */ + +#include +#include "ipa_rm_dependency_graph.h" +#include "ipa_rm_i.h" + +static int ipa_rm_dep_get_index(enum ipa_rm_resource_name resource_name) +{ + int resource_index = IPA_RM_INDEX_INVALID; + + if (IPA_RM_RESORCE_IS_PROD(resource_name)) + resource_index = ipa_rm_prod_index(resource_name); + else if (IPA_RM_RESORCE_IS_CONS(resource_name)) + resource_index = ipa_rm_cons_index(resource_name); + + return resource_index; +} + +/** + * ipa_rm_dep_graph_create() - creates graph + * @dep_graph: [out] created dependency graph + * + * Returns: dependency graph on success, NULL on failure + */ +int ipa_rm_dep_graph_create(struct ipa_rm_dep_graph **dep_graph) +{ + int result = 0; + + *dep_graph = kzalloc(sizeof(**dep_graph), GFP_KERNEL); + if (!*dep_graph) + result = -ENOMEM; + return result; +} + +/** + * ipa_rm_dep_graph_delete() - destroyes the graph + * @graph: [in] dependency graph + * + * Frees all resources. + */ +void ipa_rm_dep_graph_delete(struct ipa_rm_dep_graph *graph) +{ + int resource_index; + + if (!graph) { + IPA_RM_ERR("invalid params\n"); + return; + } + for (resource_index = 0; + resource_index < IPA_RM_RESOURCE_MAX; + resource_index++) + kfree(graph->resource_table[resource_index]); + memset(graph->resource_table, 0, sizeof(graph->resource_table)); +} + +/** + * ipa_rm_dep_graph_get_resource() - provides a resource by name + * @graph: [in] dependency graph + * @name: [in] name of the resource + * @resource: [out] resource in case of success + * + * Returns: 0 on success, negative on failure + */ +int ipa_rm_dep_graph_get_resource( + struct ipa_rm_dep_graph *graph, + enum ipa_rm_resource_name resource_name, + struct ipa_rm_resource **resource) +{ + int result; + int resource_index; + + if (!graph) { + result = -EINVAL; + goto bail; + } + resource_index = ipa_rm_dep_get_index(resource_name); + if (resource_index == IPA_RM_INDEX_INVALID) { + result = -EINVAL; + goto bail; + } + *resource = graph->resource_table[resource_index]; + if (!*resource) { + result = -EINVAL; + goto bail; + } + result = 0; +bail: + return result; +} + +/** + * ipa_rm_dep_graph_add() - adds resource to graph + * @graph: [in] dependency graph + * @resource: [in] resource to add + * + * Returns: 0 on success, negative on failure + */ +int ipa_rm_dep_graph_add(struct ipa_rm_dep_graph *graph, + struct ipa_rm_resource *resource) +{ + int result = 0; + int resource_index; + + if (!graph || !resource) { + result = -EINVAL; + goto bail; + } + resource_index = ipa_rm_dep_get_index(resource->name); + if (resource_index == IPA_RM_INDEX_INVALID) { + result = -EINVAL; + goto bail; + } + graph->resource_table[resource_index] = resource; +bail: + return result; +} + +/** + * ipa_rm_dep_graph_remove() - removes resource from graph + * @graph: [in] dependency graph + * @resource: [in] resource to add + * + * Returns: 0 on success, negative on failure + */ +int ipa_rm_dep_graph_remove(struct ipa_rm_dep_graph *graph, + enum ipa_rm_resource_name resource_name) +{ + if (!graph) + return -EINVAL; + graph->resource_table[resource_name] = NULL; + + return 0; +} + +/** + * ipa_rm_dep_graph_add_dependency() - adds dependency between + * two nodes in graph + * @graph: [in] dependency graph + * @resource_name: [in] resource to add + * @depends_on_name: [in] resource to add + * @userspace_dep: [in] operation requested by userspace ? + * + * Returns: 0 on success, negative on failure + */ +int ipa_rm_dep_graph_add_dependency(struct ipa_rm_dep_graph *graph, + enum ipa_rm_resource_name resource_name, + enum ipa_rm_resource_name depends_on_name, + bool userspace_dep) +{ + struct ipa_rm_resource *dependent = NULL; + struct ipa_rm_resource *dependency = NULL; + int result; + + if (!graph || + !IPA_RM_RESORCE_IS_PROD(resource_name) || + !IPA_RM_RESORCE_IS_CONS(depends_on_name)) { + IPA_RM_ERR("invalid params\n"); + result = -EINVAL; + goto bail; + } + if (ipa_rm_dep_graph_get_resource(graph, + resource_name, + &dependent)) { + IPA_RM_ERR("%s does not exist\n", + ipa_rm_resource_str(resource_name)); + result = -EINVAL; + goto bail; + } + if (ipa_rm_dep_graph_get_resource(graph, + depends_on_name, + &dependency)) { + IPA_RM_ERR("%s does not exist\n", + ipa_rm_resource_str(depends_on_name)); + result = -EINVAL; + goto bail; + } + result = ipa_rm_resource_add_dependency(dependent, dependency, + userspace_dep); +bail: + IPA_RM_DBG("EXIT with %d\n", result); + + return result; +} + +/** + * ipa_rm_dep_graph_delete_dependency() - deleted dependency between + * two nodes in graph + * @graph: [in] dependency graph + * @resource_name: [in] resource to delete + * @depends_on_name: [in] resource to delete + * @userspace_dep: [in] operation requested by userspace ? + * + * Returns: 0 on success, negative on failure + * + */ +int ipa_rm_dep_graph_delete_dependency(struct ipa_rm_dep_graph *graph, + enum ipa_rm_resource_name resource_name, + enum ipa_rm_resource_name depends_on_name, + bool userspace_dep) +{ + struct ipa_rm_resource *dependent = NULL; + struct ipa_rm_resource *dependency = NULL; + int result; + + if (!graph || + !IPA_RM_RESORCE_IS_PROD(resource_name) || + !IPA_RM_RESORCE_IS_CONS(depends_on_name)) { + IPA_RM_ERR("invalid params\n"); + result = -EINVAL; + goto bail; + } + + if (ipa_rm_dep_graph_get_resource(graph, + resource_name, + &dependent)) { + IPA_RM_DBG("%s does not exist\n", + ipa_rm_resource_str(resource_name)); + result = -EINVAL; + goto bail; + } + + if (ipa_rm_dep_graph_get_resource(graph, + depends_on_name, + &dependency)) { + IPA_RM_DBG("%s does not exist\n", + ipa_rm_resource_str(depends_on_name)); + result = -EINVAL; + goto bail; + } + + result = ipa_rm_resource_delete_dependency(dependent, dependency, + userspace_dep); +bail: + IPA_RM_DBG("EXIT with %d\n", result); + + return result; +} diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_rm_dependency_graph.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_rm_dependency_graph.h new file mode 100644 index 0000000000..d658e62415 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_rm_dependency_graph.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2013-2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _IPA_RM_DEPENDENCY_GRAPH_H_ +#define _IPA_RM_DEPENDENCY_GRAPH_H_ + +#include +#include "ipa.h" +#include "ipa_rm_resource.h" + +struct ipa_rm_dep_graph { + struct ipa_rm_resource *resource_table[IPA_RM_RESOURCE_MAX]; +}; + +int ipa_rm_dep_graph_get_resource( + struct ipa_rm_dep_graph *graph, + enum ipa_rm_resource_name name, + struct ipa_rm_resource **resource); + +int ipa_rm_dep_graph_create(struct ipa_rm_dep_graph **dep_graph); + +void ipa_rm_dep_graph_delete(struct ipa_rm_dep_graph *graph); + +int ipa_rm_dep_graph_add(struct ipa_rm_dep_graph *graph, + struct ipa_rm_resource *resource); + +int ipa_rm_dep_graph_remove(struct ipa_rm_dep_graph *graph, + enum ipa_rm_resource_name resource_name); + +int ipa_rm_dep_graph_add_dependency(struct ipa_rm_dep_graph *graph, + enum ipa_rm_resource_name resource_name, + enum ipa_rm_resource_name depends_on_name, + bool userspsace_dep); + +int ipa_rm_dep_graph_delete_dependency(struct ipa_rm_dep_graph *graph, + enum ipa_rm_resource_name resource_name, + enum ipa_rm_resource_name depends_on_name, + bool userspsace_dep); + +#endif /* _IPA_RM_DEPENDENCY_GRAPH_H_ */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_rm_i.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_rm_i.h new file mode 100644 index 0000000000..2c23893cc0 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_rm_i.h @@ -0,0 +1,150 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2013-2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _IPA_RM_I_H_ +#define _IPA_RM_I_H_ + +#include +#include "ipa.h" +#include "ipa_rm_resource.h" +#include "ipa_common_i.h" + +#define IPA_RM_DRV_NAME "ipa_rm" + +#define IPA_RM_DBG_LOW(fmt, args...) \ + do { \ + pr_debug(IPA_RM_DRV_NAME " %s:%d " fmt, __func__, __LINE__, \ + ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf_low(), \ + IPA_RM_DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) +#define IPA_RM_DBG(fmt, args...) \ + do { \ + pr_debug(IPA_RM_DRV_NAME " %s:%d " fmt, __func__, __LINE__, \ + ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf(), \ + IPA_RM_DRV_NAME " %s:%d " fmt, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf_low(), \ + IPA_RM_DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) + +#define IPA_RM_ERR(fmt, args...) \ + do { \ + pr_err(IPA_RM_DRV_NAME " %s:%d " fmt, __func__, __LINE__, \ + ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf(), \ + IPA_RM_DRV_NAME " %s:%d " fmt, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf_low(), \ + IPA_RM_DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) + +#define IPA_RM_RESORCE_IS_PROD(x) \ + (x < IPA_RM_RESOURCE_MAX && (x & 0x1) == 0) +#define IPA_RM_RESORCE_IS_CONS(x) \ + (x < IPA_RM_RESOURCE_MAX && (x & 0x1) == 1) +#define IPA_RM_INDEX_INVALID (-1) +#define IPA_RM_RELEASE_DELAY_IN_MSEC 1000 + +int ipa_rm_prod_index(enum ipa_rm_resource_name resource_name); +int ipa_rm_cons_index(enum ipa_rm_resource_name resource_name); + +/** + * struct ipa_rm_delayed_release_work_type - IPA RM delayed resource release + * work type + * @delayed_work: work struct + * @ipa_rm_resource_name: name of the resource on which this work should be done + * @needed_bw: bandwidth required for resource in Mbps + * @dec_usage_count: decrease usage count on release ? + */ +struct ipa_rm_delayed_release_work_type { + struct delayed_work work; + enum ipa_rm_resource_name resource_name; + u32 needed_bw; + bool dec_usage_count; + +}; + +/** + * enum ipa_rm_wq_cmd - workqueue commands + */ +enum ipa_rm_wq_cmd { + IPA_RM_WQ_NOTIFY_PROD, + IPA_RM_WQ_NOTIFY_CONS, + IPA_RM_WQ_RESOURCE_CB +}; + +/** + * struct ipa_rm_wq_work_type - IPA RM worqueue specific + * work type + * @work: work struct + * @wq_cmd: command that should be processed in workqueue context + * @resource_name: name of the resource on which this work + * should be done + * @dep_graph: data structure to search for resource if exists + * @event: event to notify + * @notify_registered_only: notify only clients registered by + * ipa_rm_register() + */ +struct ipa_rm_wq_work_type { + struct work_struct work; + enum ipa_rm_wq_cmd wq_cmd; + enum ipa_rm_resource_name resource_name; + enum ipa_rm_event event; + bool notify_registered_only; +}; + +/** + * struct ipa_rm_wq_suspend_resume_work_type - IPA RM worqueue resume or + * suspend work type + * @work: work struct + * @resource_name: name of the resource on which this work + * should be done + * @prev_state: + * @needed_bw: + */ +struct ipa_rm_wq_suspend_resume_work_type { + struct work_struct work; + enum ipa_rm_resource_name resource_name; + enum ipa_rm_resource_state prev_state; + u32 needed_bw; + bool inc_usage_count; + +}; + +int ipa_rm_wq_send_cmd(enum ipa_rm_wq_cmd wq_cmd, + enum ipa_rm_resource_name resource_name, + enum ipa_rm_event event, + bool notify_registered_only); + +int ipa_rm_wq_send_resume_cmd(enum ipa_rm_resource_name resource_name, + enum ipa_rm_resource_state prev_state, + u32 needed_bw, + bool inc_usage_count); + +int ipa_rm_wq_send_suspend_cmd(enum ipa_rm_resource_name resource_name, + enum ipa_rm_resource_state prev_state, + u32 needed_bw); + +int ipa_rm_initialize(void); + +int ipa_rm_stat(char *buf, int size); + +const char *ipa_rm_resource_str(enum ipa_rm_resource_name resource_name); + +void ipa_rm_perf_profile_change(enum ipa_rm_resource_name resource_name); + +int ipa_rm_request_resource_with_timer(enum ipa_rm_resource_name resource_name); + +void delayed_release_work_func(struct work_struct *work); + +int ipa_rm_add_dependency_from_ioctl(enum ipa_rm_resource_name resource_name, + enum ipa_rm_resource_name depends_on_name); + +int ipa_rm_delete_dependency_from_ioctl(enum ipa_rm_resource_name resource_name, + enum ipa_rm_resource_name depends_on_name); + +void ipa_rm_exit(void); + +#endif /* _IPA_RM_I_H_ */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_rm_inactivity_timer.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_rm_inactivity_timer.c new file mode 100644 index 0000000000..6419f0fafd --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_rm_inactivity_timer.c @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2013-2019, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include "ipa.h" +#include "ipa_rm_i.h" + +#define MAX_WS_NAME 20 + +/** + * struct ipa_rm_it_private - IPA RM Inactivity Timer private + * data + * @initied: indicates if instance was initialized + * @lock - spinlock for mutual exclusion + * @resource_name - resource name + * @work: delayed work object for running delayed releas + * function + * @resource_requested: boolean flag indicates if resource was requested + * @reschedule_work: boolean flag indicates to not release and to + * reschedule the release work. + * @work_in_progress: boolean flag indicates is release work was scheduled. + * @jiffies: number of jiffies for timeout + * + * WWAN private - holds all relevant info about WWAN driver + */ +struct ipa_rm_it_private { + bool initied; + enum ipa_rm_resource_name resource_name; + spinlock_t lock; + struct delayed_work work; + bool resource_requested; + bool reschedule_work; + bool work_in_progress; + unsigned long jiffies; + struct wakeup_source *w_lock; + char w_lock_name[MAX_WS_NAME]; +}; diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_rm_peers_list.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_rm_peers_list.c new file mode 100644 index 0000000000..40ac927c42 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_rm_peers_list.c @@ -0,0 +1,272 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2013-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved + */ + +#include +#include "ipa_rm_i.h" + +/** + * ipa_rm_peers_list_get_resource_index() - resource name to index + * of this resource in corresponding peers list + * @resource_name: [in] resource name + * + * Returns: resource index mapping, IPA_RM_INDEX_INVALID + * in case provided resource name isn't contained in enum + * ipa_rm_resource_name. + * + */ +static int ipa_rm_peers_list_get_resource_index( + enum ipa_rm_resource_name resource_name) +{ + int resource_index = IPA_RM_INDEX_INVALID; + + if (IPA_RM_RESORCE_IS_PROD(resource_name)) + resource_index = ipa_rm_prod_index(resource_name); + else if (IPA_RM_RESORCE_IS_CONS(resource_name)) + resource_index = ipa_rm_cons_index(resource_name); + + return resource_index; +} + +static bool ipa_rm_peers_list_check_index(int index, + struct ipa_rm_peers_list *peers_list) +{ + return !(index > peers_list->max_peers || index < 0); +} + +/** + * ipa_rm_peers_list_create() - creates the peers list + * + * @max_peers: maximum number of peers in new list + * @peers_list: [out] newly created peers list + * + * Returns: 0 in case of SUCCESS, negative otherwise + */ +int ipa_rm_peers_list_create(int max_peers, + struct ipa_rm_peers_list **peers_list) +{ + int result; + + *peers_list = kzalloc(sizeof(**peers_list), GFP_ATOMIC); + if (!*peers_list) { + IPA_RM_ERR("no mem\n"); + result = -ENOMEM; + goto bail; + } + + (*peers_list)->max_peers = max_peers; + (*peers_list)->peers = kzalloc((*peers_list)->max_peers * + sizeof(*((*peers_list)->peers)), GFP_ATOMIC); + if (!((*peers_list)->peers)) { + IPA_RM_ERR("no mem\n"); + result = -ENOMEM; + goto list_alloc_fail; + } + + return 0; + +list_alloc_fail: + kfree(*peers_list); + *peers_list = NULL; +bail: + return result; +} + +/** + * ipa_rm_peers_list_delete() - deletes the peers list + * + * @peers_list: peers list + * + */ +void ipa_rm_peers_list_delete(struct ipa_rm_peers_list *peers_list) +{ + if (peers_list) { + kfree(peers_list->peers); + kfree(peers_list); + } +} + +/** + * ipa_rm_peers_list_remove_peer() - removes peer from the list + * + * @peers_list: peers list + * @resource_name: name of the resource to remove + * + */ +void ipa_rm_peers_list_remove_peer( + struct ipa_rm_peers_list *peers_list, + enum ipa_rm_resource_name resource_name) +{ + if (!peers_list) + return; + + peers_list->peers[ipa_rm_peers_list_get_resource_index( + resource_name)].resource = NULL; + peers_list->peers[ipa_rm_peers_list_get_resource_index( + resource_name)].userspace_dep = false; + peers_list->peers_count--; +} + +/** + * ipa_rm_peers_list_add_peer() - adds peer to the list + * + * @peers_list: peers list + * @resource: resource to add + * + */ +void ipa_rm_peers_list_add_peer( + struct ipa_rm_peers_list *peers_list, + struct ipa_rm_resource *resource, + bool userspace_dep) +{ + if (!peers_list || !resource) + return; + + peers_list->peers[ipa_rm_peers_list_get_resource_index( + resource->name)].resource = resource; + peers_list->peers[ipa_rm_peers_list_get_resource_index( + resource->name)].userspace_dep = userspace_dep; + peers_list->peers_count++; +} + +/** + * ipa_rm_peers_list_is_empty() - checks + * if resource peers list is empty + * + * @peers_list: peers list + * + * Returns: true if the list is empty, false otherwise + */ +bool ipa_rm_peers_list_is_empty(struct ipa_rm_peers_list *peers_list) +{ + bool result = true; + + if (!peers_list) + goto bail; + + if (peers_list->peers_count > 0) + result = false; +bail: + return result; +} + +/** + * ipa_rm_peers_list_has_last_peer() - checks + * if resource peers list has exactly one peer + * + * @peers_list: peers list + * + * Returns: true if the list has exactly one peer, false otherwise + */ +bool ipa_rm_peers_list_has_last_peer( + struct ipa_rm_peers_list *peers_list) +{ + bool result = false; + + if (!peers_list) + goto bail; + + if (peers_list->peers_count == 1) + result = true; +bail: + return result; +} + +/** + * ipa_rm_peers_list_check_dependency() - check dependency + * between 2 peer lists + * @resource_peers: first peers list + * @resource_name: first peers list resource name + * @depends_on_peers: second peers list + * @depends_on_name: second peers list resource name + * @userspace_dep: [out] dependency was created by userspace + * + * Returns: true if there is dependency, false otherwise + * + */ +bool ipa_rm_peers_list_check_dependency( + struct ipa_rm_peers_list *resource_peers, + enum ipa_rm_resource_name resource_name, + struct ipa_rm_peers_list *depends_on_peers, + enum ipa_rm_resource_name depends_on_name, + bool *userspace_dep) +{ + bool result = false; + int resource_index; + struct ipa_rm_resource_peer *peer_ptr; + + if (!resource_peers || !depends_on_peers || !userspace_dep) + return result; + + resource_index = ipa_rm_peers_list_get_resource_index(depends_on_name); + peer_ptr = &resource_peers->peers[resource_index]; + if (peer_ptr->resource != NULL) { + result = true; + *userspace_dep = peer_ptr->userspace_dep; + } + + resource_index = ipa_rm_peers_list_get_resource_index(resource_name); + peer_ptr = &depends_on_peers->peers[resource_index]; + if (peer_ptr->resource != NULL) { + result = true; + *userspace_dep = peer_ptr->userspace_dep; + } + + return result; +} + +/** + * ipa_rm_peers_list_get_resource() - get resource by + * resource index + * @resource_index: resource index + * @resource_peers: peers list + * + * Returns: the resource if found, NULL otherwise + */ +struct ipa_rm_resource *ipa_rm_peers_list_get_resource(int resource_index, + struct ipa_rm_peers_list *resource_peers) +{ + struct ipa_rm_resource *result = NULL; + + if (!ipa_rm_peers_list_check_index(resource_index, resource_peers)) + goto bail; + + result = resource_peers->peers[resource_index].resource; +bail: + return result; +} + +/** + * ipa_rm_peers_list_get_userspace_dep() - returns whether resource dependency + * was added by userspace + * @resource_index: resource index + * @resource_peers: peers list + * + * Returns: true if dependency was added by userspace, false by kernel + */ +bool ipa_rm_peers_list_get_userspace_dep(int resource_index, + struct ipa_rm_peers_list *resource_peers) +{ + bool result = false; + + if (!ipa_rm_peers_list_check_index(resource_index, resource_peers)) + goto bail; + + result = resource_peers->peers[resource_index].userspace_dep; +bail: + return result; +} + +/** + * ipa_rm_peers_list_get_size() - get peers list sise + * + * @peers_list: peers list + * + * Returns: the size of the peers list + */ +int ipa_rm_peers_list_get_size(struct ipa_rm_peers_list *peers_list) +{ + return peers_list->max_peers; +} diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_rm_peers_list.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_rm_peers_list.h new file mode 100644 index 0000000000..98415645c3 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_rm_peers_list.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2013-2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _IPA_RM_PEERS_LIST_H_ +#define _IPA_RM_PEERS_LIST_H_ + +#include "ipa_rm_resource.h" + +struct ipa_rm_resource_peer { + struct ipa_rm_resource *resource; + bool userspace_dep; +}; + +/** + * struct ipa_rm_peers_list - IPA RM resource peers list + * @peers: the list of references to resources dependent on this resource + * in case of producer or list of dependencies in case of consumer + * @max_peers: maximum number of peers for this resource + * @peers_count: actual number of peers for this resource + */ +struct ipa_rm_peers_list { + struct ipa_rm_resource_peer *peers; + int max_peers; + int peers_count; +}; + +int ipa_rm_peers_list_create(int max_peers, + struct ipa_rm_peers_list **peers_list); +void ipa_rm_peers_list_delete(struct ipa_rm_peers_list *peers_list); +void ipa_rm_peers_list_remove_peer( + struct ipa_rm_peers_list *peers_list, + enum ipa_rm_resource_name resource_name); +void ipa_rm_peers_list_add_peer( + struct ipa_rm_peers_list *peers_list, + struct ipa_rm_resource *resource, + bool userspace_dep); +bool ipa_rm_peers_list_check_dependency( + struct ipa_rm_peers_list *resource_peers, + enum ipa_rm_resource_name resource_name, + struct ipa_rm_peers_list *depends_on_peers, + enum ipa_rm_resource_name depends_on_name, + bool *userspace_dep); +struct ipa_rm_resource *ipa_rm_peers_list_get_resource(int resource_index, + struct ipa_rm_peers_list *peers_list); +bool ipa_rm_peers_list_get_userspace_dep(int resource_index, + struct ipa_rm_peers_list *resource_peers); +int ipa_rm_peers_list_get_size(struct ipa_rm_peers_list *peers_list); +bool ipa_rm_peers_list_is_empty(struct ipa_rm_peers_list *peers_list); +bool ipa_rm_peers_list_has_last_peer( + struct ipa_rm_peers_list *peers_list); + + +#endif /* _IPA_RM_PEERS_LIST_H_ */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_rm_resource.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_rm_resource.c new file mode 100644 index 0000000000..a7f8347290 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_rm_resource.c @@ -0,0 +1,1204 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2013-2019, The Linux Foundation. All rights reserved. + */ + +#include +#include "ipa_rm_resource.h" +#include "ipa_rm_i.h" +#include "ipa_common_i.h" +/** + * ipa_rm_dep_prod_index() - producer name to producer index mapping + * @resource_name: [in] resource name (should be of producer) + * + * Returns: resource index mapping, IPA_RM_INDEX_INVALID + * in case provided resource name isn't contained + * in enum ipa_rm_resource_name or is not of producers. + * + */ +int ipa_rm_prod_index(enum ipa_rm_resource_name resource_name) +{ + int result = resource_name; + + switch (resource_name) { + case IPA_RM_RESOURCE_Q6_PROD: + case IPA_RM_RESOURCE_USB_PROD: + case IPA_RM_RESOURCE_USB_DPL_DUMMY_PROD: + case IPA_RM_RESOURCE_HSIC_PROD: + case IPA_RM_RESOURCE_STD_ECM_PROD: + case IPA_RM_RESOURCE_RNDIS_PROD: + case IPA_RM_RESOURCE_WWAN_0_PROD: + case IPA_RM_RESOURCE_WLAN_PROD: + case IPA_RM_RESOURCE_ODU_ADAPT_PROD: + case IPA_RM_RESOURCE_MHI_PROD: + case IPA_RM_RESOURCE_ETHERNET_PROD: + break; + default: + result = IPA_RM_INDEX_INVALID; + break; + } + + return result; +} + +/** + * ipa_rm_cons_index() - consumer name to consumer index mapping + * @resource_name: [in] resource name (should be of consumer) + * + * Returns: resource index mapping, IPA_RM_INDEX_INVALID + * in case provided resource name isn't contained + * in enum ipa_rm_resource_name or is not of consumers. + * + */ +int ipa_rm_cons_index(enum ipa_rm_resource_name resource_name) +{ + int result = resource_name; + + switch (resource_name) { + case IPA_RM_RESOURCE_Q6_CONS: + case IPA_RM_RESOURCE_USB_CONS: + case IPA_RM_RESOURCE_HSIC_CONS: + case IPA_RM_RESOURCE_WLAN_CONS: + case IPA_RM_RESOURCE_APPS_CONS: + case IPA_RM_RESOURCE_ODU_ADAPT_CONS: + case IPA_RM_RESOURCE_MHI_CONS: + case IPA_RM_RESOURCE_USB_DPL_CONS: + case IPA_RM_RESOURCE_ETHERNET_CONS: + break; + default: + result = IPA_RM_INDEX_INVALID; + break; + } + + return result; +} + +int ipa_rm_resource_consumer_release_work( + struct ipa_rm_resource_cons *consumer, + enum ipa_rm_resource_state prev_state, + bool notify_completion) +{ + int driver_result; + + IPA_RM_DBG_LOW("calling driver CB\n"); + driver_result = consumer->release_resource(); + IPA_RM_DBG_LOW("driver CB returned with %d\n", driver_result); + /* + * Treat IPA_RM_RELEASE_IN_PROGRESS as IPA_RM_RELEASED + * for CONS which remains in RELEASE_IN_PROGRESS. + */ + if (driver_result == -EINPROGRESS) + driver_result = 0; + if (driver_result != 0 && driver_result != -EINPROGRESS) { + IPA_RM_ERR("driver CB returned error %d\n", driver_result); + consumer->resource.state = prev_state; + goto bail; + } + if (driver_result == 0) { + if (notify_completion) + ipa_rm_resource_consumer_handle_cb(consumer, + IPA_RM_RESOURCE_RELEASED); + else + consumer->resource.state = IPA_RM_RELEASED; + } + complete_all(&consumer->request_consumer_in_progress); + + ipa_rm_perf_profile_change(consumer->resource.name); +bail: + return driver_result; +} + +int ipa_rm_resource_consumer_request_work(struct ipa_rm_resource_cons *consumer, + enum ipa_rm_resource_state prev_state, + u32 prod_needed_bw, + bool notify_completion, + bool dec_client_on_err) +{ + int driver_result; + + IPA_RM_DBG_LOW("calling driver CB\n"); + driver_result = consumer->request_resource(); + IPA_RM_DBG_LOW("driver CB returned with %d\n", driver_result); + if (driver_result == 0) { + if (notify_completion) { + ipa_rm_resource_consumer_handle_cb(consumer, + IPA_RM_RESOURCE_GRANTED); + } else { + consumer->resource.state = IPA_RM_GRANTED; + ipa_rm_perf_profile_change(consumer->resource.name); + ipa3_resume_resource(consumer->resource.name); + } + } else if (driver_result != -EINPROGRESS) { + consumer->resource.state = prev_state; + consumer->resource.needed_bw -= prod_needed_bw; + if (dec_client_on_err) + consumer->usage_count--; + } + + return driver_result; +} + +int ipa_rm_resource_consumer_request( + struct ipa_rm_resource_cons *consumer, + u32 prod_needed_bw, + bool inc_usage_count, + bool wake_client) +{ + int result = 0; + enum ipa_rm_resource_state prev_state; + struct ipa_active_client_logging_info log_info; + + IPA_RM_DBG_LOW("%s state: %d\n", + ipa_rm_resource_str(consumer->resource.name), + consumer->resource.state); + + prev_state = consumer->resource.state; + consumer->resource.needed_bw += prod_needed_bw; + switch (consumer->resource.state) { + case IPA_RM_RELEASED: + case IPA_RM_RELEASE_IN_PROGRESS: + reinit_completion(&consumer->request_consumer_in_progress); + consumer->resource.state = IPA_RM_REQUEST_IN_PROGRESS; + IPA_ACTIVE_CLIENTS_PREP_RESOURCE(log_info, + ipa_rm_resource_str(consumer->resource.name)); + if (prev_state == IPA_RM_RELEASE_IN_PROGRESS || + ipa3_inc_client_enable_clks_no_block(&log_info) != 0) { + IPA_RM_DBG_LOW("async resume work for %s\n", + ipa_rm_resource_str(consumer->resource.name)); + ipa_rm_wq_send_resume_cmd(consumer->resource.name, + prev_state, + prod_needed_bw, + inc_usage_count); + result = -EINPROGRESS; + break; + } + result = ipa_rm_resource_consumer_request_work(consumer, + prev_state, + prod_needed_bw, + false, + inc_usage_count); + break; + case IPA_RM_GRANTED: + if (wake_client) { + result = ipa_rm_resource_consumer_request_work( + consumer, prev_state, prod_needed_bw, false, + inc_usage_count); + break; + } + ipa_rm_perf_profile_change(consumer->resource.name); + break; + case IPA_RM_REQUEST_IN_PROGRESS: + result = -EINPROGRESS; + break; + default: + consumer->resource.needed_bw -= prod_needed_bw; + result = -EPERM; + goto bail; + } + if (inc_usage_count) + consumer->usage_count++; +bail: + IPA_RM_DBG_LOW("%s new state: %d\n", + ipa_rm_resource_str(consumer->resource.name), + consumer->resource.state); + IPA_RM_DBG_LOW("EXIT with %d\n", result); + + return result; +} + +int ipa_rm_resource_consumer_release( + struct ipa_rm_resource_cons *consumer, + u32 prod_needed_bw, + bool dec_usage_count) +{ + int result = 0; + enum ipa_rm_resource_state save_state; + + IPA_RM_DBG_LOW("%s state: %d\n", + ipa_rm_resource_str(consumer->resource.name), + consumer->resource.state); + save_state = consumer->resource.state; + consumer->resource.needed_bw -= prod_needed_bw; + switch (consumer->resource.state) { + case IPA_RM_RELEASED: + break; + case IPA_RM_GRANTED: + case IPA_RM_REQUEST_IN_PROGRESS: + if (dec_usage_count && consumer->usage_count > 0) + consumer->usage_count--; + if (consumer->usage_count == 0) { + consumer->resource.state = IPA_RM_RELEASE_IN_PROGRESS; + if (save_state == IPA_RM_REQUEST_IN_PROGRESS || + ipa3_suspend_resource_no_block( + consumer->resource.name) != 0) { + ipa_rm_wq_send_suspend_cmd( + consumer->resource.name, + save_state, + prod_needed_bw); + result = -EINPROGRESS; + goto bail; + } + result = ipa_rm_resource_consumer_release_work(consumer, + save_state, false); + goto bail; + } else if (consumer->resource.state == IPA_RM_GRANTED) { + ipa_rm_perf_profile_change(consumer->resource.name); + } + break; + case IPA_RM_RELEASE_IN_PROGRESS: + if (dec_usage_count && consumer->usage_count > 0) + consumer->usage_count--; + result = -EINPROGRESS; + break; + default: + result = -EPERM; + goto bail; + } +bail: + IPA_RM_DBG_LOW("%s new state: %d\n", + ipa_rm_resource_str(consumer->resource.name), + consumer->resource.state); + IPA_RM_DBG_LOW("EXIT with %d\n", result); + + return result; +} + +/** + * ipa_rm_resource_producer_notify_clients() - notify + * all registered clients of given producer + * @producer: producer + * @event: event to notify + * @notify_registered_only: notify only clients registered by + * ipa_rm_register() + */ +void ipa_rm_resource_producer_notify_clients( + struct ipa_rm_resource_prod *producer, + enum ipa_rm_event event, + bool notify_registered_only) +{ + struct ipa_rm_notification_info *reg_info; + + IPA_RM_DBG_LOW("%s event: %d notify_registered_only: %d\n", + ipa_rm_resource_str(producer->resource.name), + event, + notify_registered_only); + + list_for_each_entry(reg_info, &(producer->event_listeners), link) { + if (notify_registered_only && !reg_info->explicit) + continue; + + IPA_RM_DBG_LOW("Notifying %s event: %d\n", + ipa_rm_resource_str(producer->resource.name), event); + reg_info->reg_params.notify_cb(reg_info->reg_params.user_data, + event, + 0); + IPA_RM_DBG_LOW("back from client CB\n"); + } +} + +static int ipa_rm_resource_producer_create(struct ipa_rm_resource **resource, + struct ipa_rm_resource_prod **producer, + struct ipa_rm_create_params *create_params, + int *max_peers) +{ + int result = 0; + + *producer = kzalloc(sizeof(**producer), GFP_ATOMIC); + if (*producer == NULL) { + result = -ENOMEM; + goto bail; + } + + INIT_LIST_HEAD(&((*producer)->event_listeners)); + result = ipa_rm_resource_producer_register(*producer, + &(create_params->reg_params), + false); + if (result) { + IPA_RM_ERR("ipa_rm_resource_producer_register() failed\n"); + goto register_fail; + } + + (*resource) = (struct ipa_rm_resource *) (*producer); + (*resource)->type = IPA_RM_PRODUCER; + *max_peers = IPA_RM_RESOURCE_MAX; + goto bail; +register_fail: + kfree(*producer); +bail: + return result; +} + +static void ipa_rm_resource_producer_delete( + struct ipa_rm_resource_prod *producer) +{ + struct ipa_rm_notification_info *reg_info; + struct list_head *pos, *q; + + ipa_rm_resource_producer_release(producer); + list_for_each_safe(pos, q, &(producer->event_listeners)) { + reg_info = list_entry(pos, + struct ipa_rm_notification_info, + link); + list_del(pos); + kfree(reg_info); + } +} + +static int ipa_rm_resource_consumer_create(struct ipa_rm_resource **resource, + struct ipa_rm_resource_cons **consumer, + struct ipa_rm_create_params *create_params, + int *max_peers) +{ + int result = 0; + + *consumer = kzalloc(sizeof(**consumer), GFP_ATOMIC); + if (*consumer == NULL) { + result = -ENOMEM; + goto bail; + } + + (*consumer)->request_resource = create_params->request_resource; + (*consumer)->release_resource = create_params->release_resource; + (*resource) = (struct ipa_rm_resource *) (*consumer); + (*resource)->type = IPA_RM_CONSUMER; + init_completion(&((*consumer)->request_consumer_in_progress)); + *max_peers = IPA_RM_RESOURCE_MAX; +bail: + return result; +} + +/** + * ipa_rm_resource_create() - creates resource + * @create_params: [in] parameters needed + * for resource initialization with IPA RM + * @resource: [out] created resource + * + * Returns: 0 on success, negative on failure + */ +int ipa_rm_resource_create( + struct ipa_rm_create_params *create_params, + struct ipa_rm_resource **resource) +{ + struct ipa_rm_resource_cons *consumer; + struct ipa_rm_resource_prod *producer; + int max_peers; + int result = 0; + + if (!create_params) { + result = -EINVAL; + goto bail; + } + + if (IPA_RM_RESORCE_IS_PROD(create_params->name)) { + result = ipa_rm_resource_producer_create(resource, + &producer, + create_params, + &max_peers); + if (result) { + IPA_RM_ERR("ipa_rm_resource_producer_create failed\n"); + goto bail; + } + } else if (IPA_RM_RESORCE_IS_CONS(create_params->name)) { + result = ipa_rm_resource_consumer_create(resource, + &consumer, + create_params, + &max_peers); + if (result) { + IPA_RM_ERR("ipa_rm_resource_producer_create failed\n"); + goto bail; + } + } else { + IPA_RM_ERR("invalid resource\n"); + result = -EPERM; + goto bail; + } + + result = ipa_rm_peers_list_create(max_peers, + &((*resource)->peers_list)); + if (result) { + IPA_RM_ERR("ipa_rm_peers_list_create failed\n"); + goto peers_alloc_fail; + } + (*resource)->name = create_params->name; + (*resource)->floor_voltage = create_params->floor_voltage; + (*resource)->state = IPA_RM_RELEASED; + goto bail; + +peers_alloc_fail: + ipa_rm_resource_delete(*resource); +bail: + return result; +} + +/** + * ipa_rm_resource_delete() - deletes resource + * @resource: [in] resource + * for resource initialization with IPA RM + * + * Returns: 0 on success, negative on failure + */ +int ipa_rm_resource_delete(struct ipa_rm_resource *resource) +{ + struct ipa_rm_resource *consumer; + struct ipa_rm_resource *producer; + int peers_index; + int result = 0; + int list_size; + bool userspace_dep; + + if (!resource) { + IPA_RM_ERR("invalid params\n"); + return -EINVAL; + } + + IPA_RM_DBG("ENTER with resource %d\n", resource->name); + if (resource->type == IPA_RM_PRODUCER) { + if (resource->peers_list) { + list_size = ipa_rm_peers_list_get_size( + resource->peers_list); + for (peers_index = 0; + peers_index < list_size; + peers_index++) { + consumer = ipa_rm_peers_list_get_resource( + peers_index, + resource->peers_list); + if (consumer) { + userspace_dep = + ipa_rm_peers_list_get_userspace_dep( + peers_index, + resource->peers_list); + ipa_rm_resource_delete_dependency( + resource, + consumer, + userspace_dep); + } + } + } + + ipa_rm_resource_producer_delete( + (struct ipa_rm_resource_prod *) resource); + } else if (resource->type == IPA_RM_CONSUMER) { + if (resource->peers_list) { + list_size = ipa_rm_peers_list_get_size( + resource->peers_list); + for (peers_index = 0; + peers_index < list_size; + peers_index++){ + producer = ipa_rm_peers_list_get_resource( + peers_index, + resource->peers_list); + if (producer) { + userspace_dep = + ipa_rm_peers_list_get_userspace_dep( + peers_index, + resource->peers_list); + ipa_rm_resource_delete_dependency( + producer, + resource, + userspace_dep); + } + } + } + } + ipa_rm_peers_list_delete(resource->peers_list); + kfree(resource); + return result; +} + +/** + * ipa_rm_resource_register() - register resource + * @resource: [in] resource + * @reg_params: [in] registration parameters + * @explicit: [in] registered explicitly by ipa_rm_register() + * + * Returns: 0 on success, negative on failure + * + * Producer resource is expected for this call. + * + */ +int ipa_rm_resource_producer_register(struct ipa_rm_resource_prod *producer, + struct ipa_rm_register_params *reg_params, + bool explicit) +{ + int result = 0; + struct ipa_rm_notification_info *reg_info; + struct list_head *pos; + + if (!producer || !reg_params) { + IPA_RM_ERR("invalid params\n"); + result = -EPERM; + goto bail; + } + + list_for_each(pos, &(producer->event_listeners)) { + reg_info = list_entry(pos, + struct ipa_rm_notification_info, + link); + if (reg_info->reg_params.notify_cb == + reg_params->notify_cb) { + IPA_RM_ERR("already registered\n"); + result = -EPERM; + goto bail; + } + + } + + reg_info = kzalloc(sizeof(*reg_info), GFP_ATOMIC); + if (reg_info == NULL) { + result = -ENOMEM; + goto bail; + } + + reg_info->reg_params.user_data = reg_params->user_data; + reg_info->reg_params.notify_cb = reg_params->notify_cb; + reg_info->explicit = explicit; + INIT_LIST_HEAD(®_info->link); + list_add(®_info->link, &producer->event_listeners); +bail: + return result; +} + +/** + * ipa_rm_resource_deregister() - register resource + * @resource: [in] resource + * @reg_params: [in] registration parameters + * + * Returns: 0 on success, negative on failure + * + * Producer resource is expected for this call. + * This function deleted only single instance of + * registration info. + * + */ +int ipa_rm_resource_producer_deregister(struct ipa_rm_resource_prod *producer, + struct ipa_rm_register_params *reg_params) +{ + int result = -EINVAL; + struct ipa_rm_notification_info *reg_info; + struct list_head *pos, *q; + + if (!producer || !reg_params) { + IPA_RM_ERR("invalid params\n"); + return -EINVAL; + } + + list_for_each_safe(pos, q, &(producer->event_listeners)) { + reg_info = list_entry(pos, + struct ipa_rm_notification_info, + link); + if (reg_info->reg_params.notify_cb == + reg_params->notify_cb) { + list_del(pos); + kfree(reg_info); + result = 0; + goto bail; + } + } +bail: + return result; +} + +/** + * ipa_rm_resource_add_dependency() - add dependency between two + * given resources + * @resource: [in] resource resource + * @depends_on: [in] depends_on resource + * + * Returns: 0 on success, negative on failure + */ +int ipa_rm_resource_add_dependency(struct ipa_rm_resource *resource, + struct ipa_rm_resource *depends_on, + bool userspace_dep) +{ + int result = 0; + int consumer_result; + bool add_dep_by_userspace; + + if (!resource || !depends_on) { + IPA_RM_ERR("invalid params\n"); + return -EINVAL; + } + + if (ipa_rm_peers_list_check_dependency(resource->peers_list, + resource->name, + depends_on->peers_list, + depends_on->name, + &add_dep_by_userspace)) { + IPA_RM_ERR("dependency already exists, added by %s\n", + add_dep_by_userspace ? "userspace" : "kernel"); + return -EEXIST; + } + + ipa_rm_peers_list_add_peer(resource->peers_list, depends_on, + userspace_dep); + ipa_rm_peers_list_add_peer(depends_on->peers_list, resource, + userspace_dep); + IPA_RM_DBG("%s state: %d\n", ipa_rm_resource_str(resource->name), + resource->state); + + resource->needed_bw += depends_on->max_bw; + switch (resource->state) { + case IPA_RM_RELEASED: + case IPA_RM_RELEASE_IN_PROGRESS: + break; + case IPA_RM_GRANTED: + case IPA_RM_REQUEST_IN_PROGRESS: + { + enum ipa_rm_resource_state prev_state = resource->state; + + resource->state = IPA_RM_REQUEST_IN_PROGRESS; + ((struct ipa_rm_resource_prod *) + resource)->pending_request++; + consumer_result = ipa_rm_resource_consumer_request( + (struct ipa_rm_resource_cons *)depends_on, + resource->max_bw, + true, false); + if (consumer_result != -EINPROGRESS) { + resource->state = prev_state; + ((struct ipa_rm_resource_prod *) + resource)->pending_request--; + ipa_rm_perf_profile_change(resource->name); + } + result = consumer_result; + break; + } + default: + IPA_RM_ERR("invalid state\n"); + result = -EPERM; + goto bail; + } +bail: + IPA_RM_DBG("%s new state: %d\n", ipa_rm_resource_str(resource->name), + resource->state); + IPA_RM_DBG("EXIT with %d\n", result); + + return result; +} + +/** + * ipa_rm_resource_delete_dependency() - add dependency between two + * given resources + * @resource: [in] resource resource + * @depends_on: [in] depends_on resource + * + * Returns: 0 on success, negative on failure + * In case the resource state was changed, a notification + * will be sent to the RM client + */ +int ipa_rm_resource_delete_dependency(struct ipa_rm_resource *resource, + struct ipa_rm_resource *depends_on, + bool userspace_dep) +{ + int result = 0; + bool state_changed = false; + bool release_consumer = false; + enum ipa_rm_event evt; + bool add_dep_by_userspace; + + if (!resource || !depends_on) { + IPA_RM_ERR("invalid params\n"); + return -EINVAL; + } + + if (!ipa_rm_peers_list_check_dependency(resource->peers_list, + resource->name, + depends_on->peers_list, + depends_on->name, + &add_dep_by_userspace)) { + IPA_RM_ERR("dependency does not exist\n"); + return -EINVAL; + } + + /* + * to avoid race conditions between kernel and userspace + * need to check that the dependency was added by same entity + */ + if (add_dep_by_userspace != userspace_dep) { + IPA_RM_DBG("dependency was added by %s\n", + add_dep_by_userspace ? "userspace" : "kernel"); + IPA_RM_DBG("ignore request to delete dependency by %s\n", + userspace_dep ? "userspace" : "kernel"); + return 0; + } + + IPA_RM_DBG("%s state: %d\n", ipa_rm_resource_str(resource->name), + resource->state); + + resource->needed_bw -= depends_on->max_bw; + switch (resource->state) { + case IPA_RM_RELEASED: + break; + case IPA_RM_GRANTED: + ipa_rm_perf_profile_change(resource->name); + release_consumer = true; + break; + case IPA_RM_RELEASE_IN_PROGRESS: + if (((struct ipa_rm_resource_prod *) + resource)->pending_release > 0) + ((struct ipa_rm_resource_prod *) + resource)->pending_release--; + if (depends_on->state == IPA_RM_RELEASE_IN_PROGRESS && + ((struct ipa_rm_resource_prod *) + resource)->pending_release == 0) { + resource->state = IPA_RM_RELEASED; + state_changed = true; + evt = IPA_RM_RESOURCE_RELEASED; + ipa_rm_perf_profile_change(resource->name); + } + break; + case IPA_RM_REQUEST_IN_PROGRESS: + release_consumer = true; + if (((struct ipa_rm_resource_prod *) + resource)->pending_request > 0) + ((struct ipa_rm_resource_prod *) + resource)->pending_request--; + if (depends_on->state == IPA_RM_REQUEST_IN_PROGRESS && + ((struct ipa_rm_resource_prod *) + resource)->pending_request == 0) { + resource->state = IPA_RM_GRANTED; + state_changed = true; + evt = IPA_RM_RESOURCE_GRANTED; + ipa_rm_perf_profile_change(resource->name); + } + break; + default: + result = -EINVAL; + goto bail; + } + if (state_changed) { + (void) ipa_rm_wq_send_cmd(IPA_RM_WQ_NOTIFY_PROD, + resource->name, + evt, + false); + } + IPA_RM_DBG("%s new state: %d\n", ipa_rm_resource_str(resource->name), + resource->state); + ipa_rm_peers_list_remove_peer(resource->peers_list, + depends_on->name); + ipa_rm_peers_list_remove_peer(depends_on->peers_list, + resource->name); + if (release_consumer) + (void) ipa_rm_resource_consumer_release( + (struct ipa_rm_resource_cons *)depends_on, + resource->max_bw, + true); +bail: + IPA_RM_DBG("EXIT with %d\n", result); + + return result; +} + +/** + * ipa_rm_resource_producer_request() - producer resource request + * @producer: [in] producer + * + * Returns: 0 on success, negative on failure + */ +int ipa_rm_resource_producer_request(struct ipa_rm_resource_prod *producer) +{ + int peers_index; + int result = 0; + struct ipa_rm_resource *consumer; + int consumer_result; + enum ipa_rm_resource_state state; + + state = producer->resource.state; + switch (producer->resource.state) { + case IPA_RM_RELEASED: + case IPA_RM_RELEASE_IN_PROGRESS: + producer->resource.state = IPA_RM_REQUEST_IN_PROGRESS; + break; + case IPA_RM_GRANTED: + goto unlock_and_bail; + case IPA_RM_REQUEST_IN_PROGRESS: + result = -EINPROGRESS; + goto unlock_and_bail; + default: + result = -EINVAL; + goto unlock_and_bail; + } + + producer->pending_request = 0; + for (peers_index = 0; + peers_index < ipa_rm_peers_list_get_size( + producer->resource.peers_list); + peers_index++) { + consumer = ipa_rm_peers_list_get_resource(peers_index, + producer->resource.peers_list); + if (consumer) { + producer->pending_request++; + consumer_result = ipa_rm_resource_consumer_request( + (struct ipa_rm_resource_cons *)consumer, + producer->resource.max_bw, + true, false); + if (consumer_result == -EINPROGRESS) { + result = -EINPROGRESS; + } else { + producer->pending_request--; + if (consumer_result != 0) { + result = consumer_result; + goto bail; + } + } + } + } + + if (producer->pending_request == 0) { + producer->resource.state = IPA_RM_GRANTED; + ipa_rm_perf_profile_change(producer->resource.name); + (void) ipa_rm_wq_send_cmd(IPA_RM_WQ_NOTIFY_PROD, + producer->resource.name, + IPA_RM_RESOURCE_GRANTED, + true); + result = 0; + } +unlock_and_bail: + if (state != producer->resource.state) + IPA_RM_DBG_LOW("%s state changed %d->%d\n", + ipa_rm_resource_str(producer->resource.name), + state, + producer->resource.state); +bail: + return result; +} + +/** + * ipa_rm_resource_producer_release() - producer resource release + * producer: [in] producer resource + * + * Returns: 0 on success, negative on failure + * + */ +int ipa_rm_resource_producer_release(struct ipa_rm_resource_prod *producer) +{ + int peers_index; + int result = 0; + struct ipa_rm_resource *consumer; + int consumer_result; + enum ipa_rm_resource_state state; + + state = producer->resource.state; + switch (producer->resource.state) { + case IPA_RM_RELEASED: + goto bail; + case IPA_RM_GRANTED: + case IPA_RM_REQUEST_IN_PROGRESS: + producer->resource.state = IPA_RM_RELEASE_IN_PROGRESS; + break; + case IPA_RM_RELEASE_IN_PROGRESS: + result = -EINPROGRESS; + goto bail; + default: + result = -EPERM; + goto bail; + } + + producer->pending_release = 0; + for (peers_index = 0; + peers_index < ipa_rm_peers_list_get_size( + producer->resource.peers_list); + peers_index++) { + consumer = ipa_rm_peers_list_get_resource(peers_index, + producer->resource.peers_list); + if (consumer) { + producer->pending_release++; + consumer_result = ipa_rm_resource_consumer_release( + (struct ipa_rm_resource_cons *)consumer, + producer->resource.max_bw, + true); + producer->pending_release--; + } + } + + if (producer->pending_release == 0) { + producer->resource.state = IPA_RM_RELEASED; + ipa_rm_perf_profile_change(producer->resource.name); + (void) ipa_rm_wq_send_cmd(IPA_RM_WQ_NOTIFY_PROD, + producer->resource.name, + IPA_RM_RESOURCE_RELEASED, + true); + } +bail: + if (state != producer->resource.state) + IPA_RM_DBG_LOW("%s state changed %d->%d\n", + ipa_rm_resource_str(producer->resource.name), + state, + producer->resource.state); + + return result; +} + +static void ipa_rm_resource_producer_handle_cb( + struct ipa_rm_resource_prod *producer, + enum ipa_rm_event event) +{ + IPA_RM_DBG_LOW("%s state: %d event: %d pending_request: %d\n", + ipa_rm_resource_str(producer->resource.name), + producer->resource.state, + event, + producer->pending_request); + + switch (producer->resource.state) { + case IPA_RM_REQUEST_IN_PROGRESS: + if (event != IPA_RM_RESOURCE_GRANTED) + goto unlock_and_bail; + if (producer->pending_request > 0) { + producer->pending_request--; + if (producer->pending_request == 0) { + producer->resource.state = + IPA_RM_GRANTED; + ipa_rm_perf_profile_change( + producer->resource.name); + ipa_rm_resource_producer_notify_clients( + producer, + IPA_RM_RESOURCE_GRANTED, + false); + goto bail; + } + } + break; + case IPA_RM_RELEASE_IN_PROGRESS: + if (event != IPA_RM_RESOURCE_RELEASED) + goto unlock_and_bail; + if (producer->pending_release > 0) { + producer->pending_release--; + if (producer->pending_release == 0) { + producer->resource.state = + IPA_RM_RELEASED; + ipa_rm_perf_profile_change( + producer->resource.name); + ipa_rm_resource_producer_notify_clients( + producer, + IPA_RM_RESOURCE_RELEASED, + false); + goto bail; + } + } + break; + case IPA_RM_GRANTED: + case IPA_RM_RELEASED: + default: + goto unlock_and_bail; + } +unlock_and_bail: + IPA_RM_DBG_LOW("%s new state: %d\n", + ipa_rm_resource_str(producer->resource.name), + producer->resource.state); +bail: + return; +} + +/** + * ipa_rm_resource_consumer_handle_cb() - propagates resource + * notification to all dependent producers + * @consumer: [in] notifying resource + * + */ +void ipa_rm_resource_consumer_handle_cb(struct ipa_rm_resource_cons *consumer, + enum ipa_rm_event event) +{ + int peers_index; + struct ipa_rm_resource *producer; + + if (!consumer) { + IPA_RM_ERR("invalid params\n"); + return; + } + IPA_RM_DBG_LOW("%s state: %d event: %d\n", + ipa_rm_resource_str(consumer->resource.name), + consumer->resource.state, + event); + + switch (consumer->resource.state) { + case IPA_RM_REQUEST_IN_PROGRESS: + if (event == IPA_RM_RESOURCE_RELEASED) + goto bail; + consumer->resource.state = IPA_RM_GRANTED; + ipa_rm_perf_profile_change(consumer->resource.name); + ipa3_resume_resource(consumer->resource.name); + complete_all(&consumer->request_consumer_in_progress); + break; + case IPA_RM_RELEASE_IN_PROGRESS: + if (event == IPA_RM_RESOURCE_GRANTED) + goto bail; + consumer->resource.state = IPA_RM_RELEASED; + break; + case IPA_RM_GRANTED: + case IPA_RM_RELEASED: + default: + goto bail; + } + + for (peers_index = 0; + peers_index < ipa_rm_peers_list_get_size( + consumer->resource.peers_list); + peers_index++) { + producer = ipa_rm_peers_list_get_resource(peers_index, + consumer->resource.peers_list); + if (producer) + ipa_rm_resource_producer_handle_cb( + (struct ipa_rm_resource_prod *) + producer, + event); + } + + return; +bail: + IPA_RM_DBG_LOW("%s new state: %d\n", + ipa_rm_resource_str(consumer->resource.name), + consumer->resource.state); +} + +/* + * ipa_rm_resource_set_perf_profile() - sets the performance profile to + * resource. + * + * @resource: [in] resource + * @profile: [in] profile to be set + * + * sets the profile to the given resource, In case the resource is + * granted, update bandwidth vote of the resource + */ +int ipa_rm_resource_set_perf_profile(struct ipa_rm_resource *resource, + struct ipa_rm_perf_profile *profile) +{ + int peers_index; + struct ipa_rm_resource *peer; + + if (!resource || !profile) { + IPA_RM_ERR("invalid params\n"); + return -EINVAL; + } + + if (profile->max_supported_bandwidth_mbps == resource->max_bw) { + IPA_RM_DBG_LOW("same profile\n"); + return 0; + } + + if ((resource->type == IPA_RM_PRODUCER && + (resource->state == IPA_RM_GRANTED || + resource->state == IPA_RM_REQUEST_IN_PROGRESS)) || + resource->type == IPA_RM_CONSUMER) { + for (peers_index = 0; + peers_index < ipa_rm_peers_list_get_size( + resource->peers_list); + peers_index++) { + peer = ipa_rm_peers_list_get_resource(peers_index, + resource->peers_list); + if (!peer) + continue; + peer->needed_bw -= resource->max_bw; + peer->needed_bw += + profile->max_supported_bandwidth_mbps; + if (peer->state == IPA_RM_GRANTED) + ipa_rm_perf_profile_change(peer->name); + } + } + + resource->max_bw = profile->max_supported_bandwidth_mbps; + if (resource->state == IPA_RM_GRANTED) + ipa_rm_perf_profile_change(resource->name); + + return 0; +} + + +/* + * ipa_rm_resource_producer_print_stat() - print the + * resource status and all his dependencies + * + * @resource: [in] Resource resource + * @buff: [in] The buf used to print + * @size: [in] Buf size + * + * Returns: number of bytes used on success, negative on failure + */ +int ipa_rm_resource_producer_print_stat( + struct ipa_rm_resource *resource, + char *buf, + int size) +{ + + int i; + int nbytes; + int cnt = 0; + struct ipa_rm_resource *consumer; + + if (!buf || size < 0) + return -EINVAL; + + nbytes = scnprintf(buf + cnt, size - cnt, + ipa_rm_resource_str(resource->name)); + cnt += nbytes; + nbytes = scnprintf(buf + cnt, size - cnt, "[%d, ", resource->max_bw); + cnt += nbytes; + + switch (resource->state) { + case IPA_RM_RELEASED: + nbytes = scnprintf(buf + cnt, size - cnt, + "Released] -> "); + cnt += nbytes; + break; + case IPA_RM_REQUEST_IN_PROGRESS: + nbytes = scnprintf(buf + cnt, size - cnt, + "Request In Progress] -> "); + cnt += nbytes; + break; + case IPA_RM_GRANTED: + nbytes = scnprintf(buf + cnt, size - cnt, + "Granted] -> "); + cnt += nbytes; + break; + case IPA_RM_RELEASE_IN_PROGRESS: + nbytes = scnprintf(buf + cnt, size - cnt, + "Release In Progress] -> "); + cnt += nbytes; + break; + default: + return -EPERM; + } + + for (i = 0; i < resource->peers_list->max_peers; ++i) { + consumer = + ipa_rm_peers_list_get_resource( + i, + resource->peers_list); + if (consumer) { + nbytes = scnprintf(buf + cnt, size - cnt, + ipa_rm_resource_str(consumer->name)); + cnt += nbytes; + nbytes = scnprintf(buf + cnt, size - cnt, "[%d, ", + consumer->max_bw); + cnt += nbytes; + + switch (consumer->state) { + case IPA_RM_RELEASED: + nbytes = scnprintf(buf + cnt, size - cnt, + "Released], "); + cnt += nbytes; + break; + case IPA_RM_REQUEST_IN_PROGRESS: + nbytes = scnprintf(buf + cnt, size - cnt, + "Request In Progress], "); + cnt += nbytes; + break; + case IPA_RM_GRANTED: + nbytes = scnprintf(buf + cnt, size - cnt, + "Granted], "); + cnt += nbytes; + break; + case IPA_RM_RELEASE_IN_PROGRESS: + nbytes = scnprintf(buf + cnt, size - cnt, + "Release In Progress], "); + cnt += nbytes; + break; + default: + return -EPERM; + } + } + } + nbytes = scnprintf(buf + cnt, size - cnt, "\n"); + cnt += nbytes; + + return cnt; +} diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_rm_resource.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_rm_resource.h new file mode 100644 index 0000000000..5ce500a4b4 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_rm_resource.h @@ -0,0 +1,159 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2013-2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _IPA_RM_RESOURCE_H_ +#define _IPA_RM_RESOURCE_H_ + +#include +#include "ipa.h" +#include "ipa_rm_peers_list.h" + +/** + * enum ipa_rm_resource_state - resource state + */ +enum ipa_rm_resource_state { + IPA_RM_RELEASED, + IPA_RM_REQUEST_IN_PROGRESS, + IPA_RM_GRANTED, + IPA_RM_RELEASE_IN_PROGRESS +}; + +/** + * enum ipa_rm_resource_type - IPA resource manager resource type + */ +enum ipa_rm_resource_type { + IPA_RM_PRODUCER, + IPA_RM_CONSUMER +}; + +/** + * struct ipa_rm_notification_info - notification information + * of IPA RM client + * @reg_params: registration parameters + * @explicit: registered explicitly by ipa_rm_register() + * @link: link to the list of all registered clients information + */ +struct ipa_rm_notification_info { + struct ipa_rm_register_params reg_params; + bool explicit; + struct list_head link; +}; + +/** + * struct ipa_rm_resource - IPA RM resource + * @name: name identifying resource + * @type: type of resource (PRODUCER or CONSUMER) + * @floor_voltage: minimum voltage level for operation + * @max_bw: maximum bandwidth required for resource in Mbps + * @state: state of the resource + * @peers_list: list of the peers of the resource + */ +struct ipa_rm_resource { + enum ipa_rm_resource_name name; + enum ipa_rm_resource_type type; + enum ipa_voltage_level floor_voltage; + u32 max_bw; + u32 needed_bw; + enum ipa_rm_resource_state state; + struct ipa_rm_peers_list *peers_list; +}; + +/** + * struct ipa_rm_resource_cons - IPA RM consumer + * @resource: resource + * @usage_count: number of producers in GRANTED / REQUESTED state + * using this consumer + * @request_consumer_in_progress: when set, the consumer is during its request + * phase + * @request_resource: function which should be called to request resource + * from resource manager + * @release_resource: function which should be called to release resource + * from resource manager + * Add new fields after @resource only. + */ +struct ipa_rm_resource_cons { + struct ipa_rm_resource resource; + int usage_count; + struct completion request_consumer_in_progress; + int (*request_resource)(void); + int (*release_resource)(void); +}; + +/** + * struct ipa_rm_resource_prod - IPA RM producer + * @resource: resource + * @event_listeners: clients registered with this producer + * for notifications in resource state + * list Add new fields after @resource only. + */ +struct ipa_rm_resource_prod { + struct ipa_rm_resource resource; + struct list_head event_listeners; + int pending_request; + int pending_release; +}; + +int ipa_rm_resource_create( + struct ipa_rm_create_params *create_params, + struct ipa_rm_resource **resource); + +int ipa_rm_resource_delete(struct ipa_rm_resource *resource); + +int ipa_rm_resource_producer_register(struct ipa_rm_resource_prod *producer, + struct ipa_rm_register_params *reg_params, + bool explicit); + +int ipa_rm_resource_producer_deregister(struct ipa_rm_resource_prod *producer, + struct ipa_rm_register_params *reg_params); + +int ipa_rm_resource_add_dependency(struct ipa_rm_resource *resource, + struct ipa_rm_resource *depends_on, + bool userspace_dep); + +int ipa_rm_resource_delete_dependency(struct ipa_rm_resource *resource, + struct ipa_rm_resource *depends_on, + bool userspace_dep); + +int ipa_rm_resource_producer_request(struct ipa_rm_resource_prod *producer); + +int ipa_rm_resource_producer_release(struct ipa_rm_resource_prod *producer); + +int ipa_rm_resource_consumer_request(struct ipa_rm_resource_cons *consumer, + u32 needed_bw, + bool inc_usage_count, + bool wake_client); + +int ipa_rm_resource_consumer_release(struct ipa_rm_resource_cons *consumer, + u32 needed_bw, + bool dec_usage_count); + +int ipa_rm_resource_set_perf_profile(struct ipa_rm_resource *resource, + struct ipa_rm_perf_profile *profile); + +void ipa_rm_resource_consumer_handle_cb(struct ipa_rm_resource_cons *consumer, + enum ipa_rm_event event); + +void ipa_rm_resource_producer_notify_clients( + struct ipa_rm_resource_prod *producer, + enum ipa_rm_event event, + bool notify_registered_only); + +int ipa_rm_resource_producer_print_stat( + struct ipa_rm_resource *resource, + char *buf, + int size); + +int ipa_rm_resource_consumer_request_work(struct ipa_rm_resource_cons *consumer, + enum ipa_rm_resource_state prev_state, + u32 needed_bw, + bool notify_completion, + bool dec_client_on_err); + +int ipa_rm_resource_consumer_release_work( + struct ipa_rm_resource_cons *consumer, + enum ipa_rm_resource_state prev_state, + bool notify_completion); + +#endif /* _IPA_RM_RESOURCE_H_ */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_test_module/ipa_rm_ut.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_test_module/ipa_rm_ut.c new file mode 100644 index 0000000000..07fc68ec75 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_test_module/ipa_rm_ut.c @@ -0,0 +1,404 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* +* Copyright (c) 2017, The Linux Foundation. All rights reserved. +*/ + +#include +#include +#include +#include "ipa.h" +#include +#include +#include "ipa_rm_ut.h" + +#define IPA_UT_DBG(x...) pr_err(x) + +/** + * enum ut_wq_cmd - workqueue commands + */ +enum ut_wq_cmd { + UT_WQ_REQ, + UT_WQ_REL +}; + +/** + * struct ipa_rm_ut_wq_work_type - IPA RM worqueue specific + * work type + * @work: work struct + * @wq_cmd: command that should be processed in workqueue context + * @resource_name: name of the resource on which this work + * should be done + * @dep_graph: data structure to search for resource if exists + * @event: event to notify + */ +struct ipa_rm_ut_wq_work_type { + struct work_struct work; + enum ut_wq_cmd wq_cmd; + enum ipa_rm_resource_name resource_name; + enum ipa_rm_event event; +}; + + + +static struct { + int (*add_dependency)(enum ipa_rm_resource_name + dependant_name, + enum ipa_rm_resource_name + dependency_name); + int (*resource_request)(enum ipa_rm_resource_name resource_name); + int (*resource_release)(enum ipa_rm_resource_name resource_name); + int (*consumer_cb)(enum ipa_rm_event, + enum ipa_rm_resource_name resource_name); + struct workqueue_struct *wq; +} ipa_rm_ut_cb; + +struct device_manager_type { + void *user_data; + ipa_rm_notify_cb notify_cb; + int (*release_function)(void); + int (*request_function)(void); +}; + +static void ipa_ut_wq_handler(struct work_struct *work); +int ipa_ut_wq_send_cmd(enum ut_wq_cmd wq_cmd, + enum ipa_rm_resource_name resource_name, + enum ipa_rm_event event); +static int usb_mgr_release_function(void); +static int usb_mgr_request_function(void); +static void usb_mgr_notify_function(void *user_data, + enum ipa_rm_event event, + unsigned long data); + +static struct device_manager_type usb_device_manager = { + NULL, + usb_mgr_notify_function, + usb_mgr_release_function, + usb_mgr_request_function +}; + +/* USB device manager */ +static int usb_mgr_release_function(void) +{ + IPA_UT_DBG("USB Released\n"); + IPA_UT_DBG("ASYNC CALL USB calling to IPA RM provided CB\n"); + ipa_ut_wq_send_cmd(UT_WQ_REL, + IPA_RM_RESOURCE_USB_CONS, + IPA_RM_RESOURCE_RELEASED); + + return -EINPROGRESS; +} + +static int usb_mgr_request_function(void) +{ + IPA_UT_DBG("USB Requested\n"); + IPA_UT_DBG("ASYNC CALL USB calling to IPA RM provided CB\n"); + ipa_ut_wq_send_cmd(UT_WQ_REQ, + IPA_RM_RESOURCE_USB_CONS, + IPA_RM_RESOURCE_GRANTED); + + return -EINPROGRESS; +} + +static void usb_mgr_notify_function(void *notify_cb_data, + enum ipa_rm_event event, + unsigned long data) +{ + IPA_UT_DBG("USB got event [%d]\n", event); +} + +/* HSIC device manager */ +static int hsic_mgr_release_function(void) +{ + int result = 0; + IPA_UT_DBG("HSIC Released\n"); + IPA_UT_DBG("HSIC calling to IPA RM provided CB\n"); + result = ipa_rm_ut_cb.consumer_cb(IPA_RM_RESOURCE_RELEASED, + IPA_RM_RESOURCE_HSIC_CONS); + + return -EINPROGRESS; +} + +static int hsic_mgr_request_function(void) +{ + int result = 0; + IPA_UT_DBG("HSIC Requested\n"); + IPA_UT_DBG("HSIC calling to IPA RM provided CB\n"); + result = ipa_rm_ut_cb.consumer_cb(IPA_RM_RESOURCE_GRANTED, + IPA_RM_RESOURCE_HSIC_CONS); + + return -EINPROGRESS; +} + +static void hsic_notify_function(void *notify_cb_data, + enum ipa_rm_event event, + unsigned long data) +{ + IPA_UT_DBG("HSIC got event [%d]\n", event); +} + +static struct device_manager_type hsic_device_manager = { + NULL, + hsic_notify_function, + hsic_mgr_release_function, + hsic_mgr_request_function +}; + +static void rmnet_bridge_mgr_notify_function + (void *notify_cb_data, + enum ipa_rm_event event, + unsigned long data) +{ + IPA_UT_DBG("RmNet got event [%d]\n", event); +} + +static struct device_manager_type rmnet_bridge_device_manager = { + NULL, + rmnet_bridge_mgr_notify_function, + NULL, + NULL +}; + + +static void ipa_ut_wq_handler(struct work_struct *work) +{ + enum ut_wq_cmd ut_cmd; + struct ipa_rm_ut_wq_work_type *ipa_rm_work = + (struct ipa_rm_ut_wq_work_type *)work; + if (!ipa_rm_work) + return; + ut_cmd = (enum ut_wq_cmd)ipa_rm_work->wq_cmd; + IPA_UT_DBG("***UT CMD Q command [%d]\n", ut_cmd); + switch (ut_cmd) { + case UT_WQ_REQ: + switch (ipa_rm_work->resource_name) { + case IPA_RM_RESOURCE_USB_CONS: + IPA_UT_DBG + ("***calling to USB consumer notify request CB\n"); + ipa_rm_ut_cb.consumer_cb(IPA_RM_RESOURCE_GRANTED, + IPA_RM_RESOURCE_USB_CONS); + break; + case IPA_RM_RESOURCE_HSIC_CONS: + break; + default: + return; + } + break; + case UT_WQ_REL: + switch (ipa_rm_work->resource_name) { + case IPA_RM_RESOURCE_USB_CONS: + IPA_UT_DBG + ("***calling to USB consumer notify release CB\n"); + ipa_rm_ut_cb.consumer_cb(IPA_RM_RESOURCE_RELEASED, + IPA_RM_RESOURCE_USB_CONS); + break; + case IPA_RM_RESOURCE_HSIC_CONS: + break; + default: + return; + } + break; + default: + break; + } + + kfree((void *) work); +} + +int ipa_ut_wq_send_cmd(enum ut_wq_cmd wq_cmd, + enum ipa_rm_resource_name resource_name, + enum ipa_rm_event event) +{ + int result = 0; + struct ipa_rm_ut_wq_work_type *work = + (struct ipa_rm_ut_wq_work_type *) + kzalloc(sizeof(*work), GFP_KERNEL); + if (work) { + INIT_WORK((struct work_struct *)work, ipa_ut_wq_handler); + work->wq_cmd = (enum ut_wq_cmd) wq_cmd; + work->resource_name = resource_name; + work->event = event; + result = queue_work(ipa_rm_ut_cb.wq, + (struct work_struct *)work); + } else { + result = -ENOMEM; + } + return result; +} + +/** + * build_rmnet_bridge_use_case_graph() - simulate resource creation + * + * @create_resource: create resource function provided by ipa_rm + * unit under test + * @consumer_cb: consumer CB function provided by ipa_rm + * unit under test + * + * Returns: 0 on success, negative on failure + */ +int build_rmnet_bridge_use_case_graph( + int (*create_resource) + (struct ipa_rm_create_params *create_params), + int (*consumer_cb)(enum ipa_rm_event event, + enum ipa_rm_resource_name resource_name)) +{ + int result = 0; + struct ipa_rm_create_params create_params = {0}; + + IPA_UT_DBG("build_rmnet_bridge_use_case_graph ENTER\n"); + + ipa_rm_ut_cb.consumer_cb = consumer_cb; + + /* create USB PROD */ + create_params.name = IPA_RM_RESOURCE_USB_PROD; + create_params.reg_params.notify_cb = + usb_device_manager.notify_cb; + create_params.reg_params.user_data = + usb_device_manager.user_data; + result = create_resource(&create_params); + if (result) + goto bail; + + /* create USB CONS */ + create_params.name = IPA_RM_RESOURCE_USB_CONS; + create_params.release_resource = + usb_device_manager.release_function; + create_params.request_resource = + usb_device_manager.request_function; + result = create_resource(&create_params); + if (result) + goto bail; + + /* create HSIC PROD */ + create_params.name = IPA_RM_RESOURCE_HSIC_PROD; + create_params.reg_params.notify_cb = + hsic_device_manager.notify_cb; + create_params.reg_params.user_data = + hsic_device_manager.user_data; + result = create_resource(&create_params); + if (result) + goto bail; + + /* create HSIC CONS */ + create_params.name = IPA_RM_RESOURCE_HSIC_CONS; + create_params.release_resource = + hsic_device_manager.release_function; + create_params.request_resource = + hsic_device_manager.request_function; + result = create_resource(&create_params); + if (result) + goto bail; + + /* BRIDGE PROD */ + create_params.name = IPA_RM_RESOURCE_WWAN_0_PROD; + create_params.reg_params.notify_cb = + rmnet_bridge_device_manager.notify_cb; + create_params.reg_params.user_data = + rmnet_bridge_device_manager.user_data; + result = create_resource(&create_params); + if (result) + goto bail; + + ipa_rm_ut_cb.wq = create_singlethread_workqueue("ut_wq"); + if (!ipa_rm_ut_cb.wq) { + result = -ENOMEM; + goto bail; + } + + IPA_UT_DBG("build_rmnet_bridge_use_case_graph EXIT SUCCESS\n"); + +bail: + + return result; +} + +/** + * build_rmnet_bridge_use_case_dependencies() - simulate build + * dependency graph process + * @add_dependency: add dependency function provided by ipa_rm + * unit under test + * + * Returns: 0 on success, negative on failure + */ +int build_rmnet_bridge_use_case_dependencies( + int (*add_dependency) + (enum ipa_rm_resource_name dependant_name, + enum ipa_rm_resource_name dependency_name)) +{ + int result = 0; + + IPA_UT_DBG("build_rmnet_bridge_use_case_dependencies ENTER\n"); + + ipa_rm_ut_cb.add_dependency = add_dependency; + + result = add_dependency(IPA_RM_RESOURCE_USB_PROD, + IPA_RM_RESOURCE_HSIC_CONS); + if (result) + goto bail; + result = add_dependency(IPA_RM_RESOURCE_HSIC_PROD, + IPA_RM_RESOURCE_USB_CONS); + if (result) + goto bail; + result = add_dependency(IPA_RM_RESOURCE_WWAN_0_PROD, + IPA_RM_RESOURCE_HSIC_CONS); + if (result) + goto bail; + result = add_dependency(IPA_RM_RESOURCE_WWAN_0_PROD, + IPA_RM_RESOURCE_USB_CONS); + + if (result) + goto bail; + +bail: + IPA_UT_DBG( + "build_rmnet_bridge_use_case_dependencies EXIT result [%d]\n", + result); + return result; +} + +/** + * request_release_resource_sequence() - simulate request / release + * resource sequence + * @resource_request: request resource function provided by ipa_rm + * unit under test + * @resource_release: release resource function provided by ipa_rm + * unit under test + * + * Returns: 0 on success, negative on failure + */ +int request_release_resource_sequence( + int (*resource_request) + (enum ipa_rm_resource_name resource_name), + int (*resource_release) + (enum ipa_rm_resource_name resource_name)) +{ + int result = 0; + ipa_rm_ut_cb.resource_request = resource_request; + ipa_rm_ut_cb.resource_release = resource_release; + + IPA_UT_DBG("request_release_resource_sequence ENTER\n"); + + result = resource_request(IPA_RM_RESOURCE_USB_PROD); + IPA_UT_DBG("result [%d]\n", result); + result = resource_request(IPA_RM_RESOURCE_HSIC_PROD); + IPA_UT_DBG("result [%d]\n", result); + + result = resource_release(IPA_RM_RESOURCE_USB_PROD); + IPA_UT_DBG("result [%d]\n", result); + result = resource_release(IPA_RM_RESOURCE_HSIC_PROD); + IPA_UT_DBG("result [%d]\n", result); + + IPA_UT_DBG("request_release_resource_sequence EXIT SUCCESS\n"); + return result; +} + +/** + * clean_ut() - free unit test module resources + * + */ +void clean_ut(void) +{ + IPA_UT_DBG("clean_ut ENTER\n"); + if (ipa_rm_ut_cb.wq) + destroy_workqueue(ipa_rm_ut_cb.wq); + IPA_UT_DBG("clean_ut EXIT SUCCESS\n"); +} diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_test_module/ipa_rm_ut.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_test_module/ipa_rm_ut.h new file mode 100644 index 0000000000..0fb7d3fc08 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_test_module/ipa_rm_ut.h @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* +* Copyright (c) 2017, The Linux Foundation. All rights reserved. +*/ + +#ifndef _IPA_RM_UT_H_ +#define _IPA_RM_UT_H_ + +/** + * ipa_rm_ut - unit test module + * Defines sanity test scenarios executed from debugfs + * writer function defined in ipa_rm module + */ + +#include +#include "ipa.h" + +int build_rmnet_bridge_use_case_graph( + int (*create_resource)(struct ipa_rm_create_params *create_params), + int (*consumer_cb)(enum ipa_rm_event event, + enum ipa_rm_resource_name resource_name)); + +int build_rmnet_bridge_use_case_dependencies( + int (*add_dependency)(enum ipa_rm_resource_name dependant_name, + enum ipa_rm_resource_name dependency_name)); +int request_release_resource_sequence( + int (*resource_request)(enum ipa_rm_resource_name resource_name), + int (*resource_release)(enum ipa_rm_resource_name resource_name)); + +void clean_ut(void); + +#endif /* _IPA_RM_UT_H_ */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_test_module/ipa_test_module.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_test_module/ipa_test_module.h new file mode 100644 index 0000000000..96bdf69599 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_test_module/ipa_test_module.h @@ -0,0 +1,221 @@ +// SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note +/* +* Copyright (c) 2017-2018,2020-2021, The Linux Foundation. All rights reserved. +* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. +*/ + +#ifndef _IPA_TEST_MODULE_H_ +#define _IPA_TEST_MODULE_H_ + +#include +#include +#include +#ifdef _KERNEL_ +#include "ipa.h" +#endif + +#define IPA_TEST_IOC_MAGIC 0xA5 +enum { + IPA_TEST_IOCTL_GET_HW_TYPE = 1, + IPA_TEST_IOCTL_CONFIGURE, + IPA_TEST_IOCTL_CLEAN, + IPA_TEST_IOCTL_EP_CTRL, + IPA_TEST_IOCTL_REG_SUSPEND_HNDL, + IPA_TEST_IOCTL_HOLB_CONFIG, + IPA_TEST_IOCTL_FLT_TBL_IN_SRAM, + IPA_TEST_IOCTL_GET_MEM_PART, + IPA_TEST_IOCTL_ULSO_CONFIGURE, + IPA_TEST_IOCTL_ADD_HDR_HPC, + IPA_TEST_IOCTL_PKT_INIT_EX_SET_HDR_OFST, + IPA_TEST_IOCTL_NUM, +}; + +#define IPA_TEST_IOC_GET_HW_TYPE _IO(IPA_TEST_IOC_MAGIC, \ + IPA_TEST_IOCTL_GET_HW_TYPE) +#define IPA_TEST_IOC_CONFIGURE _IOWR(IPA_TEST_IOC_MAGIC, \ + IPA_TEST_IOCTL_CONFIGURE, \ + struct ipa_test_config_header *) +#define IPA_TEST_IOC_CLEAN _IO(IPA_TEST_IOC_MAGIC, \ + IPA_TEST_IOCTL_CLEAN) +#define IPA_TEST_IOC_EP_CTRL _IOWR(IPA_TEST_IOC_MAGIC, \ + IPA_TEST_IOCTL_EP_CTRL, \ + struct ipa_test_ep_ctrl *) +#define IPA_TEST_IOC_REG_SUSPEND_HNDL _IOWR(IPA_TEST_IOC_MAGIC, \ + IPA_TEST_IOCTL_REG_SUSPEND_HNDL, \ + struct ipa_test_reg_suspend_handler *) +#define IPA_TEST_IOC_HOLB_CONFIG _IOWR(IPA_TEST_IOC_MAGIC, \ + IPA_TEST_IOCTL_HOLB_CONFIG, \ + struct handle_holb_config_ioctl *) +#define IPA_TEST_IOC_IS_TEST_PROD_FLT_IN_SRAM _IO(IPA_TEST_IOC_MAGIC, \ + IPA_TEST_IOCTL_FLT_TBL_IN_SRAM) +#define IPA_TEST_IOC_GET_MEM_PART _IOWR(IPA_TEST_IOC_MAGIC, \ + IPA_TEST_IOCTL_GET_MEM_PART, \ + struct ipa_test_mem_partition *) +#define IPA_TEST_IOC_ULSO_CONFIGURE _IOWR(IPA_TEST_IOC_MAGIC, \ + IPA_TEST_IOCTL_ULSO_CONFIGURE, \ + struct ipa_test_config_header *) +#define IPA_TEST_IOC_ADD_HDR_HPC _IOWR(IPA_TEST_IOC_MAGIC, \ + IPA_TEST_IOCTL_ADD_HDR_HPC, \ + struct ipa_ioc_add_hdr *) +#define IPA_TEST_IOC_PKT_INIT_EX_SET_HDR_OFST _IOWR(IPA_TEST_IOC_MAGIC, \ + IPA_TEST_IOCTL_PKT_INIT_EX_SET_HDR_OFST, \ + struct ipa_ioc_set_pkt_init_ex_hdr_ofst *) + +#define IPA_TEST_CONFIG_MARKER 0x57 +#define IPA_TEST_CHANNEL_CONFIG_MARKER 0x83 + +/* + * This is the configuration number that is saved for Generic configuration + * we need it in order to allow coexistence of Generic + * configured tests with old fashion tests + */ +#define GENERIC_TEST_CONFIGURATION_IDX 37788239 + +struct ipa_test_config_header +{ + unsigned char head_marker; /* IPA_TEST_CONFIG_MARKER */ + int to_ipa_channels_num; + struct ipa_channel_config **to_ipa_channel_config; + int from_ipa_channels_num; + struct ipa_channel_config **from_ipa_channel_config; + unsigned char tail_marker; /* IPA_TEST_CONFIG_MARKER */ +}; + +struct ipa_test_en_status +{ + int num_clients; + enum ipa_client_type *clients; +}; + +struct ipa_test_ep_ctrl +{ + bool ipa_ep_suspend; + bool ipa_ep_delay; + int from_dev_num; +}; + +struct ipa_test_reg_suspend_handler +{ + int DevNum; + bool reg; + bool deferred_flag; +}; + +struct ipa_channel_config +{ + unsigned char head_marker; /* IPA_TEST_CHANNEL_CONFIG_MARKER */ + enum ipa_client_type client; + int index; /* shall be used for to_ipa_x or from_ipa_x */ + size_t config_size; + void *cfg; + bool en_status; + unsigned char tail_marker; /* IPA_TEST_CHANNEL_CONFIG_MARKER */ +}; + +struct ipa_test_holb_config +{ + enum ipa_client_type client; + unsigned tmr_val; + unsigned short en; +}; + +struct ipa_test_mem_partition { + unsigned ofst_start; + unsigned v4_flt_hash_ofst; + unsigned v4_flt_hash_size; + unsigned v4_flt_hash_size_ddr; + unsigned v4_flt_nhash_ofst; + unsigned v4_flt_nhash_size; + unsigned v4_flt_nhash_size_ddr; + unsigned v6_flt_hash_ofst; + unsigned v6_flt_hash_size; + unsigned v6_flt_hash_size_ddr; + unsigned v6_flt_nhash_ofst; + unsigned v6_flt_nhash_size; + unsigned v6_flt_nhash_size_ddr; + unsigned v4_rt_num_index; + unsigned v4_modem_rt_index_lo; + unsigned v4_modem_rt_index_hi; + unsigned v4_apps_rt_index_lo; + unsigned v4_apps_rt_index_hi; + unsigned v4_rt_hash_ofst; + unsigned v4_rt_hash_size; + unsigned v4_rt_hash_size_ddr; + unsigned v4_rt_nhash_ofst; + unsigned v4_rt_nhash_size; + unsigned v4_rt_nhash_size_ddr; + unsigned v6_rt_num_index; + unsigned v6_modem_rt_index_lo; + unsigned v6_modem_rt_index_hi; + unsigned v6_apps_rt_index_lo; + unsigned v6_apps_rt_index_hi; + unsigned v6_rt_hash_ofst; + unsigned v6_rt_hash_size; + unsigned v6_rt_hash_size_ddr; + unsigned v6_rt_nhash_ofst; + unsigned v6_rt_nhash_size; + unsigned v6_rt_nhash_size_ddr; + unsigned modem_hdr_ofst; + unsigned modem_hdr_size; + unsigned apps_hdr_ofst; + unsigned apps_hdr_size; + unsigned apps_hdr_size_ddr; + unsigned modem_hdr_proc_ctx_ofst; + unsigned modem_hdr_proc_ctx_size; + unsigned apps_hdr_proc_ctx_ofst; + unsigned apps_hdr_proc_ctx_size; + unsigned apps_hdr_proc_ctx_size_ddr; + unsigned nat_tbl_ofst; + unsigned nat_tbl_size; + unsigned modem_comp_decomp_ofst; + unsigned modem_comp_decomp_size; + unsigned modem_ofst; + unsigned modem_size; + unsigned apps_v4_flt_hash_ofst; + unsigned apps_v4_flt_hash_size; + unsigned apps_v4_flt_nhash_ofst; + unsigned apps_v4_flt_nhash_size; + unsigned apps_v6_flt_hash_ofst; + unsigned apps_v6_flt_hash_size; + unsigned apps_v6_flt_nhash_ofst; + unsigned apps_v6_flt_nhash_size; + unsigned uc_info_ofst; + unsigned uc_info_size; + unsigned end_ofst; + unsigned apps_v4_rt_hash_ofst; + unsigned apps_v4_rt_hash_size; + unsigned apps_v4_rt_nhash_ofst; + unsigned apps_v4_rt_nhash_size; + unsigned apps_v6_rt_hash_ofst; + unsigned apps_v6_rt_hash_size; + unsigned apps_v6_rt_nhash_ofst; + unsigned apps_v6_rt_nhash_size; + unsigned uc_descriptor_ram_ofst; + unsigned uc_descriptor_ram_size; + unsigned pdn_config_ofst; + unsigned pdn_config_size; + unsigned stats_quota_q6_ofst; + unsigned stats_quota_q6_size; + unsigned stats_quota_ap_ofst; + unsigned stats_quota_ap_size; + unsigned stats_tethering_ofst; + unsigned stats_tethering_size; + unsigned stats_fnr_ofst; + unsigned stats_fnr_size; + unsigned uc_ofst; + unsigned uc_size; + + /* Irrelevant starting IPA4.5 */ + unsigned stats_flt_v4_ofst; + unsigned stats_flt_v4_size; + unsigned stats_flt_v6_ofst; + unsigned stats_flt_v6_size; + unsigned stats_rt_v4_ofst; + unsigned stats_rt_v4_size; + unsigned stats_rt_v6_ofst; + unsigned stats_rt_v6_size; + + unsigned stats_drop_ofst; + unsigned stats_drop_size; +}; +#endif /* _IPA_TEST_MODULE_H_ */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_test_module/ipa_test_module_impl.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_test_module/ipa_test_module_impl.c new file mode 100644 index 0000000000..ddf141c9ea --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_test_module/ipa_test_module_impl.c @@ -0,0 +1,4857 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* +* Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. +* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. +*/ + +#include /* u32 */ +#include /* pr_debug() */ +#include /* kzalloc() */ +#include /* mutex */ +#include /* list_head */ +#include /* msleep */ +#include /* memset */ +#include /* device */ +#include /* cdev_alloc() */ +#include /* alloc_chrdev_region() */ +#include /* module_init() */ +#include /* dma_alloc_coherent() */ +#include +#include +#include "ipa.h" +#include +#include /* sk_buff */ +#include /* Kernel FIFO Implementation */ +#include /* msleep() */ +#include +#include +#include +#include "gsi.h" +#include "ipa_i.h" +#include "ipa_rm_ut.h" +#include "ipa_test_module.h" + +#ifdef INIT_COMPLETION +#define reinit_completion(x) INIT_COMPLETION(*(x)) +#endif /* INIT_COMPLETION */ + + +/** Module name string */ +#define IPA_TEST_DRV_NAME "ipa_test" + +//#define IPA_SUMMING_THRESHOLD 0x10 +#define IPA_EVENT_THRESHOLD 0x10 +#define IPA_NUM_PIPES 0x24 + +#define TEST_SIGNATURE 0xfacecafe +#define DFAB_ARB1_HCLK_CTL (MSM_CLK_CTL_BASE + 0x2564) + +#define DESC_FIFO_SZ 0x100 +#define DATA_FIFO_SZ 0x2000 + +#define GSI_CHANNEL_RING_LEN 4096 +#define GSI_EVT_RING_LEN 4096 + +#define TX_NUM_BUFFS 16 +#define TX_SZ 32768 +#define TX_BUFF_SIZE ((TX_SZ)/(TX_NUM_BUFFS)) + +#define RX_NUM_BUFFS 16 +#define RX_SZ 32768 +/* Lowest power of 2 that is bigger than what is used in Ulso test */ +#define MAX_ULSO_SEGMENT_SZ 16384 +#define RX_SZ_ULSO ((MAX_ULSO_SEGMENT_SZ) * (RX_NUM_BUFFS)) +#define RX_BUFF_SIZE ((rx_size)/(RX_NUM_BUFFS)) + +#define IPA_TEST_DMUX_HEADER_LENGTH 8 +#define IPA_TEST_META_DATA_IS_VALID 1 +#define IPA_TEST_DMUX_HEADER_META_DATA_OFFSET 4 + +#define IPA_TEST_ADDITIONAL_HDR_LEN 4 + +#define IPA_TEST_META_DATA_OFFSET_NONE 0 + +#define IPA_TEST_HDI_802_HEADER_LENGTH 22 +#define IPA_TEST_HDI_802_LENGTH_FIELD_OFFSET 11 +#define IPA_TEST_HDI_802_LENGTH_FIELD_OFFSET_VALID 1 +#define IPA_TEST_HDI_802_ADD_CONST_LENGTH 0 + +#define IPA_TEST_HDI_RMNET_HEADER_LENGTH 6 +#define IPA_TEST_HDI_RMNET_LENGTH_FIELD_OFFSET 0 +#define IPA_TEST_HDI_RMNET_LENGTH_FIELD_OFFSET_VALID 0 +#define IPA_TEST_HDI_RMNET_ADD_CONST_LENGTH 0 + +/* Settings of Exception Handling */ +#define RX_DESCRIPTOR_SIZE 2048 +#define EXCEPTION_DRV_NAME "ipa_exception_pipe" +#define EXCEPTION_KFIFO_SIZE (8) +#define EXCEPTION_KFIFO_SLEEP_MS (EXCEPTION_KFIFO_SLEEP_MS) +#define EXCEPTION_KFIFO_DEBUG_VERBOSE 1 + +#define IPATEST_DBG(fmt, args...) \ + do { \ + pr_debug(IPA_TEST_DRV_NAME " %s:%d " fmt, __func__, __LINE__, ## args);\ + } while (0) + +#define IPATEST_ERR(fmt, args...) \ + do { \ + pr_err(IPA_TEST_DRV_NAME " %s:%d " fmt, __func__, __LINE__, ## args);\ + } while (0) + +#define IPATEST_DUMP(fmt, args...) \ + do { \ + pr_debug(fmt, ## args);\ + } while (0) + +int ipa_sys_setup(struct ipa_sys_connect_params *sys_in, + unsigned long *ipa_gsi_hdl, + u32 *ipa_pipe_num, u32 *clnt_hdl, bool en_status); +int ipa_sys_teardown(u32 clnt_hdl); +int ipa_sys_update_gsi_hdls(u32 clnt_hdl, unsigned long gsi_ch_hdl, + unsigned long gsi_ev_hdl); +struct device *ipa_get_pdev(void); +enum fops_type { + IPA_TEST_REG_CHANNEL, + IPA_TEST_DATA_PATH_TEST_CHANNEL, + IPA_TEST_ULSO_DATA_PATH_TEST_CHANNEL, + MAX_FOPS +}; + +struct notify_cb_data_st { + struct kfifo_rec_ptr_2 exception_kfifo; +}; + +struct exception_hdl_data { + struct class *class; + struct device *dev; + struct cdev *p_cdev; + dev_t dev_num; + struct notify_cb_data_st notify_cb_data; +}; + +/*struct exception_hdl_data *p_exception_hdl_data = NULL;*/ +struct exception_hdl_data *p_exception_hdl_data; + +struct ipa_dma_chan { + u32 dest_pipe_index; + u32 src_pipe_index; +}; + +/** + * This struct specifies memory buffer properties. + * + * @base - Buffer virtual address. + * @phys_base - Buffer physical address. + * @size - Specifies buffer size (or maximum size). + * + */ +//struct ipa_mem_buffer { +// void *base; +// phys_addr_t phys_base; +// u32 size; +//}; + +struct test_endpoint_sys { + struct completion xfer_done; /*A completion object for end transfer*/ + struct gsi_chan_props gsi_channel_props; + struct gsi_evt_ring_props gsi_evt_ring_props; + bool gsi_valid; + unsigned long gsi_chan_hdl; + unsigned long gsi_evt_ring_hdl; +}; + +#define MAX_CHANNEL_NAME (20) + +/* A channel device is the representation of the flow of data from APPS + to IPA and vice versa. */ +struct channel_dev { + /*OS structures for representation of a channel.*/ + struct class *class; + dev_t dev_num; + struct device *dev; + struct cdev cdev; + + /*The representation of the connection from APPS to GSI/IPA*/ + struct test_endpoint_sys ep; + /*The representation of the connection from GSI to IPA*/ + struct ipa_dma_chan dma_ep; + /*The data FIFO for the APPS to IPA*/ + struct ipa_mem_buffer mem; + /*Index of the next available buffer to use under mem.buff*/ + int mem_buff_index; + /*A pointer to the test context - should be deleted - TODO*/ + struct test_context *test; + + int index;/*to_ipa_/from_ipa_*/ + char name[MAX_CHANNEL_NAME]; + int rx_pool_inited;/*check... - should be moved to contex?*/ + int ipa_client_hdl;/*returned from ipa_connect*/ +}; + +#define MAX_CHANNEL_DEVS (10) +static struct channel_dev *to_ipa_devs[MAX_CHANNEL_DEVS/2]; +/*TODO - legacy*/ +static struct channel_dev *from_ipa_devs[MAX_CHANNEL_DEVS/2]; + +/*This structure holds all the data required for the test module.*/ +struct test_context { + + /*OS structures for representation of the test module.*/ + dev_t dev_num; + struct device *dev; + struct cdev *cdev; + + /*All channels that are used to read data from + * the IPA(Receive channel)*/ + struct channel_dev *rx_channels[MAX_CHANNEL_DEVS/2]; + + /*All channels that are used to write data + * to the IPA(Transmit channel)*/ + struct channel_dev *tx_channels[MAX_CHANNEL_DEVS/2]; + int num_rx_channels; + int num_tx_channels; + + /*current test case(-EINVAL is for not-configured)TODO*/ + s32 configuration_idx; + s32 current_configuration_idx; + + u32 signature;/*Legacy*/ +}; + +/** + * struct ipa_tx_suspend_private_data - private data for IPA_TX_SUSPEND_IRQ use + * @clnt_hdl: client handle assigned by IPA + */ +struct ipa_tx_suspend_private_data { + u32 clnt_hdl; + u32 gsi_chan_hdl; +}; + +static struct test_context *ipa_test; + +static size_t rx_size; + + +/** + * Allocate memory from system memory. + * + * @param mem + */ +static void test_alloc_mem(struct ipa_mem_buffer *mem) +{ + dma_addr_t dma_addr; + struct device *pdev; + + pdev = ipa3_get_pdev(); + /* need to check return value in formal code */ + if (pdev != NULL) { + mem->base = dma_alloc_coherent(pdev, mem->size, &dma_addr, GFP_KERNEL); + mem->phys_base = dma_addr; + } +} + +/** + * Free memory from system memory. + * + * @param mem + */ +static void test_free_mem(struct ipa_mem_buffer *mem) +{ + dma_addr_t dma_addr = mem->phys_base; + struct device *pdev; + + pdev = ipa3_get_pdev(); + if (dma_addr && pdev != NULL) + dma_free_coherent(pdev, mem->size, mem->base, dma_addr); + + mem->phys_base = 0; + mem->base = NULL; +} + +void print_buff(void *data, size_t size) +{ + u8 bytes_in_line = 16; + int i, j, num_lines; + char str[256], tmp[4]; + + num_lines = size / bytes_in_line; + if (size % bytes_in_line > 0) + num_lines++; + + IPATEST_DBG("Printing buffer at address 0x%px, size = %zu:\n" + , data, size); + for (i = 0; i < num_lines; i++) { + str[0] = '\0'; + for (j = 0; (j < bytes_in_line) && + ((i * bytes_in_line + j) < size); j++) { + snprintf(tmp, sizeof(tmp), "%02x ", + ((unsigned char *)data) + [i * bytes_in_line + j]); + strlcat(str, tmp, sizeof(str)); + } + IPATEST_DUMP(": %s\n", str); + } +} + +static int channel_open(struct inode *inode, struct file *filp) +{ + struct channel_dev *channel_dev; + + /* Get the channel device data */ + channel_dev = container_of(inode->i_cdev, struct channel_dev, cdev); + + IPATEST_DBG("channel_dev address = 0x%px\n", channel_dev); + + filp->private_data = channel_dev; + + return 0; +} + +int insert_descriptors_into_rx_endpoints(u32 count) +{ + struct channel_dev *rx_channel = NULL; + int i, j, res = 0; + + /* Insert a descriptor into the receiving end(s) */ + for (i = 0; i < ipa_test->num_rx_channels; i++) { + rx_channel = ipa_test->rx_channels[i]; + if (!rx_channel->rx_pool_inited) { + res = 0; + for (j = 0; j < RX_NUM_BUFFS; j++) { + struct gsi_xfer_elem gsi_xfer; + + memset(&gsi_xfer, 0, sizeof(gsi_xfer)); + gsi_xfer.addr = rx_channel->mem.phys_base + j * count; + gsi_xfer.flags |= GSI_XFER_FLAG_EOT; + gsi_xfer.len = count; + gsi_xfer.type = GSI_XFER_ELEM_DATA; + gsi_xfer.xfer_user_data = (void*)(rx_channel->mem.phys_base + j * count); + + IPATEST_DBG("submitting credit to gsi\n"); + res |= gsi_queue_xfer(rx_channel->ep.gsi_chan_hdl, 1, &gsi_xfer, true); + if (res) { + IPATEST_ERR("gsi_queue_xfer failed %d\n", res); + return -EFAULT; + } + } + + if (res == 0) + rx_channel->rx_pool_inited = 1; + } + } + + return res; +} + +static ssize_t channel_write_gsi(struct file *filp, const char __user *buf, + size_t count, loff_t *f_pos) +{ + struct channel_dev *channel_dev = filp->private_data; + int res = 0; + void *data_address = channel_dev->mem.base + + channel_dev->mem_buff_index * TX_BUFF_SIZE; + u64 data_phys_addr = channel_dev->mem.phys_base + + channel_dev->mem_buff_index * TX_BUFF_SIZE; + struct gsi_xfer_elem gsi_xfer; + + if (count > (RX_BUFF_SIZE)) + IPATEST_ERR("-----PROBLEM----- count=%zu RX_BUFF_SIZE=%d\n", + count, RX_BUFF_SIZE); + + /* Copy the data from the user and transmit */ + res = copy_from_user(data_address, buf, count); + if (res) { + IPATEST_ERR("copy_from_user() failure.\n"); + return -EINVAL; + } + + /* Print the data */ + print_buff(data_address, count); + + IPATEST_DBG("-----Start Transfer-----\n"); + + /* Transmit */ + memset(&gsi_xfer, 0, sizeof(gsi_xfer)); + gsi_xfer.addr = data_phys_addr; + gsi_xfer.flags |= GSI_XFER_FLAG_EOT; + gsi_xfer.len = count; + gsi_xfer.type = GSI_XFER_ELEM_DATA; + + IPATEST_DBG("sending a packet to gsi\n"); + res = gsi_queue_xfer(channel_dev->ep.gsi_chan_hdl, 1, &gsi_xfer, true); + if (res != GSI_STATUS_SUCCESS) { + IPATEST_ERR("GSI xfer failed %d\n", res); + return res; + } + + channel_dev->mem_buff_index = (channel_dev->mem_buff_index + 1) % + TX_NUM_BUFFS; + return count; +} + +static ssize_t channel_read_gsi(struct file *filp, char __user *buf, + size_t count, loff_t *f_pos) +{ + struct channel_dev *channel_dev = filp->private_data; + int res = 0; + int i; + phys_addr_t offset = 0; + struct gsi_chan_xfer_notify xfer_notify; + int max_retry = 10; + struct gsi_xfer_elem gsi_xfer; + + IPATEST_DBG("size to read = %zu\n", count); + for (i = 0; i < max_retry; i++) { + res = gsi_poll_channel(channel_dev->ep.gsi_chan_hdl, + &xfer_notify); + + if (res != GSI_STATUS_SUCCESS && res != GSI_STATUS_POLL_EMPTY) { + IPATEST_ERR("gsi_poll_channel failed %d\n", res); + return res; + } + if (res == GSI_STATUS_SUCCESS) + break; + + IPATEST_DBG("channel empty %d/%d\n", i + 1, max_retry); + msleep(1000); + } + + if (i == max_retry) { + IPATEST_ERR("transfer not completed.\n"); + return 0; + } + + IPATEST_DBG("received %d bytes from 0x%px.\n", + xfer_notify.bytes_xfered, xfer_notify.xfer_user_data); + + /* Copy the received data to the user buffer */ + offset = (phys_addr_t)xfer_notify.xfer_user_data - channel_dev->mem.phys_base; + res = copy_to_user(buf, + channel_dev->mem.base + offset, + xfer_notify.bytes_xfered); + if (res < 0) { + IPATEST_ERR("copy_to_user() failed.\n"); + return 0; + } + + /* Re-insert the descriptor back to pipe */ + memset(&gsi_xfer, 0, sizeof(gsi_xfer)); + gsi_xfer.addr = (phys_addr_t)xfer_notify.xfer_user_data; + gsi_xfer.flags |= GSI_XFER_FLAG_EOT; + gsi_xfer.len = RX_BUFF_SIZE; + gsi_xfer.type = GSI_XFER_ELEM_DATA; + gsi_xfer.xfer_user_data = xfer_notify.xfer_user_data; + + IPATEST_DBG("submitting credit to gsi\n"); + res = gsi_queue_xfer(channel_dev->ep.gsi_chan_hdl, 1, &gsi_xfer, true); + if (res) { + IPATEST_ERR("gsi_queue_xfer failed %d\n", res); + return 0; + } + + msleep(20); + + IPATEST_DBG("Returning %d.\n", xfer_notify.bytes_xfered); + return xfer_notify.bytes_xfered; +} + +static ssize_t channel_write(struct file *filp, const char __user *buf, + size_t count, loff_t *f_pos) +{ + return channel_write_gsi(filp, buf, count, f_pos); +} + +static ssize_t channel_read(struct file *filp, char __user *buf, + size_t count, loff_t *f_pos) +{ + return channel_read_gsi(filp, buf, count, f_pos); +} + +static const struct file_operations channel_dev_fops = { + .owner = THIS_MODULE, + .open = channel_open, + .write = channel_write, + .read = channel_read, +}; + +static ssize_t set_skb_for_user(struct file *filp, char __user *buf, + size_t size, loff_t *p_pos); + +static ssize_t get_skb_from_user(struct file *filp, const char __user *buf, + size_t size, loff_t *f_pos); + +static ssize_t get_ulso_skb_from_user(struct file *filp, const char __user *buf, + size_t size, loff_t *f_pos); + +static const struct file_operations data_path_fops = { + .owner = THIS_MODULE, + .open = channel_open, + .read = set_skb_for_user, + .write = get_skb_from_user, +}; + +static const struct file_operations ulso_data_path_fops = { + .owner = THIS_MODULE, + .open = channel_open, + .read = set_skb_for_user, + .write = get_ulso_skb_from_user, +}; + +/* + * This will create the char device named + * "_" and allocate data + * FIFO(size mem_size). + * In this case, we will differentiate + * channel_dev_fops, which are used for + * regular data transmission + * in all the tests,and data_path_fops + * which will be used + * in DataPath tests for handling + * the SKB we will transfer + */ +int create_channel_device_by_type( + const int index, + const char *dev_name, + struct channel_dev **channel_dev_ptr, + size_t mem_size, + enum fops_type type) +{ + int ret; + char name[MAX_CHANNEL_NAME]; + struct channel_dev *channel_dev = NULL; + + scnprintf(name, sizeof(name), "%s_%d", dev_name, index); + + IPATEST_DBG(":Creating channel %d device, name = %s.\n", + index, name); + + /* Allocate memory for the device */ + *channel_dev_ptr = kzalloc(sizeof(struct channel_dev), GFP_KERNEL); + if (NULL == *channel_dev_ptr) { + IPATEST_ERR("kzalloc err for channel dev\n"); + ret = -ENOMEM; + goto create_channel_device_failure; + } + + channel_dev = *channel_dev_ptr; + + strlcpy(channel_dev->name, name, MAX_CHANNEL_NAME); + + /* Allocate memory data buffer for the pipe */ + IPATEST_DBG(":-----Allocate memory data buffer-----\n"); + channel_dev->mem.size = mem_size; + test_alloc_mem(&channel_dev->mem); + if (NULL == channel_dev->mem.base) { + IPATEST_ERR("data fifo alloc fail\n"); + ret = -ENOMEM; + goto create_channel_device_failure; + } + IPATEST_DBG(": data fifo: mem phys=0x%pa.virt=0x%px.\n", + &channel_dev->mem.phys_base, channel_dev->mem.base); + memset(channel_dev->mem.base, 0xbb, channel_dev->mem.size); + + channel_dev->mem_buff_index = 0; + + /* Add a pointer from the channel device to the test context info */ + channel_dev->test = ipa_test; + + channel_dev->class = class_create(THIS_MODULE, channel_dev->name); + if (IS_ERR(channel_dev->class)) { + IPATEST_ERR(":class_create() err.\n"); + ret = -ENOMEM; + goto create_class_failure; + } + + ret = alloc_chrdev_region(&channel_dev->dev_num, 0, 1, channel_dev->name); + if (ret) { + IPATEST_ERR("alloc_chrdev_region err.\n"); + ret = -ENOMEM; + goto alloc_chrdev_failure; + } + + channel_dev->dev = device_create(channel_dev->class, NULL, + channel_dev->dev_num, channel_dev, channel_dev->name); + if (IS_ERR(channel_dev->dev)) { + IPATEST_ERR("device_create err.\n"); + ret = -ENODEV; + goto device_create_failure; + } + switch (type) { + case IPA_TEST_REG_CHANNEL: + cdev_init(&channel_dev->cdev, &channel_dev_fops); + break; + case IPA_TEST_DATA_PATH_TEST_CHANNEL: + cdev_init(&channel_dev->cdev, &data_path_fops); + break; + case IPA_TEST_ULSO_DATA_PATH_TEST_CHANNEL: + cdev_init(&channel_dev->cdev, &ulso_data_path_fops); + break; + default: + IPATEST_ERR("Wrong fops type"); + ret = -EINVAL; + goto invalid_type_err; + } + channel_dev->cdev.owner = THIS_MODULE; + + ret = cdev_add(&channel_dev->cdev, channel_dev->dev_num, 1); + if (ret) { + IPATEST_ERR("cdev_add err=%d\n", -ret); + ret = -ENODEV; + goto cdev_add_failure; + } + + if (!ret) + IPATEST_DBG("Channel device:%d, name:%s created, address:0x%px.\n", + index, channel_dev->name, channel_dev); + + return 0; + +cdev_add_failure: + memset(&channel_dev->cdev, 0, sizeof(channel_dev->cdev)); +invalid_type_err: + device_destroy(channel_dev->class, channel_dev->dev_num); +device_create_failure: + unregister_chrdev_region(channel_dev->dev_num, 1); +alloc_chrdev_failure: + class_destroy(channel_dev->class); +create_class_failure: + test_free_mem(&channel_dev->mem); +create_channel_device_failure: + kfree(channel_dev); + IPATEST_ERR("Channel device %d, name %s creation FAILED.\n", + index, channel_dev->name); + + return ret; +} + +int create_channel_device(const int index, + const char *dev_name, + struct channel_dev **channel_dev_ptr, + size_t mem_size) { + return create_channel_device_by_type( + index, + dev_name, + channel_dev_ptr, + mem_size, + IPA_TEST_REG_CHANNEL); +} + +/* + * DataPath test definitions: + */ + +#define MAX_TEST_SKB 15 +#define TIME_OUT_TIME 2000 /* 2 seconds */ + +struct datapath_ctx { + struct mutex lock; + struct kfifo_rec_ptr_2 fifo; + struct completion write_done_completion; + struct completion ipa_receive_completion; +}; + +struct datapath_ctx *p_data_path_ctx; + +bool init_write_done_completion; + + +/* + * Inits the kfifo needed for the + * DataPath tests + */ +int datapath_ds_init(void) +{ + int res = 0; + rx_size = RX_SZ; + + p_data_path_ctx = kzalloc(sizeof(struct datapath_ctx), GFP_KERNEL); + if (!p_data_path_ctx) { + IPATEST_ERR("kzalloc returned error (%d)\n", res); + return res; + } + IPATEST_DBG("called.\n"); + + res = kfifo_alloc(&p_data_path_ctx->fifo + , (sizeof(struct sk_buff *)*MAX_TEST_SKB) + , GFP_KERNEL); + if (0 != res) { + IPATEST_ERR("kfifo_alloc returned error (%d)\n", res); + kfree(p_data_path_ctx); + return res; + } + + mutex_init(&p_data_path_ctx->lock); + init_completion(&p_data_path_ctx->ipa_receive_completion); + + IPATEST_DBG("completed.(%d)\n", res); + + return res; +} + +static struct sk_buff *datapath_create_skb(const char *buf, size_t size) +{ + struct sk_buff *skb; + unsigned char *data; +#if LINUX_VERSION_CODE < KERNEL_VERSION(5,10,0) + int err = 0; +#endif + + IPATEST_DBG("allocating SKB, len=%zu", size); + skb = alloc_skb(size, GFP_KERNEL); + if (unlikely(!skb)) + return NULL; + IPATEST_DBG("skb allocated, skb->len=%d", skb->len); + data = skb_put(skb, size); + if (unlikely(!data)) { + kfree_skb(skb); + return NULL; + } + IPATEST_DBG("skb put finish, skb->len=%d", skb->len); +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,10,0) + skb->csum = csum_and_copy_from_user(buf, data, size); + if (!skb->csum) { +#else + skb->csum = csum_and_copy_from_user(buf, data, size, 0, &err); + if (err) { +#endif + kfree_skb(skb); + return NULL; + } + IPATEST_DBG("The following packet was created:\n"); + print_buff(skb->data, size); + IPATEST_DBG("Exiting\n"); + + return skb; +} + +static struct sk_buff *ulso_create_skb(const char *buf, size_t size) +{ + struct sk_buff *skb; + + IPATEST_DBG("Entering\n"); + + skb = datapath_create_skb(buf, size); + if (unlikely(!skb)) + return NULL; + + /* Mark the skb as gso skb */ + skb_increase_gso_size(skb_shinfo(skb), 1); + + IPATEST_DBG("Exiting\n"); + + return skb; +} + +static int datapath_read_data(void *element, int size) +{ + int res; + + IPATEST_DBG("Entering\n"); + + mutex_lock(&p_data_path_ctx->lock); + reinit_completion(&p_data_path_ctx->ipa_receive_completion); + IPATEST_DBG("Init completion\n"); + IPATEST_DBG("Checking if kfifo is empty\n"); + if (kfifo_is_empty(&p_data_path_ctx->fifo)) { + IPATEST_DBG("kfifo is empty\n"); + mutex_unlock(&p_data_path_ctx->lock); + IPATEST_DBG("wait_for_ipa_receive_completion\n"); + res = wait_for_completion_timeout( + &p_data_path_ctx->ipa_receive_completion, + msecs_to_jiffies(TIME_OUT_TIME)); + IPATEST_DBG("came back from wait_for_completion_timeout\n"); + if (!res) { + IPATEST_ERR("Error in wait_for_ipa_receive_completion\n"); + return -EINVAL; + } + IPATEST_DBG("locking lock\n"); + mutex_lock(&p_data_path_ctx->lock); + } + res = kfifo_out(&p_data_path_ctx->fifo, element, size); + if (res != size) { + IPATEST_ERR("Error in taking out an element\n"); + IPATEST_ERR("unlocking lock\n"); + mutex_unlock(&p_data_path_ctx->lock); + return -EINVAL; + } + IPATEST_DBG("took %d bytes out\n", res); + IPATEST_DBG("unlocking lock\n"); + IPATEST_DBG("Exiting\n"); + mutex_unlock(&p_data_path_ctx->lock); + return res; +} + +static int datapath_write_fifo( + void *element, + int size) { + + int res; + + IPATEST_DBG("Entering\n"); + mutex_lock(&p_data_path_ctx->lock); + IPATEST_DBG("Mutex locked\n"); + IPATEST_DBG("putting %px into fifo\n", element); + res = kfifo_in(&p_data_path_ctx->fifo, &element, size); + IPATEST_DBG("finished kfifo in\n"); + if (res != size) { + IPATEST_ERR("Error in saving element\n"); + return -EINVAL; + } + IPATEST_DBG("Mutex unlocked\n"); + + complete(&p_data_path_ctx->ipa_receive_completion); + IPATEST_DBG("Completed ipa_receive_completion\n"); + mutex_unlock(&p_data_path_ctx->lock); + return 0; +} + +/* + * Receives from the user space the buff, + * create an SKB, and send it through + * ipa_tx_dp that was received in the system + */ +static ssize_t get_skb_from_user(struct file *filp, const char __user *buf, + size_t size, loff_t *f_pos) { + + int res = 0; + struct sk_buff *skb; + + IPATEST_DBG("Entering\n"); + /* Copy the data from the user and transmit */ + IPATEST_DBG("-----Copy the data from the user-----\n"); + + IPATEST_DBG("Creating SKB\n"); + + skb = datapath_create_skb(buf, size); + if (!skb) + return -EINVAL; + init_completion(&p_data_path_ctx->write_done_completion); + IPATEST_DBG( + "Starting transfer through ipa_tx_dp\n"); + res = ipa_tx_dp(IPA_CLIENT_TEST_CONS, skb, + NULL); + IPATEST_DBG("ipa_tx_dp res = %d.\n", res); + res = wait_for_completion_timeout( + &p_data_path_ctx->write_done_completion, + msecs_to_jiffies(TIME_OUT_TIME)); + IPATEST_DBG("timeout result = %d", res); + if (!res) + return -EINVAL; + IPATEST_DBG("-----Exiting-----\n"); + + return size; +} + +/* + * Receives from the user space the buff, + * create an SKB, and send it through + * ipa_tx_dp that was received in the system + */ +static ssize_t get_ulso_skb_from_user(struct file *filp, +const char __user *buf, size_t size, loff_t *f_pos) { + int res = 0; + struct sk_buff *skb; + + IPATEST_DBG("Entering\n"); + /* Copy the data from the user and transmit */ + IPATEST_DBG("-----Copy the data from the user-----\n"); + IPATEST_DBG("Creating SKB\n"); + skb = ulso_create_skb(buf, size); + if (!skb) + return -EINVAL; + + if (!init_write_done_completion) { + init_completion(&p_data_path_ctx->write_done_completion); + init_write_done_completion = true; + } else { + reinit_completion(&p_data_path_ctx->write_done_completion); + } + + IPATEST_DBG("Starting transfer through ipa_tx_dp\n"); + res = ipa_tx_dp(IPA_CLIENT_TEST_CONS, skb, NULL); + IPATEST_DBG("ipa_tx_dp res = %d.\n", res); + res = wait_for_completion_timeout( + &p_data_path_ctx->write_done_completion, + msecs_to_jiffies(TIME_OUT_TIME)); + IPATEST_DBG("timeout result = %d", res); + if (!res) + return -EINVAL; + IPATEST_DBG("-----Exiting-----\n"); + + return size; +} + +/* + * Sends the user space the next SKB + * that was received in the system + */ + +static ssize_t set_skb_for_user(struct file *filp, char __user *buf, + size_t size, loff_t *p_pos) +{ + int res; + struct sk_buff *p_skb; + + IPATEST_DBG("Entering\n"); + /* Copy the result to the user buffer */ + + IPATEST_DBG("datapath_read_data\n"); + if (datapath_read_data( + (void *)&p_skb, + sizeof(struct sk_buff *)) < 0) { + IPATEST_ERR("error in datapath_read_data\n"); + return -EINVAL; + } + print_buff(p_skb->data, size); + IPATEST_DBG("Copying data back to user\n"); + res = copy_to_user(buf, p_skb->data, size); + kfree_skb(p_skb); + /* Return the number of bytes copied to the user */ + + return res; +} + +static void datapath_ds_clean(void) +{ + kfifo_reset(&p_data_path_ctx->fifo); +} + +/* + * Destroy the kfifo needed for the + * DataPath tests + */ + +static void datapath_exit(void) +{ + kfifo_free(&p_data_path_ctx->fifo); + /* freeing kfifo */ + kfree(p_data_path_ctx); + p_data_path_ctx = NULL; +} + +/* + * CB func. for the IPA_WRITE_DONE + * event. Used in IpaTxDpTest + */ + +static void notify_ipa_write_done( + void *priv, + enum ipa_dp_evt_type evt, + unsigned long data) { + + IPATEST_DBG("Entering function\n"); + + if (evt == IPA_WRITE_DONE) { + IPATEST_DBG("evt IPA_WRITE_DONE\n"); + IPATEST_DBG("Printing received buff from IPA\n"); + print_buff( + ((struct sk_buff *)data)->data, + ((struct sk_buff *)data)->len); + + kfree_skb((struct sk_buff *)data); + complete(&p_data_path_ctx->write_done_completion); + + } else { + IPATEST_DBG("Error, wrong event %d\n", evt); + } +} + +/* + * CB func. for the IPA_RECEIVE + * event. Used in IPAToAppsTest + */ + +static void notify_ipa_received( + void *priv, + enum ipa_dp_evt_type evt, + unsigned long data){ + + struct sk_buff *p_skb = (struct sk_buff *)data; + + IPATEST_DBG("Entering function\n"); + + if (evt == IPA_RECEIVE) { + IPATEST_DBG("evt IPA_RECEIVE\n"); + IPATEST_DBG("Printing received buff from IPA\n"); + print_buff(p_skb->data, p_skb->len); + datapath_write_fifo(p_skb, sizeof(struct sk_buff *)); + } else { + IPATEST_ERR("Error: wrong event %d", evt); + } +} + +static void ipa_test_gsi_evt_ring_err_cb(struct gsi_evt_err_notify *notify) +{ + if (notify) { + switch (notify->evt_id) { + case GSI_EVT_OUT_OF_BUFFERS_ERR: + IPATEST_ERR("Received GSI_EVT_OUT_OF_BUFFERS_ERR\n"); + break; + case GSI_EVT_OUT_OF_RESOURCES_ERR: + IPATEST_ERR("Received GSI_EVT_OUT_OF_RESOURCES_ERR\n"); + break; + case GSI_EVT_UNSUPPORTED_INTER_EE_OP_ERR: + IPATEST_ERR("Received GSI_EVT_UNSUPPORTED_INTER_EE_OP_ERR\n"); + break; + case GSI_EVT_EVT_RING_EMPTY_ERR: + IPATEST_ERR("Received GSI_EVT_EVT_RING_EMPTY_ERR\n"); + break; + default: + IPATEST_ERR("Unexpected err evt: %d\n", notify->evt_id); + } + } + return; +} + +static void ipa_test_gsi_chan_err_cb(struct gsi_chan_err_notify *notify) +{ + if (notify) { + switch (notify->evt_id) { + case GSI_CHAN_INVALID_TRE_ERR: + IPATEST_ERR("Received GSI_CHAN_INVALID_TRE_ERR\n"); + break; + case GSI_CHAN_NON_ALLOCATED_EVT_ACCESS_ERR: + IPATEST_ERR("Received GSI_CHAN_NON_ALLOCATED_EVT_ACCESS_ERR\n"); + break; + case GSI_CHAN_OUT_OF_BUFFERS_ERR: + IPATEST_ERR("Received GSI_CHAN_OUT_OF_BUFFERS_ERR\n"); + break; + case GSI_CHAN_OUT_OF_RESOURCES_ERR: + IPATEST_ERR("Received GSI_CHAN_OUT_OF_RESOURCES_ERR\n"); + break; + case GSI_CHAN_UNSUPPORTED_INTER_EE_OP_ERR: + IPATEST_ERR("Received GSI_CHAN_UNSUPPORTED_INTER_EE_OP_ERR\n"); + break; + case GSI_CHAN_HWO_1_ERR: + IPATEST_ERR("Received GSI_CHAN_HWO_1_ERR\n"); + break; + default: + IPATEST_ERR("Unexpected err ch: %d\n", notify->evt_id); + } + } + return; +} + +static void ipa_test_gsi_irq_notify_cb(struct gsi_chan_xfer_notify *notify) +{ + IPATEST_DBG("ipa_test_gsi_irq_notify_cb: channel 0x%px xfer 0x%px\n", notify->chan_user_data, notify->xfer_user_data); + IPATEST_DBG("ipa_test_gsi_irq_notify_cb: event %d notified\n", notify->evt_id); + IPATEST_DBG("ipa_test_gsi_irq_notify_cb: bytes_xfered %d\n", notify->bytes_xfered); +} + +int connect_ipa_to_apps(struct test_endpoint_sys *rx_ep, + enum ipa_client_type client, + u32 pipe_index, + unsigned long ipa_gsi_hdl) +{ + int res = 0; + + dma_addr_t dma_addr; + const struct ipa_gsi_ep_config *gsi_ep_config; + struct device *pdev; + + pdev = ipa3_get_pdev(); + if (!pdev) { + IPATEST_ERR("IPA module not initialized\n"); + return -EINVAL; + } + + memset(&rx_ep->gsi_evt_ring_props, 0, sizeof(rx_ep->gsi_evt_ring_props)); + rx_ep->gsi_evt_ring_props.intf = GSI_EVT_CHTYPE_GPI_EV; + rx_ep->gsi_evt_ring_props.intr = GSI_INTR_IRQ; + rx_ep->gsi_evt_ring_props.re_size = + GSI_EVT_RING_RE_SIZE_16B; + + rx_ep->gsi_evt_ring_props.ring_len = GSI_EVT_RING_LEN; + rx_ep->gsi_evt_ring_props.ring_base_vaddr = + dma_alloc_coherent(pdev, GSI_EVT_RING_LEN, + &dma_addr, 0); + rx_ep->gsi_evt_ring_props.ring_base_addr = dma_addr; + + rx_ep->gsi_evt_ring_props.int_modt = 3200; //0.1s under 32KHz clock + rx_ep->gsi_evt_ring_props.int_modc = 1; + rx_ep->gsi_evt_ring_props.rp_update_addr = 0; + rx_ep->gsi_evt_ring_props.exclusive = true; + rx_ep->gsi_evt_ring_props.err_cb = ipa_test_gsi_evt_ring_err_cb; + rx_ep->gsi_evt_ring_props.user_data = NULL; + + res = gsi_alloc_evt_ring(&rx_ep->gsi_evt_ring_props, ipa_gsi_hdl, + &rx_ep->gsi_evt_ring_hdl); + if (res != GSI_STATUS_SUCCESS) { + IPATEST_ERR("gsi_alloc_evt_ring failed %d\n", res); + return -EFAULT; + } + + memset(&rx_ep->gsi_channel_props, 0, + sizeof(rx_ep->gsi_channel_props)); + rx_ep->gsi_channel_props.prot = GSI_CHAN_PROT_GPI; + rx_ep->gsi_channel_props.dir = GSI_CHAN_DIR_FROM_GSI; + gsi_ep_config = ipa_get_gsi_ep_info(client); + if (!gsi_ep_config) { + IPATEST_ERR("invalid gsi_ep_config\n"); + return -EFAULT; + } + rx_ep->gsi_channel_props.ch_id = + gsi_ep_config->ipa_gsi_chan_num; + rx_ep->gsi_channel_props.evt_ring_hdl = rx_ep->gsi_evt_ring_hdl; + rx_ep->gsi_channel_props.re_size = GSI_CHAN_RE_SIZE_16B; + + rx_ep->gsi_channel_props.ring_len = GSI_CHANNEL_RING_LEN; + rx_ep->gsi_channel_props.ring_base_vaddr = + dma_alloc_coherent(pdev, GSI_CHANNEL_RING_LEN, + &dma_addr, 0); + if (!rx_ep->gsi_channel_props.ring_base_vaddr) { + IPATEST_ERR("connect_ipa_to_apps: falied to alloc GSI ring\n"); + return -EFAULT; + } + + rx_ep->gsi_channel_props.ring_base_addr = dma_addr; + rx_ep->gsi_channel_props.use_db_eng = GSI_CHAN_DIRECT_MODE; + rx_ep->gsi_channel_props.max_prefetch = GSI_ONE_PREFETCH_SEG; + rx_ep->gsi_channel_props.low_weight = 1; + rx_ep->gsi_channel_props.chan_user_data = rx_ep; + if (ipa_get_hw_type() >= IPA_HW_v4_9) + rx_ep->gsi_channel_props.db_in_bytes = 1; + + rx_ep->gsi_channel_props.err_cb = ipa_test_gsi_chan_err_cb; + rx_ep->gsi_channel_props.xfer_cb = ipa_test_gsi_irq_notify_cb; + res = gsi_alloc_channel(&rx_ep->gsi_channel_props, ipa_gsi_hdl, + &rx_ep->gsi_chan_hdl); + if (res != GSI_STATUS_SUCCESS) { + IPATEST_ERR("gsi_alloc_channel failed %d\n", res); + return -EFAULT; + } + rx_ep->gsi_valid = true; + + res = ipa3_sys_update_gsi_hdls(pipe_index, rx_ep->gsi_chan_hdl, rx_ep->gsi_evt_ring_hdl); + if (res) { + IPATEST_ERR("ipa_sys_update_gsi_hdls failed %d\n", res); + return -EFAULT; + } + + res = gsi_start_channel(rx_ep->gsi_chan_hdl); + if (res != GSI_STATUS_SUCCESS) { + IPATEST_ERR("gsi_start_channel failed %d\n", res); + return -EFAULT; + } + + IPATEST_DBG("setting channel to polling mode\n"); + res = gsi_config_channel_mode(rx_ep->gsi_chan_hdl, GSI_CHAN_MODE_POLL); + if (res != GSI_STATUS_SUCCESS) { + IPATEST_ERR("gsi_config_channel_mode failed %d\n", res); + return -EFAULT; + } + + return 0; +} + +int connect_apps_to_ipa(struct test_endpoint_sys *tx_ep, + enum ipa_client_type client, + u32 pipe_index, + struct ipa_mem_buffer *desc_fifo, + unsigned long ipa_gsi_hdl) +{ + int res = 0; + dma_addr_t dma_addr; + const struct ipa_gsi_ep_config *gsi_ep_config; + struct device *pdev; + + pdev = ipa3_get_pdev(); + if (!pdev) { + IPATEST_ERR("IPA module not initialized\n"); + return -EINVAL; + } + + memset(&tx_ep->gsi_evt_ring_props, 0, sizeof(tx_ep->gsi_evt_ring_props)); + tx_ep->gsi_evt_ring_props.intf = GSI_EVT_CHTYPE_GPI_EV; + tx_ep->gsi_evt_ring_props.intr = GSI_INTR_IRQ; + tx_ep->gsi_evt_ring_props.re_size = + GSI_EVT_RING_RE_SIZE_16B; + + tx_ep->gsi_evt_ring_props.ring_len = GSI_EVT_RING_LEN; + tx_ep->gsi_evt_ring_props.ring_base_vaddr = + dma_alloc_coherent(pdev, GSI_EVT_RING_LEN, + &dma_addr, 0); + tx_ep->gsi_evt_ring_props.ring_base_addr = dma_addr; + + tx_ep->gsi_evt_ring_props.int_modt = 3200; //0.1s under 32KHz clock + tx_ep->gsi_evt_ring_props.int_modc = 1; + tx_ep->gsi_evt_ring_props.rp_update_addr = 0; + tx_ep->gsi_evt_ring_props.exclusive = true; + tx_ep->gsi_evt_ring_props.err_cb = ipa_test_gsi_evt_ring_err_cb; + tx_ep->gsi_evt_ring_props.user_data = NULL; + + res = gsi_alloc_evt_ring(&tx_ep->gsi_evt_ring_props, ipa_gsi_hdl, + &tx_ep->gsi_evt_ring_hdl); + if (res != GSI_STATUS_SUCCESS) { + IPATEST_ERR("gsi_alloc_evt_ring failed %d\n", res); + return -EFAULT; + } + + memset(&tx_ep->gsi_channel_props, 0, sizeof(tx_ep->gsi_channel_props)); + tx_ep->gsi_channel_props.prot = GSI_CHAN_PROT_GPI; + tx_ep->gsi_channel_props.dir = GSI_CHAN_DIR_TO_GSI; + gsi_ep_config = ipa_get_gsi_ep_info(client); + if (!gsi_ep_config) { + IPATEST_ERR("invalid gsi_ep_config\n"); + return -EFAULT; + } + tx_ep->gsi_channel_props.ch_id = + gsi_ep_config->ipa_gsi_chan_num; + tx_ep->gsi_channel_props.evt_ring_hdl = tx_ep->gsi_evt_ring_hdl; + tx_ep->gsi_channel_props.re_size = GSI_CHAN_RE_SIZE_16B; + + tx_ep->gsi_channel_props.ring_len = GSI_CHANNEL_RING_LEN; + tx_ep->gsi_channel_props.ring_base_vaddr = + dma_alloc_coherent(pdev, GSI_CHANNEL_RING_LEN, + &dma_addr, 0); + if (!tx_ep->gsi_channel_props.ring_base_vaddr) { + IPATEST_ERR("connect_apps_to_ipa: falied to alloc GSI ring\n"); + return -EFAULT; + } + + tx_ep->gsi_channel_props.ring_base_addr = dma_addr; + tx_ep->gsi_channel_props.use_db_eng = GSI_CHAN_DIRECT_MODE; + tx_ep->gsi_channel_props.max_prefetch = GSI_ONE_PREFETCH_SEG; + tx_ep->gsi_channel_props.low_weight = 1; + tx_ep->gsi_channel_props.chan_user_data = tx_ep; + if (ipa_get_hw_type() >= IPA_HW_v4_9) + tx_ep->gsi_channel_props.db_in_bytes = 1; + + tx_ep->gsi_channel_props.err_cb = ipa_test_gsi_chan_err_cb; + tx_ep->gsi_channel_props.xfer_cb = ipa_test_gsi_irq_notify_cb; + res = gsi_alloc_channel(&tx_ep->gsi_channel_props, ipa_gsi_hdl, + &tx_ep->gsi_chan_hdl); + if (res != GSI_STATUS_SUCCESS) { + IPATEST_ERR("gsi_alloc_channel failed %d\n", res); + return -EFAULT; + } + tx_ep->gsi_valid = true; + + res = ipa3_sys_update_gsi_hdls(pipe_index, tx_ep->gsi_chan_hdl, tx_ep->gsi_evt_ring_hdl); + if (res) { + IPATEST_ERR("ipa_sys_update_gsi_hdls failed %d\n", res); + return -EFAULT; + } + + res = gsi_start_channel(tx_ep->gsi_chan_hdl); + if (res != GSI_STATUS_SUCCESS) { + IPATEST_ERR("gsi_start_channel failed %d\n", res); + return -EFAULT; + } + + return 0; +} + +int configure_ipa_endpoint(struct ipa_ep_cfg *ipa_ep_cfg, + enum ipa_mode_type mode) +{ + const char *DEFAULT_ROUTING_TABLE_NAME = "LAN"; + const enum ipa_client_type DEFAULT_CLIENT = IPA_CLIENT_TEST4_CONS; + struct ipa_ioc_add_rt_rule *rt_rule; + struct ipa_rt_rule_add *rt_rule_entry; + struct ipa_ioc_get_rt_tbl rt_lookup; + + memset(ipa_ep_cfg, 0, sizeof(*ipa_ep_cfg)); + /* Configure mode */ + ipa_ep_cfg->mode.mode = mode; + /* Add default routing rule */ + rt_rule = kzalloc(sizeof(struct ipa_ioc_add_rt_rule) + + 1 * sizeof(struct ipa_rt_rule_add), GFP_KERNEL); + if (!rt_rule) { + IPATEST_ERR("Allocation failure.\n"); + return -EINVAL; + } + rt_rule->commit = 1; + rt_rule->num_rules = 1; + rt_rule->ip = IPA_IP_v4; + strlcpy(rt_rule->rt_tbl_name, + DEFAULT_ROUTING_TABLE_NAME, + IPA_RESOURCE_NAME_MAX); + rt_rule_entry = &rt_rule->rules[0]; + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = DEFAULT_CLIENT; + /* Issuing a routing rule without + * any equations will cause a default rule + which catches every packet and sends it + to the default endpoint. */ + if (ipa_add_rt_rule(rt_rule)) { + IPATEST_ERR("ipa_add_rt_rule() failure.\n"); + } + IPATEST_DBG("rt rule hdl1=%x.\n", rt_rule_entry->rt_rule_hdl); + /* At this point, there is a routing table in memory, + with one defalut rule. + user space test application will enter more valid + rules the default rule + must be last on the list. + Get a handle to the routing table which holds + the added rule. This will + also increment an internal reference count. */ + memset(&rt_lookup, 0, sizeof(struct ipa_ioc_get_rt_tbl)); + rt_lookup.ip = IPA_IP_v4; + strlcpy(rt_lookup.name, + DEFAULT_ROUTING_TABLE_NAME, + IPA_RESOURCE_NAME_MAX); + if (ipa3_get_rt_tbl(&rt_lookup)) { + IPATEST_ERR("ipa_get_rt_tbl() failure.\n"); + } + ipa_ep_cfg->route.rt_tbl_hdl = rt_lookup.hdl; + /* Now release the routing table hdl. This code assumes + that routing table + will continue to exist when the endpoint + connection is requested. */ + if (ipa_put_rt_tbl(rt_lookup.hdl)) { + IPATEST_ERR("ipa_put_rt_tbl() failure.\n"); + } + return 0; +} + +/* + * Configures the system as follows: + * This configuration is for one input pipe + * and one output pipe where both are USB1 + * /dev/to_ipa_0 -> MEM -> IPA + * -> MEM -> /dev/from_ipa_0 + * Those client will be configured in DMA mode thus + * no Header removal/insertion will be + * made on their data. +*/ +int configure_system_1(void) +{ + int res = 0; + struct ipa_ep_cfg ipa_ep_cfg; + + struct ipa_sys_connect_params sys_in; + unsigned long ipa_gsi_hdl; + u32 ipa_pipe_num; + + memset(&ipa_ep_cfg, 0, sizeof(ipa_ep_cfg)); + IPATEST_DBG("Configure_system_1 was called\n"); + + /* Connect IPA --> APPS MEM */ + memset(&sys_in, 0, sizeof(sys_in)); + sys_in.client = IPA_CLIENT_TEST_CONS; + if (ipa3_sys_setup(&sys_in, &ipa_gsi_hdl, &ipa_pipe_num, + &from_ipa_devs[0]->ipa_client_hdl, false)) + goto fail; + + res = connect_ipa_to_apps(&from_ipa_devs[0]->ep, + IPA_CLIENT_TEST_CONS, + ipa_pipe_num, + ipa_gsi_hdl); + if (res) + goto fail; + /* Prepare EP configuration details */ + memset(&ipa_ep_cfg, 0, sizeof(ipa_ep_cfg)); + ipa_ep_cfg.mode.mode = IPA_DMA; + ipa_ep_cfg.mode.dst = IPA_CLIENT_TEST_CONS; + + memset(&sys_in, 0, sizeof(sys_in)); + sys_in.client = IPA_CLIENT_TEST_PROD; + sys_in.ipa_ep_cfg = ipa_ep_cfg; + if (ipa3_sys_setup(&sys_in, &ipa_gsi_hdl, &ipa_pipe_num, + &to_ipa_devs[0]->ipa_client_hdl, false)) + goto fail; + + /* Connect APPS MEM --> Tx IPA */ + res = connect_apps_to_ipa(&to_ipa_devs[0]->ep, + IPA_CLIENT_TEST_PROD, + ipa_pipe_num, + &to_ipa_devs[0]->mem, + ipa_gsi_hdl); + if (res) + goto fail; +fail: + /* cleanup and tear down goes here*/ + return res; +} + +/* + Configures the system with one input to IPA and 2 outputs. + /dev/to_ipa_0 -> MEM -> GSI -> IPA |-> GSI + -> MEM -> /dev/from_ipa_0 +|-> GSI -> MEM -> /dev/from_ipa_1 +*/ +int configure_system_2(void) +{ + int res = 0; + struct ipa_ep_cfg ipa_ep_cfg; + + struct ipa_sys_connect_params sys_in; + unsigned long ipa_gsi_hdl; + u32 ipa_pipe_num; + + memset(&ipa_ep_cfg, 0, sizeof(ipa_ep_cfg)); + + + /* Connect first Rx IPA --> APPS MEM */ + memset(&sys_in, 0, sizeof(sys_in)); + sys_in.client = IPA_CLIENT_TEST2_CONS; + if (ipa3_sys_setup(&sys_in, &ipa_gsi_hdl, &ipa_pipe_num, + &from_ipa_devs[0]->ipa_client_hdl, false)) + goto fail; + + res = connect_ipa_to_apps(&from_ipa_devs[0]->ep, + IPA_CLIENT_TEST2_CONS, + ipa_pipe_num, + ipa_gsi_hdl); + if (res) + goto fail; + + /* Connect second Rx IPA --> APPS MEM */ + memset(&sys_in, 0, sizeof(sys_in)); + sys_in.client = IPA_CLIENT_TEST3_CONS; + if (ipa3_sys_setup(&sys_in, &ipa_gsi_hdl, &ipa_pipe_num, + &from_ipa_devs[1]->ipa_client_hdl, false)) + goto fail; + + res = connect_ipa_to_apps(&from_ipa_devs[1]->ep, + IPA_CLIENT_TEST3_CONS, + ipa_pipe_num, + ipa_gsi_hdl); + if (res) + goto fail; + + /* Connect third (Default) Rx IPA --> APPS MEM */ + memset(&sys_in, 0, sizeof(sys_in)); + sys_in.client = IPA_CLIENT_TEST4_CONS; + if (ipa3_sys_setup(&sys_in, &ipa_gsi_hdl, &ipa_pipe_num, + &from_ipa_devs[2]->ipa_client_hdl, false)) + goto fail; + + res = connect_ipa_to_apps(&from_ipa_devs[2]->ep, + IPA_CLIENT_TEST4_CONS, + ipa_pipe_num, + ipa_gsi_hdl); + if (res) + goto fail; + + + memset(&sys_in, 0, sizeof(sys_in)); + sys_in.client = IPA_CLIENT_TEST_PROD; + sys_in.ipa_ep_cfg = ipa_ep_cfg; + if (ipa3_sys_setup(&sys_in, &ipa_gsi_hdl, &ipa_pipe_num, + &to_ipa_devs[0]->ipa_client_hdl, false)) + goto fail; + + /* Connect APPS MEM --> Tx IPA */ + res = connect_apps_to_ipa(&to_ipa_devs[0]->ep, + IPA_CLIENT_TEST_PROD, + ipa_pipe_num, + &to_ipa_devs[0]->mem, + ipa_gsi_hdl); + + + if (res) + goto fail; + + /* Connect Tx GSI -> IPA */ + /* Prepare an endpoint configuration structure */ + res = configure_ipa_endpoint(&ipa_ep_cfg, IPA_BASIC); + if (res) + goto fail; + + /* configure header removal on Tx */ + ipa_ep_cfg.hdr.hdr_len = ETH_HLEN; + + memset(&sys_in, 0, sizeof(sys_in)); + sys_in.client = IPA_CLIENT_TEST2_PROD; + sys_in.ipa_ep_cfg = ipa_ep_cfg; + if (ipa3_sys_setup(&sys_in, &ipa_gsi_hdl, &ipa_pipe_num, + &to_ipa_devs[1]->ipa_client_hdl, false)) + goto fail; + + /* Connect APPS MEM --> Tx IPA */ + res = connect_apps_to_ipa(&to_ipa_devs[1]->ep, + IPA_CLIENT_TEST2_PROD, + ipa_pipe_num, + &to_ipa_devs[1]->mem, + ipa_gsi_hdl); + + + if (res) + goto fail; + +fail: + /* cleanup and tear down goes here */ + return res; +} + +/*Configuration used for Header Insertion Tests*/ +int configure_system_5(void) +{ + int res = 0; + struct ipa_ep_cfg ipa_ep_cfg; + + struct ipa_sys_connect_params sys_in; + unsigned long ipa_gsi_hdl; + u32 ipa_pipe_num; + + memset(&ipa_ep_cfg, 0, sizeof(ipa_ep_cfg)); + + /* configure header Insertion on Tx */ + +/* ipa_ep_cfg.hdr.hdr_len = IPA_TEST_DMUX_HEADER_LENGTH; + !< Header length in bytes to be added/removed. + Assuming heaser len is constant per endpoint. + Valid for both Input and Output Pipes + Length of Header to add / to remove + ipa_ep_cfg.hdr.hdr_additional_const_len = 0; + !< Defines the constant length that should be added + to the payload length in order for IPA to update + correctly the length field within the header + (valid only in case Hdr_Ofst_Pkt_Size_Valid=1) + Valid for Output Pipes (IPA Producer) + ipa_ep_cfg.hdr.hdr_ofst_pkt_size_valid = 0; + !< 0: Hdr_Ofst_Pkt_Size value is invalid, i.e., + no length field within the inserted header + 1: Hdr_Ofst_Pkt_Size value is valid, i.e., + a packet length field resides within the header + Valid for Output Pipes (IPA Producer) + ipa_ep_cfg.hdr.hdr_ofst_pkt_size = 0; + !< Offset within header in which packet size + reside. Upon Header Insertion, IPA will update this + field within the header with the packet length . + Assumption is that header length field size is + constant and is 2Bytes Valid for Output Pipes (IPA Producer) + ipa_ep_cfg.hdr.hdr_a5_mux = 0; + 0: Do not insert APPS Mux Header + 1: Insert APPS Mux Header + !< Determines whether APPS Mux header should be + added to the packet. This bit is valid only when + Hdr_En=01(Header Insertion) SW should set this bit + for IPA-to-APPS pipes. + 0: Do not insert APPS Mux Header + 1: Insert APPS Mux Header + Valid for Output Pipes (IPA Producer) */ + + + + /* Connect IPA -> first Rx GSI */ + memset(&ipa_ep_cfg, 0, sizeof(ipa_ep_cfg)); + ipa_ep_cfg.hdr.hdr_len = + IPA_TEST_HDI_RMNET_HEADER_LENGTH; + /* Length of Header to add / to remove */ + ipa_ep_cfg.hdr.hdr_additional_const_len = + IPA_TEST_HDI_RMNET_ADD_CONST_LENGTH; + /* constant length that should be added to the payload + * length or IPA to update correctly the length + * field within the header */ + ipa_ep_cfg.hdr.hdr_ofst_pkt_size_valid + = IPA_TEST_HDI_RMNET_LENGTH_FIELD_OFFSET_VALID; + /*0: Hdr_Ofst_Pkt_Size value is invalid, i.e., + no length field within the inserted header + 1: Hdr_Ofst_Pkt_Size value is valid, i.e., + a packet length field resides within the header*/ + ipa_ep_cfg.hdr.hdr_ofst_pkt_size + = IPA_TEST_HDI_RMNET_LENGTH_FIELD_OFFSET; + /* Offset within header in which packet size reside. + Upon Header Insertion, IPA will update this field + within the header with the packet length . + Assumption is that header length field size + is constant and is 2Bytes */ + + /* Connect first Rx IPA --> APPS MEM */ + memset(&sys_in, 0, sizeof(sys_in)); + sys_in.client = IPA_CLIENT_TEST2_CONS; + sys_in.ipa_ep_cfg = ipa_ep_cfg; + if (ipa3_sys_setup(&sys_in, &ipa_gsi_hdl, &ipa_pipe_num, + &from_ipa_devs[0]->ipa_client_hdl, false)) + goto fail; + + res = connect_ipa_to_apps(&from_ipa_devs[0]->ep, + IPA_CLIENT_TEST2_CONS, + ipa_pipe_num, + ipa_gsi_hdl); + if (res) + goto fail; + + memset(&ipa_ep_cfg, 0, sizeof(ipa_ep_cfg)); + ipa_ep_cfg.hdr.hdr_len = IPA_TEST_HDI_802_HEADER_LENGTH; + /*Length of Header to add / to remove*/ + ipa_ep_cfg.hdr.hdr_additional_const_len + = IPA_TEST_HDI_802_ADD_CONST_LENGTH; + /* constant length that should be added + * to the payload length + or IPA to update correctly the + length field within the header */ + ipa_ep_cfg.hdr.hdr_ofst_pkt_size_valid + = IPA_TEST_HDI_802_LENGTH_FIELD_OFFSET_VALID; + /*0: Hdr_Ofst_Pkt_Size value is invalid, i.e., + no length field within the inserted header + 1: Hdr_Ofst_Pkt_Size value is valid, i.e. + a packet length field resides within the header*/ + ipa_ep_cfg.hdr.hdr_ofst_pkt_size + = IPA_TEST_HDI_802_LENGTH_FIELD_OFFSET; + /* Offset within header in which packet size reside. + Upon Header Insertion, IPA will update this field + within the header with the packet length. + Assumption is that header length field size is constant + and is 2Bytes */ + /* Connect second Rx IPA --> APPS MEM */ + memset(&sys_in, 0, sizeof(sys_in)); + sys_in.client = IPA_CLIENT_TEST3_CONS; + sys_in.ipa_ep_cfg = ipa_ep_cfg; + if (ipa3_sys_setup(&sys_in, &ipa_gsi_hdl, + &ipa_pipe_num, + &from_ipa_devs[1]->ipa_client_hdl, + false)) + goto fail; + + res = connect_ipa_to_apps(&from_ipa_devs[1]->ep, + IPA_CLIENT_TEST3_CONS, + ipa_pipe_num, + ipa_gsi_hdl); + if (res) + goto fail; + + /* Connect IPA -> third (default) Rx GSI */ + memset(&ipa_ep_cfg, 0, sizeof(ipa_ep_cfg)); + ipa_ep_cfg.hdr.hdr_len + = IPA_TEST_HDI_802_HEADER_LENGTH; + /* Length of Header to add / to remove */ + ipa_ep_cfg.hdr.hdr_additional_const_len + = IPA_TEST_HDI_802_ADD_CONST_LENGTH+1; + /* constant length that should be + * added to the payload length + or IPA to update correctly the length + field within the header */ + ipa_ep_cfg.hdr.hdr_ofst_pkt_size_valid + = IPA_TEST_HDI_802_LENGTH_FIELD_OFFSET_VALID; + /* 0: Hdr_Ofst_Pkt_Size value is invalid, i.e., + no length field within the inserted header + 1: Hdr_Ofst_Pkt_Size value is valid, i.e., + a packet length field resides within the header */ + ipa_ep_cfg.hdr.hdr_ofst_pkt_size + = IPA_TEST_HDI_802_LENGTH_FIELD_OFFSET; + /* Offset within header in which packet size reside. + * Upon Header Insertion, IPA will update this field + * within the header with the packet length . + * Assumption is that header length field size is constant + * and is 2Bytes */ + /* Connect third (Default) Rx IPA --> APPS MEM */ + memset(&sys_in, 0, sizeof(sys_in)); + sys_in.client = IPA_CLIENT_TEST4_CONS; + sys_in.ipa_ep_cfg = ipa_ep_cfg; + if (ipa3_sys_setup(&sys_in, &ipa_gsi_hdl, + &ipa_pipe_num, &from_ipa_devs[2]->ipa_client_hdl, false)) + goto fail; + + res = connect_ipa_to_apps(&from_ipa_devs[2]->ep, + IPA_CLIENT_TEST4_CONS, + ipa_pipe_num, + ipa_gsi_hdl); + + if (res) + goto fail; + + /* Connect Tx GSI -> IPA */ + /* Prepare an endpoint configuration structure */ + res = configure_ipa_endpoint(&ipa_ep_cfg, IPA_BASIC); + if (res) + goto fail; + + memset(&sys_in, 0, sizeof(sys_in)); + sys_in.client = IPA_CLIENT_TEST_PROD; + sys_in.ipa_ep_cfg = ipa_ep_cfg; + if (ipa3_sys_setup(&sys_in, &ipa_gsi_hdl, &ipa_pipe_num, + &to_ipa_devs[0]->ipa_client_hdl, false)) + goto fail; + + /* Connect APPS MEM --> Tx IPA */ + res = connect_apps_to_ipa(&to_ipa_devs[0]->ep, + IPA_CLIENT_TEST_PROD, + ipa_pipe_num, + &to_ipa_devs[0]->mem, + ipa_gsi_hdl); + + if (res) + goto fail; + +fail: + /* cleanup and tear down goes here */ + return res; +} + +/*Configuration Used for USB Integration (on R3PC) */ +int configure_system_6(void) +{ + int res = 0; + struct ipa_ep_cfg ipa_ep_cfg; + struct ipa_sys_connect_params sys_in; + unsigned long ipa_gsi_hdl; + u32 ipa_pipe_num; + + memset(&ipa_ep_cfg, 0, sizeof(ipa_ep_cfg)); + /* Connect first Rx IPA --> APPS MEM */ + memset(&sys_in, 0, sizeof(sys_in)); + sys_in.client = IPA_CLIENT_TEST2_CONS; + sys_in.ipa_ep_cfg = ipa_ep_cfg; + if (ipa3_sys_setup(&sys_in, &ipa_gsi_hdl, &ipa_pipe_num, + &from_ipa_devs[0]->ipa_client_hdl, false)) + goto fail; + res = connect_ipa_to_apps(&from_ipa_devs[0]->ep, + IPA_CLIENT_TEST2_CONS, + ipa_pipe_num, + ipa_gsi_hdl); + if (res) + goto fail; + memset(&ipa_ep_cfg, 0, sizeof(ipa_ep_cfg)); + /* Prepare an endpoint configuration structure */ + ipa_ep_cfg.mode.mode = IPA_BASIC; + memset(&sys_in, 0, sizeof(sys_in)); + sys_in.client = IPA_CLIENT_TEST2_PROD; + sys_in.ipa_ep_cfg = ipa_ep_cfg; + if (ipa3_sys_setup(&sys_in, &ipa_gsi_hdl, &ipa_pipe_num, + &to_ipa_devs[0]->ipa_client_hdl, false)) + goto fail; + /* Connect APPS MEM --> Tx IPA */ + res = connect_apps_to_ipa(&to_ipa_devs[0]->ep, + IPA_CLIENT_TEST2_PROD, + ipa_pipe_num, + &to_ipa_devs[0]->mem, + ipa_gsi_hdl); + if (res) + goto fail; +fail: + /* cleanup and tear down goes here */ + return res; +} + + +/* + Configures the system as follows: + This configuration is for 4 input pipes and 3 output pipes: + /dev/to_ipa_0 -> MEM -> GSI -> + * IPA -> GSI -> MEM -> /dev/from_ipa_0 + /dev/to_ipa_1 -> MEM -> GSI -> + * IPA -> GSI -> MEM -> /dev/from_ipa_1 + /dev/to_ipa_2 -> MEM -> GSI -> + * IPA -> GSI -> MEM -> /dev/from_ipa_0 + /dev/to_ipa_3 -> MEM -> GSI -> + * IPA -> GSI -> MEM -> /dev/from_ipa_2 + to_ipa_1, to_ipa_2, from_ipa_0 & + from_ipa_2 transfer TLP aggregated packets + to_ipa_0, to_ipa_3 & from_ipa_1 transfer raw packets +*/ +int configure_system_8(void) +{ + int res = 0; + struct ipa_ep_cfg ipa_ep_cfg; + + struct ipa_sys_connect_params sys_in; + unsigned long ipa_gsi_hdl; + u32 ipa_pipe_num; + + memset(&ipa_ep_cfg, 0, sizeof(ipa_ep_cfg)); + IPATEST_DBG("Configure_system_8 was called\n"); + + /* Setup GSI pipes */ + to_ipa_devs[0]->dma_ep.src_pipe_index = 4; + to_ipa_devs[0]->dma_ep.dest_pipe_index = 5; + to_ipa_devs[1]->dma_ep.src_pipe_index = 6; + to_ipa_devs[1]->dma_ep.dest_pipe_index = 7; + to_ipa_devs[2]->dma_ep.src_pipe_index = 8; + to_ipa_devs[2]->dma_ep.dest_pipe_index = 9; + to_ipa_devs[3]->dma_ep.src_pipe_index = 10; + to_ipa_devs[3]->dma_ep.dest_pipe_index = 11; + + from_ipa_devs[0]->dma_ep.src_pipe_index = 14; + from_ipa_devs[0]->dma_ep.dest_pipe_index = 15; + from_ipa_devs[1]->dma_ep.src_pipe_index = 16; + from_ipa_devs[1]->dma_ep.dest_pipe_index = 17; + from_ipa_devs[2]->dma_ep.src_pipe_index = 18; + from_ipa_devs[2]->dma_ep.dest_pipe_index = 19; + /* configure aggregation on Tx */ + ipa_ep_cfg.aggr.aggr_en = IPA_ENABLE_AGGR; + ipa_ep_cfg.aggr.aggr = IPA_TLP; + ipa_ep_cfg.aggr.aggr_byte_limit = 1; + ipa_ep_cfg.aggr.aggr_time_limit = 0; + + /* Connect IPA --> APPS MEM */ + memset(&sys_in, 0, sizeof(sys_in)); + sys_in.client = IPA_CLIENT_TEST_CONS; + sys_in.ipa_ep_cfg = ipa_ep_cfg; + if (ipa3_sys_setup(&sys_in, &ipa_gsi_hdl, &ipa_pipe_num, + &from_ipa_devs[0]->ipa_client_hdl, false)) + goto fail; + + res = connect_ipa_to_apps(&from_ipa_devs[0]->ep, + IPA_CLIENT_TEST_CONS, + ipa_pipe_num, + ipa_gsi_hdl); + if (res) + goto fail; + + /* Connect IPA --> APPS MEM */ + memset(&sys_in, 0, sizeof(sys_in)); + sys_in.client = IPA_CLIENT_TEST3_CONS; + if (ipa3_sys_setup(&sys_in, &ipa_gsi_hdl, &ipa_pipe_num, + &from_ipa_devs[1]->ipa_client_hdl, false)) + goto fail; + + res = connect_ipa_to_apps(&from_ipa_devs[1]->ep, + IPA_CLIENT_TEST3_CONS, + ipa_pipe_num, + ipa_gsi_hdl); + if (res) + goto fail; + + /* configure aggregation on Tx */ + ipa_ep_cfg.aggr.aggr_en = IPA_ENABLE_AGGR; + ipa_ep_cfg.aggr.aggr = IPA_TLP; + ipa_ep_cfg.aggr.aggr_byte_limit = 1; + ipa_ep_cfg.aggr.aggr_time_limit = 30; + if (ipa_get_hw_type() >= IPA_HW_v4_2) + ipa_ep_cfg.aggr.aggr_time_limit *= 1000; + + /* Connect IPA --> APPS MEM */ + memset(&sys_in, 0, sizeof(sys_in)); + sys_in.client = IPA_CLIENT_TEST2_CONS; + sys_in.ipa_ep_cfg = ipa_ep_cfg; + if (ipa3_sys_setup(&sys_in, &ipa_gsi_hdl, &ipa_pipe_num, + &from_ipa_devs[2]->ipa_client_hdl, false)) + goto fail; + + res = connect_ipa_to_apps(&from_ipa_devs[2]->ep, + IPA_CLIENT_TEST2_CONS, + ipa_pipe_num, + ipa_gsi_hdl); + if (res) + goto fail; + + /* Prepare EP configuration details */ + memset(&ipa_ep_cfg, 0, sizeof(ipa_ep_cfg)); + ipa_ep_cfg.mode.mode = IPA_DMA; + ipa_ep_cfg.mode.dst = IPA_CLIENT_TEST_CONS; + + memset(&sys_in, 0, sizeof(sys_in)); + sys_in.client = IPA_CLIENT_TEST3_PROD; + sys_in.ipa_ep_cfg = ipa_ep_cfg; + if (ipa3_sys_setup(&sys_in, &ipa_gsi_hdl, &ipa_pipe_num, + &to_ipa_devs[0]->ipa_client_hdl, false)) + goto fail; + + /* Connect APPS MEM --> Tx IPA */ + res = connect_apps_to_ipa(&to_ipa_devs[0]->ep, + IPA_CLIENT_TEST3_PROD, + ipa_pipe_num, + &to_ipa_devs[0]->mem, + ipa_gsi_hdl); + if (res) + goto fail; + + /* configure deaggregation on Rx */ + memset(&ipa_ep_cfg, 0, sizeof(ipa_ep_cfg)); + ipa_ep_cfg.mode.mode = IPA_DMA; + ipa_ep_cfg.mode.dst = IPA_CLIENT_TEST3_CONS; + ipa_ep_cfg.aggr.aggr_en = IPA_ENABLE_DEAGGR; + ipa_ep_cfg.aggr.aggr = IPA_TLP; + + memset(&sys_in, 0, sizeof(sys_in)); + sys_in.client = IPA_CLIENT_TEST_PROD; + sys_in.ipa_ep_cfg = ipa_ep_cfg; + if (ipa3_sys_setup(&sys_in, &ipa_gsi_hdl, &ipa_pipe_num, + &to_ipa_devs[1]->ipa_client_hdl, false)) + goto fail; + + /* Connect APPS MEM --> Tx IPA */ + res = connect_apps_to_ipa(&to_ipa_devs[1]->ep, + IPA_CLIENT_TEST_PROD, + ipa_pipe_num, + &to_ipa_devs[1]->mem, + ipa_gsi_hdl); + if (res) + goto fail; + + /* configure deaggregation on Rx */ + memset(&ipa_ep_cfg, 0, sizeof(ipa_ep_cfg)); + ipa_ep_cfg.mode.mode = IPA_DMA; + ipa_ep_cfg.mode.dst = IPA_CLIENT_TEST_CONS; + ipa_ep_cfg.aggr.aggr_en = IPA_ENABLE_DEAGGR; + ipa_ep_cfg.aggr.aggr = IPA_TLP; + + memset(&sys_in, 0, sizeof(sys_in)); + sys_in.client = IPA_CLIENT_TEST2_PROD; + sys_in.ipa_ep_cfg = ipa_ep_cfg; + if (ipa3_sys_setup(&sys_in, &ipa_gsi_hdl, &ipa_pipe_num, + &to_ipa_devs[2]->ipa_client_hdl, false)) + goto fail; + + /* Connect APPS MEM --> Tx IPA */ + res = connect_apps_to_ipa(&to_ipa_devs[2]->ep, + IPA_CLIENT_TEST2_PROD, + ipa_pipe_num, + &to_ipa_devs[2]->mem, + ipa_gsi_hdl); + if (res) + goto fail; + + /* Prepare EP configuration details */ + memset(&ipa_ep_cfg, 0, sizeof(ipa_ep_cfg)); + ipa_ep_cfg.mode.mode = IPA_DMA; + ipa_ep_cfg.mode.dst = IPA_CLIENT_TEST2_CONS; + + memset(&sys_in, 0, sizeof(sys_in)); + sys_in.client = IPA_CLIENT_TEST4_PROD; + sys_in.ipa_ep_cfg = ipa_ep_cfg; + if (ipa3_sys_setup(&sys_in, &ipa_gsi_hdl, &ipa_pipe_num, + &to_ipa_devs[3]->ipa_client_hdl, false)) + goto fail; + + /* Connect APPS MEM --> Tx IPA */ + res = connect_apps_to_ipa(&to_ipa_devs[3]->ep, + IPA_CLIENT_TEST4_PROD, + ipa_pipe_num, + &to_ipa_devs[3]->mem, + ipa_gsi_hdl); + if (res) + goto fail; + +fail: + /* cleanup and tear down goes here */ + return res; +} + + +/* + Configures the system as follows: + This configuration is for 4 input pipes and 3 output pipes: + /dev/to_ipa_0 -> MEM -> GSI + * -> IPA -> GSI -> MEM -> /dev/from_ipa_0 + /dev/to_ipa_1 -> MEM -> GSI + * -> IPA -> GSI -> MEM -> /dev/from_ipa_1 + /dev/to_ipa_2 -> MEM -> GSI + * -> IPA -> GSI -> MEM -> /dev/from_ipa_0 + /dev/to_ipa_3 -> MEM -> GSI + * -> IPA -> GSI -> MEM -> /dev/from_ipa_2 + to_ipa_1, to_ipa_2, from_ipa_0 & + from_ipa_2 transfer MBIM aggregated packets + to_ipa_0, to_ipa_3 & from_ipa_1 transfer raw packets +*/ +int configure_system_9(void) +{ + int res = 0; + struct ipa_ep_cfg ipa_ep_cfg; + enum ipa_aggr_mode mode; + struct ipa_sys_connect_params sys_in; + unsigned long ipa_gsi_hdl; + u32 ipa_pipe_num; + + mode = IPA_MBIM_AGGR; + res = ipa_set_aggr_mode(mode); + if (res) + goto fail; + res = ipa_set_single_ndp_per_mbim(true); + if (res) + goto fail; + + memset(&ipa_ep_cfg, 0, sizeof(ipa_ep_cfg)); + IPATEST_DBG("Configure_system_9 was called\n"); + + /* Setup GSI pipes */ + to_ipa_devs[0]->dma_ep.src_pipe_index = 4; + to_ipa_devs[0]->dma_ep.dest_pipe_index = 5; + to_ipa_devs[1]->dma_ep.src_pipe_index = 6; + to_ipa_devs[1]->dma_ep.dest_pipe_index = 7; + to_ipa_devs[2]->dma_ep.src_pipe_index = 8; + to_ipa_devs[2]->dma_ep.dest_pipe_index = 9; + to_ipa_devs[3]->dma_ep.src_pipe_index = 10; + to_ipa_devs[3]->dma_ep.dest_pipe_index = 11; + + from_ipa_devs[0]->dma_ep.src_pipe_index = 14; + from_ipa_devs[0]->dma_ep.dest_pipe_index = 15; + from_ipa_devs[1]->dma_ep.src_pipe_index = 16; + from_ipa_devs[1]->dma_ep.dest_pipe_index = 17; + from_ipa_devs[2]->dma_ep.src_pipe_index = 18; + from_ipa_devs[2]->dma_ep.dest_pipe_index = 19; + + /* configure aggregation on Tx */ + ipa_ep_cfg.aggr.aggr_en = IPA_ENABLE_AGGR; + ipa_ep_cfg.aggr.aggr = IPA_MBIM_16; + ipa_ep_cfg.aggr.aggr_byte_limit = 1; + ipa_ep_cfg.aggr.aggr_time_limit = 0; + ipa_ep_cfg.hdr.hdr_len = 1; + + /* Connect IPA --> APPS MEM */ + memset(&sys_in, 0, sizeof(sys_in)); + sys_in.client = IPA_CLIENT_TEST_CONS; + sys_in.ipa_ep_cfg = ipa_ep_cfg; + if (ipa3_sys_setup(&sys_in, &ipa_gsi_hdl, &ipa_pipe_num, + &from_ipa_devs[0]->ipa_client_hdl, false)) + goto fail; + + res = connect_ipa_to_apps(&from_ipa_devs[0]->ep, + IPA_CLIENT_TEST_CONS, + ipa_pipe_num, + ipa_gsi_hdl); + if (res) + goto fail; + + /* Connect IPA --> APPS MEM */ + memset(&sys_in, 0, sizeof(sys_in)); + sys_in.client = IPA_CLIENT_TEST3_CONS; + if (ipa3_sys_setup(&sys_in, &ipa_gsi_hdl, &ipa_pipe_num, + &from_ipa_devs[1]->ipa_client_hdl, false)) + goto fail; + + res = connect_ipa_to_apps(&from_ipa_devs[1]->ep, + IPA_CLIENT_TEST3_CONS, + ipa_pipe_num, + ipa_gsi_hdl); + if (res) + goto fail; + + /* configure aggregation on Tx */ + ipa_ep_cfg.aggr.aggr_en = IPA_ENABLE_AGGR; + ipa_ep_cfg.aggr.aggr = IPA_MBIM_16; + ipa_ep_cfg.aggr.aggr_byte_limit = 1; + ipa_ep_cfg.aggr.aggr_time_limit = 30; + if (ipa_get_hw_type() >= IPA_HW_v4_2) + ipa_ep_cfg.aggr.aggr_time_limit *= 1000; + ipa_ep_cfg.hdr.hdr_len = 1; + + /* Connect IPA --> APPS MEM */ + memset(&sys_in, 0, sizeof(sys_in)); + sys_in.client = IPA_CLIENT_TEST2_CONS; + sys_in.ipa_ep_cfg = ipa_ep_cfg; + if (ipa3_sys_setup(&sys_in, &ipa_gsi_hdl, &ipa_pipe_num, + &from_ipa_devs[2]->ipa_client_hdl, false)) + goto fail; + + res = connect_ipa_to_apps(&from_ipa_devs[2]->ep, + IPA_CLIENT_TEST2_CONS, + ipa_pipe_num, + ipa_gsi_hdl); + if (res) + goto fail; + + /* Prepare EP configuration details */ + memset(&ipa_ep_cfg, 0, sizeof(ipa_ep_cfg)); + ipa_ep_cfg.mode.mode = IPA_DMA; + ipa_ep_cfg.mode.dst = IPA_CLIENT_TEST_CONS; + + memset(&sys_in, 0, sizeof(sys_in)); + sys_in.client = IPA_CLIENT_TEST3_PROD; + sys_in.ipa_ep_cfg = ipa_ep_cfg; + if (ipa3_sys_setup(&sys_in, &ipa_gsi_hdl, &ipa_pipe_num, + &to_ipa_devs[0]->ipa_client_hdl, false)) + goto fail; + + /* Connect APPS MEM --> Tx IPA */ + res = connect_apps_to_ipa(&to_ipa_devs[0]->ep, + IPA_CLIENT_TEST3_PROD, + ipa_pipe_num, + &to_ipa_devs[0]->mem, + ipa_gsi_hdl); + if (res) + goto fail; + + /* configure deaggregation on Rx */ + memset(&ipa_ep_cfg, 0, sizeof(ipa_ep_cfg)); + ipa_ep_cfg.mode.mode = IPA_DMA; + ipa_ep_cfg.mode.dst = IPA_CLIENT_TEST3_CONS; + ipa_ep_cfg.aggr.aggr_en = IPA_ENABLE_DEAGGR; + ipa_ep_cfg.aggr.aggr = IPA_MBIM_16; + + memset(&sys_in, 0, sizeof(sys_in)); + sys_in.client = IPA_CLIENT_TEST_PROD; + sys_in.ipa_ep_cfg = ipa_ep_cfg; + if (ipa3_sys_setup(&sys_in, &ipa_gsi_hdl, &ipa_pipe_num, + &to_ipa_devs[1]->ipa_client_hdl, false)) + goto fail; + + /* Connect APPS MEM --> Tx IPA */ + res = connect_apps_to_ipa(&to_ipa_devs[1]->ep, + IPA_CLIENT_TEST_PROD, + ipa_pipe_num, + &to_ipa_devs[1]->mem, + ipa_gsi_hdl); + if (res) + goto fail; + + /* configure deaggregation on Rx */ + memset(&ipa_ep_cfg, 0, sizeof(ipa_ep_cfg)); + ipa_ep_cfg.mode.mode = IPA_DMA; + ipa_ep_cfg.mode.dst = IPA_CLIENT_TEST_CONS; + ipa_ep_cfg.aggr.aggr_en = IPA_ENABLE_DEAGGR; + ipa_ep_cfg.aggr.aggr = IPA_MBIM_16; + + memset(&sys_in, 0, sizeof(sys_in)); + sys_in.client = IPA_CLIENT_TEST2_PROD; + sys_in.ipa_ep_cfg = ipa_ep_cfg; + if (ipa3_sys_setup(&sys_in, &ipa_gsi_hdl, &ipa_pipe_num, + &to_ipa_devs[2]->ipa_client_hdl, false)) + goto fail; + + /* Connect APPS MEM --> Tx IPA */ + res = connect_apps_to_ipa(&to_ipa_devs[2]->ep, + IPA_CLIENT_TEST2_PROD, + ipa_pipe_num, + &to_ipa_devs[2]->mem, + ipa_gsi_hdl); + if (res) + goto fail; + + /* Prepare EP configuration details */ + memset(&ipa_ep_cfg, 0, sizeof(ipa_ep_cfg)); + ipa_ep_cfg.mode.mode = IPA_DMA; + ipa_ep_cfg.mode.dst = IPA_CLIENT_TEST2_CONS; + + memset(&sys_in, 0, sizeof(sys_in)); + sys_in.client = IPA_CLIENT_TEST4_PROD; + sys_in.ipa_ep_cfg = ipa_ep_cfg; + if (ipa3_sys_setup(&sys_in, &ipa_gsi_hdl, &ipa_pipe_num, + &to_ipa_devs[3]->ipa_client_hdl, false)) + goto fail; + + /* Connect APPS MEM --> Tx IPA */ + res = connect_apps_to_ipa(&to_ipa_devs[3]->ep, + IPA_CLIENT_TEST4_PROD, + ipa_pipe_num, + &to_ipa_devs[3]->mem, + ipa_gsi_hdl); + if (res) + goto fail; + +fail: + /* cleanup and tear down goes here */ + return res; +} + +/* + Configures the system as follows: + This configuration is for 1 input pipe and 1 output pipe: + /dev/to_ipa_0 -> MEM -> GSI -> IPA -> GSI -> MEM -> /dev/from_ipa_0 + /dev/to_ipa_1 -> MEM -> GSI -> IPA -> GSI -> MEM -> /dev/from_ipa_1 + from_ipa_0, from_ipa_1 transfer IPA_MBIM_AGGR aggregated packets + to_ipa_0, to_ipa_1 transfer raw packets +*/ +int configure_system_10(void) +{ + int res = 0; + struct ipa_ep_cfg ipa_ep_cfg; + enum ipa_aggr_mode mode; + struct ipa_sys_connect_params sys_in; + unsigned long ipa_gsi_hdl; + u32 ipa_pipe_num; + + mode = IPA_MBIM_AGGR; + res = ipa_set_aggr_mode(mode); + if (res) + goto fail; + res = ipa_set_single_ndp_per_mbim(false); + if (res) + goto fail; + + memset(&ipa_ep_cfg, 0, sizeof(ipa_ep_cfg)); + IPATEST_DBG("Configure_system_10 was called\n"); + + /* Setup GSI pipes */ + to_ipa_devs[0]->dma_ep.src_pipe_index = 4; + to_ipa_devs[0]->dma_ep.dest_pipe_index = 5; + + from_ipa_devs[0]->dma_ep.src_pipe_index = 6; + from_ipa_devs[0]->dma_ep.dest_pipe_index = 7; + + /* configure aggregation on Tx */ + ipa_ep_cfg.aggr.aggr_en = IPA_ENABLE_AGGR; + ipa_ep_cfg.aggr.aggr = IPA_MBIM_16; + ipa_ep_cfg.aggr.aggr_byte_limit = 0; + ipa_ep_cfg.aggr.aggr_time_limit = 0; + ipa_ep_cfg.hdr.hdr_len = 1; + + /* Connect IPA --> APPS MEM */ + memset(&sys_in, 0, sizeof(sys_in)); + sys_in.client = IPA_CLIENT_TEST_CONS; + sys_in.ipa_ep_cfg = ipa_ep_cfg; + if (ipa3_sys_setup(&sys_in, &ipa_gsi_hdl, &ipa_pipe_num, + &from_ipa_devs[0]->ipa_client_hdl, false)) + goto fail; + + res = connect_ipa_to_apps(&from_ipa_devs[0]->ep, + IPA_CLIENT_TEST_CONS, + ipa_pipe_num, + ipa_gsi_hdl); + if (res) + goto fail; + + /* Prepare EP configuration details */ + memset(&ipa_ep_cfg, 0, sizeof(ipa_ep_cfg)); + ipa_ep_cfg.mode.mode = IPA_DMA; + ipa_ep_cfg.mode.dst = IPA_CLIENT_TEST_CONS; + + memset(&sys_in, 0, sizeof(sys_in)); + sys_in.client = IPA_CLIENT_TEST_PROD; + sys_in.ipa_ep_cfg = ipa_ep_cfg; + if (ipa3_sys_setup(&sys_in, &ipa_gsi_hdl, + &ipa_pipe_num, &to_ipa_devs[0]->ipa_client_hdl, false)) + goto fail; + + /* Connect APPS MEM --> Tx IPA */ + res = connect_apps_to_ipa(&to_ipa_devs[0]->ep, + IPA_CLIENT_TEST_PROD, + ipa_pipe_num, + &to_ipa_devs[0]->mem, + ipa_gsi_hdl); + if (res) + goto fail; + +fail: + /* cleanup and tear down goes here */ + return res; +} + +int configure_system_12(void) +{ + int res = 0; + struct ipa_ep_cfg ipa_ep_cfg; + enum ipa_aggr_mode mode; + char qcncm_sig[3]; + + struct ipa_sys_connect_params sys_in; + unsigned long ipa_gsi_hdl; + u32 ipa_pipe_num; + mode = IPA_QCNCM_AGGR; + res = ipa_set_aggr_mode(mode); + if (res) + goto fail; + res = ipa_set_single_ndp_per_mbim(false); + if (res) + goto fail; + qcncm_sig[0] = 0x51; + qcncm_sig[1] = 0x4e; + qcncm_sig[2] = 0x44; + res = ipa_set_qcncm_ndp_sig(qcncm_sig); + if (res) + goto fail; + + memset(&ipa_ep_cfg, 0, sizeof(ipa_ep_cfg)); + + + /* Connect IPA -> first Rx GSI */ + memset(&ipa_ep_cfg, 0, sizeof(ipa_ep_cfg)); + ipa_ep_cfg.aggr.aggr_en = IPA_ENABLE_AGGR; + ipa_ep_cfg.aggr.aggr = IPA_MBIM_16; + ipa_ep_cfg.aggr.aggr_byte_limit = 1; + ipa_ep_cfg.aggr.aggr_time_limit = 0; + ipa_ep_cfg.hdr.hdr_len = 1; + + /* Connect first Rx IPA --> APPS MEM */ + memset(&sys_in, 0, sizeof(sys_in)); + sys_in.client = IPA_CLIENT_TEST2_CONS; + sys_in.ipa_ep_cfg = ipa_ep_cfg; + if (ipa3_sys_setup(&sys_in, &ipa_gsi_hdl, + &ipa_pipe_num, &from_ipa_devs[0]->ipa_client_hdl, false)) + goto fail; + + res = connect_ipa_to_apps(&from_ipa_devs[0]->ep, + IPA_CLIENT_TEST2_CONS, + ipa_pipe_num, + ipa_gsi_hdl); + if (res) + goto fail; + + memset(&ipa_ep_cfg, 0, sizeof(ipa_ep_cfg)); + + /* Connect second Rx IPA --> APPS MEM */ + memset(&sys_in, 0, sizeof(sys_in)); + sys_in.client = IPA_CLIENT_TEST3_CONS; + sys_in.ipa_ep_cfg = ipa_ep_cfg; + if (ipa3_sys_setup(&sys_in, &ipa_gsi_hdl, + &ipa_pipe_num, &from_ipa_devs[1]->ipa_client_hdl, false)) + goto fail; + + res = connect_ipa_to_apps(&from_ipa_devs[1]->ep, + IPA_CLIENT_TEST3_CONS, + ipa_pipe_num, + ipa_gsi_hdl); + if (res) + goto fail; + + /* Connect IPA -> first Rx GSI */ + memset(&ipa_ep_cfg, 0, sizeof(ipa_ep_cfg)); + ipa_ep_cfg.aggr.aggr_en = IPA_ENABLE_AGGR; + ipa_ep_cfg.aggr.aggr = IPA_MBIM_16; + ipa_ep_cfg.aggr.aggr_byte_limit = 0; + ipa_ep_cfg.aggr.aggr_time_limit = 30; + if (ipa_get_hw_type() >= IPA_HW_v4_2) + ipa_ep_cfg.aggr.aggr_time_limit *= 1000; + ipa_ep_cfg.hdr.hdr_len = 1; + + /* Connect first Rx IPA --> APPS MEM */ + memset(&sys_in, 0, sizeof(sys_in)); + sys_in.client = IPA_CLIENT_TEST_CONS; + sys_in.ipa_ep_cfg = ipa_ep_cfg; + if (ipa3_sys_setup(&sys_in, &ipa_gsi_hdl, + &ipa_pipe_num, &from_ipa_devs[2]->ipa_client_hdl, false)) + goto fail; + + res = connect_ipa_to_apps(&from_ipa_devs[2]->ep, + IPA_CLIENT_TEST_CONS, + ipa_pipe_num, + ipa_gsi_hdl); + if (res) + goto fail; + + /* Connect IPA -> first Rx GSI */ + memset(&ipa_ep_cfg, 0, sizeof(ipa_ep_cfg)); + ipa_ep_cfg.aggr.aggr_en = IPA_ENABLE_AGGR; + ipa_ep_cfg.aggr.aggr = IPA_MBIM_16; + ipa_ep_cfg.aggr.aggr_byte_limit = 0; + ipa_ep_cfg.aggr.aggr_time_limit = 0; + ipa_ep_cfg.hdr.hdr_len = 1; + + /* Connect first Rx IPA --> APPS MEM */ + memset(&sys_in, 0, sizeof(sys_in)); + sys_in.client = IPA_CLIENT_TEST4_CONS; + sys_in.ipa_ep_cfg = ipa_ep_cfg; + if (ipa3_sys_setup(&sys_in, &ipa_gsi_hdl, + &ipa_pipe_num, &from_ipa_devs[3]->ipa_client_hdl, false)) + goto fail; + + res = connect_ipa_to_apps(&from_ipa_devs[3]->ep, + IPA_CLIENT_TEST4_CONS, + ipa_pipe_num, + ipa_gsi_hdl); + if (res) + goto fail; + + /* Connect Tx GSI -> IPA */ + /* Prepare an endpoint configuration structure */ + res = configure_ipa_endpoint(&ipa_ep_cfg, IPA_BASIC); + if (res) + goto fail; + + memset(&sys_in, 0, sizeof(sys_in)); + sys_in.client = IPA_CLIENT_TEST_PROD; + sys_in.ipa_ep_cfg = ipa_ep_cfg; + if (ipa3_sys_setup(&sys_in, &ipa_gsi_hdl, + &ipa_pipe_num, &to_ipa_devs[0]->ipa_client_hdl, false)) + goto fail; + + /* Connect APPS MEM --> Tx IPA */ + res = connect_apps_to_ipa(&to_ipa_devs[0]->ep, + IPA_CLIENT_TEST_PROD, + ipa_pipe_num, + &to_ipa_devs[0]->mem, + ipa_gsi_hdl); + + if (res) + goto fail; + + /* Connect Tx GSI -> IPA */ + /* Prepare an endpoint configuration structure */ + res = configure_ipa_endpoint(&ipa_ep_cfg, IPA_BASIC); + if (res) + goto fail; + ipa_ep_cfg.aggr.aggr_en = IPA_ENABLE_DEAGGR; + ipa_ep_cfg.aggr.aggr = IPA_MBIM_16; + + memset(&sys_in, 0, sizeof(sys_in)); + sys_in.client = IPA_CLIENT_TEST2_PROD; + sys_in.ipa_ep_cfg = ipa_ep_cfg; + if (ipa3_sys_setup(&sys_in, &ipa_gsi_hdl, + &ipa_pipe_num, &to_ipa_devs[1]->ipa_client_hdl, false)) + goto fail; + + /* Connect APPS MEM --> Tx IPA */ + res = connect_apps_to_ipa(&to_ipa_devs[1]->ep, + IPA_CLIENT_TEST2_PROD, + ipa_pipe_num, + &to_ipa_devs[1]->mem, + ipa_gsi_hdl); + + if (res) + goto fail; + +fail: + /* cleanup and tear down goes here */ + return res; +} + +void suspend_handler(enum ipa_irq_type interrupt, + void *private_data, + void *interrupt_data) +{ + u32 *suspend_data; + u32 clnt_hdl; + u32 gsi_chan_hdl; + struct ipa_ep_cfg_ctrl ipa_to_usb_ep_cfg_ctrl; + int i, res; + + suspend_data = + ((struct ipa_tx_suspend_irq_data *)interrupt_data)->endpoints; + clnt_hdl = + ((struct ipa_tx_suspend_private_data *)private_data)->clnt_hdl; + gsi_chan_hdl = + ((struct ipa_tx_suspend_private_data *)private_data)->gsi_chan_hdl; + + IPATEST_DBG("in suspend handler: interrupt=%d, clnt_hdl=%d, private_data=%d, interrupt_data=%d", + interrupt, clnt_hdl, suspend_data[0], suspend_data[1]); + for (i = 0; i < IPA_EP_ARR_SIZE; i++) + IPATEST_DBG("%d", suspend_data[i]); + + IPATEST_DBG("\nEnabling back data path for IPA_CLIENT_USB_CONS\n"); + memset(&ipa_to_usb_ep_cfg_ctrl, 0 , sizeof(struct ipa_ep_cfg_ctrl)); + ipa_to_usb_ep_cfg_ctrl.ipa_ep_suspend = false; + + if(ipa_get_hw_type() >= IPA_HW_v4_0) + res = gsi_start_channel(gsi_chan_hdl); + else + res = ipa_cfg_ep_ctrl(clnt_hdl, &ipa_to_usb_ep_cfg_ctrl); + + if (res) + IPATEST_ERR("failed enabling back data path for IPA_CLIENT_USB_CONS\n"); +} +/* + * Configures the system as follows: + * This configuration is for one input pipe and one output pipe + * where both are USB1 + * /dev/to_ipa_0 -> MEM -> GSI -> IPA -> GSI-> MEM -> /dev/from_ipa_0 + * Those clients will be configured in DMA mode thus no Header removal/insertion + * will be made on their data. + * Then disable USB_CONS EP for creating the suspend interrupt and register + * a handler for it. +*/ +int configure_system_19(void) +{ + struct ipa_ep_cfg_ctrl ipa_to_usb_ep_cfg_ctrl; + int res; + + res = configure_system_1(); + if (res) { + IPATEST_ERR("configure system (19) failed\n"); + goto fail; + } + + memset(&ipa_to_usb_ep_cfg_ctrl, 0 , sizeof(struct ipa_ep_cfg_ctrl)); + ipa_to_usb_ep_cfg_ctrl.ipa_ep_suspend = true; + + if(ipa_get_hw_type() >= IPA_HW_v4_0) + res = ipa_stop_gsi_channel(from_ipa_devs[0]->ipa_client_hdl); + else + res = ipa_cfg_ep_ctrl(from_ipa_devs[0]->ipa_client_hdl, &ipa_to_usb_ep_cfg_ctrl); + + if (res) { + IPATEST_ERR("end-point ctrl register configuration failed\n"); + goto fail; + } + IPATEST_DBG("end-point ctrl register configured successfully (ipa_ep_suspend = true)\n"); + + return 0; + +fail: + + return res; +} + +int configure_system_18(void) +{ + int res = 0; + struct ipa_ep_cfg ipa_ep_cfg; + struct ipa_sys_connect_params sys_in; + unsigned long ipa_gsi_hdl; + u32 ipa_pipe_num; + + datapath_ds_clean(); + + /* Connect IPA -> Rx GSI */ + memset(&ipa_ep_cfg, 0, sizeof(ipa_ep_cfg)); + + /* Connect Rx IPA --> APPS MEM */ + memset(&sys_in, 0, sizeof(sys_in)); + sys_in.client = IPA_CLIENT_TEST_CONS; + sys_in.ipa_ep_cfg = ipa_ep_cfg; + sys_in.notify = notify_ipa_write_done; + if (ipa3_sys_setup(&sys_in, + &ipa_gsi_hdl, + &ipa_pipe_num, + &from_ipa_devs[0]->ipa_client_hdl, + false)) + goto fail; + + res = connect_ipa_to_apps(&from_ipa_devs[0]->ep, + IPA_CLIENT_TEST_CONS, + ipa_pipe_num, + ipa_gsi_hdl); + if (res) + goto fail; + + memset(&ipa_ep_cfg, 0, sizeof(ipa_ep_cfg)); + + /* Connect Tx GSI -> IPA */ + /* Prepare an endpoint configuration structure */ + res = configure_ipa_endpoint(&ipa_ep_cfg, IPA_BASIC); + if (res) + goto fail; + + memset(&ipa_ep_cfg, 0, sizeof(ipa_ep_cfg)); + + memset(&sys_in, 0, sizeof(sys_in)); + sys_in.client = IPA_CLIENT_TEST_PROD; + sys_in.ipa_ep_cfg = ipa_ep_cfg; + sys_in.notify = notify_ipa_received; + if (ipa3_sys_setup(&sys_in, + &ipa_gsi_hdl, + &ipa_pipe_num, + &to_ipa_devs[0]->ipa_client_hdl, + false)) + goto fail; + + /* Connect APPS MEM --> Tx IPA */ + res = connect_apps_to_ipa(&to_ipa_devs[0]->ep, + IPA_CLIENT_TEST_PROD, + ipa_pipe_num, + &to_ipa_devs[0]->mem, + ipa_gsi_hdl); + + if (res) + goto fail; + +fail: + /* cleanup and tear down goes here */ + return res; +} + + +/** + * Read File. + * + * @note This function is used by User Mode Application + * in order to read data from the device node /dev/ipa_exception_pipe. + * This implementation assumes Single Reader and Single Writer. + * + */ +ssize_t exception_kfifo_read(struct file *filp, char __user *buf, + size_t count, loff_t *p_pos) +{ + int ret = 0; + size_t data_len = 0; + unsigned int copied; + + if (kfifo_is_empty( + &(p_exception_hdl_data-> + notify_cb_data.exception_kfifo))) { + /* Optimization*/ + + IPATEST_DBG("No Data in exception pipe, Sleeping...\n"); + msleep(200); + IPATEST_DBG("Sleeping Done...\n"); + if (kfifo_is_empty(&(p_exception_hdl_data-> + notify_cb_data.exception_kfifo))) { + IPATEST_DBG("No Data in exception pipe.Returning\n"); + return 0; + } + } + data_len = kfifo_peek_len + (&(p_exception_hdl_data + ->notify_cb_data.exception_kfifo)); + if (data_len > count) { + IPATEST_ERR("buffer(%zu) too small (%zu) required\n", + data_len, count); + return -ENOSPC; + } + ret = kfifo_to_user(& + (p_exception_hdl_data-> + notify_cb_data.exception_kfifo) + , buf, data_len, &copied); +#if (EXCEPTION_KFIFO_DEBUG_VERBOSE) + { + int i = 0; + + IPATEST_DBG("Exception packet's length=%zu, Packet's content:\n" + , data_len); + if (data_len - 3 > 0) { + for (i = 0; i < data_len-4; i += 4) { + IPATEST_DUMP("%02x %02x %02x %02x\n", + (buf)[i], (buf)[i+1], + (buf)[i+2], (buf)[i+3]); + } + } + } +#endif + return ret ? ret : copied; +} + +/** + * Write File. + * + * @note This function is used by User + * in order to write data to the device node /dev/ipa_exception_pipe. + * This implementation assumes Single Reader and Single Writer. + * + */ +ssize_t exception_kfifo_write(struct file *file, const char __user *buf, + size_t count, loff_t *ppos) +{ + int ret; + unsigned int copied; + + ret = kfifo_from_user + (&(p_exception_hdl_data->notify_cb_data.exception_kfifo) + , buf, count, &copied); + if (ret) { + IPATEST_ERR("(%d/%zu) Bytes were written to kfifo.\n", + copied, count); + } + return ret ? ret : copied; +} + +static const struct file_operations exception_fops = { + .owner = THIS_MODULE, + .read = exception_kfifo_read, + .write = exception_kfifo_write, +}; + +void notify_upon_exception(void *priv, + enum ipa_dp_evt_type evt, unsigned long data) +{ + int i = 0; + size_t data_len; + int res = 0; + char *p_data = NULL; + struct sk_buff *p_sk_buff = (struct sk_buff *)data; + struct notify_cb_data_st *p_notify_cb_data + = (struct notify_cb_data_st *)priv; + + IPATEST_DBG("was called, evt=%s(%d)", + (evt == IPA_RECEIVE) ? + "IPA_RECEIVE" : + "IPA_WRITE_DONE", evt); + if (IPA_RECEIVE != evt) { + IPATEST_ERR("unexpected value of evt == %d\n", evt); + return; + } + + data_len = p_sk_buff->len; /* store len */ + p_data = p_sk_buff->data; /* store pointer to the data */ + +#if (EXCEPTION_KFIFO_DEBUG_VERBOSE) + IPATEST_DBG("Exception packet length = %zu,Packet content:\n", + data_len); + for (i = 0; i < data_len - 4; i += 4) { + IPATEST_DUMP("%02x %02x %02x %02x", + (p_data)[i], (p_data)[i+1], + (p_data)[i+2], (p_data)[i+3]); + } +#endif + res = kfifo_in( + &p_notify_cb_data->exception_kfifo, + p_data , data_len); + if (res != data_len) { + IPATEST_ERR("kfifo_in copied %d Bytes instead of %zu\n", + res, data_len); + return; + } +} +/* + * This function Inits the KFIFO and the Device Node of the exceptions + */ +int exception_hdl_init(void) +{ + int res = 0; + struct notify_cb_data_st *p_notify_cb_data; + + IPATEST_DBG("called.\n"); + + if (NULL != p_exception_hdl_data) { + IPATEST_ERR("p_exception_hdl_data is initialized?=(0x%px)\n", + p_exception_hdl_data); + return -EINVAL; + } + p_exception_hdl_data = + kzalloc(sizeof(struct exception_hdl_data), GFP_KERNEL); + if (NULL == p_exception_hdl_data) { + IPATEST_ERR("kzalloc return NULL, can't alloc %zu Bytes\n", + sizeof(struct exception_hdl_data)); + return -ENOMEM; + } + IPATEST_DBG("Continue...\n"); + p_notify_cb_data = &(p_exception_hdl_data->notify_cb_data); + + res = kfifo_alloc(&(p_notify_cb_data->exception_kfifo) + , EXCEPTION_KFIFO_SIZE*(sizeof(char)*RX_DESCRIPTOR_SIZE) + , GFP_KERNEL); + if (0 != res) { + IPATEST_ERR("kfifo_alloc returned error (%d)\n", + res); + return res; + } + res = alloc_chrdev_region(&p_exception_hdl_data->dev_num + , 0, 1, EXCEPTION_DRV_NAME); + if (0 != res) { + IPATEST_ERR("alloc_chrdev_region failed (%d)\n", res); + return res; + } + p_exception_hdl_data->class = + class_create(THIS_MODULE, EXCEPTION_DRV_NAME); + p_exception_hdl_data->dev = + device_create(p_exception_hdl_data->class + , NULL, p_exception_hdl_data->dev_num, + ipa_test, EXCEPTION_DRV_NAME); + if (IS_ERR(p_exception_hdl_data->dev)) { + IPATEST_ERR("device_create returned error\n"); + return -ENODEV; + } + p_exception_hdl_data->p_cdev = cdev_alloc(); + if (NULL == p_exception_hdl_data->p_cdev) { + IPATEST_ERR("cdev_alloc() returned NULL (0x%px)\n" + , p_exception_hdl_data->p_cdev); + return -EINVAL; + } + cdev_init(p_exception_hdl_data->p_cdev, &exception_fops); + p_exception_hdl_data->p_cdev->owner = THIS_MODULE; + res = cdev_add(p_exception_hdl_data->p_cdev + , p_exception_hdl_data->dev_num, 1); + if (0 != res) { + IPATEST_ERR("cdev_add failed (%d)\n", res); + return res; + } + + IPATEST_DBG("completed.(%d)\n", res); + return res; +} +/* + * Clear the Exception Device and KFIFO + */ +void exception_hdl_exit(void) +{ + + unregister_chrdev_region + (p_exception_hdl_data->dev_num, 1); + kfifo_free(&(p_exception_hdl_data + ->notify_cb_data.exception_kfifo)); + /* freeing kfifo */ + memset(&(p_exception_hdl_data + ->notify_cb_data.exception_kfifo), 0, + sizeof(p_exception_hdl_data + ->notify_cb_data.exception_kfifo)); + kfree(p_exception_hdl_data); + p_exception_hdl_data = NULL; +} + +/* Configuration used for Exception Tests */ +int configure_system_7(void) +{ + int res = 0; + struct ipa_ep_cfg ipa_ep_cfg; + + struct ipa_sys_connect_params sys_in; + unsigned long ipa_gsi_hdl; + u32 ipa_pipe_num; + + memset(&ipa_ep_cfg, 0, sizeof(ipa_ep_cfg)); + + /* Connect first Rx IPA --> APPS MEM */ + memset(&sys_in, 0, sizeof(sys_in)); + sys_in.client = IPA_CLIENT_TEST2_CONS; + if (ipa3_sys_setup(&sys_in, &ipa_gsi_hdl, &ipa_pipe_num, + &from_ipa_devs[0]->ipa_client_hdl, + false)) + goto fail; + + res = connect_ipa_to_apps(&from_ipa_devs[0]->ep, + IPA_CLIENT_TEST2_CONS, + ipa_pipe_num, + ipa_gsi_hdl); + if (res) + goto fail; + + /* Connect second Rx IPA --> APPS MEM */ + memset(&sys_in, 0, sizeof(sys_in)); + sys_in.client = IPA_CLIENT_TEST3_CONS; + if (ipa3_sys_setup(&sys_in, &ipa_gsi_hdl, &ipa_pipe_num, + &from_ipa_devs[1]->ipa_client_hdl, + false)) + goto fail; + + res = connect_ipa_to_apps(&from_ipa_devs[1]->ep, + IPA_CLIENT_TEST3_CONS, + ipa_pipe_num, + ipa_gsi_hdl); + if (res) + goto fail; + + /* Connect third (Default) Rx IPA --> APPS MEM */ + memset(&sys_in, 0, sizeof(sys_in)); + sys_in.client = IPA_CLIENT_TEST4_CONS; + if (ipa3_sys_setup(&sys_in, &ipa_gsi_hdl, &ipa_pipe_num, + &from_ipa_devs[2]->ipa_client_hdl, + false)) + goto fail; + + res = connect_ipa_to_apps(&from_ipa_devs[2]->ep, + IPA_CLIENT_TEST4_CONS, + ipa_pipe_num, + ipa_gsi_hdl); + if (res) + goto fail; + + + /* Connect Tx GSI -> IPA */ + /* Prepare an endpoint configuration structure */ + res = configure_ipa_endpoint(&ipa_ep_cfg, IPA_BASIC); + if (res) + goto fail; + + memset(&sys_in, 0, sizeof(sys_in)); + sys_in.client = IPA_CLIENT_TEST_PROD; + sys_in.ipa_ep_cfg = ipa_ep_cfg; + sys_in.notify = ¬ify_upon_exception; + sys_in.priv = &(p_exception_hdl_data->notify_cb_data); + + if (ipa3_sys_setup(&sys_in, &ipa_gsi_hdl, &ipa_pipe_num, + &to_ipa_devs[0]->ipa_client_hdl, + false)) + goto fail; + + /* Connect APPS MEM --> Tx IPA */ + res = connect_apps_to_ipa(&to_ipa_devs[0]->ep, + IPA_CLIENT_TEST_PROD, + ipa_pipe_num, + &to_ipa_devs[0]->mem, + ipa_gsi_hdl); + + if (res) + goto fail; +fail: + /* cleanup and tear down goes here */ + return res; +} + +void destroy_channel_device(struct channel_dev *channel_dev) +{ + int res = 0; + struct device *pdev; + + IPATEST_DBG("Destroying device channel_dev = 0x%px,name %s.\n", + channel_dev, channel_dev->name); + + IPATEST_DBG("ep=0x%px gsi_chan_hdl=0x%lx\n", &channel_dev->ep, channel_dev->ep.gsi_chan_hdl); + + pdev = ipa3_get_pdev(); + + if (channel_dev->ep.gsi_valid && pdev != NULL) { + IPATEST_DBG("stopping channel 0x%lx\n", channel_dev->ep.gsi_chan_hdl); + res = ipa_stop_gsi_channel(channel_dev->ipa_client_hdl); + if (res != GSI_STATUS_SUCCESS) + IPATEST_ERR("ipa_stop_gsi_channel failed %d\n\n", res); + + IPATEST_DBG("reset channel 0x%lx\n", channel_dev->ep.gsi_chan_hdl); + res = gsi_reset_channel(channel_dev->ep.gsi_chan_hdl); + if (res != GSI_STATUS_SUCCESS) + IPATEST_ERR("gsi_reset_channel failed %d\n\n", res); + + IPATEST_DBG("deallocate channel 0x%lx\n", channel_dev->ep.gsi_chan_hdl); + res = gsi_dealloc_channel(channel_dev->ep.gsi_chan_hdl); + if (res != GSI_STATUS_SUCCESS) + IPATEST_ERR("gsi_dealloc_channel failed %d\n\n", res); + + dma_free_coherent(pdev, channel_dev->ep.gsi_channel_props.ring_len, channel_dev->ep.gsi_channel_props.ring_base_vaddr, channel_dev->ep.gsi_channel_props.ring_base_addr); + + IPATEST_DBG("deallocate channel event ring 0x%lx\n", channel_dev->ep.gsi_evt_ring_hdl); + res = gsi_dealloc_evt_ring(channel_dev->ep.gsi_evt_ring_hdl); + if (res != GSI_STATUS_SUCCESS) + IPATEST_ERR("gsi_dealloc_evt_ring failed %d\n\n", res); + dma_free_coherent(pdev, channel_dev->ep.gsi_evt_ring_props.ring_len, channel_dev->ep.gsi_evt_ring_props.ring_base_vaddr, channel_dev->ep.gsi_evt_ring_props.ring_base_addr); + + res = ipa3_sys_teardown(channel_dev->ipa_client_hdl); + if (res) { + IPATEST_ERR("Failure on ipa_sys_teardown()," + " channel_dev = 0x%px, res = %d.\n", + channel_dev, res); + } + } + + + cdev_del(&channel_dev->cdev); + memset(&channel_dev->cdev, 0, sizeof(channel_dev->cdev)); + device_destroy(channel_dev->class, channel_dev->dev_num); + unregister_chrdev_region(channel_dev->dev_num, 1); + class_destroy(channel_dev->class); + test_free_mem(&channel_dev->mem); + memset(channel_dev, 0, sizeof(struct channel_dev)); + kfree(channel_dev); +} + +void destroy_channel_devices(void) +{ + IPATEST_DBG("-----Tear Down----\n"); + while (ipa_test->num_tx_channels > 0) { + IPATEST_DBG("-- num_tx_channels = %d --\n", ipa_test->num_tx_channels); + destroy_channel_device(ipa_test->tx_channels[--ipa_test->num_tx_channels]); + ipa_test->tx_channels[ipa_test->num_tx_channels] = NULL; + } + + while (ipa_test->num_rx_channels > 0) { + IPATEST_DBG("-- num_rx_channels = %d --\n", ipa_test->num_rx_channels); + destroy_channel_device(from_ipa_devs[--ipa_test->num_rx_channels]); + from_ipa_devs[ipa_test->num_rx_channels] = NULL; + } +} + +int register_lan_interface(void) +{ + struct ipa_rx_intf rx_intf; + struct ipa_tx_intf tx_intf; + struct ipa_ioc_tx_intf_prop tx_prop; + struct ipa_ioc_rx_intf_prop rx_prop; + char *name = "rmnet1"; + int res; + + IPATEST_DBG(":new version\n"); + memset(&tx_prop, 0, sizeof(tx_prop)); + tx_prop.ip = IPA_IP_v6; + tx_prop.dst_pipe = IPA_CLIENT_TEST_CONS; + + memset(&rx_prop, 0, sizeof(rx_prop)); + rx_prop.ip = IPA_IP_v6; + rx_prop.src_pipe = IPA_CLIENT_TEST_PROD; + + memset(&rx_intf, 0, sizeof(rx_intf)); + rx_intf.num_props = 1; + rx_intf.prop = &rx_prop; + + memset(&tx_intf, 0, sizeof(tx_intf)); + tx_intf.num_props = 1; + tx_intf.prop = &tx_prop; + + res = ipa_register_intf(name, &tx_intf, &rx_intf); + if (res != 0) + goto fail; + + IPATEST_DBG(":registered interface %s !\n", name); + +fail: + return res; +} + +/* add wlan header to ipa */ + +#define IPA_TO_WLAN_HEADER_NAME "wlan0" +int add_wlan_header(void) +{ + +#define IPA_TO_WLAN_HEADER_LEN 34 + + uint8_t hdr[IPA_TO_WLAN_HEADER_LEN + 1] = { + /* HTC Header - 6 bytes */ + 0x00, 0x00, /* Reserved */ + 0x00, 0x00, /* length to be filled by IPA, + after adding 32 with IP Payload + length 32 will be + programmed while + intializing the header */ + 0x00, 0x00, /* Reserved */ + /* WMI header - 6 bytes*/ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + + /* 802.3 header - 14 bytes*/ + 0x00, 0x03, 0x7f, 0x44, 0x33, 0x89, + /* Des. MAC to be filled by IPA */ + 0x00, 0x03, 0x7f, 0x17, 0x12, 0x69, + /* Src. MAC to be filled by IPA */ + 0x00, 0x00, + /* length can be zero */ + + /* LLC SNAP header - 8 bytes */ + 0xaa, 0xaa, 0x03, 0x00, 0x00, 0x00, + 0x08, 0x00 /* type value(2 bytes) to + be filled by IPA, by reading + from ethernet header */ + /* 0x0800 - IPV4, 0x86dd - IPV6 */ + }; + + int ret = 0; + int len = 0; + struct ipa_ioc_add_hdr *ipa_to_wlan_header_partial; + struct ipa_hdr_add ipa_to_wlan_header; + + memset(&ipa_to_wlan_header, 0, sizeof(ipa_to_wlan_header)); + /* Copy header name */ + memcpy(ipa_to_wlan_header.name, + IPA_TO_WLAN_HEADER_NAME, + sizeof(IPA_TO_WLAN_HEADER_NAME)); + + /* poplate other fields of header add */ + ipa_to_wlan_header.hdr_len = IPA_TO_WLAN_HEADER_LEN; + ipa_to_wlan_header.is_partial = 1; + ipa_to_wlan_header.hdr_hdl = 0; + ipa_to_wlan_header.status = -1; + /* copy the parital header */ + memcpy(ipa_to_wlan_header.hdr, hdr, IPA_TO_WLAN_HEADER_LEN); + + /* Add wlan partial header to ipa */ + len = (sizeof(struct ipa_ioc_add_hdr)) + + (1 * sizeof(struct ipa_hdr_add)); + ipa_to_wlan_header_partial = kmalloc(len, GFP_KERNEL); + if (!ipa_to_wlan_header_partial) { + IPATEST_ERR("Memory allocation failure"); + return false; + } + + ipa_to_wlan_header_partial->commit = 1; + ipa_to_wlan_header_partial->num_hdrs = 1; + memcpy(&ipa_to_wlan_header_partial->hdr[0], + &ipa_to_wlan_header, + sizeof(ipa_to_wlan_header)); + ret = ipa_add_hdr(ipa_to_wlan_header_partial); + if (ret) { + IPATEST_ERR("unable to add wlan header %d", ret); + goto fail; + } else if (ipa_to_wlan_header_partial->hdr[0].status) { + IPATEST_ERR("unable to add wlan header %d", ret); + goto fail; + } + + IPATEST_DBG("added wlan header successfully\n"); + +fail: + kfree(ipa_to_wlan_header_partial); + + return ret; +} + +/* Wlan interface has 4 rx and 1 Tx endpoint */ +int register_wlan_interface(void) +{ + struct ipa_rx_intf rx_intf; + struct ipa_tx_intf tx_intf; + struct ipa_ioc_tx_intf_prop tx_prop[4]; + struct ipa_ioc_rx_intf_prop rx_prop; + char *name = "eth0"; + int res, index = 0; + + res = add_wlan_header(); + if (res) + return res; + + memset(&tx_prop, 0, 4 * sizeof(struct ipa_ioc_tx_intf_prop)); + + index = 0; + tx_prop[index].ip = IPA_IP_v6; + tx_prop[index].dst_pipe = IPA_CLIENT_TEST1_CONS; + memcpy(tx_prop[index].hdr_name, IPA_TO_WLAN_HEADER_NAME, + sizeof(IPA_TO_WLAN_HEADER_NAME)); + + index++; + tx_prop[index].ip = IPA_IP_v6; + tx_prop[index].dst_pipe = IPA_CLIENT_TEST2_CONS; + memcpy(tx_prop[index].hdr_name, IPA_TO_WLAN_HEADER_NAME, + sizeof(IPA_TO_WLAN_HEADER_NAME)); + + index++; + tx_prop[index].ip = IPA_IP_v6; + tx_prop[index].dst_pipe = IPA_CLIENT_TEST3_CONS; + memcpy(tx_prop[index].hdr_name, IPA_TO_WLAN_HEADER_NAME, + sizeof(IPA_TO_WLAN_HEADER_NAME)); + + index++; + tx_prop[index].ip = IPA_IP_v6; + tx_prop[index].dst_pipe = IPA_CLIENT_TEST4_CONS; + memcpy(tx_prop[index].hdr_name, IPA_TO_WLAN_HEADER_NAME, + sizeof(IPA_TO_WLAN_HEADER_NAME)); + + memset(&rx_prop, 0, sizeof(struct ipa_ioc_rx_intf_prop)); + rx_prop.ip = IPA_IP_v6; + rx_prop.src_pipe = IPA_CLIENT_TEST1_PROD; + + memset(&rx_intf, 0, sizeof(rx_intf)); + rx_intf.num_props = 1; + rx_intf.prop = &rx_prop; + + memset(&tx_intf, 0, sizeof(tx_intf)); + tx_intf.num_props = 4; + tx_intf.prop = tx_prop; + + res = ipa_register_intf(name, &tx_intf, &rx_intf); + if (res) { + IPATEST_ERR("Unable to register interface %s, %d\n", + name, res); + return res; + } + + IPATEST_DBG("Registered interface %s\n", name); + return res; +} + +/* Wan interface has 1 rx and 1 Tx endpoint */ +int register_wan_interface(void) +{ + struct ipa_rx_intf rx_intf; + struct ipa_tx_intf tx_intf; + struct ipa_ioc_tx_intf_prop tx_prop; + struct ipa_ioc_rx_intf_prop rx_prop; + char *name = "rmnet0"; + int res; + + memset(&tx_prop, 0, sizeof(tx_prop)); + tx_prop.ip = IPA_IP_v6; + tx_prop.dst_pipe = IPA_CLIENT_TEST3_CONS; + + memset(&rx_prop, 0, sizeof(rx_prop)); + rx_prop.ip = IPA_IP_v6; + rx_prop.src_pipe = IPA_CLIENT_TEST3_PROD; + + memset(&rx_intf, 0, sizeof(rx_intf)); + rx_intf.num_props = 1; + rx_intf.prop = &rx_prop; + + memset(&tx_intf, 0, sizeof(tx_intf)); + tx_intf.num_props = 1; + tx_intf.prop = &tx_prop; + + res = ipa_register_intf(name, &tx_intf, &rx_intf); + if (res != 0) + goto fail; + + IPATEST_DBG("registered interface %s !\n", name); + +fail: + return res; +} + +/* + Configures the system with one input to IPA and 2 outputs. + /dev/to_ipa_0 -> MEM -> GSI -> IPA |-> GSI + -> MEM -> /dev/from_ipa_0 +|-> GSI -> MEM -> /dev/from_ipa_1 +*/ +int configure_system_20(void) +{ + int res = 0; + int index = 0; + struct ipa_ep_cfg ipa_ep_cfg; + + struct ipa_sys_connect_params sys_in; + unsigned long ipa_gsi_hdl; + u32 ipa_pipe_num; + + memset(&ipa_ep_cfg, 0, sizeof(ipa_ep_cfg)); + ipa_ep_cfg.hdr.hdr_len = 18; + sys_in.ipa_ep_cfg = ipa_ep_cfg; + + /* Connect first Rx IPA --> AP MEM */ + memset(&sys_in, 0, sizeof(sys_in)); + sys_in.client = IPA_CLIENT_TEST2_CONS; + if (ipa3_sys_setup(&sys_in, + &ipa_gsi_hdl, &ipa_pipe_num, + &from_ipa_devs[index]->ipa_client_hdl, false)) + goto fail; + + res = connect_ipa_to_apps(&from_ipa_devs[index]->ep, + IPA_CLIENT_TEST2_CONS, + ipa_pipe_num, + ipa_gsi_hdl); + if (res) + goto fail; + + + index++; + + /* Connect IPA -> 1 Tx GSI */ + /* RNDIS Aggregation with ETH2 header */ + memset(&ipa_ep_cfg, 0, sizeof(ipa_ep_cfg)); + ipa_ep_cfg.aggr.aggr_en = IPA_ENABLE_AGGR; + ipa_ep_cfg.aggr.aggr = IPA_GENERIC; + ipa_ep_cfg.aggr.aggr_byte_limit = 1; + ipa_ep_cfg.aggr.aggr_time_limit = 0; + ipa_ep_cfg.hdr.hdr_ofst_pkt_size_valid = true; + ipa_ep_cfg.hdr.hdr_ofst_pkt_size = 12; + ipa_ep_cfg.hdr.hdr_additional_const_len = 14; + ipa_ep_cfg.hdr.hdr_len = 58; + ipa_ep_cfg.hdr_ext.hdr_little_endian = true; + ipa_ep_cfg.hdr_ext.hdr_total_len_or_pad_valid = true; + ipa_ep_cfg.hdr_ext.hdr_total_len_or_pad = IPA_HDR_TOTAL_LEN; + ipa_ep_cfg.hdr_ext.hdr_total_len_or_pad_offset = 4; + + /* Connect 1 Tx IPA --> AP MEM */ + memset(&sys_in, 0, sizeof(sys_in)); + sys_in.client = IPA_CLIENT_TEST3_CONS; + sys_in.ipa_ep_cfg = ipa_ep_cfg; + if (ipa3_sys_setup( + &sys_in, + &ipa_gsi_hdl, + &ipa_pipe_num, + &from_ipa_devs[index]->ipa_client_hdl, + false)) + goto fail; + + res = connect_ipa_to_apps( + &from_ipa_devs[index]->ep, + IPA_CLIENT_TEST3_CONS, + ipa_pipe_num, + ipa_gsi_hdl); + if (res) + goto fail; + + /* Connect Rx GSI -> IPA */ + /* Prepare an endpoint configuration structure */ + res = configure_ipa_endpoint(&ipa_ep_cfg, IPA_BASIC); + if (res) + goto fail; + + /* configure RNDIS+ETH2 header removal on Rx */ + /* configure RNDIS de-aggregation on Rx */ + ipa_ep_cfg.aggr.aggr_en = IPA_ENABLE_DEAGGR; + ipa_ep_cfg.aggr.aggr = IPA_GENERIC; + ipa_ep_cfg.deaggr.deaggr_hdr_len = 44; /* RNDIS hdr */ + ipa_ep_cfg.deaggr.packet_offset_valid = true; + ipa_ep_cfg.deaggr.packet_offset_location = 8; + ipa_ep_cfg.hdr.hdr_len = 14; /* Ethernet header */ + ipa_ep_cfg.hdr.hdr_ofst_pkt_size = 12; + ipa_ep_cfg.hdr.hdr_remove_additional = false; + ipa_ep_cfg.hdr_ext.hdr_little_endian = 1; + ipa_ep_cfg.hdr_ext.hdr_total_len_or_pad_valid = 1; + ipa_ep_cfg.hdr_ext.hdr_total_len_or_pad = IPA_HDR_TOTAL_LEN; + ipa_ep_cfg.hdr_ext.hdr_payload_len_inc_padding = 0; + ipa_ep_cfg.hdr_ext.hdr_total_len_or_pad_offset = 4; + + memset(&sys_in, 0, sizeof(sys_in)); + sys_in.client = IPA_CLIENT_TEST_PROD; + sys_in.ipa_ep_cfg = ipa_ep_cfg; + if (ipa3_sys_setup(&sys_in, &ipa_gsi_hdl, &ipa_pipe_num, + &to_ipa_devs[0]->ipa_client_hdl, false)) + goto fail; + + /* Connect AP MEM --> Tx IPA */ + res = connect_apps_to_ipa(&to_ipa_devs[0]->ep, + IPA_CLIENT_TEST_PROD, + ipa_pipe_num, + &to_ipa_devs[0]->mem, + ipa_gsi_hdl); + + + if (res) + goto fail; + + /* Connect Tx GSI -> IPA */ + /* Prepare an endpoint configuration structure */ + res = configure_ipa_endpoint(&ipa_ep_cfg, IPA_BASIC); + if (res) + goto fail; + + /* configure ETH2+WLAN\ETH2_802_1Q (18B) header removal on Tx */ + ipa_ep_cfg.hdr.hdr_len = ETH_HLEN + IPA_TEST_ADDITIONAL_HDR_LEN; + + memset(&sys_in, 0, sizeof(sys_in)); + sys_in.client = IPA_CLIENT_TEST2_PROD; + sys_in.ipa_ep_cfg = ipa_ep_cfg; + if (ipa3_sys_setup(&sys_in, &ipa_gsi_hdl, &ipa_pipe_num, + &to_ipa_devs[1]->ipa_client_hdl, false)) + goto fail; + + /* Connect AP MEM --> Tx IPA */ + res = connect_apps_to_ipa(&to_ipa_devs[1]->ep, + IPA_CLIENT_TEST2_PROD, + ipa_pipe_num, + &to_ipa_devs[1]->mem, + ipa_gsi_hdl); + + + if (res) + goto fail; + + /* Connect Tx GSI -> IPA */ + /* Prepare an endpoint configuration structure */ + res = configure_ipa_endpoint(&ipa_ep_cfg, IPA_BASIC); + if (res) + goto fail; + + /* configure ETH2 header removal on Tx */ + ipa_ep_cfg.hdr.hdr_len = ETH_HLEN; + + memset(&sys_in, 0, sizeof(sys_in)); + sys_in.client = IPA_CLIENT_TEST3_PROD; + sys_in.ipa_ep_cfg = ipa_ep_cfg; + if (ipa3_sys_setup(&sys_in, &ipa_gsi_hdl, &ipa_pipe_num, + &to_ipa_devs[2]->ipa_client_hdl, false)) + goto fail; + + /* Connect AP MEM --> Tx IPA */ + res = connect_apps_to_ipa(&to_ipa_devs[2]->ep, + IPA_CLIENT_TEST3_PROD, + ipa_pipe_num, + &to_ipa_devs[2]->mem, + ipa_gsi_hdl); + + + if (res) + goto fail; + +fail: + /* cleanup and tear down goes here */ + return res; +} + +static char **str_split(char *str, const char *delim) +{ + char **res = NULL; + char **tmp = NULL; + char *p = strsep(&str, delim); + int n_spaces = 0; + + /* split string and append tokens to 'res' */ + while (p) { + tmp = krealloc(res, sizeof(char *) * ++n_spaces, GFP_KERNEL); + + if (tmp == NULL) { + IPATEST_ERR("krealloc failed\n"); + goto fail; /* memory allocation failed */ + } + + res = tmp; + res[n_spaces-1] = p; + p = strsep(&str, delim); + } + /* realloc one extra element for the last NULL */ + tmp = krealloc(res, sizeof(char *) * (n_spaces+1), GFP_KERNEL); + if (tmp == NULL) { + IPATEST_ERR("krealloc failed\n"); + goto fail; /* memory allocation failed */ + } + res = tmp; + res[n_spaces] = 0; + return res; +fail: + kfree(res); + return res; +} + +/** + * Write File. + * + * @note Configure the system by writing a configuration + * index to the device node /dev/ipa_test + */ +ssize_t ipa_test_write(struct file *filp, const char __user *buf, + size_t size, loff_t *f_pos) +{ + int ret = 0; + int index; + + unsigned long missing; + char *str; + char **params; + + str = kzalloc(size+1, GFP_KERNEL); + if (str == NULL) { + IPATEST_ERR("kzalloc err.\n"); + return -ENOMEM; + } + + missing = copy_from_user(str, buf, size); + if (missing) { + kfree(str); + return -EFAULT; + } + IPATEST_DBG("ipa_test_write: input string= %s\n", str); + str[size] = '\0'; + + params = str_split(str, " "); + if (params == NULL) { + kfree(str); + return -EFAULT; + } + + ret = kstrtos32(params[0], 10, (s32 *)&ipa_test->configuration_idx); + if (ret) { + IPATEST_ERR("kstrtoul() failed.\n"); + ret = -EFAULT; + goto bail; + } + + IPATEST_DBG(":Invoking configuration %d.\n", + ipa_test->configuration_idx); + + /* Setup GSI */ + + switch (ipa_test->configuration_idx) { + case -1: + destroy_channel_devices(); + /*exception_hdl_exit();TODO: hsnapy un-comment this*/ + break; + + case 2: + index = 0; + ret = create_channel_device(index, + "to_ipa", &to_ipa_devs[index], + TX_SZ); + if (ret) { + IPATEST_ERR("Channel device creation error.\n"); + ret = -ENODEV; + goto bail; + } + ipa_test->tx_channels[ipa_test->num_tx_channels++] = + to_ipa_devs[index]; + ret = create_channel_device(index, "from_ipa", + &from_ipa_devs[index], + RX_SZ); + if (ret) { + IPATEST_ERR("Channel device creation error.\n"); + ret = -ENODEV; + goto bail; + } + ipa_test->rx_channels[ipa_test->num_rx_channels++] = + from_ipa_devs[index]; + + index++; + ret = create_channel_device(index, + "to_ipa", &to_ipa_devs[index], + TX_SZ); + if (ret) { + IPATEST_ERR("channel device creation error.\n"); + ret = -ENODEV; + goto bail; + } + ipa_test->tx_channels[ipa_test->num_tx_channels++] = + to_ipa_devs[index]; + ret = create_channel_device(index, "from_ipa", + &from_ipa_devs[index], + RX_SZ); + if (ret) { + IPATEST_ERR("Channel device creation error.\n"); + ret = -ENODEV; + goto bail; + } + ipa_test->rx_channels[ipa_test->num_rx_channels++] = + from_ipa_devs[index]; + + index++; + ret = create_channel_device(index, "from_ipa", + &from_ipa_devs[index], + RX_SZ); + if (ret) { + IPATEST_ERR("Channel device creation error.\n"); + ret = -ENODEV; + goto bail; + } + ipa_test->rx_channels[ipa_test->num_rx_channels++] = + from_ipa_devs[index]; + + ret = configure_system_2(); + if (ret) { + IPATEST_ERR("System configuration failed."); + ret = -ENODEV; + goto bail; + } + break; + + case 5: + index = 0; + ret = create_channel_device(index, "to_ipa", + &to_ipa_devs[index], + TX_SZ); + if (ret) { + IPATEST_ERR("Channel device creation error.\n"); + ret = -ENODEV; + goto bail; + } + ipa_test-> + tx_channels[ipa_test->num_tx_channels++] = + to_ipa_devs[index]; + + ret = create_channel_device(index, "from_ipa", + &from_ipa_devs[index], + RX_SZ); + if (ret) { + IPATEST_ERR("Channel device creation error.\n"); + ret = -ENODEV; + goto bail; + } + ipa_test-> + rx_channels[ipa_test->num_rx_channels++] = + from_ipa_devs[index]; + + index++; + ret = create_channel_device(index, "from_ipa", + &from_ipa_devs[index], + RX_SZ); + if (ret) { + IPATEST_ERR("Channel device creation error.\n"); + ret = -ENODEV; + goto bail; + } + ipa_test-> + rx_channels[ipa_test->num_rx_channels++] = + from_ipa_devs[index]; + + index++; + ret = create_channel_device(index, "from_ipa", + &from_ipa_devs[index], + RX_SZ); + if (ret) { + IPATEST_ERR("Channel device creation error.\n"); + ret = -ENODEV; + goto bail; + } + ipa_test-> + rx_channels[ipa_test->num_rx_channels++] = + from_ipa_devs[index]; + + ret = configure_system_5(); + if (ret) { + IPATEST_ERR("System configuration failed."); + ret = -ENODEV; + goto bail; + } + break; + + case 6: + index = 0; + ret = create_channel_device(index, "to_ipa", + &to_ipa_devs[index], + TX_SZ); + if (ret) { + IPATEST_ERR("Channel device creation error.\n"); + ret = -ENODEV; + goto bail; + } + ipa_test-> + tx_channels[ipa_test->num_tx_channels++] = + to_ipa_devs[index]; + + ret = create_channel_device(index, "from_ipa", + &from_ipa_devs[index], + RX_SZ); + if (ret) { + IPATEST_ERR("Channel device creation error.\n"); + ret = -ENODEV; + goto bail; + } + ipa_test-> + rx_channels[ipa_test->num_rx_channels++] = + from_ipa_devs[index]; + + ret = configure_system_6(); + if (ret) { + IPATEST_ERR("System configuration failed."); + ret = -ENODEV; + goto bail; + } + break; + + case 7: + index = 0; + ret = create_channel_device(index, "to_ipa", + &to_ipa_devs[index], + TX_SZ); + if (ret) { + IPATEST_ERR("Channel device creation error.\n"); + ret = -ENODEV; + goto bail; + } + ipa_test-> + tx_channels[ipa_test->num_tx_channels++] = + to_ipa_devs[index]; + + ret = create_channel_device(index, "from_ipa", + &from_ipa_devs[index], + RX_SZ); + if (ret) { + IPATEST_ERR("Channel device creation error.\n"); + ret = -ENODEV; + goto bail; + } + ipa_test-> + rx_channels[ipa_test->num_rx_channels++] = + from_ipa_devs[index]; + + index++; + ret = create_channel_device(index, "from_ipa", + &from_ipa_devs[index], + RX_SZ); + if (ret) { + IPATEST_ERR("Channel device creation error.\n"); + ret = -ENODEV; + goto bail; + } + ipa_test-> + rx_channels[ipa_test->num_rx_channels++] = + from_ipa_devs[index]; + + index++; + ret = create_channel_device(index, "from_ipa", + &from_ipa_devs[index], + RX_SZ); + if (ret) { + IPATEST_ERR("Channel device creation error.\n"); + ret = -ENODEV; + goto bail; + } + ipa_test-> + rx_channels[ipa_test->num_rx_channels++] = + from_ipa_devs[index]; + + ret = configure_system_7(); + if (ret) { + IPATEST_ERR("System configuration failed."); + ret = -ENODEV; + goto bail; + } + break; + + case 8: + index = 0; + ret = create_channel_device(index, "to_ipa", + &to_ipa_devs[index], + TX_SZ); + if (ret) { + IPATEST_ERR("Channel device creation error.\n"); + ret = -ENODEV; + goto bail; + } + ipa_test-> + tx_channels[ipa_test->num_tx_channels++] = + to_ipa_devs[index]; + index++; + + ret = create_channel_device(index, "to_ipa", + &to_ipa_devs[index], + TX_SZ); + if (ret) { + IPATEST_ERR("Channel device creation error.\n"); + ret = -ENODEV; + goto bail; + } + ipa_test-> + tx_channels[ipa_test->num_tx_channels++] = + to_ipa_devs[index]; + index++; + + ret = create_channel_device(index, "to_ipa", + &to_ipa_devs[index], + TX_SZ); + if (ret) { + IPATEST_ERR("Channel device creation error.\n"); + ret = -ENODEV; + goto bail; + } + ipa_test-> + tx_channels[ipa_test->num_tx_channels++] = + to_ipa_devs[index]; + index++; + + ret = create_channel_device(index, "to_ipa", + &to_ipa_devs[index], + TX_SZ); + if (ret) { + IPATEST_ERR("Channel device creation error.\n"); + ret = -ENODEV; + goto bail; + } + ipa_test-> + tx_channels[ipa_test->num_tx_channels++] = + to_ipa_devs[index]; + + index = 0; + ret = create_channel_device(index, "from_ipa", + &from_ipa_devs[index], + RX_SZ); + if (ret) { + IPATEST_ERR("Channel device creation error.\n"); + ret = -ENODEV; + goto bail; + } + ipa_test-> + rx_channels[ipa_test->num_rx_channels++] = + from_ipa_devs[index]; + index++; + + ret = create_channel_device(index, "from_ipa", + &from_ipa_devs[index], + RX_SZ); + if (ret) { + IPATEST_ERR("Channel device creation error.\n"); + ret = -ENODEV; + goto bail; + } + ipa_test-> + rx_channels[ipa_test->num_rx_channels++] = + from_ipa_devs[index]; + index++; + + ret = create_channel_device(index, "from_ipa", + &from_ipa_devs[index], + RX_SZ); + if (ret) { + IPATEST_ERR("Channel device creation error.\n"); + ret = -ENODEV; + goto bail; + } + ipa_test-> + rx_channels[ipa_test->num_rx_channels++] = + from_ipa_devs[index]; + + ret = configure_system_8(); + if (ret) { + IPATEST_ERR("System configuration failed.\n"); + ret = -ENODEV; + goto bail; + } + break; + + case 9: + index = 0; + ret = create_channel_device(index, "to_ipa", + &to_ipa_devs[index], + TX_SZ); + if (ret) { + IPATEST_ERR("Channel device creation error.\n"); + ret = -ENODEV; + goto bail; + } + ipa_test-> + tx_channels[ipa_test->num_tx_channels++] = + to_ipa_devs[index]; + index++; + + ret = create_channel_device(index, "to_ipa", + &to_ipa_devs[index], + TX_SZ); + if (ret) { + IPATEST_ERR("Channel device creation error.\n"); + ret = -ENODEV; + goto bail; + } + ipa_test-> + tx_channels[ipa_test->num_tx_channels++] = + to_ipa_devs[index]; + index++; + + ret = create_channel_device(index, "to_ipa", + &to_ipa_devs[index], + TX_SZ); + if (ret) { + IPATEST_ERR("Channel device creation error.\n"); + ret = -ENODEV; + goto bail; + } + ipa_test-> + tx_channels[ipa_test->num_tx_channels++] = + to_ipa_devs[index]; + index++; + + ret = create_channel_device(index, "to_ipa", + &to_ipa_devs[index], + TX_SZ); + if (ret) { + IPATEST_ERR("Channel device creation error.\n"); + ret = -ENODEV; + goto bail; + } + ipa_test-> + tx_channels[ipa_test->num_tx_channels++] = + to_ipa_devs[index]; + + index = 0; + ret = create_channel_device(index, "from_ipa", + &from_ipa_devs[index], + RX_SZ); + if (ret) { + IPATEST_ERR("Channel device creation error.\n"); + ret = -ENODEV; + goto bail; + } + ipa_test-> + rx_channels[ipa_test->num_rx_channels++] = + from_ipa_devs[index]; + index++; + + ret = create_channel_device(index, "from_ipa", + &from_ipa_devs[index], + RX_SZ); + if (ret) { + IPATEST_ERR("Channel device creation error.\n"); + ret = -ENODEV; + goto bail; + } + ipa_test-> + rx_channels[ipa_test->num_rx_channels++] = + from_ipa_devs[index]; + index++; + + ret = create_channel_device(index, "from_ipa", + &from_ipa_devs[index], + RX_SZ); + if (ret) { + IPATEST_ERR("Channel device creation error.\n"); + ret = -ENODEV; + goto bail; + } + ipa_test-> + rx_channels[ipa_test->num_rx_channels++] = + from_ipa_devs[index]; + + ret = configure_system_9(); + if (ret) { + IPATEST_ERR("System configuration failed.\n"); + ret = -ENODEV; + goto bail; + } + break; + + case 10: + index = 0; + ret = create_channel_device(index, "to_ipa", + &to_ipa_devs[index], + TX_SZ); + if (ret) { + IPATEST_ERR("Channel device creation error.\n"); + ret = -ENODEV; + goto bail; + } + ipa_test-> + tx_channels[ipa_test->num_tx_channels++] = + to_ipa_devs[index]; + + index = 0; + ret = create_channel_device(index, "from_ipa", + &from_ipa_devs[index], + RX_SZ); + if (ret) { + IPATEST_ERR("Channel device creation error.\n"); + ret = -ENODEV; + goto bail; + } + ipa_test-> + rx_channels[ipa_test->num_rx_channels++] = + from_ipa_devs[index]; + + ret = configure_system_10(); + if (ret) { + IPATEST_ERR("System configuration failed.\n"); + ret = -ENODEV; + goto bail; + } + break; + + case 12: + index = 0; + ret = create_channel_device(index, "to_ipa", + &to_ipa_devs[index], + TX_SZ); + if (ret) { + IPATEST_ERR("Channel device creation error.\n"); + ret = -ENODEV; + goto bail; + } + ipa_test-> + tx_channels[ipa_test->num_tx_channels++] = + to_ipa_devs[index]; + index++; + + ret = create_channel_device(index, "to_ipa", + &to_ipa_devs[index], + TX_SZ); + if (ret) { + IPATEST_ERR("Channel device creation error.\n"); + ret = -ENODEV; + goto bail; + } + ipa_test-> + tx_channels[ipa_test->num_tx_channels++] = + to_ipa_devs[index]; + + index = 0; + ret = create_channel_device(index, "from_ipa", + &from_ipa_devs[index], + RX_SZ); + if (ret) { + IPATEST_ERR("Channel device creation error.\n"); + ret = -ENODEV; + goto bail; + } + ipa_test-> + rx_channels[ipa_test->num_rx_channels++] = + from_ipa_devs[index]; + index++; + + ret = create_channel_device(index, "from_ipa", + &from_ipa_devs[index], + RX_SZ); + if (ret) { + IPATEST_ERR("Channel device creation error.\n"); + ret = -ENODEV; + goto bail; + } + ipa_test-> + rx_channels[ipa_test->num_rx_channels++] = + from_ipa_devs[index]; + index++; + + ret = create_channel_device(index, "from_ipa", + &from_ipa_devs[index], + RX_SZ); + if (ret) { + IPATEST_ERR("Channel device creation error.\n"); + ret = -ENODEV; + goto bail; + } + ipa_test-> + rx_channels[ipa_test->num_rx_channels++] = + from_ipa_devs[index]; + index++; + + ret = create_channel_device(index, "from_ipa", + &from_ipa_devs[index], + RX_SZ); + if (ret) { + IPATEST_ERR("Channel device creation error.\n"); + ret = -ENODEV; + goto bail; + } + ipa_test-> + rx_channels[ipa_test->num_rx_channels++] = + from_ipa_devs[index]; + + ret = configure_system_12(); + if (ret) { + IPATEST_ERR("System configuration failed.\n"); + ret = -ENODEV; + goto bail; + } + break; + + case 18: + index = 0; + ret = create_channel_device(index, "to_ipa", + &to_ipa_devs[index], TX_SZ); + if (ret) { + IPATEST_ERR("Channel device creation error.\n"); + return -ENODEV; + } + ipa_test-> + tx_channels[ipa_test->num_tx_channels++] = + to_ipa_devs[index]; + + index++; + ret = create_channel_device_by_type(index, "to_ipa", + &to_ipa_devs[index], RX_SZ, + IPA_TEST_DATA_PATH_TEST_CHANNEL); + if (ret) { + IPATEST_ERR("Channel device creation error.\n"); + return -ENODEV; + } + ipa_test-> + tx_channels[ipa_test->num_tx_channels++] = + to_ipa_devs[index]; + + index = 0; + ret = create_channel_device(index, "from_ipa", + &from_ipa_devs[index], RX_SZ); + if (ret) { + IPATEST_ERR("Channel device creation error.\n"); + return -ENODEV; + } + ipa_test-> + rx_channels[ipa_test->num_rx_channels++] = + from_ipa_devs[index]; + + ret = configure_system_18(); + if (ret) { + IPATEST_ERR("System configuration failed."); + return -ENODEV; + } + break; + + case 19: + index = 0; + /*Create the device on user space and allocate + * buffers for its GSI connection*/ + ret = create_channel_device(index, "to_ipa", + &to_ipa_devs[index], TX_SZ); + if (ret) { + IPATEST_ERR("Channel device creation error.\n"); + ret = -ENODEV; + goto bail; + } + ipa_test-> + tx_channels[ipa_test->num_tx_channels++] = + to_ipa_devs[index]; + + /*Create the device on user space and allocate + * buffers for its GSI connection*/ + ret = create_channel_device(index, "from_ipa", + &from_ipa_devs[index], + RX_SZ); + if (ret) { + IPATEST_ERR("Channel device creation error.\n"); + ret = -ENODEV; + goto bail; + } + ipa_test->rx_channels[ipa_test->num_rx_channels++] = + from_ipa_devs[index]; + + /*Make all the configurations required + * (IPA connect)*/ + ret = configure_system_19(); + if (ret) { + IPATEST_ERR("System configuration failed.\n"); + ret = -ENODEV; + goto bail; + } + break; + + case 20: + + /* Create producer channel 0 */ + index = 0; + ret = create_channel_device(index, + "to_ipa", &to_ipa_devs[index], + TX_SZ); + if (ret) { + IPATEST_ERR("Channel device creation error.\n"); + ret = -ENODEV; + goto bail; + } + ipa_test-> + tx_channels[ipa_test->num_tx_channels++] = + to_ipa_devs[index]; + + + /* Create producer channel 1 */ + index++; + ret = create_channel_device(index, + "to_ipa", &to_ipa_devs[index], + TX_SZ); + if (ret) { + IPATEST_ERR("Channel device creation error.\n"); + ret = -ENODEV; + goto bail; + } + ipa_test-> + tx_channels[ipa_test->num_tx_channels++] = + to_ipa_devs[index]; + + /* Create producer channel 2 */ + index++; + ret = create_channel_device(index, + "to_ipa", &to_ipa_devs[index], + TX_SZ); + if (ret) { + IPATEST_ERR("Channel device creation error.\n"); + ret = -ENODEV; + goto bail; + } + ipa_test-> + tx_channels[ipa_test->num_tx_channels++] = + to_ipa_devs[index]; + + /* Create consumer channel 0 */ + index = 0; + ret = create_channel_device(index, "from_ipa", + &from_ipa_devs[index], + RX_SZ); + if (ret) { + IPATEST_ERR("Channel device creation error.\n"); + ret = -ENODEV; + goto bail; + } + ipa_test-> + rx_channels[ipa_test->num_rx_channels++] = + from_ipa_devs[index]; + + /* Create consumer channel 1 */ + index++; + ret = create_channel_device(index, "from_ipa", + &from_ipa_devs[index], + RX_SZ); + if (ret) { + IPATEST_ERR("Channel device creation error.\n"); + ret = -ENODEV; + goto bail; + } + ipa_test-> + rx_channels[ipa_test->num_rx_channels++] = + from_ipa_devs[index]; + + ret = configure_system_20(); + if (ret) { + IPATEST_ERR("System configuration failed."); + ret = -ENODEV; + goto bail; + } + break; + + default: + IPATEST_ERR("Unsupported configuration index.\n"); + break; + } + + /* Insert descriptors into the receiving end(s) */ + ret = insert_descriptors_into_rx_endpoints(RX_BUFF_SIZE); + if (ret) { + IPATEST_DBG("Descriptor insertion into rx " + "endpoints failed.\n"); + ret = -EINVAL; + goto bail; + } + + IPATEST_DBG("System configured !\n"); + + /* Set the current configuration index */ + ipa_test->current_configuration_idx = + ipa_test->configuration_idx; + + ret = size; + +bail: + kfree(params); + kfree(str); + return ret; +} + +static ssize_t ipa_test_read(struct file *filp, + char __user *buf, + size_t count, loff_t *f_pos) +{ + int res, len; + char str[10]; + + if (0 != *f_pos) { + *f_pos = 0; + return 0; + } + + /* Convert the configuration index to a null terminated string */ + len = snprintf(str, 10, "%d", + ipa_test->current_configuration_idx); + + IPATEST_DBG("str = %s, len = %d\n", str, len); + + /* Copy the result to the user buffer */ + res = copy_to_user(buf, str, len + 1); + if (res < 0) { + IPATEST_ERR("copy_to_user() failed.\n"); + return -EFAULT; + } + + /* Increment the file position pointer */ + *f_pos += len; + + /* Return the number of bytes copied to the user */ + return len + 1; +} + +static struct class *ipa_test_class; + +//TODO make only one configuration function +static int configure_app_to_ipa_path(struct ipa_channel_config __user *to_ipa_user, + bool isUlso) +{ + int retval; + struct ipa_channel_config to_ipa_channel_config = {0}; + struct ipa_sys_connect_params sys_in; + unsigned long ipa_gsi_hdl; + u32 ipa_pipe_num; + int index; + + IPATEST_DBG("copying from 0x%px %zu bytes\n", + to_ipa_user, + sizeof(struct ipa_channel_config)); + retval = copy_from_user( + &to_ipa_channel_config, + to_ipa_user, + sizeof(struct ipa_channel_config)); + if (retval) { + IPATEST_ERR("fail to copy from user - to_ipa_user\n"); + return -1; + } + + index = to_ipa_channel_config.index; + + IPATEST_DBG("to_ipa head_marker value is 0x%x\n", + to_ipa_channel_config.head_marker); + + IPATEST_DBG("to_ipa config_size value is %zu\n", + to_ipa_channel_config.config_size); + + IPATEST_DBG("to_ipa index value is %d\n", index); + + IPATEST_DBG("client=%d\n", + to_ipa_channel_config.client); + + IPATEST_DBG("to_ipa tail_marker value is 0x%x\n", + to_ipa_channel_config.tail_marker); + + if (to_ipa_channel_config.head_marker != IPA_TEST_CHANNEL_CONFIG_MARKER) { + IPATEST_ERR("bad head_marker - possible memory corruption\n"); + return -EFAULT; + } + + if (to_ipa_channel_config.tail_marker != IPA_TEST_CHANNEL_CONFIG_MARKER) { + IPATEST_ERR("bad tail_marker - possible memory corruption\n"); + return -EFAULT; + } + + if (to_ipa_channel_config.config_size != sizeof(struct ipa_ep_cfg)) { + IPATEST_ERR("bad config size (%zu.vs.%zu) update test struct?\n", + to_ipa_channel_config.config_size, + sizeof(struct ipa_ep_cfg)); + return -EFAULT; + } + + /* Channel from which the userspace shall communicate to this pipe */ + if(isUlso){ + retval = create_channel_device_by_type(index, "to_ipa", &to_ipa_devs[index], TX_SZ, + IPA_TEST_ULSO_DATA_PATH_TEST_CHANNEL); + } else { + retval = create_channel_device(index, "to_ipa", &to_ipa_devs[index], TX_SZ); + } + if (retval) { + IPATEST_ERR("channel device creation error\n"); + return -1; + } + ipa_test->tx_channels[ipa_test->num_tx_channels++] = to_ipa_devs[index]; + if (isUlso) + return 0; + + /* Connect IPA --> Apps */ + memset(&sys_in, 0, sizeof(sys_in)); + sys_in.client = to_ipa_channel_config.client; + sys_in.notify = ¬ify_upon_exception; + sys_in.priv = &(p_exception_hdl_data->notify_cb_data); + IPATEST_DBG("copying from 0x%px\n", to_ipa_channel_config.cfg); + retval = copy_from_user(&sys_in.ipa_ep_cfg, to_ipa_channel_config.cfg, to_ipa_channel_config.config_size); + if (retval) { + IPATEST_ERR("fail to copy cfg - from_ipa_user\n"); + return -1; + } + if (ipa3_sys_setup(&sys_in, &ipa_gsi_hdl, &ipa_pipe_num, &to_ipa_devs[index]->ipa_client_hdl, false)) { + IPATEST_ERR("setup sys pipe failed\n"); + return -1; + } + + /* Connect APPS MEM --> Tx IPA */ + retval = connect_apps_to_ipa(&to_ipa_devs[index]->ep, to_ipa_channel_config.client, ipa_pipe_num, + &to_ipa_devs[index]->mem, ipa_gsi_hdl); + if (retval) { + IPATEST_ERR("fail to connect ipa to apps\n"); + return -1; + } + + return 0; +} + +static int configure_app_from_ipa_path(struct ipa_channel_config __user *from_ipa_user, bool isUlso) +{ + int retval; + struct ipa_channel_config from_ipa_channel_config = {0}; + struct ipa_sys_connect_params sys_in; + unsigned long ipa_gsi_hdl; + u32 ipa_pipe_num; + int index; + + IPATEST_DBG("copying from 0x%px %zu bytes\n", + from_ipa_user, + sizeof(struct ipa_channel_config)); + retval = copy_from_user( + &from_ipa_channel_config, + from_ipa_user, + sizeof(struct ipa_channel_config)); + if (retval) { + IPATEST_ERR("fail to copy from user - from_ipa_user (%d.vs.%zu)\n", + retval, sizeof(from_ipa_user)); + return -1; + } + + index = from_ipa_channel_config.index; + + IPATEST_DBG("from_ipa head_marker value is 0x%x\n", + from_ipa_channel_config.head_marker); + + IPATEST_DBG("from_ipa config_size value is %zu\n", + from_ipa_channel_config.config_size); + + IPATEST_DBG("from_ipa index value is %d\n", + index); + + IPATEST_DBG("client=%d\n", + from_ipa_channel_config.client); + + IPATEST_DBG("from_ipa tail_marker value is 0x%x\n", + from_ipa_channel_config.tail_marker); + + if (from_ipa_channel_config.head_marker != + IPA_TEST_CHANNEL_CONFIG_MARKER) { + IPATEST_ERR("bad head_marker - possible memory corruption\n"); + return -EFAULT; + } + + if (from_ipa_channel_config.tail_marker != + IPA_TEST_CHANNEL_CONFIG_MARKER) { + IPATEST_ERR("bad tail_marker - possible memory corruption\n"); + return -EFAULT; + } + + if (from_ipa_channel_config.config_size != sizeof(struct ipa_ep_cfg)) { + IPATEST_ERR("bad config size (%zu.vs.%zu) update test struct?\n", + from_ipa_channel_config.config_size, + sizeof(struct ipa_ep_cfg)); + return -EFAULT; + } + + /* Channel from which the userspace shall communicate to this pipe */ + retval = create_channel_device(index, "from_ipa", + &from_ipa_devs[index], rx_size); + if (retval) { + IPATEST_ERR("channel device creation error\n"); + return -1; + } + ipa_test->rx_channels[ipa_test->num_rx_channels++] = + from_ipa_devs[index]; + + /* Connect IPA --> Apps */ + IPATEST_DBG("copying from 0x%px\n", from_ipa_channel_config.cfg); + memset(&sys_in, 0, sizeof(sys_in)); + if (isUlso) { + sys_in.notify = notify_ipa_write_done; + } + sys_in.client = from_ipa_channel_config.client; + retval = copy_from_user( + &sys_in.ipa_ep_cfg, + from_ipa_channel_config.cfg, + from_ipa_channel_config.config_size); + if (retval) { + IPATEST_ERR("fail to copy cfg - from_ipa_user\n"); + return -1; + } + + if (ipa3_sys_setup(&sys_in, &ipa_gsi_hdl, &ipa_pipe_num, + &from_ipa_devs[index]->ipa_client_hdl, from_ipa_channel_config.en_status)) { + IPATEST_ERR("setup sys pipe failed\n"); + return -1; + } + + retval = connect_ipa_to_apps(&from_ipa_devs[index]->ep, + from_ipa_channel_config.client, + ipa_pipe_num, + ipa_gsi_hdl); + if (retval) { + IPATEST_ERR("fail to connect ipa to apps\n"); + return -1; + } + + return 0; +} + +static int configure_test_scenario( + struct ipa_test_config_header *ipa_test_config_header, + struct ipa_channel_config **from_ipa_channel_config_array, + struct ipa_channel_config **to_ipa_channel_config_array, + bool isUlso) +{ + int retval; + int i; + + if (ipa_test->num_tx_channels > 0 || ipa_test->num_rx_channels >0) { + IPATEST_DBG("cleanning previous configuration before new one\n"); + destroy_channel_devices(); + } else { + IPATEST_DBG("system is clean, starting new configuration"); + } + + IPATEST_DBG("starting scenario configuration\n"); + + IPATEST_DBG("head_marker value is 0x%x\n", + ipa_test_config_header->head_marker); + + IPATEST_DBG("from_ipa_channels_num=%d\n\n", + ipa_test_config_header->from_ipa_channels_num); + + IPATEST_DBG("to_ipa_channels_num=%d\n\n", + ipa_test_config_header->to_ipa_channels_num); + + IPATEST_DBG("tail_marker value is 0x%x\n", + ipa_test_config_header->tail_marker); + + if (ipa_test_config_header->head_marker != IPA_TEST_CONFIG_MARKER) { + IPATEST_ERR("bad header marker - possible memory corruption\n"); + return -EFAULT; + } + + if (ipa_test_config_header->tail_marker != IPA_TEST_CONFIG_MARKER) { + IPATEST_ERR("bad tail marker - possible memory corruption\n"); + return -EFAULT; + } + + if (isUlso) { + rx_size = RX_SZ_ULSO; + } else { + rx_size = RX_SZ; + } + + for (i = 0 ; i < ipa_test_config_header->from_ipa_channels_num ; i++) { + IPATEST_DBG("starting configuration of from_ipa_%d\n", i); + retval = configure_app_from_ipa_path(from_ipa_channel_config_array[i], isUlso); + if (retval) { + IPATEST_ERR("fail to configure from_ipa_%d", i); + goto fail; + } + } + + retval = insert_descriptors_into_rx_endpoints(RX_BUFF_SIZE); + if (retval) { + IPATEST_ERR("RX descriptors failed\n"); + goto fail; + } + IPATEST_DBG("RX descriptors were added to RX pipes\n"); + + for (i = 0 ; i < ipa_test_config_header->to_ipa_channels_num ; i++) { + retval = configure_app_to_ipa_path(to_ipa_channel_config_array[i], isUlso); + if (retval) { + IPATEST_ERR("fail to configure to_ipa_%d", i); + goto fail; + } + } + + /* + * This value is arbitrary, it is used in + * order to be able to cleanup + */ + ipa_test->current_configuration_idx = GENERIC_TEST_CONFIGURATION_IDX; + + IPATEST_DBG("finished scenario configuration\n"); + + return 0; +fail: + destroy_channel_devices(); + + return retval; +} + +static int handle_add_hdr_hpc(unsigned long ioctl_arg) +{ + struct ipa_ioc_add_hdr *hdrs; + struct ipa_hdr_add *hdr; + int retval; + + IPATEST_ERR("copying from 0x%px\n", (u8 *)ioctl_arg); + hdrs = kzalloc(sizeof(struct ipa_ioc_add_hdr) + sizeof(struct ipa_hdr_add), GFP_KERNEL); + if (!hdrs) + return -ENOMEM; + retval = copy_from_user(hdrs, (u8 *)ioctl_arg, + sizeof(struct ipa_ioc_add_hdr) + sizeof(struct ipa_hdr_add)); + if (retval) { + IPATEST_ERR("failing copying header from user\n"); + kfree(hdrs); + return retval; + } + retval = ipa3_add_hdr_hpc(hdrs); + if (retval) { + IPATEST_ERR("ipa3_add_hdr_hpc failed\n"); + kfree(hdrs); + return retval; + } + IPATEST_ERR("ELIAD: \n"); + hdr = &hdrs->hdr[0]; + if (hdr->status) { + IPATEST_ERR("ipa3_add_hdr_hpc failed\n"); + return hdr->status; + } + IPATEST_ERR("ELIAD: \n"); + if (copy_to_user((void __user *)ioctl_arg, hdrs, + sizeof(struct ipa_ioc_add_hdr) + sizeof(struct ipa_hdr_add))) { + retval = -EFAULT; + } + IPATEST_ERR("ELIAD: \n"); + + kfree(hdrs); + return 0; +} + +static int handle_pkt_init_ex_set_hdr_ofst_ioctl(unsigned long ioctl_arg) +{ + struct ipa_pkt_init_ex_hdr_ofst_set hdr_ofst; + int retval; + + IPATEST_DBG("copying from 0x%px\n", (u8 *)ioctl_arg); + retval = copy_from_user(&hdr_ofst, (u8 *)ioctl_arg, sizeof(hdr_ofst)); + if (retval) { + IPATEST_ERR("failing copying header from user\n"); + return retval; + } + + return ipa_set_pkt_init_ex_hdr_ofst(&hdr_ofst, true); +} + +static int handle_configuration_ioctl(unsigned long ioctl_arg, + bool isUlso) +{ + int retval; + int needed_bytes; + struct ipa_test_config_header test_header; + struct ipa_channel_config **from_ipa_channel_config_array; + struct ipa_channel_config **to_ipa_channel_config_array; + + /* header copy */ + IPATEST_DBG("copying from 0x%px\n", (u8 *)ioctl_arg); + retval = copy_from_user(&test_header, + (u8 *)ioctl_arg, + sizeof(test_header)); + if (retval) { + IPATEST_ERR("failing copying header from user\n"); + return retval; + } + + /* allocate place for the configuration array for "from" */ + needed_bytes = test_header.from_ipa_channels_num* + sizeof(*test_header.from_ipa_channel_config); + + from_ipa_channel_config_array = kzalloc(needed_bytes, GFP_KERNEL); + if (!from_ipa_channel_config_array) { + IPATEST_ERR("fail mem alloc for from_ipa\n"); + retval = -ENOMEM; + goto fail_from_alloc; + } + + /* copy the configuration array for "from" */ + IPATEST_DBG("copying from 0x%px\n", test_header.from_ipa_channel_config); + retval = copy_from_user(from_ipa_channel_config_array, + test_header.from_ipa_channel_config, + needed_bytes); + if (retval) { + IPATEST_ERR("failing copying to_ipa from user\n"); + goto fail_copy_from; + } + + /* allocate place for the configuration array for "from" */ + needed_bytes = test_header.to_ipa_channels_num* + sizeof(*test_header.to_ipa_channel_config); + + to_ipa_channel_config_array = kzalloc(needed_bytes, GFP_KERNEL); + if (!to_ipa_channel_config_array) { + IPATEST_ERR("fail mem alloc for to_ipa\n"); + goto fail_to_alloc; + } + + /* copy the configuration array for "to" */ + IPATEST_DBG("copying from 0x%px\n", test_header.to_ipa_channel_config); + retval = copy_from_user(to_ipa_channel_config_array, + test_header.to_ipa_channel_config, + needed_bytes); + if (retval) { + IPATEST_ERR("failing copying to_ipa from user\n"); + goto fail_copy_to; + } + + retval = configure_test_scenario(&test_header, + from_ipa_channel_config_array, + to_ipa_channel_config_array, + isUlso); + if (retval) + IPATEST_ERR("fail to configure the system\n"); + +fail_copy_to: + kfree(to_ipa_channel_config_array); +fail_to_alloc: +fail_copy_from: + kfree(from_ipa_channel_config_array); +fail_from_alloc: + return retval; + +} + +int handle_clean_ioctl(void) +{ + IPATEST_DBG("cleanning previous configuration\n"); + destroy_channel_devices(); + + return 0; +} + +static int handle_ep_ctrl_ioctl(unsigned long ioctl_arg) +{ + int retval = 0; + struct ipa_ep_cfg_ctrl ep_ctrl; + struct ipa_test_ep_ctrl test_ep_ctrl; + + retval = copy_from_user(&test_ep_ctrl, + (u8 *)ioctl_arg, + sizeof(test_ep_ctrl)); + if (retval) { + IPATEST_ERR("failed copying ep_ctrl data from user\n"); + return retval; + } + + ep_ctrl.ipa_ep_delay = test_ep_ctrl.ipa_ep_delay; + ep_ctrl.ipa_ep_suspend = test_ep_ctrl.ipa_ep_suspend; + + /* pipe suspend is not supported in IPA_v4 or higher */ + if(ipa_get_hw_type() >= IPA_HW_v4_0){ + if(ep_ctrl.ipa_ep_suspend) + retval = ipa_stop_gsi_channel(from_ipa_devs[test_ep_ctrl.from_dev_num]->ipa_client_hdl); + else + retval = gsi_start_channel(from_ipa_devs[test_ep_ctrl.from_dev_num]->ep.gsi_chan_hdl); + + if (retval) { + IPATEST_ERR("failed closing/opening the GSI channel\n"); + return retval; + } + ep_ctrl.ipa_ep_suspend = false; + } + + IPATEST_DBG("handle_ep_ctrl_ioctl: sending hdl %d\n\n", + from_ipa_devs[test_ep_ctrl.from_dev_num]->ipa_client_hdl); + + return ipa_cfg_ep_ctrl(from_ipa_devs[test_ep_ctrl.from_dev_num]->ipa_client_hdl, &ep_ctrl); +} + +static int handle_reg_suspend_handler(unsigned long ioctl_arg) +{ + int res = 0; + struct ipa_tx_suspend_private_data *suspend_priv_data = NULL; + struct ipa_test_reg_suspend_handler reg_data; + + res = copy_from_user(®_data, + (u8 *)ioctl_arg, + sizeof(reg_data)); + if (res) { + IPATEST_ERR("failed copying ep_ctrl data from user\n"); + return res; + } + + if (reg_data.reg) { + if (reg_data.DevNum >= (MAX_CHANNEL_DEVS / 2)) + { + res = -ENXIO; + IPATEST_ERR("DevNum is incorrect %d\n", reg_data.DevNum); + goto fail; + } + + suspend_priv_data = + kzalloc(sizeof(*suspend_priv_data), GFP_KERNEL); + if (!suspend_priv_data) { + IPATEST_ERR("failed allocating suspend_priv_data\n"); + res = -ENOMEM; + goto fail; + } + + suspend_priv_data->clnt_hdl = from_ipa_devs[reg_data.DevNum]->ipa_client_hdl; + suspend_priv_data->gsi_chan_hdl = from_ipa_devs[reg_data.DevNum]->ep.gsi_chan_hdl; + IPATEST_DBG("registering interrupt handle to clnt_hdl %d\n", suspend_priv_data->clnt_hdl); + res = ipa_add_interrupt_handler(IPA_TX_SUSPEND_IRQ, suspend_handler, + reg_data.deferred_flag, (void *)suspend_priv_data); + if (res) { + IPATEST_ERR("register handler for suspend interrupt failed\n"); + goto fail_allocated; + } + + } else { + res = ipa_restore_suspend_handler(); + } +fail: + return res; +fail_allocated: + kfree(suspend_priv_data); + return res; +} + +static int handle_holb_config_ioctl(unsigned long ioctl_arg) +{ + int retval = 0; + int clnt_hdl; + struct ipa_ep_cfg_holb holb_cfg = {0}; + struct ipa_test_holb_config test_holb_config; + + retval = copy_from_user(&test_holb_config, + (u8 *)ioctl_arg, + sizeof(test_holb_config)); + if (retval) { + IPATEST_ERR("failed copying holb_config data from user\n"); + return retval; + } + + clnt_hdl = ipa_get_ep_mapping(test_holb_config.client); + + IPATEST_ERR("Sending clnt_hdl %d", clnt_hdl); + + holb_cfg.en = test_holb_config.en; + holb_cfg.tmr_val = test_holb_config.tmr_val; + + return ipa3_cfg_ep_holb(clnt_hdl, &holb_cfg); +} + +static int ipa_test_get_mem_part(unsigned long ioctl_arg) +{ + unsigned long result; + + // Let's check that mirrored structure is of the same siz as the original + BUILD_BUG_ON(sizeof(struct ipa_test_mem_partition) != sizeof(struct ipa3_mem_partition)); + + result = copy_to_user((u8 *)ioctl_arg, + ipa3_ctx->ctrl->mem_partition, sizeof(struct ipa3_mem_partition)); + + if (result != 0) + return -EACCES; + + return 0; +} + +static long ipa_test_ioctl(struct file *filp, + unsigned int cmd, unsigned long arg) +{ + int retval; + + IPATEST_DBG("cmd=%x nr=%d\n", cmd, _IOC_NR(cmd)); + if (_IOC_TYPE(cmd) != IPA_TEST_IOC_MAGIC) + return -ENOTTY; + + switch (cmd) { + case IPA_TEST_IOC_CONFIGURE: + retval = handle_configuration_ioctl(arg, false); + break; + + case IPA_TEST_IOC_CLEAN: + retval = handle_clean_ioctl(); + break; + + case IPA_TEST_IOC_GET_HW_TYPE: + retval = ipa_get_hw_type(); + break; + case IPA_TEST_IOC_EP_CTRL: + retval = handle_ep_ctrl_ioctl(arg); + break; + case IPA_TEST_IOC_REG_SUSPEND_HNDL: + retval = handle_reg_suspend_handler(arg); + break; + case IPA_TEST_IOC_HOLB_CONFIG: + retval = handle_holb_config_ioctl(arg); + break; + case IPA_TEST_IOC_IS_TEST_PROD_FLT_IN_SRAM: + retval = ipa_is_test_prod_flt_in_sram_internal(arg); + break; + case IPA_TEST_IOC_GET_MEM_PART: + retval = ipa_test_get_mem_part(arg); + break; + case IPA_TEST_IOC_ULSO_CONFIGURE: + retval = handle_configuration_ioctl(arg, true); + break; + case IPA_TEST_IOC_ADD_HDR_HPC: + retval = handle_add_hdr_hpc(arg); + break; + case IPA_TEST_IOC_PKT_INIT_EX_SET_HDR_OFST: + retval = handle_pkt_init_ex_set_hdr_ofst_ioctl(arg); + break; + default: + IPATEST_ERR("ioctl is not supported (%d)\n", cmd); + return -ENOTTY; + } + + return retval; +} + +static int ipa_test_open(struct inode *inode, struct file *file) +{ + IPATEST_DBG("ipa_test module opened by %s\n", current->comm); + return 0; +} + +static int ipa_test_release(struct inode *inode, struct file *file) +{ + IPATEST_DBG("ipa_test module closed by %s\n", current->comm); + return 0; +} + + +static const struct file_operations ipa_test_fops = { + .owner = THIS_MODULE, + .write = ipa_test_write, + .read = ipa_test_read, + .open = ipa_test_open, + .release = ipa_test_release, + .unlocked_ioctl = ipa_test_ioctl, +}; + +/** + * Module Init. + */ +static int __init ipa_test_init(void) +{ + int ret; + + IPATEST_DBG("IPA test driver load...\n"); + + ipa_test = kzalloc(sizeof(*ipa_test), GFP_KERNEL); + if (ipa_test == NULL) { + IPATEST_ERR("kzalloc err.\n"); + return -ENOMEM; + } + ipa_test->signature = TEST_SIGNATURE; + ipa_test->current_configuration_idx = -1; + + ipa_test_class = class_create(THIS_MODULE, IPA_TEST_DRV_NAME); + + ret = alloc_chrdev_region(&ipa_test->dev_num, 0, 1, IPA_TEST_DRV_NAME); + if (ret) { + IPATEST_ERR("alloc_chrdev_region err.\n"); + return -ENODEV; + } + + ipa_test->dev = device_create(ipa_test_class, NULL, + ipa_test->dev_num, + ipa_test, IPA_TEST_DRV_NAME); + if (IS_ERR(ipa_test->dev)) { + IPATEST_ERR("device_create err.\n"); + return -ENODEV; + } + + ipa_test->cdev = cdev_alloc(); + if (ipa_test->cdev == NULL) { + IPATEST_ERR("cdev_alloc err.\n"); + return -ENODEV; + } + + cdev_init(ipa_test->cdev, &ipa_test_fops); + ipa_test->cdev->owner = THIS_MODULE; + + ret = cdev_add(ipa_test->cdev, ipa_test->dev_num, 1); + if (ret) + IPATEST_ERR("cdev_add err=%d\n", -ret); + + if (ret == 0) + IPATEST_DBG("IPA Test init OK, waiting for configuration index.\n"); + else + IPATEST_DBG("IPA Test init FAIL.\n"); + + ret = datapath_ds_init(); + if (ret != 0) + IPATEST_DBG("datapath_ds_init() failed (%d)\n", ret); + + ret = exception_hdl_init(); + if (ret != 0) + IPATEST_DBG("exception_hdl_init() failed (%d)\n", ret); + + return ret; +} + +/** + * Module Exit. + */ +static void __exit ipa_test_exit(void) +{ + IPATEST_DBG("ipa_test_exit.\n"); + + exception_hdl_exit(); /* Clear the Exception Device and KFIFO*/ + + datapath_exit(); + + destroy_channel_devices(); + + cdev_del(ipa_test->cdev); + device_destroy(ipa_test_class, ipa_test->dev_num); + class_destroy(ipa_test_class); + unregister_chrdev_region(ipa_test->dev_num, 1); + + kfree(ipa_test); + + IPATEST_DBG("ipa_test_exit complete.\n"); +} + +module_init(ipa_test_init); +module_exit(ipa_test_exit); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("IPA Testing"); diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_test_module/ipa_test_module_tsp.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_test_module/ipa_test_module_tsp.h new file mode 100644 index 0000000000..f4951a1119 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_test_module/ipa_test_module_tsp.h @@ -0,0 +1,190 @@ +//SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ +/* This file should be removed once TSP feature POR */ +#ifndef _IPA_TEST_MODULE_TSP_H_ +#define _IPA_TEST_MODULE_TSP_H_ + +#include + +#define IPA_IOCTL_TSP_GET_INGR_TC_NUM 91 +#define IPA_IOCTL_TSP_GET_EGR_EP_NUM 92 +#define IPA_IOCTL_TSP_GET_EGR_TC_NUM 93 +#define IPA_IOCTL_TSP_GET_INGR_TC 94 +#define IPA_IOCTL_TSP_GET_EGR_EP 95 +#define IPA_IOCTL_TSP_GET_EGR_TC 96 +#define IPA_IOCTL_TSP_SET_INGR_TC 97 +#define IPA_IOCTL_TSP_SET_EGR_EP 98 +#define IPA_IOCTL_TSP_SET_EGR_TC 99 +#define IPA_IOCTL_TSP_COMMIT 100 +#define IPA_IOCTL_TSP_RESET 101 + +/** + * struct ipa_ioc_tsp_ingress_class_params - IPA Ingress traffic-class params + * + * @max_burst: Maximal-burst allowed in bytes + * @max_rate: Maximal bandwidth rate for matching ingress traffic-class in 1.2MB/second units + * @include_l2_len: Bool - Include L2 size for bandwidth calculation? + */ +struct ipa_ioc_tsp_ingress_class_params { + __u16 max_burst; + __u16 max_rate; + __u32 include_l2_len; +}; + +/** + * struct ipa_ioc_tsp_ingress_class_get - IPA Ingress traffic-class get ioctl struct + * + * @index: Ingress traffic-class index + * @reserved: Reserved for alignment + * @params: Output parameter - Ingress traffic-class Params, valid only when + * ioctl return val is non-negative + */ +struct ipa_ioc_tsp_ingress_class_get { + __u32 index; + __u32 reserved; + struct ipa_ioc_tsp_ingress_class_params params; +}; + +/** + * struct ipa_ioc_tsp_ingress_class_set - IPA Ingress traffic-class set ioctl struct + * + * @index: Ingress traffic-class index + * @commit: Bool - Commit the setting to the HW + * @params: Params to set + */ +struct ipa_ioc_tsp_ingress_class_set { + __u32 index; + __u32 commit; + struct ipa_ioc_tsp_ingress_class_params params; +}; + +/** + * struct ipa_ioc_tsp_egress_prod_params - IPA TSP-enabled producer params + * + * @client: For output - which "clients" pipe does this entry apply to? + * @max_rate: Maximal bandwidth rate for producer in 1.2MB/second units + * @max_burst: Maximal-burst allowed in bytes + * @max_out_bytes: max output size in bytes allowed per producer + * @tc_lo: Lowest egress traffic-class index assignes to this producer + * @tc_hi: Highest egress traffic-class index assignes to this producer + * @policing_by_max_out: Bool - enable policing by max output size + * in case of valid egress_tc, max output size policing will be valid + * regardless to this flag + * @reserved: Reserved for alignment + */ +struct ipa_ioc_tsp_egress_prod_params { + enum ipa_client_type client; + __u16 max_rate; + __u16 max_burst; + __u32 max_out_bytes; + __u8 tc_lo; + __u8 tc_hi; + __u8 policing_by_max_out; + __u8 reserved; +}; + +/** + * struct ipa_ioc_tsp_egress_prod_get - IPA TSP-enabled producer get ioctl struct + * + * @index: TSP-enabled producer index + * @reserved: Reserved for alignment + * @params: Output parameter - TSP-enabled producer Params, valid only when + * ioctl return val is non-negative + */ +struct ipa_ioc_tsp_egress_prod_get { + __u32 index; + __u32 reserved; + struct ipa_ioc_tsp_egress_prod_params params; +}; + +/** + * struct ipa_ioc_tsp_egress_prod_set - IPA TSP-enabled producer set ioctl struct + * + * @index: Producer index + * @commit: Bool - Commit the setting to the HW + * @params: Params to set + */ +struct ipa_ioc_tsp_egress_prod_set { + __u32 index; + __u32 commit; + struct ipa_ioc_tsp_egress_prod_params params; +}; + +/** + * struct ipa_ioc_tsp_egress_class_params - IPA egress traffic-class params + * + * @guaranteed_rate: Guaranteed bandwidth rate for traffic-class in 1.2MB/second units + * If guaranteed_rate, guaranteed_freq and guaranteed_burst are all set to 0, + * the guaranteed bandwidth rate will be disabled, + * and only maximal bandwidth rate will be considered. + * @max_rate: Maximal bandwidth rate for traffic-class in 1.2MB/second units + * @guaranteed_burst: Maximal-burst allowed for guaranteed bandwidth rate (in bytes) + * @max_burst: Maximal-burst allowed for maximal bandwidth rate (in bytes) + */ +struct ipa_ioc_tsp_egress_class_params { + __u16 guaranteed_rate; + __u16 max_rate; + __u16 guaranteed_burst; + __u16 max_burst; +}; + +/** + * struct ipa_ioc_tsp_egress_class_get - IPA Egress traffic-class get ioctl struct + * + * @index: Egress traffic-class index + * @reserved: Reserved for alignment + * @params: Output parameter - Egress traffic-class Params, valid only when + * ioctl return val is non-negative + */ +struct ipa_ioc_tsp_egress_class_get { + __u32 index; + __u32 reserved; + struct ipa_ioc_tsp_egress_class_params params; +}; + +/** + * struct ipa_ioc_tsp_egress_class_set - IPA Engress traffic-class set ioctl struct + * + * @index: Egress traffic-class index + * @commit: Bool - Commit the setting to the HW + * @params: Params to set + */ +struct ipa_ioc_tsp_egress_class_set { + __u32 index; + __u32 commit; + struct ipa_ioc_tsp_egress_class_params params; +}; + +#define IPA_IOC_TSP_GET_INGR_TC_NUM _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_TSP_GET_INGR_TC_NUM, \ + uint32_t) +#define IPA_IOC_TSP_GET_EGR_EP_NUM _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_TSP_GET_EGR_EP_NUM, \ + uint32_t) +#define IPA_IOC_TSP_GET_EGR_TC_NUM _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_TSP_GET_EGR_TC_NUM, \ + uint32_t) +#define IPA_IOC_TSP_GET_INGR_TC _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_TSP_GET_INGR_TC, \ + struct ipa_ioc_tsp_ingress_class_get) +#define IPA_IOC_TSP_GET_EGR_EP _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_TSP_GET_EGR_EP, \ + struct ipa_ioc_tsp_egress_prod_get) +#define IPA_IOC_TSP_GET_EGR_TC _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_TSP_GET_EGR_TC, \ + struct ipa_ioc_tsp_egress_class_get) +#define IPA_IOC_TSP_SET_INGR_TC _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_TSP_SET_INGR_TC, \ + struct ipa_ioc_tsp_ingress_class_set) +#define IPA_IOC_TSP_SET_EGR_EP _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_TSP_SET_EGR_EP, \ + struct ipa_ioc_tsp_egress_prod_set) +#define IPA_IOC_TSP_SET_EGR_TC _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_TSP_SET_EGR_TC, \ + struct ipa_ioc_tsp_egress_class_set) +#define IPA_IOC_TSP_COMMIT _IO(IPA_IOC_MAGIC, IPA_IOCTL_TSP_COMMIT) +#define IPA_IOC_TSP_RESET _IO(IPA_IOC_MAGIC, IPA_IOCTL_TSP_RESET) + +#endif /* _IPA_TEST_MODULE_TSP_H_ */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_uc_offload_common_i.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_uc_offload_common_i.h new file mode 100644 index 0000000000..ecaf93ba3b --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_uc_offload_common_i.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2012-2019, The Linux Foundation. All rights reserved. + */ + +#include +#include + +#ifndef _IPA_UC_OFFLOAD_COMMON_I_H_ +#define _IPA_UC_OFFLOAD_COMMON_I_H_ + +int ipa3_setup_uc_ntn_pipes(struct ipa_ntn_conn_in_params *in, + ipa_notify_cb notify, void *priv, u8 hdr_len, + struct ipa_ntn_conn_out_params *outp); + +int ipa3_tear_down_uc_offload_pipes(int ipa_ep_idx_ul, int ipa_ep_idx_dl, + struct ipa_ntn_conn_in_params *params); + +int ipa3_ntn_uc_reg_rdyCB(void (*ipauc_ready_cb)(void *user_data), + void *user_data); +void ipa3_ntn_uc_dereg_rdyCB(void); +#endif /* _IPA_UC_OFFLOAD_COMMON_I_H_ */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/Kbuild b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/Kbuild new file mode 100644 index 0000000000..4f4fa06fa6 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/Kbuild @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + +obj-$(CONFIG_IPA3_MHI_PRIME_MANAGER) += ipampmm.o +ipampmm-objs := ipa_mpm.o diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.5/gsi_hwio.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.5/gsi_hwio.h new file mode 100644 index 0000000000..1699699af6 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.5/gsi_hwio.h @@ -0,0 +1,2392 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ +#if !defined(_GSI_HWIO_H_) +#define _GSI_HWIO_H_ +/* + * + * HWIO register definitions to follow: + * + */ +#define GSI_REG_BASE (IPA_0_IPA_WRAPPER_BASE + 0x00004000) +#define GSI_REG_BASE_PHYS (IPA_0_IPA_WRAPPER_BASE_PHYS + 0x00004000) +#define GSI_REG_BASE_OFFS 0x00004000 +#define HWIO_GSI_CFG_ADDR (GSI_REG_BASE + 0x00000000) +#define HWIO_GSI_CFG_PHYS (GSI_REG_BASE_PHYS + 0x00000000) +#define HWIO_GSI_CFG_OFFS (GSI_REG_BASE_OFFS + 0x00000000) +#define HWIO_GSI_CFG_RMSK 0xf3f +#define HWIO_GSI_CFG_ATTR 0x3 +#define HWIO_GSI_CFG_IN in_dword_masked(HWIO_GSI_CFG_ADDR, \ + HWIO_GSI_CFG_RMSK) +#define HWIO_GSI_CFG_INM(m) in_dword_masked(HWIO_GSI_CFG_ADDR, m) +#define HWIO_GSI_CFG_OUT(v) out_dword(HWIO_GSI_CFG_ADDR, v) +#define HWIO_GSI_CFG_OUTM(m, v) out_dword_masked_ns(HWIO_GSI_CFG_ADDR, \ + m, \ + v, \ + HWIO_GSI_CFG_IN) +#define HWIO_GSI_CFG_SLEEP_CLK_DIV_BMSK 0xf00 +#define HWIO_GSI_CFG_SLEEP_CLK_DIV_SHFT 0x8 +#define HWIO_GSI_CFG_BP_MTRIX_DISABLE_BMSK 0x20 +#define HWIO_GSI_CFG_BP_MTRIX_DISABLE_SHFT 0x5 +#define HWIO_GSI_CFG_GSI_PWR_CLPS_BMSK 0x10 +#define HWIO_GSI_CFG_GSI_PWR_CLPS_SHFT 0x4 +#define HWIO_GSI_CFG_UC_IS_MCS_BMSK 0x8 +#define HWIO_GSI_CFG_UC_IS_MCS_SHFT 0x3 +#define HWIO_GSI_CFG_DOUBLE_MCS_CLK_FREQ_BMSK 0x4 +#define HWIO_GSI_CFG_DOUBLE_MCS_CLK_FREQ_SHFT 0x2 +#define HWIO_GSI_CFG_MCS_ENABLE_BMSK 0x2 +#define HWIO_GSI_CFG_MCS_ENABLE_SHFT 0x1 +#define HWIO_GSI_CFG_GSI_ENABLE_BMSK 0x1 +#define HWIO_GSI_CFG_GSI_ENABLE_SHFT 0x0 +#define HWIO_GSI_MANAGER_MCS_CODE_VER_ADDR (GSI_REG_BASE + 0x00000008) +#define HWIO_GSI_MANAGER_MCS_CODE_VER_PHYS (GSI_REG_BASE_PHYS + 0x00000008) +#define HWIO_GSI_MANAGER_MCS_CODE_VER_OFFS (GSI_REG_BASE_OFFS + 0x00000008) +#define HWIO_GSI_ZEROS_ADDR (GSI_REG_BASE + 0x00000010) +#define HWIO_GSI_ZEROS_PHYS (GSI_REG_BASE_PHYS + 0x00000010) +#define HWIO_GSI_ZEROS_OFFS (GSI_REG_BASE_OFFS + 0x00000010) +#define HWIO_GSI_PERIPH_BASE_ADDR_LSB_ADDR (GSI_REG_BASE + 0x00000018) +#define HWIO_GSI_PERIPH_BASE_ADDR_LSB_PHYS (GSI_REG_BASE_PHYS + 0x00000018) +#define HWIO_GSI_PERIPH_BASE_ADDR_LSB_OFFS (GSI_REG_BASE_OFFS + 0x00000018) +#define HWIO_GSI_PERIPH_BASE_ADDR_MSB_ADDR (GSI_REG_BASE + 0x0000001c) +#define HWIO_GSI_PERIPH_BASE_ADDR_MSB_PHYS (GSI_REG_BASE_PHYS + 0x0000001c) +#define HWIO_GSI_PERIPH_BASE_ADDR_MSB_OFFS (GSI_REG_BASE_OFFS + 0x0000001c) +#define HWIO_GSI_PERIPH_PENDING_ADDR (GSI_REG_BASE + 0x00000020) +#define HWIO_GSI_PERIPH_PENDING_PHYS (GSI_REG_BASE_PHYS + 0x00000020) +#define HWIO_GSI_PERIPH_PENDING_OFFS (GSI_REG_BASE_OFFS + 0x00000020) +#define HWIO_GSI_MOQA_CFG_ADDR (GSI_REG_BASE + 0x00000030) +#define HWIO_GSI_MOQA_CFG_PHYS (GSI_REG_BASE_PHYS + 0x00000030) +#define HWIO_GSI_MOQA_CFG_OFFS (GSI_REG_BASE_OFFS + 0x00000030) +#define HWIO_GSI_REE_CFG_ADDR (GSI_REG_BASE + 0x00000038) +#define HWIO_GSI_REE_CFG_PHYS (GSI_REG_BASE_PHYS + 0x00000038) +#define HWIO_GSI_REE_CFG_OFFS (GSI_REG_BASE_OFFS + 0x00000038) +#define HWIO_GSI_REE_CFG_RMSK 0xff03 +#define HWIO_GSI_REE_CFG_ATTR 0x3 +#define HWIO_GSI_REE_CFG_IN in_dword_masked(HWIO_GSI_REE_CFG_ADDR, \ + HWIO_GSI_REE_CFG_RMSK) +#define HWIO_GSI_REE_CFG_INM(m) in_dword_masked(HWIO_GSI_REE_CFG_ADDR, m) +#define HWIO_GSI_REE_CFG_OUT(v) out_dword(HWIO_GSI_REE_CFG_ADDR, v) +#define HWIO_GSI_REE_CFG_OUTM(m, v) out_dword_masked_ns( \ + HWIO_GSI_REE_CFG_ADDR, \ + m, \ + v, \ + HWIO_GSI_REE_CFG_IN) +#define HWIO_GSI_REE_CFG_MAX_BURST_SIZE_BMSK 0xff00 +#define HWIO_GSI_REE_CFG_MAX_BURST_SIZE_SHFT 0x8 +#define HWIO_GSI_REE_CFG_CHANNEL_EMPTY_INT_ENABLE_BMSK 0x2 +#define HWIO_GSI_REE_CFG_CHANNEL_EMPTY_INT_ENABLE_SHFT 0x1 +#define HWIO_GSI_REE_CFG_MOVE_TO_ESC_CLR_MODE_TRSH_BMSK 0x1 +#define HWIO_GSI_REE_CFG_MOVE_TO_ESC_CLR_MODE_TRSH_SHFT 0x0 +#define HWIO_GSI_CGC_CTRL_ADDR (GSI_REG_BASE + 0x00000060) +#define HWIO_GSI_CGC_CTRL_PHYS (GSI_REG_BASE_PHYS + 0x00000060) +#define HWIO_GSI_CGC_CTRL_OFFS (GSI_REG_BASE_OFFS + 0x00000060) +#define HWIO_GSI_MSI_CACHEATTR_ADDR (GSI_REG_BASE + 0x00000080) +#define HWIO_GSI_MSI_CACHEATTR_PHYS (GSI_REG_BASE_PHYS + 0x00000080) +#define HWIO_GSI_MSI_CACHEATTR_OFFS (GSI_REG_BASE_OFFS + 0x00000080) +#define HWIO_GSI_EVENT_CACHEATTR_ADDR (GSI_REG_BASE + 0x00000084) +#define HWIO_GSI_EVENT_CACHEATTR_PHYS (GSI_REG_BASE_PHYS + 0x00000084) +#define HWIO_GSI_EVENT_CACHEATTR_OFFS (GSI_REG_BASE_OFFS + 0x00000084) +#define HWIO_GSI_DATA_CACHEATTR_ADDR (GSI_REG_BASE + 0x00000088) +#define HWIO_GSI_DATA_CACHEATTR_PHYS (GSI_REG_BASE_PHYS + 0x00000088) +#define HWIO_GSI_DATA_CACHEATTR_OFFS (GSI_REG_BASE_OFFS + 0x00000088) +#define HWIO_GSI_TRE_CACHEATTR_ADDR (GSI_REG_BASE + 0x00000090) +#define HWIO_GSI_TRE_CACHEATTR_PHYS (GSI_REG_BASE_PHYS + 0x00000090) +#define HWIO_GSI_TRE_CACHEATTR_OFFS (GSI_REG_BASE_OFFS + 0x00000090) +#define HWIO_IC_DISABLE_CHNL_BCK_PRS_LSB_ADDR (GSI_REG_BASE + 0x000000a0) +#define HWIO_IC_DISABLE_CHNL_BCK_PRS_LSB_PHYS (GSI_REG_BASE_PHYS + \ + 0x000000a0) +#define HWIO_IC_DISABLE_CHNL_BCK_PRS_LSB_OFFS (GSI_REG_BASE_OFFS + \ + 0x000000a0) +#define HWIO_IC_DISABLE_CHNL_BCK_PRS_MSB_ADDR (GSI_REG_BASE + 0x000000a4) +#define HWIO_IC_DISABLE_CHNL_BCK_PRS_MSB_PHYS (GSI_REG_BASE_PHYS + \ + 0x000000a4) +#define HWIO_IC_DISABLE_CHNL_BCK_PRS_MSB_OFFS (GSI_REG_BASE_OFFS + \ + 0x000000a4) +#define HWIO_IC_GEN_EVNT_BCK_PRS_LSB_ADDR (GSI_REG_BASE + 0x000000a8) +#define HWIO_IC_GEN_EVNT_BCK_PRS_LSB_PHYS (GSI_REG_BASE_PHYS + 0x000000a8) +#define HWIO_IC_GEN_EVNT_BCK_PRS_LSB_OFFS (GSI_REG_BASE_OFFS + 0x000000a8) +#define HWIO_IC_GEN_EVNT_BCK_PRS_MSB_ADDR (GSI_REG_BASE + 0x000000ac) +#define HWIO_IC_GEN_EVNT_BCK_PRS_MSB_PHYS (GSI_REG_BASE_PHYS + 0x000000ac) +#define HWIO_IC_GEN_EVNT_BCK_PRS_MSB_OFFS (GSI_REG_BASE_OFFS + 0x000000ac) +#define HWIO_IC_GEN_INT_BCK_PRS_LSB_ADDR (GSI_REG_BASE + 0x000000b0) +#define HWIO_IC_GEN_INT_BCK_PRS_LSB_PHYS (GSI_REG_BASE_PHYS + 0x000000b0) +#define HWIO_IC_GEN_INT_BCK_PRS_LSB_OFFS (GSI_REG_BASE_OFFS + 0x000000b0) +#define HWIO_IC_GEN_INT_BCK_PRS_MSB_ADDR (GSI_REG_BASE + 0x000000b4) +#define HWIO_IC_GEN_INT_BCK_PRS_MSB_PHYS (GSI_REG_BASE_PHYS + 0x000000b4) +#define HWIO_IC_GEN_INT_BCK_PRS_MSB_OFFS (GSI_REG_BASE_OFFS + 0x000000b4) +#define HWIO_IC_STOP_INT_MOD_BCK_PRS_LSB_ADDR (GSI_REG_BASE + 0x000000b8) +#define HWIO_IC_STOP_INT_MOD_BCK_PRS_LSB_PHYS (GSI_REG_BASE_PHYS + \ + 0x000000b8) +#define HWIO_IC_STOP_INT_MOD_BCK_PRS_LSB_OFFS (GSI_REG_BASE_OFFS + \ + 0x000000b8) +#define HWIO_IC_STOP_INT_MOD_BCK_PRS_MSB_ADDR (GSI_REG_BASE + 0x000000bc) +#define HWIO_IC_STOP_INT_MOD_BCK_PRS_MSB_PHYS (GSI_REG_BASE_PHYS + \ + 0x000000bc) +#define HWIO_IC_STOP_INT_MOD_BCK_PRS_MSB_OFFS (GSI_REG_BASE_OFFS + \ + 0x000000bc) +#define HWIO_IC_PROCESS_DESC_BCK_PRS_LSB_ADDR (GSI_REG_BASE + 0x000000c0) +#define HWIO_IC_PROCESS_DESC_BCK_PRS_LSB_PHYS (GSI_REG_BASE_PHYS + \ + 0x000000c0) +#define HWIO_IC_PROCESS_DESC_BCK_PRS_LSB_OFFS (GSI_REG_BASE_OFFS + \ + 0x000000c0) +#define HWIO_IC_PROCESS_DESC_BCK_PRS_MSB_ADDR (GSI_REG_BASE + 0x000000c4) +#define HWIO_IC_PROCESS_DESC_BCK_PRS_MSB_PHYS (GSI_REG_BASE_PHYS + \ + 0x000000c4) +#define HWIO_IC_PROCESS_DESC_BCK_PRS_MSB_OFFS (GSI_REG_BASE_OFFS + \ + 0x000000c4) +#define HWIO_IC_TLV_STOP_BCK_PRS_LSB_ADDR (GSI_REG_BASE + 0x000000c8) +#define HWIO_IC_TLV_STOP_BCK_PRS_LSB_PHYS (GSI_REG_BASE_PHYS + 0x000000c8) +#define HWIO_IC_TLV_STOP_BCK_PRS_LSB_OFFS (GSI_REG_BASE_OFFS + 0x000000c8) +#define HWIO_IC_TLV_STOP_BCK_PRS_MSB_ADDR (GSI_REG_BASE + 0x000000cc) +#define HWIO_IC_TLV_STOP_BCK_PRS_MSB_PHYS (GSI_REG_BASE_PHYS + 0x000000cc) +#define HWIO_IC_TLV_STOP_BCK_PRS_MSB_OFFS (GSI_REG_BASE_OFFS + 0x000000cc) +#define HWIO_IC_TLV_RESET_BCK_PRS_LSB_ADDR (GSI_REG_BASE + 0x000000d0) +#define HWIO_IC_TLV_RESET_BCK_PRS_LSB_PHYS (GSI_REG_BASE_PHYS + 0x000000d0) +#define HWIO_IC_TLV_RESET_BCK_PRS_LSB_OFFS (GSI_REG_BASE_OFFS + 0x000000d0) +#define HWIO_IC_TLV_RESET_BCK_PRS_MSB_ADDR (GSI_REG_BASE + 0x000000d4) +#define HWIO_IC_TLV_RESET_BCK_PRS_MSB_PHYS (GSI_REG_BASE_PHYS + 0x000000d4) +#define HWIO_IC_TLV_RESET_BCK_PRS_MSB_OFFS (GSI_REG_BASE_OFFS + 0x000000d4) +#define HWIO_IC_RGSTR_TIMER_BCK_PRS_LSB_ADDR (GSI_REG_BASE + 0x000000d8) +#define HWIO_IC_RGSTR_TIMER_BCK_PRS_LSB_PHYS (GSI_REG_BASE_PHYS + \ + 0x000000d8) +#define HWIO_IC_RGSTR_TIMER_BCK_PRS_LSB_OFFS (GSI_REG_BASE_OFFS + \ + 0x000000d8) +#define HWIO_IC_RGSTR_TIMER_BCK_PRS_MSB_ADDR (GSI_REG_BASE + 0x000000dc) +#define HWIO_IC_RGSTR_TIMER_BCK_PRS_MSB_PHYS (GSI_REG_BASE_PHYS + \ + 0x000000dc) +#define HWIO_IC_RGSTR_TIMER_BCK_PRS_MSB_OFFS (GSI_REG_BASE_OFFS + \ + 0x000000dc) +#define HWIO_IC_READ_BCK_PRS_LSB_ADDR (GSI_REG_BASE + 0x000000e0) +#define HWIO_IC_READ_BCK_PRS_LSB_PHYS (GSI_REG_BASE_PHYS + 0x000000e0) +#define HWIO_IC_READ_BCK_PRS_LSB_OFFS (GSI_REG_BASE_OFFS + 0x000000e0) +#define HWIO_IC_READ_BCK_PRS_MSB_ADDR (GSI_REG_BASE + 0x000000e4) +#define HWIO_IC_READ_BCK_PRS_MSB_PHYS (GSI_REG_BASE_PHYS + 0x000000e4) +#define HWIO_IC_READ_BCK_PRS_MSB_OFFS (GSI_REG_BASE_OFFS + 0x000000e4) +#define HWIO_IC_WRITE_BCK_PRS_LSB_ADDR (GSI_REG_BASE + 0x000000e8) +#define HWIO_IC_WRITE_BCK_PRS_LSB_PHYS (GSI_REG_BASE_PHYS + 0x000000e8) +#define HWIO_IC_WRITE_BCK_PRS_LSB_OFFS (GSI_REG_BASE_OFFS + 0x000000e8) +#define HWIO_IC_WRITE_BCK_PRS_MSB_ADDR (GSI_REG_BASE + 0x000000ec) +#define HWIO_IC_WRITE_BCK_PRS_MSB_PHYS (GSI_REG_BASE_PHYS + 0x000000ec) +#define HWIO_IC_WRITE_BCK_PRS_MSB_OFFS (GSI_REG_BASE_OFFS + 0x000000ec) +#define HWIO_IC_UCONTROLLER_GPR_BCK_PRS_LSB_ADDR (GSI_REG_BASE + \ + 0x000000f0) +#define HWIO_IC_UCONTROLLER_GPR_BCK_PRS_LSB_PHYS (GSI_REG_BASE_PHYS + \ + 0x000000f0) +#define HWIO_IC_UCONTROLLER_GPR_BCK_PRS_LSB_OFFS (GSI_REG_BASE_OFFS + \ + 0x000000f0) +#define HWIO_IC_UCONTROLLER_GPR_BCK_PRS_MSB_ADDR (GSI_REG_BASE + \ + 0x000000f4) +#define HWIO_IC_UCONTROLLER_GPR_BCK_PRS_MSB_PHYS (GSI_REG_BASE_PHYS + \ + 0x000000f4) +#define HWIO_IC_UCONTROLLER_GPR_BCK_PRS_MSB_OFFS (GSI_REG_BASE_OFFS + \ + 0x000000f4) +#define HWIO_IC_INT_WEIGHT_REE_ADDR (GSI_REG_BASE + 0x00000100) +#define HWIO_IC_INT_WEIGHT_REE_PHYS (GSI_REG_BASE_PHYS + 0x00000100) +#define HWIO_IC_INT_WEIGHT_REE_OFFS (GSI_REG_BASE_OFFS + 0x00000100) +#define HWIO_IC_INT_WEIGHT_EVT_ENG_ADDR (GSI_REG_BASE + 0x00000104) +#define HWIO_IC_INT_WEIGHT_EVT_ENG_PHYS (GSI_REG_BASE_PHYS + 0x00000104) +#define HWIO_IC_INT_WEIGHT_EVT_ENG_OFFS (GSI_REG_BASE_OFFS + 0x00000104) +#define HWIO_IC_INT_WEIGHT_INT_ENG_ADDR (GSI_REG_BASE + 0x00000108) +#define HWIO_IC_INT_WEIGHT_INT_ENG_PHYS (GSI_REG_BASE_PHYS + 0x00000108) +#define HWIO_IC_INT_WEIGHT_INT_ENG_OFFS (GSI_REG_BASE_OFFS + 0x00000108) +#define HWIO_IC_INT_WEIGHT_CSR_ADDR (GSI_REG_BASE + 0x0000010c) +#define HWIO_IC_INT_WEIGHT_CSR_PHYS (GSI_REG_BASE_PHYS + 0x0000010c) +#define HWIO_IC_INT_WEIGHT_CSR_OFFS (GSI_REG_BASE_OFFS + 0x0000010c) +#define HWIO_IC_INT_WEIGHT_TLV_ENG_ADDR (GSI_REG_BASE + 0x00000110) +#define HWIO_IC_INT_WEIGHT_TLV_ENG_PHYS (GSI_REG_BASE_PHYS + 0x00000110) +#define HWIO_IC_INT_WEIGHT_TLV_ENG_OFFS (GSI_REG_BASE_OFFS + 0x00000110) +#define HWIO_IC_INT_WEIGHT_TIMER_ENG_ADDR (GSI_REG_BASE + 0x00000114) +#define HWIO_IC_INT_WEIGHT_TIMER_ENG_PHYS (GSI_REG_BASE_PHYS + 0x00000114) +#define HWIO_IC_INT_WEIGHT_TIMER_ENG_OFFS (GSI_REG_BASE_OFFS + 0x00000114) +#define HWIO_IC_INT_WEIGHT_DB_ENG_ADDR (GSI_REG_BASE + 0x00000118) +#define HWIO_IC_INT_WEIGHT_DB_ENG_PHYS (GSI_REG_BASE_PHYS + 0x00000118) +#define HWIO_IC_INT_WEIGHT_DB_ENG_OFFS (GSI_REG_BASE_OFFS + 0x00000118) +#define HWIO_IC_INT_WEIGHT_RD_WR_ENG_ADDR (GSI_REG_BASE + 0x0000011c) +#define HWIO_IC_INT_WEIGHT_RD_WR_ENG_PHYS (GSI_REG_BASE_PHYS + 0x0000011c) +#define HWIO_IC_INT_WEIGHT_RD_WR_ENG_OFFS (GSI_REG_BASE_OFFS + 0x0000011c) +#define HWIO_IC_INT_WEIGHT_UCONTROLLER_ENG_ADDR (GSI_REG_BASE + 0x00000120) +#define HWIO_IC_INT_WEIGHT_UCONTROLLER_ENG_PHYS (GSI_REG_BASE_PHYS + \ + 0x00000120) +#define HWIO_IC_INT_WEIGHT_UCONTROLLER_ENG_OFFS (GSI_REG_BASE_OFFS + \ + 0x00000120) +#define HWIO_IC_INT_WEIGHT_SDMA_ADDR (GSI_REG_BASE + 0x00000124) +#define HWIO_IC_INT_WEIGHT_SDMA_PHYS (GSI_REG_BASE_PHYS + 0x00000124) +#define HWIO_IC_INT_WEIGHT_SDMA_OFFS (GSI_REG_BASE_OFFS + 0x00000124) +#define HWIO_GSI_SDMA_CFG_ADDR (GSI_REG_BASE + 0x0000003c) +#define HWIO_GSI_SDMA_CFG_PHYS (GSI_REG_BASE_PHYS + 0x0000003c) +#define HWIO_GSI_SDMA_CFG_OFFS (GSI_REG_BASE_OFFS + 0x0000003c) +#define HWIO_GSI_SDMA_CACHEATTR_ADDR (GSI_REG_BASE + 0x00000094) +#define HWIO_GSI_SDMA_CACHEATTR_PHYS (GSI_REG_BASE_PHYS + 0x00000094) +#define HWIO_GSI_SDMA_CACHEATTR_OFFS (GSI_REG_BASE_OFFS + 0x00000094) +#define HWIO_GSI_SDMA_SG_IOVEC_LSB_n_ADDR(n) (GSI_REG_BASE + 0x00000140 + \ + 0x8 * (n)) +#define HWIO_GSI_SDMA_SG_IOVEC_LSB_n_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x00000140 + 0x8 * (n)) +#define HWIO_GSI_SDMA_SG_IOVEC_LSB_n_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x00000140 + 0x8 * (n)) +#define HWIO_GSI_SDMA_SG_IOVEC_MSB_n_ADDR(n) (GSI_REG_BASE + 0x00000144 + \ + 0x8 * (n)) +#define HWIO_GSI_SDMA_SG_IOVEC_MSB_n_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x00000144 + 0x8 * (n)) +#define HWIO_GSI_SDMA_SG_IOVEC_MSB_n_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x00000144 + 0x8 * (n)) +#define HWIO_GSI_MANAGER_EE_QOS_n_ADDR(n) (GSI_REG_BASE + 0x00000300 + \ + 0x4 * (n)) +#define HWIO_GSI_MANAGER_EE_QOS_n_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x00000300 + 0x4 * (n)) +#define HWIO_GSI_MANAGER_EE_QOS_n_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x00000300 + 0x4 * (n)) +#define HWIO_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_ADDR (GSI_REG_BASE + \ + 0x00000200) +#define HWIO_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_PHYS (GSI_REG_BASE_PHYS + \ + 0x00000200) +#define HWIO_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_OFFS (GSI_REG_BASE_OFFS + \ + 0x00000200) +#define HWIO_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_ADDR (GSI_REG_BASE + \ + 0x00000204) +#define HWIO_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_PHYS (GSI_REG_BASE_PHYS + \ + 0x00000204) +#define HWIO_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_OFFS (GSI_REG_BASE_OFFS + \ + 0x00000204) +#define HWIO_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_ADDR (GSI_REG_BASE + \ + 0x00000208) +#define HWIO_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_PHYS (GSI_REG_BASE_PHYS + \ + 0x00000208) +#define HWIO_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_OFFS (GSI_REG_BASE_OFFS + \ + 0x00000208) +#define HWIO_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_ADDR (GSI_REG_BASE + \ + 0x0000020c) +#define HWIO_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_PHYS (GSI_REG_BASE_PHYS + \ + 0x0000020c) +#define HWIO_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_OFFS (GSI_REG_BASE_OFFS + \ + 0x0000020c) +#define HWIO_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_ADDR (GSI_REG_BASE + \ + 0x00000240) +#define HWIO_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_PHYS (GSI_REG_BASE_PHYS + \ + 0x00000240) +#define HWIO_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_OFFS (GSI_REG_BASE_OFFS + \ + 0x00000240) +#define HWIO_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_ADDR (GSI_REG_BASE + \ + 0x00000244) +#define HWIO_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_PHYS (GSI_REG_BASE_PHYS + \ + 0x00000244) +#define HWIO_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_OFFS (GSI_REG_BASE_OFFS + \ + 0x00000244) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_ADDR (GSI_REG_BASE + \ + 0x00000248) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_PHYS (GSI_REG_BASE_PHYS + \ + 0x00000248) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_OFFS (GSI_REG_BASE_OFFS + \ + 0x00000248) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_ADDR (GSI_REG_BASE + \ + 0x0000024c) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_PHYS (GSI_REG_BASE_PHYS \ + + 0x0000024c) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_OFFS (GSI_REG_BASE_OFFS \ + + 0x0000024c) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_ADDR (GSI_REG_BASE + \ + 0x00000250) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_PHYS (GSI_REG_BASE_PHYS \ + + 0x00000250) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_OFFS (GSI_REG_BASE_OFFS \ + + 0x00000250) +#define HWIO_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_ADDR (GSI_REG_BASE \ + + 0x00000254) +#define HWIO_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_PHYS ( \ + GSI_REG_BASE_PHYS + 0x00000254) +#define HWIO_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_OFFS ( \ + GSI_REG_BASE_OFFS + 0x00000254) +#define HWIO_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_ADDR (GSI_REG_BASE \ + + 0x00000258) +#define HWIO_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_PHYS ( \ + GSI_REG_BASE_PHYS + 0x00000258) +#define HWIO_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_OFFS ( \ + GSI_REG_BASE_OFFS + 0x00000258) +#define HWIO_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_ADDR (GSI_REG_BASE + \ + 0x0000025c) +#define HWIO_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_PHYS ( \ + GSI_REG_BASE_PHYS + 0x0000025c) +#define HWIO_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_OFFS ( \ + GSI_REG_BASE_OFFS + 0x0000025c) +#define HWIO_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_ADDR (GSI_REG_BASE + \ + 0x00000260) +#define HWIO_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_PHYS (GSI_REG_BASE_PHYS + \ + 0x00000260) +#define HWIO_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_OFFS (GSI_REG_BASE_OFFS + \ + 0x00000260) +#define HWIO_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_ADDR (GSI_REG_BASE + \ + 0x00000264) +#define HWIO_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_PHYS (GSI_REG_BASE_PHYS + \ + 0x00000264) +#define HWIO_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_OFFS (GSI_REG_BASE_OFFS + \ + 0x00000264) +#define HWIO_GSI_IRAM_PTR_CH_CMD_ADDR (GSI_REG_BASE + 0x00000400) +#define HWIO_GSI_IRAM_PTR_CH_CMD_PHYS (GSI_REG_BASE_PHYS + 0x00000400) +#define HWIO_GSI_IRAM_PTR_CH_CMD_OFFS (GSI_REG_BASE_OFFS + 0x00000400) +#define HWIO_GSI_IRAM_PTR_EE_GENERIC_CMD_ADDR (GSI_REG_BASE + 0x00000404) +#define HWIO_GSI_IRAM_PTR_EE_GENERIC_CMD_PHYS (GSI_REG_BASE_PHYS + \ + 0x00000404) +#define HWIO_GSI_IRAM_PTR_EE_GENERIC_CMD_OFFS (GSI_REG_BASE_OFFS + \ + 0x00000404) +#define HWIO_GSI_IRAM_PTR_TLV_CH_NOT_FULL_ADDR (GSI_REG_BASE + 0x00000408) +#define HWIO_GSI_IRAM_PTR_TLV_CH_NOT_FULL_PHYS (GSI_REG_BASE_PHYS + \ + 0x00000408) +#define HWIO_GSI_IRAM_PTR_TLV_CH_NOT_FULL_OFFS (GSI_REG_BASE_OFFS + \ + 0x00000408) +#define HWIO_GSI_IRAM_PTR_CH_DB_ADDR (GSI_REG_BASE + 0x00000418) +#define HWIO_GSI_IRAM_PTR_CH_DB_PHYS (GSI_REG_BASE_PHYS + 0x00000418) +#define HWIO_GSI_IRAM_PTR_CH_DB_OFFS (GSI_REG_BASE_OFFS + 0x00000418) +#define HWIO_GSI_IRAM_PTR_EV_DB_ADDR (GSI_REG_BASE + 0x0000041c) +#define HWIO_GSI_IRAM_PTR_EV_DB_PHYS (GSI_REG_BASE_PHYS + 0x0000041c) +#define HWIO_GSI_IRAM_PTR_EV_DB_OFFS (GSI_REG_BASE_OFFS + 0x0000041c) +#define HWIO_GSI_IRAM_PTR_NEW_RE_ADDR (GSI_REG_BASE + 0x00000420) +#define HWIO_GSI_IRAM_PTR_NEW_RE_PHYS (GSI_REG_BASE_PHYS + 0x00000420) +#define HWIO_GSI_IRAM_PTR_NEW_RE_OFFS (GSI_REG_BASE_OFFS + 0x00000420) +#define HWIO_GSI_IRAM_PTR_CH_DIS_COMP_ADDR (GSI_REG_BASE + 0x00000424) +#define HWIO_GSI_IRAM_PTR_CH_DIS_COMP_PHYS (GSI_REG_BASE_PHYS + 0x00000424) +#define HWIO_GSI_IRAM_PTR_CH_DIS_COMP_OFFS (GSI_REG_BASE_OFFS + 0x00000424) +#define HWIO_GSI_IRAM_PTR_CH_EMPTY_ADDR (GSI_REG_BASE + 0x00000428) +#define HWIO_GSI_IRAM_PTR_CH_EMPTY_PHYS (GSI_REG_BASE_PHYS + 0x00000428) +#define HWIO_GSI_IRAM_PTR_CH_EMPTY_OFFS (GSI_REG_BASE_OFFS + 0x00000428) +#define HWIO_GSI_IRAM_PTR_EVENT_GEN_COMP_ADDR (GSI_REG_BASE + 0x0000042c) +#define HWIO_GSI_IRAM_PTR_EVENT_GEN_COMP_PHYS (GSI_REG_BASE_PHYS + \ + 0x0000042c) +#define HWIO_GSI_IRAM_PTR_EVENT_GEN_COMP_OFFS (GSI_REG_BASE_OFFS + \ + 0x0000042c) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_ADDR (GSI_REG_BASE + \ + 0x00000430) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_PHYS (GSI_REG_BASE_PHYS + \ + 0x00000430) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_OFFS (GSI_REG_BASE_OFFS + \ + 0x00000430) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_ADDR (GSI_REG_BASE + \ + 0x00000434) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_PHYS (GSI_REG_BASE_PHYS + \ + 0x00000434) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_OFFS (GSI_REG_BASE_OFFS + \ + 0x00000434) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_ADDR (GSI_REG_BASE + \ + 0x00000438) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_PHYS (GSI_REG_BASE_PHYS + \ + 0x00000438) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_OFFS (GSI_REG_BASE_OFFS + \ + 0x00000438) +#define HWIO_GSI_IRAM_PTR_TIMER_EXPIRED_ADDR (GSI_REG_BASE + 0x0000043c) +#define HWIO_GSI_IRAM_PTR_TIMER_EXPIRED_PHYS (GSI_REG_BASE_PHYS + \ + 0x0000043c) +#define HWIO_GSI_IRAM_PTR_TIMER_EXPIRED_OFFS (GSI_REG_BASE_OFFS + \ + 0x0000043c) +#define HWIO_GSI_IRAM_PTR_WRITE_ENG_COMP_ADDR (GSI_REG_BASE + 0x00000440) +#define HWIO_GSI_IRAM_PTR_WRITE_ENG_COMP_PHYS (GSI_REG_BASE_PHYS + \ + 0x00000440) +#define HWIO_GSI_IRAM_PTR_WRITE_ENG_COMP_OFFS (GSI_REG_BASE_OFFS + \ + 0x00000440) +#define HWIO_GSI_IRAM_PTR_READ_ENG_COMP_ADDR (GSI_REG_BASE + 0x00000444) +#define HWIO_GSI_IRAM_PTR_READ_ENG_COMP_PHYS (GSI_REG_BASE_PHYS + \ + 0x00000444) +#define HWIO_GSI_IRAM_PTR_READ_ENG_COMP_OFFS (GSI_REG_BASE_OFFS + \ + 0x00000444) +#define HWIO_GSI_IRAM_PTR_UC_GP_INT_ADDR (GSI_REG_BASE + 0x00000448) +#define HWIO_GSI_IRAM_PTR_UC_GP_INT_PHYS (GSI_REG_BASE_PHYS + 0x00000448) +#define HWIO_GSI_IRAM_PTR_UC_GP_INT_OFFS (GSI_REG_BASE_OFFS + 0x00000448) +#define HWIO_GSI_IRAM_PTR_INT_MOD_STOPPED_ADDR (GSI_REG_BASE + 0x0000044c) +#define HWIO_GSI_IRAM_PTR_INT_MOD_STOPPED_PHYS (GSI_REG_BASE_PHYS + \ + 0x0000044c) +#define HWIO_GSI_IRAM_PTR_INT_MOD_STOPPED_OFFS (GSI_REG_BASE_OFFS + \ + 0x0000044c) +#define HWIO_GSI_IRAM_PTR_SDMA_INT_n_ADDR(n) (GSI_REG_BASE + 0x00000450 + \ + 0x4 * (n)) +#define HWIO_GSI_IRAM_PTR_SDMA_INT_n_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x00000450 + 0x4 * (n)) +#define HWIO_GSI_IRAM_PTR_SDMA_INT_n_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x00000450 + 0x4 * (n)) +#define HWIO_GSI_INST_RAM_n_ADDR(n) (GSI_REG_BASE + 0x0001b000 + 0x4 * (n)) +#define HWIO_GSI_INST_RAM_n_PHYS(n) (GSI_REG_BASE_PHYS + 0x0001b000 + \ + 0x4 * (n)) +#define HWIO_GSI_INST_RAM_n_OFFS(n) (GSI_REG_BASE_OFFS + 0x0001b000 + \ + 0x4 * (n)) +#define HWIO_GSI_SHRAM_n_ADDR(n) (GSI_REG_BASE + 0x00002000 + 0x4 * (n)) +#define HWIO_GSI_SHRAM_n_PHYS(n) (GSI_REG_BASE_PHYS + 0x00002000 + 0x4 * \ + (n)) +#define HWIO_GSI_SHRAM_n_OFFS(n) (GSI_REG_BASE_OFFS + 0x00002000 + 0x4 * \ + (n)) +#define HWIO_GSI_SHRAM_n_RMSK 0xffffffff +#define HWIO_GSI_SHRAM_n_MAXn 1343 +#define HWIO_GSI_SHRAM_n_ATTR 0x3 +#define HWIO_GSI_SHRAM_n_INI(n) in_dword_masked(HWIO_GSI_SHRAM_n_ADDR( \ + n), \ + HWIO_GSI_SHRAM_n_RMSK) +#define HWIO_GSI_SHRAM_n_INMI(n, mask) in_dword_masked( \ + HWIO_GSI_SHRAM_n_ADDR(n), \ + mask) +#define HWIO_GSI_SHRAM_n_OUTI(n, val) out_dword(HWIO_GSI_SHRAM_n_ADDR( \ + n), val) +#define HWIO_GSI_SHRAM_n_OUTMI(n, mask, val) out_dword_masked_ns( \ + HWIO_GSI_SHRAM_n_ADDR(n), \ + mask, \ + val, \ + HWIO_GSI_SHRAM_n_INI(n)) +#define HWIO_GSI_SHRAM_n_SHRAM_BMSK 0xffffffff +#define HWIO_GSI_SHRAM_n_SHRAM_SHFT 0x0 +#define HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_ADDR(n, k) (GSI_REG_BASE + \ + 0x00003800 + 0x80 * \ + (n) + 0x4 * (k)) +#define HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x00003800 + 0x80 * \ + (n) + 0x4 * (k)) +#define HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x00003800 + 0x80 * \ + (n) + 0x4 * (k)) +#define HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_RMSK 0x3f +#define HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_MAXn 2 +#define HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_MAXk 22 +#define HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_ATTR 0x3 +#define HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_INI2(n, k) in_dword_masked( \ + HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_ADDR(n, k), \ + HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_RMSK) +#define HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_INMI2(n, k, mask) in_dword_masked( \ + HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_ADDR(n, k), \ + mask) +#define HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_OUTI2(n, k, val) out_dword( \ + HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_ADDR(n, k), \ + val) +#define HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_INI2(n, k)) +#define HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_VALID_BMSK 0x20 +#define HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_VALID_SHFT 0x5 +#define HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_PHY_CH_BMSK 0x1f +#define HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_PHY_CH_SHFT 0x0 +#define HWIO_GSI_TEST_BUS_SEL_ADDR (GSI_REG_BASE + 0x00001000) +#define HWIO_GSI_TEST_BUS_SEL_PHYS (GSI_REG_BASE_PHYS + 0x00001000) +#define HWIO_GSI_TEST_BUS_SEL_OFFS (GSI_REG_BASE_OFFS + 0x00001000) +#define HWIO_GSI_TEST_BUS_SEL_RMSK 0xf00ff +#define HWIO_GSI_TEST_BUS_SEL_ATTR 0x3 +#define HWIO_GSI_TEST_BUS_SEL_IN in_dword_masked( \ + HWIO_GSI_TEST_BUS_SEL_ADDR, \ + HWIO_GSI_TEST_BUS_SEL_RMSK) +#define HWIO_GSI_TEST_BUS_SEL_INM(m) in_dword_masked( \ + HWIO_GSI_TEST_BUS_SEL_ADDR, \ + m) +#define HWIO_GSI_TEST_BUS_SEL_OUT(v) out_dword(HWIO_GSI_TEST_BUS_SEL_ADDR, \ + v) +#define HWIO_GSI_TEST_BUS_SEL_OUTM(m, v) out_dword_masked_ns( \ + HWIO_GSI_TEST_BUS_SEL_ADDR, \ + m, \ + v, \ + HWIO_GSI_TEST_BUS_SEL_IN) +#define HWIO_GSI_TEST_BUS_SEL_GSI_HW_EVENTS_SEL_BMSK 0xf0000 +#define HWIO_GSI_TEST_BUS_SEL_GSI_HW_EVENTS_SEL_SHFT 0x10 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_BMSK 0xff +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_SHFT 0x0 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_ZEROS_FVAL 0x0 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MCS_0_FVAL 0x1 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MCS_1_FVAL 0x2 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MCS_2_FVAL 0x3 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MCS_3_FVAL 0x4 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MCS_4_FVAL 0x5 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_DB_ENG_FVAL 0x9 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_0_FVAL 0xb +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_1_FVAL 0xc +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_2_FVAL 0xd +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_3_FVAL 0xe +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_4_FVAL 0xf +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_5_FVAL 0x10 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_6_FVAL 0x11 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_7_FVAL 0x12 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_EVE_0_FVAL 0x13 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_EVE_1_FVAL 0x14 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_EVE_2_FVAL 0x15 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_EVE_3_FVAL 0x16 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_EVE_4_FVAL 0x17 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_EVE_5_FVAL 0x18 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IE_0_FVAL 0x1b +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IE_1_FVAL 0x1c +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IE_2_FVAL 0x1d +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IC_0_FVAL 0x1f +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IC_1_FVAL 0x20 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IC_2_FVAL 0x21 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IC_3_FVAL 0x22 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IC_4_FVAL 0x23 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MOQA_0_FVAL 0x27 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MOQA_1_FVAL 0x28 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MOQA_2_FVAL 0x29 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MOQA_3_FVAL 0x2a +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_TMR_0_FVAL 0x2b +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_TMR_1_FVAL 0x2c +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_TMR_2_FVAL 0x2d +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_TMR_3_FVAL 0x2e +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_RD_WR_0_FVAL 0x33 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_RD_WR_1_FVAL 0x34 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_RD_WR_2_FVAL 0x35 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_RD_WR_3_FVAL 0x36 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_CSR_FVAL 0x3a +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_SDMA_0_FVAL 0x3c +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_SMDA_1_FVAL 0x3d +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_CSR_1_FVAL 0x3e +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_CSR_2_FVAL 0x3f +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MCS_5_FVAL 0x40 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IC_5_FVAL 0x41 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_CSR_3_FVAL 0x42 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_TLV_0_FVAL 0x43 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_8_FVAL 0x44 +#define HWIO_GSI_TEST_BUS_REG_ADDR (GSI_REG_BASE + 0x00001008) +#define HWIO_GSI_TEST_BUS_REG_PHYS (GSI_REG_BASE_PHYS + 0x00001008) +#define HWIO_GSI_TEST_BUS_REG_OFFS (GSI_REG_BASE_OFFS + 0x00001008) +#define HWIO_GSI_TEST_BUS_REG_RMSK 0xffffffff +#define HWIO_GSI_TEST_BUS_REG_ATTR 0x1 +#define HWIO_GSI_TEST_BUS_REG_IN in_dword_masked( \ + HWIO_GSI_TEST_BUS_REG_ADDR, \ + HWIO_GSI_TEST_BUS_REG_RMSK) +#define HWIO_GSI_TEST_BUS_REG_INM(m) in_dword_masked( \ + HWIO_GSI_TEST_BUS_REG_ADDR, \ + m) +#define HWIO_GSI_TEST_BUS_REG_GSI_TESTBUS_REG_BMSK 0xffffffff +#define HWIO_GSI_TEST_BUS_REG_GSI_TESTBUS_REG_SHFT 0x0 +#define HWIO_GSI_DEBUG_BUSY_REG_ADDR (GSI_REG_BASE + 0x00001010) +#define HWIO_GSI_DEBUG_BUSY_REG_PHYS (GSI_REG_BASE_PHYS + 0x00001010) +#define HWIO_GSI_DEBUG_BUSY_REG_OFFS (GSI_REG_BASE_OFFS + 0x00001010) +#define HWIO_GSI_DEBUG_EVENT_PENDING_ADDR (GSI_REG_BASE + 0x00001014) +#define HWIO_GSI_DEBUG_EVENT_PENDING_PHYS (GSI_REG_BASE_PHYS + 0x00001014) +#define HWIO_GSI_DEBUG_EVENT_PENDING_OFFS (GSI_REG_BASE_OFFS + 0x00001014) +#define HWIO_GSI_DEBUG_TIMER_PENDING_ADDR (GSI_REG_BASE + 0x00001018) +#define HWIO_GSI_DEBUG_TIMER_PENDING_PHYS (GSI_REG_BASE_PHYS + 0x00001018) +#define HWIO_GSI_DEBUG_TIMER_PENDING_OFFS (GSI_REG_BASE_OFFS + 0x00001018) +#define HWIO_GSI_DEBUG_RD_WR_PENDING_ADDR (GSI_REG_BASE + 0x0000101c) +#define HWIO_GSI_DEBUG_RD_WR_PENDING_PHYS (GSI_REG_BASE_PHYS + 0x0000101c) +#define HWIO_GSI_DEBUG_RD_WR_PENDING_OFFS (GSI_REG_BASE_OFFS + 0x0000101c) +#define HWIO_GSI_DEBUG_COUNTER_CFGn_ADDR(n) (GSI_REG_BASE + 0x00001200 + \ + 0x4 * (n)) +#define HWIO_GSI_DEBUG_COUNTER_CFGn_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x00001200 + 0x4 * (n)) +#define HWIO_GSI_DEBUG_COUNTER_CFGn_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x00001200 + 0x4 * (n)) +#define HWIO_GSI_DEBUG_COUNTERn_ADDR(n) (GSI_REG_BASE + 0x00001240 + 0x4 * \ + (n)) +#define HWIO_GSI_DEBUG_COUNTERn_PHYS(n) (GSI_REG_BASE_PHYS + 0x00001240 + \ + 0x4 * (n)) +#define HWIO_GSI_DEBUG_COUNTERn_OFFS(n) (GSI_REG_BASE_OFFS + 0x00001240 + \ + 0x4 * (n)) +#define HWIO_GSI_DEBUG_COUNTERn_RMSK 0xffff +#define HWIO_GSI_DEBUG_COUNTERn_MAXn 7 +#define HWIO_GSI_DEBUG_COUNTERn_ATTR 0x1 +#define HWIO_GSI_DEBUG_COUNTERn_INI(n) in_dword_masked( \ + HWIO_GSI_DEBUG_COUNTERn_ADDR(n), \ + HWIO_GSI_DEBUG_COUNTERn_RMSK) +#define HWIO_GSI_DEBUG_COUNTERn_INMI(n, mask) in_dword_masked( \ + HWIO_GSI_DEBUG_COUNTERn_ADDR(n), \ + mask) +#define HWIO_GSI_DEBUG_COUNTERn_COUNTER_VALUE_BMSK 0xffff +#define HWIO_GSI_DEBUG_COUNTERn_COUNTER_VALUE_SHFT 0x0 +#define HWIO_GSI_DEBUG_PC_FROM_SW_ADDR (GSI_REG_BASE + 0x00001040) +#define HWIO_GSI_DEBUG_PC_FROM_SW_PHYS (GSI_REG_BASE_PHYS + 0x00001040) +#define HWIO_GSI_DEBUG_PC_FROM_SW_OFFS (GSI_REG_BASE_OFFS + 0x00001040) +#define HWIO_GSI_DEBUG_SW_STALL_ADDR (GSI_REG_BASE + 0x00001044) +#define HWIO_GSI_DEBUG_SW_STALL_PHYS (GSI_REG_BASE_PHYS + 0x00001044) +#define HWIO_GSI_DEBUG_SW_STALL_OFFS (GSI_REG_BASE_OFFS + 0x00001044) +#define HWIO_GSI_DEBUG_PC_FOR_DEBUG_ADDR (GSI_REG_BASE + 0x00001048) +#define HWIO_GSI_DEBUG_PC_FOR_DEBUG_PHYS (GSI_REG_BASE_PHYS + 0x00001048) +#define HWIO_GSI_DEBUG_PC_FOR_DEBUG_OFFS (GSI_REG_BASE_OFFS + 0x00001048) +#define HWIO_GSI_DEBUG_QSB_LOG_SEL_ADDR (GSI_REG_BASE + 0x00001050) +#define HWIO_GSI_DEBUG_QSB_LOG_SEL_PHYS (GSI_REG_BASE_PHYS + 0x00001050) +#define HWIO_GSI_DEBUG_QSB_LOG_SEL_OFFS (GSI_REG_BASE_OFFS + 0x00001050) +#define HWIO_GSI_DEBUG_QSB_LOG_CLR_ADDR (GSI_REG_BASE + 0x00001058) +#define HWIO_GSI_DEBUG_QSB_LOG_CLR_PHYS (GSI_REG_BASE_PHYS + 0x00001058) +#define HWIO_GSI_DEBUG_QSB_LOG_CLR_OFFS (GSI_REG_BASE_OFFS + 0x00001058) +#define HWIO_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ADDR (GSI_REG_BASE + 0x00001060) +#define HWIO_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_PHYS (GSI_REG_BASE_PHYS + \ + 0x00001060) +#define HWIO_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_OFFS (GSI_REG_BASE_OFFS + \ + 0x00001060) +#define HWIO_GSI_DEBUG_QSB_LOG_0_ADDR (GSI_REG_BASE + 0x00001064) +#define HWIO_GSI_DEBUG_QSB_LOG_0_PHYS (GSI_REG_BASE_PHYS + 0x00001064) +#define HWIO_GSI_DEBUG_QSB_LOG_0_OFFS (GSI_REG_BASE_OFFS + 0x00001064) +#define HWIO_GSI_DEBUG_QSB_LOG_1_ADDR (GSI_REG_BASE + 0x00001068) +#define HWIO_GSI_DEBUG_QSB_LOG_1_PHYS (GSI_REG_BASE_PHYS + 0x00001068) +#define HWIO_GSI_DEBUG_QSB_LOG_1_OFFS (GSI_REG_BASE_OFFS + 0x00001068) +#define HWIO_GSI_DEBUG_QSB_LOG_2_ADDR (GSI_REG_BASE + 0x0000106c) +#define HWIO_GSI_DEBUG_QSB_LOG_2_PHYS (GSI_REG_BASE_PHYS + 0x0000106c) +#define HWIO_GSI_DEBUG_QSB_LOG_2_OFFS (GSI_REG_BASE_OFFS + 0x0000106c) +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_ADDR(n) (GSI_REG_BASE + \ + 0x00001070 + 0x4 * \ + (n)) +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x00001070 + 0x4 * \ + (n)) +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x00001070 + 0x4 * \ + (n)) +#define HWIO_GSI_DEBUG_SW_RF_n_WRITE_ADDR(n) (GSI_REG_BASE + 0x00001080 + \ + 0x4 * (n)) +#define HWIO_GSI_DEBUG_SW_RF_n_WRITE_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x00001080 + 0x4 * (n)) +#define HWIO_GSI_DEBUG_SW_RF_n_WRITE_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x00001080 + 0x4 * (n)) +#define HWIO_GSI_DEBUG_SW_RF_n_READ_ADDR(n) (GSI_REG_BASE + 0x00001100 + \ + 0x4 * (n)) +#define HWIO_GSI_DEBUG_SW_RF_n_READ_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x00001100 + 0x4 * (n)) +#define HWIO_GSI_DEBUG_SW_RF_n_READ_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x00001100 + 0x4 * (n)) +#define HWIO_GSI_DEBUG_SW_RF_n_READ_RMSK 0xffffffff +#define HWIO_GSI_DEBUG_SW_RF_n_READ_MAXn 31 +#define HWIO_GSI_DEBUG_SW_RF_n_READ_ATTR 0x1 +#define HWIO_GSI_DEBUG_SW_RF_n_READ_INI(n) in_dword_masked( \ + HWIO_GSI_DEBUG_SW_RF_n_READ_ADDR(n), \ + HWIO_GSI_DEBUG_SW_RF_n_READ_RMSK) +#define HWIO_GSI_DEBUG_SW_RF_n_READ_INMI(n, mask) in_dword_masked( \ + HWIO_GSI_DEBUG_SW_RF_n_READ_ADDR(n), \ + mask) +#define HWIO_GSI_DEBUG_SW_RF_n_READ_RF_REG_BMSK 0xffffffff +#define HWIO_GSI_DEBUG_SW_RF_n_READ_RF_REG_SHFT 0x0 +#define HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_ADDR(n, k) (GSI_REG_BASE + \ + 0x00001400 + 0x80 * \ + (n) + 0x4 * (k)) +#define HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x00001400 + 0x80 * \ + (n) + 0x4 * (k)) +#define HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x00001400 + 0x80 * \ + (n) + 0x4 * (k)) +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_ADDR(n, k) (GSI_REG_BASE + \ + 0x00001600 + 0x80 * \ + (n) + 0x4 * (k)) +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x00001600 + 0x80 * \ + (n) + 0x4 * (k)) +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x00001600 + 0x80 * \ + (n) + 0x4 * (k)) +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_RMSK 0x3f +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_MAXn 3 +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_MAXk 19 +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_ATTR 0x1 +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_INI2(n, k) in_dword_masked( \ + HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_ADDR(n, k), \ + HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_RMSK) +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_ADDR(n, \ + k), \ + mask) +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_VALID_BMSK 0x20 +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_VALID_SHFT 0x5 +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_PHY_EV_CH_BMSK 0x1f +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_PHY_EV_CH_SHFT 0x0 +#define HWIO_GSI_DEBUG_SDMA_TRANS_DB_n_ADDR(n) (GSI_REG_BASE + \ + 0x00001800 + 0x4 * (n)) +#define HWIO_GSI_DEBUG_SDMA_TRANS_DB_n_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x00001800 + 0x4 * (n)) +#define HWIO_GSI_DEBUG_SDMA_TRANS_DB_n_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x00001800 + 0x4 * (n)) +#define HWIO_GSI_UC_SRC_IRQ_ADDR (GSI_REG_BASE + 0x00000500) +#define HWIO_GSI_UC_SRC_IRQ_PHYS (GSI_REG_BASE_PHYS + 0x00000500) +#define HWIO_GSI_UC_SRC_IRQ_OFFS (GSI_REG_BASE_OFFS + 0x00000500) +#define HWIO_GSI_UC_SRC_IRQ_MSK_ADDR (GSI_REG_BASE + 0x00000504) +#define HWIO_GSI_UC_SRC_IRQ_MSK_PHYS (GSI_REG_BASE_PHYS + 0x00000504) +#define HWIO_GSI_UC_SRC_IRQ_MSK_OFFS (GSI_REG_BASE_OFFS + 0x00000504) +#define HWIO_GSI_UC_SRC_IRQ_CLR_ADDR (GSI_REG_BASE + 0x00000508) +#define HWIO_GSI_UC_SRC_IRQ_CLR_PHYS (GSI_REG_BASE_PHYS + 0x00000508) +#define HWIO_GSI_UC_SRC_IRQ_CLR_OFFS (GSI_REG_BASE_OFFS + 0x00000508) +#define HWIO_GSI_ACC_ARGS_n_ADDR(n) (GSI_REG_BASE + 0x0000050c + 0x4 * (n)) +#define HWIO_GSI_ACC_ARGS_n_PHYS(n) (GSI_REG_BASE_PHYS + 0x0000050c + \ + 0x4 * (n)) +#define HWIO_GSI_ACC_ARGS_n_OFFS(n) (GSI_REG_BASE_OFFS + 0x0000050c + \ + 0x4 * (n)) +#define HWIO_GSI_ACC_ROUTINE_ADDR (GSI_REG_BASE + 0x00000524) +#define HWIO_GSI_ACC_ROUTINE_PHYS (GSI_REG_BASE_PHYS + 0x00000524) +#define HWIO_GSI_ACC_ROUTINE_OFFS (GSI_REG_BASE_OFFS + 0x00000524) +#define HWIO_GSI_ACC_GO_ADDR (GSI_REG_BASE + 0x00000528) +#define HWIO_GSI_ACC_GO_PHYS (GSI_REG_BASE_PHYS + 0x00000528) +#define HWIO_GSI_ACC_GO_OFFS (GSI_REG_BASE_OFFS + 0x00000528) +#define HWIO_GSI_ACC_2_UC_MCS_STTS_ADDR (GSI_REG_BASE + 0x0000052c) +#define HWIO_GSI_ACC_2_UC_MCS_STTS_PHYS (GSI_REG_BASE_PHYS + 0x0000052c) +#define HWIO_GSI_ACC_2_UC_MCS_STTS_OFFS (GSI_REG_BASE_OFFS + 0x0000052c) +#define HWIO_GSI_ACC_2_UC_MCS_RET_VAL_LSB_ADDR (GSI_REG_BASE + 0x00000530) +#define HWIO_GSI_ACC_2_UC_MCS_RET_VAL_LSB_PHYS (GSI_REG_BASE_PHYS + \ + 0x00000530) +#define HWIO_GSI_ACC_2_UC_MCS_RET_VAL_LSB_OFFS (GSI_REG_BASE_OFFS + \ + 0x00000530) +#define HWIO_GSI_ACC_2_UC_MCS_RET_VAL_MSB_ADDR (GSI_REG_BASE + 0x00000534) +#define HWIO_GSI_ACC_2_UC_MCS_RET_VAL_MSB_PHYS (GSI_REG_BASE_PHYS + \ + 0x00000534) +#define HWIO_GSI_ACC_2_UC_MCS_RET_VAL_MSB_OFFS (GSI_REG_BASE_OFFS + \ + 0x00000534) +#define HWIO_GSI_IC_2_UC_MCS_VLD_ADDR (GSI_REG_BASE + 0x00000538) +#define HWIO_GSI_IC_2_UC_MCS_VLD_PHYS (GSI_REG_BASE_PHYS + 0x00000538) +#define HWIO_GSI_IC_2_UC_MCS_VLD_OFFS (GSI_REG_BASE_OFFS + 0x00000538) +#define HWIO_GSI_IC_2_UC_MCS_PC_ADDR (GSI_REG_BASE + 0x0000053c) +#define HWIO_GSI_IC_2_UC_MCS_PC_PHYS (GSI_REG_BASE_PHYS + 0x0000053c) +#define HWIO_GSI_IC_2_UC_MCS_PC_OFFS (GSI_REG_BASE_OFFS + 0x0000053c) +#define HWIO_GSI_IC_2_UC_MCS_ARGS_n_ADDR(n) (GSI_REG_BASE + 0x00000540 + \ + 0x4 * (n)) +#define HWIO_GSI_IC_2_UC_MCS_ARGS_n_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x00000540 + 0x4 * (n)) +#define HWIO_GSI_IC_2_UC_MCS_ARGS_n_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x00000540 + 0x4 * (n)) +#define HWIO_GSI_UC_TLV_IN_VLD_ADDR (GSI_REG_BASE + 0x00000558) +#define HWIO_GSI_UC_TLV_IN_VLD_PHYS (GSI_REG_BASE_PHYS + 0x00000558) +#define HWIO_GSI_UC_TLV_IN_VLD_OFFS (GSI_REG_BASE_OFFS + 0x00000558) +#define HWIO_GSI_UC_TLV_IN_ROUTINE_ADDR (GSI_REG_BASE + 0x0000055c) +#define HWIO_GSI_UC_TLV_IN_ROUTINE_PHYS (GSI_REG_BASE_PHYS + 0x0000055c) +#define HWIO_GSI_UC_TLV_IN_ROUTINE_OFFS (GSI_REG_BASE_OFFS + 0x0000055c) +#define HWIO_GSI_UC_TLV_IN_ARGS_n_ADDR(n) (GSI_REG_BASE + 0x00000560 + \ + 0x4 * (n)) +#define HWIO_GSI_UC_TLV_IN_ARGS_n_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x00000560 + 0x4 * (n)) +#define HWIO_GSI_UC_TLV_IN_ARGS_n_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x00000560 + 0x4 * (n)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_ADDR(n, k) (GSI_REG_BASE + 0x0000f000 + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0000f000 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0000f000 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_RMSK 0xfff7ffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_MAXk 22 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_CNTXT_0_ADDR(n, k), \ + HWIO_EE_n_GSI_CH_k_CNTXT_0_RMSK) +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_CNTXT_0_ADDR(n, k), \ + mask) +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_GSI_CH_k_CNTXT_0_ADDR(n, k), \ + val) +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_GSI_CH_k_CNTXT_0_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_GSI_CH_k_CNTXT_0_INI2(n, k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_ELEMENT_SIZE_BMSK 0xff000000 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_ELEMENT_SIZE_SHFT 0x18 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_BMSK 0xf00000 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_SHFT 0x14 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_NOT_ALLOCATED_FVAL 0x0 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_ALLOCATED_FVAL 0x1 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_STARTED_FVAL 0x2 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_STOPPED_FVAL 0x3 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_STOP_IN_PROC_FVAL 0x4 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_ERROR_FVAL 0xf +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_ERINDEX_BMSK 0x7c000 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_ERINDEX_SHFT 0xe +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_MSB_BMSK 0x2000 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_MSB_SHFT 0xd +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHID_BMSK 0x1f00 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHID_SHFT 0x8 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_EE_BMSK 0xf0 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_EE_SHFT 0x4 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_DIR_BMSK 0x8 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_DIR_SHFT 0x3 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_DIR_INBOUND_FVAL 0x0 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_DIR_OUTBOUND_FVAL 0x1 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_BMSK 0x7 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_SHFT 0x0 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_MHI_FVAL 0x0 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_XHCI_FVAL 0x1 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_GPI_FVAL 0x2 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_XDCI_FVAL 0x3 +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_ADDR(n, k) (GSI_REG_BASE + 0x0000f004 + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0000f004 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0000f004 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_RMSK 0xffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_MAXk 22 +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_CNTXT_1_ADDR(n, k), \ + HWIO_EE_n_GSI_CH_k_CNTXT_1_RMSK) +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_CNTXT_1_ADDR(n, k), \ + mask) +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_GSI_CH_k_CNTXT_1_ADDR(n, k), \ + val) +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_GSI_CH_k_CNTXT_1_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_GSI_CH_k_CNTXT_1_INI2(n, k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_R_LENGTH_BMSK 0xffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_R_LENGTH_SHFT 0x0 +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_ADDR(n, k) (GSI_REG_BASE + 0x0000f008 + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0000f008 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0000f008 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_MAXk 22 +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_CNTXT_2_ADDR(n, k), \ + HWIO_EE_n_GSI_CH_k_CNTXT_2_RMSK) +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_CNTXT_2_ADDR(n, k), \ + mask) +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_GSI_CH_k_CNTXT_2_ADDR(n, k), \ + val) +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_GSI_CH_k_CNTXT_2_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_GSI_CH_k_CNTXT_2_INI2(n, k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_R_BASE_ADDR_LSBS_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_R_BASE_ADDR_LSBS_SHFT 0x0 +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_ADDR(n, k) (GSI_REG_BASE + 0x0000f00c + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0000f00c + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0000f00c + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_MAXk 22 +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_CNTXT_3_ADDR(n, k), \ + HWIO_EE_n_GSI_CH_k_CNTXT_3_RMSK) +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_CNTXT_3_ADDR(n, k), \ + mask) +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_GSI_CH_k_CNTXT_3_ADDR(n, k), \ + val) +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_GSI_CH_k_CNTXT_3_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_GSI_CH_k_CNTXT_3_INI2(n, k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_R_BASE_ADDR_MSBS_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_R_BASE_ADDR_MSBS_SHFT 0x0 +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_ADDR(n, k) (GSI_REG_BASE + 0x0000f010 + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0000f010 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0000f010 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_MAXk 22 +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_CNTXT_4_ADDR(n, k), \ + HWIO_EE_n_GSI_CH_k_CNTXT_4_RMSK) +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_CNTXT_4_ADDR(n, k), \ + mask) +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_GSI_CH_k_CNTXT_4_ADDR(n, k), \ + val) +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_GSI_CH_k_CNTXT_4_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_GSI_CH_k_CNTXT_4_INI2(n, k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_READ_PTR_LSB_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_READ_PTR_LSB_SHFT 0x0 +#define HWIO_EE_n_GSI_CH_k_CNTXT_5_ADDR(n, k) (GSI_REG_BASE + 0x0000f014 + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_5_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0000f014 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_5_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0000f014 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_5_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_5_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_CNTXT_5_MAXk 22 +#define HWIO_EE_n_GSI_CH_k_CNTXT_5_ATTR 0x1 +#define HWIO_EE_n_GSI_CH_k_CNTXT_5_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_CNTXT_5_ADDR(n, k), \ + HWIO_EE_n_GSI_CH_k_CNTXT_5_RMSK) +#define HWIO_EE_n_GSI_CH_k_CNTXT_5_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_CNTXT_5_ADDR(n, k), \ + mask) +#define HWIO_EE_n_GSI_CH_k_CNTXT_5_READ_PTR_MSB_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_5_READ_PTR_MSB_SHFT 0x0 +#define HWIO_EE_n_GSI_CH_k_CNTXT_6_ADDR(n, k) (GSI_REG_BASE + 0x0000f018 + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_6_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0000f018 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_6_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0000f018 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_6_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_6_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_CNTXT_6_MAXk 22 +#define HWIO_EE_n_GSI_CH_k_CNTXT_6_ATTR 0x1 +#define HWIO_EE_n_GSI_CH_k_CNTXT_6_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_CNTXT_6_ADDR(n, k), \ + HWIO_EE_n_GSI_CH_k_CNTXT_6_RMSK) +#define HWIO_EE_n_GSI_CH_k_CNTXT_6_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_CNTXT_6_ADDR(n, k), \ + mask) +#define HWIO_EE_n_GSI_CH_k_CNTXT_6_WRITE_PTR_LSB_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_6_WRITE_PTR_LSB_SHFT 0x0 +#define HWIO_EE_n_GSI_CH_k_CNTXT_7_ADDR(n, k) (GSI_REG_BASE + 0x0000f01c + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_7_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0000f01c + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_7_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0000f01c + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_7_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_7_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_CNTXT_7_MAXk 22 +#define HWIO_EE_n_GSI_CH_k_CNTXT_7_ATTR 0x1 +#define HWIO_EE_n_GSI_CH_k_CNTXT_7_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_CNTXT_7_ADDR(n, k), \ + HWIO_EE_n_GSI_CH_k_CNTXT_7_RMSK) +#define HWIO_EE_n_GSI_CH_k_CNTXT_7_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_CNTXT_7_ADDR(n, k), \ + mask) +#define HWIO_EE_n_GSI_CH_k_CNTXT_7_WRITE_PTR_MSB_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_7_WRITE_PTR_MSB_SHFT 0x0 +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_ADDR(n, k) (GSI_REG_BASE + \ + 0x0000f054 + \ + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_PHYS(n, \ + k) (GSI_REG_BASE_PHYS + \ + 0x0000f054 + \ + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_OFFS(n, \ + k) (GSI_REG_BASE_OFFS + \ + 0x0000f054 + \ + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_RMSK 0xffff +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_MAXk 22 +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_ADDR(n, k), \ + HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_RMSK) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_ADDR(n, \ + k), \ + mask) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_ADDR(n, k), \ + val) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns(HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_ADDR( \ + n, \ + k), mask, val, \ + HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_INI2(n, k)) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_READ_PTR_BMSK 0xffff +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_READ_PTR_SHFT 0x0 +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_ADDR(n, k) (GSI_REG_BASE + \ + 0x0000f058 + \ + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_PHYS(n, \ + k) (GSI_REG_BASE_PHYS + \ + 0x0000f058 + \ + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_OFFS(n, \ + k) (GSI_REG_BASE_OFFS + \ + 0x0000f058 + \ + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_RMSK 0xffff +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_MAXk 22 +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_ADDR(n, k), \ + HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_RMSK) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_ADDR(n, \ + k), \ + mask) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_ADDR(n, k), \ + val) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns(HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_ADDR( \ + n, \ + k), mask, val, \ + HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_INI2(n, \ + k)) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_RE_INTR_DB_BMSK 0xffff +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_RE_INTR_DB_SHFT 0x0 +#define HWIO_EE_n_GSI_CH_k_QOS_ADDR(n, k) (GSI_REG_BASE + 0x0000f05c + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_QOS_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0000f05c + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_QOS_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0000f05c + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_QOS_RMSK 0xff3f0f +#define HWIO_EE_n_GSI_CH_k_QOS_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_QOS_MAXk 22 +#define HWIO_EE_n_GSI_CH_k_QOS_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_QOS_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_QOS_ADDR(n, k), \ + HWIO_EE_n_GSI_CH_k_QOS_RMSK) +#define HWIO_EE_n_GSI_CH_k_QOS_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_QOS_ADDR(n, k), \ + mask) +#define HWIO_EE_n_GSI_CH_k_QOS_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_GSI_CH_k_QOS_ADDR(n, k), \ + val) +#define HWIO_EE_n_GSI_CH_k_QOS_OUTMI2(n, k, mask, val) out_dword_masked_ns( \ + HWIO_EE_n_GSI_CH_k_QOS_ADDR(n, k), \ + mask, \ + val, \ + HWIO_EE_n_GSI_CH_k_QOS_INI2(n, k)) +#define HWIO_EE_n_GSI_CH_k_QOS_EMPTY_LVL_THRSHOLD_BMSK 0xff0000 +#define HWIO_EE_n_GSI_CH_k_QOS_EMPTY_LVL_THRSHOLD_SHFT 0x10 +#define HWIO_EE_n_GSI_CH_k_QOS_PREFETCH_MODE_BMSK 0x3c00 +#define HWIO_EE_n_GSI_CH_k_QOS_PREFETCH_MODE_SHFT 0xa +#define HWIO_EE_n_GSI_CH_k_QOS_PREFETCH_MODE_USE_PREFETCH_BUFS_FVAL 0x0 +#define HWIO_EE_n_GSI_CH_k_QOS_PREFETCH_MODE_ESCAPE_BUF_ONLY_FVAL 0x1 +#define HWIO_EE_n_GSI_CH_k_QOS_PREFETCH_MODE_SMART_PRE_FETCH_FVAL 0x2 +#define HWIO_EE_n_GSI_CH_k_QOS_PREFETCH_MODE_FREE_PRE_FETCH_FVAL 0x3 +#define HWIO_EE_n_GSI_CH_k_QOS_USE_DB_ENG_BMSK 0x200 +#define HWIO_EE_n_GSI_CH_k_QOS_USE_DB_ENG_SHFT 0x9 +#define HWIO_EE_n_GSI_CH_k_QOS_MAX_PREFETCH_BMSK 0x100 +#define HWIO_EE_n_GSI_CH_k_QOS_MAX_PREFETCH_SHFT 0x8 +#define HWIO_EE_n_GSI_CH_k_QOS_MAX_PREFETCH_ONE_PREFETCH_SEG_FVAL 0x0 +#define HWIO_EE_n_GSI_CH_k_QOS_MAX_PREFETCH_TWO_PREFETCH_SEG_FVAL 0x1 +#define HWIO_EE_n_GSI_CH_k_QOS_WRR_WEIGHT_BMSK 0xf +#define HWIO_EE_n_GSI_CH_k_QOS_WRR_WEIGHT_SHFT 0x0 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_ADDR(n, k) (GSI_REG_BASE + \ + 0x0000f060 + 0x4000 * \ + (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0000f060 + 0x4000 * \ + (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0000f060 + 0x4000 * \ + (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_MAXk 22 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_SCRATCH_0_ADDR(n, k), \ + HWIO_EE_n_GSI_CH_k_SCRATCH_0_RMSK) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_SCRATCH_0_ADDR(n, k), \ + mask) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_GSI_CH_k_SCRATCH_0_ADDR(n, k), \ + val) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_GSI_CH_k_SCRATCH_0_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_GSI_CH_k_SCRATCH_0_INI2(n, k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_SCRATCH_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_SCRATCH_SHFT 0x0 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_ADDR(n, k) (GSI_REG_BASE + \ + 0x0000f064 + 0x4000 * \ + (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0000f064 + 0x4000 * \ + (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0000f064 + 0x4000 * \ + (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_MAXk 22 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_SCRATCH_1_ADDR(n, k), \ + HWIO_EE_n_GSI_CH_k_SCRATCH_1_RMSK) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_SCRATCH_1_ADDR(n, k), \ + mask) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_GSI_CH_k_SCRATCH_1_ADDR(n, k), \ + val) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_GSI_CH_k_SCRATCH_1_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_GSI_CH_k_SCRATCH_1_INI2(n, k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_SCRATCH_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_SCRATCH_SHFT 0x0 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_ADDR(n, k) (GSI_REG_BASE + \ + 0x0000f068 + 0x4000 * \ + (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0000f068 + 0x4000 * \ + (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0000f068 + 0x4000 * \ + (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_MAXk 22 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_SCRATCH_2_ADDR(n, k), \ + HWIO_EE_n_GSI_CH_k_SCRATCH_2_RMSK) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_SCRATCH_2_ADDR(n, k), \ + mask) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_GSI_CH_k_SCRATCH_2_ADDR(n, k), \ + val) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_GSI_CH_k_SCRATCH_2_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_GSI_CH_k_SCRATCH_2_INI2(n, k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_SCRATCH_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_SCRATCH_SHFT 0x0 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_ADDR(n, k) (GSI_REG_BASE + \ + 0x0000f06c + 0x4000 * \ + (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0000f06c + 0x4000 * \ + (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0000f06c + 0x4000 * \ + (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_MAXk 22 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_SCRATCH_3_ADDR(n, k), \ + HWIO_EE_n_GSI_CH_k_SCRATCH_3_RMSK) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_SCRATCH_3_ADDR(n, k), \ + mask) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_GSI_CH_k_SCRATCH_3_ADDR(n, k), \ + val) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_GSI_CH_k_SCRATCH_3_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_GSI_CH_k_SCRATCH_3_INI2(n, k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_SCRATCH_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_SCRATCH_SHFT 0x0 +#define HWIO_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_ADDR(n, k) (GSI_REG_BASE + \ + 0x0000f070 + \ + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_PHYS(n, \ + k) (GSI_REG_BASE_PHYS + \ + 0x0000f070 + 0x4000 * \ + (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_OFFS(n, \ + k) (GSI_REG_BASE_OFFS + \ + 0x0000f070 + 0x4000 * \ + (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_0_ADDR(n, k) (GSI_REG_BASE + 0x00010000 + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_0_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x00010000 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_0_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x00010000 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_0_RMSK 0xfff1ffff +#define HWIO_EE_n_EV_CH_k_CNTXT_0_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_MAXk 19 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_0_ADDR(n, k), \ + HWIO_EE_n_EV_CH_k_CNTXT_0_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_0_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_0_ADDR(n, k), \ + mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_0_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_EV_CH_k_CNTXT_0_ADDR(n, k), \ + val) +#define HWIO_EE_n_EV_CH_k_CNTXT_0_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_EV_CH_k_CNTXT_0_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_EV_CH_k_CNTXT_0_INI2(n, k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_0_ELEMENT_SIZE_BMSK 0xff000000 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_ELEMENT_SIZE_SHFT 0x18 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_CHSTATE_BMSK 0xf00000 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_CHSTATE_SHFT 0x14 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_CHSTATE_NOT_ALLOCATED_FVAL 0x0 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_CHSTATE_ALLOCATED_FVAL 0x1 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_INTYPE_BMSK 0x10000 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_INTYPE_SHFT 0x10 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_INTYPE_MSI_FVAL 0x0 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_INTYPE_IRQ_FVAL 0x1 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_EVCHID_BMSK 0xff00 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_EVCHID_SHFT 0x8 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_EE_BMSK 0xf0 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_EE_SHFT 0x4 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_CHTYPE_BMSK 0xf +#define HWIO_EE_n_EV_CH_k_CNTXT_0_CHTYPE_SHFT 0x0 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_CHTYPE_MHI_EV_FVAL 0x0 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_CHTYPE_XHCI_EV_FVAL 0x1 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_CHTYPE_GPI_EV_FVAL 0x2 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_CHTYPE_XDCI_FVAL 0x3 +#define HWIO_EE_n_EV_CH_k_CNTXT_1_ADDR(n, k) (GSI_REG_BASE + 0x00010004 + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_1_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x00010004 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_1_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x00010004 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_1_RMSK 0xffff +#define HWIO_EE_n_EV_CH_k_CNTXT_1_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_1_MAXk 19 +#define HWIO_EE_n_EV_CH_k_CNTXT_1_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_CNTXT_1_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_1_ADDR(n, k), \ + HWIO_EE_n_EV_CH_k_CNTXT_1_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_1_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_1_ADDR(n, k), \ + mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_1_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_EV_CH_k_CNTXT_1_ADDR(n, k), \ + val) +#define HWIO_EE_n_EV_CH_k_CNTXT_1_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_EV_CH_k_CNTXT_1_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_EV_CH_k_CNTXT_1_INI2(n, k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_1_R_LENGTH_BMSK 0xffff +#define HWIO_EE_n_EV_CH_k_CNTXT_1_R_LENGTH_SHFT 0x0 +#define HWIO_EE_n_EV_CH_k_CNTXT_2_ADDR(n, k) (GSI_REG_BASE + 0x00010008 + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_2_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x00010008 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_2_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x00010008 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_2_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_2_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_2_MAXk 19 +#define HWIO_EE_n_EV_CH_k_CNTXT_2_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_CNTXT_2_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_2_ADDR(n, k), \ + HWIO_EE_n_EV_CH_k_CNTXT_2_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_2_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_2_ADDR(n, k), \ + mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_2_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_EV_CH_k_CNTXT_2_ADDR(n, k), \ + val) +#define HWIO_EE_n_EV_CH_k_CNTXT_2_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_EV_CH_k_CNTXT_2_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_EV_CH_k_CNTXT_2_INI2(n, k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_2_R_BASE_ADDR_LSBS_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_2_R_BASE_ADDR_LSBS_SHFT 0x0 +#define HWIO_EE_n_EV_CH_k_CNTXT_3_ADDR(n, k) (GSI_REG_BASE + 0x0001000c + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_3_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001000c + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_3_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001000c + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_3_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_3_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_3_MAXk 19 +#define HWIO_EE_n_EV_CH_k_CNTXT_3_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_CNTXT_3_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_3_ADDR(n, k), \ + HWIO_EE_n_EV_CH_k_CNTXT_3_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_3_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_3_ADDR(n, k), \ + mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_3_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_EV_CH_k_CNTXT_3_ADDR(n, k), \ + val) +#define HWIO_EE_n_EV_CH_k_CNTXT_3_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_EV_CH_k_CNTXT_3_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_EV_CH_k_CNTXT_3_INI2(n, k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_3_R_BASE_ADDR_MSBS_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_3_R_BASE_ADDR_MSBS_SHFT 0x0 +#define HWIO_EE_n_EV_CH_k_CNTXT_4_ADDR(n, k) (GSI_REG_BASE + 0x00010010 + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_4_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x00010010 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_4_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x00010010 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_4_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_4_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_4_MAXk 19 +#define HWIO_EE_n_EV_CH_k_CNTXT_4_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_CNTXT_4_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_4_ADDR(n, k), \ + HWIO_EE_n_EV_CH_k_CNTXT_4_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_4_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_4_ADDR(n, k), \ + mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_4_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_EV_CH_k_CNTXT_4_ADDR(n, k), \ + val) +#define HWIO_EE_n_EV_CH_k_CNTXT_4_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_EV_CH_k_CNTXT_4_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_EV_CH_k_CNTXT_4_INI2(n, k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_4_READ_PTR_LSB_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_4_READ_PTR_LSB_SHFT 0x0 +#define HWIO_EE_n_EV_CH_k_CNTXT_5_ADDR(n, k) (GSI_REG_BASE + 0x00010014 + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_5_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x00010014 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_5_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x00010014 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_5_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_5_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_5_MAXk 19 +#define HWIO_EE_n_EV_CH_k_CNTXT_5_ATTR 0x1 +#define HWIO_EE_n_EV_CH_k_CNTXT_5_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_5_ADDR(n, k), \ + HWIO_EE_n_EV_CH_k_CNTXT_5_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_5_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_5_ADDR(n, k), \ + mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_5_READ_PTR_MSB_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_5_READ_PTR_MSB_SHFT 0x0 +#define HWIO_EE_n_EV_CH_k_CNTXT_6_ADDR(n, k) (GSI_REG_BASE + 0x00010018 + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_6_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x00010018 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_6_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x00010018 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_6_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_6_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_6_MAXk 19 +#define HWIO_EE_n_EV_CH_k_CNTXT_6_ATTR 0x1 +#define HWIO_EE_n_EV_CH_k_CNTXT_6_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_6_ADDR(n, k), \ + HWIO_EE_n_EV_CH_k_CNTXT_6_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_6_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_6_ADDR(n, k), \ + mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_6_WRITE_PTR_LSB_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_6_WRITE_PTR_LSB_SHFT 0x0 +#define HWIO_EE_n_EV_CH_k_CNTXT_7_ADDR(n, k) (GSI_REG_BASE + 0x0001001c + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_7_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001001c + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_7_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001001c + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_7_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_7_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_7_MAXk 19 +#define HWIO_EE_n_EV_CH_k_CNTXT_7_ATTR 0x1 +#define HWIO_EE_n_EV_CH_k_CNTXT_7_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_7_ADDR(n, k), \ + HWIO_EE_n_EV_CH_k_CNTXT_7_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_7_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_7_ADDR(n, k), \ + mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_7_WRITE_PTR_MSB_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_7_WRITE_PTR_MSB_SHFT 0x0 +#define HWIO_EE_n_EV_CH_k_CNTXT_8_ADDR(n, k) (GSI_REG_BASE + 0x00010020 + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_8_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x00010020 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_8_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x00010020 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_8_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_8_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_8_MAXk 19 +#define HWIO_EE_n_EV_CH_k_CNTXT_8_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_CNTXT_8_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_8_ADDR(n, k), \ + HWIO_EE_n_EV_CH_k_CNTXT_8_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_8_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_8_ADDR(n, k), \ + mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_8_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_EV_CH_k_CNTXT_8_ADDR(n, k), \ + val) +#define HWIO_EE_n_EV_CH_k_CNTXT_8_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_EV_CH_k_CNTXT_8_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_EV_CH_k_CNTXT_8_INI2(n, k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_8_INT_MOD_CNT_BMSK 0xff000000 +#define HWIO_EE_n_EV_CH_k_CNTXT_8_INT_MOD_CNT_SHFT 0x18 +#define HWIO_EE_n_EV_CH_k_CNTXT_8_INT_MODC_BMSK 0xff0000 +#define HWIO_EE_n_EV_CH_k_CNTXT_8_INT_MODC_SHFT 0x10 +#define HWIO_EE_n_EV_CH_k_CNTXT_8_INT_MODT_BMSK 0xffff +#define HWIO_EE_n_EV_CH_k_CNTXT_8_INT_MODT_SHFT 0x0 +#define HWIO_EE_n_EV_CH_k_CNTXT_9_ADDR(n, k) (GSI_REG_BASE + 0x00010024 + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_9_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x00010024 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_9_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x00010024 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_9_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_9_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_9_MAXk 19 +#define HWIO_EE_n_EV_CH_k_CNTXT_9_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_CNTXT_9_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_9_ADDR(n, k), \ + HWIO_EE_n_EV_CH_k_CNTXT_9_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_9_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_9_ADDR(n, k), \ + mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_9_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_EV_CH_k_CNTXT_9_ADDR(n, k), \ + val) +#define HWIO_EE_n_EV_CH_k_CNTXT_9_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_EV_CH_k_CNTXT_9_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_EV_CH_k_CNTXT_9_INI2(n, k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_9_INTVEC_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_9_INTVEC_SHFT 0x0 +#define HWIO_EE_n_EV_CH_k_CNTXT_10_ADDR(n, k) (GSI_REG_BASE + 0x00010028 + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_10_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x00010028 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_10_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x00010028 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_10_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_10_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_10_MAXk 19 +#define HWIO_EE_n_EV_CH_k_CNTXT_10_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_CNTXT_10_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_10_ADDR(n, k), \ + HWIO_EE_n_EV_CH_k_CNTXT_10_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_10_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_10_ADDR(n, k), \ + mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_10_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_EV_CH_k_CNTXT_10_ADDR(n, k), \ + val) +#define HWIO_EE_n_EV_CH_k_CNTXT_10_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_EV_CH_k_CNTXT_10_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_EV_CH_k_CNTXT_10_INI2(n, k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_10_MSI_ADDR_LSB_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_10_MSI_ADDR_LSB_SHFT 0x0 +#define HWIO_EE_n_EV_CH_k_CNTXT_11_ADDR(n, k) (GSI_REG_BASE + 0x0001002c + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_11_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001002c + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_11_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001002c + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_11_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_11_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_11_MAXk 19 +#define HWIO_EE_n_EV_CH_k_CNTXT_11_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_CNTXT_11_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_11_ADDR(n, k), \ + HWIO_EE_n_EV_CH_k_CNTXT_11_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_11_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_11_ADDR(n, k), \ + mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_11_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_EV_CH_k_CNTXT_11_ADDR(n, k), \ + val) +#define HWIO_EE_n_EV_CH_k_CNTXT_11_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_EV_CH_k_CNTXT_11_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_EV_CH_k_CNTXT_11_INI2(n, k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_11_MSI_ADDR_MSB_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_11_MSI_ADDR_MSB_SHFT 0x0 +#define HWIO_EE_n_EV_CH_k_CNTXT_12_ADDR(n, k) (GSI_REG_BASE + 0x00010030 + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_12_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x00010030 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_12_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x00010030 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_12_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_12_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_12_MAXk 19 +#define HWIO_EE_n_EV_CH_k_CNTXT_12_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_CNTXT_12_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_12_ADDR(n, k), \ + HWIO_EE_n_EV_CH_k_CNTXT_12_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_12_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_12_ADDR(n, k), \ + mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_12_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_EV_CH_k_CNTXT_12_ADDR(n, k), \ + val) +#define HWIO_EE_n_EV_CH_k_CNTXT_12_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_EV_CH_k_CNTXT_12_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_EV_CH_k_CNTXT_12_INI2(n, k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_12_RP_UPDATE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_12_RP_UPDATE_ADDR_LSB_SHFT 0x0 +#define HWIO_EE_n_EV_CH_k_CNTXT_13_ADDR(n, k) (GSI_REG_BASE + 0x00010034 + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_13_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x00010034 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_13_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x00010034 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_13_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_13_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_13_MAXk 19 +#define HWIO_EE_n_EV_CH_k_CNTXT_13_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_CNTXT_13_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_13_ADDR(n, k), \ + HWIO_EE_n_EV_CH_k_CNTXT_13_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_13_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_13_ADDR(n, k), \ + mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_13_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_EV_CH_k_CNTXT_13_ADDR(n, k), \ + val) +#define HWIO_EE_n_EV_CH_k_CNTXT_13_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_EV_CH_k_CNTXT_13_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_EV_CH_k_CNTXT_13_INI2(n, k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_13_RP_UPDATE_ADDR_MSB_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_13_RP_UPDATE_ADDR_MSB_SHFT 0x0 +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_ADDR(n, k) (GSI_REG_BASE + \ + 0x00010048 + 0x4000 * \ + (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x00010048 + 0x4000 * \ + (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x00010048 + 0x4000 * \ + (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_MAXn 2 +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_MAXk 19 +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_SCRATCH_0_ADDR(n, k), \ + HWIO_EE_n_EV_CH_k_SCRATCH_0_RMSK) +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_SCRATCH_0_ADDR(n, k), \ + mask) +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_EV_CH_k_SCRATCH_0_ADDR(n, k), \ + val) +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_EV_CH_k_SCRATCH_0_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_EV_CH_k_SCRATCH_0_INI2(n, k)) +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_SCRATCH_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_SCRATCH_SHFT 0x0 +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_ADDR(n, k) (GSI_REG_BASE + \ + 0x0001004c + 0x4000 * \ + (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001004c + 0x4000 * \ + (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001004c + 0x4000 * \ + (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_MAXn 2 +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_MAXk 19 +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_SCRATCH_1_ADDR(n, k), \ + HWIO_EE_n_EV_CH_k_SCRATCH_1_RMSK) +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_SCRATCH_1_ADDR(n, k), \ + mask) +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_EV_CH_k_SCRATCH_1_ADDR(n, k), \ + val) +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_EV_CH_k_SCRATCH_1_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_EV_CH_k_SCRATCH_1_INI2(n, k)) +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_SCRATCH_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_SCRATCH_SHFT 0x0 +#define HWIO_EE_n_GSI_CH_k_DOORBELL_0_ADDR(n, k) (GSI_REG_BASE + \ + 0x00011000 + 0x4000 * \ + (n) + 0x8 * (k)) +#define HWIO_EE_n_GSI_CH_k_DOORBELL_0_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x00011000 + 0x4000 * \ + (n) + 0x8 * (k)) +#define HWIO_EE_n_GSI_CH_k_DOORBELL_0_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x00011000 + 0x4000 * \ + (n) + 0x8 * (k)) +#define HWIO_EE_n_GSI_CH_k_DOORBELL_1_ADDR(n, k) (GSI_REG_BASE + \ + 0x00011004 + 0x4000 * \ + (n) + 0x8 * (k)) +#define HWIO_EE_n_GSI_CH_k_DOORBELL_1_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x00011004 + 0x4000 * \ + (n) + 0x8 * (k)) +#define HWIO_EE_n_GSI_CH_k_DOORBELL_1_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x00011004 + 0x4000 * \ + (n) + 0x8 * (k)) +#define HWIO_EE_n_EV_CH_k_DOORBELL_0_ADDR(n, k) (GSI_REG_BASE + \ + 0x00011100 + 0x4000 * \ + (n) + 0x8 * (k)) +#define HWIO_EE_n_EV_CH_k_DOORBELL_0_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x00011100 + 0x4000 * \ + (n) + 0x8 * (k)) +#define HWIO_EE_n_EV_CH_k_DOORBELL_0_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x00011100 + 0x4000 * \ + (n) + 0x8 * (k)) +#define HWIO_EE_n_EV_CH_k_DOORBELL_1_ADDR(n, k) (GSI_REG_BASE + \ + 0x00011104 + 0x4000 * \ + (n) + 0x8 * (k)) +#define HWIO_EE_n_EV_CH_k_DOORBELL_1_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x00011104 + 0x4000 * \ + (n) + 0x8 * (k)) +#define HWIO_EE_n_EV_CH_k_DOORBELL_1_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x00011104 + 0x4000 * \ + (n) + 0x8 * (k)) +#define HWIO_EE_n_GSI_STATUS_ADDR(n) (GSI_REG_BASE + 0x00012000 + 0x4000 * \ + (n)) +#define HWIO_EE_n_GSI_STATUS_PHYS(n) (GSI_REG_BASE_PHYS + 0x00012000 + \ + 0x4000 * (n)) +#define HWIO_EE_n_GSI_STATUS_OFFS(n) (GSI_REG_BASE_OFFS + 0x00012000 + \ + 0x4000 * (n)) +#define HWIO_EE_n_GSI_STATUS_RMSK 0x1 +#define HWIO_EE_n_GSI_STATUS_MAXn 2 +#define HWIO_EE_n_GSI_STATUS_ATTR 0x1 +#define HWIO_EE_n_GSI_STATUS_INI(n) in_dword_masked( \ + HWIO_EE_n_GSI_STATUS_ADDR(n), \ + HWIO_EE_n_GSI_STATUS_RMSK) +#define HWIO_EE_n_GSI_STATUS_INMI(n, mask) in_dword_masked( \ + HWIO_EE_n_GSI_STATUS_ADDR(n), \ + mask) +#define HWIO_EE_n_GSI_STATUS_ENABLED_BMSK 0x1 +#define HWIO_EE_n_GSI_STATUS_ENABLED_SHFT 0x0 +#define HWIO_EE_n_GSI_CH_CMD_ADDR(n) (GSI_REG_BASE + 0x00012008 + 0x4000 * \ + (n)) +#define HWIO_EE_n_GSI_CH_CMD_PHYS(n) (GSI_REG_BASE_PHYS + 0x00012008 + \ + 0x4000 * (n)) +#define HWIO_EE_n_GSI_CH_CMD_OFFS(n) (GSI_REG_BASE_OFFS + 0x00012008 + \ + 0x4000 * (n)) +#define HWIO_EE_n_EV_CH_CMD_ADDR(n) (GSI_REG_BASE + 0x00012010 + 0x4000 * \ + (n)) +#define HWIO_EE_n_EV_CH_CMD_PHYS(n) (GSI_REG_BASE_PHYS + 0x00012010 + \ + 0x4000 * (n)) +#define HWIO_EE_n_EV_CH_CMD_OFFS(n) (GSI_REG_BASE_OFFS + 0x00012010 + \ + 0x4000 * (n)) +#define HWIO_EE_n_GSI_EE_GENERIC_CMD_ADDR(n) (GSI_REG_BASE + 0x00012018 + \ + 0x4000 * (n)) +#define HWIO_EE_n_GSI_EE_GENERIC_CMD_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x00012018 + 0x4000 * (n)) +#define HWIO_EE_n_GSI_EE_GENERIC_CMD_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x00012018 + 0x4000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_0_ADDR(n) (GSI_REG_BASE + 0x00012038 + \ + 0x4000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_0_PHYS(n) (GSI_REG_BASE_PHYS + 0x00012038 + \ + 0x4000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_0_OFFS(n) (GSI_REG_BASE_OFFS + 0x00012038 + \ + 0x4000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_1_ADDR(n) (GSI_REG_BASE + 0x0001203c + \ + 0x4000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_1_PHYS(n) (GSI_REG_BASE_PHYS + 0x0001203c + \ + 0x4000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_1_OFFS(n) (GSI_REG_BASE_OFFS + 0x0001203c + \ + 0x4000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_2_ADDR(n) (GSI_REG_BASE + 0x00012040 + \ + 0x4000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_2_PHYS(n) (GSI_REG_BASE_PHYS + 0x00012040 + \ + 0x4000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_2_OFFS(n) (GSI_REG_BASE_OFFS + 0x00012040 + \ + 0x4000 * (n)) +#define HWIO_EE_n_GSI_SW_VERSION_ADDR(n) (GSI_REG_BASE + 0x00012044 + \ + 0x4000 * (n)) +#define HWIO_EE_n_GSI_SW_VERSION_PHYS(n) (GSI_REG_BASE_PHYS + 0x00012044 + \ + 0x4000 * (n)) +#define HWIO_EE_n_GSI_SW_VERSION_OFFS(n) (GSI_REG_BASE_OFFS + 0x00012044 + \ + 0x4000 * (n)) +#define HWIO_EE_n_GSI_MCS_CODE_VER_ADDR(n) (GSI_REG_BASE + 0x00012048 + \ + 0x4000 * (n)) +#define HWIO_EE_n_GSI_MCS_CODE_VER_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x00012048 + 0x4000 * (n)) +#define HWIO_EE_n_GSI_MCS_CODE_VER_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x00012048 + 0x4000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_3_ADDR(n) (GSI_REG_BASE + 0x0001204c + \ + 0x4000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_3_PHYS(n) (GSI_REG_BASE_PHYS + 0x0001204c + \ + 0x4000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_3_OFFS(n) (GSI_REG_BASE_OFFS + 0x0001204c + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_ADDR(n) (GSI_REG_BASE + 0x00012080 + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_PHYS(n) (GSI_REG_BASE_PHYS + 0x00012080 + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_OFFS(n) (GSI_REG_BASE_OFFS + 0x00012080 + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_RMSK 0x7f +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MAXn 2 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_ATTR 0x1 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_INI(n) in_dword_masked( \ + HWIO_EE_n_CNTXT_TYPE_IRQ_ADDR(n), \ + HWIO_EE_n_CNTXT_TYPE_IRQ_RMSK) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_INMI(n, mask) in_dword_masked( \ + HWIO_EE_n_CNTXT_TYPE_IRQ_ADDR(n), \ + mask) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_GENERAL_BMSK 0x40 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_GENERAL_SHFT 0x6 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_INTER_EE_EV_CTRL_BMSK 0x20 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_INTER_EE_EV_CTRL_SHFT 0x5 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_INTER_EE_CH_CTRL_BMSK 0x10 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_INTER_EE_CH_CTRL_SHFT 0x4 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_IEOB_BMSK 0x8 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_IEOB_SHFT 0x3 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_GLOB_EE_BMSK 0x4 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_GLOB_EE_SHFT 0x2 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_EV_CTRL_BMSK 0x2 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_EV_CTRL_SHFT 0x1 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_CH_CTRL_BMSK 0x1 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_CH_CTRL_SHFT 0x0 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_ADDR(n) (GSI_REG_BASE + 0x00012088 + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x00012088 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x00012088 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_RMSK 0x7f +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_MAXn 2 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_ATTR 0x3 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_INI(n) in_dword_masked( \ + HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_ADDR(n), \ + HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_RMSK) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_INMI(n, mask) in_dword_masked( \ + HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_ADDR(n), \ + mask) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_OUTI(n, val) out_dword( \ + HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_ADDR(n), \ + val) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_OUTMI(n, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_ADDR( \ + n), \ + mask, \ + val, \ + HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_INI(n)) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_GENERAL_BMSK 0x40 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_GENERAL_SHFT 0x6 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_INTER_EE_EV_CTRL_BMSK 0x20 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_INTER_EE_EV_CTRL_SHFT 0x5 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_INTER_EE_CH_CTRL_BMSK 0x10 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_INTER_EE_CH_CTRL_SHFT 0x4 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_IEOB_BMSK 0x8 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_IEOB_SHFT 0x3 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_GLOB_EE_BMSK 0x4 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_GLOB_EE_SHFT 0x2 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_EV_CTRL_BMSK 0x2 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_EV_CTRL_SHFT 0x1 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_CH_CTRL_BMSK 0x1 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_CH_CTRL_SHFT 0x0 +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_ADDR(n) (GSI_REG_BASE + \ + 0x00012090 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x00012090 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x00012090 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_RMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MAXn 2 +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_ATTR 0x1 +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_INI(n) in_dword_masked( \ + HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_ADDR(n), \ + HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_RMSK) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_INMI(n, mask) in_dword_masked( \ + HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_ADDR(n), \ + mask) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_GSI_CH_BIT_MAP_BMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_GSI_CH_BIT_MAP_SHFT 0x0 +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_ADDR(n) (GSI_REG_BASE + 0x00012094 + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x00012094 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x00012094 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_RMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MAXn 2 +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_ATTR 0x1 +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_INI(n) in_dword_masked( \ + HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_ADDR(n), \ + HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_RMSK) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_INMI(n, mask) in_dword_masked( \ + HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_ADDR(n), \ + mask) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_EV_CH_BIT_MAP_BMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_EV_CH_BIT_MAP_SHFT 0x0 +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_ADDR(n) (GSI_REG_BASE + \ + 0x00012098 + 0x4000 * \ + (n)) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x00012098 + 0x4000 * \ + (n)) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x00012098 + 0x4000 * \ + (n)) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_RMSK 0x7fffff +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_MAXn 2 +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_ATTR 0x3 +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_INI(n) in_dword_masked( \ + HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_ADDR(n), \ + HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_RMSK) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_INMI(n, mask) in_dword_masked( \ + HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_ADDR(n), \ + mask) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_OUTI(n, val) out_dword( \ + HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_ADDR(n), \ + val) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_OUTMI(n, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_ADDR( \ + n), \ + mask, \ + val, \ + HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_INI(n)) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_GSI_CH_BIT_MAP_MSK_BMSK \ + 0x7fffff +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_GSI_CH_BIT_MAP_MSK_SHFT 0x0 +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_ADDR(n) (GSI_REG_BASE + \ + 0x0001209c + 0x4000 * \ + (n)) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0001209c + 0x4000 * \ + (n)) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0001209c + 0x4000 * \ + (n)) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_RMSK 0xfffff +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_MAXn 2 +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_ATTR 0x3 +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_INI(n) in_dword_masked( \ + HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_ADDR(n), \ + HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_RMSK) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_INMI(n, mask) in_dword_masked( \ + HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_ADDR(n), \ + mask) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_OUTI(n, val) out_dword( \ + HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_ADDR(n), \ + val) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_OUTMI(n, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_ADDR( \ + n), \ + mask, \ + val, \ + HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_INI(n)) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_EV_CH_BIT_MAP_MSK_BMSK 0xfffff +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_EV_CH_BIT_MAP_MSK_SHFT 0x0 +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_ADDR(n) (GSI_REG_BASE + \ + 0x000120a0 + 0x4000 * \ + (n)) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x000120a0 + 0x4000 * \ + (n)) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x000120a0 + 0x4000 * \ + (n)) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_RMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_MAXn 2 +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_ATTR 0x2 +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_OUTI(n, val) out_dword( \ + HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_ADDR(n), \ + val) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_GSI_CH_BIT_MAP_BMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_GSI_CH_BIT_MAP_SHFT 0x0 +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_ADDR(n) (GSI_REG_BASE + \ + 0x000120a4 + 0x4000 * \ + (n)) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x000120a4 + 0x4000 * \ + (n)) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x000120a4 + 0x4000 * \ + (n)) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_RMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_MAXn 2 +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_ATTR 0x2 +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_OUTI(n, val) out_dword( \ + HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_ADDR(n), \ + val) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_EV_CH_BIT_MAP_BMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_EV_CH_BIT_MAP_SHFT 0x0 +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_ADDR(n) (GSI_REG_BASE + 0x000120b0 + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x000120b0 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x000120b0 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_RMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MAXn 2 +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_ATTR 0x1 +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_INI(n) in_dword_masked( \ + HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_ADDR(n), \ + HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_RMSK) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_INMI(n, mask) in_dword_masked( \ + HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_ADDR(n), \ + mask) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_EV_CH_BIT_MAP_BMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_EV_CH_BIT_MAP_SHFT 0x0 +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_ADDR(n) (GSI_REG_BASE + \ + 0x000120b8 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x000120b8 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x000120b8 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_RMSK 0xfffff +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_MAXn 2 +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_ATTR 0x3 +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_INI(n) in_dword_masked( \ + HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_ADDR(n), \ + HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_RMSK) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_INMI(n, mask) in_dword_masked( \ + HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_ADDR(n), \ + mask) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_OUTI(n, val) out_dword( \ + HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_ADDR(n), \ + val) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_OUTMI(n, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_ADDR( \ + n), \ + mask, \ + val, \ + HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_INI(n)) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_EV_CH_BIT_MAP_MSK_BMSK 0xfffff +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_EV_CH_BIT_MAP_MSK_SHFT 0x0 +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_ADDR(n) (GSI_REG_BASE + \ + 0x000120c0 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x000120c0 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x000120c0 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_RMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_MAXn 2 +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_ATTR 0x2 +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_OUTI(n, val) out_dword( \ + HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_ADDR(n), \ + val) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_EV_CH_BIT_MAP_BMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_EV_CH_BIT_MAP_SHFT 0x0 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_ADDR(n) (GSI_REG_BASE + 0x00012100 + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x00012100 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x00012100 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_RMSK 0xf +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_MAXn 2 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_ATTR 0x1 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_INI(n) in_dword_masked( \ + HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_ADDR(n), \ + HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_RMSK) +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_INMI(n, mask) in_dword_masked( \ + HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_ADDR(n), \ + mask) +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT3_BMSK 0x8 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT3_SHFT 0x3 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT2_BMSK 0x4 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT2_SHFT 0x2 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT1_BMSK 0x2 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT1_SHFT 0x1 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_ERROR_INT_BMSK 0x1 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_ERROR_INT_SHFT 0x0 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_EN_ADDR(n) (GSI_REG_BASE + 0x00012108 + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_GLOB_IRQ_EN_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x00012108 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_GLOB_IRQ_EN_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x00012108 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_GLOB_IRQ_CLR_ADDR(n) (GSI_REG_BASE + 0x00012110 + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_GLOB_IRQ_CLR_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x00012110 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_GLOB_IRQ_CLR_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x00012110 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_ADDR(n) (GSI_REG_BASE + 0x00012118 + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x00012118 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x00012118 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_RMSK 0xf +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_MAXn 2 +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_ATTR 0x1 +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_INI(n) in_dword_masked( \ + HWIO_EE_n_CNTXT_GSI_IRQ_STTS_ADDR(n), \ + HWIO_EE_n_CNTXT_GSI_IRQ_STTS_RMSK) +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_INMI(n, mask) in_dword_masked( \ + HWIO_EE_n_CNTXT_GSI_IRQ_STTS_ADDR(n), \ + mask) +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_GSI_MCS_STACK_OVRFLOW_BMSK 0x8 +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_GSI_MCS_STACK_OVRFLOW_SHFT 0x3 +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_GSI_CMD_FIFO_OVRFLOW_BMSK 0x4 +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_GSI_CMD_FIFO_OVRFLOW_SHFT 0x2 +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_GSI_BUS_ERROR_BMSK 0x2 +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_GSI_BUS_ERROR_SHFT 0x1 +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_GSI_BREAK_POINT_BMSK 0x1 +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_GSI_BREAK_POINT_SHFT 0x0 +#define HWIO_EE_n_CNTXT_GSI_IRQ_EN_ADDR(n) (GSI_REG_BASE + 0x00012120 + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_GSI_IRQ_EN_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x00012120 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_GSI_IRQ_EN_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x00012120 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_GSI_IRQ_CLR_ADDR(n) (GSI_REG_BASE + 0x00012128 + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_GSI_IRQ_CLR_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x00012128 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_GSI_IRQ_CLR_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x00012128 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_INTSET_ADDR(n) (GSI_REG_BASE + 0x00012180 + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_INTSET_PHYS(n) (GSI_REG_BASE_PHYS + 0x00012180 + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_INTSET_OFFS(n) (GSI_REG_BASE_OFFS + 0x00012180 + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_INTSET_RMSK 0x1 +#define HWIO_EE_n_CNTXT_INTSET_MAXn 2 +#define HWIO_EE_n_CNTXT_INTSET_ATTR 0x3 +#define HWIO_EE_n_CNTXT_INTSET_INI(n) in_dword_masked( \ + HWIO_EE_n_CNTXT_INTSET_ADDR(n), \ + HWIO_EE_n_CNTXT_INTSET_RMSK) +#define HWIO_EE_n_CNTXT_INTSET_INMI(n, mask) in_dword_masked( \ + HWIO_EE_n_CNTXT_INTSET_ADDR(n), \ + mask) +#define HWIO_EE_n_CNTXT_INTSET_OUTI(n, val) out_dword( \ + HWIO_EE_n_CNTXT_INTSET_ADDR(n), \ + val) +#define HWIO_EE_n_CNTXT_INTSET_OUTMI(n, mask, val) out_dword_masked_ns( \ + HWIO_EE_n_CNTXT_INTSET_ADDR(n), \ + mask, \ + val, \ + HWIO_EE_n_CNTXT_INTSET_INI(n)) +#define HWIO_EE_n_CNTXT_INTSET_INTYPE_BMSK 0x1 +#define HWIO_EE_n_CNTXT_INTSET_INTYPE_SHFT 0x0 +#define HWIO_EE_n_CNTXT_INTSET_INTYPE_MSI_FVAL 0x0 +#define HWIO_EE_n_CNTXT_INTSET_INTYPE_IRQ_FVAL 0x1 +#define HWIO_EE_n_CNTXT_MSI_BASE_LSB_ADDR(n) (GSI_REG_BASE + 0x00012188 + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_MSI_BASE_LSB_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x00012188 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_MSI_BASE_LSB_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x00012188 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_MSI_BASE_LSB_RMSK 0xffffffff +#define HWIO_EE_n_CNTXT_MSI_BASE_LSB_MAXn 2 +#define HWIO_EE_n_CNTXT_MSI_BASE_LSB_ATTR 0x3 +#define HWIO_EE_n_CNTXT_MSI_BASE_LSB_INI(n) in_dword_masked( \ + HWIO_EE_n_CNTXT_MSI_BASE_LSB_ADDR(n), \ + HWIO_EE_n_CNTXT_MSI_BASE_LSB_RMSK) +#define HWIO_EE_n_CNTXT_MSI_BASE_LSB_INMI(n, mask) in_dword_masked( \ + HWIO_EE_n_CNTXT_MSI_BASE_LSB_ADDR(n), \ + mask) +#define HWIO_EE_n_CNTXT_MSI_BASE_LSB_OUTI(n, val) out_dword( \ + HWIO_EE_n_CNTXT_MSI_BASE_LSB_ADDR(n), \ + val) +#define HWIO_EE_n_CNTXT_MSI_BASE_LSB_OUTMI(n, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_CNTXT_MSI_BASE_LSB_ADDR( \ + n), \ + mask, \ + val, \ + HWIO_EE_n_CNTXT_MSI_BASE_LSB_INI(n)) +#define HWIO_EE_n_CNTXT_MSI_BASE_LSB_MSI_ADDR_LSB_BMSK 0xffffffff +#define HWIO_EE_n_CNTXT_MSI_BASE_LSB_MSI_ADDR_LSB_SHFT 0x0 +#define HWIO_EE_n_CNTXT_MSI_BASE_MSB_ADDR(n) (GSI_REG_BASE + 0x0001218c + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_MSI_BASE_MSB_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0001218c + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_MSI_BASE_MSB_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0001218c + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_MSI_BASE_MSB_RMSK 0xffffffff +#define HWIO_EE_n_CNTXT_MSI_BASE_MSB_MAXn 2 +#define HWIO_EE_n_CNTXT_MSI_BASE_MSB_ATTR 0x3 +#define HWIO_EE_n_CNTXT_MSI_BASE_MSB_INI(n) in_dword_masked( \ + HWIO_EE_n_CNTXT_MSI_BASE_MSB_ADDR(n), \ + HWIO_EE_n_CNTXT_MSI_BASE_MSB_RMSK) +#define HWIO_EE_n_CNTXT_MSI_BASE_MSB_INMI(n, mask) in_dword_masked( \ + HWIO_EE_n_CNTXT_MSI_BASE_MSB_ADDR(n), \ + mask) +#define HWIO_EE_n_CNTXT_MSI_BASE_MSB_OUTI(n, val) out_dword( \ + HWIO_EE_n_CNTXT_MSI_BASE_MSB_ADDR(n), \ + val) +#define HWIO_EE_n_CNTXT_MSI_BASE_MSB_OUTMI(n, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_CNTXT_MSI_BASE_MSB_ADDR( \ + n), \ + mask, \ + val, \ + HWIO_EE_n_CNTXT_MSI_BASE_MSB_INI(n)) +#define HWIO_EE_n_CNTXT_MSI_BASE_MSB_MSI_ADDR_MSB_BMSK 0xffffffff +#define HWIO_EE_n_CNTXT_MSI_BASE_MSB_MSI_ADDR_MSB_SHFT 0x0 +#define HWIO_EE_n_CNTXT_INT_VEC_ADDR(n) (GSI_REG_BASE + 0x00012190 + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_INT_VEC_PHYS(n) (GSI_REG_BASE_PHYS + 0x00012190 + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_INT_VEC_OFFS(n) (GSI_REG_BASE_OFFS + 0x00012190 + \ + 0x4000 * (n)) +#define HWIO_EE_n_ERROR_LOG_ADDR(n) (GSI_REG_BASE + 0x00012200 + 0x4000 * \ + (n)) +#define HWIO_EE_n_ERROR_LOG_PHYS(n) (GSI_REG_BASE_PHYS + 0x00012200 + \ + 0x4000 * (n)) +#define HWIO_EE_n_ERROR_LOG_OFFS(n) (GSI_REG_BASE_OFFS + 0x00012200 + \ + 0x4000 * (n)) +#define HWIO_EE_n_ERROR_LOG_RMSK 0xffffffff +#define HWIO_EE_n_ERROR_LOG_MAXn 2 +#define HWIO_EE_n_ERROR_LOG_ATTR 0x3 +#define HWIO_EE_n_ERROR_LOG_INI(n) in_dword_masked( \ + HWIO_EE_n_ERROR_LOG_ADDR(n), \ + HWIO_EE_n_ERROR_LOG_RMSK) +#define HWIO_EE_n_ERROR_LOG_INMI(n, mask) in_dword_masked( \ + HWIO_EE_n_ERROR_LOG_ADDR(n), \ + mask) +#define HWIO_EE_n_ERROR_LOG_OUTI(n, val) out_dword( \ + HWIO_EE_n_ERROR_LOG_ADDR(n), \ + val) +#define HWIO_EE_n_ERROR_LOG_OUTMI(n, mask, val) out_dword_masked_ns( \ + HWIO_EE_n_ERROR_LOG_ADDR(n), \ + mask, \ + val, \ + HWIO_EE_n_ERROR_LOG_INI(n)) +#define HWIO_EE_n_ERROR_LOG_ERROR_LOG_BMSK 0xffffffff +#define HWIO_EE_n_ERROR_LOG_ERROR_LOG_SHFT 0x0 +#define HWIO_EE_n_ERROR_LOG_CLR_ADDR(n) (GSI_REG_BASE + 0x00012210 + \ + 0x4000 * (n)) +#define HWIO_EE_n_ERROR_LOG_CLR_PHYS(n) (GSI_REG_BASE_PHYS + 0x00012210 + \ + 0x4000 * (n)) +#define HWIO_EE_n_ERROR_LOG_CLR_OFFS(n) (GSI_REG_BASE_OFFS + 0x00012210 + \ + 0x4000 * (n)) +#define HWIO_EE_n_ERROR_LOG_CLR_RMSK 0xffffffff +#define HWIO_EE_n_ERROR_LOG_CLR_MAXn 2 +#define HWIO_EE_n_ERROR_LOG_CLR_ATTR 0x2 +#define HWIO_EE_n_ERROR_LOG_CLR_OUTI(n, val) out_dword( \ + HWIO_EE_n_ERROR_LOG_CLR_ADDR(n), \ + val) +#define HWIO_EE_n_ERROR_LOG_CLR_ERROR_LOG_CLR_BMSK 0xffffffff +#define HWIO_EE_n_ERROR_LOG_CLR_ERROR_LOG_CLR_SHFT 0x0 +#define HWIO_EE_n_CNTXT_SCRATCH_0_ADDR(n) (GSI_REG_BASE + 0x00012400 + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SCRATCH_0_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x00012400 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SCRATCH_0_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x00012400 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SCRATCH_0_RMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SCRATCH_0_MAXn 2 +#define HWIO_EE_n_CNTXT_SCRATCH_0_ATTR 0x3 +#define HWIO_EE_n_CNTXT_SCRATCH_0_INI(n) in_dword_masked( \ + HWIO_EE_n_CNTXT_SCRATCH_0_ADDR(n), \ + HWIO_EE_n_CNTXT_SCRATCH_0_RMSK) +#define HWIO_EE_n_CNTXT_SCRATCH_0_INMI(n, mask) in_dword_masked( \ + HWIO_EE_n_CNTXT_SCRATCH_0_ADDR(n), \ + mask) +#define HWIO_EE_n_CNTXT_SCRATCH_0_OUTI(n, val) out_dword( \ + HWIO_EE_n_CNTXT_SCRATCH_0_ADDR(n), \ + val) +#define HWIO_EE_n_CNTXT_SCRATCH_0_OUTMI(n, mask, val) out_dword_masked_ns( \ + HWIO_EE_n_CNTXT_SCRATCH_0_ADDR(n), \ + mask, \ + val, \ + HWIO_EE_n_CNTXT_SCRATCH_0_INI(n)) +#define HWIO_EE_n_CNTXT_SCRATCH_0_SCRATCH_BMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SCRATCH_0_SCRATCH_SHFT 0x0 +#define HWIO_EE_n_CNTXT_SCRATCH_1_ADDR(n) (GSI_REG_BASE + 0x00012404 + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SCRATCH_1_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x00012404 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SCRATCH_1_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x00012404 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SCRATCH_1_RMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SCRATCH_1_MAXn 2 +#define HWIO_EE_n_CNTXT_SCRATCH_1_ATTR 0x3 +#define HWIO_EE_n_CNTXT_SCRATCH_1_INI(n) in_dword_masked( \ + HWIO_EE_n_CNTXT_SCRATCH_1_ADDR(n), \ + HWIO_EE_n_CNTXT_SCRATCH_1_RMSK) +#define HWIO_EE_n_CNTXT_SCRATCH_1_INMI(n, mask) in_dword_masked( \ + HWIO_EE_n_CNTXT_SCRATCH_1_ADDR(n), \ + mask) +#define HWIO_EE_n_CNTXT_SCRATCH_1_OUTI(n, val) out_dword( \ + HWIO_EE_n_CNTXT_SCRATCH_1_ADDR(n), \ + val) +#define HWIO_EE_n_CNTXT_SCRATCH_1_OUTMI(n, mask, val) out_dword_masked_ns( \ + HWIO_EE_n_CNTXT_SCRATCH_1_ADDR(n), \ + mask, \ + val, \ + HWIO_EE_n_CNTXT_SCRATCH_1_INI(n)) +#define HWIO_EE_n_CNTXT_SCRATCH_1_SCRATCH_BMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SCRATCH_1_SCRATCH_SHFT 0x0 +#define HWIO_GSI_MCS_CFG_ADDR (GSI_REG_BASE + 0x0000b000) +#define HWIO_GSI_MCS_CFG_PHYS (GSI_REG_BASE_PHYS + 0x0000b000) +#define HWIO_GSI_MCS_CFG_OFFS (GSI_REG_BASE_OFFS + 0x0000b000) +#define HWIO_GSI_TZ_FW_AUTH_LOCK_ADDR (GSI_REG_BASE + 0x0000b008) +#define HWIO_GSI_TZ_FW_AUTH_LOCK_PHYS (GSI_REG_BASE_PHYS + 0x0000b008) +#define HWIO_GSI_TZ_FW_AUTH_LOCK_OFFS (GSI_REG_BASE_OFFS + 0x0000b008) +#define HWIO_GSI_MSA_FW_AUTH_LOCK_ADDR (GSI_REG_BASE + 0x0000b010) +#define HWIO_GSI_MSA_FW_AUTH_LOCK_PHYS (GSI_REG_BASE_PHYS + 0x0000b010) +#define HWIO_GSI_MSA_FW_AUTH_LOCK_OFFS (GSI_REG_BASE_OFFS + 0x0000b010) +#define HWIO_GSI_SP_FW_AUTH_LOCK_ADDR (GSI_REG_BASE + 0x0000b018) +#define HWIO_GSI_SP_FW_AUTH_LOCK_PHYS (GSI_REG_BASE_PHYS + 0x0000b018) +#define HWIO_GSI_SP_FW_AUTH_LOCK_OFFS (GSI_REG_BASE_OFFS + 0x0000b018) +#define HWIO_INTER_EE_n_ORIGINATOR_EE_ADDR(n) (GSI_REG_BASE + 0x0000c000 + \ + 0x1000 * (n)) +#define HWIO_INTER_EE_n_ORIGINATOR_EE_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0000c000 + 0x1000 * (n)) +#define HWIO_INTER_EE_n_ORIGINATOR_EE_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0000c000 + 0x1000 * (n)) +#define HWIO_INTER_EE_n_GSI_CH_CMD_ADDR(n) (GSI_REG_BASE + 0x0000c008 + \ + 0x1000 * (n)) +#define HWIO_INTER_EE_n_GSI_CH_CMD_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0000c008 + 0x1000 * (n)) +#define HWIO_INTER_EE_n_GSI_CH_CMD_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0000c008 + 0x1000 * (n)) +#define HWIO_INTER_EE_n_EV_CH_CMD_ADDR(n) (GSI_REG_BASE + 0x0000c010 + \ + 0x1000 * (n)) +#define HWIO_INTER_EE_n_EV_CH_CMD_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0000c010 + 0x1000 * (n)) +#define HWIO_INTER_EE_n_EV_CH_CMD_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0000c010 + 0x1000 * (n)) +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_ADDR(n) (GSI_REG_BASE + \ + 0x0000c018 + 0x1000 * (n)) +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0000c018 + 0x1000 * (n)) +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0000c018 + 0x1000 * (n)) +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_ADDR(n) (GSI_REG_BASE + 0x0000c01c + \ + 0x1000 * (n)) +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0000c01c + 0x1000 * (n)) +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0000c01c + 0x1000 * (n)) +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_ADDR(n) (GSI_REG_BASE + \ + 0x0000c020 + 0x1000 * \ + (n)) +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0000c020 + 0x1000 * \ + (n)) +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0000c020 + 0x1000 * \ + (n)) +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_MSK_ADDR(n) (GSI_REG_BASE + \ + 0x0000c024 + 0x1000 * \ + (n)) +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_MSK_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0000c024 + 0x1000 * \ + (n)) +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_MSK_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0000c024 + 0x1000 * \ + (n)) +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_ADDR(n) (GSI_REG_BASE + \ + 0x0000c028 + 0x1000 * \ + (n)) +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0000c028 + 0x1000 * \ + (n)) +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0000c028 + 0x1000 * \ + (n)) +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_CLR_ADDR(n) (GSI_REG_BASE + \ + 0x0000c02c + 0x1000 * \ + (n)) +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_CLR_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0000c02c + 0x1000 * \ + (n)) +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_CLR_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0000c02c + 0x1000 * \ + (n)) +#endif diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.5/gsi_hwio_def.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.5/gsi_hwio_def.h new file mode 100644 index 0000000000..e47edf626e --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.5/gsi_hwio_def.h @@ -0,0 +1,530 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ +#if !defined(_GSI_HWIO_DEF_H_) +#define _GSI_HWIO_DEF_H_ +struct gsi_hwio_def_gsi_cfg_s { + u32 gsi_enable : 1; + u32 mcs_enable : 1; + u32 double_mcs_clk_freq : 1; + u32 uc_is_mcs : 1; + u32 gsi_pwr_clps : 1; + u32 bp_mtrix_disable : 1; + u32 reserved0 : 2; + u32 sleep_clk_div : 4; + u32 reserved1 : 20; +}; +union gsi_hwio_def_gsi_cfg_u { + struct gsi_hwio_def_gsi_cfg_s def; + u32 value; +}; +struct gsi_hwio_def_gsi_ree_cfg_s { + u32 move_to_esc_clr_mode_trsh : 1; + u32 channel_empty_int_enable : 1; + u32 reserved0 : 6; + u32 max_burst_size : 8; + u32 reserved1 : 16; +}; +union gsi_hwio_def_gsi_ree_cfg_u { + struct gsi_hwio_def_gsi_ree_cfg_s def; + u32 value; +}; +struct gsi_hwio_def_gsi_manager_ee_qos_n_s { + u32 ee_prio : 2; + u32 reserved0 : 6; + u32 max_ch_alloc : 5; + u32 reserved1 : 3; + u32 max_ev_alloc : 5; + u32 reserved2 : 11; +}; +union gsi_hwio_def_gsi_manager_ee_qos_n_u { + struct gsi_hwio_def_gsi_manager_ee_qos_n_s def; + u32 value; +}; +struct gsi_hwio_def_gsi_shram_n_s { + u32 shram : 32; +}; +union gsi_hwio_def_gsi_shram_n_u { + struct gsi_hwio_def_gsi_shram_n_s def; + u32 value; +}; +struct gsi_hwio_def_gsi_map_ee_n_ch_k_vp_table_s { + u32 phy_ch : 5; + u32 valid : 1; + u32 reserved0 : 26; +}; +union gsi_hwio_def_gsi_map_ee_n_ch_k_vp_table_u { + struct gsi_hwio_def_gsi_map_ee_n_ch_k_vp_table_s def; + u32 value; +}; +struct gsi_hwio_def_gsi_test_bus_sel_s { + u32 gsi_testbus_sel : 8; + u32 reserved0 : 8; + u32 gsi_hw_events_sel : 4; + u32 reserved1 : 12; +}; +union gsi_hwio_def_gsi_test_bus_sel_u { + struct gsi_hwio_def_gsi_test_bus_sel_s def; + u32 value; +}; +struct gsi_hwio_def_gsi_test_bus_reg_s { + u32 gsi_testbus_reg : 32; +}; +union gsi_hwio_def_gsi_test_bus_reg_u { + struct gsi_hwio_def_gsi_test_bus_reg_s def; + u32 value; +}; +struct gsi_hwio_def_gsi_debug_countern_s { + u32 counter_value : 16; + u32 reserved0 : 16; +}; +union gsi_hwio_def_gsi_debug_countern_u { + struct gsi_hwio_def_gsi_debug_countern_s def; + u32 value; +}; +struct gsi_hwio_def_gsi_debug_qsb_log_last_misc_idn_s { + u32 addr_20_0 : 21; + u32 write : 1; + u32 tid : 5; + u32 mid : 5; +}; +union gsi_hwio_def_gsi_debug_qsb_log_last_misc_idn_u { + struct gsi_hwio_def_gsi_debug_qsb_log_last_misc_idn_s def; + u32 value; +}; +struct gsi_hwio_def_gsi_debug_sw_rf_n_read_s { + u32 rf_reg : 32; +}; +union gsi_hwio_def_gsi_debug_sw_rf_n_read_u { + struct gsi_hwio_def_gsi_debug_sw_rf_n_read_s def; + u32 value; +}; +struct gsi_hwio_def_gsi_debug_ee_n_ev_k_vp_table_s { + u32 phy_ev_ch : 5; + u32 valid : 1; + u32 reserved0 : 26; +}; +union gsi_hwio_def_gsi_debug_ee_n_ev_k_vp_table_u { + struct gsi_hwio_def_gsi_debug_ee_n_ev_k_vp_table_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_0_s { + u32 chtype_protocol : 3; + u32 chtype_dir : 1; + u32 ee : 4; + u32 chid : 5; + u32 chtype_protocol_msb : 1; + u32 erindex : 5; + u32 reserved0 : 1; + u32 chstate : 4; + u32 element_size : 8; +}; +union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_0_u { + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_0_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_1_s { + u32 r_length : 16; + u32 reserved0 : 16; +}; +union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_1_u { + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_1_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_2_s { + u32 r_base_addr_lsbs : 32; +}; +union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_2_u { + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_2_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_3_s { + u32 r_base_addr_msbs : 32; +}; +union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_3_u { + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_3_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_4_s { + u32 read_ptr_lsb : 32; +}; +union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_4_u { + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_4_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_5_s { + u32 read_ptr_msb : 32; +}; +union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_5_u { + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_5_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_6_s { + u32 write_ptr_lsb : 32; +}; +union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_6_u { + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_6_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_7_s { + u32 write_ptr_msb : 32; +}; +union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_7_u { + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_7_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_gsi_ch_k_re_fetch_read_ptr_s { + u32 read_ptr : 16; + u32 reserved0 : 16; +}; +union gsi_hwio_def_ee_n_gsi_ch_k_re_fetch_read_ptr_u { + struct gsi_hwio_def_ee_n_gsi_ch_k_re_fetch_read_ptr_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_gsi_ch_k_re_fetch_write_ptr_s { + u32 re_intr_db : 16; + u32 reserved0 : 16; +}; +union gsi_hwio_def_ee_n_gsi_ch_k_re_fetch_write_ptr_u { + struct gsi_hwio_def_ee_n_gsi_ch_k_re_fetch_write_ptr_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_gsi_ch_k_qos_s { + u32 wrr_weight : 4; + u32 reserved0 : 4; + u32 max_prefetch : 1; + u32 use_db_eng : 1; + u32 prefetch_mode : 4; + u32 reserved1 : 2; + u32 empty_lvl_thrshold : 8; + u32 reserved2 : 8; +}; +union gsi_hwio_def_ee_n_gsi_ch_k_qos_u { + struct gsi_hwio_def_ee_n_gsi_ch_k_qos_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_0_s { + u32 scratch : 32; +}; +union gsi_hwio_def_ee_n_gsi_ch_k_scratch_0_u { + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_0_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_1_s { + u32 scratch : 32; +}; +union gsi_hwio_def_ee_n_gsi_ch_k_scratch_1_u { + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_1_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_2_s { + u32 scratch : 32; +}; +union gsi_hwio_def_ee_n_gsi_ch_k_scratch_2_u { + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_2_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_3_s { + u32 scratch : 32; +}; +union gsi_hwio_def_ee_n_gsi_ch_k_scratch_3_u { + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_3_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_0_s { + u32 chtype : 4; + u32 ee : 4; + u32 evchid : 8; + u32 intype : 1; + u32 reserved0 : 3; + u32 chstate : 4; + u32 element_size : 8; +}; +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_0_u { + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_0_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_1_s { + u32 r_length : 16; + u32 reserved0 : 16; +}; +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_1_u { + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_1_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_2_s { + u32 r_base_addr_lsbs : 32; +}; +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_2_u { + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_2_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_3_s { + u32 r_base_addr_msbs : 32; +}; +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_3_u { + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_3_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_4_s { + u32 read_ptr_lsb : 32; +}; +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_4_u { + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_4_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_5_s { + u32 read_ptr_msb : 32; +}; +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_5_u { + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_5_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_6_s { + u32 write_ptr_lsb : 32; +}; +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_6_u { + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_6_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_7_s { + u32 write_ptr_msb : 32; +}; +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_7_u { + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_7_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_8_s { + u32 int_modt : 16; + u32 int_modc : 8; + u32 int_mod_cnt : 8; +}; +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_8_u { + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_8_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_9_s { + u32 intvec : 32; +}; +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_9_u { + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_9_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_10_s { + u32 msi_addr_lsb : 32; +}; +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_10_u { + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_10_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_11_s { + u32 msi_addr_msb : 32; +}; +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_11_u { + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_11_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_12_s { + u32 rp_update_addr_lsb : 32; +}; +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_12_u { + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_12_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_13_s { + u32 rp_update_addr_msb : 32; +}; +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_13_u { + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_13_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_ev_ch_k_scratch_0_s { + u32 scratch : 32; +}; +union gsi_hwio_def_ee_n_ev_ch_k_scratch_0_u { + struct gsi_hwio_def_ee_n_ev_ch_k_scratch_0_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_ev_ch_k_scratch_1_s { + u32 scratch : 32; +}; +union gsi_hwio_def_ee_n_ev_ch_k_scratch_1_u { + struct gsi_hwio_def_ee_n_ev_ch_k_scratch_1_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_gsi_status_s { + u32 enabled : 1; + u32 reserved0 : 31; +}; +union gsi_hwio_def_ee_n_gsi_status_u { + struct gsi_hwio_def_ee_n_gsi_status_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_cntxt_type_irq_s { + u32 ch_ctrl : 1; + u32 ev_ctrl : 1; + u32 glob_ee : 1; + u32 ieob : 1; + u32 inter_ee_ch_ctrl : 1; + u32 inter_ee_ev_ctrl : 1; + u32 general : 1; + u32 reserved0 : 25; +}; +union gsi_hwio_def_ee_n_cntxt_type_irq_u { + struct gsi_hwio_def_ee_n_cntxt_type_irq_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_cntxt_type_irq_msk_s { + u32 ch_ctrl : 1; + u32 ev_ctrl : 1; + u32 glob_ee : 1; + u32 ieob : 1; + u32 inter_ee_ch_ctrl : 1; + u32 inter_ee_ev_ctrl : 1; + u32 general : 1; + u32 reserved0 : 25; +}; +union gsi_hwio_def_ee_n_cntxt_type_irq_msk_u { + struct gsi_hwio_def_ee_n_cntxt_type_irq_msk_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_s { + u32 gsi_ch_bit_map : 32; +}; +union gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_u { + struct gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_s { + u32 ev_ch_bit_map : 32; +}; +union gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_u { + struct gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_msk_s { + u32 gsi_ch_bit_map_msk : 23; + u32 reserved0 : 9; +}; +union gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_msk_u { + struct gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_msk_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_msk_s { + u32 ev_ch_bit_map_msk : 20; + u32 reserved0 : 12; +}; +union gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_msk_u { + struct gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_msk_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_clr_s { + u32 gsi_ch_bit_map : 32; +}; +union gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_clr_u { + struct gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_clr_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_clr_s { + u32 ev_ch_bit_map : 32; +}; +union gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_clr_u { + struct gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_clr_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_cntxt_src_ieob_irq_s { + u32 ev_ch_bit_map : 32; +}; +union gsi_hwio_def_ee_n_cntxt_src_ieob_irq_u { + struct gsi_hwio_def_ee_n_cntxt_src_ieob_irq_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_cntxt_src_ieob_irq_msk_s { + u32 ev_ch_bit_map_msk : 20; + u32 reserved0 : 12; +}; +union gsi_hwio_def_ee_n_cntxt_src_ieob_irq_msk_u { + struct gsi_hwio_def_ee_n_cntxt_src_ieob_irq_msk_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_cntxt_src_ieob_irq_clr_s { + u32 ev_ch_bit_map : 32; +}; +union gsi_hwio_def_ee_n_cntxt_src_ieob_irq_clr_u { + struct gsi_hwio_def_ee_n_cntxt_src_ieob_irq_clr_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_cntxt_glob_irq_stts_s { + u32 error_int : 1; + u32 gp_int1 : 1; + u32 gp_int2 : 1; + u32 gp_int3 : 1; + u32 reserved0 : 28; +}; +union gsi_hwio_def_ee_n_cntxt_glob_irq_stts_u { + struct gsi_hwio_def_ee_n_cntxt_glob_irq_stts_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_cntxt_gsi_irq_stts_s { + u32 gsi_break_point : 1; + u32 gsi_bus_error : 1; + u32 gsi_cmd_fifo_ovrflow : 1; + u32 gsi_mcs_stack_ovrflow : 1; + u32 reserved0 : 28; +}; +union gsi_hwio_def_ee_n_cntxt_gsi_irq_stts_u { + struct gsi_hwio_def_ee_n_cntxt_gsi_irq_stts_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_cntxt_intset_s { + u32 intype : 1; + u32 reserved0 : 31; +}; +union gsi_hwio_def_ee_n_cntxt_intset_u { + struct gsi_hwio_def_ee_n_cntxt_intset_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_cntxt_msi_base_lsb_s { + u32 msi_addr_lsb : 32; +}; +union gsi_hwio_def_ee_n_cntxt_msi_base_lsb_u { + struct gsi_hwio_def_ee_n_cntxt_msi_base_lsb_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_cntxt_msi_base_msb_s { + u32 msi_addr_msb : 32; +}; +union gsi_hwio_def_ee_n_cntxt_msi_base_msb_u { + struct gsi_hwio_def_ee_n_cntxt_msi_base_msb_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_error_log_s { + u32 error_log : 32; +}; +union gsi_hwio_def_ee_n_error_log_u { + struct gsi_hwio_def_ee_n_error_log_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_error_log_clr_s { + u32 error_log_clr : 32; +}; +union gsi_hwio_def_ee_n_error_log_clr_u { + struct gsi_hwio_def_ee_n_error_log_clr_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_cntxt_scratch_0_s { + u32 scratch : 32; +}; +union gsi_hwio_def_ee_n_cntxt_scratch_0_u { + struct gsi_hwio_def_ee_n_cntxt_scratch_0_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_cntxt_scratch_1_s { + u32 scratch : 32; +}; +union gsi_hwio_def_ee_n_cntxt_scratch_1_u { + struct gsi_hwio_def_ee_n_cntxt_scratch_1_s def; + u32 value; +}; +#endif diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.5/ipa_access_control.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.5/ipa_access_control.h new file mode 100644 index 0000000000..3fdb2edfc4 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.5/ipa_access_control.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ +#if !defined(_IPA_ACCESS_CONTROL_H_) +#define _IPA_ACCESS_CONTROL_H_ + +#include "ipa_reg_dump.h" + +/* + * The following is target specific. + */ +static struct reg_mem_access_map_t mem_access_map[] = { + /*------------------------------------------------------------*/ + /* Range Use when Use when */ + /* Begin End SD_ENABLED SD_DISABLED */ + /*------------------------------------------------------------*/ + { 0x04000, 0x05000, { &io_matrix[AN_COMBO], &io_matrix[AN_COMBO] } }, + { 0x1F000, 0x27000, { &io_matrix[AN_COMBO], &io_matrix[AN_COMBO] } }, + { 0x05000, 0x0f000, { &io_matrix[AA_COMBO], &io_matrix[AN_COMBO] } }, + { 0x0f000, 0x10000, { &io_matrix[NN_COMBO], &io_matrix[NN_COMBO] } }, + { 0x13000, 0x17000, { &io_matrix[AA_COMBO], &io_matrix[AA_COMBO] } }, + { 0x17000, 0x1b000, { &io_matrix[AN_COMBO], &io_matrix[AN_COMBO] } }, + { 0x1b000, 0x1f000, { &io_matrix[AN_COMBO], &io_matrix[AN_COMBO] } }, + { 0x10000, 0x11000, { &io_matrix[AA_COMBO], &io_matrix[AA_COMBO] } }, + { 0x11000, 0x12000, { &io_matrix[AN_COMBO], &io_matrix[AN_COMBO] } }, + { 0x12000, 0x13000, { &io_matrix[AA_COMBO], &io_matrix[AA_COMBO] } }, + { 0x43000, 0x44000, { &io_matrix[AA_COMBO], &io_matrix[AA_COMBO] } }, + { 0x44000, 0x45000, { &io_matrix[AA_COMBO], &io_matrix[AA_COMBO] } }, + { 0x45000, 0x47000, { &io_matrix[AN_COMBO], &io_matrix[AN_COMBO] } }, + { 0x40000, 0x42000, { &io_matrix[AA_COMBO], &io_matrix[AA_COMBO] } }, + { 0x42000, 0x43000, { &io_matrix[AA_COMBO], &io_matrix[AN_COMBO] } }, + { 0x50000, 0x60000, { &io_matrix[AA_COMBO], &io_matrix[AA_COMBO] } }, + { 0x60000, 0x80000, { &io_matrix[AN_COMBO], &io_matrix[NN_COMBO] } }, + { 0x80000, 0x81000, { &io_matrix[NN_COMBO], &io_matrix[NN_COMBO] } }, + { 0x81000, 0x83000, { &io_matrix[AN_COMBO], &io_matrix[AN_COMBO] } }, + { 0xa0000, 0xc0000, { &io_matrix[AN_COMBO], &io_matrix[AN_COMBO] } }, + { 0xc0000, 0xc2000, { &io_matrix[AA_COMBO], &io_matrix[AA_COMBO] } }, + { 0xc2000, 0xd0000, { &io_matrix[AA_COMBO], &io_matrix[AA_COMBO] } }, +}; + +#endif /* #if !defined(_IPA_ACCESS_CONTROL_H_) */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.5/ipa_gcc_hwio.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.5/ipa_gcc_hwio.h new file mode 100644 index 0000000000..0adf6ad866 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.5/ipa_gcc_hwio.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ +#if !defined(_IPA_GCC_HWIO_H_) +#define _IPA_GCC_HWIO_H_ +/* + * + * HWIO register definitions to follow: + * + */ +#endif diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.5/ipa_gcc_hwio_def.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.5/ipa_gcc_hwio_def.h new file mode 100644 index 0000000000..c841baceb7 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.5/ipa_gcc_hwio_def.h @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ +#if !defined(_IPA_GCC_HWIO_DEF_H_) +#define _IPA_GCC_HWIO_DEF_H_ +#endif diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.5/ipa_hw_common_ex.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.5/ipa_hw_common_ex.h new file mode 100644 index 0000000000..9fdc926cb0 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.5/ipa_hw_common_ex.h @@ -0,0 +1,593 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ +#if !defined(_IPA_HW_COMMON_EX_H_) +#define _IPA_HW_COMMON_EX_H_ + +/* VLVL defs are available for 854 */ +#define FEATURE_VLVL_DEFS true + +#define FEATURE_IPA_HW_VERSION_4_5 true + +/* Important Platform Specific Values : IRQ_NUM, IRQ_CNT, BCR */ +#define IPA_HW_BAM_IRQ_NUM 639 + +/* Q6 IRQ number for IPA. */ +#define IPA_HW_IRQ_NUM 640 + +/* Total number of different interrupts that can be enabled */ +#define IPA_HW_IRQ_CNT_TOTAL 23 + +/* IPAv4 spare reg value */ +#define IPA_HW_SPARE_1_REG_VAL 0xC0000005 + +/* Whether to allow setting step mode on IPA when we crash or not */ +#define IPA_CFG_HW_IS_STEP_MODE_ALLOWED (false) + +/* GSI MHI related definitions */ +#define IPA_HW_GSI_MHI_CONSUMER_CHANNEL_NUM 0x0 +#define IPA_HW_GSI_MHI_PRODUCER_CHANNEL_NUM 0x1 + +#define IPA_HW_GSI_MHI_CONSUMER_EP_NUM 0x1 +#define IPA_HW_GSI_MHI_PRODUCER_EP_NUM 0x11 + +/* IPA ZIP WA related Macros */ +#define IPA_HW_DCMP_SRC_PIPE 0x8 +#define IPA_HW_DCMP_DEST_PIPE 0x4 +#define IPA_HW_ACK_MNGR_MASK 0x1D +#define IPA_HW_DCMP_SRC_GRP 0x5 + +/* IPA Clock resource name */ +#define IPA_CLK_RESOURCE_NAME "/clk/pcnoc" + +/* IPA Clock Bus Client name */ +#define IPA_CLK_BUS_CLIENT_NAME "IPA_PCNOC_BUS_CLIENT" + +/* HPS Sequences */ +#define IPA_HW_PKT_PROCESS_HPS_DMA 0x0 +#define IPA_HW_PKT_PROCESS_HPS_DMA_DECIPH_CIPHE 0x1 +#define IPA_HW_PKT_PROCESS_HPS_PKT_PRS_NO_DECIPH_UCP 0x2 +#define IPA_HW_PKT_PROCESS_HPS_PKT_PRS_DECIPH_UCP 0x3 +#define IPA_HW_PKT_PROCESS_HPS_2_PKT_PRS_NO_DECIPH 0x4 +#define IPA_HW_PKT_PROCESS_HPS_2_PKT_PRS_DECIPH 0x5 +#define IPA_HW_PKT_PROCESS_HPS_PKT_PRS_NO_DECIPH_NO_UCP 0x6 +#define IPA_HW_PKT_PROCESS_HPS_PKT_PRS_DECIPH_NO_UCP 0x7 +#define IPA_HW_PKT_PROCESS_HPS_DMA_PARSER 0x8 +#define IPA_HW_PKT_PROCESS_HPS_DMA_DECIPH_PARSER 0x9 +#define IPA_HW_PKT_PROCESS_HPS_2_PKT_PRS_UCP_TWICE_NO_DECIPH 0xA +#define IPA_HW_PKT_PROCESS_HPS_2_PKT_PRS_UCP_TWICE_DECIPH 0xB +#define IPA_HW_PKT_PROCESS_HPS_3_PKT_PRS_UCP_TWICE_NO_DECIPH 0xC +#define IPA_HW_PKT_PROCESS_HPS_3_PKT_PRS_UCP_TWICE_DECIPH 0xD + +/* DPS Sequences */ +#define IPA_HW_PKT_PROCESS_DPS_DMA 0x0 +#define IPA_HW_PKT_PROCESS_DPS_DMA_WITH_DECIPH 0x1 +#define IPA_HW_PKT_PROCESS_DPS_DMA_WITH_DECOMP 0x2 +#define IPA_HW_PKT_PROCESS_DPS_DMA_WITH_CIPH 0x3 + +/* Src RSRC GRP config */ +#define IPA_HW_SRC_RSRC_GRP_01_RSRC_TYPE_0 0x0B040803 +#define IPA_HW_SRC_RSRC_GRP_01_RSRC_TYPE_1 0x0C0C0909 +#define IPA_HW_SRC_RSRC_GRP_01_RSRC_TYPE_2 0x0E0E0909 +#define IPA_HW_SRC_RSRC_GRP_01_RSRC_TYPE_3 0x3F003F00 +#define IPA_HW_SRC_RSRC_GRP_01_RSRC_TYPE_4 0x10101616 + +#define IPA_HW_SRC_RSRC_GRP_23_RSRC_TYPE_0 0x01010101 +#define IPA_HW_SRC_RSRC_GRP_23_RSRC_TYPE_1 0x02020202 +#define IPA_HW_SRC_RSRC_GRP_23_RSRC_TYPE_2 0x04040404 +#define IPA_HW_SRC_RSRC_GRP_23_RSRC_TYPE_3 0x3F003F00 +#define IPA_HW_SRC_RSRC_GRP_23_RSRC_TYPE_4 0x02020606 + +#define IPA_HW_SRC_RSRC_GRP_45_RSRC_TYPE_0 0x00000000 +#define IPA_HW_SRC_RSRC_GRP_45_RSRC_TYPE_1 0x00000000 +#define IPA_HW_SRC_RSRC_GRP_45_RSRC_TYPE_2 0x00000000 +#define IPA_HW_SRC_RSRC_GRP_45_RSRC_TYPE_3 0x00003F00 +#define IPA_HW_SRC_RSRC_GRP_45_RSRC_TYPE_4 0x00000000 + +/* Dest RSRC GRP config */ +#define IPA_HW_DST_RSRC_GRP_01_RSRC_TYPE_0 0x05051010 +#define IPA_HW_DST_RSRC_GRP_01_RSRC_TYPE_1 0x3F013F02 + +#define IPA_HW_DST_RSRC_GRP_23_RSRC_TYPE_0 0x02020202 +#define IPA_HW_DST_RSRC_GRP_23_RSRC_TYPE_1 0x02010201 + +#define IPA_HW_DST_RSRC_GRP_45_RSRC_TYPE_0 0x00000000 +#define IPA_HW_DST_RSRC_GRP_45_RSRC_TYPE_1 0x00000200 + +#define IPA_HW_RX_HPS_CLIENTS_MIN_DEPTH_0 0x03030303 +#define IPA_HW_RX_HPS_CLIENTS_MAX_DEPTH_0 0x03030303 + +#define IPA_HW_RSRP_GRP_0 0x0 +#define IPA_HW_RSRP_GRP_1 0x1 +#define IPA_HW_RSRP_GRP_2 0x2 +#define IPA_HW_RSRP_GRP_3 0x3 + +#define IPA_HW_PCIE_SRC_RSRP_GRP IPA_HW_RSRP_GRP_0 +#define IPA_HW_PCIE_DEST_RSRP_GRP IPA_HW_RSRP_GRP_0 + +#define IPA_HW_DDR_SRC_RSRP_GRP IPA_HW_RSRP_GRP_1 +#define IPA_HW_DDR_DEST_RSRP_GRP IPA_HW_RSRP_GRP_1 + +#define IPA_HW_DMA_SRC_RSRP_GRP IPA_HW_RSRP_GRP_2 +#define IPA_HW_DMA_DEST_RSRP_GRP IPA_HW_RSRP_GRP_2 + +#define IPA_HW_SRC_RSRP_TYPE_MAX 0x05 +#define IPA_HW_DST_RSRP_TYPE_MAX 0x02 + +#define GSI_HW_QSB_LOG_MISC_MAX 0x4 + +/* IPA Clock Bus Client name */ +#define IPA_CLK_BUS_CLIENT_NAME "IPA_PCNOC_BUS_CLIENT" + +/* Is IPA decompression feature enabled */ +#define IPA_HW_IS_DECOMPRESSION_ENABLED (1) + +/* Whether to allow setting step mode on IPA when we crash or not */ +#define IPA_HW_IS_STEP_MODE_ALLOWED (true) + +/* Max number of virtual pipes for UL QBAP provided by HW */ +#define IPA_HW_MAX_VP_NUM (32) + +/* + * HW specific clock vote freq values in KHz + * (BIMC/SNOC/PCNOC/IPA/Q6 CPU) + */ +enum ipa_hw_clk_freq_e { + /* BIMC */ + IPA_HW_CLK_FREQ_BIMC_PEAK = 518400, + IPA_HW_CLK_FREQ_BIMC_NOM_PLUS = 404200, + IPA_HW_CLK_FREQ_BIMC_NOM = 404200, + IPA_HW_CLK_FREQ_BIMC_SVS = 100000, + + /* PCNOC */ + IPA_HW_CLK_FREQ_PCNOC_PEAK = 133330, + IPA_HW_CLK_FREQ_PCNOC_NOM_PLUS = 100000, + IPA_HW_CLK_FREQ_PCNOC_NOM = 100000, + IPA_HW_CLK_FREQ_PCNOC_SVS = 50000, + + /*IPA_HW_CLK_SNOC*/ + IPA_HW_CLK_FREQ_SNOC_PEAK = 200000, + IPA_HW_CLK_FREQ_SNOC_NOM_PLUS = 150000, + IPA_HW_CLK_FREQ_SNOC_NOM = 150000, + IPA_HW_CLK_FREQ_SNOC_SVS = 85000, + IPA_HW_CLK_FREQ_SNOC_SVS_2 = 50000, + + /* IPA */ + IPA_HW_CLK_FREQ_IPA_PEAK = 600000, + IPA_HW_CLK_FREQ_IPA_NOM_PLUS = 500000, + IPA_HW_CLK_FREQ_IPA_NOM = 500000, + IPA_HW_CLK_FREQ_IPA_SVS = 250000, + IPA_HW_CLK_FREQ_IPA_SVS_2 = 150000, + + /* Q6 CPU */ + IPA_HW_CLK_FREQ_Q6_PEAK = 729600, + IPA_HW_CLK_FREQ_Q6_NOM_PLUS = 729600, + IPA_HW_CLK_FREQ_Q6_NOM = 729600, + IPA_HW_CLK_FREQ_Q6_SVS = 729600, +}; + +enum ipa_hw_qtimer_gran_e { + IPA_HW_QTIMER_GRAN_0 = 0, /* granularity 0 is 10us */ + IPA_HW_QTIMER_GRAN_1 = 1, /* granularity 1 is 100us */ + IPA_HW_QTIMER_GRAN_MAX, +}; + +/* Pipe ID of all the IPA pipes */ +enum ipa_hw_pipe_id_e { + IPA_HW_PIPE_ID_0, + IPA_HW_PIPE_ID_1, + IPA_HW_PIPE_ID_2, + IPA_HW_PIPE_ID_3, + IPA_HW_PIPE_ID_4, + IPA_HW_PIPE_ID_5, + IPA_HW_PIPE_ID_6, + IPA_HW_PIPE_ID_7, + IPA_HW_PIPE_ID_8, + IPA_HW_PIPE_ID_9, + IPA_HW_PIPE_ID_10, + IPA_HW_PIPE_ID_11, + IPA_HW_PIPE_ID_12, + IPA_HW_PIPE_ID_13, + IPA_HW_PIPE_ID_14, + IPA_HW_PIPE_ID_15, + IPA_HW_PIPE_ID_16, + IPA_HW_PIPE_ID_17, + IPA_HW_PIPE_ID_18, + IPA_HW_PIPE_ID_19, + IPA_HW_PIPE_ID_20, + IPA_HW_PIPE_ID_21, + IPA_HW_PIPE_ID_22, + IPA_HW_PIPE_ID_23, + IPA_HW_PIPE_ID_24, + IPA_HW_PIPE_ID_25, + IPA_HW_PIPE_ID_26, + IPA_HW_PIPE_ID_27, + IPA_HW_PIPE_ID_28, + IPA_HW_PIPE_ID_29, + IPA_HW_PIPE_ID_30, + IPA_HW_PIPE_ID_MAX +}; + +/* Pipe ID's of System Bam Endpoints between Q6 & IPA */ +enum ipa_hw_q6_pipe_id_e { + /* Pipes used by IPA Q6 driver */ + IPA_HW_Q6_DL_CONSUMER_PIPE_ID = IPA_HW_PIPE_ID_5, + IPA_HW_Q6_CTL_CONSUMER_PIPE_ID = IPA_HW_PIPE_ID_6, + IPA_HW_Q6_DL_NLO_CONSUMER_PIPE_ID = IPA_HW_PIPE_ID_8, + + IPA_HW_Q6_UL_ACC_ACK_PRODUCER_PIPE_ID = IPA_HW_PIPE_ID_20, + IPA_HW_Q6_UL_PRODUCER_PIPE_ID = IPA_HW_PIPE_ID_21, + IPA_HW_Q6_DL_PRODUCER_PIPE_ID = IPA_HW_PIPE_ID_17, + IPA_HW_Q6_QBAP_STATUS_PRODUCER_PIPE_ID = IPA_HW_PIPE_ID_18, + IPA_HW_Q6_UL_ACC_DATA_PRODUCER_PIPE_ID = IPA_HW_PIPE_ID_19, + + IPA_HW_Q6_UL_ACK_PRODUCER_PIPE_ID = + IPA_HW_Q6_UL_ACC_ACK_PRODUCER_PIPE_ID, + IPA_HW_Q6_UL_DATA_PRODUCER_PIPE_ID = + IPA_HW_Q6_UL_ACC_DATA_PRODUCER_PIPE_ID, + + IPA_HW_Q6_DMA_ASYNC_CONSUMER_PIPE_ID = IPA_HW_PIPE_ID_4, + IPA_HW_Q6_DMA_ASYNC_PRODUCER_PIPE_ID = IPA_HW_PIPE_ID_29, + + /* Test Simulator Pipes */ + IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_0_ID = IPA_HW_PIPE_ID_0, + IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_1_ID = IPA_HW_PIPE_ID_1, + + /* GSI UT channel SW->IPA */ + IPA_HW_Q6_GSI_UT_CONSUMER_PIPE_1_ID = IPA_HW_PIPE_ID_3, + /* GSI UT channel SW->IPA */ + IPA_HW_Q6_GSI_UT_CONSUMER_PIPE_2_ID = IPA_HW_PIPE_ID_10, + + IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_2_ID = IPA_HW_PIPE_ID_7, + + /* GSI UT channel IPA->SW */ + IPA_HW_Q6_DIAG_CONSUMER_PIPE_ID = IPA_HW_PIPE_ID_9, + + IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_0_ID = IPA_HW_PIPE_ID_23, + IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_1_ID = IPA_HW_PIPE_ID_24, + + IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_2_ID = IPA_HW_PIPE_ID_25, + + /* GSI UT channel IPA->SW */ + IPA_HW_Q6_GSI_UT_PRODUCER_PIPE_1_ID = IPA_HW_PIPE_ID_26, + + /* GSI UT channel IPA->SW */ + IPA_HW_Q6_GSI_UT_PRODUCER_PIPE_2_ID = IPA_HW_PIPE_ID_27, + IPA_HW_Q6_PIPE_ID_MAX = IPA_HW_PIPE_ID_MAX, +}; + +enum ipa_hw_q6_pipe_ch_id_e { + /* Channels used by IPA Q6 driver */ + IPA_HW_Q6_DL_CONSUMER_PIPE_CH_ID = 0, + IPA_HW_Q6_CTL_CONSUMER_PIPE_CH_ID = 1, + IPA_HW_Q6_DL_NLO_CONSUMER_PIPE_CH_ID = 2, + IPA_HW_Q6_UL_ACC_PATH_ACK_PRODUCER_PIPE_CH_ID = 6, + IPA_HW_Q6_UL_PRODUCER_PIPE_CH_ID = 7, + IPA_HW_Q6_DL_PRODUCER_PIPE_CH_ID = 3, + IPA_HW_Q6_UL_ACC_PATH_DATA_PRODUCER_PIPE_CH_ID = 5, + IPA_HW_Q6_QBAP_STATUS_PRODUCER_PIPE_CH_ID = 4, + + IPA_HW_Q6_DMA_ASYNC_CONSUMER_PIPE_CH_ID = 8, + IPA_HW_Q6_DMA_ASYNC_PRODUCER_PIPE_CH_ID = 9, + /* CH_ID 8 and 9 are Q6 SPARE CONSUMERs */ + + /* Test Simulator Channels */ + IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_0_CH_ID = 10, + IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_0_CH_ID = 11, + IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_1_CH_ID = 12, + IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_1_CH_ID = 13, + IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_2_CH_ID = 14, + IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_2_CH_ID = 15, + /* GSI UT channel SW->IPA */ + IPA_HW_Q6_GSI_UT_CONSUMER_PIPE_1_CH_ID = 16, + /* GSI UT channel IPA->SW */ + IPA_HW_Q6_GSI_UT_PRODUCER_PIPE_1_CH_ID = 17, + /* GSI UT channel SW->IPA */ + IPA_HW_Q6_GSI_UT_CONSUMER_PIPE_2_CH_ID = 18, + /* GSI UT channel IPA->SW */ + IPA_HW_Q6_GSI_UT_PRODUCER_PIPE_2_CH_ID = 19, +}; + +/* System Bam Endpoints between Q6 & IPA */ +enum ipa_hw_q6_pipe_e { + /* DL Pipe IPA->Q6 */ + IPA_HW_Q6_DL_PRODUCER_PIPE = 0, + /* UL Pipe IPA->Q6 */ + IPA_HW_Q6_UL_PRODUCER_PIPE = 1, + /* DL Pipe Q6->IPA */ + IPA_HW_Q6_DL_CONSUMER_PIPE = 2, + /* CTL Pipe Q6->IPA */ + IPA_HW_Q6_CTL_CONSUMER_PIPE = 3, + /* Q6 -> IPA, DL NLO */ + IPA_HW_Q6_DL_NLO_CONSUMER_PIPE = 4, + /* DMA ASYNC CONSUMER */ + IPA_HW_Q6_DMA_ASYNC_CONSUMER_PIPE = 5, + /* DMA ASYNC PRODUCER */ + IPA_HW_Q6_DMA_ASYNC_PRODUCER_PIPE = 6, + /* UL Acc Path Data Pipe IPA->Q6 */ + IPA_HW_Q6_UL_ACC_DATA_PRODUCER_PIPE = 7, + /* UL Acc Path ACK Pipe IPA->Q6 */ + IPA_HW_Q6_UL_ACC_ACK_PRODUCER_PIPE = 8, + /* UL Acc Path QBAP status Pipe IPA->Q6 */ + IPA_HW_Q6_QBAP_STATUS_PRODUCER_PIPE = 9, + /* Diag status pipe IPA->Q6 */ + /* Used only when FEATURE_IPA_TEST_PER_SIM is ON */ + /* SIM Pipe IPA->Sim */ + IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_0 = 10, + /* SIM Pipe Sim->IPA */ + IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_1 = 11, + /* SIM Pipe Sim->IPA */ + IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_2 = 12, + /* SIM Pipe Sim->IPA */ + IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_0 = 13, + /* SIM B2B PROD Pipe */ + IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_1 = 14, + /* SIM Pipe IPA->Sim */ + IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_2 = 15, + /* End FEATURE_IPA_TEST_PER_SIM */ + /* GSI UT channel SW->IPA */ + IPA_HW_Q6_GSI_UT_CONSUMER_PIPE_1 = 16, + /* GSI UT channel IPA->SW */ + IPA_HW_Q6_GSI_UT_PRODUCER_PIPE_1 = 17, + /* GSI UT channel SW->IPA */ + IPA_HW_Q6_GSI_UT_CONSUMER_PIPE_2 = 18, + /* GSI UT channel IPA->SW */ + IPA_HW_Q6_GSI_UT_PRODUCER_PIPE_2 = 19, + + IPA_HW_Q6_PIPE_TOTAL +}; + +/* System Bam Endpoints between Q6 & IPA */ +enum ipa_hw_q6_gsi_ev_e { /* In Sdx24 0..11 */ + /* DL Pipe IPA->Q6 */ + IPA_HW_Q6_DL_PRODUCER_PIPE_GSI_EV = 0, + /* UL Pipe IPA->Q6 */ + IPA_HW_Q6_UL_PRODUCER_PIPE_GSI_EV = 1, + /* DL Pipe Q6->IPA */ + //IPA_HW_Q6_DL_CONSUMER_PIPE_GSI_EV = 2, + /* CTL Pipe Q6->IPA */ + //IPA_HW_Q6_CTL_CONSUMER_PIPE_GSI_EV = 3, + /* Q6 -> IPA, LTE DL Optimized path */ + //IPA_HW_Q6_LTE_DL_CONSUMER_PIPE_GSI_EV = 4, + /* LWA DL(Wifi to Q6) */ + //IPA_HW_Q6_LWA_DL_PRODUCER_PIPE_GSI_EV = 5, + /* Diag status pipe IPA->Q6 */ + //IPA_HW_Q6_DIAG_STATUS_PRODUCER_PIPE_GSI_EV = 6, + /* Used only when FEATURE_IPA_TEST_PER_SIM is ON */ + /* SIM Pipe IPA->Sim */ + IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_0_GSI_EV = 2, + /* SIM Pipe Sim->IPA */ + IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_1_GSI_EV = 3, + /* SIM Pipe Sim->IPA */ + IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_2_GSI_EV = 4, + /* SIM Pipe Sim->IPA */ + IPA_HW_Q6_SIM_1_GSI_EV = 5, + IPA_HW_Q6_SIM_2_GSI_EV = 6, + IPA_HW_Q6_SIM_3_GSI_EV = 7, + IPA_HW_Q6_SIM_4_GSI_EV = 8, + + IPA_HW_Q6_PIPE_GSI_EV_TOTAL +}; + +/* + * All the IRQ's supported by the IPA HW. Use this enum to set IRQ_EN + * register and read IRQ_STTS register + */ +enum ipa_hw_irq_e { + IPA_HW_IRQ_GSI_HWP = (1 << 25), + IPA_HW_IRQ_GSI_IPA_IF_TLV_RCVD = (1 << 24), + IPA_HW_IRQ_GSI_EE_IRQ = (1 << 23), + IPA_HW_IRQ_DCMP_ERR = (1 << 22), + IPA_HW_IRQ_HWP_ERR = (1 << 21), + IPA_HW_IRQ_RED_MARKER_ABOVE = (1 << 20), + IPA_HW_IRQ_YELLOW_MARKER_ABOVE = (1 << 19), + IPA_HW_IRQ_RED_MARKER_BELOW = (1 << 18), + IPA_HW_IRQ_YELLOW_MARKER_BELOW = (1 << 17), + IPA_HW_IRQ_BAM_IDLE_IRQ = (1 << 16), + IPA_HW_IRQ_TX_HOLB_DROP = (1 << 15), + IPA_HW_IRQ_TX_SUSPEND = (1 << 14), + IPA_HW_IRQ_PROC_ERR = (1 << 13), + IPA_HW_IRQ_STEP_MODE = (1 << 12), + IPA_HW_IRQ_TX_ERR = (1 << 11), + IPA_HW_IRQ_DEAGGR_ERR = (1 << 10), + IPA_HW_IRQ_RX_ERR = (1 << 9), + IPA_HW_IRQ_PROC_TO_HW_ACK_Q_NOT_EMPTY = (1 << 8), + IPA_HW_IRQ_HWP_RX_CMD_Q_NOT_FULL = (1 << 7), + IPA_HW_IRQ_HWP_IN_Q_NOT_EMPTY = (1 << 6), + IPA_HW_IRQ_HWP_IRQ_3 = (1 << 5), + IPA_HW_IRQ_HWP_IRQ_2 = (1 << 4), + IPA_HW_IRQ_HWP_IRQ_1 = (1 << 3), + IPA_HW_IRQ_HWP_IRQ_0 = (1 << 2), + IPA_HW_IRQ_EOT_COAL = (1 << 1), + IPA_HW_IRQ_BAD_SNOC_ACCESS = (1 << 0), + IPA_HW_IRQ_NONE = 0, + IPA_HW_IRQ_ALL = 0xFFFFFFFF +}; + +/* + * All the IRQ sources supported by the IPA HW. Use this enum to set + * IRQ_SRCS register + */ +enum ipa_hw_irq_srcs_e { + IPA_HW_IRQ_SRCS_PIPE_0 = (1 << IPA_HW_PIPE_ID_0), + IPA_HW_IRQ_SRCS_PIPE_1 = (1 << IPA_HW_PIPE_ID_1), + IPA_HW_IRQ_SRCS_PIPE_2 = (1 << IPA_HW_PIPE_ID_2), + IPA_HW_IRQ_SRCS_PIPE_3 = (1 << IPA_HW_PIPE_ID_3), + IPA_HW_IRQ_SRCS_PIPE_4 = (1 << IPA_HW_PIPE_ID_4), + IPA_HW_IRQ_SRCS_PIPE_5 = (1 << IPA_HW_PIPE_ID_5), + IPA_HW_IRQ_SRCS_PIPE_6 = (1 << IPA_HW_PIPE_ID_6), + IPA_HW_IRQ_SRCS_PIPE_7 = (1 << IPA_HW_PIPE_ID_7), + IPA_HW_IRQ_SRCS_PIPE_8 = (1 << IPA_HW_PIPE_ID_8), + IPA_HW_IRQ_SRCS_PIPE_9 = (1 << IPA_HW_PIPE_ID_9), + IPA_HW_IRQ_SRCS_PIPE_10 = (1 << IPA_HW_PIPE_ID_10), + IPA_HW_IRQ_SRCS_PIPE_11 = (1 << IPA_HW_PIPE_ID_11), + IPA_HW_IRQ_SRCS_PIPE_12 = (1 << IPA_HW_PIPE_ID_12), + IPA_HW_IRQ_SRCS_PIPE_13 = (1 << IPA_HW_PIPE_ID_13), + IPA_HW_IRQ_SRCS_PIPE_14 = (1 << IPA_HW_PIPE_ID_14), + IPA_HW_IRQ_SRCS_PIPE_15 = (1 << IPA_HW_PIPE_ID_15), + IPA_HW_IRQ_SRCS_PIPE_16 = (1 << IPA_HW_PIPE_ID_16), + IPA_HW_IRQ_SRCS_PIPE_17 = (1 << IPA_HW_PIPE_ID_17), + IPA_HW_IRQ_SRCS_PIPE_18 = (1 << IPA_HW_PIPE_ID_18), + IPA_HW_IRQ_SRCS_PIPE_19 = (1 << IPA_HW_PIPE_ID_19), + IPA_HW_IRQ_SRCS_PIPE_20 = (1 << IPA_HW_PIPE_ID_20), + IPA_HW_IRQ_SRCS_PIPE_21 = (1 << IPA_HW_PIPE_ID_21), + IPA_HW_IRQ_SRCS_PIPE_22 = (1 << IPA_HW_PIPE_ID_22), + IPA_HW_IRQ_SRCS_NONE = 0, + IPA_HW_IRQ_SRCS_ALL = 0xFFFFFFFF, +}; + +/* + * Total number of channel contexts that need to be saved for APPS + */ +#define IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_A7 20 + +/* + * Total number of channel contexts that need to be saved for UC + */ +#define IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_UC 2 + +/* + * Total number of event ring contexts that need to be saved for APPS + */ +#define IPA_HW_REG_SAVE_GSI_NUM_EVT_CNTXT_A7 19 + +/* + * Total number of event ring contexts that need to be saved for UC + */ +#define IPA_HW_REG_SAVE_GSI_NUM_EVT_CNTXT_UC 1 + +/* + * Total number of endpoints for which ipa_reg_save.pipes[endp_number] + * are not saved by default (only if ipa_cfg.gen.full_reg_trace = + * true) There is no extra endpoints in Stingray + */ +#define IPA_HW_REG_SAVE_NUM_ENDP_EXTRA 0 + +/* + * Total number of endpoints for which ipa_reg_save.pipes[endp_number] + * are always saved + */ +#define IPA_HW_REG_SAVE_NUM_ACTIVE_PIPES IPA_HW_PIPE_ID_MAX + +/* + * SHRAM Bytes per ch + */ +#define IPA_REG_SAVE_BYTES_PER_CHNL_SHRAM 12 + +/* + * Total number of rx splt cmdq's see: + * ipa_rx_splt_cmdq_n_cmd[IPA_RX_SPLT_CMDQ_MAX] + */ +#define IPA_RX_SPLT_CMDQ_MAX 4 + +/* + * Although not necessary for the numbers below, the use of round_up + * is so that future developers know that these particular constants + * have to be a multiple of four bytes, because the IPA memory reads + * that they drive are always 32 bits... + */ +#define IPA_IU_ADDR 0x000A0000 +#define IPA_IU_SIZE round_up(40704, sizeof(u32)) + +#define IPA_SRAM_ADDR 0x00050000 +#define IPA_SRAM_SIZE round_up(19232, sizeof(u32)) + +#define IPA_MBOX_ADDR 0x000C2000 +#define IPA_MBOX_SIZE round_up(256, sizeof(u32)) + +#define IPA_HRAM_ADDR 0x00060000 +#define IPA_HRAM_SIZE round_up(47536, sizeof(u32)) + +#define IPA_SEQ_ADDR 0x00081000 +#define IPA_SEQ_SIZE round_up(768, sizeof(u32)) + +#define IPA_GSI_ADDR 0x00006000 +#define IPA_GSI_SIZE round_up(5376, sizeof(u32)) + +/* + * Macro to define a particular register cfg entry for all pipe + * indexed register + */ +#define IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(reg_name, var_name) \ + ({ GEN_1xVECTOR_REG_OFST(reg_name, 0), \ + (u32 *)&ipa_reg_save.ipa.pipes[0].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 1), \ + (u32 *)&ipa_reg_save.ipa.pipes[1].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 2), \ + (u32 *)&ipa_reg_save.ipa.pipes[2].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 3), \ + (u32 *)&ipa_reg_save.ipa.pipes[3].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 4), \ + (u32 *)&ipa_reg_save.ipa.pipes[4].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 5), \ + (u32 *)&ipa_reg_save.ipa.pipes[5].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 6), \ + (u32 *)&ipa_reg_save.ipa.pipes[6].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 7), \ + (u32 *)&ipa_reg_save.ipa.pipes[7].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 8), \ + (u32 *)&ipa_reg_save.ipa.pipes[8].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 9), \ + (u32 *)&ipa_reg_save.ipa.pipes[9].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 10), \ + (u32 *)&ipa_reg_save.ipa.pipes[10].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 11), \ + (u32 *)&ipa_reg_save.ipa.pipes[11].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 12), \ + (u32 *)&ipa_reg_save.ipa.pipes[12].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 13), \ + (u32 *)&ipa_reg_save.ipa.pipes[13].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 14), \ + (u32 *)&ipa_reg_save.ipa.pipes[14].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 15), \ + (u32 *)&ipa_reg_save.ipa.pipes[15].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 16), \ + (u32 *)&ipa_reg_save.ipa.pipes[16].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 17), \ + (u32 *)&ipa_reg_save.ipa.pipes[17].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 18), \ + (u32 *)&ipa_reg_save.ipa.pipes[18].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 19), \ + (u32 *)&ipa_reg_save.ipa.pipes[19].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 20), \ + (u32 *)&ipa_reg_save.ipa.pipes[20].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 21), \ + (u32 *)&ipa_reg_save.ipa.pipes[21].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 22), \ + (u32 *)&ipa_reg_save.ipa.pipes[22].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 23), \ + (u32 *)&ipa_reg_save.ipa.pipes[23].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 24), \ + (u32 *)&ipa_reg_save.ipa.pipes[24].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 25), \ + (u32 *)&ipa_reg_save.ipa.pipes[25].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 26), \ + (u32 *)&ipa_reg_save.ipa.pipes[26].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 27), \ + (u32 *)&ipa_reg_save.ipa.pipes[27].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 28), \ + (u32 *)&ipa_reg_save.ipa.pipes[28].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 29), \ + (u32 *)&ipa_reg_save.ipa.pipes[29].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 30), \ + (u32 *)&ipa_reg_save.ipa.pipes[30].endp.var_name }) + +/* + * Macro to define a particular register cfg entry for the remaining + * pipe indexed register. In Stingray case we don't have extra + * endpoints so it is intentially empty + */ +#define IPA_HW_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(REG_NAME, VAR_NAME) \ + { 0, 0 } + +/* + * Macro to set the active flag for all active pipe indexed register + * In Stingray case we don't have extra endpoints so it is intentially + * empty + */ +#define IPA_HW_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA_ACTIVE() \ + do { \ + } while (0) + +#endif /* #if !defined(_IPA_HW_COMMON_EX_H_) */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.5/ipa_hwio.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.5/ipa_hwio.h new file mode 100644 index 0000000000..c3a884b9e2 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.5/ipa_hwio.h @@ -0,0 +1,10895 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ +#if !defined(_IPA_HWIO_H_) +#define _IPA_HWIO_H_ +/* + * + * HWIO register definitions to follow: + * + */ +#define IPA_GSI_TOP_GSI_REG_BASE (IPA_0_IPA_WRAPPER_BASE + 0x00004000) +#define IPA_GSI_TOP_GSI_REG_BASE_PHYS (IPA_0_IPA_WRAPPER_BASE_PHYS + \ + 0x00004000) +#define IPA_GSI_TOP_GSI_REG_BASE_OFFS 0x00004000 +#define HWIO_IPA_GSI_TOP_GSI_CFG_ADDR (IPA_GSI_TOP_GSI_REG_BASE + \ + 0x00000000) +#define HWIO_IPA_GSI_TOP_GSI_CFG_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + \ + 0x00000000) +#define HWIO_IPA_GSI_TOP_GSI_CFG_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + \ + 0x00000000) +#define HWIO_IPA_GSI_TOP_GSI_CFG_RMSK 0xf3f +#define HWIO_IPA_GSI_TOP_GSI_CFG_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_CFG_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_CFG_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_CFG_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_CFG_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_CFG_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_CFG_OUT(v) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_CFG_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_CFG_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_CFG_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_CFG_IN) +#define HWIO_IPA_GSI_TOP_GSI_CFG_SLEEP_CLK_DIV_BMSK 0xf00 +#define HWIO_IPA_GSI_TOP_GSI_CFG_SLEEP_CLK_DIV_SHFT 0x8 +#define HWIO_IPA_GSI_TOP_GSI_CFG_BP_MTRIX_DISABLE_BMSK 0x20 +#define HWIO_IPA_GSI_TOP_GSI_CFG_BP_MTRIX_DISABLE_SHFT 0x5 +#define HWIO_IPA_GSI_TOP_GSI_CFG_GSI_PWR_CLPS_BMSK 0x10 +#define HWIO_IPA_GSI_TOP_GSI_CFG_GSI_PWR_CLPS_SHFT 0x4 +#define HWIO_IPA_GSI_TOP_GSI_CFG_UC_IS_MCS_BMSK 0x8 +#define HWIO_IPA_GSI_TOP_GSI_CFG_UC_IS_MCS_SHFT 0x3 +#define HWIO_IPA_GSI_TOP_GSI_CFG_DOUBLE_MCS_CLK_FREQ_BMSK 0x4 +#define HWIO_IPA_GSI_TOP_GSI_CFG_DOUBLE_MCS_CLK_FREQ_SHFT 0x2 +#define HWIO_IPA_GSI_TOP_GSI_CFG_MCS_ENABLE_BMSK 0x2 +#define HWIO_IPA_GSI_TOP_GSI_CFG_MCS_ENABLE_SHFT 0x1 +#define HWIO_IPA_GSI_TOP_GSI_CFG_GSI_ENABLE_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_GSI_CFG_GSI_ENABLE_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_MCS_CODE_VER_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000008) +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_MCS_CODE_VER_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000008) +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_MCS_CODE_VER_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000008) +#define HWIO_IPA_GSI_TOP_GSI_ZEROS_ADDR (IPA_GSI_TOP_GSI_REG_BASE + \ + 0x00000010) +#define HWIO_IPA_GSI_TOP_GSI_ZEROS_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + \ + 0x00000010) +#define HWIO_IPA_GSI_TOP_GSI_ZEROS_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + \ + 0x00000010) +#define HWIO_IPA_GSI_TOP_GSI_PERIPH_BASE_ADDR_LSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000018) +#define HWIO_IPA_GSI_TOP_GSI_PERIPH_BASE_ADDR_LSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000018) +#define HWIO_IPA_GSI_TOP_GSI_PERIPH_BASE_ADDR_LSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000018) +#define HWIO_IPA_GSI_TOP_GSI_PERIPH_BASE_ADDR_MSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000001c) +#define HWIO_IPA_GSI_TOP_GSI_PERIPH_BASE_ADDR_MSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000001c) +#define HWIO_IPA_GSI_TOP_GSI_PERIPH_BASE_ADDR_MSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000001c) +#define HWIO_IPA_GSI_TOP_GSI_PERIPH_PENDING_ADDR (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x00000020) +#define HWIO_IPA_GSI_TOP_GSI_PERIPH_PENDING_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000020) +#define HWIO_IPA_GSI_TOP_GSI_PERIPH_PENDING_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000020) +#define HWIO_IPA_GSI_TOP_GSI_MOQA_CFG_ADDR (IPA_GSI_TOP_GSI_REG_BASE + \ + 0x00000030) +#define HWIO_IPA_GSI_TOP_GSI_MOQA_CFG_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS \ + + 0x00000030) +#define HWIO_IPA_GSI_TOP_GSI_MOQA_CFG_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS \ + + 0x00000030) +#define HWIO_IPA_GSI_TOP_GSI_REE_CFG_ADDR (IPA_GSI_TOP_GSI_REG_BASE + \ + 0x00000038) +#define HWIO_IPA_GSI_TOP_GSI_REE_CFG_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + \ + 0x00000038) +#define HWIO_IPA_GSI_TOP_GSI_REE_CFG_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + \ + 0x00000038) +#define HWIO_IPA_GSI_TOP_GSI_REE_CFG_RMSK 0xff03 +#define HWIO_IPA_GSI_TOP_GSI_REE_CFG_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_REE_CFG_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_REE_CFG_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_REE_CFG_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_REE_CFG_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_REE_CFG_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_REE_CFG_OUT(v) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_REE_CFG_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_REE_CFG_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_REE_CFG_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_REE_CFG_IN) +#define HWIO_IPA_GSI_TOP_GSI_REE_CFG_MAX_BURST_SIZE_BMSK 0xff00 +#define HWIO_IPA_GSI_TOP_GSI_REE_CFG_MAX_BURST_SIZE_SHFT 0x8 +#define HWIO_IPA_GSI_TOP_GSI_REE_CFG_CHANNEL_EMPTY_INT_ENABLE_BMSK 0x2 +#define HWIO_IPA_GSI_TOP_GSI_REE_CFG_CHANNEL_EMPTY_INT_ENABLE_SHFT 0x1 +#define HWIO_IPA_GSI_TOP_GSI_REE_CFG_MOVE_TO_ESC_CLR_MODE_TRSH_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_GSI_REE_CFG_MOVE_TO_ESC_CLR_MODE_TRSH_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_CGC_CTRL_ADDR (IPA_GSI_TOP_GSI_REG_BASE + \ + 0x00000060) +#define HWIO_IPA_GSI_TOP_GSI_CGC_CTRL_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS \ + + 0x00000060) +#define HWIO_IPA_GSI_TOP_GSI_CGC_CTRL_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS \ + + 0x00000060) +#define HWIO_IPA_GSI_TOP_GSI_MSI_CACHEATTR_ADDR (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x00000080) +#define HWIO_IPA_GSI_TOP_GSI_MSI_CACHEATTR_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000080) +#define HWIO_IPA_GSI_TOP_GSI_MSI_CACHEATTR_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000080) +#define HWIO_IPA_GSI_TOP_GSI_EVENT_CACHEATTR_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000084) +#define HWIO_IPA_GSI_TOP_GSI_EVENT_CACHEATTR_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000084) +#define HWIO_IPA_GSI_TOP_GSI_EVENT_CACHEATTR_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000084) +#define HWIO_IPA_GSI_TOP_GSI_DATA_CACHEATTR_ADDR (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x00000088) +#define HWIO_IPA_GSI_TOP_GSI_DATA_CACHEATTR_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000088) +#define HWIO_IPA_GSI_TOP_GSI_DATA_CACHEATTR_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000088) +#define HWIO_IPA_GSI_TOP_GSI_TRE_CACHEATTR_ADDR (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x00000090) +#define HWIO_IPA_GSI_TOP_GSI_TRE_CACHEATTR_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000090) +#define HWIO_IPA_GSI_TOP_GSI_TRE_CACHEATTR_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000090) +#define HWIO_IPA_GSI_TOP_IC_DISABLE_CHNL_BCK_PRS_LSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000a0) +#define HWIO_IPA_GSI_TOP_IC_DISABLE_CHNL_BCK_PRS_LSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000a0) +#define HWIO_IPA_GSI_TOP_IC_DISABLE_CHNL_BCK_PRS_LSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000a0) +#define HWIO_IPA_GSI_TOP_IC_DISABLE_CHNL_BCK_PRS_MSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000a4) +#define HWIO_IPA_GSI_TOP_IC_DISABLE_CHNL_BCK_PRS_MSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000a4) +#define HWIO_IPA_GSI_TOP_IC_DISABLE_CHNL_BCK_PRS_MSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000a4) +#define HWIO_IPA_GSI_TOP_IC_GEN_EVNT_BCK_PRS_LSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000a8) +#define HWIO_IPA_GSI_TOP_IC_GEN_EVNT_BCK_PRS_LSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000a8) +#define HWIO_IPA_GSI_TOP_IC_GEN_EVNT_BCK_PRS_LSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000a8) +#define HWIO_IPA_GSI_TOP_IC_GEN_EVNT_BCK_PRS_MSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000ac) +#define HWIO_IPA_GSI_TOP_IC_GEN_EVNT_BCK_PRS_MSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000ac) +#define HWIO_IPA_GSI_TOP_IC_GEN_EVNT_BCK_PRS_MSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000ac) +#define HWIO_IPA_GSI_TOP_IC_GEN_INT_BCK_PRS_LSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000b0) +#define HWIO_IPA_GSI_TOP_IC_GEN_INT_BCK_PRS_LSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000b0) +#define HWIO_IPA_GSI_TOP_IC_GEN_INT_BCK_PRS_LSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000b0) +#define HWIO_IPA_GSI_TOP_IC_GEN_INT_BCK_PRS_MSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000b4) +#define HWIO_IPA_GSI_TOP_IC_GEN_INT_BCK_PRS_MSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000b4) +#define HWIO_IPA_GSI_TOP_IC_GEN_INT_BCK_PRS_MSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000b4) +#define HWIO_IPA_GSI_TOP_IC_STOP_INT_MOD_BCK_PRS_LSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000b8) +#define HWIO_IPA_GSI_TOP_IC_STOP_INT_MOD_BCK_PRS_LSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000b8) +#define HWIO_IPA_GSI_TOP_IC_STOP_INT_MOD_BCK_PRS_LSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000b8) +#define HWIO_IPA_GSI_TOP_IC_STOP_INT_MOD_BCK_PRS_MSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000bc) +#define HWIO_IPA_GSI_TOP_IC_STOP_INT_MOD_BCK_PRS_MSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000bc) +#define HWIO_IPA_GSI_TOP_IC_STOP_INT_MOD_BCK_PRS_MSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000bc) +#define HWIO_IPA_GSI_TOP_IC_PROCESS_DESC_BCK_PRS_LSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000c0) +#define HWIO_IPA_GSI_TOP_IC_PROCESS_DESC_BCK_PRS_LSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000c0) +#define HWIO_IPA_GSI_TOP_IC_PROCESS_DESC_BCK_PRS_LSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000c0) +#define HWIO_IPA_GSI_TOP_IC_PROCESS_DESC_BCK_PRS_MSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000c4) +#define HWIO_IPA_GSI_TOP_IC_PROCESS_DESC_BCK_PRS_MSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000c4) +#define HWIO_IPA_GSI_TOP_IC_PROCESS_DESC_BCK_PRS_MSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000c4) +#define HWIO_IPA_GSI_TOP_IC_TLV_STOP_BCK_PRS_LSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000c8) +#define HWIO_IPA_GSI_TOP_IC_TLV_STOP_BCK_PRS_LSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000c8) +#define HWIO_IPA_GSI_TOP_IC_TLV_STOP_BCK_PRS_LSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000c8) +#define HWIO_IPA_GSI_TOP_IC_TLV_STOP_BCK_PRS_MSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000cc) +#define HWIO_IPA_GSI_TOP_IC_TLV_STOP_BCK_PRS_MSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000cc) +#define HWIO_IPA_GSI_TOP_IC_TLV_STOP_BCK_PRS_MSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000cc) +#define HWIO_IPA_GSI_TOP_IC_TLV_RESET_BCK_PRS_LSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000d0) +#define HWIO_IPA_GSI_TOP_IC_TLV_RESET_BCK_PRS_LSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000d0) +#define HWIO_IPA_GSI_TOP_IC_TLV_RESET_BCK_PRS_LSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000d0) +#define HWIO_IPA_GSI_TOP_IC_TLV_RESET_BCK_PRS_MSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000d4) +#define HWIO_IPA_GSI_TOP_IC_TLV_RESET_BCK_PRS_MSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000d4) +#define HWIO_IPA_GSI_TOP_IC_TLV_RESET_BCK_PRS_MSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000d4) +#define HWIO_IPA_GSI_TOP_IC_RGSTR_TIMER_BCK_PRS_LSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000d8) +#define HWIO_IPA_GSI_TOP_IC_RGSTR_TIMER_BCK_PRS_LSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000d8) +#define HWIO_IPA_GSI_TOP_IC_RGSTR_TIMER_BCK_PRS_LSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000d8) +#define HWIO_IPA_GSI_TOP_IC_RGSTR_TIMER_BCK_PRS_MSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000dc) +#define HWIO_IPA_GSI_TOP_IC_RGSTR_TIMER_BCK_PRS_MSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000dc) +#define HWIO_IPA_GSI_TOP_IC_RGSTR_TIMER_BCK_PRS_MSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000dc) +#define HWIO_IPA_GSI_TOP_IC_READ_BCK_PRS_LSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000e0) +#define HWIO_IPA_GSI_TOP_IC_READ_BCK_PRS_LSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000e0) +#define HWIO_IPA_GSI_TOP_IC_READ_BCK_PRS_LSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000e0) +#define HWIO_IPA_GSI_TOP_IC_READ_BCK_PRS_MSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000e4) +#define HWIO_IPA_GSI_TOP_IC_READ_BCK_PRS_MSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000e4) +#define HWIO_IPA_GSI_TOP_IC_READ_BCK_PRS_MSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000e4) +#define HWIO_IPA_GSI_TOP_IC_WRITE_BCK_PRS_LSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000e8) +#define HWIO_IPA_GSI_TOP_IC_WRITE_BCK_PRS_LSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000e8) +#define HWIO_IPA_GSI_TOP_IC_WRITE_BCK_PRS_LSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000e8) +#define HWIO_IPA_GSI_TOP_IC_WRITE_BCK_PRS_MSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000ec) +#define HWIO_IPA_GSI_TOP_IC_WRITE_BCK_PRS_MSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000ec) +#define HWIO_IPA_GSI_TOP_IC_WRITE_BCK_PRS_MSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000ec) +#define HWIO_IPA_GSI_TOP_IC_UCONTROLLER_GPR_BCK_PRS_LSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000f0) +#define HWIO_IPA_GSI_TOP_IC_UCONTROLLER_GPR_BCK_PRS_LSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000f0) +#define HWIO_IPA_GSI_TOP_IC_UCONTROLLER_GPR_BCK_PRS_LSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000f0) +#define HWIO_IPA_GSI_TOP_IC_UCONTROLLER_GPR_BCK_PRS_MSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000f4) +#define HWIO_IPA_GSI_TOP_IC_UCONTROLLER_GPR_BCK_PRS_MSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000f4) +#define HWIO_IPA_GSI_TOP_IC_UCONTROLLER_GPR_BCK_PRS_MSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000f4) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_REE_ADDR (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x00000100) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_REE_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000100) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_REE_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000100) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_EVT_ENG_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000104) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_EVT_ENG_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000104) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_EVT_ENG_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000104) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_INT_ENG_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000108) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_INT_ENG_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000108) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_INT_ENG_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000108) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_CSR_ADDR (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x0000010c) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_CSR_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000010c) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_CSR_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000010c) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_TLV_ENG_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000110) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_TLV_ENG_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000110) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_TLV_ENG_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000110) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_TIMER_ENG_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000114) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_TIMER_ENG_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000114) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_TIMER_ENG_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000114) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_DB_ENG_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000118) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_DB_ENG_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000118) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_DB_ENG_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000118) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_RD_WR_ENG_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000011c) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_RD_WR_ENG_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000011c) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_RD_WR_ENG_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000011c) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_UCONTROLLER_ENG_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000120) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_UCONTROLLER_ENG_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000120) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_UCONTROLLER_ENG_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000120) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_SDMA_ADDR (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x00000124) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_SDMA_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000124) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_SDMA_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000124) +#define HWIO_IPA_GSI_TOP_GSI_SDMA_CFG_ADDR (IPA_GSI_TOP_GSI_REG_BASE + \ + 0x0000003c) +#define HWIO_IPA_GSI_TOP_GSI_SDMA_CFG_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS \ + + 0x0000003c) +#define HWIO_IPA_GSI_TOP_GSI_SDMA_CFG_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS \ + + 0x0000003c) +#define HWIO_IPA_GSI_TOP_GSI_SDMA_CACHEATTR_ADDR (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x00000094) +#define HWIO_IPA_GSI_TOP_GSI_SDMA_CACHEATTR_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000094) +#define HWIO_IPA_GSI_TOP_GSI_SDMA_CACHEATTR_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000094) +#define HWIO_IPA_GSI_TOP_GSI_SDMA_SG_IOVEC_LSB_n_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000140 + 0x8 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_SDMA_SG_IOVEC_LSB_n_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000140 + 0x8 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_SDMA_SG_IOVEC_LSB_n_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000140 + 0x8 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_SDMA_SG_IOVEC_MSB_n_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000144 + 0x8 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_SDMA_SG_IOVEC_MSB_n_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000144 + 0x8 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_SDMA_SG_IOVEC_MSB_n_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000144 + 0x8 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000300 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000300 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000300 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000200) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000200) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000200) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_RMSK 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_IN \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_INM(m) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_OUT(v) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_OUTM(m, \ + v) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_IN) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_SHRAM_PTR_BMSK \ + 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_SHRAM_PTR_SHFT \ + 0x0 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000204) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000204) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000204) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_RMSK 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_IN \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_INM(m) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_OUT(v) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_OUTM(m, \ + v) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_IN) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_SHRAM_PTR_BMSK \ + 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_SHRAM_PTR_SHFT \ + 0x0 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000208) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000208) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000208) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_RMSK 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_IN \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_INM(m) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_OUTM(m, \ + v) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_IN) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_SHRAM_PTR_BMSK \ + 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_SHRAM_PTR_SHFT \ + 0x0 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000020c) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000020c) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000020c) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_RMSK 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_IN \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_INM(m) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_OUTM(m, \ + v) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_IN) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_SHRAM_PTR_BMSK \ + 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_SHRAM_PTR_SHFT \ + 0x0 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000240) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000240) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000240) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_RMSK 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_IN \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_INM(m) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_OUTM(m, \ + v) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_IN) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_SHRAM_PTR_BMSK \ + 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_SHRAM_PTR_SHFT \ + 0x0 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000244) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000244) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000244) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_RMSK 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_IN \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_INM(m) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_OUTM(m, \ + v) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_IN) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_SHRAM_PTR_BMSK \ + 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_SHRAM_PTR_SHFT \ + 0x0 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000248) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000248) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000248) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000024c) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000024c) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000024c) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000250) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000250) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000250) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000254) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000254) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000254) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000258) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000258) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000258) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000025c) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000025c) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000025c) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000260) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000260) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000260) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000264) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000264) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000264) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000400) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000400) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000400) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_OUT(v) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_OUTM(m, \ + v) out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_IN) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_IRAM_PTR_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000404) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000404) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000404) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_OUT(v) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_OUTM(m, \ + v) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_IN) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_IRAM_PTR_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TLV_CH_NOT_FULL_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000408) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TLV_CH_NOT_FULL_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000408) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TLV_CH_NOT_FULL_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000408) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_ADDR (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x00000418) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000418) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000418) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_OUT(v) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_IN) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_IRAM_PTR_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_ADDR (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x0000041c) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000041c) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000041c) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_OUT(v) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_IN) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_IRAM_PTR_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000420) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000420) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000420) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_OUT(v) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_OUTM(m, \ + v) out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_IN) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_IRAM_PTR_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000424) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000424) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000424) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_OUT(v) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_OUTM(m, \ + v) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_IN) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_IRAM_PTR_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000428) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000428) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000428) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_OUT(v) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_OUTM(m, \ + v) out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_IN) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_IRAM_PTR_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000042c) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000042c) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000042c) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_OUT(v) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_OUTM(m, \ + v) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_IN) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_IRAM_PTR_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000430) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000430) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000430) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000434) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000434) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000434) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000438) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000438) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000438) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000043c) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000043c) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000043c) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_OUT(v) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_OUTM(m, \ + v) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_IN) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_IRAM_PTR_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000440) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000440) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000440) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_OUT(v) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_OUTM(m, \ + v) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_IN) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_IRAM_PTR_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000444) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000444) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000444) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_OUT(v) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_OUTM(m, \ + v) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_IN) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_IRAM_PTR_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000448) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000448) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000448) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_OUT(v) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_OUTM(m, \ + v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_IN) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_IRAM_PTR_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPPED_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000044c) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPPED_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000044c) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPPED_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000044c) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPPED_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPPED_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPPED_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPPED_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPPED_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPPED_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPPED_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPPED_OUT(v) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPPED_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPPED_OUTM(m, \ + v) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPPED_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPPED_IN) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPPED_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPPED_IRAM_PTR_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_SDMA_INT_n_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000450 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_SDMA_INT_n_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000450 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_SDMA_INT_n_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000450 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_ADDR(n) (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x0001b000 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001b000 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001b000 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_MAXn 8191 +#define HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_INI(n) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_ADDR(n), \ + HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_INMI(n, mask) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_ADDR(n), \ + mask) +#define HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_OUTI(n, val) \ + out_dword( \ + HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_ADDR(n), \ + val) +#define HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_OUTMI(n, mask, \ + val) out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_ADDR( \ + n), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_INI(n)) +#define HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_INST_BYTE_3_BMSK 0xff000000 +#define HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_INST_BYTE_3_SHFT 0x18 +#define HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_INST_BYTE_2_BMSK 0xff0000 +#define HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_INST_BYTE_2_SHFT 0x10 +#define HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_INST_BYTE_1_BMSK 0xff00 +#define HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_INST_BYTE_1_SHFT 0x8 +#define HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_INST_BYTE_0_BMSK 0xff +#define HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_INST_BYTE_0_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_n_ADDR(n) (IPA_GSI_TOP_GSI_REG_BASE + \ + 0x00002000 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_n_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00002000 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_n_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00002000 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_n_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_n_MAXn 1343 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_n_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_n_INI(n) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_n_ADDR(n), \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_n_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_n_ADDR(n), \ + mask) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_n_OUTI(n, val) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_n_ADDR(n), \ + val) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_n_OUTMI(n, mask, \ + val) out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_n_ADDR( \ + n), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_n_INI(n)) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_n_SHRAM_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_n_SHRAM_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00003800 + 0x80 * (n) + 0x4 * \ + (k)) +#define HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00003800 + 0x80 * (n) + \ + 0x4 * \ + (k)) +#define HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00003800 + 0x80 * (n) + \ + 0x4 * \ + (k)) +#define HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_RMSK 0x3f +#define HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_MAXn 2 +#define HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_MAXk 22 +#define HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_INI2(n, \ + k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_ADDR( \ + n, \ + k), \ + HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_INMI2(n, k, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_ADDR(n, k), \ + mask) +#define HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_OUTI2(n, k, \ + val) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_ADDR(n, \ + k), \ + val) +#define HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_ADDR(n, k), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_INI2(n, k)) +#define HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_VALID_BMSK 0x20 +#define HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_VALID_SHFT 0x5 +#define HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_PHY_CH_BMSK 0x1f +#define HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_PHY_CH_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_ADDR (IPA_GSI_TOP_GSI_REG_BASE + \ + 0x00001000) +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001000) +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001000) +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_RMSK 0xf00ff +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_OUT(v) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_IN) +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_HW_EVENTS_SEL_BMSK 0xf0000 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_HW_EVENTS_SEL_SHFT 0x10 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_BMSK 0xff +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_ZEROS_FVAL 0x0 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MCS_0_FVAL 0x1 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MCS_1_FVAL 0x2 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MCS_2_FVAL 0x3 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MCS_3_FVAL 0x4 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MCS_4_FVAL 0x5 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_DB_ENG_FVAL 0x9 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_0_FVAL 0xb +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_1_FVAL 0xc +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_2_FVAL 0xd +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_3_FVAL 0xe +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_4_FVAL 0xf +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_5_FVAL 0x10 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_6_FVAL 0x11 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_7_FVAL 0x12 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_EVE_0_FVAL 0x13 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_EVE_1_FVAL 0x14 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_EVE_2_FVAL 0x15 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_EVE_3_FVAL 0x16 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_EVE_4_FVAL 0x17 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_EVE_5_FVAL 0x18 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IE_0_FVAL 0x1b +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IE_1_FVAL 0x1c +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IE_2_FVAL 0x1d +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IC_0_FVAL 0x1f +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IC_1_FVAL 0x20 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IC_2_FVAL 0x21 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IC_3_FVAL 0x22 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IC_4_FVAL 0x23 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MOQA_0_FVAL 0x27 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MOQA_1_FVAL 0x28 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MOQA_2_FVAL 0x29 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MOQA_3_FVAL 0x2a +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_TMR_0_FVAL 0x2b +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_TMR_1_FVAL 0x2c +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_TMR_2_FVAL 0x2d +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_TMR_3_FVAL 0x2e +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_RD_WR_0_FVAL \ + 0x33 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_RD_WR_1_FVAL \ + 0x34 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_RD_WR_2_FVAL \ + 0x35 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_RD_WR_3_FVAL \ + 0x36 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_CSR_FVAL 0x3a +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_SDMA_0_FVAL 0x3c +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_SMDA_1_FVAL 0x3d +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_CSR_1_FVAL 0x3e +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_CSR_2_FVAL 0x3f +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MCS_5_FVAL 0x40 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IC_5_FVAL 0x41 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_CSR_3_FVAL 0x42 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_TLV_0_FVAL 0x43 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_8_FVAL 0x44 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_REG_ADDR (IPA_GSI_TOP_GSI_REG_BASE + \ + 0x00001008) +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_REG_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001008) +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_REG_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001008) +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_REG_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_REG_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_REG_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_TEST_BUS_REG_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_TEST_BUS_REG_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_REG_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_TEST_BUS_REG_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_REG_GSI_TESTBUS_REG_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_REG_GSI_TESTBUS_REG_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_ADDR (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x00001010) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001010) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001010) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_RMSK 0x1fff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_SDMA_BUSY_BMSK 0x1000 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_SDMA_BUSY_SHFT 0xc +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_IC_BUSY_BMSK 0x800 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_IC_BUSY_SHFT 0xb +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_UC_BUSY_BMSK 0x400 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_UC_BUSY_SHFT 0xa +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_DBG_CNT_BUSY_BMSK 0x200 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_DBG_CNT_BUSY_SHFT 0x9 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_DB_ENG_BUSY_BMSK 0x100 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_DB_ENG_BUSY_SHFT 0x8 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_REE_PWR_CLPS_BUSY_BMSK 0x80 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_REE_PWR_CLPS_BUSY_SHFT 0x7 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_INT_ENG_BUSY_BMSK 0x40 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_INT_ENG_BUSY_SHFT 0x6 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_EV_ENG_BUSY_BMSK 0x20 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_EV_ENG_BUSY_SHFT 0x5 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_RD_WR_BUSY_BMSK 0x10 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_RD_WR_BUSY_SHFT 0x4 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_TIMER_BUSY_BMSK 0x8 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_TIMER_BUSY_SHFT 0x3 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_MCS_BUSY_BMSK 0x4 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_MCS_BUSY_SHFT 0x2 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_REE_BUSY_BMSK 0x2 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_REE_BUSY_SHFT 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_CSR_BUSY_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_CSR_BUSY_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EVENT_PENDING_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00001014) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EVENT_PENDING_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001014) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EVENT_PENDING_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001014) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EVENT_PENDING_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EVENT_PENDING_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EVENT_PENDING_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_EVENT_PENDING_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_EVENT_PENDING_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EVENT_PENDING_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_EVENT_PENDING_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EVENT_PENDING_CHID_BIT_MAP_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EVENT_PENDING_CHID_BIT_MAP_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_TIMER_PENDING_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00001018) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_TIMER_PENDING_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001018) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_TIMER_PENDING_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001018) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_TIMER_PENDING_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_TIMER_PENDING_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_TIMER_PENDING_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_TIMER_PENDING_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_TIMER_PENDING_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_TIMER_PENDING_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_TIMER_PENDING_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_TIMER_PENDING_CHID_BIT_MAP_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_TIMER_PENDING_CHID_BIT_MAP_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000101c) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000101c) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000101c) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_CHID_BIT_MAP_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_CHID_BIT_MAP_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00001200 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001200 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001200 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTERn_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00001240 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTERn_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001240 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTERn_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001240 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTERn_RMSK 0xffff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTERn_MAXn 7 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTERn_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTERn_INI(n) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTERn_ADDR(n), \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTERn_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTERn_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTERn_ADDR(n), \ + mask) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTERn_COUNTER_VALUE_BMSK 0xffff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTERn_COUNTER_VALUE_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00001040) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001040) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001040) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_OUT(v) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_OUTM(m, \ + v) out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_IN) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_IRAM_PTR_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_ADDR (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x00001044) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001044) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001044) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_RMSK 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_OUT(v) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_IN) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_MCS_STALL_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_MCS_STALL_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00001048) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001048) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001048) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG_IRAM_PTR_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_SEL_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00001050) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_SEL_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001050) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_SEL_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001050) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_CLR_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00001058) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_CLR_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001058) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_CLR_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001058) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00001060) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001060) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001060) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_RMSK 0x1ffff01 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_INM(m) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ERR_SAVED_BMSK \ + 0x1000000 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ERR_SAVED_SHFT 0x18 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ERR_MID_BMSK \ + 0xff0000 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ERR_MID_SHFT 0x10 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ERR_TID_BMSK 0xff00 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ERR_TID_SHFT 0x8 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ERR_WRITE_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ERR_WRITE_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_0_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00001064) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_0_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001064) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_0_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001064) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_1_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00001068) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_1_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001068) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_1_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001068) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_2_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000106c) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_2_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000106c) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_2_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000106c) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00001070 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001070 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001070 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_WRITE_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00001080 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_WRITE_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001080 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_WRITE_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001080 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00001100 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001100 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001100 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_MAXn 31 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_INI(n) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_ADDR(n), \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_INMI(n, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_ADDR( \ + n), \ + mask) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_RF_REG_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_RF_REG_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00001400 + 0x80 * (n) + 0x4 * \ + (k)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001400 + 0x80 * (n) + \ + 0x4 * \ + (k)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001400 + 0x80 * (n) + \ + 0x4 * \ + (k)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00001600 + 0x80 * (n) + 0x4 * \ + (k)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001600 + 0x80 * (n) + \ + 0x4 * \ + (k)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001600 + 0x80 * (n) + \ + 0x4 * \ + (k)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_RMSK 0x3f +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_MAXn 3 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_MAXk 19 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_INI2(n, \ + k) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_INMI2(n, k, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_ADDR(n, k), \ + mask) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_VALID_BMSK 0x20 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_VALID_SHFT 0x5 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_PHY_EV_CH_BMSK 0x1f +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_PHY_EV_CH_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SDMA_TRANS_DB_n_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00001800 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SDMA_TRANS_DB_n_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001800 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SDMA_TRANS_DB_n_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001800 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_UC_SRC_IRQ_ADDR (IPA_GSI_TOP_GSI_REG_BASE + \ + 0x00000500) +#define HWIO_IPA_GSI_TOP_GSI_UC_SRC_IRQ_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000500) +#define HWIO_IPA_GSI_TOP_GSI_UC_SRC_IRQ_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000500) +#define HWIO_IPA_GSI_TOP_GSI_UC_SRC_IRQ_MSK_ADDR (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x00000504) +#define HWIO_IPA_GSI_TOP_GSI_UC_SRC_IRQ_MSK_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000504) +#define HWIO_IPA_GSI_TOP_GSI_UC_SRC_IRQ_MSK_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000504) +#define HWIO_IPA_GSI_TOP_GSI_UC_SRC_IRQ_CLR_ADDR (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x00000508) +#define HWIO_IPA_GSI_TOP_GSI_UC_SRC_IRQ_CLR_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000508) +#define HWIO_IPA_GSI_TOP_GSI_UC_SRC_IRQ_CLR_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000508) +#define HWIO_IPA_GSI_TOP_GSI_ACC_ARGS_n_ADDR(n) (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x0000050c + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_ACC_ARGS_n_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000050c + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_ACC_ARGS_n_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000050c + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_ACC_ROUTINE_ADDR (IPA_GSI_TOP_GSI_REG_BASE + \ + 0x00000524) +#define HWIO_IPA_GSI_TOP_GSI_ACC_ROUTINE_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000524) +#define HWIO_IPA_GSI_TOP_GSI_ACC_ROUTINE_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000524) +#define HWIO_IPA_GSI_TOP_GSI_ACC_GO_ADDR (IPA_GSI_TOP_GSI_REG_BASE + \ + 0x00000528) +#define HWIO_IPA_GSI_TOP_GSI_ACC_GO_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + \ + 0x00000528) +#define HWIO_IPA_GSI_TOP_GSI_ACC_GO_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + \ + 0x00000528) +#define HWIO_IPA_GSI_TOP_GSI_ACC_2_UC_MCS_STTS_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000052c) +#define HWIO_IPA_GSI_TOP_GSI_ACC_2_UC_MCS_STTS_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000052c) +#define HWIO_IPA_GSI_TOP_GSI_ACC_2_UC_MCS_STTS_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000052c) +#define HWIO_IPA_GSI_TOP_GSI_ACC_2_UC_MCS_RET_VAL_LSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000530) +#define HWIO_IPA_GSI_TOP_GSI_ACC_2_UC_MCS_RET_VAL_LSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000530) +#define HWIO_IPA_GSI_TOP_GSI_ACC_2_UC_MCS_RET_VAL_LSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000530) +#define HWIO_IPA_GSI_TOP_GSI_ACC_2_UC_MCS_RET_VAL_MSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000534) +#define HWIO_IPA_GSI_TOP_GSI_ACC_2_UC_MCS_RET_VAL_MSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000534) +#define HWIO_IPA_GSI_TOP_GSI_ACC_2_UC_MCS_RET_VAL_MSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000534) +#define HWIO_IPA_GSI_TOP_GSI_IC_2_UC_MCS_VLD_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000538) +#define HWIO_IPA_GSI_TOP_GSI_IC_2_UC_MCS_VLD_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000538) +#define HWIO_IPA_GSI_TOP_GSI_IC_2_UC_MCS_VLD_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000538) +#define HWIO_IPA_GSI_TOP_GSI_IC_2_UC_MCS_PC_ADDR (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x0000053c) +#define HWIO_IPA_GSI_TOP_GSI_IC_2_UC_MCS_PC_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000053c) +#define HWIO_IPA_GSI_TOP_GSI_IC_2_UC_MCS_PC_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000053c) +#define HWIO_IPA_GSI_TOP_GSI_IC_2_UC_MCS_ARGS_n_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000540 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_IC_2_UC_MCS_ARGS_n_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000540 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_IC_2_UC_MCS_ARGS_n_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000540 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_UC_TLV_IN_VLD_ADDR (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x00000558) +#define HWIO_IPA_GSI_TOP_GSI_UC_TLV_IN_VLD_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000558) +#define HWIO_IPA_GSI_TOP_GSI_UC_TLV_IN_VLD_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000558) +#define HWIO_IPA_GSI_TOP_GSI_UC_TLV_IN_ROUTINE_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000055c) +#define HWIO_IPA_GSI_TOP_GSI_UC_TLV_IN_ROUTINE_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000055c) +#define HWIO_IPA_GSI_TOP_GSI_UC_TLV_IN_ROUTINE_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000055c) +#define HWIO_IPA_GSI_TOP_GSI_UC_TLV_IN_ARGS_n_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000560 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_UC_TLV_IN_ARGS_n_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000560 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_UC_TLV_IN_ARGS_n_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000560 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000f000 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000f000 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000f000 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_RMSK 0xfff7ffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_MAXk 22 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_OUTI2(n, k, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_ADDR(n, k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_ADDR(n, k), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_INI2(n, k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_ELEMENT_SIZE_BMSK \ + 0xff000000 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_ELEMENT_SIZE_SHFT 0x18 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_BMSK 0xf00000 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_SHFT 0x14 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_NOT_ALLOCATED_FVAL \ + 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_ALLOCATED_FVAL 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_STARTED_FVAL 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_STOPPED_FVAL 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_STOP_IN_PROC_FVAL \ + 0x4 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_ERROR_FVAL 0xf +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_ERINDEX_BMSK 0x7c000 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_ERINDEX_SHFT 0xe +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_MSB_BMSK \ + 0x2000 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_MSB_SHFT \ + 0xd +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHID_BMSK 0x1f00 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHID_SHFT 0x8 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_EE_BMSK 0xf0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_EE_SHFT 0x4 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_DIR_BMSK 0x8 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_DIR_SHFT 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_DIR_INBOUND_FVAL 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_DIR_OUTBOUND_FVAL \ + 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_BMSK 0x7 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_MHI_FVAL \ + 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_XHCI_FVAL \ + 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_GPI_FVAL \ + 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_XDCI_FVAL \ + 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000f004 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000f004 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000f004 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_RMSK 0xffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_MAXk 22 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_OUTI2(n, k, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_ADDR(n, k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_ADDR(n, k), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_INI2(n, k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_R_LENGTH_BMSK 0xffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_R_LENGTH_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000f008 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000f008 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000f008 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_MAXk 22 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_OUTI2(n, k, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_ADDR(n, k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_ADDR(n, k), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_INI2(n, k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_R_BASE_ADDR_LSBS_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_R_BASE_ADDR_LSBS_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000f00c + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000f00c + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000f00c + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_MAXk 22 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_OUTI2(n, k, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_ADDR(n, k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_ADDR(n, k), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_INI2(n, k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_R_BASE_ADDR_MSBS_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_R_BASE_ADDR_MSBS_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000f010 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000f010 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000f010 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_MAXk 22 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_OUTI2(n, k, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_ADDR(n, k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_ADDR(n, k), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_INI2(n, k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_READ_PTR_LSB_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_READ_PTR_LSB_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000f014 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000f014 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000f014 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_MAXk 22 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_READ_PTR_MSB_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_READ_PTR_MSB_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000f018 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000f018 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000f018 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_MAXk 22 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_WRITE_PTR_LSB_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_WRITE_PTR_LSB_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000f01c + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000f01c + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000f01c + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_MAXk 22 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_WRITE_PTR_MSB_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_WRITE_PTR_MSB_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000f054 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000f054 + 0x4000 * \ + (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000f054 + 0x4000 * \ + (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_RMSK 0xffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_MAXk 22 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_INI2(n, \ + k) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_INMI2(n, k, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_ADDR(n, k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_OUTI2(n, k, \ + val) \ + out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_ADDR(n, k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_OUTMI2(n, \ + k, \ + mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_ADDR(n, k), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_INI2(n, k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_READ_PTR_BMSK \ + 0xffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_READ_PTR_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000f058 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000f058 + 0x4000 * \ + (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000f058 + 0x4000 * \ + (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_RMSK 0xffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_MAXk 22 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_INI2(n, \ + k) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_ADDR(n, \ + k), \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_INMI2(n, k, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_OUTI2(n, k, \ + val) \ + out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_ADDR(n, \ + k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_OUTMI2(n, \ + k, \ + mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_INI2(n, \ + k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_RE_INTR_DB_BMSK \ + 0xffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_RE_INTR_DB_SHFT \ + 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000f05c + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000f05c + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000f05c + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_RMSK 0xff3f0f +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_MAXk 22 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_OUTI2(n, k, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_ADDR(n, k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_INI2(n, k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_EMPTY_LVL_THRSHOLD_BMSK \ + 0xff0000 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_EMPTY_LVL_THRSHOLD_SHFT 0x10 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_PREFETCH_MODE_BMSK 0x3c00 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_PREFETCH_MODE_SHFT 0xa +#define \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_PREFETCH_MODE_ESCAPE_BUF_ONLY_FVAL \ + 0x1 +#define \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_PREFETCH_MODE_SMART_PRE_FETCH_FVAL \ + 0x2 +#define \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_PREFETCH_MODE_FREE_PRE_FETCH_FVAL \ + 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_USE_DB_ENG_BMSK 0x200 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_USE_DB_ENG_SHFT 0x9 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_MAX_PREFETCH_BMSK 0x100 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_MAX_PREFETCH_SHFT 0x8 +#define \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_MAX_PREFETCH_ONE_PREFETCH_SEG_FVAL \ + 0x0 +#define \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_MAX_PREFETCH_TWO_PREFETCH_SEG_FVAL \ + 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_WRR_WEIGHT_BMSK 0xf +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_WRR_WEIGHT_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000f060 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000f060 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000f060 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_MAXk 22 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_INI2(n, \ + k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_ADDR(n, \ + k), \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_INMI2(n, k, \ + mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_ADDR( \ + n, \ + k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_OUTI2(n, k, \ + val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_ADDR(n, \ + k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_ADDR(n, k), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_INI2(n, k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_SCRATCH_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_SCRATCH_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000f064 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000f064 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000f064 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_MAXk 22 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_INI2(n, \ + k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_ADDR(n, \ + k), \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_INMI2(n, k, \ + mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_ADDR( \ + n, \ + k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_OUTI2(n, k, \ + val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_ADDR(n, \ + k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_ADDR(n, k), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_INI2(n, k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_SCRATCH_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_SCRATCH_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000f068 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000f068 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000f068 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_MAXk 22 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_INI2(n, \ + k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_ADDR(n, \ + k), \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_INMI2(n, k, \ + mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_ADDR( \ + n, \ + k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_OUTI2(n, k, \ + val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_ADDR(n, \ + k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_ADDR(n, k), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_INI2(n, k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_SCRATCH_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_SCRATCH_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000f06c + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000f06c + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000f06c + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_MAXk 22 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_INI2(n, \ + k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_ADDR(n, \ + k), \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_INMI2(n, k, \ + mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_ADDR( \ + n, \ + k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_OUTI2(n, k, \ + val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_ADDR(n, \ + k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_ADDR(n, k), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_INI2(n, k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_SCRATCH_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_SCRATCH_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000f070 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000f070 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000f070 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00010000 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00010000 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00010000 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_RMSK 0xfff1ffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_MAXk 19 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_OUTI2(n, k, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_ADDR(n, k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_ADDR( \ + n, \ + k), mask, val, \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_INI2(n, \ + k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_ELEMENT_SIZE_BMSK 0xff000000 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_ELEMENT_SIZE_SHFT 0x18 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_CHSTATE_BMSK 0xf00000 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_CHSTATE_SHFT 0x14 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_CHSTATE_NOT_ALLOCATED_FVAL \ + 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_CHSTATE_ALLOCATED_FVAL 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_INTYPE_BMSK 0x10000 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_INTYPE_SHFT 0x10 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_INTYPE_MSI_FVAL 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_INTYPE_IRQ_FVAL 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_EVCHID_BMSK 0xff00 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_EVCHID_SHFT 0x8 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_EE_BMSK 0xf0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_EE_SHFT 0x4 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_CHTYPE_BMSK 0xf +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_CHTYPE_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_CHTYPE_MHI_EV_FVAL 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_CHTYPE_XHCI_EV_FVAL 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_CHTYPE_GPI_EV_FVAL 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_CHTYPE_XDCI_FVAL 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00010004 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00010004 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00010004 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_RMSK 0xffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_MAXk 19 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_OUTI2(n, k, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_ADDR(n, k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_ADDR( \ + n, \ + k), mask, val, \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_INI2(n, \ + k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_R_LENGTH_BMSK 0xffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_R_LENGTH_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00010008 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00010008 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00010008 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_MAXk 19 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_OUTI2(n, k, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_ADDR(n, k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_ADDR( \ + n, \ + k), mask, val, \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_INI2(n, \ + k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_R_BASE_ADDR_LSBS_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_R_BASE_ADDR_LSBS_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001000c + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001000c + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001000c + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_MAXk 19 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_OUTI2(n, k, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_ADDR(n, k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_ADDR( \ + n, \ + k), mask, val, \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_INI2(n, \ + k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_R_BASE_ADDR_MSBS_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_R_BASE_ADDR_MSBS_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00010010 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00010010 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00010010 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_MAXk 19 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_OUTI2(n, k, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_ADDR(n, k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_ADDR( \ + n, \ + k), mask, val, \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_INI2(n, \ + k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_READ_PTR_LSB_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_READ_PTR_LSB_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00010014 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00010014 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00010014 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_MAXk 19 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_READ_PTR_MSB_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_READ_PTR_MSB_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00010018 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00010018 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00010018 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_MAXk 19 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_WRITE_PTR_LSB_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_WRITE_PTR_LSB_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001001c + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001001c + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001001c + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_MAXk 19 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_WRITE_PTR_MSB_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_WRITE_PTR_MSB_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00010020 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00010020 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00010020 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_MAXk 19 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_OUTI2(n, k, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_ADDR(n, k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_ADDR( \ + n, \ + k), mask, val, \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_INI2(n, \ + k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_INT_MOD_CNT_BMSK 0xff000000 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_INT_MOD_CNT_SHFT 0x18 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_INT_MODC_BMSK 0xff0000 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_INT_MODC_SHFT 0x10 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_INT_MODT_BMSK 0xffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_INT_MODT_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00010024 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00010024 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00010024 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_MAXk 19 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_OUTI2(n, k, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_ADDR(n, k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_ADDR( \ + n, \ + k), mask, val, \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_INI2(n, \ + k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_INTVEC_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_INTVEC_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00010028 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00010028 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00010028 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_MAXk 19 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_OUTI2(n, k, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_ADDR(n, k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_ADDR(n, k), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_INI2(n, k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_MSI_ADDR_LSB_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_MSI_ADDR_LSB_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001002c + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001002c + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001002c + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_MAXk 19 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_OUTI2(n, k, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_ADDR(n, k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_ADDR(n, k), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_INI2(n, k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_MSI_ADDR_MSB_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_MSI_ADDR_MSB_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00010030 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00010030 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00010030 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_MAXk 19 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_OUTI2(n, k, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_ADDR(n, k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_ADDR(n, k), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_INI2(n, k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_RP_UPDATE_ADDR_LSB_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_RP_UPDATE_ADDR_LSB_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00010034 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00010034 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00010034 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_MAXk 19 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_OUTI2(n, k, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_ADDR(n, k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_ADDR(n, k), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_INI2(n, k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_RP_UPDATE_ADDR_MSB_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_RP_UPDATE_ADDR_MSB_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00010048 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00010048 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00010048 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_MAXk 19 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_INMI2(n, k, \ + mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_ADDR( \ + n, \ + k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_OUTI2(n, k, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_ADDR(n, k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_ADDR(n, k), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_INI2(n, k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_SCRATCH_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_SCRATCH_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001004c + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001004c + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001004c + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_MAXk 19 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_INMI2(n, k, \ + mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_ADDR( \ + n, \ + k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_OUTI2(n, k, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_ADDR(n, k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_ADDR(n, k), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_INI2(n, k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_SCRATCH_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_SCRATCH_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_0_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00011000 + 0x4000 * (n) + \ + 0x8 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_0_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00011000 + 0x4000 * \ + (n) + \ + 0x8 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_0_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00011000 + 0x4000 * \ + (n) + \ + 0x8 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_1_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00011004 + 0x4000 * (n) + \ + 0x8 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_1_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00011004 + 0x4000 * \ + (n) + \ + 0x8 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_1_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00011004 + 0x4000 * \ + (n) + \ + 0x8 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_DOORBELL_0_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00011100 + 0x4000 * (n) + \ + 0x8 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_DOORBELL_0_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00011100 + 0x4000 * \ + (n) + \ + 0x8 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_DOORBELL_0_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00011100 + 0x4000 * \ + (n) + \ + 0x8 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_DOORBELL_1_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00011104 + 0x4000 * (n) + \ + 0x8 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_DOORBELL_1_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00011104 + 0x4000 * \ + (n) + \ + 0x8 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_DOORBELL_1_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00011104 + 0x4000 * \ + (n) + \ + 0x8 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_STATUS_ADDR(n) (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x00012000 + 0x4000 * \ + (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_STATUS_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00012000 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_STATUS_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00012000 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_STATUS_RMSK 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_STATUS_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_STATUS_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_STATUS_INI(n) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_STATUS_ADDR(n), \ + HWIO_IPA_GSI_TOP_EE_n_GSI_STATUS_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_STATUS_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_STATUS_ADDR(n), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_STATUS_ENABLED_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_STATUS_ENABLED_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_CMD_ADDR(n) (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x00012008 + 0x4000 * \ + (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_CMD_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00012008 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_CMD_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00012008 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_CMD_ADDR(n) (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x00012010 + 0x4000 * \ + (n)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_CMD_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00012010 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_CMD_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00012010 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_EE_GENERIC_CMD_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00012018 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_EE_GENERIC_CMD_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00012018 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_EE_GENERIC_CMD_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00012018 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_0_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00012038 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_0_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00012038 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_0_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00012038 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_1_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001203c + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_1_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001203c + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_1_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001203c + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_2_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00012040 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_2_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00012040 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_2_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00012040 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_SW_VERSION_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00012044 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_SW_VERSION_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00012044 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_SW_VERSION_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00012044 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_MCS_CODE_VER_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00012048 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_MCS_CODE_VER_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00012048 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_MCS_CODE_VER_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00012048 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_3_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001204c + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_3_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001204c + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_3_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001204c + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00012080 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00012080 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00012080 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_RMSK 0x7f +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_INI(n) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_ADDR(n), \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_ADDR(n), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_GENERAL_BMSK 0x40 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_GENERAL_SHFT 0x6 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_INTER_EE_EV_CTRL_BMSK 0x20 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_INTER_EE_EV_CTRL_SHFT 0x5 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_INTER_EE_CH_CTRL_BMSK 0x10 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_INTER_EE_CH_CTRL_SHFT 0x4 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_IEOB_BMSK 0x8 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_IEOB_SHFT 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_GLOB_EE_BMSK 0x4 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_GLOB_EE_SHFT 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_EV_CTRL_BMSK 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_EV_CTRL_SHFT 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_CH_CTRL_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_CH_CTRL_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00012088 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00012088 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00012088 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_RMSK 0x7f +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_INI(n) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_ADDR(n), \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_INMI(n, \ + mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_ADDR( \ + n), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_OUTI(n, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_ADDR(n), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_INI(n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_GENERAL_BMSK 0x40 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_GENERAL_SHFT 0x6 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_INTER_EE_EV_CTRL_BMSK \ + 0x20 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_INTER_EE_EV_CTRL_SHFT 0x5 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_INTER_EE_CH_CTRL_BMSK \ + 0x10 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_INTER_EE_CH_CTRL_SHFT 0x4 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_IEOB_BMSK 0x8 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_IEOB_SHFT 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_GLOB_EE_BMSK 0x4 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_GLOB_EE_SHFT 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_EV_CTRL_BMSK 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_EV_CTRL_SHFT 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_CH_CTRL_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_CH_CTRL_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00012090 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00012090 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00012090 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_INI(n) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_ADDR(n), \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_INMI(n, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_ADDR(n), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_GSI_CH_BIT_MAP_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_GSI_CH_BIT_MAP_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00012094 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00012094 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00012094 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_INI(n) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_ADDR(n), \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_INMI(n, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_ADDR(n), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_EV_CH_BIT_MAP_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_EV_CH_BIT_MAP_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00012098 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00012098 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00012098 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_RMSK 0x7fffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_INI(n) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_ADDR( \ + n), \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_INMI(n, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_ADDR(n), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_OUTI(n, \ + val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_ADDR( \ + n), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_INI(n)) +#define \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_GSI_CH_BIT_MAP_MSK_BMSK \ + 0x7fffff +#define \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_GSI_CH_BIT_MAP_MSK_SHFT \ + 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001209c + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001209c + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001209c + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_RMSK 0xfffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_INI(n) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_ADDR( \ + n), \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_INMI(n, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_ADDR(n), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_OUTI(n, \ + val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_ADDR( \ + n), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_INI(n)) +#define \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_EV_CH_BIT_MAP_MSK_BMSK \ + 0xfffff +#define \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_EV_CH_BIT_MAP_MSK_SHFT \ + 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000120a0 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000120a0 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000120a0 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_ATTR 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_OUTI(n, \ + val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_ADDR( \ + n), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_GSI_CH_BIT_MAP_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_GSI_CH_BIT_MAP_SHFT \ + 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000120a4 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000120a4 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000120a4 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_ATTR 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_OUTI(n, \ + val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_ADDR( \ + n), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_EV_CH_BIT_MAP_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_EV_CH_BIT_MAP_SHFT \ + 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000120b0 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000120b0 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000120b0 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_INI(n) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_ADDR(n), \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_INMI(n, \ + mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_ADDR( \ + n), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_EV_CH_BIT_MAP_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_EV_CH_BIT_MAP_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000120b8 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000120b8 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000120b8 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_RMSK 0xfffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_INI(n) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_ADDR( \ + n), \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_INMI(n, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_ADDR(n), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_OUTI(n, \ + val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_ADDR( \ + n), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_INI(n)) +#define \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_EV_CH_BIT_MAP_MSK_BMSK \ + 0xfffff +#define \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_EV_CH_BIT_MAP_MSK_SHFT \ + 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000120c0 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000120c0 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000120c0 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_ATTR 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_OUTI(n, \ + val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_ADDR( \ + n), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_EV_CH_BIT_MAP_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_EV_CH_BIT_MAP_SHFT \ + 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00012100 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00012100 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00012100 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_RMSK 0xf +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_INI(n) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_ADDR(n), \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_INMI(n, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_ADDR(n), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT3_BMSK 0x8 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT3_SHFT 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT2_BMSK 0x4 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT2_SHFT 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT1_BMSK 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT1_SHFT 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_ERROR_INT_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_ERROR_INT_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_EN_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00012108 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_EN_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00012108 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_EN_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00012108 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_CLR_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00012110 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_CLR_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00012110 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_CLR_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00012110 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00012118 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00012118 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00012118 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_RMSK 0xf +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_INI(n) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_ADDR(n), \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_INMI(n, \ + mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_ADDR( \ + n), \ + mask) +#define \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_GSI_MCS_STACK_OVRFLOW_BMSK \ + 0x8 +#define \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_GSI_MCS_STACK_OVRFLOW_SHFT \ + 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_GSI_CMD_FIFO_OVRFLOW_BMSK \ + 0x4 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_GSI_CMD_FIFO_OVRFLOW_SHFT \ + 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_GSI_BUS_ERROR_BMSK 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_GSI_BUS_ERROR_SHFT 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_GSI_BREAK_POINT_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_GSI_BREAK_POINT_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_EN_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00012120 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_EN_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00012120 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_EN_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00012120 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_CLR_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00012128 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_CLR_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00012128 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_CLR_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00012128 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_INTSET_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00012180 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_INTSET_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00012180 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_INTSET_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00012180 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_INTSET_RMSK 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_INTSET_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_INTSET_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_INTSET_INI(n) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_INTSET_ADDR(n), \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_INTSET_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_INTSET_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_INTSET_ADDR(n), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_INTSET_OUTI(n, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_INTSET_ADDR(n), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_INTSET_OUTMI(n, mask, \ + val) out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_INTSET_ADDR( \ + n), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_INTSET_INI(n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_INTSET_INTYPE_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_INTSET_INTYPE_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_INTSET_INTYPE_MSI_FVAL 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_INTSET_INTYPE_IRQ_FVAL 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00012188 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00012188 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00012188 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB_INI(n) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB_ADDR(n), \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB_INMI(n, \ + mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB_ADDR( \ + n), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB_OUTI(n, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB_ADDR(n), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB_INI(n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB_MSI_ADDR_LSB_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB_MSI_ADDR_LSB_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_MSB_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001218c + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_MSB_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001218c + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_MSB_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001218c + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_MSB_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_MSB_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_MSB_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_MSB_INI(n) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_MSB_ADDR(n), \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_MSB_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_MSB_INMI(n, \ + mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_MSB_ADDR( \ + n), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_MSB_OUTI(n, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_MSB_ADDR(n), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_MSB_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_MSB_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_MSB_INI(n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_MSB_MSI_ADDR_MSB_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_MSB_MSI_ADDR_MSB_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_INT_VEC_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00012190 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_INT_VEC_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00012190 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_INT_VEC_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00012190 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_ADDR(n) (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x00012200 + 0x4000 * \ + (n)) +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00012200 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00012200 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_INI(n) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_ADDR(n), \ + HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_ADDR(n), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_OUTI(n, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_ADDR(n), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_OUTMI(n, mask, \ + val) out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_ADDR( \ + n), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_INI(n)) +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_ERROR_LOG_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_ERROR_LOG_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_CLR_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00012210 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_CLR_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00012210 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_CLR_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00012210 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_CLR_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_CLR_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_CLR_ATTR 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_CLR_OUTI(n, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_CLR_ADDR(n), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_CLR_ERROR_LOG_CLR_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_CLR_ERROR_LOG_CLR_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00012400 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00012400 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00012400 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_INI(n) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_ADDR(n), \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_INMI(n, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_ADDR( \ + n), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_OUTI(n, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_ADDR(n), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_ADDR( \ + n), \ + mask, val, \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_INI(n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_SCRATCH_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_SCRATCH_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00012404 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00012404 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00012404 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_INI(n) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_ADDR(n), \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_INMI(n, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_ADDR( \ + n), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_OUTI(n, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_ADDR(n), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_ADDR( \ + n), \ + mask, val, \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_INI(n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_SCRATCH_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_SCRATCH_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_MCS_CFG_ADDR (IPA_GSI_TOP_GSI_REG_BASE + \ + 0x0000b000) +#define HWIO_IPA_GSI_TOP_GSI_MCS_CFG_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + \ + 0x0000b000) +#define HWIO_IPA_GSI_TOP_GSI_MCS_CFG_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + \ + 0x0000b000) +#define HWIO_IPA_GSI_TOP_GSI_TZ_FW_AUTH_LOCK_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000b008) +#define HWIO_IPA_GSI_TOP_GSI_TZ_FW_AUTH_LOCK_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000b008) +#define HWIO_IPA_GSI_TOP_GSI_TZ_FW_AUTH_LOCK_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000b008) +#define HWIO_IPA_GSI_TOP_GSI_MSA_FW_AUTH_LOCK_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000b010) +#define HWIO_IPA_GSI_TOP_GSI_MSA_FW_AUTH_LOCK_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000b010) +#define HWIO_IPA_GSI_TOP_GSI_MSA_FW_AUTH_LOCK_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000b010) +#define HWIO_IPA_GSI_TOP_GSI_SP_FW_AUTH_LOCK_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000b018) +#define HWIO_IPA_GSI_TOP_GSI_SP_FW_AUTH_LOCK_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000b018) +#define HWIO_IPA_GSI_TOP_GSI_SP_FW_AUTH_LOCK_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000b018) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_ORIGINATOR_EE_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000c000 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_ORIGINATOR_EE_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000c000 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_ORIGINATOR_EE_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000c000 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_GSI_CH_CMD_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000c008 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_GSI_CH_CMD_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000c008 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_GSI_CH_CMD_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000c008 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_EV_CH_CMD_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000c010 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_EV_CH_CMD_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000c010 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_EV_CH_CMD_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000c010 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000c018 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000c018 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000c018 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000c01c + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000c01c + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000c01c + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000c020 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000c020 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000c020 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_MSK_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000c024 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_MSK_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000c024 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_MSK_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000c024 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000c028 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000c028 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000c028 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_CLR_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000c02c + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_CLR_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000c02c + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_CLR_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000c02c + 0x1000 * (n)) +#define IPA_CFG_REG_BASE (IPA_0_IPA_WRAPPER_BASE + 0x00040000) +#define IPA_CFG_REG_BASE_PHYS (IPA_0_IPA_WRAPPER_BASE_PHYS + 0x00040000) +#define IPA_CFG_REG_BASE_OFFS 0x00040000 +#define HWIO_IPA_COMP_HW_VERSION_ADDR (IPA_CFG_REG_BASE + 0x00000030) +#define HWIO_IPA_COMP_HW_VERSION_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000030) +#define HWIO_IPA_COMP_HW_VERSION_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000030) +#define HWIO_IPA_COMP_HW_VERSION_RMSK 0xffffffff +#define HWIO_IPA_COMP_HW_VERSION_ATTR 0x1 +#define HWIO_IPA_COMP_HW_VERSION_IN in_dword_masked( \ + HWIO_IPA_COMP_HW_VERSION_ADDR, \ + HWIO_IPA_COMP_HW_VERSION_RMSK) +#define HWIO_IPA_COMP_HW_VERSION_INM(m) in_dword_masked( \ + HWIO_IPA_COMP_HW_VERSION_ADDR, \ + m) +#define HWIO_IPA_COMP_HW_VERSION_MAJOR_BMSK 0xf0000000 +#define HWIO_IPA_COMP_HW_VERSION_MAJOR_SHFT 0x1c +#define HWIO_IPA_COMP_HW_VERSION_MINOR_BMSK 0xfff0000 +#define HWIO_IPA_COMP_HW_VERSION_MINOR_SHFT 0x10 +#define HWIO_IPA_COMP_HW_VERSION_STEP_BMSK 0xffff +#define HWIO_IPA_COMP_HW_VERSION_STEP_SHFT 0x0 +#define HWIO_IPA_VERSION_ADDR (IPA_CFG_REG_BASE + 0x00000034) +#define HWIO_IPA_VERSION_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000034) +#define HWIO_IPA_VERSION_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000034) +#define HWIO_IPA_ENABLED_PIPES_ADDR (IPA_CFG_REG_BASE + 0x00000038) +#define HWIO_IPA_ENABLED_PIPES_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000038) +#define HWIO_IPA_ENABLED_PIPES_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000038) +#define HWIO_IPA_COMP_CFG_ADDR (IPA_CFG_REG_BASE + 0x0000003c) +#define HWIO_IPA_COMP_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000003c) +#define HWIO_IPA_COMP_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000003c) +#define HWIO_IPA_COMP_CFG_RMSK 0x3fffee +#define HWIO_IPA_COMP_CFG_ATTR 0x3 +#define HWIO_IPA_COMP_CFG_IN in_dword_masked(HWIO_IPA_COMP_CFG_ADDR, \ + HWIO_IPA_COMP_CFG_RMSK) +#define HWIO_IPA_COMP_CFG_INM(m) in_dword_masked(HWIO_IPA_COMP_CFG_ADDR, m) +#define HWIO_IPA_COMP_CFG_OUT(v) out_dword(HWIO_IPA_COMP_CFG_ADDR, v) +#define HWIO_IPA_COMP_CFG_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_COMP_CFG_ADDR, \ + m, \ + v, \ + HWIO_IPA_COMP_CFG_IN) +#define HWIO_IPA_COMP_CFG_IPA_FULL_FLUSH_WAIT_RSC_CLOSURE_EN_BMSK 0x200000 +#define HWIO_IPA_COMP_CFG_IPA_FULL_FLUSH_WAIT_RSC_CLOSURE_EN_SHFT 0x15 +#define HWIO_IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_BMSK 0x1e0000 +#define HWIO_IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_SHFT 0x11 +#define HWIO_IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_GLOBAL_EN_BMSK 0x10000 +#define HWIO_IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_GLOBAL_EN_SHFT 0x10 +#define HWIO_IPA_COMP_CFG_GSI_MULTI_AXI_MASTERS_DIS_BMSK 0x8000 +#define HWIO_IPA_COMP_CFG_GSI_MULTI_AXI_MASTERS_DIS_SHFT 0xf +#define HWIO_IPA_COMP_CFG_GSI_SNOC_CNOC_LOOP_PROTECTION_DISABLE_BMSK \ + 0x4000 +#define HWIO_IPA_COMP_CFG_GSI_SNOC_CNOC_LOOP_PROTECTION_DISABLE_SHFT 0xe +#define HWIO_IPA_COMP_CFG_GEN_QMB_0_SNOC_CNOC_LOOP_PROTECTION_DISABLE_BMSK \ + 0x2000 +#define HWIO_IPA_COMP_CFG_GEN_QMB_0_SNOC_CNOC_LOOP_PROTECTION_DISABLE_SHFT \ + 0xd +#define HWIO_IPA_COMP_CFG_GEN_QMB_1_MULTI_INORDER_WR_DIS_BMSK 0x1000 +#define HWIO_IPA_COMP_CFG_GEN_QMB_1_MULTI_INORDER_WR_DIS_SHFT 0xc +#define HWIO_IPA_COMP_CFG_GEN_QMB_0_MULTI_INORDER_WR_DIS_BMSK 0x800 +#define HWIO_IPA_COMP_CFG_GEN_QMB_0_MULTI_INORDER_WR_DIS_SHFT 0xb +#define HWIO_IPA_COMP_CFG_GEN_QMB_1_MULTI_INORDER_RD_DIS_BMSK 0x400 +#define HWIO_IPA_COMP_CFG_GEN_QMB_1_MULTI_INORDER_RD_DIS_SHFT 0xa +#define HWIO_IPA_COMP_CFG_GEN_QMB_0_MULTI_INORDER_RD_DIS_BMSK 0x200 +#define HWIO_IPA_COMP_CFG_GEN_QMB_0_MULTI_INORDER_RD_DIS_SHFT 0x9 +#define HWIO_IPA_COMP_CFG_GSI_MULTI_INORDER_WR_DIS_BMSK 0x100 +#define HWIO_IPA_COMP_CFG_GSI_MULTI_INORDER_WR_DIS_SHFT 0x8 +#define HWIO_IPA_COMP_CFG_GSI_MULTI_INORDER_RD_DIS_BMSK 0x80 +#define HWIO_IPA_COMP_CFG_GSI_MULTI_INORDER_RD_DIS_SHFT 0x7 +#define HWIO_IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_PROD_EN_BMSK 0x40 +#define HWIO_IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_PROD_EN_SHFT 0x6 +#define HWIO_IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_CONS_EN_BMSK 0x20 +#define HWIO_IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_CONS_EN_SHFT 0x5 +#define HWIO_IPA_COMP_CFG_GEN_QMB_1_SNOC_BYPASS_DIS_BMSK 0x8 +#define HWIO_IPA_COMP_CFG_GEN_QMB_1_SNOC_BYPASS_DIS_SHFT 0x3 +#define HWIO_IPA_COMP_CFG_GEN_QMB_0_SNOC_BYPASS_DIS_BMSK 0x4 +#define HWIO_IPA_COMP_CFG_GEN_QMB_0_SNOC_BYPASS_DIS_SHFT 0x2 +#define HWIO_IPA_COMP_CFG_GSI_SNOC_BYPASS_DIS_BMSK 0x2 +#define HWIO_IPA_COMP_CFG_GSI_SNOC_BYPASS_DIS_SHFT 0x1 +#define HWIO_IPA_CLKON_CFG_ADDR (IPA_CFG_REG_BASE + 0x00000044) +#define HWIO_IPA_CLKON_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000044) +#define HWIO_IPA_CLKON_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000044) +#define HWIO_IPA_ROUTE_ADDR (IPA_CFG_REG_BASE + 0x00000048) +#define HWIO_IPA_ROUTE_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000048) +#define HWIO_IPA_ROUTE_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000048) +#define HWIO_IPA_ROUTE_RMSK 0x13fffff +#define HWIO_IPA_ROUTE_ATTR 0x3 +#define HWIO_IPA_ROUTE_IN in_dword_masked(HWIO_IPA_ROUTE_ADDR, \ + HWIO_IPA_ROUTE_RMSK) +#define HWIO_IPA_ROUTE_INM(m) in_dword_masked(HWIO_IPA_ROUTE_ADDR, m) +#define HWIO_IPA_ROUTE_OUT(v) out_dword(HWIO_IPA_ROUTE_ADDR, v) +#define HWIO_IPA_ROUTE_OUTM(m, v) out_dword_masked_ns(HWIO_IPA_ROUTE_ADDR, \ + m, \ + v, \ + HWIO_IPA_ROUTE_IN) +#define HWIO_IPA_ROUTE_ROUTE_DEF_RETAIN_HDR_BMSK 0x1000000 +#define HWIO_IPA_ROUTE_ROUTE_DEF_RETAIN_HDR_SHFT 0x18 +#define HWIO_IPA_ROUTE_ROUTE_FRAG_DEF_PIPE_BMSK 0x3e0000 +#define HWIO_IPA_ROUTE_ROUTE_FRAG_DEF_PIPE_SHFT 0x11 +#define HWIO_IPA_ROUTE_ROUTE_DEF_HDR_OFST_BMSK 0x1ff80 +#define HWIO_IPA_ROUTE_ROUTE_DEF_HDR_OFST_SHFT 0x7 +#define HWIO_IPA_ROUTE_ROUTE_DEF_HDR_TABLE_BMSK 0x40 +#define HWIO_IPA_ROUTE_ROUTE_DEF_HDR_TABLE_SHFT 0x6 +#define HWIO_IPA_ROUTE_ROUTE_DEF_PIPE_BMSK 0x3e +#define HWIO_IPA_ROUTE_ROUTE_DEF_PIPE_SHFT 0x1 +#define HWIO_IPA_ROUTE_ROUTE_DIS_BMSK 0x1 +#define HWIO_IPA_ROUTE_ROUTE_DIS_SHFT 0x0 +#define HWIO_IPA_FILTER_ADDR (IPA_CFG_REG_BASE + 0x0000004c) +#define HWIO_IPA_FILTER_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000004c) +#define HWIO_IPA_FILTER_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000004c) +#define HWIO_IPA_MASTER_PRIORITY_ADDR (IPA_CFG_REG_BASE + 0x00000050) +#define HWIO_IPA_MASTER_PRIORITY_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000050) +#define HWIO_IPA_MASTER_PRIORITY_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000050) +#define HWIO_IPA_SHARED_MEM_SIZE_ADDR (IPA_CFG_REG_BASE + 0x00000054) +#define HWIO_IPA_SHARED_MEM_SIZE_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000054) +#define HWIO_IPA_SHARED_MEM_SIZE_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000054) +#define HWIO_IPA_NAT_TIMER_ADDR (IPA_CFG_REG_BASE + 0x00000058) +#define HWIO_IPA_NAT_TIMER_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000058) +#define HWIO_IPA_NAT_TIMER_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000058) +#define HWIO_IPA_TAG_TIMER_ADDR (IPA_CFG_REG_BASE + 0x00000060) +#define HWIO_IPA_TAG_TIMER_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000060) +#define HWIO_IPA_TAG_TIMER_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000060) +#define HWIO_IPA_FRAG_RULES_CLR_ADDR (IPA_CFG_REG_BASE + 0x0000006c) +#define HWIO_IPA_FRAG_RULES_CLR_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000006c) +#define HWIO_IPA_FRAG_RULES_CLR_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000006c) +#define HWIO_IPA_PROC_IPH_CFG_ADDR (IPA_CFG_REG_BASE + 0x00000070) +#define HWIO_IPA_PROC_IPH_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000070) +#define HWIO_IPA_PROC_IPH_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000070) +#define HWIO_IPA_PROC_IPH_CFG_RMSK 0x1ff0ff7 +#define HWIO_IPA_PROC_IPH_CFG_ATTR 0x3 +#define HWIO_IPA_PROC_IPH_CFG_IN in_dword_masked( \ + HWIO_IPA_PROC_IPH_CFG_ADDR, \ + HWIO_IPA_PROC_IPH_CFG_RMSK) +#define HWIO_IPA_PROC_IPH_CFG_INM(m) in_dword_masked( \ + HWIO_IPA_PROC_IPH_CFG_ADDR, \ + m) +#define HWIO_IPA_PROC_IPH_CFG_OUT(v) out_dword(HWIO_IPA_PROC_IPH_CFG_ADDR, \ + v) +#define HWIO_IPA_PROC_IPH_CFG_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_PROC_IPH_CFG_ADDR, \ + m, \ + v, \ + HWIO_IPA_PROC_IPH_CFG_IN) +#define HWIO_IPA_PROC_IPH_CFG_D_DCPH_MULTI_ENGINE_DISABLE_BMSK 0x1000000 +#define HWIO_IPA_PROC_IPH_CFG_D_DCPH_MULTI_ENGINE_DISABLE_SHFT 0x18 +#define HWIO_IPA_PROC_IPH_CFG_IPH_PKT_PARSER_PROTOCOL_STOP_VALUE_BMSK \ + 0xff0000 +#define HWIO_IPA_PROC_IPH_CFG_IPH_PKT_PARSER_PROTOCOL_STOP_VALUE_SHFT 0x10 +#define HWIO_IPA_PROC_IPH_CFG_IPH_PKT_PARSER_IHL_TO_2ND_FRAG_EN_BMSK 0x800 +#define HWIO_IPA_PROC_IPH_CFG_IPH_PKT_PARSER_IHL_TO_2ND_FRAG_EN_SHFT 0xb +#define HWIO_IPA_PROC_IPH_CFG_IPH_PKT_PARSER_PROTOCOL_STOP_DEST_BMSK 0x400 +#define HWIO_IPA_PROC_IPH_CFG_IPH_PKT_PARSER_PROTOCOL_STOP_DEST_SHFT 0xa +#define HWIO_IPA_PROC_IPH_CFG_IPH_PKT_PARSER_PROTOCOL_STOP_HOP_BMSK 0x200 +#define HWIO_IPA_PROC_IPH_CFG_IPH_PKT_PARSER_PROTOCOL_STOP_HOP_SHFT 0x9 +#define HWIO_IPA_PROC_IPH_CFG_IPH_PKT_PARSER_PROTOCOL_STOP_ENABLE_BMSK \ + 0x100 +#define HWIO_IPA_PROC_IPH_CFG_IPH_PKT_PARSER_PROTOCOL_STOP_ENABLE_SHFT 0x8 +#define HWIO_IPA_PROC_IPH_CFG_FTCH_DCPH_OVERLAP_ENABLE_BMSK 0x80 +#define HWIO_IPA_PROC_IPH_CFG_FTCH_DCPH_OVERLAP_ENABLE_SHFT 0x7 +#define HWIO_IPA_PROC_IPH_CFG_PIPESTAGE_OVERLAP_DISABLE_BMSK 0x40 +#define HWIO_IPA_PROC_IPH_CFG_PIPESTAGE_OVERLAP_DISABLE_SHFT 0x6 +#define HWIO_IPA_PROC_IPH_CFG_STATUS_FROM_IPH_FRST_ALWAYS_BMSK 0x10 +#define HWIO_IPA_PROC_IPH_CFG_STATUS_FROM_IPH_FRST_ALWAYS_SHFT 0x4 +#define HWIO_IPA_PROC_IPH_CFG_IPH_PIPELINING_DISABLE_BMSK 0x4 +#define HWIO_IPA_PROC_IPH_CFG_IPH_PIPELINING_DISABLE_SHFT 0x2 +#define HWIO_IPA_PROC_IPH_CFG_IPH_THRESHOLD_BMSK 0x3 +#define HWIO_IPA_PROC_IPH_CFG_IPH_THRESHOLD_SHFT 0x0 +#define HWIO_IPA_QSB_MAX_WRITES_ADDR (IPA_CFG_REG_BASE + 0x00000074) +#define HWIO_IPA_QSB_MAX_WRITES_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000074) +#define HWIO_IPA_QSB_MAX_WRITES_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000074) +#define HWIO_IPA_QSB_MAX_READS_ADDR (IPA_CFG_REG_BASE + 0x00000078) +#define HWIO_IPA_QSB_MAX_READS_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000078) +#define HWIO_IPA_QSB_MAX_READS_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000078) +#define HWIO_IPA_QSB_OUTSTANDING_COUNTER_ADDR (IPA_CFG_REG_BASE + \ + 0x0000007c) +#define HWIO_IPA_QSB_OUTSTANDING_COUNTER_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x0000007c) +#define HWIO_IPA_QSB_OUTSTANDING_COUNTER_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x0000007c) +#define HWIO_IPA_QSB_OUTSTANDING_BEATS_COUNTER_ADDR (IPA_CFG_REG_BASE + \ + 0x00000080) +#define HWIO_IPA_QSB_OUTSTANDING_BEATS_COUNTER_PHYS (IPA_CFG_REG_BASE_PHYS \ + + 0x00000080) +#define HWIO_IPA_QSB_OUTSTANDING_BEATS_COUNTER_OFFS (IPA_CFG_REG_BASE_OFFS \ + + 0x00000080) +#define HWIO_IPA_QSB_READ_CFG_ADDR (IPA_CFG_REG_BASE + 0x00000084) +#define HWIO_IPA_QSB_READ_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000084) +#define HWIO_IPA_QSB_READ_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000084) +#define HWIO_IPA_DPL_TIMER_LSB_ADDR (IPA_CFG_REG_BASE + 0x00000088) +#define HWIO_IPA_DPL_TIMER_LSB_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000088) +#define HWIO_IPA_DPL_TIMER_LSB_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000088) +#define HWIO_IPA_DPL_TIMER_LSB_RMSK 0xffffffff +#define HWIO_IPA_DPL_TIMER_LSB_ATTR 0x3 +#define HWIO_IPA_DPL_TIMER_LSB_IN in_dword_masked( \ + HWIO_IPA_DPL_TIMER_LSB_ADDR, \ + HWIO_IPA_DPL_TIMER_LSB_RMSK) +#define HWIO_IPA_DPL_TIMER_LSB_INM(m) in_dword_masked( \ + HWIO_IPA_DPL_TIMER_LSB_ADDR, \ + m) +#define HWIO_IPA_DPL_TIMER_LSB_OUT(v) out_dword( \ + HWIO_IPA_DPL_TIMER_LSB_ADDR, \ + v) +#define HWIO_IPA_DPL_TIMER_LSB_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_DPL_TIMER_LSB_ADDR, \ + m, \ + v, \ + HWIO_IPA_DPL_TIMER_LSB_IN) +#define HWIO_IPA_DPL_TIMER_LSB_TOD_LSB_BMSK 0xffffffff +#define HWIO_IPA_DPL_TIMER_LSB_TOD_LSB_SHFT 0x0 +#define HWIO_IPA_DPL_TIMER_MSB_ADDR (IPA_CFG_REG_BASE + 0x0000008c) +#define HWIO_IPA_DPL_TIMER_MSB_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000008c) +#define HWIO_IPA_DPL_TIMER_MSB_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000008c) +#define HWIO_IPA_DPL_TIMER_MSB_RMSK 0x8000ffff +#define HWIO_IPA_DPL_TIMER_MSB_ATTR 0x3 +#define HWIO_IPA_DPL_TIMER_MSB_IN in_dword_masked( \ + HWIO_IPA_DPL_TIMER_MSB_ADDR, \ + HWIO_IPA_DPL_TIMER_MSB_RMSK) +#define HWIO_IPA_DPL_TIMER_MSB_INM(m) in_dword_masked( \ + HWIO_IPA_DPL_TIMER_MSB_ADDR, \ + m) +#define HWIO_IPA_DPL_TIMER_MSB_OUT(v) out_dword( \ + HWIO_IPA_DPL_TIMER_MSB_ADDR, \ + v) +#define HWIO_IPA_DPL_TIMER_MSB_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_DPL_TIMER_MSB_ADDR, \ + m, \ + v, \ + HWIO_IPA_DPL_TIMER_MSB_IN) +#define HWIO_IPA_DPL_TIMER_MSB_TIMER_EN_BMSK 0x80000000 +#define HWIO_IPA_DPL_TIMER_MSB_TIMER_EN_SHFT 0x1f +#define HWIO_IPA_DPL_TIMER_MSB_TOD_MSB_BMSK 0xffff +#define HWIO_IPA_DPL_TIMER_MSB_TOD_MSB_SHFT 0x0 +#define HWIO_IPA_STATE_TX_WRAPPER_ADDR (IPA_CFG_REG_BASE + 0x00000090) +#define HWIO_IPA_STATE_TX_WRAPPER_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000090) +#define HWIO_IPA_STATE_TX_WRAPPER_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000090) +#define HWIO_IPA_STATE_TX_WRAPPER_RMSK 0x1e01ffff +#define HWIO_IPA_STATE_TX_WRAPPER_ATTR 0x1 +#define HWIO_IPA_STATE_TX_WRAPPER_IN in_dword_masked( \ + HWIO_IPA_STATE_TX_WRAPPER_ADDR, \ + HWIO_IPA_STATE_TX_WRAPPER_RMSK) +#define HWIO_IPA_STATE_TX_WRAPPER_INM(m) in_dword_masked( \ + HWIO_IPA_STATE_TX_WRAPPER_ADDR, \ + m) +#define HWIO_IPA_STATE_TX_WRAPPER_COAL_SLAVE_OPEN_FRAME_BMSK 0x1e000000 +#define HWIO_IPA_STATE_TX_WRAPPER_COAL_SLAVE_OPEN_FRAME_SHFT 0x19 +#define HWIO_IPA_STATE_TX_WRAPPER_COAL_SLAVE_CTX_IDLE_BMSK 0x10000 +#define HWIO_IPA_STATE_TX_WRAPPER_COAL_SLAVE_CTX_IDLE_SHFT 0x10 +#define HWIO_IPA_STATE_TX_WRAPPER_COAL_SLAVE_IDLE_BMSK 0x8000 +#define HWIO_IPA_STATE_TX_WRAPPER_COAL_SLAVE_IDLE_SHFT 0xf +#define HWIO_IPA_STATE_TX_WRAPPER_COAL_DIRECT_DMA_BMSK 0x6000 +#define HWIO_IPA_STATE_TX_WRAPPER_COAL_DIRECT_DMA_SHFT 0xd +#define HWIO_IPA_STATE_TX_WRAPPER_NLO_DIRECT_DMA_BMSK 0x1800 +#define HWIO_IPA_STATE_TX_WRAPPER_NLO_DIRECT_DMA_SHFT 0xb +#define HWIO_IPA_STATE_TX_WRAPPER_PKT_DROP_CNT_IDLE_BMSK 0x400 +#define HWIO_IPA_STATE_TX_WRAPPER_PKT_DROP_CNT_IDLE_SHFT 0xa +#define HWIO_IPA_STATE_TX_WRAPPER_TRNSEQ_FORCE_VALID_BMSK 0x200 +#define HWIO_IPA_STATE_TX_WRAPPER_TRNSEQ_FORCE_VALID_SHFT 0x9 +#define HWIO_IPA_STATE_TX_WRAPPER_MBIM_DIRECT_DMA_BMSK 0x180 +#define HWIO_IPA_STATE_TX_WRAPPER_MBIM_DIRECT_DMA_SHFT 0x7 +#define HWIO_IPA_STATE_TX_WRAPPER_IPA_MBIM_PKT_FMS_IDLE_BMSK 0x40 +#define HWIO_IPA_STATE_TX_WRAPPER_IPA_MBIM_PKT_FMS_IDLE_SHFT 0x6 +#define HWIO_IPA_STATE_TX_WRAPPER_IPA_PROD_BRESP_TOGGLE_IDLE_BMSK 0x20 +#define HWIO_IPA_STATE_TX_WRAPPER_IPA_PROD_BRESP_TOGGLE_IDLE_SHFT 0x5 +#define HWIO_IPA_STATE_TX_WRAPPER_IPA_PROD_BRESP_EMPTY_BMSK 0x10 +#define HWIO_IPA_STATE_TX_WRAPPER_IPA_PROD_BRESP_EMPTY_SHFT 0x4 +#define HWIO_IPA_STATE_TX_WRAPPER_IPA_PROD_ACKMNGR_STATE_IDLE_BMSK 0x8 +#define HWIO_IPA_STATE_TX_WRAPPER_IPA_PROD_ACKMNGR_STATE_IDLE_SHFT 0x3 +#define HWIO_IPA_STATE_TX_WRAPPER_IPA_PROD_ACKMNGR_DB_EMPTY_BMSK 0x4 +#define HWIO_IPA_STATE_TX_WRAPPER_IPA_PROD_ACKMNGR_DB_EMPTY_SHFT 0x2 +#define HWIO_IPA_STATE_TX_WRAPPER_TX1_IDLE_BMSK 0x2 +#define HWIO_IPA_STATE_TX_WRAPPER_TX1_IDLE_SHFT 0x1 +#define HWIO_IPA_STATE_TX_WRAPPER_TX0_IDLE_BMSK 0x1 +#define HWIO_IPA_STATE_TX_WRAPPER_TX0_IDLE_SHFT 0x0 +#define HWIO_IPA_STATE_TX1_ADDR (IPA_CFG_REG_BASE + 0x00000094) +#define HWIO_IPA_STATE_TX1_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000094) +#define HWIO_IPA_STATE_TX1_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000094) +#define HWIO_IPA_STATE_TX1_RMSK 0xffffffff +#define HWIO_IPA_STATE_TX1_ATTR 0x1 +#define HWIO_IPA_STATE_TX1_IN in_dword_masked(HWIO_IPA_STATE_TX1_ADDR, \ + HWIO_IPA_STATE_TX1_RMSK) +#define HWIO_IPA_STATE_TX1_INM(m) in_dword_masked(HWIO_IPA_STATE_TX1_ADDR, \ + m) +#define HWIO_IPA_STATE_TX1_SUSPEND_REQ_EMPTY_BMSK 0x80000000 +#define HWIO_IPA_STATE_TX1_SUSPEND_REQ_EMPTY_SHFT 0x1f +#define HWIO_IPA_STATE_TX1_LAST_CMD_PIPE_BMSK 0x7c000000 +#define HWIO_IPA_STATE_TX1_LAST_CMD_PIPE_SHFT 0x1a +#define HWIO_IPA_STATE_TX1_CS_SNIF_IDLE_BMSK 0x2000000 +#define HWIO_IPA_STATE_TX1_CS_SNIF_IDLE_SHFT 0x19 +#define HWIO_IPA_STATE_TX1_SUSPEND_EMPTY_BMSK 0x1000000 +#define HWIO_IPA_STATE_TX1_SUSPEND_EMPTY_SHFT 0x18 +#define HWIO_IPA_STATE_TX1_RSRCREL_IDLE_BMSK 0x800000 +#define HWIO_IPA_STATE_TX1_RSRCREL_IDLE_SHFT 0x17 +#define HWIO_IPA_STATE_TX1_HOLB_MASK_IDLE_BMSK 0x400000 +#define HWIO_IPA_STATE_TX1_HOLB_MASK_IDLE_SHFT 0x16 +#define HWIO_IPA_STATE_TX1_HOLB_IDLE_BMSK 0x200000 +#define HWIO_IPA_STATE_TX1_HOLB_IDLE_SHFT 0x15 +#define HWIO_IPA_STATE_TX1_ALIGNER_EMPTY_BMSK 0x100000 +#define HWIO_IPA_STATE_TX1_ALIGNER_EMPTY_SHFT 0x14 +#define HWIO_IPA_STATE_TX1_PF_EMPTY_BMSK 0x80000 +#define HWIO_IPA_STATE_TX1_PF_EMPTY_SHFT 0x13 +#define HWIO_IPA_STATE_TX1_PF_IDLE_BMSK 0x40000 +#define HWIO_IPA_STATE_TX1_PF_IDLE_SHFT 0x12 +#define HWIO_IPA_STATE_TX1_DMAW_LAST_OUTSD_IDLE_BMSK 0x20000 +#define HWIO_IPA_STATE_TX1_DMAW_LAST_OUTSD_IDLE_SHFT 0x11 +#define HWIO_IPA_STATE_TX1_DMAW_IDLE_BMSK 0x10000 +#define HWIO_IPA_STATE_TX1_DMAW_IDLE_SHFT 0x10 +#define HWIO_IPA_STATE_TX1_AR_IDLE_BMSK 0x8000 +#define HWIO_IPA_STATE_TX1_AR_IDLE_SHFT 0xf +#define HWIO_IPA_STATE_TX1_TX_CMD_BRESP_INJ_IDLE_BMSK 0x4000 +#define HWIO_IPA_STATE_TX1_TX_CMD_BRESP_INJ_IDLE_SHFT 0xe +#define HWIO_IPA_STATE_TX1_TX_CMD_BRESP_ALOC_IDLE_BMSK 0x2000 +#define HWIO_IPA_STATE_TX1_TX_CMD_BRESP_ALOC_IDLE_SHFT 0xd +#define HWIO_IPA_STATE_TX1_TX_CMD_SNIF_IDLE_BMSK 0x1000 +#define HWIO_IPA_STATE_TX1_TX_CMD_SNIF_IDLE_SHFT 0xc +#define HWIO_IPA_STATE_TX1_TX_CMD_TRNSEQ_IDLE_BMSK 0x800 +#define HWIO_IPA_STATE_TX1_TX_CMD_TRNSEQ_IDLE_SHFT 0xb +#define HWIO_IPA_STATE_TX1_TX_CMD_MAIN_IDLE_BMSK 0x400 +#define HWIO_IPA_STATE_TX1_TX_CMD_MAIN_IDLE_SHFT 0xa +#define HWIO_IPA_STATE_TX1_PA_PUB_CNT_EMPTY_BMSK 0x200 +#define HWIO_IPA_STATE_TX1_PA_PUB_CNT_EMPTY_SHFT 0x9 +#define HWIO_IPA_STATE_TX1_PA_RST_IDLE_BMSK 0x100 +#define HWIO_IPA_STATE_TX1_PA_RST_IDLE_SHFT 0x8 +#define HWIO_IPA_STATE_TX1_PA_CTX_IDLE_BMSK 0x80 +#define HWIO_IPA_STATE_TX1_PA_CTX_IDLE_SHFT 0x7 +#define HWIO_IPA_STATE_TX1_PA_IDLE_BMSK 0x40 +#define HWIO_IPA_STATE_TX1_PA_IDLE_SHFT 0x6 +#define HWIO_IPA_STATE_TX1_ARBIT_TYPE_BMSK 0x38 +#define HWIO_IPA_STATE_TX1_ARBIT_TYPE_SHFT 0x3 +#define HWIO_IPA_STATE_TX1_FLOPPED_ARBIT_TYPE_BMSK 0x7 +#define HWIO_IPA_STATE_TX1_FLOPPED_ARBIT_TYPE_SHFT 0x0 +#define HWIO_IPA_STATE_FETCHER_ADDR (IPA_CFG_REG_BASE + 0x00000098) +#define HWIO_IPA_STATE_FETCHER_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000098) +#define HWIO_IPA_STATE_FETCHER_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000098) +#define HWIO_IPA_STATE_FETCHER_RMSK 0xfffff +#define HWIO_IPA_STATE_FETCHER_ATTR 0x1 +#define HWIO_IPA_STATE_FETCHER_IN in_dword_masked( \ + HWIO_IPA_STATE_FETCHER_ADDR, \ + HWIO_IPA_STATE_FETCHER_RMSK) +#define HWIO_IPA_STATE_FETCHER_INM(m) in_dword_masked( \ + HWIO_IPA_STATE_FETCHER_ADDR, \ + m) +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_IMM_CMD_EXEC_STATE_IDLE_BMSK \ + 0x80000 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_IMM_CMD_EXEC_STATE_IDLE_SHFT 0x13 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_DMAR_SLOT_STATE_IDLE_BMSK 0x7f000 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_DMAR_SLOT_STATE_IDLE_SHFT 0xc +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_DMAR_STATE_IDLE_BMSK 0xfe0 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_DMAR_STATE_IDLE_SHFT 0x5 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_FTCH_CMPLT_STATE_IDLE_BMSK 0x10 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_FTCH_CMPLT_STATE_IDLE_SHFT 0x4 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_FTCH_IMM_STATE_IDLE_BMSK 0x8 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_FTCH_IMM_STATE_IDLE_SHFT 0x3 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_FTCH_PKT_STATE_IDLE_BMSK 0x4 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_FTCH_PKT_STATE_IDLE_SHFT 0x2 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_FTCH_ALLOC_STATE_IDLE_BMSK 0x2 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_FTCH_ALLOC_STATE_IDLE_SHFT 0x1 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_FTCH_STATE_IDLE_BMSK 0x1 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_FTCH_STATE_IDLE_SHFT 0x0 +#define HWIO_IPA_STATE_FETCHER_MASK_0_ADDR (IPA_CFG_REG_BASE + 0x0000009c) +#define HWIO_IPA_STATE_FETCHER_MASK_0_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x0000009c) +#define HWIO_IPA_STATE_FETCHER_MASK_0_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x0000009c) +#define HWIO_IPA_STATE_FETCHER_MASK_0_RMSK 0xffffffff +#define HWIO_IPA_STATE_FETCHER_MASK_0_ATTR 0x1 +#define HWIO_IPA_STATE_FETCHER_MASK_0_IN in_dword_masked( \ + HWIO_IPA_STATE_FETCHER_MASK_0_ADDR, \ + HWIO_IPA_STATE_FETCHER_MASK_0_RMSK) +#define HWIO_IPA_STATE_FETCHER_MASK_0_INM(m) in_dword_masked( \ + HWIO_IPA_STATE_FETCHER_MASK_0_ADDR, \ + m) +#define \ + HWIO_IPA_STATE_FETCHER_MASK_0_MASK_QUEUE_NO_RESOURCES_HPS_DMAR_BMSK \ + 0xff000000 +#define \ + HWIO_IPA_STATE_FETCHER_MASK_0_MASK_QUEUE_NO_RESOURCES_HPS_DMAR_SHFT \ + 0x18 +#define HWIO_IPA_STATE_FETCHER_MASK_0_MASK_QUEUE_NO_RESOURCES_CONTEXT_BMSK \ + 0xff0000 +#define HWIO_IPA_STATE_FETCHER_MASK_0_MASK_QUEUE_NO_RESOURCES_CONTEXT_SHFT \ + 0x10 +#define HWIO_IPA_STATE_FETCHER_MASK_0_MASK_QUEUE_IMM_EXEC_BMSK 0xff00 +#define HWIO_IPA_STATE_FETCHER_MASK_0_MASK_QUEUE_IMM_EXEC_SHFT 0x8 +#define HWIO_IPA_STATE_FETCHER_MASK_0_MASK_QUEUE_DMAR_USES_QUEUE_BMSK 0xff +#define HWIO_IPA_STATE_FETCHER_MASK_0_MASK_QUEUE_DMAR_USES_QUEUE_SHFT 0x0 +#define HWIO_IPA_STATE_FETCHER_MASK_1_ADDR (IPA_CFG_REG_BASE + 0x000000cc) +#define HWIO_IPA_STATE_FETCHER_MASK_1_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x000000cc) +#define HWIO_IPA_STATE_FETCHER_MASK_1_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x000000cc) +#define HWIO_IPA_STATE_FETCHER_MASK_1_RMSK 0xffffffff +#define HWIO_IPA_STATE_FETCHER_MASK_1_ATTR 0x1 +#define HWIO_IPA_STATE_FETCHER_MASK_1_IN in_dword_masked( \ + HWIO_IPA_STATE_FETCHER_MASK_1_ADDR, \ + HWIO_IPA_STATE_FETCHER_MASK_1_RMSK) +#define HWIO_IPA_STATE_FETCHER_MASK_1_INM(m) in_dword_masked( \ + HWIO_IPA_STATE_FETCHER_MASK_1_ADDR, \ + m) +#define HWIO_IPA_STATE_FETCHER_MASK_1_MASK_QUEUE_NO_SPACE_DPL_FIFO_BMSK \ + 0xff000000 +#define HWIO_IPA_STATE_FETCHER_MASK_1_MASK_QUEUE_NO_SPACE_DPL_FIFO_SHFT \ + 0x18 +#define HWIO_IPA_STATE_FETCHER_MASK_1_MASK_QUEUE_STEP_MODE_BMSK 0xff0000 +#define HWIO_IPA_STATE_FETCHER_MASK_1_MASK_QUEUE_STEP_MODE_SHFT 0x10 +#define HWIO_IPA_STATE_FETCHER_MASK_1_MASK_QUEUE_ARB_LOCK_BMSK 0xff00 +#define HWIO_IPA_STATE_FETCHER_MASK_1_MASK_QUEUE_ARB_LOCK_SHFT 0x8 +#define \ + HWIO_IPA_STATE_FETCHER_MASK_1_MASK_QUEUE_NO_RESOURCES_ACK_ENTRY_BMSK \ + 0xff +#define \ + HWIO_IPA_STATE_FETCHER_MASK_1_MASK_QUEUE_NO_RESOURCES_ACK_ENTRY_SHFT \ + 0x0 +#define HWIO_IPA_STATE_DPL_FIFO_ADDR (IPA_CFG_REG_BASE + 0x000000d0) +#define HWIO_IPA_STATE_DPL_FIFO_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000d0) +#define HWIO_IPA_STATE_DPL_FIFO_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000d0) +#define HWIO_IPA_STATE_DPL_FIFO_RMSK 0x7 +#define HWIO_IPA_STATE_DPL_FIFO_ATTR 0x1 +#define HWIO_IPA_STATE_DPL_FIFO_IN in_dword_masked( \ + HWIO_IPA_STATE_DPL_FIFO_ADDR, \ + HWIO_IPA_STATE_DPL_FIFO_RMSK) +#define HWIO_IPA_STATE_DPL_FIFO_INM(m) in_dword_masked( \ + HWIO_IPA_STATE_DPL_FIFO_ADDR, \ + m) +#define HWIO_IPA_STATE_DPL_FIFO_POP_FSM_STATE_BMSK 0x7 +#define HWIO_IPA_STATE_DPL_FIFO_POP_FSM_STATE_SHFT 0x0 +#define HWIO_IPA_STATE_COAL_MASTER_ADDR (IPA_CFG_REG_BASE + 0x000000d4) +#define HWIO_IPA_STATE_COAL_MASTER_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x000000d4) +#define HWIO_IPA_STATE_COAL_MASTER_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x000000d4) +#define HWIO_IPA_STATE_COAL_MASTER_RMSK 0xffffffff +#define HWIO_IPA_STATE_COAL_MASTER_ATTR 0x1 +#define HWIO_IPA_STATE_COAL_MASTER_IN in_dword_masked( \ + HWIO_IPA_STATE_COAL_MASTER_ADDR, \ + HWIO_IPA_STATE_COAL_MASTER_RMSK) +#define HWIO_IPA_STATE_COAL_MASTER_INM(m) in_dword_masked( \ + HWIO_IPA_STATE_COAL_MASTER_ADDR, \ + m) +#define HWIO_IPA_STATE_COAL_MASTER_VP_TIMER_EXPIRED_BMSK 0xf0000000 +#define HWIO_IPA_STATE_COAL_MASTER_VP_TIMER_EXPIRED_SHFT 0x1c +#define HWIO_IPA_STATE_COAL_MASTER_LRU_VP_BMSK 0xf000000 +#define HWIO_IPA_STATE_COAL_MASTER_LRU_VP_SHFT 0x18 +#define HWIO_IPA_STATE_COAL_MASTER_INIT_VP_FSM_STATE_BMSK 0xf00000 +#define HWIO_IPA_STATE_COAL_MASTER_INIT_VP_FSM_STATE_SHFT 0x14 +#define HWIO_IPA_STATE_COAL_MASTER_CHECK_FIT_FSM_STATE_BMSK 0xf0000 +#define HWIO_IPA_STATE_COAL_MASTER_CHECK_FIT_FSM_STATE_SHFT 0x10 +#define HWIO_IPA_STATE_COAL_MASTER_HASH_CALC_FSM_STATE_BMSK 0xf000 +#define HWIO_IPA_STATE_COAL_MASTER_HASH_CALC_FSM_STATE_SHFT 0xc +#define HWIO_IPA_STATE_COAL_MASTER_FIND_OPEN_FSM_STATE_BMSK 0xf00 +#define HWIO_IPA_STATE_COAL_MASTER_FIND_OPEN_FSM_STATE_SHFT 0x8 +#define HWIO_IPA_STATE_COAL_MASTER_MAIN_FSM_STATE_BMSK 0xf0 +#define HWIO_IPA_STATE_COAL_MASTER_MAIN_FSM_STATE_SHFT 0x4 +#define HWIO_IPA_STATE_COAL_MASTER_VP_VLD_BMSK 0xf +#define HWIO_IPA_STATE_COAL_MASTER_VP_VLD_SHFT 0x0 +#define HWIO_IPA_STATE_DFETCHER_ADDR (IPA_CFG_REG_BASE + 0x000000a0) +#define HWIO_IPA_STATE_DFETCHER_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000a0) +#define HWIO_IPA_STATE_DFETCHER_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000a0) +#define HWIO_IPA_STATE_DFETCHER_RMSK 0x3f3f3 +#define HWIO_IPA_STATE_DFETCHER_ATTR 0x1 +#define HWIO_IPA_STATE_DFETCHER_IN in_dword_masked( \ + HWIO_IPA_STATE_DFETCHER_ADDR, \ + HWIO_IPA_STATE_DFETCHER_RMSK) +#define HWIO_IPA_STATE_DFETCHER_INM(m) in_dword_masked( \ + HWIO_IPA_STATE_DFETCHER_ADDR, \ + m) +#define HWIO_IPA_STATE_DFETCHER_IPA_DPS_DMAR_SLOT_STATE_IDLE_BMSK 0x3f000 +#define HWIO_IPA_STATE_DFETCHER_IPA_DPS_DMAR_SLOT_STATE_IDLE_SHFT 0xc +#define HWIO_IPA_STATE_DFETCHER_IPA_DPS_DMAR_STATE_IDLE_BMSK 0x3f0 +#define HWIO_IPA_STATE_DFETCHER_IPA_DPS_DMAR_STATE_IDLE_SHFT 0x4 +#define HWIO_IPA_STATE_DFETCHER_IPA_DPS_FTCH_CMPLT_STATE_IDLE_BMSK 0x2 +#define HWIO_IPA_STATE_DFETCHER_IPA_DPS_FTCH_CMPLT_STATE_IDLE_SHFT 0x1 +#define HWIO_IPA_STATE_DFETCHER_IPA_DPS_FTCH_PKT_STATE_IDLE_BMSK 0x1 +#define HWIO_IPA_STATE_DFETCHER_IPA_DPS_FTCH_PKT_STATE_IDLE_SHFT 0x0 +#define HWIO_IPA_STATE_ACL_ADDR (IPA_CFG_REG_BASE + 0x000000a4) +#define HWIO_IPA_STATE_ACL_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000a4) +#define HWIO_IPA_STATE_ACL_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000a4) +#define HWIO_IPA_STATE_ACL_RMSK 0xffcffff +#define HWIO_IPA_STATE_ACL_ATTR 0x1 +#define HWIO_IPA_STATE_ACL_IN in_dword_masked(HWIO_IPA_STATE_ACL_ADDR, \ + HWIO_IPA_STATE_ACL_RMSK) +#define HWIO_IPA_STATE_ACL_INM(m) in_dword_masked(HWIO_IPA_STATE_ACL_ADDR, \ + m) +#define HWIO_IPA_STATE_ACL_IPA_HPS_COAL_MASTER_ACTIVE_BMSK 0x8000000 +#define HWIO_IPA_STATE_ACL_IPA_HPS_COAL_MASTER_ACTIVE_SHFT 0x1b +#define HWIO_IPA_STATE_ACL_IPA_HPS_COAL_MASTER_EMPTY_BMSK 0x4000000 +#define HWIO_IPA_STATE_ACL_IPA_HPS_COAL_MASTER_EMPTY_SHFT 0x1a +#define HWIO_IPA_STATE_ACL_IPA_DPS_D_DCPH_2ND_ACTIVE_BMSK 0x2000000 +#define HWIO_IPA_STATE_ACL_IPA_DPS_D_DCPH_2ND_ACTIVE_SHFT 0x19 +#define HWIO_IPA_STATE_ACL_IPA_DPS_D_DCPH_2ND_EMPTY_BMSK 0x1000000 +#define HWIO_IPA_STATE_ACL_IPA_DPS_D_DCPH_2ND_EMPTY_SHFT 0x18 +#define HWIO_IPA_STATE_ACL_IPA_DPS_SEQUENCER_IDLE_BMSK 0x800000 +#define HWIO_IPA_STATE_ACL_IPA_DPS_SEQUENCER_IDLE_SHFT 0x17 +#define HWIO_IPA_STATE_ACL_IPA_HPS_SEQUENCER_IDLE_BMSK 0x400000 +#define HWIO_IPA_STATE_ACL_IPA_HPS_SEQUENCER_IDLE_SHFT 0x16 +#define HWIO_IPA_STATE_ACL_IPA_DPS_D_DCPH_2_ACTIVE_BMSK 0x200000 +#define HWIO_IPA_STATE_ACL_IPA_DPS_D_DCPH_2_ACTIVE_SHFT 0x15 +#define HWIO_IPA_STATE_ACL_IPA_DPS_D_DCPH_2_EMPTY_BMSK 0x100000 +#define HWIO_IPA_STATE_ACL_IPA_DPS_D_DCPH_2_EMPTY_SHFT 0x14 +#define HWIO_IPA_STATE_ACL_IPA_DPS_DISPATCHER_ACTIVE_BMSK 0x80000 +#define HWIO_IPA_STATE_ACL_IPA_DPS_DISPATCHER_ACTIVE_SHFT 0x13 +#define HWIO_IPA_STATE_ACL_IPA_DPS_DISPATCHER_EMPTY_BMSK 0x40000 +#define HWIO_IPA_STATE_ACL_IPA_DPS_DISPATCHER_EMPTY_SHFT 0x12 +#define HWIO_IPA_STATE_ACL_IPA_DPS_D_DCPH_ACTIVE_BMSK 0x8000 +#define HWIO_IPA_STATE_ACL_IPA_DPS_D_DCPH_ACTIVE_SHFT 0xf +#define HWIO_IPA_STATE_ACL_IPA_DPS_D_DCPH_EMPTY_BMSK 0x4000 +#define HWIO_IPA_STATE_ACL_IPA_DPS_D_DCPH_EMPTY_SHFT 0xe +#define HWIO_IPA_STATE_ACL_IPA_HPS_ENQUEUER_ACTIVE_BMSK 0x2000 +#define HWIO_IPA_STATE_ACL_IPA_HPS_ENQUEUER_ACTIVE_SHFT 0xd +#define HWIO_IPA_STATE_ACL_IPA_HPS_ENQUEUER_EMPTY_BMSK 0x1000 +#define HWIO_IPA_STATE_ACL_IPA_HPS_ENQUEUER_EMPTY_SHFT 0xc +#define HWIO_IPA_STATE_ACL_IPA_HPS_UCP_ACTIVE_BMSK 0x800 +#define HWIO_IPA_STATE_ACL_IPA_HPS_UCP_ACTIVE_SHFT 0xb +#define HWIO_IPA_STATE_ACL_IPA_HPS_UCP_EMPTY_BMSK 0x400 +#define HWIO_IPA_STATE_ACL_IPA_HPS_UCP_EMPTY_SHFT 0xa +#define HWIO_IPA_STATE_ACL_IPA_HPS_HDRI_ACTIVE_BMSK 0x200 +#define HWIO_IPA_STATE_ACL_IPA_HPS_HDRI_ACTIVE_SHFT 0x9 +#define HWIO_IPA_STATE_ACL_IPA_HPS_HDRI_EMPTY_BMSK 0x100 +#define HWIO_IPA_STATE_ACL_IPA_HPS_HDRI_EMPTY_SHFT 0x8 +#define HWIO_IPA_STATE_ACL_IPA_HPS_ROUTER_ACTIVE_BMSK 0x80 +#define HWIO_IPA_STATE_ACL_IPA_HPS_ROUTER_ACTIVE_SHFT 0x7 +#define HWIO_IPA_STATE_ACL_IPA_HPS_ROUTER_EMPTY_BMSK 0x40 +#define HWIO_IPA_STATE_ACL_IPA_HPS_ROUTER_EMPTY_SHFT 0x6 +#define HWIO_IPA_STATE_ACL_IPA_HPS_FILTER_NAT_ACTIVE_BMSK 0x20 +#define HWIO_IPA_STATE_ACL_IPA_HPS_FILTER_NAT_ACTIVE_SHFT 0x5 +#define HWIO_IPA_STATE_ACL_IPA_HPS_FILTER_NAT_EMPTY_BMSK 0x10 +#define HWIO_IPA_STATE_ACL_IPA_HPS_FILTER_NAT_EMPTY_SHFT 0x4 +#define HWIO_IPA_STATE_ACL_IPA_HPS_PKT_PARSER_ACTIVE_BMSK 0x8 +#define HWIO_IPA_STATE_ACL_IPA_HPS_PKT_PARSER_ACTIVE_SHFT 0x3 +#define HWIO_IPA_STATE_ACL_IPA_HPS_PKT_PARSER_EMPTY_BMSK 0x4 +#define HWIO_IPA_STATE_ACL_IPA_HPS_PKT_PARSER_EMPTY_SHFT 0x2 +#define HWIO_IPA_STATE_ACL_IPA_HPS_H_DCPH_ACTIVE_BMSK 0x2 +#define HWIO_IPA_STATE_ACL_IPA_HPS_H_DCPH_ACTIVE_SHFT 0x1 +#define HWIO_IPA_STATE_ACL_IPA_HPS_H_DCPH_EMPTY_BMSK 0x1 +#define HWIO_IPA_STATE_ACL_IPA_HPS_H_DCPH_EMPTY_SHFT 0x0 +#define HWIO_IPA_STATE_GSI_TLV_ADDR (IPA_CFG_REG_BASE + 0x000000b8) +#define HWIO_IPA_STATE_GSI_TLV_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000b8) +#define HWIO_IPA_STATE_GSI_TLV_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000b8) +#define HWIO_IPA_STATE_GSI_TLV_RMSK 0x1 +#define HWIO_IPA_STATE_GSI_TLV_ATTR 0x1 +#define HWIO_IPA_STATE_GSI_TLV_IN in_dword_masked( \ + HWIO_IPA_STATE_GSI_TLV_ADDR, \ + HWIO_IPA_STATE_GSI_TLV_RMSK) +#define HWIO_IPA_STATE_GSI_TLV_INM(m) in_dword_masked( \ + HWIO_IPA_STATE_GSI_TLV_ADDR, \ + m) +#define HWIO_IPA_STATE_GSI_TLV_IPA_GSI_TOGGLE_FSM_IDLE_BMSK 0x1 +#define HWIO_IPA_STATE_GSI_TLV_IPA_GSI_TOGGLE_FSM_IDLE_SHFT 0x0 +#define HWIO_IPA_STATE_GSI_AOS_ADDR (IPA_CFG_REG_BASE + 0x000000bc) +#define HWIO_IPA_STATE_GSI_AOS_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000bc) +#define HWIO_IPA_STATE_GSI_AOS_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000bc) +#define HWIO_IPA_STATE_GSI_AOS_RMSK 0x1 +#define HWIO_IPA_STATE_GSI_AOS_ATTR 0x1 +#define HWIO_IPA_STATE_GSI_AOS_IN in_dword_masked( \ + HWIO_IPA_STATE_GSI_AOS_ADDR, \ + HWIO_IPA_STATE_GSI_AOS_RMSK) +#define HWIO_IPA_STATE_GSI_AOS_INM(m) in_dword_masked( \ + HWIO_IPA_STATE_GSI_AOS_ADDR, \ + m) +#define HWIO_IPA_STATE_GSI_AOS_IPA_GSI_AOS_FSM_IDLE_BMSK 0x1 +#define HWIO_IPA_STATE_GSI_AOS_IPA_GSI_AOS_FSM_IDLE_SHFT 0x0 +#define HWIO_IPA_STATE_GSI_IF_ADDR (IPA_CFG_REG_BASE + 0x000000c0) +#define HWIO_IPA_STATE_GSI_IF_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000c0) +#define HWIO_IPA_STATE_GSI_IF_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000c0) +#define HWIO_IPA_STATE_GSI_IF_RMSK 0xff +#define HWIO_IPA_STATE_GSI_IF_ATTR 0x1 +#define HWIO_IPA_STATE_GSI_IF_IN in_dword_masked( \ + HWIO_IPA_STATE_GSI_IF_ADDR, \ + HWIO_IPA_STATE_GSI_IF_RMSK) +#define HWIO_IPA_STATE_GSI_IF_INM(m) in_dword_masked( \ + HWIO_IPA_STATE_GSI_IF_ADDR, \ + m) +#define HWIO_IPA_STATE_GSI_IF_IPA_GSI_PROD_FSM_TX_1_BMSK 0xf0 +#define HWIO_IPA_STATE_GSI_IF_IPA_GSI_PROD_FSM_TX_1_SHFT 0x4 +#define HWIO_IPA_STATE_GSI_IF_IPA_GSI_PROD_FSM_TX_0_BMSK 0xf +#define HWIO_IPA_STATE_GSI_IF_IPA_GSI_PROD_FSM_TX_0_SHFT 0x0 +#define HWIO_IPA_STATE_GSI_SKIP_ADDR (IPA_CFG_REG_BASE + 0x000000c4) +#define HWIO_IPA_STATE_GSI_SKIP_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000c4) +#define HWIO_IPA_STATE_GSI_SKIP_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000c4) +#define HWIO_IPA_STATE_GSI_SKIP_RMSK 0x3 +#define HWIO_IPA_STATE_GSI_SKIP_ATTR 0x1 +#define HWIO_IPA_STATE_GSI_SKIP_IN in_dword_masked( \ + HWIO_IPA_STATE_GSI_SKIP_ADDR, \ + HWIO_IPA_STATE_GSI_SKIP_RMSK) +#define HWIO_IPA_STATE_GSI_SKIP_INM(m) in_dword_masked( \ + HWIO_IPA_STATE_GSI_SKIP_ADDR, \ + m) +#define HWIO_IPA_STATE_GSI_SKIP_IPA_GSI_SKIP_FSM_BMSK 0x3 +#define HWIO_IPA_STATE_GSI_SKIP_IPA_GSI_SKIP_FSM_SHFT 0x0 +#define HWIO_IPA_STATE_GSI_IF_CONS_ADDR (IPA_CFG_REG_BASE + 0x000000c8) +#define HWIO_IPA_STATE_GSI_IF_CONS_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x000000c8) +#define HWIO_IPA_STATE_GSI_IF_CONS_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x000000c8) +#define HWIO_IPA_STATE_GSI_IF_CONS_RMSK 0x7ffffff +#define HWIO_IPA_STATE_GSI_IF_CONS_ATTR 0x1 +#define HWIO_IPA_STATE_GSI_IF_CONS_IN in_dword_masked( \ + HWIO_IPA_STATE_GSI_IF_CONS_ADDR, \ + HWIO_IPA_STATE_GSI_IF_CONS_RMSK) +#define HWIO_IPA_STATE_GSI_IF_CONS_INM(m) in_dword_masked( \ + HWIO_IPA_STATE_GSI_IF_CONS_ADDR, \ + m) +#define \ + HWIO_IPA_STATE_GSI_IF_CONS_IPA_STATE_GSI_IF_CONS_RX_REQ_NO_ZERO_BMSK \ + 0x7fe0000 +#define \ + HWIO_IPA_STATE_GSI_IF_CONS_IPA_STATE_GSI_IF_CONS_RX_REQ_NO_ZERO_SHFT \ + 0x11 +#define HWIO_IPA_STATE_GSI_IF_CONS_IPA_STATE_GSI_IF_CONS_RX_REQ_BMSK \ + 0x1ff80 +#define HWIO_IPA_STATE_GSI_IF_CONS_IPA_STATE_GSI_IF_CONS_RX_REQ_SHFT 0x7 +#define HWIO_IPA_STATE_GSI_IF_CONS_IPA_STATE_GSI_IF_CONS_CACHE_VLD_BMSK \ + 0x7e +#define HWIO_IPA_STATE_GSI_IF_CONS_IPA_STATE_GSI_IF_CONS_CACHE_VLD_SHFT \ + 0x1 +#define HWIO_IPA_STATE_GSI_IF_CONS_IPA_STATE_GSI_IF_CONS_STATE_BMSK 0x1 +#define HWIO_IPA_STATE_GSI_IF_CONS_IPA_STATE_GSI_IF_CONS_STATE_SHFT 0x0 +#define HWIO_IPA_STATE_ADDR (IPA_CFG_REG_BASE + 0x000000a8) +#define HWIO_IPA_STATE_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000a8) +#define HWIO_IPA_STATE_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000a8) +#define HWIO_IPA_STATE_RMSK 0xf7ffffff +#define HWIO_IPA_STATE_ATTR 0x1 +#define HWIO_IPA_STATE_IN in_dword_masked(HWIO_IPA_STATE_ADDR, \ + HWIO_IPA_STATE_RMSK) +#define HWIO_IPA_STATE_INM(m) in_dword_masked(HWIO_IPA_STATE_ADDR, m) +#define HWIO_IPA_STATE_IPA_UC_RX_HND_CMDQ_EMPTY_BMSK 0x80000000 +#define HWIO_IPA_STATE_IPA_UC_RX_HND_CMDQ_EMPTY_SHFT 0x1f +#define HWIO_IPA_STATE_IPA_DPS_TX_EMPTY_BMSK 0x40000000 +#define HWIO_IPA_STATE_IPA_DPS_TX_EMPTY_SHFT 0x1e +#define HWIO_IPA_STATE_IPA_HPS_DPS_EMPTY_BMSK 0x20000000 +#define HWIO_IPA_STATE_IPA_HPS_DPS_EMPTY_SHFT 0x1d +#define HWIO_IPA_STATE_IPA_RX_HPS_EMPTY_BMSK 0x10000000 +#define HWIO_IPA_STATE_IPA_RX_HPS_EMPTY_SHFT 0x1c +#define HWIO_IPA_STATE_IPA_RX_SPLT_CMDQ_EMPTY_BMSK 0x7800000 +#define HWIO_IPA_STATE_IPA_RX_SPLT_CMDQ_EMPTY_SHFT 0x17 +#define HWIO_IPA_STATE_IPA_TX_COMMANDER_CMDQ_EMPTY_BMSK 0x400000 +#define HWIO_IPA_STATE_IPA_TX_COMMANDER_CMDQ_EMPTY_SHFT 0x16 +#define HWIO_IPA_STATE_IPA_RX_ACKQ_EMPTY_BMSK 0x200000 +#define HWIO_IPA_STATE_IPA_RX_ACKQ_EMPTY_SHFT 0x15 +#define HWIO_IPA_STATE_IPA_UC_ACKQ_EMPTY_BMSK 0x100000 +#define HWIO_IPA_STATE_IPA_UC_ACKQ_EMPTY_SHFT 0x14 +#define HWIO_IPA_STATE_IPA_TX_ACKQ_EMPTY_BMSK 0x80000 +#define HWIO_IPA_STATE_IPA_TX_ACKQ_EMPTY_SHFT 0x13 +#define HWIO_IPA_STATE_IPA_NTF_TX_EMPTY_BMSK 0x40000 +#define HWIO_IPA_STATE_IPA_NTF_TX_EMPTY_SHFT 0x12 +#define HWIO_IPA_STATE_IPA_FULL_IDLE_BMSK 0x20000 +#define HWIO_IPA_STATE_IPA_FULL_IDLE_SHFT 0x11 +#define HWIO_IPA_STATE_IPA_PROD_BRESP_IDLE_BMSK 0x10000 +#define HWIO_IPA_STATE_IPA_PROD_BRESP_IDLE_SHFT 0x10 +#define HWIO_IPA_STATE_IPA_PROD_ACKMNGR_STATE_IDLE_BMSK 0x8000 +#define HWIO_IPA_STATE_IPA_PROD_ACKMNGR_STATE_IDLE_SHFT 0xf +#define HWIO_IPA_STATE_IPA_PROD_ACKMNGR_DB_EMPTY_BMSK 0x4000 +#define HWIO_IPA_STATE_IPA_PROD_ACKMNGR_DB_EMPTY_SHFT 0xe +#define HWIO_IPA_STATE_IPA_TX_ACKQ_FULL_BMSK 0x2000 +#define HWIO_IPA_STATE_IPA_TX_ACKQ_FULL_SHFT 0xd +#define HWIO_IPA_STATE_IPA_ACKMNGR_STATE_IDLE_BMSK 0x1000 +#define HWIO_IPA_STATE_IPA_ACKMNGR_STATE_IDLE_SHFT 0xc +#define HWIO_IPA_STATE_IPA_ACKMNGR_DB_EMPTY_BMSK 0x800 +#define HWIO_IPA_STATE_IPA_ACKMNGR_DB_EMPTY_SHFT 0xb +#define HWIO_IPA_STATE_IPA_RSRC_STATE_IDLE_BMSK 0x400 +#define HWIO_IPA_STATE_IPA_RSRC_STATE_IDLE_SHFT 0xa +#define HWIO_IPA_STATE_IPA_RSRC_MNGR_DB_EMPTY_BMSK 0x200 +#define HWIO_IPA_STATE_IPA_RSRC_MNGR_DB_EMPTY_SHFT 0x9 +#define HWIO_IPA_STATE_MBIM_AGGR_IDLE_BMSK 0x100 +#define HWIO_IPA_STATE_MBIM_AGGR_IDLE_SHFT 0x8 +#define HWIO_IPA_STATE_AGGR_IDLE_BMSK 0x80 +#define HWIO_IPA_STATE_AGGR_IDLE_SHFT 0x7 +#define HWIO_IPA_STATE_IPA_NOC_IDLE_BMSK 0x40 +#define HWIO_IPA_STATE_IPA_NOC_IDLE_SHFT 0x6 +#define HWIO_IPA_STATE_IPA_STATUS_SNIFFER_IDLE_BMSK 0x20 +#define HWIO_IPA_STATE_IPA_STATUS_SNIFFER_IDLE_SHFT 0x5 +#define HWIO_IPA_STATE_BAM_GSI_IDLE_BMSK 0x10 +#define HWIO_IPA_STATE_BAM_GSI_IDLE_SHFT 0x4 +#define HWIO_IPA_STATE_DPL_FIFO_IDLE_BMSK 0x8 +#define HWIO_IPA_STATE_DPL_FIFO_IDLE_SHFT 0x3 +#define HWIO_IPA_STATE_TX_IDLE_BMSK 0x4 +#define HWIO_IPA_STATE_TX_IDLE_SHFT 0x2 +#define HWIO_IPA_STATE_RX_IDLE_BMSK 0x2 +#define HWIO_IPA_STATE_RX_IDLE_SHFT 0x1 +#define HWIO_IPA_STATE_RX_WAIT_BMSK 0x1 +#define HWIO_IPA_STATE_RX_WAIT_SHFT 0x0 +#define HWIO_IPA_STATE_RX_ACTIVE_ADDR (IPA_CFG_REG_BASE + 0x000000ac) +#define HWIO_IPA_STATE_RX_ACTIVE_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000ac) +#define HWIO_IPA_STATE_RX_ACTIVE_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000ac) +#define HWIO_IPA_STATE_RX_ACTIVE_RMSK 0x1fff +#define HWIO_IPA_STATE_RX_ACTIVE_ATTR 0x1 +#define HWIO_IPA_STATE_RX_ACTIVE_IN in_dword_masked( \ + HWIO_IPA_STATE_RX_ACTIVE_ADDR, \ + HWIO_IPA_STATE_RX_ACTIVE_RMSK) +#define HWIO_IPA_STATE_RX_ACTIVE_INM(m) in_dword_masked( \ + HWIO_IPA_STATE_RX_ACTIVE_ADDR, \ + m) +#define HWIO_IPA_STATE_RX_ACTIVE_ENDPOINTS_BMSK 0x1fff +#define HWIO_IPA_STATE_RX_ACTIVE_ENDPOINTS_SHFT 0x0 +#define HWIO_IPA_STATE_TX0_ADDR (IPA_CFG_REG_BASE + 0x000000b0) +#define HWIO_IPA_STATE_TX0_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000b0) +#define HWIO_IPA_STATE_TX0_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000b0) +#define HWIO_IPA_STATE_TX0_RMSK 0xfffffff +#define HWIO_IPA_STATE_TX0_ATTR 0x1 +#define HWIO_IPA_STATE_TX0_IN in_dword_masked(HWIO_IPA_STATE_TX0_ADDR, \ + HWIO_IPA_STATE_TX0_RMSK) +#define HWIO_IPA_STATE_TX0_INM(m) in_dword_masked(HWIO_IPA_STATE_TX0_ADDR, \ + m) +#define HWIO_IPA_STATE_TX0_LAST_CMD_PIPE_BMSK 0xf800000 +#define HWIO_IPA_STATE_TX0_LAST_CMD_PIPE_SHFT 0x17 +#define HWIO_IPA_STATE_TX0_CS_SNIF_IDLE_BMSK 0x400000 +#define HWIO_IPA_STATE_TX0_CS_SNIF_IDLE_SHFT 0x16 +#define HWIO_IPA_STATE_TX0_SUSPEND_EMPTY_BMSK 0x200000 +#define HWIO_IPA_STATE_TX0_SUSPEND_EMPTY_SHFT 0x15 +#define HWIO_IPA_STATE_TX0_RSRCREL_IDLE_BMSK 0x100000 +#define HWIO_IPA_STATE_TX0_RSRCREL_IDLE_SHFT 0x14 +#define HWIO_IPA_STATE_TX0_HOLB_MASK_IDLE_BMSK 0x80000 +#define HWIO_IPA_STATE_TX0_HOLB_MASK_IDLE_SHFT 0x13 +#define HWIO_IPA_STATE_TX0_HOLB_IDLE_BMSK 0x40000 +#define HWIO_IPA_STATE_TX0_HOLB_IDLE_SHFT 0x12 +#define HWIO_IPA_STATE_TX0_ALIGNER_EMPTY_BMSK 0x20000 +#define HWIO_IPA_STATE_TX0_ALIGNER_EMPTY_SHFT 0x11 +#define HWIO_IPA_STATE_TX0_PF_EMPTY_BMSK 0x10000 +#define HWIO_IPA_STATE_TX0_PF_EMPTY_SHFT 0x10 +#define HWIO_IPA_STATE_TX0_PF_IDLE_BMSK 0x8000 +#define HWIO_IPA_STATE_TX0_PF_IDLE_SHFT 0xf +#define HWIO_IPA_STATE_TX0_DMAW_LAST_OUTSD_IDLE_BMSK 0x4000 +#define HWIO_IPA_STATE_TX0_DMAW_LAST_OUTSD_IDLE_SHFT 0xe +#define HWIO_IPA_STATE_TX0_DMAW_IDLE_BMSK 0x2000 +#define HWIO_IPA_STATE_TX0_DMAW_IDLE_SHFT 0xd +#define HWIO_IPA_STATE_TX0_AR_IDLE_BMSK 0x1000 +#define HWIO_IPA_STATE_TX0_AR_IDLE_SHFT 0xc +#define HWIO_IPA_STATE_TX0_TX_CMD_BRESP_INJ_IDLE_BMSK 0x800 +#define HWIO_IPA_STATE_TX0_TX_CMD_BRESP_INJ_IDLE_SHFT 0xb +#define HWIO_IPA_STATE_TX0_TX_CMD_BRESP_ALOC_IDLE_BMSK 0x400 +#define HWIO_IPA_STATE_TX0_TX_CMD_BRESP_ALOC_IDLE_SHFT 0xa +#define HWIO_IPA_STATE_TX0_TX_CMD_SNIF_IDLE_BMSK 0x200 +#define HWIO_IPA_STATE_TX0_TX_CMD_SNIF_IDLE_SHFT 0x9 +#define HWIO_IPA_STATE_TX0_TX_CMD_TRNSEQ_IDLE_BMSK 0x100 +#define HWIO_IPA_STATE_TX0_TX_CMD_TRNSEQ_IDLE_SHFT 0x8 +#define HWIO_IPA_STATE_TX0_TX_CMD_MAIN_IDLE_BMSK 0x80 +#define HWIO_IPA_STATE_TX0_TX_CMD_MAIN_IDLE_SHFT 0x7 +#define HWIO_IPA_STATE_TX0_PA_PUB_CNT_EMPTY_BMSK 0x40 +#define HWIO_IPA_STATE_TX0_PA_PUB_CNT_EMPTY_SHFT 0x6 +#define HWIO_IPA_STATE_TX0_PA_CTX_IDLE_BMSK 0x20 +#define HWIO_IPA_STATE_TX0_PA_CTX_IDLE_SHFT 0x5 +#define HWIO_IPA_STATE_TX0_PA_IDLE_BMSK 0x10 +#define HWIO_IPA_STATE_TX0_PA_IDLE_SHFT 0x4 +#define HWIO_IPA_STATE_TX0_NEXT_ARBIT_TYPE_BMSK 0xc +#define HWIO_IPA_STATE_TX0_NEXT_ARBIT_TYPE_SHFT 0x2 +#define HWIO_IPA_STATE_TX0_LAST_ARBIT_TYPE_BMSK 0x3 +#define HWIO_IPA_STATE_TX0_LAST_ARBIT_TYPE_SHFT 0x0 +#define HWIO_IPA_STATE_AGGR_ACTIVE_ADDR (IPA_CFG_REG_BASE + 0x000000b4) +#define HWIO_IPA_STATE_AGGR_ACTIVE_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x000000b4) +#define HWIO_IPA_STATE_AGGR_ACTIVE_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x000000b4) +#define HWIO_IPA_STATE_AGGR_ACTIVE_RMSK 0x7fffffff +#define HWIO_IPA_STATE_AGGR_ACTIVE_ATTR 0x1 +#define HWIO_IPA_STATE_AGGR_ACTIVE_IN in_dword_masked( \ + HWIO_IPA_STATE_AGGR_ACTIVE_ADDR, \ + HWIO_IPA_STATE_AGGR_ACTIVE_RMSK) +#define HWIO_IPA_STATE_AGGR_ACTIVE_INM(m) in_dword_masked( \ + HWIO_IPA_STATE_AGGR_ACTIVE_ADDR, \ + m) +#define HWIO_IPA_STATE_AGGR_ACTIVE_ENDPOINTS_BMSK 0x7fffffff +#define HWIO_IPA_STATE_AGGR_ACTIVE_ENDPOINTS_SHFT 0x0 +#define HWIO_IPA_GENERIC_RAM_ARBITER_PRIORITY_ADDR (IPA_CFG_REG_BASE + \ + 0x000000d8) +#define HWIO_IPA_GENERIC_RAM_ARBITER_PRIORITY_PHYS (IPA_CFG_REG_BASE_PHYS \ + + 0x000000d8) +#define HWIO_IPA_GENERIC_RAM_ARBITER_PRIORITY_OFFS (IPA_CFG_REG_BASE_OFFS \ + + 0x000000d8) +#define HWIO_IPA_STATE_NLO_AGGR_ADDR (IPA_CFG_REG_BASE + 0x000000dc) +#define HWIO_IPA_STATE_NLO_AGGR_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000dc) +#define HWIO_IPA_STATE_NLO_AGGR_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000dc) +#define HWIO_IPA_STATE_NLO_AGGR_RMSK 0xffffffff +#define HWIO_IPA_STATE_NLO_AGGR_ATTR 0x1 +#define HWIO_IPA_STATE_NLO_AGGR_IN in_dword_masked( \ + HWIO_IPA_STATE_NLO_AGGR_ADDR, \ + HWIO_IPA_STATE_NLO_AGGR_RMSK) +#define HWIO_IPA_STATE_NLO_AGGR_INM(m) in_dword_masked( \ + HWIO_IPA_STATE_NLO_AGGR_ADDR, \ + m) +#define HWIO_IPA_STATE_NLO_AGGR_NLO_AGGR_STATE_BMSK 0xffffffff +#define HWIO_IPA_STATE_NLO_AGGR_NLO_AGGR_STATE_SHFT 0x0 +#define HWIO_IPA_STATE_COAL_MASTER_1_ADDR (IPA_CFG_REG_BASE + 0x000000e0) +#define HWIO_IPA_STATE_COAL_MASTER_1_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x000000e0) +#define HWIO_IPA_STATE_COAL_MASTER_1_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x000000e0) +#define HWIO_IPA_STATE_COAL_MASTER_1_RMSK 0x3fffffff +#define HWIO_IPA_STATE_COAL_MASTER_1_ATTR 0x1 +#define HWIO_IPA_STATE_COAL_MASTER_1_IN in_dword_masked( \ + HWIO_IPA_STATE_COAL_MASTER_1_ADDR, \ + HWIO_IPA_STATE_COAL_MASTER_1_RMSK) +#define HWIO_IPA_STATE_COAL_MASTER_1_INM(m) in_dword_masked( \ + HWIO_IPA_STATE_COAL_MASTER_1_ADDR, \ + m) +#define HWIO_IPA_STATE_COAL_MASTER_1_ARBITER_STATE_BMSK 0x3c000000 +#define HWIO_IPA_STATE_COAL_MASTER_1_ARBITER_STATE_SHFT 0x1a +#define HWIO_IPA_STATE_COAL_MASTER_1_CHECK_FIT_FSM_STATE_BMSK 0x3c00000 +#define HWIO_IPA_STATE_COAL_MASTER_1_CHECK_FIT_FSM_STATE_SHFT 0x16 +#define HWIO_IPA_STATE_COAL_MASTER_1_CHECK_FIT_RD_CTX_LINE_BMSK 0x3f0000 +#define HWIO_IPA_STATE_COAL_MASTER_1_CHECK_FIT_RD_CTX_LINE_SHFT 0x10 +#define HWIO_IPA_STATE_COAL_MASTER_1_INIT_VP_FSM_STATE_BMSK 0xf000 +#define HWIO_IPA_STATE_COAL_MASTER_1_INIT_VP_FSM_STATE_SHFT 0xc +#define HWIO_IPA_STATE_COAL_MASTER_1_INIT_VP_RD_PKT_LINE_BMSK 0xfc0 +#define HWIO_IPA_STATE_COAL_MASTER_1_INIT_VP_RD_PKT_LINE_SHFT 0x6 +#define HWIO_IPA_STATE_COAL_MASTER_1_INIT_VP_WR_CTX_LINE_BMSK 0x3f +#define HWIO_IPA_STATE_COAL_MASTER_1_INIT_VP_WR_CTX_LINE_SHFT 0x0 +#define HWIO_IPA_YELLOW_MARKER_BELOW_ADDR (IPA_CFG_REG_BASE + 0x00000110) +#define HWIO_IPA_YELLOW_MARKER_BELOW_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000110) +#define HWIO_IPA_YELLOW_MARKER_BELOW_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000110) +#define HWIO_IPA_YELLOW_MARKER_BELOW_EN_ADDR (IPA_CFG_REG_BASE + \ + 0x00000114) +#define HWIO_IPA_YELLOW_MARKER_BELOW_EN_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000114) +#define HWIO_IPA_YELLOW_MARKER_BELOW_EN_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000114) +#define HWIO_IPA_YELLOW_MARKER_BELOW_CLR_ADDR (IPA_CFG_REG_BASE + \ + 0x00000118) +#define HWIO_IPA_YELLOW_MARKER_BELOW_CLR_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000118) +#define HWIO_IPA_YELLOW_MARKER_BELOW_CLR_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000118) +#define HWIO_IPA_RED_MARKER_BELOW_ADDR (IPA_CFG_REG_BASE + 0x0000011c) +#define HWIO_IPA_RED_MARKER_BELOW_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000011c) +#define HWIO_IPA_RED_MARKER_BELOW_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000011c) +#define HWIO_IPA_RED_MARKER_BELOW_EN_ADDR (IPA_CFG_REG_BASE + 0x00000120) +#define HWIO_IPA_RED_MARKER_BELOW_EN_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000120) +#define HWIO_IPA_RED_MARKER_BELOW_EN_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000120) +#define HWIO_IPA_RED_MARKER_BELOW_CLR_ADDR (IPA_CFG_REG_BASE + 0x00000124) +#define HWIO_IPA_RED_MARKER_BELOW_CLR_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000124) +#define HWIO_IPA_RED_MARKER_BELOW_CLR_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000124) +#define HWIO_IPA_YELLOW_MARKER_SHADOW_ADDR (IPA_CFG_REG_BASE + 0x00000128) +#define HWIO_IPA_YELLOW_MARKER_SHADOW_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000128) +#define HWIO_IPA_YELLOW_MARKER_SHADOW_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000128) +#define HWIO_IPA_RED_MARKER_SHADOW_ADDR (IPA_CFG_REG_BASE + 0x0000012c) +#define HWIO_IPA_RED_MARKER_SHADOW_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x0000012c) +#define HWIO_IPA_RED_MARKER_SHADOW_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x0000012c) +#define HWIO_IPA_YELLOW_MARKER_ABOVE_ADDR (IPA_CFG_REG_BASE + 0x00000130) +#define HWIO_IPA_YELLOW_MARKER_ABOVE_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000130) +#define HWIO_IPA_YELLOW_MARKER_ABOVE_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000130) +#define HWIO_IPA_YELLOW_MARKER_ABOVE_EN_ADDR (IPA_CFG_REG_BASE + \ + 0x00000134) +#define HWIO_IPA_YELLOW_MARKER_ABOVE_EN_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000134) +#define HWIO_IPA_YELLOW_MARKER_ABOVE_EN_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000134) +#define HWIO_IPA_YELLOW_MARKER_ABOVE_CLR_ADDR (IPA_CFG_REG_BASE + \ + 0x00000138) +#define HWIO_IPA_YELLOW_MARKER_ABOVE_CLR_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000138) +#define HWIO_IPA_YELLOW_MARKER_ABOVE_CLR_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000138) +#define HWIO_IPA_RED_MARKER_ABOVE_ADDR (IPA_CFG_REG_BASE + 0x0000013c) +#define HWIO_IPA_RED_MARKER_ABOVE_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000013c) +#define HWIO_IPA_RED_MARKER_ABOVE_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000013c) +#define HWIO_IPA_RED_MARKER_ABOVE_EN_ADDR (IPA_CFG_REG_BASE + 0x00000140) +#define HWIO_IPA_RED_MARKER_ABOVE_EN_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000140) +#define HWIO_IPA_RED_MARKER_ABOVE_EN_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000140) +#define HWIO_IPA_RED_MARKER_ABOVE_CLR_ADDR (IPA_CFG_REG_BASE + 0x00000144) +#define HWIO_IPA_RED_MARKER_ABOVE_CLR_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000144) +#define HWIO_IPA_RED_MARKER_ABOVE_CLR_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000144) +#define HWIO_IPA_FILT_ROUT_HASH_EN_ADDR (IPA_CFG_REG_BASE + 0x00000148) +#define HWIO_IPA_FILT_ROUT_HASH_EN_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000148) +#define HWIO_IPA_FILT_ROUT_HASH_EN_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000148) +#define HWIO_IPA_FILT_ROUT_HASH_EN_RMSK 0x1111 +#define HWIO_IPA_FILT_ROUT_HASH_EN_ATTR 0x3 +#define HWIO_IPA_FILT_ROUT_HASH_EN_IN in_dword_masked( \ + HWIO_IPA_FILT_ROUT_HASH_EN_ADDR, \ + HWIO_IPA_FILT_ROUT_HASH_EN_RMSK) +#define HWIO_IPA_FILT_ROUT_HASH_EN_INM(m) in_dword_masked( \ + HWIO_IPA_FILT_ROUT_HASH_EN_ADDR, \ + m) +#define HWIO_IPA_FILT_ROUT_HASH_EN_OUT(v) out_dword( \ + HWIO_IPA_FILT_ROUT_HASH_EN_ADDR, \ + v) +#define HWIO_IPA_FILT_ROUT_HASH_EN_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_FILT_ROUT_HASH_EN_ADDR, \ + m, \ + v, \ + HWIO_IPA_FILT_ROUT_HASH_EN_IN) +#define HWIO_IPA_FILT_ROUT_HASH_EN_IPV4_FILTER_HASH_EN_BMSK 0x1000 +#define HWIO_IPA_FILT_ROUT_HASH_EN_IPV4_FILTER_HASH_EN_SHFT 0xc +#define HWIO_IPA_FILT_ROUT_HASH_EN_IPV4_ROUTER_HASH_EN_BMSK 0x100 +#define HWIO_IPA_FILT_ROUT_HASH_EN_IPV4_ROUTER_HASH_EN_SHFT 0x8 +#define HWIO_IPA_FILT_ROUT_HASH_EN_IPV6_FILTER_HASH_EN_BMSK 0x10 +#define HWIO_IPA_FILT_ROUT_HASH_EN_IPV6_FILTER_HASH_EN_SHFT 0x4 +#define HWIO_IPA_FILT_ROUT_HASH_EN_IPV6_ROUTER_HASH_EN_BMSK 0x1 +#define HWIO_IPA_FILT_ROUT_HASH_EN_IPV6_ROUTER_HASH_EN_SHFT 0x0 +#define HWIO_IPA_FILT_ROUT_HASH_FLUSH_ADDR (IPA_CFG_REG_BASE + 0x0000014c) +#define HWIO_IPA_FILT_ROUT_HASH_FLUSH_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x0000014c) +#define HWIO_IPA_FILT_ROUT_HASH_FLUSH_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x0000014c) +#define HWIO_IPA_FILT_ROUT_HASH_FLUSH_RMSK 0x1111 +#define HWIO_IPA_FILT_ROUT_HASH_FLUSH_ATTR 0x2 +#define HWIO_IPA_FILT_ROUT_HASH_FLUSH_OUT(v) out_dword( \ + HWIO_IPA_FILT_ROUT_HASH_FLUSH_ADDR, \ + v) +#define HWIO_IPA_FILT_ROUT_HASH_FLUSH_IPV4_FILTER_HASH_FLUSH_BMSK 0x1000 +#define HWIO_IPA_FILT_ROUT_HASH_FLUSH_IPV4_FILTER_HASH_FLUSH_SHFT 0xc +#define HWIO_IPA_FILT_ROUT_HASH_FLUSH_IPV4_ROUTER_HASH_FLUSH_BMSK 0x100 +#define HWIO_IPA_FILT_ROUT_HASH_FLUSH_IPV4_ROUTER_HASH_FLUSH_SHFT 0x8 +#define HWIO_IPA_FILT_ROUT_HASH_FLUSH_IPV6_FILTER_HASH_FLUSH_BMSK 0x10 +#define HWIO_IPA_FILT_ROUT_HASH_FLUSH_IPV6_FILTER_HASH_FLUSH_SHFT 0x4 +#define HWIO_IPA_FILT_ROUT_HASH_FLUSH_IPV6_ROUTER_HASH_FLUSH_BMSK 0x1 +#define HWIO_IPA_FILT_ROUT_HASH_FLUSH_IPV6_ROUTER_HASH_FLUSH_SHFT 0x0 +#define HWIO_IPA_FILT_ROUT_CFG_ADDR (IPA_CFG_REG_BASE + 0x00000150) +#define HWIO_IPA_FILT_ROUT_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000150) +#define HWIO_IPA_FILT_ROUT_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000150) +#define HWIO_IPA_IPV4_FILTER_INIT_VALUES_ADDR (IPA_CFG_REG_BASE + \ + 0x00000160) +#define HWIO_IPA_IPV4_FILTER_INIT_VALUES_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000160) +#define HWIO_IPA_IPV4_FILTER_INIT_VALUES_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000160) +#define HWIO_IPA_IPV4_FILTER_INIT_VALUES_RMSK 0xffffffff +#define HWIO_IPA_IPV4_FILTER_INIT_VALUES_ATTR 0x1 +#define HWIO_IPA_IPV4_FILTER_INIT_VALUES_IN in_dword_masked( \ + HWIO_IPA_IPV4_FILTER_INIT_VALUES_ADDR, \ + HWIO_IPA_IPV4_FILTER_INIT_VALUES_RMSK) +#define HWIO_IPA_IPV4_FILTER_INIT_VALUES_INM(m) in_dword_masked( \ + HWIO_IPA_IPV4_FILTER_INIT_VALUES_ADDR, \ + m) +#define \ + HWIO_IPA_IPV4_FILTER_INIT_VALUES_IP_V4_FILTER_INIT_HASHED_ADDR_BMSK \ + 0xffff +#define \ + HWIO_IPA_IPV4_FILTER_INIT_VALUES_IP_V4_FILTER_INIT_HASHED_ADDR_SHFT \ + 0x0 +#define HWIO_IPA_IPV6_FILTER_INIT_VALUES_ADDR (IPA_CFG_REG_BASE + \ + 0x00000164) +#define HWIO_IPA_IPV6_FILTER_INIT_VALUES_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000164) +#define HWIO_IPA_IPV6_FILTER_INIT_VALUES_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000164) +#define HWIO_IPA_IPV6_FILTER_INIT_VALUES_RMSK 0xffffffff +#define HWIO_IPA_IPV6_FILTER_INIT_VALUES_ATTR 0x1 +#define HWIO_IPA_IPV6_FILTER_INIT_VALUES_IN in_dword_masked( \ + HWIO_IPA_IPV6_FILTER_INIT_VALUES_ADDR, \ + HWIO_IPA_IPV6_FILTER_INIT_VALUES_RMSK) +#define HWIO_IPA_IPV6_FILTER_INIT_VALUES_INM(m) in_dword_masked( \ + HWIO_IPA_IPV6_FILTER_INIT_VALUES_ADDR, \ + m) +#define \ + HWIO_IPA_IPV6_FILTER_INIT_VALUES_IP_V6_FILTER_INIT_HASHED_ADDR_BMSK \ + 0xffff +#define \ + HWIO_IPA_IPV6_FILTER_INIT_VALUES_IP_V6_FILTER_INIT_HASHED_ADDR_SHFT \ + 0x0 +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_0_ADDR (IPA_CFG_REG_BASE + \ + 0x00000178) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_0_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000178) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_0_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000178) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_0_MSB_ADDR (IPA_CFG_REG_BASE + \ + 0x0000017c) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_0_MSB_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x0000017c) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_0_MSB_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x0000017c) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_1_ADDR (IPA_CFG_REG_BASE + \ + 0x00000180) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_1_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000180) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_1_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000180) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_1_MSB_ADDR (IPA_CFG_REG_BASE + \ + 0x00000184) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_1_MSB_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000184) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_1_MSB_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000184) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_2_ADDR (IPA_CFG_REG_BASE + \ + 0x00000188) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_2_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000188) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_2_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000188) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_2_MSB_ADDR (IPA_CFG_REG_BASE + \ + 0x0000018c) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_2_MSB_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x0000018c) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_2_MSB_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x0000018c) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_3_ADDR (IPA_CFG_REG_BASE + \ + 0x00000190) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_3_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000190) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_3_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000190) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_3_MSB_ADDR (IPA_CFG_REG_BASE + \ + 0x00000194) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_3_MSB_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000194) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_3_MSB_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000194) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_4_ADDR (IPA_CFG_REG_BASE + \ + 0x00000198) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_4_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000198) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_4_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000198) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_5_ADDR (IPA_CFG_REG_BASE + \ + 0x0000019c) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_5_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x0000019c) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_5_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x0000019c) +#define HWIO_IPA_IPV4_ROUTE_INIT_VALUES_ADDR (IPA_CFG_REG_BASE + \ + 0x000001a0) +#define HWIO_IPA_IPV4_ROUTE_INIT_VALUES_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x000001a0) +#define HWIO_IPA_IPV4_ROUTE_INIT_VALUES_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x000001a0) +#define HWIO_IPA_IPV4_ROUTE_INIT_VALUES_RMSK 0xffffffff +#define HWIO_IPA_IPV4_ROUTE_INIT_VALUES_ATTR 0x1 +#define HWIO_IPA_IPV4_ROUTE_INIT_VALUES_IN in_dword_masked( \ + HWIO_IPA_IPV4_ROUTE_INIT_VALUES_ADDR, \ + HWIO_IPA_IPV4_ROUTE_INIT_VALUES_RMSK) +#define HWIO_IPA_IPV4_ROUTE_INIT_VALUES_INM(m) in_dword_masked( \ + HWIO_IPA_IPV4_ROUTE_INIT_VALUES_ADDR, \ + m) +#define \ + HWIO_IPA_IPV4_ROUTE_INIT_VALUES_IP_V4_ROUTE_INIT_NON_HASHED_ADDR_BMSK \ + 0xffff0000 +#define \ + HWIO_IPA_IPV4_ROUTE_INIT_VALUES_IP_V4_ROUTE_INIT_NON_HASHED_ADDR_SHFT \ + 0x10 +#define HWIO_IPA_IPV4_ROUTE_INIT_VALUES_IP_V4_ROUTE_INIT_HASHED_ADDR_BMSK \ + 0xffff +#define HWIO_IPA_IPV4_ROUTE_INIT_VALUES_IP_V4_ROUTE_INIT_HASHED_ADDR_SHFT \ + 0x0 +#define HWIO_IPA_IPV6_ROUTE_INIT_VALUES_ADDR (IPA_CFG_REG_BASE + \ + 0x000001a4) +#define HWIO_IPA_IPV6_ROUTE_INIT_VALUES_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x000001a4) +#define HWIO_IPA_IPV6_ROUTE_INIT_VALUES_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x000001a4) +#define HWIO_IPA_IPV6_ROUTE_INIT_VALUES_RMSK 0xffffffff +#define HWIO_IPA_IPV6_ROUTE_INIT_VALUES_ATTR 0x1 +#define HWIO_IPA_IPV6_ROUTE_INIT_VALUES_IN in_dword_masked( \ + HWIO_IPA_IPV6_ROUTE_INIT_VALUES_ADDR, \ + HWIO_IPA_IPV6_ROUTE_INIT_VALUES_RMSK) +#define HWIO_IPA_IPV6_ROUTE_INIT_VALUES_INM(m) in_dword_masked( \ + HWIO_IPA_IPV6_ROUTE_INIT_VALUES_ADDR, \ + m) +#define \ + HWIO_IPA_IPV6_ROUTE_INIT_VALUES_IP_V6_ROUTE_INIT_NON_HASHED_ADDR_BMSK \ + 0xffff0000 +#define \ + HWIO_IPA_IPV6_ROUTE_INIT_VALUES_IP_V6_ROUTE_INIT_NON_HASHED_ADDR_SHFT \ + 0x10 +#define HWIO_IPA_IPV6_ROUTE_INIT_VALUES_IP_V6_ROUTE_INIT_HASHED_ADDR_BMSK \ + 0xffff +#define HWIO_IPA_IPV6_ROUTE_INIT_VALUES_IP_V6_ROUTE_INIT_HASHED_ADDR_SHFT \ + 0x0 +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_ADDR (IPA_CFG_REG_BASE + \ + 0x000001a8) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_PHYS (IPA_CFG_REG_BASE_PHYS \ + + 0x000001a8) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_OFFS (IPA_CFG_REG_BASE_OFFS \ + + 0x000001a8) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_MSB_ADDR (IPA_CFG_REG_BASE \ + + 0x000001ac) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_MSB_PHYS ( \ + IPA_CFG_REG_BASE_PHYS + 0x000001ac) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_MSB_OFFS ( \ + IPA_CFG_REG_BASE_OFFS + 0x000001ac) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_ADDR (IPA_CFG_REG_BASE + \ + 0x000001b0) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_PHYS (IPA_CFG_REG_BASE_PHYS \ + + 0x000001b0) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_OFFS (IPA_CFG_REG_BASE_OFFS \ + + 0x000001b0) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_MSB_ADDR (IPA_CFG_REG_BASE \ + + 0x000001b4) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_MSB_PHYS ( \ + IPA_CFG_REG_BASE_PHYS + 0x000001b4) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_MSB_OFFS ( \ + IPA_CFG_REG_BASE_OFFS + 0x000001b4) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_2_ADDR (IPA_CFG_REG_BASE + \ + 0x000001b8) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_2_PHYS (IPA_CFG_REG_BASE_PHYS \ + + 0x000001b8) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_2_OFFS (IPA_CFG_REG_BASE_OFFS \ + + 0x000001b8) +#define HWIO_IPA_HDR_INIT_LOCAL_VALUES_ADDR (IPA_CFG_REG_BASE + 0x000001c0) +#define HWIO_IPA_HDR_INIT_LOCAL_VALUES_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x000001c0) +#define HWIO_IPA_HDR_INIT_LOCAL_VALUES_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x000001c0) +#define HWIO_IPA_HDR_INIT_SYSTEM_VALUES_ADDR (IPA_CFG_REG_BASE + \ + 0x000001c4) +#define HWIO_IPA_HDR_INIT_SYSTEM_VALUES_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x000001c4) +#define HWIO_IPA_HDR_INIT_SYSTEM_VALUES_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x000001c4) +#define HWIO_IPA_HDR_INIT_SYSTEM_VALUES_MSB_ADDR (IPA_CFG_REG_BASE + \ + 0x000001c8) +#define HWIO_IPA_HDR_INIT_SYSTEM_VALUES_MSB_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x000001c8) +#define HWIO_IPA_HDR_INIT_SYSTEM_VALUES_MSB_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x000001c8) +#define HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_ADDR (IPA_CFG_REG_BASE + \ + 0x000001cc) +#define HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x000001cc) +#define HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x000001cc) +#define HWIO_IPA_FRAG_VALUES_ADDR (IPA_CFG_REG_BASE + 0x000001d8) +#define HWIO_IPA_FRAG_VALUES_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000001d8) +#define HWIO_IPA_FRAG_VALUES_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000001d8) +#define HWIO_IPA_BAM_ACTIVATED_PORTS_ADDR (IPA_CFG_REG_BASE + 0x000001dc) +#define HWIO_IPA_BAM_ACTIVATED_PORTS_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x000001dc) +#define HWIO_IPA_BAM_ACTIVATED_PORTS_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x000001dc) +#define HWIO_IPA_BAM_ACTIVATED_PORTS_RMSK 0x7fffffff +#define HWIO_IPA_BAM_ACTIVATED_PORTS_ATTR 0x1 +#define HWIO_IPA_BAM_ACTIVATED_PORTS_IN in_dword_masked( \ + HWIO_IPA_BAM_ACTIVATED_PORTS_ADDR, \ + HWIO_IPA_BAM_ACTIVATED_PORTS_RMSK) +#define HWIO_IPA_BAM_ACTIVATED_PORTS_INM(m) in_dword_masked( \ + HWIO_IPA_BAM_ACTIVATED_PORTS_ADDR, \ + m) +#define HWIO_IPA_BAM_ACTIVATED_PORTS_ENDPOINTS_BMSK 0x7fffffff +#define HWIO_IPA_BAM_ACTIVATED_PORTS_ENDPOINTS_SHFT 0x0 +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_ADDR (IPA_CFG_REG_BASE + \ + 0x000001e0) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x000001e0) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x000001e0) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_RMSK 0xffffffff +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_ATTR 0x3 +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_IN in_dword_masked( \ + HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_ADDR, \ + HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_RMSK) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_INM(m) in_dword_masked( \ + HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_ADDR, \ + m) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_OUT(v) out_dword( \ + HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_ADDR, \ + v) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_ADDR, \ + m, \ + v, \ + HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_IN) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_ADDR_BMSK 0xfffffff8 +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_ADDR_SHFT 0x3 +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_ZERO_BMSK 0x7 +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_ZERO_SHFT 0x0 +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_ADDR (IPA_CFG_REG_BASE + \ + 0x000001e4) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x000001e4) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x000001e4) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_RMSK 0xffffffff +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_ATTR 0x3 +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_IN in_dword_masked( \ + HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_ADDR, \ + HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_RMSK) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_INM(m) in_dword_masked( \ + HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_ADDR, \ + m) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_OUT(v) out_dword( \ + HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_ADDR, \ + v) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_OUTM(m, \ + v) out_dword_masked_ns( \ + HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_ADDR, \ + m, \ + v, \ + HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_IN) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_ADDR_BMSK 0xffffffff +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_ADDR_SHFT 0x0 +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_ADDR (IPA_CFG_REG_BASE + \ + 0x000001e8) +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x000001e8) +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x000001e8) +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_RMSK 0x3ffff +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_ATTR 0x3 +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_IN in_dword_masked( \ + HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_ADDR, \ + HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_RMSK) +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_INM(m) in_dword_masked( \ + HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_ADDR, \ + m) +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_OUT(v) out_dword( \ + HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_ADDR, \ + v) +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_IN) +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_ADDR_BMSK 0x3fff8 +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_ADDR_SHFT 0x3 +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_ZERO_BMSK 0x7 +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_ZERO_SHFT 0x0 +#define HWIO_IPA_AGGR_FORCE_CLOSE_ADDR (IPA_CFG_REG_BASE + 0x000001ec) +#define HWIO_IPA_AGGR_FORCE_CLOSE_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000001ec) +#define HWIO_IPA_AGGR_FORCE_CLOSE_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000001ec) +#define HWIO_IPA_SCND_FRAG_VALUES_ADDR (IPA_CFG_REG_BASE + 0x000001f4) +#define HWIO_IPA_SCND_FRAG_VALUES_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000001f4) +#define HWIO_IPA_SCND_FRAG_VALUES_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000001f4) +#define HWIO_IPA_TX_CFG_ADDR (IPA_CFG_REG_BASE + 0x000001fc) +#define HWIO_IPA_TX_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000001fc) +#define HWIO_IPA_TX_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000001fc) +#define HWIO_IPA_NAT_UC_EXTERNAL_CFG_ADDR (IPA_CFG_REG_BASE + 0x00000200) +#define HWIO_IPA_NAT_UC_EXTERNAL_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000200) +#define HWIO_IPA_NAT_UC_EXTERNAL_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000200) +#define HWIO_IPA_NAT_UC_LOCAL_CFG_ADDR (IPA_CFG_REG_BASE + 0x00000204) +#define HWIO_IPA_NAT_UC_LOCAL_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000204) +#define HWIO_IPA_NAT_UC_LOCAL_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000204) +#define HWIO_IPA_NAT_UC_SHARED_CFG_ADDR (IPA_CFG_REG_BASE + 0x00000208) +#define HWIO_IPA_NAT_UC_SHARED_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000208) +#define HWIO_IPA_NAT_UC_SHARED_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000208) +#define HWIO_IPA_RAM_INTLV_CFG_ADDR (IPA_CFG_REG_BASE + 0x0000020c) +#define HWIO_IPA_RAM_INTLV_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000020c) +#define HWIO_IPA_RAM_INTLV_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000020c) +#define HWIO_IPA_FLAVOR_0_ADDR (IPA_CFG_REG_BASE + 0x00000210) +#define HWIO_IPA_FLAVOR_0_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000210) +#define HWIO_IPA_FLAVOR_0_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000210) +#define HWIO_IPA_FLAVOR_1_ADDR (IPA_CFG_REG_BASE + 0x00000214) +#define HWIO_IPA_FLAVOR_1_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000214) +#define HWIO_IPA_FLAVOR_1_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000214) +#define HWIO_IPA_FLAVOR_2_ADDR (IPA_CFG_REG_BASE + 0x00000218) +#define HWIO_IPA_FLAVOR_2_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000218) +#define HWIO_IPA_FLAVOR_2_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000218) +#define HWIO_IPA_FLAVOR_3_ADDR (IPA_CFG_REG_BASE + 0x0000021c) +#define HWIO_IPA_FLAVOR_3_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000021c) +#define HWIO_IPA_FLAVOR_3_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000021c) +#define HWIO_IPA_FLAVOR_4_ADDR (IPA_CFG_REG_BASE + 0x00000220) +#define HWIO_IPA_FLAVOR_4_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000220) +#define HWIO_IPA_FLAVOR_4_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000220) +#define HWIO_IPA_FLAVOR_5_ADDR (IPA_CFG_REG_BASE + 0x00000224) +#define HWIO_IPA_FLAVOR_5_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000224) +#define HWIO_IPA_FLAVOR_5_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000224) +#define HWIO_IPA_FLAVOR_6_ADDR (IPA_CFG_REG_BASE + 0x00000228) +#define HWIO_IPA_FLAVOR_6_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000228) +#define HWIO_IPA_FLAVOR_6_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000228) +#define HWIO_IPA_FLAVOR_7_ADDR (IPA_CFG_REG_BASE + 0x0000022c) +#define HWIO_IPA_FLAVOR_7_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000022c) +#define HWIO_IPA_FLAVOR_7_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000022c) +#define HWIO_IPA_CONN_TRACK_UC_EXTERNAL_CFG_ADDR (IPA_CFG_REG_BASE + \ + 0x00000230) +#define HWIO_IPA_CONN_TRACK_UC_EXTERNAL_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000230) +#define HWIO_IPA_CONN_TRACK_UC_EXTERNAL_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000230) +#define HWIO_IPA_CONN_TRACK_UC_LOCAL_CFG_ADDR (IPA_CFG_REG_BASE + \ + 0x00000234) +#define HWIO_IPA_CONN_TRACK_UC_LOCAL_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000234) +#define HWIO_IPA_CONN_TRACK_UC_LOCAL_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000234) +#define HWIO_IPA_CONN_TRACK_UC_SHARED_CFG_ADDR (IPA_CFG_REG_BASE + \ + 0x00000238) +#define HWIO_IPA_CONN_TRACK_UC_SHARED_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000238) +#define HWIO_IPA_CONN_TRACK_UC_SHARED_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000238) +#define HWIO_IPA_IDLE_INDICATION_CFG_ADDR (IPA_CFG_REG_BASE + 0x00000240) +#define HWIO_IPA_IDLE_INDICATION_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000240) +#define HWIO_IPA_IDLE_INDICATION_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000240) +#define HWIO_IPA_QTIME_TIMESTAMP_CFG_ADDR (IPA_CFG_REG_BASE + 0x0000024c) +#define HWIO_IPA_QTIME_TIMESTAMP_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x0000024c) +#define HWIO_IPA_QTIME_TIMESTAMP_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x0000024c) +#define HWIO_IPA_TIMERS_XO_CLK_DIV_CFG_ADDR (IPA_CFG_REG_BASE + 0x00000250) +#define HWIO_IPA_TIMERS_XO_CLK_DIV_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000250) +#define HWIO_IPA_TIMERS_XO_CLK_DIV_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000250) +#define HWIO_IPA_TIMERS_PULSE_GRAN_CFG_ADDR (IPA_CFG_REG_BASE + 0x00000254) +#define HWIO_IPA_TIMERS_PULSE_GRAN_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000254) +#define HWIO_IPA_TIMERS_PULSE_GRAN_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000254) +#define HWIO_IPA_QTIME_SMP_ADDR (IPA_CFG_REG_BASE + 0x00000260) +#define HWIO_IPA_QTIME_SMP_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000260) +#define HWIO_IPA_QTIME_SMP_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000260) +#define HWIO_IPA_QTIME_LSB_ADDR (IPA_CFG_REG_BASE + 0x00000264) +#define HWIO_IPA_QTIME_LSB_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000264) +#define HWIO_IPA_QTIME_LSB_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000264) +#define HWIO_IPA_QTIME_MSB_ADDR (IPA_CFG_REG_BASE + 0x00000268) +#define HWIO_IPA_QTIME_MSB_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000268) +#define HWIO_IPA_QTIME_MSB_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000268) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_EN_ADDR (IPA_CFG_REG_BASE + \ + 0x00000334) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_EN_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000334) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_EN_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000334) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_0_ADDR (IPA_CFG_REG_BASE + \ + 0x00000338) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_0_PHYS ( \ + IPA_CFG_REG_BASE_PHYS + 0x00000338) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_0_OFFS ( \ + IPA_CFG_REG_BASE_OFFS + 0x00000338) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_1_ADDR (IPA_CFG_REG_BASE + \ + 0x0000033c) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_1_PHYS ( \ + IPA_CFG_REG_BASE_PHYS + 0x0000033c) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_1_OFFS ( \ + IPA_CFG_REG_BASE_OFFS + 0x0000033c) +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_EN_ADDR (IPA_CFG_REG_BASE + \ + 0x00000340) +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_EN_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000340) +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_EN_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000340) +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_VALUES_0_ADDR (IPA_CFG_REG_BASE + \ + 0x00000344) +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_VALUES_0_PHYS ( \ + IPA_CFG_REG_BASE_PHYS + 0x00000344) +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_VALUES_0_OFFS ( \ + IPA_CFG_REG_BASE_OFFS + 0x00000344) +#define HWIO_IPA_HPS_DPS_CMDQ_RED_IRQ_MASK_ENABLE_ADDR (IPA_CFG_REG_BASE + \ + 0x00000348) +#define HWIO_IPA_HPS_DPS_CMDQ_RED_IRQ_MASK_ENABLE_PHYS ( \ + IPA_CFG_REG_BASE_PHYS + 0x00000348) +#define HWIO_IPA_HPS_DPS_CMDQ_RED_IRQ_MASK_ENABLE_OFFS ( \ + IPA_CFG_REG_BASE_OFFS + 0x00000348) +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000400 + 0x20 * \ + (n)) +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_PHYS(n) ( \ + IPA_CFG_REG_BASE_PHYS + 0x00000400 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_OFFS(n) ( \ + IPA_CFG_REG_BASE_OFFS + 0x00000400 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_RMSK 0x3f3f3f3f +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_MAXn 4 +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_ATTR 0x3 +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_INI(n) in_dword_masked( \ + HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_ADDR(n), \ + HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_RMSK) +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_ADDR(n), \ + mask) +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_OUTI(n, val) out_dword( \ + HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_ADDR(n), \ + val) +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns(HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_ADDR( \ + n), \ + mask, val, \ + HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_INI(n)) +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_SRC_RSRC_GRP_1_MAX_LIMIT_BMSK \ + 0x3f000000 +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_SRC_RSRC_GRP_1_MAX_LIMIT_SHFT \ + 0x18 +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_SRC_RSRC_GRP_1_MIN_LIMIT_BMSK \ + 0x3f0000 +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_SRC_RSRC_GRP_1_MIN_LIMIT_SHFT \ + 0x10 +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_SRC_RSRC_GRP_0_MAX_LIMIT_BMSK \ + 0x3f00 +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_SRC_RSRC_GRP_0_MAX_LIMIT_SHFT \ + 0x8 +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_SRC_RSRC_GRP_0_MIN_LIMIT_BMSK \ + 0x3f +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_SRC_RSRC_GRP_0_MIN_LIMIT_SHFT \ + 0x0 +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000404 + 0x20 * \ + (n)) +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_PHYS(n) ( \ + IPA_CFG_REG_BASE_PHYS + 0x00000404 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_OFFS(n) ( \ + IPA_CFG_REG_BASE_OFFS + 0x00000404 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_RMSK 0x3f3f3f3f +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_MAXn 4 +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_ATTR 0x3 +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_INI(n) in_dword_masked( \ + HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_ADDR(n), \ + HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_RMSK) +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_ADDR(n), \ + mask) +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_OUTI(n, val) out_dword( \ + HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_ADDR(n), \ + val) +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns(HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_ADDR( \ + n), \ + mask, val, \ + HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_INI(n)) +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_SRC_RSRC_GRP_3_MAX_LIMIT_BMSK \ + 0x3f000000 +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_SRC_RSRC_GRP_3_MAX_LIMIT_SHFT \ + 0x18 +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_SRC_RSRC_GRP_3_MIN_LIMIT_BMSK \ + 0x3f0000 +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_SRC_RSRC_GRP_3_MIN_LIMIT_SHFT \ + 0x10 +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_SRC_RSRC_GRP_2_MAX_LIMIT_BMSK \ + 0x3f00 +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_SRC_RSRC_GRP_2_MAX_LIMIT_SHFT \ + 0x8 +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_SRC_RSRC_GRP_2_MIN_LIMIT_BMSK \ + 0x3f +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_SRC_RSRC_GRP_2_MIN_LIMIT_SHFT \ + 0x0 +#define HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000408 + 0x20 * \ + (n)) +#define HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_PHYS(n) ( \ + IPA_CFG_REG_BASE_PHYS + 0x00000408 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_OFFS(n) ( \ + IPA_CFG_REG_BASE_OFFS + 0x00000408 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_RMSK 0x3f3f +#define HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_MAXn 4 +#define HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_ATTR 0x3 +#define HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_INI(n) in_dword_masked( \ + HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_ADDR(n), \ + HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_RMSK) +#define HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_ADDR(n), \ + mask) +#define HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_OUTI(n, val) out_dword( \ + HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_ADDR(n), \ + val) +#define HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns(HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_ADDR( \ + n), \ + mask, val, \ + HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_INI(n)) +#define HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_SRC_RSRC_GRP_4_MAX_LIMIT_BMSK \ + 0x3f00 +#define HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_SRC_RSRC_GRP_4_MAX_LIMIT_SHFT \ + 0x8 +#define HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_SRC_RSRC_GRP_4_MIN_LIMIT_BMSK \ + 0x3f +#define HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_SRC_RSRC_GRP_4_MIN_LIMIT_SHFT \ + 0x0 +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_ADDR(n) ( \ + IPA_CFG_REG_BASE + 0x00000410 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_PHYS(n) ( \ + IPA_CFG_REG_BASE_PHYS + 0x00000410 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_OFFS(n) ( \ + IPA_CFG_REG_BASE_OFFS + 0x00000410 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_RMSK 0x3f3f3f3f +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_MAXn 4 +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_ATTR 0x1 +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_INI(n) in_dword_masked( \ + HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_ADDR(n), \ + HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_RMSK) +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_INMI(n, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_ADDR(n), \ + mask) +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_SRC_RSRC_GRP_3_CNT_BMSK \ + 0x3f000000 +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_SRC_RSRC_GRP_3_CNT_SHFT \ + 0x18 +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_SRC_RSRC_GRP_2_CNT_BMSK \ + 0x3f0000 +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_SRC_RSRC_GRP_2_CNT_SHFT \ + 0x10 +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_SRC_RSRC_GRP_1_CNT_BMSK \ + 0x3f00 +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_SRC_RSRC_GRP_1_CNT_SHFT \ + 0x8 +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_SRC_RSRC_GRP_0_CNT_BMSK \ + 0x3f +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_SRC_RSRC_GRP_0_CNT_SHFT \ + 0x0 +#define HWIO_IPA_SRC_RSRC_GRP_4567_RSRC_TYPE_CNT_n_ADDR(n) ( \ + IPA_CFG_REG_BASE + 0x00000414 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_GRP_4567_RSRC_TYPE_CNT_n_PHYS(n) ( \ + IPA_CFG_REG_BASE_PHYS + 0x00000414 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_GRP_4567_RSRC_TYPE_CNT_n_OFFS(n) ( \ + IPA_CFG_REG_BASE_OFFS + 0x00000414 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_GRP_4567_RSRC_TYPE_CNT_n_RMSK 0x3f +#define HWIO_IPA_SRC_RSRC_GRP_4567_RSRC_TYPE_CNT_n_MAXn 4 +#define HWIO_IPA_SRC_RSRC_GRP_4567_RSRC_TYPE_CNT_n_ATTR 0x1 +#define HWIO_IPA_SRC_RSRC_GRP_4567_RSRC_TYPE_CNT_n_INI(n) in_dword_masked( \ + HWIO_IPA_SRC_RSRC_GRP_4567_RSRC_TYPE_CNT_n_ADDR(n), \ + HWIO_IPA_SRC_RSRC_GRP_4567_RSRC_TYPE_CNT_n_RMSK) +#define HWIO_IPA_SRC_RSRC_GRP_4567_RSRC_TYPE_CNT_n_INMI(n, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_SRC_RSRC_GRP_4567_RSRC_TYPE_CNT_n_ADDR(n), \ + mask) +#define HWIO_IPA_SRC_RSRC_GRP_4567_RSRC_TYPE_CNT_n_SRC_RSRC_GRP_4_CNT_BMSK \ + 0x3f +#define HWIO_IPA_SRC_RSRC_GRP_4567_RSRC_TYPE_CNT_n_SRC_RSRC_GRP_4_CNT_SHFT \ + 0x0 +#define HWIO_IPA_SRC_RSRC_TYPE_AMOUNT_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000418 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_TYPE_AMOUNT_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000418 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_TYPE_AMOUNT_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000418 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000500 + 0x20 * \ + (n)) +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_PHYS(n) ( \ + IPA_CFG_REG_BASE_PHYS + 0x00000500 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_OFFS(n) ( \ + IPA_CFG_REG_BASE_OFFS + 0x00000500 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_RMSK 0x3f3f3f3f +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_MAXn 1 +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_ATTR 0x3 +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_INI(n) in_dword_masked( \ + HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_ADDR(n), \ + HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_RMSK) +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_ADDR(n), \ + mask) +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_OUTI(n, val) out_dword( \ + HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_ADDR(n), \ + val) +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns(HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_ADDR( \ + n), \ + mask, val, \ + HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_INI(n)) +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_DST_RSRC_GRP_1_MAX_LIMIT_BMSK \ + 0x3f000000 +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_DST_RSRC_GRP_1_MAX_LIMIT_SHFT \ + 0x18 +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_DST_RSRC_GRP_1_MIN_LIMIT_BMSK \ + 0x3f0000 +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_DST_RSRC_GRP_1_MIN_LIMIT_SHFT \ + 0x10 +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_DST_RSRC_GRP_0_MAX_LIMIT_BMSK \ + 0x3f00 +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_DST_RSRC_GRP_0_MAX_LIMIT_SHFT \ + 0x8 +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_DST_RSRC_GRP_0_MIN_LIMIT_BMSK \ + 0x3f +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_DST_RSRC_GRP_0_MIN_LIMIT_SHFT \ + 0x0 +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000504 + 0x20 * \ + (n)) +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_PHYS(n) ( \ + IPA_CFG_REG_BASE_PHYS + 0x00000504 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_OFFS(n) ( \ + IPA_CFG_REG_BASE_OFFS + 0x00000504 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_RMSK 0x3f3f3f3f +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_MAXn 1 +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_ATTR 0x3 +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_INI(n) in_dword_masked( \ + HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_ADDR(n), \ + HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_RMSK) +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_ADDR(n), \ + mask) +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_OUTI(n, val) out_dword( \ + HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_ADDR(n), \ + val) +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns(HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_ADDR( \ + n), \ + mask, val, \ + HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_INI(n)) +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_DST_RSRC_GRP_3_MAX_LIMIT_BMSK \ + 0x3f000000 +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_DST_RSRC_GRP_3_MAX_LIMIT_SHFT \ + 0x18 +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_DST_RSRC_GRP_3_MIN_LIMIT_BMSK \ + 0x3f0000 +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_DST_RSRC_GRP_3_MIN_LIMIT_SHFT \ + 0x10 +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_DST_RSRC_GRP_2_MAX_LIMIT_BMSK \ + 0x3f00 +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_DST_RSRC_GRP_2_MAX_LIMIT_SHFT \ + 0x8 +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_DST_RSRC_GRP_2_MIN_LIMIT_BMSK \ + 0x3f +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_DST_RSRC_GRP_2_MIN_LIMIT_SHFT \ + 0x0 +#define HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000508 + 0x20 * \ + (n)) +#define HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_PHYS(n) ( \ + IPA_CFG_REG_BASE_PHYS + 0x00000508 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_OFFS(n) ( \ + IPA_CFG_REG_BASE_OFFS + 0x00000508 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_RMSK 0x3f3f +#define HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_MAXn 1 +#define HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_ATTR 0x3 +#define HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_INI(n) in_dword_masked( \ + HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_ADDR(n), \ + HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_RMSK) +#define HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_ADDR(n), \ + mask) +#define HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_OUTI(n, val) out_dword( \ + HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_ADDR(n), \ + val) +#define HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns(HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_ADDR( \ + n), \ + mask, val, \ + HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_INI(n)) +#define HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_DST_RSRC_GRP_4_MAX_LIMIT_BMSK \ + 0x3f00 +#define HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_DST_RSRC_GRP_4_MAX_LIMIT_SHFT \ + 0x8 +#define HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_DST_RSRC_GRP_4_MIN_LIMIT_BMSK \ + 0x3f +#define HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_DST_RSRC_GRP_4_MIN_LIMIT_SHFT \ + 0x0 +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_ADDR(n) ( \ + IPA_CFG_REG_BASE + 0x00000510 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_PHYS(n) ( \ + IPA_CFG_REG_BASE_PHYS + 0x00000510 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_OFFS(n) ( \ + IPA_CFG_REG_BASE_OFFS + 0x00000510 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_RMSK 0x3f3f3f3f +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_MAXn 1 +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_ATTR 0x1 +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_INI(n) in_dword_masked( \ + HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_ADDR(n), \ + HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_RMSK) +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_INMI(n, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_ADDR(n), \ + mask) +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_DST_RSRC_GRP_3_CNT_BMSK \ + 0x3f000000 +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_DST_RSRC_GRP_3_CNT_SHFT \ + 0x18 +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_DST_RSRC_GRP_2_CNT_BMSK \ + 0x3f0000 +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_DST_RSRC_GRP_2_CNT_SHFT \ + 0x10 +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_DST_RSRC_GRP_1_CNT_BMSK \ + 0x3f00 +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_DST_RSRC_GRP_1_CNT_SHFT \ + 0x8 +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_DST_RSRC_GRP_0_CNT_BMSK \ + 0x3f +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_DST_RSRC_GRP_0_CNT_SHFT \ + 0x0 +#define HWIO_IPA_DST_RSRC_GRP_4567_RSRC_TYPE_CNT_n_ADDR(n) ( \ + IPA_CFG_REG_BASE + 0x00000514 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_4567_RSRC_TYPE_CNT_n_PHYS(n) ( \ + IPA_CFG_REG_BASE_PHYS + 0x00000514 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_4567_RSRC_TYPE_CNT_n_OFFS(n) ( \ + IPA_CFG_REG_BASE_OFFS + 0x00000514 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_4567_RSRC_TYPE_CNT_n_RMSK 0xff +#define HWIO_IPA_DST_RSRC_GRP_4567_RSRC_TYPE_CNT_n_MAXn 1 +#define HWIO_IPA_DST_RSRC_GRP_4567_RSRC_TYPE_CNT_n_ATTR 0x1 +#define HWIO_IPA_DST_RSRC_GRP_4567_RSRC_TYPE_CNT_n_INI(n) in_dword_masked( \ + HWIO_IPA_DST_RSRC_GRP_4567_RSRC_TYPE_CNT_n_ADDR(n), \ + HWIO_IPA_DST_RSRC_GRP_4567_RSRC_TYPE_CNT_n_RMSK) +#define HWIO_IPA_DST_RSRC_GRP_4567_RSRC_TYPE_CNT_n_INMI(n, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_DST_RSRC_GRP_4567_RSRC_TYPE_CNT_n_ADDR(n), \ + mask) +#define HWIO_IPA_DST_RSRC_GRP_4567_RSRC_TYPE_CNT_n_DST_RSRC_GRP_4_CNT_BMSK \ + 0xff +#define HWIO_IPA_DST_RSRC_GRP_4567_RSRC_TYPE_CNT_n_DST_RSRC_GRP_4_CNT_SHFT \ + 0x0 +#define HWIO_IPA_DST_RSRC_TYPE_AMOUNT_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000518 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_TYPE_AMOUNT_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000518 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_TYPE_AMOUNT_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000518 + 0x20 * (n)) +#define HWIO_IPA_RSRC_GRP_CFG_ADDR (IPA_CFG_REG_BASE + 0x000005a0) +#define HWIO_IPA_RSRC_GRP_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000005a0) +#define HWIO_IPA_RSRC_GRP_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000005a0) +#define HWIO_IPA_RSRC_GRP_CFG_RMSK 0x3f11f171 +#define HWIO_IPA_RSRC_GRP_CFG_ATTR 0x3 +#define HWIO_IPA_RSRC_GRP_CFG_IN in_dword_masked( \ + HWIO_IPA_RSRC_GRP_CFG_ADDR, \ + HWIO_IPA_RSRC_GRP_CFG_RMSK) +#define HWIO_IPA_RSRC_GRP_CFG_INM(m) in_dword_masked( \ + HWIO_IPA_RSRC_GRP_CFG_ADDR, \ + m) +#define HWIO_IPA_RSRC_GRP_CFG_OUT(v) out_dword(HWIO_IPA_RSRC_GRP_CFG_ADDR, \ + v) +#define HWIO_IPA_RSRC_GRP_CFG_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_RSRC_GRP_CFG_ADDR, \ + m, \ + v, \ + HWIO_IPA_RSRC_GRP_CFG_IN) +#define HWIO_IPA_RSRC_GRP_CFG_DST_GRP_SPECIAL_INDEX_BMSK 0x3f000000 +#define HWIO_IPA_RSRC_GRP_CFG_DST_GRP_SPECIAL_INDEX_SHFT 0x18 +#define HWIO_IPA_RSRC_GRP_CFG_DST_GRP_SPECIAL_VALID_BMSK 0x100000 +#define HWIO_IPA_RSRC_GRP_CFG_DST_GRP_SPECIAL_VALID_SHFT 0x14 +#define HWIO_IPA_RSRC_GRP_CFG_DST_PIPE_SPECIAL_INDEX_BMSK 0x1f000 +#define HWIO_IPA_RSRC_GRP_CFG_DST_PIPE_SPECIAL_INDEX_SHFT 0xc +#define HWIO_IPA_RSRC_GRP_CFG_DST_PIPE_SPECIAL_VALID_BMSK 0x100 +#define HWIO_IPA_RSRC_GRP_CFG_DST_PIPE_SPECIAL_VALID_SHFT 0x8 +#define HWIO_IPA_RSRC_GRP_CFG_SRC_GRP_SPECIAL_INDEX_BMSK 0x70 +#define HWIO_IPA_RSRC_GRP_CFG_SRC_GRP_SPECIAL_INDEX_SHFT 0x4 +#define HWIO_IPA_RSRC_GRP_CFG_SRC_GRP_SPECIAL_VALID_BMSK 0x1 +#define HWIO_IPA_RSRC_GRP_CFG_SRC_GRP_SPECIAL_VALID_SHFT 0x0 +#define HWIO_IPA_PIPELINE_DISABLE_ADDR (IPA_CFG_REG_BASE + 0x000005a8) +#define HWIO_IPA_PIPELINE_DISABLE_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000005a8) +#define HWIO_IPA_PIPELINE_DISABLE_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000005a8) +#define HWIO_IPA_PIPELINE_DISABLE_RMSK 0x8 +#define HWIO_IPA_PIPELINE_DISABLE_ATTR 0x3 +#define HWIO_IPA_PIPELINE_DISABLE_IN in_dword_masked( \ + HWIO_IPA_PIPELINE_DISABLE_ADDR, \ + HWIO_IPA_PIPELINE_DISABLE_RMSK) +#define HWIO_IPA_PIPELINE_DISABLE_INM(m) in_dword_masked( \ + HWIO_IPA_PIPELINE_DISABLE_ADDR, \ + m) +#define HWIO_IPA_PIPELINE_DISABLE_OUT(v) out_dword( \ + HWIO_IPA_PIPELINE_DISABLE_ADDR, \ + v) +#define HWIO_IPA_PIPELINE_DISABLE_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_PIPELINE_DISABLE_ADDR, \ + m, \ + v, \ + HWIO_IPA_PIPELINE_DISABLE_IN) +#define HWIO_IPA_PIPELINE_DISABLE_RX_CMDQ_SPLITTER_DIS_BMSK 0x8 +#define HWIO_IPA_PIPELINE_DISABLE_RX_CMDQ_SPLITTER_DIS_SHFT 0x3 +#define HWIO_IPA_AXI_CFG_ADDR (IPA_CFG_REG_BASE + 0x000005ac) +#define HWIO_IPA_AXI_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000005ac) +#define HWIO_IPA_AXI_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000005ac) +#define HWIO_IPA_STAT_QUOTA_BASE_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000700 + 0x4 * (n)) +#define HWIO_IPA_STAT_QUOTA_BASE_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000700 + 0x4 * (n)) +#define HWIO_IPA_STAT_QUOTA_BASE_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000700 + 0x4 * (n)) +#define HWIO_IPA_STAT_QUOTA_MASK_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000708 + 0x4 * (n)) +#define HWIO_IPA_STAT_QUOTA_MASK_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000708 + 0x4 * (n)) +#define HWIO_IPA_STAT_QUOTA_MASK_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000708 + 0x4 * (n)) +#define HWIO_IPA_STAT_TETHERING_BASE_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000710 + 0x4 * (n)) +#define HWIO_IPA_STAT_TETHERING_BASE_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000710 + 0x4 * (n)) +#define HWIO_IPA_STAT_TETHERING_BASE_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000710 + 0x4 * (n)) +#define HWIO_IPA_STAT_TETHERING_MASK_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000718 + 0x4 * (n)) +#define HWIO_IPA_STAT_TETHERING_MASK_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000718 + 0x4 * (n)) +#define HWIO_IPA_STAT_TETHERING_MASK_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000718 + 0x4 * (n)) +#define HWIO_IPA_STAT_FILTER_IPV4_BASE_ADDR (IPA_CFG_REG_BASE + 0x00000720) +#define HWIO_IPA_STAT_FILTER_IPV4_BASE_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000720) +#define HWIO_IPA_STAT_FILTER_IPV4_BASE_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000720) +#define HWIO_IPA_STAT_FILTER_IPV6_BASE_ADDR (IPA_CFG_REG_BASE + 0x00000724) +#define HWIO_IPA_STAT_FILTER_IPV6_BASE_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000724) +#define HWIO_IPA_STAT_FILTER_IPV6_BASE_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000724) +#define HWIO_IPA_STAT_ROUTER_IPV4_BASE_ADDR (IPA_CFG_REG_BASE + 0x00000728) +#define HWIO_IPA_STAT_ROUTER_IPV4_BASE_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000728) +#define HWIO_IPA_STAT_ROUTER_IPV4_BASE_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000728) +#define HWIO_IPA_STAT_ROUTER_IPV6_BASE_ADDR (IPA_CFG_REG_BASE + 0x0000072c) +#define HWIO_IPA_STAT_ROUTER_IPV6_BASE_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x0000072c) +#define HWIO_IPA_STAT_ROUTER_IPV6_BASE_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x0000072c) +#define HWIO_IPA_STAT_DROP_CNT_BASE_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000750 + 0x4 * (n)) +#define HWIO_IPA_STAT_DROP_CNT_BASE_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000750 + 0x4 * (n)) +#define HWIO_IPA_STAT_DROP_CNT_BASE_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000750 + 0x4 * (n)) +#define HWIO_IPA_STAT_DROP_CNT_MASK_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000758 + 0x4 * (n)) +#define HWIO_IPA_STAT_DROP_CNT_MASK_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000758 + 0x4 * (n)) +#define HWIO_IPA_STAT_DROP_CNT_MASK_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000758 + 0x4 * (n)) +#define HWIO_IPA_ENDP_INIT_CTRL_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000800 + \ + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_CTRL_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000800 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_CTRL_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000800 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_CTRL_n_RMSK 0x3 +#define HWIO_IPA_ENDP_INIT_CTRL_n_MAXn 30 +#define HWIO_IPA_ENDP_INIT_CTRL_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_CTRL_n_INI(n) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_CTRL_n_ADDR(n), \ + HWIO_IPA_ENDP_INIT_CTRL_n_RMSK) +#define HWIO_IPA_ENDP_INIT_CTRL_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_CTRL_n_ADDR(n), \ + mask) +#define HWIO_IPA_ENDP_INIT_CTRL_n_OUTI(n, val) out_dword( \ + HWIO_IPA_ENDP_INIT_CTRL_n_ADDR(n), \ + val) +#define HWIO_IPA_ENDP_INIT_CTRL_n_OUTMI(n, mask, val) out_dword_masked_ns( \ + HWIO_IPA_ENDP_INIT_CTRL_n_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_ENDP_INIT_CTRL_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_CTRL_n_ENDP_DELAY_BMSK 0x2 +#define HWIO_IPA_ENDP_INIT_CTRL_n_ENDP_DELAY_SHFT 0x1 +#define HWIO_IPA_ENDP_INIT_CTRL_n_ENDP_SUSPEND_BMSK 0x1 +#define HWIO_IPA_ENDP_INIT_CTRL_n_ENDP_SUSPEND_SHFT 0x0 +#define HWIO_IPA_ENDP_INIT_CTRL_SCND_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000804 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_CTRL_SCND_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000804 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_CTRL_SCND_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000804 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_CTRL_SCND_n_RMSK 0x2 +#define HWIO_IPA_ENDP_INIT_CTRL_SCND_n_MAXn 30 +#define HWIO_IPA_ENDP_INIT_CTRL_SCND_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_CTRL_SCND_n_INI(n) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_CTRL_SCND_n_ADDR(n), \ + HWIO_IPA_ENDP_INIT_CTRL_SCND_n_RMSK) +#define HWIO_IPA_ENDP_INIT_CTRL_SCND_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_CTRL_SCND_n_ADDR(n), \ + mask) +#define HWIO_IPA_ENDP_INIT_CTRL_SCND_n_OUTI(n, val) out_dword( \ + HWIO_IPA_ENDP_INIT_CTRL_SCND_n_ADDR(n), \ + val) +#define HWIO_IPA_ENDP_INIT_CTRL_SCND_n_OUTMI(n, mask, \ + val) out_dword_masked_ns( \ + HWIO_IPA_ENDP_INIT_CTRL_SCND_n_ADDR( \ + n), \ + mask, \ + val, \ + HWIO_IPA_ENDP_INIT_CTRL_SCND_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_CTRL_SCND_n_ENDP_DELAY_BMSK 0x2 +#define HWIO_IPA_ENDP_INIT_CTRL_SCND_n_ENDP_DELAY_SHFT 0x1 +#define HWIO_IPA_ENDP_INIT_CFG_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000808 + \ + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_CFG_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000808 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_CFG_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000808 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_CFG_n_RMSK 0x17f +#define HWIO_IPA_ENDP_INIT_CFG_n_MAXn 30 +#define HWIO_IPA_ENDP_INIT_CFG_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_CFG_n_INI(n) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_CFG_n_ADDR(n), \ + HWIO_IPA_ENDP_INIT_CFG_n_RMSK) +#define HWIO_IPA_ENDP_INIT_CFG_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_CFG_n_ADDR(n), \ + mask) +#define HWIO_IPA_ENDP_INIT_CFG_n_OUTI(n, val) out_dword( \ + HWIO_IPA_ENDP_INIT_CFG_n_ADDR(n), \ + val) +#define HWIO_IPA_ENDP_INIT_CFG_n_OUTMI(n, mask, val) out_dword_masked_ns( \ + HWIO_IPA_ENDP_INIT_CFG_n_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_ENDP_INIT_CFG_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_CFG_n_GEN_QMB_MASTER_SEL_BMSK 0x100 +#define HWIO_IPA_ENDP_INIT_CFG_n_GEN_QMB_MASTER_SEL_SHFT 0x8 +#define HWIO_IPA_ENDP_INIT_CFG_n_CS_METADATA_HDR_OFFSET_BMSK 0x78 +#define HWIO_IPA_ENDP_INIT_CFG_n_CS_METADATA_HDR_OFFSET_SHFT 0x3 +#define HWIO_IPA_ENDP_INIT_CFG_n_CS_OFFLOAD_EN_BMSK 0x6 +#define HWIO_IPA_ENDP_INIT_CFG_n_CS_OFFLOAD_EN_SHFT 0x1 +#define HWIO_IPA_ENDP_INIT_CFG_n_FRAG_OFFLOAD_EN_BMSK 0x1 +#define HWIO_IPA_ENDP_INIT_CFG_n_FRAG_OFFLOAD_EN_SHFT 0x0 +#define HWIO_IPA_ENDP_INIT_NAT_n_ADDR(n) (IPA_CFG_REG_BASE + 0x0000080c + \ + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_NAT_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x0000080c + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_NAT_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x0000080c + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_NAT_n_RMSK 0x3 +#define HWIO_IPA_ENDP_INIT_NAT_n_MAXn 12 +#define HWIO_IPA_ENDP_INIT_NAT_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_NAT_n_INI(n) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_NAT_n_ADDR(n), \ + HWIO_IPA_ENDP_INIT_NAT_n_RMSK) +#define HWIO_IPA_ENDP_INIT_NAT_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_NAT_n_ADDR(n), \ + mask) +#define HWIO_IPA_ENDP_INIT_NAT_n_OUTI(n, val) out_dword( \ + HWIO_IPA_ENDP_INIT_NAT_n_ADDR(n), \ + val) +#define HWIO_IPA_ENDP_INIT_NAT_n_OUTMI(n, mask, val) out_dword_masked_ns( \ + HWIO_IPA_ENDP_INIT_NAT_n_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_ENDP_INIT_NAT_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_NAT_n_NAT_EN_BMSK 0x3 +#define HWIO_IPA_ENDP_INIT_NAT_n_NAT_EN_SHFT 0x0 +#define HWIO_IPA_ENDP_INIT_HDR_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000810 + \ + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_HDR_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000810 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_HDR_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000810 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_HDR_n_RMSK 0xffffffff +#define HWIO_IPA_ENDP_INIT_HDR_n_MAXn 30 +#define HWIO_IPA_ENDP_INIT_HDR_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_HDR_n_INI(n) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_HDR_n_ADDR(n), \ + HWIO_IPA_ENDP_INIT_HDR_n_RMSK) +#define HWIO_IPA_ENDP_INIT_HDR_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_HDR_n_ADDR(n), \ + mask) +#define HWIO_IPA_ENDP_INIT_HDR_n_OUTI(n, val) out_dword( \ + HWIO_IPA_ENDP_INIT_HDR_n_ADDR(n), \ + val) +#define HWIO_IPA_ENDP_INIT_HDR_n_OUTMI(n, mask, val) out_dword_masked_ns( \ + HWIO_IPA_ENDP_INIT_HDR_n_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_ENDP_INIT_HDR_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_MSB_BMSK 0xc0000000 +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_MSB_SHFT 0x1e +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_LEN_MSB_BMSK 0x30000000 +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_LEN_MSB_SHFT 0x1c +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_LEN_INC_DEAGG_HDR_BMSK 0x8000000 +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_LEN_INC_DEAGG_HDR_SHFT 0x1b +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_A5_MUX_BMSK 0x4000000 +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_A5_MUX_SHFT 0x1a +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_OFST_PKT_SIZE_BMSK 0x3f00000 +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_OFST_PKT_SIZE_SHFT 0x14 +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_OFST_PKT_SIZE_VALID_BMSK 0x80000 +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_OFST_PKT_SIZE_VALID_SHFT 0x13 +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_ADDITIONAL_CONST_LEN_BMSK 0x7e000 +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_ADDITIONAL_CONST_LEN_SHFT 0xd +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_BMSK 0x1f80 +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_SHFT 0x7 +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_VALID_BMSK 0x40 +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_VALID_SHFT 0x6 +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_LEN_BMSK 0x3f +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_LEN_SHFT 0x0 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000814 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000814 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000814 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_RMSK 0x3f3fff +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_MAXn 30 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_INI(n) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_HDR_EXT_n_ADDR(n), \ + HWIO_IPA_ENDP_INIT_HDR_EXT_n_RMSK) +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_HDR_EXT_n_ADDR(n), \ + mask) +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_OUTI(n, val) out_dword( \ + HWIO_IPA_ENDP_INIT_HDR_EXT_n_ADDR(n), \ + val) +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_OUTMI(n, mask, \ + val) out_dword_masked_ns( \ + HWIO_IPA_ENDP_INIT_HDR_EXT_n_ADDR( \ + n), \ + mask, \ + val, \ + HWIO_IPA_ENDP_INIT_HDR_EXT_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_ADDITIONAL_CONST_LEN_MSB_BMSK \ + 0x300000 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_ADDITIONAL_CONST_LEN_MSB_SHFT \ + 0x14 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_OFST_PKT_SIZE_MSB_BMSK 0xc0000 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_OFST_PKT_SIZE_MSB_SHFT 0x12 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB_BMSK \ + 0x30000 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB_SHFT \ + 0x10 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_PAD_TO_ALIGNMENT_BMSK 0x3c00 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_PAD_TO_ALIGNMENT_SHFT 0xa +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_OFFSET_BMSK \ + 0x3f0 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_OFFSET_SHFT 0x4 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_PAYLOAD_LEN_INC_PADDING_BMSK 0x8 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_PAYLOAD_LEN_INC_PADDING_SHFT 0x3 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_BMSK 0x4 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_SHFT 0x2 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_VALID_BMSK 0x2 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_VALID_SHFT 0x1 +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000818 + \ + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_PHYS(n) ( \ + IPA_CFG_REG_BASE_PHYS + 0x00000818 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_OFFS(n) ( \ + IPA_CFG_REG_BASE_OFFS + 0x00000818 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_RMSK 0xffffffff +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_MAXn 30 +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_INI(n) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_ADDR(n), \ + HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_RMSK) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_INMI(n, \ + mask) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_ADDR( \ + n), \ + mask) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_OUTI(n, val) out_dword( \ + HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_ADDR(n), \ + val) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_METADATA_MASK_BMSK \ + 0xffffffff +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_METADATA_MASK_SHFT 0x0 +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x0000081c + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x0000081c + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x0000081c + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_n_RMSK 0xffffffff +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_n_MAXn 12 +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_n_INI(n) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_HDR_METADATA_n_ADDR(n), \ + HWIO_IPA_ENDP_INIT_HDR_METADATA_n_RMSK) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_HDR_METADATA_n_ADDR(n), \ + mask) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_n_OUTI(n, val) out_dword( \ + HWIO_IPA_ENDP_INIT_HDR_METADATA_n_ADDR(n), \ + val) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_n_OUTMI(n, mask, \ + val) out_dword_masked_ns( \ + HWIO_IPA_ENDP_INIT_HDR_METADATA_n_ADDR( \ + n), \ + mask, \ + val, \ + HWIO_IPA_ENDP_INIT_HDR_METADATA_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_n_METADATA_BMSK 0xffffffff +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_n_METADATA_SHFT 0x0 +#define HWIO_IPA_ENDP_INIT_MODE_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000820 + \ + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_MODE_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000820 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_MODE_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000820 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_MODE_n_RMSK 0x3ffff1ff +#define HWIO_IPA_ENDP_INIT_MODE_n_MAXn 12 +#define HWIO_IPA_ENDP_INIT_MODE_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_MODE_n_INI(n) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_MODE_n_ADDR(n), \ + HWIO_IPA_ENDP_INIT_MODE_n_RMSK) +#define HWIO_IPA_ENDP_INIT_MODE_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_MODE_n_ADDR(n), \ + mask) +#define HWIO_IPA_ENDP_INIT_MODE_n_OUTI(n, val) out_dword( \ + HWIO_IPA_ENDP_INIT_MODE_n_ADDR(n), \ + val) +#define HWIO_IPA_ENDP_INIT_MODE_n_OUTMI(n, mask, val) out_dword_masked_ns( \ + HWIO_IPA_ENDP_INIT_MODE_n_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_ENDP_INIT_MODE_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_MODE_n_PAD_EN_BMSK 0x20000000 +#define HWIO_IPA_ENDP_INIT_MODE_n_PAD_EN_SHFT 0x1d +#define HWIO_IPA_ENDP_INIT_MODE_n_PIPE_REPLICATE_EN_BMSK 0x10000000 +#define HWIO_IPA_ENDP_INIT_MODE_n_PIPE_REPLICATE_EN_SHFT 0x1c +#define HWIO_IPA_ENDP_INIT_MODE_n_BYTE_THRESHOLD_BMSK 0xffff000 +#define HWIO_IPA_ENDP_INIT_MODE_n_BYTE_THRESHOLD_SHFT 0xc +#define HWIO_IPA_ENDP_INIT_MODE_n_DEST_PIPE_INDEX_BMSK 0x1f0 +#define HWIO_IPA_ENDP_INIT_MODE_n_DEST_PIPE_INDEX_SHFT 0x4 +#define HWIO_IPA_ENDP_INIT_MODE_n_DCPH_ENABLE_BMSK 0x8 +#define HWIO_IPA_ENDP_INIT_MODE_n_DCPH_ENABLE_SHFT 0x3 +#define HWIO_IPA_ENDP_INIT_MODE_n_MODE_BMSK 0x7 +#define HWIO_IPA_ENDP_INIT_MODE_n_MODE_SHFT 0x0 +#define HWIO_IPA_ENDP_INIT_AGGR_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000824 + \ + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_AGGR_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000824 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_AGGR_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000824 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_AGGR_n_RMSK 0xdfff7ff +#define HWIO_IPA_ENDP_INIT_AGGR_n_MAXn 30 +#define HWIO_IPA_ENDP_INIT_AGGR_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_AGGR_n_INI(n) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_AGGR_n_ADDR(n), \ + HWIO_IPA_ENDP_INIT_AGGR_n_RMSK) +#define HWIO_IPA_ENDP_INIT_AGGR_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_AGGR_n_ADDR(n), \ + mask) +#define HWIO_IPA_ENDP_INIT_AGGR_n_OUTI(n, val) out_dword( \ + HWIO_IPA_ENDP_INIT_AGGR_n_ADDR(n), \ + val) +#define HWIO_IPA_ENDP_INIT_AGGR_n_OUTMI(n, mask, val) out_dword_masked_ns( \ + HWIO_IPA_ENDP_INIT_AGGR_n_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_ENDP_INIT_AGGR_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_GRAN_SEL_BMSK 0x8000000 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_GRAN_SEL_SHFT 0x1b +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_HARD_BYTE_LIMIT_ENABLE_BMSK \ + 0x4000000 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_HARD_BYTE_LIMIT_ENABLE_SHFT 0x1a +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_FORCE_CLOSE_BMSK 0x1000000 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_FORCE_CLOSE_SHFT 0x18 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_SW_EOF_ACTIVE_BMSK 0x800000 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_SW_EOF_ACTIVE_SHFT 0x17 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_PKT_LIMIT_BMSK 0x7e0000 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_PKT_LIMIT_SHFT 0x11 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_TIME_LIMIT_BMSK 0x1f000 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_TIME_LIMIT_SHFT 0xc +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_BYTE_LIMIT_BMSK 0x7e0 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_BYTE_LIMIT_SHFT 0x5 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_TYPE_BMSK 0x1c +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_TYPE_SHFT 0x2 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_EN_BMSK 0x3 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_EN_SHFT 0x0 +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x0000082c + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x0000082c + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x0000082c + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_RMSK 0x1 +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_MAXn 30 +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_INI(n) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_ADDR(n), \ + HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_RMSK) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_ADDR(n), \ + mask) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_OUTI(n, val) out_dword( \ + HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_ADDR(n), \ + val) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_OUTMI(n, mask, \ + val) out_dword_masked_ns( \ + HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_ADDR( \ + n), \ + mask, \ + val, \ + HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_EN_BMSK 0x1 +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_EN_SHFT 0x0 +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000830 + 0x70 * \ + (n)) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_PHYS(n) ( \ + IPA_CFG_REG_BASE_PHYS + 0x00000830 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_OFFS(n) ( \ + IPA_CFG_REG_BASE_OFFS + 0x00000830 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_RMSK 0x11f +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_MAXn 30 +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_INI(n) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_ADDR(n), \ + HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_RMSK) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_ADDR(n), \ + mask) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_OUTI(n, val) out_dword( \ + HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_ADDR(n), \ + val) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns(HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_ADDR( \ + n), \ + mask, val, \ + HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_GRAN_SEL_BMSK 0x100 +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_GRAN_SEL_SHFT 0x8 +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_TIME_LIMIT_BMSK 0x1f +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_TIME_LIMIT_SHFT 0x0 +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000834 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000834 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000834 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_RMSK 0xffff7fff +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_MAXn 12 +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_INI(n) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_DEAGGR_n_ADDR(n), \ + HWIO_IPA_ENDP_INIT_DEAGGR_n_RMSK) +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_DEAGGR_n_ADDR(n), \ + mask) +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_OUTI(n, val) out_dword( \ + HWIO_IPA_ENDP_INIT_DEAGGR_n_ADDR(n), \ + val) +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_OUTMI(n, mask, \ + val) out_dword_masked_ns( \ + HWIO_IPA_ENDP_INIT_DEAGGR_n_ADDR( \ + n), \ + mask, \ + val, \ + HWIO_IPA_ENDP_INIT_DEAGGR_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_MAX_PACKET_LEN_BMSK 0xffff0000 +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_MAX_PACKET_LEN_SHFT 0x10 +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_IGNORE_MIN_PKT_ERR_BMSK 0x4000 +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_IGNORE_MIN_PKT_ERR_SHFT 0xe +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_PACKET_OFFSET_LOCATION_BMSK 0x3f00 +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_PACKET_OFFSET_LOCATION_SHFT 0x8 +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_PACKET_OFFSET_VALID_BMSK 0x80 +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_PACKET_OFFSET_VALID_SHFT 0x7 +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_SYSPIPE_ERR_DETECTION_BMSK 0x40 +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_SYSPIPE_ERR_DETECTION_SHFT 0x6 +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_DEAGGR_HDR_LEN_BMSK 0x3f +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_DEAGGR_HDR_LEN_SHFT 0x0 +#define HWIO_IPA_ENDP_INIT_RSRC_GRP_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000838 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_RSRC_GRP_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000838 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_RSRC_GRP_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000838 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_RSRC_GRP_n_RMSK 0x7 +#define HWIO_IPA_ENDP_INIT_RSRC_GRP_n_MAXn 30 +#define HWIO_IPA_ENDP_INIT_RSRC_GRP_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_RSRC_GRP_n_INI(n) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_RSRC_GRP_n_ADDR(n), \ + HWIO_IPA_ENDP_INIT_RSRC_GRP_n_RMSK) +#define HWIO_IPA_ENDP_INIT_RSRC_GRP_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_RSRC_GRP_n_ADDR(n), \ + mask) +#define HWIO_IPA_ENDP_INIT_RSRC_GRP_n_OUTI(n, val) out_dword( \ + HWIO_IPA_ENDP_INIT_RSRC_GRP_n_ADDR(n), \ + val) +#define HWIO_IPA_ENDP_INIT_RSRC_GRP_n_OUTMI(n, mask, \ + val) out_dword_masked_ns( \ + HWIO_IPA_ENDP_INIT_RSRC_GRP_n_ADDR( \ + n), \ + mask, \ + val, \ + HWIO_IPA_ENDP_INIT_RSRC_GRP_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_BMSK 0x7 +#define HWIO_IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_SHFT 0x0 +#define HWIO_IPA_ENDP_INIT_SEQ_n_ADDR(n) (IPA_CFG_REG_BASE + 0x0000083c + \ + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_SEQ_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x0000083c + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_SEQ_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x0000083c + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_SEQ_n_RMSK 0xffff +#define HWIO_IPA_ENDP_INIT_SEQ_n_MAXn 12 +#define HWIO_IPA_ENDP_INIT_SEQ_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_SEQ_n_INI(n) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_SEQ_n_ADDR(n), \ + HWIO_IPA_ENDP_INIT_SEQ_n_RMSK) +#define HWIO_IPA_ENDP_INIT_SEQ_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_SEQ_n_ADDR(n), \ + mask) +#define HWIO_IPA_ENDP_INIT_SEQ_n_OUTI(n, val) out_dword( \ + HWIO_IPA_ENDP_INIT_SEQ_n_ADDR(n), \ + val) +#define HWIO_IPA_ENDP_INIT_SEQ_n_OUTMI(n, mask, val) out_dword_masked_ns( \ + HWIO_IPA_ENDP_INIT_SEQ_n_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_ENDP_INIT_SEQ_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_SEQ_n_DPS_REP_SEQ_TYPE_BMSK 0xf000 +#define HWIO_IPA_ENDP_INIT_SEQ_n_DPS_REP_SEQ_TYPE_SHFT 0xc +#define HWIO_IPA_ENDP_INIT_SEQ_n_HPS_REP_SEQ_TYPE_BMSK 0xf00 +#define HWIO_IPA_ENDP_INIT_SEQ_n_HPS_REP_SEQ_TYPE_SHFT 0x8 +#define HWIO_IPA_ENDP_INIT_SEQ_n_DPS_SEQ_TYPE_BMSK 0xf0 +#define HWIO_IPA_ENDP_INIT_SEQ_n_DPS_SEQ_TYPE_SHFT 0x4 +#define HWIO_IPA_ENDP_INIT_SEQ_n_HPS_SEQ_TYPE_BMSK 0xf +#define HWIO_IPA_ENDP_INIT_SEQ_n_HPS_SEQ_TYPE_SHFT 0x0 +#define HWIO_IPA_ENDP_STATUS_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000840 + \ + 0x70 * (n)) +#define HWIO_IPA_ENDP_STATUS_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000840 + 0x70 * (n)) +#define HWIO_IPA_ENDP_STATUS_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000840 + 0x70 * (n)) +#define HWIO_IPA_ENDP_STATUS_n_RMSK 0x23f +#define HWIO_IPA_ENDP_STATUS_n_MAXn 30 +#define HWIO_IPA_ENDP_STATUS_n_ATTR 0x3 +#define HWIO_IPA_ENDP_STATUS_n_INI(n) in_dword_masked( \ + HWIO_IPA_ENDP_STATUS_n_ADDR(n), \ + HWIO_IPA_ENDP_STATUS_n_RMSK) +#define HWIO_IPA_ENDP_STATUS_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_ENDP_STATUS_n_ADDR(n), \ + mask) +#define HWIO_IPA_ENDP_STATUS_n_OUTI(n, val) out_dword( \ + HWIO_IPA_ENDP_STATUS_n_ADDR(n), \ + val) +#define HWIO_IPA_ENDP_STATUS_n_OUTMI(n, mask, val) out_dword_masked_ns( \ + HWIO_IPA_ENDP_STATUS_n_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_ENDP_STATUS_n_INI(n)) +#define HWIO_IPA_ENDP_STATUS_n_STATUS_ENDP_BMSK 0x3e +#define HWIO_IPA_ENDP_STATUS_n_STATUS_ENDP_SHFT 0x1 +#define HWIO_IPA_ENDP_STATUS_n_STATUS_EN_BMSK 0x1 +#define HWIO_IPA_ENDP_STATUS_n_STATUS_EN_SHFT 0x0 +#define HWIO_IPA_ENDP_SRC_ID_WRITE_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000848 + 0x70 * (n)) +#define HWIO_IPA_ENDP_SRC_ID_WRITE_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000848 + 0x70 * (n)) +#define HWIO_IPA_ENDP_SRC_ID_WRITE_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000848 + 0x70 * (n)) +#define HWIO_IPA_ENDP_SRC_ID_READ_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x0000084c + 0x70 * (n)) +#define HWIO_IPA_ENDP_SRC_ID_READ_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x0000084c + 0x70 * (n)) +#define HWIO_IPA_ENDP_SRC_ID_READ_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x0000084c + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_CONN_TRACK_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000850 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_CONN_TRACK_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000850 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_CONN_TRACK_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000850 + 0x70 * (n)) +#define HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x0000085c + 0x70 * \ + (n)) +#define HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_PHYS(n) ( \ + IPA_CFG_REG_BASE_PHYS + 0x0000085c + 0x70 * (n)) +#define HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_OFFS(n) ( \ + IPA_CFG_REG_BASE_OFFS + 0x0000085c + 0x70 * (n)) +#define HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_RMSK 0x7f007f +#define HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_MAXn 31 +#define HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ATTR 0x3 +#define HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_INI(n) in_dword_masked( \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ADDR(n), \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_RMSK) +#define HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_INMI(n, \ + mask) in_dword_masked( \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ADDR( \ + n), \ + mask) +#define HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_OUTI(n, val) out_dword( \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ADDR(n), \ + val) +#define HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns(HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ADDR( \ + n), \ + mask, val, \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_INI(n)) +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_METADATA_BMSK \ + 0x400000 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_METADATA_SHFT \ + 0x16 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_PROTOCOL_BMSK \ + 0x200000 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_PROTOCOL_SHFT \ + 0x15 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_DST_PORT_BMSK \ + 0x100000 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_DST_PORT_SHFT \ + 0x14 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_SRC_PORT_BMSK \ + 0x80000 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_SRC_PORT_SHFT \ + 0x13 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_DST_IP_ADD_BMSK \ + 0x40000 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_DST_IP_ADD_SHFT \ + 0x12 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_SRC_IP_ADD_BMSK \ + 0x20000 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_SRC_IP_ADD_SHFT \ + 0x11 +#define HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_SRC_ID_BMSK \ + 0x10000 +#define HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_SRC_ID_SHFT \ + 0x10 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_METADATA_BMSK \ + 0x40 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_METADATA_SHFT \ + 0x6 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_PROTOCOL_BMSK \ + 0x20 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_PROTOCOL_SHFT \ + 0x5 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_DST_PORT_BMSK \ + 0x10 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_DST_PORT_SHFT \ + 0x4 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_SRC_PORT_BMSK \ + 0x8 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_SRC_PORT_SHFT \ + 0x3 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_DST_IP_ADD_BMSK \ + 0x4 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_DST_IP_ADD_SHFT \ + 0x2 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_SRC_IP_ADD_BMSK \ + 0x2 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_SRC_IP_ADD_SHFT \ + 0x1 +#define HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_SRC_ID_BMSK \ + 0x1 +#define HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_SRC_ID_SHFT \ + 0x0 +#define HWIO_IPA_ENDP_YELLOW_RED_MARKER_CFG_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000860 + 0x70 * \ + (n)) +#define HWIO_IPA_ENDP_YELLOW_RED_MARKER_CFG_n_PHYS(n) ( \ + IPA_CFG_REG_BASE_PHYS + 0x00000860 + 0x70 * (n)) +#define HWIO_IPA_ENDP_YELLOW_RED_MARKER_CFG_n_OFFS(n) ( \ + IPA_CFG_REG_BASE_OFFS + 0x00000860 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_CTRL_STATUS_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000864 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_CTRL_STATUS_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000864 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_CTRL_STATUS_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000864 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_PROD_CFG_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000868 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_PROD_CFG_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000868 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_PROD_CFG_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000868 + 0x70 * (n)) +#define HWIO_IPA_NLO_PP_CFG1_ADDR (IPA_CFG_REG_BASE + 0x00001680) +#define HWIO_IPA_NLO_PP_CFG1_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00001680) +#define HWIO_IPA_NLO_PP_CFG1_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00001680) +#define HWIO_IPA_NLO_PP_CFG1_RMSK 0x3fffffff +#define HWIO_IPA_NLO_PP_CFG1_ATTR 0x3 +#define HWIO_IPA_NLO_PP_CFG1_IN in_dword_masked(HWIO_IPA_NLO_PP_CFG1_ADDR, \ + HWIO_IPA_NLO_PP_CFG1_RMSK) +#define HWIO_IPA_NLO_PP_CFG1_INM(m) in_dword_masked( \ + HWIO_IPA_NLO_PP_CFG1_ADDR, \ + m) +#define HWIO_IPA_NLO_PP_CFG1_OUT(v) out_dword(HWIO_IPA_NLO_PP_CFG1_ADDR, v) +#define HWIO_IPA_NLO_PP_CFG1_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_NLO_PP_CFG1_ADDR, \ + m, \ + v, \ + HWIO_IPA_NLO_PP_CFG1_IN) +#define HWIO_IPA_NLO_PP_CFG1_NLO_ACK_MAX_VP_BMSK 0x3f000000 +#define HWIO_IPA_NLO_PP_CFG1_NLO_ACK_MAX_VP_SHFT 0x18 +#define HWIO_IPA_NLO_PP_CFG1_NLO_STATUS_PP_BMSK 0xff0000 +#define HWIO_IPA_NLO_PP_CFG1_NLO_STATUS_PP_SHFT 0x10 +#define HWIO_IPA_NLO_PP_CFG1_NLO_DATA_PP_BMSK 0xff00 +#define HWIO_IPA_NLO_PP_CFG1_NLO_DATA_PP_SHFT 0x8 +#define HWIO_IPA_NLO_PP_CFG1_NLO_ACK_PP_BMSK 0xff +#define HWIO_IPA_NLO_PP_CFG1_NLO_ACK_PP_SHFT 0x0 +#define HWIO_IPA_NLO_PP_CFG2_ADDR (IPA_CFG_REG_BASE + 0x00001684) +#define HWIO_IPA_NLO_PP_CFG2_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00001684) +#define HWIO_IPA_NLO_PP_CFG2_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00001684) +#define HWIO_IPA_NLO_PP_CFG2_RMSK 0x7ffff +#define HWIO_IPA_NLO_PP_CFG2_ATTR 0x3 +#define HWIO_IPA_NLO_PP_CFG2_IN in_dword_masked(HWIO_IPA_NLO_PP_CFG2_ADDR, \ + HWIO_IPA_NLO_PP_CFG2_RMSK) +#define HWIO_IPA_NLO_PP_CFG2_INM(m) in_dword_masked( \ + HWIO_IPA_NLO_PP_CFG2_ADDR, \ + m) +#define HWIO_IPA_NLO_PP_CFG2_OUT(v) out_dword(HWIO_IPA_NLO_PP_CFG2_ADDR, v) +#define HWIO_IPA_NLO_PP_CFG2_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_NLO_PP_CFG2_ADDR, \ + m, \ + v, \ + HWIO_IPA_NLO_PP_CFG2_IN) +#define HWIO_IPA_NLO_PP_CFG2_NLO_STATUS_BUFFER_MODE_BMSK 0x40000 +#define HWIO_IPA_NLO_PP_CFG2_NLO_STATUS_BUFFER_MODE_SHFT 0x12 +#define HWIO_IPA_NLO_PP_CFG2_NLO_DATA_BUFFER_MODE_BMSK 0x20000 +#define HWIO_IPA_NLO_PP_CFG2_NLO_DATA_BUFFER_MODE_SHFT 0x11 +#define HWIO_IPA_NLO_PP_CFG2_NLO_ACK_BUFFER_MODE_BMSK 0x10000 +#define HWIO_IPA_NLO_PP_CFG2_NLO_ACK_BUFFER_MODE_SHFT 0x10 +#define HWIO_IPA_NLO_PP_CFG2_NLO_DATA_CLOSE_PADD_BMSK 0xff00 +#define HWIO_IPA_NLO_PP_CFG2_NLO_DATA_CLOSE_PADD_SHFT 0x8 +#define HWIO_IPA_NLO_PP_CFG2_NLO_ACK_CLOSE_PADD_BMSK 0xff +#define HWIO_IPA_NLO_PP_CFG2_NLO_ACK_CLOSE_PADD_SHFT 0x0 +#define HWIO_IPA_NLO_PP_ACK_LIMIT_CFG_ADDR (IPA_CFG_REG_BASE + 0x00001688) +#define HWIO_IPA_NLO_PP_ACK_LIMIT_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00001688) +#define HWIO_IPA_NLO_PP_ACK_LIMIT_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00001688) +#define HWIO_IPA_NLO_PP_ACK_LIMIT_CFG_RMSK 0xffffffff +#define HWIO_IPA_NLO_PP_ACK_LIMIT_CFG_ATTR 0x3 +#define HWIO_IPA_NLO_PP_ACK_LIMIT_CFG_IN in_dword_masked( \ + HWIO_IPA_NLO_PP_ACK_LIMIT_CFG_ADDR, \ + HWIO_IPA_NLO_PP_ACK_LIMIT_CFG_RMSK) +#define HWIO_IPA_NLO_PP_ACK_LIMIT_CFG_INM(m) in_dword_masked( \ + HWIO_IPA_NLO_PP_ACK_LIMIT_CFG_ADDR, \ + m) +#define HWIO_IPA_NLO_PP_ACK_LIMIT_CFG_OUT(v) out_dword( \ + HWIO_IPA_NLO_PP_ACK_LIMIT_CFG_ADDR, \ + v) +#define HWIO_IPA_NLO_PP_ACK_LIMIT_CFG_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_NLO_PP_ACK_LIMIT_CFG_ADDR, \ + m, \ + v, \ + HWIO_IPA_NLO_PP_ACK_LIMIT_CFG_IN) +#define HWIO_IPA_NLO_PP_ACK_LIMIT_CFG_NLO_ACK_UPPER_SIZE_BMSK 0xffff0000 +#define HWIO_IPA_NLO_PP_ACK_LIMIT_CFG_NLO_ACK_UPPER_SIZE_SHFT 0x10 +#define HWIO_IPA_NLO_PP_ACK_LIMIT_CFG_NLO_ACK_LOWER_SIZE_BMSK 0xffff +#define HWIO_IPA_NLO_PP_ACK_LIMIT_CFG_NLO_ACK_LOWER_SIZE_SHFT 0x0 +#define HWIO_IPA_NLO_PP_DATA_LIMIT_CFG_ADDR (IPA_CFG_REG_BASE + 0x0000168c) +#define HWIO_IPA_NLO_PP_DATA_LIMIT_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x0000168c) +#define HWIO_IPA_NLO_PP_DATA_LIMIT_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x0000168c) +#define HWIO_IPA_NLO_PP_DATA_LIMIT_CFG_RMSK 0xffffffff +#define HWIO_IPA_NLO_PP_DATA_LIMIT_CFG_ATTR 0x3 +#define HWIO_IPA_NLO_PP_DATA_LIMIT_CFG_IN in_dword_masked( \ + HWIO_IPA_NLO_PP_DATA_LIMIT_CFG_ADDR, \ + HWIO_IPA_NLO_PP_DATA_LIMIT_CFG_RMSK) +#define HWIO_IPA_NLO_PP_DATA_LIMIT_CFG_INM(m) in_dword_masked( \ + HWIO_IPA_NLO_PP_DATA_LIMIT_CFG_ADDR, \ + m) +#define HWIO_IPA_NLO_PP_DATA_LIMIT_CFG_OUT(v) out_dword( \ + HWIO_IPA_NLO_PP_DATA_LIMIT_CFG_ADDR, \ + v) +#define HWIO_IPA_NLO_PP_DATA_LIMIT_CFG_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_NLO_PP_DATA_LIMIT_CFG_ADDR, \ + m, \ + v, \ + HWIO_IPA_NLO_PP_DATA_LIMIT_CFG_IN) +#define HWIO_IPA_NLO_PP_DATA_LIMIT_CFG_NLO_DATA_UPPER_SIZE_BMSK 0xffff0000 +#define HWIO_IPA_NLO_PP_DATA_LIMIT_CFG_NLO_DATA_UPPER_SIZE_SHFT 0x10 +#define HWIO_IPA_NLO_PP_DATA_LIMIT_CFG_NLO_DATA_LOWER_SIZE_BMSK 0xffff +#define HWIO_IPA_NLO_PP_DATA_LIMIT_CFG_NLO_DATA_LOWER_SIZE_SHFT 0x0 +#define HWIO_IPA_NLO_MIN_DSM_CFG_ADDR (IPA_CFG_REG_BASE + 0x00001690) +#define HWIO_IPA_NLO_MIN_DSM_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00001690) +#define HWIO_IPA_NLO_MIN_DSM_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00001690) +#define HWIO_IPA_NLO_MIN_DSM_CFG_RMSK 0xffffffff +#define HWIO_IPA_NLO_MIN_DSM_CFG_ATTR 0x3 +#define HWIO_IPA_NLO_MIN_DSM_CFG_IN in_dword_masked( \ + HWIO_IPA_NLO_MIN_DSM_CFG_ADDR, \ + HWIO_IPA_NLO_MIN_DSM_CFG_RMSK) +#define HWIO_IPA_NLO_MIN_DSM_CFG_INM(m) in_dword_masked( \ + HWIO_IPA_NLO_MIN_DSM_CFG_ADDR, \ + m) +#define HWIO_IPA_NLO_MIN_DSM_CFG_OUT(v) out_dword( \ + HWIO_IPA_NLO_MIN_DSM_CFG_ADDR, \ + v) +#define HWIO_IPA_NLO_MIN_DSM_CFG_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_NLO_MIN_DSM_CFG_ADDR, \ + m, \ + v, \ + HWIO_IPA_NLO_MIN_DSM_CFG_IN) +#define HWIO_IPA_NLO_MIN_DSM_CFG_NLO_DATA_MIN_DSM_LEN_BMSK 0xffff0000 +#define HWIO_IPA_NLO_MIN_DSM_CFG_NLO_DATA_MIN_DSM_LEN_SHFT 0x10 +#define HWIO_IPA_NLO_MIN_DSM_CFG_NLO_ACK_MIN_DSM_LEN_BMSK 0xffff +#define HWIO_IPA_NLO_MIN_DSM_CFG_NLO_ACK_MIN_DSM_LEN_SHFT 0x0 +#define HWIO_IPA_NLO_VP_AGGR_CFG_LSB_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00001700 + 0x8 * (n)) +#define HWIO_IPA_NLO_VP_AGGR_CFG_LSB_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00001700 + 0x8 * (n)) +#define HWIO_IPA_NLO_VP_AGGR_CFG_LSB_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00001700 + 0x8 * (n)) +#define HWIO_IPA_NLO_VP_AGGR_CFG_MSB_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00001704 + 0x8 * (n)) +#define HWIO_IPA_NLO_VP_AGGR_CFG_MSB_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00001704 + 0x8 * (n)) +#define HWIO_IPA_NLO_VP_AGGR_CFG_MSB_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00001704 + 0x8 * (n)) +#define HWIO_IPA_SNIFFER_QMB_SEL_ADDR (IPA_CFG_REG_BASE + 0x00001800) +#define HWIO_IPA_SNIFFER_QMB_SEL_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00001800) +#define HWIO_IPA_SNIFFER_QMB_SEL_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00001800) +#define HWIO_IPA_COAL_EVICT_LRU_ADDR (IPA_CFG_REG_BASE + 0x0000180c) +#define HWIO_IPA_COAL_EVICT_LRU_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000180c) +#define HWIO_IPA_COAL_EVICT_LRU_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000180c) +#define HWIO_IPA_COAL_QMAP_CFG_ADDR (IPA_CFG_REG_BASE + 0x00001810) +#define HWIO_IPA_COAL_QMAP_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00001810) +#define HWIO_IPA_COAL_QMAP_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00001810) +#define HWIO_IPA_NLO_VP_FLUSH_REQ_ADDR (IPA_CFG_REG_BASE + 0x00001814) +#define HWIO_IPA_NLO_VP_FLUSH_REQ_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00001814) +#define HWIO_IPA_NLO_VP_FLUSH_REQ_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00001814) +#define HWIO_IPA_NLO_VP_FLUSH_REQ_RMSK 0x80ff00ff +#define HWIO_IPA_NLO_VP_FLUSH_REQ_ATTR 0x3 +#define HWIO_IPA_NLO_VP_FLUSH_REQ_IN in_dword_masked( \ + HWIO_IPA_NLO_VP_FLUSH_REQ_ADDR, \ + HWIO_IPA_NLO_VP_FLUSH_REQ_RMSK) +#define HWIO_IPA_NLO_VP_FLUSH_REQ_INM(m) in_dword_masked( \ + HWIO_IPA_NLO_VP_FLUSH_REQ_ADDR, \ + m) +#define HWIO_IPA_NLO_VP_FLUSH_REQ_OUT(v) out_dword( \ + HWIO_IPA_NLO_VP_FLUSH_REQ_ADDR, \ + v) +#define HWIO_IPA_NLO_VP_FLUSH_REQ_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_NLO_VP_FLUSH_REQ_ADDR, \ + m, \ + v, \ + HWIO_IPA_NLO_VP_FLUSH_REQ_IN) +#define HWIO_IPA_NLO_VP_FLUSH_REQ_VP_FLUSH_REQ_BMSK 0x80000000 +#define HWIO_IPA_NLO_VP_FLUSH_REQ_VP_FLUSH_REQ_SHFT 0x1f +#define HWIO_IPA_NLO_VP_FLUSH_REQ_VP_FLUSH_VP_INDX_BMSK 0xff0000 +#define HWIO_IPA_NLO_VP_FLUSH_REQ_VP_FLUSH_VP_INDX_SHFT 0x10 +#define HWIO_IPA_NLO_VP_FLUSH_REQ_VP_FLUSH_PP_INDX_BMSK 0xff +#define HWIO_IPA_NLO_VP_FLUSH_REQ_VP_FLUSH_PP_INDX_SHFT 0x0 +#define HWIO_IPA_NLO_VP_FLUSH_COOKIE_ADDR (IPA_CFG_REG_BASE + 0x00001818) +#define HWIO_IPA_NLO_VP_FLUSH_COOKIE_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00001818) +#define HWIO_IPA_NLO_VP_FLUSH_COOKIE_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00001818) +#define HWIO_IPA_NLO_VP_FLUSH_COOKIE_RMSK 0xffffffff +#define HWIO_IPA_NLO_VP_FLUSH_COOKIE_ATTR 0x1 +#define HWIO_IPA_NLO_VP_FLUSH_COOKIE_IN in_dword_masked( \ + HWIO_IPA_NLO_VP_FLUSH_COOKIE_ADDR, \ + HWIO_IPA_NLO_VP_FLUSH_COOKIE_RMSK) +#define HWIO_IPA_NLO_VP_FLUSH_COOKIE_INM(m) in_dword_masked( \ + HWIO_IPA_NLO_VP_FLUSH_COOKIE_ADDR, \ + m) +#define HWIO_IPA_NLO_VP_FLUSH_COOKIE_VP_FLUSH_COOKIE_BMSK 0xffffffff +#define HWIO_IPA_NLO_VP_FLUSH_COOKIE_VP_FLUSH_COOKIE_SHFT 0x0 +#define HWIO_IPA_NLO_VP_FLUSH_ACK_ADDR (IPA_CFG_REG_BASE + 0x0000181c) +#define HWIO_IPA_NLO_VP_FLUSH_ACK_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000181c) +#define HWIO_IPA_NLO_VP_FLUSH_ACK_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000181c) +#define HWIO_IPA_NLO_VP_FLUSH_ACK_RMSK 0x1 +#define HWIO_IPA_NLO_VP_FLUSH_ACK_ATTR 0x1 +#define HWIO_IPA_NLO_VP_FLUSH_ACK_IN in_dword_masked( \ + HWIO_IPA_NLO_VP_FLUSH_ACK_ADDR, \ + HWIO_IPA_NLO_VP_FLUSH_ACK_RMSK) +#define HWIO_IPA_NLO_VP_FLUSH_ACK_INM(m) in_dword_masked( \ + HWIO_IPA_NLO_VP_FLUSH_ACK_ADDR, \ + m) +#define HWIO_IPA_NLO_VP_FLUSH_ACK_VP_FLUSH_ACK_BMSK 0x1 +#define HWIO_IPA_NLO_VP_FLUSH_ACK_VP_FLUSH_ACK_SHFT 0x0 +#define HWIO_IPA_NLO_VP_DSM_OPEN_ADDR (IPA_CFG_REG_BASE + 0x00001820) +#define HWIO_IPA_NLO_VP_DSM_OPEN_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00001820) +#define HWIO_IPA_NLO_VP_DSM_OPEN_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00001820) +#define HWIO_IPA_NLO_VP_DSM_OPEN_RMSK 0xffffffff +#define HWIO_IPA_NLO_VP_DSM_OPEN_ATTR 0x1 +#define HWIO_IPA_NLO_VP_DSM_OPEN_IN in_dword_masked( \ + HWIO_IPA_NLO_VP_DSM_OPEN_ADDR, \ + HWIO_IPA_NLO_VP_DSM_OPEN_RMSK) +#define HWIO_IPA_NLO_VP_DSM_OPEN_INM(m) in_dword_masked( \ + HWIO_IPA_NLO_VP_DSM_OPEN_ADDR, \ + m) +#define HWIO_IPA_NLO_VP_DSM_OPEN_VP_DSM_OPEN_BMSK 0xffffffff +#define HWIO_IPA_NLO_VP_DSM_OPEN_VP_DSM_OPEN_SHFT 0x0 +#define HWIO_IPA_NLO_VP_QBAP_OPEN_ADDR (IPA_CFG_REG_BASE + 0x00001824) +#define HWIO_IPA_NLO_VP_QBAP_OPEN_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00001824) +#define HWIO_IPA_NLO_VP_QBAP_OPEN_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00001824) +#define HWIO_IPA_NLO_VP_QBAP_OPEN_RMSK 0xffffffff +#define HWIO_IPA_NLO_VP_QBAP_OPEN_ATTR 0x1 +#define HWIO_IPA_NLO_VP_QBAP_OPEN_IN in_dword_masked( \ + HWIO_IPA_NLO_VP_QBAP_OPEN_ADDR, \ + HWIO_IPA_NLO_VP_QBAP_OPEN_RMSK) +#define HWIO_IPA_NLO_VP_QBAP_OPEN_INM(m) in_dword_masked( \ + HWIO_IPA_NLO_VP_QBAP_OPEN_ADDR, \ + m) +#define HWIO_IPA_NLO_VP_QBAP_OPEN_VP_QBAP_OPEN_BMSK 0xffffffff +#define HWIO_IPA_NLO_VP_QBAP_OPEN_VP_QBAP_OPEN_SHFT 0x0 +#define IPA_DEBUG_REG_BASE (IPA_0_IPA_WRAPPER_BASE + 0x00042000) +#define IPA_DEBUG_REG_BASE_PHYS (IPA_0_IPA_WRAPPER_BASE_PHYS + 0x00042000) +#define IPA_DEBUG_REG_BASE_OFFS 0x00042000 +#define HWIO_IPA_HPS_FTCH_ARB_DEBUG_STATUS_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000000) +#define HWIO_IPA_HPS_FTCH_ARB_DEBUG_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000000) +#define HWIO_IPA_HPS_FTCH_ARB_DEBUG_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000000) +#define HWIO_IPA_HPS_FTCH_ARB_DEBUG_BLOCK_STATUS_ADDR (IPA_DEBUG_REG_BASE \ + + 0x00000004) +#define HWIO_IPA_HPS_FTCH_ARB_DEBUG_BLOCK_STATUS_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000004) +#define HWIO_IPA_HPS_FTCH_ARB_DEBUG_BLOCK_STATUS_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000004) +#define HWIO_IPA_HPS_FTCH_ARB_DEBUG_CFG_MASK_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000008) +#define HWIO_IPA_HPS_FTCH_ARB_DEBUG_CFG_MASK_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000008) +#define HWIO_IPA_HPS_FTCH_ARB_DEBUG_CFG_MASK_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000008) +#define HWIO_IPA_HPS_FTCH_ARB_DEBUG_CFG_BLOCK_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000000c) +#define HWIO_IPA_HPS_FTCH_ARB_DEBUG_CFG_BLOCK_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x0000000c) +#define HWIO_IPA_HPS_FTCH_ARB_DEBUG_CFG_BLOCK_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x0000000c) +#define HWIO_IPA_HPS_FTCH_ARB_DEBUG_CMD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000010) +#define HWIO_IPA_HPS_FTCH_ARB_DEBUG_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000010) +#define HWIO_IPA_HPS_FTCH_ARB_DEBUG_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000010) +#define HWIO_IPA_DPS_FTCH_ARB_DEBUG_STATUS_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000014) +#define HWIO_IPA_DPS_FTCH_ARB_DEBUG_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000014) +#define HWIO_IPA_DPS_FTCH_ARB_DEBUG_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000014) +#define HWIO_IPA_DPS_FTCH_ARB_DEBUG_BLOCK_STATUS_ADDR (IPA_DEBUG_REG_BASE \ + + 0x00000018) +#define HWIO_IPA_DPS_FTCH_ARB_DEBUG_BLOCK_STATUS_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000018) +#define HWIO_IPA_DPS_FTCH_ARB_DEBUG_BLOCK_STATUS_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000018) +#define HWIO_IPA_DPS_FTCH_ARB_DEBUG_CFG_MASK_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000001c) +#define HWIO_IPA_DPS_FTCH_ARB_DEBUG_CFG_MASK_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x0000001c) +#define HWIO_IPA_DPS_FTCH_ARB_DEBUG_CFG_MASK_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x0000001c) +#define HWIO_IPA_DPS_FTCH_ARB_DEBUG_CFG_BLOCK_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000020) +#define HWIO_IPA_DPS_FTCH_ARB_DEBUG_CFG_BLOCK_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000020) +#define HWIO_IPA_DPS_FTCH_ARB_DEBUG_CFG_BLOCK_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000020) +#define HWIO_IPA_DPS_FTCH_ARB_DEBUG_CMD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000024) +#define HWIO_IPA_DPS_FTCH_ARB_DEBUG_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000024) +#define HWIO_IPA_DPS_FTCH_ARB_DEBUG_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000024) +#define HWIO_IPA_RSRC_MNGR_FUNC_ARB_DEBUG_STATUS_ADDR (IPA_DEBUG_REG_BASE \ + + 0x00000028) +#define HWIO_IPA_RSRC_MNGR_FUNC_ARB_DEBUG_STATUS_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000028) +#define HWIO_IPA_RSRC_MNGR_FUNC_ARB_DEBUG_STATUS_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000028) +#define HWIO_IPA_RSRC_MNGR_FUNC_ARB_DEBUG_BLOCK_STATUS_ADDR ( \ + IPA_DEBUG_REG_BASE + 0x0000002c) +#define HWIO_IPA_RSRC_MNGR_FUNC_ARB_DEBUG_BLOCK_STATUS_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x0000002c) +#define HWIO_IPA_RSRC_MNGR_FUNC_ARB_DEBUG_BLOCK_STATUS_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x0000002c) +#define HWIO_IPA_RSRC_MNGR_FUNC_ARB_DEBUG_CFG_MASK_ADDR ( \ + IPA_DEBUG_REG_BASE + 0x00000030) +#define HWIO_IPA_RSRC_MNGR_FUNC_ARB_DEBUG_CFG_MASK_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000030) +#define HWIO_IPA_RSRC_MNGR_FUNC_ARB_DEBUG_CFG_MASK_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000030) +#define HWIO_IPA_RSRC_MNGR_FUNC_ARB_DEBUG_CFG_BLOCK_ADDR ( \ + IPA_DEBUG_REG_BASE + 0x00000034) +#define HWIO_IPA_RSRC_MNGR_FUNC_ARB_DEBUG_CFG_BLOCK_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000034) +#define HWIO_IPA_RSRC_MNGR_FUNC_ARB_DEBUG_CFG_BLOCK_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000034) +#define HWIO_IPA_RSRC_MNGR_FUNC_ARB_DEBUG_CMD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000038) +#define HWIO_IPA_RSRC_MNGR_FUNC_ARB_DEBUG_CMD_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000038) +#define HWIO_IPA_RSRC_MNGR_FUNC_ARB_DEBUG_CMD_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000038) +#define HWIO_IPA_RSRC_MNGR_ALLOC_ARB_DEBUG_STATUS_ADDR (IPA_DEBUG_REG_BASE \ + + 0x0000003c) +#define HWIO_IPA_RSRC_MNGR_ALLOC_ARB_DEBUG_STATUS_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x0000003c) +#define HWIO_IPA_RSRC_MNGR_ALLOC_ARB_DEBUG_STATUS_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x0000003c) +#define HWIO_IPA_RSRC_MNGR_ALLOC_ARB_DEBUG_BLOCK_STATUS_ADDR ( \ + IPA_DEBUG_REG_BASE + 0x00000040) +#define HWIO_IPA_RSRC_MNGR_ALLOC_ARB_DEBUG_BLOCK_STATUS_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000040) +#define HWIO_IPA_RSRC_MNGR_ALLOC_ARB_DEBUG_BLOCK_STATUS_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000040) +#define HWIO_IPA_RSRC_MNGR_ALLOC_ARB_DEBUG_CFG_MASK_ADDR ( \ + IPA_DEBUG_REG_BASE + 0x00000044) +#define HWIO_IPA_RSRC_MNGR_ALLOC_ARB_DEBUG_CFG_MASK_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000044) +#define HWIO_IPA_RSRC_MNGR_ALLOC_ARB_DEBUG_CFG_MASK_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000044) +#define HWIO_IPA_RSRC_MNGR_ALLOC_ARB_DEBUG_CFG_BLOCK_ADDR ( \ + IPA_DEBUG_REG_BASE + 0x00000048) +#define HWIO_IPA_RSRC_MNGR_ALLOC_ARB_DEBUG_CFG_BLOCK_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000048) +#define HWIO_IPA_RSRC_MNGR_ALLOC_ARB_DEBUG_CFG_BLOCK_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000048) +#define HWIO_IPA_RSRC_MNGR_ALLOC_ARB_DEBUG_CMD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000004c) +#define HWIO_IPA_RSRC_MNGR_ALLOC_ARB_DEBUG_CMD_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x0000004c) +#define HWIO_IPA_RSRC_MNGR_ALLOC_ARB_DEBUG_CMD_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x0000004c) +#define HWIO_IPA_RSRC_MNGR_SRCH_ARB_DEBUG_STATUS_ADDR (IPA_DEBUG_REG_BASE \ + + 0x00000050) +#define HWIO_IPA_RSRC_MNGR_SRCH_ARB_DEBUG_STATUS_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000050) +#define HWIO_IPA_RSRC_MNGR_SRCH_ARB_DEBUG_STATUS_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000050) +#define HWIO_IPA_RSRC_MNGR_SRCH_ARB_DEBUG_BLOCK_STATUS_ADDR ( \ + IPA_DEBUG_REG_BASE + 0x00000054) +#define HWIO_IPA_RSRC_MNGR_SRCH_ARB_DEBUG_BLOCK_STATUS_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000054) +#define HWIO_IPA_RSRC_MNGR_SRCH_ARB_DEBUG_BLOCK_STATUS_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000054) +#define HWIO_IPA_RSRC_MNGR_SRCH_ARB_DEBUG_CFG_MASK_ADDR ( \ + IPA_DEBUG_REG_BASE + 0x00000058) +#define HWIO_IPA_RSRC_MNGR_SRCH_ARB_DEBUG_CFG_MASK_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000058) +#define HWIO_IPA_RSRC_MNGR_SRCH_ARB_DEBUG_CFG_MASK_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000058) +#define HWIO_IPA_RSRC_MNGR_SRCH_ARB_DEBUG_CFG_BLOCK_ADDR ( \ + IPA_DEBUG_REG_BASE + 0x0000005c) +#define HWIO_IPA_RSRC_MNGR_SRCH_ARB_DEBUG_CFG_BLOCK_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x0000005c) +#define HWIO_IPA_RSRC_MNGR_SRCH_ARB_DEBUG_CFG_BLOCK_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x0000005c) +#define HWIO_IPA_RSRC_MNGR_SRCH_ARB_DEBUG_CMD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000060) +#define HWIO_IPA_RSRC_MNGR_SRCH_ARB_DEBUG_CMD_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000060) +#define HWIO_IPA_RSRC_MNGR_SRCH_ARB_DEBUG_CMD_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000060) +#define HWIO_IPA_RSRC_MNGR_REL_ARB_DEBUG_STATUS_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000064) +#define HWIO_IPA_RSRC_MNGR_REL_ARB_DEBUG_STATUS_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000064) +#define HWIO_IPA_RSRC_MNGR_REL_ARB_DEBUG_STATUS_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000064) +#define HWIO_IPA_RSRC_MNGR_REL_ARB_DEBUG_BLOCK_STATUS_ADDR ( \ + IPA_DEBUG_REG_BASE + 0x00000068) +#define HWIO_IPA_RSRC_MNGR_REL_ARB_DEBUG_BLOCK_STATUS_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000068) +#define HWIO_IPA_RSRC_MNGR_REL_ARB_DEBUG_BLOCK_STATUS_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000068) +#define HWIO_IPA_RSRC_MNGR_REL_ARB_DEBUG_CFG_MASK_ADDR (IPA_DEBUG_REG_BASE \ + + 0x0000006c) +#define HWIO_IPA_RSRC_MNGR_REL_ARB_DEBUG_CFG_MASK_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x0000006c) +#define HWIO_IPA_RSRC_MNGR_REL_ARB_DEBUG_CFG_MASK_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x0000006c) +#define HWIO_IPA_RSRC_MNGR_REL_ARB_DEBUG_CFG_BLOCK_ADDR ( \ + IPA_DEBUG_REG_BASE + 0x00000070) +#define HWIO_IPA_RSRC_MNGR_REL_ARB_DEBUG_CFG_BLOCK_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000070) +#define HWIO_IPA_RSRC_MNGR_REL_ARB_DEBUG_CFG_BLOCK_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000070) +#define HWIO_IPA_RSRC_MNGR_REL_ARB_DEBUG_CMD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000074) +#define HWIO_IPA_RSRC_MNGR_REL_ARB_DEBUG_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000074) +#define HWIO_IPA_RSRC_MNGR_REL_ARB_DEBUG_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000074) +#define HWIO_IPA_TX_ARB_DEBUG_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x00000078) +#define HWIO_IPA_TX_ARB_DEBUG_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000078) +#define HWIO_IPA_TX_ARB_DEBUG_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000078) +#define HWIO_IPA_TX_ARB_DEBUG_BLOCK_STATUS_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000007c) +#define HWIO_IPA_TX_ARB_DEBUG_BLOCK_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000007c) +#define HWIO_IPA_TX_ARB_DEBUG_BLOCK_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000007c) +#define HWIO_IPA_TX_ARB_DEBUG_CFG_MASK_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000080) +#define HWIO_IPA_TX_ARB_DEBUG_CFG_MASK_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000080) +#define HWIO_IPA_TX_ARB_DEBUG_CFG_MASK_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000080) +#define HWIO_IPA_TX_ARB_DEBUG_CFG_BLOCK_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000084) +#define HWIO_IPA_TX_ARB_DEBUG_CFG_BLOCK_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000084) +#define HWIO_IPA_TX_ARB_DEBUG_CFG_BLOCK_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000084) +#define HWIO_IPA_TX_ARB_DEBUG_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x00000088) +#define HWIO_IPA_TX_ARB_DEBUG_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000088) +#define HWIO_IPA_TX_ARB_DEBUG_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000088) +#define HWIO_IPA_HPS_SEQ_ARB_DEBUG_STATUS_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000008c) +#define HWIO_IPA_HPS_SEQ_ARB_DEBUG_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000008c) +#define HWIO_IPA_HPS_SEQ_ARB_DEBUG_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000008c) +#define HWIO_IPA_HPS_SEQ_ARB_DEBUG_BLOCK_STATUS_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000090) +#define HWIO_IPA_HPS_SEQ_ARB_DEBUG_BLOCK_STATUS_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000090) +#define HWIO_IPA_HPS_SEQ_ARB_DEBUG_BLOCK_STATUS_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000090) +#define HWIO_IPA_HPS_SEQ_ARB_DEBUG_CFG_MASK_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000094) +#define HWIO_IPA_HPS_SEQ_ARB_DEBUG_CFG_MASK_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000094) +#define HWIO_IPA_HPS_SEQ_ARB_DEBUG_CFG_MASK_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000094) +#define HWIO_IPA_HPS_SEQ_ARB_DEBUG_CFG_BLOCK_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000098) +#define HWIO_IPA_HPS_SEQ_ARB_DEBUG_CFG_BLOCK_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000098) +#define HWIO_IPA_HPS_SEQ_ARB_DEBUG_CFG_BLOCK_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000098) +#define HWIO_IPA_HPS_SEQ_ARB_DEBUG_CMD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000009c) +#define HWIO_IPA_HPS_SEQ_ARB_DEBUG_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000009c) +#define HWIO_IPA_HPS_SEQ_ARB_DEBUG_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000009c) +#define HWIO_IPA_DPS_SEQ_ARB_DEBUG_STATUS_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000100) +#define HWIO_IPA_DPS_SEQ_ARB_DEBUG_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000100) +#define HWIO_IPA_DPS_SEQ_ARB_DEBUG_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000100) +#define HWIO_IPA_DPS_SEQ_ARB_DEBUG_BLOCK_STATUS_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000104) +#define HWIO_IPA_DPS_SEQ_ARB_DEBUG_BLOCK_STATUS_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000104) +#define HWIO_IPA_DPS_SEQ_ARB_DEBUG_BLOCK_STATUS_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000104) +#define HWIO_IPA_DPS_SEQ_ARB_DEBUG_CFG_MASK_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000108) +#define HWIO_IPA_DPS_SEQ_ARB_DEBUG_CFG_MASK_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000108) +#define HWIO_IPA_DPS_SEQ_ARB_DEBUG_CFG_MASK_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000108) +#define HWIO_IPA_DPS_SEQ_ARB_DEBUG_CFG_BLOCK_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000010c) +#define HWIO_IPA_DPS_SEQ_ARB_DEBUG_CFG_BLOCK_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x0000010c) +#define HWIO_IPA_DPS_SEQ_ARB_DEBUG_CFG_BLOCK_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x0000010c) +#define HWIO_IPA_DPS_SEQ_ARB_DEBUG_CMD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000110) +#define HWIO_IPA_DPS_SEQ_ARB_DEBUG_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000110) +#define HWIO_IPA_DPS_SEQ_ARB_DEBUG_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000110) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000114) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000114) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000114) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_SRCH_CFG_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000118) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_SRCH_CFG_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000118) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_SRCH_CFG_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000118) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_REL_CFG_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000011c) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_REL_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x0000011c) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_REL_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x0000011c) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_CMD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000120) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000120) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000120) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_STATUS_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000124) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000124) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000124) +#define HWIO_IPA_RSRC_MNGR_DB_CFG_ADDR (IPA_DEBUG_REG_BASE + 0x00000128) +#define HWIO_IPA_RSRC_MNGR_DB_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000128) +#define HWIO_IPA_RSRC_MNGR_DB_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000128) +#define HWIO_IPA_RSRC_MNGR_DB_CFG_RMSK 0x3f77 +#define HWIO_IPA_RSRC_MNGR_DB_CFG_ATTR 0x3 +#define HWIO_IPA_RSRC_MNGR_DB_CFG_IN in_dword_masked( \ + HWIO_IPA_RSRC_MNGR_DB_CFG_ADDR, \ + HWIO_IPA_RSRC_MNGR_DB_CFG_RMSK) +#define HWIO_IPA_RSRC_MNGR_DB_CFG_INM(m) in_dword_masked( \ + HWIO_IPA_RSRC_MNGR_DB_CFG_ADDR, \ + m) +#define HWIO_IPA_RSRC_MNGR_DB_CFG_OUT(v) out_dword( \ + HWIO_IPA_RSRC_MNGR_DB_CFG_ADDR, \ + v) +#define HWIO_IPA_RSRC_MNGR_DB_CFG_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_RSRC_MNGR_DB_CFG_ADDR, \ + m, \ + v, \ + HWIO_IPA_RSRC_MNGR_DB_CFG_IN) +#define HWIO_IPA_RSRC_MNGR_DB_CFG_RSRC_ID_SEL_BMSK 0x3f00 +#define HWIO_IPA_RSRC_MNGR_DB_CFG_RSRC_ID_SEL_SHFT 0x8 +#define HWIO_IPA_RSRC_MNGR_DB_CFG_RSRC_TYPE_SEL_BMSK 0x70 +#define HWIO_IPA_RSRC_MNGR_DB_CFG_RSRC_TYPE_SEL_SHFT 0x4 +#define HWIO_IPA_RSRC_MNGR_DB_CFG_RSRC_GRP_SEL_BMSK 0x7 +#define HWIO_IPA_RSRC_MNGR_DB_CFG_RSRC_GRP_SEL_SHFT 0x0 +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000012c) +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000012c) +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000012c) +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_RMSK 0x3f3 +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_ATTR 0x1 +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_IN in_dword_masked( \ + HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_ADDR, \ + HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_RMSK) +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_INM(m) in_dword_masked( \ + HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_ADDR, \ + m) +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_RSRC_NEXT_INDEX_BMSK 0x3f0 +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_RSRC_NEXT_INDEX_SHFT 0x4 +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_RSRC_NEXT_VALID_BMSK 0x2 +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_RSRC_NEXT_VALID_SHFT 0x1 +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_RSRC_OCCUPIED_BMSK 0x1 +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_RSRC_OCCUPIED_SHFT 0x0 +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000130) +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000130) +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000130) +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_RMSK 0x7f7f3f3 +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_ATTR 0x1 +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_IN in_dword_masked( \ + HWIO_IPA_RSRC_MNGR_DB_LIST_READ_ADDR, \ + HWIO_IPA_RSRC_MNGR_DB_LIST_READ_RMSK) +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_INM(m) in_dword_masked( \ + HWIO_IPA_RSRC_MNGR_DB_LIST_READ_ADDR, \ + m) +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_RSRC_LIST_ENTRY_CNT_BMSK 0x7f00000 +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_RSRC_LIST_ENTRY_CNT_SHFT 0x14 +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_RSRC_LIST_HEAD_CNT_BMSK 0x7f000 +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_RSRC_LIST_HEAD_CNT_SHFT 0xc +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_RSRC_LIST_HEAD_RSRC_BMSK 0x3f0 +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_RSRC_LIST_HEAD_RSRC_SHFT 0x4 +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_RSRC_LIST_HOLD_BMSK 0x2 +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_RSRC_LIST_HOLD_SHFT 0x1 +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_RSRC_LIST_VALID_BMSK 0x1 +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_RSRC_LIST_VALID_SHFT 0x0 +#define HWIO_IPA_RSRC_MNGR_CONTEXTS_ADDR (IPA_DEBUG_REG_BASE + 0x00000134) +#define HWIO_IPA_RSRC_MNGR_CONTEXTS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000134) +#define HWIO_IPA_RSRC_MNGR_CONTEXTS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000134) +#define HWIO_IPA_BRESP_DB_CFG_ADDR (IPA_DEBUG_REG_BASE + 0x00000138) +#define HWIO_IPA_BRESP_DB_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000138) +#define HWIO_IPA_BRESP_DB_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000138) +#define HWIO_IPA_BRESP_DB_DATA_ADDR (IPA_DEBUG_REG_BASE + 0x0000013c) +#define HWIO_IPA_BRESP_DB_DATA_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000013c) +#define HWIO_IPA_BRESP_DB_DATA_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000013c) +#define HWIO_IPA_DEBUG_DATA_ADDR (IPA_DEBUG_REG_BASE + 0x00000204) +#define HWIO_IPA_DEBUG_DATA_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000204) +#define HWIO_IPA_DEBUG_DATA_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000204) +#define HWIO_IPA_DEBUG_DATA_RMSK 0xffffffff +#define HWIO_IPA_DEBUG_DATA_ATTR 0x1 +#define HWIO_IPA_DEBUG_DATA_IN in_dword_masked(HWIO_IPA_DEBUG_DATA_ADDR, \ + HWIO_IPA_DEBUG_DATA_RMSK) +#define HWIO_IPA_DEBUG_DATA_INM(m) in_dword_masked( \ + HWIO_IPA_DEBUG_DATA_ADDR, \ + m) +#define HWIO_IPA_DEBUG_DATA_DEBUG_DATA_BMSK 0xffffffff +#define HWIO_IPA_DEBUG_DATA_DEBUG_DATA_SHFT 0x0 +#define HWIO_IPA_TESTBUS_SEL_ADDR (IPA_DEBUG_REG_BASE + 0x00000208) +#define HWIO_IPA_TESTBUS_SEL_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000208) +#define HWIO_IPA_TESTBUS_SEL_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000208) +#define HWIO_IPA_TESTBUS_SEL_RMSK 0x1fffff1 +#define HWIO_IPA_TESTBUS_SEL_ATTR 0x3 +#define HWIO_IPA_TESTBUS_SEL_IN in_dword_masked(HWIO_IPA_TESTBUS_SEL_ADDR, \ + HWIO_IPA_TESTBUS_SEL_RMSK) +#define HWIO_IPA_TESTBUS_SEL_INM(m) in_dword_masked( \ + HWIO_IPA_TESTBUS_SEL_ADDR, \ + m) +#define HWIO_IPA_TESTBUS_SEL_OUT(v) out_dword(HWIO_IPA_TESTBUS_SEL_ADDR, v) +#define HWIO_IPA_TESTBUS_SEL_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_TESTBUS_SEL_ADDR, \ + m, \ + v, \ + HWIO_IPA_TESTBUS_SEL_IN) +#define HWIO_IPA_TESTBUS_SEL_PIPE_SELECT_BMSK 0x1f00000 +#define HWIO_IPA_TESTBUS_SEL_PIPE_SELECT_SHFT 0x14 +#define HWIO_IPA_TESTBUS_SEL_INTERNAL_BLOCK_SELECT_BMSK 0xff000 +#define HWIO_IPA_TESTBUS_SEL_INTERNAL_BLOCK_SELECT_SHFT 0xc +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_BMSK 0xff0 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_SHFT 0x4 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_IPA_RX_FVAL 0x0 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_IPA_TX0_FVAL 0x1 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_HPS_FRAG_FVAL 0x2 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_HPS_UCP_FVAL 0x3 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_HPS_ENQUEUER_FVAL 0x4 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_HPS_ROUTER_FVAL 0x5 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_HPS_PKT_PARSER_FVAL 0x6 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_HPS_FILTER_NAT_FVAL 0x7 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_HPS_HDRI_RSRCREL_FVAL \ + 0x8 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_IPA_AHB2AHB_FVAL 0x9 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_IPA_MAXI2AXI_FVAL 0xa +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_DPS_DCMP_FVAL 0xb +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_DPS_DISPATCHER_FVAL 0xc +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_DPS_D_DCPH_FVAL 0xd +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_GSI_TEST_BUS_FVAL 0xe +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_DEADBEAF_FVAL 0xf +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_IPA_MISC_FVAL 0x10 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_IPA_STTS_SNIFFER_FVAL \ + 0x11 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_IPA_QMB_0_FVAL 0x12 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_IPA_QMB_1_FVAL 0x13 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_IPA_UC_ACKQ_FVAL 0x14 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_IPA_RX_ACKQ_FVAL 0x15 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_IPA_TX1_FVAL 0x16 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_HPS_H_DCPH_FVAL 0x17 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_RX_HPS_CMDQ_FVAL 0x18 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_HPS_DPS_CMDQ_FVAL 0x19 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_DPS_TX_CMDQ_FVAL 0x1a +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_IPA_CMDQ_L_FVAL 0x1b +#define \ + HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_IPA_RX_LEGACY_CMDQ_INT_FVAL \ + 0x1c +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_IPA_CTX_HANDLER_FVAL \ + 0x1d +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_IPA_GSI_FVAL 0x1e +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_ACK_MNGR_CMDQ_FVAL 0x1f +#define \ + HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_ENDP_INIT_CTRL_SUSPEND_FVAL \ + 0x20 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_ACL_WRAPPER_FVAL 0x22 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_IPA_TX_WRAPPER_FVAL \ + 0x23 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_AHB2AHB_BRIDGE_FVAL \ + 0x24 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_RSRC_TYPE_FVAL 0x31 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_RSRC_FVAL 0x32 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_ACKMNGR_FVAL 0x33 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_HPS_SEQ_FVAL 0x34 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_DPS_SEQ_FVAL 0x35 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_HPS_FTCH_FVAL 0x36 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_DPS_FTCH_FVAL 0x37 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_HPS_D_DCPH_2_FVAL 0x38 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_NTF_TX_CMDQ_FVAL 0x39 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_PROD_ACK_MNGR_CMDQ_FVAL \ + 0x3a +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_PROD_ACKMNGR_FVAL 0x3b +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_IPA_GSI_AHB2AHB_FVAL \ + 0x3c +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_IPA_MAXI2AXI_PCIE_FVAL \ + 0x3d +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_IPA_QSB2AXI_FVAL 0x3e +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_IPA_UC_FVAL 0x3f +#define HWIO_IPA_TESTBUS_SEL_TESTBUS_EN_BMSK 0x1 +#define HWIO_IPA_TESTBUS_SEL_TESTBUS_EN_SHFT 0x0 +#define HWIO_IPA_STEP_MODE_BREAKPOINTS_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000020c) +#define HWIO_IPA_STEP_MODE_BREAKPOINTS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000020c) +#define HWIO_IPA_STEP_MODE_BREAKPOINTS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000020c) +#define HWIO_IPA_STEP_MODE_BREAKPOINTS_RMSK 0xffffffff +#define HWIO_IPA_STEP_MODE_BREAKPOINTS_ATTR 0x3 +#define HWIO_IPA_STEP_MODE_BREAKPOINTS_IN in_dword_masked( \ + HWIO_IPA_STEP_MODE_BREAKPOINTS_ADDR, \ + HWIO_IPA_STEP_MODE_BREAKPOINTS_RMSK) +#define HWIO_IPA_STEP_MODE_BREAKPOINTS_INM(m) in_dword_masked( \ + HWIO_IPA_STEP_MODE_BREAKPOINTS_ADDR, \ + m) +#define HWIO_IPA_STEP_MODE_BREAKPOINTS_OUT(v) out_dword( \ + HWIO_IPA_STEP_MODE_BREAKPOINTS_ADDR, \ + v) +#define HWIO_IPA_STEP_MODE_BREAKPOINTS_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_STEP_MODE_BREAKPOINTS_ADDR, \ + m, \ + v, \ + HWIO_IPA_STEP_MODE_BREAKPOINTS_IN) +#define HWIO_IPA_STEP_MODE_BREAKPOINTS_HW_EN_BMSK 0xffffffff +#define HWIO_IPA_STEP_MODE_BREAKPOINTS_HW_EN_SHFT 0x0 +#define HWIO_IPA_STEP_MODE_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x00000210) +#define HWIO_IPA_STEP_MODE_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000210) +#define HWIO_IPA_STEP_MODE_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000210) +#define HWIO_IPA_STEP_MODE_STATUS_RMSK 0xffffffff +#define HWIO_IPA_STEP_MODE_STATUS_ATTR 0x1 +#define HWIO_IPA_STEP_MODE_STATUS_IN in_dword_masked( \ + HWIO_IPA_STEP_MODE_STATUS_ADDR, \ + HWIO_IPA_STEP_MODE_STATUS_RMSK) +#define HWIO_IPA_STEP_MODE_STATUS_INM(m) in_dword_masked( \ + HWIO_IPA_STEP_MODE_STATUS_ADDR, \ + m) +#define HWIO_IPA_STEP_MODE_STATUS_HW_EN_BMSK 0xffffffff +#define HWIO_IPA_STEP_MODE_STATUS_HW_EN_SHFT 0x0 +#define HWIO_IPA_STEP_MODE_GO_ADDR (IPA_DEBUG_REG_BASE + 0x00000214) +#define HWIO_IPA_STEP_MODE_GO_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000214) +#define HWIO_IPA_STEP_MODE_GO_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000214) +#define HWIO_IPA_HW_EVENTS_CFG_ADDR (IPA_DEBUG_REG_BASE + 0x00000218) +#define HWIO_IPA_HW_EVENTS_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000218) +#define HWIO_IPA_HW_EVENTS_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000218) +#define HWIO_IPA_LOG_ADDR (IPA_DEBUG_REG_BASE + 0x0000021c) +#define HWIO_IPA_LOG_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000021c) +#define HWIO_IPA_LOG_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000021c) +#define HWIO_IPA_LOG_RMSK 0x3ff1f2 +#define HWIO_IPA_LOG_ATTR 0x3 +#define HWIO_IPA_LOG_IN in_dword_masked(HWIO_IPA_LOG_ADDR, \ + HWIO_IPA_LOG_RMSK) +#define HWIO_IPA_LOG_INM(m) in_dword_masked(HWIO_IPA_LOG_ADDR, m) +#define HWIO_IPA_LOG_OUT(v) out_dword(HWIO_IPA_LOG_ADDR, v) +#define HWIO_IPA_LOG_OUTM(m, v) out_dword_masked_ns(HWIO_IPA_LOG_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_IN) +#define HWIO_IPA_LOG_LOG_DPL_L2_REMOVE_EN_BMSK 0x200000 +#define HWIO_IPA_LOG_LOG_DPL_L2_REMOVE_EN_SHFT 0x15 +#define HWIO_IPA_LOG_LOG_REDUCTION_EN_BMSK 0x100000 +#define HWIO_IPA_LOG_LOG_REDUCTION_EN_SHFT 0x14 +#define HWIO_IPA_LOG_LOG_LENGTH_BMSK 0xff000 +#define HWIO_IPA_LOG_LOG_LENGTH_SHFT 0xc +#define HWIO_IPA_LOG_LOG_PIPE_BMSK 0x1f0 +#define HWIO_IPA_LOG_LOG_PIPE_SHFT 0x4 +#define HWIO_IPA_LOG_LOG_EN_BMSK 0x2 +#define HWIO_IPA_LOG_LOG_EN_SHFT 0x1 +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_ADDR (IPA_DEBUG_REG_BASE + 0x00000224) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000224) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000224) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_CMD_ADDR_ADDR, \ + HWIO_IPA_LOG_BUF_HW_CMD_ADDR_RMSK) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_CMD_ADDR_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_HW_CMD_ADDR_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_HW_CMD_ADDR_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_HW_CMD_ADDR_IN) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_START_ADDR_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_START_ADDR_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000228) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000228) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000228) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_ADDR, \ + HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_RMSK) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_IN) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_START_ADDR_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_START_ADDR_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000022c) +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000022c) +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000022c) +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_ATTR 0x1 +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_ADDR, \ + HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_RMSK) +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_WRITR_ADDR_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_WRITR_ADDR_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_MSB_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000230) +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_MSB_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000230) +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_MSB_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000230) +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_MSB_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_MSB_ATTR 0x1 +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_MSB_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_MSB_ADDR, \ + HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_MSB_RMSK) +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_MSB_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_MSB_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_MSB_WRITR_ADDR_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_MSB_WRITR_ADDR_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_ADDR (IPA_DEBUG_REG_BASE + 0x00000234) +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000234) +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000234) +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_RMSK 0x3ffff +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_CMD_CFG_ADDR, \ + HWIO_IPA_LOG_BUF_HW_CMD_CFG_RMSK) +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_CMD_CFG_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_HW_CMD_CFG_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_HW_CMD_CFG_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_HW_CMD_CFG_IN) +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_SKIP_DDR_DMA_BMSK 0x20000 +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_SKIP_DDR_DMA_SHFT 0x11 +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_ENABLE_BMSK 0x10000 +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_ENABLE_SHFT 0x10 +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_SIZE_BMSK 0xffff +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_SIZE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000238) +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000238) +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000238) +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_RMSK 0xbfff3fff +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_ATTR 0x1 +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_ADDR, \ + HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_RMSK) +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_SKIP_DDR_WRAP_HAPPENED_BMSK \ + 0x80000000 +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_SKIP_DDR_WRAP_HAPPENED_SHFT 0x1f +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_WRITE_PTR_BMSK 0x3fff0000 +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_WRITE_PTR_SHFT 0x10 +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_READ_PTR_BMSK 0x3fff +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_READ_PTR_SHFT 0x0 +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_LSB_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000023c) +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_LSB_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x0000023c) +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_LSB_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x0000023c) +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_MSB_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000240) +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_MSB_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000240) +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_MSB_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000240) +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_RESULT_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000244) +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_RESULT_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000244) +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_RESULT_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000244) +#define HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000248) +#define HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000248) +#define HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000248) +#define HWIO_IPA_STEP_MODE_HSEQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000024c) +#define HWIO_IPA_STEP_MODE_HSEQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000024c) +#define HWIO_IPA_STEP_MODE_HSEQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000024c) +#define HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000250) +#define HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000250) +#define HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000250) +#define HWIO_IPA_STEP_MODE_DSEQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000254) +#define HWIO_IPA_STEP_MODE_DSEQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000254) +#define HWIO_IPA_STEP_MODE_DSEQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000254) +#define HWIO_IPA_RX_ACKQ_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x00000258) +#define HWIO_IPA_RX_ACKQ_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000258) +#define HWIO_IPA_RX_ACKQ_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000258) +#define HWIO_IPA_RX_ACKQ_CFG_ADDR (IPA_DEBUG_REG_BASE + 0x0000025c) +#define HWIO_IPA_RX_ACKQ_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000025c) +#define HWIO_IPA_RX_ACKQ_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000025c) +#define HWIO_IPA_RX_ACKQ_DATA_WR_0_ADDR (IPA_DEBUG_REG_BASE + 0x00000260) +#define HWIO_IPA_RX_ACKQ_DATA_WR_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000260) +#define HWIO_IPA_RX_ACKQ_DATA_WR_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000260) +#define HWIO_IPA_RX_ACKQ_DATA_RD_0_ADDR (IPA_DEBUG_REG_BASE + 0x00000264) +#define HWIO_IPA_RX_ACKQ_DATA_RD_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000264) +#define HWIO_IPA_RX_ACKQ_DATA_RD_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000264) +#define HWIO_IPA_RX_ACKQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x00000268) +#define HWIO_IPA_RX_ACKQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000268) +#define HWIO_IPA_RX_ACKQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000268) +#define HWIO_IPA_UC_ACKQ_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x0000026c) +#define HWIO_IPA_UC_ACKQ_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000026c) +#define HWIO_IPA_UC_ACKQ_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000026c) +#define HWIO_IPA_UC_ACKQ_CFG_ADDR (IPA_DEBUG_REG_BASE + 0x00000270) +#define HWIO_IPA_UC_ACKQ_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000270) +#define HWIO_IPA_UC_ACKQ_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000270) +#define HWIO_IPA_UC_ACKQ_DATA_WR_0_ADDR (IPA_DEBUG_REG_BASE + 0x00000274) +#define HWIO_IPA_UC_ACKQ_DATA_WR_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000274) +#define HWIO_IPA_UC_ACKQ_DATA_WR_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000274) +#define HWIO_IPA_UC_ACKQ_DATA_RD_0_ADDR (IPA_DEBUG_REG_BASE + 0x00000278) +#define HWIO_IPA_UC_ACKQ_DATA_RD_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000278) +#define HWIO_IPA_UC_ACKQ_DATA_RD_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000278) +#define HWIO_IPA_UC_ACKQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x0000027c) +#define HWIO_IPA_UC_ACKQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000027c) +#define HWIO_IPA_UC_ACKQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000027c) +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_ADDR(n) (IPA_DEBUG_REG_BASE + \ + 0x00000280 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000280 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000280 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_RMSK 0x7f +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_MAXn 3 +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_ATTR 0x2 +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_OUTI(n, val) out_dword( \ + HWIO_IPA_RX_SPLT_CMDQ_CMD_n_ADDR(n), \ + val) +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_RELEASE_RD_PKT_ENHANCED_BMSK 0x40 +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_RELEASE_RD_PKT_ENHANCED_SHFT 0x6 +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_RELEASE_WR_PKT_BMSK 0x20 +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_RELEASE_WR_PKT_SHFT 0x5 +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_RELEASE_RD_PKT_BMSK 0x10 +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_RELEASE_RD_PKT_SHFT 0x4 +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_RELEASE_WR_CMD_BMSK 0x8 +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_RELEASE_WR_CMD_SHFT 0x3 +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_RELEASE_RD_CMD_BMSK 0x4 +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_RELEASE_RD_CMD_SHFT 0x2 +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_POP_CMD_BMSK 0x2 +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_POP_CMD_SHFT 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_WRITE_CMD_BMSK 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_WRITE_CMD_SHFT 0x0 +#define HWIO_IPA_RX_SPLT_CMDQ_CFG_n_ADDR(n) (IPA_DEBUG_REG_BASE + \ + 0x00000284 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_CFG_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000284 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_CFG_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000284 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_CFG_n_RMSK 0x3 +#define HWIO_IPA_RX_SPLT_CMDQ_CFG_n_MAXn 3 +#define HWIO_IPA_RX_SPLT_CMDQ_CFG_n_ATTR 0x3 +#define HWIO_IPA_RX_SPLT_CMDQ_CFG_n_INI(n) in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_CFG_n_ADDR(n), \ + HWIO_IPA_RX_SPLT_CMDQ_CFG_n_RMSK) +#define HWIO_IPA_RX_SPLT_CMDQ_CFG_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_CFG_n_ADDR(n), \ + mask) +#define HWIO_IPA_RX_SPLT_CMDQ_CFG_n_OUTI(n, val) out_dword( \ + HWIO_IPA_RX_SPLT_CMDQ_CFG_n_ADDR(n), \ + val) +#define HWIO_IPA_RX_SPLT_CMDQ_CFG_n_OUTMI(n, mask, \ + val) out_dword_masked_ns( \ + HWIO_IPA_RX_SPLT_CMDQ_CFG_n_ADDR( \ + n), \ + mask, \ + val, \ + HWIO_IPA_RX_SPLT_CMDQ_CFG_n_INI(n)) +#define HWIO_IPA_RX_SPLT_CMDQ_CFG_n_BLOCK_WR_BMSK 0x2 +#define HWIO_IPA_RX_SPLT_CMDQ_CFG_n_BLOCK_WR_SHFT 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_CFG_n_BLOCK_RD_BMSK 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_CFG_n_BLOCK_RD_SHFT 0x0 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_ADDR(n) (IPA_DEBUG_REG_BASE + \ + 0x00000288 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000288 + 0x2C * \ + (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000288 + 0x2C * \ + (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_RMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_MAXn 3 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_ATTR 0x3 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_INI(n) in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_ADDR(n), \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_RMSK) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_ADDR(n), \ + mask) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_OUTI(n, val) out_dword( \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_ADDR(n), \ + val) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_OUTMI(n, mask, \ + val) out_dword_masked_ns( \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_ADDR( \ + n), \ + mask, \ + val, \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_INI(n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_CMDQ_SRC_LEN_F_BMSK 0xffff0000 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_CMDQ_SRC_LEN_F_SHFT 0x10 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_CMDQ_PACKET_LEN_F_BMSK 0xffff +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_CMDQ_PACKET_LEN_F_SHFT 0x0 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_ADDR(n) (IPA_DEBUG_REG_BASE + \ + 0x0000028c + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS \ + + 0x0000028c + 0x2C * \ + (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS \ + + 0x0000028c + 0x2C * \ + (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_RMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_MAXn 3 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_ATTR 0x3 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_INI(n) in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_ADDR(n), \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_RMSK) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_ADDR(n), \ + mask) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_OUTI(n, val) out_dword( \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_ADDR(n), \ + val) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_OUTMI(n, mask, \ + val) out_dword_masked_ns( \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_ADDR( \ + n), \ + mask, \ + val, \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_INI(n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_CMDQ_METADATA_F_BMSK 0xff000000 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_CMDQ_METADATA_F_SHFT 0x18 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_CMDQ_OPCODE_F_BMSK 0xff0000 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_CMDQ_OPCODE_F_SHFT 0x10 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_CMDQ_FLAGS_F_BMSK 0xfc00 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_CMDQ_FLAGS_F_SHFT 0xa +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_CMDQ_ORDER_F_BMSK 0x300 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_CMDQ_ORDER_F_SHFT 0x8 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_CMDQ_SRC_PIPE_F_BMSK 0xff +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_CMDQ_SRC_PIPE_F_SHFT 0x0 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_ADDR(n) (IPA_DEBUG_REG_BASE + \ + 0x00000290 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000290 + 0x2C * \ + (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000290 + 0x2C * \ + (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_RMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_MAXn 3 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_ATTR 0x3 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_INI(n) in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_ADDR(n), \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_RMSK) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_ADDR(n), \ + mask) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_OUTI(n, val) out_dword( \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_ADDR(n), \ + val) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_OUTMI(n, mask, \ + val) out_dword_masked_ns( \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_ADDR( \ + n), \ + mask, \ + val, \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_INI(n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_CMDQ_ADDR_LSB_F_BMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_CMDQ_ADDR_LSB_F_SHFT 0x0 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_ADDR(n) (IPA_DEBUG_REG_BASE + \ + 0x00000294 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000294 + 0x2C * \ + (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000294 + 0x2C * \ + (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_RMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_MAXn 3 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_ATTR 0x3 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_INI(n) in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_ADDR(n), \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_RMSK) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_ADDR(n), \ + mask) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_OUTI(n, val) out_dword( \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_ADDR(n), \ + val) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_OUTMI(n, mask, \ + val) out_dword_masked_ns( \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_ADDR( \ + n), \ + mask, \ + val, \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_INI(n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_CMDQ_ADDR_MSB_F_BMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_CMDQ_ADDR_MSB_F_SHFT 0x0 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_0_n_ADDR(n) (IPA_DEBUG_REG_BASE + \ + 0x00000298 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_0_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000298 + 0x2C * \ + (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_0_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000298 + 0x2C * \ + (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_0_n_RMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_0_n_MAXn 3 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_0_n_ATTR 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_0_n_INI(n) in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_0_n_ADDR(n), \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_0_n_RMSK) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_0_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_0_n_ADDR(n), \ + mask) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_0_n_CMDQ_SRC_LEN_F_BMSK 0xffff0000 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_0_n_CMDQ_SRC_LEN_F_SHFT 0x10 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_0_n_CMDQ_PACKET_LEN_F_BMSK 0xffff +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_0_n_CMDQ_PACKET_LEN_F_SHFT 0x0 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_ADDR(n) (IPA_DEBUG_REG_BASE + \ + 0x0000029c + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS \ + + 0x0000029c + 0x2C * \ + (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS \ + + 0x0000029c + 0x2C * \ + (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_RMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_MAXn 3 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_ATTR 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_INI(n) in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_ADDR(n), \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_RMSK) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_ADDR(n), \ + mask) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_CMDQ_METADATA_F_BMSK 0xff000000 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_CMDQ_METADATA_F_SHFT 0x18 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_CMDQ_OPCODE_F_BMSK 0xff0000 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_CMDQ_OPCODE_F_SHFT 0x10 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_CMDQ_FLAGS_F_BMSK 0xfc00 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_CMDQ_FLAGS_F_SHFT 0xa +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_CMDQ_ORDER_F_BMSK 0x300 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_CMDQ_ORDER_F_SHFT 0x8 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_CMDQ_SRC_PIPE_F_BMSK 0xff +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_CMDQ_SRC_PIPE_F_SHFT 0x0 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_2_n_ADDR(n) (IPA_DEBUG_REG_BASE + \ + 0x000002a0 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_2_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS \ + + 0x000002a0 + 0x2C * \ + (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_2_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS \ + + 0x000002a0 + 0x2C * \ + (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_2_n_RMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_2_n_MAXn 3 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_2_n_ATTR 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_2_n_INI(n) in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_2_n_ADDR(n), \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_2_n_RMSK) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_2_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_2_n_ADDR(n), \ + mask) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_2_n_CMDQ_ADDR_LSB_F_BMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_2_n_CMDQ_ADDR_LSB_F_SHFT 0x0 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_3_n_ADDR(n) (IPA_DEBUG_REG_BASE + \ + 0x000002a4 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_3_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS \ + + 0x000002a4 + 0x2C * \ + (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_3_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS \ + + 0x000002a4 + 0x2C * \ + (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_3_n_RMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_3_n_MAXn 3 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_3_n_ATTR 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_3_n_INI(n) in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_3_n_ADDR(n), \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_3_n_RMSK) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_3_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_3_n_ADDR(n), \ + mask) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_3_n_CMDQ_ADDR_MSB_F_BMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_3_n_CMDQ_ADDR_MSB_F_SHFT 0x0 +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_ADDR(n) (IPA_DEBUG_REG_BASE + \ + 0x000002a8 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000002a8 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000002a8 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_RMSK 0x7f +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_MAXn 3 +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_ATTR 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_INI(n) in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_ADDR(n), \ + HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_RMSK) +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_ADDR(n), \ + mask) +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_CMDQ_DEPTH_BMSK 0x60 +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_CMDQ_DEPTH_SHFT 0x5 +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_CMDQ_COUNT_BMSK 0x18 +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_CMDQ_COUNT_SHFT 0x3 +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_CMDQ_FULL_BMSK 0x4 +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_CMDQ_FULL_SHFT 0x2 +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_CMDQ_EMPTY_BMSK 0x2 +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_CMDQ_EMPTY_SHFT 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_STATUS_BMSK 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_STATUS_SHFT 0x0 +#define HWIO_IPA_TX_COMMANDER_CMDQ_CMD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000035c) +#define HWIO_IPA_TX_COMMANDER_CMDQ_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000035c) +#define HWIO_IPA_TX_COMMANDER_CMDQ_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000035c) +#define HWIO_IPA_TX_COMMANDER_CMDQ_CFG_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000360) +#define HWIO_IPA_TX_COMMANDER_CMDQ_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000360) +#define HWIO_IPA_TX_COMMANDER_CMDQ_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000360) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_0_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000364) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_0_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000364) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_0_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000364) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_1_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000368) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_1_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000368) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_1_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000368) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_2_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000036c) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_2_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x0000036c) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_2_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x0000036c) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_0_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000370) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_0_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000370) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_0_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000370) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_1_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000374) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_1_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000374) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_1_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000374) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_2_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000378) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_2_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000378) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_2_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000378) +#define HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000037c) +#define HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000037c) +#define HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000037c) +#define HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_RMSK 0x7 +#define HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_ATTR 0x1 +#define HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_IN in_dword_masked( \ + HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_ADDR, \ + HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_RMSK) +#define HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_INM(m) in_dword_masked( \ + HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_ADDR, \ + m) +#define HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_CMDQ_FULL_BMSK 0x4 +#define HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_CMDQ_FULL_SHFT 0x2 +#define HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_CMDQ_EMPTY_BMSK 0x2 +#define HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_CMDQ_EMPTY_SHFT 0x1 +#define HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_STATUS_BMSK 0x1 +#define HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_STATUS_SHFT 0x0 +#define HWIO_IPA_RX_HPS_CMDQ_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x00000380) +#define HWIO_IPA_RX_HPS_CMDQ_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000380) +#define HWIO_IPA_RX_HPS_CMDQ_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000380) +#define HWIO_IPA_RX_HPS_CMDQ_CMD_RMSK 0x3f +#define HWIO_IPA_RX_HPS_CMDQ_CMD_ATTR 0x3 +#define HWIO_IPA_RX_HPS_CMDQ_CMD_IN in_dword_masked( \ + HWIO_IPA_RX_HPS_CMDQ_CMD_ADDR, \ + HWIO_IPA_RX_HPS_CMDQ_CMD_RMSK) +#define HWIO_IPA_RX_HPS_CMDQ_CMD_INM(m) in_dword_masked( \ + HWIO_IPA_RX_HPS_CMDQ_CMD_ADDR, \ + m) +#define HWIO_IPA_RX_HPS_CMDQ_CMD_OUT(v) out_dword( \ + HWIO_IPA_RX_HPS_CMDQ_CMD_ADDR, \ + v) +#define HWIO_IPA_RX_HPS_CMDQ_CMD_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_RX_HPS_CMDQ_CMD_ADDR, \ + m, \ + v, \ + HWIO_IPA_RX_HPS_CMDQ_CMD_IN) +#define HWIO_IPA_RX_HPS_CMDQ_CMD_RD_REQ_BMSK 0x20 +#define HWIO_IPA_RX_HPS_CMDQ_CMD_RD_REQ_SHFT 0x5 +#define HWIO_IPA_RX_HPS_CMDQ_CMD_CMD_CLIENT_BMSK 0x1c +#define HWIO_IPA_RX_HPS_CMDQ_CMD_CMD_CLIENT_SHFT 0x2 +#define HWIO_IPA_RX_HPS_CMDQ_CMD_POP_CMD_BMSK 0x2 +#define HWIO_IPA_RX_HPS_CMDQ_CMD_POP_CMD_SHFT 0x1 +#define HWIO_IPA_RX_HPS_CMDQ_CMD_WRITE_CMD_BMSK 0x1 +#define HWIO_IPA_RX_HPS_CMDQ_CMD_WRITE_CMD_SHFT 0x0 +#define HWIO_IPA_RX_HPS_CMDQ_RELEASE_WR_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000384) +#define HWIO_IPA_RX_HPS_CMDQ_RELEASE_WR_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000384) +#define HWIO_IPA_RX_HPS_CMDQ_RELEASE_WR_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000384) +#define HWIO_IPA_RX_HPS_CMDQ_RELEASE_RD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000388) +#define HWIO_IPA_RX_HPS_CMDQ_RELEASE_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000388) +#define HWIO_IPA_RX_HPS_CMDQ_RELEASE_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000388) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_ADDR (IPA_DEBUG_REG_BASE + 0x0000038c) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000038c) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000038c) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_RMSK 0x1f +#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_ATTR 0x3 +#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_IN in_dword_masked( \ + HWIO_IPA_RX_HPS_CMDQ_CFG_WR_ADDR, \ + HWIO_IPA_RX_HPS_CMDQ_CFG_WR_RMSK) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_INM(m) in_dword_masked( \ + HWIO_IPA_RX_HPS_CMDQ_CFG_WR_ADDR, \ + m) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_OUT(v) out_dword( \ + HWIO_IPA_RX_HPS_CMDQ_CFG_WR_ADDR, \ + v) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_RX_HPS_CMDQ_CFG_WR_ADDR, \ + m, \ + v, \ + HWIO_IPA_RX_HPS_CMDQ_CFG_WR_IN) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_BLOCK_WR_BMSK 0x1f +#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_BLOCK_WR_SHFT 0x0 +#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_ADDR (IPA_DEBUG_REG_BASE + 0x00000390) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000390) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000390) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_RMSK 0x1f +#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_ATTR 0x3 +#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_IN in_dword_masked( \ + HWIO_IPA_RX_HPS_CMDQ_CFG_RD_ADDR, \ + HWIO_IPA_RX_HPS_CMDQ_CFG_RD_RMSK) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_INM(m) in_dword_masked( \ + HWIO_IPA_RX_HPS_CMDQ_CFG_RD_ADDR, \ + m) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_OUT(v) out_dword( \ + HWIO_IPA_RX_HPS_CMDQ_CFG_RD_ADDR, \ + v) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_RX_HPS_CMDQ_CFG_RD_ADDR, \ + m, \ + v, \ + HWIO_IPA_RX_HPS_CMDQ_CFG_RD_IN) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_BLOCK_RD_BMSK 0x1f +#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_BLOCK_RD_SHFT 0x0 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_0_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000394) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000394) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000394) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_1_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000398) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_1_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000398) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_1_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000398) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_2_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000039c) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_2_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000039c) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_2_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000039c) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_3_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000003a0) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_3_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000003a0) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_3_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000003a0) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000003a4) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000003a4) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000003a4) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_RMSK 0xffffffff +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_ATTR 0x1 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_IN in_dword_masked( \ + HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_ADDR, \ + HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_RMSK) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_INM(m) in_dword_masked( \ + HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_ADDR, \ + m) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_CMDQ_DEST_LEN_F_BMSK 0xffff0000 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_CMDQ_DEST_LEN_F_SHFT 0x10 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_CMDQ_PACKET_LEN_F_BMSK 0xffff +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_CMDQ_PACKET_LEN_F_SHFT 0x0 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000003a8) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000003a8) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000003a8) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_RMSK 0xffffffff +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_ATTR 0x1 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_IN in_dword_masked( \ + HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_ADDR, \ + HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_RMSK) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_INM(m) in_dword_masked( \ + HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_ADDR, \ + m) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_CMDQ_METADATA_F_BMSK 0xff000000 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_CMDQ_METADATA_F_SHFT 0x18 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_CMDQ_OPCODE_F_BMSK 0xff0000 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_CMDQ_OPCODE_F_SHFT 0x10 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_CMDQ_FLAGS_F_BMSK 0xfc00 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_CMDQ_FLAGS_F_SHFT 0xa +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_CMDQ_ORDER_F_BMSK 0x300 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_CMDQ_ORDER_F_SHFT 0x8 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_CMDQ_SRC_PIPE_F_BMSK 0xff +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_CMDQ_SRC_PIPE_F_SHFT 0x0 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000003ac) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000003ac) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000003ac) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_RMSK 0xffffffff +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_ATTR 0x1 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_IN in_dword_masked( \ + HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_ADDR, \ + HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_RMSK) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_INM(m) in_dword_masked( \ + HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_ADDR, \ + m) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_CMDQ_ADDR_LSB_F_BMSK 0xffffffff +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_CMDQ_ADDR_LSB_F_SHFT 0x0 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000003b0) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000003b0) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000003b0) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_RMSK 0xffffffff +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_ATTR 0x1 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_IN in_dword_masked( \ + HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_ADDR, \ + HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_RMSK) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_INM(m) in_dword_masked( \ + HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_ADDR, \ + m) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_CMDQ_ADDR_MSB_F_BMSK 0xffffffff +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_CMDQ_ADDR_MSB_F_SHFT 0x0 +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x000003b4) +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000003b4) +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000003b4) +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_RMSK 0x1ff +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_ATTR 0x1 +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_IN in_dword_masked( \ + HWIO_IPA_RX_HPS_CMDQ_STATUS_ADDR, \ + HWIO_IPA_RX_HPS_CMDQ_STATUS_RMSK) +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_INM(m) in_dword_masked( \ + HWIO_IPA_RX_HPS_CMDQ_STATUS_ADDR, \ + m) +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_CMDQ_DEPTH_BMSK 0x1fc +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_CMDQ_DEPTH_SHFT 0x2 +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_CMDQ_FULL_BMSK 0x2 +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_CMDQ_FULL_SHFT 0x1 +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_STATUS_BMSK 0x1 +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_STATUS_SHFT 0x0 +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_EMPTY_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000003b8) +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_EMPTY_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000003b8) +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_EMPTY_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000003b8) +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_EMPTY_RMSK 0x1f +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_EMPTY_ATTR 0x1 +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_EMPTY_IN in_dword_masked( \ + HWIO_IPA_RX_HPS_CMDQ_STATUS_EMPTY_ADDR, \ + HWIO_IPA_RX_HPS_CMDQ_STATUS_EMPTY_RMSK) +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_EMPTY_INM(m) in_dword_masked( \ + HWIO_IPA_RX_HPS_CMDQ_STATUS_EMPTY_ADDR, \ + m) +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_EMPTY_CMDQ_EMPTY_BMSK 0x1f +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_EMPTY_CMDQ_EMPTY_SHFT 0x0 +#define HWIO_IPA_RX_HPS_SNP_ADDR (IPA_DEBUG_REG_BASE + 0x000003bc) +#define HWIO_IPA_RX_HPS_SNP_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000003bc) +#define HWIO_IPA_RX_HPS_SNP_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000003bc) +#define HWIO_IPA_RX_HPS_CMDQ_COUNT_ADDR (IPA_DEBUG_REG_BASE + 0x000003c0) +#define HWIO_IPA_RX_HPS_CMDQ_COUNT_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000003c0) +#define HWIO_IPA_RX_HPS_CMDQ_COUNT_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000003c0) +#define HWIO_IPA_RX_HPS_CMDQ_COUNT_RMSK 0x7f +#define HWIO_IPA_RX_HPS_CMDQ_COUNT_ATTR 0x1 +#define HWIO_IPA_RX_HPS_CMDQ_COUNT_IN in_dword_masked( \ + HWIO_IPA_RX_HPS_CMDQ_COUNT_ADDR, \ + HWIO_IPA_RX_HPS_CMDQ_COUNT_RMSK) +#define HWIO_IPA_RX_HPS_CMDQ_COUNT_INM(m) in_dword_masked( \ + HWIO_IPA_RX_HPS_CMDQ_COUNT_ADDR, \ + m) +#define HWIO_IPA_RX_HPS_CMDQ_COUNT_FIFO_COUNT_BMSK 0x7f +#define HWIO_IPA_RX_HPS_CMDQ_COUNT_FIFO_COUNT_SHFT 0x0 +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000003c4) +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x000003c4) +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x000003c4) +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_RMSK 0xff0f0f0f +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_ATTR 0x3 +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_IN in_dword_masked( \ + HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_ADDR, \ + HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_RMSK) +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_INM(m) in_dword_masked( \ + HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_ADDR, \ + m) +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_OUT(v) out_dword( \ + HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_ADDR, \ + v) +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_ADDR, \ + m, \ + v, \ + HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_IN) +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_CLIENT_4_MIN_DEPTH_BMSK \ + 0xf0000000 +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_CLIENT_4_MIN_DEPTH_SHFT 0x1c +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_CLIENT_3_MIN_DEPTH_BMSK \ + 0xf000000 +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_CLIENT_3_MIN_DEPTH_SHFT 0x18 +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_CLIENT_2_MIN_DEPTH_BMSK \ + 0xf0000 +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_CLIENT_2_MIN_DEPTH_SHFT 0x10 +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_CLIENT_1_MIN_DEPTH_BMSK 0xf00 +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_CLIENT_1_MIN_DEPTH_SHFT 0x8 +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_CLIENT_0_MIN_DEPTH_BMSK 0xf +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_CLIENT_0_MIN_DEPTH_SHFT 0x0 +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000003cc) +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x000003cc) +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x000003cc) +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_RMSK 0xff0f0f0f +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_ATTR 0x3 +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_IN in_dword_masked( \ + HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_ADDR, \ + HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_RMSK) +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_INM(m) in_dword_masked( \ + HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_ADDR, \ + m) +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_OUT(v) out_dword( \ + HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_ADDR, \ + v) +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_ADDR, \ + m, \ + v, \ + HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_IN) +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_CLIENT_4_MAX_DEPTH_BMSK \ + 0xf0000000 +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_CLIENT_4_MAX_DEPTH_SHFT 0x1c +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_CLIENT_3_MAX_DEPTH_BMSK \ + 0xf000000 +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_CLIENT_3_MAX_DEPTH_SHFT 0x18 +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_CLIENT_2_MAX_DEPTH_BMSK \ + 0xf0000 +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_CLIENT_2_MAX_DEPTH_SHFT 0x10 +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_CLIENT_1_MAX_DEPTH_BMSK 0xf00 +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_CLIENT_1_MAX_DEPTH_SHFT 0x8 +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_CLIENT_0_MAX_DEPTH_BMSK 0xf +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_CLIENT_0_MAX_DEPTH_SHFT 0x0 +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x000003d4) +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000003d4) +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000003d4) +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_RMSK 0xff +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_ATTR 0x3 +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_IN in_dword_masked( \ + HWIO_IPA_HPS_DPS_CMDQ_CMD_ADDR, \ + HWIO_IPA_HPS_DPS_CMDQ_CMD_RMSK) +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_INM(m) in_dword_masked( \ + HWIO_IPA_HPS_DPS_CMDQ_CMD_ADDR, \ + m) +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_OUT(v) out_dword( \ + HWIO_IPA_HPS_DPS_CMDQ_CMD_ADDR, \ + v) +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_HPS_DPS_CMDQ_CMD_ADDR, \ + m, \ + v, \ + HWIO_IPA_HPS_DPS_CMDQ_CMD_IN) +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_RD_REQ_BMSK 0x80 +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_RD_REQ_SHFT 0x7 +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_CMD_CLIENT_BMSK 0x7c +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_CMD_CLIENT_SHFT 0x2 +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_POP_CMD_BMSK 0x2 +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_POP_CMD_SHFT 0x1 +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_WRITE_CMD_BMSK 0x1 +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_WRITE_CMD_SHFT 0x0 +#define HWIO_IPA_HPS_DPS_CMDQ_RELEASE_WR_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000003d8) +#define HWIO_IPA_HPS_DPS_CMDQ_RELEASE_WR_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000003d8) +#define HWIO_IPA_HPS_DPS_CMDQ_RELEASE_WR_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000003d8) +#define HWIO_IPA_HPS_DPS_CMDQ_RELEASE_RD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000003dc) +#define HWIO_IPA_HPS_DPS_CMDQ_RELEASE_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000003dc) +#define HWIO_IPA_HPS_DPS_CMDQ_RELEASE_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000003dc) +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_WR_ADDR (IPA_DEBUG_REG_BASE + 0x000003e0) +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_WR_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000003e0) +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_WR_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000003e0) +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_RD_ADDR (IPA_DEBUG_REG_BASE + 0x000003e4) +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000003e4) +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000003e4) +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000003e8) +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000003e8) +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000003e8) +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000003ec) +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000003ec) +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000003ec) +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_RMSK 0xfffff +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_ATTR 0x1 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_IN in_dword_masked( \ + HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_ADDR, \ + HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_RMSK) +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_INM(m) in_dword_masked( \ + HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_ADDR, \ + m) +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_CMDQ_REP_F_BMSK 0x80000 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_CMDQ_REP_F_SHFT 0x13 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_CMDQ_OPCODE_F_BMSK 0x60000 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_CMDQ_OPCODE_F_SHFT 0x11 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_CMDQ_SRC_PIPE_F_BMSK 0x1f000 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_CMDQ_SRC_PIPE_F_SHFT 0xc +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_CMDQ_SRC_ID_F_BMSK 0xff0 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_CMDQ_SRC_ID_F_SHFT 0x4 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_CMDQ_CTX_ID_F_BMSK 0xf +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_CMDQ_CTX_ID_F_SHFT 0x0 +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x000003f0) +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000003f0) +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000003f0) +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_RMSK 0xff +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_ATTR 0x1 +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_IN in_dword_masked( \ + HWIO_IPA_HPS_DPS_CMDQ_STATUS_ADDR, \ + HWIO_IPA_HPS_DPS_CMDQ_STATUS_RMSK) +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_INM(m) in_dword_masked( \ + HWIO_IPA_HPS_DPS_CMDQ_STATUS_ADDR, \ + m) +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_CMDQ_DEPTH_BMSK 0xfc +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_CMDQ_DEPTH_SHFT 0x2 +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_CMDQ_FULL_BMSK 0x2 +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_CMDQ_FULL_SHFT 0x1 +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_STATUS_BMSK 0x1 +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_STATUS_SHFT 0x0 +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_EMPTY_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000003f4) +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_EMPTY_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000003f4) +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_EMPTY_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000003f4) +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_EMPTY_RMSK 0x7fffffff +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_EMPTY_ATTR 0x1 +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_EMPTY_IN in_dword_masked( \ + HWIO_IPA_HPS_DPS_CMDQ_STATUS_EMPTY_ADDR, \ + HWIO_IPA_HPS_DPS_CMDQ_STATUS_EMPTY_RMSK) +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_EMPTY_INM(m) in_dword_masked( \ + HWIO_IPA_HPS_DPS_CMDQ_STATUS_EMPTY_ADDR, \ + m) +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_EMPTY_CMDQ_EMPTY_BMSK 0x7fffffff +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_EMPTY_CMDQ_EMPTY_SHFT 0x0 +#define HWIO_IPA_HPS_DPS_SNP_ADDR (IPA_DEBUG_REG_BASE + 0x000003f8) +#define HWIO_IPA_HPS_DPS_SNP_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000003f8) +#define HWIO_IPA_HPS_DPS_SNP_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000003f8) +#define HWIO_IPA_HPS_DPS_CMDQ_COUNT_ADDR (IPA_DEBUG_REG_BASE + 0x000003fc) +#define HWIO_IPA_HPS_DPS_CMDQ_COUNT_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000003fc) +#define HWIO_IPA_HPS_DPS_CMDQ_COUNT_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000003fc) +#define HWIO_IPA_HPS_DPS_CMDQ_COUNT_RMSK 0x3f +#define HWIO_IPA_HPS_DPS_CMDQ_COUNT_ATTR 0x1 +#define HWIO_IPA_HPS_DPS_CMDQ_COUNT_IN in_dword_masked( \ + HWIO_IPA_HPS_DPS_CMDQ_COUNT_ADDR, \ + HWIO_IPA_HPS_DPS_CMDQ_COUNT_RMSK) +#define HWIO_IPA_HPS_DPS_CMDQ_COUNT_INM(m) in_dword_masked( \ + HWIO_IPA_HPS_DPS_CMDQ_COUNT_ADDR, \ + m) +#define HWIO_IPA_HPS_DPS_CMDQ_COUNT_FIFO_COUNT_BMSK 0x3f +#define HWIO_IPA_HPS_DPS_CMDQ_COUNT_FIFO_COUNT_SHFT 0x0 +#define HWIO_IPA_DPS_TX_CMDQ_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x00000400) +#define HWIO_IPA_DPS_TX_CMDQ_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000400) +#define HWIO_IPA_DPS_TX_CMDQ_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000400) +#define HWIO_IPA_DPS_TX_CMDQ_CMD_RMSK 0xbf +#define HWIO_IPA_DPS_TX_CMDQ_CMD_ATTR 0x3 +#define HWIO_IPA_DPS_TX_CMDQ_CMD_IN in_dword_masked( \ + HWIO_IPA_DPS_TX_CMDQ_CMD_ADDR, \ + HWIO_IPA_DPS_TX_CMDQ_CMD_RMSK) +#define HWIO_IPA_DPS_TX_CMDQ_CMD_INM(m) in_dword_masked( \ + HWIO_IPA_DPS_TX_CMDQ_CMD_ADDR, \ + m) +#define HWIO_IPA_DPS_TX_CMDQ_CMD_OUT(v) out_dword( \ + HWIO_IPA_DPS_TX_CMDQ_CMD_ADDR, \ + v) +#define HWIO_IPA_DPS_TX_CMDQ_CMD_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_DPS_TX_CMDQ_CMD_ADDR, \ + m, \ + v, \ + HWIO_IPA_DPS_TX_CMDQ_CMD_IN) +#define HWIO_IPA_DPS_TX_CMDQ_CMD_RD_REQ_BMSK 0x80 +#define HWIO_IPA_DPS_TX_CMDQ_CMD_RD_REQ_SHFT 0x7 +#define HWIO_IPA_DPS_TX_CMDQ_CMD_CMD_CLIENT_BMSK 0x3c +#define HWIO_IPA_DPS_TX_CMDQ_CMD_CMD_CLIENT_SHFT 0x2 +#define HWIO_IPA_DPS_TX_CMDQ_CMD_POP_CMD_BMSK 0x2 +#define HWIO_IPA_DPS_TX_CMDQ_CMD_POP_CMD_SHFT 0x1 +#define HWIO_IPA_DPS_TX_CMDQ_CMD_WRITE_CMD_BMSK 0x1 +#define HWIO_IPA_DPS_TX_CMDQ_CMD_WRITE_CMD_SHFT 0x0 +#define HWIO_IPA_DPS_TX_CMDQ_RELEASE_WR_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000404) +#define HWIO_IPA_DPS_TX_CMDQ_RELEASE_WR_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000404) +#define HWIO_IPA_DPS_TX_CMDQ_RELEASE_WR_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000404) +#define HWIO_IPA_DPS_TX_CMDQ_RELEASE_RD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000408) +#define HWIO_IPA_DPS_TX_CMDQ_RELEASE_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000408) +#define HWIO_IPA_DPS_TX_CMDQ_RELEASE_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000408) +#define HWIO_IPA_DPS_TX_CMDQ_CFG_WR_ADDR (IPA_DEBUG_REG_BASE + 0x0000040c) +#define HWIO_IPA_DPS_TX_CMDQ_CFG_WR_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000040c) +#define HWIO_IPA_DPS_TX_CMDQ_CFG_WR_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000040c) +#define HWIO_IPA_DPS_TX_CMDQ_CFG_RD_ADDR (IPA_DEBUG_REG_BASE + 0x00000410) +#define HWIO_IPA_DPS_TX_CMDQ_CFG_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000410) +#define HWIO_IPA_DPS_TX_CMDQ_CFG_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000410) +#define HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000414) +#define HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000414) +#define HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000414) +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000418) +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000418) +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000418) +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_RMSK 0xfffff +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_ATTR 0x1 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_IN in_dword_masked( \ + HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_ADDR, \ + HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_RMSK) +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_INM(m) in_dword_masked( \ + HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_ADDR, \ + m) +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_CMDQ_REP_F_BMSK 0x80000 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_CMDQ_REP_F_SHFT 0x13 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_CMDQ_OPCODE_F_BMSK 0x60000 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_CMDQ_OPCODE_F_SHFT 0x11 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_CMDQ_SRC_PIPE_F_BMSK 0x1f000 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_CMDQ_SRC_PIPE_F_SHFT 0xc +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_CMDQ_SRC_ID_F_BMSK 0xff0 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_CMDQ_SRC_ID_F_SHFT 0x4 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_CMDQ_CTX_ID_F_BMSK 0xf +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_CMDQ_CTX_ID_F_SHFT 0x0 +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x0000041c) +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000041c) +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000041c) +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_RMSK 0x1ff +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_ATTR 0x1 +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_IN in_dword_masked( \ + HWIO_IPA_DPS_TX_CMDQ_STATUS_ADDR, \ + HWIO_IPA_DPS_TX_CMDQ_STATUS_RMSK) +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_INM(m) in_dword_masked( \ + HWIO_IPA_DPS_TX_CMDQ_STATUS_ADDR, \ + m) +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_CMDQ_DEPTH_BMSK 0x1fc +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_CMDQ_DEPTH_SHFT 0x2 +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_CMDQ_FULL_BMSK 0x2 +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_CMDQ_FULL_SHFT 0x1 +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_STATUS_BMSK 0x1 +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_STATUS_SHFT 0x0 +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_EMPTY_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000420) +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_EMPTY_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000420) +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_EMPTY_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000420) +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_EMPTY_RMSK 0x3ff +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_EMPTY_ATTR 0x1 +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_EMPTY_IN in_dword_masked( \ + HWIO_IPA_DPS_TX_CMDQ_STATUS_EMPTY_ADDR, \ + HWIO_IPA_DPS_TX_CMDQ_STATUS_EMPTY_RMSK) +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_EMPTY_INM(m) in_dword_masked( \ + HWIO_IPA_DPS_TX_CMDQ_STATUS_EMPTY_ADDR, \ + m) +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_EMPTY_CMDQ_EMPTY_BMSK 0x3ff +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_EMPTY_CMDQ_EMPTY_SHFT 0x0 +#define HWIO_IPA_DPS_TX_SNP_ADDR (IPA_DEBUG_REG_BASE + 0x00000424) +#define HWIO_IPA_DPS_TX_SNP_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000424) +#define HWIO_IPA_DPS_TX_SNP_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000424) +#define HWIO_IPA_DPS_TX_CMDQ_COUNT_ADDR (IPA_DEBUG_REG_BASE + 0x00000428) +#define HWIO_IPA_DPS_TX_CMDQ_COUNT_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000428) +#define HWIO_IPA_DPS_TX_CMDQ_COUNT_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000428) +#define HWIO_IPA_DPS_TX_CMDQ_COUNT_RMSK 0x7f +#define HWIO_IPA_DPS_TX_CMDQ_COUNT_ATTR 0x1 +#define HWIO_IPA_DPS_TX_CMDQ_COUNT_IN in_dword_masked( \ + HWIO_IPA_DPS_TX_CMDQ_COUNT_ADDR, \ + HWIO_IPA_DPS_TX_CMDQ_COUNT_RMSK) +#define HWIO_IPA_DPS_TX_CMDQ_COUNT_INM(m) in_dword_masked( \ + HWIO_IPA_DPS_TX_CMDQ_COUNT_ADDR, \ + m) +#define HWIO_IPA_DPS_TX_CMDQ_COUNT_FIFO_COUNT_BMSK 0x7f +#define HWIO_IPA_DPS_TX_CMDQ_COUNT_FIFO_COUNT_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000042c) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000042c) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000042c) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_RMSK 0x7 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_ADDR, \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_RMSK) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_IN) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_BITMAP_BMSK 0x7 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_BITMAP_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000430) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000430) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000430) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_RMSK 0x7 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_ADDR, \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_RMSK) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_OUTM(m, \ + v) \ + out_dword_masked_ns(HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_IN) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_BITMAP_BMSK 0x7 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_BITMAP_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000434) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000434) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000434) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_RMSK 0xfff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_ADDR, \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_RMSK) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_IN) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_ALL_CLI_MUX_CONCAT_BMSK 0xfff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_ALL_CLI_MUX_CONCAT_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_ADDR(n) ( \ + IPA_DEBUG_REG_BASE + 0x00000438 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_PHYS(n) ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000438 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_OFFS(n) ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000438 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_MAXn 2 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_INI(n) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_ADDR( \ + n), \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_RMSK) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_INMI(n, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_ADDR(n), \ + mask) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_OUTI(n, \ + val) out_dword( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_ADDR( \ + n), \ + val) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_INI(n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_ADDR(n) ( \ + IPA_DEBUG_REG_BASE + 0x0000043c + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_PHYS(n) ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x0000043c + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_OFFS(n) ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x0000043c + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_MAXn 2 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_INI(n) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_ADDR( \ + n), \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_RMSK) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_INMI(n, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_ADDR(n), \ + mask) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_OUTI(n, \ + val) out_dword( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_ADDR( \ + n), \ + val) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_INI(n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_ADDR(n) ( \ + IPA_DEBUG_REG_BASE + 0x00000440 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_PHYS(n) ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000440 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_OFFS(n) ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000440 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_MAXn 2 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_INI(n) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_ADDR( \ + n), \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_RMSK) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_INMI(n, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_ADDR(n), \ + mask) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_OUTI(n, \ + val) out_dword( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_ADDR( \ + n), \ + val) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_INI(n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_ADDR(n) ( \ + IPA_DEBUG_REG_BASE + 0x00000444 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_PHYS(n) ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000444 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_OFFS(n) ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000444 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_MAXn 2 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_INI(n) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_ADDR( \ + n), \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_RMSK) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_INMI(n, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_ADDR(n), \ + mask) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_OUTI(n, \ + val) out_dword( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_ADDR( \ + n), \ + val) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_INI(n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_ADDR(n) ( \ + IPA_DEBUG_REG_BASE + 0x00000468 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_PHYS(n) ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000468 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_OFFS(n) ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000468 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_MAXn 2 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_INI(n) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_ADDR( \ + n), \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_RMSK) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_INMI(n, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_ADDR(n), \ + mask) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_OUTI(n, \ + val) out_dword( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_ADDR( \ + n), \ + val) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_INI(n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_ADDR(n) ( \ + IPA_DEBUG_REG_BASE + 0x0000046c + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_PHYS(n) ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x0000046c + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_OFFS(n) ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x0000046c + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_MAXn 2 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_INI(n) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_ADDR( \ + n), \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_RMSK) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_INMI(n, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_ADDR(n), \ + mask) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_OUTI(n, \ + val) out_dword( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_ADDR( \ + n), \ + val) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_INI(n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_ADDR(n) ( \ + IPA_DEBUG_REG_BASE + 0x00000470 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_PHYS(n) ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000470 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_OFFS(n) ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000470 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_MAXn 2 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_INI(n) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_ADDR( \ + n), \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_RMSK) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_INMI(n, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_ADDR(n), \ + mask) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_OUTI(n, \ + val) out_dword( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_ADDR( \ + n), \ + val) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_INI(n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_ADDR(n) ( \ + IPA_DEBUG_REG_BASE + 0x00000474 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_PHYS(n) ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000474 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_OFFS(n) ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000474 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_MAXn 2 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_INI(n) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_ADDR( \ + n), \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_RMSK) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_INMI(n, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_ADDR(n), \ + mask) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_OUTI(n, \ + val) out_dword( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_ADDR( \ + n), \ + val) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_INI(n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000498) +#define HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000498) +#define HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000498) +#define HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_RMSK 0x7 +#define HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_ADDR, \ + HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_RMSK) +#define HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_IN) +#define HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_SRC_GROUP_SEL_BMSK 0x7 +#define HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_SRC_GROUP_SEL_SHFT 0x0 +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x000004a0) +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004a0) +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004a0) +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_RMSK 0xff +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_ATTR 0x3 +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_IN in_dword_masked( \ + HWIO_IPA_ACKMNGR_CMDQ_CMD_ADDR, \ + HWIO_IPA_ACKMNGR_CMDQ_CMD_RMSK) +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_INM(m) in_dword_masked( \ + HWIO_IPA_ACKMNGR_CMDQ_CMD_ADDR, \ + m) +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_OUT(v) out_dword( \ + HWIO_IPA_ACKMNGR_CMDQ_CMD_ADDR, \ + v) +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_ACKMNGR_CMDQ_CMD_ADDR, \ + m, \ + v, \ + HWIO_IPA_ACKMNGR_CMDQ_CMD_IN) +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_RD_REQ_BMSK 0x80 +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_RD_REQ_SHFT 0x7 +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_CMD_CLIENT_BMSK 0x7c +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_CMD_CLIENT_SHFT 0x2 +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_POP_CMD_BMSK 0x2 +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_POP_CMD_SHFT 0x1 +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_WRITE_CMD_BMSK 0x1 +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_WRITE_CMD_SHFT 0x0 +#define HWIO_IPA_ACKMNGR_CMDQ_RELEASE_WR_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000004a4) +#define HWIO_IPA_ACKMNGR_CMDQ_RELEASE_WR_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004a4) +#define HWIO_IPA_ACKMNGR_CMDQ_RELEASE_WR_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004a4) +#define HWIO_IPA_ACKMNGR_CMDQ_RELEASE_RD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000004a8) +#define HWIO_IPA_ACKMNGR_CMDQ_RELEASE_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004a8) +#define HWIO_IPA_ACKMNGR_CMDQ_RELEASE_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004a8) +#define HWIO_IPA_ACKMNGR_CMDQ_CFG_WR_ADDR (IPA_DEBUG_REG_BASE + 0x000004ac) +#define HWIO_IPA_ACKMNGR_CMDQ_CFG_WR_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004ac) +#define HWIO_IPA_ACKMNGR_CMDQ_CFG_WR_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004ac) +#define HWIO_IPA_ACKMNGR_CMDQ_CFG_RD_ADDR (IPA_DEBUG_REG_BASE + 0x000004b0) +#define HWIO_IPA_ACKMNGR_CMDQ_CFG_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004b0) +#define HWIO_IPA_ACKMNGR_CMDQ_CFG_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004b0) +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_WR_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000004b4) +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_WR_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004b4) +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_WR_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004b4) +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000004b8) +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004b8) +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004b8) +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_RMSK 0x7ffffff +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_ATTR 0x1 +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_IN in_dword_masked( \ + HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_ADDR, \ + HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_RMSK) +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_INM(m) in_dword_masked( \ + HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_ADDR, \ + m) +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_CMDQ_SRC_ID_VALID_BMSK 0x4000000 +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_CMDQ_SRC_ID_VALID_SHFT 0x1a +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_CMDQ_SENT_BMSK 0x2000000 +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_CMDQ_SENT_SHFT 0x19 +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_CMDQ_ORIGIN_BMSK 0x1000000 +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_CMDQ_ORIGIN_SHFT 0x18 +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_CMDQ_LENGTH_BMSK 0xffff00 +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_CMDQ_LENGTH_SHFT 0x8 +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_CMDQ_SRC_ID_BMSK 0xff +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_CMDQ_SRC_ID_SHFT 0x0 +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x000004bc) +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004bc) +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004bc) +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_RMSK 0x1ff +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_ATTR 0x1 +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_IN in_dword_masked( \ + HWIO_IPA_ACKMNGR_CMDQ_STATUS_ADDR, \ + HWIO_IPA_ACKMNGR_CMDQ_STATUS_RMSK) +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_INM(m) in_dword_masked( \ + HWIO_IPA_ACKMNGR_CMDQ_STATUS_ADDR, \ + m) +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_CMDQ_DEPTH_BMSK 0x1fc +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_CMDQ_DEPTH_SHFT 0x2 +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_CMDQ_FULL_BMSK 0x2 +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_CMDQ_FULL_SHFT 0x1 +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_STATUS_BMSK 0x1 +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_STATUS_SHFT 0x0 +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_EMPTY_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000004c0) +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_EMPTY_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004c0) +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_EMPTY_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004c0) +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_EMPTY_RMSK 0x1fff +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_EMPTY_ATTR 0x1 +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_EMPTY_IN in_dword_masked( \ + HWIO_IPA_ACKMNGR_CMDQ_STATUS_EMPTY_ADDR, \ + HWIO_IPA_ACKMNGR_CMDQ_STATUS_EMPTY_RMSK) +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_EMPTY_INM(m) in_dword_masked( \ + HWIO_IPA_ACKMNGR_CMDQ_STATUS_EMPTY_ADDR, \ + m) +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_EMPTY_CMDQ_EMPTY_BMSK 0x1fff +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_EMPTY_CMDQ_EMPTY_SHFT 0x0 +#define HWIO_IPA_ACKMNGR_CMDQ_COUNT_ADDR (IPA_DEBUG_REG_BASE + 0x000004c4) +#define HWIO_IPA_ACKMNGR_CMDQ_COUNT_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004c4) +#define HWIO_IPA_ACKMNGR_CMDQ_COUNT_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004c4) +#define HWIO_IPA_ACKMNGR_CMDQ_COUNT_RMSK 0x7f +#define HWIO_IPA_ACKMNGR_CMDQ_COUNT_ATTR 0x1 +#define HWIO_IPA_ACKMNGR_CMDQ_COUNT_IN in_dword_masked( \ + HWIO_IPA_ACKMNGR_CMDQ_COUNT_ADDR, \ + HWIO_IPA_ACKMNGR_CMDQ_COUNT_RMSK) +#define HWIO_IPA_ACKMNGR_CMDQ_COUNT_INM(m) in_dword_masked( \ + HWIO_IPA_ACKMNGR_CMDQ_COUNT_ADDR, \ + m) +#define HWIO_IPA_ACKMNGR_CMDQ_COUNT_FIFO_COUNT_BMSK 0x7f +#define HWIO_IPA_ACKMNGR_CMDQ_COUNT_FIFO_COUNT_SHFT 0x0 +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000004c8) +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004c8) +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004c8) +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_RMSK 0x3f +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_ATTR 0x3 +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_IN in_dword_masked( \ + HWIO_IPA_GSI_FIFO_STATUS_CTRL_ADDR, \ + HWIO_IPA_GSI_FIFO_STATUS_CTRL_RMSK) +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_FIFO_STATUS_CTRL_ADDR, \ + m) +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_OUT(v) out_dword( \ + HWIO_IPA_GSI_FIFO_STATUS_CTRL_ADDR, \ + v) +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_GSI_FIFO_STATUS_CTRL_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_FIFO_STATUS_CTRL_IN) +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_IPA_GSI_FIFO_STATUS_EN_BMSK 0x20 +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_IPA_GSI_FIFO_STATUS_EN_SHFT 0x5 +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_IPA_GSI_FIFO_STATUS_PORT_SEL_BMSK \ + 0x1f +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_IPA_GSI_FIFO_STATUS_PORT_SEL_SHFT \ + 0x0 +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x000004cc) +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004cc) +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004cc) +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_RMSK 0x7fffffff +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_ATTR 0x1 +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_IN in_dword_masked( \ + HWIO_IPA_GSI_TLV_FIFO_STATUS_ADDR, \ + HWIO_IPA_GSI_TLV_FIFO_STATUS_RMSK) +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TLV_FIFO_STATUS_ADDR, \ + m) +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FIFO_HEAD_IS_BUBBLE_BMSK 0x40000000 +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FIFO_HEAD_IS_BUBBLE_SHFT 0x1e +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FIFO_FULL_PUB_BMSK 0x20000000 +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FIFO_FULL_PUB_SHFT 0x1d +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FIFO_ALMOST_FULL_PUB_BMSK 0x10000000 +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FIFO_ALMOST_FULL_PUB_SHFT 0x1c +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FIFO_FULL_BMSK 0x8000000 +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FIFO_FULL_SHFT 0x1b +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FIFO_ALMOST_FULL_BMSK 0x4000000 +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FIFO_ALMOST_FULL_SHFT 0x1a +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FIFO_EMPTY_PUB_BMSK 0x2000000 +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FIFO_EMPTY_PUB_SHFT 0x19 +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FIFO_EMPTY_BMSK 0x1000000 +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FIFO_EMPTY_SHFT 0x18 +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FIFO_RD_PUB_PTR_BMSK 0xff0000 +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FIFO_RD_PUB_PTR_SHFT 0x10 +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FIFO_RD_PTR_BMSK 0xff00 +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FIFO_RD_PTR_SHFT 0x8 +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FIFO_WR_PTR_BMSK 0xff +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FIFO_WR_PTR_SHFT 0x0 +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x000004d0) +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004d0) +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004d0) +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_RMSK 0x7fffffff +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_ATTR 0x1 +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_IN in_dword_masked( \ + HWIO_IPA_GSI_AOS_FIFO_STATUS_ADDR, \ + HWIO_IPA_GSI_AOS_FIFO_STATUS_RMSK) +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_AOS_FIFO_STATUS_ADDR, \ + m) +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FIFO_HEAD_IS_BUBBLE_BMSK 0x40000000 +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FIFO_HEAD_IS_BUBBLE_SHFT 0x1e +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FIFO_FULL_PUB_BMSK 0x20000000 +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FIFO_FULL_PUB_SHFT 0x1d +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FIFO_ALMOST_FULL_PUB_BMSK 0x10000000 +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FIFO_ALMOST_FULL_PUB_SHFT 0x1c +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FIFO_FULL_BMSK 0x8000000 +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FIFO_FULL_SHFT 0x1b +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FIFO_ALMOST_FULL_BMSK 0x4000000 +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FIFO_ALMOST_FULL_SHFT 0x1a +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FIFO_EMPTY_PUB_BMSK 0x2000000 +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FIFO_EMPTY_PUB_SHFT 0x19 +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FIFO_EMPTY_BMSK 0x1000000 +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FIFO_EMPTY_SHFT 0x18 +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FIFO_RD_PUB_PTR_BMSK 0xff0000 +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FIFO_RD_PUB_PTR_SHFT 0x10 +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FIFO_RD_PTR_BMSK 0xff00 +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FIFO_RD_PTR_SHFT 0x8 +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FIFO_WR_PTR_BMSK 0xff +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FIFO_WR_PTR_SHFT 0x0 +#define HWIO_IPA_ENDP_GSI_CONS_BYTES_TLV_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000004d4) +#define HWIO_IPA_ENDP_GSI_CONS_BYTES_TLV_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004d4) +#define HWIO_IPA_ENDP_GSI_CONS_BYTES_TLV_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004d4) +#define HWIO_IPA_ENDP_GSI_CONS_BYTES_AOS_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000548) +#define HWIO_IPA_ENDP_GSI_CONS_BYTES_AOS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000548) +#define HWIO_IPA_ENDP_GSI_CONS_BYTES_AOS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000548) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_0_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000004d8) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004d8) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004d8) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_0_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_0_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_0_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_0_ADDR, \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_0_RMSK) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_0_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_0_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_0_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_0_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_0_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_0_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_0_IN) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_0_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_0_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_1_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000004dc) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_1_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004dc) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_1_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004dc) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_1_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_1_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_1_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_1_ADDR, \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_1_RMSK) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_1_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_1_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_1_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_1_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_1_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_1_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_1_IN) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_1_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_1_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_2_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000004e0) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_2_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004e0) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_2_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004e0) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_2_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_2_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_2_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_2_ADDR, \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_2_RMSK) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_2_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_2_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_2_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_2_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_2_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_2_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_2_IN) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_2_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_2_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_3_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000004e4) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_3_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004e4) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_3_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004e4) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_3_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_3_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_3_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_3_ADDR, \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_3_RMSK) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_3_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_3_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_3_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_3_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_3_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_3_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_3_IN) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_3_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_3_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_4_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000004e8) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_4_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004e8) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_4_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004e8) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_4_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_4_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_4_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_4_ADDR, \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_4_RMSK) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_4_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_4_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_4_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_4_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_4_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_4_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_4_IN) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_4_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_4_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_5_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000004ec) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_5_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004ec) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_5_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004ec) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_5_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_5_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_5_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_5_ADDR, \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_5_RMSK) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_5_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_5_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_5_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_5_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_5_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_5_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_5_IN) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_5_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_5_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_6_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000004f0) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_6_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004f0) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_6_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004f0) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_6_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_6_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_6_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_6_ADDR, \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_6_RMSK) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_6_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_6_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_6_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_6_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_6_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_6_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_6_IN) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_6_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_6_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_7_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000004f4) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_7_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004f4) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_7_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004f4) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_7_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_7_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_7_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_7_ADDR, \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_7_RMSK) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_7_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_7_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_7_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_7_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_7_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_7_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_7_IN) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_7_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_7_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_0_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000004f8) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004f8) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004f8) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_0_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_0_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_0_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_0_ADDR, \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_0_RMSK) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_0_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_0_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_0_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_0_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_0_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_0_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_0_IN) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_0_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_0_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_1_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000004fc) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_1_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004fc) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_1_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004fc) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_1_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_1_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_1_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_1_ADDR, \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_1_RMSK) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_1_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_1_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_1_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_1_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_1_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_1_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_1_IN) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_1_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_1_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_2_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000500) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_2_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000500) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_2_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000500) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_2_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_2_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_2_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_2_ADDR, \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_2_RMSK) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_2_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_2_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_2_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_2_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_2_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_2_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_2_IN) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_2_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_2_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_3_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000504) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_3_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000504) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_3_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000504) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_3_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_3_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_3_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_3_ADDR, \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_3_RMSK) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_3_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_3_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_3_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_3_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_3_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_3_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_3_IN) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_3_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_3_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_4_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000508) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_4_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000508) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_4_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000508) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_4_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_4_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_4_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_4_ADDR, \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_4_RMSK) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_4_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_4_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_4_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_4_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_4_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_4_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_4_IN) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_4_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_4_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_5_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000050c) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_5_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000050c) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_5_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000050c) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_5_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_5_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_5_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_5_ADDR, \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_5_RMSK) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_5_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_5_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_5_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_5_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_5_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_5_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_5_IN) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_5_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_5_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_6_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000510) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_6_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000510) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_6_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000510) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_6_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_6_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_6_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_6_ADDR, \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_6_RMSK) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_6_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_6_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_6_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_6_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_6_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_6_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_6_IN) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_6_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_6_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_7_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000514) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_7_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000514) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_7_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000514) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_7_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_7_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_7_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_7_ADDR, \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_7_RMSK) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_7_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_7_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_7_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_7_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_7_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_7_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_7_IN) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_7_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_7_VALUE_SHFT 0x0 +#define HWIO_IPA_UC_RX_HND_CMDQ_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x00000518) +#define HWIO_IPA_UC_RX_HND_CMDQ_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000518) +#define HWIO_IPA_UC_RX_HND_CMDQ_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000518) +#define HWIO_IPA_UC_RX_HND_CMDQ_CFG_ADDR (IPA_DEBUG_REG_BASE + 0x0000051c) +#define HWIO_IPA_UC_RX_HND_CMDQ_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000051c) +#define HWIO_IPA_UC_RX_HND_CMDQ_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000051c) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_0_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000520) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000520) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000520) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_1_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000524) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_1_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000524) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_1_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000524) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_2_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000528) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_2_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000528) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_2_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000528) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_3_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000052c) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_3_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000052c) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_3_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000052c) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_0_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000530) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000530) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000530) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_1_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000534) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_1_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000534) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_1_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000534) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_2_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000538) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_2_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000538) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_2_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000538) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_3_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000053c) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_3_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000053c) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_3_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000053c) +#define HWIO_IPA_UC_RX_HND_CMDQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000540) +#define HWIO_IPA_UC_RX_HND_CMDQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000540) +#define HWIO_IPA_UC_RX_HND_CMDQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000540) +#define HWIO_IPA_RAM_HW_FIRST_ADDR (IPA_DEBUG_REG_BASE + 0x0000054c) +#define HWIO_IPA_RAM_HW_FIRST_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000054c) +#define HWIO_IPA_RAM_HW_FIRST_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000054c) +#define HWIO_IPA_RAM_HW_LAST_ADDR (IPA_DEBUG_REG_BASE + 0x00000550) +#define HWIO_IPA_RAM_HW_LAST_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000550) +#define HWIO_IPA_RAM_HW_LAST_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000550) +#define HWIO_IPA_RAM_SNIFFER_BASE_OFFSET_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000554) +#define HWIO_IPA_RAM_SNIFFER_BASE_OFFSET_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000554) +#define HWIO_IPA_RAM_SNIFFER_BASE_OFFSET_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000554) +#define HWIO_IPA_RAM_FRAG_FRST_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000558) +#define HWIO_IPA_RAM_FRAG_FRST_BASE_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000558) +#define HWIO_IPA_RAM_FRAG_FRST_BASE_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000558) +#define HWIO_IPA_RAM_FRAG_SCND_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000055c) +#define HWIO_IPA_RAM_FRAG_SCND_BASE_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000055c) +#define HWIO_IPA_RAM_FRAG_SCND_BASE_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000055c) +#define HWIO_IPA_RAM_GSI_TLV_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000560) +#define HWIO_IPA_RAM_GSI_TLV_BASE_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000560) +#define HWIO_IPA_RAM_GSI_TLV_BASE_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000560) +#define HWIO_IPA_RAM_DCPH_KEYS_FIRST_ADDR (IPA_DEBUG_REG_BASE + 0x00000564) +#define HWIO_IPA_RAM_DCPH_KEYS_FIRST_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000564) +#define HWIO_IPA_RAM_DCPH_KEYS_FIRST_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000564) +#define HWIO_IPA_RAM_DCPH_KEYS_LAST_ADDR (IPA_DEBUG_REG_BASE + 0x00000568) +#define HWIO_IPA_RAM_DCPH_KEYS_LAST_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000568) +#define HWIO_IPA_RAM_DCPH_KEYS_LAST_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000568) +#define HWIO_IPA_DPS_SEQUENCER_FIRST_ADDR (IPA_DEBUG_REG_BASE + 0x00000570) +#define HWIO_IPA_DPS_SEQUENCER_FIRST_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000570) +#define HWIO_IPA_DPS_SEQUENCER_FIRST_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000570) +#define HWIO_IPA_DPS_SEQUENCER_LAST_ADDR (IPA_DEBUG_REG_BASE + 0x00000574) +#define HWIO_IPA_DPS_SEQUENCER_LAST_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000574) +#define HWIO_IPA_DPS_SEQUENCER_LAST_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000574) +#define HWIO_IPA_HPS_SEQUENCER_FIRST_ADDR (IPA_DEBUG_REG_BASE + 0x00000578) +#define HWIO_IPA_HPS_SEQUENCER_FIRST_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000578) +#define HWIO_IPA_HPS_SEQUENCER_FIRST_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000578) +#define HWIO_IPA_HPS_SEQUENCER_LAST_ADDR (IPA_DEBUG_REG_BASE + 0x0000057c) +#define HWIO_IPA_HPS_SEQUENCER_LAST_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000057c) +#define HWIO_IPA_HPS_SEQUENCER_LAST_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000057c) +#define HWIO_IPA_RAM_PKT_CTX_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000650) +#define HWIO_IPA_RAM_PKT_CTX_BASE_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000650) +#define HWIO_IPA_RAM_PKT_CTX_BASE_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000650) +#define HWIO_IPA_RAM_SW_AREA_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000654) +#define HWIO_IPA_RAM_SW_AREA_BASE_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000654) +#define HWIO_IPA_RAM_SW_AREA_BASE_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000654) +#define HWIO_IPA_RAM_HDRI_TYPE1_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000658) +#define HWIO_IPA_RAM_HDRI_TYPE1_BASE_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000658) +#define HWIO_IPA_RAM_HDRI_TYPE1_BASE_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000658) +#define HWIO_IPA_RAM_AGGR_NLO_COUNTERS_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE \ + + 0x0000065c) +#define HWIO_IPA_RAM_AGGR_NLO_COUNTERS_BASE_ADDR_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x0000065c) +#define HWIO_IPA_RAM_AGGR_NLO_COUNTERS_BASE_ADDR_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x0000065c) +#define HWIO_IPA_RAM_NLO_VP_CACHE_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000660) +#define HWIO_IPA_RAM_NLO_VP_CACHE_BASE_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000660) +#define HWIO_IPA_RAM_NLO_VP_CACHE_BASE_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000660) +#define HWIO_IPA_RAM_COAL_VP_CACHE_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000664) +#define HWIO_IPA_RAM_COAL_VP_CACHE_BASE_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000664) +#define HWIO_IPA_RAM_COAL_VP_CACHE_BASE_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000664) +#define HWIO_IPA_RAM_COAL_VP_FIFO_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000668) +#define HWIO_IPA_RAM_COAL_VP_FIFO_BASE_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000668) +#define HWIO_IPA_RAM_COAL_VP_FIFO_BASE_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000668) +#define HWIO_IPA_RAM_GSI_IF_CONS_ACCUMS_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE \ + + 0x0000066c) +#define HWIO_IPA_RAM_GSI_IF_CONS_ACCUMS_BASE_ADDR_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x0000066c) +#define HWIO_IPA_RAM_GSI_IF_CONS_ACCUMS_BASE_ADDR_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x0000066c) +#define HWIO_IPA_RAM_AGGR_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE + 0x00000670) +#define HWIO_IPA_RAM_AGGR_BASE_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000670) +#define HWIO_IPA_RAM_AGGR_BASE_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000670) +#define HWIO_IPA_RAM_TX_COUNTERS_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000674) +#define HWIO_IPA_RAM_TX_COUNTERS_BASE_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000674) +#define HWIO_IPA_RAM_TX_COUNTERS_BASE_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000674) +#define HWIO_IPA_RAM_DPL_FIFO_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000678) +#define HWIO_IPA_RAM_DPL_FIFO_BASE_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000678) +#define HWIO_IPA_RAM_DPL_FIFO_BASE_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000678) +#define HWIO_IPA_RAM_COAL_MASTER_VP_CTX_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE \ + + 0x0000067c) +#define HWIO_IPA_RAM_COAL_MASTER_VP_CTX_BASE_ADDR_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x0000067c) +#define HWIO_IPA_RAM_COAL_MASTER_VP_CTX_BASE_ADDR_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x0000067c) +#define HWIO_IPA_RAM_COAL_MASTER_VP_AGGR_BASE_ADDR_ADDR ( \ + IPA_DEBUG_REG_BASE + 0x00000680) +#define HWIO_IPA_RAM_COAL_MASTER_VP_AGGR_BASE_ADDR_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000680) +#define HWIO_IPA_RAM_COAL_MASTER_VP_AGGR_BASE_ADDR_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000680) +#define HWIO_IPA_RAM_COAL_SLAVE_VP_CTX_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE \ + + 0x00000684) +#define HWIO_IPA_RAM_COAL_SLAVE_VP_CTX_BASE_ADDR_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000684) +#define HWIO_IPA_RAM_COAL_SLAVE_VP_CTX_BASE_ADDR_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000684) +#define HWIO_IPA_RAM_UL_NLO_AGGR_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000688) +#define HWIO_IPA_RAM_UL_NLO_AGGR_BASE_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000688) +#define HWIO_IPA_RAM_UL_NLO_AGGR_BASE_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000688) +#define HWIO_IPA_RAM_UC_IRAM_ADDR_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000069c) +#define HWIO_IPA_RAM_UC_IRAM_ADDR_BASE_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x0000069c) +#define HWIO_IPA_RAM_UC_IRAM_ADDR_BASE_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x0000069c) +#define HWIO_IPA_HPS_UC2SEQ_PUSH_ADDR (IPA_DEBUG_REG_BASE + 0x00000580) +#define HWIO_IPA_HPS_UC2SEQ_PUSH_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000580) +#define HWIO_IPA_HPS_UC2SEQ_PUSH_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000580) +#define HWIO_IPA_HPS_UC2SEQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x00000584) +#define HWIO_IPA_HPS_UC2SEQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000584) +#define HWIO_IPA_HPS_UC2SEQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000584) +#define HWIO_IPA_HPS_SEQ2UC_RD_ADDR (IPA_DEBUG_REG_BASE + 0x00000588) +#define HWIO_IPA_HPS_SEQ2UC_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000588) +#define HWIO_IPA_HPS_SEQ2UC_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000588) +#define HWIO_IPA_HPS_SEQ2UC_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x0000058c) +#define HWIO_IPA_HPS_SEQ2UC_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000058c) +#define HWIO_IPA_HPS_SEQ2UC_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000058c) +#define HWIO_IPA_HPS_SEQ2UC_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x00000590) +#define HWIO_IPA_HPS_SEQ2UC_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000590) +#define HWIO_IPA_HPS_SEQ2UC_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000590) +#define HWIO_IPA_DPS_UC2SEQ_PUSH_ADDR (IPA_DEBUG_REG_BASE + 0x00000594) +#define HWIO_IPA_DPS_UC2SEQ_PUSH_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000594) +#define HWIO_IPA_DPS_UC2SEQ_PUSH_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000594) +#define HWIO_IPA_DPS_UC2SEQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x00000598) +#define HWIO_IPA_DPS_UC2SEQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000598) +#define HWIO_IPA_DPS_UC2SEQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000598) +#define HWIO_IPA_DPS_SEQ2UC_RD_ADDR (IPA_DEBUG_REG_BASE + 0x0000059c) +#define HWIO_IPA_DPS_SEQ2UC_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000059c) +#define HWIO_IPA_DPS_SEQ2UC_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000059c) +#define HWIO_IPA_DPS_SEQ2UC_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x000005a0) +#define HWIO_IPA_DPS_SEQ2UC_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000005a0) +#define HWIO_IPA_DPS_SEQ2UC_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000005a0) +#define HWIO_IPA_DPS_SEQ2UC_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x000005a4) +#define HWIO_IPA_DPS_SEQ2UC_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000005a4) +#define HWIO_IPA_DPS_SEQ2UC_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000005a4) +#define HWIO_IPA_NTF_TX_CMDQ_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x00000600) +#define HWIO_IPA_NTF_TX_CMDQ_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000600) +#define HWIO_IPA_NTF_TX_CMDQ_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000600) +#define HWIO_IPA_NTF_TX_CMDQ_CMD_RMSK 0xff +#define HWIO_IPA_NTF_TX_CMDQ_CMD_ATTR 0x3 +#define HWIO_IPA_NTF_TX_CMDQ_CMD_IN in_dword_masked( \ + HWIO_IPA_NTF_TX_CMDQ_CMD_ADDR, \ + HWIO_IPA_NTF_TX_CMDQ_CMD_RMSK) +#define HWIO_IPA_NTF_TX_CMDQ_CMD_INM(m) in_dword_masked( \ + HWIO_IPA_NTF_TX_CMDQ_CMD_ADDR, \ + m) +#define HWIO_IPA_NTF_TX_CMDQ_CMD_OUT(v) out_dword( \ + HWIO_IPA_NTF_TX_CMDQ_CMD_ADDR, \ + v) +#define HWIO_IPA_NTF_TX_CMDQ_CMD_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_NTF_TX_CMDQ_CMD_ADDR, \ + m, \ + v, \ + HWIO_IPA_NTF_TX_CMDQ_CMD_IN) +#define HWIO_IPA_NTF_TX_CMDQ_CMD_RD_REQ_BMSK 0x80 +#define HWIO_IPA_NTF_TX_CMDQ_CMD_RD_REQ_SHFT 0x7 +#define HWIO_IPA_NTF_TX_CMDQ_CMD_CMD_CLIENT_BMSK 0x7c +#define HWIO_IPA_NTF_TX_CMDQ_CMD_CMD_CLIENT_SHFT 0x2 +#define HWIO_IPA_NTF_TX_CMDQ_CMD_POP_CMD_BMSK 0x2 +#define HWIO_IPA_NTF_TX_CMDQ_CMD_POP_CMD_SHFT 0x1 +#define HWIO_IPA_NTF_TX_CMDQ_CMD_WRITE_CMD_BMSK 0x1 +#define HWIO_IPA_NTF_TX_CMDQ_CMD_WRITE_CMD_SHFT 0x0 +#define HWIO_IPA_NTF_TX_CMDQ_RELEASE_WR_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000604) +#define HWIO_IPA_NTF_TX_CMDQ_RELEASE_WR_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000604) +#define HWIO_IPA_NTF_TX_CMDQ_RELEASE_WR_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000604) +#define HWIO_IPA_NTF_TX_CMDQ_RELEASE_RD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000608) +#define HWIO_IPA_NTF_TX_CMDQ_RELEASE_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000608) +#define HWIO_IPA_NTF_TX_CMDQ_RELEASE_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000608) +#define HWIO_IPA_NTF_TX_CMDQ_CFG_WR_ADDR (IPA_DEBUG_REG_BASE + 0x0000060c) +#define HWIO_IPA_NTF_TX_CMDQ_CFG_WR_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000060c) +#define HWIO_IPA_NTF_TX_CMDQ_CFG_WR_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000060c) +#define HWIO_IPA_NTF_TX_CMDQ_CFG_RD_ADDR (IPA_DEBUG_REG_BASE + 0x00000610) +#define HWIO_IPA_NTF_TX_CMDQ_CFG_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000610) +#define HWIO_IPA_NTF_TX_CMDQ_CFG_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000610) +#define HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000614) +#define HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000614) +#define HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000614) +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000618) +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000618) +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000618) +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_RMSK 0xfffff +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_ATTR 0x1 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_IN in_dword_masked( \ + HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_ADDR, \ + HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_RMSK) +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_INM(m) in_dword_masked( \ + HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_ADDR, \ + m) +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_CMDQ_REP_F_BMSK 0x80000 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_CMDQ_REP_F_SHFT 0x13 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_CMDQ_OPCODE_F_BMSK 0x60000 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_CMDQ_OPCODE_F_SHFT 0x11 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_CMDQ_SRC_PIPE_F_BMSK 0x1f000 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_CMDQ_SRC_PIPE_F_SHFT 0xc +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_CMDQ_SRC_ID_F_BMSK 0xff0 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_CMDQ_SRC_ID_F_SHFT 0x4 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_CMDQ_CTX_ID_F_BMSK 0xf +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_CMDQ_CTX_ID_F_SHFT 0x0 +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x0000061c) +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000061c) +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000061c) +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_RMSK 0x1ff +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_ATTR 0x1 +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_IN in_dword_masked( \ + HWIO_IPA_NTF_TX_CMDQ_STATUS_ADDR, \ + HWIO_IPA_NTF_TX_CMDQ_STATUS_RMSK) +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_INM(m) in_dword_masked( \ + HWIO_IPA_NTF_TX_CMDQ_STATUS_ADDR, \ + m) +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_CMDQ_DEPTH_BMSK 0x1fc +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_CMDQ_DEPTH_SHFT 0x2 +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_CMDQ_FULL_BMSK 0x2 +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_CMDQ_FULL_SHFT 0x1 +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_STATUS_BMSK 0x1 +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_STATUS_SHFT 0x0 +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_EMPTY_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000620) +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_EMPTY_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000620) +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_EMPTY_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000620) +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_EMPTY_RMSK 0x7fffffff +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_EMPTY_ATTR 0x1 +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_EMPTY_IN in_dword_masked( \ + HWIO_IPA_NTF_TX_CMDQ_STATUS_EMPTY_ADDR, \ + HWIO_IPA_NTF_TX_CMDQ_STATUS_EMPTY_RMSK) +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_EMPTY_INM(m) in_dword_masked( \ + HWIO_IPA_NTF_TX_CMDQ_STATUS_EMPTY_ADDR, \ + m) +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_EMPTY_CMDQ_EMPTY_BMSK 0x7fffffff +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_EMPTY_CMDQ_EMPTY_SHFT 0x0 +#define HWIO_IPA_NTF_TX_SNP_ADDR (IPA_DEBUG_REG_BASE + 0x00000624) +#define HWIO_IPA_NTF_TX_SNP_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000624) +#define HWIO_IPA_NTF_TX_SNP_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000624) +#define HWIO_IPA_NTF_TX_CMDQ_COUNT_ADDR (IPA_DEBUG_REG_BASE + 0x00000628) +#define HWIO_IPA_NTF_TX_CMDQ_COUNT_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000628) +#define HWIO_IPA_NTF_TX_CMDQ_COUNT_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000628) +#define HWIO_IPA_NTF_TX_CMDQ_COUNT_RMSK 0x7f +#define HWIO_IPA_NTF_TX_CMDQ_COUNT_ATTR 0x1 +#define HWIO_IPA_NTF_TX_CMDQ_COUNT_IN in_dword_masked( \ + HWIO_IPA_NTF_TX_CMDQ_COUNT_ADDR, \ + HWIO_IPA_NTF_TX_CMDQ_COUNT_RMSK) +#define HWIO_IPA_NTF_TX_CMDQ_COUNT_INM(m) in_dword_masked( \ + HWIO_IPA_NTF_TX_CMDQ_COUNT_ADDR, \ + m) +#define HWIO_IPA_NTF_TX_CMDQ_COUNT_FIFO_COUNT_BMSK 0x7f +#define HWIO_IPA_NTF_TX_CMDQ_COUNT_FIFO_COUNT_SHFT 0x0 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000700) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000700) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000700) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_RMSK 0xff +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_ATTR 0x3 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_IN in_dword_masked( \ + HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_ADDR, \ + HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_RMSK) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_INM(m) in_dword_masked( \ + HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_ADDR, \ + m) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_OUT(v) out_dword( \ + HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_ADDR, \ + v) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_ADDR, \ + m, \ + v, \ + HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_IN) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_RD_REQ_BMSK 0x80 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_RD_REQ_SHFT 0x7 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_CMD_CLIENT_BMSK 0x7c +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_CMD_CLIENT_SHFT 0x2 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_POP_CMD_BMSK 0x2 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_POP_CMD_SHFT 0x1 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_WRITE_CMD_BMSK 0x1 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_WRITE_CMD_SHFT 0x0 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_RELEASE_WR_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000704) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_RELEASE_WR_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000704) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_RELEASE_WR_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000704) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_RELEASE_RD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000708) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_RELEASE_RD_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000708) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_RELEASE_RD_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000708) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CFG_WR_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000070c) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CFG_WR_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000070c) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CFG_WR_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000070c) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CFG_RD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000710) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CFG_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000710) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CFG_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000710) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_WR_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000714) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_WR_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000714) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_WR_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000714) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000718) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000718) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000718) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_RMSK 0xffffffff +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_ATTR 0x3 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_IN in_dword_masked( \ + HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_ADDR, \ + HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_RMSK) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_INM(m) in_dword_masked( \ + HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_ADDR, \ + m) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_OUT(v) out_dword( \ + HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_ADDR, \ + v) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_ADDR, \ + m, \ + v, \ + HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_IN) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_CMDQ_USERDATA_BMSK 0xf8000000 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_CMDQ_USERDATA_SHFT 0x1b +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_CMDQ_SRC_ID_VALID_BMSK \ + 0x4000000 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_CMDQ_SRC_ID_VALID_SHFT 0x1a +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_CMDQ_SENT_BMSK 0x2000000 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_CMDQ_SENT_SHFT 0x19 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_CMDQ_ORIGIN_BMSK 0x1000000 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_CMDQ_ORIGIN_SHFT 0x18 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_CMDQ_LENGTH_BMSK 0xffff00 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_CMDQ_LENGTH_SHFT 0x8 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_CMDQ_SRC_ID_BMSK 0xff +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_CMDQ_SRC_ID_SHFT 0x0 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000071c) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000071c) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000071c) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_RMSK 0x1ff +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_ATTR 0x1 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_IN in_dword_masked( \ + HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_ADDR, \ + HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_RMSK) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_INM(m) in_dword_masked( \ + HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_ADDR, \ + m) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_CMDQ_DEPTH_BMSK 0x1fc +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_CMDQ_DEPTH_SHFT 0x2 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_CMDQ_FULL_BMSK 0x2 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_CMDQ_FULL_SHFT 0x1 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_STATUS_BMSK 0x1 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_STATUS_SHFT 0x0 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000720) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000720) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000720) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_RMSK 0x7fffffff +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_ATTR 0x1 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_IN in_dword_masked( \ + HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_ADDR, \ + HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_RMSK) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_INM(m) in_dword_masked( \ + HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_ADDR, \ + m) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_CMDQ_EMPTY_BMSK 0x7fffffff +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_CMDQ_EMPTY_SHFT 0x0 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000724) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000724) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000724) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_RMSK 0x7f +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_ATTR 0x1 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_IN in_dword_masked( \ + HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_ADDR, \ + HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_RMSK) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_INM(m) in_dword_masked( \ + HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_ADDR, \ + m) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_FIFO_COUNT_BMSK 0x7f +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_FIFO_COUNT_SHFT 0x0 +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_0_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000728) +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000728) +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000728) +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_1_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000072c) +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_1_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000072c) +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_1_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000072c) +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_2_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000730) +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_2_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000730) +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_2_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000730) +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_3_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000734) +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_3_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000734) +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_3_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000734) +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_4_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000738) +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_4_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000738) +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_4_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000738) +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_5_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000073c) +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_5_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000073c) +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_5_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000073c) +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_6_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000740) +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_6_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000740) +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_6_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000740) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000744) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_CFG_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000744) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_CFG_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000744) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKUPD_CFG_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000748) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKUPD_CFG_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000748) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKUPD_CFG_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000748) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_CMD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000074c) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000074c) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000074c) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_STATUS_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000750) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000750) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000750) +#define HWIO_IPA_PROD_ACKMNGR_CONTROL_CFG_0_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000754) +#define HWIO_IPA_PROD_ACKMNGR_CONTROL_CFG_0_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000754) +#define HWIO_IPA_PROD_ACKMNGR_CONTROL_CFG_0_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000754) +#define HWIO_IPA_PROD_ACKMNGR_CONTROL_CFG_1_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000758) +#define HWIO_IPA_PROD_ACKMNGR_CONTROL_CFG_1_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000758) +#define HWIO_IPA_PROD_ACKMNGR_CONTROL_CFG_1_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000758) +#define HWIO_IPA_PROD_ACKMNGR_CONTROL_CFG_2_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000075c) +#define HWIO_IPA_PROD_ACKMNGR_CONTROL_CFG_2_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x0000075c) +#define HWIO_IPA_PROD_ACKMNGR_CONTROL_CFG_2_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x0000075c) +#define HWIO_IPA_PROD_ACKMNGR_CONTROL_CFG_3_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000760) +#define HWIO_IPA_PROD_ACKMNGR_CONTROL_CFG_3_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000760) +#define HWIO_IPA_PROD_ACKMNGR_CONTROL_CFG_3_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000760) +#define HWIO_IPA_PROD_ACKMNGR_CONTROL_CFG_4_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000764) +#define HWIO_IPA_PROD_ACKMNGR_CONTROL_CFG_4_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000764) +#define HWIO_IPA_PROD_ACKMNGR_CONTROL_CFG_4_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000764) +#define HWIO_IPA_PROD_ACKMNGR_CONTROL_CFG_5_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000768) +#define HWIO_IPA_PROD_ACKMNGR_CONTROL_CFG_5_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000768) +#define HWIO_IPA_PROD_ACKMNGR_CONTROL_CFG_5_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000768) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ADDR ( \ + IPA_DEBUG_REG_BASE + 0x0000076c) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x0000076c) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x0000076c) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKUPD_CFG_ADDR ( \ + IPA_DEBUG_REG_BASE + 0x00000770) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKUPD_CFG_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000770) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKUPD_CFG_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000770) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_CMD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000774) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000774) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000774) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_STATUS_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000778) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_STATUS_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000778) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_STATUS_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000778) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG1_ADDR ( \ + IPA_DEBUG_REG_BASE + 0x0000077c) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG1_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x0000077c) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG1_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x0000077c) +#define HWIO_IPA_SPARE_REG_1_ADDR (IPA_DEBUG_REG_BASE + 0x00000780) +#define HWIO_IPA_SPARE_REG_1_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000780) +#define HWIO_IPA_SPARE_REG_1_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000780) +#define HWIO_IPA_SPARE_REG_1_RMSK 0xffffffff +#define HWIO_IPA_SPARE_REG_1_ATTR 0x3 +#define HWIO_IPA_SPARE_REG_1_IN in_dword_masked(HWIO_IPA_SPARE_REG_1_ADDR, \ + HWIO_IPA_SPARE_REG_1_RMSK) +#define HWIO_IPA_SPARE_REG_1_INM(m) in_dword_masked( \ + HWIO_IPA_SPARE_REG_1_ADDR, \ + m) +#define HWIO_IPA_SPARE_REG_1_OUT(v) out_dword(HWIO_IPA_SPARE_REG_1_ADDR, v) +#define HWIO_IPA_SPARE_REG_1_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_SPARE_REG_1_ADDR, \ + m, \ + v, \ + HWIO_IPA_SPARE_REG_1_IN) +#define HWIO_IPA_SPARE_REG_1_SPARE_BIT31_BMSK 0x80000000 +#define HWIO_IPA_SPARE_REG_1_SPARE_BIT31_SHFT 0x1f +#define HWIO_IPA_SPARE_REG_1_SPARE_BIT30_BMSK 0x40000000 +#define HWIO_IPA_SPARE_REG_1_SPARE_BIT30_SHFT 0x1e +#define HWIO_IPA_SPARE_REG_1_SPARE_ACKINJ_PIPE8_MASK_ENABLE_BMSK \ + 0x20000000 +#define HWIO_IPA_SPARE_REG_1_SPARE_ACKINJ_PIPE8_MASK_ENABLE_SHFT 0x1d +#define \ + HWIO_IPA_SPARE_REG_1_WARB_FORCE_ARB_ROUND_FINISH_SPECIAL_DISABLE_BMSK \ + 0x10000000 +#define \ + HWIO_IPA_SPARE_REG_1_WARB_FORCE_ARB_ROUND_FINISH_SPECIAL_DISABLE_SHFT \ + 0x1c +#define HWIO_IPA_SPARE_REG_1_DCPH_RAM_RD_PREFETCH_DISABLE_BMSK 0x8000000 +#define HWIO_IPA_SPARE_REG_1_DCPH_RAM_RD_PREFETCH_DISABLE_SHFT 0x1b +#define HWIO_IPA_SPARE_REG_1_RAM_SLAVEWAY_ACCESS_PROTECTION_DISABLE_BMSK \ + 0x4000000 +#define HWIO_IPA_SPARE_REG_1_RAM_SLAVEWAY_ACCESS_PROTECTION_DISABLE_SHFT \ + 0x1a +#define HWIO_IPA_SPARE_REG_1_SPARE_BIT25_BMSK 0x2000000 +#define HWIO_IPA_SPARE_REG_1_SPARE_BIT25_SHFT 0x19 +#define HWIO_IPA_SPARE_REG_1_SPARE_BIT24_BMSK 0x1000000 +#define HWIO_IPA_SPARE_REG_1_SPARE_BIT24_SHFT 0x18 +#define HWIO_IPA_SPARE_REG_1_SPARE_BIT23_BMSK 0x800000 +#define HWIO_IPA_SPARE_REG_1_SPARE_BIT23_SHFT 0x17 +#define HWIO_IPA_SPARE_REG_1_BAM_IDLE_IN_IPA_MISC_CGC_EN_BMSK 0x400000 +#define HWIO_IPA_SPARE_REG_1_BAM_IDLE_IN_IPA_MISC_CGC_EN_SHFT 0x16 +#define HWIO_IPA_SPARE_REG_1_GSI_IF_OUT_OF_BUF_STOP_RESET_MASK_ENABLE_BMSK \ + 0x200000 +#define HWIO_IPA_SPARE_REG_1_GSI_IF_OUT_OF_BUF_STOP_RESET_MASK_ENABLE_SHFT \ + 0x15 +#define HWIO_IPA_SPARE_REG_1_REVERT_WARB_FIX_BMSK 0x100000 +#define HWIO_IPA_SPARE_REG_1_REVERT_WARB_FIX_SHFT 0x14 +#define HWIO_IPA_SPARE_REG_1_SPARE_BIT19_BMSK 0x80000 +#define HWIO_IPA_SPARE_REG_1_SPARE_BIT19_SHFT 0x13 +#define HWIO_IPA_SPARE_REG_1_RX_STALL_ON_GEN_DEAGGR_ERROR_BMSK 0x40000 +#define HWIO_IPA_SPARE_REG_1_RX_STALL_ON_GEN_DEAGGR_ERROR_SHFT 0x12 +#define HWIO_IPA_SPARE_REG_1_RX_STALL_ON_MBIM_DEAGGR_ERROR_BMSK 0x20000 +#define HWIO_IPA_SPARE_REG_1_RX_STALL_ON_MBIM_DEAGGR_ERROR_SHFT 0x11 +#define HWIO_IPA_SPARE_REG_1_QMB_RAM_RD_CACHE_DISABLE_BMSK 0x10000 +#define HWIO_IPA_SPARE_REG_1_QMB_RAM_RD_CACHE_DISABLE_SHFT 0x10 +#define \ + HWIO_IPA_SPARE_REG_1_RX_CMDQ_SPLITTER_CMDQ_PENDING_MUX_DISABLE_BMSK \ + 0x8000 +#define \ + HWIO_IPA_SPARE_REG_1_RX_CMDQ_SPLITTER_CMDQ_PENDING_MUX_DISABLE_SHFT \ + 0xf +#define \ + HWIO_IPA_SPARE_REG_1_FRAG_MNGR_FAIRNESS_EVICTION_ON_CONSTRUCTING_BMSK \ + 0x4000 +#define \ + HWIO_IPA_SPARE_REG_1_FRAG_MNGR_FAIRNESS_EVICTION_ON_CONSTRUCTING_SHFT \ + 0xe +#define HWIO_IPA_SPARE_REG_1_TX_BLOCK_AGGR_QUERY_ON_HOLB_PACKET_BMSK \ + 0x2000 +#define HWIO_IPA_SPARE_REG_1_TX_BLOCK_AGGR_QUERY_ON_HOLB_PACKET_SHFT 0xd +#define HWIO_IPA_SPARE_REG_1_SPARE_BIT12_BMSK 0x1000 +#define HWIO_IPA_SPARE_REG_1_SPARE_BIT12_SHFT 0xc +#define HWIO_IPA_SPARE_REG_1_TX_GIVES_SSPND_ACK_ON_OPEN_AGGR_FRAME_BMSK \ + 0x800 +#define HWIO_IPA_SPARE_REG_1_TX_GIVES_SSPND_ACK_ON_OPEN_AGGR_FRAME_SHFT \ + 0xb +#define HWIO_IPA_SPARE_REG_1_ACL_DISPATCHER_PKT_CHECK_DISABLE_BMSK 0x400 +#define HWIO_IPA_SPARE_REG_1_ACL_DISPATCHER_PKT_CHECK_DISABLE_SHFT 0xa +#define HWIO_IPA_SPARE_REG_1_SPARE_BIT8_BMSK 0x100 +#define HWIO_IPA_SPARE_REG_1_SPARE_BIT8_SHFT 0x8 +#define HWIO_IPA_SPARE_REG_1_ACL_DISPATCHER_FRAG_NOTIF_CHECK_DISABLE_BMSK \ + 0x40 +#define HWIO_IPA_SPARE_REG_1_ACL_DISPATCHER_FRAG_NOTIF_CHECK_DISABLE_SHFT \ + 0x6 +#define HWIO_IPA_SPARE_REG_1_ACL_INORDER_MULTI_DISABLE_BMSK 0x20 +#define HWIO_IPA_SPARE_REG_1_ACL_INORDER_MULTI_DISABLE_SHFT 0x5 +#define HWIO_IPA_SPARE_REG_1_SPARE_BIT4_BMSK 0x10 +#define HWIO_IPA_SPARE_REG_1_SPARE_BIT4_SHFT 0x4 +#define HWIO_IPA_SPARE_REG_1_SPARE_BIT3_BMSK 0x8 +#define HWIO_IPA_SPARE_REG_1_SPARE_BIT3_SHFT 0x3 +#define HWIO_IPA_SPARE_REG_1_GENQMB_AOOOWR_BMSK 0x4 +#define HWIO_IPA_SPARE_REG_1_GENQMB_AOOOWR_SHFT 0x2 +#define HWIO_IPA_SPARE_REG_1_SPARE_BIT1_BMSK 0x2 +#define HWIO_IPA_SPARE_REG_1_SPARE_BIT1_SHFT 0x1 +#define HWIO_IPA_SPARE_REG_1_SPARE_BIT0_BMSK 0x1 +#define HWIO_IPA_SPARE_REG_1_SPARE_BIT0_SHFT 0x0 +#define HWIO_IPA_SPARE_REG_2_ADDR (IPA_DEBUG_REG_BASE + 0x00000784) +#define HWIO_IPA_SPARE_REG_2_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000784) +#define HWIO_IPA_SPARE_REG_2_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000784) +#define HWIO_IPA_SPARE_REG_2_RMSK 0xffffffff +#define HWIO_IPA_SPARE_REG_2_ATTR 0x3 +#define HWIO_IPA_SPARE_REG_2_IN in_dword_masked(HWIO_IPA_SPARE_REG_2_ADDR, \ + HWIO_IPA_SPARE_REG_2_RMSK) +#define HWIO_IPA_SPARE_REG_2_INM(m) in_dword_masked( \ + HWIO_IPA_SPARE_REG_2_ADDR, \ + m) +#define HWIO_IPA_SPARE_REG_2_OUT(v) out_dword(HWIO_IPA_SPARE_REG_2_ADDR, v) +#define HWIO_IPA_SPARE_REG_2_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_SPARE_REG_2_ADDR, \ + m, \ + v, \ + HWIO_IPA_SPARE_REG_2_IN) +#define HWIO_IPA_SPARE_REG_2_SPARE_BITS_BMSK 0xfffffffc +#define HWIO_IPA_SPARE_REG_2_SPARE_BITS_SHFT 0x2 +#define \ + HWIO_IPA_SPARE_REG_2_CMDQ_SPLIT_NOT_WAIT_DATA_DESC_PRIOR_HDR_PUSH_BMSK \ + 0x2 +#define \ + HWIO_IPA_SPARE_REG_2_CMDQ_SPLIT_NOT_WAIT_DATA_DESC_PRIOR_HDR_PUSH_SHFT \ + 0x1 +#define HWIO_IPA_SPARE_REG_2_TX_BRESP_INJ_WITH_FLOP_BMSK 0x1 +#define HWIO_IPA_SPARE_REG_2_TX_BRESP_INJ_WITH_FLOP_SHFT 0x0 +#define HWIO_IPA_ENDP_GSI_CFG1_n_ADDR(n) (IPA_DEBUG_REG_BASE + \ + 0x00000794 + 0x4 * (n)) +#define HWIO_IPA_ENDP_GSI_CFG1_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000794 + 0x4 * (n)) +#define HWIO_IPA_ENDP_GSI_CFG1_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000794 + 0x4 * (n)) +#define HWIO_IPA_ENDP_GSI_CFG1_n_RMSK 0x80010000 +#define HWIO_IPA_ENDP_GSI_CFG1_n_MAXn 30 +#define HWIO_IPA_ENDP_GSI_CFG1_n_ATTR 0x3 +#define HWIO_IPA_ENDP_GSI_CFG1_n_INI(n) in_dword_masked( \ + HWIO_IPA_ENDP_GSI_CFG1_n_ADDR(n), \ + HWIO_IPA_ENDP_GSI_CFG1_n_RMSK) +#define HWIO_IPA_ENDP_GSI_CFG1_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_ENDP_GSI_CFG1_n_ADDR(n), \ + mask) +#define HWIO_IPA_ENDP_GSI_CFG1_n_OUTI(n, val) out_dword( \ + HWIO_IPA_ENDP_GSI_CFG1_n_ADDR(n), \ + val) +#define HWIO_IPA_ENDP_GSI_CFG1_n_OUTMI(n, mask, val) out_dword_masked_ns( \ + HWIO_IPA_ENDP_GSI_CFG1_n_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_ENDP_GSI_CFG1_n_INI(n)) +#define HWIO_IPA_ENDP_GSI_CFG1_n_INIT_ENDP_BMSK 0x80000000 +#define HWIO_IPA_ENDP_GSI_CFG1_n_INIT_ENDP_SHFT 0x1f +#define HWIO_IPA_ENDP_GSI_CFG1_n_ENDP_EN_BMSK 0x10000 +#define HWIO_IPA_ENDP_GSI_CFG1_n_ENDP_EN_SHFT 0x10 +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_1_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000908) +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_1_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000908) +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_1_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000908) +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_2_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000090c) +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_2_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x0000090c) +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_2_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x0000090c) +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_3_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000910) +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_3_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000910) +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_3_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000910) +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_CTRL_ADDR ( \ + IPA_DEBUG_REG_BASE + 0x00000914) +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_CTRL_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000914) +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_CTRL_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000914) +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_RDY_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000918) +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_RDY_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000918) +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_RDY_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000918) +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_DATA_1_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000091c) +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_DATA_1_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000091c) +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_DATA_1_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000091c) +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_DATA_2_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000920) +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_DATA_2_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000920) +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_DATA_2_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000920) +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_ADDR(n) (IPA_DEBUG_REG_BASE + \ + 0x00000924 + 0x4 * (n)) +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000924 + 0x4 * (n)) +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000924 + 0x4 * (n)) +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_RMSK 0xffffff +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_MAXn 30 +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_ATTR 0x3 +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_INI(n) in_dword_masked( \ + HWIO_IPA_ENDP_GSI_CFG_TLV_n_ADDR(n), \ + HWIO_IPA_ENDP_GSI_CFG_TLV_n_RMSK) +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_ENDP_GSI_CFG_TLV_n_ADDR(n), \ + mask) +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_OUTI(n, val) out_dword( \ + HWIO_IPA_ENDP_GSI_CFG_TLV_n_ADDR(n), \ + val) +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_OUTMI(n, mask, \ + val) out_dword_masked_ns( \ + HWIO_IPA_ENDP_GSI_CFG_TLV_n_ADDR( \ + n), \ + mask, \ + val, \ + HWIO_IPA_ENDP_GSI_CFG_TLV_n_INI(n)) +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_FIFO_SIZE_BMSK 0xff0000 +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_FIFO_SIZE_SHFT 0x10 +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_FIFO_BASE_ADDR_BMSK 0xffff +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_FIFO_BASE_ADDR_SHFT 0x0 +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_ADDR(n) (IPA_DEBUG_REG_BASE + \ + 0x000009a8 + 0x4 * (n)) +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000009a8 + 0x4 * (n)) +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000009a8 + 0x4 * (n)) +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_RMSK 0xffffff +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_MAXn 30 +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_ATTR 0x3 +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_INI(n) in_dword_masked( \ + HWIO_IPA_ENDP_GSI_CFG_AOS_n_ADDR(n), \ + HWIO_IPA_ENDP_GSI_CFG_AOS_n_RMSK) +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_ENDP_GSI_CFG_AOS_n_ADDR(n), \ + mask) +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_OUTI(n, val) out_dword( \ + HWIO_IPA_ENDP_GSI_CFG_AOS_n_ADDR(n), \ + val) +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_OUTMI(n, mask, \ + val) out_dword_masked_ns( \ + HWIO_IPA_ENDP_GSI_CFG_AOS_n_ADDR( \ + n), \ + mask, \ + val, \ + HWIO_IPA_ENDP_GSI_CFG_AOS_n_INI(n)) +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_FIFO_SIZE_BMSK 0xff0000 +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_FIFO_SIZE_SHFT 0x10 +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_FIFO_BASE_ADDR_BMSK 0xffff +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_FIFO_BASE_ADDR_SHFT 0x0 +#define HWIO_IPA_COAL_VP_AOS_FIFO_n_ADDR(n) (IPA_DEBUG_REG_BASE + \ + 0x00000a60 + 0x4 * (n)) +#define HWIO_IPA_COAL_VP_AOS_FIFO_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000a60 + 0x4 * (n)) +#define HWIO_IPA_COAL_VP_AOS_FIFO_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000a60 + 0x4 * (n)) +#define HWIO_IPA_CTXH_CTRL_ADDR (IPA_DEBUG_REG_BASE + 0x00000afc) +#define HWIO_IPA_CTXH_CTRL_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000afc) +#define HWIO_IPA_CTXH_CTRL_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000afc) +#define HWIO_IPA_CTXH_CTRL_RMSK 0x8000000f +#define HWIO_IPA_CTXH_CTRL_ATTR 0x3 +#define HWIO_IPA_CTXH_CTRL_IN in_dword_masked(HWIO_IPA_CTXH_CTRL_ADDR, \ + HWIO_IPA_CTXH_CTRL_RMSK) +#define HWIO_IPA_CTXH_CTRL_INM(m) in_dword_masked(HWIO_IPA_CTXH_CTRL_ADDR, \ + m) +#define HWIO_IPA_CTXH_CTRL_OUT(v) out_dword(HWIO_IPA_CTXH_CTRL_ADDR, v) +#define HWIO_IPA_CTXH_CTRL_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_CTXH_CTRL_ADDR, \ + m, \ + v, \ + HWIO_IPA_CTXH_CTRL_IN) +#define HWIO_IPA_CTXH_CTRL_CTXH_LOCK_BMSK 0x80000000 +#define HWIO_IPA_CTXH_CTRL_CTXH_LOCK_SHFT 0x1f +#define HWIO_IPA_CTXH_CTRL_CTXH_LOCK_ID_BMSK 0xf +#define HWIO_IPA_CTXH_CTRL_CTXH_LOCK_ID_SHFT 0x0 +#define HWIO_IPA_CTX_ID_m_CTX_NUM_n_ADDR(m, n) (IPA_DEBUG_REG_BASE + \ + 0x00000b00 + 0x80 * (m) + \ + 0x4 * (n)) +#define HWIO_IPA_CTX_ID_m_CTX_NUM_n_PHYS(m, n) (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000b00 + 0x80 * (m) + \ + 0x4 * (n)) +#define HWIO_IPA_CTX_ID_m_CTX_NUM_n_OFFS(m, n) (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000b00 + 0x80 * (m) + \ + 0x4 * (n)) +#define IPA_EE_REG_BASE (IPA_0_IPA_WRAPPER_BASE + 0x00043000) +#define IPA_EE_REG_BASE_PHYS (IPA_0_IPA_WRAPPER_BASE_PHYS + 0x00043000) +#define IPA_EE_REG_BASE_OFFS 0x00043000 +#define HWIO_IPA_IRQ_STTS_EE_n_ADDR(n) (IPA_EE_REG_BASE + 0x00000008 + \ + 0x1000 * (n)) +#define HWIO_IPA_IRQ_STTS_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + \ + 0x00000008 + 0x1000 * (n)) +#define HWIO_IPA_IRQ_STTS_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + \ + 0x00000008 + 0x1000 * (n)) +#define HWIO_IPA_IRQ_EN_EE_n_ADDR(n) (IPA_EE_REG_BASE + 0x0000000c + \ + 0x1000 * (n)) +#define HWIO_IPA_IRQ_EN_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + 0x0000000c + \ + 0x1000 * (n)) +#define HWIO_IPA_IRQ_EN_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + 0x0000000c + \ + 0x1000 * (n)) +#define HWIO_IPA_IRQ_EN_EE_n_RMSK 0x7bffffd +#define HWIO_IPA_IRQ_EN_EE_n_MAXn 3 +#define HWIO_IPA_IRQ_EN_EE_n_ATTR 0x3 +#define HWIO_IPA_IRQ_EN_EE_n_INI(n) in_dword_masked( \ + HWIO_IPA_IRQ_EN_EE_n_ADDR(n), \ + HWIO_IPA_IRQ_EN_EE_n_RMSK) +#define HWIO_IPA_IRQ_EN_EE_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_IRQ_EN_EE_n_ADDR(n), \ + mask) +#define HWIO_IPA_IRQ_EN_EE_n_OUTI(n, val) out_dword( \ + HWIO_IPA_IRQ_EN_EE_n_ADDR(n), \ + val) +#define HWIO_IPA_IRQ_EN_EE_n_OUTMI(n, mask, val) out_dword_masked_ns( \ + HWIO_IPA_IRQ_EN_EE_n_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_IRQ_EN_EE_n_INI(n)) +#define HWIO_IPA_IRQ_EN_EE_n_TLV_LEN_MIN_DSM_IRQ_EN_BMSK 0x4000000 +#define HWIO_IPA_IRQ_EN_EE_n_TLV_LEN_MIN_DSM_IRQ_EN_SHFT 0x1a +#define HWIO_IPA_IRQ_EN_EE_n_GSI_UC_IRQ_EN_BMSK 0x2000000 +#define HWIO_IPA_IRQ_EN_EE_n_GSI_UC_IRQ_EN_SHFT 0x19 +#define HWIO_IPA_IRQ_EN_EE_n_GSI_IPA_IF_TLV_RCVD_IRQ_EN_BMSK 0x1000000 +#define HWIO_IPA_IRQ_EN_EE_n_GSI_IPA_IF_TLV_RCVD_IRQ_EN_SHFT 0x18 +#define HWIO_IPA_IRQ_EN_EE_n_GSI_EE_IRQ_EN_BMSK 0x800000 +#define HWIO_IPA_IRQ_EN_EE_n_GSI_EE_IRQ_EN_SHFT 0x17 +#define HWIO_IPA_IRQ_EN_EE_n_UCP_IRQ_EN_BMSK 0x200000 +#define HWIO_IPA_IRQ_EN_EE_n_UCP_IRQ_EN_SHFT 0x15 +#define HWIO_IPA_IRQ_EN_EE_n_PIPE_RED_MARKER_ABOVE_IRQ_EN_BMSK 0x100000 +#define HWIO_IPA_IRQ_EN_EE_n_PIPE_RED_MARKER_ABOVE_IRQ_EN_SHFT 0x14 +#define HWIO_IPA_IRQ_EN_EE_n_PIPE_YELLOW_MARKER_ABOVE_IRQ_EN_BMSK 0x80000 +#define HWIO_IPA_IRQ_EN_EE_n_PIPE_YELLOW_MARKER_ABOVE_IRQ_EN_SHFT 0x13 +#define HWIO_IPA_IRQ_EN_EE_n_PIPE_RED_MARKER_BELOW_IRQ_EN_BMSK 0x40000 +#define HWIO_IPA_IRQ_EN_EE_n_PIPE_RED_MARKER_BELOW_IRQ_EN_SHFT 0x12 +#define HWIO_IPA_IRQ_EN_EE_n_PIPE_YELLOW_MARKER_BELOW_IRQ_EN_BMSK 0x20000 +#define HWIO_IPA_IRQ_EN_EE_n_PIPE_YELLOW_MARKER_BELOW_IRQ_EN_SHFT 0x11 +#define HWIO_IPA_IRQ_EN_EE_n_BAM_GSI_IDLE_IRQ_EN_BMSK 0x10000 +#define HWIO_IPA_IRQ_EN_EE_n_BAM_GSI_IDLE_IRQ_EN_SHFT 0x10 +#define HWIO_IPA_IRQ_EN_EE_n_TX_HOLB_DROP_IRQ_EN_BMSK 0x8000 +#define HWIO_IPA_IRQ_EN_EE_n_TX_HOLB_DROP_IRQ_EN_SHFT 0xf +#define HWIO_IPA_IRQ_EN_EE_n_TX_SUSPEND_IRQ_EN_BMSK 0x4000 +#define HWIO_IPA_IRQ_EN_EE_n_TX_SUSPEND_IRQ_EN_SHFT 0xe +#define HWIO_IPA_IRQ_EN_EE_n_PROC_ERR_IRQ_EN_BMSK 0x2000 +#define HWIO_IPA_IRQ_EN_EE_n_PROC_ERR_IRQ_EN_SHFT 0xd +#define HWIO_IPA_IRQ_EN_EE_n_STEP_MODE_IRQ_EN_BMSK 0x1000 +#define HWIO_IPA_IRQ_EN_EE_n_STEP_MODE_IRQ_EN_SHFT 0xc +#define HWIO_IPA_IRQ_EN_EE_n_TX_ERR_IRQ_EN_BMSK 0x800 +#define HWIO_IPA_IRQ_EN_EE_n_TX_ERR_IRQ_EN_SHFT 0xb +#define HWIO_IPA_IRQ_EN_EE_n_DEAGGR_ERR_IRQ_EN_BMSK 0x400 +#define HWIO_IPA_IRQ_EN_EE_n_DEAGGR_ERR_IRQ_EN_SHFT 0xa +#define HWIO_IPA_IRQ_EN_EE_n_RX_ERR_IRQ_EN_BMSK 0x200 +#define HWIO_IPA_IRQ_EN_EE_n_RX_ERR_IRQ_EN_SHFT 0x9 +#define HWIO_IPA_IRQ_EN_EE_n_PROC_TO_UC_ACK_Q_NOT_EMPTY_IRQ_EN_BMSK 0x100 +#define HWIO_IPA_IRQ_EN_EE_n_PROC_TO_UC_ACK_Q_NOT_EMPTY_IRQ_EN_SHFT 0x8 +#define HWIO_IPA_IRQ_EN_EE_n_UC_RX_CMD_Q_NOT_FULL_IRQ_EN_BMSK 0x80 +#define HWIO_IPA_IRQ_EN_EE_n_UC_RX_CMD_Q_NOT_FULL_IRQ_EN_SHFT 0x7 +#define HWIO_IPA_IRQ_EN_EE_n_UC_IN_Q_NOT_EMPTY_IRQ_EN_BMSK 0x40 +#define HWIO_IPA_IRQ_EN_EE_n_UC_IN_Q_NOT_EMPTY_IRQ_EN_SHFT 0x6 +#define HWIO_IPA_IRQ_EN_EE_n_UC_IRQ_3_IRQ_EN_BMSK 0x20 +#define HWIO_IPA_IRQ_EN_EE_n_UC_IRQ_3_IRQ_EN_SHFT 0x5 +#define HWIO_IPA_IRQ_EN_EE_n_UC_IRQ_2_IRQ_EN_BMSK 0x10 +#define HWIO_IPA_IRQ_EN_EE_n_UC_IRQ_2_IRQ_EN_SHFT 0x4 +#define HWIO_IPA_IRQ_EN_EE_n_UC_IRQ_1_IRQ_EN_BMSK 0x8 +#define HWIO_IPA_IRQ_EN_EE_n_UC_IRQ_1_IRQ_EN_SHFT 0x3 +#define HWIO_IPA_IRQ_EN_EE_n_UC_IRQ_0_IRQ_EN_BMSK 0x4 +#define HWIO_IPA_IRQ_EN_EE_n_UC_IRQ_0_IRQ_EN_SHFT 0x2 +#define HWIO_IPA_IRQ_EN_EE_n_BAD_SNOC_ACCESS_IRQ_EN_BMSK 0x1 +#define HWIO_IPA_IRQ_EN_EE_n_BAD_SNOC_ACCESS_IRQ_EN_SHFT 0x0 +#define HWIO_IPA_IRQ_CLR_EE_n_ADDR(n) (IPA_EE_REG_BASE + 0x00000010 + \ + 0x1000 * (n)) +#define HWIO_IPA_IRQ_CLR_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + 0x00000010 + \ + 0x1000 * (n)) +#define HWIO_IPA_IRQ_CLR_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + 0x00000010 + \ + 0x1000 * (n)) +#define HWIO_IPA_SNOC_FEC_EE_n_ADDR(n) (IPA_EE_REG_BASE + 0x00000018 + \ + 0x1000 * (n)) +#define HWIO_IPA_SNOC_FEC_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + \ + 0x00000018 + 0x1000 * (n)) +#define HWIO_IPA_SNOC_FEC_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + \ + 0x00000018 + 0x1000 * (n)) +#define HWIO_IPA_SNOC_FEC_EE_n_RMSK 0x8000f1ff +#define HWIO_IPA_SNOC_FEC_EE_n_MAXn 3 +#define HWIO_IPA_SNOC_FEC_EE_n_ATTR 0x1 +#define HWIO_IPA_SNOC_FEC_EE_n_INI(n) in_dword_masked( \ + HWIO_IPA_SNOC_FEC_EE_n_ADDR(n), \ + HWIO_IPA_SNOC_FEC_EE_n_RMSK) +#define HWIO_IPA_SNOC_FEC_EE_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_SNOC_FEC_EE_n_ADDR(n), \ + mask) +#define HWIO_IPA_SNOC_FEC_EE_n_READ_NOT_WRITE_BMSK 0x80000000 +#define HWIO_IPA_SNOC_FEC_EE_n_READ_NOT_WRITE_SHFT 0x1f +#define HWIO_IPA_SNOC_FEC_EE_n_TID_BMSK 0xf000 +#define HWIO_IPA_SNOC_FEC_EE_n_TID_SHFT 0xc +#define HWIO_IPA_SNOC_FEC_EE_n_QMB_INDEX_BMSK 0x100 +#define HWIO_IPA_SNOC_FEC_EE_n_QMB_INDEX_SHFT 0x8 +#define HWIO_IPA_SNOC_FEC_EE_n_CLIENT_BMSK 0xff +#define HWIO_IPA_SNOC_FEC_EE_n_CLIENT_SHFT 0x0 +#define HWIO_IPA_IRQ_EE_UC_n_ADDR(n) (IPA_EE_REG_BASE + 0x0000001c + \ + 0x1000 * (n)) +#define HWIO_IPA_IRQ_EE_UC_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + 0x0000001c + \ + 0x1000 * (n)) +#define HWIO_IPA_IRQ_EE_UC_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + 0x0000001c + \ + 0x1000 * (n)) +#define HWIO_IPA_FEC_ADDR_EE_n_ADDR(n) (IPA_EE_REG_BASE + 0x00000020 + \ + 0x1000 * (n)) +#define HWIO_IPA_FEC_ADDR_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + \ + 0x00000020 + 0x1000 * (n)) +#define HWIO_IPA_FEC_ADDR_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + \ + 0x00000020 + 0x1000 * (n)) +#define HWIO_IPA_FEC_ADDR_EE_n_RMSK 0xffffffff +#define HWIO_IPA_FEC_ADDR_EE_n_MAXn 3 +#define HWIO_IPA_FEC_ADDR_EE_n_ATTR 0x1 +#define HWIO_IPA_FEC_ADDR_EE_n_INI(n) in_dword_masked( \ + HWIO_IPA_FEC_ADDR_EE_n_ADDR(n), \ + HWIO_IPA_FEC_ADDR_EE_n_RMSK) +#define HWIO_IPA_FEC_ADDR_EE_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_FEC_ADDR_EE_n_ADDR(n), \ + mask) +#define HWIO_IPA_FEC_ADDR_EE_n_ADDR_BMSK 0xffffffff +#define HWIO_IPA_FEC_ADDR_EE_n_ADDR_SHFT 0x0 +#define HWIO_IPA_FEC_ADDR_MSB_EE_n_ADDR(n) (IPA_EE_REG_BASE + 0x00000024 + \ + 0x1000 * (n)) +#define HWIO_IPA_FEC_ADDR_MSB_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + \ + 0x00000024 + 0x1000 * (n)) +#define HWIO_IPA_FEC_ADDR_MSB_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + \ + 0x00000024 + 0x1000 * (n)) +#define HWIO_IPA_FEC_ATTR_EE_n_ADDR(n) (IPA_EE_REG_BASE + 0x00000028 + \ + 0x1000 * (n)) +#define HWIO_IPA_FEC_ATTR_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + \ + 0x00000028 + 0x1000 * (n)) +#define HWIO_IPA_FEC_ATTR_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + \ + 0x00000028 + 0x1000 * (n)) +#define HWIO_IPA_FEC_ATTR_EE_n_RMSK 0xffffffff +#define HWIO_IPA_FEC_ATTR_EE_n_MAXn 3 +#define HWIO_IPA_FEC_ATTR_EE_n_ATTR 0x1 +#define HWIO_IPA_FEC_ATTR_EE_n_INI(n) in_dword_masked( \ + HWIO_IPA_FEC_ATTR_EE_n_ADDR(n), \ + HWIO_IPA_FEC_ATTR_EE_n_RMSK) +#define HWIO_IPA_FEC_ATTR_EE_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_FEC_ATTR_EE_n_ADDR(n), \ + mask) +#define HWIO_IPA_FEC_ATTR_EE_n_ERROR_INFO_BMSK 0xffffffc0 +#define HWIO_IPA_FEC_ATTR_EE_n_ERROR_INFO_SHFT 0x6 +#define HWIO_IPA_FEC_ATTR_EE_n_OPCODE_BMSK 0x3f +#define HWIO_IPA_FEC_ATTR_EE_n_OPCODE_SHFT 0x0 +#define HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_ADDR(n) (IPA_EE_REG_BASE + \ + 0x00000030 + 0x1000 * (n)) +#define HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + \ + 0x00000030 + 0x1000 * (n)) +#define HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + \ + 0x00000030 + 0x1000 * (n)) +#define HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_RMSK 0x7fffffff +#define HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_MAXn 3 +#define HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_ATTR 0x1 +#define HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_INI(n) in_dword_masked( \ + HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_ADDR(n), \ + HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_RMSK) +#define HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_ADDR(n), \ + mask) +#define HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_ENDPOINTS_BMSK 0x7fffffff +#define HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_ENDPOINTS_SHFT 0x0 +#define HWIO_IPA_SUSPEND_IRQ_EN_EE_n_ADDR(n) (IPA_EE_REG_BASE + \ + 0x00000034 + 0x1000 * (n)) +#define HWIO_IPA_SUSPEND_IRQ_EN_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + \ + 0x00000034 + 0x1000 * (n)) +#define HWIO_IPA_SUSPEND_IRQ_EN_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + \ + 0x00000034 + 0x1000 * (n)) +#define HWIO_IPA_SUSPEND_IRQ_EN_EE_n_RMSK 0x7fffffff +#define HWIO_IPA_SUSPEND_IRQ_EN_EE_n_MAXn 3 +#define HWIO_IPA_SUSPEND_IRQ_EN_EE_n_ATTR 0x3 +#define HWIO_IPA_SUSPEND_IRQ_EN_EE_n_INI(n) in_dword_masked( \ + HWIO_IPA_SUSPEND_IRQ_EN_EE_n_ADDR(n), \ + HWIO_IPA_SUSPEND_IRQ_EN_EE_n_RMSK) +#define HWIO_IPA_SUSPEND_IRQ_EN_EE_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_SUSPEND_IRQ_EN_EE_n_ADDR(n), \ + mask) +#define HWIO_IPA_SUSPEND_IRQ_EN_EE_n_OUTI(n, val) out_dword( \ + HWIO_IPA_SUSPEND_IRQ_EN_EE_n_ADDR(n), \ + val) +#define HWIO_IPA_SUSPEND_IRQ_EN_EE_n_OUTMI(n, mask, \ + val) out_dword_masked_ns( \ + HWIO_IPA_SUSPEND_IRQ_EN_EE_n_ADDR( \ + n), \ + mask, \ + val, \ + HWIO_IPA_SUSPEND_IRQ_EN_EE_n_INI(n)) +#define HWIO_IPA_SUSPEND_IRQ_EN_EE_n_ENDPOINTS_BMSK 0x7fffffff +#define HWIO_IPA_SUSPEND_IRQ_EN_EE_n_ENDPOINTS_SHFT 0x0 +#define HWIO_IPA_SUSPEND_IRQ_CLR_EE_n_ADDR(n) (IPA_EE_REG_BASE + \ + 0x00000038 + 0x1000 * (n)) +#define HWIO_IPA_SUSPEND_IRQ_CLR_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + \ + 0x00000038 + 0x1000 * (n)) +#define HWIO_IPA_SUSPEND_IRQ_CLR_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + \ + 0x00000038 + 0x1000 * (n)) +#define HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_ADDR(n) (IPA_EE_REG_BASE + \ + 0x0000003c + 0x1000 * (n)) +#define HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + \ + 0x0000003c + 0x1000 * (n)) +#define HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + \ + 0x0000003c + 0x1000 * (n)) +#define HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_RMSK 0x7fffe000 +#define HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_MAXn 3 +#define HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_ATTR 0x1 +#define HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_INI(n) in_dword_masked( \ + HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_ADDR(n), \ + HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_RMSK) +#define HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_ADDR(n), \ + mask) +#define HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_ENDPOINTS_BMSK 0x7fffe000 +#define HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_ENDPOINTS_SHFT 0xd +#define HWIO_IPA_HOLB_DROP_IRQ_EN_EE_n_ADDR(n) (IPA_EE_REG_BASE + \ + 0x00000040 + 0x1000 * (n)) +#define HWIO_IPA_HOLB_DROP_IRQ_EN_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + \ + 0x00000040 + 0x1000 * (n)) +#define HWIO_IPA_HOLB_DROP_IRQ_EN_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + \ + 0x00000040 + 0x1000 * (n)) +#define HWIO_IPA_HOLB_DROP_IRQ_CLR_EE_n_ADDR(n) (IPA_EE_REG_BASE + \ + 0x00000044 + 0x1000 * (n)) +#define HWIO_IPA_HOLB_DROP_IRQ_CLR_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + \ + 0x00000044 + 0x1000 * (n)) +#define HWIO_IPA_HOLB_DROP_IRQ_CLR_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + \ + 0x00000044 + 0x1000 * (n)) +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_ADDR (IPA_EE_REG_BASE + 0x000010a0) +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_PHYS (IPA_EE_REG_BASE_PHYS + \ + 0x000010a0) +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_OFFS (IPA_EE_REG_BASE_OFFS + \ + 0x000010a0) +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_STATUS_ADDR_ADDR, \ + HWIO_IPA_LOG_BUF_STATUS_ADDR_RMSK) +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_STATUS_ADDR_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_STATUS_ADDR_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_STATUS_ADDR_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_STATUS_ADDR_IN) +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_START_ADDR_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_START_ADDR_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_MSB_ADDR (IPA_EE_REG_BASE + \ + 0x000010a4) +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_MSB_PHYS (IPA_EE_REG_BASE_PHYS + \ + 0x000010a4) +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_MSB_OFFS (IPA_EE_REG_BASE_OFFS + \ + 0x000010a4) +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_MSB_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_MSB_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_MSB_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_STATUS_ADDR_MSB_ADDR, \ + HWIO_IPA_LOG_BUF_STATUS_ADDR_MSB_RMSK) +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_MSB_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_STATUS_ADDR_MSB_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_MSB_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_STATUS_ADDR_MSB_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_MSB_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_STATUS_ADDR_MSB_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_STATUS_ADDR_MSB_IN) +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_MSB_START_ADDR_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_MSB_START_ADDR_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_ADDR (IPA_EE_REG_BASE + \ + 0x000010a8) +#define HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_PHYS (IPA_EE_REG_BASE_PHYS + \ + 0x000010a8) +#define HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_OFFS (IPA_EE_REG_BASE_OFFS + \ + 0x000010a8) +#define HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_ATTR 0x1 +#define HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_ADDR, \ + HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_RMSK) +#define HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_WRITE_ADDR_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_WRITE_ADDR_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_MSB_ADDR (IPA_EE_REG_BASE + \ + 0x000010ac) +#define HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_MSB_PHYS (IPA_EE_REG_BASE_PHYS + \ + 0x000010ac) +#define HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_MSB_OFFS (IPA_EE_REG_BASE_OFFS + \ + 0x000010ac) +#define HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_MSB_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_MSB_ATTR 0x1 +#define HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_MSB_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_MSB_ADDR, \ + HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_MSB_RMSK) +#define HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_MSB_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_MSB_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_MSB_WRITE_ADDR_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_MSB_WRITE_ADDR_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_STATUS_CFG_ADDR (IPA_EE_REG_BASE + 0x000010b0) +#define HWIO_IPA_LOG_BUF_STATUS_CFG_PHYS (IPA_EE_REG_BASE_PHYS + \ + 0x000010b0) +#define HWIO_IPA_LOG_BUF_STATUS_CFG_OFFS (IPA_EE_REG_BASE_OFFS + \ + 0x000010b0) +#define HWIO_IPA_LOG_BUF_STATUS_CFG_RMSK 0x1ffff +#define HWIO_IPA_LOG_BUF_STATUS_CFG_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_STATUS_CFG_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_STATUS_CFG_ADDR, \ + HWIO_IPA_LOG_BUF_STATUS_CFG_RMSK) +#define HWIO_IPA_LOG_BUF_STATUS_CFG_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_STATUS_CFG_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_STATUS_CFG_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_STATUS_CFG_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_STATUS_CFG_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_STATUS_CFG_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_STATUS_CFG_IN) +#define HWIO_IPA_LOG_BUF_STATUS_CFG_ENABLE_BMSK 0x10000 +#define HWIO_IPA_LOG_BUF_STATUS_CFG_ENABLE_SHFT 0x10 +#define HWIO_IPA_LOG_BUF_STATUS_CFG_SIZE_BMSK 0xffff +#define HWIO_IPA_LOG_BUF_STATUS_CFG_SIZE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_STATUS_RAM_PTR_ADDR (IPA_EE_REG_BASE + 0x000010b4) +#define HWIO_IPA_LOG_BUF_STATUS_RAM_PTR_PHYS (IPA_EE_REG_BASE_PHYS + \ + 0x000010b4) +#define HWIO_IPA_LOG_BUF_STATUS_RAM_PTR_OFFS (IPA_EE_REG_BASE_OFFS + \ + 0x000010b4) +#define HWIO_IPA_LOG_BUF_STATUS_RAM_PTR_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_STATUS_RAM_PTR_ATTR 0x1 +#define HWIO_IPA_LOG_BUF_STATUS_RAM_PTR_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_STATUS_RAM_PTR_ADDR, \ + HWIO_IPA_LOG_BUF_STATUS_RAM_PTR_RMSK) +#define HWIO_IPA_LOG_BUF_STATUS_RAM_PTR_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_STATUS_RAM_PTR_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_STATUS_RAM_PTR_WRITE_PTR_BMSK 0xffff0000 +#define HWIO_IPA_LOG_BUF_STATUS_RAM_PTR_WRITE_PTR_SHFT 0x10 +#define HWIO_IPA_LOG_BUF_STATUS_RAM_PTR_READ_PTR_BMSK 0xffff +#define HWIO_IPA_LOG_BUF_STATUS_RAM_PTR_READ_PTR_SHFT 0x0 +#define HWIO_IPA_LTE_DECIPH_INIT_VALUES_0_ADDR (IPA_EE_REG_BASE + \ + 0x000010c0) +#define HWIO_IPA_LTE_DECIPH_INIT_VALUES_0_PHYS (IPA_EE_REG_BASE_PHYS + \ + 0x000010c0) +#define HWIO_IPA_LTE_DECIPH_INIT_VALUES_0_OFFS (IPA_EE_REG_BASE_OFFS + \ + 0x000010c0) +#define HWIO_IPA_LTE_DECIPH_INIT_VALUES_1_ADDR (IPA_EE_REG_BASE + \ + 0x000010c4) +#define HWIO_IPA_LTE_DECIPH_INIT_VALUES_1_PHYS (IPA_EE_REG_BASE_PHYS + \ + 0x000010c4) +#define HWIO_IPA_LTE_DECIPH_INIT_VALUES_1_OFFS (IPA_EE_REG_BASE_OFFS + \ + 0x000010c4) +#define HWIO_IPA_LTE_DECIPH_CONFIG_VALUES_0_ADDR (IPA_EE_REG_BASE + \ + 0x000010c8) +#define HWIO_IPA_LTE_DECIPH_CONFIG_VALUES_0_PHYS (IPA_EE_REG_BASE_PHYS + \ + 0x000010c8) +#define HWIO_IPA_LTE_DECIPH_CONFIG_VALUES_0_OFFS (IPA_EE_REG_BASE_OFFS + \ + 0x000010c8) +#define HWIO_IPA_LTE_DECIPH_CONFIG_VALUES_1_ADDR (IPA_EE_REG_BASE + \ + 0x000010cc) +#define HWIO_IPA_LTE_DECIPH_CONFIG_VALUES_1_PHYS (IPA_EE_REG_BASE_PHYS + \ + 0x000010cc) +#define HWIO_IPA_LTE_DECIPH_CONFIG_VALUES_1_OFFS (IPA_EE_REG_BASE_OFFS + \ + 0x000010cc) +#define HWIO_IPA_SECURED_PIPES_ADDR (IPA_EE_REG_BASE + 0x000010d0) +#define HWIO_IPA_SECURED_PIPES_PHYS (IPA_EE_REG_BASE_PHYS + 0x000010d0) +#define HWIO_IPA_SECURED_PIPES_OFFS (IPA_EE_REG_BASE_OFFS + 0x000010d0) +#define HWIO_IPA_LTE_DECIPH_INIT_VALUES_CFG_ADDR (IPA_EE_REG_BASE + \ + 0x000010d4) +#define HWIO_IPA_LTE_DECIPH_INIT_VALUES_CFG_PHYS (IPA_EE_REG_BASE_PHYS + \ + 0x000010d4) +#define HWIO_IPA_LTE_DECIPH_INIT_VALUES_CFG_OFFS (IPA_EE_REG_BASE_OFFS + \ + 0x000010d4) +#define HWIO_IPA_UC_REGS_INSIDE_IPA__CONTROL_ADDR (IPA_EE_REG_BASE + \ + 0x00001200) +#define HWIO_IPA_UC_REGS_INSIDE_IPA__CONTROL_PHYS (IPA_EE_REG_BASE_PHYS + \ + 0x00001200) +#define HWIO_IPA_UC_REGS_INSIDE_IPA__CONTROL_OFFS (IPA_EE_REG_BASE_OFFS + \ + 0x00001200) +#define HWIO_IPA_UC_REGS_INSIDE_IPA__NMI_ADDR (IPA_EE_REG_BASE + \ + 0x00001204) +#define HWIO_IPA_UC_REGS_INSIDE_IPA__NMI_PHYS (IPA_EE_REG_BASE_PHYS + \ + 0x00001204) +#define HWIO_IPA_UC_REGS_INSIDE_IPA__NMI_OFFS (IPA_EE_REG_BASE_OFFS + \ + 0x00001204) +#define HWIO_IPA_SET_UC_IRQ_EE_n_ADDR(n) (IPA_EE_REG_BASE + 0x00002048 + \ + 0x4 * (n)) +#define HWIO_IPA_SET_UC_IRQ_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + \ + 0x00002048 + 0x4 * (n)) +#define HWIO_IPA_SET_UC_IRQ_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + \ + 0x00002048 + 0x4 * (n)) +#define HWIO_IPA_SET_UC_IRQ_ALL_EES_ADDR (IPA_EE_REG_BASE + 0x00002058) +#define HWIO_IPA_SET_UC_IRQ_ALL_EES_PHYS (IPA_EE_REG_BASE_PHYS + \ + 0x00002058) +#define HWIO_IPA_SET_UC_IRQ_ALL_EES_OFFS (IPA_EE_REG_BASE_OFFS + \ + 0x00002058) +#define HWIO_IPA_UCP_RESUME_ADDR (IPA_EE_REG_BASE + 0x000030a0) +#define HWIO_IPA_UCP_RESUME_PHYS (IPA_EE_REG_BASE_PHYS + 0x000030a0) +#define HWIO_IPA_UCP_RESUME_OFFS (IPA_EE_REG_BASE_OFFS + 0x000030a0) +#define HWIO_IPA_PROC_UCP_CFG_ADDR (IPA_EE_REG_BASE + 0x000030a4) +#define HWIO_IPA_PROC_UCP_CFG_PHYS (IPA_EE_REG_BASE_PHYS + 0x000030a4) +#define HWIO_IPA_PROC_UCP_CFG_OFFS (IPA_EE_REG_BASE_OFFS + 0x000030a4) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_0_ADDR (IPA_EE_REG_BASE + \ + 0x000030a8) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_0_PHYS (IPA_EE_REG_BASE_PHYS + \ + 0x000030a8) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_0_OFFS (IPA_EE_REG_BASE_OFFS + \ + 0x000030a8) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_1_ADDR (IPA_EE_REG_BASE + \ + 0x000030ac) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_1_PHYS (IPA_EE_REG_BASE_PHYS + \ + 0x000030ac) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_1_OFFS (IPA_EE_REG_BASE_OFFS + \ + 0x000030ac) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_2_ADDR (IPA_EE_REG_BASE + \ + 0x000030b0) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_2_PHYS (IPA_EE_REG_BASE_PHYS + \ + 0x000030b0) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_2_OFFS (IPA_EE_REG_BASE_OFFS + \ + 0x000030b0) +#define IPA_UC_IPA_UC_PER_REG_BASE (IPA_0_IPA_WRAPPER_BASE + 0x000c0000) +#define IPA_UC_IPA_UC_PER_REG_BASE_PHYS (IPA_0_IPA_WRAPPER_BASE_PHYS + \ + 0x000c0000) +#define IPA_UC_IPA_UC_PER_REG_BASE_OFFS 0x000c0000 +#define HWIO_IPA_UC_STATUS_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000000) +#define HWIO_IPA_UC_STATUS_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000000) +#define HWIO_IPA_UC_STATUS_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000000) +#define HWIO_IPA_UC_CONTROL_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000004) +#define HWIO_IPA_UC_CONTROL_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000004) +#define HWIO_IPA_UC_CONTROL_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000004) +#define HWIO_IPA_UC_BASE_ADDR_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000008) +#define HWIO_IPA_UC_BASE_ADDR_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000008) +#define HWIO_IPA_UC_BASE_ADDR_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000008) +#define HWIO_IPA_UC_BASE_ADDR_MSB_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x0000000c) +#define HWIO_IPA_UC_BASE_ADDR_MSB_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x0000000c) +#define HWIO_IPA_UC_BASE_ADDR_MSB_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x0000000c) +#define HWIO_IPA_UC_SYS_BUS_ATTRIB_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000010) +#define HWIO_IPA_UC_SYS_BUS_ATTRIB_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000010) +#define HWIO_IPA_UC_SYS_BUS_ATTRIB_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000010) +#define HWIO_IPA_UC_PEND_IRQ_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000014) +#define HWIO_IPA_UC_PEND_IRQ_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000014) +#define HWIO_IPA_UC_PEND_IRQ_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000014) +#define HWIO_IPA_UC_TRACE_BUFFER_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000018) +#define HWIO_IPA_UC_TRACE_BUFFER_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000018) +#define HWIO_IPA_UC_TRACE_BUFFER_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000018) +#define HWIO_IPA_UC_PC_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x0000001c) +#define HWIO_IPA_UC_PC_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x0000001c) +#define HWIO_IPA_UC_PC_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x0000001c) +#define HWIO_IPA_UC_VUIC_INT_ADDRESS_LSB_ADDR (IPA_UC_IPA_UC_PER_REG_BASE \ + + 0x00000024) +#define HWIO_IPA_UC_VUIC_INT_ADDRESS_LSB_PHYS ( \ + IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000024) +#define HWIO_IPA_UC_VUIC_INT_ADDRESS_LSB_OFFS ( \ + IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000024) +#define HWIO_IPA_UC_VUIC_INT_ADDRESS_MSB_ADDR (IPA_UC_IPA_UC_PER_REG_BASE \ + + 0x00000028) +#define HWIO_IPA_UC_VUIC_INT_ADDRESS_MSB_PHYS ( \ + IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000028) +#define HWIO_IPA_UC_VUIC_INT_ADDRESS_MSB_OFFS ( \ + IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000028) +#define HWIO_IPA_UC_QMB_SYS_ADDR_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000100) +#define HWIO_IPA_UC_QMB_SYS_ADDR_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000100) +#define HWIO_IPA_UC_QMB_SYS_ADDR_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000100) +#define HWIO_IPA_UC_QMB_SYS_ADDR_RMSK 0xffffffff +#define HWIO_IPA_UC_QMB_SYS_ADDR_ATTR 0x3 +#define HWIO_IPA_UC_QMB_SYS_ADDR_IN in_dword_masked( \ + HWIO_IPA_UC_QMB_SYS_ADDR_ADDR, \ + HWIO_IPA_UC_QMB_SYS_ADDR_RMSK) +#define HWIO_IPA_UC_QMB_SYS_ADDR_INM(m) in_dword_masked( \ + HWIO_IPA_UC_QMB_SYS_ADDR_ADDR, \ + m) +#define HWIO_IPA_UC_QMB_SYS_ADDR_OUT(v) out_dword( \ + HWIO_IPA_UC_QMB_SYS_ADDR_ADDR, \ + v) +#define HWIO_IPA_UC_QMB_SYS_ADDR_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_UC_QMB_SYS_ADDR_ADDR, \ + m, \ + v, \ + HWIO_IPA_UC_QMB_SYS_ADDR_IN) +#define HWIO_IPA_UC_QMB_SYS_ADDR_ADDR_BMSK 0xffffffff +#define HWIO_IPA_UC_QMB_SYS_ADDR_ADDR_SHFT 0x0 +#define HWIO_IPA_UC_QMB_SYS_ADDR_MSB_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000104) +#define HWIO_IPA_UC_QMB_SYS_ADDR_MSB_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS \ + + 0x00000104) +#define HWIO_IPA_UC_QMB_SYS_ADDR_MSB_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS \ + + 0x00000104) +#define HWIO_IPA_UC_QMB_SYS_ADDR_MSB_RMSK 0xffffffff +#define HWIO_IPA_UC_QMB_SYS_ADDR_MSB_ATTR 0x3 +#define HWIO_IPA_UC_QMB_SYS_ADDR_MSB_IN in_dword_masked( \ + HWIO_IPA_UC_QMB_SYS_ADDR_MSB_ADDR, \ + HWIO_IPA_UC_QMB_SYS_ADDR_MSB_RMSK) +#define HWIO_IPA_UC_QMB_SYS_ADDR_MSB_INM(m) in_dword_masked( \ + HWIO_IPA_UC_QMB_SYS_ADDR_MSB_ADDR, \ + m) +#define HWIO_IPA_UC_QMB_SYS_ADDR_MSB_OUT(v) out_dword( \ + HWIO_IPA_UC_QMB_SYS_ADDR_MSB_ADDR, \ + v) +#define HWIO_IPA_UC_QMB_SYS_ADDR_MSB_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_UC_QMB_SYS_ADDR_MSB_ADDR, \ + m, \ + v, \ + HWIO_IPA_UC_QMB_SYS_ADDR_MSB_IN) +#define HWIO_IPA_UC_QMB_SYS_ADDR_MSB_ADDR_MSB_BMSK 0xffffffff +#define HWIO_IPA_UC_QMB_SYS_ADDR_MSB_ADDR_MSB_SHFT 0x0 +#define HWIO_IPA_UC_QMB_LOCAL_ADDR_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000108) +#define HWIO_IPA_UC_QMB_LOCAL_ADDR_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000108) +#define HWIO_IPA_UC_QMB_LOCAL_ADDR_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000108) +#define HWIO_IPA_UC_QMB_LOCAL_ADDR_RMSK 0x3ffff +#define HWIO_IPA_UC_QMB_LOCAL_ADDR_ATTR 0x3 +#define HWIO_IPA_UC_QMB_LOCAL_ADDR_IN in_dword_masked( \ + HWIO_IPA_UC_QMB_LOCAL_ADDR_ADDR, \ + HWIO_IPA_UC_QMB_LOCAL_ADDR_RMSK) +#define HWIO_IPA_UC_QMB_LOCAL_ADDR_INM(m) in_dword_masked( \ + HWIO_IPA_UC_QMB_LOCAL_ADDR_ADDR, \ + m) +#define HWIO_IPA_UC_QMB_LOCAL_ADDR_OUT(v) out_dword( \ + HWIO_IPA_UC_QMB_LOCAL_ADDR_ADDR, \ + v) +#define HWIO_IPA_UC_QMB_LOCAL_ADDR_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_UC_QMB_LOCAL_ADDR_ADDR, \ + m, \ + v, \ + HWIO_IPA_UC_QMB_LOCAL_ADDR_IN) +#define HWIO_IPA_UC_QMB_LOCAL_ADDR_ADDR_BMSK 0x3ffff +#define HWIO_IPA_UC_QMB_LOCAL_ADDR_ADDR_SHFT 0x0 +#define HWIO_IPA_UC_QMB_LENGTH_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x0000010c) +#define HWIO_IPA_UC_QMB_LENGTH_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x0000010c) +#define HWIO_IPA_UC_QMB_LENGTH_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x0000010c) +#define HWIO_IPA_UC_QMB_LENGTH_RMSK 0x7f +#define HWIO_IPA_UC_QMB_LENGTH_ATTR 0x3 +#define HWIO_IPA_UC_QMB_LENGTH_IN in_dword_masked( \ + HWIO_IPA_UC_QMB_LENGTH_ADDR, \ + HWIO_IPA_UC_QMB_LENGTH_RMSK) +#define HWIO_IPA_UC_QMB_LENGTH_INM(m) in_dword_masked( \ + HWIO_IPA_UC_QMB_LENGTH_ADDR, \ + m) +#define HWIO_IPA_UC_QMB_LENGTH_OUT(v) out_dword( \ + HWIO_IPA_UC_QMB_LENGTH_ADDR, \ + v) +#define HWIO_IPA_UC_QMB_LENGTH_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_UC_QMB_LENGTH_ADDR, \ + m, \ + v, \ + HWIO_IPA_UC_QMB_LENGTH_IN) +#define HWIO_IPA_UC_QMB_LENGTH_LENGTH_BMSK 0x7f +#define HWIO_IPA_UC_QMB_LENGTH_LENGTH_SHFT 0x0 +#define HWIO_IPA_UC_QMB_TRIGGER_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000110) +#define HWIO_IPA_UC_QMB_TRIGGER_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000110) +#define HWIO_IPA_UC_QMB_TRIGGER_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000110) +#define HWIO_IPA_UC_QMB_TRIGGER_RMSK 0x31 +#define HWIO_IPA_UC_QMB_TRIGGER_ATTR 0x3 +#define HWIO_IPA_UC_QMB_TRIGGER_IN in_dword_masked( \ + HWIO_IPA_UC_QMB_TRIGGER_ADDR, \ + HWIO_IPA_UC_QMB_TRIGGER_RMSK) +#define HWIO_IPA_UC_QMB_TRIGGER_INM(m) in_dword_masked( \ + HWIO_IPA_UC_QMB_TRIGGER_ADDR, \ + m) +#define HWIO_IPA_UC_QMB_TRIGGER_OUT(v) out_dword( \ + HWIO_IPA_UC_QMB_TRIGGER_ADDR, \ + v) +#define HWIO_IPA_UC_QMB_TRIGGER_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_UC_QMB_TRIGGER_ADDR, \ + m, \ + v, \ + HWIO_IPA_UC_QMB_TRIGGER_IN) +#define HWIO_IPA_UC_QMB_TRIGGER_POSTING_BMSK 0x30 +#define HWIO_IPA_UC_QMB_TRIGGER_POSTING_SHFT 0x4 +#define HWIO_IPA_UC_QMB_TRIGGER_POSTING_DATA_POSTED_FVAL 0x0 +#define HWIO_IPA_UC_QMB_TRIGGER_POSTING_RESP_POSTED_FVAL 0x1 +#define HWIO_IPA_UC_QMB_TRIGGER_POSTING_DATA_COMPLETE_FVAL 0x2 +#define HWIO_IPA_UC_QMB_TRIGGER_POSTING_RESP_COMPLETE_FVAL 0x3 +#define HWIO_IPA_UC_QMB_TRIGGER_DIRECTION_BMSK 0x1 +#define HWIO_IPA_UC_QMB_TRIGGER_DIRECTION_SHFT 0x0 +#define HWIO_IPA_UC_QMB_TRIGGER_DIRECTION_READ_FVAL 0x0 +#define HWIO_IPA_UC_QMB_TRIGGER_DIRECTION_WRITE_FVAL 0x1 +#define HWIO_IPA_UC_QMB_PENDING_TID_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000114) +#define HWIO_IPA_UC_QMB_PENDING_TID_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS \ + + 0x00000114) +#define HWIO_IPA_UC_QMB_PENDING_TID_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS \ + + 0x00000114) +#define HWIO_IPA_UC_QMB_PENDING_TID_RMSK 0x11113f +#define HWIO_IPA_UC_QMB_PENDING_TID_ATTR 0x1 +#define HWIO_IPA_UC_QMB_PENDING_TID_IN in_dword_masked( \ + HWIO_IPA_UC_QMB_PENDING_TID_ADDR, \ + HWIO_IPA_UC_QMB_PENDING_TID_RMSK) +#define HWIO_IPA_UC_QMB_PENDING_TID_INM(m) in_dword_masked( \ + HWIO_IPA_UC_QMB_PENDING_TID_ADDR, \ + m) +#define HWIO_IPA_UC_QMB_PENDING_TID_ERROR_SECURITY_BMSK 0x100000 +#define HWIO_IPA_UC_QMB_PENDING_TID_ERROR_SECURITY_SHFT 0x14 +#define HWIO_IPA_UC_QMB_PENDING_TID_ERROR_MAX_COMP_BMSK 0x10000 +#define HWIO_IPA_UC_QMB_PENDING_TID_ERROR_MAX_COMP_SHFT 0x10 +#define HWIO_IPA_UC_QMB_PENDING_TID_ERROR_MAX_OS_BMSK 0x1000 +#define HWIO_IPA_UC_QMB_PENDING_TID_ERROR_MAX_OS_SHFT 0xc +#define HWIO_IPA_UC_QMB_PENDING_TID_ERROR_BUS_BMSK 0x100 +#define HWIO_IPA_UC_QMB_PENDING_TID_ERROR_BUS_SHFT 0x8 +#define HWIO_IPA_UC_QMB_PENDING_TID_TID_BMSK 0x3f +#define HWIO_IPA_UC_QMB_PENDING_TID_TID_SHFT 0x0 +#define HWIO_IPA_UC_QMB_COMPLETED_RD_FIFO_ADDR (IPA_UC_IPA_UC_PER_REG_BASE \ + + 0x00000118) +#define HWIO_IPA_UC_QMB_COMPLETED_RD_FIFO_PHYS ( \ + IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000118) +#define HWIO_IPA_UC_QMB_COMPLETED_RD_FIFO_OFFS ( \ + IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000118) +#define HWIO_IPA_UC_QMB_COMPLETED_RD_FIFO_PEEK_ADDR ( \ + IPA_UC_IPA_UC_PER_REG_BASE + 0x0000011c) +#define HWIO_IPA_UC_QMB_COMPLETED_RD_FIFO_PEEK_PHYS ( \ + IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x0000011c) +#define HWIO_IPA_UC_QMB_COMPLETED_RD_FIFO_PEEK_OFFS ( \ + IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x0000011c) +#define HWIO_IPA_UC_QMB_COMPLETED_RD_FIFO_PEEK_RMSK 0x113f +#define HWIO_IPA_UC_QMB_COMPLETED_RD_FIFO_PEEK_ATTR 0x1 +#define HWIO_IPA_UC_QMB_COMPLETED_RD_FIFO_PEEK_IN in_dword_masked( \ + HWIO_IPA_UC_QMB_COMPLETED_RD_FIFO_PEEK_ADDR, \ + HWIO_IPA_UC_QMB_COMPLETED_RD_FIFO_PEEK_RMSK) +#define HWIO_IPA_UC_QMB_COMPLETED_RD_FIFO_PEEK_INM(m) in_dword_masked( \ + HWIO_IPA_UC_QMB_COMPLETED_RD_FIFO_PEEK_ADDR, \ + m) +#define HWIO_IPA_UC_QMB_COMPLETED_RD_FIFO_PEEK_VALID_BMSK 0x1000 +#define HWIO_IPA_UC_QMB_COMPLETED_RD_FIFO_PEEK_VALID_SHFT 0xc +#define HWIO_IPA_UC_QMB_COMPLETED_RD_FIFO_PEEK_ERROR_BMSK 0x100 +#define HWIO_IPA_UC_QMB_COMPLETED_RD_FIFO_PEEK_ERROR_SHFT 0x8 +#define HWIO_IPA_UC_QMB_COMPLETED_RD_FIFO_PEEK_TID_BMSK 0x3f +#define HWIO_IPA_UC_QMB_COMPLETED_RD_FIFO_PEEK_TID_SHFT 0x0 +#define HWIO_IPA_UC_QMB_COMPLETED_WR_FIFO_ADDR (IPA_UC_IPA_UC_PER_REG_BASE \ + + 0x00000120) +#define HWIO_IPA_UC_QMB_COMPLETED_WR_FIFO_PHYS ( \ + IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000120) +#define HWIO_IPA_UC_QMB_COMPLETED_WR_FIFO_OFFS ( \ + IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000120) +#define HWIO_IPA_UC_QMB_COMPLETED_WR_FIFO_PEEK_ADDR ( \ + IPA_UC_IPA_UC_PER_REG_BASE + 0x00000124) +#define HWIO_IPA_UC_QMB_COMPLETED_WR_FIFO_PEEK_PHYS ( \ + IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000124) +#define HWIO_IPA_UC_QMB_COMPLETED_WR_FIFO_PEEK_OFFS ( \ + IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000124) +#define HWIO_IPA_UC_QMB_COMPLETED_WR_FIFO_PEEK_RMSK 0x113f +#define HWIO_IPA_UC_QMB_COMPLETED_WR_FIFO_PEEK_ATTR 0x1 +#define HWIO_IPA_UC_QMB_COMPLETED_WR_FIFO_PEEK_IN in_dword_masked( \ + HWIO_IPA_UC_QMB_COMPLETED_WR_FIFO_PEEK_ADDR, \ + HWIO_IPA_UC_QMB_COMPLETED_WR_FIFO_PEEK_RMSK) +#define HWIO_IPA_UC_QMB_COMPLETED_WR_FIFO_PEEK_INM(m) in_dword_masked( \ + HWIO_IPA_UC_QMB_COMPLETED_WR_FIFO_PEEK_ADDR, \ + m) +#define HWIO_IPA_UC_QMB_COMPLETED_WR_FIFO_PEEK_VALID_BMSK 0x1000 +#define HWIO_IPA_UC_QMB_COMPLETED_WR_FIFO_PEEK_VALID_SHFT 0xc +#define HWIO_IPA_UC_QMB_COMPLETED_WR_FIFO_PEEK_ERROR_BMSK 0x100 +#define HWIO_IPA_UC_QMB_COMPLETED_WR_FIFO_PEEK_ERROR_SHFT 0x8 +#define HWIO_IPA_UC_QMB_COMPLETED_WR_FIFO_PEEK_TID_BMSK 0x3f +#define HWIO_IPA_UC_QMB_COMPLETED_WR_FIFO_PEEK_TID_SHFT 0x0 +#define HWIO_IPA_UC_QMB_MISC_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000128) +#define HWIO_IPA_UC_QMB_MISC_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000128) +#define HWIO_IPA_UC_QMB_MISC_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000128) +#define HWIO_IPA_UC_QMB_MISC_RMSK 0xf11333ff +#define HWIO_IPA_UC_QMB_MISC_ATTR 0x3 +#define HWIO_IPA_UC_QMB_MISC_IN in_dword_masked(HWIO_IPA_UC_QMB_MISC_ADDR, \ + HWIO_IPA_UC_QMB_MISC_RMSK) +#define HWIO_IPA_UC_QMB_MISC_INM(m) in_dword_masked( \ + HWIO_IPA_UC_QMB_MISC_ADDR, \ + m) +#define HWIO_IPA_UC_QMB_MISC_OUT(v) out_dword(HWIO_IPA_UC_QMB_MISC_ADDR, v) +#define HWIO_IPA_UC_QMB_MISC_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_UC_QMB_MISC_ADDR, \ + m, \ + v, \ + HWIO_IPA_UC_QMB_MISC_IN) +#define HWIO_IPA_UC_QMB_MISC_QMB_HREADY_BCR_BMSK 0x80000000 +#define HWIO_IPA_UC_QMB_MISC_QMB_HREADY_BCR_SHFT 0x1f +#define HWIO_IPA_UC_QMB_MISC_POSTED_STALL_BMSK 0x40000000 +#define HWIO_IPA_UC_QMB_MISC_POSTED_STALL_SHFT 0x1e +#define HWIO_IPA_UC_QMB_MISC_IRQ_COAL_BMSK 0x20000000 +#define HWIO_IPA_UC_QMB_MISC_IRQ_COAL_SHFT 0x1d +#define HWIO_IPA_UC_QMB_MISC_SWAP_BMSK 0x10000000 +#define HWIO_IPA_UC_QMB_MISC_SWAP_SHFT 0x1c +#define HWIO_IPA_UC_QMB_MISC_OOOWR_BMSK 0x1000000 +#define HWIO_IPA_UC_QMB_MISC_OOOWR_SHFT 0x18 +#define HWIO_IPA_UC_QMB_MISC_OOORD_BMSK 0x100000 +#define HWIO_IPA_UC_QMB_MISC_OOORD_SHFT 0x14 +#define HWIO_IPA_UC_QMB_MISC_WR_PRIORITY_BMSK 0x30000 +#define HWIO_IPA_UC_QMB_MISC_WR_PRIORITY_SHFT 0x10 +#define HWIO_IPA_UC_QMB_MISC_RD_PRIORITY_BMSK 0x3000 +#define HWIO_IPA_UC_QMB_MISC_RD_PRIORITY_SHFT 0xc +#define HWIO_IPA_UC_QMB_MISC_USER_BMSK 0x3ff +#define HWIO_IPA_UC_QMB_MISC_USER_SHFT 0x0 +#define HWIO_IPA_UC_QMB_STATUS_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x0000012c) +#define HWIO_IPA_UC_QMB_STATUS_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x0000012c) +#define HWIO_IPA_UC_QMB_STATUS_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x0000012c) +#define HWIO_IPA_UC_QMB_STATUS_RMSK 0x1fff1fff +#define HWIO_IPA_UC_QMB_STATUS_ATTR 0x1 +#define HWIO_IPA_UC_QMB_STATUS_IN in_dword_masked( \ + HWIO_IPA_UC_QMB_STATUS_ADDR, \ + HWIO_IPA_UC_QMB_STATUS_RMSK) +#define HWIO_IPA_UC_QMB_STATUS_INM(m) in_dword_masked( \ + HWIO_IPA_UC_QMB_STATUS_ADDR, \ + m) +#define HWIO_IPA_UC_QMB_STATUS_COMPLETED_WR_FIFO_FULL_BMSK 0x10000000 +#define HWIO_IPA_UC_QMB_STATUS_COMPLETED_WR_FIFO_FULL_SHFT 0x1c +#define HWIO_IPA_UC_QMB_STATUS_COMPLETED_WR_CNT_BMSK 0xf000000 +#define HWIO_IPA_UC_QMB_STATUS_COMPLETED_WR_CNT_SHFT 0x18 +#define HWIO_IPA_UC_QMB_STATUS_OUTSTANDING_WR_CNT_BMSK 0xf00000 +#define HWIO_IPA_UC_QMB_STATUS_OUTSTANDING_WR_CNT_SHFT 0x14 +#define HWIO_IPA_UC_QMB_STATUS_MAX_OUTSTANDING_WR_BMSK 0xf0000 +#define HWIO_IPA_UC_QMB_STATUS_MAX_OUTSTANDING_WR_SHFT 0x10 +#define HWIO_IPA_UC_QMB_STATUS_COMPLETED_RD_FIFO_FULL_BMSK 0x1000 +#define HWIO_IPA_UC_QMB_STATUS_COMPLETED_RD_FIFO_FULL_SHFT 0xc +#define HWIO_IPA_UC_QMB_STATUS_COMPLETED_RD_CNT_BMSK 0xf00 +#define HWIO_IPA_UC_QMB_STATUS_COMPLETED_RD_CNT_SHFT 0x8 +#define HWIO_IPA_UC_QMB_STATUS_OUTSTANDING_RD_CNT_BMSK 0xf0 +#define HWIO_IPA_UC_QMB_STATUS_OUTSTANDING_RD_CNT_SHFT 0x4 +#define HWIO_IPA_UC_QMB_STATUS_MAX_OUTSTANDING_RD_BMSK 0xf +#define HWIO_IPA_UC_QMB_STATUS_MAX_OUTSTANDING_RD_SHFT 0x0 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000130) +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000130) +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000130) +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_RMSK 0x1117 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_ATTR 0x3 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_IN in_dword_masked( \ + HWIO_IPA_UC_QMB_BUS_ATTRIB_ADDR, \ + HWIO_IPA_UC_QMB_BUS_ATTRIB_RMSK) +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_INM(m) in_dword_masked( \ + HWIO_IPA_UC_QMB_BUS_ATTRIB_ADDR, \ + m) +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_OUT(v) out_dword( \ + HWIO_IPA_UC_QMB_BUS_ATTRIB_ADDR, \ + v) +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_UC_QMB_BUS_ATTRIB_ADDR, \ + m, \ + v, \ + HWIO_IPA_UC_QMB_BUS_ATTRIB_IN) +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_SHARED_BMSK 0x1000 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_SHARED_SHFT 0xc +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_INNERSHARED_BMSK 0x100 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_INNERSHARED_SHFT 0x8 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_NOALLOCATE_BMSK 0x10 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_NOALLOCATE_SHFT 0x4 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_MEMTYPE_BMSK 0x7 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_MEMTYPE_SHFT 0x0 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_MEMTYPE_STRONGLY_ORDERED_FVAL 0x0 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_MEMTYPE_DEVICE_FVAL 0x1 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_MEMTYPE_NON_CACHEABLE_FVAL 0x2 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_MEMTYPE_COPYBACK_WRITEALLOCATE_FVAL 0x3 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_MEMTYPE_WRITETHROUGH_NOALLOCATE_FVAL \ + 0x6 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_MEMTYPE_COPYBACK_NOALLOCATE_FVAL 0x7 +#define HWIO_IPA_UC_MBOX_INT_STTS_n_ADDR(n) (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000200 + 0x10 * (n)) +#define HWIO_IPA_UC_MBOX_INT_STTS_n_PHYS(n) ( \ + IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000200 + 0x10 * (n)) +#define HWIO_IPA_UC_MBOX_INT_STTS_n_OFFS(n) ( \ + IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000200 + 0x10 * (n)) +#define HWIO_IPA_UC_MBOX_INT_EN_n_ADDR(n) (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000204 + 0x10 * (n)) +#define HWIO_IPA_UC_MBOX_INT_EN_n_PHYS(n) (IPA_UC_IPA_UC_PER_REG_BASE_PHYS \ + + 0x00000204 + 0x10 * (n)) +#define HWIO_IPA_UC_MBOX_INT_EN_n_OFFS(n) (IPA_UC_IPA_UC_PER_REG_BASE_OFFS \ + + 0x00000204 + 0x10 * (n)) +#define HWIO_IPA_UC_MBOX_INT_CLR_n_ADDR(n) (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000208 + 0x10 * (n)) +#define HWIO_IPA_UC_MBOX_INT_CLR_n_PHYS(n) ( \ + IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000208 + 0x10 * (n)) +#define HWIO_IPA_UC_MBOX_INT_CLR_n_OFFS(n) ( \ + IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000208 + 0x10 * (n)) +#define HWIO_IPA_UC_IPA_INT_STTS_n_ADDR(n) (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000300 + 0x10 * (n)) +#define HWIO_IPA_UC_IPA_INT_STTS_n_PHYS(n) ( \ + IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000300 + 0x10 * (n)) +#define HWIO_IPA_UC_IPA_INT_STTS_n_OFFS(n) ( \ + IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000300 + 0x10 * (n)) +#define HWIO_IPA_UC_IPA_INT_EN_n_ADDR(n) (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000304 + 0x10 * (n)) +#define HWIO_IPA_UC_IPA_INT_EN_n_PHYS(n) (IPA_UC_IPA_UC_PER_REG_BASE_PHYS \ + + 0x00000304 + 0x10 * (n)) +#define HWIO_IPA_UC_IPA_INT_EN_n_OFFS(n) (IPA_UC_IPA_UC_PER_REG_BASE_OFFS \ + + 0x00000304 + 0x10 * (n)) +#define HWIO_IPA_UC_IPA_INT_CLR_n_ADDR(n) (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000308 + 0x10 * (n)) +#define HWIO_IPA_UC_IPA_INT_CLR_n_PHYS(n) (IPA_UC_IPA_UC_PER_REG_BASE_PHYS \ + + 0x00000308 + 0x10 * (n)) +#define HWIO_IPA_UC_IPA_INT_CLR_n_OFFS(n) (IPA_UC_IPA_UC_PER_REG_BASE_OFFS \ + + 0x00000308 + 0x10 * (n)) +#define HWIO_IPA_UC_HWEV_INT_STTS_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000400) +#define HWIO_IPA_UC_HWEV_INT_STTS_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000400) +#define HWIO_IPA_UC_HWEV_INT_STTS_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000400) +#define HWIO_IPA_UC_HWEV_INT_EN_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000404) +#define HWIO_IPA_UC_HWEV_INT_EN_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000404) +#define HWIO_IPA_UC_HWEV_INT_EN_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000404) +#define HWIO_IPA_UC_HWEV_INT_CLR_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000408) +#define HWIO_IPA_UC_HWEV_INT_CLR_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000408) +#define HWIO_IPA_UC_HWEV_INT_CLR_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000408) +#define HWIO_IPA_UC_SWEV_INT_STTS_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000410) +#define HWIO_IPA_UC_SWEV_INT_STTS_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000410) +#define HWIO_IPA_UC_SWEV_INT_STTS_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000410) +#define HWIO_IPA_UC_SWEV_INT_EN_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000414) +#define HWIO_IPA_UC_SWEV_INT_EN_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000414) +#define HWIO_IPA_UC_SWEV_INT_EN_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000414) +#define HWIO_IPA_UC_SWEV_INT_CLR_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000418) +#define HWIO_IPA_UC_SWEV_INT_CLR_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000418) +#define HWIO_IPA_UC_SWEV_INT_CLR_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000418) +#define HWIO_IPA_UC_VUIC_INT_STTS_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x0000041c) +#define HWIO_IPA_UC_VUIC_INT_STTS_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x0000041c) +#define HWIO_IPA_UC_VUIC_INT_STTS_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x0000041c) +#define HWIO_IPA_UC_VUIC_INT_CLR_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000420) +#define HWIO_IPA_UC_VUIC_INT_CLR_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000420) +#define HWIO_IPA_UC_VUIC_INT_CLR_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000420) +#define HWIO_IPA_UC_TIMER_CTRL_n_ADDR(n) (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000500 + 0x10 * (n)) +#define HWIO_IPA_UC_TIMER_CTRL_n_PHYS(n) (IPA_UC_IPA_UC_PER_REG_BASE_PHYS \ + + 0x00000500 + 0x10 * (n)) +#define HWIO_IPA_UC_TIMER_CTRL_n_OFFS(n) (IPA_UC_IPA_UC_PER_REG_BASE_OFFS \ + + 0x00000500 + 0x10 * (n)) +#define HWIO_IPA_UC_TIMER_STATUS_n_ADDR(n) (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000508 + 0x10 * (n)) +#define HWIO_IPA_UC_TIMER_STATUS_n_PHYS(n) ( \ + IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000508 + 0x10 * (n)) +#define HWIO_IPA_UC_TIMER_STATUS_n_OFFS(n) ( \ + IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000508 + 0x10 * (n)) +#define HWIO_IPA_UC_EVENTS_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000600) +#define HWIO_IPA_UC_EVENTS_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000600) +#define HWIO_IPA_UC_EVENTS_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000600) +#define HWIO_IPA_UC_VUIC_BUS_ADDR_TRANSLATE_EN_ADDR ( \ + IPA_UC_IPA_UC_PER_REG_BASE + 0x00000710) +#define HWIO_IPA_UC_VUIC_BUS_ADDR_TRANSLATE_EN_PHYS ( \ + IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000710) +#define HWIO_IPA_UC_VUIC_BUS_ADDR_TRANSLATE_EN_OFFS ( \ + IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000710) +#define HWIO_IPA_UC_SYS_ADDR_MSB_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000714) +#define HWIO_IPA_UC_SYS_ADDR_MSB_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000714) +#define HWIO_IPA_UC_SYS_ADDR_MSB_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000714) +#define HWIO_IPA_UC_PC_RESTORE_WR_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000718) +#define HWIO_IPA_UC_PC_RESTORE_WR_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000718) +#define HWIO_IPA_UC_PC_RESTORE_WR_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000718) +#define HWIO_IPA_UC_PC_RESTORE_RD_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x0000071c) +#define HWIO_IPA_UC_PC_RESTORE_RD_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x0000071c) +#define HWIO_IPA_UC_PC_RESTORE_RD_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x0000071c) +#define HWIO_IPA_UC_SPARE_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00001ffc) +#define HWIO_IPA_UC_SPARE_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00001ffc) +#define HWIO_IPA_UC_SPARE_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00001ffc) +#endif diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.5/ipa_hwio_def.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.5/ipa_hwio_def.h new file mode 100644 index 0000000000..5fbff6025a --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.5/ipa_hwio_def.h @@ -0,0 +1,2963 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ +#if !defined(_IPA_HWIO_DEF_H_) +#define _IPA_HWIO_DEF_H_ +struct ipa_hwio_def_ipa_gsi_top_gsi_cfg_s { + u32 gsi_enable : 1; + u32 mcs_enable : 1; + u32 double_mcs_clk_freq : 1; + u32 uc_is_mcs : 1; + u32 gsi_pwr_clps : 1; + u32 bp_mtrix_disable : 1; + u32 reserved0 : 2; + u32 sleep_clk_div : 4; + u32 reserved1 : 20; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_cfg_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_cfg_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_ree_cfg_s { + u32 move_to_esc_clr_mode_trsh : 1; + u32 channel_empty_int_enable : 1; + u32 reserved0 : 6; + u32 max_burst_size : 8; + u32 reserved1 : 16; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_ree_cfg_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_ree_cfg_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_manager_ee_qos_n_s { + u32 ee_prio : 2; + u32 reserved0 : 6; + u32 max_ch_alloc : 5; + u32 reserved1 : 3; + u32 max_ev_alloc : 5; + u32 reserved2 : 11; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_manager_ee_qos_n_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_manager_ee_qos_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_ch_cntxt_base_addr_s { + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_ch_cntxt_base_addr_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_ch_cntxt_base_addr_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_ev_cntxt_base_addr_s { + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_ev_cntxt_base_addr_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_ev_cntxt_base_addr_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_re_storage_base_addr_s { + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_re_storage_base_addr_u { + struct + ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_re_storage_base_addr_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_re_esc_buf_base_addr_s { + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_re_esc_buf_base_addr_u { + struct + ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_re_esc_buf_base_addr_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_ee_scrach_base_addr_s { + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_ee_scrach_base_addr_u { + struct + ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_ee_scrach_base_addr_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_func_stack_base_addr_s { + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_func_stack_base_addr_u { + struct + ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_func_stack_base_addr_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ch_cmd_s { + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ch_cmd_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ch_cmd_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ee_generic_cmd_s { + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ee_generic_cmd_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ee_generic_cmd_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ch_db_s { + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ch_db_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ch_db_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ev_db_s { + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ev_db_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ev_db_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_new_re_s { + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_new_re_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_new_re_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ch_dis_comp_s { + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ch_dis_comp_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ch_dis_comp_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ch_empty_s { + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ch_empty_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ch_empty_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_event_gen_comp_s { + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_event_gen_comp_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_event_gen_comp_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_timer_expired_s { + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_timer_expired_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_timer_expired_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_write_eng_comp_s { + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_write_eng_comp_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_write_eng_comp_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_read_eng_comp_s { + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_read_eng_comp_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_read_eng_comp_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_uc_gp_int_s { + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_uc_gp_int_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_uc_gp_int_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_int_mod_stopped_s { + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_int_mod_stopped_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_int_mod_stopped_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_inst_ram_n_s { + u32 inst_byte_0 : 8; + u32 inst_byte_1 : 8; + u32 inst_byte_2 : 8; + u32 inst_byte_3 : 8; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_inst_ram_n_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_inst_ram_n_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_shram_n_s { + u32 shram : 32; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_shram_n_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_shram_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_map_ee_n_ch_k_vp_table_s { + u32 phy_ch : 5; + u32 valid : 1; + u32 reserved0 : 26; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_map_ee_n_ch_k_vp_table_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_map_ee_n_ch_k_vp_table_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_test_bus_sel_s { + u32 gsi_testbus_sel : 8; + u32 reserved0 : 8; + u32 gsi_hw_events_sel : 4; + u32 reserved1 : 12; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_test_bus_sel_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_test_bus_sel_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_test_bus_reg_s { + u32 gsi_testbus_reg : 32; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_test_bus_reg_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_test_bus_reg_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_debug_busy_reg_s { + u32 csr_busy : 1; + u32 ree_busy : 1; + u32 mcs_busy : 1; + u32 timer_busy : 1; + u32 rd_wr_busy : 1; + u32 ev_eng_busy : 1; + u32 int_eng_busy : 1; + u32 ree_pwr_clps_busy : 1; + u32 db_eng_busy : 1; + u32 dbg_cnt_busy : 1; + u32 uc_busy : 1; + u32 ic_busy : 1; + u32 sdma_busy : 1; + u32 reserved0 : 19; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_debug_busy_reg_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_busy_reg_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_debug_event_pending_s { + u32 chid_bit_map : 32; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_debug_event_pending_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_event_pending_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_debug_timer_pending_s { + u32 chid_bit_map : 32; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_debug_timer_pending_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_timer_pending_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_debug_rd_wr_pending_s { + u32 chid_bit_map : 32; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_debug_rd_wr_pending_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_rd_wr_pending_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_debug_countern_s { + u32 counter_value : 16; + u32 reserved0 : 16; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_debug_countern_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_countern_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_debug_pc_from_sw_s { + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_debug_pc_from_sw_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_pc_from_sw_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_debug_sw_stall_s { + u32 mcs_stall : 1; + u32 reserved0 : 31; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_debug_sw_stall_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_sw_stall_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_debug_pc_for_debug_s { + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_debug_pc_for_debug_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_pc_for_debug_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_debug_qsb_log_err_trns_id_s { + u32 err_write : 1; + u32 reserved0 : 7; + u32 err_tid : 8; + u32 err_mid : 8; + u32 err_saved : 1; + u32 reserved1 : 7; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_debug_qsb_log_err_trns_id_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_qsb_log_err_trns_id_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_debug_sw_rf_n_read_s { + u32 rf_reg : 32; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_debug_sw_rf_n_read_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_sw_rf_n_read_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_debug_ee_n_ev_k_vp_table_s { + u32 phy_ev_ch : 5; + u32 valid : 1; + u32 reserved0 : 26; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_debug_ee_n_ev_k_vp_table_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_ee_n_ev_k_vp_table_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_0_s { + u32 chtype_protocol : 3; + u32 chtype_dir : 1; + u32 ee : 4; + u32 chid : 5; + u32 chtype_protocol_msb : 1; + u32 erindex : 5; + u32 reserved0 : 1; + u32 chstate : 4; + u32 element_size : 8; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_0_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_0_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_1_s { + u32 r_length : 16; + u32 reserved0 : 16; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_1_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_1_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_2_s { + u32 r_base_addr_lsbs : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_2_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_2_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_3_s { + u32 r_base_addr_msbs : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_3_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_3_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_4_s { + u32 read_ptr_lsb : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_4_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_4_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_5_s { + u32 read_ptr_msb : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_5_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_5_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_6_s { + u32 write_ptr_lsb : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_6_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_6_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_7_s { + u32 write_ptr_msb : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_7_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_7_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_re_fetch_read_ptr_s { + u32 read_ptr : 16; + u32 reserved0 : 16; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_re_fetch_read_ptr_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_re_fetch_read_ptr_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_re_fetch_write_ptr_s { + u32 re_intr_db : 16; + u32 reserved0 : 16; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_re_fetch_write_ptr_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_re_fetch_write_ptr_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_qos_s { + u32 wrr_weight : 4; + u32 reserved0 : 4; + u32 max_prefetch : 1; + u32 use_db_eng : 1; + u32 prefetch_mode : 4; + u32 reserved1 : 2; + u32 empty_lvl_thrshold : 8; + u32 reserved2 : 8; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_qos_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_qos_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_0_s { + u32 scratch : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_0_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_0_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_1_s { + u32 scratch : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_1_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_1_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_2_s { + u32 scratch : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_2_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_2_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_3_s { + u32 scratch : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_3_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_3_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_0_s { + u32 chtype : 4; + u32 ee : 4; + u32 evchid : 8; + u32 intype : 1; + u32 reserved0 : 3; + u32 chstate : 4; + u32 element_size : 8; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_0_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_0_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_1_s { + u32 r_length : 16; + u32 reserved0 : 16; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_1_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_1_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_2_s { + u32 r_base_addr_lsbs : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_2_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_2_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_3_s { + u32 r_base_addr_msbs : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_3_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_3_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_4_s { + u32 read_ptr_lsb : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_4_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_4_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_5_s { + u32 read_ptr_msb : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_5_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_5_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_6_s { + u32 write_ptr_lsb : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_6_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_6_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_7_s { + u32 write_ptr_msb : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_7_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_7_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_8_s { + u32 int_modt : 16; + u32 int_modc : 8; + u32 int_mod_cnt : 8; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_8_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_8_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_9_s { + u32 intvec : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_9_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_9_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_10_s { + u32 msi_addr_lsb : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_10_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_10_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_11_s { + u32 msi_addr_msb : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_11_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_11_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_12_s { + u32 rp_update_addr_lsb : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_12_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_12_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_13_s { + u32 rp_update_addr_msb : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_13_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_13_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_scratch_0_s { + u32 scratch : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_scratch_0_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_scratch_0_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_scratch_1_s { + u32 scratch : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_scratch_1_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_scratch_1_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_status_s { + u32 enabled : 1; + u32 reserved0 : 31; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_status_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_status_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_type_irq_s { + u32 ch_ctrl : 1; + u32 ev_ctrl : 1; + u32 glob_ee : 1; + u32 ieob : 1; + u32 inter_ee_ch_ctrl : 1; + u32 inter_ee_ev_ctrl : 1; + u32 general : 1; + u32 reserved0 : 25; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_type_irq_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_type_irq_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_type_irq_msk_s { + u32 ch_ctrl : 1; + u32 ev_ctrl : 1; + u32 glob_ee : 1; + u32 ieob : 1; + u32 inter_ee_ch_ctrl : 1; + u32 inter_ee_ev_ctrl : 1; + u32 general : 1; + u32 reserved0 : 25; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_type_irq_msk_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_type_irq_msk_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_gsi_ch_irq_s { + u32 gsi_ch_bit_map : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_gsi_ch_irq_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_gsi_ch_irq_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ev_ch_irq_s { + u32 ev_ch_bit_map : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ev_ch_irq_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ev_ch_irq_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_gsi_ch_irq_msk_s { + u32 gsi_ch_bit_map_msk : 23; + u32 reserved0 : 9; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_gsi_ch_irq_msk_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_gsi_ch_irq_msk_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ev_ch_irq_msk_s { + u32 ev_ch_bit_map_msk : 20; + u32 reserved0 : 12; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ev_ch_irq_msk_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ev_ch_irq_msk_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_gsi_ch_irq_clr_s { + u32 gsi_ch_bit_map : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_gsi_ch_irq_clr_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_gsi_ch_irq_clr_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ev_ch_irq_clr_s { + u32 ev_ch_bit_map : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ev_ch_irq_clr_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ev_ch_irq_clr_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ieob_irq_s { + u32 ev_ch_bit_map : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ieob_irq_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ieob_irq_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ieob_irq_msk_s { + u32 ev_ch_bit_map_msk : 20; + u32 reserved0 : 12; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ieob_irq_msk_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ieob_irq_msk_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ieob_irq_clr_s { + u32 ev_ch_bit_map : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ieob_irq_clr_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ieob_irq_clr_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_glob_irq_stts_s { + u32 error_int : 1; + u32 gp_int1 : 1; + u32 gp_int2 : 1; + u32 gp_int3 : 1; + u32 reserved0 : 28; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_glob_irq_stts_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_glob_irq_stts_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_gsi_irq_stts_s { + u32 gsi_break_point : 1; + u32 gsi_bus_error : 1; + u32 gsi_cmd_fifo_ovrflow : 1; + u32 gsi_mcs_stack_ovrflow : 1; + u32 reserved0 : 28; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_gsi_irq_stts_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_gsi_irq_stts_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_intset_s { + u32 intype : 1; + u32 reserved0 : 31; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_intset_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_intset_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_msi_base_lsb_s { + u32 msi_addr_lsb : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_msi_base_lsb_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_msi_base_lsb_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_msi_base_msb_s { + u32 msi_addr_msb : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_msi_base_msb_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_msi_base_msb_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_error_log_s { + u32 error_log : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_error_log_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_error_log_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_error_log_clr_s { + u32 error_log_clr : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_error_log_clr_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_error_log_clr_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_scratch_0_s { + u32 scratch : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_scratch_0_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_scratch_0_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_scratch_1_s { + u32 scratch : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_scratch_1_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_scratch_1_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_comp_hw_version_s { + u32 step : 16; + u32 minor : 12; + u32 major : 4; +}; +union ipa_hwio_def_ipa_comp_hw_version_u { + struct ipa_hwio_def_ipa_comp_hw_version_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_comp_cfg_s { + u32 reserved0 : 1; + u32 gsi_snoc_bypass_dis : 1; + u32 gen_qmb_0_snoc_bypass_dis : 1; + u32 gen_qmb_1_snoc_bypass_dis : 1; + u32 reserved1 : 1; + u32 ipa_qmb_select_by_address_cons_en : 1; + u32 ipa_qmb_select_by_address_prod_en : 1; + u32 gsi_multi_inorder_rd_dis : 1; + u32 gsi_multi_inorder_wr_dis : 1; + u32 gen_qmb_0_multi_inorder_rd_dis : 1; + u32 gen_qmb_1_multi_inorder_rd_dis : 1; + u32 gen_qmb_0_multi_inorder_wr_dis : 1; + u32 gen_qmb_1_multi_inorder_wr_dis : 1; + u32 gen_qmb_0_snoc_cnoc_loop_protection_disable : 1; + u32 gsi_snoc_cnoc_loop_protection_disable : 1; + u32 gsi_multi_axi_masters_dis : 1; + u32 ipa_qmb_select_by_address_global_en : 1; + u32 ipa_atomic_fetcher_arb_lock_dis : 4; + u32 ipa_full_flush_wait_rsc_closure_en : 1; + u32 reserved2 : 10; +}; +union ipa_hwio_def_ipa_comp_cfg_u { + struct ipa_hwio_def_ipa_comp_cfg_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_route_s { + u32 route_dis : 1; + u32 route_def_pipe : 5; + u32 route_def_hdr_table : 1; + u32 route_def_hdr_ofst : 10; + u32 route_frag_def_pipe : 5; + u32 reserved0 : 2; + u32 route_def_retain_hdr : 1; + u32 reserved1 : 7; +}; +union ipa_hwio_def_ipa_route_u { + struct ipa_hwio_def_ipa_route_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_proc_iph_cfg_s { + u32 iph_threshold : 2; + u32 iph_pipelining_disable : 1; + u32 reserved0 : 1; + u32 status_from_iph_frst_always : 1; + u32 iph_nat_blind_invalidate_tport_offset_disable : 1; + u32 pipestage_overlap_disable : 1; + u32 ftch_dcph_overlap_enable : 1; + u32 iph_pkt_parser_protocol_stop_enable : 1; + u32 iph_pkt_parser_protocol_stop_hop : 1; + u32 iph_pkt_parser_protocol_stop_dest : 1; + u32 iph_pkt_parser_ihl_to_2nd_frag_en : 1; + u32 reserved1 : 4; + u32 iph_pkt_parser_protocol_stop_value : 8; + u32 d_dcph_multi_engine_disable : 1; + u32 reserved2 : 7; +}; +union ipa_hwio_def_ipa_proc_iph_cfg_u { + struct ipa_hwio_def_ipa_proc_iph_cfg_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_dpl_timer_lsb_s { + u32 tod_lsb : 32; +}; +union ipa_hwio_def_ipa_dpl_timer_lsb_u { + struct ipa_hwio_def_ipa_dpl_timer_lsb_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_dpl_timer_msb_s { + u32 tod_msb : 16; + u32 reserved0 : 15; + u32 timer_en : 1; +}; +union ipa_hwio_def_ipa_dpl_timer_msb_u { + struct ipa_hwio_def_ipa_dpl_timer_msb_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_state_tx_wrapper_s { + u32 tx0_idle : 1; + u32 tx1_idle : 1; + u32 ipa_prod_ackmngr_db_empty : 1; + u32 ipa_prod_ackmngr_state_idle : 1; + u32 ipa_prod_bresp_empty : 1; + u32 ipa_prod_bresp_toggle_idle : 1; + u32 ipa_mbim_pkt_fms_idle : 1; + u32 mbim_direct_dma : 2; + u32 trnseq_force_valid : 1; + u32 pkt_drop_cnt_idle : 1; + u32 nlo_direct_dma : 2; + u32 coal_direct_dma : 2; + u32 coal_slave_idle : 1; + u32 coal_slave_ctx_idle : 1; + u32 reserved0 : 8; + u32 coal_slave_open_frame : 4; + u32 reserved1 : 3; +}; +union ipa_hwio_def_ipa_state_tx_wrapper_u { + struct ipa_hwio_def_ipa_state_tx_wrapper_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_state_tx1_s { + u32 flopped_arbit_type : 3; + u32 arbit_type : 3; + u32 pa_idle : 1; + u32 pa_ctx_idle : 1; + u32 pa_rst_idle : 1; + u32 pa_pub_cnt_empty : 1; + u32 tx_cmd_main_idle : 1; + u32 tx_cmd_trnseq_idle : 1; + u32 tx_cmd_snif_idle : 1; + u32 tx_cmd_bresp_aloc_idle : 1; + u32 tx_cmd_bresp_inj_idle : 1; + u32 ar_idle : 1; + u32 dmaw_idle : 1; + u32 dmaw_last_outsd_idle : 1; + u32 pf_idle : 1; + u32 pf_empty : 1; + u32 aligner_empty : 1; + u32 holb_idle : 1; + u32 holb_mask_idle : 1; + u32 rsrcrel_idle : 1; + u32 suspend_empty : 1; + u32 cs_snif_idle : 1; + u32 last_cmd_pipe : 5; + u32 suspend_req_empty : 1; +}; +union ipa_hwio_def_ipa_state_tx1_u { + struct ipa_hwio_def_ipa_state_tx1_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_state_fetcher_s { + u32 ipa_hps_ftch_state_idle : 1; + u32 ipa_hps_ftch_alloc_state_idle : 1; + u32 ipa_hps_ftch_pkt_state_idle : 1; + u32 ipa_hps_ftch_imm_state_idle : 1; + u32 ipa_hps_ftch_cmplt_state_idle : 1; + u32 ipa_hps_dmar_state_idle : 7; + u32 ipa_hps_dmar_slot_state_idle : 7; + u32 ipa_hps_imm_cmd_exec_state_idle : 1; + u32 reserved0 : 12; +}; +union ipa_hwio_def_ipa_state_fetcher_u { + struct ipa_hwio_def_ipa_state_fetcher_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_state_fetcher_mask_0_s { + u32 mask_queue_dmar_uses_queue : 8; + u32 mask_queue_imm_exec : 8; + u32 mask_queue_no_resources_context : 8; + u32 mask_queue_no_resources_hps_dmar : 8; +}; +union ipa_hwio_def_ipa_state_fetcher_mask_0_u { + struct ipa_hwio_def_ipa_state_fetcher_mask_0_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_state_fetcher_mask_1_s { + u32 mask_queue_no_resources_ack_entry : 8; + u32 mask_queue_arb_lock : 8; + u32 mask_queue_step_mode : 8; + u32 mask_queue_no_space_dpl_fifo : 8; +}; +union ipa_hwio_def_ipa_state_fetcher_mask_1_u { + struct ipa_hwio_def_ipa_state_fetcher_mask_1_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_state_dpl_fifo_s { + u32 pop_fsm_state : 3; + u32 reserved0 : 29; +}; +union ipa_hwio_def_ipa_state_dpl_fifo_u { + struct ipa_hwio_def_ipa_state_dpl_fifo_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_state_coal_master_s { + u32 vp_vld : 4; + u32 main_fsm_state : 4; + u32 find_open_fsm_state : 4; + u32 hash_calc_fsm_state : 4; + u32 check_fit_fsm_state : 4; + u32 init_vp_fsm_state : 4; + u32 lru_vp : 4; + u32 vp_timer_expired : 4; +}; +union ipa_hwio_def_ipa_state_coal_master_u { + struct ipa_hwio_def_ipa_state_coal_master_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_state_dfetcher_s { + u32 ipa_dps_ftch_pkt_state_idle : 1; + u32 ipa_dps_ftch_cmplt_state_idle : 1; + u32 reserved0 : 2; + u32 ipa_dps_dmar_state_idle : 6; + u32 reserved1 : 2; + u32 ipa_dps_dmar_slot_state_idle : 6; + u32 reserved2 : 14; +}; +union ipa_hwio_def_ipa_state_dfetcher_u { + struct ipa_hwio_def_ipa_state_dfetcher_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_state_acl_s { + u32 ipa_hps_h_dcph_empty : 1; + u32 ipa_hps_h_dcph_active : 1; + u32 ipa_hps_pkt_parser_empty : 1; + u32 ipa_hps_pkt_parser_active : 1; + u32 ipa_hps_filter_nat_empty : 1; + u32 ipa_hps_filter_nat_active : 1; + u32 ipa_hps_router_empty : 1; + u32 ipa_hps_router_active : 1; + u32 ipa_hps_hdri_empty : 1; + u32 ipa_hps_hdri_active : 1; + u32 ipa_hps_ucp_empty : 1; + u32 ipa_hps_ucp_active : 1; + u32 ipa_hps_enqueuer_empty : 1; + u32 ipa_hps_enqueuer_active : 1; + u32 ipa_dps_d_dcph_empty : 1; + u32 ipa_dps_d_dcph_active : 1; + u32 reserved0 : 2; + u32 ipa_dps_dispatcher_empty : 1; + u32 ipa_dps_dispatcher_active : 1; + u32 ipa_dps_d_dcph_2_empty : 1; + u32 ipa_dps_d_dcph_2_active : 1; + u32 ipa_hps_sequencer_idle : 1; + u32 ipa_dps_sequencer_idle : 1; + u32 ipa_dps_d_dcph_2nd_empty : 1; + u32 ipa_dps_d_dcph_2nd_active : 1; + u32 ipa_hps_coal_master_empty : 1; + u32 ipa_hps_coal_master_active : 1; + u32 reserved1 : 4; +}; +union ipa_hwio_def_ipa_state_acl_u { + struct ipa_hwio_def_ipa_state_acl_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_state_gsi_tlv_s { + u32 ipa_gsi_toggle_fsm_idle : 1; + u32 reserved0 : 31; +}; +union ipa_hwio_def_ipa_state_gsi_tlv_u { + struct ipa_hwio_def_ipa_state_gsi_tlv_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_state_gsi_aos_s { + u32 ipa_gsi_aos_fsm_idle : 1; + u32 reserved0 : 31; +}; +union ipa_hwio_def_ipa_state_gsi_aos_u { + struct ipa_hwio_def_ipa_state_gsi_aos_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_state_gsi_if_s { + u32 ipa_gsi_prod_fsm_tx_0 : 4; + u32 ipa_gsi_prod_fsm_tx_1 : 4; + u32 reserved0 : 24; +}; +union ipa_hwio_def_ipa_state_gsi_if_u { + struct ipa_hwio_def_ipa_state_gsi_if_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_state_gsi_skip_s { + u32 ipa_gsi_skip_fsm : 2; + u32 reserved0 : 30; +}; +union ipa_hwio_def_ipa_state_gsi_skip_u { + struct ipa_hwio_def_ipa_state_gsi_skip_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_state_gsi_if_cons_s { + u32 state : 1; + u32 cache_vld : 6; + u32 rx_req : 10; + u32 rx_req_no_zero : 10; + u32 reserved0 : 5; +}; +union ipa_hwio_def_ipa_state_gsi_if_cons_u { + struct ipa_hwio_def_ipa_state_gsi_if_cons_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_state_s { + u32 rx_wait : 1; + u32 rx_idle : 1; + u32 tx_idle : 1; + u32 dpl_fifo_idle : 1; + u32 bam_gsi_idle : 1; + u32 ipa_status_sniffer_idle : 1; + u32 ipa_noc_idle : 1; + u32 aggr_idle : 1; + u32 mbim_aggr_idle : 1; + u32 ipa_rsrc_mngr_db_empty : 1; + u32 ipa_rsrc_state_idle : 1; + u32 ipa_ackmngr_db_empty : 1; + u32 ipa_ackmngr_state_idle : 1; + u32 ipa_tx_ackq_full : 1; + u32 ipa_prod_ackmngr_db_empty : 1; + u32 ipa_prod_ackmngr_state_idle : 1; + u32 ipa_prod_bresp_idle : 1; + u32 ipa_full_idle : 1; + u32 ipa_ntf_tx_empty : 1; + u32 ipa_tx_ackq_empty : 1; + u32 ipa_uc_ackq_empty : 1; + u32 ipa_rx_ackq_empty : 1; + u32 ipa_tx_commander_cmdq_empty : 1; + u32 ipa_rx_splt_cmdq_empty : 4; + u32 reserved0 : 1; + u32 ipa_rx_hps_empty : 1; + u32 ipa_hps_dps_empty : 1; + u32 ipa_dps_tx_empty : 1; + u32 ipa_uc_rx_hnd_cmdq_empty : 1; +}; +union ipa_hwio_def_ipa_state_u { + struct ipa_hwio_def_ipa_state_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_state_rx_active_s { + u32 endpoints : 13; + u32 reserved0 : 19; +}; +union ipa_hwio_def_ipa_state_rx_active_u { + struct ipa_hwio_def_ipa_state_rx_active_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_state_tx0_s { + u32 last_arbit_type : 2; + u32 next_arbit_type : 2; + u32 pa_idle : 1; + u32 pa_ctx_idle : 1; + u32 pa_pub_cnt_empty : 1; + u32 tx_cmd_main_idle : 1; + u32 tx_cmd_trnseq_idle : 1; + u32 tx_cmd_snif_idle : 1; + u32 tx_cmd_bresp_aloc_idle : 1; + u32 tx_cmd_bresp_inj_idle : 1; + u32 ar_idle : 1; + u32 dmaw_idle : 1; + u32 dmaw_last_outsd_idle : 1; + u32 pf_idle : 1; + u32 pf_empty : 1; + u32 aligner_empty : 1; + u32 holb_idle : 1; + u32 holb_mask_idle : 1; + u32 rsrcrel_idle : 1; + u32 suspend_empty : 1; + u32 cs_snif_idle : 1; + u32 last_cmd_pipe : 5; + u32 reserved0 : 4; +}; +union ipa_hwio_def_ipa_state_tx0_u { + struct ipa_hwio_def_ipa_state_tx0_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_state_aggr_active_s { + u32 endpoints : 31; + u32 reserved0 : 1; +}; +union ipa_hwio_def_ipa_state_aggr_active_u { + struct ipa_hwio_def_ipa_state_aggr_active_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_state_nlo_aggr_s { + u32 nlo_aggr_state : 32; +}; +union ipa_hwio_def_ipa_state_nlo_aggr_u { + struct ipa_hwio_def_ipa_state_nlo_aggr_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_state_coal_master_1_s { + u32 init_vp_wr_ctx_line : 6; + u32 init_vp_rd_pkt_line : 6; + u32 init_vp_fsm_state : 4; + u32 check_fit_rd_ctx_line : 6; + u32 check_fit_fsm_state : 4; + u32 arbiter_state : 4; + u32 reserved0 : 2; +}; +union ipa_hwio_def_ipa_state_coal_master_1_u { + struct ipa_hwio_def_ipa_state_coal_master_1_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_filt_rout_hash_en_s { + u32 ipv6_router_hash_en : 1; + u32 reserved0 : 3; + u32 ipv6_filter_hash_en : 1; + u32 reserved1 : 3; + u32 ipv4_router_hash_en : 1; + u32 reserved2 : 3; + u32 ipv4_filter_hash_en : 1; + u32 reserved3 : 19; +}; +union ipa_hwio_def_ipa_filt_rout_hash_en_u { + struct ipa_hwio_def_ipa_filt_rout_hash_en_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_filt_rout_hash_flush_s { + u32 ipv6_router_hash_flush : 1; + u32 reserved0 : 3; + u32 ipv6_filter_hash_flush : 1; + u32 reserved1 : 3; + u32 ipv4_router_hash_flush : 1; + u32 reserved2 : 3; + u32 ipv4_filter_hash_flush : 1; + u32 reserved3 : 19; +}; +union ipa_hwio_def_ipa_filt_rout_hash_flush_u { + struct ipa_hwio_def_ipa_filt_rout_hash_flush_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_ipv4_filter_init_values_s { + u32 ip_v4_filter_init_hashed_addr : 16; + u32 ip_v4_filter_init_non_hashed_addr : 16; +}; +union ipa_hwio_def_ipa_ipv4_filter_init_values_u { + struct ipa_hwio_def_ipa_ipv4_filter_init_values_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_ipv6_filter_init_values_s { + u32 ip_v6_filter_init_hashed_addr : 16; + u32 ip_v6_filter_init_non_hashed_addr : 16; +}; +union ipa_hwio_def_ipa_ipv6_filter_init_values_u { + struct ipa_hwio_def_ipa_ipv6_filter_init_values_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_ipv4_route_init_values_s { + u32 ip_v4_route_init_hashed_addr : 16; + u32 ip_v4_route_init_non_hashed_addr : 16; +}; +union ipa_hwio_def_ipa_ipv4_route_init_values_u { + struct ipa_hwio_def_ipa_ipv4_route_init_values_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_ipv6_route_init_values_s { + u32 ip_v6_route_init_hashed_addr : 16; + u32 ip_v6_route_init_non_hashed_addr : 16; +}; +union ipa_hwio_def_ipa_ipv6_route_init_values_u { + struct ipa_hwio_def_ipa_ipv6_route_init_values_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_bam_activated_ports_s { + u32 endpoints : 31; + u32 reserved0 : 1; +}; +union ipa_hwio_def_ipa_bam_activated_ports_u { + struct ipa_hwio_def_ipa_bam_activated_ports_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_sys_pkt_proc_cntxt_base_s { + u32 zero : 3; + u32 addr : 29; +}; +union ipa_hwio_def_ipa_sys_pkt_proc_cntxt_base_u { + struct ipa_hwio_def_ipa_sys_pkt_proc_cntxt_base_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_sys_pkt_proc_cntxt_base_msb_s { + u32 addr : 32; +}; +union ipa_hwio_def_ipa_sys_pkt_proc_cntxt_base_msb_u { + struct ipa_hwio_def_ipa_sys_pkt_proc_cntxt_base_msb_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_local_pkt_proc_cntxt_base_s { + u32 zero : 3; + u32 addr : 15; + u32 reserved0 : 14; +}; +union ipa_hwio_def_ipa_local_pkt_proc_cntxt_base_u { + struct ipa_hwio_def_ipa_local_pkt_proc_cntxt_base_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_src_rsrc_grp_01_rsrc_type_n_s { + u32 src_rsrc_grp_0_min_limit : 6; + u32 reserved0 : 2; + u32 src_rsrc_grp_0_max_limit : 6; + u32 reserved1 : 2; + u32 src_rsrc_grp_1_min_limit : 6; + u32 reserved2 : 2; + u32 src_rsrc_grp_1_max_limit : 6; + u32 reserved3 : 2; +}; +union ipa_hwio_def_ipa_src_rsrc_grp_01_rsrc_type_n_u { + struct ipa_hwio_def_ipa_src_rsrc_grp_01_rsrc_type_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_src_rsrc_grp_23_rsrc_type_n_s { + u32 src_rsrc_grp_2_min_limit : 6; + u32 reserved0 : 2; + u32 src_rsrc_grp_2_max_limit : 6; + u32 reserved1 : 2; + u32 src_rsrc_grp_3_min_limit : 6; + u32 reserved2 : 2; + u32 src_rsrc_grp_3_max_limit : 6; + u32 reserved3 : 2; +}; +union ipa_hwio_def_ipa_src_rsrc_grp_23_rsrc_type_n_u { + struct ipa_hwio_def_ipa_src_rsrc_grp_23_rsrc_type_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_src_rsrc_grp_45_rsrc_type_n_s { + u32 src_rsrc_grp_4_min_limit : 6; + u32 reserved0 : 2; + u32 src_rsrc_grp_4_max_limit : 6; + u32 reserved1 : 18; +}; +union ipa_hwio_def_ipa_src_rsrc_grp_45_rsrc_type_n_u { + struct ipa_hwio_def_ipa_src_rsrc_grp_45_rsrc_type_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_src_rsrc_grp_0123_rsrc_type_cnt_n_s { + u32 src_rsrc_grp_0_cnt : 6; + u32 reserved0 : 2; + u32 src_rsrc_grp_1_cnt : 6; + u32 reserved1 : 2; + u32 src_rsrc_grp_2_cnt : 6; + u32 reserved2 : 2; + u32 src_rsrc_grp_3_cnt : 6; + u32 reserved3 : 2; +}; +union ipa_hwio_def_ipa_src_rsrc_grp_0123_rsrc_type_cnt_n_u { + struct ipa_hwio_def_ipa_src_rsrc_grp_0123_rsrc_type_cnt_n_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_src_rsrc_grp_4567_rsrc_type_cnt_n_s { + u32 src_rsrc_grp_4_cnt : 6; + u32 reserved0 : 26; +}; +union ipa_hwio_def_ipa_src_rsrc_grp_4567_rsrc_type_cnt_n_u { + struct ipa_hwio_def_ipa_src_rsrc_grp_4567_rsrc_type_cnt_n_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_dst_rsrc_grp_01_rsrc_type_n_s { + u32 dst_rsrc_grp_0_min_limit : 6; + u32 reserved0 : 2; + u32 dst_rsrc_grp_0_max_limit : 6; + u32 reserved1 : 2; + u32 dst_rsrc_grp_1_min_limit : 6; + u32 reserved2 : 2; + u32 dst_rsrc_grp_1_max_limit : 6; + u32 reserved3 : 2; +}; +union ipa_hwio_def_ipa_dst_rsrc_grp_01_rsrc_type_n_u { + struct ipa_hwio_def_ipa_dst_rsrc_grp_01_rsrc_type_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_dst_rsrc_grp_23_rsrc_type_n_s { + u32 dst_rsrc_grp_2_min_limit : 6; + u32 reserved0 : 2; + u32 dst_rsrc_grp_2_max_limit : 6; + u32 reserved1 : 2; + u32 dst_rsrc_grp_3_min_limit : 6; + u32 reserved2 : 2; + u32 dst_rsrc_grp_3_max_limit : 6; + u32 reserved3 : 2; +}; +union ipa_hwio_def_ipa_dst_rsrc_grp_23_rsrc_type_n_u { + struct ipa_hwio_def_ipa_dst_rsrc_grp_23_rsrc_type_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_dst_rsrc_grp_45_rsrc_type_n_s { + u32 dst_rsrc_grp_4_min_limit : 6; + u32 reserved0 : 2; + u32 dst_rsrc_grp_4_max_limit : 6; + u32 reserved1 : 18; +}; +union ipa_hwio_def_ipa_dst_rsrc_grp_45_rsrc_type_n_u { + struct ipa_hwio_def_ipa_dst_rsrc_grp_45_rsrc_type_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_dst_rsrc_grp_0123_rsrc_type_cnt_n_s { + u32 dst_rsrc_grp_0_cnt : 6; + u32 reserved0 : 2; + u32 dst_rsrc_grp_1_cnt : 6; + u32 reserved1 : 2; + u32 dst_rsrc_grp_2_cnt : 6; + u32 reserved2 : 2; + u32 dst_rsrc_grp_3_cnt : 6; + u32 reserved3 : 2; +}; +union ipa_hwio_def_ipa_dst_rsrc_grp_0123_rsrc_type_cnt_n_u { + struct ipa_hwio_def_ipa_dst_rsrc_grp_0123_rsrc_type_cnt_n_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_dst_rsrc_grp_4567_rsrc_type_cnt_n_s { + u32 dst_rsrc_grp_4_cnt : 8; + u32 reserved0 : 24; +}; +union ipa_hwio_def_ipa_dst_rsrc_grp_4567_rsrc_type_cnt_n_u { + struct ipa_hwio_def_ipa_dst_rsrc_grp_4567_rsrc_type_cnt_n_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_rsrc_grp_cfg_s { + u32 src_grp_special_valid : 1; + u32 reserved0 : 3; + u32 src_grp_special_index : 3; + u32 reserved1 : 1; + u32 dst_pipe_special_valid : 1; + u32 reserved2 : 3; + u32 dst_pipe_special_index : 5; + u32 reserved3 : 3; + u32 dst_grp_special_valid : 1; + u32 reserved4 : 3; + u32 dst_grp_special_index : 6; + u32 reserved5 : 2; +}; +union ipa_hwio_def_ipa_rsrc_grp_cfg_u { + struct ipa_hwio_def_ipa_rsrc_grp_cfg_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_pipeline_disable_s { + u32 reserved0 : 3; + u32 rx_cmdq_splitter_dis : 1; + u32 reserved1 : 28; +}; +union ipa_hwio_def_ipa_pipeline_disable_u { + struct ipa_hwio_def_ipa_pipeline_disable_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_endp_init_ctrl_n_s { + u32 endp_suspend : 1; + u32 endp_delay : 1; + u32 reserved0 : 30; +}; +union ipa_hwio_def_ipa_endp_init_ctrl_n_u { + struct ipa_hwio_def_ipa_endp_init_ctrl_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_endp_init_ctrl_scnd_n_s { + u32 reserved0 : 1; + u32 endp_delay : 1; + u32 reserved1 : 30; +}; +union ipa_hwio_def_ipa_endp_init_ctrl_scnd_n_u { + struct ipa_hwio_def_ipa_endp_init_ctrl_scnd_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_endp_init_cfg_n_s { + u32 frag_offload_en : 1; + u32 cs_offload_en : 2; + u32 cs_metadata_hdr_offset : 4; + u32 reserved0 : 1; + u32 gen_qmb_master_sel : 1; + u32 reserved1 : 23; +}; +union ipa_hwio_def_ipa_endp_init_cfg_n_u { + struct ipa_hwio_def_ipa_endp_init_cfg_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_endp_init_nat_n_s { + u32 nat_en : 2; + u32 reserved0 : 30; +}; +union ipa_hwio_def_ipa_endp_init_nat_n_u { + struct ipa_hwio_def_ipa_endp_init_nat_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_endp_init_hdr_n_s { + u32 hdr_len : 6; + u32 hdr_ofst_metadata_valid : 1; + u32 hdr_ofst_metadata : 6; + u32 hdr_additional_const_len : 6; + u32 hdr_ofst_pkt_size_valid : 1; + u32 hdr_ofst_pkt_size : 6; + u32 hdr_a5_mux : 1; + u32 hdr_len_inc_deagg_hdr : 1; + u32 hdr_len_msb : 2; + u32 hdr_ofst_metadata_msb : 2; +}; +union ipa_hwio_def_ipa_endp_init_hdr_n_u { + struct ipa_hwio_def_ipa_endp_init_hdr_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_endp_init_hdr_ext_n_s { + u32 hdr_endianness : 1; + u32 hdr_total_len_or_pad_valid : 1; + u32 hdr_total_len_or_pad : 1; + u32 hdr_payload_len_inc_padding : 1; + u32 hdr_total_len_or_pad_offset : 6; + u32 hdr_pad_to_alignment : 4; + u32 reserved0 : 2; + u32 hdr_total_len_or_pad_offset_msb : 2; + u32 hdr_ofst_pkt_size_msb : 2; + u32 hdr_additional_const_len_msb : 2; + u32 reserved1 : 10; +}; +union ipa_hwio_def_ipa_endp_init_hdr_ext_n_u { + struct ipa_hwio_def_ipa_endp_init_hdr_ext_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_endp_init_hdr_metadata_mask_n_s { + u32 metadata_mask : 32; +}; +union ipa_hwio_def_ipa_endp_init_hdr_metadata_mask_n_u { + struct ipa_hwio_def_ipa_endp_init_hdr_metadata_mask_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_endp_init_hdr_metadata_n_s { + u32 metadata : 32; +}; +union ipa_hwio_def_ipa_endp_init_hdr_metadata_n_u { + struct ipa_hwio_def_ipa_endp_init_hdr_metadata_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_endp_init_mode_n_s { + u32 mode : 3; + u32 dcph_enable : 1; + u32 dest_pipe_index : 5; + u32 reserved0 : 3; + u32 byte_threshold : 16; + u32 pipe_replicate_en : 1; + u32 pad_en : 1; + u32 reserved1 : 2; +}; +union ipa_hwio_def_ipa_endp_init_mode_n_u { + struct ipa_hwio_def_ipa_endp_init_mode_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_endp_init_aggr_n_s { + u32 aggr_en : 2; + u32 aggr_type : 3; + u32 aggr_byte_limit : 6; + u32 reserved0 : 1; + u32 aggr_time_limit : 5; + u32 aggr_pkt_limit : 6; + u32 aggr_sw_eof_active : 1; + u32 aggr_force_close : 1; + u32 reserved1 : 1; + u32 aggr_hard_byte_limit_enable : 1; + u32 aggr_gran_sel : 1; + u32 reserved2 : 4; +}; +union ipa_hwio_def_ipa_endp_init_aggr_n_u { + struct ipa_hwio_def_ipa_endp_init_aggr_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_endp_init_hol_block_en_n_s { + u32 en : 1; + u32 reserved0 : 31; +}; +union ipa_hwio_def_ipa_endp_init_hol_block_en_n_u { + struct ipa_hwio_def_ipa_endp_init_hol_block_en_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_endp_init_hol_block_timer_n_s { + u32 time_limit : 5; + u32 reserved0 : 3; + u32 gran_sel : 1; + u32 reserved1 : 23; +}; +union ipa_hwio_def_ipa_endp_init_hol_block_timer_n_u { + struct ipa_hwio_def_ipa_endp_init_hol_block_timer_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_endp_init_deaggr_n_s { + u32 deaggr_hdr_len : 6; + u32 syspipe_err_detection : 1; + u32 packet_offset_valid : 1; + u32 packet_offset_location : 6; + u32 ignore_min_pkt_err : 1; + u32 reserved0 : 1; + u32 max_packet_len : 16; +}; +union ipa_hwio_def_ipa_endp_init_deaggr_n_u { + struct ipa_hwio_def_ipa_endp_init_deaggr_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_endp_init_rsrc_grp_n_s { + u32 rsrc_grp : 3; + u32 reserved0 : 29; +}; +union ipa_hwio_def_ipa_endp_init_rsrc_grp_n_u { + struct ipa_hwio_def_ipa_endp_init_rsrc_grp_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_endp_init_seq_n_s { + u32 hps_seq_type : 4; + u32 dps_seq_type : 4; + u32 hps_rep_seq_type : 4; + u32 dps_rep_seq_type : 4; + u32 reserved0 : 16; +}; +union ipa_hwio_def_ipa_endp_init_seq_n_u { + struct ipa_hwio_def_ipa_endp_init_seq_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_endp_status_n_s { + u32 status_en : 1; + u32 status_endp : 5; + u32 reserved0 : 3; + u32 status_pkt_suppress : 1; + u32 reserved1 : 22; +}; +union ipa_hwio_def_ipa_endp_status_n_u { + struct ipa_hwio_def_ipa_endp_status_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_endp_filter_router_hsh_cfg_n_s { + u32 filter_hash_msk_src_id : 1; + u32 filter_hash_msk_src_ip_add : 1; + u32 filter_hash_msk_dst_ip_add : 1; + u32 filter_hash_msk_src_port : 1; + u32 filter_hash_msk_dst_port : 1; + u32 filter_hash_msk_protocol : 1; + u32 filter_hash_msk_metadata : 1; + u32 reserved0 : 9; + u32 router_hash_msk_src_id : 1; + u32 router_hash_msk_src_ip_add : 1; + u32 router_hash_msk_dst_ip_add : 1; + u32 router_hash_msk_src_port : 1; + u32 router_hash_msk_dst_port : 1; + u32 router_hash_msk_protocol : 1; + u32 router_hash_msk_metadata : 1; + u32 reserved1 : 9; +}; +union ipa_hwio_def_ipa_endp_filter_router_hsh_cfg_n_u { + struct ipa_hwio_def_ipa_endp_filter_router_hsh_cfg_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_nlo_pp_cfg1_s { + u32 nlo_ack_pp : 8; + u32 nlo_data_pp : 8; + u32 nlo_status_pp : 8; + u32 nlo_ack_max_vp : 6; + u32 reserved0 : 2; +}; +union ipa_hwio_def_ipa_nlo_pp_cfg1_u { + struct ipa_hwio_def_ipa_nlo_pp_cfg1_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_nlo_pp_cfg2_s { + u32 nlo_ack_close_padd : 8; + u32 nlo_data_close_padd : 8; + u32 nlo_ack_buffer_mode : 1; + u32 nlo_data_buffer_mode : 1; + u32 nlo_status_buffer_mode : 1; + u32 reserved0 : 13; +}; +union ipa_hwio_def_ipa_nlo_pp_cfg2_u { + struct ipa_hwio_def_ipa_nlo_pp_cfg2_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_nlo_pp_ack_limit_cfg_s { + u32 nlo_ack_lower_size : 16; + u32 nlo_ack_upper_size : 16; +}; +union ipa_hwio_def_ipa_nlo_pp_ack_limit_cfg_u { + struct ipa_hwio_def_ipa_nlo_pp_ack_limit_cfg_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_nlo_pp_data_limit_cfg_s { + u32 nlo_data_lower_size : 16; + u32 nlo_data_upper_size : 16; +}; +union ipa_hwio_def_ipa_nlo_pp_data_limit_cfg_u { + struct ipa_hwio_def_ipa_nlo_pp_data_limit_cfg_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_nlo_min_dsm_cfg_s { + u32 nlo_ack_min_dsm_len : 16; + u32 nlo_data_min_dsm_len : 16; +}; +union ipa_hwio_def_ipa_nlo_min_dsm_cfg_u { + struct ipa_hwio_def_ipa_nlo_min_dsm_cfg_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_nlo_vp_flush_req_s { + u32 vp_flush_pp_indx : 8; + u32 reserved0 : 8; + u32 vp_flush_vp_indx : 8; + u32 reserved1 : 7; + u32 vp_flush_req : 1; +}; +union ipa_hwio_def_ipa_nlo_vp_flush_req_u { + struct ipa_hwio_def_ipa_nlo_vp_flush_req_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_nlo_vp_flush_cookie_s { + u32 vp_flush_cookie : 32; +}; +union ipa_hwio_def_ipa_nlo_vp_flush_cookie_u { + struct ipa_hwio_def_ipa_nlo_vp_flush_cookie_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_nlo_vp_flush_ack_s { + u32 vp_flush_ack : 1; + u32 reserved0 : 31; +}; +union ipa_hwio_def_ipa_nlo_vp_flush_ack_u { + struct ipa_hwio_def_ipa_nlo_vp_flush_ack_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_nlo_vp_dsm_open_s { + u32 vp_dsm_open : 32; +}; +union ipa_hwio_def_ipa_nlo_vp_dsm_open_u { + struct ipa_hwio_def_ipa_nlo_vp_dsm_open_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_nlo_vp_qbap_open_s { + u32 vp_qbap_open : 32; +}; +union ipa_hwio_def_ipa_nlo_vp_qbap_open_u { + struct ipa_hwio_def_ipa_nlo_vp_qbap_open_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rsrc_mngr_db_cfg_s { + u32 rsrc_grp_sel : 3; + u32 reserved0 : 1; + u32 rsrc_type_sel : 3; + u32 reserved1 : 1; + u32 rsrc_id_sel : 6; + u32 reserved2 : 18; +}; +union ipa_hwio_def_ipa_rsrc_mngr_db_cfg_u { + struct ipa_hwio_def_ipa_rsrc_mngr_db_cfg_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rsrc_mngr_db_rsrc_read_s { + u32 rsrc_occupied : 1; + u32 rsrc_next_valid : 1; + u32 reserved0 : 2; + u32 rsrc_next_index : 6; + u32 reserved1 : 22; +}; +union ipa_hwio_def_ipa_rsrc_mngr_db_rsrc_read_u { + struct ipa_hwio_def_ipa_rsrc_mngr_db_rsrc_read_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rsrc_mngr_db_list_read_s { + u32 rsrc_list_valid : 1; + u32 rsrc_list_hold : 1; + u32 reserved0 : 2; + u32 rsrc_list_head_rsrc : 6; + u32 reserved1 : 2; + u32 rsrc_list_head_cnt : 7; + u32 reserved2 : 1; + u32 rsrc_list_entry_cnt : 7; + u32 reserved3 : 5; +}; +union ipa_hwio_def_ipa_rsrc_mngr_db_list_read_u { + struct ipa_hwio_def_ipa_rsrc_mngr_db_list_read_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_debug_data_s { + u32 debug_data : 32; +}; +union ipa_hwio_def_ipa_debug_data_u { + struct ipa_hwio_def_ipa_debug_data_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_testbus_sel_s { + u32 testbus_en : 1; + u32 reserved0 : 3; + u32 external_block_select : 8; + u32 internal_block_select : 8; + u32 pipe_select : 5; + u32 reserved1 : 7; +}; +union ipa_hwio_def_ipa_testbus_sel_u { + struct ipa_hwio_def_ipa_testbus_sel_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_step_mode_breakpoints_s { + u32 hw_en : 32; +}; +union ipa_hwio_def_ipa_step_mode_breakpoints_u { + struct ipa_hwio_def_ipa_step_mode_breakpoints_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_step_mode_status_s { + u32 hw_en : 32; +}; +union ipa_hwio_def_ipa_step_mode_status_u { + struct ipa_hwio_def_ipa_step_mode_status_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_s { + u32 reserved0 : 1; + u32 log_en : 1; + u32 reserved1 : 2; + u32 log_pipe : 5; + u32 reserved2 : 3; + u32 log_length : 8; + u32 log_reduction_en : 1; + u32 log_dpl_l2_remove_en : 1; + u32 reserved3 : 10; +}; +union ipa_hwio_def_ipa_log_u { + struct ipa_hwio_def_ipa_log_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_hw_cmd_addr_s { + u32 start_addr : 32; +}; +union ipa_hwio_def_ipa_log_buf_hw_cmd_addr_u { + struct ipa_hwio_def_ipa_log_buf_hw_cmd_addr_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_hw_cmd_addr_msb_s { + u32 start_addr : 32; +}; +union ipa_hwio_def_ipa_log_buf_hw_cmd_addr_msb_u { + struct ipa_hwio_def_ipa_log_buf_hw_cmd_addr_msb_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_hw_cmd_write_ptr_s { + u32 writr_addr : 32; +}; +union ipa_hwio_def_ipa_log_buf_hw_cmd_write_ptr_u { + struct ipa_hwio_def_ipa_log_buf_hw_cmd_write_ptr_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_hw_cmd_write_ptr_msb_s { + u32 writr_addr : 32; +}; +union ipa_hwio_def_ipa_log_buf_hw_cmd_write_ptr_msb_u { + struct ipa_hwio_def_ipa_log_buf_hw_cmd_write_ptr_msb_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_hw_cmd_cfg_s { + u32 size : 16; + u32 enable : 1; + u32 skip_ddr_dma : 1; + u32 reserved0 : 14; +}; +union ipa_hwio_def_ipa_log_buf_hw_cmd_cfg_u { + struct ipa_hwio_def_ipa_log_buf_hw_cmd_cfg_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_hw_cmd_ram_ptr_s { + u32 read_ptr : 14; + u32 reserved0 : 2; + u32 write_ptr : 14; + u32 reserved1 : 1; + u32 skip_ddr_wrap_happened : 1; +}; +union ipa_hwio_def_ipa_log_buf_hw_cmd_ram_ptr_u { + struct ipa_hwio_def_ipa_log_buf_hw_cmd_ram_ptr_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_splt_cmdq_cmd_n_s { + u32 write_cmd : 1; + u32 pop_cmd : 1; + u32 release_rd_cmd : 1; + u32 release_wr_cmd : 1; + u32 release_rd_pkt : 1; + u32 release_wr_pkt : 1; + u32 release_rd_pkt_enhanced : 1; + u32 reserved0 : 25; +}; +union ipa_hwio_def_ipa_rx_splt_cmdq_cmd_n_u { + struct ipa_hwio_def_ipa_rx_splt_cmdq_cmd_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_splt_cmdq_cfg_n_s { + u32 block_rd : 1; + u32 block_wr : 1; + u32 reserved0 : 30; +}; +union ipa_hwio_def_ipa_rx_splt_cmdq_cfg_n_u { + struct ipa_hwio_def_ipa_rx_splt_cmdq_cfg_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_splt_cmdq_data_wr_0_n_s { + u32 cmdq_packet_len_f : 16; + u32 cmdq_src_len_f : 16; +}; +union ipa_hwio_def_ipa_rx_splt_cmdq_data_wr_0_n_u { + struct ipa_hwio_def_ipa_rx_splt_cmdq_data_wr_0_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_splt_cmdq_data_wr_1_n_s { + u32 cmdq_src_pipe_f : 8; + u32 cmdq_order_f : 2; + u32 cmdq_flags_f : 6; + u32 cmdq_opcode_f : 8; + u32 cmdq_metadata_f : 8; +}; +union ipa_hwio_def_ipa_rx_splt_cmdq_data_wr_1_n_u { + struct ipa_hwio_def_ipa_rx_splt_cmdq_data_wr_1_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_splt_cmdq_data_wr_2_n_s { + u32 cmdq_addr_lsb_f : 32; +}; +union ipa_hwio_def_ipa_rx_splt_cmdq_data_wr_2_n_u { + struct ipa_hwio_def_ipa_rx_splt_cmdq_data_wr_2_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_splt_cmdq_data_wr_3_n_s { + u32 cmdq_addr_msb_f : 32; +}; +union ipa_hwio_def_ipa_rx_splt_cmdq_data_wr_3_n_u { + struct ipa_hwio_def_ipa_rx_splt_cmdq_data_wr_3_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_splt_cmdq_data_rd_0_n_s { + u32 cmdq_packet_len_f : 16; + u32 cmdq_src_len_f : 16; +}; +union ipa_hwio_def_ipa_rx_splt_cmdq_data_rd_0_n_u { + struct ipa_hwio_def_ipa_rx_splt_cmdq_data_rd_0_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_splt_cmdq_data_rd_1_n_s { + u32 cmdq_src_pipe_f : 8; + u32 cmdq_order_f : 2; + u32 cmdq_flags_f : 6; + u32 cmdq_opcode_f : 8; + u32 cmdq_metadata_f : 8; +}; +union ipa_hwio_def_ipa_rx_splt_cmdq_data_rd_1_n_u { + struct ipa_hwio_def_ipa_rx_splt_cmdq_data_rd_1_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_splt_cmdq_data_rd_2_n_s { + u32 cmdq_addr_lsb_f : 32; +}; +union ipa_hwio_def_ipa_rx_splt_cmdq_data_rd_2_n_u { + struct ipa_hwio_def_ipa_rx_splt_cmdq_data_rd_2_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_splt_cmdq_data_rd_3_n_s { + u32 cmdq_addr_msb_f : 32; +}; +union ipa_hwio_def_ipa_rx_splt_cmdq_data_rd_3_n_u { + struct ipa_hwio_def_ipa_rx_splt_cmdq_data_rd_3_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_splt_cmdq_status_n_s { + u32 status : 1; + u32 cmdq_empty : 1; + u32 cmdq_full : 1; + u32 cmdq_count : 2; + u32 cmdq_depth : 2; + u32 reserved0 : 25; +}; +union ipa_hwio_def_ipa_rx_splt_cmdq_status_n_u { + struct ipa_hwio_def_ipa_rx_splt_cmdq_status_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_tx_commander_cmdq_status_s { + u32 status : 1; + u32 cmdq_empty : 1; + u32 cmdq_full : 1; + u32 reserved0 : 29; +}; +union ipa_hwio_def_ipa_tx_commander_cmdq_status_u { + struct ipa_hwio_def_ipa_tx_commander_cmdq_status_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_hps_cmdq_cmd_s { + u32 write_cmd : 1; + u32 pop_cmd : 1; + u32 cmd_client : 3; + u32 rd_req : 1; + u32 reserved0 : 26; +}; +union ipa_hwio_def_ipa_rx_hps_cmdq_cmd_u { + struct ipa_hwio_def_ipa_rx_hps_cmdq_cmd_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_hps_cmdq_cfg_wr_s { + u32 block_wr : 5; + u32 reserved0 : 27; +}; +union ipa_hwio_def_ipa_rx_hps_cmdq_cfg_wr_u { + struct ipa_hwio_def_ipa_rx_hps_cmdq_cfg_wr_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_hps_cmdq_cfg_rd_s { + u32 block_rd : 5; + u32 reserved0 : 27; +}; +union ipa_hwio_def_ipa_rx_hps_cmdq_cfg_rd_u { + struct ipa_hwio_def_ipa_rx_hps_cmdq_cfg_rd_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_0_s { + u32 cmdq_packet_len_f : 16; + u32 cmdq_dest_len_f : 16; +}; +union ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_0_u { + struct ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_0_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_1_s { + u32 cmdq_src_pipe_f : 8; + u32 cmdq_order_f : 2; + u32 cmdq_flags_f : 6; + u32 cmdq_opcode_f : 8; + u32 cmdq_metadata_f : 8; +}; +union ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_1_u { + struct ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_1_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_2_s { + u32 cmdq_addr_lsb_f : 32; +}; +union ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_2_u { + struct ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_2_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_3_s { + u32 cmdq_addr_msb_f : 32; +}; +union ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_3_u { + struct ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_3_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_hps_cmdq_status_s { + u32 status : 1; + u32 cmdq_full : 1; + u32 cmdq_depth : 7; + u32 reserved0 : 23; +}; +union ipa_hwio_def_ipa_rx_hps_cmdq_status_u { + struct ipa_hwio_def_ipa_rx_hps_cmdq_status_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_hps_cmdq_status_empty_s { + u32 cmdq_empty : 5; + u32 reserved0 : 27; +}; +union ipa_hwio_def_ipa_rx_hps_cmdq_status_empty_u { + struct ipa_hwio_def_ipa_rx_hps_cmdq_status_empty_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_hps_cmdq_count_s { + u32 fifo_count : 7; + u32 reserved0 : 25; +}; +union ipa_hwio_def_ipa_rx_hps_cmdq_count_u { + struct ipa_hwio_def_ipa_rx_hps_cmdq_count_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_hps_clients_min_depth_0_s { + u32 client_0_min_depth : 4; + u32 reserved0 : 4; + u32 client_1_min_depth : 4; + u32 reserved1 : 4; + u32 client_2_min_depth : 4; + u32 reserved2 : 4; + u32 client_3_min_depth : 4; + u32 client_4_min_depth : 4; +}; +union ipa_hwio_def_ipa_rx_hps_clients_min_depth_0_u { + struct ipa_hwio_def_ipa_rx_hps_clients_min_depth_0_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_hps_clients_max_depth_0_s { + u32 client_0_max_depth : 4; + u32 reserved0 : 4; + u32 client_1_max_depth : 4; + u32 reserved1 : 4; + u32 client_2_max_depth : 4; + u32 reserved2 : 4; + u32 client_3_max_depth : 4; + u32 client_4_max_depth : 4; +}; +union ipa_hwio_def_ipa_rx_hps_clients_max_depth_0_u { + struct ipa_hwio_def_ipa_rx_hps_clients_max_depth_0_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_hps_dps_cmdq_cmd_s { + u32 write_cmd : 1; + u32 pop_cmd : 1; + u32 cmd_client : 5; + u32 rd_req : 1; + u32 reserved0 : 24; +}; +union ipa_hwio_def_ipa_hps_dps_cmdq_cmd_u { + struct ipa_hwio_def_ipa_hps_dps_cmdq_cmd_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_hps_dps_cmdq_data_rd_0_s { + u32 cmdq_ctx_id_f : 4; + u32 cmdq_src_id_f : 8; + u32 cmdq_src_pipe_f : 5; + u32 cmdq_opcode_f : 2; + u32 cmdq_rep_f : 1; + u32 reserved0 : 12; +}; +union ipa_hwio_def_ipa_hps_dps_cmdq_data_rd_0_u { + struct ipa_hwio_def_ipa_hps_dps_cmdq_data_rd_0_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_hps_dps_cmdq_status_s { + u32 status : 1; + u32 cmdq_full : 1; + u32 cmdq_depth : 6; + u32 reserved0 : 24; +}; +union ipa_hwio_def_ipa_hps_dps_cmdq_status_u { + struct ipa_hwio_def_ipa_hps_dps_cmdq_status_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_hps_dps_cmdq_status_empty_s { + u32 cmdq_empty : 31; + u32 reserved0 : 1; +}; +union ipa_hwio_def_ipa_hps_dps_cmdq_status_empty_u { + struct ipa_hwio_def_ipa_hps_dps_cmdq_status_empty_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_hps_dps_cmdq_count_s { + u32 fifo_count : 6; + u32 reserved0 : 26; +}; +union ipa_hwio_def_ipa_hps_dps_cmdq_count_u { + struct ipa_hwio_def_ipa_hps_dps_cmdq_count_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_dps_tx_cmdq_cmd_s { + u32 write_cmd : 1; + u32 pop_cmd : 1; + u32 cmd_client : 4; + u32 reserved0 : 1; + u32 rd_req : 1; + u32 reserved1 : 24; +}; +union ipa_hwio_def_ipa_dps_tx_cmdq_cmd_u { + struct ipa_hwio_def_ipa_dps_tx_cmdq_cmd_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_dps_tx_cmdq_data_rd_0_s { + u32 cmdq_ctx_id_f : 4; + u32 cmdq_src_id_f : 8; + u32 cmdq_src_pipe_f : 5; + u32 cmdq_opcode_f : 2; + u32 cmdq_rep_f : 1; + u32 reserved0 : 12; +}; +union ipa_hwio_def_ipa_dps_tx_cmdq_data_rd_0_u { + struct ipa_hwio_def_ipa_dps_tx_cmdq_data_rd_0_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_dps_tx_cmdq_status_s { + u32 status : 1; + u32 cmdq_full : 1; + u32 cmdq_depth : 7; + u32 reserved0 : 23; +}; +union ipa_hwio_def_ipa_dps_tx_cmdq_status_u { + struct ipa_hwio_def_ipa_dps_tx_cmdq_status_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_dps_tx_cmdq_status_empty_s { + u32 cmdq_empty : 10; + u32 reserved0 : 22; +}; +union ipa_hwio_def_ipa_dps_tx_cmdq_status_empty_u { + struct ipa_hwio_def_ipa_dps_tx_cmdq_status_empty_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_dps_tx_cmdq_count_s { + u32 fifo_count : 7; + u32 reserved0 : 25; +}; +union ipa_hwio_def_ipa_dps_tx_cmdq_count_u { + struct ipa_hwio_def_ipa_dps_tx_cmdq_count_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_hw_snif_el_en_s { + u32 bitmap : 3; + u32 reserved0 : 29; +}; +union ipa_hwio_def_ipa_log_buf_hw_snif_el_en_u { + struct ipa_hwio_def_ipa_log_buf_hw_snif_el_en_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_hw_snif_el_wr_n_rd_sel_s { + u32 bitmap : 3; + u32 reserved0 : 29; +}; +union ipa_hwio_def_ipa_log_buf_hw_snif_el_wr_n_rd_sel_u { + struct ipa_hwio_def_ipa_log_buf_hw_snif_el_wr_n_rd_sel_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_hw_snif_el_cli_mux_s { + u32 all_cli_mux_concat : 12; + u32 reserved0 : 20; +}; +union ipa_hwio_def_ipa_log_buf_hw_snif_el_cli_mux_u { + struct ipa_hwio_def_ipa_log_buf_hw_snif_el_cli_mux_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_hw_snif_el_comp_val_0_cli_n_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_hw_snif_el_comp_val_0_cli_n_u { + struct ipa_hwio_def_ipa_log_buf_hw_snif_el_comp_val_0_cli_n_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_hw_snif_el_comp_val_1_cli_n_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_hw_snif_el_comp_val_1_cli_n_u { + struct ipa_hwio_def_ipa_log_buf_hw_snif_el_comp_val_1_cli_n_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_hw_snif_el_comp_val_2_cli_n_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_hw_snif_el_comp_val_2_cli_n_u { + struct ipa_hwio_def_ipa_log_buf_hw_snif_el_comp_val_2_cli_n_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_hw_snif_el_comp_val_3_cli_n_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_hw_snif_el_comp_val_3_cli_n_u { + struct ipa_hwio_def_ipa_log_buf_hw_snif_el_comp_val_3_cli_n_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_hw_snif_el_mask_val_0_cli_n_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_hw_snif_el_mask_val_0_cli_n_u { + struct ipa_hwio_def_ipa_log_buf_hw_snif_el_mask_val_0_cli_n_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_hw_snif_el_mask_val_1_cli_n_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_hw_snif_el_mask_val_1_cli_n_u { + struct ipa_hwio_def_ipa_log_buf_hw_snif_el_mask_val_1_cli_n_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_hw_snif_el_mask_val_2_cli_n_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_hw_snif_el_mask_val_2_cli_n_u { + struct ipa_hwio_def_ipa_log_buf_hw_snif_el_mask_val_2_cli_n_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_hw_snif_el_mask_val_3_cli_n_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_hw_snif_el_mask_val_3_cli_n_u { + struct ipa_hwio_def_ipa_log_buf_hw_snif_el_mask_val_3_cli_n_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_hw_snif_legacy_rx_s { + u32 src_group_sel : 3; + u32 reserved0 : 29; +}; +union ipa_hwio_def_ipa_log_buf_hw_snif_legacy_rx_u { + struct ipa_hwio_def_ipa_log_buf_hw_snif_legacy_rx_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_ackmngr_cmdq_cmd_s { + u32 write_cmd : 1; + u32 pop_cmd : 1; + u32 cmd_client : 5; + u32 rd_req : 1; + u32 reserved0 : 24; +}; +union ipa_hwio_def_ipa_ackmngr_cmdq_cmd_u { + struct ipa_hwio_def_ipa_ackmngr_cmdq_cmd_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_ackmngr_cmdq_data_rd_s { + u32 cmdq_src_id : 8; + u32 cmdq_length : 16; + u32 cmdq_origin : 1; + u32 cmdq_sent : 1; + u32 cmdq_src_id_valid : 1; + u32 reserved0 : 5; +}; +union ipa_hwio_def_ipa_ackmngr_cmdq_data_rd_u { + struct ipa_hwio_def_ipa_ackmngr_cmdq_data_rd_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_ackmngr_cmdq_status_s { + u32 status : 1; + u32 cmdq_full : 1; + u32 cmdq_depth : 7; + u32 reserved0 : 23; +}; +union ipa_hwio_def_ipa_ackmngr_cmdq_status_u { + struct ipa_hwio_def_ipa_ackmngr_cmdq_status_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_ackmngr_cmdq_status_empty_s { + u32 cmdq_empty : 13; + u32 reserved0 : 19; +}; +union ipa_hwio_def_ipa_ackmngr_cmdq_status_empty_u { + struct ipa_hwio_def_ipa_ackmngr_cmdq_status_empty_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_ackmngr_cmdq_count_s { + u32 fifo_count : 7; + u32 reserved0 : 25; +}; +union ipa_hwio_def_ipa_ackmngr_cmdq_count_u { + struct ipa_hwio_def_ipa_ackmngr_cmdq_count_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_fifo_status_ctrl_s { + u32 ipa_gsi_fifo_status_port_sel : 5; + u32 ipa_gsi_fifo_status_en : 1; + u32 reserved0 : 26; +}; +union ipa_hwio_def_ipa_gsi_fifo_status_ctrl_u { + struct ipa_hwio_def_ipa_gsi_fifo_status_ctrl_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_tlv_fifo_status_s { + u32 fifo_wr_ptr : 8; + u32 fifo_rd_ptr : 8; + u32 fifo_rd_pub_ptr : 8; + u32 fifo_empty : 1; + u32 fifo_empty_pub : 1; + u32 fifo_almost_full : 1; + u32 fifo_full : 1; + u32 fifo_almost_full_pub : 1; + u32 fifo_full_pub : 1; + u32 fifo_head_is_bubble : 1; + u32 reserved0 : 1; +}; +union ipa_hwio_def_ipa_gsi_tlv_fifo_status_u { + struct ipa_hwio_def_ipa_gsi_tlv_fifo_status_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_aos_fifo_status_s { + u32 fifo_wr_ptr : 8; + u32 fifo_rd_ptr : 8; + u32 fifo_rd_pub_ptr : 8; + u32 fifo_empty : 1; + u32 fifo_empty_pub : 1; + u32 fifo_almost_full : 1; + u32 fifo_full : 1; + u32 fifo_almost_full_pub : 1; + u32 fifo_full_pub : 1; + u32 fifo_head_is_bubble : 1; + u32 reserved0 : 1; +}; +union ipa_hwio_def_ipa_gsi_aos_fifo_status_u { + struct ipa_hwio_def_ipa_gsi_aos_fifo_status_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_sw_comp_val_0_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_sw_comp_val_0_u { + struct ipa_hwio_def_ipa_log_buf_sw_comp_val_0_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_sw_comp_val_1_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_sw_comp_val_1_u { + struct ipa_hwio_def_ipa_log_buf_sw_comp_val_1_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_sw_comp_val_2_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_sw_comp_val_2_u { + struct ipa_hwio_def_ipa_log_buf_sw_comp_val_2_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_sw_comp_val_3_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_sw_comp_val_3_u { + struct ipa_hwio_def_ipa_log_buf_sw_comp_val_3_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_sw_comp_val_4_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_sw_comp_val_4_u { + struct ipa_hwio_def_ipa_log_buf_sw_comp_val_4_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_sw_comp_val_5_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_sw_comp_val_5_u { + struct ipa_hwio_def_ipa_log_buf_sw_comp_val_5_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_sw_comp_val_6_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_sw_comp_val_6_u { + struct ipa_hwio_def_ipa_log_buf_sw_comp_val_6_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_sw_comp_val_7_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_sw_comp_val_7_u { + struct ipa_hwio_def_ipa_log_buf_sw_comp_val_7_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_sw_mask_val_0_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_sw_mask_val_0_u { + struct ipa_hwio_def_ipa_log_buf_sw_mask_val_0_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_sw_mask_val_1_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_sw_mask_val_1_u { + struct ipa_hwio_def_ipa_log_buf_sw_mask_val_1_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_sw_mask_val_2_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_sw_mask_val_2_u { + struct ipa_hwio_def_ipa_log_buf_sw_mask_val_2_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_sw_mask_val_3_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_sw_mask_val_3_u { + struct ipa_hwio_def_ipa_log_buf_sw_mask_val_3_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_sw_mask_val_4_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_sw_mask_val_4_u { + struct ipa_hwio_def_ipa_log_buf_sw_mask_val_4_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_sw_mask_val_5_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_sw_mask_val_5_u { + struct ipa_hwio_def_ipa_log_buf_sw_mask_val_5_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_sw_mask_val_6_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_sw_mask_val_6_u { + struct ipa_hwio_def_ipa_log_buf_sw_mask_val_6_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_sw_mask_val_7_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_sw_mask_val_7_u { + struct ipa_hwio_def_ipa_log_buf_sw_mask_val_7_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_ntf_tx_cmdq_cmd_s { + u32 write_cmd : 1; + u32 pop_cmd : 1; + u32 cmd_client : 5; + u32 rd_req : 1; + u32 reserved0 : 24; +}; +union ipa_hwio_def_ipa_ntf_tx_cmdq_cmd_u { + struct ipa_hwio_def_ipa_ntf_tx_cmdq_cmd_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_ntf_tx_cmdq_data_rd_0_s { + u32 cmdq_ctx_id_f : 4; + u32 cmdq_src_id_f : 8; + u32 cmdq_src_pipe_f : 5; + u32 cmdq_opcode_f : 2; + u32 cmdq_rep_f : 1; + u32 reserved0 : 12; +}; +union ipa_hwio_def_ipa_ntf_tx_cmdq_data_rd_0_u { + struct ipa_hwio_def_ipa_ntf_tx_cmdq_data_rd_0_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_ntf_tx_cmdq_status_s { + u32 status : 1; + u32 cmdq_full : 1; + u32 cmdq_depth : 7; + u32 reserved0 : 23; +}; +union ipa_hwio_def_ipa_ntf_tx_cmdq_status_u { + struct ipa_hwio_def_ipa_ntf_tx_cmdq_status_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_ntf_tx_cmdq_status_empty_s { + u32 cmdq_empty : 31; + u32 reserved0 : 1; +}; +union ipa_hwio_def_ipa_ntf_tx_cmdq_status_empty_u { + struct ipa_hwio_def_ipa_ntf_tx_cmdq_status_empty_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_ntf_tx_cmdq_count_s { + u32 fifo_count : 7; + u32 reserved0 : 25; +}; +union ipa_hwio_def_ipa_ntf_tx_cmdq_count_u { + struct ipa_hwio_def_ipa_ntf_tx_cmdq_count_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_cmd_s { + u32 write_cmd : 1; + u32 pop_cmd : 1; + u32 cmd_client : 5; + u32 rd_req : 1; + u32 reserved0 : 24; +}; +union ipa_hwio_def_ipa_prod_ackmngr_cmdq_cmd_u { + struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_cmd_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_data_rd_s { + u32 cmdq_src_id : 8; + u32 cmdq_length : 16; + u32 cmdq_origin : 1; + u32 cmdq_sent : 1; + u32 cmdq_src_id_valid : 1; + u32 cmdq_userdata : 5; +}; +union ipa_hwio_def_ipa_prod_ackmngr_cmdq_data_rd_u { + struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_data_rd_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_status_s { + u32 status : 1; + u32 cmdq_full : 1; + u32 cmdq_depth : 7; + u32 reserved0 : 23; +}; +union ipa_hwio_def_ipa_prod_ackmngr_cmdq_status_u { + struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_status_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_status_empty_s { + u32 cmdq_empty : 31; + u32 reserved0 : 1; +}; +union ipa_hwio_def_ipa_prod_ackmngr_cmdq_status_empty_u { + struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_status_empty_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_count_s { + u32 fifo_count : 7; + u32 reserved0 : 25; +}; +union ipa_hwio_def_ipa_prod_ackmngr_cmdq_count_u { + struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_count_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_spare_reg_1_s { + u32 spare_bit0 : 1; + u32 spare_bit1 : 1; + u32 genqmb_aooowr : 1; + u32 spare_bit3 : 1; + u32 spare_bit4 : 1; + u32 acl_inorder_multi_disable : 1; + u32 acl_dispatcher_frag_notif_check_disable : 1; + u32 acl_dispatcher_frag_notif_check_each_cmd_disable : 1; + u32 spare_bit8 : 1; + u32 acl_dispatcher_frag_notif_check_notif_mid_disable : 1; + u32 acl_dispatcher_pkt_check_disable : 1; + u32 tx_gives_sspnd_ack_on_open_aggr_frame : 1; + u32 spare_bit12 : 1; + u32 tx_block_aggr_query_on_holb_packet : 1; + u32 frag_mngr_fairness_eviction_on_constructing : 1; + u32 rx_cmdq_splitter_cmdq_pending_mux_disable : 1; + u32 qmb_ram_rd_cache_disable : 1; + u32 rx_stall_on_mbim_deaggr_error : 1; + u32 rx_stall_on_gen_deaggr_error : 1; + u32 spare_bit19 : 1; + u32 revert_warb_fix : 1; + u32 gsi_if_out_of_buf_stop_reset_mask_enable : 1; + u32 bam_idle_in_ipa_misc_cgc_en : 1; + u32 spare_bit23 : 1; + u32 spare_bit24 : 1; + u32 spare_bit25 : 1; + u32 ram_slaveway_access_protection_disable : 1; + u32 dcph_ram_rd_prefetch_disable : 1; + u32 warb_force_arb_round_finish_special_disable : 1; + u32 spare_ackinj_pipe8_mask_enable : 1; + u32 spare_bit30 : 1; + u32 spare_bit31 : 1; +}; +union ipa_hwio_def_ipa_spare_reg_1_u { + struct ipa_hwio_def_ipa_spare_reg_1_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_spare_reg_2_s { + u32 tx_bresp_inj_with_flop : 1; + u32 cmdq_split_not_wait_data_desc_prior_hdr_push : 1; + u32 spare_bits : 30; +}; +union ipa_hwio_def_ipa_spare_reg_2_u { + struct ipa_hwio_def_ipa_spare_reg_2_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_endp_gsi_cfg1_n_s { + u32 reserved0 : 16; + u32 endp_en : 1; + u32 reserved1 : 14; + u32 init_endp : 1; +}; +union ipa_hwio_def_ipa_endp_gsi_cfg1_n_u { + struct ipa_hwio_def_ipa_endp_gsi_cfg1_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_endp_gsi_cfg_tlv_n_s { + u32 fifo_base_addr : 16; + u32 fifo_size : 8; + u32 reserved0 : 8; +}; +union ipa_hwio_def_ipa_endp_gsi_cfg_tlv_n_u { + struct ipa_hwio_def_ipa_endp_gsi_cfg_tlv_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_endp_gsi_cfg_aos_n_s { + u32 fifo_base_addr : 16; + u32 fifo_size : 8; + u32 reserved0 : 8; +}; +union ipa_hwio_def_ipa_endp_gsi_cfg_aos_n_u { + struct ipa_hwio_def_ipa_endp_gsi_cfg_aos_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_ctxh_ctrl_s { + u32 ctxh_lock_id : 4; + u32 reserved0 : 27; + u32 ctxh_lock : 1; +}; +union ipa_hwio_def_ipa_ctxh_ctrl_u { + struct ipa_hwio_def_ipa_ctxh_ctrl_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_irq_stts_ee_n_s { + u32 bad_snoc_access_irq : 1; + u32 reserved0 : 1; + u32 uc_irq_0 : 1; + u32 uc_irq_1 : 1; + u32 uc_irq_2 : 1; + u32 uc_irq_3 : 1; + u32 uc_in_q_not_empty_irq : 1; + u32 uc_rx_cmd_q_not_full_irq : 1; + u32 proc_to_uc_ack_q_not_empty_irq : 1; + u32 rx_err_irq : 1; + u32 deaggr_err_irq : 1; + u32 tx_err_irq : 1; + u32 step_mode_irq : 1; + u32 proc_err_irq : 1; + u32 tx_suspend_irq : 1; + u32 tx_holb_drop_irq : 1; + u32 bam_gsi_idle_irq : 1; + u32 pipe_yellow_marker_below_irq : 1; + u32 pipe_red_marker_below_irq : 1; + u32 pipe_yellow_marker_above_irq : 1; + u32 pipe_red_marker_above_irq : 1; + u32 ucp_irq : 1; + u32 reserved1 : 1; + u32 gsi_ee_irq : 1; + u32 gsi_ipa_if_tlv_rcvd_irq : 1; + u32 gsi_uc_irq : 1; + u32 tlv_len_min_dsm_irq : 1; + u32 reserved2 : 5; +}; +union ipa_hwio_def_ipa_irq_stts_ee_n_u { + struct ipa_hwio_def_ipa_irq_stts_ee_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_irq_en_ee_n_s { + u32 bad_snoc_access_irq_en : 1; + u32 reserved0 : 1; + u32 uc_irq_0_irq_en : 1; + u32 uc_irq_1_irq_en : 1; + u32 uc_irq_2_irq_en : 1; + u32 uc_irq_3_irq_en : 1; + u32 uc_in_q_not_empty_irq_en : 1; + u32 uc_rx_cmd_q_not_full_irq_en : 1; + u32 proc_to_uc_ack_q_not_empty_irq_en : 1; + u32 rx_err_irq_en : 1; + u32 deaggr_err_irq_en : 1; + u32 tx_err_irq_en : 1; + u32 step_mode_irq_en : 1; + u32 proc_err_irq_en : 1; + u32 tx_suspend_irq_en : 1; + u32 tx_holb_drop_irq_en : 1; + u32 bam_gsi_idle_irq_en : 1; + u32 pipe_yellow_marker_below_irq_en : 1; + u32 pipe_red_marker_below_irq_en : 1; + u32 pipe_yellow_marker_above_irq_en : 1; + u32 pipe_red_marker_above_irq_en : 1; + u32 ucp_irq_en : 1; + u32 reserved1 : 1; + u32 gsi_ee_irq_en : 1; + u32 gsi_ipa_if_tlv_rcvd_irq_en : 1; + u32 gsi_uc_irq_en : 1; + u32 tlv_len_min_dsm_irq_en : 1; + u32 reserved2 : 5; +}; +union ipa_hwio_def_ipa_irq_en_ee_n_u { + struct ipa_hwio_def_ipa_irq_en_ee_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_snoc_fec_ee_n_s { + u32 client : 8; + u32 qmb_index : 1; + u32 reserved0 : 3; + u32 tid : 4; + u32 reserved1 : 15; + u32 read_not_write : 1; +}; +union ipa_hwio_def_ipa_snoc_fec_ee_n_u { + struct ipa_hwio_def_ipa_snoc_fec_ee_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_fec_addr_ee_n_s { + u32 addr : 32; +}; +union ipa_hwio_def_ipa_fec_addr_ee_n_u { + struct ipa_hwio_def_ipa_fec_addr_ee_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_fec_attr_ee_n_s { + u32 opcode : 6; + u32 error_info : 26; +}; +union ipa_hwio_def_ipa_fec_attr_ee_n_u { + struct ipa_hwio_def_ipa_fec_attr_ee_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_suspend_irq_info_ee_n_s { + u32 endpoints : 31; + u32 reserved0 : 1; +}; +union ipa_hwio_def_ipa_suspend_irq_info_ee_n_u { + struct ipa_hwio_def_ipa_suspend_irq_info_ee_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_suspend_irq_en_ee_n_s { + u32 endpoints : 31; + u32 reserved0 : 1; +}; +union ipa_hwio_def_ipa_suspend_irq_en_ee_n_u { + struct ipa_hwio_def_ipa_suspend_irq_en_ee_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_holb_drop_irq_info_ee_n_s { + u32 reserved0 : 13; + u32 endpoints : 18; + u32 reserved1 : 1; +}; +union ipa_hwio_def_ipa_holb_drop_irq_info_ee_n_u { + struct ipa_hwio_def_ipa_holb_drop_irq_info_ee_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_status_addr_s { + u32 start_addr : 32; +}; +union ipa_hwio_def_ipa_log_buf_status_addr_u { + struct ipa_hwio_def_ipa_log_buf_status_addr_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_status_addr_msb_s { + u32 start_addr : 32; +}; +union ipa_hwio_def_ipa_log_buf_status_addr_msb_u { + struct ipa_hwio_def_ipa_log_buf_status_addr_msb_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_status_write_ptr_s { + u32 write_addr : 32; +}; +union ipa_hwio_def_ipa_log_buf_status_write_ptr_u { + struct ipa_hwio_def_ipa_log_buf_status_write_ptr_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_status_write_ptr_msb_s { + u32 write_addr : 32; +}; +union ipa_hwio_def_ipa_log_buf_status_write_ptr_msb_u { + struct ipa_hwio_def_ipa_log_buf_status_write_ptr_msb_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_status_cfg_s { + u32 size : 16; + u32 enable : 1; + u32 reserved0 : 15; +}; +union ipa_hwio_def_ipa_log_buf_status_cfg_u { + struct ipa_hwio_def_ipa_log_buf_status_cfg_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_status_ram_ptr_s { + u32 read_ptr : 16; + u32 write_ptr : 16; +}; +union ipa_hwio_def_ipa_log_buf_status_ram_ptr_u { + struct ipa_hwio_def_ipa_log_buf_status_ram_ptr_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_uc_qmb_sys_addr_s { + u32 addr : 32; +}; +union ipa_hwio_def_ipa_uc_qmb_sys_addr_u { + struct ipa_hwio_def_ipa_uc_qmb_sys_addr_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_uc_qmb_sys_addr_msb_s { + u32 addr_msb : 32; +}; +union ipa_hwio_def_ipa_uc_qmb_sys_addr_msb_u { + struct ipa_hwio_def_ipa_uc_qmb_sys_addr_msb_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_uc_qmb_local_addr_s { + u32 addr : 18; + u32 reserved0 : 14; +}; +union ipa_hwio_def_ipa_uc_qmb_local_addr_u { + struct ipa_hwio_def_ipa_uc_qmb_local_addr_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_uc_qmb_length_s { + u32 length : 7; + u32 reserved0 : 25; +}; +union ipa_hwio_def_ipa_uc_qmb_length_u { + struct ipa_hwio_def_ipa_uc_qmb_length_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_uc_qmb_trigger_s { + u32 direction : 1; + u32 reserved0 : 3; + u32 posting : 2; + u32 reserved1 : 26; +}; +union ipa_hwio_def_ipa_uc_qmb_trigger_u { + struct ipa_hwio_def_ipa_uc_qmb_trigger_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_uc_qmb_pending_tid_s { + u32 tid : 6; + u32 reserved0 : 2; + u32 error_bus : 1; + u32 reserved1 : 3; + u32 error_max_os : 1; + u32 reserved2 : 3; + u32 error_max_comp : 1; + u32 reserved3 : 3; + u32 error_security : 1; + u32 reserved4 : 11; +}; +union ipa_hwio_def_ipa_uc_qmb_pending_tid_u { + struct ipa_hwio_def_ipa_uc_qmb_pending_tid_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_uc_qmb_completed_rd_fifo_peek_s { + u32 tid : 6; + u32 reserved0 : 2; + u32 error : 1; + u32 reserved1 : 3; + u32 valid : 1; + u32 reserved2 : 19; +}; +union ipa_hwio_def_ipa_uc_qmb_completed_rd_fifo_peek_u { + struct ipa_hwio_def_ipa_uc_qmb_completed_rd_fifo_peek_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_uc_qmb_completed_wr_fifo_peek_s { + u32 tid : 6; + u32 reserved0 : 2; + u32 error : 1; + u32 reserved1 : 3; + u32 valid : 1; + u32 reserved2 : 19; +}; +union ipa_hwio_def_ipa_uc_qmb_completed_wr_fifo_peek_u { + struct ipa_hwio_def_ipa_uc_qmb_completed_wr_fifo_peek_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_uc_qmb_misc_s { + u32 user : 10; + u32 reserved0 : 2; + u32 rd_priority : 2; + u32 reserved1 : 2; + u32 wr_priority : 2; + u32 reserved2 : 2; + u32 ooord : 1; + u32 reserved3 : 3; + u32 ooowr : 1; + u32 reserved4 : 3; + u32 swap : 1; + u32 irq_coal : 1; + u32 posted_stall : 1; + u32 qmb_hready_bcr : 1; +}; +union ipa_hwio_def_ipa_uc_qmb_misc_u { + struct ipa_hwio_def_ipa_uc_qmb_misc_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_uc_qmb_status_s { + u32 max_outstanding_rd : 4; + u32 outstanding_rd_cnt : 4; + u32 completed_rd_cnt : 4; + u32 completed_rd_fifo_full : 1; + u32 reserved0 : 3; + u32 max_outstanding_wr : 4; + u32 outstanding_wr_cnt : 4; + u32 completed_wr_cnt : 4; + u32 completed_wr_fifo_full : 1; + u32 reserved1 : 3; +}; +union ipa_hwio_def_ipa_uc_qmb_status_u { + struct ipa_hwio_def_ipa_uc_qmb_status_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_uc_qmb_bus_attrib_s { + u32 memtype : 3; + u32 reserved0 : 1; + u32 noallocate : 1; + u32 reserved1 : 3; + u32 innershared : 1; + u32 reserved2 : 3; + u32 shared : 1; + u32 reserved3 : 19; +}; +union ipa_hwio_def_ipa_uc_qmb_bus_attrib_u { + struct ipa_hwio_def_ipa_uc_qmb_bus_attrib_s def; + u32 value; +}; +#endif diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.5/ipa_pkt_cntxt.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.5/ipa_pkt_cntxt.h new file mode 100644 index 0000000000..ab31a4f412 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.5/ipa_pkt_cntxt.h @@ -0,0 +1,183 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ +#if !defined(_IPA_PKT_CNTXT_H_) +#define _IPA_PKT_CNTXT_H_ + +#define IPA_HW_PKT_CTNTX_MAX 0x10 +#define IPA_HW_NUM_SAVE_PKT_CTNTX 0x8 +#define IPA_HW_PKT_CTNTX_START_ADDR 0xE434CA00 +#define IPA_HW_PKT_CTNTX_SIZE (sizeof(ipa_pkt_ctntx_opcode_state_s) + \ + sizeof(ipa_pkt_ctntx_u)) + +/* + * Packet Context States + */ +enum ipa_hw_pkt_cntxt_state_e { + IPA_HW_PKT_CNTXT_STATE_HFETCHER_INIT = 1, + IPA_HW_PKT_CNTXT_STATE_HFETCHER_DMAR, + IPA_HW_PKT_CNTXT_STATE_HFETCHER_DMAR_REP, + IPA_HW_PKT_CNTXT_STATE_H_DCPH, + IPA_HW_PKT_CNTXT_STATE_PKT_PARSER, + IPA_HW_PKT_CNTXT_STATE_FILTER_NAT, + IPA_HW_PKT_CNTXT_STATE_ROUTER, + IPA_HW_PKT_CNTXT_STATE_HDRI, + IPA_HW_PKT_CNTXT_STATE_UCP, + IPA_HW_PKT_CNTXT_STATE_ENQUEUER, + IPA_HW_PKT_CNTXT_STATE_DFETCHER, + IPA_HW_PKT_CNTXT_STATE_D_DCPH, + IPA_HW_PKT_CNTXT_STATE_DISPATCHER, + IPA_HW_PKT_CNTXT_STATE_TX, + IPA_HW_PKT_CNTXT_STATE_TX_ZLT, + IPA_HW_PKT_CNTXT_STATE_DFETCHER_DMAR, + IPA_HW_PKT_CNTXT_STATE_DCMP, +}; + +/* + * Packet Context fields as received from VI/Design + */ +struct ipa_pkt_ctntx_s { + u64 opcode : 8; + u64 state : 5; + u64 not_used_1 : 2; + u64 tx_pkt_dma_done : 1; + u64 exc_deagg : 1; + u64 exc_pkt_version : 1; + u64 exc_pkt_len : 1; + u64 exc_threshold : 1; + u64 exc_sw : 1; + u64 exc_nat : 1; + u64 exc_frag_miss : 1; + u64 filter_bypass : 1; + u64 router_bypass : 1; + u64 nat_bypass : 1; + u64 hdri_bypass : 1; + u64 dcph_bypass : 1; + u64 security_credentials_select : 1; + u64 pkt_2nd_pass : 1; + u64 xlat_bypass : 1; + u64 dcph_valid : 1; + u64 ucp_on : 1; + u64 replication : 1; + u64 src_status_en : 1; + u64 dest_status_en : 1; + u64 frag_status_en : 1; + u64 eot_dest : 1; + u64 eot_notif : 1; + u64 prev_eot_dest : 1; + u64 src_hdr_len : 8; + u64 tx_valid_sectors : 8; + u64 rx_flags : 8; + u64 rx_packet_length : 16; + u64 revised_packet_length : 16; + u64 frag_en : 1; + u64 frag_bypass : 1; + u64 frag_process : 1; + u64 notif_pipe : 5; + u64 src_id : 8; + u64 tx_pkt_transferred : 1; + u64 src_pipe : 5; + u64 dest_pipe : 5; + u64 frag_pipe : 5; + u64 ihl_offset : 8; + u64 protocol : 8; + u64 tos : 8; + u64 id : 16; + u64 v6_reserved : 4; + u64 ff : 1; + u64 mf : 1; + u64 pkt_israg : 1; + u64 tx_holb_timer_overflow : 1; + u64 tx_holb_timer_running : 1; + u64 trnseq_0 : 3; + u64 trnseq_1 : 3; + u64 trnseq_2 : 3; + u64 trnseq_3 : 3; + u64 trnseq_4 : 3; + u64 trnseq_ex_length : 8; + u64 trnseq_4_length : 8; + u64 trnseq_4_offset : 8; + u64 dps_tx_pop_cnt : 2; + u64 dps_tx_push_cnt : 2; + u64 vol_ic_dcph_cfg : 1; + u64 vol_ic_tag_stts : 1; + u64 vol_ic_pxkt_init_e : 1; + u64 vol_ic_pkt_init : 1; + u64 tx_holb_counter : 32; + u64 trnseq_0_length : 8; + u64 trnseq_0_offset : 8; + u64 trnseq_1_length : 8; + u64 trnseq_1_offset : 8; + u64 trnseq_2_length : 8; + u64 trnseq_2_offset : 8; + u64 trnseq_3_length : 8; + u64 trnseq_3_offset : 8; + u64 dmar_valid_length : 16; + u64 dcph_valid_length : 16; + u64 frag_hdr_offset : 9; + u64 ip_payload_offset : 9; + u64 frag_rule : 4; + u64 frag_table : 1; + u64 frag_hit : 1; + u64 data_cmdq_ptr : 8; + u64 filter_result : 6; + u64 router_result : 6; + u64 nat_result : 6; + u64 hdri_result : 6; + u64 dcph_result : 6; + u64 dcph_result_valid : 1; + u32 not_used_2 : 4; + u64 tx_pkt_suspended : 1; + u64 tx_pkt_dropped : 1; + u32 not_used_3 : 3; + u64 metadata_valid : 1; + u64 metadata_type : 4; + u64 ul_cs_start_diff : 9; + u64 cs_disable_trlr_vld_bit : 1; + u64 cs_required : 1; + u64 dest_hdr_len : 8; + u64 fr_l : 1; + u64 fl_h : 1; + u64 fr_g : 1; + u64 fr_ret : 1; + u64 fr_rule_id : 10; + u64 rt_l : 1; + u64 rt_h : 1; + u64 rtng_tbl_index : 5; + u64 rt_match : 1; + u64 rt_rule_id : 10; + u64 nat_tbl_index : 13; + u64 nat_type : 2; + u64 hdr_l : 1; + u64 header_offset : 10; + u64 not_used_4 : 1; + u64 filter_result_valid : 1; + u64 router_result_valid : 1; + u64 nat_result_valid : 1; + u64 hdri_result_valid : 1; + u64 not_used_5 : 1; + u64 stream_id : 8; + u64 not_used_6 : 6; + u64 dcph_context_index : 2; + u64 dcph_cfg_size : 16; + u64 dcph_cfg_count : 32; + u64 tag_info : 48; + u64 ucp_cmd_id : 16; + u64 metadata : 32; + u64 ucp_cmd_params : 32; + u64 nat_ip_address : 32; + u64 nat_ip_cs_diff : 16; + u64 frag_dest_pipe : 5; + u64 frag_nat_type : 2; + u64 fragr_ret : 1; + u64 frag_protocol : 8; + u64 src_ip_address : 32; + u64 dest_ip_address : 32; + u64 not_used_7 : 37; + u64 frag_hdr_l : 1; + u64 frag_header_offset : 10; + u64 frag_id : 16; +} __packed; + +#endif /* #if !defined(_IPA_PKT_CNTXT_H_) */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.5/ipa_reg_dump.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.5/ipa_reg_dump.c new file mode 100644 index 0000000000..cd28af828f --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.5/ipa_reg_dump.c @@ -0,0 +1,2041 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ +#include "ipa_reg_dump.h" +#include "ipa_access_control.h" +#include + +/* Total size required for test bus */ +#define IPA_MEM_OVERLAY_SIZE 0x66000 + +#define CONFIG_IPA3_REGDUMP_NUM_EXTRA_ENDP_REGS 0 + +/* + * The following structure contains a hierarchy of structures that + * ultimately leads to a series of leafs. The leafs are structures + * containing detailed, bit level, register definitions. + */ +static struct regs_save_hierarchy_s ipa_reg_save; + +static unsigned int ipa_testbus_mem[IPA_MEM_OVERLAY_SIZE]; + +/* + * The following data structure contains a list of the registers + * (whose data are to be copied) and the locations (within + * ipa_reg_save above) into which the registers' values need to be + * copied. + */ +static struct map_src_dst_addr_s ipa_regs_to_save_array[] = { + /* + * ===================================================================== + * IPA register definitions begin here... + * ===================================================================== + */ + + /* IPA General Registers */ + GEN_SRC_DST_ADDR_MAP(IPA_STATE, + ipa.gen, + ipa_state), +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + GEN_SRC_DST_ADDR_MAP(IPA_STATE_RX_ACTIVE, + ipa.gen, + ipa_state_rx_active), +#else + GEN_SRC_DST_ADDR_MAP_ARR(IPA_STATE_RX_ACTIVE_n, + ipa.gen, + ipa_state_rx_active_n), +#endif + GEN_SRC_DST_ADDR_MAP(IPA_STATE_TX_WRAPPER, + ipa.gen, + ipa_state_tx_wrapper), + GEN_SRC_DST_ADDR_MAP(IPA_STATE_TX0, + ipa.gen, + ipa_state_tx0), +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + GEN_SRC_DST_ADDR_MAP(IPA_STATE_TX0_MISC, + ipa.gen, + ipa_state_tx0_misc), +#endif + GEN_SRC_DST_ADDR_MAP(IPA_STATE_TX1, + ipa.gen, + ipa_state_tx1), +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + GEN_SRC_DST_ADDR_MAP(IPA_STATE_AGGR_ACTIVE, + ipa.gen, + ipa_state_aggr_active), +#else + GEN_SRC_DST_ADDR_MAP(IPA_STATE_TX1_MISC, + ipa.gen, + ipa_state_tx1_misc), + GEN_SRC_DST_ADDR_MAP_ARR(IPA_STATE_AGGR_ACTIVE_n, + ipa.gen, + ipa_state_aggr_active_n), +#endif + GEN_SRC_DST_ADDR_MAP(IPA_STATE_DFETCHER, + ipa.gen, + ipa_state_dfetcher), + GEN_SRC_DST_ADDR_MAP(IPA_STATE_FETCHER_MASK_0, + ipa.gen, + ipa_state_fetcher_mask_0), + GEN_SRC_DST_ADDR_MAP(IPA_STATE_FETCHER_MASK_1, + ipa.gen, + ipa_state_fetcher_mask_1), +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + GEN_SRC_DST_ADDR_MAP(IPA_STATE_FETCHER_MASK_2, + ipa.gen, + ipa_state_fetcher_mask_2), +#endif + GEN_SRC_DST_ADDR_MAP(IPA_STATE_GSI_AOS, + ipa.gen, + ipa_state_gsi_aos), + GEN_SRC_DST_ADDR_MAP(IPA_STATE_GSI_IF, + ipa.gen, + ipa_state_gsi_if), +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + GEN_SRC_DST_ADDR_MAP(IPA_STATE_GSI_SKIP, + ipa.gen, + ipa_state_gsi_skip), + GEN_SRC_DST_ADDR_MAP(IPA_STATE_GSI_TLV, + ipa.gen, + ipa_state_gsi_tlv), +#endif + GEN_SRC_DST_ADDR_MAP(IPA_DPL_TIMER_LSB, + ipa.gen, + ipa_dpl_timer_lsb), + GEN_SRC_DST_ADDR_MAP(IPA_DPL_TIMER_MSB, + ipa.gen, + ipa_dpl_timer_msb), + GEN_SRC_DST_ADDR_MAP(IPA_PROC_IPH_CFG, + ipa.gen, + ipa_proc_iph_cfg), + GEN_SRC_DST_ADDR_MAP(IPA_ROUTE, + ipa.gen, + ipa_route), + GEN_SRC_DST_ADDR_MAP(IPA_SPARE_REG_1, + ipa.gen, + ipa_spare_reg_1), +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + GEN_SRC_DST_ADDR_MAP(IPA_SPARE_REG_2, + ipa.gen, + ipa_spare_reg_2), +#endif + GEN_SRC_DST_ADDR_MAP(IPA_LOG, + ipa.gen, + ipa_log), +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + GEN_SRC_DST_ADDR_MAP(IPA_LOG_BUF_STATUS_CFG, + ipa.gen, + ipa_log_buf_status_cfg), + GEN_SRC_DST_ADDR_MAP(IPA_LOG_BUF_STATUS_ADDR, + ipa.gen, + ipa_log_buf_status_addr), + GEN_SRC_DST_ADDR_MAP(IPA_LOG_BUF_STATUS_WRITE_PTR, + ipa.gen, + ipa_log_buf_status_write_ptr), + GEN_SRC_DST_ADDR_MAP(IPA_LOG_BUF_STATUS_RAM_PTR, + ipa.gen, + ipa_log_buf_status_ram_ptr), +#endif + GEN_SRC_DST_ADDR_MAP(IPA_LOG_BUF_HW_CMD_CFG, + ipa.gen, + ipa_log_buf_hw_cmd_cfg), + GEN_SRC_DST_ADDR_MAP(IPA_LOG_BUF_HW_CMD_ADDR, + ipa.gen, + ipa_log_buf_hw_cmd_addr), + GEN_SRC_DST_ADDR_MAP(IPA_LOG_BUF_HW_CMD_WRITE_PTR, + ipa.gen, + ipa_log_buf_hw_cmd_write_ptr), + GEN_SRC_DST_ADDR_MAP(IPA_LOG_BUF_HW_CMD_RAM_PTR, + ipa.gen, + ipa_log_buf_hw_cmd_ram_ptr), + GEN_SRC_DST_ADDR_MAP(IPA_STATE_DPL_FIFO, + ipa.gen, + ipa_state_dpl_fifo), + GEN_SRC_DST_ADDR_MAP(IPA_COMP_HW_VERSION, + ipa.gen, + ipa_comp_hw_version), +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + GEN_SRC_DST_ADDR_MAP(IPA_FILT_ROUT_HASH_EN, + ipa.gen, + ipa_filt_rout_hash_en), + GEN_SRC_DST_ADDR_MAP(IPA_FILT_ROUT_HASH_FLUSH, + ipa.gen, + ipa_filt_rout_hash_flush), +#else + GEN_SRC_DST_ADDR_MAP(IPA_FILT_ROUT_CACHE_CFG, + ipa.gen, + ipa_filt_rout_cache_cfg), + GEN_SRC_DST_ADDR_MAP(IPA_FILT_ROUT_CACHE_FLUSH, + ipa.gen, + ipa_filt_rout_cache_flush), +#endif + GEN_SRC_DST_ADDR_MAP(IPA_STATE_FETCHER, + ipa.gen, + ipa_state_fetcher), + GEN_SRC_DST_ADDR_MAP(IPA_IPV4_FILTER_INIT_VALUES, + ipa.gen, + ipa_ipv4_filter_init_values), + GEN_SRC_DST_ADDR_MAP(IPA_IPV6_FILTER_INIT_VALUES, + ipa.gen, + ipa_ipv6_filter_init_values), + GEN_SRC_DST_ADDR_MAP(IPA_IPV4_ROUTE_INIT_VALUES, + ipa.gen, + ipa_ipv4_route_init_values), + GEN_SRC_DST_ADDR_MAP(IPA_IPV6_ROUTE_INIT_VALUES, + ipa.gen, + ipa_ipv6_route_init_values), +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + GEN_SRC_DST_ADDR_MAP(IPA_BAM_ACTIVATED_PORTS, + ipa.gen, + ipa_bam_activated_ports), +#else + GEN_SRC_DST_ADDR_MAP_ARR(IPA_BAM_ACTIVATED_PORTS_n, + ipa.gen, + ipa_bam_activated_ports_n), +#endif + GEN_SRC_DST_ADDR_MAP(IPA_TX_COMMANDER_CMDQ_STATUS, + ipa.gen, + ipa_tx_commander_cmdq_status), + GEN_SRC_DST_ADDR_MAP(IPA_LOG_BUF_HW_SNIF_EL_EN, + ipa.gen, + ipa_log_buf_hw_snif_el_en), + GEN_SRC_DST_ADDR_MAP(IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL, + ipa.gen, + ipa_log_buf_hw_snif_el_wr_n_rd_sel), + GEN_SRC_DST_ADDR_MAP(IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX, + ipa.gen, + ipa_log_buf_hw_snif_el_cli_mux), +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + GEN_SRC_DST_ADDR_MAP(IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL, + ipa.gen, + ipa_log_buf_hw_cmd_noc_master_sel), +#endif + GEN_SRC_DST_ADDR_MAP(IPA_STATE_ACL, + ipa.gen, + ipa_state_acl), + GEN_SRC_DST_ADDR_MAP(IPA_SYS_PKT_PROC_CNTXT_BASE, + ipa.gen, + ipa_sys_pkt_proc_cntxt_base), + GEN_SRC_DST_ADDR_MAP(IPA_SYS_PKT_PROC_CNTXT_BASE_MSB, + ipa.gen, + ipa_sys_pkt_proc_cntxt_base_msb), + GEN_SRC_DST_ADDR_MAP(IPA_LOCAL_PKT_PROC_CNTXT_BASE, + ipa.gen, + ipa_local_pkt_proc_cntxt_base), + GEN_SRC_DST_ADDR_MAP(IPA_RSRC_GRP_CFG, + ipa.gen, + ipa_rsrc_grp_cfg), +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + GEN_SRC_DST_ADDR_MAP(IPA_PIPELINE_DISABLE, + ipa.gen, + ipa_pipeline_disable), +#endif + GEN_SRC_DST_ADDR_MAP(IPA_COMP_CFG, + ipa.gen, + ipa_comp_cfg), + GEN_SRC_DST_ADDR_MAP(IPA_STATE_NLO_AGGR, + ipa.gen, + ipa_state_nlo_aggr), +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + GEN_SRC_DST_ADDR_MAP(IPA_STATE_COAL_MASTER, + ipa.gen, + ipa_state_coal_master), + GEN_SRC_DST_ADDR_MAP(IPA_STATE_COAL_MASTER_1, + ipa.gen, + ipa_state_coal_master_1), + GEN_SRC_DST_ADDR_MAP(IPA_COAL_EVICT_LRU, + ipa.gen, + ipa_coal_evict_lru), + GEN_SRC_DST_ADDR_MAP(IPA_COAL_QMAP_CFG, + ipa.gen, + ipa_coal_qmap_cfg), + GEN_SRC_DST_ADDR_MAP(IPA_TAG_TIMER, + ipa.gen, + ipa_tag_timer), +#endif + GEN_SRC_DST_ADDR_MAP(IPA_NLO_PP_CFG1, + ipa.gen, + ipa_nlo_pp_cfg1), + GEN_SRC_DST_ADDR_MAP(IPA_NLO_PP_CFG2, + ipa.gen, + ipa_nlo_pp_cfg2), +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + GEN_SRC_DST_ADDR_MAP(IPA_NLO_PP_ACK_LIMIT_CFG, + ipa.gen, + ipa_nlo_pp_ack_limit_cfg), + GEN_SRC_DST_ADDR_MAP(IPA_NLO_PP_DATA_LIMIT_CFG, + ipa.gen, + ipa_nlo_pp_data_limit_cfg), +#endif + GEN_SRC_DST_ADDR_MAP(IPA_NLO_MIN_DSM_CFG, + ipa.gen, + ipa_nlo_min_dsm_cfg), +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + GEN_SRC_DST_ADDR_MAP_ARR(IPA_NLO_VP_AGGR_CFG_LSB_n, + ipa.gen, + ipa_nlo_vp_aggr_cfg_lsb_n), + GEN_SRC_DST_ADDR_MAP_ARR(IPA_NLO_VP_LIMIT_CFG_n, + ipa.gen, + ipa_nlo_vp_limit_cfg_n), +#endif + GEN_SRC_DST_ADDR_MAP(IPA_NLO_VP_FLUSH_REQ, + ipa.gen, + ipa_nlo_vp_flush_req), + GEN_SRC_DST_ADDR_MAP(IPA_NLO_VP_FLUSH_COOKIE, + ipa.gen, + ipa_nlo_vp_flush_cookie), + GEN_SRC_DST_ADDR_MAP(IPA_NLO_VP_FLUSH_ACK, + ipa.gen, + ipa_nlo_vp_flush_ack), + GEN_SRC_DST_ADDR_MAP(IPA_NLO_VP_DSM_OPEN, + ipa.gen, + ipa_nlo_vp_dsm_open), + GEN_SRC_DST_ADDR_MAP(IPA_NLO_VP_QBAP_OPEN, + ipa.gen, + ipa_nlo_vp_qbap_open), +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + GEN_SRC_DST_ADDR_MAP(IPA_QSB_MAX_READS, + ipa.gen, + ipa_qsb_max_reads), + GEN_SRC_DST_ADDR_MAP(IPA_QSB_MAX_WRITES, + ipa.gen, + ipa_qsb_max_writes), + GEN_SRC_DST_ADDR_MAP(IPA_IDLE_INDICATION_CFG, + ipa.gen, + ipa_idle_indication_cfg), + GEN_SRC_DST_ADDR_MAP(IPA_CLKON_CFG, + ipa.gen, + ipa_clkon_cfg), + GEN_SRC_DST_ADDR_MAP(IPA_TIMERS_XO_CLK_DIV_CFG, + ipa.gen, + ipa_timers_xo_clk_div_cfg), + GEN_SRC_DST_ADDR_MAP(IPA_TIMERS_PULSE_GRAN_CFG, + ipa.gen, + ipa_timers_pulse_gran_cfg), + GEN_SRC_DST_ADDR_MAP(IPA_QTIME_TIMESTAMP_CFG, + ipa.gen, + ipa_qtime_timestamp_cfg), + GEN_SRC_DST_ADDR_MAP(IPA_FLAVOR_0, + ipa.gen, + ipa_flavor_0), + GEN_SRC_DST_ADDR_MAP(IPA_FLAVOR_1, + ipa.gen, + ipa_flavor_1), + GEN_SRC_DST_ADDR_MAP(IPA_FILT_ROUT_CFG, + ipa.gen, + ipa_filt_rout_cfg), +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + GEN_SRC_DST_ADDR_MAP(IPA_RSRC_GRP_CFG_EXT, + ipa.gen, + ipa_rsrc_grp_cfg_ext), +#endif +#endif + + /* Debug Registers */ + GEN_SRC_DST_ADDR_MAP(IPA_DEBUG_DATA, + ipa.dbg, + ipa_debug_data), + GEN_SRC_DST_ADDR_MAP(IPA_STEP_MODE_BREAKPOINTS, + ipa.dbg, + ipa_step_mode_breakpoints), + GEN_SRC_DST_ADDR_MAP(IPA_STEP_MODE_STATUS, + ipa.dbg, + ipa_step_mode_status), + + IPA_REG_SAVE_RX_SPLT_CMDQ( + IPA_RX_SPLT_CMDQ_CMD_n, ipa_rx_splt_cmdq_cmd_n), + IPA_REG_SAVE_RX_SPLT_CMDQ( + IPA_RX_SPLT_CMDQ_CFG_n, ipa_rx_splt_cmdq_cfg_n), + IPA_REG_SAVE_RX_SPLT_CMDQ( + IPA_RX_SPLT_CMDQ_DATA_WR_0_n, ipa_rx_splt_cmdq_data_wr_0_n), + IPA_REG_SAVE_RX_SPLT_CMDQ( + IPA_RX_SPLT_CMDQ_DATA_WR_1_n, ipa_rx_splt_cmdq_data_wr_1_n), + IPA_REG_SAVE_RX_SPLT_CMDQ( + IPA_RX_SPLT_CMDQ_DATA_WR_2_n, ipa_rx_splt_cmdq_data_wr_2_n), + IPA_REG_SAVE_RX_SPLT_CMDQ( + IPA_RX_SPLT_CMDQ_DATA_WR_3_n, ipa_rx_splt_cmdq_data_wr_3_n), + IPA_REG_SAVE_RX_SPLT_CMDQ( + IPA_RX_SPLT_CMDQ_DATA_RD_0_n, ipa_rx_splt_cmdq_data_rd_0_n), + IPA_REG_SAVE_RX_SPLT_CMDQ( + IPA_RX_SPLT_CMDQ_DATA_RD_1_n, ipa_rx_splt_cmdq_data_rd_1_n), + IPA_REG_SAVE_RX_SPLT_CMDQ( + IPA_RX_SPLT_CMDQ_DATA_RD_2_n, ipa_rx_splt_cmdq_data_rd_2_n), + IPA_REG_SAVE_RX_SPLT_CMDQ( + IPA_RX_SPLT_CMDQ_DATA_RD_3_n, ipa_rx_splt_cmdq_data_rd_3_n), + IPA_REG_SAVE_RX_SPLT_CMDQ( + IPA_RX_SPLT_CMDQ_STATUS_n, ipa_rx_splt_cmdq_status_n), + + GEN_SRC_DST_ADDR_MAP(IPA_RX_HPS_CMDQ_CFG_WR, + ipa.dbg, + ipa_rx_hps_cmdq_cfg_wr), + GEN_SRC_DST_ADDR_MAP(IPA_RX_HPS_CMDQ_CFG_RD, + ipa.dbg, + ipa_rx_hps_cmdq_cfg_rd), + GEN_SRC_DST_ADDR_MAP(IPA_RX_HPS_CMDQ_CMD, + ipa.dbg, + ipa_rx_hps_cmdq_cmd), +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + GEN_SRC_DST_ADDR_MAP(IPA_STAT_FILTER_IPV4_BASE, + ipa.dbg, + ipa_stat_filter_ipv4_base), + GEN_SRC_DST_ADDR_MAP(IPA_STAT_FILTER_IPV6_BASE, + ipa.dbg, + ipa_stat_filter_ipv6_base), + GEN_SRC_DST_ADDR_MAP(IPA_STAT_ROUTER_IPV4_BASE, + ipa.dbg, + ipa_stat_router_ipv4_base), + GEN_SRC_DST_ADDR_MAP(IPA_STAT_ROUTER_IPV6_BASE, + ipa.dbg, + ipa_stat_router_ipv6_base), + GEN_SRC_DST_ADDR_MAP(IPA_RSRC_MNGR_CONTEXTS, + ipa.dbg, + ipa_rsrc_mngr_contexts), + GEN_SRC_DST_ADDR_MAP(IPA_SNOC_MONITORING_CFG, + ipa.dbg, + ipa_snoc_monitoring_cfg), + GEN_SRC_DST_ADDR_MAP(IPA_PCIE_SNOC_MONITOR_CNT, + ipa.dbg, + ipa_pcie_snoc_monitor_cnt), + GEN_SRC_DST_ADDR_MAP(IPA_DDR_SNOC_MONITOR_CNT, + ipa.dbg, + ipa_ddr_snoc_monitor_cnt), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_SNOC_MONITOR_CNT, + ipa.dbg, + ipa_gsi_snoc_monitor_cnt), + + GEN_SRC_DST_ADDR_MAP(IPA_RAM_SNIFFER_HW_BASE_ADDR, + ipa.dbg, + ipa_ram_sniffer_hw_base_addr), + GEN_SRC_DST_ADDR_MAP(IPA_BRESP_DB_CFG, + ipa.dbg, + ipa_bresp_db_cfg), + GEN_SRC_DST_ADDR_MAP(IPA_BRESP_DB_DATA, + ipa.dbg, + ipa_bresp_db_data), + + GEN_SRC_DST_ADDR_MAP(IPA_ENDP_GSI_CONS_BYTES_TLV, + ipa.dbg, + ipa_endp_gsi_cons_bytes_tlv), + GEN_SRC_DST_ADDR_MAP(IPA_RAM_GSI_TLV_BASE_ADDR, + ipa.dbg, + ipa_ram_gsi_tlv_base_addr), + GEN_SRC_DST_ADDR_MAP(IPA_ACKMNGR_CMDQ_CMD, + ipa.dbg, + ipa_ackmngr_cmdq_cmd), +#endif + GEN_SRC_DST_ADDR_MAP(IPA_RX_HPS_CMDQ_STATUS_EMPTY, + ipa.dbg, + ipa_rx_hps_cmdq_status_empty), + GEN_SRC_DST_ADDR_MAP(IPA_RX_HPS_CLIENTS_MIN_DEPTH_0, + ipa.dbg, + ipa_rx_hps_clients_min_depth_0), + GEN_SRC_DST_ADDR_MAP(IPA_RX_HPS_CLIENTS_MAX_DEPTH_0, + ipa.dbg, + ipa_rx_hps_clients_max_depth_0), + GEN_SRC_DST_ADDR_MAP(IPA_HPS_DPS_CMDQ_CMD, + ipa.dbg, + ipa_hps_dps_cmdq_cmd), +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + GEN_SRC_DST_ADDR_MAP(IPA_HPS_DPS_CMDQ_STATUS_EMPTY, + ipa.dbg, + ipa_hps_dps_cmdq_status_empty), +#else + GEN_SRC_DST_ADDR_MAP_ARR(IPA_HPS_DPS_CMDQ_STATUS_EMPTY_n, + ipa.dbg, + ipa_hps_dps_cmdq_status_empty_n), +#endif + GEN_SRC_DST_ADDR_MAP(IPA_DPS_TX_CMDQ_CMD, + ipa.dbg, + ipa_dps_tx_cmdq_cmd), + GEN_SRC_DST_ADDR_MAP(IPA_DPS_TX_CMDQ_STATUS_EMPTY, + ipa.dbg, + ipa_dps_tx_cmdq_status_empty), + GEN_SRC_DST_ADDR_MAP(IPA_ACKMNGR_CMDQ_CMD, + ipa.dbg, + ipa_ackmngr_cmdq_cmd), +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + GEN_SRC_DST_ADDR_MAP(IPA_ACKMNGR_CMDQ_STATUS_EMPTY, + ipa.dbg, + ipa_ackmngr_cmdq_status_empty), +#else + GEN_SRC_DST_ADDR_MAP_ARR(IPA_ACKMNGR_CMDQ_STATUS_EMPTY_n, + ipa.dbg, + ipa_ackmngr_cmdq_status_empty_n), + GEN_SRC_DST_ADDR_MAP_ARR(IPA_NTF_TX_CMDQ_STATUS_EMPTY_n, + ipa.dbg, + ipa_ntf_tx_cmdq_status_empty_n), +#endif + /* + * NOTE: That GEN_SRC_DST_ADDR_MAP() not used below. This is + * because the following registers are not scaler, rather + * they are register arrays... + */ + IPA_REG_SAVE_CFG_ENTRY_GEN_EE(IPA_IRQ_STTS_EE_n, + ipa_irq_stts_ee_n), + IPA_REG_SAVE_CFG_ENTRY_GEN_EE(IPA_IRQ_EN_EE_n, + ipa_irq_en_ee_n), + IPA_REG_SAVE_CFG_ENTRY_GEN_EE(IPA_FEC_ADDR_EE_n, + ipa_fec_addr_ee_n), + IPA_REG_SAVE_CFG_ENTRY_GEN_EE(IPA_FEC_ATTR_EE_n, + ipa_fec_attr_ee_n), + IPA_REG_SAVE_CFG_ENTRY_GEN_EE(IPA_SNOC_FEC_EE_n, + ipa_snoc_fec_ee_n), +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + IPA_REG_SAVE_CFG_ENTRY_GEN_EE(IPA_HOLB_DROP_IRQ_INFO_EE_n, + ipa_holb_drop_irq_info_ee_n), + IPA_REG_SAVE_CFG_ENTRY_GEN_EE(IPA_SUSPEND_IRQ_INFO_EE_n, + ipa_suspend_irq_info_ee_n), + IPA_REG_SAVE_CFG_ENTRY_GEN_EE(IPA_SUSPEND_IRQ_EN_EE_n, + ipa_suspend_irq_en_ee_n), +#else + GEN_SRC_DST_ADDR_MAP_EE_n_REG_k_ARR(IPA_HOLB_DROP_IRQ_INFO_EE_n_REG_k, + ipa.gen_ee, ipa_holb_drop_irq_info_ee_n_reg_k), + GEN_SRC_DST_ADDR_MAP_EE_n_REG_k_ARR(IPA_SUSPEND_IRQ_INFO_EE_n_REG_k, + ipa.gen_ee, ipa_suspend_irq_info_ee_n_reg_k), + GEN_SRC_DST_ADDR_MAP_EE_n_REG_k_ARR(IPA_SUSPEND_IRQ_EN_EE_n_REG_k, + ipa.gen_ee, ipa_suspend_irq_en_ee_n_reg_k), +#endif + +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + GEN_SRC_DST_ADDR_MAP_EE_n_ARR(IPA_STAT_QUOTA_BASE_n, + ipa.stat_ee, ipa_stat_quota_base_n), + GEN_SRC_DST_ADDR_MAP_EE_n_ARR(IPA_STAT_TETHERING_BASE_n, + ipa.stat_ee, ipa_stat_tethering_base_n), + GEN_SRC_DST_ADDR_MAP_EE_n_ARR(IPA_STAT_DROP_CNT_BASE_n, + ipa.stat_ee, ipa_stat_drop_cnt_base_n), + GEN_SRC_DST_ADDR_MAP_EE_n_REG_k_ARR(IPA_STAT_QUOTA_MASK_EE_n_REG_k, + ipa.stat_ee, ipa_stat_quota_mask_ee_n_reg_k), + GEN_SRC_DST_ADDR_MAP_EE_n_REG_k_ARR(IPA_STAT_TETHERING_MASK_EE_n_REG_k, + ipa.stat_ee, ipa_stat_tethering_mask_ee_n_reg_k), + GEN_SRC_DST_ADDR_MAP_EE_n_REG_k_ARR(IPA_STAT_DROP_CNT_MASK_EE_n_REG_k, + ipa.stat_ee, ipa_stat_drop_cnt_mask_ee_n_reg_k), +#endif + + /* Pipe Endp Registers */ + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_CTRL_n, + ipa_endp_init_ctrl_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_CTRL_SCND_n, + ipa_endp_init_ctrl_scnd_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_CFG_n, + ipa_endp_init_cfg_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_NAT_n, + ipa_endp_init_nat_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_HDR_n, + ipa_endp_init_hdr_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_HDR_EXT_n, + ipa_endp_init_hdr_ext_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_HDR_METADATA_MASK_n, + ipa_endp_init_hdr_metadata_mask_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_HDR_METADATA_n, + ipa_endp_init_hdr_metadata_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_MODE_n, + ipa_endp_init_mode_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_AGGR_n, + ipa_endp_init_aggr_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_HOL_BLOCK_EN_n, + ipa_endp_init_hol_block_en_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_HOL_BLOCK_TIMER_n, + ipa_endp_init_hol_block_timer_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_DEAGGR_n, + ipa_endp_init_deaggr_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_STATUS_n, + ipa_endp_status_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_RSRC_GRP_n, + ipa_endp_init_rsrc_grp_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_SEQ_n, + ipa_endp_init_seq_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_GSI_CFG_TLV_n, + ipa_endp_gsi_cfg_tlv_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_GSI_CFG_AOS_n, + ipa_endp_gsi_cfg_aos_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_GSI_CFG1_n, + ipa_endp_gsi_cfg1_n), +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_FILTER_ROUTER_HSH_CFG_n, + ipa_endp_filter_router_hsh_cfg_n), +#else + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_FILTER_CACHE_CFG_n, + ipa_filter_cache_cfg_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ROUTER_CACHE_CFG_n, + ipa_router_cache_cfg_n), +#endif + + /* Source Resource Group Config Registers */ + IPA_REG_SAVE_CFG_ENTRY_SRC_RSRC_GRP(IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n, + ipa_src_rsrc_grp_01_rsrc_type_n), + IPA_REG_SAVE_CFG_ENTRY_SRC_RSRC_GRP(IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n, + ipa_src_rsrc_grp_23_rsrc_type_n), + IPA_REG_SAVE_CFG_ENTRY_SRC_RSRC_GRP(IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n, + ipa_src_rsrc_grp_45_rsrc_type_n), +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + IPA_REG_SAVE_CFG_ENTRY_SRC_RSRC_GRP(IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n, + ipa_src_rsrc_grp_67_rsrc_type_n), + IPA_REG_SAVE_CFG_ENTRY_SRC_RSRC_GRP(IPA_SRC_RSRC_TYPE_AMOUNT_n, + ipa_src_rsrc_type_amount), +#endif + + /* Destination Resource Group Config Registers */ + IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_GRP(IPA_DST_RSRC_GRP_01_RSRC_TYPE_n, + ipa_dst_rsrc_grp_01_rsrc_type_n), + IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_GRP(IPA_DST_RSRC_GRP_23_RSRC_TYPE_n, + ipa_dst_rsrc_grp_23_rsrc_type_n), + IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_GRP(IPA_DST_RSRC_GRP_45_RSRC_TYPE_n, + ipa_dst_rsrc_grp_45_rsrc_type_n), +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_GRP(IPA_DST_RSRC_GRP_67_RSRC_TYPE_n, + ipa_dst_rsrc_grp_67_rsrc_type_n), + IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_GRP(IPA_DST_RSRC_TYPE_AMOUNT_n, + ipa_dst_rsrc_type_amount), +#endif + + /* Source Resource Group Count Registers */ + IPA_REG_SAVE_CFG_ENTRY_SRC_RSRC_CNT_GRP( + IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n, + ipa_src_rsrc_grp_0123_rsrc_type_cnt_n), + IPA_REG_SAVE_CFG_ENTRY_SRC_RSRC_CNT_GRP( + IPA_SRC_RSRC_GRP_4567_RSRC_TYPE_CNT_n, + ipa_src_rsrc_grp_4567_rsrc_type_cnt_n), + + /* Destination Resource Group Count Registers */ + IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_CNT_GRP( + IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n, + ipa_dst_rsrc_grp_0123_rsrc_type_cnt_n), + IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_CNT_GRP( + IPA_DST_RSRC_GRP_4567_RSRC_TYPE_CNT_n, + ipa_dst_rsrc_grp_4567_rsrc_type_cnt_n), + + /* + * ===================================================================== + * GSI register definitions begin here... + * ===================================================================== + */ + + /* GSI General Registers */ + GEN_SRC_DST_ADDR_MAP(GSI_CFG, + gsi.gen, + gsi_cfg), + GEN_SRC_DST_ADDR_MAP(GSI_REE_CFG, + gsi.gen, + gsi_ree_cfg), + IPA_REG_SAVE_GSI_VER( + IPA_GSI_TOP_GSI_INST_RAM_n, + ipa_gsi_top_gsi_inst_ram_n), + + /* GSI Debug Registers */ + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_DEBUG_BUSY_REG, + gsi.debug, + ipa_gsi_top_gsi_debug_busy_reg), +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_DEBUG_EVENT_PENDING, + gsi.debug, + ipa_gsi_top_gsi_debug_event_pending), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_DEBUG_TIMER_PENDING, + gsi.debug, + ipa_gsi_top_gsi_debug_timer_pending), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_DEBUG_RD_WR_PENDING, + gsi.debug, + ipa_gsi_top_gsi_debug_rd_wr_pending), +#endif + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW, + gsi.debug, + ipa_gsi_top_gsi_debug_pc_from_sw), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_DEBUG_SW_STALL, + gsi.debug, + ipa_gsi_top_gsi_debug_sw_stall), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG, + gsi.debug, + ipa_gsi_top_gsi_debug_pc_for_debug), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID, + gsi.debug, + ipa_gsi_top_gsi_debug_qsb_log_err_trns_id), +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + GEN_SRC_DST_ADDR_MAP(GSI_MCS_PROFILING_BP_CNT_LSB, + gsi.debug.gsi_mcs_prof_regs, + gsi_top_gsi_mcs_profiling_bp_cnt_lsb), + GEN_SRC_DST_ADDR_MAP(GSI_MCS_PROFILING_BP_CNT_MSB, + gsi.debug.gsi_mcs_prof_regs, + gsi_top_gsi_mcs_profiling_bp_cnt_msb), + GEN_SRC_DST_ADDR_MAP(GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB, + gsi.debug.gsi_mcs_prof_regs, + gsi_top_gsi_mcs_profiling_bp_and_pending_cnt_lsb), + GEN_SRC_DST_ADDR_MAP(GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB, + gsi.debug.gsi_mcs_prof_regs, + gsi_top_gsi_mcs_profiling_bp_and_pending_cnt_msb), + GEN_SRC_DST_ADDR_MAP(GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB, + gsi.debug.gsi_mcs_prof_regs, + gsi_top_gsi_mcs_profiling_mcs_busy_cnt_lsb), + GEN_SRC_DST_ADDR_MAP(GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB, + gsi.debug.gsi_mcs_prof_regs, + gsi_top_gsi_mcs_profiling_mcs_busy_cnt_msb), + GEN_SRC_DST_ADDR_MAP(GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB, + gsi.debug.gsi_mcs_prof_regs, + gsi_top_gsi_mcs_profiling_mcs_idle_cnt_lsb), + GEN_SRC_DST_ADDR_MAP(GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB, + gsi.debug.gsi_mcs_prof_regs, + gsi_top_gsi_mcs_profiling_mcs_idle_cnt_msb), +#endif + IPA_REG_SAVE_CFG_ENTRY_GSI_QSB_DEBUG( + GSI_DEBUG_QSB_LOG_LAST_MISC_IDn, qsb_log_last_misc), + + /* GSI IRAM pointers Registers */ + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD, + gsi.debug.gsi_iram_ptrs, + ipa_gsi_top_gsi_iram_ptr_ch_cmd), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD, + gsi.debug.gsi_iram_ptrs, + ipa_gsi_top_gsi_iram_ptr_ee_generic_cmd), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB, + gsi.debug.gsi_iram_ptrs, + ipa_gsi_top_gsi_iram_ptr_ch_db), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB, + gsi.debug.gsi_iram_ptrs, + ipa_gsi_top_gsi_iram_ptr_ev_db), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE, + gsi.debug.gsi_iram_ptrs, + ipa_gsi_top_gsi_iram_ptr_new_re), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP, + gsi.debug.gsi_iram_ptrs, + ipa_gsi_top_gsi_iram_ptr_ch_dis_comp), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY, + gsi.debug.gsi_iram_ptrs, + ipa_gsi_top_gsi_iram_ptr_ch_empty), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP, + gsi.debug.gsi_iram_ptrs, + ipa_gsi_top_gsi_iram_ptr_event_gen_comp), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED, + gsi.debug.gsi_iram_ptrs, + ipa_gsi_top_gsi_iram_ptr_timer_expired), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP, + gsi.debug.gsi_iram_ptrs, + ipa_gsi_top_gsi_iram_ptr_write_eng_comp), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP, + gsi.debug.gsi_iram_ptrs, + ipa_gsi_top_gsi_iram_ptr_read_eng_comp), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT, + gsi.debug.gsi_iram_ptrs, + ipa_gsi_top_gsi_iram_ptr_uc_gp_int), +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPPED, + gsi.debug.gsi_iram_ptrs, + ipa_gsi_top_gsi_iram_ptr_int_mod_stopped), +#else + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPED, + gsi.debug.gsi_iram_ptrs, + ipa_gsi_top_gsi_iram_ptr_int_mod_stoped), +#endif + + /* GSI SHRAM pointers Registers */ + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR, + gsi.debug.gsi_shram_ptrs, + ipa_gsi_top_gsi_shram_ptr_ch_cntxt_base_addr), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR, + gsi.debug.gsi_shram_ptrs, + ipa_gsi_top_gsi_shram_ptr_ev_cntxt_base_addr), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR, + gsi.debug.gsi_shram_ptrs, + ipa_gsi_top_gsi_shram_ptr_re_storage_base_addr), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR, + gsi.debug.gsi_shram_ptrs, + ipa_gsi_top_gsi_shram_ptr_re_esc_buf_base_addr), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR, + gsi.debug.gsi_shram_ptrs, + ipa_gsi_top_gsi_shram_ptr_ee_scrach_base_addr), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR, + gsi.debug.gsi_shram_ptrs, + ipa_gsi_top_gsi_shram_ptr_func_stack_base_addr), + + /* + * NOTE: That GEN_SRC_DST_ADDR_MAP() not used below. This is + * because the following registers are not scaler, rather + * they are register arrays... + */ + + /* GSI General EE Registers */ + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(GSI_MANAGER_EE_QOS_n, + gsi_manager_ee_qos_n), + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_GSI_STATUS, + ee_n_gsi_status), + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_CNTXT_TYPE_IRQ, + ee_n_cntxt_type_irq), + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_CNTXT_TYPE_IRQ_MSK, + ee_n_cntxt_type_irq_msk), +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_CNTXT_SRC_GSI_CH_IRQ, + ee_n_cntxt_src_gsi_ch_irq), + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_CNTXT_SRC_EV_CH_IRQ, + ee_n_cntxt_src_ev_ch_irq), + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK, + ee_n_cntxt_src_gsi_ch_irq_msk), + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_CNTXT_SRC_EV_CH_IRQ_MSK, + ee_n_cntxt_src_ev_ch_irq_msk), + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_CNTXT_SRC_IEOB_IRQ, + ee_n_cntxt_src_ieob_irq), + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_CNTXT_SRC_IEOB_IRQ_MSK, + ee_n_cntxt_src_ieob_irq_msk), +#else + GEN_SRC_DST_ADDR_MAP_EE_n_REG_k_ARR(EE_n_CNTXT_SRC_GSI_CH_IRQ_k, + gsi.gen_ee, + ee_n_cntxt_src_gsi_ch_irq_k), + GEN_SRC_DST_ADDR_MAP_EE_n_REG_k_ARR(EE_n_CNTXT_SRC_EV_CH_IRQ_k, + gsi.gen_ee, + ee_n_cntxt_src_ev_ch_irq_k), + GEN_SRC_DST_ADDR_MAP_EE_n_REG_k_ARR(EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k, + gsi.gen_ee, + ee_n_cntxt_src_gsi_ch_irq_msk_k), + GEN_SRC_DST_ADDR_MAP_EE_n_REG_k_ARR(EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k, + gsi.gen_ee, + ee_n_cntxt_src_ev_ch_irq_msk_k), + GEN_SRC_DST_ADDR_MAP_EE_n_REG_k_ARR(EE_n_CNTXT_SRC_IEOB_IRQ_k, + gsi.gen_ee, + ee_n_cntxt_src_ieob_irq_k), + GEN_SRC_DST_ADDR_MAP_EE_n_REG_k_ARR(EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k, + gsi.gen_ee, + ee_n_cntxt_src_ieob_irq_msk_k), +#endif + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_CNTXT_GSI_IRQ_STTS, + ee_n_cntxt_gsi_irq_stts), + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_CNTXT_GLOB_IRQ_STTS, + ee_n_cntxt_glob_irq_stts), + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_ERROR_LOG, + ee_n_error_log), + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_CNTXT_SCRATCH_0, + ee_n_cntxt_scratch_0), + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_CNTXT_SCRATCH_1, + ee_n_cntxt_scratch_1), + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_CNTXT_INTSET, + ee_n_cntxt_intset), + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_CNTXT_MSI_BASE_LSB, + ee_n_cntxt_msi_base_lsb), + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_CNTXT_MSI_BASE_MSB, + ee_n_cntxt_msi_base_msb), + + /* GSI Channel Context Registers */ + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_CNTXT_0, + ee_n_gsi_ch_k_cntxt_0), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_CNTXT_1, + ee_n_gsi_ch_k_cntxt_1), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_CNTXT_2, + ee_n_gsi_ch_k_cntxt_2), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_CNTXT_3, + ee_n_gsi_ch_k_cntxt_3), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_CNTXT_4, + ee_n_gsi_ch_k_cntxt_4), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_CNTXT_5, + ee_n_gsi_ch_k_cntxt_5), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_CNTXT_6, + ee_n_gsi_ch_k_cntxt_6), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_CNTXT_7, + ee_n_gsi_ch_k_cntxt_7), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_RE_FETCH_READ_PTR, + ee_n_gsi_ch_k_re_fetch_read_ptr), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR, + ee_n_gsi_ch_k_re_fetch_write_ptr), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_QOS, + ee_n_gsi_ch_k_qos), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_SCRATCH_0, + ee_n_gsi_ch_k_scratch_0), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_SCRATCH_1, + ee_n_gsi_ch_k_scratch_1), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_SCRATCH_2, + ee_n_gsi_ch_k_scratch_2), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_SCRATCH_3, + ee_n_gsi_ch_k_scratch_3), +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_SCRATCH_4, + ee_n_gsi_ch_k_scratch_4), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_SCRATCH_5, + ee_n_gsi_ch_k_scratch_5), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_SCRATCH_6, + ee_n_gsi_ch_k_scratch_6), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_SCRATCH_7, + ee_n_gsi_ch_k_scratch_7), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_SCRATCH_8, + ee_n_gsi_ch_k_scratch_8), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_SCRATCH_9, + ee_n_gsi_ch_k_scratch_9), +#endif + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(GSI_MAP_EE_n_CH_k_VP_TABLE, + gsi_map_ee_n_ch_k_vp_table), + + /* GSI Channel Event Context Registers */ + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_CNTXT_0, + ee_n_ev_ch_k_cntxt_0), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_CNTXT_1, + ee_n_ev_ch_k_cntxt_1), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_CNTXT_2, + ee_n_ev_ch_k_cntxt_2), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_CNTXT_3, + ee_n_ev_ch_k_cntxt_3), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_CNTXT_4, + ee_n_ev_ch_k_cntxt_4), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_CNTXT_5, + ee_n_ev_ch_k_cntxt_5), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_CNTXT_6, + ee_n_ev_ch_k_cntxt_6), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_CNTXT_7, + ee_n_ev_ch_k_cntxt_7), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_CNTXT_8, + ee_n_ev_ch_k_cntxt_8), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_CNTXT_9, + ee_n_ev_ch_k_cntxt_9), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_CNTXT_10, + ee_n_ev_ch_k_cntxt_10), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_CNTXT_11, + ee_n_ev_ch_k_cntxt_11), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_CNTXT_12, + ee_n_ev_ch_k_cntxt_12), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_CNTXT_13, + ee_n_ev_ch_k_cntxt_13), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_SCRATCH_0, + ee_n_ev_ch_k_scratch_0), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_SCRATCH_1, + ee_n_ev_ch_k_scratch_1), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(GSI_DEBUG_EE_n_EV_k_VP_TABLE, + gsi_debug_ee_n_ev_k_vp_table), + +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 +/* GSI Debug SW MSK Registers */ + IPA_REG_SAVE_GSI_DEBUG_MSK_REG_ENTRY(GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD, + regs), +#endif + +#if defined(CONFIG_IPA3_REGDUMP_NUM_EXTRA_ENDP_REGS) && \ + CONFIG_IPA3_REGDUMP_NUM_EXTRA_ENDP_REGS > 0 + /* Endp Registers for remaining pipes */ + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_INIT_CTRL_n, + ipa_endp_init_ctrl_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_INIT_CTRL_SCND_n, + ipa_endp_init_ctrl_scnd_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_INIT_CFG_n, + ipa_endp_init_cfg_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_INIT_NAT_n, + ipa_endp_init_nat_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_INIT_HDR_n, + ipa_endp_init_hdr_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_INIT_HDR_EXT_n, + ipa_endp_init_hdr_ext_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA + (IPA_ENDP_INIT_HDR_METADATA_MASK_n, + ipa_endp_init_hdr_metadata_mask_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_INIT_HDR_METADATA_n, + ipa_endp_init_hdr_metadata_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_INIT_MODE_n, + ipa_endp_init_mode_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_INIT_AGGR_n, + ipa_endp_init_aggr_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_INIT_HOL_BLOCK_EN_n, + ipa_endp_init_hol_block_en_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_INIT_HOL_BLOCK_TIMER_n, + ipa_endp_init_hol_block_timer_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_INIT_DEAGGR_n, + ipa_endp_init_deaggr_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_STATUS_n, + ipa_endp_status_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_INIT_RSRC_GRP_n, + ipa_endp_init_rsrc_grp_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_INIT_SEQ_n, + ipa_endp_init_seq_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_GSI_CFG_TLV_n, + ipa_endp_gsi_cfg_tlv_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_GSI_CFG_AOS_n, + ipa_endp_gsi_cfg_aos_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_GSI_CFG1_n, + ipa_endp_gsi_cfg1_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA + (IPA_ENDP_FILTER_ROUTER_HSH_CFG_n, + ipa_endp_filter_router_hsh_cfg_n), +#endif +}; + +/* IPA uC PER registers save Cfg array */ +static struct map_src_dst_addr_s ipa_uc_regs_to_save_array[] = { + /* HWP registers */ + GEN_SRC_DST_ADDR_MAP(IPA_UC_QMB_SYS_ADDR, + ipa.hwp, + ipa_uc_qmb_sys_addr), + GEN_SRC_DST_ADDR_MAP(IPA_UC_QMB_LOCAL_ADDR, + ipa.hwp, + ipa_uc_qmb_local_addr), + GEN_SRC_DST_ADDR_MAP(IPA_UC_QMB_LENGTH, + ipa.hwp, + ipa_uc_qmb_length), + GEN_SRC_DST_ADDR_MAP(IPA_UC_QMB_TRIGGER, + ipa.hwp, + ipa_uc_qmb_trigger), +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + GEN_SRC_DST_ADDR_MAP(IPA_UC_QMB_PENDING_TID, + ipa.hwp, + ipa_uc_qmb_pending_tid), + GEN_SRC_DST_ADDR_MAP(IPA_UC_QMB_COMPLETED_RD_FIFO_PEEK, + ipa.hwp, + ipa_uc_qmb_completed_rd_fifo_peek), + GEN_SRC_DST_ADDR_MAP(IPA_UC_QMB_COMPLETED_WR_FIFO_PEEK, + ipa.hwp, + ipa_uc_qmb_completed_wr_fifo_peek), + GEN_SRC_DST_ADDR_MAP(IPA_UC_QMB_MISC, + ipa.hwp, + ipa_uc_qmb_misc), + GEN_SRC_DST_ADDR_MAP(IPA_UC_QMB_STATUS, + ipa.hwp, + ipa_uc_qmb_status), +#endif + GEN_SRC_DST_ADDR_MAP(IPA_UC_QMB_BUS_ATTRIB, + ipa.hwp, + ipa_uc_qmb_bus_attrib), +}; + +static void ipa_hal_save_regs_save_ipa_testbus(void); +static void ipa_reg_save_gsi_fifo_status(void); +static void ipa_reg_save_rsrc_cnts(void); +static void ipa_hal_save_regs_ipa_cmdq(void); +static void ipa_hal_save_regs_rsrc_db(void); +static void ipa_reg_save_anomaly_check(void); + +static struct reg_access_funcs_s *get_access_funcs(u32 addr) +{ + u32 i, asub = ipa3_ctx->sd_state; + + for (i = 0; i < ARRAY_SIZE(mem_access_map); i++) { + if (addr >= mem_access_map[i].addr_range_begin && + addr < mem_access_map[i].addr_range_end) { + return mem_access_map[i].access[asub]; + } + } + + IPAERR("Unknown register offset(0x%08X). Using dflt access methods\n", + addr); + + return &io_matrix[AA_COMBO]; +} + +static u32 in_dword( + u32 addr, + u8 perm) +{ + struct reg_access_funcs_s *io = get_access_funcs(addr); + + if (perm & REG_READ_PERM) { + if (io->read == nop_read) + IPADBG_LOW("nop read action for address 0x%X\n", addr); + return io->read(ipa3_ctx->reg_collection_base + addr); + } else { + IPADBG_LOW("not permitted to read addr 0x%X\n", addr); + return nop_read(ipa3_ctx->reg_collection_base + addr); + } +} + +static u32 in_dword_masked( + u32 addr, + u32 mask, + u8 perm) +{ + struct reg_access_funcs_s *io = get_access_funcs(addr); + u32 val; + + if (perm & REG_READ_PERM) { + if (io->read == nop_read) + IPADBG_LOW("nop read action for address 0x%X\n", addr); + + val = io->read(ipa3_ctx->reg_collection_base + addr); + if (io->read == act_read) + return val & mask; + } else { + IPADBG_LOW("not permitted to read addr 0x%X\n", addr); + val = nop_read(ipa3_ctx->reg_collection_base + addr); + } + + return val; +} + +static void out_dword( + u32 addr, + u32 val, + u8 perm) +{ + struct reg_access_funcs_s *io = get_access_funcs(addr); + + if (perm & REG_WRITE_PERM) { + io->write(ipa3_ctx->reg_collection_base + addr, val); + if (io->write == nop_write) + IPADBG_LOW("nop write action for address 0x%X\n", addr); + } else { + IPADBG_LOW("not permitted to write addr 0x%X\n", addr); + return; + } +} + +/* + * FUNCTION: ipa_save_gsi_ver + * + * Saves the gsi version + * + * @return + * None + */ +void ipa_save_gsi_ver(void) +{ + if (!ipa3_ctx->do_register_collection_on_crash) + return; + + if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0) + ipa_reg_save.gsi.fw_ver = + IPA_READ_1xVECTOR_REG(IPA_GSI_TOP_GSI_INST_RAM_n, 0); + if (ipa3_ctx->ipa_hw_type == IPA_HW_v5_0) + ipa_reg_save.gsi.fw_ver = + IPA_READ_1xVECTOR_REG(IPA_GSI_TOP_GSI_INST_RAM_n, 64); +} + +/* + * FUNCTION: ipa_save_registers + * + * Saves all the IPA register values which are configured + * + * @return + * None + */ +void ipa_save_registers(void) +{ + u32 i = 0; + u32 phys_ch_idx = 0; + u32 n = 0; + /* Fetch the number of registers configured to be saved */ + u32 num_regs = ARRAY_SIZE(ipa_regs_to_save_array); + u32 num_uc_per_regs = ARRAY_SIZE(ipa_uc_regs_to_save_array); + union ipa_hwio_def_ipa_rsrc_mngr_db_cfg_u for_cfg; + union ipa_hwio_def_ipa_rsrc_mngr_db_rsrc_read_u for_read; + + if (!ipa3_ctx->do_register_collection_on_crash) + return; + + IPAERR("Commencing\n"); + + /* + * Remove the GSI FIFO and the endp registers for extra pipes for + * now. These would be saved later + */ + num_regs -= (CONFIG_IPA3_REGDUMP_NUM_EXTRA_ENDP_REGS * + IPA_REG_SAVE_NUM_EXTRA_ENDP_REGS); + + memset(&for_cfg, 0, sizeof(for_cfg)); + memset(&for_read, 0, sizeof(for_read)); + + IPAERR("reading %d registers\n", num_regs); + /* Now save all the configured registers */ + for (i = 0; i < num_regs; i++) { + /* Copy reg value to our data struct */ + *(ipa_regs_to_save_array[i].dst_addr) = + in_dword(ipa_regs_to_save_array[i].src_addr, + ipa_regs_to_save_array[i].perm); + } + + /* + * Set the active flag for all active pipe indexed registers. + */ + for (i = 0; i < IPA_HW_PIPE_ID_MAX; i++) + ipa_reg_save.ipa.pipes[i].active = true; + + /* Now save the per endp registers for the remaining pipes */ + for (i = 0; i < (CONFIG_IPA3_REGDUMP_NUM_EXTRA_ENDP_REGS * + IPA_REG_SAVE_NUM_EXTRA_ENDP_REGS); i++) { + /* Copy reg value to our data struct */ + *(ipa_regs_to_save_array[num_regs + i].dst_addr) = + in_dword(ipa_regs_to_save_array[num_regs + i].src_addr, + ipa_regs_to_save_array[num_regs + i].perm); + } + + IPA_HW_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA_ACTIVE(); + + num_regs += (CONFIG_IPA3_REGDUMP_NUM_EXTRA_ENDP_REGS * + IPA_REG_SAVE_NUM_EXTRA_ENDP_REGS); + + /* Saving GSI FIFO Status registers */ + ipa_reg_save_gsi_fifo_status(); + + /* + * On targets that support SSR, we generally want to disable + * the following reg save functionality as it may cause stalls + * in IPA after the SSR. + * + * To override this, set do_non_tn_collection_on_crash to + * true, via dtsi, and the collection will be done. + */ + if (ipa3_ctx->do_non_tn_collection_on_crash) { + /* Save all the uC PER configured registers */ + for (i = 0; i < num_uc_per_regs; i++) { + /* Copy reg value to our data struct */ + *(ipa_uc_regs_to_save_array[i].dst_addr) = + in_dword(ipa_uc_regs_to_save_array[i].src_addr, + ipa_uc_regs_to_save_array[i].perm); + } + + /* Saving CMD Queue registers */ + ipa_hal_save_regs_ipa_cmdq(); + + /* Collecting resource DB information */ + ipa_hal_save_regs_rsrc_db(); + + /* Save IPA testbus */ + if (ipa3_ctx->do_testbus_collection_on_crash) + ipa_hal_save_regs_save_ipa_testbus(); + } + + /* GSI test bus */ + for (i = 0; + i < ARRAY_SIZE(ipa_reg_save_gsi_ch_test_bus_selector_array); + i++) { + ipa_reg_save.gsi.debug.gsi_test_bus.test_bus_selector[i] = + ipa_reg_save_gsi_ch_test_bus_selector_array[i]; + + /* Write test bus selector */ + IPA_WRITE_SCALER_REG( + GSI_TEST_BUS_SEL, + ipa_reg_save_gsi_ch_test_bus_selector_array[i]); + + ipa_reg_save.gsi.debug.gsi_test_bus.test_bus_reg[ + i].gsi_testbus_reg = + (u32) IPA_READ_SCALER_REG(GSI_TEST_BUS_REG); + } + + ipa_reg_save_rsrc_cnts(); + + for (i = 0; i < HWIO_GSI_DEBUG_SW_RF_n_READ_MAXn + 1; i++) + ipa_reg_save.gsi.debug.gsi_mcs_regs.mcs_reg[i].rf_reg = + IPA_READ_1xVECTOR_REG(GSI_DEBUG_SW_RF_n_READ, i); + + for (i = 0; i < HWIO_GSI_DEBUG_COUNTERn_MAXn + 1; i++) + ipa_reg_save.gsi.debug.gsi_cnt_regs.cnt[i].counter_value = + (u16)IPA_READ_1xVECTOR_REG(GSI_DEBUG_COUNTERn, i); + + for (i = 0; i < IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_A7; i++) { + phys_ch_idx = ipa_reg_save.gsi.ch_cntxt.a7[ + i].gsi_map_ee_n_ch_k_vp_table.phy_ch; + n = phys_ch_idx * IPA_REG_SAVE_BYTES_PER_CHNL_SHRAM; + + if (!ipa_reg_save.gsi.ch_cntxt.a7[ + i].gsi_map_ee_n_ch_k_vp_table.valid) + continue; + + ipa_reg_save.gsi.ch_cntxt.a7[ + i].mcs_channel_scratch.scratch_for_seq_low.shram = + IPA_READ_1xVECTOR_REG( + GSI_SHRAM_n, + n + IPA_GSI_OFFSET_WORDS_SCRATCH_FOR_SEQ_LOW); + + ipa_reg_save.gsi.ch_cntxt.a7[ + i].mcs_channel_scratch.scratch_for_seq_high.shram = + IPA_READ_1xVECTOR_REG( + GSI_SHRAM_n, + n + IPA_GSI_OFFSET_WORDS_SCRATCH_FOR_SEQ_HIGH); +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + ipa_reg_save.gsi.ch_cntxt.a7[ + i].fc_stats_state.value = IPA_READ_1xVECTOR_REG( + GSI_SHRAM_n, + n + IPA_REG_SAVE_FC_STATE_OFFSET); + } +#endif + + for (i = 0; i < IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_UC; i++) { + phys_ch_idx = ipa_reg_save.gsi.ch_cntxt.uc[ + i].gsi_map_ee_n_ch_k_vp_table.phy_ch; + n = phys_ch_idx * IPA_REG_SAVE_BYTES_PER_CHNL_SHRAM; + + if (!ipa_reg_save.gsi.ch_cntxt.uc[ + i].gsi_map_ee_n_ch_k_vp_table.valid) + continue; + + ipa_reg_save.gsi.ch_cntxt.uc[ + i].mcs_channel_scratch.scratch_for_seq_low.shram = + IPA_READ_1xVECTOR_REG( + GSI_SHRAM_n, + n + IPA_GSI_OFFSET_WORDS_SCRATCH_FOR_SEQ_LOW); + + ipa_reg_save.gsi.ch_cntxt.uc[ + i].mcs_channel_scratch.scratch_for_seq_high.shram = + IPA_READ_1xVECTOR_REG( + GSI_SHRAM_n, + n + IPA_GSI_OFFSET_WORDS_SCRATCH_FOR_SEQ_HIGH); + +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + ipa_reg_save.gsi.ch_cntxt.uc[ + i].fc_stats_state.value = IPA_READ_1xVECTOR_REG( + GSI_SHRAM_n, + n + IPA_REG_SAVE_FC_STATE_OFFSET); + } +#endif + + for (i = 0; i < IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_Q6; i++) { + phys_ch_idx = ipa_reg_save.gsi.ch_cntxt.q6[ + i].gsi_map_ee_n_ch_k_vp_table.phy_ch; + n = phys_ch_idx * IPA_REG_SAVE_BYTES_PER_CHNL_SHRAM; + + if (!ipa_reg_save.gsi.ch_cntxt.q6[ + i].gsi_map_ee_n_ch_k_vp_table.valid) + continue; + + ipa_reg_save.gsi.ch_cntxt.q6[ + i].mcs_channel_scratch.scratch_for_seq_low.shram = + IPA_READ_1xVECTOR_REG( + GSI_SHRAM_n, + n + IPA_GSI_OFFSET_WORDS_SCRATCH_FOR_SEQ_LOW); + + ipa_reg_save.gsi.ch_cntxt.q6[ + i].mcs_channel_scratch.scratch_for_seq_high.shram = + IPA_READ_1xVECTOR_REG( + GSI_SHRAM_n, + n + IPA_GSI_OFFSET_WORDS_SCRATCH_FOR_SEQ_HIGH); + +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + ipa_reg_save.gsi.ch_cntxt.q6[ + i].fc_stats_state.value = IPA_READ_1xVECTOR_REG( + GSI_SHRAM_n, + n + IPA_REG_SAVE_FC_STATE_OFFSET); + } +#endif + + /* + * On targets that support SSR, we generally want to disable + * the following reg save functionality as it may cause stalls + * in IPA after the SSR. + * + * To override this, set do_non_tn_collection_on_crash to + * true, via dtsi, and the collection will be done. + */ + if (ipa3_ctx->do_non_tn_collection_on_crash) { + u32 ofst = GEN_2xVECTOR_REG_OFST(IPA_CTX_ID_m_CTX_NUM_n, 0, 0); + struct reg_access_funcs_s *io = get_access_funcs(ofst); + /* + * If the memory is accessible, copy pkt context directly from + * IPA_CTX_ID register space + */ + if (io->read == act_read) { + for (i = 0; i < IPA_HW_PKT_CTNTX_MAX; i++) { + memcpy((void *)(&(ipa_reg_save.pkt_ctntx[i])), + (void*)(ipa3_ctx->reg_collection_base + HWIO_IPA_CTX_ID_m_CTX_NUM_n_ADDR(i, 0)), + sizeof(ipa_reg_save.pkt_ctntx[0])); + } + + for_cfg.value = + IPA_READ_SCALER_REG(IPA_RSRC_MNGR_DB_CFG); + + for_cfg.def.rsrc_type_sel = 0; + + IPA_MASKED_WRITE_SCALER_REG( + IPA_RSRC_MNGR_DB_CFG, + for_cfg.value); + + for (i = 0; i < IPA_HW_PKT_CTNTX_MAX; i++) { + for_cfg.def.rsrc_id_sel = i; + + IPA_MASKED_WRITE_SCALER_REG( + IPA_RSRC_MNGR_DB_CFG, + for_cfg.value); + + for_read.value = + IPA_READ_SCALER_REG( + IPA_RSRC_MNGR_DB_RSRC_READ); + + if (for_read.def.rsrc_occupied) { + ipa_reg_save.pkt_ctntx_active[i] = true; + ipa_reg_save.pkt_cntxt_state[i] = + (enum ipa_hw_pkt_cntxt_state_e) + ipa_reg_save.pkt_ctntx[i].state; + } + } + } else { + IPAERR("IPA_CTX_ID is not currently accessible\n"); + } + } + + if (ipa3_ctx->do_ram_collection_on_crash) { + for (i = 0; i < IPA_IU_SIZE / sizeof(u32); i++) { + ipa_reg_save.ipa.ipa_iu_ptr[i] = + in_dword(IPA_IU_ADDR + (i * sizeof(u32)), + REG_READ_PERM); + } + for (i = 0; i < IPA_SRAM_SIZE / sizeof(u32); i++) { + ipa_reg_save.ipa.ipa_sram_ptr[i] = + in_dword(IPA_SRAM_ADDR + (i * sizeof(u32)), + REG_READ_PERM); + } + for (i = 0; i < IPA_MBOX_SIZE / sizeof(u32); i++) { + ipa_reg_save.ipa.ipa_mbox_ptr[i] = + in_dword(IPA_MBOX_ADDR + (i * sizeof(u32)), + REG_READ_PERM); + } + for (i = 0; i < IPA_HRAM_SIZE / sizeof(u32); i++) { + ipa_reg_save.ipa.ipa_hram_ptr[i] = + in_dword(IPA_HRAM_ADDR + (i * sizeof(u32)), + REG_READ_PERM); + } + for (i = 0; i < IPA_SEQ_SIZE / sizeof(u32); i++) { + ipa_reg_save.ipa.ipa_seq_ptr[i] = + in_dword(IPA_SEQ_ADDR + (i * sizeof(u32)), + REG_READ_PERM); + } + for (i = 0; i < IPA_GSI_SIZE / sizeof(u32); i++) { + ipa_reg_save.ipa.ipa_gsi_ptr[i] = + in_dword(IPA_GSI_ADDR + (i * sizeof(u32)), + REG_READ_PERM); + } + IPALOG_VnP_ADDRS(ipa_reg_save.ipa.ipa_iu_ptr); + IPALOG_VnP_ADDRS(ipa_reg_save.ipa.ipa_sram_ptr); + IPALOG_VnP_ADDRS(ipa_reg_save.ipa.ipa_mbox_ptr); + IPALOG_VnP_ADDRS(ipa_reg_save.ipa.ipa_hram_ptr); + IPALOG_VnP_ADDRS(ipa_reg_save.ipa.ipa_seq_ptr); + IPALOG_VnP_ADDRS(ipa_reg_save.ipa.ipa_gsi_ptr); + } + + ipa_reg_save_anomaly_check(); + + IPAERR("Completed\n"); +} + +/* + * FUNCTION: ipa_reg_save_gsi_fifo_status + * + * This function saves the GSI FIFO Status registers for all endpoints + * + * @param + * + * @return + */ +static void ipa_reg_save_gsi_fifo_status(void) +{ + u8 i; + for (i = 0; i < IPA_HW_PIPE_ID_MAX; i++) { + memset(&ipa_reg_save.gsi_fifo_status[i].gsi_fifo_status_ctrl, + 0, sizeof(ipa_reg_save.gsi_fifo_status[i].gsi_fifo_status_ctrl)); + + ipa_reg_save.gsi_fifo_status[i].gsi_fifo_status_ctrl.def.ipa_gsi_fifo_status_en = 1; + ipa_reg_save.gsi_fifo_status[i].gsi_fifo_status_ctrl.def.ipa_gsi_fifo_status_port_sel = i; + + IPA_MASKED_WRITE_SCALER_REG(IPA_GSI_FIFO_STATUS_CTRL, + ipa_reg_save.gsi_fifo_status[i].gsi_fifo_status_ctrl.value); + + ipa_reg_save.gsi_fifo_status[i].gsi_tlv_fifo_status.value = + IPA_READ_SCALER_REG(IPA_GSI_TLV_FIFO_STATUS); + ipa_reg_save.gsi_fifo_status[i].gsi_aos_fifo_status.value = + IPA_READ_SCALER_REG(IPA_GSI_AOS_FIFO_STATUS); + } +} + +/* + * FUNCTION: ipa_reg_save_rsrc_cnts + * + * This function saves the resource counts for all PCIE and DDR + * resource groups. + * + * @param + * @return + */ +static void ipa_reg_save_rsrc_cnts(void) +{ + union ipa_hwio_def_ipa_src_rsrc_grp_0123_rsrc_type_cnt_n_u + src_0123_rsrc_cnt; + union ipa_hwio_def_ipa_dst_rsrc_grp_0123_rsrc_type_cnt_n_u + dst_0123_rsrc_cnt; + + ipa_reg_save.rsrc_cnts.pcie.resource_group = IPA_HW_PCIE_SRC_RSRP_GRP; + ipa_reg_save.rsrc_cnts.ddr.resource_group = IPA_HW_DDR_SRC_RSRP_GRP; + + src_0123_rsrc_cnt.value = + IPA_READ_1xVECTOR_REG(IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n, 0); + + ipa_reg_save.rsrc_cnts.pcie.src.pkt_cntxt = + src_0123_rsrc_cnt.def.src_rsrc_grp_0_cnt; + ipa_reg_save.rsrc_cnts.ddr.src.pkt_cntxt = + src_0123_rsrc_cnt.def.src_rsrc_grp_1_cnt; + + src_0123_rsrc_cnt.value = + IPA_READ_1xVECTOR_REG(IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n, 1); + + ipa_reg_save.rsrc_cnts.pcie.src.descriptor_list = + src_0123_rsrc_cnt.def.src_rsrc_grp_0_cnt; + ipa_reg_save.rsrc_cnts.ddr.src.descriptor_list = + src_0123_rsrc_cnt.def.src_rsrc_grp_1_cnt; + + src_0123_rsrc_cnt.value = + IPA_READ_1xVECTOR_REG(IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n, 2); + + ipa_reg_save.rsrc_cnts.pcie.src.data_descriptor_buffer = + src_0123_rsrc_cnt.def.src_rsrc_grp_0_cnt; + ipa_reg_save.rsrc_cnts.ddr.src.data_descriptor_buffer = + src_0123_rsrc_cnt.def.src_rsrc_grp_1_cnt; + + src_0123_rsrc_cnt.value = + IPA_READ_1xVECTOR_REG(IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n, 3); + + ipa_reg_save.rsrc_cnts.pcie.src.hps_dmars = + src_0123_rsrc_cnt.def.src_rsrc_grp_0_cnt; + ipa_reg_save.rsrc_cnts.ddr.src.hps_dmars = + src_0123_rsrc_cnt.def.src_rsrc_grp_1_cnt; + + src_0123_rsrc_cnt.value = + IPA_READ_1xVECTOR_REG(IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n, 4); + + ipa_reg_save.rsrc_cnts.pcie.src.reserved_acks = + src_0123_rsrc_cnt.def.src_rsrc_grp_0_cnt; + ipa_reg_save.rsrc_cnts.ddr.src.reserved_acks = + src_0123_rsrc_cnt.def.src_rsrc_grp_1_cnt; + + dst_0123_rsrc_cnt.value = + IPA_READ_1xVECTOR_REG(IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n, 0); + + ipa_reg_save.rsrc_cnts.pcie.dst.reserved_sectors = + dst_0123_rsrc_cnt.def.dst_rsrc_grp_0_cnt; + ipa_reg_save.rsrc_cnts.ddr.dst.reserved_sectors = + dst_0123_rsrc_cnt.def.dst_rsrc_grp_1_cnt; + + dst_0123_rsrc_cnt.value = + IPA_READ_1xVECTOR_REG(IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n, 1); + + ipa_reg_save.rsrc_cnts.pcie.dst.dps_dmars = + dst_0123_rsrc_cnt.def.dst_rsrc_grp_0_cnt; + ipa_reg_save.rsrc_cnts.ddr.dst.dps_dmars = + dst_0123_rsrc_cnt.def.dst_rsrc_grp_1_cnt; +} + +/* + * FUNCTION: ipa_reg_save_rsrc_cnts_test_bus + * + * This function saves the resource counts for all PCIE and DDR + * resource groups collected from test bus. + * + * @param + * + * @return + */ +void ipa_reg_save_rsrc_cnts_test_bus(void) +{ + int32_t rsrc_type = 0; + + ipa_reg_save.rsrc_cnts.pcie.resource_group = IPA_HW_PCIE_SRC_RSRP_GRP; + ipa_reg_save.rsrc_cnts.ddr.resource_group = IPA_HW_DDR_SRC_RSRP_GRP; + + rsrc_type = 0; + ipa_reg_save.rsrc_cnts.pcie.src.pkt_cntxt = + IPA_DEBUG_TESTBUS_GET_RSRC_TYPE_CNT(rsrc_type, + IPA_HW_PCIE_SRC_RSRP_GRP); + + ipa_reg_save.rsrc_cnts.ddr.src.pkt_cntxt = + IPA_DEBUG_TESTBUS_GET_RSRC_TYPE_CNT(rsrc_type, + IPA_HW_DDR_SRC_RSRP_GRP); + + rsrc_type = 1; + ipa_reg_save.rsrc_cnts.pcie.src.descriptor_list = + IPA_DEBUG_TESTBUS_GET_RSRC_TYPE_CNT(rsrc_type, + IPA_HW_PCIE_SRC_RSRP_GRP); + + ipa_reg_save.rsrc_cnts.ddr.src.descriptor_list = + IPA_DEBUG_TESTBUS_GET_RSRC_TYPE_CNT(rsrc_type, + IPA_HW_DDR_SRC_RSRP_GRP); + + rsrc_type = 2; + ipa_reg_save.rsrc_cnts.pcie.src.data_descriptor_buffer = + IPA_DEBUG_TESTBUS_GET_RSRC_TYPE_CNT(rsrc_type, + IPA_HW_PCIE_SRC_RSRP_GRP); + + ipa_reg_save.rsrc_cnts.ddr.src.data_descriptor_buffer = + IPA_DEBUG_TESTBUS_GET_RSRC_TYPE_CNT(rsrc_type, + IPA_HW_DDR_SRC_RSRP_GRP); + + rsrc_type = 3; + ipa_reg_save.rsrc_cnts.pcie.src.hps_dmars = + IPA_DEBUG_TESTBUS_GET_RSRC_TYPE_CNT(rsrc_type, + IPA_HW_PCIE_SRC_RSRP_GRP); + + ipa_reg_save.rsrc_cnts.ddr.src.hps_dmars = + IPA_DEBUG_TESTBUS_GET_RSRC_TYPE_CNT(rsrc_type, + IPA_HW_DDR_SRC_RSRP_GRP); + + rsrc_type = 4; + ipa_reg_save.rsrc_cnts.pcie.src.reserved_acks = + IPA_DEBUG_TESTBUS_GET_RSRC_TYPE_CNT(rsrc_type, + IPA_HW_PCIE_SRC_RSRP_GRP); + + ipa_reg_save.rsrc_cnts.ddr.src.reserved_acks = + IPA_DEBUG_TESTBUS_GET_RSRC_TYPE_CNT(rsrc_type, + IPA_HW_DDR_SRC_RSRP_GRP); + + rsrc_type = 5; + ipa_reg_save.rsrc_cnts.pcie.dst.reserved_sectors = + IPA_DEBUG_TESTBUS_GET_RSRC_TYPE_CNT(rsrc_type, + IPA_HW_PCIE_DEST_RSRP_GRP); + + ipa_reg_save.rsrc_cnts.ddr.dst.reserved_sectors = + IPA_DEBUG_TESTBUS_GET_RSRC_TYPE_CNT(rsrc_type, + IPA_HW_DDR_DEST_RSRP_GRP); + + rsrc_type = 6; + ipa_reg_save.rsrc_cnts.pcie.dst.dps_dmars = + IPA_DEBUG_TESTBUS_GET_RSRC_TYPE_CNT(rsrc_type, + IPA_HW_PCIE_DEST_RSRP_GRP); + + ipa_reg_save.rsrc_cnts.ddr.dst.dps_dmars = + IPA_DEBUG_TESTBUS_GET_RSRC_TYPE_CNT(rsrc_type, + IPA_HW_DDR_DEST_RSRP_GRP); +} + +/* + * FUNCTION: ipa_hal_save_regs_ipa_cmdq + * + * This function saves the various IPA CMDQ registers + * + * @param + * + * @return + */ +static void ipa_hal_save_regs_ipa_cmdq(void) +{ + int32_t i; + union ipa_hwio_def_ipa_rx_hps_cmdq_cmd_u rx_hps_cmdq_cmd = { { 0 } }; + union ipa_hwio_def_ipa_hps_dps_cmdq_cmd_u hps_dps_cmdq_cmd = { { 0 } }; + union ipa_hwio_def_ipa_dps_tx_cmdq_cmd_u dps_tx_cmdq_cmd = { { 0 } }; + union ipa_hwio_def_ipa_ackmngr_cmdq_cmd_u ackmngr_cmdq_cmd = { { 0 } }; + union ipa_hwio_def_ipa_prod_ackmngr_cmdq_cmd_u + prod_ackmngr_cmdq_cmd = { { 0 } }; + union ipa_hwio_def_ipa_ntf_tx_cmdq_cmd_u ntf_tx_cmdq_cmd = { { 0 } }; + + /* Save RX_HPS CMDQ */ + for (i = 0; i < IPA_DEBUG_CMDQ_HPS_SELECT_NUM_GROUPS; i++) { + rx_hps_cmdq_cmd.def.rd_req = 0; + rx_hps_cmdq_cmd.def.cmd_client = i; + IPA_MASKED_WRITE_SCALER_REG(IPA_RX_HPS_CMDQ_CMD, + rx_hps_cmdq_cmd.value); + ipa_reg_save.ipa.dbg.ipa_rx_hps_cmdq_count_arr[i].value = + IPA_READ_SCALER_REG(IPA_RX_HPS_CMDQ_COUNT); + ipa_reg_save.ipa.dbg.ipa_rx_hps_cmdq_status_arr[i].value = + IPA_READ_SCALER_REG(IPA_RX_HPS_CMDQ_STATUS); + rx_hps_cmdq_cmd.def.rd_req = 1; + rx_hps_cmdq_cmd.def.cmd_client = i; + IPA_MASKED_WRITE_SCALER_REG(IPA_RX_HPS_CMDQ_CMD, + rx_hps_cmdq_cmd.value); + ipa_reg_save.ipa.dbg.ipa_rx_hps_cmdq_data_rd_0_arr[i].value = + IPA_READ_SCALER_REG(IPA_RX_HPS_CMDQ_DATA_RD_0); + ipa_reg_save.ipa.dbg.ipa_rx_hps_cmdq_data_rd_1_arr[i].value = + IPA_READ_SCALER_REG(IPA_RX_HPS_CMDQ_DATA_RD_1); + ipa_reg_save.ipa.dbg.ipa_rx_hps_cmdq_data_rd_2_arr[i].value = + IPA_READ_SCALER_REG(IPA_RX_HPS_CMDQ_DATA_RD_2); + ipa_reg_save.ipa.dbg.ipa_rx_hps_cmdq_data_rd_3_arr[i].value = + IPA_READ_SCALER_REG(IPA_RX_HPS_CMDQ_DATA_RD_3); + } + + /* Save HPS_DPS CMDQ */ + for (i = 0; i < IPA_TESTBUS_SEL_EP_MAX + 1; i++) { + hps_dps_cmdq_cmd.def.rd_req = 0; + hps_dps_cmdq_cmd.def.cmd_client = i; + IPA_MASKED_WRITE_SCALER_REG(IPA_HPS_DPS_CMDQ_CMD, + hps_dps_cmdq_cmd.value); + ipa_reg_save.ipa.dbg.ipa_hps_dps_cmdq_status_arr[i].value = + IPA_READ_SCALER_REG(IPA_HPS_DPS_CMDQ_STATUS); + ipa_reg_save.ipa.dbg.ipa_hps_dps_cmdq_count_arr[i].value = + IPA_READ_SCALER_REG(IPA_HPS_DPS_CMDQ_COUNT); + + hps_dps_cmdq_cmd.def.rd_req = 1; + hps_dps_cmdq_cmd.def.cmd_client = i; + IPA_MASKED_WRITE_SCALER_REG(IPA_HPS_DPS_CMDQ_CMD, + hps_dps_cmdq_cmd.value); + ipa_reg_save.ipa.dbg.ipa_hps_dps_cmdq_data_rd_0_arr[i].value = + IPA_READ_SCALER_REG(IPA_HPS_DPS_CMDQ_DATA_RD_0); + } + + /* Save DPS_TX CMDQ */ + for (i = 0; i < IPA_DEBUG_CMDQ_DPS_SELECT_NUM_GROUPS; i++) { + dps_tx_cmdq_cmd.def.cmd_client = i; + dps_tx_cmdq_cmd.def.rd_req = 0; + IPA_MASKED_WRITE_SCALER_REG(IPA_DPS_TX_CMDQ_CMD, + dps_tx_cmdq_cmd.value); + ipa_reg_save.ipa.dbg.ipa_dps_tx_cmdq_status_arr[i].value = + IPA_READ_SCALER_REG(IPA_DPS_TX_CMDQ_STATUS); + ipa_reg_save.ipa.dbg.ipa_dps_tx_cmdq_count_arr[i].value = + IPA_READ_SCALER_REG(IPA_DPS_TX_CMDQ_COUNT); + + dps_tx_cmdq_cmd.def.cmd_client = i; + dps_tx_cmdq_cmd.def.rd_req = 1; + IPA_MASKED_WRITE_SCALER_REG(IPA_DPS_TX_CMDQ_CMD, + dps_tx_cmdq_cmd.value); + ipa_reg_save.ipa.dbg.ipa_dps_tx_cmdq_data_rd_0_arr[i].value = + IPA_READ_SCALER_REG(IPA_DPS_TX_CMDQ_DATA_RD_0); + } + + /* Save ACKMNGR CMDQ */ + for (i = 0; i < IPA_DEBUG_CMDQ_DPS_SELECT_NUM_GROUPS; i++) { + ackmngr_cmdq_cmd.def.rd_req = 0; + ackmngr_cmdq_cmd.def.cmd_client = i; + IPA_MASKED_WRITE_SCALER_REG(IPA_ACKMNGR_CMDQ_CMD, + ackmngr_cmdq_cmd.value); + ipa_reg_save.ipa.dbg.ipa_ackmngr_cmdq_status_arr[i].value = + IPA_READ_SCALER_REG(IPA_ACKMNGR_CMDQ_STATUS); + ipa_reg_save.ipa.dbg.ipa_ackmngr_cmdq_count_arr[i].value = + IPA_READ_SCALER_REG(IPA_ACKMNGR_CMDQ_COUNT); + + ackmngr_cmdq_cmd.def.rd_req = 1; + ackmngr_cmdq_cmd.def.cmd_client = i; + IPA_MASKED_WRITE_SCALER_REG(IPA_ACKMNGR_CMDQ_CMD, + ackmngr_cmdq_cmd.value); + ipa_reg_save.ipa.dbg.ipa_ackmngr_cmdq_data_rd_arr[i].value = + IPA_READ_SCALER_REG(IPA_ACKMNGR_CMDQ_DATA_RD); + } + + /* Save PROD ACKMNGR CMDQ */ + for (i = 0; i < IPA_TESTBUS_SEL_EP_MAX + 1; i++) { + prod_ackmngr_cmdq_cmd.def.rd_req = 0; + prod_ackmngr_cmdq_cmd.def.cmd_client = i; + IPA_MASKED_WRITE_SCALER_REG(IPA_PROD_ACKMNGR_CMDQ_CMD, + prod_ackmngr_cmdq_cmd.value); + ipa_reg_save.ipa.dbg.ipa_prod_ackmngr_cmdq_status_arr[i].value + = IPA_READ_SCALER_REG( + IPA_PROD_ACKMNGR_CMDQ_STATUS); + ipa_reg_save.ipa.dbg.ipa_prod_ackmngr_cmdq_count_arr[i].value = + IPA_READ_SCALER_REG(IPA_PROD_ACKMNGR_CMDQ_COUNT); + prod_ackmngr_cmdq_cmd.def.rd_req = 1; + prod_ackmngr_cmdq_cmd.def.cmd_client = i; + IPA_MASKED_WRITE_SCALER_REG(IPA_PROD_ACKMNGR_CMDQ_CMD, + prod_ackmngr_cmdq_cmd.value); + ipa_reg_save.ipa.dbg.ipa_prod_ackmngr_cmdq_data_rd_arr[ + i].value = + IPA_READ_SCALER_REG( + IPA_PROD_ACKMNGR_CMDQ_DATA_RD); + } + + /* Save NTF_TX CMDQ */ + for (i = 0; i < IPA_TESTBUS_SEL_EP_MAX + 1; i++) { + ntf_tx_cmdq_cmd.def.rd_req = 0; + ntf_tx_cmdq_cmd.def.cmd_client = i; + IPA_MASKED_WRITE_SCALER_REG(IPA_NTF_TX_CMDQ_CMD, + ntf_tx_cmdq_cmd.value); + ipa_reg_save.ipa.dbg.ipa_ntf_tx_cmdq_status_arr[i].value = + IPA_READ_SCALER_REG(IPA_NTF_TX_CMDQ_STATUS); + ipa_reg_save.ipa.dbg.ipa_ntf_tx_cmdq_count_arr[i].value = + IPA_READ_SCALER_REG(IPA_NTF_TX_CMDQ_COUNT); + ntf_tx_cmdq_cmd.def.rd_req = 1; + ntf_tx_cmdq_cmd.def.cmd_client = i; + IPA_MASKED_WRITE_SCALER_REG(IPA_NTF_TX_CMDQ_CMD, + ntf_tx_cmdq_cmd.value); + ipa_reg_save.ipa.dbg.ipa_ntf_tx_cmdq_data_rd_0_arr[i].value = + IPA_READ_SCALER_REG(IPA_NTF_TX_CMDQ_DATA_RD_0); + } +} + +/* + * FUNCTION: ipa_hal_save_regs_save_ipa_testbus + * + * This function saves the IPA testbus + * + * @param + * + * @return + */ +static void ipa_hal_save_regs_save_ipa_testbus(void) +{ + s32 sel_internal, sel_external, sel_ep; + union ipa_hwio_def_ipa_testbus_sel_u testbus_sel = { { 0 } }; + + if (ipa_reg_save.ipa.testbus == NULL) { + /* + * Test-bus structure not allocated - exit test-bus collection + */ + IPADBG("ipa_reg_save.ipa.testbus was not allocated\n"); + return; + } + + /* Enable Test-bus */ + testbus_sel.value = 0; + testbus_sel.def.testbus_en = true; + + IPA_WRITE_SCALER_REG(IPA_TESTBUS_SEL, testbus_sel.value); + + for (sel_external = 0; + sel_external <= IPA_TESTBUS_SEL_EXTERNAL_MAX; + sel_external++) { + + for (sel_internal = 0; + sel_internal <= IPA_TESTBUS_SEL_INTERNAL_MAX; + sel_internal++) { + + testbus_sel.value = 0; +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + testbus_sel.def.pipe_select = 0; +#endif + testbus_sel.def.external_block_select = + sel_external; + testbus_sel.def.internal_block_select = + sel_internal; + + IPA_MASKED_WRITE_SCALER_REG( + IPA_TESTBUS_SEL, + testbus_sel.value); + + ipa_reg_save.ipa.testbus->global.global[ + sel_internal][sel_external].testbus_sel.value = + testbus_sel.value; + + ipa_reg_save.ipa.testbus->global.global[ + sel_internal][sel_external].testbus_data.value = + IPA_READ_SCALER_REG(IPA_DEBUG_DATA); + } + } + + /* Collect per EP test bus */ + for (sel_ep = 0; + sel_ep <= IPA_TESTBUS_SEL_EP_MAX; + sel_ep++) { + + for (sel_external = 0; + sel_external <= + IPA_TESTBUS_SEL_EXTERNAL_MAX; + sel_external++) { + + for (sel_internal = 0; + sel_internal <= + IPA_TESTBUS_SEL_INTERNAL_PIPE_MAX; + sel_internal++) { + + testbus_sel.value = 0; +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + testbus_sel.def.pipe_select = sel_ep; +#endif + testbus_sel.def.external_block_select = + sel_external; + testbus_sel.def.internal_block_select = + sel_internal; + + IPA_MASKED_WRITE_SCALER_REG( + IPA_TESTBUS_SEL, + testbus_sel.value); + + ipa_reg_save.ipa.testbus->ep[sel_ep].entry_ep[ + sel_internal][sel_external]. + testbus_sel.value = + testbus_sel.value; + + ipa_reg_save.ipa.testbus->ep[sel_ep].entry_ep[ + sel_internal][sel_external]. + testbus_data.value = + IPA_READ_SCALER_REG( + IPA_DEBUG_DATA); + } + } + } + + /* Disable Test-bus */ + testbus_sel.value = 0; + + IPA_WRITE_SCALER_REG( + IPA_TESTBUS_SEL, + testbus_sel.value); +} + +/* + * FUNCTION: ipa_reg_save_init + * + * This function initializes and memsets the register save struct. + * + * @param + * + * @return + */ +int ipa_reg_save_init(u32 value) +{ + u32 i, num_regs = ARRAY_SIZE(ipa_regs_to_save_array); +#if IS_ENABLED(CONFIG_QCOM_VA_MINIDUMP) + struct ipa_minidump_data *mini_dump; +#endif + if (!ipa3_ctx->do_register_collection_on_crash) + return 0; + + memset(&ipa_reg_save, value, sizeof(ipa_reg_save)); + + ipa_reg_save.ipa.testbus = NULL; + + if (ipa3_ctx->do_testbus_collection_on_crash) { + memset(ipa_testbus_mem, value, sizeof(ipa_testbus_mem)); + ipa_reg_save.ipa.testbus = + (struct ipa_reg_save_ipa_testbus_s *) ipa_testbus_mem; + } + + /* setup access for register collection/dump on crash */ + IPADBG("Mapping 0x%x bytes starting at 0x%x\n", + ipa3_ctx->entire_ipa_block_size, + ipa3_ctx->ipa_wrapper_base); + + ipa3_ctx->reg_collection_base = + ioremap(ipa3_ctx->ipa_wrapper_base, + ipa3_ctx->entire_ipa_block_size); + + if (!ipa3_ctx->reg_collection_base) { + IPAERR(":register collection ioremap err\n"); + goto alloc_fail1; + } + + num_regs -= + (CONFIG_IPA3_REGDUMP_NUM_EXTRA_ENDP_REGS * + IPA_REG_SAVE_NUM_EXTRA_ENDP_REGS); + + for (i = 0; + i < (CONFIG_IPA3_REGDUMP_NUM_EXTRA_ENDP_REGS * + IPA_REG_SAVE_NUM_EXTRA_ENDP_REGS); + i++) + *(ipa_regs_to_save_array[num_regs + i].dst_addr) = 0x0; + + ipa_reg_save.ipa.ipa_gsi_ptr = NULL; + ipa_reg_save.ipa.ipa_seq_ptr = NULL; + ipa_reg_save.ipa.ipa_hram_ptr = NULL; + ipa_reg_save.ipa.ipa_mbox_ptr = NULL; + ipa_reg_save.ipa.ipa_sram_ptr = NULL; + ipa_reg_save.ipa.ipa_iu_ptr = NULL; + + if (ipa3_ctx->do_ram_collection_on_crash) { + ipa_reg_save.ipa.ipa_iu_ptr = + alloc_and_init(IPA_IU_SIZE, value); + if (!ipa_reg_save.ipa.ipa_iu_ptr) { + IPAERR("ipa_iu_ptr memory alloc failed\n"); + goto alloc_fail2; + } + + ipa_reg_save.ipa.ipa_sram_ptr = + alloc_and_init(IPA_SRAM_SIZE, value); + if (!ipa_reg_save.ipa.ipa_sram_ptr) { + IPAERR("ipa_sram_ptr memory alloc failed\n"); + goto alloc_fail2; + } + + ipa_reg_save.ipa.ipa_mbox_ptr = + alloc_and_init(IPA_MBOX_SIZE, value); + if (!ipa_reg_save.ipa.ipa_mbox_ptr) { + IPAERR("ipa_mbox_ptr memory alloc failed\n"); + goto alloc_fail2; + } + + ipa_reg_save.ipa.ipa_hram_ptr = + alloc_and_init(IPA_HRAM_SIZE, value); + if (!ipa_reg_save.ipa.ipa_hram_ptr) { + IPAERR("ipa_hram_ptr memory alloc failed\n"); + goto alloc_fail2; + } + + ipa_reg_save.ipa.ipa_seq_ptr = + alloc_and_init(IPA_SEQ_SIZE, value); + if (!ipa_reg_save.ipa.ipa_seq_ptr) { + IPAERR("ipa_seq_ptr memory alloc failed\n"); + goto alloc_fail2; + } + + ipa_reg_save.ipa.ipa_gsi_ptr = + alloc_and_init(IPA_GSI_SIZE, value); + if (!ipa_reg_save.ipa.ipa_gsi_ptr) { + IPAERR("ipa_gsi_ptr memory alloc failed\n"); + goto alloc_fail2; + } + } +#if IS_ENABLED(CONFIG_QCOM_VA_MINIDUMP) + /*Adding ipa_reg_save pointer to minidump list*/ + mini_dump = (struct ipa_minidump_data *)kzalloc(sizeof(struct ipa_minidump_data), GFP_KERNEL); + if (mini_dump != NULL) { + strlcpy(mini_dump->data.owner, "ipa_reg_save", sizeof(mini_dump->data.owner)); + mini_dump->data.vaddr = (unsigned long)&ipa_reg_save; + mini_dump->data.size = sizeof(ipa_reg_save); + list_add(&mini_dump->entry, &ipa3_ctx->minidump_list_head); + } +#endif + return 0; + +alloc_fail2: + kfree(ipa_reg_save.ipa.ipa_seq_ptr); + kfree(ipa_reg_save.ipa.ipa_hram_ptr); + kfree(ipa_reg_save.ipa.ipa_mbox_ptr); + kfree(ipa_reg_save.ipa.ipa_sram_ptr); + kfree(ipa_reg_save.ipa.ipa_iu_ptr); + iounmap(ipa3_ctx->reg_collection_base); +alloc_fail1: + return -ENOMEM; +} + +/* + * FUNCTION: ipa_hal_save_regs_rsrc_db + * + * This function saves the various IPA RSRC_MNGR_DB registers + * + * @param + * + * @return + */ +static void ipa_hal_save_regs_rsrc_db(void) +{ + u32 rsrc_type = 0; + u32 rsrc_id = 0; + u32 rsrc_group = 0; + union ipa_hwio_def_ipa_rsrc_mngr_db_cfg_u + ipa_rsrc_mngr_db_cfg = { { 0 } }; + + ipa_rsrc_mngr_db_cfg.def.rsrc_grp_sel = rsrc_group; + + for (rsrc_type = 0; rsrc_type <= IPA_RSCR_MNGR_DB_RSRC_TYPE_MAX; + rsrc_type++) { + for (rsrc_id = 0; rsrc_id <= IPA_RSCR_MNGR_DB_RSRC_ID_MAX; + rsrc_id++) { + ipa_rsrc_mngr_db_cfg.def.rsrc_id_sel = rsrc_id; + ipa_rsrc_mngr_db_cfg.def.rsrc_type_sel = rsrc_type; + IPA_MASKED_WRITE_SCALER_REG(IPA_RSRC_MNGR_DB_CFG, + ipa_rsrc_mngr_db_cfg.value); + ipa_reg_save.ipa.dbg.ipa_rsrc_mngr_db_rsrc_read_arr + [rsrc_type][rsrc_id].value = + IPA_READ_SCALER_REG( + IPA_RSRC_MNGR_DB_RSRC_READ); + ipa_reg_save.ipa.dbg.ipa_rsrc_mngr_db_list_read_arr + [rsrc_type][rsrc_id].value = + IPA_READ_SCALER_REG( + IPA_RSRC_MNGR_DB_LIST_READ); + } + } +} + +/* + * FUNCTION: ipa_reg_save_anomaly_check + * + * Checks RX state and TX state upon crash dump collection and prints + * anomalies. + * + * TBD- Add more anomaly checks in the future. + * + * @return + */ +static void ipa_reg_save_anomaly_check(void) +{ + if ((ipa_reg_save.ipa.gen.ipa_state.rx_wait != 0) + || (ipa_reg_save.ipa.gen.ipa_state.rx_idle != 1)) { +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + IPADBG( + "RX ACTIVITY, ipa_state.rx_wait = %d, ipa_state.rx_idle = %d, ipa_state_rx_active.endpoints = %d (bitmask)\n", + ipa_reg_save.ipa.gen.ipa_state.rx_wait, + ipa_reg_save.ipa.gen.ipa_state.rx_idle, + ipa_reg_save.ipa.gen.ipa_state_rx_active.endpoints); +#else + int i = 0; + + for (i = 0; i < GEN_MAX_n(IPA_STATE_RX_ACTIVE_n) + 1; i++) { + IPADBG( + "RX ACTIVITY_%d, ipa_state.rx_wait = %d, ipa_state.rx_idle = %d, ipa_state_rx_active.endpoints = %d (bitmask)\n", + i, + ipa_reg_save.ipa.gen.ipa_state.rx_wait, + ipa_reg_save.ipa.gen.ipa_state.rx_idle, + ipa_reg_save.ipa.gen.ipa_state_rx_active_n[i].endpoints); + } +#endif + + if (ipa_reg_save.ipa.gen.ipa_state.tx_idle != 1) { + IPADBG( + "TX ACTIVITY, ipa_state.idle = %d, ipa_state_tx_wrapper.tx0_idle = %d, ipa_state_tx_wrapper.tx1_idle = %d\n", + ipa_reg_save.ipa.gen.ipa_state.tx_idle, + ipa_reg_save.ipa.gen.ipa_state_tx_wrapper.tx0_idle, + ipa_reg_save.ipa.gen.ipa_state_tx_wrapper.tx1_idle); +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + IPADBG( + "ipa_state_tx0.last_cmd_pipe = %d, ipa_state_tx1.last_cmd_pipe = %d\n", + ipa_reg_save.ipa.gen.ipa_state_tx0.last_cmd_pipe, + ipa_reg_save.ipa.gen.ipa_state_tx1.last_cmd_pipe); +#endif + } + } +} diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.5/ipa_reg_dump.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.5/ipa_reg_dump.h new file mode 100644 index 0000000000..3e67d3c8a8 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.5/ipa_reg_dump.h @@ -0,0 +1,2162 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + */ +#if !defined(_IPA_REG_DUMP_H_) +#define _IPA_REG_DUMP_H_ + +#include +#include + +#include "ipa_i.h" +#include "gsihal.h" +#include "gsihal_reg.h" + +#include "ipa_pkt_cntxt.h" +#include "ipa_hw_common_ex.h" + +#define IPA_0_IPA_WRAPPER_BASE 0 /* required by following includes */ + +#include "ipa_hwio.h" +#include "gsi_hwio.h" +#include "ipa_gcc_hwio.h" + +#include "ipa_hwio_def.h" +#include "gsi_hwio_def.h" +#include "ipa_gcc_hwio_def.h" + +#define IPA_DEBUG_CMDQ_DPS_SELECT_NUM_GROUPS 0x6 +#define IPA_DEBUG_CMDQ_HPS_SELECT_NUM_GROUPS 0x4 +#define IPA_DEBUG_TESTBUS_RSRC_NUM_EP 7 +#define IPA_DEBUG_TESTBUS_RSRC_NUM_GRP 3 +#define IPA_TESTBUS_SEL_EP_MAX 0x1F +#define IPA_TESTBUS_SEL_EXTERNAL_MAX 0x40 +#define IPA_TESTBUS_SEL_INTERNAL_MAX 0xFF +#define IPA_TESTBUS_SEL_INTERNAL_PIPE_MAX 0x40 +#define IPA_DEBUG_CMDQ_ACK_SELECT_NUM_GROUPS 0x9 +#define IPA_RSCR_MNGR_DB_RSRC_ID_MAX 0x3F +#define IPA_RSCR_MNGR_DB_RSRC_TYPE_MAX 0xA +#define IPA_REG_SAVE_FC_STATE_OFFSET 7 +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_ZEROS (0x0) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MCS_0 (0x1) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MCS_1 (0x2) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MCS_2 (0x3) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MCS_3 (0x4) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MCS_4 (0x5) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_DB_ENG (0x9) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_0 (0xB) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_1 (0xC) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_2 (0xD) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_3 (0xE) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_4 (0xF) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_5 (0x10) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_6 (0x11) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_7 (0x12) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_EVE_0 (0x13) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_EVE_1 (0x14) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_EVE_2 (0x15) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_EVE_3 (0x16) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_EVE_4 (0x17) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_EVE_5 (0x18) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IE_0 (0x1B) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IE_1 (0x1C) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IC_0 (0x1F) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IC_1 (0x20) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IC_2 (0x21) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IC_3 (0x22) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IC_4 (0x23) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MOQA_0 (0x27) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MOQA_1 (0x28) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MOQA_2 (0x29) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MOQA_3 (0x2A) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_TMR_0 (0x2B) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_TMR_1 (0x2C) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_TMR_2 (0x2D) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_TMR_3 (0x2E) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_RD_WR_0 (0x33) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_RD_WR_1 (0x34) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_RD_WR_2 (0x35) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_RD_WR_3 (0x36) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_CSR (0x3A) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_SDMA_0 (0x3C) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_SDMA_1 (0x3D) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IE_2 (0x1D) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_CSR_1 (0x3E) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_CSR_2 (0x3F) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MCS_5 (0x40) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IC_5 (0x41) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_CSR_3 (0x42) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_TLV_0 (0x43) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_8 (0x44) +#define IPA_DEBUG_TESTBUS_DEF_EXTERNAL 50 +#define IPA_DEBUG_TESTBUS_DEF_INTERNAL 6 +#define IPA_REG_SAVE_GSI_NUM_EE 3 +#define IPA_REG_SAVE_NUM_EXTRA_ENDP_REGS 22 +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 +#define IPA_GSI_OFFSET_WORDS_SCRATCH_FOR_SEQ_LOW 18 +#define IPA_GSI_OFFSET_WORDS_SCRATCH_FOR_SEQ_HIGH 19 +#else +#define IPA_GSI_OFFSET_WORDS_SCRATCH_FOR_SEQ_LOW 6 +#define IPA_GSI_OFFSET_WORDS_SCRATCH_FOR_SEQ_HIGH 7 +#endif +#define IPA_DEBUG_TESTBUS_RSRC_TYPE_CNT_BIT_MASK 0x7E000 +#define IPA_DEBUG_TESTBUS_RSRC_TYPE_CNT_SHIFT 13 +#define IPA_REG_SAVE_HWP_GSI_EE 2 +#define GSI_HW_DEBUG_SW_MSK_REG_ARRAY_LENGTH 9 +#define GSI_HW_DEBUG_SW_MSK_REG_MAXk 2 + +/* + * A structure used to map a source address to destination address... + */ +struct map_src_dst_addr_s { + u32 src_addr; /* register offset to copy value from */ + u32 *dst_addr; /* memory address to copy register value to */ + u8 perm; /* r\w permission as parsed from hwio */ +}; + +/* a macro to generate a number of MAX n allowed in a register + * who has suffix of _n + */ +#define GEN_MAX_n(reg_name) \ + HWIO_ ## reg_name ## _MAXn + +/* a macro to generate a number of MAX k allowed in a register + * who has suffix of _k + */ +#define GEN_MAX_k(reg_name) \ + HWIO_ ## reg_name ## _MAXk + +/* + * A macro to generate the names of scaler (ie. non-vector) registers + * that reside in the *hwio.h files (said files contain the manifest + * constants for the registers' offsets in the register memory map). + */ +#define GEN_SCALER_REG_OFST(reg_name) \ + (HWIO_ ## reg_name ## _ADDR) + +/* + * A macro designed to generate the rmsk associated with reg_name + */ +#define GEN_SCALER_REG_RMSK(reg_name) \ + (HWIO_ ## reg_name ## _RMSK) + +/* + * A macro designed to generate the attr associated with reg_name + * this is actually r\w permissions, bits [1][0] ==> [W][R] + */ +#define REG_READ_PERM BIT(0) +#define REG_WRITE_PERM BIT(1) +#define GEN_REG_ATTR(reg_name) \ + (HWIO_ ## reg_name ## _ATTR) + +/* + * A macro to generate the names of vector registers that reside in + * the *hwio.h files (said files contain the manifest constants for + * the registers' offsets in the register memory map). More + * specifically, this macro will generate access to registers that are + * addressed via one dimension. + */ +#define GEN_1xVECTOR_REG_OFST(reg_name, row) \ + (HWIO_ ## reg_name ## _ADDR(row)) + +/* + * A macro to generate the names of vector registers that reside in + * the *hwio.h files (said files contain the manifest constants for + * the registers' offsets in the register memory map). More + * specifically, this macro will generate access to registers that are + * addressed via two dimensions. + */ +#define GEN_2xVECTOR_REG_OFST(reg_name, row, col) \ + (HWIO_ ## reg_name ## _ADDR(row, col)) + +/* + * A macro to generate the access to scaler registers that reside in + * the *hwio.h files (said files contain the manifest constants for + * the registers' offsets in the register memory map). More + * specifically, this macro will generate read access from a scaler + * register.. + */ +#define IPA_READ_SCALER_REG(reg_name) \ + HWIO_ ## reg_name ## _IN + +/* + * A macro to generate the access to vector registers that reside in + * the *hwio.h files (said files contain the manifest constants for + * the registers' offsets in the register memory map). More + * specifically, this macro will generate read access from a one + * dimensional vector register... + */ +#define IPA_READ_1xVECTOR_REG(reg_name, row) \ + HWIO_ ## reg_name ## _INI(row) + +/* + * A macro to generate the access to vector registers that reside in + * the *hwio.h files (said files contain the manifest constants for + * the registers' offsets in the register memory map). More + * specifically, this macro will generate read access from a two + * dimensional vector register... + */ +#define IPA_READ_2xVECTOR_REG(reg_name, row, col) \ + HWIO_ ## reg_name ## _INI2(row, col) + +/* + * A macro to generate the access to scaler registers that reside in + * the *hwio.h files (said files contain the manifest constants for + * the registers' offsets in the register memory map). More + * specifically, this macro will generate write access to a scaler + * register.. + */ +#define IPA_WRITE_SCALER_REG(reg_name, val) \ + HWIO_ ## reg_name ## _OUT(val) + +/* + * Similar to the above, but with val masked by the register's rmsk... + */ +#define IPA_MASKED_WRITE_SCALER_REG(reg_name, val) \ + out_dword(GEN_SCALER_REG_OFST(reg_name), \ + (GEN_SCALER_REG_RMSK(reg_name) & val), \ + GEN_REG_ATTR(reg_name)) + +/* + * A macro to generate the access to vector registers that reside in + * the *hwio.h files (said files contain the manifest constants for + * the registers' offsets in the register memory map). More + * specifically, this macro will generate write access to a one + * dimensional vector register... + */ +#define IPA_WRITE_1xVECTOR_REG(reg_name, row, val) \ + HWIO_ ## reg_name ## _OUTI(row, val) + +/* + * A macro to generate the access to vector registers that reside in + * the *hwio.h files (said files contain the manifest constants for + * the registers' offsets in the register memory map). More + * specifically, this macro will generate write access to a two + * dimensional vector register... + */ +#define IPA_WRITE_2xVECTOR_REG(reg_name, row, col, val) \ + HWIO_ ## reg_name ## _OUTI2(row, col, val) + + /* + * Macro that helps generate a mapping between a register's address + * and where the register's value will get stored (ie. source and + * destination address mapping) upon dump... + */ +#define GEN_SRC_DST_ADDR_MAP(reg_name, sub_struct, field_name) \ + { GEN_SCALER_REG_OFST(reg_name), \ + (u32 *)&ipa_reg_save.sub_struct.field_name , \ + GEN_REG_ATTR(reg_name) } + +/* + * Macro to get value of bits 18:13, used tp get rsrc cnts from + * IPA_DEBUG_DATA + */ +#define IPA_DEBUG_TESTBUS_DATA_GET_RSRC_CNT_BITS_FROM_DEBUG_DATA(x) \ + ((x & IPA_DEBUG_TESTBUS_RSRC_TYPE_CNT_BIT_MASK) >> \ + IPA_DEBUG_TESTBUS_RSRC_TYPE_CNT_SHIFT) + +/* + * Macro to get rsrc cnt of specific rsrc type and rsrc grp from test + * bus collected data + */ +#define IPA_DEBUG_TESTBUS_GET_RSRC_TYPE_CNT(rsrc_type, rsrc_grp) \ + IPA_DEBUG_TESTBUS_DATA_GET_RSRC_CNT_BITS_FROM_DEBUG_DATA( \ + ipa_reg_save.ipa.testbus->ep_rsrc[rsrc_type].entry_ep \ + [rsrc_grp].testbus_data.value) + +/* + * Macro to pluck the gsi version from ram. + */ +#define IPA_REG_SAVE_GSI_VER(reg_name, var_name) \ + { GEN_1xVECTOR_REG_OFST(reg_name, 0), \ + (u32 *)&ipa_reg_save.gsi.gen.var_name,\ + GEN_REG_ATTR(reg_name) } +/* + * Macro to define a particular register cfg entry for all 3 EE + * indexed register + */ +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 +#define IPA_REG_SAVE_CFG_ENTRY_GEN_EE(reg_name, var_name) \ + { GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE), \ + (u32 *)&ipa_reg_save.ipa.gen_ee[IPA_HW_Q6_EE].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE), \ + (u32 *)&ipa_reg_save.ipa.gen_ee[IPA_HW_A7_EE].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_UC_EE), \ + (u32 *)&ipa_reg_save.ipa.gen_ee[IPA_HW_UC_EE].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_HWP_EE), \ + (u32 *)&ipa_reg_save.ipa.gen_ee[IPA_HW_HWP_EE].var_name, \ + GEN_REG_ATTR(reg_name) } +#else +#define IPA_REG_SAVE_CFG_ENTRY_GEN_EE(reg_name, var_name) \ + { GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE), \ + (u32 *)&ipa_reg_save.ipa.gen_ee[IPA_HW_Q6_EE].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE), \ + (u32 *)&ipa_reg_save.ipa.gen_ee[IPA_HW_A7_EE].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_HWP_EE), \ + (u32 *)&ipa_reg_save.ipa.gen_ee[IPA_HW_HWP_EE].var_name, \ + GEN_REG_ATTR(reg_name) } +#endif + +#define IPA_REG_SAVE_CFG_ENTRY_GSI_FIFO(reg_name, var_name, index) \ + { GEN_SCALER_REG_OFST(reg_name), \ + (u32 *)&ipa_reg_save.ipa.gsi_fifo_status[index].var_name, \ + GEN_REG_ATTR(reg_name) } + +/* + * Macro to define a particular register cfg entry for all pipe + * indexed register + */ +#define IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(reg_name, var_name) \ + { 0, 0 } + +/* + * Macro to define a particular register cfg entry for all resource + * group register + */ +#define IPA_REG_SAVE_CFG_ENTRY_SRC_RSRC_GRP(reg_name, var_name) \ + { GEN_1xVECTOR_REG_OFST(reg_name, 0), \ + (u32 *)&ipa_reg_save.ipa.src_rsrc_grp[0].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 1), \ + (u32 *)&ipa_reg_save.ipa.src_rsrc_grp[1].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 2), \ + (u32 *)&ipa_reg_save.ipa.src_rsrc_grp[2].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 3), \ + (u32 *)&ipa_reg_save.ipa.src_rsrc_grp[3].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 4), \ + (u32 *)&ipa_reg_save.ipa.src_rsrc_grp[4].var_name, \ + GEN_REG_ATTR(reg_name) } + +/* + * Macro to define a particular register cfg entry for all resource + * group register + */ +#define IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_GRP(reg_name, var_name) \ + { GEN_1xVECTOR_REG_OFST(reg_name, 0), \ + (u32 *)&ipa_reg_save.ipa.dst_rsrc_grp[0].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 1), \ + (u32 *)&ipa_reg_save.ipa.dst_rsrc_grp[1].var_name, \ + GEN_REG_ATTR(reg_name) } + +/* + * Macro to define a particular register cfg entry for all source + * resource group count register + */ +#define IPA_REG_SAVE_CFG_ENTRY_SRC_RSRC_CNT_GRP(reg_name, var_name) \ + { GEN_1xVECTOR_REG_OFST(reg_name, 0), \ + (u32 *)&ipa_reg_save.ipa.src_rsrc_cnt[0].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 1), \ + (u32 *)&ipa_reg_save.ipa.src_rsrc_cnt[1].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 2), \ + (u32 *)&ipa_reg_save.ipa.src_rsrc_cnt[2].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 3), \ + (u32 *)&ipa_reg_save.ipa.src_rsrc_cnt[3].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 4), \ + (u32 *)&ipa_reg_save.ipa.src_rsrc_cnt[4].var_name, \ + GEN_REG_ATTR(reg_name) } + +/* + * Macro to define a particular register cfg entry for all dest + * resource group count register + */ +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 +#define IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_CNT_GRP(reg_name, var_name) \ + { GEN_1xVECTOR_REG_OFST(reg_name, 0), \ + (u32 *)&ipa_reg_save.ipa.dst_rsrc_cnt[0].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 1), \ + (u32 *)&ipa_reg_save.ipa.dst_rsrc_cnt[1].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 2), \ + (u32 *)&ipa_reg_save.ipa.dst_rsrc_cnt[2].var_name, \ + GEN_REG_ATTR(reg_name) } +#else +#define IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_CNT_GRP(reg_name, var_name) \ + { GEN_1xVECTOR_REG_OFST(reg_name, 0), \ + (u32 *)&ipa_reg_save.ipa.dst_rsrc_cnt[0].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 1), \ + (u32 *)&ipa_reg_save.ipa.dst_rsrc_cnt[1].var_name, \ + GEN_REG_ATTR(reg_name) } +#endif + +#define IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(reg_name, var_name) \ + { GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE), \ + (u32 *)&ipa_reg_save.gsi.gen_ee[IPA_HW_A7_EE].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE), \ + (u32 *)&ipa_reg_save.gsi.gen_ee[IPA_HW_Q6_EE].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE), \ + (u32 *)&ipa_reg_save.gsi.gen_ee[IPA_REG_SAVE_HWP_GSI_EE].\ + var_name, \ + GEN_REG_ATTR(reg_name) } + +/* + * Macro to define a particular register cfg entry for all GSI EE + * register + */ +#define IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(reg_name, var_name) \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 0), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[0].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 1), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[1].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 2), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[2].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 3), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[3].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 4), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[4].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 5), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[5].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 6), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[6].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 7), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[7].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 8), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[8].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 9), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[9].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 10), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[10].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 11), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[11].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 12), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[12].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 13), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[13].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 14), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[14].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 15), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[15].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 16), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[16].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 17), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[17].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 18), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[18].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 19), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[19].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 1), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[0].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 3), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[1].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 0), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[0].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 1), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[1].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 2), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[2].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 3), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[3].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 4), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[4].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 5), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[5].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 6), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[6].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 7), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[7].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 8), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[8].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 9), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[9].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 10), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[10].var_name, \ + GEN_REG_ATTR(reg_name) } + +/* + * Macro to define a debug SW MSK register entry for all (n, k) + * k bound by GSI_HW_DEBUG_SW_MSK_REG_MAXk + */ +#define IPA_REG_SAVE_GSI_DEBUG_MSK_REG_ENTRY(reg_name, var_name) \ + { GEN_2xVECTOR_REG_OFST(reg_name, 0, 0), \ + (u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[0].var_name[0], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, 0, 1), \ + (u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[0].var_name[1], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, 1, 0), \ + (u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[1].var_name[0], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, 1, 1), \ + (u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[1].var_name[1], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, 2, 0), \ + (u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[2].var_name[0], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, 2, 1), \ + (u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[2].var_name[1], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, 3, 0), \ + (u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[3].var_name[0], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, 3, 1), \ + (u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[3].var_name[1], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, 4, 0), \ + (u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[4].var_name[0], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, 4, 1), \ + (u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[4].var_name[1], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, 5, 0), \ + (u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[5].var_name[0], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, 5, 1), \ + (u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[5].var_name[1], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, 6, 0), \ + (u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[6].var_name[0], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, 6, 1), \ + (u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[6].var_name[1], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, 7, 0), \ + (u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[7].var_name[0], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, 7, 1), \ + (u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[7].var_name[1], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, 8, 0), \ + (u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[8].var_name[0], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, 8, 1), \ + (u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[8].var_name[1], \ + GEN_REG_ATTR(reg_name) } + +#define IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(reg_name, var_name) \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 0), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[0].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 1), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[1].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 2), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[2].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 3), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[3].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 4), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[4].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 5), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[5].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 6), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[6].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 7), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[7].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 8), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[8].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 9), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[9].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 10), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[10].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 11), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[11].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 12), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[12].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 13), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[13].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 14), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[14].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 15), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[15].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 16), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[16].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 17), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[17].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 18), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[18].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 1), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.uc[0].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 0), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[0].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 1), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[1].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 2), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[2].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 3), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[3].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 4), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[4].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 5), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[5].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 6), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[6].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 7), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[7].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 8), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[8].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 9), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[9].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 10), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[10].var_name, \ + GEN_REG_ATTR(reg_name) } + +/* + * Macro to define a particular register cfg entry for GSI QSB debug + * registers + */ +#define IPA_REG_SAVE_CFG_ENTRY_GSI_QSB_DEBUG(reg_name, var_name) \ + { GEN_1xVECTOR_REG_OFST(reg_name, 0), \ + (u32 *)&ipa_reg_save.gsi.debug.gsi_qsb_debug.var_name[0], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 1), \ + (u32 *)&ipa_reg_save.gsi.debug.gsi_qsb_debug.var_name[1], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 2), \ + (u32 *)&ipa_reg_save.gsi.debug.gsi_qsb_debug.var_name[2], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 3), \ + (u32 *)&ipa_reg_save.gsi.debug.gsi_qsb_debug.var_name[3], \ + GEN_REG_ATTR(reg_name) } + +#define IPA_REG_SAVE_RX_SPLT_CMDQ(reg_name, var_name) \ + { GEN_1xVECTOR_REG_OFST(reg_name, 0), \ + (u32 *)&ipa_reg_save.ipa.dbg.var_name[0], \ + GEN_REG_ATTR(reg_name)}, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 1), \ + (u32 *)&ipa_reg_save.ipa.dbg.var_name[1], \ + GEN_REG_ATTR(reg_name)}, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 2), \ + (u32 *)&ipa_reg_save.ipa.dbg.var_name[2], \ + GEN_REG_ATTR(reg_name)}, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 3), \ + (u32 *)&ipa_reg_save.ipa.dbg.var_name[3], \ + GEN_REG_ATTR(reg_name) } + +/* + * Macros to save array registers + */ + +/* + * helper macro to save array register of MAXn = 0 + */ +#define GEN_SRC_DST_ADDR_MAP_ARR_0(reg_name, sub_struct, var_name) \ + { GEN_1xVECTOR_REG_OFST(reg_name, 0), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[0], \ + GEN_REG_ATTR(reg_name) } + +/* + * helper macro to save array register of MAXn = 1 + */ +#define GEN_SRC_DST_ADDR_MAP_ARR_1(reg_name, sub_struct, var_name) \ + { GEN_1xVECTOR_REG_OFST(reg_name, 0), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[0], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 1), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[1], \ + GEN_REG_ATTR(reg_name) } + /* + * helper macro to save array register of MAXn = 31 + */ +#define GEN_SRC_DST_ADDR_MAP_ARR_31(reg_name, sub_struct, var_name) \ + { GEN_1xVECTOR_REG_OFST(reg_name, 0), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[0], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 1), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[1], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 2), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[2], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 3), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[3], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 4), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[4], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 5), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[5], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 6), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[6], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 7), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[7], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 8), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[8], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 9), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[9], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 10), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[10], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 11), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[11], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 12), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[12], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 13), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[13], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 14), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[14], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 15), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[15], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 16), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[16], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 17), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[17], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 18), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[18], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 19), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[19], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 20), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[20], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 21), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[21], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 22), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[22], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 23), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[23], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 24), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[24], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 25), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[25], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 26), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[26], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 27), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[27], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 28), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[28], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 29), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[29], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 30), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[30], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 31), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[31], \ + GEN_REG_ATTR(reg_name) } + + +#define __IPA_CONCATENATE(A, B) A ## B +#define IPA_CONCATENATE(A, B) __IPA_CONCATENATE(A, B) + +/* + * helper macro to save array register + */ +#define GEN_SRC_DST_ADDR_MAP_ARR(reg_name, sub_struct, var_name) \ + IPA_CONCATENATE(GEN_SRC_DST_ADDR_MAP_ARR_, \ + GEN_MAX_n(reg_name))(reg_name, sub_struct, var_name) + + +/* + * Macros to save multi EE array registers + */ + +/* + * helper macro to save EE array register of MAXk = 0 + */ +#define GEN_SRC_DST_ADDR_MAP_EE_n_REG_k_ARR_0(reg_name, sub_struct, var_name) \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 0), \ + (u32 *)&ipa_reg_save.sub_struct[IPA_HW_A7_EE].var_name.arr[0].value, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 0), \ + (u32 *)&ipa_reg_save.sub_struct[IPA_HW_Q6_EE].var_name.arr[0].value, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_UC_EE, 0), \ + (u32 *)&ipa_reg_save.sub_struct[IPA_HW_UC_EE].var_name.arr[0].value, \ + GEN_REG_ATTR(reg_name) } + +/* + * helper macro to save EE array register of MAXk = 1 + */ +#define GEN_SRC_DST_ADDR_MAP_EE_n_REG_k_ARR_1(reg_name, sub_struct, var_name) \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 0), \ + (u32 *)&ipa_reg_save.sub_struct[IPA_HW_A7_EE].var_name.arr[0].value, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 1), \ + (u32 *)&ipa_reg_save.sub_struct[IPA_HW_A7_EE].var_name.arr[1].value, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 0), \ + (u32 *)&ipa_reg_save.sub_struct[IPA_HW_Q6_EE].var_name.arr[0].value, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 1), \ + (u32 *)&ipa_reg_save.sub_struct[IPA_HW_Q6_EE].var_name.arr[1].value, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_UC_EE, 0), \ + (u32 *)&ipa_reg_save.sub_struct[IPA_HW_UC_EE].var_name.arr[0].value, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_UC_EE, 1), \ + (u32 *)&ipa_reg_save.sub_struct[IPA_HW_UC_EE].var_name.arr[1].value, \ + GEN_REG_ATTR(reg_name) } + +/* + * helper macro to save EE n reg k array register + */ +#define GEN_SRC_DST_ADDR_MAP_EE_n_REG_k_ARR(reg_name, sub_struct, var_name) \ + IPA_CONCATENATE(GEN_SRC_DST_ADDR_MAP_EE_n_REG_k_ARR_, \ + GEN_MAX_k(reg_name))(reg_name, sub_struct, var_name) + +/* + * helper macro to save EE n array register + */ +#define GEN_SRC_DST_ADDR_MAP_EE_n_ARR(reg_name, sub_struct, var_name) \ + { GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE), \ + (u32 *)&ipa_reg_save.sub_struct[IPA_HW_Q6_EE].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE), \ + (u32 *)&ipa_reg_save.sub_struct[IPA_HW_A7_EE].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_UC_EE), \ + (u32 *)&ipa_reg_save.sub_struct[IPA_HW_UC_EE].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE), \ + (u32 *)&ipa_reg_save.sub_struct[IPA_REG_SAVE_HWP_GSI_EE].\ + var_name, \ + GEN_REG_ATTR(reg_name) } + +/* + * helper macro to wrap struct intended for array as regs array + * in order to create array with max_k == 1 we need to declare + * it as arr[max_k + 1] -> arr[2] + */ +#define GEN_REGS_ARRAY(struct_name, reg_name) \ + struct IPA_CONCATENATE(struct_name, _arr) { \ + union struct_name arr[GEN_MAX_k(reg_name) + 1]; \ + } + +//#define REGS_ARRAY struct struct_name regs[GEN_MAX_k(reg_name)] + +/* + * IPA HW Platform Type + */ +enum ipa_hw_ee_e { + IPA_HW_A7_EE = 0, /* A7's execution environment */ + IPA_HW_Q6_EE = 1, /* Q6's execution environment */ + IPA_HW_UC_EE = 2, /* uC's execution environment */ + IPA_HW_HWP_EE = 3, /* HWP's execution environment */ + IPA_HW_EE_MAX, /* Max EE to support */ +}; + +#define IPA_MAX_EE_TO_COLLECT IPA_HW_UC_EE + +/* + * General IPA register save data struct (ie. this is where register + * values, once read, get placed... + */ +struct ipa_gen_regs_s { + struct ipa_hwio_def_ipa_state_s + ipa_state; +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_hwio_def_ipa_state_rx_active_n_s + ipa_state_rx_active_n[GEN_MAX_n(IPA_STATE_RX_ACTIVE_n) + 1]; +#else + struct ipa_hwio_def_ipa_state_rx_active_s + ipa_state_rx_active; +#endif + struct ipa_hwio_def_ipa_state_tx_wrapper_s + ipa_state_tx_wrapper; + struct ipa_hwio_def_ipa_state_tx0_s + ipa_state_tx0; +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_hwio_def_ipa_state_tx0_misc_s + ipa_state_tx0_misc; +#endif + struct ipa_hwio_def_ipa_state_tx1_s + ipa_state_tx1; +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_hwio_def_ipa_state_tx1_misc_s + ipa_state_tx1_misc; + struct ipa_hwio_def_ipa_state_aggr_active_n_s + ipa_state_aggr_active_n[GEN_MAX_n(IPA_STATE_AGGR_ACTIVE_n) + 1]; +#else + struct ipa_hwio_def_ipa_state_aggr_active_s + ipa_state_aggr_active; +#endif + struct ipa_hwio_def_ipa_state_dfetcher_s + ipa_state_dfetcher; + struct ipa_hwio_def_ipa_state_fetcher_mask_0_s + ipa_state_fetcher_mask_0; + struct ipa_hwio_def_ipa_state_fetcher_mask_1_s + ipa_state_fetcher_mask_1; +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_hwio_def_ipa_state_fetcher_mask_2_s + ipa_state_fetcher_mask_2; +#endif + struct ipa_hwio_def_ipa_state_gsi_aos_s + ipa_state_gsi_aos; + struct ipa_hwio_def_ipa_state_gsi_if_s + ipa_state_gsi_if; +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_hwio_def_ipa_state_gsi_skip_s + ipa_state_gsi_skip; + struct ipa_hwio_def_ipa_state_gsi_tlv_s + ipa_state_gsi_tlv; +#endif + struct ipa_hwio_def_ipa_dpl_timer_lsb_s + ipa_dpl_timer_lsb; + struct ipa_hwio_def_ipa_dpl_timer_msb_s + ipa_dpl_timer_msb; + struct ipa_hwio_def_ipa_proc_iph_cfg_s + ipa_proc_iph_cfg; + struct ipa_hwio_def_ipa_route_s + ipa_route; + struct ipa_hwio_def_ipa_spare_reg_1_s + ipa_spare_reg_1; +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_hwio_def_ipa_spare_reg_2_s + ipa_spare_reg_2; +#endif + struct ipa_hwio_def_ipa_log_s + ipa_log; +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_hwio_def_ipa_log_buf_status_cfg_s + ipa_log_buf_status_cfg; + struct ipa_hwio_def_ipa_log_buf_status_addr_s + ipa_log_buf_status_addr; + struct ipa_hwio_def_ipa_log_buf_status_write_ptr_s + ipa_log_buf_status_write_ptr; + struct ipa_hwio_def_ipa_log_buf_status_ram_ptr_s + ipa_log_buf_status_ram_ptr; +#endif + struct ipa_hwio_def_ipa_log_buf_hw_cmd_cfg_s + ipa_log_buf_hw_cmd_cfg; + struct ipa_hwio_def_ipa_log_buf_hw_cmd_addr_s + ipa_log_buf_hw_cmd_addr; + struct ipa_hwio_def_ipa_log_buf_hw_cmd_write_ptr_s + ipa_log_buf_hw_cmd_write_ptr; + struct ipa_hwio_def_ipa_log_buf_hw_cmd_ram_ptr_s + ipa_log_buf_hw_cmd_ram_ptr; + struct ipa_hwio_def_ipa_comp_hw_version_s + ipa_comp_hw_version; +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_hwio_def_ipa_filt_rout_hash_en_s + ipa_filt_rout_hash_en; + struct ipa_hwio_def_ipa_filt_rout_hash_flush_s + ipa_filt_rout_hash_flush; +#else + struct ipa_hwio_def_ipa_filt_rout_cache_cfg_s + ipa_filt_rout_cache_cfg; + struct ipa_hwio_def_ipa_filt_rout_cache_flush_s + ipa_filt_rout_cache_flush; +#endif + struct ipa_hwio_def_ipa_state_fetcher_s + ipa_state_fetcher; + struct ipa_hwio_def_ipa_ipv4_filter_init_values_s + ipa_ipv4_filter_init_values; + struct ipa_hwio_def_ipa_ipv6_filter_init_values_s + ipa_ipv6_filter_init_values; + struct ipa_hwio_def_ipa_ipv4_route_init_values_s + ipa_ipv4_route_init_values; + struct ipa_hwio_def_ipa_ipv6_route_init_values_s + ipa_ipv6_route_init_values; +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_hwio_def_ipa_bam_activated_ports_s + ipa_bam_activated_ports; +#else + struct ipa_hwio_def_ipa_bam_activated_ports_n_s + ipa_bam_activated_ports_n[GEN_MAX_n(IPA_BAM_ACTIVATED_PORTS_n) + + 1]; +#endif + struct ipa_hwio_def_ipa_tx_commander_cmdq_status_s + ipa_tx_commander_cmdq_status; + struct ipa_hwio_def_ipa_log_buf_hw_snif_el_en_s + ipa_log_buf_hw_snif_el_en; + struct ipa_hwio_def_ipa_log_buf_hw_snif_el_wr_n_rd_sel_s + ipa_log_buf_hw_snif_el_wr_n_rd_sel; + struct ipa_hwio_def_ipa_log_buf_hw_snif_el_cli_mux_s + ipa_log_buf_hw_snif_el_cli_mux; +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_hwio_def_ipa_log_buf_hw_cmd_noc_master_sel_s + ipa_log_buf_hw_cmd_noc_master_sel; +#endif + struct ipa_hwio_def_ipa_state_acl_s + ipa_state_acl; + struct ipa_hwio_def_ipa_sys_pkt_proc_cntxt_base_s + ipa_sys_pkt_proc_cntxt_base; + struct ipa_hwio_def_ipa_sys_pkt_proc_cntxt_base_msb_s + ipa_sys_pkt_proc_cntxt_base_msb; + struct ipa_hwio_def_ipa_local_pkt_proc_cntxt_base_s + ipa_local_pkt_proc_cntxt_base; + struct ipa_hwio_def_ipa_rsrc_grp_cfg_s + ipa_rsrc_grp_cfg; +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_hwio_def_ipa_0_ipa_rsrc_grp_cfg_ext_s + ipa_rsrc_grp_cfg_ext; +#endif + struct ipa_hwio_def_ipa_comp_cfg_s + ipa_comp_cfg; + struct ipa_hwio_def_ipa_state_dpl_fifo_s + ipa_state_dpl_fifo; +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_hwio_def_ipa_pipeline_disable_s + ipa_pipeline_disable; +#endif + struct ipa_hwio_def_ipa_state_nlo_aggr_s + ipa_state_nlo_aggr; +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_hwio_def_ipa_state_coal_master_s + ipa_state_coal_master; + struct ipa_hwio_def_ipa_state_coal_master_1_s + ipa_state_coal_master_1; + struct ipa_hwio_def_ipa_coal_evict_lru_s + ipa_coal_evict_lru; + struct ipa_hwio_def_ipa_coal_qmap_cfg_s + ipa_coal_qmap_cfg; + struct ipa_hwio_def_ipa_tag_timer_s + ipa_tag_timer; +#endif + struct ipa_hwio_def_ipa_nlo_pp_cfg1_s + ipa_nlo_pp_cfg1; + struct ipa_hwio_def_ipa_nlo_pp_cfg2_s + ipa_nlo_pp_cfg2; +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_hwio_def_ipa_nlo_pp_ack_limit_cfg_s + ipa_nlo_pp_ack_limit_cfg; + struct ipa_hwio_def_ipa_nlo_pp_data_limit_cfg_s + ipa_nlo_pp_data_limit_cfg; +#endif + struct ipa_hwio_def_ipa_nlo_min_dsm_cfg_s + ipa_nlo_min_dsm_cfg; +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_hwio_def_ipa_nlo_vp_aggr_cfg_lsb_n_s + ipa_nlo_vp_aggr_cfg_lsb_n[GEN_MAX_n(IPA_NLO_VP_AGGR_CFG_LSB_n) + 1]; + struct ipa_hwio_def_ipa_nlo_vp_limit_cfg_n_s + ipa_nlo_vp_limit_cfg_n[GEN_MAX_n(IPA_NLO_VP_LIMIT_CFG_n) + 1]; +#endif + struct ipa_hwio_def_ipa_nlo_vp_flush_req_s + ipa_nlo_vp_flush_req; + struct ipa_hwio_def_ipa_nlo_vp_flush_cookie_s + ipa_nlo_vp_flush_cookie; + struct ipa_hwio_def_ipa_nlo_vp_flush_ack_s + ipa_nlo_vp_flush_ack; + struct ipa_hwio_def_ipa_nlo_vp_dsm_open_s + ipa_nlo_vp_dsm_open; + struct ipa_hwio_def_ipa_nlo_vp_qbap_open_s + ipa_nlo_vp_qbap_open; +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_hwio_def_ipa_qsb_max_reads_s + ipa_qsb_max_reads; + struct ipa_hwio_def_ipa_qsb_max_writes_s + ipa_qsb_max_writes; + struct ipa_hwio_def_ipa_idle_indication_cfg_s + ipa_idle_indication_cfg; + struct ipa_hwio_def_ipa_clkon_cfg_s + ipa_clkon_cfg; + struct ipa_hwio_def_ipa_timers_xo_clk_div_cfg_s + ipa_timers_xo_clk_div_cfg; + struct ipa_hwio_def_ipa_timers_pulse_gran_cfg_s + ipa_timers_pulse_gran_cfg; + struct ipa_hwio_def_ipa_qtime_timestamp_cfg_s + ipa_qtime_timestamp_cfg; + struct ipa_hwio_def_ipa_flavor_0_s + ipa_flavor_0; + struct ipa_hwio_def_ipa_flavor_1_s + ipa_flavor_1; + struct ipa_hwio_def_ipa_filt_rout_cfg_s + ipa_filt_rout_cfg; +#endif +}; + +/* + * General IPA register save data struct + */ +struct ipa_reg_save_gen_ee_s { + struct ipa_hwio_def_ipa_irq_stts_ee_n_s + ipa_irq_stts_ee_n; + struct ipa_hwio_def_ipa_irq_en_ee_n_s + ipa_irq_en_ee_n; + struct ipa_hwio_def_ipa_fec_addr_ee_n_s + ipa_fec_addr_ee_n; + struct ipa_hwio_def_ipa_fec_attr_ee_n_s + ipa_fec_attr_ee_n; + struct ipa_hwio_def_ipa_snoc_fec_ee_n_s + ipa_snoc_fec_ee_n; +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_hwio_def_ipa_holb_drop_irq_info_ee_n_s + ipa_holb_drop_irq_info_ee_n; + struct ipa_hwio_def_ipa_suspend_irq_info_ee_n_s + ipa_suspend_irq_info_ee_n; + struct ipa_hwio_def_ipa_suspend_irq_en_ee_n_s + ipa_suspend_irq_en_ee_n; +#else + GEN_REGS_ARRAY(ipa_hwio_def_ipa_holb_drop_irq_info_ee_n_reg_k_u, + IPA_HOLB_DROP_IRQ_INFO_EE_n_REG_k) + ipa_holb_drop_irq_info_ee_n_reg_k; + GEN_REGS_ARRAY(ipa_hwio_def_ipa_suspend_irq_info_ee_n_reg_k_u, + IPA_SUSPEND_IRQ_INFO_EE_n_REG_k) + ipa_suspend_irq_info_ee_n_reg_k; + GEN_REGS_ARRAY(ipa_hwio_def_ipa_suspend_irq_en_ee_n_reg_k_u, + IPA_SUSPEND_IRQ_EN_EE_n_REG_k) + ipa_suspend_irq_en_ee_n_reg_k; +#endif +}; + +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 +/* + * statistics IPA register save data struct + */ + +struct ipa_reg_save_stat_ee_s { + struct ipa_hwio_def_ipa_stat_quota_base_n_s + ipa_stat_quota_base_n; + struct ipa_hwio_def_ipa_stat_tethering_base_n_s + ipa_stat_tethering_base_n; + struct ipa_hwio_def_ipa_stat_drop_cnt_base_n_s + ipa_stat_drop_cnt_base_n; + GEN_REGS_ARRAY(ipa_hwio_def_ipa_stat_quota_mask_ee_n_reg_k_u, + IPA_STAT_QUOTA_MASK_EE_n_REG_k) + ipa_stat_quota_mask_ee_n_reg_k; + GEN_REGS_ARRAY(ipa_hwio_def_ipa_stat_tethering_mask_ee_n_reg_k_u, + IPA_STAT_TETHERING_MASK_EE_n_REG_k) + ipa_stat_tethering_mask_ee_n_reg_k; + GEN_REGS_ARRAY(ipa_hwio_def_ipa_stat_drop_cnt_mask_ee_n_reg_k_u, + IPA_STAT_DROP_CNT_MASK_EE_n_REG_k) + ipa_stat_drop_cnt_mask_ee_n_reg_k; +}; +#endif + +/* + * Pipe Endp IPA register save data struct + */ +struct ipa_reg_save_pipe_endp_s { + struct ipa_hwio_def_ipa_endp_init_ctrl_n_s + ipa_endp_init_ctrl_n; + struct ipa_hwio_def_ipa_endp_init_ctrl_scnd_n_s + ipa_endp_init_ctrl_scnd_n; + struct ipa_hwio_def_ipa_endp_init_cfg_n_s + ipa_endp_init_cfg_n; + struct ipa_hwio_def_ipa_endp_init_nat_n_s + ipa_endp_init_nat_n; + struct ipa_hwio_def_ipa_endp_init_hdr_n_s + ipa_endp_init_hdr_n; + struct ipa_hwio_def_ipa_endp_init_hdr_ext_n_s + ipa_endp_init_hdr_ext_n; + struct ipa_hwio_def_ipa_endp_init_hdr_metadata_mask_n_s + ipa_endp_init_hdr_metadata_mask_n; + struct ipa_hwio_def_ipa_endp_init_hdr_metadata_n_s + ipa_endp_init_hdr_metadata_n; + struct ipa_hwio_def_ipa_endp_init_mode_n_s + ipa_endp_init_mode_n; + struct ipa_hwio_def_ipa_endp_init_aggr_n_s + ipa_endp_init_aggr_n; + struct ipa_hwio_def_ipa_endp_init_hol_block_en_n_s + ipa_endp_init_hol_block_en_n; + struct ipa_hwio_def_ipa_endp_init_hol_block_timer_n_s + ipa_endp_init_hol_block_timer_n; + struct ipa_hwio_def_ipa_endp_init_deaggr_n_s + ipa_endp_init_deaggr_n; + struct ipa_hwio_def_ipa_endp_status_n_s + ipa_endp_status_n; + struct ipa_hwio_def_ipa_endp_init_rsrc_grp_n_s + ipa_endp_init_rsrc_grp_n; + struct ipa_hwio_def_ipa_endp_init_seq_n_s + ipa_endp_init_seq_n; + struct ipa_hwio_def_ipa_endp_gsi_cfg_tlv_n_s + ipa_endp_gsi_cfg_tlv_n; + struct ipa_hwio_def_ipa_endp_gsi_cfg_aos_n_s + ipa_endp_gsi_cfg_aos_n; + struct ipa_hwio_def_ipa_endp_gsi_cfg1_n_s + ipa_endp_gsi_cfg1_n; +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_hwio_def_ipa_endp_filter_router_hsh_cfg_n_s + ipa_endp_filter_router_hsh_cfg_n; +#else + struct ipa_hwio_def_ipa_filter_cache_cfg_n_s + ipa_filter_cache_cfg_n; + struct ipa_hwio_def_ipa_router_cache_cfg_n_s + ipa_router_cache_cfg_n; +#endif +}; + +/* + * Pipe IPA register save data struct + */ +struct ipa_reg_save_pipe_s { + u8 active; + struct ipa_reg_save_pipe_endp_s endp; +}; + +/* + * HWP IPA register save data struct + */ +struct ipa_reg_save_hwp_s { + struct ipa_hwio_def_ipa_uc_qmb_sys_addr_s + ipa_uc_qmb_sys_addr; + struct ipa_hwio_def_ipa_uc_qmb_local_addr_s + ipa_uc_qmb_local_addr; + struct ipa_hwio_def_ipa_uc_qmb_length_s + ipa_uc_qmb_length; + struct ipa_hwio_def_ipa_uc_qmb_trigger_s + ipa_uc_qmb_trigger; +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_hwio_def_ipa_uc_qmb_pending_tid_s + ipa_uc_qmb_pending_tid; + struct ipa_hwio_def_ipa_uc_qmb_completed_rd_fifo_peek_s + ipa_uc_qmb_completed_rd_fifo_peek; + struct ipa_hwio_def_ipa_uc_qmb_completed_wr_fifo_peek_s + ipa_uc_qmb_completed_wr_fifo_peek; + struct ipa_hwio_def_ipa_uc_qmb_misc_s + ipa_uc_qmb_misc; + struct ipa_hwio_def_ipa_uc_qmb_status_s + ipa_uc_qmb_status; +#endif + struct ipa_hwio_def_ipa_uc_qmb_bus_attrib_s + ipa_uc_qmb_bus_attrib; +}; + +/* + * IPA TESTBUS entry struct + */ +struct ipa_reg_save_ipa_testbus_entry_s { + union ipa_hwio_def_ipa_testbus_sel_u testbus_sel; + union ipa_hwio_def_ipa_debug_data_u testbus_data; +}; + +/* IPA TESTBUS global struct */ +struct ipa_reg_save_ipa_testbus_global_s { + struct ipa_reg_save_ipa_testbus_entry_s + global[IPA_TESTBUS_SEL_INTERNAL_MAX + 1] + [IPA_TESTBUS_SEL_EXTERNAL_MAX + 1]; +}; + +/* IPA TESTBUS per EP struct */ +struct ipa_reg_save_ipa_testbus_ep_s { + struct ipa_reg_save_ipa_testbus_entry_s + entry_ep[IPA_TESTBUS_SEL_INTERNAL_PIPE_MAX + 1] + [IPA_TESTBUS_SEL_EXTERNAL_MAX + 1]; +}; + +/* IPA TESTBUS per EP struct */ +struct ipa_reg_save_ipa_testbus_ep_rsrc_s { + struct ipa_reg_save_ipa_testbus_entry_s + entry_ep[IPA_DEBUG_TESTBUS_RSRC_NUM_GRP]; +}; + +/* IPA TESTBUS save data struct */ +struct ipa_reg_save_ipa_testbus_s { + struct ipa_reg_save_ipa_testbus_global_s global; + struct ipa_reg_save_ipa_testbus_ep_s + ep[IPA_TESTBUS_SEL_EP_MAX + 1]; + struct ipa_reg_save_ipa_testbus_ep_rsrc_s + ep_rsrc[IPA_DEBUG_TESTBUS_RSRC_NUM_EP]; +}; + +/* + * Debug IPA register save data struct + */ +struct ipa_reg_save_dbg_s { + struct ipa_hwio_def_ipa_debug_data_s + ipa_debug_data; + struct ipa_hwio_def_ipa_step_mode_status_s + ipa_step_mode_status; + struct ipa_hwio_def_ipa_step_mode_breakpoints_s + ipa_step_mode_breakpoints; + struct ipa_hwio_def_ipa_rx_splt_cmdq_cmd_n_s + ipa_rx_splt_cmdq_cmd_n[IPA_RX_SPLT_CMDQ_MAX]; + struct ipa_hwio_def_ipa_rx_splt_cmdq_cfg_n_s + ipa_rx_splt_cmdq_cfg_n[IPA_RX_SPLT_CMDQ_MAX]; + struct ipa_hwio_def_ipa_rx_splt_cmdq_data_wr_0_n_s + ipa_rx_splt_cmdq_data_wr_0_n[IPA_RX_SPLT_CMDQ_MAX]; + struct ipa_hwio_def_ipa_rx_splt_cmdq_data_wr_1_n_s + ipa_rx_splt_cmdq_data_wr_1_n[IPA_RX_SPLT_CMDQ_MAX]; + struct ipa_hwio_def_ipa_rx_splt_cmdq_data_wr_2_n_s + ipa_rx_splt_cmdq_data_wr_2_n[IPA_RX_SPLT_CMDQ_MAX]; + struct ipa_hwio_def_ipa_rx_splt_cmdq_data_wr_3_n_s + ipa_rx_splt_cmdq_data_wr_3_n[IPA_RX_SPLT_CMDQ_MAX]; + struct ipa_hwio_def_ipa_rx_splt_cmdq_data_rd_0_n_s + ipa_rx_splt_cmdq_data_rd_0_n[IPA_RX_SPLT_CMDQ_MAX]; + struct ipa_hwio_def_ipa_rx_splt_cmdq_data_rd_1_n_s + ipa_rx_splt_cmdq_data_rd_1_n[IPA_RX_SPLT_CMDQ_MAX]; + struct ipa_hwio_def_ipa_rx_splt_cmdq_data_rd_2_n_s + ipa_rx_splt_cmdq_data_rd_2_n[IPA_RX_SPLT_CMDQ_MAX]; + struct ipa_hwio_def_ipa_rx_splt_cmdq_data_rd_3_n_s + ipa_rx_splt_cmdq_data_rd_3_n[IPA_RX_SPLT_CMDQ_MAX]; + struct ipa_hwio_def_ipa_rx_splt_cmdq_status_n_s + ipa_rx_splt_cmdq_status_n[IPA_RX_SPLT_CMDQ_MAX]; + + union ipa_hwio_def_ipa_rx_hps_cmdq_cfg_wr_u + ipa_rx_hps_cmdq_cfg_wr; + union ipa_hwio_def_ipa_rx_hps_cmdq_cfg_rd_u + ipa_rx_hps_cmdq_cfg_rd; + + struct ipa_hwio_def_ipa_rx_hps_cmdq_cmd_s + ipa_rx_hps_cmdq_cmd; +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_hwio_def_ipa_stat_filter_ipv4_base_s + ipa_stat_filter_ipv4_base; + struct ipa_hwio_def_ipa_stat_filter_ipv6_base_s + ipa_stat_filter_ipv6_base; + struct ipa_hwio_def_ipa_stat_router_ipv4_base_s + ipa_stat_router_ipv4_base; + struct ipa_hwio_def_ipa_stat_router_ipv6_base_s + ipa_stat_router_ipv6_base; +#endif + union ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_0_u + ipa_rx_hps_cmdq_data_rd_0_arr[ + IPA_DEBUG_CMDQ_HPS_SELECT_NUM_GROUPS]; + union ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_1_u + ipa_rx_hps_cmdq_data_rd_1_arr[ + IPA_DEBUG_CMDQ_HPS_SELECT_NUM_GROUPS]; + union ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_2_u + ipa_rx_hps_cmdq_data_rd_2_arr[ + IPA_DEBUG_CMDQ_HPS_SELECT_NUM_GROUPS]; + union ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_3_u + ipa_rx_hps_cmdq_data_rd_3_arr[ + IPA_DEBUG_CMDQ_HPS_SELECT_NUM_GROUPS]; + union ipa_hwio_def_ipa_rx_hps_cmdq_count_u + ipa_rx_hps_cmdq_count_arr[IPA_DEBUG_CMDQ_HPS_SELECT_NUM_GROUPS]; + union ipa_hwio_def_ipa_rx_hps_cmdq_status_u + ipa_rx_hps_cmdq_status_arr[IPA_DEBUG_CMDQ_HPS_SELECT_NUM_GROUPS]; + struct ipa_hwio_def_ipa_rx_hps_cmdq_status_empty_s + ipa_rx_hps_cmdq_status_empty; +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_hwio_def_ipa_rsrc_mngr_contexts_s + ipa_rsrc_mngr_contexts; + struct ipa_hwio_def_ipa_snoc_monitoring_cfg_s + ipa_snoc_monitoring_cfg; + struct ipa_hwio_def_ipa_pcie_snoc_monitor_cnt_s + ipa_pcie_snoc_monitor_cnt; + struct ipa_hwio_def_ipa_ddr_snoc_monitor_cnt_s + ipa_ddr_snoc_monitor_cnt; + struct ipa_hwio_def_ipa_gsi_snoc_monitor_cnt_s + ipa_gsi_snoc_monitor_cnt; + struct ipa_hwio_def_ipa_ram_sniffer_hw_base_addr_s + ipa_ram_sniffer_hw_base_addr; + struct ipa_hwio_def_ipa_bresp_db_cfg_s + ipa_bresp_db_cfg; + struct ipa_hwio_def_ipa_bresp_db_data_s + ipa_bresp_db_data; + struct ipa_hwio_def_ipa_endp_gsi_cons_bytes_tlv_s + ipa_endp_gsi_cons_bytes_tlv; + struct ipa_hwio_def_ipa_ram_gsi_tlv_base_addr_s + ipa_ram_gsi_tlv_base_addr; +#endif + struct ipa_hwio_def_ipa_rx_hps_clients_min_depth_0_s + ipa_rx_hps_clients_min_depth_0; + struct ipa_hwio_def_ipa_rx_hps_clients_max_depth_0_s + ipa_rx_hps_clients_max_depth_0; + struct ipa_hwio_def_ipa_hps_dps_cmdq_cmd_s + ipa_hps_dps_cmdq_cmd; + union ipa_hwio_def_ipa_hps_dps_cmdq_data_rd_0_u + ipa_hps_dps_cmdq_data_rd_0_arr[IPA_TESTBUS_SEL_EP_MAX + 1]; + union ipa_hwio_def_ipa_hps_dps_cmdq_count_u + ipa_hps_dps_cmdq_count_arr[IPA_TESTBUS_SEL_EP_MAX + 1]; + union ipa_hwio_def_ipa_hps_dps_cmdq_status_u + ipa_hps_dps_cmdq_status_arr[IPA_TESTBUS_SEL_EP_MAX + 1]; +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_hwio_def_ipa_hps_dps_cmdq_status_empty_s + ipa_hps_dps_cmdq_status_empty; +#else + struct ipa_hwio_def_ipa_hps_dps_cmdq_status_empty_n_s + ipa_hps_dps_cmdq_status_empty_n[ + GEN_MAX_n(IPA_HPS_DPS_CMDQ_STATUS_EMPTY_n) + 1]; +#endif + struct ipa_hwio_def_ipa_dps_tx_cmdq_cmd_s + ipa_dps_tx_cmdq_cmd; + union ipa_hwio_def_ipa_dps_tx_cmdq_data_rd_0_u + ipa_dps_tx_cmdq_data_rd_0_arr[ + IPA_DEBUG_CMDQ_DPS_SELECT_NUM_GROUPS]; + union ipa_hwio_def_ipa_dps_tx_cmdq_count_u + ipa_dps_tx_cmdq_count_arr[IPA_DEBUG_CMDQ_DPS_SELECT_NUM_GROUPS]; + union ipa_hwio_def_ipa_dps_tx_cmdq_status_u + ipa_dps_tx_cmdq_status_arr[IPA_DEBUG_CMDQ_DPS_SELECT_NUM_GROUPS]; + struct ipa_hwio_def_ipa_dps_tx_cmdq_status_empty_s + ipa_dps_tx_cmdq_status_empty; + + struct ipa_hwio_def_ipa_ackmngr_cmdq_cmd_s + ipa_ackmngr_cmdq_cmd; + union ipa_hwio_def_ipa_ackmngr_cmdq_data_rd_u + ipa_ackmngr_cmdq_data_rd_arr[ + IPA_DEBUG_CMDQ_ACK_SELECT_NUM_GROUPS]; + union ipa_hwio_def_ipa_ackmngr_cmdq_count_u + ipa_ackmngr_cmdq_count_arr[IPA_DEBUG_CMDQ_ACK_SELECT_NUM_GROUPS]; + union ipa_hwio_def_ipa_ackmngr_cmdq_status_u + ipa_ackmngr_cmdq_status_arr[ + IPA_DEBUG_CMDQ_ACK_SELECT_NUM_GROUPS]; +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_hwio_def_ipa_ackmngr_cmdq_status_empty_s + ipa_ackmngr_cmdq_status_empty; +#else + struct ipa_hwio_def_ipa_ackmngr_cmdq_status_empty_n_s + ipa_ackmngr_cmdq_status_empty_n[ + GEN_MAX_n(IPA_ACKMNGR_CMDQ_STATUS_EMPTY_n) + 1]; +#endif + struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_cmd_s + ipa_prod_ackmngr_cmdq_cmd; + union ipa_hwio_def_ipa_prod_ackmngr_cmdq_data_rd_u + ipa_prod_ackmngr_cmdq_data_rd_arr[IPA_TESTBUS_SEL_EP_MAX + 1]; + union ipa_hwio_def_ipa_prod_ackmngr_cmdq_count_u + ipa_prod_ackmngr_cmdq_count_arr[IPA_TESTBUS_SEL_EP_MAX + 1]; + union ipa_hwio_def_ipa_prod_ackmngr_cmdq_status_u + ipa_prod_ackmngr_cmdq_status_arr[IPA_TESTBUS_SEL_EP_MAX + 1]; +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_status_empty_s + ipa_prod_ackmngr_cmdq_status_empty; +#else + struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_status_empty_n_s + ipa_prod_ackmngr_cmdq_status_empty_n[GEN_MAX_n( + IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_n) + 1]; +#endif + struct ipa_hwio_def_ipa_ntf_tx_cmdq_cmd_s + ipa_ntf_tx_cmdq_cmd; + union ipa_hwio_def_ipa_ntf_tx_cmdq_data_rd_0_u + ipa_ntf_tx_cmdq_data_rd_0_arr[IPA_TESTBUS_SEL_EP_MAX + 1]; + union ipa_hwio_def_ipa_ntf_tx_cmdq_count_u + ipa_ntf_tx_cmdq_count_arr[IPA_TESTBUS_SEL_EP_MAX + 1]; + union ipa_hwio_def_ipa_ntf_tx_cmdq_status_u + ipa_ntf_tx_cmdq_status_arr[IPA_TESTBUS_SEL_EP_MAX + 1]; +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_hwio_def_ipa_ntf_tx_cmdq_status_empty_s + ipa_ntf_tx_cmdq_status_empty; +#else + struct ipa_hwio_def_ipa_ntf_tx_cmdq_status_empty_n_s + ipa_ntf_tx_cmdq_status_empty_n[GEN_MAX_n( + IPA_NTF_TX_CMDQ_STATUS_EMPTY_n) + 1]; +#endif + union ipa_hwio_def_ipa_rsrc_mngr_db_rsrc_read_u + ipa_rsrc_mngr_db_rsrc_read_arr[IPA_RSCR_MNGR_DB_RSRC_TYPE_MAX + + 1][IPA_RSCR_MNGR_DB_RSRC_ID_MAX + + 1]; + union ipa_hwio_def_ipa_rsrc_mngr_db_list_read_u + ipa_rsrc_mngr_db_list_read_arr[IPA_RSCR_MNGR_DB_RSRC_TYPE_MAX + + 1][IPA_RSCR_MNGR_DB_RSRC_ID_MAX + + 1]; +}; + +/* Source Resource Group IPA register save data struct */ +struct ipa_reg_save_src_rsrc_grp_s { + struct ipa_hwio_def_ipa_src_rsrc_grp_01_rsrc_type_n_s + ipa_src_rsrc_grp_01_rsrc_type_n; + struct ipa_hwio_def_ipa_src_rsrc_grp_23_rsrc_type_n_s + ipa_src_rsrc_grp_23_rsrc_type_n; + struct ipa_hwio_def_ipa_src_rsrc_grp_45_rsrc_type_n_s + ipa_src_rsrc_grp_45_rsrc_type_n; +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_hwio_def_ipa_src_rsrc_grp_67_rsrc_type_n_s + ipa_src_rsrc_grp_67_rsrc_type_n; + struct ipa_hwio_def_ipa_src_rsrc_type_amount_n_s + ipa_src_rsrc_type_amount; +#endif +}; + +/* Source Resource Group IPA register save data struct */ +struct ipa_reg_save_dst_rsrc_grp_s { + struct ipa_hwio_def_ipa_dst_rsrc_grp_01_rsrc_type_n_s + ipa_dst_rsrc_grp_01_rsrc_type_n; + struct ipa_hwio_def_ipa_dst_rsrc_grp_23_rsrc_type_n_s + ipa_dst_rsrc_grp_23_rsrc_type_n; + struct ipa_hwio_def_ipa_dst_rsrc_grp_45_rsrc_type_n_s + ipa_dst_rsrc_grp_45_rsrc_type_n; +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_hwio_def_ipa_dst_rsrc_grp_67_rsrc_type_n_s + ipa_dst_rsrc_grp_67_rsrc_type_n; + struct ipa_hwio_def_ipa_dst_rsrc_type_amount_n_s + ipa_dst_rsrc_type_amount; +#endif +}; + +/* Source Resource Group Count IPA register save data struct */ +struct ipa_reg_save_src_rsrc_cnt_s { + struct ipa_hwio_def_ipa_src_rsrc_grp_0123_rsrc_type_cnt_n_s + ipa_src_rsrc_grp_0123_rsrc_type_cnt_n; + struct ipa_hwio_def_ipa_src_rsrc_grp_4567_rsrc_type_cnt_n_s + ipa_src_rsrc_grp_4567_rsrc_type_cnt_n; +}; + +/* Destination Resource Group Count IPA register save data struct */ +struct ipa_reg_save_dst_rsrc_cnt_s { + struct ipa_hwio_def_ipa_dst_rsrc_grp_0123_rsrc_type_cnt_n_s + ipa_dst_rsrc_grp_0123_rsrc_type_cnt_n; + struct ipa_hwio_def_ipa_dst_rsrc_grp_4567_rsrc_type_cnt_n_s + ipa_dst_rsrc_grp_4567_rsrc_type_cnt_n; +}; + +/* GSI General register save data struct */ +struct ipa_reg_save_gsi_gen_s { + struct gsi_hwio_def_gsi_cfg_s + gsi_cfg; + struct gsi_hwio_def_gsi_ree_cfg_s + gsi_ree_cfg; + struct ipa_hwio_def_ipa_gsi_top_gsi_inst_ram_n_s + ipa_gsi_top_gsi_inst_ram_n; +}; + +/* GSI General EE register save data struct */ +struct ipa_reg_save_gsi_gen_ee_s { + struct gsi_hwio_def_gsi_manager_ee_qos_n_s + gsi_manager_ee_qos_n; + struct gsi_hwio_def_ee_n_gsi_status_s + ee_n_gsi_status; + struct gsi_hwio_def_ee_n_cntxt_type_irq_s + ee_n_cntxt_type_irq; + struct gsi_hwio_def_ee_n_cntxt_type_irq_msk_s + ee_n_cntxt_type_irq_msk; +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_s + ee_n_cntxt_src_gsi_ch_irq; + struct gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_s + ee_n_cntxt_src_ev_ch_irq; + struct gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_msk_s + ee_n_cntxt_src_gsi_ch_irq_msk; + struct gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_msk_s + ee_n_cntxt_src_ev_ch_irq_msk; + struct gsi_hwio_def_ee_n_cntxt_src_ieob_irq_s + ee_n_cntxt_src_ieob_irq; + struct gsi_hwio_def_ee_n_cntxt_src_ieob_irq_msk_s + ee_n_cntxt_src_ieob_irq_msk; +#else + GEN_REGS_ARRAY(gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_k_u, + EE_n_CNTXT_SRC_GSI_CH_IRQ_k) + ee_n_cntxt_src_gsi_ch_irq_k; + GEN_REGS_ARRAY(gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_k_u, + EE_n_CNTXT_SRC_EV_CH_IRQ_k) + ee_n_cntxt_src_ev_ch_irq_k; + GEN_REGS_ARRAY(gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_msk_k_u, + EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k) + ee_n_cntxt_src_gsi_ch_irq_msk_k; + GEN_REGS_ARRAY(gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_msk_k_u, + EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k) + ee_n_cntxt_src_ev_ch_irq_msk_k; + GEN_REGS_ARRAY(gsi_hwio_def_ee_n_cntxt_src_ieob_irq_k_u, + EE_n_CNTXT_SRC_IEOB_IRQ_k) + ee_n_cntxt_src_ieob_irq_k; + GEN_REGS_ARRAY(gsi_hwio_def_ee_n_cntxt_src_ieob_irq_msk_k_u, + EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k) + ee_n_cntxt_src_ieob_irq_msk_k; +#endif + struct gsi_hwio_def_ee_n_cntxt_gsi_irq_stts_s + ee_n_cntxt_gsi_irq_stts; + struct gsi_hwio_def_ee_n_cntxt_glob_irq_stts_s + ee_n_cntxt_glob_irq_stts; + struct gsi_hwio_def_ee_n_error_log_s + ee_n_error_log; + struct gsi_hwio_def_ee_n_cntxt_scratch_0_s + ee_n_cntxt_scratch_0; + struct gsi_hwio_def_ee_n_cntxt_scratch_1_s + ee_n_cntxt_scratch_1; + struct gsi_hwio_def_ee_n_cntxt_intset_s + ee_n_cntxt_intset; + struct gsi_hwio_def_ee_n_cntxt_msi_base_lsb_s + ee_n_cntxt_msi_base_lsb; + struct gsi_hwio_def_ee_n_cntxt_msi_base_msb_s + ee_n_cntxt_msi_base_msb; +}; + +/* GSI QSB debug register save data struct */ +struct ipa_reg_save_gsi_qsb_debug_s { + struct gsi_hwio_def_gsi_debug_qsb_log_last_misc_idn_s + qsb_log_last_misc[GSI_HW_QSB_LOG_MISC_MAX]; +}; + +static u32 ipa_reg_save_gsi_ch_test_bus_selector_array[] = { + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_ZEROS, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MCS_0, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MCS_1, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MCS_2, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MCS_3, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MCS_4, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_DB_ENG, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_0, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_1, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_2, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_3, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_4, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_5, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_6, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_7, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_EVE_0, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_EVE_1, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_EVE_2, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_EVE_3, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_EVE_4, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_EVE_5, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IE_0, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IE_1, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IC_0, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IC_1, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IC_2, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IC_3, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IC_4, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MOQA_0, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MOQA_1, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MOQA_2, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MOQA_3, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_TMR_0, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_TMR_1, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_TMR_2, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_TMR_3, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_RD_WR_0, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_RD_WR_1, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_RD_WR_2, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_RD_WR_3, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_CSR, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_SDMA_0, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_SDMA_1, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IE_2, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_CSR_1, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_CSR_2, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MCS_5, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IC_5, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_CSR_3, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_TLV_0, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_8, +}; + +/* + * GSI QSB debug bus register save data struct + */ +struct ipa_reg_save_gsi_test_bus_s { + u32 test_bus_selector[ + ARRAY_SIZE(ipa_reg_save_gsi_ch_test_bus_selector_array)]; + struct + gsi_hwio_def_gsi_test_bus_reg_s + test_bus_reg[ARRAY_SIZE(ipa_reg_save_gsi_ch_test_bus_selector_array)]; +}; + +/* GSI debug MCS registers save data struct */ +struct ipa_reg_save_gsi_mcs_regs_s { + struct + gsi_hwio_def_gsi_debug_sw_rf_n_read_s + mcs_reg[HWIO_GSI_DEBUG_SW_RF_n_READ_MAXn + 1]; +}; + +struct ipa_reg_save_gsi_mcs_prof_regs_s { + struct gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_bp_cnt_lsb_s + gsi_top_gsi_mcs_profiling_bp_cnt_lsb; + struct gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_bp_cnt_msb_s + gsi_top_gsi_mcs_profiling_bp_cnt_msb; + struct gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_bp_and_pending_cnt_lsb_s + gsi_top_gsi_mcs_profiling_bp_and_pending_cnt_lsb; + struct gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_bp_and_pending_cnt_msb_s + gsi_top_gsi_mcs_profiling_bp_and_pending_cnt_msb; + struct gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_mcs_busy_cnt_lsb_s + gsi_top_gsi_mcs_profiling_mcs_busy_cnt_lsb; + struct gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_mcs_busy_cnt_msb_s + gsi_top_gsi_mcs_profiling_mcs_busy_cnt_msb; + struct gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_mcs_idle_cnt_lsb_s + gsi_top_gsi_mcs_profiling_mcs_idle_cnt_lsb; + struct gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_mcs_idle_cnt_msb_s + gsi_top_gsi_mcs_profiling_mcs_idle_cnt_msb; +}; + +/* GSI debug counters save data struct */ +struct ipa_reg_save_gsi_debug_cnt_s { + struct + gsi_hwio_def_gsi_debug_countern_s + cnt[HWIO_GSI_DEBUG_COUNTERn_MAXn + 1]; +}; + +/* GSI IRAM pointers (IEP) save data struct */ +struct ipa_reg_save_gsi_iram_ptr_regs_s { + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ch_cmd_s + ipa_gsi_top_gsi_iram_ptr_ch_cmd; + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ee_generic_cmd_s + ipa_gsi_top_gsi_iram_ptr_ee_generic_cmd; + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ch_db_s + ipa_gsi_top_gsi_iram_ptr_ch_db; + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ev_db_s + ipa_gsi_top_gsi_iram_ptr_ev_db; + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_new_re_s + ipa_gsi_top_gsi_iram_ptr_new_re; + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ch_dis_comp_s + ipa_gsi_top_gsi_iram_ptr_ch_dis_comp; + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ch_empty_s + ipa_gsi_top_gsi_iram_ptr_ch_empty; + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_event_gen_comp_s + ipa_gsi_top_gsi_iram_ptr_event_gen_comp; + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_timer_expired_s + ipa_gsi_top_gsi_iram_ptr_timer_expired; + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_write_eng_comp_s + ipa_gsi_top_gsi_iram_ptr_write_eng_comp; + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_read_eng_comp_s + ipa_gsi_top_gsi_iram_ptr_read_eng_comp; + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_uc_gp_int_s + ipa_gsi_top_gsi_iram_ptr_uc_gp_int; +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_int_mod_stopped_s + ipa_gsi_top_gsi_iram_ptr_int_mod_stopped; +#else + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_int_mod_stoped_s + ipa_gsi_top_gsi_iram_ptr_int_mod_stoped; +#endif +}; + +/* GSI Debug SW registers save data struct */ +struct gsi_hwio_gsi_top_gsi_debug_sw_msk_regs_entry_rd_s{ + struct gsi_hwio_def_ipa_0_gsi_top_gsi_debug_sw_msk_reg_n_sec_k_rd_s + regs[GSI_HW_DEBUG_SW_MSK_REG_MAXk]; +}; + +struct gsi_hwio_gsi_top_gsi_debug_sw_msk_regs_rd_s{ + struct gsi_hwio_gsi_top_gsi_debug_sw_msk_regs_entry_rd_s + mask_reg[GSI_HW_DEBUG_SW_MSK_REG_ARRAY_LENGTH]; +}; + +/* GSI SHRAM pointers save data struct */ +struct ipa_reg_save_gsi_shram_ptr_regs_s { + struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_ch_cntxt_base_addr_s + ipa_gsi_top_gsi_shram_ptr_ch_cntxt_base_addr; + struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_ev_cntxt_base_addr_s + ipa_gsi_top_gsi_shram_ptr_ev_cntxt_base_addr; + struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_re_storage_base_addr_s + ipa_gsi_top_gsi_shram_ptr_re_storage_base_addr; + struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_re_esc_buf_base_addr_s + ipa_gsi_top_gsi_shram_ptr_re_esc_buf_base_addr; + struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_ee_scrach_base_addr_s + ipa_gsi_top_gsi_shram_ptr_ee_scrach_base_addr; + struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_func_stack_base_addr_s + ipa_gsi_top_gsi_shram_ptr_func_stack_base_addr; +}; + +/* GSI debug register save data struct */ +struct ipa_reg_save_gsi_debug_s { + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_busy_reg_s + ipa_gsi_top_gsi_debug_busy_reg; +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_event_pending_s + ipa_gsi_top_gsi_debug_event_pending; + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_timer_pending_s + ipa_gsi_top_gsi_debug_timer_pending; + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_rd_wr_pending_s + ipa_gsi_top_gsi_debug_rd_wr_pending; +#endif + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_pc_from_sw_s + ipa_gsi_top_gsi_debug_pc_from_sw; + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_sw_stall_s + ipa_gsi_top_gsi_debug_sw_stall; + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_pc_for_debug_s + ipa_gsi_top_gsi_debug_pc_for_debug; + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_qsb_log_err_trns_id_s + ipa_gsi_top_gsi_debug_qsb_log_err_trns_id; + struct ipa_reg_save_gsi_qsb_debug_s gsi_qsb_debug; + struct ipa_reg_save_gsi_test_bus_s gsi_test_bus; + struct ipa_reg_save_gsi_mcs_regs_s gsi_mcs_regs; +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_reg_save_gsi_mcs_prof_regs_s gsi_mcs_prof_regs; +#endif + struct ipa_reg_save_gsi_debug_cnt_s gsi_cnt_regs; + struct ipa_reg_save_gsi_iram_ptr_regs_s gsi_iram_ptrs; + struct ipa_reg_save_gsi_shram_ptr_regs_s gsi_shram_ptrs; +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct gsi_hwio_gsi_top_gsi_debug_sw_msk_regs_rd_s + debug_sw_msk; +#endif +}; + +/* GSI MCS channel scratch registers save data struct */ +struct ipa_reg_save_gsi_mcs_channel_scratch_regs_s { + struct gsi_hwio_def_gsi_shram_n_s + scratch_for_seq_low; + struct gsi_hwio_def_gsi_shram_n_s + scratch_for_seq_high; +}; + +/* GSI Channel Context register save data struct */ +struct ipa_reg_save_gsi_ch_cntxt_per_ep_s { + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_0_s + ee_n_gsi_ch_k_cntxt_0; + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_1_s + ee_n_gsi_ch_k_cntxt_1; + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_2_s + ee_n_gsi_ch_k_cntxt_2; + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_3_s + ee_n_gsi_ch_k_cntxt_3; + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_4_s + ee_n_gsi_ch_k_cntxt_4; + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_5_s + ee_n_gsi_ch_k_cntxt_5; + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_6_s + ee_n_gsi_ch_k_cntxt_6; + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_7_s + ee_n_gsi_ch_k_cntxt_7; + struct gsi_hwio_def_ee_n_gsi_ch_k_re_fetch_read_ptr_s + ee_n_gsi_ch_k_re_fetch_read_ptr; + struct gsi_hwio_def_ee_n_gsi_ch_k_re_fetch_write_ptr_s + ee_n_gsi_ch_k_re_fetch_write_ptr; + struct gsi_hwio_def_ee_n_gsi_ch_k_qos_s + ee_n_gsi_ch_k_qos; + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_0_s + ee_n_gsi_ch_k_scratch_0; + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_1_s + ee_n_gsi_ch_k_scratch_1; + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_2_s + ee_n_gsi_ch_k_scratch_2; + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_3_s + ee_n_gsi_ch_k_scratch_3; +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_4_s + ee_n_gsi_ch_k_scratch_4; + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_5_s + ee_n_gsi_ch_k_scratch_5; + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_6_s + ee_n_gsi_ch_k_scratch_6; + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_7_s + ee_n_gsi_ch_k_scratch_7; + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_8_s + ee_n_gsi_ch_k_scratch_8; + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_9_s + ee_n_gsi_ch_k_scratch_9; +#endif + struct gsi_hwio_def_gsi_map_ee_n_ch_k_vp_table_s + gsi_map_ee_n_ch_k_vp_table; + struct ipa_reg_save_gsi_mcs_channel_scratch_regs_s + mcs_channel_scratch; +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + union ipa_hwio_def_fc_stats_state_u + fc_stats_state; +#endif +}; + +/* GSI Event Context register save data struct */ +struct ipa_reg_save_gsi_evt_cntxt_per_ep_s { + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_0_s + ee_n_ev_ch_k_cntxt_0; + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_1_s + ee_n_ev_ch_k_cntxt_1; + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_2_s + ee_n_ev_ch_k_cntxt_2; + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_3_s + ee_n_ev_ch_k_cntxt_3; + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_4_s + ee_n_ev_ch_k_cntxt_4; + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_5_s + ee_n_ev_ch_k_cntxt_5; + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_6_s + ee_n_ev_ch_k_cntxt_6; + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_7_s + ee_n_ev_ch_k_cntxt_7; + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_8_s + ee_n_ev_ch_k_cntxt_8; + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_9_s + ee_n_ev_ch_k_cntxt_9; + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_10_s + ee_n_ev_ch_k_cntxt_10; + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_11_s + ee_n_ev_ch_k_cntxt_11; + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_12_s + ee_n_ev_ch_k_cntxt_12; + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_13_s + ee_n_ev_ch_k_cntxt_13; + struct gsi_hwio_def_ee_n_ev_ch_k_scratch_0_s + ee_n_ev_ch_k_scratch_0; + struct gsi_hwio_def_ee_n_ev_ch_k_scratch_1_s + ee_n_ev_ch_k_scratch_1; + struct gsi_hwio_def_gsi_debug_ee_n_ev_k_vp_table_s + gsi_debug_ee_n_ev_k_vp_table; +}; + +/* GSI FIFO status register save data struct */ +struct ipa_reg_save_gsi_fifo_status_s { + union ipa_hwio_def_ipa_gsi_fifo_status_ctrl_u + gsi_fifo_status_ctrl; + union ipa_hwio_def_ipa_gsi_tlv_fifo_status_u + gsi_tlv_fifo_status; + union ipa_hwio_def_ipa_gsi_aos_fifo_status_u + gsi_aos_fifo_status; +}; + +/* GSI Channel Context register save top level data struct */ +struct ipa_reg_save_gsi_ch_cntxt_s { + struct ipa_reg_save_gsi_ch_cntxt_per_ep_s + a7[IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_A7]; + struct ipa_reg_save_gsi_ch_cntxt_per_ep_s + uc[IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_UC]; +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_reg_save_gsi_ch_cntxt_per_ep_s + q6[IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_Q6]; +#endif +}; + +/* GSI Event Context register save top level data struct */ +struct ipa_reg_save_gsi_evt_cntxt_s { + struct ipa_reg_save_gsi_evt_cntxt_per_ep_s + a7[IPA_HW_REG_SAVE_GSI_NUM_EVT_CNTXT_A7]; + struct ipa_reg_save_gsi_evt_cntxt_per_ep_s + uc[IPA_HW_REG_SAVE_GSI_NUM_EVT_CNTXT_UC]; +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_reg_save_gsi_evt_cntxt_per_ep_s + q6[IPA_HW_REG_SAVE_GSI_NUM_EVT_CNTXT_Q6]; +#endif +}; + +/* Top level IPA register save data struct */ +struct ipa_regs_save_hierarchy_s { + struct ipa_gen_regs_s + gen; + struct ipa_reg_save_gen_ee_s + gen_ee[IPA_HW_EE_MAX]; + struct ipa_reg_save_stat_ee_s + stat_ee[IPA_HW_EE_MAX]; + struct ipa_reg_save_hwp_s + hwp; + struct ipa_reg_save_dbg_s + dbg; + struct ipa_reg_save_ipa_testbus_s + *testbus; + struct ipa_reg_save_pipe_s + pipes[IPA_HW_PIPE_ID_MAX]; + struct ipa_reg_save_src_rsrc_grp_s + src_rsrc_grp[IPA_HW_SRC_RSRP_TYPE_MAX]; + struct ipa_reg_save_dst_rsrc_grp_s + dst_rsrc_grp[IPA_HW_DST_RSRP_TYPE_MAX]; + struct ipa_reg_save_src_rsrc_cnt_s + src_rsrc_cnt[IPA_HW_SRC_RSRP_TYPE_MAX]; + struct ipa_reg_save_dst_rsrc_cnt_s + dst_rsrc_cnt[IPA_HW_DST_RSRP_TYPE_MAX]; + u32 *ipa_iu_ptr; + u32 *ipa_sram_ptr; + u32 *ipa_mbox_ptr; + u32 *ipa_hram_ptr; + u32 *ipa_seq_ptr; + u32 *ipa_gsi_ptr; +}; + +/* Top level GSI register save data struct */ +struct gsi_regs_save_hierarchy_s { + u32 fw_ver; + struct ipa_reg_save_gsi_gen_s gen; + struct ipa_reg_save_gsi_gen_ee_s gen_ee[IPA_REG_SAVE_GSI_NUM_EE]; + struct ipa_reg_save_gsi_ch_cntxt_s ch_cntxt; + struct ipa_reg_save_gsi_evt_cntxt_s evt_cntxt; + struct ipa_reg_save_gsi_debug_s debug; +}; + +/* Source resources for a resource group */ +struct ipa_reg_save_src_rsrc_cnts_s { + u8 pkt_cntxt; + u8 descriptor_list; + u8 data_descriptor_buffer; + u8 hps_dmars; + u8 reserved_acks; +}; + +/* Destination resources for a resource group */ +struct ipa_reg_save_dst_rsrc_cnts_s { + u8 reserved_sectors; + u8 dps_dmars; +}; + +/* Resource count structure for a resource group */ +struct ipa_reg_save_rsrc_cnts_per_grp_s { + /* Resource group number */ + u8 resource_group; + /* Source resources for a resource group */ + struct ipa_reg_save_src_rsrc_cnts_s src; + /* Destination resources for a resource group */ + struct ipa_reg_save_dst_rsrc_cnts_s dst; +}; + +/* Top level resource count structure */ +struct ipa_reg_save_rsrc_cnts_s { + /* Resource count structure for PCIE group */ + struct ipa_reg_save_rsrc_cnts_per_grp_s pcie; + /* Resource count structure for DDR group */ + struct ipa_reg_save_rsrc_cnts_per_grp_s ddr; +}; + +/* + * Top level IPA and GSI registers save data struct + */ +struct regs_save_hierarchy_s { + struct ipa_regs_save_hierarchy_s + ipa; + struct gsi_regs_save_hierarchy_s + gsi; + bool + pkt_ctntx_active[IPA_HW_PKT_CTNTX_MAX]; + union ipa_hwio_def_ipa_ctxh_ctrl_u + pkt_ctntxt_lock; + enum ipa_hw_pkt_cntxt_state_e + pkt_cntxt_state[IPA_HW_PKT_CTNTX_MAX]; + struct ipa_pkt_ctntx_s + pkt_ctntx[IPA_HW_PKT_CTNTX_MAX]; + struct ipa_reg_save_rsrc_cnts_s + rsrc_cnts; + struct ipa_reg_save_gsi_fifo_status_s + gsi_fifo_status[IPA_HW_PIPE_ID_MAX]; +}; + +/* + * The following section deals with handling IPA registers' memory + * access relative to pre-defined memory protection schemes + * (ie. "access control"). + * + * In a nut shell, the intent of the data stuctures below is to allow + * higher level register accessors to be unaware of what really is + * going on at the lowest level (ie. real vs non-real access). This + * methodology is also designed to allow for platform specific "access + * maps." + */ + +/* + * Function for doing an actual read + */ +static inline u32 +act_read(void __iomem *addr) +{ + u32 val = ioread32(addr); + + return val; +} + +/* + * Function for doing an actual write + */ +static inline void +act_write(void __iomem *addr, u32 val) +{ + iowrite32(val, addr); +} + +/* + * Function that pretends to do a read + */ +static inline u32 +nop_read(void __iomem *addr) +{ + return IPA_MEM_INIT_VAL; +} + +/* + * Function that pretends to do a write + */ +static inline void +nop_write(void __iomem *addr, u32 val) +{ +} + +/* + * The following are used to define struct reg_access_funcs_s below... + */ +typedef u32 (*reg_read_func_t)( + void __iomem *addr); +typedef void (*reg_write_func_t)( + void __iomem *addr, + u32 val); + +/* + * The following in used to define io_matrix[] below... + */ +struct reg_access_funcs_s { + reg_read_func_t read; + reg_write_func_t write; +}; + +/* + * The following will be used to appropriately index into the + * read/write combos defined in io_matrix[] below... + */ +#define AA_COMBO 0 /* actual read, actual write */ +#define AN_COMBO 1 /* actual read, no-op write */ +#define NA_COMBO 2 /* no-op read, actual write */ +#define NN_COMBO 3 /* no-op read, no-op write */ + +/* + * The following will be used to dictate registers' access methods + * relative to the state of secure debug...whether it's enabled or + * disabled. + * + * NOTE: The table below defines all access combinations. + */ +static struct reg_access_funcs_s io_matrix[] = { + { act_read, act_write }, /* the AA_COMBO */ + { act_read, nop_write }, /* the AN_COMBO */ + { nop_read, act_write }, /* the NA_COMBO */ + { nop_read, nop_write }, /* the NN_COMBO */ +}; + +/* + * The following will be used to define and drive IPA's register + * access rules. + */ +struct reg_mem_access_map_t { + u32 addr_range_begin; + u32 addr_range_end; + struct reg_access_funcs_s *access[2]; +}; + +#endif /* #if !defined(_IPA_REG_DUMP_H_) */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.0/gsi_hwio.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.0/gsi_hwio.h new file mode 100644 index 0000000000..1248e5c864 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.0/gsi_hwio.h @@ -0,0 +1,4602 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ + +#ifndef __GSI_HWIO_H__ +#define __GSI_HWIO_H__ +/** + @file gsi_hwio.h + @brief Auto-generated HWIO interface include file. + + This file contains HWIO register definitions for the following modules: + IPA_0_GSI_TOP_.* + + 'Include' filters applied: + 'Exclude' filters applied: RESERVED DUMMY + + Attribute definitions for the HWIO_*_ATTR macros are as follows: + 0x0: Command register + 0x1: Read-Only + 0x2: Write-Only + 0x3: Read/Write +*/ + +/*---------------------------------------------------------------------------- + * MODULE: GSI + *--------------------------------------------------------------------------*/ + +#define GSI_REG_BASE (IPA_0_IPA_WRAPPER_BASE + 0x00004000) +#define GSI_REG_BASE_PHYS (IPA_0_IPA_WRAPPER_BASE_PHYS + 0x00004000) +#define GSI_REG_BASE_OFFS 0x00004000 + +#define HWIO_GSI_CFG_ADDR (GSI_REG_BASE + 0x00000000) +#define HWIO_GSI_CFG_PHYS (GSI_REG_BASE_PHYS + 0x00000000) +#define HWIO_GSI_CFG_OFFS (GSI_REG_BASE_OFFS + 0x00000000) +#define HWIO_GSI_CFG_RMSK 0xf3f +#define HWIO_GSI_CFG_ATTR 0x3 +#define HWIO_GSI_CFG_IN \ + in_dword_masked(HWIO_GSI_CFG_ADDR, HWIO_GSI_CFG_RMSK) +#define HWIO_GSI_CFG_INM(m) \ + in_dword_masked(HWIO_GSI_CFG_ADDR, m) +#define HWIO_GSI_CFG_OUT(v) \ + out_dword(HWIO_GSI_CFG_ADDR,v) +#define HWIO_GSI_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_CFG_ADDR,m,v,HWIO_GSI_CFG_IN) +#define HWIO_GSI_CFG_SLEEP_CLK_DIV_BMSK 0xf00 +#define HWIO_GSI_CFG_SLEEP_CLK_DIV_SHFT 0x8 +#define HWIO_GSI_CFG_BP_MTRIX_DISABLE_BMSK 0x20 +#define HWIO_GSI_CFG_BP_MTRIX_DISABLE_SHFT 0x5 +#define HWIO_GSI_CFG_GSI_PWR_CLPS_BMSK 0x10 +#define HWIO_GSI_CFG_GSI_PWR_CLPS_SHFT 0x4 +#define HWIO_GSI_CFG_UC_IS_MCS_BMSK 0x8 +#define HWIO_GSI_CFG_UC_IS_MCS_SHFT 0x3 +#define HWIO_GSI_CFG_DOUBLE_MCS_CLK_FREQ_BMSK 0x4 +#define HWIO_GSI_CFG_DOUBLE_MCS_CLK_FREQ_SHFT 0x2 +#define HWIO_GSI_CFG_MCS_ENABLE_BMSK 0x2 +#define HWIO_GSI_CFG_MCS_ENABLE_SHFT 0x1 +#define HWIO_GSI_CFG_GSI_ENABLE_BMSK 0x1 +#define HWIO_GSI_CFG_GSI_ENABLE_SHFT 0x0 + +#define HWIO_GSI_MANAGER_MCS_CODE_VER_ADDR (GSI_REG_BASE + 0x00000008) +#define HWIO_GSI_MANAGER_MCS_CODE_VER_PHYS (GSI_REG_BASE_PHYS + 0x00000008) +#define HWIO_GSI_MANAGER_MCS_CODE_VER_OFFS (GSI_REG_BASE_OFFS + 0x00000008) +#define HWIO_GSI_MANAGER_MCS_CODE_VER_RMSK 0xffffffff +#define HWIO_GSI_MANAGER_MCS_CODE_VER_ATTR 0x3 +#define HWIO_GSI_MANAGER_MCS_CODE_VER_IN \ + in_dword_masked(HWIO_GSI_MANAGER_MCS_CODE_VER_ADDR, HWIO_GSI_MANAGER_MCS_CODE_VER_RMSK) +#define HWIO_GSI_MANAGER_MCS_CODE_VER_INM(m) \ + in_dword_masked(HWIO_GSI_MANAGER_MCS_CODE_VER_ADDR, m) +#define HWIO_GSI_MANAGER_MCS_CODE_VER_OUT(v) \ + out_dword(HWIO_GSI_MANAGER_MCS_CODE_VER_ADDR,v) +#define HWIO_GSI_MANAGER_MCS_CODE_VER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_MANAGER_MCS_CODE_VER_ADDR,m,v,HWIO_GSI_MANAGER_MCS_CODE_VER_IN) +#define HWIO_GSI_MANAGER_MCS_CODE_VER_VER_BMSK 0xffffffff +#define HWIO_GSI_MANAGER_MCS_CODE_VER_VER_SHFT 0x0 + +#define HWIO_GSI_ZEROS_ADDR (GSI_REG_BASE + 0x00000010) +#define HWIO_GSI_ZEROS_PHYS (GSI_REG_BASE_PHYS + 0x00000010) +#define HWIO_GSI_ZEROS_OFFS (GSI_REG_BASE_OFFS + 0x00000010) +#define HWIO_GSI_ZEROS_RMSK 0xffffffff +#define HWIO_GSI_ZEROS_ATTR 0x1 +#define HWIO_GSI_ZEROS_IN \ + in_dword_masked(HWIO_GSI_ZEROS_ADDR, HWIO_GSI_ZEROS_RMSK) +#define HWIO_GSI_ZEROS_INM(m) \ + in_dword_masked(HWIO_GSI_ZEROS_ADDR, m) +#define HWIO_GSI_ZEROS_ZEROS_BMSK 0xffffffff +#define HWIO_GSI_ZEROS_ZEROS_SHFT 0x0 + +#define HWIO_GSI_PERIPH_BASE_ADDR_LSB_ADDR (GSI_REG_BASE + 0x00000018) +#define HWIO_GSI_PERIPH_BASE_ADDR_LSB_PHYS (GSI_REG_BASE_PHYS + 0x00000018) +#define HWIO_GSI_PERIPH_BASE_ADDR_LSB_OFFS (GSI_REG_BASE_OFFS + 0x00000018) +#define HWIO_GSI_PERIPH_BASE_ADDR_LSB_RMSK 0xffffffff +#define HWIO_GSI_PERIPH_BASE_ADDR_LSB_ATTR 0x3 +#define HWIO_GSI_PERIPH_BASE_ADDR_LSB_IN \ + in_dword_masked(HWIO_GSI_PERIPH_BASE_ADDR_LSB_ADDR, HWIO_GSI_PERIPH_BASE_ADDR_LSB_RMSK) +#define HWIO_GSI_PERIPH_BASE_ADDR_LSB_INM(m) \ + in_dword_masked(HWIO_GSI_PERIPH_BASE_ADDR_LSB_ADDR, m) +#define HWIO_GSI_PERIPH_BASE_ADDR_LSB_OUT(v) \ + out_dword(HWIO_GSI_PERIPH_BASE_ADDR_LSB_ADDR,v) +#define HWIO_GSI_PERIPH_BASE_ADDR_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_PERIPH_BASE_ADDR_LSB_ADDR,m,v,HWIO_GSI_PERIPH_BASE_ADDR_LSB_IN) +#define HWIO_GSI_PERIPH_BASE_ADDR_LSB_BASE_ADDR_BMSK 0xffffffff +#define HWIO_GSI_PERIPH_BASE_ADDR_LSB_BASE_ADDR_SHFT 0x0 + +#define HWIO_GSI_PERIPH_BASE_ADDR_MSB_ADDR (GSI_REG_BASE + 0x0000001c) +#define HWIO_GSI_PERIPH_BASE_ADDR_MSB_PHYS (GSI_REG_BASE_PHYS + 0x0000001c) +#define HWIO_GSI_PERIPH_BASE_ADDR_MSB_OFFS (GSI_REG_BASE_OFFS + 0x0000001c) +#define HWIO_GSI_PERIPH_BASE_ADDR_MSB_RMSK 0xffffffff +#define HWIO_GSI_PERIPH_BASE_ADDR_MSB_ATTR 0x3 +#define HWIO_GSI_PERIPH_BASE_ADDR_MSB_IN \ + in_dword_masked(HWIO_GSI_PERIPH_BASE_ADDR_MSB_ADDR, HWIO_GSI_PERIPH_BASE_ADDR_MSB_RMSK) +#define HWIO_GSI_PERIPH_BASE_ADDR_MSB_INM(m) \ + in_dword_masked(HWIO_GSI_PERIPH_BASE_ADDR_MSB_ADDR, m) +#define HWIO_GSI_PERIPH_BASE_ADDR_MSB_OUT(v) \ + out_dword(HWIO_GSI_PERIPH_BASE_ADDR_MSB_ADDR,v) +#define HWIO_GSI_PERIPH_BASE_ADDR_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_PERIPH_BASE_ADDR_MSB_ADDR,m,v,HWIO_GSI_PERIPH_BASE_ADDR_MSB_IN) +#define HWIO_GSI_PERIPH_BASE_ADDR_MSB_BASE_ADDR_BMSK 0xffffffff +#define HWIO_GSI_PERIPH_BASE_ADDR_MSB_BASE_ADDR_SHFT 0x0 + +#define HWIO_GSI_CGC_CTRL_ADDR (GSI_REG_BASE + 0x00000020) +#define HWIO_GSI_CGC_CTRL_PHYS (GSI_REG_BASE_PHYS + 0x00000020) +#define HWIO_GSI_CGC_CTRL_OFFS (GSI_REG_BASE_OFFS + 0x00000020) +#define HWIO_GSI_CGC_CTRL_RMSK 0xffff +#define HWIO_GSI_CGC_CTRL_ATTR 0x3 +#define HWIO_GSI_CGC_CTRL_IN \ + in_dword_masked(HWIO_GSI_CGC_CTRL_ADDR, HWIO_GSI_CGC_CTRL_RMSK) +#define HWIO_GSI_CGC_CTRL_INM(m) \ + in_dword_masked(HWIO_GSI_CGC_CTRL_ADDR, m) +#define HWIO_GSI_CGC_CTRL_OUT(v) \ + out_dword(HWIO_GSI_CGC_CTRL_ADDR,v) +#define HWIO_GSI_CGC_CTRL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_CGC_CTRL_ADDR,m,v,HWIO_GSI_CGC_CTRL_IN) +#define HWIO_GSI_CGC_CTRL_REGION_16_HW_CGC_EN_BMSK 0x8000 +#define HWIO_GSI_CGC_CTRL_REGION_16_HW_CGC_EN_SHFT 0xf +#define HWIO_GSI_CGC_CTRL_REGION_15_HW_CGC_EN_BMSK 0x4000 +#define HWIO_GSI_CGC_CTRL_REGION_15_HW_CGC_EN_SHFT 0xe +#define HWIO_GSI_CGC_CTRL_REGION_14_HW_CGC_EN_BMSK 0x2000 +#define HWIO_GSI_CGC_CTRL_REGION_14_HW_CGC_EN_SHFT 0xd +#define HWIO_GSI_CGC_CTRL_REGION_13_HW_CGC_EN_BMSK 0x1000 +#define HWIO_GSI_CGC_CTRL_REGION_13_HW_CGC_EN_SHFT 0xc +#define HWIO_GSI_CGC_CTRL_REGION_12_HW_CGC_EN_BMSK 0x800 +#define HWIO_GSI_CGC_CTRL_REGION_12_HW_CGC_EN_SHFT 0xb +#define HWIO_GSI_CGC_CTRL_REGION_11_HW_CGC_EN_BMSK 0x400 +#define HWIO_GSI_CGC_CTRL_REGION_11_HW_CGC_EN_SHFT 0xa +#define HWIO_GSI_CGC_CTRL_REGION_10_HW_CGC_EN_BMSK 0x200 +#define HWIO_GSI_CGC_CTRL_REGION_10_HW_CGC_EN_SHFT 0x9 +#define HWIO_GSI_CGC_CTRL_REGION_9_HW_CGC_EN_BMSK 0x100 +#define HWIO_GSI_CGC_CTRL_REGION_9_HW_CGC_EN_SHFT 0x8 +#define HWIO_GSI_CGC_CTRL_REGION_8_HW_CGC_EN_BMSK 0x80 +#define HWIO_GSI_CGC_CTRL_REGION_8_HW_CGC_EN_SHFT 0x7 +#define HWIO_GSI_CGC_CTRL_REGION_7_HW_CGC_EN_BMSK 0x40 +#define HWIO_GSI_CGC_CTRL_REGION_7_HW_CGC_EN_SHFT 0x6 +#define HWIO_GSI_CGC_CTRL_REGION_6_HW_CGC_EN_BMSK 0x20 +#define HWIO_GSI_CGC_CTRL_REGION_6_HW_CGC_EN_SHFT 0x5 +#define HWIO_GSI_CGC_CTRL_REGION_5_HW_CGC_EN_BMSK 0x10 +#define HWIO_GSI_CGC_CTRL_REGION_5_HW_CGC_EN_SHFT 0x4 +#define HWIO_GSI_CGC_CTRL_REGION_4_HW_CGC_EN_BMSK 0x8 +#define HWIO_GSI_CGC_CTRL_REGION_4_HW_CGC_EN_SHFT 0x3 +#define HWIO_GSI_CGC_CTRL_REGION_3_HW_CGC_EN_BMSK 0x4 +#define HWIO_GSI_CGC_CTRL_REGION_3_HW_CGC_EN_SHFT 0x2 +#define HWIO_GSI_CGC_CTRL_REGION_2_HW_CGC_EN_BMSK 0x2 +#define HWIO_GSI_CGC_CTRL_REGION_2_HW_CGC_EN_SHFT 0x1 +#define HWIO_GSI_CGC_CTRL_REGION_1_HW_CGC_EN_BMSK 0x1 +#define HWIO_GSI_CGC_CTRL_REGION_1_HW_CGC_EN_SHFT 0x0 + +#define HWIO_GSI_MOQA_CFG_ADDR (GSI_REG_BASE + 0x00000030) +#define HWIO_GSI_MOQA_CFG_PHYS (GSI_REG_BASE_PHYS + 0x00000030) +#define HWIO_GSI_MOQA_CFG_OFFS (GSI_REG_BASE_OFFS + 0x00000030) +#define HWIO_GSI_MOQA_CFG_RMSK 0xffffff +#define HWIO_GSI_MOQA_CFG_ATTR 0x3 +#define HWIO_GSI_MOQA_CFG_IN \ + in_dword_masked(HWIO_GSI_MOQA_CFG_ADDR, HWIO_GSI_MOQA_CFG_RMSK) +#define HWIO_GSI_MOQA_CFG_INM(m) \ + in_dword_masked(HWIO_GSI_MOQA_CFG_ADDR, m) +#define HWIO_GSI_MOQA_CFG_OUT(v) \ + out_dword(HWIO_GSI_MOQA_CFG_ADDR,v) +#define HWIO_GSI_MOQA_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_MOQA_CFG_ADDR,m,v,HWIO_GSI_MOQA_CFG_IN) +#define HWIO_GSI_MOQA_CFG_CLIENT_OOWR_BMSK 0xff0000 +#define HWIO_GSI_MOQA_CFG_CLIENT_OOWR_SHFT 0x10 +#define HWIO_GSI_MOQA_CFG_CLIENT_OORD_BMSK 0xff00 +#define HWIO_GSI_MOQA_CFG_CLIENT_OORD_SHFT 0x8 +#define HWIO_GSI_MOQA_CFG_CLIENT_REQ_PRIO_BMSK 0xff +#define HWIO_GSI_MOQA_CFG_CLIENT_REQ_PRIO_SHFT 0x0 + +#define HWIO_GSI_REE_CFG_ADDR (GSI_REG_BASE + 0x00000038) +#define HWIO_GSI_REE_CFG_PHYS (GSI_REG_BASE_PHYS + 0x00000038) +#define HWIO_GSI_REE_CFG_OFFS (GSI_REG_BASE_OFFS + 0x00000038) +#define HWIO_GSI_REE_CFG_RMSK 0xff03 +#define HWIO_GSI_REE_CFG_ATTR 0x3 +#define HWIO_GSI_REE_CFG_IN \ + in_dword_masked(HWIO_GSI_REE_CFG_ADDR, HWIO_GSI_REE_CFG_RMSK) +#define HWIO_GSI_REE_CFG_INM(m) \ + in_dword_masked(HWIO_GSI_REE_CFG_ADDR, m) +#define HWIO_GSI_REE_CFG_OUT(v) \ + out_dword(HWIO_GSI_REE_CFG_ADDR,v) +#define HWIO_GSI_REE_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_REE_CFG_ADDR,m,v,HWIO_GSI_REE_CFG_IN) +#define HWIO_GSI_REE_CFG_MAX_BURST_SIZE_BMSK 0xff00 +#define HWIO_GSI_REE_CFG_MAX_BURST_SIZE_SHFT 0x8 +#define HWIO_GSI_REE_CFG_CHANNEL_EMPTY_INT_ENABLE_BMSK 0x2 +#define HWIO_GSI_REE_CFG_CHANNEL_EMPTY_INT_ENABLE_SHFT 0x1 +#define HWIO_GSI_REE_CFG_MOVE_TO_ESC_CLR_MODE_TRSH_BMSK 0x1 +#define HWIO_GSI_REE_CFG_MOVE_TO_ESC_CLR_MODE_TRSH_SHFT 0x0 + +#define HWIO_GSI_PERIPH_PENDING_k_ADDR(k) (GSI_REG_BASE + 0x00000060 + 0x4 * (k)) +#define HWIO_GSI_PERIPH_PENDING_k_PHYS(k) (GSI_REG_BASE_PHYS + 0x00000060 + 0x4 * (k)) +#define HWIO_GSI_PERIPH_PENDING_k_OFFS(k) (GSI_REG_BASE_OFFS + 0x00000060 + 0x4 * (k)) +#define HWIO_GSI_PERIPH_PENDING_k_RMSK 0xffffffff +#define HWIO_GSI_PERIPH_PENDING_k_MAXk 1 +#define HWIO_GSI_PERIPH_PENDING_k_ATTR 0x1 +#define HWIO_GSI_PERIPH_PENDING_k_INI(k) \ + in_dword_masked(HWIO_GSI_PERIPH_PENDING_k_ADDR(k), HWIO_GSI_PERIPH_PENDING_k_RMSK) +#define HWIO_GSI_PERIPH_PENDING_k_INMI(k,mask) \ + in_dword_masked(HWIO_GSI_PERIPH_PENDING_k_ADDR(k), mask) +#define HWIO_GSI_PERIPH_PENDING_k_CHID_BIT_MAP_BMSK 0xffffffff +#define HWIO_GSI_PERIPH_PENDING_k_CHID_BIT_MAP_SHFT 0x0 + +#define HWIO_GSI_MSI_CACHEATTR_ADDR (GSI_REG_BASE + 0x00000080) +#define HWIO_GSI_MSI_CACHEATTR_PHYS (GSI_REG_BASE_PHYS + 0x00000080) +#define HWIO_GSI_MSI_CACHEATTR_OFFS (GSI_REG_BASE_OFFS + 0x00000080) +#define HWIO_GSI_MSI_CACHEATTR_RMSK 0x3f +#define HWIO_GSI_MSI_CACHEATTR_ATTR 0x3 +#define HWIO_GSI_MSI_CACHEATTR_IN \ + in_dword_masked(HWIO_GSI_MSI_CACHEATTR_ADDR, HWIO_GSI_MSI_CACHEATTR_RMSK) +#define HWIO_GSI_MSI_CACHEATTR_INM(m) \ + in_dword_masked(HWIO_GSI_MSI_CACHEATTR_ADDR, m) +#define HWIO_GSI_MSI_CACHEATTR_OUT(v) \ + out_dword(HWIO_GSI_MSI_CACHEATTR_ADDR,v) +#define HWIO_GSI_MSI_CACHEATTR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_MSI_CACHEATTR_ADDR,m,v,HWIO_GSI_MSI_CACHEATTR_IN) +#define HWIO_GSI_MSI_CACHEATTR_AREQPRIORITY_BMSK 0x30 +#define HWIO_GSI_MSI_CACHEATTR_AREQPRIORITY_SHFT 0x4 +#define HWIO_GSI_MSI_CACHEATTR_ATRANSIENT_BMSK 0x8 +#define HWIO_GSI_MSI_CACHEATTR_ATRANSIENT_SHFT 0x3 +#define HWIO_GSI_MSI_CACHEATTR_ANOALLOCATE_BMSK 0x4 +#define HWIO_GSI_MSI_CACHEATTR_ANOALLOCATE_SHFT 0x2 +#define HWIO_GSI_MSI_CACHEATTR_AINNERSHARED_BMSK 0x2 +#define HWIO_GSI_MSI_CACHEATTR_AINNERSHARED_SHFT 0x1 +#define HWIO_GSI_MSI_CACHEATTR_ASHARED_BMSK 0x1 +#define HWIO_GSI_MSI_CACHEATTR_ASHARED_SHFT 0x0 + +#define HWIO_GSI_EVENT_CACHEATTR_ADDR (GSI_REG_BASE + 0x00000084) +#define HWIO_GSI_EVENT_CACHEATTR_PHYS (GSI_REG_BASE_PHYS + 0x00000084) +#define HWIO_GSI_EVENT_CACHEATTR_OFFS (GSI_REG_BASE_OFFS + 0x00000084) +#define HWIO_GSI_EVENT_CACHEATTR_RMSK 0x3f +#define HWIO_GSI_EVENT_CACHEATTR_ATTR 0x3 +#define HWIO_GSI_EVENT_CACHEATTR_IN \ + in_dword_masked(HWIO_GSI_EVENT_CACHEATTR_ADDR, HWIO_GSI_EVENT_CACHEATTR_RMSK) +#define HWIO_GSI_EVENT_CACHEATTR_INM(m) \ + in_dword_masked(HWIO_GSI_EVENT_CACHEATTR_ADDR, m) +#define HWIO_GSI_EVENT_CACHEATTR_OUT(v) \ + out_dword(HWIO_GSI_EVENT_CACHEATTR_ADDR,v) +#define HWIO_GSI_EVENT_CACHEATTR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_EVENT_CACHEATTR_ADDR,m,v,HWIO_GSI_EVENT_CACHEATTR_IN) +#define HWIO_GSI_EVENT_CACHEATTR_AREQPRIORITY_BMSK 0x30 +#define HWIO_GSI_EVENT_CACHEATTR_AREQPRIORITY_SHFT 0x4 +#define HWIO_GSI_EVENT_CACHEATTR_ATRANSIENT_BMSK 0x8 +#define HWIO_GSI_EVENT_CACHEATTR_ATRANSIENT_SHFT 0x3 +#define HWIO_GSI_EVENT_CACHEATTR_ANOALLOCATE_BMSK 0x4 +#define HWIO_GSI_EVENT_CACHEATTR_ANOALLOCATE_SHFT 0x2 +#define HWIO_GSI_EVENT_CACHEATTR_AINNERSHARED_BMSK 0x2 +#define HWIO_GSI_EVENT_CACHEATTR_AINNERSHARED_SHFT 0x1 +#define HWIO_GSI_EVENT_CACHEATTR_ASHARED_BMSK 0x1 +#define HWIO_GSI_EVENT_CACHEATTR_ASHARED_SHFT 0x0 + +#define HWIO_GSI_DATA_CACHEATTR_ADDR (GSI_REG_BASE + 0x00000088) +#define HWIO_GSI_DATA_CACHEATTR_PHYS (GSI_REG_BASE_PHYS + 0x00000088) +#define HWIO_GSI_DATA_CACHEATTR_OFFS (GSI_REG_BASE_OFFS + 0x00000088) +#define HWIO_GSI_DATA_CACHEATTR_RMSK 0x3f +#define HWIO_GSI_DATA_CACHEATTR_ATTR 0x3 +#define HWIO_GSI_DATA_CACHEATTR_IN \ + in_dword_masked(HWIO_GSI_DATA_CACHEATTR_ADDR, HWIO_GSI_DATA_CACHEATTR_RMSK) +#define HWIO_GSI_DATA_CACHEATTR_INM(m) \ + in_dword_masked(HWIO_GSI_DATA_CACHEATTR_ADDR, m) +#define HWIO_GSI_DATA_CACHEATTR_OUT(v) \ + out_dword(HWIO_GSI_DATA_CACHEATTR_ADDR,v) +#define HWIO_GSI_DATA_CACHEATTR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_DATA_CACHEATTR_ADDR,m,v,HWIO_GSI_DATA_CACHEATTR_IN) +#define HWIO_GSI_DATA_CACHEATTR_AREQPRIORITY_BMSK 0x30 +#define HWIO_GSI_DATA_CACHEATTR_AREQPRIORITY_SHFT 0x4 +#define HWIO_GSI_DATA_CACHEATTR_ATRANSIENT_BMSK 0x8 +#define HWIO_GSI_DATA_CACHEATTR_ATRANSIENT_SHFT 0x3 +#define HWIO_GSI_DATA_CACHEATTR_ANOALLOCATE_BMSK 0x4 +#define HWIO_GSI_DATA_CACHEATTR_ANOALLOCATE_SHFT 0x2 +#define HWIO_GSI_DATA_CACHEATTR_AINNERSHARED_BMSK 0x2 +#define HWIO_GSI_DATA_CACHEATTR_AINNERSHARED_SHFT 0x1 +#define HWIO_GSI_DATA_CACHEATTR_ASHARED_BMSK 0x1 +#define HWIO_GSI_DATA_CACHEATTR_ASHARED_SHFT 0x0 + +#define HWIO_GSI_TRE_CACHEATTR_ADDR (GSI_REG_BASE + 0x00000090) +#define HWIO_GSI_TRE_CACHEATTR_PHYS (GSI_REG_BASE_PHYS + 0x00000090) +#define HWIO_GSI_TRE_CACHEATTR_OFFS (GSI_REG_BASE_OFFS + 0x00000090) +#define HWIO_GSI_TRE_CACHEATTR_RMSK 0x3f +#define HWIO_GSI_TRE_CACHEATTR_ATTR 0x3 +#define HWIO_GSI_TRE_CACHEATTR_IN \ + in_dword_masked(HWIO_GSI_TRE_CACHEATTR_ADDR, HWIO_GSI_TRE_CACHEATTR_RMSK) +#define HWIO_GSI_TRE_CACHEATTR_INM(m) \ + in_dword_masked(HWIO_GSI_TRE_CACHEATTR_ADDR, m) +#define HWIO_GSI_TRE_CACHEATTR_OUT(v) \ + out_dword(HWIO_GSI_TRE_CACHEATTR_ADDR,v) +#define HWIO_GSI_TRE_CACHEATTR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_TRE_CACHEATTR_ADDR,m,v,HWIO_GSI_TRE_CACHEATTR_IN) +#define HWIO_GSI_TRE_CACHEATTR_AREQPRIORITY_BMSK 0x30 +#define HWIO_GSI_TRE_CACHEATTR_AREQPRIORITY_SHFT 0x4 +#define HWIO_GSI_TRE_CACHEATTR_ATRANSIENT_BMSK 0x8 +#define HWIO_GSI_TRE_CACHEATTR_ATRANSIENT_SHFT 0x3 +#define HWIO_GSI_TRE_CACHEATTR_ANOALLOCATE_BMSK 0x4 +#define HWIO_GSI_TRE_CACHEATTR_ANOALLOCATE_SHFT 0x2 +#define HWIO_GSI_TRE_CACHEATTR_AINNERSHARED_BMSK 0x2 +#define HWIO_GSI_TRE_CACHEATTR_AINNERSHARED_SHFT 0x1 +#define HWIO_GSI_TRE_CACHEATTR_ASHARED_BMSK 0x1 +#define HWIO_GSI_TRE_CACHEATTR_ASHARED_SHFT 0x0 + +#define HWIO_IC_INT_WEIGHT_REE_ADDR (GSI_REG_BASE + 0x00000100) +#define HWIO_IC_INT_WEIGHT_REE_PHYS (GSI_REG_BASE_PHYS + 0x00000100) +#define HWIO_IC_INT_WEIGHT_REE_OFFS (GSI_REG_BASE_OFFS + 0x00000100) +#define HWIO_IC_INT_WEIGHT_REE_RMSK 0xfff +#define HWIO_IC_INT_WEIGHT_REE_ATTR 0x3 +#define HWIO_IC_INT_WEIGHT_REE_IN \ + in_dword_masked(HWIO_IC_INT_WEIGHT_REE_ADDR, HWIO_IC_INT_WEIGHT_REE_RMSK) +#define HWIO_IC_INT_WEIGHT_REE_INM(m) \ + in_dword_masked(HWIO_IC_INT_WEIGHT_REE_ADDR, m) +#define HWIO_IC_INT_WEIGHT_REE_OUT(v) \ + out_dword(HWIO_IC_INT_WEIGHT_REE_ADDR,v) +#define HWIO_IC_INT_WEIGHT_REE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IC_INT_WEIGHT_REE_ADDR,m,v,HWIO_IC_INT_WEIGHT_REE_IN) +#define HWIO_IC_INT_WEIGHT_REE_CH_EMPTY_INT_WEIGHT_BMSK 0xf00 +#define HWIO_IC_INT_WEIGHT_REE_CH_EMPTY_INT_WEIGHT_SHFT 0x8 +#define HWIO_IC_INT_WEIGHT_REE_NEW_RE_INT_WEIGHT_BMSK 0xf0 +#define HWIO_IC_INT_WEIGHT_REE_NEW_RE_INT_WEIGHT_SHFT 0x4 +#define HWIO_IC_INT_WEIGHT_REE_STOP_CH_COMP_INT_WEIGHT_BMSK 0xf +#define HWIO_IC_INT_WEIGHT_REE_STOP_CH_COMP_INT_WEIGHT_SHFT 0x0 + +#define HWIO_IC_INT_WEIGHT_EVT_ENG_ADDR (GSI_REG_BASE + 0x00000104) +#define HWIO_IC_INT_WEIGHT_EVT_ENG_PHYS (GSI_REG_BASE_PHYS + 0x00000104) +#define HWIO_IC_INT_WEIGHT_EVT_ENG_OFFS (GSI_REG_BASE_OFFS + 0x00000104) +#define HWIO_IC_INT_WEIGHT_EVT_ENG_RMSK 0xf +#define HWIO_IC_INT_WEIGHT_EVT_ENG_ATTR 0x3 +#define HWIO_IC_INT_WEIGHT_EVT_ENG_IN \ + in_dword_masked(HWIO_IC_INT_WEIGHT_EVT_ENG_ADDR, HWIO_IC_INT_WEIGHT_EVT_ENG_RMSK) +#define HWIO_IC_INT_WEIGHT_EVT_ENG_INM(m) \ + in_dword_masked(HWIO_IC_INT_WEIGHT_EVT_ENG_ADDR, m) +#define HWIO_IC_INT_WEIGHT_EVT_ENG_OUT(v) \ + out_dword(HWIO_IC_INT_WEIGHT_EVT_ENG_ADDR,v) +#define HWIO_IC_INT_WEIGHT_EVT_ENG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IC_INT_WEIGHT_EVT_ENG_ADDR,m,v,HWIO_IC_INT_WEIGHT_EVT_ENG_IN) +#define HWIO_IC_INT_WEIGHT_EVT_ENG_EVNT_ENG_INT_WEIGHT_BMSK 0xf +#define HWIO_IC_INT_WEIGHT_EVT_ENG_EVNT_ENG_INT_WEIGHT_SHFT 0x0 + +#define HWIO_IC_INT_WEIGHT_INT_ENG_ADDR (GSI_REG_BASE + 0x00000108) +#define HWIO_IC_INT_WEIGHT_INT_ENG_PHYS (GSI_REG_BASE_PHYS + 0x00000108) +#define HWIO_IC_INT_WEIGHT_INT_ENG_OFFS (GSI_REG_BASE_OFFS + 0x00000108) +#define HWIO_IC_INT_WEIGHT_INT_ENG_RMSK 0xf +#define HWIO_IC_INT_WEIGHT_INT_ENG_ATTR 0x3 +#define HWIO_IC_INT_WEIGHT_INT_ENG_IN \ + in_dword_masked(HWIO_IC_INT_WEIGHT_INT_ENG_ADDR, HWIO_IC_INT_WEIGHT_INT_ENG_RMSK) +#define HWIO_IC_INT_WEIGHT_INT_ENG_INM(m) \ + in_dword_masked(HWIO_IC_INT_WEIGHT_INT_ENG_ADDR, m) +#define HWIO_IC_INT_WEIGHT_INT_ENG_OUT(v) \ + out_dword(HWIO_IC_INT_WEIGHT_INT_ENG_ADDR,v) +#define HWIO_IC_INT_WEIGHT_INT_ENG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IC_INT_WEIGHT_INT_ENG_ADDR,m,v,HWIO_IC_INT_WEIGHT_INT_ENG_IN) +#define HWIO_IC_INT_WEIGHT_INT_ENG_INT_ENG_INT_WEIGHT_BMSK 0xf +#define HWIO_IC_INT_WEIGHT_INT_ENG_INT_ENG_INT_WEIGHT_SHFT 0x0 + +#define HWIO_IC_INT_WEIGHT_CSR_ADDR (GSI_REG_BASE + 0x0000010c) +#define HWIO_IC_INT_WEIGHT_CSR_PHYS (GSI_REG_BASE_PHYS + 0x0000010c) +#define HWIO_IC_INT_WEIGHT_CSR_OFFS (GSI_REG_BASE_OFFS + 0x0000010c) +#define HWIO_IC_INT_WEIGHT_CSR_RMSK 0xff +#define HWIO_IC_INT_WEIGHT_CSR_ATTR 0x3 +#define HWIO_IC_INT_WEIGHT_CSR_IN \ + in_dword_masked(HWIO_IC_INT_WEIGHT_CSR_ADDR, HWIO_IC_INT_WEIGHT_CSR_RMSK) +#define HWIO_IC_INT_WEIGHT_CSR_INM(m) \ + in_dword_masked(HWIO_IC_INT_WEIGHT_CSR_ADDR, m) +#define HWIO_IC_INT_WEIGHT_CSR_OUT(v) \ + out_dword(HWIO_IC_INT_WEIGHT_CSR_ADDR,v) +#define HWIO_IC_INT_WEIGHT_CSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IC_INT_WEIGHT_CSR_ADDR,m,v,HWIO_IC_INT_WEIGHT_CSR_IN) +#define HWIO_IC_INT_WEIGHT_CSR_EE_GENERIC_INT_WEIGHT_BMSK 0xf0 +#define HWIO_IC_INT_WEIGHT_CSR_EE_GENERIC_INT_WEIGHT_SHFT 0x4 +#define HWIO_IC_INT_WEIGHT_CSR_CH_CMD_INT_WEIGHT_BMSK 0xf +#define HWIO_IC_INT_WEIGHT_CSR_CH_CMD_INT_WEIGHT_SHFT 0x0 + +#define HWIO_IC_INT_WEIGHT_TLV_ENG_ADDR (GSI_REG_BASE + 0x00000110) +#define HWIO_IC_INT_WEIGHT_TLV_ENG_PHYS (GSI_REG_BASE_PHYS + 0x00000110) +#define HWIO_IC_INT_WEIGHT_TLV_ENG_OFFS (GSI_REG_BASE_OFFS + 0x00000110) +#define HWIO_IC_INT_WEIGHT_TLV_ENG_RMSK 0xffff +#define HWIO_IC_INT_WEIGHT_TLV_ENG_ATTR 0x3 +#define HWIO_IC_INT_WEIGHT_TLV_ENG_IN \ + in_dword_masked(HWIO_IC_INT_WEIGHT_TLV_ENG_ADDR, HWIO_IC_INT_WEIGHT_TLV_ENG_RMSK) +#define HWIO_IC_INT_WEIGHT_TLV_ENG_INM(m) \ + in_dword_masked(HWIO_IC_INT_WEIGHT_TLV_ENG_ADDR, m) +#define HWIO_IC_INT_WEIGHT_TLV_ENG_OUT(v) \ + out_dword(HWIO_IC_INT_WEIGHT_TLV_ENG_ADDR,v) +#define HWIO_IC_INT_WEIGHT_TLV_ENG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IC_INT_WEIGHT_TLV_ENG_ADDR,m,v,HWIO_IC_INT_WEIGHT_TLV_ENG_IN) +#define HWIO_IC_INT_WEIGHT_TLV_ENG_CH_NOT_FULL_INT_WEIGHT_BMSK 0xf000 +#define HWIO_IC_INT_WEIGHT_TLV_ENG_CH_NOT_FULL_INT_WEIGHT_SHFT 0xc +#define HWIO_IC_INT_WEIGHT_TLV_ENG_TLV_2_INT_WEIGHT_BMSK 0xf00 +#define HWIO_IC_INT_WEIGHT_TLV_ENG_TLV_2_INT_WEIGHT_SHFT 0x8 +#define HWIO_IC_INT_WEIGHT_TLV_ENG_TLV_1_INT_WEIGHT_BMSK 0xf0 +#define HWIO_IC_INT_WEIGHT_TLV_ENG_TLV_1_INT_WEIGHT_SHFT 0x4 +#define HWIO_IC_INT_WEIGHT_TLV_ENG_TLV_0_INT_WEIGHT_BMSK 0xf +#define HWIO_IC_INT_WEIGHT_TLV_ENG_TLV_0_INT_WEIGHT_SHFT 0x0 + +#define HWIO_IC_INT_WEIGHT_TIMER_ENG_ADDR (GSI_REG_BASE + 0x00000114) +#define HWIO_IC_INT_WEIGHT_TIMER_ENG_PHYS (GSI_REG_BASE_PHYS + 0x00000114) +#define HWIO_IC_INT_WEIGHT_TIMER_ENG_OFFS (GSI_REG_BASE_OFFS + 0x00000114) +#define HWIO_IC_INT_WEIGHT_TIMER_ENG_RMSK 0xf +#define HWIO_IC_INT_WEIGHT_TIMER_ENG_ATTR 0x3 +#define HWIO_IC_INT_WEIGHT_TIMER_ENG_IN \ + in_dword_masked(HWIO_IC_INT_WEIGHT_TIMER_ENG_ADDR, HWIO_IC_INT_WEIGHT_TIMER_ENG_RMSK) +#define HWIO_IC_INT_WEIGHT_TIMER_ENG_INM(m) \ + in_dword_masked(HWIO_IC_INT_WEIGHT_TIMER_ENG_ADDR, m) +#define HWIO_IC_INT_WEIGHT_TIMER_ENG_OUT(v) \ + out_dword(HWIO_IC_INT_WEIGHT_TIMER_ENG_ADDR,v) +#define HWIO_IC_INT_WEIGHT_TIMER_ENG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IC_INT_WEIGHT_TIMER_ENG_ADDR,m,v,HWIO_IC_INT_WEIGHT_TIMER_ENG_IN) +#define HWIO_IC_INT_WEIGHT_TIMER_ENG_TIMER_INT_WEIGHT_BMSK 0xf +#define HWIO_IC_INT_WEIGHT_TIMER_ENG_TIMER_INT_WEIGHT_SHFT 0x0 + +#define HWIO_IC_INT_WEIGHT_DB_ENG_ADDR (GSI_REG_BASE + 0x00000118) +#define HWIO_IC_INT_WEIGHT_DB_ENG_PHYS (GSI_REG_BASE_PHYS + 0x00000118) +#define HWIO_IC_INT_WEIGHT_DB_ENG_OFFS (GSI_REG_BASE_OFFS + 0x00000118) +#define HWIO_IC_INT_WEIGHT_DB_ENG_RMSK 0xf +#define HWIO_IC_INT_WEIGHT_DB_ENG_ATTR 0x3 +#define HWIO_IC_INT_WEIGHT_DB_ENG_IN \ + in_dword_masked(HWIO_IC_INT_WEIGHT_DB_ENG_ADDR, HWIO_IC_INT_WEIGHT_DB_ENG_RMSK) +#define HWIO_IC_INT_WEIGHT_DB_ENG_INM(m) \ + in_dword_masked(HWIO_IC_INT_WEIGHT_DB_ENG_ADDR, m) +#define HWIO_IC_INT_WEIGHT_DB_ENG_OUT(v) \ + out_dword(HWIO_IC_INT_WEIGHT_DB_ENG_ADDR,v) +#define HWIO_IC_INT_WEIGHT_DB_ENG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IC_INT_WEIGHT_DB_ENG_ADDR,m,v,HWIO_IC_INT_WEIGHT_DB_ENG_IN) +#define HWIO_IC_INT_WEIGHT_DB_ENG_NEW_DB_INT_WEIGHT_BMSK 0xf +#define HWIO_IC_INT_WEIGHT_DB_ENG_NEW_DB_INT_WEIGHT_SHFT 0x0 + +#define HWIO_IC_INT_WEIGHT_RD_WR_ENG_ADDR (GSI_REG_BASE + 0x0000011c) +#define HWIO_IC_INT_WEIGHT_RD_WR_ENG_PHYS (GSI_REG_BASE_PHYS + 0x0000011c) +#define HWIO_IC_INT_WEIGHT_RD_WR_ENG_OFFS (GSI_REG_BASE_OFFS + 0x0000011c) +#define HWIO_IC_INT_WEIGHT_RD_WR_ENG_RMSK 0xff +#define HWIO_IC_INT_WEIGHT_RD_WR_ENG_ATTR 0x3 +#define HWIO_IC_INT_WEIGHT_RD_WR_ENG_IN \ + in_dword_masked(HWIO_IC_INT_WEIGHT_RD_WR_ENG_ADDR, HWIO_IC_INT_WEIGHT_RD_WR_ENG_RMSK) +#define HWIO_IC_INT_WEIGHT_RD_WR_ENG_INM(m) \ + in_dword_masked(HWIO_IC_INT_WEIGHT_RD_WR_ENG_ADDR, m) +#define HWIO_IC_INT_WEIGHT_RD_WR_ENG_OUT(v) \ + out_dword(HWIO_IC_INT_WEIGHT_RD_WR_ENG_ADDR,v) +#define HWIO_IC_INT_WEIGHT_RD_WR_ENG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IC_INT_WEIGHT_RD_WR_ENG_ADDR,m,v,HWIO_IC_INT_WEIGHT_RD_WR_ENG_IN) +#define HWIO_IC_INT_WEIGHT_RD_WR_ENG_WRITE_INT_WEIGHT_BMSK 0xf0 +#define HWIO_IC_INT_WEIGHT_RD_WR_ENG_WRITE_INT_WEIGHT_SHFT 0x4 +#define HWIO_IC_INT_WEIGHT_RD_WR_ENG_READ_INT_WEIGHT_BMSK 0xf +#define HWIO_IC_INT_WEIGHT_RD_WR_ENG_READ_INT_WEIGHT_SHFT 0x0 + +#define HWIO_IC_INT_WEIGHT_UCONTROLLER_ENG_ADDR (GSI_REG_BASE + 0x00000120) +#define HWIO_IC_INT_WEIGHT_UCONTROLLER_ENG_PHYS (GSI_REG_BASE_PHYS + 0x00000120) +#define HWIO_IC_INT_WEIGHT_UCONTROLLER_ENG_OFFS (GSI_REG_BASE_OFFS + 0x00000120) +#define HWIO_IC_INT_WEIGHT_UCONTROLLER_ENG_RMSK 0xf +#define HWIO_IC_INT_WEIGHT_UCONTROLLER_ENG_ATTR 0x3 +#define HWIO_IC_INT_WEIGHT_UCONTROLLER_ENG_IN \ + in_dword_masked(HWIO_IC_INT_WEIGHT_UCONTROLLER_ENG_ADDR, HWIO_IC_INT_WEIGHT_UCONTROLLER_ENG_RMSK) +#define HWIO_IC_INT_WEIGHT_UCONTROLLER_ENG_INM(m) \ + in_dword_masked(HWIO_IC_INT_WEIGHT_UCONTROLLER_ENG_ADDR, m) +#define HWIO_IC_INT_WEIGHT_UCONTROLLER_ENG_OUT(v) \ + out_dword(HWIO_IC_INT_WEIGHT_UCONTROLLER_ENG_ADDR,v) +#define HWIO_IC_INT_WEIGHT_UCONTROLLER_ENG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IC_INT_WEIGHT_UCONTROLLER_ENG_ADDR,m,v,HWIO_IC_INT_WEIGHT_UCONTROLLER_ENG_IN) +#define HWIO_IC_INT_WEIGHT_UCONTROLLER_ENG_UCONTROLLER_GP_INT_WEIGHT_BMSK 0xf +#define HWIO_IC_INT_WEIGHT_UCONTROLLER_ENG_UCONTROLLER_GP_INT_WEIGHT_SHFT 0x0 + +#define HWIO_LOW_LATENCY_ARB_WEIGHT_ADDR (GSI_REG_BASE + 0x00000128) +#define HWIO_LOW_LATENCY_ARB_WEIGHT_PHYS (GSI_REG_BASE_PHYS + 0x00000128) +#define HWIO_LOW_LATENCY_ARB_WEIGHT_OFFS (GSI_REG_BASE_OFFS + 0x00000128) +#define HWIO_LOW_LATENCY_ARB_WEIGHT_RMSK 0x13f3f +#define HWIO_LOW_LATENCY_ARB_WEIGHT_ATTR 0x3 +#define HWIO_LOW_LATENCY_ARB_WEIGHT_IN \ + in_dword_masked(HWIO_LOW_LATENCY_ARB_WEIGHT_ADDR, HWIO_LOW_LATENCY_ARB_WEIGHT_RMSK) +#define HWIO_LOW_LATENCY_ARB_WEIGHT_INM(m) \ + in_dword_masked(HWIO_LOW_LATENCY_ARB_WEIGHT_ADDR, m) +#define HWIO_LOW_LATENCY_ARB_WEIGHT_OUT(v) \ + out_dword(HWIO_LOW_LATENCY_ARB_WEIGHT_ADDR,v) +#define HWIO_LOW_LATENCY_ARB_WEIGHT_OUTM(m,v) \ + out_dword_masked_ns(HWIO_LOW_LATENCY_ARB_WEIGHT_ADDR,m,v,HWIO_LOW_LATENCY_ARB_WEIGHT_IN) +#define HWIO_LOW_LATENCY_ARB_WEIGHT_LL_NON_LL_FIX_PRIORITY_BMSK 0x10000 +#define HWIO_LOW_LATENCY_ARB_WEIGHT_LL_NON_LL_FIX_PRIORITY_SHFT 0x10 +#define HWIO_LOW_LATENCY_ARB_WEIGHT_NON_LL_WEIGHT_BMSK 0x3f00 +#define HWIO_LOW_LATENCY_ARB_WEIGHT_NON_LL_WEIGHT_SHFT 0x8 +#define HWIO_LOW_LATENCY_ARB_WEIGHT_LL_WEIGHT_BMSK 0x3f +#define HWIO_LOW_LATENCY_ARB_WEIGHT_LL_WEIGHT_SHFT 0x0 + +#define HWIO_GSI_MANAGER_EE_QOS_n_ADDR(n) (GSI_REG_BASE + 0x00000300 + 0x4 * (n)) +#define HWIO_GSI_MANAGER_EE_QOS_n_PHYS(n) (GSI_REG_BASE_PHYS + 0x00000300 + 0x4 * (n)) +#define HWIO_GSI_MANAGER_EE_QOS_n_OFFS(n) (GSI_REG_BASE_OFFS + 0x00000300 + 0x4 * (n)) +#define HWIO_GSI_MANAGER_EE_QOS_n_RMSK 0xffff03 +#define HWIO_GSI_MANAGER_EE_QOS_n_MAXn 2 +#define HWIO_GSI_MANAGER_EE_QOS_n_ATTR 0x0 +#define HWIO_GSI_MANAGER_EE_QOS_n_INI(n) \ + in_dword_masked(HWIO_GSI_MANAGER_EE_QOS_n_ADDR(n), HWIO_GSI_MANAGER_EE_QOS_n_RMSK) +#define HWIO_GSI_MANAGER_EE_QOS_n_INMI(n,mask) \ + in_dword_masked(HWIO_GSI_MANAGER_EE_QOS_n_ADDR(n), mask) +#define HWIO_GSI_MANAGER_EE_QOS_n_OUTI(n,val) \ + out_dword(HWIO_GSI_MANAGER_EE_QOS_n_ADDR(n),val) +#define HWIO_GSI_MANAGER_EE_QOS_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_GSI_MANAGER_EE_QOS_n_ADDR(n),mask,val,HWIO_GSI_MANAGER_EE_QOS_n_INI(n)) +#define HWIO_GSI_MANAGER_EE_QOS_n_MAX_EV_ALLOC_BMSK 0xff0000 +#define HWIO_GSI_MANAGER_EE_QOS_n_MAX_EV_ALLOC_SHFT 0x10 +#define HWIO_GSI_MANAGER_EE_QOS_n_MAX_CH_ALLOC_BMSK 0xff00 +#define HWIO_GSI_MANAGER_EE_QOS_n_MAX_CH_ALLOC_SHFT 0x8 +#define HWIO_GSI_MANAGER_EE_QOS_n_EE_PRIO_BMSK 0x3 +#define HWIO_GSI_MANAGER_EE_QOS_n_EE_PRIO_SHFT 0x0 + +#define HWIO_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_ADDR (GSI_REG_BASE + 0x00000200) +#define HWIO_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_PHYS (GSI_REG_BASE_PHYS + 0x00000200) +#define HWIO_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_OFFS (GSI_REG_BASE_OFFS + 0x00000200) +#define HWIO_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_RMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_ATTR 0x3 +#define HWIO_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_IN \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_ADDR, HWIO_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_RMSK) +#define HWIO_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_ADDR, m) +#define HWIO_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_OUT(v) \ + out_dword(HWIO_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_ADDR,v) +#define HWIO_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_ADDR,m,v,HWIO_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_IN) +#define HWIO_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_ADDR (GSI_REG_BASE + 0x00000204) +#define HWIO_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_PHYS (GSI_REG_BASE_PHYS + 0x00000204) +#define HWIO_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_OFFS (GSI_REG_BASE_OFFS + 0x00000204) +#define HWIO_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_RMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_ATTR 0x3 +#define HWIO_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_IN \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_ADDR, HWIO_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_RMSK) +#define HWIO_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_ADDR, m) +#define HWIO_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_OUT(v) \ + out_dword(HWIO_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_ADDR,v) +#define HWIO_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_ADDR,m,v,HWIO_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_IN) +#define HWIO_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_ADDR (GSI_REG_BASE + 0x00000208) +#define HWIO_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_PHYS (GSI_REG_BASE_PHYS + 0x00000208) +#define HWIO_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_OFFS (GSI_REG_BASE_OFFS + 0x00000208) +#define HWIO_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_RMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_ATTR 0x3 +#define HWIO_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_IN \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_ADDR, HWIO_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_RMSK) +#define HWIO_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_ADDR, m) +#define HWIO_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_OUT(v) \ + out_dword(HWIO_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_ADDR,v) +#define HWIO_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_ADDR,m,v,HWIO_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_IN) +#define HWIO_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_ADDR (GSI_REG_BASE + 0x0000020c) +#define HWIO_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_PHYS (GSI_REG_BASE_PHYS + 0x0000020c) +#define HWIO_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_OFFS (GSI_REG_BASE_OFFS + 0x0000020c) +#define HWIO_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_RMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_ATTR 0x3 +#define HWIO_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_IN \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_ADDR, HWIO_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_RMSK) +#define HWIO_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_ADDR, m) +#define HWIO_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_OUT(v) \ + out_dword(HWIO_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_ADDR,v) +#define HWIO_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_ADDR,m,v,HWIO_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_IN) +#define HWIO_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_ADDR (GSI_REG_BASE + 0x00000240) +#define HWIO_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_PHYS (GSI_REG_BASE_PHYS + 0x00000240) +#define HWIO_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_OFFS (GSI_REG_BASE_OFFS + 0x00000240) +#define HWIO_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_RMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_ATTR 0x3 +#define HWIO_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_IN \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_ADDR, HWIO_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_RMSK) +#define HWIO_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_ADDR, m) +#define HWIO_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_OUT(v) \ + out_dword(HWIO_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_ADDR,v) +#define HWIO_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_ADDR,m,v,HWIO_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_IN) +#define HWIO_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_ADDR (GSI_REG_BASE + 0x00000244) +#define HWIO_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_PHYS (GSI_REG_BASE_PHYS + 0x00000244) +#define HWIO_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_OFFS (GSI_REG_BASE_OFFS + 0x00000244) +#define HWIO_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_RMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_ATTR 0x3 +#define HWIO_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_IN \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_ADDR, HWIO_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_RMSK) +#define HWIO_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_ADDR, m) +#define HWIO_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_OUT(v) \ + out_dword(HWIO_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_ADDR,v) +#define HWIO_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_ADDR,m,v,HWIO_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_IN) +#define HWIO_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_ADDR (GSI_REG_BASE + 0x00000210) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_PHYS (GSI_REG_BASE_PHYS + 0x00000210) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_OFFS (GSI_REG_BASE_OFFS + 0x00000210) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_RMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_ATTR 0x3 +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_IN \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_ADDR, HWIO_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_RMSK) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_ADDR, m) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_OUT(v) \ + out_dword(HWIO_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_ADDR,v) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_ADDR,m,v,HWIO_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_IN) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_ADDR (GSI_REG_BASE + 0x00000214) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_PHYS (GSI_REG_BASE_PHYS + 0x00000214) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_OFFS (GSI_REG_BASE_OFFS + 0x00000214) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_RMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_ATTR 0x3 +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_IN \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_ADDR, HWIO_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_RMSK) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_ADDR, m) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_OUT(v) \ + out_dword(HWIO_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_ADDR,v) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_ADDR,m,v,HWIO_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_IN) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_ADDR (GSI_REG_BASE + 0x00000218) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_PHYS (GSI_REG_BASE_PHYS + 0x00000218) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_OFFS (GSI_REG_BASE_OFFS + 0x00000218) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_RMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_ATTR 0x3 +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_IN \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_ADDR, HWIO_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_RMSK) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_ADDR, m) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_OUT(v) \ + out_dword(HWIO_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_ADDR,v) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_ADDR,m,v,HWIO_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_IN) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_ADDR (GSI_REG_BASE + 0x0000021c) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_PHYS (GSI_REG_BASE_PHYS + 0x0000021c) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_OFFS (GSI_REG_BASE_OFFS + 0x0000021c) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_RMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_ATTR 0x3 +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_IN \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_ADDR, HWIO_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_RMSK) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_ADDR, m) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_OUT(v) \ + out_dword(HWIO_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_ADDR,v) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_ADDR,m,v,HWIO_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_IN) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_ADDR (GSI_REG_BASE + 0x00000254) +#define HWIO_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_PHYS (GSI_REG_BASE_PHYS + 0x00000254) +#define HWIO_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_OFFS (GSI_REG_BASE_OFFS + 0x00000254) +#define HWIO_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_RMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_ATTR 0x3 +#define HWIO_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_IN \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_ADDR, HWIO_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_RMSK) +#define HWIO_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_ADDR, m) +#define HWIO_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_OUT(v) \ + out_dword(HWIO_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_ADDR,v) +#define HWIO_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_ADDR,m,v,HWIO_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_IN) +#define HWIO_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_ADDR (GSI_REG_BASE + 0x00000258) +#define HWIO_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_PHYS (GSI_REG_BASE_PHYS + 0x00000258) +#define HWIO_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_OFFS (GSI_REG_BASE_OFFS + 0x00000258) +#define HWIO_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_RMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_ATTR 0x3 +#define HWIO_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_IN \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_ADDR, HWIO_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_RMSK) +#define HWIO_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_ADDR, m) +#define HWIO_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_OUT(v) \ + out_dword(HWIO_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_ADDR,v) +#define HWIO_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_ADDR,m,v,HWIO_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_IN) +#define HWIO_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_ADDR (GSI_REG_BASE + 0x0000025c) +#define HWIO_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_PHYS (GSI_REG_BASE_PHYS + 0x0000025c) +#define HWIO_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_OFFS (GSI_REG_BASE_OFFS + 0x0000025c) +#define HWIO_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_RMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_ATTR 0x3 +#define HWIO_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_IN \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_ADDR, HWIO_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_RMSK) +#define HWIO_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_ADDR, m) +#define HWIO_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_OUT(v) \ + out_dword(HWIO_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_ADDR,v) +#define HWIO_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_ADDR,m,v,HWIO_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_IN) +#define HWIO_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_ADDR (GSI_REG_BASE + 0x00000260) +#define HWIO_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_PHYS (GSI_REG_BASE_PHYS + 0x00000260) +#define HWIO_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_OFFS (GSI_REG_BASE_OFFS + 0x00000260) +#define HWIO_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_RMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_ATTR 0x3 +#define HWIO_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_IN \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_ADDR, HWIO_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_RMSK) +#define HWIO_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_ADDR, m) +#define HWIO_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_OUT(v) \ + out_dword(HWIO_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_ADDR,v) +#define HWIO_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_ADDR,m,v,HWIO_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_IN) +#define HWIO_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_ADDR (GSI_REG_BASE + 0x00000264) +#define HWIO_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_PHYS (GSI_REG_BASE_PHYS + 0x00000264) +#define HWIO_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_OFFS (GSI_REG_BASE_OFFS + 0x00000264) +#define HWIO_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_RMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_ATTR 0x3 +#define HWIO_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_IN \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_ADDR, HWIO_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_RMSK) +#define HWIO_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_ADDR, m) +#define HWIO_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_OUT(v) \ + out_dword(HWIO_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_ADDR,v) +#define HWIO_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_ADDR,m,v,HWIO_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_IN) +#define HWIO_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_ADDR (GSI_REG_BASE + 0x00000268) +#define HWIO_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_PHYS (GSI_REG_BASE_PHYS + 0x00000268) +#define HWIO_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_OFFS (GSI_REG_BASE_OFFS + 0x00000268) +#define HWIO_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_RMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_ATTR 0x3 +#define HWIO_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_IN \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_ADDR, HWIO_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_RMSK) +#define HWIO_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_ADDR, m) +#define HWIO_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_OUT(v) \ + out_dword(HWIO_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_ADDR,v) +#define HWIO_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_ADDR,m,v,HWIO_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_IN) +#define HWIO_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_IRAM_PTR_CH_CMD_ADDR (GSI_REG_BASE + 0x00000400) +#define HWIO_GSI_IRAM_PTR_CH_CMD_PHYS (GSI_REG_BASE_PHYS + 0x00000400) +#define HWIO_GSI_IRAM_PTR_CH_CMD_OFFS (GSI_REG_BASE_OFFS + 0x00000400) +#define HWIO_GSI_IRAM_PTR_CH_CMD_RMSK 0xfff +#define HWIO_GSI_IRAM_PTR_CH_CMD_ATTR 0x3 +#define HWIO_GSI_IRAM_PTR_CH_CMD_IN \ + in_dword_masked(HWIO_GSI_IRAM_PTR_CH_CMD_ADDR, HWIO_GSI_IRAM_PTR_CH_CMD_RMSK) +#define HWIO_GSI_IRAM_PTR_CH_CMD_INM(m) \ + in_dword_masked(HWIO_GSI_IRAM_PTR_CH_CMD_ADDR, m) +#define HWIO_GSI_IRAM_PTR_CH_CMD_OUT(v) \ + out_dword(HWIO_GSI_IRAM_PTR_CH_CMD_ADDR,v) +#define HWIO_GSI_IRAM_PTR_CH_CMD_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_IRAM_PTR_CH_CMD_ADDR,m,v,HWIO_GSI_IRAM_PTR_CH_CMD_IN) +#define HWIO_GSI_IRAM_PTR_CH_CMD_IRAM_PTR_BMSK 0xfff +#define HWIO_GSI_IRAM_PTR_CH_CMD_IRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_IRAM_PTR_EE_GENERIC_CMD_ADDR (GSI_REG_BASE + 0x00000404) +#define HWIO_GSI_IRAM_PTR_EE_GENERIC_CMD_PHYS (GSI_REG_BASE_PHYS + 0x00000404) +#define HWIO_GSI_IRAM_PTR_EE_GENERIC_CMD_OFFS (GSI_REG_BASE_OFFS + 0x00000404) +#define HWIO_GSI_IRAM_PTR_EE_GENERIC_CMD_RMSK 0xfff +#define HWIO_GSI_IRAM_PTR_EE_GENERIC_CMD_ATTR 0x3 +#define HWIO_GSI_IRAM_PTR_EE_GENERIC_CMD_IN \ + in_dword_masked(HWIO_GSI_IRAM_PTR_EE_GENERIC_CMD_ADDR, HWIO_GSI_IRAM_PTR_EE_GENERIC_CMD_RMSK) +#define HWIO_GSI_IRAM_PTR_EE_GENERIC_CMD_INM(m) \ + in_dword_masked(HWIO_GSI_IRAM_PTR_EE_GENERIC_CMD_ADDR, m) +#define HWIO_GSI_IRAM_PTR_EE_GENERIC_CMD_OUT(v) \ + out_dword(HWIO_GSI_IRAM_PTR_EE_GENERIC_CMD_ADDR,v) +#define HWIO_GSI_IRAM_PTR_EE_GENERIC_CMD_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_IRAM_PTR_EE_GENERIC_CMD_ADDR,m,v,HWIO_GSI_IRAM_PTR_EE_GENERIC_CMD_IN) +#define HWIO_GSI_IRAM_PTR_EE_GENERIC_CMD_IRAM_PTR_BMSK 0xfff +#define HWIO_GSI_IRAM_PTR_EE_GENERIC_CMD_IRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_IRAM_PTR_TLV_CH_NOT_FULL_ADDR (GSI_REG_BASE + 0x00000408) +#define HWIO_GSI_IRAM_PTR_TLV_CH_NOT_FULL_PHYS (GSI_REG_BASE_PHYS + 0x00000408) +#define HWIO_GSI_IRAM_PTR_TLV_CH_NOT_FULL_OFFS (GSI_REG_BASE_OFFS + 0x00000408) +#define HWIO_GSI_IRAM_PTR_TLV_CH_NOT_FULL_RMSK 0xfff +#define HWIO_GSI_IRAM_PTR_TLV_CH_NOT_FULL_ATTR 0x3 +#define HWIO_GSI_IRAM_PTR_TLV_CH_NOT_FULL_IN \ + in_dword_masked(HWIO_GSI_IRAM_PTR_TLV_CH_NOT_FULL_ADDR, HWIO_GSI_IRAM_PTR_TLV_CH_NOT_FULL_RMSK) +#define HWIO_GSI_IRAM_PTR_TLV_CH_NOT_FULL_INM(m) \ + in_dword_masked(HWIO_GSI_IRAM_PTR_TLV_CH_NOT_FULL_ADDR, m) +#define HWIO_GSI_IRAM_PTR_TLV_CH_NOT_FULL_OUT(v) \ + out_dword(HWIO_GSI_IRAM_PTR_TLV_CH_NOT_FULL_ADDR,v) +#define HWIO_GSI_IRAM_PTR_TLV_CH_NOT_FULL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_IRAM_PTR_TLV_CH_NOT_FULL_ADDR,m,v,HWIO_GSI_IRAM_PTR_TLV_CH_NOT_FULL_IN) +#define HWIO_GSI_IRAM_PTR_TLV_CH_NOT_FULL_IRAM_PTR_BMSK 0xfff +#define HWIO_GSI_IRAM_PTR_TLV_CH_NOT_FULL_IRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_IRAM_PTR_MSI_DB_ADDR (GSI_REG_BASE + 0x00000414) +#define HWIO_GSI_IRAM_PTR_MSI_DB_PHYS (GSI_REG_BASE_PHYS + 0x00000414) +#define HWIO_GSI_IRAM_PTR_MSI_DB_OFFS (GSI_REG_BASE_OFFS + 0x00000414) +#define HWIO_GSI_IRAM_PTR_MSI_DB_RMSK 0xfff +#define HWIO_GSI_IRAM_PTR_MSI_DB_ATTR 0x3 +#define HWIO_GSI_IRAM_PTR_MSI_DB_IN \ + in_dword_masked(HWIO_GSI_IRAM_PTR_MSI_DB_ADDR, HWIO_GSI_IRAM_PTR_MSI_DB_RMSK) +#define HWIO_GSI_IRAM_PTR_MSI_DB_INM(m) \ + in_dword_masked(HWIO_GSI_IRAM_PTR_MSI_DB_ADDR, m) +#define HWIO_GSI_IRAM_PTR_MSI_DB_OUT(v) \ + out_dword(HWIO_GSI_IRAM_PTR_MSI_DB_ADDR,v) +#define HWIO_GSI_IRAM_PTR_MSI_DB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_IRAM_PTR_MSI_DB_ADDR,m,v,HWIO_GSI_IRAM_PTR_MSI_DB_IN) +#define HWIO_GSI_IRAM_PTR_MSI_DB_IRAM_PTR_BMSK 0xfff +#define HWIO_GSI_IRAM_PTR_MSI_DB_IRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_IRAM_PTR_CH_DB_ADDR (GSI_REG_BASE + 0x00000418) +#define HWIO_GSI_IRAM_PTR_CH_DB_PHYS (GSI_REG_BASE_PHYS + 0x00000418) +#define HWIO_GSI_IRAM_PTR_CH_DB_OFFS (GSI_REG_BASE_OFFS + 0x00000418) +#define HWIO_GSI_IRAM_PTR_CH_DB_RMSK 0xfff +#define HWIO_GSI_IRAM_PTR_CH_DB_ATTR 0x3 +#define HWIO_GSI_IRAM_PTR_CH_DB_IN \ + in_dword_masked(HWIO_GSI_IRAM_PTR_CH_DB_ADDR, HWIO_GSI_IRAM_PTR_CH_DB_RMSK) +#define HWIO_GSI_IRAM_PTR_CH_DB_INM(m) \ + in_dword_masked(HWIO_GSI_IRAM_PTR_CH_DB_ADDR, m) +#define HWIO_GSI_IRAM_PTR_CH_DB_OUT(v) \ + out_dword(HWIO_GSI_IRAM_PTR_CH_DB_ADDR,v) +#define HWIO_GSI_IRAM_PTR_CH_DB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_IRAM_PTR_CH_DB_ADDR,m,v,HWIO_GSI_IRAM_PTR_CH_DB_IN) +#define HWIO_GSI_IRAM_PTR_CH_DB_IRAM_PTR_BMSK 0xfff +#define HWIO_GSI_IRAM_PTR_CH_DB_IRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_IRAM_PTR_EV_DB_ADDR (GSI_REG_BASE + 0x0000041c) +#define HWIO_GSI_IRAM_PTR_EV_DB_PHYS (GSI_REG_BASE_PHYS + 0x0000041c) +#define HWIO_GSI_IRAM_PTR_EV_DB_OFFS (GSI_REG_BASE_OFFS + 0x0000041c) +#define HWIO_GSI_IRAM_PTR_EV_DB_RMSK 0xfff +#define HWIO_GSI_IRAM_PTR_EV_DB_ATTR 0x3 +#define HWIO_GSI_IRAM_PTR_EV_DB_IN \ + in_dword_masked(HWIO_GSI_IRAM_PTR_EV_DB_ADDR, HWIO_GSI_IRAM_PTR_EV_DB_RMSK) +#define HWIO_GSI_IRAM_PTR_EV_DB_INM(m) \ + in_dword_masked(HWIO_GSI_IRAM_PTR_EV_DB_ADDR, m) +#define HWIO_GSI_IRAM_PTR_EV_DB_OUT(v) \ + out_dword(HWIO_GSI_IRAM_PTR_EV_DB_ADDR,v) +#define HWIO_GSI_IRAM_PTR_EV_DB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_IRAM_PTR_EV_DB_ADDR,m,v,HWIO_GSI_IRAM_PTR_EV_DB_IN) +#define HWIO_GSI_IRAM_PTR_EV_DB_IRAM_PTR_BMSK 0xfff +#define HWIO_GSI_IRAM_PTR_EV_DB_IRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_IRAM_PTR_NEW_RE_ADDR (GSI_REG_BASE + 0x00000420) +#define HWIO_GSI_IRAM_PTR_NEW_RE_PHYS (GSI_REG_BASE_PHYS + 0x00000420) +#define HWIO_GSI_IRAM_PTR_NEW_RE_OFFS (GSI_REG_BASE_OFFS + 0x00000420) +#define HWIO_GSI_IRAM_PTR_NEW_RE_RMSK 0xfff +#define HWIO_GSI_IRAM_PTR_NEW_RE_ATTR 0x3 +#define HWIO_GSI_IRAM_PTR_NEW_RE_IN \ + in_dword_masked(HWIO_GSI_IRAM_PTR_NEW_RE_ADDR, HWIO_GSI_IRAM_PTR_NEW_RE_RMSK) +#define HWIO_GSI_IRAM_PTR_NEW_RE_INM(m) \ + in_dword_masked(HWIO_GSI_IRAM_PTR_NEW_RE_ADDR, m) +#define HWIO_GSI_IRAM_PTR_NEW_RE_OUT(v) \ + out_dword(HWIO_GSI_IRAM_PTR_NEW_RE_ADDR,v) +#define HWIO_GSI_IRAM_PTR_NEW_RE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_IRAM_PTR_NEW_RE_ADDR,m,v,HWIO_GSI_IRAM_PTR_NEW_RE_IN) +#define HWIO_GSI_IRAM_PTR_NEW_RE_IRAM_PTR_BMSK 0xfff +#define HWIO_GSI_IRAM_PTR_NEW_RE_IRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_IRAM_PTR_CH_DIS_COMP_ADDR (GSI_REG_BASE + 0x00000424) +#define HWIO_GSI_IRAM_PTR_CH_DIS_COMP_PHYS (GSI_REG_BASE_PHYS + 0x00000424) +#define HWIO_GSI_IRAM_PTR_CH_DIS_COMP_OFFS (GSI_REG_BASE_OFFS + 0x00000424) +#define HWIO_GSI_IRAM_PTR_CH_DIS_COMP_RMSK 0xfff +#define HWIO_GSI_IRAM_PTR_CH_DIS_COMP_ATTR 0x3 +#define HWIO_GSI_IRAM_PTR_CH_DIS_COMP_IN \ + in_dword_masked(HWIO_GSI_IRAM_PTR_CH_DIS_COMP_ADDR, HWIO_GSI_IRAM_PTR_CH_DIS_COMP_RMSK) +#define HWIO_GSI_IRAM_PTR_CH_DIS_COMP_INM(m) \ + in_dword_masked(HWIO_GSI_IRAM_PTR_CH_DIS_COMP_ADDR, m) +#define HWIO_GSI_IRAM_PTR_CH_DIS_COMP_OUT(v) \ + out_dword(HWIO_GSI_IRAM_PTR_CH_DIS_COMP_ADDR,v) +#define HWIO_GSI_IRAM_PTR_CH_DIS_COMP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_IRAM_PTR_CH_DIS_COMP_ADDR,m,v,HWIO_GSI_IRAM_PTR_CH_DIS_COMP_IN) +#define HWIO_GSI_IRAM_PTR_CH_DIS_COMP_IRAM_PTR_BMSK 0xfff +#define HWIO_GSI_IRAM_PTR_CH_DIS_COMP_IRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_IRAM_PTR_CH_EMPTY_ADDR (GSI_REG_BASE + 0x00000428) +#define HWIO_GSI_IRAM_PTR_CH_EMPTY_PHYS (GSI_REG_BASE_PHYS + 0x00000428) +#define HWIO_GSI_IRAM_PTR_CH_EMPTY_OFFS (GSI_REG_BASE_OFFS + 0x00000428) +#define HWIO_GSI_IRAM_PTR_CH_EMPTY_RMSK 0xfff +#define HWIO_GSI_IRAM_PTR_CH_EMPTY_ATTR 0x3 +#define HWIO_GSI_IRAM_PTR_CH_EMPTY_IN \ + in_dword_masked(HWIO_GSI_IRAM_PTR_CH_EMPTY_ADDR, HWIO_GSI_IRAM_PTR_CH_EMPTY_RMSK) +#define HWIO_GSI_IRAM_PTR_CH_EMPTY_INM(m) \ + in_dword_masked(HWIO_GSI_IRAM_PTR_CH_EMPTY_ADDR, m) +#define HWIO_GSI_IRAM_PTR_CH_EMPTY_OUT(v) \ + out_dword(HWIO_GSI_IRAM_PTR_CH_EMPTY_ADDR,v) +#define HWIO_GSI_IRAM_PTR_CH_EMPTY_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_IRAM_PTR_CH_EMPTY_ADDR,m,v,HWIO_GSI_IRAM_PTR_CH_EMPTY_IN) +#define HWIO_GSI_IRAM_PTR_CH_EMPTY_IRAM_PTR_BMSK 0xfff +#define HWIO_GSI_IRAM_PTR_CH_EMPTY_IRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_IRAM_PTR_EVENT_GEN_COMP_ADDR (GSI_REG_BASE + 0x0000042c) +#define HWIO_GSI_IRAM_PTR_EVENT_GEN_COMP_PHYS (GSI_REG_BASE_PHYS + 0x0000042c) +#define HWIO_GSI_IRAM_PTR_EVENT_GEN_COMP_OFFS (GSI_REG_BASE_OFFS + 0x0000042c) +#define HWIO_GSI_IRAM_PTR_EVENT_GEN_COMP_RMSK 0xfff +#define HWIO_GSI_IRAM_PTR_EVENT_GEN_COMP_ATTR 0x3 +#define HWIO_GSI_IRAM_PTR_EVENT_GEN_COMP_IN \ + in_dword_masked(HWIO_GSI_IRAM_PTR_EVENT_GEN_COMP_ADDR, HWIO_GSI_IRAM_PTR_EVENT_GEN_COMP_RMSK) +#define HWIO_GSI_IRAM_PTR_EVENT_GEN_COMP_INM(m) \ + in_dword_masked(HWIO_GSI_IRAM_PTR_EVENT_GEN_COMP_ADDR, m) +#define HWIO_GSI_IRAM_PTR_EVENT_GEN_COMP_OUT(v) \ + out_dword(HWIO_GSI_IRAM_PTR_EVENT_GEN_COMP_ADDR,v) +#define HWIO_GSI_IRAM_PTR_EVENT_GEN_COMP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_IRAM_PTR_EVENT_GEN_COMP_ADDR,m,v,HWIO_GSI_IRAM_PTR_EVENT_GEN_COMP_IN) +#define HWIO_GSI_IRAM_PTR_EVENT_GEN_COMP_IRAM_PTR_BMSK 0xfff +#define HWIO_GSI_IRAM_PTR_EVENT_GEN_COMP_IRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_ADDR (GSI_REG_BASE + 0x00000430) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_PHYS (GSI_REG_BASE_PHYS + 0x00000430) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_OFFS (GSI_REG_BASE_OFFS + 0x00000430) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_RMSK 0xfff +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_ATTR 0x3 +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_IN \ + in_dword_masked(HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_ADDR, HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_RMSK) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_INM(m) \ + in_dword_masked(HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_ADDR, m) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_OUT(v) \ + out_dword(HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_ADDR,v) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_ADDR,m,v,HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_IN) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_IRAM_PTR_BMSK 0xfff +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_IRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_ADDR (GSI_REG_BASE + 0x00000434) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_PHYS (GSI_REG_BASE_PHYS + 0x00000434) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_OFFS (GSI_REG_BASE_OFFS + 0x00000434) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_RMSK 0xfff +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_ATTR 0x3 +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_IN \ + in_dword_masked(HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_ADDR, HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_RMSK) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_INM(m) \ + in_dword_masked(HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_ADDR, m) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_OUT(v) \ + out_dword(HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_ADDR,v) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_ADDR,m,v,HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_IN) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_IRAM_PTR_BMSK 0xfff +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_IRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_ADDR (GSI_REG_BASE + 0x00000438) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_PHYS (GSI_REG_BASE_PHYS + 0x00000438) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_OFFS (GSI_REG_BASE_OFFS + 0x00000438) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_RMSK 0xfff +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_ATTR 0x3 +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_IN \ + in_dword_masked(HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_ADDR, HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_RMSK) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_INM(m) \ + in_dword_masked(HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_ADDR, m) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_OUT(v) \ + out_dword(HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_ADDR,v) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_ADDR,m,v,HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_IN) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_IRAM_PTR_BMSK 0xfff +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_IRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_IRAM_PTR_TIMER_EXPIRED_ADDR (GSI_REG_BASE + 0x0000043c) +#define HWIO_GSI_IRAM_PTR_TIMER_EXPIRED_PHYS (GSI_REG_BASE_PHYS + 0x0000043c) +#define HWIO_GSI_IRAM_PTR_TIMER_EXPIRED_OFFS (GSI_REG_BASE_OFFS + 0x0000043c) +#define HWIO_GSI_IRAM_PTR_TIMER_EXPIRED_RMSK 0xfff +#define HWIO_GSI_IRAM_PTR_TIMER_EXPIRED_ATTR 0x3 +#define HWIO_GSI_IRAM_PTR_TIMER_EXPIRED_IN \ + in_dword_masked(HWIO_GSI_IRAM_PTR_TIMER_EXPIRED_ADDR, HWIO_GSI_IRAM_PTR_TIMER_EXPIRED_RMSK) +#define HWIO_GSI_IRAM_PTR_TIMER_EXPIRED_INM(m) \ + in_dword_masked(HWIO_GSI_IRAM_PTR_TIMER_EXPIRED_ADDR, m) +#define HWIO_GSI_IRAM_PTR_TIMER_EXPIRED_OUT(v) \ + out_dword(HWIO_GSI_IRAM_PTR_TIMER_EXPIRED_ADDR,v) +#define HWIO_GSI_IRAM_PTR_TIMER_EXPIRED_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_IRAM_PTR_TIMER_EXPIRED_ADDR,m,v,HWIO_GSI_IRAM_PTR_TIMER_EXPIRED_IN) +#define HWIO_GSI_IRAM_PTR_TIMER_EXPIRED_IRAM_PTR_BMSK 0xfff +#define HWIO_GSI_IRAM_PTR_TIMER_EXPIRED_IRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_IRAM_PTR_WRITE_ENG_COMP_ADDR (GSI_REG_BASE + 0x00000440) +#define HWIO_GSI_IRAM_PTR_WRITE_ENG_COMP_PHYS (GSI_REG_BASE_PHYS + 0x00000440) +#define HWIO_GSI_IRAM_PTR_WRITE_ENG_COMP_OFFS (GSI_REG_BASE_OFFS + 0x00000440) +#define HWIO_GSI_IRAM_PTR_WRITE_ENG_COMP_RMSK 0xfff +#define HWIO_GSI_IRAM_PTR_WRITE_ENG_COMP_ATTR 0x3 +#define HWIO_GSI_IRAM_PTR_WRITE_ENG_COMP_IN \ + in_dword_masked(HWIO_GSI_IRAM_PTR_WRITE_ENG_COMP_ADDR, HWIO_GSI_IRAM_PTR_WRITE_ENG_COMP_RMSK) +#define HWIO_GSI_IRAM_PTR_WRITE_ENG_COMP_INM(m) \ + in_dword_masked(HWIO_GSI_IRAM_PTR_WRITE_ENG_COMP_ADDR, m) +#define HWIO_GSI_IRAM_PTR_WRITE_ENG_COMP_OUT(v) \ + out_dword(HWIO_GSI_IRAM_PTR_WRITE_ENG_COMP_ADDR,v) +#define HWIO_GSI_IRAM_PTR_WRITE_ENG_COMP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_IRAM_PTR_WRITE_ENG_COMP_ADDR,m,v,HWIO_GSI_IRAM_PTR_WRITE_ENG_COMP_IN) +#define HWIO_GSI_IRAM_PTR_WRITE_ENG_COMP_IRAM_PTR_BMSK 0xfff +#define HWIO_GSI_IRAM_PTR_WRITE_ENG_COMP_IRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_IRAM_PTR_READ_ENG_COMP_ADDR (GSI_REG_BASE + 0x00000444) +#define HWIO_GSI_IRAM_PTR_READ_ENG_COMP_PHYS (GSI_REG_BASE_PHYS + 0x00000444) +#define HWIO_GSI_IRAM_PTR_READ_ENG_COMP_OFFS (GSI_REG_BASE_OFFS + 0x00000444) +#define HWIO_GSI_IRAM_PTR_READ_ENG_COMP_RMSK 0xfff +#define HWIO_GSI_IRAM_PTR_READ_ENG_COMP_ATTR 0x3 +#define HWIO_GSI_IRAM_PTR_READ_ENG_COMP_IN \ + in_dword_masked(HWIO_GSI_IRAM_PTR_READ_ENG_COMP_ADDR, HWIO_GSI_IRAM_PTR_READ_ENG_COMP_RMSK) +#define HWIO_GSI_IRAM_PTR_READ_ENG_COMP_INM(m) \ + in_dword_masked(HWIO_GSI_IRAM_PTR_READ_ENG_COMP_ADDR, m) +#define HWIO_GSI_IRAM_PTR_READ_ENG_COMP_OUT(v) \ + out_dword(HWIO_GSI_IRAM_PTR_READ_ENG_COMP_ADDR,v) +#define HWIO_GSI_IRAM_PTR_READ_ENG_COMP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_IRAM_PTR_READ_ENG_COMP_ADDR,m,v,HWIO_GSI_IRAM_PTR_READ_ENG_COMP_IN) +#define HWIO_GSI_IRAM_PTR_READ_ENG_COMP_IRAM_PTR_BMSK 0xfff +#define HWIO_GSI_IRAM_PTR_READ_ENG_COMP_IRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_IRAM_PTR_UC_GP_INT_ADDR (GSI_REG_BASE + 0x00000448) +#define HWIO_GSI_IRAM_PTR_UC_GP_INT_PHYS (GSI_REG_BASE_PHYS + 0x00000448) +#define HWIO_GSI_IRAM_PTR_UC_GP_INT_OFFS (GSI_REG_BASE_OFFS + 0x00000448) +#define HWIO_GSI_IRAM_PTR_UC_GP_INT_RMSK 0xfff +#define HWIO_GSI_IRAM_PTR_UC_GP_INT_ATTR 0x3 +#define HWIO_GSI_IRAM_PTR_UC_GP_INT_IN \ + in_dword_masked(HWIO_GSI_IRAM_PTR_UC_GP_INT_ADDR, HWIO_GSI_IRAM_PTR_UC_GP_INT_RMSK) +#define HWIO_GSI_IRAM_PTR_UC_GP_INT_INM(m) \ + in_dword_masked(HWIO_GSI_IRAM_PTR_UC_GP_INT_ADDR, m) +#define HWIO_GSI_IRAM_PTR_UC_GP_INT_OUT(v) \ + out_dword(HWIO_GSI_IRAM_PTR_UC_GP_INT_ADDR,v) +#define HWIO_GSI_IRAM_PTR_UC_GP_INT_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_IRAM_PTR_UC_GP_INT_ADDR,m,v,HWIO_GSI_IRAM_PTR_UC_GP_INT_IN) +#define HWIO_GSI_IRAM_PTR_UC_GP_INT_IRAM_PTR_BMSK 0xfff +#define HWIO_GSI_IRAM_PTR_UC_GP_INT_IRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_IRAM_PTR_INT_MOD_STOPED_ADDR (GSI_REG_BASE + 0x0000044c) +#define HWIO_GSI_IRAM_PTR_INT_MOD_STOPED_PHYS (GSI_REG_BASE_PHYS + 0x0000044c) +#define HWIO_GSI_IRAM_PTR_INT_MOD_STOPED_OFFS (GSI_REG_BASE_OFFS + 0x0000044c) +#define HWIO_GSI_IRAM_PTR_INT_MOD_STOPED_RMSK 0xfff +#define HWIO_GSI_IRAM_PTR_INT_MOD_STOPED_ATTR 0x3 +#define HWIO_GSI_IRAM_PTR_INT_MOD_STOPED_IN \ + in_dword_masked(HWIO_GSI_IRAM_PTR_INT_MOD_STOPED_ADDR, HWIO_GSI_IRAM_PTR_INT_MOD_STOPED_RMSK) +#define HWIO_GSI_IRAM_PTR_INT_MOD_STOPED_INM(m) \ + in_dword_masked(HWIO_GSI_IRAM_PTR_INT_MOD_STOPED_ADDR, m) +#define HWIO_GSI_IRAM_PTR_INT_MOD_STOPED_OUT(v) \ + out_dword(HWIO_GSI_IRAM_PTR_INT_MOD_STOPED_ADDR,v) +#define HWIO_GSI_IRAM_PTR_INT_MOD_STOPED_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_IRAM_PTR_INT_MOD_STOPED_ADDR,m,v,HWIO_GSI_IRAM_PTR_INT_MOD_STOPED_IN) +#define HWIO_GSI_IRAM_PTR_INT_MOD_STOPED_IRAM_PTR_BMSK 0xfff +#define HWIO_GSI_IRAM_PTR_INT_MOD_STOPED_IRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_IRAM_PTR_INT_NOTIFY_MCS_ADDR (GSI_REG_BASE + 0x00000470) +#define HWIO_GSI_IRAM_PTR_INT_NOTIFY_MCS_PHYS (GSI_REG_BASE_PHYS + 0x00000470) +#define HWIO_GSI_IRAM_PTR_INT_NOTIFY_MCS_OFFS (GSI_REG_BASE_OFFS + 0x00000470) +#define HWIO_GSI_IRAM_PTR_INT_NOTIFY_MCS_RMSK 0xfff +#define HWIO_GSI_IRAM_PTR_INT_NOTIFY_MCS_ATTR 0x3 +#define HWIO_GSI_IRAM_PTR_INT_NOTIFY_MCS_IN \ + in_dword_masked(HWIO_GSI_IRAM_PTR_INT_NOTIFY_MCS_ADDR, HWIO_GSI_IRAM_PTR_INT_NOTIFY_MCS_RMSK) +#define HWIO_GSI_IRAM_PTR_INT_NOTIFY_MCS_INM(m) \ + in_dword_masked(HWIO_GSI_IRAM_PTR_INT_NOTIFY_MCS_ADDR, m) +#define HWIO_GSI_IRAM_PTR_INT_NOTIFY_MCS_OUT(v) \ + out_dword(HWIO_GSI_IRAM_PTR_INT_NOTIFY_MCS_ADDR,v) +#define HWIO_GSI_IRAM_PTR_INT_NOTIFY_MCS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_IRAM_PTR_INT_NOTIFY_MCS_ADDR,m,v,HWIO_GSI_IRAM_PTR_INT_NOTIFY_MCS_IN) +#define HWIO_GSI_IRAM_PTR_INT_NOTIFY_MCS_IRAM_PTR_BMSK 0xfff +#define HWIO_GSI_IRAM_PTR_INT_NOTIFY_MCS_IRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_INST_RAM_n_ADDR(n) (GSI_REG_BASE + 0x000a4000 + 0x4 * (n)) +#define HWIO_GSI_INST_RAM_n_PHYS(n) (GSI_REG_BASE_PHYS + 0x000a4000 + 0x4 * (n)) +#define HWIO_GSI_INST_RAM_n_OFFS(n) (GSI_REG_BASE_OFFS + 0x000a4000 + 0x4 * (n)) +#define HWIO_GSI_INST_RAM_n_RMSK 0xffffffff +#define HWIO_GSI_INST_RAM_n_MAXn 8255 +#define HWIO_GSI_INST_RAM_n_ATTR 0x3 +#define HWIO_GSI_INST_RAM_n_INI(n) \ + in_dword_masked(HWIO_GSI_INST_RAM_n_ADDR(n), HWIO_GSI_INST_RAM_n_RMSK) +#define HWIO_GSI_INST_RAM_n_INMI(n,mask) \ + in_dword_masked(HWIO_GSI_INST_RAM_n_ADDR(n), mask) +#define HWIO_GSI_INST_RAM_n_OUTI(n,val) \ + out_dword(HWIO_GSI_INST_RAM_n_ADDR(n),val) +#define HWIO_GSI_INST_RAM_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_GSI_INST_RAM_n_ADDR(n),mask,val,HWIO_GSI_INST_RAM_n_INI(n)) +#define HWIO_GSI_INST_RAM_n_INST_BYTE_3_BMSK 0xff000000 +#define HWIO_GSI_INST_RAM_n_INST_BYTE_3_SHFT 0x18 +#define HWIO_GSI_INST_RAM_n_INST_BYTE_2_BMSK 0xff0000 +#define HWIO_GSI_INST_RAM_n_INST_BYTE_2_SHFT 0x10 +#define HWIO_GSI_INST_RAM_n_INST_BYTE_1_BMSK 0xff00 +#define HWIO_GSI_INST_RAM_n_INST_BYTE_1_SHFT 0x8 +#define HWIO_GSI_INST_RAM_n_INST_BYTE_0_BMSK 0xff +#define HWIO_GSI_INST_RAM_n_INST_BYTE_0_SHFT 0x0 + +#define HWIO_GSI_SHRAM_n_ADDR(n) (GSI_REG_BASE + 0x00002000 + 0x4 * (n)) +#define HWIO_GSI_SHRAM_n_PHYS(n) (GSI_REG_BASE_PHYS + 0x00002000 + 0x4 * (n)) +#define HWIO_GSI_SHRAM_n_OFFS(n) (GSI_REG_BASE_OFFS + 0x00002000 + 0x4 * (n)) +#define HWIO_GSI_SHRAM_n_RMSK 0xffffffff +#define HWIO_GSI_SHRAM_n_MAXn 2047 +#define HWIO_GSI_SHRAM_n_ATTR 0x3 +#define HWIO_GSI_SHRAM_n_INI(n) \ + in_dword_masked(HWIO_GSI_SHRAM_n_ADDR(n), HWIO_GSI_SHRAM_n_RMSK, HWIO_GSI_SHRAM_n_ATTR) +#define HWIO_GSI_SHRAM_n_INMI(n,mask) \ + in_dword_masked(HWIO_GSI_SHRAM_n_ADDR(n), mask, HWIO_GSI_SHRAM_n_ATTR) +#define HWIO_GSI_SHRAM_n_OUTI(n,val) \ + out_dword(HWIO_GSI_SHRAM_n_ADDR(n),val, HWIO_GSI_SHRAM_n_ATTR) +#define HWIO_GSI_SHRAM_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_GSI_SHRAM_n_ADDR(n),mask,val,HWIO_GSI_SHRAM_n_INI(n)) +#define HWIO_GSI_SHRAM_n_SHRAM_BMSK 0xffffffff +#define HWIO_GSI_SHRAM_n_SHRAM_SHFT 0x0 + +#define HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_ADDR(n,k) (GSI_REG_BASE + 0x00009000 + 0x400 * (n) + 0x4 * (k)) +#define HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x00009000 + 0x400 * (n) + 0x4 * (k)) +#define HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x00009000 + 0x400 * (n) + 0x4 * (k)) +#define HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_RMSK 0x1ff +#define HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_MAXn 2 +#define HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_MAXk 27 +#define HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_ATTR 0x3 +#define HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_INI2(n,k) \ + in_dword_masked(HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_ADDR(n,k), HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_RMSK) +#define HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_INMI2(n,k,mask) \ + in_dword_masked(HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_ADDR(n,k), mask) +#define HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_OUTI2(n,k,val) \ + out_dword(HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_ADDR(n,k),val) +#define HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_ADDR(n,k),mask,val,HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_INI2(n,k)) +#define HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_VALID_BMSK 0x100 +#define HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_VALID_SHFT 0x8 +#define HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_PHY_CH_BMSK 0xff +#define HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_PHY_CH_SHFT 0x0 + +#define HWIO_GSI_TEST_BUS_SEL_ADDR (GSI_REG_BASE + 0x00001000) +#define HWIO_GSI_TEST_BUS_SEL_PHYS (GSI_REG_BASE_PHYS + 0x00001000) +#define HWIO_GSI_TEST_BUS_SEL_OFFS (GSI_REG_BASE_OFFS + 0x00001000) +#define HWIO_GSI_TEST_BUS_SEL_RMSK 0xf00ff +#define HWIO_GSI_TEST_BUS_SEL_ATTR 0x3 +#define HWIO_GSI_TEST_BUS_SEL_IN \ + in_dword_masked(HWIO_GSI_TEST_BUS_SEL_ADDR, HWIO_GSI_TEST_BUS_SEL_RMSK, HWIO_GSI_TEST_BUS_SEL_ATTR) +#define HWIO_GSI_TEST_BUS_SEL_INM(m) \ + in_dword_masked(HWIO_GSI_TEST_BUS_SEL_ADDR, m, HWIO_GSI_TEST_BUS_SEL_ATTR) +#define HWIO_GSI_TEST_BUS_SEL_OUT(v) \ + out_dword(HWIO_GSI_TEST_BUS_SEL_ADDR,v, HWIO_GSI_TEST_BUS_SEL_ATTR) +#define HWIO_GSI_TEST_BUS_SEL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_TEST_BUS_SEL_ADDR,m,v,HWIO_GSI_TEST_BUS_SEL_IN) +#define HWIO_GSI_TEST_BUS_SEL_GSI_HW_EVENTS_SEL_BMSK 0xf0000 +#define HWIO_GSI_TEST_BUS_SEL_GSI_HW_EVENTS_SEL_SHFT 0x10 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_BMSK 0xff +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_SHFT 0x0 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_ZEROS_FVAL 0x0 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MCS_0_FVAL 0x1 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MCS_1_FVAL 0x2 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MCS_2_FVAL 0x3 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MCS_3_FVAL 0x4 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MCS_4_FVAL 0x5 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_DB_ENG_FVAL 0x9 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_0_FVAL 0xb +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_1_FVAL 0xc +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_2_FVAL 0xd +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_3_FVAL 0xe +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_4_FVAL 0xf +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_5_FVAL 0x10 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_6_FVAL 0x11 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_7_FVAL 0x12 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_EVE_0_FVAL 0x13 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_EVE_1_FVAL 0x14 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_EVE_2_FVAL 0x15 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_EVE_3_FVAL 0x16 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_EVE_4_FVAL 0x17 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_EVE_5_FVAL 0x18 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IE_0_FVAL 0x1b +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IE_1_FVAL 0x1c +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IE_2_FVAL 0x1d +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IC_0_FVAL 0x1f +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IC_1_FVAL 0x20 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IC_2_FVAL 0x21 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IC_3_FVAL 0x22 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IC_4_FVAL 0x23 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MOQA_0_FVAL 0x27 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MOQA_1_FVAL 0x28 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MOQA_2_FVAL 0x29 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MOQA_3_FVAL 0x2a +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_TMR_0_FVAL 0x2b +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_TMR_1_FVAL 0x2c +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_TMR_2_FVAL 0x2d +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_TMR_3_FVAL 0x2e +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_RD_WR_0_FVAL 0x33 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_RD_WR_1_FVAL 0x34 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_RD_WR_2_FVAL 0x35 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_RD_WR_3_FVAL 0x36 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_CSR_FVAL 0x3a +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_SDMA_0_FVAL 0x3c +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_SMDA_1_FVAL 0x3d +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_CSR_1_FVAL 0x3e +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_CSR_2_FVAL 0x3f +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MCS_5_FVAL 0x40 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IC_5_FVAL 0x41 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_CSR_3_FVAL 0x42 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_TLV_0_FVAL 0x43 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_8_FVAL 0x44 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IE_NOTIFY_FVAL 0x45 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_DB_MSI_FVAL 0x46 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_9_FVAL 0x47 + +#define HWIO_GSI_TEST_BUS_REG_ADDR (GSI_REG_BASE + 0x00001008) +#define HWIO_GSI_TEST_BUS_REG_PHYS (GSI_REG_BASE_PHYS + 0x00001008) +#define HWIO_GSI_TEST_BUS_REG_OFFS (GSI_REG_BASE_OFFS + 0x00001008) +#define HWIO_GSI_TEST_BUS_REG_RMSK 0xffffffff +#define HWIO_GSI_TEST_BUS_REG_ATTR 0x1 +#define HWIO_GSI_TEST_BUS_REG_IN \ + in_dword_masked(HWIO_GSI_TEST_BUS_REG_ADDR, HWIO_GSI_TEST_BUS_REG_RMSK, HWIO_GSI_TEST_BUS_REG_ATTR) +#define HWIO_GSI_TEST_BUS_REG_INM(m) \ + in_dword_masked(HWIO_GSI_TEST_BUS_REG_ADDR, m, HWIO_GSI_TEST_BUS_REG_ATTR) +#define HWIO_GSI_TEST_BUS_REG_GSI_TESTBUS_REG_BMSK 0xffffffff +#define HWIO_GSI_TEST_BUS_REG_GSI_TESTBUS_REG_SHFT 0x0 + +#define HWIO_GSI_DEBUG_BUSY_REG_ADDR (GSI_REG_BASE + 0x00001010) +#define HWIO_GSI_DEBUG_BUSY_REG_PHYS (GSI_REG_BASE_PHYS + 0x00001010) +#define HWIO_GSI_DEBUG_BUSY_REG_OFFS (GSI_REG_BASE_OFFS + 0x00001010) +#define HWIO_GSI_DEBUG_BUSY_REG_RMSK 0x1fff +#define HWIO_GSI_DEBUG_BUSY_REG_ATTR 0x1 +#define HWIO_GSI_DEBUG_BUSY_REG_IN \ + in_dword_masked(HWIO_GSI_DEBUG_BUSY_REG_ADDR, HWIO_GSI_DEBUG_BUSY_REG_RMSK) +#define HWIO_GSI_DEBUG_BUSY_REG_INM(m) \ + in_dword_masked(HWIO_GSI_DEBUG_BUSY_REG_ADDR, m) +#define HWIO_GSI_DEBUG_BUSY_REG_SDMA_BUSY_BMSK 0x1000 +#define HWIO_GSI_DEBUG_BUSY_REG_SDMA_BUSY_SHFT 0xc +#define HWIO_GSI_DEBUG_BUSY_REG_IC_BUSY_BMSK 0x800 +#define HWIO_GSI_DEBUG_BUSY_REG_IC_BUSY_SHFT 0xb +#define HWIO_GSI_DEBUG_BUSY_REG_UC_BUSY_BMSK 0x400 +#define HWIO_GSI_DEBUG_BUSY_REG_UC_BUSY_SHFT 0xa +#define HWIO_GSI_DEBUG_BUSY_REG_DBG_CNT_BUSY_BMSK 0x200 +#define HWIO_GSI_DEBUG_BUSY_REG_DBG_CNT_BUSY_SHFT 0x9 +#define HWIO_GSI_DEBUG_BUSY_REG_DB_ENG_BUSY_BMSK 0x100 +#define HWIO_GSI_DEBUG_BUSY_REG_DB_ENG_BUSY_SHFT 0x8 +#define HWIO_GSI_DEBUG_BUSY_REG_REE_PWR_CLPS_BUSY_BMSK 0x80 +#define HWIO_GSI_DEBUG_BUSY_REG_REE_PWR_CLPS_BUSY_SHFT 0x7 +#define HWIO_GSI_DEBUG_BUSY_REG_INT_ENG_BUSY_BMSK 0x40 +#define HWIO_GSI_DEBUG_BUSY_REG_INT_ENG_BUSY_SHFT 0x6 +#define HWIO_GSI_DEBUG_BUSY_REG_EV_ENG_BUSY_BMSK 0x20 +#define HWIO_GSI_DEBUG_BUSY_REG_EV_ENG_BUSY_SHFT 0x5 +#define HWIO_GSI_DEBUG_BUSY_REG_RD_WR_BUSY_BMSK 0x10 +#define HWIO_GSI_DEBUG_BUSY_REG_RD_WR_BUSY_SHFT 0x4 +#define HWIO_GSI_DEBUG_BUSY_REG_TIMER_BUSY_BMSK 0x8 +#define HWIO_GSI_DEBUG_BUSY_REG_TIMER_BUSY_SHFT 0x3 +#define HWIO_GSI_DEBUG_BUSY_REG_MCS_BUSY_BMSK 0x4 +#define HWIO_GSI_DEBUG_BUSY_REG_MCS_BUSY_SHFT 0x2 +#define HWIO_GSI_DEBUG_BUSY_REG_REE_BUSY_BMSK 0x2 +#define HWIO_GSI_DEBUG_BUSY_REG_REE_BUSY_SHFT 0x1 +#define HWIO_GSI_DEBUG_BUSY_REG_CSR_BUSY_BMSK 0x1 +#define HWIO_GSI_DEBUG_BUSY_REG_CSR_BUSY_SHFT 0x0 + +#define HWIO_GSI_DEBUG_EVENT_PENDING_k_ADDR(k) (GSI_REG_BASE + 0x00001a80 + 0x4 * (k)) +#define HWIO_GSI_DEBUG_EVENT_PENDING_k_PHYS(k) (GSI_REG_BASE_PHYS + 0x00001a80 + 0x4 * (k)) +#define HWIO_GSI_DEBUG_EVENT_PENDING_k_OFFS(k) (GSI_REG_BASE_OFFS + 0x00001a80 + 0x4 * (k)) +#define HWIO_GSI_DEBUG_EVENT_PENDING_k_RMSK 0xffffffff +#define HWIO_GSI_DEBUG_EVENT_PENDING_k_MAXk 1 +#define HWIO_GSI_DEBUG_EVENT_PENDING_k_ATTR 0x1 +#define HWIO_GSI_DEBUG_EVENT_PENDING_k_INI(k) \ + in_dword_masked(HWIO_GSI_DEBUG_EVENT_PENDING_k_ADDR(k), HWIO_GSI_DEBUG_EVENT_PENDING_k_RMSK) +#define HWIO_GSI_DEBUG_EVENT_PENDING_k_INMI(k,mask) \ + in_dword_masked(HWIO_GSI_DEBUG_EVENT_PENDING_k_ADDR(k), mask) +#define HWIO_GSI_DEBUG_EVENT_PENDING_k_CHID_BIT_MAP_BMSK 0xffffffff +#define HWIO_GSI_DEBUG_EVENT_PENDING_k_CHID_BIT_MAP_SHFT 0x0 + +#define HWIO_GSI_DEBUG_TIMER_PENDING_k_ADDR(k) (GSI_REG_BASE + 0x00001aa0 + 0x4 * (k)) +#define HWIO_GSI_DEBUG_TIMER_PENDING_k_PHYS(k) (GSI_REG_BASE_PHYS + 0x00001aa0 + 0x4 * (k)) +#define HWIO_GSI_DEBUG_TIMER_PENDING_k_OFFS(k) (GSI_REG_BASE_OFFS + 0x00001aa0 + 0x4 * (k)) +#define HWIO_GSI_DEBUG_TIMER_PENDING_k_RMSK 0xffffffff +#define HWIO_GSI_DEBUG_TIMER_PENDING_k_MAXk 1 +#define HWIO_GSI_DEBUG_TIMER_PENDING_k_ATTR 0x1 +#define HWIO_GSI_DEBUG_TIMER_PENDING_k_INI(k) \ + in_dword_masked(HWIO_GSI_DEBUG_TIMER_PENDING_k_ADDR(k), HWIO_GSI_DEBUG_TIMER_PENDING_k_RMSK) +#define HWIO_GSI_DEBUG_TIMER_PENDING_k_INMI(k,mask) \ + in_dword_masked(HWIO_GSI_DEBUG_TIMER_PENDING_k_ADDR(k), mask) +#define HWIO_GSI_DEBUG_TIMER_PENDING_k_CHID_BIT_MAP_BMSK 0xffffffff +#define HWIO_GSI_DEBUG_TIMER_PENDING_k_CHID_BIT_MAP_SHFT 0x0 + +#define HWIO_GSI_DEBUG_RD_WR_PENDING_k_ADDR(k) (GSI_REG_BASE + 0x00001ac0 + 0x4 * (k)) +#define HWIO_GSI_DEBUG_RD_WR_PENDING_k_PHYS(k) (GSI_REG_BASE_PHYS + 0x00001ac0 + 0x4 * (k)) +#define HWIO_GSI_DEBUG_RD_WR_PENDING_k_OFFS(k) (GSI_REG_BASE_OFFS + 0x00001ac0 + 0x4 * (k)) +#define HWIO_GSI_DEBUG_RD_WR_PENDING_k_RMSK 0xffffffff +#define HWIO_GSI_DEBUG_RD_WR_PENDING_k_MAXk 1 +#define HWIO_GSI_DEBUG_RD_WR_PENDING_k_ATTR 0x1 +#define HWIO_GSI_DEBUG_RD_WR_PENDING_k_INI(k) \ + in_dword_masked(HWIO_GSI_DEBUG_RD_WR_PENDING_k_ADDR(k), HWIO_GSI_DEBUG_RD_WR_PENDING_k_RMSK) +#define HWIO_GSI_DEBUG_RD_WR_PENDING_k_INMI(k,mask) \ + in_dword_masked(HWIO_GSI_DEBUG_RD_WR_PENDING_k_ADDR(k), mask) +#define HWIO_GSI_DEBUG_RD_WR_PENDING_k_CHID_BIT_MAP_BMSK 0xffffffff +#define HWIO_GSI_DEBUG_RD_WR_PENDING_k_CHID_BIT_MAP_SHFT 0x0 + +#define HWIO_GSI_SPARE_REG_1_ADDR (GSI_REG_BASE + 0x00001030) +#define HWIO_GSI_SPARE_REG_1_PHYS (GSI_REG_BASE_PHYS + 0x00001030) +#define HWIO_GSI_SPARE_REG_1_OFFS (GSI_REG_BASE_OFFS + 0x00001030) +#define HWIO_GSI_SPARE_REG_1_RMSK 0x1 +#define HWIO_GSI_SPARE_REG_1_ATTR 0x3 +#define HWIO_GSI_SPARE_REG_1_IN \ + in_dword_masked(HWIO_GSI_SPARE_REG_1_ADDR, HWIO_GSI_SPARE_REG_1_RMSK) +#define HWIO_GSI_SPARE_REG_1_INM(m) \ + in_dword_masked(HWIO_GSI_SPARE_REG_1_ADDR, m) +#define HWIO_GSI_SPARE_REG_1_OUT(v) \ + out_dword(HWIO_GSI_SPARE_REG_1_ADDR,v) +#define HWIO_GSI_SPARE_REG_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_SPARE_REG_1_ADDR,m,v,HWIO_GSI_SPARE_REG_1_IN) +#define HWIO_GSI_SPARE_REG_1_FIX_IEOB_WRONG_MSK_DISABLE_BMSK 0x1 +#define HWIO_GSI_SPARE_REG_1_FIX_IEOB_WRONG_MSK_DISABLE_SHFT 0x0 + +#define HWIO_GSI_DEBUG_PC_FROM_SW_ADDR (GSI_REG_BASE + 0x00001040) +#define HWIO_GSI_DEBUG_PC_FROM_SW_PHYS (GSI_REG_BASE_PHYS + 0x00001040) +#define HWIO_GSI_DEBUG_PC_FROM_SW_OFFS (GSI_REG_BASE_OFFS + 0x00001040) +#define HWIO_GSI_DEBUG_PC_FROM_SW_RMSK 0xfff +#define HWIO_GSI_DEBUG_PC_FROM_SW_ATTR 0x3 +#define HWIO_GSI_DEBUG_PC_FROM_SW_IN \ + in_dword_masked(HWIO_GSI_DEBUG_PC_FROM_SW_ADDR, HWIO_GSI_DEBUG_PC_FROM_SW_RMSK) +#define HWIO_GSI_DEBUG_PC_FROM_SW_INM(m) \ + in_dword_masked(HWIO_GSI_DEBUG_PC_FROM_SW_ADDR, m) +#define HWIO_GSI_DEBUG_PC_FROM_SW_OUT(v) \ + out_dword(HWIO_GSI_DEBUG_PC_FROM_SW_ADDR,v) +#define HWIO_GSI_DEBUG_PC_FROM_SW_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_DEBUG_PC_FROM_SW_ADDR,m,v,HWIO_GSI_DEBUG_PC_FROM_SW_IN) +#define HWIO_GSI_DEBUG_PC_FROM_SW_IRAM_PTR_BMSK 0xfff +#define HWIO_GSI_DEBUG_PC_FROM_SW_IRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_DEBUG_SW_STALL_ADDR (GSI_REG_BASE + 0x00001044) +#define HWIO_GSI_DEBUG_SW_STALL_PHYS (GSI_REG_BASE_PHYS + 0x00001044) +#define HWIO_GSI_DEBUG_SW_STALL_OFFS (GSI_REG_BASE_OFFS + 0x00001044) +#define HWIO_GSI_DEBUG_SW_STALL_RMSK 0x1 +#define HWIO_GSI_DEBUG_SW_STALL_ATTR 0x3 +#define HWIO_GSI_DEBUG_SW_STALL_IN \ + in_dword_masked(HWIO_GSI_DEBUG_SW_STALL_ADDR, HWIO_GSI_DEBUG_SW_STALL_RMSK) +#define HWIO_GSI_DEBUG_SW_STALL_INM(m) \ + in_dword_masked(HWIO_GSI_DEBUG_SW_STALL_ADDR, m) +#define HWIO_GSI_DEBUG_SW_STALL_OUT(v) \ + out_dword(HWIO_GSI_DEBUG_SW_STALL_ADDR,v) +#define HWIO_GSI_DEBUG_SW_STALL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_DEBUG_SW_STALL_ADDR,m,v,HWIO_GSI_DEBUG_SW_STALL_IN) +#define HWIO_GSI_DEBUG_SW_STALL_MCS_STALL_BMSK 0x1 +#define HWIO_GSI_DEBUG_SW_STALL_MCS_STALL_SHFT 0x0 + +#define HWIO_GSI_DEBUG_PC_FOR_DEBUG_ADDR (GSI_REG_BASE + 0x00001048) +#define HWIO_GSI_DEBUG_PC_FOR_DEBUG_PHYS (GSI_REG_BASE_PHYS + 0x00001048) +#define HWIO_GSI_DEBUG_PC_FOR_DEBUG_OFFS (GSI_REG_BASE_OFFS + 0x00001048) +#define HWIO_GSI_DEBUG_PC_FOR_DEBUG_RMSK 0xfff +#define HWIO_GSI_DEBUG_PC_FOR_DEBUG_ATTR 0x1 +#define HWIO_GSI_DEBUG_PC_FOR_DEBUG_IN \ + in_dword_masked(HWIO_GSI_DEBUG_PC_FOR_DEBUG_ADDR, HWIO_GSI_DEBUG_PC_FOR_DEBUG_RMSK) +#define HWIO_GSI_DEBUG_PC_FOR_DEBUG_INM(m) \ + in_dword_masked(HWIO_GSI_DEBUG_PC_FOR_DEBUG_ADDR, m) +#define HWIO_GSI_DEBUG_PC_FOR_DEBUG_IRAM_PTR_BMSK 0xfff +#define HWIO_GSI_DEBUG_PC_FOR_DEBUG_IRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_DEBUG_QSB_LOG_SEL_ADDR (GSI_REG_BASE + 0x00001050) +#define HWIO_GSI_DEBUG_QSB_LOG_SEL_PHYS (GSI_REG_BASE_PHYS + 0x00001050) +#define HWIO_GSI_DEBUG_QSB_LOG_SEL_OFFS (GSI_REG_BASE_OFFS + 0x00001050) +#define HWIO_GSI_DEBUG_QSB_LOG_SEL_RMSK 0xffff01 +#define HWIO_GSI_DEBUG_QSB_LOG_SEL_ATTR 0x3 +#define HWIO_GSI_DEBUG_QSB_LOG_SEL_IN \ + in_dword_masked(HWIO_GSI_DEBUG_QSB_LOG_SEL_ADDR, HWIO_GSI_DEBUG_QSB_LOG_SEL_RMSK) +#define HWIO_GSI_DEBUG_QSB_LOG_SEL_INM(m) \ + in_dword_masked(HWIO_GSI_DEBUG_QSB_LOG_SEL_ADDR, m) +#define HWIO_GSI_DEBUG_QSB_LOG_SEL_OUT(v) \ + out_dword(HWIO_GSI_DEBUG_QSB_LOG_SEL_ADDR,v) +#define HWIO_GSI_DEBUG_QSB_LOG_SEL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_DEBUG_QSB_LOG_SEL_ADDR,m,v,HWIO_GSI_DEBUG_QSB_LOG_SEL_IN) +#define HWIO_GSI_DEBUG_QSB_LOG_SEL_SEL_MID_BMSK 0xff0000 +#define HWIO_GSI_DEBUG_QSB_LOG_SEL_SEL_MID_SHFT 0x10 +#define HWIO_GSI_DEBUG_QSB_LOG_SEL_SEL_TID_BMSK 0xff00 +#define HWIO_GSI_DEBUG_QSB_LOG_SEL_SEL_TID_SHFT 0x8 +#define HWIO_GSI_DEBUG_QSB_LOG_SEL_SEL_WRITE_BMSK 0x1 +#define HWIO_GSI_DEBUG_QSB_LOG_SEL_SEL_WRITE_SHFT 0x0 + +#define HWIO_GSI_DEBUG_QSB_LOG_CLR_ADDR (GSI_REG_BASE + 0x00001058) +#define HWIO_GSI_DEBUG_QSB_LOG_CLR_PHYS (GSI_REG_BASE_PHYS + 0x00001058) +#define HWIO_GSI_DEBUG_QSB_LOG_CLR_OFFS (GSI_REG_BASE_OFFS + 0x00001058) +#define HWIO_GSI_DEBUG_QSB_LOG_CLR_RMSK 0x1 +#define HWIO_GSI_DEBUG_QSB_LOG_CLR_ATTR 0x2 +#define HWIO_GSI_DEBUG_QSB_LOG_CLR_OUT(v) \ + out_dword(HWIO_GSI_DEBUG_QSB_LOG_CLR_ADDR,v) +#define HWIO_GSI_DEBUG_QSB_LOG_CLR_LOG_CLR_BMSK 0x1 +#define HWIO_GSI_DEBUG_QSB_LOG_CLR_LOG_CLR_SHFT 0x0 + +#define HWIO_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ADDR (GSI_REG_BASE + 0x00001060) +#define HWIO_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_PHYS (GSI_REG_BASE_PHYS + 0x00001060) +#define HWIO_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_OFFS (GSI_REG_BASE_OFFS + 0x00001060) +#define HWIO_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_RMSK 0x1ffff01 +#define HWIO_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ATTR 0x1 +#define HWIO_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_IN \ + in_dword_masked(HWIO_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ADDR, HWIO_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_RMSK) +#define HWIO_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_INM(m) \ + in_dword_masked(HWIO_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ADDR, m) +#define HWIO_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ERR_SAVED_BMSK 0x1000000 +#define HWIO_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ERR_SAVED_SHFT 0x18 +#define HWIO_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ERR_MID_BMSK 0xff0000 +#define HWIO_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ERR_MID_SHFT 0x10 +#define HWIO_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ERR_TID_BMSK 0xff00 +#define HWIO_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ERR_TID_SHFT 0x8 +#define HWIO_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ERR_WRITE_BMSK 0x1 +#define HWIO_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ERR_WRITE_SHFT 0x0 + +#define HWIO_GSI_DEBUG_QSB_LOG_0_ADDR (GSI_REG_BASE + 0x00001064) +#define HWIO_GSI_DEBUG_QSB_LOG_0_PHYS (GSI_REG_BASE_PHYS + 0x00001064) +#define HWIO_GSI_DEBUG_QSB_LOG_0_OFFS (GSI_REG_BASE_OFFS + 0x00001064) +#define HWIO_GSI_DEBUG_QSB_LOG_0_RMSK 0xffffffff +#define HWIO_GSI_DEBUG_QSB_LOG_0_ATTR 0x1 +#define HWIO_GSI_DEBUG_QSB_LOG_0_IN \ + in_dword_masked(HWIO_GSI_DEBUG_QSB_LOG_0_ADDR, HWIO_GSI_DEBUG_QSB_LOG_0_RMSK) +#define HWIO_GSI_DEBUG_QSB_LOG_0_INM(m) \ + in_dword_masked(HWIO_GSI_DEBUG_QSB_LOG_0_ADDR, m) +#define HWIO_GSI_DEBUG_QSB_LOG_0_ADDR_31_0_BMSK 0xffffffff +#define HWIO_GSI_DEBUG_QSB_LOG_0_ADDR_31_0_SHFT 0x0 + +#define HWIO_GSI_DEBUG_QSB_LOG_1_ADDR (GSI_REG_BASE + 0x00001068) +#define HWIO_GSI_DEBUG_QSB_LOG_1_PHYS (GSI_REG_BASE_PHYS + 0x00001068) +#define HWIO_GSI_DEBUG_QSB_LOG_1_OFFS (GSI_REG_BASE_OFFS + 0x00001068) +#define HWIO_GSI_DEBUG_QSB_LOG_1_RMSK 0xfff7ffff +#define HWIO_GSI_DEBUG_QSB_LOG_1_ATTR 0x1 +#define HWIO_GSI_DEBUG_QSB_LOG_1_IN \ + in_dword_masked(HWIO_GSI_DEBUG_QSB_LOG_1_ADDR, HWIO_GSI_DEBUG_QSB_LOG_1_RMSK) +#define HWIO_GSI_DEBUG_QSB_LOG_1_INM(m) \ + in_dword_masked(HWIO_GSI_DEBUG_QSB_LOG_1_ADDR, m) +#define HWIO_GSI_DEBUG_QSB_LOG_1_AREQPRIORITY_BMSK 0xf0000000 +#define HWIO_GSI_DEBUG_QSB_LOG_1_AREQPRIORITY_SHFT 0x1c +#define HWIO_GSI_DEBUG_QSB_LOG_1_ASIZE_BMSK 0xf000000 +#define HWIO_GSI_DEBUG_QSB_LOG_1_ASIZE_SHFT 0x18 +#define HWIO_GSI_DEBUG_QSB_LOG_1_ALEN_BMSK 0xf00000 +#define HWIO_GSI_DEBUG_QSB_LOG_1_ALEN_SHFT 0x14 +#define HWIO_GSI_DEBUG_QSB_LOG_1_AOOOWR_BMSK 0x40000 +#define HWIO_GSI_DEBUG_QSB_LOG_1_AOOOWR_SHFT 0x12 +#define HWIO_GSI_DEBUG_QSB_LOG_1_AOOORD_BMSK 0x20000 +#define HWIO_GSI_DEBUG_QSB_LOG_1_AOOORD_SHFT 0x11 +#define HWIO_GSI_DEBUG_QSB_LOG_1_ATRANSIENT_BMSK 0x10000 +#define HWIO_GSI_DEBUG_QSB_LOG_1_ATRANSIENT_SHFT 0x10 +#define HWIO_GSI_DEBUG_QSB_LOG_1_ACACHEABLE_BMSK 0x8000 +#define HWIO_GSI_DEBUG_QSB_LOG_1_ACACHEABLE_SHFT 0xf +#define HWIO_GSI_DEBUG_QSB_LOG_1_ASHARED_BMSK 0x4000 +#define HWIO_GSI_DEBUG_QSB_LOG_1_ASHARED_SHFT 0xe +#define HWIO_GSI_DEBUG_QSB_LOG_1_ANOALLOCATE_BMSK 0x2000 +#define HWIO_GSI_DEBUG_QSB_LOG_1_ANOALLOCATE_SHFT 0xd +#define HWIO_GSI_DEBUG_QSB_LOG_1_AINNERSHARED_BMSK 0x1000 +#define HWIO_GSI_DEBUG_QSB_LOG_1_AINNERSHARED_SHFT 0xc +#define HWIO_GSI_DEBUG_QSB_LOG_1_ADDR_43_32_BMSK 0xfff +#define HWIO_GSI_DEBUG_QSB_LOG_1_ADDR_43_32_SHFT 0x0 + +#define HWIO_GSI_DEBUG_QSB_LOG_2_ADDR (GSI_REG_BASE + 0x0000106c) +#define HWIO_GSI_DEBUG_QSB_LOG_2_PHYS (GSI_REG_BASE_PHYS + 0x0000106c) +#define HWIO_GSI_DEBUG_QSB_LOG_2_OFFS (GSI_REG_BASE_OFFS + 0x0000106c) +#define HWIO_GSI_DEBUG_QSB_LOG_2_RMSK 0xffff +#define HWIO_GSI_DEBUG_QSB_LOG_2_ATTR 0x1 +#define HWIO_GSI_DEBUG_QSB_LOG_2_IN \ + in_dword_masked(HWIO_GSI_DEBUG_QSB_LOG_2_ADDR, HWIO_GSI_DEBUG_QSB_LOG_2_RMSK) +#define HWIO_GSI_DEBUG_QSB_LOG_2_INM(m) \ + in_dword_masked(HWIO_GSI_DEBUG_QSB_LOG_2_ADDR, m) +#define HWIO_GSI_DEBUG_QSB_LOG_2_AMEMTYPE_BMSK 0xf000 +#define HWIO_GSI_DEBUG_QSB_LOG_2_AMEMTYPE_SHFT 0xc +#define HWIO_GSI_DEBUG_QSB_LOG_2_AMMUSID_BMSK 0xfff +#define HWIO_GSI_DEBUG_QSB_LOG_2_AMMUSID_SHFT 0x0 + +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_ADDR(n) (GSI_REG_BASE + 0x00001070 + 0x4 * (n)) +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_PHYS(n) (GSI_REG_BASE_PHYS + 0x00001070 + 0x4 * (n)) +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_OFFS(n) (GSI_REG_BASE_OFFS + 0x00001070 + 0x4 * (n)) +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_RMSK 0xffffffff +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_MAXn 3 +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_ATTR 0x1 +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_INI(n) \ + in_dword_masked(HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_ADDR(n), HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_RMSK) +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_INMI(n,mask) \ + in_dword_masked(HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_ADDR(n), mask) +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_MID_BMSK 0xf8000000 +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_MID_SHFT 0x1b +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_TID_BMSK 0x7c00000 +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_TID_SHFT 0x16 +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_WRITE_BMSK 0x200000 +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_WRITE_SHFT 0x15 +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_ADDR_20_0_BMSK 0x1fffff +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_ADDR_20_0_SHFT 0x0 + +#define HWIO_GSI_DEBUG_SW_RF_n_WRITE_ADDR(n) (GSI_REG_BASE + 0x00001080 + 0x4 * (n)) +#define HWIO_GSI_DEBUG_SW_RF_n_WRITE_PHYS(n) (GSI_REG_BASE_PHYS + 0x00001080 + 0x4 * (n)) +#define HWIO_GSI_DEBUG_SW_RF_n_WRITE_OFFS(n) (GSI_REG_BASE_OFFS + 0x00001080 + 0x4 * (n)) +#define HWIO_GSI_DEBUG_SW_RF_n_WRITE_RMSK 0xffffffff +#define HWIO_GSI_DEBUG_SW_RF_n_WRITE_MAXn 31 +#define HWIO_GSI_DEBUG_SW_RF_n_WRITE_ATTR 0x2 +#define HWIO_GSI_DEBUG_SW_RF_n_WRITE_OUTI(n,val) \ + out_dword(HWIO_GSI_DEBUG_SW_RF_n_WRITE_ADDR(n),val) +#define HWIO_GSI_DEBUG_SW_RF_n_WRITE_DATA_IN_BMSK 0xffffffff +#define HWIO_GSI_DEBUG_SW_RF_n_WRITE_DATA_IN_SHFT 0x0 + +#define HWIO_GSI_DEBUG_SW_RF_n_READ_ADDR(n) (GSI_REG_BASE + 0x00001100 + 0x4 * (n)) +#define HWIO_GSI_DEBUG_SW_RF_n_READ_PHYS(n) (GSI_REG_BASE_PHYS + 0x00001100 + 0x4 * (n)) +#define HWIO_GSI_DEBUG_SW_RF_n_READ_OFFS(n) (GSI_REG_BASE_OFFS + 0x00001100 + 0x4 * (n)) +#define HWIO_GSI_DEBUG_SW_RF_n_READ_RMSK 0xffffffff +#define HWIO_GSI_DEBUG_SW_RF_n_READ_MAXn 31 +#define HWIO_GSI_DEBUG_SW_RF_n_READ_ATTR 0x1 +#define HWIO_GSI_DEBUG_SW_RF_n_READ_INI(n) \ + in_dword_masked(HWIO_GSI_DEBUG_SW_RF_n_READ_ADDR(n), HWIO_GSI_DEBUG_SW_RF_n_READ_RMSK, HWIO_GSI_DEBUG_SW_RF_n_READ_ATTR) +#define HWIO_GSI_DEBUG_SW_RF_n_READ_INMI(n,mask) \ + in_dword_masked(HWIO_GSI_DEBUG_SW_RF_n_READ_ADDR(n), mask, HWIO_GSI_DEBUG_SW_RF_n_READ_ATTR) +#define HWIO_GSI_DEBUG_SW_RF_n_READ_RF_REG_BMSK 0xffffffff +#define HWIO_GSI_DEBUG_SW_RF_n_READ_RF_REG_SHFT 0x0 + +#define HWIO_GSI_DEBUG_COUNTER_CFGn_ADDR(n) (GSI_REG_BASE + 0x00001180 + 0x4 * (n)) +#define HWIO_GSI_DEBUG_COUNTER_CFGn_PHYS(n) (GSI_REG_BASE_PHYS + 0x00001180 + 0x4 * (n)) +#define HWIO_GSI_DEBUG_COUNTER_CFGn_OFFS(n) (GSI_REG_BASE_OFFS + 0x00001180 + 0x4 * (n)) +#define HWIO_GSI_DEBUG_COUNTER_CFGn_RMSK 0x1fffff +#define HWIO_GSI_DEBUG_COUNTER_CFGn_MAXn 7 +#define HWIO_GSI_DEBUG_COUNTER_CFGn_ATTR 0x3 +#define HWIO_GSI_DEBUG_COUNTER_CFGn_INI(n) \ + in_dword_masked(HWIO_GSI_DEBUG_COUNTER_CFGn_ADDR(n), HWIO_GSI_DEBUG_COUNTER_CFGn_RMSK) +#define HWIO_GSI_DEBUG_COUNTER_CFGn_INMI(n,mask) \ + in_dword_masked(HWIO_GSI_DEBUG_COUNTER_CFGn_ADDR(n), mask) +#define HWIO_GSI_DEBUG_COUNTER_CFGn_OUTI(n,val) \ + out_dword(HWIO_GSI_DEBUG_COUNTER_CFGn_ADDR(n),val) +#define HWIO_GSI_DEBUG_COUNTER_CFGn_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_GSI_DEBUG_COUNTER_CFGn_ADDR(n),mask,val,HWIO_GSI_DEBUG_COUNTER_CFGn_INI(n)) +#define HWIO_GSI_DEBUG_COUNTER_CFGn_CHAIN_BMSK 0x100000 +#define HWIO_GSI_DEBUG_COUNTER_CFGn_CHAIN_SHFT 0x14 +#define HWIO_GSI_DEBUG_COUNTER_CFGn_VIRTUAL_CHNL_BMSK 0xff000 +#define HWIO_GSI_DEBUG_COUNTER_CFGn_VIRTUAL_CHNL_SHFT 0xc +#define HWIO_GSI_DEBUG_COUNTER_CFGn_EE_BMSK 0xf00 +#define HWIO_GSI_DEBUG_COUNTER_CFGn_EE_SHFT 0x8 +#define HWIO_GSI_DEBUG_COUNTER_CFGn_EVNT_TYPE_BMSK 0xf8 +#define HWIO_GSI_DEBUG_COUNTER_CFGn_EVNT_TYPE_SHFT 0x3 +#define HWIO_GSI_DEBUG_COUNTER_CFGn_CLR_AT_READ_BMSK 0x4 +#define HWIO_GSI_DEBUG_COUNTER_CFGn_CLR_AT_READ_SHFT 0x2 +#define HWIO_GSI_DEBUG_COUNTER_CFGn_STOP_AT_WRAP_ARND_BMSK 0x2 +#define HWIO_GSI_DEBUG_COUNTER_CFGn_STOP_AT_WRAP_ARND_SHFT 0x1 +#define HWIO_GSI_DEBUG_COUNTER_CFGn_ENABLE_BMSK 0x1 +#define HWIO_GSI_DEBUG_COUNTER_CFGn_ENABLE_SHFT 0x0 + +#define HWIO_GSI_DEBUG_COUNTERn_ADDR(n) (GSI_REG_BASE + 0x000011a0 + 0x4 * (n)) +#define HWIO_GSI_DEBUG_COUNTERn_PHYS(n) (GSI_REG_BASE_PHYS + 0x000011a0 + 0x4 * (n)) +#define HWIO_GSI_DEBUG_COUNTERn_OFFS(n) (GSI_REG_BASE_OFFS + 0x000011a0 + 0x4 * (n)) +#define HWIO_GSI_DEBUG_COUNTERn_RMSK 0xffff +#define HWIO_GSI_DEBUG_COUNTERn_MAXn 7 +#define HWIO_GSI_DEBUG_COUNTERn_ATTR 0x1 +#define HWIO_GSI_DEBUG_COUNTERn_INI(n) \ + in_dword_masked(HWIO_GSI_DEBUG_COUNTERn_ADDR(n), HWIO_GSI_DEBUG_COUNTERn_RMSK, HWIO_GSI_DEBUG_COUNTERn_ATTR) +#define HWIO_GSI_DEBUG_COUNTERn_INMI(n,mask) \ + in_dword_masked(HWIO_GSI_DEBUG_COUNTERn_ADDR(n), mask, HWIO_GSI_DEBUG_COUNTERn_ATTR) +#define HWIO_GSI_DEBUG_COUNTERn_COUNTER_VALUE_BMSK 0xffff +#define HWIO_GSI_DEBUG_COUNTERn_COUNTER_VALUE_SHFT 0x0 + +#define HWIO_GSI_DEBUG_SW_MSK_REG_n_SEC_k_WR_ADDR(n,k) (GSI_REG_BASE + 0x000011c0 + 0x4 * (n) + 0x24 * (k)) +#define HWIO_GSI_DEBUG_SW_MSK_REG_n_SEC_k_WR_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x000011c0 + 0x4 * (n) + 0x24 * (k)) +#define HWIO_GSI_DEBUG_SW_MSK_REG_n_SEC_k_WR_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x000011c0 + 0x4 * (n) + 0x24 * (k)) +#define HWIO_GSI_DEBUG_SW_MSK_REG_n_SEC_k_WR_RMSK 0xffffffff +#define HWIO_GSI_DEBUG_SW_MSK_REG_n_SEC_k_WR_MAXn 8 +#define HWIO_GSI_DEBUG_SW_MSK_REG_n_SEC_k_WR_MAXk 1 +#define HWIO_GSI_DEBUG_SW_MSK_REG_n_SEC_k_WR_ATTR 0x2 +#define HWIO_GSI_DEBUG_SW_MSK_REG_n_SEC_k_WR_OUTI2(n,k,val) \ + out_dword(HWIO_GSI_DEBUG_SW_MSK_REG_n_SEC_k_WR_ADDR(n,k),val) +#define HWIO_GSI_DEBUG_SW_MSK_REG_n_SEC_k_WR_DATA_IN_BMSK 0xffffffff +#define HWIO_GSI_DEBUG_SW_MSK_REG_n_SEC_k_WR_DATA_IN_SHFT 0x0 + +#define HWIO_GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD_ADDR(n,k) (GSI_REG_BASE + 0x000012e0 + 0x4 * (n) + 0x24 * (k)) +#define HWIO_GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x000012e0 + 0x4 * (n) + 0x24 * (k)) +#define HWIO_GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x000012e0 + 0x4 * (n) + 0x24 * (k)) +#define HWIO_GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD_RMSK 0xffffffff +#define HWIO_GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD_MAXn 8 +#define HWIO_GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD_MAXk 1 +#define HWIO_GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD_ATTR 0x1 +#define HWIO_GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD_INI2(n,k) \ + in_dword_masked(HWIO_GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD_ADDR(n,k), HWIO_GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD_RMSK) +#define HWIO_GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD_INMI2(n,k,mask) \ + in_dword_masked(HWIO_GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD_ADDR(n,k), mask) +#define HWIO_GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD_MSK_REG_BMSK 0xffffffff +#define HWIO_GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD_MSK_REG_SHFT 0x0 + +#define HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_ADDR(n,k) (GSI_REG_BASE + 0x00001400 + 0x80 * (n) + 0x4 * (k)) +#define HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x00001400 + 0x80 * (n) + 0x4 * (k)) +#define HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x00001400 + 0x80 * (n) + 0x4 * (k)) +#define HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_RMSK 0x1ff +#define HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_MAXn 3 +#define HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_MAXk 27 +#define HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_ATTR 0x1 +#define HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_INI2(n,k) \ + in_dword_masked(HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_ADDR(n,k), HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_RMSK) +#define HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_INMI2(n,k,mask) \ + in_dword_masked(HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_ADDR(n,k), mask) +#define HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_VALID_BMSK 0x100 +#define HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_VALID_SHFT 0x8 +#define HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_PHY_CH_BMSK 0xff +#define HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_PHY_CH_SHFT 0x0 + +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_ADDR(n,k) (GSI_REG_BASE + 0x00001600 + 0x100 * (n) + 0x4 * (k)) +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x00001600 + 0x100 * (n) + 0x4 * (k)) +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x00001600 + 0x100 * (n) + 0x4 * (k)) +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_RMSK 0x1ff +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_MAXn 3 +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_MAXk 26 +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_ATTR 0x1 +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_INI2(n,k) \ + in_dword_masked(HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_ADDR(n,k), HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_RMSK) +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_INMI2(n,k,mask) \ + in_dword_masked(HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_ADDR(n,k), mask) +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_VALID_BMSK 0x100 +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_VALID_SHFT 0x8 +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_PHY_EV_CH_BMSK 0xff +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_PHY_EV_CH_SHFT 0x0 + +#define HWIO_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_ADDR (GSI_REG_BASE + 0x00001a54) +#define HWIO_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_PHYS (GSI_REG_BASE_PHYS + 0x00001a54) +#define HWIO_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_OFFS (GSI_REG_BASE_OFFS + 0x00001a54) +#define HWIO_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_RMSK 0xff +#define HWIO_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_ATTR 0x3 +#define HWIO_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_IN \ + in_dword_masked(HWIO_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_ADDR, HWIO_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_RMSK) +#define HWIO_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_INM(m) \ + in_dword_masked(HWIO_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_ADDR, m) +#define HWIO_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_OUT(v) \ + out_dword(HWIO_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_ADDR,v) +#define HWIO_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_ADDR,m,v,HWIO_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_IN) +#define HWIO_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_PREFETCH_BUF_CH_ID_BMSK 0xff +#define HWIO_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_PREFETCH_BUF_CH_ID_SHFT 0x0 + +#define HWIO_GSI_DEBUG_REE_PREFETCH_BUF_STATUS_ADDR (GSI_REG_BASE + 0x00001a58) +#define HWIO_GSI_DEBUG_REE_PREFETCH_BUF_STATUS_PHYS (GSI_REG_BASE_PHYS + 0x00001a58) +#define HWIO_GSI_DEBUG_REE_PREFETCH_BUF_STATUS_OFFS (GSI_REG_BASE_OFFS + 0x00001a58) +#define HWIO_GSI_DEBUG_REE_PREFETCH_BUF_STATUS_RMSK 0xffffffff +#define HWIO_GSI_DEBUG_REE_PREFETCH_BUF_STATUS_ATTR 0x1 +#define HWIO_GSI_DEBUG_REE_PREFETCH_BUF_STATUS_IN \ + in_dword_masked(HWIO_GSI_DEBUG_REE_PREFETCH_BUF_STATUS_ADDR, HWIO_GSI_DEBUG_REE_PREFETCH_BUF_STATUS_RMSK) +#define HWIO_GSI_DEBUG_REE_PREFETCH_BUF_STATUS_INM(m) \ + in_dword_masked(HWIO_GSI_DEBUG_REE_PREFETCH_BUF_STATUS_ADDR, m) +#define HWIO_GSI_DEBUG_REE_PREFETCH_BUF_STATUS_PREFETCH_BUF_STATUS_BMSK 0xffffffff +#define HWIO_GSI_DEBUG_REE_PREFETCH_BUF_STATUS_PREFETCH_BUF_STATUS_SHFT 0x0 + +#define HWIO_GSI_MCS_PROFILING_BP_CNT_LSB_ADDR (GSI_REG_BASE + 0x00001a5c) +#define HWIO_GSI_MCS_PROFILING_BP_CNT_LSB_PHYS (GSI_REG_BASE_PHYS + 0x00001a5c) +#define HWIO_GSI_MCS_PROFILING_BP_CNT_LSB_OFFS (GSI_REG_BASE_OFFS + 0x00001a5c) +#define HWIO_GSI_MCS_PROFILING_BP_CNT_LSB_RMSK 0xffffffff +#define HWIO_GSI_MCS_PROFILING_BP_CNT_LSB_ATTR 0x1 +#define HWIO_GSI_MCS_PROFILING_BP_CNT_LSB_IN \ + in_dword_masked(HWIO_GSI_MCS_PROFILING_BP_CNT_LSB_ADDR, HWIO_GSI_MCS_PROFILING_BP_CNT_LSB_RMSK) +#define HWIO_GSI_MCS_PROFILING_BP_CNT_LSB_INM(m) \ + in_dword_masked(HWIO_GSI_MCS_PROFILING_BP_CNT_LSB_ADDR, m) +#define HWIO_GSI_MCS_PROFILING_BP_CNT_LSB_BP_CNT_LSB_BMSK 0xffffffff +#define HWIO_GSI_MCS_PROFILING_BP_CNT_LSB_BP_CNT_LSB_SHFT 0x0 + +#define HWIO_GSI_MCS_PROFILING_BP_CNT_MSB_ADDR (GSI_REG_BASE + 0x00001a60) +#define HWIO_GSI_MCS_PROFILING_BP_CNT_MSB_PHYS (GSI_REG_BASE_PHYS + 0x00001a60) +#define HWIO_GSI_MCS_PROFILING_BP_CNT_MSB_OFFS (GSI_REG_BASE_OFFS + 0x00001a60) +#define HWIO_GSI_MCS_PROFILING_BP_CNT_MSB_RMSK 0xf +#define HWIO_GSI_MCS_PROFILING_BP_CNT_MSB_ATTR 0x1 +#define HWIO_GSI_MCS_PROFILING_BP_CNT_MSB_IN \ + in_dword_masked(HWIO_GSI_MCS_PROFILING_BP_CNT_MSB_ADDR, HWIO_GSI_MCS_PROFILING_BP_CNT_MSB_RMSK) +#define HWIO_GSI_MCS_PROFILING_BP_CNT_MSB_INM(m) \ + in_dword_masked(HWIO_GSI_MCS_PROFILING_BP_CNT_MSB_ADDR, m) +#define HWIO_GSI_MCS_PROFILING_BP_CNT_MSB_BP_CNT_MSB_BMSK 0xf +#define HWIO_GSI_MCS_PROFILING_BP_CNT_MSB_BP_CNT_MSB_SHFT 0x0 + +#define HWIO_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB_ADDR (GSI_REG_BASE + 0x00001a64) +#define HWIO_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB_PHYS (GSI_REG_BASE_PHYS + 0x00001a64) +#define HWIO_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB_OFFS (GSI_REG_BASE_OFFS + 0x00001a64) +#define HWIO_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB_RMSK 0xffffffff +#define HWIO_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB_ATTR 0x1 +#define HWIO_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB_IN \ + in_dword_masked(HWIO_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB_ADDR, HWIO_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB_RMSK) +#define HWIO_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB_INM(m) \ + in_dword_masked(HWIO_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB_ADDR, m) +#define HWIO_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB_BP_AND_PENDING_CNT_LSB_BMSK 0xffffffff +#define HWIO_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB_BP_AND_PENDING_CNT_LSB_SHFT 0x0 + +#define HWIO_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB_ADDR (GSI_REG_BASE + 0x00001a68) +#define HWIO_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB_PHYS (GSI_REG_BASE_PHYS + 0x00001a68) +#define HWIO_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB_OFFS (GSI_REG_BASE_OFFS + 0x00001a68) +#define HWIO_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB_RMSK 0xf +#define HWIO_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB_ATTR 0x1 +#define HWIO_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB_IN \ + in_dword_masked(HWIO_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB_ADDR, HWIO_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB_RMSK) +#define HWIO_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB_INM(m) \ + in_dword_masked(HWIO_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB_ADDR, m) +#define HWIO_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB_BP_AND_PENDING_CNT_MSB_BMSK 0xf +#define HWIO_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB_BP_AND_PENDING_CNT_MSB_SHFT 0x0 + +#define HWIO_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB_ADDR (GSI_REG_BASE + 0x00001a6c) +#define HWIO_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB_PHYS (GSI_REG_BASE_PHYS + 0x00001a6c) +#define HWIO_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB_OFFS (GSI_REG_BASE_OFFS + 0x00001a6c) +#define HWIO_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB_RMSK 0xffffffff +#define HWIO_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB_ATTR 0x1 +#define HWIO_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB_IN \ + in_dword_masked(HWIO_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB_ADDR, HWIO_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB_RMSK) +#define HWIO_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB_INM(m) \ + in_dword_masked(HWIO_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB_ADDR, m) +#define HWIO_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB_MCS_BUSY_CNT_LSB_BMSK 0xffffffff +#define HWIO_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB_MCS_BUSY_CNT_LSB_SHFT 0x0 + +#define HWIO_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB_ADDR (GSI_REG_BASE + 0x00001a70) +#define HWIO_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB_PHYS (GSI_REG_BASE_PHYS + 0x00001a70) +#define HWIO_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB_OFFS (GSI_REG_BASE_OFFS + 0x00001a70) +#define HWIO_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB_RMSK 0xf +#define HWIO_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB_ATTR 0x1 +#define HWIO_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB_IN \ + in_dword_masked(HWIO_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB_ADDR, HWIO_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB_RMSK) +#define HWIO_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB_INM(m) \ + in_dword_masked(HWIO_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB_ADDR, m) +#define HWIO_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB_MCS_BUSY_CNT_MSB_BMSK 0xf +#define HWIO_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB_MCS_BUSY_CNT_MSB_SHFT 0x0 + +#define HWIO_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB_ADDR (GSI_REG_BASE + 0x00001a74) +#define HWIO_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB_PHYS (GSI_REG_BASE_PHYS + 0x00001a74) +#define HWIO_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB_OFFS (GSI_REG_BASE_OFFS + 0x00001a74) +#define HWIO_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB_RMSK 0xffffffff +#define HWIO_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB_ATTR 0x1 +#define HWIO_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB_IN \ + in_dword_masked(HWIO_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB_ADDR, HWIO_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB_RMSK) +#define HWIO_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB_INM(m) \ + in_dword_masked(HWIO_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB_ADDR, m) +#define HWIO_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB_MCS_IDLE_CNT_LSB_BMSK 0xffffffff +#define HWIO_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB_MCS_IDLE_CNT_LSB_SHFT 0x0 + +#define HWIO_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_ADDR (GSI_REG_BASE + 0x00001a78) +#define HWIO_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_PHYS (GSI_REG_BASE_PHYS + 0x00001a78) +#define HWIO_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_OFFS (GSI_REG_BASE_OFFS + 0x00001a78) +#define HWIO_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_RMSK 0xf +#define HWIO_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_ATTR 0x1 +#define HWIO_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_IN \ + in_dword_masked(HWIO_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_ADDR, HWIO_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_RMSK) +#define HWIO_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_INM(m) \ + in_dword_masked(HWIO_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_ADDR, m) +#define HWIO_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_MCS_IDLE_CNT_MSB_BMSK 0xf +#define HWIO_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_MCS_IDLE_CNT_MSB_SHFT 0x0 + +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_ADDR(n,k) (GSI_REG_BASE + 0x00014000 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x00014000 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x00014000 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_MAXk 27 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_CNTXT_0_ADDR(n,k), HWIO_EE_n_GSI_CH_k_CNTXT_0_RMSK) +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_CNTXT_0_ADDR(n,k), mask) +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_GSI_CH_k_CNTXT_0_ADDR(n,k),val) +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_GSI_CH_k_CNTXT_0_ADDR(n,k),mask,val,HWIO_EE_n_GSI_CH_k_CNTXT_0_INI2(n,k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_ELEMENT_SIZE_BMSK 0xff000000 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_ELEMENT_SIZE_SHFT 0x18 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_BMSK 0xf00000 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_SHFT 0x14 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_NOT_ALLOCATED_FVAL 0x0 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_ALLOCATED_FVAL 0x1 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_STARTED_FVAL 0x2 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_STOPED_FVAL 0x3 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_STOP_IN_PROC_FVAL 0x4 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_ERROR_FVAL 0xf +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHID_BMSK 0xff000 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHID_SHFT 0xc +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_EE_BMSK 0xf00 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_EE_SHFT 0x8 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_DIR_BMSK 0x80 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_DIR_SHFT 0x7 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_DIR_INBOUND_FVAL 0x0 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_DIR_OUTBOUND_FVAL 0x1 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_BMSK 0x7f +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_SHFT 0x0 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_MHI_FVAL 0x0 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_XHCI_FVAL 0x1 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_GPI_FVAL 0x2 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_XDCI_FVAL 0x3 + +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_ADDR(n,k) (GSI_REG_BASE + 0x00014004 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x00014004 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x00014004 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_MAXk 27 +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_CNTXT_1_ADDR(n,k), HWIO_EE_n_GSI_CH_k_CNTXT_1_RMSK) +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_CNTXT_1_ADDR(n,k), mask) +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_GSI_CH_k_CNTXT_1_ADDR(n,k),val) +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_GSI_CH_k_CNTXT_1_ADDR(n,k),mask,val,HWIO_EE_n_GSI_CH_k_CNTXT_1_INI2(n,k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_ERINDEX_BMSK 0xff000000 +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_ERINDEX_SHFT 0x18 +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_R_LENGTH_BMSK 0xffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_R_LENGTH_SHFT 0x0 + +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_ADDR(n,k) (GSI_REG_BASE + 0x00014008 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x00014008 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x00014008 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_MAXk 27 +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_CNTXT_2_ADDR(n,k), HWIO_EE_n_GSI_CH_k_CNTXT_2_RMSK) +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_CNTXT_2_ADDR(n,k), mask) +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_GSI_CH_k_CNTXT_2_ADDR(n,k),val) +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_GSI_CH_k_CNTXT_2_ADDR(n,k),mask,val,HWIO_EE_n_GSI_CH_k_CNTXT_2_INI2(n,k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_R_BASE_ADDR_LSBS_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_R_BASE_ADDR_LSBS_SHFT 0x0 + +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_ADDR(n,k) (GSI_REG_BASE + 0x0001400c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x0001400c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x0001400c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_MAXk 27 +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_CNTXT_3_ADDR(n,k), HWIO_EE_n_GSI_CH_k_CNTXT_3_RMSK) +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_CNTXT_3_ADDR(n,k), mask) +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_GSI_CH_k_CNTXT_3_ADDR(n,k),val) +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_GSI_CH_k_CNTXT_3_ADDR(n,k),mask,val,HWIO_EE_n_GSI_CH_k_CNTXT_3_INI2(n,k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_R_BASE_ADDR_MSBS_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_R_BASE_ADDR_MSBS_SHFT 0x0 + +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_ADDR(n,k) (GSI_REG_BASE + 0x00014010 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x00014010 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x00014010 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_MAXk 27 +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_CNTXT_4_ADDR(n,k), HWIO_EE_n_GSI_CH_k_CNTXT_4_RMSK) +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_CNTXT_4_ADDR(n,k), mask) +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_GSI_CH_k_CNTXT_4_ADDR(n,k),val) +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_GSI_CH_k_CNTXT_4_ADDR(n,k),mask,val,HWIO_EE_n_GSI_CH_k_CNTXT_4_INI2(n,k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_READ_PTR_LSB_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_READ_PTR_LSB_SHFT 0x0 + +#define HWIO_EE_n_GSI_CH_k_CNTXT_5_ADDR(n,k) (GSI_REG_BASE + 0x00014014 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_5_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x00014014 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_5_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x00014014 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_5_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_5_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_CNTXT_5_MAXk 27 +#define HWIO_EE_n_GSI_CH_k_CNTXT_5_ATTR 0x1 +#define HWIO_EE_n_GSI_CH_k_CNTXT_5_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_CNTXT_5_ADDR(n,k), HWIO_EE_n_GSI_CH_k_CNTXT_5_RMSK) +#define HWIO_EE_n_GSI_CH_k_CNTXT_5_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_CNTXT_5_ADDR(n,k), mask) +#define HWIO_EE_n_GSI_CH_k_CNTXT_5_READ_PTR_MSB_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_5_READ_PTR_MSB_SHFT 0x0 + +#define HWIO_EE_n_GSI_CH_k_CNTXT_6_ADDR(n,k) (GSI_REG_BASE + 0x00014018 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_6_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x00014018 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_6_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x00014018 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_6_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_6_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_CNTXT_6_MAXk 27 +#define HWIO_EE_n_GSI_CH_k_CNTXT_6_ATTR 0x1 +#define HWIO_EE_n_GSI_CH_k_CNTXT_6_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_CNTXT_6_ADDR(n,k), HWIO_EE_n_GSI_CH_k_CNTXT_6_RMSK) +#define HWIO_EE_n_GSI_CH_k_CNTXT_6_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_CNTXT_6_ADDR(n,k), mask) +#define HWIO_EE_n_GSI_CH_k_CNTXT_6_WRITE_PTR_LSB_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_6_WRITE_PTR_LSB_SHFT 0x0 + +#define HWIO_EE_n_GSI_CH_k_CNTXT_7_ADDR(n,k) (GSI_REG_BASE + 0x0001401c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_7_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x0001401c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_7_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x0001401c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_7_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_7_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_CNTXT_7_MAXk 27 +#define HWIO_EE_n_GSI_CH_k_CNTXT_7_ATTR 0x1 +#define HWIO_EE_n_GSI_CH_k_CNTXT_7_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_CNTXT_7_ADDR(n,k), HWIO_EE_n_GSI_CH_k_CNTXT_7_RMSK) +#define HWIO_EE_n_GSI_CH_k_CNTXT_7_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_CNTXT_7_ADDR(n,k), mask) +#define HWIO_EE_n_GSI_CH_k_CNTXT_7_WRITE_PTR_MSB_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_7_WRITE_PTR_MSB_SHFT 0x0 + +#define HWIO_EE_n_GSI_CH_k_CNTXT_8_ADDR(n,k) (GSI_REG_BASE + 0x00014020 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_8_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x00014020 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_8_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x00014020 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_8_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_8_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_CNTXT_8_MAXk 27 +#define HWIO_EE_n_GSI_CH_k_CNTXT_8_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_CNTXT_8_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_CNTXT_8_ADDR(n,k), HWIO_EE_n_GSI_CH_k_CNTXT_8_RMSK) +#define HWIO_EE_n_GSI_CH_k_CNTXT_8_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_CNTXT_8_ADDR(n,k), mask) +#define HWIO_EE_n_GSI_CH_k_CNTXT_8_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_GSI_CH_k_CNTXT_8_ADDR(n,k),val) +#define HWIO_EE_n_GSI_CH_k_CNTXT_8_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_GSI_CH_k_CNTXT_8_ADDR(n,k),mask,val,HWIO_EE_n_GSI_CH_k_CNTXT_8_INI2(n,k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_8_DB_MSI_DATA_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_8_DB_MSI_DATA_SHFT 0x0 + +#define HWIO_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_ADDR(n,k) (GSI_REG_BASE + 0x00014024 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x00014024 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x00014024 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_RMSK 0xf +#define HWIO_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_MAXk 27 +#define HWIO_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_ATTR 0x1 +#define HWIO_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_ADDR(n,k), HWIO_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_RMSK) +#define HWIO_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_ADDR(n,k), mask) +#define HWIO_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_ELEM_SIZE_SHIFT_BMSK 0xf +#define HWIO_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_ELEM_SIZE_SHIFT_SHFT 0x0 +#define HWIO_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_ELEM_SIZE_SHIFT_TWO_FVAL 0x0 +#define HWIO_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_ELEM_SIZE_SHIFT_THREE_FVAL 0x1 +#define HWIO_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_ELEM_SIZE_SHIFT_FOUR_FVAL 0x2 +#define HWIO_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_ELEM_SIZE_SHIFT_FIVE_FVAL 0x3 +#define HWIO_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_ELEM_SIZE_SHIFT_SIX_FVAL 0x4 + +#define HWIO_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_ADDR(n,k) (GSI_REG_BASE + 0x00014028 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x00014028 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x00014028 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_RMSK 0xffff +#define HWIO_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_MAXk 27 +#define HWIO_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_ADDR(n,k), HWIO_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_RMSK) +#define HWIO_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_ADDR(n,k), mask) +#define HWIO_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_ADDR(n,k),val) +#define HWIO_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_ADDR(n,k),mask,val,HWIO_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_INI2(n,k)) +#define HWIO_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_CH_ALMST_EMPTY_THRSHOLD_BMSK 0xffff +#define HWIO_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_CH_ALMST_EMPTY_THRSHOLD_SHFT 0x0 + +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_ADDR(n,k) (GSI_REG_BASE + 0x00014040 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x00014040 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x00014040 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_RMSK 0xffffff +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_MAXk 27 +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_ADDR(n,k), HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_RMSK) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_ADDR(n,k), mask) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_ADDR(n,k),val) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_ADDR(n,k),mask,val,HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_INI2(n,k)) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_READ_PTR_BMSK 0xffffff +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_READ_PTR_SHFT 0x0 + +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_ADDR(n,k) (GSI_REG_BASE + 0x00014044 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x00014044 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x00014044 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_RMSK 0xffffff +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_MAXk 27 +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_ADDR(n,k), HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_RMSK) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_ADDR(n,k), mask) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_ADDR(n,k),val) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_ADDR(n,k),mask,val,HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_INI2(n,k)) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_RE_INTR_DB_BMSK 0xffffff +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_RE_INTR_DB_SHFT 0x0 + +#define HWIO_EE_n_GSI_CH_k_QOS_ADDR(n,k) (GSI_REG_BASE + 0x00014048 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_QOS_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x00014048 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_QOS_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x00014048 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_QOS_RMSK 0x3ff3f0f +#define HWIO_EE_n_GSI_CH_k_QOS_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_QOS_MAXk 27 +#define HWIO_EE_n_GSI_CH_k_QOS_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_QOS_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_QOS_ADDR(n,k), HWIO_EE_n_GSI_CH_k_QOS_RMSK) +#define HWIO_EE_n_GSI_CH_k_QOS_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_QOS_ADDR(n,k), mask) +#define HWIO_EE_n_GSI_CH_k_QOS_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_GSI_CH_k_QOS_ADDR(n,k),val) +#define HWIO_EE_n_GSI_CH_k_QOS_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_GSI_CH_k_QOS_ADDR(n,k),mask,val,HWIO_EE_n_GSI_CH_k_QOS_INI2(n,k)) +#define HWIO_EE_n_GSI_CH_k_QOS_LOW_LATENCY_EN_BMSK 0x2000000 +#define HWIO_EE_n_GSI_CH_k_QOS_LOW_LATENCY_EN_SHFT 0x19 +#define HWIO_EE_n_GSI_CH_k_QOS_DB_IN_BYTES_BMSK 0x1000000 +#define HWIO_EE_n_GSI_CH_k_QOS_DB_IN_BYTES_SHFT 0x18 +#define HWIO_EE_n_GSI_CH_k_QOS_EMPTY_LVL_THRSHOLD_BMSK 0xff0000 +#define HWIO_EE_n_GSI_CH_k_QOS_EMPTY_LVL_THRSHOLD_SHFT 0x10 +#define HWIO_EE_n_GSI_CH_k_QOS_PREFETCH_MODE_BMSK 0x3c00 +#define HWIO_EE_n_GSI_CH_k_QOS_PREFETCH_MODE_SHFT 0xa +#define HWIO_EE_n_GSI_CH_k_QOS_PREFETCH_MODE_USE_PREFETCH_BUFS_FVAL 0x0 +#define HWIO_EE_n_GSI_CH_k_QOS_PREFETCH_MODE_ESCAPE_BUF_ONLY_FVAL 0x1 +#define HWIO_EE_n_GSI_CH_k_QOS_PREFETCH_MODE_SMART_PRE_FETCH_FVAL 0x2 +#define HWIO_EE_n_GSI_CH_k_QOS_PREFETCH_MODE_FREE_PRE_FETCH_FVAL 0x3 +#define HWIO_EE_n_GSI_CH_k_QOS_USE_DB_ENG_BMSK 0x200 +#define HWIO_EE_n_GSI_CH_k_QOS_USE_DB_ENG_SHFT 0x9 +#define HWIO_EE_n_GSI_CH_k_QOS_MAX_PREFETCH_BMSK 0x100 +#define HWIO_EE_n_GSI_CH_k_QOS_MAX_PREFETCH_SHFT 0x8 +#define HWIO_EE_n_GSI_CH_k_QOS_MAX_PREFETCH_ONE_PREFETCH_SEG_FVAL 0x0 +#define HWIO_EE_n_GSI_CH_k_QOS_MAX_PREFETCH_TWO_PREFETCH_SEG_FVAL 0x1 +#define HWIO_EE_n_GSI_CH_k_QOS_WRR_WEIGHT_BMSK 0xf +#define HWIO_EE_n_GSI_CH_k_QOS_WRR_WEIGHT_SHFT 0x0 + +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_ADDR(n,k) (GSI_REG_BASE + 0x0001404c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x0001404c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x0001404c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_MAXk 27 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_SCRATCH_0_ADDR(n,k), HWIO_EE_n_GSI_CH_k_SCRATCH_0_RMSK) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_SCRATCH_0_ADDR(n,k), mask) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_GSI_CH_k_SCRATCH_0_ADDR(n,k),val) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_GSI_CH_k_SCRATCH_0_ADDR(n,k),mask,val,HWIO_EE_n_GSI_CH_k_SCRATCH_0_INI2(n,k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_SCRATCH_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_SCRATCH_SHFT 0x0 + +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_ADDR(n,k) (GSI_REG_BASE + 0x00014050 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x00014050 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x00014050 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_MAXk 27 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_SCRATCH_1_ADDR(n,k), HWIO_EE_n_GSI_CH_k_SCRATCH_1_RMSK) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_SCRATCH_1_ADDR(n,k), mask) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_GSI_CH_k_SCRATCH_1_ADDR(n,k),val) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_GSI_CH_k_SCRATCH_1_ADDR(n,k),mask,val,HWIO_EE_n_GSI_CH_k_SCRATCH_1_INI2(n,k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_SCRATCH_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_SCRATCH_SHFT 0x0 + +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_ADDR(n,k) (GSI_REG_BASE + 0x00014054 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x00014054 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x00014054 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_MAXk 27 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_SCRATCH_2_ADDR(n,k), HWIO_EE_n_GSI_CH_k_SCRATCH_2_RMSK) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_SCRATCH_2_ADDR(n,k), mask) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_GSI_CH_k_SCRATCH_2_ADDR(n,k),val) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_GSI_CH_k_SCRATCH_2_ADDR(n,k),mask,val,HWIO_EE_n_GSI_CH_k_SCRATCH_2_INI2(n,k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_SCRATCH_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_SCRATCH_SHFT 0x0 + +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_ADDR(n,k) (GSI_REG_BASE + 0x00014058 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x00014058 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x00014058 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_MAXk 27 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_SCRATCH_3_ADDR(n,k), HWIO_EE_n_GSI_CH_k_SCRATCH_3_RMSK) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_SCRATCH_3_ADDR(n,k), mask) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_GSI_CH_k_SCRATCH_3_ADDR(n,k),val) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_GSI_CH_k_SCRATCH_3_ADDR(n,k),mask,val,HWIO_EE_n_GSI_CH_k_SCRATCH_3_INI2(n,k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_SCRATCH_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_SCRATCH_SHFT 0x0 + +#define HWIO_EE_n_GSI_CH_k_SCRATCH_4_ADDR(n,k) (GSI_REG_BASE + 0x0001405c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_4_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x0001405c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_4_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x0001405c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_4_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_4_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_4_MAXk 27 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_4_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_4_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_SCRATCH_4_ADDR(n,k), HWIO_EE_n_GSI_CH_k_SCRATCH_4_RMSK) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_4_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_SCRATCH_4_ADDR(n,k), mask) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_4_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_GSI_CH_k_SCRATCH_4_ADDR(n,k),val) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_4_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_GSI_CH_k_SCRATCH_4_ADDR(n,k),mask,val,HWIO_EE_n_GSI_CH_k_SCRATCH_4_INI2(n,k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_4_SCRATCH_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_4_SCRATCH_SHFT 0x0 + +#define HWIO_EE_n_GSI_CH_k_SCRATCH_5_ADDR(n,k) (GSI_REG_BASE + 0x00014060 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_5_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x00014060 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_5_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x00014060 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_5_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_5_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_5_MAXk 27 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_5_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_5_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_SCRATCH_5_ADDR(n,k), HWIO_EE_n_GSI_CH_k_SCRATCH_5_RMSK) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_5_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_SCRATCH_5_ADDR(n,k), mask) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_5_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_GSI_CH_k_SCRATCH_5_ADDR(n,k),val) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_5_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_GSI_CH_k_SCRATCH_5_ADDR(n,k),mask,val,HWIO_EE_n_GSI_CH_k_SCRATCH_5_INI2(n,k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_5_SCRATCH_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_5_SCRATCH_SHFT 0x0 + +#define HWIO_EE_n_GSI_CH_k_SCRATCH_6_ADDR(n,k) (GSI_REG_BASE + 0x00014064 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_6_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x00014064 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_6_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x00014064 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_6_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_6_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_6_MAXk 27 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_6_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_6_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_SCRATCH_6_ADDR(n,k), HWIO_EE_n_GSI_CH_k_SCRATCH_6_RMSK) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_6_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_SCRATCH_6_ADDR(n,k), mask) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_6_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_GSI_CH_k_SCRATCH_6_ADDR(n,k),val) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_6_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_GSI_CH_k_SCRATCH_6_ADDR(n,k),mask,val,HWIO_EE_n_GSI_CH_k_SCRATCH_6_INI2(n,k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_6_SCRATCH_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_6_SCRATCH_SHFT 0x0 + +#define HWIO_EE_n_GSI_CH_k_SCRATCH_7_ADDR(n,k) (GSI_REG_BASE + 0x00014068 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_7_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x00014068 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_7_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x00014068 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_7_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_7_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_7_MAXk 27 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_7_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_7_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_SCRATCH_7_ADDR(n,k), HWIO_EE_n_GSI_CH_k_SCRATCH_7_RMSK) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_7_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_SCRATCH_7_ADDR(n,k), mask) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_7_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_GSI_CH_k_SCRATCH_7_ADDR(n,k),val) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_7_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_GSI_CH_k_SCRATCH_7_ADDR(n,k),mask,val,HWIO_EE_n_GSI_CH_k_SCRATCH_7_INI2(n,k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_7_SCRATCH_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_7_SCRATCH_SHFT 0x0 + +#define HWIO_EE_n_GSI_CH_k_SCRATCH_8_ADDR(n,k) (GSI_REG_BASE + 0x0001406c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_8_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x0001406c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_8_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x0001406c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_8_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_8_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_8_MAXk 27 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_8_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_8_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_SCRATCH_8_ADDR(n,k), HWIO_EE_n_GSI_CH_k_SCRATCH_8_RMSK) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_8_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_SCRATCH_8_ADDR(n,k), mask) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_8_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_GSI_CH_k_SCRATCH_8_ADDR(n,k),val) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_8_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_GSI_CH_k_SCRATCH_8_ADDR(n,k),mask,val,HWIO_EE_n_GSI_CH_k_SCRATCH_8_INI2(n,k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_8_SCRATCH_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_8_SCRATCH_SHFT 0x0 + +#define HWIO_EE_n_GSI_CH_k_SCRATCH_9_ADDR(n,k) (GSI_REG_BASE + 0x00014070 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_9_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x00014070 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_9_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x00014070 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_9_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_9_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_9_MAXk 27 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_9_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_9_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_SCRATCH_9_ADDR(n,k), HWIO_EE_n_GSI_CH_k_SCRATCH_9_RMSK) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_9_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_SCRATCH_9_ADDR(n,k), mask) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_9_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_GSI_CH_k_SCRATCH_9_ADDR(n,k),val) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_9_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_GSI_CH_k_SCRATCH_9_ADDR(n,k),mask,val,HWIO_EE_n_GSI_CH_k_SCRATCH_9_INI2(n,k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_9_SCRATCH_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_9_SCRATCH_SHFT 0x0 + +#define HWIO_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_ADDR(n,k) (GSI_REG_BASE + 0x00014074 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x00014074 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x00014074 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_RMSK 0xffff +#define HWIO_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_MAXk 27 +#define HWIO_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_ADDR(n,k), HWIO_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_RMSK) +#define HWIO_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_ADDR(n,k), mask) +#define HWIO_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_ADDR(n,k),val) +#define HWIO_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_ADDR(n,k),mask,val,HWIO_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_INI2(n,k)) +#define HWIO_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_LAST_DB_2_MCS_BMSK 0xffff +#define HWIO_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_LAST_DB_2_MCS_SHFT 0x0 + +#define HWIO_EE_n_EV_CH_k_CNTXT_0_ADDR(n,k) (GSI_REG_BASE + 0x0001c000 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_0_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x0001c000 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_0_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x0001c000 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_0_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_0_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_MAXk 26 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_CNTXT_0_ADDR(n,k), HWIO_EE_n_EV_CH_k_CNTXT_0_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_0_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_CNTXT_0_ADDR(n,k), mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_0_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_EV_CH_k_CNTXT_0_ADDR(n,k),val) +#define HWIO_EE_n_EV_CH_k_CNTXT_0_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_EV_CH_k_CNTXT_0_ADDR(n,k),mask,val,HWIO_EE_n_EV_CH_k_CNTXT_0_INI2(n,k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_0_ELEMENT_SIZE_BMSK 0xff000000 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_ELEMENT_SIZE_SHFT 0x18 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_CHSTATE_BMSK 0xf00000 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_CHSTATE_SHFT 0x14 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_CHSTATE_NOT_ALLOCATED_FVAL 0x0 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_CHSTATE_ALLOCATED_FVAL 0x1 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_EE_BMSK 0xf0000 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_EE_SHFT 0x10 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_EVCHID_BMSK 0xff00 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_EVCHID_SHFT 0x8 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_INTYPE_BMSK 0x80 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_INTYPE_SHFT 0x7 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_INTYPE_MSI_FVAL 0x0 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_INTYPE_IRQ_FVAL 0x1 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_CHTYPE_BMSK 0x7f +#define HWIO_EE_n_EV_CH_k_CNTXT_0_CHTYPE_SHFT 0x0 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_CHTYPE_MHI_EV_FVAL 0x0 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_CHTYPE_XHCI_EV_FVAL 0x1 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_CHTYPE_GPI_EV_FVAL 0x2 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_CHTYPE_XDCI_FVAL 0x3 + +#define HWIO_EE_n_EV_CH_k_CNTXT_1_ADDR(n,k) (GSI_REG_BASE + 0x0001c004 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_1_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x0001c004 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_1_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x0001c004 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_1_RMSK 0xffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_1_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_1_MAXk 26 +#define HWIO_EE_n_EV_CH_k_CNTXT_1_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_CNTXT_1_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_CNTXT_1_ADDR(n,k), HWIO_EE_n_EV_CH_k_CNTXT_1_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_1_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_CNTXT_1_ADDR(n,k), mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_1_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_EV_CH_k_CNTXT_1_ADDR(n,k),val) +#define HWIO_EE_n_EV_CH_k_CNTXT_1_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_EV_CH_k_CNTXT_1_ADDR(n,k),mask,val,HWIO_EE_n_EV_CH_k_CNTXT_1_INI2(n,k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_1_R_LENGTH_BMSK 0xffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_1_R_LENGTH_SHFT 0x0 + +#define HWIO_EE_n_EV_CH_k_CNTXT_2_ADDR(n,k) (GSI_REG_BASE + 0x0001c008 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_2_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x0001c008 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_2_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x0001c008 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_2_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_2_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_2_MAXk 26 +#define HWIO_EE_n_EV_CH_k_CNTXT_2_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_CNTXT_2_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_CNTXT_2_ADDR(n,k), HWIO_EE_n_EV_CH_k_CNTXT_2_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_2_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_CNTXT_2_ADDR(n,k), mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_2_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_EV_CH_k_CNTXT_2_ADDR(n,k),val) +#define HWIO_EE_n_EV_CH_k_CNTXT_2_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_EV_CH_k_CNTXT_2_ADDR(n,k),mask,val,HWIO_EE_n_EV_CH_k_CNTXT_2_INI2(n,k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_2_R_BASE_ADDR_LSBS_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_2_R_BASE_ADDR_LSBS_SHFT 0x0 + +#define HWIO_EE_n_EV_CH_k_CNTXT_3_ADDR(n,k) (GSI_REG_BASE + 0x0001c00c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_3_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x0001c00c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_3_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x0001c00c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_3_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_3_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_3_MAXk 26 +#define HWIO_EE_n_EV_CH_k_CNTXT_3_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_CNTXT_3_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_CNTXT_3_ADDR(n,k), HWIO_EE_n_EV_CH_k_CNTXT_3_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_3_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_CNTXT_3_ADDR(n,k), mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_3_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_EV_CH_k_CNTXT_3_ADDR(n,k),val) +#define HWIO_EE_n_EV_CH_k_CNTXT_3_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_EV_CH_k_CNTXT_3_ADDR(n,k),mask,val,HWIO_EE_n_EV_CH_k_CNTXT_3_INI2(n,k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_3_R_BASE_ADDR_MSBS_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_3_R_BASE_ADDR_MSBS_SHFT 0x0 + +#define HWIO_EE_n_EV_CH_k_CNTXT_4_ADDR(n,k) (GSI_REG_BASE + 0x0001c010 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_4_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x0001c010 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_4_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x0001c010 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_4_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_4_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_4_MAXk 26 +#define HWIO_EE_n_EV_CH_k_CNTXT_4_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_CNTXT_4_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_CNTXT_4_ADDR(n,k), HWIO_EE_n_EV_CH_k_CNTXT_4_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_4_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_CNTXT_4_ADDR(n,k), mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_4_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_EV_CH_k_CNTXT_4_ADDR(n,k),val) +#define HWIO_EE_n_EV_CH_k_CNTXT_4_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_EV_CH_k_CNTXT_4_ADDR(n,k),mask,val,HWIO_EE_n_EV_CH_k_CNTXT_4_INI2(n,k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_4_READ_PTR_LSB_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_4_READ_PTR_LSB_SHFT 0x0 + +#define HWIO_EE_n_EV_CH_k_CNTXT_5_ADDR(n,k) (GSI_REG_BASE + 0x0001c014 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_5_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x0001c014 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_5_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x0001c014 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_5_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_5_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_5_MAXk 26 +#define HWIO_EE_n_EV_CH_k_CNTXT_5_ATTR 0x1 +#define HWIO_EE_n_EV_CH_k_CNTXT_5_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_CNTXT_5_ADDR(n,k), HWIO_EE_n_EV_CH_k_CNTXT_5_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_5_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_CNTXT_5_ADDR(n,k), mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_5_READ_PTR_MSB_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_5_READ_PTR_MSB_SHFT 0x0 + +#define HWIO_EE_n_EV_CH_k_CNTXT_6_ADDR(n,k) (GSI_REG_BASE + 0x0001c018 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_6_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x0001c018 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_6_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x0001c018 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_6_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_6_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_6_MAXk 26 +#define HWIO_EE_n_EV_CH_k_CNTXT_6_ATTR 0x1 +#define HWIO_EE_n_EV_CH_k_CNTXT_6_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_CNTXT_6_ADDR(n,k), HWIO_EE_n_EV_CH_k_CNTXT_6_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_6_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_CNTXT_6_ADDR(n,k), mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_6_WRITE_PTR_LSB_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_6_WRITE_PTR_LSB_SHFT 0x0 + +#define HWIO_EE_n_EV_CH_k_CNTXT_7_ADDR(n,k) (GSI_REG_BASE + 0x0001c01c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_7_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x0001c01c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_7_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x0001c01c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_7_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_7_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_7_MAXk 26 +#define HWIO_EE_n_EV_CH_k_CNTXT_7_ATTR 0x1 +#define HWIO_EE_n_EV_CH_k_CNTXT_7_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_CNTXT_7_ADDR(n,k), HWIO_EE_n_EV_CH_k_CNTXT_7_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_7_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_CNTXT_7_ADDR(n,k), mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_7_WRITE_PTR_MSB_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_7_WRITE_PTR_MSB_SHFT 0x0 + +#define HWIO_EE_n_EV_CH_k_CNTXT_8_ADDR(n,k) (GSI_REG_BASE + 0x0001c020 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_8_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x0001c020 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_8_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x0001c020 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_8_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_8_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_8_MAXk 26 +#define HWIO_EE_n_EV_CH_k_CNTXT_8_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_CNTXT_8_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_CNTXT_8_ADDR(n,k), HWIO_EE_n_EV_CH_k_CNTXT_8_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_8_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_CNTXT_8_ADDR(n,k), mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_8_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_EV_CH_k_CNTXT_8_ADDR(n,k),val) +#define HWIO_EE_n_EV_CH_k_CNTXT_8_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_EV_CH_k_CNTXT_8_ADDR(n,k),mask,val,HWIO_EE_n_EV_CH_k_CNTXT_8_INI2(n,k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_8_INT_MOD_CNT_BMSK 0xff000000 +#define HWIO_EE_n_EV_CH_k_CNTXT_8_INT_MOD_CNT_SHFT 0x18 +#define HWIO_EE_n_EV_CH_k_CNTXT_8_INT_MODC_BMSK 0xff0000 +#define HWIO_EE_n_EV_CH_k_CNTXT_8_INT_MODC_SHFT 0x10 +#define HWIO_EE_n_EV_CH_k_CNTXT_8_INT_MODT_BMSK 0xffff +#define HWIO_EE_n_EV_CH_k_CNTXT_8_INT_MODT_SHFT 0x0 + +#define HWIO_EE_n_EV_CH_k_CNTXT_9_ADDR(n,k) (GSI_REG_BASE + 0x0001c024 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_9_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x0001c024 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_9_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x0001c024 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_9_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_9_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_9_MAXk 26 +#define HWIO_EE_n_EV_CH_k_CNTXT_9_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_CNTXT_9_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_CNTXT_9_ADDR(n,k), HWIO_EE_n_EV_CH_k_CNTXT_9_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_9_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_CNTXT_9_ADDR(n,k), mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_9_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_EV_CH_k_CNTXT_9_ADDR(n,k),val) +#define HWIO_EE_n_EV_CH_k_CNTXT_9_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_EV_CH_k_CNTXT_9_ADDR(n,k),mask,val,HWIO_EE_n_EV_CH_k_CNTXT_9_INI2(n,k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_9_INTVEC_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_9_INTVEC_SHFT 0x0 + +#define HWIO_EE_n_EV_CH_k_CNTXT_10_ADDR(n,k) (GSI_REG_BASE + 0x0001c028 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_10_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x0001c028 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_10_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x0001c028 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_10_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_10_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_10_MAXk 26 +#define HWIO_EE_n_EV_CH_k_CNTXT_10_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_CNTXT_10_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_CNTXT_10_ADDR(n,k), HWIO_EE_n_EV_CH_k_CNTXT_10_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_10_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_CNTXT_10_ADDR(n,k), mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_10_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_EV_CH_k_CNTXT_10_ADDR(n,k),val) +#define HWIO_EE_n_EV_CH_k_CNTXT_10_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_EV_CH_k_CNTXT_10_ADDR(n,k),mask,val,HWIO_EE_n_EV_CH_k_CNTXT_10_INI2(n,k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_10_MSI_ADDR_LSB_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_10_MSI_ADDR_LSB_SHFT 0x0 + +#define HWIO_EE_n_EV_CH_k_CNTXT_11_ADDR(n,k) (GSI_REG_BASE + 0x0001c02c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_11_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x0001c02c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_11_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x0001c02c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_11_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_11_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_11_MAXk 26 +#define HWIO_EE_n_EV_CH_k_CNTXT_11_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_CNTXT_11_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_CNTXT_11_ADDR(n,k), HWIO_EE_n_EV_CH_k_CNTXT_11_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_11_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_CNTXT_11_ADDR(n,k), mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_11_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_EV_CH_k_CNTXT_11_ADDR(n,k),val) +#define HWIO_EE_n_EV_CH_k_CNTXT_11_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_EV_CH_k_CNTXT_11_ADDR(n,k),mask,val,HWIO_EE_n_EV_CH_k_CNTXT_11_INI2(n,k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_11_MSI_ADDR_MSB_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_11_MSI_ADDR_MSB_SHFT 0x0 + +#define HWIO_EE_n_EV_CH_k_CNTXT_12_ADDR(n,k) (GSI_REG_BASE + 0x0001c030 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_12_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x0001c030 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_12_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x0001c030 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_12_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_12_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_12_MAXk 26 +#define HWIO_EE_n_EV_CH_k_CNTXT_12_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_CNTXT_12_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_CNTXT_12_ADDR(n,k), HWIO_EE_n_EV_CH_k_CNTXT_12_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_12_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_CNTXT_12_ADDR(n,k), mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_12_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_EV_CH_k_CNTXT_12_ADDR(n,k),val) +#define HWIO_EE_n_EV_CH_k_CNTXT_12_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_EV_CH_k_CNTXT_12_ADDR(n,k),mask,val,HWIO_EE_n_EV_CH_k_CNTXT_12_INI2(n,k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_12_RP_UPDATE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_12_RP_UPDATE_ADDR_LSB_SHFT 0x0 + +#define HWIO_EE_n_EV_CH_k_CNTXT_13_ADDR(n,k) (GSI_REG_BASE + 0x0001c034 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_13_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x0001c034 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_13_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x0001c034 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_13_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_13_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_13_MAXk 26 +#define HWIO_EE_n_EV_CH_k_CNTXT_13_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_CNTXT_13_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_CNTXT_13_ADDR(n,k), HWIO_EE_n_EV_CH_k_CNTXT_13_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_13_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_CNTXT_13_ADDR(n,k), mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_13_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_EV_CH_k_CNTXT_13_ADDR(n,k),val) +#define HWIO_EE_n_EV_CH_k_CNTXT_13_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_EV_CH_k_CNTXT_13_ADDR(n,k),mask,val,HWIO_EE_n_EV_CH_k_CNTXT_13_INI2(n,k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_13_RP_UPDATE_ADDR_MSB_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_13_RP_UPDATE_ADDR_MSB_SHFT 0x0 + +#define HWIO_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_ADDR(n,k) (GSI_REG_BASE + 0x0001c038 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x0001c038 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x0001c038 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_RMSK 0xf +#define HWIO_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_MAXn 2 +#define HWIO_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_MAXk 26 +#define HWIO_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_ATTR 0x1 +#define HWIO_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_ADDR(n,k), HWIO_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_RMSK) +#define HWIO_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_ADDR(n,k), mask) +#define HWIO_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_ELEM_SIZE_SHIFT_BMSK 0xf +#define HWIO_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_ELEM_SIZE_SHIFT_SHFT 0x0 +#define HWIO_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_ELEM_SIZE_SHIFT_TWO_FVAL 0x0 +#define HWIO_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_ELEM_SIZE_SHIFT_THREE_FVAL 0x1 +#define HWIO_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_ELEM_SIZE_SHIFT_FOUR_FVAL 0x2 +#define HWIO_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_ELEM_SIZE_SHIFT_FIVE_FVAL 0x3 +#define HWIO_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_ELEM_SIZE_SHIFT_SIX_FVAL 0x4 + +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_ADDR(n,k) (GSI_REG_BASE + 0x0001c048 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x0001c048 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x0001c048 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_MAXn 2 +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_MAXk 26 +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_SCRATCH_0_ADDR(n,k), HWIO_EE_n_EV_CH_k_SCRATCH_0_RMSK) +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_SCRATCH_0_ADDR(n,k), mask) +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_EV_CH_k_SCRATCH_0_ADDR(n,k),val) +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_EV_CH_k_SCRATCH_0_ADDR(n,k),mask,val,HWIO_EE_n_EV_CH_k_SCRATCH_0_INI2(n,k)) +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_SCRATCH_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_SCRATCH_SHFT 0x0 + +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_ADDR(n,k) (GSI_REG_BASE + 0x0001c04c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x0001c04c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x0001c04c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_MAXn 2 +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_MAXk 26 +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_SCRATCH_1_ADDR(n,k), HWIO_EE_n_EV_CH_k_SCRATCH_1_RMSK) +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_SCRATCH_1_ADDR(n,k), mask) +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_EV_CH_k_SCRATCH_1_ADDR(n,k),val) +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_EV_CH_k_SCRATCH_1_ADDR(n,k),mask,val,HWIO_EE_n_EV_CH_k_SCRATCH_1_INI2(n,k)) +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_SCRATCH_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_SCRATCH_SHFT 0x0 + +#define HWIO_EE_n_EV_CH_k_SCRATCH_2_ADDR(n,k) (GSI_REG_BASE + 0x0001c050 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_SCRATCH_2_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x0001c050 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_SCRATCH_2_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x0001c050 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_SCRATCH_2_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_SCRATCH_2_MAXn 2 +#define HWIO_EE_n_EV_CH_k_SCRATCH_2_MAXk 26 +#define HWIO_EE_n_EV_CH_k_SCRATCH_2_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_SCRATCH_2_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_SCRATCH_2_ADDR(n,k), HWIO_EE_n_EV_CH_k_SCRATCH_2_RMSK) +#define HWIO_EE_n_EV_CH_k_SCRATCH_2_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_SCRATCH_2_ADDR(n,k), mask) +#define HWIO_EE_n_EV_CH_k_SCRATCH_2_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_EV_CH_k_SCRATCH_2_ADDR(n,k),val) +#define HWIO_EE_n_EV_CH_k_SCRATCH_2_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_EV_CH_k_SCRATCH_2_ADDR(n,k),mask,val,HWIO_EE_n_EV_CH_k_SCRATCH_2_INI2(n,k)) +#define HWIO_EE_n_EV_CH_k_SCRATCH_2_SCRATCH_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_SCRATCH_2_SCRATCH_SHFT 0x0 + +#define HWIO_EE_n_GSI_CH_k_DOORBELL_0_ADDR(n,k) (GSI_REG_BASE + 0x00024000 + 0x12000 * (n) + 0x8 * (k)) +#define HWIO_EE_n_GSI_CH_k_DOORBELL_0_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x00024000 + 0x12000 * (n) + 0x8 * (k)) +#define HWIO_EE_n_GSI_CH_k_DOORBELL_0_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x00024000 + 0x12000 * (n) + 0x8 * (k)) +#define HWIO_EE_n_GSI_CH_k_DOORBELL_0_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_DOORBELL_0_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_DOORBELL_0_MAXk 27 +#define HWIO_EE_n_GSI_CH_k_DOORBELL_0_ATTR 0x2 +#define HWIO_EE_n_GSI_CH_k_DOORBELL_0_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_GSI_CH_k_DOORBELL_0_ADDR(n,k),val) +#define HWIO_EE_n_GSI_CH_k_DOORBELL_0_WRITE_PTR_LSB_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_DOORBELL_0_WRITE_PTR_LSB_SHFT 0x0 + +#define HWIO_EE_n_GSI_CH_k_DOORBELL_1_ADDR(n,k) (GSI_REG_BASE + 0x00024004 + 0x12000 * (n) + 0x8 * (k)) +#define HWIO_EE_n_GSI_CH_k_DOORBELL_1_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x00024004 + 0x12000 * (n) + 0x8 * (k)) +#define HWIO_EE_n_GSI_CH_k_DOORBELL_1_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x00024004 + 0x12000 * (n) + 0x8 * (k)) +#define HWIO_EE_n_GSI_CH_k_DOORBELL_1_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_DOORBELL_1_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_DOORBELL_1_MAXk 27 +#define HWIO_EE_n_GSI_CH_k_DOORBELL_1_ATTR 0x2 +#define HWIO_EE_n_GSI_CH_k_DOORBELL_1_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_GSI_CH_k_DOORBELL_1_ADDR(n,k),val) +#define HWIO_EE_n_GSI_CH_k_DOORBELL_1_WRITE_PTR_MSB_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_DOORBELL_1_WRITE_PTR_MSB_SHFT 0x0 + +#define HWIO_EE_n_EV_CH_k_DOORBELL_0_ADDR(n,k) (GSI_REG_BASE + 0x00024800 + 0x12000 * (n) + 0x8 * (k)) +#define HWIO_EE_n_EV_CH_k_DOORBELL_0_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x00024800 + 0x12000 * (n) + 0x8 * (k)) +#define HWIO_EE_n_EV_CH_k_DOORBELL_0_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x00024800 + 0x12000 * (n) + 0x8 * (k)) +#define HWIO_EE_n_EV_CH_k_DOORBELL_0_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_DOORBELL_0_MAXn 2 +#define HWIO_EE_n_EV_CH_k_DOORBELL_0_MAXk 26 +#define HWIO_EE_n_EV_CH_k_DOORBELL_0_ATTR 0x2 +#define HWIO_EE_n_EV_CH_k_DOORBELL_0_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_EV_CH_k_DOORBELL_0_ADDR(n,k),val) +#define HWIO_EE_n_EV_CH_k_DOORBELL_0_WRITE_PTR_LSB_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_DOORBELL_0_WRITE_PTR_LSB_SHFT 0x0 + +#define HWIO_EE_n_EV_CH_k_DOORBELL_1_ADDR(n,k) (GSI_REG_BASE + 0x00024804 + 0x12000 * (n) + 0x8 * (k)) +#define HWIO_EE_n_EV_CH_k_DOORBELL_1_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x00024804 + 0x12000 * (n) + 0x8 * (k)) +#define HWIO_EE_n_EV_CH_k_DOORBELL_1_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x00024804 + 0x12000 * (n) + 0x8 * (k)) +#define HWIO_EE_n_EV_CH_k_DOORBELL_1_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_DOORBELL_1_MAXn 2 +#define HWIO_EE_n_EV_CH_k_DOORBELL_1_MAXk 26 +#define HWIO_EE_n_EV_CH_k_DOORBELL_1_ATTR 0x2 +#define HWIO_EE_n_EV_CH_k_DOORBELL_1_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_EV_CH_k_DOORBELL_1_ADDR(n,k),val) +#define HWIO_EE_n_EV_CH_k_DOORBELL_1_WRITE_PTR_MSB_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_DOORBELL_1_WRITE_PTR_MSB_SHFT 0x0 + +#define HWIO_EE_n_GSI_STATUS_ADDR(n) (GSI_REG_BASE + 0x00025000 + 0x12000 * (n)) +#define HWIO_EE_n_GSI_STATUS_PHYS(n) (GSI_REG_BASE_PHYS + 0x00025000 + 0x12000 * (n)) +#define HWIO_EE_n_GSI_STATUS_OFFS(n) (GSI_REG_BASE_OFFS + 0x00025000 + 0x12000 * (n)) +#define HWIO_EE_n_GSI_STATUS_RMSK 0x1 +#define HWIO_EE_n_GSI_STATUS_MAXn 2 +#define HWIO_EE_n_GSI_STATUS_ATTR 0x1 +#define HWIO_EE_n_GSI_STATUS_INI(n) \ + in_dword_masked(HWIO_EE_n_GSI_STATUS_ADDR(n), HWIO_EE_n_GSI_STATUS_RMSK) +#define HWIO_EE_n_GSI_STATUS_INMI(n,mask) \ + in_dword_masked(HWIO_EE_n_GSI_STATUS_ADDR(n), mask) +#define HWIO_EE_n_GSI_STATUS_ENABLED_BMSK 0x1 +#define HWIO_EE_n_GSI_STATUS_ENABLED_SHFT 0x0 + +#define HWIO_EE_n_GSI_CH_CMD_ADDR(n) (GSI_REG_BASE + 0x00025008 + 0x12000 * (n)) +#define HWIO_EE_n_GSI_CH_CMD_PHYS(n) (GSI_REG_BASE_PHYS + 0x00025008 + 0x12000 * (n)) +#define HWIO_EE_n_GSI_CH_CMD_OFFS(n) (GSI_REG_BASE_OFFS + 0x00025008 + 0x12000 * (n)) +#define HWIO_EE_n_GSI_CH_CMD_RMSK 0xff0000ff +#define HWIO_EE_n_GSI_CH_CMD_MAXn 2 +#define HWIO_EE_n_GSI_CH_CMD_ATTR 0x2 +#define HWIO_EE_n_GSI_CH_CMD_OUTI(n,val) \ + out_dword(HWIO_EE_n_GSI_CH_CMD_ADDR(n),val) +#define HWIO_EE_n_GSI_CH_CMD_OPCODE_BMSK 0xff000000 +#define HWIO_EE_n_GSI_CH_CMD_OPCODE_SHFT 0x18 +#define HWIO_EE_n_GSI_CH_CMD_OPCODE_ALLOCATE_FVAL 0x0 +#define HWIO_EE_n_GSI_CH_CMD_OPCODE_START_FVAL 0x1 +#define HWIO_EE_n_GSI_CH_CMD_OPCODE_STOP_FVAL 0x2 +#define HWIO_EE_n_GSI_CH_CMD_OPCODE_RESET_FVAL 0x9 +#define HWIO_EE_n_GSI_CH_CMD_OPCODE_DE_ALLOC_FVAL 0xa +#define HWIO_EE_n_GSI_CH_CMD_OPCODE_DB_STOP_FVAL 0xb +#define HWIO_EE_n_GSI_CH_CMD_CHID_BMSK 0xff +#define HWIO_EE_n_GSI_CH_CMD_CHID_SHFT 0x0 + +#define HWIO_EE_n_EV_CH_CMD_ADDR(n) (GSI_REG_BASE + 0x00025010 + 0x12000 * (n)) +#define HWIO_EE_n_EV_CH_CMD_PHYS(n) (GSI_REG_BASE_PHYS + 0x00025010 + 0x12000 * (n)) +#define HWIO_EE_n_EV_CH_CMD_OFFS(n) (GSI_REG_BASE_OFFS + 0x00025010 + 0x12000 * (n)) +#define HWIO_EE_n_EV_CH_CMD_RMSK 0xff0000ff +#define HWIO_EE_n_EV_CH_CMD_MAXn 2 +#define HWIO_EE_n_EV_CH_CMD_ATTR 0x2 +#define HWIO_EE_n_EV_CH_CMD_OUTI(n,val) \ + out_dword(HWIO_EE_n_EV_CH_CMD_ADDR(n),val) +#define HWIO_EE_n_EV_CH_CMD_OPCODE_BMSK 0xff000000 +#define HWIO_EE_n_EV_CH_CMD_OPCODE_SHFT 0x18 +#define HWIO_EE_n_EV_CH_CMD_OPCODE_ALLOCATE_FVAL 0x0 +#define HWIO_EE_n_EV_CH_CMD_OPCODE_RESET_FVAL 0x9 +#define HWIO_EE_n_EV_CH_CMD_OPCODE_DE_ALLOC_FVAL 0xa +#define HWIO_EE_n_EV_CH_CMD_CHID_BMSK 0xff +#define HWIO_EE_n_EV_CH_CMD_CHID_SHFT 0x0 + +#define HWIO_EE_n_GSI_EE_GENERIC_CMD_ADDR(n) (GSI_REG_BASE + 0x00025018 + 0x12000 * (n)) +#define HWIO_EE_n_GSI_EE_GENERIC_CMD_PHYS(n) (GSI_REG_BASE_PHYS + 0x00025018 + 0x12000 * (n)) +#define HWIO_EE_n_GSI_EE_GENERIC_CMD_OFFS(n) (GSI_REG_BASE_OFFS + 0x00025018 + 0x12000 * (n)) +#define HWIO_EE_n_GSI_EE_GENERIC_CMD_RMSK 0xffffffff +#define HWIO_EE_n_GSI_EE_GENERIC_CMD_MAXn 2 +#define HWIO_EE_n_GSI_EE_GENERIC_CMD_ATTR 0x2 +#define HWIO_EE_n_GSI_EE_GENERIC_CMD_OUTI(n,val) \ + out_dword(HWIO_EE_n_GSI_EE_GENERIC_CMD_ADDR(n),val) +#define HWIO_EE_n_GSI_EE_GENERIC_CMD_OPCODE_BMSK 0xffffffff +#define HWIO_EE_n_GSI_EE_GENERIC_CMD_OPCODE_SHFT 0x0 + +#define HWIO_EE_n_GSI_HW_PARAM_0_ADDR(n) (GSI_REG_BASE + 0x00025038 + 0x12000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_0_PHYS(n) (GSI_REG_BASE_PHYS + 0x00025038 + 0x12000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_0_OFFS(n) (GSI_REG_BASE_OFFS + 0x00025038 + 0x12000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_0_RMSK 0xffffffff +#define HWIO_EE_n_GSI_HW_PARAM_0_MAXn 2 +#define HWIO_EE_n_GSI_HW_PARAM_0_ATTR 0x1 +#define HWIO_EE_n_GSI_HW_PARAM_0_INI(n) \ + in_dword_masked(HWIO_EE_n_GSI_HW_PARAM_0_ADDR(n), HWIO_EE_n_GSI_HW_PARAM_0_RMSK) +#define HWIO_EE_n_GSI_HW_PARAM_0_INMI(n,mask) \ + in_dword_masked(HWIO_EE_n_GSI_HW_PARAM_0_ADDR(n), mask) +#define HWIO_EE_n_GSI_HW_PARAM_0_USE_AXI_M_BMSK 0x80000000 +#define HWIO_EE_n_GSI_HW_PARAM_0_USE_AXI_M_SHFT 0x1f +#define HWIO_EE_n_GSI_HW_PARAM_0_PERIPH_SEC_GRP_BMSK 0x7c000000 +#define HWIO_EE_n_GSI_HW_PARAM_0_PERIPH_SEC_GRP_SHFT 0x1a +#define HWIO_EE_n_GSI_HW_PARAM_0_PERIPH_CONF_ADDR_BUS_W_BMSK 0x3e00000 +#define HWIO_EE_n_GSI_HW_PARAM_0_PERIPH_CONF_ADDR_BUS_W_SHFT 0x15 +#define HWIO_EE_n_GSI_HW_PARAM_0_NUM_EES_BMSK 0x1f0000 +#define HWIO_EE_n_GSI_HW_PARAM_0_NUM_EES_SHFT 0x10 +#define HWIO_EE_n_GSI_HW_PARAM_0_GSI_CH_NUM_BMSK 0xff00 +#define HWIO_EE_n_GSI_HW_PARAM_0_GSI_CH_NUM_SHFT 0x8 +#define HWIO_EE_n_GSI_HW_PARAM_0_GSI_EV_CH_NUM_BMSK 0xff +#define HWIO_EE_n_GSI_HW_PARAM_0_GSI_EV_CH_NUM_SHFT 0x0 + +#define HWIO_EE_n_GSI_HW_PARAM_1_ADDR(n) (GSI_REG_BASE + 0x0002503c + 0x12000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_1_PHYS(n) (GSI_REG_BASE_PHYS + 0x0002503c + 0x12000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_1_OFFS(n) (GSI_REG_BASE_OFFS + 0x0002503c + 0x12000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_1_RMSK 0xffffffff +#define HWIO_EE_n_GSI_HW_PARAM_1_MAXn 2 +#define HWIO_EE_n_GSI_HW_PARAM_1_ATTR 0x1 +#define HWIO_EE_n_GSI_HW_PARAM_1_INI(n) \ + in_dword_masked(HWIO_EE_n_GSI_HW_PARAM_1_ADDR(n), HWIO_EE_n_GSI_HW_PARAM_1_RMSK) +#define HWIO_EE_n_GSI_HW_PARAM_1_INMI(n,mask) \ + in_dword_masked(HWIO_EE_n_GSI_HW_PARAM_1_ADDR(n), mask) +#define HWIO_EE_n_GSI_HW_PARAM_1_GSI_BLK_INT_ACCESS_REGION_2_EN_BMSK 0x80000000 +#define HWIO_EE_n_GSI_HW_PARAM_1_GSI_BLK_INT_ACCESS_REGION_2_EN_SHFT 0x1f +#define HWIO_EE_n_GSI_HW_PARAM_1_GSI_BLK_INT_ACCESS_REGION_1_EN_BMSK 0x40000000 +#define HWIO_EE_n_GSI_HW_PARAM_1_GSI_BLK_INT_ACCESS_REGION_1_EN_SHFT 0x1e +#define HWIO_EE_n_GSI_HW_PARAM_1_GSI_SIMPLE_RD_WR_BMSK 0x20000000 +#define HWIO_EE_n_GSI_HW_PARAM_1_GSI_SIMPLE_RD_WR_SHFT 0x1d +#define HWIO_EE_n_GSI_HW_PARAM_1_GSI_ESCAPE_BUF_ONLY_BMSK 0x10000000 +#define HWIO_EE_n_GSI_HW_PARAM_1_GSI_ESCAPE_BUF_ONLY_SHFT 0x1c +#define HWIO_EE_n_GSI_HW_PARAM_1_GSI_USE_UC_IF_BMSK 0x8000000 +#define HWIO_EE_n_GSI_HW_PARAM_1_GSI_USE_UC_IF_SHFT 0x1b +#define HWIO_EE_n_GSI_HW_PARAM_1_GSI_USE_DB_ENG_BMSK 0x4000000 +#define HWIO_EE_n_GSI_HW_PARAM_1_GSI_USE_DB_ENG_SHFT 0x1a +#define HWIO_EE_n_GSI_HW_PARAM_1_GSI_USE_BP_MTRIX_BMSK 0x2000000 +#define HWIO_EE_n_GSI_HW_PARAM_1_GSI_USE_BP_MTRIX_SHFT 0x19 +#define HWIO_EE_n_GSI_HW_PARAM_1_GSI_NUM_TIMERS_BMSK 0x1f00000 +#define HWIO_EE_n_GSI_HW_PARAM_1_GSI_NUM_TIMERS_SHFT 0x14 +#define HWIO_EE_n_GSI_HW_PARAM_1_GSI_USE_XPU_BMSK 0x80000 +#define HWIO_EE_n_GSI_HW_PARAM_1_GSI_USE_XPU_SHFT 0x13 +#define HWIO_EE_n_GSI_HW_PARAM_1_GSI_QRIB_EN_BMSK 0x40000 +#define HWIO_EE_n_GSI_HW_PARAM_1_GSI_QRIB_EN_SHFT 0x12 +#define HWIO_EE_n_GSI_HW_PARAM_1_GSI_VMIDACR_EN_BMSK 0x20000 +#define HWIO_EE_n_GSI_HW_PARAM_1_GSI_VMIDACR_EN_SHFT 0x11 +#define HWIO_EE_n_GSI_HW_PARAM_1_GSI_SEC_EN_BMSK 0x10000 +#define HWIO_EE_n_GSI_HW_PARAM_1_GSI_SEC_EN_SHFT 0x10 +#define HWIO_EE_n_GSI_HW_PARAM_1_GSI_NONSEC_EN_BMSK 0xf000 +#define HWIO_EE_n_GSI_HW_PARAM_1_GSI_NONSEC_EN_SHFT 0xc +#define HWIO_EE_n_GSI_HW_PARAM_1_GSI_NUM_QAD_BMSK 0xf00 +#define HWIO_EE_n_GSI_HW_PARAM_1_GSI_NUM_QAD_SHFT 0x8 +#define HWIO_EE_n_GSI_HW_PARAM_1_GSI_M_DATA_BUS_W_BMSK 0xff +#define HWIO_EE_n_GSI_HW_PARAM_1_GSI_M_DATA_BUS_W_SHFT 0x0 + +#define HWIO_EE_n_GSI_HW_PARAM_2_ADDR(n) (GSI_REG_BASE + 0x00025040 + 0x12000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_2_PHYS(n) (GSI_REG_BASE_PHYS + 0x00025040 + 0x12000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_2_OFFS(n) (GSI_REG_BASE_OFFS + 0x00025040 + 0x12000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_2_RMSK 0xffffffff +#define HWIO_EE_n_GSI_HW_PARAM_2_MAXn 2 +#define HWIO_EE_n_GSI_HW_PARAM_2_ATTR 0x1 +#define HWIO_EE_n_GSI_HW_PARAM_2_INI(n) \ + in_dword_masked(HWIO_EE_n_GSI_HW_PARAM_2_ADDR(n), HWIO_EE_n_GSI_HW_PARAM_2_RMSK) +#define HWIO_EE_n_GSI_HW_PARAM_2_INMI(n,mask) \ + in_dword_masked(HWIO_EE_n_GSI_HW_PARAM_2_ADDR(n), mask) +#define HWIO_EE_n_GSI_HW_PARAM_2_GSI_USE_INTER_EE_BMSK 0x80000000 +#define HWIO_EE_n_GSI_HW_PARAM_2_GSI_USE_INTER_EE_SHFT 0x1f +#define HWIO_EE_n_GSI_HW_PARAM_2_GSI_USE_RD_WR_ENG_BMSK 0x40000000 +#define HWIO_EE_n_GSI_HW_PARAM_2_GSI_USE_RD_WR_ENG_SHFT 0x1e +#define HWIO_EE_n_GSI_HW_PARAM_2_GSI_SDMA_N_IOVEC_BMSK 0x38000000 +#define HWIO_EE_n_GSI_HW_PARAM_2_GSI_SDMA_N_IOVEC_SHFT 0x1b +#define HWIO_EE_n_GSI_HW_PARAM_2_GSI_SDMA_MAX_BURST_BMSK 0x7f80000 +#define HWIO_EE_n_GSI_HW_PARAM_2_GSI_SDMA_MAX_BURST_SHFT 0x13 +#define HWIO_EE_n_GSI_HW_PARAM_2_GSI_SDMA_N_INT_BMSK 0x70000 +#define HWIO_EE_n_GSI_HW_PARAM_2_GSI_SDMA_N_INT_SHFT 0x10 +#define HWIO_EE_n_GSI_HW_PARAM_2_GSI_USE_SDMA_BMSK 0x8000 +#define HWIO_EE_n_GSI_HW_PARAM_2_GSI_USE_SDMA_SHFT 0xf +#define HWIO_EE_n_GSI_HW_PARAM_2_GSI_CH_FULL_LOGIC_BMSK 0x4000 +#define HWIO_EE_n_GSI_HW_PARAM_2_GSI_CH_FULL_LOGIC_SHFT 0xe +#define HWIO_EE_n_GSI_HW_PARAM_2_GSI_CH_PEND_TRANSLATE_BMSK 0x2000 +#define HWIO_EE_n_GSI_HW_PARAM_2_GSI_CH_PEND_TRANSLATE_SHFT 0xd +#define HWIO_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_BMSK 0x1f00 +#define HWIO_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_SHFT 0x8 +#define HWIO_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_ONE_KB_FVAL 0x0 +#define HWIO_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_TWO_KB_FVAL 0x1 +#define HWIO_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_TWO_N_HALF_KB_FVAL 0x2 +#define HWIO_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_THREE_KB_FVAL 0x3 +#define HWIO_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_THREE_N_HALF_KB_FVAL 0x4 +#define HWIO_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_FOUR_KB_FVAL 0x5 +#define HWIO_EE_n_GSI_HW_PARAM_2_GSI_NUM_CH_PER_EE_BMSK 0xff +#define HWIO_EE_n_GSI_HW_PARAM_2_GSI_NUM_CH_PER_EE_SHFT 0x0 + +#define HWIO_EE_n_GSI_SW_VERSION_ADDR(n) (GSI_REG_BASE + 0x00025044 + 0x12000 * (n)) +#define HWIO_EE_n_GSI_SW_VERSION_PHYS(n) (GSI_REG_BASE_PHYS + 0x00025044 + 0x12000 * (n)) +#define HWIO_EE_n_GSI_SW_VERSION_OFFS(n) (GSI_REG_BASE_OFFS + 0x00025044 + 0x12000 * (n)) +#define HWIO_EE_n_GSI_SW_VERSION_RMSK 0xffffffff +#define HWIO_EE_n_GSI_SW_VERSION_MAXn 2 +#define HWIO_EE_n_GSI_SW_VERSION_ATTR 0x1 +#define HWIO_EE_n_GSI_SW_VERSION_INI(n) \ + in_dword_masked(HWIO_EE_n_GSI_SW_VERSION_ADDR(n), HWIO_EE_n_GSI_SW_VERSION_RMSK) +#define HWIO_EE_n_GSI_SW_VERSION_INMI(n,mask) \ + in_dword_masked(HWIO_EE_n_GSI_SW_VERSION_ADDR(n), mask) +#define HWIO_EE_n_GSI_SW_VERSION_MAJOR_BMSK 0xf0000000 +#define HWIO_EE_n_GSI_SW_VERSION_MAJOR_SHFT 0x1c +#define HWIO_EE_n_GSI_SW_VERSION_MINOR_BMSK 0xfff0000 +#define HWIO_EE_n_GSI_SW_VERSION_MINOR_SHFT 0x10 +#define HWIO_EE_n_GSI_SW_VERSION_STEP_BMSK 0xffff +#define HWIO_EE_n_GSI_SW_VERSION_STEP_SHFT 0x0 + +#define HWIO_EE_n_GSI_MCS_CODE_VER_ADDR(n) (GSI_REG_BASE + 0x00025048 + 0x12000 * (n)) +#define HWIO_EE_n_GSI_MCS_CODE_VER_PHYS(n) (GSI_REG_BASE_PHYS + 0x00025048 + 0x12000 * (n)) +#define HWIO_EE_n_GSI_MCS_CODE_VER_OFFS(n) (GSI_REG_BASE_OFFS + 0x00025048 + 0x12000 * (n)) +#define HWIO_EE_n_GSI_MCS_CODE_VER_RMSK 0xffffffff +#define HWIO_EE_n_GSI_MCS_CODE_VER_MAXn 2 +#define HWIO_EE_n_GSI_MCS_CODE_VER_ATTR 0x1 +#define HWIO_EE_n_GSI_MCS_CODE_VER_INI(n) \ + in_dword_masked(HWIO_EE_n_GSI_MCS_CODE_VER_ADDR(n), HWIO_EE_n_GSI_MCS_CODE_VER_RMSK) +#define HWIO_EE_n_GSI_MCS_CODE_VER_INMI(n,mask) \ + in_dword_masked(HWIO_EE_n_GSI_MCS_CODE_VER_ADDR(n), mask) +#define HWIO_EE_n_GSI_MCS_CODE_VER_VER_BMSK 0xffffffff +#define HWIO_EE_n_GSI_MCS_CODE_VER_VER_SHFT 0x0 + +#define HWIO_EE_n_GSI_HW_PARAM_3_ADDR(n) (GSI_REG_BASE + 0x0002504c + 0x12000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_3_PHYS(n) (GSI_REG_BASE_PHYS + 0x0002504c + 0x12000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_3_OFFS(n) (GSI_REG_BASE_OFFS + 0x0002504c + 0x12000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_3_RMSK 0x1fffffff +#define HWIO_EE_n_GSI_HW_PARAM_3_MAXn 2 +#define HWIO_EE_n_GSI_HW_PARAM_3_ATTR 0x1 +#define HWIO_EE_n_GSI_HW_PARAM_3_INI(n) \ + in_dword_masked(HWIO_EE_n_GSI_HW_PARAM_3_ADDR(n), HWIO_EE_n_GSI_HW_PARAM_3_RMSK) +#define HWIO_EE_n_GSI_HW_PARAM_3_INMI(n,mask) \ + in_dword_masked(HWIO_EE_n_GSI_HW_PARAM_3_ADDR(n), mask) +#define HWIO_EE_n_GSI_HW_PARAM_3_GSI_USE_DB_MSI_MODE_BMSK 0x10000000 +#define HWIO_EE_n_GSI_HW_PARAM_3_GSI_USE_DB_MSI_MODE_SHFT 0x1c +#define HWIO_EE_n_GSI_HW_PARAM_3_GSI_USE_SLEEP_CLK_DIV_BMSK 0x8000000 +#define HWIO_EE_n_GSI_HW_PARAM_3_GSI_USE_SLEEP_CLK_DIV_SHFT 0x1b +#define HWIO_EE_n_GSI_HW_PARAM_3_GSI_USE_VIR_CH_IF_BMSK 0x4000000 +#define HWIO_EE_n_GSI_HW_PARAM_3_GSI_USE_VIR_CH_IF_SHFT 0x1a +#define HWIO_EE_n_GSI_HW_PARAM_3_GSI_USE_IROM_BMSK 0x2000000 +#define HWIO_EE_n_GSI_HW_PARAM_3_GSI_USE_IROM_SHFT 0x19 +#define HWIO_EE_n_GSI_HW_PARAM_3_GSI_REE_MAX_BURST_LEN_BMSK 0x1f00000 +#define HWIO_EE_n_GSI_HW_PARAM_3_GSI_REE_MAX_BURST_LEN_SHFT 0x14 +#define HWIO_EE_n_GSI_HW_PARAM_3_GSI_M_ADDR_BUS_W_BMSK 0xff000 +#define HWIO_EE_n_GSI_HW_PARAM_3_GSI_M_ADDR_BUS_W_SHFT 0xc +#define HWIO_EE_n_GSI_HW_PARAM_3_GSI_NUM_PREFETCH_BUFS_BMSK 0xf00 +#define HWIO_EE_n_GSI_HW_PARAM_3_GSI_NUM_PREFETCH_BUFS_SHFT 0x8 +#define HWIO_EE_n_GSI_HW_PARAM_3_GSI_SDMA_MAX_OS_WR_BMSK 0xf0 +#define HWIO_EE_n_GSI_HW_PARAM_3_GSI_SDMA_MAX_OS_WR_SHFT 0x4 +#define HWIO_EE_n_GSI_HW_PARAM_3_GSI_SDMA_MAX_OS_RD_BMSK 0xf +#define HWIO_EE_n_GSI_HW_PARAM_3_GSI_SDMA_MAX_OS_RD_SHFT 0x0 + +#define HWIO_EE_n_GSI_HW_PARAM_4_ADDR(n) (GSI_REG_BASE + 0x00025050 + 0x12000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_4_PHYS(n) (GSI_REG_BASE_PHYS + 0x00025050 + 0x12000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_4_OFFS(n) (GSI_REG_BASE_OFFS + 0x00025050 + 0x12000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_4_RMSK 0xffff +#define HWIO_EE_n_GSI_HW_PARAM_4_MAXn 2 +#define HWIO_EE_n_GSI_HW_PARAM_4_ATTR 0x1 +#define HWIO_EE_n_GSI_HW_PARAM_4_INI(n) \ + in_dword_masked(HWIO_EE_n_GSI_HW_PARAM_4_ADDR(n), HWIO_EE_n_GSI_HW_PARAM_4_RMSK) +#define HWIO_EE_n_GSI_HW_PARAM_4_INMI(n,mask) \ + in_dword_masked(HWIO_EE_n_GSI_HW_PARAM_4_ADDR(n), mask) +#define HWIO_EE_n_GSI_HW_PARAM_4_GSI_IRAM_PROTCOL_CNT_BMSK 0xff00 +#define HWIO_EE_n_GSI_HW_PARAM_4_GSI_IRAM_PROTCOL_CNT_SHFT 0x8 +#define HWIO_EE_n_GSI_HW_PARAM_4_GSI_NUM_EV_PER_EE_BMSK 0xff +#define HWIO_EE_n_GSI_HW_PARAM_4_GSI_NUM_EV_PER_EE_SHFT 0x0 + +#define HWIO_EE_n_CNTXT_TYPE_IRQ_ADDR(n) (GSI_REG_BASE + 0x00025080 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_PHYS(n) (GSI_REG_BASE_PHYS + 0x00025080 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_OFFS(n) (GSI_REG_BASE_OFFS + 0x00025080 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_RMSK 0x7f +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MAXn 2 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_ATTR 0x1 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_INI(n) \ + in_dword_masked(HWIO_EE_n_CNTXT_TYPE_IRQ_ADDR(n), HWIO_EE_n_CNTXT_TYPE_IRQ_RMSK) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_INMI(n,mask) \ + in_dword_masked(HWIO_EE_n_CNTXT_TYPE_IRQ_ADDR(n), mask) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_GENERAL_BMSK 0x40 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_GENERAL_SHFT 0x6 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_INTER_EE_EV_CTRL_BMSK 0x20 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_INTER_EE_EV_CTRL_SHFT 0x5 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_INTER_EE_CH_CTRL_BMSK 0x10 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_INTER_EE_CH_CTRL_SHFT 0x4 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_IEOB_BMSK 0x8 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_IEOB_SHFT 0x3 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_GLOB_EE_BMSK 0x4 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_GLOB_EE_SHFT 0x2 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_EV_CTRL_BMSK 0x2 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_EV_CTRL_SHFT 0x1 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_CH_CTRL_BMSK 0x1 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_CH_CTRL_SHFT 0x0 + +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_ADDR(n) (GSI_REG_BASE + 0x00025088 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_PHYS(n) (GSI_REG_BASE_PHYS + 0x00025088 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_OFFS(n) (GSI_REG_BASE_OFFS + 0x00025088 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_RMSK 0x7f +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_MAXn 2 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_ATTR 0x3 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_INI(n) \ + in_dword_masked(HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_ADDR(n), HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_RMSK) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_INMI(n,mask) \ + in_dword_masked(HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_ADDR(n), mask) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_OUTI(n,val) \ + out_dword(HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_ADDR(n),val) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_ADDR(n),mask,val,HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_INI(n)) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_GENERAL_BMSK 0x40 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_GENERAL_SHFT 0x6 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_INTER_EE_EV_CTRL_BMSK 0x20 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_INTER_EE_EV_CTRL_SHFT 0x5 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_INTER_EE_CH_CTRL_BMSK 0x10 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_INTER_EE_CH_CTRL_SHFT 0x4 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_IEOB_BMSK 0x8 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_IEOB_SHFT 0x3 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_GLOB_EE_BMSK 0x4 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_GLOB_EE_SHFT 0x2 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_EV_CTRL_BMSK 0x2 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_EV_CTRL_SHFT 0x1 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_CH_CTRL_BMSK 0x1 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_CH_CTRL_SHFT 0x0 + +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_k_ADDR(n,k) (GSI_REG_BASE + 0x00025090 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_k_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x00025090 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_k_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x00025090 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_k_RMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_k_MAXn 2 +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_k_MAXk 0 +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_k_ATTR 0x1 +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_k_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_k_ADDR(n,k), HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_k_RMSK) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_k_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_k_ADDR(n,k), mask) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_k_GSI_CH_BIT_MAP_BMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_k_GSI_CH_BIT_MAP_SHFT 0x0 + +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_ADDR(n,k) (GSI_REG_BASE + 0x00025094 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x00025094 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x00025094 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_RMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_MAXn 2 +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_MAXk 0 +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_ATTR 0x3 +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_ADDR(n,k), HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_RMSK) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_ADDR(n,k), mask) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_ADDR(n,k),val) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_ADDR(n,k),mask,val,HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_INI2(n,k)) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_GSI_CH_BIT_MAP_MSK_BMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_GSI_CH_BIT_MAP_MSK_SHFT 0x0 + +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_k_ADDR(n,k) (GSI_REG_BASE + 0x00025098 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_k_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x00025098 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_k_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x00025098 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_k_RMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_k_MAXn 2 +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_k_MAXk 0 +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_k_ATTR 0x2 +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_k_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_k_ADDR(n,k),val) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_k_GSI_CH_BIT_MAP_BMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_k_GSI_CH_BIT_MAP_SHFT 0x0 + +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_k_ADDR(n,k) (GSI_REG_BASE + 0x0002509c + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_k_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x0002509c + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_k_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x0002509c + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_k_RMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_k_MAXn 2 +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_k_MAXk 0 +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_k_ATTR 0x1 +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_k_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_k_ADDR(n,k), HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_k_RMSK) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_k_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_k_ADDR(n,k), mask) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_k_EV_CH_BIT_MAP_BMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_k_EV_CH_BIT_MAP_SHFT 0x0 + +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_ADDR(n,k) (GSI_REG_BASE + 0x000250a0 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x000250a0 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x000250a0 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_RMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_MAXn 2 +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_MAXk 0 +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_ATTR 0x3 +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_ADDR(n,k), HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_RMSK) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_ADDR(n,k), mask) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_ADDR(n,k),val) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_ADDR(n,k),mask,val,HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_INI2(n,k)) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_EV_CH_BIT_MAP_MSK_BMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_EV_CH_BIT_MAP_MSK_SHFT 0x0 + +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_k_ADDR(n,k) (GSI_REG_BASE + 0x000250a4 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_k_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x000250a4 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_k_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x000250a4 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_k_RMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_k_MAXn 2 +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_k_MAXk 0 +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_k_ATTR 0x2 +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_k_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_k_ADDR(n,k),val) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_k_EV_CH_BIT_MAP_BMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_k_EV_CH_BIT_MAP_SHFT 0x0 + +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_k_ADDR(n,k) (GSI_REG_BASE + 0x000250a8 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_k_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x000250a8 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_k_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x000250a8 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_k_RMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_k_MAXn 2 +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_k_MAXk 0 +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_k_ATTR 0x1 +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_k_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_k_ADDR(n,k), HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_k_RMSK) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_k_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_k_ADDR(n,k), mask) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_k_EV_CH_BIT_MAP_BMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_k_EV_CH_BIT_MAP_SHFT 0x0 + +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_ADDR(n,k) (GSI_REG_BASE + 0x000250ac + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x000250ac + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x000250ac + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_RMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_MAXn 2 +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_MAXk 0 +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_ATTR 0x3 +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_ADDR(n,k), HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_RMSK) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_ADDR(n,k), mask) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_ADDR(n,k),val) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_ADDR(n,k),mask,val,HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_INI2(n,k)) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_EV_CH_BIT_MAP_MSK_BMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_EV_CH_BIT_MAP_MSK_SHFT 0x0 + +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_k_ADDR(n,k) (GSI_REG_BASE + 0x000250b0 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_k_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x000250b0 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_k_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x000250b0 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_k_RMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_k_MAXn 2 +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_k_MAXk 0 +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_k_ATTR 0x2 +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_k_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_k_ADDR(n,k),val) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_k_EV_CH_BIT_MAP_BMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_k_EV_CH_BIT_MAP_SHFT 0x0 + +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_ADDR(n) (GSI_REG_BASE + 0x00025200 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_PHYS(n) (GSI_REG_BASE_PHYS + 0x00025200 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_OFFS(n) (GSI_REG_BASE_OFFS + 0x00025200 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_RMSK 0xf +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_MAXn 2 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_ATTR 0x1 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_INI(n) \ + in_dword_masked(HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_ADDR(n), HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_RMSK) +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_INMI(n,mask) \ + in_dword_masked(HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_ADDR(n), mask) +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT3_BMSK 0x8 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT3_SHFT 0x3 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT2_BMSK 0x4 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT2_SHFT 0x2 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT1_BMSK 0x2 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT1_SHFT 0x1 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_ERROR_INT_BMSK 0x1 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_ERROR_INT_SHFT 0x0 + +#define HWIO_EE_n_CNTXT_GLOB_IRQ_EN_ADDR(n) (GSI_REG_BASE + 0x00025204 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_GLOB_IRQ_EN_PHYS(n) (GSI_REG_BASE_PHYS + 0x00025204 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_GLOB_IRQ_EN_OFFS(n) (GSI_REG_BASE_OFFS + 0x00025204 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_GLOB_IRQ_EN_RMSK 0xf +#define HWIO_EE_n_CNTXT_GLOB_IRQ_EN_MAXn 2 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_EN_ATTR 0x3 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_EN_INI(n) \ + in_dword_masked(HWIO_EE_n_CNTXT_GLOB_IRQ_EN_ADDR(n), HWIO_EE_n_CNTXT_GLOB_IRQ_EN_RMSK) +#define HWIO_EE_n_CNTXT_GLOB_IRQ_EN_INMI(n,mask) \ + in_dword_masked(HWIO_EE_n_CNTXT_GLOB_IRQ_EN_ADDR(n), mask) +#define HWIO_EE_n_CNTXT_GLOB_IRQ_EN_OUTI(n,val) \ + out_dword(HWIO_EE_n_CNTXT_GLOB_IRQ_EN_ADDR(n),val) +#define HWIO_EE_n_CNTXT_GLOB_IRQ_EN_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_CNTXT_GLOB_IRQ_EN_ADDR(n),mask,val,HWIO_EE_n_CNTXT_GLOB_IRQ_EN_INI(n)) +#define HWIO_EE_n_CNTXT_GLOB_IRQ_EN_GP_INT3_BMSK 0x8 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_EN_GP_INT3_SHFT 0x3 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_EN_GP_INT2_BMSK 0x4 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_EN_GP_INT2_SHFT 0x2 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_EN_GP_INT1_BMSK 0x2 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_EN_GP_INT1_SHFT 0x1 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_EN_ERROR_INT_BMSK 0x1 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_EN_ERROR_INT_SHFT 0x0 + +#define HWIO_EE_n_CNTXT_GLOB_IRQ_CLR_ADDR(n) (GSI_REG_BASE + 0x00025208 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_GLOB_IRQ_CLR_PHYS(n) (GSI_REG_BASE_PHYS + 0x00025208 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_GLOB_IRQ_CLR_OFFS(n) (GSI_REG_BASE_OFFS + 0x00025208 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_GLOB_IRQ_CLR_RMSK 0xf +#define HWIO_EE_n_CNTXT_GLOB_IRQ_CLR_MAXn 2 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_CLR_ATTR 0x2 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_CLR_OUTI(n,val) \ + out_dword(HWIO_EE_n_CNTXT_GLOB_IRQ_CLR_ADDR(n),val) +#define HWIO_EE_n_CNTXT_GLOB_IRQ_CLR_GP_INT3_BMSK 0x8 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_CLR_GP_INT3_SHFT 0x3 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_CLR_GP_INT2_BMSK 0x4 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_CLR_GP_INT2_SHFT 0x2 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_CLR_GP_INT1_BMSK 0x2 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_CLR_GP_INT1_SHFT 0x1 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_CLR_ERROR_INT_BMSK 0x1 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_CLR_ERROR_INT_SHFT 0x0 + +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_ADDR(n) (GSI_REG_BASE + 0x0002520c + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_PHYS(n) (GSI_REG_BASE_PHYS + 0x0002520c + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_OFFS(n) (GSI_REG_BASE_OFFS + 0x0002520c + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_RMSK 0xf +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_MAXn 2 +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_ATTR 0x1 +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_INI(n) \ + in_dword_masked(HWIO_EE_n_CNTXT_GSI_IRQ_STTS_ADDR(n), HWIO_EE_n_CNTXT_GSI_IRQ_STTS_RMSK) +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_INMI(n,mask) \ + in_dword_masked(HWIO_EE_n_CNTXT_GSI_IRQ_STTS_ADDR(n), mask) +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_GSI_MCS_STACK_OVRFLOW_BMSK 0x8 +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_GSI_MCS_STACK_OVRFLOW_SHFT 0x3 +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_GSI_CMD_FIFO_OVRFLOW_BMSK 0x4 +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_GSI_CMD_FIFO_OVRFLOW_SHFT 0x2 +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_GSI_BUS_ERROR_BMSK 0x2 +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_GSI_BUS_ERROR_SHFT 0x1 +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_GSI_BREAK_POINT_BMSK 0x1 +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_GSI_BREAK_POINT_SHFT 0x0 + +#define HWIO_EE_n_CNTXT_GSI_IRQ_EN_ADDR(n) (GSI_REG_BASE + 0x00025210 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_GSI_IRQ_EN_PHYS(n) (GSI_REG_BASE_PHYS + 0x00025210 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_GSI_IRQ_EN_OFFS(n) (GSI_REG_BASE_OFFS + 0x00025210 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_GSI_IRQ_EN_RMSK 0xf +#define HWIO_EE_n_CNTXT_GSI_IRQ_EN_MAXn 2 +#define HWIO_EE_n_CNTXT_GSI_IRQ_EN_ATTR 0x3 +#define HWIO_EE_n_CNTXT_GSI_IRQ_EN_INI(n) \ + in_dword_masked(HWIO_EE_n_CNTXT_GSI_IRQ_EN_ADDR(n), HWIO_EE_n_CNTXT_GSI_IRQ_EN_RMSK) +#define HWIO_EE_n_CNTXT_GSI_IRQ_EN_INMI(n,mask) \ + in_dword_masked(HWIO_EE_n_CNTXT_GSI_IRQ_EN_ADDR(n), mask) +#define HWIO_EE_n_CNTXT_GSI_IRQ_EN_OUTI(n,val) \ + out_dword(HWIO_EE_n_CNTXT_GSI_IRQ_EN_ADDR(n),val) +#define HWIO_EE_n_CNTXT_GSI_IRQ_EN_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_CNTXT_GSI_IRQ_EN_ADDR(n),mask,val,HWIO_EE_n_CNTXT_GSI_IRQ_EN_INI(n)) +#define HWIO_EE_n_CNTXT_GSI_IRQ_EN_GSI_MCS_STACK_OVRFLOW_BMSK 0x8 +#define HWIO_EE_n_CNTXT_GSI_IRQ_EN_GSI_MCS_STACK_OVRFLOW_SHFT 0x3 +#define HWIO_EE_n_CNTXT_GSI_IRQ_EN_GSI_CMD_FIFO_OVRFLOW_BMSK 0x4 +#define HWIO_EE_n_CNTXT_GSI_IRQ_EN_GSI_CMD_FIFO_OVRFLOW_SHFT 0x2 +#define HWIO_EE_n_CNTXT_GSI_IRQ_EN_GSI_BUS_ERROR_BMSK 0x2 +#define HWIO_EE_n_CNTXT_GSI_IRQ_EN_GSI_BUS_ERROR_SHFT 0x1 +#define HWIO_EE_n_CNTXT_GSI_IRQ_EN_GSI_BREAK_POINT_BMSK 0x1 +#define HWIO_EE_n_CNTXT_GSI_IRQ_EN_GSI_BREAK_POINT_SHFT 0x0 + +#define HWIO_EE_n_CNTXT_GSI_IRQ_CLR_ADDR(n) (GSI_REG_BASE + 0x00025214 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_GSI_IRQ_CLR_PHYS(n) (GSI_REG_BASE_PHYS + 0x00025214 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_GSI_IRQ_CLR_OFFS(n) (GSI_REG_BASE_OFFS + 0x00025214 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_GSI_IRQ_CLR_RMSK 0xf +#define HWIO_EE_n_CNTXT_GSI_IRQ_CLR_MAXn 2 +#define HWIO_EE_n_CNTXT_GSI_IRQ_CLR_ATTR 0x2 +#define HWIO_EE_n_CNTXT_GSI_IRQ_CLR_OUTI(n,val) \ + out_dword(HWIO_EE_n_CNTXT_GSI_IRQ_CLR_ADDR(n),val) +#define HWIO_EE_n_CNTXT_GSI_IRQ_CLR_GSI_MCS_STACK_OVRFLOW_BMSK 0x8 +#define HWIO_EE_n_CNTXT_GSI_IRQ_CLR_GSI_MCS_STACK_OVRFLOW_SHFT 0x3 +#define HWIO_EE_n_CNTXT_GSI_IRQ_CLR_GSI_CMD_FIFO_OVRFLOW_BMSK 0x4 +#define HWIO_EE_n_CNTXT_GSI_IRQ_CLR_GSI_CMD_FIFO_OVRFLOW_SHFT 0x2 +#define HWIO_EE_n_CNTXT_GSI_IRQ_CLR_GSI_BUS_ERROR_BMSK 0x2 +#define HWIO_EE_n_CNTXT_GSI_IRQ_CLR_GSI_BUS_ERROR_SHFT 0x1 +#define HWIO_EE_n_CNTXT_GSI_IRQ_CLR_GSI_BREAK_POINT_BMSK 0x1 +#define HWIO_EE_n_CNTXT_GSI_IRQ_CLR_GSI_BREAK_POINT_SHFT 0x0 + +#define HWIO_EE_n_CNTXT_INTSET_ADDR(n) (GSI_REG_BASE + 0x00025220 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_INTSET_PHYS(n) (GSI_REG_BASE_PHYS + 0x00025220 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_INTSET_OFFS(n) (GSI_REG_BASE_OFFS + 0x00025220 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_INTSET_RMSK 0x1 +#define HWIO_EE_n_CNTXT_INTSET_MAXn 2 +#define HWIO_EE_n_CNTXT_INTSET_ATTR 0x3 +#define HWIO_EE_n_CNTXT_INTSET_INI(n) \ + in_dword_masked(HWIO_EE_n_CNTXT_INTSET_ADDR(n), HWIO_EE_n_CNTXT_INTSET_RMSK) +#define HWIO_EE_n_CNTXT_INTSET_INMI(n,mask) \ + in_dword_masked(HWIO_EE_n_CNTXT_INTSET_ADDR(n), mask) +#define HWIO_EE_n_CNTXT_INTSET_OUTI(n,val) \ + out_dword(HWIO_EE_n_CNTXT_INTSET_ADDR(n),val) +#define HWIO_EE_n_CNTXT_INTSET_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_CNTXT_INTSET_ADDR(n),mask,val,HWIO_EE_n_CNTXT_INTSET_INI(n)) +#define HWIO_EE_n_CNTXT_INTSET_INTYPE_BMSK 0x1 +#define HWIO_EE_n_CNTXT_INTSET_INTYPE_SHFT 0x0 +#define HWIO_EE_n_CNTXT_INTSET_INTYPE_MSI_FVAL 0x0 +#define HWIO_EE_n_CNTXT_INTSET_INTYPE_IRQ_FVAL 0x1 + +#define HWIO_EE_n_CNTXT_MSI_BASE_LSB_ADDR(n) (GSI_REG_BASE + 0x00025230 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_MSI_BASE_LSB_PHYS(n) (GSI_REG_BASE_PHYS + 0x00025230 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_MSI_BASE_LSB_OFFS(n) (GSI_REG_BASE_OFFS + 0x00025230 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_MSI_BASE_LSB_RMSK 0xffffffff +#define HWIO_EE_n_CNTXT_MSI_BASE_LSB_MAXn 2 +#define HWIO_EE_n_CNTXT_MSI_BASE_LSB_ATTR 0x3 +#define HWIO_EE_n_CNTXT_MSI_BASE_LSB_INI(n) \ + in_dword_masked(HWIO_EE_n_CNTXT_MSI_BASE_LSB_ADDR(n), HWIO_EE_n_CNTXT_MSI_BASE_LSB_RMSK) +#define HWIO_EE_n_CNTXT_MSI_BASE_LSB_INMI(n,mask) \ + in_dword_masked(HWIO_EE_n_CNTXT_MSI_BASE_LSB_ADDR(n), mask) +#define HWIO_EE_n_CNTXT_MSI_BASE_LSB_OUTI(n,val) \ + out_dword(HWIO_EE_n_CNTXT_MSI_BASE_LSB_ADDR(n),val) +#define HWIO_EE_n_CNTXT_MSI_BASE_LSB_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_CNTXT_MSI_BASE_LSB_ADDR(n),mask,val,HWIO_EE_n_CNTXT_MSI_BASE_LSB_INI(n)) +#define HWIO_EE_n_CNTXT_MSI_BASE_LSB_MSI_ADDR_LSB_BMSK 0xffffffff +#define HWIO_EE_n_CNTXT_MSI_BASE_LSB_MSI_ADDR_LSB_SHFT 0x0 + +#define HWIO_EE_n_CNTXT_MSI_BASE_MSB_ADDR(n) (GSI_REG_BASE + 0x00025234 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_MSI_BASE_MSB_PHYS(n) (GSI_REG_BASE_PHYS + 0x00025234 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_MSI_BASE_MSB_OFFS(n) (GSI_REG_BASE_OFFS + 0x00025234 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_MSI_BASE_MSB_RMSK 0xffffffff +#define HWIO_EE_n_CNTXT_MSI_BASE_MSB_MAXn 2 +#define HWIO_EE_n_CNTXT_MSI_BASE_MSB_ATTR 0x3 +#define HWIO_EE_n_CNTXT_MSI_BASE_MSB_INI(n) \ + in_dword_masked(HWIO_EE_n_CNTXT_MSI_BASE_MSB_ADDR(n), HWIO_EE_n_CNTXT_MSI_BASE_MSB_RMSK) +#define HWIO_EE_n_CNTXT_MSI_BASE_MSB_INMI(n,mask) \ + in_dword_masked(HWIO_EE_n_CNTXT_MSI_BASE_MSB_ADDR(n), mask) +#define HWIO_EE_n_CNTXT_MSI_BASE_MSB_OUTI(n,val) \ + out_dword(HWIO_EE_n_CNTXT_MSI_BASE_MSB_ADDR(n),val) +#define HWIO_EE_n_CNTXT_MSI_BASE_MSB_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_CNTXT_MSI_BASE_MSB_ADDR(n),mask,val,HWIO_EE_n_CNTXT_MSI_BASE_MSB_INI(n)) +#define HWIO_EE_n_CNTXT_MSI_BASE_MSB_MSI_ADDR_MSB_BMSK 0xffffffff +#define HWIO_EE_n_CNTXT_MSI_BASE_MSB_MSI_ADDR_MSB_SHFT 0x0 + +#define HWIO_EE_n_CNTXT_INT_VEC_ADDR(n) (GSI_REG_BASE + 0x00025238 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_INT_VEC_PHYS(n) (GSI_REG_BASE_PHYS + 0x00025238 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_INT_VEC_OFFS(n) (GSI_REG_BASE_OFFS + 0x00025238 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_INT_VEC_RMSK 0xffffffff +#define HWIO_EE_n_CNTXT_INT_VEC_MAXn 2 +#define HWIO_EE_n_CNTXT_INT_VEC_ATTR 0x3 +#define HWIO_EE_n_CNTXT_INT_VEC_INI(n) \ + in_dword_masked(HWIO_EE_n_CNTXT_INT_VEC_ADDR(n), HWIO_EE_n_CNTXT_INT_VEC_RMSK) +#define HWIO_EE_n_CNTXT_INT_VEC_INMI(n,mask) \ + in_dword_masked(HWIO_EE_n_CNTXT_INT_VEC_ADDR(n), mask) +#define HWIO_EE_n_CNTXT_INT_VEC_OUTI(n,val) \ + out_dword(HWIO_EE_n_CNTXT_INT_VEC_ADDR(n),val) +#define HWIO_EE_n_CNTXT_INT_VEC_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_CNTXT_INT_VEC_ADDR(n),mask,val,HWIO_EE_n_CNTXT_INT_VEC_INI(n)) +#define HWIO_EE_n_CNTXT_INT_VEC_INT_VEC_BMSK 0xffffffff +#define HWIO_EE_n_CNTXT_INT_VEC_INT_VEC_SHFT 0x0 + +#define HWIO_EE_n_ERROR_LOG_ADDR(n) (GSI_REG_BASE + 0x00025240 + 0x12000 * (n)) +#define HWIO_EE_n_ERROR_LOG_PHYS(n) (GSI_REG_BASE_PHYS + 0x00025240 + 0x12000 * (n)) +#define HWIO_EE_n_ERROR_LOG_OFFS(n) (GSI_REG_BASE_OFFS + 0x00025240 + 0x12000 * (n)) +#define HWIO_EE_n_ERROR_LOG_RMSK 0xffffffff +#define HWIO_EE_n_ERROR_LOG_MAXn 2 +#define HWIO_EE_n_ERROR_LOG_ATTR 0x3 +#define HWIO_EE_n_ERROR_LOG_INI(n) \ + in_dword_masked(HWIO_EE_n_ERROR_LOG_ADDR(n), HWIO_EE_n_ERROR_LOG_RMSK) +#define HWIO_EE_n_ERROR_LOG_INMI(n,mask) \ + in_dword_masked(HWIO_EE_n_ERROR_LOG_ADDR(n), mask) +#define HWIO_EE_n_ERROR_LOG_OUTI(n,val) \ + out_dword(HWIO_EE_n_ERROR_LOG_ADDR(n),val) +#define HWIO_EE_n_ERROR_LOG_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_ERROR_LOG_ADDR(n),mask,val,HWIO_EE_n_ERROR_LOG_INI(n)) +#define HWIO_EE_n_ERROR_LOG_ERROR_LOG_BMSK 0xffffffff +#define HWIO_EE_n_ERROR_LOG_ERROR_LOG_SHFT 0x0 + +#define HWIO_EE_n_ERROR_LOG_CLR_ADDR(n) (GSI_REG_BASE + 0x00025244 + 0x12000 * (n)) +#define HWIO_EE_n_ERROR_LOG_CLR_PHYS(n) (GSI_REG_BASE_PHYS + 0x00025244 + 0x12000 * (n)) +#define HWIO_EE_n_ERROR_LOG_CLR_OFFS(n) (GSI_REG_BASE_OFFS + 0x00025244 + 0x12000 * (n)) +#define HWIO_EE_n_ERROR_LOG_CLR_RMSK 0xffffffff +#define HWIO_EE_n_ERROR_LOG_CLR_MAXn 2 +#define HWIO_EE_n_ERROR_LOG_CLR_ATTR 0x2 +#define HWIO_EE_n_ERROR_LOG_CLR_OUTI(n,val) \ + out_dword(HWIO_EE_n_ERROR_LOG_CLR_ADDR(n),val) +#define HWIO_EE_n_ERROR_LOG_CLR_ERROR_LOG_CLR_BMSK 0xffffffff +#define HWIO_EE_n_ERROR_LOG_CLR_ERROR_LOG_CLR_SHFT 0x0 + +#define HWIO_EE_n_CNTXT_SCRATCH_0_ADDR(n) (GSI_REG_BASE + 0x00025400 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SCRATCH_0_PHYS(n) (GSI_REG_BASE_PHYS + 0x00025400 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SCRATCH_0_OFFS(n) (GSI_REG_BASE_OFFS + 0x00025400 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SCRATCH_0_RMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SCRATCH_0_MAXn 2 +#define HWIO_EE_n_CNTXT_SCRATCH_0_ATTR 0x3 +#define HWIO_EE_n_CNTXT_SCRATCH_0_INI(n) \ + in_dword_masked(HWIO_EE_n_CNTXT_SCRATCH_0_ADDR(n), HWIO_EE_n_CNTXT_SCRATCH_0_RMSK) +#define HWIO_EE_n_CNTXT_SCRATCH_0_INMI(n,mask) \ + in_dword_masked(HWIO_EE_n_CNTXT_SCRATCH_0_ADDR(n), mask) +#define HWIO_EE_n_CNTXT_SCRATCH_0_OUTI(n,val) \ + out_dword(HWIO_EE_n_CNTXT_SCRATCH_0_ADDR(n),val) +#define HWIO_EE_n_CNTXT_SCRATCH_0_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_CNTXT_SCRATCH_0_ADDR(n),mask,val,HWIO_EE_n_CNTXT_SCRATCH_0_INI(n)) +#define HWIO_EE_n_CNTXT_SCRATCH_0_SCRATCH_BMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SCRATCH_0_SCRATCH_SHFT 0x0 + +#define HWIO_EE_n_CNTXT_SCRATCH_1_ADDR(n) (GSI_REG_BASE + 0x00025404 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SCRATCH_1_PHYS(n) (GSI_REG_BASE_PHYS + 0x00025404 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SCRATCH_1_OFFS(n) (GSI_REG_BASE_OFFS + 0x00025404 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SCRATCH_1_RMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SCRATCH_1_MAXn 2 +#define HWIO_EE_n_CNTXT_SCRATCH_1_ATTR 0x3 +#define HWIO_EE_n_CNTXT_SCRATCH_1_INI(n) \ + in_dword_masked(HWIO_EE_n_CNTXT_SCRATCH_1_ADDR(n), HWIO_EE_n_CNTXT_SCRATCH_1_RMSK) +#define HWIO_EE_n_CNTXT_SCRATCH_1_INMI(n,mask) \ + in_dword_masked(HWIO_EE_n_CNTXT_SCRATCH_1_ADDR(n), mask) +#define HWIO_EE_n_CNTXT_SCRATCH_1_OUTI(n,val) \ + out_dword(HWIO_EE_n_CNTXT_SCRATCH_1_ADDR(n),val) +#define HWIO_EE_n_CNTXT_SCRATCH_1_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_CNTXT_SCRATCH_1_ADDR(n),mask,val,HWIO_EE_n_CNTXT_SCRATCH_1_INI(n)) +#define HWIO_EE_n_CNTXT_SCRATCH_1_SCRATCH_BMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SCRATCH_1_SCRATCH_SHFT 0x0 + +#define HWIO_GSI_MCS_CFG_ADDR (GSI_REG_BASE + 0x0000b000) +#define HWIO_GSI_MCS_CFG_PHYS (GSI_REG_BASE_PHYS + 0x0000b000) +#define HWIO_GSI_MCS_CFG_OFFS (GSI_REG_BASE_OFFS + 0x0000b000) +#define HWIO_GSI_MCS_CFG_RMSK 0x1 +#define HWIO_GSI_MCS_CFG_ATTR 0x3 +#define HWIO_GSI_MCS_CFG_IN \ + in_dword_masked(HWIO_GSI_MCS_CFG_ADDR, HWIO_GSI_MCS_CFG_RMSK) +#define HWIO_GSI_MCS_CFG_INM(m) \ + in_dword_masked(HWIO_GSI_MCS_CFG_ADDR, m) +#define HWIO_GSI_MCS_CFG_OUT(v) \ + out_dword(HWIO_GSI_MCS_CFG_ADDR,v) +#define HWIO_GSI_MCS_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_MCS_CFG_ADDR,m,v,HWIO_GSI_MCS_CFG_IN) +#define HWIO_GSI_MCS_CFG_MCS_ENABLE_BMSK 0x1 +#define HWIO_GSI_MCS_CFG_MCS_ENABLE_SHFT 0x0 + +#define HWIO_GSI_TZ_FW_AUTH_LOCK_ADDR (GSI_REG_BASE + 0x0000b008) +#define HWIO_GSI_TZ_FW_AUTH_LOCK_PHYS (GSI_REG_BASE_PHYS + 0x0000b008) +#define HWIO_GSI_TZ_FW_AUTH_LOCK_OFFS (GSI_REG_BASE_OFFS + 0x0000b008) +#define HWIO_GSI_TZ_FW_AUTH_LOCK_RMSK 0x3 +#define HWIO_GSI_TZ_FW_AUTH_LOCK_ATTR 0x3 +#define HWIO_GSI_TZ_FW_AUTH_LOCK_IN \ + in_dword_masked(HWIO_GSI_TZ_FW_AUTH_LOCK_ADDR, HWIO_GSI_TZ_FW_AUTH_LOCK_RMSK) +#define HWIO_GSI_TZ_FW_AUTH_LOCK_INM(m) \ + in_dword_masked(HWIO_GSI_TZ_FW_AUTH_LOCK_ADDR, m) +#define HWIO_GSI_TZ_FW_AUTH_LOCK_OUT(v) \ + out_dword(HWIO_GSI_TZ_FW_AUTH_LOCK_ADDR,v) +#define HWIO_GSI_TZ_FW_AUTH_LOCK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_TZ_FW_AUTH_LOCK_ADDR,m,v,HWIO_GSI_TZ_FW_AUTH_LOCK_IN) +#define HWIO_GSI_TZ_FW_AUTH_LOCK_DIS_DEBUG_SHRAM_WRITE_BMSK 0x2 +#define HWIO_GSI_TZ_FW_AUTH_LOCK_DIS_DEBUG_SHRAM_WRITE_SHFT 0x1 +#define HWIO_GSI_TZ_FW_AUTH_LOCK_DIS_IRAM_WRITE_BMSK 0x1 +#define HWIO_GSI_TZ_FW_AUTH_LOCK_DIS_IRAM_WRITE_SHFT 0x0 + +#define HWIO_GSI_MSA_FW_AUTH_LOCK_ADDR (GSI_REG_BASE + 0x0000b010) +#define HWIO_GSI_MSA_FW_AUTH_LOCK_PHYS (GSI_REG_BASE_PHYS + 0x0000b010) +#define HWIO_GSI_MSA_FW_AUTH_LOCK_OFFS (GSI_REG_BASE_OFFS + 0x0000b010) +#define HWIO_GSI_MSA_FW_AUTH_LOCK_RMSK 0x3 +#define HWIO_GSI_MSA_FW_AUTH_LOCK_ATTR 0x3 +#define HWIO_GSI_MSA_FW_AUTH_LOCK_IN \ + in_dword_masked(HWIO_GSI_MSA_FW_AUTH_LOCK_ADDR, HWIO_GSI_MSA_FW_AUTH_LOCK_RMSK) +#define HWIO_GSI_MSA_FW_AUTH_LOCK_INM(m) \ + in_dword_masked(HWIO_GSI_MSA_FW_AUTH_LOCK_ADDR, m) +#define HWIO_GSI_MSA_FW_AUTH_LOCK_OUT(v) \ + out_dword(HWIO_GSI_MSA_FW_AUTH_LOCK_ADDR,v) +#define HWIO_GSI_MSA_FW_AUTH_LOCK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_MSA_FW_AUTH_LOCK_ADDR,m,v,HWIO_GSI_MSA_FW_AUTH_LOCK_IN) +#define HWIO_GSI_MSA_FW_AUTH_LOCK_DIS_DEBUG_SHRAM_WRITE_BMSK 0x2 +#define HWIO_GSI_MSA_FW_AUTH_LOCK_DIS_DEBUG_SHRAM_WRITE_SHFT 0x1 +#define HWIO_GSI_MSA_FW_AUTH_LOCK_DIS_IRAM_WRITE_BMSK 0x1 +#define HWIO_GSI_MSA_FW_AUTH_LOCK_DIS_IRAM_WRITE_SHFT 0x0 + +#define HWIO_GSI_SP_FW_AUTH_LOCK_ADDR (GSI_REG_BASE + 0x0000b018) +#define HWIO_GSI_SP_FW_AUTH_LOCK_PHYS (GSI_REG_BASE_PHYS + 0x0000b018) +#define HWIO_GSI_SP_FW_AUTH_LOCK_OFFS (GSI_REG_BASE_OFFS + 0x0000b018) +#define HWIO_GSI_SP_FW_AUTH_LOCK_RMSK 0x3 +#define HWIO_GSI_SP_FW_AUTH_LOCK_ATTR 0x3 +#define HWIO_GSI_SP_FW_AUTH_LOCK_IN \ + in_dword_masked(HWIO_GSI_SP_FW_AUTH_LOCK_ADDR, HWIO_GSI_SP_FW_AUTH_LOCK_RMSK) +#define HWIO_GSI_SP_FW_AUTH_LOCK_INM(m) \ + in_dword_masked(HWIO_GSI_SP_FW_AUTH_LOCK_ADDR, m) +#define HWIO_GSI_SP_FW_AUTH_LOCK_OUT(v) \ + out_dword(HWIO_GSI_SP_FW_AUTH_LOCK_ADDR,v) +#define HWIO_GSI_SP_FW_AUTH_LOCK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_SP_FW_AUTH_LOCK_ADDR,m,v,HWIO_GSI_SP_FW_AUTH_LOCK_IN) +#define HWIO_GSI_SP_FW_AUTH_LOCK_DIS_DEBUG_SHRAM_WRITE_BMSK 0x2 +#define HWIO_GSI_SP_FW_AUTH_LOCK_DIS_DEBUG_SHRAM_WRITE_SHFT 0x1 +#define HWIO_GSI_SP_FW_AUTH_LOCK_DIS_IRAM_WRITE_BMSK 0x1 +#define HWIO_GSI_SP_FW_AUTH_LOCK_DIS_IRAM_WRITE_SHFT 0x0 + +#define HWIO_INTER_EE_n_ORIGINATOR_EE_ADDR(n) (GSI_REG_BASE + 0x0000c000 + 0x1000 * (n)) +#define HWIO_INTER_EE_n_ORIGINATOR_EE_PHYS(n) (GSI_REG_BASE_PHYS + 0x0000c000 + 0x1000 * (n)) +#define HWIO_INTER_EE_n_ORIGINATOR_EE_OFFS(n) (GSI_REG_BASE_OFFS + 0x0000c000 + 0x1000 * (n)) +#define HWIO_INTER_EE_n_ORIGINATOR_EE_RMSK 0xf +#define HWIO_INTER_EE_n_ORIGINATOR_EE_MAXn 2 +#define HWIO_INTER_EE_n_ORIGINATOR_EE_ATTR 0x3 +#define HWIO_INTER_EE_n_ORIGINATOR_EE_INI(n) \ + in_dword_masked(HWIO_INTER_EE_n_ORIGINATOR_EE_ADDR(n), HWIO_INTER_EE_n_ORIGINATOR_EE_RMSK) +#define HWIO_INTER_EE_n_ORIGINATOR_EE_INMI(n,mask) \ + in_dword_masked(HWIO_INTER_EE_n_ORIGINATOR_EE_ADDR(n), mask) +#define HWIO_INTER_EE_n_ORIGINATOR_EE_OUTI(n,val) \ + out_dword(HWIO_INTER_EE_n_ORIGINATOR_EE_ADDR(n),val) +#define HWIO_INTER_EE_n_ORIGINATOR_EE_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_INTER_EE_n_ORIGINATOR_EE_ADDR(n),mask,val,HWIO_INTER_EE_n_ORIGINATOR_EE_INI(n)) +#define HWIO_INTER_EE_n_ORIGINATOR_EE_EE_NUMBER_BMSK 0xf +#define HWIO_INTER_EE_n_ORIGINATOR_EE_EE_NUMBER_SHFT 0x0 + +#define HWIO_INTER_EE_n_GSI_CH_CMD_ADDR(n) (GSI_REG_BASE + 0x0000c008 + 0x1000 * (n)) +#define HWIO_INTER_EE_n_GSI_CH_CMD_PHYS(n) (GSI_REG_BASE_PHYS + 0x0000c008 + 0x1000 * (n)) +#define HWIO_INTER_EE_n_GSI_CH_CMD_OFFS(n) (GSI_REG_BASE_OFFS + 0x0000c008 + 0x1000 * (n)) +#define HWIO_INTER_EE_n_GSI_CH_CMD_RMSK 0xff0000ff +#define HWIO_INTER_EE_n_GSI_CH_CMD_MAXn 2 +#define HWIO_INTER_EE_n_GSI_CH_CMD_ATTR 0x2 +#define HWIO_INTER_EE_n_GSI_CH_CMD_OUTI(n,val) \ + out_dword(HWIO_INTER_EE_n_GSI_CH_CMD_ADDR(n),val) +#define HWIO_INTER_EE_n_GSI_CH_CMD_OPCODE_BMSK 0xff000000 +#define HWIO_INTER_EE_n_GSI_CH_CMD_OPCODE_SHFT 0x18 +#define HWIO_INTER_EE_n_GSI_CH_CMD_OPCODE_START_FVAL 0x1 +#define HWIO_INTER_EE_n_GSI_CH_CMD_OPCODE_STOP_FVAL 0x2 +#define HWIO_INTER_EE_n_GSI_CH_CMD_OPCODE_RESET_FVAL 0x9 +#define HWIO_INTER_EE_n_GSI_CH_CMD_OPCODE_DE_ALLOC_FVAL 0xa +#define HWIO_INTER_EE_n_GSI_CH_CMD_OPCODE_DB_STOP_FVAL 0xb +#define HWIO_INTER_EE_n_GSI_CH_CMD_CHID_BMSK 0xff +#define HWIO_INTER_EE_n_GSI_CH_CMD_CHID_SHFT 0x0 + +#define HWIO_INTER_EE_n_EV_CH_CMD_ADDR(n) (GSI_REG_BASE + 0x0000c010 + 0x1000 * (n)) +#define HWIO_INTER_EE_n_EV_CH_CMD_PHYS(n) (GSI_REG_BASE_PHYS + 0x0000c010 + 0x1000 * (n)) +#define HWIO_INTER_EE_n_EV_CH_CMD_OFFS(n) (GSI_REG_BASE_OFFS + 0x0000c010 + 0x1000 * (n)) +#define HWIO_INTER_EE_n_EV_CH_CMD_RMSK 0xff0000ff +#define HWIO_INTER_EE_n_EV_CH_CMD_MAXn 2 +#define HWIO_INTER_EE_n_EV_CH_CMD_ATTR 0x2 +#define HWIO_INTER_EE_n_EV_CH_CMD_OUTI(n,val) \ + out_dword(HWIO_INTER_EE_n_EV_CH_CMD_ADDR(n),val) +#define HWIO_INTER_EE_n_EV_CH_CMD_OPCODE_BMSK 0xff000000 +#define HWIO_INTER_EE_n_EV_CH_CMD_OPCODE_SHFT 0x18 +#define HWIO_INTER_EE_n_EV_CH_CMD_OPCODE_RESET_FVAL 0x9 +#define HWIO_INTER_EE_n_EV_CH_CMD_OPCODE_DE_ALLOC_FVAL 0xa +#define HWIO_INTER_EE_n_EV_CH_CMD_CHID_BMSK 0xff +#define HWIO_INTER_EE_n_EV_CH_CMD_CHID_SHFT 0x0 + +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_k_ADDR(n,k) (GSI_REG_BASE + 0x0000c018 + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_k_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x0000c018 + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_k_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x0000c018 + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_k_RMSK 0xffffffff +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_k_MAXn 2 +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_k_MAXk 0 +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_k_ATTR 0x1 +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_k_INI2(n,k) \ + in_dword_masked(HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_k_ADDR(n,k), HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_k_RMSK) +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_k_INMI2(n,k,mask) \ + in_dword_masked(HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_k_ADDR(n,k), mask) +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_k_GSI_CH_BIT_MAP_BMSK 0xffffffff +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_k_GSI_CH_BIT_MAP_SHFT 0x0 + +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_ADDR(n,k) (GSI_REG_BASE + 0x0000c01c + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x0000c01c + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x0000c01c + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_RMSK 0xffffffff +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_MAXn 2 +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_MAXk 0 +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_ATTR 0x3 +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_INI2(n,k) \ + in_dword_masked(HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_ADDR(n,k), HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_RMSK) +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_INMI2(n,k,mask) \ + in_dword_masked(HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_ADDR(n,k), mask) +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_OUTI2(n,k,val) \ + out_dword(HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_ADDR(n,k),val) +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_ADDR(n,k),mask,val,HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_INI2(n,k)) +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_GSI_CH_BIT_MAP_MSK_BMSK 0xffffffff +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_GSI_CH_BIT_MAP_MSK_SHFT 0x0 + +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_k_ADDR(n,k) (GSI_REG_BASE + 0x0000c020 + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_k_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x0000c020 + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_k_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x0000c020 + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_k_RMSK 0xffffffff +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_k_MAXn 2 +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_k_MAXk 0 +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_k_ATTR 0x2 +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_k_OUTI2(n,k,val) \ + out_dword(HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_k_ADDR(n,k),val) +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_k_GSI_CH_BIT_MAP_BMSK 0xffffffff +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_k_GSI_CH_BIT_MAP_SHFT 0x0 + +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_k_ADDR(n,k) (GSI_REG_BASE + 0x0000c024 + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_k_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x0000c024 + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_k_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x0000c024 + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_k_RMSK 0xffffffff +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_k_MAXn 2 +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_k_MAXk 0 +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_k_ATTR 0x1 +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_k_INI2(n,k) \ + in_dword_masked(HWIO_INTER_EE_n_SRC_EV_CH_IRQ_k_ADDR(n,k), HWIO_INTER_EE_n_SRC_EV_CH_IRQ_k_RMSK) +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_k_INMI2(n,k,mask) \ + in_dword_masked(HWIO_INTER_EE_n_SRC_EV_CH_IRQ_k_ADDR(n,k), mask) +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_k_EV_CH_BIT_MAP_BMSK 0xffffffff +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_k_EV_CH_BIT_MAP_SHFT 0x0 + +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_ADDR(n,k) (GSI_REG_BASE + 0x0000c028 + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x0000c028 + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x0000c028 + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_RMSK 0xffffffff +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_MAXn 2 +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_MAXk 0 +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_ATTR 0x3 +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_INI2(n,k) \ + in_dword_masked(HWIO_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_ADDR(n,k), HWIO_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_RMSK) +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_INMI2(n,k,mask) \ + in_dword_masked(HWIO_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_ADDR(n,k), mask) +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_OUTI2(n,k,val) \ + out_dword(HWIO_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_ADDR(n,k),val) +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_ADDR(n,k),mask,val,HWIO_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_INI2(n,k)) +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_EV_CH_BIT_MAP_MSK_BMSK 0xffffffff +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_EV_CH_BIT_MAP_MSK_SHFT 0x0 + +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_CLR_k_ADDR(n,k) (GSI_REG_BASE + 0x0000c02c + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_CLR_k_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x0000c02c + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_CLR_k_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x0000c02c + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_CLR_k_RMSK 0xffffffff +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_CLR_k_MAXn 2 +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_CLR_k_MAXk 0 +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_CLR_k_ATTR 0x2 +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_CLR_k_OUTI2(n,k,val) \ + out_dword(HWIO_INTER_EE_n_SRC_EV_CH_IRQ_CLR_k_ADDR(n,k),val) +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_CLR_k_EV_CH_BIT_MAP_BMSK 0xffffffff +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_CLR_k_EV_CH_BIT_MAP_SHFT 0x0 + +/*---------------------------------------------------------------------------- + * MODULE: IPA_0_GSI_TOP_XPU3 + *--------------------------------------------------------------------------*/ + +#define IPA_0_GSI_TOP_XPU3_REG_BASE (IPA_0_IPA_WRAPPER_BASE + 0x00000000) +#define IPA_0_GSI_TOP_XPU3_REG_BASE_PHYS (IPA_0_IPA_WRAPPER_BASE_PHYS + 0x00000000) +#define IPA_0_GSI_TOP_XPU3_REG_BASE_OFFS 0x00000000 + +#define HWIO_IPA_0_GSI_TOP_XPU3_GCR0_ADDR (IPA_0_GSI_TOP_XPU3_REG_BASE + 0x00000000) +#define HWIO_IPA_0_GSI_TOP_XPU3_GCR0_PHYS (IPA_0_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000000) +#define HWIO_IPA_0_GSI_TOP_XPU3_GCR0_OFFS (IPA_0_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000000) +#define HWIO_IPA_0_GSI_TOP_XPU3_GCR0_RMSK 0x3 +#define HWIO_IPA_0_GSI_TOP_XPU3_GCR0_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_XPU3_GCR0_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_GCR0_ADDR, HWIO_IPA_0_GSI_TOP_XPU3_GCR0_RMSK) +#define HWIO_IPA_0_GSI_TOP_XPU3_GCR0_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_GCR0_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_XPU3_GCR0_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_XPU3_GCR0_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_XPU3_GCR0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_XPU3_GCR0_ADDR,m,v,HWIO_IPA_0_GSI_TOP_XPU3_GCR0_IN) +#define HWIO_IPA_0_GSI_TOP_XPU3_GCR0_AALOG_MODE_DIS_BMSK 0x2 +#define HWIO_IPA_0_GSI_TOP_XPU3_GCR0_AALOG_MODE_DIS_SHFT 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_GCR0_AADEN_BMSK 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_GCR0_AADEN_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_XPU3_SCR0_ADDR (IPA_0_GSI_TOP_XPU3_REG_BASE + 0x00000008) +#define HWIO_IPA_0_GSI_TOP_XPU3_SCR0_PHYS (IPA_0_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000008) +#define HWIO_IPA_0_GSI_TOP_XPU3_SCR0_OFFS (IPA_0_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000008) +#define HWIO_IPA_0_GSI_TOP_XPU3_SCR0_RMSK 0x10f +#define HWIO_IPA_0_GSI_TOP_XPU3_SCR0_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_XPU3_SCR0_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_SCR0_ADDR, HWIO_IPA_0_GSI_TOP_XPU3_SCR0_RMSK) +#define HWIO_IPA_0_GSI_TOP_XPU3_SCR0_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_SCR0_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_XPU3_SCR0_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_XPU3_SCR0_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_XPU3_SCR0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_XPU3_SCR0_ADDR,m,v,HWIO_IPA_0_GSI_TOP_XPU3_SCR0_IN) +#define HWIO_IPA_0_GSI_TOP_XPU3_SCR0_DYNAMIC_CLK_EN_BMSK 0x100 +#define HWIO_IPA_0_GSI_TOP_XPU3_SCR0_DYNAMIC_CLK_EN_SHFT 0x8 +#define HWIO_IPA_0_GSI_TOP_XPU3_SCR0_SCLEIE_BMSK 0x8 +#define HWIO_IPA_0_GSI_TOP_XPU3_SCR0_SCLEIE_SHFT 0x3 +#define HWIO_IPA_0_GSI_TOP_XPU3_SCR0_SCFGEIE_BMSK 0x4 +#define HWIO_IPA_0_GSI_TOP_XPU3_SCR0_SCFGEIE_SHFT 0x2 +#define HWIO_IPA_0_GSI_TOP_XPU3_SCR0_SCLERE_BMSK 0x2 +#define HWIO_IPA_0_GSI_TOP_XPU3_SCR0_SCLERE_SHFT 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_SCR0_SCFGERE_BMSK 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_SCR0_SCFGERE_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_XPU3_CR0_ADDR (IPA_0_GSI_TOP_XPU3_REG_BASE + 0x00000010) +#define HWIO_IPA_0_GSI_TOP_XPU3_CR0_PHYS (IPA_0_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000010) +#define HWIO_IPA_0_GSI_TOP_XPU3_CR0_OFFS (IPA_0_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000010) +#define HWIO_IPA_0_GSI_TOP_XPU3_CR0_RMSK 0x18f +#define HWIO_IPA_0_GSI_TOP_XPU3_CR0_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_XPU3_CR0_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_CR0_ADDR, HWIO_IPA_0_GSI_TOP_XPU3_CR0_RMSK) +#define HWIO_IPA_0_GSI_TOP_XPU3_CR0_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_CR0_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_XPU3_CR0_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_XPU3_CR0_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_XPU3_CR0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_XPU3_CR0_ADDR,m,v,HWIO_IPA_0_GSI_TOP_XPU3_CR0_IN) +#define HWIO_IPA_0_GSI_TOP_XPU3_CR0_DYNAMIC_CLK_EN_BMSK 0x100 +#define HWIO_IPA_0_GSI_TOP_XPU3_CR0_DYNAMIC_CLK_EN_SHFT 0x8 +#define HWIO_IPA_0_GSI_TOP_XPU3_CR0_VMIDEN_BMSK 0x80 +#define HWIO_IPA_0_GSI_TOP_XPU3_CR0_VMIDEN_SHFT 0x7 +#define HWIO_IPA_0_GSI_TOP_XPU3_CR0_CLEIE_BMSK 0x8 +#define HWIO_IPA_0_GSI_TOP_XPU3_CR0_CLEIE_SHFT 0x3 +#define HWIO_IPA_0_GSI_TOP_XPU3_CR0_CFGEIE_BMSK 0x4 +#define HWIO_IPA_0_GSI_TOP_XPU3_CR0_CFGEIE_SHFT 0x2 +#define HWIO_IPA_0_GSI_TOP_XPU3_CR0_CLERE_BMSK 0x2 +#define HWIO_IPA_0_GSI_TOP_XPU3_CR0_CLERE_SHFT 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_CR0_CFGERE_BMSK 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_CR0_CFGERE_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_XPU3_RPU_ACR0_ADDR (IPA_0_GSI_TOP_XPU3_REG_BASE + 0x00000020) +#define HWIO_IPA_0_GSI_TOP_XPU3_RPU_ACR0_PHYS (IPA_0_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000020) +#define HWIO_IPA_0_GSI_TOP_XPU3_RPU_ACR0_OFFS (IPA_0_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000020) +#define HWIO_IPA_0_GSI_TOP_XPU3_RPU_ACR0_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_XPU3_RPU_ACR0_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_XPU3_RPU_ACR0_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_RPU_ACR0_ADDR, HWIO_IPA_0_GSI_TOP_XPU3_RPU_ACR0_RMSK) +#define HWIO_IPA_0_GSI_TOP_XPU3_RPU_ACR0_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_RPU_ACR0_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_XPU3_RPU_ACR0_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_XPU3_RPU_ACR0_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_XPU3_RPU_ACR0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_XPU3_RPU_ACR0_ADDR,m,v,HWIO_IPA_0_GSI_TOP_XPU3_RPU_ACR0_IN) +#define HWIO_IPA_0_GSI_TOP_XPU3_RPU_ACR0_SUVMID_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_XPU3_RPU_ACR0_SUVMID_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_GCR0_ADDR (IPA_0_GSI_TOP_XPU3_REG_BASE + 0x00000080) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_GCR0_PHYS (IPA_0_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000080) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_GCR0_OFFS (IPA_0_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000080) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_GCR0_RMSK 0x3 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_GCR0_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_GCR0_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_QAD0_GCR0_ADDR, HWIO_IPA_0_GSI_TOP_XPU3_QAD0_GCR0_RMSK) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_GCR0_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_QAD0_GCR0_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_GCR0_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_XPU3_QAD0_GCR0_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_GCR0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_XPU3_QAD0_GCR0_ADDR,m,v,HWIO_IPA_0_GSI_TOP_XPU3_QAD0_GCR0_IN) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_GCR0_QAD0LOG_MODE_DIS_BMSK 0x2 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_GCR0_QAD0LOG_MODE_DIS_SHFT 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_GCR0_QAD0DEN_BMSK 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_GCR0_QAD0DEN_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_CR0_ADDR (IPA_0_GSI_TOP_XPU3_REG_BASE + 0x00000090) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_CR0_PHYS (IPA_0_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000090) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_CR0_OFFS (IPA_0_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000090) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_CR0_RMSK 0x10f +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_CR0_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_CR0_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_QAD0_CR0_ADDR, HWIO_IPA_0_GSI_TOP_XPU3_QAD0_CR0_RMSK) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_CR0_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_QAD0_CR0_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_CR0_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_XPU3_QAD0_CR0_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_CR0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_XPU3_QAD0_CR0_ADDR,m,v,HWIO_IPA_0_GSI_TOP_XPU3_QAD0_CR0_IN) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_CR0_DYNAMIC_CLK_EN_BMSK 0x100 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_CR0_DYNAMIC_CLK_EN_SHFT 0x8 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_CR0_CLEIE_BMSK 0x8 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_CR0_CLEIE_SHFT 0x3 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_CR0_CFGEIE_BMSK 0x4 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_CR0_CFGEIE_SHFT 0x2 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_CR0_CLERE_BMSK 0x2 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_CR0_CLERE_SHFT 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_CR0_CFGERE_BMSK 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_CR0_CFGERE_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_GCR0_ADDR (IPA_0_GSI_TOP_XPU3_REG_BASE + 0x00000100) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_GCR0_PHYS (IPA_0_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000100) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_GCR0_OFFS (IPA_0_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000100) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_GCR0_RMSK 0x3 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_GCR0_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_GCR0_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_QAD1_GCR0_ADDR, HWIO_IPA_0_GSI_TOP_XPU3_QAD1_GCR0_RMSK) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_GCR0_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_QAD1_GCR0_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_GCR0_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_XPU3_QAD1_GCR0_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_GCR0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_XPU3_QAD1_GCR0_ADDR,m,v,HWIO_IPA_0_GSI_TOP_XPU3_QAD1_GCR0_IN) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_GCR0_QAD1LOG_MODE_DIS_BMSK 0x2 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_GCR0_QAD1LOG_MODE_DIS_SHFT 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_GCR0_QAD1DEN_BMSK 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_GCR0_QAD1DEN_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_CR0_ADDR (IPA_0_GSI_TOP_XPU3_REG_BASE + 0x00000110) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_CR0_PHYS (IPA_0_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000110) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_CR0_OFFS (IPA_0_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000110) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_CR0_RMSK 0x10f +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_CR0_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_CR0_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_QAD1_CR0_ADDR, HWIO_IPA_0_GSI_TOP_XPU3_QAD1_CR0_RMSK) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_CR0_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_QAD1_CR0_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_CR0_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_XPU3_QAD1_CR0_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_CR0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_XPU3_QAD1_CR0_ADDR,m,v,HWIO_IPA_0_GSI_TOP_XPU3_QAD1_CR0_IN) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_CR0_DYNAMIC_CLK_EN_BMSK 0x100 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_CR0_DYNAMIC_CLK_EN_SHFT 0x8 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_CR0_CLEIE_BMSK 0x8 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_CR0_CLEIE_SHFT 0x3 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_CR0_CFGEIE_BMSK 0x4 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_CR0_CFGEIE_SHFT 0x2 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_CR0_CLERE_BMSK 0x2 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_CR0_CLERE_SHFT 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_CR0_CFGERE_BMSK 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_CR0_CFGERE_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_XPU3_IDR3_ADDR (IPA_0_GSI_TOP_XPU3_REG_BASE + 0x000003ec) +#define HWIO_IPA_0_GSI_TOP_XPU3_IDR3_PHYS (IPA_0_GSI_TOP_XPU3_REG_BASE_PHYS + 0x000003ec) +#define HWIO_IPA_0_GSI_TOP_XPU3_IDR3_OFFS (IPA_0_GSI_TOP_XPU3_REG_BASE_OFFS + 0x000003ec) +#define HWIO_IPA_0_GSI_TOP_XPU3_IDR3_RMSK 0x3ff +#define HWIO_IPA_0_GSI_TOP_XPU3_IDR3_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_IDR3_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_IDR3_ADDR, HWIO_IPA_0_GSI_TOP_XPU3_IDR3_RMSK) +#define HWIO_IPA_0_GSI_TOP_XPU3_IDR3_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_IDR3_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_XPU3_IDR3_PT_BMSK 0x200 +#define HWIO_IPA_0_GSI_TOP_XPU3_IDR3_PT_SHFT 0x9 +#define HWIO_IPA_0_GSI_TOP_XPU3_IDR3_MV_BMSK 0x100 +#define HWIO_IPA_0_GSI_TOP_XPU3_IDR3_MV_SHFT 0x8 +#define HWIO_IPA_0_GSI_TOP_XPU3_IDR3_NVMID_BMSK 0xff +#define HWIO_IPA_0_GSI_TOP_XPU3_IDR3_NVMID_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_XPU3_IDR2_ADDR (IPA_0_GSI_TOP_XPU3_REG_BASE + 0x000003f0) +#define HWIO_IPA_0_GSI_TOP_XPU3_IDR2_PHYS (IPA_0_GSI_TOP_XPU3_REG_BASE_PHYS + 0x000003f0) +#define HWIO_IPA_0_GSI_TOP_XPU3_IDR2_OFFS (IPA_0_GSI_TOP_XPU3_REG_BASE_OFFS + 0x000003f0) +#define HWIO_IPA_0_GSI_TOP_XPU3_IDR2_RMSK 0xffffff0f +#define HWIO_IPA_0_GSI_TOP_XPU3_IDR2_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_IDR2_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_IDR2_ADDR, HWIO_IPA_0_GSI_TOP_XPU3_IDR2_RMSK) +#define HWIO_IPA_0_GSI_TOP_XPU3_IDR2_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_IDR2_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_XPU3_IDR2_NONSEC_EN_BMSK 0xff000000 +#define HWIO_IPA_0_GSI_TOP_XPU3_IDR2_NONSEC_EN_SHFT 0x18 +#define HWIO_IPA_0_GSI_TOP_XPU3_IDR2_SEC_EN_BMSK 0xff0000 +#define HWIO_IPA_0_GSI_TOP_XPU3_IDR2_SEC_EN_SHFT 0x10 +#define HWIO_IPA_0_GSI_TOP_XPU3_IDR2_VMIDACR_EN_BMSK 0xff00 +#define HWIO_IPA_0_GSI_TOP_XPU3_IDR2_VMIDACR_EN_SHFT 0x8 +#define HWIO_IPA_0_GSI_TOP_XPU3_IDR2_NUM_QAD_BMSK 0xf +#define HWIO_IPA_0_GSI_TOP_XPU3_IDR2_NUM_QAD_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_XPU3_IDR1_ADDR (IPA_0_GSI_TOP_XPU3_REG_BASE + 0x000003f4) +#define HWIO_IPA_0_GSI_TOP_XPU3_IDR1_PHYS (IPA_0_GSI_TOP_XPU3_REG_BASE_PHYS + 0x000003f4) +#define HWIO_IPA_0_GSI_TOP_XPU3_IDR1_OFFS (IPA_0_GSI_TOP_XPU3_REG_BASE_OFFS + 0x000003f4) +#define HWIO_IPA_0_GSI_TOP_XPU3_IDR1_RMSK 0x3f3f0000 +#define HWIO_IPA_0_GSI_TOP_XPU3_IDR1_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_IDR1_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_IDR1_ADDR, HWIO_IPA_0_GSI_TOP_XPU3_IDR1_RMSK) +#define HWIO_IPA_0_GSI_TOP_XPU3_IDR1_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_IDR1_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_XPU3_IDR1_CLIENT_ADDR_WIDTH_BMSK 0x3f000000 +#define HWIO_IPA_0_GSI_TOP_XPU3_IDR1_CLIENT_ADDR_WIDTH_SHFT 0x18 +#define HWIO_IPA_0_GSI_TOP_XPU3_IDR1_CONFIG_ADDR_WIDTH_BMSK 0x3f0000 +#define HWIO_IPA_0_GSI_TOP_XPU3_IDR1_CONFIG_ADDR_WIDTH_SHFT 0x10 + +#define HWIO_IPA_0_GSI_TOP_XPU3_IDR0_ADDR (IPA_0_GSI_TOP_XPU3_REG_BASE + 0x000003f8) +#define HWIO_IPA_0_GSI_TOP_XPU3_IDR0_PHYS (IPA_0_GSI_TOP_XPU3_REG_BASE_PHYS + 0x000003f8) +#define HWIO_IPA_0_GSI_TOP_XPU3_IDR0_OFFS (IPA_0_GSI_TOP_XPU3_REG_BASE_OFFS + 0x000003f8) +#define HWIO_IPA_0_GSI_TOP_XPU3_IDR0_RMSK 0x3ff0023 +#define HWIO_IPA_0_GSI_TOP_XPU3_IDR0_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_IDR0_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_IDR0_ADDR, HWIO_IPA_0_GSI_TOP_XPU3_IDR0_RMSK) +#define HWIO_IPA_0_GSI_TOP_XPU3_IDR0_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_IDR0_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_XPU3_IDR0_NRG_BMSK 0x3ff0000 +#define HWIO_IPA_0_GSI_TOP_XPU3_IDR0_NRG_SHFT 0x10 +#define HWIO_IPA_0_GSI_TOP_XPU3_IDR0_CLIENTREQ_HALT_ACK_HW_EN_BMSK 0x20 +#define HWIO_IPA_0_GSI_TOP_XPU3_IDR0_CLIENTREQ_HALT_ACK_HW_EN_SHFT 0x5 +#define HWIO_IPA_0_GSI_TOP_XPU3_IDR0_XPUTYPE_BMSK 0x3 +#define HWIO_IPA_0_GSI_TOP_XPU3_IDR0_XPUTYPE_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_XPU3_REV_ADDR (IPA_0_GSI_TOP_XPU3_REG_BASE + 0x000003fc) +#define HWIO_IPA_0_GSI_TOP_XPU3_REV_PHYS (IPA_0_GSI_TOP_XPU3_REG_BASE_PHYS + 0x000003fc) +#define HWIO_IPA_0_GSI_TOP_XPU3_REV_OFFS (IPA_0_GSI_TOP_XPU3_REG_BASE_OFFS + 0x000003fc) +#define HWIO_IPA_0_GSI_TOP_XPU3_REV_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_XPU3_REV_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_REV_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_REV_ADDR, HWIO_IPA_0_GSI_TOP_XPU3_REV_RMSK) +#define HWIO_IPA_0_GSI_TOP_XPU3_REV_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_REV_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_XPU3_REV_MAJOR_BMSK 0xf0000000 +#define HWIO_IPA_0_GSI_TOP_XPU3_REV_MAJOR_SHFT 0x1c +#define HWIO_IPA_0_GSI_TOP_XPU3_REV_MINOR_BMSK 0xfff0000 +#define HWIO_IPA_0_GSI_TOP_XPU3_REV_MINOR_SHFT 0x10 +#define HWIO_IPA_0_GSI_TOP_XPU3_REV_STEP_BMSK 0xffff +#define HWIO_IPA_0_GSI_TOP_XPU3_REV_STEP_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_XPU3_LOG_MODE_DIS_ADDR (IPA_0_GSI_TOP_XPU3_REG_BASE + 0x00000400) +#define HWIO_IPA_0_GSI_TOP_XPU3_LOG_MODE_DIS_PHYS (IPA_0_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000400) +#define HWIO_IPA_0_GSI_TOP_XPU3_LOG_MODE_DIS_OFFS (IPA_0_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000400) +#define HWIO_IPA_0_GSI_TOP_XPU3_LOG_MODE_DIS_RMSK 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_LOG_MODE_DIS_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_XPU3_LOG_MODE_DIS_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_LOG_MODE_DIS_ADDR, HWIO_IPA_0_GSI_TOP_XPU3_LOG_MODE_DIS_RMSK) +#define HWIO_IPA_0_GSI_TOP_XPU3_LOG_MODE_DIS_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_LOG_MODE_DIS_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_XPU3_LOG_MODE_DIS_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_XPU3_LOG_MODE_DIS_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_XPU3_LOG_MODE_DIS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_XPU3_LOG_MODE_DIS_ADDR,m,v,HWIO_IPA_0_GSI_TOP_XPU3_LOG_MODE_DIS_IN) +#define HWIO_IPA_0_GSI_TOP_XPU3_LOG_MODE_DIS_LOG_MODE_DIS_BMSK 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_LOG_MODE_DIS_LOG_MODE_DIS_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_XPU3_RGN_FREESTATUSr_ADDR(r) (IPA_0_GSI_TOP_XPU3_REG_BASE + 0x00000500 + 0x4 * (r)) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGN_FREESTATUSr_PHYS(r) (IPA_0_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000500 + 0x4 * (r)) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGN_FREESTATUSr_OFFS(r) (IPA_0_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000500 + 0x4 * (r)) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGN_FREESTATUSr_RMSK 0x1fffff +#define HWIO_IPA_0_GSI_TOP_XPU3_RGN_FREESTATUSr_MAXr 0 +#define HWIO_IPA_0_GSI_TOP_XPU3_RGN_FREESTATUSr_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_RGN_FREESTATUSr_INI(r) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_RGN_FREESTATUSr_ADDR(r), HWIO_IPA_0_GSI_TOP_XPU3_RGN_FREESTATUSr_RMSK) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGN_FREESTATUSr_INMI(r,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_RGN_FREESTATUSr_ADDR(r), mask) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGN_FREESTATUSr_RGFREESTATUS_BMSK 0x1fffff +#define HWIO_IPA_0_GSI_TOP_XPU3_RGN_FREESTATUSr_RGFREESTATUS_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_XPU3_SEAR0_ADDR (IPA_0_GSI_TOP_XPU3_REG_BASE + 0x00000800) +#define HWIO_IPA_0_GSI_TOP_XPU3_SEAR0_PHYS (IPA_0_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000800) +#define HWIO_IPA_0_GSI_TOP_XPU3_SEAR0_OFFS (IPA_0_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000800) +#define HWIO_IPA_0_GSI_TOP_XPU3_SEAR0_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_XPU3_SEAR0_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_SEAR0_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_SEAR0_ADDR, HWIO_IPA_0_GSI_TOP_XPU3_SEAR0_RMSK) +#define HWIO_IPA_0_GSI_TOP_XPU3_SEAR0_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_SEAR0_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_XPU3_SEAR0_ADDR_31_0_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_XPU3_SEAR0_ADDR_31_0_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_XPU3_SESR_ADDR (IPA_0_GSI_TOP_XPU3_REG_BASE + 0x00000808) +#define HWIO_IPA_0_GSI_TOP_XPU3_SESR_PHYS (IPA_0_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000808) +#define HWIO_IPA_0_GSI_TOP_XPU3_SESR_OFFS (IPA_0_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000808) +#define HWIO_IPA_0_GSI_TOP_XPU3_SESR_RMSK 0xf +#define HWIO_IPA_0_GSI_TOP_XPU3_SESR_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESR_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_SESR_ADDR, HWIO_IPA_0_GSI_TOP_XPU3_SESR_RMSK) +#define HWIO_IPA_0_GSI_TOP_XPU3_SESR_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_SESR_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_XPU3_SESR_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_XPU3_SESR_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_XPU3_SESR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_XPU3_SESR_ADDR,m,v,HWIO_IPA_0_GSI_TOP_XPU3_SESR_IN) +#define HWIO_IPA_0_GSI_TOP_XPU3_SESR_CLMULTI_BMSK 0x8 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESR_CLMULTI_SHFT 0x3 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESR_CFGMULTI_BMSK 0x4 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESR_CFGMULTI_SHFT 0x2 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESR_CLIENT_BMSK 0x2 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESR_CLIENT_SHFT 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESR_CFG_BMSK 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESR_CFG_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_XPU3_SESRRESTORE_ADDR (IPA_0_GSI_TOP_XPU3_REG_BASE + 0x0000080c) +#define HWIO_IPA_0_GSI_TOP_XPU3_SESRRESTORE_PHYS (IPA_0_GSI_TOP_XPU3_REG_BASE_PHYS + 0x0000080c) +#define HWIO_IPA_0_GSI_TOP_XPU3_SESRRESTORE_OFFS (IPA_0_GSI_TOP_XPU3_REG_BASE_OFFS + 0x0000080c) +#define HWIO_IPA_0_GSI_TOP_XPU3_SESRRESTORE_RMSK 0xf +#define HWIO_IPA_0_GSI_TOP_XPU3_SESRRESTORE_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESRRESTORE_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_SESRRESTORE_ADDR, HWIO_IPA_0_GSI_TOP_XPU3_SESRRESTORE_RMSK) +#define HWIO_IPA_0_GSI_TOP_XPU3_SESRRESTORE_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_SESRRESTORE_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_XPU3_SESRRESTORE_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_XPU3_SESRRESTORE_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_XPU3_SESRRESTORE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_XPU3_SESRRESTORE_ADDR,m,v,HWIO_IPA_0_GSI_TOP_XPU3_SESRRESTORE_IN) +#define HWIO_IPA_0_GSI_TOP_XPU3_SESRRESTORE_CLMULTI_BMSK 0x8 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESRRESTORE_CLMULTI_SHFT 0x3 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESRRESTORE_CFGMULTI_BMSK 0x4 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESRRESTORE_CFGMULTI_SHFT 0x2 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESRRESTORE_CLIENT_BMSK 0x2 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESRRESTORE_CLIENT_SHFT 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESRRESTORE_CFG_BMSK 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESRRESTORE_CFG_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR0_ADDR (IPA_0_GSI_TOP_XPU3_REG_BASE + 0x00000810) +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR0_PHYS (IPA_0_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000810) +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR0_OFFS (IPA_0_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000810) +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR0_RMSK 0x67ffff0f +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR0_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR0_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_SESYNR0_ADDR, HWIO_IPA_0_GSI_TOP_XPU3_SESYNR0_RMSK) +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR0_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_SESYNR0_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR0_AC_BMSK 0x40000000 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR0_AC_SHFT 0x1e +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR0_BURSTLEN_BMSK 0x20000000 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR0_BURSTLEN_SHFT 0x1d +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR0_ASIZE_BMSK 0x7000000 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR0_ASIZE_SHFT 0x18 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR0_ALEN_BMSK 0xff0000 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR0_ALEN_SHFT 0x10 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR0_QAD_BMSK 0xff00 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR0_QAD_SHFT 0x8 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR0_XPRIV_BMSK 0x8 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR0_XPRIV_SHFT 0x3 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR0_XINST_BMSK 0x4 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR0_XINST_SHFT 0x2 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR0_AWRITE_BMSK 0x2 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR0_AWRITE_SHFT 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR0_XPROTNS_BMSK 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR0_XPROTNS_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR1_ADDR (IPA_0_GSI_TOP_XPU3_REG_BASE + 0x00000814) +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR1_PHYS (IPA_0_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000814) +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR1_OFFS (IPA_0_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000814) +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR1_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR1_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR1_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_SESYNR1_ADDR, HWIO_IPA_0_GSI_TOP_XPU3_SESYNR1_RMSK) +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR1_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_SESYNR1_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR1_TID_BMSK 0xff000000 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR1_TID_SHFT 0x18 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR1_VMID_BMSK 0xff0000 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR1_VMID_SHFT 0x10 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR1_BID_BMSK 0xe000 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR1_BID_SHFT 0xd +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR1_PID_BMSK 0x1f00 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR1_PID_SHFT 0x8 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR1_MID_BMSK 0xff +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR1_MID_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR2_ADDR (IPA_0_GSI_TOP_XPU3_REG_BASE + 0x00000818) +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR2_PHYS (IPA_0_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000818) +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR2_OFFS (IPA_0_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000818) +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR2_RMSK 0xffffff87 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR2_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR2_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_SESYNR2_ADDR, HWIO_IPA_0_GSI_TOP_XPU3_SESYNR2_RMSK) +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR2_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_SESYNR2_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR2_BAR_BMSK 0xc0000000 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR2_BAR_SHFT 0x1e +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR2_BURST_BMSK 0x20000000 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR2_BURST_SHFT 0x1d +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR2_CACHEABLE_BMSK 0x10000000 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR2_CACHEABLE_SHFT 0x1c +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR2_DEVICE_BMSK 0x8000000 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR2_DEVICE_SHFT 0x1b +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR2_DEVICE_TYPE_BMSK 0x6000000 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR2_DEVICE_TYPE_SHFT 0x19 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR2_EARLYWRRESP_BMSK 0x1000000 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR2_EARLYWRRESP_SHFT 0x18 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR2_ERROR_BMSK 0x800000 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR2_ERROR_SHFT 0x17 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR2_EXCLUSIVE_BMSK 0x400000 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR2_EXCLUSIVE_SHFT 0x16 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR2_FULL_BMSK 0x200000 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR2_FULL_SHFT 0x15 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR2_SHARED_BMSK 0x100000 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR2_SHARED_SHFT 0x14 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR2_WRITETHROUGH_BMSK 0x80000 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR2_WRITETHROUGH_SHFT 0x13 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR2_INNERNOALLOCATE_BMSK 0x40000 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR2_INNERNOALLOCATE_SHFT 0x12 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR2_INNERCACHEABLE_BMSK 0x20000 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR2_INNERCACHEABLE_SHFT 0x11 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR2_INNERSHARED_BMSK 0x10000 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR2_INNERSHARED_SHFT 0x10 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR2_INNERTRANSIENT_BMSK 0x8000 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR2_INNERTRANSIENT_SHFT 0xf +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR2_INNERWRITETHROUGH_BMSK 0x4000 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR2_INNERWRITETHROUGH_SHFT 0xe +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR2_PORTMREL_BMSK 0x2000 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR2_PORTMREL_SHFT 0xd +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR2_ORDEREDRD_BMSK 0x1000 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR2_ORDEREDRD_SHFT 0xc +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR2_ORDEREDWR_BMSK 0x800 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR2_ORDEREDWR_SHFT 0xb +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR2_OOORD_BMSK 0x400 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR2_OOORD_SHFT 0xa +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR2_OOOWR_BMSK 0x200 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR2_OOOWR_SHFT 0x9 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR2_NOALLOCATE_BMSK 0x100 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR2_NOALLOCATE_SHFT 0x8 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR2_TRANSIENT_BMSK 0x80 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR2_TRANSIENT_SHFT 0x7 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR2_MEMTYPE_BMSK 0x7 +#define HWIO_IPA_0_GSI_TOP_XPU3_SESYNR2_MEMTYPE_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_XPU3_SEAR1_ADDR (IPA_0_GSI_TOP_XPU3_REG_BASE + 0x00000804) +#define HWIO_IPA_0_GSI_TOP_XPU3_SEAR1_PHYS (IPA_0_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000804) +#define HWIO_IPA_0_GSI_TOP_XPU3_SEAR1_OFFS (IPA_0_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000804) +#define HWIO_IPA_0_GSI_TOP_XPU3_SEAR1_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_XPU3_SEAR1_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_SEAR1_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_SEAR1_ADDR, HWIO_IPA_0_GSI_TOP_XPU3_SEAR1_RMSK) +#define HWIO_IPA_0_GSI_TOP_XPU3_SEAR1_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_SEAR1_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_XPU3_SEAR1_ADDR_63_32_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_XPU3_SEAR1_ADDR_63_32_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_XPU3_EAR0_ADDR (IPA_0_GSI_TOP_XPU3_REG_BASE + 0x00000880) +#define HWIO_IPA_0_GSI_TOP_XPU3_EAR0_PHYS (IPA_0_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000880) +#define HWIO_IPA_0_GSI_TOP_XPU3_EAR0_OFFS (IPA_0_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000880) +#define HWIO_IPA_0_GSI_TOP_XPU3_EAR0_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_XPU3_EAR0_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_EAR0_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_EAR0_ADDR, HWIO_IPA_0_GSI_TOP_XPU3_EAR0_RMSK) +#define HWIO_IPA_0_GSI_TOP_XPU3_EAR0_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_EAR0_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_XPU3_EAR0_ADDR_31_0_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_XPU3_EAR0_ADDR_31_0_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_XPU3_ESR_ADDR (IPA_0_GSI_TOP_XPU3_REG_BASE + 0x00000888) +#define HWIO_IPA_0_GSI_TOP_XPU3_ESR_PHYS (IPA_0_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000888) +#define HWIO_IPA_0_GSI_TOP_XPU3_ESR_OFFS (IPA_0_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000888) +#define HWIO_IPA_0_GSI_TOP_XPU3_ESR_RMSK 0xf +#define HWIO_IPA_0_GSI_TOP_XPU3_ESR_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESR_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_ESR_ADDR, HWIO_IPA_0_GSI_TOP_XPU3_ESR_RMSK) +#define HWIO_IPA_0_GSI_TOP_XPU3_ESR_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_ESR_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_XPU3_ESR_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_XPU3_ESR_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_XPU3_ESR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_XPU3_ESR_ADDR,m,v,HWIO_IPA_0_GSI_TOP_XPU3_ESR_IN) +#define HWIO_IPA_0_GSI_TOP_XPU3_ESR_CLMULTI_BMSK 0x8 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESR_CLMULTI_SHFT 0x3 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESR_CFGMULTI_BMSK 0x4 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESR_CFGMULTI_SHFT 0x2 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESR_CLIENT_BMSK 0x2 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESR_CLIENT_SHFT 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESR_CFG_BMSK 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESR_CFG_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_XPU3_ESRRESTORE_ADDR (IPA_0_GSI_TOP_XPU3_REG_BASE + 0x0000088c) +#define HWIO_IPA_0_GSI_TOP_XPU3_ESRRESTORE_PHYS (IPA_0_GSI_TOP_XPU3_REG_BASE_PHYS + 0x0000088c) +#define HWIO_IPA_0_GSI_TOP_XPU3_ESRRESTORE_OFFS (IPA_0_GSI_TOP_XPU3_REG_BASE_OFFS + 0x0000088c) +#define HWIO_IPA_0_GSI_TOP_XPU3_ESRRESTORE_RMSK 0xf +#define HWIO_IPA_0_GSI_TOP_XPU3_ESRRESTORE_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESRRESTORE_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_ESRRESTORE_ADDR, HWIO_IPA_0_GSI_TOP_XPU3_ESRRESTORE_RMSK) +#define HWIO_IPA_0_GSI_TOP_XPU3_ESRRESTORE_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_ESRRESTORE_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_XPU3_ESRRESTORE_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_XPU3_ESRRESTORE_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_XPU3_ESRRESTORE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_XPU3_ESRRESTORE_ADDR,m,v,HWIO_IPA_0_GSI_TOP_XPU3_ESRRESTORE_IN) +#define HWIO_IPA_0_GSI_TOP_XPU3_ESRRESTORE_CLMULTI_BMSK 0x8 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESRRESTORE_CLMULTI_SHFT 0x3 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESRRESTORE_CFGMULTI_BMSK 0x4 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESRRESTORE_CFGMULTI_SHFT 0x2 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESRRESTORE_CLIENT_BMSK 0x2 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESRRESTORE_CLIENT_SHFT 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESRRESTORE_CFG_BMSK 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESRRESTORE_CFG_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR0_ADDR (IPA_0_GSI_TOP_XPU3_REG_BASE + 0x00000890) +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR0_PHYS (IPA_0_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000890) +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR0_OFFS (IPA_0_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000890) +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR0_RMSK 0x67ffff0f +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR0_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR0_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_ESYNR0_ADDR, HWIO_IPA_0_GSI_TOP_XPU3_ESYNR0_RMSK) +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR0_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_ESYNR0_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR0_AC_BMSK 0x40000000 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR0_AC_SHFT 0x1e +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR0_BURSTLEN_BMSK 0x20000000 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR0_BURSTLEN_SHFT 0x1d +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR0_ASIZE_BMSK 0x7000000 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR0_ASIZE_SHFT 0x18 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR0_ALEN_BMSK 0xff0000 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR0_ALEN_SHFT 0x10 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR0_QAD_BMSK 0xff00 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR0_QAD_SHFT 0x8 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR0_XPRIV_BMSK 0x8 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR0_XPRIV_SHFT 0x3 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR0_XINST_BMSK 0x4 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR0_XINST_SHFT 0x2 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR0_AWRITE_BMSK 0x2 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR0_AWRITE_SHFT 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR0_XPROTNS_BMSK 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR0_XPROTNS_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR1_ADDR (IPA_0_GSI_TOP_XPU3_REG_BASE + 0x00000894) +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR1_PHYS (IPA_0_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000894) +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR1_OFFS (IPA_0_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000894) +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR1_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR1_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR1_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_ESYNR1_ADDR, HWIO_IPA_0_GSI_TOP_XPU3_ESYNR1_RMSK) +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR1_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_ESYNR1_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR1_TID_BMSK 0xff000000 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR1_TID_SHFT 0x18 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR1_VMID_BMSK 0xff0000 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR1_VMID_SHFT 0x10 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR1_BID_BMSK 0xe000 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR1_BID_SHFT 0xd +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR1_PID_BMSK 0x1f00 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR1_PID_SHFT 0x8 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR1_MID_BMSK 0xff +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR1_MID_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR2_ADDR (IPA_0_GSI_TOP_XPU3_REG_BASE + 0x00000898) +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR2_PHYS (IPA_0_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000898) +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR2_OFFS (IPA_0_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000898) +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR2_RMSK 0xffffff87 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR2_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR2_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_ESYNR2_ADDR, HWIO_IPA_0_GSI_TOP_XPU3_ESYNR2_RMSK) +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR2_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_ESYNR2_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR2_BAR_BMSK 0xc0000000 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR2_BAR_SHFT 0x1e +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR2_BURST_BMSK 0x20000000 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR2_BURST_SHFT 0x1d +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR2_CACHEABLE_BMSK 0x10000000 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR2_CACHEABLE_SHFT 0x1c +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR2_DEVICE_BMSK 0x8000000 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR2_DEVICE_SHFT 0x1b +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR2_DEVICE_TYPE_BMSK 0x6000000 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR2_DEVICE_TYPE_SHFT 0x19 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR2_EARLYWRRESP_BMSK 0x1000000 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR2_EARLYWRRESP_SHFT 0x18 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR2_ERROR_BMSK 0x800000 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR2_ERROR_SHFT 0x17 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR2_EXCLUSIVE_BMSK 0x400000 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR2_EXCLUSIVE_SHFT 0x16 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR2_FULL_BMSK 0x200000 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR2_FULL_SHFT 0x15 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR2_SHARED_BMSK 0x100000 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR2_SHARED_SHFT 0x14 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR2_WRITETHROUGH_BMSK 0x80000 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR2_WRITETHROUGH_SHFT 0x13 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR2_INNERNOALLOCATE_BMSK 0x40000 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR2_INNERNOALLOCATE_SHFT 0x12 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR2_INNERCACHEABLE_BMSK 0x20000 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR2_INNERCACHEABLE_SHFT 0x11 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR2_INNERSHARED_BMSK 0x10000 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR2_INNERSHARED_SHFT 0x10 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR2_INNERTRANSIENT_BMSK 0x8000 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR2_INNERTRANSIENT_SHFT 0xf +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR2_INNERWRITETHROUGH_BMSK 0x4000 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR2_INNERWRITETHROUGH_SHFT 0xe +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR2_PORTMREL_BMSK 0x2000 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR2_PORTMREL_SHFT 0xd +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR2_ORDEREDRD_BMSK 0x1000 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR2_ORDEREDRD_SHFT 0xc +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR2_ORDEREDWR_BMSK 0x800 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR2_ORDEREDWR_SHFT 0xb +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR2_OOORD_BMSK 0x400 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR2_OOORD_SHFT 0xa +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR2_OOOWR_BMSK 0x200 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR2_OOOWR_SHFT 0x9 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR2_NOALLOCATE_BMSK 0x100 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR2_NOALLOCATE_SHFT 0x8 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR2_TRANSIENT_BMSK 0x80 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR2_TRANSIENT_SHFT 0x7 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR2_MEMTYPE_BMSK 0x7 +#define HWIO_IPA_0_GSI_TOP_XPU3_ESYNR2_MEMTYPE_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_XPU3_EAR1_ADDR (IPA_0_GSI_TOP_XPU3_REG_BASE + 0x00000884) +#define HWIO_IPA_0_GSI_TOP_XPU3_EAR1_PHYS (IPA_0_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000884) +#define HWIO_IPA_0_GSI_TOP_XPU3_EAR1_OFFS (IPA_0_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000884) +#define HWIO_IPA_0_GSI_TOP_XPU3_EAR1_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_XPU3_EAR1_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_EAR1_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_EAR1_ADDR, HWIO_IPA_0_GSI_TOP_XPU3_EAR1_RMSK) +#define HWIO_IPA_0_GSI_TOP_XPU3_EAR1_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_EAR1_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_XPU3_EAR1_ADDR_63_32_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_XPU3_EAR1_ADDR_63_32_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_EAR0_ADDR (IPA_0_GSI_TOP_XPU3_REG_BASE + 0x00000880) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_EAR0_PHYS (IPA_0_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000880) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_EAR0_OFFS (IPA_0_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000880) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_EAR0_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_EAR0_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_EAR0_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_QAD0_EAR0_ADDR, HWIO_IPA_0_GSI_TOP_XPU3_QAD0_EAR0_RMSK) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_EAR0_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_QAD0_EAR0_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_EAR0_ADDR_31_0_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_EAR0_ADDR_31_0_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESR_ADDR (IPA_0_GSI_TOP_XPU3_REG_BASE + 0x00000888) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESR_PHYS (IPA_0_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000888) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESR_OFFS (IPA_0_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000888) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESR_RMSK 0xf +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESR_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESR_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESR_ADDR, HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESR_RMSK) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESR_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESR_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESR_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESR_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESR_ADDR,m,v,HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESR_IN) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESR_CLMULTI_BMSK 0x8 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESR_CLMULTI_SHFT 0x3 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESR_CFGMULTI_BMSK 0x4 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESR_CFGMULTI_SHFT 0x2 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESR_CLIENT_BMSK 0x2 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESR_CLIENT_SHFT 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESR_CFG_BMSK 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESR_CFG_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESRRESTORE_ADDR (IPA_0_GSI_TOP_XPU3_REG_BASE + 0x0000088c) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESRRESTORE_PHYS (IPA_0_GSI_TOP_XPU3_REG_BASE_PHYS + 0x0000088c) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESRRESTORE_OFFS (IPA_0_GSI_TOP_XPU3_REG_BASE_OFFS + 0x0000088c) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESRRESTORE_RMSK 0xf +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESRRESTORE_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESRRESTORE_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESRRESTORE_ADDR, HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESRRESTORE_RMSK) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESRRESTORE_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESRRESTORE_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESRRESTORE_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESRRESTORE_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESRRESTORE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESRRESTORE_ADDR,m,v,HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESRRESTORE_IN) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESRRESTORE_CLMULTI_BMSK 0x8 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESRRESTORE_CLMULTI_SHFT 0x3 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESRRESTORE_CFGMULTI_BMSK 0x4 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESRRESTORE_CFGMULTI_SHFT 0x2 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESRRESTORE_CLIENT_BMSK 0x2 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESRRESTORE_CLIENT_SHFT 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESRRESTORE_CFG_BMSK 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESRRESTORE_CFG_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR0_ADDR (IPA_0_GSI_TOP_XPU3_REG_BASE + 0x00000890) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR0_PHYS (IPA_0_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000890) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR0_OFFS (IPA_0_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000890) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR0_RMSK 0x67ffff0f +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR0_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR0_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR0_ADDR, HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR0_RMSK) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR0_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR0_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR0_AC_BMSK 0x40000000 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR0_AC_SHFT 0x1e +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR0_BURSTLEN_BMSK 0x20000000 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR0_BURSTLEN_SHFT 0x1d +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR0_ASIZE_BMSK 0x7000000 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR0_ASIZE_SHFT 0x18 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR0_ALEN_BMSK 0xff0000 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR0_ALEN_SHFT 0x10 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR0_QAD_BMSK 0xff00 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR0_QAD_SHFT 0x8 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR0_XPRIV_BMSK 0x8 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR0_XPRIV_SHFT 0x3 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR0_XINST_BMSK 0x4 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR0_XINST_SHFT 0x2 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR0_AWRITE_BMSK 0x2 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR0_AWRITE_SHFT 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR0_XPROTNS_BMSK 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR0_XPROTNS_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR1_ADDR (IPA_0_GSI_TOP_XPU3_REG_BASE + 0x00000894) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR1_PHYS (IPA_0_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000894) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR1_OFFS (IPA_0_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000894) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR1_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR1_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR1_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR1_ADDR, HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR1_RMSK) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR1_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR1_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR1_TID_BMSK 0xff000000 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR1_TID_SHFT 0x18 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR1_VMID_BMSK 0xff0000 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR1_VMID_SHFT 0x10 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR1_BID_BMSK 0xe000 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR1_BID_SHFT 0xd +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR1_PID_BMSK 0x1f00 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR1_PID_SHFT 0x8 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR1_MID_BMSK 0xff +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR1_MID_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR2_ADDR (IPA_0_GSI_TOP_XPU3_REG_BASE + 0x00000898) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR2_PHYS (IPA_0_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000898) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR2_OFFS (IPA_0_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000898) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR2_RMSK 0xffffff87 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR2_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR2_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR2_ADDR, HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR2_RMSK) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR2_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR2_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR2_BAR_BMSK 0xc0000000 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR2_BAR_SHFT 0x1e +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR2_BURST_BMSK 0x20000000 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR2_BURST_SHFT 0x1d +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR2_CACHEABLE_BMSK 0x10000000 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR2_CACHEABLE_SHFT 0x1c +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR2_DEVICE_BMSK 0x8000000 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR2_DEVICE_SHFT 0x1b +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR2_DEVICE_TYPE_BMSK 0x6000000 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR2_DEVICE_TYPE_SHFT 0x19 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR2_EARLYWRRESP_BMSK 0x1000000 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR2_EARLYWRRESP_SHFT 0x18 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR2_ERROR_BMSK 0x800000 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR2_ERROR_SHFT 0x17 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR2_EXCLUSIVE_BMSK 0x400000 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR2_EXCLUSIVE_SHFT 0x16 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR2_FULL_BMSK 0x200000 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR2_FULL_SHFT 0x15 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR2_SHARED_BMSK 0x100000 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR2_SHARED_SHFT 0x14 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR2_WRITETHROUGH_BMSK 0x80000 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR2_WRITETHROUGH_SHFT 0x13 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR2_INNERNOALLOCATE_BMSK 0x40000 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR2_INNERNOALLOCATE_SHFT 0x12 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR2_INNERCACHEABLE_BMSK 0x20000 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR2_INNERCACHEABLE_SHFT 0x11 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR2_INNERSHARED_BMSK 0x10000 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR2_INNERSHARED_SHFT 0x10 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR2_INNERTRANSIENT_BMSK 0x8000 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR2_INNERTRANSIENT_SHFT 0xf +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR2_INNERWRITETHROUGH_BMSK 0x4000 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR2_INNERWRITETHROUGH_SHFT 0xe +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR2_PORTMREL_BMSK 0x2000 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR2_PORTMREL_SHFT 0xd +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR2_ORDEREDRD_BMSK 0x1000 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR2_ORDEREDRD_SHFT 0xc +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR2_ORDEREDWR_BMSK 0x800 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR2_ORDEREDWR_SHFT 0xb +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR2_OOORD_BMSK 0x400 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR2_OOORD_SHFT 0xa +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR2_OOOWR_BMSK 0x200 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR2_OOOWR_SHFT 0x9 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR2_NOALLOCATE_BMSK 0x100 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR2_NOALLOCATE_SHFT 0x8 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR2_TRANSIENT_BMSK 0x80 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR2_TRANSIENT_SHFT 0x7 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR2_MEMTYPE_BMSK 0x7 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_ESYNR2_MEMTYPE_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_EAR1_ADDR (IPA_0_GSI_TOP_XPU3_REG_BASE + 0x00000884) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_EAR1_PHYS (IPA_0_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000884) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_EAR1_OFFS (IPA_0_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000884) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_EAR1_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_EAR1_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_EAR1_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_QAD0_EAR1_ADDR, HWIO_IPA_0_GSI_TOP_XPU3_QAD0_EAR1_RMSK) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_EAR1_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_QAD0_EAR1_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_EAR1_ADDR_63_32_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD0_EAR1_ADDR_63_32_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_EAR0_ADDR (IPA_0_GSI_TOP_XPU3_REG_BASE + 0x00000880) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_EAR0_PHYS (IPA_0_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000880) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_EAR0_OFFS (IPA_0_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000880) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_EAR0_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_EAR0_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_EAR0_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_QAD1_EAR0_ADDR, HWIO_IPA_0_GSI_TOP_XPU3_QAD1_EAR0_RMSK) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_EAR0_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_QAD1_EAR0_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_EAR0_ADDR_31_0_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_EAR0_ADDR_31_0_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESR_ADDR (IPA_0_GSI_TOP_XPU3_REG_BASE + 0x00000888) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESR_PHYS (IPA_0_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000888) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESR_OFFS (IPA_0_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000888) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESR_RMSK 0xf +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESR_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESR_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESR_ADDR, HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESR_RMSK) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESR_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESR_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESR_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESR_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESR_ADDR,m,v,HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESR_IN) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESR_CLMULTI_BMSK 0x8 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESR_CLMULTI_SHFT 0x3 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESR_CFGMULTI_BMSK 0x4 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESR_CFGMULTI_SHFT 0x2 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESR_CLIENT_BMSK 0x2 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESR_CLIENT_SHFT 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESR_CFG_BMSK 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESR_CFG_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESRRESTORE_ADDR (IPA_0_GSI_TOP_XPU3_REG_BASE + 0x0000088c) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESRRESTORE_PHYS (IPA_0_GSI_TOP_XPU3_REG_BASE_PHYS + 0x0000088c) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESRRESTORE_OFFS (IPA_0_GSI_TOP_XPU3_REG_BASE_OFFS + 0x0000088c) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESRRESTORE_RMSK 0xf +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESRRESTORE_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESRRESTORE_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESRRESTORE_ADDR, HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESRRESTORE_RMSK) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESRRESTORE_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESRRESTORE_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESRRESTORE_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESRRESTORE_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESRRESTORE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESRRESTORE_ADDR,m,v,HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESRRESTORE_IN) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESRRESTORE_CLMULTI_BMSK 0x8 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESRRESTORE_CLMULTI_SHFT 0x3 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESRRESTORE_CFGMULTI_BMSK 0x4 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESRRESTORE_CFGMULTI_SHFT 0x2 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESRRESTORE_CLIENT_BMSK 0x2 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESRRESTORE_CLIENT_SHFT 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESRRESTORE_CFG_BMSK 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESRRESTORE_CFG_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR0_ADDR (IPA_0_GSI_TOP_XPU3_REG_BASE + 0x00000890) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR0_PHYS (IPA_0_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000890) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR0_OFFS (IPA_0_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000890) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR0_RMSK 0x67ffff0f +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR0_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR0_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR0_ADDR, HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR0_RMSK) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR0_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR0_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR0_AC_BMSK 0x40000000 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR0_AC_SHFT 0x1e +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR0_BURSTLEN_BMSK 0x20000000 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR0_BURSTLEN_SHFT 0x1d +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR0_ASIZE_BMSK 0x7000000 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR0_ASIZE_SHFT 0x18 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR0_ALEN_BMSK 0xff0000 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR0_ALEN_SHFT 0x10 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR0_QAD_BMSK 0xff00 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR0_QAD_SHFT 0x8 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR0_XPRIV_BMSK 0x8 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR0_XPRIV_SHFT 0x3 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR0_XINST_BMSK 0x4 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR0_XINST_SHFT 0x2 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR0_AWRITE_BMSK 0x2 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR0_AWRITE_SHFT 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR0_XPROTNS_BMSK 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR0_XPROTNS_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR1_ADDR (IPA_0_GSI_TOP_XPU3_REG_BASE + 0x00000894) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR1_PHYS (IPA_0_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000894) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR1_OFFS (IPA_0_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000894) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR1_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR1_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR1_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR1_ADDR, HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR1_RMSK) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR1_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR1_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR1_TID_BMSK 0xff000000 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR1_TID_SHFT 0x18 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR1_VMID_BMSK 0xff0000 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR1_VMID_SHFT 0x10 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR1_BID_BMSK 0xe000 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR1_BID_SHFT 0xd +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR1_PID_BMSK 0x1f00 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR1_PID_SHFT 0x8 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR1_MID_BMSK 0xff +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR1_MID_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR2_ADDR (IPA_0_GSI_TOP_XPU3_REG_BASE + 0x00000898) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR2_PHYS (IPA_0_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000898) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR2_OFFS (IPA_0_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000898) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR2_RMSK 0xffffff87 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR2_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR2_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR2_ADDR, HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR2_RMSK) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR2_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR2_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR2_BAR_BMSK 0xc0000000 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR2_BAR_SHFT 0x1e +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR2_BURST_BMSK 0x20000000 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR2_BURST_SHFT 0x1d +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR2_CACHEABLE_BMSK 0x10000000 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR2_CACHEABLE_SHFT 0x1c +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR2_DEVICE_BMSK 0x8000000 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR2_DEVICE_SHFT 0x1b +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR2_DEVICE_TYPE_BMSK 0x6000000 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR2_DEVICE_TYPE_SHFT 0x19 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR2_EARLYWRRESP_BMSK 0x1000000 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR2_EARLYWRRESP_SHFT 0x18 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR2_ERROR_BMSK 0x800000 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR2_ERROR_SHFT 0x17 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR2_EXCLUSIVE_BMSK 0x400000 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR2_EXCLUSIVE_SHFT 0x16 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR2_FULL_BMSK 0x200000 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR2_FULL_SHFT 0x15 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR2_SHARED_BMSK 0x100000 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR2_SHARED_SHFT 0x14 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR2_WRITETHROUGH_BMSK 0x80000 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR2_WRITETHROUGH_SHFT 0x13 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR2_INNERNOALLOCATE_BMSK 0x40000 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR2_INNERNOALLOCATE_SHFT 0x12 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR2_INNERCACHEABLE_BMSK 0x20000 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR2_INNERCACHEABLE_SHFT 0x11 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR2_INNERSHARED_BMSK 0x10000 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR2_INNERSHARED_SHFT 0x10 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR2_INNERTRANSIENT_BMSK 0x8000 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR2_INNERTRANSIENT_SHFT 0xf +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR2_INNERWRITETHROUGH_BMSK 0x4000 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR2_INNERWRITETHROUGH_SHFT 0xe +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR2_PORTMREL_BMSK 0x2000 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR2_PORTMREL_SHFT 0xd +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR2_ORDEREDRD_BMSK 0x1000 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR2_ORDEREDRD_SHFT 0xc +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR2_ORDEREDWR_BMSK 0x800 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR2_ORDEREDWR_SHFT 0xb +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR2_OOORD_BMSK 0x400 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR2_OOORD_SHFT 0xa +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR2_OOOWR_BMSK 0x200 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR2_OOOWR_SHFT 0x9 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR2_NOALLOCATE_BMSK 0x100 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR2_NOALLOCATE_SHFT 0x8 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR2_TRANSIENT_BMSK 0x80 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR2_TRANSIENT_SHFT 0x7 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR2_MEMTYPE_BMSK 0x7 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_ESYNR2_MEMTYPE_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_EAR1_ADDR (IPA_0_GSI_TOP_XPU3_REG_BASE + 0x00000884) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_EAR1_PHYS (IPA_0_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000884) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_EAR1_OFFS (IPA_0_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000884) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_EAR1_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_EAR1_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_EAR1_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_QAD1_EAR1_ADDR, HWIO_IPA_0_GSI_TOP_XPU3_QAD1_EAR1_RMSK) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_EAR1_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_QAD1_EAR1_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_EAR1_ADDR_63_32_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_XPU3_QAD1_EAR1_ADDR_63_32_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_XPU3_RGN_OWNERSTATUSr_ADDR(r) (IPA_0_GSI_TOP_XPU3_REG_BASE + 0x00000900 + 0x4 * (r)) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGN_OWNERSTATUSr_PHYS(r) (IPA_0_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000900 + 0x4 * (r)) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGN_OWNERSTATUSr_OFFS(r) (IPA_0_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000900 + 0x4 * (r)) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGN_OWNERSTATUSr_RMSK 0x1fffff +#define HWIO_IPA_0_GSI_TOP_XPU3_RGN_OWNERSTATUSr_MAXr 0 +#define HWIO_IPA_0_GSI_TOP_XPU3_RGN_OWNERSTATUSr_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_RGN_OWNERSTATUSr_INI(r) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_RGN_OWNERSTATUSr_ADDR(r), HWIO_IPA_0_GSI_TOP_XPU3_RGN_OWNERSTATUSr_RMSK) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGN_OWNERSTATUSr_INMI(r,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_RGN_OWNERSTATUSr_ADDR(r), mask) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGN_OWNERSTATUSr_RGOWNERSTATUS_BMSK 0x1fffff +#define HWIO_IPA_0_GSI_TOP_XPU3_RGN_OWNERSTATUSr_RGOWNERSTATUS_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_GCR0_ADDR(n) (IPA_0_GSI_TOP_XPU3_REG_BASE + 0x00001000 + 0x80 * (n)) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_GCR0_PHYS(n) (IPA_0_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00001000 + 0x80 * (n)) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_GCR0_OFFS(n) (IPA_0_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00001000 + 0x80 * (n)) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_GCR0_RMSK 0x107 +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_GCR0_MAXn 20 +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_GCR0_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_GCR0_INI(n) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_RGn_GCR0_ADDR(n), HWIO_IPA_0_GSI_TOP_XPU3_RGn_GCR0_RMSK) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_GCR0_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_RGn_GCR0_ADDR(n), mask) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_GCR0_OUTI(n,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_XPU3_RGn_GCR0_ADDR(n),val) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_GCR0_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_XPU3_RGn_GCR0_ADDR(n),mask,val,HWIO_IPA_0_GSI_TOP_XPU3_RGn_GCR0_INI(n)) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_GCR0_RG_SEC_APPS_BMSK 0x100 +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_GCR0_RG_SEC_APPS_SHFT 0x8 +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_GCR0_RG_OWNER_BMSK 0x7 +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_GCR0_RG_OWNER_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_GCR3_ADDR(n) (IPA_0_GSI_TOP_XPU3_REG_BASE + 0x0000100c + 0x80 * (n)) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_GCR3_PHYS(n) (IPA_0_GSI_TOP_XPU3_REG_BASE_PHYS + 0x0000100c + 0x80 * (n)) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_GCR3_OFFS(n) (IPA_0_GSI_TOP_XPU3_REG_BASE_OFFS + 0x0000100c + 0x80 * (n)) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_GCR3_RMSK 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_GCR3_MAXn 20 +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_GCR3_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_GCR3_INI(n) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_RGn_GCR3_ADDR(n), HWIO_IPA_0_GSI_TOP_XPU3_RGn_GCR3_RMSK) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_GCR3_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_RGn_GCR3_ADDR(n), mask) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_GCR3_OUTI(n,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_XPU3_RGn_GCR3_ADDR(n),val) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_GCR3_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_XPU3_RGn_GCR3_ADDR(n),mask,val,HWIO_IPA_0_GSI_TOP_XPU3_RGn_GCR3_INI(n)) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_GCR3_SECURE_ACCESS_LOCK_BMSK 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_GCR3_SECURE_ACCESS_LOCK_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR0_ADDR(n) (IPA_0_GSI_TOP_XPU3_REG_BASE + 0x00001010 + 0x80 * (n)) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR0_PHYS(n) (IPA_0_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00001010 + 0x80 * (n)) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR0_OFFS(n) (IPA_0_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00001010 + 0x80 * (n)) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR0_RMSK 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR0_MAXn 20 +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR0_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR0_INI(n) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR0_ADDR(n), HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR0_RMSK) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR0_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR0_ADDR(n), mask) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR0_OUTI(n,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR0_ADDR(n),val) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR0_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR0_ADDR(n),mask,val,HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR0_INI(n)) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR0_RGSCLRDEN_APPS_BMSK 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR0_RGSCLRDEN_APPS_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR1_ADDR(n) (IPA_0_GSI_TOP_XPU3_REG_BASE + 0x00001014 + 0x80 * (n)) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR1_PHYS(n) (IPA_0_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00001014 + 0x80 * (n)) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR1_OFFS(n) (IPA_0_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00001014 + 0x80 * (n)) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR1_RMSK 0x7 +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR1_MAXn 20 +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR1_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR1_INI(n) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR1_ADDR(n), HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR1_RMSK) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR1_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR1_ADDR(n), mask) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR1_OUTI(n,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR1_ADDR(n),val) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR1_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR1_ADDR(n),mask,val,HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR1_INI(n)) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR1_RGCLRDEN_BMSK 0x7 +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR1_RGCLRDEN_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR2_ADDR(n) (IPA_0_GSI_TOP_XPU3_REG_BASE + 0x00001018 + 0x80 * (n)) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR2_PHYS(n) (IPA_0_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00001018 + 0x80 * (n)) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR2_OFFS(n) (IPA_0_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00001018 + 0x80 * (n)) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR2_RMSK 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR2_MAXn 20 +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR2_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR2_INI(n) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR2_ADDR(n), HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR2_RMSK) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR2_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR2_ADDR(n), mask) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR2_OUTI(n,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR2_ADDR(n),val) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR2_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR2_ADDR(n),mask,val,HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR2_INI(n)) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR2_RGSCLWREN_APPS_BMSK 0x1 +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR2_RGSCLWREN_APPS_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR3_ADDR(n) (IPA_0_GSI_TOP_XPU3_REG_BASE + 0x0000101c + 0x80 * (n)) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR3_PHYS(n) (IPA_0_GSI_TOP_XPU3_REG_BASE_PHYS + 0x0000101c + 0x80 * (n)) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR3_OFFS(n) (IPA_0_GSI_TOP_XPU3_REG_BASE_OFFS + 0x0000101c + 0x80 * (n)) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR3_RMSK 0x7 +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR3_MAXn 20 +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR3_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR3_INI(n) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR3_ADDR(n), HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR3_RMSK) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR3_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR3_ADDR(n), mask) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR3_OUTI(n,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR3_ADDR(n),val) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR3_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR3_ADDR(n),mask,val,HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR3_INI(n)) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR3_RGCLWREN_BMSK 0x7 +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_CR3_RGCLWREN_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_RACR_ADDR(n) (IPA_0_GSI_TOP_XPU3_REG_BASE + 0x00001040 + 0x80 * (n)) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_RACR_PHYS(n) (IPA_0_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00001040 + 0x80 * (n)) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_RACR_OFFS(n) (IPA_0_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00001040 + 0x80 * (n)) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_RACR_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_RACR_MAXn 20 +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_RACR_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_RACR_INI(n) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_RGn_RACR_ADDR(n), HWIO_IPA_0_GSI_TOP_XPU3_RGn_RACR_RMSK) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_RACR_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_RGn_RACR_ADDR(n), mask) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_RACR_OUTI(n,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_XPU3_RGn_RACR_ADDR(n),val) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_RACR_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_XPU3_RGn_RACR_ADDR(n),mask,val,HWIO_IPA_0_GSI_TOP_XPU3_RGn_RACR_INI(n)) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_RACR_RE_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_RACR_RE_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_WACR_ADDR(n) (IPA_0_GSI_TOP_XPU3_REG_BASE + 0x00001060 + 0x80 * (n)) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_WACR_PHYS(n) (IPA_0_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00001060 + 0x80 * (n)) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_WACR_OFFS(n) (IPA_0_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00001060 + 0x80 * (n)) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_WACR_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_WACR_MAXn 20 +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_WACR_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_WACR_INI(n) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_RGn_WACR_ADDR(n), HWIO_IPA_0_GSI_TOP_XPU3_RGn_WACR_RMSK) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_WACR_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_XPU3_RGn_WACR_ADDR(n), mask) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_WACR_OUTI(n,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_XPU3_RGn_WACR_ADDR(n),val) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_WACR_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_XPU3_RGn_WACR_ADDR(n),mask,val,HWIO_IPA_0_GSI_TOP_XPU3_RGn_WACR_INI(n)) +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_WACR_WE_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_XPU3_RGn_WACR_WE_SHFT 0x0 + + +#endif /* __GSI_HWIO_H__ */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.0/gsi_hwio_def.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.0/gsi_hwio_def.h new file mode 100644 index 0000000000..f82db90518 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.0/gsi_hwio_def.h @@ -0,0 +1,5152 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ + +#ifndef __GSI_HWIO_DEF_H__ +#define __GSI_HWIO_DEF_H__ +/** + @file gsi_hwio.h + @brief Auto-generated HWIO interface include file. + + This file contains HWIO register definitions for the following modules: + IPA_0_GSI_TOP_.* + + 'Include' filters applied: + 'Exclude' filters applied: RESERVED DUMMY +*/ + +/*---------------------------------------------------------------------------- + * MODULE: GSI + *--------------------------------------------------------------------------*/ + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_cfg_s +{ + u32 gsi_enable : 1; + u32 mcs_enable : 1; + u32 double_mcs_clk_freq : 1; + u32 uc_is_mcs : 1; + u32 gsi_pwr_clps : 1; + u32 bp_mtrix_disable : 1; + u32 reserved0 : 2; + u32 sleep_clk_div : 4; + u32 reserved1 : 20; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_cfg_u +{ + struct gsi_hwio_def_gsi_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_MANAGER_MCS_CODE_VER +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_manager_mcs_code_ver_s +{ + u32 ver : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_manager_mcs_code_ver_u +{ + struct gsi_hwio_def_gsi_manager_mcs_code_ver_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_ZEROS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_zeros_s +{ + u32 zeros : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_zeros_u +{ + struct gsi_hwio_def_gsi_zeros_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_PERIPH_BASE_ADDR_LSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_periph_base_addr_lsb_s +{ + u32 base_addr : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_periph_base_addr_lsb_u +{ + struct gsi_hwio_def_gsi_periph_base_addr_lsb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_PERIPH_BASE_ADDR_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_periph_base_addr_msb_s +{ + u32 base_addr : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_periph_base_addr_msb_u +{ + struct gsi_hwio_def_gsi_periph_base_addr_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_CGC_CTRL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_cgc_ctrl_s +{ + u32 region_1_hw_cgc_en : 1; + u32 region_2_hw_cgc_en : 1; + u32 region_3_hw_cgc_en : 1; + u32 region_4_hw_cgc_en : 1; + u32 region_5_hw_cgc_en : 1; + u32 region_6_hw_cgc_en : 1; + u32 region_7_hw_cgc_en : 1; + u32 region_8_hw_cgc_en : 1; + u32 region_9_hw_cgc_en : 1; + u32 region_10_hw_cgc_en : 1; + u32 region_11_hw_cgc_en : 1; + u32 region_12_hw_cgc_en : 1; + u32 region_13_hw_cgc_en : 1; + u32 region_14_hw_cgc_en : 1; + u32 region_15_hw_cgc_en : 1; + u32 region_16_hw_cgc_en : 1; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_cgc_ctrl_u +{ + struct gsi_hwio_def_gsi_cgc_ctrl_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_MOQA_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_moqa_cfg_s +{ + u32 client_req_prio : 8; + u32 client_oord : 8; + u32 client_oowr : 8; + u32 reserved0 : 8; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_moqa_cfg_u +{ + struct gsi_hwio_def_gsi_moqa_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_REE_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_ree_cfg_s +{ + u32 move_to_esc_clr_mode_trsh : 1; + u32 channel_empty_int_enable : 1; + u32 reserved0 : 6; + u32 max_burst_size : 8; + u32 reserved1 : 16; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_ree_cfg_u +{ + struct gsi_hwio_def_gsi_ree_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_PERIPH_PENDING_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_periph_pending_k_s +{ + u32 chid_bit_map : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_periph_pending_k_u +{ + struct gsi_hwio_def_gsi_periph_pending_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_MSI_CACHEATTR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_msi_cacheattr_s +{ + u32 ashared : 1; + u32 ainnershared : 1; + u32 anoallocate : 1; + u32 atransient : 1; + u32 areqpriority : 2; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_msi_cacheattr_u +{ + struct gsi_hwio_def_gsi_msi_cacheattr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_EVENT_CACHEATTR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_event_cacheattr_s +{ + u32 ashared : 1; + u32 ainnershared : 1; + u32 anoallocate : 1; + u32 atransient : 1; + u32 areqpriority : 2; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_event_cacheattr_u +{ + struct gsi_hwio_def_gsi_event_cacheattr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_DATA_CACHEATTR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_data_cacheattr_s +{ + u32 ashared : 1; + u32 ainnershared : 1; + u32 anoallocate : 1; + u32 atransient : 1; + u32 areqpriority : 2; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_data_cacheattr_u +{ + struct gsi_hwio_def_gsi_data_cacheattr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_TRE_CACHEATTR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_tre_cacheattr_s +{ + u32 ashared : 1; + u32 ainnershared : 1; + u32 anoallocate : 1; + u32 atransient : 1; + u32 areqpriority : 2; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_tre_cacheattr_u +{ + struct gsi_hwio_def_gsi_tre_cacheattr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IC_INT_WEIGHT_REE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ic_int_weight_ree_s +{ + u32 stop_ch_comp_int_weight : 4; + u32 new_re_int_weight : 4; + u32 ch_empty_int_weight : 4; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union gsi_hwio_def_ic_int_weight_ree_u +{ + struct gsi_hwio_def_ic_int_weight_ree_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IC_INT_WEIGHT_EVT_ENG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ic_int_weight_evt_eng_s +{ + u32 evnt_eng_int_weight : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union gsi_hwio_def_ic_int_weight_evt_eng_u +{ + struct gsi_hwio_def_ic_int_weight_evt_eng_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IC_INT_WEIGHT_INT_ENG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ic_int_weight_int_eng_s +{ + u32 int_eng_int_weight : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union gsi_hwio_def_ic_int_weight_int_eng_u +{ + struct gsi_hwio_def_ic_int_weight_int_eng_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IC_INT_WEIGHT_CSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ic_int_weight_csr_s +{ + u32 ch_cmd_int_weight : 4; + u32 ee_generic_int_weight : 4; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union gsi_hwio_def_ic_int_weight_csr_u +{ + struct gsi_hwio_def_ic_int_weight_csr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IC_INT_WEIGHT_TLV_ENG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ic_int_weight_tlv_eng_s +{ + u32 tlv_0_int_weight : 4; + u32 tlv_1_int_weight : 4; + u32 tlv_2_int_weight : 4; + u32 ch_not_full_int_weight : 4; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union gsi_hwio_def_ic_int_weight_tlv_eng_u +{ + struct gsi_hwio_def_ic_int_weight_tlv_eng_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IC_INT_WEIGHT_TIMER_ENG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ic_int_weight_timer_eng_s +{ + u32 timer_int_weight : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union gsi_hwio_def_ic_int_weight_timer_eng_u +{ + struct gsi_hwio_def_ic_int_weight_timer_eng_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IC_INT_WEIGHT_DB_ENG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ic_int_weight_db_eng_s +{ + u32 new_db_int_weight : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union gsi_hwio_def_ic_int_weight_db_eng_u +{ + struct gsi_hwio_def_ic_int_weight_db_eng_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IC_INT_WEIGHT_RD_WR_ENG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ic_int_weight_rd_wr_eng_s +{ + u32 read_int_weight : 4; + u32 write_int_weight : 4; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union gsi_hwio_def_ic_int_weight_rd_wr_eng_u +{ + struct gsi_hwio_def_ic_int_weight_rd_wr_eng_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IC_INT_WEIGHT_UCONTROLLER_ENG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ic_int_weight_ucontroller_eng_s +{ + u32 ucontroller_gp_int_weight : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union gsi_hwio_def_ic_int_weight_ucontroller_eng_u +{ + struct gsi_hwio_def_ic_int_weight_ucontroller_eng_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: LOW_LATENCY_ARB_WEIGHT +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_low_latency_arb_weight_s +{ + u32 ll_weight : 6; + u32 reserved0 : 2; + u32 non_ll_weight : 6; + u32 reserved1 : 2; + u32 ll_non_ll_fix_priority : 1; + u32 reserved2 : 15; +}; + +/* Union definition of register */ +union gsi_hwio_def_low_latency_arb_weight_u +{ + struct gsi_hwio_def_low_latency_arb_weight_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_MANAGER_EE_QOS_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_manager_ee_qos_n_s +{ + u32 ee_prio : 2; + u32 reserved0 : 6; + u32 max_ch_alloc : 8; + u32 max_ev_alloc : 8; + u32 reserved1 : 8; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_manager_ee_qos_n_u +{ + struct gsi_hwio_def_gsi_manager_ee_qos_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_shram_ptr_ch_cntxt_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_shram_ptr_ch_cntxt_base_addr_u +{ + struct gsi_hwio_def_gsi_shram_ptr_ch_cntxt_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_shram_ptr_ev_cntxt_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_shram_ptr_ev_cntxt_base_addr_u +{ + struct gsi_hwio_def_gsi_shram_ptr_ev_cntxt_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_shram_ptr_re_storage_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_shram_ptr_re_storage_base_addr_u +{ + struct gsi_hwio_def_gsi_shram_ptr_re_storage_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_shram_ptr_re_esc_buf_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_shram_ptr_re_esc_buf_base_addr_u +{ + struct gsi_hwio_def_gsi_shram_ptr_re_esc_buf_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_shram_ptr_ee_scrach_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_shram_ptr_ee_scrach_base_addr_u +{ + struct gsi_hwio_def_gsi_shram_ptr_ee_scrach_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_shram_ptr_func_stack_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_shram_ptr_func_stack_base_addr_u +{ + struct gsi_hwio_def_gsi_shram_ptr_func_stack_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_shram_ptr_mcs_scratch_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_shram_ptr_mcs_scratch_base_addr_u +{ + struct gsi_hwio_def_gsi_shram_ptr_mcs_scratch_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_shram_ptr_mcs_scratch1_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_shram_ptr_mcs_scratch1_base_addr_u +{ + struct gsi_hwio_def_gsi_shram_ptr_mcs_scratch1_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_shram_ptr_mcs_scratch2_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_shram_ptr_mcs_scratch2_base_addr_u +{ + struct gsi_hwio_def_gsi_shram_ptr_mcs_scratch2_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_shram_ptr_mcs_scratch3_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_shram_ptr_mcs_scratch3_base_addr_u +{ + struct gsi_hwio_def_gsi_shram_ptr_mcs_scratch3_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_shram_ptr_ch_vp_trans_table_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_shram_ptr_ch_vp_trans_table_base_addr_u +{ + struct gsi_hwio_def_gsi_shram_ptr_ch_vp_trans_table_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_shram_ptr_ev_vp_trans_table_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_shram_ptr_ev_vp_trans_table_base_addr_u +{ + struct gsi_hwio_def_gsi_shram_ptr_ev_vp_trans_table_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_shram_ptr_user_info_data_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_shram_ptr_user_info_data_base_addr_u +{ + struct gsi_hwio_def_gsi_shram_ptr_user_info_data_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_shram_ptr_ee_cmd_fifo_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_shram_ptr_ee_cmd_fifo_base_addr_u +{ + struct gsi_hwio_def_gsi_shram_ptr_ee_cmd_fifo_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_shram_ptr_ch_cmd_fifo_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_shram_ptr_ch_cmd_fifo_base_addr_u +{ + struct gsi_hwio_def_gsi_shram_ptr_ch_cmd_fifo_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_shram_ptr_eve_ed_storage_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_shram_ptr_eve_ed_storage_base_addr_u +{ + struct gsi_hwio_def_gsi_shram_ptr_eve_ed_storage_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_IRAM_PTR_CH_CMD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_iram_ptr_ch_cmd_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_iram_ptr_ch_cmd_u +{ + struct gsi_hwio_def_gsi_iram_ptr_ch_cmd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_IRAM_PTR_EE_GENERIC_CMD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_iram_ptr_ee_generic_cmd_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_iram_ptr_ee_generic_cmd_u +{ + struct gsi_hwio_def_gsi_iram_ptr_ee_generic_cmd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_IRAM_PTR_TLV_CH_NOT_FULL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_iram_ptr_tlv_ch_not_full_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_iram_ptr_tlv_ch_not_full_u +{ + struct gsi_hwio_def_gsi_iram_ptr_tlv_ch_not_full_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_IRAM_PTR_MSI_DB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_iram_ptr_msi_db_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_iram_ptr_msi_db_u +{ + struct gsi_hwio_def_gsi_iram_ptr_msi_db_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_IRAM_PTR_CH_DB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_iram_ptr_ch_db_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_iram_ptr_ch_db_u +{ + struct gsi_hwio_def_gsi_iram_ptr_ch_db_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_IRAM_PTR_EV_DB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_iram_ptr_ev_db_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_iram_ptr_ev_db_u +{ + struct gsi_hwio_def_gsi_iram_ptr_ev_db_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_IRAM_PTR_NEW_RE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_iram_ptr_new_re_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_iram_ptr_new_re_u +{ + struct gsi_hwio_def_gsi_iram_ptr_new_re_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_IRAM_PTR_CH_DIS_COMP +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_iram_ptr_ch_dis_comp_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_iram_ptr_ch_dis_comp_u +{ + struct gsi_hwio_def_gsi_iram_ptr_ch_dis_comp_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_IRAM_PTR_CH_EMPTY +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_iram_ptr_ch_empty_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_iram_ptr_ch_empty_u +{ + struct gsi_hwio_def_gsi_iram_ptr_ch_empty_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_IRAM_PTR_EVENT_GEN_COMP +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_iram_ptr_event_gen_comp_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_iram_ptr_event_gen_comp_u +{ + struct gsi_hwio_def_gsi_iram_ptr_event_gen_comp_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_iram_ptr_periph_if_tlv_in_0_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_iram_ptr_periph_if_tlv_in_0_u +{ + struct gsi_hwio_def_gsi_iram_ptr_periph_if_tlv_in_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_iram_ptr_periph_if_tlv_in_2_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_iram_ptr_periph_if_tlv_in_2_u +{ + struct gsi_hwio_def_gsi_iram_ptr_periph_if_tlv_in_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_iram_ptr_periph_if_tlv_in_1_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_iram_ptr_periph_if_tlv_in_1_u +{ + struct gsi_hwio_def_gsi_iram_ptr_periph_if_tlv_in_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_IRAM_PTR_TIMER_EXPIRED +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_iram_ptr_timer_expired_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_iram_ptr_timer_expired_u +{ + struct gsi_hwio_def_gsi_iram_ptr_timer_expired_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_IRAM_PTR_WRITE_ENG_COMP +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_iram_ptr_write_eng_comp_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_iram_ptr_write_eng_comp_u +{ + struct gsi_hwio_def_gsi_iram_ptr_write_eng_comp_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_IRAM_PTR_READ_ENG_COMP +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_iram_ptr_read_eng_comp_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_iram_ptr_read_eng_comp_u +{ + struct gsi_hwio_def_gsi_iram_ptr_read_eng_comp_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_IRAM_PTR_UC_GP_INT +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_iram_ptr_uc_gp_int_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_iram_ptr_uc_gp_int_u +{ + struct gsi_hwio_def_gsi_iram_ptr_uc_gp_int_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_IRAM_PTR_INT_MOD_STOPED +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_iram_ptr_int_mod_stoped_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_iram_ptr_int_mod_stoped_u +{ + struct gsi_hwio_def_gsi_iram_ptr_int_mod_stoped_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_IRAM_PTR_INT_NOTIFY_MCS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_iram_ptr_int_notify_mcs_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_iram_ptr_int_notify_mcs_u +{ + struct gsi_hwio_def_gsi_iram_ptr_int_notify_mcs_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_INST_RAM_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_inst_ram_n_s +{ + u32 inst_byte_0 : 8; + u32 inst_byte_1 : 8; + u32 inst_byte_2 : 8; + u32 inst_byte_3 : 8; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_inst_ram_n_u +{ + struct gsi_hwio_def_gsi_inst_ram_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_SHRAM_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_shram_n_s +{ + u32 shram : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_shram_n_u +{ + struct gsi_hwio_def_gsi_shram_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_MAP_EE_n_CH_k_VP_TABLE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_map_ee_n_ch_k_vp_table_s +{ + u32 phy_ch : 8; + u32 valid : 1; + u32 reserved0 : 23; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_map_ee_n_ch_k_vp_table_u +{ + struct gsi_hwio_def_gsi_map_ee_n_ch_k_vp_table_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_TEST_BUS_SEL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_test_bus_sel_s +{ + u32 gsi_testbus_sel : 8; + u32 reserved0 : 8; + u32 gsi_hw_events_sel : 4; + u32 reserved1 : 12; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_test_bus_sel_u +{ + struct gsi_hwio_def_gsi_test_bus_sel_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_TEST_BUS_REG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_test_bus_reg_s +{ + u32 gsi_testbus_reg : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_test_bus_reg_u +{ + struct gsi_hwio_def_gsi_test_bus_reg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_DEBUG_BUSY_REG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_debug_busy_reg_s +{ + u32 csr_busy : 1; + u32 ree_busy : 1; + u32 mcs_busy : 1; + u32 timer_busy : 1; + u32 rd_wr_busy : 1; + u32 ev_eng_busy : 1; + u32 int_eng_busy : 1; + u32 ree_pwr_clps_busy : 1; + u32 db_eng_busy : 1; + u32 dbg_cnt_busy : 1; + u32 uc_busy : 1; + u32 ic_busy : 1; + u32 sdma_busy : 1; + u32 reserved0 : 19; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_debug_busy_reg_u +{ + struct gsi_hwio_def_gsi_debug_busy_reg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_DEBUG_EVENT_PENDING_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_debug_event_pending_k_s +{ + u32 chid_bit_map : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_debug_event_pending_k_u +{ + struct gsi_hwio_def_gsi_debug_event_pending_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_DEBUG_TIMER_PENDING_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_debug_timer_pending_k_s +{ + u32 chid_bit_map : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_debug_timer_pending_k_u +{ + struct gsi_hwio_def_gsi_debug_timer_pending_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_DEBUG_RD_WR_PENDING_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_debug_rd_wr_pending_k_s +{ + u32 chid_bit_map : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_debug_rd_wr_pending_k_u +{ + struct gsi_hwio_def_gsi_debug_rd_wr_pending_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_SPARE_REG_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_spare_reg_1_s +{ + u32 fix_ieob_wrong_msk_disable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_spare_reg_1_u +{ + struct gsi_hwio_def_gsi_spare_reg_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_DEBUG_PC_FROM_SW +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_debug_pc_from_sw_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_debug_pc_from_sw_u +{ + struct gsi_hwio_def_gsi_debug_pc_from_sw_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_DEBUG_SW_STALL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_debug_sw_stall_s +{ + u32 mcs_stall : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_debug_sw_stall_u +{ + struct gsi_hwio_def_gsi_debug_sw_stall_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_DEBUG_PC_FOR_DEBUG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_debug_pc_for_debug_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_debug_pc_for_debug_u +{ + struct gsi_hwio_def_gsi_debug_pc_for_debug_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_DEBUG_QSB_LOG_SEL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_debug_qsb_log_sel_s +{ + u32 sel_write : 1; + u32 reserved0 : 7; + u32 sel_tid : 8; + u32 sel_mid : 8; + u32 reserved1 : 8; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_debug_qsb_log_sel_u +{ + struct gsi_hwio_def_gsi_debug_qsb_log_sel_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_DEBUG_QSB_LOG_CLR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_debug_qsb_log_clr_s +{ + u32 log_clr : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_debug_qsb_log_clr_u +{ + struct gsi_hwio_def_gsi_debug_qsb_log_clr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_DEBUG_QSB_LOG_ERR_TRNS_ID +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_debug_qsb_log_err_trns_id_s +{ + u32 err_write : 1; + u32 reserved0 : 7; + u32 err_tid : 8; + u32 err_mid : 8; + u32 err_saved : 1; + u32 reserved1 : 7; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_debug_qsb_log_err_trns_id_u +{ + struct gsi_hwio_def_gsi_debug_qsb_log_err_trns_id_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_DEBUG_QSB_LOG_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_debug_qsb_log_0_s +{ + u32 addr_31_0 : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_debug_qsb_log_0_u +{ + struct gsi_hwio_def_gsi_debug_qsb_log_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_DEBUG_QSB_LOG_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_debug_qsb_log_1_s +{ + u32 addr_43_32 : 12; + u32 ainnershared : 1; + u32 anoallocate : 1; + u32 ashared : 1; + u32 acacheable : 1; + u32 atransient : 1; + u32 aooord : 1; + u32 aooowr : 1; + u32 reserved0 : 1; + u32 alen : 4; + u32 asize : 4; + u32 areqpriority : 4; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_debug_qsb_log_1_u +{ + struct gsi_hwio_def_gsi_debug_qsb_log_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_DEBUG_QSB_LOG_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_debug_qsb_log_2_s +{ + u32 ammusid : 12; + u32 amemtype : 4; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_debug_qsb_log_2_u +{ + struct gsi_hwio_def_gsi_debug_qsb_log_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_DEBUG_QSB_LOG_LAST_MISC_IDn +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_debug_qsb_log_last_misc_idn_s +{ + u32 addr_20_0 : 21; + u32 write : 1; + u32 tid : 5; + u32 mid : 5; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_debug_qsb_log_last_misc_idn_u +{ + struct gsi_hwio_def_gsi_debug_qsb_log_last_misc_idn_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_DEBUG_SW_RF_n_WRITE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_debug_sw_rf_n_write_s +{ + u32 data_in : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_debug_sw_rf_n_write_u +{ + struct gsi_hwio_def_gsi_debug_sw_rf_n_write_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_DEBUG_SW_RF_n_READ +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_debug_sw_rf_n_read_s +{ + u32 rf_reg : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_debug_sw_rf_n_read_u +{ + struct gsi_hwio_def_gsi_debug_sw_rf_n_read_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_DEBUG_COUNTER_CFGn +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_debug_counter_cfgn_s +{ + u32 enable : 1; + u32 stop_at_wrap_arnd : 1; + u32 clr_at_read : 1; + u32 evnt_type : 5; + u32 ee : 4; + u32 virtual_chnl : 8; + u32 chain : 1; + u32 reserved0 : 11; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_debug_counter_cfgn_u +{ + struct gsi_hwio_def_gsi_debug_counter_cfgn_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_DEBUG_COUNTERn +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_debug_countern_s +{ + u32 counter_value : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_debug_countern_u +{ + struct gsi_hwio_def_gsi_debug_countern_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_DEBUG_SW_MSK_REG_n_SEC_k_WR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_debug_sw_msk_reg_n_sec_k_wr_s +{ + u32 data_in : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_debug_sw_msk_reg_n_sec_k_wr_u +{ + struct gsi_hwio_def_gsi_debug_sw_msk_reg_n_sec_k_wr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_debug_sw_msk_reg_n_sec_k_rd_s +{ + u32 msk_reg : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_debug_sw_msk_reg_n_sec_k_rd_u +{ + struct gsi_hwio_def_gsi_debug_sw_msk_reg_n_sec_k_rd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_DEBUG_EE_n_CH_k_VP_TABLE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_debug_ee_n_ch_k_vp_table_s +{ + u32 phy_ch : 8; + u32 valid : 1; + u32 reserved0 : 23; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_debug_ee_n_ch_k_vp_table_u +{ + struct gsi_hwio_def_gsi_debug_ee_n_ch_k_vp_table_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_DEBUG_EE_n_EV_k_VP_TABLE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_debug_ee_n_ev_k_vp_table_s +{ + u32 phy_ev_ch : 8; + u32 valid : 1; + u32 reserved0 : 23; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_debug_ee_n_ev_k_vp_table_u +{ + struct gsi_hwio_def_gsi_debug_ee_n_ev_k_vp_table_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_DEBUG_REE_PREFETCH_BUF_CH_ID +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_debug_ree_prefetch_buf_ch_id_s +{ + u32 prefetch_buf_ch_id : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_debug_ree_prefetch_buf_ch_id_u +{ + struct gsi_hwio_def_gsi_debug_ree_prefetch_buf_ch_id_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_DEBUG_REE_PREFETCH_BUF_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_debug_ree_prefetch_buf_status_s +{ + u32 prefetch_buf_status : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_debug_ree_prefetch_buf_status_u +{ + struct gsi_hwio_def_gsi_debug_ree_prefetch_buf_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_MCS_PROFILING_BP_CNT_LSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_mcs_profiling_bp_cnt_lsb_s +{ + u32 bp_cnt_lsb : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_mcs_profiling_bp_cnt_lsb_u +{ + struct gsi_hwio_def_gsi_mcs_profiling_bp_cnt_lsb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_MCS_PROFILING_BP_CNT_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_mcs_profiling_bp_cnt_msb_s +{ + u32 bp_cnt_msb : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_mcs_profiling_bp_cnt_msb_u +{ + struct gsi_hwio_def_gsi_mcs_profiling_bp_cnt_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_mcs_profiling_bp_and_pending_cnt_lsb_s +{ + u32 bp_and_pending_cnt_lsb : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_mcs_profiling_bp_and_pending_cnt_lsb_u +{ + struct gsi_hwio_def_gsi_mcs_profiling_bp_and_pending_cnt_lsb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_mcs_profiling_bp_and_pending_cnt_msb_s +{ + u32 bp_and_pending_cnt_msb : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_mcs_profiling_bp_and_pending_cnt_msb_u +{ + struct gsi_hwio_def_gsi_mcs_profiling_bp_and_pending_cnt_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_mcs_profiling_mcs_busy_cnt_lsb_s +{ + u32 mcs_busy_cnt_lsb : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_mcs_profiling_mcs_busy_cnt_lsb_u +{ + struct gsi_hwio_def_gsi_mcs_profiling_mcs_busy_cnt_lsb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_mcs_profiling_mcs_busy_cnt_msb_s +{ + u32 mcs_busy_cnt_msb : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_mcs_profiling_mcs_busy_cnt_msb_u +{ + struct gsi_hwio_def_gsi_mcs_profiling_mcs_busy_cnt_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_mcs_profiling_mcs_idle_cnt_lsb_s +{ + u32 mcs_idle_cnt_lsb : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_mcs_profiling_mcs_idle_cnt_lsb_u +{ + struct gsi_hwio_def_gsi_mcs_profiling_mcs_idle_cnt_lsb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_mcs_profiling_mcs_idle_cnt_msb_s +{ + u32 mcs_idle_cnt_msb : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_mcs_profiling_mcs_idle_cnt_msb_u +{ + struct gsi_hwio_def_gsi_mcs_profiling_mcs_idle_cnt_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_CH_k_CNTXT_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_0_s +{ + u32 chtype_protocol : 7; + u32 chtype_dir : 1; + u32 ee : 4; + u32 chid : 8; + u32 chstate : 4; + u32 element_size : 8; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_0_u +{ + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_CH_k_CNTXT_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_1_s +{ + u32 r_length : 24; + u32 erindex : 8; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_1_u +{ + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_CH_k_CNTXT_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_2_s +{ + u32 r_base_addr_lsbs : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_2_u +{ + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_CH_k_CNTXT_3 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_3_s +{ + u32 r_base_addr_msbs : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_3_u +{ + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_3_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_CH_k_CNTXT_4 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_4_s +{ + u32 read_ptr_lsb : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_4_u +{ + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_4_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_CH_k_CNTXT_5 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_5_s +{ + u32 read_ptr_msb : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_5_u +{ + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_5_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_CH_k_CNTXT_6 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_6_s +{ + u32 write_ptr_lsb : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_6_u +{ + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_6_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_CH_k_CNTXT_7 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_7_s +{ + u32 write_ptr_msb : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_7_u +{ + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_7_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_CH_k_CNTXT_8 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_8_s +{ + u32 db_msi_data : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_8_u +{ + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_8_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_CH_k_ELEM_SIZE_SHIFT +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_ch_k_elem_size_shift_s +{ + u32 elem_size_shift : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_ch_k_elem_size_shift_u +{ + struct gsi_hwio_def_ee_n_gsi_ch_k_elem_size_shift_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_ch_k_ch_almst_empty_thrshold_s +{ + u32 ch_almst_empty_thrshold : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_ch_k_ch_almst_empty_thrshold_u +{ + struct gsi_hwio_def_ee_n_gsi_ch_k_ch_almst_empty_thrshold_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_CH_k_RE_FETCH_READ_PTR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_ch_k_re_fetch_read_ptr_s +{ + u32 read_ptr : 24; + u32 reserved0 : 8; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_ch_k_re_fetch_read_ptr_u +{ + struct gsi_hwio_def_ee_n_gsi_ch_k_re_fetch_read_ptr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_ch_k_re_fetch_write_ptr_s +{ + u32 re_intr_db : 24; + u32 reserved0 : 8; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_ch_k_re_fetch_write_ptr_u +{ + struct gsi_hwio_def_ee_n_gsi_ch_k_re_fetch_write_ptr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_CH_k_QOS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_ch_k_qos_s +{ + u32 wrr_weight : 4; + u32 reserved0 : 4; + u32 max_prefetch : 1; + u32 use_db_eng : 1; + u32 prefetch_mode : 4; + u32 reserved1 : 2; + u32 empty_lvl_thrshold : 8; + u32 db_in_bytes : 1; + u32 low_latency_en : 1; + u32 reserved2 : 6; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_ch_k_qos_u +{ + struct gsi_hwio_def_ee_n_gsi_ch_k_qos_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_CH_k_SCRATCH_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_0_s +{ + u32 scratch : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_ch_k_scratch_0_u +{ + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_CH_k_SCRATCH_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_1_s +{ + u32 scratch : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_ch_k_scratch_1_u +{ + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_CH_k_SCRATCH_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_2_s +{ + u32 scratch : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_ch_k_scratch_2_u +{ + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_CH_k_SCRATCH_3 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_3_s +{ + u32 scratch : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_ch_k_scratch_3_u +{ + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_3_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_CH_k_SCRATCH_4 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_4_s +{ + u32 scratch : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_ch_k_scratch_4_u +{ + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_4_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_CH_k_SCRATCH_5 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_5_s +{ + u32 scratch : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_ch_k_scratch_5_u +{ + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_5_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_CH_k_SCRATCH_6 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_6_s +{ + u32 scratch : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_ch_k_scratch_6_u +{ + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_6_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_CH_k_SCRATCH_7 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_7_s +{ + u32 scratch : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_ch_k_scratch_7_u +{ + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_7_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_CH_k_SCRATCH_8 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_8_s +{ + u32 scratch : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_ch_k_scratch_8_u +{ + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_8_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_CH_k_SCRATCH_9 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_9_s +{ + u32 scratch : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_ch_k_scratch_9_u +{ + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_9_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_CH_k_DB_ENG_WRITE_PTR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_ch_k_db_eng_write_ptr_s +{ + u32 last_db_2_mcs : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_ch_k_db_eng_write_ptr_u +{ + struct gsi_hwio_def_ee_n_gsi_ch_k_db_eng_write_ptr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_EV_CH_k_CNTXT_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_0_s +{ + u32 chtype : 7; + u32 intype : 1; + u32 evchid : 8; + u32 ee : 4; + u32 chstate : 4; + u32 element_size : 8; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_0_u +{ + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_EV_CH_k_CNTXT_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_1_s +{ + u32 r_length : 24; + u32 reserved0 : 8; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_1_u +{ + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_EV_CH_k_CNTXT_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_2_s +{ + u32 r_base_addr_lsbs : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_2_u +{ + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_EV_CH_k_CNTXT_3 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_3_s +{ + u32 r_base_addr_msbs : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_3_u +{ + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_3_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_EV_CH_k_CNTXT_4 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_4_s +{ + u32 read_ptr_lsb : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_4_u +{ + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_4_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_EV_CH_k_CNTXT_5 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_5_s +{ + u32 read_ptr_msb : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_5_u +{ + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_5_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_EV_CH_k_CNTXT_6 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_6_s +{ + u32 write_ptr_lsb : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_6_u +{ + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_6_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_EV_CH_k_CNTXT_7 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_7_s +{ + u32 write_ptr_msb : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_7_u +{ + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_7_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_EV_CH_k_CNTXT_8 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_8_s +{ + u32 int_modt : 16; + u32 int_modc : 8; + u32 int_mod_cnt : 8; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_8_u +{ + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_8_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_EV_CH_k_CNTXT_9 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_9_s +{ + u32 intvec : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_9_u +{ + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_9_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_EV_CH_k_CNTXT_10 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_10_s +{ + u32 msi_addr_lsb : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_10_u +{ + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_10_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_EV_CH_k_CNTXT_11 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_11_s +{ + u32 msi_addr_msb : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_11_u +{ + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_11_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_EV_CH_k_CNTXT_12 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_12_s +{ + u32 rp_update_addr_lsb : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_12_u +{ + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_12_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_EV_CH_k_CNTXT_13 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_13_s +{ + u32 rp_update_addr_msb : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_13_u +{ + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_13_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_EV_CH_k_ELEM_SIZE_SHIFT +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_ev_ch_k_elem_size_shift_s +{ + u32 elem_size_shift : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_ev_ch_k_elem_size_shift_u +{ + struct gsi_hwio_def_ee_n_ev_ch_k_elem_size_shift_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_EV_CH_k_SCRATCH_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_ev_ch_k_scratch_0_s +{ + u32 scratch : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_ev_ch_k_scratch_0_u +{ + struct gsi_hwio_def_ee_n_ev_ch_k_scratch_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_EV_CH_k_SCRATCH_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_ev_ch_k_scratch_1_s +{ + u32 scratch : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_ev_ch_k_scratch_1_u +{ + struct gsi_hwio_def_ee_n_ev_ch_k_scratch_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_EV_CH_k_SCRATCH_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_ev_ch_k_scratch_2_s +{ + u32 scratch : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_ev_ch_k_scratch_2_u +{ + struct gsi_hwio_def_ee_n_ev_ch_k_scratch_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_CH_k_DOORBELL_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_ch_k_doorbell_0_s +{ + u32 write_ptr_lsb : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_ch_k_doorbell_0_u +{ + struct gsi_hwio_def_ee_n_gsi_ch_k_doorbell_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_CH_k_DOORBELL_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_ch_k_doorbell_1_s +{ + u32 write_ptr_msb : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_ch_k_doorbell_1_u +{ + struct gsi_hwio_def_ee_n_gsi_ch_k_doorbell_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_EV_CH_k_DOORBELL_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_ev_ch_k_doorbell_0_s +{ + u32 write_ptr_lsb : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_ev_ch_k_doorbell_0_u +{ + struct gsi_hwio_def_ee_n_ev_ch_k_doorbell_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_EV_CH_k_DOORBELL_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_ev_ch_k_doorbell_1_s +{ + u32 write_ptr_msb : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_ev_ch_k_doorbell_1_u +{ + struct gsi_hwio_def_ee_n_ev_ch_k_doorbell_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_status_s +{ + u32 enabled : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_status_u +{ + struct gsi_hwio_def_ee_n_gsi_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_CH_CMD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_ch_cmd_s +{ + u32 chid : 8; + u32 reserved0 : 16; + u32 opcode : 8; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_ch_cmd_u +{ + struct gsi_hwio_def_ee_n_gsi_ch_cmd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_EV_CH_CMD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_ev_ch_cmd_s +{ + u32 chid : 8; + u32 reserved0 : 16; + u32 opcode : 8; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_ev_ch_cmd_u +{ + struct gsi_hwio_def_ee_n_ev_ch_cmd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_EE_GENERIC_CMD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_ee_generic_cmd_s +{ + u32 opcode : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_ee_generic_cmd_u +{ + struct gsi_hwio_def_ee_n_gsi_ee_generic_cmd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_HW_PARAM_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_hw_param_0_s +{ + u32 gsi_ev_ch_num : 8; + u32 gsi_ch_num : 8; + u32 num_ees : 5; + u32 periph_conf_addr_bus_w : 5; + u32 periph_sec_grp : 5; + u32 use_axi_m : 1; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_hw_param_0_u +{ + struct gsi_hwio_def_ee_n_gsi_hw_param_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_HW_PARAM_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_hw_param_1_s +{ + u32 gsi_m_data_bus_w : 8; + u32 gsi_num_qad : 4; + u32 gsi_nonsec_en : 4; + u32 gsi_sec_en : 1; + u32 gsi_vmidacr_en : 1; + u32 gsi_qrib_en : 1; + u32 gsi_use_xpu : 1; + u32 gsi_num_timers : 5; + u32 gsi_use_bp_mtrix : 1; + u32 gsi_use_db_eng : 1; + u32 gsi_use_uc_if : 1; + u32 gsi_escape_buf_only : 1; + u32 gsi_simple_rd_wr : 1; + u32 gsi_blk_int_access_region_1_en : 1; + u32 gsi_blk_int_access_region_2_en : 1; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_hw_param_1_u +{ + struct gsi_hwio_def_ee_n_gsi_hw_param_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_HW_PARAM_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_hw_param_2_s +{ + u32 gsi_num_ch_per_ee : 8; + u32 gsi_iram_size : 5; + u32 gsi_ch_pend_translate : 1; + u32 gsi_ch_full_logic : 1; + u32 gsi_use_sdma : 1; + u32 gsi_sdma_n_int : 3; + u32 gsi_sdma_max_burst : 8; + u32 gsi_sdma_n_iovec : 3; + u32 gsi_use_rd_wr_eng : 1; + u32 gsi_use_inter_ee : 1; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_hw_param_2_u +{ + struct gsi_hwio_def_ee_n_gsi_hw_param_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_SW_VERSION +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_sw_version_s +{ + u32 step : 16; + u32 minor : 12; + u32 major : 4; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_sw_version_u +{ + struct gsi_hwio_def_ee_n_gsi_sw_version_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_MCS_CODE_VER +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_mcs_code_ver_s +{ + u32 ver : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_mcs_code_ver_u +{ + struct gsi_hwio_def_ee_n_gsi_mcs_code_ver_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_HW_PARAM_3 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_hw_param_3_s +{ + u32 gsi_sdma_max_os_rd : 4; + u32 gsi_sdma_max_os_wr : 4; + u32 gsi_num_prefetch_bufs : 4; + u32 gsi_m_addr_bus_w : 8; + u32 gsi_ree_max_burst_len : 5; + u32 gsi_use_irom : 1; + u32 gsi_use_vir_ch_if : 1; + u32 gsi_use_sleep_clk_div : 1; + u32 gsi_use_db_msi_mode : 1; + u32 reserved0 : 3; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_hw_param_3_u +{ + struct gsi_hwio_def_ee_n_gsi_hw_param_3_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_HW_PARAM_4 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_hw_param_4_s +{ + u32 gsi_num_ev_per_ee : 8; + u32 gsi_iram_protcol_cnt : 8; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_hw_param_4_u +{ + struct gsi_hwio_def_ee_n_gsi_hw_param_4_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_CNTXT_TYPE_IRQ +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_cntxt_type_irq_s +{ + u32 ch_ctrl : 1; + u32 ev_ctrl : 1; + u32 glob_ee : 1; + u32 ieob : 1; + u32 inter_ee_ch_ctrl : 1; + u32 inter_ee_ev_ctrl : 1; + u32 general : 1; + u32 reserved0 : 25; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_cntxt_type_irq_u +{ + struct gsi_hwio_def_ee_n_cntxt_type_irq_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_CNTXT_TYPE_IRQ_MSK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_cntxt_type_irq_msk_s +{ + u32 ch_ctrl : 1; + u32 ev_ctrl : 1; + u32 glob_ee : 1; + u32 ieob : 1; + u32 inter_ee_ch_ctrl : 1; + u32 inter_ee_ev_ctrl : 1; + u32 general : 1; + u32 reserved0 : 25; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_cntxt_type_irq_msk_u +{ + struct gsi_hwio_def_ee_n_cntxt_type_irq_msk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_CNTXT_SRC_GSI_CH_IRQ_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_k_s +{ + u32 gsi_ch_bit_map : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_k_u +{ + struct gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_msk_k_s +{ + u32 gsi_ch_bit_map_msk : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_msk_k_u +{ + struct gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_msk_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_clr_k_s +{ + u32 gsi_ch_bit_map : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_clr_k_u +{ + struct gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_clr_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_CNTXT_SRC_EV_CH_IRQ_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_k_s +{ + u32 ev_ch_bit_map : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_k_u +{ + struct gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_msk_k_s +{ + u32 ev_ch_bit_map_msk : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_msk_k_u +{ + struct gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_msk_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_clr_k_s +{ + u32 ev_ch_bit_map : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_clr_k_u +{ + struct gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_clr_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_CNTXT_SRC_IEOB_IRQ_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_cntxt_src_ieob_irq_k_s +{ + u32 ev_ch_bit_map : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_cntxt_src_ieob_irq_k_u +{ + struct gsi_hwio_def_ee_n_cntxt_src_ieob_irq_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_cntxt_src_ieob_irq_msk_k_s +{ + u32 ev_ch_bit_map_msk : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_cntxt_src_ieob_irq_msk_k_u +{ + struct gsi_hwio_def_ee_n_cntxt_src_ieob_irq_msk_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_CNTXT_SRC_IEOB_IRQ_CLR_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_cntxt_src_ieob_irq_clr_k_s +{ + u32 ev_ch_bit_map : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_cntxt_src_ieob_irq_clr_k_u +{ + struct gsi_hwio_def_ee_n_cntxt_src_ieob_irq_clr_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_CNTXT_GLOB_IRQ_STTS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_cntxt_glob_irq_stts_s +{ + u32 error_int : 1; + u32 gp_int1 : 1; + u32 gp_int2 : 1; + u32 gp_int3 : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_cntxt_glob_irq_stts_u +{ + struct gsi_hwio_def_ee_n_cntxt_glob_irq_stts_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_CNTXT_GLOB_IRQ_EN +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_cntxt_glob_irq_en_s +{ + u32 error_int : 1; + u32 gp_int1 : 1; + u32 gp_int2 : 1; + u32 gp_int3 : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_cntxt_glob_irq_en_u +{ + struct gsi_hwio_def_ee_n_cntxt_glob_irq_en_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_CNTXT_GLOB_IRQ_CLR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_cntxt_glob_irq_clr_s +{ + u32 error_int : 1; + u32 gp_int1 : 1; + u32 gp_int2 : 1; + u32 gp_int3 : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_cntxt_glob_irq_clr_u +{ + struct gsi_hwio_def_ee_n_cntxt_glob_irq_clr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_CNTXT_GSI_IRQ_STTS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_cntxt_gsi_irq_stts_s +{ + u32 gsi_break_point : 1; + u32 gsi_bus_error : 1; + u32 gsi_cmd_fifo_ovrflow : 1; + u32 gsi_mcs_stack_ovrflow : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_cntxt_gsi_irq_stts_u +{ + struct gsi_hwio_def_ee_n_cntxt_gsi_irq_stts_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_CNTXT_GSI_IRQ_EN +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_cntxt_gsi_irq_en_s +{ + u32 gsi_break_point : 1; + u32 gsi_bus_error : 1; + u32 gsi_cmd_fifo_ovrflow : 1; + u32 gsi_mcs_stack_ovrflow : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_cntxt_gsi_irq_en_u +{ + struct gsi_hwio_def_ee_n_cntxt_gsi_irq_en_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_CNTXT_GSI_IRQ_CLR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_cntxt_gsi_irq_clr_s +{ + u32 gsi_break_point : 1; + u32 gsi_bus_error : 1; + u32 gsi_cmd_fifo_ovrflow : 1; + u32 gsi_mcs_stack_ovrflow : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_cntxt_gsi_irq_clr_u +{ + struct gsi_hwio_def_ee_n_cntxt_gsi_irq_clr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_CNTXT_INTSET +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_cntxt_intset_s +{ + u32 intype : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_cntxt_intset_u +{ + struct gsi_hwio_def_ee_n_cntxt_intset_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_CNTXT_MSI_BASE_LSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_cntxt_msi_base_lsb_s +{ + u32 msi_addr_lsb : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_cntxt_msi_base_lsb_u +{ + struct gsi_hwio_def_ee_n_cntxt_msi_base_lsb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_CNTXT_MSI_BASE_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_cntxt_msi_base_msb_s +{ + u32 msi_addr_msb : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_cntxt_msi_base_msb_u +{ + struct gsi_hwio_def_ee_n_cntxt_msi_base_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_CNTXT_INT_VEC +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_cntxt_int_vec_s +{ + u32 int_vec : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_cntxt_int_vec_u +{ + struct gsi_hwio_def_ee_n_cntxt_int_vec_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_ERROR_LOG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_error_log_s +{ + u32 error_log : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_error_log_u +{ + struct gsi_hwio_def_ee_n_error_log_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_ERROR_LOG_CLR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_error_log_clr_s +{ + u32 error_log_clr : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_error_log_clr_u +{ + struct gsi_hwio_def_ee_n_error_log_clr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_CNTXT_SCRATCH_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_cntxt_scratch_0_s +{ + u32 scratch : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_cntxt_scratch_0_u +{ + struct gsi_hwio_def_ee_n_cntxt_scratch_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_CNTXT_SCRATCH_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_cntxt_scratch_1_s +{ + u32 scratch : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_cntxt_scratch_1_u +{ + struct gsi_hwio_def_ee_n_cntxt_scratch_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_MCS_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_mcs_cfg_s +{ + u32 mcs_enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_mcs_cfg_u +{ + struct gsi_hwio_def_gsi_mcs_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_TZ_FW_AUTH_LOCK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_tz_fw_auth_lock_s +{ + u32 dis_iram_write : 1; + u32 dis_debug_shram_write : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_tz_fw_auth_lock_u +{ + struct gsi_hwio_def_gsi_tz_fw_auth_lock_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_MSA_FW_AUTH_LOCK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_msa_fw_auth_lock_s +{ + u32 dis_iram_write : 1; + u32 dis_debug_shram_write : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_msa_fw_auth_lock_u +{ + struct gsi_hwio_def_gsi_msa_fw_auth_lock_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_SP_FW_AUTH_LOCK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_sp_fw_auth_lock_s +{ + u32 dis_iram_write : 1; + u32 dis_debug_shram_write : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_sp_fw_auth_lock_u +{ + struct gsi_hwio_def_gsi_sp_fw_auth_lock_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: INTER_EE_n_ORIGINATOR_EE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_inter_ee_n_originator_ee_s +{ + u32 ee_number : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union gsi_hwio_def_inter_ee_n_originator_ee_u +{ + struct gsi_hwio_def_inter_ee_n_originator_ee_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: INTER_EE_n_GSI_CH_CMD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_inter_ee_n_gsi_ch_cmd_s +{ + u32 chid : 8; + u32 reserved0 : 16; + u32 opcode : 8; +}; + +/* Union definition of register */ +union gsi_hwio_def_inter_ee_n_gsi_ch_cmd_u +{ + struct gsi_hwio_def_inter_ee_n_gsi_ch_cmd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: INTER_EE_n_EV_CH_CMD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_inter_ee_n_ev_ch_cmd_s +{ + u32 chid : 8; + u32 reserved0 : 16; + u32 opcode : 8; +}; + +/* Union definition of register */ +union gsi_hwio_def_inter_ee_n_ev_ch_cmd_u +{ + struct gsi_hwio_def_inter_ee_n_ev_ch_cmd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: INTER_EE_n_SRC_GSI_CH_IRQ_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_inter_ee_n_src_gsi_ch_irq_k_s +{ + u32 gsi_ch_bit_map : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_inter_ee_n_src_gsi_ch_irq_k_u +{ + struct gsi_hwio_def_inter_ee_n_src_gsi_ch_irq_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_inter_ee_n_src_gsi_ch_irq_msk_k_s +{ + u32 gsi_ch_bit_map_msk : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_inter_ee_n_src_gsi_ch_irq_msk_k_u +{ + struct gsi_hwio_def_inter_ee_n_src_gsi_ch_irq_msk_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: INTER_EE_n_SRC_GSI_CH_IRQ_CLR_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_inter_ee_n_src_gsi_ch_irq_clr_k_s +{ + u32 gsi_ch_bit_map : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_inter_ee_n_src_gsi_ch_irq_clr_k_u +{ + struct gsi_hwio_def_inter_ee_n_src_gsi_ch_irq_clr_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: INTER_EE_n_SRC_EV_CH_IRQ_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_inter_ee_n_src_ev_ch_irq_k_s +{ + u32 ev_ch_bit_map : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_inter_ee_n_src_ev_ch_irq_k_u +{ + struct gsi_hwio_def_inter_ee_n_src_ev_ch_irq_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: INTER_EE_n_SRC_EV_CH_IRQ_MSK_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_inter_ee_n_src_ev_ch_irq_msk_k_s +{ + u32 ev_ch_bit_map_msk : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_inter_ee_n_src_ev_ch_irq_msk_k_u +{ + struct gsi_hwio_def_inter_ee_n_src_ev_ch_irq_msk_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: INTER_EE_n_SRC_EV_CH_IRQ_CLR_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_inter_ee_n_src_ev_ch_irq_clr_k_s +{ + u32 ev_ch_bit_map : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_inter_ee_n_src_ev_ch_irq_clr_k_u +{ + struct gsi_hwio_def_inter_ee_n_src_ev_ch_irq_clr_k_s def; + u32 value; +}; + +/*---------------------------------------------------------------------------- + * MODULE: IPA_0_GSI_TOP_XPU3 + *--------------------------------------------------------------------------*/ + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_XPU3_GCR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ipa_0_gsi_top_xpu3_gcr0_s +{ + u32 aaden : 1; + u32 aalog_mode_dis : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union gsi_hwio_def_ipa_0_gsi_top_xpu3_gcr0_u +{ + struct gsi_hwio_def_ipa_0_gsi_top_xpu3_gcr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_XPU3_SCR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ipa_0_gsi_top_xpu3_scr0_s +{ + u32 scfgere : 1; + u32 sclere : 1; + u32 scfgeie : 1; + u32 scleie : 1; + u32 reserved0 : 4; + u32 dynamic_clk_en : 1; + u32 reserved1 : 23; +}; + +/* Union definition of register */ +union gsi_hwio_def_ipa_0_gsi_top_xpu3_scr0_u +{ + struct gsi_hwio_def_ipa_0_gsi_top_xpu3_scr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_XPU3_CR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ipa_0_gsi_top_xpu3_cr0_s +{ + u32 cfgere : 1; + u32 clere : 1; + u32 cfgeie : 1; + u32 cleie : 1; + u32 reserved0 : 3; + u32 vmiden : 1; + u32 dynamic_clk_en : 1; + u32 reserved1 : 23; +}; + +/* Union definition of register */ +union gsi_hwio_def_ipa_0_gsi_top_xpu3_cr0_u +{ + struct gsi_hwio_def_ipa_0_gsi_top_xpu3_cr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_XPU3_RPU_ACR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ipa_0_gsi_top_xpu3_rpu_acr0_s +{ + u32 suvmid : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ipa_0_gsi_top_xpu3_rpu_acr0_u +{ + struct gsi_hwio_def_ipa_0_gsi_top_xpu3_rpu_acr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_XPU3_QAD0_GCR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ipa_0_gsi_top_xpu3_qad0_gcr0_s +{ + u32 qad0den : 1; + u32 qad0log_mode_dis : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union gsi_hwio_def_ipa_0_gsi_top_xpu3_qad0_gcr0_u +{ + struct gsi_hwio_def_ipa_0_gsi_top_xpu3_qad0_gcr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_XPU3_QAD0_CR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ipa_0_gsi_top_xpu3_qad0_cr0_s +{ + u32 cfgere : 1; + u32 clere : 1; + u32 cfgeie : 1; + u32 cleie : 1; + u32 reserved0 : 4; + u32 dynamic_clk_en : 1; + u32 reserved1 : 23; +}; + +/* Union definition of register */ +union gsi_hwio_def_ipa_0_gsi_top_xpu3_qad0_cr0_u +{ + struct gsi_hwio_def_ipa_0_gsi_top_xpu3_qad0_cr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_XPU3_QAD1_GCR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ipa_0_gsi_top_xpu3_qad1_gcr0_s +{ + u32 qad1den : 1; + u32 qad1log_mode_dis : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union gsi_hwio_def_ipa_0_gsi_top_xpu3_qad1_gcr0_u +{ + struct gsi_hwio_def_ipa_0_gsi_top_xpu3_qad1_gcr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_XPU3_QAD1_CR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ipa_0_gsi_top_xpu3_qad1_cr0_s +{ + u32 cfgere : 1; + u32 clere : 1; + u32 cfgeie : 1; + u32 cleie : 1; + u32 reserved0 : 4; + u32 dynamic_clk_en : 1; + u32 reserved1 : 23; +}; + +/* Union definition of register */ +union gsi_hwio_def_ipa_0_gsi_top_xpu3_qad1_cr0_u +{ + struct gsi_hwio_def_ipa_0_gsi_top_xpu3_qad1_cr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_XPU3_IDR3 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ipa_0_gsi_top_xpu3_idr3_s +{ + u32 nvmid : 8; + u32 mv : 1; + u32 pt : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union gsi_hwio_def_ipa_0_gsi_top_xpu3_idr3_u +{ + struct gsi_hwio_def_ipa_0_gsi_top_xpu3_idr3_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_XPU3_IDR2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ipa_0_gsi_top_xpu3_idr2_s +{ + u32 num_qad : 4; + u32 reserved0 : 4; + u32 vmidacr_en : 8; + u32 sec_en : 8; + u32 nonsec_en : 8; +}; + +/* Union definition of register */ +union gsi_hwio_def_ipa_0_gsi_top_xpu3_idr2_u +{ + struct gsi_hwio_def_ipa_0_gsi_top_xpu3_idr2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_XPU3_IDR1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ipa_0_gsi_top_xpu3_idr1_s +{ + u32 reserved0 : 16; + u32 config_addr_width : 6; + u32 reserved1 : 2; + u32 client_addr_width : 6; + u32 reserved2 : 2; +}; + +/* Union definition of register */ +union gsi_hwio_def_ipa_0_gsi_top_xpu3_idr1_u +{ + struct gsi_hwio_def_ipa_0_gsi_top_xpu3_idr1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_XPU3_IDR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ipa_0_gsi_top_xpu3_idr0_s +{ + u32 xputype : 2; + u32 reserved0 : 3; + u32 clientreq_halt_ack_hw_en : 1; + u32 reserved1 : 10; + u32 nrg : 10; + u32 reserved2 : 6; +}; + +/* Union definition of register */ +union gsi_hwio_def_ipa_0_gsi_top_xpu3_idr0_u +{ + struct gsi_hwio_def_ipa_0_gsi_top_xpu3_idr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_XPU3_REV +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ipa_0_gsi_top_xpu3_rev_s +{ + u32 step : 16; + u32 minor : 12; + u32 major : 4; +}; + +/* Union definition of register */ +union gsi_hwio_def_ipa_0_gsi_top_xpu3_rev_u +{ + struct gsi_hwio_def_ipa_0_gsi_top_xpu3_rev_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_XPU3_LOG_MODE_DIS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ipa_0_gsi_top_xpu3_log_mode_dis_s +{ + u32 log_mode_dis : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union gsi_hwio_def_ipa_0_gsi_top_xpu3_log_mode_dis_u +{ + struct gsi_hwio_def_ipa_0_gsi_top_xpu3_log_mode_dis_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_XPU3_RGN_FREESTATUSr +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ipa_0_gsi_top_xpu3_rgn_freestatusr_s +{ + u32 rgfreestatus : 21; + u32 reserved0 : 11; +}; + +/* Union definition of register */ +union gsi_hwio_def_ipa_0_gsi_top_xpu3_rgn_freestatusr_u +{ + struct gsi_hwio_def_ipa_0_gsi_top_xpu3_rgn_freestatusr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_XPU3_SEAR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ipa_0_gsi_top_xpu3_sear0_s +{ + u32 addr_31_0 : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ipa_0_gsi_top_xpu3_sear0_u +{ + struct gsi_hwio_def_ipa_0_gsi_top_xpu3_sear0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_XPU3_SESR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ipa_0_gsi_top_xpu3_sesr_s +{ + u32 cfg : 1; + u32 client : 1; + u32 cfgmulti : 1; + u32 clmulti : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union gsi_hwio_def_ipa_0_gsi_top_xpu3_sesr_u +{ + struct gsi_hwio_def_ipa_0_gsi_top_xpu3_sesr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_XPU3_SESRRESTORE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ipa_0_gsi_top_xpu3_sesrrestore_s +{ + u32 cfg : 1; + u32 client : 1; + u32 cfgmulti : 1; + u32 clmulti : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union gsi_hwio_def_ipa_0_gsi_top_xpu3_sesrrestore_u +{ + struct gsi_hwio_def_ipa_0_gsi_top_xpu3_sesrrestore_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_XPU3_SESYNR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ipa_0_gsi_top_xpu3_sesynr0_s +{ + u32 xprotns : 1; + u32 awrite : 1; + u32 xinst : 1; + u32 xpriv : 1; + u32 reserved0 : 4; + u32 qad : 8; + u32 alen : 8; + u32 asize : 3; + u32 reserved1 : 2; + u32 burstlen : 1; + u32 ac : 1; + u32 reserved2 : 1; +}; + +/* Union definition of register */ +union gsi_hwio_def_ipa_0_gsi_top_xpu3_sesynr0_u +{ + struct gsi_hwio_def_ipa_0_gsi_top_xpu3_sesynr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_XPU3_SESYNR1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ipa_0_gsi_top_xpu3_sesynr1_s +{ + u32 mid : 8; + u32 pid : 5; + u32 bid : 3; + u32 vmid : 8; + u32 tid : 8; +}; + +/* Union definition of register */ +union gsi_hwio_def_ipa_0_gsi_top_xpu3_sesynr1_u +{ + struct gsi_hwio_def_ipa_0_gsi_top_xpu3_sesynr1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_XPU3_SESYNR2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ipa_0_gsi_top_xpu3_sesynr2_s +{ + u32 memtype : 3; + u32 reserved0 : 4; + u32 transient : 1; + u32 noallocate : 1; + u32 ooowr : 1; + u32 ooord : 1; + u32 orderedwr : 1; + u32 orderedrd : 1; + u32 portmrel : 1; + u32 innerwritethrough : 1; + u32 innertransient : 1; + u32 innershared : 1; + u32 innercacheable : 1; + u32 innernoallocate : 1; + u32 writethrough : 1; + u32 shared : 1; + u32 full : 1; + u32 exclusive : 1; + u32 error : 1; + u32 earlywrresp : 1; + u32 device_type : 2; + u32 device : 1; + u32 cacheable : 1; + u32 burst : 1; + u32 bar : 2; +}; + +/* Union definition of register */ +union gsi_hwio_def_ipa_0_gsi_top_xpu3_sesynr2_u +{ + struct gsi_hwio_def_ipa_0_gsi_top_xpu3_sesynr2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_XPU3_SEAR1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ipa_0_gsi_top_xpu3_sear1_s +{ + u32 addr_63_32 : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ipa_0_gsi_top_xpu3_sear1_u +{ + struct gsi_hwio_def_ipa_0_gsi_top_xpu3_sear1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_XPU3_EAR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ipa_0_gsi_top_xpu3_ear0_s +{ + u32 addr_31_0 : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ipa_0_gsi_top_xpu3_ear0_u +{ + struct gsi_hwio_def_ipa_0_gsi_top_xpu3_ear0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_XPU3_ESR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ipa_0_gsi_top_xpu3_esr_s +{ + u32 cfg : 1; + u32 client : 1; + u32 cfgmulti : 1; + u32 clmulti : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union gsi_hwio_def_ipa_0_gsi_top_xpu3_esr_u +{ + struct gsi_hwio_def_ipa_0_gsi_top_xpu3_esr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_XPU3_ESRRESTORE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ipa_0_gsi_top_xpu3_esrrestore_s +{ + u32 cfg : 1; + u32 client : 1; + u32 cfgmulti : 1; + u32 clmulti : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union gsi_hwio_def_ipa_0_gsi_top_xpu3_esrrestore_u +{ + struct gsi_hwio_def_ipa_0_gsi_top_xpu3_esrrestore_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_XPU3_ESYNR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ipa_0_gsi_top_xpu3_esynr0_s +{ + u32 xprotns : 1; + u32 awrite : 1; + u32 xinst : 1; + u32 xpriv : 1; + u32 reserved0 : 4; + u32 qad : 8; + u32 alen : 8; + u32 asize : 3; + u32 reserved1 : 2; + u32 burstlen : 1; + u32 ac : 1; + u32 reserved2 : 1; +}; + +/* Union definition of register */ +union gsi_hwio_def_ipa_0_gsi_top_xpu3_esynr0_u +{ + struct gsi_hwio_def_ipa_0_gsi_top_xpu3_esynr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_XPU3_ESYNR1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ipa_0_gsi_top_xpu3_esynr1_s +{ + u32 mid : 8; + u32 pid : 5; + u32 bid : 3; + u32 vmid : 8; + u32 tid : 8; +}; + +/* Union definition of register */ +union gsi_hwio_def_ipa_0_gsi_top_xpu3_esynr1_u +{ + struct gsi_hwio_def_ipa_0_gsi_top_xpu3_esynr1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_XPU3_ESYNR2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ipa_0_gsi_top_xpu3_esynr2_s +{ + u32 memtype : 3; + u32 reserved0 : 4; + u32 transient : 1; + u32 noallocate : 1; + u32 ooowr : 1; + u32 ooord : 1; + u32 orderedwr : 1; + u32 orderedrd : 1; + u32 portmrel : 1; + u32 innerwritethrough : 1; + u32 innertransient : 1; + u32 innershared : 1; + u32 innercacheable : 1; + u32 innernoallocate : 1; + u32 writethrough : 1; + u32 shared : 1; + u32 full : 1; + u32 exclusive : 1; + u32 error : 1; + u32 earlywrresp : 1; + u32 device_type : 2; + u32 device : 1; + u32 cacheable : 1; + u32 burst : 1; + u32 bar : 2; +}; + +/* Union definition of register */ +union gsi_hwio_def_ipa_0_gsi_top_xpu3_esynr2_u +{ + struct gsi_hwio_def_ipa_0_gsi_top_xpu3_esynr2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_XPU3_EAR1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ipa_0_gsi_top_xpu3_ear1_s +{ + u32 addr_63_32 : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ipa_0_gsi_top_xpu3_ear1_u +{ + struct gsi_hwio_def_ipa_0_gsi_top_xpu3_ear1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_XPU3_QAD0_EAR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ipa_0_gsi_top_xpu3_qad0_ear0_s +{ + u32 addr_31_0 : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ipa_0_gsi_top_xpu3_qad0_ear0_u +{ + struct gsi_hwio_def_ipa_0_gsi_top_xpu3_qad0_ear0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_XPU3_QAD0_ESR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ipa_0_gsi_top_xpu3_qad0_esr_s +{ + u32 cfg : 1; + u32 client : 1; + u32 cfgmulti : 1; + u32 clmulti : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union gsi_hwio_def_ipa_0_gsi_top_xpu3_qad0_esr_u +{ + struct gsi_hwio_def_ipa_0_gsi_top_xpu3_qad0_esr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_XPU3_QAD0_ESRRESTORE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ipa_0_gsi_top_xpu3_qad0_esrrestore_s +{ + u32 cfg : 1; + u32 client : 1; + u32 cfgmulti : 1; + u32 clmulti : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union gsi_hwio_def_ipa_0_gsi_top_xpu3_qad0_esrrestore_u +{ + struct gsi_hwio_def_ipa_0_gsi_top_xpu3_qad0_esrrestore_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_XPU3_QAD0_ESYNR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ipa_0_gsi_top_xpu3_qad0_esynr0_s +{ + u32 xprotns : 1; + u32 awrite : 1; + u32 xinst : 1; + u32 xpriv : 1; + u32 reserved0 : 4; + u32 qad : 8; + u32 alen : 8; + u32 asize : 3; + u32 reserved1 : 2; + u32 burstlen : 1; + u32 ac : 1; + u32 reserved2 : 1; +}; + +/* Union definition of register */ +union gsi_hwio_def_ipa_0_gsi_top_xpu3_qad0_esynr0_u +{ + struct gsi_hwio_def_ipa_0_gsi_top_xpu3_qad0_esynr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_XPU3_QAD0_ESYNR1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ipa_0_gsi_top_xpu3_qad0_esynr1_s +{ + u32 mid : 8; + u32 pid : 5; + u32 bid : 3; + u32 vmid : 8; + u32 tid : 8; +}; + +/* Union definition of register */ +union gsi_hwio_def_ipa_0_gsi_top_xpu3_qad0_esynr1_u +{ + struct gsi_hwio_def_ipa_0_gsi_top_xpu3_qad0_esynr1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_XPU3_QAD0_ESYNR2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ipa_0_gsi_top_xpu3_qad0_esynr2_s +{ + u32 memtype : 3; + u32 reserved0 : 4; + u32 transient : 1; + u32 noallocate : 1; + u32 ooowr : 1; + u32 ooord : 1; + u32 orderedwr : 1; + u32 orderedrd : 1; + u32 portmrel : 1; + u32 innerwritethrough : 1; + u32 innertransient : 1; + u32 innershared : 1; + u32 innercacheable : 1; + u32 innernoallocate : 1; + u32 writethrough : 1; + u32 shared : 1; + u32 full : 1; + u32 exclusive : 1; + u32 error : 1; + u32 earlywrresp : 1; + u32 device_type : 2; + u32 device : 1; + u32 cacheable : 1; + u32 burst : 1; + u32 bar : 2; +}; + +/* Union definition of register */ +union gsi_hwio_def_ipa_0_gsi_top_xpu3_qad0_esynr2_u +{ + struct gsi_hwio_def_ipa_0_gsi_top_xpu3_qad0_esynr2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_XPU3_QAD0_EAR1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ipa_0_gsi_top_xpu3_qad0_ear1_s +{ + u32 addr_63_32 : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ipa_0_gsi_top_xpu3_qad0_ear1_u +{ + struct gsi_hwio_def_ipa_0_gsi_top_xpu3_qad0_ear1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_XPU3_QAD1_EAR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ipa_0_gsi_top_xpu3_qad1_ear0_s +{ + u32 addr_31_0 : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ipa_0_gsi_top_xpu3_qad1_ear0_u +{ + struct gsi_hwio_def_ipa_0_gsi_top_xpu3_qad1_ear0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_XPU3_QAD1_ESR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ipa_0_gsi_top_xpu3_qad1_esr_s +{ + u32 cfg : 1; + u32 client : 1; + u32 cfgmulti : 1; + u32 clmulti : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union gsi_hwio_def_ipa_0_gsi_top_xpu3_qad1_esr_u +{ + struct gsi_hwio_def_ipa_0_gsi_top_xpu3_qad1_esr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_XPU3_QAD1_ESRRESTORE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ipa_0_gsi_top_xpu3_qad1_esrrestore_s +{ + u32 cfg : 1; + u32 client : 1; + u32 cfgmulti : 1; + u32 clmulti : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union gsi_hwio_def_ipa_0_gsi_top_xpu3_qad1_esrrestore_u +{ + struct gsi_hwio_def_ipa_0_gsi_top_xpu3_qad1_esrrestore_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_XPU3_QAD1_ESYNR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ipa_0_gsi_top_xpu3_qad1_esynr0_s +{ + u32 xprotns : 1; + u32 awrite : 1; + u32 xinst : 1; + u32 xpriv : 1; + u32 reserved0 : 4; + u32 qad : 8; + u32 alen : 8; + u32 asize : 3; + u32 reserved1 : 2; + u32 burstlen : 1; + u32 ac : 1; + u32 reserved2 : 1; +}; + +/* Union definition of register */ +union gsi_hwio_def_ipa_0_gsi_top_xpu3_qad1_esynr0_u +{ + struct gsi_hwio_def_ipa_0_gsi_top_xpu3_qad1_esynr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_XPU3_QAD1_ESYNR1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ipa_0_gsi_top_xpu3_qad1_esynr1_s +{ + u32 mid : 8; + u32 pid : 5; + u32 bid : 3; + u32 vmid : 8; + u32 tid : 8; +}; + +/* Union definition of register */ +union gsi_hwio_def_ipa_0_gsi_top_xpu3_qad1_esynr1_u +{ + struct gsi_hwio_def_ipa_0_gsi_top_xpu3_qad1_esynr1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_XPU3_QAD1_ESYNR2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ipa_0_gsi_top_xpu3_qad1_esynr2_s +{ + u32 memtype : 3; + u32 reserved0 : 4; + u32 transient : 1; + u32 noallocate : 1; + u32 ooowr : 1; + u32 ooord : 1; + u32 orderedwr : 1; + u32 orderedrd : 1; + u32 portmrel : 1; + u32 innerwritethrough : 1; + u32 innertransient : 1; + u32 innershared : 1; + u32 innercacheable : 1; + u32 innernoallocate : 1; + u32 writethrough : 1; + u32 shared : 1; + u32 full : 1; + u32 exclusive : 1; + u32 error : 1; + u32 earlywrresp : 1; + u32 device_type : 2; + u32 device : 1; + u32 cacheable : 1; + u32 burst : 1; + u32 bar : 2; +}; + +/* Union definition of register */ +union gsi_hwio_def_ipa_0_gsi_top_xpu3_qad1_esynr2_u +{ + struct gsi_hwio_def_ipa_0_gsi_top_xpu3_qad1_esynr2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_XPU3_QAD1_EAR1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ipa_0_gsi_top_xpu3_qad1_ear1_s +{ + u32 addr_63_32 : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ipa_0_gsi_top_xpu3_qad1_ear1_u +{ + struct gsi_hwio_def_ipa_0_gsi_top_xpu3_qad1_ear1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_XPU3_RGN_OWNERSTATUSr +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ipa_0_gsi_top_xpu3_rgn_ownerstatusr_s +{ + u32 rgownerstatus : 21; + u32 reserved0 : 11; +}; + +/* Union definition of register */ +union gsi_hwio_def_ipa_0_gsi_top_xpu3_rgn_ownerstatusr_u +{ + struct gsi_hwio_def_ipa_0_gsi_top_xpu3_rgn_ownerstatusr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_XPU3_RGn_GCR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ipa_0_gsi_top_xpu3_rgn_gcr0_s +{ + u32 rg_owner : 3; + u32 reserved0 : 5; + u32 rg_sec_apps : 1; + u32 reserved1 : 23; +}; + +/* Union definition of register */ +union gsi_hwio_def_ipa_0_gsi_top_xpu3_rgn_gcr0_u +{ + struct gsi_hwio_def_ipa_0_gsi_top_xpu3_rgn_gcr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_XPU3_RGn_GCR3 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ipa_0_gsi_top_xpu3_rgn_gcr3_s +{ + u32 secure_access_lock : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union gsi_hwio_def_ipa_0_gsi_top_xpu3_rgn_gcr3_u +{ + struct gsi_hwio_def_ipa_0_gsi_top_xpu3_rgn_gcr3_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_XPU3_RGn_CR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ipa_0_gsi_top_xpu3_rgn_cr0_s +{ + u32 rgsclrden_apps : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union gsi_hwio_def_ipa_0_gsi_top_xpu3_rgn_cr0_u +{ + struct gsi_hwio_def_ipa_0_gsi_top_xpu3_rgn_cr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_XPU3_RGn_CR1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ipa_0_gsi_top_xpu3_rgn_cr1_s +{ + u32 rgclrden : 3; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union gsi_hwio_def_ipa_0_gsi_top_xpu3_rgn_cr1_u +{ + struct gsi_hwio_def_ipa_0_gsi_top_xpu3_rgn_cr1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_XPU3_RGn_CR2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ipa_0_gsi_top_xpu3_rgn_cr2_s +{ + u32 rgsclwren_apps : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union gsi_hwio_def_ipa_0_gsi_top_xpu3_rgn_cr2_u +{ + struct gsi_hwio_def_ipa_0_gsi_top_xpu3_rgn_cr2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_XPU3_RGn_CR3 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ipa_0_gsi_top_xpu3_rgn_cr3_s +{ + u32 rgclwren : 3; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union gsi_hwio_def_ipa_0_gsi_top_xpu3_rgn_cr3_u +{ + struct gsi_hwio_def_ipa_0_gsi_top_xpu3_rgn_cr3_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_XPU3_RGn_RACR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ipa_0_gsi_top_xpu3_rgn_racr_s +{ + u32 re : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ipa_0_gsi_top_xpu3_rgn_racr_u +{ + struct gsi_hwio_def_ipa_0_gsi_top_xpu3_rgn_racr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_XPU3_RGn_WACR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ipa_0_gsi_top_xpu3_rgn_wacr_s +{ + u32 we : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ipa_0_gsi_top_xpu3_rgn_wacr_u +{ + struct gsi_hwio_def_ipa_0_gsi_top_xpu3_rgn_wacr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_MCS_PROFILING_BP_CNT_LSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_bp_cnt_lsb_s +{ + u32 bp_cnt_lsb : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_bp_cnt_lsb_u +{ + struct gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_bp_cnt_lsb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_MCS_PROFILING_BP_CNT_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_bp_cnt_msb_s +{ + u32 bp_cnt_msb : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_bp_cnt_msb_u +{ + struct gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_bp_cnt_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_bp_and_pending_cnt_lsb_s +{ + u32 bp_and_pending_cnt_lsb : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_bp_and_pending_cnt_lsb_u +{ + struct gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_bp_and_pending_cnt_lsb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_bp_and_pending_cnt_msb_s +{ + u32 bp_and_pending_cnt_msb : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_bp_and_pending_cnt_msb_u +{ + struct gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_bp_and_pending_cnt_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_mcs_busy_cnt_lsb_s +{ + u32 mcs_busy_cnt_lsb : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_mcs_busy_cnt_lsb_u +{ + struct gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_mcs_busy_cnt_lsb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_mcs_busy_cnt_msb_s +{ + u32 mcs_busy_cnt_msb : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_mcs_busy_cnt_msb_u +{ + struct gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_mcs_busy_cnt_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_mcs_idle_cnt_lsb_s +{ + u32 mcs_idle_cnt_lsb : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_mcs_idle_cnt_lsb_u +{ + struct gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_mcs_idle_cnt_lsb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_mcs_idle_cnt_msb_s +{ + u32 mcs_idle_cnt_msb : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_mcs_idle_cnt_msb_u +{ + struct gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_mcs_idle_cnt_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ipa_0_gsi_top_gsi_debug_sw_msk_reg_n_sec_k_rd_s +{ + u32 msk_reg : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ipa_0_gsi_top_gsi_debug_sw_msk_reg_n_sec_k_rd_u +{ + struct gsi_hwio_def_ipa_0_gsi_top_gsi_debug_sw_msk_reg_n_sec_k_rd_s def; + u32 value; +}; + +#endif /* __GSI_HWIO_DEF_H__ */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.0/ipa_access_control.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.0/ipa_access_control.h new file mode 100644 index 0000000000..a4d3dc41d4 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.0/ipa_access_control.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ +#if !defined(_IPA_ACCESS_CONTROL_H_) +#define _IPA_ACCESS_CONTROL_H_ + +#include "ipa_reg_dump.h" + +/* + * AA_COMBO - actual read, actual write + * AN_COMBO - actual read, no-op write + * NA_COMBO - no-op read, actual write + * NN_COMBO - no-op read, no-op write + */ + +/* + * The following is target specific. + */ +static struct reg_mem_access_map_t mem_access_map[] = { + /*------------------------------------------------------------*/ + /* Range Use when Use when */ + /* Begin End SD_ENABLED SD_DISABLED */ + /*------------------------------------------------------------*/ + { 0x04000, 0x04FFF, { &io_matrix[AN_COMBO], &io_matrix[AN_COMBO] } }, + { 0xA8000, 0xB7FFF, { &io_matrix[AN_COMBO], &io_matrix[AN_COMBO] } }, + { 0x05000, 0x0EFFF, { &io_matrix[AN_COMBO], &io_matrix[AN_COMBO] } }, + { 0x0F000, 0x0FFFF, { &io_matrix[AN_COMBO], &io_matrix[AN_COMBO] } }, + { 0x18000, 0x29FFF, { &io_matrix[AA_COMBO], &io_matrix[AA_COMBO] } }, + { 0x2A000, 0x3BFFF, { &io_matrix[AN_COMBO], &io_matrix[AN_COMBO] } }, + { 0x3C000, 0x4DFFF, { &io_matrix[AN_COMBO], &io_matrix[AN_COMBO] } }, + { 0x10000, 0x10FFF, { &io_matrix[AA_COMBO], &io_matrix[AA_COMBO] } }, + { 0x11000, 0x11FFF, { &io_matrix[NN_COMBO], &io_matrix[NN_COMBO] } }, + { 0x12000, 0x12FFF, { &io_matrix[NN_COMBO], &io_matrix[NN_COMBO] } }, + { 0x14C000, 0x14CFFF, { &io_matrix[AA_COMBO], &io_matrix[AA_COMBO] } }, + { 0x14D000, 0x14DFFF, { &io_matrix[NN_COMBO], &io_matrix[NN_COMBO] } }, + { 0x14E000, 0x14FFFF, { &io_matrix[NN_COMBO], &io_matrix[NN_COMBO] } }, + { 0x140000, 0x147FFF, { &io_matrix[AA_COMBO], &io_matrix[AA_COMBO] } }, + { 0x148000, 0x14BFFF, { &io_matrix[AN_COMBO], &io_matrix[AN_COMBO] } }, + { 0x150000, 0x15FFFF, { &io_matrix[AA_COMBO], &io_matrix[AA_COMBO] } }, + { 0x160000, 0x17FFFF, { &io_matrix[AN_COMBO], &io_matrix[NN_COMBO] } }, + { 0x180000, 0x180FFF, { &io_matrix[NN_COMBO], &io_matrix[NN_COMBO] } }, + { 0x181000, 0x19FFFF, { &io_matrix[AN_COMBO], &io_matrix[AN_COMBO] } }, + { 0x1A0000, 0x1BFFFF, { &io_matrix[AN_COMBO], &io_matrix[NN_COMBO] } }, + { 0x1C0000, 0x1C1FFF, { &io_matrix[NN_COMBO], &io_matrix[NN_COMBO] } }, + { 0x1C2000, 0x1C3FFF, { &io_matrix[AA_COMBO], &io_matrix[AA_COMBO] } }, +}; + +#endif /* #if !defined(_IPA_ACCESS_CONTROL_H_) */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.0/ipa_gcc_hwio.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.0/ipa_gcc_hwio.h new file mode 100644 index 0000000000..c71f4f7071 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.0/ipa_gcc_hwio.h @@ -0,0 +1,47043 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ + +#ifndef __IPA_GCC_HWIO_H__ +#define __IPA_GCC_HWIO_H__ +/** + @file ipa_gcc_hwio.h + @brief Auto-generated HWIO interface include file. + + This file contains HWIO register definitions for the following modules: + GCC_CLK_CTL_REG.* + + 'Include' filters applied: + 'Exclude' filters applied: RESERVED DUMMY + + Attribute definitions for the HWIO_*_ATTR macros are as follows: + 0x0: Command register + 0x1: Read-Only + 0x2: Write-Only + 0x3: Read/Write +*/ + +/*---------------------------------------------------------------------------- + * MODULE: GCC_CLK_CTL_REG + *--------------------------------------------------------------------------*/ + +#define GCC_CLK_CTL_REG_REG_BASE (CLK_CTL_BASE + 0x00010000) +#define GCC_CLK_CTL_REG_REG_BASE_PHYS (CLK_CTL_BASE_PHYS + 0x00010000) +#define GCC_CLK_CTL_REG_REG_BASE_OFFS 0x00010000 + +#define HWIO_GCC_SYSTEM_NOC_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000000) +#define HWIO_GCC_SYSTEM_NOC_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000000) +#define HWIO_GCC_SYSTEM_NOC_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000000) +#define HWIO_GCC_SYSTEM_NOC_BCR_RMSK 0x1 +#define HWIO_GCC_SYSTEM_NOC_BCR_ATTR 0x3 +#define HWIO_GCC_SYSTEM_NOC_BCR_IN \ + in_dword_masked(HWIO_GCC_SYSTEM_NOC_BCR_ADDR, HWIO_GCC_SYSTEM_NOC_BCR_RMSK) +#define HWIO_GCC_SYSTEM_NOC_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_SYSTEM_NOC_BCR_ADDR, m) +#define HWIO_GCC_SYSTEM_NOC_BCR_OUT(v) \ + out_dword(HWIO_GCC_SYSTEM_NOC_BCR_ADDR,v) +#define HWIO_GCC_SYSTEM_NOC_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SYSTEM_NOC_BCR_ADDR,m,v,HWIO_GCC_SYSTEM_NOC_BCR_IN) +#define HWIO_GCC_SYSTEM_NOC_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_SYSTEM_NOC_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_SYSTEM_NOC_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_SYSTEM_NOC_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SYS_NOC_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000004) +#define HWIO_GCC_SYS_NOC_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000004) +#define HWIO_GCC_SYS_NOC_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000004) +#define HWIO_GCC_SYS_NOC_AXI_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_SYS_NOC_AXI_CBCR_ATTR 0x3 +#define HWIO_GCC_SYS_NOC_AXI_CBCR_IN \ + in_dword_masked(HWIO_GCC_SYS_NOC_AXI_CBCR_ADDR, HWIO_GCC_SYS_NOC_AXI_CBCR_RMSK) +#define HWIO_GCC_SYS_NOC_AXI_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_SYS_NOC_AXI_CBCR_ADDR, m) +#define HWIO_GCC_SYS_NOC_AXI_CBCR_OUT(v) \ + out_dword(HWIO_GCC_SYS_NOC_AXI_CBCR_ADDR,v) +#define HWIO_GCC_SYS_NOC_AXI_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SYS_NOC_AXI_CBCR_ADDR,m,v,HWIO_GCC_SYS_NOC_AXI_CBCR_IN) +#define HWIO_GCC_SYS_NOC_AXI_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SYS_NOC_AXI_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SYS_NOC_AXI_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_SYS_NOC_AXI_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_SYS_NOC_AXI_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_SYS_NOC_AXI_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_SYS_NOC_AXI_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_SYS_NOC_AXI_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_SYS_NOC_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_SYS_NOC_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_SYS_NOC_AXI_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_SYS_NOC_AXI_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_SYS_NOC_AXI_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_SYS_NOC_AXI_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_SYS_NOC_AXI_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_AXI_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_AXI_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_SYS_NOC_AXI_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_SYS_NOC_AXI_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_AXI_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_AXI_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SYS_NOC_AXI_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SYS_NOC_AXI_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_AXI_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SYS_NOC_HS_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000008) +#define HWIO_GCC_SYS_NOC_HS_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000008) +#define HWIO_GCC_SYS_NOC_HS_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000008) +#define HWIO_GCC_SYS_NOC_HS_AXI_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_SYS_NOC_HS_AXI_CBCR_ATTR 0x3 +#define HWIO_GCC_SYS_NOC_HS_AXI_CBCR_IN \ + in_dword_masked(HWIO_GCC_SYS_NOC_HS_AXI_CBCR_ADDR, HWIO_GCC_SYS_NOC_HS_AXI_CBCR_RMSK) +#define HWIO_GCC_SYS_NOC_HS_AXI_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_SYS_NOC_HS_AXI_CBCR_ADDR, m) +#define HWIO_GCC_SYS_NOC_HS_AXI_CBCR_OUT(v) \ + out_dword(HWIO_GCC_SYS_NOC_HS_AXI_CBCR_ADDR,v) +#define HWIO_GCC_SYS_NOC_HS_AXI_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SYS_NOC_HS_AXI_CBCR_ADDR,m,v,HWIO_GCC_SYS_NOC_HS_AXI_CBCR_IN) +#define HWIO_GCC_SYS_NOC_HS_AXI_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SYS_NOC_HS_AXI_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SYS_NOC_HS_AXI_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_SYS_NOC_HS_AXI_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_SYS_NOC_HS_AXI_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_SYS_NOC_HS_AXI_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_SYS_NOC_HS_AXI_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_SYS_NOC_HS_AXI_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_SYS_NOC_HS_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_SYS_NOC_HS_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_SYS_NOC_HS_AXI_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_SYS_NOC_HS_AXI_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_SYS_NOC_HS_AXI_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_SYS_NOC_HS_AXI_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_SYS_NOC_HS_AXI_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_HS_AXI_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_HS_AXI_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_SYS_NOC_HS_AXI_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_SYS_NOC_HS_AXI_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_HS_AXI_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_HS_AXI_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SYS_NOC_HS_AXI_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SYS_NOC_HS_AXI_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_HS_AXI_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000000c) +#define HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000000c) +#define HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000000c) +#define HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_ATTR 0x3 +#define HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_IN \ + in_dword_masked(HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_ADDR, HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_RMSK) +#define HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_ADDR, m) +#define HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_OUT(v) \ + out_dword(HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_ADDR,v) +#define HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_ADDR,m,v,HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_IN) +#define HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000010) +#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000010) +#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000010) +#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_RMSK 0x81c0000e +#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_ADDR, HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_RMSK) +#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_ADDR, m) +#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_ADDR,v) +#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_ADDR,m,v,HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_IN) +#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000014) +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000014) +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000014) +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_ATTR 0x3 +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_IN \ + in_dword_masked(HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_ADDR, HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_RMSK) +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_ADDR, m) +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_OUT(v) \ + out_dword(HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_ADDR,v) +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_ADDR,m,v,HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_IN) +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SYS_NOC_IPA_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000018) +#define HWIO_GCC_SYS_NOC_IPA_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000018) +#define HWIO_GCC_SYS_NOC_IPA_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000018) +#define HWIO_GCC_SYS_NOC_IPA_CBCR_RMSK 0x81d00005 +#define HWIO_GCC_SYS_NOC_IPA_CBCR_ATTR 0x3 +#define HWIO_GCC_SYS_NOC_IPA_CBCR_IN \ + in_dword_masked(HWIO_GCC_SYS_NOC_IPA_CBCR_ADDR, HWIO_GCC_SYS_NOC_IPA_CBCR_RMSK) +#define HWIO_GCC_SYS_NOC_IPA_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_SYS_NOC_IPA_CBCR_ADDR, m) +#define HWIO_GCC_SYS_NOC_IPA_CBCR_OUT(v) \ + out_dword(HWIO_GCC_SYS_NOC_IPA_CBCR_ADDR,v) +#define HWIO_GCC_SYS_NOC_IPA_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SYS_NOC_IPA_CBCR_ADDR,m,v,HWIO_GCC_SYS_NOC_IPA_CBCR_IN) +#define HWIO_GCC_SYS_NOC_IPA_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SYS_NOC_IPA_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SYS_NOC_IPA_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_SYS_NOC_IPA_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_SYS_NOC_IPA_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_SYS_NOC_IPA_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_SYS_NOC_IPA_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_SYS_NOC_IPA_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_SYS_NOC_IPA_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_SYS_NOC_IPA_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_SYS_NOC_IPA_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_SYS_NOC_IPA_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_SYS_NOC_IPA_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_IPA_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_IPA_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SYS_NOC_IPA_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SYS_NOC_IPA_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_IPA_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SYS_NOC_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000001c) +#define HWIO_GCC_SYS_NOC_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000001c) +#define HWIO_GCC_SYS_NOC_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000001c) +#define HWIO_GCC_SYS_NOC_AT_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_SYS_NOC_AT_CBCR_ATTR 0x3 +#define HWIO_GCC_SYS_NOC_AT_CBCR_IN \ + in_dword_masked(HWIO_GCC_SYS_NOC_AT_CBCR_ADDR, HWIO_GCC_SYS_NOC_AT_CBCR_RMSK) +#define HWIO_GCC_SYS_NOC_AT_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_SYS_NOC_AT_CBCR_ADDR, m) +#define HWIO_GCC_SYS_NOC_AT_CBCR_OUT(v) \ + out_dword(HWIO_GCC_SYS_NOC_AT_CBCR_ADDR,v) +#define HWIO_GCC_SYS_NOC_AT_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SYS_NOC_AT_CBCR_ADDR,m,v,HWIO_GCC_SYS_NOC_AT_CBCR_IN) +#define HWIO_GCC_SYS_NOC_AT_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SYS_NOC_AT_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SYS_NOC_AT_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_SYS_NOC_AT_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_SYS_NOC_AT_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_SYS_NOC_AT_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_SYS_NOC_AT_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_SYS_NOC_AT_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_SYS_NOC_AT_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_SYS_NOC_AT_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_SYS_NOC_AT_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_SYS_NOC_AT_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_SYS_NOC_AT_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_SYS_NOC_AT_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_SYS_NOC_AT_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_AT_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_AT_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_SYS_NOC_AT_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_SYS_NOC_AT_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_AT_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_AT_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SYS_NOC_AT_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SYS_NOC_AT_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_AT_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000034) +#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000034) +#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000034) +#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_RMSK 0x7ffff +#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_RCG_SW_CTRL_BMSK 0x78000 +#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_RCG_SW_CTRL_SHFT 0xf +#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_SW_PERF_STATE_BMSK 0x7800 +#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_SW_PERF_STATE_SHFT 0xb +#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_SW_OVERRIDE_BMSK 0x400 +#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_SW_OVERRIDE_SHFT 0xa +#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK 0x200 +#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_DFS_FSM_STATE_BMSK 0x1c0 +#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_DFS_FSM_STATE_SHFT 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_HW_CLK_CONTROL_BMSK 0x20 +#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_HW_CLK_CONTROL_SHFT 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_CURR_PERF_STATE_BMSK 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_CURR_PERF_STATE_SHFT 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_DFS_EN_BMSK 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_DFS_EN_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_DFS_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_DFS_EN_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000003c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000003c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000003c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000040) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000040) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000040) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000044) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000044) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000044) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000048) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000048) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000048) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000004c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000004c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000004c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000050) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000050) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000050) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000054) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000054) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000054) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000058) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000058) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000058) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000005c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000005c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000005c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000060) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000060) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000060) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000064) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000064) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000064) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000068) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000068) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000068) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000006c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000006c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000006c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000070) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000070) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000070) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000074) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000074) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000074) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000078) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000078) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000078) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_SYS_NOC_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000020) +#define HWIO_GCC_SYS_NOC_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000020) +#define HWIO_GCC_SYS_NOC_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000020) +#define HWIO_GCC_SYS_NOC_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_SYS_NOC_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_SYS_NOC_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_SYS_NOC_CMD_RCGR_ADDR, HWIO_GCC_SYS_NOC_CMD_RCGR_RMSK) +#define HWIO_GCC_SYS_NOC_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_SYS_NOC_CMD_RCGR_ADDR, m) +#define HWIO_GCC_SYS_NOC_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_SYS_NOC_CMD_RCGR_ADDR,v) +#define HWIO_GCC_SYS_NOC_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SYS_NOC_CMD_RCGR_ADDR,m,v,HWIO_GCC_SYS_NOC_CMD_RCGR_IN) +#define HWIO_GCC_SYS_NOC_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_SYS_NOC_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_SYS_NOC_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_SYS_NOC_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_SYS_NOC_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_SYS_NOC_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_SYS_NOC_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_SYS_NOC_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_SYS_NOC_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SYS_NOC_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000024) +#define HWIO_GCC_SYS_NOC_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000024) +#define HWIO_GCC_SYS_NOC_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000024) +#define HWIO_GCC_SYS_NOC_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_SYS_NOC_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_SYS_NOC_CFG_RCGR_ADDR, HWIO_GCC_SYS_NOC_CFG_RCGR_RMSK) +#define HWIO_GCC_SYS_NOC_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_SYS_NOC_CFG_RCGR_ADDR, m) +#define HWIO_GCC_SYS_NOC_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_SYS_NOC_CFG_RCGR_ADDR,v) +#define HWIO_GCC_SYS_NOC_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SYS_NOC_CFG_RCGR_ADDR,m,v,HWIO_GCC_SYS_NOC_CFG_RCGR_IN) +#define HWIO_GCC_SYS_NOC_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_SYS_NOC_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000014c) +#define HWIO_GCC_SYS_NOC_DCD_CDIV_DCDR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000014c) +#define HWIO_GCC_SYS_NOC_DCD_CDIV_DCDR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000014c) +#define HWIO_GCC_SYS_NOC_DCD_CDIV_DCDR_RMSK 0x1 +#define HWIO_GCC_SYS_NOC_DCD_CDIV_DCDR_ATTR 0x3 +#define HWIO_GCC_SYS_NOC_DCD_CDIV_DCDR_IN \ + in_dword_masked(HWIO_GCC_SYS_NOC_DCD_CDIV_DCDR_ADDR, HWIO_GCC_SYS_NOC_DCD_CDIV_DCDR_RMSK) +#define HWIO_GCC_SYS_NOC_DCD_CDIV_DCDR_INM(m) \ + in_dword_masked(HWIO_GCC_SYS_NOC_DCD_CDIV_DCDR_ADDR, m) +#define HWIO_GCC_SYS_NOC_DCD_CDIV_DCDR_OUT(v) \ + out_dword(HWIO_GCC_SYS_NOC_DCD_CDIV_DCDR_ADDR,v) +#define HWIO_GCC_SYS_NOC_DCD_CDIV_DCDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SYS_NOC_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_SYS_NOC_DCD_CDIV_DCDR_IN) +#define HWIO_GCC_SYS_NOC_DCD_CDIV_DCDR_DCD_ENABLE_BMSK 0x1 +#define HWIO_GCC_SYS_NOC_DCD_CDIV_DCDR_DCD_ENABLE_SHFT 0x0 +#define HWIO_GCC_SYS_NOC_DCD_CDIV_DCDR_DCD_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_DCD_CDIV_DCDR_DCD_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000016c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000016c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000016c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF0_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF0_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF0_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF0_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000170) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000170) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000170) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF1_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF1_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF1_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF1_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000174) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000174) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000174) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF2_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF2_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF2_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF2_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000178) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000178) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000178) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF3_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF3_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF3_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF3_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000017c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000017c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000017c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF4_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF4_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF4_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF4_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000180) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000180) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000180) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF5_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF5_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF5_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF5_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000184) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000184) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000184) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF6_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF6_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF6_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF6_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000188) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000188) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000188) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF7_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF7_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF7_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF7_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF8_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000018c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF8_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000018c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF8_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000018c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF8_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF8_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF8_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF8_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF8_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF8_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF8_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF8_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF8_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF8_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF8_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF8_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF8_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF8_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF8_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF8_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF8_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF8_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF8_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF8_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF8_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF8_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF8_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF8_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF8_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF8_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF8_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF8_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF8_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF8_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF8_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF8_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF8_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF8_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF8_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF8_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF8_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF8_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF8_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF8_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF8_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF8_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF8_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF8_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF8_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF8_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF8_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF8_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF8_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF8_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF8_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF8_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF8_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF8_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF8_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF9_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000190) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF9_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000190) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF9_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000190) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF9_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF9_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF9_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF9_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF9_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF9_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF9_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF9_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF9_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF9_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF9_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF9_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF9_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF9_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF9_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF9_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF9_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF9_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF9_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF9_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF9_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF9_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF9_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF9_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF9_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF9_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF9_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF9_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF9_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF9_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF9_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF9_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF9_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF9_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF9_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF9_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF9_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF9_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF9_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF9_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF9_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF9_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF9_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF9_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF9_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF9_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF9_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF9_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF9_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF9_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF9_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF9_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF9_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF9_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF9_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF10_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000194) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF10_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000194) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF10_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000194) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF10_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF10_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF10_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF10_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF10_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF10_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF10_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF10_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF10_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF10_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF10_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF10_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF10_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF10_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF10_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF10_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF10_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF10_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF10_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF10_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF10_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF10_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF10_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF10_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF10_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF10_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF10_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF10_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF10_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF10_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF10_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF10_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF10_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF10_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF10_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF10_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF10_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF10_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF10_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF10_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF10_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF10_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF10_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF10_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF10_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF10_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF10_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF10_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF10_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF10_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF10_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF10_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF10_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF10_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF10_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF11_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000198) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF11_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000198) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF11_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000198) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF11_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF11_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF11_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF11_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF11_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF11_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF11_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF11_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF11_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF11_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF11_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF11_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF11_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF11_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF11_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF11_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF11_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF11_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF11_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF11_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF11_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF11_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF11_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF11_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF11_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF11_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF11_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF11_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF11_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF11_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF11_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF11_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF11_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF11_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF11_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF11_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF11_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF11_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF11_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF11_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF11_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF11_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF11_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF11_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF11_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF11_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF11_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF11_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF11_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF11_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF11_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF11_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF11_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF11_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF11_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF12_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000019c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF12_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000019c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF12_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000019c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF12_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF12_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF12_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF12_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF12_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF12_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF12_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF12_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF12_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF12_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF12_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF12_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF12_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF12_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF12_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF12_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF12_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF12_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF12_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF12_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF12_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF12_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF12_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF12_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF12_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF12_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF12_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF12_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF12_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF12_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF12_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF12_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF12_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF12_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF12_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF12_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF12_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF12_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF12_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF12_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF12_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF12_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF12_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF12_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF12_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF12_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF12_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF12_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF12_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF12_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF12_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF12_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF12_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF12_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF12_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF13_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000001a0) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF13_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000001a0) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF13_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000001a0) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF13_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF13_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF13_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF13_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF13_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF13_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF13_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF13_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF13_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF13_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF13_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF13_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF13_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF13_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF13_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF13_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF13_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF13_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF13_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF13_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF13_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF13_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF13_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF13_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF13_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF13_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF13_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF13_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF13_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF13_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF13_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF13_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF13_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF13_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF13_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF13_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF13_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF13_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF13_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF13_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF13_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF13_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF13_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF13_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF13_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF13_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF13_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF13_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF13_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF13_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF13_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF13_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF13_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF13_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF13_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF14_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000001a4) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF14_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000001a4) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF14_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000001a4) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF14_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF14_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF14_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF14_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF14_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF14_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF14_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF14_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF14_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF14_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF14_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF14_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF14_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF14_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF14_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF14_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF14_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF14_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF14_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF14_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF14_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF14_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF14_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF14_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF14_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF14_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF14_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF14_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF14_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF14_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF14_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF14_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF14_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF14_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF14_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF14_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF14_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF14_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF14_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF14_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF14_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF14_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF14_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF14_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF14_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF14_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF14_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF14_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF14_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF14_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF14_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF14_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF14_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF14_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF14_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF15_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000001a8) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF15_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000001a8) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF15_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000001a8) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF15_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF15_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF15_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF15_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF15_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF15_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF15_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF15_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF15_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF15_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF15_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF15_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF15_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF15_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF15_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF15_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF15_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF15_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF15_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF15_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF15_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF15_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF15_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF15_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF15_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF15_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF15_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF15_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF15_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF15_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF15_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF15_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF15_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF15_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF15_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF15_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF15_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF15_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF15_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF15_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF15_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF15_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF15_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF15_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF15_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF15_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF15_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF15_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF15_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF15_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF15_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF15_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF15_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF15_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF15_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_SYS_NOC_HS_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000150) +#define HWIO_GCC_SYS_NOC_HS_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000150) +#define HWIO_GCC_SYS_NOC_HS_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000150) +#define HWIO_GCC_SYS_NOC_HS_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_SYS_NOC_HS_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_SYS_NOC_HS_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_SYS_NOC_HS_CMD_RCGR_ADDR, HWIO_GCC_SYS_NOC_HS_CMD_RCGR_RMSK) +#define HWIO_GCC_SYS_NOC_HS_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_SYS_NOC_HS_CMD_RCGR_ADDR, m) +#define HWIO_GCC_SYS_NOC_HS_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_SYS_NOC_HS_CMD_RCGR_ADDR,v) +#define HWIO_GCC_SYS_NOC_HS_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SYS_NOC_HS_CMD_RCGR_ADDR,m,v,HWIO_GCC_SYS_NOC_HS_CMD_RCGR_IN) +#define HWIO_GCC_SYS_NOC_HS_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_SYS_NOC_HS_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_SYS_NOC_HS_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_SYS_NOC_HS_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_SYS_NOC_HS_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_SYS_NOC_HS_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_SYS_NOC_HS_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_HS_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_HS_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_SYS_NOC_HS_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_SYS_NOC_HS_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_HS_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SYS_NOC_HS_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000154) +#define HWIO_GCC_SYS_NOC_HS_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000154) +#define HWIO_GCC_SYS_NOC_HS_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000154) +#define HWIO_GCC_SYS_NOC_HS_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_SYS_NOC_HS_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_SYS_NOC_HS_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_SYS_NOC_HS_CFG_RCGR_ADDR, HWIO_GCC_SYS_NOC_HS_CFG_RCGR_RMSK) +#define HWIO_GCC_SYS_NOC_HS_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_SYS_NOC_HS_CFG_RCGR_ADDR, m) +#define HWIO_GCC_SYS_NOC_HS_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_SYS_NOC_HS_CFG_RCGR_ADDR,v) +#define HWIO_GCC_SYS_NOC_HS_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SYS_NOC_HS_CFG_RCGR_ADDR,m,v,HWIO_GCC_SYS_NOC_HS_CFG_RCGR_IN) +#define HWIO_GCC_SYS_NOC_HS_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_SYS_NOC_HS_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_SYS_NOC_HS_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_HS_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_HS_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_SYS_NOC_HS_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_SYS_NOC_HS_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_HS_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_HS_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_SYS_NOC_HS_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_SYS_NOC_HS_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_HS_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_HS_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_SYS_NOC_HS_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_SYS_NOC_HS_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_SYS_NOC_HS_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_SYS_NOC_HS_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_SYS_NOC_HS_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_SYS_NOC_HS_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_SYS_NOC_HS_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_SYS_NOC_HS_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_HS_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_HS_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_SYS_NOC_HS_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_SYS_NOC_HS_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_SYS_NOC_HS_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_SYS_NOC_HS_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_SYS_NOC_HS_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_SYS_NOC_HS_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_SYS_NOC_HS_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_SYS_NOC_HS_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_SYS_NOC_HS_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_SYS_NOC_HS_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_SYS_NOC_HS_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_SYS_NOC_HS_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_SYS_NOC_HS_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_SYS_NOC_HS_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_SYS_NOC_HS_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_SYS_NOC_HS_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_SYS_NOC_HS_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_SYS_NOC_HS_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_SYS_NOC_HS_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_SYS_NOC_HS_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_SYS_NOC_HS_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_SYS_NOC_HS_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_SYS_NOC_HS_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_SYS_NOC_HS_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_SYS_NOC_HS_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_SYS_NOC_HS_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_SYS_NOC_HS_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_SYS_NOC_HS_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_SYS_NOC_HS_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_SYS_NOC_HS_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000027c) +#define HWIO_GCC_SYS_NOC_HS_DCD_CDIV_DCDR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000027c) +#define HWIO_GCC_SYS_NOC_HS_DCD_CDIV_DCDR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000027c) +#define HWIO_GCC_SYS_NOC_HS_DCD_CDIV_DCDR_RMSK 0x1 +#define HWIO_GCC_SYS_NOC_HS_DCD_CDIV_DCDR_ATTR 0x3 +#define HWIO_GCC_SYS_NOC_HS_DCD_CDIV_DCDR_IN \ + in_dword_masked(HWIO_GCC_SYS_NOC_HS_DCD_CDIV_DCDR_ADDR, HWIO_GCC_SYS_NOC_HS_DCD_CDIV_DCDR_RMSK) +#define HWIO_GCC_SYS_NOC_HS_DCD_CDIV_DCDR_INM(m) \ + in_dword_masked(HWIO_GCC_SYS_NOC_HS_DCD_CDIV_DCDR_ADDR, m) +#define HWIO_GCC_SYS_NOC_HS_DCD_CDIV_DCDR_OUT(v) \ + out_dword(HWIO_GCC_SYS_NOC_HS_DCD_CDIV_DCDR_ADDR,v) +#define HWIO_GCC_SYS_NOC_HS_DCD_CDIV_DCDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SYS_NOC_HS_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_SYS_NOC_HS_DCD_CDIV_DCDR_IN) +#define HWIO_GCC_SYS_NOC_HS_DCD_CDIV_DCDR_DCD_ENABLE_BMSK 0x1 +#define HWIO_GCC_SYS_NOC_HS_DCD_CDIV_DCDR_DCD_ENABLE_SHFT 0x0 +#define HWIO_GCC_SYS_NOC_HS_DCD_CDIV_DCDR_DCD_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_HS_DCD_CDIV_DCDR_DCD_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SNOC_QOSGEN_EXTREF_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000280) +#define HWIO_GCC_SNOC_QOSGEN_EXTREF_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000280) +#define HWIO_GCC_SNOC_QOSGEN_EXTREF_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000280) +#define HWIO_GCC_SNOC_QOSGEN_EXTREF_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_SNOC_QOSGEN_EXTREF_CBCR_ATTR 0x3 +#define HWIO_GCC_SNOC_QOSGEN_EXTREF_CBCR_IN \ + in_dword_masked(HWIO_GCC_SNOC_QOSGEN_EXTREF_CBCR_ADDR, HWIO_GCC_SNOC_QOSGEN_EXTREF_CBCR_RMSK) +#define HWIO_GCC_SNOC_QOSGEN_EXTREF_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_SNOC_QOSGEN_EXTREF_CBCR_ADDR, m) +#define HWIO_GCC_SNOC_QOSGEN_EXTREF_CBCR_OUT(v) \ + out_dword(HWIO_GCC_SNOC_QOSGEN_EXTREF_CBCR_ADDR,v) +#define HWIO_GCC_SNOC_QOSGEN_EXTREF_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SNOC_QOSGEN_EXTREF_CBCR_ADDR,m,v,HWIO_GCC_SNOC_QOSGEN_EXTREF_CBCR_IN) +#define HWIO_GCC_SNOC_QOSGEN_EXTREF_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SNOC_QOSGEN_EXTREF_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SNOC_QOSGEN_EXTREF_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_SNOC_QOSGEN_EXTREF_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_SNOC_QOSGEN_EXTREF_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_SNOC_QOSGEN_EXTREF_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_SNOC_QOSGEN_EXTREF_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_SNOC_QOSGEN_EXTREF_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_SNOC_QOSGEN_EXTREF_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_SNOC_QOSGEN_EXTREF_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_SNOC_QOSGEN_EXTREF_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SNOC_QOSGEN_EXTREF_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_SNOC_QOSGEN_EXTREF_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SNOC_QOSGEN_EXTREF_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SNOC_QOSGEN_EXTREF_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SNOC_QOSGEN_EXTREF_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCNOC_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00001000) +#define HWIO_GCC_PCNOC_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00001000) +#define HWIO_GCC_PCNOC_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00001000) +#define HWIO_GCC_PCNOC_BCR_RMSK 0x1 +#define HWIO_GCC_PCNOC_BCR_ATTR 0x3 +#define HWIO_GCC_PCNOC_BCR_IN \ + in_dword_masked(HWIO_GCC_PCNOC_BCR_ADDR, HWIO_GCC_PCNOC_BCR_RMSK) +#define HWIO_GCC_PCNOC_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCNOC_BCR_ADDR, m) +#define HWIO_GCC_PCNOC_BCR_OUT(v) \ + out_dword(HWIO_GCC_PCNOC_BCR_ADDR,v) +#define HWIO_GCC_PCNOC_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCNOC_BCR_ADDR,m,v,HWIO_GCC_PCNOC_BCR_IN) +#define HWIO_GCC_PCNOC_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_PCNOC_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_PCNOC_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCNOC_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CFG_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00001004) +#define HWIO_GCC_CFG_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00001004) +#define HWIO_GCC_CFG_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00001004) +#define HWIO_GCC_CFG_AHB_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_CFG_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_CFG_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_CFG_AHB_CBCR_ADDR, HWIO_GCC_CFG_AHB_CBCR_RMSK) +#define HWIO_GCC_CFG_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_CFG_AHB_CBCR_ADDR, m) +#define HWIO_GCC_CFG_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_CFG_AHB_CBCR_ADDR,v) +#define HWIO_GCC_CFG_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CFG_AHB_CBCR_ADDR,m,v,HWIO_GCC_CFG_AHB_CBCR_IN) +#define HWIO_GCC_CFG_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_CFG_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_CFG_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_CFG_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_CFG_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_CFG_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_CFG_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_CFG_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_CFG_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_CFG_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_CFG_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_CFG_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_CFG_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_CFG_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_CFG_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_CFG_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_CFG_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_CFG_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_CFG_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_CFG_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_CFG_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CFG_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_NOC_DCD_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00001008) +#define HWIO_GCC_NOC_DCD_XO_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00001008) +#define HWIO_GCC_NOC_DCD_XO_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00001008) +#define HWIO_GCC_NOC_DCD_XO_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_NOC_DCD_XO_CBCR_ATTR 0x3 +#define HWIO_GCC_NOC_DCD_XO_CBCR_IN \ + in_dword_masked(HWIO_GCC_NOC_DCD_XO_CBCR_ADDR, HWIO_GCC_NOC_DCD_XO_CBCR_RMSK) +#define HWIO_GCC_NOC_DCD_XO_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_NOC_DCD_XO_CBCR_ADDR, m) +#define HWIO_GCC_NOC_DCD_XO_CBCR_OUT(v) \ + out_dword(HWIO_GCC_NOC_DCD_XO_CBCR_ADDR,v) +#define HWIO_GCC_NOC_DCD_XO_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_NOC_DCD_XO_CBCR_ADDR,m,v,HWIO_GCC_NOC_DCD_XO_CBCR_IN) +#define HWIO_GCC_NOC_DCD_XO_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_NOC_DCD_XO_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_NOC_DCD_XO_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_NOC_DCD_XO_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_NOC_DCD_XO_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_NOC_DCD_XO_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_NOC_DCD_XO_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_NOC_DCD_XO_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_NOC_DCD_XO_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_NOC_DCD_XO_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_NOC_DCD_XO_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_NOC_DCD_XO_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_NOC_DCD_XO_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_NOC_DCD_XO_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_NOC_DCD_XO_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_NOC_DCD_XO_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCNOC_SPMI_VGIS_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000100c) +#define HWIO_GCC_PCNOC_SPMI_VGIS_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000100c) +#define HWIO_GCC_PCNOC_SPMI_VGIS_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000100c) +#define HWIO_GCC_PCNOC_SPMI_VGIS_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_PCNOC_SPMI_VGIS_CBCR_ATTR 0x3 +#define HWIO_GCC_PCNOC_SPMI_VGIS_CBCR_IN \ + in_dword_masked(HWIO_GCC_PCNOC_SPMI_VGIS_CBCR_ADDR, HWIO_GCC_PCNOC_SPMI_VGIS_CBCR_RMSK) +#define HWIO_GCC_PCNOC_SPMI_VGIS_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCNOC_SPMI_VGIS_CBCR_ADDR, m) +#define HWIO_GCC_PCNOC_SPMI_VGIS_CBCR_OUT(v) \ + out_dword(HWIO_GCC_PCNOC_SPMI_VGIS_CBCR_ADDR,v) +#define HWIO_GCC_PCNOC_SPMI_VGIS_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCNOC_SPMI_VGIS_CBCR_ADDR,m,v,HWIO_GCC_PCNOC_SPMI_VGIS_CBCR_IN) +#define HWIO_GCC_PCNOC_SPMI_VGIS_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_PCNOC_SPMI_VGIS_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_PCNOC_SPMI_VGIS_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_PCNOC_SPMI_VGIS_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_PCNOC_SPMI_VGIS_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_PCNOC_SPMI_VGIS_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_PCNOC_SPMI_VGIS_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_PCNOC_SPMI_VGIS_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_PCNOC_SPMI_VGIS_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_PCNOC_SPMI_VGIS_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_PCNOC_SPMI_VGIS_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_PCNOC_SPMI_VGIS_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_PCNOC_SPMI_VGIS_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_PCNOC_SPMI_VGIS_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_PCNOC_SPMI_VGIS_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCNOC_SPMI_VGIS_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00001024) +#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00001024) +#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00001024) +#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_RMSK 0xffff +#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CMD_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CMD_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CMD_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CMD_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CMD_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CMD_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_RCG_SW_CTRL_BMSK 0x8000 +#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_RCG_SW_CTRL_SHFT 0xf +#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_SW_PERF_STATE_BMSK 0x7800 +#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_SW_PERF_STATE_SHFT 0xb +#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_SW_OVERRIDE_BMSK 0x400 +#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_SW_OVERRIDE_SHFT 0xa +#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK 0x200 +#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT 0x9 +#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_DFS_FSM_STATE_BMSK 0x1c0 +#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_DFS_FSM_STATE_SHFT 0x6 +#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_HW_CLK_CONTROL_BMSK 0x20 +#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_HW_CLK_CONTROL_SHFT 0x5 +#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_CURR_PERF_STATE_BMSK 0x1e +#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_CURR_PERF_STATE_SHFT 0x1 +#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_DFS_EN_BMSK 0x1 +#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_DFS_EN_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_DFS_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_DFS_EN_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000102c) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000102c) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000102c) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF0_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PCNOC_PERF0_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_PCNOC_PERF0_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PCNOC_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_PCNOC_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PCNOC_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PCNOC_PERF0_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00001030) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00001030) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00001030) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF1_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PCNOC_PERF1_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_PCNOC_PERF1_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PCNOC_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_PCNOC_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PCNOC_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PCNOC_PERF1_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00001034) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00001034) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00001034) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF2_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PCNOC_PERF2_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_PCNOC_PERF2_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PCNOC_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_PCNOC_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PCNOC_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PCNOC_PERF2_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00001038) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00001038) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00001038) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF3_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PCNOC_PERF3_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_PCNOC_PERF3_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PCNOC_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_PCNOC_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PCNOC_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PCNOC_PERF3_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000103c) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000103c) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000103c) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF4_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PCNOC_PERF4_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_PCNOC_PERF4_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PCNOC_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_PCNOC_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PCNOC_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PCNOC_PERF4_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00001040) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00001040) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00001040) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF5_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PCNOC_PERF5_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_PCNOC_PERF5_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PCNOC_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_PCNOC_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PCNOC_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PCNOC_PERF5_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00001044) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00001044) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00001044) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF6_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PCNOC_PERF6_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_PCNOC_PERF6_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PCNOC_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_PCNOC_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PCNOC_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PCNOC_PERF6_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00001048) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00001048) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00001048) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF7_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PCNOC_PERF7_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_PCNOC_PERF7_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PCNOC_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_PCNOC_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PCNOC_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PCNOC_PERF7_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF8_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000104c) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF8_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000104c) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF8_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000104c) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF8_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF8_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF8_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PCNOC_PERF8_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_PCNOC_PERF8_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF8_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PCNOC_PERF8_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF8_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_PCNOC_PERF8_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF8_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PCNOC_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PCNOC_PERF8_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF8_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF8_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF8_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF8_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF8_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF8_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF8_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF8_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF8_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF8_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF8_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF8_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF8_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF8_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF8_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF8_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF8_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF8_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF8_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF8_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF8_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF8_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF8_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF8_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF8_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF8_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF8_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF8_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF8_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF8_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF8_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF8_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF8_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF8_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF8_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF8_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF8_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF8_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF8_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF8_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF8_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF8_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF8_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF8_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF9_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00001050) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF9_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00001050) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF9_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00001050) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF9_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF9_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF9_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PCNOC_PERF9_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_PCNOC_PERF9_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF9_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PCNOC_PERF9_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF9_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_PCNOC_PERF9_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF9_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PCNOC_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PCNOC_PERF9_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF9_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF9_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF9_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF9_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF9_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF9_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF9_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF9_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF9_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF9_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF9_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF9_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF9_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF9_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF9_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF9_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF9_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF9_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF9_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF9_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF9_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF9_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF9_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF9_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF9_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF9_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF9_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF9_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF9_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF9_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF9_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF9_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF9_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF9_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF9_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF9_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF9_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF9_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF9_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF9_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF9_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF9_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF9_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF9_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF10_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00001054) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF10_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00001054) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF10_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00001054) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF10_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF10_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF10_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PCNOC_PERF10_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_PCNOC_PERF10_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF10_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PCNOC_PERF10_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF10_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_PCNOC_PERF10_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF10_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PCNOC_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PCNOC_PERF10_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF10_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF10_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF10_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF10_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF10_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF10_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF10_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF10_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF10_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF10_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF10_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF10_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF10_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF10_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF10_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF10_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF10_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF10_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF10_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF10_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF10_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF10_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF10_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF10_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF10_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF10_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF10_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF10_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF10_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF10_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF10_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF10_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF10_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF10_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF10_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF10_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF10_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF10_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF10_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF10_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF10_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF10_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF10_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF10_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF11_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00001058) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF11_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00001058) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF11_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00001058) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF11_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF11_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF11_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PCNOC_PERF11_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_PCNOC_PERF11_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF11_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PCNOC_PERF11_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF11_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_PCNOC_PERF11_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF11_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PCNOC_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PCNOC_PERF11_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF11_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF11_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF11_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF11_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF11_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF11_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF11_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF11_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF11_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF11_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF11_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF11_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF11_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF11_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF11_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF11_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF11_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF11_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF11_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF11_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF11_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF11_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF11_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF11_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF11_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF11_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF11_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF11_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF11_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF11_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF11_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF11_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF11_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF11_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF11_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF11_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF11_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF11_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF11_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF11_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF11_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF11_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF11_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF11_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF12_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000105c) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF12_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000105c) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF12_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000105c) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF12_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF12_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF12_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PCNOC_PERF12_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_PCNOC_PERF12_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF12_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PCNOC_PERF12_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF12_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_PCNOC_PERF12_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF12_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PCNOC_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PCNOC_PERF12_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF12_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF12_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF12_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF12_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF12_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF12_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF12_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF12_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF12_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF12_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF12_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF12_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF12_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF12_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF12_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF12_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF12_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF12_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF12_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF12_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF12_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF12_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF12_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF12_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF12_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF12_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF12_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF12_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF12_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF12_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF12_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF12_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF12_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF12_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF12_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF12_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF12_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF12_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF12_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF12_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF12_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF12_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF12_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF12_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF13_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00001060) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF13_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00001060) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF13_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00001060) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF13_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF13_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF13_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PCNOC_PERF13_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_PCNOC_PERF13_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF13_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PCNOC_PERF13_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF13_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_PCNOC_PERF13_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF13_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PCNOC_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PCNOC_PERF13_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF13_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF13_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF13_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF13_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF13_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF13_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF13_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF13_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF13_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF13_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF13_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF13_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF13_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF13_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF13_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF13_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF13_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF13_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF13_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF13_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF13_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF13_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF13_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF13_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF13_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF13_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF13_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF13_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF13_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF13_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF13_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF13_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF13_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF13_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF13_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF13_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF13_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF13_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF13_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF13_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF13_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF13_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF13_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF13_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF14_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00001064) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF14_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00001064) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF14_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00001064) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF14_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF14_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF14_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PCNOC_PERF14_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_PCNOC_PERF14_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF14_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PCNOC_PERF14_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF14_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_PCNOC_PERF14_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF14_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PCNOC_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PCNOC_PERF14_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF14_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF14_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF14_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF14_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF14_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF14_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF14_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF14_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF14_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF14_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF14_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF14_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF14_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF14_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF14_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF14_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF14_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF14_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF14_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF14_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF14_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF14_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF14_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF14_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF14_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF14_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF14_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF14_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF14_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF14_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF14_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF14_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF14_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF14_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF14_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF14_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF14_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF14_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF14_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF14_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF14_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF14_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF14_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF14_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF15_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00001068) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF15_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00001068) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF15_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00001068) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF15_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF15_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF15_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PCNOC_PERF15_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_PCNOC_PERF15_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF15_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PCNOC_PERF15_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF15_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_PCNOC_PERF15_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF15_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PCNOC_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PCNOC_PERF15_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF15_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF15_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF15_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF15_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF15_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF15_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF15_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF15_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF15_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF15_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF15_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF15_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF15_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF15_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF15_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF15_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF15_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF15_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF15_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF15_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF15_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF15_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF15_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF15_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF15_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF15_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF15_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF15_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF15_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF15_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF15_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF15_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF15_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF15_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF15_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF15_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF15_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF15_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF15_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF15_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF15_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF15_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF15_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_PCNOC_PERF15_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_PCNOC_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00001010) +#define HWIO_GCC_PCNOC_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00001010) +#define HWIO_GCC_PCNOC_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00001010) +#define HWIO_GCC_PCNOC_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_PCNOC_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_PCNOC_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_PCNOC_CMD_RCGR_ADDR, HWIO_GCC_PCNOC_CMD_RCGR_RMSK) +#define HWIO_GCC_PCNOC_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_PCNOC_CMD_RCGR_ADDR, m) +#define HWIO_GCC_PCNOC_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_PCNOC_CMD_RCGR_ADDR,v) +#define HWIO_GCC_PCNOC_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCNOC_CMD_RCGR_ADDR,m,v,HWIO_GCC_PCNOC_CMD_RCGR_IN) +#define HWIO_GCC_PCNOC_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_PCNOC_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_PCNOC_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_PCNOC_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_PCNOC_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_PCNOC_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_PCNOC_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCNOC_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCNOC_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_PCNOC_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_PCNOC_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCNOC_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCNOC_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00001014) +#define HWIO_GCC_PCNOC_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00001014) +#define HWIO_GCC_PCNOC_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00001014) +#define HWIO_GCC_PCNOC_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_PCNOC_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_PCNOC_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_PCNOC_CFG_RCGR_ADDR, HWIO_GCC_PCNOC_CFG_RCGR_RMSK) +#define HWIO_GCC_PCNOC_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_PCNOC_CFG_RCGR_ADDR, m) +#define HWIO_GCC_PCNOC_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_PCNOC_CFG_RCGR_ADDR,v) +#define HWIO_GCC_PCNOC_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCNOC_CFG_RCGR_ADDR,m,v,HWIO_GCC_PCNOC_CFG_RCGR_IN) +#define HWIO_GCC_PCNOC_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_PCNOC_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_PCNOC_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCNOC_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCNOC_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_PCNOC_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_PCNOC_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_PCNOC_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_PCNOC_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_PCNOC_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_PCNOC_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_PCNOC_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_PCNOC_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_PCNOC_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_PCNOC_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_PCNOC_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_PCNOC_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_PCNOC_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_PCNOC_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_PCNOC_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_PCNOC_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_PCNOC_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_PCNOC_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_PCNOC_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_PCNOC_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_PCNOC_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_PCNOC_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_PCNOC_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_PCNOC_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_PCNOC_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_PCNOC_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_PCNOC_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_PCNOC_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_PCNOC_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_PCNOC_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_PCNOC_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_PCNOC_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_PCNOC_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_PCNOC_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_PCNOC_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_PCNOC_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_PCNOC_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_PCNOC_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_PCNOC_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_PCNOC_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_PCNOC_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_PCNOC_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_PCNOC_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_PCNOC_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_PCNOC_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_PCNOC_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_PCNOC_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_PCNOC_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000113c) +#define HWIO_GCC_PCNOC_DCD_CDIV_DCDR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000113c) +#define HWIO_GCC_PCNOC_DCD_CDIV_DCDR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000113c) +#define HWIO_GCC_PCNOC_DCD_CDIV_DCDR_RMSK 0x1 +#define HWIO_GCC_PCNOC_DCD_CDIV_DCDR_ATTR 0x3 +#define HWIO_GCC_PCNOC_DCD_CDIV_DCDR_IN \ + in_dword_masked(HWIO_GCC_PCNOC_DCD_CDIV_DCDR_ADDR, HWIO_GCC_PCNOC_DCD_CDIV_DCDR_RMSK) +#define HWIO_GCC_PCNOC_DCD_CDIV_DCDR_INM(m) \ + in_dword_masked(HWIO_GCC_PCNOC_DCD_CDIV_DCDR_ADDR, m) +#define HWIO_GCC_PCNOC_DCD_CDIV_DCDR_OUT(v) \ + out_dword(HWIO_GCC_PCNOC_DCD_CDIV_DCDR_ADDR,v) +#define HWIO_GCC_PCNOC_DCD_CDIV_DCDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCNOC_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_PCNOC_DCD_CDIV_DCDR_IN) +#define HWIO_GCC_PCNOC_DCD_CDIV_DCDR_DCD_ENABLE_BMSK 0x1 +#define HWIO_GCC_PCNOC_DCD_CDIV_DCDR_DCD_ENABLE_SHFT 0x0 +#define HWIO_GCC_PCNOC_DCD_CDIV_DCDR_DCD_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCNOC_DCD_CDIV_DCDR_DCD_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TIC_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00002000) +#define HWIO_GCC_TIC_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00002000) +#define HWIO_GCC_TIC_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00002000) +#define HWIO_GCC_TIC_CBCR_RMSK 0x81c0000f +#define HWIO_GCC_TIC_CBCR_ATTR 0x3 +#define HWIO_GCC_TIC_CBCR_IN \ + in_dword_masked(HWIO_GCC_TIC_CBCR_ADDR, HWIO_GCC_TIC_CBCR_RMSK) +#define HWIO_GCC_TIC_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_TIC_CBCR_ADDR, m) +#define HWIO_GCC_TIC_CBCR_OUT(v) \ + out_dword(HWIO_GCC_TIC_CBCR_ADDR,v) +#define HWIO_GCC_TIC_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TIC_CBCR_ADDR,m,v,HWIO_GCC_TIC_CBCR_IN) +#define HWIO_GCC_TIC_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TIC_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TIC_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_TIC_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_TIC_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_TIC_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_TIC_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_TIC_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_TIC_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_TIC_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_TIC_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_TIC_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_TIC_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_TIC_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_TIC_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_TIC_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_TIC_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_TIC_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_TIC_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_TIC_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_TIC_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TIC_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TIC_CFG_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00002004) +#define HWIO_GCC_TIC_CFG_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00002004) +#define HWIO_GCC_TIC_CFG_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00002004) +#define HWIO_GCC_TIC_CFG_AHB_CBCR_RMSK 0x81d07fff +#define HWIO_GCC_TIC_CFG_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_TIC_CFG_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_TIC_CFG_AHB_CBCR_ADDR, HWIO_GCC_TIC_CFG_AHB_CBCR_RMSK) +#define HWIO_GCC_TIC_CFG_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_TIC_CFG_AHB_CBCR_ADDR, m) +#define HWIO_GCC_TIC_CFG_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_TIC_CFG_AHB_CBCR_ADDR,v) +#define HWIO_GCC_TIC_CFG_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TIC_CFG_AHB_CBCR_ADDR,m,v,HWIO_GCC_TIC_CFG_AHB_CBCR_IN) +#define HWIO_GCC_TIC_CFG_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TIC_CFG_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TIC_CFG_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_TIC_CFG_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_TIC_CFG_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_TIC_CFG_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_TIC_CFG_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_TIC_CFG_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_TIC_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_TIC_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_TIC_CFG_AHB_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_TIC_CFG_AHB_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_TIC_CFG_AHB_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TIC_CFG_AHB_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TIC_CFG_AHB_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_TIC_CFG_AHB_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_TIC_CFG_AHB_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TIC_CFG_AHB_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TIC_CFG_AHB_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_TIC_CFG_AHB_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_TIC_CFG_AHB_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TIC_CFG_AHB_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TIC_CFG_AHB_CBCR_WAKEUP_BMSK 0xf00 +#define HWIO_GCC_TIC_CFG_AHB_CBCR_WAKEUP_SHFT 0x8 +#define HWIO_GCC_TIC_CFG_AHB_CBCR_WAKEUP_CLOCK0_FVAL 0x0 +#define HWIO_GCC_TIC_CFG_AHB_CBCR_WAKEUP_CLOCK1_FVAL 0x1 +#define HWIO_GCC_TIC_CFG_AHB_CBCR_WAKEUP_CLOCK2_FVAL 0x2 +#define HWIO_GCC_TIC_CFG_AHB_CBCR_WAKEUP_CLOCK3_FVAL 0x3 +#define HWIO_GCC_TIC_CFG_AHB_CBCR_WAKEUP_CLOCK4_FVAL 0x4 +#define HWIO_GCC_TIC_CFG_AHB_CBCR_WAKEUP_CLOCK5_FVAL 0x5 +#define HWIO_GCC_TIC_CFG_AHB_CBCR_WAKEUP_CLOCK6_FVAL 0x6 +#define HWIO_GCC_TIC_CFG_AHB_CBCR_WAKEUP_CLOCK7_FVAL 0x7 +#define HWIO_GCC_TIC_CFG_AHB_CBCR_WAKEUP_CLOCK8_FVAL 0x8 +#define HWIO_GCC_TIC_CFG_AHB_CBCR_WAKEUP_CLOCK9_FVAL 0x9 +#define HWIO_GCC_TIC_CFG_AHB_CBCR_WAKEUP_CLOCK10_FVAL 0xa +#define HWIO_GCC_TIC_CFG_AHB_CBCR_WAKEUP_CLOCK11_FVAL 0xb +#define HWIO_GCC_TIC_CFG_AHB_CBCR_WAKEUP_CLOCK12_FVAL 0xc +#define HWIO_GCC_TIC_CFG_AHB_CBCR_WAKEUP_CLOCK13_FVAL 0xd +#define HWIO_GCC_TIC_CFG_AHB_CBCR_WAKEUP_CLOCK14_FVAL 0xe +#define HWIO_GCC_TIC_CFG_AHB_CBCR_WAKEUP_CLOCK15_FVAL 0xf +#define HWIO_GCC_TIC_CFG_AHB_CBCR_SLEEP_BMSK 0xf0 +#define HWIO_GCC_TIC_CFG_AHB_CBCR_SLEEP_SHFT 0x4 +#define HWIO_GCC_TIC_CFG_AHB_CBCR_SLEEP_CLOCK0_FVAL 0x0 +#define HWIO_GCC_TIC_CFG_AHB_CBCR_SLEEP_CLOCK1_FVAL 0x1 +#define HWIO_GCC_TIC_CFG_AHB_CBCR_SLEEP_CLOCK2_FVAL 0x2 +#define HWIO_GCC_TIC_CFG_AHB_CBCR_SLEEP_CLOCK3_FVAL 0x3 +#define HWIO_GCC_TIC_CFG_AHB_CBCR_SLEEP_CLOCK4_FVAL 0x4 +#define HWIO_GCC_TIC_CFG_AHB_CBCR_SLEEP_CLOCK5_FVAL 0x5 +#define HWIO_GCC_TIC_CFG_AHB_CBCR_SLEEP_CLOCK6_FVAL 0x6 +#define HWIO_GCC_TIC_CFG_AHB_CBCR_SLEEP_CLOCK7_FVAL 0x7 +#define HWIO_GCC_TIC_CFG_AHB_CBCR_SLEEP_CLOCK8_FVAL 0x8 +#define HWIO_GCC_TIC_CFG_AHB_CBCR_SLEEP_CLOCK9_FVAL 0x9 +#define HWIO_GCC_TIC_CFG_AHB_CBCR_SLEEP_CLOCK10_FVAL 0xa +#define HWIO_GCC_TIC_CFG_AHB_CBCR_SLEEP_CLOCK11_FVAL 0xb +#define HWIO_GCC_TIC_CFG_AHB_CBCR_SLEEP_CLOCK12_FVAL 0xc +#define HWIO_GCC_TIC_CFG_AHB_CBCR_SLEEP_CLOCK13_FVAL 0xd +#define HWIO_GCC_TIC_CFG_AHB_CBCR_SLEEP_CLOCK14_FVAL 0xe +#define HWIO_GCC_TIC_CFG_AHB_CBCR_SLEEP_CLOCK15_FVAL 0xf +#define HWIO_GCC_TIC_CFG_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_TIC_CFG_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_TIC_CFG_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_TIC_CFG_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_TIC_CFG_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_TIC_CFG_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_TIC_CFG_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_TIC_CFG_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_TIC_CFG_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_TIC_CFG_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_TIC_CFG_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_TIC_CFG_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_TIC_CFG_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TIC_CFG_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TIC_CFG_AHB_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00002008) +#define HWIO_GCC_TIC_CFG_AHB_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00002008) +#define HWIO_GCC_TIC_CFG_AHB_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00002008) +#define HWIO_GCC_TIC_CFG_AHB_SREGR_RMSK 0xfffffffe +#define HWIO_GCC_TIC_CFG_AHB_SREGR_ATTR 0x3 +#define HWIO_GCC_TIC_CFG_AHB_SREGR_IN \ + in_dword_masked(HWIO_GCC_TIC_CFG_AHB_SREGR_ADDR, HWIO_GCC_TIC_CFG_AHB_SREGR_RMSK) +#define HWIO_GCC_TIC_CFG_AHB_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_TIC_CFG_AHB_SREGR_ADDR, m) +#define HWIO_GCC_TIC_CFG_AHB_SREGR_OUT(v) \ + out_dword(HWIO_GCC_TIC_CFG_AHB_SREGR_ADDR,v) +#define HWIO_GCC_TIC_CFG_AHB_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TIC_CFG_AHB_SREGR_ADDR,m,v,HWIO_GCC_TIC_CFG_AHB_SREGR_IN) +#define HWIO_GCC_TIC_CFG_AHB_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xff000000 +#define HWIO_GCC_TIC_CFG_AHB_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_TIC_CFG_AHB_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xff0000 +#define HWIO_GCC_TIC_CFG_AHB_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_TIC_CFG_AHB_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_TIC_CFG_AHB_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_TIC_CFG_AHB_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_TIC_CFG_AHB_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_TIC_CFG_AHB_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_TIC_CFG_AHB_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_TIC_CFG_AHB_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_TIC_CFG_AHB_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_TIC_CFG_AHB_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_TIC_CFG_AHB_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_TIC_CFG_AHB_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_TIC_CFG_AHB_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_TIC_CFG_AHB_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_TIC_CFG_AHB_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_TIC_CFG_AHB_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_TIC_CFG_AHB_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_TIC_CFG_AHB_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_TIC_CFG_AHB_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_TIC_CFG_AHB_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_TIC_CFG_AHB_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_TIC_CFG_AHB_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_TIC_CFG_AHB_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_TIC_CFG_AHB_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_TIC_CFG_AHB_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_TIC_CFG_AHB_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_TIC_CFG_AHB_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_TIC_CFG_AHB_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_TIC_CFG_AHB_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_TIC_CFG_AHB_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TIC_CFG_AHB_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TIC_CFG_AHB_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_TIC_CFG_AHB_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_TIC_CFG_AHB_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_TIC_CFG_AHB_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TIC_CFG_AHB_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_TIC_CFG_AHB_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_TIC_CFG_AHB_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_TIC_CFG_AHB_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_TIC_CFG_AHB_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_TIC_CFG_AHB_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_TIC_CFG_AHB_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_TIC_CFG_AHB_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_TIC_CFG_AHB_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_TIC_CFG_AHB_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_TIC_CFG_AHB_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_TIC_CFG_AHB_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_TIC_CFG_AHB_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_TIC_CFG_AHB_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_TIC_CFG_AHB_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_TIC_CFG_AHB_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_TIC_CFG_AHB_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_TIC_CFG_AHB_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_TIC_CFG_AHB_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_TIC_CFG_AHB_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_IMEM_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00003000) +#define HWIO_GCC_IMEM_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00003000) +#define HWIO_GCC_IMEM_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00003000) +#define HWIO_GCC_IMEM_BCR_RMSK 0x1 +#define HWIO_GCC_IMEM_BCR_ATTR 0x3 +#define HWIO_GCC_IMEM_BCR_IN \ + in_dword_masked(HWIO_GCC_IMEM_BCR_ADDR, HWIO_GCC_IMEM_BCR_RMSK) +#define HWIO_GCC_IMEM_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_IMEM_BCR_ADDR, m) +#define HWIO_GCC_IMEM_BCR_OUT(v) \ + out_dword(HWIO_GCC_IMEM_BCR_ADDR,v) +#define HWIO_GCC_IMEM_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_IMEM_BCR_ADDR,m,v,HWIO_GCC_IMEM_BCR_IN) +#define HWIO_GCC_IMEM_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_IMEM_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_IMEM_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_IMEM_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_IMEM_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00003004) +#define HWIO_GCC_IMEM_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00003004) +#define HWIO_GCC_IMEM_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00003004) +#define HWIO_GCC_IMEM_AXI_CBCR_RMSK 0x81d07ff4 +#define HWIO_GCC_IMEM_AXI_CBCR_ATTR 0x3 +#define HWIO_GCC_IMEM_AXI_CBCR_IN \ + in_dword_masked(HWIO_GCC_IMEM_AXI_CBCR_ADDR, HWIO_GCC_IMEM_AXI_CBCR_RMSK) +#define HWIO_GCC_IMEM_AXI_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_IMEM_AXI_CBCR_ADDR, m) +#define HWIO_GCC_IMEM_AXI_CBCR_OUT(v) \ + out_dword(HWIO_GCC_IMEM_AXI_CBCR_ADDR,v) +#define HWIO_GCC_IMEM_AXI_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_IMEM_AXI_CBCR_ADDR,m,v,HWIO_GCC_IMEM_AXI_CBCR_IN) +#define HWIO_GCC_IMEM_AXI_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_IMEM_AXI_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_IMEM_AXI_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_IMEM_AXI_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_IMEM_AXI_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_IMEM_AXI_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_IMEM_AXI_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_IMEM_AXI_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_IMEM_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_IMEM_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_IMEM_AXI_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_IMEM_AXI_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_IMEM_AXI_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IMEM_AXI_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_IMEM_AXI_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_IMEM_AXI_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_IMEM_AXI_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IMEM_AXI_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_IMEM_AXI_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_IMEM_AXI_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_IMEM_AXI_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IMEM_AXI_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_IMEM_AXI_CBCR_WAKEUP_BMSK 0xf00 +#define HWIO_GCC_IMEM_AXI_CBCR_WAKEUP_SHFT 0x8 +#define HWIO_GCC_IMEM_AXI_CBCR_WAKEUP_CLOCK0_FVAL 0x0 +#define HWIO_GCC_IMEM_AXI_CBCR_WAKEUP_CLOCK1_FVAL 0x1 +#define HWIO_GCC_IMEM_AXI_CBCR_WAKEUP_CLOCK2_FVAL 0x2 +#define HWIO_GCC_IMEM_AXI_CBCR_WAKEUP_CLOCK3_FVAL 0x3 +#define HWIO_GCC_IMEM_AXI_CBCR_WAKEUP_CLOCK4_FVAL 0x4 +#define HWIO_GCC_IMEM_AXI_CBCR_WAKEUP_CLOCK5_FVAL 0x5 +#define HWIO_GCC_IMEM_AXI_CBCR_WAKEUP_CLOCK6_FVAL 0x6 +#define HWIO_GCC_IMEM_AXI_CBCR_WAKEUP_CLOCK7_FVAL 0x7 +#define HWIO_GCC_IMEM_AXI_CBCR_WAKEUP_CLOCK8_FVAL 0x8 +#define HWIO_GCC_IMEM_AXI_CBCR_WAKEUP_CLOCK9_FVAL 0x9 +#define HWIO_GCC_IMEM_AXI_CBCR_WAKEUP_CLOCK10_FVAL 0xa +#define HWIO_GCC_IMEM_AXI_CBCR_WAKEUP_CLOCK11_FVAL 0xb +#define HWIO_GCC_IMEM_AXI_CBCR_WAKEUP_CLOCK12_FVAL 0xc +#define HWIO_GCC_IMEM_AXI_CBCR_WAKEUP_CLOCK13_FVAL 0xd +#define HWIO_GCC_IMEM_AXI_CBCR_WAKEUP_CLOCK14_FVAL 0xe +#define HWIO_GCC_IMEM_AXI_CBCR_WAKEUP_CLOCK15_FVAL 0xf +#define HWIO_GCC_IMEM_AXI_CBCR_SLEEP_BMSK 0xf0 +#define HWIO_GCC_IMEM_AXI_CBCR_SLEEP_SHFT 0x4 +#define HWIO_GCC_IMEM_AXI_CBCR_SLEEP_CLOCK0_FVAL 0x0 +#define HWIO_GCC_IMEM_AXI_CBCR_SLEEP_CLOCK1_FVAL 0x1 +#define HWIO_GCC_IMEM_AXI_CBCR_SLEEP_CLOCK2_FVAL 0x2 +#define HWIO_GCC_IMEM_AXI_CBCR_SLEEP_CLOCK3_FVAL 0x3 +#define HWIO_GCC_IMEM_AXI_CBCR_SLEEP_CLOCK4_FVAL 0x4 +#define HWIO_GCC_IMEM_AXI_CBCR_SLEEP_CLOCK5_FVAL 0x5 +#define HWIO_GCC_IMEM_AXI_CBCR_SLEEP_CLOCK6_FVAL 0x6 +#define HWIO_GCC_IMEM_AXI_CBCR_SLEEP_CLOCK7_FVAL 0x7 +#define HWIO_GCC_IMEM_AXI_CBCR_SLEEP_CLOCK8_FVAL 0x8 +#define HWIO_GCC_IMEM_AXI_CBCR_SLEEP_CLOCK9_FVAL 0x9 +#define HWIO_GCC_IMEM_AXI_CBCR_SLEEP_CLOCK10_FVAL 0xa +#define HWIO_GCC_IMEM_AXI_CBCR_SLEEP_CLOCK11_FVAL 0xb +#define HWIO_GCC_IMEM_AXI_CBCR_SLEEP_CLOCK12_FVAL 0xc +#define HWIO_GCC_IMEM_AXI_CBCR_SLEEP_CLOCK13_FVAL 0xd +#define HWIO_GCC_IMEM_AXI_CBCR_SLEEP_CLOCK14_FVAL 0xe +#define HWIO_GCC_IMEM_AXI_CBCR_SLEEP_CLOCK15_FVAL 0xf +#define HWIO_GCC_IMEM_AXI_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_IMEM_AXI_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_IMEM_AXI_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_IMEM_AXI_CBCR_CLK_ARES_RESET_FVAL 0x1 + +#define HWIO_GCC_IMEM_AXI_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00003008) +#define HWIO_GCC_IMEM_AXI_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00003008) +#define HWIO_GCC_IMEM_AXI_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00003008) +#define HWIO_GCC_IMEM_AXI_SREGR_RMSK 0xfffffffe +#define HWIO_GCC_IMEM_AXI_SREGR_ATTR 0x3 +#define HWIO_GCC_IMEM_AXI_SREGR_IN \ + in_dword_masked(HWIO_GCC_IMEM_AXI_SREGR_ADDR, HWIO_GCC_IMEM_AXI_SREGR_RMSK) +#define HWIO_GCC_IMEM_AXI_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_IMEM_AXI_SREGR_ADDR, m) +#define HWIO_GCC_IMEM_AXI_SREGR_OUT(v) \ + out_dword(HWIO_GCC_IMEM_AXI_SREGR_ADDR,v) +#define HWIO_GCC_IMEM_AXI_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_IMEM_AXI_SREGR_ADDR,m,v,HWIO_GCC_IMEM_AXI_SREGR_IN) +#define HWIO_GCC_IMEM_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xff000000 +#define HWIO_GCC_IMEM_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_IMEM_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xff0000 +#define HWIO_GCC_IMEM_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_IMEM_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_IMEM_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_IMEM_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_IMEM_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_IMEM_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_IMEM_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_IMEM_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_IMEM_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_IMEM_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_IMEM_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_IMEM_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_IMEM_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_IMEM_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_IMEM_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_IMEM_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_IMEM_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_IMEM_AXI_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_IMEM_AXI_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_IMEM_AXI_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_IMEM_AXI_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_IMEM_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_IMEM_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_IMEM_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_IMEM_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_IMEM_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_IMEM_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_IMEM_AXI_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_IMEM_AXI_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_IMEM_AXI_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IMEM_AXI_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_IMEM_AXI_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_IMEM_AXI_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_IMEM_AXI_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_IMEM_AXI_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_IMEM_AXI_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_IMEM_AXI_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_IMEM_AXI_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_IMEM_AXI_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_IMEM_AXI_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_IMEM_AXI_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_IMEM_AXI_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_IMEM_AXI_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_IMEM_AXI_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_IMEM_AXI_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_IMEM_AXI_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_IMEM_AXI_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_IMEM_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_IMEM_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_IMEM_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_IMEM_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_IMEM_AXI_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_IMEM_AXI_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_IMEM_AXI_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_IMEM_AXI_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_IMEM_CFG_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000300c) +#define HWIO_GCC_IMEM_CFG_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000300c) +#define HWIO_GCC_IMEM_CFG_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000300c) +#define HWIO_GCC_IMEM_CFG_AHB_CBCR_RMSK 0x81d00005 +#define HWIO_GCC_IMEM_CFG_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_IMEM_CFG_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_IMEM_CFG_AHB_CBCR_ADDR, HWIO_GCC_IMEM_CFG_AHB_CBCR_RMSK) +#define HWIO_GCC_IMEM_CFG_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_IMEM_CFG_AHB_CBCR_ADDR, m) +#define HWIO_GCC_IMEM_CFG_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_IMEM_CFG_AHB_CBCR_ADDR,v) +#define HWIO_GCC_IMEM_CFG_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_IMEM_CFG_AHB_CBCR_ADDR,m,v,HWIO_GCC_IMEM_CFG_AHB_CBCR_IN) +#define HWIO_GCC_IMEM_CFG_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_IMEM_CFG_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_IMEM_CFG_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_IMEM_CFG_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_IMEM_CFG_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_IMEM_CFG_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_IMEM_CFG_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_IMEM_CFG_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_IMEM_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_IMEM_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_IMEM_CFG_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_IMEM_CFG_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_IMEM_CFG_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_IMEM_CFG_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_IMEM_CFG_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_IMEM_CFG_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_IMEM_CFG_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IMEM_CFG_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MMU_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00004000) +#define HWIO_GCC_MMU_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004000) +#define HWIO_GCC_MMU_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004000) +#define HWIO_GCC_MMU_BCR_RMSK 0x1 +#define HWIO_GCC_MMU_BCR_ATTR 0x3 +#define HWIO_GCC_MMU_BCR_IN \ + in_dword_masked(HWIO_GCC_MMU_BCR_ADDR, HWIO_GCC_MMU_BCR_RMSK) +#define HWIO_GCC_MMU_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_MMU_BCR_ADDR, m) +#define HWIO_GCC_MMU_BCR_OUT(v) \ + out_dword(HWIO_GCC_MMU_BCR_ADDR,v) +#define HWIO_GCC_MMU_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MMU_BCR_ADDR,m,v,HWIO_GCC_MMU_BCR_IN) +#define HWIO_GCC_MMU_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_MMU_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_MMU_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMU_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SYS_NOC_TCU_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00004004) +#define HWIO_GCC_SYS_NOC_TCU_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004004) +#define HWIO_GCC_SYS_NOC_TCU_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004004) +#define HWIO_GCC_SYS_NOC_TCU_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_SYS_NOC_TCU_CBCR_ATTR 0x3 +#define HWIO_GCC_SYS_NOC_TCU_CBCR_IN \ + in_dword_masked(HWIO_GCC_SYS_NOC_TCU_CBCR_ADDR, HWIO_GCC_SYS_NOC_TCU_CBCR_RMSK) +#define HWIO_GCC_SYS_NOC_TCU_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_SYS_NOC_TCU_CBCR_ADDR, m) +#define HWIO_GCC_SYS_NOC_TCU_CBCR_OUT(v) \ + out_dword(HWIO_GCC_SYS_NOC_TCU_CBCR_ADDR,v) +#define HWIO_GCC_SYS_NOC_TCU_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SYS_NOC_TCU_CBCR_ADDR,m,v,HWIO_GCC_SYS_NOC_TCU_CBCR_IN) +#define HWIO_GCC_SYS_NOC_TCU_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SYS_NOC_TCU_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SYS_NOC_TCU_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_SYS_NOC_TCU_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_SYS_NOC_TCU_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_SYS_NOC_TCU_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_SYS_NOC_TCU_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_SYS_NOC_TCU_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_SYS_NOC_TCU_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_SYS_NOC_TCU_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_SYS_NOC_TCU_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_SYS_NOC_TCU_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_SYS_NOC_TCU_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_SYS_NOC_TCU_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_SYS_NOC_TCU_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_TCU_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_TCU_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_SYS_NOC_TCU_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_SYS_NOC_TCU_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_TCU_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_TCU_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SYS_NOC_TCU_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SYS_NOC_TCU_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_TCU_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MMU_TCU_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00004008) +#define HWIO_GCC_MMU_TCU_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004008) +#define HWIO_GCC_MMU_TCU_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004008) +#define HWIO_GCC_MMU_TCU_CBCR_RMSK 0x81d07fff +#define HWIO_GCC_MMU_TCU_CBCR_ATTR 0x3 +#define HWIO_GCC_MMU_TCU_CBCR_IN \ + in_dword_masked(HWIO_GCC_MMU_TCU_CBCR_ADDR, HWIO_GCC_MMU_TCU_CBCR_RMSK) +#define HWIO_GCC_MMU_TCU_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_MMU_TCU_CBCR_ADDR, m) +#define HWIO_GCC_MMU_TCU_CBCR_OUT(v) \ + out_dword(HWIO_GCC_MMU_TCU_CBCR_ADDR,v) +#define HWIO_GCC_MMU_TCU_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MMU_TCU_CBCR_ADDR,m,v,HWIO_GCC_MMU_TCU_CBCR_IN) +#define HWIO_GCC_MMU_TCU_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_MMU_TCU_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_MMU_TCU_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_MMU_TCU_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_MMU_TCU_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_MMU_TCU_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_MMU_TCU_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_MMU_TCU_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_MMU_TCU_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_MMU_TCU_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_MMU_TCU_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_MMU_TCU_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_MMU_TCU_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMU_TCU_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMU_TCU_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_MMU_TCU_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_MMU_TCU_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMU_TCU_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMU_TCU_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_MMU_TCU_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_MMU_TCU_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMU_TCU_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMU_TCU_CBCR_WAKEUP_BMSK 0xf00 +#define HWIO_GCC_MMU_TCU_CBCR_WAKEUP_SHFT 0x8 +#define HWIO_GCC_MMU_TCU_CBCR_WAKEUP_CLOCK0_FVAL 0x0 +#define HWIO_GCC_MMU_TCU_CBCR_WAKEUP_CLOCK1_FVAL 0x1 +#define HWIO_GCC_MMU_TCU_CBCR_WAKEUP_CLOCK2_FVAL 0x2 +#define HWIO_GCC_MMU_TCU_CBCR_WAKEUP_CLOCK3_FVAL 0x3 +#define HWIO_GCC_MMU_TCU_CBCR_WAKEUP_CLOCK4_FVAL 0x4 +#define HWIO_GCC_MMU_TCU_CBCR_WAKEUP_CLOCK5_FVAL 0x5 +#define HWIO_GCC_MMU_TCU_CBCR_WAKEUP_CLOCK6_FVAL 0x6 +#define HWIO_GCC_MMU_TCU_CBCR_WAKEUP_CLOCK7_FVAL 0x7 +#define HWIO_GCC_MMU_TCU_CBCR_WAKEUP_CLOCK8_FVAL 0x8 +#define HWIO_GCC_MMU_TCU_CBCR_WAKEUP_CLOCK9_FVAL 0x9 +#define HWIO_GCC_MMU_TCU_CBCR_WAKEUP_CLOCK10_FVAL 0xa +#define HWIO_GCC_MMU_TCU_CBCR_WAKEUP_CLOCK11_FVAL 0xb +#define HWIO_GCC_MMU_TCU_CBCR_WAKEUP_CLOCK12_FVAL 0xc +#define HWIO_GCC_MMU_TCU_CBCR_WAKEUP_CLOCK13_FVAL 0xd +#define HWIO_GCC_MMU_TCU_CBCR_WAKEUP_CLOCK14_FVAL 0xe +#define HWIO_GCC_MMU_TCU_CBCR_WAKEUP_CLOCK15_FVAL 0xf +#define HWIO_GCC_MMU_TCU_CBCR_SLEEP_BMSK 0xf0 +#define HWIO_GCC_MMU_TCU_CBCR_SLEEP_SHFT 0x4 +#define HWIO_GCC_MMU_TCU_CBCR_SLEEP_CLOCK0_FVAL 0x0 +#define HWIO_GCC_MMU_TCU_CBCR_SLEEP_CLOCK1_FVAL 0x1 +#define HWIO_GCC_MMU_TCU_CBCR_SLEEP_CLOCK2_FVAL 0x2 +#define HWIO_GCC_MMU_TCU_CBCR_SLEEP_CLOCK3_FVAL 0x3 +#define HWIO_GCC_MMU_TCU_CBCR_SLEEP_CLOCK4_FVAL 0x4 +#define HWIO_GCC_MMU_TCU_CBCR_SLEEP_CLOCK5_FVAL 0x5 +#define HWIO_GCC_MMU_TCU_CBCR_SLEEP_CLOCK6_FVAL 0x6 +#define HWIO_GCC_MMU_TCU_CBCR_SLEEP_CLOCK7_FVAL 0x7 +#define HWIO_GCC_MMU_TCU_CBCR_SLEEP_CLOCK8_FVAL 0x8 +#define HWIO_GCC_MMU_TCU_CBCR_SLEEP_CLOCK9_FVAL 0x9 +#define HWIO_GCC_MMU_TCU_CBCR_SLEEP_CLOCK10_FVAL 0xa +#define HWIO_GCC_MMU_TCU_CBCR_SLEEP_CLOCK11_FVAL 0xb +#define HWIO_GCC_MMU_TCU_CBCR_SLEEP_CLOCK12_FVAL 0xc +#define HWIO_GCC_MMU_TCU_CBCR_SLEEP_CLOCK13_FVAL 0xd +#define HWIO_GCC_MMU_TCU_CBCR_SLEEP_CLOCK14_FVAL 0xe +#define HWIO_GCC_MMU_TCU_CBCR_SLEEP_CLOCK15_FVAL 0xf +#define HWIO_GCC_MMU_TCU_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_MMU_TCU_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_MMU_TCU_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_MMU_TCU_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_MMU_TCU_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_MMU_TCU_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_MMU_TCU_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_MMU_TCU_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_MMU_TCU_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMU_TCU_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMU_TCU_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_MMU_TCU_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_MMU_TCU_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMU_TCU_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MMU_TCU_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000400c) +#define HWIO_GCC_MMU_TCU_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000400c) +#define HWIO_GCC_MMU_TCU_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000400c) +#define HWIO_GCC_MMU_TCU_SREGR_RMSK 0xfffffffe +#define HWIO_GCC_MMU_TCU_SREGR_ATTR 0x3 +#define HWIO_GCC_MMU_TCU_SREGR_IN \ + in_dword_masked(HWIO_GCC_MMU_TCU_SREGR_ADDR, HWIO_GCC_MMU_TCU_SREGR_RMSK) +#define HWIO_GCC_MMU_TCU_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_MMU_TCU_SREGR_ADDR, m) +#define HWIO_GCC_MMU_TCU_SREGR_OUT(v) \ + out_dword(HWIO_GCC_MMU_TCU_SREGR_ADDR,v) +#define HWIO_GCC_MMU_TCU_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MMU_TCU_SREGR_ADDR,m,v,HWIO_GCC_MMU_TCU_SREGR_IN) +#define HWIO_GCC_MMU_TCU_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xff000000 +#define HWIO_GCC_MMU_TCU_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_MMU_TCU_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xff0000 +#define HWIO_GCC_MMU_TCU_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_MMU_TCU_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_MMU_TCU_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_MMU_TCU_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_MMU_TCU_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_MMU_TCU_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_MMU_TCU_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_MMU_TCU_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_MMU_TCU_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_MMU_TCU_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_MMU_TCU_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_MMU_TCU_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_MMU_TCU_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_MMU_TCU_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_MMU_TCU_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_MMU_TCU_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_MMU_TCU_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_MMU_TCU_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_MMU_TCU_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_MMU_TCU_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_MMU_TCU_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_MMU_TCU_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_MMU_TCU_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_MMU_TCU_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_MMU_TCU_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_MMU_TCU_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_MMU_TCU_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_MMU_TCU_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_MMU_TCU_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_MMU_TCU_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMU_TCU_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMU_TCU_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_MMU_TCU_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_MMU_TCU_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_MMU_TCU_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMU_TCU_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_MMU_TCU_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_MMU_TCU_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_MMU_TCU_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_MMU_TCU_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_MMU_TCU_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_MMU_TCU_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_MMU_TCU_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_MMU_TCU_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_MMU_TCU_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_MMU_TCU_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_MMU_TCU_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_MMU_TCU_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_MMU_TCU_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_MMU_TCU_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_MMU_TCU_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_MMU_TCU_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_MMU_TCU_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_MMU_TCU_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMU_TCU_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00004024) +#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004024) +#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004024) +#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_RMSK 0xfffff +#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_CMD_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_CMD_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_CMD_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_CMD_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_CMD_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_CMD_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_RCG_SW_CTRL_BMSK 0xf8000 +#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_RCG_SW_CTRL_SHFT 0xf +#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_SW_PERF_STATE_BMSK 0x7800 +#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_SW_PERF_STATE_SHFT 0xb +#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_SW_OVERRIDE_BMSK 0x400 +#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_SW_OVERRIDE_SHFT 0xa +#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK 0x200 +#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT 0x9 +#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_DFS_FSM_STATE_BMSK 0x1c0 +#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_DFS_FSM_STATE_SHFT 0x6 +#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_HW_CLK_CONTROL_BMSK 0x20 +#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_HW_CLK_CONTROL_SHFT 0x5 +#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_CURR_PERF_STATE_BMSK 0x1e +#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_CURR_PERF_STATE_SHFT 0x1 +#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_DFS_EN_BMSK 0x1 +#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_DFS_EN_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_DFS_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_DFS_EN_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000402c) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000402c) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000402c) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00004030) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004030) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004030) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00004034) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004034) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004034) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00004038) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004038) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004038) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000403c) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000403c) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000403c) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00004040) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004040) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004040) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00004044) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004044) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004044) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00004048) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004048) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004048) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000404c) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000404c) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000404c) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00004050) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004050) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004050) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00004054) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004054) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004054) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00004058) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004058) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004058) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000405c) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000405c) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000405c) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00004060) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004060) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004060) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00004064) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004064) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004064) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00004068) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004068) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004068) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_MMU_TCU_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00004010) +#define HWIO_GCC_MMU_TCU_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004010) +#define HWIO_GCC_MMU_TCU_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004010) +#define HWIO_GCC_MMU_TCU_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_MMU_TCU_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_MMU_TCU_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_MMU_TCU_CMD_RCGR_ADDR, HWIO_GCC_MMU_TCU_CMD_RCGR_RMSK) +#define HWIO_GCC_MMU_TCU_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_MMU_TCU_CMD_RCGR_ADDR, m) +#define HWIO_GCC_MMU_TCU_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_MMU_TCU_CMD_RCGR_ADDR,v) +#define HWIO_GCC_MMU_TCU_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MMU_TCU_CMD_RCGR_ADDR,m,v,HWIO_GCC_MMU_TCU_CMD_RCGR_IN) +#define HWIO_GCC_MMU_TCU_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_MMU_TCU_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_MMU_TCU_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_MMU_TCU_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_MMU_TCU_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_MMU_TCU_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_MMU_TCU_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMU_TCU_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMU_TCU_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_MMU_TCU_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_MMU_TCU_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMU_TCU_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MMU_TCU_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00004014) +#define HWIO_GCC_MMU_TCU_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004014) +#define HWIO_GCC_MMU_TCU_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004014) +#define HWIO_GCC_MMU_TCU_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_MMU_TCU_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_MMU_TCU_CFG_RCGR_ADDR, HWIO_GCC_MMU_TCU_CFG_RCGR_RMSK) +#define HWIO_GCC_MMU_TCU_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_MMU_TCU_CFG_RCGR_ADDR, m) +#define HWIO_GCC_MMU_TCU_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_MMU_TCU_CFG_RCGR_ADDR,v) +#define HWIO_GCC_MMU_TCU_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MMU_TCU_CFG_RCGR_ADDR,m,v,HWIO_GCC_MMU_TCU_CFG_RCGR_IN) +#define HWIO_GCC_MMU_TCU_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_MMU_TCU_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000413c) +#define HWIO_GCC_MMU_TCU_DCD_CDIV_DCDR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000413c) +#define HWIO_GCC_MMU_TCU_DCD_CDIV_DCDR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000413c) +#define HWIO_GCC_MMU_TCU_DCD_CDIV_DCDR_RMSK 0x1 +#define HWIO_GCC_MMU_TCU_DCD_CDIV_DCDR_ATTR 0x3 +#define HWIO_GCC_MMU_TCU_DCD_CDIV_DCDR_IN \ + in_dword_masked(HWIO_GCC_MMU_TCU_DCD_CDIV_DCDR_ADDR, HWIO_GCC_MMU_TCU_DCD_CDIV_DCDR_RMSK) +#define HWIO_GCC_MMU_TCU_DCD_CDIV_DCDR_INM(m) \ + in_dword_masked(HWIO_GCC_MMU_TCU_DCD_CDIV_DCDR_ADDR, m) +#define HWIO_GCC_MMU_TCU_DCD_CDIV_DCDR_OUT(v) \ + out_dword(HWIO_GCC_MMU_TCU_DCD_CDIV_DCDR_ADDR,v) +#define HWIO_GCC_MMU_TCU_DCD_CDIV_DCDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MMU_TCU_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_MMU_TCU_DCD_CDIV_DCDR_IN) +#define HWIO_GCC_MMU_TCU_DCD_CDIV_DCDR_DCD_ENABLE_BMSK 0x1 +#define HWIO_GCC_MMU_TCU_DCD_CDIV_DCDR_DCD_ENABLE_SHFT 0x0 +#define HWIO_GCC_MMU_TCU_DCD_CDIV_DCDR_DCD_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMU_TCU_DCD_CDIV_DCDR_DCD_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_ANOC_TBU_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00005000) +#define HWIO_GCC_ANOC_TBU_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00005000) +#define HWIO_GCC_ANOC_TBU_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00005000) +#define HWIO_GCC_ANOC_TBU_BCR_RMSK 0x1 +#define HWIO_GCC_ANOC_TBU_BCR_ATTR 0x3 +#define HWIO_GCC_ANOC_TBU_BCR_IN \ + in_dword_masked(HWIO_GCC_ANOC_TBU_BCR_ADDR, HWIO_GCC_ANOC_TBU_BCR_RMSK) +#define HWIO_GCC_ANOC_TBU_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_ANOC_TBU_BCR_ADDR, m) +#define HWIO_GCC_ANOC_TBU_BCR_OUT(v) \ + out_dword(HWIO_GCC_ANOC_TBU_BCR_ADDR,v) +#define HWIO_GCC_ANOC_TBU_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ANOC_TBU_BCR_ADDR,m,v,HWIO_GCC_ANOC_TBU_BCR_IN) +#define HWIO_GCC_ANOC_TBU_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_ANOC_TBU_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_ANOC_TBU_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_ANOC_TBU_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00005004) +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00005004) +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00005004) +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_RMSK 0x81d07fff +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_ATTR 0x3 +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_IN \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_TBU1_CBCR_ADDR, HWIO_GCC_AGGRE_NOC_TBU1_CBCR_RMSK) +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_TBU1_CBCR_ADDR, m) +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_OUT(v) \ + out_dword(HWIO_GCC_AGGRE_NOC_TBU1_CBCR_ADDR,v) +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_TBU1_CBCR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_TBU1_CBCR_IN) +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_WAKEUP_BMSK 0xf00 +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_WAKEUP_SHFT 0x8 +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_WAKEUP_CLOCK0_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_WAKEUP_CLOCK1_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_WAKEUP_CLOCK2_FVAL 0x2 +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_WAKEUP_CLOCK3_FVAL 0x3 +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_WAKEUP_CLOCK4_FVAL 0x4 +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_WAKEUP_CLOCK5_FVAL 0x5 +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_WAKEUP_CLOCK6_FVAL 0x6 +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_WAKEUP_CLOCK7_FVAL 0x7 +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_WAKEUP_CLOCK8_FVAL 0x8 +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_WAKEUP_CLOCK9_FVAL 0x9 +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_WAKEUP_CLOCK10_FVAL 0xa +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_WAKEUP_CLOCK11_FVAL 0xb +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_WAKEUP_CLOCK12_FVAL 0xc +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_WAKEUP_CLOCK13_FVAL 0xd +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_WAKEUP_CLOCK14_FVAL 0xe +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_WAKEUP_CLOCK15_FVAL 0xf +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_SLEEP_BMSK 0xf0 +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_SLEEP_SHFT 0x4 +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_SLEEP_CLOCK0_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_SLEEP_CLOCK1_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_SLEEP_CLOCK2_FVAL 0x2 +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_SLEEP_CLOCK3_FVAL 0x3 +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_SLEEP_CLOCK4_FVAL 0x4 +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_SLEEP_CLOCK5_FVAL 0x5 +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_SLEEP_CLOCK6_FVAL 0x6 +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_SLEEP_CLOCK7_FVAL 0x7 +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_SLEEP_CLOCK8_FVAL 0x8 +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_SLEEP_CLOCK9_FVAL 0x9 +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_SLEEP_CLOCK10_FVAL 0xa +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_SLEEP_CLOCK11_FVAL 0xb +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_SLEEP_CLOCK12_FVAL 0xc +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_SLEEP_CLOCK13_FVAL 0xd +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_SLEEP_CLOCK14_FVAL 0xe +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_SLEEP_CLOCK15_FVAL 0xf +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00005008) +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00005008) +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00005008) +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_RMSK 0xfffffffe +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_ATTR 0x3 +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_IN \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_TBU1_SREGR_ADDR, HWIO_GCC_AGGRE_NOC_TBU1_SREGR_RMSK) +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_TBU1_SREGR_ADDR, m) +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_OUT(v) \ + out_dword(HWIO_GCC_AGGRE_NOC_TBU1_SREGR_ADDR,v) +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_TBU1_SREGR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_TBU1_SREGR_IN) +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xff000000 +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xff0000 +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000500c) +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000500c) +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000500c) +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_RMSK 0x81d07fff +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_ATTR 0x3 +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_IN \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_TBU2_CBCR_ADDR, HWIO_GCC_AGGRE_NOC_TBU2_CBCR_RMSK) +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_TBU2_CBCR_ADDR, m) +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_OUT(v) \ + out_dword(HWIO_GCC_AGGRE_NOC_TBU2_CBCR_ADDR,v) +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_TBU2_CBCR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_TBU2_CBCR_IN) +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_WAKEUP_BMSK 0xf00 +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_WAKEUP_SHFT 0x8 +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_WAKEUP_CLOCK0_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_WAKEUP_CLOCK1_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_WAKEUP_CLOCK2_FVAL 0x2 +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_WAKEUP_CLOCK3_FVAL 0x3 +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_WAKEUP_CLOCK4_FVAL 0x4 +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_WAKEUP_CLOCK5_FVAL 0x5 +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_WAKEUP_CLOCK6_FVAL 0x6 +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_WAKEUP_CLOCK7_FVAL 0x7 +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_WAKEUP_CLOCK8_FVAL 0x8 +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_WAKEUP_CLOCK9_FVAL 0x9 +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_WAKEUP_CLOCK10_FVAL 0xa +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_WAKEUP_CLOCK11_FVAL 0xb +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_WAKEUP_CLOCK12_FVAL 0xc +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_WAKEUP_CLOCK13_FVAL 0xd +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_WAKEUP_CLOCK14_FVAL 0xe +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_WAKEUP_CLOCK15_FVAL 0xf +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_SLEEP_BMSK 0xf0 +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_SLEEP_SHFT 0x4 +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_SLEEP_CLOCK0_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_SLEEP_CLOCK1_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_SLEEP_CLOCK2_FVAL 0x2 +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_SLEEP_CLOCK3_FVAL 0x3 +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_SLEEP_CLOCK4_FVAL 0x4 +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_SLEEP_CLOCK5_FVAL 0x5 +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_SLEEP_CLOCK6_FVAL 0x6 +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_SLEEP_CLOCK7_FVAL 0x7 +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_SLEEP_CLOCK8_FVAL 0x8 +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_SLEEP_CLOCK9_FVAL 0x9 +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_SLEEP_CLOCK10_FVAL 0xa +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_SLEEP_CLOCK11_FVAL 0xb +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_SLEEP_CLOCK12_FVAL 0xc +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_SLEEP_CLOCK13_FVAL 0xd +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_SLEEP_CLOCK14_FVAL 0xe +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_SLEEP_CLOCK15_FVAL 0xf +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00005010) +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00005010) +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00005010) +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_RMSK 0xfffffffe +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_ATTR 0x3 +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_IN \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_TBU2_SREGR_ADDR, HWIO_GCC_AGGRE_NOC_TBU2_SREGR_RMSK) +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_TBU2_SREGR_ADDR, m) +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_OUT(v) \ + out_dword(HWIO_GCC_AGGRE_NOC_TBU2_SREGR_ADDR,v) +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_TBU2_SREGR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_TBU2_SREGR_IN) +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xff000000 +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xff0000 +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QDSS_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006000) +#define HWIO_GCC_QDSS_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00006000) +#define HWIO_GCC_QDSS_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00006000) +#define HWIO_GCC_QDSS_BCR_RMSK 0x1 +#define HWIO_GCC_QDSS_BCR_ATTR 0x3 +#define HWIO_GCC_QDSS_BCR_IN \ + in_dword_masked(HWIO_GCC_QDSS_BCR_ADDR, HWIO_GCC_QDSS_BCR_RMSK) +#define HWIO_GCC_QDSS_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_QDSS_BCR_ADDR, m) +#define HWIO_GCC_QDSS_BCR_OUT(v) \ + out_dword(HWIO_GCC_QDSS_BCR_ADDR,v) +#define HWIO_GCC_QDSS_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QDSS_BCR_ADDR,m,v,HWIO_GCC_QDSS_BCR_IN) +#define HWIO_GCC_QDSS_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_QDSS_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_QDSS_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006004) +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00006004) +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00006004) +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_QDSS_DAP_AHB_CBCR_ADDR, HWIO_GCC_QDSS_DAP_AHB_CBCR_RMSK) +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QDSS_DAP_AHB_CBCR_ADDR, m) +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QDSS_DAP_AHB_CBCR_ADDR,v) +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QDSS_DAP_AHB_CBCR_ADDR,m,v,HWIO_GCC_QDSS_DAP_AHB_CBCR_IN) +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006008) +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00006008) +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00006008) +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_RMSK 0x81d0000e +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_QDSS_CFG_AHB_CBCR_ADDR, HWIO_GCC_QDSS_CFG_AHB_CBCR_RMSK) +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QDSS_CFG_AHB_CBCR_ADDR, m) +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QDSS_CFG_AHB_CBCR_ADDR,v) +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QDSS_CFG_AHB_CBCR_ADDR,m,v,HWIO_GCC_QDSS_CFG_AHB_CBCR_IN) +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QDSS_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000600c) +#define HWIO_GCC_QDSS_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000600c) +#define HWIO_GCC_QDSS_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000600c) +#define HWIO_GCC_QDSS_AT_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_QDSS_AT_CBCR_ATTR 0x3 +#define HWIO_GCC_QDSS_AT_CBCR_IN \ + in_dword_masked(HWIO_GCC_QDSS_AT_CBCR_ADDR, HWIO_GCC_QDSS_AT_CBCR_RMSK) +#define HWIO_GCC_QDSS_AT_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QDSS_AT_CBCR_ADDR, m) +#define HWIO_GCC_QDSS_AT_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QDSS_AT_CBCR_ADDR,v) +#define HWIO_GCC_QDSS_AT_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QDSS_AT_CBCR_ADDR,m,v,HWIO_GCC_QDSS_AT_CBCR_IN) +#define HWIO_GCC_QDSS_AT_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QDSS_AT_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QDSS_AT_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QDSS_AT_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QDSS_AT_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QDSS_AT_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QDSS_AT_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QDSS_AT_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QDSS_AT_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_QDSS_AT_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_QDSS_AT_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_QDSS_AT_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_QDSS_AT_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QDSS_AT_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QDSS_AT_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QDSS_AT_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_QDSS_AT_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_QDSS_AT_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_QDSS_AT_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_AT_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QDSS_AT_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_QDSS_AT_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_QDSS_AT_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_AT_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QDSS_ETR_USB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006010) +#define HWIO_GCC_QDSS_ETR_USB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00006010) +#define HWIO_GCC_QDSS_ETR_USB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00006010) +#define HWIO_GCC_QDSS_ETR_USB_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_QDSS_ETR_USB_CBCR_ATTR 0x3 +#define HWIO_GCC_QDSS_ETR_USB_CBCR_IN \ + in_dword_masked(HWIO_GCC_QDSS_ETR_USB_CBCR_ADDR, HWIO_GCC_QDSS_ETR_USB_CBCR_RMSK) +#define HWIO_GCC_QDSS_ETR_USB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QDSS_ETR_USB_CBCR_ADDR, m) +#define HWIO_GCC_QDSS_ETR_USB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QDSS_ETR_USB_CBCR_ADDR,v) +#define HWIO_GCC_QDSS_ETR_USB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QDSS_ETR_USB_CBCR_ADDR,m,v,HWIO_GCC_QDSS_ETR_USB_CBCR_IN) +#define HWIO_GCC_QDSS_ETR_USB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QDSS_ETR_USB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QDSS_ETR_USB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QDSS_ETR_USB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QDSS_ETR_USB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QDSS_ETR_USB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QDSS_ETR_USB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QDSS_ETR_USB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QDSS_ETR_USB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_QDSS_ETR_USB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_QDSS_ETR_USB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_QDSS_ETR_USB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_QDSS_ETR_USB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QDSS_ETR_USB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QDSS_ETR_USB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QDSS_ETR_USB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_QDSS_ETR_USB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_QDSS_ETR_USB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_QDSS_ETR_USB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_ETR_USB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QDSS_ETR_USB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_QDSS_ETR_USB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_QDSS_ETR_USB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_ETR_USB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QDSS_STM_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006014) +#define HWIO_GCC_QDSS_STM_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00006014) +#define HWIO_GCC_QDSS_STM_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00006014) +#define HWIO_GCC_QDSS_STM_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_QDSS_STM_CBCR_ATTR 0x3 +#define HWIO_GCC_QDSS_STM_CBCR_IN \ + in_dword_masked(HWIO_GCC_QDSS_STM_CBCR_ADDR, HWIO_GCC_QDSS_STM_CBCR_RMSK) +#define HWIO_GCC_QDSS_STM_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QDSS_STM_CBCR_ADDR, m) +#define HWIO_GCC_QDSS_STM_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QDSS_STM_CBCR_ADDR,v) +#define HWIO_GCC_QDSS_STM_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QDSS_STM_CBCR_ADDR,m,v,HWIO_GCC_QDSS_STM_CBCR_IN) +#define HWIO_GCC_QDSS_STM_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QDSS_STM_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QDSS_STM_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QDSS_STM_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QDSS_STM_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QDSS_STM_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QDSS_STM_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QDSS_STM_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QDSS_STM_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_QDSS_STM_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_QDSS_STM_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_QDSS_STM_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_QDSS_STM_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QDSS_STM_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QDSS_STM_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QDSS_STM_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_QDSS_STM_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_QDSS_STM_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_QDSS_STM_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_STM_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QDSS_STM_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_QDSS_STM_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_QDSS_STM_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_STM_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006018) +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00006018) +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00006018) +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_ATTR 0x3 +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_IN \ + in_dword_masked(HWIO_GCC_QDSS_TRACECLKIN_CBCR_ADDR, HWIO_GCC_QDSS_TRACECLKIN_CBCR_RMSK) +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QDSS_TRACECLKIN_CBCR_ADDR, m) +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QDSS_TRACECLKIN_CBCR_ADDR,v) +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QDSS_TRACECLKIN_CBCR_ADDR,m,v,HWIO_GCC_QDSS_TRACECLKIN_CBCR_IN) +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QDSS_TSCTR_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000601c) +#define HWIO_GCC_QDSS_TSCTR_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000601c) +#define HWIO_GCC_QDSS_TSCTR_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000601c) +#define HWIO_GCC_QDSS_TSCTR_CBCR_RMSK 0x81c0000f +#define HWIO_GCC_QDSS_TSCTR_CBCR_ATTR 0x3 +#define HWIO_GCC_QDSS_TSCTR_CBCR_IN \ + in_dword_masked(HWIO_GCC_QDSS_TSCTR_CBCR_ADDR, HWIO_GCC_QDSS_TSCTR_CBCR_RMSK) +#define HWIO_GCC_QDSS_TSCTR_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QDSS_TSCTR_CBCR_ADDR, m) +#define HWIO_GCC_QDSS_TSCTR_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QDSS_TSCTR_CBCR_ADDR,v) +#define HWIO_GCC_QDSS_TSCTR_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QDSS_TSCTR_CBCR_ADDR,m,v,HWIO_GCC_QDSS_TSCTR_CBCR_IN) +#define HWIO_GCC_QDSS_TSCTR_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QDSS_TSCTR_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QDSS_TSCTR_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QDSS_TSCTR_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QDSS_TSCTR_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QDSS_TSCTR_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QDSS_TSCTR_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QDSS_TSCTR_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QDSS_TSCTR_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_QDSS_TSCTR_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_QDSS_TSCTR_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QDSS_TSCTR_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QDSS_TSCTR_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QDSS_TSCTR_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_QDSS_TSCTR_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_QDSS_TSCTR_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_QDSS_TSCTR_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_TSCTR_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QDSS_TSCTR_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_QDSS_TSCTR_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_QDSS_TSCTR_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_TSCTR_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QDSS_TRIG_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006020) +#define HWIO_GCC_QDSS_TRIG_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00006020) +#define HWIO_GCC_QDSS_TRIG_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00006020) +#define HWIO_GCC_QDSS_TRIG_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_QDSS_TRIG_CBCR_ATTR 0x3 +#define HWIO_GCC_QDSS_TRIG_CBCR_IN \ + in_dword_masked(HWIO_GCC_QDSS_TRIG_CBCR_ADDR, HWIO_GCC_QDSS_TRIG_CBCR_RMSK) +#define HWIO_GCC_QDSS_TRIG_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QDSS_TRIG_CBCR_ADDR, m) +#define HWIO_GCC_QDSS_TRIG_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QDSS_TRIG_CBCR_ADDR,v) +#define HWIO_GCC_QDSS_TRIG_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QDSS_TRIG_CBCR_ADDR,m,v,HWIO_GCC_QDSS_TRIG_CBCR_IN) +#define HWIO_GCC_QDSS_TRIG_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QDSS_TRIG_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QDSS_TRIG_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QDSS_TRIG_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QDSS_TRIG_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QDSS_TRIG_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QDSS_TRIG_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QDSS_TRIG_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QDSS_TRIG_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_QDSS_TRIG_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_QDSS_TRIG_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_QDSS_TRIG_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_QDSS_TRIG_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QDSS_TRIG_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QDSS_TRIG_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QDSS_TRIG_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_QDSS_TRIG_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_QDSS_TRIG_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_QDSS_TRIG_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_TRIG_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QDSS_TRIG_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_QDSS_TRIG_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_QDSS_TRIG_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_TRIG_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QDSS_DAP_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006024) +#define HWIO_GCC_QDSS_DAP_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00006024) +#define HWIO_GCC_QDSS_DAP_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00006024) +#define HWIO_GCC_QDSS_DAP_CBCR_RMSK 0x81c0000f +#define HWIO_GCC_QDSS_DAP_CBCR_ATTR 0x3 +#define HWIO_GCC_QDSS_DAP_CBCR_IN \ + in_dword_masked(HWIO_GCC_QDSS_DAP_CBCR_ADDR, HWIO_GCC_QDSS_DAP_CBCR_RMSK) +#define HWIO_GCC_QDSS_DAP_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QDSS_DAP_CBCR_ADDR, m) +#define HWIO_GCC_QDSS_DAP_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QDSS_DAP_CBCR_ADDR,v) +#define HWIO_GCC_QDSS_DAP_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QDSS_DAP_CBCR_ADDR,m,v,HWIO_GCC_QDSS_DAP_CBCR_IN) +#define HWIO_GCC_QDSS_DAP_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QDSS_DAP_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QDSS_DAP_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QDSS_DAP_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QDSS_DAP_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QDSS_DAP_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QDSS_DAP_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QDSS_DAP_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QDSS_DAP_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_QDSS_DAP_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_QDSS_DAP_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QDSS_DAP_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QDSS_DAP_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QDSS_DAP_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_QDSS_DAP_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_QDSS_DAP_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_QDSS_DAP_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_DAP_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QDSS_DAP_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_QDSS_DAP_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_QDSS_DAP_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_DAP_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_APB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006028) +#define HWIO_GCC_APB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00006028) +#define HWIO_GCC_APB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00006028) +#define HWIO_GCC_APB_CBCR_RMSK 0x81c0000f +#define HWIO_GCC_APB_CBCR_ATTR 0x3 +#define HWIO_GCC_APB_CBCR_IN \ + in_dword_masked(HWIO_GCC_APB_CBCR_ADDR, HWIO_GCC_APB_CBCR_RMSK) +#define HWIO_GCC_APB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_APB_CBCR_ADDR, m) +#define HWIO_GCC_APB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_APB_CBCR_ADDR,v) +#define HWIO_GCC_APB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_APB_CBCR_ADDR,m,v,HWIO_GCC_APB_CBCR_IN) +#define HWIO_GCC_APB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_APB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_APB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_APB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_APB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_APB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_APB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_APB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_APB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_APB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_APB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_APB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_APB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_APB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_APB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_APB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_APB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_APB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_APB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_APB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_APB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QDSS_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000602c) +#define HWIO_GCC_QDSS_XO_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000602c) +#define HWIO_GCC_QDSS_XO_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000602c) +#define HWIO_GCC_QDSS_XO_CBCR_RMSK 0x81c0000f +#define HWIO_GCC_QDSS_XO_CBCR_ATTR 0x3 +#define HWIO_GCC_QDSS_XO_CBCR_IN \ + in_dword_masked(HWIO_GCC_QDSS_XO_CBCR_ADDR, HWIO_GCC_QDSS_XO_CBCR_RMSK) +#define HWIO_GCC_QDSS_XO_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QDSS_XO_CBCR_ADDR, m) +#define HWIO_GCC_QDSS_XO_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QDSS_XO_CBCR_ADDR,v) +#define HWIO_GCC_QDSS_XO_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QDSS_XO_CBCR_ADDR,m,v,HWIO_GCC_QDSS_XO_CBCR_IN) +#define HWIO_GCC_QDSS_XO_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QDSS_XO_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QDSS_XO_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QDSS_XO_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QDSS_XO_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QDSS_XO_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QDSS_XO_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QDSS_XO_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QDSS_XO_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_QDSS_XO_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_QDSS_XO_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QDSS_XO_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QDSS_XO_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QDSS_XO_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_QDSS_XO_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_QDSS_XO_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_QDSS_XO_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_XO_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QDSS_XO_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_QDSS_XO_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_QDSS_XO_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_XO_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000604c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000604c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000604c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006050) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00006050) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00006050) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006054) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00006054) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00006054) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006058) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00006058) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00006058) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000605c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000605c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000605c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006060) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00006060) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00006060) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006064) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00006064) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00006064) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006068) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00006068) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00006068) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000606c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000606c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000606c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006070) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00006070) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00006070) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006074) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00006074) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00006074) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006078) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00006078) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00006078) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000607c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000607c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000607c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006080) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00006080) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00006080) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006084) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00006084) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00006084) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006088) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00006088) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00006088) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QDSS_STM_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006030) +#define HWIO_GCC_QDSS_STM_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00006030) +#define HWIO_GCC_QDSS_STM_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00006030) +#define HWIO_GCC_QDSS_STM_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_QDSS_STM_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_QDSS_STM_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_QDSS_STM_CMD_RCGR_ADDR, HWIO_GCC_QDSS_STM_CMD_RCGR_RMSK) +#define HWIO_GCC_QDSS_STM_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QDSS_STM_CMD_RCGR_ADDR, m) +#define HWIO_GCC_QDSS_STM_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QDSS_STM_CMD_RCGR_ADDR,v) +#define HWIO_GCC_QDSS_STM_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QDSS_STM_CMD_RCGR_ADDR,m,v,HWIO_GCC_QDSS_STM_CMD_RCGR_IN) +#define HWIO_GCC_QDSS_STM_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_QDSS_STM_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_QDSS_STM_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_QDSS_STM_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_QDSS_STM_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_QDSS_STM_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_QDSS_STM_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_STM_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_QDSS_STM_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_QDSS_STM_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_QDSS_STM_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_STM_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QDSS_STM_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006034) +#define HWIO_GCC_QDSS_STM_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00006034) +#define HWIO_GCC_QDSS_STM_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00006034) +#define HWIO_GCC_QDSS_STM_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_QDSS_STM_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_QDSS_STM_CFG_RCGR_ADDR, HWIO_GCC_QDSS_STM_CFG_RCGR_RMSK) +#define HWIO_GCC_QDSS_STM_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QDSS_STM_CFG_RCGR_ADDR, m) +#define HWIO_GCC_QDSS_STM_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QDSS_STM_CFG_RCGR_ADDR,v) +#define HWIO_GCC_QDSS_STM_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QDSS_STM_CFG_RCGR_ADDR,m,v,HWIO_GCC_QDSS_STM_CFG_RCGR_IN) +#define HWIO_GCC_QDSS_STM_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006178) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00006178) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00006178) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000617c) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000617c) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000617c) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006180) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00006180) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00006180) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006184) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00006184) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00006184) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006188) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00006188) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00006188) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000618c) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000618c) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000618c) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006190) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00006190) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00006190) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006194) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00006194) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00006194) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006198) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00006198) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00006198) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000619c) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000619c) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000619c) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000061a0) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000061a0) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000061a0) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000061a4) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000061a4) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000061a4) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000061a8) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000061a8) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000061a8) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000061ac) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000061ac) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000061ac) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000061b0) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000061b0) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000061b0) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000061b4) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000061b4) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000061b4) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000615c) +#define HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000615c) +#define HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000615c) +#define HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_ADDR, HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_RMSK) +#define HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_ADDR, m) +#define HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_ADDR,v) +#define HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_ADDR,m,v,HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_IN) +#define HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006160) +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00006160) +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00006160) +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_ADDR, HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_RMSK) +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_ADDR, m) +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_ADDR,v) +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_ADDR,m,v,HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_IN) +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006288) +#define HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00006288) +#define HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00006288) +#define HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_ADDR, HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_RMSK) +#define HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_ADDR, m) +#define HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_ADDR,v) +#define HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_ADDR,m,v,HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_IN) +#define HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000628c) +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000628c) +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000628c) +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_ADDR, HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_RMSK) +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_ADDR, m) +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_ADDR,v) +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_ADDR,m,v,HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_IN) +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000062bc) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000062bc) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000062bc) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000062c0) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000062c0) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000062c0) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000062c4) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000062c4) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000062c4) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000062c8) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000062c8) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000062c8) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000062cc) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000062cc) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000062cc) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000062d0) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000062d0) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000062d0) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000062d4) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000062d4) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000062d4) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000062d8) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000062d8) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000062d8) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000062dc) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000062dc) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000062dc) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000062e0) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000062e0) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000062e0) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000062e4) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000062e4) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000062e4) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000062e8) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000062e8) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000062e8) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000062ec) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000062ec) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000062ec) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000062f0) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000062f0) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000062f0) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000062f4) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000062f4) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000062f4) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000062f8) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000062f8) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000062f8) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QDSS_TRIG_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000062a0) +#define HWIO_GCC_QDSS_TRIG_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000062a0) +#define HWIO_GCC_QDSS_TRIG_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000062a0) +#define HWIO_GCC_QDSS_TRIG_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_QDSS_TRIG_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_QDSS_TRIG_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_QDSS_TRIG_CMD_RCGR_ADDR, HWIO_GCC_QDSS_TRIG_CMD_RCGR_RMSK) +#define HWIO_GCC_QDSS_TRIG_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QDSS_TRIG_CMD_RCGR_ADDR, m) +#define HWIO_GCC_QDSS_TRIG_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QDSS_TRIG_CMD_RCGR_ADDR,v) +#define HWIO_GCC_QDSS_TRIG_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QDSS_TRIG_CMD_RCGR_ADDR,m,v,HWIO_GCC_QDSS_TRIG_CMD_RCGR_IN) +#define HWIO_GCC_QDSS_TRIG_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_QDSS_TRIG_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_QDSS_TRIG_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_QDSS_TRIG_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_QDSS_TRIG_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_QDSS_TRIG_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_QDSS_TRIG_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_TRIG_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_QDSS_TRIG_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_QDSS_TRIG_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_QDSS_TRIG_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_TRIG_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000062a4) +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000062a4) +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000062a4) +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_QDSS_TRIG_CFG_RCGR_ADDR, HWIO_GCC_QDSS_TRIG_CFG_RCGR_RMSK) +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QDSS_TRIG_CFG_RCGR_ADDR, m) +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QDSS_TRIG_CFG_RCGR_ADDR,v) +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QDSS_TRIG_CFG_RCGR_ADDR,m,v,HWIO_GCC_QDSS_TRIG_CFG_RCGR_IN) +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000063e8) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000063e8) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000063e8) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF0_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF0_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF0_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF0_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000063ec) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000063ec) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000063ec) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF1_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF1_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF1_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF1_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000063f0) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000063f0) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000063f0) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF2_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF2_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF2_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF2_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000063f4) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000063f4) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000063f4) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF3_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF3_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF3_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF3_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000063f8) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000063f8) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000063f8) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF4_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF4_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF4_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF4_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000063fc) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000063fc) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000063fc) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF5_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF5_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF5_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF5_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006400) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00006400) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00006400) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF6_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF6_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF6_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF6_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006404) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00006404) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00006404) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF7_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF7_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF7_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF7_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF8_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006408) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF8_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00006408) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF8_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00006408) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF8_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF8_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF8_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF8_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF8_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF8_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF8_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF8_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF8_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF8_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF8_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF8_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF8_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF8_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF8_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF8_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF8_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF8_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF8_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF8_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF8_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF8_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF8_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF8_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF8_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF8_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF8_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF8_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF8_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF8_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF8_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF8_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF8_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF8_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF8_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF8_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF8_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF8_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF8_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF8_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF8_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF8_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF8_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF8_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF8_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF8_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF8_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF8_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF8_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF8_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF8_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF8_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF8_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF8_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF8_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF9_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000640c) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF9_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000640c) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF9_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000640c) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF9_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF9_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF9_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF9_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF9_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF9_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF9_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF9_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF9_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF9_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF9_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF9_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF9_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF9_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF9_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF9_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF9_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF9_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF9_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF9_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF9_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF9_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF9_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF9_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF9_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF9_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF9_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF9_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF9_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF9_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF9_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF9_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF9_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF9_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF9_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF9_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF9_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF9_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF9_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF9_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF9_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF9_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF9_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF9_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF9_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF9_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF9_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF9_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF9_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF9_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF9_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF9_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF9_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF9_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF9_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF10_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006410) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF10_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00006410) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF10_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00006410) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF10_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF10_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF10_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF10_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF10_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF10_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF10_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF10_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF10_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF10_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF10_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF10_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF10_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF10_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF10_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF10_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF10_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF10_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF10_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF10_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF10_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF10_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF10_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF10_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF10_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF10_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF10_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF10_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF10_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF10_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF10_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF10_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF10_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF10_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF10_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF10_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF10_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF10_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF10_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF10_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF10_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF10_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF10_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF10_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF10_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF10_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF10_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF10_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF10_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF10_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF10_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF10_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF10_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF10_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF10_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF11_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006414) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF11_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00006414) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF11_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00006414) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF11_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF11_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF11_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF11_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF11_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF11_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF11_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF11_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF11_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF11_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF11_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF11_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF11_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF11_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF11_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF11_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF11_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF11_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF11_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF11_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF11_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF11_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF11_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF11_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF11_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF11_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF11_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF11_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF11_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF11_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF11_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF11_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF11_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF11_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF11_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF11_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF11_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF11_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF11_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF11_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF11_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF11_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF11_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF11_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF11_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF11_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF11_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF11_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF11_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF11_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF11_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF11_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF11_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF11_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF11_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF12_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006418) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF12_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00006418) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF12_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00006418) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF12_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF12_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF12_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF12_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF12_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF12_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF12_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF12_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF12_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF12_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF12_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF12_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF12_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF12_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF12_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF12_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF12_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF12_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF12_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF12_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF12_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF12_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF12_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF12_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF12_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF12_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF12_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF12_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF12_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF12_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF12_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF12_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF12_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF12_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF12_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF12_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF12_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF12_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF12_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF12_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF12_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF12_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF12_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF12_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF12_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF12_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF12_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF12_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF12_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF12_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF12_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF12_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF12_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF12_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF12_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF13_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000641c) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF13_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000641c) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF13_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000641c) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF13_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF13_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF13_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF13_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF13_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF13_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF13_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF13_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF13_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF13_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF13_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF13_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF13_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF13_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF13_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF13_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF13_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF13_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF13_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF13_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF13_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF13_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF13_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF13_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF13_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF13_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF13_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF13_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF13_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF13_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF13_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF13_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF13_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF13_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF13_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF13_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF13_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF13_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF13_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF13_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF13_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF13_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF13_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF13_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF13_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF13_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF13_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF13_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF13_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF13_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF13_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF13_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF13_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF13_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF13_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF14_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006420) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF14_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00006420) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF14_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00006420) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF14_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF14_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF14_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF14_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF14_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF14_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF14_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF14_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF14_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF14_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF14_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF14_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF14_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF14_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF14_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF14_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF14_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF14_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF14_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF14_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF14_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF14_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF14_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF14_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF14_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF14_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF14_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF14_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF14_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF14_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF14_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF14_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF14_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF14_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF14_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF14_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF14_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF14_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF14_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF14_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF14_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF14_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF14_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF14_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF14_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF14_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF14_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF14_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF14_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF14_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF14_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF14_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF14_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF14_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF14_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF15_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006424) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF15_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00006424) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF15_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00006424) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF15_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF15_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF15_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF15_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF15_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF15_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF15_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF15_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF15_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF15_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF15_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF15_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF15_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF15_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF15_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF15_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF15_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF15_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF15_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF15_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF15_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF15_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF15_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF15_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF15_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF15_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF15_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF15_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF15_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF15_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF15_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF15_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF15_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF15_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF15_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF15_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF15_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF15_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF15_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF15_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF15_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF15_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF15_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF15_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF15_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF15_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF15_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF15_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF15_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF15_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF15_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF15_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF15_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF15_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_AT_PERF15_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QDSS_AT_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000063cc) +#define HWIO_GCC_QDSS_AT_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000063cc) +#define HWIO_GCC_QDSS_AT_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000063cc) +#define HWIO_GCC_QDSS_AT_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_QDSS_AT_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_QDSS_AT_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_QDSS_AT_CMD_RCGR_ADDR, HWIO_GCC_QDSS_AT_CMD_RCGR_RMSK) +#define HWIO_GCC_QDSS_AT_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QDSS_AT_CMD_RCGR_ADDR, m) +#define HWIO_GCC_QDSS_AT_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QDSS_AT_CMD_RCGR_ADDR,v) +#define HWIO_GCC_QDSS_AT_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QDSS_AT_CMD_RCGR_ADDR,m,v,HWIO_GCC_QDSS_AT_CMD_RCGR_IN) +#define HWIO_GCC_QDSS_AT_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_QDSS_AT_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_QDSS_AT_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_QDSS_AT_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_QDSS_AT_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_QDSS_AT_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_QDSS_AT_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_AT_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_QDSS_AT_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_QDSS_AT_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_QDSS_AT_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_AT_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QDSS_AT_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000063d0) +#define HWIO_GCC_QDSS_AT_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000063d0) +#define HWIO_GCC_QDSS_AT_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000063d0) +#define HWIO_GCC_QDSS_AT_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_QDSS_AT_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_QDSS_AT_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_QDSS_AT_CFG_RCGR_ADDR, HWIO_GCC_QDSS_AT_CFG_RCGR_RMSK) +#define HWIO_GCC_QDSS_AT_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QDSS_AT_CFG_RCGR_ADDR, m) +#define HWIO_GCC_QDSS_AT_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QDSS_AT_CFG_RCGR_ADDR,v) +#define HWIO_GCC_QDSS_AT_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QDSS_AT_CFG_RCGR_ADDR,m,v,HWIO_GCC_QDSS_AT_CFG_RCGR_IN) +#define HWIO_GCC_QDSS_AT_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_QDSS_AT_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_QDSS_AT_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_AT_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QDSS_AT_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_QDSS_AT_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_QDSS_AT_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_QDSS_AT_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_QDSS_AT_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QDSS_AT_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QDSS_AT_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QDSS_AT_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QDSS_AT_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QDSS_AT_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QDSS_AT_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QDSS_AT_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QDSS_AT_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QDSS_AT_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QDSS_AT_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QDSS_AT_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QDSS_AT_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QDSS_AT_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QDSS_AT_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QDSS_AT_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QDSS_AT_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QDSS_AT_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QDSS_AT_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QDSS_AT_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QDSS_AT_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QDSS_AT_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QDSS_AT_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QDSS_AT_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QDSS_AT_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QDSS_AT_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QDSS_AT_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QDSS_AT_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QDSS_AT_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QDSS_AT_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QDSS_AT_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QDSS_AT_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QDSS_AT_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QDSS_AT_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QDSS_AT_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QDSS_AT_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QDSS_AT_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QDSS_AT_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QDSS_AT_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QDSS_AT_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QDSS_AT_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QDSS_AT_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QDSS_AT_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QDSS_AT_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_USB30_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00007000) +#define HWIO_GCC_USB30_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00007000) +#define HWIO_GCC_USB30_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00007000) +#define HWIO_GCC_USB30_BCR_RMSK 0x1 +#define HWIO_GCC_USB30_BCR_ATTR 0x3 +#define HWIO_GCC_USB30_BCR_IN \ + in_dword_masked(HWIO_GCC_USB30_BCR_ADDR, HWIO_GCC_USB30_BCR_RMSK) +#define HWIO_GCC_USB30_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_USB30_BCR_ADDR, m) +#define HWIO_GCC_USB30_BCR_OUT(v) \ + out_dword(HWIO_GCC_USB30_BCR_ADDR,v) +#define HWIO_GCC_USB30_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB30_BCR_ADDR,m,v,HWIO_GCC_USB30_BCR_IN) +#define HWIO_GCC_USB30_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_USB30_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_USB30_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_USB30_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00007004) +#define HWIO_GCC_USB30_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00007004) +#define HWIO_GCC_USB30_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00007004) +#define HWIO_GCC_USB30_GDSCR_RMSK 0xf8ffffff +#define HWIO_GCC_USB30_GDSCR_ATTR 0x3 +#define HWIO_GCC_USB30_GDSCR_IN \ + in_dword_masked(HWIO_GCC_USB30_GDSCR_ADDR, HWIO_GCC_USB30_GDSCR_RMSK) +#define HWIO_GCC_USB30_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_USB30_GDSCR_ADDR, m) +#define HWIO_GCC_USB30_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_USB30_GDSCR_ADDR,v) +#define HWIO_GCC_USB30_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB30_GDSCR_ADDR,m,v,HWIO_GCC_USB30_GDSCR_IN) +#define HWIO_GCC_USB30_GDSCR_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_USB30_GDSCR_PWR_ON_SHFT 0x1f +#define HWIO_GCC_USB30_GDSCR_GDSC_STATE_BMSK 0x78000000 +#define HWIO_GCC_USB30_GDSCR_GDSC_STATE_SHFT 0x1b +#define HWIO_GCC_USB30_GDSCR_EN_REST_WAIT_BMSK 0xf00000 +#define HWIO_GCC_USB30_GDSCR_EN_REST_WAIT_SHFT 0x14 +#define HWIO_GCC_USB30_GDSCR_EN_FEW_WAIT_BMSK 0xf0000 +#define HWIO_GCC_USB30_GDSCR_EN_FEW_WAIT_SHFT 0x10 +#define HWIO_GCC_USB30_GDSCR_CLK_DIS_WAIT_BMSK 0xf000 +#define HWIO_GCC_USB30_GDSCR_CLK_DIS_WAIT_SHFT 0xc +#define HWIO_GCC_USB30_GDSCR_RETAIN_FF_ENABLE_BMSK 0x800 +#define HWIO_GCC_USB30_GDSCR_RETAIN_FF_ENABLE_SHFT 0xb +#define HWIO_GCC_USB30_GDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_GDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB30_GDSCR_RESTORE_BMSK 0x400 +#define HWIO_GCC_USB30_GDSCR_RESTORE_SHFT 0xa +#define HWIO_GCC_USB30_GDSCR_RESTORE_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_GDSCR_RESTORE_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB30_GDSCR_SAVE_BMSK 0x200 +#define HWIO_GCC_USB30_GDSCR_SAVE_SHFT 0x9 +#define HWIO_GCC_USB30_GDSCR_SAVE_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_GDSCR_SAVE_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB30_GDSCR_RETAIN_BMSK 0x100 +#define HWIO_GCC_USB30_GDSCR_RETAIN_SHFT 0x8 +#define HWIO_GCC_USB30_GDSCR_RETAIN_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_GDSCR_RETAIN_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB30_GDSCR_EN_REST_BMSK 0x80 +#define HWIO_GCC_USB30_GDSCR_EN_REST_SHFT 0x7 +#define HWIO_GCC_USB30_GDSCR_EN_REST_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_GDSCR_EN_REST_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB30_GDSCR_EN_FEW_BMSK 0x40 +#define HWIO_GCC_USB30_GDSCR_EN_FEW_SHFT 0x6 +#define HWIO_GCC_USB30_GDSCR_EN_FEW_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_GDSCR_EN_FEW_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB30_GDSCR_CLAMP_IO_BMSK 0x20 +#define HWIO_GCC_USB30_GDSCR_CLAMP_IO_SHFT 0x5 +#define HWIO_GCC_USB30_GDSCR_CLAMP_IO_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_GDSCR_CLAMP_IO_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB30_GDSCR_CLK_DISABLE_BMSK 0x10 +#define HWIO_GCC_USB30_GDSCR_CLK_DISABLE_SHFT 0x4 +#define HWIO_GCC_USB30_GDSCR_CLK_DISABLE_CLK_NOT_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_GDSCR_CLK_DISABLE_CLK_IS_DISABLE_FVAL 0x1 +#define HWIO_GCC_USB30_GDSCR_PD_ARES_BMSK 0x8 +#define HWIO_GCC_USB30_GDSCR_PD_ARES_SHFT 0x3 +#define HWIO_GCC_USB30_GDSCR_PD_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_USB30_GDSCR_PD_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_USB30_GDSCR_SW_OVERRIDE_BMSK 0x4 +#define HWIO_GCC_USB30_GDSCR_SW_OVERRIDE_SHFT 0x2 +#define HWIO_GCC_USB30_GDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_GDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB30_GDSCR_HW_CONTROL_BMSK 0x2 +#define HWIO_GCC_USB30_GDSCR_HW_CONTROL_SHFT 0x1 +#define HWIO_GCC_USB30_GDSCR_HW_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_GDSCR_HW_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB30_GDSCR_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_USB30_GDSCR_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_USB30_GDSCR_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_GDSCR_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_USB30_CFG_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00007008) +#define HWIO_GCC_USB30_CFG_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00007008) +#define HWIO_GCC_USB30_CFG_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00007008) +#define HWIO_GCC_USB30_CFG_GDSCR_RMSK 0x3ffffff +#define HWIO_GCC_USB30_CFG_GDSCR_ATTR 0x3 +#define HWIO_GCC_USB30_CFG_GDSCR_IN \ + in_dword_masked(HWIO_GCC_USB30_CFG_GDSCR_ADDR, HWIO_GCC_USB30_CFG_GDSCR_RMSK) +#define HWIO_GCC_USB30_CFG_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_USB30_CFG_GDSCR_ADDR, m) +#define HWIO_GCC_USB30_CFG_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_USB30_CFG_GDSCR_ADDR,v) +#define HWIO_GCC_USB30_CFG_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB30_CFG_GDSCR_ADDR,m,v,HWIO_GCC_USB30_CFG_GDSCR_IN) +#define HWIO_GCC_USB30_CFG_GDSCR_GDSC_PWR_DWN_START_BMSK 0x2000000 +#define HWIO_GCC_USB30_CFG_GDSCR_GDSC_PWR_DWN_START_SHFT 0x19 +#define HWIO_GCC_USB30_CFG_GDSCR_GDSC_PWR_UP_START_BMSK 0x1000000 +#define HWIO_GCC_USB30_CFG_GDSCR_GDSC_PWR_UP_START_SHFT 0x18 +#define HWIO_GCC_USB30_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_BMSK 0xf00000 +#define HWIO_GCC_USB30_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_SHFT 0x14 +#define HWIO_GCC_USB30_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_BMSK 0x80000 +#define HWIO_GCC_USB30_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_SHFT 0x13 +#define HWIO_GCC_USB30_CFG_GDSCR_GDSC_ENR_ACK_STATUS_BMSK 0x40000 +#define HWIO_GCC_USB30_CFG_GDSCR_GDSC_ENR_ACK_STATUS_SHFT 0x12 +#define HWIO_GCC_USB30_CFG_GDSCR_GDSC_ENF_ACK_STATUS_BMSK 0x20000 +#define HWIO_GCC_USB30_CFG_GDSCR_GDSC_ENF_ACK_STATUS_SHFT 0x11 +#define HWIO_GCC_USB30_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_BMSK 0x10000 +#define HWIO_GCC_USB30_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_SHFT 0x10 +#define HWIO_GCC_USB30_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_BMSK 0x8000 +#define HWIO_GCC_USB30_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_SHFT 0xf +#define HWIO_GCC_USB30_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_BMSK 0x7800 +#define HWIO_GCC_USB30_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_SHFT 0xb +#define HWIO_GCC_USB30_CFG_GDSCR_GDSC_HANDSHAKE_DIS_BMSK 0x400 +#define HWIO_GCC_USB30_CFG_GDSCR_GDSC_HANDSHAKE_DIS_SHFT 0xa +#define HWIO_GCC_USB30_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_BMSK 0x200 +#define HWIO_GCC_USB30_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_SHFT 0x9 +#define HWIO_GCC_USB30_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_BMSK 0x100 +#define HWIO_GCC_USB30_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_SHFT 0x8 +#define HWIO_GCC_USB30_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_BMSK 0x80 +#define HWIO_GCC_USB30_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_SHFT 0x7 +#define HWIO_GCC_USB30_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_BMSK 0x60 +#define HWIO_GCC_USB30_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_SHFT 0x5 +#define HWIO_GCC_USB30_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_BMSK 0x10 +#define HWIO_GCC_USB30_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_SHFT 0x4 +#define HWIO_GCC_USB30_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_BMSK 0x8 +#define HWIO_GCC_USB30_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_SHFT 0x3 +#define HWIO_GCC_USB30_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_BMSK 0x4 +#define HWIO_GCC_USB30_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_SHFT 0x2 +#define HWIO_GCC_USB30_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_BMSK 0x2 +#define HWIO_GCC_USB30_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_SHFT 0x1 +#define HWIO_GCC_USB30_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_USB30_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_SHFT 0x0 + +#define HWIO_GCC_USB30_CFG2_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000700c) +#define HWIO_GCC_USB30_CFG2_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000700c) +#define HWIO_GCC_USB30_CFG2_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000700c) +#define HWIO_GCC_USB30_CFG2_GDSCR_RMSK 0x7ffff +#define HWIO_GCC_USB30_CFG2_GDSCR_ATTR 0x3 +#define HWIO_GCC_USB30_CFG2_GDSCR_IN \ + in_dword_masked(HWIO_GCC_USB30_CFG2_GDSCR_ADDR, HWIO_GCC_USB30_CFG2_GDSCR_RMSK) +#define HWIO_GCC_USB30_CFG2_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_USB30_CFG2_GDSCR_ADDR, m) +#define HWIO_GCC_USB30_CFG2_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_USB30_CFG2_GDSCR_ADDR,v) +#define HWIO_GCC_USB30_CFG2_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB30_CFG2_GDSCR_ADDR,m,v,HWIO_GCC_USB30_CFG2_GDSCR_IN) +#define HWIO_GCC_USB30_CFG2_GDSCR_GDSC_MEM_PWRUP_ACK_OVERRIDE_BMSK 0x40000 +#define HWIO_GCC_USB30_CFG2_GDSCR_GDSC_MEM_PWRUP_ACK_OVERRIDE_SHFT 0x12 +#define HWIO_GCC_USB30_CFG2_GDSCR_GDSC_PWRDWN_ENABLE_ACK_OVERRIDE_BMSK 0x20000 +#define HWIO_GCC_USB30_CFG2_GDSCR_GDSC_PWRDWN_ENABLE_ACK_OVERRIDE_SHFT 0x11 +#define HWIO_GCC_USB30_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_BMSK 0x10000 +#define HWIO_GCC_USB30_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_SHFT 0x10 +#define HWIO_GCC_USB30_CFG2_GDSCR_DLY_MEM_PWR_UP_BMSK 0xf000 +#define HWIO_GCC_USB30_CFG2_GDSCR_DLY_MEM_PWR_UP_SHFT 0xc +#define HWIO_GCC_USB30_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_BMSK 0xf00 +#define HWIO_GCC_USB30_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_SHFT 0x8 +#define HWIO_GCC_USB30_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_BMSK 0xf0 +#define HWIO_GCC_USB30_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_SHFT 0x4 +#define HWIO_GCC_USB30_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_BMSK 0xf +#define HWIO_GCC_USB30_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_SHFT 0x0 + +#define HWIO_GCC_USB30_CFG3_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00007010) +#define HWIO_GCC_USB30_CFG3_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00007010) +#define HWIO_GCC_USB30_CFG3_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00007010) +#define HWIO_GCC_USB30_CFG3_GDSCR_RMSK 0x7ffffff +#define HWIO_GCC_USB30_CFG3_GDSCR_ATTR 0x3 +#define HWIO_GCC_USB30_CFG3_GDSCR_IN \ + in_dword_masked(HWIO_GCC_USB30_CFG3_GDSCR_ADDR, HWIO_GCC_USB30_CFG3_GDSCR_RMSK) +#define HWIO_GCC_USB30_CFG3_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_USB30_CFG3_GDSCR_ADDR, m) +#define HWIO_GCC_USB30_CFG3_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_USB30_CFG3_GDSCR_ADDR,v) +#define HWIO_GCC_USB30_CFG3_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB30_CFG3_GDSCR_ADDR,m,v,HWIO_GCC_USB30_CFG3_GDSCR_IN) +#define HWIO_GCC_USB30_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_STATUS_BMSK 0x4000000 +#define HWIO_GCC_USB30_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_STATUS_SHFT 0x1a +#define HWIO_GCC_USB30_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_BMSK 0x2000000 +#define HWIO_GCC_USB30_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_SHFT 0x19 +#define HWIO_GCC_USB30_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB30_CFG3_GDSCR_DLY_ACCU_RED_SHIFTER_DONE_BMSK 0x1e00000 +#define HWIO_GCC_USB30_CFG3_GDSCR_DLY_ACCU_RED_SHIFTER_DONE_SHFT 0x15 +#define HWIO_GCC_USB30_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_BMSK 0x100000 +#define HWIO_GCC_USB30_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_SHFT 0x14 +#define HWIO_GCC_USB30_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB30_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_BMSK 0x80000 +#define HWIO_GCC_USB30_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_SHFT 0x13 +#define HWIO_GCC_USB30_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB30_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_BMSK 0x40000 +#define HWIO_GCC_USB30_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_SHFT 0x12 +#define HWIO_GCC_USB30_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB30_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_BMSK 0x20000 +#define HWIO_GCC_USB30_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_SHFT 0x11 +#define HWIO_GCC_USB30_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB30_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_BMSK 0x10000 +#define HWIO_GCC_USB30_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_SHFT 0x10 +#define HWIO_GCC_USB30_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB30_CFG3_GDSCR_GDSC_SPARE_CTRL_IN_BMSK 0xff00 +#define HWIO_GCC_USB30_CFG3_GDSCR_GDSC_SPARE_CTRL_IN_SHFT 0x8 +#define HWIO_GCC_USB30_CFG3_GDSCR_GDSC_SPARE_CTRL_OUT_BMSK 0xff +#define HWIO_GCC_USB30_CFG3_GDSCR_GDSC_SPARE_CTRL_OUT_SHFT 0x0 + +#define HWIO_GCC_USB30_CFG4_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00007014) +#define HWIO_GCC_USB30_CFG4_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00007014) +#define HWIO_GCC_USB30_CFG4_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00007014) +#define HWIO_GCC_USB30_CFG4_GDSCR_RMSK 0xffffff +#define HWIO_GCC_USB30_CFG4_GDSCR_ATTR 0x3 +#define HWIO_GCC_USB30_CFG4_GDSCR_IN \ + in_dword_masked(HWIO_GCC_USB30_CFG4_GDSCR_ADDR, HWIO_GCC_USB30_CFG4_GDSCR_RMSK) +#define HWIO_GCC_USB30_CFG4_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_USB30_CFG4_GDSCR_ADDR, m) +#define HWIO_GCC_USB30_CFG4_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_USB30_CFG4_GDSCR_ADDR,v) +#define HWIO_GCC_USB30_CFG4_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB30_CFG4_GDSCR_ADDR,m,v,HWIO_GCC_USB30_CFG4_GDSCR_IN) +#define HWIO_GCC_USB30_CFG4_GDSCR_DLY_UNCLAMPIO_BMSK 0xf00000 +#define HWIO_GCC_USB30_CFG4_GDSCR_DLY_UNCLAMPIO_SHFT 0x14 +#define HWIO_GCC_USB30_CFG4_GDSCR_DLY_RESTOREFF_BMSK 0xf0000 +#define HWIO_GCC_USB30_CFG4_GDSCR_DLY_RESTOREFF_SHFT 0x10 +#define HWIO_GCC_USB30_CFG4_GDSCR_DLY_NORETAINFF_BMSK 0xf000 +#define HWIO_GCC_USB30_CFG4_GDSCR_DLY_NORETAINFF_SHFT 0xc +#define HWIO_GCC_USB30_CFG4_GDSCR_DLY_DEASSERTARES_BMSK 0xf00 +#define HWIO_GCC_USB30_CFG4_GDSCR_DLY_DEASSERTARES_SHFT 0x8 +#define HWIO_GCC_USB30_CFG4_GDSCR_DLY_CLAMPIO_BMSK 0xf0 +#define HWIO_GCC_USB30_CFG4_GDSCR_DLY_CLAMPIO_SHFT 0x4 +#define HWIO_GCC_USB30_CFG4_GDSCR_DLY_RETAINFF_BMSK 0xf +#define HWIO_GCC_USB30_CFG4_GDSCR_DLY_RETAINFF_SHFT 0x0 + +#define HWIO_GCC_USB30_MASTER_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00007018) +#define HWIO_GCC_USB30_MASTER_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00007018) +#define HWIO_GCC_USB30_MASTER_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00007018) +#define HWIO_GCC_USB30_MASTER_CBCR_RMSK 0x81c07ff5 +#define HWIO_GCC_USB30_MASTER_CBCR_ATTR 0x3 +#define HWIO_GCC_USB30_MASTER_CBCR_IN \ + in_dword_masked(HWIO_GCC_USB30_MASTER_CBCR_ADDR, HWIO_GCC_USB30_MASTER_CBCR_RMSK) +#define HWIO_GCC_USB30_MASTER_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_USB30_MASTER_CBCR_ADDR, m) +#define HWIO_GCC_USB30_MASTER_CBCR_OUT(v) \ + out_dword(HWIO_GCC_USB30_MASTER_CBCR_ADDR,v) +#define HWIO_GCC_USB30_MASTER_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB30_MASTER_CBCR_ADDR,m,v,HWIO_GCC_USB30_MASTER_CBCR_IN) +#define HWIO_GCC_USB30_MASTER_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_USB30_MASTER_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_USB30_MASTER_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_USB30_MASTER_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_USB30_MASTER_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_USB30_MASTER_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_USB30_MASTER_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_USB30_MASTER_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_USB30_MASTER_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_USB30_MASTER_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_USB30_MASTER_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_MASTER_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB30_MASTER_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_USB30_MASTER_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_USB30_MASTER_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_MASTER_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB30_MASTER_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_USB30_MASTER_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_USB30_MASTER_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_MASTER_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB30_MASTER_CBCR_WAKEUP_BMSK 0xf00 +#define HWIO_GCC_USB30_MASTER_CBCR_WAKEUP_SHFT 0x8 +#define HWIO_GCC_USB30_MASTER_CBCR_WAKEUP_CLOCK0_FVAL 0x0 +#define HWIO_GCC_USB30_MASTER_CBCR_WAKEUP_CLOCK1_FVAL 0x1 +#define HWIO_GCC_USB30_MASTER_CBCR_WAKEUP_CLOCK2_FVAL 0x2 +#define HWIO_GCC_USB30_MASTER_CBCR_WAKEUP_CLOCK3_FVAL 0x3 +#define HWIO_GCC_USB30_MASTER_CBCR_WAKEUP_CLOCK4_FVAL 0x4 +#define HWIO_GCC_USB30_MASTER_CBCR_WAKEUP_CLOCK5_FVAL 0x5 +#define HWIO_GCC_USB30_MASTER_CBCR_WAKEUP_CLOCK6_FVAL 0x6 +#define HWIO_GCC_USB30_MASTER_CBCR_WAKEUP_CLOCK7_FVAL 0x7 +#define HWIO_GCC_USB30_MASTER_CBCR_WAKEUP_CLOCK8_FVAL 0x8 +#define HWIO_GCC_USB30_MASTER_CBCR_WAKEUP_CLOCK9_FVAL 0x9 +#define HWIO_GCC_USB30_MASTER_CBCR_WAKEUP_CLOCK10_FVAL 0xa +#define HWIO_GCC_USB30_MASTER_CBCR_WAKEUP_CLOCK11_FVAL 0xb +#define HWIO_GCC_USB30_MASTER_CBCR_WAKEUP_CLOCK12_FVAL 0xc +#define HWIO_GCC_USB30_MASTER_CBCR_WAKEUP_CLOCK13_FVAL 0xd +#define HWIO_GCC_USB30_MASTER_CBCR_WAKEUP_CLOCK14_FVAL 0xe +#define HWIO_GCC_USB30_MASTER_CBCR_WAKEUP_CLOCK15_FVAL 0xf +#define HWIO_GCC_USB30_MASTER_CBCR_SLEEP_BMSK 0xf0 +#define HWIO_GCC_USB30_MASTER_CBCR_SLEEP_SHFT 0x4 +#define HWIO_GCC_USB30_MASTER_CBCR_SLEEP_CLOCK0_FVAL 0x0 +#define HWIO_GCC_USB30_MASTER_CBCR_SLEEP_CLOCK1_FVAL 0x1 +#define HWIO_GCC_USB30_MASTER_CBCR_SLEEP_CLOCK2_FVAL 0x2 +#define HWIO_GCC_USB30_MASTER_CBCR_SLEEP_CLOCK3_FVAL 0x3 +#define HWIO_GCC_USB30_MASTER_CBCR_SLEEP_CLOCK4_FVAL 0x4 +#define HWIO_GCC_USB30_MASTER_CBCR_SLEEP_CLOCK5_FVAL 0x5 +#define HWIO_GCC_USB30_MASTER_CBCR_SLEEP_CLOCK6_FVAL 0x6 +#define HWIO_GCC_USB30_MASTER_CBCR_SLEEP_CLOCK7_FVAL 0x7 +#define HWIO_GCC_USB30_MASTER_CBCR_SLEEP_CLOCK8_FVAL 0x8 +#define HWIO_GCC_USB30_MASTER_CBCR_SLEEP_CLOCK9_FVAL 0x9 +#define HWIO_GCC_USB30_MASTER_CBCR_SLEEP_CLOCK10_FVAL 0xa +#define HWIO_GCC_USB30_MASTER_CBCR_SLEEP_CLOCK11_FVAL 0xb +#define HWIO_GCC_USB30_MASTER_CBCR_SLEEP_CLOCK12_FVAL 0xc +#define HWIO_GCC_USB30_MASTER_CBCR_SLEEP_CLOCK13_FVAL 0xd +#define HWIO_GCC_USB30_MASTER_CBCR_SLEEP_CLOCK14_FVAL 0xe +#define HWIO_GCC_USB30_MASTER_CBCR_SLEEP_CLOCK15_FVAL 0xf +#define HWIO_GCC_USB30_MASTER_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_USB30_MASTER_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_USB30_MASTER_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_USB30_MASTER_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_USB30_MASTER_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_USB30_MASTER_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_USB30_MASTER_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_MASTER_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_USB30_MASTER_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000701c) +#define HWIO_GCC_USB30_MASTER_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000701c) +#define HWIO_GCC_USB30_MASTER_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000701c) +#define HWIO_GCC_USB30_MASTER_SREGR_RMSK 0xfffffffe +#define HWIO_GCC_USB30_MASTER_SREGR_ATTR 0x3 +#define HWIO_GCC_USB30_MASTER_SREGR_IN \ + in_dword_masked(HWIO_GCC_USB30_MASTER_SREGR_ADDR, HWIO_GCC_USB30_MASTER_SREGR_RMSK) +#define HWIO_GCC_USB30_MASTER_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_USB30_MASTER_SREGR_ADDR, m) +#define HWIO_GCC_USB30_MASTER_SREGR_OUT(v) \ + out_dword(HWIO_GCC_USB30_MASTER_SREGR_ADDR,v) +#define HWIO_GCC_USB30_MASTER_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB30_MASTER_SREGR_ADDR,m,v,HWIO_GCC_USB30_MASTER_SREGR_IN) +#define HWIO_GCC_USB30_MASTER_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xff000000 +#define HWIO_GCC_USB30_MASTER_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_USB30_MASTER_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xff0000 +#define HWIO_GCC_USB30_MASTER_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_USB30_MASTER_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_USB30_MASTER_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_USB30_MASTER_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_USB30_MASTER_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_USB30_MASTER_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_USB30_MASTER_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_USB30_MASTER_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_USB30_MASTER_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_USB30_MASTER_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_USB30_MASTER_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_USB30_MASTER_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_USB30_MASTER_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_USB30_MASTER_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_USB30_MASTER_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_USB30_MASTER_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_USB30_MASTER_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_USB30_MASTER_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_USB30_MASTER_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_USB30_MASTER_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_USB30_MASTER_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_USB30_MASTER_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_USB30_MASTER_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_USB30_MASTER_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_USB30_MASTER_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_USB30_MASTER_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_USB30_MASTER_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_USB30_MASTER_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_USB30_MASTER_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_USB30_MASTER_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_MASTER_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB30_MASTER_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_USB30_MASTER_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_USB30_MASTER_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_USB30_MASTER_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB30_MASTER_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_USB30_MASTER_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_USB30_MASTER_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_USB30_MASTER_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_USB30_MASTER_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_USB30_MASTER_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_USB30_MASTER_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_USB30_MASTER_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_USB30_MASTER_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_USB30_MASTER_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_USB30_MASTER_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_USB30_MASTER_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_USB30_MASTER_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_USB30_MASTER_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_USB30_MASTER_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_USB30_MASTER_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_USB30_MASTER_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_USB30_MASTER_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_USB30_MASTER_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_MASTER_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_USB30_MSTR_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00007020) +#define HWIO_GCC_USB30_MSTR_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00007020) +#define HWIO_GCC_USB30_MSTR_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00007020) +#define HWIO_GCC_USB30_MSTR_AXI_CBCR_RMSK 0x81d00005 +#define HWIO_GCC_USB30_MSTR_AXI_CBCR_ATTR 0x3 +#define HWIO_GCC_USB30_MSTR_AXI_CBCR_IN \ + in_dword_masked(HWIO_GCC_USB30_MSTR_AXI_CBCR_ADDR, HWIO_GCC_USB30_MSTR_AXI_CBCR_RMSK) +#define HWIO_GCC_USB30_MSTR_AXI_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_USB30_MSTR_AXI_CBCR_ADDR, m) +#define HWIO_GCC_USB30_MSTR_AXI_CBCR_OUT(v) \ + out_dword(HWIO_GCC_USB30_MSTR_AXI_CBCR_ADDR,v) +#define HWIO_GCC_USB30_MSTR_AXI_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB30_MSTR_AXI_CBCR_ADDR,m,v,HWIO_GCC_USB30_MSTR_AXI_CBCR_IN) +#define HWIO_GCC_USB30_MSTR_AXI_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_USB30_MSTR_AXI_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_USB30_MSTR_AXI_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_USB30_MSTR_AXI_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_USB30_MSTR_AXI_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_USB30_MSTR_AXI_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_USB30_MSTR_AXI_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_USB30_MSTR_AXI_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_USB30_MSTR_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_USB30_MSTR_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_USB30_MSTR_AXI_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_USB30_MSTR_AXI_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_USB30_MSTR_AXI_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_USB30_MSTR_AXI_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_USB30_MSTR_AXI_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_USB30_MSTR_AXI_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_USB30_MSTR_AXI_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_MSTR_AXI_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_USB30_SLV_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00007024) +#define HWIO_GCC_USB30_SLV_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00007024) +#define HWIO_GCC_USB30_SLV_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00007024) +#define HWIO_GCC_USB30_SLV_AHB_CBCR_RMSK 0x81d00005 +#define HWIO_GCC_USB30_SLV_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_USB30_SLV_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_USB30_SLV_AHB_CBCR_ADDR, HWIO_GCC_USB30_SLV_AHB_CBCR_RMSK) +#define HWIO_GCC_USB30_SLV_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_USB30_SLV_AHB_CBCR_ADDR, m) +#define HWIO_GCC_USB30_SLV_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_USB30_SLV_AHB_CBCR_ADDR,v) +#define HWIO_GCC_USB30_SLV_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB30_SLV_AHB_CBCR_ADDR,m,v,HWIO_GCC_USB30_SLV_AHB_CBCR_IN) +#define HWIO_GCC_USB30_SLV_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_USB30_SLV_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_USB30_SLV_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_USB30_SLV_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_USB30_SLV_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_USB30_SLV_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_USB30_SLV_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_USB30_SLV_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_USB30_SLV_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_USB30_SLV_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_USB30_SLV_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_USB30_SLV_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_USB30_SLV_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_USB30_SLV_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_USB30_SLV_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_USB30_SLV_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_USB30_SLV_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_SLV_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_USB30_SLEEP_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00007028) +#define HWIO_GCC_USB30_SLEEP_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00007028) +#define HWIO_GCC_USB30_SLEEP_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00007028) +#define HWIO_GCC_USB30_SLEEP_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_USB30_SLEEP_CBCR_ATTR 0x3 +#define HWIO_GCC_USB30_SLEEP_CBCR_IN \ + in_dword_masked(HWIO_GCC_USB30_SLEEP_CBCR_ADDR, HWIO_GCC_USB30_SLEEP_CBCR_RMSK) +#define HWIO_GCC_USB30_SLEEP_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_USB30_SLEEP_CBCR_ADDR, m) +#define HWIO_GCC_USB30_SLEEP_CBCR_OUT(v) \ + out_dword(HWIO_GCC_USB30_SLEEP_CBCR_ADDR,v) +#define HWIO_GCC_USB30_SLEEP_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB30_SLEEP_CBCR_ADDR,m,v,HWIO_GCC_USB30_SLEEP_CBCR_IN) +#define HWIO_GCC_USB30_SLEEP_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_USB30_SLEEP_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_USB30_SLEEP_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_USB30_SLEEP_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_USB30_SLEEP_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_USB30_SLEEP_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_USB30_SLEEP_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_USB30_SLEEP_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_USB30_SLEEP_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_USB30_SLEEP_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_USB30_SLEEP_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_USB30_SLEEP_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_USB30_SLEEP_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_USB30_SLEEP_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_USB30_SLEEP_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_SLEEP_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_USB30_MOCK_UTMI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000702c) +#define HWIO_GCC_USB30_MOCK_UTMI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000702c) +#define HWIO_GCC_USB30_MOCK_UTMI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000702c) +#define HWIO_GCC_USB30_MOCK_UTMI_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_USB30_MOCK_UTMI_CBCR_ATTR 0x3 +#define HWIO_GCC_USB30_MOCK_UTMI_CBCR_IN \ + in_dword_masked(HWIO_GCC_USB30_MOCK_UTMI_CBCR_ADDR, HWIO_GCC_USB30_MOCK_UTMI_CBCR_RMSK) +#define HWIO_GCC_USB30_MOCK_UTMI_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_USB30_MOCK_UTMI_CBCR_ADDR, m) +#define HWIO_GCC_USB30_MOCK_UTMI_CBCR_OUT(v) \ + out_dword(HWIO_GCC_USB30_MOCK_UTMI_CBCR_ADDR,v) +#define HWIO_GCC_USB30_MOCK_UTMI_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB30_MOCK_UTMI_CBCR_ADDR,m,v,HWIO_GCC_USB30_MOCK_UTMI_CBCR_IN) +#define HWIO_GCC_USB30_MOCK_UTMI_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_USB30_MOCK_UTMI_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_USB30_MOCK_UTMI_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_USB30_MOCK_UTMI_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_USB30_MOCK_UTMI_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_USB30_MOCK_UTMI_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_USB30_MOCK_UTMI_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_USB30_MOCK_UTMI_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_USB30_MOCK_UTMI_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_USB30_MOCK_UTMI_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_USB30_MOCK_UTMI_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_USB30_MOCK_UTMI_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_USB30_MOCK_UTMI_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_USB30_MOCK_UTMI_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_USB30_MOCK_UTMI_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_MOCK_UTMI_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_USB30_MASTER_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00007030) +#define HWIO_GCC_USB30_MASTER_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00007030) +#define HWIO_GCC_USB30_MASTER_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00007030) +#define HWIO_GCC_USB30_MASTER_CMD_RCGR_RMSK 0x800000f3 +#define HWIO_GCC_USB30_MASTER_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_USB30_MASTER_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_USB30_MASTER_CMD_RCGR_ADDR, HWIO_GCC_USB30_MASTER_CMD_RCGR_RMSK) +#define HWIO_GCC_USB30_MASTER_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_USB30_MASTER_CMD_RCGR_ADDR, m) +#define HWIO_GCC_USB30_MASTER_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_USB30_MASTER_CMD_RCGR_ADDR,v) +#define HWIO_GCC_USB30_MASTER_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB30_MASTER_CMD_RCGR_ADDR,m,v,HWIO_GCC_USB30_MASTER_CMD_RCGR_IN) +#define HWIO_GCC_USB30_MASTER_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_USB30_MASTER_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_USB30_MASTER_CMD_RCGR_DIRTY_D_BMSK 0x80 +#define HWIO_GCC_USB30_MASTER_CMD_RCGR_DIRTY_D_SHFT 0x7 +#define HWIO_GCC_USB30_MASTER_CMD_RCGR_DIRTY_N_BMSK 0x40 +#define HWIO_GCC_USB30_MASTER_CMD_RCGR_DIRTY_N_SHFT 0x6 +#define HWIO_GCC_USB30_MASTER_CMD_RCGR_DIRTY_M_BMSK 0x20 +#define HWIO_GCC_USB30_MASTER_CMD_RCGR_DIRTY_M_SHFT 0x5 +#define HWIO_GCC_USB30_MASTER_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_USB30_MASTER_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_USB30_MASTER_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_USB30_MASTER_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_USB30_MASTER_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_MASTER_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB30_MASTER_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_USB30_MASTER_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_USB30_MASTER_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_MASTER_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00007034) +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00007034) +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00007034) +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_RMSK 0x10371f +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_USB30_MASTER_CFG_RCGR_ADDR, HWIO_GCC_USB30_MASTER_CFG_RCGR_RMSK) +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_USB30_MASTER_CFG_RCGR_ADDR, m) +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_USB30_MASTER_CFG_RCGR_ADDR,v) +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB30_MASTER_CFG_RCGR_ADDR,m,v,HWIO_GCC_USB30_MASTER_CFG_RCGR_IN) +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_MODE_BMSK 0x3000 +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_MODE_SHFT 0xc +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_USB30_MASTER_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_USB30_MASTER_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00007038) +#define HWIO_GCC_USB30_MASTER_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00007038) +#define HWIO_GCC_USB30_MASTER_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00007038) +#define HWIO_GCC_USB30_MASTER_M_RMSK 0xff +#define HWIO_GCC_USB30_MASTER_M_ATTR 0x3 +#define HWIO_GCC_USB30_MASTER_M_IN \ + in_dword_masked(HWIO_GCC_USB30_MASTER_M_ADDR, HWIO_GCC_USB30_MASTER_M_RMSK) +#define HWIO_GCC_USB30_MASTER_M_INM(m) \ + in_dword_masked(HWIO_GCC_USB30_MASTER_M_ADDR, m) +#define HWIO_GCC_USB30_MASTER_M_OUT(v) \ + out_dword(HWIO_GCC_USB30_MASTER_M_ADDR,v) +#define HWIO_GCC_USB30_MASTER_M_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB30_MASTER_M_ADDR,m,v,HWIO_GCC_USB30_MASTER_M_IN) +#define HWIO_GCC_USB30_MASTER_M_M_BMSK 0xff +#define HWIO_GCC_USB30_MASTER_M_M_SHFT 0x0 + +#define HWIO_GCC_USB30_MASTER_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000703c) +#define HWIO_GCC_USB30_MASTER_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000703c) +#define HWIO_GCC_USB30_MASTER_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000703c) +#define HWIO_GCC_USB30_MASTER_N_RMSK 0xff +#define HWIO_GCC_USB30_MASTER_N_ATTR 0x3 +#define HWIO_GCC_USB30_MASTER_N_IN \ + in_dword_masked(HWIO_GCC_USB30_MASTER_N_ADDR, HWIO_GCC_USB30_MASTER_N_RMSK) +#define HWIO_GCC_USB30_MASTER_N_INM(m) \ + in_dword_masked(HWIO_GCC_USB30_MASTER_N_ADDR, m) +#define HWIO_GCC_USB30_MASTER_N_OUT(v) \ + out_dword(HWIO_GCC_USB30_MASTER_N_ADDR,v) +#define HWIO_GCC_USB30_MASTER_N_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB30_MASTER_N_ADDR,m,v,HWIO_GCC_USB30_MASTER_N_IN) +#define HWIO_GCC_USB30_MASTER_N_NOT_N_MINUS_M_BMSK 0xff +#define HWIO_GCC_USB30_MASTER_N_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_USB30_MASTER_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00007040) +#define HWIO_GCC_USB30_MASTER_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00007040) +#define HWIO_GCC_USB30_MASTER_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00007040) +#define HWIO_GCC_USB30_MASTER_D_RMSK 0xff +#define HWIO_GCC_USB30_MASTER_D_ATTR 0x3 +#define HWIO_GCC_USB30_MASTER_D_IN \ + in_dword_masked(HWIO_GCC_USB30_MASTER_D_ADDR, HWIO_GCC_USB30_MASTER_D_RMSK) +#define HWIO_GCC_USB30_MASTER_D_INM(m) \ + in_dword_masked(HWIO_GCC_USB30_MASTER_D_ADDR, m) +#define HWIO_GCC_USB30_MASTER_D_OUT(v) \ + out_dword(HWIO_GCC_USB30_MASTER_D_ADDR,v) +#define HWIO_GCC_USB30_MASTER_D_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB30_MASTER_D_ADDR,m,v,HWIO_GCC_USB30_MASTER_D_IN) +#define HWIO_GCC_USB30_MASTER_D_NOT_2D_BMSK 0xff +#define HWIO_GCC_USB30_MASTER_D_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_USB30_MOCK_UTMI_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00007048) +#define HWIO_GCC_USB30_MOCK_UTMI_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00007048) +#define HWIO_GCC_USB30_MOCK_UTMI_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00007048) +#define HWIO_GCC_USB30_MOCK_UTMI_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_USB30_MOCK_UTMI_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_USB30_MOCK_UTMI_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_USB30_MOCK_UTMI_CMD_RCGR_ADDR, HWIO_GCC_USB30_MOCK_UTMI_CMD_RCGR_RMSK) +#define HWIO_GCC_USB30_MOCK_UTMI_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_USB30_MOCK_UTMI_CMD_RCGR_ADDR, m) +#define HWIO_GCC_USB30_MOCK_UTMI_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_USB30_MOCK_UTMI_CMD_RCGR_ADDR,v) +#define HWIO_GCC_USB30_MOCK_UTMI_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB30_MOCK_UTMI_CMD_RCGR_ADDR,m,v,HWIO_GCC_USB30_MOCK_UTMI_CMD_RCGR_IN) +#define HWIO_GCC_USB30_MOCK_UTMI_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_USB30_MOCK_UTMI_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_USB30_MOCK_UTMI_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_USB30_MOCK_UTMI_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_USB30_MOCK_UTMI_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_USB30_MOCK_UTMI_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_USB30_MOCK_UTMI_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_MOCK_UTMI_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB30_MOCK_UTMI_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_USB30_MOCK_UTMI_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_USB30_MOCK_UTMI_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_MOCK_UTMI_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000704c) +#define HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000704c) +#define HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000704c) +#define HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_ADDR, HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_RMSK) +#define HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_ADDR, m) +#define HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_ADDR,v) +#define HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_ADDR,m,v,HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_IN) +#define HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_USB30_MOCK_UTMI_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_USB30_MOCK_UTMI_POSTDIV_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00007060) +#define HWIO_GCC_USB30_MOCK_UTMI_POSTDIV_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00007060) +#define HWIO_GCC_USB30_MOCK_UTMI_POSTDIV_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00007060) +#define HWIO_GCC_USB30_MOCK_UTMI_POSTDIV_CDIVR_RMSK 0xf +#define HWIO_GCC_USB30_MOCK_UTMI_POSTDIV_CDIVR_ATTR 0x3 +#define HWIO_GCC_USB30_MOCK_UTMI_POSTDIV_CDIVR_IN \ + in_dword_masked(HWIO_GCC_USB30_MOCK_UTMI_POSTDIV_CDIVR_ADDR, HWIO_GCC_USB30_MOCK_UTMI_POSTDIV_CDIVR_RMSK) +#define HWIO_GCC_USB30_MOCK_UTMI_POSTDIV_CDIVR_INM(m) \ + in_dword_masked(HWIO_GCC_USB30_MOCK_UTMI_POSTDIV_CDIVR_ADDR, m) +#define HWIO_GCC_USB30_MOCK_UTMI_POSTDIV_CDIVR_OUT(v) \ + out_dword(HWIO_GCC_USB30_MOCK_UTMI_POSTDIV_CDIVR_ADDR,v) +#define HWIO_GCC_USB30_MOCK_UTMI_POSTDIV_CDIVR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB30_MOCK_UTMI_POSTDIV_CDIVR_ADDR,m,v,HWIO_GCC_USB30_MOCK_UTMI_POSTDIV_CDIVR_IN) +#define HWIO_GCC_USB30_MOCK_UTMI_POSTDIV_CDIVR_CLK_DIV_BMSK 0xf +#define HWIO_GCC_USB30_MOCK_UTMI_POSTDIV_CDIVR_CLK_DIV_SHFT 0x0 + +#define HWIO_GCC_USB3_PHY_AUX_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00007064) +#define HWIO_GCC_USB3_PHY_AUX_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00007064) +#define HWIO_GCC_USB3_PHY_AUX_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00007064) +#define HWIO_GCC_USB3_PHY_AUX_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_USB3_PHY_AUX_CBCR_ATTR 0x3 +#define HWIO_GCC_USB3_PHY_AUX_CBCR_IN \ + in_dword_masked(HWIO_GCC_USB3_PHY_AUX_CBCR_ADDR, HWIO_GCC_USB3_PHY_AUX_CBCR_RMSK) +#define HWIO_GCC_USB3_PHY_AUX_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_USB3_PHY_AUX_CBCR_ADDR, m) +#define HWIO_GCC_USB3_PHY_AUX_CBCR_OUT(v) \ + out_dword(HWIO_GCC_USB3_PHY_AUX_CBCR_ADDR,v) +#define HWIO_GCC_USB3_PHY_AUX_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB3_PHY_AUX_CBCR_ADDR,m,v,HWIO_GCC_USB3_PHY_AUX_CBCR_IN) +#define HWIO_GCC_USB3_PHY_AUX_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_USB3_PHY_AUX_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_USB3_PHY_AUX_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_USB3_PHY_AUX_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_USB3_PHY_AUX_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_USB3_PHY_AUX_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_USB3_PHY_AUX_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_USB3_PHY_AUX_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_USB3_PHY_AUX_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_USB3_PHY_AUX_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_USB3_PHY_AUX_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_USB3_PHY_AUX_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_USB3_PHY_AUX_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_USB3_PHY_AUX_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_USB3_PHY_AUX_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB3_PHY_AUX_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_USB3_PHY_PIPE_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00007068) +#define HWIO_GCC_USB3_PHY_PIPE_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00007068) +#define HWIO_GCC_USB3_PHY_PIPE_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00007068) +#define HWIO_GCC_USB3_PHY_PIPE_CBCR_RMSK 0x81c0000f +#define HWIO_GCC_USB3_PHY_PIPE_CBCR_ATTR 0x3 +#define HWIO_GCC_USB3_PHY_PIPE_CBCR_IN \ + in_dword_masked(HWIO_GCC_USB3_PHY_PIPE_CBCR_ADDR, HWIO_GCC_USB3_PHY_PIPE_CBCR_RMSK) +#define HWIO_GCC_USB3_PHY_PIPE_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_USB3_PHY_PIPE_CBCR_ADDR, m) +#define HWIO_GCC_USB3_PHY_PIPE_CBCR_OUT(v) \ + out_dword(HWIO_GCC_USB3_PHY_PIPE_CBCR_ADDR,v) +#define HWIO_GCC_USB3_PHY_PIPE_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB3_PHY_PIPE_CBCR_ADDR,m,v,HWIO_GCC_USB3_PHY_PIPE_CBCR_IN) +#define HWIO_GCC_USB3_PHY_PIPE_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_USB3_PHY_PIPE_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_USB3_PHY_PIPE_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_USB3_PHY_PIPE_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_USB3_PHY_PIPE_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_USB3_PHY_PIPE_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_USB3_PHY_PIPE_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_USB3_PHY_PIPE_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_USB3_PHY_PIPE_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_USB3_PHY_PIPE_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_USB3_PHY_PIPE_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_USB3_PHY_PIPE_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_USB3_PHY_PIPE_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_USB3_PHY_PIPE_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_USB3_PHY_PIPE_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_USB3_PHY_PIPE_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_USB3_PHY_PIPE_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB3_PHY_PIPE_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB3_PHY_PIPE_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_USB3_PHY_PIPE_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_USB3_PHY_PIPE_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB3_PHY_PIPE_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_USB3_PHY_AUX_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00007070) +#define HWIO_GCC_USB3_PHY_AUX_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00007070) +#define HWIO_GCC_USB3_PHY_AUX_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00007070) +#define HWIO_GCC_USB3_PHY_AUX_CMD_RCGR_RMSK 0x800000f3 +#define HWIO_GCC_USB3_PHY_AUX_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_USB3_PHY_AUX_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_USB3_PHY_AUX_CMD_RCGR_ADDR, HWIO_GCC_USB3_PHY_AUX_CMD_RCGR_RMSK) +#define HWIO_GCC_USB3_PHY_AUX_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_USB3_PHY_AUX_CMD_RCGR_ADDR, m) +#define HWIO_GCC_USB3_PHY_AUX_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_USB3_PHY_AUX_CMD_RCGR_ADDR,v) +#define HWIO_GCC_USB3_PHY_AUX_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB3_PHY_AUX_CMD_RCGR_ADDR,m,v,HWIO_GCC_USB3_PHY_AUX_CMD_RCGR_IN) +#define HWIO_GCC_USB3_PHY_AUX_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_USB3_PHY_AUX_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_USB3_PHY_AUX_CMD_RCGR_DIRTY_D_BMSK 0x80 +#define HWIO_GCC_USB3_PHY_AUX_CMD_RCGR_DIRTY_D_SHFT 0x7 +#define HWIO_GCC_USB3_PHY_AUX_CMD_RCGR_DIRTY_N_BMSK 0x40 +#define HWIO_GCC_USB3_PHY_AUX_CMD_RCGR_DIRTY_N_SHFT 0x6 +#define HWIO_GCC_USB3_PHY_AUX_CMD_RCGR_DIRTY_M_BMSK 0x20 +#define HWIO_GCC_USB3_PHY_AUX_CMD_RCGR_DIRTY_M_SHFT 0x5 +#define HWIO_GCC_USB3_PHY_AUX_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_USB3_PHY_AUX_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_USB3_PHY_AUX_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_USB3_PHY_AUX_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_USB3_PHY_AUX_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB3_PHY_AUX_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB3_PHY_AUX_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_USB3_PHY_AUX_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_USB3_PHY_AUX_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB3_PHY_AUX_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00007074) +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00007074) +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00007074) +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_RMSK 0x10371f +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_ADDR, HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_RMSK) +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_ADDR, m) +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_ADDR,v) +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_ADDR,m,v,HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_IN) +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_MODE_BMSK 0x3000 +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_MODE_SHFT 0xc +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_USB3_PHY_AUX_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_USB3_PHY_AUX_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00007078) +#define HWIO_GCC_USB3_PHY_AUX_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00007078) +#define HWIO_GCC_USB3_PHY_AUX_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00007078) +#define HWIO_GCC_USB3_PHY_AUX_M_RMSK 0xffff +#define HWIO_GCC_USB3_PHY_AUX_M_ATTR 0x3 +#define HWIO_GCC_USB3_PHY_AUX_M_IN \ + in_dword_masked(HWIO_GCC_USB3_PHY_AUX_M_ADDR, HWIO_GCC_USB3_PHY_AUX_M_RMSK) +#define HWIO_GCC_USB3_PHY_AUX_M_INM(m) \ + in_dword_masked(HWIO_GCC_USB3_PHY_AUX_M_ADDR, m) +#define HWIO_GCC_USB3_PHY_AUX_M_OUT(v) \ + out_dword(HWIO_GCC_USB3_PHY_AUX_M_ADDR,v) +#define HWIO_GCC_USB3_PHY_AUX_M_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB3_PHY_AUX_M_ADDR,m,v,HWIO_GCC_USB3_PHY_AUX_M_IN) +#define HWIO_GCC_USB3_PHY_AUX_M_M_BMSK 0xffff +#define HWIO_GCC_USB3_PHY_AUX_M_M_SHFT 0x0 + +#define HWIO_GCC_USB3_PHY_AUX_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000707c) +#define HWIO_GCC_USB3_PHY_AUX_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000707c) +#define HWIO_GCC_USB3_PHY_AUX_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000707c) +#define HWIO_GCC_USB3_PHY_AUX_N_RMSK 0xffff +#define HWIO_GCC_USB3_PHY_AUX_N_ATTR 0x3 +#define HWIO_GCC_USB3_PHY_AUX_N_IN \ + in_dword_masked(HWIO_GCC_USB3_PHY_AUX_N_ADDR, HWIO_GCC_USB3_PHY_AUX_N_RMSK) +#define HWIO_GCC_USB3_PHY_AUX_N_INM(m) \ + in_dword_masked(HWIO_GCC_USB3_PHY_AUX_N_ADDR, m) +#define HWIO_GCC_USB3_PHY_AUX_N_OUT(v) \ + out_dword(HWIO_GCC_USB3_PHY_AUX_N_ADDR,v) +#define HWIO_GCC_USB3_PHY_AUX_N_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB3_PHY_AUX_N_ADDR,m,v,HWIO_GCC_USB3_PHY_AUX_N_IN) +#define HWIO_GCC_USB3_PHY_AUX_N_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_USB3_PHY_AUX_N_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_USB3_PHY_AUX_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00007080) +#define HWIO_GCC_USB3_PHY_AUX_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00007080) +#define HWIO_GCC_USB3_PHY_AUX_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00007080) +#define HWIO_GCC_USB3_PHY_AUX_D_RMSK 0xffff +#define HWIO_GCC_USB3_PHY_AUX_D_ATTR 0x3 +#define HWIO_GCC_USB3_PHY_AUX_D_IN \ + in_dword_masked(HWIO_GCC_USB3_PHY_AUX_D_ADDR, HWIO_GCC_USB3_PHY_AUX_D_RMSK) +#define HWIO_GCC_USB3_PHY_AUX_D_INM(m) \ + in_dword_masked(HWIO_GCC_USB3_PHY_AUX_D_ADDR, m) +#define HWIO_GCC_USB3_PHY_AUX_D_OUT(v) \ + out_dword(HWIO_GCC_USB3_PHY_AUX_D_ADDR,v) +#define HWIO_GCC_USB3_PHY_AUX_D_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB3_PHY_AUX_D_ADDR,m,v,HWIO_GCC_USB3_PHY_AUX_D_IN) +#define HWIO_GCC_USB3_PHY_AUX_D_NOT_2D_BMSK 0xffff +#define HWIO_GCC_USB3_PHY_AUX_D_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_USB3_PHY_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008000) +#define HWIO_GCC_USB3_PHY_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008000) +#define HWIO_GCC_USB3_PHY_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008000) +#define HWIO_GCC_USB3_PHY_BCR_RMSK 0x1 +#define HWIO_GCC_USB3_PHY_BCR_ATTR 0x3 +#define HWIO_GCC_USB3_PHY_BCR_IN \ + in_dword_masked(HWIO_GCC_USB3_PHY_BCR_ADDR, HWIO_GCC_USB3_PHY_BCR_RMSK) +#define HWIO_GCC_USB3_PHY_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_USB3_PHY_BCR_ADDR, m) +#define HWIO_GCC_USB3_PHY_BCR_OUT(v) \ + out_dword(HWIO_GCC_USB3_PHY_BCR_ADDR,v) +#define HWIO_GCC_USB3_PHY_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB3_PHY_BCR_ADDR,m,v,HWIO_GCC_USB3_PHY_BCR_IN) +#define HWIO_GCC_USB3_PHY_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_USB3_PHY_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_USB3_PHY_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB3_PHY_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_USB3PHY_PHY_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008004) +#define HWIO_GCC_USB3PHY_PHY_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008004) +#define HWIO_GCC_USB3PHY_PHY_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008004) +#define HWIO_GCC_USB3PHY_PHY_BCR_RMSK 0x1 +#define HWIO_GCC_USB3PHY_PHY_BCR_ATTR 0x3 +#define HWIO_GCC_USB3PHY_PHY_BCR_IN \ + in_dword_masked(HWIO_GCC_USB3PHY_PHY_BCR_ADDR, HWIO_GCC_USB3PHY_PHY_BCR_RMSK) +#define HWIO_GCC_USB3PHY_PHY_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_USB3PHY_PHY_BCR_ADDR, m) +#define HWIO_GCC_USB3PHY_PHY_BCR_OUT(v) \ + out_dword(HWIO_GCC_USB3PHY_PHY_BCR_ADDR,v) +#define HWIO_GCC_USB3PHY_PHY_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB3PHY_PHY_BCR_ADDR,m,v,HWIO_GCC_USB3PHY_PHY_BCR_IN) +#define HWIO_GCC_USB3PHY_PHY_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_USB3PHY_PHY_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_USB3PHY_PHY_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB3PHY_PHY_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUSB2PHY_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00009000) +#define HWIO_GCC_QUSB2PHY_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00009000) +#define HWIO_GCC_QUSB2PHY_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00009000) +#define HWIO_GCC_QUSB2PHY_BCR_RMSK 0x1 +#define HWIO_GCC_QUSB2PHY_BCR_ATTR 0x3 +#define HWIO_GCC_QUSB2PHY_BCR_IN \ + in_dword_masked(HWIO_GCC_QUSB2PHY_BCR_ADDR, HWIO_GCC_QUSB2PHY_BCR_RMSK) +#define HWIO_GCC_QUSB2PHY_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_QUSB2PHY_BCR_ADDR, m) +#define HWIO_GCC_QUSB2PHY_BCR_OUT(v) \ + out_dword(HWIO_GCC_QUSB2PHY_BCR_ADDR,v) +#define HWIO_GCC_QUSB2PHY_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUSB2PHY_BCR_ADDR,m,v,HWIO_GCC_QUSB2PHY_BCR_IN) +#define HWIO_GCC_QUSB2PHY_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_QUSB2PHY_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_QUSB2PHY_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUSB2PHY_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00009004) +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00009004) +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00009004) +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_BCR_RMSK 0x1 +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_BCR_ATTR 0x3 +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_BCR_IN \ + in_dword_masked(HWIO_GCC_USB_PHY_CFG_AHB2PHY_BCR_ADDR, HWIO_GCC_USB_PHY_CFG_AHB2PHY_BCR_RMSK) +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_USB_PHY_CFG_AHB2PHY_BCR_ADDR, m) +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_BCR_OUT(v) \ + out_dword(HWIO_GCC_USB_PHY_CFG_AHB2PHY_BCR_ADDR,v) +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB_PHY_CFG_AHB2PHY_BCR_ADDR,m,v,HWIO_GCC_USB_PHY_CFG_AHB2PHY_BCR_IN) +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00009008) +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00009008) +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00009008) +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_CBCR_ATTR 0x3 +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_CBCR_IN \ + in_dword_masked(HWIO_GCC_USB_PHY_CFG_AHB2PHY_CBCR_ADDR, HWIO_GCC_USB_PHY_CFG_AHB2PHY_CBCR_RMSK) +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_USB_PHY_CFG_AHB2PHY_CBCR_ADDR, m) +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_CBCR_OUT(v) \ + out_dword(HWIO_GCC_USB_PHY_CFG_AHB2PHY_CBCR_ADDR,v) +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB_PHY_CFG_AHB2PHY_CBCR_ADDR,m,v,HWIO_GCC_USB_PHY_CFG_AHB2PHY_CBCR_IN) +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SDCC1_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000a000) +#define HWIO_GCC_SDCC1_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000a000) +#define HWIO_GCC_SDCC1_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000a000) +#define HWIO_GCC_SDCC1_BCR_RMSK 0x1 +#define HWIO_GCC_SDCC1_BCR_ATTR 0x3 +#define HWIO_GCC_SDCC1_BCR_IN \ + in_dword_masked(HWIO_GCC_SDCC1_BCR_ADDR, HWIO_GCC_SDCC1_BCR_RMSK) +#define HWIO_GCC_SDCC1_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_SDCC1_BCR_ADDR, m) +#define HWIO_GCC_SDCC1_BCR_OUT(v) \ + out_dword(HWIO_GCC_SDCC1_BCR_ADDR,v) +#define HWIO_GCC_SDCC1_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SDCC1_BCR_ADDR,m,v,HWIO_GCC_SDCC1_BCR_IN) +#define HWIO_GCC_SDCC1_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_SDCC1_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_SDCC1_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_SDCC1_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SDCC1_APPS_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000a004) +#define HWIO_GCC_SDCC1_APPS_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000a004) +#define HWIO_GCC_SDCC1_APPS_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000a004) +#define HWIO_GCC_SDCC1_APPS_CBCR_RMSK 0x81c07ff5 +#define HWIO_GCC_SDCC1_APPS_CBCR_ATTR 0x3 +#define HWIO_GCC_SDCC1_APPS_CBCR_IN \ + in_dword_masked(HWIO_GCC_SDCC1_APPS_CBCR_ADDR, HWIO_GCC_SDCC1_APPS_CBCR_RMSK) +#define HWIO_GCC_SDCC1_APPS_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_SDCC1_APPS_CBCR_ADDR, m) +#define HWIO_GCC_SDCC1_APPS_CBCR_OUT(v) \ + out_dword(HWIO_GCC_SDCC1_APPS_CBCR_ADDR,v) +#define HWIO_GCC_SDCC1_APPS_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SDCC1_APPS_CBCR_ADDR,m,v,HWIO_GCC_SDCC1_APPS_CBCR_IN) +#define HWIO_GCC_SDCC1_APPS_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SDCC1_APPS_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SDCC1_APPS_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_SDCC1_APPS_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_SDCC1_APPS_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_SDCC1_APPS_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_SDCC1_APPS_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_SDCC1_APPS_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_SDCC1_APPS_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_SDCC1_APPS_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_SDCC1_APPS_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SDCC1_APPS_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SDCC1_APPS_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_SDCC1_APPS_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_SDCC1_APPS_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SDCC1_APPS_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SDCC1_APPS_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_SDCC1_APPS_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_SDCC1_APPS_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SDCC1_APPS_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SDCC1_APPS_CBCR_WAKEUP_BMSK 0xf00 +#define HWIO_GCC_SDCC1_APPS_CBCR_WAKEUP_SHFT 0x8 +#define HWIO_GCC_SDCC1_APPS_CBCR_WAKEUP_CLOCK0_FVAL 0x0 +#define HWIO_GCC_SDCC1_APPS_CBCR_WAKEUP_CLOCK1_FVAL 0x1 +#define HWIO_GCC_SDCC1_APPS_CBCR_WAKEUP_CLOCK2_FVAL 0x2 +#define HWIO_GCC_SDCC1_APPS_CBCR_WAKEUP_CLOCK3_FVAL 0x3 +#define HWIO_GCC_SDCC1_APPS_CBCR_WAKEUP_CLOCK4_FVAL 0x4 +#define HWIO_GCC_SDCC1_APPS_CBCR_WAKEUP_CLOCK5_FVAL 0x5 +#define HWIO_GCC_SDCC1_APPS_CBCR_WAKEUP_CLOCK6_FVAL 0x6 +#define HWIO_GCC_SDCC1_APPS_CBCR_WAKEUP_CLOCK7_FVAL 0x7 +#define HWIO_GCC_SDCC1_APPS_CBCR_WAKEUP_CLOCK8_FVAL 0x8 +#define HWIO_GCC_SDCC1_APPS_CBCR_WAKEUP_CLOCK9_FVAL 0x9 +#define HWIO_GCC_SDCC1_APPS_CBCR_WAKEUP_CLOCK10_FVAL 0xa +#define HWIO_GCC_SDCC1_APPS_CBCR_WAKEUP_CLOCK11_FVAL 0xb +#define HWIO_GCC_SDCC1_APPS_CBCR_WAKEUP_CLOCK12_FVAL 0xc +#define HWIO_GCC_SDCC1_APPS_CBCR_WAKEUP_CLOCK13_FVAL 0xd +#define HWIO_GCC_SDCC1_APPS_CBCR_WAKEUP_CLOCK14_FVAL 0xe +#define HWIO_GCC_SDCC1_APPS_CBCR_WAKEUP_CLOCK15_FVAL 0xf +#define HWIO_GCC_SDCC1_APPS_CBCR_SLEEP_BMSK 0xf0 +#define HWIO_GCC_SDCC1_APPS_CBCR_SLEEP_SHFT 0x4 +#define HWIO_GCC_SDCC1_APPS_CBCR_SLEEP_CLOCK0_FVAL 0x0 +#define HWIO_GCC_SDCC1_APPS_CBCR_SLEEP_CLOCK1_FVAL 0x1 +#define HWIO_GCC_SDCC1_APPS_CBCR_SLEEP_CLOCK2_FVAL 0x2 +#define HWIO_GCC_SDCC1_APPS_CBCR_SLEEP_CLOCK3_FVAL 0x3 +#define HWIO_GCC_SDCC1_APPS_CBCR_SLEEP_CLOCK4_FVAL 0x4 +#define HWIO_GCC_SDCC1_APPS_CBCR_SLEEP_CLOCK5_FVAL 0x5 +#define HWIO_GCC_SDCC1_APPS_CBCR_SLEEP_CLOCK6_FVAL 0x6 +#define HWIO_GCC_SDCC1_APPS_CBCR_SLEEP_CLOCK7_FVAL 0x7 +#define HWIO_GCC_SDCC1_APPS_CBCR_SLEEP_CLOCK8_FVAL 0x8 +#define HWIO_GCC_SDCC1_APPS_CBCR_SLEEP_CLOCK9_FVAL 0x9 +#define HWIO_GCC_SDCC1_APPS_CBCR_SLEEP_CLOCK10_FVAL 0xa +#define HWIO_GCC_SDCC1_APPS_CBCR_SLEEP_CLOCK11_FVAL 0xb +#define HWIO_GCC_SDCC1_APPS_CBCR_SLEEP_CLOCK12_FVAL 0xc +#define HWIO_GCC_SDCC1_APPS_CBCR_SLEEP_CLOCK13_FVAL 0xd +#define HWIO_GCC_SDCC1_APPS_CBCR_SLEEP_CLOCK14_FVAL 0xe +#define HWIO_GCC_SDCC1_APPS_CBCR_SLEEP_CLOCK15_FVAL 0xf +#define HWIO_GCC_SDCC1_APPS_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_SDCC1_APPS_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_SDCC1_APPS_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SDCC1_APPS_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_SDCC1_APPS_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SDCC1_APPS_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SDCC1_APPS_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SDCC1_APPS_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SDCC1_APPS_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000a008) +#define HWIO_GCC_SDCC1_APPS_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000a008) +#define HWIO_GCC_SDCC1_APPS_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000a008) +#define HWIO_GCC_SDCC1_APPS_SREGR_RMSK 0xfffffffe +#define HWIO_GCC_SDCC1_APPS_SREGR_ATTR 0x3 +#define HWIO_GCC_SDCC1_APPS_SREGR_IN \ + in_dword_masked(HWIO_GCC_SDCC1_APPS_SREGR_ADDR, HWIO_GCC_SDCC1_APPS_SREGR_RMSK) +#define HWIO_GCC_SDCC1_APPS_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_SDCC1_APPS_SREGR_ADDR, m) +#define HWIO_GCC_SDCC1_APPS_SREGR_OUT(v) \ + out_dword(HWIO_GCC_SDCC1_APPS_SREGR_ADDR,v) +#define HWIO_GCC_SDCC1_APPS_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SDCC1_APPS_SREGR_ADDR,m,v,HWIO_GCC_SDCC1_APPS_SREGR_IN) +#define HWIO_GCC_SDCC1_APPS_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xff000000 +#define HWIO_GCC_SDCC1_APPS_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_SDCC1_APPS_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xff0000 +#define HWIO_GCC_SDCC1_APPS_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_SDCC1_APPS_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_SDCC1_APPS_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_SDCC1_APPS_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_SDCC1_APPS_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_SDCC1_APPS_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_SDCC1_APPS_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_SDCC1_APPS_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_SDCC1_APPS_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_SDCC1_APPS_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_SDCC1_APPS_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_SDCC1_APPS_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_SDCC1_APPS_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_SDCC1_APPS_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_SDCC1_APPS_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_SDCC1_APPS_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SDCC1_APPS_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_SDCC1_APPS_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_SDCC1_APPS_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_SDCC1_APPS_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_SDCC1_APPS_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_SDCC1_APPS_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_SDCC1_APPS_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_SDCC1_APPS_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_SDCC1_APPS_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_SDCC1_APPS_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_SDCC1_APPS_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_SDCC1_APPS_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_SDCC1_APPS_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_SDCC1_APPS_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SDCC1_APPS_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SDCC1_APPS_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_SDCC1_APPS_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_SDCC1_APPS_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_SDCC1_APPS_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SDCC1_APPS_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_SDCC1_APPS_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_SDCC1_APPS_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_SDCC1_APPS_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_SDCC1_APPS_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_SDCC1_APPS_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_SDCC1_APPS_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_SDCC1_APPS_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_SDCC1_APPS_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_SDCC1_APPS_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_SDCC1_APPS_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_SDCC1_APPS_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_SDCC1_APPS_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_SDCC1_APPS_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_SDCC1_APPS_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_SDCC1_APPS_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_SDCC1_APPS_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_SDCC1_APPS_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_SDCC1_APPS_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_SDCC1_APPS_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SDCC1_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000a00c) +#define HWIO_GCC_SDCC1_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000a00c) +#define HWIO_GCC_SDCC1_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000a00c) +#define HWIO_GCC_SDCC1_AHB_CBCR_RMSK 0x81d00005 +#define HWIO_GCC_SDCC1_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_SDCC1_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_SDCC1_AHB_CBCR_ADDR, HWIO_GCC_SDCC1_AHB_CBCR_RMSK) +#define HWIO_GCC_SDCC1_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_SDCC1_AHB_CBCR_ADDR, m) +#define HWIO_GCC_SDCC1_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_SDCC1_AHB_CBCR_ADDR,v) +#define HWIO_GCC_SDCC1_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SDCC1_AHB_CBCR_ADDR,m,v,HWIO_GCC_SDCC1_AHB_CBCR_IN) +#define HWIO_GCC_SDCC1_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SDCC1_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SDCC1_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_SDCC1_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_SDCC1_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_SDCC1_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_SDCC1_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_SDCC1_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_SDCC1_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_SDCC1_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_SDCC1_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_SDCC1_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_SDCC1_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SDCC1_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_SDCC1_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SDCC1_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SDCC1_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SDCC1_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SDCC1_APPS_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000a010) +#define HWIO_GCC_SDCC1_APPS_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000a010) +#define HWIO_GCC_SDCC1_APPS_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000a010) +#define HWIO_GCC_SDCC1_APPS_CMD_RCGR_RMSK 0x800000f3 +#define HWIO_GCC_SDCC1_APPS_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_SDCC1_APPS_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_SDCC1_APPS_CMD_RCGR_ADDR, HWIO_GCC_SDCC1_APPS_CMD_RCGR_RMSK) +#define HWIO_GCC_SDCC1_APPS_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_SDCC1_APPS_CMD_RCGR_ADDR, m) +#define HWIO_GCC_SDCC1_APPS_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_SDCC1_APPS_CMD_RCGR_ADDR,v) +#define HWIO_GCC_SDCC1_APPS_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SDCC1_APPS_CMD_RCGR_ADDR,m,v,HWIO_GCC_SDCC1_APPS_CMD_RCGR_IN) +#define HWIO_GCC_SDCC1_APPS_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_SDCC1_APPS_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_SDCC1_APPS_CMD_RCGR_DIRTY_D_BMSK 0x80 +#define HWIO_GCC_SDCC1_APPS_CMD_RCGR_DIRTY_D_SHFT 0x7 +#define HWIO_GCC_SDCC1_APPS_CMD_RCGR_DIRTY_N_BMSK 0x40 +#define HWIO_GCC_SDCC1_APPS_CMD_RCGR_DIRTY_N_SHFT 0x6 +#define HWIO_GCC_SDCC1_APPS_CMD_RCGR_DIRTY_M_BMSK 0x20 +#define HWIO_GCC_SDCC1_APPS_CMD_RCGR_DIRTY_M_SHFT 0x5 +#define HWIO_GCC_SDCC1_APPS_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_SDCC1_APPS_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_SDCC1_APPS_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_SDCC1_APPS_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_SDCC1_APPS_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_SDCC1_APPS_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_SDCC1_APPS_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_SDCC1_APPS_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_SDCC1_APPS_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SDCC1_APPS_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000a014) +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000a014) +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000a014) +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_RMSK 0x10371f +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_SDCC1_APPS_CFG_RCGR_ADDR, HWIO_GCC_SDCC1_APPS_CFG_RCGR_RMSK) +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_SDCC1_APPS_CFG_RCGR_ADDR, m) +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_SDCC1_APPS_CFG_RCGR_ADDR,v) +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SDCC1_APPS_CFG_RCGR_ADDR,m,v,HWIO_GCC_SDCC1_APPS_CFG_RCGR_IN) +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_MODE_BMSK 0x3000 +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_MODE_SHFT 0xc +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_SDCC1_APPS_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_SDCC1_APPS_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000a018) +#define HWIO_GCC_SDCC1_APPS_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000a018) +#define HWIO_GCC_SDCC1_APPS_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000a018) +#define HWIO_GCC_SDCC1_APPS_M_RMSK 0xff +#define HWIO_GCC_SDCC1_APPS_M_ATTR 0x3 +#define HWIO_GCC_SDCC1_APPS_M_IN \ + in_dword_masked(HWIO_GCC_SDCC1_APPS_M_ADDR, HWIO_GCC_SDCC1_APPS_M_RMSK) +#define HWIO_GCC_SDCC1_APPS_M_INM(m) \ + in_dword_masked(HWIO_GCC_SDCC1_APPS_M_ADDR, m) +#define HWIO_GCC_SDCC1_APPS_M_OUT(v) \ + out_dword(HWIO_GCC_SDCC1_APPS_M_ADDR,v) +#define HWIO_GCC_SDCC1_APPS_M_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SDCC1_APPS_M_ADDR,m,v,HWIO_GCC_SDCC1_APPS_M_IN) +#define HWIO_GCC_SDCC1_APPS_M_M_BMSK 0xff +#define HWIO_GCC_SDCC1_APPS_M_M_SHFT 0x0 + +#define HWIO_GCC_SDCC1_APPS_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000a01c) +#define HWIO_GCC_SDCC1_APPS_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000a01c) +#define HWIO_GCC_SDCC1_APPS_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000a01c) +#define HWIO_GCC_SDCC1_APPS_N_RMSK 0xff +#define HWIO_GCC_SDCC1_APPS_N_ATTR 0x3 +#define HWIO_GCC_SDCC1_APPS_N_IN \ + in_dword_masked(HWIO_GCC_SDCC1_APPS_N_ADDR, HWIO_GCC_SDCC1_APPS_N_RMSK) +#define HWIO_GCC_SDCC1_APPS_N_INM(m) \ + in_dword_masked(HWIO_GCC_SDCC1_APPS_N_ADDR, m) +#define HWIO_GCC_SDCC1_APPS_N_OUT(v) \ + out_dword(HWIO_GCC_SDCC1_APPS_N_ADDR,v) +#define HWIO_GCC_SDCC1_APPS_N_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SDCC1_APPS_N_ADDR,m,v,HWIO_GCC_SDCC1_APPS_N_IN) +#define HWIO_GCC_SDCC1_APPS_N_NOT_N_MINUS_M_BMSK 0xff +#define HWIO_GCC_SDCC1_APPS_N_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_SDCC1_APPS_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000a020) +#define HWIO_GCC_SDCC1_APPS_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000a020) +#define HWIO_GCC_SDCC1_APPS_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000a020) +#define HWIO_GCC_SDCC1_APPS_D_RMSK 0xff +#define HWIO_GCC_SDCC1_APPS_D_ATTR 0x3 +#define HWIO_GCC_SDCC1_APPS_D_IN \ + in_dword_masked(HWIO_GCC_SDCC1_APPS_D_ADDR, HWIO_GCC_SDCC1_APPS_D_RMSK) +#define HWIO_GCC_SDCC1_APPS_D_INM(m) \ + in_dword_masked(HWIO_GCC_SDCC1_APPS_D_ADDR, m) +#define HWIO_GCC_SDCC1_APPS_D_OUT(v) \ + out_dword(HWIO_GCC_SDCC1_APPS_D_ADDR,v) +#define HWIO_GCC_SDCC1_APPS_D_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SDCC1_APPS_D_ADDR,m,v,HWIO_GCC_SDCC1_APPS_D_IN) +#define HWIO_GCC_SDCC1_APPS_D_NOT_2D_BMSK 0xff +#define HWIO_GCC_SDCC1_APPS_D_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_BLSP1_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000b000) +#define HWIO_GCC_BLSP1_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000b000) +#define HWIO_GCC_BLSP1_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000b000) +#define HWIO_GCC_BLSP1_BCR_RMSK 0x1 +#define HWIO_GCC_BLSP1_BCR_ATTR 0x3 +#define HWIO_GCC_BLSP1_BCR_IN \ + in_dword_masked(HWIO_GCC_BLSP1_BCR_ADDR, HWIO_GCC_BLSP1_BCR_RMSK) +#define HWIO_GCC_BLSP1_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_BCR_ADDR, m) +#define HWIO_GCC_BLSP1_BCR_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_BCR_ADDR,v) +#define HWIO_GCC_BLSP1_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_BCR_ADDR,m,v,HWIO_GCC_BLSP1_BCR_IN) +#define HWIO_GCC_BLSP1_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_BLSP1_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_BLSP1_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_BLSP1_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000b004) +#define HWIO_GCC_BLSP1_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000b004) +#define HWIO_GCC_BLSP1_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000b004) +#define HWIO_GCC_BLSP1_AHB_CBCR_RMSK 0x81d07ff4 +#define HWIO_GCC_BLSP1_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_BLSP1_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_BLSP1_AHB_CBCR_ADDR, HWIO_GCC_BLSP1_AHB_CBCR_RMSK) +#define HWIO_GCC_BLSP1_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_AHB_CBCR_ADDR, m) +#define HWIO_GCC_BLSP1_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_AHB_CBCR_ADDR,v) +#define HWIO_GCC_BLSP1_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_AHB_CBCR_ADDR,m,v,HWIO_GCC_BLSP1_AHB_CBCR_IN) +#define HWIO_GCC_BLSP1_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_BLSP1_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_BLSP1_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_BLSP1_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_BLSP1_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_BLSP1_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_BLSP1_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_BLSP1_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_BLSP1_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_BLSP1_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_BLSP1_AHB_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_BLSP1_AHB_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_BLSP1_AHB_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_AHB_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_BLSP1_AHB_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_BLSP1_AHB_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_BLSP1_AHB_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_AHB_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_BLSP1_AHB_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_BLSP1_AHB_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_BLSP1_AHB_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_AHB_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_BLSP1_AHB_CBCR_WAKEUP_BMSK 0xf00 +#define HWIO_GCC_BLSP1_AHB_CBCR_WAKEUP_SHFT 0x8 +#define HWIO_GCC_BLSP1_AHB_CBCR_WAKEUP_CLOCK0_FVAL 0x0 +#define HWIO_GCC_BLSP1_AHB_CBCR_WAKEUP_CLOCK1_FVAL 0x1 +#define HWIO_GCC_BLSP1_AHB_CBCR_WAKEUP_CLOCK2_FVAL 0x2 +#define HWIO_GCC_BLSP1_AHB_CBCR_WAKEUP_CLOCK3_FVAL 0x3 +#define HWIO_GCC_BLSP1_AHB_CBCR_WAKEUP_CLOCK4_FVAL 0x4 +#define HWIO_GCC_BLSP1_AHB_CBCR_WAKEUP_CLOCK5_FVAL 0x5 +#define HWIO_GCC_BLSP1_AHB_CBCR_WAKEUP_CLOCK6_FVAL 0x6 +#define HWIO_GCC_BLSP1_AHB_CBCR_WAKEUP_CLOCK7_FVAL 0x7 +#define HWIO_GCC_BLSP1_AHB_CBCR_WAKEUP_CLOCK8_FVAL 0x8 +#define HWIO_GCC_BLSP1_AHB_CBCR_WAKEUP_CLOCK9_FVAL 0x9 +#define HWIO_GCC_BLSP1_AHB_CBCR_WAKEUP_CLOCK10_FVAL 0xa +#define HWIO_GCC_BLSP1_AHB_CBCR_WAKEUP_CLOCK11_FVAL 0xb +#define HWIO_GCC_BLSP1_AHB_CBCR_WAKEUP_CLOCK12_FVAL 0xc +#define HWIO_GCC_BLSP1_AHB_CBCR_WAKEUP_CLOCK13_FVAL 0xd +#define HWIO_GCC_BLSP1_AHB_CBCR_WAKEUP_CLOCK14_FVAL 0xe +#define HWIO_GCC_BLSP1_AHB_CBCR_WAKEUP_CLOCK15_FVAL 0xf +#define HWIO_GCC_BLSP1_AHB_CBCR_SLEEP_BMSK 0xf0 +#define HWIO_GCC_BLSP1_AHB_CBCR_SLEEP_SHFT 0x4 +#define HWIO_GCC_BLSP1_AHB_CBCR_SLEEP_CLOCK0_FVAL 0x0 +#define HWIO_GCC_BLSP1_AHB_CBCR_SLEEP_CLOCK1_FVAL 0x1 +#define HWIO_GCC_BLSP1_AHB_CBCR_SLEEP_CLOCK2_FVAL 0x2 +#define HWIO_GCC_BLSP1_AHB_CBCR_SLEEP_CLOCK3_FVAL 0x3 +#define HWIO_GCC_BLSP1_AHB_CBCR_SLEEP_CLOCK4_FVAL 0x4 +#define HWIO_GCC_BLSP1_AHB_CBCR_SLEEP_CLOCK5_FVAL 0x5 +#define HWIO_GCC_BLSP1_AHB_CBCR_SLEEP_CLOCK6_FVAL 0x6 +#define HWIO_GCC_BLSP1_AHB_CBCR_SLEEP_CLOCK7_FVAL 0x7 +#define HWIO_GCC_BLSP1_AHB_CBCR_SLEEP_CLOCK8_FVAL 0x8 +#define HWIO_GCC_BLSP1_AHB_CBCR_SLEEP_CLOCK9_FVAL 0x9 +#define HWIO_GCC_BLSP1_AHB_CBCR_SLEEP_CLOCK10_FVAL 0xa +#define HWIO_GCC_BLSP1_AHB_CBCR_SLEEP_CLOCK11_FVAL 0xb +#define HWIO_GCC_BLSP1_AHB_CBCR_SLEEP_CLOCK12_FVAL 0xc +#define HWIO_GCC_BLSP1_AHB_CBCR_SLEEP_CLOCK13_FVAL 0xd +#define HWIO_GCC_BLSP1_AHB_CBCR_SLEEP_CLOCK14_FVAL 0xe +#define HWIO_GCC_BLSP1_AHB_CBCR_SLEEP_CLOCK15_FVAL 0xf +#define HWIO_GCC_BLSP1_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_BLSP1_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_BLSP1_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_BLSP1_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 + +#define HWIO_GCC_BLSP1_AHB_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000b008) +#define HWIO_GCC_BLSP1_AHB_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000b008) +#define HWIO_GCC_BLSP1_AHB_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000b008) +#define HWIO_GCC_BLSP1_AHB_SREGR_RMSK 0xfffffffe +#define HWIO_GCC_BLSP1_AHB_SREGR_ATTR 0x3 +#define HWIO_GCC_BLSP1_AHB_SREGR_IN \ + in_dword_masked(HWIO_GCC_BLSP1_AHB_SREGR_ADDR, HWIO_GCC_BLSP1_AHB_SREGR_RMSK) +#define HWIO_GCC_BLSP1_AHB_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_AHB_SREGR_ADDR, m) +#define HWIO_GCC_BLSP1_AHB_SREGR_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_AHB_SREGR_ADDR,v) +#define HWIO_GCC_BLSP1_AHB_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_AHB_SREGR_ADDR,m,v,HWIO_GCC_BLSP1_AHB_SREGR_IN) +#define HWIO_GCC_BLSP1_AHB_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xff000000 +#define HWIO_GCC_BLSP1_AHB_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_BLSP1_AHB_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xff0000 +#define HWIO_GCC_BLSP1_AHB_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_BLSP1_AHB_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_BLSP1_AHB_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_BLSP1_AHB_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_BLSP1_AHB_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_BLSP1_AHB_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_BLSP1_AHB_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_BLSP1_AHB_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_BLSP1_AHB_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_BLSP1_AHB_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_BLSP1_AHB_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_BLSP1_AHB_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_BLSP1_AHB_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_BLSP1_AHB_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_BLSP1_AHB_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_BLSP1_AHB_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_BLSP1_AHB_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_BLSP1_AHB_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_BLSP1_AHB_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_BLSP1_AHB_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_BLSP1_AHB_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_BLSP1_AHB_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_BLSP1_AHB_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_BLSP1_AHB_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_BLSP1_AHB_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_BLSP1_AHB_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_BLSP1_AHB_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_BLSP1_AHB_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_BLSP1_AHB_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_BLSP1_AHB_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_AHB_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_BLSP1_AHB_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_BLSP1_AHB_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_BLSP1_AHB_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_BLSP1_AHB_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_BLSP1_AHB_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_BLSP1_AHB_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_BLSP1_AHB_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_BLSP1_AHB_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_BLSP1_AHB_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_BLSP1_AHB_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_BLSP1_AHB_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_BLSP1_AHB_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_BLSP1_AHB_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_BLSP1_AHB_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_BLSP1_AHB_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_BLSP1_AHB_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_BLSP1_AHB_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_BLSP1_AHB_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_BLSP1_AHB_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_BLSP1_AHB_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_BLSP1_AHB_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_BLSP1_AHB_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_BLSP1_AHB_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_AHB_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_BLSP1_SLEEP_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000b00c) +#define HWIO_GCC_BLSP1_SLEEP_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000b00c) +#define HWIO_GCC_BLSP1_SLEEP_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000b00c) +#define HWIO_GCC_BLSP1_SLEEP_CBCR_RMSK 0x81c00004 +#define HWIO_GCC_BLSP1_SLEEP_CBCR_ATTR 0x3 +#define HWIO_GCC_BLSP1_SLEEP_CBCR_IN \ + in_dword_masked(HWIO_GCC_BLSP1_SLEEP_CBCR_ADDR, HWIO_GCC_BLSP1_SLEEP_CBCR_RMSK) +#define HWIO_GCC_BLSP1_SLEEP_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_SLEEP_CBCR_ADDR, m) +#define HWIO_GCC_BLSP1_SLEEP_CBCR_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_SLEEP_CBCR_ADDR,v) +#define HWIO_GCC_BLSP1_SLEEP_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_SLEEP_CBCR_ADDR,m,v,HWIO_GCC_BLSP1_SLEEP_CBCR_IN) +#define HWIO_GCC_BLSP1_SLEEP_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_BLSP1_SLEEP_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_BLSP1_SLEEP_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_BLSP1_SLEEP_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_BLSP1_SLEEP_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_BLSP1_SLEEP_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_BLSP1_SLEEP_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_BLSP1_SLEEP_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_BLSP1_SLEEP_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_BLSP1_SLEEP_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_BLSP1_SLEEP_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_BLSP1_SLEEP_CBCR_CLK_ARES_RESET_FVAL 0x1 + +#define HWIO_GCC_BLSP_UART_SIM_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000b010) +#define HWIO_GCC_BLSP_UART_SIM_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000b010) +#define HWIO_GCC_BLSP_UART_SIM_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000b010) +#define HWIO_GCC_BLSP_UART_SIM_CMD_RCGR_RMSK 0x800000f3 +#define HWIO_GCC_BLSP_UART_SIM_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_BLSP_UART_SIM_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_BLSP_UART_SIM_CMD_RCGR_ADDR, HWIO_GCC_BLSP_UART_SIM_CMD_RCGR_RMSK) +#define HWIO_GCC_BLSP_UART_SIM_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP_UART_SIM_CMD_RCGR_ADDR, m) +#define HWIO_GCC_BLSP_UART_SIM_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_BLSP_UART_SIM_CMD_RCGR_ADDR,v) +#define HWIO_GCC_BLSP_UART_SIM_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP_UART_SIM_CMD_RCGR_ADDR,m,v,HWIO_GCC_BLSP_UART_SIM_CMD_RCGR_IN) +#define HWIO_GCC_BLSP_UART_SIM_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_BLSP_UART_SIM_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_BLSP_UART_SIM_CMD_RCGR_DIRTY_D_BMSK 0x80 +#define HWIO_GCC_BLSP_UART_SIM_CMD_RCGR_DIRTY_D_SHFT 0x7 +#define HWIO_GCC_BLSP_UART_SIM_CMD_RCGR_DIRTY_N_BMSK 0x40 +#define HWIO_GCC_BLSP_UART_SIM_CMD_RCGR_DIRTY_N_SHFT 0x6 +#define HWIO_GCC_BLSP_UART_SIM_CMD_RCGR_DIRTY_M_BMSK 0x20 +#define HWIO_GCC_BLSP_UART_SIM_CMD_RCGR_DIRTY_M_SHFT 0x5 +#define HWIO_GCC_BLSP_UART_SIM_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_BLSP_UART_SIM_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_BLSP_UART_SIM_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_BLSP_UART_SIM_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_BLSP_UART_SIM_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP_UART_SIM_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_BLSP_UART_SIM_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_BLSP_UART_SIM_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_BLSP_UART_SIM_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP_UART_SIM_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000b014) +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000b014) +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000b014) +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_RMSK 0x10371f +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_ADDR, HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_RMSK) +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_ADDR, m) +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_ADDR,v) +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_ADDR,m,v,HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_IN) +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_MODE_BMSK 0x3000 +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_MODE_SHFT 0xc +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_BLSP_UART_SIM_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_BLSP_UART_SIM_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000b018) +#define HWIO_GCC_BLSP_UART_SIM_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000b018) +#define HWIO_GCC_BLSP_UART_SIM_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000b018) +#define HWIO_GCC_BLSP_UART_SIM_M_RMSK 0xff +#define HWIO_GCC_BLSP_UART_SIM_M_ATTR 0x3 +#define HWIO_GCC_BLSP_UART_SIM_M_IN \ + in_dword_masked(HWIO_GCC_BLSP_UART_SIM_M_ADDR, HWIO_GCC_BLSP_UART_SIM_M_RMSK) +#define HWIO_GCC_BLSP_UART_SIM_M_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP_UART_SIM_M_ADDR, m) +#define HWIO_GCC_BLSP_UART_SIM_M_OUT(v) \ + out_dword(HWIO_GCC_BLSP_UART_SIM_M_ADDR,v) +#define HWIO_GCC_BLSP_UART_SIM_M_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP_UART_SIM_M_ADDR,m,v,HWIO_GCC_BLSP_UART_SIM_M_IN) +#define HWIO_GCC_BLSP_UART_SIM_M_M_BMSK 0xff +#define HWIO_GCC_BLSP_UART_SIM_M_M_SHFT 0x0 + +#define HWIO_GCC_BLSP_UART_SIM_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000b01c) +#define HWIO_GCC_BLSP_UART_SIM_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000b01c) +#define HWIO_GCC_BLSP_UART_SIM_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000b01c) +#define HWIO_GCC_BLSP_UART_SIM_N_RMSK 0xff +#define HWIO_GCC_BLSP_UART_SIM_N_ATTR 0x3 +#define HWIO_GCC_BLSP_UART_SIM_N_IN \ + in_dword_masked(HWIO_GCC_BLSP_UART_SIM_N_ADDR, HWIO_GCC_BLSP_UART_SIM_N_RMSK) +#define HWIO_GCC_BLSP_UART_SIM_N_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP_UART_SIM_N_ADDR, m) +#define HWIO_GCC_BLSP_UART_SIM_N_OUT(v) \ + out_dword(HWIO_GCC_BLSP_UART_SIM_N_ADDR,v) +#define HWIO_GCC_BLSP_UART_SIM_N_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP_UART_SIM_N_ADDR,m,v,HWIO_GCC_BLSP_UART_SIM_N_IN) +#define HWIO_GCC_BLSP_UART_SIM_N_NOT_N_MINUS_M_BMSK 0xff +#define HWIO_GCC_BLSP_UART_SIM_N_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_BLSP_UART_SIM_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000b020) +#define HWIO_GCC_BLSP_UART_SIM_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000b020) +#define HWIO_GCC_BLSP_UART_SIM_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000b020) +#define HWIO_GCC_BLSP_UART_SIM_D_RMSK 0xff +#define HWIO_GCC_BLSP_UART_SIM_D_ATTR 0x3 +#define HWIO_GCC_BLSP_UART_SIM_D_IN \ + in_dword_masked(HWIO_GCC_BLSP_UART_SIM_D_ADDR, HWIO_GCC_BLSP_UART_SIM_D_RMSK) +#define HWIO_GCC_BLSP_UART_SIM_D_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP_UART_SIM_D_ADDR, m) +#define HWIO_GCC_BLSP_UART_SIM_D_OUT(v) \ + out_dword(HWIO_GCC_BLSP_UART_SIM_D_ADDR,v) +#define HWIO_GCC_BLSP_UART_SIM_D_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP_UART_SIM_D_ADDR,m,v,HWIO_GCC_BLSP_UART_SIM_D_IN) +#define HWIO_GCC_BLSP_UART_SIM_D_NOT_2D_BMSK 0xff +#define HWIO_GCC_BLSP_UART_SIM_D_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_BLSP1_QUP1_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000c000) +#define HWIO_GCC_BLSP1_QUP1_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c000) +#define HWIO_GCC_BLSP1_QUP1_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c000) +#define HWIO_GCC_BLSP1_QUP1_BCR_RMSK 0x1 +#define HWIO_GCC_BLSP1_QUP1_BCR_ATTR 0x3 +#define HWIO_GCC_BLSP1_QUP1_BCR_IN \ + in_dword_masked(HWIO_GCC_BLSP1_QUP1_BCR_ADDR, HWIO_GCC_BLSP1_QUP1_BCR_RMSK) +#define HWIO_GCC_BLSP1_QUP1_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_QUP1_BCR_ADDR, m) +#define HWIO_GCC_BLSP1_QUP1_BCR_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_QUP1_BCR_ADDR,v) +#define HWIO_GCC_BLSP1_QUP1_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_QUP1_BCR_ADDR,m,v,HWIO_GCC_BLSP1_QUP1_BCR_IN) +#define HWIO_GCC_BLSP1_QUP1_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_BLSP1_QUP1_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_BLSP1_QUP1_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP1_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000c004) +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c004) +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c004) +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CBCR_ATTR 0x3 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CBCR_IN \ + in_dword_masked(HWIO_GCC_BLSP1_QUP1_SPI_APPS_CBCR_ADDR, HWIO_GCC_BLSP1_QUP1_SPI_APPS_CBCR_RMSK) +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_QUP1_SPI_APPS_CBCR_ADDR, m) +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CBCR_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_QUP1_SPI_APPS_CBCR_ADDR,v) +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_QUP1_SPI_APPS_CBCR_ADDR,m,v,HWIO_GCC_BLSP1_QUP1_SPI_APPS_CBCR_IN) +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000c008) +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c008) +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c008) +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CBCR_ATTR 0x3 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CBCR_IN \ + in_dword_masked(HWIO_GCC_BLSP1_QUP1_I2C_APPS_CBCR_ADDR, HWIO_GCC_BLSP1_QUP1_I2C_APPS_CBCR_RMSK) +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_QUP1_I2C_APPS_CBCR_ADDR, m) +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CBCR_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_QUP1_I2C_APPS_CBCR_ADDR,v) +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_QUP1_I2C_APPS_CBCR_ADDR,m,v,HWIO_GCC_BLSP1_QUP1_I2C_APPS_CBCR_IN) +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000c00c) +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c00c) +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c00c) +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CMD_RCGR_RMSK 0x800000f3 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_BLSP1_QUP1_SPI_APPS_CMD_RCGR_ADDR, HWIO_GCC_BLSP1_QUP1_SPI_APPS_CMD_RCGR_RMSK) +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_QUP1_SPI_APPS_CMD_RCGR_ADDR, m) +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_QUP1_SPI_APPS_CMD_RCGR_ADDR,v) +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_QUP1_SPI_APPS_CMD_RCGR_ADDR,m,v,HWIO_GCC_BLSP1_QUP1_SPI_APPS_CMD_RCGR_IN) +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CMD_RCGR_DIRTY_D_BMSK 0x80 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CMD_RCGR_DIRTY_D_SHFT 0x7 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CMD_RCGR_DIRTY_N_BMSK 0x40 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CMD_RCGR_DIRTY_N_SHFT 0x6 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CMD_RCGR_DIRTY_M_BMSK 0x20 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CMD_RCGR_DIRTY_M_SHFT 0x5 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000c010) +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c010) +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c010) +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_RMSK 0x10371f +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_ADDR, HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_RMSK) +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_ADDR, m) +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_ADDR,v) +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_ADDR,m,v,HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_IN) +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_MODE_BMSK 0x3000 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_MODE_SHFT 0xc +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000c014) +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c014) +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c014) +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_M_RMSK 0xff +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_M_ATTR 0x3 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_M_IN \ + in_dword_masked(HWIO_GCC_BLSP1_QUP1_SPI_APPS_M_ADDR, HWIO_GCC_BLSP1_QUP1_SPI_APPS_M_RMSK) +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_M_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_QUP1_SPI_APPS_M_ADDR, m) +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_M_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_QUP1_SPI_APPS_M_ADDR,v) +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_M_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_QUP1_SPI_APPS_M_ADDR,m,v,HWIO_GCC_BLSP1_QUP1_SPI_APPS_M_IN) +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_M_M_BMSK 0xff +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_M_M_SHFT 0x0 + +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000c018) +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c018) +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c018) +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_N_RMSK 0xff +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_N_ATTR 0x3 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_N_IN \ + in_dword_masked(HWIO_GCC_BLSP1_QUP1_SPI_APPS_N_ADDR, HWIO_GCC_BLSP1_QUP1_SPI_APPS_N_RMSK) +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_N_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_QUP1_SPI_APPS_N_ADDR, m) +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_N_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_QUP1_SPI_APPS_N_ADDR,v) +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_N_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_QUP1_SPI_APPS_N_ADDR,m,v,HWIO_GCC_BLSP1_QUP1_SPI_APPS_N_IN) +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_N_NOT_N_MINUS_M_BMSK 0xff +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_N_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000c01c) +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c01c) +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c01c) +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_D_RMSK 0xff +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_D_ATTR 0x3 +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_D_IN \ + in_dword_masked(HWIO_GCC_BLSP1_QUP1_SPI_APPS_D_ADDR, HWIO_GCC_BLSP1_QUP1_SPI_APPS_D_RMSK) +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_D_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_QUP1_SPI_APPS_D_ADDR, m) +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_D_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_QUP1_SPI_APPS_D_ADDR,v) +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_D_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_QUP1_SPI_APPS_D_ADDR,m,v,HWIO_GCC_BLSP1_QUP1_SPI_APPS_D_IN) +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_D_NOT_2D_BMSK 0xff +#define HWIO_GCC_BLSP1_QUP1_SPI_APPS_D_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000c024) +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c024) +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c024) +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR_RMSK 0x800000f3 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR_ADDR, HWIO_GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR_RMSK) +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR_ADDR, m) +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR_ADDR,v) +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR_ADDR,m,v,HWIO_GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR_IN) +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR_DIRTY_D_BMSK 0x80 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR_DIRTY_D_SHFT 0x7 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR_DIRTY_N_BMSK 0x40 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR_DIRTY_N_SHFT 0x6 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR_DIRTY_M_BMSK 0x20 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR_DIRTY_M_SHFT 0x5 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000c028) +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c028) +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c028) +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_RMSK 0x10371f +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_ADDR, HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_RMSK) +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_ADDR, m) +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_ADDR,v) +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_ADDR,m,v,HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_IN) +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_MODE_BMSK 0x3000 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_MODE_SHFT 0xc +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000c02c) +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c02c) +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c02c) +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_M_RMSK 0xff +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_M_ATTR 0x3 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_M_IN \ + in_dword_masked(HWIO_GCC_BLSP1_QUP1_I2C_APPS_M_ADDR, HWIO_GCC_BLSP1_QUP1_I2C_APPS_M_RMSK) +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_M_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_QUP1_I2C_APPS_M_ADDR, m) +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_M_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_QUP1_I2C_APPS_M_ADDR,v) +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_M_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_QUP1_I2C_APPS_M_ADDR,m,v,HWIO_GCC_BLSP1_QUP1_I2C_APPS_M_IN) +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_M_M_BMSK 0xff +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_M_M_SHFT 0x0 + +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000c030) +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c030) +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c030) +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_N_RMSK 0xff +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_N_ATTR 0x3 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_N_IN \ + in_dword_masked(HWIO_GCC_BLSP1_QUP1_I2C_APPS_N_ADDR, HWIO_GCC_BLSP1_QUP1_I2C_APPS_N_RMSK) +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_N_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_QUP1_I2C_APPS_N_ADDR, m) +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_N_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_QUP1_I2C_APPS_N_ADDR,v) +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_N_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_QUP1_I2C_APPS_N_ADDR,m,v,HWIO_GCC_BLSP1_QUP1_I2C_APPS_N_IN) +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_N_NOT_N_MINUS_M_BMSK 0xff +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_N_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000c034) +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c034) +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c034) +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_D_RMSK 0xff +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_D_ATTR 0x3 +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_D_IN \ + in_dword_masked(HWIO_GCC_BLSP1_QUP1_I2C_APPS_D_ADDR, HWIO_GCC_BLSP1_QUP1_I2C_APPS_D_RMSK) +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_D_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_QUP1_I2C_APPS_D_ADDR, m) +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_D_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_QUP1_I2C_APPS_D_ADDR,v) +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_D_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_QUP1_I2C_APPS_D_ADDR,m,v,HWIO_GCC_BLSP1_QUP1_I2C_APPS_D_IN) +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_D_NOT_2D_BMSK 0xff +#define HWIO_GCC_BLSP1_QUP1_I2C_APPS_D_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_BLSP1_UART1_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000d000) +#define HWIO_GCC_BLSP1_UART1_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000d000) +#define HWIO_GCC_BLSP1_UART1_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000d000) +#define HWIO_GCC_BLSP1_UART1_BCR_RMSK 0x1 +#define HWIO_GCC_BLSP1_UART1_BCR_ATTR 0x3 +#define HWIO_GCC_BLSP1_UART1_BCR_IN \ + in_dword_masked(HWIO_GCC_BLSP1_UART1_BCR_ADDR, HWIO_GCC_BLSP1_UART1_BCR_RMSK) +#define HWIO_GCC_BLSP1_UART1_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_UART1_BCR_ADDR, m) +#define HWIO_GCC_BLSP1_UART1_BCR_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_UART1_BCR_ADDR,v) +#define HWIO_GCC_BLSP1_UART1_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_UART1_BCR_ADDR,m,v,HWIO_GCC_BLSP1_UART1_BCR_IN) +#define HWIO_GCC_BLSP1_UART1_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_BLSP1_UART1_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_BLSP1_UART1_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_UART1_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_BLSP1_UART1_APPS_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000d004) +#define HWIO_GCC_BLSP1_UART1_APPS_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000d004) +#define HWIO_GCC_BLSP1_UART1_APPS_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000d004) +#define HWIO_GCC_BLSP1_UART1_APPS_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_BLSP1_UART1_APPS_CBCR_ATTR 0x3 +#define HWIO_GCC_BLSP1_UART1_APPS_CBCR_IN \ + in_dword_masked(HWIO_GCC_BLSP1_UART1_APPS_CBCR_ADDR, HWIO_GCC_BLSP1_UART1_APPS_CBCR_RMSK) +#define HWIO_GCC_BLSP1_UART1_APPS_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_UART1_APPS_CBCR_ADDR, m) +#define HWIO_GCC_BLSP1_UART1_APPS_CBCR_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_UART1_APPS_CBCR_ADDR,v) +#define HWIO_GCC_BLSP1_UART1_APPS_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_UART1_APPS_CBCR_ADDR,m,v,HWIO_GCC_BLSP1_UART1_APPS_CBCR_IN) +#define HWIO_GCC_BLSP1_UART1_APPS_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_BLSP1_UART1_APPS_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_BLSP1_UART1_APPS_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_BLSP1_UART1_APPS_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_BLSP1_UART1_APPS_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_BLSP1_UART1_APPS_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_BLSP1_UART1_APPS_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_BLSP1_UART1_APPS_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_BLSP1_UART1_APPS_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_BLSP1_UART1_APPS_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_BLSP1_UART1_APPS_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_BLSP1_UART1_APPS_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_BLSP1_UART1_APPS_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_BLSP1_UART1_APPS_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_BLSP1_UART1_APPS_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_UART1_APPS_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_BLSP1_UART1_SIM_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000d008) +#define HWIO_GCC_BLSP1_UART1_SIM_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000d008) +#define HWIO_GCC_BLSP1_UART1_SIM_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000d008) +#define HWIO_GCC_BLSP1_UART1_SIM_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_BLSP1_UART1_SIM_CBCR_ATTR 0x3 +#define HWIO_GCC_BLSP1_UART1_SIM_CBCR_IN \ + in_dword_masked(HWIO_GCC_BLSP1_UART1_SIM_CBCR_ADDR, HWIO_GCC_BLSP1_UART1_SIM_CBCR_RMSK) +#define HWIO_GCC_BLSP1_UART1_SIM_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_UART1_SIM_CBCR_ADDR, m) +#define HWIO_GCC_BLSP1_UART1_SIM_CBCR_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_UART1_SIM_CBCR_ADDR,v) +#define HWIO_GCC_BLSP1_UART1_SIM_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_UART1_SIM_CBCR_ADDR,m,v,HWIO_GCC_BLSP1_UART1_SIM_CBCR_IN) +#define HWIO_GCC_BLSP1_UART1_SIM_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_BLSP1_UART1_SIM_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_BLSP1_UART1_SIM_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_BLSP1_UART1_SIM_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_BLSP1_UART1_SIM_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_BLSP1_UART1_SIM_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_BLSP1_UART1_SIM_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_BLSP1_UART1_SIM_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_BLSP1_UART1_SIM_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_BLSP1_UART1_SIM_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_BLSP1_UART1_SIM_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_BLSP1_UART1_SIM_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_BLSP1_UART1_SIM_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_BLSP1_UART1_SIM_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_BLSP1_UART1_SIM_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_UART1_SIM_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_BLSP1_UART1_APPS_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000d00c) +#define HWIO_GCC_BLSP1_UART1_APPS_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000d00c) +#define HWIO_GCC_BLSP1_UART1_APPS_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000d00c) +#define HWIO_GCC_BLSP1_UART1_APPS_CMD_RCGR_RMSK 0x800000f3 +#define HWIO_GCC_BLSP1_UART1_APPS_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_BLSP1_UART1_APPS_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_BLSP1_UART1_APPS_CMD_RCGR_ADDR, HWIO_GCC_BLSP1_UART1_APPS_CMD_RCGR_RMSK) +#define HWIO_GCC_BLSP1_UART1_APPS_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_UART1_APPS_CMD_RCGR_ADDR, m) +#define HWIO_GCC_BLSP1_UART1_APPS_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_UART1_APPS_CMD_RCGR_ADDR,v) +#define HWIO_GCC_BLSP1_UART1_APPS_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_UART1_APPS_CMD_RCGR_ADDR,m,v,HWIO_GCC_BLSP1_UART1_APPS_CMD_RCGR_IN) +#define HWIO_GCC_BLSP1_UART1_APPS_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_BLSP1_UART1_APPS_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_BLSP1_UART1_APPS_CMD_RCGR_DIRTY_D_BMSK 0x80 +#define HWIO_GCC_BLSP1_UART1_APPS_CMD_RCGR_DIRTY_D_SHFT 0x7 +#define HWIO_GCC_BLSP1_UART1_APPS_CMD_RCGR_DIRTY_N_BMSK 0x40 +#define HWIO_GCC_BLSP1_UART1_APPS_CMD_RCGR_DIRTY_N_SHFT 0x6 +#define HWIO_GCC_BLSP1_UART1_APPS_CMD_RCGR_DIRTY_M_BMSK 0x20 +#define HWIO_GCC_BLSP1_UART1_APPS_CMD_RCGR_DIRTY_M_SHFT 0x5 +#define HWIO_GCC_BLSP1_UART1_APPS_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_BLSP1_UART1_APPS_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_BLSP1_UART1_APPS_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_BLSP1_UART1_APPS_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_BLSP1_UART1_APPS_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_UART1_APPS_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_BLSP1_UART1_APPS_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_BLSP1_UART1_APPS_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_BLSP1_UART1_APPS_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_UART1_APPS_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000d010) +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000d010) +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000d010) +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_RMSK 0x10371f +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_ADDR, HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_RMSK) +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_ADDR, m) +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_ADDR,v) +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_ADDR,m,v,HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_IN) +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_MODE_BMSK 0x3000 +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_MODE_SHFT 0xc +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_BLSP1_UART1_APPS_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_BLSP1_UART1_APPS_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000d014) +#define HWIO_GCC_BLSP1_UART1_APPS_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000d014) +#define HWIO_GCC_BLSP1_UART1_APPS_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000d014) +#define HWIO_GCC_BLSP1_UART1_APPS_M_RMSK 0xffff +#define HWIO_GCC_BLSP1_UART1_APPS_M_ATTR 0x3 +#define HWIO_GCC_BLSP1_UART1_APPS_M_IN \ + in_dword_masked(HWIO_GCC_BLSP1_UART1_APPS_M_ADDR, HWIO_GCC_BLSP1_UART1_APPS_M_RMSK) +#define HWIO_GCC_BLSP1_UART1_APPS_M_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_UART1_APPS_M_ADDR, m) +#define HWIO_GCC_BLSP1_UART1_APPS_M_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_UART1_APPS_M_ADDR,v) +#define HWIO_GCC_BLSP1_UART1_APPS_M_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_UART1_APPS_M_ADDR,m,v,HWIO_GCC_BLSP1_UART1_APPS_M_IN) +#define HWIO_GCC_BLSP1_UART1_APPS_M_M_BMSK 0xffff +#define HWIO_GCC_BLSP1_UART1_APPS_M_M_SHFT 0x0 + +#define HWIO_GCC_BLSP1_UART1_APPS_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000d018) +#define HWIO_GCC_BLSP1_UART1_APPS_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000d018) +#define HWIO_GCC_BLSP1_UART1_APPS_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000d018) +#define HWIO_GCC_BLSP1_UART1_APPS_N_RMSK 0xffff +#define HWIO_GCC_BLSP1_UART1_APPS_N_ATTR 0x3 +#define HWIO_GCC_BLSP1_UART1_APPS_N_IN \ + in_dword_masked(HWIO_GCC_BLSP1_UART1_APPS_N_ADDR, HWIO_GCC_BLSP1_UART1_APPS_N_RMSK) +#define HWIO_GCC_BLSP1_UART1_APPS_N_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_UART1_APPS_N_ADDR, m) +#define HWIO_GCC_BLSP1_UART1_APPS_N_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_UART1_APPS_N_ADDR,v) +#define HWIO_GCC_BLSP1_UART1_APPS_N_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_UART1_APPS_N_ADDR,m,v,HWIO_GCC_BLSP1_UART1_APPS_N_IN) +#define HWIO_GCC_BLSP1_UART1_APPS_N_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_BLSP1_UART1_APPS_N_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_BLSP1_UART1_APPS_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000d01c) +#define HWIO_GCC_BLSP1_UART1_APPS_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000d01c) +#define HWIO_GCC_BLSP1_UART1_APPS_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000d01c) +#define HWIO_GCC_BLSP1_UART1_APPS_D_RMSK 0xffff +#define HWIO_GCC_BLSP1_UART1_APPS_D_ATTR 0x3 +#define HWIO_GCC_BLSP1_UART1_APPS_D_IN \ + in_dword_masked(HWIO_GCC_BLSP1_UART1_APPS_D_ADDR, HWIO_GCC_BLSP1_UART1_APPS_D_RMSK) +#define HWIO_GCC_BLSP1_UART1_APPS_D_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_UART1_APPS_D_ADDR, m) +#define HWIO_GCC_BLSP1_UART1_APPS_D_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_UART1_APPS_D_ADDR,v) +#define HWIO_GCC_BLSP1_UART1_APPS_D_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_UART1_APPS_D_ADDR,m,v,HWIO_GCC_BLSP1_UART1_APPS_D_IN) +#define HWIO_GCC_BLSP1_UART1_APPS_D_NOT_2D_BMSK 0xffff +#define HWIO_GCC_BLSP1_UART1_APPS_D_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_BLSP1_QUP2_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e000) +#define HWIO_GCC_BLSP1_QUP2_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e000) +#define HWIO_GCC_BLSP1_QUP2_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e000) +#define HWIO_GCC_BLSP1_QUP2_BCR_RMSK 0x1 +#define HWIO_GCC_BLSP1_QUP2_BCR_ATTR 0x3 +#define HWIO_GCC_BLSP1_QUP2_BCR_IN \ + in_dword_masked(HWIO_GCC_BLSP1_QUP2_BCR_ADDR, HWIO_GCC_BLSP1_QUP2_BCR_RMSK) +#define HWIO_GCC_BLSP1_QUP2_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_QUP2_BCR_ADDR, m) +#define HWIO_GCC_BLSP1_QUP2_BCR_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_QUP2_BCR_ADDR,v) +#define HWIO_GCC_BLSP1_QUP2_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_QUP2_BCR_ADDR,m,v,HWIO_GCC_BLSP1_QUP2_BCR_IN) +#define HWIO_GCC_BLSP1_QUP2_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_BLSP1_QUP2_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_BLSP1_QUP2_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP2_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e004) +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e004) +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e004) +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CBCR_ATTR 0x3 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CBCR_IN \ + in_dword_masked(HWIO_GCC_BLSP1_QUP2_SPI_APPS_CBCR_ADDR, HWIO_GCC_BLSP1_QUP2_SPI_APPS_CBCR_RMSK) +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_QUP2_SPI_APPS_CBCR_ADDR, m) +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CBCR_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_QUP2_SPI_APPS_CBCR_ADDR,v) +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_QUP2_SPI_APPS_CBCR_ADDR,m,v,HWIO_GCC_BLSP1_QUP2_SPI_APPS_CBCR_IN) +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e008) +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e008) +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e008) +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CBCR_ATTR 0x3 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CBCR_IN \ + in_dword_masked(HWIO_GCC_BLSP1_QUP2_I2C_APPS_CBCR_ADDR, HWIO_GCC_BLSP1_QUP2_I2C_APPS_CBCR_RMSK) +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_QUP2_I2C_APPS_CBCR_ADDR, m) +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CBCR_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_QUP2_I2C_APPS_CBCR_ADDR,v) +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_QUP2_I2C_APPS_CBCR_ADDR,m,v,HWIO_GCC_BLSP1_QUP2_I2C_APPS_CBCR_IN) +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e00c) +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e00c) +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e00c) +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CMD_RCGR_RMSK 0x800000f3 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_BLSP1_QUP2_SPI_APPS_CMD_RCGR_ADDR, HWIO_GCC_BLSP1_QUP2_SPI_APPS_CMD_RCGR_RMSK) +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_QUP2_SPI_APPS_CMD_RCGR_ADDR, m) +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_QUP2_SPI_APPS_CMD_RCGR_ADDR,v) +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_QUP2_SPI_APPS_CMD_RCGR_ADDR,m,v,HWIO_GCC_BLSP1_QUP2_SPI_APPS_CMD_RCGR_IN) +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CMD_RCGR_DIRTY_D_BMSK 0x80 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CMD_RCGR_DIRTY_D_SHFT 0x7 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CMD_RCGR_DIRTY_N_BMSK 0x40 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CMD_RCGR_DIRTY_N_SHFT 0x6 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CMD_RCGR_DIRTY_M_BMSK 0x20 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CMD_RCGR_DIRTY_M_SHFT 0x5 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e010) +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e010) +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e010) +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_RMSK 0x10371f +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_ADDR, HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_RMSK) +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_ADDR, m) +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_ADDR,v) +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_ADDR,m,v,HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_IN) +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_MODE_BMSK 0x3000 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_MODE_SHFT 0xc +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e014) +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e014) +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e014) +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_M_RMSK 0xff +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_M_ATTR 0x3 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_M_IN \ + in_dword_masked(HWIO_GCC_BLSP1_QUP2_SPI_APPS_M_ADDR, HWIO_GCC_BLSP1_QUP2_SPI_APPS_M_RMSK) +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_M_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_QUP2_SPI_APPS_M_ADDR, m) +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_M_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_QUP2_SPI_APPS_M_ADDR,v) +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_M_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_QUP2_SPI_APPS_M_ADDR,m,v,HWIO_GCC_BLSP1_QUP2_SPI_APPS_M_IN) +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_M_M_BMSK 0xff +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_M_M_SHFT 0x0 + +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e018) +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e018) +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e018) +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_N_RMSK 0xff +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_N_ATTR 0x3 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_N_IN \ + in_dword_masked(HWIO_GCC_BLSP1_QUP2_SPI_APPS_N_ADDR, HWIO_GCC_BLSP1_QUP2_SPI_APPS_N_RMSK) +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_N_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_QUP2_SPI_APPS_N_ADDR, m) +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_N_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_QUP2_SPI_APPS_N_ADDR,v) +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_N_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_QUP2_SPI_APPS_N_ADDR,m,v,HWIO_GCC_BLSP1_QUP2_SPI_APPS_N_IN) +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_N_NOT_N_MINUS_M_BMSK 0xff +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_N_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e01c) +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e01c) +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e01c) +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_D_RMSK 0xff +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_D_ATTR 0x3 +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_D_IN \ + in_dword_masked(HWIO_GCC_BLSP1_QUP2_SPI_APPS_D_ADDR, HWIO_GCC_BLSP1_QUP2_SPI_APPS_D_RMSK) +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_D_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_QUP2_SPI_APPS_D_ADDR, m) +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_D_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_QUP2_SPI_APPS_D_ADDR,v) +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_D_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_QUP2_SPI_APPS_D_ADDR,m,v,HWIO_GCC_BLSP1_QUP2_SPI_APPS_D_IN) +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_D_NOT_2D_BMSK 0xff +#define HWIO_GCC_BLSP1_QUP2_SPI_APPS_D_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e024) +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e024) +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e024) +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CMD_RCGR_RMSK 0x800000f3 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_BLSP1_QUP2_I2C_APPS_CMD_RCGR_ADDR, HWIO_GCC_BLSP1_QUP2_I2C_APPS_CMD_RCGR_RMSK) +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_QUP2_I2C_APPS_CMD_RCGR_ADDR, m) +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_QUP2_I2C_APPS_CMD_RCGR_ADDR,v) +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_QUP2_I2C_APPS_CMD_RCGR_ADDR,m,v,HWIO_GCC_BLSP1_QUP2_I2C_APPS_CMD_RCGR_IN) +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CMD_RCGR_DIRTY_D_BMSK 0x80 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CMD_RCGR_DIRTY_D_SHFT 0x7 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CMD_RCGR_DIRTY_N_BMSK 0x40 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CMD_RCGR_DIRTY_N_SHFT 0x6 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CMD_RCGR_DIRTY_M_BMSK 0x20 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CMD_RCGR_DIRTY_M_SHFT 0x5 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e028) +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e028) +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e028) +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_RMSK 0x10371f +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_ADDR, HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_RMSK) +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_ADDR, m) +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_ADDR,v) +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_ADDR,m,v,HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_IN) +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_MODE_BMSK 0x3000 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_MODE_SHFT 0xc +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e02c) +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e02c) +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e02c) +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_M_RMSK 0xff +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_M_ATTR 0x3 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_M_IN \ + in_dword_masked(HWIO_GCC_BLSP1_QUP2_I2C_APPS_M_ADDR, HWIO_GCC_BLSP1_QUP2_I2C_APPS_M_RMSK) +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_M_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_QUP2_I2C_APPS_M_ADDR, m) +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_M_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_QUP2_I2C_APPS_M_ADDR,v) +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_M_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_QUP2_I2C_APPS_M_ADDR,m,v,HWIO_GCC_BLSP1_QUP2_I2C_APPS_M_IN) +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_M_M_BMSK 0xff +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_M_M_SHFT 0x0 + +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e030) +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e030) +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e030) +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_N_RMSK 0xff +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_N_ATTR 0x3 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_N_IN \ + in_dword_masked(HWIO_GCC_BLSP1_QUP2_I2C_APPS_N_ADDR, HWIO_GCC_BLSP1_QUP2_I2C_APPS_N_RMSK) +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_N_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_QUP2_I2C_APPS_N_ADDR, m) +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_N_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_QUP2_I2C_APPS_N_ADDR,v) +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_N_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_QUP2_I2C_APPS_N_ADDR,m,v,HWIO_GCC_BLSP1_QUP2_I2C_APPS_N_IN) +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_N_NOT_N_MINUS_M_BMSK 0xff +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_N_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e034) +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e034) +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e034) +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_D_RMSK 0xff +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_D_ATTR 0x3 +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_D_IN \ + in_dword_masked(HWIO_GCC_BLSP1_QUP2_I2C_APPS_D_ADDR, HWIO_GCC_BLSP1_QUP2_I2C_APPS_D_RMSK) +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_D_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_QUP2_I2C_APPS_D_ADDR, m) +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_D_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_QUP2_I2C_APPS_D_ADDR,v) +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_D_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_QUP2_I2C_APPS_D_ADDR,m,v,HWIO_GCC_BLSP1_QUP2_I2C_APPS_D_IN) +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_D_NOT_2D_BMSK 0xff +#define HWIO_GCC_BLSP1_QUP2_I2C_APPS_D_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_BLSP1_UART2_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f000) +#define HWIO_GCC_BLSP1_UART2_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f000) +#define HWIO_GCC_BLSP1_UART2_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f000) +#define HWIO_GCC_BLSP1_UART2_BCR_RMSK 0x1 +#define HWIO_GCC_BLSP1_UART2_BCR_ATTR 0x3 +#define HWIO_GCC_BLSP1_UART2_BCR_IN \ + in_dword_masked(HWIO_GCC_BLSP1_UART2_BCR_ADDR, HWIO_GCC_BLSP1_UART2_BCR_RMSK) +#define HWIO_GCC_BLSP1_UART2_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_UART2_BCR_ADDR, m) +#define HWIO_GCC_BLSP1_UART2_BCR_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_UART2_BCR_ADDR,v) +#define HWIO_GCC_BLSP1_UART2_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_UART2_BCR_ADDR,m,v,HWIO_GCC_BLSP1_UART2_BCR_IN) +#define HWIO_GCC_BLSP1_UART2_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_BLSP1_UART2_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_BLSP1_UART2_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_UART2_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_BLSP1_UART2_APPS_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f004) +#define HWIO_GCC_BLSP1_UART2_APPS_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f004) +#define HWIO_GCC_BLSP1_UART2_APPS_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f004) +#define HWIO_GCC_BLSP1_UART2_APPS_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_BLSP1_UART2_APPS_CBCR_ATTR 0x3 +#define HWIO_GCC_BLSP1_UART2_APPS_CBCR_IN \ + in_dword_masked(HWIO_GCC_BLSP1_UART2_APPS_CBCR_ADDR, HWIO_GCC_BLSP1_UART2_APPS_CBCR_RMSK) +#define HWIO_GCC_BLSP1_UART2_APPS_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_UART2_APPS_CBCR_ADDR, m) +#define HWIO_GCC_BLSP1_UART2_APPS_CBCR_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_UART2_APPS_CBCR_ADDR,v) +#define HWIO_GCC_BLSP1_UART2_APPS_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_UART2_APPS_CBCR_ADDR,m,v,HWIO_GCC_BLSP1_UART2_APPS_CBCR_IN) +#define HWIO_GCC_BLSP1_UART2_APPS_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_BLSP1_UART2_APPS_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_BLSP1_UART2_APPS_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_BLSP1_UART2_APPS_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_BLSP1_UART2_APPS_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_BLSP1_UART2_APPS_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_BLSP1_UART2_APPS_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_BLSP1_UART2_APPS_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_BLSP1_UART2_APPS_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_BLSP1_UART2_APPS_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_BLSP1_UART2_APPS_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_BLSP1_UART2_APPS_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_BLSP1_UART2_APPS_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_BLSP1_UART2_APPS_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_BLSP1_UART2_APPS_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_UART2_APPS_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_BLSP1_UART2_SIM_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f008) +#define HWIO_GCC_BLSP1_UART2_SIM_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f008) +#define HWIO_GCC_BLSP1_UART2_SIM_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f008) +#define HWIO_GCC_BLSP1_UART2_SIM_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_BLSP1_UART2_SIM_CBCR_ATTR 0x3 +#define HWIO_GCC_BLSP1_UART2_SIM_CBCR_IN \ + in_dword_masked(HWIO_GCC_BLSP1_UART2_SIM_CBCR_ADDR, HWIO_GCC_BLSP1_UART2_SIM_CBCR_RMSK) +#define HWIO_GCC_BLSP1_UART2_SIM_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_UART2_SIM_CBCR_ADDR, m) +#define HWIO_GCC_BLSP1_UART2_SIM_CBCR_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_UART2_SIM_CBCR_ADDR,v) +#define HWIO_GCC_BLSP1_UART2_SIM_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_UART2_SIM_CBCR_ADDR,m,v,HWIO_GCC_BLSP1_UART2_SIM_CBCR_IN) +#define HWIO_GCC_BLSP1_UART2_SIM_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_BLSP1_UART2_SIM_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_BLSP1_UART2_SIM_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_BLSP1_UART2_SIM_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_BLSP1_UART2_SIM_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_BLSP1_UART2_SIM_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_BLSP1_UART2_SIM_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_BLSP1_UART2_SIM_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_BLSP1_UART2_SIM_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_BLSP1_UART2_SIM_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_BLSP1_UART2_SIM_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_BLSP1_UART2_SIM_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_BLSP1_UART2_SIM_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_BLSP1_UART2_SIM_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_BLSP1_UART2_SIM_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_UART2_SIM_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_BLSP1_UART2_APPS_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f00c) +#define HWIO_GCC_BLSP1_UART2_APPS_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f00c) +#define HWIO_GCC_BLSP1_UART2_APPS_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f00c) +#define HWIO_GCC_BLSP1_UART2_APPS_CMD_RCGR_RMSK 0x800000f3 +#define HWIO_GCC_BLSP1_UART2_APPS_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_BLSP1_UART2_APPS_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_BLSP1_UART2_APPS_CMD_RCGR_ADDR, HWIO_GCC_BLSP1_UART2_APPS_CMD_RCGR_RMSK) +#define HWIO_GCC_BLSP1_UART2_APPS_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_UART2_APPS_CMD_RCGR_ADDR, m) +#define HWIO_GCC_BLSP1_UART2_APPS_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_UART2_APPS_CMD_RCGR_ADDR,v) +#define HWIO_GCC_BLSP1_UART2_APPS_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_UART2_APPS_CMD_RCGR_ADDR,m,v,HWIO_GCC_BLSP1_UART2_APPS_CMD_RCGR_IN) +#define HWIO_GCC_BLSP1_UART2_APPS_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_BLSP1_UART2_APPS_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_BLSP1_UART2_APPS_CMD_RCGR_DIRTY_D_BMSK 0x80 +#define HWIO_GCC_BLSP1_UART2_APPS_CMD_RCGR_DIRTY_D_SHFT 0x7 +#define HWIO_GCC_BLSP1_UART2_APPS_CMD_RCGR_DIRTY_N_BMSK 0x40 +#define HWIO_GCC_BLSP1_UART2_APPS_CMD_RCGR_DIRTY_N_SHFT 0x6 +#define HWIO_GCC_BLSP1_UART2_APPS_CMD_RCGR_DIRTY_M_BMSK 0x20 +#define HWIO_GCC_BLSP1_UART2_APPS_CMD_RCGR_DIRTY_M_SHFT 0x5 +#define HWIO_GCC_BLSP1_UART2_APPS_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_BLSP1_UART2_APPS_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_BLSP1_UART2_APPS_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_BLSP1_UART2_APPS_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_BLSP1_UART2_APPS_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_UART2_APPS_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_BLSP1_UART2_APPS_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_BLSP1_UART2_APPS_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_BLSP1_UART2_APPS_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_UART2_APPS_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f010) +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f010) +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f010) +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_RMSK 0x10371f +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_ADDR, HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_RMSK) +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_ADDR, m) +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_ADDR,v) +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_ADDR,m,v,HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_IN) +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_MODE_BMSK 0x3000 +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_MODE_SHFT 0xc +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_BLSP1_UART2_APPS_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_BLSP1_UART2_APPS_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f014) +#define HWIO_GCC_BLSP1_UART2_APPS_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f014) +#define HWIO_GCC_BLSP1_UART2_APPS_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f014) +#define HWIO_GCC_BLSP1_UART2_APPS_M_RMSK 0xffff +#define HWIO_GCC_BLSP1_UART2_APPS_M_ATTR 0x3 +#define HWIO_GCC_BLSP1_UART2_APPS_M_IN \ + in_dword_masked(HWIO_GCC_BLSP1_UART2_APPS_M_ADDR, HWIO_GCC_BLSP1_UART2_APPS_M_RMSK) +#define HWIO_GCC_BLSP1_UART2_APPS_M_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_UART2_APPS_M_ADDR, m) +#define HWIO_GCC_BLSP1_UART2_APPS_M_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_UART2_APPS_M_ADDR,v) +#define HWIO_GCC_BLSP1_UART2_APPS_M_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_UART2_APPS_M_ADDR,m,v,HWIO_GCC_BLSP1_UART2_APPS_M_IN) +#define HWIO_GCC_BLSP1_UART2_APPS_M_M_BMSK 0xffff +#define HWIO_GCC_BLSP1_UART2_APPS_M_M_SHFT 0x0 + +#define HWIO_GCC_BLSP1_UART2_APPS_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f018) +#define HWIO_GCC_BLSP1_UART2_APPS_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f018) +#define HWIO_GCC_BLSP1_UART2_APPS_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f018) +#define HWIO_GCC_BLSP1_UART2_APPS_N_RMSK 0xffff +#define HWIO_GCC_BLSP1_UART2_APPS_N_ATTR 0x3 +#define HWIO_GCC_BLSP1_UART2_APPS_N_IN \ + in_dword_masked(HWIO_GCC_BLSP1_UART2_APPS_N_ADDR, HWIO_GCC_BLSP1_UART2_APPS_N_RMSK) +#define HWIO_GCC_BLSP1_UART2_APPS_N_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_UART2_APPS_N_ADDR, m) +#define HWIO_GCC_BLSP1_UART2_APPS_N_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_UART2_APPS_N_ADDR,v) +#define HWIO_GCC_BLSP1_UART2_APPS_N_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_UART2_APPS_N_ADDR,m,v,HWIO_GCC_BLSP1_UART2_APPS_N_IN) +#define HWIO_GCC_BLSP1_UART2_APPS_N_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_BLSP1_UART2_APPS_N_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_BLSP1_UART2_APPS_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f01c) +#define HWIO_GCC_BLSP1_UART2_APPS_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f01c) +#define HWIO_GCC_BLSP1_UART2_APPS_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f01c) +#define HWIO_GCC_BLSP1_UART2_APPS_D_RMSK 0xffff +#define HWIO_GCC_BLSP1_UART2_APPS_D_ATTR 0x3 +#define HWIO_GCC_BLSP1_UART2_APPS_D_IN \ + in_dword_masked(HWIO_GCC_BLSP1_UART2_APPS_D_ADDR, HWIO_GCC_BLSP1_UART2_APPS_D_RMSK) +#define HWIO_GCC_BLSP1_UART2_APPS_D_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_UART2_APPS_D_ADDR, m) +#define HWIO_GCC_BLSP1_UART2_APPS_D_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_UART2_APPS_D_ADDR,v) +#define HWIO_GCC_BLSP1_UART2_APPS_D_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_UART2_APPS_D_ADDR,m,v,HWIO_GCC_BLSP1_UART2_APPS_D_IN) +#define HWIO_GCC_BLSP1_UART2_APPS_D_NOT_2D_BMSK 0xffff +#define HWIO_GCC_BLSP1_UART2_APPS_D_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_BLSP1_QUP3_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00010000) +#define HWIO_GCC_BLSP1_QUP3_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00010000) +#define HWIO_GCC_BLSP1_QUP3_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00010000) +#define HWIO_GCC_BLSP1_QUP3_BCR_RMSK 0x1 +#define HWIO_GCC_BLSP1_QUP3_BCR_ATTR 0x3 +#define HWIO_GCC_BLSP1_QUP3_BCR_IN \ + in_dword_masked(HWIO_GCC_BLSP1_QUP3_BCR_ADDR, HWIO_GCC_BLSP1_QUP3_BCR_RMSK) +#define HWIO_GCC_BLSP1_QUP3_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_QUP3_BCR_ADDR, m) +#define HWIO_GCC_BLSP1_QUP3_BCR_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_QUP3_BCR_ADDR,v) +#define HWIO_GCC_BLSP1_QUP3_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_QUP3_BCR_ADDR,m,v,HWIO_GCC_BLSP1_QUP3_BCR_IN) +#define HWIO_GCC_BLSP1_QUP3_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_BLSP1_QUP3_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_BLSP1_QUP3_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP3_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00010004) +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00010004) +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00010004) +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CBCR_ATTR 0x3 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CBCR_IN \ + in_dword_masked(HWIO_GCC_BLSP1_QUP3_SPI_APPS_CBCR_ADDR, HWIO_GCC_BLSP1_QUP3_SPI_APPS_CBCR_RMSK) +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_QUP3_SPI_APPS_CBCR_ADDR, m) +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CBCR_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_QUP3_SPI_APPS_CBCR_ADDR,v) +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_QUP3_SPI_APPS_CBCR_ADDR,m,v,HWIO_GCC_BLSP1_QUP3_SPI_APPS_CBCR_IN) +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00010008) +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00010008) +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00010008) +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CBCR_ATTR 0x3 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CBCR_IN \ + in_dword_masked(HWIO_GCC_BLSP1_QUP3_I2C_APPS_CBCR_ADDR, HWIO_GCC_BLSP1_QUP3_I2C_APPS_CBCR_RMSK) +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_QUP3_I2C_APPS_CBCR_ADDR, m) +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CBCR_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_QUP3_I2C_APPS_CBCR_ADDR,v) +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_QUP3_I2C_APPS_CBCR_ADDR,m,v,HWIO_GCC_BLSP1_QUP3_I2C_APPS_CBCR_IN) +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001000c) +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001000c) +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001000c) +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CMD_RCGR_RMSK 0x800000f3 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_BLSP1_QUP3_SPI_APPS_CMD_RCGR_ADDR, HWIO_GCC_BLSP1_QUP3_SPI_APPS_CMD_RCGR_RMSK) +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_QUP3_SPI_APPS_CMD_RCGR_ADDR, m) +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_QUP3_SPI_APPS_CMD_RCGR_ADDR,v) +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_QUP3_SPI_APPS_CMD_RCGR_ADDR,m,v,HWIO_GCC_BLSP1_QUP3_SPI_APPS_CMD_RCGR_IN) +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CMD_RCGR_DIRTY_D_BMSK 0x80 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CMD_RCGR_DIRTY_D_SHFT 0x7 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CMD_RCGR_DIRTY_N_BMSK 0x40 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CMD_RCGR_DIRTY_N_SHFT 0x6 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CMD_RCGR_DIRTY_M_BMSK 0x20 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CMD_RCGR_DIRTY_M_SHFT 0x5 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00010010) +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00010010) +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00010010) +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_RMSK 0x10371f +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_ADDR, HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_RMSK) +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_ADDR, m) +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_ADDR,v) +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_ADDR,m,v,HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_IN) +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_MODE_BMSK 0x3000 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_MODE_SHFT 0xc +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00010014) +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00010014) +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00010014) +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_M_RMSK 0xff +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_M_ATTR 0x3 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_M_IN \ + in_dword_masked(HWIO_GCC_BLSP1_QUP3_SPI_APPS_M_ADDR, HWIO_GCC_BLSP1_QUP3_SPI_APPS_M_RMSK) +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_M_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_QUP3_SPI_APPS_M_ADDR, m) +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_M_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_QUP3_SPI_APPS_M_ADDR,v) +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_M_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_QUP3_SPI_APPS_M_ADDR,m,v,HWIO_GCC_BLSP1_QUP3_SPI_APPS_M_IN) +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_M_M_BMSK 0xff +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_M_M_SHFT 0x0 + +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00010018) +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00010018) +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00010018) +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_N_RMSK 0xff +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_N_ATTR 0x3 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_N_IN \ + in_dword_masked(HWIO_GCC_BLSP1_QUP3_SPI_APPS_N_ADDR, HWIO_GCC_BLSP1_QUP3_SPI_APPS_N_RMSK) +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_N_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_QUP3_SPI_APPS_N_ADDR, m) +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_N_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_QUP3_SPI_APPS_N_ADDR,v) +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_N_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_QUP3_SPI_APPS_N_ADDR,m,v,HWIO_GCC_BLSP1_QUP3_SPI_APPS_N_IN) +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_N_NOT_N_MINUS_M_BMSK 0xff +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_N_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001001c) +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001001c) +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001001c) +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_D_RMSK 0xff +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_D_ATTR 0x3 +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_D_IN \ + in_dword_masked(HWIO_GCC_BLSP1_QUP3_SPI_APPS_D_ADDR, HWIO_GCC_BLSP1_QUP3_SPI_APPS_D_RMSK) +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_D_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_QUP3_SPI_APPS_D_ADDR, m) +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_D_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_QUP3_SPI_APPS_D_ADDR,v) +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_D_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_QUP3_SPI_APPS_D_ADDR,m,v,HWIO_GCC_BLSP1_QUP3_SPI_APPS_D_IN) +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_D_NOT_2D_BMSK 0xff +#define HWIO_GCC_BLSP1_QUP3_SPI_APPS_D_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00010024) +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00010024) +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00010024) +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CMD_RCGR_RMSK 0x800000f3 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_BLSP1_QUP3_I2C_APPS_CMD_RCGR_ADDR, HWIO_GCC_BLSP1_QUP3_I2C_APPS_CMD_RCGR_RMSK) +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_QUP3_I2C_APPS_CMD_RCGR_ADDR, m) +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_QUP3_I2C_APPS_CMD_RCGR_ADDR,v) +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_QUP3_I2C_APPS_CMD_RCGR_ADDR,m,v,HWIO_GCC_BLSP1_QUP3_I2C_APPS_CMD_RCGR_IN) +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CMD_RCGR_DIRTY_D_BMSK 0x80 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CMD_RCGR_DIRTY_D_SHFT 0x7 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CMD_RCGR_DIRTY_N_BMSK 0x40 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CMD_RCGR_DIRTY_N_SHFT 0x6 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CMD_RCGR_DIRTY_M_BMSK 0x20 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CMD_RCGR_DIRTY_M_SHFT 0x5 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00010028) +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00010028) +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00010028) +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_RMSK 0x10371f +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_ADDR, HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_RMSK) +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_ADDR, m) +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_ADDR,v) +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_ADDR,m,v,HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_IN) +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_MODE_BMSK 0x3000 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_MODE_SHFT 0xc +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001002c) +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001002c) +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001002c) +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_M_RMSK 0xff +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_M_ATTR 0x3 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_M_IN \ + in_dword_masked(HWIO_GCC_BLSP1_QUP3_I2C_APPS_M_ADDR, HWIO_GCC_BLSP1_QUP3_I2C_APPS_M_RMSK) +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_M_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_QUP3_I2C_APPS_M_ADDR, m) +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_M_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_QUP3_I2C_APPS_M_ADDR,v) +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_M_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_QUP3_I2C_APPS_M_ADDR,m,v,HWIO_GCC_BLSP1_QUP3_I2C_APPS_M_IN) +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_M_M_BMSK 0xff +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_M_M_SHFT 0x0 + +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00010030) +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00010030) +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00010030) +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_N_RMSK 0xff +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_N_ATTR 0x3 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_N_IN \ + in_dword_masked(HWIO_GCC_BLSP1_QUP3_I2C_APPS_N_ADDR, HWIO_GCC_BLSP1_QUP3_I2C_APPS_N_RMSK) +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_N_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_QUP3_I2C_APPS_N_ADDR, m) +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_N_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_QUP3_I2C_APPS_N_ADDR,v) +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_N_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_QUP3_I2C_APPS_N_ADDR,m,v,HWIO_GCC_BLSP1_QUP3_I2C_APPS_N_IN) +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_N_NOT_N_MINUS_M_BMSK 0xff +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_N_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00010034) +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00010034) +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00010034) +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_D_RMSK 0xff +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_D_ATTR 0x3 +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_D_IN \ + in_dword_masked(HWIO_GCC_BLSP1_QUP3_I2C_APPS_D_ADDR, HWIO_GCC_BLSP1_QUP3_I2C_APPS_D_RMSK) +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_D_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_QUP3_I2C_APPS_D_ADDR, m) +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_D_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_QUP3_I2C_APPS_D_ADDR,v) +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_D_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_QUP3_I2C_APPS_D_ADDR,m,v,HWIO_GCC_BLSP1_QUP3_I2C_APPS_D_IN) +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_D_NOT_2D_BMSK 0xff +#define HWIO_GCC_BLSP1_QUP3_I2C_APPS_D_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_BLSP1_UART3_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00011000) +#define HWIO_GCC_BLSP1_UART3_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00011000) +#define HWIO_GCC_BLSP1_UART3_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00011000) +#define HWIO_GCC_BLSP1_UART3_BCR_RMSK 0x1 +#define HWIO_GCC_BLSP1_UART3_BCR_ATTR 0x3 +#define HWIO_GCC_BLSP1_UART3_BCR_IN \ + in_dword_masked(HWIO_GCC_BLSP1_UART3_BCR_ADDR, HWIO_GCC_BLSP1_UART3_BCR_RMSK) +#define HWIO_GCC_BLSP1_UART3_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_UART3_BCR_ADDR, m) +#define HWIO_GCC_BLSP1_UART3_BCR_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_UART3_BCR_ADDR,v) +#define HWIO_GCC_BLSP1_UART3_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_UART3_BCR_ADDR,m,v,HWIO_GCC_BLSP1_UART3_BCR_IN) +#define HWIO_GCC_BLSP1_UART3_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_BLSP1_UART3_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_BLSP1_UART3_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_UART3_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_BLSP1_UART3_APPS_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00011004) +#define HWIO_GCC_BLSP1_UART3_APPS_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00011004) +#define HWIO_GCC_BLSP1_UART3_APPS_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00011004) +#define HWIO_GCC_BLSP1_UART3_APPS_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_BLSP1_UART3_APPS_CBCR_ATTR 0x3 +#define HWIO_GCC_BLSP1_UART3_APPS_CBCR_IN \ + in_dword_masked(HWIO_GCC_BLSP1_UART3_APPS_CBCR_ADDR, HWIO_GCC_BLSP1_UART3_APPS_CBCR_RMSK) +#define HWIO_GCC_BLSP1_UART3_APPS_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_UART3_APPS_CBCR_ADDR, m) +#define HWIO_GCC_BLSP1_UART3_APPS_CBCR_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_UART3_APPS_CBCR_ADDR,v) +#define HWIO_GCC_BLSP1_UART3_APPS_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_UART3_APPS_CBCR_ADDR,m,v,HWIO_GCC_BLSP1_UART3_APPS_CBCR_IN) +#define HWIO_GCC_BLSP1_UART3_APPS_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_BLSP1_UART3_APPS_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_BLSP1_UART3_APPS_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_BLSP1_UART3_APPS_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_BLSP1_UART3_APPS_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_BLSP1_UART3_APPS_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_BLSP1_UART3_APPS_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_BLSP1_UART3_APPS_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_BLSP1_UART3_APPS_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_BLSP1_UART3_APPS_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_BLSP1_UART3_APPS_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_BLSP1_UART3_APPS_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_BLSP1_UART3_APPS_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_BLSP1_UART3_APPS_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_BLSP1_UART3_APPS_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_UART3_APPS_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_BLSP1_UART3_SIM_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00011008) +#define HWIO_GCC_BLSP1_UART3_SIM_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00011008) +#define HWIO_GCC_BLSP1_UART3_SIM_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00011008) +#define HWIO_GCC_BLSP1_UART3_SIM_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_BLSP1_UART3_SIM_CBCR_ATTR 0x3 +#define HWIO_GCC_BLSP1_UART3_SIM_CBCR_IN \ + in_dword_masked(HWIO_GCC_BLSP1_UART3_SIM_CBCR_ADDR, HWIO_GCC_BLSP1_UART3_SIM_CBCR_RMSK) +#define HWIO_GCC_BLSP1_UART3_SIM_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_UART3_SIM_CBCR_ADDR, m) +#define HWIO_GCC_BLSP1_UART3_SIM_CBCR_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_UART3_SIM_CBCR_ADDR,v) +#define HWIO_GCC_BLSP1_UART3_SIM_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_UART3_SIM_CBCR_ADDR,m,v,HWIO_GCC_BLSP1_UART3_SIM_CBCR_IN) +#define HWIO_GCC_BLSP1_UART3_SIM_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_BLSP1_UART3_SIM_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_BLSP1_UART3_SIM_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_BLSP1_UART3_SIM_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_BLSP1_UART3_SIM_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_BLSP1_UART3_SIM_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_BLSP1_UART3_SIM_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_BLSP1_UART3_SIM_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_BLSP1_UART3_SIM_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_BLSP1_UART3_SIM_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_BLSP1_UART3_SIM_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_BLSP1_UART3_SIM_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_BLSP1_UART3_SIM_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_BLSP1_UART3_SIM_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_BLSP1_UART3_SIM_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_UART3_SIM_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_BLSP1_UART3_APPS_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001100c) +#define HWIO_GCC_BLSP1_UART3_APPS_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001100c) +#define HWIO_GCC_BLSP1_UART3_APPS_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001100c) +#define HWIO_GCC_BLSP1_UART3_APPS_CMD_RCGR_RMSK 0x800000f3 +#define HWIO_GCC_BLSP1_UART3_APPS_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_BLSP1_UART3_APPS_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_BLSP1_UART3_APPS_CMD_RCGR_ADDR, HWIO_GCC_BLSP1_UART3_APPS_CMD_RCGR_RMSK) +#define HWIO_GCC_BLSP1_UART3_APPS_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_UART3_APPS_CMD_RCGR_ADDR, m) +#define HWIO_GCC_BLSP1_UART3_APPS_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_UART3_APPS_CMD_RCGR_ADDR,v) +#define HWIO_GCC_BLSP1_UART3_APPS_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_UART3_APPS_CMD_RCGR_ADDR,m,v,HWIO_GCC_BLSP1_UART3_APPS_CMD_RCGR_IN) +#define HWIO_GCC_BLSP1_UART3_APPS_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_BLSP1_UART3_APPS_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_BLSP1_UART3_APPS_CMD_RCGR_DIRTY_D_BMSK 0x80 +#define HWIO_GCC_BLSP1_UART3_APPS_CMD_RCGR_DIRTY_D_SHFT 0x7 +#define HWIO_GCC_BLSP1_UART3_APPS_CMD_RCGR_DIRTY_N_BMSK 0x40 +#define HWIO_GCC_BLSP1_UART3_APPS_CMD_RCGR_DIRTY_N_SHFT 0x6 +#define HWIO_GCC_BLSP1_UART3_APPS_CMD_RCGR_DIRTY_M_BMSK 0x20 +#define HWIO_GCC_BLSP1_UART3_APPS_CMD_RCGR_DIRTY_M_SHFT 0x5 +#define HWIO_GCC_BLSP1_UART3_APPS_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_BLSP1_UART3_APPS_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_BLSP1_UART3_APPS_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_BLSP1_UART3_APPS_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_BLSP1_UART3_APPS_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_UART3_APPS_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_BLSP1_UART3_APPS_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_BLSP1_UART3_APPS_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_BLSP1_UART3_APPS_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_UART3_APPS_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00011010) +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00011010) +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00011010) +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_RMSK 0x10371f +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_ADDR, HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_RMSK) +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_ADDR, m) +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_ADDR,v) +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_ADDR,m,v,HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_IN) +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_MODE_BMSK 0x3000 +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_MODE_SHFT 0xc +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_BLSP1_UART3_APPS_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_BLSP1_UART3_APPS_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00011014) +#define HWIO_GCC_BLSP1_UART3_APPS_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00011014) +#define HWIO_GCC_BLSP1_UART3_APPS_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00011014) +#define HWIO_GCC_BLSP1_UART3_APPS_M_RMSK 0xffff +#define HWIO_GCC_BLSP1_UART3_APPS_M_ATTR 0x3 +#define HWIO_GCC_BLSP1_UART3_APPS_M_IN \ + in_dword_masked(HWIO_GCC_BLSP1_UART3_APPS_M_ADDR, HWIO_GCC_BLSP1_UART3_APPS_M_RMSK) +#define HWIO_GCC_BLSP1_UART3_APPS_M_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_UART3_APPS_M_ADDR, m) +#define HWIO_GCC_BLSP1_UART3_APPS_M_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_UART3_APPS_M_ADDR,v) +#define HWIO_GCC_BLSP1_UART3_APPS_M_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_UART3_APPS_M_ADDR,m,v,HWIO_GCC_BLSP1_UART3_APPS_M_IN) +#define HWIO_GCC_BLSP1_UART3_APPS_M_M_BMSK 0xffff +#define HWIO_GCC_BLSP1_UART3_APPS_M_M_SHFT 0x0 + +#define HWIO_GCC_BLSP1_UART3_APPS_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00011018) +#define HWIO_GCC_BLSP1_UART3_APPS_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00011018) +#define HWIO_GCC_BLSP1_UART3_APPS_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00011018) +#define HWIO_GCC_BLSP1_UART3_APPS_N_RMSK 0xffff +#define HWIO_GCC_BLSP1_UART3_APPS_N_ATTR 0x3 +#define HWIO_GCC_BLSP1_UART3_APPS_N_IN \ + in_dword_masked(HWIO_GCC_BLSP1_UART3_APPS_N_ADDR, HWIO_GCC_BLSP1_UART3_APPS_N_RMSK) +#define HWIO_GCC_BLSP1_UART3_APPS_N_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_UART3_APPS_N_ADDR, m) +#define HWIO_GCC_BLSP1_UART3_APPS_N_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_UART3_APPS_N_ADDR,v) +#define HWIO_GCC_BLSP1_UART3_APPS_N_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_UART3_APPS_N_ADDR,m,v,HWIO_GCC_BLSP1_UART3_APPS_N_IN) +#define HWIO_GCC_BLSP1_UART3_APPS_N_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_BLSP1_UART3_APPS_N_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_BLSP1_UART3_APPS_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001101c) +#define HWIO_GCC_BLSP1_UART3_APPS_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001101c) +#define HWIO_GCC_BLSP1_UART3_APPS_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001101c) +#define HWIO_GCC_BLSP1_UART3_APPS_D_RMSK 0xffff +#define HWIO_GCC_BLSP1_UART3_APPS_D_ATTR 0x3 +#define HWIO_GCC_BLSP1_UART3_APPS_D_IN \ + in_dword_masked(HWIO_GCC_BLSP1_UART3_APPS_D_ADDR, HWIO_GCC_BLSP1_UART3_APPS_D_RMSK) +#define HWIO_GCC_BLSP1_UART3_APPS_D_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_UART3_APPS_D_ADDR, m) +#define HWIO_GCC_BLSP1_UART3_APPS_D_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_UART3_APPS_D_ADDR,v) +#define HWIO_GCC_BLSP1_UART3_APPS_D_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_UART3_APPS_D_ADDR,m,v,HWIO_GCC_BLSP1_UART3_APPS_D_IN) +#define HWIO_GCC_BLSP1_UART3_APPS_D_NOT_2D_BMSK 0xffff +#define HWIO_GCC_BLSP1_UART3_APPS_D_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_BLSP1_QUP4_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00012000) +#define HWIO_GCC_BLSP1_QUP4_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00012000) +#define HWIO_GCC_BLSP1_QUP4_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00012000) +#define HWIO_GCC_BLSP1_QUP4_BCR_RMSK 0x1 +#define HWIO_GCC_BLSP1_QUP4_BCR_ATTR 0x3 +#define HWIO_GCC_BLSP1_QUP4_BCR_IN \ + in_dword_masked(HWIO_GCC_BLSP1_QUP4_BCR_ADDR, HWIO_GCC_BLSP1_QUP4_BCR_RMSK) +#define HWIO_GCC_BLSP1_QUP4_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_QUP4_BCR_ADDR, m) +#define HWIO_GCC_BLSP1_QUP4_BCR_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_QUP4_BCR_ADDR,v) +#define HWIO_GCC_BLSP1_QUP4_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_QUP4_BCR_ADDR,m,v,HWIO_GCC_BLSP1_QUP4_BCR_IN) +#define HWIO_GCC_BLSP1_QUP4_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_BLSP1_QUP4_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_BLSP1_QUP4_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP4_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00012004) +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00012004) +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00012004) +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CBCR_ATTR 0x3 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CBCR_IN \ + in_dword_masked(HWIO_GCC_BLSP1_QUP4_SPI_APPS_CBCR_ADDR, HWIO_GCC_BLSP1_QUP4_SPI_APPS_CBCR_RMSK) +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_QUP4_SPI_APPS_CBCR_ADDR, m) +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CBCR_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_QUP4_SPI_APPS_CBCR_ADDR,v) +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_QUP4_SPI_APPS_CBCR_ADDR,m,v,HWIO_GCC_BLSP1_QUP4_SPI_APPS_CBCR_IN) +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00012008) +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00012008) +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00012008) +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CBCR_ATTR 0x3 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CBCR_IN \ + in_dword_masked(HWIO_GCC_BLSP1_QUP4_I2C_APPS_CBCR_ADDR, HWIO_GCC_BLSP1_QUP4_I2C_APPS_CBCR_RMSK) +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_QUP4_I2C_APPS_CBCR_ADDR, m) +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CBCR_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_QUP4_I2C_APPS_CBCR_ADDR,v) +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_QUP4_I2C_APPS_CBCR_ADDR,m,v,HWIO_GCC_BLSP1_QUP4_I2C_APPS_CBCR_IN) +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001200c) +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001200c) +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001200c) +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CMD_RCGR_RMSK 0x800000f3 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_BLSP1_QUP4_SPI_APPS_CMD_RCGR_ADDR, HWIO_GCC_BLSP1_QUP4_SPI_APPS_CMD_RCGR_RMSK) +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_QUP4_SPI_APPS_CMD_RCGR_ADDR, m) +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_QUP4_SPI_APPS_CMD_RCGR_ADDR,v) +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_QUP4_SPI_APPS_CMD_RCGR_ADDR,m,v,HWIO_GCC_BLSP1_QUP4_SPI_APPS_CMD_RCGR_IN) +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CMD_RCGR_DIRTY_D_BMSK 0x80 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CMD_RCGR_DIRTY_D_SHFT 0x7 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CMD_RCGR_DIRTY_N_BMSK 0x40 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CMD_RCGR_DIRTY_N_SHFT 0x6 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CMD_RCGR_DIRTY_M_BMSK 0x20 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CMD_RCGR_DIRTY_M_SHFT 0x5 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00012010) +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00012010) +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00012010) +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_RMSK 0x10371f +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_ADDR, HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_RMSK) +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_ADDR, m) +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_ADDR,v) +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_ADDR,m,v,HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_IN) +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_MODE_BMSK 0x3000 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_MODE_SHFT 0xc +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00012014) +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00012014) +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00012014) +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_M_RMSK 0xff +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_M_ATTR 0x3 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_M_IN \ + in_dword_masked(HWIO_GCC_BLSP1_QUP4_SPI_APPS_M_ADDR, HWIO_GCC_BLSP1_QUP4_SPI_APPS_M_RMSK) +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_M_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_QUP4_SPI_APPS_M_ADDR, m) +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_M_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_QUP4_SPI_APPS_M_ADDR,v) +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_M_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_QUP4_SPI_APPS_M_ADDR,m,v,HWIO_GCC_BLSP1_QUP4_SPI_APPS_M_IN) +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_M_M_BMSK 0xff +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_M_M_SHFT 0x0 + +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00012018) +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00012018) +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00012018) +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_N_RMSK 0xff +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_N_ATTR 0x3 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_N_IN \ + in_dword_masked(HWIO_GCC_BLSP1_QUP4_SPI_APPS_N_ADDR, HWIO_GCC_BLSP1_QUP4_SPI_APPS_N_RMSK) +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_N_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_QUP4_SPI_APPS_N_ADDR, m) +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_N_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_QUP4_SPI_APPS_N_ADDR,v) +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_N_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_QUP4_SPI_APPS_N_ADDR,m,v,HWIO_GCC_BLSP1_QUP4_SPI_APPS_N_IN) +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_N_NOT_N_MINUS_M_BMSK 0xff +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_N_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001201c) +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001201c) +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001201c) +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_D_RMSK 0xff +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_D_ATTR 0x3 +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_D_IN \ + in_dword_masked(HWIO_GCC_BLSP1_QUP4_SPI_APPS_D_ADDR, HWIO_GCC_BLSP1_QUP4_SPI_APPS_D_RMSK) +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_D_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_QUP4_SPI_APPS_D_ADDR, m) +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_D_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_QUP4_SPI_APPS_D_ADDR,v) +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_D_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_QUP4_SPI_APPS_D_ADDR,m,v,HWIO_GCC_BLSP1_QUP4_SPI_APPS_D_IN) +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_D_NOT_2D_BMSK 0xff +#define HWIO_GCC_BLSP1_QUP4_SPI_APPS_D_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00012024) +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00012024) +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00012024) +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CMD_RCGR_RMSK 0x800000f3 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_BLSP1_QUP4_I2C_APPS_CMD_RCGR_ADDR, HWIO_GCC_BLSP1_QUP4_I2C_APPS_CMD_RCGR_RMSK) +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_QUP4_I2C_APPS_CMD_RCGR_ADDR, m) +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_QUP4_I2C_APPS_CMD_RCGR_ADDR,v) +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_QUP4_I2C_APPS_CMD_RCGR_ADDR,m,v,HWIO_GCC_BLSP1_QUP4_I2C_APPS_CMD_RCGR_IN) +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CMD_RCGR_DIRTY_D_BMSK 0x80 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CMD_RCGR_DIRTY_D_SHFT 0x7 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CMD_RCGR_DIRTY_N_BMSK 0x40 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CMD_RCGR_DIRTY_N_SHFT 0x6 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CMD_RCGR_DIRTY_M_BMSK 0x20 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CMD_RCGR_DIRTY_M_SHFT 0x5 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00012028) +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00012028) +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00012028) +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_RMSK 0x10371f +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_ADDR, HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_RMSK) +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_ADDR, m) +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_ADDR,v) +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_ADDR,m,v,HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_IN) +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_MODE_BMSK 0x3000 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_MODE_SHFT 0xc +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001202c) +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001202c) +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001202c) +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_M_RMSK 0xff +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_M_ATTR 0x3 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_M_IN \ + in_dword_masked(HWIO_GCC_BLSP1_QUP4_I2C_APPS_M_ADDR, HWIO_GCC_BLSP1_QUP4_I2C_APPS_M_RMSK) +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_M_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_QUP4_I2C_APPS_M_ADDR, m) +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_M_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_QUP4_I2C_APPS_M_ADDR,v) +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_M_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_QUP4_I2C_APPS_M_ADDR,m,v,HWIO_GCC_BLSP1_QUP4_I2C_APPS_M_IN) +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_M_M_BMSK 0xff +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_M_M_SHFT 0x0 + +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00012030) +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00012030) +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00012030) +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_N_RMSK 0xff +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_N_ATTR 0x3 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_N_IN \ + in_dword_masked(HWIO_GCC_BLSP1_QUP4_I2C_APPS_N_ADDR, HWIO_GCC_BLSP1_QUP4_I2C_APPS_N_RMSK) +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_N_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_QUP4_I2C_APPS_N_ADDR, m) +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_N_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_QUP4_I2C_APPS_N_ADDR,v) +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_N_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_QUP4_I2C_APPS_N_ADDR,m,v,HWIO_GCC_BLSP1_QUP4_I2C_APPS_N_IN) +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_N_NOT_N_MINUS_M_BMSK 0xff +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_N_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00012034) +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00012034) +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00012034) +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_D_RMSK 0xff +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_D_ATTR 0x3 +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_D_IN \ + in_dword_masked(HWIO_GCC_BLSP1_QUP4_I2C_APPS_D_ADDR, HWIO_GCC_BLSP1_QUP4_I2C_APPS_D_RMSK) +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_D_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_QUP4_I2C_APPS_D_ADDR, m) +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_D_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_QUP4_I2C_APPS_D_ADDR,v) +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_D_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_QUP4_I2C_APPS_D_ADDR,m,v,HWIO_GCC_BLSP1_QUP4_I2C_APPS_D_IN) +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_D_NOT_2D_BMSK 0xff +#define HWIO_GCC_BLSP1_QUP4_I2C_APPS_D_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_BLSP1_UART4_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00013000) +#define HWIO_GCC_BLSP1_UART4_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00013000) +#define HWIO_GCC_BLSP1_UART4_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00013000) +#define HWIO_GCC_BLSP1_UART4_BCR_RMSK 0x1 +#define HWIO_GCC_BLSP1_UART4_BCR_ATTR 0x3 +#define HWIO_GCC_BLSP1_UART4_BCR_IN \ + in_dword_masked(HWIO_GCC_BLSP1_UART4_BCR_ADDR, HWIO_GCC_BLSP1_UART4_BCR_RMSK) +#define HWIO_GCC_BLSP1_UART4_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_UART4_BCR_ADDR, m) +#define HWIO_GCC_BLSP1_UART4_BCR_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_UART4_BCR_ADDR,v) +#define HWIO_GCC_BLSP1_UART4_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_UART4_BCR_ADDR,m,v,HWIO_GCC_BLSP1_UART4_BCR_IN) +#define HWIO_GCC_BLSP1_UART4_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_BLSP1_UART4_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_BLSP1_UART4_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_UART4_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_BLSP1_UART4_APPS_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00013004) +#define HWIO_GCC_BLSP1_UART4_APPS_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00013004) +#define HWIO_GCC_BLSP1_UART4_APPS_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00013004) +#define HWIO_GCC_BLSP1_UART4_APPS_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_BLSP1_UART4_APPS_CBCR_ATTR 0x3 +#define HWIO_GCC_BLSP1_UART4_APPS_CBCR_IN \ + in_dword_masked(HWIO_GCC_BLSP1_UART4_APPS_CBCR_ADDR, HWIO_GCC_BLSP1_UART4_APPS_CBCR_RMSK) +#define HWIO_GCC_BLSP1_UART4_APPS_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_UART4_APPS_CBCR_ADDR, m) +#define HWIO_GCC_BLSP1_UART4_APPS_CBCR_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_UART4_APPS_CBCR_ADDR,v) +#define HWIO_GCC_BLSP1_UART4_APPS_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_UART4_APPS_CBCR_ADDR,m,v,HWIO_GCC_BLSP1_UART4_APPS_CBCR_IN) +#define HWIO_GCC_BLSP1_UART4_APPS_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_BLSP1_UART4_APPS_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_BLSP1_UART4_APPS_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_BLSP1_UART4_APPS_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_BLSP1_UART4_APPS_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_BLSP1_UART4_APPS_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_BLSP1_UART4_APPS_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_BLSP1_UART4_APPS_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_BLSP1_UART4_APPS_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_BLSP1_UART4_APPS_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_BLSP1_UART4_APPS_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_BLSP1_UART4_APPS_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_BLSP1_UART4_APPS_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_BLSP1_UART4_APPS_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_BLSP1_UART4_APPS_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_UART4_APPS_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_BLSP1_UART4_SIM_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00013008) +#define HWIO_GCC_BLSP1_UART4_SIM_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00013008) +#define HWIO_GCC_BLSP1_UART4_SIM_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00013008) +#define HWIO_GCC_BLSP1_UART4_SIM_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_BLSP1_UART4_SIM_CBCR_ATTR 0x3 +#define HWIO_GCC_BLSP1_UART4_SIM_CBCR_IN \ + in_dword_masked(HWIO_GCC_BLSP1_UART4_SIM_CBCR_ADDR, HWIO_GCC_BLSP1_UART4_SIM_CBCR_RMSK) +#define HWIO_GCC_BLSP1_UART4_SIM_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_UART4_SIM_CBCR_ADDR, m) +#define HWIO_GCC_BLSP1_UART4_SIM_CBCR_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_UART4_SIM_CBCR_ADDR,v) +#define HWIO_GCC_BLSP1_UART4_SIM_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_UART4_SIM_CBCR_ADDR,m,v,HWIO_GCC_BLSP1_UART4_SIM_CBCR_IN) +#define HWIO_GCC_BLSP1_UART4_SIM_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_BLSP1_UART4_SIM_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_BLSP1_UART4_SIM_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_BLSP1_UART4_SIM_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_BLSP1_UART4_SIM_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_BLSP1_UART4_SIM_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_BLSP1_UART4_SIM_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_BLSP1_UART4_SIM_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_BLSP1_UART4_SIM_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_BLSP1_UART4_SIM_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_BLSP1_UART4_SIM_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_BLSP1_UART4_SIM_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_BLSP1_UART4_SIM_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_BLSP1_UART4_SIM_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_BLSP1_UART4_SIM_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_UART4_SIM_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_BLSP1_UART4_APPS_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001300c) +#define HWIO_GCC_BLSP1_UART4_APPS_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001300c) +#define HWIO_GCC_BLSP1_UART4_APPS_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001300c) +#define HWIO_GCC_BLSP1_UART4_APPS_CMD_RCGR_RMSK 0x800000f3 +#define HWIO_GCC_BLSP1_UART4_APPS_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_BLSP1_UART4_APPS_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_BLSP1_UART4_APPS_CMD_RCGR_ADDR, HWIO_GCC_BLSP1_UART4_APPS_CMD_RCGR_RMSK) +#define HWIO_GCC_BLSP1_UART4_APPS_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_UART4_APPS_CMD_RCGR_ADDR, m) +#define HWIO_GCC_BLSP1_UART4_APPS_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_UART4_APPS_CMD_RCGR_ADDR,v) +#define HWIO_GCC_BLSP1_UART4_APPS_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_UART4_APPS_CMD_RCGR_ADDR,m,v,HWIO_GCC_BLSP1_UART4_APPS_CMD_RCGR_IN) +#define HWIO_GCC_BLSP1_UART4_APPS_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_BLSP1_UART4_APPS_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_BLSP1_UART4_APPS_CMD_RCGR_DIRTY_D_BMSK 0x80 +#define HWIO_GCC_BLSP1_UART4_APPS_CMD_RCGR_DIRTY_D_SHFT 0x7 +#define HWIO_GCC_BLSP1_UART4_APPS_CMD_RCGR_DIRTY_N_BMSK 0x40 +#define HWIO_GCC_BLSP1_UART4_APPS_CMD_RCGR_DIRTY_N_SHFT 0x6 +#define HWIO_GCC_BLSP1_UART4_APPS_CMD_RCGR_DIRTY_M_BMSK 0x20 +#define HWIO_GCC_BLSP1_UART4_APPS_CMD_RCGR_DIRTY_M_SHFT 0x5 +#define HWIO_GCC_BLSP1_UART4_APPS_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_BLSP1_UART4_APPS_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_BLSP1_UART4_APPS_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_BLSP1_UART4_APPS_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_BLSP1_UART4_APPS_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_UART4_APPS_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_BLSP1_UART4_APPS_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_BLSP1_UART4_APPS_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_BLSP1_UART4_APPS_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_UART4_APPS_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00013010) +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00013010) +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00013010) +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_RMSK 0x10371f +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_ADDR, HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_RMSK) +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_ADDR, m) +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_ADDR,v) +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_ADDR,m,v,HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_IN) +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_MODE_BMSK 0x3000 +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_MODE_SHFT 0xc +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_BLSP1_UART4_APPS_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_BLSP1_UART4_APPS_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00013014) +#define HWIO_GCC_BLSP1_UART4_APPS_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00013014) +#define HWIO_GCC_BLSP1_UART4_APPS_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00013014) +#define HWIO_GCC_BLSP1_UART4_APPS_M_RMSK 0xffff +#define HWIO_GCC_BLSP1_UART4_APPS_M_ATTR 0x3 +#define HWIO_GCC_BLSP1_UART4_APPS_M_IN \ + in_dword_masked(HWIO_GCC_BLSP1_UART4_APPS_M_ADDR, HWIO_GCC_BLSP1_UART4_APPS_M_RMSK) +#define HWIO_GCC_BLSP1_UART4_APPS_M_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_UART4_APPS_M_ADDR, m) +#define HWIO_GCC_BLSP1_UART4_APPS_M_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_UART4_APPS_M_ADDR,v) +#define HWIO_GCC_BLSP1_UART4_APPS_M_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_UART4_APPS_M_ADDR,m,v,HWIO_GCC_BLSP1_UART4_APPS_M_IN) +#define HWIO_GCC_BLSP1_UART4_APPS_M_M_BMSK 0xffff +#define HWIO_GCC_BLSP1_UART4_APPS_M_M_SHFT 0x0 + +#define HWIO_GCC_BLSP1_UART4_APPS_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00013018) +#define HWIO_GCC_BLSP1_UART4_APPS_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00013018) +#define HWIO_GCC_BLSP1_UART4_APPS_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00013018) +#define HWIO_GCC_BLSP1_UART4_APPS_N_RMSK 0xffff +#define HWIO_GCC_BLSP1_UART4_APPS_N_ATTR 0x3 +#define HWIO_GCC_BLSP1_UART4_APPS_N_IN \ + in_dword_masked(HWIO_GCC_BLSP1_UART4_APPS_N_ADDR, HWIO_GCC_BLSP1_UART4_APPS_N_RMSK) +#define HWIO_GCC_BLSP1_UART4_APPS_N_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_UART4_APPS_N_ADDR, m) +#define HWIO_GCC_BLSP1_UART4_APPS_N_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_UART4_APPS_N_ADDR,v) +#define HWIO_GCC_BLSP1_UART4_APPS_N_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_UART4_APPS_N_ADDR,m,v,HWIO_GCC_BLSP1_UART4_APPS_N_IN) +#define HWIO_GCC_BLSP1_UART4_APPS_N_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_BLSP1_UART4_APPS_N_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_BLSP1_UART4_APPS_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001301c) +#define HWIO_GCC_BLSP1_UART4_APPS_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001301c) +#define HWIO_GCC_BLSP1_UART4_APPS_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001301c) +#define HWIO_GCC_BLSP1_UART4_APPS_D_RMSK 0xffff +#define HWIO_GCC_BLSP1_UART4_APPS_D_ATTR 0x3 +#define HWIO_GCC_BLSP1_UART4_APPS_D_IN \ + in_dword_masked(HWIO_GCC_BLSP1_UART4_APPS_D_ADDR, HWIO_GCC_BLSP1_UART4_APPS_D_RMSK) +#define HWIO_GCC_BLSP1_UART4_APPS_D_INM(m) \ + in_dword_masked(HWIO_GCC_BLSP1_UART4_APPS_D_ADDR, m) +#define HWIO_GCC_BLSP1_UART4_APPS_D_OUT(v) \ + out_dword(HWIO_GCC_BLSP1_UART4_APPS_D_ADDR,v) +#define HWIO_GCC_BLSP1_UART4_APPS_D_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BLSP1_UART4_APPS_D_ADDR,m,v,HWIO_GCC_BLSP1_UART4_APPS_D_IN) +#define HWIO_GCC_BLSP1_UART4_APPS_D_NOT_2D_BMSK 0xffff +#define HWIO_GCC_BLSP1_UART4_APPS_D_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_PDM_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00014000) +#define HWIO_GCC_PDM_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00014000) +#define HWIO_GCC_PDM_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00014000) +#define HWIO_GCC_PDM_BCR_RMSK 0x1 +#define HWIO_GCC_PDM_BCR_ATTR 0x3 +#define HWIO_GCC_PDM_BCR_IN \ + in_dword_masked(HWIO_GCC_PDM_BCR_ADDR, HWIO_GCC_PDM_BCR_RMSK) +#define HWIO_GCC_PDM_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_PDM_BCR_ADDR, m) +#define HWIO_GCC_PDM_BCR_OUT(v) \ + out_dword(HWIO_GCC_PDM_BCR_ADDR,v) +#define HWIO_GCC_PDM_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PDM_BCR_ADDR,m,v,HWIO_GCC_PDM_BCR_IN) +#define HWIO_GCC_PDM_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_PDM_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_PDM_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_PDM_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PDM_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00014004) +#define HWIO_GCC_PDM_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00014004) +#define HWIO_GCC_PDM_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00014004) +#define HWIO_GCC_PDM_AHB_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_PDM_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_PDM_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_PDM_AHB_CBCR_ADDR, HWIO_GCC_PDM_AHB_CBCR_RMSK) +#define HWIO_GCC_PDM_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_PDM_AHB_CBCR_ADDR, m) +#define HWIO_GCC_PDM_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_PDM_AHB_CBCR_ADDR,v) +#define HWIO_GCC_PDM_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PDM_AHB_CBCR_ADDR,m,v,HWIO_GCC_PDM_AHB_CBCR_IN) +#define HWIO_GCC_PDM_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_PDM_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_PDM_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_PDM_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_PDM_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_PDM_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_PDM_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_PDM_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_PDM_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_PDM_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_PDM_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_PDM_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_PDM_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_PDM_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_PDM_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_PDM_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_PDM_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_PDM_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_PDM_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_PDM_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_PDM_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_PDM_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_PDM_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PDM_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PDM_XO4_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00014008) +#define HWIO_GCC_PDM_XO4_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00014008) +#define HWIO_GCC_PDM_XO4_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00014008) +#define HWIO_GCC_PDM_XO4_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_PDM_XO4_CBCR_ATTR 0x3 +#define HWIO_GCC_PDM_XO4_CBCR_IN \ + in_dword_masked(HWIO_GCC_PDM_XO4_CBCR_ADDR, HWIO_GCC_PDM_XO4_CBCR_RMSK) +#define HWIO_GCC_PDM_XO4_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_PDM_XO4_CBCR_ADDR, m) +#define HWIO_GCC_PDM_XO4_CBCR_OUT(v) \ + out_dword(HWIO_GCC_PDM_XO4_CBCR_ADDR,v) +#define HWIO_GCC_PDM_XO4_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PDM_XO4_CBCR_ADDR,m,v,HWIO_GCC_PDM_XO4_CBCR_IN) +#define HWIO_GCC_PDM_XO4_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_PDM_XO4_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_PDM_XO4_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_PDM_XO4_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_PDM_XO4_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_PDM_XO4_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_PDM_XO4_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_PDM_XO4_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_PDM_XO4_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_PDM_XO4_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_PDM_XO4_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_PDM_XO4_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_PDM_XO4_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_PDM_XO4_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_PDM_XO4_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PDM_XO4_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PDM2_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001400c) +#define HWIO_GCC_PDM2_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001400c) +#define HWIO_GCC_PDM2_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001400c) +#define HWIO_GCC_PDM2_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_PDM2_CBCR_ATTR 0x3 +#define HWIO_GCC_PDM2_CBCR_IN \ + in_dword_masked(HWIO_GCC_PDM2_CBCR_ADDR, HWIO_GCC_PDM2_CBCR_RMSK) +#define HWIO_GCC_PDM2_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_PDM2_CBCR_ADDR, m) +#define HWIO_GCC_PDM2_CBCR_OUT(v) \ + out_dword(HWIO_GCC_PDM2_CBCR_ADDR,v) +#define HWIO_GCC_PDM2_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PDM2_CBCR_ADDR,m,v,HWIO_GCC_PDM2_CBCR_IN) +#define HWIO_GCC_PDM2_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_PDM2_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_PDM2_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_PDM2_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_PDM2_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_PDM2_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_PDM2_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_PDM2_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_PDM2_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_PDM2_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_PDM2_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_PDM2_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_PDM2_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_PDM2_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_PDM2_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PDM2_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PDM2_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00014010) +#define HWIO_GCC_PDM2_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00014010) +#define HWIO_GCC_PDM2_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00014010) +#define HWIO_GCC_PDM2_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_PDM2_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_PDM2_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_PDM2_CMD_RCGR_ADDR, HWIO_GCC_PDM2_CMD_RCGR_RMSK) +#define HWIO_GCC_PDM2_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_PDM2_CMD_RCGR_ADDR, m) +#define HWIO_GCC_PDM2_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_PDM2_CMD_RCGR_ADDR,v) +#define HWIO_GCC_PDM2_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PDM2_CMD_RCGR_ADDR,m,v,HWIO_GCC_PDM2_CMD_RCGR_IN) +#define HWIO_GCC_PDM2_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_PDM2_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_PDM2_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_PDM2_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_PDM2_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_PDM2_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_PDM2_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_PDM2_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_PDM2_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_PDM2_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_PDM2_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PDM2_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PDM2_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00014014) +#define HWIO_GCC_PDM2_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00014014) +#define HWIO_GCC_PDM2_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00014014) +#define HWIO_GCC_PDM2_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_PDM2_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_PDM2_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_PDM2_CFG_RCGR_ADDR, HWIO_GCC_PDM2_CFG_RCGR_RMSK) +#define HWIO_GCC_PDM2_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_PDM2_CFG_RCGR_ADDR, m) +#define HWIO_GCC_PDM2_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_PDM2_CFG_RCGR_ADDR,v) +#define HWIO_GCC_PDM2_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PDM2_CFG_RCGR_ADDR,m,v,HWIO_GCC_PDM2_CFG_RCGR_IN) +#define HWIO_GCC_PDM2_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_PDM2_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_PDM2_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_PDM2_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_PDM2_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_PDM2_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_PDM2_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_PDM2_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_PDM_XO4_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00014028) +#define HWIO_GCC_PDM_XO4_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00014028) +#define HWIO_GCC_PDM_XO4_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00014028) +#define HWIO_GCC_PDM_XO4_CDIVR_RMSK 0xf +#define HWIO_GCC_PDM_XO4_CDIVR_ATTR 0x3 +#define HWIO_GCC_PDM_XO4_CDIVR_IN \ + in_dword_masked(HWIO_GCC_PDM_XO4_CDIVR_ADDR, HWIO_GCC_PDM_XO4_CDIVR_RMSK) +#define HWIO_GCC_PDM_XO4_CDIVR_INM(m) \ + in_dword_masked(HWIO_GCC_PDM_XO4_CDIVR_ADDR, m) +#define HWIO_GCC_PDM_XO4_CDIVR_OUT(v) \ + out_dword(HWIO_GCC_PDM_XO4_CDIVR_ADDR,v) +#define HWIO_GCC_PDM_XO4_CDIVR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PDM_XO4_CDIVR_ADDR,m,v,HWIO_GCC_PDM_XO4_CDIVR_IN) +#define HWIO_GCC_PDM_XO4_CDIVR_CLK_DIV_BMSK 0xf +#define HWIO_GCC_PDM_XO4_CDIVR_CLK_DIV_SHFT 0x0 + +#define HWIO_GCC_PRNG_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00015000) +#define HWIO_GCC_PRNG_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00015000) +#define HWIO_GCC_PRNG_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00015000) +#define HWIO_GCC_PRNG_BCR_RMSK 0x1 +#define HWIO_GCC_PRNG_BCR_ATTR 0x3 +#define HWIO_GCC_PRNG_BCR_IN \ + in_dword_masked(HWIO_GCC_PRNG_BCR_ADDR, HWIO_GCC_PRNG_BCR_RMSK) +#define HWIO_GCC_PRNG_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_PRNG_BCR_ADDR, m) +#define HWIO_GCC_PRNG_BCR_OUT(v) \ + out_dword(HWIO_GCC_PRNG_BCR_ADDR,v) +#define HWIO_GCC_PRNG_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PRNG_BCR_ADDR,m,v,HWIO_GCC_PRNG_BCR_IN) +#define HWIO_GCC_PRNG_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_PRNG_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_PRNG_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_PRNG_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PRNG_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00015004) +#define HWIO_GCC_PRNG_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00015004) +#define HWIO_GCC_PRNG_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00015004) +#define HWIO_GCC_PRNG_AHB_CBCR_RMSK 0x81d00004 +#define HWIO_GCC_PRNG_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_PRNG_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_PRNG_AHB_CBCR_ADDR, HWIO_GCC_PRNG_AHB_CBCR_RMSK) +#define HWIO_GCC_PRNG_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_PRNG_AHB_CBCR_ADDR, m) +#define HWIO_GCC_PRNG_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_PRNG_AHB_CBCR_ADDR,v) +#define HWIO_GCC_PRNG_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PRNG_AHB_CBCR_ADDR,m,v,HWIO_GCC_PRNG_AHB_CBCR_IN) +#define HWIO_GCC_PRNG_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_PRNG_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_PRNG_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_PRNG_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_PRNG_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_PRNG_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_PRNG_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_PRNG_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_PRNG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_PRNG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_PRNG_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_PRNG_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_PRNG_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_PRNG_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 + +#define HWIO_GCC_TCSR_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00016000) +#define HWIO_GCC_TCSR_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00016000) +#define HWIO_GCC_TCSR_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00016000) +#define HWIO_GCC_TCSR_BCR_RMSK 0x1 +#define HWIO_GCC_TCSR_BCR_ATTR 0x3 +#define HWIO_GCC_TCSR_BCR_IN \ + in_dword_masked(HWIO_GCC_TCSR_BCR_ADDR, HWIO_GCC_TCSR_BCR_RMSK) +#define HWIO_GCC_TCSR_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_TCSR_BCR_ADDR, m) +#define HWIO_GCC_TCSR_BCR_OUT(v) \ + out_dword(HWIO_GCC_TCSR_BCR_ADDR,v) +#define HWIO_GCC_TCSR_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TCSR_BCR_ADDR,m,v,HWIO_GCC_TCSR_BCR_IN) +#define HWIO_GCC_TCSR_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_TCSR_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_TCSR_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_TCSR_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TCSR_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00016004) +#define HWIO_GCC_TCSR_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00016004) +#define HWIO_GCC_TCSR_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00016004) +#define HWIO_GCC_TCSR_AHB_CBCR_RMSK 0x81d0000e +#define HWIO_GCC_TCSR_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_TCSR_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_TCSR_AHB_CBCR_ADDR, HWIO_GCC_TCSR_AHB_CBCR_RMSK) +#define HWIO_GCC_TCSR_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_TCSR_AHB_CBCR_ADDR, m) +#define HWIO_GCC_TCSR_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_TCSR_AHB_CBCR_ADDR,v) +#define HWIO_GCC_TCSR_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TCSR_AHB_CBCR_ADDR,m,v,HWIO_GCC_TCSR_AHB_CBCR_IN) +#define HWIO_GCC_TCSR_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TCSR_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TCSR_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_TCSR_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_TCSR_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_TCSR_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_TCSR_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_TCSR_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_TCSR_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_TCSR_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_TCSR_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_TCSR_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_TCSR_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_TCSR_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_TCSR_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_TCSR_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_TCSR_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_TCSR_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_TCSR_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_TCSR_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TCSR_ACC_SERIAL_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00016008) +#define HWIO_GCC_TCSR_ACC_SERIAL_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00016008) +#define HWIO_GCC_TCSR_ACC_SERIAL_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00016008) +#define HWIO_GCC_TCSR_ACC_SERIAL_CBCR_RMSK 0x81c0000f +#define HWIO_GCC_TCSR_ACC_SERIAL_CBCR_ATTR 0x3 +#define HWIO_GCC_TCSR_ACC_SERIAL_CBCR_IN \ + in_dword_masked(HWIO_GCC_TCSR_ACC_SERIAL_CBCR_ADDR, HWIO_GCC_TCSR_ACC_SERIAL_CBCR_RMSK) +#define HWIO_GCC_TCSR_ACC_SERIAL_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_TCSR_ACC_SERIAL_CBCR_ADDR, m) +#define HWIO_GCC_TCSR_ACC_SERIAL_CBCR_OUT(v) \ + out_dword(HWIO_GCC_TCSR_ACC_SERIAL_CBCR_ADDR,v) +#define HWIO_GCC_TCSR_ACC_SERIAL_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TCSR_ACC_SERIAL_CBCR_ADDR,m,v,HWIO_GCC_TCSR_ACC_SERIAL_CBCR_IN) +#define HWIO_GCC_TCSR_ACC_SERIAL_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TCSR_ACC_SERIAL_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TCSR_ACC_SERIAL_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_TCSR_ACC_SERIAL_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_TCSR_ACC_SERIAL_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_TCSR_ACC_SERIAL_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_TCSR_ACC_SERIAL_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_TCSR_ACC_SERIAL_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_TCSR_ACC_SERIAL_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_TCSR_ACC_SERIAL_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_TCSR_ACC_SERIAL_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_TCSR_ACC_SERIAL_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_TCSR_ACC_SERIAL_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_TCSR_ACC_SERIAL_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_TCSR_ACC_SERIAL_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_TCSR_ACC_SERIAL_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_TCSR_ACC_SERIAL_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_TCSR_ACC_SERIAL_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_TCSR_ACC_SERIAL_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_TCSR_ACC_SERIAL_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_TCSR_ACC_SERIAL_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TCSR_ACC_SERIAL_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_BOOT_ROM_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00017000) +#define HWIO_GCC_BOOT_ROM_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017000) +#define HWIO_GCC_BOOT_ROM_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017000) +#define HWIO_GCC_BOOT_ROM_BCR_RMSK 0x1 +#define HWIO_GCC_BOOT_ROM_BCR_ATTR 0x3 +#define HWIO_GCC_BOOT_ROM_BCR_IN \ + in_dword_masked(HWIO_GCC_BOOT_ROM_BCR_ADDR, HWIO_GCC_BOOT_ROM_BCR_RMSK) +#define HWIO_GCC_BOOT_ROM_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_BOOT_ROM_BCR_ADDR, m) +#define HWIO_GCC_BOOT_ROM_BCR_OUT(v) \ + out_dword(HWIO_GCC_BOOT_ROM_BCR_ADDR,v) +#define HWIO_GCC_BOOT_ROM_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BOOT_ROM_BCR_ADDR,m,v,HWIO_GCC_BOOT_ROM_BCR_IN) +#define HWIO_GCC_BOOT_ROM_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_BOOT_ROM_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_BOOT_ROM_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_BOOT_ROM_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00017004) +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017004) +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017004) +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_RMSK 0x81d07ffe +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_BOOT_ROM_AHB_CBCR_ADDR, HWIO_GCC_BOOT_ROM_AHB_CBCR_RMSK) +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_BOOT_ROM_AHB_CBCR_ADDR, m) +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_BOOT_ROM_AHB_CBCR_ADDR,v) +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BOOT_ROM_AHB_CBCR_ADDR,m,v,HWIO_GCC_BOOT_ROM_AHB_CBCR_IN) +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_WAKEUP_BMSK 0xf00 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_WAKEUP_SHFT 0x8 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_WAKEUP_CLOCK0_FVAL 0x0 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_WAKEUP_CLOCK1_FVAL 0x1 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_WAKEUP_CLOCK2_FVAL 0x2 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_WAKEUP_CLOCK3_FVAL 0x3 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_WAKEUP_CLOCK4_FVAL 0x4 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_WAKEUP_CLOCK5_FVAL 0x5 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_WAKEUP_CLOCK6_FVAL 0x6 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_WAKEUP_CLOCK7_FVAL 0x7 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_WAKEUP_CLOCK8_FVAL 0x8 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_WAKEUP_CLOCK9_FVAL 0x9 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_WAKEUP_CLOCK10_FVAL 0xa +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_WAKEUP_CLOCK11_FVAL 0xb +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_WAKEUP_CLOCK12_FVAL 0xc +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_WAKEUP_CLOCK13_FVAL 0xd +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_WAKEUP_CLOCK14_FVAL 0xe +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_WAKEUP_CLOCK15_FVAL 0xf +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_SLEEP_BMSK 0xf0 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_SLEEP_SHFT 0x4 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_SLEEP_CLOCK0_FVAL 0x0 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_SLEEP_CLOCK1_FVAL 0x1 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_SLEEP_CLOCK2_FVAL 0x2 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_SLEEP_CLOCK3_FVAL 0x3 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_SLEEP_CLOCK4_FVAL 0x4 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_SLEEP_CLOCK5_FVAL 0x5 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_SLEEP_CLOCK6_FVAL 0x6 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_SLEEP_CLOCK7_FVAL 0x7 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_SLEEP_CLOCK8_FVAL 0x8 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_SLEEP_CLOCK9_FVAL 0x9 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_SLEEP_CLOCK10_FVAL 0xa +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_SLEEP_CLOCK11_FVAL 0xb +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_SLEEP_CLOCK12_FVAL 0xc +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_SLEEP_CLOCK13_FVAL 0xd +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_SLEEP_CLOCK14_FVAL 0xe +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_SLEEP_CLOCK15_FVAL 0xf +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 + +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00017008) +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017008) +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017008) +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_RMSK 0xfffffffe +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_ATTR 0x3 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_IN \ + in_dword_masked(HWIO_GCC_BOOT_ROM_AHB_SREGR_ADDR, HWIO_GCC_BOOT_ROM_AHB_SREGR_RMSK) +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_BOOT_ROM_AHB_SREGR_ADDR, m) +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_OUT(v) \ + out_dword(HWIO_GCC_BOOT_ROM_AHB_SREGR_ADDR,v) +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BOOT_ROM_AHB_SREGR_ADDR,m,v,HWIO_GCC_BOOT_ROM_AHB_SREGR_IN) +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xff000000 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xff0000 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TLMM_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00018000) +#define HWIO_GCC_TLMM_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018000) +#define HWIO_GCC_TLMM_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018000) +#define HWIO_GCC_TLMM_BCR_RMSK 0x1 +#define HWIO_GCC_TLMM_BCR_ATTR 0x3 +#define HWIO_GCC_TLMM_BCR_IN \ + in_dword_masked(HWIO_GCC_TLMM_BCR_ADDR, HWIO_GCC_TLMM_BCR_RMSK) +#define HWIO_GCC_TLMM_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_TLMM_BCR_ADDR, m) +#define HWIO_GCC_TLMM_BCR_OUT(v) \ + out_dword(HWIO_GCC_TLMM_BCR_ADDR,v) +#define HWIO_GCC_TLMM_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TLMM_BCR_ADDR,m,v,HWIO_GCC_TLMM_BCR_IN) +#define HWIO_GCC_TLMM_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_TLMM_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_TLMM_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_TLMM_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TLMM_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00018004) +#define HWIO_GCC_TLMM_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018004) +#define HWIO_GCC_TLMM_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018004) +#define HWIO_GCC_TLMM_AHB_CBCR_RMSK 0x81d00004 +#define HWIO_GCC_TLMM_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_TLMM_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_TLMM_AHB_CBCR_ADDR, HWIO_GCC_TLMM_AHB_CBCR_RMSK) +#define HWIO_GCC_TLMM_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_TLMM_AHB_CBCR_ADDR, m) +#define HWIO_GCC_TLMM_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_TLMM_AHB_CBCR_ADDR,v) +#define HWIO_GCC_TLMM_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TLMM_AHB_CBCR_ADDR,m,v,HWIO_GCC_TLMM_AHB_CBCR_IN) +#define HWIO_GCC_TLMM_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TLMM_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TLMM_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_TLMM_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_TLMM_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_TLMM_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_TLMM_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_TLMM_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_TLMM_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_TLMM_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_TLMM_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_TLMM_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_TLMM_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_TLMM_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 + +#define HWIO_GCC_TLMM_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00018008) +#define HWIO_GCC_TLMM_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018008) +#define HWIO_GCC_TLMM_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018008) +#define HWIO_GCC_TLMM_CBCR_RMSK 0x81d00004 +#define HWIO_GCC_TLMM_CBCR_ATTR 0x3 +#define HWIO_GCC_TLMM_CBCR_IN \ + in_dword_masked(HWIO_GCC_TLMM_CBCR_ADDR, HWIO_GCC_TLMM_CBCR_RMSK) +#define HWIO_GCC_TLMM_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_TLMM_CBCR_ADDR, m) +#define HWIO_GCC_TLMM_CBCR_OUT(v) \ + out_dword(HWIO_GCC_TLMM_CBCR_ADDR,v) +#define HWIO_GCC_TLMM_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TLMM_CBCR_ADDR,m,v,HWIO_GCC_TLMM_CBCR_IN) +#define HWIO_GCC_TLMM_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TLMM_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TLMM_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_TLMM_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_TLMM_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_TLMM_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_TLMM_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_TLMM_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_TLMM_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_TLMM_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_TLMM_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_TLMM_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_TLMM_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_TLMM_CBCR_CLK_ARES_RESET_FVAL 0x1 + +#define HWIO_GCC_AOSS_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00019000) +#define HWIO_GCC_AOSS_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00019000) +#define HWIO_GCC_AOSS_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00019000) +#define HWIO_GCC_AOSS_BCR_RMSK 0x1 +#define HWIO_GCC_AOSS_BCR_ATTR 0x3 +#define HWIO_GCC_AOSS_BCR_IN \ + in_dword_masked(HWIO_GCC_AOSS_BCR_ADDR, HWIO_GCC_AOSS_BCR_RMSK) +#define HWIO_GCC_AOSS_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_AOSS_BCR_ADDR, m) +#define HWIO_GCC_AOSS_BCR_OUT(v) \ + out_dword(HWIO_GCC_AOSS_BCR_ADDR,v) +#define HWIO_GCC_AOSS_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AOSS_BCR_ADDR,m,v,HWIO_GCC_AOSS_BCR_IN) +#define HWIO_GCC_AOSS_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_AOSS_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_AOSS_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_AOSS_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_AOSS_CFG_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00019004) +#define HWIO_GCC_AOSS_CFG_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00019004) +#define HWIO_GCC_AOSS_CFG_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00019004) +#define HWIO_GCC_AOSS_CFG_AHB_CBCR_RMSK 0x81d00005 +#define HWIO_GCC_AOSS_CFG_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_AOSS_CFG_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_AOSS_CFG_AHB_CBCR_ADDR, HWIO_GCC_AOSS_CFG_AHB_CBCR_RMSK) +#define HWIO_GCC_AOSS_CFG_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_AOSS_CFG_AHB_CBCR_ADDR, m) +#define HWIO_GCC_AOSS_CFG_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_AOSS_CFG_AHB_CBCR_ADDR,v) +#define HWIO_GCC_AOSS_CFG_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AOSS_CFG_AHB_CBCR_ADDR,m,v,HWIO_GCC_AOSS_CFG_AHB_CBCR_IN) +#define HWIO_GCC_AOSS_CFG_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_AOSS_CFG_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_AOSS_CFG_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_AOSS_CFG_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_AOSS_CFG_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_AOSS_CFG_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_AOSS_CFG_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_AOSS_CFG_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_AOSS_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_AOSS_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_AOSS_CFG_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_AOSS_CFG_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_AOSS_CFG_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_AOSS_CFG_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_AOSS_CFG_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_AOSS_CFG_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_AOSS_CFG_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AOSS_CFG_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_AOSS_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00019008) +#define HWIO_GCC_AOSS_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00019008) +#define HWIO_GCC_AOSS_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00019008) +#define HWIO_GCC_AOSS_AT_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_AOSS_AT_CBCR_ATTR 0x3 +#define HWIO_GCC_AOSS_AT_CBCR_IN \ + in_dword_masked(HWIO_GCC_AOSS_AT_CBCR_ADDR, HWIO_GCC_AOSS_AT_CBCR_RMSK) +#define HWIO_GCC_AOSS_AT_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_AOSS_AT_CBCR_ADDR, m) +#define HWIO_GCC_AOSS_AT_CBCR_OUT(v) \ + out_dword(HWIO_GCC_AOSS_AT_CBCR_ADDR,v) +#define HWIO_GCC_AOSS_AT_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AOSS_AT_CBCR_ADDR,m,v,HWIO_GCC_AOSS_AT_CBCR_IN) +#define HWIO_GCC_AOSS_AT_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_AOSS_AT_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_AOSS_AT_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_AOSS_AT_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_AOSS_AT_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_AOSS_AT_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_AOSS_AT_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_AOSS_AT_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_AOSS_AT_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_AOSS_AT_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_AOSS_AT_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_AOSS_AT_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_AOSS_AT_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_AOSS_AT_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_AOSS_AT_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_AOSS_AT_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_AOSS_AT_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_AOSS_AT_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_AOSS_AT_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_AOSS_AT_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_AOSS_AT_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_AOSS_AT_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_AOSS_AT_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AOSS_AT_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SEC_CTRL_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001a000) +#define HWIO_GCC_SEC_CTRL_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001a000) +#define HWIO_GCC_SEC_CTRL_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001a000) +#define HWIO_GCC_SEC_CTRL_BCR_RMSK 0x1 +#define HWIO_GCC_SEC_CTRL_BCR_ATTR 0x3 +#define HWIO_GCC_SEC_CTRL_BCR_IN \ + in_dword_masked(HWIO_GCC_SEC_CTRL_BCR_ADDR, HWIO_GCC_SEC_CTRL_BCR_RMSK) +#define HWIO_GCC_SEC_CTRL_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_SEC_CTRL_BCR_ADDR, m) +#define HWIO_GCC_SEC_CTRL_BCR_OUT(v) \ + out_dword(HWIO_GCC_SEC_CTRL_BCR_ADDR,v) +#define HWIO_GCC_SEC_CTRL_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SEC_CTRL_BCR_ADDR,m,v,HWIO_GCC_SEC_CTRL_BCR_IN) +#define HWIO_GCC_SEC_CTRL_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_SEC_CTRL_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_SEC_CTRL_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_SEC_CTRL_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SEC_CTRL_ACC_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001a004) +#define HWIO_GCC_SEC_CTRL_ACC_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001a004) +#define HWIO_GCC_SEC_CTRL_ACC_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001a004) +#define HWIO_GCC_SEC_CTRL_ACC_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_SEC_CTRL_ACC_CBCR_ATTR 0x3 +#define HWIO_GCC_SEC_CTRL_ACC_CBCR_IN \ + in_dword_masked(HWIO_GCC_SEC_CTRL_ACC_CBCR_ADDR, HWIO_GCC_SEC_CTRL_ACC_CBCR_RMSK) +#define HWIO_GCC_SEC_CTRL_ACC_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_SEC_CTRL_ACC_CBCR_ADDR, m) +#define HWIO_GCC_SEC_CTRL_ACC_CBCR_OUT(v) \ + out_dword(HWIO_GCC_SEC_CTRL_ACC_CBCR_ADDR,v) +#define HWIO_GCC_SEC_CTRL_ACC_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SEC_CTRL_ACC_CBCR_ADDR,m,v,HWIO_GCC_SEC_CTRL_ACC_CBCR_IN) +#define HWIO_GCC_SEC_CTRL_ACC_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SEC_CTRL_ACC_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SEC_CTRL_ACC_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_SEC_CTRL_ACC_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_SEC_CTRL_ACC_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_SEC_CTRL_ACC_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_SEC_CTRL_ACC_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_SEC_CTRL_ACC_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_SEC_CTRL_ACC_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_SEC_CTRL_ACC_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_SEC_CTRL_ACC_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SEC_CTRL_ACC_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_SEC_CTRL_ACC_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SEC_CTRL_ACC_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SEC_CTRL_ACC_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SEC_CTRL_ACC_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SEC_CTRL_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001a008) +#define HWIO_GCC_SEC_CTRL_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001a008) +#define HWIO_GCC_SEC_CTRL_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001a008) +#define HWIO_GCC_SEC_CTRL_AHB_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_SEC_CTRL_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_SEC_CTRL_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_SEC_CTRL_AHB_CBCR_ADDR, HWIO_GCC_SEC_CTRL_AHB_CBCR_RMSK) +#define HWIO_GCC_SEC_CTRL_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_SEC_CTRL_AHB_CBCR_ADDR, m) +#define HWIO_GCC_SEC_CTRL_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_SEC_CTRL_AHB_CBCR_ADDR,v) +#define HWIO_GCC_SEC_CTRL_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SEC_CTRL_AHB_CBCR_ADDR,m,v,HWIO_GCC_SEC_CTRL_AHB_CBCR_IN) +#define HWIO_GCC_SEC_CTRL_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SEC_CTRL_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SEC_CTRL_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_SEC_CTRL_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_SEC_CTRL_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_SEC_CTRL_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_SEC_CTRL_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_SEC_CTRL_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_SEC_CTRL_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_SEC_CTRL_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_SEC_CTRL_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_SEC_CTRL_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_SEC_CTRL_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_SEC_CTRL_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_SEC_CTRL_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SEC_CTRL_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_SEC_CTRL_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_SEC_CTRL_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_SEC_CTRL_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_SEC_CTRL_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_SEC_CTRL_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SEC_CTRL_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SEC_CTRL_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SEC_CTRL_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SEC_CTRL_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001a00c) +#define HWIO_GCC_SEC_CTRL_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001a00c) +#define HWIO_GCC_SEC_CTRL_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001a00c) +#define HWIO_GCC_SEC_CTRL_CBCR_RMSK 0x81c07ff5 +#define HWIO_GCC_SEC_CTRL_CBCR_ATTR 0x3 +#define HWIO_GCC_SEC_CTRL_CBCR_IN \ + in_dword_masked(HWIO_GCC_SEC_CTRL_CBCR_ADDR, HWIO_GCC_SEC_CTRL_CBCR_RMSK) +#define HWIO_GCC_SEC_CTRL_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_SEC_CTRL_CBCR_ADDR, m) +#define HWIO_GCC_SEC_CTRL_CBCR_OUT(v) \ + out_dword(HWIO_GCC_SEC_CTRL_CBCR_ADDR,v) +#define HWIO_GCC_SEC_CTRL_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SEC_CTRL_CBCR_ADDR,m,v,HWIO_GCC_SEC_CTRL_CBCR_IN) +#define HWIO_GCC_SEC_CTRL_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SEC_CTRL_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SEC_CTRL_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_SEC_CTRL_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_SEC_CTRL_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_SEC_CTRL_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_SEC_CTRL_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_SEC_CTRL_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_SEC_CTRL_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_SEC_CTRL_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_SEC_CTRL_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SEC_CTRL_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SEC_CTRL_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_SEC_CTRL_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_SEC_CTRL_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SEC_CTRL_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SEC_CTRL_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_SEC_CTRL_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_SEC_CTRL_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SEC_CTRL_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SEC_CTRL_CBCR_WAKEUP_BMSK 0xf00 +#define HWIO_GCC_SEC_CTRL_CBCR_WAKEUP_SHFT 0x8 +#define HWIO_GCC_SEC_CTRL_CBCR_WAKEUP_CLOCK0_FVAL 0x0 +#define HWIO_GCC_SEC_CTRL_CBCR_WAKEUP_CLOCK1_FVAL 0x1 +#define HWIO_GCC_SEC_CTRL_CBCR_WAKEUP_CLOCK2_FVAL 0x2 +#define HWIO_GCC_SEC_CTRL_CBCR_WAKEUP_CLOCK3_FVAL 0x3 +#define HWIO_GCC_SEC_CTRL_CBCR_WAKEUP_CLOCK4_FVAL 0x4 +#define HWIO_GCC_SEC_CTRL_CBCR_WAKEUP_CLOCK5_FVAL 0x5 +#define HWIO_GCC_SEC_CTRL_CBCR_WAKEUP_CLOCK6_FVAL 0x6 +#define HWIO_GCC_SEC_CTRL_CBCR_WAKEUP_CLOCK7_FVAL 0x7 +#define HWIO_GCC_SEC_CTRL_CBCR_WAKEUP_CLOCK8_FVAL 0x8 +#define HWIO_GCC_SEC_CTRL_CBCR_WAKEUP_CLOCK9_FVAL 0x9 +#define HWIO_GCC_SEC_CTRL_CBCR_WAKEUP_CLOCK10_FVAL 0xa +#define HWIO_GCC_SEC_CTRL_CBCR_WAKEUP_CLOCK11_FVAL 0xb +#define HWIO_GCC_SEC_CTRL_CBCR_WAKEUP_CLOCK12_FVAL 0xc +#define HWIO_GCC_SEC_CTRL_CBCR_WAKEUP_CLOCK13_FVAL 0xd +#define HWIO_GCC_SEC_CTRL_CBCR_WAKEUP_CLOCK14_FVAL 0xe +#define HWIO_GCC_SEC_CTRL_CBCR_WAKEUP_CLOCK15_FVAL 0xf +#define HWIO_GCC_SEC_CTRL_CBCR_SLEEP_BMSK 0xf0 +#define HWIO_GCC_SEC_CTRL_CBCR_SLEEP_SHFT 0x4 +#define HWIO_GCC_SEC_CTRL_CBCR_SLEEP_CLOCK0_FVAL 0x0 +#define HWIO_GCC_SEC_CTRL_CBCR_SLEEP_CLOCK1_FVAL 0x1 +#define HWIO_GCC_SEC_CTRL_CBCR_SLEEP_CLOCK2_FVAL 0x2 +#define HWIO_GCC_SEC_CTRL_CBCR_SLEEP_CLOCK3_FVAL 0x3 +#define HWIO_GCC_SEC_CTRL_CBCR_SLEEP_CLOCK4_FVAL 0x4 +#define HWIO_GCC_SEC_CTRL_CBCR_SLEEP_CLOCK5_FVAL 0x5 +#define HWIO_GCC_SEC_CTRL_CBCR_SLEEP_CLOCK6_FVAL 0x6 +#define HWIO_GCC_SEC_CTRL_CBCR_SLEEP_CLOCK7_FVAL 0x7 +#define HWIO_GCC_SEC_CTRL_CBCR_SLEEP_CLOCK8_FVAL 0x8 +#define HWIO_GCC_SEC_CTRL_CBCR_SLEEP_CLOCK9_FVAL 0x9 +#define HWIO_GCC_SEC_CTRL_CBCR_SLEEP_CLOCK10_FVAL 0xa +#define HWIO_GCC_SEC_CTRL_CBCR_SLEEP_CLOCK11_FVAL 0xb +#define HWIO_GCC_SEC_CTRL_CBCR_SLEEP_CLOCK12_FVAL 0xc +#define HWIO_GCC_SEC_CTRL_CBCR_SLEEP_CLOCK13_FVAL 0xd +#define HWIO_GCC_SEC_CTRL_CBCR_SLEEP_CLOCK14_FVAL 0xe +#define HWIO_GCC_SEC_CTRL_CBCR_SLEEP_CLOCK15_FVAL 0xf +#define HWIO_GCC_SEC_CTRL_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_SEC_CTRL_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_SEC_CTRL_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SEC_CTRL_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_SEC_CTRL_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SEC_CTRL_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SEC_CTRL_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SEC_CTRL_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SEC_CTRL_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001a010) +#define HWIO_GCC_SEC_CTRL_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001a010) +#define HWIO_GCC_SEC_CTRL_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001a010) +#define HWIO_GCC_SEC_CTRL_SREGR_RMSK 0xfffffffe +#define HWIO_GCC_SEC_CTRL_SREGR_ATTR 0x3 +#define HWIO_GCC_SEC_CTRL_SREGR_IN \ + in_dword_masked(HWIO_GCC_SEC_CTRL_SREGR_ADDR, HWIO_GCC_SEC_CTRL_SREGR_RMSK) +#define HWIO_GCC_SEC_CTRL_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_SEC_CTRL_SREGR_ADDR, m) +#define HWIO_GCC_SEC_CTRL_SREGR_OUT(v) \ + out_dword(HWIO_GCC_SEC_CTRL_SREGR_ADDR,v) +#define HWIO_GCC_SEC_CTRL_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SEC_CTRL_SREGR_ADDR,m,v,HWIO_GCC_SEC_CTRL_SREGR_IN) +#define HWIO_GCC_SEC_CTRL_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xff000000 +#define HWIO_GCC_SEC_CTRL_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_SEC_CTRL_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xff0000 +#define HWIO_GCC_SEC_CTRL_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_SEC_CTRL_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_SEC_CTRL_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_SEC_CTRL_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_SEC_CTRL_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_SEC_CTRL_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_SEC_CTRL_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_SEC_CTRL_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_SEC_CTRL_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_SEC_CTRL_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_SEC_CTRL_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_SEC_CTRL_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_SEC_CTRL_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_SEC_CTRL_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_SEC_CTRL_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_SEC_CTRL_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SEC_CTRL_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_SEC_CTRL_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_SEC_CTRL_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_SEC_CTRL_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_SEC_CTRL_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_SEC_CTRL_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_SEC_CTRL_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_SEC_CTRL_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_SEC_CTRL_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_SEC_CTRL_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_SEC_CTRL_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_SEC_CTRL_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_SEC_CTRL_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_SEC_CTRL_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SEC_CTRL_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SEC_CTRL_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_SEC_CTRL_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_SEC_CTRL_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_SEC_CTRL_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SEC_CTRL_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_SEC_CTRL_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_SEC_CTRL_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_SEC_CTRL_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_SEC_CTRL_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_SEC_CTRL_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_SEC_CTRL_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_SEC_CTRL_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_SEC_CTRL_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_SEC_CTRL_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_SEC_CTRL_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_SEC_CTRL_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_SEC_CTRL_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_SEC_CTRL_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_SEC_CTRL_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_SEC_CTRL_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_SEC_CTRL_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_SEC_CTRL_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_SEC_CTRL_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_SEC_CTRL_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SEC_CTRL_SENSE_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001a014) +#define HWIO_GCC_SEC_CTRL_SENSE_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001a014) +#define HWIO_GCC_SEC_CTRL_SENSE_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001a014) +#define HWIO_GCC_SEC_CTRL_SENSE_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_SEC_CTRL_SENSE_CBCR_ATTR 0x3 +#define HWIO_GCC_SEC_CTRL_SENSE_CBCR_IN \ + in_dword_masked(HWIO_GCC_SEC_CTRL_SENSE_CBCR_ADDR, HWIO_GCC_SEC_CTRL_SENSE_CBCR_RMSK) +#define HWIO_GCC_SEC_CTRL_SENSE_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_SEC_CTRL_SENSE_CBCR_ADDR, m) +#define HWIO_GCC_SEC_CTRL_SENSE_CBCR_OUT(v) \ + out_dword(HWIO_GCC_SEC_CTRL_SENSE_CBCR_ADDR,v) +#define HWIO_GCC_SEC_CTRL_SENSE_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SEC_CTRL_SENSE_CBCR_ADDR,m,v,HWIO_GCC_SEC_CTRL_SENSE_CBCR_IN) +#define HWIO_GCC_SEC_CTRL_SENSE_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SEC_CTRL_SENSE_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SEC_CTRL_SENSE_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_SEC_CTRL_SENSE_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_SEC_CTRL_SENSE_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_SEC_CTRL_SENSE_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_SEC_CTRL_SENSE_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_SEC_CTRL_SENSE_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_SEC_CTRL_SENSE_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_SEC_CTRL_SENSE_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_SEC_CTRL_SENSE_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SEC_CTRL_SENSE_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_SEC_CTRL_SENSE_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SEC_CTRL_SENSE_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SEC_CTRL_SENSE_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SEC_CTRL_SENSE_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SEC_CTRL_BOOT_ROM_PATCH_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001a018) +#define HWIO_GCC_SEC_CTRL_BOOT_ROM_PATCH_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001a018) +#define HWIO_GCC_SEC_CTRL_BOOT_ROM_PATCH_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001a018) +#define HWIO_GCC_SEC_CTRL_BOOT_ROM_PATCH_CBCR_RMSK 0x81d00005 +#define HWIO_GCC_SEC_CTRL_BOOT_ROM_PATCH_CBCR_ATTR 0x3 +#define HWIO_GCC_SEC_CTRL_BOOT_ROM_PATCH_CBCR_IN \ + in_dword_masked(HWIO_GCC_SEC_CTRL_BOOT_ROM_PATCH_CBCR_ADDR, HWIO_GCC_SEC_CTRL_BOOT_ROM_PATCH_CBCR_RMSK) +#define HWIO_GCC_SEC_CTRL_BOOT_ROM_PATCH_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_SEC_CTRL_BOOT_ROM_PATCH_CBCR_ADDR, m) +#define HWIO_GCC_SEC_CTRL_BOOT_ROM_PATCH_CBCR_OUT(v) \ + out_dword(HWIO_GCC_SEC_CTRL_BOOT_ROM_PATCH_CBCR_ADDR,v) +#define HWIO_GCC_SEC_CTRL_BOOT_ROM_PATCH_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SEC_CTRL_BOOT_ROM_PATCH_CBCR_ADDR,m,v,HWIO_GCC_SEC_CTRL_BOOT_ROM_PATCH_CBCR_IN) +#define HWIO_GCC_SEC_CTRL_BOOT_ROM_PATCH_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SEC_CTRL_BOOT_ROM_PATCH_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SEC_CTRL_BOOT_ROM_PATCH_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_SEC_CTRL_BOOT_ROM_PATCH_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_SEC_CTRL_BOOT_ROM_PATCH_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_SEC_CTRL_BOOT_ROM_PATCH_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_SEC_CTRL_BOOT_ROM_PATCH_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_SEC_CTRL_BOOT_ROM_PATCH_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_SEC_CTRL_BOOT_ROM_PATCH_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_SEC_CTRL_BOOT_ROM_PATCH_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_SEC_CTRL_BOOT_ROM_PATCH_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_SEC_CTRL_BOOT_ROM_PATCH_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_SEC_CTRL_BOOT_ROM_PATCH_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SEC_CTRL_BOOT_ROM_PATCH_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_SEC_CTRL_BOOT_ROM_PATCH_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SEC_CTRL_BOOT_ROM_PATCH_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SEC_CTRL_BOOT_ROM_PATCH_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SEC_CTRL_BOOT_ROM_PATCH_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_ACC_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001a01c) +#define HWIO_GCC_ACC_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001a01c) +#define HWIO_GCC_ACC_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001a01c) +#define HWIO_GCC_ACC_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_ACC_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_ACC_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_ACC_CMD_RCGR_ADDR, HWIO_GCC_ACC_CMD_RCGR_RMSK) +#define HWIO_GCC_ACC_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_ACC_CMD_RCGR_ADDR, m) +#define HWIO_GCC_ACC_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_ACC_CMD_RCGR_ADDR,v) +#define HWIO_GCC_ACC_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ACC_CMD_RCGR_ADDR,m,v,HWIO_GCC_ACC_CMD_RCGR_IN) +#define HWIO_GCC_ACC_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_ACC_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_ACC_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_ACC_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_ACC_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_ACC_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_ACC_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_ACC_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_ACC_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_ACC_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_ACC_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_ACC_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_ACC_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001a020) +#define HWIO_GCC_ACC_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001a020) +#define HWIO_GCC_ACC_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001a020) +#define HWIO_GCC_ACC_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_ACC_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_ACC_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_ACC_CFG_RCGR_ADDR, HWIO_GCC_ACC_CFG_RCGR_RMSK) +#define HWIO_GCC_ACC_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_ACC_CFG_RCGR_ADDR, m) +#define HWIO_GCC_ACC_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_ACC_CFG_RCGR_ADDR,v) +#define HWIO_GCC_ACC_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ACC_CFG_RCGR_ADDR,m,v,HWIO_GCC_ACC_CFG_RCGR_IN) +#define HWIO_GCC_ACC_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_ACC_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_ACC_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_ACC_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_ACC_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_ACC_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_ACC_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_ACC_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_ACC_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_ACC_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_ACC_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_ACC_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_ACC_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_ACC_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_ACC_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_ACC_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_ACC_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_ACC_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_ACC_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_ACC_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_ACC_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_ACC_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_ACC_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_ACC_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_ACC_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_ACC_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_ACC_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_ACC_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_ACC_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_ACC_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_ACC_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_ACC_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_ACC_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_ACC_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_ACC_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_ACC_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_ACC_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_ACC_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_ACC_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_ACC_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_ACC_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_ACC_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_ACC_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_ACC_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_ACC_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_ACC_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_ACC_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_ACC_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_ACC_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_ACC_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_ACC_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_ACC_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_SEC_CTRL_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001a034) +#define HWIO_GCC_SEC_CTRL_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001a034) +#define HWIO_GCC_SEC_CTRL_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001a034) +#define HWIO_GCC_SEC_CTRL_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_SEC_CTRL_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_SEC_CTRL_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_SEC_CTRL_CMD_RCGR_ADDR, HWIO_GCC_SEC_CTRL_CMD_RCGR_RMSK) +#define HWIO_GCC_SEC_CTRL_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_SEC_CTRL_CMD_RCGR_ADDR, m) +#define HWIO_GCC_SEC_CTRL_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_SEC_CTRL_CMD_RCGR_ADDR,v) +#define HWIO_GCC_SEC_CTRL_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SEC_CTRL_CMD_RCGR_ADDR,m,v,HWIO_GCC_SEC_CTRL_CMD_RCGR_IN) +#define HWIO_GCC_SEC_CTRL_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_SEC_CTRL_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_SEC_CTRL_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_SEC_CTRL_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_SEC_CTRL_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_SEC_CTRL_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_SEC_CTRL_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_SEC_CTRL_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_SEC_CTRL_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_SEC_CTRL_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_SEC_CTRL_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SEC_CTRL_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001a038) +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001a038) +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001a038) +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_SEC_CTRL_CFG_RCGR_ADDR, HWIO_GCC_SEC_CTRL_CFG_RCGR_RMSK) +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_SEC_CTRL_CFG_RCGR_ADDR, m) +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_SEC_CTRL_CFG_RCGR_ADDR,v) +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SEC_CTRL_CFG_RCGR_ADDR,m,v,HWIO_GCC_SEC_CTRL_CFG_RCGR_IN) +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_SPDM_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001b000) +#define HWIO_GCC_SPDM_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001b000) +#define HWIO_GCC_SPDM_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001b000) +#define HWIO_GCC_SPDM_BCR_RMSK 0x1 +#define HWIO_GCC_SPDM_BCR_ATTR 0x3 +#define HWIO_GCC_SPDM_BCR_IN \ + in_dword_masked(HWIO_GCC_SPDM_BCR_ADDR, HWIO_GCC_SPDM_BCR_RMSK) +#define HWIO_GCC_SPDM_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_SPDM_BCR_ADDR, m) +#define HWIO_GCC_SPDM_BCR_OUT(v) \ + out_dword(HWIO_GCC_SPDM_BCR_ADDR,v) +#define HWIO_GCC_SPDM_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPDM_BCR_ADDR,m,v,HWIO_GCC_SPDM_BCR_IN) +#define HWIO_GCC_SPDM_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_SPDM_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_SPDM_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPDM_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPDM_CFG_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001b004) +#define HWIO_GCC_SPDM_CFG_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001b004) +#define HWIO_GCC_SPDM_CFG_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001b004) +#define HWIO_GCC_SPDM_CFG_AHB_CBCR_RMSK 0x81d00005 +#define HWIO_GCC_SPDM_CFG_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_SPDM_CFG_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_SPDM_CFG_AHB_CBCR_ADDR, HWIO_GCC_SPDM_CFG_AHB_CBCR_RMSK) +#define HWIO_GCC_SPDM_CFG_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_SPDM_CFG_AHB_CBCR_ADDR, m) +#define HWIO_GCC_SPDM_CFG_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_SPDM_CFG_AHB_CBCR_ADDR,v) +#define HWIO_GCC_SPDM_CFG_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPDM_CFG_AHB_CBCR_ADDR,m,v,HWIO_GCC_SPDM_CFG_AHB_CBCR_IN) +#define HWIO_GCC_SPDM_CFG_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SPDM_CFG_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SPDM_CFG_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_SPDM_CFG_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_SPDM_CFG_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_SPDM_CFG_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_SPDM_CFG_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_SPDM_CFG_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_SPDM_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_SPDM_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_SPDM_CFG_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_SPDM_CFG_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_SPDM_CFG_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SPDM_CFG_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_SPDM_CFG_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SPDM_CFG_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SPDM_CFG_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPDM_CFG_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPDM_MSTR_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001b008) +#define HWIO_GCC_SPDM_MSTR_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001b008) +#define HWIO_GCC_SPDM_MSTR_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001b008) +#define HWIO_GCC_SPDM_MSTR_AHB_CBCR_RMSK 0x81d00005 +#define HWIO_GCC_SPDM_MSTR_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_SPDM_MSTR_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_SPDM_MSTR_AHB_CBCR_ADDR, HWIO_GCC_SPDM_MSTR_AHB_CBCR_RMSK) +#define HWIO_GCC_SPDM_MSTR_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_SPDM_MSTR_AHB_CBCR_ADDR, m) +#define HWIO_GCC_SPDM_MSTR_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_SPDM_MSTR_AHB_CBCR_ADDR,v) +#define HWIO_GCC_SPDM_MSTR_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPDM_MSTR_AHB_CBCR_ADDR,m,v,HWIO_GCC_SPDM_MSTR_AHB_CBCR_IN) +#define HWIO_GCC_SPDM_MSTR_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SPDM_MSTR_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SPDM_MSTR_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_SPDM_MSTR_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_SPDM_MSTR_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_SPDM_MSTR_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_SPDM_MSTR_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_SPDM_MSTR_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_SPDM_MSTR_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_SPDM_MSTR_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_SPDM_MSTR_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_SPDM_MSTR_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_SPDM_MSTR_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SPDM_MSTR_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_SPDM_MSTR_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SPDM_MSTR_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SPDM_MSTR_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPDM_MSTR_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPDM_FF_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001b00c) +#define HWIO_GCC_SPDM_FF_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001b00c) +#define HWIO_GCC_SPDM_FF_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001b00c) +#define HWIO_GCC_SPDM_FF_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_SPDM_FF_CBCR_ATTR 0x3 +#define HWIO_GCC_SPDM_FF_CBCR_IN \ + in_dword_masked(HWIO_GCC_SPDM_FF_CBCR_ADDR, HWIO_GCC_SPDM_FF_CBCR_RMSK) +#define HWIO_GCC_SPDM_FF_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_SPDM_FF_CBCR_ADDR, m) +#define HWIO_GCC_SPDM_FF_CBCR_OUT(v) \ + out_dword(HWIO_GCC_SPDM_FF_CBCR_ADDR,v) +#define HWIO_GCC_SPDM_FF_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPDM_FF_CBCR_ADDR,m,v,HWIO_GCC_SPDM_FF_CBCR_IN) +#define HWIO_GCC_SPDM_FF_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SPDM_FF_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SPDM_FF_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_SPDM_FF_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_SPDM_FF_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_SPDM_FF_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_SPDM_FF_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_SPDM_FF_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_SPDM_FF_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_SPDM_FF_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_SPDM_FF_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SPDM_FF_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_SPDM_FF_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SPDM_FF_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SPDM_FF_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPDM_FF_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001b010) +#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001b010) +#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001b010) +#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_RMSK 0x81d00005 +#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_ATTR 0x3 +#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_IN \ + in_dword_masked(HWIO_GCC_SPDM_MEMNOC_CY_CBCR_ADDR, HWIO_GCC_SPDM_MEMNOC_CY_CBCR_RMSK) +#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_SPDM_MEMNOC_CY_CBCR_ADDR, m) +#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_OUT(v) \ + out_dword(HWIO_GCC_SPDM_MEMNOC_CY_CBCR_ADDR,v) +#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPDM_MEMNOC_CY_CBCR_ADDR,m,v,HWIO_GCC_SPDM_MEMNOC_CY_CBCR_IN) +#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPDM_SNOC_CY_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001b014) +#define HWIO_GCC_SPDM_SNOC_CY_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001b014) +#define HWIO_GCC_SPDM_SNOC_CY_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001b014) +#define HWIO_GCC_SPDM_SNOC_CY_CBCR_RMSK 0x81d00005 +#define HWIO_GCC_SPDM_SNOC_CY_CBCR_ATTR 0x3 +#define HWIO_GCC_SPDM_SNOC_CY_CBCR_IN \ + in_dword_masked(HWIO_GCC_SPDM_SNOC_CY_CBCR_ADDR, HWIO_GCC_SPDM_SNOC_CY_CBCR_RMSK) +#define HWIO_GCC_SPDM_SNOC_CY_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_SPDM_SNOC_CY_CBCR_ADDR, m) +#define HWIO_GCC_SPDM_SNOC_CY_CBCR_OUT(v) \ + out_dword(HWIO_GCC_SPDM_SNOC_CY_CBCR_ADDR,v) +#define HWIO_GCC_SPDM_SNOC_CY_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPDM_SNOC_CY_CBCR_ADDR,m,v,HWIO_GCC_SPDM_SNOC_CY_CBCR_IN) +#define HWIO_GCC_SPDM_SNOC_CY_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SPDM_SNOC_CY_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SPDM_SNOC_CY_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_SPDM_SNOC_CY_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_SPDM_SNOC_CY_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_SPDM_SNOC_CY_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_SPDM_SNOC_CY_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_SPDM_SNOC_CY_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_SPDM_SNOC_CY_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_SPDM_SNOC_CY_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_SPDM_SNOC_CY_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_SPDM_SNOC_CY_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_SPDM_SNOC_CY_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SPDM_SNOC_CY_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_SPDM_SNOC_CY_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SPDM_SNOC_CY_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SPDM_SNOC_CY_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPDM_SNOC_CY_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001b018) +#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001b018) +#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001b018) +#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_ATTR 0x3 +#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_IN \ + in_dword_masked(HWIO_GCC_SPDM_DEBUG_CY_CBCR_ADDR, HWIO_GCC_SPDM_DEBUG_CY_CBCR_RMSK) +#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_SPDM_DEBUG_CY_CBCR_ADDR, m) +#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_OUT(v) \ + out_dword(HWIO_GCC_SPDM_DEBUG_CY_CBCR_ADDR,v) +#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPDM_DEBUG_CY_CBCR_ADDR,m,v,HWIO_GCC_SPDM_DEBUG_CY_CBCR_IN) +#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_EFABRIC_SPDM_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001b01c) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_EFABRIC_SPDM_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001b01c) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_EFABRIC_SPDM_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001b01c) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_EFABRIC_SPDM_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_EFABRIC_SPDM_CBCR_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_EFABRIC_SPDM_CBCR_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_AHBFABRIC_EFABRIC_SPDM_CBCR_ADDR, HWIO_GCC_ULTAUDIO_AHBFABRIC_EFABRIC_SPDM_CBCR_RMSK) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_EFABRIC_SPDM_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_AHBFABRIC_EFABRIC_SPDM_CBCR_ADDR, m) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_EFABRIC_SPDM_CBCR_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_AHBFABRIC_EFABRIC_SPDM_CBCR_ADDR,v) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_EFABRIC_SPDM_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_AHBFABRIC_EFABRIC_SPDM_CBCR_ADDR,m,v,HWIO_GCC_ULTAUDIO_AHBFABRIC_EFABRIC_SPDM_CBCR_IN) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_EFABRIC_SPDM_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_EFABRIC_SPDM_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_EFABRIC_SPDM_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_EFABRIC_SPDM_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_EFABRIC_SPDM_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_EFABRIC_SPDM_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_EFABRIC_SPDM_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_EFABRIC_SPDM_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_EFABRIC_SPDM_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_EFABRIC_SPDM_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_EFABRIC_SPDM_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_EFABRIC_SPDM_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_EFABRIC_SPDM_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_EFABRIC_SPDM_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_EFABRIC_SPDM_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_EFABRIC_SPDM_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPDM_PNOC_CY_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001b020) +#define HWIO_GCC_SPDM_PNOC_CY_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001b020) +#define HWIO_GCC_SPDM_PNOC_CY_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001b020) +#define HWIO_GCC_SPDM_PNOC_CY_CBCR_RMSK 0x81d00005 +#define HWIO_GCC_SPDM_PNOC_CY_CBCR_ATTR 0x3 +#define HWIO_GCC_SPDM_PNOC_CY_CBCR_IN \ + in_dword_masked(HWIO_GCC_SPDM_PNOC_CY_CBCR_ADDR, HWIO_GCC_SPDM_PNOC_CY_CBCR_RMSK) +#define HWIO_GCC_SPDM_PNOC_CY_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_SPDM_PNOC_CY_CBCR_ADDR, m) +#define HWIO_GCC_SPDM_PNOC_CY_CBCR_OUT(v) \ + out_dword(HWIO_GCC_SPDM_PNOC_CY_CBCR_ADDR,v) +#define HWIO_GCC_SPDM_PNOC_CY_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPDM_PNOC_CY_CBCR_ADDR,m,v,HWIO_GCC_SPDM_PNOC_CY_CBCR_IN) +#define HWIO_GCC_SPDM_PNOC_CY_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SPDM_PNOC_CY_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SPDM_PNOC_CY_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_SPDM_PNOC_CY_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_SPDM_PNOC_CY_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_SPDM_PNOC_CY_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_SPDM_PNOC_CY_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_SPDM_PNOC_CY_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_SPDM_PNOC_CY_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_SPDM_PNOC_CY_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_SPDM_PNOC_CY_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_SPDM_PNOC_CY_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_SPDM_PNOC_CY_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SPDM_PNOC_CY_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_SPDM_PNOC_CY_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SPDM_PNOC_CY_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SPDM_PNOC_CY_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPDM_PNOC_CY_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPDM_MEMNOC_CY_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001b024) +#define HWIO_GCC_SPDM_MEMNOC_CY_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001b024) +#define HWIO_GCC_SPDM_MEMNOC_CY_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001b024) +#define HWIO_GCC_SPDM_MEMNOC_CY_CDIVR_RMSK 0xf +#define HWIO_GCC_SPDM_MEMNOC_CY_CDIVR_ATTR 0x3 +#define HWIO_GCC_SPDM_MEMNOC_CY_CDIVR_IN \ + in_dword_masked(HWIO_GCC_SPDM_MEMNOC_CY_CDIVR_ADDR, HWIO_GCC_SPDM_MEMNOC_CY_CDIVR_RMSK) +#define HWIO_GCC_SPDM_MEMNOC_CY_CDIVR_INM(m) \ + in_dword_masked(HWIO_GCC_SPDM_MEMNOC_CY_CDIVR_ADDR, m) +#define HWIO_GCC_SPDM_MEMNOC_CY_CDIVR_OUT(v) \ + out_dword(HWIO_GCC_SPDM_MEMNOC_CY_CDIVR_ADDR,v) +#define HWIO_GCC_SPDM_MEMNOC_CY_CDIVR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPDM_MEMNOC_CY_CDIVR_ADDR,m,v,HWIO_GCC_SPDM_MEMNOC_CY_CDIVR_IN) +#define HWIO_GCC_SPDM_MEMNOC_CY_CDIVR_CLK_DIV_BMSK 0xf +#define HWIO_GCC_SPDM_MEMNOC_CY_CDIVR_CLK_DIV_SHFT 0x0 + +#define HWIO_GCC_SPDM_SNOC_CY_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001b028) +#define HWIO_GCC_SPDM_SNOC_CY_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001b028) +#define HWIO_GCC_SPDM_SNOC_CY_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001b028) +#define HWIO_GCC_SPDM_SNOC_CY_CDIVR_RMSK 0xf +#define HWIO_GCC_SPDM_SNOC_CY_CDIVR_ATTR 0x3 +#define HWIO_GCC_SPDM_SNOC_CY_CDIVR_IN \ + in_dword_masked(HWIO_GCC_SPDM_SNOC_CY_CDIVR_ADDR, HWIO_GCC_SPDM_SNOC_CY_CDIVR_RMSK) +#define HWIO_GCC_SPDM_SNOC_CY_CDIVR_INM(m) \ + in_dword_masked(HWIO_GCC_SPDM_SNOC_CY_CDIVR_ADDR, m) +#define HWIO_GCC_SPDM_SNOC_CY_CDIVR_OUT(v) \ + out_dword(HWIO_GCC_SPDM_SNOC_CY_CDIVR_ADDR,v) +#define HWIO_GCC_SPDM_SNOC_CY_CDIVR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPDM_SNOC_CY_CDIVR_ADDR,m,v,HWIO_GCC_SPDM_SNOC_CY_CDIVR_IN) +#define HWIO_GCC_SPDM_SNOC_CY_CDIVR_CLK_DIV_BMSK 0xf +#define HWIO_GCC_SPDM_SNOC_CY_CDIVR_CLK_DIV_SHFT 0x0 + +#define HWIO_GCC_SPDM_DEBUG_CY_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001b02c) +#define HWIO_GCC_SPDM_DEBUG_CY_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001b02c) +#define HWIO_GCC_SPDM_DEBUG_CY_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001b02c) +#define HWIO_GCC_SPDM_DEBUG_CY_CDIVR_RMSK 0xf +#define HWIO_GCC_SPDM_DEBUG_CY_CDIVR_ATTR 0x3 +#define HWIO_GCC_SPDM_DEBUG_CY_CDIVR_IN \ + in_dword_masked(HWIO_GCC_SPDM_DEBUG_CY_CDIVR_ADDR, HWIO_GCC_SPDM_DEBUG_CY_CDIVR_RMSK) +#define HWIO_GCC_SPDM_DEBUG_CY_CDIVR_INM(m) \ + in_dword_masked(HWIO_GCC_SPDM_DEBUG_CY_CDIVR_ADDR, m) +#define HWIO_GCC_SPDM_DEBUG_CY_CDIVR_OUT(v) \ + out_dword(HWIO_GCC_SPDM_DEBUG_CY_CDIVR_ADDR,v) +#define HWIO_GCC_SPDM_DEBUG_CY_CDIVR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPDM_DEBUG_CY_CDIVR_ADDR,m,v,HWIO_GCC_SPDM_DEBUG_CY_CDIVR_IN) +#define HWIO_GCC_SPDM_DEBUG_CY_CDIVR_CLK_DIV_BMSK 0xf +#define HWIO_GCC_SPDM_DEBUG_CY_CDIVR_CLK_DIV_SHFT 0x0 + +#define HWIO_GCC_CE1_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001c000) +#define HWIO_GCC_CE1_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001c000) +#define HWIO_GCC_CE1_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001c000) +#define HWIO_GCC_CE1_BCR_RMSK 0x1 +#define HWIO_GCC_CE1_BCR_ATTR 0x3 +#define HWIO_GCC_CE1_BCR_IN \ + in_dword_masked(HWIO_GCC_CE1_BCR_ADDR, HWIO_GCC_CE1_BCR_RMSK) +#define HWIO_GCC_CE1_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_CE1_BCR_ADDR, m) +#define HWIO_GCC_CE1_BCR_OUT(v) \ + out_dword(HWIO_GCC_CE1_BCR_ADDR,v) +#define HWIO_GCC_CE1_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CE1_BCR_ADDR,m,v,HWIO_GCC_CE1_BCR_IN) +#define HWIO_GCC_CE1_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_CE1_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_CE1_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_CE1_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CE1_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001c004) +#define HWIO_GCC_CE1_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001c004) +#define HWIO_GCC_CE1_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001c004) +#define HWIO_GCC_CE1_CBCR_RMSK 0x81d07ff4 +#define HWIO_GCC_CE1_CBCR_ATTR 0x3 +#define HWIO_GCC_CE1_CBCR_IN \ + in_dword_masked(HWIO_GCC_CE1_CBCR_ADDR, HWIO_GCC_CE1_CBCR_RMSK) +#define HWIO_GCC_CE1_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_CE1_CBCR_ADDR, m) +#define HWIO_GCC_CE1_CBCR_OUT(v) \ + out_dword(HWIO_GCC_CE1_CBCR_ADDR,v) +#define HWIO_GCC_CE1_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CE1_CBCR_ADDR,m,v,HWIO_GCC_CE1_CBCR_IN) +#define HWIO_GCC_CE1_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_CE1_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_CE1_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_CE1_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_CE1_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_CE1_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_CE1_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_CE1_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_CE1_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_CE1_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_CE1_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_CE1_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_CE1_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CE1_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_CE1_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_CE1_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_CE1_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CE1_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_CE1_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_CE1_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_CE1_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CE1_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_CE1_CBCR_WAKEUP_BMSK 0xf00 +#define HWIO_GCC_CE1_CBCR_WAKEUP_SHFT 0x8 +#define HWIO_GCC_CE1_CBCR_WAKEUP_CLOCK0_FVAL 0x0 +#define HWIO_GCC_CE1_CBCR_WAKEUP_CLOCK1_FVAL 0x1 +#define HWIO_GCC_CE1_CBCR_WAKEUP_CLOCK2_FVAL 0x2 +#define HWIO_GCC_CE1_CBCR_WAKEUP_CLOCK3_FVAL 0x3 +#define HWIO_GCC_CE1_CBCR_WAKEUP_CLOCK4_FVAL 0x4 +#define HWIO_GCC_CE1_CBCR_WAKEUP_CLOCK5_FVAL 0x5 +#define HWIO_GCC_CE1_CBCR_WAKEUP_CLOCK6_FVAL 0x6 +#define HWIO_GCC_CE1_CBCR_WAKEUP_CLOCK7_FVAL 0x7 +#define HWIO_GCC_CE1_CBCR_WAKEUP_CLOCK8_FVAL 0x8 +#define HWIO_GCC_CE1_CBCR_WAKEUP_CLOCK9_FVAL 0x9 +#define HWIO_GCC_CE1_CBCR_WAKEUP_CLOCK10_FVAL 0xa +#define HWIO_GCC_CE1_CBCR_WAKEUP_CLOCK11_FVAL 0xb +#define HWIO_GCC_CE1_CBCR_WAKEUP_CLOCK12_FVAL 0xc +#define HWIO_GCC_CE1_CBCR_WAKEUP_CLOCK13_FVAL 0xd +#define HWIO_GCC_CE1_CBCR_WAKEUP_CLOCK14_FVAL 0xe +#define HWIO_GCC_CE1_CBCR_WAKEUP_CLOCK15_FVAL 0xf +#define HWIO_GCC_CE1_CBCR_SLEEP_BMSK 0xf0 +#define HWIO_GCC_CE1_CBCR_SLEEP_SHFT 0x4 +#define HWIO_GCC_CE1_CBCR_SLEEP_CLOCK0_FVAL 0x0 +#define HWIO_GCC_CE1_CBCR_SLEEP_CLOCK1_FVAL 0x1 +#define HWIO_GCC_CE1_CBCR_SLEEP_CLOCK2_FVAL 0x2 +#define HWIO_GCC_CE1_CBCR_SLEEP_CLOCK3_FVAL 0x3 +#define HWIO_GCC_CE1_CBCR_SLEEP_CLOCK4_FVAL 0x4 +#define HWIO_GCC_CE1_CBCR_SLEEP_CLOCK5_FVAL 0x5 +#define HWIO_GCC_CE1_CBCR_SLEEP_CLOCK6_FVAL 0x6 +#define HWIO_GCC_CE1_CBCR_SLEEP_CLOCK7_FVAL 0x7 +#define HWIO_GCC_CE1_CBCR_SLEEP_CLOCK8_FVAL 0x8 +#define HWIO_GCC_CE1_CBCR_SLEEP_CLOCK9_FVAL 0x9 +#define HWIO_GCC_CE1_CBCR_SLEEP_CLOCK10_FVAL 0xa +#define HWIO_GCC_CE1_CBCR_SLEEP_CLOCK11_FVAL 0xb +#define HWIO_GCC_CE1_CBCR_SLEEP_CLOCK12_FVAL 0xc +#define HWIO_GCC_CE1_CBCR_SLEEP_CLOCK13_FVAL 0xd +#define HWIO_GCC_CE1_CBCR_SLEEP_CLOCK14_FVAL 0xe +#define HWIO_GCC_CE1_CBCR_SLEEP_CLOCK15_FVAL 0xf +#define HWIO_GCC_CE1_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_CE1_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_CE1_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_CE1_CBCR_CLK_ARES_RESET_FVAL 0x1 + +#define HWIO_GCC_CE1_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001c008) +#define HWIO_GCC_CE1_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001c008) +#define HWIO_GCC_CE1_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001c008) +#define HWIO_GCC_CE1_SREGR_RMSK 0xfffffffe +#define HWIO_GCC_CE1_SREGR_ATTR 0x3 +#define HWIO_GCC_CE1_SREGR_IN \ + in_dword_masked(HWIO_GCC_CE1_SREGR_ADDR, HWIO_GCC_CE1_SREGR_RMSK) +#define HWIO_GCC_CE1_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_CE1_SREGR_ADDR, m) +#define HWIO_GCC_CE1_SREGR_OUT(v) \ + out_dword(HWIO_GCC_CE1_SREGR_ADDR,v) +#define HWIO_GCC_CE1_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CE1_SREGR_ADDR,m,v,HWIO_GCC_CE1_SREGR_IN) +#define HWIO_GCC_CE1_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xff000000 +#define HWIO_GCC_CE1_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_CE1_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xff0000 +#define HWIO_GCC_CE1_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_CE1_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_CE1_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_CE1_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_CE1_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_CE1_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_CE1_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_CE1_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_CE1_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_CE1_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_CE1_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_CE1_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_CE1_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_CE1_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_CE1_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_CE1_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_CE1_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_CE1_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_CE1_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_CE1_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_CE1_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_CE1_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_CE1_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_CE1_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_CE1_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_CE1_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_CE1_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_CE1_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_CE1_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_CE1_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CE1_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_CE1_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_CE1_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_CE1_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_CE1_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_CE1_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_CE1_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_CE1_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_CE1_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_CE1_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_CE1_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_CE1_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_CE1_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_CE1_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_CE1_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_CE1_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_CE1_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_CE1_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_CE1_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_CE1_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_CE1_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_CE1_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_CE1_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_CE1_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_CE1_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CE1_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001c00c) +#define HWIO_GCC_CE1_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001c00c) +#define HWIO_GCC_CE1_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001c00c) +#define HWIO_GCC_CE1_AXI_CBCR_RMSK 0x81d00004 +#define HWIO_GCC_CE1_AXI_CBCR_ATTR 0x3 +#define HWIO_GCC_CE1_AXI_CBCR_IN \ + in_dword_masked(HWIO_GCC_CE1_AXI_CBCR_ADDR, HWIO_GCC_CE1_AXI_CBCR_RMSK) +#define HWIO_GCC_CE1_AXI_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_CE1_AXI_CBCR_ADDR, m) +#define HWIO_GCC_CE1_AXI_CBCR_OUT(v) \ + out_dword(HWIO_GCC_CE1_AXI_CBCR_ADDR,v) +#define HWIO_GCC_CE1_AXI_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CE1_AXI_CBCR_ADDR,m,v,HWIO_GCC_CE1_AXI_CBCR_IN) +#define HWIO_GCC_CE1_AXI_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_CE1_AXI_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_CE1_AXI_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_CE1_AXI_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_CE1_AXI_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_CE1_AXI_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_CE1_AXI_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_CE1_AXI_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_CE1_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_CE1_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_CE1_AXI_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_CE1_AXI_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_CE1_AXI_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_CE1_AXI_CBCR_CLK_ARES_RESET_FVAL 0x1 + +#define HWIO_GCC_CE1_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001c010) +#define HWIO_GCC_CE1_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001c010) +#define HWIO_GCC_CE1_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001c010) +#define HWIO_GCC_CE1_AHB_CBCR_RMSK 0x81d0000e +#define HWIO_GCC_CE1_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_CE1_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_CE1_AHB_CBCR_ADDR, HWIO_GCC_CE1_AHB_CBCR_RMSK) +#define HWIO_GCC_CE1_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_CE1_AHB_CBCR_ADDR, m) +#define HWIO_GCC_CE1_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_CE1_AHB_CBCR_ADDR,v) +#define HWIO_GCC_CE1_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CE1_AHB_CBCR_ADDR,m,v,HWIO_GCC_CE1_AHB_CBCR_IN) +#define HWIO_GCC_CE1_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_CE1_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_CE1_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_CE1_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_CE1_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_CE1_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_CE1_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_CE1_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_CE1_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_CE1_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_CE1_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_CE1_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_CE1_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_CE1_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_CE1_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_CE1_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_CE1_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_CE1_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_CE1_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_CE1_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CE_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001c028) +#define HWIO_GCC_RPMH_CE_CMD_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001c028) +#define HWIO_GCC_RPMH_CE_CMD_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001c028) +#define HWIO_GCC_RPMH_CE_CMD_DFSR_RMSK 0xffff +#define HWIO_GCC_RPMH_CE_CMD_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_CMD_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_CMD_DFSR_ADDR, HWIO_GCC_RPMH_CE_CMD_DFSR_RMSK) +#define HWIO_GCC_RPMH_CE_CMD_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_CMD_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CE_CMD_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_CMD_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CE_CMD_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_CMD_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CE_CMD_DFSR_IN) +#define HWIO_GCC_RPMH_CE_CMD_DFSR_RCG_SW_CTRL_BMSK 0x8000 +#define HWIO_GCC_RPMH_CE_CMD_DFSR_RCG_SW_CTRL_SHFT 0xf +#define HWIO_GCC_RPMH_CE_CMD_DFSR_SW_PERF_STATE_BMSK 0x7800 +#define HWIO_GCC_RPMH_CE_CMD_DFSR_SW_PERF_STATE_SHFT 0xb +#define HWIO_GCC_RPMH_CE_CMD_DFSR_SW_OVERRIDE_BMSK 0x400 +#define HWIO_GCC_RPMH_CE_CMD_DFSR_SW_OVERRIDE_SHFT 0xa +#define HWIO_GCC_RPMH_CE_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK 0x200 +#define HWIO_GCC_RPMH_CE_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT 0x9 +#define HWIO_GCC_RPMH_CE_CMD_DFSR_DFS_FSM_STATE_BMSK 0x1c0 +#define HWIO_GCC_RPMH_CE_CMD_DFSR_DFS_FSM_STATE_SHFT 0x6 +#define HWIO_GCC_RPMH_CE_CMD_DFSR_HW_CLK_CONTROL_BMSK 0x20 +#define HWIO_GCC_RPMH_CE_CMD_DFSR_HW_CLK_CONTROL_SHFT 0x5 +#define HWIO_GCC_RPMH_CE_CMD_DFSR_CURR_PERF_STATE_BMSK 0x1e +#define HWIO_GCC_RPMH_CE_CMD_DFSR_CURR_PERF_STATE_SHFT 0x1 +#define HWIO_GCC_RPMH_CE_CMD_DFSR_DFS_EN_BMSK 0x1 +#define HWIO_GCC_RPMH_CE_CMD_DFSR_DFS_EN_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_CMD_DFSR_DFS_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CMD_DFSR_DFS_EN_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001c030) +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001c030) +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001c030) +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_ADDR, HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_RMSK) +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_IN) +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001c034) +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001c034) +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001c034) +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_ADDR, HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_RMSK) +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_IN) +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001c038) +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001c038) +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001c038) +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_ADDR, HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_RMSK) +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_IN) +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001c03c) +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001c03c) +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001c03c) +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_ADDR, HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_RMSK) +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_IN) +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001c040) +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001c040) +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001c040) +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_ADDR, HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_RMSK) +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_IN) +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001c044) +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001c044) +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001c044) +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_ADDR, HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_RMSK) +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_IN) +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001c048) +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001c048) +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001c048) +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_ADDR, HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_RMSK) +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_IN) +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001c04c) +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001c04c) +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001c04c) +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_ADDR, HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_RMSK) +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_IN) +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001c050) +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001c050) +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001c050) +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_ADDR, HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_RMSK) +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_IN) +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001c054) +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001c054) +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001c054) +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_ADDR, HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_RMSK) +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_IN) +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001c058) +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001c058) +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001c058) +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_ADDR, HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_RMSK) +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_IN) +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001c05c) +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001c05c) +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001c05c) +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_ADDR, HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_RMSK) +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_IN) +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001c060) +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001c060) +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001c060) +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_ADDR, HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_RMSK) +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_IN) +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001c064) +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001c064) +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001c064) +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_ADDR, HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_RMSK) +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_IN) +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001c068) +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001c068) +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001c068) +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_ADDR, HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_RMSK) +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_IN) +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001c06c) +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001c06c) +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001c06c) +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_ADDR, HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_RMSK) +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_IN) +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_CE1_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001c014) +#define HWIO_GCC_CE1_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001c014) +#define HWIO_GCC_CE1_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001c014) +#define HWIO_GCC_CE1_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_CE1_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_CE1_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_CE1_CMD_RCGR_ADDR, HWIO_GCC_CE1_CMD_RCGR_RMSK) +#define HWIO_GCC_CE1_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_CE1_CMD_RCGR_ADDR, m) +#define HWIO_GCC_CE1_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_CE1_CMD_RCGR_ADDR,v) +#define HWIO_GCC_CE1_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CE1_CMD_RCGR_ADDR,m,v,HWIO_GCC_CE1_CMD_RCGR_IN) +#define HWIO_GCC_CE1_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_CE1_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_CE1_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_CE1_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_CE1_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_CE1_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_CE1_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_CE1_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_CE1_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_CE1_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_CE1_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CE1_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CE1_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001c018) +#define HWIO_GCC_CE1_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001c018) +#define HWIO_GCC_CE1_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001c018) +#define HWIO_GCC_CE1_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_CE1_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_CE1_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_CE1_CFG_RCGR_ADDR, HWIO_GCC_CE1_CFG_RCGR_RMSK) +#define HWIO_GCC_CE1_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_CE1_CFG_RCGR_ADDR, m) +#define HWIO_GCC_CE1_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_CE1_CFG_RCGR_ADDR,v) +#define HWIO_GCC_CE1_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CE1_CFG_RCGR_ADDR,m,v,HWIO_GCC_CE1_CFG_RCGR_IN) +#define HWIO_GCC_CE1_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_CE1_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_CE1_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_CE1_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_CE1_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_CE1_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_CE1_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_CE1_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001e000) +#define HWIO_GCC_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e000) +#define HWIO_GCC_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e000) +#define HWIO_GCC_AHB_CBCR_RMSK 0x81d00005 +#define HWIO_GCC_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_AHB_CBCR_ADDR, HWIO_GCC_AHB_CBCR_RMSK) +#define HWIO_GCC_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_AHB_CBCR_ADDR, m) +#define HWIO_GCC_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_AHB_CBCR_ADDR,v) +#define HWIO_GCC_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AHB_CBCR_ADDR,m,v,HWIO_GCC_AHB_CBCR_IN) +#define HWIO_GCC_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_AHB_PCIE_LINK_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001e004) +#define HWIO_GCC_AHB_PCIE_LINK_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e004) +#define HWIO_GCC_AHB_PCIE_LINK_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e004) +#define HWIO_GCC_AHB_PCIE_LINK_CBCR_RMSK 0x81d00005 +#define HWIO_GCC_AHB_PCIE_LINK_CBCR_ATTR 0x3 +#define HWIO_GCC_AHB_PCIE_LINK_CBCR_IN \ + in_dword_masked(HWIO_GCC_AHB_PCIE_LINK_CBCR_ADDR, HWIO_GCC_AHB_PCIE_LINK_CBCR_RMSK) +#define HWIO_GCC_AHB_PCIE_LINK_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_AHB_PCIE_LINK_CBCR_ADDR, m) +#define HWIO_GCC_AHB_PCIE_LINK_CBCR_OUT(v) \ + out_dword(HWIO_GCC_AHB_PCIE_LINK_CBCR_ADDR,v) +#define HWIO_GCC_AHB_PCIE_LINK_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AHB_PCIE_LINK_CBCR_ADDR,m,v,HWIO_GCC_AHB_PCIE_LINK_CBCR_IN) +#define HWIO_GCC_AHB_PCIE_LINK_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_AHB_PCIE_LINK_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_AHB_PCIE_LINK_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_AHB_PCIE_LINK_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_AHB_PCIE_LINK_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_AHB_PCIE_LINK_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_AHB_PCIE_LINK_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_AHB_PCIE_LINK_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_AHB_PCIE_LINK_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_AHB_PCIE_LINK_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_AHB_PCIE_LINK_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_AHB_PCIE_LINK_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_AHB_PCIE_LINK_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_AHB_PCIE_LINK_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_AHB_PCIE_LINK_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_AHB_PCIE_LINK_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_AHB_PCIE_LINK_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AHB_PCIE_LINK_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_XO_PCIE_LINK_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001e008) +#define HWIO_GCC_XO_PCIE_LINK_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e008) +#define HWIO_GCC_XO_PCIE_LINK_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e008) +#define HWIO_GCC_XO_PCIE_LINK_CBCR_RMSK 0x81c0000f +#define HWIO_GCC_XO_PCIE_LINK_CBCR_ATTR 0x3 +#define HWIO_GCC_XO_PCIE_LINK_CBCR_IN \ + in_dword_masked(HWIO_GCC_XO_PCIE_LINK_CBCR_ADDR, HWIO_GCC_XO_PCIE_LINK_CBCR_RMSK) +#define HWIO_GCC_XO_PCIE_LINK_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_XO_PCIE_LINK_CBCR_ADDR, m) +#define HWIO_GCC_XO_PCIE_LINK_CBCR_OUT(v) \ + out_dword(HWIO_GCC_XO_PCIE_LINK_CBCR_ADDR,v) +#define HWIO_GCC_XO_PCIE_LINK_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_XO_PCIE_LINK_CBCR_ADDR,m,v,HWIO_GCC_XO_PCIE_LINK_CBCR_IN) +#define HWIO_GCC_XO_PCIE_LINK_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_XO_PCIE_LINK_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_XO_PCIE_LINK_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_XO_PCIE_LINK_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_XO_PCIE_LINK_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_XO_PCIE_LINK_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_XO_PCIE_LINK_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_XO_PCIE_LINK_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_XO_PCIE_LINK_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_XO_PCIE_LINK_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_XO_PCIE_LINK_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_XO_PCIE_LINK_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_XO_PCIE_LINK_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_XO_PCIE_LINK_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_XO_PCIE_LINK_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_XO_PCIE_LINK_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_XO_PCIE_LINK_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_XO_PCIE_LINK_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_XO_PCIE_LINK_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_XO_PCIE_LINK_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_XO_PCIE_LINK_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_XO_PCIE_LINK_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001e00c) +#define HWIO_GCC_XO_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e00c) +#define HWIO_GCC_XO_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e00c) +#define HWIO_GCC_XO_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_XO_CBCR_ATTR 0x3 +#define HWIO_GCC_XO_CBCR_IN \ + in_dword_masked(HWIO_GCC_XO_CBCR_ADDR, HWIO_GCC_XO_CBCR_RMSK) +#define HWIO_GCC_XO_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_XO_CBCR_ADDR, m) +#define HWIO_GCC_XO_CBCR_OUT(v) \ + out_dword(HWIO_GCC_XO_CBCR_ADDR,v) +#define HWIO_GCC_XO_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_XO_CBCR_ADDR,m,v,HWIO_GCC_XO_CBCR_IN) +#define HWIO_GCC_XO_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_XO_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_XO_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_XO_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_XO_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_XO_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_XO_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_XO_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_XO_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_XO_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_XO_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_XO_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_XO_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_XO_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_XO_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_XO_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_XO_DIV4_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001e010) +#define HWIO_GCC_XO_DIV4_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e010) +#define HWIO_GCC_XO_DIV4_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e010) +#define HWIO_GCC_XO_DIV4_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_XO_DIV4_CBCR_ATTR 0x3 +#define HWIO_GCC_XO_DIV4_CBCR_IN \ + in_dword_masked(HWIO_GCC_XO_DIV4_CBCR_ADDR, HWIO_GCC_XO_DIV4_CBCR_RMSK) +#define HWIO_GCC_XO_DIV4_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_XO_DIV4_CBCR_ADDR, m) +#define HWIO_GCC_XO_DIV4_CBCR_OUT(v) \ + out_dword(HWIO_GCC_XO_DIV4_CBCR_ADDR,v) +#define HWIO_GCC_XO_DIV4_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_XO_DIV4_CBCR_ADDR,m,v,HWIO_GCC_XO_DIV4_CBCR_IN) +#define HWIO_GCC_XO_DIV4_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_XO_DIV4_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_XO_DIV4_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_XO_DIV4_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_XO_DIV4_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_XO_DIV4_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_XO_DIV4_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_XO_DIV4_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_XO_DIV4_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_XO_DIV4_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_XO_DIV4_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_XO_DIV4_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_XO_DIV4_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_XO_DIV4_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_XO_DIV4_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_XO_DIV4_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SLEEP_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001e014) +#define HWIO_GCC_SLEEP_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e014) +#define HWIO_GCC_SLEEP_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e014) +#define HWIO_GCC_SLEEP_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_SLEEP_CBCR_ATTR 0x3 +#define HWIO_GCC_SLEEP_CBCR_IN \ + in_dword_masked(HWIO_GCC_SLEEP_CBCR_ADDR, HWIO_GCC_SLEEP_CBCR_RMSK) +#define HWIO_GCC_SLEEP_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_SLEEP_CBCR_ADDR, m) +#define HWIO_GCC_SLEEP_CBCR_OUT(v) \ + out_dword(HWIO_GCC_SLEEP_CBCR_ADDR,v) +#define HWIO_GCC_SLEEP_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SLEEP_CBCR_ADDR,m,v,HWIO_GCC_SLEEP_CBCR_IN) +#define HWIO_GCC_SLEEP_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SLEEP_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SLEEP_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_SLEEP_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_SLEEP_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_SLEEP_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_SLEEP_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_SLEEP_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_SLEEP_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_SLEEP_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_SLEEP_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SLEEP_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_SLEEP_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SLEEP_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SLEEP_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SLEEP_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_XO_DIV4_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001e018) +#define HWIO_GCC_XO_DIV4_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e018) +#define HWIO_GCC_XO_DIV4_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e018) +#define HWIO_GCC_XO_DIV4_CDIVR_RMSK 0xf +#define HWIO_GCC_XO_DIV4_CDIVR_ATTR 0x3 +#define HWIO_GCC_XO_DIV4_CDIVR_IN \ + in_dword_masked(HWIO_GCC_XO_DIV4_CDIVR_ADDR, HWIO_GCC_XO_DIV4_CDIVR_RMSK) +#define HWIO_GCC_XO_DIV4_CDIVR_INM(m) \ + in_dword_masked(HWIO_GCC_XO_DIV4_CDIVR_ADDR, m) +#define HWIO_GCC_XO_DIV4_CDIVR_OUT(v) \ + out_dword(HWIO_GCC_XO_DIV4_CDIVR_ADDR,v) +#define HWIO_GCC_XO_DIV4_CDIVR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_XO_DIV4_CDIVR_ADDR,m,v,HWIO_GCC_XO_DIV4_CDIVR_IN) +#define HWIO_GCC_XO_DIV4_CDIVR_CLK_DIV_BMSK 0xf +#define HWIO_GCC_XO_DIV4_CDIVR_CLK_DIV_SHFT 0x0 + +#define HWIO_GCC_SLEEP_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001e01c) +#define HWIO_GCC_SLEEP_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e01c) +#define HWIO_GCC_SLEEP_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e01c) +#define HWIO_GCC_SLEEP_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_SLEEP_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_SLEEP_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_SLEEP_CMD_RCGR_ADDR, HWIO_GCC_SLEEP_CMD_RCGR_RMSK) +#define HWIO_GCC_SLEEP_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_SLEEP_CMD_RCGR_ADDR, m) +#define HWIO_GCC_SLEEP_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_SLEEP_CMD_RCGR_ADDR,v) +#define HWIO_GCC_SLEEP_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SLEEP_CMD_RCGR_ADDR,m,v,HWIO_GCC_SLEEP_CMD_RCGR_IN) +#define HWIO_GCC_SLEEP_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_SLEEP_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_SLEEP_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_SLEEP_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_SLEEP_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_SLEEP_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_SLEEP_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_SLEEP_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_SLEEP_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_SLEEP_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_SLEEP_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SLEEP_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SLEEP_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001e020) +#define HWIO_GCC_SLEEP_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e020) +#define HWIO_GCC_SLEEP_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e020) +#define HWIO_GCC_SLEEP_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_SLEEP_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_SLEEP_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_SLEEP_CFG_RCGR_ADDR, HWIO_GCC_SLEEP_CFG_RCGR_RMSK) +#define HWIO_GCC_SLEEP_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_SLEEP_CFG_RCGR_ADDR, m) +#define HWIO_GCC_SLEEP_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_SLEEP_CFG_RCGR_ADDR,v) +#define HWIO_GCC_SLEEP_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SLEEP_CFG_RCGR_ADDR,m,v,HWIO_GCC_SLEEP_CFG_RCGR_IN) +#define HWIO_GCC_SLEEP_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_SLEEP_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_SLEEP_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_SLEEP_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_SLEEP_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_SLEEP_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_SLEEP_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_SLEEP_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_XO_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001e038) +#define HWIO_GCC_XO_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e038) +#define HWIO_GCC_XO_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e038) +#define HWIO_GCC_XO_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_XO_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_XO_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_XO_CMD_RCGR_ADDR, HWIO_GCC_XO_CMD_RCGR_RMSK) +#define HWIO_GCC_XO_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_XO_CMD_RCGR_ADDR, m) +#define HWIO_GCC_XO_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_XO_CMD_RCGR_ADDR,v) +#define HWIO_GCC_XO_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_XO_CMD_RCGR_ADDR,m,v,HWIO_GCC_XO_CMD_RCGR_IN) +#define HWIO_GCC_XO_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_XO_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_XO_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_XO_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_XO_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_XO_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_XO_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_XO_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_XO_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_XO_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_XO_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_XO_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_XO_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001e03c) +#define HWIO_GCC_XO_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e03c) +#define HWIO_GCC_XO_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e03c) +#define HWIO_GCC_XO_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_XO_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_XO_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_XO_CFG_RCGR_ADDR, HWIO_GCC_XO_CFG_RCGR_RMSK) +#define HWIO_GCC_XO_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_XO_CFG_RCGR_ADDR, m) +#define HWIO_GCC_XO_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_XO_CFG_RCGR_ADDR,v) +#define HWIO_GCC_XO_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_XO_CFG_RCGR_ADDR,m,v,HWIO_GCC_XO_CFG_RCGR_IN) +#define HWIO_GCC_XO_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_XO_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_XO_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_XO_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_XO_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_XO_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_XO_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_XO_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_XO_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_XO_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_XO_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_XO_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_XO_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_XO_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_XO_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_XO_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_XO_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_XO_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_DDRSS_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f000) +#define HWIO_GCC_DDRSS_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f000) +#define HWIO_GCC_DDRSS_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f000) +#define HWIO_GCC_DDRSS_BCR_RMSK 0x1 +#define HWIO_GCC_DDRSS_BCR_ATTR 0x3 +#define HWIO_GCC_DDRSS_BCR_IN \ + in_dword_masked(HWIO_GCC_DDRSS_BCR_ADDR, HWIO_GCC_DDRSS_BCR_RMSK) +#define HWIO_GCC_DDRSS_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_DDRSS_BCR_ADDR, m) +#define HWIO_GCC_DDRSS_BCR_OUT(v) \ + out_dword(HWIO_GCC_DDRSS_BCR_ADDR,v) +#define HWIO_GCC_DDRSS_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DDRSS_BCR_ADDR,m,v,HWIO_GCC_DDRSS_BCR_IN) +#define HWIO_GCC_DDRSS_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_DDRSS_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_DDRSS_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_DDRSS_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f004) +#define HWIO_GCC_DDRSS_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f004) +#define HWIO_GCC_DDRSS_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f004) +#define HWIO_GCC_DDRSS_GDSCR_RMSK 0xf8ffffff +#define HWIO_GCC_DDRSS_GDSCR_ATTR 0x3 +#define HWIO_GCC_DDRSS_GDSCR_IN \ + in_dword_masked(HWIO_GCC_DDRSS_GDSCR_ADDR, HWIO_GCC_DDRSS_GDSCR_RMSK) +#define HWIO_GCC_DDRSS_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_DDRSS_GDSCR_ADDR, m) +#define HWIO_GCC_DDRSS_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_DDRSS_GDSCR_ADDR,v) +#define HWIO_GCC_DDRSS_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DDRSS_GDSCR_ADDR,m,v,HWIO_GCC_DDRSS_GDSCR_IN) +#define HWIO_GCC_DDRSS_GDSCR_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_DDRSS_GDSCR_PWR_ON_SHFT 0x1f +#define HWIO_GCC_DDRSS_GDSCR_GDSC_STATE_BMSK 0x78000000 +#define HWIO_GCC_DDRSS_GDSCR_GDSC_STATE_SHFT 0x1b +#define HWIO_GCC_DDRSS_GDSCR_EN_REST_WAIT_BMSK 0xf00000 +#define HWIO_GCC_DDRSS_GDSCR_EN_REST_WAIT_SHFT 0x14 +#define HWIO_GCC_DDRSS_GDSCR_EN_FEW_WAIT_BMSK 0xf0000 +#define HWIO_GCC_DDRSS_GDSCR_EN_FEW_WAIT_SHFT 0x10 +#define HWIO_GCC_DDRSS_GDSCR_CLK_DIS_WAIT_BMSK 0xf000 +#define HWIO_GCC_DDRSS_GDSCR_CLK_DIS_WAIT_SHFT 0xc +#define HWIO_GCC_DDRSS_GDSCR_RETAIN_FF_ENABLE_BMSK 0x800 +#define HWIO_GCC_DDRSS_GDSCR_RETAIN_FF_ENABLE_SHFT 0xb +#define HWIO_GCC_DDRSS_GDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_GDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_DDRSS_GDSCR_RESTORE_BMSK 0x400 +#define HWIO_GCC_DDRSS_GDSCR_RESTORE_SHFT 0xa +#define HWIO_GCC_DDRSS_GDSCR_RESTORE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_GDSCR_RESTORE_ENABLE_FVAL 0x1 +#define HWIO_GCC_DDRSS_GDSCR_SAVE_BMSK 0x200 +#define HWIO_GCC_DDRSS_GDSCR_SAVE_SHFT 0x9 +#define HWIO_GCC_DDRSS_GDSCR_SAVE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_GDSCR_SAVE_ENABLE_FVAL 0x1 +#define HWIO_GCC_DDRSS_GDSCR_RETAIN_BMSK 0x100 +#define HWIO_GCC_DDRSS_GDSCR_RETAIN_SHFT 0x8 +#define HWIO_GCC_DDRSS_GDSCR_RETAIN_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_GDSCR_RETAIN_ENABLE_FVAL 0x1 +#define HWIO_GCC_DDRSS_GDSCR_EN_REST_BMSK 0x80 +#define HWIO_GCC_DDRSS_GDSCR_EN_REST_SHFT 0x7 +#define HWIO_GCC_DDRSS_GDSCR_EN_REST_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_GDSCR_EN_REST_ENABLE_FVAL 0x1 +#define HWIO_GCC_DDRSS_GDSCR_EN_FEW_BMSK 0x40 +#define HWIO_GCC_DDRSS_GDSCR_EN_FEW_SHFT 0x6 +#define HWIO_GCC_DDRSS_GDSCR_EN_FEW_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_GDSCR_EN_FEW_ENABLE_FVAL 0x1 +#define HWIO_GCC_DDRSS_GDSCR_CLAMP_IO_BMSK 0x20 +#define HWIO_GCC_DDRSS_GDSCR_CLAMP_IO_SHFT 0x5 +#define HWIO_GCC_DDRSS_GDSCR_CLAMP_IO_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_GDSCR_CLAMP_IO_ENABLE_FVAL 0x1 +#define HWIO_GCC_DDRSS_GDSCR_CLK_DISABLE_BMSK 0x10 +#define HWIO_GCC_DDRSS_GDSCR_CLK_DISABLE_SHFT 0x4 +#define HWIO_GCC_DDRSS_GDSCR_CLK_DISABLE_CLK_NOT_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_GDSCR_CLK_DISABLE_CLK_IS_DISABLE_FVAL 0x1 +#define HWIO_GCC_DDRSS_GDSCR_PD_ARES_BMSK 0x8 +#define HWIO_GCC_DDRSS_GDSCR_PD_ARES_SHFT 0x3 +#define HWIO_GCC_DDRSS_GDSCR_PD_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_DDRSS_GDSCR_PD_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_DDRSS_GDSCR_SW_OVERRIDE_BMSK 0x4 +#define HWIO_GCC_DDRSS_GDSCR_SW_OVERRIDE_SHFT 0x2 +#define HWIO_GCC_DDRSS_GDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_GDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 +#define HWIO_GCC_DDRSS_GDSCR_HW_CONTROL_BMSK 0x2 +#define HWIO_GCC_DDRSS_GDSCR_HW_CONTROL_SHFT 0x1 +#define HWIO_GCC_DDRSS_GDSCR_HW_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_GDSCR_HW_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_DDRSS_GDSCR_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_DDRSS_GDSCR_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_DDRSS_GDSCR_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_GDSCR_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_DDRSS_CFG_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f008) +#define HWIO_GCC_DDRSS_CFG_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f008) +#define HWIO_GCC_DDRSS_CFG_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f008) +#define HWIO_GCC_DDRSS_CFG_GDSCR_RMSK 0x3ffffff +#define HWIO_GCC_DDRSS_CFG_GDSCR_ATTR 0x3 +#define HWIO_GCC_DDRSS_CFG_GDSCR_IN \ + in_dword_masked(HWIO_GCC_DDRSS_CFG_GDSCR_ADDR, HWIO_GCC_DDRSS_CFG_GDSCR_RMSK) +#define HWIO_GCC_DDRSS_CFG_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_DDRSS_CFG_GDSCR_ADDR, m) +#define HWIO_GCC_DDRSS_CFG_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_DDRSS_CFG_GDSCR_ADDR,v) +#define HWIO_GCC_DDRSS_CFG_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DDRSS_CFG_GDSCR_ADDR,m,v,HWIO_GCC_DDRSS_CFG_GDSCR_IN) +#define HWIO_GCC_DDRSS_CFG_GDSCR_GDSC_PWR_DWN_START_BMSK 0x2000000 +#define HWIO_GCC_DDRSS_CFG_GDSCR_GDSC_PWR_DWN_START_SHFT 0x19 +#define HWIO_GCC_DDRSS_CFG_GDSCR_GDSC_PWR_UP_START_BMSK 0x1000000 +#define HWIO_GCC_DDRSS_CFG_GDSCR_GDSC_PWR_UP_START_SHFT 0x18 +#define HWIO_GCC_DDRSS_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_BMSK 0xf00000 +#define HWIO_GCC_DDRSS_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_SHFT 0x14 +#define HWIO_GCC_DDRSS_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_BMSK 0x80000 +#define HWIO_GCC_DDRSS_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_SHFT 0x13 +#define HWIO_GCC_DDRSS_CFG_GDSCR_GDSC_ENR_ACK_STATUS_BMSK 0x40000 +#define HWIO_GCC_DDRSS_CFG_GDSCR_GDSC_ENR_ACK_STATUS_SHFT 0x12 +#define HWIO_GCC_DDRSS_CFG_GDSCR_GDSC_ENF_ACK_STATUS_BMSK 0x20000 +#define HWIO_GCC_DDRSS_CFG_GDSCR_GDSC_ENF_ACK_STATUS_SHFT 0x11 +#define HWIO_GCC_DDRSS_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_BMSK 0x10000 +#define HWIO_GCC_DDRSS_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_SHFT 0x10 +#define HWIO_GCC_DDRSS_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_BMSK 0x8000 +#define HWIO_GCC_DDRSS_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_SHFT 0xf +#define HWIO_GCC_DDRSS_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_BMSK 0x7800 +#define HWIO_GCC_DDRSS_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_SHFT 0xb +#define HWIO_GCC_DDRSS_CFG_GDSCR_GDSC_HANDSHAKE_DIS_BMSK 0x400 +#define HWIO_GCC_DDRSS_CFG_GDSCR_GDSC_HANDSHAKE_DIS_SHFT 0xa +#define HWIO_GCC_DDRSS_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_BMSK 0x200 +#define HWIO_GCC_DDRSS_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_SHFT 0x9 +#define HWIO_GCC_DDRSS_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_BMSK 0x100 +#define HWIO_GCC_DDRSS_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_SHFT 0x8 +#define HWIO_GCC_DDRSS_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_BMSK 0x80 +#define HWIO_GCC_DDRSS_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_SHFT 0x7 +#define HWIO_GCC_DDRSS_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_BMSK 0x60 +#define HWIO_GCC_DDRSS_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_SHFT 0x5 +#define HWIO_GCC_DDRSS_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_BMSK 0x10 +#define HWIO_GCC_DDRSS_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_SHFT 0x4 +#define HWIO_GCC_DDRSS_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_BMSK 0x8 +#define HWIO_GCC_DDRSS_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_SHFT 0x3 +#define HWIO_GCC_DDRSS_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_BMSK 0x4 +#define HWIO_GCC_DDRSS_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_SHFT 0x2 +#define HWIO_GCC_DDRSS_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_BMSK 0x2 +#define HWIO_GCC_DDRSS_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_SHFT 0x1 +#define HWIO_GCC_DDRSS_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_DDRSS_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_SHFT 0x0 + +#define HWIO_GCC_DDRSS_CFG2_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f00c) +#define HWIO_GCC_DDRSS_CFG2_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f00c) +#define HWIO_GCC_DDRSS_CFG2_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f00c) +#define HWIO_GCC_DDRSS_CFG2_GDSCR_RMSK 0x7ffff +#define HWIO_GCC_DDRSS_CFG2_GDSCR_ATTR 0x3 +#define HWIO_GCC_DDRSS_CFG2_GDSCR_IN \ + in_dword_masked(HWIO_GCC_DDRSS_CFG2_GDSCR_ADDR, HWIO_GCC_DDRSS_CFG2_GDSCR_RMSK) +#define HWIO_GCC_DDRSS_CFG2_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_DDRSS_CFG2_GDSCR_ADDR, m) +#define HWIO_GCC_DDRSS_CFG2_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_DDRSS_CFG2_GDSCR_ADDR,v) +#define HWIO_GCC_DDRSS_CFG2_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DDRSS_CFG2_GDSCR_ADDR,m,v,HWIO_GCC_DDRSS_CFG2_GDSCR_IN) +#define HWIO_GCC_DDRSS_CFG2_GDSCR_GDSC_MEM_PWRUP_ACK_OVERRIDE_BMSK 0x40000 +#define HWIO_GCC_DDRSS_CFG2_GDSCR_GDSC_MEM_PWRUP_ACK_OVERRIDE_SHFT 0x12 +#define HWIO_GCC_DDRSS_CFG2_GDSCR_GDSC_PWRDWN_ENABLE_ACK_OVERRIDE_BMSK 0x20000 +#define HWIO_GCC_DDRSS_CFG2_GDSCR_GDSC_PWRDWN_ENABLE_ACK_OVERRIDE_SHFT 0x11 +#define HWIO_GCC_DDRSS_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_BMSK 0x10000 +#define HWIO_GCC_DDRSS_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_SHFT 0x10 +#define HWIO_GCC_DDRSS_CFG2_GDSCR_DLY_MEM_PWR_UP_BMSK 0xf000 +#define HWIO_GCC_DDRSS_CFG2_GDSCR_DLY_MEM_PWR_UP_SHFT 0xc +#define HWIO_GCC_DDRSS_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_BMSK 0xf00 +#define HWIO_GCC_DDRSS_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_SHFT 0x8 +#define HWIO_GCC_DDRSS_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_BMSK 0xf0 +#define HWIO_GCC_DDRSS_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_SHFT 0x4 +#define HWIO_GCC_DDRSS_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_BMSK 0xf +#define HWIO_GCC_DDRSS_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_SHFT 0x0 + +#define HWIO_GCC_DDRSS_CFG3_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f010) +#define HWIO_GCC_DDRSS_CFG3_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f010) +#define HWIO_GCC_DDRSS_CFG3_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f010) +#define HWIO_GCC_DDRSS_CFG3_GDSCR_RMSK 0x7ffffff +#define HWIO_GCC_DDRSS_CFG3_GDSCR_ATTR 0x3 +#define HWIO_GCC_DDRSS_CFG3_GDSCR_IN \ + in_dword_masked(HWIO_GCC_DDRSS_CFG3_GDSCR_ADDR, HWIO_GCC_DDRSS_CFG3_GDSCR_RMSK) +#define HWIO_GCC_DDRSS_CFG3_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_DDRSS_CFG3_GDSCR_ADDR, m) +#define HWIO_GCC_DDRSS_CFG3_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_DDRSS_CFG3_GDSCR_ADDR,v) +#define HWIO_GCC_DDRSS_CFG3_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DDRSS_CFG3_GDSCR_ADDR,m,v,HWIO_GCC_DDRSS_CFG3_GDSCR_IN) +#define HWIO_GCC_DDRSS_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_STATUS_BMSK 0x4000000 +#define HWIO_GCC_DDRSS_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_STATUS_SHFT 0x1a +#define HWIO_GCC_DDRSS_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_BMSK 0x2000000 +#define HWIO_GCC_DDRSS_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_SHFT 0x19 +#define HWIO_GCC_DDRSS_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_DDRSS_CFG3_GDSCR_DLY_ACCU_RED_SHIFTER_DONE_BMSK 0x1e00000 +#define HWIO_GCC_DDRSS_CFG3_GDSCR_DLY_ACCU_RED_SHIFTER_DONE_SHFT 0x15 +#define HWIO_GCC_DDRSS_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_BMSK 0x100000 +#define HWIO_GCC_DDRSS_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_SHFT 0x14 +#define HWIO_GCC_DDRSS_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_ENABLE_FVAL 0x1 +#define HWIO_GCC_DDRSS_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_BMSK 0x80000 +#define HWIO_GCC_DDRSS_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_SHFT 0x13 +#define HWIO_GCC_DDRSS_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_ENABLE_FVAL 0x1 +#define HWIO_GCC_DDRSS_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_BMSK 0x40000 +#define HWIO_GCC_DDRSS_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_SHFT 0x12 +#define HWIO_GCC_DDRSS_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_ENABLE_FVAL 0x1 +#define HWIO_GCC_DDRSS_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_BMSK 0x20000 +#define HWIO_GCC_DDRSS_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_SHFT 0x11 +#define HWIO_GCC_DDRSS_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_ENABLE_FVAL 0x1 +#define HWIO_GCC_DDRSS_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_BMSK 0x10000 +#define HWIO_GCC_DDRSS_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_SHFT 0x10 +#define HWIO_GCC_DDRSS_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_ENABLE_FVAL 0x1 +#define HWIO_GCC_DDRSS_CFG3_GDSCR_GDSC_SPARE_CTRL_IN_BMSK 0xff00 +#define HWIO_GCC_DDRSS_CFG3_GDSCR_GDSC_SPARE_CTRL_IN_SHFT 0x8 +#define HWIO_GCC_DDRSS_CFG3_GDSCR_GDSC_SPARE_CTRL_OUT_BMSK 0xff +#define HWIO_GCC_DDRSS_CFG3_GDSCR_GDSC_SPARE_CTRL_OUT_SHFT 0x0 + +#define HWIO_GCC_DDRSS_CFG4_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f014) +#define HWIO_GCC_DDRSS_CFG4_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f014) +#define HWIO_GCC_DDRSS_CFG4_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f014) +#define HWIO_GCC_DDRSS_CFG4_GDSCR_RMSK 0xffffff +#define HWIO_GCC_DDRSS_CFG4_GDSCR_ATTR 0x3 +#define HWIO_GCC_DDRSS_CFG4_GDSCR_IN \ + in_dword_masked(HWIO_GCC_DDRSS_CFG4_GDSCR_ADDR, HWIO_GCC_DDRSS_CFG4_GDSCR_RMSK) +#define HWIO_GCC_DDRSS_CFG4_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_DDRSS_CFG4_GDSCR_ADDR, m) +#define HWIO_GCC_DDRSS_CFG4_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_DDRSS_CFG4_GDSCR_ADDR,v) +#define HWIO_GCC_DDRSS_CFG4_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DDRSS_CFG4_GDSCR_ADDR,m,v,HWIO_GCC_DDRSS_CFG4_GDSCR_IN) +#define HWIO_GCC_DDRSS_CFG4_GDSCR_DLY_UNCLAMPIO_BMSK 0xf00000 +#define HWIO_GCC_DDRSS_CFG4_GDSCR_DLY_UNCLAMPIO_SHFT 0x14 +#define HWIO_GCC_DDRSS_CFG4_GDSCR_DLY_RESTOREFF_BMSK 0xf0000 +#define HWIO_GCC_DDRSS_CFG4_GDSCR_DLY_RESTOREFF_SHFT 0x10 +#define HWIO_GCC_DDRSS_CFG4_GDSCR_DLY_NORETAINFF_BMSK 0xf000 +#define HWIO_GCC_DDRSS_CFG4_GDSCR_DLY_NORETAINFF_SHFT 0xc +#define HWIO_GCC_DDRSS_CFG4_GDSCR_DLY_DEASSERTARES_BMSK 0xf00 +#define HWIO_GCC_DDRSS_CFG4_GDSCR_DLY_DEASSERTARES_SHFT 0x8 +#define HWIO_GCC_DDRSS_CFG4_GDSCR_DLY_CLAMPIO_BMSK 0xf0 +#define HWIO_GCC_DDRSS_CFG4_GDSCR_DLY_CLAMPIO_SHFT 0x4 +#define HWIO_GCC_DDRSS_CFG4_GDSCR_DLY_RETAINFF_BMSK 0xf +#define HWIO_GCC_DDRSS_CFG4_GDSCR_DLY_RETAINFF_SHFT 0x0 + +#define HWIO_GCC_DDRSS_TCU_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f018) +#define HWIO_GCC_DDRSS_TCU_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f018) +#define HWIO_GCC_DDRSS_TCU_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f018) +#define HWIO_GCC_DDRSS_TCU_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_DDRSS_TCU_CBCR_ATTR 0x3 +#define HWIO_GCC_DDRSS_TCU_CBCR_IN \ + in_dword_masked(HWIO_GCC_DDRSS_TCU_CBCR_ADDR, HWIO_GCC_DDRSS_TCU_CBCR_RMSK) +#define HWIO_GCC_DDRSS_TCU_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_DDRSS_TCU_CBCR_ADDR, m) +#define HWIO_GCC_DDRSS_TCU_CBCR_OUT(v) \ + out_dword(HWIO_GCC_DDRSS_TCU_CBCR_ADDR,v) +#define HWIO_GCC_DDRSS_TCU_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DDRSS_TCU_CBCR_ADDR,m,v,HWIO_GCC_DDRSS_TCU_CBCR_IN) +#define HWIO_GCC_DDRSS_TCU_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_DDRSS_TCU_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_DDRSS_TCU_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_DDRSS_TCU_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_DDRSS_TCU_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_DDRSS_TCU_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_DDRSS_TCU_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_DDRSS_TCU_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_DDRSS_TCU_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_DDRSS_TCU_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_DDRSS_TCU_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_DDRSS_TCU_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_DDRSS_TCU_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_DDRSS_TCU_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_DDRSS_TCU_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_DDRSS_TCU_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_DDRSS_TCU_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_DDRSS_TCU_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_DDRSS_TCU_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_TCU_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_DDRSS_TCU_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_DDRSS_TCU_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_DDRSS_TCU_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_TCU_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_DDRSS_SYS_NOC_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f01c) +#define HWIO_GCC_DDRSS_SYS_NOC_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f01c) +#define HWIO_GCC_DDRSS_SYS_NOC_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f01c) +#define HWIO_GCC_DDRSS_SYS_NOC_AXI_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_DDRSS_SYS_NOC_AXI_CBCR_ATTR 0x3 +#define HWIO_GCC_DDRSS_SYS_NOC_AXI_CBCR_IN \ + in_dword_masked(HWIO_GCC_DDRSS_SYS_NOC_AXI_CBCR_ADDR, HWIO_GCC_DDRSS_SYS_NOC_AXI_CBCR_RMSK) +#define HWIO_GCC_DDRSS_SYS_NOC_AXI_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_DDRSS_SYS_NOC_AXI_CBCR_ADDR, m) +#define HWIO_GCC_DDRSS_SYS_NOC_AXI_CBCR_OUT(v) \ + out_dword(HWIO_GCC_DDRSS_SYS_NOC_AXI_CBCR_ADDR,v) +#define HWIO_GCC_DDRSS_SYS_NOC_AXI_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DDRSS_SYS_NOC_AXI_CBCR_ADDR,m,v,HWIO_GCC_DDRSS_SYS_NOC_AXI_CBCR_IN) +#define HWIO_GCC_DDRSS_SYS_NOC_AXI_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_DDRSS_SYS_NOC_AXI_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_DDRSS_SYS_NOC_AXI_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_DDRSS_SYS_NOC_AXI_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_DDRSS_SYS_NOC_AXI_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_DDRSS_SYS_NOC_AXI_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_DDRSS_SYS_NOC_AXI_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_DDRSS_SYS_NOC_AXI_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_DDRSS_SYS_NOC_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_DDRSS_SYS_NOC_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_DDRSS_SYS_NOC_AXI_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_DDRSS_SYS_NOC_AXI_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_DDRSS_SYS_NOC_AXI_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_DDRSS_SYS_NOC_AXI_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_DDRSS_SYS_NOC_AXI_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_DDRSS_SYS_NOC_AXI_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_DDRSS_SYS_NOC_AXI_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_DDRSS_SYS_NOC_AXI_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_DDRSS_SYS_NOC_AXI_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_SYS_NOC_AXI_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_DDRSS_SYS_NOC_AXI_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_DDRSS_SYS_NOC_AXI_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_DDRSS_SYS_NOC_AXI_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_SYS_NOC_AXI_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_DDRSS_SYS_NOC_HS_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f020) +#define HWIO_GCC_DDRSS_SYS_NOC_HS_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f020) +#define HWIO_GCC_DDRSS_SYS_NOC_HS_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f020) +#define HWIO_GCC_DDRSS_SYS_NOC_HS_AXI_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_DDRSS_SYS_NOC_HS_AXI_CBCR_ATTR 0x3 +#define HWIO_GCC_DDRSS_SYS_NOC_HS_AXI_CBCR_IN \ + in_dword_masked(HWIO_GCC_DDRSS_SYS_NOC_HS_AXI_CBCR_ADDR, HWIO_GCC_DDRSS_SYS_NOC_HS_AXI_CBCR_RMSK) +#define HWIO_GCC_DDRSS_SYS_NOC_HS_AXI_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_DDRSS_SYS_NOC_HS_AXI_CBCR_ADDR, m) +#define HWIO_GCC_DDRSS_SYS_NOC_HS_AXI_CBCR_OUT(v) \ + out_dword(HWIO_GCC_DDRSS_SYS_NOC_HS_AXI_CBCR_ADDR,v) +#define HWIO_GCC_DDRSS_SYS_NOC_HS_AXI_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DDRSS_SYS_NOC_HS_AXI_CBCR_ADDR,m,v,HWIO_GCC_DDRSS_SYS_NOC_HS_AXI_CBCR_IN) +#define HWIO_GCC_DDRSS_SYS_NOC_HS_AXI_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_DDRSS_SYS_NOC_HS_AXI_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_DDRSS_SYS_NOC_HS_AXI_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_DDRSS_SYS_NOC_HS_AXI_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_DDRSS_SYS_NOC_HS_AXI_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_DDRSS_SYS_NOC_HS_AXI_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_DDRSS_SYS_NOC_HS_AXI_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_DDRSS_SYS_NOC_HS_AXI_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_DDRSS_SYS_NOC_HS_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_DDRSS_SYS_NOC_HS_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_DDRSS_SYS_NOC_HS_AXI_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_DDRSS_SYS_NOC_HS_AXI_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_DDRSS_SYS_NOC_HS_AXI_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_DDRSS_SYS_NOC_HS_AXI_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_DDRSS_SYS_NOC_HS_AXI_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_DDRSS_SYS_NOC_HS_AXI_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_DDRSS_SYS_NOC_HS_AXI_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_DDRSS_SYS_NOC_HS_AXI_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_DDRSS_SYS_NOC_HS_AXI_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_SYS_NOC_HS_AXI_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_DDRSS_SYS_NOC_HS_AXI_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_DDRSS_SYS_NOC_HS_AXI_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_DDRSS_SYS_NOC_HS_AXI_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_SYS_NOC_HS_AXI_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_DDRSS_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f024) +#define HWIO_GCC_DDRSS_XO_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f024) +#define HWIO_GCC_DDRSS_XO_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f024) +#define HWIO_GCC_DDRSS_XO_CBCR_RMSK 0x81c0000f +#define HWIO_GCC_DDRSS_XO_CBCR_ATTR 0x3 +#define HWIO_GCC_DDRSS_XO_CBCR_IN \ + in_dword_masked(HWIO_GCC_DDRSS_XO_CBCR_ADDR, HWIO_GCC_DDRSS_XO_CBCR_RMSK) +#define HWIO_GCC_DDRSS_XO_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_DDRSS_XO_CBCR_ADDR, m) +#define HWIO_GCC_DDRSS_XO_CBCR_OUT(v) \ + out_dword(HWIO_GCC_DDRSS_XO_CBCR_ADDR,v) +#define HWIO_GCC_DDRSS_XO_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DDRSS_XO_CBCR_ADDR,m,v,HWIO_GCC_DDRSS_XO_CBCR_IN) +#define HWIO_GCC_DDRSS_XO_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_DDRSS_XO_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_DDRSS_XO_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_DDRSS_XO_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_DDRSS_XO_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_DDRSS_XO_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_DDRSS_XO_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_DDRSS_XO_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_DDRSS_XO_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_DDRSS_XO_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_DDRSS_XO_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_DDRSS_XO_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_DDRSS_XO_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_DDRSS_XO_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_DDRSS_XO_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_DDRSS_XO_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_DDRSS_XO_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_XO_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_DDRSS_XO_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_DDRSS_XO_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_DDRSS_XO_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_XO_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f028) +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f028) +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f028) +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_DDRSS_CFG_AHB_CBCR_ADDR, HWIO_GCC_DDRSS_CFG_AHB_CBCR_RMSK) +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_DDRSS_CFG_AHB_CBCR_ADDR, m) +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_DDRSS_CFG_AHB_CBCR_ADDR,v) +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DDRSS_CFG_AHB_CBCR_ADDR,m,v,HWIO_GCC_DDRSS_CFG_AHB_CBCR_IN) +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_DDRSS_SLEEP_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f02c) +#define HWIO_GCC_DDRSS_SLEEP_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f02c) +#define HWIO_GCC_DDRSS_SLEEP_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f02c) +#define HWIO_GCC_DDRSS_SLEEP_CBCR_RMSK 0x81c0000f +#define HWIO_GCC_DDRSS_SLEEP_CBCR_ATTR 0x3 +#define HWIO_GCC_DDRSS_SLEEP_CBCR_IN \ + in_dword_masked(HWIO_GCC_DDRSS_SLEEP_CBCR_ADDR, HWIO_GCC_DDRSS_SLEEP_CBCR_RMSK) +#define HWIO_GCC_DDRSS_SLEEP_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_DDRSS_SLEEP_CBCR_ADDR, m) +#define HWIO_GCC_DDRSS_SLEEP_CBCR_OUT(v) \ + out_dword(HWIO_GCC_DDRSS_SLEEP_CBCR_ADDR,v) +#define HWIO_GCC_DDRSS_SLEEP_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DDRSS_SLEEP_CBCR_ADDR,m,v,HWIO_GCC_DDRSS_SLEEP_CBCR_IN) +#define HWIO_GCC_DDRSS_SLEEP_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_DDRSS_SLEEP_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_DDRSS_SLEEP_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_DDRSS_SLEEP_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_DDRSS_SLEEP_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_DDRSS_SLEEP_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_DDRSS_SLEEP_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_DDRSS_SLEEP_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_DDRSS_SLEEP_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_DDRSS_SLEEP_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_DDRSS_SLEEP_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_DDRSS_SLEEP_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_DDRSS_SLEEP_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_DDRSS_SLEEP_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_DDRSS_SLEEP_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_DDRSS_SLEEP_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_DDRSS_SLEEP_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_SLEEP_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_DDRSS_SLEEP_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_DDRSS_SLEEP_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_DDRSS_SLEEP_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_SLEEP_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MEMNOC_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f030) +#define HWIO_GCC_MEMNOC_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f030) +#define HWIO_GCC_MEMNOC_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f030) +#define HWIO_GCC_MEMNOC_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_MEMNOC_CBCR_ATTR 0x3 +#define HWIO_GCC_MEMNOC_CBCR_IN \ + in_dword_masked(HWIO_GCC_MEMNOC_CBCR_ADDR, HWIO_GCC_MEMNOC_CBCR_RMSK) +#define HWIO_GCC_MEMNOC_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_MEMNOC_CBCR_ADDR, m) +#define HWIO_GCC_MEMNOC_CBCR_OUT(v) \ + out_dword(HWIO_GCC_MEMNOC_CBCR_ADDR,v) +#define HWIO_GCC_MEMNOC_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MEMNOC_CBCR_ADDR,m,v,HWIO_GCC_MEMNOC_CBCR_IN) +#define HWIO_GCC_MEMNOC_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_MEMNOC_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_MEMNOC_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_MEMNOC_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_MEMNOC_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_MEMNOC_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_MEMNOC_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_MEMNOC_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_MEMNOC_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_MEMNOC_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_MEMNOC_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_MEMNOC_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_MEMNOC_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_MEMNOC_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_MEMNOC_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_MEMNOC_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_MEMNOC_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_MEMNOC_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_MEMNOC_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_MEMNOC_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_MEMNOC_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_MEMNOC_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_MEMNOC_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MEMNOC_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_DDRSS_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f034) +#define HWIO_GCC_DDRSS_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f034) +#define HWIO_GCC_DDRSS_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f034) +#define HWIO_GCC_DDRSS_AT_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_DDRSS_AT_CBCR_ATTR 0x3 +#define HWIO_GCC_DDRSS_AT_CBCR_IN \ + in_dword_masked(HWIO_GCC_DDRSS_AT_CBCR_ADDR, HWIO_GCC_DDRSS_AT_CBCR_RMSK) +#define HWIO_GCC_DDRSS_AT_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_DDRSS_AT_CBCR_ADDR, m) +#define HWIO_GCC_DDRSS_AT_CBCR_OUT(v) \ + out_dword(HWIO_GCC_DDRSS_AT_CBCR_ADDR,v) +#define HWIO_GCC_DDRSS_AT_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DDRSS_AT_CBCR_ADDR,m,v,HWIO_GCC_DDRSS_AT_CBCR_IN) +#define HWIO_GCC_DDRSS_AT_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_DDRSS_AT_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_DDRSS_AT_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_DDRSS_AT_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_DDRSS_AT_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_DDRSS_AT_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_DDRSS_AT_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_DDRSS_AT_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_DDRSS_AT_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_DDRSS_AT_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_DDRSS_AT_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_DDRSS_AT_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_DDRSS_AT_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_DDRSS_AT_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_DDRSS_AT_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_DDRSS_AT_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_DDRSS_AT_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_DDRSS_AT_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_DDRSS_AT_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_AT_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_DDRSS_AT_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_DDRSS_AT_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_DDRSS_AT_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_AT_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_DDRSS_MSS_MCDMA_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f038) +#define HWIO_GCC_DDRSS_MSS_MCDMA_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f038) +#define HWIO_GCC_DDRSS_MSS_MCDMA_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f038) +#define HWIO_GCC_DDRSS_MSS_MCDMA_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_DDRSS_MSS_MCDMA_CBCR_ATTR 0x3 +#define HWIO_GCC_DDRSS_MSS_MCDMA_CBCR_IN \ + in_dword_masked(HWIO_GCC_DDRSS_MSS_MCDMA_CBCR_ADDR, HWIO_GCC_DDRSS_MSS_MCDMA_CBCR_RMSK) +#define HWIO_GCC_DDRSS_MSS_MCDMA_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_DDRSS_MSS_MCDMA_CBCR_ADDR, m) +#define HWIO_GCC_DDRSS_MSS_MCDMA_CBCR_OUT(v) \ + out_dword(HWIO_GCC_DDRSS_MSS_MCDMA_CBCR_ADDR,v) +#define HWIO_GCC_DDRSS_MSS_MCDMA_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DDRSS_MSS_MCDMA_CBCR_ADDR,m,v,HWIO_GCC_DDRSS_MSS_MCDMA_CBCR_IN) +#define HWIO_GCC_DDRSS_MSS_MCDMA_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_DDRSS_MSS_MCDMA_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_DDRSS_MSS_MCDMA_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_DDRSS_MSS_MCDMA_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_DDRSS_MSS_MCDMA_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_DDRSS_MSS_MCDMA_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_DDRSS_MSS_MCDMA_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_DDRSS_MSS_MCDMA_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_DDRSS_MSS_MCDMA_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_DDRSS_MSS_MCDMA_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_DDRSS_MSS_MCDMA_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_DDRSS_MSS_MCDMA_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_DDRSS_MSS_MCDMA_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_DDRSS_MSS_MCDMA_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_DDRSS_MSS_MCDMA_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_DDRSS_MSS_MCDMA_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_DDRSS_MSS_MCDMA_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_DDRSS_MSS_MCDMA_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_DDRSS_MSS_MCDMA_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_MSS_MCDMA_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_DDRSS_MSS_MCDMA_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_DDRSS_MSS_MCDMA_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_DDRSS_MSS_MCDMA_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_MSS_MCDMA_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f058) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f058) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f058) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f05c) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f05c) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f05c) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f060) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f060) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f060) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f064) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f064) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f064) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f068) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f068) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f068) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f06c) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f06c) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f06c) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f070) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f070) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f070) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f074) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f074) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f074) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f078) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f078) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f078) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f07c) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f07c) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f07c) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f080) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f080) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f080) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f084) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f084) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f084) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f088) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f088) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f088) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f08c) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f08c) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f08c) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f090) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f090) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f090) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f094) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f094) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f094) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_MEMNOC_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f03c) +#define HWIO_GCC_MEMNOC_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f03c) +#define HWIO_GCC_MEMNOC_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f03c) +#define HWIO_GCC_MEMNOC_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_MEMNOC_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_MEMNOC_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_MEMNOC_CMD_RCGR_ADDR, HWIO_GCC_MEMNOC_CMD_RCGR_RMSK) +#define HWIO_GCC_MEMNOC_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_MEMNOC_CMD_RCGR_ADDR, m) +#define HWIO_GCC_MEMNOC_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_MEMNOC_CMD_RCGR_ADDR,v) +#define HWIO_GCC_MEMNOC_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MEMNOC_CMD_RCGR_ADDR,m,v,HWIO_GCC_MEMNOC_CMD_RCGR_IN) +#define HWIO_GCC_MEMNOC_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_MEMNOC_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_MEMNOC_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_MEMNOC_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_MEMNOC_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_MEMNOC_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_MEMNOC_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_MEMNOC_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_MEMNOC_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_MEMNOC_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_MEMNOC_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MEMNOC_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MEMNOC_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f040) +#define HWIO_GCC_MEMNOC_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f040) +#define HWIO_GCC_MEMNOC_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f040) +#define HWIO_GCC_MEMNOC_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_MEMNOC_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_MEMNOC_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_MEMNOC_CFG_RCGR_ADDR, HWIO_GCC_MEMNOC_CFG_RCGR_RMSK) +#define HWIO_GCC_MEMNOC_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_MEMNOC_CFG_RCGR_ADDR, m) +#define HWIO_GCC_MEMNOC_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_MEMNOC_CFG_RCGR_ADDR,v) +#define HWIO_GCC_MEMNOC_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MEMNOC_CFG_RCGR_ADDR,m,v,HWIO_GCC_MEMNOC_CFG_RCGR_IN) +#define HWIO_GCC_MEMNOC_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_MEMNOC_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_MEMNOC_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_MEMNOC_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_MEMNOC_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_MEMNOC_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_MEMNOC_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_MEMNOC_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f17c) +#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f17c) +#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f17c) +#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_RMSK 0xffff +#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_CMD_DFSR_ADDR, HWIO_GCC_RPMH_SHRM_CMD_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_CMD_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_CMD_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_CMD_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHRM_CMD_DFSR_IN) +#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_RCG_SW_CTRL_BMSK 0x8000 +#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_RCG_SW_CTRL_SHFT 0xf +#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_SW_PERF_STATE_BMSK 0x7800 +#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_SW_PERF_STATE_SHFT 0xb +#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_SW_OVERRIDE_BMSK 0x400 +#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_SW_OVERRIDE_SHFT 0xa +#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK 0x200 +#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT 0x9 +#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_DFS_FSM_STATE_BMSK 0x1c0 +#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_DFS_FSM_STATE_SHFT 0x6 +#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_HW_CLK_CONTROL_BMSK 0x20 +#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_HW_CLK_CONTROL_SHFT 0x5 +#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_CURR_PERF_STATE_BMSK 0x1e +#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_CURR_PERF_STATE_SHFT 0x1 +#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_DFS_EN_BMSK 0x1 +#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_DFS_EN_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_DFS_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_DFS_EN_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f184) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f184) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f184) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_ADDR, HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_IN) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f188) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f188) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f188) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_ADDR, HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_IN) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f18c) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f18c) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f18c) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_ADDR, HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_IN) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f190) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f190) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f190) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_ADDR, HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_IN) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f194) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f194) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f194) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_ADDR, HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_IN) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f198) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f198) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f198) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_ADDR, HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_IN) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f19c) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f19c) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f19c) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_ADDR, HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_IN) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f1a0) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f1a0) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f1a0) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_ADDR, HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_IN) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f1a4) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f1a4) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f1a4) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_ADDR, HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_IN) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f1a8) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f1a8) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f1a8) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_ADDR, HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_IN) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f1ac) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f1ac) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f1ac) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_ADDR, HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_IN) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f1b0) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f1b0) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f1b0) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_ADDR, HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_IN) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f1b4) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f1b4) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f1b4) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_ADDR, HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_IN) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f1b8) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f1b8) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f1b8) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_ADDR, HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_IN) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f1bc) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f1bc) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f1bc) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_ADDR, HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_IN) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f1c0) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f1c0) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f1c0) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_ADDR, HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_IN) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_SHRM_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f168) +#define HWIO_GCC_SHRM_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f168) +#define HWIO_GCC_SHRM_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f168) +#define HWIO_GCC_SHRM_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_SHRM_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_SHRM_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_SHRM_CMD_RCGR_ADDR, HWIO_GCC_SHRM_CMD_RCGR_RMSK) +#define HWIO_GCC_SHRM_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_SHRM_CMD_RCGR_ADDR, m) +#define HWIO_GCC_SHRM_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_SHRM_CMD_RCGR_ADDR,v) +#define HWIO_GCC_SHRM_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SHRM_CMD_RCGR_ADDR,m,v,HWIO_GCC_SHRM_CMD_RCGR_IN) +#define HWIO_GCC_SHRM_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_SHRM_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_SHRM_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_SHRM_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_SHRM_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_SHRM_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_SHRM_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_SHRM_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_SHRM_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_SHRM_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_SHRM_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SHRM_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SHRM_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f16c) +#define HWIO_GCC_SHRM_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f16c) +#define HWIO_GCC_SHRM_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f16c) +#define HWIO_GCC_SHRM_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_SHRM_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_SHRM_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_SHRM_CFG_RCGR_ADDR, HWIO_GCC_SHRM_CFG_RCGR_RMSK) +#define HWIO_GCC_SHRM_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_SHRM_CFG_RCGR_ADDR, m) +#define HWIO_GCC_SHRM_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_SHRM_CFG_RCGR_ADDR,v) +#define HWIO_GCC_SHRM_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SHRM_CFG_RCGR_ADDR,m,v,HWIO_GCC_SHRM_CFG_RCGR_IN) +#define HWIO_GCC_SHRM_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_SHRM_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_SHRM_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_SHRM_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_SHRM_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_SHRM_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_SHRM_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_SHRM_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_SHRM_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f294) +#define HWIO_GCC_SHRM_DCD_CDIV_DCDR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f294) +#define HWIO_GCC_SHRM_DCD_CDIV_DCDR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f294) +#define HWIO_GCC_SHRM_DCD_CDIV_DCDR_RMSK 0x1 +#define HWIO_GCC_SHRM_DCD_CDIV_DCDR_ATTR 0x3 +#define HWIO_GCC_SHRM_DCD_CDIV_DCDR_IN \ + in_dword_masked(HWIO_GCC_SHRM_DCD_CDIV_DCDR_ADDR, HWIO_GCC_SHRM_DCD_CDIV_DCDR_RMSK) +#define HWIO_GCC_SHRM_DCD_CDIV_DCDR_INM(m) \ + in_dword_masked(HWIO_GCC_SHRM_DCD_CDIV_DCDR_ADDR, m) +#define HWIO_GCC_SHRM_DCD_CDIV_DCDR_OUT(v) \ + out_dword(HWIO_GCC_SHRM_DCD_CDIV_DCDR_ADDR,v) +#define HWIO_GCC_SHRM_DCD_CDIV_DCDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SHRM_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_SHRM_DCD_CDIV_DCDR_IN) +#define HWIO_GCC_SHRM_DCD_CDIV_DCDR_DCD_ENABLE_BMSK 0x1 +#define HWIO_GCC_SHRM_DCD_CDIV_DCDR_DCD_ENABLE_SHFT 0x0 +#define HWIO_GCC_SHRM_DCD_CDIV_DCDR_DCD_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SHRM_DCD_CDIV_DCDR_DCD_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MEMNOC_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f298) +#define HWIO_GCC_MEMNOC_DCD_CDIV_DCDR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f298) +#define HWIO_GCC_MEMNOC_DCD_CDIV_DCDR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f298) +#define HWIO_GCC_MEMNOC_DCD_CDIV_DCDR_RMSK 0x1 +#define HWIO_GCC_MEMNOC_DCD_CDIV_DCDR_ATTR 0x3 +#define HWIO_GCC_MEMNOC_DCD_CDIV_DCDR_IN \ + in_dword_masked(HWIO_GCC_MEMNOC_DCD_CDIV_DCDR_ADDR, HWIO_GCC_MEMNOC_DCD_CDIV_DCDR_RMSK) +#define HWIO_GCC_MEMNOC_DCD_CDIV_DCDR_INM(m) \ + in_dword_masked(HWIO_GCC_MEMNOC_DCD_CDIV_DCDR_ADDR, m) +#define HWIO_GCC_MEMNOC_DCD_CDIV_DCDR_OUT(v) \ + out_dword(HWIO_GCC_MEMNOC_DCD_CDIV_DCDR_ADDR,v) +#define HWIO_GCC_MEMNOC_DCD_CDIV_DCDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MEMNOC_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_MEMNOC_DCD_CDIV_DCDR_IN) +#define HWIO_GCC_MEMNOC_DCD_CDIV_DCDR_DCD_ENABLE_BMSK 0x1 +#define HWIO_GCC_MEMNOC_DCD_CDIV_DCDR_DCD_ENABLE_SHFT 0x0 +#define HWIO_GCC_MEMNOC_DCD_CDIV_DCDR_DCD_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MEMNOC_DCD_CDIV_DCDR_DCD_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_DDR_I_HCLK_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f29c) +#define HWIO_GCC_DDR_I_HCLK_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f29c) +#define HWIO_GCC_DDR_I_HCLK_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f29c) +#define HWIO_GCC_DDR_I_HCLK_CBCR_RMSK 0x81c0000f +#define HWIO_GCC_DDR_I_HCLK_CBCR_ATTR 0x3 +#define HWIO_GCC_DDR_I_HCLK_CBCR_IN \ + in_dword_masked(HWIO_GCC_DDR_I_HCLK_CBCR_ADDR, HWIO_GCC_DDR_I_HCLK_CBCR_RMSK) +#define HWIO_GCC_DDR_I_HCLK_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_DDR_I_HCLK_CBCR_ADDR, m) +#define HWIO_GCC_DDR_I_HCLK_CBCR_OUT(v) \ + out_dword(HWIO_GCC_DDR_I_HCLK_CBCR_ADDR,v) +#define HWIO_GCC_DDR_I_HCLK_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DDR_I_HCLK_CBCR_ADDR,m,v,HWIO_GCC_DDR_I_HCLK_CBCR_IN) +#define HWIO_GCC_DDR_I_HCLK_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_DDR_I_HCLK_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_DDR_I_HCLK_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_DDR_I_HCLK_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_DDR_I_HCLK_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_DDR_I_HCLK_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_DDR_I_HCLK_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_DDR_I_HCLK_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_DDR_I_HCLK_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_DDR_I_HCLK_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_DDR_I_HCLK_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_DDR_I_HCLK_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_DDR_I_HCLK_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_DDR_I_HCLK_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_DDR_I_HCLK_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_DDR_I_HCLK_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_DDR_I_HCLK_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDR_I_HCLK_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_DDR_I_HCLK_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_DDR_I_HCLK_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_DDR_I_HCLK_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDR_I_HCLK_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_DDRMC_CH0_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f2a0) +#define HWIO_GCC_DDRMC_CH0_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f2a0) +#define HWIO_GCC_DDRMC_CH0_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f2a0) +#define HWIO_GCC_DDRMC_CH0_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_DDRMC_CH0_CBCR_ATTR 0x3 +#define HWIO_GCC_DDRMC_CH0_CBCR_IN \ + in_dword_masked(HWIO_GCC_DDRMC_CH0_CBCR_ADDR, HWIO_GCC_DDRMC_CH0_CBCR_RMSK) +#define HWIO_GCC_DDRMC_CH0_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_DDRMC_CH0_CBCR_ADDR, m) +#define HWIO_GCC_DDRMC_CH0_CBCR_OUT(v) \ + out_dword(HWIO_GCC_DDRMC_CH0_CBCR_ADDR,v) +#define HWIO_GCC_DDRMC_CH0_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DDRMC_CH0_CBCR_ADDR,m,v,HWIO_GCC_DDRMC_CH0_CBCR_IN) +#define HWIO_GCC_DDRMC_CH0_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_DDRMC_CH0_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_DDRMC_CH0_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_DDRMC_CH0_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_DDRMC_CH0_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_DDRMC_CH0_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_DDRMC_CH0_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_DDRMC_CH0_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_DDRMC_CH0_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_DDRMC_CH0_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_DDRMC_CH0_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_DDRMC_CH0_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_DDRMC_CH0_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_DDRMC_CH0_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_DDRMC_CH0_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_DDRMC_CH0_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_DDRMC_CH0_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_DDRMC_CH0_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_DDRMC_CH0_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRMC_CH0_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_DDRMC_CH0_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_DDRMC_CH0_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_DDRMC_CH0_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRMC_CH0_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_DDRMC_CH1_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f2a4) +#define HWIO_GCC_DDRMC_CH1_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f2a4) +#define HWIO_GCC_DDRMC_CH1_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f2a4) +#define HWIO_GCC_DDRMC_CH1_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_DDRMC_CH1_CBCR_ATTR 0x3 +#define HWIO_GCC_DDRMC_CH1_CBCR_IN \ + in_dword_masked(HWIO_GCC_DDRMC_CH1_CBCR_ADDR, HWIO_GCC_DDRMC_CH1_CBCR_RMSK) +#define HWIO_GCC_DDRMC_CH1_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_DDRMC_CH1_CBCR_ADDR, m) +#define HWIO_GCC_DDRMC_CH1_CBCR_OUT(v) \ + out_dword(HWIO_GCC_DDRMC_CH1_CBCR_ADDR,v) +#define HWIO_GCC_DDRMC_CH1_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DDRMC_CH1_CBCR_ADDR,m,v,HWIO_GCC_DDRMC_CH1_CBCR_IN) +#define HWIO_GCC_DDRMC_CH1_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_DDRMC_CH1_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_DDRMC_CH1_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_DDRMC_CH1_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_DDRMC_CH1_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_DDRMC_CH1_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_DDRMC_CH1_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_DDRMC_CH1_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_DDRMC_CH1_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_DDRMC_CH1_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_DDRMC_CH1_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_DDRMC_CH1_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_DDRMC_CH1_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_DDRMC_CH1_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_DDRMC_CH1_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_DDRMC_CH1_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_DDRMC_CH1_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_DDRMC_CH1_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_DDRMC_CH1_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRMC_CH1_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_DDRMC_CH1_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_DDRMC_CH1_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_DDRMC_CH1_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRMC_CH1_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f2bc) +#define HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f2bc) +#define HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f2bc) +#define HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_RMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_ADDR, HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_RMSK) +#define HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_IN) +#define HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_RCG_SW_CTRL_BMSK 0x8000 +#define HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_RCG_SW_CTRL_SHFT 0xf +#define HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_SW_PERF_STATE_BMSK 0x7800 +#define HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_SW_PERF_STATE_SHFT 0xb +#define HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_SW_OVERRIDE_BMSK 0x400 +#define HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_SW_OVERRIDE_SHFT 0xa +#define HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK 0x200 +#define HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT 0x9 +#define HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_DFS_FSM_STATE_BMSK 0x1c0 +#define HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_DFS_FSM_STATE_SHFT 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_HW_CLK_CONTROL_BMSK 0x20 +#define HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_HW_CLK_CONTROL_SHFT 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_CURR_PERF_STATE_BMSK 0x1e +#define HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_CURR_PERF_STATE_SHFT 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_DFS_EN_BMSK 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_DFS_EN_SHFT 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_DFS_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_DFS_EN_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f2c4) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f2c4) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f2c4) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_ADDR, HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_RMSK) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_IN) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f2c8) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f2c8) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f2c8) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_ADDR, HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_RMSK) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_IN) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f2cc) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f2cc) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f2cc) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_ADDR, HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_RMSK) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_IN) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f2d0) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f2d0) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f2d0) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_ADDR, HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_RMSK) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_IN) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f2d4) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f2d4) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f2d4) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_ADDR, HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_RMSK) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_IN) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f2d8) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f2d8) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f2d8) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_ADDR, HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_RMSK) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_IN) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f2dc) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f2dc) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f2dc) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_ADDR, HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_RMSK) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_IN) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f2e0) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f2e0) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f2e0) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_ADDR, HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_RMSK) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_IN) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f2e4) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f2e4) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f2e4) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_ADDR, HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_RMSK) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_IN) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f2e8) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f2e8) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f2e8) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_ADDR, HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_RMSK) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_IN) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f2ec) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f2ec) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f2ec) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_ADDR, HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_RMSK) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_IN) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f2f0) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f2f0) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f2f0) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_ADDR, HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_RMSK) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_IN) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f2f4) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f2f4) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f2f4) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_ADDR, HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_RMSK) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_IN) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f2f8) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f2f8) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f2f8) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_ADDR, HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_RMSK) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_IN) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f2fc) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f2fc) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f2fc) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_ADDR, HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_RMSK) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_IN) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f300) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f300) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f300) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_ADDR, HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_RMSK) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_IN) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_DDRMC_CH0_ROOT_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f2a8) +#define HWIO_GCC_DDRMC_CH0_ROOT_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f2a8) +#define HWIO_GCC_DDRMC_CH0_ROOT_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f2a8) +#define HWIO_GCC_DDRMC_CH0_ROOT_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_DDRMC_CH0_ROOT_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_DDRMC_CH0_ROOT_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_DDRMC_CH0_ROOT_CMD_RCGR_ADDR, HWIO_GCC_DDRMC_CH0_ROOT_CMD_RCGR_RMSK) +#define HWIO_GCC_DDRMC_CH0_ROOT_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_DDRMC_CH0_ROOT_CMD_RCGR_ADDR, m) +#define HWIO_GCC_DDRMC_CH0_ROOT_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_DDRMC_CH0_ROOT_CMD_RCGR_ADDR,v) +#define HWIO_GCC_DDRMC_CH0_ROOT_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DDRMC_CH0_ROOT_CMD_RCGR_ADDR,m,v,HWIO_GCC_DDRMC_CH0_ROOT_CMD_RCGR_IN) +#define HWIO_GCC_DDRMC_CH0_ROOT_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_DDRMC_CH0_ROOT_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_DDRMC_CH0_ROOT_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_DDRMC_CH0_ROOT_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_DDRMC_CH0_ROOT_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_DDRMC_CH0_ROOT_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_DDRMC_CH0_ROOT_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRMC_CH0_ROOT_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_DDRMC_CH0_ROOT_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_DDRMC_CH0_ROOT_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_DDRMC_CH0_ROOT_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRMC_CH0_ROOT_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f2ac) +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f2ac) +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f2ac) +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_ADDR, HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_RMSK) +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_ADDR, m) +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_ADDR,v) +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_ADDR,m,v,HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_IN) +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_DDRMC_CH0_ROOT_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f3d4) +#define HWIO_GCC_DDRMC_CH0_ROOT_DCD_CDIV_DCDR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f3d4) +#define HWIO_GCC_DDRMC_CH0_ROOT_DCD_CDIV_DCDR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f3d4) +#define HWIO_GCC_DDRMC_CH0_ROOT_DCD_CDIV_DCDR_RMSK 0x1 +#define HWIO_GCC_DDRMC_CH0_ROOT_DCD_CDIV_DCDR_ATTR 0x3 +#define HWIO_GCC_DDRMC_CH0_ROOT_DCD_CDIV_DCDR_IN \ + in_dword_masked(HWIO_GCC_DDRMC_CH0_ROOT_DCD_CDIV_DCDR_ADDR, HWIO_GCC_DDRMC_CH0_ROOT_DCD_CDIV_DCDR_RMSK) +#define HWIO_GCC_DDRMC_CH0_ROOT_DCD_CDIV_DCDR_INM(m) \ + in_dword_masked(HWIO_GCC_DDRMC_CH0_ROOT_DCD_CDIV_DCDR_ADDR, m) +#define HWIO_GCC_DDRMC_CH0_ROOT_DCD_CDIV_DCDR_OUT(v) \ + out_dword(HWIO_GCC_DDRMC_CH0_ROOT_DCD_CDIV_DCDR_ADDR,v) +#define HWIO_GCC_DDRMC_CH0_ROOT_DCD_CDIV_DCDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DDRMC_CH0_ROOT_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_DDRMC_CH0_ROOT_DCD_CDIV_DCDR_IN) +#define HWIO_GCC_DDRMC_CH0_ROOT_DCD_CDIV_DCDR_DCD_ENABLE_BMSK 0x1 +#define HWIO_GCC_DDRMC_CH0_ROOT_DCD_CDIV_DCDR_DCD_ENABLE_SHFT 0x0 +#define HWIO_GCC_DDRMC_CH0_ROOT_DCD_CDIV_DCDR_DCD_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRMC_CH0_ROOT_DCD_CDIV_DCDR_DCD_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f3ec) +#define HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f3ec) +#define HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f3ec) +#define HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_RMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_ADDR, HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_RMSK) +#define HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_IN) +#define HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_RCG_SW_CTRL_BMSK 0x8000 +#define HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_RCG_SW_CTRL_SHFT 0xf +#define HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_SW_PERF_STATE_BMSK 0x7800 +#define HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_SW_PERF_STATE_SHFT 0xb +#define HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_SW_OVERRIDE_BMSK 0x400 +#define HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_SW_OVERRIDE_SHFT 0xa +#define HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK 0x200 +#define HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT 0x9 +#define HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_DFS_FSM_STATE_BMSK 0x1c0 +#define HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_DFS_FSM_STATE_SHFT 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_HW_CLK_CONTROL_BMSK 0x20 +#define HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_HW_CLK_CONTROL_SHFT 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_CURR_PERF_STATE_BMSK 0x1e +#define HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_CURR_PERF_STATE_SHFT 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_DFS_EN_BMSK 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_DFS_EN_SHFT 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_DFS_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_DFS_EN_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f3f4) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f3f4) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f3f4) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_ADDR, HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_RMSK) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_IN) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f3f8) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f3f8) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f3f8) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_ADDR, HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_RMSK) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_IN) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f3fc) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f3fc) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f3fc) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_ADDR, HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_RMSK) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_IN) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f400) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f400) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f400) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_ADDR, HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_RMSK) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_IN) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f404) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f404) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f404) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_ADDR, HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_RMSK) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_IN) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f408) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f408) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f408) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_ADDR, HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_RMSK) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_IN) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f40c) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f40c) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f40c) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_ADDR, HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_RMSK) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_IN) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f410) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f410) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f410) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_ADDR, HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_RMSK) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_IN) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f414) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f414) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f414) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_ADDR, HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_RMSK) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_IN) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f418) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f418) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f418) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_ADDR, HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_RMSK) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_IN) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f41c) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f41c) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f41c) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_ADDR, HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_RMSK) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_IN) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f420) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f420) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f420) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_ADDR, HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_RMSK) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_IN) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f424) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f424) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f424) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_ADDR, HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_RMSK) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_IN) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f428) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f428) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f428) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_ADDR, HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_RMSK) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_IN) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f42c) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f42c) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f42c) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_ADDR, HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_RMSK) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_IN) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f430) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f430) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f430) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_ADDR, HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_RMSK) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_IN) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_DDRMC_CH1_ROOT_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f3d8) +#define HWIO_GCC_DDRMC_CH1_ROOT_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f3d8) +#define HWIO_GCC_DDRMC_CH1_ROOT_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f3d8) +#define HWIO_GCC_DDRMC_CH1_ROOT_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_DDRMC_CH1_ROOT_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_DDRMC_CH1_ROOT_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_DDRMC_CH1_ROOT_CMD_RCGR_ADDR, HWIO_GCC_DDRMC_CH1_ROOT_CMD_RCGR_RMSK) +#define HWIO_GCC_DDRMC_CH1_ROOT_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_DDRMC_CH1_ROOT_CMD_RCGR_ADDR, m) +#define HWIO_GCC_DDRMC_CH1_ROOT_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_DDRMC_CH1_ROOT_CMD_RCGR_ADDR,v) +#define HWIO_GCC_DDRMC_CH1_ROOT_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DDRMC_CH1_ROOT_CMD_RCGR_ADDR,m,v,HWIO_GCC_DDRMC_CH1_ROOT_CMD_RCGR_IN) +#define HWIO_GCC_DDRMC_CH1_ROOT_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_DDRMC_CH1_ROOT_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_DDRMC_CH1_ROOT_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_DDRMC_CH1_ROOT_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_DDRMC_CH1_ROOT_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_DDRMC_CH1_ROOT_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_DDRMC_CH1_ROOT_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRMC_CH1_ROOT_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_DDRMC_CH1_ROOT_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_DDRMC_CH1_ROOT_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_DDRMC_CH1_ROOT_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRMC_CH1_ROOT_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f3dc) +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f3dc) +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f3dc) +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_ADDR, HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_RMSK) +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_ADDR, m) +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_ADDR,v) +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_ADDR,m,v,HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_IN) +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_DDRMC_CH1_ROOT_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f504) +#define HWIO_GCC_DDRMC_CH1_ROOT_DCD_CDIV_DCDR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f504) +#define HWIO_GCC_DDRMC_CH1_ROOT_DCD_CDIV_DCDR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f504) +#define HWIO_GCC_DDRMC_CH1_ROOT_DCD_CDIV_DCDR_RMSK 0x1 +#define HWIO_GCC_DDRMC_CH1_ROOT_DCD_CDIV_DCDR_ATTR 0x3 +#define HWIO_GCC_DDRMC_CH1_ROOT_DCD_CDIV_DCDR_IN \ + in_dword_masked(HWIO_GCC_DDRMC_CH1_ROOT_DCD_CDIV_DCDR_ADDR, HWIO_GCC_DDRMC_CH1_ROOT_DCD_CDIV_DCDR_RMSK) +#define HWIO_GCC_DDRMC_CH1_ROOT_DCD_CDIV_DCDR_INM(m) \ + in_dword_masked(HWIO_GCC_DDRMC_CH1_ROOT_DCD_CDIV_DCDR_ADDR, m) +#define HWIO_GCC_DDRMC_CH1_ROOT_DCD_CDIV_DCDR_OUT(v) \ + out_dword(HWIO_GCC_DDRMC_CH1_ROOT_DCD_CDIV_DCDR_ADDR,v) +#define HWIO_GCC_DDRMC_CH1_ROOT_DCD_CDIV_DCDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DDRMC_CH1_ROOT_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_DDRMC_CH1_ROOT_DCD_CDIV_DCDR_IN) +#define HWIO_GCC_DDRMC_CH1_ROOT_DCD_CDIV_DCDR_DCD_ENABLE_BMSK 0x1 +#define HWIO_GCC_DDRMC_CH1_ROOT_DCD_CDIV_DCDR_DCD_ENABLE_SHFT 0x0 +#define HWIO_GCC_DDRMC_CH1_ROOT_DCD_CDIV_DCDR_DCD_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRMC_CH1_ROOT_DCD_CDIV_DCDR_DCD_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CPUSS_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00020000) +#define HWIO_GCC_CPUSS_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00020000) +#define HWIO_GCC_CPUSS_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00020000) +#define HWIO_GCC_CPUSS_AHB_CBCR_RMSK 0x81c0000e +#define HWIO_GCC_CPUSS_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_CPUSS_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_CPUSS_AHB_CBCR_ADDR, HWIO_GCC_CPUSS_AHB_CBCR_RMSK) +#define HWIO_GCC_CPUSS_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_CPUSS_AHB_CBCR_ADDR, m) +#define HWIO_GCC_CPUSS_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_CPUSS_AHB_CBCR_ADDR,v) +#define HWIO_GCC_CPUSS_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CPUSS_AHB_CBCR_ADDR,m,v,HWIO_GCC_CPUSS_AHB_CBCR_IN) +#define HWIO_GCC_CPUSS_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_CPUSS_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_CPUSS_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_CPUSS_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_CPUSS_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_CPUSS_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_CPUSS_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_CPUSS_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_CPUSS_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_CPUSS_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_CPUSS_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_CPUSS_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_CPUSS_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_CPUSS_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_CPUSS_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_CPUSS_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_CPUSS_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_CPUSS_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CPUSS_GNOC_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00020004) +#define HWIO_GCC_CPUSS_GNOC_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00020004) +#define HWIO_GCC_CPUSS_GNOC_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00020004) +#define HWIO_GCC_CPUSS_GNOC_CBCR_RMSK 0x81d0000e +#define HWIO_GCC_CPUSS_GNOC_CBCR_ATTR 0x3 +#define HWIO_GCC_CPUSS_GNOC_CBCR_IN \ + in_dword_masked(HWIO_GCC_CPUSS_GNOC_CBCR_ADDR, HWIO_GCC_CPUSS_GNOC_CBCR_RMSK) +#define HWIO_GCC_CPUSS_GNOC_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_CPUSS_GNOC_CBCR_ADDR, m) +#define HWIO_GCC_CPUSS_GNOC_CBCR_OUT(v) \ + out_dword(HWIO_GCC_CPUSS_GNOC_CBCR_ADDR,v) +#define HWIO_GCC_CPUSS_GNOC_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CPUSS_GNOC_CBCR_ADDR,m,v,HWIO_GCC_CPUSS_GNOC_CBCR_IN) +#define HWIO_GCC_CPUSS_GNOC_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_CPUSS_GNOC_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_CPUSS_GNOC_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_CPUSS_GNOC_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_CPUSS_GNOC_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_CPUSS_GNOC_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_CPUSS_GNOC_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_CPUSS_GNOC_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_CPUSS_GNOC_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_CPUSS_GNOC_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_CPUSS_GNOC_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_CPUSS_GNOC_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_CPUSS_GNOC_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_CPUSS_GNOC_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_CPUSS_GNOC_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_CPUSS_GNOC_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_CPUSS_GNOC_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_CPUSS_GNOC_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_CPUSS_GNOC_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_CPUSS_GNOC_CBCR_HW_CTL_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CPUSS_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00020008) +#define HWIO_GCC_CPUSS_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00020008) +#define HWIO_GCC_CPUSS_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00020008) +#define HWIO_GCC_CPUSS_AT_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_CPUSS_AT_CBCR_ATTR 0x3 +#define HWIO_GCC_CPUSS_AT_CBCR_IN \ + in_dword_masked(HWIO_GCC_CPUSS_AT_CBCR_ADDR, HWIO_GCC_CPUSS_AT_CBCR_RMSK) +#define HWIO_GCC_CPUSS_AT_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_CPUSS_AT_CBCR_ADDR, m) +#define HWIO_GCC_CPUSS_AT_CBCR_OUT(v) \ + out_dword(HWIO_GCC_CPUSS_AT_CBCR_ADDR,v) +#define HWIO_GCC_CPUSS_AT_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CPUSS_AT_CBCR_ADDR,m,v,HWIO_GCC_CPUSS_AT_CBCR_IN) +#define HWIO_GCC_CPUSS_AT_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_CPUSS_AT_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_CPUSS_AT_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_CPUSS_AT_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_CPUSS_AT_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_CPUSS_AT_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_CPUSS_AT_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_CPUSS_AT_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_CPUSS_AT_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_CPUSS_AT_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_CPUSS_AT_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_CPUSS_AT_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_CPUSS_AT_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_CPUSS_AT_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_CPUSS_AT_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_CPUSS_AT_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_CPUSS_AT_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_CPUSS_AT_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_CPUSS_AT_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_CPUSS_AT_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_CPUSS_AT_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_CPUSS_AT_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_CPUSS_AT_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CPUSS_AT_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CPUSS_AHB_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002000c) +#define HWIO_GCC_CPUSS_AHB_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002000c) +#define HWIO_GCC_CPUSS_AHB_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002000c) +#define HWIO_GCC_CPUSS_AHB_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_CPUSS_AHB_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_CPUSS_AHB_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_CPUSS_AHB_CMD_RCGR_ADDR, HWIO_GCC_CPUSS_AHB_CMD_RCGR_RMSK) +#define HWIO_GCC_CPUSS_AHB_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_CPUSS_AHB_CMD_RCGR_ADDR, m) +#define HWIO_GCC_CPUSS_AHB_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_CPUSS_AHB_CMD_RCGR_ADDR,v) +#define HWIO_GCC_CPUSS_AHB_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CPUSS_AHB_CMD_RCGR_ADDR,m,v,HWIO_GCC_CPUSS_AHB_CMD_RCGR_IN) +#define HWIO_GCC_CPUSS_AHB_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_CPUSS_AHB_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_CPUSS_AHB_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_CPUSS_AHB_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_CPUSS_AHB_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_CPUSS_AHB_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_CPUSS_AHB_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_CPUSS_AHB_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_CPUSS_AHB_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_CPUSS_AHB_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_CPUSS_AHB_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CPUSS_AHB_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00020010) +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00020010) +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00020010) +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_CPUSS_AHB_CFG_RCGR_ADDR, HWIO_GCC_CPUSS_AHB_CFG_RCGR_RMSK) +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_CPUSS_AHB_CFG_RCGR_ADDR, m) +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_CPUSS_AHB_CFG_RCGR_ADDR,v) +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CPUSS_AHB_CFG_RCGR_ADDR,m,v,HWIO_GCC_CPUSS_AHB_CFG_RCGR_IN) +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_CPUSS_AHB_POSTDIV_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00020024) +#define HWIO_GCC_CPUSS_AHB_POSTDIV_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00020024) +#define HWIO_GCC_CPUSS_AHB_POSTDIV_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00020024) +#define HWIO_GCC_CPUSS_AHB_POSTDIV_CDIVR_RMSK 0xf +#define HWIO_GCC_CPUSS_AHB_POSTDIV_CDIVR_ATTR 0x3 +#define HWIO_GCC_CPUSS_AHB_POSTDIV_CDIVR_IN \ + in_dword_masked(HWIO_GCC_CPUSS_AHB_POSTDIV_CDIVR_ADDR, HWIO_GCC_CPUSS_AHB_POSTDIV_CDIVR_RMSK) +#define HWIO_GCC_CPUSS_AHB_POSTDIV_CDIVR_INM(m) \ + in_dword_masked(HWIO_GCC_CPUSS_AHB_POSTDIV_CDIVR_ADDR, m) +#define HWIO_GCC_CPUSS_AHB_POSTDIV_CDIVR_OUT(v) \ + out_dword(HWIO_GCC_CPUSS_AHB_POSTDIV_CDIVR_ADDR,v) +#define HWIO_GCC_CPUSS_AHB_POSTDIV_CDIVR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CPUSS_AHB_POSTDIV_CDIVR_ADDR,m,v,HWIO_GCC_CPUSS_AHB_POSTDIV_CDIVR_IN) +#define HWIO_GCC_CPUSS_AHB_POSTDIV_CDIVR_CLK_DIV_BMSK 0xf +#define HWIO_GCC_CPUSS_AHB_POSTDIV_CDIVR_CLK_DIV_SHFT 0x0 + +#define HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00020028) +#define HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00020028) +#define HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00020028) +#define HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_ADDR, HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_RMSK) +#define HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_ADDR, m) +#define HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_ADDR,v) +#define HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_ADDR,m,v,HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_IN) +#define HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002002c) +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002002c) +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002002c) +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_ADDR, HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_RMSK) +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_ADDR, m) +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_ADDR,v) +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_ADDR,m,v,HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_IN) +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00020040) +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00020040) +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00020040) +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_RMSK 0x81c0000f +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_ATTR 0x3 +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_IN \ + in_dword_masked(HWIO_GCC_APSS_QDSS_TSCTR_CBCR_ADDR, HWIO_GCC_APSS_QDSS_TSCTR_CBCR_RMSK) +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_APSS_QDSS_TSCTR_CBCR_ADDR, m) +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_OUT(v) \ + out_dword(HWIO_GCC_APSS_QDSS_TSCTR_CBCR_ADDR,v) +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_APSS_QDSS_TSCTR_CBCR_ADDR,m,v,HWIO_GCC_APSS_QDSS_TSCTR_CBCR_IN) +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_APSS_QDSS_APB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00020044) +#define HWIO_GCC_APSS_QDSS_APB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00020044) +#define HWIO_GCC_APSS_QDSS_APB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00020044) +#define HWIO_GCC_APSS_QDSS_APB_CBCR_RMSK 0x81c0000f +#define HWIO_GCC_APSS_QDSS_APB_CBCR_ATTR 0x3 +#define HWIO_GCC_APSS_QDSS_APB_CBCR_IN \ + in_dword_masked(HWIO_GCC_APSS_QDSS_APB_CBCR_ADDR, HWIO_GCC_APSS_QDSS_APB_CBCR_RMSK) +#define HWIO_GCC_APSS_QDSS_APB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_APSS_QDSS_APB_CBCR_ADDR, m) +#define HWIO_GCC_APSS_QDSS_APB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_APSS_QDSS_APB_CBCR_ADDR,v) +#define HWIO_GCC_APSS_QDSS_APB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_APSS_QDSS_APB_CBCR_ADDR,m,v,HWIO_GCC_APSS_QDSS_APB_CBCR_IN) +#define HWIO_GCC_APSS_QDSS_APB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_APSS_QDSS_APB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_APSS_QDSS_APB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_APSS_QDSS_APB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_APSS_QDSS_APB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_APSS_QDSS_APB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_APSS_QDSS_APB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_APSS_QDSS_APB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_APSS_QDSS_APB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_APSS_QDSS_APB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_APSS_QDSS_APB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_APSS_QDSS_APB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_APSS_QDSS_APB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_APSS_QDSS_APB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_APSS_QDSS_APB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_APSS_QDSS_APB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_APSS_QDSS_APB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_APSS_QDSS_APB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_APSS_QDSS_APB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_APSS_QDSS_APB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_APSS_QDSS_APB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APSS_QDSS_APB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00021000) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00021000) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00021000) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_BCR_RMSK 0x1 +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_BCR_ATTR 0x3 +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_BCR_IN \ + in_dword_masked(HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_BCR_ADDR, HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_BCR_RMSK) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_BCR_ADDR, m) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_BCR_OUT(v) \ + out_dword(HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_BCR_ADDR,v) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_BCR_ADDR,m,v,HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_BCR_IN) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00021004) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00021004) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00021004) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_ATTR 0x3 +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_IN \ + in_dword_masked(HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_ADDR, HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_RMSK) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_ADDR, m) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_OUT(v) \ + out_dword(HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_ADDR,v) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_ADDR,m,v,HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_IN) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00021008) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00021008) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00021008) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CDIVR_RMSK 0xf +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CDIVR_ATTR 0x3 +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CDIVR_IN \ + in_dword_masked(HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CDIVR_ADDR, HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CDIVR_RMSK) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CDIVR_INM(m) \ + in_dword_masked(HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CDIVR_ADDR, m) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CDIVR_OUT(v) \ + out_dword(HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CDIVR_ADDR,v) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CDIVR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CDIVR_ADDR,m,v,HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CDIVR_IN) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CDIVR_CLK_DIV_BMSK 0xf +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CDIVR_CLK_DIV_SHFT 0x0 + +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV1024_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002100c) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV1024_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002100c) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV1024_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002100c) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV1024_CDIVR_RMSK 0x1ff +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV1024_CDIVR_ATTR 0x3 +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV1024_CDIVR_IN \ + in_dword_masked(HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV1024_CDIVR_ADDR, HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV1024_CDIVR_RMSK) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV1024_CDIVR_INM(m) \ + in_dword_masked(HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV1024_CDIVR_ADDR, m) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV1024_CDIVR_OUT(v) \ + out_dword(HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV1024_CDIVR_ADDR,v) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV1024_CDIVR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV1024_CDIVR_ADDR,m,v,HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV1024_CDIVR_IN) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV1024_CDIVR_CLK_DIV_BMSK 0x1ff +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV1024_CDIVR_CLK_DIV_SHFT 0x0 + +#define HWIO_GCC_APB2JTAG_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00022000) +#define HWIO_GCC_APB2JTAG_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00022000) +#define HWIO_GCC_APB2JTAG_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00022000) +#define HWIO_GCC_APB2JTAG_BCR_RMSK 0x1 +#define HWIO_GCC_APB2JTAG_BCR_ATTR 0x3 +#define HWIO_GCC_APB2JTAG_BCR_IN \ + in_dword_masked(HWIO_GCC_APB2JTAG_BCR_ADDR, HWIO_GCC_APB2JTAG_BCR_RMSK) +#define HWIO_GCC_APB2JTAG_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_APB2JTAG_BCR_ADDR, m) +#define HWIO_GCC_APB2JTAG_BCR_OUT(v) \ + out_dword(HWIO_GCC_APB2JTAG_BCR_ADDR,v) +#define HWIO_GCC_APB2JTAG_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_APB2JTAG_BCR_ADDR,m,v,HWIO_GCC_APB2JTAG_BCR_IN) +#define HWIO_GCC_APB2JTAG_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_APB2JTAG_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_APB2JTAG_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_APB2JTAG_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RBCPR_CX_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00023000) +#define HWIO_GCC_RBCPR_CX_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00023000) +#define HWIO_GCC_RBCPR_CX_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00023000) +#define HWIO_GCC_RBCPR_CX_BCR_RMSK 0x1 +#define HWIO_GCC_RBCPR_CX_BCR_ATTR 0x3 +#define HWIO_GCC_RBCPR_CX_BCR_IN \ + in_dword_masked(HWIO_GCC_RBCPR_CX_BCR_ADDR, HWIO_GCC_RBCPR_CX_BCR_RMSK) +#define HWIO_GCC_RBCPR_CX_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_RBCPR_CX_BCR_ADDR, m) +#define HWIO_GCC_RBCPR_CX_BCR_OUT(v) \ + out_dword(HWIO_GCC_RBCPR_CX_BCR_ADDR,v) +#define HWIO_GCC_RBCPR_CX_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RBCPR_CX_BCR_ADDR,m,v,HWIO_GCC_RBCPR_CX_BCR_IN) +#define HWIO_GCC_RBCPR_CX_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_RBCPR_CX_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_RBCPR_CX_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_RBCPR_CX_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RBCPR_CX_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00023004) +#define HWIO_GCC_RBCPR_CX_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00023004) +#define HWIO_GCC_RBCPR_CX_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00023004) +#define HWIO_GCC_RBCPR_CX_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_RBCPR_CX_CBCR_ATTR 0x3 +#define HWIO_GCC_RBCPR_CX_CBCR_IN \ + in_dword_masked(HWIO_GCC_RBCPR_CX_CBCR_ADDR, HWIO_GCC_RBCPR_CX_CBCR_RMSK) +#define HWIO_GCC_RBCPR_CX_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_RBCPR_CX_CBCR_ADDR, m) +#define HWIO_GCC_RBCPR_CX_CBCR_OUT(v) \ + out_dword(HWIO_GCC_RBCPR_CX_CBCR_ADDR,v) +#define HWIO_GCC_RBCPR_CX_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RBCPR_CX_CBCR_ADDR,m,v,HWIO_GCC_RBCPR_CX_CBCR_IN) +#define HWIO_GCC_RBCPR_CX_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_RBCPR_CX_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_RBCPR_CX_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_RBCPR_CX_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_RBCPR_CX_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_RBCPR_CX_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_RBCPR_CX_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_RBCPR_CX_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_RBCPR_CX_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_RBCPR_CX_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_RBCPR_CX_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_RBCPR_CX_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_RBCPR_CX_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_RBCPR_CX_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_RBCPR_CX_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_RBCPR_CX_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00023008) +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00023008) +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00023008) +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_RMSK 0x81d00005 +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_RBCPR_CX_AHB_CBCR_ADDR, HWIO_GCC_RBCPR_CX_AHB_CBCR_RMSK) +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_RBCPR_CX_AHB_CBCR_ADDR, m) +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_RBCPR_CX_AHB_CBCR_ADDR,v) +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RBCPR_CX_AHB_CBCR_ADDR,m,v,HWIO_GCC_RBCPR_CX_AHB_CBCR_IN) +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RBCPR_CX_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002300c) +#define HWIO_GCC_RBCPR_CX_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002300c) +#define HWIO_GCC_RBCPR_CX_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002300c) +#define HWIO_GCC_RBCPR_CX_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_RBCPR_CX_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_RBCPR_CX_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_RBCPR_CX_CMD_RCGR_ADDR, HWIO_GCC_RBCPR_CX_CMD_RCGR_RMSK) +#define HWIO_GCC_RBCPR_CX_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_RBCPR_CX_CMD_RCGR_ADDR, m) +#define HWIO_GCC_RBCPR_CX_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_RBCPR_CX_CMD_RCGR_ADDR,v) +#define HWIO_GCC_RBCPR_CX_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RBCPR_CX_CMD_RCGR_ADDR,m,v,HWIO_GCC_RBCPR_CX_CMD_RCGR_IN) +#define HWIO_GCC_RBCPR_CX_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_RBCPR_CX_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_RBCPR_CX_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_RBCPR_CX_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_RBCPR_CX_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_RBCPR_CX_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_RBCPR_CX_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_RBCPR_CX_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_RBCPR_CX_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_RBCPR_CX_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_RBCPR_CX_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_RBCPR_CX_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00023010) +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00023010) +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00023010) +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_RBCPR_CX_CFG_RCGR_ADDR, HWIO_GCC_RBCPR_CX_CFG_RCGR_RMSK) +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_RBCPR_CX_CFG_RCGR_ADDR, m) +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_RBCPR_CX_CFG_RCGR_ADDR,v) +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RBCPR_CX_CFG_RCGR_ADDR,m,v,HWIO_GCC_RBCPR_CX_CFG_RCGR_IN) +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RBCPR_MX_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00024000) +#define HWIO_GCC_RBCPR_MX_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00024000) +#define HWIO_GCC_RBCPR_MX_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00024000) +#define HWIO_GCC_RBCPR_MX_BCR_RMSK 0x1 +#define HWIO_GCC_RBCPR_MX_BCR_ATTR 0x3 +#define HWIO_GCC_RBCPR_MX_BCR_IN \ + in_dword_masked(HWIO_GCC_RBCPR_MX_BCR_ADDR, HWIO_GCC_RBCPR_MX_BCR_RMSK) +#define HWIO_GCC_RBCPR_MX_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_RBCPR_MX_BCR_ADDR, m) +#define HWIO_GCC_RBCPR_MX_BCR_OUT(v) \ + out_dword(HWIO_GCC_RBCPR_MX_BCR_ADDR,v) +#define HWIO_GCC_RBCPR_MX_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RBCPR_MX_BCR_ADDR,m,v,HWIO_GCC_RBCPR_MX_BCR_IN) +#define HWIO_GCC_RBCPR_MX_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_RBCPR_MX_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_RBCPR_MX_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_RBCPR_MX_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RBCPR_MX_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00024004) +#define HWIO_GCC_RBCPR_MX_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00024004) +#define HWIO_GCC_RBCPR_MX_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00024004) +#define HWIO_GCC_RBCPR_MX_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_RBCPR_MX_CBCR_ATTR 0x3 +#define HWIO_GCC_RBCPR_MX_CBCR_IN \ + in_dword_masked(HWIO_GCC_RBCPR_MX_CBCR_ADDR, HWIO_GCC_RBCPR_MX_CBCR_RMSK) +#define HWIO_GCC_RBCPR_MX_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_RBCPR_MX_CBCR_ADDR, m) +#define HWIO_GCC_RBCPR_MX_CBCR_OUT(v) \ + out_dword(HWIO_GCC_RBCPR_MX_CBCR_ADDR,v) +#define HWIO_GCC_RBCPR_MX_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RBCPR_MX_CBCR_ADDR,m,v,HWIO_GCC_RBCPR_MX_CBCR_IN) +#define HWIO_GCC_RBCPR_MX_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_RBCPR_MX_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_RBCPR_MX_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_RBCPR_MX_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_RBCPR_MX_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_RBCPR_MX_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_RBCPR_MX_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_RBCPR_MX_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_RBCPR_MX_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_RBCPR_MX_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_RBCPR_MX_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_RBCPR_MX_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_RBCPR_MX_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_RBCPR_MX_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_RBCPR_MX_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_RBCPR_MX_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RBCPR_MX_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00024008) +#define HWIO_GCC_RBCPR_MX_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00024008) +#define HWIO_GCC_RBCPR_MX_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00024008) +#define HWIO_GCC_RBCPR_MX_AHB_CBCR_RMSK 0x81d00005 +#define HWIO_GCC_RBCPR_MX_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_RBCPR_MX_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_RBCPR_MX_AHB_CBCR_ADDR, HWIO_GCC_RBCPR_MX_AHB_CBCR_RMSK) +#define HWIO_GCC_RBCPR_MX_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_RBCPR_MX_AHB_CBCR_ADDR, m) +#define HWIO_GCC_RBCPR_MX_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_RBCPR_MX_AHB_CBCR_ADDR,v) +#define HWIO_GCC_RBCPR_MX_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RBCPR_MX_AHB_CBCR_ADDR,m,v,HWIO_GCC_RBCPR_MX_AHB_CBCR_IN) +#define HWIO_GCC_RBCPR_MX_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_RBCPR_MX_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_RBCPR_MX_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_RBCPR_MX_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_RBCPR_MX_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_RBCPR_MX_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_RBCPR_MX_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_RBCPR_MX_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_RBCPR_MX_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_RBCPR_MX_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_RBCPR_MX_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_RBCPR_MX_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_RBCPR_MX_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_RBCPR_MX_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_RBCPR_MX_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_RBCPR_MX_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_RBCPR_MX_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_RBCPR_MX_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RBCPR_MX_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002400c) +#define HWIO_GCC_RBCPR_MX_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002400c) +#define HWIO_GCC_RBCPR_MX_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002400c) +#define HWIO_GCC_RBCPR_MX_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_RBCPR_MX_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_RBCPR_MX_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_RBCPR_MX_CMD_RCGR_ADDR, HWIO_GCC_RBCPR_MX_CMD_RCGR_RMSK) +#define HWIO_GCC_RBCPR_MX_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_RBCPR_MX_CMD_RCGR_ADDR, m) +#define HWIO_GCC_RBCPR_MX_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_RBCPR_MX_CMD_RCGR_ADDR,v) +#define HWIO_GCC_RBCPR_MX_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RBCPR_MX_CMD_RCGR_ADDR,m,v,HWIO_GCC_RBCPR_MX_CMD_RCGR_IN) +#define HWIO_GCC_RBCPR_MX_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_RBCPR_MX_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_RBCPR_MX_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_RBCPR_MX_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_RBCPR_MX_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_RBCPR_MX_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_RBCPR_MX_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_RBCPR_MX_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_RBCPR_MX_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_RBCPR_MX_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_RBCPR_MX_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_RBCPR_MX_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00024010) +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00024010) +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00024010) +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_RBCPR_MX_CFG_RCGR_ADDR, HWIO_GCC_RBCPR_MX_CFG_RCGR_RMSK) +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_RBCPR_MX_CFG_RCGR_ADDR, m) +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_RBCPR_MX_CFG_RCGR_ADDR,v) +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RBCPR_MX_CFG_RCGR_ADDR,m,v,HWIO_GCC_RBCPR_MX_CFG_RCGR_IN) +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RBCPR_MXC_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00046000) +#define HWIO_GCC_RBCPR_MXC_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00046000) +#define HWIO_GCC_RBCPR_MXC_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00046000) +#define HWIO_GCC_RBCPR_MXC_BCR_RMSK 0x1 +#define HWIO_GCC_RBCPR_MXC_BCR_ATTR 0x3 +#define HWIO_GCC_RBCPR_MXC_BCR_IN \ + in_dword_masked(HWIO_GCC_RBCPR_MXC_BCR_ADDR, HWIO_GCC_RBCPR_MXC_BCR_RMSK) +#define HWIO_GCC_RBCPR_MXC_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_RBCPR_MXC_BCR_ADDR, m) +#define HWIO_GCC_RBCPR_MXC_BCR_OUT(v) \ + out_dword(HWIO_GCC_RBCPR_MXC_BCR_ADDR,v) +#define HWIO_GCC_RBCPR_MXC_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RBCPR_MXC_BCR_ADDR,m,v,HWIO_GCC_RBCPR_MXC_BCR_IN) +#define HWIO_GCC_RBCPR_MXC_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_RBCPR_MXC_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_RBCPR_MXC_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_RBCPR_MXC_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RBCPR_MXC_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00046004) +#define HWIO_GCC_RBCPR_MXC_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00046004) +#define HWIO_GCC_RBCPR_MXC_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00046004) +#define HWIO_GCC_RBCPR_MXC_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_RBCPR_MXC_CBCR_ATTR 0x3 +#define HWIO_GCC_RBCPR_MXC_CBCR_IN \ + in_dword_masked(HWIO_GCC_RBCPR_MXC_CBCR_ADDR, HWIO_GCC_RBCPR_MXC_CBCR_RMSK) +#define HWIO_GCC_RBCPR_MXC_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_RBCPR_MXC_CBCR_ADDR, m) +#define HWIO_GCC_RBCPR_MXC_CBCR_OUT(v) \ + out_dword(HWIO_GCC_RBCPR_MXC_CBCR_ADDR,v) +#define HWIO_GCC_RBCPR_MXC_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RBCPR_MXC_CBCR_ADDR,m,v,HWIO_GCC_RBCPR_MXC_CBCR_IN) +#define HWIO_GCC_RBCPR_MXC_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_RBCPR_MXC_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_RBCPR_MXC_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_RBCPR_MXC_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_RBCPR_MXC_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_RBCPR_MXC_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_RBCPR_MXC_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_RBCPR_MXC_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_RBCPR_MXC_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_RBCPR_MXC_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_RBCPR_MXC_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_RBCPR_MXC_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_RBCPR_MXC_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_RBCPR_MXC_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_RBCPR_MXC_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_RBCPR_MXC_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RBCPR_MXC_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00046008) +#define HWIO_GCC_RBCPR_MXC_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00046008) +#define HWIO_GCC_RBCPR_MXC_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00046008) +#define HWIO_GCC_RBCPR_MXC_AHB_CBCR_RMSK 0x81d00005 +#define HWIO_GCC_RBCPR_MXC_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_RBCPR_MXC_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_RBCPR_MXC_AHB_CBCR_ADDR, HWIO_GCC_RBCPR_MXC_AHB_CBCR_RMSK) +#define HWIO_GCC_RBCPR_MXC_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_RBCPR_MXC_AHB_CBCR_ADDR, m) +#define HWIO_GCC_RBCPR_MXC_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_RBCPR_MXC_AHB_CBCR_ADDR,v) +#define HWIO_GCC_RBCPR_MXC_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RBCPR_MXC_AHB_CBCR_ADDR,m,v,HWIO_GCC_RBCPR_MXC_AHB_CBCR_IN) +#define HWIO_GCC_RBCPR_MXC_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_RBCPR_MXC_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_RBCPR_MXC_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_RBCPR_MXC_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_RBCPR_MXC_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_RBCPR_MXC_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_RBCPR_MXC_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_RBCPR_MXC_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_RBCPR_MXC_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_RBCPR_MXC_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_RBCPR_MXC_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_RBCPR_MXC_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_RBCPR_MXC_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_RBCPR_MXC_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_RBCPR_MXC_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_RBCPR_MXC_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_RBCPR_MXC_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_RBCPR_MXC_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RBCPR_MXC_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004600c) +#define HWIO_GCC_RBCPR_MXC_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004600c) +#define HWIO_GCC_RBCPR_MXC_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004600c) +#define HWIO_GCC_RBCPR_MXC_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_RBCPR_MXC_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_RBCPR_MXC_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_RBCPR_MXC_CMD_RCGR_ADDR, HWIO_GCC_RBCPR_MXC_CMD_RCGR_RMSK) +#define HWIO_GCC_RBCPR_MXC_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_RBCPR_MXC_CMD_RCGR_ADDR, m) +#define HWIO_GCC_RBCPR_MXC_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_RBCPR_MXC_CMD_RCGR_ADDR,v) +#define HWIO_GCC_RBCPR_MXC_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RBCPR_MXC_CMD_RCGR_ADDR,m,v,HWIO_GCC_RBCPR_MXC_CMD_RCGR_IN) +#define HWIO_GCC_RBCPR_MXC_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_RBCPR_MXC_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_RBCPR_MXC_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_RBCPR_MXC_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_RBCPR_MXC_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_RBCPR_MXC_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_RBCPR_MXC_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_RBCPR_MXC_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_RBCPR_MXC_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_RBCPR_MXC_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_RBCPR_MXC_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_RBCPR_MXC_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00046010) +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00046010) +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00046010) +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_RBCPR_MXC_CFG_RCGR_ADDR, HWIO_GCC_RBCPR_MXC_CFG_RCGR_RMSK) +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_RBCPR_MXC_CFG_RCGR_ADDR, m) +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_RBCPR_MXC_CFG_RCGR_ADDR,v) +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RBCPR_MXC_CFG_RCGR_ADDR,m,v,HWIO_GCC_RBCPR_MXC_CFG_RCGR_IN) +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_DEBUG_DIV_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00025000) +#define HWIO_GCC_DEBUG_DIV_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00025000) +#define HWIO_GCC_DEBUG_DIV_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00025000) +#define HWIO_GCC_DEBUG_DIV_CDIVR_RMSK 0xf +#define HWIO_GCC_DEBUG_DIV_CDIVR_ATTR 0x3 +#define HWIO_GCC_DEBUG_DIV_CDIVR_IN \ + in_dword_masked(HWIO_GCC_DEBUG_DIV_CDIVR_ADDR, HWIO_GCC_DEBUG_DIV_CDIVR_RMSK) +#define HWIO_GCC_DEBUG_DIV_CDIVR_INM(m) \ + in_dword_masked(HWIO_GCC_DEBUG_DIV_CDIVR_ADDR, m) +#define HWIO_GCC_DEBUG_DIV_CDIVR_OUT(v) \ + out_dword(HWIO_GCC_DEBUG_DIV_CDIVR_ADDR,v) +#define HWIO_GCC_DEBUG_DIV_CDIVR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DEBUG_DIV_CDIVR_ADDR,m,v,HWIO_GCC_DEBUG_DIV_CDIVR_IN) +#define HWIO_GCC_DEBUG_DIV_CDIVR_CLK_DIV_BMSK 0xf +#define HWIO_GCC_DEBUG_DIV_CDIVR_CLK_DIV_SHFT 0x0 + +#define HWIO_GCC_DEBUG_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00025004) +#define HWIO_GCC_DEBUG_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00025004) +#define HWIO_GCC_DEBUG_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00025004) +#define HWIO_GCC_DEBUG_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_DEBUG_CBCR_ATTR 0x3 +#define HWIO_GCC_DEBUG_CBCR_IN \ + in_dword_masked(HWIO_GCC_DEBUG_CBCR_ADDR, HWIO_GCC_DEBUG_CBCR_RMSK) +#define HWIO_GCC_DEBUG_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_DEBUG_CBCR_ADDR, m) +#define HWIO_GCC_DEBUG_CBCR_OUT(v) \ + out_dword(HWIO_GCC_DEBUG_CBCR_ADDR,v) +#define HWIO_GCC_DEBUG_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DEBUG_CBCR_ADDR,m,v,HWIO_GCC_DEBUG_CBCR_IN) +#define HWIO_GCC_DEBUG_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_DEBUG_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_DEBUG_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_DEBUG_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_DEBUG_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_DEBUG_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_DEBUG_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_DEBUG_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_DEBUG_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_DEBUG_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_DEBUG_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_DEBUG_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_DEBUG_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_DEBUG_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_DEBUG_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DEBUG_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GP1_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00027000) +#define HWIO_GCC_GP1_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00027000) +#define HWIO_GCC_GP1_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00027000) +#define HWIO_GCC_GP1_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_GP1_CBCR_ATTR 0x3 +#define HWIO_GCC_GP1_CBCR_IN \ + in_dword_masked(HWIO_GCC_GP1_CBCR_ADDR, HWIO_GCC_GP1_CBCR_RMSK) +#define HWIO_GCC_GP1_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_GP1_CBCR_ADDR, m) +#define HWIO_GCC_GP1_CBCR_OUT(v) \ + out_dword(HWIO_GCC_GP1_CBCR_ADDR,v) +#define HWIO_GCC_GP1_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GP1_CBCR_ADDR,m,v,HWIO_GCC_GP1_CBCR_IN) +#define HWIO_GCC_GP1_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_GP1_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_GP1_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_GP1_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_GP1_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_GP1_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_GP1_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_GP1_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_GP1_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_GP1_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_GP1_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_GP1_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_GP1_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GP1_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_GP1_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GP1_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GP1_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00027004) +#define HWIO_GCC_GP1_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00027004) +#define HWIO_GCC_GP1_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00027004) +#define HWIO_GCC_GP1_CMD_RCGR_RMSK 0x800000f3 +#define HWIO_GCC_GP1_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_GP1_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_GP1_CMD_RCGR_ADDR, HWIO_GCC_GP1_CMD_RCGR_RMSK) +#define HWIO_GCC_GP1_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_GP1_CMD_RCGR_ADDR, m) +#define HWIO_GCC_GP1_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_GP1_CMD_RCGR_ADDR,v) +#define HWIO_GCC_GP1_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GP1_CMD_RCGR_ADDR,m,v,HWIO_GCC_GP1_CMD_RCGR_IN) +#define HWIO_GCC_GP1_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_GP1_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_GP1_CMD_RCGR_DIRTY_D_BMSK 0x80 +#define HWIO_GCC_GP1_CMD_RCGR_DIRTY_D_SHFT 0x7 +#define HWIO_GCC_GP1_CMD_RCGR_DIRTY_N_BMSK 0x40 +#define HWIO_GCC_GP1_CMD_RCGR_DIRTY_N_SHFT 0x6 +#define HWIO_GCC_GP1_CMD_RCGR_DIRTY_M_BMSK 0x20 +#define HWIO_GCC_GP1_CMD_RCGR_DIRTY_M_SHFT 0x5 +#define HWIO_GCC_GP1_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_GP1_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_GP1_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_GP1_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_GP1_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_GP1_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_GP1_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_GP1_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_GP1_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GP1_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GP1_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00027008) +#define HWIO_GCC_GP1_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00027008) +#define HWIO_GCC_GP1_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00027008) +#define HWIO_GCC_GP1_CFG_RCGR_RMSK 0x10371f +#define HWIO_GCC_GP1_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_GP1_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_GP1_CFG_RCGR_ADDR, HWIO_GCC_GP1_CFG_RCGR_RMSK) +#define HWIO_GCC_GP1_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_GP1_CFG_RCGR_ADDR, m) +#define HWIO_GCC_GP1_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_GP1_CFG_RCGR_ADDR,v) +#define HWIO_GCC_GP1_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GP1_CFG_RCGR_ADDR,m,v,HWIO_GCC_GP1_CFG_RCGR_IN) +#define HWIO_GCC_GP1_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_GP1_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_GP1_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_GP1_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_GP1_CFG_RCGR_MODE_BMSK 0x3000 +#define HWIO_GCC_GP1_CFG_RCGR_MODE_SHFT 0xc +#define HWIO_GCC_GP1_CFG_RCGR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_GP1_CFG_RCGR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_GP1_CFG_RCGR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_GP1_CFG_RCGR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_GP1_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002700c) +#define HWIO_GCC_GP1_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002700c) +#define HWIO_GCC_GP1_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002700c) +#define HWIO_GCC_GP1_M_RMSK 0xffff +#define HWIO_GCC_GP1_M_ATTR 0x3 +#define HWIO_GCC_GP1_M_IN \ + in_dword_masked(HWIO_GCC_GP1_M_ADDR, HWIO_GCC_GP1_M_RMSK) +#define HWIO_GCC_GP1_M_INM(m) \ + in_dword_masked(HWIO_GCC_GP1_M_ADDR, m) +#define HWIO_GCC_GP1_M_OUT(v) \ + out_dword(HWIO_GCC_GP1_M_ADDR,v) +#define HWIO_GCC_GP1_M_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GP1_M_ADDR,m,v,HWIO_GCC_GP1_M_IN) +#define HWIO_GCC_GP1_M_M_BMSK 0xffff +#define HWIO_GCC_GP1_M_M_SHFT 0x0 + +#define HWIO_GCC_GP1_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00027010) +#define HWIO_GCC_GP1_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00027010) +#define HWIO_GCC_GP1_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00027010) +#define HWIO_GCC_GP1_N_RMSK 0xffff +#define HWIO_GCC_GP1_N_ATTR 0x3 +#define HWIO_GCC_GP1_N_IN \ + in_dword_masked(HWIO_GCC_GP1_N_ADDR, HWIO_GCC_GP1_N_RMSK) +#define HWIO_GCC_GP1_N_INM(m) \ + in_dword_masked(HWIO_GCC_GP1_N_ADDR, m) +#define HWIO_GCC_GP1_N_OUT(v) \ + out_dword(HWIO_GCC_GP1_N_ADDR,v) +#define HWIO_GCC_GP1_N_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GP1_N_ADDR,m,v,HWIO_GCC_GP1_N_IN) +#define HWIO_GCC_GP1_N_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_GP1_N_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_GP1_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00027014) +#define HWIO_GCC_GP1_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00027014) +#define HWIO_GCC_GP1_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00027014) +#define HWIO_GCC_GP1_D_RMSK 0xffff +#define HWIO_GCC_GP1_D_ATTR 0x3 +#define HWIO_GCC_GP1_D_IN \ + in_dword_masked(HWIO_GCC_GP1_D_ADDR, HWIO_GCC_GP1_D_RMSK) +#define HWIO_GCC_GP1_D_INM(m) \ + in_dword_masked(HWIO_GCC_GP1_D_ADDR, m) +#define HWIO_GCC_GP1_D_OUT(v) \ + out_dword(HWIO_GCC_GP1_D_ADDR,v) +#define HWIO_GCC_GP1_D_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GP1_D_ADDR,m,v,HWIO_GCC_GP1_D_IN) +#define HWIO_GCC_GP1_D_NOT_2D_BMSK 0xffff +#define HWIO_GCC_GP1_D_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_GP2_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00028000) +#define HWIO_GCC_GP2_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00028000) +#define HWIO_GCC_GP2_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00028000) +#define HWIO_GCC_GP2_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_GP2_CBCR_ATTR 0x3 +#define HWIO_GCC_GP2_CBCR_IN \ + in_dword_masked(HWIO_GCC_GP2_CBCR_ADDR, HWIO_GCC_GP2_CBCR_RMSK) +#define HWIO_GCC_GP2_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_GP2_CBCR_ADDR, m) +#define HWIO_GCC_GP2_CBCR_OUT(v) \ + out_dword(HWIO_GCC_GP2_CBCR_ADDR,v) +#define HWIO_GCC_GP2_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GP2_CBCR_ADDR,m,v,HWIO_GCC_GP2_CBCR_IN) +#define HWIO_GCC_GP2_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_GP2_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_GP2_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_GP2_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_GP2_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_GP2_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_GP2_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_GP2_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_GP2_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_GP2_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_GP2_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_GP2_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_GP2_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GP2_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_GP2_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GP2_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GP2_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00028004) +#define HWIO_GCC_GP2_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00028004) +#define HWIO_GCC_GP2_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00028004) +#define HWIO_GCC_GP2_CMD_RCGR_RMSK 0x800000f3 +#define HWIO_GCC_GP2_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_GP2_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_GP2_CMD_RCGR_ADDR, HWIO_GCC_GP2_CMD_RCGR_RMSK) +#define HWIO_GCC_GP2_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_GP2_CMD_RCGR_ADDR, m) +#define HWIO_GCC_GP2_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_GP2_CMD_RCGR_ADDR,v) +#define HWIO_GCC_GP2_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GP2_CMD_RCGR_ADDR,m,v,HWIO_GCC_GP2_CMD_RCGR_IN) +#define HWIO_GCC_GP2_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_GP2_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_GP2_CMD_RCGR_DIRTY_D_BMSK 0x80 +#define HWIO_GCC_GP2_CMD_RCGR_DIRTY_D_SHFT 0x7 +#define HWIO_GCC_GP2_CMD_RCGR_DIRTY_N_BMSK 0x40 +#define HWIO_GCC_GP2_CMD_RCGR_DIRTY_N_SHFT 0x6 +#define HWIO_GCC_GP2_CMD_RCGR_DIRTY_M_BMSK 0x20 +#define HWIO_GCC_GP2_CMD_RCGR_DIRTY_M_SHFT 0x5 +#define HWIO_GCC_GP2_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_GP2_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_GP2_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_GP2_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_GP2_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_GP2_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_GP2_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_GP2_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_GP2_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GP2_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GP2_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00028008) +#define HWIO_GCC_GP2_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00028008) +#define HWIO_GCC_GP2_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00028008) +#define HWIO_GCC_GP2_CFG_RCGR_RMSK 0x10371f +#define HWIO_GCC_GP2_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_GP2_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_GP2_CFG_RCGR_ADDR, HWIO_GCC_GP2_CFG_RCGR_RMSK) +#define HWIO_GCC_GP2_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_GP2_CFG_RCGR_ADDR, m) +#define HWIO_GCC_GP2_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_GP2_CFG_RCGR_ADDR,v) +#define HWIO_GCC_GP2_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GP2_CFG_RCGR_ADDR,m,v,HWIO_GCC_GP2_CFG_RCGR_IN) +#define HWIO_GCC_GP2_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_GP2_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_GP2_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_GP2_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_GP2_CFG_RCGR_MODE_BMSK 0x3000 +#define HWIO_GCC_GP2_CFG_RCGR_MODE_SHFT 0xc +#define HWIO_GCC_GP2_CFG_RCGR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_GP2_CFG_RCGR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_GP2_CFG_RCGR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_GP2_CFG_RCGR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_GP2_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002800c) +#define HWIO_GCC_GP2_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002800c) +#define HWIO_GCC_GP2_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002800c) +#define HWIO_GCC_GP2_M_RMSK 0xffff +#define HWIO_GCC_GP2_M_ATTR 0x3 +#define HWIO_GCC_GP2_M_IN \ + in_dword_masked(HWIO_GCC_GP2_M_ADDR, HWIO_GCC_GP2_M_RMSK) +#define HWIO_GCC_GP2_M_INM(m) \ + in_dword_masked(HWIO_GCC_GP2_M_ADDR, m) +#define HWIO_GCC_GP2_M_OUT(v) \ + out_dword(HWIO_GCC_GP2_M_ADDR,v) +#define HWIO_GCC_GP2_M_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GP2_M_ADDR,m,v,HWIO_GCC_GP2_M_IN) +#define HWIO_GCC_GP2_M_M_BMSK 0xffff +#define HWIO_GCC_GP2_M_M_SHFT 0x0 + +#define HWIO_GCC_GP2_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00028010) +#define HWIO_GCC_GP2_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00028010) +#define HWIO_GCC_GP2_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00028010) +#define HWIO_GCC_GP2_N_RMSK 0xffff +#define HWIO_GCC_GP2_N_ATTR 0x3 +#define HWIO_GCC_GP2_N_IN \ + in_dword_masked(HWIO_GCC_GP2_N_ADDR, HWIO_GCC_GP2_N_RMSK) +#define HWIO_GCC_GP2_N_INM(m) \ + in_dword_masked(HWIO_GCC_GP2_N_ADDR, m) +#define HWIO_GCC_GP2_N_OUT(v) \ + out_dword(HWIO_GCC_GP2_N_ADDR,v) +#define HWIO_GCC_GP2_N_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GP2_N_ADDR,m,v,HWIO_GCC_GP2_N_IN) +#define HWIO_GCC_GP2_N_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_GP2_N_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_GP2_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00028014) +#define HWIO_GCC_GP2_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00028014) +#define HWIO_GCC_GP2_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00028014) +#define HWIO_GCC_GP2_D_RMSK 0xffff +#define HWIO_GCC_GP2_D_ATTR 0x3 +#define HWIO_GCC_GP2_D_IN \ + in_dword_masked(HWIO_GCC_GP2_D_ADDR, HWIO_GCC_GP2_D_RMSK) +#define HWIO_GCC_GP2_D_INM(m) \ + in_dword_masked(HWIO_GCC_GP2_D_ADDR, m) +#define HWIO_GCC_GP2_D_OUT(v) \ + out_dword(HWIO_GCC_GP2_D_ADDR,v) +#define HWIO_GCC_GP2_D_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GP2_D_ADDR,m,v,HWIO_GCC_GP2_D_IN) +#define HWIO_GCC_GP2_D_NOT_2D_BMSK 0xffff +#define HWIO_GCC_GP2_D_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_GP3_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00029000) +#define HWIO_GCC_GP3_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00029000) +#define HWIO_GCC_GP3_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00029000) +#define HWIO_GCC_GP3_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_GP3_CBCR_ATTR 0x3 +#define HWIO_GCC_GP3_CBCR_IN \ + in_dword_masked(HWIO_GCC_GP3_CBCR_ADDR, HWIO_GCC_GP3_CBCR_RMSK) +#define HWIO_GCC_GP3_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_GP3_CBCR_ADDR, m) +#define HWIO_GCC_GP3_CBCR_OUT(v) \ + out_dword(HWIO_GCC_GP3_CBCR_ADDR,v) +#define HWIO_GCC_GP3_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GP3_CBCR_ADDR,m,v,HWIO_GCC_GP3_CBCR_IN) +#define HWIO_GCC_GP3_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_GP3_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_GP3_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_GP3_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_GP3_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_GP3_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_GP3_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_GP3_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_GP3_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_GP3_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_GP3_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_GP3_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_GP3_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GP3_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_GP3_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GP3_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GP3_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00029004) +#define HWIO_GCC_GP3_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00029004) +#define HWIO_GCC_GP3_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00029004) +#define HWIO_GCC_GP3_CMD_RCGR_RMSK 0x800000f3 +#define HWIO_GCC_GP3_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_GP3_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_GP3_CMD_RCGR_ADDR, HWIO_GCC_GP3_CMD_RCGR_RMSK) +#define HWIO_GCC_GP3_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_GP3_CMD_RCGR_ADDR, m) +#define HWIO_GCC_GP3_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_GP3_CMD_RCGR_ADDR,v) +#define HWIO_GCC_GP3_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GP3_CMD_RCGR_ADDR,m,v,HWIO_GCC_GP3_CMD_RCGR_IN) +#define HWIO_GCC_GP3_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_GP3_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_GP3_CMD_RCGR_DIRTY_D_BMSK 0x80 +#define HWIO_GCC_GP3_CMD_RCGR_DIRTY_D_SHFT 0x7 +#define HWIO_GCC_GP3_CMD_RCGR_DIRTY_N_BMSK 0x40 +#define HWIO_GCC_GP3_CMD_RCGR_DIRTY_N_SHFT 0x6 +#define HWIO_GCC_GP3_CMD_RCGR_DIRTY_M_BMSK 0x20 +#define HWIO_GCC_GP3_CMD_RCGR_DIRTY_M_SHFT 0x5 +#define HWIO_GCC_GP3_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_GP3_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_GP3_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_GP3_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_GP3_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_GP3_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_GP3_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_GP3_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_GP3_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GP3_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GP3_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00029008) +#define HWIO_GCC_GP3_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00029008) +#define HWIO_GCC_GP3_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00029008) +#define HWIO_GCC_GP3_CFG_RCGR_RMSK 0x10371f +#define HWIO_GCC_GP3_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_GP3_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_GP3_CFG_RCGR_ADDR, HWIO_GCC_GP3_CFG_RCGR_RMSK) +#define HWIO_GCC_GP3_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_GP3_CFG_RCGR_ADDR, m) +#define HWIO_GCC_GP3_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_GP3_CFG_RCGR_ADDR,v) +#define HWIO_GCC_GP3_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GP3_CFG_RCGR_ADDR,m,v,HWIO_GCC_GP3_CFG_RCGR_IN) +#define HWIO_GCC_GP3_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_GP3_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_GP3_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_GP3_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_GP3_CFG_RCGR_MODE_BMSK 0x3000 +#define HWIO_GCC_GP3_CFG_RCGR_MODE_SHFT 0xc +#define HWIO_GCC_GP3_CFG_RCGR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_GP3_CFG_RCGR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_GP3_CFG_RCGR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_GP3_CFG_RCGR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_GP3_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002900c) +#define HWIO_GCC_GP3_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002900c) +#define HWIO_GCC_GP3_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002900c) +#define HWIO_GCC_GP3_M_RMSK 0xffff +#define HWIO_GCC_GP3_M_ATTR 0x3 +#define HWIO_GCC_GP3_M_IN \ + in_dword_masked(HWIO_GCC_GP3_M_ADDR, HWIO_GCC_GP3_M_RMSK) +#define HWIO_GCC_GP3_M_INM(m) \ + in_dword_masked(HWIO_GCC_GP3_M_ADDR, m) +#define HWIO_GCC_GP3_M_OUT(v) \ + out_dword(HWIO_GCC_GP3_M_ADDR,v) +#define HWIO_GCC_GP3_M_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GP3_M_ADDR,m,v,HWIO_GCC_GP3_M_IN) +#define HWIO_GCC_GP3_M_M_BMSK 0xffff +#define HWIO_GCC_GP3_M_M_SHFT 0x0 + +#define HWIO_GCC_GP3_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00029010) +#define HWIO_GCC_GP3_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00029010) +#define HWIO_GCC_GP3_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00029010) +#define HWIO_GCC_GP3_N_RMSK 0xffff +#define HWIO_GCC_GP3_N_ATTR 0x3 +#define HWIO_GCC_GP3_N_IN \ + in_dword_masked(HWIO_GCC_GP3_N_ADDR, HWIO_GCC_GP3_N_RMSK) +#define HWIO_GCC_GP3_N_INM(m) \ + in_dword_masked(HWIO_GCC_GP3_N_ADDR, m) +#define HWIO_GCC_GP3_N_OUT(v) \ + out_dword(HWIO_GCC_GP3_N_ADDR,v) +#define HWIO_GCC_GP3_N_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GP3_N_ADDR,m,v,HWIO_GCC_GP3_N_IN) +#define HWIO_GCC_GP3_N_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_GP3_N_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_GP3_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00029014) +#define HWIO_GCC_GP3_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00029014) +#define HWIO_GCC_GP3_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00029014) +#define HWIO_GCC_GP3_D_RMSK 0xffff +#define HWIO_GCC_GP3_D_ATTR 0x3 +#define HWIO_GCC_GP3_D_IN \ + in_dword_masked(HWIO_GCC_GP3_D_ADDR, HWIO_GCC_GP3_D_RMSK) +#define HWIO_GCC_GP3_D_INM(m) \ + in_dword_masked(HWIO_GCC_GP3_D_ADDR, m) +#define HWIO_GCC_GP3_D_OUT(v) \ + out_dword(HWIO_GCC_GP3_D_ADDR,v) +#define HWIO_GCC_GP3_D_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GP3_D_ADDR,m,v,HWIO_GCC_GP3_D_IN) +#define HWIO_GCC_GP3_D_NOT_2D_BMSK 0xffff +#define HWIO_GCC_GP3_D_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_AUDIO_CORE_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002a000) +#define HWIO_GCC_AUDIO_CORE_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002a000) +#define HWIO_GCC_AUDIO_CORE_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002a000) +#define HWIO_GCC_AUDIO_CORE_BCR_RMSK 0x1 +#define HWIO_GCC_AUDIO_CORE_BCR_ATTR 0x3 +#define HWIO_GCC_AUDIO_CORE_BCR_IN \ + in_dword_masked(HWIO_GCC_AUDIO_CORE_BCR_ADDR, HWIO_GCC_AUDIO_CORE_BCR_RMSK) +#define HWIO_GCC_AUDIO_CORE_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_AUDIO_CORE_BCR_ADDR, m) +#define HWIO_GCC_AUDIO_CORE_BCR_OUT(v) \ + out_dword(HWIO_GCC_AUDIO_CORE_BCR_ADDR,v) +#define HWIO_GCC_AUDIO_CORE_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AUDIO_CORE_BCR_ADDR,m,v,HWIO_GCC_AUDIO_CORE_BCR_IN) +#define HWIO_GCC_AUDIO_CORE_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_AUDIO_CORE_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_AUDIO_CORE_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_AUDIO_CORE_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_ULTAUDIO_PCNOC_MPORT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002a004) +#define HWIO_GCC_ULTAUDIO_PCNOC_MPORT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002a004) +#define HWIO_GCC_ULTAUDIO_PCNOC_MPORT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002a004) +#define HWIO_GCC_ULTAUDIO_PCNOC_MPORT_CBCR_RMSK 0x81d00005 +#define HWIO_GCC_ULTAUDIO_PCNOC_MPORT_CBCR_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_PCNOC_MPORT_CBCR_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_PCNOC_MPORT_CBCR_ADDR, HWIO_GCC_ULTAUDIO_PCNOC_MPORT_CBCR_RMSK) +#define HWIO_GCC_ULTAUDIO_PCNOC_MPORT_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_PCNOC_MPORT_CBCR_ADDR, m) +#define HWIO_GCC_ULTAUDIO_PCNOC_MPORT_CBCR_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_PCNOC_MPORT_CBCR_ADDR,v) +#define HWIO_GCC_ULTAUDIO_PCNOC_MPORT_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_PCNOC_MPORT_CBCR_ADDR,m,v,HWIO_GCC_ULTAUDIO_PCNOC_MPORT_CBCR_IN) +#define HWIO_GCC_ULTAUDIO_PCNOC_MPORT_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_ULTAUDIO_PCNOC_MPORT_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_ULTAUDIO_PCNOC_MPORT_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_ULTAUDIO_PCNOC_MPORT_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_ULTAUDIO_PCNOC_MPORT_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_ULTAUDIO_PCNOC_MPORT_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_ULTAUDIO_PCNOC_MPORT_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_ULTAUDIO_PCNOC_MPORT_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_ULTAUDIO_PCNOC_MPORT_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_ULTAUDIO_PCNOC_MPORT_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_ULTAUDIO_PCNOC_MPORT_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_ULTAUDIO_PCNOC_MPORT_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_ULTAUDIO_PCNOC_MPORT_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_PCNOC_MPORT_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_PCNOC_MPORT_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_ULTAUDIO_PCNOC_MPORT_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_ULTAUDIO_PCNOC_MPORT_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_PCNOC_MPORT_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_ULTAUDIO_PCNOC_SWAY_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002a008) +#define HWIO_GCC_ULTAUDIO_PCNOC_SWAY_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002a008) +#define HWIO_GCC_ULTAUDIO_PCNOC_SWAY_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002a008) +#define HWIO_GCC_ULTAUDIO_PCNOC_SWAY_CBCR_RMSK 0x81d0000e +#define HWIO_GCC_ULTAUDIO_PCNOC_SWAY_CBCR_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_PCNOC_SWAY_CBCR_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_PCNOC_SWAY_CBCR_ADDR, HWIO_GCC_ULTAUDIO_PCNOC_SWAY_CBCR_RMSK) +#define HWIO_GCC_ULTAUDIO_PCNOC_SWAY_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_PCNOC_SWAY_CBCR_ADDR, m) +#define HWIO_GCC_ULTAUDIO_PCNOC_SWAY_CBCR_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_PCNOC_SWAY_CBCR_ADDR,v) +#define HWIO_GCC_ULTAUDIO_PCNOC_SWAY_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_PCNOC_SWAY_CBCR_ADDR,m,v,HWIO_GCC_ULTAUDIO_PCNOC_SWAY_CBCR_IN) +#define HWIO_GCC_ULTAUDIO_PCNOC_SWAY_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_ULTAUDIO_PCNOC_SWAY_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_ULTAUDIO_PCNOC_SWAY_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_ULTAUDIO_PCNOC_SWAY_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_ULTAUDIO_PCNOC_SWAY_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_ULTAUDIO_PCNOC_SWAY_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_ULTAUDIO_PCNOC_SWAY_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_ULTAUDIO_PCNOC_SWAY_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_ULTAUDIO_PCNOC_SWAY_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_ULTAUDIO_PCNOC_SWAY_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_ULTAUDIO_PCNOC_SWAY_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_ULTAUDIO_PCNOC_SWAY_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_ULTAUDIO_PCNOC_SWAY_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_ULTAUDIO_PCNOC_SWAY_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_ULTAUDIO_PCNOC_SWAY_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_PCNOC_SWAY_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_PCNOC_SWAY_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_ULTAUDIO_PCNOC_SWAY_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_ULTAUDIO_PCNOC_SWAY_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_PCNOC_SWAY_CBCR_HW_CTL_ENABLE_FVAL 0x1 + +#define HWIO_GCC_AUDIO_AHB_BUS_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002b000) +#define HWIO_GCC_AUDIO_AHB_BUS_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002b000) +#define HWIO_GCC_AUDIO_AHB_BUS_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002b000) +#define HWIO_GCC_AUDIO_AHB_BUS_BCR_RMSK 0x1 +#define HWIO_GCC_AUDIO_AHB_BUS_BCR_ATTR 0x3 +#define HWIO_GCC_AUDIO_AHB_BUS_BCR_IN \ + in_dword_masked(HWIO_GCC_AUDIO_AHB_BUS_BCR_ADDR, HWIO_GCC_AUDIO_AHB_BUS_BCR_RMSK) +#define HWIO_GCC_AUDIO_AHB_BUS_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_AUDIO_AHB_BUS_BCR_ADDR, m) +#define HWIO_GCC_AUDIO_AHB_BUS_BCR_OUT(v) \ + out_dword(HWIO_GCC_AUDIO_AHB_BUS_BCR_ADDR,v) +#define HWIO_GCC_AUDIO_AHB_BUS_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AUDIO_AHB_BUS_BCR_ADDR,m,v,HWIO_GCC_AUDIO_AHB_BUS_BCR_IN) +#define HWIO_GCC_AUDIO_AHB_BUS_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_AUDIO_AHB_BUS_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_AUDIO_AHB_BUS_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_AUDIO_AHB_BUS_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002b004) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002b004) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002b004) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CBCR_RMSK 0x81c00004 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CBCR_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CBCR_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CBCR_ADDR, HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CBCR_RMSK) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CBCR_ADDR, m) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CBCR_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CBCR_ADDR,v) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CBCR_ADDR,m,v,HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CBCR_IN) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CBCR_CLK_ARES_RESET_FVAL 0x1 + +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002b008) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002b008) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002b008) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_RMSK 0x81c07ff5 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_ADDR, HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_RMSK) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_ADDR, m) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_ADDR,v) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_ADDR,m,v,HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_IN) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_WAKEUP_BMSK 0xf00 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_WAKEUP_SHFT 0x8 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_WAKEUP_CLOCK0_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_WAKEUP_CLOCK1_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_WAKEUP_CLOCK2_FVAL 0x2 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_WAKEUP_CLOCK3_FVAL 0x3 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_WAKEUP_CLOCK4_FVAL 0x4 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_WAKEUP_CLOCK5_FVAL 0x5 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_WAKEUP_CLOCK6_FVAL 0x6 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_WAKEUP_CLOCK7_FVAL 0x7 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_WAKEUP_CLOCK8_FVAL 0x8 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_WAKEUP_CLOCK9_FVAL 0x9 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_WAKEUP_CLOCK10_FVAL 0xa +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_WAKEUP_CLOCK11_FVAL 0xb +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_WAKEUP_CLOCK12_FVAL 0xc +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_WAKEUP_CLOCK13_FVAL 0xd +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_WAKEUP_CLOCK14_FVAL 0xe +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_WAKEUP_CLOCK15_FVAL 0xf +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_SLEEP_BMSK 0xf0 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_SLEEP_SHFT 0x4 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_SLEEP_CLOCK0_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_SLEEP_CLOCK1_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_SLEEP_CLOCK2_FVAL 0x2 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_SLEEP_CLOCK3_FVAL 0x3 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_SLEEP_CLOCK4_FVAL 0x4 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_SLEEP_CLOCK5_FVAL 0x5 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_SLEEP_CLOCK6_FVAL 0x6 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_SLEEP_CLOCK7_FVAL 0x7 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_SLEEP_CLOCK8_FVAL 0x8 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_SLEEP_CLOCK9_FVAL 0x9 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_SLEEP_CLOCK10_FVAL 0xa +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_SLEEP_CLOCK11_FVAL 0xb +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_SLEEP_CLOCK12_FVAL 0xc +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_SLEEP_CLOCK13_FVAL 0xd +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_SLEEP_CLOCK14_FVAL 0xe +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_SLEEP_CLOCK15_FVAL 0xf +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002b00c) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002b00c) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002b00c) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_RMSK 0xfffffffe +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_ADDR, HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_RMSK) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_ADDR, m) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_ADDR,v) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_ADDR,m,v,HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_IN) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xff000000 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xff0000 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002b010) +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002b010) +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002b010) +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_RMSK 0x81c07ff5 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_ADDR, HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_RMSK) +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_ADDR, m) +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_ADDR,v) +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_ADDR,m,v,HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_IN) +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_WAKEUP_BMSK 0xf00 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_WAKEUP_SHFT 0x8 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_WAKEUP_CLOCK0_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_WAKEUP_CLOCK1_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_WAKEUP_CLOCK2_FVAL 0x2 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_WAKEUP_CLOCK3_FVAL 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_WAKEUP_CLOCK4_FVAL 0x4 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_WAKEUP_CLOCK5_FVAL 0x5 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_WAKEUP_CLOCK6_FVAL 0x6 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_WAKEUP_CLOCK7_FVAL 0x7 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_WAKEUP_CLOCK8_FVAL 0x8 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_WAKEUP_CLOCK9_FVAL 0x9 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_WAKEUP_CLOCK10_FVAL 0xa +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_WAKEUP_CLOCK11_FVAL 0xb +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_WAKEUP_CLOCK12_FVAL 0xc +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_WAKEUP_CLOCK13_FVAL 0xd +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_WAKEUP_CLOCK14_FVAL 0xe +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_WAKEUP_CLOCK15_FVAL 0xf +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_SLEEP_BMSK 0xf0 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_SLEEP_SHFT 0x4 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_SLEEP_CLOCK0_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_SLEEP_CLOCK1_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_SLEEP_CLOCK2_FVAL 0x2 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_SLEEP_CLOCK3_FVAL 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_SLEEP_CLOCK4_FVAL 0x4 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_SLEEP_CLOCK5_FVAL 0x5 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_SLEEP_CLOCK6_FVAL 0x6 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_SLEEP_CLOCK7_FVAL 0x7 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_SLEEP_CLOCK8_FVAL 0x8 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_SLEEP_CLOCK9_FVAL 0x9 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_SLEEP_CLOCK10_FVAL 0xa +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_SLEEP_CLOCK11_FVAL 0xb +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_SLEEP_CLOCK12_FVAL 0xc +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_SLEEP_CLOCK13_FVAL 0xd +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_SLEEP_CLOCK14_FVAL 0xe +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_SLEEP_CLOCK15_FVAL 0xf +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002b014) +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002b014) +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002b014) +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_RMSK 0xfffffffe +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_ADDR, HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_RMSK) +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_ADDR, m) +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_ADDR,v) +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_ADDR,m,v,HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_IN) +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xff000000 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xff0000 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002b018) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002b018) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002b018) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CMD_RCGR_RMSK 0x800000f3 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_AHBFABRIC_CMD_RCGR_ADDR, HWIO_GCC_ULTAUDIO_AHBFABRIC_CMD_RCGR_RMSK) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_AHBFABRIC_CMD_RCGR_ADDR, m) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_AHBFABRIC_CMD_RCGR_ADDR,v) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_AHBFABRIC_CMD_RCGR_ADDR,m,v,HWIO_GCC_ULTAUDIO_AHBFABRIC_CMD_RCGR_IN) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CMD_RCGR_DIRTY_D_BMSK 0x80 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CMD_RCGR_DIRTY_D_SHFT 0x7 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CMD_RCGR_DIRTY_N_BMSK 0x40 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CMD_RCGR_DIRTY_N_SHFT 0x6 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CMD_RCGR_DIRTY_M_BMSK 0x20 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CMD_RCGR_DIRTY_M_SHFT 0x5 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002b01c) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002b01c) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002b01c) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_RMSK 0x10371f +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_ADDR, HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_RMSK) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_ADDR, m) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_ADDR,v) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_ADDR,m,v,HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_IN) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_MODE_BMSK 0x3000 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_MODE_SHFT 0xc +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002b020) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002b020) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002b020) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_M_RMSK 0xff +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_M_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_M_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_AHBFABRIC_M_ADDR, HWIO_GCC_ULTAUDIO_AHBFABRIC_M_RMSK) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_M_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_AHBFABRIC_M_ADDR, m) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_M_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_AHBFABRIC_M_ADDR,v) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_M_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_AHBFABRIC_M_ADDR,m,v,HWIO_GCC_ULTAUDIO_AHBFABRIC_M_IN) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_M_M_BMSK 0xff +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_M_M_SHFT 0x0 + +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002b024) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002b024) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002b024) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_N_RMSK 0xff +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_N_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_N_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_AHBFABRIC_N_ADDR, HWIO_GCC_ULTAUDIO_AHBFABRIC_N_RMSK) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_N_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_AHBFABRIC_N_ADDR, m) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_N_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_AHBFABRIC_N_ADDR,v) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_N_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_AHBFABRIC_N_ADDR,m,v,HWIO_GCC_ULTAUDIO_AHBFABRIC_N_IN) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_N_NOT_N_MINUS_M_BMSK 0xff +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_N_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002b028) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002b028) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002b028) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_D_RMSK 0xff +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_D_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_D_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_AHBFABRIC_D_ADDR, HWIO_GCC_ULTAUDIO_AHBFABRIC_D_RMSK) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_D_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_AHBFABRIC_D_ADDR, m) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_D_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_AHBFABRIC_D_ADDR,v) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_D_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_AHBFABRIC_D_ADDR,m,v,HWIO_GCC_ULTAUDIO_AHBFABRIC_D_IN) +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_D_NOT_2D_BMSK 0xff +#define HWIO_GCC_ULTAUDIO_AHBFABRIC_D_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_ULTAUDIO_PRI_I2S_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002c000) +#define HWIO_GCC_ULTAUDIO_PRI_I2S_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002c000) +#define HWIO_GCC_ULTAUDIO_PRI_I2S_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002c000) +#define HWIO_GCC_ULTAUDIO_PRI_I2S_BCR_RMSK 0x1 +#define HWIO_GCC_ULTAUDIO_PRI_I2S_BCR_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_PRI_I2S_BCR_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_PRI_I2S_BCR_ADDR, HWIO_GCC_ULTAUDIO_PRI_I2S_BCR_RMSK) +#define HWIO_GCC_ULTAUDIO_PRI_I2S_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_PRI_I2S_BCR_ADDR, m) +#define HWIO_GCC_ULTAUDIO_PRI_I2S_BCR_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_PRI_I2S_BCR_ADDR,v) +#define HWIO_GCC_ULTAUDIO_PRI_I2S_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_PRI_I2S_BCR_ADDR,m,v,HWIO_GCC_ULTAUDIO_PRI_I2S_BCR_IN) +#define HWIO_GCC_ULTAUDIO_PRI_I2S_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_ULTAUDIO_PRI_I2S_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_ULTAUDIO_PRI_I2S_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_PRI_I2S_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002c004) +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002c004) +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002c004) +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CBCR_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CBCR_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CBCR_ADDR, HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CBCR_RMSK) +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CBCR_ADDR, m) +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CBCR_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CBCR_ADDR,v) +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CBCR_ADDR,m,v,HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CBCR_IN) +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002c008) +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002c008) +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002c008) +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CMD_RCGR_RMSK 0x800000f3 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CMD_RCGR_ADDR, HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CMD_RCGR_RMSK) +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CMD_RCGR_ADDR, m) +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CMD_RCGR_ADDR,v) +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CMD_RCGR_ADDR,m,v,HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CMD_RCGR_IN) +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CMD_RCGR_DIRTY_D_BMSK 0x80 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CMD_RCGR_DIRTY_D_SHFT 0x7 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CMD_RCGR_DIRTY_N_BMSK 0x40 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CMD_RCGR_DIRTY_N_SHFT 0x6 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CMD_RCGR_DIRTY_M_BMSK 0x20 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CMD_RCGR_DIRTY_M_SHFT 0x5 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002c00c) +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002c00c) +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002c00c) +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_RMSK 0x10371f +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_ADDR, HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_RMSK) +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_ADDR, m) +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_ADDR,v) +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_ADDR,m,v,HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_IN) +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_MODE_BMSK 0x3000 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_MODE_SHFT 0xc +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002c010) +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002c010) +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002c010) +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_M_RMSK 0xff +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_M_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_M_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_M_ADDR, HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_M_RMSK) +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_M_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_M_ADDR, m) +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_M_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_M_ADDR,v) +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_M_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_M_ADDR,m,v,HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_M_IN) +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_M_M_BMSK 0xff +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_M_M_SHFT 0x0 + +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002c014) +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002c014) +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002c014) +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_N_RMSK 0xff +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_N_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_N_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_N_ADDR, HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_N_RMSK) +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_N_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_N_ADDR, m) +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_N_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_N_ADDR,v) +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_N_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_N_ADDR,m,v,HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_N_IN) +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_N_NOT_N_MINUS_M_BMSK 0xff +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_N_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002c018) +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002c018) +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002c018) +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_D_RMSK 0xff +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_D_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_D_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_D_ADDR, HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_D_RMSK) +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_D_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_D_ADDR, m) +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_D_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_D_ADDR,v) +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_D_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_D_ADDR,m,v,HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_D_IN) +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_D_NOT_2D_BMSK 0xff +#define HWIO_GCC_ULTAUDIO_LPAIF_PRI_I2S_D_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_ULTAUDIO_SEC_I2S_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002d000) +#define HWIO_GCC_ULTAUDIO_SEC_I2S_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002d000) +#define HWIO_GCC_ULTAUDIO_SEC_I2S_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002d000) +#define HWIO_GCC_ULTAUDIO_SEC_I2S_BCR_RMSK 0x1 +#define HWIO_GCC_ULTAUDIO_SEC_I2S_BCR_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_SEC_I2S_BCR_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_SEC_I2S_BCR_ADDR, HWIO_GCC_ULTAUDIO_SEC_I2S_BCR_RMSK) +#define HWIO_GCC_ULTAUDIO_SEC_I2S_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_SEC_I2S_BCR_ADDR, m) +#define HWIO_GCC_ULTAUDIO_SEC_I2S_BCR_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_SEC_I2S_BCR_ADDR,v) +#define HWIO_GCC_ULTAUDIO_SEC_I2S_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_SEC_I2S_BCR_ADDR,m,v,HWIO_GCC_ULTAUDIO_SEC_I2S_BCR_IN) +#define HWIO_GCC_ULTAUDIO_SEC_I2S_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_ULTAUDIO_SEC_I2S_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_ULTAUDIO_SEC_I2S_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_SEC_I2S_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002d004) +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002d004) +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002d004) +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CBCR_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CBCR_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CBCR_ADDR, HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CBCR_RMSK) +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CBCR_ADDR, m) +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CBCR_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CBCR_ADDR,v) +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CBCR_ADDR,m,v,HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CBCR_IN) +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002d008) +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002d008) +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002d008) +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CMD_RCGR_RMSK 0x800000f3 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CMD_RCGR_ADDR, HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CMD_RCGR_RMSK) +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CMD_RCGR_ADDR, m) +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CMD_RCGR_ADDR,v) +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CMD_RCGR_ADDR,m,v,HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CMD_RCGR_IN) +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CMD_RCGR_DIRTY_D_BMSK 0x80 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CMD_RCGR_DIRTY_D_SHFT 0x7 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CMD_RCGR_DIRTY_N_BMSK 0x40 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CMD_RCGR_DIRTY_N_SHFT 0x6 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CMD_RCGR_DIRTY_M_BMSK 0x20 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CMD_RCGR_DIRTY_M_SHFT 0x5 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002d00c) +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002d00c) +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002d00c) +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_RMSK 0x10371f +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_ADDR, HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_RMSK) +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_ADDR, m) +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_ADDR,v) +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_ADDR,m,v,HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_IN) +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_MODE_BMSK 0x3000 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_MODE_SHFT 0xc +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002d010) +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002d010) +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002d010) +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_M_RMSK 0xff +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_M_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_M_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_M_ADDR, HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_M_RMSK) +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_M_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_M_ADDR, m) +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_M_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_M_ADDR,v) +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_M_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_M_ADDR,m,v,HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_M_IN) +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_M_M_BMSK 0xff +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_M_M_SHFT 0x0 + +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002d014) +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002d014) +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002d014) +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_N_RMSK 0xff +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_N_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_N_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_N_ADDR, HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_N_RMSK) +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_N_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_N_ADDR, m) +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_N_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_N_ADDR,v) +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_N_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_N_ADDR,m,v,HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_N_IN) +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_N_NOT_N_MINUS_M_BMSK 0xff +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_N_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002d018) +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002d018) +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002d018) +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_D_RMSK 0xff +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_D_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_D_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_D_ADDR, HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_D_RMSK) +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_D_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_D_ADDR, m) +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_D_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_D_ADDR,v) +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_D_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_D_ADDR,m,v,HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_D_IN) +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_D_NOT_2D_BMSK 0xff +#define HWIO_GCC_ULTAUDIO_LPAIF_SEC_I2S_D_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_ULTAUDIO_AUX_I2S_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002e000) +#define HWIO_GCC_ULTAUDIO_AUX_I2S_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002e000) +#define HWIO_GCC_ULTAUDIO_AUX_I2S_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002e000) +#define HWIO_GCC_ULTAUDIO_AUX_I2S_BCR_RMSK 0x1 +#define HWIO_GCC_ULTAUDIO_AUX_I2S_BCR_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_AUX_I2S_BCR_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_AUX_I2S_BCR_ADDR, HWIO_GCC_ULTAUDIO_AUX_I2S_BCR_RMSK) +#define HWIO_GCC_ULTAUDIO_AUX_I2S_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_AUX_I2S_BCR_ADDR, m) +#define HWIO_GCC_ULTAUDIO_AUX_I2S_BCR_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_AUX_I2S_BCR_ADDR,v) +#define HWIO_GCC_ULTAUDIO_AUX_I2S_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_AUX_I2S_BCR_ADDR,m,v,HWIO_GCC_ULTAUDIO_AUX_I2S_BCR_IN) +#define HWIO_GCC_ULTAUDIO_AUX_I2S_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_ULTAUDIO_AUX_I2S_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_ULTAUDIO_AUX_I2S_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_AUX_I2S_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002e004) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002e004) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002e004) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CBCR_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CBCR_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CBCR_ADDR, HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CBCR_RMSK) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CBCR_ADDR, m) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CBCR_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CBCR_ADDR,v) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CBCR_ADDR,m,v,HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CBCR_IN) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002e008) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002e008) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002e008) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CMD_RCGR_RMSK 0x800000f3 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CMD_RCGR_ADDR, HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CMD_RCGR_RMSK) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CMD_RCGR_ADDR, m) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CMD_RCGR_ADDR,v) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CMD_RCGR_ADDR,m,v,HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CMD_RCGR_IN) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CMD_RCGR_DIRTY_D_BMSK 0x80 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CMD_RCGR_DIRTY_D_SHFT 0x7 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CMD_RCGR_DIRTY_N_BMSK 0x40 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CMD_RCGR_DIRTY_N_SHFT 0x6 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CMD_RCGR_DIRTY_M_BMSK 0x20 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CMD_RCGR_DIRTY_M_SHFT 0x5 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002e00c) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002e00c) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002e00c) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_RMSK 0x10371f +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_ADDR, HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_RMSK) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_ADDR, m) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_ADDR,v) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_ADDR,m,v,HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_IN) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_MODE_BMSK 0x3000 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_MODE_SHFT 0xc +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002e010) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002e010) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002e010) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_M_RMSK 0xff +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_M_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_M_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_M_ADDR, HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_M_RMSK) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_M_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_M_ADDR, m) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_M_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_M_ADDR,v) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_M_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_M_ADDR,m,v,HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_M_IN) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_M_M_BMSK 0xff +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_M_M_SHFT 0x0 + +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002e014) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002e014) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002e014) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_N_RMSK 0xff +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_N_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_N_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_N_ADDR, HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_N_RMSK) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_N_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_N_ADDR, m) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_N_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_N_ADDR,v) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_N_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_N_ADDR,m,v,HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_N_IN) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_N_NOT_N_MINUS_M_BMSK 0xff +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_N_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002e018) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002e018) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002e018) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_D_RMSK 0xff +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_D_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_D_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_D_ADDR, HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_D_RMSK) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_D_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_D_ADDR, m) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_D_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_D_ADDR,v) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_D_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_D_ADDR,m,v,HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_D_IN) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_D_NOT_2D_BMSK 0xff +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_I2S_D_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_AUDIO_CXO_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002f000) +#define HWIO_GCC_AUDIO_CXO_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002f000) +#define HWIO_GCC_AUDIO_CXO_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002f000) +#define HWIO_GCC_AUDIO_CXO_BCR_RMSK 0x1 +#define HWIO_GCC_AUDIO_CXO_BCR_ATTR 0x3 +#define HWIO_GCC_AUDIO_CXO_BCR_IN \ + in_dword_masked(HWIO_GCC_AUDIO_CXO_BCR_ADDR, HWIO_GCC_AUDIO_CXO_BCR_RMSK) +#define HWIO_GCC_AUDIO_CXO_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_AUDIO_CXO_BCR_ADDR, m) +#define HWIO_GCC_AUDIO_CXO_BCR_OUT(v) \ + out_dword(HWIO_GCC_AUDIO_CXO_BCR_ADDR,v) +#define HWIO_GCC_AUDIO_CXO_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AUDIO_CXO_BCR_ADDR,m,v,HWIO_GCC_AUDIO_CXO_BCR_IN) +#define HWIO_GCC_AUDIO_CXO_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_AUDIO_CXO_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_AUDIO_CXO_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_AUDIO_CXO_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_ULTAUDIO_AVSYNC_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002f004) +#define HWIO_GCC_ULTAUDIO_AVSYNC_XO_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002f004) +#define HWIO_GCC_ULTAUDIO_AVSYNC_XO_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002f004) +#define HWIO_GCC_ULTAUDIO_AVSYNC_XO_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_ULTAUDIO_AVSYNC_XO_CBCR_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_AVSYNC_XO_CBCR_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_AVSYNC_XO_CBCR_ADDR, HWIO_GCC_ULTAUDIO_AVSYNC_XO_CBCR_RMSK) +#define HWIO_GCC_ULTAUDIO_AVSYNC_XO_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_AVSYNC_XO_CBCR_ADDR, m) +#define HWIO_GCC_ULTAUDIO_AVSYNC_XO_CBCR_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_AVSYNC_XO_CBCR_ADDR,v) +#define HWIO_GCC_ULTAUDIO_AVSYNC_XO_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_AVSYNC_XO_CBCR_ADDR,m,v,HWIO_GCC_ULTAUDIO_AVSYNC_XO_CBCR_IN) +#define HWIO_GCC_ULTAUDIO_AVSYNC_XO_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_ULTAUDIO_AVSYNC_XO_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_ULTAUDIO_AVSYNC_XO_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_ULTAUDIO_AVSYNC_XO_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_ULTAUDIO_AVSYNC_XO_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_ULTAUDIO_AVSYNC_XO_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_ULTAUDIO_AVSYNC_XO_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_ULTAUDIO_AVSYNC_XO_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_ULTAUDIO_AVSYNC_XO_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_ULTAUDIO_AVSYNC_XO_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_ULTAUDIO_AVSYNC_XO_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_AVSYNC_XO_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_AVSYNC_XO_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_ULTAUDIO_AVSYNC_XO_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_ULTAUDIO_AVSYNC_XO_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_AVSYNC_XO_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_ULTAUDIO_XO_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002f008) +#define HWIO_GCC_ULTAUDIO_XO_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002f008) +#define HWIO_GCC_ULTAUDIO_XO_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002f008) +#define HWIO_GCC_ULTAUDIO_XO_CMD_RCGR_RMSK 0x800000f3 +#define HWIO_GCC_ULTAUDIO_XO_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_XO_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_XO_CMD_RCGR_ADDR, HWIO_GCC_ULTAUDIO_XO_CMD_RCGR_RMSK) +#define HWIO_GCC_ULTAUDIO_XO_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_XO_CMD_RCGR_ADDR, m) +#define HWIO_GCC_ULTAUDIO_XO_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_XO_CMD_RCGR_ADDR,v) +#define HWIO_GCC_ULTAUDIO_XO_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_XO_CMD_RCGR_ADDR,m,v,HWIO_GCC_ULTAUDIO_XO_CMD_RCGR_IN) +#define HWIO_GCC_ULTAUDIO_XO_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_ULTAUDIO_XO_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_ULTAUDIO_XO_CMD_RCGR_DIRTY_D_BMSK 0x80 +#define HWIO_GCC_ULTAUDIO_XO_CMD_RCGR_DIRTY_D_SHFT 0x7 +#define HWIO_GCC_ULTAUDIO_XO_CMD_RCGR_DIRTY_N_BMSK 0x40 +#define HWIO_GCC_ULTAUDIO_XO_CMD_RCGR_DIRTY_N_SHFT 0x6 +#define HWIO_GCC_ULTAUDIO_XO_CMD_RCGR_DIRTY_M_BMSK 0x20 +#define HWIO_GCC_ULTAUDIO_XO_CMD_RCGR_DIRTY_M_SHFT 0x5 +#define HWIO_GCC_ULTAUDIO_XO_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_ULTAUDIO_XO_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_ULTAUDIO_XO_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_ULTAUDIO_XO_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_ULTAUDIO_XO_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_XO_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_XO_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_ULTAUDIO_XO_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_ULTAUDIO_XO_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_XO_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002f00c) +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002f00c) +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002f00c) +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_RMSK 0x10371f +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_ADDR, HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_RMSK) +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_ADDR, m) +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_ADDR,v) +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_ADDR,m,v,HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_IN) +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_MODE_BMSK 0x3000 +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_MODE_SHFT 0xc +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_ULTAUDIO_XO_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_ULTAUDIO_XO_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002f010) +#define HWIO_GCC_ULTAUDIO_XO_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002f010) +#define HWIO_GCC_ULTAUDIO_XO_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002f010) +#define HWIO_GCC_ULTAUDIO_XO_M_RMSK 0xff +#define HWIO_GCC_ULTAUDIO_XO_M_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_XO_M_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_XO_M_ADDR, HWIO_GCC_ULTAUDIO_XO_M_RMSK) +#define HWIO_GCC_ULTAUDIO_XO_M_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_XO_M_ADDR, m) +#define HWIO_GCC_ULTAUDIO_XO_M_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_XO_M_ADDR,v) +#define HWIO_GCC_ULTAUDIO_XO_M_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_XO_M_ADDR,m,v,HWIO_GCC_ULTAUDIO_XO_M_IN) +#define HWIO_GCC_ULTAUDIO_XO_M_M_BMSK 0xff +#define HWIO_GCC_ULTAUDIO_XO_M_M_SHFT 0x0 + +#define HWIO_GCC_ULTAUDIO_XO_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002f014) +#define HWIO_GCC_ULTAUDIO_XO_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002f014) +#define HWIO_GCC_ULTAUDIO_XO_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002f014) +#define HWIO_GCC_ULTAUDIO_XO_N_RMSK 0xff +#define HWIO_GCC_ULTAUDIO_XO_N_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_XO_N_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_XO_N_ADDR, HWIO_GCC_ULTAUDIO_XO_N_RMSK) +#define HWIO_GCC_ULTAUDIO_XO_N_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_XO_N_ADDR, m) +#define HWIO_GCC_ULTAUDIO_XO_N_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_XO_N_ADDR,v) +#define HWIO_GCC_ULTAUDIO_XO_N_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_XO_N_ADDR,m,v,HWIO_GCC_ULTAUDIO_XO_N_IN) +#define HWIO_GCC_ULTAUDIO_XO_N_NOT_N_MINUS_M_BMSK 0xff +#define HWIO_GCC_ULTAUDIO_XO_N_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_ULTAUDIO_XO_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002f018) +#define HWIO_GCC_ULTAUDIO_XO_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002f018) +#define HWIO_GCC_ULTAUDIO_XO_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002f018) +#define HWIO_GCC_ULTAUDIO_XO_D_RMSK 0xff +#define HWIO_GCC_ULTAUDIO_XO_D_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_XO_D_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_XO_D_ADDR, HWIO_GCC_ULTAUDIO_XO_D_RMSK) +#define HWIO_GCC_ULTAUDIO_XO_D_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_XO_D_ADDR, m) +#define HWIO_GCC_ULTAUDIO_XO_D_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_XO_D_ADDR,v) +#define HWIO_GCC_ULTAUDIO_XO_D_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_XO_D_ADDR,m,v,HWIO_GCC_ULTAUDIO_XO_D_IN) +#define HWIO_GCC_ULTAUDIO_XO_D_NOT_2D_BMSK 0xff +#define HWIO_GCC_ULTAUDIO_XO_D_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_ULTAUDIO_EXT_I2S_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00030000) +#define HWIO_GCC_ULTAUDIO_EXT_I2S_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00030000) +#define HWIO_GCC_ULTAUDIO_EXT_I2S_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00030000) +#define HWIO_GCC_ULTAUDIO_EXT_I2S_BCR_RMSK 0x1 +#define HWIO_GCC_ULTAUDIO_EXT_I2S_BCR_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_EXT_I2S_BCR_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_EXT_I2S_BCR_ADDR, HWIO_GCC_ULTAUDIO_EXT_I2S_BCR_RMSK) +#define HWIO_GCC_ULTAUDIO_EXT_I2S_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_EXT_I2S_BCR_ADDR, m) +#define HWIO_GCC_ULTAUDIO_EXT_I2S_BCR_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_EXT_I2S_BCR_ADDR,v) +#define HWIO_GCC_ULTAUDIO_EXT_I2S_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_EXT_I2S_BCR_ADDR,m,v,HWIO_GCC_ULTAUDIO_EXT_I2S_BCR_IN) +#define HWIO_GCC_ULTAUDIO_EXT_I2S_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_ULTAUDIO_EXT_I2S_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_ULTAUDIO_EXT_I2S_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_EXT_I2S_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00030004) +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00030004) +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00030004) +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CBCR_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CBCR_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CBCR_ADDR, HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CBCR_RMSK) +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CBCR_ADDR, m) +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CBCR_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CBCR_ADDR,v) +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CBCR_ADDR,m,v,HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CBCR_IN) +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00030008) +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00030008) +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00030008) +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CMD_RCGR_RMSK 0x800000f3 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CMD_RCGR_ADDR, HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CMD_RCGR_RMSK) +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CMD_RCGR_ADDR, m) +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CMD_RCGR_ADDR,v) +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CMD_RCGR_ADDR,m,v,HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CMD_RCGR_IN) +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CMD_RCGR_DIRTY_D_BMSK 0x80 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CMD_RCGR_DIRTY_D_SHFT 0x7 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CMD_RCGR_DIRTY_N_BMSK 0x40 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CMD_RCGR_DIRTY_N_SHFT 0x6 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CMD_RCGR_DIRTY_M_BMSK 0x20 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CMD_RCGR_DIRTY_M_SHFT 0x5 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003000c) +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003000c) +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003000c) +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_RMSK 0x10371f +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_ADDR, HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_RMSK) +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_ADDR, m) +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_ADDR,v) +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_ADDR,m,v,HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_IN) +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_MODE_BMSK 0x3000 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_MODE_SHFT 0xc +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00030010) +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00030010) +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00030010) +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_M_RMSK 0xff +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_M_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_M_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_M_ADDR, HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_M_RMSK) +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_M_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_M_ADDR, m) +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_M_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_M_ADDR,v) +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_M_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_M_ADDR,m,v,HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_M_IN) +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_M_M_BMSK 0xff +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_M_M_SHFT 0x0 + +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00030014) +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00030014) +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00030014) +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_N_RMSK 0xff +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_N_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_N_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_N_ADDR, HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_N_RMSK) +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_N_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_N_ADDR, m) +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_N_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_N_ADDR,v) +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_N_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_N_ADDR,m,v,HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_N_IN) +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_N_NOT_N_MINUS_M_BMSK 0xff +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_N_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00030018) +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00030018) +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00030018) +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_D_RMSK 0xff +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_D_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_D_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_D_ADDR, HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_D_RMSK) +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_D_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_D_ADDR, m) +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_D_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_D_ADDR,v) +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_D_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_D_ADDR,m,v,HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_D_IN) +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_D_NOT_2D_BMSK 0xff +#define HWIO_GCC_ULTAUDIO_LPAIF_EXT_I2S_D_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_SLIMBUS_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00031000) +#define HWIO_GCC_SLIMBUS_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00031000) +#define HWIO_GCC_SLIMBUS_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00031000) +#define HWIO_GCC_SLIMBUS_BCR_RMSK 0x1 +#define HWIO_GCC_SLIMBUS_BCR_ATTR 0x3 +#define HWIO_GCC_SLIMBUS_BCR_IN \ + in_dword_masked(HWIO_GCC_SLIMBUS_BCR_ADDR, HWIO_GCC_SLIMBUS_BCR_RMSK) +#define HWIO_GCC_SLIMBUS_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_SLIMBUS_BCR_ADDR, m) +#define HWIO_GCC_SLIMBUS_BCR_OUT(v) \ + out_dword(HWIO_GCC_SLIMBUS_BCR_ADDR,v) +#define HWIO_GCC_SLIMBUS_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SLIMBUS_BCR_ADDR,m,v,HWIO_GCC_SLIMBUS_BCR_IN) +#define HWIO_GCC_SLIMBUS_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_SLIMBUS_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_SLIMBUS_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_SLIMBUS_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00031004) +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00031004) +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00031004) +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CBCR_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CBCR_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CBCR_ADDR, HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CBCR_RMSK) +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CBCR_ADDR, m) +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CBCR_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CBCR_ADDR,v) +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CBCR_ADDR,m,v,HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CBCR_IN) +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00031008) +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00031008) +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00031008) +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CMD_RCGR_RMSK 0x800000f3 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CMD_RCGR_ADDR, HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CMD_RCGR_RMSK) +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CMD_RCGR_ADDR, m) +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CMD_RCGR_ADDR,v) +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CMD_RCGR_ADDR,m,v,HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CMD_RCGR_IN) +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CMD_RCGR_DIRTY_D_BMSK 0x80 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CMD_RCGR_DIRTY_D_SHFT 0x7 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CMD_RCGR_DIRTY_N_BMSK 0x40 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CMD_RCGR_DIRTY_N_SHFT 0x6 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CMD_RCGR_DIRTY_M_BMSK 0x20 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CMD_RCGR_DIRTY_M_SHFT 0x5 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003100c) +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003100c) +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003100c) +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_RMSK 0x10371f +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_ADDR, HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_RMSK) +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_ADDR, m) +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_ADDR,v) +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_ADDR,m,v,HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_IN) +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_MODE_BMSK 0x3000 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_MODE_SHFT 0xc +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00031010) +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00031010) +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00031010) +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_M_RMSK 0xff +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_M_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_M_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_M_ADDR, HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_M_RMSK) +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_M_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_M_ADDR, m) +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_M_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_M_ADDR,v) +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_M_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_M_ADDR,m,v,HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_M_IN) +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_M_M_BMSK 0xff +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_M_M_SHFT 0x0 + +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00031014) +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00031014) +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00031014) +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_N_RMSK 0xff +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_N_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_N_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_N_ADDR, HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_N_RMSK) +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_N_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_N_ADDR, m) +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_N_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_N_ADDR,v) +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_N_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_N_ADDR,m,v,HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_N_IN) +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_N_NOT_N_MINUS_M_BMSK 0xff +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_N_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00031018) +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00031018) +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00031018) +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_D_RMSK 0xff +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_D_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_D_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_D_ADDR, HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_D_RMSK) +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_D_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_D_ADDR, m) +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_D_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_D_ADDR,v) +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_D_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_D_ADDR,m,v,HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_D_IN) +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_D_NOT_2D_BMSK 0xff +#define HWIO_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_D_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_ULTAUDIO_PCM_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00032000) +#define HWIO_GCC_ULTAUDIO_PCM_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00032000) +#define HWIO_GCC_ULTAUDIO_PCM_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00032000) +#define HWIO_GCC_ULTAUDIO_PCM_BCR_RMSK 0x1 +#define HWIO_GCC_ULTAUDIO_PCM_BCR_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_PCM_BCR_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_PCM_BCR_ADDR, HWIO_GCC_ULTAUDIO_PCM_BCR_RMSK) +#define HWIO_GCC_ULTAUDIO_PCM_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_PCM_BCR_ADDR, m) +#define HWIO_GCC_ULTAUDIO_PCM_BCR_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_PCM_BCR_ADDR,v) +#define HWIO_GCC_ULTAUDIO_PCM_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_PCM_BCR_ADDR,m,v,HWIO_GCC_ULTAUDIO_PCM_BCR_IN) +#define HWIO_GCC_ULTAUDIO_PCM_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_ULTAUDIO_PCM_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_ULTAUDIO_PCM_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_PCM_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00032004) +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00032004) +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00032004) +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CBCR_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CBCR_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CBCR_ADDR, HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CBCR_RMSK) +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CBCR_ADDR, m) +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CBCR_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CBCR_ADDR,v) +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CBCR_ADDR,m,v,HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CBCR_IN) +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00032008) +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00032008) +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00032008) +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CMD_RCGR_RMSK 0x800000f3 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CMD_RCGR_ADDR, HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CMD_RCGR_RMSK) +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CMD_RCGR_ADDR, m) +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CMD_RCGR_ADDR,v) +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CMD_RCGR_ADDR,m,v,HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CMD_RCGR_IN) +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CMD_RCGR_DIRTY_D_BMSK 0x80 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CMD_RCGR_DIRTY_D_SHFT 0x7 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CMD_RCGR_DIRTY_N_BMSK 0x40 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CMD_RCGR_DIRTY_N_SHFT 0x6 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CMD_RCGR_DIRTY_M_BMSK 0x20 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CMD_RCGR_DIRTY_M_SHFT 0x5 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003200c) +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003200c) +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003200c) +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_RMSK 0x10371f +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_ADDR, HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_RMSK) +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_ADDR, m) +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_ADDR,v) +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_ADDR,m,v,HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_IN) +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_MODE_BMSK 0x3000 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_MODE_SHFT 0xc +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00032010) +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00032010) +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00032010) +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_M_RMSK 0xff +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_M_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_M_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_M_ADDR, HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_M_RMSK) +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_M_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_M_ADDR, m) +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_M_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_M_ADDR,v) +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_M_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_M_ADDR,m,v,HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_M_IN) +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_M_M_BMSK 0xff +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_M_M_SHFT 0x0 + +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00032014) +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00032014) +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00032014) +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_N_RMSK 0xff +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_N_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_N_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_N_ADDR, HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_N_RMSK) +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_N_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_N_ADDR, m) +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_N_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_N_ADDR,v) +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_N_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_N_ADDR,m,v,HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_N_IN) +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_N_NOT_N_MINUS_M_BMSK 0xff +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_N_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00032018) +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00032018) +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00032018) +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_D_RMSK 0xff +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_D_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_D_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_D_ADDR, HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_D_RMSK) +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_D_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_D_ADDR, m) +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_D_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_D_ADDR,v) +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_D_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_D_ADDR,m,v,HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_D_IN) +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_D_NOT_2D_BMSK 0xff +#define HWIO_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_D_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00032020) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00032020) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00032020) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CBCR_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CBCR_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CBCR_ADDR, HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CBCR_RMSK) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CBCR_ADDR, m) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CBCR_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CBCR_ADDR,v) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CBCR_ADDR,m,v,HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CBCR_IN) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00032024) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00032024) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00032024) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CMD_RCGR_RMSK 0x800000f3 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CMD_RCGR_ADDR, HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CMD_RCGR_RMSK) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CMD_RCGR_ADDR, m) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CMD_RCGR_ADDR,v) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CMD_RCGR_ADDR,m,v,HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CMD_RCGR_IN) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CMD_RCGR_DIRTY_D_BMSK 0x80 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CMD_RCGR_DIRTY_D_SHFT 0x7 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CMD_RCGR_DIRTY_N_BMSK 0x40 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CMD_RCGR_DIRTY_N_SHFT 0x6 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CMD_RCGR_DIRTY_M_BMSK 0x20 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CMD_RCGR_DIRTY_M_SHFT 0x5 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00032028) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00032028) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00032028) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_RMSK 0x10371f +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_ADDR, HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_RMSK) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_ADDR, m) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_ADDR,v) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_ADDR,m,v,HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_IN) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_MODE_BMSK 0x3000 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_MODE_SHFT 0xc +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003202c) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003202c) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003202c) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_M_RMSK 0xff +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_M_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_M_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_M_ADDR, HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_M_RMSK) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_M_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_M_ADDR, m) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_M_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_M_ADDR,v) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_M_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_M_ADDR,m,v,HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_M_IN) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_M_M_BMSK 0xff +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_M_M_SHFT 0x0 + +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00032030) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00032030) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00032030) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_N_RMSK 0xff +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_N_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_N_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_N_ADDR, HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_N_RMSK) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_N_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_N_ADDR, m) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_N_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_N_ADDR,v) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_N_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_N_ADDR,m,v,HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_N_IN) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_N_NOT_N_MINUS_M_BMSK 0xff +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_N_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00032034) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00032034) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00032034) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_D_RMSK 0xff +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_D_ATTR 0x3 +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_D_IN \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_D_ADDR, HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_D_RMSK) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_D_INM(m) \ + in_dword_masked(HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_D_ADDR, m) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_D_OUT(v) \ + out_dword(HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_D_ADDR,v) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_D_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_D_ADDR,m,v,HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_D_IN) +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_D_NOT_2D_BMSK 0xff +#define HWIO_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_D_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_PCIE_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00033000) +#define HWIO_GCC_PCIE_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00033000) +#define HWIO_GCC_PCIE_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00033000) +#define HWIO_GCC_PCIE_BCR_RMSK 0x1 +#define HWIO_GCC_PCIE_BCR_ATTR 0x3 +#define HWIO_GCC_PCIE_BCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_BCR_ADDR, HWIO_GCC_PCIE_BCR_RMSK) +#define HWIO_GCC_PCIE_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_BCR_ADDR, m) +#define HWIO_GCC_PCIE_BCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_BCR_ADDR,v) +#define HWIO_GCC_PCIE_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_BCR_ADDR,m,v,HWIO_GCC_PCIE_BCR_IN) +#define HWIO_GCC_PCIE_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_PCIE_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_PCIE_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00033004) +#define HWIO_GCC_PCIE_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00033004) +#define HWIO_GCC_PCIE_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00033004) +#define HWIO_GCC_PCIE_GDSCR_RMSK 0xf8ffffff +#define HWIO_GCC_PCIE_GDSCR_ATTR 0x3 +#define HWIO_GCC_PCIE_GDSCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_GDSCR_ADDR, HWIO_GCC_PCIE_GDSCR_RMSK) +#define HWIO_GCC_PCIE_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_GDSCR_ADDR, m) +#define HWIO_GCC_PCIE_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_GDSCR_ADDR,v) +#define HWIO_GCC_PCIE_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_GDSCR_ADDR,m,v,HWIO_GCC_PCIE_GDSCR_IN) +#define HWIO_GCC_PCIE_GDSCR_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_PCIE_GDSCR_PWR_ON_SHFT 0x1f +#define HWIO_GCC_PCIE_GDSCR_GDSC_STATE_BMSK 0x78000000 +#define HWIO_GCC_PCIE_GDSCR_GDSC_STATE_SHFT 0x1b +#define HWIO_GCC_PCIE_GDSCR_EN_REST_WAIT_BMSK 0xf00000 +#define HWIO_GCC_PCIE_GDSCR_EN_REST_WAIT_SHFT 0x14 +#define HWIO_GCC_PCIE_GDSCR_EN_FEW_WAIT_BMSK 0xf0000 +#define HWIO_GCC_PCIE_GDSCR_EN_FEW_WAIT_SHFT 0x10 +#define HWIO_GCC_PCIE_GDSCR_CLK_DIS_WAIT_BMSK 0xf000 +#define HWIO_GCC_PCIE_GDSCR_CLK_DIS_WAIT_SHFT 0xc +#define HWIO_GCC_PCIE_GDSCR_RETAIN_FF_ENABLE_BMSK 0x800 +#define HWIO_GCC_PCIE_GDSCR_RETAIN_FF_ENABLE_SHFT 0xb +#define HWIO_GCC_PCIE_GDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_GDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_GDSCR_RESTORE_BMSK 0x400 +#define HWIO_GCC_PCIE_GDSCR_RESTORE_SHFT 0xa +#define HWIO_GCC_PCIE_GDSCR_RESTORE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_GDSCR_RESTORE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_GDSCR_SAVE_BMSK 0x200 +#define HWIO_GCC_PCIE_GDSCR_SAVE_SHFT 0x9 +#define HWIO_GCC_PCIE_GDSCR_SAVE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_GDSCR_SAVE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_GDSCR_RETAIN_BMSK 0x100 +#define HWIO_GCC_PCIE_GDSCR_RETAIN_SHFT 0x8 +#define HWIO_GCC_PCIE_GDSCR_RETAIN_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_GDSCR_RETAIN_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_GDSCR_EN_REST_BMSK 0x80 +#define HWIO_GCC_PCIE_GDSCR_EN_REST_SHFT 0x7 +#define HWIO_GCC_PCIE_GDSCR_EN_REST_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_GDSCR_EN_REST_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_GDSCR_EN_FEW_BMSK 0x40 +#define HWIO_GCC_PCIE_GDSCR_EN_FEW_SHFT 0x6 +#define HWIO_GCC_PCIE_GDSCR_EN_FEW_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_GDSCR_EN_FEW_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_GDSCR_CLAMP_IO_BMSK 0x20 +#define HWIO_GCC_PCIE_GDSCR_CLAMP_IO_SHFT 0x5 +#define HWIO_GCC_PCIE_GDSCR_CLAMP_IO_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_GDSCR_CLAMP_IO_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_GDSCR_CLK_DISABLE_BMSK 0x10 +#define HWIO_GCC_PCIE_GDSCR_CLK_DISABLE_SHFT 0x4 +#define HWIO_GCC_PCIE_GDSCR_CLK_DISABLE_CLK_NOT_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_GDSCR_CLK_DISABLE_CLK_IS_DISABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_GDSCR_PD_ARES_BMSK 0x8 +#define HWIO_GCC_PCIE_GDSCR_PD_ARES_SHFT 0x3 +#define HWIO_GCC_PCIE_GDSCR_PD_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_PCIE_GDSCR_PD_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_PCIE_GDSCR_SW_OVERRIDE_BMSK 0x4 +#define HWIO_GCC_PCIE_GDSCR_SW_OVERRIDE_SHFT 0x2 +#define HWIO_GCC_PCIE_GDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_GDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_GDSCR_HW_CONTROL_BMSK 0x2 +#define HWIO_GCC_PCIE_GDSCR_HW_CONTROL_SHFT 0x1 +#define HWIO_GCC_PCIE_GDSCR_HW_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_GDSCR_HW_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_GDSCR_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_PCIE_GDSCR_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_PCIE_GDSCR_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_GDSCR_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_CFG_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00033008) +#define HWIO_GCC_PCIE_CFG_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00033008) +#define HWIO_GCC_PCIE_CFG_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00033008) +#define HWIO_GCC_PCIE_CFG_GDSCR_RMSK 0x3ffffff +#define HWIO_GCC_PCIE_CFG_GDSCR_ATTR 0x3 +#define HWIO_GCC_PCIE_CFG_GDSCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_CFG_GDSCR_ADDR, HWIO_GCC_PCIE_CFG_GDSCR_RMSK) +#define HWIO_GCC_PCIE_CFG_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_CFG_GDSCR_ADDR, m) +#define HWIO_GCC_PCIE_CFG_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_CFG_GDSCR_ADDR,v) +#define HWIO_GCC_PCIE_CFG_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_CFG_GDSCR_ADDR,m,v,HWIO_GCC_PCIE_CFG_GDSCR_IN) +#define HWIO_GCC_PCIE_CFG_GDSCR_GDSC_PWR_DWN_START_BMSK 0x2000000 +#define HWIO_GCC_PCIE_CFG_GDSCR_GDSC_PWR_DWN_START_SHFT 0x19 +#define HWIO_GCC_PCIE_CFG_GDSCR_GDSC_PWR_UP_START_BMSK 0x1000000 +#define HWIO_GCC_PCIE_CFG_GDSCR_GDSC_PWR_UP_START_SHFT 0x18 +#define HWIO_GCC_PCIE_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_BMSK 0xf00000 +#define HWIO_GCC_PCIE_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_SHFT 0x14 +#define HWIO_GCC_PCIE_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_BMSK 0x80000 +#define HWIO_GCC_PCIE_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_SHFT 0x13 +#define HWIO_GCC_PCIE_CFG_GDSCR_GDSC_ENR_ACK_STATUS_BMSK 0x40000 +#define HWIO_GCC_PCIE_CFG_GDSCR_GDSC_ENR_ACK_STATUS_SHFT 0x12 +#define HWIO_GCC_PCIE_CFG_GDSCR_GDSC_ENF_ACK_STATUS_BMSK 0x20000 +#define HWIO_GCC_PCIE_CFG_GDSCR_GDSC_ENF_ACK_STATUS_SHFT 0x11 +#define HWIO_GCC_PCIE_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_BMSK 0x10000 +#define HWIO_GCC_PCIE_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_SHFT 0x10 +#define HWIO_GCC_PCIE_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_BMSK 0x8000 +#define HWIO_GCC_PCIE_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_SHFT 0xf +#define HWIO_GCC_PCIE_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_BMSK 0x7800 +#define HWIO_GCC_PCIE_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_SHFT 0xb +#define HWIO_GCC_PCIE_CFG_GDSCR_GDSC_HANDSHAKE_DIS_BMSK 0x400 +#define HWIO_GCC_PCIE_CFG_GDSCR_GDSC_HANDSHAKE_DIS_SHFT 0xa +#define HWIO_GCC_PCIE_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_BMSK 0x200 +#define HWIO_GCC_PCIE_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_SHFT 0x9 +#define HWIO_GCC_PCIE_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_BMSK 0x100 +#define HWIO_GCC_PCIE_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_SHFT 0x8 +#define HWIO_GCC_PCIE_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_BMSK 0x80 +#define HWIO_GCC_PCIE_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_SHFT 0x7 +#define HWIO_GCC_PCIE_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_BMSK 0x60 +#define HWIO_GCC_PCIE_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_SHFT 0x5 +#define HWIO_GCC_PCIE_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_BMSK 0x10 +#define HWIO_GCC_PCIE_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_SHFT 0x4 +#define HWIO_GCC_PCIE_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_BMSK 0x8 +#define HWIO_GCC_PCIE_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_SHFT 0x3 +#define HWIO_GCC_PCIE_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_BMSK 0x4 +#define HWIO_GCC_PCIE_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_SHFT 0x2 +#define HWIO_GCC_PCIE_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_BMSK 0x2 +#define HWIO_GCC_PCIE_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_SHFT 0x1 +#define HWIO_GCC_PCIE_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_PCIE_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_SHFT 0x0 + +#define HWIO_GCC_PCIE_CFG2_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003300c) +#define HWIO_GCC_PCIE_CFG2_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003300c) +#define HWIO_GCC_PCIE_CFG2_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003300c) +#define HWIO_GCC_PCIE_CFG2_GDSCR_RMSK 0x7ffff +#define HWIO_GCC_PCIE_CFG2_GDSCR_ATTR 0x3 +#define HWIO_GCC_PCIE_CFG2_GDSCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_CFG2_GDSCR_ADDR, HWIO_GCC_PCIE_CFG2_GDSCR_RMSK) +#define HWIO_GCC_PCIE_CFG2_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_CFG2_GDSCR_ADDR, m) +#define HWIO_GCC_PCIE_CFG2_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_CFG2_GDSCR_ADDR,v) +#define HWIO_GCC_PCIE_CFG2_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_CFG2_GDSCR_ADDR,m,v,HWIO_GCC_PCIE_CFG2_GDSCR_IN) +#define HWIO_GCC_PCIE_CFG2_GDSCR_GDSC_MEM_PWRUP_ACK_OVERRIDE_BMSK 0x40000 +#define HWIO_GCC_PCIE_CFG2_GDSCR_GDSC_MEM_PWRUP_ACK_OVERRIDE_SHFT 0x12 +#define HWIO_GCC_PCIE_CFG2_GDSCR_GDSC_PWRDWN_ENABLE_ACK_OVERRIDE_BMSK 0x20000 +#define HWIO_GCC_PCIE_CFG2_GDSCR_GDSC_PWRDWN_ENABLE_ACK_OVERRIDE_SHFT 0x11 +#define HWIO_GCC_PCIE_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_BMSK 0x10000 +#define HWIO_GCC_PCIE_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_SHFT 0x10 +#define HWIO_GCC_PCIE_CFG2_GDSCR_DLY_MEM_PWR_UP_BMSK 0xf000 +#define HWIO_GCC_PCIE_CFG2_GDSCR_DLY_MEM_PWR_UP_SHFT 0xc +#define HWIO_GCC_PCIE_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_BMSK 0xf00 +#define HWIO_GCC_PCIE_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_SHFT 0x8 +#define HWIO_GCC_PCIE_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_BMSK 0xf0 +#define HWIO_GCC_PCIE_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_SHFT 0x4 +#define HWIO_GCC_PCIE_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_BMSK 0xf +#define HWIO_GCC_PCIE_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_SHFT 0x0 + +#define HWIO_GCC_PCIE_CFG3_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00033010) +#define HWIO_GCC_PCIE_CFG3_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00033010) +#define HWIO_GCC_PCIE_CFG3_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00033010) +#define HWIO_GCC_PCIE_CFG3_GDSCR_RMSK 0x7ffffff +#define HWIO_GCC_PCIE_CFG3_GDSCR_ATTR 0x3 +#define HWIO_GCC_PCIE_CFG3_GDSCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_CFG3_GDSCR_ADDR, HWIO_GCC_PCIE_CFG3_GDSCR_RMSK) +#define HWIO_GCC_PCIE_CFG3_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_CFG3_GDSCR_ADDR, m) +#define HWIO_GCC_PCIE_CFG3_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_CFG3_GDSCR_ADDR,v) +#define HWIO_GCC_PCIE_CFG3_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_CFG3_GDSCR_ADDR,m,v,HWIO_GCC_PCIE_CFG3_GDSCR_IN) +#define HWIO_GCC_PCIE_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_STATUS_BMSK 0x4000000 +#define HWIO_GCC_PCIE_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_STATUS_SHFT 0x1a +#define HWIO_GCC_PCIE_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_BMSK 0x2000000 +#define HWIO_GCC_PCIE_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_SHFT 0x19 +#define HWIO_GCC_PCIE_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_CFG3_GDSCR_DLY_ACCU_RED_SHIFTER_DONE_BMSK 0x1e00000 +#define HWIO_GCC_PCIE_CFG3_GDSCR_DLY_ACCU_RED_SHIFTER_DONE_SHFT 0x15 +#define HWIO_GCC_PCIE_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_BMSK 0x100000 +#define HWIO_GCC_PCIE_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_SHFT 0x14 +#define HWIO_GCC_PCIE_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_BMSK 0x80000 +#define HWIO_GCC_PCIE_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_SHFT 0x13 +#define HWIO_GCC_PCIE_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_BMSK 0x40000 +#define HWIO_GCC_PCIE_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_SHFT 0x12 +#define HWIO_GCC_PCIE_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_BMSK 0x20000 +#define HWIO_GCC_PCIE_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_SHFT 0x11 +#define HWIO_GCC_PCIE_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_BMSK 0x10000 +#define HWIO_GCC_PCIE_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_SHFT 0x10 +#define HWIO_GCC_PCIE_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_CFG3_GDSCR_GDSC_SPARE_CTRL_IN_BMSK 0xff00 +#define HWIO_GCC_PCIE_CFG3_GDSCR_GDSC_SPARE_CTRL_IN_SHFT 0x8 +#define HWIO_GCC_PCIE_CFG3_GDSCR_GDSC_SPARE_CTRL_OUT_BMSK 0xff +#define HWIO_GCC_PCIE_CFG3_GDSCR_GDSC_SPARE_CTRL_OUT_SHFT 0x0 + +#define HWIO_GCC_PCIE_CFG4_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00033014) +#define HWIO_GCC_PCIE_CFG4_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00033014) +#define HWIO_GCC_PCIE_CFG4_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00033014) +#define HWIO_GCC_PCIE_CFG4_GDSCR_RMSK 0xffffff +#define HWIO_GCC_PCIE_CFG4_GDSCR_ATTR 0x3 +#define HWIO_GCC_PCIE_CFG4_GDSCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_CFG4_GDSCR_ADDR, HWIO_GCC_PCIE_CFG4_GDSCR_RMSK) +#define HWIO_GCC_PCIE_CFG4_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_CFG4_GDSCR_ADDR, m) +#define HWIO_GCC_PCIE_CFG4_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_CFG4_GDSCR_ADDR,v) +#define HWIO_GCC_PCIE_CFG4_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_CFG4_GDSCR_ADDR,m,v,HWIO_GCC_PCIE_CFG4_GDSCR_IN) +#define HWIO_GCC_PCIE_CFG4_GDSCR_DLY_UNCLAMPIO_BMSK 0xf00000 +#define HWIO_GCC_PCIE_CFG4_GDSCR_DLY_UNCLAMPIO_SHFT 0x14 +#define HWIO_GCC_PCIE_CFG4_GDSCR_DLY_RESTOREFF_BMSK 0xf0000 +#define HWIO_GCC_PCIE_CFG4_GDSCR_DLY_RESTOREFF_SHFT 0x10 +#define HWIO_GCC_PCIE_CFG4_GDSCR_DLY_NORETAINFF_BMSK 0xf000 +#define HWIO_GCC_PCIE_CFG4_GDSCR_DLY_NORETAINFF_SHFT 0xc +#define HWIO_GCC_PCIE_CFG4_GDSCR_DLY_DEASSERTARES_BMSK 0xf00 +#define HWIO_GCC_PCIE_CFG4_GDSCR_DLY_DEASSERTARES_SHFT 0x8 +#define HWIO_GCC_PCIE_CFG4_GDSCR_DLY_CLAMPIO_BMSK 0xf0 +#define HWIO_GCC_PCIE_CFG4_GDSCR_DLY_CLAMPIO_SHFT 0x4 +#define HWIO_GCC_PCIE_CFG4_GDSCR_DLY_RETAINFF_BMSK 0xf +#define HWIO_GCC_PCIE_CFG4_GDSCR_DLY_RETAINFF_SHFT 0x0 + +#define HWIO_GCC_PCIE_SLV_Q2A_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00033018) +#define HWIO_GCC_PCIE_SLV_Q2A_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00033018) +#define HWIO_GCC_PCIE_SLV_Q2A_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00033018) +#define HWIO_GCC_PCIE_SLV_Q2A_AXI_CBCR_RMSK 0x81d0000e +#define HWIO_GCC_PCIE_SLV_Q2A_AXI_CBCR_ATTR 0x3 +#define HWIO_GCC_PCIE_SLV_Q2A_AXI_CBCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_SLV_Q2A_AXI_CBCR_ADDR, HWIO_GCC_PCIE_SLV_Q2A_AXI_CBCR_RMSK) +#define HWIO_GCC_PCIE_SLV_Q2A_AXI_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_SLV_Q2A_AXI_CBCR_ADDR, m) +#define HWIO_GCC_PCIE_SLV_Q2A_AXI_CBCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_SLV_Q2A_AXI_CBCR_ADDR,v) +#define HWIO_GCC_PCIE_SLV_Q2A_AXI_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_SLV_Q2A_AXI_CBCR_ADDR,m,v,HWIO_GCC_PCIE_SLV_Q2A_AXI_CBCR_IN) +#define HWIO_GCC_PCIE_SLV_Q2A_AXI_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_PCIE_SLV_Q2A_AXI_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_PCIE_SLV_Q2A_AXI_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_PCIE_SLV_Q2A_AXI_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_PCIE_SLV_Q2A_AXI_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_PCIE_SLV_Q2A_AXI_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_PCIE_SLV_Q2A_AXI_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_PCIE_SLV_Q2A_AXI_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_PCIE_SLV_Q2A_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_PCIE_SLV_Q2A_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_PCIE_SLV_Q2A_AXI_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_PCIE_SLV_Q2A_AXI_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_PCIE_SLV_Q2A_AXI_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_PCIE_SLV_Q2A_AXI_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_PCIE_SLV_Q2A_AXI_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_PCIE_SLV_Q2A_AXI_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_PCIE_SLV_Q2A_AXI_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_PCIE_SLV_Q2A_AXI_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_PCIE_SLV_Q2A_AXI_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_SLV_Q2A_AXI_CBCR_HW_CTL_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003301c) +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003301c) +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003301c) +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_RMSK 0x81d07ffe +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_ATTR 0x3 +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_SLV_AXI_CBCR_ADDR, HWIO_GCC_PCIE_SLV_AXI_CBCR_RMSK) +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_SLV_AXI_CBCR_ADDR, m) +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_SLV_AXI_CBCR_ADDR,v) +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_SLV_AXI_CBCR_ADDR,m,v,HWIO_GCC_PCIE_SLV_AXI_CBCR_IN) +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_WAKEUP_BMSK 0xf00 +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_WAKEUP_SHFT 0x8 +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_WAKEUP_CLOCK0_FVAL 0x0 +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_WAKEUP_CLOCK1_FVAL 0x1 +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_WAKEUP_CLOCK2_FVAL 0x2 +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_WAKEUP_CLOCK3_FVAL 0x3 +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_WAKEUP_CLOCK4_FVAL 0x4 +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_WAKEUP_CLOCK5_FVAL 0x5 +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_WAKEUP_CLOCK6_FVAL 0x6 +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_WAKEUP_CLOCK7_FVAL 0x7 +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_WAKEUP_CLOCK8_FVAL 0x8 +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_WAKEUP_CLOCK9_FVAL 0x9 +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_WAKEUP_CLOCK10_FVAL 0xa +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_WAKEUP_CLOCK11_FVAL 0xb +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_WAKEUP_CLOCK12_FVAL 0xc +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_WAKEUP_CLOCK13_FVAL 0xd +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_WAKEUP_CLOCK14_FVAL 0xe +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_WAKEUP_CLOCK15_FVAL 0xf +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_SLEEP_BMSK 0xf0 +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_SLEEP_SHFT 0x4 +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_SLEEP_CLOCK0_FVAL 0x0 +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_SLEEP_CLOCK1_FVAL 0x1 +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_SLEEP_CLOCK2_FVAL 0x2 +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_SLEEP_CLOCK3_FVAL 0x3 +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_SLEEP_CLOCK4_FVAL 0x4 +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_SLEEP_CLOCK5_FVAL 0x5 +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_SLEEP_CLOCK6_FVAL 0x6 +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_SLEEP_CLOCK7_FVAL 0x7 +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_SLEEP_CLOCK8_FVAL 0x8 +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_SLEEP_CLOCK9_FVAL 0x9 +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_SLEEP_CLOCK10_FVAL 0xa +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_SLEEP_CLOCK11_FVAL 0xb +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_SLEEP_CLOCK12_FVAL 0xc +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_SLEEP_CLOCK13_FVAL 0xd +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_SLEEP_CLOCK14_FVAL 0xe +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_SLEEP_CLOCK15_FVAL 0xf +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_SLV_AXI_CBCR_HW_CTL_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00033020) +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00033020) +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00033020) +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_RMSK 0xfffffffe +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_ATTR 0x3 +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_IN \ + in_dword_masked(HWIO_GCC_PCIE_SLV_AXI_SREGR_ADDR, HWIO_GCC_PCIE_SLV_AXI_SREGR_RMSK) +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_SLV_AXI_SREGR_ADDR, m) +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_SLV_AXI_SREGR_ADDR,v) +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_SLV_AXI_SREGR_ADDR,m,v,HWIO_GCC_PCIE_SLV_AXI_SREGR_IN) +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xff000000 +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xff0000 +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_SLV_AXI_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00033024) +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00033024) +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00033024) +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_RMSK 0x81d07ffe +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_ATTR 0x3 +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_MSTR_AXI_CBCR_ADDR, HWIO_GCC_PCIE_MSTR_AXI_CBCR_RMSK) +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_MSTR_AXI_CBCR_ADDR, m) +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_MSTR_AXI_CBCR_ADDR,v) +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_MSTR_AXI_CBCR_ADDR,m,v,HWIO_GCC_PCIE_MSTR_AXI_CBCR_IN) +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_WAKEUP_BMSK 0xf00 +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_WAKEUP_SHFT 0x8 +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_WAKEUP_CLOCK0_FVAL 0x0 +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_WAKEUP_CLOCK1_FVAL 0x1 +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_WAKEUP_CLOCK2_FVAL 0x2 +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_WAKEUP_CLOCK3_FVAL 0x3 +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_WAKEUP_CLOCK4_FVAL 0x4 +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_WAKEUP_CLOCK5_FVAL 0x5 +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_WAKEUP_CLOCK6_FVAL 0x6 +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_WAKEUP_CLOCK7_FVAL 0x7 +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_WAKEUP_CLOCK8_FVAL 0x8 +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_WAKEUP_CLOCK9_FVAL 0x9 +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_WAKEUP_CLOCK10_FVAL 0xa +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_WAKEUP_CLOCK11_FVAL 0xb +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_WAKEUP_CLOCK12_FVAL 0xc +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_WAKEUP_CLOCK13_FVAL 0xd +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_WAKEUP_CLOCK14_FVAL 0xe +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_WAKEUP_CLOCK15_FVAL 0xf +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_SLEEP_BMSK 0xf0 +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_SLEEP_SHFT 0x4 +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_SLEEP_CLOCK0_FVAL 0x0 +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_SLEEP_CLOCK1_FVAL 0x1 +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_SLEEP_CLOCK2_FVAL 0x2 +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_SLEEP_CLOCK3_FVAL 0x3 +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_SLEEP_CLOCK4_FVAL 0x4 +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_SLEEP_CLOCK5_FVAL 0x5 +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_SLEEP_CLOCK6_FVAL 0x6 +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_SLEEP_CLOCK7_FVAL 0x7 +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_SLEEP_CLOCK8_FVAL 0x8 +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_SLEEP_CLOCK9_FVAL 0x9 +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_SLEEP_CLOCK10_FVAL 0xa +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_SLEEP_CLOCK11_FVAL 0xb +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_SLEEP_CLOCK12_FVAL 0xc +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_SLEEP_CLOCK13_FVAL 0xd +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_SLEEP_CLOCK14_FVAL 0xe +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_SLEEP_CLOCK15_FVAL 0xf +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_MSTR_AXI_CBCR_HW_CTL_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00033028) +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00033028) +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00033028) +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_RMSK 0xfffffffe +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_ATTR 0x3 +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_IN \ + in_dword_masked(HWIO_GCC_PCIE_MSTR_AXI_SREGR_ADDR, HWIO_GCC_PCIE_MSTR_AXI_SREGR_RMSK) +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_MSTR_AXI_SREGR_ADDR, m) +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_MSTR_AXI_SREGR_ADDR,v) +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_MSTR_AXI_SREGR_ADDR,m,v,HWIO_GCC_PCIE_MSTR_AXI_SREGR_IN) +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xff000000 +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xff0000 +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_MSTR_AXI_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_CFG_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003302c) +#define HWIO_GCC_PCIE_CFG_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003302c) +#define HWIO_GCC_PCIE_CFG_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003302c) +#define HWIO_GCC_PCIE_CFG_AHB_CBCR_RMSK 0x81d0000e +#define HWIO_GCC_PCIE_CFG_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_PCIE_CFG_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_CFG_AHB_CBCR_ADDR, HWIO_GCC_PCIE_CFG_AHB_CBCR_RMSK) +#define HWIO_GCC_PCIE_CFG_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_CFG_AHB_CBCR_ADDR, m) +#define HWIO_GCC_PCIE_CFG_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_CFG_AHB_CBCR_ADDR,v) +#define HWIO_GCC_PCIE_CFG_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_CFG_AHB_CBCR_ADDR,m,v,HWIO_GCC_PCIE_CFG_AHB_CBCR_IN) +#define HWIO_GCC_PCIE_CFG_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_PCIE_CFG_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_PCIE_CFG_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_PCIE_CFG_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_PCIE_CFG_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_PCIE_CFG_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_PCIE_CFG_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_PCIE_CFG_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_PCIE_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_PCIE_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_PCIE_CFG_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_PCIE_CFG_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_PCIE_CFG_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_PCIE_CFG_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_PCIE_CFG_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_PCIE_CFG_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_PCIE_CFG_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_PCIE_CFG_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_PCIE_CFG_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_CFG_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_RCHNG_PHY_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00033030) +#define HWIO_GCC_PCIE_RCHNG_PHY_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00033030) +#define HWIO_GCC_PCIE_RCHNG_PHY_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00033030) +#define HWIO_GCC_PCIE_RCHNG_PHY_CBCR_RMSK 0x81c0000e +#define HWIO_GCC_PCIE_RCHNG_PHY_CBCR_ATTR 0x3 +#define HWIO_GCC_PCIE_RCHNG_PHY_CBCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_RCHNG_PHY_CBCR_ADDR, HWIO_GCC_PCIE_RCHNG_PHY_CBCR_RMSK) +#define HWIO_GCC_PCIE_RCHNG_PHY_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_RCHNG_PHY_CBCR_ADDR, m) +#define HWIO_GCC_PCIE_RCHNG_PHY_CBCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_RCHNG_PHY_CBCR_ADDR,v) +#define HWIO_GCC_PCIE_RCHNG_PHY_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_RCHNG_PHY_CBCR_ADDR,m,v,HWIO_GCC_PCIE_RCHNG_PHY_CBCR_IN) +#define HWIO_GCC_PCIE_RCHNG_PHY_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_PCIE_RCHNG_PHY_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_PCIE_RCHNG_PHY_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_PCIE_RCHNG_PHY_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_PCIE_RCHNG_PHY_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_PCIE_RCHNG_PHY_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_PCIE_RCHNG_PHY_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_PCIE_RCHNG_PHY_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_PCIE_RCHNG_PHY_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_PCIE_RCHNG_PHY_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_PCIE_RCHNG_PHY_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_PCIE_RCHNG_PHY_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_PCIE_RCHNG_PHY_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_PCIE_RCHNG_PHY_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_PCIE_RCHNG_PHY_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_PCIE_RCHNG_PHY_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_PCIE_RCHNG_PHY_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_RCHNG_PHY_CBCR_HW_CTL_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_AUX_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00033034) +#define HWIO_GCC_PCIE_AUX_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00033034) +#define HWIO_GCC_PCIE_AUX_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00033034) +#define HWIO_GCC_PCIE_AUX_CBCR_RMSK 0x81c0000e +#define HWIO_GCC_PCIE_AUX_CBCR_ATTR 0x3 +#define HWIO_GCC_PCIE_AUX_CBCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_AUX_CBCR_ADDR, HWIO_GCC_PCIE_AUX_CBCR_RMSK) +#define HWIO_GCC_PCIE_AUX_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_AUX_CBCR_ADDR, m) +#define HWIO_GCC_PCIE_AUX_CBCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_AUX_CBCR_ADDR,v) +#define HWIO_GCC_PCIE_AUX_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_AUX_CBCR_ADDR,m,v,HWIO_GCC_PCIE_AUX_CBCR_IN) +#define HWIO_GCC_PCIE_AUX_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_PCIE_AUX_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_PCIE_AUX_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_PCIE_AUX_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_PCIE_AUX_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_PCIE_AUX_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_PCIE_AUX_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_PCIE_AUX_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_PCIE_AUX_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_PCIE_AUX_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_PCIE_AUX_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_PCIE_AUX_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_PCIE_AUX_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_PCIE_AUX_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_PCIE_AUX_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_PCIE_AUX_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_PCIE_AUX_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_AUX_CBCR_HW_CTL_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_SLEEP_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00033038) +#define HWIO_GCC_PCIE_SLEEP_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00033038) +#define HWIO_GCC_PCIE_SLEEP_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00033038) +#define HWIO_GCC_PCIE_SLEEP_CBCR_RMSK 0x81c0000e +#define HWIO_GCC_PCIE_SLEEP_CBCR_ATTR 0x3 +#define HWIO_GCC_PCIE_SLEEP_CBCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_SLEEP_CBCR_ADDR, HWIO_GCC_PCIE_SLEEP_CBCR_RMSK) +#define HWIO_GCC_PCIE_SLEEP_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_SLEEP_CBCR_ADDR, m) +#define HWIO_GCC_PCIE_SLEEP_CBCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_SLEEP_CBCR_ADDR,v) +#define HWIO_GCC_PCIE_SLEEP_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_SLEEP_CBCR_ADDR,m,v,HWIO_GCC_PCIE_SLEEP_CBCR_IN) +#define HWIO_GCC_PCIE_SLEEP_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_PCIE_SLEEP_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_PCIE_SLEEP_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_PCIE_SLEEP_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_PCIE_SLEEP_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_PCIE_SLEEP_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_PCIE_SLEEP_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_PCIE_SLEEP_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_PCIE_SLEEP_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_PCIE_SLEEP_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_PCIE_SLEEP_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_PCIE_SLEEP_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_PCIE_SLEEP_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_PCIE_SLEEP_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_PCIE_SLEEP_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_PCIE_SLEEP_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_PCIE_SLEEP_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_SLEEP_CBCR_HW_CTL_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_PIPE_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003303c) +#define HWIO_GCC_PCIE_PIPE_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003303c) +#define HWIO_GCC_PCIE_PIPE_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003303c) +#define HWIO_GCC_PCIE_PIPE_CBCR_RMSK 0x81c07ffe +#define HWIO_GCC_PCIE_PIPE_CBCR_ATTR 0x3 +#define HWIO_GCC_PCIE_PIPE_CBCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_PIPE_CBCR_ADDR, HWIO_GCC_PCIE_PIPE_CBCR_RMSK) +#define HWIO_GCC_PCIE_PIPE_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_PIPE_CBCR_ADDR, m) +#define HWIO_GCC_PCIE_PIPE_CBCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_PIPE_CBCR_ADDR,v) +#define HWIO_GCC_PCIE_PIPE_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_PIPE_CBCR_ADDR,m,v,HWIO_GCC_PCIE_PIPE_CBCR_IN) +#define HWIO_GCC_PCIE_PIPE_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_PCIE_PIPE_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_PCIE_PIPE_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_PCIE_PIPE_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_PCIE_PIPE_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_PCIE_PIPE_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_PCIE_PIPE_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_PCIE_PIPE_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_PCIE_PIPE_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_PCIE_PIPE_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_PCIE_PIPE_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_PIPE_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_PIPE_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_PCIE_PIPE_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_PCIE_PIPE_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_PIPE_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_PIPE_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_PCIE_PIPE_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_PCIE_PIPE_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_PIPE_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_PIPE_CBCR_WAKEUP_BMSK 0xf00 +#define HWIO_GCC_PCIE_PIPE_CBCR_WAKEUP_SHFT 0x8 +#define HWIO_GCC_PCIE_PIPE_CBCR_WAKEUP_CLOCK0_FVAL 0x0 +#define HWIO_GCC_PCIE_PIPE_CBCR_WAKEUP_CLOCK1_FVAL 0x1 +#define HWIO_GCC_PCIE_PIPE_CBCR_WAKEUP_CLOCK2_FVAL 0x2 +#define HWIO_GCC_PCIE_PIPE_CBCR_WAKEUP_CLOCK3_FVAL 0x3 +#define HWIO_GCC_PCIE_PIPE_CBCR_WAKEUP_CLOCK4_FVAL 0x4 +#define HWIO_GCC_PCIE_PIPE_CBCR_WAKEUP_CLOCK5_FVAL 0x5 +#define HWIO_GCC_PCIE_PIPE_CBCR_WAKEUP_CLOCK6_FVAL 0x6 +#define HWIO_GCC_PCIE_PIPE_CBCR_WAKEUP_CLOCK7_FVAL 0x7 +#define HWIO_GCC_PCIE_PIPE_CBCR_WAKEUP_CLOCK8_FVAL 0x8 +#define HWIO_GCC_PCIE_PIPE_CBCR_WAKEUP_CLOCK9_FVAL 0x9 +#define HWIO_GCC_PCIE_PIPE_CBCR_WAKEUP_CLOCK10_FVAL 0xa +#define HWIO_GCC_PCIE_PIPE_CBCR_WAKEUP_CLOCK11_FVAL 0xb +#define HWIO_GCC_PCIE_PIPE_CBCR_WAKEUP_CLOCK12_FVAL 0xc +#define HWIO_GCC_PCIE_PIPE_CBCR_WAKEUP_CLOCK13_FVAL 0xd +#define HWIO_GCC_PCIE_PIPE_CBCR_WAKEUP_CLOCK14_FVAL 0xe +#define HWIO_GCC_PCIE_PIPE_CBCR_WAKEUP_CLOCK15_FVAL 0xf +#define HWIO_GCC_PCIE_PIPE_CBCR_SLEEP_BMSK 0xf0 +#define HWIO_GCC_PCIE_PIPE_CBCR_SLEEP_SHFT 0x4 +#define HWIO_GCC_PCIE_PIPE_CBCR_SLEEP_CLOCK0_FVAL 0x0 +#define HWIO_GCC_PCIE_PIPE_CBCR_SLEEP_CLOCK1_FVAL 0x1 +#define HWIO_GCC_PCIE_PIPE_CBCR_SLEEP_CLOCK2_FVAL 0x2 +#define HWIO_GCC_PCIE_PIPE_CBCR_SLEEP_CLOCK3_FVAL 0x3 +#define HWIO_GCC_PCIE_PIPE_CBCR_SLEEP_CLOCK4_FVAL 0x4 +#define HWIO_GCC_PCIE_PIPE_CBCR_SLEEP_CLOCK5_FVAL 0x5 +#define HWIO_GCC_PCIE_PIPE_CBCR_SLEEP_CLOCK6_FVAL 0x6 +#define HWIO_GCC_PCIE_PIPE_CBCR_SLEEP_CLOCK7_FVAL 0x7 +#define HWIO_GCC_PCIE_PIPE_CBCR_SLEEP_CLOCK8_FVAL 0x8 +#define HWIO_GCC_PCIE_PIPE_CBCR_SLEEP_CLOCK9_FVAL 0x9 +#define HWIO_GCC_PCIE_PIPE_CBCR_SLEEP_CLOCK10_FVAL 0xa +#define HWIO_GCC_PCIE_PIPE_CBCR_SLEEP_CLOCK11_FVAL 0xb +#define HWIO_GCC_PCIE_PIPE_CBCR_SLEEP_CLOCK12_FVAL 0xc +#define HWIO_GCC_PCIE_PIPE_CBCR_SLEEP_CLOCK13_FVAL 0xd +#define HWIO_GCC_PCIE_PIPE_CBCR_SLEEP_CLOCK14_FVAL 0xe +#define HWIO_GCC_PCIE_PIPE_CBCR_SLEEP_CLOCK15_FVAL 0xf +#define HWIO_GCC_PCIE_PIPE_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_PCIE_PIPE_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_PCIE_PIPE_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_PCIE_PIPE_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_PCIE_PIPE_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_PCIE_PIPE_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_PCIE_PIPE_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_PCIE_PIPE_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_PCIE_PIPE_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_PIPE_CBCR_HW_CTL_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_PIPE_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00033040) +#define HWIO_GCC_PCIE_PIPE_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00033040) +#define HWIO_GCC_PCIE_PIPE_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00033040) +#define HWIO_GCC_PCIE_PIPE_SREGR_RMSK 0xfffffffe +#define HWIO_GCC_PCIE_PIPE_SREGR_ATTR 0x3 +#define HWIO_GCC_PCIE_PIPE_SREGR_IN \ + in_dword_masked(HWIO_GCC_PCIE_PIPE_SREGR_ADDR, HWIO_GCC_PCIE_PIPE_SREGR_RMSK) +#define HWIO_GCC_PCIE_PIPE_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_PIPE_SREGR_ADDR, m) +#define HWIO_GCC_PCIE_PIPE_SREGR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_PIPE_SREGR_ADDR,v) +#define HWIO_GCC_PCIE_PIPE_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_PIPE_SREGR_ADDR,m,v,HWIO_GCC_PCIE_PIPE_SREGR_IN) +#define HWIO_GCC_PCIE_PIPE_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xff000000 +#define HWIO_GCC_PCIE_PIPE_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_PCIE_PIPE_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xff0000 +#define HWIO_GCC_PCIE_PIPE_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_PCIE_PIPE_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_PCIE_PIPE_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_PCIE_PIPE_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_PCIE_PIPE_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_PCIE_PIPE_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_PCIE_PIPE_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_PCIE_PIPE_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_PCIE_PIPE_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_PCIE_PIPE_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_PCIE_PIPE_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_PCIE_PIPE_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_PCIE_PIPE_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_PCIE_PIPE_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_PCIE_PIPE_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_PCIE_PIPE_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_PCIE_PIPE_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_PCIE_PIPE_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_PCIE_PIPE_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_PCIE_PIPE_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_PCIE_PIPE_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_PCIE_PIPE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_PCIE_PIPE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_PCIE_PIPE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_PCIE_PIPE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_PCIE_PIPE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_PCIE_PIPE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_PCIE_PIPE_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_PCIE_PIPE_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_PCIE_PIPE_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_PIPE_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_PIPE_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_PCIE_PIPE_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_PCIE_PIPE_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_PCIE_PIPE_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_PIPE_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_PCIE_PIPE_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_PCIE_PIPE_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_PCIE_PIPE_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_PCIE_PIPE_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_PCIE_PIPE_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_PCIE_PIPE_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_PCIE_PIPE_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_PCIE_PIPE_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_PCIE_PIPE_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_PCIE_PIPE_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_PCIE_PIPE_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_PCIE_PIPE_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_PCIE_PIPE_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_PCIE_PIPE_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_PCIE_PIPE_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_PCIE_PIPE_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_PCIE_PIPE_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_PCIE_PIPE_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_PIPE_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_AUX_PHY_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00033048) +#define HWIO_GCC_PCIE_AUX_PHY_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00033048) +#define HWIO_GCC_PCIE_AUX_PHY_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00033048) +#define HWIO_GCC_PCIE_AUX_PHY_CMD_RCGR_RMSK 0x800000f3 +#define HWIO_GCC_PCIE_AUX_PHY_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_PCIE_AUX_PHY_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_PCIE_AUX_PHY_CMD_RCGR_ADDR, HWIO_GCC_PCIE_AUX_PHY_CMD_RCGR_RMSK) +#define HWIO_GCC_PCIE_AUX_PHY_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_AUX_PHY_CMD_RCGR_ADDR, m) +#define HWIO_GCC_PCIE_AUX_PHY_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_AUX_PHY_CMD_RCGR_ADDR,v) +#define HWIO_GCC_PCIE_AUX_PHY_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_AUX_PHY_CMD_RCGR_ADDR,m,v,HWIO_GCC_PCIE_AUX_PHY_CMD_RCGR_IN) +#define HWIO_GCC_PCIE_AUX_PHY_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_PCIE_AUX_PHY_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_PCIE_AUX_PHY_CMD_RCGR_DIRTY_D_BMSK 0x80 +#define HWIO_GCC_PCIE_AUX_PHY_CMD_RCGR_DIRTY_D_SHFT 0x7 +#define HWIO_GCC_PCIE_AUX_PHY_CMD_RCGR_DIRTY_N_BMSK 0x40 +#define HWIO_GCC_PCIE_AUX_PHY_CMD_RCGR_DIRTY_N_SHFT 0x6 +#define HWIO_GCC_PCIE_AUX_PHY_CMD_RCGR_DIRTY_M_BMSK 0x20 +#define HWIO_GCC_PCIE_AUX_PHY_CMD_RCGR_DIRTY_M_SHFT 0x5 +#define HWIO_GCC_PCIE_AUX_PHY_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_PCIE_AUX_PHY_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_PCIE_AUX_PHY_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_PCIE_AUX_PHY_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_PCIE_AUX_PHY_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_AUX_PHY_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_AUX_PHY_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_PCIE_AUX_PHY_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_PCIE_AUX_PHY_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_AUX_PHY_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003304c) +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003304c) +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003304c) +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_RMSK 0x10371f +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_ADDR, HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_RMSK) +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_ADDR, m) +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_ADDR,v) +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_ADDR,m,v,HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_IN) +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_MODE_BMSK 0x3000 +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_MODE_SHFT 0xc +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_PCIE_AUX_PHY_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_PCIE_AUX_PHY_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00033050) +#define HWIO_GCC_PCIE_AUX_PHY_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00033050) +#define HWIO_GCC_PCIE_AUX_PHY_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00033050) +#define HWIO_GCC_PCIE_AUX_PHY_M_RMSK 0xffff +#define HWIO_GCC_PCIE_AUX_PHY_M_ATTR 0x3 +#define HWIO_GCC_PCIE_AUX_PHY_M_IN \ + in_dword_masked(HWIO_GCC_PCIE_AUX_PHY_M_ADDR, HWIO_GCC_PCIE_AUX_PHY_M_RMSK) +#define HWIO_GCC_PCIE_AUX_PHY_M_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_AUX_PHY_M_ADDR, m) +#define HWIO_GCC_PCIE_AUX_PHY_M_OUT(v) \ + out_dword(HWIO_GCC_PCIE_AUX_PHY_M_ADDR,v) +#define HWIO_GCC_PCIE_AUX_PHY_M_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_AUX_PHY_M_ADDR,m,v,HWIO_GCC_PCIE_AUX_PHY_M_IN) +#define HWIO_GCC_PCIE_AUX_PHY_M_M_BMSK 0xffff +#define HWIO_GCC_PCIE_AUX_PHY_M_M_SHFT 0x0 + +#define HWIO_GCC_PCIE_AUX_PHY_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00033054) +#define HWIO_GCC_PCIE_AUX_PHY_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00033054) +#define HWIO_GCC_PCIE_AUX_PHY_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00033054) +#define HWIO_GCC_PCIE_AUX_PHY_N_RMSK 0xffff +#define HWIO_GCC_PCIE_AUX_PHY_N_ATTR 0x3 +#define HWIO_GCC_PCIE_AUX_PHY_N_IN \ + in_dword_masked(HWIO_GCC_PCIE_AUX_PHY_N_ADDR, HWIO_GCC_PCIE_AUX_PHY_N_RMSK) +#define HWIO_GCC_PCIE_AUX_PHY_N_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_AUX_PHY_N_ADDR, m) +#define HWIO_GCC_PCIE_AUX_PHY_N_OUT(v) \ + out_dword(HWIO_GCC_PCIE_AUX_PHY_N_ADDR,v) +#define HWIO_GCC_PCIE_AUX_PHY_N_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_AUX_PHY_N_ADDR,m,v,HWIO_GCC_PCIE_AUX_PHY_N_IN) +#define HWIO_GCC_PCIE_AUX_PHY_N_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_PCIE_AUX_PHY_N_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_PCIE_AUX_PHY_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00033058) +#define HWIO_GCC_PCIE_AUX_PHY_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00033058) +#define HWIO_GCC_PCIE_AUX_PHY_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00033058) +#define HWIO_GCC_PCIE_AUX_PHY_D_RMSK 0xffff +#define HWIO_GCC_PCIE_AUX_PHY_D_ATTR 0x3 +#define HWIO_GCC_PCIE_AUX_PHY_D_IN \ + in_dword_masked(HWIO_GCC_PCIE_AUX_PHY_D_ADDR, HWIO_GCC_PCIE_AUX_PHY_D_RMSK) +#define HWIO_GCC_PCIE_AUX_PHY_D_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_AUX_PHY_D_ADDR, m) +#define HWIO_GCC_PCIE_AUX_PHY_D_OUT(v) \ + out_dword(HWIO_GCC_PCIE_AUX_PHY_D_ADDR,v) +#define HWIO_GCC_PCIE_AUX_PHY_D_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_AUX_PHY_D_ADDR,m,v,HWIO_GCC_PCIE_AUX_PHY_D_IN) +#define HWIO_GCC_PCIE_AUX_PHY_D_NOT_2D_BMSK 0xffff +#define HWIO_GCC_PCIE_AUX_PHY_D_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_PCIE_RCHNG_PHY_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00033064) +#define HWIO_GCC_PCIE_RCHNG_PHY_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00033064) +#define HWIO_GCC_PCIE_RCHNG_PHY_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00033064) +#define HWIO_GCC_PCIE_RCHNG_PHY_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_PCIE_RCHNG_PHY_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_PCIE_RCHNG_PHY_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_PCIE_RCHNG_PHY_CMD_RCGR_ADDR, HWIO_GCC_PCIE_RCHNG_PHY_CMD_RCGR_RMSK) +#define HWIO_GCC_PCIE_RCHNG_PHY_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_RCHNG_PHY_CMD_RCGR_ADDR, m) +#define HWIO_GCC_PCIE_RCHNG_PHY_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_RCHNG_PHY_CMD_RCGR_ADDR,v) +#define HWIO_GCC_PCIE_RCHNG_PHY_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_RCHNG_PHY_CMD_RCGR_ADDR,m,v,HWIO_GCC_PCIE_RCHNG_PHY_CMD_RCGR_IN) +#define HWIO_GCC_PCIE_RCHNG_PHY_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_PCIE_RCHNG_PHY_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_PCIE_RCHNG_PHY_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_PCIE_RCHNG_PHY_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_PCIE_RCHNG_PHY_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_PCIE_RCHNG_PHY_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_PCIE_RCHNG_PHY_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_RCHNG_PHY_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_RCHNG_PHY_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_PCIE_RCHNG_PHY_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_PCIE_RCHNG_PHY_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_RCHNG_PHY_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00033068) +#define HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00033068) +#define HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00033068) +#define HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_ADDR, HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_RMSK) +#define HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_ADDR, m) +#define HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_ADDR,v) +#define HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_ADDR,m,v,HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_IN) +#define HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_PCIE_RCHNG_PHY_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_PCIE_PHY_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00034000) +#define HWIO_GCC_PCIE_PHY_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00034000) +#define HWIO_GCC_PCIE_PHY_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00034000) +#define HWIO_GCC_PCIE_PHY_BCR_RMSK 0x1 +#define HWIO_GCC_PCIE_PHY_BCR_ATTR 0x3 +#define HWIO_GCC_PCIE_PHY_BCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_PHY_BCR_ADDR, HWIO_GCC_PCIE_PHY_BCR_RMSK) +#define HWIO_GCC_PCIE_PHY_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_PHY_BCR_ADDR, m) +#define HWIO_GCC_PCIE_PHY_BCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_PHY_BCR_ADDR,v) +#define HWIO_GCC_PCIE_PHY_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_PHY_BCR_ADDR,m,v,HWIO_GCC_PCIE_PHY_BCR_IN) +#define HWIO_GCC_PCIE_PHY_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_PCIE_PHY_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_PCIE_PHY_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_PHY_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_VS_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00035000) +#define HWIO_GCC_VS_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00035000) +#define HWIO_GCC_VS_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00035000) +#define HWIO_GCC_VS_BCR_RMSK 0x1 +#define HWIO_GCC_VS_BCR_ATTR 0x3 +#define HWIO_GCC_VS_BCR_IN \ + in_dword_masked(HWIO_GCC_VS_BCR_ADDR, HWIO_GCC_VS_BCR_RMSK) +#define HWIO_GCC_VS_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_VS_BCR_ADDR, m) +#define HWIO_GCC_VS_BCR_OUT(v) \ + out_dword(HWIO_GCC_VS_BCR_ADDR,v) +#define HWIO_GCC_VS_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_VS_BCR_ADDR,m,v,HWIO_GCC_VS_BCR_IN) +#define HWIO_GCC_VS_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_VS_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_VS_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_VS_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_VDDCX_VS_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00035004) +#define HWIO_GCC_VDDCX_VS_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00035004) +#define HWIO_GCC_VDDCX_VS_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00035004) +#define HWIO_GCC_VDDCX_VS_CBCR_RMSK 0x81c0000f +#define HWIO_GCC_VDDCX_VS_CBCR_ATTR 0x3 +#define HWIO_GCC_VDDCX_VS_CBCR_IN \ + in_dword_masked(HWIO_GCC_VDDCX_VS_CBCR_ADDR, HWIO_GCC_VDDCX_VS_CBCR_RMSK) +#define HWIO_GCC_VDDCX_VS_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_VDDCX_VS_CBCR_ADDR, m) +#define HWIO_GCC_VDDCX_VS_CBCR_OUT(v) \ + out_dword(HWIO_GCC_VDDCX_VS_CBCR_ADDR,v) +#define HWIO_GCC_VDDCX_VS_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_VDDCX_VS_CBCR_ADDR,m,v,HWIO_GCC_VDDCX_VS_CBCR_IN) +#define HWIO_GCC_VDDCX_VS_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_VDDCX_VS_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_VDDCX_VS_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_VDDCX_VS_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_VDDCX_VS_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_VDDCX_VS_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_VDDCX_VS_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_VDDCX_VS_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_VDDCX_VS_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_VDDCX_VS_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_VDDCX_VS_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_VDDCX_VS_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_VDDCX_VS_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_VDDCX_VS_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_VDDCX_VS_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_VDDCX_VS_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_VDDCX_VS_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_VDDCX_VS_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_VDDCX_VS_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_VDDCX_VS_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_VDDCX_VS_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_VDDCX_VS_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_VDDMX_VS_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00035008) +#define HWIO_GCC_VDDMX_VS_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00035008) +#define HWIO_GCC_VDDMX_VS_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00035008) +#define HWIO_GCC_VDDMX_VS_CBCR_RMSK 0x81c0000f +#define HWIO_GCC_VDDMX_VS_CBCR_ATTR 0x3 +#define HWIO_GCC_VDDMX_VS_CBCR_IN \ + in_dword_masked(HWIO_GCC_VDDMX_VS_CBCR_ADDR, HWIO_GCC_VDDMX_VS_CBCR_RMSK) +#define HWIO_GCC_VDDMX_VS_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_VDDMX_VS_CBCR_ADDR, m) +#define HWIO_GCC_VDDMX_VS_CBCR_OUT(v) \ + out_dword(HWIO_GCC_VDDMX_VS_CBCR_ADDR,v) +#define HWIO_GCC_VDDMX_VS_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_VDDMX_VS_CBCR_ADDR,m,v,HWIO_GCC_VDDMX_VS_CBCR_IN) +#define HWIO_GCC_VDDMX_VS_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_VDDMX_VS_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_VDDMX_VS_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_VDDMX_VS_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_VDDMX_VS_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_VDDMX_VS_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_VDDMX_VS_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_VDDMX_VS_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_VDDMX_VS_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_VDDMX_VS_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_VDDMX_VS_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_VDDMX_VS_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_VDDMX_VS_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_VDDMX_VS_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_VDDMX_VS_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_VDDMX_VS_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_VDDMX_VS_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_VDDMX_VS_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_VDDMX_VS_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_VDDMX_VS_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_VDDMX_VS_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_VDDMX_VS_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_VDDA_VS_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003500c) +#define HWIO_GCC_VDDA_VS_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003500c) +#define HWIO_GCC_VDDA_VS_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003500c) +#define HWIO_GCC_VDDA_VS_CBCR_RMSK 0x81c0000f +#define HWIO_GCC_VDDA_VS_CBCR_ATTR 0x3 +#define HWIO_GCC_VDDA_VS_CBCR_IN \ + in_dword_masked(HWIO_GCC_VDDA_VS_CBCR_ADDR, HWIO_GCC_VDDA_VS_CBCR_RMSK) +#define HWIO_GCC_VDDA_VS_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_VDDA_VS_CBCR_ADDR, m) +#define HWIO_GCC_VDDA_VS_CBCR_OUT(v) \ + out_dword(HWIO_GCC_VDDA_VS_CBCR_ADDR,v) +#define HWIO_GCC_VDDA_VS_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_VDDA_VS_CBCR_ADDR,m,v,HWIO_GCC_VDDA_VS_CBCR_IN) +#define HWIO_GCC_VDDA_VS_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_VDDA_VS_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_VDDA_VS_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_VDDA_VS_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_VDDA_VS_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_VDDA_VS_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_VDDA_VS_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_VDDA_VS_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_VDDA_VS_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_VDDA_VS_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_VDDA_VS_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_VDDA_VS_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_VDDA_VS_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_VDDA_VS_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_VDDA_VS_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_VDDA_VS_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_VDDA_VS_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_VDDA_VS_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_VDDA_VS_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_VDDA_VS_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_VDDA_VS_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_VDDA_VS_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_VDDMXC_VS_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00035010) +#define HWIO_GCC_VDDMXC_VS_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00035010) +#define HWIO_GCC_VDDMXC_VS_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00035010) +#define HWIO_GCC_VDDMXC_VS_CBCR_RMSK 0x81c0000f +#define HWIO_GCC_VDDMXC_VS_CBCR_ATTR 0x3 +#define HWIO_GCC_VDDMXC_VS_CBCR_IN \ + in_dword_masked(HWIO_GCC_VDDMXC_VS_CBCR_ADDR, HWIO_GCC_VDDMXC_VS_CBCR_RMSK) +#define HWIO_GCC_VDDMXC_VS_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_VDDMXC_VS_CBCR_ADDR, m) +#define HWIO_GCC_VDDMXC_VS_CBCR_OUT(v) \ + out_dword(HWIO_GCC_VDDMXC_VS_CBCR_ADDR,v) +#define HWIO_GCC_VDDMXC_VS_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_VDDMXC_VS_CBCR_ADDR,m,v,HWIO_GCC_VDDMXC_VS_CBCR_IN) +#define HWIO_GCC_VDDMXC_VS_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_VDDMXC_VS_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_VDDMXC_VS_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_VDDMXC_VS_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_VDDMXC_VS_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_VDDMXC_VS_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_VDDMXC_VS_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_VDDMXC_VS_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_VDDMXC_VS_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_VDDMXC_VS_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_VDDMXC_VS_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_VDDMXC_VS_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_VDDMXC_VS_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_VDDMXC_VS_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_VDDMXC_VS_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_VDDMXC_VS_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_VDDMXC_VS_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_VDDMXC_VS_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_VDDMXC_VS_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_VDDMXC_VS_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_VDDMXC_VS_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_VDDMXC_VS_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_VS_CTRL_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00035014) +#define HWIO_GCC_VS_CTRL_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00035014) +#define HWIO_GCC_VS_CTRL_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00035014) +#define HWIO_GCC_VS_CTRL_CBCR_RMSK 0x81c0000f +#define HWIO_GCC_VS_CTRL_CBCR_ATTR 0x3 +#define HWIO_GCC_VS_CTRL_CBCR_IN \ + in_dword_masked(HWIO_GCC_VS_CTRL_CBCR_ADDR, HWIO_GCC_VS_CTRL_CBCR_RMSK) +#define HWIO_GCC_VS_CTRL_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_VS_CTRL_CBCR_ADDR, m) +#define HWIO_GCC_VS_CTRL_CBCR_OUT(v) \ + out_dword(HWIO_GCC_VS_CTRL_CBCR_ADDR,v) +#define HWIO_GCC_VS_CTRL_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_VS_CTRL_CBCR_ADDR,m,v,HWIO_GCC_VS_CTRL_CBCR_IN) +#define HWIO_GCC_VS_CTRL_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_VS_CTRL_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_VS_CTRL_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_VS_CTRL_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_VS_CTRL_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_VS_CTRL_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_VS_CTRL_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_VS_CTRL_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_VS_CTRL_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_VS_CTRL_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_VS_CTRL_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_VS_CTRL_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_VS_CTRL_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_VS_CTRL_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_VS_CTRL_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_VS_CTRL_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_VS_CTRL_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_VS_CTRL_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_VS_CTRL_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_VS_CTRL_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_VS_CTRL_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_VS_CTRL_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_VS_CTRL_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00035018) +#define HWIO_GCC_VS_CTRL_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00035018) +#define HWIO_GCC_VS_CTRL_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00035018) +#define HWIO_GCC_VS_CTRL_AHB_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_VS_CTRL_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_VS_CTRL_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_VS_CTRL_AHB_CBCR_ADDR, HWIO_GCC_VS_CTRL_AHB_CBCR_RMSK) +#define HWIO_GCC_VS_CTRL_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_VS_CTRL_AHB_CBCR_ADDR, m) +#define HWIO_GCC_VS_CTRL_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_VS_CTRL_AHB_CBCR_ADDR,v) +#define HWIO_GCC_VS_CTRL_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_VS_CTRL_AHB_CBCR_ADDR,m,v,HWIO_GCC_VS_CTRL_AHB_CBCR_IN) +#define HWIO_GCC_VS_CTRL_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_VS_CTRL_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_VS_CTRL_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_VS_CTRL_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_VS_CTRL_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_VS_CTRL_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_VS_CTRL_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_VS_CTRL_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_VS_CTRL_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_VS_CTRL_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_VS_CTRL_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_VS_CTRL_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_VS_CTRL_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_VS_CTRL_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_VS_CTRL_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_VS_CTRL_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_VS_CTRL_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_VS_CTRL_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_VS_CTRL_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_VS_CTRL_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_VS_CTRL_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_VS_CTRL_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_VS_CTRL_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_VS_CTRL_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_VSENSOR_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003501c) +#define HWIO_GCC_VSENSOR_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003501c) +#define HWIO_GCC_VSENSOR_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003501c) +#define HWIO_GCC_VSENSOR_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_VSENSOR_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_VSENSOR_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_VSENSOR_CMD_RCGR_ADDR, HWIO_GCC_VSENSOR_CMD_RCGR_RMSK) +#define HWIO_GCC_VSENSOR_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_VSENSOR_CMD_RCGR_ADDR, m) +#define HWIO_GCC_VSENSOR_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_VSENSOR_CMD_RCGR_ADDR,v) +#define HWIO_GCC_VSENSOR_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_VSENSOR_CMD_RCGR_ADDR,m,v,HWIO_GCC_VSENSOR_CMD_RCGR_IN) +#define HWIO_GCC_VSENSOR_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_VSENSOR_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_VSENSOR_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_VSENSOR_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_VSENSOR_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_VSENSOR_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_VSENSOR_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_VSENSOR_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_VSENSOR_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_VSENSOR_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_VSENSOR_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_VSENSOR_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_VSENSOR_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00035020) +#define HWIO_GCC_VSENSOR_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00035020) +#define HWIO_GCC_VSENSOR_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00035020) +#define HWIO_GCC_VSENSOR_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_VSENSOR_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_VSENSOR_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_VSENSOR_CFG_RCGR_ADDR, HWIO_GCC_VSENSOR_CFG_RCGR_RMSK) +#define HWIO_GCC_VSENSOR_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_VSENSOR_CFG_RCGR_ADDR, m) +#define HWIO_GCC_VSENSOR_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_VSENSOR_CFG_RCGR_ADDR,v) +#define HWIO_GCC_VSENSOR_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_VSENSOR_CFG_RCGR_ADDR,m,v,HWIO_GCC_VSENSOR_CFG_RCGR_IN) +#define HWIO_GCC_VSENSOR_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_VSENSOR_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_VSENSOR_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_VSENSOR_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_VSENSOR_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_VSENSOR_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_VSENSOR_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_VSENSOR_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_VS_CTRL_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00035034) +#define HWIO_GCC_VS_CTRL_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00035034) +#define HWIO_GCC_VS_CTRL_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00035034) +#define HWIO_GCC_VS_CTRL_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_VS_CTRL_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_VS_CTRL_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_VS_CTRL_CMD_RCGR_ADDR, HWIO_GCC_VS_CTRL_CMD_RCGR_RMSK) +#define HWIO_GCC_VS_CTRL_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_VS_CTRL_CMD_RCGR_ADDR, m) +#define HWIO_GCC_VS_CTRL_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_VS_CTRL_CMD_RCGR_ADDR,v) +#define HWIO_GCC_VS_CTRL_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_VS_CTRL_CMD_RCGR_ADDR,m,v,HWIO_GCC_VS_CTRL_CMD_RCGR_IN) +#define HWIO_GCC_VS_CTRL_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_VS_CTRL_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_VS_CTRL_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_VS_CTRL_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_VS_CTRL_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_VS_CTRL_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_VS_CTRL_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_VS_CTRL_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_VS_CTRL_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_VS_CTRL_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_VS_CTRL_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_VS_CTRL_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_VS_CTRL_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00035038) +#define HWIO_GCC_VS_CTRL_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00035038) +#define HWIO_GCC_VS_CTRL_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00035038) +#define HWIO_GCC_VS_CTRL_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_VS_CTRL_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_VS_CTRL_CFG_RCGR_ADDR, HWIO_GCC_VS_CTRL_CFG_RCGR_RMSK) +#define HWIO_GCC_VS_CTRL_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_VS_CTRL_CFG_RCGR_ADDR, m) +#define HWIO_GCC_VS_CTRL_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_VS_CTRL_CFG_RCGR_ADDR,v) +#define HWIO_GCC_VS_CTRL_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_VS_CTRL_CFG_RCGR_ADDR,m,v,HWIO_GCC_VS_CTRL_CFG_RCGR_IN) +#define HWIO_GCC_VS_CTRL_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_MSS_VS_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003504c) +#define HWIO_GCC_MSS_VS_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003504c) +#define HWIO_GCC_MSS_VS_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003504c) +#define HWIO_GCC_MSS_VS_CBCR_RMSK 0x81c0000f +#define HWIO_GCC_MSS_VS_CBCR_ATTR 0x3 +#define HWIO_GCC_MSS_VS_CBCR_IN \ + in_dword_masked(HWIO_GCC_MSS_VS_CBCR_ADDR, HWIO_GCC_MSS_VS_CBCR_RMSK) +#define HWIO_GCC_MSS_VS_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_VS_CBCR_ADDR, m) +#define HWIO_GCC_MSS_VS_CBCR_OUT(v) \ + out_dword(HWIO_GCC_MSS_VS_CBCR_ADDR,v) +#define HWIO_GCC_MSS_VS_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_VS_CBCR_ADDR,m,v,HWIO_GCC_MSS_VS_CBCR_IN) +#define HWIO_GCC_MSS_VS_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_MSS_VS_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_MSS_VS_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_MSS_VS_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_MSS_VS_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_MSS_VS_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_MSS_VS_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_MSS_VS_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_MSS_VS_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_MSS_VS_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_MSS_VS_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_MSS_VS_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_MSS_VS_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_MSS_VS_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_MSS_VS_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_MSS_VS_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_MSS_VS_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_VS_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_VS_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_MSS_VS_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_MSS_VS_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_VS_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_DCC_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00037000) +#define HWIO_GCC_DCC_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00037000) +#define HWIO_GCC_DCC_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00037000) +#define HWIO_GCC_DCC_BCR_RMSK 0x1 +#define HWIO_GCC_DCC_BCR_ATTR 0x3 +#define HWIO_GCC_DCC_BCR_IN \ + in_dword_masked(HWIO_GCC_DCC_BCR_ADDR, HWIO_GCC_DCC_BCR_RMSK) +#define HWIO_GCC_DCC_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_DCC_BCR_ADDR, m) +#define HWIO_GCC_DCC_BCR_OUT(v) \ + out_dword(HWIO_GCC_DCC_BCR_ADDR,v) +#define HWIO_GCC_DCC_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DCC_BCR_ADDR,m,v,HWIO_GCC_DCC_BCR_IN) +#define HWIO_GCC_DCC_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_DCC_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_DCC_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_DCC_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_DCC_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00037004) +#define HWIO_GCC_DCC_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00037004) +#define HWIO_GCC_DCC_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00037004) +#define HWIO_GCC_DCC_AHB_CBCR_RMSK 0x81d07fff +#define HWIO_GCC_DCC_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_DCC_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_DCC_AHB_CBCR_ADDR, HWIO_GCC_DCC_AHB_CBCR_RMSK) +#define HWIO_GCC_DCC_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_DCC_AHB_CBCR_ADDR, m) +#define HWIO_GCC_DCC_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_DCC_AHB_CBCR_ADDR,v) +#define HWIO_GCC_DCC_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DCC_AHB_CBCR_ADDR,m,v,HWIO_GCC_DCC_AHB_CBCR_IN) +#define HWIO_GCC_DCC_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_DCC_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_DCC_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_DCC_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_DCC_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_DCC_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_DCC_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_DCC_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_DCC_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_DCC_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_DCC_AHB_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_DCC_AHB_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_DCC_AHB_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DCC_AHB_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_DCC_AHB_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_DCC_AHB_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_DCC_AHB_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DCC_AHB_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_DCC_AHB_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_DCC_AHB_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_DCC_AHB_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DCC_AHB_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_DCC_AHB_CBCR_WAKEUP_BMSK 0xf00 +#define HWIO_GCC_DCC_AHB_CBCR_WAKEUP_SHFT 0x8 +#define HWIO_GCC_DCC_AHB_CBCR_WAKEUP_CLOCK0_FVAL 0x0 +#define HWIO_GCC_DCC_AHB_CBCR_WAKEUP_CLOCK1_FVAL 0x1 +#define HWIO_GCC_DCC_AHB_CBCR_WAKEUP_CLOCK2_FVAL 0x2 +#define HWIO_GCC_DCC_AHB_CBCR_WAKEUP_CLOCK3_FVAL 0x3 +#define HWIO_GCC_DCC_AHB_CBCR_WAKEUP_CLOCK4_FVAL 0x4 +#define HWIO_GCC_DCC_AHB_CBCR_WAKEUP_CLOCK5_FVAL 0x5 +#define HWIO_GCC_DCC_AHB_CBCR_WAKEUP_CLOCK6_FVAL 0x6 +#define HWIO_GCC_DCC_AHB_CBCR_WAKEUP_CLOCK7_FVAL 0x7 +#define HWIO_GCC_DCC_AHB_CBCR_WAKEUP_CLOCK8_FVAL 0x8 +#define HWIO_GCC_DCC_AHB_CBCR_WAKEUP_CLOCK9_FVAL 0x9 +#define HWIO_GCC_DCC_AHB_CBCR_WAKEUP_CLOCK10_FVAL 0xa +#define HWIO_GCC_DCC_AHB_CBCR_WAKEUP_CLOCK11_FVAL 0xb +#define HWIO_GCC_DCC_AHB_CBCR_WAKEUP_CLOCK12_FVAL 0xc +#define HWIO_GCC_DCC_AHB_CBCR_WAKEUP_CLOCK13_FVAL 0xd +#define HWIO_GCC_DCC_AHB_CBCR_WAKEUP_CLOCK14_FVAL 0xe +#define HWIO_GCC_DCC_AHB_CBCR_WAKEUP_CLOCK15_FVAL 0xf +#define HWIO_GCC_DCC_AHB_CBCR_SLEEP_BMSK 0xf0 +#define HWIO_GCC_DCC_AHB_CBCR_SLEEP_SHFT 0x4 +#define HWIO_GCC_DCC_AHB_CBCR_SLEEP_CLOCK0_FVAL 0x0 +#define HWIO_GCC_DCC_AHB_CBCR_SLEEP_CLOCK1_FVAL 0x1 +#define HWIO_GCC_DCC_AHB_CBCR_SLEEP_CLOCK2_FVAL 0x2 +#define HWIO_GCC_DCC_AHB_CBCR_SLEEP_CLOCK3_FVAL 0x3 +#define HWIO_GCC_DCC_AHB_CBCR_SLEEP_CLOCK4_FVAL 0x4 +#define HWIO_GCC_DCC_AHB_CBCR_SLEEP_CLOCK5_FVAL 0x5 +#define HWIO_GCC_DCC_AHB_CBCR_SLEEP_CLOCK6_FVAL 0x6 +#define HWIO_GCC_DCC_AHB_CBCR_SLEEP_CLOCK7_FVAL 0x7 +#define HWIO_GCC_DCC_AHB_CBCR_SLEEP_CLOCK8_FVAL 0x8 +#define HWIO_GCC_DCC_AHB_CBCR_SLEEP_CLOCK9_FVAL 0x9 +#define HWIO_GCC_DCC_AHB_CBCR_SLEEP_CLOCK10_FVAL 0xa +#define HWIO_GCC_DCC_AHB_CBCR_SLEEP_CLOCK11_FVAL 0xb +#define HWIO_GCC_DCC_AHB_CBCR_SLEEP_CLOCK12_FVAL 0xc +#define HWIO_GCC_DCC_AHB_CBCR_SLEEP_CLOCK13_FVAL 0xd +#define HWIO_GCC_DCC_AHB_CBCR_SLEEP_CLOCK14_FVAL 0xe +#define HWIO_GCC_DCC_AHB_CBCR_SLEEP_CLOCK15_FVAL 0xf +#define HWIO_GCC_DCC_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_DCC_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_DCC_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_DCC_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_DCC_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_DCC_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_DCC_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_DCC_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_DCC_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_DCC_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_DCC_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_DCC_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_DCC_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DCC_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_DCC_AHB_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00037008) +#define HWIO_GCC_DCC_AHB_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00037008) +#define HWIO_GCC_DCC_AHB_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00037008) +#define HWIO_GCC_DCC_AHB_SREGR_RMSK 0xfffffffe +#define HWIO_GCC_DCC_AHB_SREGR_ATTR 0x3 +#define HWIO_GCC_DCC_AHB_SREGR_IN \ + in_dword_masked(HWIO_GCC_DCC_AHB_SREGR_ADDR, HWIO_GCC_DCC_AHB_SREGR_RMSK) +#define HWIO_GCC_DCC_AHB_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_DCC_AHB_SREGR_ADDR, m) +#define HWIO_GCC_DCC_AHB_SREGR_OUT(v) \ + out_dword(HWIO_GCC_DCC_AHB_SREGR_ADDR,v) +#define HWIO_GCC_DCC_AHB_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DCC_AHB_SREGR_ADDR,m,v,HWIO_GCC_DCC_AHB_SREGR_IN) +#define HWIO_GCC_DCC_AHB_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xff000000 +#define HWIO_GCC_DCC_AHB_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_DCC_AHB_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xff0000 +#define HWIO_GCC_DCC_AHB_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_DCC_AHB_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_DCC_AHB_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_DCC_AHB_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_DCC_AHB_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_DCC_AHB_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_DCC_AHB_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_DCC_AHB_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_DCC_AHB_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_DCC_AHB_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_DCC_AHB_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_DCC_AHB_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_DCC_AHB_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_DCC_AHB_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_DCC_AHB_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_DCC_AHB_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_DCC_AHB_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_DCC_AHB_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_DCC_AHB_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_DCC_AHB_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_DCC_AHB_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_DCC_AHB_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_DCC_AHB_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_DCC_AHB_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_DCC_AHB_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_DCC_AHB_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_DCC_AHB_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_DCC_AHB_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_DCC_AHB_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_DCC_AHB_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DCC_AHB_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_DCC_AHB_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_DCC_AHB_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_DCC_AHB_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_DCC_AHB_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_DCC_AHB_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_DCC_AHB_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_DCC_AHB_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_DCC_AHB_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_DCC_AHB_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_DCC_AHB_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_DCC_AHB_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_DCC_AHB_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_DCC_AHB_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_DCC_AHB_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_DCC_AHB_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_DCC_AHB_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_DCC_AHB_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_DCC_AHB_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_DCC_AHB_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_DCC_AHB_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_DCC_AHB_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_DCC_AHB_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_DCC_AHB_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_DCC_AHB_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_IPA_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038000) +#define HWIO_GCC_IPA_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038000) +#define HWIO_GCC_IPA_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038000) +#define HWIO_GCC_IPA_BCR_RMSK 0x1 +#define HWIO_GCC_IPA_BCR_ATTR 0x3 +#define HWIO_GCC_IPA_BCR_IN \ + in_dword_masked(HWIO_GCC_IPA_BCR_ADDR, HWIO_GCC_IPA_BCR_RMSK) +#define HWIO_GCC_IPA_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_IPA_BCR_ADDR, m) +#define HWIO_GCC_IPA_BCR_OUT(v) \ + out_dword(HWIO_GCC_IPA_BCR_ADDR,v) +#define HWIO_GCC_IPA_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_IPA_BCR_ADDR,m,v,HWIO_GCC_IPA_BCR_IN) +#define HWIO_GCC_IPA_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_IPA_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_IPA_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_IPA_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038004) +#define HWIO_GCC_IPA_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038004) +#define HWIO_GCC_IPA_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038004) +#define HWIO_GCC_IPA_GDSCR_RMSK 0xf8ffffff +#define HWIO_GCC_IPA_GDSCR_ATTR 0x3 +#define HWIO_GCC_IPA_GDSCR_IN \ + in_dword_masked(HWIO_GCC_IPA_GDSCR_ADDR, HWIO_GCC_IPA_GDSCR_RMSK) +#define HWIO_GCC_IPA_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_IPA_GDSCR_ADDR, m) +#define HWIO_GCC_IPA_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_IPA_GDSCR_ADDR,v) +#define HWIO_GCC_IPA_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_IPA_GDSCR_ADDR,m,v,HWIO_GCC_IPA_GDSCR_IN) +#define HWIO_GCC_IPA_GDSCR_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_IPA_GDSCR_PWR_ON_SHFT 0x1f +#define HWIO_GCC_IPA_GDSCR_GDSC_STATE_BMSK 0x78000000 +#define HWIO_GCC_IPA_GDSCR_GDSC_STATE_SHFT 0x1b +#define HWIO_GCC_IPA_GDSCR_EN_REST_WAIT_BMSK 0xf00000 +#define HWIO_GCC_IPA_GDSCR_EN_REST_WAIT_SHFT 0x14 +#define HWIO_GCC_IPA_GDSCR_EN_FEW_WAIT_BMSK 0xf0000 +#define HWIO_GCC_IPA_GDSCR_EN_FEW_WAIT_SHFT 0x10 +#define HWIO_GCC_IPA_GDSCR_CLK_DIS_WAIT_BMSK 0xf000 +#define HWIO_GCC_IPA_GDSCR_CLK_DIS_WAIT_SHFT 0xc +#define HWIO_GCC_IPA_GDSCR_RETAIN_FF_ENABLE_BMSK 0x800 +#define HWIO_GCC_IPA_GDSCR_RETAIN_FF_ENABLE_SHFT 0xb +#define HWIO_GCC_IPA_GDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_GDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPA_GDSCR_RESTORE_BMSK 0x400 +#define HWIO_GCC_IPA_GDSCR_RESTORE_SHFT 0xa +#define HWIO_GCC_IPA_GDSCR_RESTORE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_GDSCR_RESTORE_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPA_GDSCR_SAVE_BMSK 0x200 +#define HWIO_GCC_IPA_GDSCR_SAVE_SHFT 0x9 +#define HWIO_GCC_IPA_GDSCR_SAVE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_GDSCR_SAVE_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPA_GDSCR_RETAIN_BMSK 0x100 +#define HWIO_GCC_IPA_GDSCR_RETAIN_SHFT 0x8 +#define HWIO_GCC_IPA_GDSCR_RETAIN_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_GDSCR_RETAIN_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPA_GDSCR_EN_REST_BMSK 0x80 +#define HWIO_GCC_IPA_GDSCR_EN_REST_SHFT 0x7 +#define HWIO_GCC_IPA_GDSCR_EN_REST_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_GDSCR_EN_REST_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPA_GDSCR_EN_FEW_BMSK 0x40 +#define HWIO_GCC_IPA_GDSCR_EN_FEW_SHFT 0x6 +#define HWIO_GCC_IPA_GDSCR_EN_FEW_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_GDSCR_EN_FEW_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPA_GDSCR_CLAMP_IO_BMSK 0x20 +#define HWIO_GCC_IPA_GDSCR_CLAMP_IO_SHFT 0x5 +#define HWIO_GCC_IPA_GDSCR_CLAMP_IO_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_GDSCR_CLAMP_IO_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPA_GDSCR_CLK_DISABLE_BMSK 0x10 +#define HWIO_GCC_IPA_GDSCR_CLK_DISABLE_SHFT 0x4 +#define HWIO_GCC_IPA_GDSCR_CLK_DISABLE_CLK_NOT_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_GDSCR_CLK_DISABLE_CLK_IS_DISABLE_FVAL 0x1 +#define HWIO_GCC_IPA_GDSCR_PD_ARES_BMSK 0x8 +#define HWIO_GCC_IPA_GDSCR_PD_ARES_SHFT 0x3 +#define HWIO_GCC_IPA_GDSCR_PD_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_IPA_GDSCR_PD_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_IPA_GDSCR_SW_OVERRIDE_BMSK 0x4 +#define HWIO_GCC_IPA_GDSCR_SW_OVERRIDE_SHFT 0x2 +#define HWIO_GCC_IPA_GDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_GDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPA_GDSCR_HW_CONTROL_BMSK 0x2 +#define HWIO_GCC_IPA_GDSCR_HW_CONTROL_SHFT 0x1 +#define HWIO_GCC_IPA_GDSCR_HW_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_GDSCR_HW_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPA_GDSCR_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_IPA_GDSCR_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_IPA_GDSCR_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_GDSCR_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_IPA_CFG_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038008) +#define HWIO_GCC_IPA_CFG_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038008) +#define HWIO_GCC_IPA_CFG_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038008) +#define HWIO_GCC_IPA_CFG_GDSCR_RMSK 0x3ffffff +#define HWIO_GCC_IPA_CFG_GDSCR_ATTR 0x3 +#define HWIO_GCC_IPA_CFG_GDSCR_IN \ + in_dword_masked(HWIO_GCC_IPA_CFG_GDSCR_ADDR, HWIO_GCC_IPA_CFG_GDSCR_RMSK) +#define HWIO_GCC_IPA_CFG_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_IPA_CFG_GDSCR_ADDR, m) +#define HWIO_GCC_IPA_CFG_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_IPA_CFG_GDSCR_ADDR,v) +#define HWIO_GCC_IPA_CFG_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_IPA_CFG_GDSCR_ADDR,m,v,HWIO_GCC_IPA_CFG_GDSCR_IN) +#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_PWR_DWN_START_BMSK 0x2000000 +#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_PWR_DWN_START_SHFT 0x19 +#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_PWR_UP_START_BMSK 0x1000000 +#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_PWR_UP_START_SHFT 0x18 +#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_BMSK 0xf00000 +#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_SHFT 0x14 +#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_BMSK 0x80000 +#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_SHFT 0x13 +#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_ENR_ACK_STATUS_BMSK 0x40000 +#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_ENR_ACK_STATUS_SHFT 0x12 +#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_ENF_ACK_STATUS_BMSK 0x20000 +#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_ENF_ACK_STATUS_SHFT 0x11 +#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_BMSK 0x10000 +#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_SHFT 0x10 +#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_BMSK 0x8000 +#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_SHFT 0xf +#define HWIO_GCC_IPA_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_BMSK 0x7800 +#define HWIO_GCC_IPA_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_SHFT 0xb +#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_HANDSHAKE_DIS_BMSK 0x400 +#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_HANDSHAKE_DIS_SHFT 0xa +#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_BMSK 0x200 +#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_SHFT 0x9 +#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_BMSK 0x100 +#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_SHFT 0x8 +#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_BMSK 0x80 +#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_SHFT 0x7 +#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_BMSK 0x60 +#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_SHFT 0x5 +#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_BMSK 0x10 +#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_SHFT 0x4 +#define HWIO_GCC_IPA_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_BMSK 0x8 +#define HWIO_GCC_IPA_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_SHFT 0x3 +#define HWIO_GCC_IPA_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_BMSK 0x4 +#define HWIO_GCC_IPA_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_SHFT 0x2 +#define HWIO_GCC_IPA_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_BMSK 0x2 +#define HWIO_GCC_IPA_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_SHFT 0x1 +#define HWIO_GCC_IPA_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_IPA_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_SHFT 0x0 + +#define HWIO_GCC_IPA_CFG2_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003800c) +#define HWIO_GCC_IPA_CFG2_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003800c) +#define HWIO_GCC_IPA_CFG2_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003800c) +#define HWIO_GCC_IPA_CFG2_GDSCR_RMSK 0x7ffff +#define HWIO_GCC_IPA_CFG2_GDSCR_ATTR 0x3 +#define HWIO_GCC_IPA_CFG2_GDSCR_IN \ + in_dword_masked(HWIO_GCC_IPA_CFG2_GDSCR_ADDR, HWIO_GCC_IPA_CFG2_GDSCR_RMSK) +#define HWIO_GCC_IPA_CFG2_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_IPA_CFG2_GDSCR_ADDR, m) +#define HWIO_GCC_IPA_CFG2_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_IPA_CFG2_GDSCR_ADDR,v) +#define HWIO_GCC_IPA_CFG2_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_IPA_CFG2_GDSCR_ADDR,m,v,HWIO_GCC_IPA_CFG2_GDSCR_IN) +#define HWIO_GCC_IPA_CFG2_GDSCR_GDSC_MEM_PWRUP_ACK_OVERRIDE_BMSK 0x40000 +#define HWIO_GCC_IPA_CFG2_GDSCR_GDSC_MEM_PWRUP_ACK_OVERRIDE_SHFT 0x12 +#define HWIO_GCC_IPA_CFG2_GDSCR_GDSC_PWRDWN_ENABLE_ACK_OVERRIDE_BMSK 0x20000 +#define HWIO_GCC_IPA_CFG2_GDSCR_GDSC_PWRDWN_ENABLE_ACK_OVERRIDE_SHFT 0x11 +#define HWIO_GCC_IPA_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_BMSK 0x10000 +#define HWIO_GCC_IPA_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_SHFT 0x10 +#define HWIO_GCC_IPA_CFG2_GDSCR_DLY_MEM_PWR_UP_BMSK 0xf000 +#define HWIO_GCC_IPA_CFG2_GDSCR_DLY_MEM_PWR_UP_SHFT 0xc +#define HWIO_GCC_IPA_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_BMSK 0xf00 +#define HWIO_GCC_IPA_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_SHFT 0x8 +#define HWIO_GCC_IPA_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_BMSK 0xf0 +#define HWIO_GCC_IPA_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_SHFT 0x4 +#define HWIO_GCC_IPA_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_BMSK 0xf +#define HWIO_GCC_IPA_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_SHFT 0x0 + +#define HWIO_GCC_IPA_CFG3_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038010) +#define HWIO_GCC_IPA_CFG3_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038010) +#define HWIO_GCC_IPA_CFG3_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038010) +#define HWIO_GCC_IPA_CFG3_GDSCR_RMSK 0x7ffffff +#define HWIO_GCC_IPA_CFG3_GDSCR_ATTR 0x3 +#define HWIO_GCC_IPA_CFG3_GDSCR_IN \ + in_dword_masked(HWIO_GCC_IPA_CFG3_GDSCR_ADDR, HWIO_GCC_IPA_CFG3_GDSCR_RMSK) +#define HWIO_GCC_IPA_CFG3_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_IPA_CFG3_GDSCR_ADDR, m) +#define HWIO_GCC_IPA_CFG3_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_IPA_CFG3_GDSCR_ADDR,v) +#define HWIO_GCC_IPA_CFG3_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_IPA_CFG3_GDSCR_ADDR,m,v,HWIO_GCC_IPA_CFG3_GDSCR_IN) +#define HWIO_GCC_IPA_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_STATUS_BMSK 0x4000000 +#define HWIO_GCC_IPA_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_STATUS_SHFT 0x1a +#define HWIO_GCC_IPA_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_BMSK 0x2000000 +#define HWIO_GCC_IPA_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_SHFT 0x19 +#define HWIO_GCC_IPA_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPA_CFG3_GDSCR_DLY_ACCU_RED_SHIFTER_DONE_BMSK 0x1e00000 +#define HWIO_GCC_IPA_CFG3_GDSCR_DLY_ACCU_RED_SHIFTER_DONE_SHFT 0x15 +#define HWIO_GCC_IPA_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_BMSK 0x100000 +#define HWIO_GCC_IPA_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_SHFT 0x14 +#define HWIO_GCC_IPA_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPA_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_BMSK 0x80000 +#define HWIO_GCC_IPA_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_SHFT 0x13 +#define HWIO_GCC_IPA_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPA_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_BMSK 0x40000 +#define HWIO_GCC_IPA_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_SHFT 0x12 +#define HWIO_GCC_IPA_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPA_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_BMSK 0x20000 +#define HWIO_GCC_IPA_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_SHFT 0x11 +#define HWIO_GCC_IPA_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPA_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_BMSK 0x10000 +#define HWIO_GCC_IPA_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_SHFT 0x10 +#define HWIO_GCC_IPA_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPA_CFG3_GDSCR_GDSC_SPARE_CTRL_IN_BMSK 0xff00 +#define HWIO_GCC_IPA_CFG3_GDSCR_GDSC_SPARE_CTRL_IN_SHFT 0x8 +#define HWIO_GCC_IPA_CFG3_GDSCR_GDSC_SPARE_CTRL_OUT_BMSK 0xff +#define HWIO_GCC_IPA_CFG3_GDSCR_GDSC_SPARE_CTRL_OUT_SHFT 0x0 + +#define HWIO_GCC_IPA_CFG4_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038014) +#define HWIO_GCC_IPA_CFG4_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038014) +#define HWIO_GCC_IPA_CFG4_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038014) +#define HWIO_GCC_IPA_CFG4_GDSCR_RMSK 0xffffff +#define HWIO_GCC_IPA_CFG4_GDSCR_ATTR 0x3 +#define HWIO_GCC_IPA_CFG4_GDSCR_IN \ + in_dword_masked(HWIO_GCC_IPA_CFG4_GDSCR_ADDR, HWIO_GCC_IPA_CFG4_GDSCR_RMSK) +#define HWIO_GCC_IPA_CFG4_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_IPA_CFG4_GDSCR_ADDR, m) +#define HWIO_GCC_IPA_CFG4_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_IPA_CFG4_GDSCR_ADDR,v) +#define HWIO_GCC_IPA_CFG4_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_IPA_CFG4_GDSCR_ADDR,m,v,HWIO_GCC_IPA_CFG4_GDSCR_IN) +#define HWIO_GCC_IPA_CFG4_GDSCR_DLY_UNCLAMPIO_BMSK 0xf00000 +#define HWIO_GCC_IPA_CFG4_GDSCR_DLY_UNCLAMPIO_SHFT 0x14 +#define HWIO_GCC_IPA_CFG4_GDSCR_DLY_RESTOREFF_BMSK 0xf0000 +#define HWIO_GCC_IPA_CFG4_GDSCR_DLY_RESTOREFF_SHFT 0x10 +#define HWIO_GCC_IPA_CFG4_GDSCR_DLY_NORETAINFF_BMSK 0xf000 +#define HWIO_GCC_IPA_CFG4_GDSCR_DLY_NORETAINFF_SHFT 0xc +#define HWIO_GCC_IPA_CFG4_GDSCR_DLY_DEASSERTARES_BMSK 0xf00 +#define HWIO_GCC_IPA_CFG4_GDSCR_DLY_DEASSERTARES_SHFT 0x8 +#define HWIO_GCC_IPA_CFG4_GDSCR_DLY_CLAMPIO_BMSK 0xf0 +#define HWIO_GCC_IPA_CFG4_GDSCR_DLY_CLAMPIO_SHFT 0x4 +#define HWIO_GCC_IPA_CFG4_GDSCR_DLY_RETAINFF_BMSK 0xf +#define HWIO_GCC_IPA_CFG4_GDSCR_DLY_RETAINFF_SHFT 0x0 + +#define HWIO_GCC_IPA_2X_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038018) +#define HWIO_GCC_IPA_2X_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038018) +#define HWIO_GCC_IPA_2X_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038018) +#define HWIO_GCC_IPA_2X_CBCR_RMSK 0x81d07ff5 +#define HWIO_GCC_IPA_2X_CBCR_ATTR 0x3 +#define HWIO_GCC_IPA_2X_CBCR_IN \ + in_dword_masked(HWIO_GCC_IPA_2X_CBCR_ADDR, HWIO_GCC_IPA_2X_CBCR_RMSK) +#define HWIO_GCC_IPA_2X_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_IPA_2X_CBCR_ADDR, m) +#define HWIO_GCC_IPA_2X_CBCR_OUT(v) \ + out_dword(HWIO_GCC_IPA_2X_CBCR_ADDR,v) +#define HWIO_GCC_IPA_2X_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_IPA_2X_CBCR_ADDR,m,v,HWIO_GCC_IPA_2X_CBCR_IN) +#define HWIO_GCC_IPA_2X_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_IPA_2X_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_IPA_2X_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_IPA_2X_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_IPA_2X_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_IPA_2X_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_IPA_2X_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_IPA_2X_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_IPA_2X_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_IPA_2X_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_IPA_2X_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_IPA_2X_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_IPA_2X_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_2X_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPA_2X_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_IPA_2X_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_IPA_2X_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_2X_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPA_2X_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_IPA_2X_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_IPA_2X_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_2X_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPA_2X_CBCR_WAKEUP_BMSK 0xf00 +#define HWIO_GCC_IPA_2X_CBCR_WAKEUP_SHFT 0x8 +#define HWIO_GCC_IPA_2X_CBCR_WAKEUP_CLOCK0_FVAL 0x0 +#define HWIO_GCC_IPA_2X_CBCR_WAKEUP_CLOCK1_FVAL 0x1 +#define HWIO_GCC_IPA_2X_CBCR_WAKEUP_CLOCK2_FVAL 0x2 +#define HWIO_GCC_IPA_2X_CBCR_WAKEUP_CLOCK3_FVAL 0x3 +#define HWIO_GCC_IPA_2X_CBCR_WAKEUP_CLOCK4_FVAL 0x4 +#define HWIO_GCC_IPA_2X_CBCR_WAKEUP_CLOCK5_FVAL 0x5 +#define HWIO_GCC_IPA_2X_CBCR_WAKEUP_CLOCK6_FVAL 0x6 +#define HWIO_GCC_IPA_2X_CBCR_WAKEUP_CLOCK7_FVAL 0x7 +#define HWIO_GCC_IPA_2X_CBCR_WAKEUP_CLOCK8_FVAL 0x8 +#define HWIO_GCC_IPA_2X_CBCR_WAKEUP_CLOCK9_FVAL 0x9 +#define HWIO_GCC_IPA_2X_CBCR_WAKEUP_CLOCK10_FVAL 0xa +#define HWIO_GCC_IPA_2X_CBCR_WAKEUP_CLOCK11_FVAL 0xb +#define HWIO_GCC_IPA_2X_CBCR_WAKEUP_CLOCK12_FVAL 0xc +#define HWIO_GCC_IPA_2X_CBCR_WAKEUP_CLOCK13_FVAL 0xd +#define HWIO_GCC_IPA_2X_CBCR_WAKEUP_CLOCK14_FVAL 0xe +#define HWIO_GCC_IPA_2X_CBCR_WAKEUP_CLOCK15_FVAL 0xf +#define HWIO_GCC_IPA_2X_CBCR_SLEEP_BMSK 0xf0 +#define HWIO_GCC_IPA_2X_CBCR_SLEEP_SHFT 0x4 +#define HWIO_GCC_IPA_2X_CBCR_SLEEP_CLOCK0_FVAL 0x0 +#define HWIO_GCC_IPA_2X_CBCR_SLEEP_CLOCK1_FVAL 0x1 +#define HWIO_GCC_IPA_2X_CBCR_SLEEP_CLOCK2_FVAL 0x2 +#define HWIO_GCC_IPA_2X_CBCR_SLEEP_CLOCK3_FVAL 0x3 +#define HWIO_GCC_IPA_2X_CBCR_SLEEP_CLOCK4_FVAL 0x4 +#define HWIO_GCC_IPA_2X_CBCR_SLEEP_CLOCK5_FVAL 0x5 +#define HWIO_GCC_IPA_2X_CBCR_SLEEP_CLOCK6_FVAL 0x6 +#define HWIO_GCC_IPA_2X_CBCR_SLEEP_CLOCK7_FVAL 0x7 +#define HWIO_GCC_IPA_2X_CBCR_SLEEP_CLOCK8_FVAL 0x8 +#define HWIO_GCC_IPA_2X_CBCR_SLEEP_CLOCK9_FVAL 0x9 +#define HWIO_GCC_IPA_2X_CBCR_SLEEP_CLOCK10_FVAL 0xa +#define HWIO_GCC_IPA_2X_CBCR_SLEEP_CLOCK11_FVAL 0xb +#define HWIO_GCC_IPA_2X_CBCR_SLEEP_CLOCK12_FVAL 0xc +#define HWIO_GCC_IPA_2X_CBCR_SLEEP_CLOCK13_FVAL 0xd +#define HWIO_GCC_IPA_2X_CBCR_SLEEP_CLOCK14_FVAL 0xe +#define HWIO_GCC_IPA_2X_CBCR_SLEEP_CLOCK15_FVAL 0xf +#define HWIO_GCC_IPA_2X_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_IPA_2X_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_IPA_2X_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_IPA_2X_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_IPA_2X_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_IPA_2X_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_IPA_2X_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_2X_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_IPA_2X_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003801c) +#define HWIO_GCC_IPA_2X_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003801c) +#define HWIO_GCC_IPA_2X_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003801c) +#define HWIO_GCC_IPA_2X_SREGR_RMSK 0xfffffffe +#define HWIO_GCC_IPA_2X_SREGR_ATTR 0x3 +#define HWIO_GCC_IPA_2X_SREGR_IN \ + in_dword_masked(HWIO_GCC_IPA_2X_SREGR_ADDR, HWIO_GCC_IPA_2X_SREGR_RMSK) +#define HWIO_GCC_IPA_2X_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_IPA_2X_SREGR_ADDR, m) +#define HWIO_GCC_IPA_2X_SREGR_OUT(v) \ + out_dword(HWIO_GCC_IPA_2X_SREGR_ADDR,v) +#define HWIO_GCC_IPA_2X_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_IPA_2X_SREGR_ADDR,m,v,HWIO_GCC_IPA_2X_SREGR_IN) +#define HWIO_GCC_IPA_2X_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xff000000 +#define HWIO_GCC_IPA_2X_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_IPA_2X_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xff0000 +#define HWIO_GCC_IPA_2X_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_IPA_2X_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_IPA_2X_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_IPA_2X_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_IPA_2X_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_IPA_2X_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_IPA_2X_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_IPA_2X_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_IPA_2X_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_IPA_2X_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_IPA_2X_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_IPA_2X_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_IPA_2X_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_IPA_2X_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_IPA_2X_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_IPA_2X_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_IPA_2X_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_IPA_2X_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_IPA_2X_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_IPA_2X_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_IPA_2X_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_IPA_2X_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_IPA_2X_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_IPA_2X_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_IPA_2X_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_IPA_2X_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_IPA_2X_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_IPA_2X_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_IPA_2X_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_IPA_2X_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_2X_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPA_2X_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_IPA_2X_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_IPA_2X_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_IPA_2X_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPA_2X_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_IPA_2X_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_IPA_2X_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_IPA_2X_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_IPA_2X_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_IPA_2X_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_IPA_2X_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_IPA_2X_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_IPA_2X_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_IPA_2X_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_IPA_2X_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_IPA_2X_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_IPA_2X_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_IPA_2X_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_IPA_2X_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_IPA_2X_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_IPA_2X_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_IPA_2X_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_IPA_2X_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_2X_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_IPA_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038020) +#define HWIO_GCC_IPA_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038020) +#define HWIO_GCC_IPA_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038020) +#define HWIO_GCC_IPA_CBCR_RMSK 0x81d07ff5 +#define HWIO_GCC_IPA_CBCR_ATTR 0x3 +#define HWIO_GCC_IPA_CBCR_IN \ + in_dword_masked(HWIO_GCC_IPA_CBCR_ADDR, HWIO_GCC_IPA_CBCR_RMSK) +#define HWIO_GCC_IPA_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_IPA_CBCR_ADDR, m) +#define HWIO_GCC_IPA_CBCR_OUT(v) \ + out_dword(HWIO_GCC_IPA_CBCR_ADDR,v) +#define HWIO_GCC_IPA_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_IPA_CBCR_ADDR,m,v,HWIO_GCC_IPA_CBCR_IN) +#define HWIO_GCC_IPA_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_IPA_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_IPA_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_IPA_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_IPA_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_IPA_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_IPA_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_IPA_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_IPA_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_IPA_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_IPA_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_IPA_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_IPA_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPA_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_IPA_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_IPA_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPA_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_IPA_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_IPA_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPA_CBCR_WAKEUP_BMSK 0xf00 +#define HWIO_GCC_IPA_CBCR_WAKEUP_SHFT 0x8 +#define HWIO_GCC_IPA_CBCR_WAKEUP_CLOCK0_FVAL 0x0 +#define HWIO_GCC_IPA_CBCR_WAKEUP_CLOCK1_FVAL 0x1 +#define HWIO_GCC_IPA_CBCR_WAKEUP_CLOCK2_FVAL 0x2 +#define HWIO_GCC_IPA_CBCR_WAKEUP_CLOCK3_FVAL 0x3 +#define HWIO_GCC_IPA_CBCR_WAKEUP_CLOCK4_FVAL 0x4 +#define HWIO_GCC_IPA_CBCR_WAKEUP_CLOCK5_FVAL 0x5 +#define HWIO_GCC_IPA_CBCR_WAKEUP_CLOCK6_FVAL 0x6 +#define HWIO_GCC_IPA_CBCR_WAKEUP_CLOCK7_FVAL 0x7 +#define HWIO_GCC_IPA_CBCR_WAKEUP_CLOCK8_FVAL 0x8 +#define HWIO_GCC_IPA_CBCR_WAKEUP_CLOCK9_FVAL 0x9 +#define HWIO_GCC_IPA_CBCR_WAKEUP_CLOCK10_FVAL 0xa +#define HWIO_GCC_IPA_CBCR_WAKEUP_CLOCK11_FVAL 0xb +#define HWIO_GCC_IPA_CBCR_WAKEUP_CLOCK12_FVAL 0xc +#define HWIO_GCC_IPA_CBCR_WAKEUP_CLOCK13_FVAL 0xd +#define HWIO_GCC_IPA_CBCR_WAKEUP_CLOCK14_FVAL 0xe +#define HWIO_GCC_IPA_CBCR_WAKEUP_CLOCK15_FVAL 0xf +#define HWIO_GCC_IPA_CBCR_SLEEP_BMSK 0xf0 +#define HWIO_GCC_IPA_CBCR_SLEEP_SHFT 0x4 +#define HWIO_GCC_IPA_CBCR_SLEEP_CLOCK0_FVAL 0x0 +#define HWIO_GCC_IPA_CBCR_SLEEP_CLOCK1_FVAL 0x1 +#define HWIO_GCC_IPA_CBCR_SLEEP_CLOCK2_FVAL 0x2 +#define HWIO_GCC_IPA_CBCR_SLEEP_CLOCK3_FVAL 0x3 +#define HWIO_GCC_IPA_CBCR_SLEEP_CLOCK4_FVAL 0x4 +#define HWIO_GCC_IPA_CBCR_SLEEP_CLOCK5_FVAL 0x5 +#define HWIO_GCC_IPA_CBCR_SLEEP_CLOCK6_FVAL 0x6 +#define HWIO_GCC_IPA_CBCR_SLEEP_CLOCK7_FVAL 0x7 +#define HWIO_GCC_IPA_CBCR_SLEEP_CLOCK8_FVAL 0x8 +#define HWIO_GCC_IPA_CBCR_SLEEP_CLOCK9_FVAL 0x9 +#define HWIO_GCC_IPA_CBCR_SLEEP_CLOCK10_FVAL 0xa +#define HWIO_GCC_IPA_CBCR_SLEEP_CLOCK11_FVAL 0xb +#define HWIO_GCC_IPA_CBCR_SLEEP_CLOCK12_FVAL 0xc +#define HWIO_GCC_IPA_CBCR_SLEEP_CLOCK13_FVAL 0xd +#define HWIO_GCC_IPA_CBCR_SLEEP_CLOCK14_FVAL 0xe +#define HWIO_GCC_IPA_CBCR_SLEEP_CLOCK15_FVAL 0xf +#define HWIO_GCC_IPA_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_IPA_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_IPA_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_IPA_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_IPA_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_IPA_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_IPA_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_IPA_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038024) +#define HWIO_GCC_IPA_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038024) +#define HWIO_GCC_IPA_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038024) +#define HWIO_GCC_IPA_SREGR_RMSK 0xfffffffe +#define HWIO_GCC_IPA_SREGR_ATTR 0x3 +#define HWIO_GCC_IPA_SREGR_IN \ + in_dword_masked(HWIO_GCC_IPA_SREGR_ADDR, HWIO_GCC_IPA_SREGR_RMSK) +#define HWIO_GCC_IPA_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_IPA_SREGR_ADDR, m) +#define HWIO_GCC_IPA_SREGR_OUT(v) \ + out_dword(HWIO_GCC_IPA_SREGR_ADDR,v) +#define HWIO_GCC_IPA_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_IPA_SREGR_ADDR,m,v,HWIO_GCC_IPA_SREGR_IN) +#define HWIO_GCC_IPA_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xff000000 +#define HWIO_GCC_IPA_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_IPA_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xff0000 +#define HWIO_GCC_IPA_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_IPA_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_IPA_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_IPA_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_IPA_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_IPA_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_IPA_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_IPA_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_IPA_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_IPA_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_IPA_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_IPA_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_IPA_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_IPA_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_IPA_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_IPA_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_IPA_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_IPA_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_IPA_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_IPA_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_IPA_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_IPA_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_IPA_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_IPA_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_IPA_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_IPA_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_IPA_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_IPA_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_IPA_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_IPA_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPA_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_IPA_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_IPA_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_IPA_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPA_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_IPA_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_IPA_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_IPA_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_IPA_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_IPA_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_IPA_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_IPA_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_IPA_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_IPA_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_IPA_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_IPA_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_IPA_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_IPA_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_IPA_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_IPA_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_IPA_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_IPA_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_IPA_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_IPA_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038028) +#define HWIO_GCC_IPA_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038028) +#define HWIO_GCC_IPA_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038028) +#define HWIO_GCC_IPA_AHB_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_IPA_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_IPA_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_IPA_AHB_CBCR_ADDR, HWIO_GCC_IPA_AHB_CBCR_RMSK) +#define HWIO_GCC_IPA_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_IPA_AHB_CBCR_ADDR, m) +#define HWIO_GCC_IPA_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_IPA_AHB_CBCR_ADDR,v) +#define HWIO_GCC_IPA_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_IPA_AHB_CBCR_ADDR,m,v,HWIO_GCC_IPA_AHB_CBCR_IN) +#define HWIO_GCC_IPA_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_IPA_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_IPA_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_IPA_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_IPA_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_IPA_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_IPA_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_IPA_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_IPA_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_IPA_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_IPA_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_IPA_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_IPA_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_IPA_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_IPA_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_IPA_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_IPA_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_IPA_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_IPA_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPA_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_IPA_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_IPA_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_IPA_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003802c) +#define HWIO_GCC_IPA_XO_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003802c) +#define HWIO_GCC_IPA_XO_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003802c) +#define HWIO_GCC_IPA_XO_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_IPA_XO_CBCR_ATTR 0x3 +#define HWIO_GCC_IPA_XO_CBCR_IN \ + in_dword_masked(HWIO_GCC_IPA_XO_CBCR_ADDR, HWIO_GCC_IPA_XO_CBCR_RMSK) +#define HWIO_GCC_IPA_XO_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_IPA_XO_CBCR_ADDR, m) +#define HWIO_GCC_IPA_XO_CBCR_OUT(v) \ + out_dword(HWIO_GCC_IPA_XO_CBCR_ADDR,v) +#define HWIO_GCC_IPA_XO_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_IPA_XO_CBCR_ADDR,m,v,HWIO_GCC_IPA_XO_CBCR_IN) +#define HWIO_GCC_IPA_XO_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_IPA_XO_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_IPA_XO_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_IPA_XO_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_IPA_XO_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_IPA_XO_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_IPA_XO_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_IPA_XO_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_IPA_XO_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_IPA_XO_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_IPA_XO_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_IPA_XO_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_IPA_XO_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_IPA_XO_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_IPA_XO_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_XO_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_IPA_2X_CDIV_DCD_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038030) +#define HWIO_GCC_IPA_2X_CDIV_DCD_DCDR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038030) +#define HWIO_GCC_IPA_2X_CDIV_DCD_DCDR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038030) +#define HWIO_GCC_IPA_2X_CDIV_DCD_DCDR_RMSK 0x1 +#define HWIO_GCC_IPA_2X_CDIV_DCD_DCDR_ATTR 0x3 +#define HWIO_GCC_IPA_2X_CDIV_DCD_DCDR_IN \ + in_dword_masked(HWIO_GCC_IPA_2X_CDIV_DCD_DCDR_ADDR, HWIO_GCC_IPA_2X_CDIV_DCD_DCDR_RMSK) +#define HWIO_GCC_IPA_2X_CDIV_DCD_DCDR_INM(m) \ + in_dword_masked(HWIO_GCC_IPA_2X_CDIV_DCD_DCDR_ADDR, m) +#define HWIO_GCC_IPA_2X_CDIV_DCD_DCDR_OUT(v) \ + out_dword(HWIO_GCC_IPA_2X_CDIV_DCD_DCDR_ADDR,v) +#define HWIO_GCC_IPA_2X_CDIV_DCD_DCDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_IPA_2X_CDIV_DCD_DCDR_ADDR,m,v,HWIO_GCC_IPA_2X_CDIV_DCD_DCDR_IN) +#define HWIO_GCC_IPA_2X_CDIV_DCD_DCDR_DCD_ENABLE_BMSK 0x1 +#define HWIO_GCC_IPA_2X_CDIV_DCD_DCDR_DCD_ENABLE_SHFT 0x0 +#define HWIO_GCC_IPA_2X_CDIV_DCD_DCDR_DCD_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_2X_CDIV_DCD_DCDR_DCD_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_IPA_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038048) +#define HWIO_GCC_RPMH_IPA_CMD_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038048) +#define HWIO_GCC_RPMH_IPA_CMD_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038048) +#define HWIO_GCC_RPMH_IPA_CMD_DFSR_RMSK 0xffff +#define HWIO_GCC_RPMH_IPA_CMD_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_CMD_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_CMD_DFSR_ADDR, HWIO_GCC_RPMH_IPA_CMD_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_CMD_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_CMD_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_CMD_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_CMD_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_CMD_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_CMD_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_CMD_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_CMD_DFSR_RCG_SW_CTRL_BMSK 0x8000 +#define HWIO_GCC_RPMH_IPA_CMD_DFSR_RCG_SW_CTRL_SHFT 0xf +#define HWIO_GCC_RPMH_IPA_CMD_DFSR_SW_PERF_STATE_BMSK 0x7800 +#define HWIO_GCC_RPMH_IPA_CMD_DFSR_SW_PERF_STATE_SHFT 0xb +#define HWIO_GCC_RPMH_IPA_CMD_DFSR_SW_OVERRIDE_BMSK 0x400 +#define HWIO_GCC_RPMH_IPA_CMD_DFSR_SW_OVERRIDE_SHFT 0xa +#define HWIO_GCC_RPMH_IPA_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK 0x200 +#define HWIO_GCC_RPMH_IPA_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT 0x9 +#define HWIO_GCC_RPMH_IPA_CMD_DFSR_DFS_FSM_STATE_BMSK 0x1c0 +#define HWIO_GCC_RPMH_IPA_CMD_DFSR_DFS_FSM_STATE_SHFT 0x6 +#define HWIO_GCC_RPMH_IPA_CMD_DFSR_HW_CLK_CONTROL_BMSK 0x20 +#define HWIO_GCC_RPMH_IPA_CMD_DFSR_HW_CLK_CONTROL_SHFT 0x5 +#define HWIO_GCC_RPMH_IPA_CMD_DFSR_CURR_PERF_STATE_BMSK 0x1e +#define HWIO_GCC_RPMH_IPA_CMD_DFSR_CURR_PERF_STATE_SHFT 0x1 +#define HWIO_GCC_RPMH_IPA_CMD_DFSR_DFS_EN_BMSK 0x1 +#define HWIO_GCC_RPMH_IPA_CMD_DFSR_DFS_EN_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_CMD_DFSR_DFS_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_CMD_DFSR_DFS_EN_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038050) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038050) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038050) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_RMSK 0x371f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038054) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038054) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038054) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_RMSK 0x371f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038058) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038058) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038058) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_RMSK 0x371f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003805c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003805c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003805c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_RMSK 0x371f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038060) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038060) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038060) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_RMSK 0x371f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038064) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038064) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038064) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_RMSK 0x371f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038068) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038068) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038068) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_RMSK 0x371f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003806c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003806c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003806c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_RMSK 0x371f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038070) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038070) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038070) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_RMSK 0x371f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038074) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038074) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038074) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_RMSK 0x371f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038078) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038078) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038078) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_RMSK 0x371f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003807c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003807c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003807c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_RMSK 0x371f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038080) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038080) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038080) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_RMSK 0x371f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038084) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038084) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038084) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_RMSK 0x371f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038088) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038088) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038088) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_RMSK 0x371f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003808c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003808c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003808c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_RMSK 0x371f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038090) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038090) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038090) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_M_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_M_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_M_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_M_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_M_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_M_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_M_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_M_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_M_DFSR_M_BMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038094) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038094) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038094) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_M_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_M_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_M_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_M_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_M_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_M_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_M_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_M_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_M_DFSR_M_BMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038098) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038098) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038098) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_M_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_M_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_M_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_M_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_M_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_M_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_M_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_M_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_M_DFSR_M_BMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003809c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003809c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003809c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_M_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_M_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_M_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_M_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_M_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_M_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_M_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_M_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_M_DFSR_M_BMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000380a0) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000380a0) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000380a0) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_M_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_M_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_M_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_M_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_M_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_M_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_M_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_M_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_M_DFSR_M_BMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000380a4) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000380a4) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000380a4) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_M_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_M_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_M_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_M_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_M_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_M_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_M_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_M_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_M_DFSR_M_BMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000380a8) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000380a8) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000380a8) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_M_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_M_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_M_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_M_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_M_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_M_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_M_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_M_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_M_DFSR_M_BMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000380ac) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000380ac) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000380ac) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_M_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_M_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_M_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_M_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_M_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_M_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_M_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_M_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_M_DFSR_M_BMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000380b0) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000380b0) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000380b0) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_M_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_M_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_M_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_M_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_M_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_M_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_M_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_M_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_M_DFSR_M_BMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000380b4) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000380b4) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000380b4) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_M_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_M_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_M_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_M_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_M_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_M_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_M_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_M_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_M_DFSR_M_BMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000380b8) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000380b8) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000380b8) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_M_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_M_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_M_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_M_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_M_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_M_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_M_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_M_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_M_DFSR_M_BMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000380bc) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000380bc) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000380bc) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_M_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_M_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_M_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_M_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_M_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_M_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_M_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_M_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_M_DFSR_M_BMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000380c0) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000380c0) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000380c0) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_M_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_M_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_M_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_M_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_M_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_M_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_M_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_M_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_M_DFSR_M_BMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000380c4) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000380c4) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000380c4) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_M_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_M_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_M_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_M_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_M_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_M_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_M_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_M_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_M_DFSR_M_BMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000380c8) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000380c8) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000380c8) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_M_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_M_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_M_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_M_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_M_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_M_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_M_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_M_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_M_DFSR_M_BMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000380cc) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000380cc) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000380cc) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_M_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_M_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_M_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_M_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_M_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_M_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_M_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_M_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_M_DFSR_M_BMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000380d0) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000380d0) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000380d0) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_N_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_N_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_N_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_N_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_N_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_N_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_N_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_N_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_N_DFSR_NOT_N_MINUS_M_BMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000380d4) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000380d4) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000380d4) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_N_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_N_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_N_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_N_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_N_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_N_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_N_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_N_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_N_DFSR_NOT_N_MINUS_M_BMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000380d8) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000380d8) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000380d8) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_N_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_N_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_N_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_N_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_N_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_N_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_N_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_N_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_N_DFSR_NOT_N_MINUS_M_BMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000380dc) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000380dc) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000380dc) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_N_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_N_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_N_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_N_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_N_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_N_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_N_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_N_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_N_DFSR_NOT_N_MINUS_M_BMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000380e0) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000380e0) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000380e0) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_N_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_N_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_N_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_N_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_N_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_N_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_N_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_N_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_N_DFSR_NOT_N_MINUS_M_BMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000380e4) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000380e4) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000380e4) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_N_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_N_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_N_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_N_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_N_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_N_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_N_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_N_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_N_DFSR_NOT_N_MINUS_M_BMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000380e8) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000380e8) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000380e8) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_N_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_N_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_N_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_N_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_N_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_N_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_N_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_N_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_N_DFSR_NOT_N_MINUS_M_BMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000380ec) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000380ec) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000380ec) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_N_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_N_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_N_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_N_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_N_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_N_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_N_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_N_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_N_DFSR_NOT_N_MINUS_M_BMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000380f0) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000380f0) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000380f0) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_N_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_N_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_N_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_N_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_N_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_N_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_N_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_N_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_N_DFSR_NOT_N_MINUS_M_BMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000380f4) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000380f4) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000380f4) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_N_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_N_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_N_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_N_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_N_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_N_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_N_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_N_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_N_DFSR_NOT_N_MINUS_M_BMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000380f8) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000380f8) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000380f8) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_N_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_N_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_N_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_N_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_N_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_N_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_N_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_N_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_N_DFSR_NOT_N_MINUS_M_BMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000380fc) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000380fc) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000380fc) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_N_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_N_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_N_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_N_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_N_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_N_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_N_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_N_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_N_DFSR_NOT_N_MINUS_M_BMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038100) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038100) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038100) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_N_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_N_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_N_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_N_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_N_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_N_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_N_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_N_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_N_DFSR_NOT_N_MINUS_M_BMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038104) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038104) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038104) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_N_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_N_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_N_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_N_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_N_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_N_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_N_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_N_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_N_DFSR_NOT_N_MINUS_M_BMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038108) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038108) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038108) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_N_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_N_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_N_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_N_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_N_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_N_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_N_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_N_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_N_DFSR_NOT_N_MINUS_M_BMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003810c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003810c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003810c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_N_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_N_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_N_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_N_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_N_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_N_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_N_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_N_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_N_DFSR_NOT_N_MINUS_M_BMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038110) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038110) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038110) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_D_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_D_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_D_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_D_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_D_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_D_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_D_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_D_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_D_DFSR_NOT_2D_BMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038114) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038114) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038114) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_D_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_D_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_D_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_D_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_D_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_D_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_D_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_D_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_D_DFSR_NOT_2D_BMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038118) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038118) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038118) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_D_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_D_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_D_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_D_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_D_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_D_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_D_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_D_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_D_DFSR_NOT_2D_BMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003811c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003811c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003811c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_D_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_D_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_D_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_D_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_D_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_D_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_D_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_D_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_D_DFSR_NOT_2D_BMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038120) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038120) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038120) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_D_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_D_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_D_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_D_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_D_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_D_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_D_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_D_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_D_DFSR_NOT_2D_BMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038124) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038124) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038124) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_D_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_D_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_D_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_D_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_D_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_D_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_D_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_D_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_D_DFSR_NOT_2D_BMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038128) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038128) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038128) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_D_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_D_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_D_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_D_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_D_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_D_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_D_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_D_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_D_DFSR_NOT_2D_BMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003812c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003812c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003812c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_D_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_D_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_D_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_D_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_D_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_D_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_D_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_D_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_D_DFSR_NOT_2D_BMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038130) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038130) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038130) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_D_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_D_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_D_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_D_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_D_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_D_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_D_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_D_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_D_DFSR_NOT_2D_BMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038134) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038134) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038134) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_D_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_D_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_D_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_D_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_D_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_D_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_D_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_D_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_D_DFSR_NOT_2D_BMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038138) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038138) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038138) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_D_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_D_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_D_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_D_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_D_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_D_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_D_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_D_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_D_DFSR_NOT_2D_BMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003813c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003813c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003813c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_D_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_D_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_D_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_D_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_D_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_D_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_D_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_D_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_D_DFSR_NOT_2D_BMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038140) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038140) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038140) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_D_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_D_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_D_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_D_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_D_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_D_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_D_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_D_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_D_DFSR_NOT_2D_BMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038144) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038144) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038144) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_D_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_D_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_D_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_D_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_D_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_D_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_D_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_D_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_D_DFSR_NOT_2D_BMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038148) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038148) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038148) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_D_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_D_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_D_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_D_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_D_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_D_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_D_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_D_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_D_DFSR_NOT_2D_BMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003814c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003814c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003814c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_D_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_D_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_D_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_D_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_D_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_D_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_D_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_D_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_D_DFSR_NOT_2D_BMSK 0xff +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_IPA_2X_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038034) +#define HWIO_GCC_IPA_2X_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038034) +#define HWIO_GCC_IPA_2X_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038034) +#define HWIO_GCC_IPA_2X_CMD_RCGR_RMSK 0x800000f3 +#define HWIO_GCC_IPA_2X_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_IPA_2X_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_IPA_2X_CMD_RCGR_ADDR, HWIO_GCC_IPA_2X_CMD_RCGR_RMSK) +#define HWIO_GCC_IPA_2X_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_IPA_2X_CMD_RCGR_ADDR, m) +#define HWIO_GCC_IPA_2X_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_IPA_2X_CMD_RCGR_ADDR,v) +#define HWIO_GCC_IPA_2X_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_IPA_2X_CMD_RCGR_ADDR,m,v,HWIO_GCC_IPA_2X_CMD_RCGR_IN) +#define HWIO_GCC_IPA_2X_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_IPA_2X_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_IPA_2X_CMD_RCGR_DIRTY_D_BMSK 0x80 +#define HWIO_GCC_IPA_2X_CMD_RCGR_DIRTY_D_SHFT 0x7 +#define HWIO_GCC_IPA_2X_CMD_RCGR_DIRTY_N_BMSK 0x40 +#define HWIO_GCC_IPA_2X_CMD_RCGR_DIRTY_N_SHFT 0x6 +#define HWIO_GCC_IPA_2X_CMD_RCGR_DIRTY_M_BMSK 0x20 +#define HWIO_GCC_IPA_2X_CMD_RCGR_DIRTY_M_SHFT 0x5 +#define HWIO_GCC_IPA_2X_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_IPA_2X_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_IPA_2X_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_IPA_2X_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_IPA_2X_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_2X_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPA_2X_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_IPA_2X_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_IPA_2X_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_2X_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_IPA_2X_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038038) +#define HWIO_GCC_IPA_2X_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038038) +#define HWIO_GCC_IPA_2X_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038038) +#define HWIO_GCC_IPA_2X_CFG_RCGR_RMSK 0x10371f +#define HWIO_GCC_IPA_2X_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_IPA_2X_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_IPA_2X_CFG_RCGR_ADDR, HWIO_GCC_IPA_2X_CFG_RCGR_RMSK) +#define HWIO_GCC_IPA_2X_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_IPA_2X_CFG_RCGR_ADDR, m) +#define HWIO_GCC_IPA_2X_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_IPA_2X_CFG_RCGR_ADDR,v) +#define HWIO_GCC_IPA_2X_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_IPA_2X_CFG_RCGR_ADDR,m,v,HWIO_GCC_IPA_2X_CFG_RCGR_IN) +#define HWIO_GCC_IPA_2X_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_IPA_2X_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_IPA_2X_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_2X_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPA_2X_CFG_RCGR_MODE_BMSK 0x3000 +#define HWIO_GCC_IPA_2X_CFG_RCGR_MODE_SHFT 0xc +#define HWIO_GCC_IPA_2X_CFG_RCGR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_IPA_2X_CFG_RCGR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_IPA_2X_CFG_RCGR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_IPA_2X_CFG_RCGR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_IPA_2X_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003803c) +#define HWIO_GCC_IPA_2X_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003803c) +#define HWIO_GCC_IPA_2X_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003803c) +#define HWIO_GCC_IPA_2X_M_RMSK 0xff +#define HWIO_GCC_IPA_2X_M_ATTR 0x3 +#define HWIO_GCC_IPA_2X_M_IN \ + in_dword_masked(HWIO_GCC_IPA_2X_M_ADDR, HWIO_GCC_IPA_2X_M_RMSK) +#define HWIO_GCC_IPA_2X_M_INM(m) \ + in_dword_masked(HWIO_GCC_IPA_2X_M_ADDR, m) +#define HWIO_GCC_IPA_2X_M_OUT(v) \ + out_dword(HWIO_GCC_IPA_2X_M_ADDR,v) +#define HWIO_GCC_IPA_2X_M_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_IPA_2X_M_ADDR,m,v,HWIO_GCC_IPA_2X_M_IN) +#define HWIO_GCC_IPA_2X_M_M_BMSK 0xff +#define HWIO_GCC_IPA_2X_M_M_SHFT 0x0 + +#define HWIO_GCC_IPA_2X_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038040) +#define HWIO_GCC_IPA_2X_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038040) +#define HWIO_GCC_IPA_2X_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038040) +#define HWIO_GCC_IPA_2X_N_RMSK 0xff +#define HWIO_GCC_IPA_2X_N_ATTR 0x3 +#define HWIO_GCC_IPA_2X_N_IN \ + in_dword_masked(HWIO_GCC_IPA_2X_N_ADDR, HWIO_GCC_IPA_2X_N_RMSK) +#define HWIO_GCC_IPA_2X_N_INM(m) \ + in_dword_masked(HWIO_GCC_IPA_2X_N_ADDR, m) +#define HWIO_GCC_IPA_2X_N_OUT(v) \ + out_dword(HWIO_GCC_IPA_2X_N_ADDR,v) +#define HWIO_GCC_IPA_2X_N_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_IPA_2X_N_ADDR,m,v,HWIO_GCC_IPA_2X_N_IN) +#define HWIO_GCC_IPA_2X_N_NOT_N_MINUS_M_BMSK 0xff +#define HWIO_GCC_IPA_2X_N_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_IPA_2X_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038044) +#define HWIO_GCC_IPA_2X_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038044) +#define HWIO_GCC_IPA_2X_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038044) +#define HWIO_GCC_IPA_2X_D_RMSK 0xff +#define HWIO_GCC_IPA_2X_D_ATTR 0x3 +#define HWIO_GCC_IPA_2X_D_IN \ + in_dword_masked(HWIO_GCC_IPA_2X_D_ADDR, HWIO_GCC_IPA_2X_D_RMSK) +#define HWIO_GCC_IPA_2X_D_INM(m) \ + in_dword_masked(HWIO_GCC_IPA_2X_D_ADDR, m) +#define HWIO_GCC_IPA_2X_D_OUT(v) \ + out_dword(HWIO_GCC_IPA_2X_D_ADDR,v) +#define HWIO_GCC_IPA_2X_D_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_IPA_2X_D_ADDR,m,v,HWIO_GCC_IPA_2X_D_IN) +#define HWIO_GCC_IPA_2X_D_NOT_2D_BMSK 0xff +#define HWIO_GCC_IPA_2X_D_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_IPA_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038160) +#define HWIO_GCC_IPA_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038160) +#define HWIO_GCC_IPA_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038160) +#define HWIO_GCC_IPA_CDIVR_RMSK 0xf +#define HWIO_GCC_IPA_CDIVR_ATTR 0x3 +#define HWIO_GCC_IPA_CDIVR_IN \ + in_dword_masked(HWIO_GCC_IPA_CDIVR_ADDR, HWIO_GCC_IPA_CDIVR_RMSK) +#define HWIO_GCC_IPA_CDIVR_INM(m) \ + in_dword_masked(HWIO_GCC_IPA_CDIVR_ADDR, m) +#define HWIO_GCC_IPA_CDIVR_OUT(v) \ + out_dword(HWIO_GCC_IPA_CDIVR_ADDR,v) +#define HWIO_GCC_IPA_CDIVR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_IPA_CDIVR_ADDR,m,v,HWIO_GCC_IPA_CDIVR_IN) +#define HWIO_GCC_IPA_CDIVR_CLK_DIV_BMSK 0xf +#define HWIO_GCC_IPA_CDIVR_CLK_DIV_SHFT 0x0 + +#define HWIO_GCC_QPIC_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00039000) +#define HWIO_GCC_QPIC_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00039000) +#define HWIO_GCC_QPIC_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00039000) +#define HWIO_GCC_QPIC_BCR_RMSK 0x1 +#define HWIO_GCC_QPIC_BCR_ATTR 0x3 +#define HWIO_GCC_QPIC_BCR_IN \ + in_dword_masked(HWIO_GCC_QPIC_BCR_ADDR, HWIO_GCC_QPIC_BCR_RMSK) +#define HWIO_GCC_QPIC_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_QPIC_BCR_ADDR, m) +#define HWIO_GCC_QPIC_BCR_OUT(v) \ + out_dword(HWIO_GCC_QPIC_BCR_ADDR,v) +#define HWIO_GCC_QPIC_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QPIC_BCR_ADDR,m,v,HWIO_GCC_QPIC_BCR_IN) +#define HWIO_GCC_QPIC_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_QPIC_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_QPIC_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_QPIC_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QPIC_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00039004) +#define HWIO_GCC_QPIC_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00039004) +#define HWIO_GCC_QPIC_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00039004) +#define HWIO_GCC_QPIC_CBCR_RMSK 0x81d07ff5 +#define HWIO_GCC_QPIC_CBCR_ATTR 0x3 +#define HWIO_GCC_QPIC_CBCR_IN \ + in_dword_masked(HWIO_GCC_QPIC_CBCR_ADDR, HWIO_GCC_QPIC_CBCR_RMSK) +#define HWIO_GCC_QPIC_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QPIC_CBCR_ADDR, m) +#define HWIO_GCC_QPIC_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QPIC_CBCR_ADDR,v) +#define HWIO_GCC_QPIC_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QPIC_CBCR_ADDR,m,v,HWIO_GCC_QPIC_CBCR_IN) +#define HWIO_GCC_QPIC_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QPIC_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QPIC_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QPIC_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QPIC_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QPIC_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QPIC_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QPIC_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QPIC_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_QPIC_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_QPIC_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_QPIC_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_QPIC_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QPIC_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QPIC_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_QPIC_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_QPIC_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QPIC_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QPIC_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_QPIC_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_QPIC_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QPIC_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QPIC_CBCR_WAKEUP_BMSK 0xf00 +#define HWIO_GCC_QPIC_CBCR_WAKEUP_SHFT 0x8 +#define HWIO_GCC_QPIC_CBCR_WAKEUP_CLOCK0_FVAL 0x0 +#define HWIO_GCC_QPIC_CBCR_WAKEUP_CLOCK1_FVAL 0x1 +#define HWIO_GCC_QPIC_CBCR_WAKEUP_CLOCK2_FVAL 0x2 +#define HWIO_GCC_QPIC_CBCR_WAKEUP_CLOCK3_FVAL 0x3 +#define HWIO_GCC_QPIC_CBCR_WAKEUP_CLOCK4_FVAL 0x4 +#define HWIO_GCC_QPIC_CBCR_WAKEUP_CLOCK5_FVAL 0x5 +#define HWIO_GCC_QPIC_CBCR_WAKEUP_CLOCK6_FVAL 0x6 +#define HWIO_GCC_QPIC_CBCR_WAKEUP_CLOCK7_FVAL 0x7 +#define HWIO_GCC_QPIC_CBCR_WAKEUP_CLOCK8_FVAL 0x8 +#define HWIO_GCC_QPIC_CBCR_WAKEUP_CLOCK9_FVAL 0x9 +#define HWIO_GCC_QPIC_CBCR_WAKEUP_CLOCK10_FVAL 0xa +#define HWIO_GCC_QPIC_CBCR_WAKEUP_CLOCK11_FVAL 0xb +#define HWIO_GCC_QPIC_CBCR_WAKEUP_CLOCK12_FVAL 0xc +#define HWIO_GCC_QPIC_CBCR_WAKEUP_CLOCK13_FVAL 0xd +#define HWIO_GCC_QPIC_CBCR_WAKEUP_CLOCK14_FVAL 0xe +#define HWIO_GCC_QPIC_CBCR_WAKEUP_CLOCK15_FVAL 0xf +#define HWIO_GCC_QPIC_CBCR_SLEEP_BMSK 0xf0 +#define HWIO_GCC_QPIC_CBCR_SLEEP_SHFT 0x4 +#define HWIO_GCC_QPIC_CBCR_SLEEP_CLOCK0_FVAL 0x0 +#define HWIO_GCC_QPIC_CBCR_SLEEP_CLOCK1_FVAL 0x1 +#define HWIO_GCC_QPIC_CBCR_SLEEP_CLOCK2_FVAL 0x2 +#define HWIO_GCC_QPIC_CBCR_SLEEP_CLOCK3_FVAL 0x3 +#define HWIO_GCC_QPIC_CBCR_SLEEP_CLOCK4_FVAL 0x4 +#define HWIO_GCC_QPIC_CBCR_SLEEP_CLOCK5_FVAL 0x5 +#define HWIO_GCC_QPIC_CBCR_SLEEP_CLOCK6_FVAL 0x6 +#define HWIO_GCC_QPIC_CBCR_SLEEP_CLOCK7_FVAL 0x7 +#define HWIO_GCC_QPIC_CBCR_SLEEP_CLOCK8_FVAL 0x8 +#define HWIO_GCC_QPIC_CBCR_SLEEP_CLOCK9_FVAL 0x9 +#define HWIO_GCC_QPIC_CBCR_SLEEP_CLOCK10_FVAL 0xa +#define HWIO_GCC_QPIC_CBCR_SLEEP_CLOCK11_FVAL 0xb +#define HWIO_GCC_QPIC_CBCR_SLEEP_CLOCK12_FVAL 0xc +#define HWIO_GCC_QPIC_CBCR_SLEEP_CLOCK13_FVAL 0xd +#define HWIO_GCC_QPIC_CBCR_SLEEP_CLOCK14_FVAL 0xe +#define HWIO_GCC_QPIC_CBCR_SLEEP_CLOCK15_FVAL 0xf +#define HWIO_GCC_QPIC_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QPIC_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QPIC_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QPIC_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_QPIC_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_QPIC_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_QPIC_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QPIC_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QPIC_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00039008) +#define HWIO_GCC_QPIC_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00039008) +#define HWIO_GCC_QPIC_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00039008) +#define HWIO_GCC_QPIC_SREGR_RMSK 0xfffffffe +#define HWIO_GCC_QPIC_SREGR_ATTR 0x3 +#define HWIO_GCC_QPIC_SREGR_IN \ + in_dword_masked(HWIO_GCC_QPIC_SREGR_ADDR, HWIO_GCC_QPIC_SREGR_RMSK) +#define HWIO_GCC_QPIC_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_QPIC_SREGR_ADDR, m) +#define HWIO_GCC_QPIC_SREGR_OUT(v) \ + out_dword(HWIO_GCC_QPIC_SREGR_ADDR,v) +#define HWIO_GCC_QPIC_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QPIC_SREGR_ADDR,m,v,HWIO_GCC_QPIC_SREGR_IN) +#define HWIO_GCC_QPIC_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xff000000 +#define HWIO_GCC_QPIC_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_QPIC_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xff0000 +#define HWIO_GCC_QPIC_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_QPIC_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_QPIC_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_QPIC_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_QPIC_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_QPIC_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_QPIC_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_QPIC_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_QPIC_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_QPIC_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_QPIC_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_QPIC_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_QPIC_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_QPIC_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_QPIC_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_QPIC_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QPIC_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_QPIC_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_QPIC_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_QPIC_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_QPIC_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_QPIC_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_QPIC_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_QPIC_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_QPIC_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_QPIC_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_QPIC_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_QPIC_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_QPIC_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_QPIC_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QPIC_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QPIC_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_QPIC_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_QPIC_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_QPIC_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QPIC_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_QPIC_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_QPIC_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_QPIC_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_QPIC_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_QPIC_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_QPIC_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_QPIC_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_QPIC_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_QPIC_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_QPIC_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_QPIC_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_QPIC_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_QPIC_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_QPIC_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_QPIC_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_QPIC_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_QPIC_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_QPIC_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_QPIC_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QPIC_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003900c) +#define HWIO_GCC_QPIC_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003900c) +#define HWIO_GCC_QPIC_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003900c) +#define HWIO_GCC_QPIC_AHB_CBCR_RMSK 0x81d00005 +#define HWIO_GCC_QPIC_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_QPIC_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_QPIC_AHB_CBCR_ADDR, HWIO_GCC_QPIC_AHB_CBCR_RMSK) +#define HWIO_GCC_QPIC_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QPIC_AHB_CBCR_ADDR, m) +#define HWIO_GCC_QPIC_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QPIC_AHB_CBCR_ADDR,v) +#define HWIO_GCC_QPIC_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QPIC_AHB_CBCR_ADDR,m,v,HWIO_GCC_QPIC_AHB_CBCR_IN) +#define HWIO_GCC_QPIC_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QPIC_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QPIC_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QPIC_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QPIC_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QPIC_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QPIC_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QPIC_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QPIC_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_QPIC_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_QPIC_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QPIC_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QPIC_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QPIC_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_QPIC_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_QPIC_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_QPIC_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QPIC_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QPIC_SYSTEM_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00039010) +#define HWIO_GCC_QPIC_SYSTEM_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00039010) +#define HWIO_GCC_QPIC_SYSTEM_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00039010) +#define HWIO_GCC_QPIC_SYSTEM_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_QPIC_SYSTEM_CBCR_ATTR 0x3 +#define HWIO_GCC_QPIC_SYSTEM_CBCR_IN \ + in_dword_masked(HWIO_GCC_QPIC_SYSTEM_CBCR_ADDR, HWIO_GCC_QPIC_SYSTEM_CBCR_RMSK) +#define HWIO_GCC_QPIC_SYSTEM_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QPIC_SYSTEM_CBCR_ADDR, m) +#define HWIO_GCC_QPIC_SYSTEM_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QPIC_SYSTEM_CBCR_ADDR,v) +#define HWIO_GCC_QPIC_SYSTEM_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QPIC_SYSTEM_CBCR_ADDR,m,v,HWIO_GCC_QPIC_SYSTEM_CBCR_IN) +#define HWIO_GCC_QPIC_SYSTEM_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QPIC_SYSTEM_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QPIC_SYSTEM_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QPIC_SYSTEM_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QPIC_SYSTEM_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QPIC_SYSTEM_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QPIC_SYSTEM_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QPIC_SYSTEM_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QPIC_SYSTEM_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QPIC_SYSTEM_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QPIC_SYSTEM_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QPIC_SYSTEM_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_QPIC_SYSTEM_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_QPIC_SYSTEM_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_QPIC_SYSTEM_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QPIC_SYSTEM_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_QPIC_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00039028) +#define HWIO_GCC_RPMH_QPIC_CMD_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00039028) +#define HWIO_GCC_RPMH_QPIC_CMD_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00039028) +#define HWIO_GCC_RPMH_QPIC_CMD_DFSR_RMSK 0xffff +#define HWIO_GCC_RPMH_QPIC_CMD_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_CMD_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_CMD_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_CMD_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_CMD_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_CMD_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_CMD_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_CMD_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_CMD_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_CMD_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_CMD_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_CMD_DFSR_RCG_SW_CTRL_BMSK 0x8000 +#define HWIO_GCC_RPMH_QPIC_CMD_DFSR_RCG_SW_CTRL_SHFT 0xf +#define HWIO_GCC_RPMH_QPIC_CMD_DFSR_SW_PERF_STATE_BMSK 0x7800 +#define HWIO_GCC_RPMH_QPIC_CMD_DFSR_SW_PERF_STATE_SHFT 0xb +#define HWIO_GCC_RPMH_QPIC_CMD_DFSR_SW_OVERRIDE_BMSK 0x400 +#define HWIO_GCC_RPMH_QPIC_CMD_DFSR_SW_OVERRIDE_SHFT 0xa +#define HWIO_GCC_RPMH_QPIC_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK 0x200 +#define HWIO_GCC_RPMH_QPIC_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT 0x9 +#define HWIO_GCC_RPMH_QPIC_CMD_DFSR_DFS_FSM_STATE_BMSK 0x1c0 +#define HWIO_GCC_RPMH_QPIC_CMD_DFSR_DFS_FSM_STATE_SHFT 0x6 +#define HWIO_GCC_RPMH_QPIC_CMD_DFSR_HW_CLK_CONTROL_BMSK 0x20 +#define HWIO_GCC_RPMH_QPIC_CMD_DFSR_HW_CLK_CONTROL_SHFT 0x5 +#define HWIO_GCC_RPMH_QPIC_CMD_DFSR_CURR_PERF_STATE_BMSK 0x1e +#define HWIO_GCC_RPMH_QPIC_CMD_DFSR_CURR_PERF_STATE_SHFT 0x1 +#define HWIO_GCC_RPMH_QPIC_CMD_DFSR_DFS_EN_BMSK 0x1 +#define HWIO_GCC_RPMH_QPIC_CMD_DFSR_DFS_EN_SHFT 0x0 +#define HWIO_GCC_RPMH_QPIC_CMD_DFSR_DFS_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_CMD_DFSR_DFS_EN_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00039030) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00039030) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00039030) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_RMSK 0x371f +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00039034) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00039034) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00039034) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_RMSK 0x371f +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00039038) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00039038) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00039038) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_RMSK 0x371f +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003903c) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003903c) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003903c) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_RMSK 0x371f +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00039040) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00039040) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00039040) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_RMSK 0x371f +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00039044) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00039044) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00039044) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_RMSK 0x371f +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00039048) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00039048) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00039048) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_RMSK 0x371f +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003904c) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003904c) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003904c) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_RMSK 0x371f +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00039050) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00039050) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00039050) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_RMSK 0x371f +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00039054) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00039054) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00039054) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_RMSK 0x371f +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00039058) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00039058) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00039058) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_RMSK 0x371f +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003905c) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003905c) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003905c) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_RMSK 0x371f +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00039060) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00039060) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00039060) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_RMSK 0x371f +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00039064) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00039064) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00039064) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_RMSK 0x371f +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00039068) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00039068) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00039068) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_RMSK 0x371f +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003906c) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003906c) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003906c) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_RMSK 0x371f +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00039070) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00039070) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00039070) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_M_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_M_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF0_M_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF0_M_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF0_M_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF0_M_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF0_M_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF0_M_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_M_DFSR_M_BMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00039074) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00039074) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00039074) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_M_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_M_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF1_M_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF1_M_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF1_M_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF1_M_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF1_M_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF1_M_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_M_DFSR_M_BMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00039078) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00039078) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00039078) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_M_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_M_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF2_M_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF2_M_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF2_M_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF2_M_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF2_M_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF2_M_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_M_DFSR_M_BMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003907c) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003907c) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003907c) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_M_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_M_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF3_M_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF3_M_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF3_M_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF3_M_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF3_M_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF3_M_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_M_DFSR_M_BMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00039080) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00039080) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00039080) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_M_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_M_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF4_M_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF4_M_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF4_M_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF4_M_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF4_M_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF4_M_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_M_DFSR_M_BMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00039084) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00039084) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00039084) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_M_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_M_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF5_M_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF5_M_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF5_M_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF5_M_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF5_M_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF5_M_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_M_DFSR_M_BMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00039088) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00039088) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00039088) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_M_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_M_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF6_M_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF6_M_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF6_M_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF6_M_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF6_M_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF6_M_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_M_DFSR_M_BMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003908c) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003908c) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003908c) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_M_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_M_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF7_M_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF7_M_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF7_M_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF7_M_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF7_M_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF7_M_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_M_DFSR_M_BMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00039090) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00039090) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00039090) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_M_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_M_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF8_M_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF8_M_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF8_M_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF8_M_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF8_M_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF8_M_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_M_DFSR_M_BMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00039094) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00039094) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00039094) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_M_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_M_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF9_M_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF9_M_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF9_M_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF9_M_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF9_M_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF9_M_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_M_DFSR_M_BMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00039098) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00039098) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00039098) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_M_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_M_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF10_M_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF10_M_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF10_M_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF10_M_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF10_M_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF10_M_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_M_DFSR_M_BMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003909c) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003909c) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003909c) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_M_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_M_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF11_M_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF11_M_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF11_M_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF11_M_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF11_M_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF11_M_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_M_DFSR_M_BMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000390a0) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000390a0) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000390a0) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_M_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_M_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF12_M_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF12_M_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF12_M_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF12_M_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF12_M_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF12_M_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_M_DFSR_M_BMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000390a4) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000390a4) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000390a4) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_M_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_M_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF13_M_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF13_M_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF13_M_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF13_M_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF13_M_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF13_M_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_M_DFSR_M_BMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000390a8) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000390a8) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000390a8) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_M_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_M_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF14_M_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF14_M_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF14_M_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF14_M_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF14_M_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF14_M_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_M_DFSR_M_BMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000390ac) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000390ac) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000390ac) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_M_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_M_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF15_M_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF15_M_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF15_M_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF15_M_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF15_M_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF15_M_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_M_DFSR_M_BMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000390b0) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000390b0) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000390b0) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_N_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_N_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF0_N_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF0_N_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF0_N_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF0_N_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF0_N_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF0_N_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_N_DFSR_NOT_N_MINUS_M_BMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000390b4) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000390b4) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000390b4) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_N_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_N_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF1_N_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF1_N_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF1_N_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF1_N_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF1_N_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF1_N_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_N_DFSR_NOT_N_MINUS_M_BMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000390b8) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000390b8) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000390b8) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_N_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_N_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF2_N_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF2_N_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF2_N_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF2_N_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF2_N_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF2_N_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_N_DFSR_NOT_N_MINUS_M_BMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000390bc) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000390bc) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000390bc) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_N_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_N_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF3_N_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF3_N_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF3_N_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF3_N_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF3_N_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF3_N_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_N_DFSR_NOT_N_MINUS_M_BMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000390c0) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000390c0) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000390c0) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_N_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_N_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF4_N_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF4_N_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF4_N_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF4_N_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF4_N_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF4_N_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_N_DFSR_NOT_N_MINUS_M_BMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000390c4) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000390c4) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000390c4) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_N_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_N_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF5_N_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF5_N_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF5_N_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF5_N_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF5_N_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF5_N_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_N_DFSR_NOT_N_MINUS_M_BMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000390c8) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000390c8) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000390c8) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_N_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_N_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF6_N_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF6_N_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF6_N_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF6_N_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF6_N_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF6_N_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_N_DFSR_NOT_N_MINUS_M_BMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000390cc) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000390cc) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000390cc) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_N_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_N_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF7_N_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF7_N_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF7_N_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF7_N_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF7_N_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF7_N_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_N_DFSR_NOT_N_MINUS_M_BMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000390d0) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000390d0) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000390d0) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_N_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_N_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF8_N_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF8_N_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF8_N_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF8_N_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF8_N_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF8_N_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_N_DFSR_NOT_N_MINUS_M_BMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000390d4) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000390d4) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000390d4) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_N_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_N_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF9_N_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF9_N_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF9_N_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF9_N_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF9_N_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF9_N_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_N_DFSR_NOT_N_MINUS_M_BMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000390d8) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000390d8) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000390d8) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_N_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_N_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF10_N_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF10_N_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF10_N_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF10_N_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF10_N_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF10_N_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_N_DFSR_NOT_N_MINUS_M_BMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000390dc) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000390dc) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000390dc) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_N_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_N_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF11_N_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF11_N_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF11_N_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF11_N_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF11_N_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF11_N_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_N_DFSR_NOT_N_MINUS_M_BMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000390e0) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000390e0) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000390e0) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_N_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_N_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF12_N_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF12_N_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF12_N_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF12_N_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF12_N_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF12_N_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_N_DFSR_NOT_N_MINUS_M_BMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000390e4) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000390e4) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000390e4) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_N_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_N_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF13_N_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF13_N_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF13_N_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF13_N_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF13_N_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF13_N_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_N_DFSR_NOT_N_MINUS_M_BMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000390e8) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000390e8) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000390e8) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_N_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_N_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF14_N_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF14_N_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF14_N_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF14_N_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF14_N_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF14_N_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_N_DFSR_NOT_N_MINUS_M_BMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000390ec) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000390ec) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000390ec) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_N_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_N_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF15_N_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF15_N_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF15_N_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF15_N_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF15_N_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF15_N_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_N_DFSR_NOT_N_MINUS_M_BMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000390f0) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000390f0) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000390f0) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_D_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_D_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF0_D_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF0_D_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF0_D_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF0_D_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF0_D_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF0_D_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_D_DFSR_NOT_2D_BMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF0_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000390f4) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000390f4) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000390f4) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_D_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_D_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF1_D_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF1_D_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF1_D_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF1_D_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF1_D_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF1_D_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_D_DFSR_NOT_2D_BMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF1_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000390f8) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000390f8) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000390f8) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_D_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_D_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF2_D_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF2_D_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF2_D_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF2_D_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF2_D_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF2_D_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_D_DFSR_NOT_2D_BMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF2_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000390fc) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000390fc) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000390fc) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_D_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_D_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF3_D_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF3_D_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF3_D_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF3_D_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF3_D_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF3_D_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_D_DFSR_NOT_2D_BMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF3_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00039100) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00039100) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00039100) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_D_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_D_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF4_D_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF4_D_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF4_D_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF4_D_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF4_D_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF4_D_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_D_DFSR_NOT_2D_BMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF4_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00039104) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00039104) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00039104) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_D_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_D_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF5_D_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF5_D_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF5_D_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF5_D_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF5_D_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF5_D_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_D_DFSR_NOT_2D_BMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF5_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00039108) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00039108) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00039108) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_D_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_D_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF6_D_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF6_D_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF6_D_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF6_D_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF6_D_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF6_D_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_D_DFSR_NOT_2D_BMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF6_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003910c) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003910c) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003910c) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_D_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_D_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF7_D_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF7_D_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF7_D_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF7_D_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF7_D_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF7_D_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_D_DFSR_NOT_2D_BMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF7_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00039110) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00039110) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00039110) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_D_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_D_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF8_D_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF8_D_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF8_D_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF8_D_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF8_D_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF8_D_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_D_DFSR_NOT_2D_BMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF8_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00039114) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00039114) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00039114) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_D_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_D_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF9_D_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF9_D_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF9_D_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF9_D_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF9_D_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF9_D_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_D_DFSR_NOT_2D_BMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF9_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00039118) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00039118) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00039118) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_D_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_D_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF10_D_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF10_D_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF10_D_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF10_D_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF10_D_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF10_D_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_D_DFSR_NOT_2D_BMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF10_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003911c) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003911c) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003911c) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_D_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_D_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF11_D_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF11_D_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF11_D_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF11_D_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF11_D_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF11_D_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_D_DFSR_NOT_2D_BMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF11_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00039120) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00039120) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00039120) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_D_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_D_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF12_D_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF12_D_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF12_D_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF12_D_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF12_D_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF12_D_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_D_DFSR_NOT_2D_BMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF12_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00039124) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00039124) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00039124) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_D_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_D_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF13_D_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF13_D_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF13_D_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF13_D_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF13_D_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF13_D_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_D_DFSR_NOT_2D_BMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF13_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00039128) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00039128) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00039128) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_D_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_D_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF14_D_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF14_D_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF14_D_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF14_D_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF14_D_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF14_D_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_D_DFSR_NOT_2D_BMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF14_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003912c) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003912c) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003912c) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_D_DFSR_RMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_D_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF15_D_DFSR_ADDR, HWIO_GCC_RPMH_QPIC_QPIC_PERF15_D_DFSR_RMSK) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_QPIC_PERF15_D_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_QPIC_PERF15_D_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_QPIC_PERF15_D_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QPIC_QPIC_PERF15_D_DFSR_IN) +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_D_DFSR_NOT_2D_BMSK 0xff +#define HWIO_GCC_RPMH_QPIC_QPIC_PERF15_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QPIC_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00039014) +#define HWIO_GCC_QPIC_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00039014) +#define HWIO_GCC_QPIC_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00039014) +#define HWIO_GCC_QPIC_CMD_RCGR_RMSK 0x800000f3 +#define HWIO_GCC_QPIC_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_QPIC_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_QPIC_CMD_RCGR_ADDR, HWIO_GCC_QPIC_CMD_RCGR_RMSK) +#define HWIO_GCC_QPIC_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QPIC_CMD_RCGR_ADDR, m) +#define HWIO_GCC_QPIC_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QPIC_CMD_RCGR_ADDR,v) +#define HWIO_GCC_QPIC_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QPIC_CMD_RCGR_ADDR,m,v,HWIO_GCC_QPIC_CMD_RCGR_IN) +#define HWIO_GCC_QPIC_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_QPIC_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_QPIC_CMD_RCGR_DIRTY_D_BMSK 0x80 +#define HWIO_GCC_QPIC_CMD_RCGR_DIRTY_D_SHFT 0x7 +#define HWIO_GCC_QPIC_CMD_RCGR_DIRTY_N_BMSK 0x40 +#define HWIO_GCC_QPIC_CMD_RCGR_DIRTY_N_SHFT 0x6 +#define HWIO_GCC_QPIC_CMD_RCGR_DIRTY_M_BMSK 0x20 +#define HWIO_GCC_QPIC_CMD_RCGR_DIRTY_M_SHFT 0x5 +#define HWIO_GCC_QPIC_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_QPIC_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_QPIC_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_QPIC_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_QPIC_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_QPIC_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_QPIC_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_QPIC_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_QPIC_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QPIC_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QPIC_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00039018) +#define HWIO_GCC_QPIC_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00039018) +#define HWIO_GCC_QPIC_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00039018) +#define HWIO_GCC_QPIC_CFG_RCGR_RMSK 0x10371f +#define HWIO_GCC_QPIC_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_QPIC_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_QPIC_CFG_RCGR_ADDR, HWIO_GCC_QPIC_CFG_RCGR_RMSK) +#define HWIO_GCC_QPIC_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QPIC_CFG_RCGR_ADDR, m) +#define HWIO_GCC_QPIC_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QPIC_CFG_RCGR_ADDR,v) +#define HWIO_GCC_QPIC_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QPIC_CFG_RCGR_ADDR,m,v,HWIO_GCC_QPIC_CFG_RCGR_IN) +#define HWIO_GCC_QPIC_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_QPIC_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_QPIC_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QPIC_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QPIC_CFG_RCGR_MODE_BMSK 0x3000 +#define HWIO_GCC_QPIC_CFG_RCGR_MODE_SHFT 0xc +#define HWIO_GCC_QPIC_CFG_RCGR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QPIC_CFG_RCGR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QPIC_CFG_RCGR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QPIC_CFG_RCGR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QPIC_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QPIC_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QPIC_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QPIC_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QPIC_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QPIC_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QPIC_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QPIC_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QPIC_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QPIC_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QPIC_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QPIC_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QPIC_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QPIC_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QPIC_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QPIC_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QPIC_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QPIC_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QPIC_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QPIC_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QPIC_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QPIC_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QPIC_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QPIC_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QPIC_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QPIC_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QPIC_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QPIC_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QPIC_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QPIC_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QPIC_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QPIC_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QPIC_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QPIC_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QPIC_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QPIC_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QPIC_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QPIC_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QPIC_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QPIC_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QPIC_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QPIC_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QPIC_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QPIC_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QPIC_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003901c) +#define HWIO_GCC_QPIC_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003901c) +#define HWIO_GCC_QPIC_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003901c) +#define HWIO_GCC_QPIC_M_RMSK 0xff +#define HWIO_GCC_QPIC_M_ATTR 0x3 +#define HWIO_GCC_QPIC_M_IN \ + in_dword_masked(HWIO_GCC_QPIC_M_ADDR, HWIO_GCC_QPIC_M_RMSK) +#define HWIO_GCC_QPIC_M_INM(m) \ + in_dword_masked(HWIO_GCC_QPIC_M_ADDR, m) +#define HWIO_GCC_QPIC_M_OUT(v) \ + out_dword(HWIO_GCC_QPIC_M_ADDR,v) +#define HWIO_GCC_QPIC_M_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QPIC_M_ADDR,m,v,HWIO_GCC_QPIC_M_IN) +#define HWIO_GCC_QPIC_M_M_BMSK 0xff +#define HWIO_GCC_QPIC_M_M_SHFT 0x0 + +#define HWIO_GCC_QPIC_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00039020) +#define HWIO_GCC_QPIC_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00039020) +#define HWIO_GCC_QPIC_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00039020) +#define HWIO_GCC_QPIC_N_RMSK 0xff +#define HWIO_GCC_QPIC_N_ATTR 0x3 +#define HWIO_GCC_QPIC_N_IN \ + in_dword_masked(HWIO_GCC_QPIC_N_ADDR, HWIO_GCC_QPIC_N_RMSK) +#define HWIO_GCC_QPIC_N_INM(m) \ + in_dword_masked(HWIO_GCC_QPIC_N_ADDR, m) +#define HWIO_GCC_QPIC_N_OUT(v) \ + out_dword(HWIO_GCC_QPIC_N_ADDR,v) +#define HWIO_GCC_QPIC_N_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QPIC_N_ADDR,m,v,HWIO_GCC_QPIC_N_IN) +#define HWIO_GCC_QPIC_N_NOT_N_MINUS_M_BMSK 0xff +#define HWIO_GCC_QPIC_N_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QPIC_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00039024) +#define HWIO_GCC_QPIC_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00039024) +#define HWIO_GCC_QPIC_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00039024) +#define HWIO_GCC_QPIC_D_RMSK 0xff +#define HWIO_GCC_QPIC_D_ATTR 0x3 +#define HWIO_GCC_QPIC_D_IN \ + in_dword_masked(HWIO_GCC_QPIC_D_ADDR, HWIO_GCC_QPIC_D_RMSK) +#define HWIO_GCC_QPIC_D_INM(m) \ + in_dword_masked(HWIO_GCC_QPIC_D_ADDR, m) +#define HWIO_GCC_QPIC_D_OUT(v) \ + out_dword(HWIO_GCC_QPIC_D_ADDR,v) +#define HWIO_GCC_QPIC_D_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QPIC_D_ADDR,m,v,HWIO_GCC_QPIC_D_IN) +#define HWIO_GCC_QPIC_D_NOT_2D_BMSK 0xff +#define HWIO_GCC_QPIC_D_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_SPMI_FETCHER_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003a000) +#define HWIO_GCC_SPMI_FETCHER_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003a000) +#define HWIO_GCC_SPMI_FETCHER_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003a000) +#define HWIO_GCC_SPMI_FETCHER_BCR_RMSK 0x1 +#define HWIO_GCC_SPMI_FETCHER_BCR_ATTR 0x3 +#define HWIO_GCC_SPMI_FETCHER_BCR_IN \ + in_dword_masked(HWIO_GCC_SPMI_FETCHER_BCR_ADDR, HWIO_GCC_SPMI_FETCHER_BCR_RMSK) +#define HWIO_GCC_SPMI_FETCHER_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_SPMI_FETCHER_BCR_ADDR, m) +#define HWIO_GCC_SPMI_FETCHER_BCR_OUT(v) \ + out_dword(HWIO_GCC_SPMI_FETCHER_BCR_ADDR,v) +#define HWIO_GCC_SPMI_FETCHER_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPMI_FETCHER_BCR_ADDR,m,v,HWIO_GCC_SPMI_FETCHER_BCR_IN) +#define HWIO_GCC_SPMI_FETCHER_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_SPMI_FETCHER_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_SPMI_FETCHER_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPMI_FETCHER_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPMI_FETCHER_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003a004) +#define HWIO_GCC_SPMI_FETCHER_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003a004) +#define HWIO_GCC_SPMI_FETCHER_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003a004) +#define HWIO_GCC_SPMI_FETCHER_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_SPMI_FETCHER_CBCR_ATTR 0x3 +#define HWIO_GCC_SPMI_FETCHER_CBCR_IN \ + in_dword_masked(HWIO_GCC_SPMI_FETCHER_CBCR_ADDR, HWIO_GCC_SPMI_FETCHER_CBCR_RMSK) +#define HWIO_GCC_SPMI_FETCHER_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_SPMI_FETCHER_CBCR_ADDR, m) +#define HWIO_GCC_SPMI_FETCHER_CBCR_OUT(v) \ + out_dword(HWIO_GCC_SPMI_FETCHER_CBCR_ADDR,v) +#define HWIO_GCC_SPMI_FETCHER_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPMI_FETCHER_CBCR_ADDR,m,v,HWIO_GCC_SPMI_FETCHER_CBCR_IN) +#define HWIO_GCC_SPMI_FETCHER_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SPMI_FETCHER_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SPMI_FETCHER_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_SPMI_FETCHER_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_SPMI_FETCHER_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_SPMI_FETCHER_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_SPMI_FETCHER_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_SPMI_FETCHER_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_SPMI_FETCHER_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_SPMI_FETCHER_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_SPMI_FETCHER_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SPMI_FETCHER_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_SPMI_FETCHER_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SPMI_FETCHER_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SPMI_FETCHER_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPMI_FETCHER_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPMI_FETCHER_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003a008) +#define HWIO_GCC_SPMI_FETCHER_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003a008) +#define HWIO_GCC_SPMI_FETCHER_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003a008) +#define HWIO_GCC_SPMI_FETCHER_AHB_CBCR_RMSK 0x81d00005 +#define HWIO_GCC_SPMI_FETCHER_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_SPMI_FETCHER_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_SPMI_FETCHER_AHB_CBCR_ADDR, HWIO_GCC_SPMI_FETCHER_AHB_CBCR_RMSK) +#define HWIO_GCC_SPMI_FETCHER_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_SPMI_FETCHER_AHB_CBCR_ADDR, m) +#define HWIO_GCC_SPMI_FETCHER_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_SPMI_FETCHER_AHB_CBCR_ADDR,v) +#define HWIO_GCC_SPMI_FETCHER_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPMI_FETCHER_AHB_CBCR_ADDR,m,v,HWIO_GCC_SPMI_FETCHER_AHB_CBCR_IN) +#define HWIO_GCC_SPMI_FETCHER_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SPMI_FETCHER_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SPMI_FETCHER_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_SPMI_FETCHER_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_SPMI_FETCHER_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_SPMI_FETCHER_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_SPMI_FETCHER_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_SPMI_FETCHER_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_SPMI_FETCHER_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_SPMI_FETCHER_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_SPMI_FETCHER_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_SPMI_FETCHER_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_SPMI_FETCHER_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SPMI_FETCHER_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_SPMI_FETCHER_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SPMI_FETCHER_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SPMI_FETCHER_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPMI_FETCHER_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPMI_FETCHER_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003a00c) +#define HWIO_GCC_SPMI_FETCHER_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003a00c) +#define HWIO_GCC_SPMI_FETCHER_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003a00c) +#define HWIO_GCC_SPMI_FETCHER_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_SPMI_FETCHER_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_SPMI_FETCHER_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_SPMI_FETCHER_CMD_RCGR_ADDR, HWIO_GCC_SPMI_FETCHER_CMD_RCGR_RMSK) +#define HWIO_GCC_SPMI_FETCHER_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_SPMI_FETCHER_CMD_RCGR_ADDR, m) +#define HWIO_GCC_SPMI_FETCHER_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_SPMI_FETCHER_CMD_RCGR_ADDR,v) +#define HWIO_GCC_SPMI_FETCHER_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPMI_FETCHER_CMD_RCGR_ADDR,m,v,HWIO_GCC_SPMI_FETCHER_CMD_RCGR_IN) +#define HWIO_GCC_SPMI_FETCHER_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_SPMI_FETCHER_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_SPMI_FETCHER_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_SPMI_FETCHER_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_SPMI_FETCHER_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_SPMI_FETCHER_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_SPMI_FETCHER_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPMI_FETCHER_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPMI_FETCHER_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_SPMI_FETCHER_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_SPMI_FETCHER_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPMI_FETCHER_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPMI_FETCHER_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003a010) +#define HWIO_GCC_SPMI_FETCHER_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003a010) +#define HWIO_GCC_SPMI_FETCHER_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003a010) +#define HWIO_GCC_SPMI_FETCHER_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_SPMI_FETCHER_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_SPMI_FETCHER_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_SPMI_FETCHER_CFG_RCGR_ADDR, HWIO_GCC_SPMI_FETCHER_CFG_RCGR_RMSK) +#define HWIO_GCC_SPMI_FETCHER_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_SPMI_FETCHER_CFG_RCGR_ADDR, m) +#define HWIO_GCC_SPMI_FETCHER_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_SPMI_FETCHER_CFG_RCGR_ADDR,v) +#define HWIO_GCC_SPMI_FETCHER_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPMI_FETCHER_CFG_RCGR_ADDR,m,v,HWIO_GCC_SPMI_FETCHER_CFG_RCGR_IN) +#define HWIO_GCC_SPMI_FETCHER_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_SPMI_FETCHER_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_SPMI_FETCHER_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPMI_FETCHER_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPMI_FETCHER_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_SPMI_FETCHER_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_SPMI_FETCHER_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_SPMI_FETCHER_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_SPMI_FETCHER_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_SPMI_FETCHER_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_SPMI_FETCHER_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_SPMI_FETCHER_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_SPMI_FETCHER_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_SPMI_FETCHER_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_SPMI_FETCHER_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_SPMI_FETCHER_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_SPMI_FETCHER_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_SPMI_FETCHER_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_SPMI_FETCHER_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_SPMI_FETCHER_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_SPMI_FETCHER_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_SPMI_FETCHER_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_SPMI_FETCHER_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_SPMI_FETCHER_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_SPMI_FETCHER_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_SPMI_FETCHER_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_SPMI_FETCHER_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_SPMI_FETCHER_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_SPMI_FETCHER_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_SPMI_FETCHER_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_SPMI_FETCHER_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_SPMI_FETCHER_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_SPMI_FETCHER_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_SPMI_FETCHER_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_SPMI_FETCHER_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_SPMI_FETCHER_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_SPMI_FETCHER_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_SPMI_FETCHER_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_SPMI_FETCHER_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_SPMI_FETCHER_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_SPMI_FETCHER_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_SPMI_FETCHER_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_SPMI_FETCHER_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_SPMI_FETCHER_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_SPMI_FETCHER_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_SPMI_FETCHER_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_SPMI_FETCHER_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_SPMI_FETCHER_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_SPMI_FETCHER_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_SPMI_FETCHER_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_SPMI_FETCHER_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_SPMI_FETCHER_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_MSS_CFG_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003b000) +#define HWIO_GCC_MSS_CFG_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003b000) +#define HWIO_GCC_MSS_CFG_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003b000) +#define HWIO_GCC_MSS_CFG_AHB_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_MSS_CFG_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_MSS_CFG_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_MSS_CFG_AHB_CBCR_ADDR, HWIO_GCC_MSS_CFG_AHB_CBCR_RMSK) +#define HWIO_GCC_MSS_CFG_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_CFG_AHB_CBCR_ADDR, m) +#define HWIO_GCC_MSS_CFG_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_MSS_CFG_AHB_CBCR_ADDR,v) +#define HWIO_GCC_MSS_CFG_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_CFG_AHB_CBCR_ADDR,m,v,HWIO_GCC_MSS_CFG_AHB_CBCR_IN) +#define HWIO_GCC_MSS_CFG_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_MSS_CFG_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_MSS_CFG_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_MSS_CFG_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_MSS_CFG_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_MSS_CFG_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_MSS_CFG_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_MSS_CFG_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_MSS_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_MSS_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_MSS_CFG_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_MSS_CFG_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_MSS_CFG_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_MSS_CFG_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_MSS_CFG_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_MSS_CFG_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_MSS_CFG_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_MSS_CFG_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_MSS_CFG_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_CFG_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_CFG_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_MSS_CFG_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_MSS_CFG_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_CFG_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003b004) +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003b004) +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003b004) +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_ATTR 0x3 +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_IN \ + in_dword_masked(HWIO_GCC_MSS_OFFLINE_AXI_CBCR_ADDR, HWIO_GCC_MSS_OFFLINE_AXI_CBCR_RMSK) +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_OFFLINE_AXI_CBCR_ADDR, m) +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_OUT(v) \ + out_dword(HWIO_GCC_MSS_OFFLINE_AXI_CBCR_ADDR,v) +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_OFFLINE_AXI_CBCR_ADDR,m,v,HWIO_GCC_MSS_OFFLINE_AXI_CBCR_IN) +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_CE_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003b008) +#define HWIO_GCC_MSS_CE_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003b008) +#define HWIO_GCC_MSS_CE_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003b008) +#define HWIO_GCC_MSS_CE_AXI_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_MSS_CE_AXI_CBCR_ATTR 0x3 +#define HWIO_GCC_MSS_CE_AXI_CBCR_IN \ + in_dword_masked(HWIO_GCC_MSS_CE_AXI_CBCR_ADDR, HWIO_GCC_MSS_CE_AXI_CBCR_RMSK) +#define HWIO_GCC_MSS_CE_AXI_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_CE_AXI_CBCR_ADDR, m) +#define HWIO_GCC_MSS_CE_AXI_CBCR_OUT(v) \ + out_dword(HWIO_GCC_MSS_CE_AXI_CBCR_ADDR,v) +#define HWIO_GCC_MSS_CE_AXI_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_CE_AXI_CBCR_ADDR,m,v,HWIO_GCC_MSS_CE_AXI_CBCR_IN) +#define HWIO_GCC_MSS_CE_AXI_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_MSS_CE_AXI_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_MSS_CE_AXI_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_MSS_CE_AXI_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_MSS_CE_AXI_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_MSS_CE_AXI_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_MSS_CE_AXI_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_MSS_CE_AXI_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_MSS_CE_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_MSS_CE_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_MSS_CE_AXI_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_MSS_CE_AXI_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_MSS_CE_AXI_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_MSS_CE_AXI_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_MSS_CE_AXI_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_MSS_CE_AXI_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_MSS_CE_AXI_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_MSS_CE_AXI_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_MSS_CE_AXI_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_CE_AXI_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_CE_AXI_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_MSS_CE_AXI_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_MSS_CE_AXI_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_CE_AXI_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_TRIG_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003b00c) +#define HWIO_GCC_MSS_TRIG_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003b00c) +#define HWIO_GCC_MSS_TRIG_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003b00c) +#define HWIO_GCC_MSS_TRIG_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_MSS_TRIG_CBCR_ATTR 0x3 +#define HWIO_GCC_MSS_TRIG_CBCR_IN \ + in_dword_masked(HWIO_GCC_MSS_TRIG_CBCR_ADDR, HWIO_GCC_MSS_TRIG_CBCR_RMSK) +#define HWIO_GCC_MSS_TRIG_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_TRIG_CBCR_ADDR, m) +#define HWIO_GCC_MSS_TRIG_CBCR_OUT(v) \ + out_dword(HWIO_GCC_MSS_TRIG_CBCR_ADDR,v) +#define HWIO_GCC_MSS_TRIG_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_TRIG_CBCR_ADDR,m,v,HWIO_GCC_MSS_TRIG_CBCR_IN) +#define HWIO_GCC_MSS_TRIG_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_MSS_TRIG_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_MSS_TRIG_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_MSS_TRIG_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_MSS_TRIG_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_MSS_TRIG_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_MSS_TRIG_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_MSS_TRIG_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_MSS_TRIG_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_MSS_TRIG_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_MSS_TRIG_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_MSS_TRIG_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_MSS_TRIG_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_MSS_TRIG_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_MSS_TRIG_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_MSS_TRIG_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_MSS_TRIG_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_MSS_TRIG_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_MSS_TRIG_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_TRIG_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_TRIG_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_MSS_TRIG_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_MSS_TRIG_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_TRIG_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003b010) +#define HWIO_GCC_MSS_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003b010) +#define HWIO_GCC_MSS_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003b010) +#define HWIO_GCC_MSS_AT_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_MSS_AT_CBCR_ATTR 0x3 +#define HWIO_GCC_MSS_AT_CBCR_IN \ + in_dword_masked(HWIO_GCC_MSS_AT_CBCR_ADDR, HWIO_GCC_MSS_AT_CBCR_RMSK) +#define HWIO_GCC_MSS_AT_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_AT_CBCR_ADDR, m) +#define HWIO_GCC_MSS_AT_CBCR_OUT(v) \ + out_dword(HWIO_GCC_MSS_AT_CBCR_ADDR,v) +#define HWIO_GCC_MSS_AT_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_AT_CBCR_ADDR,m,v,HWIO_GCC_MSS_AT_CBCR_IN) +#define HWIO_GCC_MSS_AT_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_MSS_AT_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_MSS_AT_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_MSS_AT_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_MSS_AT_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_MSS_AT_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_MSS_AT_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_MSS_AT_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_MSS_AT_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_MSS_AT_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_MSS_AT_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_MSS_AT_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_MSS_AT_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_MSS_AT_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_MSS_AT_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_MSS_AT_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_MSS_AT_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_MSS_AT_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_MSS_AT_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_AT_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_AT_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_MSS_AT_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_MSS_AT_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_AT_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_PLL0_MAIN_DIV_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003b014) +#define HWIO_GCC_MSS_PLL0_MAIN_DIV_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003b014) +#define HWIO_GCC_MSS_PLL0_MAIN_DIV_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003b014) +#define HWIO_GCC_MSS_PLL0_MAIN_DIV_CDIVR_RMSK 0xf +#define HWIO_GCC_MSS_PLL0_MAIN_DIV_CDIVR_ATTR 0x3 +#define HWIO_GCC_MSS_PLL0_MAIN_DIV_CDIVR_IN \ + in_dword_masked(HWIO_GCC_MSS_PLL0_MAIN_DIV_CDIVR_ADDR, HWIO_GCC_MSS_PLL0_MAIN_DIV_CDIVR_RMSK) +#define HWIO_GCC_MSS_PLL0_MAIN_DIV_CDIVR_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_PLL0_MAIN_DIV_CDIVR_ADDR, m) +#define HWIO_GCC_MSS_PLL0_MAIN_DIV_CDIVR_OUT(v) \ + out_dword(HWIO_GCC_MSS_PLL0_MAIN_DIV_CDIVR_ADDR,v) +#define HWIO_GCC_MSS_PLL0_MAIN_DIV_CDIVR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_PLL0_MAIN_DIV_CDIVR_ADDR,m,v,HWIO_GCC_MSS_PLL0_MAIN_DIV_CDIVR_IN) +#define HWIO_GCC_MSS_PLL0_MAIN_DIV_CDIVR_CLK_DIV_BMSK 0xf +#define HWIO_GCC_MSS_PLL0_MAIN_DIV_CDIVR_CLK_DIV_SHFT 0x0 + +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003b034) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003b034) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003b034) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF0_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF0_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF0_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF0_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003b038) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003b038) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003b038) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF1_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF1_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF1_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF1_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003b03c) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003b03c) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003b03c) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF2_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF2_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF2_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF2_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003b040) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003b040) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003b040) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF3_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF3_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF3_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF3_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003b044) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003b044) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003b044) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF4_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF4_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF4_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF4_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003b048) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003b048) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003b048) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF5_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF5_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF5_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF5_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003b04c) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003b04c) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003b04c) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF6_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF6_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF6_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF6_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003b050) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003b050) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003b050) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF7_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF7_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF7_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF7_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF8_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003b054) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF8_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003b054) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF8_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003b054) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF8_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF8_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF8_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF8_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF8_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF8_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF8_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF8_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF8_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF8_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF8_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF8_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF8_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF8_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF8_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF8_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF8_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF8_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF8_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF8_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF8_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF8_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF8_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF8_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF8_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF8_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF8_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF8_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF8_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF8_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF8_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF8_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF8_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF8_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF8_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF8_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF8_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF8_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF8_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF8_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF8_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF8_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF8_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF8_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF8_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF8_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF8_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF8_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF8_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF8_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF8_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF8_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF8_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF8_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF8_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF9_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003b058) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF9_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003b058) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF9_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003b058) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF9_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF9_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF9_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF9_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF9_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF9_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF9_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF9_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF9_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF9_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF9_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF9_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF9_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF9_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF9_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF9_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF9_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF9_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF9_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF9_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF9_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF9_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF9_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF9_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF9_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF9_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF9_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF9_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF9_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF9_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF9_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF9_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF9_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF9_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF9_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF9_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF9_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF9_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF9_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF9_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF9_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF9_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF9_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF9_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF9_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF9_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF9_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF9_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF9_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF9_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF9_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF9_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF9_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF9_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF9_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF10_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003b05c) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF10_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003b05c) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF10_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003b05c) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF10_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF10_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF10_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF10_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF10_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF10_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF10_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF10_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF10_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF10_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF10_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF10_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF10_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF10_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF10_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF10_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF10_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF10_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF10_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF10_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF10_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF10_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF10_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF10_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF10_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF10_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF10_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF10_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF10_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF10_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF10_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF10_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF10_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF10_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF10_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF10_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF10_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF10_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF10_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF10_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF10_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF10_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF10_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF10_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF10_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF10_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF10_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF10_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF10_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF10_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF10_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF10_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF10_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF10_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF10_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF11_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003b060) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF11_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003b060) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF11_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003b060) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF11_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF11_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF11_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF11_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF11_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF11_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF11_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF11_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF11_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF11_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF11_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF11_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF11_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF11_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF11_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF11_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF11_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF11_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF11_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF11_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF11_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF11_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF11_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF11_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF11_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF11_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF11_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF11_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF11_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF11_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF11_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF11_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF11_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF11_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF11_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF11_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF11_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF11_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF11_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF11_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF11_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF11_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF11_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF11_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF11_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF11_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF11_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF11_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF11_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF11_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF11_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF11_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF11_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF11_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF11_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF12_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003b064) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF12_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003b064) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF12_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003b064) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF12_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF12_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF12_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF12_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF12_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF12_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF12_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF12_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF12_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF12_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF12_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF12_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF12_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF12_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF12_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF12_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF12_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF12_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF12_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF12_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF12_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF12_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF12_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF12_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF12_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF12_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF12_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF12_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF12_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF12_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF12_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF12_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF12_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF12_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF12_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF12_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF12_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF12_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF12_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF12_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF12_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF12_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF12_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF12_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF12_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF12_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF12_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF12_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF12_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF12_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF12_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF12_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF12_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF12_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF12_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF13_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003b068) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF13_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003b068) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF13_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003b068) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF13_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF13_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF13_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF13_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF13_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF13_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF13_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF13_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF13_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF13_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF13_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF13_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF13_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF13_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF13_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF13_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF13_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF13_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF13_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF13_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF13_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF13_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF13_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF13_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF13_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF13_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF13_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF13_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF13_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF13_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF13_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF13_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF13_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF13_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF13_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF13_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF13_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF13_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF13_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF13_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF13_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF13_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF13_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF13_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF13_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF13_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF13_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF13_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF13_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF13_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF13_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF13_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF13_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF13_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF13_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF14_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003b06c) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF14_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003b06c) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF14_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003b06c) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF14_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF14_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF14_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF14_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF14_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF14_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF14_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF14_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF14_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF14_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF14_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF14_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF14_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF14_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF14_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF14_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF14_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF14_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF14_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF14_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF14_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF14_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF14_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF14_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF14_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF14_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF14_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF14_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF14_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF14_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF14_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF14_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF14_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF14_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF14_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF14_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF14_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF14_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF14_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF14_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF14_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF14_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF14_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF14_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF14_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF14_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF14_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF14_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF14_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF14_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF14_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF14_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF14_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF14_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF14_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF15_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003b070) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF15_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003b070) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF15_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003b070) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF15_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF15_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF15_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF15_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF15_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF15_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF15_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF15_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF15_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF15_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF15_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF15_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF15_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF15_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF15_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF15_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF15_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF15_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF15_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF15_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF15_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF15_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF15_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF15_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF15_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF15_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF15_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF15_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF15_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF15_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF15_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF15_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF15_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF15_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF15_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF15_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF15_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF15_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF15_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF15_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF15_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF15_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF15_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF15_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF15_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF15_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF15_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF15_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF15_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF15_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF15_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF15_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF15_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF15_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF15_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003b018) +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003b018) +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003b018) +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_MSS_MCDMA_MEMNOC_CMD_RCGR_ADDR, HWIO_GCC_MSS_MCDMA_MEMNOC_CMD_RCGR_RMSK) +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_MCDMA_MEMNOC_CMD_RCGR_ADDR, m) +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_MSS_MCDMA_MEMNOC_CMD_RCGR_ADDR,v) +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_MCDMA_MEMNOC_CMD_RCGR_ADDR,m,v,HWIO_GCC_MSS_MCDMA_MEMNOC_CMD_RCGR_IN) +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003b01c) +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003b01c) +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003b01c) +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_ADDR, HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_RMSK) +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_ADDR, m) +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_ADDR,v) +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_ADDR,m,v,HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_IN) +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_MSS_MCDMA_MEMNOC_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003b148) +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003b148) +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003b148) +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_RMSK 0x81d00005 +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_ATTR 0x3 +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_IN \ + in_dword_masked(HWIO_GCC_MSS_SNOC_AXI_CBCR_ADDR, HWIO_GCC_MSS_SNOC_AXI_CBCR_RMSK) +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_SNOC_AXI_CBCR_ADDR, m) +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_OUT(v) \ + out_dword(HWIO_GCC_MSS_SNOC_AXI_CBCR_ADDR,v) +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_SNOC_AXI_CBCR_ADDR,m,v,HWIO_GCC_MSS_SNOC_AXI_CBCR_IN) +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_Q6VQ6_AXIM1_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003b14c) +#define HWIO_GCC_MSS_Q6VQ6_AXIM1_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003b14c) +#define HWIO_GCC_MSS_Q6VQ6_AXIM1_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003b14c) +#define HWIO_GCC_MSS_Q6VQ6_AXIM1_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_MSS_Q6VQ6_AXIM1_CBCR_ATTR 0x3 +#define HWIO_GCC_MSS_Q6VQ6_AXIM1_CBCR_IN \ + in_dword_masked(HWIO_GCC_MSS_Q6VQ6_AXIM1_CBCR_ADDR, HWIO_GCC_MSS_Q6VQ6_AXIM1_CBCR_RMSK) +#define HWIO_GCC_MSS_Q6VQ6_AXIM1_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_Q6VQ6_AXIM1_CBCR_ADDR, m) +#define HWIO_GCC_MSS_Q6VQ6_AXIM1_CBCR_OUT(v) \ + out_dword(HWIO_GCC_MSS_Q6VQ6_AXIM1_CBCR_ADDR,v) +#define HWIO_GCC_MSS_Q6VQ6_AXIM1_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_Q6VQ6_AXIM1_CBCR_ADDR,m,v,HWIO_GCC_MSS_Q6VQ6_AXIM1_CBCR_IN) +#define HWIO_GCC_MSS_Q6VQ6_AXIM1_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_MSS_Q6VQ6_AXIM1_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_MSS_Q6VQ6_AXIM1_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_MSS_Q6VQ6_AXIM1_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_MSS_Q6VQ6_AXIM1_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_MSS_Q6VQ6_AXIM1_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_MSS_Q6VQ6_AXIM1_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_MSS_Q6VQ6_AXIM1_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_MSS_Q6VQ6_AXIM1_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_MSS_Q6VQ6_AXIM1_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_MSS_Q6VQ6_AXIM1_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_MSS_Q6VQ6_AXIM1_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_MSS_Q6VQ6_AXIM1_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_MSS_Q6VQ6_AXIM1_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_MSS_Q6VQ6_AXIM1_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_MSS_Q6VQ6_AXIM1_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_MSS_Q6VQ6_AXIM1_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_MSS_Q6VQ6_AXIM1_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_MSS_Q6VQ6_AXIM1_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6VQ6_AXIM1_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6VQ6_AXIM1_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_MSS_Q6VQ6_AXIM1_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_MSS_Q6VQ6_AXIM1_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6VQ6_AXIM1_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QREFS_VBG_CAL_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003c000) +#define HWIO_GCC_QREFS_VBG_CAL_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003c000) +#define HWIO_GCC_QREFS_VBG_CAL_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003c000) +#define HWIO_GCC_QREFS_VBG_CAL_BCR_RMSK 0x1 +#define HWIO_GCC_QREFS_VBG_CAL_BCR_ATTR 0x3 +#define HWIO_GCC_QREFS_VBG_CAL_BCR_IN \ + in_dword_masked(HWIO_GCC_QREFS_VBG_CAL_BCR_ADDR, HWIO_GCC_QREFS_VBG_CAL_BCR_RMSK) +#define HWIO_GCC_QREFS_VBG_CAL_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_QREFS_VBG_CAL_BCR_ADDR, m) +#define HWIO_GCC_QREFS_VBG_CAL_BCR_OUT(v) \ + out_dword(HWIO_GCC_QREFS_VBG_CAL_BCR_ADDR,v) +#define HWIO_GCC_QREFS_VBG_CAL_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QREFS_VBG_CAL_BCR_ADDR,m,v,HWIO_GCC_QREFS_VBG_CAL_BCR_IN) +#define HWIO_GCC_QREFS_VBG_CAL_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_QREFS_VBG_CAL_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_QREFS_VBG_CAL_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_QREFS_VBG_CAL_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QREFS_VBG_CAL_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003c004) +#define HWIO_GCC_QREFS_VBG_CAL_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003c004) +#define HWIO_GCC_QREFS_VBG_CAL_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003c004) +#define HWIO_GCC_QREFS_VBG_CAL_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_QREFS_VBG_CAL_CBCR_ATTR 0x3 +#define HWIO_GCC_QREFS_VBG_CAL_CBCR_IN \ + in_dword_masked(HWIO_GCC_QREFS_VBG_CAL_CBCR_ADDR, HWIO_GCC_QREFS_VBG_CAL_CBCR_RMSK) +#define HWIO_GCC_QREFS_VBG_CAL_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QREFS_VBG_CAL_CBCR_ADDR, m) +#define HWIO_GCC_QREFS_VBG_CAL_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QREFS_VBG_CAL_CBCR_ADDR,v) +#define HWIO_GCC_QREFS_VBG_CAL_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QREFS_VBG_CAL_CBCR_ADDR,m,v,HWIO_GCC_QREFS_VBG_CAL_CBCR_IN) +#define HWIO_GCC_QREFS_VBG_CAL_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QREFS_VBG_CAL_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QREFS_VBG_CAL_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QREFS_VBG_CAL_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QREFS_VBG_CAL_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QREFS_VBG_CAL_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QREFS_VBG_CAL_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QREFS_VBG_CAL_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QREFS_VBG_CAL_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QREFS_VBG_CAL_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QREFS_VBG_CAL_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QREFS_VBG_CAL_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_QREFS_VBG_CAL_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_QREFS_VBG_CAL_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_QREFS_VBG_CAL_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QREFS_VBG_CAL_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_NAV_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003d000) +#define HWIO_GCC_NAV_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003d000) +#define HWIO_GCC_NAV_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003d000) +#define HWIO_GCC_NAV_BCR_RMSK 0x1 +#define HWIO_GCC_NAV_BCR_ATTR 0x3 +#define HWIO_GCC_NAV_BCR_IN \ + in_dword_masked(HWIO_GCC_NAV_BCR_ADDR, HWIO_GCC_NAV_BCR_RMSK) +#define HWIO_GCC_NAV_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_NAV_BCR_ADDR, m) +#define HWIO_GCC_NAV_BCR_OUT(v) \ + out_dword(HWIO_GCC_NAV_BCR_ADDR,v) +#define HWIO_GCC_NAV_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_NAV_BCR_ADDR,m,v,HWIO_GCC_NAV_BCR_IN) +#define HWIO_GCC_NAV_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_NAV_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_NAV_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_NAV_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_NAV_SNOC_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003d004) +#define HWIO_GCC_NAV_SNOC_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003d004) +#define HWIO_GCC_NAV_SNOC_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003d004) +#define HWIO_GCC_NAV_SNOC_AXI_CBCR_RMSK 0x81d00005 +#define HWIO_GCC_NAV_SNOC_AXI_CBCR_ATTR 0x3 +#define HWIO_GCC_NAV_SNOC_AXI_CBCR_IN \ + in_dword_masked(HWIO_GCC_NAV_SNOC_AXI_CBCR_ADDR, HWIO_GCC_NAV_SNOC_AXI_CBCR_RMSK) +#define HWIO_GCC_NAV_SNOC_AXI_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_NAV_SNOC_AXI_CBCR_ADDR, m) +#define HWIO_GCC_NAV_SNOC_AXI_CBCR_OUT(v) \ + out_dword(HWIO_GCC_NAV_SNOC_AXI_CBCR_ADDR,v) +#define HWIO_GCC_NAV_SNOC_AXI_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_NAV_SNOC_AXI_CBCR_ADDR,m,v,HWIO_GCC_NAV_SNOC_AXI_CBCR_IN) +#define HWIO_GCC_NAV_SNOC_AXI_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_NAV_SNOC_AXI_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_NAV_SNOC_AXI_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_NAV_SNOC_AXI_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_NAV_SNOC_AXI_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_NAV_SNOC_AXI_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_NAV_SNOC_AXI_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_NAV_SNOC_AXI_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_NAV_SNOC_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_NAV_SNOC_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_NAV_SNOC_AXI_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_NAV_SNOC_AXI_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_NAV_SNOC_AXI_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_NAV_SNOC_AXI_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_NAV_SNOC_AXI_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_NAV_SNOC_AXI_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_NAV_SNOC_AXI_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_NAV_SNOC_AXI_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GPLL4_OUT_EVEN_DIV_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003d010) +#define HWIO_GCC_GPLL4_OUT_EVEN_DIV_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003d010) +#define HWIO_GCC_GPLL4_OUT_EVEN_DIV_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003d010) +#define HWIO_GCC_GPLL4_OUT_EVEN_DIV_CDIVR_RMSK 0xf +#define HWIO_GCC_GPLL4_OUT_EVEN_DIV_CDIVR_ATTR 0x3 +#define HWIO_GCC_GPLL4_OUT_EVEN_DIV_CDIVR_IN \ + in_dword_masked(HWIO_GCC_GPLL4_OUT_EVEN_DIV_CDIVR_ADDR, HWIO_GCC_GPLL4_OUT_EVEN_DIV_CDIVR_RMSK) +#define HWIO_GCC_GPLL4_OUT_EVEN_DIV_CDIVR_INM(m) \ + in_dword_masked(HWIO_GCC_GPLL4_OUT_EVEN_DIV_CDIVR_ADDR, m) +#define HWIO_GCC_GPLL4_OUT_EVEN_DIV_CDIVR_OUT(v) \ + out_dword(HWIO_GCC_GPLL4_OUT_EVEN_DIV_CDIVR_ADDR,v) +#define HWIO_GCC_GPLL4_OUT_EVEN_DIV_CDIVR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPLL4_OUT_EVEN_DIV_CDIVR_ADDR,m,v,HWIO_GCC_GPLL4_OUT_EVEN_DIV_CDIVR_IN) +#define HWIO_GCC_GPLL4_OUT_EVEN_DIV_CDIVR_CLK_DIV_BMSK 0xf +#define HWIO_GCC_GPLL4_OUT_EVEN_DIV_CDIVR_CLK_DIV_SHFT 0x0 + +#define HWIO_GCC_CM_PHY_REFGEN1_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003e000) +#define HWIO_GCC_CM_PHY_REFGEN1_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003e000) +#define HWIO_GCC_CM_PHY_REFGEN1_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003e000) +#define HWIO_GCC_CM_PHY_REFGEN1_BCR_RMSK 0x1 +#define HWIO_GCC_CM_PHY_REFGEN1_BCR_ATTR 0x3 +#define HWIO_GCC_CM_PHY_REFGEN1_BCR_IN \ + in_dword_masked(HWIO_GCC_CM_PHY_REFGEN1_BCR_ADDR, HWIO_GCC_CM_PHY_REFGEN1_BCR_RMSK) +#define HWIO_GCC_CM_PHY_REFGEN1_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_CM_PHY_REFGEN1_BCR_ADDR, m) +#define HWIO_GCC_CM_PHY_REFGEN1_BCR_OUT(v) \ + out_dword(HWIO_GCC_CM_PHY_REFGEN1_BCR_ADDR,v) +#define HWIO_GCC_CM_PHY_REFGEN1_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CM_PHY_REFGEN1_BCR_ADDR,m,v,HWIO_GCC_CM_PHY_REFGEN1_BCR_IN) +#define HWIO_GCC_CM_PHY_REFGEN1_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_CM_PHY_REFGEN1_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_CM_PHY_REFGEN1_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_CM_PHY_REFGEN1_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003e004) +#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003e004) +#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003e004) +#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_RMSK 0x81c0000f +#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_ATTR 0x3 +#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_IN \ + in_dword_masked(HWIO_GCC_CM_PHY_REFGEN1_CBCR_ADDR, HWIO_GCC_CM_PHY_REFGEN1_CBCR_RMSK) +#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_CM_PHY_REFGEN1_CBCR_ADDR, m) +#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_OUT(v) \ + out_dword(HWIO_GCC_CM_PHY_REFGEN1_CBCR_ADDR,v) +#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CM_PHY_REFGEN1_CBCR_ADDR,m,v,HWIO_GCC_CM_PHY_REFGEN1_CBCR_IN) +#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_ECC_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00040000) +#define HWIO_GCC_ECC_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00040000) +#define HWIO_GCC_ECC_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00040000) +#define HWIO_GCC_ECC_BCR_RMSK 0x1 +#define HWIO_GCC_ECC_BCR_ATTR 0x3 +#define HWIO_GCC_ECC_BCR_IN \ + in_dword_masked(HWIO_GCC_ECC_BCR_ADDR, HWIO_GCC_ECC_BCR_RMSK) +#define HWIO_GCC_ECC_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_ECC_BCR_ADDR, m) +#define HWIO_GCC_ECC_BCR_OUT(v) \ + out_dword(HWIO_GCC_ECC_BCR_ADDR,v) +#define HWIO_GCC_ECC_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ECC_BCR_ADDR,m,v,HWIO_GCC_ECC_BCR_IN) +#define HWIO_GCC_ECC_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_ECC_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_ECC_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_ECC_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_ECC_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00040004) +#define HWIO_GCC_ECC_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00040004) +#define HWIO_GCC_ECC_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00040004) +#define HWIO_GCC_ECC_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_ECC_CBCR_ATTR 0x3 +#define HWIO_GCC_ECC_CBCR_IN \ + in_dword_masked(HWIO_GCC_ECC_CBCR_ADDR, HWIO_GCC_ECC_CBCR_RMSK) +#define HWIO_GCC_ECC_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_ECC_CBCR_ADDR, m) +#define HWIO_GCC_ECC_CBCR_OUT(v) \ + out_dword(HWIO_GCC_ECC_CBCR_ADDR,v) +#define HWIO_GCC_ECC_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ECC_CBCR_ADDR,m,v,HWIO_GCC_ECC_CBCR_IN) +#define HWIO_GCC_ECC_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_ECC_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_ECC_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_ECC_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_ECC_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_ECC_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_ECC_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_ECC_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_ECC_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_ECC_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_ECC_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_ECC_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_ECC_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_ECC_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_ECC_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_ECC_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_ECC_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_ECC_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_ECC_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_ECC_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_ECC_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_ECC_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_ECC_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_ECC_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_ECC_CORE_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00040008) +#define HWIO_GCC_ECC_CORE_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00040008) +#define HWIO_GCC_ECC_CORE_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00040008) +#define HWIO_GCC_ECC_CORE_CBCR_RMSK 0x81d07ff5 +#define HWIO_GCC_ECC_CORE_CBCR_ATTR 0x3 +#define HWIO_GCC_ECC_CORE_CBCR_IN \ + in_dword_masked(HWIO_GCC_ECC_CORE_CBCR_ADDR, HWIO_GCC_ECC_CORE_CBCR_RMSK) +#define HWIO_GCC_ECC_CORE_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_ECC_CORE_CBCR_ADDR, m) +#define HWIO_GCC_ECC_CORE_CBCR_OUT(v) \ + out_dword(HWIO_GCC_ECC_CORE_CBCR_ADDR,v) +#define HWIO_GCC_ECC_CORE_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ECC_CORE_CBCR_ADDR,m,v,HWIO_GCC_ECC_CORE_CBCR_IN) +#define HWIO_GCC_ECC_CORE_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_ECC_CORE_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_ECC_CORE_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_ECC_CORE_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_ECC_CORE_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_ECC_CORE_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_ECC_CORE_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_ECC_CORE_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_ECC_CORE_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_ECC_CORE_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_ECC_CORE_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_ECC_CORE_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_ECC_CORE_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_ECC_CORE_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_ECC_CORE_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_ECC_CORE_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_ECC_CORE_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_ECC_CORE_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_ECC_CORE_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_ECC_CORE_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_ECC_CORE_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_ECC_CORE_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_ECC_CORE_CBCR_WAKEUP_BMSK 0xf00 +#define HWIO_GCC_ECC_CORE_CBCR_WAKEUP_SHFT 0x8 +#define HWIO_GCC_ECC_CORE_CBCR_WAKEUP_CLOCK0_FVAL 0x0 +#define HWIO_GCC_ECC_CORE_CBCR_WAKEUP_CLOCK1_FVAL 0x1 +#define HWIO_GCC_ECC_CORE_CBCR_WAKEUP_CLOCK2_FVAL 0x2 +#define HWIO_GCC_ECC_CORE_CBCR_WAKEUP_CLOCK3_FVAL 0x3 +#define HWIO_GCC_ECC_CORE_CBCR_WAKEUP_CLOCK4_FVAL 0x4 +#define HWIO_GCC_ECC_CORE_CBCR_WAKEUP_CLOCK5_FVAL 0x5 +#define HWIO_GCC_ECC_CORE_CBCR_WAKEUP_CLOCK6_FVAL 0x6 +#define HWIO_GCC_ECC_CORE_CBCR_WAKEUP_CLOCK7_FVAL 0x7 +#define HWIO_GCC_ECC_CORE_CBCR_WAKEUP_CLOCK8_FVAL 0x8 +#define HWIO_GCC_ECC_CORE_CBCR_WAKEUP_CLOCK9_FVAL 0x9 +#define HWIO_GCC_ECC_CORE_CBCR_WAKEUP_CLOCK10_FVAL 0xa +#define HWIO_GCC_ECC_CORE_CBCR_WAKEUP_CLOCK11_FVAL 0xb +#define HWIO_GCC_ECC_CORE_CBCR_WAKEUP_CLOCK12_FVAL 0xc +#define HWIO_GCC_ECC_CORE_CBCR_WAKEUP_CLOCK13_FVAL 0xd +#define HWIO_GCC_ECC_CORE_CBCR_WAKEUP_CLOCK14_FVAL 0xe +#define HWIO_GCC_ECC_CORE_CBCR_WAKEUP_CLOCK15_FVAL 0xf +#define HWIO_GCC_ECC_CORE_CBCR_SLEEP_BMSK 0xf0 +#define HWIO_GCC_ECC_CORE_CBCR_SLEEP_SHFT 0x4 +#define HWIO_GCC_ECC_CORE_CBCR_SLEEP_CLOCK0_FVAL 0x0 +#define HWIO_GCC_ECC_CORE_CBCR_SLEEP_CLOCK1_FVAL 0x1 +#define HWIO_GCC_ECC_CORE_CBCR_SLEEP_CLOCK2_FVAL 0x2 +#define HWIO_GCC_ECC_CORE_CBCR_SLEEP_CLOCK3_FVAL 0x3 +#define HWIO_GCC_ECC_CORE_CBCR_SLEEP_CLOCK4_FVAL 0x4 +#define HWIO_GCC_ECC_CORE_CBCR_SLEEP_CLOCK5_FVAL 0x5 +#define HWIO_GCC_ECC_CORE_CBCR_SLEEP_CLOCK6_FVAL 0x6 +#define HWIO_GCC_ECC_CORE_CBCR_SLEEP_CLOCK7_FVAL 0x7 +#define HWIO_GCC_ECC_CORE_CBCR_SLEEP_CLOCK8_FVAL 0x8 +#define HWIO_GCC_ECC_CORE_CBCR_SLEEP_CLOCK9_FVAL 0x9 +#define HWIO_GCC_ECC_CORE_CBCR_SLEEP_CLOCK10_FVAL 0xa +#define HWIO_GCC_ECC_CORE_CBCR_SLEEP_CLOCK11_FVAL 0xb +#define HWIO_GCC_ECC_CORE_CBCR_SLEEP_CLOCK12_FVAL 0xc +#define HWIO_GCC_ECC_CORE_CBCR_SLEEP_CLOCK13_FVAL 0xd +#define HWIO_GCC_ECC_CORE_CBCR_SLEEP_CLOCK14_FVAL 0xe +#define HWIO_GCC_ECC_CORE_CBCR_SLEEP_CLOCK15_FVAL 0xf +#define HWIO_GCC_ECC_CORE_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_ECC_CORE_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_ECC_CORE_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_ECC_CORE_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_ECC_CORE_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_ECC_CORE_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_ECC_CORE_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_ECC_CORE_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_ECC_CORE_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004000c) +#define HWIO_GCC_ECC_CORE_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004000c) +#define HWIO_GCC_ECC_CORE_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004000c) +#define HWIO_GCC_ECC_CORE_SREGR_RMSK 0xfffffffe +#define HWIO_GCC_ECC_CORE_SREGR_ATTR 0x3 +#define HWIO_GCC_ECC_CORE_SREGR_IN \ + in_dword_masked(HWIO_GCC_ECC_CORE_SREGR_ADDR, HWIO_GCC_ECC_CORE_SREGR_RMSK) +#define HWIO_GCC_ECC_CORE_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_ECC_CORE_SREGR_ADDR, m) +#define HWIO_GCC_ECC_CORE_SREGR_OUT(v) \ + out_dword(HWIO_GCC_ECC_CORE_SREGR_ADDR,v) +#define HWIO_GCC_ECC_CORE_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ECC_CORE_SREGR_ADDR,m,v,HWIO_GCC_ECC_CORE_SREGR_IN) +#define HWIO_GCC_ECC_CORE_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xff000000 +#define HWIO_GCC_ECC_CORE_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_ECC_CORE_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xff0000 +#define HWIO_GCC_ECC_CORE_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_ECC_CORE_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_ECC_CORE_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_ECC_CORE_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_ECC_CORE_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_ECC_CORE_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_ECC_CORE_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_ECC_CORE_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_ECC_CORE_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_ECC_CORE_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_ECC_CORE_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_ECC_CORE_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_ECC_CORE_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_ECC_CORE_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_ECC_CORE_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_ECC_CORE_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_ECC_CORE_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_ECC_CORE_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_ECC_CORE_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_ECC_CORE_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_ECC_CORE_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_ECC_CORE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_ECC_CORE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_ECC_CORE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_ECC_CORE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_ECC_CORE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_ECC_CORE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_ECC_CORE_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_ECC_CORE_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_ECC_CORE_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_ECC_CORE_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_ECC_CORE_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_ECC_CORE_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_ECC_CORE_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_ECC_CORE_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_ECC_CORE_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_ECC_CORE_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_ECC_CORE_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_ECC_CORE_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_ECC_CORE_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_ECC_CORE_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_ECC_CORE_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_ECC_CORE_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_ECC_CORE_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_ECC_CORE_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_ECC_CORE_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_ECC_CORE_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_ECC_CORE_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_ECC_CORE_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_ECC_CORE_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_ECC_CORE_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_ECC_CORE_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_ECC_CORE_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_ECC_CORE_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_ECC_CORE_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_PKA_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00040024) +#define HWIO_GCC_RPMH_PKA_CMD_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00040024) +#define HWIO_GCC_RPMH_PKA_CMD_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00040024) +#define HWIO_GCC_RPMH_PKA_CMD_DFSR_RMSK 0xffff +#define HWIO_GCC_RPMH_PKA_CMD_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_PKA_CMD_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_PKA_CMD_DFSR_ADDR, HWIO_GCC_RPMH_PKA_CMD_DFSR_RMSK) +#define HWIO_GCC_RPMH_PKA_CMD_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PKA_CMD_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_PKA_CMD_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PKA_CMD_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_PKA_CMD_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PKA_CMD_DFSR_ADDR,m,v,HWIO_GCC_RPMH_PKA_CMD_DFSR_IN) +#define HWIO_GCC_RPMH_PKA_CMD_DFSR_RCG_SW_CTRL_BMSK 0x8000 +#define HWIO_GCC_RPMH_PKA_CMD_DFSR_RCG_SW_CTRL_SHFT 0xf +#define HWIO_GCC_RPMH_PKA_CMD_DFSR_SW_PERF_STATE_BMSK 0x7800 +#define HWIO_GCC_RPMH_PKA_CMD_DFSR_SW_PERF_STATE_SHFT 0xb +#define HWIO_GCC_RPMH_PKA_CMD_DFSR_SW_OVERRIDE_BMSK 0x400 +#define HWIO_GCC_RPMH_PKA_CMD_DFSR_SW_OVERRIDE_SHFT 0xa +#define HWIO_GCC_RPMH_PKA_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK 0x200 +#define HWIO_GCC_RPMH_PKA_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT 0x9 +#define HWIO_GCC_RPMH_PKA_CMD_DFSR_DFS_FSM_STATE_BMSK 0x1c0 +#define HWIO_GCC_RPMH_PKA_CMD_DFSR_DFS_FSM_STATE_SHFT 0x6 +#define HWIO_GCC_RPMH_PKA_CMD_DFSR_HW_CLK_CONTROL_BMSK 0x20 +#define HWIO_GCC_RPMH_PKA_CMD_DFSR_HW_CLK_CONTROL_SHFT 0x5 +#define HWIO_GCC_RPMH_PKA_CMD_DFSR_CURR_PERF_STATE_BMSK 0x1e +#define HWIO_GCC_RPMH_PKA_CMD_DFSR_CURR_PERF_STATE_SHFT 0x1 +#define HWIO_GCC_RPMH_PKA_CMD_DFSR_DFS_EN_BMSK 0x1 +#define HWIO_GCC_RPMH_PKA_CMD_DFSR_DFS_EN_SHFT 0x0 +#define HWIO_GCC_RPMH_PKA_CMD_DFSR_DFS_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_CMD_DFSR_DFS_EN_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_PKA_ECC_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004002c) +#define HWIO_GCC_RPMH_PKA_ECC_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004002c) +#define HWIO_GCC_RPMH_PKA_ECC_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004002c) +#define HWIO_GCC_RPMH_PKA_ECC_PERF0_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_PKA_ECC_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_PKA_ECC_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_PKA_ECC_PERF0_DFSR_ADDR, HWIO_GCC_RPMH_PKA_ECC_PERF0_DFSR_RMSK) +#define HWIO_GCC_RPMH_PKA_ECC_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PKA_ECC_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_PKA_ECC_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PKA_ECC_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_PKA_ECC_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PKA_ECC_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_PKA_ECC_PERF0_DFSR_IN) +#define HWIO_GCC_RPMH_PKA_ECC_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_PKA_ECC_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_PKA_ECC_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_ECC_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_ECC_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_PKA_ECC_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_PKA_ECC_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_PKA_ECC_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_PKA_ECC_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_PKA_ECC_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_PKA_ECC_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_PKA_ECC_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_PKA_ECC_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_ECC_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_ECC_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_PKA_ECC_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_PKA_ECC_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_PKA_ECC_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_PKA_ECC_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_PKA_ECC_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_PKA_ECC_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_PKA_ECC_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_PKA_ECC_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_PKA_ECC_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_PKA_ECC_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_PKA_ECC_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_PKA_ECC_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_PKA_ECC_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_PKA_ECC_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_PKA_ECC_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_PKA_ECC_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_PKA_ECC_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_PKA_ECC_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_PKA_ECC_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_PKA_ECC_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_PKA_ECC_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_PKA_ECC_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_PKA_ECC_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_PKA_ECC_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_PKA_ECC_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_PKA_ECC_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_PKA_ECC_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_PKA_ECC_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_PKA_ECC_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_PKA_ECC_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00040030) +#define HWIO_GCC_RPMH_PKA_ECC_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00040030) +#define HWIO_GCC_RPMH_PKA_ECC_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00040030) +#define HWIO_GCC_RPMH_PKA_ECC_PERF1_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_PKA_ECC_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_PKA_ECC_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_PKA_ECC_PERF1_DFSR_ADDR, HWIO_GCC_RPMH_PKA_ECC_PERF1_DFSR_RMSK) +#define HWIO_GCC_RPMH_PKA_ECC_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PKA_ECC_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_PKA_ECC_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PKA_ECC_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_PKA_ECC_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PKA_ECC_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_PKA_ECC_PERF1_DFSR_IN) +#define HWIO_GCC_RPMH_PKA_ECC_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_PKA_ECC_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_PKA_ECC_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_ECC_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_ECC_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_PKA_ECC_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_PKA_ECC_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_PKA_ECC_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_PKA_ECC_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_PKA_ECC_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_PKA_ECC_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_PKA_ECC_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_PKA_ECC_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_ECC_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_ECC_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_PKA_ECC_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_PKA_ECC_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_PKA_ECC_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_PKA_ECC_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_PKA_ECC_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_PKA_ECC_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_PKA_ECC_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_PKA_ECC_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_PKA_ECC_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_PKA_ECC_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_PKA_ECC_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_PKA_ECC_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_PKA_ECC_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_PKA_ECC_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_PKA_ECC_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_PKA_ECC_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_PKA_ECC_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_PKA_ECC_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_PKA_ECC_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_PKA_ECC_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_PKA_ECC_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_PKA_ECC_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_PKA_ECC_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_PKA_ECC_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_PKA_ECC_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_PKA_ECC_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_PKA_ECC_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_PKA_ECC_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_PKA_ECC_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_PKA_ECC_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00040034) +#define HWIO_GCC_RPMH_PKA_ECC_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00040034) +#define HWIO_GCC_RPMH_PKA_ECC_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00040034) +#define HWIO_GCC_RPMH_PKA_ECC_PERF2_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_PKA_ECC_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_PKA_ECC_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_PKA_ECC_PERF2_DFSR_ADDR, HWIO_GCC_RPMH_PKA_ECC_PERF2_DFSR_RMSK) +#define HWIO_GCC_RPMH_PKA_ECC_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PKA_ECC_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_PKA_ECC_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PKA_ECC_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_PKA_ECC_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PKA_ECC_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_PKA_ECC_PERF2_DFSR_IN) +#define HWIO_GCC_RPMH_PKA_ECC_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_PKA_ECC_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_PKA_ECC_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_ECC_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_ECC_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_PKA_ECC_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_PKA_ECC_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_PKA_ECC_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_PKA_ECC_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_PKA_ECC_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_PKA_ECC_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_PKA_ECC_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_PKA_ECC_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_ECC_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_ECC_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_PKA_ECC_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_PKA_ECC_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_PKA_ECC_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_PKA_ECC_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_PKA_ECC_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_PKA_ECC_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_PKA_ECC_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_PKA_ECC_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_PKA_ECC_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_PKA_ECC_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_PKA_ECC_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_PKA_ECC_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_PKA_ECC_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_PKA_ECC_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_PKA_ECC_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_PKA_ECC_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_PKA_ECC_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_PKA_ECC_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_PKA_ECC_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_PKA_ECC_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_PKA_ECC_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_PKA_ECC_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_PKA_ECC_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_PKA_ECC_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_PKA_ECC_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_PKA_ECC_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_PKA_ECC_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_PKA_ECC_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_PKA_ECC_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_PKA_ECC_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00040038) +#define HWIO_GCC_RPMH_PKA_ECC_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00040038) +#define HWIO_GCC_RPMH_PKA_ECC_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00040038) +#define HWIO_GCC_RPMH_PKA_ECC_PERF3_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_PKA_ECC_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_PKA_ECC_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_PKA_ECC_PERF3_DFSR_ADDR, HWIO_GCC_RPMH_PKA_ECC_PERF3_DFSR_RMSK) +#define HWIO_GCC_RPMH_PKA_ECC_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PKA_ECC_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_PKA_ECC_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PKA_ECC_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_PKA_ECC_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PKA_ECC_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_PKA_ECC_PERF3_DFSR_IN) +#define HWIO_GCC_RPMH_PKA_ECC_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_PKA_ECC_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_PKA_ECC_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_ECC_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_ECC_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_PKA_ECC_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_PKA_ECC_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_PKA_ECC_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_PKA_ECC_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_PKA_ECC_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_PKA_ECC_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_PKA_ECC_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_PKA_ECC_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_ECC_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_ECC_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_PKA_ECC_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_PKA_ECC_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_PKA_ECC_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_PKA_ECC_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_PKA_ECC_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_PKA_ECC_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_PKA_ECC_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_PKA_ECC_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_PKA_ECC_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_PKA_ECC_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_PKA_ECC_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_PKA_ECC_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_PKA_ECC_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_PKA_ECC_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_PKA_ECC_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_PKA_ECC_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_PKA_ECC_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_PKA_ECC_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_PKA_ECC_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_PKA_ECC_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_PKA_ECC_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_PKA_ECC_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_PKA_ECC_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_PKA_ECC_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_PKA_ECC_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_PKA_ECC_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_PKA_ECC_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_PKA_ECC_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_PKA_ECC_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_PKA_ECC_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004003c) +#define HWIO_GCC_RPMH_PKA_ECC_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004003c) +#define HWIO_GCC_RPMH_PKA_ECC_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004003c) +#define HWIO_GCC_RPMH_PKA_ECC_PERF4_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_PKA_ECC_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_PKA_ECC_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_PKA_ECC_PERF4_DFSR_ADDR, HWIO_GCC_RPMH_PKA_ECC_PERF4_DFSR_RMSK) +#define HWIO_GCC_RPMH_PKA_ECC_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PKA_ECC_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_PKA_ECC_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PKA_ECC_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_PKA_ECC_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PKA_ECC_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_PKA_ECC_PERF4_DFSR_IN) +#define HWIO_GCC_RPMH_PKA_ECC_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_PKA_ECC_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_PKA_ECC_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_ECC_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_ECC_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_PKA_ECC_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_PKA_ECC_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_PKA_ECC_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_PKA_ECC_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_PKA_ECC_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_PKA_ECC_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_PKA_ECC_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_PKA_ECC_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_ECC_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_ECC_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_PKA_ECC_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_PKA_ECC_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_PKA_ECC_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_PKA_ECC_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_PKA_ECC_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_PKA_ECC_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_PKA_ECC_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_PKA_ECC_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_PKA_ECC_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_PKA_ECC_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_PKA_ECC_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_PKA_ECC_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_PKA_ECC_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_PKA_ECC_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_PKA_ECC_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_PKA_ECC_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_PKA_ECC_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_PKA_ECC_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_PKA_ECC_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_PKA_ECC_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_PKA_ECC_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_PKA_ECC_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_PKA_ECC_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_PKA_ECC_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_PKA_ECC_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_PKA_ECC_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_PKA_ECC_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_PKA_ECC_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_PKA_ECC_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_PKA_ECC_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00040040) +#define HWIO_GCC_RPMH_PKA_ECC_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00040040) +#define HWIO_GCC_RPMH_PKA_ECC_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00040040) +#define HWIO_GCC_RPMH_PKA_ECC_PERF5_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_PKA_ECC_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_PKA_ECC_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_PKA_ECC_PERF5_DFSR_ADDR, HWIO_GCC_RPMH_PKA_ECC_PERF5_DFSR_RMSK) +#define HWIO_GCC_RPMH_PKA_ECC_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PKA_ECC_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_PKA_ECC_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PKA_ECC_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_PKA_ECC_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PKA_ECC_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_PKA_ECC_PERF5_DFSR_IN) +#define HWIO_GCC_RPMH_PKA_ECC_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_PKA_ECC_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_PKA_ECC_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_ECC_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_ECC_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_PKA_ECC_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_PKA_ECC_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_PKA_ECC_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_PKA_ECC_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_PKA_ECC_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_PKA_ECC_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_PKA_ECC_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_PKA_ECC_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_ECC_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_ECC_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_PKA_ECC_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_PKA_ECC_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_PKA_ECC_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_PKA_ECC_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_PKA_ECC_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_PKA_ECC_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_PKA_ECC_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_PKA_ECC_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_PKA_ECC_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_PKA_ECC_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_PKA_ECC_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_PKA_ECC_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_PKA_ECC_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_PKA_ECC_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_PKA_ECC_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_PKA_ECC_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_PKA_ECC_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_PKA_ECC_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_PKA_ECC_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_PKA_ECC_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_PKA_ECC_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_PKA_ECC_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_PKA_ECC_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_PKA_ECC_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_PKA_ECC_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_PKA_ECC_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_PKA_ECC_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_PKA_ECC_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_PKA_ECC_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_PKA_ECC_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00040044) +#define HWIO_GCC_RPMH_PKA_ECC_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00040044) +#define HWIO_GCC_RPMH_PKA_ECC_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00040044) +#define HWIO_GCC_RPMH_PKA_ECC_PERF6_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_PKA_ECC_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_PKA_ECC_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_PKA_ECC_PERF6_DFSR_ADDR, HWIO_GCC_RPMH_PKA_ECC_PERF6_DFSR_RMSK) +#define HWIO_GCC_RPMH_PKA_ECC_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PKA_ECC_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_PKA_ECC_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PKA_ECC_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_PKA_ECC_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PKA_ECC_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_PKA_ECC_PERF6_DFSR_IN) +#define HWIO_GCC_RPMH_PKA_ECC_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_PKA_ECC_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_PKA_ECC_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_ECC_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_ECC_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_PKA_ECC_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_PKA_ECC_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_PKA_ECC_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_PKA_ECC_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_PKA_ECC_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_PKA_ECC_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_PKA_ECC_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_PKA_ECC_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_ECC_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_ECC_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_PKA_ECC_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_PKA_ECC_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_PKA_ECC_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_PKA_ECC_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_PKA_ECC_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_PKA_ECC_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_PKA_ECC_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_PKA_ECC_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_PKA_ECC_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_PKA_ECC_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_PKA_ECC_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_PKA_ECC_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_PKA_ECC_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_PKA_ECC_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_PKA_ECC_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_PKA_ECC_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_PKA_ECC_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_PKA_ECC_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_PKA_ECC_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_PKA_ECC_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_PKA_ECC_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_PKA_ECC_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_PKA_ECC_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_PKA_ECC_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_PKA_ECC_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_PKA_ECC_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_PKA_ECC_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_PKA_ECC_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_PKA_ECC_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_PKA_ECC_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00040048) +#define HWIO_GCC_RPMH_PKA_ECC_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00040048) +#define HWIO_GCC_RPMH_PKA_ECC_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00040048) +#define HWIO_GCC_RPMH_PKA_ECC_PERF7_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_PKA_ECC_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_PKA_ECC_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_PKA_ECC_PERF7_DFSR_ADDR, HWIO_GCC_RPMH_PKA_ECC_PERF7_DFSR_RMSK) +#define HWIO_GCC_RPMH_PKA_ECC_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PKA_ECC_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_PKA_ECC_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PKA_ECC_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_PKA_ECC_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PKA_ECC_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_PKA_ECC_PERF7_DFSR_IN) +#define HWIO_GCC_RPMH_PKA_ECC_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_PKA_ECC_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_PKA_ECC_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_ECC_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_ECC_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_PKA_ECC_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_PKA_ECC_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_PKA_ECC_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_PKA_ECC_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_PKA_ECC_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_PKA_ECC_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_PKA_ECC_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_PKA_ECC_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_ECC_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_ECC_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_PKA_ECC_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_PKA_ECC_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_PKA_ECC_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_PKA_ECC_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_PKA_ECC_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_PKA_ECC_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_PKA_ECC_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_PKA_ECC_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_PKA_ECC_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_PKA_ECC_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_PKA_ECC_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_PKA_ECC_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_PKA_ECC_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_PKA_ECC_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_PKA_ECC_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_PKA_ECC_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_PKA_ECC_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_PKA_ECC_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_PKA_ECC_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_PKA_ECC_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_PKA_ECC_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_PKA_ECC_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_PKA_ECC_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_PKA_ECC_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_PKA_ECC_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_PKA_ECC_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_PKA_ECC_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_PKA_ECC_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_PKA_ECC_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_PKA_ECC_PERF8_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004004c) +#define HWIO_GCC_RPMH_PKA_ECC_PERF8_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004004c) +#define HWIO_GCC_RPMH_PKA_ECC_PERF8_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004004c) +#define HWIO_GCC_RPMH_PKA_ECC_PERF8_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_PKA_ECC_PERF8_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_PKA_ECC_PERF8_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_PKA_ECC_PERF8_DFSR_ADDR, HWIO_GCC_RPMH_PKA_ECC_PERF8_DFSR_RMSK) +#define HWIO_GCC_RPMH_PKA_ECC_PERF8_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PKA_ECC_PERF8_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_PKA_ECC_PERF8_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PKA_ECC_PERF8_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_PKA_ECC_PERF8_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PKA_ECC_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_PKA_ECC_PERF8_DFSR_IN) +#define HWIO_GCC_RPMH_PKA_ECC_PERF8_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_PKA_ECC_PERF8_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_PKA_ECC_PERF8_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_ECC_PERF8_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_ECC_PERF8_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_PKA_ECC_PERF8_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_PKA_ECC_PERF8_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_PKA_ECC_PERF8_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_PKA_ECC_PERF8_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_PKA_ECC_PERF8_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_PKA_ECC_PERF8_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_PKA_ECC_PERF8_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_PKA_ECC_PERF8_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_ECC_PERF8_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_ECC_PERF8_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_PKA_ECC_PERF8_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_PKA_ECC_PERF8_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_PKA_ECC_PERF8_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_PKA_ECC_PERF8_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_PKA_ECC_PERF8_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_PKA_ECC_PERF8_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_PKA_ECC_PERF8_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_PKA_ECC_PERF8_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_PKA_ECC_PERF8_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_PKA_ECC_PERF8_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_PKA_ECC_PERF8_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_PKA_ECC_PERF8_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_PKA_ECC_PERF8_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_PKA_ECC_PERF8_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_PKA_ECC_PERF8_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_PKA_ECC_PERF8_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_PKA_ECC_PERF8_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_PKA_ECC_PERF8_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_PKA_ECC_PERF8_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_PKA_ECC_PERF8_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_PKA_ECC_PERF8_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_PKA_ECC_PERF8_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_PKA_ECC_PERF8_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_PKA_ECC_PERF8_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_PKA_ECC_PERF8_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_PKA_ECC_PERF8_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_PKA_ECC_PERF8_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_PKA_ECC_PERF8_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_PKA_ECC_PERF8_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_PKA_ECC_PERF9_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00040050) +#define HWIO_GCC_RPMH_PKA_ECC_PERF9_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00040050) +#define HWIO_GCC_RPMH_PKA_ECC_PERF9_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00040050) +#define HWIO_GCC_RPMH_PKA_ECC_PERF9_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_PKA_ECC_PERF9_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_PKA_ECC_PERF9_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_PKA_ECC_PERF9_DFSR_ADDR, HWIO_GCC_RPMH_PKA_ECC_PERF9_DFSR_RMSK) +#define HWIO_GCC_RPMH_PKA_ECC_PERF9_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PKA_ECC_PERF9_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_PKA_ECC_PERF9_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PKA_ECC_PERF9_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_PKA_ECC_PERF9_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PKA_ECC_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_PKA_ECC_PERF9_DFSR_IN) +#define HWIO_GCC_RPMH_PKA_ECC_PERF9_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_PKA_ECC_PERF9_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_PKA_ECC_PERF9_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_ECC_PERF9_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_ECC_PERF9_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_PKA_ECC_PERF9_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_PKA_ECC_PERF9_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_PKA_ECC_PERF9_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_PKA_ECC_PERF9_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_PKA_ECC_PERF9_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_PKA_ECC_PERF9_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_PKA_ECC_PERF9_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_PKA_ECC_PERF9_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_ECC_PERF9_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_ECC_PERF9_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_PKA_ECC_PERF9_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_PKA_ECC_PERF9_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_PKA_ECC_PERF9_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_PKA_ECC_PERF9_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_PKA_ECC_PERF9_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_PKA_ECC_PERF9_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_PKA_ECC_PERF9_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_PKA_ECC_PERF9_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_PKA_ECC_PERF9_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_PKA_ECC_PERF9_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_PKA_ECC_PERF9_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_PKA_ECC_PERF9_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_PKA_ECC_PERF9_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_PKA_ECC_PERF9_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_PKA_ECC_PERF9_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_PKA_ECC_PERF9_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_PKA_ECC_PERF9_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_PKA_ECC_PERF9_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_PKA_ECC_PERF9_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_PKA_ECC_PERF9_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_PKA_ECC_PERF9_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_PKA_ECC_PERF9_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_PKA_ECC_PERF9_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_PKA_ECC_PERF9_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_PKA_ECC_PERF9_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_PKA_ECC_PERF9_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_PKA_ECC_PERF9_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_PKA_ECC_PERF9_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_PKA_ECC_PERF9_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_PKA_ECC_PERF10_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00040054) +#define HWIO_GCC_RPMH_PKA_ECC_PERF10_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00040054) +#define HWIO_GCC_RPMH_PKA_ECC_PERF10_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00040054) +#define HWIO_GCC_RPMH_PKA_ECC_PERF10_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_PKA_ECC_PERF10_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_PKA_ECC_PERF10_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_PKA_ECC_PERF10_DFSR_ADDR, HWIO_GCC_RPMH_PKA_ECC_PERF10_DFSR_RMSK) +#define HWIO_GCC_RPMH_PKA_ECC_PERF10_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PKA_ECC_PERF10_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_PKA_ECC_PERF10_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PKA_ECC_PERF10_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_PKA_ECC_PERF10_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PKA_ECC_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_PKA_ECC_PERF10_DFSR_IN) +#define HWIO_GCC_RPMH_PKA_ECC_PERF10_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_PKA_ECC_PERF10_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_PKA_ECC_PERF10_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_ECC_PERF10_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_ECC_PERF10_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_PKA_ECC_PERF10_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_PKA_ECC_PERF10_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_PKA_ECC_PERF10_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_PKA_ECC_PERF10_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_PKA_ECC_PERF10_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_PKA_ECC_PERF10_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_PKA_ECC_PERF10_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_PKA_ECC_PERF10_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_ECC_PERF10_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_ECC_PERF10_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_PKA_ECC_PERF10_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_PKA_ECC_PERF10_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_PKA_ECC_PERF10_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_PKA_ECC_PERF10_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_PKA_ECC_PERF10_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_PKA_ECC_PERF10_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_PKA_ECC_PERF10_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_PKA_ECC_PERF10_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_PKA_ECC_PERF10_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_PKA_ECC_PERF10_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_PKA_ECC_PERF10_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_PKA_ECC_PERF10_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_PKA_ECC_PERF10_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_PKA_ECC_PERF10_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_PKA_ECC_PERF10_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_PKA_ECC_PERF10_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_PKA_ECC_PERF10_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_PKA_ECC_PERF10_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_PKA_ECC_PERF10_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_PKA_ECC_PERF10_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_PKA_ECC_PERF10_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_PKA_ECC_PERF10_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_PKA_ECC_PERF10_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_PKA_ECC_PERF10_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_PKA_ECC_PERF10_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_PKA_ECC_PERF10_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_PKA_ECC_PERF10_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_PKA_ECC_PERF10_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_PKA_ECC_PERF10_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_PKA_ECC_PERF11_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00040058) +#define HWIO_GCC_RPMH_PKA_ECC_PERF11_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00040058) +#define HWIO_GCC_RPMH_PKA_ECC_PERF11_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00040058) +#define HWIO_GCC_RPMH_PKA_ECC_PERF11_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_PKA_ECC_PERF11_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_PKA_ECC_PERF11_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_PKA_ECC_PERF11_DFSR_ADDR, HWIO_GCC_RPMH_PKA_ECC_PERF11_DFSR_RMSK) +#define HWIO_GCC_RPMH_PKA_ECC_PERF11_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PKA_ECC_PERF11_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_PKA_ECC_PERF11_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PKA_ECC_PERF11_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_PKA_ECC_PERF11_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PKA_ECC_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_PKA_ECC_PERF11_DFSR_IN) +#define HWIO_GCC_RPMH_PKA_ECC_PERF11_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_PKA_ECC_PERF11_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_PKA_ECC_PERF11_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_ECC_PERF11_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_ECC_PERF11_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_PKA_ECC_PERF11_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_PKA_ECC_PERF11_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_PKA_ECC_PERF11_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_PKA_ECC_PERF11_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_PKA_ECC_PERF11_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_PKA_ECC_PERF11_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_PKA_ECC_PERF11_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_PKA_ECC_PERF11_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_ECC_PERF11_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_ECC_PERF11_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_PKA_ECC_PERF11_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_PKA_ECC_PERF11_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_PKA_ECC_PERF11_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_PKA_ECC_PERF11_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_PKA_ECC_PERF11_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_PKA_ECC_PERF11_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_PKA_ECC_PERF11_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_PKA_ECC_PERF11_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_PKA_ECC_PERF11_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_PKA_ECC_PERF11_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_PKA_ECC_PERF11_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_PKA_ECC_PERF11_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_PKA_ECC_PERF11_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_PKA_ECC_PERF11_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_PKA_ECC_PERF11_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_PKA_ECC_PERF11_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_PKA_ECC_PERF11_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_PKA_ECC_PERF11_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_PKA_ECC_PERF11_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_PKA_ECC_PERF11_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_PKA_ECC_PERF11_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_PKA_ECC_PERF11_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_PKA_ECC_PERF11_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_PKA_ECC_PERF11_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_PKA_ECC_PERF11_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_PKA_ECC_PERF11_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_PKA_ECC_PERF11_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_PKA_ECC_PERF11_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_PKA_ECC_PERF11_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_PKA_ECC_PERF12_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004005c) +#define HWIO_GCC_RPMH_PKA_ECC_PERF12_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004005c) +#define HWIO_GCC_RPMH_PKA_ECC_PERF12_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004005c) +#define HWIO_GCC_RPMH_PKA_ECC_PERF12_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_PKA_ECC_PERF12_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_PKA_ECC_PERF12_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_PKA_ECC_PERF12_DFSR_ADDR, HWIO_GCC_RPMH_PKA_ECC_PERF12_DFSR_RMSK) +#define HWIO_GCC_RPMH_PKA_ECC_PERF12_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PKA_ECC_PERF12_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_PKA_ECC_PERF12_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PKA_ECC_PERF12_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_PKA_ECC_PERF12_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PKA_ECC_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_PKA_ECC_PERF12_DFSR_IN) +#define HWIO_GCC_RPMH_PKA_ECC_PERF12_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_PKA_ECC_PERF12_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_PKA_ECC_PERF12_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_ECC_PERF12_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_ECC_PERF12_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_PKA_ECC_PERF12_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_PKA_ECC_PERF12_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_PKA_ECC_PERF12_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_PKA_ECC_PERF12_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_PKA_ECC_PERF12_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_PKA_ECC_PERF12_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_PKA_ECC_PERF12_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_PKA_ECC_PERF12_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_ECC_PERF12_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_ECC_PERF12_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_PKA_ECC_PERF12_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_PKA_ECC_PERF12_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_PKA_ECC_PERF12_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_PKA_ECC_PERF12_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_PKA_ECC_PERF12_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_PKA_ECC_PERF12_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_PKA_ECC_PERF12_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_PKA_ECC_PERF12_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_PKA_ECC_PERF12_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_PKA_ECC_PERF12_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_PKA_ECC_PERF12_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_PKA_ECC_PERF12_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_PKA_ECC_PERF12_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_PKA_ECC_PERF12_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_PKA_ECC_PERF12_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_PKA_ECC_PERF12_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_PKA_ECC_PERF12_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_PKA_ECC_PERF12_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_PKA_ECC_PERF12_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_PKA_ECC_PERF12_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_PKA_ECC_PERF12_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_PKA_ECC_PERF12_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_PKA_ECC_PERF12_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_PKA_ECC_PERF12_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_PKA_ECC_PERF12_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_PKA_ECC_PERF12_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_PKA_ECC_PERF12_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_PKA_ECC_PERF12_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_PKA_ECC_PERF12_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_PKA_ECC_PERF13_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00040060) +#define HWIO_GCC_RPMH_PKA_ECC_PERF13_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00040060) +#define HWIO_GCC_RPMH_PKA_ECC_PERF13_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00040060) +#define HWIO_GCC_RPMH_PKA_ECC_PERF13_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_PKA_ECC_PERF13_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_PKA_ECC_PERF13_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_PKA_ECC_PERF13_DFSR_ADDR, HWIO_GCC_RPMH_PKA_ECC_PERF13_DFSR_RMSK) +#define HWIO_GCC_RPMH_PKA_ECC_PERF13_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PKA_ECC_PERF13_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_PKA_ECC_PERF13_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PKA_ECC_PERF13_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_PKA_ECC_PERF13_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PKA_ECC_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_PKA_ECC_PERF13_DFSR_IN) +#define HWIO_GCC_RPMH_PKA_ECC_PERF13_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_PKA_ECC_PERF13_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_PKA_ECC_PERF13_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_ECC_PERF13_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_ECC_PERF13_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_PKA_ECC_PERF13_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_PKA_ECC_PERF13_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_PKA_ECC_PERF13_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_PKA_ECC_PERF13_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_PKA_ECC_PERF13_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_PKA_ECC_PERF13_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_PKA_ECC_PERF13_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_PKA_ECC_PERF13_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_ECC_PERF13_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_ECC_PERF13_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_PKA_ECC_PERF13_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_PKA_ECC_PERF13_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_PKA_ECC_PERF13_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_PKA_ECC_PERF13_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_PKA_ECC_PERF13_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_PKA_ECC_PERF13_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_PKA_ECC_PERF13_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_PKA_ECC_PERF13_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_PKA_ECC_PERF13_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_PKA_ECC_PERF13_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_PKA_ECC_PERF13_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_PKA_ECC_PERF13_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_PKA_ECC_PERF13_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_PKA_ECC_PERF13_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_PKA_ECC_PERF13_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_PKA_ECC_PERF13_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_PKA_ECC_PERF13_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_PKA_ECC_PERF13_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_PKA_ECC_PERF13_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_PKA_ECC_PERF13_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_PKA_ECC_PERF13_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_PKA_ECC_PERF13_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_PKA_ECC_PERF13_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_PKA_ECC_PERF13_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_PKA_ECC_PERF13_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_PKA_ECC_PERF13_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_PKA_ECC_PERF13_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_PKA_ECC_PERF13_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_PKA_ECC_PERF13_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_PKA_ECC_PERF14_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00040064) +#define HWIO_GCC_RPMH_PKA_ECC_PERF14_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00040064) +#define HWIO_GCC_RPMH_PKA_ECC_PERF14_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00040064) +#define HWIO_GCC_RPMH_PKA_ECC_PERF14_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_PKA_ECC_PERF14_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_PKA_ECC_PERF14_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_PKA_ECC_PERF14_DFSR_ADDR, HWIO_GCC_RPMH_PKA_ECC_PERF14_DFSR_RMSK) +#define HWIO_GCC_RPMH_PKA_ECC_PERF14_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PKA_ECC_PERF14_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_PKA_ECC_PERF14_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PKA_ECC_PERF14_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_PKA_ECC_PERF14_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PKA_ECC_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_PKA_ECC_PERF14_DFSR_IN) +#define HWIO_GCC_RPMH_PKA_ECC_PERF14_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_PKA_ECC_PERF14_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_PKA_ECC_PERF14_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_ECC_PERF14_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_ECC_PERF14_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_PKA_ECC_PERF14_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_PKA_ECC_PERF14_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_PKA_ECC_PERF14_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_PKA_ECC_PERF14_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_PKA_ECC_PERF14_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_PKA_ECC_PERF14_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_PKA_ECC_PERF14_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_PKA_ECC_PERF14_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_ECC_PERF14_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_ECC_PERF14_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_PKA_ECC_PERF14_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_PKA_ECC_PERF14_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_PKA_ECC_PERF14_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_PKA_ECC_PERF14_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_PKA_ECC_PERF14_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_PKA_ECC_PERF14_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_PKA_ECC_PERF14_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_PKA_ECC_PERF14_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_PKA_ECC_PERF14_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_PKA_ECC_PERF14_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_PKA_ECC_PERF14_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_PKA_ECC_PERF14_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_PKA_ECC_PERF14_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_PKA_ECC_PERF14_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_PKA_ECC_PERF14_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_PKA_ECC_PERF14_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_PKA_ECC_PERF14_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_PKA_ECC_PERF14_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_PKA_ECC_PERF14_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_PKA_ECC_PERF14_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_PKA_ECC_PERF14_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_PKA_ECC_PERF14_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_PKA_ECC_PERF14_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_PKA_ECC_PERF14_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_PKA_ECC_PERF14_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_PKA_ECC_PERF14_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_PKA_ECC_PERF14_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_PKA_ECC_PERF14_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_PKA_ECC_PERF14_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_PKA_ECC_PERF15_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00040068) +#define HWIO_GCC_RPMH_PKA_ECC_PERF15_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00040068) +#define HWIO_GCC_RPMH_PKA_ECC_PERF15_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00040068) +#define HWIO_GCC_RPMH_PKA_ECC_PERF15_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_PKA_ECC_PERF15_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_PKA_ECC_PERF15_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_PKA_ECC_PERF15_DFSR_ADDR, HWIO_GCC_RPMH_PKA_ECC_PERF15_DFSR_RMSK) +#define HWIO_GCC_RPMH_PKA_ECC_PERF15_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PKA_ECC_PERF15_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_PKA_ECC_PERF15_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PKA_ECC_PERF15_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_PKA_ECC_PERF15_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PKA_ECC_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_PKA_ECC_PERF15_DFSR_IN) +#define HWIO_GCC_RPMH_PKA_ECC_PERF15_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_PKA_ECC_PERF15_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_PKA_ECC_PERF15_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_ECC_PERF15_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_ECC_PERF15_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_PKA_ECC_PERF15_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_PKA_ECC_PERF15_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_PKA_ECC_PERF15_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_PKA_ECC_PERF15_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_PKA_ECC_PERF15_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_PKA_ECC_PERF15_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_PKA_ECC_PERF15_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_PKA_ECC_PERF15_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_ECC_PERF15_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_ECC_PERF15_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_PKA_ECC_PERF15_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_PKA_ECC_PERF15_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_PKA_ECC_PERF15_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_PKA_ECC_PERF15_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_PKA_ECC_PERF15_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_PKA_ECC_PERF15_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_PKA_ECC_PERF15_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_PKA_ECC_PERF15_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_PKA_ECC_PERF15_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_PKA_ECC_PERF15_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_PKA_ECC_PERF15_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_PKA_ECC_PERF15_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_PKA_ECC_PERF15_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_PKA_ECC_PERF15_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_PKA_ECC_PERF15_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_PKA_ECC_PERF15_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_PKA_ECC_PERF15_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_PKA_ECC_PERF15_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_PKA_ECC_PERF15_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_PKA_ECC_PERF15_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_PKA_ECC_PERF15_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_PKA_ECC_PERF15_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_PKA_ECC_PERF15_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_PKA_ECC_PERF15_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_PKA_ECC_PERF15_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_PKA_ECC_PERF15_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_PKA_ECC_PERF15_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_PKA_ECC_PERF15_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_PKA_ECC_PERF15_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_ECC_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00040010) +#define HWIO_GCC_ECC_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00040010) +#define HWIO_GCC_ECC_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00040010) +#define HWIO_GCC_ECC_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_ECC_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_ECC_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_ECC_CMD_RCGR_ADDR, HWIO_GCC_ECC_CMD_RCGR_RMSK) +#define HWIO_GCC_ECC_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_ECC_CMD_RCGR_ADDR, m) +#define HWIO_GCC_ECC_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_ECC_CMD_RCGR_ADDR,v) +#define HWIO_GCC_ECC_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ECC_CMD_RCGR_ADDR,m,v,HWIO_GCC_ECC_CMD_RCGR_IN) +#define HWIO_GCC_ECC_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_ECC_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_ECC_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_ECC_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_ECC_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_ECC_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_ECC_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_ECC_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_ECC_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_ECC_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_ECC_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_ECC_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_ECC_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00040014) +#define HWIO_GCC_ECC_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00040014) +#define HWIO_GCC_ECC_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00040014) +#define HWIO_GCC_ECC_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_ECC_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_ECC_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_ECC_CFG_RCGR_ADDR, HWIO_GCC_ECC_CFG_RCGR_RMSK) +#define HWIO_GCC_ECC_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_ECC_CFG_RCGR_ADDR, m) +#define HWIO_GCC_ECC_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_ECC_CFG_RCGR_ADDR,v) +#define HWIO_GCC_ECC_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ECC_CFG_RCGR_ADDR,m,v,HWIO_GCC_ECC_CFG_RCGR_IN) +#define HWIO_GCC_ECC_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_ECC_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_ECC_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_ECC_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_ECC_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_ECC_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_ECC_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_ECC_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_ECC_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_ECC_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_ECC_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_ECC_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_ECC_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_ECC_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_ECC_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_ECC_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_ECC_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_ECC_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_ECC_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_ECC_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_ECC_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_ECC_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_ECC_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_ECC_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_ECC_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_ECC_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_ECC_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_ECC_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_ECC_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_ECC_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_ECC_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_ECC_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_ECC_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_ECC_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_ECC_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_ECC_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_ECC_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_ECC_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_ECC_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_ECC_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_ECC_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_ECC_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_ECC_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_ECC_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_ECC_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_ECC_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_ECC_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_ECC_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_ECC_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_ECC_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_ECC_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_ECC_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QM_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00042000) +#define HWIO_GCC_QM_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00042000) +#define HWIO_GCC_QM_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00042000) +#define HWIO_GCC_QM_BCR_RMSK 0x1 +#define HWIO_GCC_QM_BCR_ATTR 0x3 +#define HWIO_GCC_QM_BCR_IN \ + in_dword_masked(HWIO_GCC_QM_BCR_ADDR, HWIO_GCC_QM_BCR_RMSK) +#define HWIO_GCC_QM_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_QM_BCR_ADDR, m) +#define HWIO_GCC_QM_BCR_OUT(v) \ + out_dword(HWIO_GCC_QM_BCR_ADDR,v) +#define HWIO_GCC_QM_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QM_BCR_ADDR,m,v,HWIO_GCC_QM_BCR_IN) +#define HWIO_GCC_QM_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_QM_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_QM_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_QM_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QM_CFG_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00042004) +#define HWIO_GCC_QM_CFG_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00042004) +#define HWIO_GCC_QM_CFG_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00042004) +#define HWIO_GCC_QM_CFG_AHB_CBCR_RMSK 0x81d00005 +#define HWIO_GCC_QM_CFG_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_QM_CFG_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_QM_CFG_AHB_CBCR_ADDR, HWIO_GCC_QM_CFG_AHB_CBCR_RMSK) +#define HWIO_GCC_QM_CFG_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QM_CFG_AHB_CBCR_ADDR, m) +#define HWIO_GCC_QM_CFG_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QM_CFG_AHB_CBCR_ADDR,v) +#define HWIO_GCC_QM_CFG_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QM_CFG_AHB_CBCR_ADDR,m,v,HWIO_GCC_QM_CFG_AHB_CBCR_IN) +#define HWIO_GCC_QM_CFG_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QM_CFG_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QM_CFG_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QM_CFG_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QM_CFG_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QM_CFG_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QM_CFG_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QM_CFG_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QM_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_QM_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_QM_CFG_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QM_CFG_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QM_CFG_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QM_CFG_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_QM_CFG_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_QM_CFG_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_QM_CFG_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QM_CFG_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QM_CORE_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00042008) +#define HWIO_GCC_QM_CORE_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00042008) +#define HWIO_GCC_QM_CORE_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00042008) +#define HWIO_GCC_QM_CORE_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_QM_CORE_CBCR_ATTR 0x3 +#define HWIO_GCC_QM_CORE_CBCR_IN \ + in_dword_masked(HWIO_GCC_QM_CORE_CBCR_ADDR, HWIO_GCC_QM_CORE_CBCR_RMSK) +#define HWIO_GCC_QM_CORE_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QM_CORE_CBCR_ADDR, m) +#define HWIO_GCC_QM_CORE_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QM_CORE_CBCR_ADDR,v) +#define HWIO_GCC_QM_CORE_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QM_CORE_CBCR_ADDR,m,v,HWIO_GCC_QM_CORE_CBCR_IN) +#define HWIO_GCC_QM_CORE_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QM_CORE_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QM_CORE_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QM_CORE_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QM_CORE_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QM_CORE_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QM_CORE_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QM_CORE_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QM_CORE_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QM_CORE_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QM_CORE_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QM_CORE_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_QM_CORE_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_QM_CORE_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_QM_CORE_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QM_CORE_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QM_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004200c) +#define HWIO_GCC_QM_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004200c) +#define HWIO_GCC_QM_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004200c) +#define HWIO_GCC_QM_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_QM_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_QM_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_QM_CMD_RCGR_ADDR, HWIO_GCC_QM_CMD_RCGR_RMSK) +#define HWIO_GCC_QM_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QM_CMD_RCGR_ADDR, m) +#define HWIO_GCC_QM_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QM_CMD_RCGR_ADDR,v) +#define HWIO_GCC_QM_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QM_CMD_RCGR_ADDR,m,v,HWIO_GCC_QM_CMD_RCGR_IN) +#define HWIO_GCC_QM_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_QM_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_QM_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_QM_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_QM_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_QM_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_QM_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_QM_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_QM_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_QM_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_QM_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QM_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QM_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00042010) +#define HWIO_GCC_QM_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00042010) +#define HWIO_GCC_QM_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00042010) +#define HWIO_GCC_QM_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_QM_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_QM_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_QM_CFG_RCGR_ADDR, HWIO_GCC_QM_CFG_RCGR_RMSK) +#define HWIO_GCC_QM_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QM_CFG_RCGR_ADDR, m) +#define HWIO_GCC_QM_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QM_CFG_RCGR_ADDR,v) +#define HWIO_GCC_QM_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QM_CFG_RCGR_ADDR,m,v,HWIO_GCC_QM_CFG_RCGR_IN) +#define HWIO_GCC_QM_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_QM_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_QM_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QM_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QM_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_QM_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_QM_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_QM_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_QM_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QM_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QM_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QM_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QM_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QM_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QM_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QM_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QM_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QM_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QM_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QM_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QM_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QM_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QM_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QM_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QM_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QM_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QM_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QM_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QM_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QM_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QM_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QM_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QM_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QM_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QM_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QM_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QM_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QM_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QM_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QM_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QM_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QM_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QM_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QM_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QM_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QM_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QM_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QM_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QM_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QM_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QM_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QM_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_MSS_CE_NAV_BRIDGE_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00043000) +#define HWIO_GCC_MSS_CE_NAV_BRIDGE_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00043000) +#define HWIO_GCC_MSS_CE_NAV_BRIDGE_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00043000) +#define HWIO_GCC_MSS_CE_NAV_BRIDGE_BCR_RMSK 0x1 +#define HWIO_GCC_MSS_CE_NAV_BRIDGE_BCR_ATTR 0x3 +#define HWIO_GCC_MSS_CE_NAV_BRIDGE_BCR_IN \ + in_dword_masked(HWIO_GCC_MSS_CE_NAV_BRIDGE_BCR_ADDR, HWIO_GCC_MSS_CE_NAV_BRIDGE_BCR_RMSK) +#define HWIO_GCC_MSS_CE_NAV_BRIDGE_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_CE_NAV_BRIDGE_BCR_ADDR, m) +#define HWIO_GCC_MSS_CE_NAV_BRIDGE_BCR_OUT(v) \ + out_dword(HWIO_GCC_MSS_CE_NAV_BRIDGE_BCR_ADDR,v) +#define HWIO_GCC_MSS_CE_NAV_BRIDGE_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_CE_NAV_BRIDGE_BCR_ADDR,m,v,HWIO_GCC_MSS_CE_NAV_BRIDGE_BCR_IN) +#define HWIO_GCC_MSS_CE_NAV_BRIDGE_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_MSS_CE_NAV_BRIDGE_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_MSS_CE_NAV_BRIDGE_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_CE_NAV_BRIDGE_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_CE_NAV_BRIDGE_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00043004) +#define HWIO_GCC_MSS_CE_NAV_BRIDGE_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00043004) +#define HWIO_GCC_MSS_CE_NAV_BRIDGE_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00043004) +#define HWIO_GCC_MSS_CE_NAV_BRIDGE_AXI_CBCR_RMSK 0x81d00005 +#define HWIO_GCC_MSS_CE_NAV_BRIDGE_AXI_CBCR_ATTR 0x3 +#define HWIO_GCC_MSS_CE_NAV_BRIDGE_AXI_CBCR_IN \ + in_dword_masked(HWIO_GCC_MSS_CE_NAV_BRIDGE_AXI_CBCR_ADDR, HWIO_GCC_MSS_CE_NAV_BRIDGE_AXI_CBCR_RMSK) +#define HWIO_GCC_MSS_CE_NAV_BRIDGE_AXI_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_CE_NAV_BRIDGE_AXI_CBCR_ADDR, m) +#define HWIO_GCC_MSS_CE_NAV_BRIDGE_AXI_CBCR_OUT(v) \ + out_dword(HWIO_GCC_MSS_CE_NAV_BRIDGE_AXI_CBCR_ADDR,v) +#define HWIO_GCC_MSS_CE_NAV_BRIDGE_AXI_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_CE_NAV_BRIDGE_AXI_CBCR_ADDR,m,v,HWIO_GCC_MSS_CE_NAV_BRIDGE_AXI_CBCR_IN) +#define HWIO_GCC_MSS_CE_NAV_BRIDGE_AXI_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_MSS_CE_NAV_BRIDGE_AXI_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_MSS_CE_NAV_BRIDGE_AXI_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_MSS_CE_NAV_BRIDGE_AXI_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_MSS_CE_NAV_BRIDGE_AXI_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_MSS_CE_NAV_BRIDGE_AXI_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_MSS_CE_NAV_BRIDGE_AXI_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_MSS_CE_NAV_BRIDGE_AXI_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_MSS_CE_NAV_BRIDGE_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_MSS_CE_NAV_BRIDGE_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_MSS_CE_NAV_BRIDGE_AXI_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_MSS_CE_NAV_BRIDGE_AXI_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_MSS_CE_NAV_BRIDGE_AXI_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_MSS_CE_NAV_BRIDGE_AXI_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_MSS_CE_NAV_BRIDGE_AXI_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_MSS_CE_NAV_BRIDGE_AXI_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_MSS_CE_NAV_BRIDGE_AXI_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_CE_NAV_BRIDGE_AXI_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPMI_VGIS_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00044000) +#define HWIO_GCC_SPMI_VGIS_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044000) +#define HWIO_GCC_SPMI_VGIS_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044000) +#define HWIO_GCC_SPMI_VGIS_BCR_RMSK 0x1 +#define HWIO_GCC_SPMI_VGIS_BCR_ATTR 0x3 +#define HWIO_GCC_SPMI_VGIS_BCR_IN \ + in_dword_masked(HWIO_GCC_SPMI_VGIS_BCR_ADDR, HWIO_GCC_SPMI_VGIS_BCR_RMSK) +#define HWIO_GCC_SPMI_VGIS_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_SPMI_VGIS_BCR_ADDR, m) +#define HWIO_GCC_SPMI_VGIS_BCR_OUT(v) \ + out_dword(HWIO_GCC_SPMI_VGIS_BCR_ADDR,v) +#define HWIO_GCC_SPMI_VGIS_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPMI_VGIS_BCR_ADDR,m,v,HWIO_GCC_SPMI_VGIS_BCR_IN) +#define HWIO_GCC_SPMI_VGIS_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_SPMI_VGIS_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_SPMI_VGIS_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPMI_VGIS_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPMI_VGIS_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00044004) +#define HWIO_GCC_SPMI_VGIS_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044004) +#define HWIO_GCC_SPMI_VGIS_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044004) +#define HWIO_GCC_SPMI_VGIS_CBCR_RMSK 0x81c0000f +#define HWIO_GCC_SPMI_VGIS_CBCR_ATTR 0x3 +#define HWIO_GCC_SPMI_VGIS_CBCR_IN \ + in_dword_masked(HWIO_GCC_SPMI_VGIS_CBCR_ADDR, HWIO_GCC_SPMI_VGIS_CBCR_RMSK) +#define HWIO_GCC_SPMI_VGIS_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_SPMI_VGIS_CBCR_ADDR, m) +#define HWIO_GCC_SPMI_VGIS_CBCR_OUT(v) \ + out_dword(HWIO_GCC_SPMI_VGIS_CBCR_ADDR,v) +#define HWIO_GCC_SPMI_VGIS_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPMI_VGIS_CBCR_ADDR,m,v,HWIO_GCC_SPMI_VGIS_CBCR_IN) +#define HWIO_GCC_SPMI_VGIS_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SPMI_VGIS_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SPMI_VGIS_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_SPMI_VGIS_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_SPMI_VGIS_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_SPMI_VGIS_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_SPMI_VGIS_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_SPMI_VGIS_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_SPMI_VGIS_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_SPMI_VGIS_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_SPMI_VGIS_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_SPMI_VGIS_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_SPMI_VGIS_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SPMI_VGIS_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_SPMI_VGIS_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_SPMI_VGIS_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_SPMI_VGIS_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPMI_VGIS_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPMI_VGIS_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SPMI_VGIS_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SPMI_VGIS_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPMI_VGIS_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPMI_VGIS_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00044008) +#define HWIO_GCC_SPMI_VGIS_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044008) +#define HWIO_GCC_SPMI_VGIS_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044008) +#define HWIO_GCC_SPMI_VGIS_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_SPMI_VGIS_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_SPMI_VGIS_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_SPMI_VGIS_CMD_RCGR_ADDR, HWIO_GCC_SPMI_VGIS_CMD_RCGR_RMSK) +#define HWIO_GCC_SPMI_VGIS_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_SPMI_VGIS_CMD_RCGR_ADDR, m) +#define HWIO_GCC_SPMI_VGIS_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_SPMI_VGIS_CMD_RCGR_ADDR,v) +#define HWIO_GCC_SPMI_VGIS_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPMI_VGIS_CMD_RCGR_ADDR,m,v,HWIO_GCC_SPMI_VGIS_CMD_RCGR_IN) +#define HWIO_GCC_SPMI_VGIS_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_SPMI_VGIS_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_SPMI_VGIS_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_SPMI_VGIS_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_SPMI_VGIS_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_SPMI_VGIS_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_SPMI_VGIS_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPMI_VGIS_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPMI_VGIS_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_SPMI_VGIS_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_SPMI_VGIS_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPMI_VGIS_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPMI_VGIS_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004400c) +#define HWIO_GCC_SPMI_VGIS_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004400c) +#define HWIO_GCC_SPMI_VGIS_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004400c) +#define HWIO_GCC_SPMI_VGIS_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_SPMI_VGIS_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_SPMI_VGIS_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_SPMI_VGIS_CFG_RCGR_ADDR, HWIO_GCC_SPMI_VGIS_CFG_RCGR_RMSK) +#define HWIO_GCC_SPMI_VGIS_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_SPMI_VGIS_CFG_RCGR_ADDR, m) +#define HWIO_GCC_SPMI_VGIS_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_SPMI_VGIS_CFG_RCGR_ADDR,v) +#define HWIO_GCC_SPMI_VGIS_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPMI_VGIS_CFG_RCGR_ADDR,m,v,HWIO_GCC_SPMI_VGIS_CFG_RCGR_IN) +#define HWIO_GCC_SPMI_VGIS_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_SPMI_VGIS_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_SPMI_VGIS_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPMI_VGIS_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPMI_VGIS_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_SPMI_VGIS_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_SPMI_VGIS_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_SPMI_VGIS_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_SPMI_VGIS_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_SPMI_VGIS_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_SPMI_VGIS_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_SPMI_VGIS_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_SPMI_VGIS_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_SPMI_VGIS_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_SPMI_VGIS_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_SPMI_VGIS_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_SPMI_VGIS_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_SPMI_VGIS_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_SPMI_VGIS_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_SPMI_VGIS_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_SPMI_VGIS_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_SPMI_VGIS_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_SPMI_VGIS_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_SPMI_VGIS_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_SPMI_VGIS_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_SPMI_VGIS_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_SPMI_VGIS_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_SPMI_VGIS_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_SPMI_VGIS_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_SPMI_VGIS_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_SPMI_VGIS_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_SPMI_VGIS_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_SPMI_VGIS_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_SPMI_VGIS_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_SPMI_VGIS_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_SPMI_VGIS_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_SPMI_VGIS_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_SPMI_VGIS_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_SPMI_VGIS_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_SPMI_VGIS_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_SPMI_VGIS_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_SPMI_VGIS_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_SPMI_VGIS_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_SPMI_VGIS_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_SPMI_VGIS_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_SPMI_VGIS_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_SPMI_VGIS_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_SPMI_VGIS_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_SPMI_VGIS_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_SPMI_VGIS_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_SPMI_VGIS_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_SPMI_VGIS_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_MISC_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00045000) +#define HWIO_GCC_MISC_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00045000) +#define HWIO_GCC_MISC_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00045000) +#define HWIO_GCC_MISC_BCR_RMSK 0x1 +#define HWIO_GCC_MISC_BCR_ATTR 0x3 +#define HWIO_GCC_MISC_BCR_IN \ + in_dword_masked(HWIO_GCC_MISC_BCR_ADDR, HWIO_GCC_MISC_BCR_RMSK) +#define HWIO_GCC_MISC_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_MISC_BCR_ADDR, m) +#define HWIO_GCC_MISC_BCR_OUT(v) \ + out_dword(HWIO_GCC_MISC_BCR_ADDR,v) +#define HWIO_GCC_MISC_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MISC_BCR_ADDR,m,v,HWIO_GCC_MISC_BCR_IN) +#define HWIO_GCC_MISC_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_MISC_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_MISC_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_MISC_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_LINK_DOWN_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00067000) +#define HWIO_GCC_PCIE_LINK_DOWN_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00067000) +#define HWIO_GCC_PCIE_LINK_DOWN_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00067000) +#define HWIO_GCC_PCIE_LINK_DOWN_BCR_RMSK 0x1 +#define HWIO_GCC_PCIE_LINK_DOWN_BCR_ATTR 0x3 +#define HWIO_GCC_PCIE_LINK_DOWN_BCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_LINK_DOWN_BCR_ADDR, HWIO_GCC_PCIE_LINK_DOWN_BCR_RMSK) +#define HWIO_GCC_PCIE_LINK_DOWN_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_LINK_DOWN_BCR_ADDR, m) +#define HWIO_GCC_PCIE_LINK_DOWN_BCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_LINK_DOWN_BCR_ADDR,v) +#define HWIO_GCC_PCIE_LINK_DOWN_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_LINK_DOWN_BCR_ADDR,m,v,HWIO_GCC_PCIE_LINK_DOWN_BCR_IN) +#define HWIO_GCC_PCIE_LINK_DOWN_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_PCIE_LINK_DOWN_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_PCIE_LINK_DOWN_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_LINK_DOWN_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_PHY_CFG_AHB_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00068000) +#define HWIO_GCC_PCIE_PHY_CFG_AHB_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00068000) +#define HWIO_GCC_PCIE_PHY_CFG_AHB_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00068000) +#define HWIO_GCC_PCIE_PHY_CFG_AHB_BCR_RMSK 0x1 +#define HWIO_GCC_PCIE_PHY_CFG_AHB_BCR_ATTR 0x3 +#define HWIO_GCC_PCIE_PHY_CFG_AHB_BCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_PHY_CFG_AHB_BCR_ADDR, HWIO_GCC_PCIE_PHY_CFG_AHB_BCR_RMSK) +#define HWIO_GCC_PCIE_PHY_CFG_AHB_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_PHY_CFG_AHB_BCR_ADDR, m) +#define HWIO_GCC_PCIE_PHY_CFG_AHB_BCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_PHY_CFG_AHB_BCR_ADDR,v) +#define HWIO_GCC_PCIE_PHY_CFG_AHB_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_PHY_CFG_AHB_BCR_ADDR,m,v,HWIO_GCC_PCIE_PHY_CFG_AHB_BCR_IN) +#define HWIO_GCC_PCIE_PHY_CFG_AHB_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_PCIE_PHY_CFG_AHB_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_PCIE_PHY_CFG_AHB_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_PHY_CFG_AHB_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_PHY_COM_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00068004) +#define HWIO_GCC_PCIE_PHY_COM_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00068004) +#define HWIO_GCC_PCIE_PHY_COM_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00068004) +#define HWIO_GCC_PCIE_PHY_COM_BCR_RMSK 0x1 +#define HWIO_GCC_PCIE_PHY_COM_BCR_ATTR 0x3 +#define HWIO_GCC_PCIE_PHY_COM_BCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_PHY_COM_BCR_ADDR, HWIO_GCC_PCIE_PHY_COM_BCR_RMSK) +#define HWIO_GCC_PCIE_PHY_COM_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_PHY_COM_BCR_ADDR, m) +#define HWIO_GCC_PCIE_PHY_COM_BCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_PHY_COM_BCR_ADDR,v) +#define HWIO_GCC_PCIE_PHY_COM_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_PHY_COM_BCR_ADDR,m,v,HWIO_GCC_PCIE_PHY_COM_BCR_IN) +#define HWIO_GCC_PCIE_PHY_COM_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_PCIE_PHY_COM_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_PCIE_PHY_COM_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_PHY_COM_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_NOCSR_COM_PHY_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00068008) +#define HWIO_GCC_PCIE_NOCSR_COM_PHY_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00068008) +#define HWIO_GCC_PCIE_NOCSR_COM_PHY_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00068008) +#define HWIO_GCC_PCIE_NOCSR_COM_PHY_BCR_RMSK 0x1 +#define HWIO_GCC_PCIE_NOCSR_COM_PHY_BCR_ATTR 0x3 +#define HWIO_GCC_PCIE_NOCSR_COM_PHY_BCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_NOCSR_COM_PHY_BCR_ADDR, HWIO_GCC_PCIE_NOCSR_COM_PHY_BCR_RMSK) +#define HWIO_GCC_PCIE_NOCSR_COM_PHY_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_NOCSR_COM_PHY_BCR_ADDR, m) +#define HWIO_GCC_PCIE_NOCSR_COM_PHY_BCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_NOCSR_COM_PHY_BCR_ADDR,v) +#define HWIO_GCC_PCIE_NOCSR_COM_PHY_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_NOCSR_COM_PHY_BCR_ADDR,m,v,HWIO_GCC_PCIE_NOCSR_COM_PHY_BCR_IN) +#define HWIO_GCC_PCIE_NOCSR_COM_PHY_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_PCIE_NOCSR_COM_PHY_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_PCIE_NOCSR_COM_PHY_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_NOCSR_COM_PHY_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_PHY_NOCSR_COM_PHY_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006800c) +#define HWIO_GCC_PCIE_PHY_NOCSR_COM_PHY_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006800c) +#define HWIO_GCC_PCIE_PHY_NOCSR_COM_PHY_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006800c) +#define HWIO_GCC_PCIE_PHY_NOCSR_COM_PHY_BCR_RMSK 0x1 +#define HWIO_GCC_PCIE_PHY_NOCSR_COM_PHY_BCR_ATTR 0x3 +#define HWIO_GCC_PCIE_PHY_NOCSR_COM_PHY_BCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_PHY_NOCSR_COM_PHY_BCR_ADDR, HWIO_GCC_PCIE_PHY_NOCSR_COM_PHY_BCR_RMSK) +#define HWIO_GCC_PCIE_PHY_NOCSR_COM_PHY_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_PHY_NOCSR_COM_PHY_BCR_ADDR, m) +#define HWIO_GCC_PCIE_PHY_NOCSR_COM_PHY_BCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_PHY_NOCSR_COM_PHY_BCR_ADDR,v) +#define HWIO_GCC_PCIE_PHY_NOCSR_COM_PHY_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_PHY_NOCSR_COM_PHY_BCR_ADDR,m,v,HWIO_GCC_PCIE_PHY_NOCSR_COM_PHY_BCR_IN) +#define HWIO_GCC_PCIE_PHY_NOCSR_COM_PHY_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_PCIE_PHY_NOCSR_COM_PHY_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_PCIE_PHY_NOCSR_COM_PHY_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_PHY_NOCSR_COM_PHY_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GPLL4_OUT_EVEN_PWRGRP1_CLKGEN_ACGC_ACGCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00090004) +#define HWIO_GCC_GPLL4_OUT_EVEN_PWRGRP1_CLKGEN_ACGC_ACGCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00090004) +#define HWIO_GCC_GPLL4_OUT_EVEN_PWRGRP1_CLKGEN_ACGC_ACGCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00090004) +#define HWIO_GCC_GPLL4_OUT_EVEN_PWRGRP1_CLKGEN_ACGC_ACGCR_RMSK 0x80000001 +#define HWIO_GCC_GPLL4_OUT_EVEN_PWRGRP1_CLKGEN_ACGC_ACGCR_ATTR 0x3 +#define HWIO_GCC_GPLL4_OUT_EVEN_PWRGRP1_CLKGEN_ACGC_ACGCR_IN \ + in_dword_masked(HWIO_GCC_GPLL4_OUT_EVEN_PWRGRP1_CLKGEN_ACGC_ACGCR_ADDR, HWIO_GCC_GPLL4_OUT_EVEN_PWRGRP1_CLKGEN_ACGC_ACGCR_RMSK) +#define HWIO_GCC_GPLL4_OUT_EVEN_PWRGRP1_CLKGEN_ACGC_ACGCR_INM(m) \ + in_dword_masked(HWIO_GCC_GPLL4_OUT_EVEN_PWRGRP1_CLKGEN_ACGC_ACGCR_ADDR, m) +#define HWIO_GCC_GPLL4_OUT_EVEN_PWRGRP1_CLKGEN_ACGC_ACGCR_OUT(v) \ + out_dword(HWIO_GCC_GPLL4_OUT_EVEN_PWRGRP1_CLKGEN_ACGC_ACGCR_ADDR,v) +#define HWIO_GCC_GPLL4_OUT_EVEN_PWRGRP1_CLKGEN_ACGC_ACGCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPLL4_OUT_EVEN_PWRGRP1_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL4_OUT_EVEN_PWRGRP1_CLKGEN_ACGC_ACGCR_IN) +#define HWIO_GCC_GPLL4_OUT_EVEN_PWRGRP1_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK 0x80000000 +#define HWIO_GCC_GPLL4_OUT_EVEN_PWRGRP1_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT 0x1f +#define HWIO_GCC_GPLL4_OUT_EVEN_PWRGRP1_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GPLL4_OUT_EVEN_PWRGRP1_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_GPLL4_OUT_EVEN_PWRGRP1_CLKGEN_ACGC_ACGCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GPLL4_OUT_EVEN_PWRGRP1_CLKGEN_ACGC_ACGCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GPLL4_OUT_EVEN_PWRGRP2_CLKGEN_ACGC_ACGCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00090008) +#define HWIO_GCC_GPLL4_OUT_EVEN_PWRGRP2_CLKGEN_ACGC_ACGCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00090008) +#define HWIO_GCC_GPLL4_OUT_EVEN_PWRGRP2_CLKGEN_ACGC_ACGCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00090008) +#define HWIO_GCC_GPLL4_OUT_EVEN_PWRGRP2_CLKGEN_ACGC_ACGCR_RMSK 0x80000001 +#define HWIO_GCC_GPLL4_OUT_EVEN_PWRGRP2_CLKGEN_ACGC_ACGCR_ATTR 0x3 +#define HWIO_GCC_GPLL4_OUT_EVEN_PWRGRP2_CLKGEN_ACGC_ACGCR_IN \ + in_dword_masked(HWIO_GCC_GPLL4_OUT_EVEN_PWRGRP2_CLKGEN_ACGC_ACGCR_ADDR, HWIO_GCC_GPLL4_OUT_EVEN_PWRGRP2_CLKGEN_ACGC_ACGCR_RMSK) +#define HWIO_GCC_GPLL4_OUT_EVEN_PWRGRP2_CLKGEN_ACGC_ACGCR_INM(m) \ + in_dword_masked(HWIO_GCC_GPLL4_OUT_EVEN_PWRGRP2_CLKGEN_ACGC_ACGCR_ADDR, m) +#define HWIO_GCC_GPLL4_OUT_EVEN_PWRGRP2_CLKGEN_ACGC_ACGCR_OUT(v) \ + out_dword(HWIO_GCC_GPLL4_OUT_EVEN_PWRGRP2_CLKGEN_ACGC_ACGCR_ADDR,v) +#define HWIO_GCC_GPLL4_OUT_EVEN_PWRGRP2_CLKGEN_ACGC_ACGCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPLL4_OUT_EVEN_PWRGRP2_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL4_OUT_EVEN_PWRGRP2_CLKGEN_ACGC_ACGCR_IN) +#define HWIO_GCC_GPLL4_OUT_EVEN_PWRGRP2_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK 0x80000000 +#define HWIO_GCC_GPLL4_OUT_EVEN_PWRGRP2_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT 0x1f +#define HWIO_GCC_GPLL4_OUT_EVEN_PWRGRP2_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GPLL4_OUT_EVEN_PWRGRP2_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_GPLL4_OUT_EVEN_PWRGRP2_CLKGEN_ACGC_ACGCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GPLL4_OUT_EVEN_PWRGRP2_CLKGEN_ACGC_ACGCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GPLL1_OUT_EVEN_PWRGRP2_CLKGEN_ACGC_ACGCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008d008) +#define HWIO_GCC_GPLL1_OUT_EVEN_PWRGRP2_CLKGEN_ACGC_ACGCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008d008) +#define HWIO_GCC_GPLL1_OUT_EVEN_PWRGRP2_CLKGEN_ACGC_ACGCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008d008) +#define HWIO_GCC_GPLL1_OUT_EVEN_PWRGRP2_CLKGEN_ACGC_ACGCR_RMSK 0x80000001 +#define HWIO_GCC_GPLL1_OUT_EVEN_PWRGRP2_CLKGEN_ACGC_ACGCR_ATTR 0x3 +#define HWIO_GCC_GPLL1_OUT_EVEN_PWRGRP2_CLKGEN_ACGC_ACGCR_IN \ + in_dword_masked(HWIO_GCC_GPLL1_OUT_EVEN_PWRGRP2_CLKGEN_ACGC_ACGCR_ADDR, HWIO_GCC_GPLL1_OUT_EVEN_PWRGRP2_CLKGEN_ACGC_ACGCR_RMSK) +#define HWIO_GCC_GPLL1_OUT_EVEN_PWRGRP2_CLKGEN_ACGC_ACGCR_INM(m) \ + in_dword_masked(HWIO_GCC_GPLL1_OUT_EVEN_PWRGRP2_CLKGEN_ACGC_ACGCR_ADDR, m) +#define HWIO_GCC_GPLL1_OUT_EVEN_PWRGRP2_CLKGEN_ACGC_ACGCR_OUT(v) \ + out_dword(HWIO_GCC_GPLL1_OUT_EVEN_PWRGRP2_CLKGEN_ACGC_ACGCR_ADDR,v) +#define HWIO_GCC_GPLL1_OUT_EVEN_PWRGRP2_CLKGEN_ACGC_ACGCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPLL1_OUT_EVEN_PWRGRP2_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL1_OUT_EVEN_PWRGRP2_CLKGEN_ACGC_ACGCR_IN) +#define HWIO_GCC_GPLL1_OUT_EVEN_PWRGRP2_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK 0x80000000 +#define HWIO_GCC_GPLL1_OUT_EVEN_PWRGRP2_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT 0x1f +#define HWIO_GCC_GPLL1_OUT_EVEN_PWRGRP2_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GPLL1_OUT_EVEN_PWRGRP2_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_GPLL1_OUT_EVEN_PWRGRP2_CLKGEN_ACGC_ACGCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GPLL1_OUT_EVEN_PWRGRP2_CLKGEN_ACGC_ACGCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GPLL1_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008d004) +#define HWIO_GCC_GPLL1_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008d004) +#define HWIO_GCC_GPLL1_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008d004) +#define HWIO_GCC_GPLL1_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_RMSK 0x80000001 +#define HWIO_GCC_GPLL1_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_ATTR 0x3 +#define HWIO_GCC_GPLL1_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_IN \ + in_dword_masked(HWIO_GCC_GPLL1_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_ADDR, HWIO_GCC_GPLL1_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_RMSK) +#define HWIO_GCC_GPLL1_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_INM(m) \ + in_dword_masked(HWIO_GCC_GPLL1_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_ADDR, m) +#define HWIO_GCC_GPLL1_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_OUT(v) \ + out_dword(HWIO_GCC_GPLL1_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_ADDR,v) +#define HWIO_GCC_GPLL1_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPLL1_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL1_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_IN) +#define HWIO_GCC_GPLL1_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK 0x80000000 +#define HWIO_GCC_GPLL1_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT 0x1f +#define HWIO_GCC_GPLL1_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GPLL1_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_GPLL1_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GPLL1_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GPLL5_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00091004) +#define HWIO_GCC_GPLL5_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00091004) +#define HWIO_GCC_GPLL5_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00091004) +#define HWIO_GCC_GPLL5_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_RMSK 0x80000001 +#define HWIO_GCC_GPLL5_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_ATTR 0x3 +#define HWIO_GCC_GPLL5_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_IN \ + in_dword_masked(HWIO_GCC_GPLL5_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_ADDR, HWIO_GCC_GPLL5_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_RMSK) +#define HWIO_GCC_GPLL5_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_INM(m) \ + in_dword_masked(HWIO_GCC_GPLL5_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_ADDR, m) +#define HWIO_GCC_GPLL5_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_OUT(v) \ + out_dword(HWIO_GCC_GPLL5_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_ADDR,v) +#define HWIO_GCC_GPLL5_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPLL5_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL5_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_IN) +#define HWIO_GCC_GPLL5_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK 0x80000000 +#define HWIO_GCC_GPLL5_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT 0x1f +#define HWIO_GCC_GPLL5_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GPLL5_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_GPLL5_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GPLL5_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GPLL5_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00091008) +#define HWIO_GCC_GPLL5_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00091008) +#define HWIO_GCC_GPLL5_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00091008) +#define HWIO_GCC_GPLL5_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_RMSK 0x80000001 +#define HWIO_GCC_GPLL5_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_ATTR 0x3 +#define HWIO_GCC_GPLL5_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_IN \ + in_dword_masked(HWIO_GCC_GPLL5_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_ADDR, HWIO_GCC_GPLL5_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_RMSK) +#define HWIO_GCC_GPLL5_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_INM(m) \ + in_dword_masked(HWIO_GCC_GPLL5_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_ADDR, m) +#define HWIO_GCC_GPLL5_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_OUT(v) \ + out_dword(HWIO_GCC_GPLL5_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_ADDR,v) +#define HWIO_GCC_GPLL5_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPLL5_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL5_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_IN) +#define HWIO_GCC_GPLL5_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK 0x80000000 +#define HWIO_GCC_GPLL5_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT 0x1f +#define HWIO_GCC_GPLL5_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GPLL5_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_GPLL5_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GPLL5_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008c004) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008c004) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008c004) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_RMSK 0x80000001 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_ATTR 0x3 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_IN \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_ADDR, HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_RMSK) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_INM(m) \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_ADDR, m) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_OUT(v) \ + out_dword(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_ADDR,v) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_IN) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK 0x80000000 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT 0x1f +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008c008) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008c008) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008c008) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_RMSK 0x80000001 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_ATTR 0x3 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_IN \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_ADDR, HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_RMSK) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_INM(m) \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_ADDR, m) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_OUT(v) \ + out_dword(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_ADDR,v) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_IN) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK 0x80000000 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT 0x1f +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008c00c) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008c00c) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008c00c) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_RMSK 0x80000001 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_ATTR 0x3 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_IN \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_ADDR, HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_RMSK) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_INM(m) \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_ADDR, m) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_OUT(v) \ + out_dword(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_ADDR,v) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_IN) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK 0x80000000 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT 0x1f +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008c010) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008c010) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008c010) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_RMSK 0x80000001 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_ATTR 0x3 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_IN \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_ADDR, HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_RMSK) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_INM(m) \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_ADDR, m) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_OUT(v) \ + out_dword(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_ADDR,v) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_IN) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK 0x80000000 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT 0x1f +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008c014) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008c014) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008c014) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_RMSK 0x80000001 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_ATTR 0x3 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_IN \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_ADDR, HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_RMSK) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_INM(m) \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_ADDR, m) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_OUT(v) \ + out_dword(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_ADDR,v) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_IN) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK 0x80000000 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT 0x1f +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008c018) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008c018) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008c018) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_RMSK 0x80000001 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_ATTR 0x3 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_IN \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_ADDR, HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_RMSK) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_INM(m) \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_ADDR, m) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_OUT(v) \ + out_dword(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_ADDR,v) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_IN) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK 0x80000000 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT 0x1f +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008c01c) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008c01c) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008c01c) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_RMSK 0x80000001 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_ATTR 0x3 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_IN \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_ADDR, HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_RMSK) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_INM(m) \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_ADDR, m) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_OUT(v) \ + out_dword(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_ADDR,v) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_IN) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK 0x80000000 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT 0x1f +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008c020) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008c020) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008c020) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_RMSK 0x80000001 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_ATTR 0x3 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_IN \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_ADDR, HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_RMSK) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_INM(m) \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_ADDR, m) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_OUT(v) \ + out_dword(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_ADDR,v) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_IN) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK 0x80000000 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT 0x1f +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008c024) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008c024) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008c024) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_RMSK 0x80000001 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_ATTR 0x3 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_IN \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_ADDR, HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_RMSK) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_INM(m) \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_ADDR, m) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_OUT(v) \ + out_dword(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_ADDR,v) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_IN) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK 0x80000000 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT 0x1f +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008c028) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008c028) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008c028) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_RMSK 0x80000001 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_ATTR 0x3 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_IN \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_ADDR, HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_RMSK) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_INM(m) \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_ADDR, m) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_OUT(v) \ + out_dword(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_ADDR,v) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_IN) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK 0x80000000 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT 0x1f +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008c02c) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008c02c) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008c02c) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_RMSK 0x80000001 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_ATTR 0x3 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_IN \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_ADDR, HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_RMSK) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_INM(m) \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_ADDR, m) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_OUT(v) \ + out_dword(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_ADDR,v) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_IN) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK 0x80000000 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT 0x1f +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008c030) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008c030) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008c030) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_RMSK 0x80000001 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_ATTR 0x3 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_IN \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_ADDR, HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_RMSK) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_INM(m) \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_ADDR, m) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_OUT(v) \ + out_dword(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_ADDR,v) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_IN) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK 0x80000000 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT 0x1f +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008c03c) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008c03c) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008c03c) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_RMSK 0x80000001 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_ATTR 0x3 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_IN \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_ADDR, HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_RMSK) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_INM(m) \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_ADDR, m) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_OUT(v) \ + out_dword(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_ADDR,v) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_IN) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK 0x80000000 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT 0x1f +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_NAV_MBIST_ACGCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003d008) +#define HWIO_GCC_NAV_MBIST_ACGCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003d008) +#define HWIO_GCC_NAV_MBIST_ACGCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003d008) +#define HWIO_GCC_NAV_MBIST_ACGCR_RMSK 0x80000001 +#define HWIO_GCC_NAV_MBIST_ACGCR_ATTR 0x3 +#define HWIO_GCC_NAV_MBIST_ACGCR_IN \ + in_dword_masked(HWIO_GCC_NAV_MBIST_ACGCR_ADDR, HWIO_GCC_NAV_MBIST_ACGCR_RMSK) +#define HWIO_GCC_NAV_MBIST_ACGCR_INM(m) \ + in_dword_masked(HWIO_GCC_NAV_MBIST_ACGCR_ADDR, m) +#define HWIO_GCC_NAV_MBIST_ACGCR_OUT(v) \ + out_dword(HWIO_GCC_NAV_MBIST_ACGCR_ADDR,v) +#define HWIO_GCC_NAV_MBIST_ACGCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_NAV_MBIST_ACGCR_ADDR,m,v,HWIO_GCC_NAV_MBIST_ACGCR_IN) +#define HWIO_GCC_NAV_MBIST_ACGCR_CLK_ON_BMSK 0x80000000 +#define HWIO_GCC_NAV_MBIST_ACGCR_CLK_ON_SHFT 0x1f +#define HWIO_GCC_NAV_MBIST_ACGCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_NAV_MBIST_ACGCR_CLK_ENABLE_SHFT 0x0 + +#define HWIO_GCC_USB3_PHY_PIPE_MUXR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000706c) +#define HWIO_GCC_USB3_PHY_PIPE_MUXR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000706c) +#define HWIO_GCC_USB3_PHY_PIPE_MUXR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000706c) +#define HWIO_GCC_USB3_PHY_PIPE_MUXR_RMSK 0x3 +#define HWIO_GCC_USB3_PHY_PIPE_MUXR_ATTR 0x3 +#define HWIO_GCC_USB3_PHY_PIPE_MUXR_IN \ + in_dword_masked(HWIO_GCC_USB3_PHY_PIPE_MUXR_ADDR, HWIO_GCC_USB3_PHY_PIPE_MUXR_RMSK) +#define HWIO_GCC_USB3_PHY_PIPE_MUXR_INM(m) \ + in_dword_masked(HWIO_GCC_USB3_PHY_PIPE_MUXR_ADDR, m) +#define HWIO_GCC_USB3_PHY_PIPE_MUXR_OUT(v) \ + out_dword(HWIO_GCC_USB3_PHY_PIPE_MUXR_ADDR,v) +#define HWIO_GCC_USB3_PHY_PIPE_MUXR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB3_PHY_PIPE_MUXR_ADDR,m,v,HWIO_GCC_USB3_PHY_PIPE_MUXR_IN) +#define HWIO_GCC_USB3_PHY_PIPE_MUXR_MUX_SEL_BMSK 0x3 +#define HWIO_GCC_USB3_PHY_PIPE_MUXR_MUX_SEL_SHFT 0x0 + +#define HWIO_GCC_JBIST_REF_CLK_MUXR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001e034) +#define HWIO_GCC_JBIST_REF_CLK_MUXR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e034) +#define HWIO_GCC_JBIST_REF_CLK_MUXR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e034) +#define HWIO_GCC_JBIST_REF_CLK_MUXR_RMSK 0x3 +#define HWIO_GCC_JBIST_REF_CLK_MUXR_ATTR 0x3 +#define HWIO_GCC_JBIST_REF_CLK_MUXR_IN \ + in_dword_masked(HWIO_GCC_JBIST_REF_CLK_MUXR_ADDR, HWIO_GCC_JBIST_REF_CLK_MUXR_RMSK) +#define HWIO_GCC_JBIST_REF_CLK_MUXR_INM(m) \ + in_dword_masked(HWIO_GCC_JBIST_REF_CLK_MUXR_ADDR, m) +#define HWIO_GCC_JBIST_REF_CLK_MUXR_OUT(v) \ + out_dword(HWIO_GCC_JBIST_REF_CLK_MUXR_ADDR,v) +#define HWIO_GCC_JBIST_REF_CLK_MUXR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_JBIST_REF_CLK_MUXR_ADDR,m,v,HWIO_GCC_JBIST_REF_CLK_MUXR_IN) +#define HWIO_GCC_JBIST_REF_CLK_MUXR_MUX_SEL_BMSK 0x3 +#define HWIO_GCC_JBIST_REF_CLK_MUXR_MUX_SEL_SHFT 0x0 + +#define HWIO_GCC_PCIE_PIPE_MUXR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00033044) +#define HWIO_GCC_PCIE_PIPE_MUXR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00033044) +#define HWIO_GCC_PCIE_PIPE_MUXR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00033044) +#define HWIO_GCC_PCIE_PIPE_MUXR_RMSK 0x3 +#define HWIO_GCC_PCIE_PIPE_MUXR_ATTR 0x3 +#define HWIO_GCC_PCIE_PIPE_MUXR_IN \ + in_dword_masked(HWIO_GCC_PCIE_PIPE_MUXR_ADDR, HWIO_GCC_PCIE_PIPE_MUXR_RMSK) +#define HWIO_GCC_PCIE_PIPE_MUXR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_PIPE_MUXR_ADDR, m) +#define HWIO_GCC_PCIE_PIPE_MUXR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_PIPE_MUXR_ADDR,v) +#define HWIO_GCC_PCIE_PIPE_MUXR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_PIPE_MUXR_ADDR,m,v,HWIO_GCC_PCIE_PIPE_MUXR_IN) +#define HWIO_GCC_PCIE_PIPE_MUXR_MUX_SEL_BMSK 0x3 +#define HWIO_GCC_PCIE_PIPE_MUXR_MUX_SEL_SHFT 0x0 + +#define HWIO_GCC_PCIE_AUX_MUXR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00033060) +#define HWIO_GCC_PCIE_AUX_MUXR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00033060) +#define HWIO_GCC_PCIE_AUX_MUXR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00033060) +#define HWIO_GCC_PCIE_AUX_MUXR_RMSK 0x3 +#define HWIO_GCC_PCIE_AUX_MUXR_ATTR 0x3 +#define HWIO_GCC_PCIE_AUX_MUXR_IN \ + in_dword_masked(HWIO_GCC_PCIE_AUX_MUXR_ADDR, HWIO_GCC_PCIE_AUX_MUXR_RMSK) +#define HWIO_GCC_PCIE_AUX_MUXR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_AUX_MUXR_ADDR, m) +#define HWIO_GCC_PCIE_AUX_MUXR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_AUX_MUXR_ADDR,v) +#define HWIO_GCC_PCIE_AUX_MUXR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_AUX_MUXR_ADDR,m,v,HWIO_GCC_PCIE_AUX_MUXR_IN) +#define HWIO_GCC_PCIE_AUX_MUXR_MUX_SEL_BMSK 0x3 +#define HWIO_GCC_PCIE_AUX_MUXR_MUX_SEL_SHFT 0x0 + +#define HWIO_GCC_PCIE_MBIST_MUXR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003307c) +#define HWIO_GCC_PCIE_MBIST_MUXR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003307c) +#define HWIO_GCC_PCIE_MBIST_MUXR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003307c) +#define HWIO_GCC_PCIE_MBIST_MUXR_RMSK 0x3 +#define HWIO_GCC_PCIE_MBIST_MUXR_ATTR 0x3 +#define HWIO_GCC_PCIE_MBIST_MUXR_IN \ + in_dword_masked(HWIO_GCC_PCIE_MBIST_MUXR_ADDR, HWIO_GCC_PCIE_MBIST_MUXR_RMSK) +#define HWIO_GCC_PCIE_MBIST_MUXR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_MBIST_MUXR_ADDR, m) +#define HWIO_GCC_PCIE_MBIST_MUXR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_MBIST_MUXR_ADDR,v) +#define HWIO_GCC_PCIE_MBIST_MUXR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_MBIST_MUXR_ADDR,m,v,HWIO_GCC_PCIE_MBIST_MUXR_IN) +#define HWIO_GCC_PCIE_MBIST_MUXR_MUX_SEL_BMSK 0x3 +#define HWIO_GCC_PCIE_MBIST_MUXR_MUX_SEL_SHFT 0x0 + +#define HWIO_GCC_NAV_MBIST_MUXR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003d00c) +#define HWIO_GCC_NAV_MBIST_MUXR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003d00c) +#define HWIO_GCC_NAV_MBIST_MUXR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003d00c) +#define HWIO_GCC_NAV_MBIST_MUXR_RMSK 0x1 +#define HWIO_GCC_NAV_MBIST_MUXR_ATTR 0x3 +#define HWIO_GCC_NAV_MBIST_MUXR_IN \ + in_dword_masked(HWIO_GCC_NAV_MBIST_MUXR_ADDR, HWIO_GCC_NAV_MBIST_MUXR_RMSK) +#define HWIO_GCC_NAV_MBIST_MUXR_INM(m) \ + in_dword_masked(HWIO_GCC_NAV_MBIST_MUXR_ADDR, m) +#define HWIO_GCC_NAV_MBIST_MUXR_OUT(v) \ + out_dword(HWIO_GCC_NAV_MBIST_MUXR_ADDR,v) +#define HWIO_GCC_NAV_MBIST_MUXR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_NAV_MBIST_MUXR_ADDR,m,v,HWIO_GCC_NAV_MBIST_MUXR_IN) +#define HWIO_GCC_NAV_MBIST_MUXR_MUX_SEL_BMSK 0x1 +#define HWIO_GCC_NAV_MBIST_MUXR_MUX_SEL_SHFT 0x0 + +#define HWIO_GCC_MSS_Q6SS_BOOT_GPLL0_MUXR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00030144) +#define HWIO_GCC_MSS_Q6SS_BOOT_GPLL0_MUXR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00030144) +#define HWIO_GCC_MSS_Q6SS_BOOT_GPLL0_MUXR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00030144) +#define HWIO_GCC_MSS_Q6SS_BOOT_GPLL0_MUXR_RMSK 0x1 +#define HWIO_GCC_MSS_Q6SS_BOOT_GPLL0_MUXR_ATTR 0x3 +#define HWIO_GCC_MSS_Q6SS_BOOT_GPLL0_MUXR_IN \ + in_dword_masked(HWIO_GCC_MSS_Q6SS_BOOT_GPLL0_MUXR_ADDR, HWIO_GCC_MSS_Q6SS_BOOT_GPLL0_MUXR_RMSK) +#define HWIO_GCC_MSS_Q6SS_BOOT_GPLL0_MUXR_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_Q6SS_BOOT_GPLL0_MUXR_ADDR, m) +#define HWIO_GCC_MSS_Q6SS_BOOT_GPLL0_MUXR_OUT(v) \ + out_dword(HWIO_GCC_MSS_Q6SS_BOOT_GPLL0_MUXR_ADDR,v) +#define HWIO_GCC_MSS_Q6SS_BOOT_GPLL0_MUXR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_Q6SS_BOOT_GPLL0_MUXR_ADDR,m,v,HWIO_GCC_MSS_Q6SS_BOOT_GPLL0_MUXR_IN) +#define HWIO_GCC_MSS_Q6SS_BOOT_GPLL0_MUXR_MUX_SEL_BMSK 0x1 +#define HWIO_GCC_MSS_Q6SS_BOOT_GPLL0_MUXR_MUX_SEL_SHFT 0x0 + +#define HWIO_GCC_AUDIO_PLL_REF_MUXR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00055000) +#define HWIO_GCC_AUDIO_PLL_REF_MUXR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00055000) +#define HWIO_GCC_AUDIO_PLL_REF_MUXR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00055000) +#define HWIO_GCC_AUDIO_PLL_REF_MUXR_RMSK 0x3 +#define HWIO_GCC_AUDIO_PLL_REF_MUXR_ATTR 0x3 +#define HWIO_GCC_AUDIO_PLL_REF_MUXR_IN \ + in_dword_masked(HWIO_GCC_AUDIO_PLL_REF_MUXR_ADDR, HWIO_GCC_AUDIO_PLL_REF_MUXR_RMSK) +#define HWIO_GCC_AUDIO_PLL_REF_MUXR_INM(m) \ + in_dword_masked(HWIO_GCC_AUDIO_PLL_REF_MUXR_ADDR, m) +#define HWIO_GCC_AUDIO_PLL_REF_MUXR_OUT(v) \ + out_dword(HWIO_GCC_AUDIO_PLL_REF_MUXR_ADDR,v) +#define HWIO_GCC_AUDIO_PLL_REF_MUXR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AUDIO_PLL_REF_MUXR_ADDR,m,v,HWIO_GCC_AUDIO_PLL_REF_MUXR_IN) +#define HWIO_GCC_AUDIO_PLL_REF_MUXR_MUX_SEL_BMSK 0x3 +#define HWIO_GCC_AUDIO_PLL_REF_MUXR_MUX_SEL_SHFT 0x0 +#define HWIO_GCC_AUDIO_PLL_REF_MUXR_MUX_SEL_TCXO_FVAL 0x0 +#define HWIO_GCC_AUDIO_PLL_REF_MUXR_MUX_SEL_AUD_REF_CLK_FVAL 0x1 +#define HWIO_GCC_AUDIO_PLL_REF_MUXR_MUX_SEL_PTP_PPS_CLK_FVAL 0x2 + +#define HWIO_GCC_IPA_AHB_MISC_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00056000) +#define HWIO_GCC_IPA_AHB_MISC_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00056000) +#define HWIO_GCC_IPA_AHB_MISC_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00056000) +#define HWIO_GCC_IPA_AHB_MISC_CBCR_RMSK 0x2 +#define HWIO_GCC_IPA_AHB_MISC_CBCR_ATTR 0x3 +#define HWIO_GCC_IPA_AHB_MISC_CBCR_IN \ + in_dword_masked(HWIO_GCC_IPA_AHB_MISC_CBCR_ADDR, HWIO_GCC_IPA_AHB_MISC_CBCR_RMSK) +#define HWIO_GCC_IPA_AHB_MISC_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_IPA_AHB_MISC_CBCR_ADDR, m) +#define HWIO_GCC_IPA_AHB_MISC_CBCR_OUT(v) \ + out_dword(HWIO_GCC_IPA_AHB_MISC_CBCR_ADDR,v) +#define HWIO_GCC_IPA_AHB_MISC_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_IPA_AHB_MISC_CBCR_ADDR,m,v,HWIO_GCC_IPA_AHB_MISC_CBCR_IN) +#define HWIO_GCC_IPA_AHB_MISC_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_IPA_AHB_MISC_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_IPA_AHB_MISC_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_AHB_MISC_CBCR_HW_CTL_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TCSR_PCIE_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00047000) +#define HWIO_GCC_TCSR_PCIE_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00047000) +#define HWIO_GCC_TCSR_PCIE_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00047000) +#define HWIO_GCC_TCSR_PCIE_BCR_RMSK 0x1 +#define HWIO_GCC_TCSR_PCIE_BCR_ATTR 0x3 +#define HWIO_GCC_TCSR_PCIE_BCR_IN \ + in_dword_masked(HWIO_GCC_TCSR_PCIE_BCR_ADDR, HWIO_GCC_TCSR_PCIE_BCR_RMSK) +#define HWIO_GCC_TCSR_PCIE_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_TCSR_PCIE_BCR_ADDR, m) +#define HWIO_GCC_TCSR_PCIE_BCR_OUT(v) \ + out_dword(HWIO_GCC_TCSR_PCIE_BCR_ADDR,v) +#define HWIO_GCC_TCSR_PCIE_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TCSR_PCIE_BCR_ADDR,m,v,HWIO_GCC_TCSR_PCIE_BCR_IN) +#define HWIO_GCC_TCSR_PCIE_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_TCSR_PCIE_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_TCSR_PCIE_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_TCSR_PCIE_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GPLL4_PLL_TEST_SE_OVRD_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00057000) +#define HWIO_GCC_GPLL4_PLL_TEST_SE_OVRD_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00057000) +#define HWIO_GCC_GPLL4_PLL_TEST_SE_OVRD_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00057000) +#define HWIO_GCC_GPLL4_PLL_TEST_SE_OVRD_RMSK 0x1 +#define HWIO_GCC_GPLL4_PLL_TEST_SE_OVRD_ATTR 0x3 +#define HWIO_GCC_GPLL4_PLL_TEST_SE_OVRD_IN \ + in_dword_masked(HWIO_GCC_GPLL4_PLL_TEST_SE_OVRD_ADDR, HWIO_GCC_GPLL4_PLL_TEST_SE_OVRD_RMSK) +#define HWIO_GCC_GPLL4_PLL_TEST_SE_OVRD_INM(m) \ + in_dword_masked(HWIO_GCC_GPLL4_PLL_TEST_SE_OVRD_ADDR, m) +#define HWIO_GCC_GPLL4_PLL_TEST_SE_OVRD_OUT(v) \ + out_dword(HWIO_GCC_GPLL4_PLL_TEST_SE_OVRD_ADDR,v) +#define HWIO_GCC_GPLL4_PLL_TEST_SE_OVRD_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPLL4_PLL_TEST_SE_OVRD_ADDR,m,v,HWIO_GCC_GPLL4_PLL_TEST_SE_OVRD_IN) +#define HWIO_GCC_GPLL4_PLL_TEST_SE_OVRD_OVRD_BMSK 0x1 +#define HWIO_GCC_GPLL4_PLL_TEST_SE_OVRD_OVRD_SHFT 0x0 + +#define HWIO_GCC_ACC_MISC_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00058000) +#define HWIO_GCC_ACC_MISC_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00058000) +#define HWIO_GCC_ACC_MISC_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00058000) +#define HWIO_GCC_ACC_MISC_RMSK 0x1 +#define HWIO_GCC_ACC_MISC_ATTR 0x3 +#define HWIO_GCC_ACC_MISC_IN \ + in_dword_masked(HWIO_GCC_ACC_MISC_ADDR, HWIO_GCC_ACC_MISC_RMSK) +#define HWIO_GCC_ACC_MISC_INM(m) \ + in_dword_masked(HWIO_GCC_ACC_MISC_ADDR, m) +#define HWIO_GCC_ACC_MISC_OUT(v) \ + out_dword(HWIO_GCC_ACC_MISC_ADDR,v) +#define HWIO_GCC_ACC_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ACC_MISC_ADDR,m,v,HWIO_GCC_ACC_MISC_IN) +#define HWIO_GCC_ACC_MISC_JTAG_ACC_SRC_SEL_EN_BMSK 0x1 +#define HWIO_GCC_ACC_MISC_JTAG_ACC_SRC_SEL_EN_SHFT 0x0 +#define HWIO_GCC_ACC_MISC_JTAG_ACC_SRC_SEL_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_ACC_MISC_JTAG_ACC_SRC_SEL_EN_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CPUSS_AHB_MISC_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00059000) +#define HWIO_GCC_CPUSS_AHB_MISC_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00059000) +#define HWIO_GCC_CPUSS_AHB_MISC_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00059000) +#define HWIO_GCC_CPUSS_AHB_MISC_RMSK 0xf1 +#define HWIO_GCC_CPUSS_AHB_MISC_ATTR 0x3 +#define HWIO_GCC_CPUSS_AHB_MISC_IN \ + in_dword_masked(HWIO_GCC_CPUSS_AHB_MISC_ADDR, HWIO_GCC_CPUSS_AHB_MISC_RMSK) +#define HWIO_GCC_CPUSS_AHB_MISC_INM(m) \ + in_dword_masked(HWIO_GCC_CPUSS_AHB_MISC_ADDR, m) +#define HWIO_GCC_CPUSS_AHB_MISC_OUT(v) \ + out_dword(HWIO_GCC_CPUSS_AHB_MISC_ADDR,v) +#define HWIO_GCC_CPUSS_AHB_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CPUSS_AHB_MISC_ADDR,m,v,HWIO_GCC_CPUSS_AHB_MISC_IN) +#define HWIO_GCC_CPUSS_AHB_MISC_CPUSS_AHB_CLK_AUTO_SCALE_DIV_BMSK 0xf0 +#define HWIO_GCC_CPUSS_AHB_MISC_CPUSS_AHB_CLK_AUTO_SCALE_DIV_SHFT 0x4 +#define HWIO_GCC_CPUSS_AHB_MISC_CPUSS_AHB_CLK_AUTO_SCALE_DIV_DIV1_FVAL 0x0 +#define HWIO_GCC_CPUSS_AHB_MISC_CPUSS_AHB_CLK_AUTO_SCALE_DIV_DIV2_FVAL 0x1 +#define HWIO_GCC_CPUSS_AHB_MISC_CPUSS_AHB_CLK_AUTO_SCALE_DIV_DIV3_FVAL 0x2 +#define HWIO_GCC_CPUSS_AHB_MISC_CPUSS_AHB_CLK_AUTO_SCALE_DIV_DIV4_FVAL 0x3 +#define HWIO_GCC_CPUSS_AHB_MISC_CPUSS_AHB_CLK_AUTO_SCALE_DIV_DIV5_FVAL 0x4 +#define HWIO_GCC_CPUSS_AHB_MISC_CPUSS_AHB_CLK_AUTO_SCALE_DIV_DIV6_FVAL 0x5 +#define HWIO_GCC_CPUSS_AHB_MISC_CPUSS_AHB_CLK_AUTO_SCALE_DIV_DIV7_FVAL 0x6 +#define HWIO_GCC_CPUSS_AHB_MISC_CPUSS_AHB_CLK_AUTO_SCALE_DIV_DIV8_FVAL 0x7 +#define HWIO_GCC_CPUSS_AHB_MISC_CPUSS_AHB_CLK_AUTO_SCALE_DIV_DIV9_FVAL 0x8 +#define HWIO_GCC_CPUSS_AHB_MISC_CPUSS_AHB_CLK_AUTO_SCALE_DIV_DIV10_FVAL 0x9 +#define HWIO_GCC_CPUSS_AHB_MISC_CPUSS_AHB_CLK_AUTO_SCALE_DIV_DIV11_FVAL 0xa +#define HWIO_GCC_CPUSS_AHB_MISC_CPUSS_AHB_CLK_AUTO_SCALE_DIV_DIV12_FVAL 0xb +#define HWIO_GCC_CPUSS_AHB_MISC_CPUSS_AHB_CLK_AUTO_SCALE_DIV_DIV13_FVAL 0xc +#define HWIO_GCC_CPUSS_AHB_MISC_CPUSS_AHB_CLK_AUTO_SCALE_DIV_DIV14_FVAL 0xd +#define HWIO_GCC_CPUSS_AHB_MISC_CPUSS_AHB_CLK_AUTO_SCALE_DIV_DIV15_FVAL 0xe +#define HWIO_GCC_CPUSS_AHB_MISC_CPUSS_AHB_CLK_AUTO_SCALE_DIV_DIV16_FVAL 0xf +#define HWIO_GCC_CPUSS_AHB_MISC_CPUSS_AHB_CLK_AUTO_SCALE_DIS_BMSK 0x1 +#define HWIO_GCC_CPUSS_AHB_MISC_CPUSS_AHB_CLK_AUTO_SCALE_DIS_SHFT 0x0 +#define HWIO_GCC_CPUSS_AHB_MISC_CPUSS_AHB_CLK_AUTO_SCALE_DIS_SCALE_NOT_DISABLE_FVAL 0x0 +#define HWIO_GCC_CPUSS_AHB_MISC_CPUSS_AHB_CLK_AUTO_SCALE_DIS_SCALE_DISABLE_FVAL 0x1 + +#define HWIO_GCC_USB_30_MISC_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005a000) +#define HWIO_GCC_USB_30_MISC_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005a000) +#define HWIO_GCC_USB_30_MISC_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005a000) +#define HWIO_GCC_USB_30_MISC_RMSK 0x1 +#define HWIO_GCC_USB_30_MISC_ATTR 0x3 +#define HWIO_GCC_USB_30_MISC_IN \ + in_dword_masked(HWIO_GCC_USB_30_MISC_ADDR, HWIO_GCC_USB_30_MISC_RMSK) +#define HWIO_GCC_USB_30_MISC_INM(m) \ + in_dword_masked(HWIO_GCC_USB_30_MISC_ADDR, m) +#define HWIO_GCC_USB_30_MISC_OUT(v) \ + out_dword(HWIO_GCC_USB_30_MISC_ADDR,v) +#define HWIO_GCC_USB_30_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB_30_MISC_ADDR,m,v,HWIO_GCC_USB_30_MISC_IN) +#define HWIO_GCC_USB_30_MISC_BLK_ARES_ALL_BMSK 0x1 +#define HWIO_GCC_USB_30_MISC_BLK_ARES_ALL_SHFT 0x0 +#define HWIO_GCC_USB_30_MISC_BLK_ARES_ALL_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB_30_MISC_BLK_ARES_ALL_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPM_GPLL_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005c000) +#define HWIO_GCC_RPM_GPLL_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005c000) +#define HWIO_GCC_RPM_GPLL_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005c000) +#define HWIO_GCC_RPM_GPLL_ENA_VOTE_RMSK 0x7f +#define HWIO_GCC_RPM_GPLL_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPM_GPLL_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPM_GPLL_ENA_VOTE_ADDR, HWIO_GCC_RPM_GPLL_ENA_VOTE_RMSK) +#define HWIO_GCC_RPM_GPLL_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPM_GPLL_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPM_GPLL_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPM_GPLL_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPM_GPLL_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPM_GPLL_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPM_GPLL_ENA_VOTE_IN) +#define HWIO_GCC_RPM_GPLL_ENA_VOTE_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPM_GPLL_ENA_VOTE_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPM_GPLL_ENA_VOTE_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_GPLL_ENA_VOTE_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_GPLL_ENA_VOTE_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPM_GPLL_ENA_VOTE_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPM_GPLL_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_GPLL_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_GPLL_ENA_VOTE_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPM_GPLL_ENA_VOTE_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPM_GPLL_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_GPLL_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_GPLL_ENA_VOTE_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPM_GPLL_ENA_VOTE_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPM_GPLL_ENA_VOTE_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_GPLL_ENA_VOTE_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_GPLL_ENA_VOTE_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPM_GPLL_ENA_VOTE_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPM_GPLL_ENA_VOTE_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_GPLL_ENA_VOTE_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_GPLL_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPM_GPLL_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPM_GPLL_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_GPLL_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_GPLL_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPM_GPLL_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPM_GPLL_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_GPLL_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPM_GPLL_SLEEP_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005c004) +#define HWIO_GCC_RPM_GPLL_SLEEP_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005c004) +#define HWIO_GCC_RPM_GPLL_SLEEP_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005c004) +#define HWIO_GCC_RPM_GPLL_SLEEP_ENA_VOTE_RMSK 0x7f +#define HWIO_GCC_RPM_GPLL_SLEEP_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPM_GPLL_SLEEP_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPM_GPLL_SLEEP_ENA_VOTE_ADDR, HWIO_GCC_RPM_GPLL_SLEEP_ENA_VOTE_RMSK) +#define HWIO_GCC_RPM_GPLL_SLEEP_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPM_GPLL_SLEEP_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPM_GPLL_SLEEP_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPM_GPLL_SLEEP_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPM_GPLL_SLEEP_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPM_GPLL_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPM_GPLL_SLEEP_ENA_VOTE_IN) +#define HWIO_GCC_RPM_GPLL_SLEEP_ENA_VOTE_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPM_GPLL_SLEEP_ENA_VOTE_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPM_GPLL_SLEEP_ENA_VOTE_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_GPLL_SLEEP_ENA_VOTE_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_GPLL_SLEEP_ENA_VOTE_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPM_GPLL_SLEEP_ENA_VOTE_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPM_GPLL_SLEEP_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_GPLL_SLEEP_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_GPLL_SLEEP_ENA_VOTE_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPM_GPLL_SLEEP_ENA_VOTE_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPM_GPLL_SLEEP_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_GPLL_SLEEP_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_GPLL_SLEEP_ENA_VOTE_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPM_GPLL_SLEEP_ENA_VOTE_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPM_GPLL_SLEEP_ENA_VOTE_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_GPLL_SLEEP_ENA_VOTE_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_GPLL_SLEEP_ENA_VOTE_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPM_GPLL_SLEEP_ENA_VOTE_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPM_GPLL_SLEEP_ENA_VOTE_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_GPLL_SLEEP_ENA_VOTE_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_GPLL_SLEEP_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPM_GPLL_SLEEP_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPM_GPLL_SLEEP_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_GPLL_SLEEP_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_GPLL_SLEEP_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPM_GPLL_SLEEP_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPM_GPLL_SLEEP_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_GPLL_SLEEP_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005c008) +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005c008) +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005c008) +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_RMSK 0x162f5ff +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_ADDR, HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_RMSK) +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_IN) +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_IMEM_AXI_CLK_ENA_BMSK 0x1000000 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_IMEM_AXI_CLK_ENA_SHFT 0x18 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_IMEM_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_IMEM_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_CPUSS_GNOC_CLK_ENA_BMSK 0x400000 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_CPUSS_GNOC_CLK_ENA_SHFT 0x16 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_CPUSS_GNOC_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_CPUSS_GNOC_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_BMSK 0x200000 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_SHFT 0x15 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_BMSK 0x20000 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_SHFT 0x11 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_BLSP1_SLEEP_CLK_ENA_BMSK 0x8000 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_BLSP1_SLEEP_CLK_ENA_SHFT 0xf +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_BLSP1_SLEEP_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_BLSP1_SLEEP_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_BLSP1_AHB_CLK_ENA_BMSK 0x4000 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_BLSP1_AHB_CLK_ENA_SHFT 0xe +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_BLSP1_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_BLSP1_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_BMSK 0x2000 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_SHFT 0xd +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_BMSK 0x1000 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_SHFT 0xc +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_BMSK 0x400 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_SHFT 0xa +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_ENA_BMSK 0x100 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_ENA_SHFT 0x8 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_ENA_BMSK 0x80 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_ENA_SHFT 0x7 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_BMSK 0x40 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_SHFT 0x6 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_BMSK 0x20 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_SHFT 0x5 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_BMSK 0x10 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_SHFT 0x4 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_BMSK 0x8 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_SHFT 0x3 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_BMSK 0x4 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_SHFT 0x2 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_BMSK 0x2 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_SHFT 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_BMSK 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_SHFT 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005c00c) +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005c00c) +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005c00c) +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_RMSK 0x162f5ff +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_ADDR, HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_RMSK) +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_IN) +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_IMEM_AXI_CLK_SLEEP_ENA_BMSK 0x1000000 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_IMEM_AXI_CLK_SLEEP_ENA_SHFT 0x18 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_IMEM_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_IMEM_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_CPUSS_GNOC_CLK_SLEEP_ENA_BMSK 0x400000 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_CPUSS_GNOC_CLK_SLEEP_ENA_SHFT 0x16 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_CPUSS_GNOC_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_CPUSS_GNOC_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_BMSK 0x200000 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_SHFT 0x15 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK 0x20000 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT 0x11 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_BLSP1_SLEEP_CLK_SLEEP_ENA_BMSK 0x8000 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_BLSP1_SLEEP_CLK_SLEEP_ENA_SHFT 0xf +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_BLSP1_SLEEP_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_BLSP1_SLEEP_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_BLSP1_AHB_CLK_SLEEP_ENA_BMSK 0x4000 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_BLSP1_AHB_CLK_SLEEP_ENA_SHFT 0xe +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_BLSP1_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_BLSP1_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_BMSK 0x2000 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_SHFT 0xd +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_BMSK 0x1000 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_SHFT 0xc +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_BMSK 0x400 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_SHFT 0xa +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_SLEEP_ENA_BMSK 0x100 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_SLEEP_ENA_SHFT 0x8 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_SLEEP_ENA_BMSK 0x80 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_SLEEP_ENA_SHFT 0x7 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_BMSK 0x40 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_SHFT 0x6 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_BMSK 0x20 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_SHFT 0x5 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_BMSK 0x10 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_SHFT 0x4 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_BMSK 0x8 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_SHFT 0x3 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_BMSK 0x4 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_SHFT 0x2 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_BMSK 0x2 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_SHFT 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_BMSK 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_SHFT 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005c010) +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005c010) +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005c010) +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_RMSK 0xff +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_ATTR 0x3 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_IN \ + in_dword_masked(HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_ADDR, HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_RMSK) +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_INM(m) \ + in_dword_masked(HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_ADDR, m) +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_OUT(v) \ + out_dword(HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_ADDR,v) +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_ADDR,m,v,HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_IN) +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_ENA_BMSK 0x80 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_ENA_SHFT 0x7 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLEEP_CLK_ENA_BMSK 0x40 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLEEP_CLK_ENA_SHFT 0x6 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLEEP_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLEEP_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_ENA_BMSK 0x20 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_ENA_SHFT 0x5 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_PIPE_CLK_ENA_BMSK 0x10 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_PIPE_CLK_ENA_SHFT 0x4 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_PIPE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_PIPE_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_AUX_CLK_ENA_BMSK 0x8 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_AUX_CLK_ENA_SHFT 0x3 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_AUX_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_AUX_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_CFG_AHB_CLK_ENA_BMSK 0x4 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_CFG_AHB_CLK_ENA_SHFT 0x2 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_CFG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_CFG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_ENA_BMSK 0x2 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_ENA_SHFT 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_AXI_CLK_ENA_BMSK 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_AXI_CLK_ENA_SHFT 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_AXI_CLK_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005c014) +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005c014) +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005c014) +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_RMSK 0xff +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_ATTR 0x3 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_IN \ + in_dword_masked(HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_ADDR, HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_RMSK) +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_INM(m) \ + in_dword_masked(HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_ADDR, m) +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_OUT(v) \ + out_dword(HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_ADDR,v) +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_ADDR,m,v,HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_IN) +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_SLEEP_ENA_BMSK 0x80 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_SLEEP_ENA_SHFT 0x7 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLEEP_CLK_SLEEP_ENA_BMSK 0x40 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLEEP_CLK_SLEEP_ENA_SHFT 0x6 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLEEP_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLEEP_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK 0x20 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT 0x5 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_PIPE_CLK_SLEEP_ENA_BMSK 0x10 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_PIPE_CLK_SLEEP_ENA_SHFT 0x4 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_PIPE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_PIPE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_AUX_CLK_SLEEP_ENA_BMSK 0x8 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_AUX_CLK_SLEEP_ENA_SHFT 0x3 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_AUX_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_AUX_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_CFG_AHB_CLK_SLEEP_ENA_BMSK 0x4 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_CFG_AHB_CLK_SLEEP_ENA_SHFT 0x2 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_CFG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_CFG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_SLEEP_ENA_BMSK 0x2 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_SLEEP_ENA_SHFT 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_AXI_CLK_SLEEP_ENA_BMSK 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_AXI_CLK_SLEEP_ENA_SHFT 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_APCS_GPLL_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005d000) +#define HWIO_GCC_APCS_GPLL_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005d000) +#define HWIO_GCC_APCS_GPLL_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005d000) +#define HWIO_GCC_APCS_GPLL_ENA_VOTE_RMSK 0x7f +#define HWIO_GCC_APCS_GPLL_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_APCS_GPLL_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_APCS_GPLL_ENA_VOTE_ADDR, HWIO_GCC_APCS_GPLL_ENA_VOTE_RMSK) +#define HWIO_GCC_APCS_GPLL_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_APCS_GPLL_ENA_VOTE_ADDR, m) +#define HWIO_GCC_APCS_GPLL_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_APCS_GPLL_ENA_VOTE_ADDR,v) +#define HWIO_GCC_APCS_GPLL_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_APCS_GPLL_ENA_VOTE_ADDR,m,v,HWIO_GCC_APCS_GPLL_ENA_VOTE_IN) +#define HWIO_GCC_APCS_GPLL_ENA_VOTE_GPLL6_BMSK 0x40 +#define HWIO_GCC_APCS_GPLL_ENA_VOTE_GPLL6_SHFT 0x6 +#define HWIO_GCC_APCS_GPLL_ENA_VOTE_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_GPLL_ENA_VOTE_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_GPLL_ENA_VOTE_GPLL5_BMSK 0x20 +#define HWIO_GCC_APCS_GPLL_ENA_VOTE_GPLL5_SHFT 0x5 +#define HWIO_GCC_APCS_GPLL_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_GPLL_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_GPLL_ENA_VOTE_GPLL4_BMSK 0x10 +#define HWIO_GCC_APCS_GPLL_ENA_VOTE_GPLL4_SHFT 0x4 +#define HWIO_GCC_APCS_GPLL_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_GPLL_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_GPLL_ENA_VOTE_GPLL3_BMSK 0x8 +#define HWIO_GCC_APCS_GPLL_ENA_VOTE_GPLL3_SHFT 0x3 +#define HWIO_GCC_APCS_GPLL_ENA_VOTE_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_GPLL_ENA_VOTE_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_GPLL_ENA_VOTE_GPLL2_BMSK 0x4 +#define HWIO_GCC_APCS_GPLL_ENA_VOTE_GPLL2_SHFT 0x2 +#define HWIO_GCC_APCS_GPLL_ENA_VOTE_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_GPLL_ENA_VOTE_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_GPLL_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_APCS_GPLL_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_APCS_GPLL_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_GPLL_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_GPLL_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_APCS_GPLL_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_APCS_GPLL_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_GPLL_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_APCS_GPLL_SLEEP_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005d004) +#define HWIO_GCC_APCS_GPLL_SLEEP_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005d004) +#define HWIO_GCC_APCS_GPLL_SLEEP_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005d004) +#define HWIO_GCC_APCS_GPLL_SLEEP_ENA_VOTE_RMSK 0x7f +#define HWIO_GCC_APCS_GPLL_SLEEP_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_APCS_GPLL_SLEEP_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_APCS_GPLL_SLEEP_ENA_VOTE_ADDR, HWIO_GCC_APCS_GPLL_SLEEP_ENA_VOTE_RMSK) +#define HWIO_GCC_APCS_GPLL_SLEEP_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_APCS_GPLL_SLEEP_ENA_VOTE_ADDR, m) +#define HWIO_GCC_APCS_GPLL_SLEEP_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_APCS_GPLL_SLEEP_ENA_VOTE_ADDR,v) +#define HWIO_GCC_APCS_GPLL_SLEEP_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_APCS_GPLL_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_APCS_GPLL_SLEEP_ENA_VOTE_IN) +#define HWIO_GCC_APCS_GPLL_SLEEP_ENA_VOTE_GPLL6_BMSK 0x40 +#define HWIO_GCC_APCS_GPLL_SLEEP_ENA_VOTE_GPLL6_SHFT 0x6 +#define HWIO_GCC_APCS_GPLL_SLEEP_ENA_VOTE_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_GPLL_SLEEP_ENA_VOTE_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_GPLL_SLEEP_ENA_VOTE_GPLL5_BMSK 0x20 +#define HWIO_GCC_APCS_GPLL_SLEEP_ENA_VOTE_GPLL5_SHFT 0x5 +#define HWIO_GCC_APCS_GPLL_SLEEP_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_GPLL_SLEEP_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_GPLL_SLEEP_ENA_VOTE_GPLL4_BMSK 0x10 +#define HWIO_GCC_APCS_GPLL_SLEEP_ENA_VOTE_GPLL4_SHFT 0x4 +#define HWIO_GCC_APCS_GPLL_SLEEP_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_GPLL_SLEEP_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_GPLL_SLEEP_ENA_VOTE_GPLL3_BMSK 0x8 +#define HWIO_GCC_APCS_GPLL_SLEEP_ENA_VOTE_GPLL3_SHFT 0x3 +#define HWIO_GCC_APCS_GPLL_SLEEP_ENA_VOTE_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_GPLL_SLEEP_ENA_VOTE_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_GPLL_SLEEP_ENA_VOTE_GPLL2_BMSK 0x4 +#define HWIO_GCC_APCS_GPLL_SLEEP_ENA_VOTE_GPLL2_SHFT 0x2 +#define HWIO_GCC_APCS_GPLL_SLEEP_ENA_VOTE_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_GPLL_SLEEP_ENA_VOTE_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_GPLL_SLEEP_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_APCS_GPLL_SLEEP_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_APCS_GPLL_SLEEP_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_GPLL_SLEEP_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_GPLL_SLEEP_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_APCS_GPLL_SLEEP_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_APCS_GPLL_SLEEP_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_GPLL_SLEEP_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005d008) +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005d008) +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005d008) +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_RMSK 0x162f5ff +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_ADDR, HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_RMSK) +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_ADDR, m) +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_ADDR,v) +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_IN) +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_IMEM_AXI_CLK_ENA_BMSK 0x1000000 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_IMEM_AXI_CLK_ENA_SHFT 0x18 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_IMEM_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_IMEM_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_CPUSS_GNOC_CLK_ENA_BMSK 0x400000 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_CPUSS_GNOC_CLK_ENA_SHFT 0x16 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_CPUSS_GNOC_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_CPUSS_GNOC_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_BMSK 0x200000 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_SHFT 0x15 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_BMSK 0x20000 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_SHFT 0x11 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_BLSP1_SLEEP_CLK_ENA_BMSK 0x8000 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_BLSP1_SLEEP_CLK_ENA_SHFT 0xf +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_BLSP1_SLEEP_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_BLSP1_SLEEP_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_BLSP1_AHB_CLK_ENA_BMSK 0x4000 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_BLSP1_AHB_CLK_ENA_SHFT 0xe +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_BLSP1_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_BLSP1_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_BMSK 0x2000 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_SHFT 0xd +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_BMSK 0x1000 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_SHFT 0xc +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_BMSK 0x400 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_SHFT 0xa +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_ENA_BMSK 0x100 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_ENA_SHFT 0x8 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_ENA_BMSK 0x80 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_ENA_SHFT 0x7 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_BMSK 0x40 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_SHFT 0x6 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_BMSK 0x20 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_SHFT 0x5 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_BMSK 0x10 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_SHFT 0x4 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_BMSK 0x8 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_SHFT 0x3 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_BMSK 0x4 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_SHFT 0x2 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_BMSK 0x2 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_SHFT 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_BMSK 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_SHFT 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005d00c) +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005d00c) +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005d00c) +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_RMSK 0x162f5ff +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_ADDR, HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_RMSK) +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_ADDR, m) +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_ADDR,v) +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_IN) +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_IMEM_AXI_CLK_SLEEP_ENA_BMSK 0x1000000 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_IMEM_AXI_CLK_SLEEP_ENA_SHFT 0x18 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_IMEM_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_IMEM_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_CPUSS_GNOC_CLK_SLEEP_ENA_BMSK 0x400000 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_CPUSS_GNOC_CLK_SLEEP_ENA_SHFT 0x16 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_CPUSS_GNOC_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_CPUSS_GNOC_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_BMSK 0x200000 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_SHFT 0x15 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK 0x20000 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT 0x11 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_BLSP1_SLEEP_CLK_SLEEP_ENA_BMSK 0x8000 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_BLSP1_SLEEP_CLK_SLEEP_ENA_SHFT 0xf +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_BLSP1_SLEEP_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_BLSP1_SLEEP_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_BLSP1_AHB_CLK_SLEEP_ENA_BMSK 0x4000 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_BLSP1_AHB_CLK_SLEEP_ENA_SHFT 0xe +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_BLSP1_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_BLSP1_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_BMSK 0x2000 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_SHFT 0xd +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_BMSK 0x1000 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_SHFT 0xc +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_BMSK 0x400 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_SHFT 0xa +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_SLEEP_ENA_BMSK 0x100 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_SLEEP_ENA_SHFT 0x8 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_SLEEP_ENA_BMSK 0x80 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_SLEEP_ENA_SHFT 0x7 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_BMSK 0x40 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_SHFT 0x6 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_BMSK 0x20 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_SHFT 0x5 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_BMSK 0x10 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_SHFT 0x4 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_BMSK 0x8 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_SHFT 0x3 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_BMSK 0x4 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_SHFT 0x2 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_BMSK 0x2 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_SHFT 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_BMSK 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_SHFT 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005d010) +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005d010) +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005d010) +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_RMSK 0xff +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_ATTR 0x3 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_IN \ + in_dword_masked(HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_ADDR, HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_RMSK) +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_INM(m) \ + in_dword_masked(HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_ADDR, m) +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_OUT(v) \ + out_dword(HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_ADDR,v) +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_ADDR,m,v,HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_IN) +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_ENA_BMSK 0x80 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_ENA_SHFT 0x7 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLEEP_CLK_ENA_BMSK 0x40 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLEEP_CLK_ENA_SHFT 0x6 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLEEP_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLEEP_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_ENA_BMSK 0x20 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_ENA_SHFT 0x5 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_PIPE_CLK_ENA_BMSK 0x10 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_PIPE_CLK_ENA_SHFT 0x4 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_PIPE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_PIPE_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_AUX_CLK_ENA_BMSK 0x8 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_AUX_CLK_ENA_SHFT 0x3 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_AUX_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_AUX_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_CFG_AHB_CLK_ENA_BMSK 0x4 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_CFG_AHB_CLK_ENA_SHFT 0x2 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_CFG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_CFG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_ENA_BMSK 0x2 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_ENA_SHFT 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_AXI_CLK_ENA_BMSK 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_AXI_CLK_ENA_SHFT 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_AXI_CLK_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005d014) +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005d014) +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005d014) +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_RMSK 0xff +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_ATTR 0x3 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_IN \ + in_dword_masked(HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_ADDR, HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_RMSK) +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_INM(m) \ + in_dword_masked(HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_ADDR, m) +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_OUT(v) \ + out_dword(HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_ADDR,v) +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_ADDR,m,v,HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_IN) +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_SLEEP_ENA_BMSK 0x80 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_SLEEP_ENA_SHFT 0x7 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLEEP_CLK_SLEEP_ENA_BMSK 0x40 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLEEP_CLK_SLEEP_ENA_SHFT 0x6 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLEEP_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLEEP_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK 0x20 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT 0x5 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_PIPE_CLK_SLEEP_ENA_BMSK 0x10 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_PIPE_CLK_SLEEP_ENA_SHFT 0x4 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_PIPE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_PIPE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_AUX_CLK_SLEEP_ENA_BMSK 0x8 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_AUX_CLK_SLEEP_ENA_SHFT 0x3 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_AUX_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_AUX_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_CFG_AHB_CLK_SLEEP_ENA_BMSK 0x4 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_CFG_AHB_CLK_SLEEP_ENA_SHFT 0x2 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_CFG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_CFG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_SLEEP_ENA_BMSK 0x2 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_SLEEP_ENA_SHFT 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_AXI_CLK_SLEEP_ENA_BMSK 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_AXI_CLK_SLEEP_ENA_SHFT 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_APCS_TZ_GPLL_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005e000) +#define HWIO_GCC_APCS_TZ_GPLL_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005e000) +#define HWIO_GCC_APCS_TZ_GPLL_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005e000) +#define HWIO_GCC_APCS_TZ_GPLL_ENA_VOTE_RMSK 0x7f +#define HWIO_GCC_APCS_TZ_GPLL_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_APCS_TZ_GPLL_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_APCS_TZ_GPLL_ENA_VOTE_ADDR, HWIO_GCC_APCS_TZ_GPLL_ENA_VOTE_RMSK) +#define HWIO_GCC_APCS_TZ_GPLL_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_APCS_TZ_GPLL_ENA_VOTE_ADDR, m) +#define HWIO_GCC_APCS_TZ_GPLL_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_APCS_TZ_GPLL_ENA_VOTE_ADDR,v) +#define HWIO_GCC_APCS_TZ_GPLL_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_APCS_TZ_GPLL_ENA_VOTE_ADDR,m,v,HWIO_GCC_APCS_TZ_GPLL_ENA_VOTE_IN) +#define HWIO_GCC_APCS_TZ_GPLL_ENA_VOTE_GPLL6_BMSK 0x40 +#define HWIO_GCC_APCS_TZ_GPLL_ENA_VOTE_GPLL6_SHFT 0x6 +#define HWIO_GCC_APCS_TZ_GPLL_ENA_VOTE_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_GPLL_ENA_VOTE_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_GPLL_ENA_VOTE_GPLL5_BMSK 0x20 +#define HWIO_GCC_APCS_TZ_GPLL_ENA_VOTE_GPLL5_SHFT 0x5 +#define HWIO_GCC_APCS_TZ_GPLL_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_GPLL_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_GPLL_ENA_VOTE_GPLL4_BMSK 0x10 +#define HWIO_GCC_APCS_TZ_GPLL_ENA_VOTE_GPLL4_SHFT 0x4 +#define HWIO_GCC_APCS_TZ_GPLL_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_GPLL_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_GPLL_ENA_VOTE_GPLL3_BMSK 0x8 +#define HWIO_GCC_APCS_TZ_GPLL_ENA_VOTE_GPLL3_SHFT 0x3 +#define HWIO_GCC_APCS_TZ_GPLL_ENA_VOTE_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_GPLL_ENA_VOTE_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_GPLL_ENA_VOTE_GPLL2_BMSK 0x4 +#define HWIO_GCC_APCS_TZ_GPLL_ENA_VOTE_GPLL2_SHFT 0x2 +#define HWIO_GCC_APCS_TZ_GPLL_ENA_VOTE_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_GPLL_ENA_VOTE_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_GPLL_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_APCS_TZ_GPLL_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_APCS_TZ_GPLL_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_GPLL_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_GPLL_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_APCS_TZ_GPLL_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_APCS_TZ_GPLL_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_GPLL_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_APCS_TZ_GPLL_SLEEP_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005e004) +#define HWIO_GCC_APCS_TZ_GPLL_SLEEP_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005e004) +#define HWIO_GCC_APCS_TZ_GPLL_SLEEP_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005e004) +#define HWIO_GCC_APCS_TZ_GPLL_SLEEP_ENA_VOTE_RMSK 0x7f +#define HWIO_GCC_APCS_TZ_GPLL_SLEEP_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_APCS_TZ_GPLL_SLEEP_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_APCS_TZ_GPLL_SLEEP_ENA_VOTE_ADDR, HWIO_GCC_APCS_TZ_GPLL_SLEEP_ENA_VOTE_RMSK) +#define HWIO_GCC_APCS_TZ_GPLL_SLEEP_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_APCS_TZ_GPLL_SLEEP_ENA_VOTE_ADDR, m) +#define HWIO_GCC_APCS_TZ_GPLL_SLEEP_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_APCS_TZ_GPLL_SLEEP_ENA_VOTE_ADDR,v) +#define HWIO_GCC_APCS_TZ_GPLL_SLEEP_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_APCS_TZ_GPLL_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_APCS_TZ_GPLL_SLEEP_ENA_VOTE_IN) +#define HWIO_GCC_APCS_TZ_GPLL_SLEEP_ENA_VOTE_GPLL6_BMSK 0x40 +#define HWIO_GCC_APCS_TZ_GPLL_SLEEP_ENA_VOTE_GPLL6_SHFT 0x6 +#define HWIO_GCC_APCS_TZ_GPLL_SLEEP_ENA_VOTE_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_GPLL_SLEEP_ENA_VOTE_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_GPLL_SLEEP_ENA_VOTE_GPLL5_BMSK 0x20 +#define HWIO_GCC_APCS_TZ_GPLL_SLEEP_ENA_VOTE_GPLL5_SHFT 0x5 +#define HWIO_GCC_APCS_TZ_GPLL_SLEEP_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_GPLL_SLEEP_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_GPLL_SLEEP_ENA_VOTE_GPLL4_BMSK 0x10 +#define HWIO_GCC_APCS_TZ_GPLL_SLEEP_ENA_VOTE_GPLL4_SHFT 0x4 +#define HWIO_GCC_APCS_TZ_GPLL_SLEEP_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_GPLL_SLEEP_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_GPLL_SLEEP_ENA_VOTE_GPLL3_BMSK 0x8 +#define HWIO_GCC_APCS_TZ_GPLL_SLEEP_ENA_VOTE_GPLL3_SHFT 0x3 +#define HWIO_GCC_APCS_TZ_GPLL_SLEEP_ENA_VOTE_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_GPLL_SLEEP_ENA_VOTE_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_GPLL_SLEEP_ENA_VOTE_GPLL2_BMSK 0x4 +#define HWIO_GCC_APCS_TZ_GPLL_SLEEP_ENA_VOTE_GPLL2_SHFT 0x2 +#define HWIO_GCC_APCS_TZ_GPLL_SLEEP_ENA_VOTE_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_GPLL_SLEEP_ENA_VOTE_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_GPLL_SLEEP_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_APCS_TZ_GPLL_SLEEP_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_APCS_TZ_GPLL_SLEEP_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_GPLL_SLEEP_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_GPLL_SLEEP_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_APCS_TZ_GPLL_SLEEP_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_APCS_TZ_GPLL_SLEEP_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_GPLL_SLEEP_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005e008) +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005e008) +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005e008) +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_RMSK 0x162f5ff +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_ADDR, HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_RMSK) +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_ADDR, m) +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_ADDR,v) +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_IN) +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_IMEM_AXI_CLK_ENA_BMSK 0x1000000 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_IMEM_AXI_CLK_ENA_SHFT 0x18 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_IMEM_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_IMEM_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_CPUSS_GNOC_CLK_ENA_BMSK 0x400000 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_CPUSS_GNOC_CLK_ENA_SHFT 0x16 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_CPUSS_GNOC_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_CPUSS_GNOC_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_BMSK 0x200000 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_SHFT 0x15 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_BMSK 0x20000 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_SHFT 0x11 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_BLSP1_SLEEP_CLK_ENA_BMSK 0x8000 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_BLSP1_SLEEP_CLK_ENA_SHFT 0xf +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_BLSP1_SLEEP_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_BLSP1_SLEEP_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_BLSP1_AHB_CLK_ENA_BMSK 0x4000 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_BLSP1_AHB_CLK_ENA_SHFT 0xe +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_BLSP1_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_BLSP1_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_BMSK 0x2000 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_SHFT 0xd +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_BMSK 0x1000 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_SHFT 0xc +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_BMSK 0x400 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_SHFT 0xa +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_ENA_BMSK 0x100 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_ENA_SHFT 0x8 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_ENA_BMSK 0x80 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_ENA_SHFT 0x7 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_BMSK 0x40 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_SHFT 0x6 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_BMSK 0x20 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_SHFT 0x5 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_BMSK 0x10 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_SHFT 0x4 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_BMSK 0x8 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_SHFT 0x3 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_BMSK 0x4 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_SHFT 0x2 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_BMSK 0x2 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_SHFT 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_BMSK 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_SHFT 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005e00c) +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005e00c) +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005e00c) +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_RMSK 0x162f5ff +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_ADDR, HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_RMSK) +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_ADDR, m) +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_ADDR,v) +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_IN) +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_IMEM_AXI_CLK_SLEEP_ENA_BMSK 0x1000000 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_IMEM_AXI_CLK_SLEEP_ENA_SHFT 0x18 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_IMEM_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_IMEM_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_CPUSS_GNOC_CLK_SLEEP_ENA_BMSK 0x400000 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_CPUSS_GNOC_CLK_SLEEP_ENA_SHFT 0x16 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_CPUSS_GNOC_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_CPUSS_GNOC_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_BMSK 0x200000 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_SHFT 0x15 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK 0x20000 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT 0x11 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_BLSP1_SLEEP_CLK_SLEEP_ENA_BMSK 0x8000 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_BLSP1_SLEEP_CLK_SLEEP_ENA_SHFT 0xf +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_BLSP1_SLEEP_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_BLSP1_SLEEP_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_BLSP1_AHB_CLK_SLEEP_ENA_BMSK 0x4000 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_BLSP1_AHB_CLK_SLEEP_ENA_SHFT 0xe +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_BLSP1_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_BLSP1_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_BMSK 0x2000 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_SHFT 0xd +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_BMSK 0x1000 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_SHFT 0xc +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_BMSK 0x400 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_SHFT 0xa +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_SLEEP_ENA_BMSK 0x100 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_SLEEP_ENA_SHFT 0x8 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_SLEEP_ENA_BMSK 0x80 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_SLEEP_ENA_SHFT 0x7 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_BMSK 0x40 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_SHFT 0x6 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_BMSK 0x20 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_SHFT 0x5 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_BMSK 0x10 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_SHFT 0x4 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_BMSK 0x8 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_SHFT 0x3 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_BMSK 0x4 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_SHFT 0x2 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_BMSK 0x2 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_SHFT 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_BMSK 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_SHFT 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005e010) +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005e010) +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005e010) +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_RMSK 0xff +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_ATTR 0x3 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_IN \ + in_dword_masked(HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_ADDR, HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_RMSK) +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_INM(m) \ + in_dword_masked(HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_ADDR, m) +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_OUT(v) \ + out_dword(HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_ADDR,v) +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_ADDR,m,v,HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_IN) +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_ENA_BMSK 0x80 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_ENA_SHFT 0x7 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLEEP_CLK_ENA_BMSK 0x40 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLEEP_CLK_ENA_SHFT 0x6 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLEEP_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLEEP_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_ENA_BMSK 0x20 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_ENA_SHFT 0x5 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_PIPE_CLK_ENA_BMSK 0x10 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_PIPE_CLK_ENA_SHFT 0x4 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_PIPE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_PIPE_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_AUX_CLK_ENA_BMSK 0x8 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_AUX_CLK_ENA_SHFT 0x3 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_AUX_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_AUX_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_CFG_AHB_CLK_ENA_BMSK 0x4 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_CFG_AHB_CLK_ENA_SHFT 0x2 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_CFG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_CFG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_ENA_BMSK 0x2 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_ENA_SHFT 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_AXI_CLK_ENA_BMSK 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_AXI_CLK_ENA_SHFT 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_AXI_CLK_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005e014) +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005e014) +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005e014) +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_RMSK 0xff +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_ATTR 0x3 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_IN \ + in_dword_masked(HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_ADDR, HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_RMSK) +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_INM(m) \ + in_dword_masked(HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_ADDR, m) +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_OUT(v) \ + out_dword(HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_ADDR,v) +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_ADDR,m,v,HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_IN) +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_SLEEP_ENA_BMSK 0x80 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_SLEEP_ENA_SHFT 0x7 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLEEP_CLK_SLEEP_ENA_BMSK 0x40 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLEEP_CLK_SLEEP_ENA_SHFT 0x6 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLEEP_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLEEP_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK 0x20 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT 0x5 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_PIPE_CLK_SLEEP_ENA_BMSK 0x10 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_PIPE_CLK_SLEEP_ENA_SHFT 0x4 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_PIPE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_PIPE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_AUX_CLK_SLEEP_ENA_BMSK 0x8 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_AUX_CLK_SLEEP_ENA_SHFT 0x3 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_AUX_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_AUX_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_CFG_AHB_CLK_SLEEP_ENA_BMSK 0x4 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_CFG_AHB_CLK_SLEEP_ENA_SHFT 0x2 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_CFG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_CFG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_SLEEP_ENA_BMSK 0x2 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_SLEEP_ENA_SHFT 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_AXI_CLK_SLEEP_ENA_BMSK 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_AXI_CLK_SLEEP_ENA_SHFT 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HYP_GPLL_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005f000) +#define HWIO_GCC_HYP_GPLL_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005f000) +#define HWIO_GCC_HYP_GPLL_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005f000) +#define HWIO_GCC_HYP_GPLL_ENA_VOTE_RMSK 0x7f +#define HWIO_GCC_HYP_GPLL_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_HYP_GPLL_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_HYP_GPLL_ENA_VOTE_ADDR, HWIO_GCC_HYP_GPLL_ENA_VOTE_RMSK) +#define HWIO_GCC_HYP_GPLL_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_HYP_GPLL_ENA_VOTE_ADDR, m) +#define HWIO_GCC_HYP_GPLL_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_HYP_GPLL_ENA_VOTE_ADDR,v) +#define HWIO_GCC_HYP_GPLL_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HYP_GPLL_ENA_VOTE_ADDR,m,v,HWIO_GCC_HYP_GPLL_ENA_VOTE_IN) +#define HWIO_GCC_HYP_GPLL_ENA_VOTE_GPLL6_BMSK 0x40 +#define HWIO_GCC_HYP_GPLL_ENA_VOTE_GPLL6_SHFT 0x6 +#define HWIO_GCC_HYP_GPLL_ENA_VOTE_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_GPLL_ENA_VOTE_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_GPLL_ENA_VOTE_GPLL5_BMSK 0x20 +#define HWIO_GCC_HYP_GPLL_ENA_VOTE_GPLL5_SHFT 0x5 +#define HWIO_GCC_HYP_GPLL_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_GPLL_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_GPLL_ENA_VOTE_GPLL4_BMSK 0x10 +#define HWIO_GCC_HYP_GPLL_ENA_VOTE_GPLL4_SHFT 0x4 +#define HWIO_GCC_HYP_GPLL_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_GPLL_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_GPLL_ENA_VOTE_GPLL3_BMSK 0x8 +#define HWIO_GCC_HYP_GPLL_ENA_VOTE_GPLL3_SHFT 0x3 +#define HWIO_GCC_HYP_GPLL_ENA_VOTE_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_GPLL_ENA_VOTE_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_GPLL_ENA_VOTE_GPLL2_BMSK 0x4 +#define HWIO_GCC_HYP_GPLL_ENA_VOTE_GPLL2_SHFT 0x2 +#define HWIO_GCC_HYP_GPLL_ENA_VOTE_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_GPLL_ENA_VOTE_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_GPLL_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_HYP_GPLL_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_HYP_GPLL_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_GPLL_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_GPLL_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_HYP_GPLL_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_HYP_GPLL_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_GPLL_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HYP_GPLL_SLEEP_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005f004) +#define HWIO_GCC_HYP_GPLL_SLEEP_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005f004) +#define HWIO_GCC_HYP_GPLL_SLEEP_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005f004) +#define HWIO_GCC_HYP_GPLL_SLEEP_ENA_VOTE_RMSK 0x7f +#define HWIO_GCC_HYP_GPLL_SLEEP_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_HYP_GPLL_SLEEP_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_HYP_GPLL_SLEEP_ENA_VOTE_ADDR, HWIO_GCC_HYP_GPLL_SLEEP_ENA_VOTE_RMSK) +#define HWIO_GCC_HYP_GPLL_SLEEP_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_HYP_GPLL_SLEEP_ENA_VOTE_ADDR, m) +#define HWIO_GCC_HYP_GPLL_SLEEP_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_HYP_GPLL_SLEEP_ENA_VOTE_ADDR,v) +#define HWIO_GCC_HYP_GPLL_SLEEP_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HYP_GPLL_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_HYP_GPLL_SLEEP_ENA_VOTE_IN) +#define HWIO_GCC_HYP_GPLL_SLEEP_ENA_VOTE_GPLL6_BMSK 0x40 +#define HWIO_GCC_HYP_GPLL_SLEEP_ENA_VOTE_GPLL6_SHFT 0x6 +#define HWIO_GCC_HYP_GPLL_SLEEP_ENA_VOTE_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_GPLL_SLEEP_ENA_VOTE_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_GPLL_SLEEP_ENA_VOTE_GPLL5_BMSK 0x20 +#define HWIO_GCC_HYP_GPLL_SLEEP_ENA_VOTE_GPLL5_SHFT 0x5 +#define HWIO_GCC_HYP_GPLL_SLEEP_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_GPLL_SLEEP_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_GPLL_SLEEP_ENA_VOTE_GPLL4_BMSK 0x10 +#define HWIO_GCC_HYP_GPLL_SLEEP_ENA_VOTE_GPLL4_SHFT 0x4 +#define HWIO_GCC_HYP_GPLL_SLEEP_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_GPLL_SLEEP_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_GPLL_SLEEP_ENA_VOTE_GPLL3_BMSK 0x8 +#define HWIO_GCC_HYP_GPLL_SLEEP_ENA_VOTE_GPLL3_SHFT 0x3 +#define HWIO_GCC_HYP_GPLL_SLEEP_ENA_VOTE_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_GPLL_SLEEP_ENA_VOTE_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_GPLL_SLEEP_ENA_VOTE_GPLL2_BMSK 0x4 +#define HWIO_GCC_HYP_GPLL_SLEEP_ENA_VOTE_GPLL2_SHFT 0x2 +#define HWIO_GCC_HYP_GPLL_SLEEP_ENA_VOTE_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_GPLL_SLEEP_ENA_VOTE_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_GPLL_SLEEP_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_HYP_GPLL_SLEEP_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_HYP_GPLL_SLEEP_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_GPLL_SLEEP_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_GPLL_SLEEP_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_HYP_GPLL_SLEEP_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_HYP_GPLL_SLEEP_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_GPLL_SLEEP_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005f008) +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005f008) +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005f008) +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_RMSK 0x162f5ff +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_ADDR, HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_RMSK) +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_ADDR, m) +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_ADDR,v) +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_IN) +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_IMEM_AXI_CLK_ENA_BMSK 0x1000000 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_IMEM_AXI_CLK_ENA_SHFT 0x18 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_IMEM_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_IMEM_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_CPUSS_GNOC_CLK_ENA_BMSK 0x400000 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_CPUSS_GNOC_CLK_ENA_SHFT 0x16 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_CPUSS_GNOC_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_CPUSS_GNOC_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_BMSK 0x200000 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_SHFT 0x15 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_BMSK 0x20000 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_SHFT 0x11 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_BLSP1_SLEEP_CLK_ENA_BMSK 0x8000 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_BLSP1_SLEEP_CLK_ENA_SHFT 0xf +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_BLSP1_SLEEP_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_BLSP1_SLEEP_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_BLSP1_AHB_CLK_ENA_BMSK 0x4000 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_BLSP1_AHB_CLK_ENA_SHFT 0xe +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_BLSP1_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_BLSP1_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_BMSK 0x2000 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_SHFT 0xd +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_BMSK 0x1000 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_SHFT 0xc +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_BMSK 0x400 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_SHFT 0xa +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_ENA_BMSK 0x100 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_ENA_SHFT 0x8 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_ENA_BMSK 0x80 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_ENA_SHFT 0x7 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_BMSK 0x40 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_SHFT 0x6 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_BMSK 0x20 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_SHFT 0x5 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_BMSK 0x10 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_SHFT 0x4 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_BMSK 0x8 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_SHFT 0x3 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_BMSK 0x4 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_SHFT 0x2 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_BMSK 0x2 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_SHFT 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_BMSK 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_SHFT 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005f00c) +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005f00c) +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005f00c) +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_RMSK 0x162f5ff +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_ADDR, HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_RMSK) +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_ADDR, m) +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_ADDR,v) +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_IN) +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_IMEM_AXI_CLK_SLEEP_ENA_BMSK 0x1000000 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_IMEM_AXI_CLK_SLEEP_ENA_SHFT 0x18 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_IMEM_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_IMEM_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_CPUSS_GNOC_CLK_SLEEP_ENA_BMSK 0x400000 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_CPUSS_GNOC_CLK_SLEEP_ENA_SHFT 0x16 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_CPUSS_GNOC_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_CPUSS_GNOC_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_BMSK 0x200000 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_SHFT 0x15 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK 0x20000 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT 0x11 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_BLSP1_SLEEP_CLK_SLEEP_ENA_BMSK 0x8000 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_BLSP1_SLEEP_CLK_SLEEP_ENA_SHFT 0xf +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_BLSP1_SLEEP_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_BLSP1_SLEEP_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_BLSP1_AHB_CLK_SLEEP_ENA_BMSK 0x4000 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_BLSP1_AHB_CLK_SLEEP_ENA_SHFT 0xe +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_BLSP1_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_BLSP1_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_BMSK 0x2000 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_SHFT 0xd +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_BMSK 0x1000 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_SHFT 0xc +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_BMSK 0x400 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_SHFT 0xa +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_SLEEP_ENA_BMSK 0x100 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_SLEEP_ENA_SHFT 0x8 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_SLEEP_ENA_BMSK 0x80 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_SLEEP_ENA_SHFT 0x7 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_BMSK 0x40 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_SHFT 0x6 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_BMSK 0x20 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_SHFT 0x5 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_BMSK 0x10 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_SHFT 0x4 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_BMSK 0x8 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_SHFT 0x3 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_BMSK 0x4 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_SHFT 0x2 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_BMSK 0x2 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_SHFT 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_BMSK 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_SHFT 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005f010) +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005f010) +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005f010) +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_RMSK 0xff +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_ATTR 0x3 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_IN \ + in_dword_masked(HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_ADDR, HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_RMSK) +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_INM(m) \ + in_dword_masked(HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_ADDR, m) +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_OUT(v) \ + out_dword(HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_ADDR,v) +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_ADDR,m,v,HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_IN) +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_ENA_BMSK 0x80 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_ENA_SHFT 0x7 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLEEP_CLK_ENA_BMSK 0x40 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLEEP_CLK_ENA_SHFT 0x6 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLEEP_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLEEP_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_ENA_BMSK 0x20 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_ENA_SHFT 0x5 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_PIPE_CLK_ENA_BMSK 0x10 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_PIPE_CLK_ENA_SHFT 0x4 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_PIPE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_PIPE_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_AUX_CLK_ENA_BMSK 0x8 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_AUX_CLK_ENA_SHFT 0x3 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_AUX_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_AUX_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_CFG_AHB_CLK_ENA_BMSK 0x4 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_CFG_AHB_CLK_ENA_SHFT 0x2 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_CFG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_CFG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_ENA_BMSK 0x2 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_ENA_SHFT 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_AXI_CLK_ENA_BMSK 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_AXI_CLK_ENA_SHFT 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_AXI_CLK_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005f014) +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005f014) +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005f014) +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_RMSK 0xff +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_ATTR 0x3 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_IN \ + in_dword_masked(HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_ADDR, HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_RMSK) +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_INM(m) \ + in_dword_masked(HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_ADDR, m) +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_OUT(v) \ + out_dword(HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_ADDR,v) +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_ADDR,m,v,HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_IN) +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_SLEEP_ENA_BMSK 0x80 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_SLEEP_ENA_SHFT 0x7 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLEEP_CLK_SLEEP_ENA_BMSK 0x40 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLEEP_CLK_SLEEP_ENA_SHFT 0x6 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLEEP_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLEEP_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK 0x20 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT 0x5 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_PIPE_CLK_SLEEP_ENA_BMSK 0x10 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_PIPE_CLK_SLEEP_ENA_SHFT 0x4 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_PIPE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_PIPE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_AUX_CLK_SLEEP_ENA_BMSK 0x8 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_AUX_CLK_SLEEP_ENA_SHFT 0x3 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_AUX_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_AUX_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_CFG_AHB_CLK_SLEEP_ENA_BMSK 0x4 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_CFG_AHB_CLK_SLEEP_ENA_SHFT 0x2 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_CFG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_CFG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_SLEEP_ENA_BMSK 0x2 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_SLEEP_ENA_SHFT 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_AXI_CLK_SLEEP_ENA_BMSK 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_AXI_CLK_SLEEP_ENA_SHFT 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPARE_GPLL_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00060000) +#define HWIO_GCC_SPARE_GPLL_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00060000) +#define HWIO_GCC_SPARE_GPLL_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00060000) +#define HWIO_GCC_SPARE_GPLL_ENA_VOTE_RMSK 0x7f +#define HWIO_GCC_SPARE_GPLL_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_SPARE_GPLL_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_SPARE_GPLL_ENA_VOTE_ADDR, HWIO_GCC_SPARE_GPLL_ENA_VOTE_RMSK) +#define HWIO_GCC_SPARE_GPLL_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_SPARE_GPLL_ENA_VOTE_ADDR, m) +#define HWIO_GCC_SPARE_GPLL_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_SPARE_GPLL_ENA_VOTE_ADDR,v) +#define HWIO_GCC_SPARE_GPLL_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPARE_GPLL_ENA_VOTE_ADDR,m,v,HWIO_GCC_SPARE_GPLL_ENA_VOTE_IN) +#define HWIO_GCC_SPARE_GPLL_ENA_VOTE_GPLL6_BMSK 0x40 +#define HWIO_GCC_SPARE_GPLL_ENA_VOTE_GPLL6_SHFT 0x6 +#define HWIO_GCC_SPARE_GPLL_ENA_VOTE_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_GPLL_ENA_VOTE_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_GPLL_ENA_VOTE_GPLL5_BMSK 0x20 +#define HWIO_GCC_SPARE_GPLL_ENA_VOTE_GPLL5_SHFT 0x5 +#define HWIO_GCC_SPARE_GPLL_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_GPLL_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_GPLL_ENA_VOTE_GPLL4_BMSK 0x10 +#define HWIO_GCC_SPARE_GPLL_ENA_VOTE_GPLL4_SHFT 0x4 +#define HWIO_GCC_SPARE_GPLL_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_GPLL_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_GPLL_ENA_VOTE_GPLL3_BMSK 0x8 +#define HWIO_GCC_SPARE_GPLL_ENA_VOTE_GPLL3_SHFT 0x3 +#define HWIO_GCC_SPARE_GPLL_ENA_VOTE_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_GPLL_ENA_VOTE_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_GPLL_ENA_VOTE_GPLL2_BMSK 0x4 +#define HWIO_GCC_SPARE_GPLL_ENA_VOTE_GPLL2_SHFT 0x2 +#define HWIO_GCC_SPARE_GPLL_ENA_VOTE_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_GPLL_ENA_VOTE_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_GPLL_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_SPARE_GPLL_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_SPARE_GPLL_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_GPLL_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_GPLL_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_SPARE_GPLL_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_SPARE_GPLL_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_GPLL_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPARE_GPLL_SLEEP_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00060004) +#define HWIO_GCC_SPARE_GPLL_SLEEP_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00060004) +#define HWIO_GCC_SPARE_GPLL_SLEEP_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00060004) +#define HWIO_GCC_SPARE_GPLL_SLEEP_ENA_VOTE_RMSK 0x7f +#define HWIO_GCC_SPARE_GPLL_SLEEP_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_SPARE_GPLL_SLEEP_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_SPARE_GPLL_SLEEP_ENA_VOTE_ADDR, HWIO_GCC_SPARE_GPLL_SLEEP_ENA_VOTE_RMSK) +#define HWIO_GCC_SPARE_GPLL_SLEEP_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_SPARE_GPLL_SLEEP_ENA_VOTE_ADDR, m) +#define HWIO_GCC_SPARE_GPLL_SLEEP_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_SPARE_GPLL_SLEEP_ENA_VOTE_ADDR,v) +#define HWIO_GCC_SPARE_GPLL_SLEEP_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPARE_GPLL_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_SPARE_GPLL_SLEEP_ENA_VOTE_IN) +#define HWIO_GCC_SPARE_GPLL_SLEEP_ENA_VOTE_GPLL6_BMSK 0x40 +#define HWIO_GCC_SPARE_GPLL_SLEEP_ENA_VOTE_GPLL6_SHFT 0x6 +#define HWIO_GCC_SPARE_GPLL_SLEEP_ENA_VOTE_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_GPLL_SLEEP_ENA_VOTE_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_GPLL_SLEEP_ENA_VOTE_GPLL5_BMSK 0x20 +#define HWIO_GCC_SPARE_GPLL_SLEEP_ENA_VOTE_GPLL5_SHFT 0x5 +#define HWIO_GCC_SPARE_GPLL_SLEEP_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_GPLL_SLEEP_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_GPLL_SLEEP_ENA_VOTE_GPLL4_BMSK 0x10 +#define HWIO_GCC_SPARE_GPLL_SLEEP_ENA_VOTE_GPLL4_SHFT 0x4 +#define HWIO_GCC_SPARE_GPLL_SLEEP_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_GPLL_SLEEP_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_GPLL_SLEEP_ENA_VOTE_GPLL3_BMSK 0x8 +#define HWIO_GCC_SPARE_GPLL_SLEEP_ENA_VOTE_GPLL3_SHFT 0x3 +#define HWIO_GCC_SPARE_GPLL_SLEEP_ENA_VOTE_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_GPLL_SLEEP_ENA_VOTE_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_GPLL_SLEEP_ENA_VOTE_GPLL2_BMSK 0x4 +#define HWIO_GCC_SPARE_GPLL_SLEEP_ENA_VOTE_GPLL2_SHFT 0x2 +#define HWIO_GCC_SPARE_GPLL_SLEEP_ENA_VOTE_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_GPLL_SLEEP_ENA_VOTE_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_GPLL_SLEEP_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_SPARE_GPLL_SLEEP_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_SPARE_GPLL_SLEEP_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_GPLL_SLEEP_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_GPLL_SLEEP_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_SPARE_GPLL_SLEEP_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_SPARE_GPLL_SLEEP_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_GPLL_SLEEP_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00060008) +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00060008) +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00060008) +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_RMSK 0x162f5ff +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_ADDR, HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_RMSK) +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_ADDR, m) +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_ADDR,v) +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_IN) +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_IMEM_AXI_CLK_ENA_BMSK 0x1000000 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_IMEM_AXI_CLK_ENA_SHFT 0x18 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_IMEM_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_IMEM_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_CPUSS_GNOC_CLK_ENA_BMSK 0x400000 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_CPUSS_GNOC_CLK_ENA_SHFT 0x16 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_CPUSS_GNOC_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_CPUSS_GNOC_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_BMSK 0x200000 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_SHFT 0x15 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_BMSK 0x20000 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_SHFT 0x11 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_BLSP1_SLEEP_CLK_ENA_BMSK 0x8000 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_BLSP1_SLEEP_CLK_ENA_SHFT 0xf +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_BLSP1_SLEEP_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_BLSP1_SLEEP_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_BLSP1_AHB_CLK_ENA_BMSK 0x4000 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_BLSP1_AHB_CLK_ENA_SHFT 0xe +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_BLSP1_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_BLSP1_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_BMSK 0x2000 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_SHFT 0xd +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_BMSK 0x1000 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_SHFT 0xc +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_BMSK 0x400 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_SHFT 0xa +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_ENA_BMSK 0x100 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_ENA_SHFT 0x8 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_ENA_BMSK 0x80 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_ENA_SHFT 0x7 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_BMSK 0x40 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_SHFT 0x6 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_BMSK 0x20 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_SHFT 0x5 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_BMSK 0x10 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_SHFT 0x4 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_BMSK 0x8 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_SHFT 0x3 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_BMSK 0x4 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_SHFT 0x2 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_BMSK 0x2 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_SHFT 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_BMSK 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_SHFT 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006000c) +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006000c) +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006000c) +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_RMSK 0x162f5ff +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_ADDR, HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_RMSK) +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_ADDR, m) +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_ADDR,v) +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_IN) +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_IMEM_AXI_CLK_SLEEP_ENA_BMSK 0x1000000 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_IMEM_AXI_CLK_SLEEP_ENA_SHFT 0x18 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_IMEM_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_IMEM_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_CPUSS_GNOC_CLK_SLEEP_ENA_BMSK 0x400000 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_CPUSS_GNOC_CLK_SLEEP_ENA_SHFT 0x16 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_CPUSS_GNOC_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_CPUSS_GNOC_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_BMSK 0x200000 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_SHFT 0x15 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK 0x20000 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT 0x11 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_BLSP1_SLEEP_CLK_SLEEP_ENA_BMSK 0x8000 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_BLSP1_SLEEP_CLK_SLEEP_ENA_SHFT 0xf +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_BLSP1_SLEEP_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_BLSP1_SLEEP_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_BLSP1_AHB_CLK_SLEEP_ENA_BMSK 0x4000 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_BLSP1_AHB_CLK_SLEEP_ENA_SHFT 0xe +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_BLSP1_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_BLSP1_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_BMSK 0x2000 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_SHFT 0xd +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_BMSK 0x1000 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_SHFT 0xc +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_BMSK 0x400 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_SHFT 0xa +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_SLEEP_ENA_BMSK 0x100 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_SLEEP_ENA_SHFT 0x8 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_SLEEP_ENA_BMSK 0x80 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_SLEEP_ENA_SHFT 0x7 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_BMSK 0x40 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_SHFT 0x6 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_BMSK 0x20 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_SHFT 0x5 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_BMSK 0x10 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_SHFT 0x4 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_BMSK 0x8 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_SHFT 0x3 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_BMSK 0x4 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_SHFT 0x2 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_BMSK 0x2 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_SHFT 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_BMSK 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_SHFT 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00060010) +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00060010) +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00060010) +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_RMSK 0xff +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_ATTR 0x3 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_IN \ + in_dword_masked(HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_ADDR, HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_RMSK) +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_INM(m) \ + in_dword_masked(HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_ADDR, m) +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_OUT(v) \ + out_dword(HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_ADDR,v) +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_ADDR,m,v,HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_IN) +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_ENA_BMSK 0x80 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_ENA_SHFT 0x7 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLEEP_CLK_ENA_BMSK 0x40 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLEEP_CLK_ENA_SHFT 0x6 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLEEP_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLEEP_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_ENA_BMSK 0x20 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_ENA_SHFT 0x5 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_PIPE_CLK_ENA_BMSK 0x10 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_PIPE_CLK_ENA_SHFT 0x4 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_PIPE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_PIPE_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_AUX_CLK_ENA_BMSK 0x8 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_AUX_CLK_ENA_SHFT 0x3 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_AUX_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_AUX_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_CFG_AHB_CLK_ENA_BMSK 0x4 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_CFG_AHB_CLK_ENA_SHFT 0x2 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_CFG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_CFG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_ENA_BMSK 0x2 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_ENA_SHFT 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_AXI_CLK_ENA_BMSK 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_AXI_CLK_ENA_SHFT 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_AXI_CLK_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00060014) +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00060014) +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00060014) +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_RMSK 0xff +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_ATTR 0x3 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_IN \ + in_dword_masked(HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_ADDR, HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_RMSK) +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_INM(m) \ + in_dword_masked(HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_ADDR, m) +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_OUT(v) \ + out_dword(HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_ADDR,v) +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_ADDR,m,v,HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_IN) +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_SLEEP_ENA_BMSK 0x80 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_SLEEP_ENA_SHFT 0x7 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLEEP_CLK_SLEEP_ENA_BMSK 0x40 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLEEP_CLK_SLEEP_ENA_SHFT 0x6 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLEEP_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLEEP_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK 0x20 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT 0x5 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_PIPE_CLK_SLEEP_ENA_BMSK 0x10 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_PIPE_CLK_SLEEP_ENA_SHFT 0x4 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_PIPE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_PIPE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_AUX_CLK_SLEEP_ENA_BMSK 0x8 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_AUX_CLK_SLEEP_ENA_SHFT 0x3 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_AUX_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_AUX_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_CFG_AHB_CLK_SLEEP_ENA_BMSK 0x4 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_CFG_AHB_CLK_SLEEP_ENA_SHFT 0x2 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_CFG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_CFG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_SLEEP_ENA_BMSK 0x2 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_SLEEP_ENA_SHFT 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_AXI_CLK_SLEEP_ENA_BMSK 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_AXI_CLK_SLEEP_ENA_SHFT 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPARE1_GPLL_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00061000) +#define HWIO_GCC_SPARE1_GPLL_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00061000) +#define HWIO_GCC_SPARE1_GPLL_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00061000) +#define HWIO_GCC_SPARE1_GPLL_ENA_VOTE_RMSK 0x7f +#define HWIO_GCC_SPARE1_GPLL_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_SPARE1_GPLL_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_SPARE1_GPLL_ENA_VOTE_ADDR, HWIO_GCC_SPARE1_GPLL_ENA_VOTE_RMSK) +#define HWIO_GCC_SPARE1_GPLL_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_SPARE1_GPLL_ENA_VOTE_ADDR, m) +#define HWIO_GCC_SPARE1_GPLL_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_SPARE1_GPLL_ENA_VOTE_ADDR,v) +#define HWIO_GCC_SPARE1_GPLL_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPARE1_GPLL_ENA_VOTE_ADDR,m,v,HWIO_GCC_SPARE1_GPLL_ENA_VOTE_IN) +#define HWIO_GCC_SPARE1_GPLL_ENA_VOTE_GPLL6_BMSK 0x40 +#define HWIO_GCC_SPARE1_GPLL_ENA_VOTE_GPLL6_SHFT 0x6 +#define HWIO_GCC_SPARE1_GPLL_ENA_VOTE_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_GPLL_ENA_VOTE_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_GPLL_ENA_VOTE_GPLL5_BMSK 0x20 +#define HWIO_GCC_SPARE1_GPLL_ENA_VOTE_GPLL5_SHFT 0x5 +#define HWIO_GCC_SPARE1_GPLL_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_GPLL_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_GPLL_ENA_VOTE_GPLL4_BMSK 0x10 +#define HWIO_GCC_SPARE1_GPLL_ENA_VOTE_GPLL4_SHFT 0x4 +#define HWIO_GCC_SPARE1_GPLL_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_GPLL_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_GPLL_ENA_VOTE_GPLL3_BMSK 0x8 +#define HWIO_GCC_SPARE1_GPLL_ENA_VOTE_GPLL3_SHFT 0x3 +#define HWIO_GCC_SPARE1_GPLL_ENA_VOTE_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_GPLL_ENA_VOTE_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_GPLL_ENA_VOTE_GPLL2_BMSK 0x4 +#define HWIO_GCC_SPARE1_GPLL_ENA_VOTE_GPLL2_SHFT 0x2 +#define HWIO_GCC_SPARE1_GPLL_ENA_VOTE_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_GPLL_ENA_VOTE_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_GPLL_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_SPARE1_GPLL_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_SPARE1_GPLL_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_GPLL_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_GPLL_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_SPARE1_GPLL_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_SPARE1_GPLL_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_GPLL_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPARE1_GPLL_SLEEP_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00061004) +#define HWIO_GCC_SPARE1_GPLL_SLEEP_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00061004) +#define HWIO_GCC_SPARE1_GPLL_SLEEP_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00061004) +#define HWIO_GCC_SPARE1_GPLL_SLEEP_ENA_VOTE_RMSK 0x7f +#define HWIO_GCC_SPARE1_GPLL_SLEEP_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_SPARE1_GPLL_SLEEP_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_SPARE1_GPLL_SLEEP_ENA_VOTE_ADDR, HWIO_GCC_SPARE1_GPLL_SLEEP_ENA_VOTE_RMSK) +#define HWIO_GCC_SPARE1_GPLL_SLEEP_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_SPARE1_GPLL_SLEEP_ENA_VOTE_ADDR, m) +#define HWIO_GCC_SPARE1_GPLL_SLEEP_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_SPARE1_GPLL_SLEEP_ENA_VOTE_ADDR,v) +#define HWIO_GCC_SPARE1_GPLL_SLEEP_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPARE1_GPLL_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_SPARE1_GPLL_SLEEP_ENA_VOTE_IN) +#define HWIO_GCC_SPARE1_GPLL_SLEEP_ENA_VOTE_GPLL6_BMSK 0x40 +#define HWIO_GCC_SPARE1_GPLL_SLEEP_ENA_VOTE_GPLL6_SHFT 0x6 +#define HWIO_GCC_SPARE1_GPLL_SLEEP_ENA_VOTE_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_GPLL_SLEEP_ENA_VOTE_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_GPLL_SLEEP_ENA_VOTE_GPLL5_BMSK 0x20 +#define HWIO_GCC_SPARE1_GPLL_SLEEP_ENA_VOTE_GPLL5_SHFT 0x5 +#define HWIO_GCC_SPARE1_GPLL_SLEEP_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_GPLL_SLEEP_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_GPLL_SLEEP_ENA_VOTE_GPLL4_BMSK 0x10 +#define HWIO_GCC_SPARE1_GPLL_SLEEP_ENA_VOTE_GPLL4_SHFT 0x4 +#define HWIO_GCC_SPARE1_GPLL_SLEEP_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_GPLL_SLEEP_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_GPLL_SLEEP_ENA_VOTE_GPLL3_BMSK 0x8 +#define HWIO_GCC_SPARE1_GPLL_SLEEP_ENA_VOTE_GPLL3_SHFT 0x3 +#define HWIO_GCC_SPARE1_GPLL_SLEEP_ENA_VOTE_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_GPLL_SLEEP_ENA_VOTE_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_GPLL_SLEEP_ENA_VOTE_GPLL2_BMSK 0x4 +#define HWIO_GCC_SPARE1_GPLL_SLEEP_ENA_VOTE_GPLL2_SHFT 0x2 +#define HWIO_GCC_SPARE1_GPLL_SLEEP_ENA_VOTE_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_GPLL_SLEEP_ENA_VOTE_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_GPLL_SLEEP_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_SPARE1_GPLL_SLEEP_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_SPARE1_GPLL_SLEEP_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_GPLL_SLEEP_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_GPLL_SLEEP_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_SPARE1_GPLL_SLEEP_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_SPARE1_GPLL_SLEEP_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_GPLL_SLEEP_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00061008) +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00061008) +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00061008) +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_RMSK 0x162f5ff +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_ADDR, HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_RMSK) +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_ADDR, m) +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_ADDR,v) +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_IN) +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_IMEM_AXI_CLK_ENA_BMSK 0x1000000 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_IMEM_AXI_CLK_ENA_SHFT 0x18 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_IMEM_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_IMEM_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_CPUSS_GNOC_CLK_ENA_BMSK 0x400000 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_CPUSS_GNOC_CLK_ENA_SHFT 0x16 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_CPUSS_GNOC_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_CPUSS_GNOC_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_BMSK 0x200000 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_SHFT 0x15 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_BMSK 0x20000 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_SHFT 0x11 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_BLSP1_SLEEP_CLK_ENA_BMSK 0x8000 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_BLSP1_SLEEP_CLK_ENA_SHFT 0xf +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_BLSP1_SLEEP_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_BLSP1_SLEEP_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_BLSP1_AHB_CLK_ENA_BMSK 0x4000 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_BLSP1_AHB_CLK_ENA_SHFT 0xe +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_BLSP1_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_BLSP1_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_BMSK 0x2000 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_SHFT 0xd +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_BMSK 0x1000 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_SHFT 0xc +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_BMSK 0x400 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_SHFT 0xa +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_ENA_BMSK 0x100 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_ENA_SHFT 0x8 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_ENA_BMSK 0x80 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_ENA_SHFT 0x7 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_BMSK 0x40 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_SHFT 0x6 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_BMSK 0x20 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_SHFT 0x5 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_BMSK 0x10 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_SHFT 0x4 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_BMSK 0x8 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_SHFT 0x3 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_BMSK 0x4 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_SHFT 0x2 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_BMSK 0x2 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_SHFT 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_BMSK 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_SHFT 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006100c) +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006100c) +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006100c) +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_RMSK 0x162f5ff +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_ADDR, HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_RMSK) +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_ADDR, m) +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_ADDR,v) +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_IN) +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_IMEM_AXI_CLK_SLEEP_ENA_BMSK 0x1000000 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_IMEM_AXI_CLK_SLEEP_ENA_SHFT 0x18 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_IMEM_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_IMEM_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_CPUSS_GNOC_CLK_SLEEP_ENA_BMSK 0x400000 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_CPUSS_GNOC_CLK_SLEEP_ENA_SHFT 0x16 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_CPUSS_GNOC_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_CPUSS_GNOC_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_BMSK 0x200000 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_SHFT 0x15 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK 0x20000 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT 0x11 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_BLSP1_SLEEP_CLK_SLEEP_ENA_BMSK 0x8000 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_BLSP1_SLEEP_CLK_SLEEP_ENA_SHFT 0xf +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_BLSP1_SLEEP_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_BLSP1_SLEEP_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_BLSP1_AHB_CLK_SLEEP_ENA_BMSK 0x4000 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_BLSP1_AHB_CLK_SLEEP_ENA_SHFT 0xe +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_BLSP1_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_BLSP1_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_BMSK 0x2000 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_SHFT 0xd +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_BMSK 0x1000 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_SHFT 0xc +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_BMSK 0x400 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_SHFT 0xa +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_SLEEP_ENA_BMSK 0x100 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_SLEEP_ENA_SHFT 0x8 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_SLEEP_ENA_BMSK 0x80 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_SLEEP_ENA_SHFT 0x7 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_BMSK 0x40 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_SHFT 0x6 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_BMSK 0x20 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_SHFT 0x5 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_BMSK 0x10 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_SHFT 0x4 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_BMSK 0x8 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_SHFT 0x3 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_BMSK 0x4 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_SHFT 0x2 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_BMSK 0x2 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_SHFT 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_BMSK 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_SHFT 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00061010) +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00061010) +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00061010) +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_RMSK 0xff +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_ATTR 0x3 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_IN \ + in_dword_masked(HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_ADDR, HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_RMSK) +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_INM(m) \ + in_dword_masked(HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_ADDR, m) +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_OUT(v) \ + out_dword(HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_ADDR,v) +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_ADDR,m,v,HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_IN) +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_ENA_BMSK 0x80 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_ENA_SHFT 0x7 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLEEP_CLK_ENA_BMSK 0x40 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLEEP_CLK_ENA_SHFT 0x6 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLEEP_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLEEP_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_ENA_BMSK 0x20 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_ENA_SHFT 0x5 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_PIPE_CLK_ENA_BMSK 0x10 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_PIPE_CLK_ENA_SHFT 0x4 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_PIPE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_PIPE_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_AUX_CLK_ENA_BMSK 0x8 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_AUX_CLK_ENA_SHFT 0x3 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_AUX_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_AUX_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_CFG_AHB_CLK_ENA_BMSK 0x4 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_CFG_AHB_CLK_ENA_SHFT 0x2 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_CFG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_CFG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_ENA_BMSK 0x2 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_ENA_SHFT 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_AXI_CLK_ENA_BMSK 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_AXI_CLK_ENA_SHFT 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_AXI_CLK_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00061014) +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00061014) +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00061014) +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_RMSK 0xff +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_ATTR 0x3 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_IN \ + in_dword_masked(HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_ADDR, HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_RMSK) +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_INM(m) \ + in_dword_masked(HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_ADDR, m) +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_OUT(v) \ + out_dword(HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_ADDR,v) +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_ADDR,m,v,HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_IN) +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_SLEEP_ENA_BMSK 0x80 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_SLEEP_ENA_SHFT 0x7 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLEEP_CLK_SLEEP_ENA_BMSK 0x40 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLEEP_CLK_SLEEP_ENA_SHFT 0x6 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLEEP_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLEEP_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK 0x20 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT 0x5 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_PIPE_CLK_SLEEP_ENA_BMSK 0x10 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_PIPE_CLK_SLEEP_ENA_SHFT 0x4 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_PIPE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_PIPE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_AUX_CLK_SLEEP_ENA_BMSK 0x8 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_AUX_CLK_SLEEP_ENA_SHFT 0x3 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_AUX_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_AUX_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_CFG_AHB_CLK_SLEEP_ENA_BMSK 0x4 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_CFG_AHB_CLK_SLEEP_ENA_SHFT 0x2 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_CFG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_CFG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_SLEEP_ENA_BMSK 0x2 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_SLEEP_ENA_SHFT 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_AXI_CLK_SLEEP_ENA_BMSK 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_AXI_CLK_SLEEP_ENA_SHFT 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPARE2_GPLL_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00062000) +#define HWIO_GCC_SPARE2_GPLL_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00062000) +#define HWIO_GCC_SPARE2_GPLL_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00062000) +#define HWIO_GCC_SPARE2_GPLL_ENA_VOTE_RMSK 0x7f +#define HWIO_GCC_SPARE2_GPLL_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_SPARE2_GPLL_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_SPARE2_GPLL_ENA_VOTE_ADDR, HWIO_GCC_SPARE2_GPLL_ENA_VOTE_RMSK) +#define HWIO_GCC_SPARE2_GPLL_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_SPARE2_GPLL_ENA_VOTE_ADDR, m) +#define HWIO_GCC_SPARE2_GPLL_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_SPARE2_GPLL_ENA_VOTE_ADDR,v) +#define HWIO_GCC_SPARE2_GPLL_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPARE2_GPLL_ENA_VOTE_ADDR,m,v,HWIO_GCC_SPARE2_GPLL_ENA_VOTE_IN) +#define HWIO_GCC_SPARE2_GPLL_ENA_VOTE_GPLL6_BMSK 0x40 +#define HWIO_GCC_SPARE2_GPLL_ENA_VOTE_GPLL6_SHFT 0x6 +#define HWIO_GCC_SPARE2_GPLL_ENA_VOTE_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_GPLL_ENA_VOTE_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE2_GPLL_ENA_VOTE_GPLL5_BMSK 0x20 +#define HWIO_GCC_SPARE2_GPLL_ENA_VOTE_GPLL5_SHFT 0x5 +#define HWIO_GCC_SPARE2_GPLL_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_GPLL_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE2_GPLL_ENA_VOTE_GPLL4_BMSK 0x10 +#define HWIO_GCC_SPARE2_GPLL_ENA_VOTE_GPLL4_SHFT 0x4 +#define HWIO_GCC_SPARE2_GPLL_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_GPLL_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE2_GPLL_ENA_VOTE_GPLL3_BMSK 0x8 +#define HWIO_GCC_SPARE2_GPLL_ENA_VOTE_GPLL3_SHFT 0x3 +#define HWIO_GCC_SPARE2_GPLL_ENA_VOTE_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_GPLL_ENA_VOTE_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE2_GPLL_ENA_VOTE_GPLL2_BMSK 0x4 +#define HWIO_GCC_SPARE2_GPLL_ENA_VOTE_GPLL2_SHFT 0x2 +#define HWIO_GCC_SPARE2_GPLL_ENA_VOTE_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_GPLL_ENA_VOTE_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE2_GPLL_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_SPARE2_GPLL_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_SPARE2_GPLL_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_GPLL_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE2_GPLL_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_SPARE2_GPLL_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_SPARE2_GPLL_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_GPLL_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPARE2_GPLL_SLEEP_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00062004) +#define HWIO_GCC_SPARE2_GPLL_SLEEP_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00062004) +#define HWIO_GCC_SPARE2_GPLL_SLEEP_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00062004) +#define HWIO_GCC_SPARE2_GPLL_SLEEP_ENA_VOTE_RMSK 0x7f +#define HWIO_GCC_SPARE2_GPLL_SLEEP_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_SPARE2_GPLL_SLEEP_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_SPARE2_GPLL_SLEEP_ENA_VOTE_ADDR, HWIO_GCC_SPARE2_GPLL_SLEEP_ENA_VOTE_RMSK) +#define HWIO_GCC_SPARE2_GPLL_SLEEP_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_SPARE2_GPLL_SLEEP_ENA_VOTE_ADDR, m) +#define HWIO_GCC_SPARE2_GPLL_SLEEP_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_SPARE2_GPLL_SLEEP_ENA_VOTE_ADDR,v) +#define HWIO_GCC_SPARE2_GPLL_SLEEP_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPARE2_GPLL_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_SPARE2_GPLL_SLEEP_ENA_VOTE_IN) +#define HWIO_GCC_SPARE2_GPLL_SLEEP_ENA_VOTE_GPLL6_BMSK 0x40 +#define HWIO_GCC_SPARE2_GPLL_SLEEP_ENA_VOTE_GPLL6_SHFT 0x6 +#define HWIO_GCC_SPARE2_GPLL_SLEEP_ENA_VOTE_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_GPLL_SLEEP_ENA_VOTE_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE2_GPLL_SLEEP_ENA_VOTE_GPLL5_BMSK 0x20 +#define HWIO_GCC_SPARE2_GPLL_SLEEP_ENA_VOTE_GPLL5_SHFT 0x5 +#define HWIO_GCC_SPARE2_GPLL_SLEEP_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_GPLL_SLEEP_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE2_GPLL_SLEEP_ENA_VOTE_GPLL4_BMSK 0x10 +#define HWIO_GCC_SPARE2_GPLL_SLEEP_ENA_VOTE_GPLL4_SHFT 0x4 +#define HWIO_GCC_SPARE2_GPLL_SLEEP_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_GPLL_SLEEP_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE2_GPLL_SLEEP_ENA_VOTE_GPLL3_BMSK 0x8 +#define HWIO_GCC_SPARE2_GPLL_SLEEP_ENA_VOTE_GPLL3_SHFT 0x3 +#define HWIO_GCC_SPARE2_GPLL_SLEEP_ENA_VOTE_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_GPLL_SLEEP_ENA_VOTE_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE2_GPLL_SLEEP_ENA_VOTE_GPLL2_BMSK 0x4 +#define HWIO_GCC_SPARE2_GPLL_SLEEP_ENA_VOTE_GPLL2_SHFT 0x2 +#define HWIO_GCC_SPARE2_GPLL_SLEEP_ENA_VOTE_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_GPLL_SLEEP_ENA_VOTE_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE2_GPLL_SLEEP_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_SPARE2_GPLL_SLEEP_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_SPARE2_GPLL_SLEEP_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_GPLL_SLEEP_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE2_GPLL_SLEEP_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_SPARE2_GPLL_SLEEP_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_SPARE2_GPLL_SLEEP_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_GPLL_SLEEP_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00062008) +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00062008) +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00062008) +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_RMSK 0x162f5ff +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_ADDR, HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_RMSK) +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_ADDR, m) +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_ADDR,v) +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_IN) +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_IMEM_AXI_CLK_ENA_BMSK 0x1000000 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_IMEM_AXI_CLK_ENA_SHFT 0x18 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_IMEM_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_IMEM_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_CPUSS_GNOC_CLK_ENA_BMSK 0x400000 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_CPUSS_GNOC_CLK_ENA_SHFT 0x16 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_CPUSS_GNOC_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_CPUSS_GNOC_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_BMSK 0x200000 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_SHFT 0x15 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_BMSK 0x20000 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_SHFT 0x11 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_BLSP1_SLEEP_CLK_ENA_BMSK 0x8000 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_BLSP1_SLEEP_CLK_ENA_SHFT 0xf +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_BLSP1_SLEEP_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_BLSP1_SLEEP_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_BLSP1_AHB_CLK_ENA_BMSK 0x4000 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_BLSP1_AHB_CLK_ENA_SHFT 0xe +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_BLSP1_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_BLSP1_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_BMSK 0x2000 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_SHFT 0xd +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_BMSK 0x1000 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_SHFT 0xc +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_BMSK 0x400 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_SHFT 0xa +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_ENA_BMSK 0x100 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_ENA_SHFT 0x8 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_ENA_BMSK 0x80 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_ENA_SHFT 0x7 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_BMSK 0x40 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_SHFT 0x6 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_BMSK 0x20 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_SHFT 0x5 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_BMSK 0x10 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_SHFT 0x4 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_BMSK 0x8 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_SHFT 0x3 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_BMSK 0x4 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_SHFT 0x2 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_BMSK 0x2 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_SHFT 0x1 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_BMSK 0x1 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_SHFT 0x0 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006200c) +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006200c) +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006200c) +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_RMSK 0x162f5ff +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_ADDR, HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_RMSK) +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_ADDR, m) +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_ADDR,v) +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_IN) +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_IMEM_AXI_CLK_SLEEP_ENA_BMSK 0x1000000 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_IMEM_AXI_CLK_SLEEP_ENA_SHFT 0x18 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_IMEM_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_IMEM_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_CPUSS_GNOC_CLK_SLEEP_ENA_BMSK 0x400000 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_CPUSS_GNOC_CLK_SLEEP_ENA_SHFT 0x16 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_CPUSS_GNOC_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_CPUSS_GNOC_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_BMSK 0x200000 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_SHFT 0x15 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK 0x20000 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT 0x11 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_BLSP1_SLEEP_CLK_SLEEP_ENA_BMSK 0x8000 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_BLSP1_SLEEP_CLK_SLEEP_ENA_SHFT 0xf +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_BLSP1_SLEEP_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_BLSP1_SLEEP_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_BLSP1_AHB_CLK_SLEEP_ENA_BMSK 0x4000 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_BLSP1_AHB_CLK_SLEEP_ENA_SHFT 0xe +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_BLSP1_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_BLSP1_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_BMSK 0x2000 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_SHFT 0xd +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_BMSK 0x1000 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_SHFT 0xc +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_BMSK 0x400 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_SHFT 0xa +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_SLEEP_ENA_BMSK 0x100 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_SLEEP_ENA_SHFT 0x8 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_SLEEP_ENA_BMSK 0x80 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_SLEEP_ENA_SHFT 0x7 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_BMSK 0x40 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_SHFT 0x6 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_BMSK 0x20 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_SHFT 0x5 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_BMSK 0x10 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_SHFT 0x4 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_BMSK 0x8 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_SHFT 0x3 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_BMSK 0x4 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_SHFT 0x2 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_BMSK 0x2 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_SHFT 0x1 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_BMSK 0x1 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_SHFT 0x0 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_1_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00062010) +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00062010) +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00062010) +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_1_RMSK 0xff +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_1_ATTR 0x3 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_1_IN \ + in_dword_masked(HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_1_ADDR, HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_1_RMSK) +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_1_INM(m) \ + in_dword_masked(HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_1_ADDR, m) +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_1_OUT(v) \ + out_dword(HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_1_ADDR,v) +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_1_ADDR,m,v,HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_1_IN) +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_ENA_BMSK 0x80 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_ENA_SHFT 0x7 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLEEP_CLK_ENA_BMSK 0x40 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLEEP_CLK_ENA_SHFT 0x6 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLEEP_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLEEP_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_ENA_BMSK 0x20 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_ENA_SHFT 0x5 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_1_PCIE_PIPE_CLK_ENA_BMSK 0x10 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_1_PCIE_PIPE_CLK_ENA_SHFT 0x4 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_1_PCIE_PIPE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_1_PCIE_PIPE_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_1_PCIE_AUX_CLK_ENA_BMSK 0x8 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_1_PCIE_AUX_CLK_ENA_SHFT 0x3 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_1_PCIE_AUX_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_1_PCIE_AUX_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_1_PCIE_CFG_AHB_CLK_ENA_BMSK 0x4 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_1_PCIE_CFG_AHB_CLK_ENA_SHFT 0x2 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_1_PCIE_CFG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_1_PCIE_CFG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_ENA_BMSK 0x2 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_ENA_SHFT 0x1 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_AXI_CLK_ENA_BMSK 0x1 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_AXI_CLK_ENA_SHFT 0x0 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_AXI_CLK_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_1_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00062014) +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00062014) +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00062014) +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_1_RMSK 0xff +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_1_ATTR 0x3 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_1_IN \ + in_dword_masked(HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_1_ADDR, HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_1_RMSK) +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_1_INM(m) \ + in_dword_masked(HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_1_ADDR, m) +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_1_OUT(v) \ + out_dword(HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_1_ADDR,v) +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_1_ADDR,m,v,HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_1_IN) +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_SLEEP_ENA_BMSK 0x80 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_SLEEP_ENA_SHFT 0x7 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLEEP_CLK_SLEEP_ENA_BMSK 0x40 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLEEP_CLK_SLEEP_ENA_SHFT 0x6 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLEEP_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLEEP_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK 0x20 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT 0x5 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_1_PCIE_PIPE_CLK_SLEEP_ENA_BMSK 0x10 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_1_PCIE_PIPE_CLK_SLEEP_ENA_SHFT 0x4 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_1_PCIE_PIPE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_1_PCIE_PIPE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_1_PCIE_AUX_CLK_SLEEP_ENA_BMSK 0x8 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_1_PCIE_AUX_CLK_SLEEP_ENA_SHFT 0x3 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_1_PCIE_AUX_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_1_PCIE_AUX_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_1_PCIE_CFG_AHB_CLK_SLEEP_ENA_BMSK 0x4 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_1_PCIE_CFG_AHB_CLK_SLEEP_ENA_SHFT 0x2 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_1_PCIE_CFG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_1_PCIE_CFG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_SLEEP_ENA_BMSK 0x2 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_SLEEP_ENA_SHFT 0x1 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_AXI_CLK_SLEEP_ENA_BMSK 0x1 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_AXI_CLK_SLEEP_ENA_SHFT 0x0 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_Q6_GPLL_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00063000) +#define HWIO_GCC_MSS_Q6_GPLL_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00063000) +#define HWIO_GCC_MSS_Q6_GPLL_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00063000) +#define HWIO_GCC_MSS_Q6_GPLL_ENA_VOTE_RMSK 0x7f +#define HWIO_GCC_MSS_Q6_GPLL_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_MSS_Q6_GPLL_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_MSS_Q6_GPLL_ENA_VOTE_ADDR, HWIO_GCC_MSS_Q6_GPLL_ENA_VOTE_RMSK) +#define HWIO_GCC_MSS_Q6_GPLL_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_Q6_GPLL_ENA_VOTE_ADDR, m) +#define HWIO_GCC_MSS_Q6_GPLL_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_MSS_Q6_GPLL_ENA_VOTE_ADDR,v) +#define HWIO_GCC_MSS_Q6_GPLL_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_Q6_GPLL_ENA_VOTE_ADDR,m,v,HWIO_GCC_MSS_Q6_GPLL_ENA_VOTE_IN) +#define HWIO_GCC_MSS_Q6_GPLL_ENA_VOTE_GPLL6_BMSK 0x40 +#define HWIO_GCC_MSS_Q6_GPLL_ENA_VOTE_GPLL6_SHFT 0x6 +#define HWIO_GCC_MSS_Q6_GPLL_ENA_VOTE_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_GPLL_ENA_VOTE_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_GPLL_ENA_VOTE_GPLL5_BMSK 0x20 +#define HWIO_GCC_MSS_Q6_GPLL_ENA_VOTE_GPLL5_SHFT 0x5 +#define HWIO_GCC_MSS_Q6_GPLL_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_GPLL_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_GPLL_ENA_VOTE_GPLL4_BMSK 0x10 +#define HWIO_GCC_MSS_Q6_GPLL_ENA_VOTE_GPLL4_SHFT 0x4 +#define HWIO_GCC_MSS_Q6_GPLL_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_GPLL_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_GPLL_ENA_VOTE_GPLL3_BMSK 0x8 +#define HWIO_GCC_MSS_Q6_GPLL_ENA_VOTE_GPLL3_SHFT 0x3 +#define HWIO_GCC_MSS_Q6_GPLL_ENA_VOTE_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_GPLL_ENA_VOTE_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_GPLL_ENA_VOTE_GPLL2_BMSK 0x4 +#define HWIO_GCC_MSS_Q6_GPLL_ENA_VOTE_GPLL2_SHFT 0x2 +#define HWIO_GCC_MSS_Q6_GPLL_ENA_VOTE_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_GPLL_ENA_VOTE_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_GPLL_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_MSS_Q6_GPLL_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_MSS_Q6_GPLL_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_GPLL_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_GPLL_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_MSS_Q6_GPLL_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_MSS_Q6_GPLL_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_GPLL_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_Q6_GPLL_SLEEP_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00063004) +#define HWIO_GCC_MSS_Q6_GPLL_SLEEP_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00063004) +#define HWIO_GCC_MSS_Q6_GPLL_SLEEP_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00063004) +#define HWIO_GCC_MSS_Q6_GPLL_SLEEP_ENA_VOTE_RMSK 0x7f +#define HWIO_GCC_MSS_Q6_GPLL_SLEEP_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_MSS_Q6_GPLL_SLEEP_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_MSS_Q6_GPLL_SLEEP_ENA_VOTE_ADDR, HWIO_GCC_MSS_Q6_GPLL_SLEEP_ENA_VOTE_RMSK) +#define HWIO_GCC_MSS_Q6_GPLL_SLEEP_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_Q6_GPLL_SLEEP_ENA_VOTE_ADDR, m) +#define HWIO_GCC_MSS_Q6_GPLL_SLEEP_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_MSS_Q6_GPLL_SLEEP_ENA_VOTE_ADDR,v) +#define HWIO_GCC_MSS_Q6_GPLL_SLEEP_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_Q6_GPLL_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_MSS_Q6_GPLL_SLEEP_ENA_VOTE_IN) +#define HWIO_GCC_MSS_Q6_GPLL_SLEEP_ENA_VOTE_GPLL6_BMSK 0x40 +#define HWIO_GCC_MSS_Q6_GPLL_SLEEP_ENA_VOTE_GPLL6_SHFT 0x6 +#define HWIO_GCC_MSS_Q6_GPLL_SLEEP_ENA_VOTE_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_GPLL_SLEEP_ENA_VOTE_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_GPLL_SLEEP_ENA_VOTE_GPLL5_BMSK 0x20 +#define HWIO_GCC_MSS_Q6_GPLL_SLEEP_ENA_VOTE_GPLL5_SHFT 0x5 +#define HWIO_GCC_MSS_Q6_GPLL_SLEEP_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_GPLL_SLEEP_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_GPLL_SLEEP_ENA_VOTE_GPLL4_BMSK 0x10 +#define HWIO_GCC_MSS_Q6_GPLL_SLEEP_ENA_VOTE_GPLL4_SHFT 0x4 +#define HWIO_GCC_MSS_Q6_GPLL_SLEEP_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_GPLL_SLEEP_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_GPLL_SLEEP_ENA_VOTE_GPLL3_BMSK 0x8 +#define HWIO_GCC_MSS_Q6_GPLL_SLEEP_ENA_VOTE_GPLL3_SHFT 0x3 +#define HWIO_GCC_MSS_Q6_GPLL_SLEEP_ENA_VOTE_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_GPLL_SLEEP_ENA_VOTE_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_GPLL_SLEEP_ENA_VOTE_GPLL2_BMSK 0x4 +#define HWIO_GCC_MSS_Q6_GPLL_SLEEP_ENA_VOTE_GPLL2_SHFT 0x2 +#define HWIO_GCC_MSS_Q6_GPLL_SLEEP_ENA_VOTE_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_GPLL_SLEEP_ENA_VOTE_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_GPLL_SLEEP_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_MSS_Q6_GPLL_SLEEP_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_MSS_Q6_GPLL_SLEEP_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_GPLL_SLEEP_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_GPLL_SLEEP_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_MSS_Q6_GPLL_SLEEP_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_MSS_Q6_GPLL_SLEEP_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_GPLL_SLEEP_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00063008) +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00063008) +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00063008) +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_RMSK 0x162f5ff +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_ADDR, HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_RMSK) +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_ADDR, m) +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_ADDR,v) +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_IN) +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_IMEM_AXI_CLK_ENA_BMSK 0x1000000 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_IMEM_AXI_CLK_ENA_SHFT 0x18 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_IMEM_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_IMEM_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_CPUSS_GNOC_CLK_ENA_BMSK 0x400000 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_CPUSS_GNOC_CLK_ENA_SHFT 0x16 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_CPUSS_GNOC_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_CPUSS_GNOC_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_BMSK 0x200000 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_SHFT 0x15 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_BMSK 0x20000 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_SHFT 0x11 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_BLSP1_SLEEP_CLK_ENA_BMSK 0x8000 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_BLSP1_SLEEP_CLK_ENA_SHFT 0xf +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_BLSP1_SLEEP_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_BLSP1_SLEEP_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_BLSP1_AHB_CLK_ENA_BMSK 0x4000 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_BLSP1_AHB_CLK_ENA_SHFT 0xe +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_BLSP1_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_BLSP1_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_BMSK 0x2000 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_SHFT 0xd +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_BMSK 0x1000 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_SHFT 0xc +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_BMSK 0x400 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_SHFT 0xa +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_ENA_BMSK 0x100 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_ENA_SHFT 0x8 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_ENA_BMSK 0x80 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_ENA_SHFT 0x7 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_BMSK 0x40 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_SHFT 0x6 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_BMSK 0x20 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_SHFT 0x5 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_BMSK 0x10 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_SHFT 0x4 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_BMSK 0x8 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_SHFT 0x3 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_BMSK 0x4 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_SHFT 0x2 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_BMSK 0x2 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_SHFT 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_BMSK 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_SHFT 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006300c) +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006300c) +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006300c) +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_RMSK 0x162f5ff +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_ADDR, HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_RMSK) +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_ADDR, m) +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_ADDR,v) +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_IN) +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_IMEM_AXI_CLK_SLEEP_ENA_BMSK 0x1000000 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_IMEM_AXI_CLK_SLEEP_ENA_SHFT 0x18 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_IMEM_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_IMEM_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_CPUSS_GNOC_CLK_SLEEP_ENA_BMSK 0x400000 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_CPUSS_GNOC_CLK_SLEEP_ENA_SHFT 0x16 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_CPUSS_GNOC_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_CPUSS_GNOC_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_BMSK 0x200000 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_SHFT 0x15 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK 0x20000 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT 0x11 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_BLSP1_SLEEP_CLK_SLEEP_ENA_BMSK 0x8000 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_BLSP1_SLEEP_CLK_SLEEP_ENA_SHFT 0xf +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_BLSP1_SLEEP_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_BLSP1_SLEEP_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_BLSP1_AHB_CLK_SLEEP_ENA_BMSK 0x4000 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_BLSP1_AHB_CLK_SLEEP_ENA_SHFT 0xe +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_BLSP1_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_BLSP1_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_BMSK 0x2000 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_SHFT 0xd +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_BMSK 0x1000 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_SHFT 0xc +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_BMSK 0x400 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_SHFT 0xa +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_SLEEP_ENA_BMSK 0x100 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_SLEEP_ENA_SHFT 0x8 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_SLEEP_ENA_BMSK 0x80 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_SLEEP_ENA_SHFT 0x7 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_ULTAUDIO_PCNOC_SWAY_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_BMSK 0x40 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_SHFT 0x6 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_BMSK 0x20 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_SHFT 0x5 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_BMSK 0x10 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_SHFT 0x4 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_BMSK 0x8 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_SHFT 0x3 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_BMSK 0x4 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_SHFT 0x2 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_BMSK 0x2 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_SHFT 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_BMSK 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_SHFT 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00063010) +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00063010) +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00063010) +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_RMSK 0xff +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_ATTR 0x3 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_IN \ + in_dword_masked(HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_ADDR, HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_RMSK) +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_ADDR, m) +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_OUT(v) \ + out_dword(HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_ADDR,v) +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_ADDR,m,v,HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_IN) +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_ENA_BMSK 0x80 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_ENA_SHFT 0x7 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLEEP_CLK_ENA_BMSK 0x40 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLEEP_CLK_ENA_SHFT 0x6 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLEEP_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLEEP_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_ENA_BMSK 0x20 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_ENA_SHFT 0x5 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_PIPE_CLK_ENA_BMSK 0x10 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_PIPE_CLK_ENA_SHFT 0x4 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_PIPE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_PIPE_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_AUX_CLK_ENA_BMSK 0x8 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_AUX_CLK_ENA_SHFT 0x3 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_AUX_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_AUX_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_CFG_AHB_CLK_ENA_BMSK 0x4 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_CFG_AHB_CLK_ENA_SHFT 0x2 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_CFG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_CFG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_ENA_BMSK 0x2 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_ENA_SHFT 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_AXI_CLK_ENA_BMSK 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_AXI_CLK_ENA_SHFT 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_SLV_AXI_CLK_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00063014) +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00063014) +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00063014) +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_RMSK 0xff +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_ATTR 0x3 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_IN \ + in_dword_masked(HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_ADDR, HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_RMSK) +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_ADDR, m) +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_OUT(v) \ + out_dword(HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_ADDR,v) +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_ADDR,m,v,HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_IN) +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_SLEEP_ENA_BMSK 0x80 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_SLEEP_ENA_SHFT 0x7 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_RCHNG_PHY_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLEEP_CLK_SLEEP_ENA_BMSK 0x40 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLEEP_CLK_SLEEP_ENA_SHFT 0x6 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLEEP_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLEEP_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK 0x20 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT 0x5 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_Q2A_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_PIPE_CLK_SLEEP_ENA_BMSK 0x10 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_PIPE_CLK_SLEEP_ENA_SHFT 0x4 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_PIPE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_PIPE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_AUX_CLK_SLEEP_ENA_BMSK 0x8 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_AUX_CLK_SLEEP_ENA_SHFT 0x3 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_AUX_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_AUX_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_CFG_AHB_CLK_SLEEP_ENA_BMSK 0x4 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_CFG_AHB_CLK_SLEEP_ENA_SHFT 0x2 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_CFG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_CFG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_SLEEP_ENA_BMSK 0x2 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_SLEEP_ENA_SHFT 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_MSTR_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_AXI_CLK_SLEEP_ENA_BMSK 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_AXI_CLK_SLEEP_ENA_SHFT 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_SLV_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_MISC_RESET_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00067004) +#define HWIO_GCC_PCIE_MISC_RESET_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00067004) +#define HWIO_GCC_PCIE_MISC_RESET_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00067004) +#define HWIO_GCC_PCIE_MISC_RESET_RMSK 0x3fff +#define HWIO_GCC_PCIE_MISC_RESET_ATTR 0x3 +#define HWIO_GCC_PCIE_MISC_RESET_IN \ + in_dword_masked(HWIO_GCC_PCIE_MISC_RESET_ADDR, HWIO_GCC_PCIE_MISC_RESET_RMSK) +#define HWIO_GCC_PCIE_MISC_RESET_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_MISC_RESET_ADDR, m) +#define HWIO_GCC_PCIE_MISC_RESET_OUT(v) \ + out_dword(HWIO_GCC_PCIE_MISC_RESET_ADDR,v) +#define HWIO_GCC_PCIE_MISC_RESET_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_MISC_RESET_ADDR,m,v,HWIO_GCC_PCIE_MISC_RESET_IN) +#define HWIO_GCC_PCIE_MISC_RESET_PCIE_SLV_AXI_Q2A_BRIDGE2MX_BCR_BLK_ARES_BMSK 0x2000 +#define HWIO_GCC_PCIE_MISC_RESET_PCIE_SLV_AXI_Q2A_BRIDGE2MX_BCR_BLK_ARES_SHFT 0xd +#define HWIO_GCC_PCIE_MISC_RESET_PCIE_SLV_AXI_Q2A_BRIDGE2MX_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_MISC_RESET_PCIE_SLV_AXI_Q2A_BRIDGE2MX_BCR_BLK_ARES_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_MISC_RESET_PCIE_MSTR_AXI_BRIDGE2MX_BCR_BLK_ARES_BMSK 0x1000 +#define HWIO_GCC_PCIE_MISC_RESET_PCIE_MSTR_AXI_BRIDGE2MX_BCR_BLK_ARES_SHFT 0xc +#define HWIO_GCC_PCIE_MISC_RESET_PCIE_MSTR_AXI_BRIDGE2MX_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_MISC_RESET_PCIE_MSTR_AXI_BRIDGE2MX_BCR_BLK_ARES_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_MISC_RESET_PCIE_CFG_AHB_BRIDGE2MX_BCR_BLK_ARES_BMSK 0x800 +#define HWIO_GCC_PCIE_MISC_RESET_PCIE_CFG_AHB_BRIDGE2MX_BCR_BLK_ARES_SHFT 0xb +#define HWIO_GCC_PCIE_MISC_RESET_PCIE_CFG_AHB_BRIDGE2MX_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_MISC_RESET_PCIE_CFG_AHB_BRIDGE2MX_BCR_BLK_ARES_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_MISC_RESET_PCIE_RCHNG_PHY_BCR_BLK_ARES_BMSK 0x400 +#define HWIO_GCC_PCIE_MISC_RESET_PCIE_RCHNG_PHY_BCR_BLK_ARES_SHFT 0xa +#define HWIO_GCC_PCIE_MISC_RESET_PCIE_RCHNG_PHY_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_MISC_RESET_PCIE_RCHNG_PHY_BCR_BLK_ARES_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_MISC_RESET_PCIE_SLV_AXI_Q2A_BCR_BLK_ARES_BMSK 0x200 +#define HWIO_GCC_PCIE_MISC_RESET_PCIE_SLV_AXI_Q2A_BCR_BLK_ARES_SHFT 0x9 +#define HWIO_GCC_PCIE_MISC_RESET_PCIE_SLV_AXI_Q2A_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_MISC_RESET_PCIE_SLV_AXI_Q2A_BCR_BLK_ARES_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_MISC_RESET_PCIE_SLEEP_BCR_BLK_ARES_BMSK 0x100 +#define HWIO_GCC_PCIE_MISC_RESET_PCIE_SLEEP_BCR_BLK_ARES_SHFT 0x8 +#define HWIO_GCC_PCIE_MISC_RESET_PCIE_SLEEP_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_MISC_RESET_PCIE_SLEEP_BCR_BLK_ARES_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_MISC_RESET_PCIE_SLV_AXI_STICKY_BCR_BLK_ARES_BMSK 0x80 +#define HWIO_GCC_PCIE_MISC_RESET_PCIE_SLV_AXI_STICKY_BCR_BLK_ARES_SHFT 0x7 +#define HWIO_GCC_PCIE_MISC_RESET_PCIE_SLV_AXI_STICKY_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_MISC_RESET_PCIE_SLV_AXI_STICKY_BCR_BLK_ARES_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_MISC_RESET_PCIE_CORE_STICKY_BCR_BLK_ARES_BMSK 0x40 +#define HWIO_GCC_PCIE_MISC_RESET_PCIE_CORE_STICKY_BCR_BLK_ARES_SHFT 0x6 +#define HWIO_GCC_PCIE_MISC_RESET_PCIE_CORE_STICKY_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_MISC_RESET_PCIE_CORE_STICKY_BCR_BLK_ARES_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_MISC_RESET_PCIE_MSTR_AXI_STICKY_BCR_BLK_ARES_BMSK 0x20 +#define HWIO_GCC_PCIE_MISC_RESET_PCIE_MSTR_AXI_STICKY_BCR_BLK_ARES_SHFT 0x5 +#define HWIO_GCC_PCIE_MISC_RESET_PCIE_MSTR_AXI_STICKY_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_MISC_RESET_PCIE_MSTR_AXI_STICKY_BCR_BLK_ARES_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_MISC_RESET_PCIE_PIPE_BCR_BLK_ARES_BMSK 0x10 +#define HWIO_GCC_PCIE_MISC_RESET_PCIE_PIPE_BCR_BLK_ARES_SHFT 0x4 +#define HWIO_GCC_PCIE_MISC_RESET_PCIE_PIPE_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_MISC_RESET_PCIE_PIPE_BCR_BLK_ARES_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_MISC_RESET_PCIE_AUX_BCR_BLK_ARES_BMSK 0x8 +#define HWIO_GCC_PCIE_MISC_RESET_PCIE_AUX_BCR_BLK_ARES_SHFT 0x3 +#define HWIO_GCC_PCIE_MISC_RESET_PCIE_AUX_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_MISC_RESET_PCIE_AUX_BCR_BLK_ARES_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_MISC_RESET_PCIE_CFG_AHB_BCR_BLK_ARES_BMSK 0x4 +#define HWIO_GCC_PCIE_MISC_RESET_PCIE_CFG_AHB_BCR_BLK_ARES_SHFT 0x2 +#define HWIO_GCC_PCIE_MISC_RESET_PCIE_CFG_AHB_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_MISC_RESET_PCIE_CFG_AHB_BCR_BLK_ARES_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_MISC_RESET_PCIE_MSTR_AXI_BCR_BLK_ARES_BMSK 0x2 +#define HWIO_GCC_PCIE_MISC_RESET_PCIE_MSTR_AXI_BCR_BLK_ARES_SHFT 0x1 +#define HWIO_GCC_PCIE_MISC_RESET_PCIE_MSTR_AXI_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_MISC_RESET_PCIE_MSTR_AXI_BCR_BLK_ARES_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_MISC_RESET_PCIE_SLV_AXI_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_PCIE_MISC_RESET_PCIE_SLV_AXI_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_PCIE_MISC_RESET_PCIE_SLV_AXI_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_MISC_RESET_PCIE_SLV_AXI_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_DEBUG_CLK_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00069000) +#define HWIO_GCC_DEBUG_CLK_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00069000) +#define HWIO_GCC_DEBUG_CLK_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00069000) +#define HWIO_GCC_DEBUG_CLK_CTL_RMSK 0x7fc7ff +#define HWIO_GCC_DEBUG_CLK_CTL_ATTR 0x3 +#define HWIO_GCC_DEBUG_CLK_CTL_IN \ + in_dword_masked(HWIO_GCC_DEBUG_CLK_CTL_ADDR, HWIO_GCC_DEBUG_CLK_CTL_RMSK) +#define HWIO_GCC_DEBUG_CLK_CTL_INM(m) \ + in_dword_masked(HWIO_GCC_DEBUG_CLK_CTL_ADDR, m) +#define HWIO_GCC_DEBUG_CLK_CTL_OUT(v) \ + out_dword(HWIO_GCC_DEBUG_CLK_CTL_ADDR,v) +#define HWIO_GCC_DEBUG_CLK_CTL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DEBUG_CLK_CTL_ADDR,m,v,HWIO_GCC_DEBUG_CLK_CTL_IN) +#define HWIO_GCC_DEBUG_CLK_CTL_DEBUG_BUS_SEL_BMSK 0x780000 +#define HWIO_GCC_DEBUG_CLK_CTL_DEBUG_BUS_SEL_SHFT 0x13 +#define HWIO_GCC_DEBUG_CLK_CTL_DEBUG_BUS_SEL_DEFAULT_ZERO_FVAL 0x0 +#define HWIO_GCC_DEBUG_CLK_CTL_DEBUG_BUS_SEL_GPLL0_STATUS_DEBUG_FVAL 0x1 +#define HWIO_GCC_DEBUG_CLK_CTL_DEBUG_BUS_SEL_GPLL1_STATUS_DEBUG_FVAL 0x2 +#define HWIO_GCC_DEBUG_CLK_CTL_DEBUG_BUS_SEL_GPLL2_STATUS_DEBUG_FVAL 0x3 +#define HWIO_GCC_DEBUG_CLK_CTL_DEBUG_BUS_SEL_GPLL3_STATUS_DEBUG_FVAL 0x4 +#define HWIO_GCC_DEBUG_CLK_CTL_DEBUG_BUS_SEL_GPLL4_STATUS_DEBUG_FVAL 0x5 +#define HWIO_GCC_DEBUG_CLK_CTL_DEBUG_BUS_SEL_GPLL5_STATUS_DEBUG_FVAL 0x6 +#define HWIO_GCC_DEBUG_CLK_CTL_DEBUG_BUS_SEL_JBIST_STATUS_DEBUG_FVAL 0x7 +#define HWIO_GCC_DEBUG_CLK_CTL_DEBUG_BUS_SEL_SYSTEM_NOC_CLK_SRC_DEBUG_BUS_FVAL 0xa +#define HWIO_GCC_DEBUG_CLK_CTL_DEBUG_BUS_SEL_GPLL_LOCK_DET_STATUS_FVAL 0xb +#define HWIO_GCC_DEBUG_CLK_CTL_DEBUG_BUS_SEL_GPLL_DTEST_FVAL 0xc +#define HWIO_GCC_DEBUG_CLK_CTL_PLL_LOCK_DET_MUX_SEL_BMSK 0x7c000 +#define HWIO_GCC_DEBUG_CLK_CTL_PLL_LOCK_DET_MUX_SEL_SHFT 0xe +#define HWIO_GCC_DEBUG_CLK_CTL_PLL_LOCK_DET_MUX_SEL_GPLL0_LOCK_DET_STATUS_FVAL 0x1 +#define HWIO_GCC_DEBUG_CLK_CTL_PLL_LOCK_DET_MUX_SEL_GPLL1_LOCK_DET_STATUS_FVAL 0x2 +#define HWIO_GCC_DEBUG_CLK_CTL_PLL_LOCK_DET_MUX_SEL_GPLL2_LOCK_DET_STATUS_FVAL 0x3 +#define HWIO_GCC_DEBUG_CLK_CTL_PLL_LOCK_DET_MUX_SEL_GPLL3_LOCK_DET_STATUS_FVAL 0x4 +#define HWIO_GCC_DEBUG_CLK_CTL_PLL_LOCK_DET_MUX_SEL_GPLL4_LOCK_DET_STATUS_FVAL 0x5 +#define HWIO_GCC_DEBUG_CLK_CTL_PLL_LOCK_DET_MUX_SEL_GPLL5_LOCK_DET_STATUS_FVAL 0x6 +#define HWIO_GCC_DEBUG_CLK_CTL_PLL_LOCK_DET_MUX_SEL_MSS_PLL0_LOCK_DET_STATUS_FVAL 0x8 +#define HWIO_GCC_DEBUG_CLK_CTL_PLL_LOCK_DET_MUX_SEL_MSS_PLL1_LOCK_DET_STATUS_FVAL 0x9 +#define HWIO_GCC_DEBUG_CLK_CTL_PLL_LOCK_DET_MUX_SEL_MSS_PLL2_LOCK_DET_STATUS_FVAL 0xa +#define HWIO_GCC_DEBUG_CLK_CTL_PLL_LOCK_DET_MUX_SEL_MSS_PLL3_LOCK_DET_STATUS_FVAL 0xb +#define HWIO_GCC_DEBUG_CLK_CTL_PLL_LOCK_DET_MUX_SEL_CPUSS_PLL0_LOCK_DET_STATUS_FVAL 0xc +#define HWIO_GCC_DEBUG_CLK_CTL_PLL_LOCK_DET_MUX_SEL_AOSS_PLL0_LOCK_DET_STATUS_FVAL 0xd +#define HWIO_GCC_DEBUG_CLK_CTL_PLL_LOCK_DET_MUX_SEL_AOSS_PLL1_LOCK_DET_STATUS_FVAL 0xe +#define HWIO_GCC_DEBUG_CLK_CTL_PLL_LOCK_DET_MUX_SEL_NAV_PLL0_LOCK_DET_STATUS_FVAL 0xf +#define HWIO_GCC_DEBUG_CLK_CTL_PLL_LOCK_DET_MUX_SEL_DDRSS_PLL0_LOCK_DET_STATUS_FVAL 0x10 +#define HWIO_GCC_DEBUG_CLK_CTL_PLL_LOCK_DET_MUX_SEL_EMAC_DLL_LOCK_DET_STATUS_FVAL 0x11 +#define HWIO_GCC_DEBUG_CLK_CTL_PLL_LOCK_DET_MUX_SEL_SDCC_DLL_LOCK_DET_STATUS_FVAL 0x12 +#define HWIO_GCC_DEBUG_CLK_CTL_PLLTEST_DE_SEL_BMSK 0x400 +#define HWIO_GCC_DEBUG_CLK_CTL_PLLTEST_DE_SEL_SHFT 0xa +#define HWIO_GCC_DEBUG_CLK_CTL_PLLTEST_DE_SEL_DEBUG_PREDIV_CLK_FVAL 0x0 +#define HWIO_GCC_DEBUG_CLK_CTL_PLLTEST_DE_SEL_PLLTEST_DE_FVAL 0x1 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_BMSK 0x3ff +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_SHFT 0x0 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_BI_TCXO_FVAL 0x1 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_CORE_PI_SLEEP_CLK_FVAL 0x2 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_TIC_CLK_FVAL 0x3 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_AUD_REF_CLK_FVAL 0x4 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_CORE_BI_PLL_TEST_SE_FVAL 0x5 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_JBIST_REF_CLK_FVAL 0x6 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_SYS_NOC_IPA_CLK_FVAL 0xa +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_SYS_NOC_AT_CLK_FVAL 0xd +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_SNOC_QOSGEN_EXTREF_CLK_FVAL 0xf +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_CFG_AHB_CLK_FVAL 0x10 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_NOC_DCD_XO_CLK_FVAL 0x12 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_TIC_CLK_FVAL 0x13 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_TIC_CFG_AHB_CLK_FVAL 0x14 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_IMEM_AXI_CLK_FVAL 0x15 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_IMEM_CFG_AHB_CLK_FVAL 0x16 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_SYS_NOC_TCU_CLK_FVAL 0x17 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_MMU_TCU_CLK_FVAL 0x18 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_AGGRE_NOC_TBU1_CLK_FVAL 0x1b +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_AGGRE_NOC_TBU2_CLK_FVAL 0x1c +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_QDSS_DAP_AHB_CLK_FVAL 0x1d +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_QDSS_CFG_AHB_CLK_FVAL 0x1e +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_QDSS_AT_CLK_FVAL 0x1f +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_QDSS_ETR_USB_CLK_FVAL 0x20 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_QDSS_STM_CLK_FVAL 0x21 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_QDSS_TRACECLKIN_CLK_FVAL 0x22 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_QDSS_TSCTR_CLK_FVAL 0x23 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_QDSS_TRIG_CLK_FVAL 0x24 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_QDSS_DAP_CLK_FVAL 0x25 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_APB_CLK_FVAL 0x26 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_QDSS_XO_CLK_FVAL 0x27 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_USB30_MASTER_CLK_FVAL 0x28 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_USB30_SLEEP_CLK_FVAL 0x29 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_USB30_MOCK_UTMI_CLK_FVAL 0x2a +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_USB3_PHY_AUX_CLK_FVAL 0x2b +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_USB3_PHY_PIPE_CLK_FVAL 0x2d +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK_FVAL 0x2e +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_QUSB2PHY_SEC_GCC_USB30_UTMI_CLK_FVAL 0x2f +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_QUSB2PHY_GCC_USB30_UTMI_CLK_FVAL 0x30 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_USB_PHY_CFG_AHB2PHY_CLK_FVAL 0x31 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_SDCC1_APPS_CLK_FVAL 0x32 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_SDCC1_AHB_CLK_FVAL 0x33 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_BLSP1_AHB_CLK_FVAL 0x34 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_BLSP1_SLEEP_CLK_FVAL 0x35 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_BLSP1_QUP1_SPI_APPS_CLK_FVAL 0x36 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_BLSP1_QUP1_I2C_APPS_CLK_FVAL 0x37 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_BLSP1_UART1_APPS_CLK_FVAL 0x38 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_BLSP1_UART1_SIM_CLK_FVAL 0x39 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_BLSP1_QUP2_SPI_APPS_CLK_FVAL 0x3a +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_BLSP1_QUP2_I2C_APPS_CLK_FVAL 0x3b +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_BLSP1_UART2_APPS_CLK_FVAL 0x3c +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_BLSP1_UART2_SIM_CLK_FVAL 0x3d +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_BLSP1_QUP3_SPI_APPS_CLK_FVAL 0x3e +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_BLSP1_QUP3_I2C_APPS_CLK_FVAL 0x3f +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_BLSP1_UART3_APPS_CLK_FVAL 0x40 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_BLSP1_UART3_SIM_CLK_FVAL 0x41 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_BLSP1_QUP4_SPI_APPS_CLK_FVAL 0x42 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_BLSP1_QUP4_I2C_APPS_CLK_FVAL 0x43 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_BLSP1_UART4_APPS_CLK_FVAL 0x44 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_BLSP1_UART4_SIM_CLK_FVAL 0x45 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_PDM_AHB_CLK_FVAL 0x46 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_PDM_XO4_CLK_FVAL 0x47 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_PDM2_CLK_FVAL 0x48 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_PRNG_AHB_CLK_FVAL 0x49 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_TCSR_AHB_CLK_FVAL 0x4a +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_BOOT_ROM_AHB_CLK_FVAL 0x4b +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_TLMM_AHB_CLK_FVAL 0x4c +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_TLMM_CLK_FVAL 0x4d +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_AOSS_CFG_AHB_CLK_FVAL 0x4e +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_USB30_MSTR_AXI_CLK_FVAL 0x4f +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_PCNOC_SPMI_VGIS_CLK_FVAL 0x50 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_AOSS_GCC_DEBUG_CLK_FVAL 0x51 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_SEC_CTRL_ACC_CLK_FVAL 0x52 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_SEC_CTRL_AHB_CLK_FVAL 0x53 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_SEC_CTRL_CLK_FVAL 0x54 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_SEC_CTRL_SENSE_CLK_FVAL 0x55 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_SEC_CTRL_BOOT_ROM_PATCH_CLK_FVAL 0x56 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_SPDM_CFG_AHB_CLK_FVAL 0x57 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_SPDM_MSTR_AHB_CLK_FVAL 0x58 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_SPDM_FF_CLK_FVAL 0x59 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_SPDM_MEMNOC_CY_CLK_FVAL 0x5a +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_SPDM_SNOC_CY_CLK_FVAL 0x5b +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_SPDM_PNOC_CY_CLK_FVAL 0x5d +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_CE1_CLK_FVAL 0x5e +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_CE1_AXI_CLK_FVAL 0x5f +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_CE1_AHB_CLK_FVAL 0x60 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_AHB_CLK_FVAL 0x61 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_XO_CLK_FVAL 0x62 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_XO_DIV4_CLK_FVAL 0x63 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_SLEEP_CLK_FVAL 0x64 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_DDRSS_TCU_CLK_FVAL 0x65 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_DDRSS_SYS_NOC_AXI_CLK_FVAL 0x66 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_DDRSS_XO_CLK_FVAL 0x67 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_DDRSS_CFG_AHB_CLK_FVAL 0x68 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_DDRSS_SLEEP_CLK_FVAL 0x69 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_MEMNOC_CLK_FVAL 0x6a +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_USB30_SLV_AHB_CLK_FVAL 0x6b +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_DDRSS_AT_CLK_FVAL 0x6c +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_DDR_I_HCLK_FVAL 0x6f +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_DDRMC_CH0_CLK_FVAL 0x70 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_DDRSS_GCC_DEBUG_CLK_FVAL 0x73 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_CPUSS_AHB_CLK_FVAL 0x74 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_CPUSS_GNOC_CLK_FVAL 0x75 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_XO_PCIE_LINK_CLK_FVAL 0x77 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_CPUSS_AT_CLK_FVAL 0x78 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_APSS_QDSS_TSCTR_CLK_FVAL 0x7a +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_APSS_QDSS_APB_CLK_FVAL 0x7b +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_CPUSS_GCC_DEBUG_CLK_FVAL 0x7c +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_NOC_BUS_TIMEOUT_EXTREF_CLK_FVAL 0x7d +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_RBCPR_CX_CLK_FVAL 0x7e +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_RBCPR_CX_AHB_CLK_FVAL 0x7f +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_RBCPR_MX_CLK_FVAL 0x80 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_RBCPR_MX_AHB_CLK_FVAL 0x81 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_QUSB2PHY_GCC_CLK_TEST_PRIM_FVAL 0x83 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_QUSB2PHY_GCC_CLK_TEST_SEC_FVAL 0x84 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_GP1_CLK_FVAL 0x85 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_GP2_CLK_FVAL 0x86 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_GP3_CLK_FVAL 0x87 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_ULTAUDIO_PCNOC_MPORT_CLK_FVAL 0x88 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_ULTAUDIO_PCNOC_SWAY_CLK_FVAL 0x89 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK_FVAL 0x8a +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CLK_FVAL 0x8b +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CLK_FVAL 0x8c +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK_FVAL 0x8d +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK_FVAL 0x8e +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK_FVAL 0x8f +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_ULTAUDIO_AVSYNC_XO_CLK_FVAL 0x90 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_ULTAUDIO_LPAIF_EXT_I2S_CLK_FVAL 0x91 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CLK_FVAL 0x92 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CLK_FVAL 0x93 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CLK_FVAL 0x94 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_PCIE_SLV_Q2A_AXI_CLK_FVAL 0x95 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_PCIE_SLV_AXI_CLK_FVAL 0x96 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_PCIE_MSTR_AXI_CLK_FVAL 0x97 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_PCIE_CFG_AHB_CLK_FVAL 0x98 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_PCIE_AUX_CLK_FVAL 0x99 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_PCIE_PIPE_CLK_FVAL 0x9a +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_PCIE_PIPE_CLK_FVAL 0x9b +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_PCIE_SLEEP_CLK_FVAL 0x9c +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_VDDCX_VS_CLK_FVAL 0x9d +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_VDDMX_VS_CLK_FVAL 0x9e +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_VDDA_VS_CLK_FVAL 0x9f +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_VS_CTRL_CLK_FVAL 0xa0 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_VS_CTRL_AHB_CLK_FVAL 0xa1 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_MSS_VS_CLK_FVAL 0xa2 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_SYS_NOC_HS_AXI_CLK_FVAL 0xa3 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_DDRSS_SYS_NOC_HS_AXI_CLK_FVAL 0xa4 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_SPMI_VGIS_CLK_FVAL 0xa6 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_NAV_MBIST_CLK_FVAL 0xa9 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_SLEEP_CLK_FVAL 0xaa +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_DCC_AHB_CLK_FVAL 0xab +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_IPA_2X_CLK_FVAL 0xac +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_IPA_CLK_FVAL 0xad +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_IPA_AHB_CLK_FVAL 0xae +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_IPA_XO_CLK_FVAL 0xaf +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_QPIC_CLK_FVAL 0xb1 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_QPIC_AHB_CLK_FVAL 0xb2 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_QPIC_SYSTEM_CLK_FVAL 0xb3 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_SPMI_FETCHER_CLK_FVAL 0xb4 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_SPMI_FETCHER_AHB_CLK_FVAL 0xb5 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_MSS_CFG_AHB_CLK_FVAL 0xb6 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_MSS_OFFLINE_AXI_CLK_FVAL 0xb7 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_MSS_CE_AXI_CLK_FVAL 0xb8 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_PCIE_RCHNG_PHY_CLK_FVAL 0xb9 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_MSS_TRIG_CLK_FVAL 0xba +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_MSS_AT_CLK_FVAL 0xbb +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_MSS_GPLL0_DIV_CLK_SRC_FVAL 0xbc +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_MSS_Q6SS_BOOT_GPLL0_CLK_SRC_FVAL 0xbd +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_MSS_SNOC_AXI_CLK_FVAL 0xbe +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_MSS_Q6VQ6_AXIM1_CLK_FVAL 0xbf +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_MSS_GCC_DEBUG_CLK_FVAL 0xc0 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_QREFS_VBG_CAL_CLK_FVAL 0xc1 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_NAV_GCC_DEBUG_CLK_FVAL 0xc2 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_CM_PHY_REFGEN1_CLK_FVAL 0xc5 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_ECC_CLK_FVAL 0xc6 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_ECC_CORE_CLK_FVAL 0xc7 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_ULTAUDIO_AHBFABRIC_EFABRIC_SPDM_CLK_FVAL 0xcc +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_AOSS_AT_CLK_FVAL 0xcd +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_QM_CFG_AHB_CLK_FVAL 0xce +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_AHB_PCIE_LINK_CLK_FVAL 0xcf +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_QM_CORE_CLK_FVAL 0xd0 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_DDRMC_CH1_CLK_FVAL 0xd1 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_DDRSS_MSS_MCDMA_CLK_FVAL 0xfa +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_PCIE20_PHY_AUX_CLK_FVAL 0xfc +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_NAV_SNOC_AXI_CLK_FVAL 0x105 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_EXT_PRI_I2S_FVAL 0x106 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_EXT_SEC_I2S_FVAL 0x107 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_EXT_AUX_I2S_FVAL 0x108 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_SYS_NOC_AXI_CLK_FVAL 0x109 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_SYS_NOC_QDSS_STM_AXI_CLK_FVAL 0x10a +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_SYS_NOC_CPUSS_AHB_CLK_FVAL 0x10b +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_SYS_NOC_AHB_CFG_CLK_FVAL 0x10c +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_PCIEPHY_DEBUG_CLK_FVAL 0x10d +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_USB3PHY_DEBUG_CLK_FVAL 0x10e +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_MSS_CE_NAV_BRIDGE_AXI_CLK_FVAL 0x10f +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_VDDMXC_VS_CLK_FVAL 0x110 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_RBCPR_MXC_CLK_FVAL 0x111 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_RBCPR_MXC_AHB_CLK_FVAL 0x112 +#define HWIO_GCC_DEBUG_CLK_CTL_MUX_SEL_GCC_TCSR_ACC_SERIAL_CLK_FVAL 0x113 + +#define HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00069004) +#define HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00069004) +#define HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00069004) +#define HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_RMSK 0x3fffff +#define HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_ATTR 0x3 +#define HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_IN \ + in_dword_masked(HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_ADDR, HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_RMSK) +#define HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_INM(m) \ + in_dword_masked(HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_ADDR, m) +#define HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_OUT(v) \ + out_dword(HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_ADDR,v) +#define HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_ADDR,m,v,HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_IN) +#define HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_CLR_CNT_BMSK 0x200000 +#define HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_CLR_CNT_SHFT 0x15 +#define HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_CLR_CNT_DISABLE_FVAL 0x0 +#define HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_CLR_CNT_ENABLE_FVAL 0x1 +#define HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_CNT_EN_BMSK 0x100000 +#define HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_CNT_EN_SHFT 0x14 +#define HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_CNT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_CNT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_XO_DIV4_TERM_CNT_BMSK 0xfffff +#define HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_XO_DIV4_TERM_CNT_SHFT 0x0 + +#define HWIO_GCC_CLOCK_FRQ_MEASURE_STATUS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00069008) +#define HWIO_GCC_CLOCK_FRQ_MEASURE_STATUS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00069008) +#define HWIO_GCC_CLOCK_FRQ_MEASURE_STATUS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00069008) +#define HWIO_GCC_CLOCK_FRQ_MEASURE_STATUS_RMSK 0x3ffffff +#define HWIO_GCC_CLOCK_FRQ_MEASURE_STATUS_ATTR 0x1 +#define HWIO_GCC_CLOCK_FRQ_MEASURE_STATUS_IN \ + in_dword_masked(HWIO_GCC_CLOCK_FRQ_MEASURE_STATUS_ADDR, HWIO_GCC_CLOCK_FRQ_MEASURE_STATUS_RMSK) +#define HWIO_GCC_CLOCK_FRQ_MEASURE_STATUS_INM(m) \ + in_dword_masked(HWIO_GCC_CLOCK_FRQ_MEASURE_STATUS_ADDR, m) +#define HWIO_GCC_CLOCK_FRQ_MEASURE_STATUS_XO_DIV4_CNT_DONE_BMSK 0x2000000 +#define HWIO_GCC_CLOCK_FRQ_MEASURE_STATUS_XO_DIV4_CNT_DONE_SHFT 0x19 +#define HWIO_GCC_CLOCK_FRQ_MEASURE_STATUS_MEASURE_CNT_BMSK 0x1ffffff +#define HWIO_GCC_CLOCK_FRQ_MEASURE_STATUS_MEASURE_CNT_SHFT 0x0 + +#define HWIO_GCC_PLLTEST_PAD_CFG_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006900c) +#define HWIO_GCC_PLLTEST_PAD_CFG_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006900c) +#define HWIO_GCC_PLLTEST_PAD_CFG_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006900c) +#define HWIO_GCC_PLLTEST_PAD_CFG_RMSK 0x3ffffff +#define HWIO_GCC_PLLTEST_PAD_CFG_ATTR 0x3 +#define HWIO_GCC_PLLTEST_PAD_CFG_IN \ + in_dword_masked(HWIO_GCC_PLLTEST_PAD_CFG_ADDR, HWIO_GCC_PLLTEST_PAD_CFG_RMSK) +#define HWIO_GCC_PLLTEST_PAD_CFG_INM(m) \ + in_dword_masked(HWIO_GCC_PLLTEST_PAD_CFG_ADDR, m) +#define HWIO_GCC_PLLTEST_PAD_CFG_OUT(v) \ + out_dword(HWIO_GCC_PLLTEST_PAD_CFG_ADDR,v) +#define HWIO_GCC_PLLTEST_PAD_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PLLTEST_PAD_CFG_ADDR,m,v,HWIO_GCC_PLLTEST_PAD_CFG_IN) +#define HWIO_GCC_PLLTEST_PAD_CFG_CORE_PLL_B_BMSK 0x3000000 +#define HWIO_GCC_PLLTEST_PAD_CFG_CORE_PLL_B_SHFT 0x18 +#define HWIO_GCC_PLLTEST_PAD_CFG_CORE_PLL_B_NONE_FVAL 0x0 +#define HWIO_GCC_PLLTEST_PAD_CFG_CORE_PLL_B_PULLDOWN_FVAL 0x1 +#define HWIO_GCC_PLLTEST_PAD_CFG_CORE_PLL_B_KEEP_FVAL 0x2 +#define HWIO_GCC_PLLTEST_PAD_CFG_CORE_PLL_B_PULLUP_FVAL 0x3 +#define HWIO_GCC_PLLTEST_PAD_CFG_RESERVE_BITS23_20_BMSK 0xf00000 +#define HWIO_GCC_PLLTEST_PAD_CFG_RESERVE_BITS23_20_SHFT 0x14 +#define HWIO_GCC_PLLTEST_PAD_CFG_CORE_PLL_EN_BMSK 0x80000 +#define HWIO_GCC_PLLTEST_PAD_CFG_CORE_PLL_EN_SHFT 0x13 +#define HWIO_GCC_PLLTEST_PAD_CFG_CORE_PLL_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_PLLTEST_PAD_CFG_CORE_PLL_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_PLLTEST_PAD_CFG_RESERVE_BIT18_BMSK 0x40000 +#define HWIO_GCC_PLLTEST_PAD_CFG_RESERVE_BIT18_SHFT 0x12 +#define HWIO_GCC_PLLTEST_PAD_CFG_CORE_OE_BMSK 0x20000 +#define HWIO_GCC_PLLTEST_PAD_CFG_CORE_OE_SHFT 0x11 +#define HWIO_GCC_PLLTEST_PAD_CFG_CORE_OE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PLLTEST_PAD_CFG_CORE_OE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PLLTEST_PAD_CFG_RESERVE_BIT16_BMSK 0x10000 +#define HWIO_GCC_PLLTEST_PAD_CFG_RESERVE_BIT16_SHFT 0x10 +#define HWIO_GCC_PLLTEST_PAD_CFG_CORE_IE_BMSK 0x8000 +#define HWIO_GCC_PLLTEST_PAD_CFG_CORE_IE_SHFT 0xf +#define HWIO_GCC_PLLTEST_PAD_CFG_CORE_IE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PLLTEST_PAD_CFG_CORE_IE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PLLTEST_PAD_CFG_HIHYS_EN_BMSK 0x4000 +#define HWIO_GCC_PLLTEST_PAD_CFG_HIHYS_EN_SHFT 0xe +#define HWIO_GCC_PLLTEST_PAD_CFG_HIHYS_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_PLLTEST_PAD_CFG_HIHYS_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_PLLTEST_PAD_CFG_HDRIVE_BMSK 0x3800 +#define HWIO_GCC_PLLTEST_PAD_CFG_HDRIVE_SHFT 0xb +#define HWIO_GCC_PLLTEST_PAD_CFG_HDRIVE_DRIVE_150MV_FVAL 0x0 +#define HWIO_GCC_PLLTEST_PAD_CFG_HDRIVE_DRIVE_200MV_FVAL 0x1 +#define HWIO_GCC_PLLTEST_PAD_CFG_HDRIVE_DRIVE_250MV_FVAL 0x2 +#define HWIO_GCC_PLLTEST_PAD_CFG_HDRIVE_DRIVE_300MV_FVAL 0x3 +#define HWIO_GCC_PLLTEST_PAD_CFG_HDRIVE_NEW_A_FVAL 0x4 +#define HWIO_GCC_PLLTEST_PAD_CFG_HDRIVE_NEW_B_FVAL 0x5 +#define HWIO_GCC_PLLTEST_PAD_CFG_HDRIVE_NEW_C_FVAL 0x6 +#define HWIO_GCC_PLLTEST_PAD_CFG_HDRIVE_NEW_D_FVAL 0x7 +#define HWIO_GCC_PLLTEST_PAD_CFG_RESERVE_BITS10_5_BMSK 0x7e0 +#define HWIO_GCC_PLLTEST_PAD_CFG_RESERVE_BITS10_5_SHFT 0x5 +#define HWIO_GCC_PLLTEST_PAD_CFG_OUT_SEL_BMSK 0x1f +#define HWIO_GCC_PLLTEST_PAD_CFG_OUT_SEL_SHFT 0x0 +#define HWIO_GCC_PLLTEST_PAD_CFG_OUT_SEL_GCC_DEBUG_CLK_FVAL 0x0 +#define HWIO_GCC_PLLTEST_PAD_CFG_OUT_SEL_GPLL0_OUT_TEST_FVAL 0x1 +#define HWIO_GCC_PLLTEST_PAD_CFG_OUT_SEL_GPLL1_OUT_TEST_FVAL 0x2 +#define HWIO_GCC_PLLTEST_PAD_CFG_OUT_SEL_GPLL2_OUT_TEST_FVAL 0x3 +#define HWIO_GCC_PLLTEST_PAD_CFG_OUT_SEL_GPLL3_OUT_TEST_FVAL 0x4 +#define HWIO_GCC_PLLTEST_PAD_CFG_OUT_SEL_GPLL4_OUT_TEST_FVAL 0x5 +#define HWIO_GCC_PLLTEST_PAD_CFG_OUT_SEL_GPLL5_OUT_TEST_FVAL 0x6 +#define HWIO_GCC_PLLTEST_PAD_CFG_OUT_SEL_CPUSS_GCC_PLL_TEST_CLK_FVAL 0x8 +#define HWIO_GCC_PLLTEST_PAD_CFG_OUT_SEL_MSS_GCC_PLL_TEST_CLK_FVAL 0xa +#define HWIO_GCC_PLLTEST_PAD_CFG_OUT_SEL_USB30_LPC_PLL_TEST_SE_FVAL 0xb +#define HWIO_GCC_PLLTEST_PAD_CFG_OUT_SEL_NAV_GCC_PLL_TEST_CLK_FVAL 0xe +#define HWIO_GCC_PLLTEST_PAD_CFG_OUT_SEL_DDRSS_GCC_PLL_TEST_CLK_FVAL 0x11 +#define HWIO_GCC_PLLTEST_PAD_CFG_OUT_SEL_MSS_GCC_Q6_LDO_NMO_OUT_FVAL 0x12 +#define HWIO_GCC_PLLTEST_PAD_CFG_OUT_SEL_MSS_GCC_VQ6_LDO_NMO_OUT_FVAL 0x13 +#define HWIO_GCC_PLLTEST_PAD_CFG_OUT_SEL_QREFS_GCC_CXO_RXTAP1_CLK_TEST_SE_FVAL 0x18 +#define HWIO_GCC_PLLTEST_PAD_CFG_OUT_SEL_QREFS_GCC_CXO2_RXTAP0_CLK_TEST_SE_FVAL 0x19 +#define HWIO_GCC_PLLTEST_PAD_CFG_OUT_SEL_QREFS_GCC_CXO_RXTAP2_CLK_TEST_SE_FVAL 0x1a +#define HWIO_GCC_PLLTEST_PAD_CFG_OUT_SEL_QREFS_GCC_CXO_RXTAP3_CLK_TEST_SE_FVAL 0x1b +#define HWIO_GCC_PLLTEST_PAD_CFG_OUT_SEL_QREFS_GCC_CXO_RX0_CLK_TEST_SE_FVAL 0x1c +#define HWIO_GCC_PLLTEST_PAD_CFG_OUT_SEL_AOSS_GCC_PLL_TEST_CLK_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_INTERFACE_FSM_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000300) +#define HWIO_GCC_RPMH_SYS_NOC_INTERFACE_FSM_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000300) +#define HWIO_GCC_RPMH_SYS_NOC_INTERFACE_FSM_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000300) +#define HWIO_GCC_RPMH_SYS_NOC_INTERFACE_FSM_RMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_INTERFACE_FSM_ATTR 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_INTERFACE_FSM_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_INTERFACE_FSM_ADDR, HWIO_GCC_RPMH_SYS_NOC_INTERFACE_FSM_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_INTERFACE_FSM_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_INTERFACE_FSM_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_INTERFACE_FSM_FSM_STATE_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_INTERFACE_FSM_FSM_STATE_SHFT 0x0 + +#define HWIO_GCC_RPMH_CNOC_INTERFACE_FSM_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00001300) +#define HWIO_GCC_RPMH_CNOC_INTERFACE_FSM_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00001300) +#define HWIO_GCC_RPMH_CNOC_INTERFACE_FSM_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00001300) +#define HWIO_GCC_RPMH_CNOC_INTERFACE_FSM_RMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_INTERFACE_FSM_ATTR 0x1 +#define HWIO_GCC_RPMH_CNOC_INTERFACE_FSM_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_INTERFACE_FSM_ADDR, HWIO_GCC_RPMH_CNOC_INTERFACE_FSM_RMSK) +#define HWIO_GCC_RPMH_CNOC_INTERFACE_FSM_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_INTERFACE_FSM_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_INTERFACE_FSM_FSM_STATE_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_INTERFACE_FSM_FSM_STATE_SHFT 0x0 + +#define HWIO_GCC_RPMH_SHUB_INTERFACE_FSM_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00004300) +#define HWIO_GCC_RPMH_SHUB_INTERFACE_FSM_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004300) +#define HWIO_GCC_RPMH_SHUB_INTERFACE_FSM_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004300) +#define HWIO_GCC_RPMH_SHUB_INTERFACE_FSM_RMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_INTERFACE_FSM_ATTR 0x1 +#define HWIO_GCC_RPMH_SHUB_INTERFACE_FSM_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_INTERFACE_FSM_ADDR, HWIO_GCC_RPMH_SHUB_INTERFACE_FSM_RMSK) +#define HWIO_GCC_RPMH_SHUB_INTERFACE_FSM_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_INTERFACE_FSM_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_INTERFACE_FSM_FSM_STATE_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_INTERFACE_FSM_FSM_STATE_SHFT 0x0 + +#define HWIO_GCC_RPMH_CE_INTERFACE_FSM_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001c300) +#define HWIO_GCC_RPMH_CE_INTERFACE_FSM_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001c300) +#define HWIO_GCC_RPMH_CE_INTERFACE_FSM_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001c300) +#define HWIO_GCC_RPMH_CE_INTERFACE_FSM_RMSK 0x1f +#define HWIO_GCC_RPMH_CE_INTERFACE_FSM_ATTR 0x1 +#define HWIO_GCC_RPMH_CE_INTERFACE_FSM_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_INTERFACE_FSM_ADDR, HWIO_GCC_RPMH_CE_INTERFACE_FSM_RMSK) +#define HWIO_GCC_RPMH_CE_INTERFACE_FSM_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_INTERFACE_FSM_ADDR, m) +#define HWIO_GCC_RPMH_CE_INTERFACE_FSM_FSM_STATE_BMSK 0x1f +#define HWIO_GCC_RPMH_CE_INTERFACE_FSM_FSM_STATE_SHFT 0x0 + +#define HWIO_GCC_RPMH_SHRM_INTERFACE_FSM_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f604) +#define HWIO_GCC_RPMH_SHRM_INTERFACE_FSM_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f604) +#define HWIO_GCC_RPMH_SHRM_INTERFACE_FSM_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f604) +#define HWIO_GCC_RPMH_SHRM_INTERFACE_FSM_RMSK 0x1f +#define HWIO_GCC_RPMH_SHRM_INTERFACE_FSM_ATTR 0x1 +#define HWIO_GCC_RPMH_SHRM_INTERFACE_FSM_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_INTERFACE_FSM_ADDR, HWIO_GCC_RPMH_SHRM_INTERFACE_FSM_RMSK) +#define HWIO_GCC_RPMH_SHRM_INTERFACE_FSM_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_INTERFACE_FSM_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_INTERFACE_FSM_FSM_STATE_BMSK 0x1f +#define HWIO_GCC_RPMH_SHRM_INTERFACE_FSM_FSM_STATE_SHFT 0x0 + +#define HWIO_GCC_RPMH_IPA_INTERFACE_FSM_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038300) +#define HWIO_GCC_RPMH_IPA_INTERFACE_FSM_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038300) +#define HWIO_GCC_RPMH_IPA_INTERFACE_FSM_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038300) +#define HWIO_GCC_RPMH_IPA_INTERFACE_FSM_RMSK 0x1f +#define HWIO_GCC_RPMH_IPA_INTERFACE_FSM_ATTR 0x1 +#define HWIO_GCC_RPMH_IPA_INTERFACE_FSM_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_INTERFACE_FSM_ADDR, HWIO_GCC_RPMH_IPA_INTERFACE_FSM_RMSK) +#define HWIO_GCC_RPMH_IPA_INTERFACE_FSM_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_INTERFACE_FSM_ADDR, m) +#define HWIO_GCC_RPMH_IPA_INTERFACE_FSM_FSM_STATE_BMSK 0x1f +#define HWIO_GCC_RPMH_IPA_INTERFACE_FSM_FSM_STATE_SHFT 0x0 + +#define HWIO_GCC_RPMH_QPIC_INTERFACE_FSM_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00039300) +#define HWIO_GCC_RPMH_QPIC_INTERFACE_FSM_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00039300) +#define HWIO_GCC_RPMH_QPIC_INTERFACE_FSM_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00039300) +#define HWIO_GCC_RPMH_QPIC_INTERFACE_FSM_RMSK 0x1f +#define HWIO_GCC_RPMH_QPIC_INTERFACE_FSM_ATTR 0x1 +#define HWIO_GCC_RPMH_QPIC_INTERFACE_FSM_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_INTERFACE_FSM_ADDR, HWIO_GCC_RPMH_QPIC_INTERFACE_FSM_RMSK) +#define HWIO_GCC_RPMH_QPIC_INTERFACE_FSM_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_INTERFACE_FSM_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_INTERFACE_FSM_FSM_STATE_BMSK 0x1f +#define HWIO_GCC_RPMH_QPIC_INTERFACE_FSM_FSM_STATE_SHFT 0x0 + +#define HWIO_GCC_RPMH_PKA_INTERFACE_FSM_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00040300) +#define HWIO_GCC_RPMH_PKA_INTERFACE_FSM_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00040300) +#define HWIO_GCC_RPMH_PKA_INTERFACE_FSM_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00040300) +#define HWIO_GCC_RPMH_PKA_INTERFACE_FSM_RMSK 0x1f +#define HWIO_GCC_RPMH_PKA_INTERFACE_FSM_ATTR 0x1 +#define HWIO_GCC_RPMH_PKA_INTERFACE_FSM_IN \ + in_dword_masked(HWIO_GCC_RPMH_PKA_INTERFACE_FSM_ADDR, HWIO_GCC_RPMH_PKA_INTERFACE_FSM_RMSK) +#define HWIO_GCC_RPMH_PKA_INTERFACE_FSM_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PKA_INTERFACE_FSM_ADDR, m) +#define HWIO_GCC_RPMH_PKA_INTERFACE_FSM_FSM_STATE_BMSK 0x1f +#define HWIO_GCC_RPMH_PKA_INTERFACE_FSM_FSM_STATE_SHFT 0x0 + +#define HWIO_GCC_RPMH_DDRMC_INTERFACE_FSM_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001f600) +#define HWIO_GCC_RPMH_DDRMC_INTERFACE_FSM_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001f600) +#define HWIO_GCC_RPMH_DDRMC_INTERFACE_FSM_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001f600) +#define HWIO_GCC_RPMH_DDRMC_INTERFACE_FSM_RMSK 0x1f +#define HWIO_GCC_RPMH_DDRMC_INTERFACE_FSM_ATTR 0x1 +#define HWIO_GCC_RPMH_DDRMC_INTERFACE_FSM_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_INTERFACE_FSM_ADDR, HWIO_GCC_RPMH_DDRMC_INTERFACE_FSM_RMSK) +#define HWIO_GCC_RPMH_DDRMC_INTERFACE_FSM_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_INTERFACE_FSM_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_INTERFACE_FSM_FSM_STATE_BMSK 0x1f +#define HWIO_GCC_RPMH_DDRMC_INTERFACE_FSM_FSM_STATE_SHFT 0x0 + +#define HWIO_GCC_USB_BOOT_CLOCK_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006a000) +#define HWIO_GCC_USB_BOOT_CLOCK_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006a000) +#define HWIO_GCC_USB_BOOT_CLOCK_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006a000) +#define HWIO_GCC_USB_BOOT_CLOCK_CTL_RMSK 0x1 +#define HWIO_GCC_USB_BOOT_CLOCK_CTL_ATTR 0x3 +#define HWIO_GCC_USB_BOOT_CLOCK_CTL_IN \ + in_dword_masked(HWIO_GCC_USB_BOOT_CLOCK_CTL_ADDR, HWIO_GCC_USB_BOOT_CLOCK_CTL_RMSK) +#define HWIO_GCC_USB_BOOT_CLOCK_CTL_INM(m) \ + in_dword_masked(HWIO_GCC_USB_BOOT_CLOCK_CTL_ADDR, m) +#define HWIO_GCC_USB_BOOT_CLOCK_CTL_OUT(v) \ + out_dword(HWIO_GCC_USB_BOOT_CLOCK_CTL_ADDR,v) +#define HWIO_GCC_USB_BOOT_CLOCK_CTL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB_BOOT_CLOCK_CTL_ADDR,m,v,HWIO_GCC_USB_BOOT_CLOCK_CTL_IN) +#define HWIO_GCC_USB_BOOT_CLOCK_CTL_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_USB_BOOT_CLOCK_CTL_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_USB_BOOT_CLOCK_CTL_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB_BOOT_CLOCK_CTL_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_BOOT_CLOCK_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006b000) +#define HWIO_GCC_PCIE_BOOT_CLOCK_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006b000) +#define HWIO_GCC_PCIE_BOOT_CLOCK_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006b000) +#define HWIO_GCC_PCIE_BOOT_CLOCK_CTL_RMSK 0x1 +#define HWIO_GCC_PCIE_BOOT_CLOCK_CTL_ATTR 0x3 +#define HWIO_GCC_PCIE_BOOT_CLOCK_CTL_IN \ + in_dword_masked(HWIO_GCC_PCIE_BOOT_CLOCK_CTL_ADDR, HWIO_GCC_PCIE_BOOT_CLOCK_CTL_RMSK) +#define HWIO_GCC_PCIE_BOOT_CLOCK_CTL_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_BOOT_CLOCK_CTL_ADDR, m) +#define HWIO_GCC_PCIE_BOOT_CLOCK_CTL_OUT(v) \ + out_dword(HWIO_GCC_PCIE_BOOT_CLOCK_CTL_ADDR,v) +#define HWIO_GCC_PCIE_BOOT_CLOCK_CTL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_BOOT_CLOCK_CTL_ADDR,m,v,HWIO_GCC_PCIE_BOOT_CLOCK_CTL_IN) +#define HWIO_GCC_PCIE_BOOT_CLOCK_CTL_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_PCIE_BOOT_CLOCK_CTL_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_PCIE_BOOT_CLOCK_CTL_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_BOOT_CLOCK_CTL_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TIC_MODE_APCS_BOOT_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006c000) +#define HWIO_GCC_TIC_MODE_APCS_BOOT_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006c000) +#define HWIO_GCC_TIC_MODE_APCS_BOOT_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006c000) +#define HWIO_GCC_TIC_MODE_APCS_BOOT_RMSK 0x1 +#define HWIO_GCC_TIC_MODE_APCS_BOOT_ATTR 0x3 +#define HWIO_GCC_TIC_MODE_APCS_BOOT_IN \ + in_dword_masked(HWIO_GCC_TIC_MODE_APCS_BOOT_ADDR, HWIO_GCC_TIC_MODE_APCS_BOOT_RMSK) +#define HWIO_GCC_TIC_MODE_APCS_BOOT_INM(m) \ + in_dword_masked(HWIO_GCC_TIC_MODE_APCS_BOOT_ADDR, m) +#define HWIO_GCC_TIC_MODE_APCS_BOOT_OUT(v) \ + out_dword(HWIO_GCC_TIC_MODE_APCS_BOOT_ADDR,v) +#define HWIO_GCC_TIC_MODE_APCS_BOOT_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TIC_MODE_APCS_BOOT_ADDR,m,v,HWIO_GCC_TIC_MODE_APCS_BOOT_IN) +#define HWIO_GCC_TIC_MODE_APCS_BOOT_APCS_BOOT_IN_TIC_MODE_BMSK 0x1 +#define HWIO_GCC_TIC_MODE_APCS_BOOT_APCS_BOOT_IN_TIC_MODE_SHFT 0x0 +#define HWIO_GCC_TIC_MODE_APCS_BOOT_APCS_BOOT_IN_TIC_MODE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TIC_MODE_APCS_BOOT_APCS_BOOT_IN_TIC_MODE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_IPA_GDSC_OVRD_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006d000) +#define HWIO_GCC_IPA_GDSC_OVRD_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006d000) +#define HWIO_GCC_IPA_GDSC_OVRD_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006d000) +#define HWIO_GCC_IPA_GDSC_OVRD_RMSK 0x3 +#define HWIO_GCC_IPA_GDSC_OVRD_ATTR 0x3 +#define HWIO_GCC_IPA_GDSC_OVRD_IN \ + in_dword_masked(HWIO_GCC_IPA_GDSC_OVRD_ADDR, HWIO_GCC_IPA_GDSC_OVRD_RMSK) +#define HWIO_GCC_IPA_GDSC_OVRD_INM(m) \ + in_dword_masked(HWIO_GCC_IPA_GDSC_OVRD_ADDR, m) +#define HWIO_GCC_IPA_GDSC_OVRD_OUT(v) \ + out_dword(HWIO_GCC_IPA_GDSC_OVRD_ADDR,v) +#define HWIO_GCC_IPA_GDSC_OVRD_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_IPA_GDSC_OVRD_ADDR,m,v,HWIO_GCC_IPA_GDSC_OVRD_IN) +#define HWIO_GCC_IPA_GDSC_OVRD_SW_OVERRIDE_BMSK 0x2 +#define HWIO_GCC_IPA_GDSC_OVRD_SW_OVERRIDE_SHFT 0x1 +#define HWIO_GCC_IPA_GDSC_OVRD_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_GDSC_OVRD_SW_OVERRIDE_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPA_GDSC_OVRD_RETAIN_FF_ENABLE_BMSK 0x1 +#define HWIO_GCC_IPA_GDSC_OVRD_RETAIN_FF_ENABLE_SHFT 0x0 +#define HWIO_GCC_IPA_GDSC_OVRD_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_GDSC_OVRD_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_USB30_PRIM_GDSC_OVRD_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006d004) +#define HWIO_GCC_USB30_PRIM_GDSC_OVRD_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006d004) +#define HWIO_GCC_USB30_PRIM_GDSC_OVRD_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006d004) +#define HWIO_GCC_USB30_PRIM_GDSC_OVRD_RMSK 0x3 +#define HWIO_GCC_USB30_PRIM_GDSC_OVRD_ATTR 0x3 +#define HWIO_GCC_USB30_PRIM_GDSC_OVRD_IN \ + in_dword_masked(HWIO_GCC_USB30_PRIM_GDSC_OVRD_ADDR, HWIO_GCC_USB30_PRIM_GDSC_OVRD_RMSK) +#define HWIO_GCC_USB30_PRIM_GDSC_OVRD_INM(m) \ + in_dword_masked(HWIO_GCC_USB30_PRIM_GDSC_OVRD_ADDR, m) +#define HWIO_GCC_USB30_PRIM_GDSC_OVRD_OUT(v) \ + out_dword(HWIO_GCC_USB30_PRIM_GDSC_OVRD_ADDR,v) +#define HWIO_GCC_USB30_PRIM_GDSC_OVRD_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB30_PRIM_GDSC_OVRD_ADDR,m,v,HWIO_GCC_USB30_PRIM_GDSC_OVRD_IN) +#define HWIO_GCC_USB30_PRIM_GDSC_OVRD_SW_OVERRIDE_BMSK 0x2 +#define HWIO_GCC_USB30_PRIM_GDSC_OVRD_SW_OVERRIDE_SHFT 0x1 +#define HWIO_GCC_USB30_PRIM_GDSC_OVRD_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_PRIM_GDSC_OVRD_SW_OVERRIDE_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB30_PRIM_GDSC_OVRD_RETAIN_FF_ENABLE_BMSK 0x1 +#define HWIO_GCC_USB30_PRIM_GDSC_OVRD_RETAIN_FF_ENABLE_SHFT 0x0 +#define HWIO_GCC_USB30_PRIM_GDSC_OVRD_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_PRIM_GDSC_OVRD_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_0_GDSC_OVRD_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006d008) +#define HWIO_GCC_PCIE_0_GDSC_OVRD_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006d008) +#define HWIO_GCC_PCIE_0_GDSC_OVRD_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006d008) +#define HWIO_GCC_PCIE_0_GDSC_OVRD_RMSK 0x3 +#define HWIO_GCC_PCIE_0_GDSC_OVRD_ATTR 0x3 +#define HWIO_GCC_PCIE_0_GDSC_OVRD_IN \ + in_dword_masked(HWIO_GCC_PCIE_0_GDSC_OVRD_ADDR, HWIO_GCC_PCIE_0_GDSC_OVRD_RMSK) +#define HWIO_GCC_PCIE_0_GDSC_OVRD_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_0_GDSC_OVRD_ADDR, m) +#define HWIO_GCC_PCIE_0_GDSC_OVRD_OUT(v) \ + out_dword(HWIO_GCC_PCIE_0_GDSC_OVRD_ADDR,v) +#define HWIO_GCC_PCIE_0_GDSC_OVRD_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_0_GDSC_OVRD_ADDR,m,v,HWIO_GCC_PCIE_0_GDSC_OVRD_IN) +#define HWIO_GCC_PCIE_0_GDSC_OVRD_SW_OVERRIDE_BMSK 0x2 +#define HWIO_GCC_PCIE_0_GDSC_OVRD_SW_OVERRIDE_SHFT 0x1 +#define HWIO_GCC_PCIE_0_GDSC_OVRD_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_GDSC_OVRD_SW_OVERRIDE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_GDSC_OVRD_RETAIN_FF_ENABLE_BMSK 0x1 +#define HWIO_GCC_PCIE_0_GDSC_OVRD_RETAIN_FF_ENABLE_SHFT 0x0 +#define HWIO_GCC_PCIE_0_GDSC_OVRD_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_GDSC_OVRD_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_DDRSS_GDSC_OVRD_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006d010) +#define HWIO_GCC_DDRSS_GDSC_OVRD_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006d010) +#define HWIO_GCC_DDRSS_GDSC_OVRD_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006d010) +#define HWIO_GCC_DDRSS_GDSC_OVRD_RMSK 0x3 +#define HWIO_GCC_DDRSS_GDSC_OVRD_ATTR 0x3 +#define HWIO_GCC_DDRSS_GDSC_OVRD_IN \ + in_dword_masked(HWIO_GCC_DDRSS_GDSC_OVRD_ADDR, HWIO_GCC_DDRSS_GDSC_OVRD_RMSK) +#define HWIO_GCC_DDRSS_GDSC_OVRD_INM(m) \ + in_dword_masked(HWIO_GCC_DDRSS_GDSC_OVRD_ADDR, m) +#define HWIO_GCC_DDRSS_GDSC_OVRD_OUT(v) \ + out_dword(HWIO_GCC_DDRSS_GDSC_OVRD_ADDR,v) +#define HWIO_GCC_DDRSS_GDSC_OVRD_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DDRSS_GDSC_OVRD_ADDR,m,v,HWIO_GCC_DDRSS_GDSC_OVRD_IN) +#define HWIO_GCC_DDRSS_GDSC_OVRD_SW_OVERRIDE_BMSK 0x2 +#define HWIO_GCC_DDRSS_GDSC_OVRD_SW_OVERRIDE_SHFT 0x1 +#define HWIO_GCC_DDRSS_GDSC_OVRD_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_GDSC_OVRD_SW_OVERRIDE_ENABLE_FVAL 0x1 +#define HWIO_GCC_DDRSS_GDSC_OVRD_RETAIN_FF_ENABLE_BMSK 0x1 +#define HWIO_GCC_DDRSS_GDSC_OVRD_RETAIN_FF_ENABLE_SHFT 0x0 +#define HWIO_GCC_DDRSS_GDSC_OVRD_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_GDSC_OVRD_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GDS_HW_CTRL_SPARE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006d014) +#define HWIO_GCC_GDS_HW_CTRL_SPARE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006d014) +#define HWIO_GCC_GDS_HW_CTRL_SPARE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006d014) +#define HWIO_GCC_GDS_HW_CTRL_SPARE_RMSK 0xff +#define HWIO_GCC_GDS_HW_CTRL_SPARE_ATTR 0x3 +#define HWIO_GCC_GDS_HW_CTRL_SPARE_IN \ + in_dword_masked(HWIO_GCC_GDS_HW_CTRL_SPARE_ADDR, HWIO_GCC_GDS_HW_CTRL_SPARE_RMSK) +#define HWIO_GCC_GDS_HW_CTRL_SPARE_INM(m) \ + in_dword_masked(HWIO_GCC_GDS_HW_CTRL_SPARE_ADDR, m) +#define HWIO_GCC_GDS_HW_CTRL_SPARE_OUT(v) \ + out_dword(HWIO_GCC_GDS_HW_CTRL_SPARE_ADDR,v) +#define HWIO_GCC_GDS_HW_CTRL_SPARE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GDS_HW_CTRL_SPARE_ADDR,m,v,HWIO_GCC_GDS_HW_CTRL_SPARE_IN) +#define HWIO_GCC_GDS_HW_CTRL_SPARE_SPARE_BMSK 0xff +#define HWIO_GCC_GDS_HW_CTRL_SPARE_SPARE_SHFT 0x0 + +#define HWIO_GCC_ARC_CLK_DIS_ACK_OVRD_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00001104) +#define HWIO_GCC_ARC_CLK_DIS_ACK_OVRD_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00001104) +#define HWIO_GCC_ARC_CLK_DIS_ACK_OVRD_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00001104) +#define HWIO_GCC_ARC_CLK_DIS_ACK_OVRD_RMSK 0x1f001f +#define HWIO_GCC_ARC_CLK_DIS_ACK_OVRD_ATTR 0x3 +#define HWIO_GCC_ARC_CLK_DIS_ACK_OVRD_IN \ + in_dword_masked(HWIO_GCC_ARC_CLK_DIS_ACK_OVRD_ADDR, HWIO_GCC_ARC_CLK_DIS_ACK_OVRD_RMSK) +#define HWIO_GCC_ARC_CLK_DIS_ACK_OVRD_INM(m) \ + in_dword_masked(HWIO_GCC_ARC_CLK_DIS_ACK_OVRD_ADDR, m) +#define HWIO_GCC_ARC_CLK_DIS_ACK_OVRD_OUT(v) \ + out_dword(HWIO_GCC_ARC_CLK_DIS_ACK_OVRD_ADDR,v) +#define HWIO_GCC_ARC_CLK_DIS_ACK_OVRD_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ARC_CLK_DIS_ACK_OVRD_ADDR,m,v,HWIO_GCC_ARC_CLK_DIS_ACK_OVRD_IN) +#define HWIO_GCC_ARC_CLK_DIS_ACK_OVRD_DDR_PHY_CX_CLK_DIS_ACK_OVRD_BMSK 0x100000 +#define HWIO_GCC_ARC_CLK_DIS_ACK_OVRD_DDR_PHY_CX_CLK_DIS_ACK_OVRD_SHFT 0x14 +#define HWIO_GCC_ARC_CLK_DIS_ACK_OVRD_DDR_PHY_CX_CLK_DIS_ACK_OVRD_DISABLE_FVAL 0x0 +#define HWIO_GCC_ARC_CLK_DIS_ACK_OVRD_DDR_PHY_CX_CLK_DIS_ACK_OVRD_ENABLE_FVAL 0x1 +#define HWIO_GCC_ARC_CLK_DIS_ACK_OVRD_MSS_CX_CLK_DIS_ACK_OVRD_BMSK 0x80000 +#define HWIO_GCC_ARC_CLK_DIS_ACK_OVRD_MSS_CX_CLK_DIS_ACK_OVRD_SHFT 0x13 +#define HWIO_GCC_ARC_CLK_DIS_ACK_OVRD_MSS_CX_CLK_DIS_ACK_OVRD_DISABLE_FVAL 0x0 +#define HWIO_GCC_ARC_CLK_DIS_ACK_OVRD_MSS_CX_CLK_DIS_ACK_OVRD_ENABLE_FVAL 0x1 +#define HWIO_GCC_ARC_CLK_DIS_ACK_OVRD_APSS_CX_CLK_DIS_ACK_OVRD_BMSK 0x40000 +#define HWIO_GCC_ARC_CLK_DIS_ACK_OVRD_APSS_CX_CLK_DIS_ACK_OVRD_SHFT 0x12 +#define HWIO_GCC_ARC_CLK_DIS_ACK_OVRD_APSS_CX_CLK_DIS_ACK_OVRD_DISABLE_FVAL 0x0 +#define HWIO_GCC_ARC_CLK_DIS_ACK_OVRD_APSS_CX_CLK_DIS_ACK_OVRD_ENABLE_FVAL 0x1 +#define HWIO_GCC_ARC_CLK_DIS_ACK_OVRD_NAV_CX_CLK_DIS_ACK_OVRD_BMSK 0x20000 +#define HWIO_GCC_ARC_CLK_DIS_ACK_OVRD_NAV_CX_CLK_DIS_ACK_OVRD_SHFT 0x11 +#define HWIO_GCC_ARC_CLK_DIS_ACK_OVRD_NAV_CX_CLK_DIS_ACK_OVRD_DISABLE_FVAL 0x0 +#define HWIO_GCC_ARC_CLK_DIS_ACK_OVRD_NAV_CX_CLK_DIS_ACK_OVRD_ENABLE_FVAL 0x1 +#define HWIO_GCC_ARC_CLK_DIS_ACK_OVRD_GCC_CX_CLK_DIS_ACK_OVRD_BMSK 0x10000 +#define HWIO_GCC_ARC_CLK_DIS_ACK_OVRD_GCC_CX_CLK_DIS_ACK_OVRD_SHFT 0x10 +#define HWIO_GCC_ARC_CLK_DIS_ACK_OVRD_GCC_CX_CLK_DIS_ACK_OVRD_DISABLE_FVAL 0x0 +#define HWIO_GCC_ARC_CLK_DIS_ACK_OVRD_GCC_CX_CLK_DIS_ACK_OVRD_ENABLE_FVAL 0x1 +#define HWIO_GCC_ARC_CLK_DIS_ACK_OVRD_DDR_PHY_MX_CLK_DIS_ACK_OVRD_BMSK 0x10 +#define HWIO_GCC_ARC_CLK_DIS_ACK_OVRD_DDR_PHY_MX_CLK_DIS_ACK_OVRD_SHFT 0x4 +#define HWIO_GCC_ARC_CLK_DIS_ACK_OVRD_DDR_PHY_MX_CLK_DIS_ACK_OVRD_DISABLE_FVAL 0x0 +#define HWIO_GCC_ARC_CLK_DIS_ACK_OVRD_DDR_PHY_MX_CLK_DIS_ACK_OVRD_ENABLE_FVAL 0x1 +#define HWIO_GCC_ARC_CLK_DIS_ACK_OVRD_MSS_MX_CLK_DIS_ACK_OVRD_BMSK 0x8 +#define HWIO_GCC_ARC_CLK_DIS_ACK_OVRD_MSS_MX_CLK_DIS_ACK_OVRD_SHFT 0x3 +#define HWIO_GCC_ARC_CLK_DIS_ACK_OVRD_MSS_MX_CLK_DIS_ACK_OVRD_DISABLE_FVAL 0x0 +#define HWIO_GCC_ARC_CLK_DIS_ACK_OVRD_MSS_MX_CLK_DIS_ACK_OVRD_ENABLE_FVAL 0x1 +#define HWIO_GCC_ARC_CLK_DIS_ACK_OVRD_APSS_MX_CLK_DIS_ACK_OVRD_BMSK 0x4 +#define HWIO_GCC_ARC_CLK_DIS_ACK_OVRD_APSS_MX_CLK_DIS_ACK_OVRD_SHFT 0x2 +#define HWIO_GCC_ARC_CLK_DIS_ACK_OVRD_APSS_MX_CLK_DIS_ACK_OVRD_DISABLE_FVAL 0x0 +#define HWIO_GCC_ARC_CLK_DIS_ACK_OVRD_APSS_MX_CLK_DIS_ACK_OVRD_ENABLE_FVAL 0x1 +#define HWIO_GCC_ARC_CLK_DIS_ACK_OVRD_NAV_MX_CLK_DIS_ACK_OVRD_BMSK 0x2 +#define HWIO_GCC_ARC_CLK_DIS_ACK_OVRD_NAV_MX_CLK_DIS_ACK_OVRD_SHFT 0x1 +#define HWIO_GCC_ARC_CLK_DIS_ACK_OVRD_NAV_MX_CLK_DIS_ACK_OVRD_DISABLE_FVAL 0x0 +#define HWIO_GCC_ARC_CLK_DIS_ACK_OVRD_NAV_MX_CLK_DIS_ACK_OVRD_ENABLE_FVAL 0x1 +#define HWIO_GCC_ARC_CLK_DIS_ACK_OVRD_GCC_MX_CLK_DIS_ACK_OVRD_BMSK 0x1 +#define HWIO_GCC_ARC_CLK_DIS_ACK_OVRD_GCC_MX_CLK_DIS_ACK_OVRD_SHFT 0x0 +#define HWIO_GCC_ARC_CLK_DIS_ACK_OVRD_GCC_MX_CLK_DIS_ACK_OVRD_DISABLE_FVAL 0x0 +#define HWIO_GCC_ARC_CLK_DIS_ACK_OVRD_GCC_MX_CLK_DIS_ACK_OVRD_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPARE0_REG_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006e000) +#define HWIO_GCC_SPARE0_REG_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006e000) +#define HWIO_GCC_SPARE0_REG_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006e000) +#define HWIO_GCC_SPARE0_REG_RMSK 0xffffffff +#define HWIO_GCC_SPARE0_REG_ATTR 0x3 +#define HWIO_GCC_SPARE0_REG_IN \ + in_dword_masked(HWIO_GCC_SPARE0_REG_ADDR, HWIO_GCC_SPARE0_REG_RMSK) +#define HWIO_GCC_SPARE0_REG_INM(m) \ + in_dword_masked(HWIO_GCC_SPARE0_REG_ADDR, m) +#define HWIO_GCC_SPARE0_REG_OUT(v) \ + out_dword(HWIO_GCC_SPARE0_REG_ADDR,v) +#define HWIO_GCC_SPARE0_REG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPARE0_REG_ADDR,m,v,HWIO_GCC_SPARE0_REG_IN) +#define HWIO_GCC_SPARE0_REG_SPARE_BITS_BMSK 0xffffffff +#define HWIO_GCC_SPARE0_REG_SPARE_BITS_SHFT 0x0 + +#define HWIO_GCC_SPARE1_REG_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006f000) +#define HWIO_GCC_SPARE1_REG_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006f000) +#define HWIO_GCC_SPARE1_REG_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006f000) +#define HWIO_GCC_SPARE1_REG_RMSK 0xffffffff +#define HWIO_GCC_SPARE1_REG_ATTR 0x3 +#define HWIO_GCC_SPARE1_REG_IN \ + in_dword_masked(HWIO_GCC_SPARE1_REG_ADDR, HWIO_GCC_SPARE1_REG_RMSK) +#define HWIO_GCC_SPARE1_REG_INM(m) \ + in_dword_masked(HWIO_GCC_SPARE1_REG_ADDR, m) +#define HWIO_GCC_SPARE1_REG_OUT(v) \ + out_dword(HWIO_GCC_SPARE1_REG_ADDR,v) +#define HWIO_GCC_SPARE1_REG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPARE1_REG_ADDR,m,v,HWIO_GCC_SPARE1_REG_IN) +#define HWIO_GCC_SPARE1_REG_SPARE_BITS_BMSK 0xffffffff +#define HWIO_GCC_SPARE1_REG_SPARE_BITS_SHFT 0x0 + +#define HWIO_GCC_SPARE2_REG_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00070000) +#define HWIO_GCC_SPARE2_REG_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00070000) +#define HWIO_GCC_SPARE2_REG_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00070000) +#define HWIO_GCC_SPARE2_REG_RMSK 0xffffffff +#define HWIO_GCC_SPARE2_REG_ATTR 0x3 +#define HWIO_GCC_SPARE2_REG_IN \ + in_dword_masked(HWIO_GCC_SPARE2_REG_ADDR, HWIO_GCC_SPARE2_REG_RMSK) +#define HWIO_GCC_SPARE2_REG_INM(m) \ + in_dword_masked(HWIO_GCC_SPARE2_REG_ADDR, m) +#define HWIO_GCC_SPARE2_REG_OUT(v) \ + out_dword(HWIO_GCC_SPARE2_REG_ADDR,v) +#define HWIO_GCC_SPARE2_REG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPARE2_REG_ADDR,m,v,HWIO_GCC_SPARE2_REG_IN) +#define HWIO_GCC_SPARE2_REG_SPARE_BITS_BMSK 0xffffffff +#define HWIO_GCC_SPARE2_REG_SPARE_BITS_SHFT 0x0 + +#define HWIO_GCC_SPARE3_REG_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00071000) +#define HWIO_GCC_SPARE3_REG_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00071000) +#define HWIO_GCC_SPARE3_REG_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00071000) +#define HWIO_GCC_SPARE3_REG_RMSK 0xffffffff +#define HWIO_GCC_SPARE3_REG_ATTR 0x3 +#define HWIO_GCC_SPARE3_REG_IN \ + in_dword_masked(HWIO_GCC_SPARE3_REG_ADDR, HWIO_GCC_SPARE3_REG_RMSK) +#define HWIO_GCC_SPARE3_REG_INM(m) \ + in_dword_masked(HWIO_GCC_SPARE3_REG_ADDR, m) +#define HWIO_GCC_SPARE3_REG_OUT(v) \ + out_dword(HWIO_GCC_SPARE3_REG_ADDR,v) +#define HWIO_GCC_SPARE3_REG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPARE3_REG_ADDR,m,v,HWIO_GCC_SPARE3_REG_IN) +#define HWIO_GCC_SPARE3_REG_SPARE_BITS_BMSK 0xffffffff +#define HWIO_GCC_SPARE3_REG_SPARE_BITS_SHFT 0x0 + +#define HWIO_GCC_RAW_SLEEP_CLK_CTRL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00072000) +#define HWIO_GCC_RAW_SLEEP_CLK_CTRL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00072000) +#define HWIO_GCC_RAW_SLEEP_CLK_CTRL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00072000) +#define HWIO_GCC_RAW_SLEEP_CLK_CTRL_RMSK 0x1 +#define HWIO_GCC_RAW_SLEEP_CLK_CTRL_ATTR 0x3 +#define HWIO_GCC_RAW_SLEEP_CLK_CTRL_IN \ + in_dword_masked(HWIO_GCC_RAW_SLEEP_CLK_CTRL_ADDR, HWIO_GCC_RAW_SLEEP_CLK_CTRL_RMSK) +#define HWIO_GCC_RAW_SLEEP_CLK_CTRL_INM(m) \ + in_dword_masked(HWIO_GCC_RAW_SLEEP_CLK_CTRL_ADDR, m) +#define HWIO_GCC_RAW_SLEEP_CLK_CTRL_OUT(v) \ + out_dword(HWIO_GCC_RAW_SLEEP_CLK_CTRL_ADDR,v) +#define HWIO_GCC_RAW_SLEEP_CLK_CTRL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RAW_SLEEP_CLK_CTRL_ADDR,m,v,HWIO_GCC_RAW_SLEEP_CLK_CTRL_IN) +#define HWIO_GCC_RAW_SLEEP_CLK_CTRL_GATING_DISABLE_BMSK 0x1 +#define HWIO_GCC_RAW_SLEEP_CLK_CTRL_GATING_DISABLE_SHFT 0x0 +#define HWIO_GCC_RAW_SLEEP_CLK_CTRL_GATING_DISABLE_ENABLE_FVAL 0x0 +#define HWIO_GCC_RAW_SLEEP_CLK_CTRL_GATING_DISABLE_DISABLE_FVAL 0x1 + +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00073000) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00073000) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00073000) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_CLK_RMSK 0x80000001 +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ATTR 0x3 +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_CLK_IN \ + in_dword_masked(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR, HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_CLK_RMSK) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR, m) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_CLK_OUT(v) \ + out_dword(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR,v) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR,m,v,HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_CLK_IN) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00073004) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00073004) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00073004) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_CLK_RMSK 0x80000001 +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ATTR 0x3 +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_CLK_IN \ + in_dword_masked(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR, HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_CLK_RMSK) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR, m) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_CLK_OUT(v) \ + out_dword(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR,v) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR,m,v,HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_CLK_IN) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00073008) +#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00073008) +#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00073008) +#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_RMSK 0x80000001 +#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_ATTR 0x3 +#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_IN \ + in_dword_masked(HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_ADDR, HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_RMSK) +#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_ADDR, m) +#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_OUT(v) \ + out_dword(HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_ADDR,v) +#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_ADDR,m,v,HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_IN) +#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007300c) +#define HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007300c) +#define HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007300c) +#define HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_RMSK 0x80000001 +#define HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_ATTR 0x3 +#define HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_IN \ + in_dword_masked(HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_ADDR, HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_RMSK) +#define HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_ADDR, m) +#define HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_OUT(v) \ + out_dword(HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_ADDR,v) +#define HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_ADDR,m,v,HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_IN) +#define HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00074000) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00074000) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00074000) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_RMSK 0x80000001 +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ATTR 0x3 +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_IN \ + in_dword_masked(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR, HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_RMSK) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR, m) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_OUT(v) \ + out_dword(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR,v) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR,m,v,HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_IN) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00074004) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00074004) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00074004) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_RMSK 0x80000001 +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ATTR 0x3 +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_IN \ + in_dword_masked(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR, HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_RMSK) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR, m) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_OUT(v) \ + out_dword(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR,v) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR,m,v,HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_IN) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00074008) +#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00074008) +#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00074008) +#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_RMSK 0x80000001 +#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_ATTR 0x3 +#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_IN \ + in_dword_masked(HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_ADDR, HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_RMSK) +#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_ADDR, m) +#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_OUT(v) \ + out_dword(HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_ADDR,v) +#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_ADDR,m,v,HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_IN) +#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007400c) +#define HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007400c) +#define HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007400c) +#define HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_RMSK 0x80000001 +#define HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_ATTR 0x3 +#define HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_IN \ + in_dword_masked(HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_ADDR, HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_RMSK) +#define HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_ADDR, m) +#define HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_OUT(v) \ + out_dword(HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_ADDR,v) +#define HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_ADDR,m,v,HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_IN) +#define HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00075000) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00075000) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00075000) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_CLK_RMSK 0x80000001 +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ATTR 0x3 +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_CLK_IN \ + in_dword_masked(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR, HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_CLK_RMSK) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR, m) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_CLK_OUT(v) \ + out_dword(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR,v) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR,m,v,HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_CLK_IN) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00075004) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00075004) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00075004) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_CLK_RMSK 0x80000001 +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ATTR 0x3 +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_CLK_IN \ + in_dword_masked(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR, HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_CLK_RMSK) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR, m) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_CLK_OUT(v) \ + out_dword(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR,v) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR,m,v,HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_CLK_IN) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00075008) +#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00075008) +#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00075008) +#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_RMSK 0x80000001 +#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_ATTR 0x3 +#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_IN \ + in_dword_masked(HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_ADDR, HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_RMSK) +#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_ADDR, m) +#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_OUT(v) \ + out_dword(HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_ADDR,v) +#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_ADDR,m,v,HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_IN) +#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007500c) +#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007500c) +#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007500c) +#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_RMSK 0x80000001 +#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_ATTR 0x3 +#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_IN \ + in_dword_masked(HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_ADDR, HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_RMSK) +#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_ADDR, m) +#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_OUT(v) \ + out_dword(HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_ADDR,v) +#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_ADDR,m,v,HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_IN) +#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00076000) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00076000) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00076000) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_CLK_RMSK 0x80000001 +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ATTR 0x3 +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_CLK_IN \ + in_dword_masked(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR, HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_CLK_RMSK) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR, m) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_CLK_OUT(v) \ + out_dword(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR,v) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR,m,v,HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_CLK_IN) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00076004) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00076004) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00076004) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_CLK_RMSK 0x80000001 +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ATTR 0x3 +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_CLK_IN \ + in_dword_masked(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR, HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_CLK_RMSK) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR, m) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_CLK_OUT(v) \ + out_dword(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR,v) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR,m,v,HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_CLK_IN) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00076008) +#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00076008) +#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00076008) +#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_RMSK 0x80000001 +#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_ATTR 0x3 +#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_IN \ + in_dword_masked(HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_ADDR, HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_RMSK) +#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_ADDR, m) +#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_OUT(v) \ + out_dword(HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_ADDR,v) +#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_ADDR,m,v,HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_IN) +#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007600c) +#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007600c) +#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007600c) +#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_RMSK 0x80000001 +#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_ATTR 0x3 +#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_IN \ + in_dword_masked(HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_ADDR, HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_RMSK) +#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_ADDR, m) +#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_OUT(v) \ + out_dword(HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_ADDR,v) +#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_ADDR,m,v,HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_IN) +#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_USB3_PRIM_CLKREF_EN_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00078000) +#define HWIO_GCC_USB3_PRIM_CLKREF_EN_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00078000) +#define HWIO_GCC_USB3_PRIM_CLKREF_EN_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00078000) +#define HWIO_GCC_USB3_PRIM_CLKREF_EN_RMSK 0x80000001 +#define HWIO_GCC_USB3_PRIM_CLKREF_EN_ATTR 0x3 +#define HWIO_GCC_USB3_PRIM_CLKREF_EN_IN \ + in_dword_masked(HWIO_GCC_USB3_PRIM_CLKREF_EN_ADDR, HWIO_GCC_USB3_PRIM_CLKREF_EN_RMSK) +#define HWIO_GCC_USB3_PRIM_CLKREF_EN_INM(m) \ + in_dword_masked(HWIO_GCC_USB3_PRIM_CLKREF_EN_ADDR, m) +#define HWIO_GCC_USB3_PRIM_CLKREF_EN_OUT(v) \ + out_dword(HWIO_GCC_USB3_PRIM_CLKREF_EN_ADDR,v) +#define HWIO_GCC_USB3_PRIM_CLKREF_EN_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB3_PRIM_CLKREF_EN_ADDR,m,v,HWIO_GCC_USB3_PRIM_CLKREF_EN_IN) +#define HWIO_GCC_USB3_PRIM_CLKREF_EN_USB3_STATUS_BMSK 0x80000000 +#define HWIO_GCC_USB3_PRIM_CLKREF_EN_USB3_STATUS_SHFT 0x1f +#define HWIO_GCC_USB3_PRIM_CLKREF_EN_USB3_ENABLE_BMSK 0x1 +#define HWIO_GCC_USB3_PRIM_CLKREF_EN_USB3_ENABLE_SHFT 0x0 +#define HWIO_GCC_USB3_PRIM_CLKREF_EN_USB3_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB3_PRIM_CLKREF_EN_USB3_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_0_CLKREF_EN_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00078004) +#define HWIO_GCC_PCIE_0_CLKREF_EN_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00078004) +#define HWIO_GCC_PCIE_0_CLKREF_EN_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00078004) +#define HWIO_GCC_PCIE_0_CLKREF_EN_RMSK 0x80000001 +#define HWIO_GCC_PCIE_0_CLKREF_EN_ATTR 0x3 +#define HWIO_GCC_PCIE_0_CLKREF_EN_IN \ + in_dword_masked(HWIO_GCC_PCIE_0_CLKREF_EN_ADDR, HWIO_GCC_PCIE_0_CLKREF_EN_RMSK) +#define HWIO_GCC_PCIE_0_CLKREF_EN_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_0_CLKREF_EN_ADDR, m) +#define HWIO_GCC_PCIE_0_CLKREF_EN_OUT(v) \ + out_dword(HWIO_GCC_PCIE_0_CLKREF_EN_ADDR,v) +#define HWIO_GCC_PCIE_0_CLKREF_EN_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_0_CLKREF_EN_ADDR,m,v,HWIO_GCC_PCIE_0_CLKREF_EN_IN) +#define HWIO_GCC_PCIE_0_CLKREF_EN_PCIE_STATUS_BMSK 0x80000000 +#define HWIO_GCC_PCIE_0_CLKREF_EN_PCIE_STATUS_SHFT 0x1f +#define HWIO_GCC_PCIE_0_CLKREF_EN_PCIE_ENABLE_BMSK 0x1 +#define HWIO_GCC_PCIE_0_CLKREF_EN_PCIE_ENABLE_SHFT 0x0 +#define HWIO_GCC_PCIE_0_CLKREF_EN_PCIE_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_CLKREF_EN_PCIE_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RX1_USB2_CLKREF_EN_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00078008) +#define HWIO_GCC_RX1_USB2_CLKREF_EN_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00078008) +#define HWIO_GCC_RX1_USB2_CLKREF_EN_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00078008) +#define HWIO_GCC_RX1_USB2_CLKREF_EN_RMSK 0x80000003 +#define HWIO_GCC_RX1_USB2_CLKREF_EN_ATTR 0x3 +#define HWIO_GCC_RX1_USB2_CLKREF_EN_IN \ + in_dword_masked(HWIO_GCC_RX1_USB2_CLKREF_EN_ADDR, HWIO_GCC_RX1_USB2_CLKREF_EN_RMSK) +#define HWIO_GCC_RX1_USB2_CLKREF_EN_INM(m) \ + in_dword_masked(HWIO_GCC_RX1_USB2_CLKREF_EN_ADDR, m) +#define HWIO_GCC_RX1_USB2_CLKREF_EN_OUT(v) \ + out_dword(HWIO_GCC_RX1_USB2_CLKREF_EN_ADDR,v) +#define HWIO_GCC_RX1_USB2_CLKREF_EN_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RX1_USB2_CLKREF_EN_ADDR,m,v,HWIO_GCC_RX1_USB2_CLKREF_EN_IN) +#define HWIO_GCC_RX1_USB2_CLKREF_EN_RX1_USB2_STATUS_BMSK 0x80000000 +#define HWIO_GCC_RX1_USB2_CLKREF_EN_RX1_USB2_STATUS_SHFT 0x1f +#define HWIO_GCC_RX1_USB2_CLKREF_EN_CREF_ENABLE_BMSK 0x2 +#define HWIO_GCC_RX1_USB2_CLKREF_EN_CREF_ENABLE_SHFT 0x1 +#define HWIO_GCC_RX1_USB2_CLKREF_EN_CREF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_RX1_USB2_CLKREF_EN_CREF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_RX1_USB2_CLKREF_EN_RX1_USB2_ENABLE_BMSK 0x1 +#define HWIO_GCC_RX1_USB2_CLKREF_EN_RX1_USB2_ENABLE_SHFT 0x0 +#define HWIO_GCC_RX1_USB2_CLKREF_EN_RX1_USB2_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_RX1_USB2_CLKREF_EN_RX1_USB2_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RX2_QLINK_CLKREF_EN_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007800c) +#define HWIO_GCC_RX2_QLINK_CLKREF_EN_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007800c) +#define HWIO_GCC_RX2_QLINK_CLKREF_EN_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007800c) +#define HWIO_GCC_RX2_QLINK_CLKREF_EN_RMSK 0x80000003 +#define HWIO_GCC_RX2_QLINK_CLKREF_EN_ATTR 0x3 +#define HWIO_GCC_RX2_QLINK_CLKREF_EN_IN \ + in_dword_masked(HWIO_GCC_RX2_QLINK_CLKREF_EN_ADDR, HWIO_GCC_RX2_QLINK_CLKREF_EN_RMSK) +#define HWIO_GCC_RX2_QLINK_CLKREF_EN_INM(m) \ + in_dword_masked(HWIO_GCC_RX2_QLINK_CLKREF_EN_ADDR, m) +#define HWIO_GCC_RX2_QLINK_CLKREF_EN_OUT(v) \ + out_dword(HWIO_GCC_RX2_QLINK_CLKREF_EN_ADDR,v) +#define HWIO_GCC_RX2_QLINK_CLKREF_EN_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RX2_QLINK_CLKREF_EN_ADDR,m,v,HWIO_GCC_RX2_QLINK_CLKREF_EN_IN) +#define HWIO_GCC_RX2_QLINK_CLKREF_EN_RX2_QLINK_STATUS_BMSK 0x80000000 +#define HWIO_GCC_RX2_QLINK_CLKREF_EN_RX2_QLINK_STATUS_SHFT 0x1f +#define HWIO_GCC_RX2_QLINK_CLKREF_EN_RXTAP0_ENABLE_BMSK 0x2 +#define HWIO_GCC_RX2_QLINK_CLKREF_EN_RXTAP0_ENABLE_SHFT 0x1 +#define HWIO_GCC_RX2_QLINK_CLKREF_EN_RXTAP0_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_RX2_QLINK_CLKREF_EN_RXTAP0_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_RX2_QLINK_CLKREF_EN_RX2_QLINK_ENABLE_BMSK 0x1 +#define HWIO_GCC_RX2_QLINK_CLKREF_EN_RX2_QLINK_ENABLE_SHFT 0x0 +#define HWIO_GCC_RX2_QLINK_CLKREF_EN_RX2_QLINK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_RX2_QLINK_CLKREF_EN_RX2_QLINK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RX3_MODEM_CLKREF_EN_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00078010) +#define HWIO_GCC_RX3_MODEM_CLKREF_EN_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00078010) +#define HWIO_GCC_RX3_MODEM_CLKREF_EN_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00078010) +#define HWIO_GCC_RX3_MODEM_CLKREF_EN_RMSK 0x80000003 +#define HWIO_GCC_RX3_MODEM_CLKREF_EN_ATTR 0x3 +#define HWIO_GCC_RX3_MODEM_CLKREF_EN_IN \ + in_dword_masked(HWIO_GCC_RX3_MODEM_CLKREF_EN_ADDR, HWIO_GCC_RX3_MODEM_CLKREF_EN_RMSK) +#define HWIO_GCC_RX3_MODEM_CLKREF_EN_INM(m) \ + in_dword_masked(HWIO_GCC_RX3_MODEM_CLKREF_EN_ADDR, m) +#define HWIO_GCC_RX3_MODEM_CLKREF_EN_OUT(v) \ + out_dword(HWIO_GCC_RX3_MODEM_CLKREF_EN_ADDR,v) +#define HWIO_GCC_RX3_MODEM_CLKREF_EN_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RX3_MODEM_CLKREF_EN_ADDR,m,v,HWIO_GCC_RX3_MODEM_CLKREF_EN_IN) +#define HWIO_GCC_RX3_MODEM_CLKREF_EN_RX3_MODEM_STATUS_BMSK 0x80000000 +#define HWIO_GCC_RX3_MODEM_CLKREF_EN_RX3_MODEM_STATUS_SHFT 0x1f +#define HWIO_GCC_RX3_MODEM_CLKREF_EN_RXTAP1_ENABLE_BMSK 0x2 +#define HWIO_GCC_RX3_MODEM_CLKREF_EN_RXTAP1_ENABLE_SHFT 0x1 +#define HWIO_GCC_RX3_MODEM_CLKREF_EN_RXTAP1_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_RX3_MODEM_CLKREF_EN_RXTAP1_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_RX3_MODEM_CLKREF_EN_RX3_MODEM_ENABLE_BMSK 0x1 +#define HWIO_GCC_RX3_MODEM_CLKREF_EN_RX3_MODEM_ENABLE_SHFT 0x0 +#define HWIO_GCC_RX3_MODEM_CLKREF_EN_RX3_MODEM_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_RX3_MODEM_CLKREF_EN_RX3_MODEM_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CXO_TX1_CLKREF_EN1_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00078014) +#define HWIO_GCC_CXO_TX1_CLKREF_EN1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00078014) +#define HWIO_GCC_CXO_TX1_CLKREF_EN1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00078014) +#define HWIO_GCC_CXO_TX1_CLKREF_EN1_RMSK 0x80000001 +#define HWIO_GCC_CXO_TX1_CLKREF_EN1_ATTR 0x3 +#define HWIO_GCC_CXO_TX1_CLKREF_EN1_IN \ + in_dword_masked(HWIO_GCC_CXO_TX1_CLKREF_EN1_ADDR, HWIO_GCC_CXO_TX1_CLKREF_EN1_RMSK) +#define HWIO_GCC_CXO_TX1_CLKREF_EN1_INM(m) \ + in_dword_masked(HWIO_GCC_CXO_TX1_CLKREF_EN1_ADDR, m) +#define HWIO_GCC_CXO_TX1_CLKREF_EN1_OUT(v) \ + out_dword(HWIO_GCC_CXO_TX1_CLKREF_EN1_ADDR,v) +#define HWIO_GCC_CXO_TX1_CLKREF_EN1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CXO_TX1_CLKREF_EN1_ADDR,m,v,HWIO_GCC_CXO_TX1_CLKREF_EN1_IN) +#define HWIO_GCC_CXO_TX1_CLKREF_EN1_CXO_TX1_STATUS_BMSK 0x80000000 +#define HWIO_GCC_CXO_TX1_CLKREF_EN1_CXO_TX1_STATUS_SHFT 0x1f +#define HWIO_GCC_CXO_TX1_CLKREF_EN1_CXO_TX1_ENABLE_BMSK 0x1 +#define HWIO_GCC_CXO_TX1_CLKREF_EN1_CXO_TX1_ENABLE_SHFT 0x0 +#define HWIO_GCC_CXO_TX1_CLKREF_EN1_CXO_TX1_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CXO_TX1_CLKREF_EN1_CXO_TX1_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CLKREF_SPARE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00078018) +#define HWIO_GCC_CLKREF_SPARE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00078018) +#define HWIO_GCC_CLKREF_SPARE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00078018) +#define HWIO_GCC_CLKREF_SPARE_RMSK 0xff +#define HWIO_GCC_CLKREF_SPARE_ATTR 0x3 +#define HWIO_GCC_CLKREF_SPARE_IN \ + in_dword_masked(HWIO_GCC_CLKREF_SPARE_ADDR, HWIO_GCC_CLKREF_SPARE_RMSK) +#define HWIO_GCC_CLKREF_SPARE_INM(m) \ + in_dword_masked(HWIO_GCC_CLKREF_SPARE_ADDR, m) +#define HWIO_GCC_CLKREF_SPARE_OUT(v) \ + out_dword(HWIO_GCC_CLKREF_SPARE_ADDR,v) +#define HWIO_GCC_CLKREF_SPARE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CLKREF_SPARE_ADDR,m,v,HWIO_GCC_CLKREF_SPARE_IN) +#define HWIO_GCC_CLKREF_SPARE_SPARE_BMSK 0xff +#define HWIO_GCC_CLKREF_SPARE_SPARE_SHFT 0x0 + +#define HWIO_GCC_CXO_REFGEN_BIAS_SEL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007801c) +#define HWIO_GCC_CXO_REFGEN_BIAS_SEL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007801c) +#define HWIO_GCC_CXO_REFGEN_BIAS_SEL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007801c) +#define HWIO_GCC_CXO_REFGEN_BIAS_SEL_RMSK 0x80000001 +#define HWIO_GCC_CXO_REFGEN_BIAS_SEL_ATTR 0x3 +#define HWIO_GCC_CXO_REFGEN_BIAS_SEL_IN \ + in_dword_masked(HWIO_GCC_CXO_REFGEN_BIAS_SEL_ADDR, HWIO_GCC_CXO_REFGEN_BIAS_SEL_RMSK) +#define HWIO_GCC_CXO_REFGEN_BIAS_SEL_INM(m) \ + in_dword_masked(HWIO_GCC_CXO_REFGEN_BIAS_SEL_ADDR, m) +#define HWIO_GCC_CXO_REFGEN_BIAS_SEL_OUT(v) \ + out_dword(HWIO_GCC_CXO_REFGEN_BIAS_SEL_ADDR,v) +#define HWIO_GCC_CXO_REFGEN_BIAS_SEL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CXO_REFGEN_BIAS_SEL_ADDR,m,v,HWIO_GCC_CXO_REFGEN_BIAS_SEL_IN) +#define HWIO_GCC_CXO_REFGEN_BIAS_SEL_SEL_REFGEN_STATUS_BMSK 0x80000000 +#define HWIO_GCC_CXO_REFGEN_BIAS_SEL_SEL_REFGEN_STATUS_SHFT 0x1f +#define HWIO_GCC_CXO_REFGEN_BIAS_SEL_SEL_REFGEN_BMSK 0x1 +#define HWIO_GCC_CXO_REFGEN_BIAS_SEL_SEL_REFGEN_SHFT 0x0 +#define HWIO_GCC_CXO_REFGEN_BIAS_SEL_SEL_REFGEN_DISABLE_FVAL 0x0 +#define HWIO_GCC_CXO_REFGEN_BIAS_SEL_SEL_REFGEN_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00077000) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00077000) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00077000) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_CLK_RMSK 0x80000001 +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ATTR 0x3 +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_CLK_IN \ + in_dword_masked(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR, HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_CLK_RMSK) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR, m) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_CLK_OUT(v) \ + out_dword(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR,v) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR,m,v,HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_CLK_IN) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00077004) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00077004) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00077004) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_CLK_RMSK 0x80000001 +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ATTR 0x3 +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_CLK_IN \ + in_dword_masked(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR, HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_CLK_RMSK) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR, m) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_CLK_OUT(v) \ + out_dword(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR,v) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR,m,v,HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_CLK_IN) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00077008) +#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00077008) +#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00077008) +#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_RMSK 0x80000001 +#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_ATTR 0x3 +#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_IN \ + in_dword_masked(HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_ADDR, HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_RMSK) +#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_ADDR, m) +#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_OUT(v) \ + out_dword(HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_ADDR,v) +#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_ADDR,m,v,HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_IN) +#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007700c) +#define HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007700c) +#define HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007700c) +#define HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_RMSK 0x80000001 +#define HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_ATTR 0x3 +#define HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_IN \ + in_dword_masked(HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_ADDR, HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_RMSK) +#define HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_ADDR, m) +#define HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_OUT(v) \ + out_dword(HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_ADDR,v) +#define HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_ADDR,m,v,HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_IN) +#define HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005c018) +#define HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005c018) +#define HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005c018) +#define HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_RMSK 0x80000001 +#define HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_ATTR 0x3 +#define HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_IN \ + in_dword_masked(HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_ADDR, HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_RMSK) +#define HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_ADDR, m) +#define HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_OUT(v) \ + out_dword(HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_ADDR,v) +#define HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_ADDR,m,v,HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_IN) +#define HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00063018) +#define HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00063018) +#define HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00063018) +#define HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_RMSK 0x80000001 +#define HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_ATTR 0x3 +#define HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_IN \ + in_dword_masked(HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_ADDR, HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_RMSK) +#define HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_ADDR, m) +#define HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_OUT(v) \ + out_dword(HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_ADDR,v) +#define HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_ADDR,m,v,HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_IN) +#define HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005d018) +#define HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005d018) +#define HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005d018) +#define HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_RMSK 0x80000001 +#define HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_ATTR 0x3 +#define HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_IN \ + in_dword_masked(HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_ADDR, HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_RMSK) +#define HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_ADDR, m) +#define HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_OUT(v) \ + out_dword(HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_ADDR,v) +#define HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_ADDR,m,v,HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_IN) +#define HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005e018) +#define HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005e018) +#define HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005e018) +#define HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_RMSK 0x80000001 +#define HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_ATTR 0x3 +#define HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_IN \ + in_dword_masked(HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_ADDR, HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_RMSK) +#define HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_ADDR, m) +#define HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_OUT(v) \ + out_dword(HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_ADDR,v) +#define HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_ADDR,m,v,HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_IN) +#define HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005f018) +#define HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005f018) +#define HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005f018) +#define HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_RMSK 0x80000001 +#define HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_ATTR 0x3 +#define HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_IN \ + in_dword_masked(HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_ADDR, HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_RMSK) +#define HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_ADDR, m) +#define HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_OUT(v) \ + out_dword(HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_ADDR,v) +#define HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_ADDR,m,v,HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_IN) +#define HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00061018) +#define HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00061018) +#define HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00061018) +#define HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_RMSK 0x80000001 +#define HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_ATTR 0x3 +#define HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_IN \ + in_dword_masked(HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_ADDR, HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_RMSK) +#define HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_ADDR, m) +#define HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_OUT(v) \ + out_dword(HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_ADDR,v) +#define HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_ADDR,m,v,HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_IN) +#define HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPARE2_VOTE_QDSS_APB_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00062018) +#define HWIO_GCC_SPARE2_VOTE_QDSS_APB_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00062018) +#define HWIO_GCC_SPARE2_VOTE_QDSS_APB_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00062018) +#define HWIO_GCC_SPARE2_VOTE_QDSS_APB_CLK_RMSK 0x80000001 +#define HWIO_GCC_SPARE2_VOTE_QDSS_APB_CLK_ATTR 0x3 +#define HWIO_GCC_SPARE2_VOTE_QDSS_APB_CLK_IN \ + in_dword_masked(HWIO_GCC_SPARE2_VOTE_QDSS_APB_CLK_ADDR, HWIO_GCC_SPARE2_VOTE_QDSS_APB_CLK_RMSK) +#define HWIO_GCC_SPARE2_VOTE_QDSS_APB_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_SPARE2_VOTE_QDSS_APB_CLK_ADDR, m) +#define HWIO_GCC_SPARE2_VOTE_QDSS_APB_CLK_OUT(v) \ + out_dword(HWIO_GCC_SPARE2_VOTE_QDSS_APB_CLK_ADDR,v) +#define HWIO_GCC_SPARE2_VOTE_QDSS_APB_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPARE2_VOTE_QDSS_APB_CLK_ADDR,m,v,HWIO_GCC_SPARE2_VOTE_QDSS_APB_CLK_IN) +#define HWIO_GCC_SPARE2_VOTE_QDSS_APB_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SPARE2_VOTE_QDSS_APB_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SPARE2_VOTE_QDSS_APB_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SPARE2_VOTE_QDSS_APB_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SPARE2_VOTE_QDSS_APB_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE2_VOTE_QDSS_APB_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_JBIST_MODE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00079000) +#define HWIO_GCC_JBIST_MODE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00079000) +#define HWIO_GCC_JBIST_MODE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00079000) +#define HWIO_GCC_JBIST_MODE_RMSK 0xffffffff +#define HWIO_GCC_JBIST_MODE_ATTR 0x3 +#define HWIO_GCC_JBIST_MODE_IN \ + in_dword_masked(HWIO_GCC_JBIST_MODE_ADDR, HWIO_GCC_JBIST_MODE_RMSK) +#define HWIO_GCC_JBIST_MODE_INM(m) \ + in_dword_masked(HWIO_GCC_JBIST_MODE_ADDR, m) +#define HWIO_GCC_JBIST_MODE_OUT(v) \ + out_dword(HWIO_GCC_JBIST_MODE_ADDR,v) +#define HWIO_GCC_JBIST_MODE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_JBIST_MODE_ADDR,m,v,HWIO_GCC_JBIST_MODE_IN) +#define HWIO_GCC_JBIST_MODE_RESERVE_BITS31_4_BMSK 0xfffffff0 +#define HWIO_GCC_JBIST_MODE_RESERVE_BITS31_4_SHFT 0x4 +#define HWIO_GCC_JBIST_MODE_START_MEAS_BMSK 0x8 +#define HWIO_GCC_JBIST_MODE_START_MEAS_SHFT 0x3 +#define HWIO_GCC_JBIST_MODE_JBIST_TEST_BMSK 0x4 +#define HWIO_GCC_JBIST_MODE_JBIST_TEST_SHFT 0x2 +#define HWIO_GCC_JBIST_MODE_RESET_N_BMSK 0x2 +#define HWIO_GCC_JBIST_MODE_RESET_N_SHFT 0x1 +#define HWIO_GCC_JBIST_MODE_SLEEP_N_BMSK 0x1 +#define HWIO_GCC_JBIST_MODE_SLEEP_N_SHFT 0x0 + +#define HWIO_GCC_JBIST_CONFIG_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00079004) +#define HWIO_GCC_JBIST_CONFIG_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00079004) +#define HWIO_GCC_JBIST_CONFIG_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00079004) +#define HWIO_GCC_JBIST_CONFIG_CTL_RMSK 0xffffffff +#define HWIO_GCC_JBIST_CONFIG_CTL_ATTR 0x3 +#define HWIO_GCC_JBIST_CONFIG_CTL_IN \ + in_dword_masked(HWIO_GCC_JBIST_CONFIG_CTL_ADDR, HWIO_GCC_JBIST_CONFIG_CTL_RMSK) +#define HWIO_GCC_JBIST_CONFIG_CTL_INM(m) \ + in_dword_masked(HWIO_GCC_JBIST_CONFIG_CTL_ADDR, m) +#define HWIO_GCC_JBIST_CONFIG_CTL_OUT(v) \ + out_dword(HWIO_GCC_JBIST_CONFIG_CTL_ADDR,v) +#define HWIO_GCC_JBIST_CONFIG_CTL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_JBIST_CONFIG_CTL_ADDR,m,v,HWIO_GCC_JBIST_CONFIG_CTL_IN) +#define HWIO_GCC_JBIST_CONFIG_CTL_JBIST_CONFIG_CTL_BMSK 0xffffffff +#define HWIO_GCC_JBIST_CONFIG_CTL_JBIST_CONFIG_CTL_SHFT 0x0 + +#define HWIO_GCC_JBIST_USER_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00079008) +#define HWIO_GCC_JBIST_USER_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00079008) +#define HWIO_GCC_JBIST_USER_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00079008) +#define HWIO_GCC_JBIST_USER_CTL_RMSK 0xffffffff +#define HWIO_GCC_JBIST_USER_CTL_ATTR 0x3 +#define HWIO_GCC_JBIST_USER_CTL_IN \ + in_dword_masked(HWIO_GCC_JBIST_USER_CTL_ADDR, HWIO_GCC_JBIST_USER_CTL_RMSK) +#define HWIO_GCC_JBIST_USER_CTL_INM(m) \ + in_dword_masked(HWIO_GCC_JBIST_USER_CTL_ADDR, m) +#define HWIO_GCC_JBIST_USER_CTL_OUT(v) \ + out_dword(HWIO_GCC_JBIST_USER_CTL_ADDR,v) +#define HWIO_GCC_JBIST_USER_CTL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_JBIST_USER_CTL_ADDR,m,v,HWIO_GCC_JBIST_USER_CTL_IN) +#define HWIO_GCC_JBIST_USER_CTL_JBIST_USER_CTL_BMSK 0xffffffff +#define HWIO_GCC_JBIST_USER_CTL_JBIST_USER_CTL_SHFT 0x0 + +#define HWIO_GCC_JBIST_USER_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007900c) +#define HWIO_GCC_JBIST_USER_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007900c) +#define HWIO_GCC_JBIST_USER_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007900c) +#define HWIO_GCC_JBIST_USER_CTL_U_RMSK 0xffffffff +#define HWIO_GCC_JBIST_USER_CTL_U_ATTR 0x3 +#define HWIO_GCC_JBIST_USER_CTL_U_IN \ + in_dword_masked(HWIO_GCC_JBIST_USER_CTL_U_ADDR, HWIO_GCC_JBIST_USER_CTL_U_RMSK) +#define HWIO_GCC_JBIST_USER_CTL_U_INM(m) \ + in_dword_masked(HWIO_GCC_JBIST_USER_CTL_U_ADDR, m) +#define HWIO_GCC_JBIST_USER_CTL_U_OUT(v) \ + out_dword(HWIO_GCC_JBIST_USER_CTL_U_ADDR,v) +#define HWIO_GCC_JBIST_USER_CTL_U_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_JBIST_USER_CTL_U_ADDR,m,v,HWIO_GCC_JBIST_USER_CTL_U_IN) +#define HWIO_GCC_JBIST_USER_CTL_U_JBIST_USER_CTL_U_BMSK 0xffffffff +#define HWIO_GCC_JBIST_USER_CTL_U_JBIST_USER_CTL_U_SHFT 0x0 + +#define HWIO_GCC_JBIST_TEST_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00079010) +#define HWIO_GCC_JBIST_TEST_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00079010) +#define HWIO_GCC_JBIST_TEST_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00079010) +#define HWIO_GCC_JBIST_TEST_CTL_RMSK 0xffffffff +#define HWIO_GCC_JBIST_TEST_CTL_ATTR 0x3 +#define HWIO_GCC_JBIST_TEST_CTL_IN \ + in_dword_masked(HWIO_GCC_JBIST_TEST_CTL_ADDR, HWIO_GCC_JBIST_TEST_CTL_RMSK) +#define HWIO_GCC_JBIST_TEST_CTL_INM(m) \ + in_dword_masked(HWIO_GCC_JBIST_TEST_CTL_ADDR, m) +#define HWIO_GCC_JBIST_TEST_CTL_OUT(v) \ + out_dword(HWIO_GCC_JBIST_TEST_CTL_ADDR,v) +#define HWIO_GCC_JBIST_TEST_CTL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_JBIST_TEST_CTL_ADDR,m,v,HWIO_GCC_JBIST_TEST_CTL_IN) +#define HWIO_GCC_JBIST_TEST_CTL_JBIST_TEST_CTL_BMSK 0xffffffff +#define HWIO_GCC_JBIST_TEST_CTL_JBIST_TEST_CTL_SHFT 0x0 + +#define HWIO_GCC_JBIST_STATUS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00079014) +#define HWIO_GCC_JBIST_STATUS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00079014) +#define HWIO_GCC_JBIST_STATUS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00079014) +#define HWIO_GCC_JBIST_STATUS_RMSK 0xffffffff +#define HWIO_GCC_JBIST_STATUS_ATTR 0x1 +#define HWIO_GCC_JBIST_STATUS_IN \ + in_dword_masked(HWIO_GCC_JBIST_STATUS_ADDR, HWIO_GCC_JBIST_STATUS_RMSK) +#define HWIO_GCC_JBIST_STATUS_INM(m) \ + in_dword_masked(HWIO_GCC_JBIST_STATUS_ADDR, m) +#define HWIO_GCC_JBIST_STATUS_JBIST_STATUS_BMSK 0xffffffff +#define HWIO_GCC_JBIST_STATUS_JBIST_STATUS_SHFT 0x0 + +#define HWIO_GCC_JBIST_MEAS_DONE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00079018) +#define HWIO_GCC_JBIST_MEAS_DONE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00079018) +#define HWIO_GCC_JBIST_MEAS_DONE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00079018) +#define HWIO_GCC_JBIST_MEAS_DONE_RMSK 0xffffffff +#define HWIO_GCC_JBIST_MEAS_DONE_ATTR 0x3 +#define HWIO_GCC_JBIST_MEAS_DONE_IN \ + in_dword_masked(HWIO_GCC_JBIST_MEAS_DONE_ADDR, HWIO_GCC_JBIST_MEAS_DONE_RMSK) +#define HWIO_GCC_JBIST_MEAS_DONE_INM(m) \ + in_dword_masked(HWIO_GCC_JBIST_MEAS_DONE_ADDR, m) +#define HWIO_GCC_JBIST_MEAS_DONE_OUT(v) \ + out_dword(HWIO_GCC_JBIST_MEAS_DONE_ADDR,v) +#define HWIO_GCC_JBIST_MEAS_DONE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_JBIST_MEAS_DONE_ADDR,m,v,HWIO_GCC_JBIST_MEAS_DONE_IN) +#define HWIO_GCC_JBIST_MEAS_DONE_RESERVE_BITS31_1_BMSK 0xfffffffe +#define HWIO_GCC_JBIST_MEAS_DONE_RESERVE_BITS31_1_SHFT 0x1 +#define HWIO_GCC_JBIST_MEAS_DONE_JBIST_DATA_STREAM_RDY_BMSK 0x1 +#define HWIO_GCC_JBIST_MEAS_DONE_JBIST_DATA_STREAM_RDY_SHFT 0x0 + +#define HWIO_GCC_JBIST_MISC_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007901c) +#define HWIO_GCC_JBIST_MISC_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007901c) +#define HWIO_GCC_JBIST_MISC_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007901c) +#define HWIO_GCC_JBIST_MISC_RMSK 0x3 +#define HWIO_GCC_JBIST_MISC_ATTR 0x3 +#define HWIO_GCC_JBIST_MISC_IN \ + in_dword_masked(HWIO_GCC_JBIST_MISC_ADDR, HWIO_GCC_JBIST_MISC_RMSK) +#define HWIO_GCC_JBIST_MISC_INM(m) \ + in_dword_masked(HWIO_GCC_JBIST_MISC_ADDR, m) +#define HWIO_GCC_JBIST_MISC_OUT(v) \ + out_dword(HWIO_GCC_JBIST_MISC_ADDR,v) +#define HWIO_GCC_JBIST_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_JBIST_MISC_ADDR,m,v,HWIO_GCC_JBIST_MISC_IN) +#define HWIO_GCC_JBIST_MISC_CLK_EXT_SEL_BMSK 0x3 +#define HWIO_GCC_JBIST_MISC_CLK_EXT_SEL_SHFT 0x0 +#define HWIO_GCC_JBIST_MISC_CLK_EXT_SEL_EMAC_DLL_CLK_FVAL 0x1 +#define HWIO_GCC_JBIST_MISC_CLK_EXT_SEL_SDCC_DLL_CLK_FVAL 0x2 + +#define HWIO_GCC_GLOBAL_EN_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a000) +#define HWIO_GCC_GLOBAL_EN_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007a000) +#define HWIO_GCC_GLOBAL_EN_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007a000) +#define HWIO_GCC_GLOBAL_EN_RMSK 0xffffffff +#define HWIO_GCC_GLOBAL_EN_ATTR 0x3 +#define HWIO_GCC_GLOBAL_EN_IN \ + in_dword_masked(HWIO_GCC_GLOBAL_EN_ADDR, HWIO_GCC_GLOBAL_EN_RMSK) +#define HWIO_GCC_GLOBAL_EN_INM(m) \ + in_dword_masked(HWIO_GCC_GLOBAL_EN_ADDR, m) +#define HWIO_GCC_GLOBAL_EN_OUT(v) \ + out_dword(HWIO_GCC_GLOBAL_EN_ADDR,v) +#define HWIO_GCC_GLOBAL_EN_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GLOBAL_EN_ADDR,m,v,HWIO_GCC_GLOBAL_EN_IN) +#define HWIO_GCC_GLOBAL_EN_SPARE_ENABLE_BMSK 0xffff8000 +#define HWIO_GCC_GLOBAL_EN_SPARE_ENABLE_SHFT 0xf +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_7_BMSK 0x4000 +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_7_SHFT 0xe +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_7_DISABLE_FVAL 0x0 +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_7_ENABLE_FVAL 0x1 +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_6_BMSK 0x2000 +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_6_SHFT 0xd +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_6_DISABLE_FVAL 0x0 +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_6_ENABLE_FVAL 0x1 +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_5_BMSK 0x1000 +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_5_SHFT 0xc +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_5_DISABLE_FVAL 0x0 +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_5_ENABLE_FVAL 0x1 +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_4_BMSK 0x800 +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_4_SHFT 0xb +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_4_DISABLE_FVAL 0x0 +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_4_ENABLE_FVAL 0x1 +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_3_BMSK 0x400 +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_3_SHFT 0xa +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_2_BMSK 0x200 +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_2_SHFT 0x9 +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_2_DISABLE_FVAL 0x0 +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_2_ENABLE_FVAL 0x1 +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_1_BMSK 0x100 +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_1_SHFT 0x8 +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_1_DISABLE_FVAL 0x0 +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_1_ENABLE_FVAL 0x1 +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_0_BMSK 0x80 +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_0_SHFT 0x7 +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_0_DISABLE_FVAL 0x0 +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_0_ENABLE_FVAL 0x1 +#define HWIO_GCC_GLOBAL_EN_REST_ENABLE_BMSK 0x40 +#define HWIO_GCC_GLOBAL_EN_REST_ENABLE_SHFT 0x6 +#define HWIO_GCC_GLOBAL_EN_REST_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GLOBAL_EN_REST_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_GLOBAL_EN_PERIPHERALS_ENABLE_BMSK 0x20 +#define HWIO_GCC_GLOBAL_EN_PERIPHERALS_ENABLE_SHFT 0x5 +#define HWIO_GCC_GLOBAL_EN_PERIPHERALS_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GLOBAL_EN_PERIPHERALS_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_GLOBAL_EN_CENTER_ENABLE_BMSK 0x10 +#define HWIO_GCC_GLOBAL_EN_CENTER_ENABLE_SHFT 0x4 +#define HWIO_GCC_GLOBAL_EN_CENTER_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GLOBAL_EN_CENTER_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_GLOBAL_EN_SOUTH_ENABLE_BMSK 0x8 +#define HWIO_GCC_GLOBAL_EN_SOUTH_ENABLE_SHFT 0x3 +#define HWIO_GCC_GLOBAL_EN_SOUTH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GLOBAL_EN_SOUTH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_GLOBAL_EN_NORTH_ENABLE_BMSK 0x4 +#define HWIO_GCC_GLOBAL_EN_NORTH_ENABLE_SHFT 0x2 +#define HWIO_GCC_GLOBAL_EN_NORTH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GLOBAL_EN_NORTH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_GLOBAL_EN_WEST_ENABLE_BMSK 0x2 +#define HWIO_GCC_GLOBAL_EN_WEST_ENABLE_SHFT 0x1 +#define HWIO_GCC_GLOBAL_EN_WEST_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GLOBAL_EN_WEST_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_GLOBAL_EN_EAST_ENABLE_BMSK 0x1 +#define HWIO_GCC_GLOBAL_EN_EAST_ENABLE_SHFT 0x0 +#define HWIO_GCC_GLOBAL_EN_EAST_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GLOBAL_EN_EAST_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_USB3_LPC_GPLL0_ACGCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007b000) +#define HWIO_GCC_USB3_LPC_GPLL0_ACGCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007b000) +#define HWIO_GCC_USB3_LPC_GPLL0_ACGCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007b000) +#define HWIO_GCC_USB3_LPC_GPLL0_ACGCR_RMSK 0x80000000 +#define HWIO_GCC_USB3_LPC_GPLL0_ACGCR_ATTR 0x1 +#define HWIO_GCC_USB3_LPC_GPLL0_ACGCR_IN \ + in_dword_masked(HWIO_GCC_USB3_LPC_GPLL0_ACGCR_ADDR, HWIO_GCC_USB3_LPC_GPLL0_ACGCR_RMSK) +#define HWIO_GCC_USB3_LPC_GPLL0_ACGCR_INM(m) \ + in_dword_masked(HWIO_GCC_USB3_LPC_GPLL0_ACGCR_ADDR, m) +#define HWIO_GCC_USB3_LPC_GPLL0_ACGCR_CLK_ON_BMSK 0x80000000 +#define HWIO_GCC_USB3_LPC_GPLL0_ACGCR_CLK_ON_SHFT 0x1f + +#define HWIO_GCC_USB3_LPC_GPLL4_ACGCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007b004) +#define HWIO_GCC_USB3_LPC_GPLL4_ACGCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007b004) +#define HWIO_GCC_USB3_LPC_GPLL4_ACGCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007b004) +#define HWIO_GCC_USB3_LPC_GPLL4_ACGCR_RMSK 0x80000000 +#define HWIO_GCC_USB3_LPC_GPLL4_ACGCR_ATTR 0x1 +#define HWIO_GCC_USB3_LPC_GPLL4_ACGCR_IN \ + in_dword_masked(HWIO_GCC_USB3_LPC_GPLL4_ACGCR_ADDR, HWIO_GCC_USB3_LPC_GPLL4_ACGCR_RMSK) +#define HWIO_GCC_USB3_LPC_GPLL4_ACGCR_INM(m) \ + in_dword_masked(HWIO_GCC_USB3_LPC_GPLL4_ACGCR_ADDR, m) +#define HWIO_GCC_USB3_LPC_GPLL4_ACGCR_CLK_ON_BMSK 0x80000000 +#define HWIO_GCC_USB3_LPC_GPLL4_ACGCR_CLK_ON_SHFT 0x1f + +#define HWIO_GCC_CPUSS_GPLL1_ACGCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007b008) +#define HWIO_GCC_CPUSS_GPLL1_ACGCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007b008) +#define HWIO_GCC_CPUSS_GPLL1_ACGCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007b008) +#define HWIO_GCC_CPUSS_GPLL1_ACGCR_RMSK 0x80000000 +#define HWIO_GCC_CPUSS_GPLL1_ACGCR_ATTR 0x1 +#define HWIO_GCC_CPUSS_GPLL1_ACGCR_IN \ + in_dword_masked(HWIO_GCC_CPUSS_GPLL1_ACGCR_ADDR, HWIO_GCC_CPUSS_GPLL1_ACGCR_RMSK) +#define HWIO_GCC_CPUSS_GPLL1_ACGCR_INM(m) \ + in_dword_masked(HWIO_GCC_CPUSS_GPLL1_ACGCR_ADDR, m) +#define HWIO_GCC_CPUSS_GPLL1_ACGCR_CLK_ON_BMSK 0x80000000 +#define HWIO_GCC_CPUSS_GPLL1_ACGCR_CLK_ON_SHFT 0x1f + +#define HWIO_GCC_CPUSS_GPLL4_ACGCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007b00c) +#define HWIO_GCC_CPUSS_GPLL4_ACGCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007b00c) +#define HWIO_GCC_CPUSS_GPLL4_ACGCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007b00c) +#define HWIO_GCC_CPUSS_GPLL4_ACGCR_RMSK 0x80000000 +#define HWIO_GCC_CPUSS_GPLL4_ACGCR_ATTR 0x1 +#define HWIO_GCC_CPUSS_GPLL4_ACGCR_IN \ + in_dword_masked(HWIO_GCC_CPUSS_GPLL4_ACGCR_ADDR, HWIO_GCC_CPUSS_GPLL4_ACGCR_RMSK) +#define HWIO_GCC_CPUSS_GPLL4_ACGCR_INM(m) \ + in_dword_masked(HWIO_GCC_CPUSS_GPLL4_ACGCR_ADDR, m) +#define HWIO_GCC_CPUSS_GPLL4_ACGCR_CLK_ON_BMSK 0x80000000 +#define HWIO_GCC_CPUSS_GPLL4_ACGCR_CLK_ON_SHFT 0x1f + +#define HWIO_GCC_CPUSS_GPLL5_ACGCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007b010) +#define HWIO_GCC_CPUSS_GPLL5_ACGCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007b010) +#define HWIO_GCC_CPUSS_GPLL5_ACGCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007b010) +#define HWIO_GCC_CPUSS_GPLL5_ACGCR_RMSK 0x80000000 +#define HWIO_GCC_CPUSS_GPLL5_ACGCR_ATTR 0x1 +#define HWIO_GCC_CPUSS_GPLL5_ACGCR_IN \ + in_dword_masked(HWIO_GCC_CPUSS_GPLL5_ACGCR_ADDR, HWIO_GCC_CPUSS_GPLL5_ACGCR_RMSK) +#define HWIO_GCC_CPUSS_GPLL5_ACGCR_INM(m) \ + in_dword_masked(HWIO_GCC_CPUSS_GPLL5_ACGCR_ADDR, m) +#define HWIO_GCC_CPUSS_GPLL5_ACGCR_CLK_ON_BMSK 0x80000000 +#define HWIO_GCC_CPUSS_GPLL5_ACGCR_CLK_ON_SHFT 0x1f + +#define HWIO_GCC_MSS_GPLL0_DIV_ACGCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007b014) +#define HWIO_GCC_MSS_GPLL0_DIV_ACGCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007b014) +#define HWIO_GCC_MSS_GPLL0_DIV_ACGCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007b014) +#define HWIO_GCC_MSS_GPLL0_DIV_ACGCR_RMSK 0x80000000 +#define HWIO_GCC_MSS_GPLL0_DIV_ACGCR_ATTR 0x1 +#define HWIO_GCC_MSS_GPLL0_DIV_ACGCR_IN \ + in_dword_masked(HWIO_GCC_MSS_GPLL0_DIV_ACGCR_ADDR, HWIO_GCC_MSS_GPLL0_DIV_ACGCR_RMSK) +#define HWIO_GCC_MSS_GPLL0_DIV_ACGCR_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_GPLL0_DIV_ACGCR_ADDR, m) +#define HWIO_GCC_MSS_GPLL0_DIV_ACGCR_CLK_ON_BMSK 0x80000000 +#define HWIO_GCC_MSS_GPLL0_DIV_ACGCR_CLK_ON_SHFT 0x1f + +#define HWIO_GCC_PLL_MISC_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007c000) +#define HWIO_GCC_PLL_MISC_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007c000) +#define HWIO_GCC_PLL_MISC_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007c000) +#define HWIO_GCC_PLL_MISC_RMSK 0x1 +#define HWIO_GCC_PLL_MISC_ATTR 0x3 +#define HWIO_GCC_PLL_MISC_IN \ + in_dword_masked(HWIO_GCC_PLL_MISC_ADDR, HWIO_GCC_PLL_MISC_RMSK) +#define HWIO_GCC_PLL_MISC_INM(m) \ + in_dword_masked(HWIO_GCC_PLL_MISC_ADDR, m) +#define HWIO_GCC_PLL_MISC_OUT(v) \ + out_dword(HWIO_GCC_PLL_MISC_ADDR,v) +#define HWIO_GCC_PLL_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PLL_MISC_ADDR,m,v,HWIO_GCC_PLL_MISC_IN) +#define HWIO_GCC_PLL_MISC_HW_TRIGGERED_STBY_DIS_BMSK 0x1 +#define HWIO_GCC_PLL_MISC_HW_TRIGGERED_STBY_DIS_SHFT 0x0 +#define HWIO_GCC_PLL_MISC_HW_TRIGGERED_STBY_DIS_DISABLE_FVAL 0x0 +#define HWIO_GCC_PLL_MISC_HW_TRIGGERED_STBY_DIS_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PLL_MISC1_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007c004) +#define HWIO_GCC_PLL_MISC1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007c004) +#define HWIO_GCC_PLL_MISC1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007c004) +#define HWIO_GCC_PLL_MISC1_RMSK 0x3f +#define HWIO_GCC_PLL_MISC1_ATTR 0x3 +#define HWIO_GCC_PLL_MISC1_IN \ + in_dword_masked(HWIO_GCC_PLL_MISC1_ADDR, HWIO_GCC_PLL_MISC1_RMSK) +#define HWIO_GCC_PLL_MISC1_INM(m) \ + in_dword_masked(HWIO_GCC_PLL_MISC1_ADDR, m) +#define HWIO_GCC_PLL_MISC1_OUT(v) \ + out_dword(HWIO_GCC_PLL_MISC1_ADDR,v) +#define HWIO_GCC_PLL_MISC1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PLL_MISC1_ADDR,m,v,HWIO_GCC_PLL_MISC1_IN) +#define HWIO_GCC_PLL_MISC1_PLL5_PLL_ACTIVE_MUX_BMSK 0x20 +#define HWIO_GCC_PLL_MISC1_PLL5_PLL_ACTIVE_MUX_SHFT 0x5 +#define HWIO_GCC_PLL_MISC1_PLL5_PLL_ACTIVE_MUX_DISABLE_FVAL 0x0 +#define HWIO_GCC_PLL_MISC1_PLL5_PLL_ACTIVE_MUX_ENABLE_FVAL 0x1 +#define HWIO_GCC_PLL_MISC1_PLL4_PLL_ACTIVE_MUX_BMSK 0x10 +#define HWIO_GCC_PLL_MISC1_PLL4_PLL_ACTIVE_MUX_SHFT 0x4 +#define HWIO_GCC_PLL_MISC1_PLL4_PLL_ACTIVE_MUX_DISABLE_FVAL 0x0 +#define HWIO_GCC_PLL_MISC1_PLL4_PLL_ACTIVE_MUX_ENABLE_FVAL 0x1 +#define HWIO_GCC_PLL_MISC1_PLL3_PLL_ACTIVE_MUX_BMSK 0x8 +#define HWIO_GCC_PLL_MISC1_PLL3_PLL_ACTIVE_MUX_SHFT 0x3 +#define HWIO_GCC_PLL_MISC1_PLL3_PLL_ACTIVE_MUX_DISABLE_FVAL 0x0 +#define HWIO_GCC_PLL_MISC1_PLL3_PLL_ACTIVE_MUX_ENABLE_FVAL 0x1 +#define HWIO_GCC_PLL_MISC1_PLL2_PLL_ACTIVE_MUX_BMSK 0x4 +#define HWIO_GCC_PLL_MISC1_PLL2_PLL_ACTIVE_MUX_SHFT 0x2 +#define HWIO_GCC_PLL_MISC1_PLL2_PLL_ACTIVE_MUX_DISABLE_FVAL 0x0 +#define HWIO_GCC_PLL_MISC1_PLL2_PLL_ACTIVE_MUX_ENABLE_FVAL 0x1 +#define HWIO_GCC_PLL_MISC1_PLL1_PLL_ACTIVE_MUX_BMSK 0x2 +#define HWIO_GCC_PLL_MISC1_PLL1_PLL_ACTIVE_MUX_SHFT 0x1 +#define HWIO_GCC_PLL_MISC1_PLL1_PLL_ACTIVE_MUX_DISABLE_FVAL 0x0 +#define HWIO_GCC_PLL_MISC1_PLL1_PLL_ACTIVE_MUX_ENABLE_FVAL 0x1 +#define HWIO_GCC_PLL_MISC1_PLL0_PLL_ACTIVE_MUX_BMSK 0x1 +#define HWIO_GCC_PLL_MISC1_PLL0_PLL_ACTIVE_MUX_SHFT 0x0 +#define HWIO_GCC_PLL_MISC1_PLL0_PLL_ACTIVE_MUX_DISABLE_FVAL 0x0 +#define HWIO_GCC_PLL_MISC1_PLL0_PLL_ACTIVE_MUX_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_PERST_HANDSHAKE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007d000) +#define HWIO_GCC_PCIE_PERST_HANDSHAKE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d000) +#define HWIO_GCC_PCIE_PERST_HANDSHAKE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d000) +#define HWIO_GCC_PCIE_PERST_HANDSHAKE_RMSK 0xe0000001 +#define HWIO_GCC_PCIE_PERST_HANDSHAKE_ATTR 0x3 +#define HWIO_GCC_PCIE_PERST_HANDSHAKE_IN \ + in_dword_masked(HWIO_GCC_PCIE_PERST_HANDSHAKE_ADDR, HWIO_GCC_PCIE_PERST_HANDSHAKE_RMSK) +#define HWIO_GCC_PCIE_PERST_HANDSHAKE_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_PERST_HANDSHAKE_ADDR, m) +#define HWIO_GCC_PCIE_PERST_HANDSHAKE_OUT(v) \ + out_dword(HWIO_GCC_PCIE_PERST_HANDSHAKE_ADDR,v) +#define HWIO_GCC_PCIE_PERST_HANDSHAKE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_PERST_HANDSHAKE_ADDR,m,v,HWIO_GCC_PCIE_PERST_HANDSHAKE_IN) +#define HWIO_GCC_PCIE_PERST_HANDSHAKE_TIMEOUT_STATUS_BMSK 0x80000000 +#define HWIO_GCC_PCIE_PERST_HANDSHAKE_TIMEOUT_STATUS_SHFT 0x1f +#define HWIO_GCC_PCIE_PERST_HANDSHAKE_FSM_STATUS_BMSK 0x60000000 +#define HWIO_GCC_PCIE_PERST_HANDSHAKE_FSM_STATUS_SHFT 0x1d +#define HWIO_GCC_PCIE_PERST_HANDSHAKE_TIMER_ENABLE_BMSK 0x1 +#define HWIO_GCC_PCIE_PERST_HANDSHAKE_TIMER_ENABLE_SHFT 0x0 +#define HWIO_GCC_PCIE_PERST_HANDSHAKE_TIMER_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_PERST_HANDSHAKE_TIMER_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_PERST_HANDSHAKE_TIMER_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007d004) +#define HWIO_GCC_PCIE_PERST_HANDSHAKE_TIMER_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d004) +#define HWIO_GCC_PCIE_PERST_HANDSHAKE_TIMER_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d004) +#define HWIO_GCC_PCIE_PERST_HANDSHAKE_TIMER_RMSK 0xffffffff +#define HWIO_GCC_PCIE_PERST_HANDSHAKE_TIMER_ATTR 0x3 +#define HWIO_GCC_PCIE_PERST_HANDSHAKE_TIMER_IN \ + in_dword_masked(HWIO_GCC_PCIE_PERST_HANDSHAKE_TIMER_ADDR, HWIO_GCC_PCIE_PERST_HANDSHAKE_TIMER_RMSK) +#define HWIO_GCC_PCIE_PERST_HANDSHAKE_TIMER_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_PERST_HANDSHAKE_TIMER_ADDR, m) +#define HWIO_GCC_PCIE_PERST_HANDSHAKE_TIMER_OUT(v) \ + out_dword(HWIO_GCC_PCIE_PERST_HANDSHAKE_TIMER_ADDR,v) +#define HWIO_GCC_PCIE_PERST_HANDSHAKE_TIMER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_PERST_HANDSHAKE_TIMER_ADDR,m,v,HWIO_GCC_PCIE_PERST_HANDSHAKE_TIMER_IN) +#define HWIO_GCC_PCIE_PERST_HANDSHAKE_TIMER_TIMER_VAL_BMSK 0xffffffff +#define HWIO_GCC_PCIE_PERST_HANDSHAKE_TIMER_TIMER_VAL_SHFT 0x0 + +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00084000) +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00084000) +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00084000) +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00081004) +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00081004) +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00081004) +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00081008) +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00081008) +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00081008) +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008100c) +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008100c) +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008100c) +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00081010) +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00081010) +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00081010) +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00081014) +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00081014) +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00081014) +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00081018) +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00081018) +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00081018) +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008101c) +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008101c) +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008101c) +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00081020) +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00081020) +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00081020) +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00081024) +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00081024) +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00081024) +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00081028) +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00081028) +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00081028) +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008102c) +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008102c) +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008102c) +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00081030) +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00081030) +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00081030) +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00081034) +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00081034) +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00081034) +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00081038) +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00081038) +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00081038) +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008103c) +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008103c) +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008103c) +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00082004) +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082004) +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082004) +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00082008) +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082008) +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082008) +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008200c) +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008200c) +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008200c) +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00082010) +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082010) +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082010) +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00082014) +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082014) +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082014) +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00082018) +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082018) +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082018) +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008201c) +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008201c) +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008201c) +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00082020) +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082020) +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082020) +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00082024) +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082024) +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082024) +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00082028) +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082028) +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082028) +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008202c) +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008202c) +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008202c) +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00082030) +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082030) +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082030) +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00082034) +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082034) +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082034) +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00082038) +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082038) +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082038) +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008203c) +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008203c) +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008203c) +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00082040) +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082040) +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082040) +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00083004) +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00083004) +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00083004) +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_ADDR, HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00083008) +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00083008) +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00083008) +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_ADDR, HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008300c) +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008300c) +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008300c) +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_ADDR, HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00083010) +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00083010) +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00083010) +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_ADDR, HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00083014) +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00083014) +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00083014) +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_ADDR, HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00083018) +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00083018) +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00083018) +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_ADDR, HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008301c) +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008301c) +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008301c) +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_ADDR, HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00083020) +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00083020) +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00083020) +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_ADDR, HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00083024) +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00083024) +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00083024) +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_ADDR, HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00083028) +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00083028) +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00083028) +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_ADDR, HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008302c) +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008302c) +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008302c) +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_ADDR, HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00083030) +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00083030) +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00083030) +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_ADDR, HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00083034) +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00083034) +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00083034) +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_ADDR, HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00083038) +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00083038) +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00083038) +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_ADDR, HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008303c) +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008303c) +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008303c) +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_ADDR, HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00083040) +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00083040) +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00083040) +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_ADDR, HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_QPIC_PERF0_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008b004) +#define HWIO_GCC_RPMH_QPIC_PERF0_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008b004) +#define HWIO_GCC_RPMH_QPIC_PERF0_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008b004) +#define HWIO_GCC_RPMH_QPIC_PERF0_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_QPIC_PERF0_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_PERF0_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_PERF0_ENA_VOTE_ADDR, HWIO_GCC_RPMH_QPIC_PERF0_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_QPIC_PERF0_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_PERF0_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_PERF0_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_PERF0_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_PERF0_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_PERF0_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_QPIC_PERF0_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_QPIC_PERF0_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_QPIC_PERF0_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_QPIC_PERF0_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF0_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF0_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_QPIC_PERF0_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_QPIC_PERF0_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF0_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF0_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_QPIC_PERF0_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_QPIC_PERF0_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF0_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF0_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_QPIC_PERF0_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF0_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF0_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF0_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF0_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF0_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF0_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_QPIC_PERF1_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008b008) +#define HWIO_GCC_RPMH_QPIC_PERF1_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008b008) +#define HWIO_GCC_RPMH_QPIC_PERF1_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008b008) +#define HWIO_GCC_RPMH_QPIC_PERF1_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_QPIC_PERF1_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_PERF1_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_PERF1_ENA_VOTE_ADDR, HWIO_GCC_RPMH_QPIC_PERF1_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_QPIC_PERF1_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_PERF1_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_PERF1_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_PERF1_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_PERF1_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_PERF1_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_QPIC_PERF1_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_QPIC_PERF1_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_QPIC_PERF1_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_QPIC_PERF1_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF1_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF1_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_QPIC_PERF1_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_QPIC_PERF1_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF1_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF1_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_QPIC_PERF1_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_QPIC_PERF1_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF1_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF1_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_QPIC_PERF1_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF1_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF1_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF1_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF1_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF1_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF1_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_QPIC_PERF2_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008b00c) +#define HWIO_GCC_RPMH_QPIC_PERF2_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008b00c) +#define HWIO_GCC_RPMH_QPIC_PERF2_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008b00c) +#define HWIO_GCC_RPMH_QPIC_PERF2_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_QPIC_PERF2_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_PERF2_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_PERF2_ENA_VOTE_ADDR, HWIO_GCC_RPMH_QPIC_PERF2_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_QPIC_PERF2_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_PERF2_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_PERF2_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_PERF2_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_PERF2_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_PERF2_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_QPIC_PERF2_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_QPIC_PERF2_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_QPIC_PERF2_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_QPIC_PERF2_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF2_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF2_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_QPIC_PERF2_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_QPIC_PERF2_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF2_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF2_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_QPIC_PERF2_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_QPIC_PERF2_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF2_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF2_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_QPIC_PERF2_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF2_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF2_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF2_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF2_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF2_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF2_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_QPIC_PERF3_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008b010) +#define HWIO_GCC_RPMH_QPIC_PERF3_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008b010) +#define HWIO_GCC_RPMH_QPIC_PERF3_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008b010) +#define HWIO_GCC_RPMH_QPIC_PERF3_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_QPIC_PERF3_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_PERF3_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_PERF3_ENA_VOTE_ADDR, HWIO_GCC_RPMH_QPIC_PERF3_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_QPIC_PERF3_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_PERF3_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_PERF3_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_PERF3_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_PERF3_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_PERF3_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_QPIC_PERF3_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_QPIC_PERF3_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_QPIC_PERF3_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_QPIC_PERF3_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF3_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF3_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_QPIC_PERF3_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_QPIC_PERF3_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF3_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF3_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_QPIC_PERF3_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_QPIC_PERF3_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF3_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF3_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_QPIC_PERF3_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF3_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF3_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF3_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF3_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF3_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF3_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_QPIC_PERF4_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008b014) +#define HWIO_GCC_RPMH_QPIC_PERF4_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008b014) +#define HWIO_GCC_RPMH_QPIC_PERF4_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008b014) +#define HWIO_GCC_RPMH_QPIC_PERF4_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_QPIC_PERF4_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_PERF4_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_PERF4_ENA_VOTE_ADDR, HWIO_GCC_RPMH_QPIC_PERF4_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_QPIC_PERF4_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_PERF4_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_PERF4_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_PERF4_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_PERF4_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_PERF4_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_QPIC_PERF4_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_QPIC_PERF4_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_QPIC_PERF4_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_QPIC_PERF4_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF4_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF4_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_QPIC_PERF4_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_QPIC_PERF4_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF4_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF4_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_QPIC_PERF4_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_QPIC_PERF4_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF4_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF4_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_QPIC_PERF4_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF4_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF4_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF4_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF4_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF4_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF4_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_QPIC_PERF5_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008b018) +#define HWIO_GCC_RPMH_QPIC_PERF5_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008b018) +#define HWIO_GCC_RPMH_QPIC_PERF5_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008b018) +#define HWIO_GCC_RPMH_QPIC_PERF5_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_QPIC_PERF5_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_PERF5_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_PERF5_ENA_VOTE_ADDR, HWIO_GCC_RPMH_QPIC_PERF5_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_QPIC_PERF5_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_PERF5_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_PERF5_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_PERF5_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_PERF5_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_PERF5_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_QPIC_PERF5_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_QPIC_PERF5_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_QPIC_PERF5_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_QPIC_PERF5_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF5_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF5_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_QPIC_PERF5_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_QPIC_PERF5_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF5_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF5_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_QPIC_PERF5_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_QPIC_PERF5_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF5_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF5_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_QPIC_PERF5_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF5_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF5_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF5_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF5_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF5_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF5_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_QPIC_PERF6_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008b01c) +#define HWIO_GCC_RPMH_QPIC_PERF6_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008b01c) +#define HWIO_GCC_RPMH_QPIC_PERF6_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008b01c) +#define HWIO_GCC_RPMH_QPIC_PERF6_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_QPIC_PERF6_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_PERF6_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_PERF6_ENA_VOTE_ADDR, HWIO_GCC_RPMH_QPIC_PERF6_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_QPIC_PERF6_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_PERF6_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_PERF6_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_PERF6_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_PERF6_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_PERF6_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_QPIC_PERF6_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_QPIC_PERF6_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_QPIC_PERF6_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_QPIC_PERF6_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF6_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF6_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_QPIC_PERF6_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_QPIC_PERF6_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF6_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF6_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_QPIC_PERF6_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_QPIC_PERF6_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF6_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF6_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_QPIC_PERF6_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF6_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF6_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF6_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF6_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF6_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF6_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_QPIC_PERF7_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008b020) +#define HWIO_GCC_RPMH_QPIC_PERF7_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008b020) +#define HWIO_GCC_RPMH_QPIC_PERF7_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008b020) +#define HWIO_GCC_RPMH_QPIC_PERF7_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_QPIC_PERF7_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_PERF7_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_PERF7_ENA_VOTE_ADDR, HWIO_GCC_RPMH_QPIC_PERF7_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_QPIC_PERF7_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_PERF7_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_PERF7_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_PERF7_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_PERF7_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_PERF7_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_QPIC_PERF7_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_QPIC_PERF7_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_QPIC_PERF7_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_QPIC_PERF7_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF7_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF7_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_QPIC_PERF7_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_QPIC_PERF7_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF7_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF7_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_QPIC_PERF7_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_QPIC_PERF7_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF7_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF7_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_QPIC_PERF7_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF7_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF7_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF7_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF7_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF7_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF7_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_QPIC_PERF8_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008b024) +#define HWIO_GCC_RPMH_QPIC_PERF8_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008b024) +#define HWIO_GCC_RPMH_QPIC_PERF8_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008b024) +#define HWIO_GCC_RPMH_QPIC_PERF8_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_QPIC_PERF8_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_PERF8_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_PERF8_ENA_VOTE_ADDR, HWIO_GCC_RPMH_QPIC_PERF8_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_QPIC_PERF8_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_PERF8_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_PERF8_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_PERF8_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_PERF8_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_PERF8_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_QPIC_PERF8_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_QPIC_PERF8_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_QPIC_PERF8_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_QPIC_PERF8_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF8_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF8_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_QPIC_PERF8_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_QPIC_PERF8_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF8_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF8_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_QPIC_PERF8_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_QPIC_PERF8_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF8_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF8_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_QPIC_PERF8_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF8_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF8_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF8_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF8_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF8_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF8_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_QPIC_PERF9_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008b028) +#define HWIO_GCC_RPMH_QPIC_PERF9_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008b028) +#define HWIO_GCC_RPMH_QPIC_PERF9_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008b028) +#define HWIO_GCC_RPMH_QPIC_PERF9_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_QPIC_PERF9_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_PERF9_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_PERF9_ENA_VOTE_ADDR, HWIO_GCC_RPMH_QPIC_PERF9_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_QPIC_PERF9_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_PERF9_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_PERF9_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_PERF9_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_PERF9_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_PERF9_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_QPIC_PERF9_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_QPIC_PERF9_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_QPIC_PERF9_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_QPIC_PERF9_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF9_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF9_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_QPIC_PERF9_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_QPIC_PERF9_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF9_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF9_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_QPIC_PERF9_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_QPIC_PERF9_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF9_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF9_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_QPIC_PERF9_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF9_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF9_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF9_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF9_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF9_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF9_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_QPIC_PERF10_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008b02c) +#define HWIO_GCC_RPMH_QPIC_PERF10_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008b02c) +#define HWIO_GCC_RPMH_QPIC_PERF10_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008b02c) +#define HWIO_GCC_RPMH_QPIC_PERF10_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_QPIC_PERF10_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_PERF10_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_PERF10_ENA_VOTE_ADDR, HWIO_GCC_RPMH_QPIC_PERF10_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_QPIC_PERF10_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_PERF10_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_PERF10_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_PERF10_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_PERF10_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_PERF10_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_QPIC_PERF10_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_QPIC_PERF10_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_QPIC_PERF10_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_QPIC_PERF10_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF10_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF10_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_QPIC_PERF10_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_QPIC_PERF10_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF10_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF10_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_QPIC_PERF10_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_QPIC_PERF10_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF10_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF10_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_QPIC_PERF10_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF10_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF10_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF10_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF10_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF10_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF10_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_QPIC_PERF11_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008b030) +#define HWIO_GCC_RPMH_QPIC_PERF11_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008b030) +#define HWIO_GCC_RPMH_QPIC_PERF11_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008b030) +#define HWIO_GCC_RPMH_QPIC_PERF11_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_QPIC_PERF11_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_PERF11_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_PERF11_ENA_VOTE_ADDR, HWIO_GCC_RPMH_QPIC_PERF11_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_QPIC_PERF11_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_PERF11_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_PERF11_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_PERF11_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_PERF11_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_PERF11_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_QPIC_PERF11_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_QPIC_PERF11_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_QPIC_PERF11_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_QPIC_PERF11_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF11_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF11_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_QPIC_PERF11_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_QPIC_PERF11_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF11_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF11_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_QPIC_PERF11_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_QPIC_PERF11_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF11_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF11_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_QPIC_PERF11_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF11_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF11_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF11_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF11_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF11_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF11_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_QPIC_PERF12_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008b034) +#define HWIO_GCC_RPMH_QPIC_PERF12_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008b034) +#define HWIO_GCC_RPMH_QPIC_PERF12_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008b034) +#define HWIO_GCC_RPMH_QPIC_PERF12_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_QPIC_PERF12_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_PERF12_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_PERF12_ENA_VOTE_ADDR, HWIO_GCC_RPMH_QPIC_PERF12_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_QPIC_PERF12_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_PERF12_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_PERF12_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_PERF12_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_PERF12_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_PERF12_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_QPIC_PERF12_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_QPIC_PERF12_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_QPIC_PERF12_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_QPIC_PERF12_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF12_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF12_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_QPIC_PERF12_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_QPIC_PERF12_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF12_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF12_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_QPIC_PERF12_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_QPIC_PERF12_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF12_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF12_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_QPIC_PERF12_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF12_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF12_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF12_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF12_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF12_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF12_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_QPIC_PERF13_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008b038) +#define HWIO_GCC_RPMH_QPIC_PERF13_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008b038) +#define HWIO_GCC_RPMH_QPIC_PERF13_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008b038) +#define HWIO_GCC_RPMH_QPIC_PERF13_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_QPIC_PERF13_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_PERF13_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_PERF13_ENA_VOTE_ADDR, HWIO_GCC_RPMH_QPIC_PERF13_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_QPIC_PERF13_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_PERF13_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_PERF13_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_PERF13_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_PERF13_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_PERF13_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_QPIC_PERF13_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_QPIC_PERF13_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_QPIC_PERF13_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_QPIC_PERF13_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF13_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF13_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_QPIC_PERF13_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_QPIC_PERF13_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF13_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF13_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_QPIC_PERF13_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_QPIC_PERF13_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF13_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF13_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_QPIC_PERF13_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF13_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF13_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF13_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF13_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF13_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF13_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_QPIC_PERF14_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008b03c) +#define HWIO_GCC_RPMH_QPIC_PERF14_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008b03c) +#define HWIO_GCC_RPMH_QPIC_PERF14_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008b03c) +#define HWIO_GCC_RPMH_QPIC_PERF14_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_QPIC_PERF14_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_PERF14_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_PERF14_ENA_VOTE_ADDR, HWIO_GCC_RPMH_QPIC_PERF14_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_QPIC_PERF14_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_PERF14_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_PERF14_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_PERF14_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_PERF14_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_PERF14_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_QPIC_PERF14_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_QPIC_PERF14_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_QPIC_PERF14_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_QPIC_PERF14_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF14_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF14_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_QPIC_PERF14_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_QPIC_PERF14_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF14_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF14_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_QPIC_PERF14_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_QPIC_PERF14_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF14_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF14_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_QPIC_PERF14_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF14_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF14_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF14_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF14_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF14_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF14_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_QPIC_PERF15_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008b040) +#define HWIO_GCC_RPMH_QPIC_PERF15_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008b040) +#define HWIO_GCC_RPMH_QPIC_PERF15_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008b040) +#define HWIO_GCC_RPMH_QPIC_PERF15_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_QPIC_PERF15_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_QPIC_PERF15_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_PERF15_ENA_VOTE_ADDR, HWIO_GCC_RPMH_QPIC_PERF15_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_QPIC_PERF15_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QPIC_PERF15_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_QPIC_PERF15_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QPIC_PERF15_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_QPIC_PERF15_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QPIC_PERF15_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_QPIC_PERF15_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_QPIC_PERF15_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_QPIC_PERF15_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_QPIC_PERF15_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF15_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF15_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_QPIC_PERF15_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_QPIC_PERF15_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF15_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF15_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_QPIC_PERF15_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_QPIC_PERF15_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF15_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF15_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_QPIC_PERF15_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF15_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF15_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF15_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_QPIC_PERF15_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF15_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QPIC_PERF15_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_PKA_PERF0_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00085004) +#define HWIO_GCC_RPMH_PKA_PERF0_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00085004) +#define HWIO_GCC_RPMH_PKA_PERF0_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00085004) +#define HWIO_GCC_RPMH_PKA_PERF0_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_PKA_PERF0_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_PKA_PERF0_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_PKA_PERF0_ENA_VOTE_ADDR, HWIO_GCC_RPMH_PKA_PERF0_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_PKA_PERF0_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PKA_PERF0_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_PKA_PERF0_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PKA_PERF0_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_PKA_PERF0_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PKA_PERF0_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_PKA_PERF0_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_PKA_PERF0_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_PKA_PERF0_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_PKA_PERF0_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF0_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF0_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_PKA_PERF0_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_PKA_PERF0_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF0_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF0_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_PKA_PERF0_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_PKA_PERF0_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF0_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF0_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_PKA_PERF0_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_PKA_PERF0_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF0_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF0_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_PKA_PERF0_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_PKA_PERF0_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF0_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_PKA_PERF1_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00085008) +#define HWIO_GCC_RPMH_PKA_PERF1_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00085008) +#define HWIO_GCC_RPMH_PKA_PERF1_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00085008) +#define HWIO_GCC_RPMH_PKA_PERF1_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_PKA_PERF1_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_PKA_PERF1_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_PKA_PERF1_ENA_VOTE_ADDR, HWIO_GCC_RPMH_PKA_PERF1_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_PKA_PERF1_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PKA_PERF1_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_PKA_PERF1_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PKA_PERF1_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_PKA_PERF1_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PKA_PERF1_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_PKA_PERF1_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_PKA_PERF1_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_PKA_PERF1_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_PKA_PERF1_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF1_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF1_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_PKA_PERF1_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_PKA_PERF1_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF1_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF1_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_PKA_PERF1_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_PKA_PERF1_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF1_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF1_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_PKA_PERF1_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_PKA_PERF1_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF1_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF1_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_PKA_PERF1_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_PKA_PERF1_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF1_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_PKA_PERF2_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008500c) +#define HWIO_GCC_RPMH_PKA_PERF2_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008500c) +#define HWIO_GCC_RPMH_PKA_PERF2_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008500c) +#define HWIO_GCC_RPMH_PKA_PERF2_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_PKA_PERF2_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_PKA_PERF2_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_PKA_PERF2_ENA_VOTE_ADDR, HWIO_GCC_RPMH_PKA_PERF2_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_PKA_PERF2_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PKA_PERF2_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_PKA_PERF2_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PKA_PERF2_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_PKA_PERF2_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PKA_PERF2_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_PKA_PERF2_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_PKA_PERF2_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_PKA_PERF2_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_PKA_PERF2_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF2_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF2_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_PKA_PERF2_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_PKA_PERF2_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF2_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF2_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_PKA_PERF2_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_PKA_PERF2_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF2_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF2_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_PKA_PERF2_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_PKA_PERF2_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF2_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF2_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_PKA_PERF2_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_PKA_PERF2_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF2_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_PKA_PERF3_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00085010) +#define HWIO_GCC_RPMH_PKA_PERF3_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00085010) +#define HWIO_GCC_RPMH_PKA_PERF3_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00085010) +#define HWIO_GCC_RPMH_PKA_PERF3_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_PKA_PERF3_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_PKA_PERF3_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_PKA_PERF3_ENA_VOTE_ADDR, HWIO_GCC_RPMH_PKA_PERF3_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_PKA_PERF3_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PKA_PERF3_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_PKA_PERF3_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PKA_PERF3_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_PKA_PERF3_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PKA_PERF3_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_PKA_PERF3_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_PKA_PERF3_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_PKA_PERF3_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_PKA_PERF3_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF3_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF3_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_PKA_PERF3_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_PKA_PERF3_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF3_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF3_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_PKA_PERF3_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_PKA_PERF3_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF3_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF3_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_PKA_PERF3_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_PKA_PERF3_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF3_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF3_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_PKA_PERF3_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_PKA_PERF3_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF3_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_PKA_PERF4_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00085014) +#define HWIO_GCC_RPMH_PKA_PERF4_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00085014) +#define HWIO_GCC_RPMH_PKA_PERF4_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00085014) +#define HWIO_GCC_RPMH_PKA_PERF4_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_PKA_PERF4_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_PKA_PERF4_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_PKA_PERF4_ENA_VOTE_ADDR, HWIO_GCC_RPMH_PKA_PERF4_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_PKA_PERF4_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PKA_PERF4_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_PKA_PERF4_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PKA_PERF4_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_PKA_PERF4_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PKA_PERF4_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_PKA_PERF4_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_PKA_PERF4_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_PKA_PERF4_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_PKA_PERF4_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF4_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF4_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_PKA_PERF4_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_PKA_PERF4_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF4_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF4_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_PKA_PERF4_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_PKA_PERF4_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF4_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF4_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_PKA_PERF4_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_PKA_PERF4_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF4_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF4_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_PKA_PERF4_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_PKA_PERF4_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF4_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_PKA_PERF5_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00085018) +#define HWIO_GCC_RPMH_PKA_PERF5_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00085018) +#define HWIO_GCC_RPMH_PKA_PERF5_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00085018) +#define HWIO_GCC_RPMH_PKA_PERF5_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_PKA_PERF5_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_PKA_PERF5_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_PKA_PERF5_ENA_VOTE_ADDR, HWIO_GCC_RPMH_PKA_PERF5_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_PKA_PERF5_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PKA_PERF5_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_PKA_PERF5_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PKA_PERF5_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_PKA_PERF5_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PKA_PERF5_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_PKA_PERF5_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_PKA_PERF5_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_PKA_PERF5_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_PKA_PERF5_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF5_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF5_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_PKA_PERF5_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_PKA_PERF5_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF5_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF5_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_PKA_PERF5_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_PKA_PERF5_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF5_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF5_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_PKA_PERF5_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_PKA_PERF5_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF5_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF5_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_PKA_PERF5_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_PKA_PERF5_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF5_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_PKA_PERF6_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008501c) +#define HWIO_GCC_RPMH_PKA_PERF6_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008501c) +#define HWIO_GCC_RPMH_PKA_PERF6_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008501c) +#define HWIO_GCC_RPMH_PKA_PERF6_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_PKA_PERF6_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_PKA_PERF6_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_PKA_PERF6_ENA_VOTE_ADDR, HWIO_GCC_RPMH_PKA_PERF6_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_PKA_PERF6_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PKA_PERF6_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_PKA_PERF6_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PKA_PERF6_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_PKA_PERF6_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PKA_PERF6_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_PKA_PERF6_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_PKA_PERF6_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_PKA_PERF6_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_PKA_PERF6_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF6_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF6_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_PKA_PERF6_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_PKA_PERF6_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF6_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF6_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_PKA_PERF6_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_PKA_PERF6_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF6_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF6_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_PKA_PERF6_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_PKA_PERF6_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF6_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF6_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_PKA_PERF6_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_PKA_PERF6_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF6_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_PKA_PERF7_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00085020) +#define HWIO_GCC_RPMH_PKA_PERF7_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00085020) +#define HWIO_GCC_RPMH_PKA_PERF7_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00085020) +#define HWIO_GCC_RPMH_PKA_PERF7_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_PKA_PERF7_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_PKA_PERF7_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_PKA_PERF7_ENA_VOTE_ADDR, HWIO_GCC_RPMH_PKA_PERF7_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_PKA_PERF7_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PKA_PERF7_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_PKA_PERF7_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PKA_PERF7_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_PKA_PERF7_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PKA_PERF7_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_PKA_PERF7_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_PKA_PERF7_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_PKA_PERF7_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_PKA_PERF7_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF7_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF7_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_PKA_PERF7_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_PKA_PERF7_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF7_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF7_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_PKA_PERF7_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_PKA_PERF7_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF7_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF7_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_PKA_PERF7_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_PKA_PERF7_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF7_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF7_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_PKA_PERF7_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_PKA_PERF7_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF7_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_PKA_PERF8_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00085024) +#define HWIO_GCC_RPMH_PKA_PERF8_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00085024) +#define HWIO_GCC_RPMH_PKA_PERF8_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00085024) +#define HWIO_GCC_RPMH_PKA_PERF8_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_PKA_PERF8_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_PKA_PERF8_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_PKA_PERF8_ENA_VOTE_ADDR, HWIO_GCC_RPMH_PKA_PERF8_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_PKA_PERF8_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PKA_PERF8_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_PKA_PERF8_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PKA_PERF8_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_PKA_PERF8_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PKA_PERF8_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_PKA_PERF8_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_PKA_PERF8_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_PKA_PERF8_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_PKA_PERF8_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF8_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF8_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_PKA_PERF8_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_PKA_PERF8_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF8_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF8_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_PKA_PERF8_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_PKA_PERF8_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF8_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF8_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_PKA_PERF8_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_PKA_PERF8_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF8_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF8_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_PKA_PERF8_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_PKA_PERF8_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF8_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_PKA_PERF9_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00085028) +#define HWIO_GCC_RPMH_PKA_PERF9_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00085028) +#define HWIO_GCC_RPMH_PKA_PERF9_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00085028) +#define HWIO_GCC_RPMH_PKA_PERF9_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_PKA_PERF9_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_PKA_PERF9_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_PKA_PERF9_ENA_VOTE_ADDR, HWIO_GCC_RPMH_PKA_PERF9_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_PKA_PERF9_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PKA_PERF9_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_PKA_PERF9_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PKA_PERF9_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_PKA_PERF9_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PKA_PERF9_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_PKA_PERF9_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_PKA_PERF9_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_PKA_PERF9_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_PKA_PERF9_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF9_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF9_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_PKA_PERF9_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_PKA_PERF9_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF9_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF9_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_PKA_PERF9_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_PKA_PERF9_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF9_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF9_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_PKA_PERF9_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_PKA_PERF9_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF9_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF9_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_PKA_PERF9_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_PKA_PERF9_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF9_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_PKA_PERF10_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008502c) +#define HWIO_GCC_RPMH_PKA_PERF10_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008502c) +#define HWIO_GCC_RPMH_PKA_PERF10_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008502c) +#define HWIO_GCC_RPMH_PKA_PERF10_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_PKA_PERF10_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_PKA_PERF10_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_PKA_PERF10_ENA_VOTE_ADDR, HWIO_GCC_RPMH_PKA_PERF10_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_PKA_PERF10_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PKA_PERF10_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_PKA_PERF10_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PKA_PERF10_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_PKA_PERF10_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PKA_PERF10_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_PKA_PERF10_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_PKA_PERF10_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_PKA_PERF10_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_PKA_PERF10_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF10_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF10_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_PKA_PERF10_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_PKA_PERF10_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF10_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF10_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_PKA_PERF10_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_PKA_PERF10_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF10_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF10_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_PKA_PERF10_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_PKA_PERF10_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF10_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF10_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_PKA_PERF10_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_PKA_PERF10_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF10_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_PKA_PERF11_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00085030) +#define HWIO_GCC_RPMH_PKA_PERF11_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00085030) +#define HWIO_GCC_RPMH_PKA_PERF11_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00085030) +#define HWIO_GCC_RPMH_PKA_PERF11_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_PKA_PERF11_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_PKA_PERF11_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_PKA_PERF11_ENA_VOTE_ADDR, HWIO_GCC_RPMH_PKA_PERF11_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_PKA_PERF11_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PKA_PERF11_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_PKA_PERF11_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PKA_PERF11_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_PKA_PERF11_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PKA_PERF11_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_PKA_PERF11_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_PKA_PERF11_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_PKA_PERF11_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_PKA_PERF11_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF11_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF11_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_PKA_PERF11_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_PKA_PERF11_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF11_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF11_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_PKA_PERF11_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_PKA_PERF11_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF11_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF11_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_PKA_PERF11_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_PKA_PERF11_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF11_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF11_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_PKA_PERF11_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_PKA_PERF11_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF11_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_PKA_PERF12_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00085034) +#define HWIO_GCC_RPMH_PKA_PERF12_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00085034) +#define HWIO_GCC_RPMH_PKA_PERF12_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00085034) +#define HWIO_GCC_RPMH_PKA_PERF12_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_PKA_PERF12_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_PKA_PERF12_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_PKA_PERF12_ENA_VOTE_ADDR, HWIO_GCC_RPMH_PKA_PERF12_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_PKA_PERF12_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PKA_PERF12_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_PKA_PERF12_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PKA_PERF12_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_PKA_PERF12_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PKA_PERF12_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_PKA_PERF12_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_PKA_PERF12_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_PKA_PERF12_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_PKA_PERF12_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF12_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF12_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_PKA_PERF12_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_PKA_PERF12_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF12_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF12_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_PKA_PERF12_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_PKA_PERF12_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF12_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF12_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_PKA_PERF12_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_PKA_PERF12_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF12_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF12_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_PKA_PERF12_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_PKA_PERF12_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF12_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_PKA_PERF13_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00085038) +#define HWIO_GCC_RPMH_PKA_PERF13_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00085038) +#define HWIO_GCC_RPMH_PKA_PERF13_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00085038) +#define HWIO_GCC_RPMH_PKA_PERF13_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_PKA_PERF13_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_PKA_PERF13_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_PKA_PERF13_ENA_VOTE_ADDR, HWIO_GCC_RPMH_PKA_PERF13_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_PKA_PERF13_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PKA_PERF13_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_PKA_PERF13_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PKA_PERF13_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_PKA_PERF13_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PKA_PERF13_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_PKA_PERF13_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_PKA_PERF13_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_PKA_PERF13_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_PKA_PERF13_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF13_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF13_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_PKA_PERF13_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_PKA_PERF13_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF13_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF13_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_PKA_PERF13_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_PKA_PERF13_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF13_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF13_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_PKA_PERF13_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_PKA_PERF13_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF13_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF13_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_PKA_PERF13_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_PKA_PERF13_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF13_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_PKA_PERF14_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008503c) +#define HWIO_GCC_RPMH_PKA_PERF14_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008503c) +#define HWIO_GCC_RPMH_PKA_PERF14_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008503c) +#define HWIO_GCC_RPMH_PKA_PERF14_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_PKA_PERF14_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_PKA_PERF14_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_PKA_PERF14_ENA_VOTE_ADDR, HWIO_GCC_RPMH_PKA_PERF14_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_PKA_PERF14_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PKA_PERF14_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_PKA_PERF14_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PKA_PERF14_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_PKA_PERF14_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PKA_PERF14_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_PKA_PERF14_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_PKA_PERF14_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_PKA_PERF14_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_PKA_PERF14_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF14_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF14_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_PKA_PERF14_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_PKA_PERF14_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF14_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF14_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_PKA_PERF14_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_PKA_PERF14_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF14_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF14_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_PKA_PERF14_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_PKA_PERF14_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF14_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF14_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_PKA_PERF14_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_PKA_PERF14_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF14_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_PKA_PERF15_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00085040) +#define HWIO_GCC_RPMH_PKA_PERF15_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00085040) +#define HWIO_GCC_RPMH_PKA_PERF15_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00085040) +#define HWIO_GCC_RPMH_PKA_PERF15_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_PKA_PERF15_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_PKA_PERF15_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_PKA_PERF15_ENA_VOTE_ADDR, HWIO_GCC_RPMH_PKA_PERF15_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_PKA_PERF15_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PKA_PERF15_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_PKA_PERF15_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PKA_PERF15_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_PKA_PERF15_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PKA_PERF15_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_PKA_PERF15_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_PKA_PERF15_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_PKA_PERF15_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_PKA_PERF15_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF15_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF15_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_PKA_PERF15_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_PKA_PERF15_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF15_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF15_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_PKA_PERF15_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_PKA_PERF15_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF15_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF15_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_PKA_PERF15_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_PKA_PERF15_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF15_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PKA_PERF15_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_PKA_PERF15_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_PKA_PERF15_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PKA_PERF15_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00084004) +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00084004) +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00084004) +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00084008) +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00084008) +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00084008) +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008400c) +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008400c) +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008400c) +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00084010) +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00084010) +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00084010) +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00084014) +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00084014) +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00084014) +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00084018) +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00084018) +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00084018) +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008401c) +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008401c) +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008401c) +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00084020) +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00084020) +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00084020) +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00084024) +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00084024) +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00084024) +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00084028) +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00084028) +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00084028) +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008402c) +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008402c) +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008402c) +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00084030) +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00084030) +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00084030) +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00084034) +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00084034) +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00084034) +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00084038) +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00084038) +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00084038) +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008403c) +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008403c) +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008403c) +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00084040) +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00084040) +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00084040) +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00086004) +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00086004) +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00086004) +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00086008) +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00086008) +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00086008) +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008600c) +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008600c) +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008600c) +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00086010) +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00086010) +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00086010) +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00086014) +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00086014) +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00086014) +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00086018) +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00086018) +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00086018) +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008601c) +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008601c) +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008601c) +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00086020) +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00086020) +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00086020) +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00086024) +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00086024) +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00086024) +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00086028) +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00086028) +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00086028) +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008602c) +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008602c) +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008602c) +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00086030) +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00086030) +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00086030) +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00086034) +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00086034) +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00086034) +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00086038) +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00086038) +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00086038) +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008603c) +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008603c) +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008603c) +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00086040) +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00086040) +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00086040) +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00087004) +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00087004) +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00087004) +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00087008) +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00087008) +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00087008) +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008700c) +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008700c) +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008700c) +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00087010) +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00087010) +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00087010) +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00087014) +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00087014) +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00087014) +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00087018) +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00087018) +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00087018) +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008701c) +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008701c) +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008701c) +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00087020) +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00087020) +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00087020) +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00087024) +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00087024) +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00087024) +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00087028) +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00087028) +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00087028) +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008702c) +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008702c) +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008702c) +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00087030) +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00087030) +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00087030) +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00087034) +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00087034) +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00087034) +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00087038) +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00087038) +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00087038) +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008703c) +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008703c) +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008703c) +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00087040) +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00087040) +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00087040) +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008a004) +#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a004) +#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a004) +#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_RMSK 0x3f +#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_ADDR, HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_GCC_MODE_BMSK 0x20 +#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_GCC_MODE_SHFT 0x5 +#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_GCC_MODE_GCC_MODE_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_GCC_MODE_GCC_MODE_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008a008) +#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a008) +#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a008) +#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_RMSK 0x3f +#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_ADDR, HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_GCC_MODE_BMSK 0x20 +#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_GCC_MODE_SHFT 0x5 +#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_GCC_MODE_GCC_MODE_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_GCC_MODE_GCC_MODE_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008a00c) +#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a00c) +#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a00c) +#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_RMSK 0x3f +#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_ADDR, HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_GCC_MODE_BMSK 0x20 +#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_GCC_MODE_SHFT 0x5 +#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_GCC_MODE_GCC_MODE_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_GCC_MODE_GCC_MODE_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008a010) +#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a010) +#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a010) +#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_RMSK 0x3f +#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_ADDR, HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_GCC_MODE_BMSK 0x20 +#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_GCC_MODE_SHFT 0x5 +#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_GCC_MODE_GCC_MODE_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_GCC_MODE_GCC_MODE_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008a014) +#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a014) +#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a014) +#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_RMSK 0x3f +#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_ADDR, HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_GCC_MODE_BMSK 0x20 +#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_GCC_MODE_SHFT 0x5 +#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_GCC_MODE_GCC_MODE_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_GCC_MODE_GCC_MODE_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008a018) +#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a018) +#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a018) +#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_RMSK 0x3f +#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_ADDR, HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_GCC_MODE_BMSK 0x20 +#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_GCC_MODE_SHFT 0x5 +#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_GCC_MODE_GCC_MODE_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_GCC_MODE_GCC_MODE_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008a01c) +#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a01c) +#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a01c) +#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_RMSK 0x3f +#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_ADDR, HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_GCC_MODE_BMSK 0x20 +#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_GCC_MODE_SHFT 0x5 +#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_GCC_MODE_GCC_MODE_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_GCC_MODE_GCC_MODE_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008a020) +#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a020) +#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a020) +#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_RMSK 0x3f +#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_ADDR, HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_GCC_MODE_BMSK 0x20 +#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_GCC_MODE_SHFT 0x5 +#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_GCC_MODE_GCC_MODE_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_GCC_MODE_GCC_MODE_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008a024) +#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a024) +#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a024) +#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_RMSK 0x3f +#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_ADDR, HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_GCC_MODE_BMSK 0x20 +#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_GCC_MODE_SHFT 0x5 +#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_GCC_MODE_GCC_MODE_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_GCC_MODE_GCC_MODE_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008a028) +#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a028) +#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a028) +#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_RMSK 0x3f +#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_ADDR, HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_GCC_MODE_BMSK 0x20 +#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_GCC_MODE_SHFT 0x5 +#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_GCC_MODE_GCC_MODE_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_GCC_MODE_GCC_MODE_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008a02c) +#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a02c) +#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a02c) +#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_RMSK 0x3f +#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_ADDR, HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_GCC_MODE_BMSK 0x20 +#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_GCC_MODE_SHFT 0x5 +#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_GCC_MODE_GCC_MODE_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_GCC_MODE_GCC_MODE_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008a030) +#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a030) +#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a030) +#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_RMSK 0x3f +#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_ADDR, HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_GCC_MODE_BMSK 0x20 +#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_GCC_MODE_SHFT 0x5 +#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_GCC_MODE_GCC_MODE_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_GCC_MODE_GCC_MODE_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008a034) +#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a034) +#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a034) +#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_RMSK 0x3f +#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_ADDR, HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_GCC_MODE_BMSK 0x20 +#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_GCC_MODE_SHFT 0x5 +#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_GCC_MODE_GCC_MODE_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_GCC_MODE_GCC_MODE_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008a038) +#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a038) +#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a038) +#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_RMSK 0x3f +#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_ADDR, HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_GCC_MODE_BMSK 0x20 +#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_GCC_MODE_SHFT 0x5 +#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_GCC_MODE_GCC_MODE_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_GCC_MODE_GCC_MODE_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008a03c) +#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a03c) +#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a03c) +#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_RMSK 0x3f +#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_ADDR, HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_GCC_MODE_BMSK 0x20 +#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_GCC_MODE_SHFT 0x5 +#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_GCC_MODE_GCC_MODE_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_GCC_MODE_GCC_MODE_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008a040) +#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a040) +#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a040) +#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_RMSK 0x3f +#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_ADDR, HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_GCC_MODE_BMSK 0x20 +#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_GCC_MODE_SHFT 0x5 +#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_GCC_MODE_GCC_MODE_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_GCC_MODE_GCC_MODE_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_GPLL5_BMSK 0x10 +#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_GPLL5_SHFT 0x4 +#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_GPLL4_BMSK 0x8 +#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_GPLL4_SHFT 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_GPLL2_3_BMSK 0x4 +#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_GPLL2_3_SHFT 0x2 +#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_GPLL2_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_GPLL2_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_L_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00088004) +#define HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_L_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00088004) +#define HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_L_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00088004) +#define HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_L_VAL_RMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_L_VAL_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_L_VAL_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_L_VAL_ADDR, HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_L_VAL_RMSK) +#define HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_L_VAL_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_L_VAL_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_L_VAL_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_L_VAL_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_L_VAL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_L_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_L_VAL_IN) +#define HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_L_VAL_PLL_L_BMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_L_VAL_PLL_L_SHFT 0x0 + +#define HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_L_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00088008) +#define HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_L_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00088008) +#define HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_L_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00088008) +#define HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_L_VAL_RMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_L_VAL_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_L_VAL_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_L_VAL_ADDR, HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_L_VAL_RMSK) +#define HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_L_VAL_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_L_VAL_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_L_VAL_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_L_VAL_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_L_VAL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_L_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_L_VAL_IN) +#define HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_L_VAL_PLL_L_BMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_L_VAL_PLL_L_SHFT 0x0 + +#define HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_L_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008800c) +#define HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_L_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008800c) +#define HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_L_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008800c) +#define HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_L_VAL_RMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_L_VAL_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_L_VAL_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_L_VAL_ADDR, HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_L_VAL_RMSK) +#define HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_L_VAL_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_L_VAL_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_L_VAL_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_L_VAL_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_L_VAL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_L_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_L_VAL_IN) +#define HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_L_VAL_PLL_L_BMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_L_VAL_PLL_L_SHFT 0x0 + +#define HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_L_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00088010) +#define HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_L_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00088010) +#define HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_L_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00088010) +#define HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_L_VAL_RMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_L_VAL_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_L_VAL_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_L_VAL_ADDR, HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_L_VAL_RMSK) +#define HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_L_VAL_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_L_VAL_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_L_VAL_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_L_VAL_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_L_VAL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_L_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_L_VAL_IN) +#define HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_L_VAL_PLL_L_BMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_L_VAL_PLL_L_SHFT 0x0 + +#define HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_L_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00088014) +#define HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_L_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00088014) +#define HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_L_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00088014) +#define HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_L_VAL_RMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_L_VAL_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_L_VAL_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_L_VAL_ADDR, HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_L_VAL_RMSK) +#define HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_L_VAL_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_L_VAL_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_L_VAL_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_L_VAL_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_L_VAL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_L_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_L_VAL_IN) +#define HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_L_VAL_PLL_L_BMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_L_VAL_PLL_L_SHFT 0x0 + +#define HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_L_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00088018) +#define HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_L_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00088018) +#define HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_L_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00088018) +#define HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_L_VAL_RMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_L_VAL_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_L_VAL_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_L_VAL_ADDR, HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_L_VAL_RMSK) +#define HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_L_VAL_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_L_VAL_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_L_VAL_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_L_VAL_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_L_VAL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_L_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_L_VAL_IN) +#define HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_L_VAL_PLL_L_BMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_L_VAL_PLL_L_SHFT 0x0 + +#define HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_L_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008801c) +#define HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_L_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008801c) +#define HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_L_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008801c) +#define HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_L_VAL_RMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_L_VAL_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_L_VAL_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_L_VAL_ADDR, HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_L_VAL_RMSK) +#define HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_L_VAL_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_L_VAL_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_L_VAL_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_L_VAL_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_L_VAL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_L_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_L_VAL_IN) +#define HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_L_VAL_PLL_L_BMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_L_VAL_PLL_L_SHFT 0x0 + +#define HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_L_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00088020) +#define HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_L_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00088020) +#define HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_L_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00088020) +#define HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_L_VAL_RMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_L_VAL_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_L_VAL_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_L_VAL_ADDR, HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_L_VAL_RMSK) +#define HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_L_VAL_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_L_VAL_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_L_VAL_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_L_VAL_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_L_VAL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_L_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_L_VAL_IN) +#define HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_L_VAL_PLL_L_BMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_L_VAL_PLL_L_SHFT 0x0 + +#define HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_L_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00088024) +#define HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_L_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00088024) +#define HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_L_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00088024) +#define HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_L_VAL_RMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_L_VAL_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_L_VAL_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_L_VAL_ADDR, HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_L_VAL_RMSK) +#define HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_L_VAL_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_L_VAL_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_L_VAL_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_L_VAL_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_L_VAL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_L_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_L_VAL_IN) +#define HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_L_VAL_PLL_L_BMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_L_VAL_PLL_L_SHFT 0x0 + +#define HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_L_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00088028) +#define HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_L_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00088028) +#define HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_L_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00088028) +#define HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_L_VAL_RMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_L_VAL_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_L_VAL_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_L_VAL_ADDR, HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_L_VAL_RMSK) +#define HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_L_VAL_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_L_VAL_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_L_VAL_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_L_VAL_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_L_VAL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_L_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_L_VAL_IN) +#define HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_L_VAL_PLL_L_BMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_L_VAL_PLL_L_SHFT 0x0 + +#define HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_L_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008802c) +#define HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_L_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008802c) +#define HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_L_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008802c) +#define HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_L_VAL_RMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_L_VAL_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_L_VAL_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_L_VAL_ADDR, HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_L_VAL_RMSK) +#define HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_L_VAL_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_L_VAL_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_L_VAL_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_L_VAL_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_L_VAL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_L_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_L_VAL_IN) +#define HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_L_VAL_PLL_L_BMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_L_VAL_PLL_L_SHFT 0x0 + +#define HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_L_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00088030) +#define HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_L_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00088030) +#define HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_L_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00088030) +#define HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_L_VAL_RMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_L_VAL_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_L_VAL_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_L_VAL_ADDR, HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_L_VAL_RMSK) +#define HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_L_VAL_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_L_VAL_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_L_VAL_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_L_VAL_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_L_VAL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_L_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_L_VAL_IN) +#define HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_L_VAL_PLL_L_BMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_L_VAL_PLL_L_SHFT 0x0 + +#define HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_L_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00088034) +#define HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_L_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00088034) +#define HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_L_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00088034) +#define HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_L_VAL_RMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_L_VAL_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_L_VAL_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_L_VAL_ADDR, HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_L_VAL_RMSK) +#define HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_L_VAL_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_L_VAL_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_L_VAL_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_L_VAL_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_L_VAL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_L_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_L_VAL_IN) +#define HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_L_VAL_PLL_L_BMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_L_VAL_PLL_L_SHFT 0x0 + +#define HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_L_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00088038) +#define HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_L_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00088038) +#define HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_L_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00088038) +#define HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_L_VAL_RMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_L_VAL_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_L_VAL_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_L_VAL_ADDR, HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_L_VAL_RMSK) +#define HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_L_VAL_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_L_VAL_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_L_VAL_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_L_VAL_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_L_VAL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_L_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_L_VAL_IN) +#define HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_L_VAL_PLL_L_BMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_L_VAL_PLL_L_SHFT 0x0 + +#define HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_L_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008803c) +#define HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_L_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008803c) +#define HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_L_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008803c) +#define HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_L_VAL_RMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_L_VAL_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_L_VAL_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_L_VAL_ADDR, HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_L_VAL_RMSK) +#define HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_L_VAL_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_L_VAL_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_L_VAL_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_L_VAL_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_L_VAL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_L_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_L_VAL_IN) +#define HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_L_VAL_PLL_L_BMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_L_VAL_PLL_L_SHFT 0x0 + +#define HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_L_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00088040) +#define HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_L_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00088040) +#define HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_L_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00088040) +#define HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_L_VAL_RMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_L_VAL_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_L_VAL_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_L_VAL_ADDR, HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_L_VAL_RMSK) +#define HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_L_VAL_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_L_VAL_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_L_VAL_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_L_VAL_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_L_VAL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_L_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_L_VAL_IN) +#define HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_L_VAL_PLL_L_BMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_L_VAL_PLL_L_SHFT 0x0 + +#define HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_FRAC_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00089004) +#define HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_FRAC_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00089004) +#define HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_FRAC_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00089004) +#define HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_FRAC_VAL_RMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_FRAC_VAL_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_FRAC_VAL_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_FRAC_VAL_ADDR, HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_FRAC_VAL_RMSK) +#define HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_FRAC_VAL_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_FRAC_VAL_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_FRAC_VAL_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_FRAC_VAL_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_FRAC_VAL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_FRAC_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_FRAC_VAL_IN) +#define HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_BMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_SHFT 0x0 + +#define HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_FRAC_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00089008) +#define HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_FRAC_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00089008) +#define HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_FRAC_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00089008) +#define HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_FRAC_VAL_RMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_FRAC_VAL_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_FRAC_VAL_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_FRAC_VAL_ADDR, HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_FRAC_VAL_RMSK) +#define HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_FRAC_VAL_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_FRAC_VAL_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_FRAC_VAL_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_FRAC_VAL_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_FRAC_VAL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_FRAC_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_FRAC_VAL_IN) +#define HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_BMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_SHFT 0x0 + +#define HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_FRAC_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008900c) +#define HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_FRAC_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008900c) +#define HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_FRAC_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008900c) +#define HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_FRAC_VAL_RMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_FRAC_VAL_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_FRAC_VAL_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_FRAC_VAL_ADDR, HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_FRAC_VAL_RMSK) +#define HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_FRAC_VAL_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_FRAC_VAL_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_FRAC_VAL_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_FRAC_VAL_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_FRAC_VAL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_FRAC_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_FRAC_VAL_IN) +#define HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_BMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_SHFT 0x0 + +#define HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_FRAC_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00089010) +#define HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_FRAC_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00089010) +#define HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_FRAC_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00089010) +#define HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_FRAC_VAL_RMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_FRAC_VAL_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_FRAC_VAL_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_FRAC_VAL_ADDR, HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_FRAC_VAL_RMSK) +#define HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_FRAC_VAL_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_FRAC_VAL_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_FRAC_VAL_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_FRAC_VAL_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_FRAC_VAL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_FRAC_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_FRAC_VAL_IN) +#define HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_BMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_SHFT 0x0 + +#define HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_FRAC_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00089014) +#define HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_FRAC_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00089014) +#define HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_FRAC_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00089014) +#define HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_FRAC_VAL_RMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_FRAC_VAL_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_FRAC_VAL_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_FRAC_VAL_ADDR, HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_FRAC_VAL_RMSK) +#define HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_FRAC_VAL_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_FRAC_VAL_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_FRAC_VAL_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_FRAC_VAL_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_FRAC_VAL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_FRAC_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_FRAC_VAL_IN) +#define HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_BMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_SHFT 0x0 + +#define HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_FRAC_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00089018) +#define HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_FRAC_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00089018) +#define HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_FRAC_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00089018) +#define HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_FRAC_VAL_RMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_FRAC_VAL_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_FRAC_VAL_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_FRAC_VAL_ADDR, HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_FRAC_VAL_RMSK) +#define HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_FRAC_VAL_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_FRAC_VAL_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_FRAC_VAL_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_FRAC_VAL_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_FRAC_VAL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_FRAC_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_FRAC_VAL_IN) +#define HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_BMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_SHFT 0x0 + +#define HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_FRAC_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008901c) +#define HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_FRAC_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008901c) +#define HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_FRAC_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008901c) +#define HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_FRAC_VAL_RMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_FRAC_VAL_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_FRAC_VAL_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_FRAC_VAL_ADDR, HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_FRAC_VAL_RMSK) +#define HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_FRAC_VAL_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_FRAC_VAL_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_FRAC_VAL_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_FRAC_VAL_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_FRAC_VAL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_FRAC_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_FRAC_VAL_IN) +#define HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_BMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_SHFT 0x0 + +#define HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_FRAC_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00089020) +#define HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_FRAC_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00089020) +#define HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_FRAC_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00089020) +#define HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_FRAC_VAL_RMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_FRAC_VAL_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_FRAC_VAL_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_FRAC_VAL_ADDR, HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_FRAC_VAL_RMSK) +#define HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_FRAC_VAL_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_FRAC_VAL_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_FRAC_VAL_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_FRAC_VAL_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_FRAC_VAL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_FRAC_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_FRAC_VAL_IN) +#define HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_BMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_SHFT 0x0 + +#define HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_FRAC_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00089024) +#define HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_FRAC_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00089024) +#define HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_FRAC_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00089024) +#define HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_FRAC_VAL_RMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_FRAC_VAL_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_FRAC_VAL_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_FRAC_VAL_ADDR, HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_FRAC_VAL_RMSK) +#define HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_FRAC_VAL_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_FRAC_VAL_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_FRAC_VAL_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_FRAC_VAL_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_FRAC_VAL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_FRAC_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_FRAC_VAL_IN) +#define HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_BMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_SHFT 0x0 + +#define HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_FRAC_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00089028) +#define HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_FRAC_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00089028) +#define HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_FRAC_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00089028) +#define HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_FRAC_VAL_RMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_FRAC_VAL_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_FRAC_VAL_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_FRAC_VAL_ADDR, HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_FRAC_VAL_RMSK) +#define HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_FRAC_VAL_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_FRAC_VAL_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_FRAC_VAL_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_FRAC_VAL_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_FRAC_VAL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_FRAC_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_FRAC_VAL_IN) +#define HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_BMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_SHFT 0x0 + +#define HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_FRAC_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008902c) +#define HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_FRAC_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008902c) +#define HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_FRAC_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008902c) +#define HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_FRAC_VAL_RMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_FRAC_VAL_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_FRAC_VAL_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_FRAC_VAL_ADDR, HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_FRAC_VAL_RMSK) +#define HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_FRAC_VAL_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_FRAC_VAL_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_FRAC_VAL_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_FRAC_VAL_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_FRAC_VAL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_FRAC_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_FRAC_VAL_IN) +#define HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_BMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_SHFT 0x0 + +#define HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_FRAC_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00089030) +#define HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_FRAC_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00089030) +#define HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_FRAC_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00089030) +#define HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_FRAC_VAL_RMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_FRAC_VAL_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_FRAC_VAL_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_FRAC_VAL_ADDR, HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_FRAC_VAL_RMSK) +#define HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_FRAC_VAL_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_FRAC_VAL_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_FRAC_VAL_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_FRAC_VAL_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_FRAC_VAL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_FRAC_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_FRAC_VAL_IN) +#define HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_BMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_SHFT 0x0 + +#define HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_FRAC_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00089034) +#define HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_FRAC_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00089034) +#define HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_FRAC_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00089034) +#define HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_FRAC_VAL_RMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_FRAC_VAL_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_FRAC_VAL_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_FRAC_VAL_ADDR, HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_FRAC_VAL_RMSK) +#define HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_FRAC_VAL_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_FRAC_VAL_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_FRAC_VAL_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_FRAC_VAL_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_FRAC_VAL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_FRAC_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_FRAC_VAL_IN) +#define HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_BMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_SHFT 0x0 + +#define HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_FRAC_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00089038) +#define HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_FRAC_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00089038) +#define HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_FRAC_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00089038) +#define HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_FRAC_VAL_RMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_FRAC_VAL_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_FRAC_VAL_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_FRAC_VAL_ADDR, HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_FRAC_VAL_RMSK) +#define HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_FRAC_VAL_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_FRAC_VAL_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_FRAC_VAL_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_FRAC_VAL_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_FRAC_VAL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_FRAC_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_FRAC_VAL_IN) +#define HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_BMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_SHFT 0x0 + +#define HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_FRAC_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008903c) +#define HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_FRAC_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008903c) +#define HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_FRAC_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008903c) +#define HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_FRAC_VAL_RMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_FRAC_VAL_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_FRAC_VAL_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_FRAC_VAL_ADDR, HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_FRAC_VAL_RMSK) +#define HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_FRAC_VAL_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_FRAC_VAL_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_FRAC_VAL_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_FRAC_VAL_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_FRAC_VAL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_FRAC_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_FRAC_VAL_IN) +#define HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_BMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_SHFT 0x0 + +#define HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_FRAC_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00089040) +#define HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_FRAC_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00089040) +#define HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_FRAC_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00089040) +#define HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_FRAC_VAL_RMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_FRAC_VAL_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_FRAC_VAL_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_FRAC_VAL_ADDR, HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_FRAC_VAL_RMSK) +#define HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_FRAC_VAL_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_FRAC_VAL_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_FRAC_VAL_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_FRAC_VAL_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_FRAC_VAL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_FRAC_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_FRAC_VAL_IN) +#define HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_BMSK 0xffff +#define HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_SHFT 0x0 + +#define HWIO_GCC_RPMH_DDRMC_FAKE_SWITCH_DEBUG_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00089080) +#define HWIO_GCC_RPMH_DDRMC_FAKE_SWITCH_DEBUG_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00089080) +#define HWIO_GCC_RPMH_DDRMC_FAKE_SWITCH_DEBUG_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00089080) +#define HWIO_GCC_RPMH_DDRMC_FAKE_SWITCH_DEBUG_RMSK 0x3 +#define HWIO_GCC_RPMH_DDRMC_FAKE_SWITCH_DEBUG_ATTR 0x3 +#define HWIO_GCC_RPMH_DDRMC_FAKE_SWITCH_DEBUG_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_FAKE_SWITCH_DEBUG_ADDR, HWIO_GCC_RPMH_DDRMC_FAKE_SWITCH_DEBUG_RMSK) +#define HWIO_GCC_RPMH_DDRMC_FAKE_SWITCH_DEBUG_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_FAKE_SWITCH_DEBUG_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_FAKE_SWITCH_DEBUG_OUT(v) \ + out_dword(HWIO_GCC_RPMH_DDRMC_FAKE_SWITCH_DEBUG_ADDR,v) +#define HWIO_GCC_RPMH_DDRMC_FAKE_SWITCH_DEBUG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_FAKE_SWITCH_DEBUG_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_FAKE_SWITCH_DEBUG_IN) +#define HWIO_GCC_RPMH_DDRMC_FAKE_SWITCH_DEBUG_RCG_TOGGLE_EN_BMSK 0x2 +#define HWIO_GCC_RPMH_DDRMC_FAKE_SWITCH_DEBUG_RCG_TOGGLE_EN_SHFT 0x1 +#define HWIO_GCC_RPMH_DDRMC_FAKE_SWITCH_DEBUG_PLL_TOGGLE_EN_BMSK 0x1 +#define HWIO_GCC_RPMH_DDRMC_FAKE_SWITCH_DEBUG_PLL_TOGGLE_EN_SHFT 0x0 + +#define HWIO_GCC_RPMH_DDRMC_SWITCH_STATUS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00089044) +#define HWIO_GCC_RPMH_DDRMC_SWITCH_STATUS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00089044) +#define HWIO_GCC_RPMH_DDRMC_SWITCH_STATUS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00089044) +#define HWIO_GCC_RPMH_DDRMC_SWITCH_STATUS_RMSK 0x7f +#define HWIO_GCC_RPMH_DDRMC_SWITCH_STATUS_ATTR 0x1 +#define HWIO_GCC_RPMH_DDRMC_SWITCH_STATUS_IN \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_SWITCH_STATUS_ADDR, HWIO_GCC_RPMH_DDRMC_SWITCH_STATUS_RMSK) +#define HWIO_GCC_RPMH_DDRMC_SWITCH_STATUS_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_DDRMC_SWITCH_STATUS_ADDR, m) +#define HWIO_GCC_RPMH_DDRMC_SWITCH_STATUS_RPMH_DDRMC_CLOCK_SWITCH_FSM_RCG_TOGGLE_FSM_STATE_BMSK 0x40 +#define HWIO_GCC_RPMH_DDRMC_SWITCH_STATUS_RPMH_DDRMC_CLOCK_SWITCH_FSM_RCG_TOGGLE_FSM_STATE_SHFT 0x6 +#define HWIO_GCC_RPMH_DDRMC_SWITCH_STATUS_RPMH_DDRMC_CLOCK_SWITCH_FSM_RCG_TOGGLE_FSM_STATE_PING_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_SWITCH_STATUS_RPMH_DDRMC_CLOCK_SWITCH_FSM_RCG_TOGGLE_FSM_STATE_PONG_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_SWITCH_STATUS_RPMH_DDRMC_CLOCK_SWITCH_FSM_PLL_TOGGLE_FSM_STATE_BMSK 0x20 +#define HWIO_GCC_RPMH_DDRMC_SWITCH_STATUS_RPMH_DDRMC_CLOCK_SWITCH_FSM_PLL_TOGGLE_FSM_STATE_SHFT 0x5 +#define HWIO_GCC_RPMH_DDRMC_SWITCH_STATUS_RPMH_DDRMC_CLOCK_SWITCH_FSM_PLL_TOGGLE_FSM_STATE_PING_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_SWITCH_STATUS_RPMH_DDRMC_CLOCK_SWITCH_FSM_PLL_TOGGLE_FSM_STATE_PONG_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_SWITCH_STATUS_RPMH_DDRMC_CLOCK_SWITCH_FSM_STATE_BMSK 0x1f +#define HWIO_GCC_RPMH_DDRMC_SWITCH_STATUS_RPMH_DDRMC_CLOCK_SWITCH_FSM_STATE_SHFT 0x0 +#define HWIO_GCC_RPMH_DDRMC_SWITCH_STATUS_RPMH_DDRMC_CLOCK_SWITCH_FSM_STATE_IDLE_FVAL 0x0 +#define HWIO_GCC_RPMH_DDRMC_SWITCH_STATUS_RPMH_DDRMC_CLOCK_SWITCH_FSM_STATE_LATCH_CLOCK_PLAN_FVAL 0x1 +#define HWIO_GCC_RPMH_DDRMC_SWITCH_STATUS_RPMH_DDRMC_CLOCK_SWITCH_FSM_STATE_TOGGLE_FSM_FVAL 0x2 +#define HWIO_GCC_RPMH_DDRMC_SWITCH_STATUS_RPMH_DDRMC_CLOCK_SWITCH_FSM_STATE_PLL_L_VAL_LATCH_LATCH_FVAL 0x4 +#define HWIO_GCC_RPMH_DDRMC_SWITCH_STATUS_RPMH_DDRMC_CLOCK_SWITCH_FSM_STATE_CHANGE_WAIT_FVAL 0x8 +#define HWIO_GCC_RPMH_DDRMC_SWITCH_STATUS_RPMH_DDRMC_CLOCK_SWITCH_FSM_STATE_PRESENT_WORK_DONE_FVAL 0x10 + + +#endif /* __IPA_GCC_HWIO_H__ */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.0/ipa_gcc_hwio_def.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.0/ipa_gcc_hwio_def.h new file mode 100644 index 0000000000..0e0bcf0831 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.0/ipa_gcc_hwio_def.h @@ -0,0 +1,28406 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ + +#ifndef __IPA_GCC_HWIO_DEF_H__ +#define __IPA_GCC_HWIO_DEF_H__ +/** + @file ipa_gcc_hwio.h + @brief Auto-generated HWIO interface include file. + + This file contains HWIO register definitions for the following modules: + GCC_CLK_CTL_REG.* + + 'Include' filters applied: + 'Exclude' filters applied: RESERVED DUMMY +*/ + +/*---------------------------------------------------------------------------- + * MODULE: GCC_CLK_CTL_REG + *--------------------------------------------------------------------------*/ + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SYSTEM_NOC_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_system_noc_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_system_noc_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_system_noc_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SYS_NOC_AXI_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sys_noc_axi_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sys_noc_axi_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_sys_noc_axi_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SYS_NOC_HS_AXI_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sys_noc_hs_axi_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sys_noc_hs_axi_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_sys_noc_hs_axi_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SYS_NOC_QDSS_STM_AXI_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sys_noc_qdss_stm_axi_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sys_noc_qdss_stm_axi_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_sys_noc_qdss_stm_axi_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SYS_NOC_CPUSS_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sys_noc_cpuss_ahb_cbcr_s +{ + u32 reserved0 : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved1 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sys_noc_cpuss_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_sys_noc_cpuss_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SYS_NOC_AHB_CFG_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sys_noc_ahb_cfg_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sys_noc_ahb_cfg_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_sys_noc_ahb_cfg_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SYS_NOC_IPA_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sys_noc_ipa_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sys_noc_ipa_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_sys_noc_ipa_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SYS_NOC_AT_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sys_noc_at_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sys_noc_at_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_sys_noc_at_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_CMD_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_cmd_dfsr_s +{ + u32 dfs_en : 1; + u32 curr_perf_state : 4; + u32 hw_clk_control : 1; + u32 dfs_fsm_state : 3; + u32 perf_state_update_status : 1; + u32 sw_override : 1; + u32 sw_perf_state : 4; + u32 rcg_sw_ctrl : 4; + u32 reserved0 : 13; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_cmd_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_cmd_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf8_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf8_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf8_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf9_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf9_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf9_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf10_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf10_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf10_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf11_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf11_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf11_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf12_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf12_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf12_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf13_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf13_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf13_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf14_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf14_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf14_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf15_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf15_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf15_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SYS_NOC_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sys_noc_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sys_noc_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_sys_noc_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SYS_NOC_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sys_noc_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sys_noc_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_sys_noc_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SYS_NOC_DCD_CDIV_DCDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sys_noc_dcd_cdiv_dcdr_s +{ + u32 dcd_enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sys_noc_dcd_cdiv_dcdr_u +{ + struct ipa_gcc_hwio_def_gcc_sys_noc_dcd_cdiv_dcdr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_hs_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_hs_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_hs_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_hs_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_hs_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_hs_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_hs_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_hs_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_hs_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_hs_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_hs_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_hs_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_hs_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_hs_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_hs_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_hs_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_hs_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_hs_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_hs_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_hs_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_hs_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_hs_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_hs_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_hs_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF8_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_hs_perf8_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_hs_perf8_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_hs_perf8_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF9_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_hs_perf9_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_hs_perf9_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_hs_perf9_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF10_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_hs_perf10_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_hs_perf10_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_hs_perf10_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF11_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_hs_perf11_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_hs_perf11_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_hs_perf11_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF12_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_hs_perf12_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_hs_perf12_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_hs_perf12_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF13_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_hs_perf13_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_hs_perf13_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_hs_perf13_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF14_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_hs_perf14_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_hs_perf14_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_hs_perf14_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_HS_PERF15_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_hs_perf15_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_hs_perf15_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_hs_perf15_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SYS_NOC_HS_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sys_noc_hs_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sys_noc_hs_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_sys_noc_hs_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SYS_NOC_HS_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sys_noc_hs_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sys_noc_hs_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_sys_noc_hs_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SYS_NOC_HS_DCD_CDIV_DCDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sys_noc_hs_dcd_cdiv_dcdr_s +{ + u32 dcd_enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sys_noc_hs_dcd_cdiv_dcdr_u +{ + struct ipa_gcc_hwio_def_gcc_sys_noc_hs_dcd_cdiv_dcdr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SNOC_QOSGEN_EXTREF_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_snoc_qosgen_extref_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_snoc_qosgen_extref_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_snoc_qosgen_extref_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCNOC_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcnoc_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcnoc_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_pcnoc_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CFG_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cfg_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cfg_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_cfg_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_NOC_DCD_XO_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_noc_dcd_xo_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_noc_dcd_xo_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_noc_dcd_xo_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCNOC_SPMI_VGIS_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcnoc_spmi_vgis_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcnoc_spmi_vgis_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_pcnoc_spmi_vgis_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CMD_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cmd_dfsr_s +{ + u32 dfs_en : 1; + u32 curr_perf_state : 4; + u32 hw_clk_control : 1; + u32 dfs_fsm_state : 3; + u32 perf_state_update_status : 1; + u32 sw_override : 1; + u32 sw_perf_state : 4; + u32 rcg_sw_ctrl : 1; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cmd_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cmd_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_PCNOC_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_pcnoc_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_pcnoc_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_pcnoc_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_PCNOC_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_pcnoc_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_pcnoc_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_pcnoc_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_PCNOC_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_pcnoc_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_pcnoc_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_pcnoc_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_PCNOC_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_pcnoc_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_pcnoc_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_pcnoc_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_PCNOC_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_pcnoc_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_pcnoc_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_pcnoc_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_PCNOC_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_pcnoc_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_pcnoc_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_pcnoc_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_PCNOC_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_pcnoc_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_pcnoc_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_pcnoc_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_PCNOC_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_pcnoc_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_pcnoc_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_pcnoc_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_PCNOC_PERF8_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_pcnoc_perf8_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_pcnoc_perf8_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_pcnoc_perf8_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_PCNOC_PERF9_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_pcnoc_perf9_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_pcnoc_perf9_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_pcnoc_perf9_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_PCNOC_PERF10_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_pcnoc_perf10_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_pcnoc_perf10_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_pcnoc_perf10_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_PCNOC_PERF11_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_pcnoc_perf11_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_pcnoc_perf11_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_pcnoc_perf11_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_PCNOC_PERF12_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_pcnoc_perf12_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_pcnoc_perf12_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_pcnoc_perf12_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_PCNOC_PERF13_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_pcnoc_perf13_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_pcnoc_perf13_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_pcnoc_perf13_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_PCNOC_PERF14_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_pcnoc_perf14_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_pcnoc_perf14_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_pcnoc_perf14_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_PCNOC_PERF15_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_pcnoc_perf15_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_pcnoc_perf15_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_pcnoc_perf15_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCNOC_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcnoc_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcnoc_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_pcnoc_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCNOC_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcnoc_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcnoc_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_pcnoc_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCNOC_DCD_CDIV_DCDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcnoc_dcd_cdiv_dcdr_s +{ + u32 dcd_enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcnoc_dcd_cdiv_dcdr_u +{ + struct ipa_gcc_hwio_def_gcc_pcnoc_dcd_cdiv_dcdr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TIC_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tic_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tic_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_tic_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TIC_CFG_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tic_cfg_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 sleep : 4; + u32 wakeup : 4; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved0 : 5; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tic_cfg_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_tic_cfg_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TIC_CFG_AHB_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tic_cfg_ahb_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 8; + u32 sreg_pscbc_spare_ctrl_out : 8; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tic_cfg_ahb_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_tic_cfg_ahb_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_IMEM_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_imem_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_imem_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_imem_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_IMEM_AXI_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_imem_axi_cbcr_s +{ + u32 reserved0 : 2; + u32 clk_ares : 1; + u32 reserved1 : 1; + u32 sleep : 4; + u32 wakeup : 4; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved2 : 5; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved3 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved4 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_imem_axi_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_imem_axi_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_IMEM_AXI_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_imem_axi_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 8; + u32 sreg_pscbc_spare_ctrl_out : 8; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_imem_axi_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_imem_axi_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_IMEM_CFG_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_imem_cfg_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_imem_cfg_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_imem_cfg_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MMU_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mmu_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mmu_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_mmu_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SYS_NOC_TCU_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sys_noc_tcu_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sys_noc_tcu_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_sys_noc_tcu_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MMU_TCU_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mmu_tcu_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 sleep : 4; + u32 wakeup : 4; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved0 : 5; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mmu_tcu_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_mmu_tcu_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MMU_TCU_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mmu_tcu_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 8; + u32 sreg_pscbc_spare_ctrl_out : 8; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mmu_tcu_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_mmu_tcu_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_CMD_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_cmd_dfsr_s +{ + u32 dfs_en : 1; + u32 curr_perf_state : 4; + u32 hw_clk_control : 1; + u32 dfs_fsm_state : 3; + u32 perf_state_update_status : 1; + u32 sw_override : 1; + u32 sw_perf_state : 4; + u32 rcg_sw_ctrl : 5; + u32 reserved0 : 12; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_cmd_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_cmd_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf8_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf8_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf8_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf9_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf9_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf9_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf10_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf10_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf10_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf11_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf11_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf11_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf12_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf12_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf12_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf13_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf13_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf13_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf14_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf14_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf14_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf15_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf15_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf15_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MMU_TCU_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mmu_tcu_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mmu_tcu_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_mmu_tcu_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MMU_TCU_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mmu_tcu_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mmu_tcu_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_mmu_tcu_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MMU_TCU_DCD_CDIV_DCDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mmu_tcu_dcd_cdiv_dcdr_s +{ + u32 dcd_enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mmu_tcu_dcd_cdiv_dcdr_u +{ + struct ipa_gcc_hwio_def_gcc_mmu_tcu_dcd_cdiv_dcdr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ANOC_TBU_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_anoc_tbu_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_anoc_tbu_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_anoc_tbu_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AGGRE_NOC_TBU1_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_aggre_noc_tbu1_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 sleep : 4; + u32 wakeup : 4; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved0 : 5; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_aggre_noc_tbu1_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_aggre_noc_tbu1_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AGGRE_NOC_TBU1_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_aggre_noc_tbu1_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 8; + u32 sreg_pscbc_spare_ctrl_out : 8; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_aggre_noc_tbu1_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_aggre_noc_tbu1_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AGGRE_NOC_TBU2_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_aggre_noc_tbu2_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 sleep : 4; + u32 wakeup : 4; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved0 : 5; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_aggre_noc_tbu2_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_aggre_noc_tbu2_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AGGRE_NOC_TBU2_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_aggre_noc_tbu2_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 8; + u32 sreg_pscbc_spare_ctrl_out : 8; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_aggre_noc_tbu2_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_aggre_noc_tbu2_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QDSS_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qdss_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qdss_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_qdss_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QDSS_DAP_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qdss_dap_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qdss_dap_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qdss_dap_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QDSS_CFG_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qdss_cfg_ahb_cbcr_s +{ + u32 reserved0 : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved1 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qdss_cfg_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qdss_cfg_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QDSS_AT_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qdss_at_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qdss_at_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qdss_at_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QDSS_ETR_USB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qdss_etr_usb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qdss_etr_usb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qdss_etr_usb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QDSS_STM_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qdss_stm_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qdss_stm_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qdss_stm_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QDSS_TRACECLKIN_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qdss_traceclkin_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qdss_traceclkin_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qdss_traceclkin_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QDSS_TSCTR_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qdss_tsctr_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qdss_tsctr_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qdss_tsctr_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QDSS_TRIG_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qdss_trig_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qdss_trig_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qdss_trig_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QDSS_DAP_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qdss_dap_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qdss_dap_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qdss_dap_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_APB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_apb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_apb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_apb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QDSS_XO_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qdss_xo_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qdss_xo_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qdss_xo_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf8_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf8_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf8_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf9_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf9_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf9_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf10_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf10_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf10_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf11_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf11_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf11_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf12_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf12_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf12_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf13_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf13_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf13_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf14_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf14_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf14_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf15_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf15_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf15_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QDSS_STM_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qdss_stm_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qdss_stm_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qdss_stm_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QDSS_STM_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qdss_stm_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qdss_stm_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qdss_stm_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf8_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf8_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf8_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf9_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf9_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf9_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf10_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf10_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf10_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf11_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf11_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf11_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf12_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf12_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf12_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf13_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf13_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf13_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf14_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf14_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf14_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf15_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf15_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf15_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QDSS_TRACECLKIN_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qdss_traceclkin_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qdss_traceclkin_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qdss_traceclkin_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QDSS_TRACECLKIN_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qdss_traceclkin_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qdss_traceclkin_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qdss_traceclkin_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QDSS_APB_TSCTR_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qdss_apb_tsctr_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qdss_apb_tsctr_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qdss_apb_tsctr_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QDSS_APB_TSCTR_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qdss_apb_tsctr_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qdss_apb_tsctr_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qdss_apb_tsctr_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf8_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf8_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf8_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf9_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf9_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf9_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf10_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf10_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf10_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf11_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf11_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf11_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf12_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf12_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf12_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf13_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf13_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf13_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf14_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf14_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf14_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf15_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf15_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf15_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QDSS_TRIG_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qdss_trig_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qdss_trig_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qdss_trig_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QDSS_TRIG_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qdss_trig_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qdss_trig_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qdss_trig_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_AT_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_at_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_at_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_at_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_AT_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_at_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_at_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_at_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_AT_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_at_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_at_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_at_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_AT_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_at_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_at_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_at_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_AT_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_at_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_at_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_at_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_AT_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_at_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_at_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_at_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_AT_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_at_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_at_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_at_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_AT_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_at_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_at_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_at_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_AT_PERF8_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_at_perf8_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_at_perf8_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_at_perf8_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_AT_PERF9_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_at_perf9_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_at_perf9_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_at_perf9_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_AT_PERF10_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_at_perf10_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_at_perf10_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_at_perf10_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_AT_PERF11_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_at_perf11_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_at_perf11_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_at_perf11_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_AT_PERF12_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_at_perf12_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_at_perf12_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_at_perf12_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_AT_PERF13_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_at_perf13_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_at_perf13_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_at_perf13_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_AT_PERF14_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_at_perf14_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_at_perf14_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_at_perf14_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_AT_PERF15_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_at_perf15_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_at_perf15_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_at_perf15_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QDSS_AT_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qdss_at_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qdss_at_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qdss_at_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QDSS_AT_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qdss_at_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qdss_at_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qdss_at_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB30_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb30_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb30_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_usb30_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB30_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb30_gdscr_s +{ + u32 sw_collapse : 1; + u32 hw_control : 1; + u32 sw_override : 1; + u32 pd_ares : 1; + u32 clk_disable : 1; + u32 clamp_io : 1; + u32 en_few : 1; + u32 en_rest : 1; + u32 retain : 1; + u32 save : 1; + u32 restore : 1; + u32 retain_ff_enable : 1; + u32 clk_dis_wait : 4; + u32 en_few_wait : 4; + u32 en_rest_wait : 4; + u32 reserved0 : 3; + u32 gdsc_state : 4; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb30_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_usb30_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB30_CFG_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb30_cfg_gdscr_s +{ + u32 disable_clk_software_override : 1; + u32 clamp_io_software_override : 1; + u32 save_restore_software_override : 1; + u32 unclamp_io_software_override : 1; + u32 gdsc_pscbc_pwr_dwn_sw : 1; + u32 gdsc_phase_reset_delay_count_sw : 2; + u32 gdsc_phase_reset_en_sw : 1; + u32 gdsc_mem_core_force_in_sw : 1; + u32 gdsc_mem_peri_force_in_sw : 1; + u32 gdsc_handshake_dis : 1; + u32 software_control_override : 4; + u32 gdsc_power_down_complete : 1; + u32 gdsc_power_up_complete : 1; + u32 gdsc_enf_ack_status : 1; + u32 gdsc_enr_ack_status : 1; + u32 gdsc_mem_pwr_ack_status : 1; + u32 gdsc_cfg_fsm_state_status : 4; + u32 gdsc_pwr_up_start : 1; + u32 gdsc_pwr_dwn_start : 1; + u32 reserved0 : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb30_cfg_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_usb30_cfg_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB30_CFG2_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb30_cfg2_gdscr_s +{ + u32 mem_pwr_dwn_timeout : 4; + u32 dly_assert_clamp_mem : 4; + u32 dly_deassert_clamp_mem : 4; + u32 dly_mem_pwr_up : 4; + u32 gdsc_clamp_mem_sw : 1; + u32 gdsc_pwrdwn_enable_ack_override : 1; + u32 gdsc_mem_pwrup_ack_override : 1; + u32 reserved0 : 13; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb30_cfg2_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_usb30_cfg2_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB30_CFG3_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb30_cfg3_gdscr_s +{ + u32 gdsc_spare_ctrl_out : 8; + u32 gdsc_spare_ctrl_in : 8; + u32 gdsc_accu_red_sw_override : 1; + u32 gdsc_accu_red_shifter_start_sw : 1; + u32 gdsc_accu_red_shifter_clk_en_sw : 1; + u32 gdsc_accu_red_shifter_done_override : 1; + u32 gdsc_accu_red_timer_en_sw : 1; + u32 dly_accu_red_shifter_done : 4; + u32 gdsc_accu_red_enable : 1; + u32 gdsc_accu_red_shifter_done_status : 1; + u32 reserved0 : 5; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb30_cfg3_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_usb30_cfg3_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB30_CFG4_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb30_cfg4_gdscr_s +{ + u32 dly_retainff : 4; + u32 dly_clampio : 4; + u32 dly_deassertares : 4; + u32 dly_noretainff : 4; + u32 dly_restoreff : 4; + u32 dly_unclampio : 4; + u32 reserved0 : 8; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb30_cfg4_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_usb30_cfg4_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB30_MASTER_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb30_master_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 1; + u32 sleep : 4; + u32 wakeup : 4; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved2 : 7; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb30_master_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_usb30_master_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB30_MASTER_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb30_master_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 8; + u32 sreg_pscbc_spare_ctrl_out : 8; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb30_master_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_usb30_master_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB30_MSTR_AXI_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb30_mstr_axi_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb30_mstr_axi_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_usb30_mstr_axi_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB30_SLV_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb30_slv_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb30_slv_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_usb30_slv_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB30_SLEEP_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb30_sleep_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb30_sleep_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_usb30_sleep_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB30_MOCK_UTMI_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb30_mock_utmi_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb30_mock_utmi_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_usb30_mock_utmi_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB30_MASTER_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb30_master_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 dirty_m : 1; + u32 dirty_n : 1; + u32 dirty_d : 1; + u32 reserved1 : 23; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb30_master_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_usb30_master_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB30_MASTER_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb30_master_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 6; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb30_master_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_usb30_master_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB30_MASTER_M +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb30_master_m_s +{ + u32 m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb30_master_m_u +{ + struct ipa_gcc_hwio_def_gcc_usb30_master_m_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB30_MASTER_N +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb30_master_n_s +{ + u32 not_n_minus_m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb30_master_n_u +{ + struct ipa_gcc_hwio_def_gcc_usb30_master_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB30_MASTER_D +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb30_master_d_s +{ + u32 not_2d : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb30_master_d_u +{ + struct ipa_gcc_hwio_def_gcc_usb30_master_d_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB30_MOCK_UTMI_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb30_mock_utmi_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb30_mock_utmi_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_usb30_mock_utmi_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB30_MOCK_UTMI_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb30_mock_utmi_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb30_mock_utmi_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_usb30_mock_utmi_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB30_MOCK_UTMI_POSTDIV_CDIVR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb30_mock_utmi_postdiv_cdivr_s +{ + u32 clk_div : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb30_mock_utmi_postdiv_cdivr_u +{ + struct ipa_gcc_hwio_def_gcc_usb30_mock_utmi_postdiv_cdivr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB3_PHY_AUX_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb3_phy_aux_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb3_phy_aux_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_usb3_phy_aux_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB3_PHY_PIPE_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb3_phy_pipe_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb3_phy_pipe_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_usb3_phy_pipe_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB3_PHY_AUX_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb3_phy_aux_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 dirty_m : 1; + u32 dirty_n : 1; + u32 dirty_d : 1; + u32 reserved1 : 23; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb3_phy_aux_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_usb3_phy_aux_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB3_PHY_AUX_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb3_phy_aux_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 6; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb3_phy_aux_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_usb3_phy_aux_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB3_PHY_AUX_M +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb3_phy_aux_m_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb3_phy_aux_m_u +{ + struct ipa_gcc_hwio_def_gcc_usb3_phy_aux_m_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB3_PHY_AUX_N +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb3_phy_aux_n_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb3_phy_aux_n_u +{ + struct ipa_gcc_hwio_def_gcc_usb3_phy_aux_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB3_PHY_AUX_D +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb3_phy_aux_d_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb3_phy_aux_d_u +{ + struct ipa_gcc_hwio_def_gcc_usb3_phy_aux_d_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB3_PHY_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb3_phy_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb3_phy_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_usb3_phy_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB3PHY_PHY_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb3phy_phy_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb3phy_phy_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_usb3phy_phy_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUSB2PHY_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qusb2phy_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qusb2phy_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_qusb2phy_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB_PHY_CFG_AHB2PHY_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb_phy_cfg_ahb2phy_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb_phy_cfg_ahb2phy_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_usb_phy_cfg_ahb2phy_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB_PHY_CFG_AHB2PHY_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb_phy_cfg_ahb2phy_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb_phy_cfg_ahb2phy_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_usb_phy_cfg_ahb2phy_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SDCC1_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sdcc1_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sdcc1_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_sdcc1_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SDCC1_APPS_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sdcc1_apps_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 1; + u32 sleep : 4; + u32 wakeup : 4; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved2 : 7; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sdcc1_apps_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_sdcc1_apps_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SDCC1_APPS_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sdcc1_apps_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 8; + u32 sreg_pscbc_spare_ctrl_out : 8; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sdcc1_apps_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_sdcc1_apps_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SDCC1_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sdcc1_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sdcc1_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_sdcc1_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SDCC1_APPS_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sdcc1_apps_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 dirty_m : 1; + u32 dirty_n : 1; + u32 dirty_d : 1; + u32 reserved1 : 23; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sdcc1_apps_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_sdcc1_apps_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SDCC1_APPS_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sdcc1_apps_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 6; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sdcc1_apps_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_sdcc1_apps_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SDCC1_APPS_M +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sdcc1_apps_m_s +{ + u32 m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sdcc1_apps_m_u +{ + struct ipa_gcc_hwio_def_gcc_sdcc1_apps_m_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SDCC1_APPS_N +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sdcc1_apps_n_s +{ + u32 not_n_minus_m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sdcc1_apps_n_u +{ + struct ipa_gcc_hwio_def_gcc_sdcc1_apps_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SDCC1_APPS_D +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sdcc1_apps_d_s +{ + u32 not_2d : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sdcc1_apps_d_u +{ + struct ipa_gcc_hwio_def_gcc_sdcc1_apps_d_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_ahb_cbcr_s +{ + u32 reserved0 : 2; + u32 clk_ares : 1; + u32 reserved1 : 1; + u32 sleep : 4; + u32 wakeup : 4; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved2 : 5; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved3 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved4 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_AHB_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_ahb_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 8; + u32 sreg_pscbc_spare_ctrl_out : 8; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_ahb_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_ahb_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_SLEEP_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_sleep_cbcr_s +{ + u32 reserved0 : 2; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_sleep_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_sleep_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP_UART_SIM_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp_uart_sim_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 dirty_m : 1; + u32 dirty_n : 1; + u32 dirty_d : 1; + u32 reserved1 : 23; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp_uart_sim_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_blsp_uart_sim_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP_UART_SIM_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp_uart_sim_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 6; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp_uart_sim_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_blsp_uart_sim_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP_UART_SIM_M +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp_uart_sim_m_s +{ + u32 m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp_uart_sim_m_u +{ + struct ipa_gcc_hwio_def_gcc_blsp_uart_sim_m_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP_UART_SIM_N +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp_uart_sim_n_s +{ + u32 not_n_minus_m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp_uart_sim_n_u +{ + struct ipa_gcc_hwio_def_gcc_blsp_uart_sim_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP_UART_SIM_D +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp_uart_sim_d_s +{ + u32 not_2d : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp_uart_sim_d_u +{ + struct ipa_gcc_hwio_def_gcc_blsp_uart_sim_d_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_QUP1_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_qup1_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_qup1_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_qup1_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_QUP1_SPI_APPS_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_qup1_spi_apps_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_qup1_spi_apps_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_qup1_spi_apps_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_QUP1_I2C_APPS_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_qup1_i2c_apps_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_qup1_i2c_apps_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_qup1_i2c_apps_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_QUP1_SPI_APPS_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_qup1_spi_apps_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 dirty_m : 1; + u32 dirty_n : 1; + u32 dirty_d : 1; + u32 reserved1 : 23; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_qup1_spi_apps_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_qup1_spi_apps_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_qup1_spi_apps_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 6; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_qup1_spi_apps_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_qup1_spi_apps_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_QUP1_SPI_APPS_M +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_qup1_spi_apps_m_s +{ + u32 m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_qup1_spi_apps_m_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_qup1_spi_apps_m_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_QUP1_SPI_APPS_N +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_qup1_spi_apps_n_s +{ + u32 not_n_minus_m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_qup1_spi_apps_n_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_qup1_spi_apps_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_QUP1_SPI_APPS_D +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_qup1_spi_apps_d_s +{ + u32 not_2d : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_qup1_spi_apps_d_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_qup1_spi_apps_d_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_qup1_i2c_apps_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 dirty_m : 1; + u32 dirty_n : 1; + u32 dirty_d : 1; + u32 reserved1 : 23; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_qup1_i2c_apps_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_qup1_i2c_apps_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_qup1_i2c_apps_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 6; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_qup1_i2c_apps_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_qup1_i2c_apps_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_QUP1_I2C_APPS_M +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_qup1_i2c_apps_m_s +{ + u32 m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_qup1_i2c_apps_m_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_qup1_i2c_apps_m_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_QUP1_I2C_APPS_N +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_qup1_i2c_apps_n_s +{ + u32 not_n_minus_m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_qup1_i2c_apps_n_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_qup1_i2c_apps_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_QUP1_I2C_APPS_D +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_qup1_i2c_apps_d_s +{ + u32 not_2d : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_qup1_i2c_apps_d_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_qup1_i2c_apps_d_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_UART1_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_uart1_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_uart1_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_uart1_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_UART1_APPS_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_uart1_apps_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_uart1_apps_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_uart1_apps_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_UART1_SIM_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_uart1_sim_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_uart1_sim_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_uart1_sim_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_UART1_APPS_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_uart1_apps_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 dirty_m : 1; + u32 dirty_n : 1; + u32 dirty_d : 1; + u32 reserved1 : 23; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_uart1_apps_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_uart1_apps_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_UART1_APPS_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_uart1_apps_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 6; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_uart1_apps_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_uart1_apps_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_UART1_APPS_M +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_uart1_apps_m_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_uart1_apps_m_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_uart1_apps_m_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_UART1_APPS_N +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_uart1_apps_n_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_uart1_apps_n_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_uart1_apps_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_UART1_APPS_D +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_uart1_apps_d_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_uart1_apps_d_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_uart1_apps_d_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_QUP2_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_qup2_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_qup2_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_qup2_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_QUP2_SPI_APPS_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_qup2_spi_apps_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_qup2_spi_apps_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_qup2_spi_apps_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_QUP2_I2C_APPS_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_qup2_i2c_apps_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_qup2_i2c_apps_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_qup2_i2c_apps_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_QUP2_SPI_APPS_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_qup2_spi_apps_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 dirty_m : 1; + u32 dirty_n : 1; + u32 dirty_d : 1; + u32 reserved1 : 23; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_qup2_spi_apps_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_qup2_spi_apps_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_qup2_spi_apps_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 6; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_qup2_spi_apps_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_qup2_spi_apps_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_QUP2_SPI_APPS_M +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_qup2_spi_apps_m_s +{ + u32 m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_qup2_spi_apps_m_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_qup2_spi_apps_m_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_QUP2_SPI_APPS_N +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_qup2_spi_apps_n_s +{ + u32 not_n_minus_m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_qup2_spi_apps_n_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_qup2_spi_apps_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_QUP2_SPI_APPS_D +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_qup2_spi_apps_d_s +{ + u32 not_2d : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_qup2_spi_apps_d_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_qup2_spi_apps_d_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_QUP2_I2C_APPS_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_qup2_i2c_apps_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 dirty_m : 1; + u32 dirty_n : 1; + u32 dirty_d : 1; + u32 reserved1 : 23; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_qup2_i2c_apps_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_qup2_i2c_apps_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_qup2_i2c_apps_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 6; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_qup2_i2c_apps_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_qup2_i2c_apps_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_QUP2_I2C_APPS_M +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_qup2_i2c_apps_m_s +{ + u32 m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_qup2_i2c_apps_m_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_qup2_i2c_apps_m_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_QUP2_I2C_APPS_N +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_qup2_i2c_apps_n_s +{ + u32 not_n_minus_m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_qup2_i2c_apps_n_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_qup2_i2c_apps_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_QUP2_I2C_APPS_D +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_qup2_i2c_apps_d_s +{ + u32 not_2d : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_qup2_i2c_apps_d_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_qup2_i2c_apps_d_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_UART2_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_uart2_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_uart2_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_uart2_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_UART2_APPS_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_uart2_apps_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_uart2_apps_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_uart2_apps_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_UART2_SIM_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_uart2_sim_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_uart2_sim_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_uart2_sim_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_UART2_APPS_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_uart2_apps_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 dirty_m : 1; + u32 dirty_n : 1; + u32 dirty_d : 1; + u32 reserved1 : 23; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_uart2_apps_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_uart2_apps_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_UART2_APPS_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_uart2_apps_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 6; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_uart2_apps_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_uart2_apps_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_UART2_APPS_M +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_uart2_apps_m_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_uart2_apps_m_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_uart2_apps_m_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_UART2_APPS_N +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_uart2_apps_n_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_uart2_apps_n_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_uart2_apps_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_UART2_APPS_D +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_uart2_apps_d_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_uart2_apps_d_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_uart2_apps_d_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_QUP3_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_qup3_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_qup3_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_qup3_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_QUP3_SPI_APPS_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_qup3_spi_apps_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_qup3_spi_apps_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_qup3_spi_apps_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_QUP3_I2C_APPS_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_qup3_i2c_apps_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_qup3_i2c_apps_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_qup3_i2c_apps_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_QUP3_SPI_APPS_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_qup3_spi_apps_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 dirty_m : 1; + u32 dirty_n : 1; + u32 dirty_d : 1; + u32 reserved1 : 23; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_qup3_spi_apps_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_qup3_spi_apps_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_QUP3_SPI_APPS_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_qup3_spi_apps_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 6; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_qup3_spi_apps_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_qup3_spi_apps_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_QUP3_SPI_APPS_M +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_qup3_spi_apps_m_s +{ + u32 m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_qup3_spi_apps_m_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_qup3_spi_apps_m_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_QUP3_SPI_APPS_N +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_qup3_spi_apps_n_s +{ + u32 not_n_minus_m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_qup3_spi_apps_n_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_qup3_spi_apps_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_QUP3_SPI_APPS_D +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_qup3_spi_apps_d_s +{ + u32 not_2d : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_qup3_spi_apps_d_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_qup3_spi_apps_d_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_QUP3_I2C_APPS_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_qup3_i2c_apps_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 dirty_m : 1; + u32 dirty_n : 1; + u32 dirty_d : 1; + u32 reserved1 : 23; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_qup3_i2c_apps_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_qup3_i2c_apps_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_QUP3_I2C_APPS_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_qup3_i2c_apps_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 6; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_qup3_i2c_apps_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_qup3_i2c_apps_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_QUP3_I2C_APPS_M +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_qup3_i2c_apps_m_s +{ + u32 m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_qup3_i2c_apps_m_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_qup3_i2c_apps_m_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_QUP3_I2C_APPS_N +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_qup3_i2c_apps_n_s +{ + u32 not_n_minus_m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_qup3_i2c_apps_n_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_qup3_i2c_apps_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_QUP3_I2C_APPS_D +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_qup3_i2c_apps_d_s +{ + u32 not_2d : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_qup3_i2c_apps_d_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_qup3_i2c_apps_d_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_UART3_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_uart3_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_uart3_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_uart3_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_UART3_APPS_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_uart3_apps_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_uart3_apps_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_uart3_apps_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_UART3_SIM_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_uart3_sim_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_uart3_sim_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_uart3_sim_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_UART3_APPS_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_uart3_apps_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 dirty_m : 1; + u32 dirty_n : 1; + u32 dirty_d : 1; + u32 reserved1 : 23; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_uart3_apps_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_uart3_apps_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_UART3_APPS_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_uart3_apps_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 6; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_uart3_apps_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_uart3_apps_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_UART3_APPS_M +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_uart3_apps_m_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_uart3_apps_m_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_uart3_apps_m_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_UART3_APPS_N +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_uart3_apps_n_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_uart3_apps_n_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_uart3_apps_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_UART3_APPS_D +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_uart3_apps_d_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_uart3_apps_d_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_uart3_apps_d_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_QUP4_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_qup4_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_qup4_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_qup4_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_QUP4_SPI_APPS_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_qup4_spi_apps_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_qup4_spi_apps_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_qup4_spi_apps_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_QUP4_I2C_APPS_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_qup4_i2c_apps_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_qup4_i2c_apps_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_qup4_i2c_apps_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_QUP4_SPI_APPS_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_qup4_spi_apps_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 dirty_m : 1; + u32 dirty_n : 1; + u32 dirty_d : 1; + u32 reserved1 : 23; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_qup4_spi_apps_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_qup4_spi_apps_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_QUP4_SPI_APPS_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_qup4_spi_apps_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 6; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_qup4_spi_apps_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_qup4_spi_apps_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_QUP4_SPI_APPS_M +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_qup4_spi_apps_m_s +{ + u32 m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_qup4_spi_apps_m_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_qup4_spi_apps_m_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_QUP4_SPI_APPS_N +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_qup4_spi_apps_n_s +{ + u32 not_n_minus_m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_qup4_spi_apps_n_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_qup4_spi_apps_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_QUP4_SPI_APPS_D +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_qup4_spi_apps_d_s +{ + u32 not_2d : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_qup4_spi_apps_d_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_qup4_spi_apps_d_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_QUP4_I2C_APPS_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_qup4_i2c_apps_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 dirty_m : 1; + u32 dirty_n : 1; + u32 dirty_d : 1; + u32 reserved1 : 23; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_qup4_i2c_apps_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_qup4_i2c_apps_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_QUP4_I2C_APPS_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_qup4_i2c_apps_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 6; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_qup4_i2c_apps_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_qup4_i2c_apps_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_QUP4_I2C_APPS_M +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_qup4_i2c_apps_m_s +{ + u32 m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_qup4_i2c_apps_m_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_qup4_i2c_apps_m_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_QUP4_I2C_APPS_N +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_qup4_i2c_apps_n_s +{ + u32 not_n_minus_m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_qup4_i2c_apps_n_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_qup4_i2c_apps_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_QUP4_I2C_APPS_D +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_qup4_i2c_apps_d_s +{ + u32 not_2d : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_qup4_i2c_apps_d_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_qup4_i2c_apps_d_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_UART4_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_uart4_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_uart4_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_uart4_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_UART4_APPS_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_uart4_apps_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_uart4_apps_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_uart4_apps_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_UART4_SIM_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_uart4_sim_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_uart4_sim_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_uart4_sim_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_UART4_APPS_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_uart4_apps_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 dirty_m : 1; + u32 dirty_n : 1; + u32 dirty_d : 1; + u32 reserved1 : 23; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_uart4_apps_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_uart4_apps_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_UART4_APPS_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_uart4_apps_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 6; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_uart4_apps_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_uart4_apps_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_UART4_APPS_M +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_uart4_apps_m_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_uart4_apps_m_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_uart4_apps_m_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_UART4_APPS_N +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_uart4_apps_n_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_uart4_apps_n_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_uart4_apps_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BLSP1_UART4_APPS_D +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_blsp1_uart4_apps_d_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_blsp1_uart4_apps_d_u +{ + struct ipa_gcc_hwio_def_gcc_blsp1_uart4_apps_d_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PDM_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pdm_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pdm_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_pdm_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PDM_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pdm_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pdm_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_pdm_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PDM_XO4_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pdm_xo4_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pdm_xo4_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_pdm_xo4_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PDM2_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pdm2_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pdm2_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_pdm2_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PDM2_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pdm2_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pdm2_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_pdm2_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PDM2_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pdm2_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pdm2_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_pdm2_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PDM_XO4_CDIVR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pdm_xo4_cdivr_s +{ + u32 clk_div : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pdm_xo4_cdivr_u +{ + struct ipa_gcc_hwio_def_gcc_pdm_xo4_cdivr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PRNG_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_prng_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_prng_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_prng_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PRNG_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_prng_ahb_cbcr_s +{ + u32 reserved0 : 2; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_prng_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_prng_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TCSR_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tcsr_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tcsr_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_tcsr_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TCSR_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tcsr_ahb_cbcr_s +{ + u32 reserved0 : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved1 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tcsr_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_tcsr_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TCSR_ACC_SERIAL_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tcsr_acc_serial_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tcsr_acc_serial_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_tcsr_acc_serial_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BOOT_ROM_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_boot_rom_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_boot_rom_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_boot_rom_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BOOT_ROM_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_boot_rom_ahb_cbcr_s +{ + u32 reserved0 : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 sleep : 4; + u32 wakeup : 4; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved1 : 5; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_boot_rom_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_boot_rom_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BOOT_ROM_AHB_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_boot_rom_ahb_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 8; + u32 sreg_pscbc_spare_ctrl_out : 8; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_boot_rom_ahb_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_boot_rom_ahb_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TLMM_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tlmm_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tlmm_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_tlmm_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TLMM_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tlmm_ahb_cbcr_s +{ + u32 reserved0 : 2; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tlmm_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_tlmm_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TLMM_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tlmm_cbcr_s +{ + u32 reserved0 : 2; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tlmm_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_tlmm_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AOSS_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_aoss_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_aoss_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_aoss_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AOSS_CFG_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_aoss_cfg_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_aoss_cfg_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_aoss_cfg_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AOSS_AT_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_aoss_at_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_aoss_at_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_aoss_at_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SEC_CTRL_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sec_ctrl_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sec_ctrl_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_sec_ctrl_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SEC_CTRL_ACC_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sec_ctrl_acc_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sec_ctrl_acc_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_sec_ctrl_acc_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SEC_CTRL_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sec_ctrl_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sec_ctrl_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_sec_ctrl_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SEC_CTRL_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sec_ctrl_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 1; + u32 sleep : 4; + u32 wakeup : 4; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved2 : 7; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sec_ctrl_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_sec_ctrl_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SEC_CTRL_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sec_ctrl_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 8; + u32 sreg_pscbc_spare_ctrl_out : 8; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sec_ctrl_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_sec_ctrl_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SEC_CTRL_SENSE_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sec_ctrl_sense_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sec_ctrl_sense_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_sec_ctrl_sense_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SEC_CTRL_BOOT_ROM_PATCH_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sec_ctrl_boot_rom_patch_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sec_ctrl_boot_rom_patch_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_sec_ctrl_boot_rom_patch_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ACC_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_acc_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_acc_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_acc_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ACC_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_acc_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_acc_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_acc_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SEC_CTRL_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sec_ctrl_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sec_ctrl_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_sec_ctrl_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SEC_CTRL_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sec_ctrl_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sec_ctrl_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_sec_ctrl_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPDM_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spdm_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spdm_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_spdm_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPDM_CFG_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spdm_cfg_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spdm_cfg_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_spdm_cfg_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPDM_MSTR_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spdm_mstr_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spdm_mstr_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_spdm_mstr_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPDM_FF_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spdm_ff_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spdm_ff_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_spdm_ff_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPDM_MEMNOC_CY_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spdm_memnoc_cy_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spdm_memnoc_cy_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_spdm_memnoc_cy_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPDM_SNOC_CY_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spdm_snoc_cy_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spdm_snoc_cy_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_spdm_snoc_cy_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPDM_DEBUG_CY_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spdm_debug_cy_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spdm_debug_cy_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_spdm_debug_cy_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_AHBFABRIC_EFABRIC_SPDM_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_ahbfabric_efabric_spdm_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_ahbfabric_efabric_spdm_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_ahbfabric_efabric_spdm_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPDM_PNOC_CY_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spdm_pnoc_cy_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spdm_pnoc_cy_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_spdm_pnoc_cy_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPDM_MEMNOC_CY_CDIVR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spdm_memnoc_cy_cdivr_s +{ + u32 clk_div : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spdm_memnoc_cy_cdivr_u +{ + struct ipa_gcc_hwio_def_gcc_spdm_memnoc_cy_cdivr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPDM_SNOC_CY_CDIVR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spdm_snoc_cy_cdivr_s +{ + u32 clk_div : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spdm_snoc_cy_cdivr_u +{ + struct ipa_gcc_hwio_def_gcc_spdm_snoc_cy_cdivr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPDM_DEBUG_CY_CDIVR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spdm_debug_cy_cdivr_s +{ + u32 clk_div : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spdm_debug_cy_cdivr_u +{ + struct ipa_gcc_hwio_def_gcc_spdm_debug_cy_cdivr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CE1_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ce1_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ce1_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_ce1_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CE1_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ce1_cbcr_s +{ + u32 reserved0 : 2; + u32 clk_ares : 1; + u32 reserved1 : 1; + u32 sleep : 4; + u32 wakeup : 4; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved2 : 5; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved3 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved4 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ce1_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ce1_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CE1_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ce1_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 8; + u32 sreg_pscbc_spare_ctrl_out : 8; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ce1_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_ce1_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CE1_AXI_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ce1_axi_cbcr_s +{ + u32 reserved0 : 2; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ce1_axi_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ce1_axi_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CE1_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ce1_ahb_cbcr_s +{ + u32 reserved0 : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved1 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ce1_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ce1_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_CMD_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_cmd_dfsr_s +{ + u32 dfs_en : 1; + u32 curr_perf_state : 4; + u32 hw_clk_control : 1; + u32 dfs_fsm_state : 3; + u32 perf_state_update_status : 1; + u32 sw_override : 1; + u32 sw_perf_state : 4; + u32 rcg_sw_ctrl : 1; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_cmd_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_cmd_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_CE1_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_CE1_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_CE1_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_CE1_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_CE1_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_CE1_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_CE1_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_CE1_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_CE1_PERF8_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf8_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf8_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf8_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_CE1_PERF9_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf9_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf9_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf9_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_CE1_PERF10_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf10_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf10_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf10_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_CE1_PERF11_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf11_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf11_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf11_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_CE1_PERF12_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf12_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf12_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf12_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_CE1_PERF13_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf13_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf13_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf13_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_CE1_PERF14_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf14_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf14_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf14_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_CE1_PERF15_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf15_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf15_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf15_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CE1_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ce1_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ce1_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_ce1_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CE1_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ce1_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ce1_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_ce1_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AHB_PCIE_LINK_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ahb_pcie_link_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ahb_pcie_link_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ahb_pcie_link_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_XO_PCIE_LINK_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_xo_pcie_link_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_xo_pcie_link_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_xo_pcie_link_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_XO_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_xo_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_xo_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_xo_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_XO_DIV4_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_xo_div4_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_xo_div4_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_xo_div4_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SLEEP_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sleep_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sleep_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_sleep_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_XO_DIV4_CDIVR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_xo_div4_cdivr_s +{ + u32 clk_div : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_xo_div4_cdivr_u +{ + struct ipa_gcc_hwio_def_gcc_xo_div4_cdivr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SLEEP_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sleep_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sleep_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_sleep_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SLEEP_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sleep_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sleep_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_sleep_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_XO_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_xo_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_xo_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_xo_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_XO_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_xo_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_xo_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_xo_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DDRSS_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ddrss_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ddrss_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_ddrss_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DDRSS_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ddrss_gdscr_s +{ + u32 sw_collapse : 1; + u32 hw_control : 1; + u32 sw_override : 1; + u32 pd_ares : 1; + u32 clk_disable : 1; + u32 clamp_io : 1; + u32 en_few : 1; + u32 en_rest : 1; + u32 retain : 1; + u32 save : 1; + u32 restore : 1; + u32 retain_ff_enable : 1; + u32 clk_dis_wait : 4; + u32 en_few_wait : 4; + u32 en_rest_wait : 4; + u32 reserved0 : 3; + u32 gdsc_state : 4; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ddrss_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_ddrss_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DDRSS_CFG_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ddrss_cfg_gdscr_s +{ + u32 disable_clk_software_override : 1; + u32 clamp_io_software_override : 1; + u32 save_restore_software_override : 1; + u32 unclamp_io_software_override : 1; + u32 gdsc_pscbc_pwr_dwn_sw : 1; + u32 gdsc_phase_reset_delay_count_sw : 2; + u32 gdsc_phase_reset_en_sw : 1; + u32 gdsc_mem_core_force_in_sw : 1; + u32 gdsc_mem_peri_force_in_sw : 1; + u32 gdsc_handshake_dis : 1; + u32 software_control_override : 4; + u32 gdsc_power_down_complete : 1; + u32 gdsc_power_up_complete : 1; + u32 gdsc_enf_ack_status : 1; + u32 gdsc_enr_ack_status : 1; + u32 gdsc_mem_pwr_ack_status : 1; + u32 gdsc_cfg_fsm_state_status : 4; + u32 gdsc_pwr_up_start : 1; + u32 gdsc_pwr_dwn_start : 1; + u32 reserved0 : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ddrss_cfg_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_ddrss_cfg_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DDRSS_CFG2_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ddrss_cfg2_gdscr_s +{ + u32 mem_pwr_dwn_timeout : 4; + u32 dly_assert_clamp_mem : 4; + u32 dly_deassert_clamp_mem : 4; + u32 dly_mem_pwr_up : 4; + u32 gdsc_clamp_mem_sw : 1; + u32 gdsc_pwrdwn_enable_ack_override : 1; + u32 gdsc_mem_pwrup_ack_override : 1; + u32 reserved0 : 13; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ddrss_cfg2_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_ddrss_cfg2_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DDRSS_CFG3_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ddrss_cfg3_gdscr_s +{ + u32 gdsc_spare_ctrl_out : 8; + u32 gdsc_spare_ctrl_in : 8; + u32 gdsc_accu_red_sw_override : 1; + u32 gdsc_accu_red_shifter_start_sw : 1; + u32 gdsc_accu_red_shifter_clk_en_sw : 1; + u32 gdsc_accu_red_shifter_done_override : 1; + u32 gdsc_accu_red_timer_en_sw : 1; + u32 dly_accu_red_shifter_done : 4; + u32 gdsc_accu_red_enable : 1; + u32 gdsc_accu_red_shifter_done_status : 1; + u32 reserved0 : 5; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ddrss_cfg3_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_ddrss_cfg3_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DDRSS_CFG4_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ddrss_cfg4_gdscr_s +{ + u32 dly_retainff : 4; + u32 dly_clampio : 4; + u32 dly_deassertares : 4; + u32 dly_noretainff : 4; + u32 dly_restoreff : 4; + u32 dly_unclampio : 4; + u32 reserved0 : 8; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ddrss_cfg4_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_ddrss_cfg4_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DDRSS_TCU_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ddrss_tcu_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ddrss_tcu_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ddrss_tcu_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DDRSS_SYS_NOC_AXI_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ddrss_sys_noc_axi_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ddrss_sys_noc_axi_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ddrss_sys_noc_axi_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DDRSS_SYS_NOC_HS_AXI_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ddrss_sys_noc_hs_axi_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ddrss_sys_noc_hs_axi_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ddrss_sys_noc_hs_axi_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DDRSS_XO_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ddrss_xo_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ddrss_xo_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ddrss_xo_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DDRSS_CFG_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ddrss_cfg_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ddrss_cfg_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ddrss_cfg_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DDRSS_SLEEP_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ddrss_sleep_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ddrss_sleep_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ddrss_sleep_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MEMNOC_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_memnoc_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_memnoc_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_memnoc_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DDRSS_AT_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ddrss_at_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ddrss_at_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ddrss_at_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DDRSS_MSS_MCDMA_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ddrss_mss_mcdma_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ddrss_mss_mcdma_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ddrss_mss_mcdma_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf8_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf8_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf8_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf9_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf9_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf9_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf10_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf10_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf10_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf11_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf11_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf11_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf12_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf12_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf12_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf13_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf13_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf13_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf14_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf14_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf14_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf15_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf15_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf15_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MEMNOC_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_memnoc_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_memnoc_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_memnoc_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MEMNOC_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_memnoc_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_memnoc_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_memnoc_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_CMD_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_cmd_dfsr_s +{ + u32 dfs_en : 1; + u32 curr_perf_state : 4; + u32 hw_clk_control : 1; + u32 dfs_fsm_state : 3; + u32 perf_state_update_status : 1; + u32 sw_override : 1; + u32 sw_perf_state : 4; + u32 rcg_sw_ctrl : 1; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_cmd_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_cmd_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_SHRM_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_SHRM_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_SHRM_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_SHRM_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_SHRM_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_SHRM_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_SHRM_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_SHRM_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_SHRM_PERF8_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf8_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf8_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf8_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_SHRM_PERF9_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf9_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf9_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf9_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_SHRM_PERF10_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf10_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf10_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf10_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_SHRM_PERF11_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf11_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf11_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf11_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_SHRM_PERF12_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf12_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf12_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf12_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_SHRM_PERF13_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf13_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf13_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf13_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_SHRM_PERF14_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf14_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf14_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf14_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_SHRM_PERF15_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf15_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf15_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf15_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SHRM_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_shrm_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_shrm_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_shrm_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SHRM_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_shrm_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_shrm_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_shrm_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SHRM_DCD_CDIV_DCDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_shrm_dcd_cdiv_dcdr_s +{ + u32 dcd_enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_shrm_dcd_cdiv_dcdr_u +{ + struct ipa_gcc_hwio_def_gcc_shrm_dcd_cdiv_dcdr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MEMNOC_DCD_CDIV_DCDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_memnoc_dcd_cdiv_dcdr_s +{ + u32 dcd_enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_memnoc_dcd_cdiv_dcdr_u +{ + struct ipa_gcc_hwio_def_gcc_memnoc_dcd_cdiv_dcdr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DDR_I_HCLK_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ddr_i_hclk_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ddr_i_hclk_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ddr_i_hclk_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DDRMC_CH0_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ddrmc_ch0_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ddrmc_ch0_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ddrmc_ch0_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DDRMC_CH1_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ddrmc_ch1_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ddrmc_ch1_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ddrmc_ch1_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_CH0_CMD_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch0_cmd_dfsr_s +{ + u32 dfs_en : 1; + u32 curr_perf_state : 4; + u32 hw_clk_control : 1; + u32 dfs_fsm_state : 3; + u32 perf_state_update_status : 1; + u32 sw_override : 1; + u32 sw_perf_state : 4; + u32 rcg_sw_ctrl : 1; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch0_cmd_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch0_cmd_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch0_ddrmc_ch0_root_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch0_ddrmc_ch0_root_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch0_ddrmc_ch0_root_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch0_ddrmc_ch0_root_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch0_ddrmc_ch0_root_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch0_ddrmc_ch0_root_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch0_ddrmc_ch0_root_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch0_ddrmc_ch0_root_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch0_ddrmc_ch0_root_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch0_ddrmc_ch0_root_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch0_ddrmc_ch0_root_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch0_ddrmc_ch0_root_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch0_ddrmc_ch0_root_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch0_ddrmc_ch0_root_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch0_ddrmc_ch0_root_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch0_ddrmc_ch0_root_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch0_ddrmc_ch0_root_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch0_ddrmc_ch0_root_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch0_ddrmc_ch0_root_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch0_ddrmc_ch0_root_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch0_ddrmc_ch0_root_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch0_ddrmc_ch0_root_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch0_ddrmc_ch0_root_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch0_ddrmc_ch0_root_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch0_ddrmc_ch0_root_perf8_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch0_ddrmc_ch0_root_perf8_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch0_ddrmc_ch0_root_perf8_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch0_ddrmc_ch0_root_perf9_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch0_ddrmc_ch0_root_perf9_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch0_ddrmc_ch0_root_perf9_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch0_ddrmc_ch0_root_perf10_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch0_ddrmc_ch0_root_perf10_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch0_ddrmc_ch0_root_perf10_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch0_ddrmc_ch0_root_perf11_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch0_ddrmc_ch0_root_perf11_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch0_ddrmc_ch0_root_perf11_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch0_ddrmc_ch0_root_perf12_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch0_ddrmc_ch0_root_perf12_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch0_ddrmc_ch0_root_perf12_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch0_ddrmc_ch0_root_perf13_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch0_ddrmc_ch0_root_perf13_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch0_ddrmc_ch0_root_perf13_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch0_ddrmc_ch0_root_perf14_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch0_ddrmc_ch0_root_perf14_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch0_ddrmc_ch0_root_perf14_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch0_ddrmc_ch0_root_perf15_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch0_ddrmc_ch0_root_perf15_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch0_ddrmc_ch0_root_perf15_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DDRMC_CH0_ROOT_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ddrmc_ch0_root_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ddrmc_ch0_root_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_ddrmc_ch0_root_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DDRMC_CH0_ROOT_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ddrmc_ch0_root_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ddrmc_ch0_root_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_ddrmc_ch0_root_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DDRMC_CH0_ROOT_DCD_CDIV_DCDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ddrmc_ch0_root_dcd_cdiv_dcdr_s +{ + u32 dcd_enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ddrmc_ch0_root_dcd_cdiv_dcdr_u +{ + struct ipa_gcc_hwio_def_gcc_ddrmc_ch0_root_dcd_cdiv_dcdr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_CH1_CMD_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch1_cmd_dfsr_s +{ + u32 dfs_en : 1; + u32 curr_perf_state : 4; + u32 hw_clk_control : 1; + u32 dfs_fsm_state : 3; + u32 perf_state_update_status : 1; + u32 sw_override : 1; + u32 sw_perf_state : 4; + u32 rcg_sw_ctrl : 1; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch1_cmd_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch1_cmd_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch1_ddrmc_ch1_root_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch1_ddrmc_ch1_root_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch1_ddrmc_ch1_root_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch1_ddrmc_ch1_root_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch1_ddrmc_ch1_root_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch1_ddrmc_ch1_root_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch1_ddrmc_ch1_root_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch1_ddrmc_ch1_root_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch1_ddrmc_ch1_root_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch1_ddrmc_ch1_root_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch1_ddrmc_ch1_root_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch1_ddrmc_ch1_root_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch1_ddrmc_ch1_root_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch1_ddrmc_ch1_root_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch1_ddrmc_ch1_root_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch1_ddrmc_ch1_root_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch1_ddrmc_ch1_root_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch1_ddrmc_ch1_root_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch1_ddrmc_ch1_root_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch1_ddrmc_ch1_root_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch1_ddrmc_ch1_root_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch1_ddrmc_ch1_root_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch1_ddrmc_ch1_root_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch1_ddrmc_ch1_root_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch1_ddrmc_ch1_root_perf8_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch1_ddrmc_ch1_root_perf8_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch1_ddrmc_ch1_root_perf8_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch1_ddrmc_ch1_root_perf9_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch1_ddrmc_ch1_root_perf9_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch1_ddrmc_ch1_root_perf9_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch1_ddrmc_ch1_root_perf10_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch1_ddrmc_ch1_root_perf10_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch1_ddrmc_ch1_root_perf10_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch1_ddrmc_ch1_root_perf11_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch1_ddrmc_ch1_root_perf11_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch1_ddrmc_ch1_root_perf11_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch1_ddrmc_ch1_root_perf12_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch1_ddrmc_ch1_root_perf12_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch1_ddrmc_ch1_root_perf12_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch1_ddrmc_ch1_root_perf13_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch1_ddrmc_ch1_root_perf13_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch1_ddrmc_ch1_root_perf13_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch1_ddrmc_ch1_root_perf14_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch1_ddrmc_ch1_root_perf14_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch1_ddrmc_ch1_root_perf14_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch1_ddrmc_ch1_root_perf15_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch1_ddrmc_ch1_root_perf15_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_ch1_ddrmc_ch1_root_perf15_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DDRMC_CH1_ROOT_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ddrmc_ch1_root_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ddrmc_ch1_root_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_ddrmc_ch1_root_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DDRMC_CH1_ROOT_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ddrmc_ch1_root_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ddrmc_ch1_root_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_ddrmc_ch1_root_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DDRMC_CH1_ROOT_DCD_CDIV_DCDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ddrmc_ch1_root_dcd_cdiv_dcdr_s +{ + u32 dcd_enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ddrmc_ch1_root_dcd_cdiv_dcdr_u +{ + struct ipa_gcc_hwio_def_gcc_ddrmc_ch1_root_dcd_cdiv_dcdr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CPUSS_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cpuss_ahb_cbcr_s +{ + u32 reserved0 : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved1 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cpuss_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_cpuss_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CPUSS_GNOC_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cpuss_gnoc_cbcr_s +{ + u32 reserved0 : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved1 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cpuss_gnoc_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_cpuss_gnoc_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CPUSS_AT_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cpuss_at_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cpuss_at_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_cpuss_at_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CPUSS_AHB_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cpuss_ahb_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cpuss_ahb_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_cpuss_ahb_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CPUSS_AHB_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cpuss_ahb_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cpuss_ahb_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_cpuss_ahb_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CPUSS_AHB_POSTDIV_CDIVR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cpuss_ahb_postdiv_cdivr_s +{ + u32 clk_div : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cpuss_ahb_postdiv_cdivr_u +{ + struct ipa_gcc_hwio_def_gcc_cpuss_ahb_postdiv_cdivr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CPUSS_GPLL0_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cpuss_gpll0_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cpuss_gpll0_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_cpuss_gpll0_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CPUSS_GPLL0_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cpuss_gpll0_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cpuss_gpll0_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_cpuss_gpll0_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_APSS_QDSS_TSCTR_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_apss_qdss_tsctr_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_apss_qdss_tsctr_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_apss_qdss_tsctr_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_APSS_QDSS_APB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_apss_qdss_apb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_apss_qdss_apb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_apss_qdss_apb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_NOC_BUS_TIMEOUT_EXTREF_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_noc_bus_timeout_extref_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_noc_bus_timeout_extref_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_noc_bus_timeout_extref_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_noc_bus_timeout_extref_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_noc_bus_timeout_extref_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_noc_bus_timeout_extref_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_NOC_BUS_TIMEOUT_EXTREF_CDIVR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_noc_bus_timeout_extref_cdivr_s +{ + u32 clk_div : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_noc_bus_timeout_extref_cdivr_u +{ + struct ipa_gcc_hwio_def_gcc_noc_bus_timeout_extref_cdivr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_NOC_BUS_TIMEOUT_EXTREF_DIV1024_CDIVR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_noc_bus_timeout_extref_div1024_cdivr_s +{ + u32 clk_div : 9; + u32 reserved0 : 23; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_noc_bus_timeout_extref_div1024_cdivr_u +{ + struct ipa_gcc_hwio_def_gcc_noc_bus_timeout_extref_div1024_cdivr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_APB2JTAG_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_apb2jtag_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_apb2jtag_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_apb2jtag_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RBCPR_CX_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rbcpr_cx_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rbcpr_cx_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_rbcpr_cx_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RBCPR_CX_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rbcpr_cx_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rbcpr_cx_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_rbcpr_cx_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RBCPR_CX_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rbcpr_cx_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rbcpr_cx_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_rbcpr_cx_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RBCPR_CX_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rbcpr_cx_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rbcpr_cx_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_rbcpr_cx_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RBCPR_CX_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rbcpr_cx_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rbcpr_cx_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_rbcpr_cx_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RBCPR_MX_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rbcpr_mx_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rbcpr_mx_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_rbcpr_mx_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RBCPR_MX_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rbcpr_mx_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rbcpr_mx_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_rbcpr_mx_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RBCPR_MX_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rbcpr_mx_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rbcpr_mx_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_rbcpr_mx_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RBCPR_MX_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rbcpr_mx_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rbcpr_mx_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_rbcpr_mx_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RBCPR_MX_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rbcpr_mx_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rbcpr_mx_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_rbcpr_mx_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RBCPR_MXC_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rbcpr_mxc_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rbcpr_mxc_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_rbcpr_mxc_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RBCPR_MXC_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rbcpr_mxc_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rbcpr_mxc_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_rbcpr_mxc_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RBCPR_MXC_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rbcpr_mxc_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rbcpr_mxc_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_rbcpr_mxc_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RBCPR_MXC_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rbcpr_mxc_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rbcpr_mxc_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_rbcpr_mxc_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RBCPR_MXC_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rbcpr_mxc_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rbcpr_mxc_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_rbcpr_mxc_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DEBUG_DIV_CDIVR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_debug_div_cdivr_s +{ + u32 clk_div : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_debug_div_cdivr_u +{ + struct ipa_gcc_hwio_def_gcc_debug_div_cdivr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DEBUG_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_debug_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_debug_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_debug_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GP1_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gp1_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gp1_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_gp1_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GP1_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gp1_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 dirty_m : 1; + u32 dirty_n : 1; + u32 dirty_d : 1; + u32 reserved1 : 23; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gp1_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_gp1_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GP1_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gp1_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 6; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gp1_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_gp1_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GP1_M +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gp1_m_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gp1_m_u +{ + struct ipa_gcc_hwio_def_gcc_gp1_m_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GP1_N +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gp1_n_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gp1_n_u +{ + struct ipa_gcc_hwio_def_gcc_gp1_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GP1_D +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gp1_d_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gp1_d_u +{ + struct ipa_gcc_hwio_def_gcc_gp1_d_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GP2_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gp2_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gp2_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_gp2_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GP2_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gp2_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 dirty_m : 1; + u32 dirty_n : 1; + u32 dirty_d : 1; + u32 reserved1 : 23; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gp2_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_gp2_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GP2_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gp2_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 6; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gp2_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_gp2_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GP2_M +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gp2_m_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gp2_m_u +{ + struct ipa_gcc_hwio_def_gcc_gp2_m_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GP2_N +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gp2_n_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gp2_n_u +{ + struct ipa_gcc_hwio_def_gcc_gp2_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GP2_D +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gp2_d_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gp2_d_u +{ + struct ipa_gcc_hwio_def_gcc_gp2_d_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GP3_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gp3_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gp3_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_gp3_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GP3_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gp3_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 dirty_m : 1; + u32 dirty_n : 1; + u32 dirty_d : 1; + u32 reserved1 : 23; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gp3_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_gp3_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GP3_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gp3_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 6; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gp3_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_gp3_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GP3_M +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gp3_m_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gp3_m_u +{ + struct ipa_gcc_hwio_def_gcc_gp3_m_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GP3_N +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gp3_n_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gp3_n_u +{ + struct ipa_gcc_hwio_def_gcc_gp3_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GP3_D +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gp3_d_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gp3_d_u +{ + struct ipa_gcc_hwio_def_gcc_gp3_d_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AUDIO_CORE_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_audio_core_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_audio_core_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_audio_core_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_PCNOC_MPORT_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_pcnoc_mport_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_pcnoc_mport_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_pcnoc_mport_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_PCNOC_SWAY_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_pcnoc_sway_cbcr_s +{ + u32 reserved0 : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved1 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_pcnoc_sway_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_pcnoc_sway_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AUDIO_AHB_BUS_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_audio_ahb_bus_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_audio_ahb_bus_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_audio_ahb_bus_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_ahbfabric_ixfabric_cbcr_s +{ + u32 reserved0 : 2; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_ahbfabric_ixfabric_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_ahbfabric_ixfabric_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_ahbfabric_ixfabric_lpm_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 1; + u32 sleep : 4; + u32 wakeup : 4; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved2 : 7; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_ahbfabric_ixfabric_lpm_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_ahbfabric_ixfabric_lpm_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_ahbfabric_ixfabric_lpm_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 8; + u32 sreg_pscbc_spare_ctrl_out : 8; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_ahbfabric_ixfabric_lpm_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_ahbfabric_ixfabric_lpm_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_slimbus_bam_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 1; + u32 sleep : 4; + u32 wakeup : 4; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved2 : 7; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_lpaif_slimbus_bam_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_slimbus_bam_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_LPAIF_SLIMBUS_BAM_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_slimbus_bam_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 8; + u32 sreg_pscbc_spare_ctrl_out : 8; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_lpaif_slimbus_bam_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_slimbus_bam_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_AHBFABRIC_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_ahbfabric_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 dirty_m : 1; + u32 dirty_n : 1; + u32 dirty_d : 1; + u32 reserved1 : 23; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_ahbfabric_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_ahbfabric_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_AHBFABRIC_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_ahbfabric_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 6; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_ahbfabric_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_ahbfabric_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_AHBFABRIC_M +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_ahbfabric_m_s +{ + u32 m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_ahbfabric_m_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_ahbfabric_m_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_AHBFABRIC_N +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_ahbfabric_n_s +{ + u32 not_n_minus_m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_ahbfabric_n_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_ahbfabric_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_AHBFABRIC_D +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_ahbfabric_d_s +{ + u32 not_2d : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_ahbfabric_d_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_ahbfabric_d_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_PRI_I2S_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_pri_i2s_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_pri_i2s_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_pri_i2s_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_LPAIF_PRI_I2S_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_pri_i2s_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_lpaif_pri_i2s_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_pri_i2s_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_LPAIF_PRI_I2S_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_pri_i2s_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 dirty_m : 1; + u32 dirty_n : 1; + u32 dirty_d : 1; + u32 reserved1 : 23; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_lpaif_pri_i2s_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_pri_i2s_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_LPAIF_PRI_I2S_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_pri_i2s_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 6; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_lpaif_pri_i2s_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_pri_i2s_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_LPAIF_PRI_I2S_M +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_pri_i2s_m_s +{ + u32 m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_lpaif_pri_i2s_m_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_pri_i2s_m_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_LPAIF_PRI_I2S_N +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_pri_i2s_n_s +{ + u32 not_n_minus_m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_lpaif_pri_i2s_n_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_pri_i2s_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_LPAIF_PRI_I2S_D +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_pri_i2s_d_s +{ + u32 not_2d : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_lpaif_pri_i2s_d_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_pri_i2s_d_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_SEC_I2S_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_sec_i2s_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_sec_i2s_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_sec_i2s_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_LPAIF_SEC_I2S_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_sec_i2s_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_lpaif_sec_i2s_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_sec_i2s_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_LPAIF_SEC_I2S_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_sec_i2s_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 dirty_m : 1; + u32 dirty_n : 1; + u32 dirty_d : 1; + u32 reserved1 : 23; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_lpaif_sec_i2s_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_sec_i2s_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_LPAIF_SEC_I2S_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_sec_i2s_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 6; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_lpaif_sec_i2s_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_sec_i2s_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_LPAIF_SEC_I2S_M +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_sec_i2s_m_s +{ + u32 m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_lpaif_sec_i2s_m_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_sec_i2s_m_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_LPAIF_SEC_I2S_N +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_sec_i2s_n_s +{ + u32 not_n_minus_m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_lpaif_sec_i2s_n_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_sec_i2s_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_LPAIF_SEC_I2S_D +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_sec_i2s_d_s +{ + u32 not_2d : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_lpaif_sec_i2s_d_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_sec_i2s_d_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_AUX_I2S_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_aux_i2s_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_aux_i2s_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_aux_i2s_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_LPAIF_AUX_I2S_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_aux_i2s_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_lpaif_aux_i2s_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_aux_i2s_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_LPAIF_AUX_I2S_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_aux_i2s_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 dirty_m : 1; + u32 dirty_n : 1; + u32 dirty_d : 1; + u32 reserved1 : 23; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_lpaif_aux_i2s_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_aux_i2s_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_LPAIF_AUX_I2S_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_aux_i2s_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 6; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_lpaif_aux_i2s_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_aux_i2s_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_LPAIF_AUX_I2S_M +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_aux_i2s_m_s +{ + u32 m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_lpaif_aux_i2s_m_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_aux_i2s_m_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_LPAIF_AUX_I2S_N +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_aux_i2s_n_s +{ + u32 not_n_minus_m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_lpaif_aux_i2s_n_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_aux_i2s_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_LPAIF_AUX_I2S_D +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_aux_i2s_d_s +{ + u32 not_2d : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_lpaif_aux_i2s_d_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_aux_i2s_d_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AUDIO_CXO_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_audio_cxo_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_audio_cxo_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_audio_cxo_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_AVSYNC_XO_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_avsync_xo_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_avsync_xo_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_avsync_xo_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_XO_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_xo_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 dirty_m : 1; + u32 dirty_n : 1; + u32 dirty_d : 1; + u32 reserved1 : 23; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_xo_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_xo_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_XO_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_xo_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 6; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_xo_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_xo_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_XO_M +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_xo_m_s +{ + u32 m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_xo_m_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_xo_m_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_XO_N +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_xo_n_s +{ + u32 not_n_minus_m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_xo_n_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_xo_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_XO_D +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_xo_d_s +{ + u32 not_2d : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_xo_d_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_xo_d_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_EXT_I2S_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_ext_i2s_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_ext_i2s_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_ext_i2s_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_LPAIF_EXT_I2S_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_ext_i2s_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_lpaif_ext_i2s_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_ext_i2s_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_LPAIF_EXT_I2S_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_ext_i2s_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 dirty_m : 1; + u32 dirty_n : 1; + u32 dirty_d : 1; + u32 reserved1 : 23; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_lpaif_ext_i2s_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_ext_i2s_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_LPAIF_EXT_I2S_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_ext_i2s_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 6; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_lpaif_ext_i2s_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_ext_i2s_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_LPAIF_EXT_I2S_M +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_ext_i2s_m_s +{ + u32 m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_lpaif_ext_i2s_m_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_ext_i2s_m_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_LPAIF_EXT_I2S_N +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_ext_i2s_n_s +{ + u32 not_n_minus_m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_lpaif_ext_i2s_n_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_ext_i2s_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_LPAIF_EXT_I2S_D +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_ext_i2s_d_s +{ + u32 not_2d : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_lpaif_ext_i2s_d_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_ext_i2s_d_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SLIMBUS_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_slimbus_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_slimbus_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_slimbus_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_slimbus_core_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_lpaif_slimbus_core_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_slimbus_core_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_slimbus_core_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 dirty_m : 1; + u32 dirty_n : 1; + u32 dirty_d : 1; + u32 reserved1 : 23; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_lpaif_slimbus_core_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_slimbus_core_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_slimbus_core_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 6; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_lpaif_slimbus_core_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_slimbus_core_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_M +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_slimbus_core_m_s +{ + u32 m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_lpaif_slimbus_core_m_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_slimbus_core_m_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_N +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_slimbus_core_n_s +{ + u32 not_n_minus_m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_lpaif_slimbus_core_n_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_slimbus_core_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_LPAIF_SLIMBUS_CORE_D +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_slimbus_core_d_s +{ + u32 not_2d : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_lpaif_slimbus_core_d_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_slimbus_core_d_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_PCM_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_pcm_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_pcm_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_pcm_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_pcm_dataoe_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_lpaif_pcm_dataoe_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_pcm_dataoe_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_pcm_dataoe_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 dirty_m : 1; + u32 dirty_n : 1; + u32 dirty_d : 1; + u32 reserved1 : 23; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_lpaif_pcm_dataoe_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_pcm_dataoe_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_LPAIF_PCM_DATAOE_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_pcm_dataoe_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 6; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_lpaif_pcm_dataoe_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_pcm_dataoe_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_LPAIF_PCM_DATAOE_M +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_pcm_dataoe_m_s +{ + u32 m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_lpaif_pcm_dataoe_m_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_pcm_dataoe_m_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_LPAIF_PCM_DATAOE_N +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_pcm_dataoe_n_s +{ + u32 not_n_minus_m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_lpaif_pcm_dataoe_n_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_pcm_dataoe_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_LPAIF_PCM_DATAOE_D +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_pcm_dataoe_d_s +{ + u32 not_2d : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_lpaif_pcm_dataoe_d_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_pcm_dataoe_d_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_aux_pcm_dataoe_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_lpaif_aux_pcm_dataoe_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_aux_pcm_dataoe_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_aux_pcm_dataoe_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 dirty_m : 1; + u32 dirty_n : 1; + u32 dirty_d : 1; + u32 reserved1 : 23; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_lpaif_aux_pcm_dataoe_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_aux_pcm_dataoe_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_aux_pcm_dataoe_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 6; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_lpaif_aux_pcm_dataoe_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_aux_pcm_dataoe_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_M +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_aux_pcm_dataoe_m_s +{ + u32 m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_lpaif_aux_pcm_dataoe_m_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_aux_pcm_dataoe_m_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_N +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_aux_pcm_dataoe_n_s +{ + u32 not_n_minus_m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_lpaif_aux_pcm_dataoe_n_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_aux_pcm_dataoe_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ULTAUDIO_LPAIF_AUX_PCM_DATAOE_D +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_aux_pcm_dataoe_d_s +{ + u32 not_2d : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ultaudio_lpaif_aux_pcm_dataoe_d_u +{ + struct ipa_gcc_hwio_def_gcc_ultaudio_lpaif_aux_pcm_dataoe_d_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_gdscr_s +{ + u32 sw_collapse : 1; + u32 hw_control : 1; + u32 sw_override : 1; + u32 pd_ares : 1; + u32 clk_disable : 1; + u32 clamp_io : 1; + u32 en_few : 1; + u32 en_rest : 1; + u32 retain : 1; + u32 save : 1; + u32 restore : 1; + u32 retain_ff_enable : 1; + u32 clk_dis_wait : 4; + u32 en_few_wait : 4; + u32 en_rest_wait : 4; + u32 reserved0 : 3; + u32 gdsc_state : 4; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_CFG_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_cfg_gdscr_s +{ + u32 disable_clk_software_override : 1; + u32 clamp_io_software_override : 1; + u32 save_restore_software_override : 1; + u32 unclamp_io_software_override : 1; + u32 gdsc_pscbc_pwr_dwn_sw : 1; + u32 gdsc_phase_reset_delay_count_sw : 2; + u32 gdsc_phase_reset_en_sw : 1; + u32 gdsc_mem_core_force_in_sw : 1; + u32 gdsc_mem_peri_force_in_sw : 1; + u32 gdsc_handshake_dis : 1; + u32 software_control_override : 4; + u32 gdsc_power_down_complete : 1; + u32 gdsc_power_up_complete : 1; + u32 gdsc_enf_ack_status : 1; + u32 gdsc_enr_ack_status : 1; + u32 gdsc_mem_pwr_ack_status : 1; + u32 gdsc_cfg_fsm_state_status : 4; + u32 gdsc_pwr_up_start : 1; + u32 gdsc_pwr_dwn_start : 1; + u32 reserved0 : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_cfg_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_cfg_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_CFG2_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_cfg2_gdscr_s +{ + u32 mem_pwr_dwn_timeout : 4; + u32 dly_assert_clamp_mem : 4; + u32 dly_deassert_clamp_mem : 4; + u32 dly_mem_pwr_up : 4; + u32 gdsc_clamp_mem_sw : 1; + u32 gdsc_pwrdwn_enable_ack_override : 1; + u32 gdsc_mem_pwrup_ack_override : 1; + u32 reserved0 : 13; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_cfg2_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_cfg2_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_CFG3_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_cfg3_gdscr_s +{ + u32 gdsc_spare_ctrl_out : 8; + u32 gdsc_spare_ctrl_in : 8; + u32 gdsc_accu_red_sw_override : 1; + u32 gdsc_accu_red_shifter_start_sw : 1; + u32 gdsc_accu_red_shifter_clk_en_sw : 1; + u32 gdsc_accu_red_shifter_done_override : 1; + u32 gdsc_accu_red_timer_en_sw : 1; + u32 dly_accu_red_shifter_done : 4; + u32 gdsc_accu_red_enable : 1; + u32 gdsc_accu_red_shifter_done_status : 1; + u32 reserved0 : 5; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_cfg3_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_cfg3_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_CFG4_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_cfg4_gdscr_s +{ + u32 dly_retainff : 4; + u32 dly_clampio : 4; + u32 dly_deassertares : 4; + u32 dly_noretainff : 4; + u32 dly_restoreff : 4; + u32 dly_unclampio : 4; + u32 reserved0 : 8; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_cfg4_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_cfg4_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_SLV_Q2A_AXI_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_slv_q2a_axi_cbcr_s +{ + u32 reserved0 : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved1 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_slv_q2a_axi_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_slv_q2a_axi_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_SLV_AXI_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_slv_axi_cbcr_s +{ + u32 reserved0 : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 sleep : 4; + u32 wakeup : 4; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved1 : 5; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_slv_axi_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_slv_axi_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_SLV_AXI_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_slv_axi_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 8; + u32 sreg_pscbc_spare_ctrl_out : 8; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_slv_axi_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_slv_axi_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_MSTR_AXI_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_mstr_axi_cbcr_s +{ + u32 reserved0 : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 sleep : 4; + u32 wakeup : 4; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved1 : 5; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_mstr_axi_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_mstr_axi_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_MSTR_AXI_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_mstr_axi_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 8; + u32 sreg_pscbc_spare_ctrl_out : 8; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_mstr_axi_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_mstr_axi_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_CFG_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_cfg_ahb_cbcr_s +{ + u32 reserved0 : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved1 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_cfg_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_cfg_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_RCHNG_PHY_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_rchng_phy_cbcr_s +{ + u32 reserved0 : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved1 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_rchng_phy_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_rchng_phy_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_AUX_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_aux_cbcr_s +{ + u32 reserved0 : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved1 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_aux_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_aux_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_SLEEP_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_sleep_cbcr_s +{ + u32 reserved0 : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved1 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_sleep_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_sleep_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_PIPE_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_pipe_cbcr_s +{ + u32 reserved0 : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 sleep : 4; + u32 wakeup : 4; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved1 : 7; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_pipe_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_pipe_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_PIPE_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_pipe_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 8; + u32 sreg_pscbc_spare_ctrl_out : 8; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_pipe_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_pipe_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_AUX_PHY_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_aux_phy_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 dirty_m : 1; + u32 dirty_n : 1; + u32 dirty_d : 1; + u32 reserved1 : 23; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_aux_phy_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_aux_phy_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_AUX_PHY_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_aux_phy_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 6; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_aux_phy_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_aux_phy_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_AUX_PHY_M +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_aux_phy_m_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_aux_phy_m_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_aux_phy_m_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_AUX_PHY_N +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_aux_phy_n_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_aux_phy_n_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_aux_phy_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_AUX_PHY_D +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_aux_phy_d_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_aux_phy_d_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_aux_phy_d_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_RCHNG_PHY_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_rchng_phy_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_rchng_phy_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_rchng_phy_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_RCHNG_PHY_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_rchng_phy_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_rchng_phy_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_rchng_phy_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_PHY_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_phy_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_phy_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_phy_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_VS_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_vs_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_vs_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_vs_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_VDDCX_VS_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_vddcx_vs_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_vddcx_vs_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_vddcx_vs_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_VDDMX_VS_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_vddmx_vs_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_vddmx_vs_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_vddmx_vs_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_VDDA_VS_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_vdda_vs_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_vdda_vs_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_vdda_vs_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_VDDMXC_VS_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_vddmxc_vs_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_vddmxc_vs_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_vddmxc_vs_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_VS_CTRL_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_vs_ctrl_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_vs_ctrl_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_vs_ctrl_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_VS_CTRL_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_vs_ctrl_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_vs_ctrl_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_vs_ctrl_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_VSENSOR_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_vsensor_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_vsensor_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_vsensor_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_VSENSOR_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_vsensor_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_vsensor_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_vsensor_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_VS_CTRL_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_vs_ctrl_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_vs_ctrl_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_vs_ctrl_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_VS_CTRL_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_vs_ctrl_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_vs_ctrl_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_vs_ctrl_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_VS_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_vs_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_vs_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_mss_vs_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DCC_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_dcc_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_dcc_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_dcc_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DCC_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_dcc_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 sleep : 4; + u32 wakeup : 4; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved0 : 5; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_dcc_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_dcc_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DCC_AHB_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_dcc_ahb_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 8; + u32 sreg_pscbc_spare_ctrl_out : 8; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_dcc_ahb_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_dcc_ahb_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_IPA_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ipa_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ipa_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_ipa_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_IPA_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ipa_gdscr_s +{ + u32 sw_collapse : 1; + u32 hw_control : 1; + u32 sw_override : 1; + u32 pd_ares : 1; + u32 clk_disable : 1; + u32 clamp_io : 1; + u32 en_few : 1; + u32 en_rest : 1; + u32 retain : 1; + u32 save : 1; + u32 restore : 1; + u32 retain_ff_enable : 1; + u32 clk_dis_wait : 4; + u32 en_few_wait : 4; + u32 en_rest_wait : 4; + u32 reserved0 : 3; + u32 gdsc_state : 4; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ipa_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_ipa_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_IPA_CFG_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ipa_cfg_gdscr_s +{ + u32 disable_clk_software_override : 1; + u32 clamp_io_software_override : 1; + u32 save_restore_software_override : 1; + u32 unclamp_io_software_override : 1; + u32 gdsc_pscbc_pwr_dwn_sw : 1; + u32 gdsc_phase_reset_delay_count_sw : 2; + u32 gdsc_phase_reset_en_sw : 1; + u32 gdsc_mem_core_force_in_sw : 1; + u32 gdsc_mem_peri_force_in_sw : 1; + u32 gdsc_handshake_dis : 1; + u32 software_control_override : 4; + u32 gdsc_power_down_complete : 1; + u32 gdsc_power_up_complete : 1; + u32 gdsc_enf_ack_status : 1; + u32 gdsc_enr_ack_status : 1; + u32 gdsc_mem_pwr_ack_status : 1; + u32 gdsc_cfg_fsm_state_status : 4; + u32 gdsc_pwr_up_start : 1; + u32 gdsc_pwr_dwn_start : 1; + u32 reserved0 : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ipa_cfg_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_ipa_cfg_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_IPA_CFG2_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ipa_cfg2_gdscr_s +{ + u32 mem_pwr_dwn_timeout : 4; + u32 dly_assert_clamp_mem : 4; + u32 dly_deassert_clamp_mem : 4; + u32 dly_mem_pwr_up : 4; + u32 gdsc_clamp_mem_sw : 1; + u32 gdsc_pwrdwn_enable_ack_override : 1; + u32 gdsc_mem_pwrup_ack_override : 1; + u32 reserved0 : 13; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ipa_cfg2_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_ipa_cfg2_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_IPA_CFG3_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ipa_cfg3_gdscr_s +{ + u32 gdsc_spare_ctrl_out : 8; + u32 gdsc_spare_ctrl_in : 8; + u32 gdsc_accu_red_sw_override : 1; + u32 gdsc_accu_red_shifter_start_sw : 1; + u32 gdsc_accu_red_shifter_clk_en_sw : 1; + u32 gdsc_accu_red_shifter_done_override : 1; + u32 gdsc_accu_red_timer_en_sw : 1; + u32 dly_accu_red_shifter_done : 4; + u32 gdsc_accu_red_enable : 1; + u32 gdsc_accu_red_shifter_done_status : 1; + u32 reserved0 : 5; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ipa_cfg3_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_ipa_cfg3_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_IPA_CFG4_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ipa_cfg4_gdscr_s +{ + u32 dly_retainff : 4; + u32 dly_clampio : 4; + u32 dly_deassertares : 4; + u32 dly_noretainff : 4; + u32 dly_restoreff : 4; + u32 dly_unclampio : 4; + u32 reserved0 : 8; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ipa_cfg4_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_ipa_cfg4_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_IPA_2X_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ipa_2x_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 1; + u32 sleep : 4; + u32 wakeup : 4; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved2 : 5; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved3 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved4 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ipa_2x_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ipa_2x_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_IPA_2X_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ipa_2x_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 8; + u32 sreg_pscbc_spare_ctrl_out : 8; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ipa_2x_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_ipa_2x_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_IPA_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ipa_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 1; + u32 sleep : 4; + u32 wakeup : 4; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved2 : 5; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved3 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved4 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ipa_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ipa_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_IPA_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ipa_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 8; + u32 sreg_pscbc_spare_ctrl_out : 8; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ipa_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_ipa_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_IPA_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ipa_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ipa_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ipa_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_IPA_XO_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ipa_xo_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ipa_xo_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ipa_xo_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_IPA_2X_CDIV_DCD_DCDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ipa_2x_cdiv_dcd_dcdr_s +{ + u32 dcd_enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ipa_2x_cdiv_dcd_dcdr_u +{ + struct ipa_gcc_hwio_def_gcc_ipa_2x_cdiv_dcd_dcdr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_CMD_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_cmd_dfsr_s +{ + u32 dfs_en : 1; + u32 curr_perf_state : 4; + u32 hw_clk_control : 1; + u32 dfs_fsm_state : 3; + u32 perf_state_update_status : 1; + u32 sw_override : 1; + u32 sw_perf_state : 4; + u32 rcg_sw_ctrl : 1; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_cmd_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_cmd_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF8_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf8_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf8_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf8_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF9_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf9_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf9_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf9_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF10_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf10_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf10_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf10_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF11_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf11_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf11_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf11_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF12_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf12_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf12_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf12_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF13_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf13_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf13_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf13_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF14_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf14_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf14_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf14_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF15_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf15_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf15_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf15_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF0_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf0_m_dfsr_s +{ + u32 m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf0_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf0_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF1_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf1_m_dfsr_s +{ + u32 m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf1_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf1_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF2_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf2_m_dfsr_s +{ + u32 m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf2_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf2_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF3_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf3_m_dfsr_s +{ + u32 m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf3_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf3_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF4_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf4_m_dfsr_s +{ + u32 m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf4_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf4_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF5_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf5_m_dfsr_s +{ + u32 m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf5_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf5_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF6_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf6_m_dfsr_s +{ + u32 m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf6_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf6_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF7_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf7_m_dfsr_s +{ + u32 m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf7_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf7_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF8_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf8_m_dfsr_s +{ + u32 m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf8_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf8_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF9_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf9_m_dfsr_s +{ + u32 m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf9_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf9_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF10_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf10_m_dfsr_s +{ + u32 m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf10_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf10_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF11_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf11_m_dfsr_s +{ + u32 m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf11_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf11_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF12_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf12_m_dfsr_s +{ + u32 m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf12_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf12_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF13_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf13_m_dfsr_s +{ + u32 m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf13_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf13_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF14_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf14_m_dfsr_s +{ + u32 m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf14_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf14_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF15_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf15_m_dfsr_s +{ + u32 m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf15_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf15_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF0_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf0_n_dfsr_s +{ + u32 not_n_minus_m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf0_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf0_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF1_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf1_n_dfsr_s +{ + u32 not_n_minus_m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf1_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf1_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF2_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf2_n_dfsr_s +{ + u32 not_n_minus_m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf2_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf2_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF3_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf3_n_dfsr_s +{ + u32 not_n_minus_m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf3_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf3_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF4_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf4_n_dfsr_s +{ + u32 not_n_minus_m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf4_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf4_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF5_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf5_n_dfsr_s +{ + u32 not_n_minus_m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf5_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf5_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF6_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf6_n_dfsr_s +{ + u32 not_n_minus_m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf6_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf6_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF7_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf7_n_dfsr_s +{ + u32 not_n_minus_m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf7_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf7_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF8_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf8_n_dfsr_s +{ + u32 not_n_minus_m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf8_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf8_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF9_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf9_n_dfsr_s +{ + u32 not_n_minus_m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf9_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf9_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF10_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf10_n_dfsr_s +{ + u32 not_n_minus_m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf10_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf10_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF11_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf11_n_dfsr_s +{ + u32 not_n_minus_m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf11_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf11_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF12_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf12_n_dfsr_s +{ + u32 not_n_minus_m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf12_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf12_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF13_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf13_n_dfsr_s +{ + u32 not_n_minus_m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf13_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf13_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF14_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf14_n_dfsr_s +{ + u32 not_n_minus_m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf14_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf14_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF15_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf15_n_dfsr_s +{ + u32 not_n_minus_m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf15_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf15_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF0_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf0_d_dfsr_s +{ + u32 not_2d : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf0_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf0_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF1_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf1_d_dfsr_s +{ + u32 not_2d : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf1_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf1_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF2_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf2_d_dfsr_s +{ + u32 not_2d : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf2_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf2_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF3_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf3_d_dfsr_s +{ + u32 not_2d : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf3_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf3_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF4_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf4_d_dfsr_s +{ + u32 not_2d : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf4_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf4_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF5_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf5_d_dfsr_s +{ + u32 not_2d : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf5_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf5_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF6_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf6_d_dfsr_s +{ + u32 not_2d : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf6_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf6_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF7_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf7_d_dfsr_s +{ + u32 not_2d : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf7_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf7_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF8_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf8_d_dfsr_s +{ + u32 not_2d : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf8_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf8_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF9_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf9_d_dfsr_s +{ + u32 not_2d : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf9_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf9_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF10_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf10_d_dfsr_s +{ + u32 not_2d : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf10_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf10_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF11_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf11_d_dfsr_s +{ + u32 not_2d : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf11_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf11_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF12_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf12_d_dfsr_s +{ + u32 not_2d : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf12_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf12_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF13_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf13_d_dfsr_s +{ + u32 not_2d : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf13_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf13_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF14_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf14_d_dfsr_s +{ + u32 not_2d : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf14_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf14_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF15_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf15_d_dfsr_s +{ + u32 not_2d : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf15_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf15_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_IPA_2X_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ipa_2x_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 dirty_m : 1; + u32 dirty_n : 1; + u32 dirty_d : 1; + u32 reserved1 : 23; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ipa_2x_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_ipa_2x_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_IPA_2X_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ipa_2x_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 6; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ipa_2x_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_ipa_2x_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_IPA_2X_M +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ipa_2x_m_s +{ + u32 m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ipa_2x_m_u +{ + struct ipa_gcc_hwio_def_gcc_ipa_2x_m_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_IPA_2X_N +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ipa_2x_n_s +{ + u32 not_n_minus_m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ipa_2x_n_u +{ + struct ipa_gcc_hwio_def_gcc_ipa_2x_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_IPA_2X_D +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ipa_2x_d_s +{ + u32 not_2d : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ipa_2x_d_u +{ + struct ipa_gcc_hwio_def_gcc_ipa_2x_d_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_IPA_CDIVR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ipa_cdivr_s +{ + u32 clk_div : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ipa_cdivr_u +{ + struct ipa_gcc_hwio_def_gcc_ipa_cdivr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QPIC_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qpic_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qpic_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_qpic_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QPIC_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qpic_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 1; + u32 sleep : 4; + u32 wakeup : 4; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved2 : 5; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved3 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved4 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qpic_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qpic_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QPIC_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qpic_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 8; + u32 sreg_pscbc_spare_ctrl_out : 8; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qpic_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_qpic_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QPIC_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qpic_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qpic_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qpic_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QPIC_SYSTEM_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qpic_system_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qpic_system_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qpic_system_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_CMD_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_cmd_dfsr_s +{ + u32 dfs_en : 1; + u32 curr_perf_state : 4; + u32 hw_clk_control : 1; + u32 dfs_fsm_state : 3; + u32 perf_state_update_status : 1; + u32 sw_override : 1; + u32 sw_perf_state : 4; + u32 rcg_sw_ctrl : 1; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_cmd_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_cmd_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF8_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf8_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf8_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf8_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF9_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf9_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf9_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf9_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF10_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf10_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf10_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf10_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF11_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf11_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf11_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf11_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF12_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf12_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf12_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf12_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF13_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf13_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf13_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf13_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF14_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf14_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf14_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf14_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF15_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf15_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf15_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf15_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF0_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf0_m_dfsr_s +{ + u32 m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf0_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf0_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF1_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf1_m_dfsr_s +{ + u32 m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf1_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf1_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF2_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf2_m_dfsr_s +{ + u32 m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf2_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf2_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF3_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf3_m_dfsr_s +{ + u32 m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf3_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf3_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF4_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf4_m_dfsr_s +{ + u32 m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf4_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf4_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF5_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf5_m_dfsr_s +{ + u32 m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf5_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf5_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF6_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf6_m_dfsr_s +{ + u32 m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf6_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf6_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF7_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf7_m_dfsr_s +{ + u32 m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf7_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf7_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF8_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf8_m_dfsr_s +{ + u32 m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf8_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf8_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF9_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf9_m_dfsr_s +{ + u32 m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf9_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf9_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF10_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf10_m_dfsr_s +{ + u32 m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf10_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf10_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF11_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf11_m_dfsr_s +{ + u32 m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf11_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf11_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF12_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf12_m_dfsr_s +{ + u32 m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf12_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf12_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF13_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf13_m_dfsr_s +{ + u32 m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf13_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf13_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF14_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf14_m_dfsr_s +{ + u32 m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf14_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf14_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF15_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf15_m_dfsr_s +{ + u32 m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf15_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf15_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF0_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf0_n_dfsr_s +{ + u32 not_n_minus_m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf0_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf0_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF1_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf1_n_dfsr_s +{ + u32 not_n_minus_m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf1_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf1_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF2_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf2_n_dfsr_s +{ + u32 not_n_minus_m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf2_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf2_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF3_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf3_n_dfsr_s +{ + u32 not_n_minus_m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf3_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf3_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF4_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf4_n_dfsr_s +{ + u32 not_n_minus_m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf4_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf4_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF5_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf5_n_dfsr_s +{ + u32 not_n_minus_m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf5_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf5_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF6_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf6_n_dfsr_s +{ + u32 not_n_minus_m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf6_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf6_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF7_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf7_n_dfsr_s +{ + u32 not_n_minus_m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf7_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf7_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF8_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf8_n_dfsr_s +{ + u32 not_n_minus_m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf8_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf8_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF9_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf9_n_dfsr_s +{ + u32 not_n_minus_m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf9_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf9_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF10_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf10_n_dfsr_s +{ + u32 not_n_minus_m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf10_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf10_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF11_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf11_n_dfsr_s +{ + u32 not_n_minus_m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf11_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf11_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF12_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf12_n_dfsr_s +{ + u32 not_n_minus_m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf12_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf12_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF13_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf13_n_dfsr_s +{ + u32 not_n_minus_m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf13_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf13_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF14_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf14_n_dfsr_s +{ + u32 not_n_minus_m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf14_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf14_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF15_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf15_n_dfsr_s +{ + u32 not_n_minus_m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf15_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf15_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF0_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf0_d_dfsr_s +{ + u32 not_2d : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf0_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf0_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF1_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf1_d_dfsr_s +{ + u32 not_2d : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf1_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf1_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF2_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf2_d_dfsr_s +{ + u32 not_2d : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf2_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf2_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF3_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf3_d_dfsr_s +{ + u32 not_2d : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf3_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf3_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF4_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf4_d_dfsr_s +{ + u32 not_2d : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf4_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf4_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF5_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf5_d_dfsr_s +{ + u32 not_2d : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf5_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf5_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF6_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf6_d_dfsr_s +{ + u32 not_2d : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf6_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf6_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF7_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf7_d_dfsr_s +{ + u32 not_2d : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf7_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf7_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF8_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf8_d_dfsr_s +{ + u32 not_2d : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf8_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf8_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF9_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf9_d_dfsr_s +{ + u32 not_2d : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf9_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf9_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF10_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf10_d_dfsr_s +{ + u32 not_2d : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf10_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf10_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF11_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf11_d_dfsr_s +{ + u32 not_2d : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf11_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf11_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF12_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf12_d_dfsr_s +{ + u32 not_2d : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf12_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf12_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF13_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf13_d_dfsr_s +{ + u32 not_2d : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf13_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf13_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF14_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf14_d_dfsr_s +{ + u32 not_2d : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf14_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf14_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_QPIC_PERF15_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf15_d_dfsr_s +{ + u32 not_2d : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf15_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_qpic_perf15_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QPIC_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qpic_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 dirty_m : 1; + u32 dirty_n : 1; + u32 dirty_d : 1; + u32 reserved1 : 23; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qpic_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qpic_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QPIC_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qpic_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 6; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qpic_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qpic_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QPIC_M +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qpic_m_s +{ + u32 m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qpic_m_u +{ + struct ipa_gcc_hwio_def_gcc_qpic_m_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QPIC_N +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qpic_n_s +{ + u32 not_n_minus_m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qpic_n_u +{ + struct ipa_gcc_hwio_def_gcc_qpic_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QPIC_D +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qpic_d_s +{ + u32 not_2d : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qpic_d_u +{ + struct ipa_gcc_hwio_def_gcc_qpic_d_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPMI_FETCHER_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spmi_fetcher_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spmi_fetcher_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_spmi_fetcher_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPMI_FETCHER_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spmi_fetcher_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spmi_fetcher_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_spmi_fetcher_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPMI_FETCHER_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spmi_fetcher_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spmi_fetcher_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_spmi_fetcher_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPMI_FETCHER_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spmi_fetcher_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spmi_fetcher_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_spmi_fetcher_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPMI_FETCHER_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spmi_fetcher_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spmi_fetcher_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_spmi_fetcher_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_CFG_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_cfg_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_cfg_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_mss_cfg_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_OFFLINE_AXI_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_offline_axi_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_offline_axi_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_mss_offline_axi_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_CE_AXI_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_ce_axi_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_ce_axi_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_mss_ce_axi_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_TRIG_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_trig_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_trig_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_mss_trig_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_AT_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_at_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_at_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_mss_at_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_PLL0_MAIN_DIV_CDIVR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_pll0_main_div_cdivr_s +{ + u32 clk_div : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_pll0_main_div_cdivr_u +{ + struct ipa_gcc_hwio_def_gcc_mss_pll0_main_div_cdivr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_mcdma_memnoc_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mss_mcdma_memnoc_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_mcdma_memnoc_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_mcdma_memnoc_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mss_mcdma_memnoc_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_mcdma_memnoc_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_mcdma_memnoc_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mss_mcdma_memnoc_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_mcdma_memnoc_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_mcdma_memnoc_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mss_mcdma_memnoc_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_mcdma_memnoc_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_mcdma_memnoc_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mss_mcdma_memnoc_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_mcdma_memnoc_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_mcdma_memnoc_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mss_mcdma_memnoc_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_mcdma_memnoc_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_mcdma_memnoc_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mss_mcdma_memnoc_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_mcdma_memnoc_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_mcdma_memnoc_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mss_mcdma_memnoc_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_mcdma_memnoc_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF8_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_mcdma_memnoc_perf8_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mss_mcdma_memnoc_perf8_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_mcdma_memnoc_perf8_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF9_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_mcdma_memnoc_perf9_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mss_mcdma_memnoc_perf9_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_mcdma_memnoc_perf9_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF10_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_mcdma_memnoc_perf10_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mss_mcdma_memnoc_perf10_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_mcdma_memnoc_perf10_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF11_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_mcdma_memnoc_perf11_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mss_mcdma_memnoc_perf11_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_mcdma_memnoc_perf11_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF12_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_mcdma_memnoc_perf12_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mss_mcdma_memnoc_perf12_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_mcdma_memnoc_perf12_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF13_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_mcdma_memnoc_perf13_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mss_mcdma_memnoc_perf13_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_mcdma_memnoc_perf13_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF14_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_mcdma_memnoc_perf14_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mss_mcdma_memnoc_perf14_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_mcdma_memnoc_perf14_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MSS_MCDMA_MEMNOC_PERF15_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_mcdma_memnoc_perf15_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mss_mcdma_memnoc_perf15_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_mcdma_memnoc_perf15_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_MCDMA_MEMNOC_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_mcdma_memnoc_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_mcdma_memnoc_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_mss_mcdma_memnoc_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_MCDMA_MEMNOC_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_mcdma_memnoc_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_mcdma_memnoc_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_mss_mcdma_memnoc_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_SNOC_AXI_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_snoc_axi_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_snoc_axi_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_mss_snoc_axi_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_Q6VQ6_AXIM1_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_q6vq6_axim1_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_q6vq6_axim1_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_mss_q6vq6_axim1_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QREFS_VBG_CAL_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qrefs_vbg_cal_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qrefs_vbg_cal_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_qrefs_vbg_cal_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QREFS_VBG_CAL_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qrefs_vbg_cal_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qrefs_vbg_cal_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qrefs_vbg_cal_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_NAV_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_nav_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_nav_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_nav_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_NAV_SNOC_AXI_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_nav_snoc_axi_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_nav_snoc_axi_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_nav_snoc_axi_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPLL4_OUT_EVEN_DIV_CDIVR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpll4_out_even_div_cdivr_s +{ + u32 clk_div : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpll4_out_even_div_cdivr_u +{ + struct ipa_gcc_hwio_def_gcc_gpll4_out_even_div_cdivr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CM_PHY_REFGEN1_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cm_phy_refgen1_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cm_phy_refgen1_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_cm_phy_refgen1_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CM_PHY_REFGEN1_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cm_phy_refgen1_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cm_phy_refgen1_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_cm_phy_refgen1_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ECC_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ecc_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ecc_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_ecc_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ECC_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ecc_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ecc_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ecc_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ECC_CORE_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ecc_core_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 1; + u32 sleep : 4; + u32 wakeup : 4; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved2 : 5; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved3 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved4 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ecc_core_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ecc_core_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ECC_CORE_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ecc_core_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 8; + u32 sreg_pscbc_spare_ctrl_out : 8; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ecc_core_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_ecc_core_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PKA_CMD_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pka_cmd_dfsr_s +{ + u32 dfs_en : 1; + u32 curr_perf_state : 4; + u32 hw_clk_control : 1; + u32 dfs_fsm_state : 3; + u32 perf_state_update_status : 1; + u32 sw_override : 1; + u32 sw_perf_state : 4; + u32 rcg_sw_ctrl : 1; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pka_cmd_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pka_cmd_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PKA_ECC_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pka_ecc_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pka_ecc_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pka_ecc_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PKA_ECC_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pka_ecc_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pka_ecc_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pka_ecc_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PKA_ECC_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pka_ecc_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pka_ecc_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pka_ecc_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PKA_ECC_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pka_ecc_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pka_ecc_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pka_ecc_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PKA_ECC_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pka_ecc_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pka_ecc_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pka_ecc_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PKA_ECC_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pka_ecc_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pka_ecc_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pka_ecc_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PKA_ECC_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pka_ecc_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pka_ecc_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pka_ecc_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PKA_ECC_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pka_ecc_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pka_ecc_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pka_ecc_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PKA_ECC_PERF8_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pka_ecc_perf8_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pka_ecc_perf8_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pka_ecc_perf8_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PKA_ECC_PERF9_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pka_ecc_perf9_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pka_ecc_perf9_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pka_ecc_perf9_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PKA_ECC_PERF10_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pka_ecc_perf10_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pka_ecc_perf10_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pka_ecc_perf10_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PKA_ECC_PERF11_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pka_ecc_perf11_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pka_ecc_perf11_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pka_ecc_perf11_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PKA_ECC_PERF12_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pka_ecc_perf12_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pka_ecc_perf12_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pka_ecc_perf12_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PKA_ECC_PERF13_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pka_ecc_perf13_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pka_ecc_perf13_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pka_ecc_perf13_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PKA_ECC_PERF14_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pka_ecc_perf14_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pka_ecc_perf14_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pka_ecc_perf14_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PKA_ECC_PERF15_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pka_ecc_perf15_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pka_ecc_perf15_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pka_ecc_perf15_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ECC_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ecc_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ecc_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_ecc_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ECC_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ecc_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ecc_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_ecc_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QM_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qm_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qm_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_qm_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QM_CFG_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qm_cfg_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qm_cfg_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qm_cfg_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QM_CORE_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qm_core_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qm_core_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qm_core_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QM_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qm_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qm_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qm_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QM_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qm_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qm_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qm_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_CE_NAV_BRIDGE_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_ce_nav_bridge_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_ce_nav_bridge_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_mss_ce_nav_bridge_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_CE_NAV_BRIDGE_AXI_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_ce_nav_bridge_axi_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_ce_nav_bridge_axi_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_mss_ce_nav_bridge_axi_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPMI_VGIS_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spmi_vgis_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spmi_vgis_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_spmi_vgis_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPMI_VGIS_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spmi_vgis_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spmi_vgis_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_spmi_vgis_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPMI_VGIS_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spmi_vgis_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spmi_vgis_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_spmi_vgis_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPMI_VGIS_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spmi_vgis_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spmi_vgis_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_spmi_vgis_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MISC_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_misc_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_misc_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_misc_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_LINK_DOWN_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_link_down_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_link_down_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_link_down_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_PHY_CFG_AHB_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_phy_cfg_ahb_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_phy_cfg_ahb_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_phy_cfg_ahb_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_PHY_COM_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_phy_com_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_phy_com_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_phy_com_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_NOCSR_COM_PHY_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_nocsr_com_phy_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_nocsr_com_phy_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_nocsr_com_phy_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_PHY_NOCSR_COM_PHY_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_phy_nocsr_com_phy_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_phy_nocsr_com_phy_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_phy_nocsr_com_phy_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPLL4_OUT_EVEN_PWRGRP1_CLKGEN_ACGC_ACGCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpll4_out_even_pwrgrp1_clkgen_acgc_acgcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpll4_out_even_pwrgrp1_clkgen_acgc_acgcr_u +{ + struct ipa_gcc_hwio_def_gcc_gpll4_out_even_pwrgrp1_clkgen_acgc_acgcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPLL4_OUT_EVEN_PWRGRP2_CLKGEN_ACGC_ACGCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpll4_out_even_pwrgrp2_clkgen_acgc_acgcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpll4_out_even_pwrgrp2_clkgen_acgc_acgcr_u +{ + struct ipa_gcc_hwio_def_gcc_gpll4_out_even_pwrgrp2_clkgen_acgc_acgcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPLL1_OUT_EVEN_PWRGRP2_CLKGEN_ACGC_ACGCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpll1_out_even_pwrgrp2_clkgen_acgc_acgcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpll1_out_even_pwrgrp2_clkgen_acgc_acgcr_u +{ + struct ipa_gcc_hwio_def_gcc_gpll1_out_even_pwrgrp2_clkgen_acgc_acgcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPLL1_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpll1_out_main_pwrgrp1_clkgen_acgc_acgcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpll1_out_main_pwrgrp1_clkgen_acgc_acgcr_u +{ + struct ipa_gcc_hwio_def_gcc_gpll1_out_main_pwrgrp1_clkgen_acgc_acgcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPLL5_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpll5_out_main_pwrgrp1_clkgen_acgc_acgcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpll5_out_main_pwrgrp1_clkgen_acgc_acgcr_u +{ + struct ipa_gcc_hwio_def_gcc_gpll5_out_main_pwrgrp1_clkgen_acgc_acgcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPLL5_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpll5_out_main_pwrgrp2_clkgen_acgc_acgcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpll5_out_main_pwrgrp2_clkgen_acgc_acgcr_u +{ + struct ipa_gcc_hwio_def_gcc_gpll5_out_main_pwrgrp2_clkgen_acgc_acgcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp1_clkgen_acgc_acgcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp1_clkgen_acgc_acgcr_u +{ + struct ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp1_clkgen_acgc_acgcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp2_clkgen_acgc_acgcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp2_clkgen_acgc_acgcr_u +{ + struct ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp2_clkgen_acgc_acgcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp3_clkgen_acgc_acgcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp3_clkgen_acgc_acgcr_u +{ + struct ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp3_clkgen_acgc_acgcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp4_clkgen_acgc_acgcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp4_clkgen_acgc_acgcr_u +{ + struct ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp4_clkgen_acgc_acgcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp5_clkgen_acgc_acgcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp5_clkgen_acgc_acgcr_u +{ + struct ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp5_clkgen_acgc_acgcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp6_clkgen_acgc_acgcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp6_clkgen_acgc_acgcr_u +{ + struct ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp6_clkgen_acgc_acgcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp7_clkgen_acgc_acgcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp7_clkgen_acgc_acgcr_u +{ + struct ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp7_clkgen_acgc_acgcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp8_clkgen_acgc_acgcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp8_clkgen_acgc_acgcr_u +{ + struct ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp8_clkgen_acgc_acgcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp9_clkgen_acgc_acgcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp9_clkgen_acgc_acgcr_u +{ + struct ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp9_clkgen_acgc_acgcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp10_clkgen_acgc_acgcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp10_clkgen_acgc_acgcr_u +{ + struct ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp10_clkgen_acgc_acgcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp11_clkgen_acgc_acgcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp11_clkgen_acgc_acgcr_u +{ + struct ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp11_clkgen_acgc_acgcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp12_clkgen_acgc_acgcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp12_clkgen_acgc_acgcr_u +{ + struct ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp12_clkgen_acgc_acgcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpll0_out_even_pwrgrp15_clkgen_acgc_acgcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpll0_out_even_pwrgrp15_clkgen_acgc_acgcr_u +{ + struct ipa_gcc_hwio_def_gcc_gpll0_out_even_pwrgrp15_clkgen_acgc_acgcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_NAV_MBIST_ACGCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_nav_mbist_acgcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_nav_mbist_acgcr_u +{ + struct ipa_gcc_hwio_def_gcc_nav_mbist_acgcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB3_PHY_PIPE_MUXR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb3_phy_pipe_muxr_s +{ + u32 mux_sel : 2; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb3_phy_pipe_muxr_u +{ + struct ipa_gcc_hwio_def_gcc_usb3_phy_pipe_muxr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_JBIST_REF_CLK_MUXR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_jbist_ref_clk_muxr_s +{ + u32 mux_sel : 2; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_jbist_ref_clk_muxr_u +{ + struct ipa_gcc_hwio_def_gcc_jbist_ref_clk_muxr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_PIPE_MUXR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_pipe_muxr_s +{ + u32 mux_sel : 2; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_pipe_muxr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_pipe_muxr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_AUX_MUXR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_aux_muxr_s +{ + u32 mux_sel : 2; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_aux_muxr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_aux_muxr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_MBIST_MUXR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_mbist_muxr_s +{ + u32 mux_sel : 2; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_mbist_muxr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_mbist_muxr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_NAV_MBIST_MUXR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_nav_mbist_muxr_s +{ + u32 mux_sel : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_nav_mbist_muxr_u +{ + struct ipa_gcc_hwio_def_gcc_nav_mbist_muxr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_Q6SS_BOOT_GPLL0_MUXR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_q6ss_boot_gpll0_muxr_s +{ + u32 mux_sel : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_q6ss_boot_gpll0_muxr_u +{ + struct ipa_gcc_hwio_def_gcc_mss_q6ss_boot_gpll0_muxr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AUDIO_PLL_REF_MUXR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_audio_pll_ref_muxr_s +{ + u32 mux_sel : 2; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_audio_pll_ref_muxr_u +{ + struct ipa_gcc_hwio_def_gcc_audio_pll_ref_muxr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_IPA_AHB_MISC_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ipa_ahb_misc_cbcr_s +{ + u32 reserved0 : 1; + u32 hw_ctl : 1; + u32 reserved1 : 30; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ipa_ahb_misc_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ipa_ahb_misc_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TCSR_PCIE_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tcsr_pcie_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tcsr_pcie_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_tcsr_pcie_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPLL4_PLL_TEST_SE_OVRD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpll4_pll_test_se_ovrd_s +{ + u32 ovrd : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpll4_pll_test_se_ovrd_u +{ + struct ipa_gcc_hwio_def_gcc_gpll4_pll_test_se_ovrd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ACC_MISC +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_acc_misc_s +{ + u32 jtag_acc_src_sel_en : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_acc_misc_u +{ + struct ipa_gcc_hwio_def_gcc_acc_misc_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CPUSS_AHB_MISC +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cpuss_ahb_misc_s +{ + u32 cpuss_ahb_clk_auto_scale_dis : 1; + u32 reserved0 : 3; + u32 cpuss_ahb_clk_auto_scale_div : 4; + u32 reserved1 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cpuss_ahb_misc_u +{ + struct ipa_gcc_hwio_def_gcc_cpuss_ahb_misc_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB_30_MISC +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb_30_misc_s +{ + u32 blk_ares_all : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb_30_misc_u +{ + struct ipa_gcc_hwio_def_gcc_usb_30_misc_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPM_GPLL_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpm_gpll_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2 : 1; + u32 gpll3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 gpll6 : 1; + u32 reserved0 : 25; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpm_gpll_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpm_gpll_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPM_GPLL_SLEEP_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpm_gpll_sleep_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2 : 1; + u32 gpll3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 gpll6 : 1; + u32 reserved0 : 25; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpm_gpll_sleep_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpm_gpll_sleep_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPM_CLOCK_BRANCH_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpm_clock_branch_ena_vote_s +{ + u32 sys_noc_cpuss_ahb_clk_ena : 1; + u32 tcsr_ahb_clk_ena : 1; + u32 qdss_cfg_ahb_clk_ena : 1; + u32 ce1_ahb_clk_ena : 1; + u32 ce1_axi_clk_ena : 1; + u32 ce1_clk_ena : 1; + u32 tlmm_clk_ena : 1; + u32 ultaudio_pcnoc_sway_clk_ena : 1; + u32 ultaudio_ahbfabric_ixfabric_clk_ena : 1; + u32 reserved0 : 1; + u32 boot_rom_ahb_clk_ena : 1; + u32 reserved1 : 1; + u32 tlmm_ahb_clk_ena : 1; + u32 prng_ahb_clk_ena : 1; + u32 blsp1_ahb_clk_ena : 1; + u32 blsp1_sleep_clk_ena : 1; + u32 reserved2 : 1; + u32 mss_gpll0_div_clk_src_ena : 1; + u32 reserved3 : 3; + u32 cpuss_ahb_clk_ena : 1; + u32 cpuss_gnoc_clk_ena : 1; + u32 reserved4 : 1; + u32 imem_axi_clk_ena : 1; + u32 reserved5 : 7; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpm_clock_branch_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpm_clock_branch_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPM_CLOCK_SLEEP_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpm_clock_sleep_ena_vote_s +{ + u32 sys_noc_cpuss_ahb_clk_sleep_ena : 1; + u32 tcsr_ahb_clk_sleep_ena : 1; + u32 qdss_cfg_ahb_clk_sleep_ena : 1; + u32 ce1_ahb_clk_sleep_ena : 1; + u32 ce1_axi_clk_sleep_ena : 1; + u32 ce1_clk_sleep_ena : 1; + u32 tlmm_clk_sleep_ena : 1; + u32 ultaudio_pcnoc_sway_clk_sleep_ena : 1; + u32 ultaudio_ahbfabric_ixfabric_clk_sleep_ena : 1; + u32 reserved0 : 1; + u32 boot_rom_ahb_clk_sleep_ena : 1; + u32 reserved1 : 1; + u32 tlmm_ahb_clk_sleep_ena : 1; + u32 prng_ahb_clk_sleep_ena : 1; + u32 blsp1_ahb_clk_sleep_ena : 1; + u32 blsp1_sleep_clk_sleep_ena : 1; + u32 reserved2 : 1; + u32 mss_gpll0_div_clk_src_sleep_ena : 1; + u32 reserved3 : 3; + u32 cpuss_ahb_clk_sleep_ena : 1; + u32 cpuss_gnoc_clk_sleep_ena : 1; + u32 reserved4 : 1; + u32 imem_axi_clk_sleep_ena : 1; + u32 reserved5 : 7; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpm_clock_sleep_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpm_clock_sleep_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpm_clock_branch_ena_vote_1_s +{ + u32 pcie_slv_axi_clk_ena : 1; + u32 pcie_mstr_axi_clk_ena : 1; + u32 pcie_cfg_ahb_clk_ena : 1; + u32 pcie_aux_clk_ena : 1; + u32 pcie_pipe_clk_ena : 1; + u32 pcie_slv_q2a_axi_clk_ena : 1; + u32 pcie_sleep_clk_ena : 1; + u32 pcie_rchng_phy_clk_ena : 1; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpm_clock_branch_ena_vote_1_u +{ + struct ipa_gcc_hwio_def_gcc_rpm_clock_branch_ena_vote_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpm_clock_sleep_ena_vote_1_s +{ + u32 pcie_slv_axi_clk_sleep_ena : 1; + u32 pcie_mstr_axi_clk_sleep_ena : 1; + u32 pcie_cfg_ahb_clk_sleep_ena : 1; + u32 pcie_aux_clk_sleep_ena : 1; + u32 pcie_pipe_clk_sleep_ena : 1; + u32 pcie_slv_q2a_axi_clk_sleep_ena : 1; + u32 pcie_sleep_clk_sleep_ena : 1; + u32 pcie_rchng_phy_clk_sleep_ena : 1; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpm_clock_sleep_ena_vote_1_u +{ + struct ipa_gcc_hwio_def_gcc_rpm_clock_sleep_ena_vote_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_APCS_GPLL_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_apcs_gpll_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2 : 1; + u32 gpll3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 gpll6 : 1; + u32 reserved0 : 25; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_apcs_gpll_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_apcs_gpll_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_APCS_GPLL_SLEEP_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_apcs_gpll_sleep_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2 : 1; + u32 gpll3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 gpll6 : 1; + u32 reserved0 : 25; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_apcs_gpll_sleep_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_apcs_gpll_sleep_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_APCS_CLOCK_BRANCH_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_apcs_clock_branch_ena_vote_s +{ + u32 sys_noc_cpuss_ahb_clk_ena : 1; + u32 tcsr_ahb_clk_ena : 1; + u32 qdss_cfg_ahb_clk_ena : 1; + u32 ce1_ahb_clk_ena : 1; + u32 ce1_axi_clk_ena : 1; + u32 ce1_clk_ena : 1; + u32 tlmm_clk_ena : 1; + u32 ultaudio_pcnoc_sway_clk_ena : 1; + u32 ultaudio_ahbfabric_ixfabric_clk_ena : 1; + u32 reserved0 : 1; + u32 boot_rom_ahb_clk_ena : 1; + u32 reserved1 : 1; + u32 tlmm_ahb_clk_ena : 1; + u32 prng_ahb_clk_ena : 1; + u32 blsp1_ahb_clk_ena : 1; + u32 blsp1_sleep_clk_ena : 1; + u32 reserved2 : 1; + u32 mss_gpll0_div_clk_src_ena : 1; + u32 reserved3 : 3; + u32 cpuss_ahb_clk_ena : 1; + u32 cpuss_gnoc_clk_ena : 1; + u32 reserved4 : 1; + u32 imem_axi_clk_ena : 1; + u32 reserved5 : 7; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_apcs_clock_branch_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_apcs_clock_branch_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_APCS_CLOCK_SLEEP_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_apcs_clock_sleep_ena_vote_s +{ + u32 sys_noc_cpuss_ahb_clk_sleep_ena : 1; + u32 tcsr_ahb_clk_sleep_ena : 1; + u32 qdss_cfg_ahb_clk_sleep_ena : 1; + u32 ce1_ahb_clk_sleep_ena : 1; + u32 ce1_axi_clk_sleep_ena : 1; + u32 ce1_clk_sleep_ena : 1; + u32 tlmm_clk_sleep_ena : 1; + u32 ultaudio_pcnoc_sway_clk_sleep_ena : 1; + u32 ultaudio_ahbfabric_ixfabric_clk_sleep_ena : 1; + u32 reserved0 : 1; + u32 boot_rom_ahb_clk_sleep_ena : 1; + u32 reserved1 : 1; + u32 tlmm_ahb_clk_sleep_ena : 1; + u32 prng_ahb_clk_sleep_ena : 1; + u32 blsp1_ahb_clk_sleep_ena : 1; + u32 blsp1_sleep_clk_sleep_ena : 1; + u32 reserved2 : 1; + u32 mss_gpll0_div_clk_src_sleep_ena : 1; + u32 reserved3 : 3; + u32 cpuss_ahb_clk_sleep_ena : 1; + u32 cpuss_gnoc_clk_sleep_ena : 1; + u32 reserved4 : 1; + u32 imem_axi_clk_sleep_ena : 1; + u32 reserved5 : 7; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_apcs_clock_sleep_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_apcs_clock_sleep_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_apcs_clock_branch_ena_vote_1_s +{ + u32 pcie_slv_axi_clk_ena : 1; + u32 pcie_mstr_axi_clk_ena : 1; + u32 pcie_cfg_ahb_clk_ena : 1; + u32 pcie_aux_clk_ena : 1; + u32 pcie_pipe_clk_ena : 1; + u32 pcie_slv_q2a_axi_clk_ena : 1; + u32 pcie_sleep_clk_ena : 1; + u32 pcie_rchng_phy_clk_ena : 1; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_apcs_clock_branch_ena_vote_1_u +{ + struct ipa_gcc_hwio_def_gcc_apcs_clock_branch_ena_vote_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_apcs_clock_sleep_ena_vote_1_s +{ + u32 pcie_slv_axi_clk_sleep_ena : 1; + u32 pcie_mstr_axi_clk_sleep_ena : 1; + u32 pcie_cfg_ahb_clk_sleep_ena : 1; + u32 pcie_aux_clk_sleep_ena : 1; + u32 pcie_pipe_clk_sleep_ena : 1; + u32 pcie_slv_q2a_axi_clk_sleep_ena : 1; + u32 pcie_sleep_clk_sleep_ena : 1; + u32 pcie_rchng_phy_clk_sleep_ena : 1; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_apcs_clock_sleep_ena_vote_1_u +{ + struct ipa_gcc_hwio_def_gcc_apcs_clock_sleep_ena_vote_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_APCS_TZ_GPLL_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_apcs_tz_gpll_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2 : 1; + u32 gpll3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 gpll6 : 1; + u32 reserved0 : 25; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_apcs_tz_gpll_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_apcs_tz_gpll_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_APCS_TZ_GPLL_SLEEP_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_apcs_tz_gpll_sleep_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2 : 1; + u32 gpll3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 gpll6 : 1; + u32 reserved0 : 25; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_apcs_tz_gpll_sleep_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_apcs_tz_gpll_sleep_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_apcs_tz_clock_branch_ena_vote_s +{ + u32 sys_noc_cpuss_ahb_clk_ena : 1; + u32 tcsr_ahb_clk_ena : 1; + u32 qdss_cfg_ahb_clk_ena : 1; + u32 ce1_ahb_clk_ena : 1; + u32 ce1_axi_clk_ena : 1; + u32 ce1_clk_ena : 1; + u32 tlmm_clk_ena : 1; + u32 ultaudio_pcnoc_sway_clk_ena : 1; + u32 ultaudio_ahbfabric_ixfabric_clk_ena : 1; + u32 reserved0 : 1; + u32 boot_rom_ahb_clk_ena : 1; + u32 reserved1 : 1; + u32 tlmm_ahb_clk_ena : 1; + u32 prng_ahb_clk_ena : 1; + u32 blsp1_ahb_clk_ena : 1; + u32 blsp1_sleep_clk_ena : 1; + u32 reserved2 : 1; + u32 mss_gpll0_div_clk_src_ena : 1; + u32 reserved3 : 3; + u32 cpuss_ahb_clk_ena : 1; + u32 cpuss_gnoc_clk_ena : 1; + u32 reserved4 : 1; + u32 imem_axi_clk_ena : 1; + u32 reserved5 : 7; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_apcs_tz_clock_branch_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_apcs_tz_clock_branch_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_apcs_tz_clock_sleep_ena_vote_s +{ + u32 sys_noc_cpuss_ahb_clk_sleep_ena : 1; + u32 tcsr_ahb_clk_sleep_ena : 1; + u32 qdss_cfg_ahb_clk_sleep_ena : 1; + u32 ce1_ahb_clk_sleep_ena : 1; + u32 ce1_axi_clk_sleep_ena : 1; + u32 ce1_clk_sleep_ena : 1; + u32 tlmm_clk_sleep_ena : 1; + u32 ultaudio_pcnoc_sway_clk_sleep_ena : 1; + u32 ultaudio_ahbfabric_ixfabric_clk_sleep_ena : 1; + u32 reserved0 : 1; + u32 boot_rom_ahb_clk_sleep_ena : 1; + u32 reserved1 : 1; + u32 tlmm_ahb_clk_sleep_ena : 1; + u32 prng_ahb_clk_sleep_ena : 1; + u32 blsp1_ahb_clk_sleep_ena : 1; + u32 blsp1_sleep_clk_sleep_ena : 1; + u32 reserved2 : 1; + u32 mss_gpll0_div_clk_src_sleep_ena : 1; + u32 reserved3 : 3; + u32 cpuss_ahb_clk_sleep_ena : 1; + u32 cpuss_gnoc_clk_sleep_ena : 1; + u32 reserved4 : 1; + u32 imem_axi_clk_sleep_ena : 1; + u32 reserved5 : 7; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_apcs_tz_clock_sleep_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_apcs_tz_clock_sleep_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_apcs_tz_clock_branch_ena_vote_1_s +{ + u32 pcie_slv_axi_clk_ena : 1; + u32 pcie_mstr_axi_clk_ena : 1; + u32 pcie_cfg_ahb_clk_ena : 1; + u32 pcie_aux_clk_ena : 1; + u32 pcie_pipe_clk_ena : 1; + u32 pcie_slv_q2a_axi_clk_ena : 1; + u32 pcie_sleep_clk_ena : 1; + u32 pcie_rchng_phy_clk_ena : 1; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_apcs_tz_clock_branch_ena_vote_1_u +{ + struct ipa_gcc_hwio_def_gcc_apcs_tz_clock_branch_ena_vote_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_apcs_tz_clock_sleep_ena_vote_1_s +{ + u32 pcie_slv_axi_clk_sleep_ena : 1; + u32 pcie_mstr_axi_clk_sleep_ena : 1; + u32 pcie_cfg_ahb_clk_sleep_ena : 1; + u32 pcie_aux_clk_sleep_ena : 1; + u32 pcie_pipe_clk_sleep_ena : 1; + u32 pcie_slv_q2a_axi_clk_sleep_ena : 1; + u32 pcie_sleep_clk_sleep_ena : 1; + u32 pcie_rchng_phy_clk_sleep_ena : 1; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_apcs_tz_clock_sleep_ena_vote_1_u +{ + struct ipa_gcc_hwio_def_gcc_apcs_tz_clock_sleep_ena_vote_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HYP_GPLL_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hyp_gpll_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2 : 1; + u32 gpll3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 gpll6 : 1; + u32 reserved0 : 25; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hyp_gpll_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_hyp_gpll_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HYP_GPLL_SLEEP_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hyp_gpll_sleep_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2 : 1; + u32 gpll3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 gpll6 : 1; + u32 reserved0 : 25; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hyp_gpll_sleep_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_hyp_gpll_sleep_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HYP_CLOCK_BRANCH_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hyp_clock_branch_ena_vote_s +{ + u32 sys_noc_cpuss_ahb_clk_ena : 1; + u32 tcsr_ahb_clk_ena : 1; + u32 qdss_cfg_ahb_clk_ena : 1; + u32 ce1_ahb_clk_ena : 1; + u32 ce1_axi_clk_ena : 1; + u32 ce1_clk_ena : 1; + u32 tlmm_clk_ena : 1; + u32 ultaudio_pcnoc_sway_clk_ena : 1; + u32 ultaudio_ahbfabric_ixfabric_clk_ena : 1; + u32 reserved0 : 1; + u32 boot_rom_ahb_clk_ena : 1; + u32 reserved1 : 1; + u32 tlmm_ahb_clk_ena : 1; + u32 prng_ahb_clk_ena : 1; + u32 blsp1_ahb_clk_ena : 1; + u32 blsp1_sleep_clk_ena : 1; + u32 reserved2 : 1; + u32 mss_gpll0_div_clk_src_ena : 1; + u32 reserved3 : 3; + u32 cpuss_ahb_clk_ena : 1; + u32 cpuss_gnoc_clk_ena : 1; + u32 reserved4 : 1; + u32 imem_axi_clk_ena : 1; + u32 reserved5 : 7; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hyp_clock_branch_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_hyp_clock_branch_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HYP_CLOCK_SLEEP_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hyp_clock_sleep_ena_vote_s +{ + u32 sys_noc_cpuss_ahb_clk_sleep_ena : 1; + u32 tcsr_ahb_clk_sleep_ena : 1; + u32 qdss_cfg_ahb_clk_sleep_ena : 1; + u32 ce1_ahb_clk_sleep_ena : 1; + u32 ce1_axi_clk_sleep_ena : 1; + u32 ce1_clk_sleep_ena : 1; + u32 tlmm_clk_sleep_ena : 1; + u32 ultaudio_pcnoc_sway_clk_sleep_ena : 1; + u32 ultaudio_ahbfabric_ixfabric_clk_sleep_ena : 1; + u32 reserved0 : 1; + u32 boot_rom_ahb_clk_sleep_ena : 1; + u32 reserved1 : 1; + u32 tlmm_ahb_clk_sleep_ena : 1; + u32 prng_ahb_clk_sleep_ena : 1; + u32 blsp1_ahb_clk_sleep_ena : 1; + u32 blsp1_sleep_clk_sleep_ena : 1; + u32 reserved2 : 1; + u32 mss_gpll0_div_clk_src_sleep_ena : 1; + u32 reserved3 : 3; + u32 cpuss_ahb_clk_sleep_ena : 1; + u32 cpuss_gnoc_clk_sleep_ena : 1; + u32 reserved4 : 1; + u32 imem_axi_clk_sleep_ena : 1; + u32 reserved5 : 7; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hyp_clock_sleep_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_hyp_clock_sleep_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hyp_clock_branch_ena_vote_1_s +{ + u32 pcie_slv_axi_clk_ena : 1; + u32 pcie_mstr_axi_clk_ena : 1; + u32 pcie_cfg_ahb_clk_ena : 1; + u32 pcie_aux_clk_ena : 1; + u32 pcie_pipe_clk_ena : 1; + u32 pcie_slv_q2a_axi_clk_ena : 1; + u32 pcie_sleep_clk_ena : 1; + u32 pcie_rchng_phy_clk_ena : 1; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hyp_clock_branch_ena_vote_1_u +{ + struct ipa_gcc_hwio_def_gcc_hyp_clock_branch_ena_vote_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hyp_clock_sleep_ena_vote_1_s +{ + u32 pcie_slv_axi_clk_sleep_ena : 1; + u32 pcie_mstr_axi_clk_sleep_ena : 1; + u32 pcie_cfg_ahb_clk_sleep_ena : 1; + u32 pcie_aux_clk_sleep_ena : 1; + u32 pcie_pipe_clk_sleep_ena : 1; + u32 pcie_slv_q2a_axi_clk_sleep_ena : 1; + u32 pcie_sleep_clk_sleep_ena : 1; + u32 pcie_rchng_phy_clk_sleep_ena : 1; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hyp_clock_sleep_ena_vote_1_u +{ + struct ipa_gcc_hwio_def_gcc_hyp_clock_sleep_ena_vote_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPARE_GPLL_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spare_gpll_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2 : 1; + u32 gpll3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 gpll6 : 1; + u32 reserved0 : 25; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spare_gpll_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_spare_gpll_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPARE_GPLL_SLEEP_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spare_gpll_sleep_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2 : 1; + u32 gpll3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 gpll6 : 1; + u32 reserved0 : 25; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spare_gpll_sleep_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_spare_gpll_sleep_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPARE_CLOCK_BRANCH_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spare_clock_branch_ena_vote_s +{ + u32 sys_noc_cpuss_ahb_clk_ena : 1; + u32 tcsr_ahb_clk_ena : 1; + u32 qdss_cfg_ahb_clk_ena : 1; + u32 ce1_ahb_clk_ena : 1; + u32 ce1_axi_clk_ena : 1; + u32 ce1_clk_ena : 1; + u32 tlmm_clk_ena : 1; + u32 ultaudio_pcnoc_sway_clk_ena : 1; + u32 ultaudio_ahbfabric_ixfabric_clk_ena : 1; + u32 reserved0 : 1; + u32 boot_rom_ahb_clk_ena : 1; + u32 reserved1 : 1; + u32 tlmm_ahb_clk_ena : 1; + u32 prng_ahb_clk_ena : 1; + u32 blsp1_ahb_clk_ena : 1; + u32 blsp1_sleep_clk_ena : 1; + u32 reserved2 : 1; + u32 mss_gpll0_div_clk_src_ena : 1; + u32 reserved3 : 3; + u32 cpuss_ahb_clk_ena : 1; + u32 cpuss_gnoc_clk_ena : 1; + u32 reserved4 : 1; + u32 imem_axi_clk_ena : 1; + u32 reserved5 : 7; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spare_clock_branch_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_spare_clock_branch_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPARE_CLOCK_SLEEP_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spare_clock_sleep_ena_vote_s +{ + u32 sys_noc_cpuss_ahb_clk_sleep_ena : 1; + u32 tcsr_ahb_clk_sleep_ena : 1; + u32 qdss_cfg_ahb_clk_sleep_ena : 1; + u32 ce1_ahb_clk_sleep_ena : 1; + u32 ce1_axi_clk_sleep_ena : 1; + u32 ce1_clk_sleep_ena : 1; + u32 tlmm_clk_sleep_ena : 1; + u32 ultaudio_pcnoc_sway_clk_sleep_ena : 1; + u32 ultaudio_ahbfabric_ixfabric_clk_sleep_ena : 1; + u32 reserved0 : 1; + u32 boot_rom_ahb_clk_sleep_ena : 1; + u32 reserved1 : 1; + u32 tlmm_ahb_clk_sleep_ena : 1; + u32 prng_ahb_clk_sleep_ena : 1; + u32 blsp1_ahb_clk_sleep_ena : 1; + u32 blsp1_sleep_clk_sleep_ena : 1; + u32 reserved2 : 1; + u32 mss_gpll0_div_clk_src_sleep_ena : 1; + u32 reserved3 : 3; + u32 cpuss_ahb_clk_sleep_ena : 1; + u32 cpuss_gnoc_clk_sleep_ena : 1; + u32 reserved4 : 1; + u32 imem_axi_clk_sleep_ena : 1; + u32 reserved5 : 7; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spare_clock_sleep_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_spare_clock_sleep_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spare_clock_branch_ena_vote_1_s +{ + u32 pcie_slv_axi_clk_ena : 1; + u32 pcie_mstr_axi_clk_ena : 1; + u32 pcie_cfg_ahb_clk_ena : 1; + u32 pcie_aux_clk_ena : 1; + u32 pcie_pipe_clk_ena : 1; + u32 pcie_slv_q2a_axi_clk_ena : 1; + u32 pcie_sleep_clk_ena : 1; + u32 pcie_rchng_phy_clk_ena : 1; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spare_clock_branch_ena_vote_1_u +{ + struct ipa_gcc_hwio_def_gcc_spare_clock_branch_ena_vote_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spare_clock_sleep_ena_vote_1_s +{ + u32 pcie_slv_axi_clk_sleep_ena : 1; + u32 pcie_mstr_axi_clk_sleep_ena : 1; + u32 pcie_cfg_ahb_clk_sleep_ena : 1; + u32 pcie_aux_clk_sleep_ena : 1; + u32 pcie_pipe_clk_sleep_ena : 1; + u32 pcie_slv_q2a_axi_clk_sleep_ena : 1; + u32 pcie_sleep_clk_sleep_ena : 1; + u32 pcie_rchng_phy_clk_sleep_ena : 1; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spare_clock_sleep_ena_vote_1_u +{ + struct ipa_gcc_hwio_def_gcc_spare_clock_sleep_ena_vote_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPARE1_GPLL_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spare1_gpll_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2 : 1; + u32 gpll3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 gpll6 : 1; + u32 reserved0 : 25; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spare1_gpll_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_spare1_gpll_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPARE1_GPLL_SLEEP_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spare1_gpll_sleep_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2 : 1; + u32 gpll3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 gpll6 : 1; + u32 reserved0 : 25; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spare1_gpll_sleep_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_spare1_gpll_sleep_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spare1_clock_branch_ena_vote_s +{ + u32 sys_noc_cpuss_ahb_clk_ena : 1; + u32 tcsr_ahb_clk_ena : 1; + u32 qdss_cfg_ahb_clk_ena : 1; + u32 ce1_ahb_clk_ena : 1; + u32 ce1_axi_clk_ena : 1; + u32 ce1_clk_ena : 1; + u32 tlmm_clk_ena : 1; + u32 ultaudio_pcnoc_sway_clk_ena : 1; + u32 ultaudio_ahbfabric_ixfabric_clk_ena : 1; + u32 reserved0 : 1; + u32 boot_rom_ahb_clk_ena : 1; + u32 reserved1 : 1; + u32 tlmm_ahb_clk_ena : 1; + u32 prng_ahb_clk_ena : 1; + u32 blsp1_ahb_clk_ena : 1; + u32 blsp1_sleep_clk_ena : 1; + u32 reserved2 : 1; + u32 mss_gpll0_div_clk_src_ena : 1; + u32 reserved3 : 3; + u32 cpuss_ahb_clk_ena : 1; + u32 cpuss_gnoc_clk_ena : 1; + u32 reserved4 : 1; + u32 imem_axi_clk_ena : 1; + u32 reserved5 : 7; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spare1_clock_branch_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_spare1_clock_branch_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spare1_clock_sleep_ena_vote_s +{ + u32 sys_noc_cpuss_ahb_clk_sleep_ena : 1; + u32 tcsr_ahb_clk_sleep_ena : 1; + u32 qdss_cfg_ahb_clk_sleep_ena : 1; + u32 ce1_ahb_clk_sleep_ena : 1; + u32 ce1_axi_clk_sleep_ena : 1; + u32 ce1_clk_sleep_ena : 1; + u32 tlmm_clk_sleep_ena : 1; + u32 ultaudio_pcnoc_sway_clk_sleep_ena : 1; + u32 ultaudio_ahbfabric_ixfabric_clk_sleep_ena : 1; + u32 reserved0 : 1; + u32 boot_rom_ahb_clk_sleep_ena : 1; + u32 reserved1 : 1; + u32 tlmm_ahb_clk_sleep_ena : 1; + u32 prng_ahb_clk_sleep_ena : 1; + u32 blsp1_ahb_clk_sleep_ena : 1; + u32 blsp1_sleep_clk_sleep_ena : 1; + u32 reserved2 : 1; + u32 mss_gpll0_div_clk_src_sleep_ena : 1; + u32 reserved3 : 3; + u32 cpuss_ahb_clk_sleep_ena : 1; + u32 cpuss_gnoc_clk_sleep_ena : 1; + u32 reserved4 : 1; + u32 imem_axi_clk_sleep_ena : 1; + u32 reserved5 : 7; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spare1_clock_sleep_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_spare1_clock_sleep_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spare1_clock_branch_ena_vote_1_s +{ + u32 pcie_slv_axi_clk_ena : 1; + u32 pcie_mstr_axi_clk_ena : 1; + u32 pcie_cfg_ahb_clk_ena : 1; + u32 pcie_aux_clk_ena : 1; + u32 pcie_pipe_clk_ena : 1; + u32 pcie_slv_q2a_axi_clk_ena : 1; + u32 pcie_sleep_clk_ena : 1; + u32 pcie_rchng_phy_clk_ena : 1; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spare1_clock_branch_ena_vote_1_u +{ + struct ipa_gcc_hwio_def_gcc_spare1_clock_branch_ena_vote_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spare1_clock_sleep_ena_vote_1_s +{ + u32 pcie_slv_axi_clk_sleep_ena : 1; + u32 pcie_mstr_axi_clk_sleep_ena : 1; + u32 pcie_cfg_ahb_clk_sleep_ena : 1; + u32 pcie_aux_clk_sleep_ena : 1; + u32 pcie_pipe_clk_sleep_ena : 1; + u32 pcie_slv_q2a_axi_clk_sleep_ena : 1; + u32 pcie_sleep_clk_sleep_ena : 1; + u32 pcie_rchng_phy_clk_sleep_ena : 1; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spare1_clock_sleep_ena_vote_1_u +{ + struct ipa_gcc_hwio_def_gcc_spare1_clock_sleep_ena_vote_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPARE2_GPLL_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spare2_gpll_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2 : 1; + u32 gpll3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 gpll6 : 1; + u32 reserved0 : 25; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spare2_gpll_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_spare2_gpll_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPARE2_GPLL_SLEEP_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spare2_gpll_sleep_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2 : 1; + u32 gpll3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 gpll6 : 1; + u32 reserved0 : 25; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spare2_gpll_sleep_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_spare2_gpll_sleep_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spare2_clock_branch_ena_vote_s +{ + u32 sys_noc_cpuss_ahb_clk_ena : 1; + u32 tcsr_ahb_clk_ena : 1; + u32 qdss_cfg_ahb_clk_ena : 1; + u32 ce1_ahb_clk_ena : 1; + u32 ce1_axi_clk_ena : 1; + u32 ce1_clk_ena : 1; + u32 tlmm_clk_ena : 1; + u32 ultaudio_pcnoc_sway_clk_ena : 1; + u32 ultaudio_ahbfabric_ixfabric_clk_ena : 1; + u32 reserved0 : 1; + u32 boot_rom_ahb_clk_ena : 1; + u32 reserved1 : 1; + u32 tlmm_ahb_clk_ena : 1; + u32 prng_ahb_clk_ena : 1; + u32 blsp1_ahb_clk_ena : 1; + u32 blsp1_sleep_clk_ena : 1; + u32 reserved2 : 1; + u32 mss_gpll0_div_clk_src_ena : 1; + u32 reserved3 : 3; + u32 cpuss_ahb_clk_ena : 1; + u32 cpuss_gnoc_clk_ena : 1; + u32 reserved4 : 1; + u32 imem_axi_clk_ena : 1; + u32 reserved5 : 7; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spare2_clock_branch_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_spare2_clock_branch_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spare2_clock_sleep_ena_vote_s +{ + u32 sys_noc_cpuss_ahb_clk_sleep_ena : 1; + u32 tcsr_ahb_clk_sleep_ena : 1; + u32 qdss_cfg_ahb_clk_sleep_ena : 1; + u32 ce1_ahb_clk_sleep_ena : 1; + u32 ce1_axi_clk_sleep_ena : 1; + u32 ce1_clk_sleep_ena : 1; + u32 tlmm_clk_sleep_ena : 1; + u32 ultaudio_pcnoc_sway_clk_sleep_ena : 1; + u32 ultaudio_ahbfabric_ixfabric_clk_sleep_ena : 1; + u32 reserved0 : 1; + u32 boot_rom_ahb_clk_sleep_ena : 1; + u32 reserved1 : 1; + u32 tlmm_ahb_clk_sleep_ena : 1; + u32 prng_ahb_clk_sleep_ena : 1; + u32 blsp1_ahb_clk_sleep_ena : 1; + u32 blsp1_sleep_clk_sleep_ena : 1; + u32 reserved2 : 1; + u32 mss_gpll0_div_clk_src_sleep_ena : 1; + u32 reserved3 : 3; + u32 cpuss_ahb_clk_sleep_ena : 1; + u32 cpuss_gnoc_clk_sleep_ena : 1; + u32 reserved4 : 1; + u32 imem_axi_clk_sleep_ena : 1; + u32 reserved5 : 7; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spare2_clock_sleep_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_spare2_clock_sleep_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spare2_clock_branch_ena_vote_1_s +{ + u32 pcie_slv_axi_clk_ena : 1; + u32 pcie_mstr_axi_clk_ena : 1; + u32 pcie_cfg_ahb_clk_ena : 1; + u32 pcie_aux_clk_ena : 1; + u32 pcie_pipe_clk_ena : 1; + u32 pcie_slv_q2a_axi_clk_ena : 1; + u32 pcie_sleep_clk_ena : 1; + u32 pcie_rchng_phy_clk_ena : 1; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spare2_clock_branch_ena_vote_1_u +{ + struct ipa_gcc_hwio_def_gcc_spare2_clock_branch_ena_vote_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spare2_clock_sleep_ena_vote_1_s +{ + u32 pcie_slv_axi_clk_sleep_ena : 1; + u32 pcie_mstr_axi_clk_sleep_ena : 1; + u32 pcie_cfg_ahb_clk_sleep_ena : 1; + u32 pcie_aux_clk_sleep_ena : 1; + u32 pcie_pipe_clk_sleep_ena : 1; + u32 pcie_slv_q2a_axi_clk_sleep_ena : 1; + u32 pcie_sleep_clk_sleep_ena : 1; + u32 pcie_rchng_phy_clk_sleep_ena : 1; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spare2_clock_sleep_ena_vote_1_u +{ + struct ipa_gcc_hwio_def_gcc_spare2_clock_sleep_ena_vote_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_Q6_GPLL_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_q6_gpll_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2 : 1; + u32 gpll3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 gpll6 : 1; + u32 reserved0 : 25; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_q6_gpll_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_mss_q6_gpll_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_Q6_GPLL_SLEEP_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_q6_gpll_sleep_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2 : 1; + u32 gpll3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 gpll6 : 1; + u32 reserved0 : 25; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_q6_gpll_sleep_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_mss_q6_gpll_sleep_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_q6_clock_branch_ena_vote_s +{ + u32 sys_noc_cpuss_ahb_clk_ena : 1; + u32 tcsr_ahb_clk_ena : 1; + u32 qdss_cfg_ahb_clk_ena : 1; + u32 ce1_ahb_clk_ena : 1; + u32 ce1_axi_clk_ena : 1; + u32 ce1_clk_ena : 1; + u32 tlmm_clk_ena : 1; + u32 ultaudio_pcnoc_sway_clk_ena : 1; + u32 ultaudio_ahbfabric_ixfabric_clk_ena : 1; + u32 reserved0 : 1; + u32 boot_rom_ahb_clk_ena : 1; + u32 reserved1 : 1; + u32 tlmm_ahb_clk_ena : 1; + u32 prng_ahb_clk_ena : 1; + u32 blsp1_ahb_clk_ena : 1; + u32 blsp1_sleep_clk_ena : 1; + u32 reserved2 : 1; + u32 mss_gpll0_div_clk_src_ena : 1; + u32 reserved3 : 3; + u32 cpuss_ahb_clk_ena : 1; + u32 cpuss_gnoc_clk_ena : 1; + u32 reserved4 : 1; + u32 imem_axi_clk_ena : 1; + u32 reserved5 : 7; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_q6_clock_branch_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_mss_q6_clock_branch_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_q6_clock_sleep_ena_vote_s +{ + u32 sys_noc_cpuss_ahb_clk_sleep_ena : 1; + u32 tcsr_ahb_clk_sleep_ena : 1; + u32 qdss_cfg_ahb_clk_sleep_ena : 1; + u32 ce1_ahb_clk_sleep_ena : 1; + u32 ce1_axi_clk_sleep_ena : 1; + u32 ce1_clk_sleep_ena : 1; + u32 tlmm_clk_sleep_ena : 1; + u32 ultaudio_pcnoc_sway_clk_sleep_ena : 1; + u32 ultaudio_ahbfabric_ixfabric_clk_sleep_ena : 1; + u32 reserved0 : 1; + u32 boot_rom_ahb_clk_sleep_ena : 1; + u32 reserved1 : 1; + u32 tlmm_ahb_clk_sleep_ena : 1; + u32 prng_ahb_clk_sleep_ena : 1; + u32 blsp1_ahb_clk_sleep_ena : 1; + u32 blsp1_sleep_clk_sleep_ena : 1; + u32 reserved2 : 1; + u32 mss_gpll0_div_clk_src_sleep_ena : 1; + u32 reserved3 : 3; + u32 cpuss_ahb_clk_sleep_ena : 1; + u32 cpuss_gnoc_clk_sleep_ena : 1; + u32 reserved4 : 1; + u32 imem_axi_clk_sleep_ena : 1; + u32 reserved5 : 7; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_q6_clock_sleep_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_mss_q6_clock_sleep_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_q6_clock_branch_ena_vote_1_s +{ + u32 pcie_slv_axi_clk_ena : 1; + u32 pcie_mstr_axi_clk_ena : 1; + u32 pcie_cfg_ahb_clk_ena : 1; + u32 pcie_aux_clk_ena : 1; + u32 pcie_pipe_clk_ena : 1; + u32 pcie_slv_q2a_axi_clk_ena : 1; + u32 pcie_sleep_clk_ena : 1; + u32 pcie_rchng_phy_clk_ena : 1; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_q6_clock_branch_ena_vote_1_u +{ + struct ipa_gcc_hwio_def_gcc_mss_q6_clock_branch_ena_vote_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_q6_clock_sleep_ena_vote_1_s +{ + u32 pcie_slv_axi_clk_sleep_ena : 1; + u32 pcie_mstr_axi_clk_sleep_ena : 1; + u32 pcie_cfg_ahb_clk_sleep_ena : 1; + u32 pcie_aux_clk_sleep_ena : 1; + u32 pcie_pipe_clk_sleep_ena : 1; + u32 pcie_slv_q2a_axi_clk_sleep_ena : 1; + u32 pcie_sleep_clk_sleep_ena : 1; + u32 pcie_rchng_phy_clk_sleep_ena : 1; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_q6_clock_sleep_ena_vote_1_u +{ + struct ipa_gcc_hwio_def_gcc_mss_q6_clock_sleep_ena_vote_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_MISC_RESET +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_misc_reset_s +{ + u32 pcie_slv_axi_bcr_blk_ares : 1; + u32 pcie_mstr_axi_bcr_blk_ares : 1; + u32 pcie_cfg_ahb_bcr_blk_ares : 1; + u32 pcie_aux_bcr_blk_ares : 1; + u32 pcie_pipe_bcr_blk_ares : 1; + u32 pcie_mstr_axi_sticky_bcr_blk_ares : 1; + u32 pcie_core_sticky_bcr_blk_ares : 1; + u32 pcie_slv_axi_sticky_bcr_blk_ares : 1; + u32 pcie_sleep_bcr_blk_ares : 1; + u32 pcie_slv_axi_q2a_bcr_blk_ares : 1; + u32 pcie_rchng_phy_bcr_blk_ares : 1; + u32 pcie_cfg_ahb_bridge2mx_bcr_blk_ares : 1; + u32 pcie_mstr_axi_bridge2mx_bcr_blk_ares : 1; + u32 pcie_slv_axi_q2a_bridge2mx_bcr_blk_ares : 1; + u32 reserved0 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_misc_reset_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_misc_reset_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DEBUG_CLK_CTL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_debug_clk_ctl_s +{ + u32 mux_sel : 10; + u32 plltest_de_sel : 1; + u32 reserved0 : 3; + u32 pll_lock_det_mux_sel : 5; + u32 debug_bus_sel : 4; + u32 reserved1 : 9; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_debug_clk_ctl_u +{ + struct ipa_gcc_hwio_def_gcc_debug_clk_ctl_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CLOCK_FRQ_MEASURE_CTL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_clock_frq_measure_ctl_s +{ + u32 xo_div4_term_cnt : 20; + u32 cnt_en : 1; + u32 clr_cnt : 1; + u32 reserved0 : 10; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_clock_frq_measure_ctl_u +{ + struct ipa_gcc_hwio_def_gcc_clock_frq_measure_ctl_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CLOCK_FRQ_MEASURE_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_clock_frq_measure_status_s +{ + u32 measure_cnt : 25; + u32 xo_div4_cnt_done : 1; + u32 reserved0 : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_clock_frq_measure_status_u +{ + struct ipa_gcc_hwio_def_gcc_clock_frq_measure_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PLLTEST_PAD_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_plltest_pad_cfg_s +{ + u32 out_sel : 5; + u32 reserve_bits10_5 : 6; + u32 hdrive : 3; + u32 hihys_en : 1; + u32 core_ie : 1; + u32 reserve_bit16 : 1; + u32 core_oe : 1; + u32 reserve_bit18 : 1; + u32 core_pll_en : 1; + u32 reserve_bits23_20 : 4; + u32 core_pll_b : 2; + u32 reserved0 : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_plltest_pad_cfg_u +{ + struct ipa_gcc_hwio_def_gcc_plltest_pad_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_INTERFACE_FSM +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_interface_fsm_s +{ + u32 fsm_state : 5; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_interface_fsm_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_interface_fsm_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_INTERFACE_FSM +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_interface_fsm_s +{ + u32 fsm_state : 5; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_interface_fsm_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_interface_fsm_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_INTERFACE_FSM +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_interface_fsm_s +{ + u32 fsm_state : 5; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_interface_fsm_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_interface_fsm_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_INTERFACE_FSM +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_interface_fsm_s +{ + u32 fsm_state : 5; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_interface_fsm_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_interface_fsm_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_INTERFACE_FSM +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_interface_fsm_s +{ + u32 fsm_state : 5; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_interface_fsm_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_interface_fsm_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_INTERFACE_FSM +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_interface_fsm_s +{ + u32 fsm_state : 5; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_interface_fsm_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_interface_fsm_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_INTERFACE_FSM +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_interface_fsm_s +{ + u32 fsm_state : 5; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_interface_fsm_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_interface_fsm_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PKA_INTERFACE_FSM +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pka_interface_fsm_s +{ + u32 fsm_state : 5; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pka_interface_fsm_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pka_interface_fsm_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_INTERFACE_FSM +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_interface_fsm_s +{ + u32 fsm_state : 5; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_interface_fsm_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_interface_fsm_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB_BOOT_CLOCK_CTL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb_boot_clock_ctl_s +{ + u32 clk_enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb_boot_clock_ctl_u +{ + struct ipa_gcc_hwio_def_gcc_usb_boot_clock_ctl_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_BOOT_CLOCK_CTL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_boot_clock_ctl_s +{ + u32 clk_enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_boot_clock_ctl_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_boot_clock_ctl_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TIC_MODE_APCS_BOOT +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tic_mode_apcs_boot_s +{ + u32 apcs_boot_in_tic_mode : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tic_mode_apcs_boot_u +{ + struct ipa_gcc_hwio_def_gcc_tic_mode_apcs_boot_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_IPA_GDSC_OVRD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ipa_gdsc_ovrd_s +{ + u32 retain_ff_enable : 1; + u32 sw_override : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ipa_gdsc_ovrd_u +{ + struct ipa_gcc_hwio_def_gcc_ipa_gdsc_ovrd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB30_PRIM_GDSC_OVRD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb30_prim_gdsc_ovrd_s +{ + u32 retain_ff_enable : 1; + u32 sw_override : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb30_prim_gdsc_ovrd_u +{ + struct ipa_gcc_hwio_def_gcc_usb30_prim_gdsc_ovrd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_0_GDSC_OVRD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_0_gdsc_ovrd_s +{ + u32 retain_ff_enable : 1; + u32 sw_override : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_0_gdsc_ovrd_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_0_gdsc_ovrd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DDRSS_GDSC_OVRD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ddrss_gdsc_ovrd_s +{ + u32 retain_ff_enable : 1; + u32 sw_override : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ddrss_gdsc_ovrd_u +{ + struct ipa_gcc_hwio_def_gcc_ddrss_gdsc_ovrd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GDS_HW_CTRL_SPARE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gds_hw_ctrl_spare_s +{ + u32 spare : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gds_hw_ctrl_spare_u +{ + struct ipa_gcc_hwio_def_gcc_gds_hw_ctrl_spare_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ARC_CLK_DIS_ACK_OVRD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_arc_clk_dis_ack_ovrd_s +{ + u32 gcc_mx_clk_dis_ack_ovrd : 1; + u32 nav_mx_clk_dis_ack_ovrd : 1; + u32 apss_mx_clk_dis_ack_ovrd : 1; + u32 mss_mx_clk_dis_ack_ovrd : 1; + u32 ddr_phy_mx_clk_dis_ack_ovrd : 1; + u32 reserved0 : 11; + u32 gcc_cx_clk_dis_ack_ovrd : 1; + u32 nav_cx_clk_dis_ack_ovrd : 1; + u32 apss_cx_clk_dis_ack_ovrd : 1; + u32 mss_cx_clk_dis_ack_ovrd : 1; + u32 ddr_phy_cx_clk_dis_ack_ovrd : 1; + u32 reserved1 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_arc_clk_dis_ack_ovrd_u +{ + struct ipa_gcc_hwio_def_gcc_arc_clk_dis_ack_ovrd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPARE0_REG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spare0_reg_s +{ + u32 spare_bits : 32; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spare0_reg_u +{ + struct ipa_gcc_hwio_def_gcc_spare0_reg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPARE1_REG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spare1_reg_s +{ + u32 spare_bits : 32; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spare1_reg_u +{ + struct ipa_gcc_hwio_def_gcc_spare1_reg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPARE2_REG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spare2_reg_s +{ + u32 spare_bits : 32; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spare2_reg_u +{ + struct ipa_gcc_hwio_def_gcc_spare2_reg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPARE3_REG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spare3_reg_s +{ + u32 spare_bits : 32; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spare3_reg_u +{ + struct ipa_gcc_hwio_def_gcc_spare3_reg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RAW_SLEEP_CLK_CTRL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_raw_sleep_clk_ctrl_s +{ + u32 gating_disable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_raw_sleep_clk_ctrl_u +{ + struct ipa_gcc_hwio_def_gcc_raw_sleep_clk_ctrl_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tz_vote_aggre_noc_mmu_tbu1_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tz_vote_aggre_noc_mmu_tbu1_clk_u +{ + struct ipa_gcc_hwio_def_gcc_tz_vote_aggre_noc_mmu_tbu1_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tz_vote_aggre_noc_mmu_tbu2_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tz_vote_aggre_noc_mmu_tbu2_clk_u +{ + struct ipa_gcc_hwio_def_gcc_tz_vote_aggre_noc_mmu_tbu2_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TZ_VOTE_ALL_SMMU_MMU_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tz_vote_all_smmu_mmu_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tz_vote_all_smmu_mmu_clk_u +{ + struct ipa_gcc_hwio_def_gcc_tz_vote_all_smmu_mmu_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TZ_VOTE_MMU_TCU_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tz_vote_mmu_tcu_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tz_vote_mmu_tcu_clk_u +{ + struct ipa_gcc_hwio_def_gcc_tz_vote_mmu_tcu_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hyp_vote_aggre_noc_mmu_tbu1_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hyp_vote_aggre_noc_mmu_tbu1_clk_u +{ + struct ipa_gcc_hwio_def_gcc_hyp_vote_aggre_noc_mmu_tbu1_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hyp_vote_aggre_noc_mmu_tbu2_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hyp_vote_aggre_noc_mmu_tbu2_clk_u +{ + struct ipa_gcc_hwio_def_gcc_hyp_vote_aggre_noc_mmu_tbu2_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HYP_VOTE_ALL_SMMU_MMU_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hyp_vote_all_smmu_mmu_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hyp_vote_all_smmu_mmu_clk_u +{ + struct ipa_gcc_hwio_def_gcc_hyp_vote_all_smmu_mmu_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HYP_VOTE_MMU_TCU_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hyp_vote_mmu_tcu_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hyp_vote_mmu_tcu_clk_u +{ + struct ipa_gcc_hwio_def_gcc_hyp_vote_mmu_tcu_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hlos1_vote_aggre_noc_mmu_tbu1_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hlos1_vote_aggre_noc_mmu_tbu1_clk_u +{ + struct ipa_gcc_hwio_def_gcc_hlos1_vote_aggre_noc_mmu_tbu1_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hlos1_vote_aggre_noc_mmu_tbu2_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hlos1_vote_aggre_noc_mmu_tbu2_clk_u +{ + struct ipa_gcc_hwio_def_gcc_hlos1_vote_aggre_noc_mmu_tbu2_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hlos1_vote_all_smmu_mmu_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hlos1_vote_all_smmu_mmu_clk_u +{ + struct ipa_gcc_hwio_def_gcc_hlos1_vote_all_smmu_mmu_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HLOS1_VOTE_MMU_TCU_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hlos1_vote_mmu_tcu_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hlos1_vote_mmu_tcu_clk_u +{ + struct ipa_gcc_hwio_def_gcc_hlos1_vote_mmu_tcu_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hlos2_vote_aggre_noc_mmu_tbu1_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hlos2_vote_aggre_noc_mmu_tbu1_clk_u +{ + struct ipa_gcc_hwio_def_gcc_hlos2_vote_aggre_noc_mmu_tbu1_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hlos2_vote_aggre_noc_mmu_tbu2_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hlos2_vote_aggre_noc_mmu_tbu2_clk_u +{ + struct ipa_gcc_hwio_def_gcc_hlos2_vote_aggre_noc_mmu_tbu2_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hlos2_vote_all_smmu_mmu_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hlos2_vote_all_smmu_mmu_clk_u +{ + struct ipa_gcc_hwio_def_gcc_hlos2_vote_all_smmu_mmu_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HLOS2_VOTE_MMU_TCU_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hlos2_vote_mmu_tcu_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hlos2_vote_mmu_tcu_clk_u +{ + struct ipa_gcc_hwio_def_gcc_hlos2_vote_mmu_tcu_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB3_PRIM_CLKREF_EN +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb3_prim_clkref_en_s +{ + u32 usb3_enable : 1; + u32 reserved0 : 30; + u32 usb3_status : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb3_prim_clkref_en_u +{ + struct ipa_gcc_hwio_def_gcc_usb3_prim_clkref_en_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_0_CLKREF_EN +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_0_clkref_en_s +{ + u32 pcie_enable : 1; + u32 reserved0 : 30; + u32 pcie_status : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_0_clkref_en_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_0_clkref_en_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RX1_USB2_CLKREF_EN +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rx1_usb2_clkref_en_s +{ + u32 rx1_usb2_enable : 1; + u32 cref_enable : 1; + u32 reserved0 : 29; + u32 rx1_usb2_status : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rx1_usb2_clkref_en_u +{ + struct ipa_gcc_hwio_def_gcc_rx1_usb2_clkref_en_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RX2_QLINK_CLKREF_EN +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rx2_qlink_clkref_en_s +{ + u32 rx2_qlink_enable : 1; + u32 rxtap0_enable : 1; + u32 reserved0 : 29; + u32 rx2_qlink_status : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rx2_qlink_clkref_en_u +{ + struct ipa_gcc_hwio_def_gcc_rx2_qlink_clkref_en_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RX3_MODEM_CLKREF_EN +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rx3_modem_clkref_en_s +{ + u32 rx3_modem_enable : 1; + u32 rxtap1_enable : 1; + u32 reserved0 : 29; + u32 rx3_modem_status : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rx3_modem_clkref_en_u +{ + struct ipa_gcc_hwio_def_gcc_rx3_modem_clkref_en_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CXO_TX1_CLKREF_EN1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cxo_tx1_clkref_en1_s +{ + u32 cxo_tx1_enable : 1; + u32 reserved0 : 30; + u32 cxo_tx1_status : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cxo_tx1_clkref_en1_u +{ + struct ipa_gcc_hwio_def_gcc_cxo_tx1_clkref_en1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CLKREF_SPARE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_clkref_spare_s +{ + u32 spare : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_clkref_spare_u +{ + struct ipa_gcc_hwio_def_gcc_clkref_spare_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CXO_REFGEN_BIAS_SEL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cxo_refgen_bias_sel_s +{ + u32 sel_refgen : 1; + u32 reserved0 : 30; + u32 sel_refgen_status : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cxo_refgen_bias_sel_u +{ + struct ipa_gcc_hwio_def_gcc_cxo_refgen_bias_sel_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_vote_aggre_noc_mmu_tbu1_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_vote_aggre_noc_mmu_tbu1_clk_u +{ + struct ipa_gcc_hwio_def_gcc_mss_vote_aggre_noc_mmu_tbu1_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_vote_aggre_noc_mmu_tbu2_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_vote_aggre_noc_mmu_tbu2_clk_u +{ + struct ipa_gcc_hwio_def_gcc_mss_vote_aggre_noc_mmu_tbu2_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_VOTE_ALL_SMMU_MMU_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_vote_all_smmu_mmu_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_vote_all_smmu_mmu_clk_u +{ + struct ipa_gcc_hwio_def_gcc_mss_vote_all_smmu_mmu_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_VOTE_MMU_TCU_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_vote_mmu_tcu_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_vote_mmu_tcu_clk_u +{ + struct ipa_gcc_hwio_def_gcc_mss_vote_mmu_tcu_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPM_VOTE_QDSS_APB_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpm_vote_qdss_apb_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpm_vote_qdss_apb_clk_u +{ + struct ipa_gcc_hwio_def_gcc_rpm_vote_qdss_apb_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_Q6_VOTE_QDSS_APB_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_q6_vote_qdss_apb_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_q6_vote_qdss_apb_clk_u +{ + struct ipa_gcc_hwio_def_gcc_mss_q6_vote_qdss_apb_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_APCS_VOTE_QDSS_APB_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_apcs_vote_qdss_apb_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_apcs_vote_qdss_apb_clk_u +{ + struct ipa_gcc_hwio_def_gcc_apcs_vote_qdss_apb_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_APCS_TZ_VOTE_QDSS_APB_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_apcs_tz_vote_qdss_apb_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_apcs_tz_vote_qdss_apb_clk_u +{ + struct ipa_gcc_hwio_def_gcc_apcs_tz_vote_qdss_apb_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HYP_VOTE_QDSS_APB_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hyp_vote_qdss_apb_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hyp_vote_qdss_apb_clk_u +{ + struct ipa_gcc_hwio_def_gcc_hyp_vote_qdss_apb_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPARE1_VOTE_QDSS_APB_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spare1_vote_qdss_apb_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spare1_vote_qdss_apb_clk_u +{ + struct ipa_gcc_hwio_def_gcc_spare1_vote_qdss_apb_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPARE2_VOTE_QDSS_APB_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spare2_vote_qdss_apb_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spare2_vote_qdss_apb_clk_u +{ + struct ipa_gcc_hwio_def_gcc_spare2_vote_qdss_apb_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_JBIST_MODE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_jbist_mode_s +{ + u32 sleep_n : 1; + u32 reset_n : 1; + u32 jbist_test : 1; + u32 start_meas : 1; + u32 reserve_bits31_4 : 28; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_jbist_mode_u +{ + struct ipa_gcc_hwio_def_gcc_jbist_mode_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_JBIST_CONFIG_CTL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_jbist_config_ctl_s +{ + u32 jbist_config_ctl : 32; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_jbist_config_ctl_u +{ + struct ipa_gcc_hwio_def_gcc_jbist_config_ctl_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_JBIST_USER_CTL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_jbist_user_ctl_s +{ + u32 jbist_user_ctl : 32; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_jbist_user_ctl_u +{ + struct ipa_gcc_hwio_def_gcc_jbist_user_ctl_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_JBIST_USER_CTL_U +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_jbist_user_ctl_u_s +{ + u32 jbist_user_ctl_u : 32; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_jbist_user_ctl_u_u +{ + struct ipa_gcc_hwio_def_gcc_jbist_user_ctl_u_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_JBIST_TEST_CTL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_jbist_test_ctl_s +{ + u32 jbist_test_ctl : 32; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_jbist_test_ctl_u +{ + struct ipa_gcc_hwio_def_gcc_jbist_test_ctl_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_JBIST_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_jbist_status_s +{ + u32 jbist_status : 32; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_jbist_status_u +{ + struct ipa_gcc_hwio_def_gcc_jbist_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_JBIST_MEAS_DONE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_jbist_meas_done_s +{ + u32 jbist_data_stream_rdy : 1; + u32 reserve_bits31_1 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_jbist_meas_done_u +{ + struct ipa_gcc_hwio_def_gcc_jbist_meas_done_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_JBIST_MISC +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_jbist_misc_s +{ + u32 clk_ext_sel : 2; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_jbist_misc_u +{ + struct ipa_gcc_hwio_def_gcc_jbist_misc_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GLOBAL_EN +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_global_en_s +{ + u32 east_enable : 1; + u32 west_enable : 1; + u32 north_enable : 1; + u32 south_enable : 1; + u32 center_enable : 1; + u32 peripherals_enable : 1; + u32 rest_enable : 1; + u32 mem_enable_0 : 1; + u32 mem_enable_1 : 1; + u32 mem_enable_2 : 1; + u32 mem_enable_3 : 1; + u32 mem_enable_4 : 1; + u32 mem_enable_5 : 1; + u32 mem_enable_6 : 1; + u32 mem_enable_7 : 1; + u32 spare_enable : 17; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_global_en_u +{ + struct ipa_gcc_hwio_def_gcc_global_en_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB3_LPC_GPLL0_ACGCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb3_lpc_gpll0_acgcr_s +{ + u32 reserved0 : 31; + u32 clk_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb3_lpc_gpll0_acgcr_u +{ + struct ipa_gcc_hwio_def_gcc_usb3_lpc_gpll0_acgcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB3_LPC_GPLL4_ACGCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb3_lpc_gpll4_acgcr_s +{ + u32 reserved0 : 31; + u32 clk_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb3_lpc_gpll4_acgcr_u +{ + struct ipa_gcc_hwio_def_gcc_usb3_lpc_gpll4_acgcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CPUSS_GPLL1_ACGCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cpuss_gpll1_acgcr_s +{ + u32 reserved0 : 31; + u32 clk_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cpuss_gpll1_acgcr_u +{ + struct ipa_gcc_hwio_def_gcc_cpuss_gpll1_acgcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CPUSS_GPLL4_ACGCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cpuss_gpll4_acgcr_s +{ + u32 reserved0 : 31; + u32 clk_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cpuss_gpll4_acgcr_u +{ + struct ipa_gcc_hwio_def_gcc_cpuss_gpll4_acgcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CPUSS_GPLL5_ACGCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cpuss_gpll5_acgcr_s +{ + u32 reserved0 : 31; + u32 clk_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cpuss_gpll5_acgcr_u +{ + struct ipa_gcc_hwio_def_gcc_cpuss_gpll5_acgcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_GPLL0_DIV_ACGCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_gpll0_div_acgcr_s +{ + u32 reserved0 : 31; + u32 clk_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_gpll0_div_acgcr_u +{ + struct ipa_gcc_hwio_def_gcc_mss_gpll0_div_acgcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PLL_MISC +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pll_misc_s +{ + u32 hw_triggered_stby_dis : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pll_misc_u +{ + struct ipa_gcc_hwio_def_gcc_pll_misc_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PLL_MISC1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pll_misc1_s +{ + u32 pll0_pll_active_mux : 1; + u32 pll1_pll_active_mux : 1; + u32 pll2_pll_active_mux : 1; + u32 pll3_pll_active_mux : 1; + u32 pll4_pll_active_mux : 1; + u32 pll5_pll_active_mux : 1; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pll_misc1_u +{ + struct ipa_gcc_hwio_def_gcc_pll_misc1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_PERST_HANDSHAKE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_perst_handshake_s +{ + u32 timer_enable : 1; + u32 reserved0 : 28; + u32 fsm_status : 2; + u32 timeout_status : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_perst_handshake_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_perst_handshake_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_PERST_HANDSHAKE_TIMER +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_perst_handshake_timer_s +{ + u32 timer_val : 32; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_perst_handshake_timer_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_perst_handshake_timer_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf0_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf0_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf0_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf1_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf1_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf1_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf2_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf2_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf2_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf3_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf3_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf3_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf4_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf4_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf4_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf5_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf5_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf5_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf6_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf6_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf6_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf7_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf7_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf7_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf8_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf8_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf8_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf9_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf9_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf9_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf10_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf10_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf10_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf11_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf11_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf11_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf12_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf12_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf12_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf13_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf13_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf13_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf14_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf14_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf14_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf15_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf15_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf15_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_PERF0_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf0_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf0_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf0_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_PERF1_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf1_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf1_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf1_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_PERF2_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf2_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf2_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf2_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_PERF3_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf3_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf3_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf3_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_PERF4_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf4_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf4_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf4_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_PERF5_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf5_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf5_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf5_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_PERF6_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf6_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf6_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf6_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_PERF7_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf7_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf7_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf7_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_PERF8_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf8_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf8_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf8_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_PERF9_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf9_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf9_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf9_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_PERF10_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf10_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf10_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf10_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_PERF11_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf11_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf11_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf11_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_PERF12_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf12_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf12_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf12_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_PERF13_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf13_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf13_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf13_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_PERF14_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf14_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf14_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf14_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_PERF15_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf15_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf15_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf15_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_PERF0_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf0_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_perf0_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf0_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_PERF1_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf1_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_perf1_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf1_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_PERF2_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf2_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_perf2_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf2_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_PERF3_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf3_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_perf3_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf3_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_PERF4_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf4_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_perf4_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf4_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_PERF5_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf5_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_perf5_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf5_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_PERF6_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf6_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_perf6_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf6_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_PERF7_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf7_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_perf7_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf7_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_PERF8_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf8_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_perf8_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf8_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_PERF9_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf9_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_perf9_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf9_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_PERF10_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf10_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_perf10_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf10_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_PERF11_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf11_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_perf11_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf11_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_PERF12_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf12_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_perf12_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf12_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_PERF13_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf13_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_perf13_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf13_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_PERF14_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf14_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_perf14_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf14_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_PERF15_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf15_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_perf15_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf15_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_PERF0_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_perf0_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_perf0_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_perf0_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_PERF1_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_perf1_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_perf1_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_perf1_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_PERF2_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_perf2_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_perf2_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_perf2_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_PERF3_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_perf3_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_perf3_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_perf3_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_PERF4_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_perf4_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_perf4_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_perf4_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_PERF5_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_perf5_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_perf5_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_perf5_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_PERF6_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_perf6_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_perf6_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_perf6_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_PERF7_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_perf7_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_perf7_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_perf7_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_PERF8_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_perf8_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_perf8_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_perf8_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_PERF9_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_perf9_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_perf9_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_perf9_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_PERF10_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_perf10_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_perf10_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_perf10_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_PERF11_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_perf11_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_perf11_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_perf11_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_PERF12_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_perf12_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_perf12_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_perf12_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_PERF13_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_perf13_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_perf13_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_perf13_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_PERF14_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_perf14_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_perf14_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_perf14_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QPIC_PERF15_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qpic_perf15_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qpic_perf15_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qpic_perf15_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PKA_PERF0_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pka_perf0_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pka_perf0_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pka_perf0_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PKA_PERF1_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pka_perf1_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pka_perf1_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pka_perf1_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PKA_PERF2_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pka_perf2_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pka_perf2_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pka_perf2_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PKA_PERF3_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pka_perf3_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pka_perf3_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pka_perf3_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PKA_PERF4_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pka_perf4_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pka_perf4_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pka_perf4_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PKA_PERF5_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pka_perf5_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pka_perf5_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pka_perf5_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PKA_PERF6_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pka_perf6_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pka_perf6_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pka_perf6_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PKA_PERF7_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pka_perf7_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pka_perf7_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pka_perf7_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PKA_PERF8_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pka_perf8_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pka_perf8_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pka_perf8_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PKA_PERF9_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pka_perf9_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pka_perf9_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pka_perf9_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PKA_PERF10_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pka_perf10_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pka_perf10_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pka_perf10_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PKA_PERF11_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pka_perf11_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pka_perf11_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pka_perf11_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PKA_PERF12_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pka_perf12_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pka_perf12_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pka_perf12_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PKA_PERF13_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pka_perf13_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pka_perf13_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pka_perf13_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PKA_PERF14_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pka_perf14_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pka_perf14_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pka_perf14_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PKA_PERF15_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pka_perf15_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pka_perf15_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pka_perf15_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_PERF0_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf0_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_perf0_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf0_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_PERF1_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf1_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_perf1_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf1_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_PERF2_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf2_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_perf2_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf2_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_PERF3_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf3_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_perf3_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf3_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_PERF4_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf4_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_perf4_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf4_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_PERF5_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf5_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_perf5_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf5_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_PERF6_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf6_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_perf6_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf6_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_PERF7_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf7_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_perf7_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf7_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_PERF8_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf8_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_perf8_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf8_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_PERF9_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf9_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_perf9_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf9_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_PERF10_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf10_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_perf10_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf10_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_PERF11_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf11_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_perf11_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf11_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_PERF12_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf12_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_perf12_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf12_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_PERF13_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf13_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_perf13_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf13_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_PERF14_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf14_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_perf14_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf14_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_PERF15_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf15_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_perf15_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf15_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_PERF0_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf0_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_perf0_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf0_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_PERF1_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf1_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_perf1_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf1_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_PERF2_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf2_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_perf2_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf2_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_PERF3_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf3_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_perf3_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf3_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_PERF4_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf4_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_perf4_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf4_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_PERF5_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf5_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_perf5_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf5_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_PERF6_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf6_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_perf6_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf6_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_PERF7_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf7_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_perf7_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf7_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_PERF8_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf8_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_perf8_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf8_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_PERF9_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf9_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_perf9_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf9_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_PERF10_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf10_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_perf10_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf10_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_PERF11_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf11_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_perf11_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf11_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_PERF12_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf12_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_perf12_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf12_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_PERF13_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf13_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_perf13_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf13_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_PERF14_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf14_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_perf14_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf14_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_PERF15_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf15_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_perf15_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf15_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_PERF0_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf0_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_perf0_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf0_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_PERF1_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf1_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_perf1_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf1_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_PERF2_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf2_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_perf2_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf2_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_PERF3_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf3_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_perf3_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf3_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_PERF4_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf4_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_perf4_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf4_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_PERF5_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf5_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_perf5_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf5_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_PERF6_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf6_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_perf6_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf6_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_PERF7_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf7_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_perf7_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf7_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_PERF8_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf8_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_perf8_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf8_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_PERF9_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf9_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_perf9_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf9_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_PERF10_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf10_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_perf10_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf10_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_PERF11_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf11_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_perf11_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf11_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_PERF12_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf12_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_perf12_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf12_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_PERF13_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf13_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_perf13_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf13_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_PERF14_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf14_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_perf14_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf14_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_PERF15_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf15_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_perf15_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf15_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_PERF0_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf0_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 gcc_mode : 1; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf0_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf0_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_PERF1_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf1_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 gcc_mode : 1; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf1_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf1_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_PERF2_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf2_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 gcc_mode : 1; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf2_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf2_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_PERF3_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf3_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 gcc_mode : 1; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf3_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf3_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_PERF4_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf4_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 gcc_mode : 1; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf4_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf4_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_PERF5_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf5_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 gcc_mode : 1; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf5_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf5_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_PERF6_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf6_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 gcc_mode : 1; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf6_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf6_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_PERF7_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf7_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 gcc_mode : 1; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf7_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf7_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_PERF8_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf8_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 gcc_mode : 1; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf8_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf8_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_PERF9_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf9_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 gcc_mode : 1; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf9_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf9_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_PERF10_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf10_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 gcc_mode : 1; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf10_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf10_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_PERF11_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf11_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 gcc_mode : 1; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf11_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf11_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_PERF12_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf12_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 gcc_mode : 1; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf12_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf12_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_PERF13_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf13_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 gcc_mode : 1; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf13_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf13_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_PERF14_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf14_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 gcc_mode : 1; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf14_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf14_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_PERF15_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf15_ena_vote_s +{ + u32 gpll0 : 1; + u32 gpll1 : 1; + u32 gpll2_3 : 1; + u32 gpll4 : 1; + u32 gpll5 : 1; + u32 gcc_mode : 1; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf15_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf15_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_PERF0_GPLL2_3_L_VAL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf0_gpll2_3_l_val_s +{ + u32 pll_l : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf0_gpll2_3_l_val_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf0_gpll2_3_l_val_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_PERF1_GPLL2_3_L_VAL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf1_gpll2_3_l_val_s +{ + u32 pll_l : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf1_gpll2_3_l_val_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf1_gpll2_3_l_val_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_PERF2_GPLL2_3_L_VAL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf2_gpll2_3_l_val_s +{ + u32 pll_l : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf2_gpll2_3_l_val_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf2_gpll2_3_l_val_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_PERF3_GPLL2_3_L_VAL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf3_gpll2_3_l_val_s +{ + u32 pll_l : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf3_gpll2_3_l_val_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf3_gpll2_3_l_val_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_PERF4_GPLL2_3_L_VAL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf4_gpll2_3_l_val_s +{ + u32 pll_l : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf4_gpll2_3_l_val_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf4_gpll2_3_l_val_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_PERF5_GPLL2_3_L_VAL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf5_gpll2_3_l_val_s +{ + u32 pll_l : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf5_gpll2_3_l_val_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf5_gpll2_3_l_val_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_PERF6_GPLL2_3_L_VAL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf6_gpll2_3_l_val_s +{ + u32 pll_l : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf6_gpll2_3_l_val_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf6_gpll2_3_l_val_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_PERF7_GPLL2_3_L_VAL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf7_gpll2_3_l_val_s +{ + u32 pll_l : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf7_gpll2_3_l_val_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf7_gpll2_3_l_val_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_PERF8_GPLL2_3_L_VAL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf8_gpll2_3_l_val_s +{ + u32 pll_l : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf8_gpll2_3_l_val_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf8_gpll2_3_l_val_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_PERF9_GPLL2_3_L_VAL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf9_gpll2_3_l_val_s +{ + u32 pll_l : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf9_gpll2_3_l_val_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf9_gpll2_3_l_val_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_PERF10_GPLL2_3_L_VAL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf10_gpll2_3_l_val_s +{ + u32 pll_l : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf10_gpll2_3_l_val_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf10_gpll2_3_l_val_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_PERF11_GPLL2_3_L_VAL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf11_gpll2_3_l_val_s +{ + u32 pll_l : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf11_gpll2_3_l_val_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf11_gpll2_3_l_val_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_PERF12_GPLL2_3_L_VAL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf12_gpll2_3_l_val_s +{ + u32 pll_l : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf12_gpll2_3_l_val_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf12_gpll2_3_l_val_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_PERF13_GPLL2_3_L_VAL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf13_gpll2_3_l_val_s +{ + u32 pll_l : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf13_gpll2_3_l_val_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf13_gpll2_3_l_val_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_PERF14_GPLL2_3_L_VAL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf14_gpll2_3_l_val_s +{ + u32 pll_l : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf14_gpll2_3_l_val_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf14_gpll2_3_l_val_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_PERF15_GPLL2_3_L_VAL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf15_gpll2_3_l_val_s +{ + u32 pll_l : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf15_gpll2_3_l_val_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf15_gpll2_3_l_val_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_PERF0_GPLL2_3_FRAC_VAL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf0_gpll2_3_frac_val_s +{ + u32 pll_frac_val : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf0_gpll2_3_frac_val_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf0_gpll2_3_frac_val_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_PERF1_GPLL2_3_FRAC_VAL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf1_gpll2_3_frac_val_s +{ + u32 pll_frac_val : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf1_gpll2_3_frac_val_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf1_gpll2_3_frac_val_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_PERF2_GPLL2_3_FRAC_VAL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf2_gpll2_3_frac_val_s +{ + u32 pll_frac_val : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf2_gpll2_3_frac_val_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf2_gpll2_3_frac_val_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_PERF3_GPLL2_3_FRAC_VAL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf3_gpll2_3_frac_val_s +{ + u32 pll_frac_val : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf3_gpll2_3_frac_val_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf3_gpll2_3_frac_val_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_PERF4_GPLL2_3_FRAC_VAL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf4_gpll2_3_frac_val_s +{ + u32 pll_frac_val : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf4_gpll2_3_frac_val_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf4_gpll2_3_frac_val_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_PERF5_GPLL2_3_FRAC_VAL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf5_gpll2_3_frac_val_s +{ + u32 pll_frac_val : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf5_gpll2_3_frac_val_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf5_gpll2_3_frac_val_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_PERF6_GPLL2_3_FRAC_VAL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf6_gpll2_3_frac_val_s +{ + u32 pll_frac_val : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf6_gpll2_3_frac_val_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf6_gpll2_3_frac_val_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_PERF7_GPLL2_3_FRAC_VAL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf7_gpll2_3_frac_val_s +{ + u32 pll_frac_val : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf7_gpll2_3_frac_val_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf7_gpll2_3_frac_val_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_PERF8_GPLL2_3_FRAC_VAL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf8_gpll2_3_frac_val_s +{ + u32 pll_frac_val : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf8_gpll2_3_frac_val_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf8_gpll2_3_frac_val_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_PERF9_GPLL2_3_FRAC_VAL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf9_gpll2_3_frac_val_s +{ + u32 pll_frac_val : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf9_gpll2_3_frac_val_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf9_gpll2_3_frac_val_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_PERF10_GPLL2_3_FRAC_VAL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf10_gpll2_3_frac_val_s +{ + u32 pll_frac_val : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf10_gpll2_3_frac_val_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf10_gpll2_3_frac_val_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_PERF11_GPLL2_3_FRAC_VAL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf11_gpll2_3_frac_val_s +{ + u32 pll_frac_val : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf11_gpll2_3_frac_val_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf11_gpll2_3_frac_val_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_PERF12_GPLL2_3_FRAC_VAL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf12_gpll2_3_frac_val_s +{ + u32 pll_frac_val : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf12_gpll2_3_frac_val_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf12_gpll2_3_frac_val_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_PERF13_GPLL2_3_FRAC_VAL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf13_gpll2_3_frac_val_s +{ + u32 pll_frac_val : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf13_gpll2_3_frac_val_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf13_gpll2_3_frac_val_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_PERF14_GPLL2_3_FRAC_VAL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf14_gpll2_3_frac_val_s +{ + u32 pll_frac_val : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf14_gpll2_3_frac_val_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf14_gpll2_3_frac_val_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_PERF15_GPLL2_3_FRAC_VAL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf15_gpll2_3_frac_val_s +{ + u32 pll_frac_val : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf15_gpll2_3_frac_val_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_perf15_gpll2_3_frac_val_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_FAKE_SWITCH_DEBUG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_fake_switch_debug_s +{ + u32 pll_toggle_en : 1; + u32 rcg_toggle_en : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_fake_switch_debug_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_fake_switch_debug_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_DDRMC_SWITCH_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_switch_status_s +{ + u32 rpmh_ddrmc_clock_switch_fsm_state : 5; + u32 rpmh_ddrmc_clock_switch_fsm_pll_toggle_fsm_state : 1; + u32 rpmh_ddrmc_clock_switch_fsm_rcg_toggle_fsm_state : 1; + u32 reserved0 : 25; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ddrmc_switch_status_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ddrmc_switch_status_s def; + u32 value; +}; + + +#endif /* __IPA_GCC_HWIO_DEF_H__ */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.0/ipa_hw_common_ex.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.0/ipa_hw_common_ex.h new file mode 100644 index 0000000000..52856a91db --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.0/ipa_hw_common_ex.h @@ -0,0 +1,658 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ +#if !defined(_IPA_HW_COMMON_EX_H_) +#define _IPA_HW_COMMON_EX_H_ + +/* VLVL defs are available for 854 */ +#define FEATURE_VLVL_DEFS true + +#define FEATURE_IPA_HW_VERSION_4_5 true + +/* Important Platform Specific Values : IRQ_NUM, IRQ_CNT, BCR */ +#define IPA_HW_BAM_IRQ_NUM 639 + +/* Q6 IRQ number for IPA. */ +#define IPA_HW_IRQ_NUM 640 + +/* Total number of different interrupts that can be enabled */ +#define IPA_HW_IRQ_CNT_TOTAL 23 + +/* IPAv4 spare reg value */ +#define IPA_HW_SPARE_1_REG_VAL 0xC0000005 + +/* Whether to allow setting step mode on IPA when we crash or not */ +#define IPA_CFG_HW_IS_STEP_MODE_ALLOWED (false) + +/* GSI MHI related definitions */ +#define IPA_HW_GSI_MHI_CONSUMER_CHANNEL_NUM 0x0 +#define IPA_HW_GSI_MHI_PRODUCER_CHANNEL_NUM 0x1 + +#define IPA_HW_GSI_MHI_CONSUMER_EP_NUM 0x1 +#define IPA_HW_GSI_MHI_PRODUCER_EP_NUM 0x11 + +/* IPA ZIP WA related Macros */ +#define IPA_HW_DCMP_SRC_PIPE 0x8 +#define IPA_HW_DCMP_DEST_PIPE 0x4 +#define IPA_HW_ACK_MNGR_MASK 0x1D +#define IPA_HW_DCMP_SRC_GRP 0x5 + +/* IPA Clock resource name */ +#define IPA_CLK_RESOURCE_NAME "/clk/pcnoc" + +/* IPA Clock Bus Client name */ +#define IPA_CLK_BUS_CLIENT_NAME "IPA_PCNOC_BUS_CLIENT" + +/* HPS Sequences */ +#define IPA_HW_PKT_PROCESS_HPS_DMA 0x0 +#define IPA_HW_PKT_PROCESS_HPS_DMA_DECIPH_CIPHE 0x1 +#define IPA_HW_PKT_PROCESS_HPS_PKT_PRS_NO_DECIPH_UCP 0x2 +#define IPA_HW_PKT_PROCESS_HPS_PKT_PRS_DECIPH_UCP 0x3 +#define IPA_HW_PKT_PROCESS_HPS_2_PKT_PRS_NO_DECIPH 0x4 +#define IPA_HW_PKT_PROCESS_HPS_2_PKT_PRS_DECIPH 0x5 +#define IPA_HW_PKT_PROCESS_HPS_PKT_PRS_NO_DECIPH_NO_UCP 0x6 +#define IPA_HW_PKT_PROCESS_HPS_PKT_PRS_DECIPH_NO_UCP 0x7 +#define IPA_HW_PKT_PROCESS_HPS_DMA_PARSER 0x8 +#define IPA_HW_PKT_PROCESS_HPS_DMA_DECIPH_PARSER 0x9 +#define IPA_HW_PKT_PROCESS_HPS_2_PKT_PRS_UCP_TWICE_NO_DECIPH 0xA +#define IPA_HW_PKT_PROCESS_HPS_2_PKT_PRS_UCP_TWICE_DECIPH 0xB +#define IPA_HW_PKT_PROCESS_HPS_3_PKT_PRS_UCP_TWICE_NO_DECIPH 0xC +#define IPA_HW_PKT_PROCESS_HPS_3_PKT_PRS_UCP_TWICE_DECIPH 0xD + +/* DPS Sequences */ +#define IPA_HW_PKT_PROCESS_DPS_DMA 0x0 +#define IPA_HW_PKT_PROCESS_DPS_DMA_WITH_DECIPH 0x1 +#define IPA_HW_PKT_PROCESS_DPS_DMA_WITH_DECOMP 0x2 +#define IPA_HW_PKT_PROCESS_DPS_DMA_WITH_CIPH 0x3 + +/* Src RSRC GRP config */ +#define IPA_HW_SRC_RSRC_GRP_01_RSRC_TYPE_0 0x0B040803 +#define IPA_HW_SRC_RSRC_GRP_01_RSRC_TYPE_1 0x0C0C0909 +#define IPA_HW_SRC_RSRC_GRP_01_RSRC_TYPE_2 0x0E0E0909 +#define IPA_HW_SRC_RSRC_GRP_01_RSRC_TYPE_3 0x3F003F00 +#define IPA_HW_SRC_RSRC_GRP_01_RSRC_TYPE_4 0x10101616 + +#define IPA_HW_SRC_RSRC_GRP_23_RSRC_TYPE_0 0x01010101 +#define IPA_HW_SRC_RSRC_GRP_23_RSRC_TYPE_1 0x02020202 +#define IPA_HW_SRC_RSRC_GRP_23_RSRC_TYPE_2 0x04040404 +#define IPA_HW_SRC_RSRC_GRP_23_RSRC_TYPE_3 0x3F003F00 +#define IPA_HW_SRC_RSRC_GRP_23_RSRC_TYPE_4 0x02020606 + +#define IPA_HW_SRC_RSRC_GRP_45_RSRC_TYPE_0 0x00000000 +#define IPA_HW_SRC_RSRC_GRP_45_RSRC_TYPE_1 0x00000000 +#define IPA_HW_SRC_RSRC_GRP_45_RSRC_TYPE_2 0x00000000 +#define IPA_HW_SRC_RSRC_GRP_45_RSRC_TYPE_3 0x00003F00 +#define IPA_HW_SRC_RSRC_GRP_45_RSRC_TYPE_4 0x00000000 + +/* Dest RSRC GRP config */ +#define IPA_HW_DST_RSRC_GRP_01_RSRC_TYPE_0 0x05051010 +#define IPA_HW_DST_RSRC_GRP_01_RSRC_TYPE_1 0x3F013F02 + +#define IPA_HW_DST_RSRC_GRP_23_RSRC_TYPE_0 0x02020202 +#define IPA_HW_DST_RSRC_GRP_23_RSRC_TYPE_1 0x02010201 + +#define IPA_HW_DST_RSRC_GRP_45_RSRC_TYPE_0 0x00000000 +#define IPA_HW_DST_RSRC_GRP_45_RSRC_TYPE_1 0x00000200 + +#define IPA_HW_RX_HPS_CLIENTS_MIN_DEPTH_0 0x03030303 +#define IPA_HW_RX_HPS_CLIENTS_MAX_DEPTH_0 0x03030303 + +#define IPA_HW_RSRP_GRP_0 0x0 +#define IPA_HW_RSRP_GRP_1 0x1 +#define IPA_HW_RSRP_GRP_2 0x2 +#define IPA_HW_RSRP_GRP_3 0x3 + +#define IPA_HW_PCIE_SRC_RSRP_GRP IPA_HW_RSRP_GRP_0 +#define IPA_HW_PCIE_DEST_RSRP_GRP IPA_HW_RSRP_GRP_0 + +#define IPA_HW_DDR_SRC_RSRP_GRP IPA_HW_RSRP_GRP_1 +#define IPA_HW_DDR_DEST_RSRP_GRP IPA_HW_RSRP_GRP_1 + +#define IPA_HW_DMA_SRC_RSRP_GRP IPA_HW_RSRP_GRP_2 +#define IPA_HW_DMA_DEST_RSRP_GRP IPA_HW_RSRP_GRP_2 + +#define IPA_HW_SRC_RSRP_TYPE_MAX 0x05 +#define IPA_HW_DST_RSRP_TYPE_MAX 0x03 + +#define GSI_HW_QSB_LOG_MISC_MAX 0x4 + +/* IPA Clock Bus Client name */ +#define IPA_CLK_BUS_CLIENT_NAME "IPA_PCNOC_BUS_CLIENT" + +/* Is IPA decompression feature enabled */ +#define IPA_HW_IS_DECOMPRESSION_ENABLED (1) + +/* Whether to allow setting step mode on IPA when we crash or not */ +#define IPA_HW_IS_STEP_MODE_ALLOWED (true) + +/* Max number of virtual pipes for UL QBAP provided by HW */ +#define IPA_HW_MAX_VP_NUM (32) + +/* + * HW specific clock vote freq values in KHz + * (BIMC/SNOC/PCNOC/IPA/Q6 CPU) + */ +enum ipa_hw_clk_freq_e { + /* BIMC */ + IPA_HW_CLK_FREQ_BIMC_PEAK = 518400, + IPA_HW_CLK_FREQ_BIMC_NOM_PLUS = 404200, + IPA_HW_CLK_FREQ_BIMC_NOM = 404200, + IPA_HW_CLK_FREQ_BIMC_SVS = 100000, + + /* PCNOC */ + IPA_HW_CLK_FREQ_PCNOC_PEAK = 133330, + IPA_HW_CLK_FREQ_PCNOC_NOM_PLUS = 100000, + IPA_HW_CLK_FREQ_PCNOC_NOM = 100000, + IPA_HW_CLK_FREQ_PCNOC_SVS = 50000, + + /*IPA_HW_CLK_SNOC*/ + IPA_HW_CLK_FREQ_SNOC_PEAK = 200000, + IPA_HW_CLK_FREQ_SNOC_NOM_PLUS = 150000, + IPA_HW_CLK_FREQ_SNOC_NOM = 150000, + IPA_HW_CLK_FREQ_SNOC_SVS = 85000, + IPA_HW_CLK_FREQ_SNOC_SVS_2 = 50000, + + /* IPA */ + IPA_HW_CLK_FREQ_IPA_PEAK = 600000, + IPA_HW_CLK_FREQ_IPA_NOM_PLUS = 500000, + IPA_HW_CLK_FREQ_IPA_NOM = 500000, + IPA_HW_CLK_FREQ_IPA_SVS = 250000, + IPA_HW_CLK_FREQ_IPA_SVS_2 = 150000, + + /* Q6 CPU */ + IPA_HW_CLK_FREQ_Q6_PEAK = 729600, + IPA_HW_CLK_FREQ_Q6_NOM_PLUS = 729600, + IPA_HW_CLK_FREQ_Q6_NOM = 729600, + IPA_HW_CLK_FREQ_Q6_SVS = 729600, +}; + +enum ipa_hw_qtimer_gran_e { + IPA_HW_QTIMER_GRAN_0 = 0, /* granularity 0 is 10us */ + IPA_HW_QTIMER_GRAN_1 = 1, /* granularity 1 is 100us */ + IPA_HW_QTIMER_GRAN_MAX, +}; + +/* Pipe ID of all the IPA pipes */ +enum ipa_hw_pipe_id_e { + IPA_HW_PIPE_ID_0, + IPA_HW_PIPE_ID_1, + IPA_HW_PIPE_ID_2, + IPA_HW_PIPE_ID_3, + IPA_HW_PIPE_ID_4, + IPA_HW_PIPE_ID_5, + IPA_HW_PIPE_ID_6, + IPA_HW_PIPE_ID_7, + IPA_HW_PIPE_ID_8, + IPA_HW_PIPE_ID_9, + IPA_HW_PIPE_ID_10, + IPA_HW_PIPE_ID_11, + IPA_HW_PIPE_ID_12, + IPA_HW_PIPE_ID_13, + IPA_HW_PIPE_ID_14, + IPA_HW_PIPE_ID_15, + IPA_HW_PIPE_ID_16, + IPA_HW_PIPE_ID_17, + IPA_HW_PIPE_ID_18, + IPA_HW_PIPE_ID_19, + IPA_HW_PIPE_ID_20, + IPA_HW_PIPE_ID_21, + IPA_HW_PIPE_ID_22, + IPA_HW_PIPE_ID_23, + IPA_HW_PIPE_ID_24, + IPA_HW_PIPE_ID_25, + IPA_HW_PIPE_ID_26, + IPA_HW_PIPE_ID_27, + IPA_HW_PIPE_ID_28, + IPA_HW_PIPE_ID_29, + IPA_HW_PIPE_ID_30, + IPA_HW_PIPE_ID_31, + IPA_HW_PIPE_ID_32, + IPA_HW_PIPE_ID_33, + IPA_HW_PIPE_ID_34, + IPA_HW_PIPE_ID_35, + IPA_HW_PIPE_ID_MAX +}; + +/* Pipe ID's of System Bam Endpoints between Q6 & IPA */ +enum ipa_hw_q6_pipe_id_e { + /* Pipes used by IPA Q6 driver */ + IPA_HW_Q6_DL_CONSUMER_PIPE_ID = IPA_HW_PIPE_ID_5, + IPA_HW_Q6_CTL_CONSUMER_PIPE_ID = IPA_HW_PIPE_ID_6, + IPA_HW_Q6_DL_NLO_CONSUMER_PIPE_ID = IPA_HW_PIPE_ID_8, + + IPA_HW_Q6_UL_ACC_ACK_PRODUCER_PIPE_ID = IPA_HW_PIPE_ID_20, + IPA_HW_Q6_UL_PRODUCER_PIPE_ID = IPA_HW_PIPE_ID_21, + IPA_HW_Q6_DL_PRODUCER_PIPE_ID = IPA_HW_PIPE_ID_17, + IPA_HW_Q6_QBAP_STATUS_PRODUCER_PIPE_ID = IPA_HW_PIPE_ID_18, + IPA_HW_Q6_UL_ACC_DATA_PRODUCER_PIPE_ID = IPA_HW_PIPE_ID_19, + + IPA_HW_Q6_UL_ACK_PRODUCER_PIPE_ID = + IPA_HW_Q6_UL_ACC_ACK_PRODUCER_PIPE_ID, + IPA_HW_Q6_UL_DATA_PRODUCER_PIPE_ID = + IPA_HW_Q6_UL_ACC_DATA_PRODUCER_PIPE_ID, + + IPA_HW_Q6_DMA_ASYNC_CONSUMER_PIPE_ID = IPA_HW_PIPE_ID_4, + IPA_HW_Q6_DMA_ASYNC_PRODUCER_PIPE_ID = IPA_HW_PIPE_ID_29, + + /* Test Simulator Pipes */ + IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_0_ID = IPA_HW_PIPE_ID_0, + IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_1_ID = IPA_HW_PIPE_ID_1, + + /* GSI UT channel SW->IPA */ + IPA_HW_Q6_GSI_UT_CONSUMER_PIPE_1_ID = IPA_HW_PIPE_ID_3, + /* GSI UT channel SW->IPA */ + IPA_HW_Q6_GSI_UT_CONSUMER_PIPE_2_ID = IPA_HW_PIPE_ID_10, + + IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_2_ID = IPA_HW_PIPE_ID_7, + + /* GSI UT channel IPA->SW */ + IPA_HW_Q6_DIAG_CONSUMER_PIPE_ID = IPA_HW_PIPE_ID_9, + + IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_0_ID = IPA_HW_PIPE_ID_23, + IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_1_ID = IPA_HW_PIPE_ID_24, + + IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_2_ID = IPA_HW_PIPE_ID_25, + + /* GSI UT channel IPA->SW */ + IPA_HW_Q6_GSI_UT_PRODUCER_PIPE_1_ID = IPA_HW_PIPE_ID_26, + + /* GSI UT channel IPA->SW */ + IPA_HW_Q6_GSI_UT_PRODUCER_PIPE_2_ID = IPA_HW_PIPE_ID_27, + IPA_HW_Q6_PIPE_ID_MAX = IPA_HW_PIPE_ID_MAX, +}; + +enum ipa_hw_q6_pipe_ch_id_e { + /* Channels used by IPA Q6 driver */ + IPA_HW_Q6_DL_CONSUMER_PIPE_CH_ID = 0, + IPA_HW_Q6_CTL_CONSUMER_PIPE_CH_ID = 1, + IPA_HW_Q6_DL_NLO_CONSUMER_PIPE_CH_ID = 2, + IPA_HW_Q6_UL_ACC_PATH_ACK_PRODUCER_PIPE_CH_ID = 6, + IPA_HW_Q6_UL_PRODUCER_PIPE_CH_ID = 7, + IPA_HW_Q6_DL_PRODUCER_PIPE_CH_ID = 3, + IPA_HW_Q6_UL_ACC_PATH_DATA_PRODUCER_PIPE_CH_ID = 5, + IPA_HW_Q6_QBAP_STATUS_PRODUCER_PIPE_CH_ID = 4, + + IPA_HW_Q6_DMA_ASYNC_CONSUMER_PIPE_CH_ID = 8, + IPA_HW_Q6_DMA_ASYNC_PRODUCER_PIPE_CH_ID = 9, + /* CH_ID 8 and 9 are Q6 SPARE CONSUMERs */ + + /* Test Simulator Channels */ + IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_0_CH_ID = 10, + IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_0_CH_ID = 11, + IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_1_CH_ID = 12, + IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_1_CH_ID = 13, + IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_2_CH_ID = 14, + IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_2_CH_ID = 15, + /* GSI UT channel SW->IPA */ + IPA_HW_Q6_GSI_UT_CONSUMER_PIPE_1_CH_ID = 16, + /* GSI UT channel IPA->SW */ + IPA_HW_Q6_GSI_UT_PRODUCER_PIPE_1_CH_ID = 17, + /* GSI UT channel SW->IPA */ + IPA_HW_Q6_GSI_UT_CONSUMER_PIPE_2_CH_ID = 18, + /* GSI UT channel IPA->SW */ + IPA_HW_Q6_GSI_UT_PRODUCER_PIPE_2_CH_ID = 19, +}; + +/* System Bam Endpoints between Q6 & IPA */ +enum ipa_hw_q6_pipe_e { + /* DL Pipe IPA->Q6 */ + IPA_HW_Q6_DL_PRODUCER_PIPE = 0, + /* UL Pipe IPA->Q6 */ + IPA_HW_Q6_UL_PRODUCER_PIPE = 1, + /* DL Pipe Q6->IPA */ + IPA_HW_Q6_DL_CONSUMER_PIPE = 2, + /* CTL Pipe Q6->IPA */ + IPA_HW_Q6_CTL_CONSUMER_PIPE = 3, + /* Q6 -> IPA, DL NLO */ + IPA_HW_Q6_DL_NLO_CONSUMER_PIPE = 4, + /* DMA ASYNC CONSUMER */ + IPA_HW_Q6_DMA_ASYNC_CONSUMER_PIPE = 5, + /* DMA ASYNC PRODUCER */ + IPA_HW_Q6_DMA_ASYNC_PRODUCER_PIPE = 6, + /* UL Acc Path Data Pipe IPA->Q6 */ + IPA_HW_Q6_UL_ACC_DATA_PRODUCER_PIPE = 7, + /* UL Acc Path ACK Pipe IPA->Q6 */ + IPA_HW_Q6_UL_ACC_ACK_PRODUCER_PIPE = 8, + /* UL Acc Path QBAP status Pipe IPA->Q6 */ + IPA_HW_Q6_QBAP_STATUS_PRODUCER_PIPE = 9, + /* Diag status pipe IPA->Q6 */ + /* Used only when FEATURE_IPA_TEST_PER_SIM is ON */ + /* SIM Pipe IPA->Sim */ + IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_0 = 10, + /* SIM Pipe Sim->IPA */ + IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_1 = 11, + /* SIM Pipe Sim->IPA */ + IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_2 = 12, + /* SIM Pipe Sim->IPA */ + IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_0 = 13, + /* SIM B2B PROD Pipe */ + IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_1 = 14, + /* SIM Pipe IPA->Sim */ + IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_2 = 15, + /* End FEATURE_IPA_TEST_PER_SIM */ + /* GSI UT channel SW->IPA */ + IPA_HW_Q6_GSI_UT_CONSUMER_PIPE_1 = 16, + /* GSI UT channel IPA->SW */ + IPA_HW_Q6_GSI_UT_PRODUCER_PIPE_1 = 17, + /* GSI UT channel SW->IPA */ + IPA_HW_Q6_GSI_UT_CONSUMER_PIPE_2 = 18, + /* GSI UT channel IPA->SW */ + IPA_HW_Q6_GSI_UT_PRODUCER_PIPE_2 = 19, + + IPA_HW_Q6_PIPE_TOTAL +}; + +/* System Bam Endpoints between Q6 & IPA */ +enum ipa_hw_q6_gsi_ev_e { /* In Sdx24 0..11 */ + /* DL Pipe IPA->Q6 */ + IPA_HW_Q6_DL_PRODUCER_PIPE_GSI_EV = 0, + /* UL Pipe IPA->Q6 */ + IPA_HW_Q6_UL_PRODUCER_PIPE_GSI_EV = 1, + /* DL Pipe Q6->IPA */ + //IPA_HW_Q6_DL_CONSUMER_PIPE_GSI_EV = 2, + /* CTL Pipe Q6->IPA */ + //IPA_HW_Q6_CTL_CONSUMER_PIPE_GSI_EV = 3, + /* Q6 -> IPA, LTE DL Optimized path */ + //IPA_HW_Q6_LTE_DL_CONSUMER_PIPE_GSI_EV = 4, + /* LWA DL(Wifi to Q6) */ + //IPA_HW_Q6_LWA_DL_PRODUCER_PIPE_GSI_EV = 5, + /* Diag status pipe IPA->Q6 */ + //IPA_HW_Q6_DIAG_STATUS_PRODUCER_PIPE_GSI_EV = 6, + /* Used only when FEATURE_IPA_TEST_PER_SIM is ON */ + /* SIM Pipe IPA->Sim */ + IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_0_GSI_EV = 2, + /* SIM Pipe Sim->IPA */ + IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_1_GSI_EV = 3, + /* SIM Pipe Sim->IPA */ + IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_2_GSI_EV = 4, + /* SIM Pipe Sim->IPA */ + IPA_HW_Q6_SIM_1_GSI_EV = 5, + IPA_HW_Q6_SIM_2_GSI_EV = 6, + IPA_HW_Q6_SIM_3_GSI_EV = 7, + IPA_HW_Q6_SIM_4_GSI_EV = 8, + + IPA_HW_Q6_PIPE_GSI_EV_TOTAL +}; + +/* + * All the IRQ's supported by the IPA HW. Use this enum to set IRQ_EN + * register and read IRQ_STTS register + */ +enum ipa_hw_irq_e { + IPA_HW_IRQ_GSI_HWP = (1 << 25), + IPA_HW_IRQ_GSI_IPA_IF_TLV_RCVD = (1 << 24), + IPA_HW_IRQ_GSI_EE_IRQ = (1 << 23), + IPA_HW_IRQ_DCMP_ERR = (1 << 22), + IPA_HW_IRQ_HWP_ERR = (1 << 21), + IPA_HW_IRQ_RED_MARKER_ABOVE = (1 << 20), + IPA_HW_IRQ_YELLOW_MARKER_ABOVE = (1 << 19), + IPA_HW_IRQ_RED_MARKER_BELOW = (1 << 18), + IPA_HW_IRQ_YELLOW_MARKER_BELOW = (1 << 17), + IPA_HW_IRQ_BAM_IDLE_IRQ = (1 << 16), + IPA_HW_IRQ_TX_HOLB_DROP = (1 << 15), + IPA_HW_IRQ_TX_SUSPEND = (1 << 14), + IPA_HW_IRQ_PROC_ERR = (1 << 13), + IPA_HW_IRQ_STEP_MODE = (1 << 12), + IPA_HW_IRQ_TX_ERR = (1 << 11), + IPA_HW_IRQ_DEAGGR_ERR = (1 << 10), + IPA_HW_IRQ_RX_ERR = (1 << 9), + IPA_HW_IRQ_PROC_TO_HW_ACK_Q_NOT_EMPTY = (1 << 8), + IPA_HW_IRQ_HWP_RX_CMD_Q_NOT_FULL = (1 << 7), + IPA_HW_IRQ_HWP_IN_Q_NOT_EMPTY = (1 << 6), + IPA_HW_IRQ_HWP_IRQ_3 = (1 << 5), + IPA_HW_IRQ_HWP_IRQ_2 = (1 << 4), + IPA_HW_IRQ_HWP_IRQ_1 = (1 << 3), + IPA_HW_IRQ_HWP_IRQ_0 = (1 << 2), + IPA_HW_IRQ_EOT_COAL = (1 << 1), + IPA_HW_IRQ_BAD_SNOC_ACCESS = (1 << 0), + IPA_HW_IRQ_NONE = 0, + IPA_HW_IRQ_ALL = 0xFFFFFFFF +}; + +/* + * All the IRQ sources supported by the IPA HW. Use this enum to set + * IRQ_SRCS register + */ +enum ipa_hw_irq_srcs_e { + IPA_HW_IRQ_SRCS_PIPE_0 = (1 << IPA_HW_PIPE_ID_0), + IPA_HW_IRQ_SRCS_PIPE_1 = (1 << IPA_HW_PIPE_ID_1), + IPA_HW_IRQ_SRCS_PIPE_2 = (1 << IPA_HW_PIPE_ID_2), + IPA_HW_IRQ_SRCS_PIPE_3 = (1 << IPA_HW_PIPE_ID_3), + IPA_HW_IRQ_SRCS_PIPE_4 = (1 << IPA_HW_PIPE_ID_4), + IPA_HW_IRQ_SRCS_PIPE_5 = (1 << IPA_HW_PIPE_ID_5), + IPA_HW_IRQ_SRCS_PIPE_6 = (1 << IPA_HW_PIPE_ID_6), + IPA_HW_IRQ_SRCS_PIPE_7 = (1 << IPA_HW_PIPE_ID_7), + IPA_HW_IRQ_SRCS_PIPE_8 = (1 << IPA_HW_PIPE_ID_8), + IPA_HW_IRQ_SRCS_PIPE_9 = (1 << IPA_HW_PIPE_ID_9), + IPA_HW_IRQ_SRCS_PIPE_10 = (1 << IPA_HW_PIPE_ID_10), + IPA_HW_IRQ_SRCS_PIPE_11 = (1 << IPA_HW_PIPE_ID_11), + IPA_HW_IRQ_SRCS_PIPE_12 = (1 << IPA_HW_PIPE_ID_12), + IPA_HW_IRQ_SRCS_PIPE_13 = (1 << IPA_HW_PIPE_ID_13), + IPA_HW_IRQ_SRCS_PIPE_14 = (1 << IPA_HW_PIPE_ID_14), + IPA_HW_IRQ_SRCS_PIPE_15 = (1 << IPA_HW_PIPE_ID_15), + IPA_HW_IRQ_SRCS_PIPE_16 = (1 << IPA_HW_PIPE_ID_16), + IPA_HW_IRQ_SRCS_PIPE_17 = (1 << IPA_HW_PIPE_ID_17), + IPA_HW_IRQ_SRCS_PIPE_18 = (1 << IPA_HW_PIPE_ID_18), + IPA_HW_IRQ_SRCS_PIPE_19 = (1 << IPA_HW_PIPE_ID_19), + IPA_HW_IRQ_SRCS_PIPE_20 = (1 << IPA_HW_PIPE_ID_20), + IPA_HW_IRQ_SRCS_PIPE_21 = (1 << IPA_HW_PIPE_ID_21), + IPA_HW_IRQ_SRCS_PIPE_22 = (1 << IPA_HW_PIPE_ID_22), + IPA_HW_IRQ_SRCS_NONE = 0, + IPA_HW_IRQ_SRCS_ALL = 0xFFFFFFFF, +}; + +/* + * Total number of channel contexts that need to be saved for APPS + */ +#define IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_A7 27 + +/* + * Total number of channel contexts that need to be saved for UC + */ +#define IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_UC 2 + + /* + * Total number of channel contexts that need to be saved for Q6 + */ +#define IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_Q6 11 + +/* + * Total number of event ring contexts that need to be saved for APPS + */ +#define IPA_HW_REG_SAVE_GSI_NUM_EVT_CNTXT_A7 27 + +/* + * Total number of event ring contexts that need to be saved for UC + */ +#define IPA_HW_REG_SAVE_GSI_NUM_EVT_CNTXT_UC 2 + +/* + * Total number of event ring contexts that need to be saved for Q6 + */ +#define IPA_HW_REG_SAVE_GSI_NUM_EVT_CNTXT_Q6 11 + +/* + * Total number of endpoints for which ipa_reg_save.pipes[endp_number] + * are not saved by default (only if ipa_cfg.gen.full_reg_trace = + * true) There is no extra endpoints in Stingray + */ +#define IPA_HW_REG_SAVE_NUM_ENDP_EXTRA 0 + +/* + * Total number of endpoints for which ipa_reg_save.pipes[endp_number] + * are always saved + */ +#define IPA_HW_REG_SAVE_NUM_ACTIVE_PIPES IPA_HW_PIPE_ID_MAX + +/* + * SHRAM Bytes per ch + */ +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 +#define IPA_REG_SAVE_BYTES_PER_CHNL_SHRAM 20 +#else +#define IPA_REG_SAVE_BYTES_PER_CHNL_SHRAM 12 +#endif + +/* + * Total number of rx splt cmdq's see: + * ipa_rx_splt_cmdq_n_cmd[IPA_RX_SPLT_CMDQ_MAX] + */ +#define IPA_RX_SPLT_CMDQ_MAX 4 + +/* + * Although not necessary for the numbers below, the use of round_up + * is so that future developers know that these particular constants + * have to be a multiple of four bytes, because the IPA memory reads + * that they drive are always 32 bits... + */ +#define IPA_IU_ADDR 0x001A0000 +#define IPA_IU_SIZE round_up(40704, sizeof(u32)) + +#define IPA_SRAM_ADDR 0x00150000 +#define IPA_SRAM_SIZE round_up(19232, sizeof(u32)) + +#define IPA_MBOX_ADDR 0x001C2000 +#define IPA_MBOX_SIZE round_up(256, sizeof(u32)) + +#define IPA_HRAM_ADDR 0x00160000 +#define IPA_HRAM_SIZE round_up(47536, sizeof(u32)) + +#define IPA_SEQ_ADDR 0x00181000 +#define IPA_SEQ_SIZE round_up(768, sizeof(u32)) + +#define IPA_GSI_ADDR 0x00006000 +#define IPA_GSI_SIZE round_up(5376, sizeof(u32)) + +/* + * Macro to define a particular register cfg entry for all pipe + * indexed register + */ +#define IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(reg_name, var_name) \ + { GEN_1xVECTOR_REG_OFST(reg_name, 0), \ + (u32 *)&ipa_reg_save.ipa.pipes[0].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 1), \ + (u32 *)&ipa_reg_save.ipa.pipes[1].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 2), \ + (u32 *)&ipa_reg_save.ipa.pipes[2].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 3), \ + (u32 *)&ipa_reg_save.ipa.pipes[3].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 4), \ + (u32 *)&ipa_reg_save.ipa.pipes[4].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 5), \ + (u32 *)&ipa_reg_save.ipa.pipes[5].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 6), \ + (u32 *)&ipa_reg_save.ipa.pipes[6].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 7), \ + (u32 *)&ipa_reg_save.ipa.pipes[7].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 8), \ + (u32 *)&ipa_reg_save.ipa.pipes[8].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 9), \ + (u32 *)&ipa_reg_save.ipa.pipes[9].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 10), \ + (u32 *)&ipa_reg_save.ipa.pipes[10].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 11), \ + (u32 *)&ipa_reg_save.ipa.pipes[11].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 12), \ + (u32 *)&ipa_reg_save.ipa.pipes[12].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 13), \ + (u32 *)&ipa_reg_save.ipa.pipes[13].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 14), \ + (u32 *)&ipa_reg_save.ipa.pipes[14].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 15), \ + (u32 *)&ipa_reg_save.ipa.pipes[15].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 16), \ + (u32 *)&ipa_reg_save.ipa.pipes[16].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 17), \ + (u32 *)&ipa_reg_save.ipa.pipes[17].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 18), \ + (u32 *)&ipa_reg_save.ipa.pipes[18].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 19), \ + (u32 *)&ipa_reg_save.ipa.pipes[19].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 20), \ + (u32 *)&ipa_reg_save.ipa.pipes[20].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 21), \ + (u32 *)&ipa_reg_save.ipa.pipes[21].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 22), \ + (u32 *)&ipa_reg_save.ipa.pipes[22].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 23), \ + (u32 *)&ipa_reg_save.ipa.pipes[23].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 24), \ + (u32 *)&ipa_reg_save.ipa.pipes[24].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 25), \ + (u32 *)&ipa_reg_save.ipa.pipes[25].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 26), \ + (u32 *)&ipa_reg_save.ipa.pipes[26].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 27), \ + (u32 *)&ipa_reg_save.ipa.pipes[27].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 28), \ + (u32 *)&ipa_reg_save.ipa.pipes[28].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 29), \ + (u32 *)&ipa_reg_save.ipa.pipes[29].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 30), \ + (u32 *)&ipa_reg_save.ipa.pipes[30].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 31), \ + (u32 *)&ipa_reg_save.ipa.pipes[31].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 32), \ + (u32 *)&ipa_reg_save.ipa.pipes[32].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 33), \ + (u32 *)&ipa_reg_save.ipa.pipes[33].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 34), \ + (u32 *)&ipa_reg_save.ipa.pipes[34].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 35), \ + (u32 *)&ipa_reg_save.ipa.pipes[35].endp.var_name, \ + GEN_REG_ATTR(reg_name) } + +/* + * Macro to define a particular register cfg entry for the remaining + * pipe indexed register. In Stingray case we don't have extra + * endpoints so it is intentially empty + */ +#define IPA_HW_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(REG_NAME, VAR_NAME) \ + { 0, 0 } + +/* + * Macro to set the active flag for all active pipe indexed register + * In Stingray case we don't have extra endpoints so it is intentially + * empty + */ +#define IPA_HW_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA_ACTIVE() \ + do { \ + } while (0) + +#endif /* #if !defined(_IPA_HW_COMMON_EX_H_) */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.0/ipa_hwio.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.0/ipa_hwio.h new file mode 100644 index 0000000000..6200223dd2 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.0/ipa_hwio.h @@ -0,0 +1,16822 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ + +#ifndef __IPA_HWIO_H__ +#define __IPA_HWIO_H__ +/** + @file ipa_hwio.h + @brief Auto-generated HWIO interface include file. + + This file contains HWIO register definitions for the following modules: + IPA.* + + 'Include' filters applied: + 'Exclude' filters applied: RESERVED DUMMY + + Attribute definitions for the HWIO_*_ATTR macros are as follows: + 0x0: Command register + 0x1: Read-Only + 0x2: Write-Only + 0x3: Read/Write +*/ + +/*---------------------------------------------------------------------------- + * MODULE: IPA_UC_IPA_UC + *--------------------------------------------------------------------------*/ + +#define IPA_UC_IPA_UC_REG_BASE (IPA_0_IPA_WRAPPER_BASE + 0x001a0000) +#define IPA_UC_IPA_UC_REG_BASE_PHYS (IPA_0_IPA_WRAPPER_BASE_PHYS + 0x001a0000) +#define IPA_UC_IPA_UC_REG_BASE_OFFS 0x001a0000 + +/*---------------------------------------------------------------------------- + * MODULE: IPA_UC_IPA_UC_RAM + *--------------------------------------------------------------------------*/ + +#define IPA_UC_IPA_UC_RAM_REG_BASE (IPA_0_IPA_WRAPPER_BASE + 0x001a0000) +#define IPA_UC_IPA_UC_RAM_REG_BASE_PHYS (IPA_0_IPA_WRAPPER_BASE_PHYS + 0x001a0000) +#define IPA_UC_IPA_UC_RAM_REG_BASE_OFFS 0x001a0000 + +#define HWIO_IPA_UC_IRAM_START_ADDR (IPA_UC_IPA_UC_RAM_REG_BASE + 0x00000000) +#define HWIO_IPA_UC_IRAM_START_PHYS (IPA_UC_IPA_UC_RAM_REG_BASE_PHYS + 0x00000000) +#define HWIO_IPA_UC_IRAM_START_OFFS (IPA_UC_IPA_UC_RAM_REG_BASE_OFFS + 0x00000000) +#define HWIO_IPA_UC_IRAM_START_RMSK 0xffffffff +#define HWIO_IPA_UC_IRAM_START_ATTR 0x3 +#define HWIO_IPA_UC_IRAM_START_IN \ + in_dword_masked(HWIO_IPA_UC_IRAM_START_ADDR, HWIO_IPA_UC_IRAM_START_RMSK) +#define HWIO_IPA_UC_IRAM_START_INM(m) \ + in_dword_masked(HWIO_IPA_UC_IRAM_START_ADDR, m) +#define HWIO_IPA_UC_IRAM_START_OUT(v) \ + out_dword(HWIO_IPA_UC_IRAM_START_ADDR,v) +#define HWIO_IPA_UC_IRAM_START_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_IRAM_START_ADDR,m,v,HWIO_IPA_UC_IRAM_START_IN) +#define HWIO_IPA_UC_IRAM_START_DATA_BMSK 0xffffffff +#define HWIO_IPA_UC_IRAM_START_DATA_SHFT 0x0 + +#define HWIO_IPA_UC_DRAM_START_ADDR (IPA_UC_IPA_UC_RAM_REG_BASE + 0x00008000) +#define HWIO_IPA_UC_DRAM_START_PHYS (IPA_UC_IPA_UC_RAM_REG_BASE_PHYS + 0x00008000) +#define HWIO_IPA_UC_DRAM_START_OFFS (IPA_UC_IPA_UC_RAM_REG_BASE_OFFS + 0x00008000) +#define HWIO_IPA_UC_DRAM_START_RMSK 0xffffffff +#define HWIO_IPA_UC_DRAM_START_ATTR 0x3 +#define HWIO_IPA_UC_DRAM_START_IN \ + in_dword_masked(HWIO_IPA_UC_DRAM_START_ADDR, HWIO_IPA_UC_DRAM_START_RMSK) +#define HWIO_IPA_UC_DRAM_START_INM(m) \ + in_dword_masked(HWIO_IPA_UC_DRAM_START_ADDR, m) +#define HWIO_IPA_UC_DRAM_START_OUT(v) \ + out_dword(HWIO_IPA_UC_DRAM_START_ADDR,v) +#define HWIO_IPA_UC_DRAM_START_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_DRAM_START_ADDR,m,v,HWIO_IPA_UC_DRAM_START_IN) +#define HWIO_IPA_UC_DRAM_START_DATA_BMSK 0xffffffff +#define HWIO_IPA_UC_DRAM_START_DATA_SHFT 0x0 + +/*---------------------------------------------------------------------------- + * MODULE: IPA_UC_IPA_UC_PER + *--------------------------------------------------------------------------*/ + +#define IPA_UC_IPA_UC_PER_REG_BASE (IPA_0_IPA_WRAPPER_BASE + 0x001c0000) +#define IPA_UC_IPA_UC_PER_REG_BASE_PHYS (IPA_0_IPA_WRAPPER_BASE_PHYS + 0x001c0000) +#define IPA_UC_IPA_UC_PER_REG_BASE_OFFS 0x001c0000 + +#define HWIO_IPA_UC_STATUS_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000000) +#define HWIO_IPA_UC_STATUS_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000000) +#define HWIO_IPA_UC_STATUS_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000000) +#define HWIO_IPA_UC_STATUS_RMSK 0xf +#define HWIO_IPA_UC_STATUS_ATTR 0x1 +#define HWIO_IPA_UC_STATUS_IN \ + in_dword_masked(HWIO_IPA_UC_STATUS_ADDR, HWIO_IPA_UC_STATUS_RMSK) +#define HWIO_IPA_UC_STATUS_INM(m) \ + in_dword_masked(HWIO_IPA_UC_STATUS_ADDR, m) +#define HWIO_IPA_UC_STATUS_UC_ENABLE_BMSK 0x8 +#define HWIO_IPA_UC_STATUS_UC_ENABLE_SHFT 0x3 +#define HWIO_IPA_UC_STATUS_LOCKUP_BMSK 0x4 +#define HWIO_IPA_UC_STATUS_LOCKUP_SHFT 0x2 +#define HWIO_IPA_UC_STATUS_SLEEP_BMSK 0x2 +#define HWIO_IPA_UC_STATUS_SLEEP_SHFT 0x1 +#define HWIO_IPA_UC_STATUS_SLEEPDEEP_BMSK 0x1 +#define HWIO_IPA_UC_STATUS_SLEEPDEEP_SHFT 0x0 + +#define HWIO_IPA_UC_CONTROL_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000004) +#define HWIO_IPA_UC_CONTROL_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000004) +#define HWIO_IPA_UC_CONTROL_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000004) +#define HWIO_IPA_UC_CONTROL_RMSK 0x9000ffe +#define HWIO_IPA_UC_CONTROL_ATTR 0x3 +#define HWIO_IPA_UC_CONTROL_IN \ + in_dword_masked(HWIO_IPA_UC_CONTROL_ADDR, HWIO_IPA_UC_CONTROL_RMSK) +#define HWIO_IPA_UC_CONTROL_INM(m) \ + in_dword_masked(HWIO_IPA_UC_CONTROL_ADDR, m) +#define HWIO_IPA_UC_CONTROL_OUT(v) \ + out_dword(HWIO_IPA_UC_CONTROL_ADDR,v) +#define HWIO_IPA_UC_CONTROL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_CONTROL_ADDR,m,v,HWIO_IPA_UC_CONTROL_IN) +#define HWIO_IPA_UC_CONTROL_UC_RAM_RD_CLI_CACHE_DIS_BMSK 0x8000000 +#define HWIO_IPA_UC_CONTROL_UC_RAM_RD_CLI_CACHE_DIS_SHFT 0x1b +#define HWIO_IPA_UC_CONTROL_WARMBOOT_DIS_BMSK 0x1000000 +#define HWIO_IPA_UC_CONTROL_WARMBOOT_DIS_SHFT 0x18 +#define HWIO_IPA_UC_CONTROL_MBOX_DIS_BMSK 0xff0 +#define HWIO_IPA_UC_CONTROL_MBOX_DIS_SHFT 0x4 +#define HWIO_IPA_UC_CONTROL_UC_CLOCK_GATING_DIS_BMSK 0x8 +#define HWIO_IPA_UC_CONTROL_UC_CLOCK_GATING_DIS_SHFT 0x3 +#define HWIO_IPA_UC_CONTROL_QMB_SNOC_BYPASS_DIS_BMSK 0x4 +#define HWIO_IPA_UC_CONTROL_QMB_SNOC_BYPASS_DIS_SHFT 0x2 +#define HWIO_IPA_UC_CONTROL_UC_DSMODE_BMSK 0x2 +#define HWIO_IPA_UC_CONTROL_UC_DSMODE_SHFT 0x1 + +#define HWIO_IPA_UC_SYS_BUS_ATTRIB_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000010) +#define HWIO_IPA_UC_SYS_BUS_ATTRIB_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000010) +#define HWIO_IPA_UC_SYS_BUS_ATTRIB_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000010) +#define HWIO_IPA_UC_SYS_BUS_ATTRIB_RMSK 0x1117 +#define HWIO_IPA_UC_SYS_BUS_ATTRIB_ATTR 0x3 +#define HWIO_IPA_UC_SYS_BUS_ATTRIB_IN \ + in_dword_masked(HWIO_IPA_UC_SYS_BUS_ATTRIB_ADDR, HWIO_IPA_UC_SYS_BUS_ATTRIB_RMSK) +#define HWIO_IPA_UC_SYS_BUS_ATTRIB_INM(m) \ + in_dword_masked(HWIO_IPA_UC_SYS_BUS_ATTRIB_ADDR, m) +#define HWIO_IPA_UC_SYS_BUS_ATTRIB_OUT(v) \ + out_dword(HWIO_IPA_UC_SYS_BUS_ATTRIB_ADDR,v) +#define HWIO_IPA_UC_SYS_BUS_ATTRIB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_SYS_BUS_ATTRIB_ADDR,m,v,HWIO_IPA_UC_SYS_BUS_ATTRIB_IN) +#define HWIO_IPA_UC_SYS_BUS_ATTRIB_SHARED_BMSK 0x1000 +#define HWIO_IPA_UC_SYS_BUS_ATTRIB_SHARED_SHFT 0xc +#define HWIO_IPA_UC_SYS_BUS_ATTRIB_INNERSHARED_BMSK 0x100 +#define HWIO_IPA_UC_SYS_BUS_ATTRIB_INNERSHARED_SHFT 0x8 +#define HWIO_IPA_UC_SYS_BUS_ATTRIB_NOALLOCATE_BMSK 0x10 +#define HWIO_IPA_UC_SYS_BUS_ATTRIB_NOALLOCATE_SHFT 0x4 +#define HWIO_IPA_UC_SYS_BUS_ATTRIB_MEMTYPE_BMSK 0x7 +#define HWIO_IPA_UC_SYS_BUS_ATTRIB_MEMTYPE_SHFT 0x0 +#define HWIO_IPA_UC_SYS_BUS_ATTRIB_MEMTYPE_STRONGLY_ORDERED_FVAL 0x0 +#define HWIO_IPA_UC_SYS_BUS_ATTRIB_MEMTYPE_DEVICE_FVAL 0x1 +#define HWIO_IPA_UC_SYS_BUS_ATTRIB_MEMTYPE_NON_CACHEABLE_FVAL 0x2 +#define HWIO_IPA_UC_SYS_BUS_ATTRIB_MEMTYPE_COPYBACK_WRITEALLOCATE_FVAL 0x3 +#define HWIO_IPA_UC_SYS_BUS_ATTRIB_MEMTYPE_WRITETHROUGH_NOALLOCATE_FVAL 0x6 +#define HWIO_IPA_UC_SYS_BUS_ATTRIB_MEMTYPE_COPYBACK_NOALLOCATE_FVAL 0x7 + +#define HWIO_IPA_UC_PEND_IRQ_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000014) +#define HWIO_IPA_UC_PEND_IRQ_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000014) +#define HWIO_IPA_UC_PEND_IRQ_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000014) +#define HWIO_IPA_UC_PEND_IRQ_RMSK 0xffffffff +#define HWIO_IPA_UC_PEND_IRQ_ATTR 0x1 +#define HWIO_IPA_UC_PEND_IRQ_IN \ + in_dword_masked(HWIO_IPA_UC_PEND_IRQ_ADDR, HWIO_IPA_UC_PEND_IRQ_RMSK) +#define HWIO_IPA_UC_PEND_IRQ_INM(m) \ + in_dword_masked(HWIO_IPA_UC_PEND_IRQ_ADDR, m) +#define HWIO_IPA_UC_PEND_IRQ_PEND_IRQ_BMSK 0xffffffff +#define HWIO_IPA_UC_PEND_IRQ_PEND_IRQ_SHFT 0x0 + +#define HWIO_IPA_UC_TRACE_BUFFER_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000018) +#define HWIO_IPA_UC_TRACE_BUFFER_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000018) +#define HWIO_IPA_UC_TRACE_BUFFER_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000018) +#define HWIO_IPA_UC_TRACE_BUFFER_RMSK 0xffffffff +#define HWIO_IPA_UC_TRACE_BUFFER_ATTR 0x1 +#define HWIO_IPA_UC_TRACE_BUFFER_IN \ + in_dword_masked(HWIO_IPA_UC_TRACE_BUFFER_ADDR, HWIO_IPA_UC_TRACE_BUFFER_RMSK) +#define HWIO_IPA_UC_TRACE_BUFFER_INM(m) \ + in_dword_masked(HWIO_IPA_UC_TRACE_BUFFER_ADDR, m) +#define HWIO_IPA_UC_TRACE_BUFFER_TRACE_BUFFER_BMSK 0xffffffff +#define HWIO_IPA_UC_TRACE_BUFFER_TRACE_BUFFER_SHFT 0x0 + +#define HWIO_IPA_UC_PC_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x0000001c) +#define HWIO_IPA_UC_PC_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x0000001c) +#define HWIO_IPA_UC_PC_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x0000001c) +#define HWIO_IPA_UC_PC_RMSK 0xffffffff +#define HWIO_IPA_UC_PC_ATTR 0x1 +#define HWIO_IPA_UC_PC_IN \ + in_dword_masked(HWIO_IPA_UC_PC_ADDR, HWIO_IPA_UC_PC_RMSK) +#define HWIO_IPA_UC_PC_INM(m) \ + in_dword_masked(HWIO_IPA_UC_PC_ADDR, m) +#define HWIO_IPA_UC_PC_PC_BMSK 0xffffffff +#define HWIO_IPA_UC_PC_PC_SHFT 0x0 + +#define HWIO_IPA_UC_VUIC_INT_ADDRESS_LSB_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000024) +#define HWIO_IPA_UC_VUIC_INT_ADDRESS_LSB_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000024) +#define HWIO_IPA_UC_VUIC_INT_ADDRESS_LSB_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000024) +#define HWIO_IPA_UC_VUIC_INT_ADDRESS_LSB_RMSK 0xffffffff +#define HWIO_IPA_UC_VUIC_INT_ADDRESS_LSB_ATTR 0x1 +#define HWIO_IPA_UC_VUIC_INT_ADDRESS_LSB_IN \ + in_dword_masked(HWIO_IPA_UC_VUIC_INT_ADDRESS_LSB_ADDR, HWIO_IPA_UC_VUIC_INT_ADDRESS_LSB_RMSK) +#define HWIO_IPA_UC_VUIC_INT_ADDRESS_LSB_INM(m) \ + in_dword_masked(HWIO_IPA_UC_VUIC_INT_ADDRESS_LSB_ADDR, m) +#define HWIO_IPA_UC_VUIC_INT_ADDRESS_LSB_ADDRRESS_BMSK 0xffffffff +#define HWIO_IPA_UC_VUIC_INT_ADDRESS_LSB_ADDRRESS_SHFT 0x0 + +#define HWIO_IPA_UC_VUIC_INT_ADDRESS_MSB_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000028) +#define HWIO_IPA_UC_VUIC_INT_ADDRESS_MSB_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000028) +#define HWIO_IPA_UC_VUIC_INT_ADDRESS_MSB_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000028) +#define HWIO_IPA_UC_VUIC_INT_ADDRESS_MSB_RMSK 0x1ff +#define HWIO_IPA_UC_VUIC_INT_ADDRESS_MSB_ATTR 0x1 +#define HWIO_IPA_UC_VUIC_INT_ADDRESS_MSB_IN \ + in_dword_masked(HWIO_IPA_UC_VUIC_INT_ADDRESS_MSB_ADDR, HWIO_IPA_UC_VUIC_INT_ADDRESS_MSB_RMSK) +#define HWIO_IPA_UC_VUIC_INT_ADDRESS_MSB_INM(m) \ + in_dword_masked(HWIO_IPA_UC_VUIC_INT_ADDRESS_MSB_ADDR, m) +#define HWIO_IPA_UC_VUIC_INT_ADDRESS_MSB_ADDRRESS_BMSK 0x1ff +#define HWIO_IPA_UC_VUIC_INT_ADDRESS_MSB_ADDRRESS_SHFT 0x0 + +#define HWIO_IPA_UC_QMB_SYS_ADDR_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000100) +#define HWIO_IPA_UC_QMB_SYS_ADDR_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000100) +#define HWIO_IPA_UC_QMB_SYS_ADDR_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000100) +#define HWIO_IPA_UC_QMB_SYS_ADDR_RMSK 0xffffffff +#define HWIO_IPA_UC_QMB_SYS_ADDR_ATTR 0x3 +#define HWIO_IPA_UC_QMB_SYS_ADDR_IN \ + in_dword_masked(HWIO_IPA_UC_QMB_SYS_ADDR_ADDR, HWIO_IPA_UC_QMB_SYS_ADDR_RMSK) +#define HWIO_IPA_UC_QMB_SYS_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_UC_QMB_SYS_ADDR_ADDR, m) +#define HWIO_IPA_UC_QMB_SYS_ADDR_OUT(v) \ + out_dword(HWIO_IPA_UC_QMB_SYS_ADDR_ADDR,v) +#define HWIO_IPA_UC_QMB_SYS_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_QMB_SYS_ADDR_ADDR,m,v,HWIO_IPA_UC_QMB_SYS_ADDR_IN) +#define HWIO_IPA_UC_QMB_SYS_ADDR_ADDR_BMSK 0xffffffff +#define HWIO_IPA_UC_QMB_SYS_ADDR_ADDR_SHFT 0x0 + +#define HWIO_IPA_UC_QMB_SYS_ADDR_MSB_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000104) +#define HWIO_IPA_UC_QMB_SYS_ADDR_MSB_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000104) +#define HWIO_IPA_UC_QMB_SYS_ADDR_MSB_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000104) +#define HWIO_IPA_UC_QMB_SYS_ADDR_MSB_RMSK 0xffffffff +#define HWIO_IPA_UC_QMB_SYS_ADDR_MSB_ATTR 0x3 +#define HWIO_IPA_UC_QMB_SYS_ADDR_MSB_IN \ + in_dword_masked(HWIO_IPA_UC_QMB_SYS_ADDR_MSB_ADDR, HWIO_IPA_UC_QMB_SYS_ADDR_MSB_RMSK) +#define HWIO_IPA_UC_QMB_SYS_ADDR_MSB_INM(m) \ + in_dword_masked(HWIO_IPA_UC_QMB_SYS_ADDR_MSB_ADDR, m) +#define HWIO_IPA_UC_QMB_SYS_ADDR_MSB_OUT(v) \ + out_dword(HWIO_IPA_UC_QMB_SYS_ADDR_MSB_ADDR,v) +#define HWIO_IPA_UC_QMB_SYS_ADDR_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_QMB_SYS_ADDR_MSB_ADDR,m,v,HWIO_IPA_UC_QMB_SYS_ADDR_MSB_IN) +#define HWIO_IPA_UC_QMB_SYS_ADDR_MSB_ADDR_MSB_BMSK 0xffffffff +#define HWIO_IPA_UC_QMB_SYS_ADDR_MSB_ADDR_MSB_SHFT 0x0 + +#define HWIO_IPA_UC_QMB_LOCAL_ADDR_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000108) +#define HWIO_IPA_UC_QMB_LOCAL_ADDR_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000108) +#define HWIO_IPA_UC_QMB_LOCAL_ADDR_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000108) +#define HWIO_IPA_UC_QMB_LOCAL_ADDR_RMSK 0x3ffff +#define HWIO_IPA_UC_QMB_LOCAL_ADDR_ATTR 0x3 +#define HWIO_IPA_UC_QMB_LOCAL_ADDR_IN \ + in_dword_masked(HWIO_IPA_UC_QMB_LOCAL_ADDR_ADDR, HWIO_IPA_UC_QMB_LOCAL_ADDR_RMSK) +#define HWIO_IPA_UC_QMB_LOCAL_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_UC_QMB_LOCAL_ADDR_ADDR, m) +#define HWIO_IPA_UC_QMB_LOCAL_ADDR_OUT(v) \ + out_dword(HWIO_IPA_UC_QMB_LOCAL_ADDR_ADDR,v) +#define HWIO_IPA_UC_QMB_LOCAL_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_QMB_LOCAL_ADDR_ADDR,m,v,HWIO_IPA_UC_QMB_LOCAL_ADDR_IN) +#define HWIO_IPA_UC_QMB_LOCAL_ADDR_ADDR_BMSK 0x3ffff +#define HWIO_IPA_UC_QMB_LOCAL_ADDR_ADDR_SHFT 0x0 + +#define HWIO_IPA_UC_QMB_LENGTH_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x0000010c) +#define HWIO_IPA_UC_QMB_LENGTH_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x0000010c) +#define HWIO_IPA_UC_QMB_LENGTH_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x0000010c) +#define HWIO_IPA_UC_QMB_LENGTH_RMSK 0xffff +#define HWIO_IPA_UC_QMB_LENGTH_ATTR 0x3 +#define HWIO_IPA_UC_QMB_LENGTH_IN \ + in_dword_masked(HWIO_IPA_UC_QMB_LENGTH_ADDR, HWIO_IPA_UC_QMB_LENGTH_RMSK) +#define HWIO_IPA_UC_QMB_LENGTH_INM(m) \ + in_dword_masked(HWIO_IPA_UC_QMB_LENGTH_ADDR, m) +#define HWIO_IPA_UC_QMB_LENGTH_OUT(v) \ + out_dword(HWIO_IPA_UC_QMB_LENGTH_ADDR,v) +#define HWIO_IPA_UC_QMB_LENGTH_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_QMB_LENGTH_ADDR,m,v,HWIO_IPA_UC_QMB_LENGTH_IN) +#define HWIO_IPA_UC_QMB_LENGTH_LENGTH_BMSK 0xffff +#define HWIO_IPA_UC_QMB_LENGTH_LENGTH_SHFT 0x0 + +#define HWIO_IPA_UC_QMB_TRIGGER_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000110) +#define HWIO_IPA_UC_QMB_TRIGGER_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000110) +#define HWIO_IPA_UC_QMB_TRIGGER_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000110) +#define HWIO_IPA_UC_QMB_TRIGGER_RMSK 0xffffffff +#define HWIO_IPA_UC_QMB_TRIGGER_ATTR 0x2 +#define HWIO_IPA_UC_QMB_TRIGGER_OUT(v) \ + out_dword(HWIO_IPA_UC_QMB_TRIGGER_ADDR,v) +#define HWIO_IPA_UC_QMB_TRIGGER_RSV_BMSK 0xffffffff +#define HWIO_IPA_UC_QMB_TRIGGER_RSV_SHFT 0x0 + +#define HWIO_IPA_UC_QMB_COMMAND_ATTR_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000114) +#define HWIO_IPA_UC_QMB_COMMAND_ATTR_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000114) +#define HWIO_IPA_UC_QMB_COMMAND_ATTR_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000114) +#define HWIO_IPA_UC_QMB_COMMAND_ATTR_RMSK 0x7ff003f +#define HWIO_IPA_UC_QMB_COMMAND_ATTR_ATTR 0x3 +#define HWIO_IPA_UC_QMB_COMMAND_ATTR_IN \ + in_dword_masked(HWIO_IPA_UC_QMB_COMMAND_ATTR_ADDR, HWIO_IPA_UC_QMB_COMMAND_ATTR_RMSK) +#define HWIO_IPA_UC_QMB_COMMAND_ATTR_INM(m) \ + in_dword_masked(HWIO_IPA_UC_QMB_COMMAND_ATTR_ADDR, m) +#define HWIO_IPA_UC_QMB_COMMAND_ATTR_OUT(v) \ + out_dword(HWIO_IPA_UC_QMB_COMMAND_ATTR_ADDR,v) +#define HWIO_IPA_UC_QMB_COMMAND_ATTR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_QMB_COMMAND_ATTR_ADDR,m,v,HWIO_IPA_UC_QMB_COMMAND_ATTR_IN) +#define HWIO_IPA_UC_QMB_COMMAND_ATTR_USER_BMSK 0x7ff0000 +#define HWIO_IPA_UC_QMB_COMMAND_ATTR_USER_SHFT 0x10 +#define HWIO_IPA_UC_QMB_COMMAND_ATTR_QUEUE_NUMBER_BMSK 0x20 +#define HWIO_IPA_UC_QMB_COMMAND_ATTR_QUEUE_NUMBER_SHFT 0x5 +#define HWIO_IPA_UC_QMB_COMMAND_ATTR_INTERRUPT_ON_COMPLETION_BMSK 0x10 +#define HWIO_IPA_UC_QMB_COMMAND_ATTR_INTERRUPT_ON_COMPLETION_SHFT 0x4 +#define HWIO_IPA_UC_QMB_COMMAND_ATTR_SYNC_BMSK 0x8 +#define HWIO_IPA_UC_QMB_COMMAND_ATTR_SYNC_SHFT 0x3 +#define HWIO_IPA_UC_QMB_COMMAND_ATTR_WAIT_FOR_RESPONSE_MODE_BMSK 0x4 +#define HWIO_IPA_UC_QMB_COMMAND_ATTR_WAIT_FOR_RESPONSE_MODE_SHFT 0x2 +#define HWIO_IPA_UC_QMB_COMMAND_ATTR_INORDER_BMSK 0x2 +#define HWIO_IPA_UC_QMB_COMMAND_ATTR_INORDER_SHFT 0x1 +#define HWIO_IPA_UC_QMB_COMMAND_ATTR_DIRECTION_BMSK 0x1 +#define HWIO_IPA_UC_QMB_COMMAND_ATTR_DIRECTION_SHFT 0x0 + +#define HWIO_IPA_UC_QMB_COMMAND_UCTAG_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000118) +#define HWIO_IPA_UC_QMB_COMMAND_UCTAG_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000118) +#define HWIO_IPA_UC_QMB_COMMAND_UCTAG_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000118) +#define HWIO_IPA_UC_QMB_COMMAND_UCTAG_RMSK 0x3ffff +#define HWIO_IPA_UC_QMB_COMMAND_UCTAG_ATTR 0x3 +#define HWIO_IPA_UC_QMB_COMMAND_UCTAG_IN \ + in_dword_masked(HWIO_IPA_UC_QMB_COMMAND_UCTAG_ADDR, HWIO_IPA_UC_QMB_COMMAND_UCTAG_RMSK) +#define HWIO_IPA_UC_QMB_COMMAND_UCTAG_INM(m) \ + in_dword_masked(HWIO_IPA_UC_QMB_COMMAND_UCTAG_ADDR, m) +#define HWIO_IPA_UC_QMB_COMMAND_UCTAG_OUT(v) \ + out_dword(HWIO_IPA_UC_QMB_COMMAND_UCTAG_ADDR,v) +#define HWIO_IPA_UC_QMB_COMMAND_UCTAG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_QMB_COMMAND_UCTAG_ADDR,m,v,HWIO_IPA_UC_QMB_COMMAND_UCTAG_IN) +#define HWIO_IPA_UC_QMB_COMMAND_UCTAG_UCTAG_BMSK 0x3ffff +#define HWIO_IPA_UC_QMB_COMMAND_UCTAG_UCTAG_SHFT 0x0 + +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_n_ADDR(n) (IPA_UC_IPA_UC_PER_REG_BASE + 0x0000011c + 0x4 * (n)) +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_n_PHYS(n) (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x0000011c + 0x4 * (n)) +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_n_OFFS(n) (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x0000011c + 0x4 * (n)) +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_n_RMSK 0xc7ffffff +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_n_MAXn 1 +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_n_ATTR 0x1 +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_n_INI(n) \ + in_dword_masked(HWIO_IPA_UC_QMB_COMPLETED_FIFO_n_ADDR(n), HWIO_IPA_UC_QMB_COMPLETED_FIFO_n_RMSK) +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_UC_QMB_COMPLETED_FIFO_n_ADDR(n), mask) +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_n_FULL_BMSK 0x80000000 +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_n_FULL_SHFT 0x1f +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_n_EMPTY_BMSK 0x40000000 +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_n_EMPTY_SHFT 0x1e +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_n_ERROR_BMSK 0x4000000 +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_n_ERROR_SHFT 0x1a +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_n_FIFO_CNT_BMSK 0x3c00000 +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_n_FIFO_CNT_SHFT 0x16 +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_n_FIFO_SIZE_BMSK 0x3c0000 +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_n_FIFO_SIZE_SHFT 0x12 +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_n_UCTAG_BMSK 0x3ffff +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_n_UCTAG_SHFT 0x0 + +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_PEEK_n_ADDR(n) (IPA_UC_IPA_UC_PER_REG_BASE + 0x0000012c + 0x4 * (n)) +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_PEEK_n_PHYS(n) (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x0000012c + 0x4 * (n)) +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_PEEK_n_OFFS(n) (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x0000012c + 0x4 * (n)) +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_PEEK_n_RMSK 0xc7ffffff +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_PEEK_n_MAXn 1 +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_PEEK_n_ATTR 0x1 +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_PEEK_n_INI(n) \ + in_dword_masked(HWIO_IPA_UC_QMB_COMPLETED_FIFO_PEEK_n_ADDR(n), HWIO_IPA_UC_QMB_COMPLETED_FIFO_PEEK_n_RMSK) +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_PEEK_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_UC_QMB_COMPLETED_FIFO_PEEK_n_ADDR(n), mask) +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_PEEK_n_FULL_BMSK 0x80000000 +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_PEEK_n_FULL_SHFT 0x1f +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_PEEK_n_EMPTY_BMSK 0x40000000 +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_PEEK_n_EMPTY_SHFT 0x1e +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_PEEK_n_ERROR_BMSK 0x4000000 +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_PEEK_n_ERROR_SHFT 0x1a +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_PEEK_n_FIFO_CNT_BMSK 0x3c00000 +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_PEEK_n_FIFO_CNT_SHFT 0x16 +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_PEEK_n_FIFO_SIZE_BMSK 0x3c0000 +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_PEEK_n_FIFO_SIZE_SHFT 0x12 +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_PEEK_n_UCTAG_BMSK 0x3ffff +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_PEEK_n_UCTAG_SHFT 0x0 + +#define HWIO_IPA_UC_QMB_CMD_FIFO_STATUS_n_ADDR(n) (IPA_UC_IPA_UC_PER_REG_BASE + 0x0000013c + 0x4 * (n)) +#define HWIO_IPA_UC_QMB_CMD_FIFO_STATUS_n_PHYS(n) (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x0000013c + 0x4 * (n)) +#define HWIO_IPA_UC_QMB_CMD_FIFO_STATUS_n_OFFS(n) (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x0000013c + 0x4 * (n)) +#define HWIO_IPA_UC_QMB_CMD_FIFO_STATUS_n_RMSK 0x300ff +#define HWIO_IPA_UC_QMB_CMD_FIFO_STATUS_n_MAXn 1 +#define HWIO_IPA_UC_QMB_CMD_FIFO_STATUS_n_ATTR 0x1 +#define HWIO_IPA_UC_QMB_CMD_FIFO_STATUS_n_INI(n) \ + in_dword_masked(HWIO_IPA_UC_QMB_CMD_FIFO_STATUS_n_ADDR(n), HWIO_IPA_UC_QMB_CMD_FIFO_STATUS_n_RMSK) +#define HWIO_IPA_UC_QMB_CMD_FIFO_STATUS_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_UC_QMB_CMD_FIFO_STATUS_n_ADDR(n), mask) +#define HWIO_IPA_UC_QMB_CMD_FIFO_STATUS_n_FULL_BMSK 0x20000 +#define HWIO_IPA_UC_QMB_CMD_FIFO_STATUS_n_FULL_SHFT 0x11 +#define HWIO_IPA_UC_QMB_CMD_FIFO_STATUS_n_EMPTY_BMSK 0x10000 +#define HWIO_IPA_UC_QMB_CMD_FIFO_STATUS_n_EMPTY_SHFT 0x10 +#define HWIO_IPA_UC_QMB_CMD_FIFO_STATUS_n_FIFO_CNT_BMSK 0xf0 +#define HWIO_IPA_UC_QMB_CMD_FIFO_STATUS_n_FIFO_CNT_SHFT 0x4 +#define HWIO_IPA_UC_QMB_CMD_FIFO_STATUS_n_FIFO_SIZE_BMSK 0xf +#define HWIO_IPA_UC_QMB_CMD_FIFO_STATUS_n_FIFO_SIZE_SHFT 0x0 + +#define HWIO_IPA_UC_QMB_SYNC_STATUS_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000150) +#define HWIO_IPA_UC_QMB_SYNC_STATUS_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000150) +#define HWIO_IPA_UC_QMB_SYNC_STATUS_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000150) +#define HWIO_IPA_UC_QMB_SYNC_STATUS_RMSK 0x10001 +#define HWIO_IPA_UC_QMB_SYNC_STATUS_ATTR 0x1 +#define HWIO_IPA_UC_QMB_SYNC_STATUS_IN \ + in_dword_masked(HWIO_IPA_UC_QMB_SYNC_STATUS_ADDR, HWIO_IPA_UC_QMB_SYNC_STATUS_RMSK) +#define HWIO_IPA_UC_QMB_SYNC_STATUS_INM(m) \ + in_dword_masked(HWIO_IPA_UC_QMB_SYNC_STATUS_ADDR, m) +#define HWIO_IPA_UC_QMB_SYNC_STATUS_ERROR_QUEUE_1_BMSK 0x10000 +#define HWIO_IPA_UC_QMB_SYNC_STATUS_ERROR_QUEUE_1_SHFT 0x10 +#define HWIO_IPA_UC_QMB_SYNC_STATUS_ERROR_QUEUE_0_BMSK 0x1 +#define HWIO_IPA_UC_QMB_SYNC_STATUS_ERROR_QUEUE_0_SHFT 0x0 + +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000154) +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000154) +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000154) +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_RMSK 0x1117 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_ATTR 0x3 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_IN \ + in_dword_masked(HWIO_IPA_UC_QMB_BUS_ATTRIB_ADDR, HWIO_IPA_UC_QMB_BUS_ATTRIB_RMSK) +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_INM(m) \ + in_dword_masked(HWIO_IPA_UC_QMB_BUS_ATTRIB_ADDR, m) +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_OUT(v) \ + out_dword(HWIO_IPA_UC_QMB_BUS_ATTRIB_ADDR,v) +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_QMB_BUS_ATTRIB_ADDR,m,v,HWIO_IPA_UC_QMB_BUS_ATTRIB_IN) +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_SHARED_BMSK 0x1000 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_SHARED_SHFT 0xc +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_INNERSHARED_BMSK 0x100 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_INNERSHARED_SHFT 0x8 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_NOALLOCATE_BMSK 0x10 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_NOALLOCATE_SHFT 0x4 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_MEMTYPE_BMSK 0x7 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_MEMTYPE_SHFT 0x0 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_MEMTYPE_STRONGLY_ORDERED_FVAL 0x0 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_MEMTYPE_DEVICE_FVAL 0x1 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_MEMTYPE_NON_CACHEABLE_FVAL 0x2 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_MEMTYPE_COPYBACK_WRITEALLOCATE_FVAL 0x3 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_MEMTYPE_WRITETHROUGH_NOALLOCATE_FVAL 0x6 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_MEMTYPE_COPYBACK_NOALLOCATE_FVAL 0x7 + +#define HWIO_IPA_UC_QMB_OUTSTANDING_CFG_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000158) +#define HWIO_IPA_UC_QMB_OUTSTANDING_CFG_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000158) +#define HWIO_IPA_UC_QMB_OUTSTANDING_CFG_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000158) +#define HWIO_IPA_UC_QMB_OUTSTANDING_CFG_RMSK 0xffffff +#define HWIO_IPA_UC_QMB_OUTSTANDING_CFG_ATTR 0x3 +#define HWIO_IPA_UC_QMB_OUTSTANDING_CFG_IN \ + in_dword_masked(HWIO_IPA_UC_QMB_OUTSTANDING_CFG_ADDR, HWIO_IPA_UC_QMB_OUTSTANDING_CFG_RMSK) +#define HWIO_IPA_UC_QMB_OUTSTANDING_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_UC_QMB_OUTSTANDING_CFG_ADDR, m) +#define HWIO_IPA_UC_QMB_OUTSTANDING_CFG_OUT(v) \ + out_dword(HWIO_IPA_UC_QMB_OUTSTANDING_CFG_ADDR,v) +#define HWIO_IPA_UC_QMB_OUTSTANDING_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_QMB_OUTSTANDING_CFG_ADDR,m,v,HWIO_IPA_UC_QMB_OUTSTANDING_CFG_IN) +#define HWIO_IPA_UC_QMB_OUTSTANDING_CFG_MAX_OT_WR_BMSK 0xff0000 +#define HWIO_IPA_UC_QMB_OUTSTANDING_CFG_MAX_OT_WR_SHFT 0x10 +#define HWIO_IPA_UC_QMB_OUTSTANDING_CFG_MAX_OT_RD_BMSK 0xff00 +#define HWIO_IPA_UC_QMB_OUTSTANDING_CFG_MAX_OT_RD_SHFT 0x8 +#define HWIO_IPA_UC_QMB_OUTSTANDING_CFG_MAX_OT_OVERALL_BMSK 0xff +#define HWIO_IPA_UC_QMB_OUTSTANDING_CFG_MAX_OT_OVERALL_SHFT 0x0 + +#define HWIO_IPA_UC_QMB_OUTSTANDING_STATUS_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x0000015c) +#define HWIO_IPA_UC_QMB_OUTSTANDING_STATUS_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x0000015c) +#define HWIO_IPA_UC_QMB_OUTSTANDING_STATUS_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x0000015c) +#define HWIO_IPA_UC_QMB_OUTSTANDING_STATUS_RMSK 0xffffff +#define HWIO_IPA_UC_QMB_OUTSTANDING_STATUS_ATTR 0x1 +#define HWIO_IPA_UC_QMB_OUTSTANDING_STATUS_IN \ + in_dword_masked(HWIO_IPA_UC_QMB_OUTSTANDING_STATUS_ADDR, HWIO_IPA_UC_QMB_OUTSTANDING_STATUS_RMSK) +#define HWIO_IPA_UC_QMB_OUTSTANDING_STATUS_INM(m) \ + in_dword_masked(HWIO_IPA_UC_QMB_OUTSTANDING_STATUS_ADDR, m) +#define HWIO_IPA_UC_QMB_OUTSTANDING_STATUS_CURRENT_OT_WR_BMSK 0xff0000 +#define HWIO_IPA_UC_QMB_OUTSTANDING_STATUS_CURRENT_OT_WR_SHFT 0x10 +#define HWIO_IPA_UC_QMB_OUTSTANDING_STATUS_CURRENT_OT_RD_BMSK 0xff00 +#define HWIO_IPA_UC_QMB_OUTSTANDING_STATUS_CURRENT_OT_RD_SHFT 0x8 +#define HWIO_IPA_UC_QMB_OUTSTANDING_STATUS_CURRENT_OT_OVERALL_BMSK 0xff +#define HWIO_IPA_UC_QMB_OUTSTANDING_STATUS_CURRENT_OT_OVERALL_SHFT 0x0 + +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_EN_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000160) +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_EN_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000160) +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_EN_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000160) +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_EN_RMSK 0x70007 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_EN_ATTR 0x3 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_EN_IN \ + in_dword_masked(HWIO_IPA_UC_QMB_COMP_FIFO_INT_EN_ADDR, HWIO_IPA_UC_QMB_COMP_FIFO_INT_EN_RMSK) +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_EN_INM(m) \ + in_dword_masked(HWIO_IPA_UC_QMB_COMP_FIFO_INT_EN_ADDR, m) +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_EN_OUT(v) \ + out_dword(HWIO_IPA_UC_QMB_COMP_FIFO_INT_EN_ADDR,v) +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_EN_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_QMB_COMP_FIFO_INT_EN_ADDR,m,v,HWIO_IPA_UC_QMB_COMP_FIFO_INT_EN_IN) +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_EN_COMP_FIFO_1_IOC_CMD_BMSK 0x40000 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_EN_COMP_FIFO_1_IOC_CMD_SHFT 0x12 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_EN_COMP_FIFO_1_FULL_BMSK 0x20000 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_EN_COMP_FIFO_1_FULL_SHFT 0x11 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_EN_COMP_FIFO_1_NOT_EMPTY_BMSK 0x10000 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_EN_COMP_FIFO_1_NOT_EMPTY_SHFT 0x10 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_EN_COMP_FIFO_0_IOC_CMD_BMSK 0x4 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_EN_COMP_FIFO_0_IOC_CMD_SHFT 0x2 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_EN_COMP_FIFO_0_FULL_BMSK 0x2 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_EN_COMP_FIFO_0_FULL_SHFT 0x1 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_EN_COMP_FIFO_0_NOT_EMPTY_BMSK 0x1 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_EN_COMP_FIFO_0_NOT_EMPTY_SHFT 0x0 + +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_CLR_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000164) +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_CLR_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000164) +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_CLR_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000164) +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_CLR_RMSK 0x70007 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_CLR_ATTR 0x2 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_CLR_OUT(v) \ + out_dword(HWIO_IPA_UC_QMB_COMP_FIFO_INT_CLR_ADDR,v) +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_CLR_COMP_FIFO_1_IOC_CMD_BMSK 0x40000 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_CLR_COMP_FIFO_1_IOC_CMD_SHFT 0x12 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_CLR_COMP_FIFO_1_FULL_BMSK 0x20000 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_CLR_COMP_FIFO_1_FULL_SHFT 0x11 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_CLR_COMP_FIFO_1_NOT_EMPTY_BMSK 0x10000 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_CLR_COMP_FIFO_1_NOT_EMPTY_SHFT 0x10 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_CLR_COMP_FIFO_0_IOC_CMD_BMSK 0x4 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_CLR_COMP_FIFO_0_IOC_CMD_SHFT 0x2 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_CLR_COMP_FIFO_0_FULL_BMSK 0x2 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_CLR_COMP_FIFO_0_FULL_SHFT 0x1 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_CLR_COMP_FIFO_0_NOT_EMPTY_BMSK 0x1 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_CLR_COMP_FIFO_0_NOT_EMPTY_SHFT 0x0 + +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_STTS_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000168) +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_STTS_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000168) +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_STTS_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000168) +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_STTS_RMSK 0x70007 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_STTS_ATTR 0x1 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_STTS_IN \ + in_dword_masked(HWIO_IPA_UC_QMB_COMP_FIFO_INT_STTS_ADDR, HWIO_IPA_UC_QMB_COMP_FIFO_INT_STTS_RMSK) +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_STTS_INM(m) \ + in_dword_masked(HWIO_IPA_UC_QMB_COMP_FIFO_INT_STTS_ADDR, m) +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_STTS_COMP_FIFO_1_IOC_CMD_BMSK 0x40000 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_STTS_COMP_FIFO_1_IOC_CMD_SHFT 0x12 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_STTS_COMP_FIFO_1_FULL_BMSK 0x20000 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_STTS_COMP_FIFO_1_FULL_SHFT 0x11 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_STTS_COMP_FIFO_1_NOT_EMPTY_BMSK 0x10000 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_STTS_COMP_FIFO_1_NOT_EMPTY_SHFT 0x10 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_STTS_COMP_FIFO_0_IOC_CMD_BMSK 0x4 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_STTS_COMP_FIFO_0_IOC_CMD_SHFT 0x2 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_STTS_COMP_FIFO_0_FULL_BMSK 0x2 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_STTS_COMP_FIFO_0_FULL_SHFT 0x1 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_STTS_COMP_FIFO_0_NOT_EMPTY_BMSK 0x1 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_STTS_COMP_FIFO_0_NOT_EMPTY_SHFT 0x0 + +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_EN_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x0000016c) +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_EN_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x0000016c) +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_EN_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x0000016c) +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_EN_RMSK 0x3 +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_EN_ATTR 0x3 +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_EN_IN \ + in_dword_masked(HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_EN_ADDR, HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_EN_RMSK) +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_EN_INM(m) \ + in_dword_masked(HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_EN_ADDR, m) +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_EN_OUT(v) \ + out_dword(HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_EN_ADDR,v) +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_EN_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_EN_ADDR,m,v,HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_EN_IN) +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_EN_SYNC_COMPLETED_1_BMSK 0x2 +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_EN_SYNC_COMPLETED_1_SHFT 0x1 +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_EN_SYNC_COMPLETED_0_BMSK 0x1 +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_EN_SYNC_COMPLETED_0_SHFT 0x0 + +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_CLR_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000170) +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_CLR_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000170) +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_CLR_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000170) +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_CLR_RMSK 0x3 +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_CLR_ATTR 0x2 +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_CLR_OUT(v) \ + out_dword(HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_CLR_ADDR,v) +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_CLR_SYNC_COMPLETED_1_BMSK 0x2 +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_CLR_SYNC_COMPLETED_1_SHFT 0x1 +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_CLR_SYNC_COMPLETED_0_BMSK 0x1 +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_CLR_SYNC_COMPLETED_0_SHFT 0x0 + +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_STTS_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000174) +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_STTS_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000174) +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_STTS_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000174) +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_STTS_RMSK 0x3 +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_STTS_ATTR 0x1 +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_STTS_IN \ + in_dword_masked(HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_STTS_ADDR, HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_STTS_RMSK) +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_STTS_INM(m) \ + in_dword_masked(HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_STTS_ADDR, m) +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_STTS_SYNC_COMPLETED_1_BMSK 0x2 +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_STTS_SYNC_COMPLETED_1_SHFT 0x1 +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_STTS_SYNC_COMPLETED_0_BMSK 0x1 +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_STTS_SYNC_COMPLETED_0_SHFT 0x0 + +#define HWIO_IPA_UC_MBOX_INT_STTS_n_ADDR(n) (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000200 + 0x10 * (n)) +#define HWIO_IPA_UC_MBOX_INT_STTS_n_PHYS(n) (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000200 + 0x10 * (n)) +#define HWIO_IPA_UC_MBOX_INT_STTS_n_OFFS(n) (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000200 + 0x10 * (n)) +#define HWIO_IPA_UC_MBOX_INT_STTS_n_RMSK 0xffff +#define HWIO_IPA_UC_MBOX_INT_STTS_n_MAXn 7 +#define HWIO_IPA_UC_MBOX_INT_STTS_n_ATTR 0x1 +#define HWIO_IPA_UC_MBOX_INT_STTS_n_INI(n) \ + in_dword_masked(HWIO_IPA_UC_MBOX_INT_STTS_n_ADDR(n), HWIO_IPA_UC_MBOX_INT_STTS_n_RMSK) +#define HWIO_IPA_UC_MBOX_INT_STTS_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_UC_MBOX_INT_STTS_n_ADDR(n), mask) +#define HWIO_IPA_UC_MBOX_INT_STTS_n_IRQ_STATUS_BMSK 0xffff +#define HWIO_IPA_UC_MBOX_INT_STTS_n_IRQ_STATUS_SHFT 0x0 + +#define HWIO_IPA_UC_MBOX_INT_EN_n_ADDR(n) (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000204 + 0x10 * (n)) +#define HWIO_IPA_UC_MBOX_INT_EN_n_PHYS(n) (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000204 + 0x10 * (n)) +#define HWIO_IPA_UC_MBOX_INT_EN_n_OFFS(n) (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000204 + 0x10 * (n)) +#define HWIO_IPA_UC_MBOX_INT_EN_n_RMSK 0xffff +#define HWIO_IPA_UC_MBOX_INT_EN_n_MAXn 7 +#define HWIO_IPA_UC_MBOX_INT_EN_n_ATTR 0x3 +#define HWIO_IPA_UC_MBOX_INT_EN_n_INI(n) \ + in_dword_masked(HWIO_IPA_UC_MBOX_INT_EN_n_ADDR(n), HWIO_IPA_UC_MBOX_INT_EN_n_RMSK) +#define HWIO_IPA_UC_MBOX_INT_EN_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_UC_MBOX_INT_EN_n_ADDR(n), mask) +#define HWIO_IPA_UC_MBOX_INT_EN_n_OUTI(n,val) \ + out_dword(HWIO_IPA_UC_MBOX_INT_EN_n_ADDR(n),val) +#define HWIO_IPA_UC_MBOX_INT_EN_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_UC_MBOX_INT_EN_n_ADDR(n),mask,val,HWIO_IPA_UC_MBOX_INT_EN_n_INI(n)) +#define HWIO_IPA_UC_MBOX_INT_EN_n_IRQ_EN_BMSK 0xffff +#define HWIO_IPA_UC_MBOX_INT_EN_n_IRQ_EN_SHFT 0x0 + +#define HWIO_IPA_UC_MBOX_INT_CLR_n_ADDR(n) (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000208 + 0x10 * (n)) +#define HWIO_IPA_UC_MBOX_INT_CLR_n_PHYS(n) (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000208 + 0x10 * (n)) +#define HWIO_IPA_UC_MBOX_INT_CLR_n_OFFS(n) (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000208 + 0x10 * (n)) +#define HWIO_IPA_UC_MBOX_INT_CLR_n_RMSK 0xffff +#define HWIO_IPA_UC_MBOX_INT_CLR_n_MAXn 7 +#define HWIO_IPA_UC_MBOX_INT_CLR_n_ATTR 0x0 +#define HWIO_IPA_UC_MBOX_INT_CLR_n_OUTI(n,val) \ + out_dword(HWIO_IPA_UC_MBOX_INT_CLR_n_ADDR(n),val) +#define HWIO_IPA_UC_MBOX_INT_CLR_n_IRQ_CLR_BMSK 0xffff +#define HWIO_IPA_UC_MBOX_INT_CLR_n_IRQ_CLR_SHFT 0x0 + +#define HWIO_IPA_UC_IPA_INT_STTS_n_ADDR(n) (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000300 + 0x10 * (n)) +#define HWIO_IPA_UC_IPA_INT_STTS_n_PHYS(n) (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000300 + 0x10 * (n)) +#define HWIO_IPA_UC_IPA_INT_STTS_n_OFFS(n) (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000300 + 0x10 * (n)) +#define HWIO_IPA_UC_IPA_INT_STTS_n_RMSK 0xf +#define HWIO_IPA_UC_IPA_INT_STTS_n_MAXn 3 +#define HWIO_IPA_UC_IPA_INT_STTS_n_ATTR 0x1 +#define HWIO_IPA_UC_IPA_INT_STTS_n_INI(n) \ + in_dword_masked(HWIO_IPA_UC_IPA_INT_STTS_n_ADDR(n), HWIO_IPA_UC_IPA_INT_STTS_n_RMSK) +#define HWIO_IPA_UC_IPA_INT_STTS_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_UC_IPA_INT_STTS_n_ADDR(n), mask) +#define HWIO_IPA_UC_IPA_INT_STTS_n_IRQ_STATUS_BMSK 0xf +#define HWIO_IPA_UC_IPA_INT_STTS_n_IRQ_STATUS_SHFT 0x0 + +#define HWIO_IPA_UC_IPA_INT_EN_n_ADDR(n) (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000304 + 0x10 * (n)) +#define HWIO_IPA_UC_IPA_INT_EN_n_PHYS(n) (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000304 + 0x10 * (n)) +#define HWIO_IPA_UC_IPA_INT_EN_n_OFFS(n) (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000304 + 0x10 * (n)) +#define HWIO_IPA_UC_IPA_INT_EN_n_RMSK 0xf +#define HWIO_IPA_UC_IPA_INT_EN_n_MAXn 3 +#define HWIO_IPA_UC_IPA_INT_EN_n_ATTR 0x3 +#define HWIO_IPA_UC_IPA_INT_EN_n_INI(n) \ + in_dword_masked(HWIO_IPA_UC_IPA_INT_EN_n_ADDR(n), HWIO_IPA_UC_IPA_INT_EN_n_RMSK) +#define HWIO_IPA_UC_IPA_INT_EN_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_UC_IPA_INT_EN_n_ADDR(n), mask) +#define HWIO_IPA_UC_IPA_INT_EN_n_OUTI(n,val) \ + out_dword(HWIO_IPA_UC_IPA_INT_EN_n_ADDR(n),val) +#define HWIO_IPA_UC_IPA_INT_EN_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_UC_IPA_INT_EN_n_ADDR(n),mask,val,HWIO_IPA_UC_IPA_INT_EN_n_INI(n)) +#define HWIO_IPA_UC_IPA_INT_EN_n_IRQ_EN_BMSK 0xf +#define HWIO_IPA_UC_IPA_INT_EN_n_IRQ_EN_SHFT 0x0 + +#define HWIO_IPA_UC_IPA_INT_CLR_n_ADDR(n) (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000308 + 0x10 * (n)) +#define HWIO_IPA_UC_IPA_INT_CLR_n_PHYS(n) (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000308 + 0x10 * (n)) +#define HWIO_IPA_UC_IPA_INT_CLR_n_OFFS(n) (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000308 + 0x10 * (n)) +#define HWIO_IPA_UC_IPA_INT_CLR_n_RMSK 0xf +#define HWIO_IPA_UC_IPA_INT_CLR_n_MAXn 3 +#define HWIO_IPA_UC_IPA_INT_CLR_n_ATTR 0x0 +#define HWIO_IPA_UC_IPA_INT_CLR_n_OUTI(n,val) \ + out_dword(HWIO_IPA_UC_IPA_INT_CLR_n_ADDR(n),val) +#define HWIO_IPA_UC_IPA_INT_CLR_n_IRQ_CLR_BMSK 0xf +#define HWIO_IPA_UC_IPA_INT_CLR_n_IRQ_CLR_SHFT 0x0 + +#define HWIO_IPA_UC_HWEV_INT_STTS_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000400) +#define HWIO_IPA_UC_HWEV_INT_STTS_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000400) +#define HWIO_IPA_UC_HWEV_INT_STTS_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000400) +#define HWIO_IPA_UC_HWEV_INT_STTS_RMSK 0xffffffff +#define HWIO_IPA_UC_HWEV_INT_STTS_ATTR 0x1 +#define HWIO_IPA_UC_HWEV_INT_STTS_IN \ + in_dword_masked(HWIO_IPA_UC_HWEV_INT_STTS_ADDR, HWIO_IPA_UC_HWEV_INT_STTS_RMSK) +#define HWIO_IPA_UC_HWEV_INT_STTS_INM(m) \ + in_dword_masked(HWIO_IPA_UC_HWEV_INT_STTS_ADDR, m) +#define HWIO_IPA_UC_HWEV_INT_STTS_IRQ_STATUS_BMSK 0xffffffff +#define HWIO_IPA_UC_HWEV_INT_STTS_IRQ_STATUS_SHFT 0x0 + +#define HWIO_IPA_UC_HWEV_INT_EN_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000404) +#define HWIO_IPA_UC_HWEV_INT_EN_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000404) +#define HWIO_IPA_UC_HWEV_INT_EN_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000404) +#define HWIO_IPA_UC_HWEV_INT_EN_RMSK 0xffffffff +#define HWIO_IPA_UC_HWEV_INT_EN_ATTR 0x3 +#define HWIO_IPA_UC_HWEV_INT_EN_IN \ + in_dword_masked(HWIO_IPA_UC_HWEV_INT_EN_ADDR, HWIO_IPA_UC_HWEV_INT_EN_RMSK) +#define HWIO_IPA_UC_HWEV_INT_EN_INM(m) \ + in_dword_masked(HWIO_IPA_UC_HWEV_INT_EN_ADDR, m) +#define HWIO_IPA_UC_HWEV_INT_EN_OUT(v) \ + out_dword(HWIO_IPA_UC_HWEV_INT_EN_ADDR,v) +#define HWIO_IPA_UC_HWEV_INT_EN_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_HWEV_INT_EN_ADDR,m,v,HWIO_IPA_UC_HWEV_INT_EN_IN) +#define HWIO_IPA_UC_HWEV_INT_EN_IRQ_EN_BMSK 0xffffffff +#define HWIO_IPA_UC_HWEV_INT_EN_IRQ_EN_SHFT 0x0 + +#define HWIO_IPA_UC_HWEV_INT_CLR_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000408) +#define HWIO_IPA_UC_HWEV_INT_CLR_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000408) +#define HWIO_IPA_UC_HWEV_INT_CLR_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000408) +#define HWIO_IPA_UC_HWEV_INT_CLR_RMSK 0xffffffff +#define HWIO_IPA_UC_HWEV_INT_CLR_ATTR 0x0 +#define HWIO_IPA_UC_HWEV_INT_CLR_OUT(v) \ + out_dword(HWIO_IPA_UC_HWEV_INT_CLR_ADDR,v) +#define HWIO_IPA_UC_HWEV_INT_CLR_IRQ_CLR_BMSK 0xffffffff +#define HWIO_IPA_UC_HWEV_INT_CLR_IRQ_CLR_SHFT 0x0 + +#define HWIO_IPA_UC_SWEV_INT_STTS_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000410) +#define HWIO_IPA_UC_SWEV_INT_STTS_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000410) +#define HWIO_IPA_UC_SWEV_INT_STTS_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000410) +#define HWIO_IPA_UC_SWEV_INT_STTS_RMSK 0xffffffff +#define HWIO_IPA_UC_SWEV_INT_STTS_ATTR 0x1 +#define HWIO_IPA_UC_SWEV_INT_STTS_IN \ + in_dword_masked(HWIO_IPA_UC_SWEV_INT_STTS_ADDR, HWIO_IPA_UC_SWEV_INT_STTS_RMSK) +#define HWIO_IPA_UC_SWEV_INT_STTS_INM(m) \ + in_dword_masked(HWIO_IPA_UC_SWEV_INT_STTS_ADDR, m) +#define HWIO_IPA_UC_SWEV_INT_STTS_IRQ_STATUS_BMSK 0xffffffff +#define HWIO_IPA_UC_SWEV_INT_STTS_IRQ_STATUS_SHFT 0x0 + +#define HWIO_IPA_UC_SWEV_INT_EN_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000414) +#define HWIO_IPA_UC_SWEV_INT_EN_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000414) +#define HWIO_IPA_UC_SWEV_INT_EN_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000414) +#define HWIO_IPA_UC_SWEV_INT_EN_RMSK 0xffffffff +#define HWIO_IPA_UC_SWEV_INT_EN_ATTR 0x3 +#define HWIO_IPA_UC_SWEV_INT_EN_IN \ + in_dword_masked(HWIO_IPA_UC_SWEV_INT_EN_ADDR, HWIO_IPA_UC_SWEV_INT_EN_RMSK) +#define HWIO_IPA_UC_SWEV_INT_EN_INM(m) \ + in_dword_masked(HWIO_IPA_UC_SWEV_INT_EN_ADDR, m) +#define HWIO_IPA_UC_SWEV_INT_EN_OUT(v) \ + out_dword(HWIO_IPA_UC_SWEV_INT_EN_ADDR,v) +#define HWIO_IPA_UC_SWEV_INT_EN_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_SWEV_INT_EN_ADDR,m,v,HWIO_IPA_UC_SWEV_INT_EN_IN) +#define HWIO_IPA_UC_SWEV_INT_EN_IRQ_EN_BMSK 0xffffffff +#define HWIO_IPA_UC_SWEV_INT_EN_IRQ_EN_SHFT 0x0 + +#define HWIO_IPA_UC_SWEV_INT_CLR_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000418) +#define HWIO_IPA_UC_SWEV_INT_CLR_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000418) +#define HWIO_IPA_UC_SWEV_INT_CLR_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000418) +#define HWIO_IPA_UC_SWEV_INT_CLR_RMSK 0xffffffff +#define HWIO_IPA_UC_SWEV_INT_CLR_ATTR 0x0 +#define HWIO_IPA_UC_SWEV_INT_CLR_OUT(v) \ + out_dword(HWIO_IPA_UC_SWEV_INT_CLR_ADDR,v) +#define HWIO_IPA_UC_SWEV_INT_CLR_IRQ_CLR_BMSK 0xffffffff +#define HWIO_IPA_UC_SWEV_INT_CLR_IRQ_CLR_SHFT 0x0 + +#define HWIO_IPA_UC_VUIC_INT_STTS_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x0000041c) +#define HWIO_IPA_UC_VUIC_INT_STTS_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x0000041c) +#define HWIO_IPA_UC_VUIC_INT_STTS_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x0000041c) +#define HWIO_IPA_UC_VUIC_INT_STTS_RMSK 0x1 +#define HWIO_IPA_UC_VUIC_INT_STTS_ATTR 0x1 +#define HWIO_IPA_UC_VUIC_INT_STTS_IN \ + in_dword_masked(HWIO_IPA_UC_VUIC_INT_STTS_ADDR, HWIO_IPA_UC_VUIC_INT_STTS_RMSK) +#define HWIO_IPA_UC_VUIC_INT_STTS_INM(m) \ + in_dword_masked(HWIO_IPA_UC_VUIC_INT_STTS_ADDR, m) +#define HWIO_IPA_UC_VUIC_INT_STTS_IRQ_STATUS_BMSK 0x1 +#define HWIO_IPA_UC_VUIC_INT_STTS_IRQ_STATUS_SHFT 0x0 + +#define HWIO_IPA_UC_VUIC_INT_CLR_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000420) +#define HWIO_IPA_UC_VUIC_INT_CLR_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000420) +#define HWIO_IPA_UC_VUIC_INT_CLR_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000420) +#define HWIO_IPA_UC_VUIC_INT_CLR_RMSK 0x1 +#define HWIO_IPA_UC_VUIC_INT_CLR_ATTR 0x0 +#define HWIO_IPA_UC_VUIC_INT_CLR_OUT(v) \ + out_dword(HWIO_IPA_UC_VUIC_INT_CLR_ADDR,v) +#define HWIO_IPA_UC_VUIC_INT_CLR_IRQ_CLR_BMSK 0x1 +#define HWIO_IPA_UC_VUIC_INT_CLR_IRQ_CLR_SHFT 0x0 + +#define HWIO_IPA_UC_TIMER_CTRL_n_ADDR(n) (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000500 + 0x10 * (n)) +#define HWIO_IPA_UC_TIMER_CTRL_n_PHYS(n) (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000500 + 0x10 * (n)) +#define HWIO_IPA_UC_TIMER_CTRL_n_OFFS(n) (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000500 + 0x10 * (n)) +#define HWIO_IPA_UC_TIMER_CTRL_n_RMSK 0xc17fffff +#define HWIO_IPA_UC_TIMER_CTRL_n_MAXn 3 +#define HWIO_IPA_UC_TIMER_CTRL_n_ATTR 0x3 +#define HWIO_IPA_UC_TIMER_CTRL_n_INI(n) \ + in_dword_masked(HWIO_IPA_UC_TIMER_CTRL_n_ADDR(n), HWIO_IPA_UC_TIMER_CTRL_n_RMSK) +#define HWIO_IPA_UC_TIMER_CTRL_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_UC_TIMER_CTRL_n_ADDR(n), mask) +#define HWIO_IPA_UC_TIMER_CTRL_n_OUTI(n,val) \ + out_dword(HWIO_IPA_UC_TIMER_CTRL_n_ADDR(n),val) +#define HWIO_IPA_UC_TIMER_CTRL_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_UC_TIMER_CTRL_n_ADDR(n),mask,val,HWIO_IPA_UC_TIMER_CTRL_n_INI(n)) +#define HWIO_IPA_UC_TIMER_CTRL_n_GRAN_SEL_BMSK 0xc0000000 +#define HWIO_IPA_UC_TIMER_CTRL_n_GRAN_SEL_SHFT 0x1e +#define HWIO_IPA_UC_TIMER_CTRL_n_RETRIG_BMSK 0x1000000 +#define HWIO_IPA_UC_TIMER_CTRL_n_RETRIG_SHFT 0x18 +#define HWIO_IPA_UC_TIMER_CTRL_n_RETRIG_ONE_SHOT_FVAL 0x0 +#define HWIO_IPA_UC_TIMER_CTRL_n_RETRIG_RETRIG_FVAL 0x1 +#define HWIO_IPA_UC_TIMER_CTRL_n_EVENT_SEL_BMSK 0x7f0000 +#define HWIO_IPA_UC_TIMER_CTRL_n_EVENT_SEL_SHFT 0x10 +#define HWIO_IPA_UC_TIMER_CTRL_n_COUNT_BMSK 0xffff +#define HWIO_IPA_UC_TIMER_CTRL_n_COUNT_SHFT 0x0 + +#define HWIO_IPA_UC_TIMER_STATUS_n_ADDR(n) (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000508 + 0x10 * (n)) +#define HWIO_IPA_UC_TIMER_STATUS_n_PHYS(n) (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000508 + 0x10 * (n)) +#define HWIO_IPA_UC_TIMER_STATUS_n_OFFS(n) (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000508 + 0x10 * (n)) +#define HWIO_IPA_UC_TIMER_STATUS_n_RMSK 0x100ffff +#define HWIO_IPA_UC_TIMER_STATUS_n_MAXn 3 +#define HWIO_IPA_UC_TIMER_STATUS_n_ATTR 0x1 +#define HWIO_IPA_UC_TIMER_STATUS_n_INI(n) \ + in_dword_masked(HWIO_IPA_UC_TIMER_STATUS_n_ADDR(n), HWIO_IPA_UC_TIMER_STATUS_n_RMSK) +#define HWIO_IPA_UC_TIMER_STATUS_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_UC_TIMER_STATUS_n_ADDR(n), mask) +#define HWIO_IPA_UC_TIMER_STATUS_n_ACTIVE_BMSK 0x1000000 +#define HWIO_IPA_UC_TIMER_STATUS_n_ACTIVE_SHFT 0x18 +#define HWIO_IPA_UC_TIMER_STATUS_n_COUNT_BMSK 0xffff +#define HWIO_IPA_UC_TIMER_STATUS_n_COUNT_SHFT 0x0 + +#define HWIO_IPA_UC_EVENTS_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000600) +#define HWIO_IPA_UC_EVENTS_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000600) +#define HWIO_IPA_UC_EVENTS_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000600) +#define HWIO_IPA_UC_EVENTS_RMSK 0xffffffff +#define HWIO_IPA_UC_EVENTS_ATTR 0x2 +#define HWIO_IPA_UC_EVENTS_OUT(v) \ + out_dword(HWIO_IPA_UC_EVENTS_ADDR,v) +#define HWIO_IPA_UC_EVENTS_EVENTS_BMSK 0xffffffff +#define HWIO_IPA_UC_EVENTS_EVENTS_SHFT 0x0 + +#define HWIO_IPA_UC_VUIC_BUS_ADDR_TRANSLATE_EN_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000710) +#define HWIO_IPA_UC_VUIC_BUS_ADDR_TRANSLATE_EN_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000710) +#define HWIO_IPA_UC_VUIC_BUS_ADDR_TRANSLATE_EN_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000710) +#define HWIO_IPA_UC_VUIC_BUS_ADDR_TRANSLATE_EN_RMSK 0x3 +#define HWIO_IPA_UC_VUIC_BUS_ADDR_TRANSLATE_EN_ATTR 0x3 +#define HWIO_IPA_UC_VUIC_BUS_ADDR_TRANSLATE_EN_IN \ + in_dword_masked(HWIO_IPA_UC_VUIC_BUS_ADDR_TRANSLATE_EN_ADDR, HWIO_IPA_UC_VUIC_BUS_ADDR_TRANSLATE_EN_RMSK) +#define HWIO_IPA_UC_VUIC_BUS_ADDR_TRANSLATE_EN_INM(m) \ + in_dword_masked(HWIO_IPA_UC_VUIC_BUS_ADDR_TRANSLATE_EN_ADDR, m) +#define HWIO_IPA_UC_VUIC_BUS_ADDR_TRANSLATE_EN_OUT(v) \ + out_dword(HWIO_IPA_UC_VUIC_BUS_ADDR_TRANSLATE_EN_ADDR,v) +#define HWIO_IPA_UC_VUIC_BUS_ADDR_TRANSLATE_EN_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_VUIC_BUS_ADDR_TRANSLATE_EN_ADDR,m,v,HWIO_IPA_UC_VUIC_BUS_ADDR_TRANSLATE_EN_IN) +#define HWIO_IPA_UC_VUIC_BUS_ADDR_TRANSLATE_EN_DIRECT_ADDR_TRANSLATE_BMSK 0x2 +#define HWIO_IPA_UC_VUIC_BUS_ADDR_TRANSLATE_EN_DIRECT_ADDR_TRANSLATE_SHFT 0x1 +#define HWIO_IPA_UC_VUIC_BUS_ADDR_TRANSLATE_EN_QMB_ADDR_TRANSLATE_BMSK 0x1 +#define HWIO_IPA_UC_VUIC_BUS_ADDR_TRANSLATE_EN_QMB_ADDR_TRANSLATE_SHFT 0x0 + +#define HWIO_IPA_UC_SYS_ADDR_MSB_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000714) +#define HWIO_IPA_UC_SYS_ADDR_MSB_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000714) +#define HWIO_IPA_UC_SYS_ADDR_MSB_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000714) +#define HWIO_IPA_UC_SYS_ADDR_MSB_RMSK 0xffffffff +#define HWIO_IPA_UC_SYS_ADDR_MSB_ATTR 0x3 +#define HWIO_IPA_UC_SYS_ADDR_MSB_IN \ + in_dword_masked(HWIO_IPA_UC_SYS_ADDR_MSB_ADDR, HWIO_IPA_UC_SYS_ADDR_MSB_RMSK) +#define HWIO_IPA_UC_SYS_ADDR_MSB_INM(m) \ + in_dword_masked(HWIO_IPA_UC_SYS_ADDR_MSB_ADDR, m) +#define HWIO_IPA_UC_SYS_ADDR_MSB_OUT(v) \ + out_dword(HWIO_IPA_UC_SYS_ADDR_MSB_ADDR,v) +#define HWIO_IPA_UC_SYS_ADDR_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_SYS_ADDR_MSB_ADDR,m,v,HWIO_IPA_UC_SYS_ADDR_MSB_IN) +#define HWIO_IPA_UC_SYS_ADDR_MSB_SYS_ADDR_MSB_BMSK 0xffffffff +#define HWIO_IPA_UC_SYS_ADDR_MSB_SYS_ADDR_MSB_SHFT 0x0 + +#define HWIO_IPA_UC_PC_RESTORE_WR_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000718) +#define HWIO_IPA_UC_PC_RESTORE_WR_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000718) +#define HWIO_IPA_UC_PC_RESTORE_WR_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000718) +#define HWIO_IPA_UC_PC_RESTORE_WR_RMSK 0xf +#define HWIO_IPA_UC_PC_RESTORE_WR_ATTR 0x2 +#define HWIO_IPA_UC_PC_RESTORE_WR_OUT(v) \ + out_dword(HWIO_IPA_UC_PC_RESTORE_WR_ADDR,v) +#define HWIO_IPA_UC_PC_RESTORE_WR_CLEAR_IPA_RESTORE_ACK_BMSK 0x8 +#define HWIO_IPA_UC_PC_RESTORE_WR_CLEAR_IPA_RESTORE_ACK_SHFT 0x3 +#define HWIO_IPA_UC_PC_RESTORE_WR_SET_IPA_RESTORE_ACK_BMSK 0x4 +#define HWIO_IPA_UC_PC_RESTORE_WR_SET_IPA_RESTORE_ACK_SHFT 0x2 +#define HWIO_IPA_UC_PC_RESTORE_WR_CLEAR_IPA_PC_ACK_BMSK 0x2 +#define HWIO_IPA_UC_PC_RESTORE_WR_CLEAR_IPA_PC_ACK_SHFT 0x1 +#define HWIO_IPA_UC_PC_RESTORE_WR_SET_IPA_PC_ACK_BMSK 0x1 +#define HWIO_IPA_UC_PC_RESTORE_WR_SET_IPA_PC_ACK_SHFT 0x0 + +#define HWIO_IPA_UC_PC_RESTORE_RD_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x0000071c) +#define HWIO_IPA_UC_PC_RESTORE_RD_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x0000071c) +#define HWIO_IPA_UC_PC_RESTORE_RD_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x0000071c) +#define HWIO_IPA_UC_PC_RESTORE_RD_RMSK 0xf +#define HWIO_IPA_UC_PC_RESTORE_RD_ATTR 0x1 +#define HWIO_IPA_UC_PC_RESTORE_RD_IN \ + in_dword_masked(HWIO_IPA_UC_PC_RESTORE_RD_ADDR, HWIO_IPA_UC_PC_RESTORE_RD_RMSK) +#define HWIO_IPA_UC_PC_RESTORE_RD_INM(m) \ + in_dword_masked(HWIO_IPA_UC_PC_RESTORE_RD_ADDR, m) +#define HWIO_IPA_UC_PC_RESTORE_RD_IPA_RESTORE_ACK_BMSK 0x8 +#define HWIO_IPA_UC_PC_RESTORE_RD_IPA_RESTORE_ACK_SHFT 0x3 +#define HWIO_IPA_UC_PC_RESTORE_RD_IPA_RESTORE_REQ_BMSK 0x4 +#define HWIO_IPA_UC_PC_RESTORE_RD_IPA_RESTORE_REQ_SHFT 0x2 +#define HWIO_IPA_UC_PC_RESTORE_RD_IPA_PC_ACK_BMSK 0x2 +#define HWIO_IPA_UC_PC_RESTORE_RD_IPA_PC_ACK_SHFT 0x1 +#define HWIO_IPA_UC_PC_RESTORE_RD_IPA_PC_REQ_BMSK 0x1 +#define HWIO_IPA_UC_PC_RESTORE_RD_IPA_PC_REQ_SHFT 0x0 + +#define HWIO_IPA_UC_CNT_GLOBAL_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000800) +#define HWIO_IPA_UC_CNT_GLOBAL_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000800) +#define HWIO_IPA_UC_CNT_GLOBAL_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000800) +#define HWIO_IPA_UC_CNT_GLOBAL_RMSK 0x80000003 +#define HWIO_IPA_UC_CNT_GLOBAL_ATTR 0x0 +#define HWIO_IPA_UC_CNT_GLOBAL_IN \ + in_dword_masked(HWIO_IPA_UC_CNT_GLOBAL_ADDR, HWIO_IPA_UC_CNT_GLOBAL_RMSK) +#define HWIO_IPA_UC_CNT_GLOBAL_INM(m) \ + in_dword_masked(HWIO_IPA_UC_CNT_GLOBAL_ADDR, m) +#define HWIO_IPA_UC_CNT_GLOBAL_OUT(v) \ + out_dword(HWIO_IPA_UC_CNT_GLOBAL_ADDR,v) +#define HWIO_IPA_UC_CNT_GLOBAL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_CNT_GLOBAL_ADDR,m,v,HWIO_IPA_UC_CNT_GLOBAL_IN) +#define HWIO_IPA_UC_CNT_GLOBAL_CLEAR_ALL_BMSK 0x80000000 +#define HWIO_IPA_UC_CNT_GLOBAL_CLEAR_ALL_SHFT 0x1f +#define HWIO_IPA_UC_CNT_GLOBAL_COUNT_CGC_OPEN_BMSK 0x2 +#define HWIO_IPA_UC_CNT_GLOBAL_COUNT_CGC_OPEN_SHFT 0x1 +#define HWIO_IPA_UC_CNT_GLOBAL_COUNT_EN_BMSK 0x1 +#define HWIO_IPA_UC_CNT_GLOBAL_COUNT_EN_SHFT 0x0 + +#define HWIO_IPA_UC_CNT_CTL_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000804) +#define HWIO_IPA_UC_CNT_CTL_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000804) +#define HWIO_IPA_UC_CNT_CTL_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000804) +#define HWIO_IPA_UC_CNT_CTL_RMSK 0xff755 +#define HWIO_IPA_UC_CNT_CTL_ATTR 0x0 +#define HWIO_IPA_UC_CNT_CTL_IN \ + in_dword_masked(HWIO_IPA_UC_CNT_CTL_ADDR, HWIO_IPA_UC_CNT_CTL_RMSK) +#define HWIO_IPA_UC_CNT_CTL_INM(m) \ + in_dword_masked(HWIO_IPA_UC_CNT_CTL_ADDR, m) +#define HWIO_IPA_UC_CNT_CTL_OUT(v) \ + out_dword(HWIO_IPA_UC_CNT_CTL_ADDR,v) +#define HWIO_IPA_UC_CNT_CTL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_CNT_CTL_ADDR,m,v,HWIO_IPA_UC_CNT_CTL_IN) +#define HWIO_IPA_UC_CNT_CTL_DRAM_CNT_CLR_BMSK 0x80000 +#define HWIO_IPA_UC_CNT_CTL_DRAM_CNT_CLR_SHFT 0x13 +#define HWIO_IPA_UC_CNT_CTL_DRAM_CLR_AFTER_RD_BMSK 0x40000 +#define HWIO_IPA_UC_CNT_CTL_DRAM_CLR_AFTER_RD_SHFT 0x12 +#define HWIO_IPA_UC_CNT_CTL_DRAM_WR_CNT_EN_BMSK 0x20000 +#define HWIO_IPA_UC_CNT_CTL_DRAM_WR_CNT_EN_SHFT 0x11 +#define HWIO_IPA_UC_CNT_CTL_DRAM_RD_CNT_EN_BMSK 0x10000 +#define HWIO_IPA_UC_CNT_CTL_DRAM_RD_CNT_EN_SHFT 0x10 +#define HWIO_IPA_UC_CNT_CTL_VUIC_CNT_CLR_BMSK 0x8000 +#define HWIO_IPA_UC_CNT_CTL_VUIC_CNT_CLR_SHFT 0xf +#define HWIO_IPA_UC_CNT_CTL_VUIC_CLR_AFTER_RD_BMSK 0x4000 +#define HWIO_IPA_UC_CNT_CTL_VUIC_CLR_AFTER_RD_SHFT 0xe +#define HWIO_IPA_UC_CNT_CTL_VUIC_WR_CNT_EN_BMSK 0x2000 +#define HWIO_IPA_UC_CNT_CTL_VUIC_WR_CNT_EN_SHFT 0xd +#define HWIO_IPA_UC_CNT_CTL_VUIC_RD_CNT_EN_BMSK 0x1000 +#define HWIO_IPA_UC_CNT_CTL_VUIC_RD_CNT_EN_SHFT 0xc +#define HWIO_IPA_UC_CNT_CTL_INST_CNT_CLR_BMSK 0x400 +#define HWIO_IPA_UC_CNT_CTL_INST_CNT_CLR_SHFT 0xa +#define HWIO_IPA_UC_CNT_CTL_INST_CLR_AFTER_RD_BMSK 0x200 +#define HWIO_IPA_UC_CNT_CTL_INST_CLR_AFTER_RD_SHFT 0x9 +#define HWIO_IPA_UC_CNT_CTL_INST_CNT_EN_BMSK 0x100 +#define HWIO_IPA_UC_CNT_CTL_INST_CNT_EN_SHFT 0x8 +#define HWIO_IPA_UC_CNT_CTL_IDLE_CNT_CLR_BMSK 0x40 +#define HWIO_IPA_UC_CNT_CTL_IDLE_CNT_CLR_SHFT 0x6 +#define HWIO_IPA_UC_CNT_CTL_IDLE_CNT_EN_BMSK 0x10 +#define HWIO_IPA_UC_CNT_CTL_IDLE_CNT_EN_SHFT 0x4 +#define HWIO_IPA_UC_CNT_CTL_CYCLE_CNT_CLR_BMSK 0x4 +#define HWIO_IPA_UC_CNT_CTL_CYCLE_CNT_CLR_SHFT 0x2 +#define HWIO_IPA_UC_CNT_CTL_CYCLE_CNT_EN_BMSK 0x1 +#define HWIO_IPA_UC_CNT_CTL_CYCLE_CNT_EN_SHFT 0x0 + +#define HWIO_IPA_UC_CNT_CLK_CYCLE_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000808) +#define HWIO_IPA_UC_CNT_CLK_CYCLE_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000808) +#define HWIO_IPA_UC_CNT_CLK_CYCLE_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000808) +#define HWIO_IPA_UC_CNT_CLK_CYCLE_RMSK 0xffffffff +#define HWIO_IPA_UC_CNT_CLK_CYCLE_ATTR 0x1 +#define HWIO_IPA_UC_CNT_CLK_CYCLE_IN \ + in_dword_masked(HWIO_IPA_UC_CNT_CLK_CYCLE_ADDR, HWIO_IPA_UC_CNT_CLK_CYCLE_RMSK) +#define HWIO_IPA_UC_CNT_CLK_CYCLE_INM(m) \ + in_dword_masked(HWIO_IPA_UC_CNT_CLK_CYCLE_ADDR, m) +#define HWIO_IPA_UC_CNT_CLK_CYCLE_COUNTER_BMSK 0xffffffff +#define HWIO_IPA_UC_CNT_CLK_CYCLE_COUNTER_SHFT 0x0 + +#define HWIO_IPA_UC_CNT_CLK_CYCLE_MSB_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x0000080c) +#define HWIO_IPA_UC_CNT_CLK_CYCLE_MSB_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x0000080c) +#define HWIO_IPA_UC_CNT_CLK_CYCLE_MSB_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x0000080c) +#define HWIO_IPA_UC_CNT_CLK_CYCLE_MSB_RMSK 0xff +#define HWIO_IPA_UC_CNT_CLK_CYCLE_MSB_ATTR 0x1 +#define HWIO_IPA_UC_CNT_CLK_CYCLE_MSB_IN \ + in_dword_masked(HWIO_IPA_UC_CNT_CLK_CYCLE_MSB_ADDR, HWIO_IPA_UC_CNT_CLK_CYCLE_MSB_RMSK) +#define HWIO_IPA_UC_CNT_CLK_CYCLE_MSB_INM(m) \ + in_dword_masked(HWIO_IPA_UC_CNT_CLK_CYCLE_MSB_ADDR, m) +#define HWIO_IPA_UC_CNT_CLK_CYCLE_MSB_COUNTER_BMSK 0xff +#define HWIO_IPA_UC_CNT_CLK_CYCLE_MSB_COUNTER_SHFT 0x0 + +#define HWIO_IPA_UC_CNT_IDLE_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000810) +#define HWIO_IPA_UC_CNT_IDLE_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000810) +#define HWIO_IPA_UC_CNT_IDLE_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000810) +#define HWIO_IPA_UC_CNT_IDLE_RMSK 0xffffffff +#define HWIO_IPA_UC_CNT_IDLE_ATTR 0x1 +#define HWIO_IPA_UC_CNT_IDLE_IN \ + in_dword_masked(HWIO_IPA_UC_CNT_IDLE_ADDR, HWIO_IPA_UC_CNT_IDLE_RMSK) +#define HWIO_IPA_UC_CNT_IDLE_INM(m) \ + in_dword_masked(HWIO_IPA_UC_CNT_IDLE_ADDR, m) +#define HWIO_IPA_UC_CNT_IDLE_COUNTER_BMSK 0xffffffff +#define HWIO_IPA_UC_CNT_IDLE_COUNTER_SHFT 0x0 + +#define HWIO_IPA_UC_CNT_IDLE_MSB_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000814) +#define HWIO_IPA_UC_CNT_IDLE_MSB_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000814) +#define HWIO_IPA_UC_CNT_IDLE_MSB_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000814) +#define HWIO_IPA_UC_CNT_IDLE_MSB_RMSK 0xff +#define HWIO_IPA_UC_CNT_IDLE_MSB_ATTR 0x1 +#define HWIO_IPA_UC_CNT_IDLE_MSB_IN \ + in_dword_masked(HWIO_IPA_UC_CNT_IDLE_MSB_ADDR, HWIO_IPA_UC_CNT_IDLE_MSB_RMSK) +#define HWIO_IPA_UC_CNT_IDLE_MSB_INM(m) \ + in_dword_masked(HWIO_IPA_UC_CNT_IDLE_MSB_ADDR, m) +#define HWIO_IPA_UC_CNT_IDLE_MSB_COUNTER_BMSK 0xff +#define HWIO_IPA_UC_CNT_IDLE_MSB_COUNTER_SHFT 0x0 + +#define HWIO_IPA_UC_CNT_INST_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000818) +#define HWIO_IPA_UC_CNT_INST_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000818) +#define HWIO_IPA_UC_CNT_INST_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000818) +#define HWIO_IPA_UC_CNT_INST_RMSK 0xffffffff +#define HWIO_IPA_UC_CNT_INST_ATTR 0x1 +#define HWIO_IPA_UC_CNT_INST_IN \ + in_dword_masked(HWIO_IPA_UC_CNT_INST_ADDR, HWIO_IPA_UC_CNT_INST_RMSK) +#define HWIO_IPA_UC_CNT_INST_INM(m) \ + in_dword_masked(HWIO_IPA_UC_CNT_INST_ADDR, m) +#define HWIO_IPA_UC_CNT_INST_COUNTER_BMSK 0xffffffff +#define HWIO_IPA_UC_CNT_INST_COUNTER_SHFT 0x0 + +#define HWIO_IPA_UC_CNT_DRAM_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x0000081c) +#define HWIO_IPA_UC_CNT_DRAM_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x0000081c) +#define HWIO_IPA_UC_CNT_DRAM_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x0000081c) +#define HWIO_IPA_UC_CNT_DRAM_RMSK 0xffffffff +#define HWIO_IPA_UC_CNT_DRAM_ATTR 0x1 +#define HWIO_IPA_UC_CNT_DRAM_IN \ + in_dword_masked(HWIO_IPA_UC_CNT_DRAM_ADDR, HWIO_IPA_UC_CNT_DRAM_RMSK) +#define HWIO_IPA_UC_CNT_DRAM_INM(m) \ + in_dword_masked(HWIO_IPA_UC_CNT_DRAM_ADDR, m) +#define HWIO_IPA_UC_CNT_DRAM_COUNTER_BMSK 0xffffffff +#define HWIO_IPA_UC_CNT_DRAM_COUNTER_SHFT 0x0 + +#define HWIO_IPA_UC_CNT_VUIC_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000820) +#define HWIO_IPA_UC_CNT_VUIC_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000820) +#define HWIO_IPA_UC_CNT_VUIC_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000820) +#define HWIO_IPA_UC_CNT_VUIC_RMSK 0xffffffff +#define HWIO_IPA_UC_CNT_VUIC_ATTR 0x1 +#define HWIO_IPA_UC_CNT_VUIC_IN \ + in_dword_masked(HWIO_IPA_UC_CNT_VUIC_ADDR, HWIO_IPA_UC_CNT_VUIC_RMSK) +#define HWIO_IPA_UC_CNT_VUIC_INM(m) \ + in_dword_masked(HWIO_IPA_UC_CNT_VUIC_ADDR, m) +#define HWIO_IPA_UC_CNT_VUIC_COUNTER_BMSK 0xffffffff +#define HWIO_IPA_UC_CNT_VUIC_COUNTER_SHFT 0x0 + +#define HWIO_IPA_UC_SPARE_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00001ffc) +#define HWIO_IPA_UC_SPARE_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00001ffc) +#define HWIO_IPA_UC_SPARE_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00001ffc) +#define HWIO_IPA_UC_SPARE_RMSK 0xffffffff +#define HWIO_IPA_UC_SPARE_ATTR 0x3 +#define HWIO_IPA_UC_SPARE_IN \ + in_dword_masked(HWIO_IPA_UC_SPARE_ADDR, HWIO_IPA_UC_SPARE_RMSK) +#define HWIO_IPA_UC_SPARE_INM(m) \ + in_dword_masked(HWIO_IPA_UC_SPARE_ADDR, m) +#define HWIO_IPA_UC_SPARE_OUT(v) \ + out_dword(HWIO_IPA_UC_SPARE_ADDR,v) +#define HWIO_IPA_UC_SPARE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_SPARE_ADDR,m,v,HWIO_IPA_UC_SPARE_IN) +#define HWIO_IPA_UC_SPARE_SPARE_BMSK 0xffffffff +#define HWIO_IPA_UC_SPARE_SPARE_SHFT 0x0 + +/*---------------------------------------------------------------------------- + * MODULE: IPA_UC_IPA_UC_MBOX + *--------------------------------------------------------------------------*/ + +#define IPA_UC_IPA_UC_MBOX_REG_BASE (IPA_0_IPA_WRAPPER_BASE + 0x001c2000) +#define IPA_UC_IPA_UC_MBOX_REG_BASE_PHYS (IPA_0_IPA_WRAPPER_BASE_PHYS + 0x001c2000) +#define IPA_UC_IPA_UC_MBOX_REG_BASE_OFFS 0x001c2000 + +#define HWIO_IPA_UC_MAILBOX_m_n_ADDR(m,n) (IPA_UC_IPA_UC_MBOX_REG_BASE + 0x00000000 + 0x80 * (m) + 0x4 * (n)) +#define HWIO_IPA_UC_MAILBOX_m_n_PHYS(m,n) (IPA_UC_IPA_UC_MBOX_REG_BASE_PHYS + 0x00000000 + 0x80 * (m) + 0x4 * (n)) +#define HWIO_IPA_UC_MAILBOX_m_n_OFFS(m,n) (IPA_UC_IPA_UC_MBOX_REG_BASE_OFFS + 0x00000000 + 0x80 * (m) + 0x4 * (n)) +#define HWIO_IPA_UC_MAILBOX_m_n_RMSK 0xffffffff +#define HWIO_IPA_UC_MAILBOX_m_n_MAXm 3 +#define HWIO_IPA_UC_MAILBOX_m_n_MAXn 31 +#define HWIO_IPA_UC_MAILBOX_m_n_ATTR 0x3 +#define HWIO_IPA_UC_MAILBOX_m_n_INI2(m,n) \ + in_dword_masked(HWIO_IPA_UC_MAILBOX_m_n_ADDR(m,n), HWIO_IPA_UC_MAILBOX_m_n_RMSK) +#define HWIO_IPA_UC_MAILBOX_m_n_INMI2(m,n,mask) \ + in_dword_masked(HWIO_IPA_UC_MAILBOX_m_n_ADDR(m,n), mask) +#define HWIO_IPA_UC_MAILBOX_m_n_OUTI2(m,n,val) \ + out_dword(HWIO_IPA_UC_MAILBOX_m_n_ADDR(m,n),val) +#define HWIO_IPA_UC_MAILBOX_m_n_OUTMI2(m,n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_UC_MAILBOX_m_n_ADDR(m,n),mask,val,HWIO_IPA_UC_MAILBOX_m_n_INI2(m,n)) +#define HWIO_IPA_UC_MAILBOX_m_n_DATA_BMSK 0xffffffff +#define HWIO_IPA_UC_MAILBOX_m_n_DATA_SHFT 0x0 + +/*---------------------------------------------------------------------------- + * MODULE: IPA_RAM + *--------------------------------------------------------------------------*/ + +#define IPA_RAM_REG_BASE (IPA_0_IPA_WRAPPER_BASE + 0x00150000) +#define IPA_RAM_REG_BASE_PHYS (IPA_0_IPA_WRAPPER_BASE_PHYS + 0x00150000) +#define IPA_RAM_REG_BASE_OFFS 0x00150000 + +#define HWIO_IPA_SW_AREA_RAM_DIRECT_ACCESS_n_ADDR(n) (IPA_RAM_REG_BASE + 0x00000000 + 0x4 * (n)) +#define HWIO_IPA_SW_AREA_RAM_DIRECT_ACCESS_n_PHYS(n) (IPA_RAM_REG_BASE_PHYS + 0x00000000 + 0x4 * (n)) +#define HWIO_IPA_SW_AREA_RAM_DIRECT_ACCESS_n_OFFS(n) (IPA_RAM_REG_BASE_OFFS + 0x00000000 + 0x4 * (n)) +#define HWIO_IPA_SW_AREA_RAM_DIRECT_ACCESS_n_RMSK 0xffffffff +#define HWIO_IPA_SW_AREA_RAM_DIRECT_ACCESS_n_MAXn 5119 +#define HWIO_IPA_SW_AREA_RAM_DIRECT_ACCESS_n_ATTR 0x3 +#define HWIO_IPA_SW_AREA_RAM_DIRECT_ACCESS_n_INI(n) \ + in_dword_masked(HWIO_IPA_SW_AREA_RAM_DIRECT_ACCESS_n_ADDR(n), HWIO_IPA_SW_AREA_RAM_DIRECT_ACCESS_n_RMSK) +#define HWIO_IPA_SW_AREA_RAM_DIRECT_ACCESS_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_SW_AREA_RAM_DIRECT_ACCESS_n_ADDR(n), mask) +#define HWIO_IPA_SW_AREA_RAM_DIRECT_ACCESS_n_OUTI(n,val) \ + out_dword(HWIO_IPA_SW_AREA_RAM_DIRECT_ACCESS_n_ADDR(n),val) +#define HWIO_IPA_SW_AREA_RAM_DIRECT_ACCESS_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_SW_AREA_RAM_DIRECT_ACCESS_n_ADDR(n),mask,val,HWIO_IPA_SW_AREA_RAM_DIRECT_ACCESS_n_INI(n)) +#define HWIO_IPA_SW_AREA_RAM_DIRECT_ACCESS_n_DATA_WORD_BMSK 0xffffffff +#define HWIO_IPA_SW_AREA_RAM_DIRECT_ACCESS_n_DATA_WORD_SHFT 0x0 + +#define HWIO_IPA_HW_AREA_RAM_DIRECT_ACCESS_n_ADDR(n) (IPA_RAM_REG_BASE + 0x00010000 + 0x4 * (n)) +#define HWIO_IPA_HW_AREA_RAM_DIRECT_ACCESS_n_PHYS(n) (IPA_RAM_REG_BASE_PHYS + 0x00010000 + 0x4 * (n)) +#define HWIO_IPA_HW_AREA_RAM_DIRECT_ACCESS_n_OFFS(n) (IPA_RAM_REG_BASE_OFFS + 0x00010000 + 0x4 * (n)) +#define HWIO_IPA_HW_AREA_RAM_DIRECT_ACCESS_n_RMSK 0xffffffff +#define HWIO_IPA_HW_AREA_RAM_DIRECT_ACCESS_n_MAXn 10051 +#define HWIO_IPA_HW_AREA_RAM_DIRECT_ACCESS_n_ATTR 0x3 +#define HWIO_IPA_HW_AREA_RAM_DIRECT_ACCESS_n_INI(n) \ + in_dword_masked(HWIO_IPA_HW_AREA_RAM_DIRECT_ACCESS_n_ADDR(n), HWIO_IPA_HW_AREA_RAM_DIRECT_ACCESS_n_RMSK) +#define HWIO_IPA_HW_AREA_RAM_DIRECT_ACCESS_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_HW_AREA_RAM_DIRECT_ACCESS_n_ADDR(n), mask) +#define HWIO_IPA_HW_AREA_RAM_DIRECT_ACCESS_n_OUTI(n,val) \ + out_dword(HWIO_IPA_HW_AREA_RAM_DIRECT_ACCESS_n_ADDR(n),val) +#define HWIO_IPA_HW_AREA_RAM_DIRECT_ACCESS_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_HW_AREA_RAM_DIRECT_ACCESS_n_ADDR(n),mask,val,HWIO_IPA_HW_AREA_RAM_DIRECT_ACCESS_n_INI(n)) +#define HWIO_IPA_HW_AREA_RAM_DIRECT_ACCESS_n_DATA_WORD_BMSK 0xffffffff +#define HWIO_IPA_HW_AREA_RAM_DIRECT_ACCESS_n_DATA_WORD_SHFT 0x0 + +/*---------------------------------------------------------------------------- + * MODULE: IPA_EE + *--------------------------------------------------------------------------*/ + +#define IPA_EE_REG_BASE (IPA_0_IPA_WRAPPER_BASE + 0x0014c000) +#define IPA_EE_REG_BASE_PHYS (IPA_0_IPA_WRAPPER_BASE_PHYS + 0x0014c000) +#define IPA_EE_REG_BASE_OFFS 0x0014c000 + +#define HWIO_IPA_IRQ_STTS_EE_n_ADDR(n) (IPA_EE_REG_BASE + 0x00000008 + 0x1000 * (n)) +#define HWIO_IPA_IRQ_STTS_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + 0x00000008 + 0x1000 * (n)) +#define HWIO_IPA_IRQ_STTS_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + 0x00000008 + 0x1000 * (n)) +#define HWIO_IPA_IRQ_STTS_EE_n_RMSK 0x3fbffffd +#define HWIO_IPA_IRQ_STTS_EE_n_MAXn 3 +#define HWIO_IPA_IRQ_STTS_EE_n_ATTR 0x1 +#define HWIO_IPA_IRQ_STTS_EE_n_INI(n) \ + in_dword_masked(HWIO_IPA_IRQ_STTS_EE_n_ADDR(n), HWIO_IPA_IRQ_STTS_EE_n_RMSK) +#define HWIO_IPA_IRQ_STTS_EE_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_IRQ_STTS_EE_n_ADDR(n), mask) +#define HWIO_IPA_IRQ_STTS_EE_n_DRBIP_IMM_CMD_NO_FLSH_HZRD_IRQ_BMSK 0x20000000 +#define HWIO_IPA_IRQ_STTS_EE_n_DRBIP_IMM_CMD_NO_FLSH_HZRD_IRQ_SHFT 0x1d +#define HWIO_IPA_IRQ_STTS_EE_n_DRBIP_DATA_SCTR_CFG_ERROR_IRQ_BMSK 0x10000000 +#define HWIO_IPA_IRQ_STTS_EE_n_DRBIP_DATA_SCTR_CFG_ERROR_IRQ_SHFT 0x1c +#define HWIO_IPA_IRQ_STTS_EE_n_DRBIP_PKT_EXCEED_MAX_SIZE_IRQ_BMSK 0x8000000 +#define HWIO_IPA_IRQ_STTS_EE_n_DRBIP_PKT_EXCEED_MAX_SIZE_IRQ_SHFT 0x1b +#define HWIO_IPA_IRQ_STTS_EE_n_TLV_LEN_MIN_DSM_IRQ_BMSK 0x4000000 +#define HWIO_IPA_IRQ_STTS_EE_n_TLV_LEN_MIN_DSM_IRQ_SHFT 0x1a +#define HWIO_IPA_IRQ_STTS_EE_n_GSI_UC_IRQ_BMSK 0x2000000 +#define HWIO_IPA_IRQ_STTS_EE_n_GSI_UC_IRQ_SHFT 0x19 +#define HWIO_IPA_IRQ_STTS_EE_n_GSI_IPA_IF_TLV_RCVD_IRQ_BMSK 0x1000000 +#define HWIO_IPA_IRQ_STTS_EE_n_GSI_IPA_IF_TLV_RCVD_IRQ_SHFT 0x18 +#define HWIO_IPA_IRQ_STTS_EE_n_GSI_EE_IRQ_BMSK 0x800000 +#define HWIO_IPA_IRQ_STTS_EE_n_GSI_EE_IRQ_SHFT 0x17 +#define HWIO_IPA_IRQ_STTS_EE_n_UCP_IRQ_BMSK 0x200000 +#define HWIO_IPA_IRQ_STTS_EE_n_UCP_IRQ_SHFT 0x15 +#define HWIO_IPA_IRQ_STTS_EE_n_PIPE_RED_MARKER_ABOVE_IRQ_BMSK 0x100000 +#define HWIO_IPA_IRQ_STTS_EE_n_PIPE_RED_MARKER_ABOVE_IRQ_SHFT 0x14 +#define HWIO_IPA_IRQ_STTS_EE_n_PIPE_YELLOW_MARKER_ABOVE_IRQ_BMSK 0x80000 +#define HWIO_IPA_IRQ_STTS_EE_n_PIPE_YELLOW_MARKER_ABOVE_IRQ_SHFT 0x13 +#define HWIO_IPA_IRQ_STTS_EE_n_PIPE_RED_MARKER_BELOW_IRQ_BMSK 0x40000 +#define HWIO_IPA_IRQ_STTS_EE_n_PIPE_RED_MARKER_BELOW_IRQ_SHFT 0x12 +#define HWIO_IPA_IRQ_STTS_EE_n_PIPE_YELLOW_MARKER_BELOW_IRQ_BMSK 0x20000 +#define HWIO_IPA_IRQ_STTS_EE_n_PIPE_YELLOW_MARKER_BELOW_IRQ_SHFT 0x11 +#define HWIO_IPA_IRQ_STTS_EE_n_BAM_GSI_IDLE_IRQ_BMSK 0x10000 +#define HWIO_IPA_IRQ_STTS_EE_n_BAM_GSI_IDLE_IRQ_SHFT 0x10 +#define HWIO_IPA_IRQ_STTS_EE_n_TX_HOLB_DROP_IRQ_BMSK 0x8000 +#define HWIO_IPA_IRQ_STTS_EE_n_TX_HOLB_DROP_IRQ_SHFT 0xf +#define HWIO_IPA_IRQ_STTS_EE_n_TX_SUSPEND_IRQ_BMSK 0x4000 +#define HWIO_IPA_IRQ_STTS_EE_n_TX_SUSPEND_IRQ_SHFT 0xe +#define HWIO_IPA_IRQ_STTS_EE_n_PROC_ERR_IRQ_BMSK 0x2000 +#define HWIO_IPA_IRQ_STTS_EE_n_PROC_ERR_IRQ_SHFT 0xd +#define HWIO_IPA_IRQ_STTS_EE_n_STEP_MODE_IRQ_BMSK 0x1000 +#define HWIO_IPA_IRQ_STTS_EE_n_STEP_MODE_IRQ_SHFT 0xc +#define HWIO_IPA_IRQ_STTS_EE_n_TX_ERR_IRQ_BMSK 0x800 +#define HWIO_IPA_IRQ_STTS_EE_n_TX_ERR_IRQ_SHFT 0xb +#define HWIO_IPA_IRQ_STTS_EE_n_DEAGGR_ERR_IRQ_BMSK 0x400 +#define HWIO_IPA_IRQ_STTS_EE_n_DEAGGR_ERR_IRQ_SHFT 0xa +#define HWIO_IPA_IRQ_STTS_EE_n_RX_ERR_IRQ_BMSK 0x200 +#define HWIO_IPA_IRQ_STTS_EE_n_RX_ERR_IRQ_SHFT 0x9 +#define HWIO_IPA_IRQ_STTS_EE_n_PROC_TO_UC_ACK_Q_NOT_EMPTY_IRQ_BMSK 0x100 +#define HWIO_IPA_IRQ_STTS_EE_n_PROC_TO_UC_ACK_Q_NOT_EMPTY_IRQ_SHFT 0x8 +#define HWIO_IPA_IRQ_STTS_EE_n_UC_RX_CMD_Q_NOT_FULL_IRQ_BMSK 0x80 +#define HWIO_IPA_IRQ_STTS_EE_n_UC_RX_CMD_Q_NOT_FULL_IRQ_SHFT 0x7 +#define HWIO_IPA_IRQ_STTS_EE_n_UC_IN_Q_NOT_EMPTY_IRQ_BMSK 0x40 +#define HWIO_IPA_IRQ_STTS_EE_n_UC_IN_Q_NOT_EMPTY_IRQ_SHFT 0x6 +#define HWIO_IPA_IRQ_STTS_EE_n_UC_IRQ_3_BMSK 0x20 +#define HWIO_IPA_IRQ_STTS_EE_n_UC_IRQ_3_SHFT 0x5 +#define HWIO_IPA_IRQ_STTS_EE_n_UC_IRQ_2_BMSK 0x10 +#define HWIO_IPA_IRQ_STTS_EE_n_UC_IRQ_2_SHFT 0x4 +#define HWIO_IPA_IRQ_STTS_EE_n_UC_IRQ_1_BMSK 0x8 +#define HWIO_IPA_IRQ_STTS_EE_n_UC_IRQ_1_SHFT 0x3 +#define HWIO_IPA_IRQ_STTS_EE_n_UC_IRQ_0_BMSK 0x4 +#define HWIO_IPA_IRQ_STTS_EE_n_UC_IRQ_0_SHFT 0x2 +#define HWIO_IPA_IRQ_STTS_EE_n_BAD_SNOC_ACCESS_IRQ_BMSK 0x1 +#define HWIO_IPA_IRQ_STTS_EE_n_BAD_SNOC_ACCESS_IRQ_SHFT 0x0 + +#define HWIO_IPA_IRQ_EN_EE_n_ADDR(n) (IPA_EE_REG_BASE + 0x0000000c + 0x1000 * (n)) +#define HWIO_IPA_IRQ_EN_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + 0x0000000c + 0x1000 * (n)) +#define HWIO_IPA_IRQ_EN_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + 0x0000000c + 0x1000 * (n)) +#define HWIO_IPA_IRQ_EN_EE_n_RMSK 0x3fbffffd +#define HWIO_IPA_IRQ_EN_EE_n_MAXn 3 +#define HWIO_IPA_IRQ_EN_EE_n_ATTR 0x3 +#define HWIO_IPA_IRQ_EN_EE_n_INI(n) \ + in_dword_masked(HWIO_IPA_IRQ_EN_EE_n_ADDR(n), HWIO_IPA_IRQ_EN_EE_n_RMSK) +#define HWIO_IPA_IRQ_EN_EE_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_IRQ_EN_EE_n_ADDR(n), mask) +#define HWIO_IPA_IRQ_EN_EE_n_OUTI(n,val) \ + out_dword(HWIO_IPA_IRQ_EN_EE_n_ADDR(n),val) +#define HWIO_IPA_IRQ_EN_EE_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_IRQ_EN_EE_n_ADDR(n),mask,val,HWIO_IPA_IRQ_EN_EE_n_INI(n)) +#define HWIO_IPA_IRQ_EN_EE_n_DRBIP_IMM_CMD_NO_FLSH_HZRD_IRQ_EN_BMSK 0x20000000 +#define HWIO_IPA_IRQ_EN_EE_n_DRBIP_IMM_CMD_NO_FLSH_HZRD_IRQ_EN_SHFT 0x1d +#define HWIO_IPA_IRQ_EN_EE_n_DRBIP_DATA_SCTR_CFG_ERROR_IRQ_EN_BMSK 0x10000000 +#define HWIO_IPA_IRQ_EN_EE_n_DRBIP_DATA_SCTR_CFG_ERROR_IRQ_EN_SHFT 0x1c +#define HWIO_IPA_IRQ_EN_EE_n_DRBIP_PKT_EXCEED_MAX_SIZE_IRQ_EN_BMSK 0x8000000 +#define HWIO_IPA_IRQ_EN_EE_n_DRBIP_PKT_EXCEED_MAX_SIZE_IRQ_EN_SHFT 0x1b +#define HWIO_IPA_IRQ_EN_EE_n_TLV_LEN_MIN_DSM_IRQ_EN_BMSK 0x4000000 +#define HWIO_IPA_IRQ_EN_EE_n_TLV_LEN_MIN_DSM_IRQ_EN_SHFT 0x1a +#define HWIO_IPA_IRQ_EN_EE_n_GSI_UC_IRQ_EN_BMSK 0x2000000 +#define HWIO_IPA_IRQ_EN_EE_n_GSI_UC_IRQ_EN_SHFT 0x19 +#define HWIO_IPA_IRQ_EN_EE_n_GSI_IPA_IF_TLV_RCVD_IRQ_EN_BMSK 0x1000000 +#define HWIO_IPA_IRQ_EN_EE_n_GSI_IPA_IF_TLV_RCVD_IRQ_EN_SHFT 0x18 +#define HWIO_IPA_IRQ_EN_EE_n_GSI_EE_IRQ_EN_BMSK 0x800000 +#define HWIO_IPA_IRQ_EN_EE_n_GSI_EE_IRQ_EN_SHFT 0x17 +#define HWIO_IPA_IRQ_EN_EE_n_UCP_IRQ_EN_BMSK 0x200000 +#define HWIO_IPA_IRQ_EN_EE_n_UCP_IRQ_EN_SHFT 0x15 +#define HWIO_IPA_IRQ_EN_EE_n_PIPE_RED_MARKER_ABOVE_IRQ_EN_BMSK 0x100000 +#define HWIO_IPA_IRQ_EN_EE_n_PIPE_RED_MARKER_ABOVE_IRQ_EN_SHFT 0x14 +#define HWIO_IPA_IRQ_EN_EE_n_PIPE_YELLOW_MARKER_ABOVE_IRQ_EN_BMSK 0x80000 +#define HWIO_IPA_IRQ_EN_EE_n_PIPE_YELLOW_MARKER_ABOVE_IRQ_EN_SHFT 0x13 +#define HWIO_IPA_IRQ_EN_EE_n_PIPE_RED_MARKER_BELOW_IRQ_EN_BMSK 0x40000 +#define HWIO_IPA_IRQ_EN_EE_n_PIPE_RED_MARKER_BELOW_IRQ_EN_SHFT 0x12 +#define HWIO_IPA_IRQ_EN_EE_n_PIPE_YELLOW_MARKER_BELOW_IRQ_EN_BMSK 0x20000 +#define HWIO_IPA_IRQ_EN_EE_n_PIPE_YELLOW_MARKER_BELOW_IRQ_EN_SHFT 0x11 +#define HWIO_IPA_IRQ_EN_EE_n_BAM_GSI_IDLE_IRQ_EN_BMSK 0x10000 +#define HWIO_IPA_IRQ_EN_EE_n_BAM_GSI_IDLE_IRQ_EN_SHFT 0x10 +#define HWIO_IPA_IRQ_EN_EE_n_TX_HOLB_DROP_IRQ_EN_BMSK 0x8000 +#define HWIO_IPA_IRQ_EN_EE_n_TX_HOLB_DROP_IRQ_EN_SHFT 0xf +#define HWIO_IPA_IRQ_EN_EE_n_TX_SUSPEND_IRQ_EN_BMSK 0x4000 +#define HWIO_IPA_IRQ_EN_EE_n_TX_SUSPEND_IRQ_EN_SHFT 0xe +#define HWIO_IPA_IRQ_EN_EE_n_PROC_ERR_IRQ_EN_BMSK 0x2000 +#define HWIO_IPA_IRQ_EN_EE_n_PROC_ERR_IRQ_EN_SHFT 0xd +#define HWIO_IPA_IRQ_EN_EE_n_STEP_MODE_IRQ_EN_BMSK 0x1000 +#define HWIO_IPA_IRQ_EN_EE_n_STEP_MODE_IRQ_EN_SHFT 0xc +#define HWIO_IPA_IRQ_EN_EE_n_TX_ERR_IRQ_EN_BMSK 0x800 +#define HWIO_IPA_IRQ_EN_EE_n_TX_ERR_IRQ_EN_SHFT 0xb +#define HWIO_IPA_IRQ_EN_EE_n_DEAGGR_ERR_IRQ_EN_BMSK 0x400 +#define HWIO_IPA_IRQ_EN_EE_n_DEAGGR_ERR_IRQ_EN_SHFT 0xa +#define HWIO_IPA_IRQ_EN_EE_n_RX_ERR_IRQ_EN_BMSK 0x200 +#define HWIO_IPA_IRQ_EN_EE_n_RX_ERR_IRQ_EN_SHFT 0x9 +#define HWIO_IPA_IRQ_EN_EE_n_PROC_TO_UC_ACK_Q_NOT_EMPTY_IRQ_EN_BMSK 0x100 +#define HWIO_IPA_IRQ_EN_EE_n_PROC_TO_UC_ACK_Q_NOT_EMPTY_IRQ_EN_SHFT 0x8 +#define HWIO_IPA_IRQ_EN_EE_n_UC_RX_CMD_Q_NOT_FULL_IRQ_EN_BMSK 0x80 +#define HWIO_IPA_IRQ_EN_EE_n_UC_RX_CMD_Q_NOT_FULL_IRQ_EN_SHFT 0x7 +#define HWIO_IPA_IRQ_EN_EE_n_UC_IN_Q_NOT_EMPTY_IRQ_EN_BMSK 0x40 +#define HWIO_IPA_IRQ_EN_EE_n_UC_IN_Q_NOT_EMPTY_IRQ_EN_SHFT 0x6 +#define HWIO_IPA_IRQ_EN_EE_n_UC_IRQ_3_IRQ_EN_BMSK 0x20 +#define HWIO_IPA_IRQ_EN_EE_n_UC_IRQ_3_IRQ_EN_SHFT 0x5 +#define HWIO_IPA_IRQ_EN_EE_n_UC_IRQ_2_IRQ_EN_BMSK 0x10 +#define HWIO_IPA_IRQ_EN_EE_n_UC_IRQ_2_IRQ_EN_SHFT 0x4 +#define HWIO_IPA_IRQ_EN_EE_n_UC_IRQ_1_IRQ_EN_BMSK 0x8 +#define HWIO_IPA_IRQ_EN_EE_n_UC_IRQ_1_IRQ_EN_SHFT 0x3 +#define HWIO_IPA_IRQ_EN_EE_n_UC_IRQ_0_IRQ_EN_BMSK 0x4 +#define HWIO_IPA_IRQ_EN_EE_n_UC_IRQ_0_IRQ_EN_SHFT 0x2 +#define HWIO_IPA_IRQ_EN_EE_n_BAD_SNOC_ACCESS_IRQ_EN_BMSK 0x1 +#define HWIO_IPA_IRQ_EN_EE_n_BAD_SNOC_ACCESS_IRQ_EN_SHFT 0x0 + +#define HWIO_IPA_IRQ_CLR_EE_n_ADDR(n) (IPA_EE_REG_BASE + 0x00000010 + 0x1000 * (n)) +#define HWIO_IPA_IRQ_CLR_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + 0x00000010 + 0x1000 * (n)) +#define HWIO_IPA_IRQ_CLR_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + 0x00000010 + 0x1000 * (n)) +#define HWIO_IPA_IRQ_CLR_EE_n_RMSK 0x3fbffffd +#define HWIO_IPA_IRQ_CLR_EE_n_MAXn 3 +#define HWIO_IPA_IRQ_CLR_EE_n_ATTR 0x2 +#define HWIO_IPA_IRQ_CLR_EE_n_OUTI(n,val) \ + out_dword(HWIO_IPA_IRQ_CLR_EE_n_ADDR(n),val) +#define HWIO_IPA_IRQ_CLR_EE_n_DRBIP_IMM_CMD_NO_FLSH_HZRD_IRQ_CLR_BMSK 0x20000000 +#define HWIO_IPA_IRQ_CLR_EE_n_DRBIP_IMM_CMD_NO_FLSH_HZRD_IRQ_CLR_SHFT 0x1d +#define HWIO_IPA_IRQ_CLR_EE_n_DRBIP_DATA_SCTR_CFG_ERROR_IRQ_CLR_BMSK 0x10000000 +#define HWIO_IPA_IRQ_CLR_EE_n_DRBIP_DATA_SCTR_CFG_ERROR_IRQ_CLR_SHFT 0x1c +#define HWIO_IPA_IRQ_CLR_EE_n_DRBIP_PKT_EXCEED_MAX_SIZE_IRQ_CLR_BMSK 0x8000000 +#define HWIO_IPA_IRQ_CLR_EE_n_DRBIP_PKT_EXCEED_MAX_SIZE_IRQ_CLR_SHFT 0x1b +#define HWIO_IPA_IRQ_CLR_EE_n_TLV_LEN_MIN_DSM_IRQ_CLR_BMSK 0x4000000 +#define HWIO_IPA_IRQ_CLR_EE_n_TLV_LEN_MIN_DSM_IRQ_CLR_SHFT 0x1a +#define HWIO_IPA_IRQ_CLR_EE_n_GSI_UC_IRQ_CLR_BMSK 0x2000000 +#define HWIO_IPA_IRQ_CLR_EE_n_GSI_UC_IRQ_CLR_SHFT 0x19 +#define HWIO_IPA_IRQ_CLR_EE_n_GSI_IPA_IF_TLV_RCVD_IRQ_CLR_BMSK 0x1000000 +#define HWIO_IPA_IRQ_CLR_EE_n_GSI_IPA_IF_TLV_RCVD_IRQ_CLR_SHFT 0x18 +#define HWIO_IPA_IRQ_CLR_EE_n_GSI_EE_IRQ_CLR_BMSK 0x800000 +#define HWIO_IPA_IRQ_CLR_EE_n_GSI_EE_IRQ_CLR_SHFT 0x17 +#define HWIO_IPA_IRQ_CLR_EE_n_UCP_IRQ_CLR_BMSK 0x200000 +#define HWIO_IPA_IRQ_CLR_EE_n_UCP_IRQ_CLR_SHFT 0x15 +#define HWIO_IPA_IRQ_CLR_EE_n_PIPE_RED_MARKER_ABOVE_IRQ_CLR_BMSK 0x100000 +#define HWIO_IPA_IRQ_CLR_EE_n_PIPE_RED_MARKER_ABOVE_IRQ_CLR_SHFT 0x14 +#define HWIO_IPA_IRQ_CLR_EE_n_PIPE_YELLOW_MARKER_ABOVE_IRQ_CLR_BMSK 0x80000 +#define HWIO_IPA_IRQ_CLR_EE_n_PIPE_YELLOW_MARKER_ABOVE_IRQ_CLR_SHFT 0x13 +#define HWIO_IPA_IRQ_CLR_EE_n_PIPE_RED_MARKER_BELOW_IRQ_CLR_BMSK 0x40000 +#define HWIO_IPA_IRQ_CLR_EE_n_PIPE_RED_MARKER_BELOW_IRQ_CLR_SHFT 0x12 +#define HWIO_IPA_IRQ_CLR_EE_n_PIPE_YELLOW_MARKER_BELOW_IRQ_CLR_BMSK 0x20000 +#define HWIO_IPA_IRQ_CLR_EE_n_PIPE_YELLOW_MARKER_BELOW_IRQ_CLR_SHFT 0x11 +#define HWIO_IPA_IRQ_CLR_EE_n_BAM_GSI_IDLE_IRQ_CLR_BMSK 0x10000 +#define HWIO_IPA_IRQ_CLR_EE_n_BAM_GSI_IDLE_IRQ_CLR_SHFT 0x10 +#define HWIO_IPA_IRQ_CLR_EE_n_TX_HOLB_DROP_IRQ_CLR_BMSK 0x8000 +#define HWIO_IPA_IRQ_CLR_EE_n_TX_HOLB_DROP_IRQ_CLR_SHFT 0xf +#define HWIO_IPA_IRQ_CLR_EE_n_TX_SUSPEND_IRQ_CLR_BMSK 0x4000 +#define HWIO_IPA_IRQ_CLR_EE_n_TX_SUSPEND_IRQ_CLR_SHFT 0xe +#define HWIO_IPA_IRQ_CLR_EE_n_PROC_ERR_IRQ_CLR_BMSK 0x2000 +#define HWIO_IPA_IRQ_CLR_EE_n_PROC_ERR_IRQ_CLR_SHFT 0xd +#define HWIO_IPA_IRQ_CLR_EE_n_STEP_MODE_IRQ_CLR_BMSK 0x1000 +#define HWIO_IPA_IRQ_CLR_EE_n_STEP_MODE_IRQ_CLR_SHFT 0xc +#define HWIO_IPA_IRQ_CLR_EE_n_TX_ERR_IRQ_CLR_BMSK 0x800 +#define HWIO_IPA_IRQ_CLR_EE_n_TX_ERR_IRQ_CLR_SHFT 0xb +#define HWIO_IPA_IRQ_CLR_EE_n_DEAGGR_ERR_IRQ_CLR_BMSK 0x400 +#define HWIO_IPA_IRQ_CLR_EE_n_DEAGGR_ERR_IRQ_CLR_SHFT 0xa +#define HWIO_IPA_IRQ_CLR_EE_n_RX_ERR_IRQ_CLR_BMSK 0x200 +#define HWIO_IPA_IRQ_CLR_EE_n_RX_ERR_IRQ_CLR_SHFT 0x9 +#define HWIO_IPA_IRQ_CLR_EE_n_PROC_TO_UC_ACK_Q_NOT_EMPTY_IRQ_CLR_BMSK 0x100 +#define HWIO_IPA_IRQ_CLR_EE_n_PROC_TO_UC_ACK_Q_NOT_EMPTY_IRQ_CLR_SHFT 0x8 +#define HWIO_IPA_IRQ_CLR_EE_n_UC_RX_CMD_Q_NOT_FULL_IRQ_CLR_BMSK 0x80 +#define HWIO_IPA_IRQ_CLR_EE_n_UC_RX_CMD_Q_NOT_FULL_IRQ_CLR_SHFT 0x7 +#define HWIO_IPA_IRQ_CLR_EE_n_UC_IN_Q_NOT_EMPTY_IRQ_CLR_BMSK 0x40 +#define HWIO_IPA_IRQ_CLR_EE_n_UC_IN_Q_NOT_EMPTY_IRQ_CLR_SHFT 0x6 +#define HWIO_IPA_IRQ_CLR_EE_n_UC_IRQ_3_CLR_BMSK 0x20 +#define HWIO_IPA_IRQ_CLR_EE_n_UC_IRQ_3_CLR_SHFT 0x5 +#define HWIO_IPA_IRQ_CLR_EE_n_UC_IRQ_2_CLR_BMSK 0x10 +#define HWIO_IPA_IRQ_CLR_EE_n_UC_IRQ_2_CLR_SHFT 0x4 +#define HWIO_IPA_IRQ_CLR_EE_n_UC_IRQ_1_CLR_BMSK 0x8 +#define HWIO_IPA_IRQ_CLR_EE_n_UC_IRQ_1_CLR_SHFT 0x3 +#define HWIO_IPA_IRQ_CLR_EE_n_UC_IRQ_0_CLR_BMSK 0x4 +#define HWIO_IPA_IRQ_CLR_EE_n_UC_IRQ_0_CLR_SHFT 0x2 +#define HWIO_IPA_IRQ_CLR_EE_n_BAD_SNOC_ACCESS_IRQ_CLR_BMSK 0x1 +#define HWIO_IPA_IRQ_CLR_EE_n_BAD_SNOC_ACCESS_IRQ_CLR_SHFT 0x0 + +#define HWIO_IPA_SNOC_FEC_EE_n_ADDR(n) (IPA_EE_REG_BASE + 0x00000018 + 0x1000 * (n)) +#define HWIO_IPA_SNOC_FEC_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + 0x00000018 + 0x1000 * (n)) +#define HWIO_IPA_SNOC_FEC_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + 0x00000018 + 0x1000 * (n)) +#define HWIO_IPA_SNOC_FEC_EE_n_RMSK 0xb001ffff +#define HWIO_IPA_SNOC_FEC_EE_n_MAXn 3 +#define HWIO_IPA_SNOC_FEC_EE_n_ATTR 0x3 +#define HWIO_IPA_SNOC_FEC_EE_n_INI(n) \ + in_dword_masked(HWIO_IPA_SNOC_FEC_EE_n_ADDR(n), HWIO_IPA_SNOC_FEC_EE_n_RMSK) +#define HWIO_IPA_SNOC_FEC_EE_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_SNOC_FEC_EE_n_ADDR(n), mask) +#define HWIO_IPA_SNOC_FEC_EE_n_OUTI(n,val) \ + out_dword(HWIO_IPA_SNOC_FEC_EE_n_ADDR(n),val) +#define HWIO_IPA_SNOC_FEC_EE_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_SNOC_FEC_EE_n_ADDR(n),mask,val,HWIO_IPA_SNOC_FEC_EE_n_INI(n)) +#define HWIO_IPA_SNOC_FEC_EE_n_DIRECTION_BMSK 0x80000000 +#define HWIO_IPA_SNOC_FEC_EE_n_DIRECTION_SHFT 0x1f +#define HWIO_IPA_SNOC_FEC_EE_n_CLEAR_BMSK 0x20000000 +#define HWIO_IPA_SNOC_FEC_EE_n_CLEAR_SHFT 0x1d +#define HWIO_IPA_SNOC_FEC_EE_n_VALID_BMSK 0x10000000 +#define HWIO_IPA_SNOC_FEC_EE_n_VALID_SHFT 0x1c +#define HWIO_IPA_SNOC_FEC_EE_n_TID_BMSK 0x1f000 +#define HWIO_IPA_SNOC_FEC_EE_n_TID_SHFT 0xc +#define HWIO_IPA_SNOC_FEC_EE_n_NOC_MASTER_BMSK 0xe00 +#define HWIO_IPA_SNOC_FEC_EE_n_NOC_MASTER_SHFT 0x9 +#define HWIO_IPA_SNOC_FEC_EE_n_NOC_PORT_BMSK 0x100 +#define HWIO_IPA_SNOC_FEC_EE_n_NOC_PORT_SHFT 0x8 +#define HWIO_IPA_SNOC_FEC_EE_n_CLIENT_BMSK 0xff +#define HWIO_IPA_SNOC_FEC_EE_n_CLIENT_SHFT 0x0 + +#define HWIO_IPA_IRQ_EE_UC_n_ADDR(n) (IPA_EE_REG_BASE + 0x0000001c + 0x1000 * (n)) +#define HWIO_IPA_IRQ_EE_UC_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + 0x0000001c + 0x1000 * (n)) +#define HWIO_IPA_IRQ_EE_UC_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + 0x0000001c + 0x1000 * (n)) +#define HWIO_IPA_IRQ_EE_UC_n_RMSK 0x1 +#define HWIO_IPA_IRQ_EE_UC_n_MAXn 3 +#define HWIO_IPA_IRQ_EE_UC_n_ATTR 0x2 +#define HWIO_IPA_IRQ_EE_UC_n_OUTI(n,val) \ + out_dword(HWIO_IPA_IRQ_EE_UC_n_ADDR(n),val) +#define HWIO_IPA_IRQ_EE_UC_n_INTR_BMSK 0x1 +#define HWIO_IPA_IRQ_EE_UC_n_INTR_SHFT 0x0 + +#define HWIO_IPA_FEC_ADDR_EE_n_ADDR(n) (IPA_EE_REG_BASE + 0x00000020 + 0x1000 * (n)) +#define HWIO_IPA_FEC_ADDR_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + 0x00000020 + 0x1000 * (n)) +#define HWIO_IPA_FEC_ADDR_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + 0x00000020 + 0x1000 * (n)) +#define HWIO_IPA_FEC_ADDR_EE_n_RMSK 0xffffffff +#define HWIO_IPA_FEC_ADDR_EE_n_MAXn 3 +#define HWIO_IPA_FEC_ADDR_EE_n_ATTR 0x1 +#define HWIO_IPA_FEC_ADDR_EE_n_INI(n) \ + in_dword_masked(HWIO_IPA_FEC_ADDR_EE_n_ADDR(n), HWIO_IPA_FEC_ADDR_EE_n_RMSK) +#define HWIO_IPA_FEC_ADDR_EE_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_FEC_ADDR_EE_n_ADDR(n), mask) +#define HWIO_IPA_FEC_ADDR_EE_n_ADDR_BMSK 0xffffffff +#define HWIO_IPA_FEC_ADDR_EE_n_ADDR_SHFT 0x0 + +#define HWIO_IPA_FEC_ADDR_MSB_EE_n_ADDR(n) (IPA_EE_REG_BASE + 0x00000024 + 0x1000 * (n)) +#define HWIO_IPA_FEC_ADDR_MSB_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + 0x00000024 + 0x1000 * (n)) +#define HWIO_IPA_FEC_ADDR_MSB_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + 0x00000024 + 0x1000 * (n)) +#define HWIO_IPA_FEC_ADDR_MSB_EE_n_RMSK 0xffffffff +#define HWIO_IPA_FEC_ADDR_MSB_EE_n_MAXn 3 +#define HWIO_IPA_FEC_ADDR_MSB_EE_n_ATTR 0x1 +#define HWIO_IPA_FEC_ADDR_MSB_EE_n_INI(n) \ + in_dword_masked(HWIO_IPA_FEC_ADDR_MSB_EE_n_ADDR(n), HWIO_IPA_FEC_ADDR_MSB_EE_n_RMSK) +#define HWIO_IPA_FEC_ADDR_MSB_EE_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_FEC_ADDR_MSB_EE_n_ADDR(n), mask) +#define HWIO_IPA_FEC_ADDR_MSB_EE_n_ADDR_BMSK 0xffffffff +#define HWIO_IPA_FEC_ADDR_MSB_EE_n_ADDR_SHFT 0x0 + +#define HWIO_IPA_FEC_ATTR_EE_n_ADDR(n) (IPA_EE_REG_BASE + 0x00000028 + 0x1000 * (n)) +#define HWIO_IPA_FEC_ATTR_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + 0x00000028 + 0x1000 * (n)) +#define HWIO_IPA_FEC_ATTR_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + 0x00000028 + 0x1000 * (n)) +#define HWIO_IPA_FEC_ATTR_EE_n_RMSK 0xffffffff +#define HWIO_IPA_FEC_ATTR_EE_n_MAXn 3 +#define HWIO_IPA_FEC_ATTR_EE_n_ATTR 0x1 +#define HWIO_IPA_FEC_ATTR_EE_n_INI(n) \ + in_dword_masked(HWIO_IPA_FEC_ATTR_EE_n_ADDR(n), HWIO_IPA_FEC_ATTR_EE_n_RMSK) +#define HWIO_IPA_FEC_ATTR_EE_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_FEC_ATTR_EE_n_ADDR(n), mask) +#define HWIO_IPA_FEC_ATTR_EE_n_ERROR_INFO_BMSK 0xffffffc0 +#define HWIO_IPA_FEC_ATTR_EE_n_ERROR_INFO_SHFT 0x6 +#define HWIO_IPA_FEC_ATTR_EE_n_OPCODE_BMSK 0x3f +#define HWIO_IPA_FEC_ATTR_EE_n_OPCODE_SHFT 0x0 + +#define HWIO_IPA_DRBIP_FEC_INFO_EE_n_ADDR(n) (IPA_EE_REG_BASE + 0x00000060 + 0x1000 * (n)) +#define HWIO_IPA_DRBIP_FEC_INFO_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + 0x00000060 + 0x1000 * (n)) +#define HWIO_IPA_DRBIP_FEC_INFO_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + 0x00000060 + 0x1000 * (n)) +#define HWIO_IPA_DRBIP_FEC_INFO_EE_n_RMSK 0xffffffff +#define HWIO_IPA_DRBIP_FEC_INFO_EE_n_MAXn 3 +#define HWIO_IPA_DRBIP_FEC_INFO_EE_n_ATTR 0x1 +#define HWIO_IPA_DRBIP_FEC_INFO_EE_n_INI(n) \ + in_dword_masked(HWIO_IPA_DRBIP_FEC_INFO_EE_n_ADDR(n), HWIO_IPA_DRBIP_FEC_INFO_EE_n_RMSK) +#define HWIO_IPA_DRBIP_FEC_INFO_EE_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_DRBIP_FEC_INFO_EE_n_ADDR(n), mask) +#define HWIO_IPA_DRBIP_FEC_INFO_EE_n_AVAIL_DATA_SECTORS_BMSK 0xff000000 +#define HWIO_IPA_DRBIP_FEC_INFO_EE_n_AVAIL_DATA_SECTORS_SHFT 0x18 +#define HWIO_IPA_DRBIP_FEC_INFO_EE_n_REQUIRED_DATA_SECTORS_BMSK 0xff0000 +#define HWIO_IPA_DRBIP_FEC_INFO_EE_n_REQUIRED_DATA_SECTORS_SHFT 0x10 +#define HWIO_IPA_DRBIP_FEC_INFO_EE_n_SRC_PIPE_BMSK 0xff00 +#define HWIO_IPA_DRBIP_FEC_INFO_EE_n_SRC_PIPE_SHFT 0x8 +#define HWIO_IPA_DRBIP_FEC_INFO_EE_n_SRC_GRP_BMSK 0xf0 +#define HWIO_IPA_DRBIP_FEC_INFO_EE_n_SRC_GRP_SHFT 0x4 +#define HWIO_IPA_DRBIP_FEC_INFO_EE_n_ERROR_CODE_BMSK 0xf +#define HWIO_IPA_DRBIP_FEC_INFO_EE_n_ERROR_CODE_SHFT 0x0 + +#define HWIO_IPA_DRBIP_FEC_INFO_EXT_EE_n_ADDR(n) (IPA_EE_REG_BASE + 0x00000064 + 0x1000 * (n)) +#define HWIO_IPA_DRBIP_FEC_INFO_EXT_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + 0x00000064 + 0x1000 * (n)) +#define HWIO_IPA_DRBIP_FEC_INFO_EXT_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + 0x00000064 + 0x1000 * (n)) +#define HWIO_IPA_DRBIP_FEC_INFO_EXT_EE_n_RMSK 0xffffff +#define HWIO_IPA_DRBIP_FEC_INFO_EXT_EE_n_MAXn 3 +#define HWIO_IPA_DRBIP_FEC_INFO_EXT_EE_n_ATTR 0x1 +#define HWIO_IPA_DRBIP_FEC_INFO_EXT_EE_n_INI(n) \ + in_dword_masked(HWIO_IPA_DRBIP_FEC_INFO_EXT_EE_n_ADDR(n), HWIO_IPA_DRBIP_FEC_INFO_EXT_EE_n_RMSK) +#define HWIO_IPA_DRBIP_FEC_INFO_EXT_EE_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_DRBIP_FEC_INFO_EXT_EE_n_ADDR(n), mask) +#define HWIO_IPA_DRBIP_FEC_INFO_EXT_EE_n_OPOCODE_BMSK 0xff0000 +#define HWIO_IPA_DRBIP_FEC_INFO_EXT_EE_n_OPOCODE_SHFT 0x10 +#define HWIO_IPA_DRBIP_FEC_INFO_EXT_EE_n_SIZE_BMSK 0xffff +#define HWIO_IPA_DRBIP_FEC_INFO_EXT_EE_n_SIZE_SHFT 0x0 + +#define HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_REG_k_ADDR(n,k) (IPA_EE_REG_BASE + 0x00000030 + 0x1000 * (n) + 0x4 * (k)) +#define HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_REG_k_PHYS(n,k) (IPA_EE_REG_BASE_PHYS + 0x00000030 + 0x1000 * (n) + 0x4 * (k)) +#define HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_REG_k_OFFS(n,k) (IPA_EE_REG_BASE_OFFS + 0x00000030 + 0x1000 * (n) + 0x4 * (k)) +#define HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_REG_k_RMSK 0xffffffff +#define HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_REG_k_MAXn 3 +#define HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_REG_k_MAXk 1 +#define HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_REG_k_ATTR 0x1 +#define HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_REG_k_INI2(n,k) \ + in_dword_masked(HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_REG_k_ADDR(n,k), HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_REG_k_RMSK) +#define HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_REG_k_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_REG_k_ADDR(n,k), mask) +#define HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_REG_k_ENDPOINTS_BMSK 0xffffffff +#define HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_REG_k_ENDPOINTS_SHFT 0x0 + +#define HWIO_IPA_SUSPEND_IRQ_EN_EE_n_REG_k_ADDR(n,k) (IPA_EE_REG_BASE + 0x00000050 + 0x1000 * (n) + 0x4 * (k)) +#define HWIO_IPA_SUSPEND_IRQ_EN_EE_n_REG_k_PHYS(n,k) (IPA_EE_REG_BASE_PHYS + 0x00000050 + 0x1000 * (n) + 0x4 * (k)) +#define HWIO_IPA_SUSPEND_IRQ_EN_EE_n_REG_k_OFFS(n,k) (IPA_EE_REG_BASE_OFFS + 0x00000050 + 0x1000 * (n) + 0x4 * (k)) +#define HWIO_IPA_SUSPEND_IRQ_EN_EE_n_REG_k_RMSK 0xffffffff +#define HWIO_IPA_SUSPEND_IRQ_EN_EE_n_REG_k_MAXn 3 +#define HWIO_IPA_SUSPEND_IRQ_EN_EE_n_REG_k_MAXk 1 +#define HWIO_IPA_SUSPEND_IRQ_EN_EE_n_REG_k_ATTR 0x3 +#define HWIO_IPA_SUSPEND_IRQ_EN_EE_n_REG_k_INI2(n,k) \ + in_dword_masked(HWIO_IPA_SUSPEND_IRQ_EN_EE_n_REG_k_ADDR(n,k), HWIO_IPA_SUSPEND_IRQ_EN_EE_n_REG_k_RMSK) +#define HWIO_IPA_SUSPEND_IRQ_EN_EE_n_REG_k_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_SUSPEND_IRQ_EN_EE_n_REG_k_ADDR(n,k), mask) +#define HWIO_IPA_SUSPEND_IRQ_EN_EE_n_REG_k_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_SUSPEND_IRQ_EN_EE_n_REG_k_ADDR(n,k),val) +#define HWIO_IPA_SUSPEND_IRQ_EN_EE_n_REG_k_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_SUSPEND_IRQ_EN_EE_n_REG_k_ADDR(n,k),mask,val,HWIO_IPA_SUSPEND_IRQ_EN_EE_n_REG_k_INI2(n,k)) +#define HWIO_IPA_SUSPEND_IRQ_EN_EE_n_REG_k_ENDPOINTS_BMSK 0xffffffff +#define HWIO_IPA_SUSPEND_IRQ_EN_EE_n_REG_k_ENDPOINTS_SHFT 0x0 + +#define HWIO_IPA_SUSPEND_IRQ_CLR_EE_n_REG_k_ADDR(n,k) (IPA_EE_REG_BASE + 0x00000070 + 0x1000 * (n) + 0x4 * (k)) +#define HWIO_IPA_SUSPEND_IRQ_CLR_EE_n_REG_k_PHYS(n,k) (IPA_EE_REG_BASE_PHYS + 0x00000070 + 0x1000 * (n) + 0x4 * (k)) +#define HWIO_IPA_SUSPEND_IRQ_CLR_EE_n_REG_k_OFFS(n,k) (IPA_EE_REG_BASE_OFFS + 0x00000070 + 0x1000 * (n) + 0x4 * (k)) +#define HWIO_IPA_SUSPEND_IRQ_CLR_EE_n_REG_k_RMSK 0xffffffff +#define HWIO_IPA_SUSPEND_IRQ_CLR_EE_n_REG_k_MAXn 3 +#define HWIO_IPA_SUSPEND_IRQ_CLR_EE_n_REG_k_MAXk 1 +#define HWIO_IPA_SUSPEND_IRQ_CLR_EE_n_REG_k_ATTR 0x2 +#define HWIO_IPA_SUSPEND_IRQ_CLR_EE_n_REG_k_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_SUSPEND_IRQ_CLR_EE_n_REG_k_ADDR(n,k),val) +#define HWIO_IPA_SUSPEND_IRQ_CLR_EE_n_REG_k_ENDPOINTS_BMSK 0xffffffff +#define HWIO_IPA_SUSPEND_IRQ_CLR_EE_n_REG_k_ENDPOINTS_SHFT 0x0 + +#define HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_REG_k_ADDR(n,k) (IPA_EE_REG_BASE + 0x00000090 + 0x1000 * (n) + 0x4 * (k)) +#define HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_REG_k_PHYS(n,k) (IPA_EE_REG_BASE_PHYS + 0x00000090 + 0x1000 * (n) + 0x4 * (k)) +#define HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_REG_k_OFFS(n,k) (IPA_EE_REG_BASE_OFFS + 0x00000090 + 0x1000 * (n) + 0x4 * (k)) +#define HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_REG_k_RMSK 0xffffffff +#define HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_REG_k_MAXn 3 +#define HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_REG_k_MAXk 1 +#define HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_REG_k_ATTR 0x1 +#define HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_REG_k_INI2(n,k) \ + in_dword_masked(HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_REG_k_ADDR(n,k), HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_REG_k_RMSK) +#define HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_REG_k_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_REG_k_ADDR(n,k), mask) +#define HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_REG_k_ENDPOINTS_BMSK 0xffffffff +#define HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_REG_k_ENDPOINTS_SHFT 0x0 + +#define HWIO_IPA_HOLB_DROP_IRQ_EN_EE_n_REG_k_ADDR(n,k) (IPA_EE_REG_BASE + 0x000000b0 + 0x1000 * (n) + 0x4 * (k)) +#define HWIO_IPA_HOLB_DROP_IRQ_EN_EE_n_REG_k_PHYS(n,k) (IPA_EE_REG_BASE_PHYS + 0x000000b0 + 0x1000 * (n) + 0x4 * (k)) +#define HWIO_IPA_HOLB_DROP_IRQ_EN_EE_n_REG_k_OFFS(n,k) (IPA_EE_REG_BASE_OFFS + 0x000000b0 + 0x1000 * (n) + 0x4 * (k)) +#define HWIO_IPA_HOLB_DROP_IRQ_EN_EE_n_REG_k_RMSK 0xffffffff +#define HWIO_IPA_HOLB_DROP_IRQ_EN_EE_n_REG_k_MAXn 3 +#define HWIO_IPA_HOLB_DROP_IRQ_EN_EE_n_REG_k_MAXk 1 +#define HWIO_IPA_HOLB_DROP_IRQ_EN_EE_n_REG_k_ATTR 0x3 +#define HWIO_IPA_HOLB_DROP_IRQ_EN_EE_n_REG_k_INI2(n,k) \ + in_dword_masked(HWIO_IPA_HOLB_DROP_IRQ_EN_EE_n_REG_k_ADDR(n,k), HWIO_IPA_HOLB_DROP_IRQ_EN_EE_n_REG_k_RMSK) +#define HWIO_IPA_HOLB_DROP_IRQ_EN_EE_n_REG_k_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_HOLB_DROP_IRQ_EN_EE_n_REG_k_ADDR(n,k), mask) +#define HWIO_IPA_HOLB_DROP_IRQ_EN_EE_n_REG_k_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_HOLB_DROP_IRQ_EN_EE_n_REG_k_ADDR(n,k),val) +#define HWIO_IPA_HOLB_DROP_IRQ_EN_EE_n_REG_k_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_HOLB_DROP_IRQ_EN_EE_n_REG_k_ADDR(n,k),mask,val,HWIO_IPA_HOLB_DROP_IRQ_EN_EE_n_REG_k_INI2(n,k)) +#define HWIO_IPA_HOLB_DROP_IRQ_EN_EE_n_REG_k_ENDPOINTS_BMSK 0xffffffff +#define HWIO_IPA_HOLB_DROP_IRQ_EN_EE_n_REG_k_ENDPOINTS_SHFT 0x0 + +#define HWIO_IPA_HOLB_DROP_IRQ_CLR_EE_n_REG_k_ADDR(n,k) (IPA_EE_REG_BASE + 0x000000c0 + 0x1000 * (n) + 0x4 * (k)) +#define HWIO_IPA_HOLB_DROP_IRQ_CLR_EE_n_REG_k_PHYS(n,k) (IPA_EE_REG_BASE_PHYS + 0x000000c0 + 0x1000 * (n) + 0x4 * (k)) +#define HWIO_IPA_HOLB_DROP_IRQ_CLR_EE_n_REG_k_OFFS(n,k) (IPA_EE_REG_BASE_OFFS + 0x000000c0 + 0x1000 * (n) + 0x4 * (k)) +#define HWIO_IPA_HOLB_DROP_IRQ_CLR_EE_n_REG_k_RMSK 0xffffffff +#define HWIO_IPA_HOLB_DROP_IRQ_CLR_EE_n_REG_k_MAXn 3 +#define HWIO_IPA_HOLB_DROP_IRQ_CLR_EE_n_REG_k_MAXk 1 +#define HWIO_IPA_HOLB_DROP_IRQ_CLR_EE_n_REG_k_ATTR 0x2 +#define HWIO_IPA_HOLB_DROP_IRQ_CLR_EE_n_REG_k_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_HOLB_DROP_IRQ_CLR_EE_n_REG_k_ADDR(n,k),val) +#define HWIO_IPA_HOLB_DROP_IRQ_CLR_EE_n_REG_k_ENDPOINTS_BMSK 0xffffffff +#define HWIO_IPA_HOLB_DROP_IRQ_CLR_EE_n_REG_k_ENDPOINTS_SHFT 0x0 + +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_0_ADDR (IPA_EE_REG_BASE + 0x00001100) +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_0_PHYS (IPA_EE_REG_BASE_PHYS + 0x00001100) +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_0_OFFS (IPA_EE_REG_BASE_OFFS + 0x00001100) +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_0_RMSK 0xff1ff0ff +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_0_ATTR 0x1 +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_0_IN \ + in_dword_masked(HWIO_IPA_MODEM_BEARER_INIT_VALUES_0_ADDR, HWIO_IPA_MODEM_BEARER_INIT_VALUES_0_RMSK) +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_0_INM(m) \ + in_dword_masked(HWIO_IPA_MODEM_BEARER_INIT_VALUES_0_ADDR, m) +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_0_MODEM_BEARER_INIT_BEARER_BMSK 0xff000000 +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_0_MODEM_BEARER_INIT_BEARER_SHFT 0x18 +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_0_MODEM_BEARER_INIT_CPHR_KEY_INDX_BMSK 0x1f0000 +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_0_MODEM_BEARER_INIT_CPHR_KEY_INDX_SHFT 0x10 +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_0_MODEM_BEARER_INIT_CPHR_ALGORITHM_BMSK 0xf000 +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_0_MODEM_BEARER_INIT_CPHR_ALGORITHM_SHFT 0xc +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_0_MODEM_BEARER_INIT_L2_HDR_SIZE_BMSK 0xff +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_0_MODEM_BEARER_INIT_L2_HDR_SIZE_SHFT 0x0 + +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_1_ADDR (IPA_EE_REG_BASE + 0x00001104) +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_1_PHYS (IPA_EE_REG_BASE_PHYS + 0x00001104) +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_1_OFFS (IPA_EE_REG_BASE_OFFS + 0x00001104) +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_1_RMSK 0xffffffff +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_1_ATTR 0x1 +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_1_IN \ + in_dword_masked(HWIO_IPA_MODEM_BEARER_INIT_VALUES_1_ADDR, HWIO_IPA_MODEM_BEARER_INIT_VALUES_1_RMSK) +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_1_INM(m) \ + in_dword_masked(HWIO_IPA_MODEM_BEARER_INIT_VALUES_1_ADDR, m) +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_1_MODEM_BEARER_INIT_BEARER_SEL_BMSK 0x80000000 +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_1_MODEM_BEARER_INIT_BEARER_SEL_SHFT 0x1f +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_1_MODEM_BEARER_INIT_DIRECTION_BMSK 0x40000000 +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_1_MODEM_BEARER_INIT_DIRECTION_SHFT 0x1e +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_1_MODEM_BEARER_INIT_CPHR_OFST_START_BMSK 0x3fff0000 +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_1_MODEM_BEARER_INIT_CPHR_OFST_START_SHFT 0x10 +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_1_MODEM_BEARER_INIT_CPHR_OFST_KEYSTRM_BMSK 0xffff +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_1_MODEM_BEARER_INIT_CPHR_OFST_KEYSTRM_SHFT 0x0 + +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_2_ADDR (IPA_EE_REG_BASE + 0x00001108) +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_2_PHYS (IPA_EE_REG_BASE_PHYS + 0x00001108) +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_2_OFFS (IPA_EE_REG_BASE_OFFS + 0x00001108) +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_2_RMSK 0x31ff +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_2_ATTR 0x1 +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_2_IN \ + in_dword_masked(HWIO_IPA_MODEM_BEARER_INIT_VALUES_2_ADDR, HWIO_IPA_MODEM_BEARER_INIT_VALUES_2_RMSK) +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_2_INM(m) \ + in_dword_masked(HWIO_IPA_MODEM_BEARER_INIT_VALUES_2_ADDR, m) +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_2_MODEM_BEARER_INIT_IP_MACI_SIZE_BMSK 0x3000 +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_2_MODEM_BEARER_INIT_IP_MACI_SIZE_SHFT 0xc +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_2_MODEM_BEARER_INIT_IP_KEY_INDX_BMSK 0x1f0 +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_2_MODEM_BEARER_INIT_IP_KEY_INDX_SHFT 0x4 +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_2_MODEM_BEARER_INIT_IP_ALGORITHM_BMSK 0xf +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_2_MODEM_BEARER_INIT_IP_ALGORITHM_SHFT 0x0 + +#define HWIO_IPA_MODEM_BEARER_CONFIG_VALUES_0_ADDR (IPA_EE_REG_BASE + 0x0000110c) +#define HWIO_IPA_MODEM_BEARER_CONFIG_VALUES_0_PHYS (IPA_EE_REG_BASE_PHYS + 0x0000110c) +#define HWIO_IPA_MODEM_BEARER_CONFIG_VALUES_0_OFFS (IPA_EE_REG_BASE_OFFS + 0x0000110c) +#define HWIO_IPA_MODEM_BEARER_CONFIG_VALUES_0_RMSK 0xffffffff +#define HWIO_IPA_MODEM_BEARER_CONFIG_VALUES_0_ATTR 0x1 +#define HWIO_IPA_MODEM_BEARER_CONFIG_VALUES_0_IN \ + in_dword_masked(HWIO_IPA_MODEM_BEARER_CONFIG_VALUES_0_ADDR, HWIO_IPA_MODEM_BEARER_CONFIG_VALUES_0_RMSK) +#define HWIO_IPA_MODEM_BEARER_CONFIG_VALUES_0_INM(m) \ + in_dword_masked(HWIO_IPA_MODEM_BEARER_CONFIG_VALUES_0_ADDR, m) +#define HWIO_IPA_MODEM_BEARER_CONFIG_VALUES_0_MODEM_BEARER_CONFIG_COUNT_F_BMSK 0xffffffff +#define HWIO_IPA_MODEM_BEARER_CONFIG_VALUES_0_MODEM_BEARER_CONFIG_COUNT_F_SHFT 0x0 + +#define HWIO_IPA_MODEM_BEARER_CONFIG_VALUES_1_ADDR (IPA_EE_REG_BASE + 0x00001110) +#define HWIO_IPA_MODEM_BEARER_CONFIG_VALUES_1_PHYS (IPA_EE_REG_BASE_PHYS + 0x00001110) +#define HWIO_IPA_MODEM_BEARER_CONFIG_VALUES_1_OFFS (IPA_EE_REG_BASE_OFFS + 0x00001110) +#define HWIO_IPA_MODEM_BEARER_CONFIG_VALUES_1_RMSK 0xffff +#define HWIO_IPA_MODEM_BEARER_CONFIG_VALUES_1_ATTR 0x1 +#define HWIO_IPA_MODEM_BEARER_CONFIG_VALUES_1_IN \ + in_dword_masked(HWIO_IPA_MODEM_BEARER_CONFIG_VALUES_1_ADDR, HWIO_IPA_MODEM_BEARER_CONFIG_VALUES_1_RMSK) +#define HWIO_IPA_MODEM_BEARER_CONFIG_VALUES_1_INM(m) \ + in_dword_masked(HWIO_IPA_MODEM_BEARER_CONFIG_VALUES_1_ADDR, m) +#define HWIO_IPA_MODEM_BEARER_CONFIG_VALUES_1_MODEM_BEARER_CONFIG_SIZE_F_BMSK 0xffff +#define HWIO_IPA_MODEM_BEARER_CONFIG_VALUES_1_MODEM_BEARER_CONFIG_SIZE_F_SHFT 0x0 + +#define HWIO_IPA_SECURED_PIPES_n_ADDR(n) (IPA_EE_REG_BASE + 0x00001120 + 0x4 * (n)) +#define HWIO_IPA_SECURED_PIPES_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + 0x00001120 + 0x4 * (n)) +#define HWIO_IPA_SECURED_PIPES_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + 0x00001120 + 0x4 * (n)) +#define HWIO_IPA_SECURED_PIPES_n_RMSK 0xffffffff +#define HWIO_IPA_SECURED_PIPES_n_MAXn 1 +#define HWIO_IPA_SECURED_PIPES_n_ATTR 0x3 +#define HWIO_IPA_SECURED_PIPES_n_INI(n) \ + in_dword_masked(HWIO_IPA_SECURED_PIPES_n_ADDR(n), HWIO_IPA_SECURED_PIPES_n_RMSK) +#define HWIO_IPA_SECURED_PIPES_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_SECURED_PIPES_n_ADDR(n), mask) +#define HWIO_IPA_SECURED_PIPES_n_OUTI(n,val) \ + out_dword(HWIO_IPA_SECURED_PIPES_n_ADDR(n),val) +#define HWIO_IPA_SECURED_PIPES_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_SECURED_PIPES_n_ADDR(n),mask,val,HWIO_IPA_SECURED_PIPES_n_INI(n)) +#define HWIO_IPA_SECURED_PIPES_n_ENDPOINTS_BMSK 0xffffffff +#define HWIO_IPA_SECURED_PIPES_n_ENDPOINTS_SHFT 0x0 + +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_CFG_ADDR (IPA_EE_REG_BASE + 0x00001140) +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_CFG_PHYS (IPA_EE_REG_BASE_PHYS + 0x00001140) +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_CFG_OFFS (IPA_EE_REG_BASE_OFFS + 0x00001140) +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_CFG_RMSK 0x3 +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_CFG_ATTR 0x3 +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_CFG_IN \ + in_dword_masked(HWIO_IPA_MODEM_BEARER_INIT_VALUES_CFG_ADDR, HWIO_IPA_MODEM_BEARER_INIT_VALUES_CFG_RMSK) +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_MODEM_BEARER_INIT_VALUES_CFG_ADDR, m) +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_CFG_OUT(v) \ + out_dword(HWIO_IPA_MODEM_BEARER_INIT_VALUES_CFG_ADDR,v) +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_MODEM_BEARER_INIT_VALUES_CFG_ADDR,m,v,HWIO_IPA_MODEM_BEARER_INIT_VALUES_CFG_IN) +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_CFG_BEARER_CONTEXT_INDEX_SEL_BMSK 0x3 +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_CFG_BEARER_CONTEXT_INDEX_SEL_SHFT 0x0 + +#define HWIO_IPA_UC_REGS_INSIDE_IPA__CONTROL_ADDR (IPA_EE_REG_BASE + 0x00001200) +#define HWIO_IPA_UC_REGS_INSIDE_IPA__CONTROL_PHYS (IPA_EE_REG_BASE_PHYS + 0x00001200) +#define HWIO_IPA_UC_REGS_INSIDE_IPA__CONTROL_OFFS (IPA_EE_REG_BASE_OFFS + 0x00001200) +#define HWIO_IPA_UC_REGS_INSIDE_IPA__CONTROL_RMSK 0x1 +#define HWIO_IPA_UC_REGS_INSIDE_IPA__CONTROL_ATTR 0x3 +#define HWIO_IPA_UC_REGS_INSIDE_IPA__CONTROL_IN \ + in_dword_masked(HWIO_IPA_UC_REGS_INSIDE_IPA__CONTROL_ADDR, HWIO_IPA_UC_REGS_INSIDE_IPA__CONTROL_RMSK) +#define HWIO_IPA_UC_REGS_INSIDE_IPA__CONTROL_INM(m) \ + in_dword_masked(HWIO_IPA_UC_REGS_INSIDE_IPA__CONTROL_ADDR, m) +#define HWIO_IPA_UC_REGS_INSIDE_IPA__CONTROL_OUT(v) \ + out_dword(HWIO_IPA_UC_REGS_INSIDE_IPA__CONTROL_ADDR,v) +#define HWIO_IPA_UC_REGS_INSIDE_IPA__CONTROL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_REGS_INSIDE_IPA__CONTROL_ADDR,m,v,HWIO_IPA_UC_REGS_INSIDE_IPA__CONTROL_IN) +#define HWIO_IPA_UC_REGS_INSIDE_IPA__CONTROL_UC_ENABLE_BMSK 0x1 +#define HWIO_IPA_UC_REGS_INSIDE_IPA__CONTROL_UC_ENABLE_SHFT 0x0 + +#define HWIO_IPA_UC_REGS_INSIDE_IPA__NMI_ADDR (IPA_EE_REG_BASE + 0x00001204) +#define HWIO_IPA_UC_REGS_INSIDE_IPA__NMI_PHYS (IPA_EE_REG_BASE_PHYS + 0x00001204) +#define HWIO_IPA_UC_REGS_INSIDE_IPA__NMI_OFFS (IPA_EE_REG_BASE_OFFS + 0x00001204) +#define HWIO_IPA_UC_REGS_INSIDE_IPA__NMI_RMSK 0x1 +#define HWIO_IPA_UC_REGS_INSIDE_IPA__NMI_ATTR 0x2 +#define HWIO_IPA_UC_REGS_INSIDE_IPA__NMI_OUT(v) \ + out_dword(HWIO_IPA_UC_REGS_INSIDE_IPA__NMI_ADDR,v) +#define HWIO_IPA_UC_REGS_INSIDE_IPA__NMI_PULSE_BMSK 0x1 +#define HWIO_IPA_UC_REGS_INSIDE_IPA__NMI_PULSE_SHFT 0x0 + +#define HWIO_IPA_DRBIP_CFG_ADDR (IPA_EE_REG_BASE + 0x00001400) +#define HWIO_IPA_DRBIP_CFG_PHYS (IPA_EE_REG_BASE_PHYS + 0x00001400) +#define HWIO_IPA_DRBIP_CFG_OFFS (IPA_EE_REG_BASE_OFFS + 0x00001400) +#define HWIO_IPA_DRBIP_CFG_RMSK 0x1 +#define HWIO_IPA_DRBIP_CFG_ATTR 0x3 +#define HWIO_IPA_DRBIP_CFG_IN \ + in_dword_masked(HWIO_IPA_DRBIP_CFG_ADDR, HWIO_IPA_DRBIP_CFG_RMSK) +#define HWIO_IPA_DRBIP_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_DRBIP_CFG_ADDR, m) +#define HWIO_IPA_DRBIP_CFG_OUT(v) \ + out_dword(HWIO_IPA_DRBIP_CFG_ADDR,v) +#define HWIO_IPA_DRBIP_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_DRBIP_CFG_ADDR,m,v,HWIO_IPA_DRBIP_CFG_IN) +#define HWIO_IPA_DRBIP_CFG_OPERATION_MODE_BMSK 0x1 +#define HWIO_IPA_DRBIP_CFG_OPERATION_MODE_SHFT 0x0 + +#define HWIO_IPA_SET_UC_IRQ_EE_n_ADDR(n) (IPA_EE_REG_BASE + 0x000020e0 + 0x4 * (n)) +#define HWIO_IPA_SET_UC_IRQ_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + 0x000020e0 + 0x4 * (n)) +#define HWIO_IPA_SET_UC_IRQ_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + 0x000020e0 + 0x4 * (n)) +#define HWIO_IPA_SET_UC_IRQ_EE_n_RMSK 0xf +#define HWIO_IPA_SET_UC_IRQ_EE_n_MAXn 3 +#define HWIO_IPA_SET_UC_IRQ_EE_n_ATTR 0x2 +#define HWIO_IPA_SET_UC_IRQ_EE_n_OUTI(n,val) \ + out_dword(HWIO_IPA_SET_UC_IRQ_EE_n_ADDR(n),val) +#define HWIO_IPA_SET_UC_IRQ_EE_n_SET_UC_IRQ_3_BMSK 0x8 +#define HWIO_IPA_SET_UC_IRQ_EE_n_SET_UC_IRQ_3_SHFT 0x3 +#define HWIO_IPA_SET_UC_IRQ_EE_n_SET_UC_IRQ_2_BMSK 0x4 +#define HWIO_IPA_SET_UC_IRQ_EE_n_SET_UC_IRQ_2_SHFT 0x2 +#define HWIO_IPA_SET_UC_IRQ_EE_n_SET_UC_IRQ_1_BMSK 0x2 +#define HWIO_IPA_SET_UC_IRQ_EE_n_SET_UC_IRQ_1_SHFT 0x1 +#define HWIO_IPA_SET_UC_IRQ_EE_n_SET_UC_IRQ_0_BMSK 0x1 +#define HWIO_IPA_SET_UC_IRQ_EE_n_SET_UC_IRQ_0_SHFT 0x0 + +#define HWIO_IPA_SET_UC_IRQ_ALL_EES_ADDR (IPA_EE_REG_BASE + 0x000020f0) +#define HWIO_IPA_SET_UC_IRQ_ALL_EES_PHYS (IPA_EE_REG_BASE_PHYS + 0x000020f0) +#define HWIO_IPA_SET_UC_IRQ_ALL_EES_OFFS (IPA_EE_REG_BASE_OFFS + 0x000020f0) +#define HWIO_IPA_SET_UC_IRQ_ALL_EES_RMSK 0xf +#define HWIO_IPA_SET_UC_IRQ_ALL_EES_ATTR 0x2 +#define HWIO_IPA_SET_UC_IRQ_ALL_EES_OUT(v) \ + out_dword(HWIO_IPA_SET_UC_IRQ_ALL_EES_ADDR,v) +#define HWIO_IPA_SET_UC_IRQ_ALL_EES_SET_UC_IRQ_3_BMSK 0x8 +#define HWIO_IPA_SET_UC_IRQ_ALL_EES_SET_UC_IRQ_3_SHFT 0x3 +#define HWIO_IPA_SET_UC_IRQ_ALL_EES_SET_UC_IRQ_2_BMSK 0x4 +#define HWIO_IPA_SET_UC_IRQ_ALL_EES_SET_UC_IRQ_2_SHFT 0x2 +#define HWIO_IPA_SET_UC_IRQ_ALL_EES_SET_UC_IRQ_1_BMSK 0x2 +#define HWIO_IPA_SET_UC_IRQ_ALL_EES_SET_UC_IRQ_1_SHFT 0x1 +#define HWIO_IPA_SET_UC_IRQ_ALL_EES_SET_UC_IRQ_0_BMSK 0x1 +#define HWIO_IPA_SET_UC_IRQ_ALL_EES_SET_UC_IRQ_0_SHFT 0x0 + +#define HWIO_IPA_UCP_RESUME_ADDR (IPA_EE_REG_BASE + 0x000030e0) +#define HWIO_IPA_UCP_RESUME_PHYS (IPA_EE_REG_BASE_PHYS + 0x000030e0) +#define HWIO_IPA_UCP_RESUME_OFFS (IPA_EE_REG_BASE_OFFS + 0x000030e0) +#define HWIO_IPA_UCP_RESUME_RMSK 0x19ff36 +#define HWIO_IPA_UCP_RESUME_ATTR 0x2 +#define HWIO_IPA_UCP_RESUME_OUT(v) \ + out_dword(HWIO_IPA_UCP_RESUME_ADDR,v) +#define HWIO_IPA_UCP_RESUME_IPA_UCP_RESUME_METADATA_OVERRIDE_BMSK 0x100000 +#define HWIO_IPA_UCP_RESUME_IPA_UCP_RESUME_METADATA_OVERRIDE_SHFT 0x14 +#define HWIO_IPA_UCP_RESUME_IPA_UCP_RESUME_NEXT_PKT_PARSER_DIS_BMSK 0x80000 +#define HWIO_IPA_UCP_RESUME_IPA_UCP_RESUME_NEXT_PKT_PARSER_DIS_SHFT 0x13 +#define HWIO_IPA_UCP_RESUME_IPA_UCP_RESUME_EXCEPTION_BMSK 0x10000 +#define HWIO_IPA_UCP_RESUME_IPA_UCP_RESUME_EXCEPTION_SHFT 0x10 +#define HWIO_IPA_UCP_RESUME_IPA_UCP_RESUME_DEST_PIPE_VALUE_BMSK 0xff00 +#define HWIO_IPA_UCP_RESUME_IPA_UCP_RESUME_DEST_PIPE_VALUE_SHFT 0x8 +#define HWIO_IPA_UCP_RESUME_IPA_UCP_RESUME_TPORT_CHECKSUM_FIX_EN_BMSK 0x20 +#define HWIO_IPA_UCP_RESUME_IPA_UCP_RESUME_TPORT_CHECKSUM_FIX_EN_SHFT 0x5 +#define HWIO_IPA_UCP_RESUME_IPA_UCP_RESUME_IP_CHECKSUM_FIX_EN_BMSK 0x10 +#define HWIO_IPA_UCP_RESUME_IPA_UCP_RESUME_IP_CHECKSUM_FIX_EN_SHFT 0x4 +#define HWIO_IPA_UCP_RESUME_IPA_UCP_RESUME_DEST_PIPE_OVERRIDE_BMSK 0x4 +#define HWIO_IPA_UCP_RESUME_IPA_UCP_RESUME_DEST_PIPE_OVERRIDE_SHFT 0x2 +#define HWIO_IPA_UCP_RESUME_IPA_UCP_RESUME_NEXT_ROUND_EN_BMSK 0x2 +#define HWIO_IPA_UCP_RESUME_IPA_UCP_RESUME_NEXT_ROUND_EN_SHFT 0x1 + +#define HWIO_IPA_UCP_RESUME_METADATA_ADDR (IPA_EE_REG_BASE + 0x000030e4) +#define HWIO_IPA_UCP_RESUME_METADATA_PHYS (IPA_EE_REG_BASE_PHYS + 0x000030e4) +#define HWIO_IPA_UCP_RESUME_METADATA_OFFS (IPA_EE_REG_BASE_OFFS + 0x000030e4) +#define HWIO_IPA_UCP_RESUME_METADATA_RMSK 0xffffffff +#define HWIO_IPA_UCP_RESUME_METADATA_ATTR 0x3 +#define HWIO_IPA_UCP_RESUME_METADATA_IN \ + in_dword_masked(HWIO_IPA_UCP_RESUME_METADATA_ADDR, HWIO_IPA_UCP_RESUME_METADATA_RMSK) +#define HWIO_IPA_UCP_RESUME_METADATA_INM(m) \ + in_dword_masked(HWIO_IPA_UCP_RESUME_METADATA_ADDR, m) +#define HWIO_IPA_UCP_RESUME_METADATA_OUT(v) \ + out_dword(HWIO_IPA_UCP_RESUME_METADATA_ADDR,v) +#define HWIO_IPA_UCP_RESUME_METADATA_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UCP_RESUME_METADATA_ADDR,m,v,HWIO_IPA_UCP_RESUME_METADATA_IN) +#define HWIO_IPA_UCP_RESUME_METADATA_METADATA_BMSK 0xffffffff +#define HWIO_IPA_UCP_RESUME_METADATA_METADATA_SHFT 0x0 + +#define HWIO_IPA_PROC_UCP_CFG_ADDR (IPA_EE_REG_BASE + 0x000030e8) +#define HWIO_IPA_PROC_UCP_CFG_PHYS (IPA_EE_REG_BASE_PHYS + 0x000030e8) +#define HWIO_IPA_PROC_UCP_CFG_OFFS (IPA_EE_REG_BASE_OFFS + 0x000030e8) +#define HWIO_IPA_PROC_UCP_CFG_RMSK 0x1 +#define HWIO_IPA_PROC_UCP_CFG_ATTR 0x3 +#define HWIO_IPA_PROC_UCP_CFG_IN \ + in_dword_masked(HWIO_IPA_PROC_UCP_CFG_ADDR, HWIO_IPA_PROC_UCP_CFG_RMSK) +#define HWIO_IPA_PROC_UCP_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_PROC_UCP_CFG_ADDR, m) +#define HWIO_IPA_PROC_UCP_CFG_OUT(v) \ + out_dword(HWIO_IPA_PROC_UCP_CFG_ADDR,v) +#define HWIO_IPA_PROC_UCP_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_PROC_UCP_CFG_ADDR,m,v,HWIO_IPA_PROC_UCP_CFG_IN) +#define HWIO_IPA_PROC_UCP_CFG_IPA_UCP_IRQ_SW_EVENTS_UC_MUX_EN_BMSK 0x1 +#define HWIO_IPA_PROC_UCP_CFG_IPA_UCP_IRQ_SW_EVENTS_UC_MUX_EN_SHFT 0x0 + +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_0_ADDR (IPA_EE_REG_BASE + 0x000030ec) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_0_PHYS (IPA_EE_REG_BASE_PHYS + 0x000030ec) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_0_OFFS (IPA_EE_REG_BASE_OFFS + 0x000030ec) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_0_RMSK 0x3ffff +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_0_ATTR 0x3 +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_0_IN \ + in_dword_masked(HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_0_ADDR, HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_0_RMSK) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_0_INM(m) \ + in_dword_masked(HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_0_ADDR, m) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_0_OUT(v) \ + out_dword(HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_0_ADDR,v) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_0_ADDR,m,v,HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_0_IN) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_0_IPA_UC_PKT_PROCESS_CONTEXT_BASE_BMSK 0x3ffff +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_0_IPA_UC_PKT_PROCESS_CONTEXT_BASE_SHFT 0x0 + +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_1_ADDR (IPA_EE_REG_BASE + 0x000030f0) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_1_PHYS (IPA_EE_REG_BASE_PHYS + 0x000030f0) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_1_OFFS (IPA_EE_REG_BASE_OFFS + 0x000030f0) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_1_RMSK 0x3ffff +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_1_ATTR 0x3 +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_1_IN \ + in_dword_masked(HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_1_ADDR, HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_1_RMSK) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_1_INM(m) \ + in_dword_masked(HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_1_ADDR, m) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_1_OUT(v) \ + out_dword(HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_1_ADDR,v) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_1_ADDR,m,v,HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_1_IN) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_1_IPA_UC_PKT_PROCESS_PKT_BASE_BMSK 0x3ffff +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_1_IPA_UC_PKT_PROCESS_PKT_BASE_SHFT 0x0 + +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_2_ADDR (IPA_EE_REG_BASE + 0x000030f4) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_2_PHYS (IPA_EE_REG_BASE_PHYS + 0x000030f4) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_2_OFFS (IPA_EE_REG_BASE_OFFS + 0x000030f4) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_2_RMSK 0x3ffff +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_2_ATTR 0x3 +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_2_IN \ + in_dword_masked(HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_2_ADDR, HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_2_RMSK) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_2_INM(m) \ + in_dword_masked(HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_2_ADDR, m) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_2_OUT(v) \ + out_dword(HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_2_ADDR,v) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_2_ADDR,m,v,HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_2_IN) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_2_IPA_UC_PKT_PROCESS_HDR_BASE_BMSK 0x3ffff +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_2_IPA_UC_PKT_PROCESS_HDR_BASE_SHFT 0x0 + +/*---------------------------------------------------------------------------- + * MODULE: IPA_DEBUG + *--------------------------------------------------------------------------*/ + +#define IPA_DEBUG_REG_BASE (IPA_0_IPA_WRAPPER_BASE + 0x00148000) +#define IPA_DEBUG_REG_BASE_PHYS (IPA_0_IPA_WRAPPER_BASE_PHYS + 0x00148000) +#define IPA_DEBUG_REG_BASE_OFFS 0x00148000 + +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_ADDR (IPA_DEBUG_REG_BASE + 0x00000000) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000000) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000000) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_RMSK 0xf3f3f77 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_ATTR 0x3 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_IN \ + in_dword_masked(HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_ADDR, HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_RMSK) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_ADDR, m) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_OUT(v) \ + out_dword(HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_ADDR,v) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_ADDR,m,v,HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_IN) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_ALLOC_LIST_TYPE_BMSK 0xc000000 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_ALLOC_LIST_TYPE_SHFT 0x1a +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_ALLOC_HOLD_BMSK 0x1000000 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_ALLOC_HOLD_SHFT 0x18 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_ALLOC_LIST_ID_BMSK 0x3f0000 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_ALLOC_LIST_ID_SHFT 0x10 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_ALLOC_RSRC_ID_CURR_BMSK 0x3f00 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_ALLOC_RSRC_ID_CURR_SHFT 0x8 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_ALLOC_RSRC_GRP_BMSK 0x70 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_ALLOC_RSRC_GRP_SHFT 0x4 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_ALLOC_RSRC_TYPE_BMSK 0x7 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_ALLOC_RSRC_TYPE_SHFT 0x0 + +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_SRCH_CFG_ADDR (IPA_DEBUG_REG_BASE + 0x00000004) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_SRCH_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000004) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_SRCH_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000004) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_SRCH_CFG_RMSK 0xff7f7 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_SRCH_CFG_ATTR 0x3 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_SRCH_CFG_IN \ + in_dword_masked(HWIO_IPA_RSRC_MNGR_SW_ACCESS_SRCH_CFG_ADDR, HWIO_IPA_RSRC_MNGR_SW_ACCESS_SRCH_CFG_RMSK) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_SRCH_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_RSRC_MNGR_SW_ACCESS_SRCH_CFG_ADDR, m) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_SRCH_CFG_OUT(v) \ + out_dword(HWIO_IPA_RSRC_MNGR_SW_ACCESS_SRCH_CFG_ADDR,v) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_SRCH_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_RSRC_MNGR_SW_ACCESS_SRCH_CFG_ADDR,m,v,HWIO_IPA_RSRC_MNGR_SW_ACCESS_SRCH_CFG_IN) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_SRCH_CFG_SRCH_LIST_TYPE_BMSK 0xc0000 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_SRCH_CFG_SRCH_LIST_TYPE_SHFT 0x12 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_SRCH_CFG_SRCH_LIST_ID_BMSK 0x3f000 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_SRCH_CFG_SRCH_LIST_ID_SHFT 0xc +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_SRCH_CFG_SRCH_RSRC_CNT_BMSK 0x7f0 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_SRCH_CFG_SRCH_RSRC_CNT_SHFT 0x4 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_SRCH_CFG_SRCH_RSRC_TYPE_BMSK 0x7 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_SRCH_CFG_SRCH_RSRC_TYPE_SHFT 0x0 + +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_REL_CFG_ADDR (IPA_DEBUG_REG_BASE + 0x00000008) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_REL_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000008) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_REL_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000008) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_REL_CFG_RMSK 0xff3f77 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_REL_CFG_ATTR 0x3 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_REL_CFG_IN \ + in_dword_masked(HWIO_IPA_RSRC_MNGR_SW_ACCESS_REL_CFG_ADDR, HWIO_IPA_RSRC_MNGR_SW_ACCESS_REL_CFG_RMSK) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_REL_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_RSRC_MNGR_SW_ACCESS_REL_CFG_ADDR, m) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_REL_CFG_OUT(v) \ + out_dword(HWIO_IPA_RSRC_MNGR_SW_ACCESS_REL_CFG_ADDR,v) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_REL_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_RSRC_MNGR_SW_ACCESS_REL_CFG_ADDR,m,v,HWIO_IPA_RSRC_MNGR_SW_ACCESS_REL_CFG_IN) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_REL_CFG_REL_LIST_TYPE_BMSK 0xc00000 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_REL_CFG_REL_LIST_TYPE_SHFT 0x16 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_REL_CFG_REL_LIST_ID_BMSK 0x3f0000 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_REL_CFG_REL_LIST_ID_SHFT 0x10 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_REL_CFG_REL_RSRC_ID_BMSK 0x3f00 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_REL_CFG_REL_RSRC_ID_SHFT 0x8 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_REL_CFG_REL_RSRC_GRP_BMSK 0x70 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_REL_CFG_REL_RSRC_GRP_SHFT 0x4 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_REL_CFG_REL_RSRC_TYPE_BMSK 0x7 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_REL_CFG_REL_RSRC_TYPE_SHFT 0x0 + +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_RSRV_CFG_ADDR (IPA_DEBUG_REG_BASE + 0x0000000c) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_RSRV_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000000c) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_RSRV_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000000c) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_RSRV_CFG_RMSK 0x3f77 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_RSRV_CFG_ATTR 0x3 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_RSRV_CFG_IN \ + in_dword_masked(HWIO_IPA_RSRC_MNGR_SW_ACCESS_RSRV_CFG_ADDR, HWIO_IPA_RSRC_MNGR_SW_ACCESS_RSRV_CFG_RMSK) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_RSRV_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_RSRC_MNGR_SW_ACCESS_RSRV_CFG_ADDR, m) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_RSRV_CFG_OUT(v) \ + out_dword(HWIO_IPA_RSRC_MNGR_SW_ACCESS_RSRV_CFG_ADDR,v) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_RSRV_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_RSRC_MNGR_SW_ACCESS_RSRV_CFG_ADDR,m,v,HWIO_IPA_RSRC_MNGR_SW_ACCESS_RSRV_CFG_IN) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_RSRV_CFG_RSRV_RSRC_AMOUNT_BMSK 0x3f00 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_RSRV_CFG_RSRV_RSRC_AMOUNT_SHFT 0x8 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_RSRV_CFG_RSRV_RSRC_GRP_BMSK 0x70 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_RSRV_CFG_RSRV_RSRC_GRP_SHFT 0x4 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_RSRV_CFG_RSRV_RSRC_TYPE_BMSK 0x7 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_RSRV_CFG_RSRV_RSRC_TYPE_SHFT 0x0 + +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x00000010) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000010) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000010) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_CMD_RMSK 0xf +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_CMD_ATTR 0x2 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_CMD_OUT(v) \ + out_dword(HWIO_IPA_RSRC_MNGR_SW_ACCESS_CMD_ADDR,v) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_CMD_RSRV_VALID_BMSK 0x8 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_CMD_RSRV_VALID_SHFT 0x3 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_CMD_REL_VALID_BMSK 0x4 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_CMD_REL_VALID_SHFT 0x2 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_CMD_SRCH_VALID_BMSK 0x2 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_CMD_SRCH_VALID_SHFT 0x1 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_CMD_ALLOC_VALID_BMSK 0x1 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_CMD_ALLOC_VALID_SHFT 0x0 + +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x00000014) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000014) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000014) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_STATUS_RMSK 0x3f3ff +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_STATUS_ATTR 0x1 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_STATUS_IN \ + in_dword_masked(HWIO_IPA_RSRC_MNGR_SW_ACCESS_STATUS_ADDR, HWIO_IPA_RSRC_MNGR_SW_ACCESS_STATUS_RMSK) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_STATUS_INM(m) \ + in_dword_masked(HWIO_IPA_RSRC_MNGR_SW_ACCESS_STATUS_ADDR, m) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_STATUS_SRCH_RSRC_ID_NEXT_BMSK 0x3f000 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_STATUS_SRCH_RSRC_ID_NEXT_SHFT 0xc +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_STATUS_ALLOC_RSRC_ID_NEXT_BMSK 0x3f0 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_STATUS_ALLOC_RSRC_ID_NEXT_SHFT 0x4 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_STATUS_RSRV_READY_BMSK 0x8 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_STATUS_RSRV_READY_SHFT 0x3 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_STATUS_REL_READY_BMSK 0x4 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_STATUS_REL_READY_SHFT 0x2 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_STATUS_SRCH_READY_BMSK 0x2 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_STATUS_SRCH_READY_SHFT 0x1 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_STATUS_ALLOC_READY_BMSK 0x1 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_STATUS_ALLOC_READY_SHFT 0x0 + +#define HWIO_IPA_RSRC_MNGR_DB_CFG_ADDR (IPA_DEBUG_REG_BASE + 0x00000018) +#define HWIO_IPA_RSRC_MNGR_DB_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000018) +#define HWIO_IPA_RSRC_MNGR_DB_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000018) +#define HWIO_IPA_RSRC_MNGR_DB_CFG_RMSK 0x3f77 +#define HWIO_IPA_RSRC_MNGR_DB_CFG_ATTR 0x3 +#define HWIO_IPA_RSRC_MNGR_DB_CFG_IN \ + in_dword_masked(HWIO_IPA_RSRC_MNGR_DB_CFG_ADDR, HWIO_IPA_RSRC_MNGR_DB_CFG_RMSK, HWIO_IPA_RSRC_MNGR_DB_CFG_ATTR) +#define HWIO_IPA_RSRC_MNGR_DB_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_RSRC_MNGR_DB_CFG_ADDR, m, HWIO_IPA_RSRC_MNGR_DB_CFG_ATTR) +#define HWIO_IPA_RSRC_MNGR_DB_CFG_OUT(v) \ + out_dword(HWIO_IPA_RSRC_MNGR_DB_CFG_ADDR,v, HWIO_IPA_RSRC_MNGR_DB_CFG_ATTR) +#define HWIO_IPA_RSRC_MNGR_DB_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_RSRC_MNGR_DB_CFG_ADDR,m,v,HWIO_IPA_RSRC_MNGR_DB_CFG_IN) +#define HWIO_IPA_RSRC_MNGR_DB_CFG_RSRC_ID_SEL_BMSK 0x3f00 +#define HWIO_IPA_RSRC_MNGR_DB_CFG_RSRC_ID_SEL_SHFT 0x8 +#define HWIO_IPA_RSRC_MNGR_DB_CFG_RSRC_TYPE_SEL_BMSK 0x70 +#define HWIO_IPA_RSRC_MNGR_DB_CFG_RSRC_TYPE_SEL_SHFT 0x4 +#define HWIO_IPA_RSRC_MNGR_DB_CFG_RSRC_GRP_SEL_BMSK 0x7 +#define HWIO_IPA_RSRC_MNGR_DB_CFG_RSRC_GRP_SEL_SHFT 0x0 + +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_ADDR (IPA_DEBUG_REG_BASE + 0x0000001c) +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000001c) +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000001c) +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_RMSK 0x3f3 +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_ATTR 0x1 +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_IN \ + in_dword_masked(HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_ADDR, HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_RMSK, HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_ATTR) +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_INM(m) \ + in_dword_masked(HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_ADDR, m, HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_ATTR) +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_RSRC_NEXT_INDEX_BMSK 0x3f0 +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_RSRC_NEXT_INDEX_SHFT 0x4 +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_RSRC_NEXT_VALID_BMSK 0x2 +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_RSRC_NEXT_VALID_SHFT 0x1 +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_RSRC_OCCUPIED_BMSK 0x1 +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_RSRC_OCCUPIED_SHFT 0x0 + +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_ADDR (IPA_DEBUG_REG_BASE + 0x00000020) +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000020) +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000020) +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_RMSK 0x7f7f3f3 +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_ATTR 0x1 +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_IN \ + in_dword_masked(HWIO_IPA_RSRC_MNGR_DB_LIST_READ_ADDR, HWIO_IPA_RSRC_MNGR_DB_LIST_READ_RMSK, HWIO_IPA_RSRC_MNGR_DB_LIST_READ_ATTR) +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_INM(m) \ + in_dword_masked(HWIO_IPA_RSRC_MNGR_DB_LIST_READ_ADDR, m, HWIO_IPA_RSRC_MNGR_DB_LIST_READ_ATTR) +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_RSRC_LIST_ENTRY_CNT_BMSK 0x7f00000 +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_RSRC_LIST_ENTRY_CNT_SHFT 0x14 +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_RSRC_LIST_HEAD_CNT_BMSK 0x7f000 +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_RSRC_LIST_HEAD_CNT_SHFT 0xc +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_RSRC_LIST_HEAD_RSRC_BMSK 0x3f0 +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_RSRC_LIST_HEAD_RSRC_SHFT 0x4 +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_RSRC_LIST_HOLD_BMSK 0x2 +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_RSRC_LIST_HOLD_SHFT 0x1 +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_RSRC_LIST_VALID_BMSK 0x1 +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_RSRC_LIST_VALID_SHFT 0x0 + +#define HWIO_IPA_RSRC_MNGR_CONTEXTS_ADDR (IPA_DEBUG_REG_BASE + 0x00000024) +#define HWIO_IPA_RSRC_MNGR_CONTEXTS_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000024) +#define HWIO_IPA_RSRC_MNGR_CONTEXTS_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000024) +#define HWIO_IPA_RSRC_MNGR_CONTEXTS_RMSK 0xffff +#define HWIO_IPA_RSRC_MNGR_CONTEXTS_ATTR 0x1 +#define HWIO_IPA_RSRC_MNGR_CONTEXTS_IN \ + in_dword_masked(HWIO_IPA_RSRC_MNGR_CONTEXTS_ADDR, HWIO_IPA_RSRC_MNGR_CONTEXTS_RMSK) +#define HWIO_IPA_RSRC_MNGR_CONTEXTS_INM(m) \ + in_dword_masked(HWIO_IPA_RSRC_MNGR_CONTEXTS_ADDR, m) +#define HWIO_IPA_RSRC_MNGR_CONTEXTS_RSRC_OCCUPIED_CONTEXTS_BITMAP_BMSK 0xffff +#define HWIO_IPA_RSRC_MNGR_CONTEXTS_RSRC_OCCUPIED_CONTEXTS_BITMAP_SHFT 0x0 + +#define HWIO_IPA_BRESP_DB_CFG_ADDR (IPA_DEBUG_REG_BASE + 0x00000028) +#define HWIO_IPA_BRESP_DB_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000028) +#define HWIO_IPA_BRESP_DB_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000028) +#define HWIO_IPA_BRESP_DB_CFG_RMSK 0x7ff +#define HWIO_IPA_BRESP_DB_CFG_ATTR 0x3 +#define HWIO_IPA_BRESP_DB_CFG_IN \ + in_dword_masked(HWIO_IPA_BRESP_DB_CFG_ADDR, HWIO_IPA_BRESP_DB_CFG_RMSK) +#define HWIO_IPA_BRESP_DB_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_BRESP_DB_CFG_ADDR, m) +#define HWIO_IPA_BRESP_DB_CFG_OUT(v) \ + out_dword(HWIO_IPA_BRESP_DB_CFG_ADDR,v) +#define HWIO_IPA_BRESP_DB_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_BRESP_DB_CFG_ADDR,m,v,HWIO_IPA_BRESP_DB_CFG_IN) +#define HWIO_IPA_BRESP_DB_CFG_SEL_PIPE_BMSK 0x7f8 +#define HWIO_IPA_BRESP_DB_CFG_SEL_PIPE_SHFT 0x3 +#define HWIO_IPA_BRESP_DB_CFG_SEL_ENTRY_BMSK 0x7 +#define HWIO_IPA_BRESP_DB_CFG_SEL_ENTRY_SHFT 0x0 + +#define HWIO_IPA_BRESP_DB_DATA_ADDR (IPA_DEBUG_REG_BASE + 0x0000002c) +#define HWIO_IPA_BRESP_DB_DATA_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000002c) +#define HWIO_IPA_BRESP_DB_DATA_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000002c) +#define HWIO_IPA_BRESP_DB_DATA_RMSK 0xffffffff +#define HWIO_IPA_BRESP_DB_DATA_ATTR 0x1 +#define HWIO_IPA_BRESP_DB_DATA_IN \ + in_dword_masked(HWIO_IPA_BRESP_DB_DATA_ADDR, HWIO_IPA_BRESP_DB_DATA_RMSK) +#define HWIO_IPA_BRESP_DB_DATA_INM(m) \ + in_dword_masked(HWIO_IPA_BRESP_DB_DATA_ADDR, m) +#define HWIO_IPA_BRESP_DB_DATA_DATA_BMSK 0xffffffff +#define HWIO_IPA_BRESP_DB_DATA_DATA_SHFT 0x0 + +#define HWIO_IPA_SNOC_MONITORING_CFG_ADDR (IPA_DEBUG_REG_BASE + 0x00000030) +#define HWIO_IPA_SNOC_MONITORING_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000030) +#define HWIO_IPA_SNOC_MONITORING_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000030) +#define HWIO_IPA_SNOC_MONITORING_CFG_RMSK 0x1 +#define HWIO_IPA_SNOC_MONITORING_CFG_ATTR 0x3 +#define HWIO_IPA_SNOC_MONITORING_CFG_IN \ + in_dword_masked(HWIO_IPA_SNOC_MONITORING_CFG_ADDR, HWIO_IPA_SNOC_MONITORING_CFG_RMSK) +#define HWIO_IPA_SNOC_MONITORING_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_SNOC_MONITORING_CFG_ADDR, m) +#define HWIO_IPA_SNOC_MONITORING_CFG_OUT(v) \ + out_dword(HWIO_IPA_SNOC_MONITORING_CFG_ADDR,v) +#define HWIO_IPA_SNOC_MONITORING_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_SNOC_MONITORING_CFG_ADDR,m,v,HWIO_IPA_SNOC_MONITORING_CFG_IN) +#define HWIO_IPA_SNOC_MONITORING_CFG_ENABLE_BMSK 0x1 +#define HWIO_IPA_SNOC_MONITORING_CFG_ENABLE_SHFT 0x0 + +#define HWIO_IPA_PCIE_SNOC_MONITOR_CNT_ADDR (IPA_DEBUG_REG_BASE + 0x00000034) +#define HWIO_IPA_PCIE_SNOC_MONITOR_CNT_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000034) +#define HWIO_IPA_PCIE_SNOC_MONITOR_CNT_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000034) +#define HWIO_IPA_PCIE_SNOC_MONITOR_CNT_RMSK 0x1f7df7df +#define HWIO_IPA_PCIE_SNOC_MONITOR_CNT_ATTR 0x1 +#define HWIO_IPA_PCIE_SNOC_MONITOR_CNT_IN \ + in_dword_masked(HWIO_IPA_PCIE_SNOC_MONITOR_CNT_ADDR, HWIO_IPA_PCIE_SNOC_MONITOR_CNT_RMSK) +#define HWIO_IPA_PCIE_SNOC_MONITOR_CNT_INM(m) \ + in_dword_masked(HWIO_IPA_PCIE_SNOC_MONITOR_CNT_ADDR, m) +#define HWIO_IPA_PCIE_SNOC_MONITOR_CNT_B_VALUE_BMSK 0x1f000000 +#define HWIO_IPA_PCIE_SNOC_MONITOR_CNT_B_VALUE_SHFT 0x18 +#define HWIO_IPA_PCIE_SNOC_MONITOR_CNT_W_VALUE_BMSK 0x7c0000 +#define HWIO_IPA_PCIE_SNOC_MONITOR_CNT_W_VALUE_SHFT 0x12 +#define HWIO_IPA_PCIE_SNOC_MONITOR_CNT_R_VALUE_BMSK 0x1f000 +#define HWIO_IPA_PCIE_SNOC_MONITOR_CNT_R_VALUE_SHFT 0xc +#define HWIO_IPA_PCIE_SNOC_MONITOR_CNT_AW_VALUE_BMSK 0x7c0 +#define HWIO_IPA_PCIE_SNOC_MONITOR_CNT_AW_VALUE_SHFT 0x6 +#define HWIO_IPA_PCIE_SNOC_MONITOR_CNT_AR_VALUE_BMSK 0x1f +#define HWIO_IPA_PCIE_SNOC_MONITOR_CNT_AR_VALUE_SHFT 0x0 + +#define HWIO_IPA_DDR_SNOC_MONITOR_CNT_ADDR (IPA_DEBUG_REG_BASE + 0x00000038) +#define HWIO_IPA_DDR_SNOC_MONITOR_CNT_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000038) +#define HWIO_IPA_DDR_SNOC_MONITOR_CNT_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000038) +#define HWIO_IPA_DDR_SNOC_MONITOR_CNT_RMSK 0x1f7df7df +#define HWIO_IPA_DDR_SNOC_MONITOR_CNT_ATTR 0x1 +#define HWIO_IPA_DDR_SNOC_MONITOR_CNT_IN \ + in_dword_masked(HWIO_IPA_DDR_SNOC_MONITOR_CNT_ADDR, HWIO_IPA_DDR_SNOC_MONITOR_CNT_RMSK) +#define HWIO_IPA_DDR_SNOC_MONITOR_CNT_INM(m) \ + in_dword_masked(HWIO_IPA_DDR_SNOC_MONITOR_CNT_ADDR, m) +#define HWIO_IPA_DDR_SNOC_MONITOR_CNT_B_VALUE_BMSK 0x1f000000 +#define HWIO_IPA_DDR_SNOC_MONITOR_CNT_B_VALUE_SHFT 0x18 +#define HWIO_IPA_DDR_SNOC_MONITOR_CNT_W_VALUE_BMSK 0x7c0000 +#define HWIO_IPA_DDR_SNOC_MONITOR_CNT_W_VALUE_SHFT 0x12 +#define HWIO_IPA_DDR_SNOC_MONITOR_CNT_R_VALUE_BMSK 0x1f000 +#define HWIO_IPA_DDR_SNOC_MONITOR_CNT_R_VALUE_SHFT 0xc +#define HWIO_IPA_DDR_SNOC_MONITOR_CNT_AW_VALUE_BMSK 0x7c0 +#define HWIO_IPA_DDR_SNOC_MONITOR_CNT_AW_VALUE_SHFT 0x6 +#define HWIO_IPA_DDR_SNOC_MONITOR_CNT_AR_VALUE_BMSK 0x1f +#define HWIO_IPA_DDR_SNOC_MONITOR_CNT_AR_VALUE_SHFT 0x0 + +#define HWIO_IPA_GSI_SNOC_MONITOR_CNT_ADDR (IPA_DEBUG_REG_BASE + 0x0000003c) +#define HWIO_IPA_GSI_SNOC_MONITOR_CNT_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000003c) +#define HWIO_IPA_GSI_SNOC_MONITOR_CNT_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000003c) +#define HWIO_IPA_GSI_SNOC_MONITOR_CNT_RMSK 0x1f7df7df +#define HWIO_IPA_GSI_SNOC_MONITOR_CNT_ATTR 0x1 +#define HWIO_IPA_GSI_SNOC_MONITOR_CNT_IN \ + in_dword_masked(HWIO_IPA_GSI_SNOC_MONITOR_CNT_ADDR, HWIO_IPA_GSI_SNOC_MONITOR_CNT_RMSK) +#define HWIO_IPA_GSI_SNOC_MONITOR_CNT_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_SNOC_MONITOR_CNT_ADDR, m) +#define HWIO_IPA_GSI_SNOC_MONITOR_CNT_B_VALUE_BMSK 0x1f000000 +#define HWIO_IPA_GSI_SNOC_MONITOR_CNT_B_VALUE_SHFT 0x18 +#define HWIO_IPA_GSI_SNOC_MONITOR_CNT_W_VALUE_BMSK 0x7c0000 +#define HWIO_IPA_GSI_SNOC_MONITOR_CNT_W_VALUE_SHFT 0x12 +#define HWIO_IPA_GSI_SNOC_MONITOR_CNT_R_VALUE_BMSK 0x1f000 +#define HWIO_IPA_GSI_SNOC_MONITOR_CNT_R_VALUE_SHFT 0xc +#define HWIO_IPA_GSI_SNOC_MONITOR_CNT_AW_VALUE_BMSK 0x7c0 +#define HWIO_IPA_GSI_SNOC_MONITOR_CNT_AW_VALUE_SHFT 0x6 +#define HWIO_IPA_GSI_SNOC_MONITOR_CNT_AR_VALUE_BMSK 0x1f +#define HWIO_IPA_GSI_SNOC_MONITOR_CNT_AR_VALUE_SHFT 0x0 + +#define HWIO_IPA_DEBUG_DATA_ADDR (IPA_DEBUG_REG_BASE + 0x00000040) +#define HWIO_IPA_DEBUG_DATA_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000040) +#define HWIO_IPA_DEBUG_DATA_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000040) +#define HWIO_IPA_DEBUG_DATA_RMSK 0xffffffff +#define HWIO_IPA_DEBUG_DATA_ATTR 0x1 +#define HWIO_IPA_DEBUG_DATA_IN \ + in_dword_masked(HWIO_IPA_DEBUG_DATA_ADDR, HWIO_IPA_DEBUG_DATA_RMSK, HWIO_IPA_DEBUG_DATA_ATTR) +#define HWIO_IPA_DEBUG_DATA_INM(m) \ + in_dword_masked(HWIO_IPA_DEBUG_DATA_ADDR, m, HWIO_IPA_DEBUG_DATA_ATTR) +#define HWIO_IPA_DEBUG_DATA_DEBUG_DATA_BMSK 0xffffffff +#define HWIO_IPA_DEBUG_DATA_DEBUG_DATA_SHFT 0x0 + +#define HWIO_IPA_TESTBUS_SEL_ADDR (IPA_DEBUG_REG_BASE + 0x0000004c) +#define HWIO_IPA_TESTBUS_SEL_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000004c) +#define HWIO_IPA_TESTBUS_SEL_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000004c) +#define HWIO_IPA_TESTBUS_SEL_RMSK 0xffff1 +#define HWIO_IPA_TESTBUS_SEL_ATTR 0x3 +#define HWIO_IPA_TESTBUS_SEL_IN \ + in_dword_masked(HWIO_IPA_TESTBUS_SEL_ADDR, HWIO_IPA_TESTBUS_SEL_RMSK, HWIO_IPA_TESTBUS_SEL_ATTR) +#define HWIO_IPA_TESTBUS_SEL_INM(m) \ + in_dword_masked(HWIO_IPA_TESTBUS_SEL_ADDR, m, HWIO_IPA_TESTBUS_SEL_ATTR) +#define HWIO_IPA_TESTBUS_SEL_OUT(v) \ + out_dword(HWIO_IPA_TESTBUS_SEL_ADDR,v, HWIO_IPA_TESTBUS_SEL_ATTR) +#define HWIO_IPA_TESTBUS_SEL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_TESTBUS_SEL_ADDR,m,v,HWIO_IPA_TESTBUS_SEL_IN) +#define HWIO_IPA_TESTBUS_SEL_INTERNAL_BLOCK_SELECT_BMSK 0xff000 +#define HWIO_IPA_TESTBUS_SEL_INTERNAL_BLOCK_SELECT_SHFT 0xc +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_BMSK 0xff0 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_SHFT 0x4 +#define HWIO_IPA_TESTBUS_SEL_TESTBUS_EN_BMSK 0x1 +#define HWIO_IPA_TESTBUS_SEL_TESTBUS_EN_SHFT 0x0 + +#define HWIO_IPA_STEP_MODE_BREAKPOINTS_ADDR (IPA_DEBUG_REG_BASE + 0x00000050) +#define HWIO_IPA_STEP_MODE_BREAKPOINTS_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000050) +#define HWIO_IPA_STEP_MODE_BREAKPOINTS_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000050) +#define HWIO_IPA_STEP_MODE_BREAKPOINTS_RMSK 0xffffffff +#define HWIO_IPA_STEP_MODE_BREAKPOINTS_ATTR 0x3 +#define HWIO_IPA_STEP_MODE_BREAKPOINTS_IN \ + in_dword_masked(HWIO_IPA_STEP_MODE_BREAKPOINTS_ADDR, HWIO_IPA_STEP_MODE_BREAKPOINTS_RMSK) +#define HWIO_IPA_STEP_MODE_BREAKPOINTS_INM(m) \ + in_dword_masked(HWIO_IPA_STEP_MODE_BREAKPOINTS_ADDR, m) +#define HWIO_IPA_STEP_MODE_BREAKPOINTS_OUT(v) \ + out_dword(HWIO_IPA_STEP_MODE_BREAKPOINTS_ADDR,v) +#define HWIO_IPA_STEP_MODE_BREAKPOINTS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_STEP_MODE_BREAKPOINTS_ADDR,m,v,HWIO_IPA_STEP_MODE_BREAKPOINTS_IN) +#define HWIO_IPA_STEP_MODE_BREAKPOINTS_HW_EN_BMSK 0xffffffff +#define HWIO_IPA_STEP_MODE_BREAKPOINTS_HW_EN_SHFT 0x0 + +#define HWIO_IPA_STEP_MODE_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x00000054) +#define HWIO_IPA_STEP_MODE_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000054) +#define HWIO_IPA_STEP_MODE_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000054) +#define HWIO_IPA_STEP_MODE_STATUS_RMSK 0xffffffff +#define HWIO_IPA_STEP_MODE_STATUS_ATTR 0x1 +#define HWIO_IPA_STEP_MODE_STATUS_IN \ + in_dword_masked(HWIO_IPA_STEP_MODE_STATUS_ADDR, HWIO_IPA_STEP_MODE_STATUS_RMSK) +#define HWIO_IPA_STEP_MODE_STATUS_INM(m) \ + in_dword_masked(HWIO_IPA_STEP_MODE_STATUS_ADDR, m) +#define HWIO_IPA_STEP_MODE_STATUS_HW_EN_BMSK 0xffffffff +#define HWIO_IPA_STEP_MODE_STATUS_HW_EN_SHFT 0x0 + +#define HWIO_IPA_STEP_MODE_GO_ADDR (IPA_DEBUG_REG_BASE + 0x00000058) +#define HWIO_IPA_STEP_MODE_GO_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000058) +#define HWIO_IPA_STEP_MODE_GO_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000058) +#define HWIO_IPA_STEP_MODE_GO_RMSK 0xffffffff +#define HWIO_IPA_STEP_MODE_GO_ATTR 0x2 +#define HWIO_IPA_STEP_MODE_GO_OUT(v) \ + out_dword(HWIO_IPA_STEP_MODE_GO_ADDR,v) +#define HWIO_IPA_STEP_MODE_GO_HW_EN_BMSK 0xffffffff +#define HWIO_IPA_STEP_MODE_GO_HW_EN_SHFT 0x0 + +#define HWIO_IPA_HW_EVENTS_CFG_ADDR (IPA_DEBUG_REG_BASE + 0x0000005c) +#define HWIO_IPA_HW_EVENTS_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000005c) +#define HWIO_IPA_HW_EVENTS_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000005c) +#define HWIO_IPA_HW_EVENTS_CFG_RMSK 0xfff +#define HWIO_IPA_HW_EVENTS_CFG_ATTR 0x3 +#define HWIO_IPA_HW_EVENTS_CFG_IN \ + in_dword_masked(HWIO_IPA_HW_EVENTS_CFG_ADDR, HWIO_IPA_HW_EVENTS_CFG_RMSK) +#define HWIO_IPA_HW_EVENTS_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_HW_EVENTS_CFG_ADDR, m) +#define HWIO_IPA_HW_EVENTS_CFG_OUT(v) \ + out_dword(HWIO_IPA_HW_EVENTS_CFG_ADDR,v) +#define HWIO_IPA_HW_EVENTS_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_HW_EVENTS_CFG_ADDR,m,v,HWIO_IPA_HW_EVENTS_CFG_IN) +#define HWIO_IPA_HW_EVENTS_CFG_RX_EVENTS_PIPE_SELECT_BMSK 0xff0 +#define HWIO_IPA_HW_EVENTS_CFG_RX_EVENTS_PIPE_SELECT_SHFT 0x4 +#define HWIO_IPA_HW_EVENTS_CFG_HW_EVENTS_SELECT_BMSK 0xf +#define HWIO_IPA_HW_EVENTS_CFG_HW_EVENTS_SELECT_SHFT 0x0 + +#define HWIO_IPA_LOG_ADDR (IPA_DEBUG_REG_BASE + 0x00000060) +#define HWIO_IPA_LOG_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000060) +#define HWIO_IPA_LOG_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000060) +#define HWIO_IPA_LOG_RMSK 0x3ffff2 +#define HWIO_IPA_LOG_ATTR 0x3 +#define HWIO_IPA_LOG_IN \ + in_dword_masked(HWIO_IPA_LOG_ADDR, HWIO_IPA_LOG_RMSK) +#define HWIO_IPA_LOG_INM(m) \ + in_dword_masked(HWIO_IPA_LOG_ADDR, m) +#define HWIO_IPA_LOG_OUT(v) \ + out_dword(HWIO_IPA_LOG_ADDR,v) +#define HWIO_IPA_LOG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_LOG_ADDR,m,v,HWIO_IPA_LOG_IN) +#define HWIO_IPA_LOG_LOG_DPL_L2_REMOVE_EN_BMSK 0x200000 +#define HWIO_IPA_LOG_LOG_DPL_L2_REMOVE_EN_SHFT 0x15 +#define HWIO_IPA_LOG_LOG_REDUCTION_EN_BMSK 0x100000 +#define HWIO_IPA_LOG_LOG_REDUCTION_EN_SHFT 0x14 +#define HWIO_IPA_LOG_LOG_LENGTH_BMSK 0xff000 +#define HWIO_IPA_LOG_LOG_LENGTH_SHFT 0xc +#define HWIO_IPA_LOG_LOG_PIPE_BMSK 0xff0 +#define HWIO_IPA_LOG_LOG_PIPE_SHFT 0x4 +#define HWIO_IPA_LOG_LOG_EN_BMSK 0x2 +#define HWIO_IPA_LOG_LOG_EN_SHFT 0x1 + +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_ADDR (IPA_DEBUG_REG_BASE + 0x00000064) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000064) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000064) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_IN \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_CMD_ADDR_ADDR, HWIO_IPA_LOG_BUF_HW_CMD_ADDR_RMSK) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_CMD_ADDR_ADDR, m) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_OUT(v) \ + out_dword(HWIO_IPA_LOG_BUF_HW_CMD_ADDR_ADDR,v) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_LOG_BUF_HW_CMD_ADDR_ADDR,m,v,HWIO_IPA_LOG_BUF_HW_CMD_ADDR_IN) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_START_ADDR_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_START_ADDR_SHFT 0x0 + +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_ADDR (IPA_DEBUG_REG_BASE + 0x00000068) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000068) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000068) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_IN \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_ADDR, HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_RMSK) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_INM(m) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_ADDR, m) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_OUT(v) \ + out_dword(HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_ADDR,v) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_ADDR,m,v,HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_IN) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_START_ADDR_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_START_ADDR_SHFT 0x0 + +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_ADDR (IPA_DEBUG_REG_BASE + 0x0000006c) +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000006c) +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000006c) +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_ATTR 0x1 +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_IN \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_ADDR, HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_RMSK) +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_INM(m) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_ADDR, m) +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_WRITR_ADDR_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_WRITR_ADDR_SHFT 0x0 + +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_MSB_ADDR (IPA_DEBUG_REG_BASE + 0x00000070) +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_MSB_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000070) +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_MSB_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000070) +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_MSB_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_MSB_ATTR 0x1 +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_MSB_IN \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_MSB_ADDR, HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_MSB_RMSK) +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_MSB_INM(m) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_MSB_ADDR, m) +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_MSB_WRITR_ADDR_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_MSB_WRITR_ADDR_SHFT 0x0 + +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_ADDR (IPA_DEBUG_REG_BASE + 0x00000074) +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000074) +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000074) +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_RMSK 0x7ffff +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_IN \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_CMD_CFG_ADDR, HWIO_IPA_LOG_BUF_HW_CMD_CFG_RMSK) +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_CMD_CFG_ADDR, m) +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_OUT(v) \ + out_dword(HWIO_IPA_LOG_BUF_HW_CMD_CFG_ADDR,v) +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_LOG_BUF_HW_CMD_CFG_ADDR,m,v,HWIO_IPA_LOG_BUF_HW_CMD_CFG_IN) +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_TPDM_ENABLE_BMSK 0x40000 +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_TPDM_ENABLE_SHFT 0x12 +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_SKIP_DDR_DMA_BMSK 0x20000 +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_SKIP_DDR_DMA_SHFT 0x11 +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_ENABLE_BMSK 0x10000 +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_ENABLE_SHFT 0x10 +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_SIZE_BMSK 0xffff +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_SIZE_SHFT 0x0 + +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_ADDR (IPA_DEBUG_REG_BASE + 0x00000078) +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000078) +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000078) +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_RMSK 0xffff3fff +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_ATTR 0x1 +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_IN \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_ADDR, HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_RMSK) +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_INM(m) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_ADDR, m) +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_SKIP_DDR_WRAP_HAPPENED_BMSK 0x80000000 +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_SKIP_DDR_WRAP_HAPPENED_SHFT 0x1f +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_FULL_BMSK 0x40000000 +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_FULL_SHFT 0x1e +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_WRITE_PTR_BMSK 0x3fff0000 +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_WRITE_PTR_SHFT 0x10 +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_READ_PTR_BMSK 0x3fff +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_READ_PTR_SHFT 0x0 + +#define HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_ADDR (IPA_DEBUG_REG_BASE + 0x00000080) +#define HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000080) +#define HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000080) +#define HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_RMSK 0x3ff +#define HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_IN \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_ADDR, HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_RMSK) +#define HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_INM(m) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_ADDR, m) +#define HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_OUT(v) \ + out_dword(HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_ADDR,v) +#define HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_ADDR,m,v,HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_IN) +#define HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_UC_RESP_EN_BMSK 0x200 +#define HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_UC_RESP_EN_SHFT 0x9 +#define HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_GSI_RESP_EN_BMSK 0x100 +#define HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_GSI_RESP_EN_SHFT 0x8 +#define HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_QMB_RESP_EN_BMSK 0x80 +#define HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_QMB_RESP_EN_SHFT 0x7 +#define HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_UC_WR_EN_BMSK 0x40 +#define HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_UC_WR_EN_SHFT 0x6 +#define HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_UC_RD_EN_BMSK 0x20 +#define HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_UC_RD_EN_SHFT 0x5 +#define HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_GSI_WR_EN_BMSK 0x10 +#define HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_GSI_WR_EN_SHFT 0x4 +#define HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_GSI_RD_EN_BMSK 0x8 +#define HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_GSI_RD_EN_SHFT 0x3 +#define HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_QMB_WR_EN_BMSK 0x4 +#define HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_QMB_WR_EN_SHFT 0x2 +#define HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_QMB_RD_EN_BMSK 0x2 +#define HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_QMB_RD_EN_SHFT 0x1 +#define HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_NOC_PORT_SEL_BMSK 0x1 +#define HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_NOC_PORT_SEL_SHFT 0x0 + +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_LSB_ADDR (IPA_DEBUG_REG_BASE + 0x00000084) +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_LSB_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000084) +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_LSB_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000084) +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_LSB_RMSK 0xffffffff +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_LSB_ATTR 0x3 +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_LSB_IN \ + in_dword_masked(HWIO_IPA_STEP_MODE_HFETCHER_ADDR_LSB_ADDR, HWIO_IPA_STEP_MODE_HFETCHER_ADDR_LSB_RMSK) +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_LSB_INM(m) \ + in_dword_masked(HWIO_IPA_STEP_MODE_HFETCHER_ADDR_LSB_ADDR, m) +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_LSB_OUT(v) \ + out_dword(HWIO_IPA_STEP_MODE_HFETCHER_ADDR_LSB_ADDR,v) +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_STEP_MODE_HFETCHER_ADDR_LSB_ADDR,m,v,HWIO_IPA_STEP_MODE_HFETCHER_ADDR_LSB_IN) +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_LSB_ADDR_LSB_BMSK 0xffffffff +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_LSB_ADDR_LSB_SHFT 0x0 + +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_MSB_ADDR (IPA_DEBUG_REG_BASE + 0x00000088) +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_MSB_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000088) +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_MSB_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000088) +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_MSB_RMSK 0xffffffff +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_MSB_ATTR 0x3 +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_MSB_IN \ + in_dword_masked(HWIO_IPA_STEP_MODE_HFETCHER_ADDR_MSB_ADDR, HWIO_IPA_STEP_MODE_HFETCHER_ADDR_MSB_RMSK) +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_MSB_INM(m) \ + in_dword_masked(HWIO_IPA_STEP_MODE_HFETCHER_ADDR_MSB_ADDR, m) +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_MSB_OUT(v) \ + out_dword(HWIO_IPA_STEP_MODE_HFETCHER_ADDR_MSB_ADDR,v) +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_STEP_MODE_HFETCHER_ADDR_MSB_ADDR,m,v,HWIO_IPA_STEP_MODE_HFETCHER_ADDR_MSB_IN) +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_MSB_ADDR_MSB_BMSK 0xffffffff +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_MSB_ADDR_MSB_SHFT 0x0 + +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_RESULT_ADDR (IPA_DEBUG_REG_BASE + 0x0000008c) +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_RESULT_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000008c) +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_RESULT_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000008c) +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_RESULT_RMSK 0x7fffff +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_RESULT_ATTR 0x1 +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_RESULT_IN \ + in_dword_masked(HWIO_IPA_STEP_MODE_HFETCHER_ADDR_RESULT_ADDR, HWIO_IPA_STEP_MODE_HFETCHER_ADDR_RESULT_RMSK) +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_RESULT_INM(m) \ + in_dword_masked(HWIO_IPA_STEP_MODE_HFETCHER_ADDR_RESULT_ADDR, m) +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_RESULT_TYPE_F_BMSK 0x400000 +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_RESULT_TYPE_F_SHFT 0x16 +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_RESULT_OPCODE_F_BMSK 0x300000 +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_RESULT_OPCODE_F_SHFT 0x14 +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_RESULT_SRC_PIPE_F_BMSK 0xff000 +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_RESULT_SRC_PIPE_F_SHFT 0xc +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_RESULT_SRC_ID_F_BMSK 0xff0 +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_RESULT_SRC_ID_F_SHFT 0x4 +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_RESULT_CTX_ID_F_BMSK 0xf +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_RESULT_CTX_ID_F_SHFT 0x0 + +#define HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_ADDR (IPA_DEBUG_REG_BASE + 0x00000090) +#define HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000090) +#define HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000090) +#define HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_RMSK 0x1fffffff +#define HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_ATTR 0x3 +#define HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_IN \ + in_dword_masked(HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_ADDR, HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_RMSK) +#define HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_INM(m) \ + in_dword_masked(HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_ADDR, m) +#define HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_OUT(v) \ + out_dword(HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_ADDR,v) +#define HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_ADDR,m,v,HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_IN) +#define HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_ACL_ID_F_BMSK 0x1f800000 +#define HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_ACL_ID_F_SHFT 0x17 +#define HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_TYPE_F_BMSK 0x400000 +#define HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_TYPE_F_SHFT 0x16 +#define HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_OPCODE_F_BMSK 0x300000 +#define HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_OPCODE_F_SHFT 0x14 +#define HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_SRC_PIPE_F_BMSK 0xff000 +#define HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_SRC_PIPE_F_SHFT 0xc +#define HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_SRC_ID_F_BMSK 0xff0 +#define HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_SRC_ID_F_SHFT 0x4 +#define HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_CTX_ID_F_BMSK 0xf +#define HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_CTX_ID_F_SHFT 0x0 + +#define HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_1_ADDR (IPA_DEBUG_REG_BASE + 0x00000094) +#define HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_1_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000094) +#define HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_1_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000094) +#define HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_1_RMSK 0x3f +#define HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_1_ATTR 0x3 +#define HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_1_IN \ + in_dword_masked(HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_1_ADDR, HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_1_RMSK) +#define HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_1_INM(m) \ + in_dword_masked(HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_1_ADDR, m) +#define HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_1_OUT(v) \ + out_dword(HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_1_ADDR,v) +#define HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_1_ADDR,m,v,HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_1_IN) +#define HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_1_ACL_ID_V_BMSK 0x20 +#define HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_1_ACL_ID_V_SHFT 0x5 +#define HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_1_TYPE_V_BMSK 0x10 +#define HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_1_TYPE_V_SHFT 0x4 +#define HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_1_OPCODE_V_BMSK 0x8 +#define HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_1_OPCODE_V_SHFT 0x3 +#define HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_1_SRC_PIPE_V_BMSK 0x4 +#define HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_1_SRC_PIPE_V_SHFT 0x2 +#define HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_1_SRC_ID_V_BMSK 0x2 +#define HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_1_SRC_ID_V_SHFT 0x1 +#define HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_1_CTX_ID_V_BMSK 0x1 +#define HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_1_CTX_ID_V_SHFT 0x0 + +#define HWIO_IPA_STEP_MODE_HSEQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x00000098) +#define HWIO_IPA_STEP_MODE_HSEQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000098) +#define HWIO_IPA_STEP_MODE_HSEQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000098) +#define HWIO_IPA_STEP_MODE_HSEQ_STATUS_RMSK 0x1fffffff +#define HWIO_IPA_STEP_MODE_HSEQ_STATUS_ATTR 0x1 +#define HWIO_IPA_STEP_MODE_HSEQ_STATUS_IN \ + in_dword_masked(HWIO_IPA_STEP_MODE_HSEQ_STATUS_ADDR, HWIO_IPA_STEP_MODE_HSEQ_STATUS_RMSK) +#define HWIO_IPA_STEP_MODE_HSEQ_STATUS_INM(m) \ + in_dword_masked(HWIO_IPA_STEP_MODE_HSEQ_STATUS_ADDR, m) +#define HWIO_IPA_STEP_MODE_HSEQ_STATUS_ACL_ID_F_BMSK 0x1f800000 +#define HWIO_IPA_STEP_MODE_HSEQ_STATUS_ACL_ID_F_SHFT 0x17 +#define HWIO_IPA_STEP_MODE_HSEQ_STATUS_TYPE_F_BMSK 0x400000 +#define HWIO_IPA_STEP_MODE_HSEQ_STATUS_TYPE_F_SHFT 0x16 +#define HWIO_IPA_STEP_MODE_HSEQ_STATUS_OPCODE_F_BMSK 0x300000 +#define HWIO_IPA_STEP_MODE_HSEQ_STATUS_OPCODE_F_SHFT 0x14 +#define HWIO_IPA_STEP_MODE_HSEQ_STATUS_SRC_PIPE_F_BMSK 0xff000 +#define HWIO_IPA_STEP_MODE_HSEQ_STATUS_SRC_PIPE_F_SHFT 0xc +#define HWIO_IPA_STEP_MODE_HSEQ_STATUS_SRC_ID_F_BMSK 0xff0 +#define HWIO_IPA_STEP_MODE_HSEQ_STATUS_SRC_ID_F_SHFT 0x4 +#define HWIO_IPA_STEP_MODE_HSEQ_STATUS_CTX_ID_F_BMSK 0xf +#define HWIO_IPA_STEP_MODE_HSEQ_STATUS_CTX_ID_F_SHFT 0x0 + +#define HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_ADDR (IPA_DEBUG_REG_BASE + 0x0000009c) +#define HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000009c) +#define HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000009c) +#define HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_RMSK 0x1fffffff +#define HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_ATTR 0x3 +#define HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_IN \ + in_dword_masked(HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_ADDR, HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_RMSK) +#define HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_INM(m) \ + in_dword_masked(HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_ADDR, m) +#define HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_OUT(v) \ + out_dword(HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_ADDR,v) +#define HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_ADDR,m,v,HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_IN) +#define HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_ACL_ID_F_BMSK 0x1f800000 +#define HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_ACL_ID_F_SHFT 0x17 +#define HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_TYPE_F_BMSK 0x400000 +#define HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_TYPE_F_SHFT 0x16 +#define HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_OPCODE_F_BMSK 0x300000 +#define HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_OPCODE_F_SHFT 0x14 +#define HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_SRC_PIPE_F_BMSK 0xff000 +#define HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_SRC_PIPE_F_SHFT 0xc +#define HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_SRC_ID_F_BMSK 0xff0 +#define HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_SRC_ID_F_SHFT 0x4 +#define HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_CTX_ID_F_BMSK 0xf +#define HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_CTX_ID_F_SHFT 0x0 + +#define HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_1_ADDR (IPA_DEBUG_REG_BASE + 0x00000100) +#define HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_1_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000100) +#define HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_1_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000100) +#define HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_1_RMSK 0x3f +#define HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_1_ATTR 0x3 +#define HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_1_IN \ + in_dword_masked(HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_1_ADDR, HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_1_RMSK) +#define HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_1_INM(m) \ + in_dword_masked(HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_1_ADDR, m) +#define HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_1_OUT(v) \ + out_dword(HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_1_ADDR,v) +#define HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_1_ADDR,m,v,HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_1_IN) +#define HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_1_ACL_ID_V_BMSK 0x20 +#define HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_1_ACL_ID_V_SHFT 0x5 +#define HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_1_TYPE_V_BMSK 0x10 +#define HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_1_TYPE_V_SHFT 0x4 +#define HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_1_OPCODE_V_BMSK 0x8 +#define HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_1_OPCODE_V_SHFT 0x3 +#define HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_1_SRC_PIPE_V_BMSK 0x4 +#define HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_1_SRC_PIPE_V_SHFT 0x2 +#define HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_1_SRC_ID_V_BMSK 0x2 +#define HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_1_SRC_ID_V_SHFT 0x1 +#define HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_1_CTX_ID_V_BMSK 0x1 +#define HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_1_CTX_ID_V_SHFT 0x0 + +#define HWIO_IPA_STEP_MODE_DSEQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x00000104) +#define HWIO_IPA_STEP_MODE_DSEQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000104) +#define HWIO_IPA_STEP_MODE_DSEQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000104) +#define HWIO_IPA_STEP_MODE_DSEQ_STATUS_RMSK 0x1fffffff +#define HWIO_IPA_STEP_MODE_DSEQ_STATUS_ATTR 0x1 +#define HWIO_IPA_STEP_MODE_DSEQ_STATUS_IN \ + in_dword_masked(HWIO_IPA_STEP_MODE_DSEQ_STATUS_ADDR, HWIO_IPA_STEP_MODE_DSEQ_STATUS_RMSK) +#define HWIO_IPA_STEP_MODE_DSEQ_STATUS_INM(m) \ + in_dword_masked(HWIO_IPA_STEP_MODE_DSEQ_STATUS_ADDR, m) +#define HWIO_IPA_STEP_MODE_DSEQ_STATUS_ACL_ID_F_BMSK 0x1f800000 +#define HWIO_IPA_STEP_MODE_DSEQ_STATUS_ACL_ID_F_SHFT 0x17 +#define HWIO_IPA_STEP_MODE_DSEQ_STATUS_TYPE_F_BMSK 0x400000 +#define HWIO_IPA_STEP_MODE_DSEQ_STATUS_TYPE_F_SHFT 0x16 +#define HWIO_IPA_STEP_MODE_DSEQ_STATUS_OPCODE_F_BMSK 0x300000 +#define HWIO_IPA_STEP_MODE_DSEQ_STATUS_OPCODE_F_SHFT 0x14 +#define HWIO_IPA_STEP_MODE_DSEQ_STATUS_SRC_PIPE_F_BMSK 0xff000 +#define HWIO_IPA_STEP_MODE_DSEQ_STATUS_SRC_PIPE_F_SHFT 0xc +#define HWIO_IPA_STEP_MODE_DSEQ_STATUS_SRC_ID_F_BMSK 0xff0 +#define HWIO_IPA_STEP_MODE_DSEQ_STATUS_SRC_ID_F_SHFT 0x4 +#define HWIO_IPA_STEP_MODE_DSEQ_STATUS_CTX_ID_F_BMSK 0xf +#define HWIO_IPA_STEP_MODE_DSEQ_STATUS_CTX_ID_F_SHFT 0x0 + +#define HWIO_IPA_RX_ACKQ_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x00000158) +#define HWIO_IPA_RX_ACKQ_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000158) +#define HWIO_IPA_RX_ACKQ_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000158) +#define HWIO_IPA_RX_ACKQ_CMD_RMSK 0xf +#define HWIO_IPA_RX_ACKQ_CMD_ATTR 0x2 +#define HWIO_IPA_RX_ACKQ_CMD_OUT(v) \ + out_dword(HWIO_IPA_RX_ACKQ_CMD_ADDR,v) +#define HWIO_IPA_RX_ACKQ_CMD_RELEASE_WR_CMD_BMSK 0x8 +#define HWIO_IPA_RX_ACKQ_CMD_RELEASE_WR_CMD_SHFT 0x3 +#define HWIO_IPA_RX_ACKQ_CMD_RELEASE_RD_CMD_BMSK 0x4 +#define HWIO_IPA_RX_ACKQ_CMD_RELEASE_RD_CMD_SHFT 0x2 +#define HWIO_IPA_RX_ACKQ_CMD_POP_CMD_BMSK 0x2 +#define HWIO_IPA_RX_ACKQ_CMD_POP_CMD_SHFT 0x1 +#define HWIO_IPA_RX_ACKQ_CMD_WRITE_CMD_BMSK 0x1 +#define HWIO_IPA_RX_ACKQ_CMD_WRITE_CMD_SHFT 0x0 + +#define HWIO_IPA_RX_ACKQ_CFG_ADDR (IPA_DEBUG_REG_BASE + 0x0000015c) +#define HWIO_IPA_RX_ACKQ_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000015c) +#define HWIO_IPA_RX_ACKQ_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000015c) +#define HWIO_IPA_RX_ACKQ_CFG_RMSK 0x3 +#define HWIO_IPA_RX_ACKQ_CFG_ATTR 0x3 +#define HWIO_IPA_RX_ACKQ_CFG_IN \ + in_dword_masked(HWIO_IPA_RX_ACKQ_CFG_ADDR, HWIO_IPA_RX_ACKQ_CFG_RMSK) +#define HWIO_IPA_RX_ACKQ_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_RX_ACKQ_CFG_ADDR, m) +#define HWIO_IPA_RX_ACKQ_CFG_OUT(v) \ + out_dword(HWIO_IPA_RX_ACKQ_CFG_ADDR,v) +#define HWIO_IPA_RX_ACKQ_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_RX_ACKQ_CFG_ADDR,m,v,HWIO_IPA_RX_ACKQ_CFG_IN) +#define HWIO_IPA_RX_ACKQ_CFG_BLOCK_WR_BMSK 0x2 +#define HWIO_IPA_RX_ACKQ_CFG_BLOCK_WR_SHFT 0x1 +#define HWIO_IPA_RX_ACKQ_CFG_BLOCK_RD_REQ_BMSK 0x1 +#define HWIO_IPA_RX_ACKQ_CFG_BLOCK_RD_REQ_SHFT 0x0 + +#define HWIO_IPA_RX_ACKQ_DATA_WR_0_ADDR (IPA_DEBUG_REG_BASE + 0x00000160) +#define HWIO_IPA_RX_ACKQ_DATA_WR_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000160) +#define HWIO_IPA_RX_ACKQ_DATA_WR_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000160) +#define HWIO_IPA_RX_ACKQ_DATA_WR_0_RMSK 0x1ffffff +#define HWIO_IPA_RX_ACKQ_DATA_WR_0_ATTR 0x3 +#define HWIO_IPA_RX_ACKQ_DATA_WR_0_IN \ + in_dword_masked(HWIO_IPA_RX_ACKQ_DATA_WR_0_ADDR, HWIO_IPA_RX_ACKQ_DATA_WR_0_RMSK) +#define HWIO_IPA_RX_ACKQ_DATA_WR_0_INM(m) \ + in_dword_masked(HWIO_IPA_RX_ACKQ_DATA_WR_0_ADDR, m) +#define HWIO_IPA_RX_ACKQ_DATA_WR_0_OUT(v) \ + out_dword(HWIO_IPA_RX_ACKQ_DATA_WR_0_ADDR,v) +#define HWIO_IPA_RX_ACKQ_DATA_WR_0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_RX_ACKQ_DATA_WR_0_ADDR,m,v,HWIO_IPA_RX_ACKQ_DATA_WR_0_IN) +#define HWIO_IPA_RX_ACKQ_DATA_WR_0_ACK_VALUE1_TYPE_BMSK 0x1000000 +#define HWIO_IPA_RX_ACKQ_DATA_WR_0_ACK_VALUE1_TYPE_SHFT 0x18 +#define HWIO_IPA_RX_ACKQ_DATA_WR_0_ACK_VALUE2_BMSK 0xff0000 +#define HWIO_IPA_RX_ACKQ_DATA_WR_0_ACK_VALUE2_SHFT 0x10 +#define HWIO_IPA_RX_ACKQ_DATA_WR_0_ACK_VALUE1_BMSK 0xffff +#define HWIO_IPA_RX_ACKQ_DATA_WR_0_ACK_VALUE1_SHFT 0x0 + +#define HWIO_IPA_RX_ACKQ_DATA_RD_0_ADDR (IPA_DEBUG_REG_BASE + 0x00000164) +#define HWIO_IPA_RX_ACKQ_DATA_RD_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000164) +#define HWIO_IPA_RX_ACKQ_DATA_RD_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000164) +#define HWIO_IPA_RX_ACKQ_DATA_RD_0_RMSK 0x1ffffff +#define HWIO_IPA_RX_ACKQ_DATA_RD_0_ATTR 0x1 +#define HWIO_IPA_RX_ACKQ_DATA_RD_0_IN \ + in_dword_masked(HWIO_IPA_RX_ACKQ_DATA_RD_0_ADDR, HWIO_IPA_RX_ACKQ_DATA_RD_0_RMSK) +#define HWIO_IPA_RX_ACKQ_DATA_RD_0_INM(m) \ + in_dword_masked(HWIO_IPA_RX_ACKQ_DATA_RD_0_ADDR, m) +#define HWIO_IPA_RX_ACKQ_DATA_RD_0_ACK_VALUE1_TYPE_BMSK 0x1000000 +#define HWIO_IPA_RX_ACKQ_DATA_RD_0_ACK_VALUE1_TYPE_SHFT 0x18 +#define HWIO_IPA_RX_ACKQ_DATA_RD_0_ACK_VALUE2_BMSK 0xff0000 +#define HWIO_IPA_RX_ACKQ_DATA_RD_0_ACK_VALUE2_SHFT 0x10 +#define HWIO_IPA_RX_ACKQ_DATA_RD_0_ACK_VALUE1_BMSK 0xffff +#define HWIO_IPA_RX_ACKQ_DATA_RD_0_ACK_VALUE1_SHFT 0x0 + +#define HWIO_IPA_RX_ACKQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x00000168) +#define HWIO_IPA_RX_ACKQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000168) +#define HWIO_IPA_RX_ACKQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000168) +#define HWIO_IPA_RX_ACKQ_STATUS_RMSK 0x1ff7 +#define HWIO_IPA_RX_ACKQ_STATUS_ATTR 0x1 +#define HWIO_IPA_RX_ACKQ_STATUS_IN \ + in_dword_masked(HWIO_IPA_RX_ACKQ_STATUS_ADDR, HWIO_IPA_RX_ACKQ_STATUS_RMSK) +#define HWIO_IPA_RX_ACKQ_STATUS_INM(m) \ + in_dword_masked(HWIO_IPA_RX_ACKQ_STATUS_ADDR, m) +#define HWIO_IPA_RX_ACKQ_STATUS_BLOCK_RD_ACK_BMSK 0x1000 +#define HWIO_IPA_RX_ACKQ_STATUS_BLOCK_RD_ACK_SHFT 0xc +#define HWIO_IPA_RX_ACKQ_STATUS_ACKQ_DEPTH_BMSK 0xf00 +#define HWIO_IPA_RX_ACKQ_STATUS_ACKQ_DEPTH_SHFT 0x8 +#define HWIO_IPA_RX_ACKQ_STATUS_ACKQ_COUNT_BMSK 0xf0 +#define HWIO_IPA_RX_ACKQ_STATUS_ACKQ_COUNT_SHFT 0x4 +#define HWIO_IPA_RX_ACKQ_STATUS_ACKQ_FULL_BMSK 0x4 +#define HWIO_IPA_RX_ACKQ_STATUS_ACKQ_FULL_SHFT 0x2 +#define HWIO_IPA_RX_ACKQ_STATUS_ACKQ_EMPTY_BMSK 0x2 +#define HWIO_IPA_RX_ACKQ_STATUS_ACKQ_EMPTY_SHFT 0x1 +#define HWIO_IPA_RX_ACKQ_STATUS_STATUS_BMSK 0x1 +#define HWIO_IPA_RX_ACKQ_STATUS_STATUS_SHFT 0x0 + +#define HWIO_IPA_UC_ACKQ_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x0000016c) +#define HWIO_IPA_UC_ACKQ_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000016c) +#define HWIO_IPA_UC_ACKQ_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000016c) +#define HWIO_IPA_UC_ACKQ_CMD_RMSK 0xf +#define HWIO_IPA_UC_ACKQ_CMD_ATTR 0x2 +#define HWIO_IPA_UC_ACKQ_CMD_OUT(v) \ + out_dword(HWIO_IPA_UC_ACKQ_CMD_ADDR,v) +#define HWIO_IPA_UC_ACKQ_CMD_RELEASE_WR_CMD_BMSK 0x8 +#define HWIO_IPA_UC_ACKQ_CMD_RELEASE_WR_CMD_SHFT 0x3 +#define HWIO_IPA_UC_ACKQ_CMD_RELEASE_RD_CMD_BMSK 0x4 +#define HWIO_IPA_UC_ACKQ_CMD_RELEASE_RD_CMD_SHFT 0x2 +#define HWIO_IPA_UC_ACKQ_CMD_POP_CMD_BMSK 0x2 +#define HWIO_IPA_UC_ACKQ_CMD_POP_CMD_SHFT 0x1 +#define HWIO_IPA_UC_ACKQ_CMD_WRITE_CMD_BMSK 0x1 +#define HWIO_IPA_UC_ACKQ_CMD_WRITE_CMD_SHFT 0x0 + +#define HWIO_IPA_UC_ACKQ_CFG_ADDR (IPA_DEBUG_REG_BASE + 0x00000170) +#define HWIO_IPA_UC_ACKQ_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000170) +#define HWIO_IPA_UC_ACKQ_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000170) +#define HWIO_IPA_UC_ACKQ_CFG_RMSK 0x3 +#define HWIO_IPA_UC_ACKQ_CFG_ATTR 0x3 +#define HWIO_IPA_UC_ACKQ_CFG_IN \ + in_dword_masked(HWIO_IPA_UC_ACKQ_CFG_ADDR, HWIO_IPA_UC_ACKQ_CFG_RMSK) +#define HWIO_IPA_UC_ACKQ_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_UC_ACKQ_CFG_ADDR, m) +#define HWIO_IPA_UC_ACKQ_CFG_OUT(v) \ + out_dword(HWIO_IPA_UC_ACKQ_CFG_ADDR,v) +#define HWIO_IPA_UC_ACKQ_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_ACKQ_CFG_ADDR,m,v,HWIO_IPA_UC_ACKQ_CFG_IN) +#define HWIO_IPA_UC_ACKQ_CFG_BLOCK_WR_BMSK 0x2 +#define HWIO_IPA_UC_ACKQ_CFG_BLOCK_WR_SHFT 0x1 +#define HWIO_IPA_UC_ACKQ_CFG_BLOCK_RD_BMSK 0x1 +#define HWIO_IPA_UC_ACKQ_CFG_BLOCK_RD_SHFT 0x0 + +#define HWIO_IPA_UC_ACKQ_DATA_WR_0_ADDR (IPA_DEBUG_REG_BASE + 0x00000174) +#define HWIO_IPA_UC_ACKQ_DATA_WR_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000174) +#define HWIO_IPA_UC_ACKQ_DATA_WR_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000174) +#define HWIO_IPA_UC_ACKQ_DATA_WR_0_RMSK 0x1ffffff +#define HWIO_IPA_UC_ACKQ_DATA_WR_0_ATTR 0x3 +#define HWIO_IPA_UC_ACKQ_DATA_WR_0_IN \ + in_dword_masked(HWIO_IPA_UC_ACKQ_DATA_WR_0_ADDR, HWIO_IPA_UC_ACKQ_DATA_WR_0_RMSK) +#define HWIO_IPA_UC_ACKQ_DATA_WR_0_INM(m) \ + in_dword_masked(HWIO_IPA_UC_ACKQ_DATA_WR_0_ADDR, m) +#define HWIO_IPA_UC_ACKQ_DATA_WR_0_OUT(v) \ + out_dword(HWIO_IPA_UC_ACKQ_DATA_WR_0_ADDR,v) +#define HWIO_IPA_UC_ACKQ_DATA_WR_0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_ACKQ_DATA_WR_0_ADDR,m,v,HWIO_IPA_UC_ACKQ_DATA_WR_0_IN) +#define HWIO_IPA_UC_ACKQ_DATA_WR_0_ACK_VALUE1_TYPE_BMSK 0x1000000 +#define HWIO_IPA_UC_ACKQ_DATA_WR_0_ACK_VALUE1_TYPE_SHFT 0x18 +#define HWIO_IPA_UC_ACKQ_DATA_WR_0_ACK_VALUE2_BMSK 0xff0000 +#define HWIO_IPA_UC_ACKQ_DATA_WR_0_ACK_VALUE2_SHFT 0x10 +#define HWIO_IPA_UC_ACKQ_DATA_WR_0_ACK_VALUE1_BMSK 0xffff +#define HWIO_IPA_UC_ACKQ_DATA_WR_0_ACK_VALUE1_SHFT 0x0 + +#define HWIO_IPA_UC_ACKQ_DATA_RD_0_ADDR (IPA_DEBUG_REG_BASE + 0x00000178) +#define HWIO_IPA_UC_ACKQ_DATA_RD_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000178) +#define HWIO_IPA_UC_ACKQ_DATA_RD_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000178) +#define HWIO_IPA_UC_ACKQ_DATA_RD_0_RMSK 0x1ffffff +#define HWIO_IPA_UC_ACKQ_DATA_RD_0_ATTR 0x1 +#define HWIO_IPA_UC_ACKQ_DATA_RD_0_IN \ + in_dword_masked(HWIO_IPA_UC_ACKQ_DATA_RD_0_ADDR, HWIO_IPA_UC_ACKQ_DATA_RD_0_RMSK) +#define HWIO_IPA_UC_ACKQ_DATA_RD_0_INM(m) \ + in_dword_masked(HWIO_IPA_UC_ACKQ_DATA_RD_0_ADDR, m) +#define HWIO_IPA_UC_ACKQ_DATA_RD_0_ACK_VALUE1_TYPE_BMSK 0x1000000 +#define HWIO_IPA_UC_ACKQ_DATA_RD_0_ACK_VALUE1_TYPE_SHFT 0x18 +#define HWIO_IPA_UC_ACKQ_DATA_RD_0_ACK_VALUE2_BMSK 0xff0000 +#define HWIO_IPA_UC_ACKQ_DATA_RD_0_ACK_VALUE2_SHFT 0x10 +#define HWIO_IPA_UC_ACKQ_DATA_RD_0_ACK_VALUE1_BMSK 0xffff +#define HWIO_IPA_UC_ACKQ_DATA_RD_0_ACK_VALUE1_SHFT 0x0 + +#define HWIO_IPA_UC_ACKQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x0000017c) +#define HWIO_IPA_UC_ACKQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000017c) +#define HWIO_IPA_UC_ACKQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000017c) +#define HWIO_IPA_UC_ACKQ_STATUS_RMSK 0x1f1f7 +#define HWIO_IPA_UC_ACKQ_STATUS_ATTR 0x1 +#define HWIO_IPA_UC_ACKQ_STATUS_IN \ + in_dword_masked(HWIO_IPA_UC_ACKQ_STATUS_ADDR, HWIO_IPA_UC_ACKQ_STATUS_RMSK) +#define HWIO_IPA_UC_ACKQ_STATUS_INM(m) \ + in_dword_masked(HWIO_IPA_UC_ACKQ_STATUS_ADDR, m) +#define HWIO_IPA_UC_ACKQ_STATUS_ACKQ_DEPTH_BMSK 0x1f000 +#define HWIO_IPA_UC_ACKQ_STATUS_ACKQ_DEPTH_SHFT 0xc +#define HWIO_IPA_UC_ACKQ_STATUS_ACKQ_COUNT_BMSK 0x1f0 +#define HWIO_IPA_UC_ACKQ_STATUS_ACKQ_COUNT_SHFT 0x4 +#define HWIO_IPA_UC_ACKQ_STATUS_ACKQ_FULL_BMSK 0x4 +#define HWIO_IPA_UC_ACKQ_STATUS_ACKQ_FULL_SHFT 0x2 +#define HWIO_IPA_UC_ACKQ_STATUS_ACKQ_EMPTY_BMSK 0x2 +#define HWIO_IPA_UC_ACKQ_STATUS_ACKQ_EMPTY_SHFT 0x1 +#define HWIO_IPA_UC_ACKQ_STATUS_STATUS_BMSK 0x1 +#define HWIO_IPA_UC_ACKQ_STATUS_STATUS_SHFT 0x0 + +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x00000180 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x00000180 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x00000180 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_RMSK 0x7f +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_MAXn 4 +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_ATTR 0x2 +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_OUTI(n,val) \ + out_dword(HWIO_IPA_RX_SPLT_CMDQ_CMD_n_ADDR(n),val) +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_RELEASE_RD_PKT_ENHANCED_BMSK 0x40 +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_RELEASE_RD_PKT_ENHANCED_SHFT 0x6 +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_RELEASE_WR_PKT_BMSK 0x20 +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_RELEASE_WR_PKT_SHFT 0x5 +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_RELEASE_RD_PKT_BMSK 0x10 +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_RELEASE_RD_PKT_SHFT 0x4 +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_RELEASE_WR_CMD_BMSK 0x8 +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_RELEASE_WR_CMD_SHFT 0x3 +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_RELEASE_RD_CMD_BMSK 0x4 +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_RELEASE_RD_CMD_SHFT 0x2 +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_POP_CMD_BMSK 0x2 +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_POP_CMD_SHFT 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_WRITE_CMD_BMSK 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_WRITE_CMD_SHFT 0x0 + +#define HWIO_IPA_RX_SPLT_CMDQ_CFG_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x00000184 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_CFG_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x00000184 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_CFG_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x00000184 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_CFG_n_RMSK 0x3 +#define HWIO_IPA_RX_SPLT_CMDQ_CFG_n_MAXn 4 +#define HWIO_IPA_RX_SPLT_CMDQ_CFG_n_ATTR 0x3 +#define HWIO_IPA_RX_SPLT_CMDQ_CFG_n_INI(n) \ + in_dword_masked(HWIO_IPA_RX_SPLT_CMDQ_CFG_n_ADDR(n), HWIO_IPA_RX_SPLT_CMDQ_CFG_n_RMSK) +#define HWIO_IPA_RX_SPLT_CMDQ_CFG_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_RX_SPLT_CMDQ_CFG_n_ADDR(n), mask) +#define HWIO_IPA_RX_SPLT_CMDQ_CFG_n_OUTI(n,val) \ + out_dword(HWIO_IPA_RX_SPLT_CMDQ_CFG_n_ADDR(n),val) +#define HWIO_IPA_RX_SPLT_CMDQ_CFG_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_RX_SPLT_CMDQ_CFG_n_ADDR(n),mask,val,HWIO_IPA_RX_SPLT_CMDQ_CFG_n_INI(n)) +#define HWIO_IPA_RX_SPLT_CMDQ_CFG_n_BLOCK_WR_BMSK 0x2 +#define HWIO_IPA_RX_SPLT_CMDQ_CFG_n_BLOCK_WR_SHFT 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_CFG_n_BLOCK_RD_BMSK 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_CFG_n_BLOCK_RD_SHFT 0x0 + +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x00000188 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x00000188 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x00000188 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_RMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_MAXn 4 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_ATTR 0x3 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_INI(n) \ + in_dword_masked(HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_ADDR(n), HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_RMSK) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_ADDR(n), mask) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_OUTI(n,val) \ + out_dword(HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_ADDR(n),val) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_ADDR(n),mask,val,HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_INI(n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_CMDQ_SRC_LEN_F_BMSK 0xffff0000 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_CMDQ_SRC_LEN_F_SHFT 0x10 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_CMDQ_PACKET_LEN_F_BMSK 0xffff +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_CMDQ_PACKET_LEN_F_SHFT 0x0 + +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x0000018c + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x0000018c + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x0000018c + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_RMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_MAXn 4 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_ATTR 0x3 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_INI(n) \ + in_dword_masked(HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_ADDR(n), HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_RMSK) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_ADDR(n), mask) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_OUTI(n,val) \ + out_dword(HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_ADDR(n),val) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_ADDR(n),mask,val,HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_INI(n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_CMDQ_METADATA_F_BMSK 0xff000000 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_CMDQ_METADATA_F_SHFT 0x18 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_CMDQ_OPCODE_F_BMSK 0xff0000 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_CMDQ_OPCODE_F_SHFT 0x10 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_CMDQ_FLAGS_F_BMSK 0xfc00 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_CMDQ_FLAGS_F_SHFT 0xa +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_CMDQ_ORDER_F_BMSK 0x300 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_CMDQ_ORDER_F_SHFT 0x8 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_CMDQ_SRC_PIPE_F_BMSK 0xff +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_CMDQ_SRC_PIPE_F_SHFT 0x0 + +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x00000190 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x00000190 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x00000190 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_RMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_MAXn 4 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_ATTR 0x3 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_INI(n) \ + in_dword_masked(HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_ADDR(n), HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_RMSK) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_ADDR(n), mask) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_OUTI(n,val) \ + out_dword(HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_ADDR(n),val) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_ADDR(n),mask,val,HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_INI(n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_CMDQ_ADDR_LSB_F_BMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_CMDQ_ADDR_LSB_F_SHFT 0x0 + +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x00000194 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x00000194 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x00000194 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_RMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_MAXn 4 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_ATTR 0x3 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_INI(n) \ + in_dword_masked(HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_ADDR(n), HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_RMSK) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_ADDR(n), mask) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_OUTI(n,val) \ + out_dword(HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_ADDR(n),val) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_ADDR(n),mask,val,HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_INI(n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_CMDQ_ADDR_MSB_F_BMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_CMDQ_ADDR_MSB_F_SHFT 0x0 + +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_0_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x00000198 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_0_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x00000198 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_0_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x00000198 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_0_n_RMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_0_n_MAXn 4 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_0_n_ATTR 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_0_n_INI(n) \ + in_dword_masked(HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_0_n_ADDR(n), HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_0_n_RMSK) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_0_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_0_n_ADDR(n), mask) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_0_n_CMDQ_SRC_LEN_F_BMSK 0xffff0000 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_0_n_CMDQ_SRC_LEN_F_SHFT 0x10 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_0_n_CMDQ_PACKET_LEN_F_BMSK 0xffff +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_0_n_CMDQ_PACKET_LEN_F_SHFT 0x0 + +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x0000019c + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x0000019c + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x0000019c + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_RMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_MAXn 4 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_ATTR 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_INI(n) \ + in_dword_masked(HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_ADDR(n), HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_RMSK) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_ADDR(n), mask) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_CMDQ_METADATA_F_BMSK 0xff000000 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_CMDQ_METADATA_F_SHFT 0x18 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_CMDQ_OPCODE_F_BMSK 0xff0000 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_CMDQ_OPCODE_F_SHFT 0x10 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_CMDQ_FLAGS_F_BMSK 0xfc00 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_CMDQ_FLAGS_F_SHFT 0xa +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_CMDQ_ORDER_F_BMSK 0x300 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_CMDQ_ORDER_F_SHFT 0x8 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_CMDQ_SRC_PIPE_F_BMSK 0xff +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_CMDQ_SRC_PIPE_F_SHFT 0x0 + +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_2_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x000001a0 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_2_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x000001a0 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_2_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x000001a0 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_2_n_RMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_2_n_MAXn 4 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_2_n_ATTR 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_2_n_INI(n) \ + in_dword_masked(HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_2_n_ADDR(n), HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_2_n_RMSK) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_2_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_2_n_ADDR(n), mask) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_2_n_CMDQ_ADDR_LSB_F_BMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_2_n_CMDQ_ADDR_LSB_F_SHFT 0x0 + +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_3_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x000001a4 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_3_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x000001a4 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_3_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x000001a4 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_3_n_RMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_3_n_MAXn 4 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_3_n_ATTR 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_3_n_INI(n) \ + in_dword_masked(HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_3_n_ADDR(n), HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_3_n_RMSK) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_3_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_3_n_ADDR(n), mask) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_3_n_CMDQ_ADDR_MSB_F_BMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_3_n_CMDQ_ADDR_MSB_F_SHFT 0x0 + +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x000001a8 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x000001a8 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x000001a8 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_RMSK 0x7f +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_MAXn 4 +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_ATTR 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_INI(n) \ + in_dword_masked(HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_ADDR(n), HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_RMSK) +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_ADDR(n), mask) +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_CMDQ_DEPTH_BMSK 0x60 +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_CMDQ_DEPTH_SHFT 0x5 +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_CMDQ_COUNT_BMSK 0x18 +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_CMDQ_COUNT_SHFT 0x3 +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_CMDQ_FULL_BMSK 0x4 +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_CMDQ_FULL_SHFT 0x2 +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_CMDQ_EMPTY_BMSK 0x2 +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_CMDQ_EMPTY_SHFT 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_STATUS_BMSK 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_STATUS_SHFT 0x0 + +#define HWIO_IPA_TX_COMMANDER_CMDQ_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x0000025c) +#define HWIO_IPA_TX_COMMANDER_CMDQ_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000025c) +#define HWIO_IPA_TX_COMMANDER_CMDQ_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000025c) +#define HWIO_IPA_TX_COMMANDER_CMDQ_CMD_RMSK 0x17 +#define HWIO_IPA_TX_COMMANDER_CMDQ_CMD_ATTR 0x2 +#define HWIO_IPA_TX_COMMANDER_CMDQ_CMD_OUT(v) \ + out_dword(HWIO_IPA_TX_COMMANDER_CMDQ_CMD_ADDR,v) +#define HWIO_IPA_TX_COMMANDER_CMDQ_CMD_RELEASE_WR_PKT_BMSK 0x10 +#define HWIO_IPA_TX_COMMANDER_CMDQ_CMD_RELEASE_WR_PKT_SHFT 0x4 +#define HWIO_IPA_TX_COMMANDER_CMDQ_CMD_RELEASE_WR_CMD_BMSK 0x4 +#define HWIO_IPA_TX_COMMANDER_CMDQ_CMD_RELEASE_WR_CMD_SHFT 0x2 +#define HWIO_IPA_TX_COMMANDER_CMDQ_CMD_POP_CMD_BMSK 0x2 +#define HWIO_IPA_TX_COMMANDER_CMDQ_CMD_POP_CMD_SHFT 0x1 +#define HWIO_IPA_TX_COMMANDER_CMDQ_CMD_WRITE_CMD_BMSK 0x1 +#define HWIO_IPA_TX_COMMANDER_CMDQ_CMD_WRITE_CMD_SHFT 0x0 + +#define HWIO_IPA_TX_COMMANDER_CMDQ_CFG_ADDR (IPA_DEBUG_REG_BASE + 0x00000260) +#define HWIO_IPA_TX_COMMANDER_CMDQ_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000260) +#define HWIO_IPA_TX_COMMANDER_CMDQ_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000260) +#define HWIO_IPA_TX_COMMANDER_CMDQ_CFG_RMSK 0x11 +#define HWIO_IPA_TX_COMMANDER_CMDQ_CFG_ATTR 0x3 +#define HWIO_IPA_TX_COMMANDER_CMDQ_CFG_IN \ + in_dword_masked(HWIO_IPA_TX_COMMANDER_CMDQ_CFG_ADDR, HWIO_IPA_TX_COMMANDER_CMDQ_CFG_RMSK) +#define HWIO_IPA_TX_COMMANDER_CMDQ_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_TX_COMMANDER_CMDQ_CFG_ADDR, m) +#define HWIO_IPA_TX_COMMANDER_CMDQ_CFG_OUT(v) \ + out_dword(HWIO_IPA_TX_COMMANDER_CMDQ_CFG_ADDR,v) +#define HWIO_IPA_TX_COMMANDER_CMDQ_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_TX_COMMANDER_CMDQ_CFG_ADDR,m,v,HWIO_IPA_TX_COMMANDER_CMDQ_CFG_IN) +#define HWIO_IPA_TX_COMMANDER_CMDQ_CFG_TX_SELECT_BMSK 0x10 +#define HWIO_IPA_TX_COMMANDER_CMDQ_CFG_TX_SELECT_SHFT 0x4 +#define HWIO_IPA_TX_COMMANDER_CMDQ_CFG_BLOCK_WR_BMSK 0x1 +#define HWIO_IPA_TX_COMMANDER_CMDQ_CFG_BLOCK_WR_SHFT 0x0 + +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_0_ADDR (IPA_DEBUG_REG_BASE + 0x00000264) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000264) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000264) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_0_RMSK 0xffffffff +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_0_ATTR 0x3 +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_0_IN \ + in_dword_masked(HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_0_ADDR, HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_0_RMSK) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_0_INM(m) \ + in_dword_masked(HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_0_ADDR, m) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_0_OUT(v) \ + out_dword(HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_0_ADDR,v) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_0_ADDR,m,v,HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_0_IN) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_0_CMDQ_DEST_LEN_F_BMSK 0xffff0000 +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_0_CMDQ_DEST_LEN_F_SHFT 0x10 +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_0_CMDQ_PACKET_LEN_F_BMSK 0xffff +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_0_CMDQ_PACKET_LEN_F_SHFT 0x0 + +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_1_ADDR (IPA_DEBUG_REG_BASE + 0x00000268) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_1_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000268) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_1_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000268) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_1_RMSK 0xffffffff +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_1_ATTR 0x3 +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_1_IN \ + in_dword_masked(HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_1_ADDR, HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_1_RMSK) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_1_INM(m) \ + in_dword_masked(HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_1_ADDR, m) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_1_OUT(v) \ + out_dword(HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_1_ADDR,v) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_1_ADDR,m,v,HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_1_IN) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_1_CMDQ_RSRC_ARG_F_BMSK 0xff000000 +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_1_CMDQ_RSRC_ARG_F_SHFT 0x18 +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_1_CMDQ_RSRC_TYPE_F_BMSK 0xff0000 +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_1_CMDQ_RSRC_TYPE_F_SHFT 0x10 +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_1_CMDQ_FLAGS_F_BMSK 0xfc00 +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_1_CMDQ_FLAGS_F_SHFT 0xa +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_1_CMDQ_ORDER_F_BMSK 0x300 +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_1_CMDQ_ORDER_F_SHFT 0x8 +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_1_CMDQ_DEST_PIPE_F_BMSK 0xff +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_1_CMDQ_DEST_PIPE_F_SHFT 0x0 + +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_2_ADDR (IPA_DEBUG_REG_BASE + 0x0000026c) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_2_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000026c) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_2_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000026c) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_2_RMSK 0xffffffff +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_2_ATTR 0x3 +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_2_IN \ + in_dword_masked(HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_2_ADDR, HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_2_RMSK) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_2_INM(m) \ + in_dword_masked(HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_2_ADDR, m) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_2_OUT(v) \ + out_dword(HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_2_ADDR,v) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_2_ADDR,m,v,HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_2_IN) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_2_CMDQ_ADDR_F_BMSK 0xffffffff +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_2_CMDQ_ADDR_F_SHFT 0x0 + +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_0_ADDR (IPA_DEBUG_REG_BASE + 0x00000270) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000270) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000270) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_0_RMSK 0xffffffff +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_0_ATTR 0x1 +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_0_IN \ + in_dword_masked(HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_0_ADDR, HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_0_RMSK) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_0_INM(m) \ + in_dword_masked(HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_0_ADDR, m) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_0_CMDQ_DEST_LEN_F_BMSK 0xffff0000 +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_0_CMDQ_DEST_LEN_F_SHFT 0x10 +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_0_CMDQ_PACKET_LEN_F_BMSK 0xffff +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_0_CMDQ_PACKET_LEN_F_SHFT 0x0 + +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_1_ADDR (IPA_DEBUG_REG_BASE + 0x00000274) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_1_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000274) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_1_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000274) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_1_RMSK 0xffffffff +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_1_ATTR 0x1 +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_1_IN \ + in_dword_masked(HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_1_ADDR, HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_1_RMSK) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_1_INM(m) \ + in_dword_masked(HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_1_ADDR, m) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_1_CMDQ_RSRC_ARG_F_BMSK 0xff000000 +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_1_CMDQ_RSRC_ARG_F_SHFT 0x18 +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_1_CMDQ_RSRC_TYPE_F_BMSK 0xff0000 +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_1_CMDQ_RSRC_TYPE_F_SHFT 0x10 +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_1_CMDQ_FLAGS_F_BMSK 0xfc00 +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_1_CMDQ_FLAGS_F_SHFT 0xa +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_1_CMDQ_ORDER_F_BMSK 0x300 +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_1_CMDQ_ORDER_F_SHFT 0x8 +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_1_CMDQ_DEST_PIPE_F_BMSK 0xff +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_1_CMDQ_DEST_PIPE_F_SHFT 0x0 + +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_2_ADDR (IPA_DEBUG_REG_BASE + 0x00000278) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_2_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000278) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_2_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000278) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_2_RMSK 0xffffffff +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_2_ATTR 0x1 +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_2_IN \ + in_dword_masked(HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_2_ADDR, HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_2_RMSK) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_2_INM(m) \ + in_dword_masked(HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_2_ADDR, m) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_2_CMDQ_ADDR_F_BMSK 0xffffffff +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_2_CMDQ_ADDR_F_SHFT 0x0 + +#define HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x0000027c) +#define HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000027c) +#define HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000027c) +#define HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_RMSK 0x7 +#define HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_ATTR 0x1 +#define HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_IN \ + in_dword_masked(HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_ADDR, HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_RMSK) +#define HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_INM(m) \ + in_dword_masked(HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_ADDR, m) +#define HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_CMDQ_FULL_BMSK 0x4 +#define HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_CMDQ_FULL_SHFT 0x2 +#define HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_CMDQ_EMPTY_BMSK 0x2 +#define HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_CMDQ_EMPTY_SHFT 0x1 +#define HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_STATUS_BMSK 0x1 +#define HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_STATUS_SHFT 0x0 + +#define HWIO_IPA_RX_HPS_CMDQ_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x00000280) +#define HWIO_IPA_RX_HPS_CMDQ_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000280) +#define HWIO_IPA_RX_HPS_CMDQ_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000280) +#define HWIO_IPA_RX_HPS_CMDQ_CMD_RMSK 0x3f +#define HWIO_IPA_RX_HPS_CMDQ_CMD_ATTR 0x3 +#define HWIO_IPA_RX_HPS_CMDQ_CMD_IN \ + in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_CMD_ADDR, HWIO_IPA_RX_HPS_CMDQ_CMD_RMSK) +#define HWIO_IPA_RX_HPS_CMDQ_CMD_INM(m) \ + in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_CMD_ADDR, m) +#define HWIO_IPA_RX_HPS_CMDQ_CMD_OUT(v) \ + out_dword(HWIO_IPA_RX_HPS_CMDQ_CMD_ADDR,v) +#define HWIO_IPA_RX_HPS_CMDQ_CMD_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_RX_HPS_CMDQ_CMD_ADDR,m,v,HWIO_IPA_RX_HPS_CMDQ_CMD_IN) +#define HWIO_IPA_RX_HPS_CMDQ_CMD_RD_REQ_BMSK 0x20 +#define HWIO_IPA_RX_HPS_CMDQ_CMD_RD_REQ_SHFT 0x5 +#define HWIO_IPA_RX_HPS_CMDQ_CMD_CMD_CLIENT_BMSK 0x1c +#define HWIO_IPA_RX_HPS_CMDQ_CMD_CMD_CLIENT_SHFT 0x2 +#define HWIO_IPA_RX_HPS_CMDQ_CMD_POP_CMD_BMSK 0x2 +#define HWIO_IPA_RX_HPS_CMDQ_CMD_POP_CMD_SHFT 0x1 +#define HWIO_IPA_RX_HPS_CMDQ_CMD_WRITE_CMD_BMSK 0x1 +#define HWIO_IPA_RX_HPS_CMDQ_CMD_WRITE_CMD_SHFT 0x0 + +#define HWIO_IPA_RX_HPS_CMDQ_RELEASE_WR_ADDR (IPA_DEBUG_REG_BASE + 0x00000284) +#define HWIO_IPA_RX_HPS_CMDQ_RELEASE_WR_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000284) +#define HWIO_IPA_RX_HPS_CMDQ_RELEASE_WR_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000284) +#define HWIO_IPA_RX_HPS_CMDQ_RELEASE_WR_RMSK 0x3f +#define HWIO_IPA_RX_HPS_CMDQ_RELEASE_WR_ATTR 0x2 +#define HWIO_IPA_RX_HPS_CMDQ_RELEASE_WR_OUT(v) \ + out_dword(HWIO_IPA_RX_HPS_CMDQ_RELEASE_WR_ADDR,v) +#define HWIO_IPA_RX_HPS_CMDQ_RELEASE_WR_RELEASE_WR_CMD_BMSK 0x3f +#define HWIO_IPA_RX_HPS_CMDQ_RELEASE_WR_RELEASE_WR_CMD_SHFT 0x0 + +#define HWIO_IPA_RX_HPS_CMDQ_RELEASE_RD_ADDR (IPA_DEBUG_REG_BASE + 0x00000288) +#define HWIO_IPA_RX_HPS_CMDQ_RELEASE_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000288) +#define HWIO_IPA_RX_HPS_CMDQ_RELEASE_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000288) +#define HWIO_IPA_RX_HPS_CMDQ_RELEASE_RD_RMSK 0x3f +#define HWIO_IPA_RX_HPS_CMDQ_RELEASE_RD_ATTR 0x2 +#define HWIO_IPA_RX_HPS_CMDQ_RELEASE_RD_OUT(v) \ + out_dword(HWIO_IPA_RX_HPS_CMDQ_RELEASE_RD_ADDR,v) +#define HWIO_IPA_RX_HPS_CMDQ_RELEASE_RD_RELEASE_RD_CMD_BMSK 0x3f +#define HWIO_IPA_RX_HPS_CMDQ_RELEASE_RD_RELEASE_RD_CMD_SHFT 0x0 + +#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_ADDR (IPA_DEBUG_REG_BASE + 0x0000028c) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000028c) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000028c) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_RMSK 0x3f +#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_ATTR 0x3 +#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_IN \ + in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_CFG_WR_ADDR, HWIO_IPA_RX_HPS_CMDQ_CFG_WR_RMSK) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_INM(m) \ + in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_CFG_WR_ADDR, m) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_OUT(v) \ + out_dword(HWIO_IPA_RX_HPS_CMDQ_CFG_WR_ADDR,v) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_RX_HPS_CMDQ_CFG_WR_ADDR,m,v,HWIO_IPA_RX_HPS_CMDQ_CFG_WR_IN) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_BLOCK_WR_BMSK 0x3f +#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_BLOCK_WR_SHFT 0x0 + +#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_ADDR (IPA_DEBUG_REG_BASE + 0x00000290) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000290) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000290) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_RMSK 0x3f +#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_ATTR 0x3 +#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_IN \ + in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_CFG_RD_ADDR, HWIO_IPA_RX_HPS_CMDQ_CFG_RD_RMSK) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_INM(m) \ + in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_CFG_RD_ADDR, m) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_OUT(v) \ + out_dword(HWIO_IPA_RX_HPS_CMDQ_CFG_RD_ADDR,v) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_RX_HPS_CMDQ_CFG_RD_ADDR,m,v,HWIO_IPA_RX_HPS_CMDQ_CFG_RD_IN) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_BLOCK_RD_BMSK 0x3f +#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_BLOCK_RD_SHFT 0x0 + +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_0_ADDR (IPA_DEBUG_REG_BASE + 0x00000294) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000294) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000294) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_0_RMSK 0xffffffff +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_0_ATTR 0x3 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_0_IN \ + in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_DATA_WR_0_ADDR, HWIO_IPA_RX_HPS_CMDQ_DATA_WR_0_RMSK) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_0_INM(m) \ + in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_DATA_WR_0_ADDR, m) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_0_OUT(v) \ + out_dword(HWIO_IPA_RX_HPS_CMDQ_DATA_WR_0_ADDR,v) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_RX_HPS_CMDQ_DATA_WR_0_ADDR,m,v,HWIO_IPA_RX_HPS_CMDQ_DATA_WR_0_IN) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_0_CMDQ_DEST_LEN_F_BMSK 0xffff0000 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_0_CMDQ_DEST_LEN_F_SHFT 0x10 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_0_CMDQ_PACKET_LEN_F_BMSK 0xffff +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_0_CMDQ_PACKET_LEN_F_SHFT 0x0 + +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_1_ADDR (IPA_DEBUG_REG_BASE + 0x00000298) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_1_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000298) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_1_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000298) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_1_RMSK 0xffffffff +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_1_ATTR 0x3 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_1_IN \ + in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_DATA_WR_1_ADDR, HWIO_IPA_RX_HPS_CMDQ_DATA_WR_1_RMSK) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_1_INM(m) \ + in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_DATA_WR_1_ADDR, m) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_1_OUT(v) \ + out_dword(HWIO_IPA_RX_HPS_CMDQ_DATA_WR_1_ADDR,v) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_RX_HPS_CMDQ_DATA_WR_1_ADDR,m,v,HWIO_IPA_RX_HPS_CMDQ_DATA_WR_1_IN) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_1_CMDQ_METADATA_F_BMSK 0xff000000 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_1_CMDQ_METADATA_F_SHFT 0x18 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_1_CMDQ_OPCODE_F_BMSK 0xff0000 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_1_CMDQ_OPCODE_F_SHFT 0x10 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_1_CMDQ_FLAGS_F_BMSK 0xfc00 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_1_CMDQ_FLAGS_F_SHFT 0xa +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_1_CMDQ_ORDER_F_BMSK 0x300 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_1_CMDQ_ORDER_F_SHFT 0x8 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_1_CMDQ_SRC_PIPE_F_BMSK 0xff +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_1_CMDQ_SRC_PIPE_F_SHFT 0x0 + +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_2_ADDR (IPA_DEBUG_REG_BASE + 0x0000029c) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_2_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000029c) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_2_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000029c) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_2_RMSK 0xffffffff +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_2_ATTR 0x3 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_2_IN \ + in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_DATA_WR_2_ADDR, HWIO_IPA_RX_HPS_CMDQ_DATA_WR_2_RMSK) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_2_INM(m) \ + in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_DATA_WR_2_ADDR, m) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_2_OUT(v) \ + out_dword(HWIO_IPA_RX_HPS_CMDQ_DATA_WR_2_ADDR,v) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_RX_HPS_CMDQ_DATA_WR_2_ADDR,m,v,HWIO_IPA_RX_HPS_CMDQ_DATA_WR_2_IN) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_2_CMDQ_ADDR_LSB_F_BMSK 0xffffffff +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_2_CMDQ_ADDR_LSB_F_SHFT 0x0 + +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_3_ADDR (IPA_DEBUG_REG_BASE + 0x000002a0) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_3_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000002a0) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_3_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000002a0) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_3_RMSK 0xffffffff +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_3_ATTR 0x3 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_3_IN \ + in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_DATA_WR_3_ADDR, HWIO_IPA_RX_HPS_CMDQ_DATA_WR_3_RMSK) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_3_INM(m) \ + in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_DATA_WR_3_ADDR, m) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_3_OUT(v) \ + out_dword(HWIO_IPA_RX_HPS_CMDQ_DATA_WR_3_ADDR,v) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_3_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_RX_HPS_CMDQ_DATA_WR_3_ADDR,m,v,HWIO_IPA_RX_HPS_CMDQ_DATA_WR_3_IN) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_3_CMDQ_ADDR_MSB_F_BMSK 0xffffffff +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_3_CMDQ_ADDR_MSB_F_SHFT 0x0 + +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_ADDR (IPA_DEBUG_REG_BASE + 0x000002a4) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000002a4) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000002a4) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_RMSK 0xffffffff +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_ATTR 0x1 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_IN \ + in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_ADDR, HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_RMSK, HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_ATTR) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_INM(m) \ + in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_ADDR, m, HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_ATTR) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_CMDQ_DEST_LEN_F_BMSK 0xffff0000 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_CMDQ_DEST_LEN_F_SHFT 0x10 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_CMDQ_PACKET_LEN_F_BMSK 0xffff +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_CMDQ_PACKET_LEN_F_SHFT 0x0 + +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_ADDR (IPA_DEBUG_REG_BASE + 0x000002a8) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000002a8) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000002a8) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_RMSK 0xffffffff +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_ATTR 0x1 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_IN \ + in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_ADDR, HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_RMSK, HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_ATTR) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_INM(m) \ + in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_ADDR, m, HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_ATTR) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_CMDQ_METADATA_F_BMSK 0xff000000 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_CMDQ_METADATA_F_SHFT 0x18 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_CMDQ_OPCODE_F_BMSK 0xff0000 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_CMDQ_OPCODE_F_SHFT 0x10 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_CMDQ_FLAGS_F_BMSK 0xfc00 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_CMDQ_FLAGS_F_SHFT 0xa +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_CMDQ_ORDER_F_BMSK 0x300 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_CMDQ_ORDER_F_SHFT 0x8 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_CMDQ_SRC_PIPE_F_BMSK 0xff +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_CMDQ_SRC_PIPE_F_SHFT 0x0 + +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_ADDR (IPA_DEBUG_REG_BASE + 0x000002ac) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000002ac) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000002ac) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_RMSK 0xffffffff +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_ATTR 0x1 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_IN \ + in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_ADDR, HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_RMSK, HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_ATTR) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_INM(m) \ + in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_ADDR, m, HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_ATTR) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_CMDQ_ADDR_LSB_F_BMSK 0xffffffff +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_CMDQ_ADDR_LSB_F_SHFT 0x0 + +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_ADDR (IPA_DEBUG_REG_BASE + 0x000002b0) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000002b0) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000002b0) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_RMSK 0xffffffff +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_ATTR 0x1 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_IN \ + in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_ADDR, HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_RMSK, HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_ATTR) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_INM(m) \ + in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_ADDR, m, HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_ATTR) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_CMDQ_ADDR_MSB_F_BMSK 0xffffffff +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_CMDQ_ADDR_MSB_F_SHFT 0x0 + +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x000002b4) +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000002b4) +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000002b4) +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_RMSK 0x1ff +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_ATTR 0x1 +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_IN \ + in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_STATUS_ADDR, HWIO_IPA_RX_HPS_CMDQ_STATUS_RMSK, HWIO_IPA_RX_HPS_CMDQ_STATUS_ATTR) +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_INM(m) \ + in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_STATUS_ADDR, m, HWIO_IPA_RX_HPS_CMDQ_STATUS_ATTR) +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_CMDQ_DEPTH_BMSK 0x1fc +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_CMDQ_DEPTH_SHFT 0x2 +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_CMDQ_FULL_BMSK 0x2 +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_CMDQ_FULL_SHFT 0x1 +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_STATUS_BMSK 0x1 +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_STATUS_SHFT 0x0 + +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_EMPTY_ADDR (IPA_DEBUG_REG_BASE + 0x000002b8) +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_EMPTY_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000002b8) +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_EMPTY_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000002b8) +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_EMPTY_RMSK 0x3f +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_EMPTY_ATTR 0x1 +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_EMPTY_IN \ + in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_STATUS_EMPTY_ADDR, HWIO_IPA_RX_HPS_CMDQ_STATUS_EMPTY_RMSK) +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_EMPTY_INM(m) \ + in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_STATUS_EMPTY_ADDR, m) +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_EMPTY_CMDQ_EMPTY_BMSK 0x3f +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_EMPTY_CMDQ_EMPTY_SHFT 0x0 + +#define HWIO_IPA_RX_HPS_SNP_ADDR (IPA_DEBUG_REG_BASE + 0x000002bc) +#define HWIO_IPA_RX_HPS_SNP_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000002bc) +#define HWIO_IPA_RX_HPS_SNP_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000002bc) +#define HWIO_IPA_RX_HPS_SNP_RMSK 0xffff +#define HWIO_IPA_RX_HPS_SNP_ATTR 0x3 +#define HWIO_IPA_RX_HPS_SNP_IN \ + in_dword_masked(HWIO_IPA_RX_HPS_SNP_ADDR, HWIO_IPA_RX_HPS_SNP_RMSK) +#define HWIO_IPA_RX_HPS_SNP_INM(m) \ + in_dword_masked(HWIO_IPA_RX_HPS_SNP_ADDR, m) +#define HWIO_IPA_RX_HPS_SNP_OUT(v) \ + out_dword(HWIO_IPA_RX_HPS_SNP_ADDR,v) +#define HWIO_IPA_RX_HPS_SNP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_RX_HPS_SNP_ADDR,m,v,HWIO_IPA_RX_HPS_SNP_IN) +#define HWIO_IPA_RX_HPS_SNP_SNP_ADDR_BMSK 0xf000 +#define HWIO_IPA_RX_HPS_SNP_SNP_ADDR_SHFT 0xc +#define HWIO_IPA_RX_HPS_SNP_SNP_HEAD_BMSK 0xf00 +#define HWIO_IPA_RX_HPS_SNP_SNP_HEAD_SHFT 0x8 +#define HWIO_IPA_RX_HPS_SNP_SNP_NEXT_BMSK 0xf0 +#define HWIO_IPA_RX_HPS_SNP_SNP_NEXT_SHFT 0x4 +#define HWIO_IPA_RX_HPS_SNP_SNP_NEXT_IS_VALID_BMSK 0x8 +#define HWIO_IPA_RX_HPS_SNP_SNP_NEXT_IS_VALID_SHFT 0x3 +#define HWIO_IPA_RX_HPS_SNP_SNP_VALID_BMSK 0x4 +#define HWIO_IPA_RX_HPS_SNP_SNP_VALID_SHFT 0x2 +#define HWIO_IPA_RX_HPS_SNP_SNP_WRITE_BMSK 0x2 +#define HWIO_IPA_RX_HPS_SNP_SNP_WRITE_SHFT 0x1 +#define HWIO_IPA_RX_HPS_SNP_SNP_LAST_BMSK 0x1 +#define HWIO_IPA_RX_HPS_SNP_SNP_LAST_SHFT 0x0 + +#define HWIO_IPA_RX_HPS_CMDQ_COUNT_ADDR (IPA_DEBUG_REG_BASE + 0x000002c0) +#define HWIO_IPA_RX_HPS_CMDQ_COUNT_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000002c0) +#define HWIO_IPA_RX_HPS_CMDQ_COUNT_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000002c0) +#define HWIO_IPA_RX_HPS_CMDQ_COUNT_RMSK 0x7f +#define HWIO_IPA_RX_HPS_CMDQ_COUNT_ATTR 0x1 +#define HWIO_IPA_RX_HPS_CMDQ_COUNT_IN \ + in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_COUNT_ADDR, HWIO_IPA_RX_HPS_CMDQ_COUNT_RMSK, HWIO_IPA_RX_HPS_CMDQ_COUNT_ATTR) +#define HWIO_IPA_RX_HPS_CMDQ_COUNT_INM(m) \ + in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_COUNT_ADDR, m, HWIO_IPA_RX_HPS_CMDQ_COUNT_ATTR) +#define HWIO_IPA_RX_HPS_CMDQ_COUNT_FIFO_COUNT_BMSK 0x7f +#define HWIO_IPA_RX_HPS_CMDQ_COUNT_FIFO_COUNT_SHFT 0x0 + +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_ADDR (IPA_DEBUG_REG_BASE + 0x000002c4) +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000002c4) +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000002c4) +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_RMSK 0xff0f0f0f +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_ATTR 0x3 +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_IN \ + in_dword_masked(HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_ADDR, HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_RMSK) +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_INM(m) \ + in_dword_masked(HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_ADDR, m) +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_OUT(v) \ + out_dword(HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_ADDR,v) +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_ADDR,m,v,HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_IN) +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_CLIENT_4_MIN_DEPTH_BMSK 0xf0000000 +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_CLIENT_4_MIN_DEPTH_SHFT 0x1c +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_CLIENT_3_MIN_DEPTH_BMSK 0xf000000 +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_CLIENT_3_MIN_DEPTH_SHFT 0x18 +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_CLIENT_2_MIN_DEPTH_BMSK 0xf0000 +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_CLIENT_2_MIN_DEPTH_SHFT 0x10 +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_CLIENT_1_MIN_DEPTH_BMSK 0xf00 +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_CLIENT_1_MIN_DEPTH_SHFT 0x8 +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_CLIENT_0_MIN_DEPTH_BMSK 0xf +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_CLIENT_0_MIN_DEPTH_SHFT 0x0 + +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_1_ADDR (IPA_DEBUG_REG_BASE + 0x000002c8) +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_1_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000002c8) +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_1_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000002c8) +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_1_RMSK 0xff0f0f0f +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_1_ATTR 0x3 +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_1_IN \ + in_dword_masked(HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_1_ADDR, HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_1_RMSK) +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_1_INM(m) \ + in_dword_masked(HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_1_ADDR, m) +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_1_OUT(v) \ + out_dword(HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_1_ADDR,v) +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_1_ADDR,m,v,HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_1_IN) +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_1_CLIENT_9_MIN_DEPTH_BMSK 0xf0000000 +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_1_CLIENT_9_MIN_DEPTH_SHFT 0x1c +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_1_CLIENT_8_MIN_DEPTH_BMSK 0xf000000 +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_1_CLIENT_8_MIN_DEPTH_SHFT 0x18 +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_1_CLIENT_7_MIN_DEPTH_BMSK 0xf0000 +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_1_CLIENT_7_MIN_DEPTH_SHFT 0x10 +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_1_CLIENT_6_MIN_DEPTH_BMSK 0xf00 +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_1_CLIENT_6_MIN_DEPTH_SHFT 0x8 +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_1_CLIENT_5_MIN_DEPTH_BMSK 0xf +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_1_CLIENT_5_MIN_DEPTH_SHFT 0x0 + +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_ADDR (IPA_DEBUG_REG_BASE + 0x000002cc) +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000002cc) +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000002cc) +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_RMSK 0xff0f0f0f +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_ATTR 0x3 +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_IN \ + in_dword_masked(HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_ADDR, HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_RMSK) +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_INM(m) \ + in_dword_masked(HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_ADDR, m) +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_OUT(v) \ + out_dword(HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_ADDR,v) +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_ADDR,m,v,HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_IN) +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_CLIENT_4_MAX_DEPTH_BMSK 0xf0000000 +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_CLIENT_4_MAX_DEPTH_SHFT 0x1c +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_CLIENT_3_MAX_DEPTH_BMSK 0xf000000 +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_CLIENT_3_MAX_DEPTH_SHFT 0x18 +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_CLIENT_2_MAX_DEPTH_BMSK 0xf0000 +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_CLIENT_2_MAX_DEPTH_SHFT 0x10 +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_CLIENT_1_MAX_DEPTH_BMSK 0xf00 +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_CLIENT_1_MAX_DEPTH_SHFT 0x8 +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_CLIENT_0_MAX_DEPTH_BMSK 0xf +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_CLIENT_0_MAX_DEPTH_SHFT 0x0 + +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_1_ADDR (IPA_DEBUG_REG_BASE + 0x000002d0) +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_1_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000002d0) +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_1_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000002d0) +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_1_RMSK 0xff0f0f0f +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_1_ATTR 0x3 +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_1_IN \ + in_dword_masked(HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_1_ADDR, HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_1_RMSK) +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_1_INM(m) \ + in_dword_masked(HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_1_ADDR, m) +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_1_OUT(v) \ + out_dword(HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_1_ADDR,v) +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_1_ADDR,m,v,HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_1_IN) +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_1_CLIENT_9_MAX_DEPTH_BMSK 0xf0000000 +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_1_CLIENT_9_MAX_DEPTH_SHFT 0x1c +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_1_CLIENT_8_MAX_DEPTH_BMSK 0xf000000 +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_1_CLIENT_8_MAX_DEPTH_SHFT 0x18 +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_1_CLIENT_7_MAX_DEPTH_BMSK 0xf0000 +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_1_CLIENT_7_MAX_DEPTH_SHFT 0x10 +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_1_CLIENT_6_MAX_DEPTH_BMSK 0xf00 +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_1_CLIENT_6_MAX_DEPTH_SHFT 0x8 +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_1_CLIENT_5_MAX_DEPTH_BMSK 0xf +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_1_CLIENT_5_MAX_DEPTH_SHFT 0x0 + +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x000002e0) +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000002e0) +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000002e0) +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_RMSK 0xff7 +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_ATTR 0x3 +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_IN \ + in_dword_masked(HWIO_IPA_HPS_DPS_CMDQ_CMD_ADDR, HWIO_IPA_HPS_DPS_CMDQ_CMD_RMSK) +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_INM(m) \ + in_dword_masked(HWIO_IPA_HPS_DPS_CMDQ_CMD_ADDR, m) +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_OUT(v) \ + out_dword(HWIO_IPA_HPS_DPS_CMDQ_CMD_ADDR,v) +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_HPS_DPS_CMDQ_CMD_ADDR,m,v,HWIO_IPA_HPS_DPS_CMDQ_CMD_IN) +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_CMD_CLIENT_BMSK 0xff0 +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_CMD_CLIENT_SHFT 0x4 +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_RD_REQ_BMSK 0x4 +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_RD_REQ_SHFT 0x2 +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_POP_CMD_BMSK 0x2 +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_POP_CMD_SHFT 0x1 +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_WRITE_CMD_BMSK 0x1 +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_WRITE_CMD_SHFT 0x0 + +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_ADDR (IPA_DEBUG_REG_BASE + 0x000002e4) +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000002e4) +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000002e4) +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_RMSK 0xffffff +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_ATTR 0x3 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_IN \ + in_dword_masked(HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_ADDR, HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_RMSK) +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_INM(m) \ + in_dword_masked(HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_ADDR, m) +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_OUT(v) \ + out_dword(HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_ADDR,v) +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_ADDR,m,v,HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_IN) +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_CMDQ_VIRT_COD_F_BMSK 0x800000 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_CMDQ_VIRT_COD_F_SHFT 0x17 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_CMDQ_TYPE_F_BMSK 0x400000 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_CMDQ_TYPE_F_SHFT 0x16 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_CMDQ_OPCODE_F_BMSK 0x300000 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_CMDQ_OPCODE_F_SHFT 0x14 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_CMDQ_SRC_PIPE_F_BMSK 0xff000 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_CMDQ_SRC_PIPE_F_SHFT 0xc +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_CMDQ_SRC_ID_F_BMSK 0xff0 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_CMDQ_SRC_ID_F_SHFT 0x4 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_CMDQ_CTX_ID_F_BMSK 0xf +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_CMDQ_CTX_ID_F_SHFT 0x0 + +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_ADDR (IPA_DEBUG_REG_BASE + 0x000002e8) +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000002e8) +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000002e8) +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_RMSK 0xffffff +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_ATTR 0x1 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_IN \ + in_dword_masked(HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_ADDR, HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_RMSK, HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_ATTR) +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_INM(m) \ + in_dword_masked(HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_ADDR, m, HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_ATTR) +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_CMDQ_VIRT_COD_F_BMSK 0x800000 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_CMDQ_VIRT_COD_F_SHFT 0x17 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_CMDQ_TYPE_F_BMSK 0x400000 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_CMDQ_TYPE_F_SHFT 0x16 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_CMDQ_OPCODE_F_BMSK 0x300000 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_CMDQ_OPCODE_F_SHFT 0x14 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_CMDQ_SRC_PIPE_F_BMSK 0xff000 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_CMDQ_SRC_PIPE_F_SHFT 0xc +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_CMDQ_SRC_ID_F_BMSK 0xff0 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_CMDQ_SRC_ID_F_SHFT 0x4 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_CMDQ_CTX_ID_F_BMSK 0xf +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_CMDQ_CTX_ID_F_SHFT 0x0 + +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x000002ec) +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000002ec) +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000002ec) +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_RMSK 0xff3 +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_ATTR 0x1 +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_IN \ + in_dword_masked(HWIO_IPA_HPS_DPS_CMDQ_STATUS_ADDR, HWIO_IPA_HPS_DPS_CMDQ_STATUS_RMSK, HWIO_IPA_HPS_DPS_CMDQ_STATUS_ATTR) +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_INM(m) \ + in_dword_masked(HWIO_IPA_HPS_DPS_CMDQ_STATUS_ADDR, m, HWIO_IPA_HPS_DPS_CMDQ_STATUS_ATTR) +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_CMDQ_DEPTH_BMSK 0xff0 +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_CMDQ_DEPTH_SHFT 0x4 +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_CMDQ_FULL_BMSK 0x2 +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_CMDQ_FULL_SHFT 0x1 +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_STATUS_BMSK 0x1 +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_STATUS_SHFT 0x0 + +#define HWIO_IPA_HPS_DPS_SNP_ADDR (IPA_DEBUG_REG_BASE + 0x000002f0) +#define HWIO_IPA_HPS_DPS_SNP_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000002f0) +#define HWIO_IPA_HPS_DPS_SNP_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000002f0) +#define HWIO_IPA_HPS_DPS_SNP_RMSK 0xfffffff +#define HWIO_IPA_HPS_DPS_SNP_ATTR 0x3 +#define HWIO_IPA_HPS_DPS_SNP_IN \ + in_dword_masked(HWIO_IPA_HPS_DPS_SNP_ADDR, HWIO_IPA_HPS_DPS_SNP_RMSK) +#define HWIO_IPA_HPS_DPS_SNP_INM(m) \ + in_dword_masked(HWIO_IPA_HPS_DPS_SNP_ADDR, m) +#define HWIO_IPA_HPS_DPS_SNP_OUT(v) \ + out_dword(HWIO_IPA_HPS_DPS_SNP_ADDR,v) +#define HWIO_IPA_HPS_DPS_SNP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_HPS_DPS_SNP_ADDR,m,v,HWIO_IPA_HPS_DPS_SNP_IN) +#define HWIO_IPA_HPS_DPS_SNP_SNP_ADDR_BMSK 0xff00000 +#define HWIO_IPA_HPS_DPS_SNP_SNP_ADDR_SHFT 0x14 +#define HWIO_IPA_HPS_DPS_SNP_SNP_HEAD_BMSK 0xff000 +#define HWIO_IPA_HPS_DPS_SNP_SNP_HEAD_SHFT 0xc +#define HWIO_IPA_HPS_DPS_SNP_SNP_NEXT_BMSK 0xff0 +#define HWIO_IPA_HPS_DPS_SNP_SNP_NEXT_SHFT 0x4 +#define HWIO_IPA_HPS_DPS_SNP_SNP_NEXT_IS_VALID_BMSK 0x8 +#define HWIO_IPA_HPS_DPS_SNP_SNP_NEXT_IS_VALID_SHFT 0x3 +#define HWIO_IPA_HPS_DPS_SNP_SNP_VALID_BMSK 0x4 +#define HWIO_IPA_HPS_DPS_SNP_SNP_VALID_SHFT 0x2 +#define HWIO_IPA_HPS_DPS_SNP_SNP_WRITE_BMSK 0x2 +#define HWIO_IPA_HPS_DPS_SNP_SNP_WRITE_SHFT 0x1 +#define HWIO_IPA_HPS_DPS_SNP_SNP_LAST_BMSK 0x1 +#define HWIO_IPA_HPS_DPS_SNP_SNP_LAST_SHFT 0x0 + +#define HWIO_IPA_HPS_DPS_CMDQ_COUNT_ADDR (IPA_DEBUG_REG_BASE + 0x000002f4) +#define HWIO_IPA_HPS_DPS_CMDQ_COUNT_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000002f4) +#define HWIO_IPA_HPS_DPS_CMDQ_COUNT_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000002f4) +#define HWIO_IPA_HPS_DPS_CMDQ_COUNT_RMSK 0xff +#define HWIO_IPA_HPS_DPS_CMDQ_COUNT_ATTR 0x1 +#define HWIO_IPA_HPS_DPS_CMDQ_COUNT_IN \ + in_dword_masked(HWIO_IPA_HPS_DPS_CMDQ_COUNT_ADDR, HWIO_IPA_HPS_DPS_CMDQ_COUNT_RMSK, HWIO_IPA_HPS_DPS_CMDQ_COUNT_ATTR) +#define HWIO_IPA_HPS_DPS_CMDQ_COUNT_INM(m) \ + in_dword_masked(HWIO_IPA_HPS_DPS_CMDQ_COUNT_ADDR, m, HWIO_IPA_HPS_DPS_CMDQ_COUNT_ATTR) +#define HWIO_IPA_HPS_DPS_CMDQ_COUNT_FIFO_COUNT_BMSK 0xff +#define HWIO_IPA_HPS_DPS_CMDQ_COUNT_FIFO_COUNT_SHFT 0x0 + +#define HWIO_IPA_HPS_DPS_CMDQ_RELEASE_WR_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x00000300 + 0x4 * (n)) +#define HWIO_IPA_HPS_DPS_CMDQ_RELEASE_WR_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x00000300 + 0x4 * (n)) +#define HWIO_IPA_HPS_DPS_CMDQ_RELEASE_WR_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x00000300 + 0x4 * (n)) +#define HWIO_IPA_HPS_DPS_CMDQ_RELEASE_WR_n_RMSK 0xffffffff +#define HWIO_IPA_HPS_DPS_CMDQ_RELEASE_WR_n_MAXn 1 +#define HWIO_IPA_HPS_DPS_CMDQ_RELEASE_WR_n_ATTR 0x2 +#define HWIO_IPA_HPS_DPS_CMDQ_RELEASE_WR_n_OUTI(n,val) \ + out_dword(HWIO_IPA_HPS_DPS_CMDQ_RELEASE_WR_n_ADDR(n),val) +#define HWIO_IPA_HPS_DPS_CMDQ_RELEASE_WR_n_RELEASE_WR_CMD_BMSK 0xffffffff +#define HWIO_IPA_HPS_DPS_CMDQ_RELEASE_WR_n_RELEASE_WR_CMD_SHFT 0x0 + +#define HWIO_IPA_HPS_DPS_CMDQ_RELEASE_RD_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x00000320 + 0x4 * (n)) +#define HWIO_IPA_HPS_DPS_CMDQ_RELEASE_RD_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x00000320 + 0x4 * (n)) +#define HWIO_IPA_HPS_DPS_CMDQ_RELEASE_RD_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x00000320 + 0x4 * (n)) +#define HWIO_IPA_HPS_DPS_CMDQ_RELEASE_RD_n_RMSK 0xffffffff +#define HWIO_IPA_HPS_DPS_CMDQ_RELEASE_RD_n_MAXn 1 +#define HWIO_IPA_HPS_DPS_CMDQ_RELEASE_RD_n_ATTR 0x2 +#define HWIO_IPA_HPS_DPS_CMDQ_RELEASE_RD_n_OUTI(n,val) \ + out_dword(HWIO_IPA_HPS_DPS_CMDQ_RELEASE_RD_n_ADDR(n),val) +#define HWIO_IPA_HPS_DPS_CMDQ_RELEASE_RD_n_RELEASE_RD_CMD_BMSK 0xffffffff +#define HWIO_IPA_HPS_DPS_CMDQ_RELEASE_RD_n_RELEASE_RD_CMD_SHFT 0x0 + +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_WR_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x00000340 + 0x4 * (n)) +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_WR_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x00000340 + 0x4 * (n)) +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_WR_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x00000340 + 0x4 * (n)) +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_WR_n_RMSK 0xffffffff +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_WR_n_MAXn 1 +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_WR_n_ATTR 0x3 +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_WR_n_INI(n) \ + in_dword_masked(HWIO_IPA_HPS_DPS_CMDQ_CFG_WR_n_ADDR(n), HWIO_IPA_HPS_DPS_CMDQ_CFG_WR_n_RMSK) +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_WR_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_HPS_DPS_CMDQ_CFG_WR_n_ADDR(n), mask) +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_WR_n_OUTI(n,val) \ + out_dword(HWIO_IPA_HPS_DPS_CMDQ_CFG_WR_n_ADDR(n),val) +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_WR_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_HPS_DPS_CMDQ_CFG_WR_n_ADDR(n),mask,val,HWIO_IPA_HPS_DPS_CMDQ_CFG_WR_n_INI(n)) +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_WR_n_BLOCK_WR_BMSK 0xffffffff +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_WR_n_BLOCK_WR_SHFT 0x0 + +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_RD_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x00000360 + 0x4 * (n)) +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_RD_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x00000360 + 0x4 * (n)) +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_RD_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x00000360 + 0x4 * (n)) +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_RD_n_RMSK 0xffffffff +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_RD_n_MAXn 1 +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_RD_n_ATTR 0x3 +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_RD_n_INI(n) \ + in_dword_masked(HWIO_IPA_HPS_DPS_CMDQ_CFG_RD_n_ADDR(n), HWIO_IPA_HPS_DPS_CMDQ_CFG_RD_n_RMSK) +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_RD_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_HPS_DPS_CMDQ_CFG_RD_n_ADDR(n), mask) +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_RD_n_OUTI(n,val) \ + out_dword(HWIO_IPA_HPS_DPS_CMDQ_CFG_RD_n_ADDR(n),val) +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_RD_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_HPS_DPS_CMDQ_CFG_RD_n_ADDR(n),mask,val,HWIO_IPA_HPS_DPS_CMDQ_CFG_RD_n_INI(n)) +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_RD_n_BLOCK_RD_BMSK 0xffffffff +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_RD_n_BLOCK_RD_SHFT 0x0 + +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_EMPTY_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x00000380 + 0x4 * (n)) +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_EMPTY_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x00000380 + 0x4 * (n)) +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_EMPTY_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x00000380 + 0x4 * (n)) +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_EMPTY_n_RMSK 0xffffffff +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_EMPTY_n_MAXn 1 +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_EMPTY_n_ATTR 0x1 +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_EMPTY_n_INI(n) \ + in_dword_masked(HWIO_IPA_HPS_DPS_CMDQ_STATUS_EMPTY_n_ADDR(n), HWIO_IPA_HPS_DPS_CMDQ_STATUS_EMPTY_n_RMSK) +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_EMPTY_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_HPS_DPS_CMDQ_STATUS_EMPTY_n_ADDR(n), mask) +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_EMPTY_n_CMDQ_EMPTY_BMSK 0xffffffff +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_EMPTY_n_CMDQ_EMPTY_SHFT 0x0 + +#define HWIO_IPA_DPS_TX_CMDQ_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x00000400) +#define HWIO_IPA_DPS_TX_CMDQ_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000400) +#define HWIO_IPA_DPS_TX_CMDQ_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000400) +#define HWIO_IPA_DPS_TX_CMDQ_CMD_RMSK 0x7f +#define HWIO_IPA_DPS_TX_CMDQ_CMD_ATTR 0x3 +#define HWIO_IPA_DPS_TX_CMDQ_CMD_IN \ + in_dword_masked(HWIO_IPA_DPS_TX_CMDQ_CMD_ADDR, HWIO_IPA_DPS_TX_CMDQ_CMD_RMSK) +#define HWIO_IPA_DPS_TX_CMDQ_CMD_INM(m) \ + in_dword_masked(HWIO_IPA_DPS_TX_CMDQ_CMD_ADDR, m) +#define HWIO_IPA_DPS_TX_CMDQ_CMD_OUT(v) \ + out_dword(HWIO_IPA_DPS_TX_CMDQ_CMD_ADDR,v) +#define HWIO_IPA_DPS_TX_CMDQ_CMD_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_DPS_TX_CMDQ_CMD_ADDR,m,v,HWIO_IPA_DPS_TX_CMDQ_CMD_IN) +#define HWIO_IPA_DPS_TX_CMDQ_CMD_CMD_CLIENT_BMSK 0x78 +#define HWIO_IPA_DPS_TX_CMDQ_CMD_CMD_CLIENT_SHFT 0x3 +#define HWIO_IPA_DPS_TX_CMDQ_CMD_RD_REQ_BMSK 0x4 +#define HWIO_IPA_DPS_TX_CMDQ_CMD_RD_REQ_SHFT 0x2 +#define HWIO_IPA_DPS_TX_CMDQ_CMD_POP_CMD_BMSK 0x2 +#define HWIO_IPA_DPS_TX_CMDQ_CMD_POP_CMD_SHFT 0x1 +#define HWIO_IPA_DPS_TX_CMDQ_CMD_WRITE_CMD_BMSK 0x1 +#define HWIO_IPA_DPS_TX_CMDQ_CMD_WRITE_CMD_SHFT 0x0 + +#define HWIO_IPA_DPS_TX_CMDQ_RELEASE_WR_ADDR (IPA_DEBUG_REG_BASE + 0x00000404) +#define HWIO_IPA_DPS_TX_CMDQ_RELEASE_WR_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000404) +#define HWIO_IPA_DPS_TX_CMDQ_RELEASE_WR_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000404) +#define HWIO_IPA_DPS_TX_CMDQ_RELEASE_WR_RMSK 0xfff +#define HWIO_IPA_DPS_TX_CMDQ_RELEASE_WR_ATTR 0x2 +#define HWIO_IPA_DPS_TX_CMDQ_RELEASE_WR_OUT(v) \ + out_dword(HWIO_IPA_DPS_TX_CMDQ_RELEASE_WR_ADDR,v) +#define HWIO_IPA_DPS_TX_CMDQ_RELEASE_WR_RELEASE_WR_CMD_BMSK 0xfff +#define HWIO_IPA_DPS_TX_CMDQ_RELEASE_WR_RELEASE_WR_CMD_SHFT 0x0 + +#define HWIO_IPA_DPS_TX_CMDQ_RELEASE_RD_ADDR (IPA_DEBUG_REG_BASE + 0x00000408) +#define HWIO_IPA_DPS_TX_CMDQ_RELEASE_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000408) +#define HWIO_IPA_DPS_TX_CMDQ_RELEASE_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000408) +#define HWIO_IPA_DPS_TX_CMDQ_RELEASE_RD_RMSK 0xfff +#define HWIO_IPA_DPS_TX_CMDQ_RELEASE_RD_ATTR 0x2 +#define HWIO_IPA_DPS_TX_CMDQ_RELEASE_RD_OUT(v) \ + out_dword(HWIO_IPA_DPS_TX_CMDQ_RELEASE_RD_ADDR,v) +#define HWIO_IPA_DPS_TX_CMDQ_RELEASE_RD_RELEASE_RD_CMD_BMSK 0xfff +#define HWIO_IPA_DPS_TX_CMDQ_RELEASE_RD_RELEASE_RD_CMD_SHFT 0x0 + +#define HWIO_IPA_DPS_TX_CMDQ_CFG_WR_ADDR (IPA_DEBUG_REG_BASE + 0x0000040c) +#define HWIO_IPA_DPS_TX_CMDQ_CFG_WR_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000040c) +#define HWIO_IPA_DPS_TX_CMDQ_CFG_WR_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000040c) +#define HWIO_IPA_DPS_TX_CMDQ_CFG_WR_RMSK 0xfff +#define HWIO_IPA_DPS_TX_CMDQ_CFG_WR_ATTR 0x3 +#define HWIO_IPA_DPS_TX_CMDQ_CFG_WR_IN \ + in_dword_masked(HWIO_IPA_DPS_TX_CMDQ_CFG_WR_ADDR, HWIO_IPA_DPS_TX_CMDQ_CFG_WR_RMSK) +#define HWIO_IPA_DPS_TX_CMDQ_CFG_WR_INM(m) \ + in_dword_masked(HWIO_IPA_DPS_TX_CMDQ_CFG_WR_ADDR, m) +#define HWIO_IPA_DPS_TX_CMDQ_CFG_WR_OUT(v) \ + out_dword(HWIO_IPA_DPS_TX_CMDQ_CFG_WR_ADDR,v) +#define HWIO_IPA_DPS_TX_CMDQ_CFG_WR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_DPS_TX_CMDQ_CFG_WR_ADDR,m,v,HWIO_IPA_DPS_TX_CMDQ_CFG_WR_IN) +#define HWIO_IPA_DPS_TX_CMDQ_CFG_WR_BLOCK_WR_BMSK 0xfff +#define HWIO_IPA_DPS_TX_CMDQ_CFG_WR_BLOCK_WR_SHFT 0x0 + +#define HWIO_IPA_DPS_TX_CMDQ_CFG_RD_ADDR (IPA_DEBUG_REG_BASE + 0x00000410) +#define HWIO_IPA_DPS_TX_CMDQ_CFG_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000410) +#define HWIO_IPA_DPS_TX_CMDQ_CFG_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000410) +#define HWIO_IPA_DPS_TX_CMDQ_CFG_RD_RMSK 0xfff +#define HWIO_IPA_DPS_TX_CMDQ_CFG_RD_ATTR 0x3 +#define HWIO_IPA_DPS_TX_CMDQ_CFG_RD_IN \ + in_dword_masked(HWIO_IPA_DPS_TX_CMDQ_CFG_RD_ADDR, HWIO_IPA_DPS_TX_CMDQ_CFG_RD_RMSK) +#define HWIO_IPA_DPS_TX_CMDQ_CFG_RD_INM(m) \ + in_dword_masked(HWIO_IPA_DPS_TX_CMDQ_CFG_RD_ADDR, m) +#define HWIO_IPA_DPS_TX_CMDQ_CFG_RD_OUT(v) \ + out_dword(HWIO_IPA_DPS_TX_CMDQ_CFG_RD_ADDR,v) +#define HWIO_IPA_DPS_TX_CMDQ_CFG_RD_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_DPS_TX_CMDQ_CFG_RD_ADDR,m,v,HWIO_IPA_DPS_TX_CMDQ_CFG_RD_IN) +#define HWIO_IPA_DPS_TX_CMDQ_CFG_RD_BLOCK_RD_BMSK 0xfff +#define HWIO_IPA_DPS_TX_CMDQ_CFG_RD_BLOCK_RD_SHFT 0x0 + +#define HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_ADDR (IPA_DEBUG_REG_BASE + 0x00000414) +#define HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000414) +#define HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000414) +#define HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_RMSK 0x7ffffff +#define HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_ATTR 0x3 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_IN \ + in_dword_masked(HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_ADDR, HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_RMSK) +#define HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_INM(m) \ + in_dword_masked(HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_ADDR, m) +#define HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_OUT(v) \ + out_dword(HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_ADDR,v) +#define HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_ADDR,m,v,HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_IN) +#define HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_SEG_CTX_ID_F_BMSK 0x6000000 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_SEG_CTX_ID_F_SHFT 0x19 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_SEG_VALID_F_BMSK 0x1000000 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_SEG_VALID_F_SHFT 0x18 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_CMDQ_VIRT_COD_F_BMSK 0x800000 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_CMDQ_VIRT_COD_F_SHFT 0x17 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_CMDQ_TYPE_F_BMSK 0x400000 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_CMDQ_TYPE_F_SHFT 0x16 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_CMDQ_OPCODE_F_BMSK 0x300000 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_CMDQ_OPCODE_F_SHFT 0x14 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_CMDQ_SRC_PIPE_F_BMSK 0xff000 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_CMDQ_SRC_PIPE_F_SHFT 0xc +#define HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_CMDQ_SRC_ID_F_BMSK 0xff0 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_CMDQ_SRC_ID_F_SHFT 0x4 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_CMDQ_CTX_ID_F_BMSK 0xf +#define HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_CMDQ_CTX_ID_F_SHFT 0x0 + +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_ADDR (IPA_DEBUG_REG_BASE + 0x00000418) +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000418) +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000418) +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_RMSK 0x7ffffff +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_ATTR 0x1 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_IN \ + in_dword_masked(HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_ADDR, HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_RMSK, HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_ATTR) +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_INM(m) \ + in_dword_masked(HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_ADDR, m, HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_ATTR) +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_SEG_CTX_ID_F_BMSK 0x6000000 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_SEG_CTX_ID_F_SHFT 0x19 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_SEG_VALID_F_BMSK 0x1000000 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_SEG_VALID_F_SHFT 0x18 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_CMDQ_VIRT_COD_F_BMSK 0x800000 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_CMDQ_VIRT_COD_F_SHFT 0x17 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_CMDQ_TYPE_F_BMSK 0x400000 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_CMDQ_TYPE_F_SHFT 0x16 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_CMDQ_OPCODE_F_BMSK 0x300000 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_CMDQ_OPCODE_F_SHFT 0x14 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_CMDQ_SRC_PIPE_F_BMSK 0xff000 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_CMDQ_SRC_PIPE_F_SHFT 0xc +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_CMDQ_SRC_ID_F_BMSK 0xff0 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_CMDQ_SRC_ID_F_SHFT 0x4 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_CMDQ_CTX_ID_F_BMSK 0xf +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_CMDQ_CTX_ID_F_SHFT 0x0 + +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x0000041c) +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000041c) +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000041c) +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_RMSK 0xff3 +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_ATTR 0x1 +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_IN \ + in_dword_masked(HWIO_IPA_DPS_TX_CMDQ_STATUS_ADDR, HWIO_IPA_DPS_TX_CMDQ_STATUS_RMSK, HWIO_IPA_DPS_TX_CMDQ_STATUS_ATTR) +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_INM(m) \ + in_dword_masked(HWIO_IPA_DPS_TX_CMDQ_STATUS_ADDR, m, HWIO_IPA_DPS_TX_CMDQ_STATUS_ATTR) +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_CMDQ_DEPTH_BMSK 0xff0 +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_CMDQ_DEPTH_SHFT 0x4 +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_CMDQ_FULL_BMSK 0x2 +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_CMDQ_FULL_SHFT 0x1 +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_STATUS_BMSK 0x1 +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_STATUS_SHFT 0x0 + +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_EMPTY_ADDR (IPA_DEBUG_REG_BASE + 0x00000420) +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_EMPTY_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000420) +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_EMPTY_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000420) +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_EMPTY_RMSK 0xfff +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_EMPTY_ATTR 0x1 +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_EMPTY_IN \ + in_dword_masked(HWIO_IPA_DPS_TX_CMDQ_STATUS_EMPTY_ADDR, HWIO_IPA_DPS_TX_CMDQ_STATUS_EMPTY_RMSK) +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_EMPTY_INM(m) \ + in_dword_masked(HWIO_IPA_DPS_TX_CMDQ_STATUS_EMPTY_ADDR, m) +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_EMPTY_CMDQ_EMPTY_BMSK 0xfff +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_EMPTY_CMDQ_EMPTY_SHFT 0x0 + +#define HWIO_IPA_DPS_TX_SNP_ADDR (IPA_DEBUG_REG_BASE + 0x00000424) +#define HWIO_IPA_DPS_TX_SNP_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000424) +#define HWIO_IPA_DPS_TX_SNP_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000424) +#define HWIO_IPA_DPS_TX_SNP_RMSK 0xfffffff +#define HWIO_IPA_DPS_TX_SNP_ATTR 0x3 +#define HWIO_IPA_DPS_TX_SNP_IN \ + in_dword_masked(HWIO_IPA_DPS_TX_SNP_ADDR, HWIO_IPA_DPS_TX_SNP_RMSK) +#define HWIO_IPA_DPS_TX_SNP_INM(m) \ + in_dword_masked(HWIO_IPA_DPS_TX_SNP_ADDR, m) +#define HWIO_IPA_DPS_TX_SNP_OUT(v) \ + out_dword(HWIO_IPA_DPS_TX_SNP_ADDR,v) +#define HWIO_IPA_DPS_TX_SNP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_DPS_TX_SNP_ADDR,m,v,HWIO_IPA_DPS_TX_SNP_IN) +#define HWIO_IPA_DPS_TX_SNP_SNP_ADDR_BMSK 0xff00000 +#define HWIO_IPA_DPS_TX_SNP_SNP_ADDR_SHFT 0x14 +#define HWIO_IPA_DPS_TX_SNP_SNP_HEAD_BMSK 0xff000 +#define HWIO_IPA_DPS_TX_SNP_SNP_HEAD_SHFT 0xc +#define HWIO_IPA_DPS_TX_SNP_SNP_NEXT_BMSK 0xff0 +#define HWIO_IPA_DPS_TX_SNP_SNP_NEXT_SHFT 0x4 +#define HWIO_IPA_DPS_TX_SNP_SNP_NEXT_IS_VALID_BMSK 0x8 +#define HWIO_IPA_DPS_TX_SNP_SNP_NEXT_IS_VALID_SHFT 0x3 +#define HWIO_IPA_DPS_TX_SNP_SNP_VALID_BMSK 0x4 +#define HWIO_IPA_DPS_TX_SNP_SNP_VALID_SHFT 0x2 +#define HWIO_IPA_DPS_TX_SNP_SNP_WRITE_BMSK 0x2 +#define HWIO_IPA_DPS_TX_SNP_SNP_WRITE_SHFT 0x1 +#define HWIO_IPA_DPS_TX_SNP_SNP_LAST_BMSK 0x1 +#define HWIO_IPA_DPS_TX_SNP_SNP_LAST_SHFT 0x0 + +#define HWIO_IPA_DPS_TX_CMDQ_COUNT_ADDR (IPA_DEBUG_REG_BASE + 0x00000428) +#define HWIO_IPA_DPS_TX_CMDQ_COUNT_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000428) +#define HWIO_IPA_DPS_TX_CMDQ_COUNT_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000428) +#define HWIO_IPA_DPS_TX_CMDQ_COUNT_RMSK 0x7f +#define HWIO_IPA_DPS_TX_CMDQ_COUNT_ATTR 0x1 +#define HWIO_IPA_DPS_TX_CMDQ_COUNT_IN \ + in_dword_masked(HWIO_IPA_DPS_TX_CMDQ_COUNT_ADDR, HWIO_IPA_DPS_TX_CMDQ_COUNT_RMSK, HWIO_IPA_DPS_TX_CMDQ_COUNT_ATTR) +#define HWIO_IPA_DPS_TX_CMDQ_COUNT_INM(m) \ + in_dword_masked(HWIO_IPA_DPS_TX_CMDQ_COUNT_ADDR, m, HWIO_IPA_DPS_TX_CMDQ_COUNT_ATTR) +#define HWIO_IPA_DPS_TX_CMDQ_COUNT_FIFO_COUNT_BMSK 0x7f +#define HWIO_IPA_DPS_TX_CMDQ_COUNT_FIFO_COUNT_SHFT 0x0 + +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_ADDR (IPA_DEBUG_REG_BASE + 0x0000042c) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000042c) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000042c) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_RMSK 0x7 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_IN \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_ADDR, HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_RMSK) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_INM(m) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_ADDR, m) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_OUT(v) \ + out_dword(HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_ADDR,v) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_ADDR,m,v,HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_IN) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_BITMAP_BMSK 0x7 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_BITMAP_SHFT 0x0 + +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_ADDR (IPA_DEBUG_REG_BASE + 0x00000430) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000430) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000430) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_RMSK 0x7 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_IN \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_ADDR, HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_RMSK) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_INM(m) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_ADDR, m) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_OUT(v) \ + out_dword(HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_ADDR,v) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_ADDR,m,v,HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_IN) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_BITMAP_BMSK 0x7 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_BITMAP_SHFT 0x0 + +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_ADDR (IPA_DEBUG_REG_BASE + 0x00000434) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000434) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000434) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_RMSK 0x7fff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_IN \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_ADDR, HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_RMSK) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_INM(m) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_ADDR, m) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_OUT(v) \ + out_dword(HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_ADDR,v) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_ADDR,m,v,HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_IN) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_ALL_CLI_MUX_CONCAT_BMSK 0x7fff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_ALL_CLI_MUX_CONCAT_SHFT 0x0 + +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x00000438 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x00000438 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x00000438 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_MAXn 2 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_INI(n) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_ADDR(n), HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_RMSK) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_ADDR(n), mask) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_OUTI(n,val) \ + out_dword(HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_ADDR(n),val) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_ADDR(n),mask,val,HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_INI(n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_VALUE_SHFT 0x0 + +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x0000043c + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x0000043c + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x0000043c + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_MAXn 2 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_INI(n) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_ADDR(n), HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_RMSK) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_ADDR(n), mask) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_OUTI(n,val) \ + out_dword(HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_ADDR(n),val) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_ADDR(n),mask,val,HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_INI(n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_VALUE_SHFT 0x0 + +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x00000440 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x00000440 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x00000440 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_MAXn 2 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_INI(n) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_ADDR(n), HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_RMSK) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_ADDR(n), mask) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_OUTI(n,val) \ + out_dword(HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_ADDR(n),val) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_ADDR(n),mask,val,HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_INI(n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_VALUE_SHFT 0x0 + +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x00000444 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x00000444 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x00000444 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_MAXn 2 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_INI(n) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_ADDR(n), HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_RMSK) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_ADDR(n), mask) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_OUTI(n,val) \ + out_dword(HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_ADDR(n),val) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_ADDR(n),mask,val,HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_INI(n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_VALUE_SHFT 0x0 + +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x00000468 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x00000468 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x00000468 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_MAXn 2 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_INI(n) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_ADDR(n), HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_RMSK) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_ADDR(n), mask) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_OUTI(n,val) \ + out_dword(HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_ADDR(n),val) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_ADDR(n),mask,val,HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_INI(n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_VALUE_SHFT 0x0 + +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x0000046c + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x0000046c + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x0000046c + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_MAXn 2 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_INI(n) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_ADDR(n), HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_RMSK) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_ADDR(n), mask) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_OUTI(n,val) \ + out_dword(HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_ADDR(n),val) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_ADDR(n),mask,val,HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_INI(n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_VALUE_SHFT 0x0 + +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x00000470 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x00000470 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x00000470 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_MAXn 2 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_INI(n) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_ADDR(n), HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_RMSK) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_ADDR(n), mask) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_OUTI(n,val) \ + out_dword(HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_ADDR(n),val) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_ADDR(n),mask,val,HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_INI(n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_VALUE_SHFT 0x0 + +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x00000474 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x00000474 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x00000474 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_MAXn 2 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_INI(n) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_ADDR(n), HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_RMSK) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_ADDR(n), mask) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_OUTI(n,val) \ + out_dword(HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_ADDR(n),val) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_ADDR(n),mask,val,HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_INI(n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_VALUE_SHFT 0x0 + +#define HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_ADDR (IPA_DEBUG_REG_BASE + 0x00000498) +#define HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000498) +#define HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000498) +#define HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_RMSK 0x7 +#define HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_IN \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_ADDR, HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_RMSK) +#define HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_INM(m) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_ADDR, m) +#define HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_OUT(v) \ + out_dword(HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_ADDR,v) +#define HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_ADDR,m,v,HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_IN) +#define HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_SRC_GROUP_SEL_BMSK 0x7 +#define HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_SRC_GROUP_SEL_SHFT 0x0 + +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x000004a0) +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000004a0) +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000004a0) +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_RMSK 0x7ff +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_ATTR 0x3 +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_IN \ + in_dword_masked(HWIO_IPA_ACKMNGR_CMDQ_CMD_ADDR, HWIO_IPA_ACKMNGR_CMDQ_CMD_RMSK) +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_INM(m) \ + in_dword_masked(HWIO_IPA_ACKMNGR_CMDQ_CMD_ADDR, m) +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_OUT(v) \ + out_dword(HWIO_IPA_ACKMNGR_CMDQ_CMD_ADDR,v) +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_ACKMNGR_CMDQ_CMD_ADDR,m,v,HWIO_IPA_ACKMNGR_CMDQ_CMD_IN) +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_RD_REQ_BMSK 0x400 +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_RD_REQ_SHFT 0xa +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_CMD_CLIENT_BMSK 0x3fc +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_CMD_CLIENT_SHFT 0x2 +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_POP_CMD_BMSK 0x2 +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_POP_CMD_SHFT 0x1 +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_WRITE_CMD_BMSK 0x1 +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_WRITE_CMD_SHFT 0x0 + +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_ADDR (IPA_DEBUG_REG_BASE + 0x000004b8) +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000004b8) +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000004b8) +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_RMSK 0xfffffff +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_ATTR 0x1 +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_IN \ + in_dword_masked(HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_ADDR, HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_RMSK, HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_ATTR) +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_INM(m) \ + in_dword_masked(HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_ADDR, m, HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_ATTR) +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_CMDQ_ERROR_BMSK 0x8000000 +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_CMDQ_ERROR_SHFT 0x1b +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_CMDQ_SRC_ID_VALID_BMSK 0x4000000 +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_CMDQ_SRC_ID_VALID_SHFT 0x1a +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_CMDQ_SENT_BMSK 0x2000000 +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_CMDQ_SENT_SHFT 0x19 +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_CMDQ_ORIGIN_BMSK 0x1000000 +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_CMDQ_ORIGIN_SHFT 0x18 +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_CMDQ_LENGTH_BMSK 0xffff00 +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_CMDQ_LENGTH_SHFT 0x8 +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_CMDQ_SRC_ID_BMSK 0xff +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_CMDQ_SRC_ID_SHFT 0x0 + +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x000004bc) +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000004bc) +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000004bc) +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_RMSK 0x1ff +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_ATTR 0x1 +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_IN \ + in_dword_masked(HWIO_IPA_ACKMNGR_CMDQ_STATUS_ADDR, HWIO_IPA_ACKMNGR_CMDQ_STATUS_RMSK, HWIO_IPA_ACKMNGR_CMDQ_STATUS_ATTR) +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_INM(m) \ + in_dword_masked(HWIO_IPA_ACKMNGR_CMDQ_STATUS_ADDR, m, HWIO_IPA_ACKMNGR_CMDQ_STATUS_ATTR) +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_CMDQ_DEPTH_BMSK 0x1fc +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_CMDQ_DEPTH_SHFT 0x2 +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_CMDQ_FULL_BMSK 0x2 +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_CMDQ_FULL_SHFT 0x1 +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_STATUS_BMSK 0x1 +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_STATUS_SHFT 0x0 + +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_EMPTY_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x000004c0 + 0x4 * (n)) +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_EMPTY_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x000004c0 + 0x4 * (n)) +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_EMPTY_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x000004c0 + 0x4 * (n)) +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_EMPTY_n_RMSK 0xffffffff +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_EMPTY_n_MAXn 1 +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_EMPTY_n_ATTR 0x1 +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_EMPTY_n_INI(n) \ + in_dword_masked(HWIO_IPA_ACKMNGR_CMDQ_STATUS_EMPTY_n_ADDR(n), HWIO_IPA_ACKMNGR_CMDQ_STATUS_EMPTY_n_RMSK) +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_EMPTY_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ACKMNGR_CMDQ_STATUS_EMPTY_n_ADDR(n), mask) +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_EMPTY_n_CMDQ_EMPTY_BMSK 0xffffffff +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_EMPTY_n_CMDQ_EMPTY_SHFT 0x0 + +#define HWIO_IPA_ACKMNGR_CMDQ_COUNT_ADDR (IPA_DEBUG_REG_BASE + 0x000004e0) +#define HWIO_IPA_ACKMNGR_CMDQ_COUNT_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000004e0) +#define HWIO_IPA_ACKMNGR_CMDQ_COUNT_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000004e0) +#define HWIO_IPA_ACKMNGR_CMDQ_COUNT_RMSK 0x7f +#define HWIO_IPA_ACKMNGR_CMDQ_COUNT_ATTR 0x1 +#define HWIO_IPA_ACKMNGR_CMDQ_COUNT_IN \ + in_dword_masked(HWIO_IPA_ACKMNGR_CMDQ_COUNT_ADDR, HWIO_IPA_ACKMNGR_CMDQ_COUNT_RMSK, HWIO_IPA_ACKMNGR_CMDQ_COUNT_ATTR) +#define HWIO_IPA_ACKMNGR_CMDQ_COUNT_INM(m) \ + in_dword_masked(HWIO_IPA_ACKMNGR_CMDQ_COUNT_ADDR, m, HWIO_IPA_ACKMNGR_CMDQ_COUNT_ATTR) +#define HWIO_IPA_ACKMNGR_CMDQ_COUNT_FIFO_COUNT_BMSK 0x7f +#define HWIO_IPA_ACKMNGR_CMDQ_COUNT_FIFO_COUNT_SHFT 0x0 + +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_ADDR (IPA_DEBUG_REG_BASE + 0x000004e4) +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000004e4) +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000004e4) +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_RMSK 0x3f +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_ATTR 0x3 +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_IN \ + in_dword_masked(HWIO_IPA_GSI_FIFO_STATUS_CTRL_ADDR, HWIO_IPA_GSI_FIFO_STATUS_CTRL_RMSK, HWIO_IPA_GSI_FIFO_STATUS_CTRL_ATTR) +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_FIFO_STATUS_CTRL_ADDR, m, HWIO_IPA_GSI_FIFO_STATUS_CTRL_ATTR) +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_OUT(v) \ + out_dword(HWIO_IPA_GSI_FIFO_STATUS_CTRL_ADDR,v, HWIO_IPA_GSI_FIFO_STATUS_CTRL_ATTR) +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_FIFO_STATUS_CTRL_ADDR,m,v,HWIO_IPA_GSI_FIFO_STATUS_CTRL_IN) +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_IPA_GSI_FIFO_STATUS_EN_BMSK 0x20 +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_IPA_GSI_FIFO_STATUS_EN_SHFT 0x5 +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_IPA_GSI_FIFO_STATUS_PORT_SEL_BMSK 0x1f +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_IPA_GSI_FIFO_STATUS_PORT_SEL_SHFT 0x0 + +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x000004e8) +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000004e8) +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000004e8) +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_RMSK 0x7fffffff +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_ATTR 0x1 +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_IN \ + in_dword_masked(HWIO_IPA_GSI_TLV_FIFO_STATUS_ADDR, HWIO_IPA_GSI_TLV_FIFO_STATUS_RMSK, HWIO_IPA_GSI_TLV_FIFO_STATUS_ATTR) +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TLV_FIFO_STATUS_ADDR, m, HWIO_IPA_GSI_TLV_FIFO_STATUS_ATTR) +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FIFO_HEAD_IS_BUBBLE_BMSK 0x40000000 +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FIFO_HEAD_IS_BUBBLE_SHFT 0x1e +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FIFO_FULL_PUB_BMSK 0x20000000 +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FIFO_FULL_PUB_SHFT 0x1d +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FIFO_ALMOST_FULL_PUB_BMSK 0x10000000 +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FIFO_ALMOST_FULL_PUB_SHFT 0x1c +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FIFO_FULL_BMSK 0x8000000 +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FIFO_FULL_SHFT 0x1b +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FIFO_ALMOST_FULL_BMSK 0x4000000 +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FIFO_ALMOST_FULL_SHFT 0x1a +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FIFO_EMPTY_PUB_BMSK 0x2000000 +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FIFO_EMPTY_PUB_SHFT 0x19 +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FIFO_EMPTY_BMSK 0x1000000 +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FIFO_EMPTY_SHFT 0x18 +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FIFO_RD_PUB_PTR_BMSK 0xff0000 +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FIFO_RD_PUB_PTR_SHFT 0x10 +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FIFO_RD_PTR_BMSK 0xff00 +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FIFO_RD_PTR_SHFT 0x8 +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FIFO_WR_PTR_BMSK 0xff +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FIFO_WR_PTR_SHFT 0x0 + +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x000004ec) +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000004ec) +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000004ec) +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_RMSK 0x7fffffff +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_ATTR 0x1 +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_IN \ + in_dword_masked(HWIO_IPA_GSI_AOS_FIFO_STATUS_ADDR, HWIO_IPA_GSI_AOS_FIFO_STATUS_RMSK, HWIO_IPA_GSI_AOS_FIFO_STATUS_ATTR) +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_AOS_FIFO_STATUS_ADDR, m, HWIO_IPA_GSI_AOS_FIFO_STATUS_ATTR) +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FIFO_HEAD_IS_BUBBLE_BMSK 0x40000000 +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FIFO_HEAD_IS_BUBBLE_SHFT 0x1e +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FIFO_FULL_PUB_BMSK 0x20000000 +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FIFO_FULL_PUB_SHFT 0x1d +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FIFO_ALMOST_FULL_PUB_BMSK 0x10000000 +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FIFO_ALMOST_FULL_PUB_SHFT 0x1c +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FIFO_FULL_BMSK 0x8000000 +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FIFO_FULL_SHFT 0x1b +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FIFO_ALMOST_FULL_BMSK 0x4000000 +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FIFO_ALMOST_FULL_SHFT 0x1a +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FIFO_EMPTY_PUB_BMSK 0x2000000 +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FIFO_EMPTY_PUB_SHFT 0x19 +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FIFO_EMPTY_BMSK 0x1000000 +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FIFO_EMPTY_SHFT 0x18 +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FIFO_RD_PUB_PTR_BMSK 0xff0000 +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FIFO_RD_PUB_PTR_SHFT 0x10 +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FIFO_RD_PTR_BMSK 0xff00 +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FIFO_RD_PTR_SHFT 0x8 +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FIFO_WR_PTR_BMSK 0xff +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FIFO_WR_PTR_SHFT 0x0 + +#define HWIO_IPA_ENDP_GSI_CONS_BYTES_TLV_ADDR (IPA_DEBUG_REG_BASE + 0x000004f0) +#define HWIO_IPA_ENDP_GSI_CONS_BYTES_TLV_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000004f0) +#define HWIO_IPA_ENDP_GSI_CONS_BYTES_TLV_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000004f0) +#define HWIO_IPA_ENDP_GSI_CONS_BYTES_TLV_RMSK 0xffff +#define HWIO_IPA_ENDP_GSI_CONS_BYTES_TLV_ATTR 0x1 +#define HWIO_IPA_ENDP_GSI_CONS_BYTES_TLV_IN \ + in_dword_masked(HWIO_IPA_ENDP_GSI_CONS_BYTES_TLV_ADDR, HWIO_IPA_ENDP_GSI_CONS_BYTES_TLV_RMSK) +#define HWIO_IPA_ENDP_GSI_CONS_BYTES_TLV_INM(m) \ + in_dword_masked(HWIO_IPA_ENDP_GSI_CONS_BYTES_TLV_ADDR, m) +#define HWIO_IPA_ENDP_GSI_CONS_BYTES_TLV_CONS_BYTES_BMSK 0xffff +#define HWIO_IPA_ENDP_GSI_CONS_BYTES_TLV_CONS_BYTES_SHFT 0x0 + +#define HWIO_IPA_ENDP_GSI_CONS_BYTES_AOS_ADDR (IPA_DEBUG_REG_BASE + 0x000004f4) +#define HWIO_IPA_ENDP_GSI_CONS_BYTES_AOS_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000004f4) +#define HWIO_IPA_ENDP_GSI_CONS_BYTES_AOS_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000004f4) +#define HWIO_IPA_ENDP_GSI_CONS_BYTES_AOS_RMSK 0xffff +#define HWIO_IPA_ENDP_GSI_CONS_BYTES_AOS_ATTR 0x1 +#define HWIO_IPA_ENDP_GSI_CONS_BYTES_AOS_IN \ + in_dword_masked(HWIO_IPA_ENDP_GSI_CONS_BYTES_AOS_ADDR, HWIO_IPA_ENDP_GSI_CONS_BYTES_AOS_RMSK) +#define HWIO_IPA_ENDP_GSI_CONS_BYTES_AOS_INM(m) \ + in_dword_masked(HWIO_IPA_ENDP_GSI_CONS_BYTES_AOS_ADDR, m) +#define HWIO_IPA_ENDP_GSI_CONS_BYTES_AOS_CONS_BYTES_BMSK 0xffff +#define HWIO_IPA_ENDP_GSI_CONS_BYTES_AOS_CONS_BYTES_SHFT 0x0 + +#define HWIO_IPA_LOG_BUF_HW_GEN_RAM_OFFSET_ADDR (IPA_DEBUG_REG_BASE + 0x000004f8) +#define HWIO_IPA_LOG_BUF_HW_GEN_RAM_OFFSET_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000004f8) +#define HWIO_IPA_LOG_BUF_HW_GEN_RAM_OFFSET_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000004f8) +#define HWIO_IPA_LOG_BUF_HW_GEN_RAM_OFFSET_RMSK 0x80f7ffff +#define HWIO_IPA_LOG_BUF_HW_GEN_RAM_OFFSET_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_GEN_RAM_OFFSET_IN \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_GEN_RAM_OFFSET_ADDR, HWIO_IPA_LOG_BUF_HW_GEN_RAM_OFFSET_RMSK) +#define HWIO_IPA_LOG_BUF_HW_GEN_RAM_OFFSET_INM(m) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_GEN_RAM_OFFSET_ADDR, m) +#define HWIO_IPA_LOG_BUF_HW_GEN_RAM_OFFSET_OUT(v) \ + out_dword(HWIO_IPA_LOG_BUF_HW_GEN_RAM_OFFSET_ADDR,v) +#define HWIO_IPA_LOG_BUF_HW_GEN_RAM_OFFSET_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_LOG_BUF_HW_GEN_RAM_OFFSET_ADDR,m,v,HWIO_IPA_LOG_BUF_HW_GEN_RAM_OFFSET_IN) +#define HWIO_IPA_LOG_BUF_HW_GEN_RAM_OFFSET_ENABLE_BMSK 0x80000000 +#define HWIO_IPA_LOG_BUF_HW_GEN_RAM_OFFSET_ENABLE_SHFT 0x1f +#define HWIO_IPA_LOG_BUF_HW_GEN_RAM_OFFSET_RAM_REGION_SIZE_BMSK 0xf00000 +#define HWIO_IPA_LOG_BUF_HW_GEN_RAM_OFFSET_RAM_REGION_SIZE_SHFT 0x14 +#define HWIO_IPA_LOG_BUF_HW_GEN_RAM_OFFSET_RAM_REGION_BADDR_BMSK 0x7ffff +#define HWIO_IPA_LOG_BUF_HW_GEN_RAM_OFFSET_RAM_REGION_BADDR_SHFT 0x0 + +#define HWIO_IPA_UC_RX_HND_CMDQ_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x00000538) +#define HWIO_IPA_UC_RX_HND_CMDQ_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000538) +#define HWIO_IPA_UC_RX_HND_CMDQ_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000538) +#define HWIO_IPA_UC_RX_HND_CMDQ_CMD_RMSK 0x7f +#define HWIO_IPA_UC_RX_HND_CMDQ_CMD_ATTR 0x2 +#define HWIO_IPA_UC_RX_HND_CMDQ_CMD_OUT(v) \ + out_dword(HWIO_IPA_UC_RX_HND_CMDQ_CMD_ADDR,v) +#define HWIO_IPA_UC_RX_HND_CMDQ_CMD_RELEASE_RD_PKT_ENHANCED_BMSK 0x40 +#define HWIO_IPA_UC_RX_HND_CMDQ_CMD_RELEASE_RD_PKT_ENHANCED_SHFT 0x6 +#define HWIO_IPA_UC_RX_HND_CMDQ_CMD_RELEASE_WR_PKT_BMSK 0x20 +#define HWIO_IPA_UC_RX_HND_CMDQ_CMD_RELEASE_WR_PKT_SHFT 0x5 +#define HWIO_IPA_UC_RX_HND_CMDQ_CMD_RELEASE_RD_PKT_BMSK 0x10 +#define HWIO_IPA_UC_RX_HND_CMDQ_CMD_RELEASE_RD_PKT_SHFT 0x4 +#define HWIO_IPA_UC_RX_HND_CMDQ_CMD_RELEASE_WR_CMD_BMSK 0x8 +#define HWIO_IPA_UC_RX_HND_CMDQ_CMD_RELEASE_WR_CMD_SHFT 0x3 +#define HWIO_IPA_UC_RX_HND_CMDQ_CMD_RELEASE_RD_CMD_BMSK 0x4 +#define HWIO_IPA_UC_RX_HND_CMDQ_CMD_RELEASE_RD_CMD_SHFT 0x2 +#define HWIO_IPA_UC_RX_HND_CMDQ_CMD_POP_CMD_BMSK 0x2 +#define HWIO_IPA_UC_RX_HND_CMDQ_CMD_POP_CMD_SHFT 0x1 +#define HWIO_IPA_UC_RX_HND_CMDQ_CMD_WRITE_CMD_BMSK 0x1 +#define HWIO_IPA_UC_RX_HND_CMDQ_CMD_WRITE_CMD_SHFT 0x0 + +#define HWIO_IPA_UC_RX_HND_CMDQ_CFG_ADDR (IPA_DEBUG_REG_BASE + 0x0000053c) +#define HWIO_IPA_UC_RX_HND_CMDQ_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000053c) +#define HWIO_IPA_UC_RX_HND_CMDQ_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000053c) +#define HWIO_IPA_UC_RX_HND_CMDQ_CFG_RMSK 0x3 +#define HWIO_IPA_UC_RX_HND_CMDQ_CFG_ATTR 0x3 +#define HWIO_IPA_UC_RX_HND_CMDQ_CFG_IN \ + in_dword_masked(HWIO_IPA_UC_RX_HND_CMDQ_CFG_ADDR, HWIO_IPA_UC_RX_HND_CMDQ_CFG_RMSK) +#define HWIO_IPA_UC_RX_HND_CMDQ_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_UC_RX_HND_CMDQ_CFG_ADDR, m) +#define HWIO_IPA_UC_RX_HND_CMDQ_CFG_OUT(v) \ + out_dword(HWIO_IPA_UC_RX_HND_CMDQ_CFG_ADDR,v) +#define HWIO_IPA_UC_RX_HND_CMDQ_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_RX_HND_CMDQ_CFG_ADDR,m,v,HWIO_IPA_UC_RX_HND_CMDQ_CFG_IN) +#define HWIO_IPA_UC_RX_HND_CMDQ_CFG_BLOCK_WR_BMSK 0x2 +#define HWIO_IPA_UC_RX_HND_CMDQ_CFG_BLOCK_WR_SHFT 0x1 +#define HWIO_IPA_UC_RX_HND_CMDQ_CFG_BLOCK_RD_BMSK 0x1 +#define HWIO_IPA_UC_RX_HND_CMDQ_CFG_BLOCK_RD_SHFT 0x0 + +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_0_ADDR (IPA_DEBUG_REG_BASE + 0x00000540) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000540) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000540) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_0_RMSK 0xffffffff +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_0_ATTR 0x3 +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_0_IN \ + in_dword_masked(HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_0_ADDR, HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_0_RMSK) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_0_INM(m) \ + in_dword_masked(HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_0_ADDR, m) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_0_OUT(v) \ + out_dword(HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_0_ADDR,v) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_0_ADDR,m,v,HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_0_IN) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_0_CMDQ_SRC_LEN_F_BMSK 0xffff0000 +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_0_CMDQ_SRC_LEN_F_SHFT 0x10 +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_0_CMDQ_PACKET_LEN_F_BMSK 0xffff +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_0_CMDQ_PACKET_LEN_F_SHFT 0x0 + +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_1_ADDR (IPA_DEBUG_REG_BASE + 0x00000544) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_1_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000544) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_1_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000544) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_1_RMSK 0xffffffff +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_1_ATTR 0x3 +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_1_IN \ + in_dword_masked(HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_1_ADDR, HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_1_RMSK) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_1_INM(m) \ + in_dword_masked(HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_1_ADDR, m) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_1_OUT(v) \ + out_dword(HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_1_ADDR,v) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_1_ADDR,m,v,HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_1_IN) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_1_CMDQ_METADATA_F_BMSK 0xff000000 +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_1_CMDQ_METADATA_F_SHFT 0x18 +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_1_CMDQ_OPCODE_F_BMSK 0xff0000 +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_1_CMDQ_OPCODE_F_SHFT 0x10 +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_1_CMDQ_FLAGS_F_BMSK 0xfc00 +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_1_CMDQ_FLAGS_F_SHFT 0xa +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_1_CMDQ_ORDER_F_BMSK 0x300 +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_1_CMDQ_ORDER_F_SHFT 0x8 +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_1_CMDQ_SRC_PIPE_F_BMSK 0xff +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_1_CMDQ_SRC_PIPE_F_SHFT 0x0 + +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_2_ADDR (IPA_DEBUG_REG_BASE + 0x00000548) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_2_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000548) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_2_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000548) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_2_RMSK 0xffffffff +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_2_ATTR 0x3 +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_2_IN \ + in_dword_masked(HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_2_ADDR, HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_2_RMSK) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_2_INM(m) \ + in_dword_masked(HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_2_ADDR, m) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_2_OUT(v) \ + out_dword(HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_2_ADDR,v) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_2_ADDR,m,v,HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_2_IN) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_2_CMDQ_ADDR_LSB_F_BMSK 0xffffffff +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_2_CMDQ_ADDR_LSB_F_SHFT 0x0 + +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_3_ADDR (IPA_DEBUG_REG_BASE + 0x0000054c) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_3_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000054c) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_3_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000054c) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_3_RMSK 0xffffffff +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_3_ATTR 0x3 +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_3_IN \ + in_dword_masked(HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_3_ADDR, HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_3_RMSK) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_3_INM(m) \ + in_dword_masked(HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_3_ADDR, m) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_3_OUT(v) \ + out_dword(HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_3_ADDR,v) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_3_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_3_ADDR,m,v,HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_3_IN) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_3_CMDQ_ADDR_MSB_F_BMSK 0xffffffff +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_3_CMDQ_ADDR_MSB_F_SHFT 0x0 + +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_0_ADDR (IPA_DEBUG_REG_BASE + 0x00000550) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000550) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000550) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_0_RMSK 0xffffffff +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_0_ATTR 0x1 +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_0_IN \ + in_dword_masked(HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_0_ADDR, HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_0_RMSK) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_0_INM(m) \ + in_dword_masked(HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_0_ADDR, m) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_0_CMDQ_SRC_LEN_F_BMSK 0xffff0000 +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_0_CMDQ_SRC_LEN_F_SHFT 0x10 +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_0_CMDQ_PACKET_LEN_F_BMSK 0xffff +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_0_CMDQ_PACKET_LEN_F_SHFT 0x0 + +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_1_ADDR (IPA_DEBUG_REG_BASE + 0x00000554) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_1_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000554) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_1_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000554) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_1_RMSK 0xffffffff +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_1_ATTR 0x1 +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_1_IN \ + in_dword_masked(HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_1_ADDR, HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_1_RMSK) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_1_INM(m) \ + in_dword_masked(HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_1_ADDR, m) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_1_CMDQ_METADATA_F_BMSK 0xff000000 +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_1_CMDQ_METADATA_F_SHFT 0x18 +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_1_CMDQ_OPCODE_F_BMSK 0xff0000 +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_1_CMDQ_OPCODE_F_SHFT 0x10 +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_1_CMDQ_FLAGS_F_BMSK 0xfc00 +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_1_CMDQ_FLAGS_F_SHFT 0xa +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_1_CMDQ_ORDER_F_BMSK 0x300 +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_1_CMDQ_ORDER_F_SHFT 0x8 +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_1_CMDQ_SRC_PIPE_F_BMSK 0xff +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_1_CMDQ_SRC_PIPE_F_SHFT 0x0 + +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_2_ADDR (IPA_DEBUG_REG_BASE + 0x00000558) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_2_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000558) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_2_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000558) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_2_RMSK 0xffffffff +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_2_ATTR 0x1 +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_2_IN \ + in_dword_masked(HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_2_ADDR, HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_2_RMSK) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_2_INM(m) \ + in_dword_masked(HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_2_ADDR, m) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_2_CMDQ_ADDR_LSB_F_BMSK 0xffffffff +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_2_CMDQ_ADDR_LSB_F_SHFT 0x0 + +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_3_ADDR (IPA_DEBUG_REG_BASE + 0x0000055c) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_3_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000055c) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_3_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000055c) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_3_RMSK 0xffffffff +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_3_ATTR 0x1 +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_3_IN \ + in_dword_masked(HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_3_ADDR, HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_3_RMSK) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_3_INM(m) \ + in_dword_masked(HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_3_ADDR, m) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_3_CMDQ_ADDR_MSB_F_BMSK 0xffffffff +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_3_CMDQ_ADDR_MSB_F_SHFT 0x0 + +#define HWIO_IPA_UC_RX_HND_CMDQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x00000560) +#define HWIO_IPA_UC_RX_HND_CMDQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000560) +#define HWIO_IPA_UC_RX_HND_CMDQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000560) +#define HWIO_IPA_UC_RX_HND_CMDQ_STATUS_RMSK 0x7ff +#define HWIO_IPA_UC_RX_HND_CMDQ_STATUS_ATTR 0x1 +#define HWIO_IPA_UC_RX_HND_CMDQ_STATUS_IN \ + in_dword_masked(HWIO_IPA_UC_RX_HND_CMDQ_STATUS_ADDR, HWIO_IPA_UC_RX_HND_CMDQ_STATUS_RMSK) +#define HWIO_IPA_UC_RX_HND_CMDQ_STATUS_INM(m) \ + in_dword_masked(HWIO_IPA_UC_RX_HND_CMDQ_STATUS_ADDR, m) +#define HWIO_IPA_UC_RX_HND_CMDQ_STATUS_CMDQ_DEPTH_BMSK 0x780 +#define HWIO_IPA_UC_RX_HND_CMDQ_STATUS_CMDQ_DEPTH_SHFT 0x7 +#define HWIO_IPA_UC_RX_HND_CMDQ_STATUS_CMDQ_COUNT_BMSK 0x78 +#define HWIO_IPA_UC_RX_HND_CMDQ_STATUS_CMDQ_COUNT_SHFT 0x3 +#define HWIO_IPA_UC_RX_HND_CMDQ_STATUS_CMDQ_FULL_BMSK 0x4 +#define HWIO_IPA_UC_RX_HND_CMDQ_STATUS_CMDQ_FULL_SHFT 0x2 +#define HWIO_IPA_UC_RX_HND_CMDQ_STATUS_CMDQ_EMPTY_BMSK 0x2 +#define HWIO_IPA_UC_RX_HND_CMDQ_STATUS_CMDQ_EMPTY_SHFT 0x1 +#define HWIO_IPA_UC_RX_HND_CMDQ_STATUS_STATUS_BMSK 0x1 +#define HWIO_IPA_UC_RX_HND_CMDQ_STATUS_STATUS_SHFT 0x0 + +#define HWIO_IPA_RAM_HW_FIRST_ADDR (IPA_DEBUG_REG_BASE + 0x00000564) +#define HWIO_IPA_RAM_HW_FIRST_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000564) +#define HWIO_IPA_RAM_HW_FIRST_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000564) +#define HWIO_IPA_RAM_HW_FIRST_RMSK 0xffffffff +#define HWIO_IPA_RAM_HW_FIRST_ATTR 0x1 +#define HWIO_IPA_RAM_HW_FIRST_IN \ + in_dword_masked(HWIO_IPA_RAM_HW_FIRST_ADDR, HWIO_IPA_RAM_HW_FIRST_RMSK) +#define HWIO_IPA_RAM_HW_FIRST_INM(m) \ + in_dword_masked(HWIO_IPA_RAM_HW_FIRST_ADDR, m) +#define HWIO_IPA_RAM_HW_FIRST_ADDRESS_BMSK 0xffffffff +#define HWIO_IPA_RAM_HW_FIRST_ADDRESS_SHFT 0x0 + +#define HWIO_IPA_RAM_HW_LAST_ADDR (IPA_DEBUG_REG_BASE + 0x00000568) +#define HWIO_IPA_RAM_HW_LAST_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000568) +#define HWIO_IPA_RAM_HW_LAST_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000568) +#define HWIO_IPA_RAM_HW_LAST_RMSK 0xffffffff +#define HWIO_IPA_RAM_HW_LAST_ATTR 0x1 +#define HWIO_IPA_RAM_HW_LAST_IN \ + in_dword_masked(HWIO_IPA_RAM_HW_LAST_ADDR, HWIO_IPA_RAM_HW_LAST_RMSK) +#define HWIO_IPA_RAM_HW_LAST_INM(m) \ + in_dword_masked(HWIO_IPA_RAM_HW_LAST_ADDR, m) +#define HWIO_IPA_RAM_HW_LAST_ADDRESS_BMSK 0xffffffff +#define HWIO_IPA_RAM_HW_LAST_ADDRESS_SHFT 0x0 + +#define HWIO_IPA_RAM_FRAG_FRST_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE + 0x00000570) +#define HWIO_IPA_RAM_FRAG_FRST_BASE_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000570) +#define HWIO_IPA_RAM_FRAG_FRST_BASE_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000570) +#define HWIO_IPA_RAM_FRAG_FRST_BASE_ADDR_RMSK 0xffffffff +#define HWIO_IPA_RAM_FRAG_FRST_BASE_ADDR_ATTR 0x1 +#define HWIO_IPA_RAM_FRAG_FRST_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_RAM_FRAG_FRST_BASE_ADDR_ADDR, HWIO_IPA_RAM_FRAG_FRST_BASE_ADDR_RMSK) +#define HWIO_IPA_RAM_FRAG_FRST_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_RAM_FRAG_FRST_BASE_ADDR_ADDR, m) +#define HWIO_IPA_RAM_FRAG_FRST_BASE_ADDR_ADDRESS_BMSK 0xffffffff +#define HWIO_IPA_RAM_FRAG_FRST_BASE_ADDR_ADDRESS_SHFT 0x0 + +#define HWIO_IPA_RAM_FRAG_SCND_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE + 0x00000574) +#define HWIO_IPA_RAM_FRAG_SCND_BASE_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000574) +#define HWIO_IPA_RAM_FRAG_SCND_BASE_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000574) +#define HWIO_IPA_RAM_FRAG_SCND_BASE_ADDR_RMSK 0xffffffff +#define HWIO_IPA_RAM_FRAG_SCND_BASE_ADDR_ATTR 0x1 +#define HWIO_IPA_RAM_FRAG_SCND_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_RAM_FRAG_SCND_BASE_ADDR_ADDR, HWIO_IPA_RAM_FRAG_SCND_BASE_ADDR_RMSK) +#define HWIO_IPA_RAM_FRAG_SCND_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_RAM_FRAG_SCND_BASE_ADDR_ADDR, m) +#define HWIO_IPA_RAM_FRAG_SCND_BASE_ADDR_ADDRESS_BMSK 0xffffffff +#define HWIO_IPA_RAM_FRAG_SCND_BASE_ADDR_ADDRESS_SHFT 0x0 + +#define HWIO_IPA_RAM_GSI_TLV_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE + 0x00000578) +#define HWIO_IPA_RAM_GSI_TLV_BASE_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000578) +#define HWIO_IPA_RAM_GSI_TLV_BASE_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000578) +#define HWIO_IPA_RAM_GSI_TLV_BASE_ADDR_RMSK 0xffffffff +#define HWIO_IPA_RAM_GSI_TLV_BASE_ADDR_ATTR 0x1 +#define HWIO_IPA_RAM_GSI_TLV_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_RAM_GSI_TLV_BASE_ADDR_ADDR, HWIO_IPA_RAM_GSI_TLV_BASE_ADDR_RMSK) +#define HWIO_IPA_RAM_GSI_TLV_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_RAM_GSI_TLV_BASE_ADDR_ADDR, m) +#define HWIO_IPA_RAM_GSI_TLV_BASE_ADDR_ADDRESS_BMSK 0xffffffff +#define HWIO_IPA_RAM_GSI_TLV_BASE_ADDR_ADDRESS_SHFT 0x0 + +#define HWIO_IPA_RAM_DCPH_KEYS_FIRST_ADDR (IPA_DEBUG_REG_BASE + 0x0000057c) +#define HWIO_IPA_RAM_DCPH_KEYS_FIRST_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000057c) +#define HWIO_IPA_RAM_DCPH_KEYS_FIRST_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000057c) +#define HWIO_IPA_RAM_DCPH_KEYS_FIRST_RMSK 0xffffffff +#define HWIO_IPA_RAM_DCPH_KEYS_FIRST_ATTR 0x1 +#define HWIO_IPA_RAM_DCPH_KEYS_FIRST_IN \ + in_dword_masked(HWIO_IPA_RAM_DCPH_KEYS_FIRST_ADDR, HWIO_IPA_RAM_DCPH_KEYS_FIRST_RMSK) +#define HWIO_IPA_RAM_DCPH_KEYS_FIRST_INM(m) \ + in_dword_masked(HWIO_IPA_RAM_DCPH_KEYS_FIRST_ADDR, m) +#define HWIO_IPA_RAM_DCPH_KEYS_FIRST_ADDRESS_BMSK 0xffffffff +#define HWIO_IPA_RAM_DCPH_KEYS_FIRST_ADDRESS_SHFT 0x0 + +#define HWIO_IPA_RAM_DCPH_KEYS_LAST_ADDR (IPA_DEBUG_REG_BASE + 0x00000580) +#define HWIO_IPA_RAM_DCPH_KEYS_LAST_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000580) +#define HWIO_IPA_RAM_DCPH_KEYS_LAST_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000580) +#define HWIO_IPA_RAM_DCPH_KEYS_LAST_RMSK 0xffffffff +#define HWIO_IPA_RAM_DCPH_KEYS_LAST_ATTR 0x1 +#define HWIO_IPA_RAM_DCPH_KEYS_LAST_IN \ + in_dword_masked(HWIO_IPA_RAM_DCPH_KEYS_LAST_ADDR, HWIO_IPA_RAM_DCPH_KEYS_LAST_RMSK) +#define HWIO_IPA_RAM_DCPH_KEYS_LAST_INM(m) \ + in_dword_masked(HWIO_IPA_RAM_DCPH_KEYS_LAST_ADDR, m) +#define HWIO_IPA_RAM_DCPH_KEYS_LAST_ADDRESS_BMSK 0xffffffff +#define HWIO_IPA_RAM_DCPH_KEYS_LAST_ADDRESS_SHFT 0x0 + +#define HWIO_IPA_DPS_SEQUENCER_FIRST_ADDR (IPA_DEBUG_REG_BASE + 0x00000584) +#define HWIO_IPA_DPS_SEQUENCER_FIRST_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000584) +#define HWIO_IPA_DPS_SEQUENCER_FIRST_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000584) +#define HWIO_IPA_DPS_SEQUENCER_FIRST_RMSK 0xffffffff +#define HWIO_IPA_DPS_SEQUENCER_FIRST_ATTR 0x1 +#define HWIO_IPA_DPS_SEQUENCER_FIRST_IN \ + in_dword_masked(HWIO_IPA_DPS_SEQUENCER_FIRST_ADDR, HWIO_IPA_DPS_SEQUENCER_FIRST_RMSK) +#define HWIO_IPA_DPS_SEQUENCER_FIRST_INM(m) \ + in_dword_masked(HWIO_IPA_DPS_SEQUENCER_FIRST_ADDR, m) +#define HWIO_IPA_DPS_SEQUENCER_FIRST_ADDRESS_BMSK 0xffffffff +#define HWIO_IPA_DPS_SEQUENCER_FIRST_ADDRESS_SHFT 0x0 + +#define HWIO_IPA_DPS_SEQUENCER_LAST_ADDR (IPA_DEBUG_REG_BASE + 0x00000588) +#define HWIO_IPA_DPS_SEQUENCER_LAST_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000588) +#define HWIO_IPA_DPS_SEQUENCER_LAST_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000588) +#define HWIO_IPA_DPS_SEQUENCER_LAST_RMSK 0xffffffff +#define HWIO_IPA_DPS_SEQUENCER_LAST_ATTR 0x1 +#define HWIO_IPA_DPS_SEQUENCER_LAST_IN \ + in_dword_masked(HWIO_IPA_DPS_SEQUENCER_LAST_ADDR, HWIO_IPA_DPS_SEQUENCER_LAST_RMSK) +#define HWIO_IPA_DPS_SEQUENCER_LAST_INM(m) \ + in_dword_masked(HWIO_IPA_DPS_SEQUENCER_LAST_ADDR, m) +#define HWIO_IPA_DPS_SEQUENCER_LAST_ADDRESS_BMSK 0xffffffff +#define HWIO_IPA_DPS_SEQUENCER_LAST_ADDRESS_SHFT 0x0 + +#define HWIO_IPA_HPS_SEQUENCER_FIRST_ADDR (IPA_DEBUG_REG_BASE + 0x0000058c) +#define HWIO_IPA_HPS_SEQUENCER_FIRST_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000058c) +#define HWIO_IPA_HPS_SEQUENCER_FIRST_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000058c) +#define HWIO_IPA_HPS_SEQUENCER_FIRST_RMSK 0xffffffff +#define HWIO_IPA_HPS_SEQUENCER_FIRST_ATTR 0x1 +#define HWIO_IPA_HPS_SEQUENCER_FIRST_IN \ + in_dword_masked(HWIO_IPA_HPS_SEQUENCER_FIRST_ADDR, HWIO_IPA_HPS_SEQUENCER_FIRST_RMSK) +#define HWIO_IPA_HPS_SEQUENCER_FIRST_INM(m) \ + in_dword_masked(HWIO_IPA_HPS_SEQUENCER_FIRST_ADDR, m) +#define HWIO_IPA_HPS_SEQUENCER_FIRST_ADDRESS_BMSK 0xffffffff +#define HWIO_IPA_HPS_SEQUENCER_FIRST_ADDRESS_SHFT 0x0 + +#define HWIO_IPA_HPS_SEQUENCER_LAST_ADDR (IPA_DEBUG_REG_BASE + 0x00000590) +#define HWIO_IPA_HPS_SEQUENCER_LAST_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000590) +#define HWIO_IPA_HPS_SEQUENCER_LAST_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000590) +#define HWIO_IPA_HPS_SEQUENCER_LAST_RMSK 0xffffffff +#define HWIO_IPA_HPS_SEQUENCER_LAST_ATTR 0x1 +#define HWIO_IPA_HPS_SEQUENCER_LAST_IN \ + in_dword_masked(HWIO_IPA_HPS_SEQUENCER_LAST_ADDR, HWIO_IPA_HPS_SEQUENCER_LAST_RMSK) +#define HWIO_IPA_HPS_SEQUENCER_LAST_INM(m) \ + in_dword_masked(HWIO_IPA_HPS_SEQUENCER_LAST_ADDR, m) +#define HWIO_IPA_HPS_SEQUENCER_LAST_ADDRESS_BMSK 0xffffffff +#define HWIO_IPA_HPS_SEQUENCER_LAST_ADDRESS_SHFT 0x0 + +#define HWIO_IPA_RAM_PKT_CTX_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE + 0x00000594) +#define HWIO_IPA_RAM_PKT_CTX_BASE_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000594) +#define HWIO_IPA_RAM_PKT_CTX_BASE_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000594) +#define HWIO_IPA_RAM_PKT_CTX_BASE_ADDR_RMSK 0xffffffff +#define HWIO_IPA_RAM_PKT_CTX_BASE_ADDR_ATTR 0x1 +#define HWIO_IPA_RAM_PKT_CTX_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_RAM_PKT_CTX_BASE_ADDR_ADDR, HWIO_IPA_RAM_PKT_CTX_BASE_ADDR_RMSK) +#define HWIO_IPA_RAM_PKT_CTX_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_RAM_PKT_CTX_BASE_ADDR_ADDR, m) +#define HWIO_IPA_RAM_PKT_CTX_BASE_ADDR_ADDRESS_BMSK 0xffffffff +#define HWIO_IPA_RAM_PKT_CTX_BASE_ADDR_ADDRESS_SHFT 0x0 + +#define HWIO_IPA_RAM_SW_AREA_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE + 0x00000598) +#define HWIO_IPA_RAM_SW_AREA_BASE_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000598) +#define HWIO_IPA_RAM_SW_AREA_BASE_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000598) +#define HWIO_IPA_RAM_SW_AREA_BASE_ADDR_RMSK 0xffffffff +#define HWIO_IPA_RAM_SW_AREA_BASE_ADDR_ATTR 0x1 +#define HWIO_IPA_RAM_SW_AREA_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_RAM_SW_AREA_BASE_ADDR_ADDR, HWIO_IPA_RAM_SW_AREA_BASE_ADDR_RMSK) +#define HWIO_IPA_RAM_SW_AREA_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_RAM_SW_AREA_BASE_ADDR_ADDR, m) +#define HWIO_IPA_RAM_SW_AREA_BASE_ADDR_ADDRESS_BMSK 0xffffffff +#define HWIO_IPA_RAM_SW_AREA_BASE_ADDR_ADDRESS_SHFT 0x0 + +#define HWIO_IPA_RAM_HDRI_TYPE1_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE + 0x0000059c) +#define HWIO_IPA_RAM_HDRI_TYPE1_BASE_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000059c) +#define HWIO_IPA_RAM_HDRI_TYPE1_BASE_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000059c) +#define HWIO_IPA_RAM_HDRI_TYPE1_BASE_ADDR_RMSK 0xffffffff +#define HWIO_IPA_RAM_HDRI_TYPE1_BASE_ADDR_ATTR 0x1 +#define HWIO_IPA_RAM_HDRI_TYPE1_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_RAM_HDRI_TYPE1_BASE_ADDR_ADDR, HWIO_IPA_RAM_HDRI_TYPE1_BASE_ADDR_RMSK) +#define HWIO_IPA_RAM_HDRI_TYPE1_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_RAM_HDRI_TYPE1_BASE_ADDR_ADDR, m) +#define HWIO_IPA_RAM_HDRI_TYPE1_BASE_ADDR_ADDRESS_BMSK 0xffffffff +#define HWIO_IPA_RAM_HDRI_TYPE1_BASE_ADDR_ADDRESS_SHFT 0x0 + +#define HWIO_IPA_RAM_AGGR_NLO_COUNTERS_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE + 0x000005a0) +#define HWIO_IPA_RAM_AGGR_NLO_COUNTERS_BASE_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000005a0) +#define HWIO_IPA_RAM_AGGR_NLO_COUNTERS_BASE_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000005a0) +#define HWIO_IPA_RAM_AGGR_NLO_COUNTERS_BASE_ADDR_RMSK 0xffffffff +#define HWIO_IPA_RAM_AGGR_NLO_COUNTERS_BASE_ADDR_ATTR 0x1 +#define HWIO_IPA_RAM_AGGR_NLO_COUNTERS_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_RAM_AGGR_NLO_COUNTERS_BASE_ADDR_ADDR, HWIO_IPA_RAM_AGGR_NLO_COUNTERS_BASE_ADDR_RMSK) +#define HWIO_IPA_RAM_AGGR_NLO_COUNTERS_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_RAM_AGGR_NLO_COUNTERS_BASE_ADDR_ADDR, m) +#define HWIO_IPA_RAM_AGGR_NLO_COUNTERS_BASE_ADDR_ADDRESS_BMSK 0xffffffff +#define HWIO_IPA_RAM_AGGR_NLO_COUNTERS_BASE_ADDR_ADDRESS_SHFT 0x0 + +#define HWIO_IPA_RAM_NLO_VP_CACHE_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE + 0x000005a4) +#define HWIO_IPA_RAM_NLO_VP_CACHE_BASE_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000005a4) +#define HWIO_IPA_RAM_NLO_VP_CACHE_BASE_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000005a4) +#define HWIO_IPA_RAM_NLO_VP_CACHE_BASE_ADDR_RMSK 0xffffffff +#define HWIO_IPA_RAM_NLO_VP_CACHE_BASE_ADDR_ATTR 0x1 +#define HWIO_IPA_RAM_NLO_VP_CACHE_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_RAM_NLO_VP_CACHE_BASE_ADDR_ADDR, HWIO_IPA_RAM_NLO_VP_CACHE_BASE_ADDR_RMSK) +#define HWIO_IPA_RAM_NLO_VP_CACHE_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_RAM_NLO_VP_CACHE_BASE_ADDR_ADDR, m) +#define HWIO_IPA_RAM_NLO_VP_CACHE_BASE_ADDR_ADDRESS_BMSK 0xffffffff +#define HWIO_IPA_RAM_NLO_VP_CACHE_BASE_ADDR_ADDRESS_SHFT 0x0 + +#define HWIO_IPA_RAM_COAL_VP_CACHE_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE + 0x000005a8) +#define HWIO_IPA_RAM_COAL_VP_CACHE_BASE_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000005a8) +#define HWIO_IPA_RAM_COAL_VP_CACHE_BASE_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000005a8) +#define HWIO_IPA_RAM_COAL_VP_CACHE_BASE_ADDR_RMSK 0xffffffff +#define HWIO_IPA_RAM_COAL_VP_CACHE_BASE_ADDR_ATTR 0x1 +#define HWIO_IPA_RAM_COAL_VP_CACHE_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_RAM_COAL_VP_CACHE_BASE_ADDR_ADDR, HWIO_IPA_RAM_COAL_VP_CACHE_BASE_ADDR_RMSK) +#define HWIO_IPA_RAM_COAL_VP_CACHE_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_RAM_COAL_VP_CACHE_BASE_ADDR_ADDR, m) +#define HWIO_IPA_RAM_COAL_VP_CACHE_BASE_ADDR_ADDRESS_BMSK 0xffffffff +#define HWIO_IPA_RAM_COAL_VP_CACHE_BASE_ADDR_ADDRESS_SHFT 0x0 + +#define HWIO_IPA_RAM_COAL_VP_FIFO_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE + 0x000005ac) +#define HWIO_IPA_RAM_COAL_VP_FIFO_BASE_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000005ac) +#define HWIO_IPA_RAM_COAL_VP_FIFO_BASE_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000005ac) +#define HWIO_IPA_RAM_COAL_VP_FIFO_BASE_ADDR_RMSK 0xffffffff +#define HWIO_IPA_RAM_COAL_VP_FIFO_BASE_ADDR_ATTR 0x1 +#define HWIO_IPA_RAM_COAL_VP_FIFO_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_RAM_COAL_VP_FIFO_BASE_ADDR_ADDR, HWIO_IPA_RAM_COAL_VP_FIFO_BASE_ADDR_RMSK) +#define HWIO_IPA_RAM_COAL_VP_FIFO_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_RAM_COAL_VP_FIFO_BASE_ADDR_ADDR, m) +#define HWIO_IPA_RAM_COAL_VP_FIFO_BASE_ADDR_ADDRESS_BMSK 0xffffffff +#define HWIO_IPA_RAM_COAL_VP_FIFO_BASE_ADDR_ADDRESS_SHFT 0x0 + +#define HWIO_IPA_RAM_AGGR_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE + 0x000005b4) +#define HWIO_IPA_RAM_AGGR_BASE_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000005b4) +#define HWIO_IPA_RAM_AGGR_BASE_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000005b4) +#define HWIO_IPA_RAM_AGGR_BASE_ADDR_RMSK 0xffffffff +#define HWIO_IPA_RAM_AGGR_BASE_ADDR_ATTR 0x1 +#define HWIO_IPA_RAM_AGGR_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_RAM_AGGR_BASE_ADDR_ADDR, HWIO_IPA_RAM_AGGR_BASE_ADDR_RMSK) +#define HWIO_IPA_RAM_AGGR_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_RAM_AGGR_BASE_ADDR_ADDR, m) +#define HWIO_IPA_RAM_AGGR_BASE_ADDR_ADDRESS_BMSK 0xffffffff +#define HWIO_IPA_RAM_AGGR_BASE_ADDR_ADDRESS_SHFT 0x0 + +#define HWIO_IPA_RAM_TX_COUNTERS_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE + 0x000005b8) +#define HWIO_IPA_RAM_TX_COUNTERS_BASE_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000005b8) +#define HWIO_IPA_RAM_TX_COUNTERS_BASE_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000005b8) +#define HWIO_IPA_RAM_TX_COUNTERS_BASE_ADDR_RMSK 0xffffffff +#define HWIO_IPA_RAM_TX_COUNTERS_BASE_ADDR_ATTR 0x1 +#define HWIO_IPA_RAM_TX_COUNTERS_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_RAM_TX_COUNTERS_BASE_ADDR_ADDR, HWIO_IPA_RAM_TX_COUNTERS_BASE_ADDR_RMSK) +#define HWIO_IPA_RAM_TX_COUNTERS_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_RAM_TX_COUNTERS_BASE_ADDR_ADDR, m) +#define HWIO_IPA_RAM_TX_COUNTERS_BASE_ADDR_ADDRESS_BMSK 0xffffffff +#define HWIO_IPA_RAM_TX_COUNTERS_BASE_ADDR_ADDRESS_SHFT 0x0 + +#define HWIO_IPA_RAM_DPL_FIFO_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE + 0x000005bc) +#define HWIO_IPA_RAM_DPL_FIFO_BASE_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000005bc) +#define HWIO_IPA_RAM_DPL_FIFO_BASE_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000005bc) +#define HWIO_IPA_RAM_DPL_FIFO_BASE_ADDR_RMSK 0xffffffff +#define HWIO_IPA_RAM_DPL_FIFO_BASE_ADDR_ATTR 0x1 +#define HWIO_IPA_RAM_DPL_FIFO_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_RAM_DPL_FIFO_BASE_ADDR_ADDR, HWIO_IPA_RAM_DPL_FIFO_BASE_ADDR_RMSK) +#define HWIO_IPA_RAM_DPL_FIFO_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_RAM_DPL_FIFO_BASE_ADDR_ADDR, m) +#define HWIO_IPA_RAM_DPL_FIFO_BASE_ADDR_ADDRESS_BMSK 0xffffffff +#define HWIO_IPA_RAM_DPL_FIFO_BASE_ADDR_ADDRESS_SHFT 0x0 + +#define HWIO_IPA_RAM_COAL_MASTER_VP_CTX_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE + 0x000005c0) +#define HWIO_IPA_RAM_COAL_MASTER_VP_CTX_BASE_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000005c0) +#define HWIO_IPA_RAM_COAL_MASTER_VP_CTX_BASE_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000005c0) +#define HWIO_IPA_RAM_COAL_MASTER_VP_CTX_BASE_ADDR_RMSK 0xffffffff +#define HWIO_IPA_RAM_COAL_MASTER_VP_CTX_BASE_ADDR_ATTR 0x1 +#define HWIO_IPA_RAM_COAL_MASTER_VP_CTX_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_RAM_COAL_MASTER_VP_CTX_BASE_ADDR_ADDR, HWIO_IPA_RAM_COAL_MASTER_VP_CTX_BASE_ADDR_RMSK) +#define HWIO_IPA_RAM_COAL_MASTER_VP_CTX_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_RAM_COAL_MASTER_VP_CTX_BASE_ADDR_ADDR, m) +#define HWIO_IPA_RAM_COAL_MASTER_VP_CTX_BASE_ADDR_ADDRESS_BMSK 0xffffffff +#define HWIO_IPA_RAM_COAL_MASTER_VP_CTX_BASE_ADDR_ADDRESS_SHFT 0x0 + +#define HWIO_IPA_RAM_COAL_MASTER_VP_AGGR_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE + 0x000005c4) +#define HWIO_IPA_RAM_COAL_MASTER_VP_AGGR_BASE_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000005c4) +#define HWIO_IPA_RAM_COAL_MASTER_VP_AGGR_BASE_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000005c4) +#define HWIO_IPA_RAM_COAL_MASTER_VP_AGGR_BASE_ADDR_RMSK 0xffffffff +#define HWIO_IPA_RAM_COAL_MASTER_VP_AGGR_BASE_ADDR_ATTR 0x1 +#define HWIO_IPA_RAM_COAL_MASTER_VP_AGGR_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_RAM_COAL_MASTER_VP_AGGR_BASE_ADDR_ADDR, HWIO_IPA_RAM_COAL_MASTER_VP_AGGR_BASE_ADDR_RMSK) +#define HWIO_IPA_RAM_COAL_MASTER_VP_AGGR_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_RAM_COAL_MASTER_VP_AGGR_BASE_ADDR_ADDR, m) +#define HWIO_IPA_RAM_COAL_MASTER_VP_AGGR_BASE_ADDR_ADDRESS_BMSK 0xffffffff +#define HWIO_IPA_RAM_COAL_MASTER_VP_AGGR_BASE_ADDR_ADDRESS_SHFT 0x0 + +#define HWIO_IPA_RAM_COAL_SLAVE_VP_CTX_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE + 0x000005c8) +#define HWIO_IPA_RAM_COAL_SLAVE_VP_CTX_BASE_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000005c8) +#define HWIO_IPA_RAM_COAL_SLAVE_VP_CTX_BASE_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000005c8) +#define HWIO_IPA_RAM_COAL_SLAVE_VP_CTX_BASE_ADDR_RMSK 0xffffffff +#define HWIO_IPA_RAM_COAL_SLAVE_VP_CTX_BASE_ADDR_ATTR 0x1 +#define HWIO_IPA_RAM_COAL_SLAVE_VP_CTX_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_RAM_COAL_SLAVE_VP_CTX_BASE_ADDR_ADDR, HWIO_IPA_RAM_COAL_SLAVE_VP_CTX_BASE_ADDR_RMSK) +#define HWIO_IPA_RAM_COAL_SLAVE_VP_CTX_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_RAM_COAL_SLAVE_VP_CTX_BASE_ADDR_ADDR, m) +#define HWIO_IPA_RAM_COAL_SLAVE_VP_CTX_BASE_ADDR_ADDRESS_BMSK 0xffffffff +#define HWIO_IPA_RAM_COAL_SLAVE_VP_CTX_BASE_ADDR_ADDRESS_SHFT 0x0 + +#define HWIO_IPA_RAM_UL_NLO_AGGR_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE + 0x000005cc) +#define HWIO_IPA_RAM_UL_NLO_AGGR_BASE_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000005cc) +#define HWIO_IPA_RAM_UL_NLO_AGGR_BASE_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000005cc) +#define HWIO_IPA_RAM_UL_NLO_AGGR_BASE_ADDR_RMSK 0xffffffff +#define HWIO_IPA_RAM_UL_NLO_AGGR_BASE_ADDR_ATTR 0x1 +#define HWIO_IPA_RAM_UL_NLO_AGGR_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_RAM_UL_NLO_AGGR_BASE_ADDR_ADDR, HWIO_IPA_RAM_UL_NLO_AGGR_BASE_ADDR_RMSK) +#define HWIO_IPA_RAM_UL_NLO_AGGR_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_RAM_UL_NLO_AGGR_BASE_ADDR_ADDR, m) +#define HWIO_IPA_RAM_UL_NLO_AGGR_BASE_ADDR_ADDRESS_BMSK 0xffffffff +#define HWIO_IPA_RAM_UL_NLO_AGGR_BASE_ADDR_ADDRESS_SHFT 0x0 + +#define HWIO_IPA_RAM_UC_IRAM_ADDR_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE + 0x000005d0) +#define HWIO_IPA_RAM_UC_IRAM_ADDR_BASE_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000005d0) +#define HWIO_IPA_RAM_UC_IRAM_ADDR_BASE_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000005d0) +#define HWIO_IPA_RAM_UC_IRAM_ADDR_BASE_ADDR_RMSK 0xffffffff +#define HWIO_IPA_RAM_UC_IRAM_ADDR_BASE_ADDR_ATTR 0x1 +#define HWIO_IPA_RAM_UC_IRAM_ADDR_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_RAM_UC_IRAM_ADDR_BASE_ADDR_ADDR, HWIO_IPA_RAM_UC_IRAM_ADDR_BASE_ADDR_RMSK) +#define HWIO_IPA_RAM_UC_IRAM_ADDR_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_RAM_UC_IRAM_ADDR_BASE_ADDR_ADDR, m) +#define HWIO_IPA_RAM_UC_IRAM_ADDR_BASE_ADDR_ADDRESS_BMSK 0xffffffff +#define HWIO_IPA_RAM_UC_IRAM_ADDR_BASE_ADDR_ADDRESS_SHFT 0x0 + +#define HWIO_IPA_RAM_SNIFFER_HW_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE + 0x000005d4) +#define HWIO_IPA_RAM_SNIFFER_HW_BASE_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000005d4) +#define HWIO_IPA_RAM_SNIFFER_HW_BASE_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000005d4) +#define HWIO_IPA_RAM_SNIFFER_HW_BASE_ADDR_RMSK 0xffffffff +#define HWIO_IPA_RAM_SNIFFER_HW_BASE_ADDR_ATTR 0x1 +#define HWIO_IPA_RAM_SNIFFER_HW_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_RAM_SNIFFER_HW_BASE_ADDR_ADDR, HWIO_IPA_RAM_SNIFFER_HW_BASE_ADDR_RMSK) +#define HWIO_IPA_RAM_SNIFFER_HW_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_RAM_SNIFFER_HW_BASE_ADDR_ADDR, m) +#define HWIO_IPA_RAM_SNIFFER_HW_BASE_ADDR_ADDRESS_BMSK 0xffffffff +#define HWIO_IPA_RAM_SNIFFER_HW_BASE_ADDR_ADDRESS_SHFT 0x0 + +#define HWIO_IPA_RAM_FILTER_ROUTER_CACHE_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE + 0x000005d8) +#define HWIO_IPA_RAM_FILTER_ROUTER_CACHE_BASE_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000005d8) +#define HWIO_IPA_RAM_FILTER_ROUTER_CACHE_BASE_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000005d8) +#define HWIO_IPA_RAM_FILTER_ROUTER_CACHE_BASE_ADDR_RMSK 0xffffffff +#define HWIO_IPA_RAM_FILTER_ROUTER_CACHE_BASE_ADDR_ATTR 0x1 +#define HWIO_IPA_RAM_FILTER_ROUTER_CACHE_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_RAM_FILTER_ROUTER_CACHE_BASE_ADDR_ADDR, HWIO_IPA_RAM_FILTER_ROUTER_CACHE_BASE_ADDR_RMSK) +#define HWIO_IPA_RAM_FILTER_ROUTER_CACHE_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_RAM_FILTER_ROUTER_CACHE_BASE_ADDR_ADDR, m) +#define HWIO_IPA_RAM_FILTER_ROUTER_CACHE_BASE_ADDR_ADDRESS_BMSK 0xffffffff +#define HWIO_IPA_RAM_FILTER_ROUTER_CACHE_BASE_ADDR_ADDRESS_SHFT 0x0 + +#define HWIO_IPA_SPARE_REG_1_ADDR (IPA_DEBUG_REG_BASE + 0x000005dc) +#define HWIO_IPA_SPARE_REG_1_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000005dc) +#define HWIO_IPA_SPARE_REG_1_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000005dc) +#define HWIO_IPA_SPARE_REG_1_RMSK 0xffff +#define HWIO_IPA_SPARE_REG_1_ATTR 0x3 +#define HWIO_IPA_SPARE_REG_1_IN \ + in_dword_masked(HWIO_IPA_SPARE_REG_1_ADDR, HWIO_IPA_SPARE_REG_1_RMSK) +#define HWIO_IPA_SPARE_REG_1_INM(m) \ + in_dword_masked(HWIO_IPA_SPARE_REG_1_ADDR, m) +#define HWIO_IPA_SPARE_REG_1_OUT(v) \ + out_dword(HWIO_IPA_SPARE_REG_1_ADDR,v) +#define HWIO_IPA_SPARE_REG_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_SPARE_REG_1_ADDR,m,v,HWIO_IPA_SPARE_REG_1_IN) +#define HWIO_IPA_SPARE_REG_1_SPARE_BITS_BMSK 0xffff +#define HWIO_IPA_SPARE_REG_1_SPARE_BITS_SHFT 0x0 + +#define HWIO_IPA_HPS_UC2SEQ_PUSH_ADDR (IPA_DEBUG_REG_BASE + 0x000005e0) +#define HWIO_IPA_HPS_UC2SEQ_PUSH_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000005e0) +#define HWIO_IPA_HPS_UC2SEQ_PUSH_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000005e0) +#define HWIO_IPA_HPS_UC2SEQ_PUSH_RMSK 0xc03fffff +#define HWIO_IPA_HPS_UC2SEQ_PUSH_ATTR 0x2 +#define HWIO_IPA_HPS_UC2SEQ_PUSH_OUT(v) \ + out_dword(HWIO_IPA_HPS_UC2SEQ_PUSH_ADDR,v) +#define HWIO_IPA_HPS_UC2SEQ_PUSH_TYPE_BMSK 0x80000000 +#define HWIO_IPA_HPS_UC2SEQ_PUSH_TYPE_SHFT 0x1f +#define HWIO_IPA_HPS_UC2SEQ_PUSH_VIRT_OPCODE_BMSK 0x40000000 +#define HWIO_IPA_HPS_UC2SEQ_PUSH_VIRT_OPCODE_SHFT 0x1e +#define HWIO_IPA_HPS_UC2SEQ_PUSH_CTX_ID_BMSK 0x3c0000 +#define HWIO_IPA_HPS_UC2SEQ_PUSH_CTX_ID_SHFT 0x12 +#define HWIO_IPA_HPS_UC2SEQ_PUSH_SRC_ID_BMSK 0x3fc00 +#define HWIO_IPA_HPS_UC2SEQ_PUSH_SRC_ID_SHFT 0xa +#define HWIO_IPA_HPS_UC2SEQ_PUSH_SRC_FLAGS_BMSK 0x300 +#define HWIO_IPA_HPS_UC2SEQ_PUSH_SRC_FLAGS_SHFT 0x8 +#define HWIO_IPA_HPS_UC2SEQ_PUSH_SRC_PIPE_BMSK 0xff +#define HWIO_IPA_HPS_UC2SEQ_PUSH_SRC_PIPE_SHFT 0x0 + +#define HWIO_IPA_HPS_UC2SEQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x000005e4) +#define HWIO_IPA_HPS_UC2SEQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000005e4) +#define HWIO_IPA_HPS_UC2SEQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000005e4) +#define HWIO_IPA_HPS_UC2SEQ_STATUS_RMSK 0xf +#define HWIO_IPA_HPS_UC2SEQ_STATUS_ATTR 0x1 +#define HWIO_IPA_HPS_UC2SEQ_STATUS_IN \ + in_dword_masked(HWIO_IPA_HPS_UC2SEQ_STATUS_ADDR, HWIO_IPA_HPS_UC2SEQ_STATUS_RMSK) +#define HWIO_IPA_HPS_UC2SEQ_STATUS_INM(m) \ + in_dword_masked(HWIO_IPA_HPS_UC2SEQ_STATUS_ADDR, m) +#define HWIO_IPA_HPS_UC2SEQ_STATUS_FILL_LEVEL_BMSK 0xf +#define HWIO_IPA_HPS_UC2SEQ_STATUS_FILL_LEVEL_SHFT 0x0 + +#define HWIO_IPA_HPS_SEQ2UC_RD_ADDR (IPA_DEBUG_REG_BASE + 0x000005e8) +#define HWIO_IPA_HPS_SEQ2UC_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000005e8) +#define HWIO_IPA_HPS_SEQ2UC_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000005e8) +#define HWIO_IPA_HPS_SEQ2UC_RD_RMSK 0x803fffff +#define HWIO_IPA_HPS_SEQ2UC_RD_ATTR 0x1 +#define HWIO_IPA_HPS_SEQ2UC_RD_IN \ + in_dword_masked(HWIO_IPA_HPS_SEQ2UC_RD_ADDR, HWIO_IPA_HPS_SEQ2UC_RD_RMSK) +#define HWIO_IPA_HPS_SEQ2UC_RD_INM(m) \ + in_dword_masked(HWIO_IPA_HPS_SEQ2UC_RD_ADDR, m) +#define HWIO_IPA_HPS_SEQ2UC_RD_TYPE_BMSK 0x80000000 +#define HWIO_IPA_HPS_SEQ2UC_RD_TYPE_SHFT 0x1f +#define HWIO_IPA_HPS_SEQ2UC_RD_CTX_ID_BMSK 0x3c0000 +#define HWIO_IPA_HPS_SEQ2UC_RD_CTX_ID_SHFT 0x12 +#define HWIO_IPA_HPS_SEQ2UC_RD_SRC_ID_BMSK 0x3fc00 +#define HWIO_IPA_HPS_SEQ2UC_RD_SRC_ID_SHFT 0xa +#define HWIO_IPA_HPS_SEQ2UC_RD_SRC_FLAGS_BMSK 0x300 +#define HWIO_IPA_HPS_SEQ2UC_RD_SRC_FLAGS_SHFT 0x8 +#define HWIO_IPA_HPS_SEQ2UC_RD_SRC_PIPE_BMSK 0xff +#define HWIO_IPA_HPS_SEQ2UC_RD_SRC_PIPE_SHFT 0x0 + +#define HWIO_IPA_HPS_SEQ2UC_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x000005ec) +#define HWIO_IPA_HPS_SEQ2UC_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000005ec) +#define HWIO_IPA_HPS_SEQ2UC_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000005ec) +#define HWIO_IPA_HPS_SEQ2UC_STATUS_RMSK 0xf +#define HWIO_IPA_HPS_SEQ2UC_STATUS_ATTR 0x1 +#define HWIO_IPA_HPS_SEQ2UC_STATUS_IN \ + in_dword_masked(HWIO_IPA_HPS_SEQ2UC_STATUS_ADDR, HWIO_IPA_HPS_SEQ2UC_STATUS_RMSK) +#define HWIO_IPA_HPS_SEQ2UC_STATUS_INM(m) \ + in_dword_masked(HWIO_IPA_HPS_SEQ2UC_STATUS_ADDR, m) +#define HWIO_IPA_HPS_SEQ2UC_STATUS_FILL_LEVEL_BMSK 0xf +#define HWIO_IPA_HPS_SEQ2UC_STATUS_FILL_LEVEL_SHFT 0x0 + +#define HWIO_IPA_HPS_SEQ2UC_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x000005f0) +#define HWIO_IPA_HPS_SEQ2UC_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000005f0) +#define HWIO_IPA_HPS_SEQ2UC_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000005f0) +#define HWIO_IPA_HPS_SEQ2UC_CMD_RMSK 0x1 +#define HWIO_IPA_HPS_SEQ2UC_CMD_ATTR 0x2 +#define HWIO_IPA_HPS_SEQ2UC_CMD_OUT(v) \ + out_dword(HWIO_IPA_HPS_SEQ2UC_CMD_ADDR,v) +#define HWIO_IPA_HPS_SEQ2UC_CMD_POP_BMSK 0x1 +#define HWIO_IPA_HPS_SEQ2UC_CMD_POP_SHFT 0x0 + +#define HWIO_IPA_DPS_UC2SEQ_PUSH_ADDR (IPA_DEBUG_REG_BASE + 0x000005f4) +#define HWIO_IPA_DPS_UC2SEQ_PUSH_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000005f4) +#define HWIO_IPA_DPS_UC2SEQ_PUSH_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000005f4) +#define HWIO_IPA_DPS_UC2SEQ_PUSH_RMSK 0xbfffffff +#define HWIO_IPA_DPS_UC2SEQ_PUSH_ATTR 0x2 +#define HWIO_IPA_DPS_UC2SEQ_PUSH_OUT(v) \ + out_dword(HWIO_IPA_DPS_UC2SEQ_PUSH_ADDR,v) +#define HWIO_IPA_DPS_UC2SEQ_PUSH_TYPE_BMSK 0x80000000 +#define HWIO_IPA_DPS_UC2SEQ_PUSH_TYPE_SHFT 0x1f +#define HWIO_IPA_DPS_UC2SEQ_PUSH_DEST_PIPE_BMSK 0x3fc00000 +#define HWIO_IPA_DPS_UC2SEQ_PUSH_DEST_PIPE_SHFT 0x16 +#define HWIO_IPA_DPS_UC2SEQ_PUSH_CTX_ID_BMSK 0x3c0000 +#define HWIO_IPA_DPS_UC2SEQ_PUSH_CTX_ID_SHFT 0x12 +#define HWIO_IPA_DPS_UC2SEQ_PUSH_SRC_ID_BMSK 0x3fc00 +#define HWIO_IPA_DPS_UC2SEQ_PUSH_SRC_ID_SHFT 0xa +#define HWIO_IPA_DPS_UC2SEQ_PUSH_SRC_FLAGS_BMSK 0x300 +#define HWIO_IPA_DPS_UC2SEQ_PUSH_SRC_FLAGS_SHFT 0x8 +#define HWIO_IPA_DPS_UC2SEQ_PUSH_SRC_PIPE_BMSK 0xff +#define HWIO_IPA_DPS_UC2SEQ_PUSH_SRC_PIPE_SHFT 0x0 + +#define HWIO_IPA_DPS_UC2SEQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x000005f8) +#define HWIO_IPA_DPS_UC2SEQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000005f8) +#define HWIO_IPA_DPS_UC2SEQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000005f8) +#define HWIO_IPA_DPS_UC2SEQ_STATUS_RMSK 0xf +#define HWIO_IPA_DPS_UC2SEQ_STATUS_ATTR 0x1 +#define HWIO_IPA_DPS_UC2SEQ_STATUS_IN \ + in_dword_masked(HWIO_IPA_DPS_UC2SEQ_STATUS_ADDR, HWIO_IPA_DPS_UC2SEQ_STATUS_RMSK) +#define HWIO_IPA_DPS_UC2SEQ_STATUS_INM(m) \ + in_dword_masked(HWIO_IPA_DPS_UC2SEQ_STATUS_ADDR, m) +#define HWIO_IPA_DPS_UC2SEQ_STATUS_FILL_LEVEL_BMSK 0xf +#define HWIO_IPA_DPS_UC2SEQ_STATUS_FILL_LEVEL_SHFT 0x0 + +#define HWIO_IPA_DPS_SEQ2UC_RD_ADDR (IPA_DEBUG_REG_BASE + 0x000005fc) +#define HWIO_IPA_DPS_SEQ2UC_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000005fc) +#define HWIO_IPA_DPS_SEQ2UC_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000005fc) +#define HWIO_IPA_DPS_SEQ2UC_RD_RMSK 0xbfffffff +#define HWIO_IPA_DPS_SEQ2UC_RD_ATTR 0x1 +#define HWIO_IPA_DPS_SEQ2UC_RD_IN \ + in_dword_masked(HWIO_IPA_DPS_SEQ2UC_RD_ADDR, HWIO_IPA_DPS_SEQ2UC_RD_RMSK) +#define HWIO_IPA_DPS_SEQ2UC_RD_INM(m) \ + in_dword_masked(HWIO_IPA_DPS_SEQ2UC_RD_ADDR, m) +#define HWIO_IPA_DPS_SEQ2UC_RD_TYPE_BMSK 0x80000000 +#define HWIO_IPA_DPS_SEQ2UC_RD_TYPE_SHFT 0x1f +#define HWIO_IPA_DPS_SEQ2UC_RD_DEST_PIPE_BMSK 0x3fc00000 +#define HWIO_IPA_DPS_SEQ2UC_RD_DEST_PIPE_SHFT 0x16 +#define HWIO_IPA_DPS_SEQ2UC_RD_CTX_ID_BMSK 0x3c0000 +#define HWIO_IPA_DPS_SEQ2UC_RD_CTX_ID_SHFT 0x12 +#define HWIO_IPA_DPS_SEQ2UC_RD_SRC_ID_BMSK 0x3fc00 +#define HWIO_IPA_DPS_SEQ2UC_RD_SRC_ID_SHFT 0xa +#define HWIO_IPA_DPS_SEQ2UC_RD_SRC_FLAGS_BMSK 0x300 +#define HWIO_IPA_DPS_SEQ2UC_RD_SRC_FLAGS_SHFT 0x8 +#define HWIO_IPA_DPS_SEQ2UC_RD_SRC_PIPE_BMSK 0xff +#define HWIO_IPA_DPS_SEQ2UC_RD_SRC_PIPE_SHFT 0x0 + +#define HWIO_IPA_DPS_SEQ2UC_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x00000600) +#define HWIO_IPA_DPS_SEQ2UC_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000600) +#define HWIO_IPA_DPS_SEQ2UC_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000600) +#define HWIO_IPA_DPS_SEQ2UC_STATUS_RMSK 0xf +#define HWIO_IPA_DPS_SEQ2UC_STATUS_ATTR 0x1 +#define HWIO_IPA_DPS_SEQ2UC_STATUS_IN \ + in_dword_masked(HWIO_IPA_DPS_SEQ2UC_STATUS_ADDR, HWIO_IPA_DPS_SEQ2UC_STATUS_RMSK) +#define HWIO_IPA_DPS_SEQ2UC_STATUS_INM(m) \ + in_dword_masked(HWIO_IPA_DPS_SEQ2UC_STATUS_ADDR, m) +#define HWIO_IPA_DPS_SEQ2UC_STATUS_FILL_LEVEL_BMSK 0xf +#define HWIO_IPA_DPS_SEQ2UC_STATUS_FILL_LEVEL_SHFT 0x0 + +#define HWIO_IPA_DPS_SEQ2UC_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x00000604) +#define HWIO_IPA_DPS_SEQ2UC_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000604) +#define HWIO_IPA_DPS_SEQ2UC_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000604) +#define HWIO_IPA_DPS_SEQ2UC_CMD_RMSK 0x1 +#define HWIO_IPA_DPS_SEQ2UC_CMD_ATTR 0x2 +#define HWIO_IPA_DPS_SEQ2UC_CMD_OUT(v) \ + out_dword(HWIO_IPA_DPS_SEQ2UC_CMD_ADDR,v) +#define HWIO_IPA_DPS_SEQ2UC_CMD_POP_BMSK 0x1 +#define HWIO_IPA_DPS_SEQ2UC_CMD_POP_SHFT 0x0 + +#define HWIO_IPA_NTF_TX_CMDQ_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x00000608) +#define HWIO_IPA_NTF_TX_CMDQ_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000608) +#define HWIO_IPA_NTF_TX_CMDQ_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000608) +#define HWIO_IPA_NTF_TX_CMDQ_CMD_RMSK 0xff7 +#define HWIO_IPA_NTF_TX_CMDQ_CMD_ATTR 0x3 +#define HWIO_IPA_NTF_TX_CMDQ_CMD_IN \ + in_dword_masked(HWIO_IPA_NTF_TX_CMDQ_CMD_ADDR, HWIO_IPA_NTF_TX_CMDQ_CMD_RMSK) +#define HWIO_IPA_NTF_TX_CMDQ_CMD_INM(m) \ + in_dword_masked(HWIO_IPA_NTF_TX_CMDQ_CMD_ADDR, m) +#define HWIO_IPA_NTF_TX_CMDQ_CMD_OUT(v) \ + out_dword(HWIO_IPA_NTF_TX_CMDQ_CMD_ADDR,v) +#define HWIO_IPA_NTF_TX_CMDQ_CMD_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_NTF_TX_CMDQ_CMD_ADDR,m,v,HWIO_IPA_NTF_TX_CMDQ_CMD_IN) +#define HWIO_IPA_NTF_TX_CMDQ_CMD_CMD_CLIENT_BMSK 0xff0 +#define HWIO_IPA_NTF_TX_CMDQ_CMD_CMD_CLIENT_SHFT 0x4 +#define HWIO_IPA_NTF_TX_CMDQ_CMD_RD_REQ_BMSK 0x4 +#define HWIO_IPA_NTF_TX_CMDQ_CMD_RD_REQ_SHFT 0x2 +#define HWIO_IPA_NTF_TX_CMDQ_CMD_POP_CMD_BMSK 0x2 +#define HWIO_IPA_NTF_TX_CMDQ_CMD_POP_CMD_SHFT 0x1 +#define HWIO_IPA_NTF_TX_CMDQ_CMD_WRITE_CMD_BMSK 0x1 +#define HWIO_IPA_NTF_TX_CMDQ_CMD_WRITE_CMD_SHFT 0x0 + +#define HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_ADDR (IPA_DEBUG_REG_BASE + 0x0000060c) +#define HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000060c) +#define HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000060c) +#define HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_RMSK 0x7ffffff +#define HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_ATTR 0x3 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_IN \ + in_dword_masked(HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_ADDR, HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_RMSK) +#define HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_INM(m) \ + in_dword_masked(HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_ADDR, m) +#define HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_OUT(v) \ + out_dword(HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_ADDR,v) +#define HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_ADDR,m,v,HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_IN) +#define HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_SEG_CTX_ID_F_BMSK 0x6000000 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_SEG_CTX_ID_F_SHFT 0x19 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_SEG_VALID_F_BMSK 0x1000000 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_SEG_VALID_F_SHFT 0x18 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_CMDQ_VIRT_COD_F_BMSK 0x800000 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_CMDQ_VIRT_COD_F_SHFT 0x17 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_CMDQ_TYPE_F_BMSK 0x400000 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_CMDQ_TYPE_F_SHFT 0x16 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_CMDQ_OPCODE_F_BMSK 0x300000 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_CMDQ_OPCODE_F_SHFT 0x14 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_CMDQ_SRC_PIPE_F_BMSK 0xff000 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_CMDQ_SRC_PIPE_F_SHFT 0xc +#define HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_CMDQ_SRC_ID_F_BMSK 0xff0 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_CMDQ_SRC_ID_F_SHFT 0x4 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_CMDQ_CTX_ID_F_BMSK 0xf +#define HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_CMDQ_CTX_ID_F_SHFT 0x0 + +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_ADDR (IPA_DEBUG_REG_BASE + 0x00000610) +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000610) +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000610) +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_RMSK 0x7ffffff +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_ATTR 0x1 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_IN \ + in_dword_masked(HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_ADDR, HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_RMSK, HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_ATTR) +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_INM(m) \ + in_dword_masked(HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_ADDR, m, HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_ATTR) +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_SEG_CTX_ID_F_BMSK 0x6000000 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_SEG_CTX_ID_F_SHFT 0x19 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_SEG_VALID_F_BMSK 0x1000000 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_SEG_VALID_F_SHFT 0x18 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_CMDQ_VIRT_COD_F_BMSK 0x800000 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_CMDQ_VIRT_COD_F_SHFT 0x17 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_CMDQ_TYPE_F_BMSK 0x400000 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_CMDQ_TYPE_F_SHFT 0x16 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_CMDQ_OPCODE_F_BMSK 0x300000 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_CMDQ_OPCODE_F_SHFT 0x14 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_CMDQ_SRC_PIPE_F_BMSK 0xff000 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_CMDQ_SRC_PIPE_F_SHFT 0xc +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_CMDQ_SRC_ID_F_BMSK 0xff0 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_CMDQ_SRC_ID_F_SHFT 0x4 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_CMDQ_CTX_ID_F_BMSK 0xf +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_CMDQ_CTX_ID_F_SHFT 0x0 + +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x00000614) +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000614) +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000614) +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_RMSK 0x1ff +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_ATTR 0x1 +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_IN \ + in_dword_masked(HWIO_IPA_NTF_TX_CMDQ_STATUS_ADDR, HWIO_IPA_NTF_TX_CMDQ_STATUS_RMSK, HWIO_IPA_NTF_TX_CMDQ_STATUS_ATTR) +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_INM(m) \ + in_dword_masked(HWIO_IPA_NTF_TX_CMDQ_STATUS_ADDR, m, HWIO_IPA_NTF_TX_CMDQ_STATUS_ATTR) +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_CMDQ_DEPTH_BMSK 0x1fc +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_CMDQ_DEPTH_SHFT 0x2 +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_CMDQ_FULL_BMSK 0x2 +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_CMDQ_FULL_SHFT 0x1 +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_STATUS_BMSK 0x1 +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_STATUS_SHFT 0x0 + +#define HWIO_IPA_NTF_TX_SNP_ADDR (IPA_DEBUG_REG_BASE + 0x0000061c) +#define HWIO_IPA_NTF_TX_SNP_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000061c) +#define HWIO_IPA_NTF_TX_SNP_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000061c) +#define HWIO_IPA_NTF_TX_SNP_RMSK 0xfffffff +#define HWIO_IPA_NTF_TX_SNP_ATTR 0x3 +#define HWIO_IPA_NTF_TX_SNP_IN \ + in_dword_masked(HWIO_IPA_NTF_TX_SNP_ADDR, HWIO_IPA_NTF_TX_SNP_RMSK) +#define HWIO_IPA_NTF_TX_SNP_INM(m) \ + in_dword_masked(HWIO_IPA_NTF_TX_SNP_ADDR, m) +#define HWIO_IPA_NTF_TX_SNP_OUT(v) \ + out_dword(HWIO_IPA_NTF_TX_SNP_ADDR,v) +#define HWIO_IPA_NTF_TX_SNP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_NTF_TX_SNP_ADDR,m,v,HWIO_IPA_NTF_TX_SNP_IN) +#define HWIO_IPA_NTF_TX_SNP_SNP_ADDR_BMSK 0xff00000 +#define HWIO_IPA_NTF_TX_SNP_SNP_ADDR_SHFT 0x14 +#define HWIO_IPA_NTF_TX_SNP_SNP_HEAD_BMSK 0xff000 +#define HWIO_IPA_NTF_TX_SNP_SNP_HEAD_SHFT 0xc +#define HWIO_IPA_NTF_TX_SNP_SNP_NEXT_BMSK 0xff0 +#define HWIO_IPA_NTF_TX_SNP_SNP_NEXT_SHFT 0x4 +#define HWIO_IPA_NTF_TX_SNP_SNP_NEXT_IS_VALID_BMSK 0x8 +#define HWIO_IPA_NTF_TX_SNP_SNP_NEXT_IS_VALID_SHFT 0x3 +#define HWIO_IPA_NTF_TX_SNP_SNP_VALID_BMSK 0x4 +#define HWIO_IPA_NTF_TX_SNP_SNP_VALID_SHFT 0x2 +#define HWIO_IPA_NTF_TX_SNP_SNP_WRITE_BMSK 0x2 +#define HWIO_IPA_NTF_TX_SNP_SNP_WRITE_SHFT 0x1 +#define HWIO_IPA_NTF_TX_SNP_SNP_LAST_BMSK 0x1 +#define HWIO_IPA_NTF_TX_SNP_SNP_LAST_SHFT 0x0 + +#define HWIO_IPA_NTF_TX_CMDQ_COUNT_ADDR (IPA_DEBUG_REG_BASE + 0x00000620) +#define HWIO_IPA_NTF_TX_CMDQ_COUNT_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000620) +#define HWIO_IPA_NTF_TX_CMDQ_COUNT_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000620) +#define HWIO_IPA_NTF_TX_CMDQ_COUNT_RMSK 0x7f +#define HWIO_IPA_NTF_TX_CMDQ_COUNT_ATTR 0x1 +#define HWIO_IPA_NTF_TX_CMDQ_COUNT_IN \ + in_dword_masked(HWIO_IPA_NTF_TX_CMDQ_COUNT_ADDR, HWIO_IPA_NTF_TX_CMDQ_COUNT_RMSK, HWIO_IPA_NTF_TX_CMDQ_COUNT_ATTR) +#define HWIO_IPA_NTF_TX_CMDQ_COUNT_INM(m) \ + in_dword_masked(HWIO_IPA_NTF_TX_CMDQ_COUNT_ADDR, m, HWIO_IPA_NTF_TX_CMDQ_COUNT_ATTR) +#define HWIO_IPA_NTF_TX_CMDQ_COUNT_FIFO_COUNT_BMSK 0x7f +#define HWIO_IPA_NTF_TX_CMDQ_COUNT_FIFO_COUNT_SHFT 0x0 + +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x00000624) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000624) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000624) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_RMSK 0x7ff +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_ATTR 0x3 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_IN \ + in_dword_masked(HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_ADDR, HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_RMSK) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_INM(m) \ + in_dword_masked(HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_ADDR, m) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_OUT(v) \ + out_dword(HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_ADDR,v) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_ADDR,m,v,HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_IN) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_RD_REQ_BMSK 0x400 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_RD_REQ_SHFT 0xa +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_CMD_CLIENT_BMSK 0x3fc +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_CMD_CLIENT_SHFT 0x2 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_POP_CMD_BMSK 0x2 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_POP_CMD_SHFT 0x1 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_WRITE_CMD_BMSK 0x1 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_WRITE_CMD_SHFT 0x0 + +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_ADDR (IPA_DEBUG_REG_BASE + 0x00000628) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000628) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000628) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_RMSK 0xffffffff +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_ATTR 0x3 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_IN \ + in_dword_masked(HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_ADDR, HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_RMSK, HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_ATTR) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_INM(m) \ + in_dword_masked(HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_ADDR, m, HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_ATTR) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_OUT(v) \ + out_dword(HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_ADDR,v) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_ADDR,m,v,HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_IN) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_CMDQ_USERDATA_BMSK 0xf8000000 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_CMDQ_USERDATA_SHFT 0x1b +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_CMDQ_SRC_ID_VALID_BMSK 0x4000000 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_CMDQ_SRC_ID_VALID_SHFT 0x1a +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_CMDQ_SENT_BMSK 0x2000000 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_CMDQ_SENT_SHFT 0x19 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_CMDQ_ORIGIN_BMSK 0x1000000 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_CMDQ_ORIGIN_SHFT 0x18 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_CMDQ_LENGTH_BMSK 0xffff00 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_CMDQ_LENGTH_SHFT 0x8 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_CMDQ_SRC_ID_BMSK 0xff +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_CMDQ_SRC_ID_SHFT 0x0 + +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_1_ADDR (IPA_DEBUG_REG_BASE + 0x0000062c) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_1_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000062c) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_1_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000062c) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_1_RMSK 0x1 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_1_ATTR 0x1 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_1_IN \ + in_dword_masked(HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_1_ADDR, HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_1_RMSK) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_1_INM(m) \ + in_dword_masked(HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_1_ADDR, m) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_1_CMDQ_FNR_AGGR_FC_BMSK 0x1 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_1_CMDQ_FNR_AGGR_FC_SHFT 0x0 + +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x00000630 + 0x4 * (n)) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x00000630 + 0x4 * (n)) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x00000630 + 0x4 * (n)) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_n_RMSK 0xffffffff +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_n_MAXn 1 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_n_ATTR 0x1 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_n_INI(n) \ + in_dword_masked(HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_n_ADDR(n), HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_n_RMSK) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_n_ADDR(n), mask) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_n_CMDQ_EMPTY_BMSK 0xffffffff +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_n_CMDQ_EMPTY_SHFT 0x0 + +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x00000650) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000650) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000650) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_RMSK 0x1ff +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_ATTR 0x1 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_IN \ + in_dword_masked(HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_ADDR, HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_RMSK, HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_ATTR) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_INM(m) \ + in_dword_masked(HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_ADDR, m, HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_ATTR) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_CMDQ_DEPTH_BMSK 0x1fc +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_CMDQ_DEPTH_SHFT 0x2 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_CMDQ_FULL_BMSK 0x2 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_CMDQ_FULL_SHFT 0x1 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_STATUS_BMSK 0x1 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_STATUS_SHFT 0x0 + +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_ADDR (IPA_DEBUG_REG_BASE + 0x00000654) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000654) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000654) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_RMSK 0x7f +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_ATTR 0x1 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_IN \ + in_dword_masked(HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_ADDR, HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_RMSK, HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_ATTR) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_INM(m) \ + in_dword_masked(HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_ADDR, m, HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_ATTR) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_FIFO_COUNT_BMSK 0x7f +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_FIFO_COUNT_SHFT 0x0 + +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ADDR (IPA_DEBUG_REG_BASE + 0x00000658) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000658) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000658) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_CFG_RMSK 0xffffffe0 +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ATTR 0x3 +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_CFG_IN \ + in_dword_masked(HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ADDR, HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_CFG_RMSK) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ADDR, m) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_CFG_OUT(v) \ + out_dword(HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ADDR,v) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ADDR,m,v,HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_CFG_IN) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ACKINJ_LENGTH_BMSK 0xffff0000 +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ACKINJ_LENGTH_SHFT 0x10 +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ACKINJ_SRC_ID_BMSK 0xff00 +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ACKINJ_SRC_ID_SHFT 0x8 +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ACKINJ_SENT_BMSK 0x80 +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ACKINJ_SENT_SHFT 0x7 +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ACKINJ_ORIGIN_BMSK 0x40 +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ACKINJ_ORIGIN_SHFT 0x6 +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ACKINJ_SRC_ID_VALID_BMSK 0x20 +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ACKINJ_SRC_ID_VALID_SHFT 0x5 + +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_PIPE_ADDR (IPA_DEBUG_REG_BASE + 0x0000065c) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_PIPE_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000065c) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_PIPE_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000065c) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_PIPE_RMSK 0xffff +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_PIPE_ATTR 0x3 +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_PIPE_IN \ + in_dword_masked(HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_PIPE_ADDR, HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_PIPE_RMSK) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_PIPE_INM(m) \ + in_dword_masked(HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_PIPE_ADDR, m) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_PIPE_OUT(v) \ + out_dword(HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_PIPE_ADDR,v) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_PIPE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_PIPE_ADDR,m,v,HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_PIPE_IN) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_PIPE_PROD_ACKINJ_SRC_PIPE_BMSK 0xff00 +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_PIPE_PROD_ACKINJ_SRC_PIPE_SHFT 0x8 +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_PIPE_CONS_ACKINJ_SRC_PIPE_BMSK 0xff +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_PIPE_CONS_ACKINJ_SRC_PIPE_SHFT 0x0 + +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKUPD_CFG_ADDR (IPA_DEBUG_REG_BASE + 0x00000660) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKUPD_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000660) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKUPD_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000660) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKUPD_CFG_RMSK 0x1ffff +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKUPD_CFG_ATTR 0x3 +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKUPD_CFG_IN \ + in_dword_masked(HWIO_IPA_ACKMNGR_SW_ACCESS_ACKUPD_CFG_ADDR, HWIO_IPA_ACKMNGR_SW_ACCESS_ACKUPD_CFG_RMSK) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKUPD_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_ACKMNGR_SW_ACCESS_ACKUPD_CFG_ADDR, m) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKUPD_CFG_OUT(v) \ + out_dword(HWIO_IPA_ACKMNGR_SW_ACCESS_ACKUPD_CFG_ADDR,v) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKUPD_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_ACKMNGR_SW_ACCESS_ACKUPD_CFG_ADDR,m,v,HWIO_IPA_ACKMNGR_SW_ACCESS_ACKUPD_CFG_IN) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKUPD_CFG_ACKUPD_ERROR_BMSK 0x10000 +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKUPD_CFG_ACKUPD_ERROR_SHFT 0x10 +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKUPD_CFG_ACKUPD_SRC_ID_BMSK 0xff00 +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKUPD_CFG_ACKUPD_SRC_ID_SHFT 0x8 +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKUPD_CFG_ACKUPD_SRC_PIPE_BMSK 0xff +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKUPD_CFG_ACKUPD_SRC_PIPE_SHFT 0x0 + +#define HWIO_IPA_ACKMNGR_SW_ACCESS_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x00000664) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000664) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000664) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_CMD_RMSK 0x3 +#define HWIO_IPA_ACKMNGR_SW_ACCESS_CMD_ATTR 0x2 +#define HWIO_IPA_ACKMNGR_SW_ACCESS_CMD_OUT(v) \ + out_dword(HWIO_IPA_ACKMNGR_SW_ACCESS_CMD_ADDR,v) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_CMD_ACKUPD_VALID_BMSK 0x2 +#define HWIO_IPA_ACKMNGR_SW_ACCESS_CMD_ACKUPD_VALID_SHFT 0x1 +#define HWIO_IPA_ACKMNGR_SW_ACCESS_CMD_ACKINJ_VALID_BMSK 0x1 +#define HWIO_IPA_ACKMNGR_SW_ACCESS_CMD_ACKINJ_VALID_SHFT 0x0 + +#define HWIO_IPA_ACKMNGR_SW_ACCESS_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x00000668) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000668) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000668) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_STATUS_RMSK 0x3 +#define HWIO_IPA_ACKMNGR_SW_ACCESS_STATUS_ATTR 0x1 +#define HWIO_IPA_ACKMNGR_SW_ACCESS_STATUS_IN \ + in_dword_masked(HWIO_IPA_ACKMNGR_SW_ACCESS_STATUS_ADDR, HWIO_IPA_ACKMNGR_SW_ACCESS_STATUS_RMSK) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_STATUS_INM(m) \ + in_dword_masked(HWIO_IPA_ACKMNGR_SW_ACCESS_STATUS_ADDR, m) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_STATUS_ACKUPD_READY_BMSK 0x2 +#define HWIO_IPA_ACKMNGR_SW_ACCESS_STATUS_ACKUPD_READY_SHFT 0x1 +#define HWIO_IPA_ACKMNGR_SW_ACCESS_STATUS_ACKINJ_READY_BMSK 0x1 +#define HWIO_IPA_ACKMNGR_SW_ACCESS_STATUS_ACKINJ_READY_SHFT 0x0 + +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ADDR (IPA_DEBUG_REG_BASE + 0x0000066c) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000066c) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000066c) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG_RMSK 0xffffffe0 +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ATTR 0x3 +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG_IN \ + in_dword_masked(HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ADDR, HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG_RMSK) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ADDR, m) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG_OUT(v) \ + out_dword(HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ADDR,v) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ADDR,m,v,HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG_IN) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ACKINJ_LENGTH_BMSK 0xffff0000 +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ACKINJ_LENGTH_SHFT 0x10 +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ACKINJ_SRC_ID_BMSK 0xff00 +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ACKINJ_SRC_ID_SHFT 0x8 +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ACKINJ_SENT_BMSK 0x80 +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ACKINJ_SENT_SHFT 0x7 +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ACKINJ_ORIGIN_BMSK 0x40 +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ACKINJ_ORIGIN_SHFT 0x6 +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ACKINJ_SRC_ID_VALID_BMSK 0x20 +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ACKINJ_SRC_ID_VALID_SHFT 0x5 + +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKUPD_CFG_ADDR (IPA_DEBUG_REG_BASE + 0x00000670) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKUPD_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000670) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKUPD_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000670) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKUPD_CFG_RMSK 0xffff +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKUPD_CFG_ATTR 0x3 +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKUPD_CFG_IN \ + in_dword_masked(HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKUPD_CFG_ADDR, HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKUPD_CFG_RMSK) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKUPD_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKUPD_CFG_ADDR, m) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKUPD_CFG_OUT(v) \ + out_dword(HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKUPD_CFG_ADDR,v) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKUPD_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKUPD_CFG_ADDR,m,v,HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKUPD_CFG_IN) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKUPD_CFG_ACKUPD_SRC_ID_BMSK 0xff00 +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKUPD_CFG_ACKUPD_SRC_ID_SHFT 0x8 +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKUPD_CFG_ACKUPD_SRC_PIPE_BMSK 0xff +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKUPD_CFG_ACKUPD_SRC_PIPE_SHFT 0x0 + +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x00000674) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000674) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000674) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_CMD_RMSK 0x3 +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_CMD_ATTR 0x2 +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_CMD_OUT(v) \ + out_dword(HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_CMD_ADDR,v) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_CMD_ACKUPD_VALID_BMSK 0x2 +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_CMD_ACKUPD_VALID_SHFT 0x1 +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_CMD_ACKINJ_VALID_BMSK 0x1 +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_CMD_ACKINJ_VALID_SHFT 0x0 + +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x00000678) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000678) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000678) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_STATUS_RMSK 0x3 +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_STATUS_ATTR 0x1 +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_STATUS_IN \ + in_dword_masked(HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_STATUS_ADDR, HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_STATUS_RMSK) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_STATUS_INM(m) \ + in_dword_masked(HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_STATUS_ADDR, m) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_STATUS_ACKUPD_READY_BMSK 0x2 +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_STATUS_ACKUPD_READY_SHFT 0x1 +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_STATUS_ACKINJ_READY_BMSK 0x1 +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_STATUS_ACKINJ_READY_SHFT 0x0 + +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG1_ADDR (IPA_DEBUG_REG_BASE + 0x0000067c) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG1_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000067c) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG1_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000067c) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG1_RMSK 0x3f +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG1_ATTR 0x3 +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG1_IN \ + in_dword_masked(HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG1_ADDR, HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG1_RMSK) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG1_INM(m) \ + in_dword_masked(HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG1_ADDR, m) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG1_OUT(v) \ + out_dword(HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG1_ADDR,v) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG1_ADDR,m,v,HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG1_IN) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG1_ACKINJ_USERDATA_BMSK 0x3f +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG1_ACKINJ_USERDATA_SHFT 0x0 + +#define HWIO_IPA_NTF_TX_CMDQ_RELEASE_WR_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x00000680 + 0x4 * (n)) +#define HWIO_IPA_NTF_TX_CMDQ_RELEASE_WR_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x00000680 + 0x4 * (n)) +#define HWIO_IPA_NTF_TX_CMDQ_RELEASE_WR_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x00000680 + 0x4 * (n)) +#define HWIO_IPA_NTF_TX_CMDQ_RELEASE_WR_n_RMSK 0xffffffff +#define HWIO_IPA_NTF_TX_CMDQ_RELEASE_WR_n_MAXn 1 +#define HWIO_IPA_NTF_TX_CMDQ_RELEASE_WR_n_ATTR 0x2 +#define HWIO_IPA_NTF_TX_CMDQ_RELEASE_WR_n_OUTI(n,val) \ + out_dword(HWIO_IPA_NTF_TX_CMDQ_RELEASE_WR_n_ADDR(n),val) +#define HWIO_IPA_NTF_TX_CMDQ_RELEASE_WR_n_RELEASE_WR_CMD_BMSK 0xffffffff +#define HWIO_IPA_NTF_TX_CMDQ_RELEASE_WR_n_RELEASE_WR_CMD_SHFT 0x0 + +#define HWIO_IPA_NTF_TX_CMDQ_RELEASE_RD_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x000006a0 + 0x4 * (n)) +#define HWIO_IPA_NTF_TX_CMDQ_RELEASE_RD_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x000006a0 + 0x4 * (n)) +#define HWIO_IPA_NTF_TX_CMDQ_RELEASE_RD_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x000006a0 + 0x4 * (n)) +#define HWIO_IPA_NTF_TX_CMDQ_RELEASE_RD_n_RMSK 0xffffffff +#define HWIO_IPA_NTF_TX_CMDQ_RELEASE_RD_n_MAXn 1 +#define HWIO_IPA_NTF_TX_CMDQ_RELEASE_RD_n_ATTR 0x2 +#define HWIO_IPA_NTF_TX_CMDQ_RELEASE_RD_n_OUTI(n,val) \ + out_dword(HWIO_IPA_NTF_TX_CMDQ_RELEASE_RD_n_ADDR(n),val) +#define HWIO_IPA_NTF_TX_CMDQ_RELEASE_RD_n_RELEASE_RD_CMD_BMSK 0xffffffff +#define HWIO_IPA_NTF_TX_CMDQ_RELEASE_RD_n_RELEASE_RD_CMD_SHFT 0x0 + +#define HWIO_IPA_NTF_TX_CMDQ_CFG_WR_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x000006c0 + 0x4 * (n)) +#define HWIO_IPA_NTF_TX_CMDQ_CFG_WR_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x000006c0 + 0x4 * (n)) +#define HWIO_IPA_NTF_TX_CMDQ_CFG_WR_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x000006c0 + 0x4 * (n)) +#define HWIO_IPA_NTF_TX_CMDQ_CFG_WR_n_RMSK 0xffffffff +#define HWIO_IPA_NTF_TX_CMDQ_CFG_WR_n_MAXn 1 +#define HWIO_IPA_NTF_TX_CMDQ_CFG_WR_n_ATTR 0x3 +#define HWIO_IPA_NTF_TX_CMDQ_CFG_WR_n_INI(n) \ + in_dword_masked(HWIO_IPA_NTF_TX_CMDQ_CFG_WR_n_ADDR(n), HWIO_IPA_NTF_TX_CMDQ_CFG_WR_n_RMSK) +#define HWIO_IPA_NTF_TX_CMDQ_CFG_WR_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_NTF_TX_CMDQ_CFG_WR_n_ADDR(n), mask) +#define HWIO_IPA_NTF_TX_CMDQ_CFG_WR_n_OUTI(n,val) \ + out_dword(HWIO_IPA_NTF_TX_CMDQ_CFG_WR_n_ADDR(n),val) +#define HWIO_IPA_NTF_TX_CMDQ_CFG_WR_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_NTF_TX_CMDQ_CFG_WR_n_ADDR(n),mask,val,HWIO_IPA_NTF_TX_CMDQ_CFG_WR_n_INI(n)) +#define HWIO_IPA_NTF_TX_CMDQ_CFG_WR_n_BLOCK_WR_BMSK 0xffffffff +#define HWIO_IPA_NTF_TX_CMDQ_CFG_WR_n_BLOCK_WR_SHFT 0x0 + +#define HWIO_IPA_NTF_TX_CMDQ_CFG_RD_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x000006e0 + 0x4 * (n)) +#define HWIO_IPA_NTF_TX_CMDQ_CFG_RD_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x000006e0 + 0x4 * (n)) +#define HWIO_IPA_NTF_TX_CMDQ_CFG_RD_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x000006e0 + 0x4 * (n)) +#define HWIO_IPA_NTF_TX_CMDQ_CFG_RD_n_RMSK 0xffffffff +#define HWIO_IPA_NTF_TX_CMDQ_CFG_RD_n_MAXn 1 +#define HWIO_IPA_NTF_TX_CMDQ_CFG_RD_n_ATTR 0x3 +#define HWIO_IPA_NTF_TX_CMDQ_CFG_RD_n_INI(n) \ + in_dword_masked(HWIO_IPA_NTF_TX_CMDQ_CFG_RD_n_ADDR(n), HWIO_IPA_NTF_TX_CMDQ_CFG_RD_n_RMSK) +#define HWIO_IPA_NTF_TX_CMDQ_CFG_RD_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_NTF_TX_CMDQ_CFG_RD_n_ADDR(n), mask) +#define HWIO_IPA_NTF_TX_CMDQ_CFG_RD_n_OUTI(n,val) \ + out_dword(HWIO_IPA_NTF_TX_CMDQ_CFG_RD_n_ADDR(n),val) +#define HWIO_IPA_NTF_TX_CMDQ_CFG_RD_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_NTF_TX_CMDQ_CFG_RD_n_ADDR(n),mask,val,HWIO_IPA_NTF_TX_CMDQ_CFG_RD_n_INI(n)) +#define HWIO_IPA_NTF_TX_CMDQ_CFG_RD_n_BLOCK_RD_BMSK 0xffffffff +#define HWIO_IPA_NTF_TX_CMDQ_CFG_RD_n_BLOCK_RD_SHFT 0x0 + +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_EMPTY_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x00000700 + 0x4 * (n)) +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_EMPTY_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x00000700 + 0x4 * (n)) +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_EMPTY_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x00000700 + 0x4 * (n)) +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_EMPTY_n_RMSK 0xffffffff +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_EMPTY_n_MAXn 1 +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_EMPTY_n_ATTR 0x1 +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_EMPTY_n_INI(n) \ + in_dword_masked(HWIO_IPA_NTF_TX_CMDQ_STATUS_EMPTY_n_ADDR(n), HWIO_IPA_NTF_TX_CMDQ_STATUS_EMPTY_n_RMSK) +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_EMPTY_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_NTF_TX_CMDQ_STATUS_EMPTY_n_ADDR(n), mask) +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_EMPTY_n_CMDQ_EMPTY_BMSK 0xffffffff +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_EMPTY_n_CMDQ_EMPTY_SHFT 0x0 + +#define HWIO_IPA_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE + 0x00000720) +#define HWIO_IPA_BASE_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000720) +#define HWIO_IPA_BASE_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000720) +#define HWIO_IPA_BASE_ADDR_RMSK 0xffffffff +#define HWIO_IPA_BASE_ADDR_ATTR 0x3 +#define HWIO_IPA_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_BASE_ADDR_ADDR, HWIO_IPA_BASE_ADDR_RMSK) +#define HWIO_IPA_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_BASE_ADDR_ADDR, m) +#define HWIO_IPA_BASE_ADDR_OUT(v) \ + out_dword(HWIO_IPA_BASE_ADDR_ADDR,v) +#define HWIO_IPA_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_BASE_ADDR_ADDR,m,v,HWIO_IPA_BASE_ADDR_IN) +#define HWIO_IPA_BASE_ADDR_BASE_BMSK 0xffe00000 +#define HWIO_IPA_BASE_ADDR_BASE_SHFT 0x15 +#define HWIO_IPA_BASE_ADDR_ZERO_BMSK 0x1fffff +#define HWIO_IPA_BASE_ADDR_ZERO_SHFT 0x0 + +#define HWIO_IPA_BASE_ADDR_MSB_ADDR (IPA_DEBUG_REG_BASE + 0x00000724) +#define HWIO_IPA_BASE_ADDR_MSB_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000724) +#define HWIO_IPA_BASE_ADDR_MSB_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000724) +#define HWIO_IPA_BASE_ADDR_MSB_RMSK 0xffffffff +#define HWIO_IPA_BASE_ADDR_MSB_ATTR 0x3 +#define HWIO_IPA_BASE_ADDR_MSB_IN \ + in_dword_masked(HWIO_IPA_BASE_ADDR_MSB_ADDR, HWIO_IPA_BASE_ADDR_MSB_RMSK) +#define HWIO_IPA_BASE_ADDR_MSB_INM(m) \ + in_dword_masked(HWIO_IPA_BASE_ADDR_MSB_ADDR, m) +#define HWIO_IPA_BASE_ADDR_MSB_OUT(v) \ + out_dword(HWIO_IPA_BASE_ADDR_MSB_ADDR,v) +#define HWIO_IPA_BASE_ADDR_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_BASE_ADDR_MSB_ADDR,m,v,HWIO_IPA_BASE_ADDR_MSB_IN) +#define HWIO_IPA_BASE_ADDR_MSB_BASE_MSB_BMSK 0xffffffff +#define HWIO_IPA_BASE_ADDR_MSB_BASE_MSB_SHFT 0x0 + +#define HWIO_IPA_ENDP_GSI_CFG1_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x00000800 + 0x4 * (n)) +#define HWIO_IPA_ENDP_GSI_CFG1_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x00000800 + 0x4 * (n)) +#define HWIO_IPA_ENDP_GSI_CFG1_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x00000800 + 0x4 * (n)) +#define HWIO_IPA_ENDP_GSI_CFG1_n_RMSK 0x80010000 +#define HWIO_IPA_ENDP_GSI_CFG1_n_MAXn 35 +#define HWIO_IPA_ENDP_GSI_CFG1_n_ATTR 0x3 +#define HWIO_IPA_ENDP_GSI_CFG1_n_INI(n) \ + in_dword_masked(HWIO_IPA_ENDP_GSI_CFG1_n_ADDR(n), HWIO_IPA_ENDP_GSI_CFG1_n_RMSK) +#define HWIO_IPA_ENDP_GSI_CFG1_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ENDP_GSI_CFG1_n_ADDR(n), mask) +#define HWIO_IPA_ENDP_GSI_CFG1_n_OUTI(n,val) \ + out_dword(HWIO_IPA_ENDP_GSI_CFG1_n_ADDR(n),val) +#define HWIO_IPA_ENDP_GSI_CFG1_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_ENDP_GSI_CFG1_n_ADDR(n),mask,val,HWIO_IPA_ENDP_GSI_CFG1_n_INI(n)) +#define HWIO_IPA_ENDP_GSI_CFG1_n_INIT_ENDP_BMSK 0x80000000 +#define HWIO_IPA_ENDP_GSI_CFG1_n_INIT_ENDP_SHFT 0x1f +#define HWIO_IPA_ENDP_GSI_CFG1_n_ENDP_EN_BMSK 0x10000 +#define HWIO_IPA_ENDP_GSI_CFG1_n_ENDP_EN_SHFT 0x10 + +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_1_ADDR (IPA_DEBUG_REG_BASE + 0x00000c00) +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_1_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000c00) +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_1_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000c00) +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_1_RMSK 0xffffffff +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_1_ATTR 0x3 +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_1_IN \ + in_dword_masked(HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_1_ADDR, HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_1_RMSK) +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_1_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_1_ADDR, m) +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_1_OUT(v) \ + out_dword(HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_1_ADDR,v) +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_1_ADDR,m,v,HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_1_IN) +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_1_GEN_TLV_OUT_ADDR_LSB_BMSK 0xffffffff +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_1_GEN_TLV_OUT_ADDR_LSB_SHFT 0x0 + +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_2_ADDR (IPA_DEBUG_REG_BASE + 0x00000c04) +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_2_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000c04) +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_2_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000c04) +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_2_RMSK 0xffffffff +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_2_ATTR 0x3 +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_2_IN \ + in_dword_masked(HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_2_ADDR, HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_2_RMSK) +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_2_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_2_ADDR, m) +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_2_OUT(v) \ + out_dword(HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_2_ADDR,v) +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_2_ADDR,m,v,HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_2_IN) +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_2_GEN_TLV_OUT_EE_BMSK 0xf0000000 +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_2_GEN_TLV_OUT_EE_SHFT 0x1c +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_2_GEN_TLV_OUT_ROUTINE_BMSK 0xf000000 +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_2_GEN_TLV_OUT_ROUTINE_SHFT 0x18 +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_2_GEN_TLV_OUT_LENGTH_BMSK 0xffff00 +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_2_GEN_TLV_OUT_LENGTH_SHFT 0x8 +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_2_GEN_TLV_OUT_ADDR_MSB_BMSK 0xff +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_2_GEN_TLV_OUT_ADDR_MSB_SHFT 0x0 + +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_3_ADDR (IPA_DEBUG_REG_BASE + 0x00000c08) +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_3_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000c08) +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_3_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000c08) +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_3_RMSK 0xffff3fff +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_3_ATTR 0x3 +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_3_IN \ + in_dword_masked(HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_3_ADDR, HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_3_RMSK) +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_3_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_3_ADDR, m) +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_3_OUT(v) \ + out_dword(HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_3_ADDR,v) +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_3_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_3_ADDR,m,v,HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_3_IN) +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_3_GEN_TLV_OUT_USER_DATA_BMSK 0xfffe0000 +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_3_GEN_TLV_OUT_USER_DATA_SHFT 0x11 +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_3_GEN_TLV_OUT_CHAIN_BMSK 0x10000 +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_3_GEN_TLV_OUT_CHAIN_SHFT 0x10 +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_3_GEN_TLV_OUT_TOP_ADDR_BIT_BMSK 0x2000 +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_3_GEN_TLV_OUT_TOP_ADDR_BIT_SHFT 0xd +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_3_GEN_TLV_OUT_DIRECTION_BMSK 0x1000 +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_3_GEN_TLV_OUT_DIRECTION_SHFT 0xc +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_3_GEN_TLV_OUT_TYPE_BMSK 0xf00 +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_3_GEN_TLV_OUT_TYPE_SHFT 0x8 +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_3_GEN_TLV_OUT_CHID_BMSK 0xff +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_3_GEN_TLV_OUT_CHID_SHFT 0x0 + +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_CTRL_ADDR (IPA_DEBUG_REG_BASE + 0x00000c0c) +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_CTRL_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000c0c) +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_CTRL_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000c0c) +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_CTRL_RMSK 0x1100f1 +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_CTRL_ATTR 0x3 +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_CTRL_IN \ + in_dword_masked(HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_CTRL_ADDR, HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_CTRL_RMSK) +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_CTRL_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_CTRL_ADDR, m) +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_CTRL_OUT(v) \ + out_dword(HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_CTRL_ADDR,v) +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_CTRL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_CTRL_ADDR,m,v,HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_CTRL_IN) +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_CTRL_GEN_TLV_OUT_EN_BMSK 0x100000 +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_CTRL_GEN_TLV_OUT_EN_SHFT 0x14 +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_CTRL_GEN_TLV_OUT_ACTIVATE_BMSK 0x10000 +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_CTRL_GEN_TLV_OUT_ACTIVATE_SHFT 0x10 +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_CTRL_GEN_TLV_OUT_STATUS_BMSK 0xf0 +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_CTRL_GEN_TLV_OUT_STATUS_SHFT 0x4 +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_CTRL_GEN_TLV_OUT_RDY_BMSK 0x1 +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_CTRL_GEN_TLV_OUT_RDY_SHFT 0x0 + +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_RDY_ADDR (IPA_DEBUG_REG_BASE + 0x00000d10) +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_RDY_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000d10) +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_RDY_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000d10) +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_RDY_RMSK 0x1 +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_RDY_ATTR 0x3 +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_RDY_IN \ + in_dword_masked(HWIO_IPA_GSI_IPA_IF_TLV_IN_RDY_ADDR, HWIO_IPA_GSI_IPA_IF_TLV_IN_RDY_RMSK) +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_RDY_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_IPA_IF_TLV_IN_RDY_ADDR, m) +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_RDY_OUT(v) \ + out_dword(HWIO_IPA_GSI_IPA_IF_TLV_IN_RDY_ADDR,v) +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_RDY_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_IPA_IF_TLV_IN_RDY_ADDR,m,v,HWIO_IPA_GSI_IPA_IF_TLV_IN_RDY_IN) +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_RDY_GEN_TLV_IN_RDY_BMSK 0x1 +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_RDY_GEN_TLV_IN_RDY_SHFT 0x0 + +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_DATA_1_ADDR (IPA_DEBUG_REG_BASE + 0x00000d14) +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_DATA_1_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000d14) +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_DATA_1_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000d14) +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_DATA_1_RMSK 0xffffffff +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_DATA_1_ATTR 0x1 +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_DATA_1_IN \ + in_dword_masked(HWIO_IPA_GSI_IPA_IF_TLV_IN_DATA_1_ADDR, HWIO_IPA_GSI_IPA_IF_TLV_IN_DATA_1_RMSK) +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_DATA_1_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_IPA_IF_TLV_IN_DATA_1_ADDR, m) +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_DATA_1_GEN_TLV_IN_LENGTH_BMSK 0xffff0000 +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_DATA_1_GEN_TLV_IN_LENGTH_SHFT 0x10 +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_DATA_1_GEN_TLV_IN_USER_DATA_BMSK 0xffff +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_DATA_1_GEN_TLV_IN_USER_DATA_SHFT 0x0 + +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_DATA_2_ADDR (IPA_DEBUG_REG_BASE + 0x00000d18) +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_DATA_2_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000d18) +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_DATA_2_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000d18) +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_DATA_2_RMSK 0xf00ffff1 +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_DATA_2_ATTR 0x3 +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_DATA_2_IN \ + in_dword_masked(HWIO_IPA_GSI_IPA_IF_TLV_IN_DATA_2_ADDR, HWIO_IPA_GSI_IPA_IF_TLV_IN_DATA_2_RMSK) +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_DATA_2_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_IPA_IF_TLV_IN_DATA_2_ADDR, m) +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_DATA_2_OUT(v) \ + out_dword(HWIO_IPA_GSI_IPA_IF_TLV_IN_DATA_2_ADDR,v) +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_DATA_2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_IPA_IF_TLV_IN_DATA_2_ADDR,m,v,HWIO_IPA_GSI_IPA_IF_TLV_IN_DATA_2_IN) +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_DATA_2_GEN_TLV_IN_ROUTINE_BMSK 0xf0000000 +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_DATA_2_GEN_TLV_IN_ROUTINE_SHFT 0x1c +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_DATA_2_GEN_TLV_IN_STATUS_BMSK 0xf0000 +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_DATA_2_GEN_TLV_IN_STATUS_SHFT 0x10 +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_DATA_2_GEN_TLV_IN_CHID_BMSK 0xff00 +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_DATA_2_GEN_TLV_IN_CHID_SHFT 0x8 +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_DATA_2_GEN_TLV_IN_EE_BMSK 0xf0 +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_DATA_2_GEN_TLV_IN_EE_SHFT 0x4 +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_DATA_2_GEN_TLV_IN_EOT_BMSK 0x1 +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_DATA_2_GEN_TLV_IN_EOT_SHFT 0x0 + +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x00001000 + 0x4 * (n)) +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x00001000 + 0x4 * (n)) +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x00001000 + 0x4 * (n)) +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_RMSK 0xffffff +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_MAXn 35 +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_ATTR 0x3 +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_INI(n) \ + in_dword_masked(HWIO_IPA_ENDP_GSI_CFG_TLV_n_ADDR(n), HWIO_IPA_ENDP_GSI_CFG_TLV_n_RMSK) +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ENDP_GSI_CFG_TLV_n_ADDR(n), mask) +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_OUTI(n,val) \ + out_dword(HWIO_IPA_ENDP_GSI_CFG_TLV_n_ADDR(n),val) +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_ENDP_GSI_CFG_TLV_n_ADDR(n),mask,val,HWIO_IPA_ENDP_GSI_CFG_TLV_n_INI(n)) +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_FIFO_SIZE_BMSK 0xff0000 +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_FIFO_SIZE_SHFT 0x10 +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_FIFO_BASE_ADDR_BMSK 0xffff +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_FIFO_BASE_ADDR_SHFT 0x0 + +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x00001400 + 0x4 * (n)) +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x00001400 + 0x4 * (n)) +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x00001400 + 0x4 * (n)) +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_RMSK 0xffffff +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_MAXn 35 +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_ATTR 0x3 +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_INI(n) \ + in_dword_masked(HWIO_IPA_ENDP_GSI_CFG_AOS_n_ADDR(n), HWIO_IPA_ENDP_GSI_CFG_AOS_n_RMSK) +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ENDP_GSI_CFG_AOS_n_ADDR(n), mask) +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_OUTI(n,val) \ + out_dword(HWIO_IPA_ENDP_GSI_CFG_AOS_n_ADDR(n),val) +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_ENDP_GSI_CFG_AOS_n_ADDR(n),mask,val,HWIO_IPA_ENDP_GSI_CFG_AOS_n_INI(n)) +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_FIFO_SIZE_BMSK 0xff0000 +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_FIFO_SIZE_SHFT 0x10 +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_FIFO_BASE_ADDR_BMSK 0xffff +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_FIFO_BASE_ADDR_SHFT 0x0 + +#define HWIO_IPA_COAL_VP_AOS_FIFO_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x00001800 + 0x4 * (n)) +#define HWIO_IPA_COAL_VP_AOS_FIFO_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x00001800 + 0x4 * (n)) +#define HWIO_IPA_COAL_VP_AOS_FIFO_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x00001800 + 0x4 * (n)) +#define HWIO_IPA_COAL_VP_AOS_FIFO_n_RMSK 0xffffff +#define HWIO_IPA_COAL_VP_AOS_FIFO_n_MAXn 3 +#define HWIO_IPA_COAL_VP_AOS_FIFO_n_ATTR 0x3 +#define HWIO_IPA_COAL_VP_AOS_FIFO_n_INI(n) \ + in_dword_masked(HWIO_IPA_COAL_VP_AOS_FIFO_n_ADDR(n), HWIO_IPA_COAL_VP_AOS_FIFO_n_RMSK) +#define HWIO_IPA_COAL_VP_AOS_FIFO_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_COAL_VP_AOS_FIFO_n_ADDR(n), mask) +#define HWIO_IPA_COAL_VP_AOS_FIFO_n_OUTI(n,val) \ + out_dword(HWIO_IPA_COAL_VP_AOS_FIFO_n_ADDR(n),val) +#define HWIO_IPA_COAL_VP_AOS_FIFO_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_COAL_VP_AOS_FIFO_n_ADDR(n),mask,val,HWIO_IPA_COAL_VP_AOS_FIFO_n_INI(n)) +#define HWIO_IPA_COAL_VP_AOS_FIFO_n_FIFO_SIZE_BMSK 0xff0000 +#define HWIO_IPA_COAL_VP_AOS_FIFO_n_FIFO_SIZE_SHFT 0x10 +#define HWIO_IPA_COAL_VP_AOS_FIFO_n_FIFO_BASE_ADDR_BMSK 0xffff +#define HWIO_IPA_COAL_VP_AOS_FIFO_n_FIFO_BASE_ADDR_SHFT 0x0 + +#define HWIO_IPA_QMB_DEBUG_CTRL_ADDR (IPA_DEBUG_REG_BASE + 0x00001d40) +#define HWIO_IPA_QMB_DEBUG_CTRL_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00001d40) +#define HWIO_IPA_QMB_DEBUG_CTRL_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00001d40) +#define HWIO_IPA_QMB_DEBUG_CTRL_RMSK 0x1 +#define HWIO_IPA_QMB_DEBUG_CTRL_ATTR 0x3 +#define HWIO_IPA_QMB_DEBUG_CTRL_IN \ + in_dword_masked(HWIO_IPA_QMB_DEBUG_CTRL_ADDR, HWIO_IPA_QMB_DEBUG_CTRL_RMSK) +#define HWIO_IPA_QMB_DEBUG_CTRL_INM(m) \ + in_dword_masked(HWIO_IPA_QMB_DEBUG_CTRL_ADDR, m) +#define HWIO_IPA_QMB_DEBUG_CTRL_OUT(v) \ + out_dword(HWIO_IPA_QMB_DEBUG_CTRL_ADDR,v) +#define HWIO_IPA_QMB_DEBUG_CTRL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_QMB_DEBUG_CTRL_ADDR,m,v,HWIO_IPA_QMB_DEBUG_CTRL_IN) +#define HWIO_IPA_QMB_DEBUG_CTRL_RAM_SLAVEWAY_ACCESS_PROTECTION_DISABLE_BMSK 0x1 +#define HWIO_IPA_QMB_DEBUG_CTRL_RAM_SLAVEWAY_ACCESS_PROTECTION_DISABLE_SHFT 0x0 + +#define HWIO_IPA_CTXH_CTRL_ADDR (IPA_DEBUG_REG_BASE + 0x00001e50) +#define HWIO_IPA_CTXH_CTRL_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00001e50) +#define HWIO_IPA_CTXH_CTRL_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00001e50) +#define HWIO_IPA_CTXH_CTRL_RMSK 0xe000000f +#define HWIO_IPA_CTXH_CTRL_ATTR 0x3 +#define HWIO_IPA_CTXH_CTRL_IN \ + in_dword_masked(HWIO_IPA_CTXH_CTRL_ADDR, HWIO_IPA_CTXH_CTRL_RMSK) +#define HWIO_IPA_CTXH_CTRL_INM(m) \ + in_dword_masked(HWIO_IPA_CTXH_CTRL_ADDR, m) +#define HWIO_IPA_CTXH_CTRL_OUT(v) \ + out_dword(HWIO_IPA_CTXH_CTRL_ADDR,v) +#define HWIO_IPA_CTXH_CTRL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_CTXH_CTRL_ADDR,m,v,HWIO_IPA_CTXH_CTRL_IN) +#define HWIO_IPA_CTXH_CTRL_CTXH_LOCK_BMSK 0x80000000 +#define HWIO_IPA_CTXH_CTRL_CTXH_LOCK_SHFT 0x1f +#define HWIO_IPA_CTXH_CTRL_CTXH_LOCK_ACTIVE_BMSK 0x40000000 +#define HWIO_IPA_CTXH_CTRL_CTXH_LOCK_ACTIVE_SHFT 0x1e +#define HWIO_IPA_CTXH_CTRL_CTXH_WR_BLOCK_ON_NOC_ERR_BMSK 0x20000000 +#define HWIO_IPA_CTXH_CTRL_CTXH_WR_BLOCK_ON_NOC_ERR_SHFT 0x1d +#define HWIO_IPA_CTXH_CTRL_CTXH_LOCK_ID_BMSK 0xf +#define HWIO_IPA_CTXH_CTRL_CTXH_LOCK_ID_SHFT 0x0 + +#define HWIO_IPA_CTX_ID_m_CTX_NUM_n_ADDR(m,n) (IPA_DEBUG_REG_BASE + 0x00002000 + 0x100 * (m) + 0x4 * (n)) +#define HWIO_IPA_CTX_ID_m_CTX_NUM_n_PHYS(m,n) (IPA_DEBUG_REG_BASE_PHYS + 0x00002000 + 0x100 * (m) + 0x4 * (n)) +#define HWIO_IPA_CTX_ID_m_CTX_NUM_n_OFFS(m,n) (IPA_DEBUG_REG_BASE_OFFS + 0x00002000 + 0x100 * (m) + 0x4 * (n)) +#define HWIO_IPA_CTX_ID_m_CTX_NUM_n_RMSK 0xffffffff +#define HWIO_IPA_CTX_ID_m_CTX_NUM_n_MAXm 15 +#define HWIO_IPA_CTX_ID_m_CTX_NUM_n_MAXn 63 +#define HWIO_IPA_CTX_ID_m_CTX_NUM_n_ATTR 0x3 +#define HWIO_IPA_CTX_ID_m_CTX_NUM_n_INI2(m,n) \ + in_dword_masked(HWIO_IPA_CTX_ID_m_CTX_NUM_n_ADDR(m,n), HWIO_IPA_CTX_ID_m_CTX_NUM_n_RMSK) +#define HWIO_IPA_CTX_ID_m_CTX_NUM_n_INMI2(m,n,mask) \ + in_dword_masked(HWIO_IPA_CTX_ID_m_CTX_NUM_n_ADDR(m,n), mask) +#define HWIO_IPA_CTX_ID_m_CTX_NUM_n_OUTI2(m,n,val) \ + out_dword(HWIO_IPA_CTX_ID_m_CTX_NUM_n_ADDR(m,n),val) +#define HWIO_IPA_CTX_ID_m_CTX_NUM_n_OUTMI2(m,n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_CTX_ID_m_CTX_NUM_n_ADDR(m,n),mask,val,HWIO_IPA_CTX_ID_m_CTX_NUM_n_INI2(m,n)) +#define HWIO_IPA_CTX_ID_m_CTX_NUM_n_IPA_CTXH_DATA_BMSK 0xffffffff +#define HWIO_IPA_CTX_ID_m_CTX_NUM_n_IPA_CTXH_DATA_SHFT 0x0 + +/*---------------------------------------------------------------------------- + * MODULE: IPA_CFG + *--------------------------------------------------------------------------*/ + +#define IPA_CFG_REG_BASE (IPA_0_IPA_WRAPPER_BASE + 0x00140000) +#define IPA_CFG_REG_BASE_PHYS (IPA_0_IPA_WRAPPER_BASE_PHYS + 0x00140000) +#define IPA_CFG_REG_BASE_OFFS 0x00140000 + +#define HWIO_IPA_FLAVOR_0_ADDR (IPA_CFG_REG_BASE + 0x00000000) +#define HWIO_IPA_FLAVOR_0_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000000) +#define HWIO_IPA_FLAVOR_0_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000000) +#define HWIO_IPA_FLAVOR_0_RMSK 0xffffffff +#define HWIO_IPA_FLAVOR_0_ATTR 0x1 +#define HWIO_IPA_FLAVOR_0_IN \ + in_dword_masked(HWIO_IPA_FLAVOR_0_ADDR, HWIO_IPA_FLAVOR_0_RMSK) +#define HWIO_IPA_FLAVOR_0_INM(m) \ + in_dword_masked(HWIO_IPA_FLAVOR_0_ADDR, m) +#define HWIO_IPA_FLAVOR_0_IPA_PROD_LOWEST_BMSK 0xff000000 +#define HWIO_IPA_FLAVOR_0_IPA_PROD_LOWEST_SHFT 0x18 +#define HWIO_IPA_FLAVOR_0_IPA_PROD_PIPES_BMSK 0xff0000 +#define HWIO_IPA_FLAVOR_0_IPA_PROD_PIPES_SHFT 0x10 +#define HWIO_IPA_FLAVOR_0_IPA_CONS_PIPES_BMSK 0xff00 +#define HWIO_IPA_FLAVOR_0_IPA_CONS_PIPES_SHFT 0x8 +#define HWIO_IPA_FLAVOR_0_IPA_PIPES_BMSK 0xff +#define HWIO_IPA_FLAVOR_0_IPA_PIPES_SHFT 0x0 + +#define HWIO_IPA_FLAVOR_1_ADDR (IPA_CFG_REG_BASE + 0x00000004) +#define HWIO_IPA_FLAVOR_1_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000004) +#define HWIO_IPA_FLAVOR_1_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000004) +#define HWIO_IPA_FLAVOR_1_RMSK 0x1fffdf3f +#define HWIO_IPA_FLAVOR_1_ATTR 0x1 +#define HWIO_IPA_FLAVOR_1_IN \ + in_dword_masked(HWIO_IPA_FLAVOR_1_ADDR, HWIO_IPA_FLAVOR_1_RMSK) +#define HWIO_IPA_FLAVOR_1_INM(m) \ + in_dword_masked(HWIO_IPA_FLAVOR_1_ADDR, m) +#define HWIO_IPA_FLAVOR_1_D_DCPH_ENGINE_NUM_BMSK 0x18000000 +#define HWIO_IPA_FLAVOR_1_D_DCPH_ENGINE_NUM_SHFT 0x1b +#define HWIO_IPA_FLAVOR_1_PCIE_PATH_EN_BMSK 0x4000000 +#define HWIO_IPA_FLAVOR_1_PCIE_PATH_EN_SHFT 0x1a +#define HWIO_IPA_FLAVOR_1_GSI_SLAVEWAY_EN_BMSK 0x2000000 +#define HWIO_IPA_FLAVOR_1_GSI_SLAVEWAY_EN_SHFT 0x19 +#define HWIO_IPA_FLAVOR_1_RX_UC_HANDLER_EN_BMSK 0x1000000 +#define HWIO_IPA_FLAVOR_1_RX_UC_HANDLER_EN_SHFT 0x18 +#define HWIO_IPA_FLAVOR_1_DUAL_TX_EN_BMSK 0x800000 +#define HWIO_IPA_FLAVOR_1_DUAL_TX_EN_SHFT 0x17 +#define HWIO_IPA_FLAVOR_1_QMB1_EN_BMSK 0x400000 +#define HWIO_IPA_FLAVOR_1_QMB1_EN_SHFT 0x16 +#define HWIO_IPA_FLAVOR_1_QMB1_SLAVEWAY_EN_BMSK 0x200000 +#define HWIO_IPA_FLAVOR_1_QMB1_SLAVEWAY_EN_SHFT 0x15 +#define HWIO_IPA_FLAVOR_1_QMB0_SLAVEWAY_EN_BMSK 0x100000 +#define HWIO_IPA_FLAVOR_1_QMB0_SLAVEWAY_EN_SHFT 0x14 +#define HWIO_IPA_FLAVOR_1_DPL_EN_BMSK 0x80000 +#define HWIO_IPA_FLAVOR_1_DPL_EN_SHFT 0x13 +#define HWIO_IPA_FLAVOR_1_CPR_EN_BMSK 0x40000 +#define HWIO_IPA_FLAVOR_1_CPR_EN_SHFT 0x12 +#define HWIO_IPA_FLAVOR_1_UC_EN_BMSK 0x20000 +#define HWIO_IPA_FLAVOR_1_UC_EN_SHFT 0x11 +#define HWIO_IPA_FLAVOR_1_VMIDMT_EN_BMSK 0x10000 +#define HWIO_IPA_FLAVOR_1_VMIDMT_EN_SHFT 0x10 +#define HWIO_IPA_FLAVOR_1_NAT_ACL_EN_BMSK 0x8000 +#define HWIO_IPA_FLAVOR_1_NAT_ACL_EN_SHFT 0xf +#define HWIO_IPA_FLAVOR_1_FILTER_ROUTER_CACHE_GEN_BMSK 0x4000 +#define HWIO_IPA_FLAVOR_1_FILTER_ROUTER_CACHE_GEN_SHFT 0xe +#define HWIO_IPA_FLAVOR_1_H_DCPH_EN_BMSK 0x1000 +#define HWIO_IPA_FLAVOR_1_H_DCPH_EN_SHFT 0xc +#define HWIO_IPA_FLAVOR_1_D_DCPH_EN_BMSK 0x800 +#define HWIO_IPA_FLAVOR_1_D_DCPH_EN_SHFT 0xb +#define HWIO_IPA_FLAVOR_1_D_DCPH_2_EN_BMSK 0x400 +#define HWIO_IPA_FLAVOR_1_D_DCPH_2_EN_SHFT 0xa +#define HWIO_IPA_FLAVOR_1_UCP_EN_BMSK 0x200 +#define HWIO_IPA_FLAVOR_1_UCP_EN_SHFT 0x9 +#define HWIO_IPA_FLAVOR_1_MBIM_DEAGG_EN_BMSK 0x100 +#define HWIO_IPA_FLAVOR_1_MBIM_DEAGG_EN_SHFT 0x8 +#define HWIO_IPA_FLAVOR_1_CTX_N_BMSK 0x3f +#define HWIO_IPA_FLAVOR_1_CTX_N_SHFT 0x0 + +#define HWIO_IPA_FLAVOR_2_ADDR (IPA_CFG_REG_BASE + 0x00000008) +#define HWIO_IPA_FLAVOR_2_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000008) +#define HWIO_IPA_FLAVOR_2_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000008) +#define HWIO_IPA_FLAVOR_2_RMSK 0x3f3f3f3f +#define HWIO_IPA_FLAVOR_2_ATTR 0x1 +#define HWIO_IPA_FLAVOR_2_IN \ + in_dword_masked(HWIO_IPA_FLAVOR_2_ADDR, HWIO_IPA_FLAVOR_2_RMSK) +#define HWIO_IPA_FLAVOR_2_INM(m) \ + in_dword_masked(HWIO_IPA_FLAVOR_2_ADDR, m) +#define HWIO_IPA_FLAVOR_2_QMB1_OUTST_RD_BMSK 0x3f000000 +#define HWIO_IPA_FLAVOR_2_QMB1_OUTST_RD_SHFT 0x18 +#define HWIO_IPA_FLAVOR_2_QMB1_OUTST_WR_BMSK 0x3f0000 +#define HWIO_IPA_FLAVOR_2_QMB1_OUTST_WR_SHFT 0x10 +#define HWIO_IPA_FLAVOR_2_QMB0_OUTST_RD_BMSK 0x3f00 +#define HWIO_IPA_FLAVOR_2_QMB0_OUTST_RD_SHFT 0x8 +#define HWIO_IPA_FLAVOR_2_QMB0_OUTST_WR_BMSK 0x3f +#define HWIO_IPA_FLAVOR_2_QMB0_OUTST_WR_SHFT 0x0 + +#define HWIO_IPA_FLAVOR_3_ADDR (IPA_CFG_REG_BASE + 0x0000000c) +#define HWIO_IPA_FLAVOR_3_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000000c) +#define HWIO_IPA_FLAVOR_3_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000000c) +#define HWIO_IPA_FLAVOR_3_RMSK 0xfffffff +#define HWIO_IPA_FLAVOR_3_ATTR 0x1 +#define HWIO_IPA_FLAVOR_3_IN \ + in_dword_masked(HWIO_IPA_FLAVOR_3_ADDR, HWIO_IPA_FLAVOR_3_RMSK) +#define HWIO_IPA_FLAVOR_3_INM(m) \ + in_dword_masked(HWIO_IPA_FLAVOR_3_ADDR, m) +#define HWIO_IPA_FLAVOR_3_RSRC_GRP_DST_NUM_DRBIP_BMSK 0xf000000 +#define HWIO_IPA_FLAVOR_3_RSRC_GRP_DST_NUM_DRBIP_SHFT 0x18 +#define HWIO_IPA_FLAVOR_3_PKT_CTX_SIZE_BMSK 0xff0000 +#define HWIO_IPA_FLAVOR_3_PKT_CTX_SIZE_SHFT 0x10 +#define HWIO_IPA_FLAVOR_3_RSRC_GRP_DST_NUM_UC_BMSK 0xf000 +#define HWIO_IPA_FLAVOR_3_RSRC_GRP_DST_NUM_UC_SHFT 0xc +#define HWIO_IPA_FLAVOR_3_RSRC_GRP_DST_NUM_WO_UC_N_DRBIP_BMSK 0xf00 +#define HWIO_IPA_FLAVOR_3_RSRC_GRP_DST_NUM_WO_UC_N_DRBIP_SHFT 0x8 +#define HWIO_IPA_FLAVOR_3_RSRC_GRP_SRC_NUM_UC_BMSK 0xf0 +#define HWIO_IPA_FLAVOR_3_RSRC_GRP_SRC_NUM_UC_SHFT 0x4 +#define HWIO_IPA_FLAVOR_3_RSRC_GRP_SRC_NUM_WOUT_UC_BMSK 0xf +#define HWIO_IPA_FLAVOR_3_RSRC_GRP_SRC_NUM_WOUT_UC_SHFT 0x0 + +#define HWIO_IPA_FLAVOR_4_ADDR (IPA_CFG_REG_BASE + 0x00000010) +#define HWIO_IPA_FLAVOR_4_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000010) +#define HWIO_IPA_FLAVOR_4_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000010) +#define HWIO_IPA_FLAVOR_4_RMSK 0x30ffffff +#define HWIO_IPA_FLAVOR_4_ATTR 0x1 +#define HWIO_IPA_FLAVOR_4_IN \ + in_dword_masked(HWIO_IPA_FLAVOR_4_ADDR, HWIO_IPA_FLAVOR_4_RMSK) +#define HWIO_IPA_FLAVOR_4_INM(m) \ + in_dword_masked(HWIO_IPA_FLAVOR_4_ADDR, m) +#define HWIO_IPA_FLAVOR_4_FRAG_TABLES_NUM_BMSK 0x30000000 +#define HWIO_IPA_FLAVOR_4_FRAG_TABLES_NUM_SHFT 0x1c +#define HWIO_IPA_FLAVOR_4_MBIM_AGG_PIPES_BMSK 0xf00000 +#define HWIO_IPA_FLAVOR_4_MBIM_AGG_PIPES_SHFT 0x14 +#define HWIO_IPA_FLAVOR_4_BEARER_INIT_CTX_NUM_BMSK 0xf0000 +#define HWIO_IPA_FLAVOR_4_BEARER_INIT_CTX_NUM_SHFT 0x10 +#define HWIO_IPA_FLAVOR_4_GENERIC_DEAGG_PIPES_BMSK 0xff00 +#define HWIO_IPA_FLAVOR_4_GENERIC_DEAGG_PIPES_SHFT 0x8 +#define HWIO_IPA_FLAVOR_4_GENERIC_AGG_PIPES_BMSK 0xff +#define HWIO_IPA_FLAVOR_4_GENERIC_AGG_PIPES_SHFT 0x0 + +#define HWIO_IPA_FLAVOR_5_ADDR (IPA_CFG_REG_BASE + 0x00000014) +#define HWIO_IPA_FLAVOR_5_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000014) +#define HWIO_IPA_FLAVOR_5_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000014) +#define HWIO_IPA_FLAVOR_5_RMSK 0x3fff3f3f +#define HWIO_IPA_FLAVOR_5_ATTR 0x1 +#define HWIO_IPA_FLAVOR_5_IN \ + in_dword_masked(HWIO_IPA_FLAVOR_5_ADDR, HWIO_IPA_FLAVOR_5_RMSK) +#define HWIO_IPA_FLAVOR_5_INM(m) \ + in_dword_masked(HWIO_IPA_FLAVOR_5_ADDR, m) +#define HWIO_IPA_FLAVOR_5_RX_HPS_CMDQ_Q_DEPTH_BMSK 0x3f000000 +#define HWIO_IPA_FLAVOR_5_RX_HPS_CMDQ_Q_DEPTH_SHFT 0x18 +#define HWIO_IPA_FLAVOR_5_GSI_NUM_EES_BMSK 0xf00000 +#define HWIO_IPA_FLAVOR_5_GSI_NUM_EES_SHFT 0x14 +#define HWIO_IPA_FLAVOR_5_IPA_NUM_EES_BMSK 0xf0000 +#define HWIO_IPA_FLAVOR_5_IPA_NUM_EES_SHFT 0x10 +#define HWIO_IPA_FLAVOR_5_PRODUCER_ACK_MNGR_DB_DEPTH_BMSK 0x3f00 +#define HWIO_IPA_FLAVOR_5_PRODUCER_ACK_MNGR_DB_DEPTH_SHFT 0x8 +#define HWIO_IPA_FLAVOR_5_CONSUMER_ACK_MNGR_DB_DEPTH_BMSK 0x3f +#define HWIO_IPA_FLAVOR_5_CONSUMER_ACK_MNGR_DB_DEPTH_SHFT 0x0 + +#define HWIO_IPA_FLAVOR_6_ADDR (IPA_CFG_REG_BASE + 0x00000018) +#define HWIO_IPA_FLAVOR_6_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000018) +#define HWIO_IPA_FLAVOR_6_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000018) +#define HWIO_IPA_FLAVOR_6_RMSK 0x3fff3fff +#define HWIO_IPA_FLAVOR_6_ATTR 0x1 +#define HWIO_IPA_FLAVOR_6_IN \ + in_dword_masked(HWIO_IPA_FLAVOR_6_ADDR, HWIO_IPA_FLAVOR_6_RMSK) +#define HWIO_IPA_FLAVOR_6_INM(m) \ + in_dword_masked(HWIO_IPA_FLAVOR_6_ADDR, m) +#define HWIO_IPA_FLAVOR_6_DATA_SECTORS_BMSK 0x3f000000 +#define HWIO_IPA_FLAVOR_6_DATA_SECTORS_SHFT 0x18 +#define HWIO_IPA_FLAVOR_6_DATA_DESCRIPTOR_BUFFERS_BMSK 0xff0000 +#define HWIO_IPA_FLAVOR_6_DATA_DESCRIPTOR_BUFFERS_SHFT 0x10 +#define HWIO_IPA_FLAVOR_6_DATA_DESCRIPTOR_LISTS_BMSK 0x3f00 +#define HWIO_IPA_FLAVOR_6_DATA_DESCRIPTOR_LISTS_SHFT 0x8 +#define HWIO_IPA_FLAVOR_6_DPS_DMAR_NUM_BMSK 0xf0 +#define HWIO_IPA_FLAVOR_6_DPS_DMAR_NUM_SHFT 0x4 +#define HWIO_IPA_FLAVOR_6_HPS_DMAR_NUM_BMSK 0xf +#define HWIO_IPA_FLAVOR_6_HPS_DMAR_NUM_SHFT 0x0 + +#define HWIO_IPA_FLAVOR_7_ADDR (IPA_CFG_REG_BASE + 0x0000001c) +#define HWIO_IPA_FLAVOR_7_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000001c) +#define HWIO_IPA_FLAVOR_7_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000001c) +#define HWIO_IPA_FLAVOR_7_RMSK 0x3fff03ff +#define HWIO_IPA_FLAVOR_7_ATTR 0x1 +#define HWIO_IPA_FLAVOR_7_IN \ + in_dword_masked(HWIO_IPA_FLAVOR_7_ADDR, HWIO_IPA_FLAVOR_7_RMSK) +#define HWIO_IPA_FLAVOR_7_INM(m) \ + in_dword_masked(HWIO_IPA_FLAVOR_7_ADDR, m) +#define HWIO_IPA_FLAVOR_7_COAL_VP_NUM_BMSK 0x3c000000 +#define HWIO_IPA_FLAVOR_7_COAL_VP_NUM_SHFT 0x1a +#define HWIO_IPA_FLAVOR_7_AOS_ENTRY_NUM_BMSK 0x3ff0000 +#define HWIO_IPA_FLAVOR_7_AOS_ENTRY_NUM_SHFT 0x10 +#define HWIO_IPA_FLAVOR_7_TLV_ENTRY_NUM_BMSK 0x3ff +#define HWIO_IPA_FLAVOR_7_TLV_ENTRY_NUM_SHFT 0x0 + +#define HWIO_IPA_FLAVOR_8_ADDR (IPA_CFG_REG_BASE + 0x00000020) +#define HWIO_IPA_FLAVOR_8_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000020) +#define HWIO_IPA_FLAVOR_8_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000020) +#define HWIO_IPA_FLAVOR_8_RMSK 0xff +#define HWIO_IPA_FLAVOR_8_ATTR 0x1 +#define HWIO_IPA_FLAVOR_8_IN \ + in_dword_masked(HWIO_IPA_FLAVOR_8_ADDR, HWIO_IPA_FLAVOR_8_RMSK) +#define HWIO_IPA_FLAVOR_8_INM(m) \ + in_dword_masked(HWIO_IPA_FLAVOR_8_ADDR, m) +#define HWIO_IPA_FLAVOR_8_MULTI_DRBIP_DCPH_ENGINE_NUM_BMSK 0xf0 +#define HWIO_IPA_FLAVOR_8_MULTI_DRBIP_DCPH_ENGINE_NUM_SHFT 0x4 +#define HWIO_IPA_FLAVOR_8_MULTI_DRBIP_DMAR_ENGINE_NUM_BMSK 0xf +#define HWIO_IPA_FLAVOR_8_MULTI_DRBIP_DMAR_ENGINE_NUM_SHFT 0x0 + +#define HWIO_IPA_COMP_HW_VERSION_ADDR (IPA_CFG_REG_BASE + 0x00000024) +#define HWIO_IPA_COMP_HW_VERSION_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000024) +#define HWIO_IPA_COMP_HW_VERSION_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000024) +#define HWIO_IPA_COMP_HW_VERSION_RMSK 0xffffffff +#define HWIO_IPA_COMP_HW_VERSION_ATTR 0x1 +#define HWIO_IPA_COMP_HW_VERSION_IN \ + in_dword_masked(HWIO_IPA_COMP_HW_VERSION_ADDR, HWIO_IPA_COMP_HW_VERSION_RMSK) +#define HWIO_IPA_COMP_HW_VERSION_INM(m) \ + in_dword_masked(HWIO_IPA_COMP_HW_VERSION_ADDR, m) +#define HWIO_IPA_COMP_HW_VERSION_MAJOR_BMSK 0xf0000000 +#define HWIO_IPA_COMP_HW_VERSION_MAJOR_SHFT 0x1c +#define HWIO_IPA_COMP_HW_VERSION_MINOR_BMSK 0xfff0000 +#define HWIO_IPA_COMP_HW_VERSION_MINOR_SHFT 0x10 +#define HWIO_IPA_COMP_HW_VERSION_STEP_BMSK 0xffff +#define HWIO_IPA_COMP_HW_VERSION_STEP_SHFT 0x0 + +#define HWIO_IPA_VERSION_ADDR (IPA_CFG_REG_BASE + 0x00000028) +#define HWIO_IPA_VERSION_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000028) +#define HWIO_IPA_VERSION_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000028) +#define HWIO_IPA_VERSION_RMSK 0xffffffff +#define HWIO_IPA_VERSION_ATTR 0x1 +#define HWIO_IPA_VERSION_IN \ + in_dword_masked(HWIO_IPA_VERSION_ADDR, HWIO_IPA_VERSION_RMSK) +#define HWIO_IPA_VERSION_INM(m) \ + in_dword_masked(HWIO_IPA_VERSION_ADDR, m) +#define HWIO_IPA_VERSION_IPA_R_REV_BMSK 0xffffffff +#define HWIO_IPA_VERSION_IPA_R_REV_SHFT 0x0 + +#define HWIO_IPA_COMP_CFG_ADDR (IPA_CFG_REG_BASE + 0x0000002c) +#define HWIO_IPA_COMP_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000002c) +#define HWIO_IPA_COMP_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000002c) +#define HWIO_IPA_COMP_CFG_RMSK 0xcffbffef +#define HWIO_IPA_COMP_CFG_ATTR 0x3 +#define HWIO_IPA_COMP_CFG_IN \ + in_dword_masked(HWIO_IPA_COMP_CFG_ADDR, HWIO_IPA_COMP_CFG_RMSK) +#define HWIO_IPA_COMP_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_COMP_CFG_ADDR, m) +#define HWIO_IPA_COMP_CFG_OUT(v) \ + out_dword(HWIO_IPA_COMP_CFG_ADDR,v) +#define HWIO_IPA_COMP_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_COMP_CFG_ADDR,m,v,HWIO_IPA_COMP_CFG_IN) +#define HWIO_IPA_COMP_CFG_GEN_QMB_0_DYNAMIC_ASIZE_BMSK 0x80000000 +#define HWIO_IPA_COMP_CFG_GEN_QMB_0_DYNAMIC_ASIZE_SHFT 0x1f +#define HWIO_IPA_COMP_CFG_GEN_QMB_1_DYNAMIC_ASIZE_BMSK 0x40000000 +#define HWIO_IPA_COMP_CFG_GEN_QMB_1_DYNAMIC_ASIZE_SHFT 0x1e +#define HWIO_IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_BMSK 0xfc00000 +#define HWIO_IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_SHFT 0x16 +#define HWIO_IPA_COMP_CFG_GSI_IF_OUT_OF_BUF_STOP_RESET_MASK_ENABLE_BMSK 0x200000 +#define HWIO_IPA_COMP_CFG_GSI_IF_OUT_OF_BUF_STOP_RESET_MASK_ENABLE_SHFT 0x15 +#define HWIO_IPA_COMP_CFG_GENQMB_AOOOWR_BMSK 0x100000 +#define HWIO_IPA_COMP_CFG_GENQMB_AOOOWR_SHFT 0x14 +#define HWIO_IPA_COMP_CFG_QMB_RAM_RD_CACHE_DISABLE_BMSK 0x80000 +#define HWIO_IPA_COMP_CFG_QMB_RAM_RD_CACHE_DISABLE_SHFT 0x13 +#define HWIO_IPA_COMP_CFG_IPA_FULL_FLUSH_WAIT_RSC_CLOSURE_EN_BMSK 0x20000 +#define HWIO_IPA_COMP_CFG_IPA_FULL_FLUSH_WAIT_RSC_CLOSURE_EN_SHFT 0x11 +#define HWIO_IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_GLOBAL_EN_BMSK 0x10000 +#define HWIO_IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_GLOBAL_EN_SHFT 0x10 +#define HWIO_IPA_COMP_CFG_GSI_MULTI_AXI_MASTERS_DIS_BMSK 0x8000 +#define HWIO_IPA_COMP_CFG_GSI_MULTI_AXI_MASTERS_DIS_SHFT 0xf +#define HWIO_IPA_COMP_CFG_GSI_SNOC_CNOC_LOOP_PROTECTION_DISABLE_BMSK 0x4000 +#define HWIO_IPA_COMP_CFG_GSI_SNOC_CNOC_LOOP_PROTECTION_DISABLE_SHFT 0xe +#define HWIO_IPA_COMP_CFG_GEN_QMB_0_SNOC_CNOC_LOOP_PROTECTION_DISABLE_BMSK 0x2000 +#define HWIO_IPA_COMP_CFG_GEN_QMB_0_SNOC_CNOC_LOOP_PROTECTION_DISABLE_SHFT 0xd +#define HWIO_IPA_COMP_CFG_GEN_QMB_1_MULTI_INORDER_WR_DIS_BMSK 0x1000 +#define HWIO_IPA_COMP_CFG_GEN_QMB_1_MULTI_INORDER_WR_DIS_SHFT 0xc +#define HWIO_IPA_COMP_CFG_GEN_QMB_0_MULTI_INORDER_WR_DIS_BMSK 0x800 +#define HWIO_IPA_COMP_CFG_GEN_QMB_0_MULTI_INORDER_WR_DIS_SHFT 0xb +#define HWIO_IPA_COMP_CFG_GEN_QMB_1_MULTI_INORDER_RD_DIS_BMSK 0x400 +#define HWIO_IPA_COMP_CFG_GEN_QMB_1_MULTI_INORDER_RD_DIS_SHFT 0xa +#define HWIO_IPA_COMP_CFG_GEN_QMB_0_MULTI_INORDER_RD_DIS_BMSK 0x200 +#define HWIO_IPA_COMP_CFG_GEN_QMB_0_MULTI_INORDER_RD_DIS_SHFT 0x9 +#define HWIO_IPA_COMP_CFG_GSI_MULTI_INORDER_WR_DIS_BMSK 0x100 +#define HWIO_IPA_COMP_CFG_GSI_MULTI_INORDER_WR_DIS_SHFT 0x8 +#define HWIO_IPA_COMP_CFG_GSI_MULTI_INORDER_RD_DIS_BMSK 0x80 +#define HWIO_IPA_COMP_CFG_GSI_MULTI_INORDER_RD_DIS_SHFT 0x7 +#define HWIO_IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_PROD_EN_BMSK 0x40 +#define HWIO_IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_PROD_EN_SHFT 0x6 +#define HWIO_IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_CONS_EN_BMSK 0x20 +#define HWIO_IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_CONS_EN_SHFT 0x5 +#define HWIO_IPA_COMP_CFG_GEN_QMB_1_SNOC_BYPASS_DIS_BMSK 0x8 +#define HWIO_IPA_COMP_CFG_GEN_QMB_1_SNOC_BYPASS_DIS_SHFT 0x3 +#define HWIO_IPA_COMP_CFG_GEN_QMB_0_SNOC_BYPASS_DIS_BMSK 0x4 +#define HWIO_IPA_COMP_CFG_GEN_QMB_0_SNOC_BYPASS_DIS_SHFT 0x2 +#define HWIO_IPA_COMP_CFG_GSI_SNOC_BYPASS_DIS_BMSK 0x2 +#define HWIO_IPA_COMP_CFG_GSI_SNOC_BYPASS_DIS_SHFT 0x1 +#define HWIO_IPA_COMP_CFG_RAM_ARB_PRIORITY_CLIENT_SAMP_FIX_DISABLE_BMSK 0x1 +#define HWIO_IPA_COMP_CFG_RAM_ARB_PRIORITY_CLIENT_SAMP_FIX_DISABLE_SHFT 0x0 + +#define HWIO_IPA_CLKON_CFG_1_ADDR (IPA_CFG_REG_BASE + 0x00000030) +#define HWIO_IPA_CLKON_CFG_1_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000030) +#define HWIO_IPA_CLKON_CFG_1_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000030) +#define HWIO_IPA_CLKON_CFG_1_RMSK 0x1 +#define HWIO_IPA_CLKON_CFG_1_ATTR 0x3 +#define HWIO_IPA_CLKON_CFG_1_IN \ + in_dword_masked(HWIO_IPA_CLKON_CFG_1_ADDR, HWIO_IPA_CLKON_CFG_1_RMSK) +#define HWIO_IPA_CLKON_CFG_1_INM(m) \ + in_dword_masked(HWIO_IPA_CLKON_CFG_1_ADDR, m) +#define HWIO_IPA_CLKON_CFG_1_OUT(v) \ + out_dword(HWIO_IPA_CLKON_CFG_1_ADDR,v) +#define HWIO_IPA_CLKON_CFG_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_CLKON_CFG_1_ADDR,m,v,HWIO_IPA_CLKON_CFG_1_IN) +#define HWIO_IPA_CLKON_CFG_1_CGC_OPEN_IPA_CORE_CLK_PHASE_BMSK 0x1 +#define HWIO_IPA_CLKON_CFG_1_CGC_OPEN_IPA_CORE_CLK_PHASE_SHFT 0x0 + +#define HWIO_IPA_CLKON_CFG_ADDR (IPA_CFG_REG_BASE + 0x00000034) +#define HWIO_IPA_CLKON_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000034) +#define HWIO_IPA_CLKON_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000034) +#define HWIO_IPA_CLKON_CFG_RMSK 0xfffdffff +#define HWIO_IPA_CLKON_CFG_ATTR 0x3 +#define HWIO_IPA_CLKON_CFG_IN \ + in_dword_masked(HWIO_IPA_CLKON_CFG_ADDR, HWIO_IPA_CLKON_CFG_RMSK) +#define HWIO_IPA_CLKON_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_CLKON_CFG_ADDR, m) +#define HWIO_IPA_CLKON_CFG_OUT(v) \ + out_dword(HWIO_IPA_CLKON_CFG_ADDR,v) +#define HWIO_IPA_CLKON_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_CLKON_CFG_ADDR,m,v,HWIO_IPA_CLKON_CFG_IN) +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_DRBIP_BMSK 0x80000000 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_DRBIP_SHFT 0x1f +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_DPL_FIFO_BMSK 0x40000000 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_DPL_FIFO_SHFT 0x1e +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_GLOBAL_2X_CLK_BMSK 0x20000000 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_GLOBAL_2X_CLK_SHFT 0x1d +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_GLOBAL_BMSK 0x10000000 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_GLOBAL_SHFT 0x1c +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_GSI_IF_BMSK 0x8000000 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_GSI_IF_SHFT 0x1b +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_WEIGHT_ARB_BMSK 0x4000000 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_WEIGHT_ARB_SHFT 0x1a +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_QMB_BMSK 0x2000000 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_QMB_SHFT 0x19 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_RAM_SLAVEWAY_BMSK 0x1000000 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_RAM_SLAVEWAY_SHFT 0x18 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_AGGR_WRAPPER_BMSK 0x800000 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_AGGR_WRAPPER_SHFT 0x17 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_QSB2AXI_CMDQ_L_BMSK 0x400000 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_QSB2AXI_CMDQ_L_SHFT 0x16 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_FNR_BMSK 0x200000 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_FNR_SHFT 0x15 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_TX_1_BMSK 0x100000 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_TX_1_SHFT 0x14 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_TX_0_BMSK 0x80000 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_TX_0_SHFT 0x13 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_NTF_TX_CMDQS_BMSK 0x40000 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_NTF_TX_CMDQS_SHFT 0x12 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_H_DCPH_BMSK 0x10000 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_H_DCPH_SHFT 0x10 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_D_DCPH_BMSK 0x8000 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_D_DCPH_SHFT 0xf +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_ACK_MNGR_BMSK 0x4000 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_ACK_MNGR_SHFT 0xe +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_CTX_HANDLER_BMSK 0x2000 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_CTX_HANDLER_SHFT 0xd +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_RSRC_MNGR_BMSK 0x1000 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_RSRC_MNGR_SHFT 0xc +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_DPS_TX_CMDQS_BMSK 0x800 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_DPS_TX_CMDQS_SHFT 0xb +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_HPS_DPS_CMDQS_BMSK 0x400 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_HPS_DPS_CMDQS_SHFT 0xa +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_RX_HPS_CMDQS_BMSK 0x200 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_RX_HPS_CMDQS_SHFT 0x9 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_DPS_BMSK 0x100 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_DPS_SHFT 0x8 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_HPS_BMSK 0x80 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_HPS_SHFT 0x7 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_FTCH_DPS_BMSK 0x40 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_FTCH_DPS_SHFT 0x6 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_FTCH_HPS_BMSK 0x20 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_FTCH_HPS_SHFT 0x5 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_RAM_ARB_BMSK 0x10 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_RAM_ARB_SHFT 0x4 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_MISC_BMSK 0x8 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_MISC_SHFT 0x3 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_TX_WRAPPER_BMSK 0x4 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_TX_WRAPPER_SHFT 0x2 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_PROC_BMSK 0x2 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_PROC_SHFT 0x1 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_RX_BMSK 0x1 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_RX_SHFT 0x0 + +#define HWIO_IPA_ROUTE_ADDR (IPA_CFG_REG_BASE + 0x00000038) +#define HWIO_IPA_ROUTE_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000038) +#define HWIO_IPA_ROUTE_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000038) +#define HWIO_IPA_ROUTE_RMSK 0x1fffffff +#define HWIO_IPA_ROUTE_ATTR 0x3 +#define HWIO_IPA_ROUTE_IN \ + in_dword_masked(HWIO_IPA_ROUTE_ADDR, HWIO_IPA_ROUTE_RMSK) +#define HWIO_IPA_ROUTE_INM(m) \ + in_dword_masked(HWIO_IPA_ROUTE_ADDR, m) +#define HWIO_IPA_ROUTE_OUT(v) \ + out_dword(HWIO_IPA_ROUTE_ADDR,v) +#define HWIO_IPA_ROUTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_ROUTE_ADDR,m,v,HWIO_IPA_ROUTE_IN) +#define HWIO_IPA_ROUTE_ROUTE_DIS_BMSK 0x10000000 +#define HWIO_IPA_ROUTE_ROUTE_DIS_SHFT 0x1c +#define HWIO_IPA_ROUTE_ROUTE_DEF_RETAIN_HDR_BMSK 0x8000000 +#define HWIO_IPA_ROUTE_ROUTE_DEF_RETAIN_HDR_SHFT 0x1b +#define HWIO_IPA_ROUTE_ROUTE_DEF_HDR_TABLE_BMSK 0x4000000 +#define HWIO_IPA_ROUTE_ROUTE_DEF_HDR_TABLE_SHFT 0x1a +#define HWIO_IPA_ROUTE_ROUTE_DEF_HDR_OFST_BMSK 0x3ff0000 +#define HWIO_IPA_ROUTE_ROUTE_DEF_HDR_OFST_SHFT 0x10 +#define HWIO_IPA_ROUTE_ROUTE_FRAG_DEF_PIPE_BMSK 0xff00 +#define HWIO_IPA_ROUTE_ROUTE_FRAG_DEF_PIPE_SHFT 0x8 +#define HWIO_IPA_ROUTE_ROUTE_DEF_PIPE_BMSK 0xff +#define HWIO_IPA_ROUTE_ROUTE_DEF_PIPE_SHFT 0x0 + +#define HWIO_IPA_MASTER_PRIORITY_ADDR (IPA_CFG_REG_BASE + 0x0000003c) +#define HWIO_IPA_MASTER_PRIORITY_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000003c) +#define HWIO_IPA_MASTER_PRIORITY_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000003c) +#define HWIO_IPA_MASTER_PRIORITY_RMSK 0xf +#define HWIO_IPA_MASTER_PRIORITY_ATTR 0x3 +#define HWIO_IPA_MASTER_PRIORITY_IN \ + in_dword_masked(HWIO_IPA_MASTER_PRIORITY_ADDR, HWIO_IPA_MASTER_PRIORITY_RMSK) +#define HWIO_IPA_MASTER_PRIORITY_INM(m) \ + in_dword_masked(HWIO_IPA_MASTER_PRIORITY_ADDR, m) +#define HWIO_IPA_MASTER_PRIORITY_OUT(v) \ + out_dword(HWIO_IPA_MASTER_PRIORITY_ADDR,v) +#define HWIO_IPA_MASTER_PRIORITY_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_MASTER_PRIORITY_ADDR,m,v,HWIO_IPA_MASTER_PRIORITY_IN) +#define HWIO_IPA_MASTER_PRIORITY_QMB_1_RD_BMSK 0xc +#define HWIO_IPA_MASTER_PRIORITY_QMB_1_RD_SHFT 0x2 +#define HWIO_IPA_MASTER_PRIORITY_QMB_0_RD_BMSK 0x3 +#define HWIO_IPA_MASTER_PRIORITY_QMB_0_RD_SHFT 0x0 + +#define HWIO_IPA_SHARED_MEM_SIZE_ADDR (IPA_CFG_REG_BASE + 0x00000040) +#define HWIO_IPA_SHARED_MEM_SIZE_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000040) +#define HWIO_IPA_SHARED_MEM_SIZE_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000040) +#define HWIO_IPA_SHARED_MEM_SIZE_RMSK 0xffffffff +#define HWIO_IPA_SHARED_MEM_SIZE_ATTR 0x1 +#define HWIO_IPA_SHARED_MEM_SIZE_IN \ + in_dword_masked(HWIO_IPA_SHARED_MEM_SIZE_ADDR, HWIO_IPA_SHARED_MEM_SIZE_RMSK) +#define HWIO_IPA_SHARED_MEM_SIZE_INM(m) \ + in_dword_masked(HWIO_IPA_SHARED_MEM_SIZE_ADDR, m) +#define HWIO_IPA_SHARED_MEM_SIZE_SHARED_MEM_BADDR_BMSK 0xffff0000 +#define HWIO_IPA_SHARED_MEM_SIZE_SHARED_MEM_BADDR_SHFT 0x10 +#define HWIO_IPA_SHARED_MEM_SIZE_SHARED_MEM_SIZE_BMSK 0xffff +#define HWIO_IPA_SHARED_MEM_SIZE_SHARED_MEM_SIZE_SHFT 0x0 + +#define HWIO_IPA_NAT_TIMER_ADDR (IPA_CFG_REG_BASE + 0x00000048) +#define HWIO_IPA_NAT_TIMER_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000048) +#define HWIO_IPA_NAT_TIMER_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000048) +#define HWIO_IPA_NAT_TIMER_RMSK 0xffffff +#define HWIO_IPA_NAT_TIMER_ATTR 0x1 +#define HWIO_IPA_NAT_TIMER_IN \ + in_dword_masked(HWIO_IPA_NAT_TIMER_ADDR, HWIO_IPA_NAT_TIMER_RMSK) +#define HWIO_IPA_NAT_TIMER_INM(m) \ + in_dword_masked(HWIO_IPA_NAT_TIMER_ADDR, m) +#define HWIO_IPA_NAT_TIMER_NAT_TIMER_BMSK 0xffffff +#define HWIO_IPA_NAT_TIMER_NAT_TIMER_SHFT 0x0 + +#define HWIO_IPA_TAG_TIMER_ADDR (IPA_CFG_REG_BASE + 0x00000044) +#define HWIO_IPA_TAG_TIMER_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000044) +#define HWIO_IPA_TAG_TIMER_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000044) +#define HWIO_IPA_TAG_TIMER_RMSK 0xffffff +#define HWIO_IPA_TAG_TIMER_ATTR 0x1 +#define HWIO_IPA_TAG_TIMER_IN \ + in_dword_masked(HWIO_IPA_TAG_TIMER_ADDR, HWIO_IPA_TAG_TIMER_RMSK) +#define HWIO_IPA_TAG_TIMER_INM(m) \ + in_dword_masked(HWIO_IPA_TAG_TIMER_ADDR, m) +#define HWIO_IPA_TAG_TIMER_TAG_TIMER_BMSK 0xffffff +#define HWIO_IPA_TAG_TIMER_TAG_TIMER_SHFT 0x0 + +#define HWIO_IPA_FRAG_RULES_CLR_ADDR (IPA_CFG_REG_BASE + 0x0000004c) +#define HWIO_IPA_FRAG_RULES_CLR_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000004c) +#define HWIO_IPA_FRAG_RULES_CLR_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000004c) +#define HWIO_IPA_FRAG_RULES_CLR_RMSK 0x1 +#define HWIO_IPA_FRAG_RULES_CLR_ATTR 0x2 +#define HWIO_IPA_FRAG_RULES_CLR_OUT(v) \ + out_dword(HWIO_IPA_FRAG_RULES_CLR_ADDR,v) +#define HWIO_IPA_FRAG_RULES_CLR_CLR_BMSK 0x1 +#define HWIO_IPA_FRAG_RULES_CLR_CLR_SHFT 0x0 + +#define HWIO_IPA_PROC_IPH_CFG_ADDR (IPA_CFG_REG_BASE + 0x00000050) +#define HWIO_IPA_PROC_IPH_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000050) +#define HWIO_IPA_PROC_IPH_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000050) +#define HWIO_IPA_PROC_IPH_CFG_RMSK 0x1ff0f00 +#define HWIO_IPA_PROC_IPH_CFG_ATTR 0x3 +#define HWIO_IPA_PROC_IPH_CFG_IN \ + in_dword_masked(HWIO_IPA_PROC_IPH_CFG_ADDR, HWIO_IPA_PROC_IPH_CFG_RMSK) +#define HWIO_IPA_PROC_IPH_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_PROC_IPH_CFG_ADDR, m) +#define HWIO_IPA_PROC_IPH_CFG_OUT(v) \ + out_dword(HWIO_IPA_PROC_IPH_CFG_ADDR,v) +#define HWIO_IPA_PROC_IPH_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_PROC_IPH_CFG_ADDR,m,v,HWIO_IPA_PROC_IPH_CFG_IN) +#define HWIO_IPA_PROC_IPH_CFG_D_DCPH_MULTI_ENGINE_DISABLE_BMSK 0x1000000 +#define HWIO_IPA_PROC_IPH_CFG_D_DCPH_MULTI_ENGINE_DISABLE_SHFT 0x18 +#define HWIO_IPA_PROC_IPH_CFG_IPH_PKT_PARSER_PROTOCOL_STOP_VALUE_BMSK 0xff0000 +#define HWIO_IPA_PROC_IPH_CFG_IPH_PKT_PARSER_PROTOCOL_STOP_VALUE_SHFT 0x10 +#define HWIO_IPA_PROC_IPH_CFG_IPH_PKT_PARSER_IHL_TO_2ND_FRAG_EN_BMSK 0x800 +#define HWIO_IPA_PROC_IPH_CFG_IPH_PKT_PARSER_IHL_TO_2ND_FRAG_EN_SHFT 0xb +#define HWIO_IPA_PROC_IPH_CFG_IPH_PKT_PARSER_PROTOCOL_STOP_DEST_BMSK 0x400 +#define HWIO_IPA_PROC_IPH_CFG_IPH_PKT_PARSER_PROTOCOL_STOP_DEST_SHFT 0xa +#define HWIO_IPA_PROC_IPH_CFG_IPH_PKT_PARSER_PROTOCOL_STOP_HOP_BMSK 0x200 +#define HWIO_IPA_PROC_IPH_CFG_IPH_PKT_PARSER_PROTOCOL_STOP_HOP_SHFT 0x9 +#define HWIO_IPA_PROC_IPH_CFG_IPH_PKT_PARSER_PROTOCOL_STOP_ENABLE_BMSK 0x100 +#define HWIO_IPA_PROC_IPH_CFG_IPH_PKT_PARSER_PROTOCOL_STOP_ENABLE_SHFT 0x8 + +#define HWIO_IPA_QSB_MAX_WRITES_ADDR (IPA_CFG_REG_BASE + 0x00000054) +#define HWIO_IPA_QSB_MAX_WRITES_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000054) +#define HWIO_IPA_QSB_MAX_WRITES_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000054) +#define HWIO_IPA_QSB_MAX_WRITES_RMSK 0xff +#define HWIO_IPA_QSB_MAX_WRITES_ATTR 0x3 +#define HWIO_IPA_QSB_MAX_WRITES_IN \ + in_dword_masked(HWIO_IPA_QSB_MAX_WRITES_ADDR, HWIO_IPA_QSB_MAX_WRITES_RMSK) +#define HWIO_IPA_QSB_MAX_WRITES_INM(m) \ + in_dword_masked(HWIO_IPA_QSB_MAX_WRITES_ADDR, m) +#define HWIO_IPA_QSB_MAX_WRITES_OUT(v) \ + out_dword(HWIO_IPA_QSB_MAX_WRITES_ADDR,v) +#define HWIO_IPA_QSB_MAX_WRITES_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_QSB_MAX_WRITES_ADDR,m,v,HWIO_IPA_QSB_MAX_WRITES_IN) +#define HWIO_IPA_QSB_MAX_WRITES_GEN_QMB_1_MAX_WRITES_BMSK 0xf0 +#define HWIO_IPA_QSB_MAX_WRITES_GEN_QMB_1_MAX_WRITES_SHFT 0x4 +#define HWIO_IPA_QSB_MAX_WRITES_GEN_QMB_0_MAX_WRITES_BMSK 0xf +#define HWIO_IPA_QSB_MAX_WRITES_GEN_QMB_0_MAX_WRITES_SHFT 0x0 + +#define HWIO_IPA_QSB_MAX_READS_ADDR (IPA_CFG_REG_BASE + 0x00000058) +#define HWIO_IPA_QSB_MAX_READS_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000058) +#define HWIO_IPA_QSB_MAX_READS_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000058) +#define HWIO_IPA_QSB_MAX_READS_RMSK 0xffff00ff +#define HWIO_IPA_QSB_MAX_READS_ATTR 0x3 +#define HWIO_IPA_QSB_MAX_READS_IN \ + in_dword_masked(HWIO_IPA_QSB_MAX_READS_ADDR, HWIO_IPA_QSB_MAX_READS_RMSK) +#define HWIO_IPA_QSB_MAX_READS_INM(m) \ + in_dword_masked(HWIO_IPA_QSB_MAX_READS_ADDR, m) +#define HWIO_IPA_QSB_MAX_READS_OUT(v) \ + out_dword(HWIO_IPA_QSB_MAX_READS_ADDR,v) +#define HWIO_IPA_QSB_MAX_READS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_QSB_MAX_READS_ADDR,m,v,HWIO_IPA_QSB_MAX_READS_IN) +#define HWIO_IPA_QSB_MAX_READS_GEN_QMB_1_MAX_READ_BEATS_BMSK 0xff000000 +#define HWIO_IPA_QSB_MAX_READS_GEN_QMB_1_MAX_READ_BEATS_SHFT 0x18 +#define HWIO_IPA_QSB_MAX_READS_GEN_QMB_0_MAX_READ_BEATS_BMSK 0xff0000 +#define HWIO_IPA_QSB_MAX_READS_GEN_QMB_0_MAX_READ_BEATS_SHFT 0x10 +#define HWIO_IPA_QSB_MAX_READS_GEN_QMB_1_MAX_READS_BMSK 0xf0 +#define HWIO_IPA_QSB_MAX_READS_GEN_QMB_1_MAX_READS_SHFT 0x4 +#define HWIO_IPA_QSB_MAX_READS_GEN_QMB_0_MAX_READS_BMSK 0xf +#define HWIO_IPA_QSB_MAX_READS_GEN_QMB_0_MAX_READS_SHFT 0x0 + +#define HWIO_IPA_QSB_OUTSTANDING_COUNTER_ADDR (IPA_CFG_REG_BASE + 0x0000005c) +#define HWIO_IPA_QSB_OUTSTANDING_COUNTER_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000005c) +#define HWIO_IPA_QSB_OUTSTANDING_COUNTER_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000005c) +#define HWIO_IPA_QSB_OUTSTANDING_COUNTER_RMSK 0x1f1f1f1f +#define HWIO_IPA_QSB_OUTSTANDING_COUNTER_ATTR 0x1 +#define HWIO_IPA_QSB_OUTSTANDING_COUNTER_IN \ + in_dword_masked(HWIO_IPA_QSB_OUTSTANDING_COUNTER_ADDR, HWIO_IPA_QSB_OUTSTANDING_COUNTER_RMSK) +#define HWIO_IPA_QSB_OUTSTANDING_COUNTER_INM(m) \ + in_dword_masked(HWIO_IPA_QSB_OUTSTANDING_COUNTER_ADDR, m) +#define HWIO_IPA_QSB_OUTSTANDING_COUNTER_GEN_QMB_1_WRITES_CNT_BMSK 0x1f000000 +#define HWIO_IPA_QSB_OUTSTANDING_COUNTER_GEN_QMB_1_WRITES_CNT_SHFT 0x18 +#define HWIO_IPA_QSB_OUTSTANDING_COUNTER_GEN_QMB_0_WRITES_CNT_BMSK 0x1f0000 +#define HWIO_IPA_QSB_OUTSTANDING_COUNTER_GEN_QMB_0_WRITES_CNT_SHFT 0x10 +#define HWIO_IPA_QSB_OUTSTANDING_COUNTER_GEN_QMB_1_READS_CNT_BMSK 0x1f00 +#define HWIO_IPA_QSB_OUTSTANDING_COUNTER_GEN_QMB_1_READS_CNT_SHFT 0x8 +#define HWIO_IPA_QSB_OUTSTANDING_COUNTER_GEN_QMB_0_READS_CNT_BMSK 0x1f +#define HWIO_IPA_QSB_OUTSTANDING_COUNTER_GEN_QMB_0_READS_CNT_SHFT 0x0 + +#define HWIO_IPA_QSB_OUTSTANDING_BEATS_COUNTER_ADDR (IPA_CFG_REG_BASE + 0x00000060) +#define HWIO_IPA_QSB_OUTSTANDING_BEATS_COUNTER_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000060) +#define HWIO_IPA_QSB_OUTSTANDING_BEATS_COUNTER_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000060) +#define HWIO_IPA_QSB_OUTSTANDING_BEATS_COUNTER_RMSK 0xffff +#define HWIO_IPA_QSB_OUTSTANDING_BEATS_COUNTER_ATTR 0x1 +#define HWIO_IPA_QSB_OUTSTANDING_BEATS_COUNTER_IN \ + in_dword_masked(HWIO_IPA_QSB_OUTSTANDING_BEATS_COUNTER_ADDR, HWIO_IPA_QSB_OUTSTANDING_BEATS_COUNTER_RMSK) +#define HWIO_IPA_QSB_OUTSTANDING_BEATS_COUNTER_INM(m) \ + in_dword_masked(HWIO_IPA_QSB_OUTSTANDING_BEATS_COUNTER_ADDR, m) +#define HWIO_IPA_QSB_OUTSTANDING_BEATS_COUNTER_GEN_QMB_1_READ_BEATS_CNT_BMSK 0xff00 +#define HWIO_IPA_QSB_OUTSTANDING_BEATS_COUNTER_GEN_QMB_1_READ_BEATS_CNT_SHFT 0x8 +#define HWIO_IPA_QSB_OUTSTANDING_BEATS_COUNTER_GEN_QMB_0_READ_BEATS_CNT_BMSK 0xff +#define HWIO_IPA_QSB_OUTSTANDING_BEATS_COUNTER_GEN_QMB_0_READ_BEATS_CNT_SHFT 0x0 + +#define HWIO_IPA_DPL_TIMER_LSB_ADDR (IPA_CFG_REG_BASE + 0x00000064) +#define HWIO_IPA_DPL_TIMER_LSB_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000064) +#define HWIO_IPA_DPL_TIMER_LSB_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000064) +#define HWIO_IPA_DPL_TIMER_LSB_RMSK 0xffffffff +#define HWIO_IPA_DPL_TIMER_LSB_ATTR 0x3 +#define HWIO_IPA_DPL_TIMER_LSB_IN \ + in_dword_masked(HWIO_IPA_DPL_TIMER_LSB_ADDR, HWIO_IPA_DPL_TIMER_LSB_RMSK) +#define HWIO_IPA_DPL_TIMER_LSB_INM(m) \ + in_dword_masked(HWIO_IPA_DPL_TIMER_LSB_ADDR, m) +#define HWIO_IPA_DPL_TIMER_LSB_OUT(v) \ + out_dword(HWIO_IPA_DPL_TIMER_LSB_ADDR,v) +#define HWIO_IPA_DPL_TIMER_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_DPL_TIMER_LSB_ADDR,m,v,HWIO_IPA_DPL_TIMER_LSB_IN) +#define HWIO_IPA_DPL_TIMER_LSB_TOD_LSB_BMSK 0xffffffff +#define HWIO_IPA_DPL_TIMER_LSB_TOD_LSB_SHFT 0x0 + +#define HWIO_IPA_DPL_TIMER_MSB_ADDR (IPA_CFG_REG_BASE + 0x00000068) +#define HWIO_IPA_DPL_TIMER_MSB_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000068) +#define HWIO_IPA_DPL_TIMER_MSB_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000068) +#define HWIO_IPA_DPL_TIMER_MSB_RMSK 0xf800ffff +#define HWIO_IPA_DPL_TIMER_MSB_ATTR 0x3 +#define HWIO_IPA_DPL_TIMER_MSB_IN \ + in_dword_masked(HWIO_IPA_DPL_TIMER_MSB_ADDR, HWIO_IPA_DPL_TIMER_MSB_RMSK) +#define HWIO_IPA_DPL_TIMER_MSB_INM(m) \ + in_dword_masked(HWIO_IPA_DPL_TIMER_MSB_ADDR, m) +#define HWIO_IPA_DPL_TIMER_MSB_OUT(v) \ + out_dword(HWIO_IPA_DPL_TIMER_MSB_ADDR,v) +#define HWIO_IPA_DPL_TIMER_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_DPL_TIMER_MSB_ADDR,m,v,HWIO_IPA_DPL_TIMER_MSB_IN) +#define HWIO_IPA_DPL_TIMER_MSB_TIMER_EN_BMSK 0x80000000 +#define HWIO_IPA_DPL_TIMER_MSB_TIMER_EN_SHFT 0x1f +#define HWIO_IPA_DPL_TIMER_MSB_GRAN_SEL_BMSK 0x78000000 +#define HWIO_IPA_DPL_TIMER_MSB_GRAN_SEL_SHFT 0x1b +#define HWIO_IPA_DPL_TIMER_MSB_TOD_MSB_BMSK 0xffff +#define HWIO_IPA_DPL_TIMER_MSB_TOD_MSB_SHFT 0x0 + +#define HWIO_IPA_STATE_RX_ACTIVE_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000070 + 0x4 * (n)) +#define HWIO_IPA_STATE_RX_ACTIVE_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000070 + 0x4 * (n)) +#define HWIO_IPA_STATE_RX_ACTIVE_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000070 + 0x4 * (n)) +#define HWIO_IPA_STATE_RX_ACTIVE_n_RMSK 0xffffffff +#define HWIO_IPA_STATE_RX_ACTIVE_n_MAXn 0 +#define HWIO_IPA_STATE_RX_ACTIVE_n_ATTR 0x1 +#define HWIO_IPA_STATE_RX_ACTIVE_n_INI(n) \ + in_dword_masked(HWIO_IPA_STATE_RX_ACTIVE_n_ADDR(n), HWIO_IPA_STATE_RX_ACTIVE_n_RMSK) +#define HWIO_IPA_STATE_RX_ACTIVE_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_STATE_RX_ACTIVE_n_ADDR(n), mask) +#define HWIO_IPA_STATE_RX_ACTIVE_n_ENDPOINTS_BMSK 0xffffffff +#define HWIO_IPA_STATE_RX_ACTIVE_n_ENDPOINTS_SHFT 0x0 + +#define HWIO_IPA_STATE_TX_WRAPPER_ADDR (IPA_CFG_REG_BASE + 0x00000090) +#define HWIO_IPA_STATE_TX_WRAPPER_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000090) +#define HWIO_IPA_STATE_TX_WRAPPER_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000090) +#define HWIO_IPA_STATE_TX_WRAPPER_RMSK 0xf00c001f +#define HWIO_IPA_STATE_TX_WRAPPER_ATTR 0x1 +#define HWIO_IPA_STATE_TX_WRAPPER_IN \ + in_dword_masked(HWIO_IPA_STATE_TX_WRAPPER_ADDR, HWIO_IPA_STATE_TX_WRAPPER_RMSK) +#define HWIO_IPA_STATE_TX_WRAPPER_INM(m) \ + in_dword_masked(HWIO_IPA_STATE_TX_WRAPPER_ADDR, m) +#define HWIO_IPA_STATE_TX_WRAPPER_COAL_SLAVE_OPEN_FRAME_BMSK 0xf0000000 +#define HWIO_IPA_STATE_TX_WRAPPER_COAL_SLAVE_OPEN_FRAME_SHFT 0x1c +#define HWIO_IPA_STATE_TX_WRAPPER_COAL_SLAVE_CTX_IDLE_BMSK 0x80000 +#define HWIO_IPA_STATE_TX_WRAPPER_COAL_SLAVE_CTX_IDLE_SHFT 0x13 +#define HWIO_IPA_STATE_TX_WRAPPER_COAL_SLAVE_IDLE_BMSK 0x40000 +#define HWIO_IPA_STATE_TX_WRAPPER_COAL_SLAVE_IDLE_SHFT 0x12 +#define HWIO_IPA_STATE_TX_WRAPPER_IPA_PROD_BRESP_EMPTY_BMSK 0x10 +#define HWIO_IPA_STATE_TX_WRAPPER_IPA_PROD_BRESP_EMPTY_SHFT 0x4 +#define HWIO_IPA_STATE_TX_WRAPPER_IPA_PROD_ACKMNGR_STATE_IDLE_BMSK 0x8 +#define HWIO_IPA_STATE_TX_WRAPPER_IPA_PROD_ACKMNGR_STATE_IDLE_SHFT 0x3 +#define HWIO_IPA_STATE_TX_WRAPPER_IPA_PROD_ACKMNGR_DB_EMPTY_BMSK 0x4 +#define HWIO_IPA_STATE_TX_WRAPPER_IPA_PROD_ACKMNGR_DB_EMPTY_SHFT 0x2 +#define HWIO_IPA_STATE_TX_WRAPPER_TX1_IDLE_BMSK 0x2 +#define HWIO_IPA_STATE_TX_WRAPPER_TX1_IDLE_SHFT 0x1 +#define HWIO_IPA_STATE_TX_WRAPPER_TX0_IDLE_BMSK 0x1 +#define HWIO_IPA_STATE_TX_WRAPPER_TX0_IDLE_SHFT 0x0 + +#define HWIO_IPA_STATE_TX0_ADDR (IPA_CFG_REG_BASE + 0x00000094) +#define HWIO_IPA_STATE_TX0_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000094) +#define HWIO_IPA_STATE_TX0_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000094) +#define HWIO_IPA_STATE_TX0_RMSK 0x7ffffff +#define HWIO_IPA_STATE_TX0_ATTR 0x1 +#define HWIO_IPA_STATE_TX0_IN \ + in_dword_masked(HWIO_IPA_STATE_TX0_ADDR, HWIO_IPA_STATE_TX0_RMSK) +#define HWIO_IPA_STATE_TX0_INM(m) \ + in_dword_masked(HWIO_IPA_STATE_TX0_ADDR, m) +#define HWIO_IPA_STATE_TX0_SUSPEND_REQ_EMPTY_BMSK 0x4000000 +#define HWIO_IPA_STATE_TX0_SUSPEND_REQ_EMPTY_SHFT 0x1a +#define HWIO_IPA_STATE_TX0_CS_SNIF_IDLE_BMSK 0x2000000 +#define HWIO_IPA_STATE_TX0_CS_SNIF_IDLE_SHFT 0x19 +#define HWIO_IPA_STATE_TX0_SUSPEND_EMPTY_BMSK 0x1000000 +#define HWIO_IPA_STATE_TX0_SUSPEND_EMPTY_SHFT 0x18 +#define HWIO_IPA_STATE_TX0_RSRCREL_IDLE_BMSK 0x800000 +#define HWIO_IPA_STATE_TX0_RSRCREL_IDLE_SHFT 0x17 +#define HWIO_IPA_STATE_TX0_HOLB_MASK_IDLE_BMSK 0x400000 +#define HWIO_IPA_STATE_TX0_HOLB_MASK_IDLE_SHFT 0x16 +#define HWIO_IPA_STATE_TX0_HOLB_IDLE_BMSK 0x200000 +#define HWIO_IPA_STATE_TX0_HOLB_IDLE_SHFT 0x15 +#define HWIO_IPA_STATE_TX0_ALIGNER_EMPTY_BMSK 0x100000 +#define HWIO_IPA_STATE_TX0_ALIGNER_EMPTY_SHFT 0x14 +#define HWIO_IPA_STATE_TX0_PF_EMPTY_BMSK 0x80000 +#define HWIO_IPA_STATE_TX0_PF_EMPTY_SHFT 0x13 +#define HWIO_IPA_STATE_TX0_PF_IDLE_BMSK 0x40000 +#define HWIO_IPA_STATE_TX0_PF_IDLE_SHFT 0x12 +#define HWIO_IPA_STATE_TX0_DMAW_LAST_OUTSD_IDLE_BMSK 0x20000 +#define HWIO_IPA_STATE_TX0_DMAW_LAST_OUTSD_IDLE_SHFT 0x11 +#define HWIO_IPA_STATE_TX0_DMAW_IDLE_BMSK 0x10000 +#define HWIO_IPA_STATE_TX0_DMAW_IDLE_SHFT 0x10 +#define HWIO_IPA_STATE_TX0_AR_IDLE_BMSK 0x8000 +#define HWIO_IPA_STATE_TX0_AR_IDLE_SHFT 0xf +#define HWIO_IPA_STATE_TX0_TX_CMD_BRESP_INJ_IDLE_BMSK 0x4000 +#define HWIO_IPA_STATE_TX0_TX_CMD_BRESP_INJ_IDLE_SHFT 0xe +#define HWIO_IPA_STATE_TX0_TX_CMD_BRESP_ALOC_IDLE_BMSK 0x2000 +#define HWIO_IPA_STATE_TX0_TX_CMD_BRESP_ALOC_IDLE_SHFT 0xd +#define HWIO_IPA_STATE_TX0_TX_CMD_SNIF_IDLE_BMSK 0x1000 +#define HWIO_IPA_STATE_TX0_TX_CMD_SNIF_IDLE_SHFT 0xc +#define HWIO_IPA_STATE_TX0_TX_CMD_TRNSEQ_IDLE_BMSK 0x800 +#define HWIO_IPA_STATE_TX0_TX_CMD_TRNSEQ_IDLE_SHFT 0xb +#define HWIO_IPA_STATE_TX0_TX_CMD_MAIN_IDLE_BMSK 0x400 +#define HWIO_IPA_STATE_TX0_TX_CMD_MAIN_IDLE_SHFT 0xa +#define HWIO_IPA_STATE_TX0_PA_PUB_CNT_EMPTY_BMSK 0x200 +#define HWIO_IPA_STATE_TX0_PA_PUB_CNT_EMPTY_SHFT 0x9 +#define HWIO_IPA_STATE_TX0_PA_RST_IDLE_BMSK 0x100 +#define HWIO_IPA_STATE_TX0_PA_RST_IDLE_SHFT 0x8 +#define HWIO_IPA_STATE_TX0_PA_CTX_IDLE_BMSK 0x80 +#define HWIO_IPA_STATE_TX0_PA_CTX_IDLE_SHFT 0x7 +#define HWIO_IPA_STATE_TX0_PA_IDLE_BMSK 0x40 +#define HWIO_IPA_STATE_TX0_PA_IDLE_SHFT 0x6 +#define HWIO_IPA_STATE_TX0_ARBIT_TYPE_BMSK 0x38 +#define HWIO_IPA_STATE_TX0_ARBIT_TYPE_SHFT 0x3 +#define HWIO_IPA_STATE_TX0_FLOPPED_ARBIT_TYPE_BMSK 0x7 +#define HWIO_IPA_STATE_TX0_FLOPPED_ARBIT_TYPE_SHFT 0x0 + +#define HWIO_IPA_STATE_TX1_ADDR (IPA_CFG_REG_BASE + 0x00000098) +#define HWIO_IPA_STATE_TX1_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000098) +#define HWIO_IPA_STATE_TX1_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000098) +#define HWIO_IPA_STATE_TX1_RMSK 0x7ffffff +#define HWIO_IPA_STATE_TX1_ATTR 0x1 +#define HWIO_IPA_STATE_TX1_IN \ + in_dword_masked(HWIO_IPA_STATE_TX1_ADDR, HWIO_IPA_STATE_TX1_RMSK) +#define HWIO_IPA_STATE_TX1_INM(m) \ + in_dword_masked(HWIO_IPA_STATE_TX1_ADDR, m) +#define HWIO_IPA_STATE_TX1_SUSPEND_REQ_EMPTY_BMSK 0x4000000 +#define HWIO_IPA_STATE_TX1_SUSPEND_REQ_EMPTY_SHFT 0x1a +#define HWIO_IPA_STATE_TX1_CS_SNIF_IDLE_BMSK 0x2000000 +#define HWIO_IPA_STATE_TX1_CS_SNIF_IDLE_SHFT 0x19 +#define HWIO_IPA_STATE_TX1_SUSPEND_EMPTY_BMSK 0x1000000 +#define HWIO_IPA_STATE_TX1_SUSPEND_EMPTY_SHFT 0x18 +#define HWIO_IPA_STATE_TX1_RSRCREL_IDLE_BMSK 0x800000 +#define HWIO_IPA_STATE_TX1_RSRCREL_IDLE_SHFT 0x17 +#define HWIO_IPA_STATE_TX1_HOLB_MASK_IDLE_BMSK 0x400000 +#define HWIO_IPA_STATE_TX1_HOLB_MASK_IDLE_SHFT 0x16 +#define HWIO_IPA_STATE_TX1_HOLB_IDLE_BMSK 0x200000 +#define HWIO_IPA_STATE_TX1_HOLB_IDLE_SHFT 0x15 +#define HWIO_IPA_STATE_TX1_ALIGNER_EMPTY_BMSK 0x100000 +#define HWIO_IPA_STATE_TX1_ALIGNER_EMPTY_SHFT 0x14 +#define HWIO_IPA_STATE_TX1_PF_EMPTY_BMSK 0x80000 +#define HWIO_IPA_STATE_TX1_PF_EMPTY_SHFT 0x13 +#define HWIO_IPA_STATE_TX1_PF_IDLE_BMSK 0x40000 +#define HWIO_IPA_STATE_TX1_PF_IDLE_SHFT 0x12 +#define HWIO_IPA_STATE_TX1_DMAW_LAST_OUTSD_IDLE_BMSK 0x20000 +#define HWIO_IPA_STATE_TX1_DMAW_LAST_OUTSD_IDLE_SHFT 0x11 +#define HWIO_IPA_STATE_TX1_DMAW_IDLE_BMSK 0x10000 +#define HWIO_IPA_STATE_TX1_DMAW_IDLE_SHFT 0x10 +#define HWIO_IPA_STATE_TX1_AR_IDLE_BMSK 0x8000 +#define HWIO_IPA_STATE_TX1_AR_IDLE_SHFT 0xf +#define HWIO_IPA_STATE_TX1_TX_CMD_BRESP_INJ_IDLE_BMSK 0x4000 +#define HWIO_IPA_STATE_TX1_TX_CMD_BRESP_INJ_IDLE_SHFT 0xe +#define HWIO_IPA_STATE_TX1_TX_CMD_BRESP_ALOC_IDLE_BMSK 0x2000 +#define HWIO_IPA_STATE_TX1_TX_CMD_BRESP_ALOC_IDLE_SHFT 0xd +#define HWIO_IPA_STATE_TX1_TX_CMD_SNIF_IDLE_BMSK 0x1000 +#define HWIO_IPA_STATE_TX1_TX_CMD_SNIF_IDLE_SHFT 0xc +#define HWIO_IPA_STATE_TX1_TX_CMD_TRNSEQ_IDLE_BMSK 0x800 +#define HWIO_IPA_STATE_TX1_TX_CMD_TRNSEQ_IDLE_SHFT 0xb +#define HWIO_IPA_STATE_TX1_TX_CMD_MAIN_IDLE_BMSK 0x400 +#define HWIO_IPA_STATE_TX1_TX_CMD_MAIN_IDLE_SHFT 0xa +#define HWIO_IPA_STATE_TX1_PA_PUB_CNT_EMPTY_BMSK 0x200 +#define HWIO_IPA_STATE_TX1_PA_PUB_CNT_EMPTY_SHFT 0x9 +#define HWIO_IPA_STATE_TX1_PA_RST_IDLE_BMSK 0x100 +#define HWIO_IPA_STATE_TX1_PA_RST_IDLE_SHFT 0x8 +#define HWIO_IPA_STATE_TX1_PA_CTX_IDLE_BMSK 0x80 +#define HWIO_IPA_STATE_TX1_PA_CTX_IDLE_SHFT 0x7 +#define HWIO_IPA_STATE_TX1_PA_IDLE_BMSK 0x40 +#define HWIO_IPA_STATE_TX1_PA_IDLE_SHFT 0x6 +#define HWIO_IPA_STATE_TX1_ARBIT_TYPE_BMSK 0x38 +#define HWIO_IPA_STATE_TX1_ARBIT_TYPE_SHFT 0x3 +#define HWIO_IPA_STATE_TX1_FLOPPED_ARBIT_TYPE_BMSK 0x7 +#define HWIO_IPA_STATE_TX1_FLOPPED_ARBIT_TYPE_SHFT 0x0 + +#define HWIO_IPA_STATE_TX0_MISC_ADDR (IPA_CFG_REG_BASE + 0x0000009c) +#define HWIO_IPA_STATE_TX0_MISC_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000009c) +#define HWIO_IPA_STATE_TX0_MISC_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000009c) +#define HWIO_IPA_STATE_TX0_MISC_RMSK 0x3fff +#define HWIO_IPA_STATE_TX0_MISC_ATTR 0x1 +#define HWIO_IPA_STATE_TX0_MISC_IN \ + in_dword_masked(HWIO_IPA_STATE_TX0_MISC_ADDR, HWIO_IPA_STATE_TX0_MISC_RMSK) +#define HWIO_IPA_STATE_TX0_MISC_INM(m) \ + in_dword_masked(HWIO_IPA_STATE_TX0_MISC_ADDR, m) +#define HWIO_IPA_STATE_TX0_MISC_LAST_CMD_PIPE_BMSK 0x3fc0 +#define HWIO_IPA_STATE_TX0_MISC_LAST_CMD_PIPE_SHFT 0x6 +#define HWIO_IPA_STATE_TX0_MISC_COAL_DIRECT_DMA_BMSK 0x20 +#define HWIO_IPA_STATE_TX0_MISC_COAL_DIRECT_DMA_SHFT 0x5 +#define HWIO_IPA_STATE_TX0_MISC_NLO_DIRECT_DMA_BMSK 0x10 +#define HWIO_IPA_STATE_TX0_MISC_NLO_DIRECT_DMA_SHFT 0x4 +#define HWIO_IPA_STATE_TX0_MISC_PKT_DROP_CNT_IDLE_BMSK 0x8 +#define HWIO_IPA_STATE_TX0_MISC_PKT_DROP_CNT_IDLE_SHFT 0x3 +#define HWIO_IPA_STATE_TX0_MISC_TRNSEQ_FORCE_VALID_BMSK 0x4 +#define HWIO_IPA_STATE_TX0_MISC_TRNSEQ_FORCE_VALID_SHFT 0x2 +#define HWIO_IPA_STATE_TX0_MISC_MBIM_DIRECT_DMA_BMSK 0x2 +#define HWIO_IPA_STATE_TX0_MISC_MBIM_DIRECT_DMA_SHFT 0x1 +#define HWIO_IPA_STATE_TX0_MISC_IPA_MBIM_PKT_FMS_IDLE_BMSK 0x1 +#define HWIO_IPA_STATE_TX0_MISC_IPA_MBIM_PKT_FMS_IDLE_SHFT 0x0 + +#define HWIO_IPA_STATE_TX1_MISC_ADDR (IPA_CFG_REG_BASE + 0x000000a0) +#define HWIO_IPA_STATE_TX1_MISC_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000a0) +#define HWIO_IPA_STATE_TX1_MISC_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000a0) +#define HWIO_IPA_STATE_TX1_MISC_RMSK 0x3fff +#define HWIO_IPA_STATE_TX1_MISC_ATTR 0x1 +#define HWIO_IPA_STATE_TX1_MISC_IN \ + in_dword_masked(HWIO_IPA_STATE_TX1_MISC_ADDR, HWIO_IPA_STATE_TX1_MISC_RMSK) +#define HWIO_IPA_STATE_TX1_MISC_INM(m) \ + in_dword_masked(HWIO_IPA_STATE_TX1_MISC_ADDR, m) +#define HWIO_IPA_STATE_TX1_MISC_LAST_CMD_PIPE_BMSK 0x3fc0 +#define HWIO_IPA_STATE_TX1_MISC_LAST_CMD_PIPE_SHFT 0x6 +#define HWIO_IPA_STATE_TX1_MISC_COAL_DIRECT_DMA_BMSK 0x20 +#define HWIO_IPA_STATE_TX1_MISC_COAL_DIRECT_DMA_SHFT 0x5 +#define HWIO_IPA_STATE_TX1_MISC_NLO_DIRECT_DMA_BMSK 0x10 +#define HWIO_IPA_STATE_TX1_MISC_NLO_DIRECT_DMA_SHFT 0x4 +#define HWIO_IPA_STATE_TX1_MISC_PKT_DROP_CNT_IDLE_BMSK 0x8 +#define HWIO_IPA_STATE_TX1_MISC_PKT_DROP_CNT_IDLE_SHFT 0x3 +#define HWIO_IPA_STATE_TX1_MISC_TRNSEQ_FORCE_VALID_BMSK 0x4 +#define HWIO_IPA_STATE_TX1_MISC_TRNSEQ_FORCE_VALID_SHFT 0x2 +#define HWIO_IPA_STATE_TX1_MISC_MBIM_DIRECT_DMA_BMSK 0x2 +#define HWIO_IPA_STATE_TX1_MISC_MBIM_DIRECT_DMA_SHFT 0x1 +#define HWIO_IPA_STATE_TX1_MISC_IPA_MBIM_PKT_FMS_IDLE_BMSK 0x1 +#define HWIO_IPA_STATE_TX1_MISC_IPA_MBIM_PKT_FMS_IDLE_SHFT 0x0 + +#define HWIO_IPA_STATE_FETCHER_ADDR (IPA_CFG_REG_BASE + 0x000000a4) +#define HWIO_IPA_STATE_FETCHER_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000a4) +#define HWIO_IPA_STATE_FETCHER_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000a4) +#define HWIO_IPA_STATE_FETCHER_RMSK 0xfffff +#define HWIO_IPA_STATE_FETCHER_ATTR 0x1 +#define HWIO_IPA_STATE_FETCHER_IN \ + in_dword_masked(HWIO_IPA_STATE_FETCHER_ADDR, HWIO_IPA_STATE_FETCHER_RMSK) +#define HWIO_IPA_STATE_FETCHER_INM(m) \ + in_dword_masked(HWIO_IPA_STATE_FETCHER_ADDR, m) +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_IMM_CMD_EXEC_STATE_IDLE_BMSK 0x80000 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_IMM_CMD_EXEC_STATE_IDLE_SHFT 0x13 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_DMAR_SLOT_STATE_IDLE_BMSK 0x7f000 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_DMAR_SLOT_STATE_IDLE_SHFT 0xc +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_DMAR_STATE_IDLE_BMSK 0xfe0 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_DMAR_STATE_IDLE_SHFT 0x5 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_FTCH_CMPLT_STATE_IDLE_BMSK 0x10 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_FTCH_CMPLT_STATE_IDLE_SHFT 0x4 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_FTCH_IMM_STATE_IDLE_BMSK 0x8 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_FTCH_IMM_STATE_IDLE_SHFT 0x3 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_FTCH_PKT_STATE_IDLE_BMSK 0x4 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_FTCH_PKT_STATE_IDLE_SHFT 0x2 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_FTCH_ALLOC_STATE_IDLE_BMSK 0x2 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_FTCH_ALLOC_STATE_IDLE_SHFT 0x1 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_FTCH_STATE_IDLE_BMSK 0x1 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_FTCH_STATE_IDLE_SHFT 0x0 + +#define HWIO_IPA_STATE_FETCHER_MASK_0_ADDR (IPA_CFG_REG_BASE + 0x000000a8) +#define HWIO_IPA_STATE_FETCHER_MASK_0_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000a8) +#define HWIO_IPA_STATE_FETCHER_MASK_0_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000a8) +#define HWIO_IPA_STATE_FETCHER_MASK_0_RMSK 0xffffffff +#define HWIO_IPA_STATE_FETCHER_MASK_0_ATTR 0x1 +#define HWIO_IPA_STATE_FETCHER_MASK_0_IN \ + in_dword_masked(HWIO_IPA_STATE_FETCHER_MASK_0_ADDR, HWIO_IPA_STATE_FETCHER_MASK_0_RMSK) +#define HWIO_IPA_STATE_FETCHER_MASK_0_INM(m) \ + in_dword_masked(HWIO_IPA_STATE_FETCHER_MASK_0_ADDR, m) +#define HWIO_IPA_STATE_FETCHER_MASK_0_MASK_QUEUE_NO_RESOURCES_HPS_DMAR_BMSK 0xff000000 +#define HWIO_IPA_STATE_FETCHER_MASK_0_MASK_QUEUE_NO_RESOURCES_HPS_DMAR_SHFT 0x18 +#define HWIO_IPA_STATE_FETCHER_MASK_0_MASK_QUEUE_NO_RESOURCES_CONTEXT_BMSK 0xff0000 +#define HWIO_IPA_STATE_FETCHER_MASK_0_MASK_QUEUE_NO_RESOURCES_CONTEXT_SHFT 0x10 +#define HWIO_IPA_STATE_FETCHER_MASK_0_MASK_QUEUE_IMM_EXEC_BMSK 0xff00 +#define HWIO_IPA_STATE_FETCHER_MASK_0_MASK_QUEUE_IMM_EXEC_SHFT 0x8 +#define HWIO_IPA_STATE_FETCHER_MASK_0_MASK_QUEUE_DMAR_USES_QUEUE_BMSK 0xff +#define HWIO_IPA_STATE_FETCHER_MASK_0_MASK_QUEUE_DMAR_USES_QUEUE_SHFT 0x0 + +#define HWIO_IPA_STATE_DFETCHER_ADDR (IPA_CFG_REG_BASE + 0x000000ac) +#define HWIO_IPA_STATE_DFETCHER_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000ac) +#define HWIO_IPA_STATE_DFETCHER_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000ac) +#define HWIO_IPA_STATE_DFETCHER_RMSK 0x7f07f3 +#define HWIO_IPA_STATE_DFETCHER_ATTR 0x1 +#define HWIO_IPA_STATE_DFETCHER_IN \ + in_dword_masked(HWIO_IPA_STATE_DFETCHER_ADDR, HWIO_IPA_STATE_DFETCHER_RMSK) +#define HWIO_IPA_STATE_DFETCHER_INM(m) \ + in_dword_masked(HWIO_IPA_STATE_DFETCHER_ADDR, m) +#define HWIO_IPA_STATE_DFETCHER_IPA_DPS_DMAR_SLOT_STATE_IDLE_BMSK 0x7f0000 +#define HWIO_IPA_STATE_DFETCHER_IPA_DPS_DMAR_SLOT_STATE_IDLE_SHFT 0x10 +#define HWIO_IPA_STATE_DFETCHER_IPA_DPS_DMAR_STATE_IDLE_BMSK 0x7f0 +#define HWIO_IPA_STATE_DFETCHER_IPA_DPS_DMAR_STATE_IDLE_SHFT 0x4 +#define HWIO_IPA_STATE_DFETCHER_IPA_DPS_FTCH_CMPLT_STATE_IDLE_BMSK 0x2 +#define HWIO_IPA_STATE_DFETCHER_IPA_DPS_FTCH_CMPLT_STATE_IDLE_SHFT 0x1 +#define HWIO_IPA_STATE_DFETCHER_IPA_DPS_FTCH_PKT_STATE_IDLE_BMSK 0x1 +#define HWIO_IPA_STATE_DFETCHER_IPA_DPS_FTCH_PKT_STATE_IDLE_SHFT 0x0 + +#define HWIO_IPA_STATE_ACL_ADDR (IPA_CFG_REG_BASE + 0x000000b0) +#define HWIO_IPA_STATE_ACL_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000b0) +#define HWIO_IPA_STATE_ACL_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000b0) +#define HWIO_IPA_STATE_ACL_RMSK 0x3ffcffff +#define HWIO_IPA_STATE_ACL_ATTR 0x1 +#define HWIO_IPA_STATE_ACL_IN \ + in_dword_masked(HWIO_IPA_STATE_ACL_ADDR, HWIO_IPA_STATE_ACL_RMSK) +#define HWIO_IPA_STATE_ACL_INM(m) \ + in_dword_masked(HWIO_IPA_STATE_ACL_ADDR, m) +#define HWIO_IPA_STATE_ACL_IPA_HPS_MULTI_DRBIP_ACTIVE_BMSK 0x20000000 +#define HWIO_IPA_STATE_ACL_IPA_HPS_MULTI_DRBIP_ACTIVE_SHFT 0x1d +#define HWIO_IPA_STATE_ACL_IPA_HPS_MULTI_DRBIP_EMPTY_BMSK 0x10000000 +#define HWIO_IPA_STATE_ACL_IPA_HPS_MULTI_DRBIP_EMPTY_SHFT 0x1c +#define HWIO_IPA_STATE_ACL_IPA_HPS_COAL_MASTER_ACTIVE_BMSK 0x8000000 +#define HWIO_IPA_STATE_ACL_IPA_HPS_COAL_MASTER_ACTIVE_SHFT 0x1b +#define HWIO_IPA_STATE_ACL_IPA_HPS_COAL_MASTER_EMPTY_BMSK 0x4000000 +#define HWIO_IPA_STATE_ACL_IPA_HPS_COAL_MASTER_EMPTY_SHFT 0x1a +#define HWIO_IPA_STATE_ACL_IPA_DPS_D_DCPH_2ND_ACTIVE_BMSK 0x2000000 +#define HWIO_IPA_STATE_ACL_IPA_DPS_D_DCPH_2ND_ACTIVE_SHFT 0x19 +#define HWIO_IPA_STATE_ACL_IPA_DPS_D_DCPH_2ND_EMPTY_BMSK 0x1000000 +#define HWIO_IPA_STATE_ACL_IPA_DPS_D_DCPH_2ND_EMPTY_SHFT 0x18 +#define HWIO_IPA_STATE_ACL_IPA_DPS_SEQUENCER_IDLE_BMSK 0x800000 +#define HWIO_IPA_STATE_ACL_IPA_DPS_SEQUENCER_IDLE_SHFT 0x17 +#define HWIO_IPA_STATE_ACL_IPA_HPS_SEQUENCER_IDLE_BMSK 0x400000 +#define HWIO_IPA_STATE_ACL_IPA_HPS_SEQUENCER_IDLE_SHFT 0x16 +#define HWIO_IPA_STATE_ACL_IPA_DPS_D_DCPH_2_ACTIVE_BMSK 0x200000 +#define HWIO_IPA_STATE_ACL_IPA_DPS_D_DCPH_2_ACTIVE_SHFT 0x15 +#define HWIO_IPA_STATE_ACL_IPA_DPS_D_DCPH_2_EMPTY_BMSK 0x100000 +#define HWIO_IPA_STATE_ACL_IPA_DPS_D_DCPH_2_EMPTY_SHFT 0x14 +#define HWIO_IPA_STATE_ACL_IPA_DPS_DISPATCHER_ACTIVE_BMSK 0x80000 +#define HWIO_IPA_STATE_ACL_IPA_DPS_DISPATCHER_ACTIVE_SHFT 0x13 +#define HWIO_IPA_STATE_ACL_IPA_DPS_DISPATCHER_EMPTY_BMSK 0x40000 +#define HWIO_IPA_STATE_ACL_IPA_DPS_DISPATCHER_EMPTY_SHFT 0x12 +#define HWIO_IPA_STATE_ACL_IPA_DPS_D_DCPH_ACTIVE_BMSK 0x8000 +#define HWIO_IPA_STATE_ACL_IPA_DPS_D_DCPH_ACTIVE_SHFT 0xf +#define HWIO_IPA_STATE_ACL_IPA_DPS_D_DCPH_EMPTY_BMSK 0x4000 +#define HWIO_IPA_STATE_ACL_IPA_DPS_D_DCPH_EMPTY_SHFT 0xe +#define HWIO_IPA_STATE_ACL_IPA_HPS_ENQUEUER_ACTIVE_BMSK 0x2000 +#define HWIO_IPA_STATE_ACL_IPA_HPS_ENQUEUER_ACTIVE_SHFT 0xd +#define HWIO_IPA_STATE_ACL_IPA_HPS_ENQUEUER_EMPTY_BMSK 0x1000 +#define HWIO_IPA_STATE_ACL_IPA_HPS_ENQUEUER_EMPTY_SHFT 0xc +#define HWIO_IPA_STATE_ACL_IPA_HPS_UCP_ACTIVE_BMSK 0x800 +#define HWIO_IPA_STATE_ACL_IPA_HPS_UCP_ACTIVE_SHFT 0xb +#define HWIO_IPA_STATE_ACL_IPA_HPS_UCP_EMPTY_BMSK 0x400 +#define HWIO_IPA_STATE_ACL_IPA_HPS_UCP_EMPTY_SHFT 0xa +#define HWIO_IPA_STATE_ACL_IPA_HPS_HDRI_ACTIVE_BMSK 0x200 +#define HWIO_IPA_STATE_ACL_IPA_HPS_HDRI_ACTIVE_SHFT 0x9 +#define HWIO_IPA_STATE_ACL_IPA_HPS_HDRI_EMPTY_BMSK 0x100 +#define HWIO_IPA_STATE_ACL_IPA_HPS_HDRI_EMPTY_SHFT 0x8 +#define HWIO_IPA_STATE_ACL_IPA_HPS_ROUTER_ACTIVE_BMSK 0x80 +#define HWIO_IPA_STATE_ACL_IPA_HPS_ROUTER_ACTIVE_SHFT 0x7 +#define HWIO_IPA_STATE_ACL_IPA_HPS_ROUTER_EMPTY_BMSK 0x40 +#define HWIO_IPA_STATE_ACL_IPA_HPS_ROUTER_EMPTY_SHFT 0x6 +#define HWIO_IPA_STATE_ACL_IPA_HPS_FILTER_NAT_ACTIVE_BMSK 0x20 +#define HWIO_IPA_STATE_ACL_IPA_HPS_FILTER_NAT_ACTIVE_SHFT 0x5 +#define HWIO_IPA_STATE_ACL_IPA_HPS_FILTER_NAT_EMPTY_BMSK 0x10 +#define HWIO_IPA_STATE_ACL_IPA_HPS_FILTER_NAT_EMPTY_SHFT 0x4 +#define HWIO_IPA_STATE_ACL_IPA_HPS_PKT_PARSER_ACTIVE_BMSK 0x8 +#define HWIO_IPA_STATE_ACL_IPA_HPS_PKT_PARSER_ACTIVE_SHFT 0x3 +#define HWIO_IPA_STATE_ACL_IPA_HPS_PKT_PARSER_EMPTY_BMSK 0x4 +#define HWIO_IPA_STATE_ACL_IPA_HPS_PKT_PARSER_EMPTY_SHFT 0x2 +#define HWIO_IPA_STATE_ACL_IPA_HPS_H_DCPH_ACTIVE_BMSK 0x2 +#define HWIO_IPA_STATE_ACL_IPA_HPS_H_DCPH_ACTIVE_SHFT 0x1 +#define HWIO_IPA_STATE_ACL_IPA_HPS_H_DCPH_EMPTY_BMSK 0x1 +#define HWIO_IPA_STATE_ACL_IPA_HPS_H_DCPH_EMPTY_SHFT 0x0 + +#define HWIO_IPA_STATE_ADDR (IPA_CFG_REG_BASE + 0x000000b4) +#define HWIO_IPA_STATE_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000b4) +#define HWIO_IPA_STATE_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000b4) +#define HWIO_IPA_STATE_RMSK 0xffffffff +#define HWIO_IPA_STATE_ATTR 0x1 +#define HWIO_IPA_STATE_IN \ + in_dword_masked(HWIO_IPA_STATE_ADDR, HWIO_IPA_STATE_RMSK) +#define HWIO_IPA_STATE_INM(m) \ + in_dword_masked(HWIO_IPA_STATE_ADDR, m) +#define HWIO_IPA_STATE_IPA_UC_RX_HND_CMDQ_EMPTY_BMSK 0x80000000 +#define HWIO_IPA_STATE_IPA_UC_RX_HND_CMDQ_EMPTY_SHFT 0x1f +#define HWIO_IPA_STATE_IPA_DPS_TX_EMPTY_BMSK 0x40000000 +#define HWIO_IPA_STATE_IPA_DPS_TX_EMPTY_SHFT 0x1e +#define HWIO_IPA_STATE_IPA_HPS_DPS_EMPTY_BMSK 0x20000000 +#define HWIO_IPA_STATE_IPA_HPS_DPS_EMPTY_SHFT 0x1d +#define HWIO_IPA_STATE_IPA_RX_HPS_EMPTY_BMSK 0x10000000 +#define HWIO_IPA_STATE_IPA_RX_HPS_EMPTY_SHFT 0x1c +#define HWIO_IPA_STATE_IPA_RX_SPLT_CMDQ_EMPTY_BMSK 0xf800000 +#define HWIO_IPA_STATE_IPA_RX_SPLT_CMDQ_EMPTY_SHFT 0x17 +#define HWIO_IPA_STATE_IPA_TX_COMMANDER_CMDQ_EMPTY_BMSK 0x400000 +#define HWIO_IPA_STATE_IPA_TX_COMMANDER_CMDQ_EMPTY_SHFT 0x16 +#define HWIO_IPA_STATE_IPA_RX_ACKQ_EMPTY_BMSK 0x200000 +#define HWIO_IPA_STATE_IPA_RX_ACKQ_EMPTY_SHFT 0x15 +#define HWIO_IPA_STATE_IPA_UC_ACKQ_EMPTY_BMSK 0x100000 +#define HWIO_IPA_STATE_IPA_UC_ACKQ_EMPTY_SHFT 0x14 +#define HWIO_IPA_STATE_IPA_TX_ACKQ_EMPTY_BMSK 0x80000 +#define HWIO_IPA_STATE_IPA_TX_ACKQ_EMPTY_SHFT 0x13 +#define HWIO_IPA_STATE_IPA_NTF_TX_EMPTY_BMSK 0x40000 +#define HWIO_IPA_STATE_IPA_NTF_TX_EMPTY_SHFT 0x12 +#define HWIO_IPA_STATE_IPA_FULL_IDLE_BMSK 0x20000 +#define HWIO_IPA_STATE_IPA_FULL_IDLE_SHFT 0x11 +#define HWIO_IPA_STATE_IPA_PROD_BRESP_IDLE_BMSK 0x10000 +#define HWIO_IPA_STATE_IPA_PROD_BRESP_IDLE_SHFT 0x10 +#define HWIO_IPA_STATE_IPA_PROD_ACKMNGR_STATE_IDLE_BMSK 0x8000 +#define HWIO_IPA_STATE_IPA_PROD_ACKMNGR_STATE_IDLE_SHFT 0xf +#define HWIO_IPA_STATE_IPA_PROD_ACKMNGR_DB_EMPTY_BMSK 0x4000 +#define HWIO_IPA_STATE_IPA_PROD_ACKMNGR_DB_EMPTY_SHFT 0xe +#define HWIO_IPA_STATE_IPA_TX_ACKQ_FULL_BMSK 0x2000 +#define HWIO_IPA_STATE_IPA_TX_ACKQ_FULL_SHFT 0xd +#define HWIO_IPA_STATE_IPA_ACKMNGR_STATE_IDLE_BMSK 0x1000 +#define HWIO_IPA_STATE_IPA_ACKMNGR_STATE_IDLE_SHFT 0xc +#define HWIO_IPA_STATE_IPA_ACKMNGR_DB_EMPTY_BMSK 0x800 +#define HWIO_IPA_STATE_IPA_ACKMNGR_DB_EMPTY_SHFT 0xb +#define HWIO_IPA_STATE_IPA_RSRC_STATE_IDLE_BMSK 0x400 +#define HWIO_IPA_STATE_IPA_RSRC_STATE_IDLE_SHFT 0xa +#define HWIO_IPA_STATE_IPA_RSRC_MNGR_DB_EMPTY_BMSK 0x200 +#define HWIO_IPA_STATE_IPA_RSRC_MNGR_DB_EMPTY_SHFT 0x9 +#define HWIO_IPA_STATE_MBIM_AGGR_IDLE_BMSK 0x100 +#define HWIO_IPA_STATE_MBIM_AGGR_IDLE_SHFT 0x8 +#define HWIO_IPA_STATE_AGGR_IDLE_BMSK 0x80 +#define HWIO_IPA_STATE_AGGR_IDLE_SHFT 0x7 +#define HWIO_IPA_STATE_IPA_NOC_IDLE_BMSK 0x40 +#define HWIO_IPA_STATE_IPA_NOC_IDLE_SHFT 0x6 +#define HWIO_IPA_STATE_IPA_STATUS_SNIFFER_IDLE_BMSK 0x20 +#define HWIO_IPA_STATE_IPA_STATUS_SNIFFER_IDLE_SHFT 0x5 +#define HWIO_IPA_STATE_BAM_GSI_IDLE_BMSK 0x10 +#define HWIO_IPA_STATE_BAM_GSI_IDLE_SHFT 0x4 +#define HWIO_IPA_STATE_DPL_FIFO_IDLE_BMSK 0x8 +#define HWIO_IPA_STATE_DPL_FIFO_IDLE_SHFT 0x3 +#define HWIO_IPA_STATE_TX_IDLE_BMSK 0x4 +#define HWIO_IPA_STATE_TX_IDLE_SHFT 0x2 +#define HWIO_IPA_STATE_RX_IDLE_BMSK 0x2 +#define HWIO_IPA_STATE_RX_IDLE_SHFT 0x1 +#define HWIO_IPA_STATE_RX_WAIT_BMSK 0x1 +#define HWIO_IPA_STATE_RX_WAIT_SHFT 0x0 + +#define HWIO_IPA_STATE_GSI_AOS_ADDR (IPA_CFG_REG_BASE + 0x000000b8) +#define HWIO_IPA_STATE_GSI_AOS_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000b8) +#define HWIO_IPA_STATE_GSI_AOS_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000b8) +#define HWIO_IPA_STATE_GSI_AOS_RMSK 0x3 +#define HWIO_IPA_STATE_GSI_AOS_ATTR 0x1 +#define HWIO_IPA_STATE_GSI_AOS_IN \ + in_dword_masked(HWIO_IPA_STATE_GSI_AOS_ADDR, HWIO_IPA_STATE_GSI_AOS_RMSK) +#define HWIO_IPA_STATE_GSI_AOS_INM(m) \ + in_dword_masked(HWIO_IPA_STATE_GSI_AOS_ADDR, m) +#define HWIO_IPA_STATE_GSI_AOS_IPA_GSI_AOS_NLO_FSM_IDLE_BMSK 0x2 +#define HWIO_IPA_STATE_GSI_AOS_IPA_GSI_AOS_NLO_FSM_IDLE_SHFT 0x1 +#define HWIO_IPA_STATE_GSI_AOS_IPA_GSI_AOS_FSM_IDLE_BMSK 0x1 +#define HWIO_IPA_STATE_GSI_AOS_IPA_GSI_AOS_FSM_IDLE_SHFT 0x0 + +#define HWIO_IPA_STATE_GSI_IF_ADDR (IPA_CFG_REG_BASE + 0x000000c0) +#define HWIO_IPA_STATE_GSI_IF_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000c0) +#define HWIO_IPA_STATE_GSI_IF_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000c0) +#define HWIO_IPA_STATE_GSI_IF_RMSK 0x301ff +#define HWIO_IPA_STATE_GSI_IF_ATTR 0x1 +#define HWIO_IPA_STATE_GSI_IF_IN \ + in_dword_masked(HWIO_IPA_STATE_GSI_IF_ADDR, HWIO_IPA_STATE_GSI_IF_RMSK) +#define HWIO_IPA_STATE_GSI_IF_INM(m) \ + in_dword_masked(HWIO_IPA_STATE_GSI_IF_ADDR, m) +#define HWIO_IPA_STATE_GSI_IF_IPA_GSI_SKIP_FSM_BMSK 0x30000 +#define HWIO_IPA_STATE_GSI_IF_IPA_GSI_SKIP_FSM_SHFT 0x10 +#define HWIO_IPA_STATE_GSI_IF_IPA_GSI_TOGGLE_FSM_IDLE_BMSK 0x100 +#define HWIO_IPA_STATE_GSI_IF_IPA_GSI_TOGGLE_FSM_IDLE_SHFT 0x8 +#define HWIO_IPA_STATE_GSI_IF_IPA_GSI_PROD_FSM_TX_1_BMSK 0xf0 +#define HWIO_IPA_STATE_GSI_IF_IPA_GSI_PROD_FSM_TX_1_SHFT 0x4 +#define HWIO_IPA_STATE_GSI_IF_IPA_GSI_PROD_FSM_TX_0_BMSK 0xf +#define HWIO_IPA_STATE_GSI_IF_IPA_GSI_PROD_FSM_TX_0_SHFT 0x0 + +#define HWIO_IPA_STATE_GSI_IF_CONS_ADDR (IPA_CFG_REG_BASE + 0x000000c8) +#define HWIO_IPA_STATE_GSI_IF_CONS_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000c8) +#define HWIO_IPA_STATE_GSI_IF_CONS_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000c8) +#define HWIO_IPA_STATE_GSI_IF_CONS_RMSK 0xff +#define HWIO_IPA_STATE_GSI_IF_CONS_ATTR 0x1 +#define HWIO_IPA_STATE_GSI_IF_CONS_IN \ + in_dword_masked(HWIO_IPA_STATE_GSI_IF_CONS_ADDR, HWIO_IPA_STATE_GSI_IF_CONS_RMSK) +#define HWIO_IPA_STATE_GSI_IF_CONS_INM(m) \ + in_dword_masked(HWIO_IPA_STATE_GSI_IF_CONS_ADDR, m) +#define HWIO_IPA_STATE_GSI_IF_CONS_IPA_STATE_GSI_IF_CONS_CACHE_VLD_BMSK 0xfe +#define HWIO_IPA_STATE_GSI_IF_CONS_IPA_STATE_GSI_IF_CONS_CACHE_VLD_SHFT 0x1 +#define HWIO_IPA_STATE_GSI_IF_CONS_IPA_STATE_GSI_IF_CONS_STATE_IDLE_BMSK 0x1 +#define HWIO_IPA_STATE_GSI_IF_CONS_IPA_STATE_GSI_IF_CONS_STATE_IDLE_SHFT 0x0 + +#define HWIO_IPA_STATE_FETCHER_MASK_1_ADDR (IPA_CFG_REG_BASE + 0x000000cc) +#define HWIO_IPA_STATE_FETCHER_MASK_1_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000cc) +#define HWIO_IPA_STATE_FETCHER_MASK_1_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000cc) +#define HWIO_IPA_STATE_FETCHER_MASK_1_RMSK 0xffffffff +#define HWIO_IPA_STATE_FETCHER_MASK_1_ATTR 0x1 +#define HWIO_IPA_STATE_FETCHER_MASK_1_IN \ + in_dword_masked(HWIO_IPA_STATE_FETCHER_MASK_1_ADDR, HWIO_IPA_STATE_FETCHER_MASK_1_RMSK) +#define HWIO_IPA_STATE_FETCHER_MASK_1_INM(m) \ + in_dword_masked(HWIO_IPA_STATE_FETCHER_MASK_1_ADDR, m) +#define HWIO_IPA_STATE_FETCHER_MASK_1_MASK_QUEUE_NO_SPACE_DPL_FIFO_BMSK 0xff000000 +#define HWIO_IPA_STATE_FETCHER_MASK_1_MASK_QUEUE_NO_SPACE_DPL_FIFO_SHFT 0x18 +#define HWIO_IPA_STATE_FETCHER_MASK_1_MASK_QUEUE_STEP_MODE_BMSK 0xff0000 +#define HWIO_IPA_STATE_FETCHER_MASK_1_MASK_QUEUE_STEP_MODE_SHFT 0x10 +#define HWIO_IPA_STATE_FETCHER_MASK_1_MASK_QUEUE_ARB_LOCK_BMSK 0xff00 +#define HWIO_IPA_STATE_FETCHER_MASK_1_MASK_QUEUE_ARB_LOCK_SHFT 0x8 +#define HWIO_IPA_STATE_FETCHER_MASK_1_MASK_QUEUE_NO_RESOURCES_ACK_ENTRY_BMSK 0xff +#define HWIO_IPA_STATE_FETCHER_MASK_1_MASK_QUEUE_NO_RESOURCES_ACK_ENTRY_SHFT 0x0 + +#define HWIO_IPA_STATE_FETCHER_MASK_2_ADDR (IPA_CFG_REG_BASE + 0x000000d0) +#define HWIO_IPA_STATE_FETCHER_MASK_2_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000d0) +#define HWIO_IPA_STATE_FETCHER_MASK_2_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000d0) +#define HWIO_IPA_STATE_FETCHER_MASK_2_RMSK 0xffff +#define HWIO_IPA_STATE_FETCHER_MASK_2_ATTR 0x1 +#define HWIO_IPA_STATE_FETCHER_MASK_2_IN \ + in_dword_masked(HWIO_IPA_STATE_FETCHER_MASK_2_ADDR, HWIO_IPA_STATE_FETCHER_MASK_2_RMSK) +#define HWIO_IPA_STATE_FETCHER_MASK_2_INM(m) \ + in_dword_masked(HWIO_IPA_STATE_FETCHER_MASK_2_ADDR, m) +#define HWIO_IPA_STATE_FETCHER_MASK_2_MASK_QUEUE_DRBIP_PKT_EXCEED_MAX_SIZE_BMSK 0xff00 +#define HWIO_IPA_STATE_FETCHER_MASK_2_MASK_QUEUE_DRBIP_PKT_EXCEED_MAX_SIZE_SHFT 0x8 +#define HWIO_IPA_STATE_FETCHER_MASK_2_MASK_QUEUE_DRBIP_NO_DATA_SECTORS_BMSK 0xff +#define HWIO_IPA_STATE_FETCHER_MASK_2_MASK_QUEUE_DRBIP_NO_DATA_SECTORS_SHFT 0x0 + +#define HWIO_IPA_STATE_DPL_FIFO_ADDR (IPA_CFG_REG_BASE + 0x000000d4) +#define HWIO_IPA_STATE_DPL_FIFO_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000d4) +#define HWIO_IPA_STATE_DPL_FIFO_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000d4) +#define HWIO_IPA_STATE_DPL_FIFO_RMSK 0x7 +#define HWIO_IPA_STATE_DPL_FIFO_ATTR 0x1 +#define HWIO_IPA_STATE_DPL_FIFO_IN \ + in_dword_masked(HWIO_IPA_STATE_DPL_FIFO_ADDR, HWIO_IPA_STATE_DPL_FIFO_RMSK) +#define HWIO_IPA_STATE_DPL_FIFO_INM(m) \ + in_dword_masked(HWIO_IPA_STATE_DPL_FIFO_ADDR, m) +#define HWIO_IPA_STATE_DPL_FIFO_POP_FSM_STATE_BMSK 0x7 +#define HWIO_IPA_STATE_DPL_FIFO_POP_FSM_STATE_SHFT 0x0 + +#define HWIO_IPA_STATE_COAL_MASTER_ADDR (IPA_CFG_REG_BASE + 0x000000d8) +#define HWIO_IPA_STATE_COAL_MASTER_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000d8) +#define HWIO_IPA_STATE_COAL_MASTER_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000d8) +#define HWIO_IPA_STATE_COAL_MASTER_RMSK 0xffffffff +#define HWIO_IPA_STATE_COAL_MASTER_ATTR 0x1 +#define HWIO_IPA_STATE_COAL_MASTER_IN \ + in_dword_masked(HWIO_IPA_STATE_COAL_MASTER_ADDR, HWIO_IPA_STATE_COAL_MASTER_RMSK) +#define HWIO_IPA_STATE_COAL_MASTER_INM(m) \ + in_dword_masked(HWIO_IPA_STATE_COAL_MASTER_ADDR, m) +#define HWIO_IPA_STATE_COAL_MASTER_VP_TIMER_EXPIRED_BMSK 0xf0000000 +#define HWIO_IPA_STATE_COAL_MASTER_VP_TIMER_EXPIRED_SHFT 0x1c +#define HWIO_IPA_STATE_COAL_MASTER_LRU_VP_BMSK 0xf000000 +#define HWIO_IPA_STATE_COAL_MASTER_LRU_VP_SHFT 0x18 +#define HWIO_IPA_STATE_COAL_MASTER_INIT_VP_FSM_STATE_BMSK 0xf00000 +#define HWIO_IPA_STATE_COAL_MASTER_INIT_VP_FSM_STATE_SHFT 0x14 +#define HWIO_IPA_STATE_COAL_MASTER_CHECK_FIT_FSM_STATE_BMSK 0xf0000 +#define HWIO_IPA_STATE_COAL_MASTER_CHECK_FIT_FSM_STATE_SHFT 0x10 +#define HWIO_IPA_STATE_COAL_MASTER_HASH_CALC_FSM_STATE_BMSK 0xf000 +#define HWIO_IPA_STATE_COAL_MASTER_HASH_CALC_FSM_STATE_SHFT 0xc +#define HWIO_IPA_STATE_COAL_MASTER_FIND_OPEN_FSM_STATE_BMSK 0xf00 +#define HWIO_IPA_STATE_COAL_MASTER_FIND_OPEN_FSM_STATE_SHFT 0x8 +#define HWIO_IPA_STATE_COAL_MASTER_MAIN_FSM_STATE_BMSK 0xf0 +#define HWIO_IPA_STATE_COAL_MASTER_MAIN_FSM_STATE_SHFT 0x4 +#define HWIO_IPA_STATE_COAL_MASTER_VP_VLD_BMSK 0xf +#define HWIO_IPA_STATE_COAL_MASTER_VP_VLD_SHFT 0x0 + +#define HWIO_IPA_STATE_COAL_MASTER_1_ADDR (IPA_CFG_REG_BASE + 0x000000dc) +#define HWIO_IPA_STATE_COAL_MASTER_1_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000dc) +#define HWIO_IPA_STATE_COAL_MASTER_1_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000dc) +#define HWIO_IPA_STATE_COAL_MASTER_1_RMSK 0x3fffffff +#define HWIO_IPA_STATE_COAL_MASTER_1_ATTR 0x1 +#define HWIO_IPA_STATE_COAL_MASTER_1_IN \ + in_dword_masked(HWIO_IPA_STATE_COAL_MASTER_1_ADDR, HWIO_IPA_STATE_COAL_MASTER_1_RMSK) +#define HWIO_IPA_STATE_COAL_MASTER_1_INM(m) \ + in_dword_masked(HWIO_IPA_STATE_COAL_MASTER_1_ADDR, m) +#define HWIO_IPA_STATE_COAL_MASTER_1_ARBITER_STATE_BMSK 0x3c000000 +#define HWIO_IPA_STATE_COAL_MASTER_1_ARBITER_STATE_SHFT 0x1a +#define HWIO_IPA_STATE_COAL_MASTER_1_CHECK_FIT_FSM_STATE_BMSK 0x3c00000 +#define HWIO_IPA_STATE_COAL_MASTER_1_CHECK_FIT_FSM_STATE_SHFT 0x16 +#define HWIO_IPA_STATE_COAL_MASTER_1_CHECK_FIT_RD_CTX_LINE_BMSK 0x3f0000 +#define HWIO_IPA_STATE_COAL_MASTER_1_CHECK_FIT_RD_CTX_LINE_SHFT 0x10 +#define HWIO_IPA_STATE_COAL_MASTER_1_INIT_VP_FSM_STATE_BMSK 0xf000 +#define HWIO_IPA_STATE_COAL_MASTER_1_INIT_VP_FSM_STATE_SHFT 0xc +#define HWIO_IPA_STATE_COAL_MASTER_1_INIT_VP_RD_PKT_LINE_BMSK 0xfc0 +#define HWIO_IPA_STATE_COAL_MASTER_1_INIT_VP_RD_PKT_LINE_SHFT 0x6 +#define HWIO_IPA_STATE_COAL_MASTER_1_INIT_VP_WR_CTX_LINE_BMSK 0x3f +#define HWIO_IPA_STATE_COAL_MASTER_1_INIT_VP_WR_CTX_LINE_SHFT 0x0 + +#define HWIO_IPA_STATE_NLO_AGGR_ADDR (IPA_CFG_REG_BASE + 0x000000e0) +#define HWIO_IPA_STATE_NLO_AGGR_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000e0) +#define HWIO_IPA_STATE_NLO_AGGR_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000e0) +#define HWIO_IPA_STATE_NLO_AGGR_RMSK 0xffffffff +#define HWIO_IPA_STATE_NLO_AGGR_ATTR 0x1 +#define HWIO_IPA_STATE_NLO_AGGR_IN \ + in_dword_masked(HWIO_IPA_STATE_NLO_AGGR_ADDR, HWIO_IPA_STATE_NLO_AGGR_RMSK) +#define HWIO_IPA_STATE_NLO_AGGR_INM(m) \ + in_dword_masked(HWIO_IPA_STATE_NLO_AGGR_ADDR, m) +#define HWIO_IPA_STATE_NLO_AGGR_NLO_AGGR_STATE_BMSK 0xffffffff +#define HWIO_IPA_STATE_NLO_AGGR_NLO_AGGR_STATE_SHFT 0x0 + +#define HWIO_IPA_STATE_CTXH_ADDR (IPA_CFG_REG_BASE + 0x000000e4) +#define HWIO_IPA_STATE_CTXH_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000e4) +#define HWIO_IPA_STATE_CTXH_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000e4) +#define HWIO_IPA_STATE_CTXH_RMSK 0x3 +#define HWIO_IPA_STATE_CTXH_ATTR 0x1 +#define HWIO_IPA_STATE_CTXH_IN \ + in_dword_masked(HWIO_IPA_STATE_CTXH_ADDR, HWIO_IPA_STATE_CTXH_RMSK) +#define HWIO_IPA_STATE_CTXH_INM(m) \ + in_dword_masked(HWIO_IPA_STATE_CTXH_ADDR, m) +#define HWIO_IPA_STATE_CTXH_IPA_CTXH_WR_IDLE_BMSK 0x2 +#define HWIO_IPA_STATE_CTXH_IPA_CTXH_WR_IDLE_SHFT 0x1 +#define HWIO_IPA_STATE_CTXH_IPA_CTXH_RD_IDLE_BMSK 0x1 +#define HWIO_IPA_STATE_CTXH_IPA_CTXH_RD_IDLE_SHFT 0x0 + +#define HWIO_IPA_STATE_UC_QMB_ADDR (IPA_CFG_REG_BASE + 0x000000e8) +#define HWIO_IPA_STATE_UC_QMB_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000e8) +#define HWIO_IPA_STATE_UC_QMB_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000e8) +#define HWIO_IPA_STATE_UC_QMB_RMSK 0x1ff01ff +#define HWIO_IPA_STATE_UC_QMB_ATTR 0x1 +#define HWIO_IPA_STATE_UC_QMB_IN \ + in_dword_masked(HWIO_IPA_STATE_UC_QMB_ADDR, HWIO_IPA_STATE_UC_QMB_RMSK) +#define HWIO_IPA_STATE_UC_QMB_INM(m) \ + in_dword_masked(HWIO_IPA_STATE_UC_QMB_ADDR, m) +#define HWIO_IPA_STATE_UC_QMB_QUEUE_1_IDLE_BMSK 0x1000000 +#define HWIO_IPA_STATE_UC_QMB_QUEUE_1_IDLE_SHFT 0x18 +#define HWIO_IPA_STATE_UC_QMB_CMD_FIFO_FULL_QUEUE_1_BMSK 0x800000 +#define HWIO_IPA_STATE_UC_QMB_CMD_FIFO_FULL_QUEUE_1_SHFT 0x17 +#define HWIO_IPA_STATE_UC_QMB_CMD_FIFO_EMPTY_QUEUE_1_BMSK 0x400000 +#define HWIO_IPA_STATE_UC_QMB_CMD_FIFO_EMPTY_QUEUE_1_SHFT 0x16 +#define HWIO_IPA_STATE_UC_QMB_COMP_FIFO_FULL_QUEUE_1_BMSK 0x200000 +#define HWIO_IPA_STATE_UC_QMB_COMP_FIFO_FULL_QUEUE_1_SHFT 0x15 +#define HWIO_IPA_STATE_UC_QMB_COMP_FIFO_EMPTY_QUEUE_1_BMSK 0x100000 +#define HWIO_IPA_STATE_UC_QMB_COMP_FIFO_EMPTY_QUEUE_1_SHFT 0x14 +#define HWIO_IPA_STATE_UC_QMB_OT_TABLE_FULL_QUEUE_1_BMSK 0x80000 +#define HWIO_IPA_STATE_UC_QMB_OT_TABLE_FULL_QUEUE_1_SHFT 0x13 +#define HWIO_IPA_STATE_UC_QMB_OT_TABLE_EMPTY_QUEUE_1_BMSK 0x40000 +#define HWIO_IPA_STATE_UC_QMB_OT_TABLE_EMPTY_QUEUE_1_SHFT 0x12 +#define HWIO_IPA_STATE_UC_QMB_CTRL_FSM_STATE_QUEUE_1_BMSK 0x30000 +#define HWIO_IPA_STATE_UC_QMB_CTRL_FSM_STATE_QUEUE_1_SHFT 0x10 +#define HWIO_IPA_STATE_UC_QMB_QUEUE_0_IDLE_BMSK 0x100 +#define HWIO_IPA_STATE_UC_QMB_QUEUE_0_IDLE_SHFT 0x8 +#define HWIO_IPA_STATE_UC_QMB_CMD_FIFO_FULL_QUEUE_0_BMSK 0x80 +#define HWIO_IPA_STATE_UC_QMB_CMD_FIFO_FULL_QUEUE_0_SHFT 0x7 +#define HWIO_IPA_STATE_UC_QMB_CMD_FIFO_EMPTY_QUEUE_0_BMSK 0x40 +#define HWIO_IPA_STATE_UC_QMB_CMD_FIFO_EMPTY_QUEUE_0_SHFT 0x6 +#define HWIO_IPA_STATE_UC_QMB_COMP_FIFO_FULL_QUEUE_0_BMSK 0x20 +#define HWIO_IPA_STATE_UC_QMB_COMP_FIFO_FULL_QUEUE_0_SHFT 0x5 +#define HWIO_IPA_STATE_UC_QMB_COMP_FIFO_EMPTY_QUEUE_0_BMSK 0x10 +#define HWIO_IPA_STATE_UC_QMB_COMP_FIFO_EMPTY_QUEUE_0_SHFT 0x4 +#define HWIO_IPA_STATE_UC_QMB_OT_TABLE_FULL_QUEUE_0_BMSK 0x8 +#define HWIO_IPA_STATE_UC_QMB_OT_TABLE_FULL_QUEUE_0_SHFT 0x3 +#define HWIO_IPA_STATE_UC_QMB_OT_TABLE_EMPTY_QUEUE_0_BMSK 0x4 +#define HWIO_IPA_STATE_UC_QMB_OT_TABLE_EMPTY_QUEUE_0_SHFT 0x2 +#define HWIO_IPA_STATE_UC_QMB_CTRL_FSM_STATE_QUEUE_0_BMSK 0x3 +#define HWIO_IPA_STATE_UC_QMB_CTRL_FSM_STATE_QUEUE_0_SHFT 0x0 + +#define HWIO_IPA_STATE_DRBIP_ADDR (IPA_CFG_REG_BASE + 0x000000ec) +#define HWIO_IPA_STATE_DRBIP_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000ec) +#define HWIO_IPA_STATE_DRBIP_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000ec) +#define HWIO_IPA_STATE_DRBIP_RMSK 0xf0107 +#define HWIO_IPA_STATE_DRBIP_ATTR 0x1 +#define HWIO_IPA_STATE_DRBIP_IN \ + in_dword_masked(HWIO_IPA_STATE_DRBIP_ADDR, HWIO_IPA_STATE_DRBIP_RMSK) +#define HWIO_IPA_STATE_DRBIP_INM(m) \ + in_dword_masked(HWIO_IPA_STATE_DRBIP_ADDR, m) +#define HWIO_IPA_STATE_DRBIP_DRBIP_PKT_IDLE_BMSK 0xf0000 +#define HWIO_IPA_STATE_DRBIP_DRBIP_PKT_IDLE_SHFT 0x10 +#define HWIO_IPA_STATE_DRBIP_DRBIP_DCPH_IDLE_BMSK 0x100 +#define HWIO_IPA_STATE_DRBIP_DRBIP_DCPH_IDLE_SHFT 0x8 +#define HWIO_IPA_STATE_DRBIP_DRBIP_DMAR_IDLE_BMSK 0x7 +#define HWIO_IPA_STATE_DRBIP_DRBIP_DMAR_IDLE_SHFT 0x0 + +#define HWIO_IPA_STATE_AGGR_ACTIVE_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000100 + 0x4 * (n)) +#define HWIO_IPA_STATE_AGGR_ACTIVE_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000100 + 0x4 * (n)) +#define HWIO_IPA_STATE_AGGR_ACTIVE_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000100 + 0x4 * (n)) +#define HWIO_IPA_STATE_AGGR_ACTIVE_n_RMSK 0xffffffff +#define HWIO_IPA_STATE_AGGR_ACTIVE_n_MAXn 1 +#define HWIO_IPA_STATE_AGGR_ACTIVE_n_ATTR 0x1 +#define HWIO_IPA_STATE_AGGR_ACTIVE_n_INI(n) \ + in_dword_masked(HWIO_IPA_STATE_AGGR_ACTIVE_n_ADDR(n), HWIO_IPA_STATE_AGGR_ACTIVE_n_RMSK) +#define HWIO_IPA_STATE_AGGR_ACTIVE_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_STATE_AGGR_ACTIVE_n_ADDR(n), mask) +#define HWIO_IPA_STATE_AGGR_ACTIVE_n_ENDPOINTS_BMSK 0xffffffff +#define HWIO_IPA_STATE_AGGR_ACTIVE_n_ENDPOINTS_SHFT 0x0 + +#define HWIO_IPA_STATE_GSI_TLV_FIFO_EMPTY_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000120 + 0x4 * (n)) +#define HWIO_IPA_STATE_GSI_TLV_FIFO_EMPTY_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000120 + 0x4 * (n)) +#define HWIO_IPA_STATE_GSI_TLV_FIFO_EMPTY_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000120 + 0x4 * (n)) +#define HWIO_IPA_STATE_GSI_TLV_FIFO_EMPTY_n_RMSK 0xffffffff +#define HWIO_IPA_STATE_GSI_TLV_FIFO_EMPTY_n_MAXn 1 +#define HWIO_IPA_STATE_GSI_TLV_FIFO_EMPTY_n_ATTR 0x1 +#define HWIO_IPA_STATE_GSI_TLV_FIFO_EMPTY_n_INI(n) \ + in_dword_masked(HWIO_IPA_STATE_GSI_TLV_FIFO_EMPTY_n_ADDR(n), HWIO_IPA_STATE_GSI_TLV_FIFO_EMPTY_n_RMSK) +#define HWIO_IPA_STATE_GSI_TLV_FIFO_EMPTY_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_STATE_GSI_TLV_FIFO_EMPTY_n_ADDR(n), mask) +#define HWIO_IPA_STATE_GSI_TLV_FIFO_EMPTY_n_PIPE_FIFO_EMPTY_BMSK 0xffffffff +#define HWIO_IPA_STATE_GSI_TLV_FIFO_EMPTY_n_PIPE_FIFO_EMPTY_SHFT 0x0 + +#define HWIO_IPA_STATE_GSI_AOS_FIFO_EMPTY_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000140 + 0x4 * (n)) +#define HWIO_IPA_STATE_GSI_AOS_FIFO_EMPTY_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000140 + 0x4 * (n)) +#define HWIO_IPA_STATE_GSI_AOS_FIFO_EMPTY_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000140 + 0x4 * (n)) +#define HWIO_IPA_STATE_GSI_AOS_FIFO_EMPTY_n_RMSK 0xffffffff +#define HWIO_IPA_STATE_GSI_AOS_FIFO_EMPTY_n_MAXn 1 +#define HWIO_IPA_STATE_GSI_AOS_FIFO_EMPTY_n_ATTR 0x1 +#define HWIO_IPA_STATE_GSI_AOS_FIFO_EMPTY_n_INI(n) \ + in_dword_masked(HWIO_IPA_STATE_GSI_AOS_FIFO_EMPTY_n_ADDR(n), HWIO_IPA_STATE_GSI_AOS_FIFO_EMPTY_n_RMSK) +#define HWIO_IPA_STATE_GSI_AOS_FIFO_EMPTY_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_STATE_GSI_AOS_FIFO_EMPTY_n_ADDR(n), mask) +#define HWIO_IPA_STATE_GSI_AOS_FIFO_EMPTY_n_PIPE_FIFO_EMPTY_BMSK 0xffffffff +#define HWIO_IPA_STATE_GSI_AOS_FIFO_EMPTY_n_PIPE_FIFO_EMPTY_SHFT 0x0 + +#define HWIO_IPA_STATE_DRBIP_DROP_STATE_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000160 + 0x4 * (n)) +#define HWIO_IPA_STATE_DRBIP_DROP_STATE_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000160 + 0x4 * (n)) +#define HWIO_IPA_STATE_DRBIP_DROP_STATE_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000160 + 0x4 * (n)) +#define HWIO_IPA_STATE_DRBIP_DROP_STATE_n_RMSK 0xffffffff +#define HWIO_IPA_STATE_DRBIP_DROP_STATE_n_MAXn 1 +#define HWIO_IPA_STATE_DRBIP_DROP_STATE_n_ATTR 0x1 +#define HWIO_IPA_STATE_DRBIP_DROP_STATE_n_INI(n) \ + in_dword_masked(HWIO_IPA_STATE_DRBIP_DROP_STATE_n_ADDR(n), HWIO_IPA_STATE_DRBIP_DROP_STATE_n_RMSK) +#define HWIO_IPA_STATE_DRBIP_DROP_STATE_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_STATE_DRBIP_DROP_STATE_n_ADDR(n), mask) +#define HWIO_IPA_STATE_DRBIP_DROP_STATE_n_CONSUMER_PIPE_DROP_STATE_BMSK 0xffffffff +#define HWIO_IPA_STATE_DRBIP_DROP_STATE_n_CONSUMER_PIPE_DROP_STATE_SHFT 0x0 + +#define HWIO_IPA_STATE_DFETCHER_MASK_0_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000180 + 0x4 * (n)) +#define HWIO_IPA_STATE_DFETCHER_MASK_0_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000180 + 0x4 * (n)) +#define HWIO_IPA_STATE_DFETCHER_MASK_0_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000180 + 0x4 * (n)) +#define HWIO_IPA_STATE_DFETCHER_MASK_0_n_RMSK 0xffffffff +#define HWIO_IPA_STATE_DFETCHER_MASK_0_n_MAXn 1 +#define HWIO_IPA_STATE_DFETCHER_MASK_0_n_ATTR 0x1 +#define HWIO_IPA_STATE_DFETCHER_MASK_0_n_INI(n) \ + in_dword_masked(HWIO_IPA_STATE_DFETCHER_MASK_0_n_ADDR(n), HWIO_IPA_STATE_DFETCHER_MASK_0_n_RMSK) +#define HWIO_IPA_STATE_DFETCHER_MASK_0_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_STATE_DFETCHER_MASK_0_n_ADDR(n), mask) +#define HWIO_IPA_STATE_DFETCHER_MASK_0_n_MASK_QUEUE_DST_GRP_DMAR_OUTSTANDING_BMSK 0xffffffff +#define HWIO_IPA_STATE_DFETCHER_MASK_0_n_MASK_QUEUE_DST_GRP_DMAR_OUTSTANDING_SHFT 0x0 + +#define HWIO_IPA_STATE_DFETCHER_MASK_1_n_ADDR(n) (IPA_CFG_REG_BASE + 0x000001a0 + 0x4 * (n)) +#define HWIO_IPA_STATE_DFETCHER_MASK_1_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x000001a0 + 0x4 * (n)) +#define HWIO_IPA_STATE_DFETCHER_MASK_1_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x000001a0 + 0x4 * (n)) +#define HWIO_IPA_STATE_DFETCHER_MASK_1_n_RMSK 0xffffffff +#define HWIO_IPA_STATE_DFETCHER_MASK_1_n_MAXn 1 +#define HWIO_IPA_STATE_DFETCHER_MASK_1_n_ATTR 0x1 +#define HWIO_IPA_STATE_DFETCHER_MASK_1_n_INI(n) \ + in_dword_masked(HWIO_IPA_STATE_DFETCHER_MASK_1_n_ADDR(n), HWIO_IPA_STATE_DFETCHER_MASK_1_n_RMSK) +#define HWIO_IPA_STATE_DFETCHER_MASK_1_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_STATE_DFETCHER_MASK_1_n_ADDR(n), mask) +#define HWIO_IPA_STATE_DFETCHER_MASK_1_n_MASK_QUEUE_NO_RESOURCES_DATA_SECTORS_BMSK 0xffffffff +#define HWIO_IPA_STATE_DFETCHER_MASK_1_n_MASK_QUEUE_NO_RESOURCES_DATA_SECTORS_SHFT 0x0 + +#define HWIO_IPA_STATE_DFETCHER_MASK_2_n_ADDR(n) (IPA_CFG_REG_BASE + 0x000001c0 + 0x4 * (n)) +#define HWIO_IPA_STATE_DFETCHER_MASK_2_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x000001c0 + 0x4 * (n)) +#define HWIO_IPA_STATE_DFETCHER_MASK_2_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x000001c0 + 0x4 * (n)) +#define HWIO_IPA_STATE_DFETCHER_MASK_2_n_RMSK 0xffffffff +#define HWIO_IPA_STATE_DFETCHER_MASK_2_n_MAXn 1 +#define HWIO_IPA_STATE_DFETCHER_MASK_2_n_ATTR 0x1 +#define HWIO_IPA_STATE_DFETCHER_MASK_2_n_INI(n) \ + in_dword_masked(HWIO_IPA_STATE_DFETCHER_MASK_2_n_ADDR(n), HWIO_IPA_STATE_DFETCHER_MASK_2_n_RMSK) +#define HWIO_IPA_STATE_DFETCHER_MASK_2_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_STATE_DFETCHER_MASK_2_n_ADDR(n), mask) +#define HWIO_IPA_STATE_DFETCHER_MASK_2_n_MASK_QUEUE_NO_RESOURCES_DPS_DMAR_BMSK 0xffffffff +#define HWIO_IPA_STATE_DFETCHER_MASK_2_n_MASK_QUEUE_NO_RESOURCES_DPS_DMAR_SHFT 0x0 + +#define HWIO_IPA_STATE_DFETCHER_MASK_3_n_ADDR(n) (IPA_CFG_REG_BASE + 0x000001e0 + 0x4 * (n)) +#define HWIO_IPA_STATE_DFETCHER_MASK_3_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x000001e0 + 0x4 * (n)) +#define HWIO_IPA_STATE_DFETCHER_MASK_3_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x000001e0 + 0x4 * (n)) +#define HWIO_IPA_STATE_DFETCHER_MASK_3_n_RMSK 0xffffffff +#define HWIO_IPA_STATE_DFETCHER_MASK_3_n_MAXn 1 +#define HWIO_IPA_STATE_DFETCHER_MASK_3_n_ATTR 0x1 +#define HWIO_IPA_STATE_DFETCHER_MASK_3_n_INI(n) \ + in_dword_masked(HWIO_IPA_STATE_DFETCHER_MASK_3_n_ADDR(n), HWIO_IPA_STATE_DFETCHER_MASK_3_n_RMSK) +#define HWIO_IPA_STATE_DFETCHER_MASK_3_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_STATE_DFETCHER_MASK_3_n_ADDR(n), mask) +#define HWIO_IPA_STATE_DFETCHER_MASK_3_n_MASK_QUEUE_NO_RESOURCES_SEG_CTX_BMSK 0xffffffff +#define HWIO_IPA_STATE_DFETCHER_MASK_3_n_MASK_QUEUE_NO_RESOURCES_SEG_CTX_SHFT 0x0 + +#define HWIO_IPA_BAM_ACTIVATED_PORTS_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000200 + 0x4 * (n)) +#define HWIO_IPA_BAM_ACTIVATED_PORTS_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000200 + 0x4 * (n)) +#define HWIO_IPA_BAM_ACTIVATED_PORTS_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000200 + 0x4 * (n)) +#define HWIO_IPA_BAM_ACTIVATED_PORTS_n_RMSK 0xffffffff +#define HWIO_IPA_BAM_ACTIVATED_PORTS_n_MAXn 1 +#define HWIO_IPA_BAM_ACTIVATED_PORTS_n_ATTR 0x1 +#define HWIO_IPA_BAM_ACTIVATED_PORTS_n_INI(n) \ + in_dword_masked(HWIO_IPA_BAM_ACTIVATED_PORTS_n_ADDR(n), HWIO_IPA_BAM_ACTIVATED_PORTS_n_RMSK) +#define HWIO_IPA_BAM_ACTIVATED_PORTS_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_BAM_ACTIVATED_PORTS_n_ADDR(n), mask) +#define HWIO_IPA_BAM_ACTIVATED_PORTS_n_ENDPOINTS_BMSK 0xffffffff +#define HWIO_IPA_BAM_ACTIVATED_PORTS_n_ENDPOINTS_SHFT 0x0 + +#define HWIO_IPA_YELLOW_MARKER_BELOW_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000220 + 0x4 * (n)) +#define HWIO_IPA_YELLOW_MARKER_BELOW_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000220 + 0x4 * (n)) +#define HWIO_IPA_YELLOW_MARKER_BELOW_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000220 + 0x4 * (n)) +#define HWIO_IPA_YELLOW_MARKER_BELOW_n_RMSK 0xffffffff +#define HWIO_IPA_YELLOW_MARKER_BELOW_n_MAXn 1 +#define HWIO_IPA_YELLOW_MARKER_BELOW_n_ATTR 0x1 +#define HWIO_IPA_YELLOW_MARKER_BELOW_n_INI(n) \ + in_dword_masked(HWIO_IPA_YELLOW_MARKER_BELOW_n_ADDR(n), HWIO_IPA_YELLOW_MARKER_BELOW_n_RMSK) +#define HWIO_IPA_YELLOW_MARKER_BELOW_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_YELLOW_MARKER_BELOW_n_ADDR(n), mask) +#define HWIO_IPA_YELLOW_MARKER_BELOW_n_ENDPOINTS_BMSK 0xffffffff +#define HWIO_IPA_YELLOW_MARKER_BELOW_n_ENDPOINTS_SHFT 0x0 + +#define HWIO_IPA_YELLOW_MARKER_BELOW_EN_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000240 + 0x4 * (n)) +#define HWIO_IPA_YELLOW_MARKER_BELOW_EN_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000240 + 0x4 * (n)) +#define HWIO_IPA_YELLOW_MARKER_BELOW_EN_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000240 + 0x4 * (n)) +#define HWIO_IPA_YELLOW_MARKER_BELOW_EN_n_RMSK 0xffffffff +#define HWIO_IPA_YELLOW_MARKER_BELOW_EN_n_MAXn 1 +#define HWIO_IPA_YELLOW_MARKER_BELOW_EN_n_ATTR 0x3 +#define HWIO_IPA_YELLOW_MARKER_BELOW_EN_n_INI(n) \ + in_dword_masked(HWIO_IPA_YELLOW_MARKER_BELOW_EN_n_ADDR(n), HWIO_IPA_YELLOW_MARKER_BELOW_EN_n_RMSK) +#define HWIO_IPA_YELLOW_MARKER_BELOW_EN_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_YELLOW_MARKER_BELOW_EN_n_ADDR(n), mask) +#define HWIO_IPA_YELLOW_MARKER_BELOW_EN_n_OUTI(n,val) \ + out_dword(HWIO_IPA_YELLOW_MARKER_BELOW_EN_n_ADDR(n),val) +#define HWIO_IPA_YELLOW_MARKER_BELOW_EN_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_YELLOW_MARKER_BELOW_EN_n_ADDR(n),mask,val,HWIO_IPA_YELLOW_MARKER_BELOW_EN_n_INI(n)) +#define HWIO_IPA_YELLOW_MARKER_BELOW_EN_n_ENDPOINTS_BMSK 0xffffffff +#define HWIO_IPA_YELLOW_MARKER_BELOW_EN_n_ENDPOINTS_SHFT 0x0 + +#define HWIO_IPA_YELLOW_MARKER_BELOW_CLR_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000260 + 0x4 * (n)) +#define HWIO_IPA_YELLOW_MARKER_BELOW_CLR_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000260 + 0x4 * (n)) +#define HWIO_IPA_YELLOW_MARKER_BELOW_CLR_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000260 + 0x4 * (n)) +#define HWIO_IPA_YELLOW_MARKER_BELOW_CLR_n_RMSK 0xffffffff +#define HWIO_IPA_YELLOW_MARKER_BELOW_CLR_n_MAXn 1 +#define HWIO_IPA_YELLOW_MARKER_BELOW_CLR_n_ATTR 0x2 +#define HWIO_IPA_YELLOW_MARKER_BELOW_CLR_n_OUTI(n,val) \ + out_dword(HWIO_IPA_YELLOW_MARKER_BELOW_CLR_n_ADDR(n),val) +#define HWIO_IPA_YELLOW_MARKER_BELOW_CLR_n_ENDPOINTS_BMSK 0xffffffff +#define HWIO_IPA_YELLOW_MARKER_BELOW_CLR_n_ENDPOINTS_SHFT 0x0 + +#define HWIO_IPA_RED_MARKER_BELOW_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000280 + 0x4 * (n)) +#define HWIO_IPA_RED_MARKER_BELOW_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000280 + 0x4 * (n)) +#define HWIO_IPA_RED_MARKER_BELOW_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000280 + 0x4 * (n)) +#define HWIO_IPA_RED_MARKER_BELOW_n_RMSK 0xffffffff +#define HWIO_IPA_RED_MARKER_BELOW_n_MAXn 1 +#define HWIO_IPA_RED_MARKER_BELOW_n_ATTR 0x1 +#define HWIO_IPA_RED_MARKER_BELOW_n_INI(n) \ + in_dword_masked(HWIO_IPA_RED_MARKER_BELOW_n_ADDR(n), HWIO_IPA_RED_MARKER_BELOW_n_RMSK) +#define HWIO_IPA_RED_MARKER_BELOW_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_RED_MARKER_BELOW_n_ADDR(n), mask) +#define HWIO_IPA_RED_MARKER_BELOW_n_ENDPOINTS_BMSK 0xffffffff +#define HWIO_IPA_RED_MARKER_BELOW_n_ENDPOINTS_SHFT 0x0 + +#define HWIO_IPA_RED_MARKER_BELOW_EN_n_ADDR(n) (IPA_CFG_REG_BASE + 0x000002a0 + 0x4 * (n)) +#define HWIO_IPA_RED_MARKER_BELOW_EN_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x000002a0 + 0x4 * (n)) +#define HWIO_IPA_RED_MARKER_BELOW_EN_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x000002a0 + 0x4 * (n)) +#define HWIO_IPA_RED_MARKER_BELOW_EN_n_RMSK 0xffffffff +#define HWIO_IPA_RED_MARKER_BELOW_EN_n_MAXn 1 +#define HWIO_IPA_RED_MARKER_BELOW_EN_n_ATTR 0x3 +#define HWIO_IPA_RED_MARKER_BELOW_EN_n_INI(n) \ + in_dword_masked(HWIO_IPA_RED_MARKER_BELOW_EN_n_ADDR(n), HWIO_IPA_RED_MARKER_BELOW_EN_n_RMSK) +#define HWIO_IPA_RED_MARKER_BELOW_EN_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_RED_MARKER_BELOW_EN_n_ADDR(n), mask) +#define HWIO_IPA_RED_MARKER_BELOW_EN_n_OUTI(n,val) \ + out_dword(HWIO_IPA_RED_MARKER_BELOW_EN_n_ADDR(n),val) +#define HWIO_IPA_RED_MARKER_BELOW_EN_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_RED_MARKER_BELOW_EN_n_ADDR(n),mask,val,HWIO_IPA_RED_MARKER_BELOW_EN_n_INI(n)) +#define HWIO_IPA_RED_MARKER_BELOW_EN_n_ENDPOINTS_BMSK 0xffffffff +#define HWIO_IPA_RED_MARKER_BELOW_EN_n_ENDPOINTS_SHFT 0x0 + +#define HWIO_IPA_RED_MARKER_BELOW_CLR_n_ADDR(n) (IPA_CFG_REG_BASE + 0x000002c0 + 0x4 * (n)) +#define HWIO_IPA_RED_MARKER_BELOW_CLR_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x000002c0 + 0x4 * (n)) +#define HWIO_IPA_RED_MARKER_BELOW_CLR_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x000002c0 + 0x4 * (n)) +#define HWIO_IPA_RED_MARKER_BELOW_CLR_n_RMSK 0xffffffff +#define HWIO_IPA_RED_MARKER_BELOW_CLR_n_MAXn 1 +#define HWIO_IPA_RED_MARKER_BELOW_CLR_n_ATTR 0x2 +#define HWIO_IPA_RED_MARKER_BELOW_CLR_n_OUTI(n,val) \ + out_dword(HWIO_IPA_RED_MARKER_BELOW_CLR_n_ADDR(n),val) +#define HWIO_IPA_RED_MARKER_BELOW_CLR_n_ENDPOINTS_BMSK 0xffffffff +#define HWIO_IPA_RED_MARKER_BELOW_CLR_n_ENDPOINTS_SHFT 0x0 + +#define HWIO_IPA_YELLOW_MARKER_SHADOW_n_ADDR(n) (IPA_CFG_REG_BASE + 0x000002e0 + 0x4 * (n)) +#define HWIO_IPA_YELLOW_MARKER_SHADOW_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x000002e0 + 0x4 * (n)) +#define HWIO_IPA_YELLOW_MARKER_SHADOW_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x000002e0 + 0x4 * (n)) +#define HWIO_IPA_YELLOW_MARKER_SHADOW_n_RMSK 0xffffffff +#define HWIO_IPA_YELLOW_MARKER_SHADOW_n_MAXn 1 +#define HWIO_IPA_YELLOW_MARKER_SHADOW_n_ATTR 0x1 +#define HWIO_IPA_YELLOW_MARKER_SHADOW_n_INI(n) \ + in_dword_masked(HWIO_IPA_YELLOW_MARKER_SHADOW_n_ADDR(n), HWIO_IPA_YELLOW_MARKER_SHADOW_n_RMSK) +#define HWIO_IPA_YELLOW_MARKER_SHADOW_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_YELLOW_MARKER_SHADOW_n_ADDR(n), mask) +#define HWIO_IPA_YELLOW_MARKER_SHADOW_n_ENDPOINTS_BMSK 0xffffffff +#define HWIO_IPA_YELLOW_MARKER_SHADOW_n_ENDPOINTS_SHFT 0x0 + +#define HWIO_IPA_RED_MARKER_SHADOW_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000300 + 0x4 * (n)) +#define HWIO_IPA_RED_MARKER_SHADOW_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000300 + 0x4 * (n)) +#define HWIO_IPA_RED_MARKER_SHADOW_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000300 + 0x4 * (n)) +#define HWIO_IPA_RED_MARKER_SHADOW_n_RMSK 0xffffffff +#define HWIO_IPA_RED_MARKER_SHADOW_n_MAXn 1 +#define HWIO_IPA_RED_MARKER_SHADOW_n_ATTR 0x1 +#define HWIO_IPA_RED_MARKER_SHADOW_n_INI(n) \ + in_dword_masked(HWIO_IPA_RED_MARKER_SHADOW_n_ADDR(n), HWIO_IPA_RED_MARKER_SHADOW_n_RMSK) +#define HWIO_IPA_RED_MARKER_SHADOW_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_RED_MARKER_SHADOW_n_ADDR(n), mask) +#define HWIO_IPA_RED_MARKER_SHADOW_n_ENDPOINTS_BMSK 0xffffffff +#define HWIO_IPA_RED_MARKER_SHADOW_n_ENDPOINTS_SHFT 0x0 + +#define HWIO_IPA_YELLOW_MARKER_ABOVE_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000320 + 0x4 * (n)) +#define HWIO_IPA_YELLOW_MARKER_ABOVE_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000320 + 0x4 * (n)) +#define HWIO_IPA_YELLOW_MARKER_ABOVE_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000320 + 0x4 * (n)) +#define HWIO_IPA_YELLOW_MARKER_ABOVE_n_RMSK 0xffffffff +#define HWIO_IPA_YELLOW_MARKER_ABOVE_n_MAXn 1 +#define HWIO_IPA_YELLOW_MARKER_ABOVE_n_ATTR 0x1 +#define HWIO_IPA_YELLOW_MARKER_ABOVE_n_INI(n) \ + in_dword_masked(HWIO_IPA_YELLOW_MARKER_ABOVE_n_ADDR(n), HWIO_IPA_YELLOW_MARKER_ABOVE_n_RMSK) +#define HWIO_IPA_YELLOW_MARKER_ABOVE_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_YELLOW_MARKER_ABOVE_n_ADDR(n), mask) +#define HWIO_IPA_YELLOW_MARKER_ABOVE_n_ENDPOINTS_BMSK 0xffffffff +#define HWIO_IPA_YELLOW_MARKER_ABOVE_n_ENDPOINTS_SHFT 0x0 + +#define HWIO_IPA_YELLOW_MARKER_ABOVE_EN_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000340 + 0x4 * (n)) +#define HWIO_IPA_YELLOW_MARKER_ABOVE_EN_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000340 + 0x4 * (n)) +#define HWIO_IPA_YELLOW_MARKER_ABOVE_EN_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000340 + 0x4 * (n)) +#define HWIO_IPA_YELLOW_MARKER_ABOVE_EN_n_RMSK 0xffffffff +#define HWIO_IPA_YELLOW_MARKER_ABOVE_EN_n_MAXn 1 +#define HWIO_IPA_YELLOW_MARKER_ABOVE_EN_n_ATTR 0x3 +#define HWIO_IPA_YELLOW_MARKER_ABOVE_EN_n_INI(n) \ + in_dword_masked(HWIO_IPA_YELLOW_MARKER_ABOVE_EN_n_ADDR(n), HWIO_IPA_YELLOW_MARKER_ABOVE_EN_n_RMSK) +#define HWIO_IPA_YELLOW_MARKER_ABOVE_EN_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_YELLOW_MARKER_ABOVE_EN_n_ADDR(n), mask) +#define HWIO_IPA_YELLOW_MARKER_ABOVE_EN_n_OUTI(n,val) \ + out_dword(HWIO_IPA_YELLOW_MARKER_ABOVE_EN_n_ADDR(n),val) +#define HWIO_IPA_YELLOW_MARKER_ABOVE_EN_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_YELLOW_MARKER_ABOVE_EN_n_ADDR(n),mask,val,HWIO_IPA_YELLOW_MARKER_ABOVE_EN_n_INI(n)) +#define HWIO_IPA_YELLOW_MARKER_ABOVE_EN_n_ENDPOINTS_BMSK 0xffffffff +#define HWIO_IPA_YELLOW_MARKER_ABOVE_EN_n_ENDPOINTS_SHFT 0x0 + +#define HWIO_IPA_YELLOW_MARKER_ABOVE_CLR_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000360 + 0x4 * (n)) +#define HWIO_IPA_YELLOW_MARKER_ABOVE_CLR_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000360 + 0x4 * (n)) +#define HWIO_IPA_YELLOW_MARKER_ABOVE_CLR_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000360 + 0x4 * (n)) +#define HWIO_IPA_YELLOW_MARKER_ABOVE_CLR_n_RMSK 0xffffffff +#define HWIO_IPA_YELLOW_MARKER_ABOVE_CLR_n_MAXn 1 +#define HWIO_IPA_YELLOW_MARKER_ABOVE_CLR_n_ATTR 0x2 +#define HWIO_IPA_YELLOW_MARKER_ABOVE_CLR_n_OUTI(n,val) \ + out_dword(HWIO_IPA_YELLOW_MARKER_ABOVE_CLR_n_ADDR(n),val) +#define HWIO_IPA_YELLOW_MARKER_ABOVE_CLR_n_ENDPOINTS_BMSK 0xffffffff +#define HWIO_IPA_YELLOW_MARKER_ABOVE_CLR_n_ENDPOINTS_SHFT 0x0 + +#define HWIO_IPA_RED_MARKER_ABOVE_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000380 + 0x4 * (n)) +#define HWIO_IPA_RED_MARKER_ABOVE_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000380 + 0x4 * (n)) +#define HWIO_IPA_RED_MARKER_ABOVE_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000380 + 0x4 * (n)) +#define HWIO_IPA_RED_MARKER_ABOVE_n_RMSK 0xffffffff +#define HWIO_IPA_RED_MARKER_ABOVE_n_MAXn 1 +#define HWIO_IPA_RED_MARKER_ABOVE_n_ATTR 0x1 +#define HWIO_IPA_RED_MARKER_ABOVE_n_INI(n) \ + in_dword_masked(HWIO_IPA_RED_MARKER_ABOVE_n_ADDR(n), HWIO_IPA_RED_MARKER_ABOVE_n_RMSK) +#define HWIO_IPA_RED_MARKER_ABOVE_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_RED_MARKER_ABOVE_n_ADDR(n), mask) +#define HWIO_IPA_RED_MARKER_ABOVE_n_ENDPOINTS_BMSK 0xffffffff +#define HWIO_IPA_RED_MARKER_ABOVE_n_ENDPOINTS_SHFT 0x0 + +#define HWIO_IPA_RED_MARKER_ABOVE_EN_n_ADDR(n) (IPA_CFG_REG_BASE + 0x000003a0 + 0x4 * (n)) +#define HWIO_IPA_RED_MARKER_ABOVE_EN_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x000003a0 + 0x4 * (n)) +#define HWIO_IPA_RED_MARKER_ABOVE_EN_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x000003a0 + 0x4 * (n)) +#define HWIO_IPA_RED_MARKER_ABOVE_EN_n_RMSK 0xffffffff +#define HWIO_IPA_RED_MARKER_ABOVE_EN_n_MAXn 1 +#define HWIO_IPA_RED_MARKER_ABOVE_EN_n_ATTR 0x3 +#define HWIO_IPA_RED_MARKER_ABOVE_EN_n_INI(n) \ + in_dword_masked(HWIO_IPA_RED_MARKER_ABOVE_EN_n_ADDR(n), HWIO_IPA_RED_MARKER_ABOVE_EN_n_RMSK) +#define HWIO_IPA_RED_MARKER_ABOVE_EN_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_RED_MARKER_ABOVE_EN_n_ADDR(n), mask) +#define HWIO_IPA_RED_MARKER_ABOVE_EN_n_OUTI(n,val) \ + out_dword(HWIO_IPA_RED_MARKER_ABOVE_EN_n_ADDR(n),val) +#define HWIO_IPA_RED_MARKER_ABOVE_EN_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_RED_MARKER_ABOVE_EN_n_ADDR(n),mask,val,HWIO_IPA_RED_MARKER_ABOVE_EN_n_INI(n)) +#define HWIO_IPA_RED_MARKER_ABOVE_EN_n_ENDPOINTS_BMSK 0xffffffff +#define HWIO_IPA_RED_MARKER_ABOVE_EN_n_ENDPOINTS_SHFT 0x0 + +#define HWIO_IPA_RED_MARKER_ABOVE_CLR_n_ADDR(n) (IPA_CFG_REG_BASE + 0x000003c0 + 0x4 * (n)) +#define HWIO_IPA_RED_MARKER_ABOVE_CLR_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x000003c0 + 0x4 * (n)) +#define HWIO_IPA_RED_MARKER_ABOVE_CLR_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x000003c0 + 0x4 * (n)) +#define HWIO_IPA_RED_MARKER_ABOVE_CLR_n_RMSK 0xffffffff +#define HWIO_IPA_RED_MARKER_ABOVE_CLR_n_MAXn 1 +#define HWIO_IPA_RED_MARKER_ABOVE_CLR_n_ATTR 0x2 +#define HWIO_IPA_RED_MARKER_ABOVE_CLR_n_OUTI(n,val) \ + out_dword(HWIO_IPA_RED_MARKER_ABOVE_CLR_n_ADDR(n),val) +#define HWIO_IPA_RED_MARKER_ABOVE_CLR_n_ENDPOINTS_BMSK 0xffffffff +#define HWIO_IPA_RED_MARKER_ABOVE_CLR_n_ENDPOINTS_SHFT 0x0 + +#define HWIO_IPA_FILT_ROUT_CACHE_CFG_ADDR (IPA_CFG_REG_BASE + 0x00000400) +#define HWIO_IPA_FILT_ROUT_CACHE_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000400) +#define HWIO_IPA_FILT_ROUT_CACHE_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000400) +#define HWIO_IPA_FILT_ROUT_CACHE_CFG_RMSK 0xffff0111 +#define HWIO_IPA_FILT_ROUT_CACHE_CFG_ATTR 0x3 +#define HWIO_IPA_FILT_ROUT_CACHE_CFG_IN \ + in_dword_masked(HWIO_IPA_FILT_ROUT_CACHE_CFG_ADDR, HWIO_IPA_FILT_ROUT_CACHE_CFG_RMSK) +#define HWIO_IPA_FILT_ROUT_CACHE_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_FILT_ROUT_CACHE_CFG_ADDR, m) +#define HWIO_IPA_FILT_ROUT_CACHE_CFG_OUT(v) \ + out_dword(HWIO_IPA_FILT_ROUT_CACHE_CFG_ADDR,v) +#define HWIO_IPA_FILT_ROUT_CACHE_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_FILT_ROUT_CACHE_CFG_ADDR,m,v,HWIO_IPA_FILT_ROUT_CACHE_CFG_IN) +#define HWIO_IPA_FILT_ROUT_CACHE_CFG_CACHE_LRU_EVICTION_THRESHOLD_BMSK 0xffff0000 +#define HWIO_IPA_FILT_ROUT_CACHE_CFG_CACHE_LRU_EVICTION_THRESHOLD_SHFT 0x10 +#define HWIO_IPA_FILT_ROUT_CACHE_CFG_CACHE_LOW_PRIORITY_HASHABLE_HIT_DISABLE_BMSK 0x100 +#define HWIO_IPA_FILT_ROUT_CACHE_CFG_CACHE_LOW_PRIORITY_HASHABLE_HIT_DISABLE_SHFT 0x8 +#define HWIO_IPA_FILT_ROUT_CACHE_CFG_IPA_FILTER_CACHE_EN_BMSK 0x10 +#define HWIO_IPA_FILT_ROUT_CACHE_CFG_IPA_FILTER_CACHE_EN_SHFT 0x4 +#define HWIO_IPA_FILT_ROUT_CACHE_CFG_IPA_ROUTER_CACHE_EN_BMSK 0x1 +#define HWIO_IPA_FILT_ROUT_CACHE_CFG_IPA_ROUTER_CACHE_EN_SHFT 0x0 + +#define HWIO_IPA_FILT_ROUT_CACHE_REDUCE_CFG_ADDR (IPA_CFG_REG_BASE + 0x000004e0) +#define HWIO_IPA_FILT_ROUT_CACHE_REDUCE_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000004e0) +#define HWIO_IPA_FILT_ROUT_CACHE_REDUCE_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000004e0) +#define HWIO_IPA_FILT_ROUT_CACHE_REDUCE_CFG_RMSK 0xffff11 +#define HWIO_IPA_FILT_ROUT_CACHE_REDUCE_CFG_ATTR 0x3 +#define HWIO_IPA_FILT_ROUT_CACHE_REDUCE_CFG_IN \ + in_dword_masked(HWIO_IPA_FILT_ROUT_CACHE_REDUCE_CFG_ADDR, HWIO_IPA_FILT_ROUT_CACHE_REDUCE_CFG_RMSK) +#define HWIO_IPA_FILT_ROUT_CACHE_REDUCE_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_FILT_ROUT_CACHE_REDUCE_CFG_ADDR, m) +#define HWIO_IPA_FILT_ROUT_CACHE_REDUCE_CFG_OUT(v) \ + out_dword(HWIO_IPA_FILT_ROUT_CACHE_REDUCE_CFG_ADDR,v) +#define HWIO_IPA_FILT_ROUT_CACHE_REDUCE_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_FILT_ROUT_CACHE_REDUCE_CFG_ADDR,m,v,HWIO_IPA_FILT_ROUT_CACHE_REDUCE_CFG_IN) +#define HWIO_IPA_FILT_ROUT_CACHE_REDUCE_CFG_IPA_FILTER_CACHE_REDUCE_LEVEL_BMSK 0xff0000 +#define HWIO_IPA_FILT_ROUT_CACHE_REDUCE_CFG_IPA_FILTER_CACHE_REDUCE_LEVEL_SHFT 0x10 +#define HWIO_IPA_FILT_ROUT_CACHE_REDUCE_CFG_IPA_ROUTER_CACHE_REDUCE_LEVEL_BMSK 0xff00 +#define HWIO_IPA_FILT_ROUT_CACHE_REDUCE_CFG_IPA_ROUTER_CACHE_REDUCE_LEVEL_SHFT 0x8 +#define HWIO_IPA_FILT_ROUT_CACHE_REDUCE_CFG_IPA_FILTER_CACHE_REDUCE_EN_BMSK 0x10 +#define HWIO_IPA_FILT_ROUT_CACHE_REDUCE_CFG_IPA_FILTER_CACHE_REDUCE_EN_SHFT 0x4 +#define HWIO_IPA_FILT_ROUT_CACHE_REDUCE_CFG_IPA_ROUTER_CACHE_REDUCE_EN_BMSK 0x1 +#define HWIO_IPA_FILT_ROUT_CACHE_REDUCE_CFG_IPA_ROUTER_CACHE_REDUCE_EN_SHFT 0x0 + +#define HWIO_IPA_FILT_ROUT_CACHE_FLUSH_ADDR (IPA_CFG_REG_BASE + 0x00000404) +#define HWIO_IPA_FILT_ROUT_CACHE_FLUSH_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000404) +#define HWIO_IPA_FILT_ROUT_CACHE_FLUSH_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000404) +#define HWIO_IPA_FILT_ROUT_CACHE_FLUSH_RMSK 0x11 +#define HWIO_IPA_FILT_ROUT_CACHE_FLUSH_ATTR 0x2 +#define HWIO_IPA_FILT_ROUT_CACHE_FLUSH_OUT(v) \ + out_dword(HWIO_IPA_FILT_ROUT_CACHE_FLUSH_ADDR,v) +#define HWIO_IPA_FILT_ROUT_CACHE_FLUSH_IPA_FILTER_CACHE_FLUSH_BMSK 0x10 +#define HWIO_IPA_FILT_ROUT_CACHE_FLUSH_IPA_FILTER_CACHE_FLUSH_SHFT 0x4 +#define HWIO_IPA_FILT_ROUT_CACHE_FLUSH_IPA_ROUTER_CACHE_FLUSH_BMSK 0x1 +#define HWIO_IPA_FILT_ROUT_CACHE_FLUSH_IPA_ROUTER_CACHE_FLUSH_SHFT 0x0 + +#define HWIO_IPA_FILT_ROUT_CFG_ADDR (IPA_CFG_REG_BASE + 0x00000408) +#define HWIO_IPA_FILT_ROUT_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000408) +#define HWIO_IPA_FILT_ROUT_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000408) +#define HWIO_IPA_FILT_ROUT_CFG_RMSK 0x111 +#define HWIO_IPA_FILT_ROUT_CFG_ATTR 0x3 +#define HWIO_IPA_FILT_ROUT_CFG_IN \ + in_dword_masked(HWIO_IPA_FILT_ROUT_CFG_ADDR, HWIO_IPA_FILT_ROUT_CFG_RMSK) +#define HWIO_IPA_FILT_ROUT_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_FILT_ROUT_CFG_ADDR, m) +#define HWIO_IPA_FILT_ROUT_CFG_OUT(v) \ + out_dword(HWIO_IPA_FILT_ROUT_CFG_ADDR,v) +#define HWIO_IPA_FILT_ROUT_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_FILT_ROUT_CFG_ADDR,m,v,HWIO_IPA_FILT_ROUT_CFG_IN) +#define HWIO_IPA_FILT_ROUT_CFG_FILT_ROUT_DATA_CACHE_EN_BMSK 0x100 +#define HWIO_IPA_FILT_ROUT_CFG_FILT_ROUT_DATA_CACHE_EN_SHFT 0x8 +#define HWIO_IPA_FILT_ROUT_CFG_FILTER_PREFETCH_EN_BMSK 0x10 +#define HWIO_IPA_FILT_ROUT_CFG_FILTER_PREFETCH_EN_SHFT 0x4 +#define HWIO_IPA_FILT_ROUT_CFG_ROUTER_PREFETCH_EN_BMSK 0x1 +#define HWIO_IPA_FILT_ROUT_CFG_ROUTER_PREFETCH_EN_SHFT 0x0 + +#define HWIO_IPA_IPV4_FILTER_INIT_VALUES_ADDR (IPA_CFG_REG_BASE + 0x0000040c) +#define HWIO_IPA_IPV4_FILTER_INIT_VALUES_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000040c) +#define HWIO_IPA_IPV4_FILTER_INIT_VALUES_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000040c) +#define HWIO_IPA_IPV4_FILTER_INIT_VALUES_RMSK 0xffffffff +#define HWIO_IPA_IPV4_FILTER_INIT_VALUES_ATTR 0x1 +#define HWIO_IPA_IPV4_FILTER_INIT_VALUES_IN \ + in_dword_masked(HWIO_IPA_IPV4_FILTER_INIT_VALUES_ADDR, HWIO_IPA_IPV4_FILTER_INIT_VALUES_RMSK) +#define HWIO_IPA_IPV4_FILTER_INIT_VALUES_INM(m) \ + in_dword_masked(HWIO_IPA_IPV4_FILTER_INIT_VALUES_ADDR, m) +#define HWIO_IPA_IPV4_FILTER_INIT_VALUES_IP_V4_FILTER_INIT_NON_HASHED_ADDR_BMSK 0xffff0000 +#define HWIO_IPA_IPV4_FILTER_INIT_VALUES_IP_V4_FILTER_INIT_NON_HASHED_ADDR_SHFT 0x10 +#define HWIO_IPA_IPV4_FILTER_INIT_VALUES_IP_V4_FILTER_INIT_HASHED_ADDR_BMSK 0xffff +#define HWIO_IPA_IPV4_FILTER_INIT_VALUES_IP_V4_FILTER_INIT_HASHED_ADDR_SHFT 0x0 + +#define HWIO_IPA_IPV6_FILTER_INIT_VALUES_ADDR (IPA_CFG_REG_BASE + 0x00000410) +#define HWIO_IPA_IPV6_FILTER_INIT_VALUES_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000410) +#define HWIO_IPA_IPV6_FILTER_INIT_VALUES_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000410) +#define HWIO_IPA_IPV6_FILTER_INIT_VALUES_RMSK 0xffffffff +#define HWIO_IPA_IPV6_FILTER_INIT_VALUES_ATTR 0x1 +#define HWIO_IPA_IPV6_FILTER_INIT_VALUES_IN \ + in_dword_masked(HWIO_IPA_IPV6_FILTER_INIT_VALUES_ADDR, HWIO_IPA_IPV6_FILTER_INIT_VALUES_RMSK) +#define HWIO_IPA_IPV6_FILTER_INIT_VALUES_INM(m) \ + in_dword_masked(HWIO_IPA_IPV6_FILTER_INIT_VALUES_ADDR, m) +#define HWIO_IPA_IPV6_FILTER_INIT_VALUES_IP_V6_FILTER_INIT_NON_HASHED_ADDR_BMSK 0xffff0000 +#define HWIO_IPA_IPV6_FILTER_INIT_VALUES_IP_V6_FILTER_INIT_NON_HASHED_ADDR_SHFT 0x10 +#define HWIO_IPA_IPV6_FILTER_INIT_VALUES_IP_V6_FILTER_INIT_HASHED_ADDR_BMSK 0xffff +#define HWIO_IPA_IPV6_FILTER_INIT_VALUES_IP_V6_FILTER_INIT_HASHED_ADDR_SHFT 0x0 + +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_0_ADDR (IPA_CFG_REG_BASE + 0x00000414) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_0_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000414) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_0_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000414) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_0_RMSK 0xffffffff +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_0_ATTR 0x1 +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_0_IN \ + in_dword_masked(HWIO_IPA_IPV4_NAT_INIT_VALUES_0_ADDR, HWIO_IPA_IPV4_NAT_INIT_VALUES_0_RMSK) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_0_INM(m) \ + in_dword_masked(HWIO_IPA_IPV4_NAT_INIT_VALUES_0_ADDR, m) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_0_IP_V4_NAT_INIT_RULES_ADDR_BMSK 0xffffffff +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_0_IP_V4_NAT_INIT_RULES_ADDR_SHFT 0x0 + +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_0_MSB_ADDR (IPA_CFG_REG_BASE + 0x00000418) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_0_MSB_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000418) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_0_MSB_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000418) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_0_MSB_RMSK 0xffffffff +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_0_MSB_ATTR 0x1 +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_0_MSB_IN \ + in_dword_masked(HWIO_IPA_IPV4_NAT_INIT_VALUES_0_MSB_ADDR, HWIO_IPA_IPV4_NAT_INIT_VALUES_0_MSB_RMSK) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_0_MSB_INM(m) \ + in_dword_masked(HWIO_IPA_IPV4_NAT_INIT_VALUES_0_MSB_ADDR, m) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_0_MSB_IP_V4_NAT_INIT_RULES_ADDR_BMSK 0xffffffff +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_0_MSB_IP_V4_NAT_INIT_RULES_ADDR_SHFT 0x0 + +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_1_ADDR (IPA_CFG_REG_BASE + 0x0000041c) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_1_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000041c) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_1_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000041c) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_1_RMSK 0xffffffff +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_1_ATTR 0x1 +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_1_IN \ + in_dword_masked(HWIO_IPA_IPV4_NAT_INIT_VALUES_1_ADDR, HWIO_IPA_IPV4_NAT_INIT_VALUES_1_RMSK) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_1_INM(m) \ + in_dword_masked(HWIO_IPA_IPV4_NAT_INIT_VALUES_1_ADDR, m) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_1_IP_V4_NAT_INIT_EXP_RULES_ADDR_BMSK 0xffffffff +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_1_IP_V4_NAT_INIT_EXP_RULES_ADDR_SHFT 0x0 + +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_1_MSB_ADDR (IPA_CFG_REG_BASE + 0x00000420) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_1_MSB_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000420) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_1_MSB_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000420) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_1_MSB_RMSK 0xffffffff +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_1_MSB_ATTR 0x1 +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_1_MSB_IN \ + in_dword_masked(HWIO_IPA_IPV4_NAT_INIT_VALUES_1_MSB_ADDR, HWIO_IPA_IPV4_NAT_INIT_VALUES_1_MSB_RMSK) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_1_MSB_INM(m) \ + in_dword_masked(HWIO_IPA_IPV4_NAT_INIT_VALUES_1_MSB_ADDR, m) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_1_MSB_IP_V4_NAT_INIT_EXP_RULES_ADDR_BMSK 0xffffffff +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_1_MSB_IP_V4_NAT_INIT_EXP_RULES_ADDR_SHFT 0x0 + +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_2_ADDR (IPA_CFG_REG_BASE + 0x00000424) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_2_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000424) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_2_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000424) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_2_RMSK 0xffffffff +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_2_ATTR 0x1 +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_2_IN \ + in_dword_masked(HWIO_IPA_IPV4_NAT_INIT_VALUES_2_ADDR, HWIO_IPA_IPV4_NAT_INIT_VALUES_2_RMSK) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_2_INM(m) \ + in_dword_masked(HWIO_IPA_IPV4_NAT_INIT_VALUES_2_ADDR, m) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_2_IP_V4_NAT_INIT_INDEX_TABLE_ADDR_BMSK 0xffffffff +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_2_IP_V4_NAT_INIT_INDEX_TABLE_ADDR_SHFT 0x0 + +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_2_MSB_ADDR (IPA_CFG_REG_BASE + 0x00000428) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_2_MSB_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000428) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_2_MSB_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000428) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_2_MSB_RMSK 0xffffffff +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_2_MSB_ATTR 0x1 +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_2_MSB_IN \ + in_dword_masked(HWIO_IPA_IPV4_NAT_INIT_VALUES_2_MSB_ADDR, HWIO_IPA_IPV4_NAT_INIT_VALUES_2_MSB_RMSK) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_2_MSB_INM(m) \ + in_dword_masked(HWIO_IPA_IPV4_NAT_INIT_VALUES_2_MSB_ADDR, m) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_2_MSB_IP_V4_NAT_INIT_INDEX_TABLE_ADDR_BMSK 0xffffffff +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_2_MSB_IP_V4_NAT_INIT_INDEX_TABLE_ADDR_SHFT 0x0 + +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_3_ADDR (IPA_CFG_REG_BASE + 0x0000042c) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_3_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000042c) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_3_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000042c) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_3_RMSK 0xffffffff +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_3_ATTR 0x1 +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_3_IN \ + in_dword_masked(HWIO_IPA_IPV4_NAT_INIT_VALUES_3_ADDR, HWIO_IPA_IPV4_NAT_INIT_VALUES_3_RMSK) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_3_INM(m) \ + in_dword_masked(HWIO_IPA_IPV4_NAT_INIT_VALUES_3_ADDR, m) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_3_IP_V4_NAT_INIT_INDEX_TABLE_EXP_ADDR_BMSK 0xffffffff +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_3_IP_V4_NAT_INIT_INDEX_TABLE_EXP_ADDR_SHFT 0x0 + +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_3_MSB_ADDR (IPA_CFG_REG_BASE + 0x00000430) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_3_MSB_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000430) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_3_MSB_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000430) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_3_MSB_RMSK 0xffffffff +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_3_MSB_ATTR 0x1 +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_3_MSB_IN \ + in_dword_masked(HWIO_IPA_IPV4_NAT_INIT_VALUES_3_MSB_ADDR, HWIO_IPA_IPV4_NAT_INIT_VALUES_3_MSB_RMSK) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_3_MSB_INM(m) \ + in_dword_masked(HWIO_IPA_IPV4_NAT_INIT_VALUES_3_MSB_ADDR, m) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_3_MSB_IP_V4_NAT_INIT_INDEX_TABLE_EXP_ADDR_BMSK 0xffffffff +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_3_MSB_IP_V4_NAT_INIT_INDEX_TABLE_EXP_ADDR_SHFT 0x0 + +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_4_ADDR (IPA_CFG_REG_BASE + 0x00000434) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_4_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000434) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_4_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000434) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_4_RMSK 0x3ffffff7 +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_4_ATTR 0x1 +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_4_IN \ + in_dword_masked(HWIO_IPA_IPV4_NAT_INIT_VALUES_4_ADDR, HWIO_IPA_IPV4_NAT_INIT_VALUES_4_RMSK) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_4_INM(m) \ + in_dword_masked(HWIO_IPA_IPV4_NAT_INIT_VALUES_4_ADDR, m) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_4_IP_V4_NAT_INIT_SIZE_EXP_TABLES_BMSK 0x3ff00000 +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_4_IP_V4_NAT_INIT_SIZE_EXP_TABLES_SHFT 0x14 +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_4_IP_V4_NAT_INIT_SIZE_BASE_TABLES_BMSK 0xfff00 +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_4_IP_V4_NAT_INIT_SIZE_BASE_TABLES_SHFT 0x8 +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_4_IP_V4_NAT_INIT_INDEX_TABLE_EXP_ADDR_TYPE_BMSK 0x80 +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_4_IP_V4_NAT_INIT_INDEX_TABLE_EXP_ADDR_TYPE_SHFT 0x7 +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_4_IP_V4_NAT_INIT_INDEX_TABLE_ADDR_TYPE_BMSK 0x40 +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_4_IP_V4_NAT_INIT_INDEX_TABLE_ADDR_TYPE_SHFT 0x6 +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_4_IP_V4_NAT_INIT_EXP_RULES_ADDR_TYPE_BMSK 0x20 +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_4_IP_V4_NAT_INIT_EXP_RULES_ADDR_TYPE_SHFT 0x5 +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_4_IP_V4_NAT_INIT_RULES_ADDR_TYPE_BMSK 0x10 +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_4_IP_V4_NAT_INIT_RULES_ADDR_TYPE_SHFT 0x4 +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_4_IP_V4_NAT_INIT_TABLE_INDEX_BMSK 0x7 +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_4_IP_V4_NAT_INIT_TABLE_INDEX_SHFT 0x0 + +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_5_ADDR (IPA_CFG_REG_BASE + 0x00000438) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_5_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000438) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_5_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000438) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_5_RMSK 0xfffff +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_5_ATTR 0x1 +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_5_IN \ + in_dword_masked(HWIO_IPA_IPV4_NAT_INIT_VALUES_5_ADDR, HWIO_IPA_IPV4_NAT_INIT_VALUES_5_RMSK) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_5_INM(m) \ + in_dword_masked(HWIO_IPA_IPV4_NAT_INIT_VALUES_5_ADDR, m) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_5_IP_V4_NAT_INIT_PDN_CONFIG_TABLE_ADDR_BMSK 0xfffff +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_5_IP_V4_NAT_INIT_PDN_CONFIG_TABLE_ADDR_SHFT 0x0 + +#define HWIO_IPA_IPV4_ROUTE_INIT_VALUES_ADDR (IPA_CFG_REG_BASE + 0x0000043c) +#define HWIO_IPA_IPV4_ROUTE_INIT_VALUES_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000043c) +#define HWIO_IPA_IPV4_ROUTE_INIT_VALUES_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000043c) +#define HWIO_IPA_IPV4_ROUTE_INIT_VALUES_RMSK 0xffffffff +#define HWIO_IPA_IPV4_ROUTE_INIT_VALUES_ATTR 0x1 +#define HWIO_IPA_IPV4_ROUTE_INIT_VALUES_IN \ + in_dword_masked(HWIO_IPA_IPV4_ROUTE_INIT_VALUES_ADDR, HWIO_IPA_IPV4_ROUTE_INIT_VALUES_RMSK) +#define HWIO_IPA_IPV4_ROUTE_INIT_VALUES_INM(m) \ + in_dword_masked(HWIO_IPA_IPV4_ROUTE_INIT_VALUES_ADDR, m) +#define HWIO_IPA_IPV4_ROUTE_INIT_VALUES_IP_V4_ROUTE_INIT_NON_HASHED_ADDR_BMSK 0xffff0000 +#define HWIO_IPA_IPV4_ROUTE_INIT_VALUES_IP_V4_ROUTE_INIT_NON_HASHED_ADDR_SHFT 0x10 +#define HWIO_IPA_IPV4_ROUTE_INIT_VALUES_IP_V4_ROUTE_INIT_HASHED_ADDR_BMSK 0xffff +#define HWIO_IPA_IPV4_ROUTE_INIT_VALUES_IP_V4_ROUTE_INIT_HASHED_ADDR_SHFT 0x0 + +#define HWIO_IPA_IPV6_ROUTE_INIT_VALUES_ADDR (IPA_CFG_REG_BASE + 0x00000440) +#define HWIO_IPA_IPV6_ROUTE_INIT_VALUES_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000440) +#define HWIO_IPA_IPV6_ROUTE_INIT_VALUES_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000440) +#define HWIO_IPA_IPV6_ROUTE_INIT_VALUES_RMSK 0xffffffff +#define HWIO_IPA_IPV6_ROUTE_INIT_VALUES_ATTR 0x1 +#define HWIO_IPA_IPV6_ROUTE_INIT_VALUES_IN \ + in_dword_masked(HWIO_IPA_IPV6_ROUTE_INIT_VALUES_ADDR, HWIO_IPA_IPV6_ROUTE_INIT_VALUES_RMSK) +#define HWIO_IPA_IPV6_ROUTE_INIT_VALUES_INM(m) \ + in_dword_masked(HWIO_IPA_IPV6_ROUTE_INIT_VALUES_ADDR, m) +#define HWIO_IPA_IPV6_ROUTE_INIT_VALUES_IP_V6_ROUTE_INIT_NON_HASHED_ADDR_BMSK 0xffff0000 +#define HWIO_IPA_IPV6_ROUTE_INIT_VALUES_IP_V6_ROUTE_INIT_NON_HASHED_ADDR_SHFT 0x10 +#define HWIO_IPA_IPV6_ROUTE_INIT_VALUES_IP_V6_ROUTE_INIT_HASHED_ADDR_BMSK 0xffff +#define HWIO_IPA_IPV6_ROUTE_INIT_VALUES_IP_V6_ROUTE_INIT_HASHED_ADDR_SHFT 0x0 + +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_ADDR (IPA_CFG_REG_BASE + 0x00000444) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000444) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000444) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_RMSK 0xffffffff +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_ATTR 0x1 +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_IN \ + in_dword_masked(HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_ADDR, HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_RMSK) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_INM(m) \ + in_dword_masked(HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_ADDR, m) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_IP_V6_CONN_TRACK_INIT_TABLE_ADDR_BMSK 0xffffffff +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_IP_V6_CONN_TRACK_INIT_TABLE_ADDR_SHFT 0x0 + +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_MSB_ADDR (IPA_CFG_REG_BASE + 0x00000448) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_MSB_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000448) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_MSB_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000448) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_MSB_RMSK 0xffffffff +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_MSB_ATTR 0x1 +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_MSB_IN \ + in_dword_masked(HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_MSB_ADDR, HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_MSB_RMSK) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_MSB_INM(m) \ + in_dword_masked(HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_MSB_ADDR, m) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_MSB_IP_V6_CONN_TRACK_INIT_TABLE_ADDR_BMSK 0xffffffff +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_MSB_IP_V6_CONN_TRACK_INIT_TABLE_ADDR_SHFT 0x0 + +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_ADDR (IPA_CFG_REG_BASE + 0x0000044c) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000044c) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000044c) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_RMSK 0xffffffff +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_ATTR 0x1 +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_IN \ + in_dword_masked(HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_ADDR, HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_RMSK) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_INM(m) \ + in_dword_masked(HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_ADDR, m) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_IP_V6_CONN_TRACK_INIT_EXP_TABLE_ADDR_BMSK 0xffffffff +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_IP_V6_CONN_TRACK_INIT_EXP_TABLE_ADDR_SHFT 0x0 + +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_MSB_ADDR (IPA_CFG_REG_BASE + 0x00000450) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_MSB_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000450) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_MSB_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000450) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_MSB_RMSK 0xffffffff +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_MSB_ATTR 0x1 +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_MSB_IN \ + in_dword_masked(HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_MSB_ADDR, HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_MSB_RMSK) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_MSB_INM(m) \ + in_dword_masked(HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_MSB_ADDR, m) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_MSB_IP_V6_CONN_TRACK_INIT_EXP_TABLE_ADDR_BMSK 0xffffffff +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_MSB_IP_V6_CONN_TRACK_INIT_EXP_TABLE_ADDR_SHFT 0x0 + +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_2_ADDR (IPA_CFG_REG_BASE + 0x00000454) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_2_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000454) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_2_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000454) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_2_RMSK 0x3fffff37 +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_2_ATTR 0x1 +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_2_IN \ + in_dword_masked(HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_2_ADDR, HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_2_RMSK) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_2_INM(m) \ + in_dword_masked(HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_2_ADDR, m) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_2_IP_V6_CONN_TRACK_INIT_SIZE_EXP_TABLES_BMSK 0x3ff00000 +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_2_IP_V6_CONN_TRACK_INIT_SIZE_EXP_TABLES_SHFT 0x14 +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_2_IP_V6_CONN_TRACK_INIT_SIZE_BASE_TABLES_BMSK 0xfff00 +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_2_IP_V6_CONN_TRACK_INIT_SIZE_BASE_TABLES_SHFT 0x8 +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_2_IP_V6_CONN_TRACK_INIT_EXP_TABLE_ADDR_TYPE_BMSK 0x20 +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_2_IP_V6_CONN_TRACK_INIT_EXP_TABLE_ADDR_TYPE_SHFT 0x5 +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_2_IP_V6_CONN_TRACK_INIT_TABLE_ADDR_TYPE_BMSK 0x10 +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_2_IP_V6_CONN_TRACK_INIT_TABLE_ADDR_TYPE_SHFT 0x4 +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_2_IP_V6_CONN_TRACK_INIT_TABLE_INDEX_BMSK 0x7 +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_2_IP_V6_CONN_TRACK_INIT_TABLE_INDEX_SHFT 0x0 + +#define HWIO_IPA_HDR_INIT_LOCAL_VALUES_ADDR (IPA_CFG_REG_BASE + 0x00000458) +#define HWIO_IPA_HDR_INIT_LOCAL_VALUES_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000458) +#define HWIO_IPA_HDR_INIT_LOCAL_VALUES_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000458) +#define HWIO_IPA_HDR_INIT_LOCAL_VALUES_RMSK 0xffff000 +#define HWIO_IPA_HDR_INIT_LOCAL_VALUES_ATTR 0x1 +#define HWIO_IPA_HDR_INIT_LOCAL_VALUES_IN \ + in_dword_masked(HWIO_IPA_HDR_INIT_LOCAL_VALUES_ADDR, HWIO_IPA_HDR_INIT_LOCAL_VALUES_RMSK) +#define HWIO_IPA_HDR_INIT_LOCAL_VALUES_INM(m) \ + in_dword_masked(HWIO_IPA_HDR_INIT_LOCAL_VALUES_ADDR, m) +#define HWIO_IPA_HDR_INIT_LOCAL_VALUES_HDR_INIT_LOCAL_HDR_ADDR_BMSK 0xffff000 +#define HWIO_IPA_HDR_INIT_LOCAL_VALUES_HDR_INIT_LOCAL_HDR_ADDR_SHFT 0xc + +#define HWIO_IPA_HDR_INIT_SYSTEM_VALUES_ADDR (IPA_CFG_REG_BASE + 0x0000045c) +#define HWIO_IPA_HDR_INIT_SYSTEM_VALUES_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000045c) +#define HWIO_IPA_HDR_INIT_SYSTEM_VALUES_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000045c) +#define HWIO_IPA_HDR_INIT_SYSTEM_VALUES_RMSK 0xffffffff +#define HWIO_IPA_HDR_INIT_SYSTEM_VALUES_ATTR 0x1 +#define HWIO_IPA_HDR_INIT_SYSTEM_VALUES_IN \ + in_dword_masked(HWIO_IPA_HDR_INIT_SYSTEM_VALUES_ADDR, HWIO_IPA_HDR_INIT_SYSTEM_VALUES_RMSK) +#define HWIO_IPA_HDR_INIT_SYSTEM_VALUES_INM(m) \ + in_dword_masked(HWIO_IPA_HDR_INIT_SYSTEM_VALUES_ADDR, m) +#define HWIO_IPA_HDR_INIT_SYSTEM_VALUES_HDR_INIT_SYSTEM_HDR_TABLE_ADDR_BMSK 0xffffffff +#define HWIO_IPA_HDR_INIT_SYSTEM_VALUES_HDR_INIT_SYSTEM_HDR_TABLE_ADDR_SHFT 0x0 + +#define HWIO_IPA_HDR_INIT_SYSTEM_VALUES_MSB_ADDR (IPA_CFG_REG_BASE + 0x00000460) +#define HWIO_IPA_HDR_INIT_SYSTEM_VALUES_MSB_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000460) +#define HWIO_IPA_HDR_INIT_SYSTEM_VALUES_MSB_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000460) +#define HWIO_IPA_HDR_INIT_SYSTEM_VALUES_MSB_RMSK 0xffffffff +#define HWIO_IPA_HDR_INIT_SYSTEM_VALUES_MSB_ATTR 0x1 +#define HWIO_IPA_HDR_INIT_SYSTEM_VALUES_MSB_IN \ + in_dword_masked(HWIO_IPA_HDR_INIT_SYSTEM_VALUES_MSB_ADDR, HWIO_IPA_HDR_INIT_SYSTEM_VALUES_MSB_RMSK) +#define HWIO_IPA_HDR_INIT_SYSTEM_VALUES_MSB_INM(m) \ + in_dword_masked(HWIO_IPA_HDR_INIT_SYSTEM_VALUES_MSB_ADDR, m) +#define HWIO_IPA_HDR_INIT_SYSTEM_VALUES_MSB_HDR_INIT_SYSTEM_HDR_TABLE_ADDR_BMSK 0xffffffff +#define HWIO_IPA_HDR_INIT_SYSTEM_VALUES_MSB_HDR_INIT_SYSTEM_HDR_TABLE_ADDR_SHFT 0x0 + +#define HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_ADDR (IPA_CFG_REG_BASE + 0x00000464) +#define HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000464) +#define HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000464) +#define HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_RMSK 0xffffffff +#define HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_ATTR 0x1 +#define HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_IN \ + in_dword_masked(HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_ADDR, HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_RMSK) +#define HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_INM(m) \ + in_dword_masked(HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_ADDR, m) +#define HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_IMM_CMD_HDRI_PIPE_BMSK 0xff000000 +#define HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_IMM_CMD_HDRI_PIPE_SHFT 0x18 +#define HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_IMM_CMD_CONN_TRACK_PIPE_BMSK 0xff0000 +#define HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_IMM_CMD_CONN_TRACK_PIPE_SHFT 0x10 +#define HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_IMM_CMD_NAT_PIPE_BMSK 0xff00 +#define HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_IMM_CMD_NAT_PIPE_SHFT 0x8 +#define HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_IMM_CMD_FILTER_ROUTER_PIPE_BMSK 0xff +#define HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_IMM_CMD_FILTER_ROUTER_PIPE_SHFT 0x0 + +#define HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_1_ADDR (IPA_CFG_REG_BASE + 0x00000468) +#define HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_1_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000468) +#define HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_1_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000468) +#define HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_1_RMSK 0xff +#define HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_1_ATTR 0x1 +#define HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_1_IN \ + in_dword_masked(HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_1_ADDR, HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_1_RMSK) +#define HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_1_INM(m) \ + in_dword_masked(HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_1_ADDR, m) +#define HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_1_IMM_CMD_GEN_PIPE_BMSK 0xff +#define HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_1_IMM_CMD_GEN_PIPE_SHFT 0x0 + +#define HWIO_IPA_FRAG_VALUES_ADDR (IPA_CFG_REG_BASE + 0x0000046c) +#define HWIO_IPA_FRAG_VALUES_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000046c) +#define HWIO_IPA_FRAG_VALUES_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000046c) +#define HWIO_IPA_FRAG_VALUES_RMSK 0xf00ffff +#define HWIO_IPA_FRAG_VALUES_ATTR 0x3 +#define HWIO_IPA_FRAG_VALUES_IN \ + in_dword_masked(HWIO_IPA_FRAG_VALUES_ADDR, HWIO_IPA_FRAG_VALUES_RMSK) +#define HWIO_IPA_FRAG_VALUES_INM(m) \ + in_dword_masked(HWIO_IPA_FRAG_VALUES_ADDR, m) +#define HWIO_IPA_FRAG_VALUES_OUT(v) \ + out_dword(HWIO_IPA_FRAG_VALUES_ADDR,v) +#define HWIO_IPA_FRAG_VALUES_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_FRAG_VALUES_ADDR,m,v,HWIO_IPA_FRAG_VALUES_IN) +#define HWIO_IPA_FRAG_VALUES_IPA_FRAG_FAIRNESS_CNT_BMSK 0xf000000 +#define HWIO_IPA_FRAG_VALUES_IPA_FRAG_FAIRNESS_CNT_SHFT 0x18 +#define HWIO_IPA_FRAG_VALUES_IPA_FRAG_RAM_LAST_ADDR_BMSK 0xffff +#define HWIO_IPA_FRAG_VALUES_IPA_FRAG_RAM_LAST_ADDR_SHFT 0x0 + +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_ADDR (IPA_CFG_REG_BASE + 0x00000470) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000470) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000470) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_RMSK 0xffffffff +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_ATTR 0x3 +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_IN \ + in_dword_masked(HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_ADDR, HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_RMSK) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_INM(m) \ + in_dword_masked(HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_ADDR, m) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_OUT(v) \ + out_dword(HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_ADDR,v) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_ADDR,m,v,HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_IN) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_ADDR_BMSK 0xfffffff8 +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_ADDR_SHFT 0x3 +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_ZERO_BMSK 0x7 +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_ZERO_SHFT 0x0 + +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_ADDR (IPA_CFG_REG_BASE + 0x00000474) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000474) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000474) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_RMSK 0xffffffff +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_ATTR 0x3 +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_IN \ + in_dword_masked(HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_ADDR, HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_RMSK) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_ADDR, m) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_OUT(v) \ + out_dword(HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_ADDR,v) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_ADDR,m,v,HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_IN) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_ADDR_BMSK 0xffffffff +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_ADDR_SHFT 0x0 + +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_ADDR (IPA_CFG_REG_BASE + 0x00000478) +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000478) +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000478) +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_RMSK 0x3ffff +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_ATTR 0x3 +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_IN \ + in_dword_masked(HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_ADDR, HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_RMSK) +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_INM(m) \ + in_dword_masked(HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_ADDR, m) +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_OUT(v) \ + out_dword(HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_ADDR,v) +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_ADDR,m,v,HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_IN) +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_ADDR_BMSK 0x3fff8 +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_ADDR_SHFT 0x3 +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_ZERO_BMSK 0x7 +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_ZERO_SHFT 0x0 + +#define HWIO_IPA_SCND_FRAG_VALUES_ADDR (IPA_CFG_REG_BASE + 0x00000480) +#define HWIO_IPA_SCND_FRAG_VALUES_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000480) +#define HWIO_IPA_SCND_FRAG_VALUES_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000480) +#define HWIO_IPA_SCND_FRAG_VALUES_RMSK 0xf00ffff +#define HWIO_IPA_SCND_FRAG_VALUES_ATTR 0x3 +#define HWIO_IPA_SCND_FRAG_VALUES_IN \ + in_dword_masked(HWIO_IPA_SCND_FRAG_VALUES_ADDR, HWIO_IPA_SCND_FRAG_VALUES_RMSK) +#define HWIO_IPA_SCND_FRAG_VALUES_INM(m) \ + in_dword_masked(HWIO_IPA_SCND_FRAG_VALUES_ADDR, m) +#define HWIO_IPA_SCND_FRAG_VALUES_OUT(v) \ + out_dword(HWIO_IPA_SCND_FRAG_VALUES_ADDR,v) +#define HWIO_IPA_SCND_FRAG_VALUES_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_SCND_FRAG_VALUES_ADDR,m,v,HWIO_IPA_SCND_FRAG_VALUES_IN) +#define HWIO_IPA_SCND_FRAG_VALUES_IPA_SCND_FRAG_FAIRNESS_CNT_BMSK 0xf000000 +#define HWIO_IPA_SCND_FRAG_VALUES_IPA_SCND_FRAG_FAIRNESS_CNT_SHFT 0x18 +#define HWIO_IPA_SCND_FRAG_VALUES_IPA_SCND_FRAG_RAM_LAST_ADDR_BMSK 0xffff +#define HWIO_IPA_SCND_FRAG_VALUES_IPA_SCND_FRAG_RAM_LAST_ADDR_SHFT 0x0 + +#define HWIO_IPA_AOS_CFG_ADDR (IPA_CFG_REG_BASE + 0x00000484) +#define HWIO_IPA_AOS_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000484) +#define HWIO_IPA_AOS_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000484) +#define HWIO_IPA_AOS_CFG_RMSK 0x1 +#define HWIO_IPA_AOS_CFG_ATTR 0x3 +#define HWIO_IPA_AOS_CFG_IN \ + in_dword_masked(HWIO_IPA_AOS_CFG_ADDR, HWIO_IPA_AOS_CFG_RMSK) +#define HWIO_IPA_AOS_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_AOS_CFG_ADDR, m) +#define HWIO_IPA_AOS_CFG_OUT(v) \ + out_dword(HWIO_IPA_AOS_CFG_ADDR,v) +#define HWIO_IPA_AOS_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_AOS_CFG_ADDR,m,v,HWIO_IPA_AOS_CFG_IN) +#define HWIO_IPA_AOS_CFG_IPA_AOS_TX_RX_PRIORITY_BMSK 0x1 +#define HWIO_IPA_AOS_CFG_IPA_AOS_TX_RX_PRIORITY_SHFT 0x0 + +#define HWIO_IPA_TX_CFG_ADDR (IPA_CFG_REG_BASE + 0x00000488) +#define HWIO_IPA_TX_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000488) +#define HWIO_IPA_TX_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000488) +#define HWIO_IPA_TX_CFG_RMSK 0x17fffc +#define HWIO_IPA_TX_CFG_ATTR 0x3 +#define HWIO_IPA_TX_CFG_IN \ + in_dword_masked(HWIO_IPA_TX_CFG_ADDR, HWIO_IPA_TX_CFG_RMSK) +#define HWIO_IPA_TX_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_TX_CFG_ADDR, m) +#define HWIO_IPA_TX_CFG_OUT(v) \ + out_dword(HWIO_IPA_TX_CFG_ADDR,v) +#define HWIO_IPA_TX_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_TX_CFG_ADDR,m,v,HWIO_IPA_TX_CFG_IN) +#define HWIO_IPA_TX_CFG_HOLB_STICKY_DROP_EN_BMSK 0x100000 +#define HWIO_IPA_TX_CFG_HOLB_STICKY_DROP_EN_SHFT 0x14 +#define HWIO_IPA_TX_CFG_SSPND_PA_NO_START_STATE_BMSK 0x40000 +#define HWIO_IPA_TX_CFG_SSPND_PA_NO_START_STATE_SHFT 0x12 +#define HWIO_IPA_TX_CFG_DUAL_TX_ENABLE_BMSK 0x20000 +#define HWIO_IPA_TX_CFG_DUAL_TX_ENABLE_SHFT 0x11 +#define HWIO_IPA_TX_CFG_PREFETCH_ALMOST_EMPTY_SIZE_TX1_BMSK 0x1e000 +#define HWIO_IPA_TX_CFG_PREFETCH_ALMOST_EMPTY_SIZE_TX1_SHFT 0xd +#define HWIO_IPA_TX_CFG_PA_MASK_EN_BMSK 0x1000 +#define HWIO_IPA_TX_CFG_PA_MASK_EN_SHFT 0xc +#define HWIO_IPA_TX_CFG_DMAW_MAX_BEATS_256_DIS_BMSK 0x800 +#define HWIO_IPA_TX_CFG_DMAW_MAX_BEATS_256_DIS_SHFT 0xb +#define HWIO_IPA_TX_CFG_DMAW_SCND_OUTSD_PRED_EN_BMSK 0x400 +#define HWIO_IPA_TX_CFG_DMAW_SCND_OUTSD_PRED_EN_SHFT 0xa +#define HWIO_IPA_TX_CFG_DMAW_SCND_OUTSD_PRED_THRESHOLD_BMSK 0x3c0 +#define HWIO_IPA_TX_CFG_DMAW_SCND_OUTSD_PRED_THRESHOLD_SHFT 0x6 +#define HWIO_IPA_TX_CFG_PREFETCH_ALMOST_EMPTY_SIZE_TX0_BMSK 0x3c +#define HWIO_IPA_TX_CFG_PREFETCH_ALMOST_EMPTY_SIZE_TX0_SHFT 0x2 + +#define HWIO_IPA_NAT_UC_EXTERNAL_CFG_ADDR (IPA_CFG_REG_BASE + 0x0000048c) +#define HWIO_IPA_NAT_UC_EXTERNAL_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000048c) +#define HWIO_IPA_NAT_UC_EXTERNAL_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000048c) +#define HWIO_IPA_NAT_UC_EXTERNAL_CFG_RMSK 0xffffffff +#define HWIO_IPA_NAT_UC_EXTERNAL_CFG_ATTR 0x3 +#define HWIO_IPA_NAT_UC_EXTERNAL_CFG_IN \ + in_dword_masked(HWIO_IPA_NAT_UC_EXTERNAL_CFG_ADDR, HWIO_IPA_NAT_UC_EXTERNAL_CFG_RMSK) +#define HWIO_IPA_NAT_UC_EXTERNAL_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_NAT_UC_EXTERNAL_CFG_ADDR, m) +#define HWIO_IPA_NAT_UC_EXTERNAL_CFG_OUT(v) \ + out_dword(HWIO_IPA_NAT_UC_EXTERNAL_CFG_ADDR,v) +#define HWIO_IPA_NAT_UC_EXTERNAL_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_NAT_UC_EXTERNAL_CFG_ADDR,m,v,HWIO_IPA_NAT_UC_EXTERNAL_CFG_IN) +#define HWIO_IPA_NAT_UC_EXTERNAL_CFG_IPA_NAT_UC_EXTERNAL_TABLE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_IPA_NAT_UC_EXTERNAL_CFG_IPA_NAT_UC_EXTERNAL_TABLE_ADDR_LSB_SHFT 0x0 + +#define HWIO_IPA_NAT_UC_LOCAL_CFG_ADDR (IPA_CFG_REG_BASE + 0x00000490) +#define HWIO_IPA_NAT_UC_LOCAL_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000490) +#define HWIO_IPA_NAT_UC_LOCAL_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000490) +#define HWIO_IPA_NAT_UC_LOCAL_CFG_RMSK 0xffffffff +#define HWIO_IPA_NAT_UC_LOCAL_CFG_ATTR 0x3 +#define HWIO_IPA_NAT_UC_LOCAL_CFG_IN \ + in_dword_masked(HWIO_IPA_NAT_UC_LOCAL_CFG_ADDR, HWIO_IPA_NAT_UC_LOCAL_CFG_RMSK) +#define HWIO_IPA_NAT_UC_LOCAL_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_NAT_UC_LOCAL_CFG_ADDR, m) +#define HWIO_IPA_NAT_UC_LOCAL_CFG_OUT(v) \ + out_dword(HWIO_IPA_NAT_UC_LOCAL_CFG_ADDR,v) +#define HWIO_IPA_NAT_UC_LOCAL_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_NAT_UC_LOCAL_CFG_ADDR,m,v,HWIO_IPA_NAT_UC_LOCAL_CFG_IN) +#define HWIO_IPA_NAT_UC_LOCAL_CFG_IPA_NAT_UC_LOCAL_TABLE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_IPA_NAT_UC_LOCAL_CFG_IPA_NAT_UC_LOCAL_TABLE_ADDR_LSB_SHFT 0x0 + +#define HWIO_IPA_NAT_UC_SHARED_CFG_ADDR (IPA_CFG_REG_BASE + 0x00000494) +#define HWIO_IPA_NAT_UC_SHARED_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000494) +#define HWIO_IPA_NAT_UC_SHARED_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000494) +#define HWIO_IPA_NAT_UC_SHARED_CFG_RMSK 0xffffffff +#define HWIO_IPA_NAT_UC_SHARED_CFG_ATTR 0x3 +#define HWIO_IPA_NAT_UC_SHARED_CFG_IN \ + in_dword_masked(HWIO_IPA_NAT_UC_SHARED_CFG_ADDR, HWIO_IPA_NAT_UC_SHARED_CFG_RMSK) +#define HWIO_IPA_NAT_UC_SHARED_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_NAT_UC_SHARED_CFG_ADDR, m) +#define HWIO_IPA_NAT_UC_SHARED_CFG_OUT(v) \ + out_dword(HWIO_IPA_NAT_UC_SHARED_CFG_ADDR,v) +#define HWIO_IPA_NAT_UC_SHARED_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_NAT_UC_SHARED_CFG_ADDR,m,v,HWIO_IPA_NAT_UC_SHARED_CFG_IN) +#define HWIO_IPA_NAT_UC_SHARED_CFG_IPA_NAT_UC_LOCAL_TABLE_ADDR_MSB_BMSK 0xffff0000 +#define HWIO_IPA_NAT_UC_SHARED_CFG_IPA_NAT_UC_LOCAL_TABLE_ADDR_MSB_SHFT 0x10 +#define HWIO_IPA_NAT_UC_SHARED_CFG_IPA_NAT_UC_EXTERNAL_TABLE_ADDR_MSB_BMSK 0xffff +#define HWIO_IPA_NAT_UC_SHARED_CFG_IPA_NAT_UC_EXTERNAL_TABLE_ADDR_MSB_SHFT 0x0 + +#define HWIO_IPA_RAM_INTLV_CFG_ADDR (IPA_CFG_REG_BASE + 0x00000498) +#define HWIO_IPA_RAM_INTLV_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000498) +#define HWIO_IPA_RAM_INTLV_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000498) +#define HWIO_IPA_RAM_INTLV_CFG_RMSK 0xffff +#define HWIO_IPA_RAM_INTLV_CFG_ATTR 0x3 +#define HWIO_IPA_RAM_INTLV_CFG_IN \ + in_dword_masked(HWIO_IPA_RAM_INTLV_CFG_ADDR, HWIO_IPA_RAM_INTLV_CFG_RMSK) +#define HWIO_IPA_RAM_INTLV_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_RAM_INTLV_CFG_ADDR, m) +#define HWIO_IPA_RAM_INTLV_CFG_OUT(v) \ + out_dword(HWIO_IPA_RAM_INTLV_CFG_ADDR,v) +#define HWIO_IPA_RAM_INTLV_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_RAM_INTLV_CFG_ADDR,m,v,HWIO_IPA_RAM_INTLV_CFG_IN) +#define HWIO_IPA_RAM_INTLV_CFG_IPA_RAM_INTLV_CFG_BMSK 0xffff +#define HWIO_IPA_RAM_INTLV_CFG_IPA_RAM_INTLV_CFG_SHFT 0x0 + +#define HWIO_IPA_CONN_TRACK_UC_EXTERNAL_CFG_ADDR (IPA_CFG_REG_BASE + 0x0000049c) +#define HWIO_IPA_CONN_TRACK_UC_EXTERNAL_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000049c) +#define HWIO_IPA_CONN_TRACK_UC_EXTERNAL_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000049c) +#define HWIO_IPA_CONN_TRACK_UC_EXTERNAL_CFG_RMSK 0xffffffff +#define HWIO_IPA_CONN_TRACK_UC_EXTERNAL_CFG_ATTR 0x3 +#define HWIO_IPA_CONN_TRACK_UC_EXTERNAL_CFG_IN \ + in_dword_masked(HWIO_IPA_CONN_TRACK_UC_EXTERNAL_CFG_ADDR, HWIO_IPA_CONN_TRACK_UC_EXTERNAL_CFG_RMSK) +#define HWIO_IPA_CONN_TRACK_UC_EXTERNAL_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_CONN_TRACK_UC_EXTERNAL_CFG_ADDR, m) +#define HWIO_IPA_CONN_TRACK_UC_EXTERNAL_CFG_OUT(v) \ + out_dword(HWIO_IPA_CONN_TRACK_UC_EXTERNAL_CFG_ADDR,v) +#define HWIO_IPA_CONN_TRACK_UC_EXTERNAL_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_CONN_TRACK_UC_EXTERNAL_CFG_ADDR,m,v,HWIO_IPA_CONN_TRACK_UC_EXTERNAL_CFG_IN) +#define HWIO_IPA_CONN_TRACK_UC_EXTERNAL_CFG_IPA_CONN_TRACK_UC_EXTERNAL_TABLE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_IPA_CONN_TRACK_UC_EXTERNAL_CFG_IPA_CONN_TRACK_UC_EXTERNAL_TABLE_ADDR_LSB_SHFT 0x0 + +#define HWIO_IPA_CONN_TRACK_UC_LOCAL_CFG_ADDR (IPA_CFG_REG_BASE + 0x000004a0) +#define HWIO_IPA_CONN_TRACK_UC_LOCAL_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000004a0) +#define HWIO_IPA_CONN_TRACK_UC_LOCAL_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000004a0) +#define HWIO_IPA_CONN_TRACK_UC_LOCAL_CFG_RMSK 0xffffffff +#define HWIO_IPA_CONN_TRACK_UC_LOCAL_CFG_ATTR 0x3 +#define HWIO_IPA_CONN_TRACK_UC_LOCAL_CFG_IN \ + in_dword_masked(HWIO_IPA_CONN_TRACK_UC_LOCAL_CFG_ADDR, HWIO_IPA_CONN_TRACK_UC_LOCAL_CFG_RMSK) +#define HWIO_IPA_CONN_TRACK_UC_LOCAL_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_CONN_TRACK_UC_LOCAL_CFG_ADDR, m) +#define HWIO_IPA_CONN_TRACK_UC_LOCAL_CFG_OUT(v) \ + out_dword(HWIO_IPA_CONN_TRACK_UC_LOCAL_CFG_ADDR,v) +#define HWIO_IPA_CONN_TRACK_UC_LOCAL_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_CONN_TRACK_UC_LOCAL_CFG_ADDR,m,v,HWIO_IPA_CONN_TRACK_UC_LOCAL_CFG_IN) +#define HWIO_IPA_CONN_TRACK_UC_LOCAL_CFG_IPA_CONN_TRACK_UC_LOCAL_TABLE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_IPA_CONN_TRACK_UC_LOCAL_CFG_IPA_CONN_TRACK_UC_LOCAL_TABLE_ADDR_LSB_SHFT 0x0 + +#define HWIO_IPA_CONN_TRACK_UC_SHARED_CFG_ADDR (IPA_CFG_REG_BASE + 0x000004a4) +#define HWIO_IPA_CONN_TRACK_UC_SHARED_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000004a4) +#define HWIO_IPA_CONN_TRACK_UC_SHARED_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000004a4) +#define HWIO_IPA_CONN_TRACK_UC_SHARED_CFG_RMSK 0xffffffff +#define HWIO_IPA_CONN_TRACK_UC_SHARED_CFG_ATTR 0x3 +#define HWIO_IPA_CONN_TRACK_UC_SHARED_CFG_IN \ + in_dword_masked(HWIO_IPA_CONN_TRACK_UC_SHARED_CFG_ADDR, HWIO_IPA_CONN_TRACK_UC_SHARED_CFG_RMSK) +#define HWIO_IPA_CONN_TRACK_UC_SHARED_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_CONN_TRACK_UC_SHARED_CFG_ADDR, m) +#define HWIO_IPA_CONN_TRACK_UC_SHARED_CFG_OUT(v) \ + out_dword(HWIO_IPA_CONN_TRACK_UC_SHARED_CFG_ADDR,v) +#define HWIO_IPA_CONN_TRACK_UC_SHARED_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_CONN_TRACK_UC_SHARED_CFG_ADDR,m,v,HWIO_IPA_CONN_TRACK_UC_SHARED_CFG_IN) +#define HWIO_IPA_CONN_TRACK_UC_SHARED_CFG_IPA_CONN_TRACK_UC_LOCAL_TABLE_ADDR_MSB_BMSK 0xffff0000 +#define HWIO_IPA_CONN_TRACK_UC_SHARED_CFG_IPA_CONN_TRACK_UC_LOCAL_TABLE_ADDR_MSB_SHFT 0x10 +#define HWIO_IPA_CONN_TRACK_UC_SHARED_CFG_IPA_CONN_TRACK_UC_EXTERNAL_TABLE_ADDR_MSB_BMSK 0xffff +#define HWIO_IPA_CONN_TRACK_UC_SHARED_CFG_IPA_CONN_TRACK_UC_EXTERNAL_TABLE_ADDR_MSB_SHFT 0x0 + +#define HWIO_IPA_IDLE_INDICATION_CFG_ADDR (IPA_CFG_REG_BASE + 0x000004a8) +#define HWIO_IPA_IDLE_INDICATION_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000004a8) +#define HWIO_IPA_IDLE_INDICATION_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000004a8) +#define HWIO_IPA_IDLE_INDICATION_CFG_RMSK 0x1ffff +#define HWIO_IPA_IDLE_INDICATION_CFG_ATTR 0x3 +#define HWIO_IPA_IDLE_INDICATION_CFG_IN \ + in_dword_masked(HWIO_IPA_IDLE_INDICATION_CFG_ADDR, HWIO_IPA_IDLE_INDICATION_CFG_RMSK) +#define HWIO_IPA_IDLE_INDICATION_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_IDLE_INDICATION_CFG_ADDR, m) +#define HWIO_IPA_IDLE_INDICATION_CFG_OUT(v) \ + out_dword(HWIO_IPA_IDLE_INDICATION_CFG_ADDR,v) +#define HWIO_IPA_IDLE_INDICATION_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_IDLE_INDICATION_CFG_ADDR,m,v,HWIO_IPA_IDLE_INDICATION_CFG_IN) +#define HWIO_IPA_IDLE_INDICATION_CFG_IDLE_INDICATION_ENABLE_BMSK 0x10000 +#define HWIO_IPA_IDLE_INDICATION_CFG_IDLE_INDICATION_ENABLE_SHFT 0x10 +#define HWIO_IPA_IDLE_INDICATION_CFG_ENTER_IDLE_DEBOUNCE_THRESH_BMSK 0xffff +#define HWIO_IPA_IDLE_INDICATION_CFG_ENTER_IDLE_DEBOUNCE_THRESH_SHFT 0x0 + +#define HWIO_IPA_QTIME_TIMESTAMP_CFG_ADDR (IPA_CFG_REG_BASE + 0x000004ac) +#define HWIO_IPA_QTIME_TIMESTAMP_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000004ac) +#define HWIO_IPA_QTIME_TIMESTAMP_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000004ac) +#define HWIO_IPA_QTIME_TIMESTAMP_CFG_RMSK 0x1f1f9f +#define HWIO_IPA_QTIME_TIMESTAMP_CFG_ATTR 0x3 +#define HWIO_IPA_QTIME_TIMESTAMP_CFG_IN \ + in_dword_masked(HWIO_IPA_QTIME_TIMESTAMP_CFG_ADDR, HWIO_IPA_QTIME_TIMESTAMP_CFG_RMSK) +#define HWIO_IPA_QTIME_TIMESTAMP_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_QTIME_TIMESTAMP_CFG_ADDR, m) +#define HWIO_IPA_QTIME_TIMESTAMP_CFG_OUT(v) \ + out_dword(HWIO_IPA_QTIME_TIMESTAMP_CFG_ADDR,v) +#define HWIO_IPA_QTIME_TIMESTAMP_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_QTIME_TIMESTAMP_CFG_ADDR,m,v,HWIO_IPA_QTIME_TIMESTAMP_CFG_IN) +#define HWIO_IPA_QTIME_TIMESTAMP_CFG_NAT_TIMESTAMP_LSB_BMSK 0x1f0000 +#define HWIO_IPA_QTIME_TIMESTAMP_CFG_NAT_TIMESTAMP_LSB_SHFT 0x10 +#define HWIO_IPA_QTIME_TIMESTAMP_CFG_TAG_TIMESTAMP_LSB_BMSK 0x1f00 +#define HWIO_IPA_QTIME_TIMESTAMP_CFG_TAG_TIMESTAMP_LSB_SHFT 0x8 +#define HWIO_IPA_QTIME_TIMESTAMP_CFG_DPL_TIMESTAMP_SEL_BMSK 0x80 +#define HWIO_IPA_QTIME_TIMESTAMP_CFG_DPL_TIMESTAMP_SEL_SHFT 0x7 +#define HWIO_IPA_QTIME_TIMESTAMP_CFG_DPL_TIMESTAMP_LSB_BMSK 0x1f +#define HWIO_IPA_QTIME_TIMESTAMP_CFG_DPL_TIMESTAMP_LSB_SHFT 0x0 + +#define HWIO_IPA_TIMERS_XO_CLK_DIV_CFG_ADDR (IPA_CFG_REG_BASE + 0x000004b0) +#define HWIO_IPA_TIMERS_XO_CLK_DIV_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000004b0) +#define HWIO_IPA_TIMERS_XO_CLK_DIV_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000004b0) +#define HWIO_IPA_TIMERS_XO_CLK_DIV_CFG_RMSK 0x800001ff +#define HWIO_IPA_TIMERS_XO_CLK_DIV_CFG_ATTR 0x3 +#define HWIO_IPA_TIMERS_XO_CLK_DIV_CFG_IN \ + in_dword_masked(HWIO_IPA_TIMERS_XO_CLK_DIV_CFG_ADDR, HWIO_IPA_TIMERS_XO_CLK_DIV_CFG_RMSK) +#define HWIO_IPA_TIMERS_XO_CLK_DIV_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_TIMERS_XO_CLK_DIV_CFG_ADDR, m) +#define HWIO_IPA_TIMERS_XO_CLK_DIV_CFG_OUT(v) \ + out_dword(HWIO_IPA_TIMERS_XO_CLK_DIV_CFG_ADDR,v) +#define HWIO_IPA_TIMERS_XO_CLK_DIV_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_TIMERS_XO_CLK_DIV_CFG_ADDR,m,v,HWIO_IPA_TIMERS_XO_CLK_DIV_CFG_IN) +#define HWIO_IPA_TIMERS_XO_CLK_DIV_CFG_ENABLE_BMSK 0x80000000 +#define HWIO_IPA_TIMERS_XO_CLK_DIV_CFG_ENABLE_SHFT 0x1f +#define HWIO_IPA_TIMERS_XO_CLK_DIV_CFG_VALUE_BMSK 0x1ff +#define HWIO_IPA_TIMERS_XO_CLK_DIV_CFG_VALUE_SHFT 0x0 + +#define HWIO_IPA_TIMERS_PULSE_GRAN_CFG_ADDR (IPA_CFG_REG_BASE + 0x000004b4) +#define HWIO_IPA_TIMERS_PULSE_GRAN_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000004b4) +#define HWIO_IPA_TIMERS_PULSE_GRAN_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000004b4) +#define HWIO_IPA_TIMERS_PULSE_GRAN_CFG_RMSK 0xfff +#define HWIO_IPA_TIMERS_PULSE_GRAN_CFG_ATTR 0x3 +#define HWIO_IPA_TIMERS_PULSE_GRAN_CFG_IN \ + in_dword_masked(HWIO_IPA_TIMERS_PULSE_GRAN_CFG_ADDR, HWIO_IPA_TIMERS_PULSE_GRAN_CFG_RMSK) +#define HWIO_IPA_TIMERS_PULSE_GRAN_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_TIMERS_PULSE_GRAN_CFG_ADDR, m) +#define HWIO_IPA_TIMERS_PULSE_GRAN_CFG_OUT(v) \ + out_dword(HWIO_IPA_TIMERS_PULSE_GRAN_CFG_ADDR,v) +#define HWIO_IPA_TIMERS_PULSE_GRAN_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_TIMERS_PULSE_GRAN_CFG_ADDR,m,v,HWIO_IPA_TIMERS_PULSE_GRAN_CFG_IN) +#define HWIO_IPA_TIMERS_PULSE_GRAN_CFG_GRAN_3_BMSK 0xe00 +#define HWIO_IPA_TIMERS_PULSE_GRAN_CFG_GRAN_3_SHFT 0x9 +#define HWIO_IPA_TIMERS_PULSE_GRAN_CFG_GRAN_2_BMSK 0x1c0 +#define HWIO_IPA_TIMERS_PULSE_GRAN_CFG_GRAN_2_SHFT 0x6 +#define HWIO_IPA_TIMERS_PULSE_GRAN_CFG_GRAN_1_BMSK 0x38 +#define HWIO_IPA_TIMERS_PULSE_GRAN_CFG_GRAN_1_SHFT 0x3 +#define HWIO_IPA_TIMERS_PULSE_GRAN_CFG_GRAN_0_BMSK 0x7 +#define HWIO_IPA_TIMERS_PULSE_GRAN_CFG_GRAN_0_SHFT 0x0 + +#define HWIO_IPA_QTIME_SMP_ADDR (IPA_CFG_REG_BASE + 0x000004b8) +#define HWIO_IPA_QTIME_SMP_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000004b8) +#define HWIO_IPA_QTIME_SMP_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000004b8) +#define HWIO_IPA_QTIME_SMP_RMSK 0x1 +#define HWIO_IPA_QTIME_SMP_ATTR 0x2 +#define HWIO_IPA_QTIME_SMP_OUT(v) \ + out_dword(HWIO_IPA_QTIME_SMP_ADDR,v) +#define HWIO_IPA_QTIME_SMP_PULSE_BMSK 0x1 +#define HWIO_IPA_QTIME_SMP_PULSE_SHFT 0x0 + +#define HWIO_IPA_QTIME_LSB_ADDR (IPA_CFG_REG_BASE + 0x000004bc) +#define HWIO_IPA_QTIME_LSB_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000004bc) +#define HWIO_IPA_QTIME_LSB_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000004bc) +#define HWIO_IPA_QTIME_LSB_RMSK 0xffffffff +#define HWIO_IPA_QTIME_LSB_ATTR 0x1 +#define HWIO_IPA_QTIME_LSB_IN \ + in_dword_masked(HWIO_IPA_QTIME_LSB_ADDR, HWIO_IPA_QTIME_LSB_RMSK) +#define HWIO_IPA_QTIME_LSB_INM(m) \ + in_dword_masked(HWIO_IPA_QTIME_LSB_ADDR, m) +#define HWIO_IPA_QTIME_LSB_VALUE_BMSK 0xffffffff +#define HWIO_IPA_QTIME_LSB_VALUE_SHFT 0x0 + +#define HWIO_IPA_QTIME_MSB_ADDR (IPA_CFG_REG_BASE + 0x000004c0) +#define HWIO_IPA_QTIME_MSB_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000004c0) +#define HWIO_IPA_QTIME_MSB_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000004c0) +#define HWIO_IPA_QTIME_MSB_RMSK 0xffffffff +#define HWIO_IPA_QTIME_MSB_ATTR 0x1 +#define HWIO_IPA_QTIME_MSB_IN \ + in_dword_masked(HWIO_IPA_QTIME_MSB_ADDR, HWIO_IPA_QTIME_MSB_RMSK) +#define HWIO_IPA_QTIME_MSB_INM(m) \ + in_dword_masked(HWIO_IPA_QTIME_MSB_ADDR, m) +#define HWIO_IPA_QTIME_MSB_VALUE_BMSK 0xffffffff +#define HWIO_IPA_QTIME_MSB_VALUE_SHFT 0x0 + +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_EN_ADDR (IPA_CFG_REG_BASE + 0x000004c4) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_EN_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000004c4) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_EN_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000004c4) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_EN_RMSK 0xff +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_EN_ATTR 0x3 +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_EN_IN \ + in_dword_masked(HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_EN_ADDR, HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_EN_RMSK) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_EN_INM(m) \ + in_dword_masked(HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_EN_ADDR, m) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_EN_OUT(v) \ + out_dword(HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_EN_ADDR,v) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_EN_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_EN_ADDR,m,v,HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_EN_IN) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_EN_IPA_SRC_RSRC_AMOUNT_REDUCE_EN_BMSK 0xff +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_EN_IPA_SRC_RSRC_AMOUNT_REDUCE_EN_SHFT 0x0 + +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_0_ADDR (IPA_CFG_REG_BASE + 0x000004c8) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_0_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000004c8) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_0_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000004c8) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_0_RMSK 0x3f3f3f3f +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_0_ATTR 0x3 +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_0_IN \ + in_dword_masked(HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_0_ADDR, HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_0_RMSK) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_0_INM(m) \ + in_dword_masked(HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_0_ADDR, m) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_0_OUT(v) \ + out_dword(HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_0_ADDR,v) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_0_ADDR,m,v,HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_0_IN) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_0_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUE_RSRC_TYPE_3_BMSK 0x3f000000 +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_0_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUE_RSRC_TYPE_3_SHFT 0x18 +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_0_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUE_RSRC_TYPE_2_BMSK 0x3f0000 +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_0_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUE_RSRC_TYPE_2_SHFT 0x10 +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_0_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUE_RSRC_TYPE_1_BMSK 0x3f00 +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_0_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUE_RSRC_TYPE_1_SHFT 0x8 +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_0_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUE_RSRC_TYPE_0_BMSK 0x3f +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_0_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUE_RSRC_TYPE_0_SHFT 0x0 + +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_1_ADDR (IPA_CFG_REG_BASE + 0x000004cc) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_1_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000004cc) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_1_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000004cc) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_1_RMSK 0x3f +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_1_ATTR 0x3 +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_1_IN \ + in_dword_masked(HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_1_ADDR, HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_1_RMSK) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_1_INM(m) \ + in_dword_masked(HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_1_ADDR, m) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_1_OUT(v) \ + out_dword(HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_1_ADDR,v) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_1_ADDR,m,v,HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_1_IN) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_1_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUE_RSRC_TYPE_4_BMSK 0x3f +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_1_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUE_RSRC_TYPE_4_SHFT 0x0 + +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_EN_ADDR (IPA_CFG_REG_BASE + 0x000004d0) +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_EN_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000004d0) +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_EN_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000004d0) +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_EN_RMSK 0xf +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_EN_ATTR 0x3 +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_EN_IN \ + in_dword_masked(HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_EN_ADDR, HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_EN_RMSK) +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_EN_INM(m) \ + in_dword_masked(HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_EN_ADDR, m) +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_EN_OUT(v) \ + out_dword(HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_EN_ADDR,v) +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_EN_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_EN_ADDR,m,v,HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_EN_IN) +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_EN_IPA_DST_RSRC_AMOUNT_REDUCE_EN_BMSK 0xf +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_EN_IPA_DST_RSRC_AMOUNT_REDUCE_EN_SHFT 0x0 + +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_VALUES_0_ADDR (IPA_CFG_REG_BASE + 0x000004d4) +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_VALUES_0_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000004d4) +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_VALUES_0_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000004d4) +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_VALUES_0_RMSK 0x3f3f +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_VALUES_0_ATTR 0x3 +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_VALUES_0_IN \ + in_dword_masked(HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_VALUES_0_ADDR, HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_VALUES_0_RMSK) +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_VALUES_0_INM(m) \ + in_dword_masked(HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_VALUES_0_ADDR, m) +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_VALUES_0_OUT(v) \ + out_dword(HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_VALUES_0_ADDR,v) +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_VALUES_0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_VALUES_0_ADDR,m,v,HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_VALUES_0_IN) +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_VALUES_0_IPA_DST_RSRC_AMOUNT_REDUCE_VALUE_RSRC_TYPE_1_BMSK 0x3f00 +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_VALUES_0_IPA_DST_RSRC_AMOUNT_REDUCE_VALUE_RSRC_TYPE_1_SHFT 0x8 +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_VALUES_0_IPA_DST_RSRC_AMOUNT_REDUCE_VALUE_RSRC_TYPE_0_BMSK 0x3f +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_VALUES_0_IPA_DST_RSRC_AMOUNT_REDUCE_VALUE_RSRC_TYPE_0_SHFT 0x0 + +#define HWIO_IPA_ATOMIC_LOCK_CFG_ADDR (IPA_CFG_REG_BASE + 0x000004d8) +#define HWIO_IPA_ATOMIC_LOCK_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000004d8) +#define HWIO_IPA_ATOMIC_LOCK_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000004d8) +#define HWIO_IPA_ATOMIC_LOCK_CFG_RMSK 0x3f +#define HWIO_IPA_ATOMIC_LOCK_CFG_ATTR 0x3 +#define HWIO_IPA_ATOMIC_LOCK_CFG_IN \ + in_dword_masked(HWIO_IPA_ATOMIC_LOCK_CFG_ADDR, HWIO_IPA_ATOMIC_LOCK_CFG_RMSK) +#define HWIO_IPA_ATOMIC_LOCK_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_ATOMIC_LOCK_CFG_ADDR, m) +#define HWIO_IPA_ATOMIC_LOCK_CFG_OUT(v) \ + out_dword(HWIO_IPA_ATOMIC_LOCK_CFG_ADDR,v) +#define HWIO_IPA_ATOMIC_LOCK_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_ATOMIC_LOCK_CFG_ADDR,m,v,HWIO_IPA_ATOMIC_LOCK_CFG_IN) +#define HWIO_IPA_ATOMIC_LOCK_CFG_GROUPS_TO_MASK_BMSK 0x3f +#define HWIO_IPA_ATOMIC_LOCK_CFG_GROUPS_TO_MASK_SHFT 0x0 + +#define HWIO_IPA_GENERIC_RAM_ARBITER_PRIORITY_ADDR (IPA_CFG_REG_BASE + 0x000004dc) +#define HWIO_IPA_GENERIC_RAM_ARBITER_PRIORITY_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000004dc) +#define HWIO_IPA_GENERIC_RAM_ARBITER_PRIORITY_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000004dc) +#define HWIO_IPA_GENERIC_RAM_ARBITER_PRIORITY_RMSK 0xffff3 +#define HWIO_IPA_GENERIC_RAM_ARBITER_PRIORITY_ATTR 0x3 +#define HWIO_IPA_GENERIC_RAM_ARBITER_PRIORITY_IN \ + in_dword_masked(HWIO_IPA_GENERIC_RAM_ARBITER_PRIORITY_ADDR, HWIO_IPA_GENERIC_RAM_ARBITER_PRIORITY_RMSK) +#define HWIO_IPA_GENERIC_RAM_ARBITER_PRIORITY_INM(m) \ + in_dword_masked(HWIO_IPA_GENERIC_RAM_ARBITER_PRIORITY_ADDR, m) +#define HWIO_IPA_GENERIC_RAM_ARBITER_PRIORITY_OUT(v) \ + out_dword(HWIO_IPA_GENERIC_RAM_ARBITER_PRIORITY_ADDR,v) +#define HWIO_IPA_GENERIC_RAM_ARBITER_PRIORITY_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GENERIC_RAM_ARBITER_PRIORITY_ADDR,m,v,HWIO_IPA_GENERIC_RAM_ARBITER_PRIORITY_IN) +#define HWIO_IPA_GENERIC_RAM_ARBITER_PRIORITY_WR_PRIORITY_INDEX_BMSK 0xff000 +#define HWIO_IPA_GENERIC_RAM_ARBITER_PRIORITY_WR_PRIORITY_INDEX_SHFT 0xc +#define HWIO_IPA_GENERIC_RAM_ARBITER_PRIORITY_RD_PRIORITY_INDEX_BMSK 0xff0 +#define HWIO_IPA_GENERIC_RAM_ARBITER_PRIORITY_RD_PRIORITY_INDEX_SHFT 0x4 +#define HWIO_IPA_GENERIC_RAM_ARBITER_PRIORITY_WR_PRIORITY_VALID_BMSK 0x2 +#define HWIO_IPA_GENERIC_RAM_ARBITER_PRIORITY_WR_PRIORITY_VALID_SHFT 0x1 +#define HWIO_IPA_GENERIC_RAM_ARBITER_PRIORITY_RD_PRIORITY_VALID_BMSK 0x1 +#define HWIO_IPA_GENERIC_RAM_ARBITER_PRIORITY_RD_PRIORITY_VALID_SHFT 0x0 + +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000500 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000500 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000500 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_RMSK 0x3f3f3f3f +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_MAXn 4 +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_ATTR 0x3 +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_INI(n) \ + in_dword_masked(HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_ADDR(n), HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_RMSK) +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_ADDR(n), mask) +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_OUTI(n,val) \ + out_dword(HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_ADDR(n),val) +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_ADDR(n),mask,val,HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_INI(n)) +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_SRC_RSRC_GRP_1_MAX_LIMIT_BMSK 0x3f000000 +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_SRC_RSRC_GRP_1_MAX_LIMIT_SHFT 0x18 +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_SRC_RSRC_GRP_1_MIN_LIMIT_BMSK 0x3f0000 +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_SRC_RSRC_GRP_1_MIN_LIMIT_SHFT 0x10 +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_SRC_RSRC_GRP_0_MAX_LIMIT_BMSK 0x3f00 +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_SRC_RSRC_GRP_0_MAX_LIMIT_SHFT 0x8 +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_SRC_RSRC_GRP_0_MIN_LIMIT_BMSK 0x3f +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_SRC_RSRC_GRP_0_MIN_LIMIT_SHFT 0x0 + +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000504 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000504 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000504 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_RMSK 0x3f3f3f3f +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_MAXn 4 +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_ATTR 0x3 +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_INI(n) \ + in_dword_masked(HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_ADDR(n), HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_RMSK) +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_ADDR(n), mask) +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_OUTI(n,val) \ + out_dword(HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_ADDR(n),val) +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_ADDR(n),mask,val,HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_INI(n)) +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_SRC_RSRC_GRP_3_MAX_LIMIT_BMSK 0x3f000000 +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_SRC_RSRC_GRP_3_MAX_LIMIT_SHFT 0x18 +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_SRC_RSRC_GRP_3_MIN_LIMIT_BMSK 0x3f0000 +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_SRC_RSRC_GRP_3_MIN_LIMIT_SHFT 0x10 +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_SRC_RSRC_GRP_2_MAX_LIMIT_BMSK 0x3f00 +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_SRC_RSRC_GRP_2_MAX_LIMIT_SHFT 0x8 +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_SRC_RSRC_GRP_2_MIN_LIMIT_BMSK 0x3f +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_SRC_RSRC_GRP_2_MIN_LIMIT_SHFT 0x0 + +#define HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000508 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000508 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000508 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_RMSK 0x3f3f3f3f +#define HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_MAXn 4 +#define HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_ATTR 0x3 +#define HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_INI(n) \ + in_dword_masked(HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_ADDR(n), HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_RMSK) +#define HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_ADDR(n), mask) +#define HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_OUTI(n,val) \ + out_dword(HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_ADDR(n),val) +#define HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_ADDR(n),mask,val,HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_INI(n)) +#define HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_SRC_RSRC_GRP_5_MAX_LIMIT_BMSK 0x3f000000 +#define HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_SRC_RSRC_GRP_5_MAX_LIMIT_SHFT 0x18 +#define HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_SRC_RSRC_GRP_5_MIN_LIMIT_BMSK 0x3f0000 +#define HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_SRC_RSRC_GRP_5_MIN_LIMIT_SHFT 0x10 +#define HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_SRC_RSRC_GRP_4_MAX_LIMIT_BMSK 0x3f00 +#define HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_SRC_RSRC_GRP_4_MAX_LIMIT_SHFT 0x8 +#define HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_SRC_RSRC_GRP_4_MIN_LIMIT_BMSK 0x3f +#define HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_SRC_RSRC_GRP_4_MIN_LIMIT_SHFT 0x0 + +#define HWIO_IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n_ADDR(n) (IPA_CFG_REG_BASE + 0x0000050c + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x0000050c + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x0000050c + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n_RMSK 0x3f3f3f3f +#define HWIO_IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n_MAXn 4 +#define HWIO_IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n_ATTR 0x3 +#define HWIO_IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n_INI(n) \ + in_dword_masked(HWIO_IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n_ADDR(n), HWIO_IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n_RMSK) +#define HWIO_IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n_ADDR(n), mask) +#define HWIO_IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n_OUTI(n,val) \ + out_dword(HWIO_IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n_ADDR(n),val) +#define HWIO_IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n_ADDR(n),mask,val,HWIO_IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n_INI(n)) +#define HWIO_IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n_SRC_RSRC_GRP_7_MAX_LIMIT_BMSK 0x3f000000 +#define HWIO_IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n_SRC_RSRC_GRP_7_MAX_LIMIT_SHFT 0x18 +#define HWIO_IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n_SRC_RSRC_GRP_7_MIN_LIMIT_BMSK 0x3f0000 +#define HWIO_IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n_SRC_RSRC_GRP_7_MIN_LIMIT_SHFT 0x10 +#define HWIO_IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n_SRC_RSRC_GRP_6_MAX_LIMIT_BMSK 0x3f00 +#define HWIO_IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n_SRC_RSRC_GRP_6_MAX_LIMIT_SHFT 0x8 +#define HWIO_IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n_SRC_RSRC_GRP_6_MIN_LIMIT_BMSK 0x3f +#define HWIO_IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n_SRC_RSRC_GRP_6_MIN_LIMIT_SHFT 0x0 + +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000510 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000510 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000510 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_RMSK 0x3f3f3f3f +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_MAXn 4 +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_ATTR 0x1 +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_INI(n) \ + in_dword_masked(HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_ADDR(n), HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_RMSK, HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_ATTR) +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_ADDR(n), mask, HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_ATTR) +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_SRC_RSRC_GRP_3_CNT_BMSK 0x3f000000 +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_SRC_RSRC_GRP_3_CNT_SHFT 0x18 +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_SRC_RSRC_GRP_2_CNT_BMSK 0x3f0000 +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_SRC_RSRC_GRP_2_CNT_SHFT 0x10 +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_SRC_RSRC_GRP_1_CNT_BMSK 0x3f00 +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_SRC_RSRC_GRP_1_CNT_SHFT 0x8 +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_SRC_RSRC_GRP_0_CNT_BMSK 0x3f +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_SRC_RSRC_GRP_0_CNT_SHFT 0x0 + +#define HWIO_IPA_SRC_RSRC_GRP_4567_RSRC_TYPE_CNT_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000514 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_GRP_4567_RSRC_TYPE_CNT_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000514 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_GRP_4567_RSRC_TYPE_CNT_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000514 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_GRP_4567_RSRC_TYPE_CNT_n_RMSK 0x3f3f +#define HWIO_IPA_SRC_RSRC_GRP_4567_RSRC_TYPE_CNT_n_MAXn 4 +#define HWIO_IPA_SRC_RSRC_GRP_4567_RSRC_TYPE_CNT_n_ATTR 0x1 +#define HWIO_IPA_SRC_RSRC_GRP_4567_RSRC_TYPE_CNT_n_INI(n) \ + in_dword_masked(HWIO_IPA_SRC_RSRC_GRP_4567_RSRC_TYPE_CNT_n_ADDR(n), HWIO_IPA_SRC_RSRC_GRP_4567_RSRC_TYPE_CNT_n_RMSK) +#define HWIO_IPA_SRC_RSRC_GRP_4567_RSRC_TYPE_CNT_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_SRC_RSRC_GRP_4567_RSRC_TYPE_CNT_n_ADDR(n), mask) +#define HWIO_IPA_SRC_RSRC_GRP_4567_RSRC_TYPE_CNT_n_SRC_RSRC_GRP_5_CNT_BMSK 0x3f00 +#define HWIO_IPA_SRC_RSRC_GRP_4567_RSRC_TYPE_CNT_n_SRC_RSRC_GRP_5_CNT_SHFT 0x8 +#define HWIO_IPA_SRC_RSRC_GRP_4567_RSRC_TYPE_CNT_n_SRC_RSRC_GRP_4_CNT_BMSK 0x3f +#define HWIO_IPA_SRC_RSRC_GRP_4567_RSRC_TYPE_CNT_n_SRC_RSRC_GRP_4_CNT_SHFT 0x0 + +#define HWIO_IPA_SRC_RSRC_TYPE_AMOUNT_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000518 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_TYPE_AMOUNT_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000518 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_TYPE_AMOUNT_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000518 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_TYPE_AMOUNT_n_RMSK 0x3f +#define HWIO_IPA_SRC_RSRC_TYPE_AMOUNT_n_MAXn 4 +#define HWIO_IPA_SRC_RSRC_TYPE_AMOUNT_n_ATTR 0x1 +#define HWIO_IPA_SRC_RSRC_TYPE_AMOUNT_n_INI(n) \ + in_dword_masked(HWIO_IPA_SRC_RSRC_TYPE_AMOUNT_n_ADDR(n), HWIO_IPA_SRC_RSRC_TYPE_AMOUNT_n_RMSK) +#define HWIO_IPA_SRC_RSRC_TYPE_AMOUNT_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_SRC_RSRC_TYPE_AMOUNT_n_ADDR(n), mask) +#define HWIO_IPA_SRC_RSRC_TYPE_AMOUNT_n_SRC_RSRC_TYPE_AMOUNT_BMSK 0x3f +#define HWIO_IPA_SRC_RSRC_TYPE_AMOUNT_n_SRC_RSRC_TYPE_AMOUNT_SHFT 0x0 + +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000600 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000600 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000600 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_RMSK 0x3f3f3f3f +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_MAXn 2 +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_ATTR 0x3 +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_INI(n) \ + in_dword_masked(HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_ADDR(n), HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_RMSK) +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_ADDR(n), mask) +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_OUTI(n,val) \ + out_dword(HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_ADDR(n),val) +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_ADDR(n),mask,val,HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_INI(n)) +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_DST_RSRC_GRP_1_MAX_LIMIT_BMSK 0x3f000000 +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_DST_RSRC_GRP_1_MAX_LIMIT_SHFT 0x18 +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_DST_RSRC_GRP_1_MIN_LIMIT_BMSK 0x3f0000 +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_DST_RSRC_GRP_1_MIN_LIMIT_SHFT 0x10 +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_DST_RSRC_GRP_0_MAX_LIMIT_BMSK 0x3f00 +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_DST_RSRC_GRP_0_MAX_LIMIT_SHFT 0x8 +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_DST_RSRC_GRP_0_MIN_LIMIT_BMSK 0x3f +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_DST_RSRC_GRP_0_MIN_LIMIT_SHFT 0x0 + +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000604 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000604 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000604 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_RMSK 0x3f3f3f3f +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_MAXn 2 +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_ATTR 0x3 +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_INI(n) \ + in_dword_masked(HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_ADDR(n), HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_RMSK) +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_ADDR(n), mask) +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_OUTI(n,val) \ + out_dword(HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_ADDR(n),val) +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_ADDR(n),mask,val,HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_INI(n)) +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_DST_RSRC_GRP_3_MAX_LIMIT_BMSK 0x3f000000 +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_DST_RSRC_GRP_3_MAX_LIMIT_SHFT 0x18 +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_DST_RSRC_GRP_3_MIN_LIMIT_BMSK 0x3f0000 +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_DST_RSRC_GRP_3_MIN_LIMIT_SHFT 0x10 +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_DST_RSRC_GRP_2_MAX_LIMIT_BMSK 0x3f00 +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_DST_RSRC_GRP_2_MAX_LIMIT_SHFT 0x8 +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_DST_RSRC_GRP_2_MIN_LIMIT_BMSK 0x3f +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_DST_RSRC_GRP_2_MIN_LIMIT_SHFT 0x0 + +#define HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000608 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000608 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000608 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_RMSK 0x3f3f3f3f +#define HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_MAXn 2 +#define HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_ATTR 0x3 +#define HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_INI(n) \ + in_dword_masked(HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_ADDR(n), HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_RMSK) +#define HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_ADDR(n), mask) +#define HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_OUTI(n,val) \ + out_dword(HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_ADDR(n),val) +#define HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_ADDR(n),mask,val,HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_INI(n)) +#define HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_DST_RSRC_GRP_5_MAX_LIMIT_BMSK 0x3f000000 +#define HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_DST_RSRC_GRP_5_MAX_LIMIT_SHFT 0x18 +#define HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_DST_RSRC_GRP_5_MIN_LIMIT_BMSK 0x3f0000 +#define HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_DST_RSRC_GRP_5_MIN_LIMIT_SHFT 0x10 +#define HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_DST_RSRC_GRP_4_MAX_LIMIT_BMSK 0x3f00 +#define HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_DST_RSRC_GRP_4_MAX_LIMIT_SHFT 0x8 +#define HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_DST_RSRC_GRP_4_MIN_LIMIT_BMSK 0x3f +#define HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_DST_RSRC_GRP_4_MIN_LIMIT_SHFT 0x0 + +#define HWIO_IPA_DST_RSRC_GRP_67_RSRC_TYPE_n_ADDR(n) (IPA_CFG_REG_BASE + 0x0000060c + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_67_RSRC_TYPE_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x0000060c + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_67_RSRC_TYPE_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x0000060c + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_67_RSRC_TYPE_n_RMSK 0x3f3f +#define HWIO_IPA_DST_RSRC_GRP_67_RSRC_TYPE_n_MAXn 2 +#define HWIO_IPA_DST_RSRC_GRP_67_RSRC_TYPE_n_ATTR 0x3 +#define HWIO_IPA_DST_RSRC_GRP_67_RSRC_TYPE_n_INI(n) \ + in_dword_masked(HWIO_IPA_DST_RSRC_GRP_67_RSRC_TYPE_n_ADDR(n), HWIO_IPA_DST_RSRC_GRP_67_RSRC_TYPE_n_RMSK) +#define HWIO_IPA_DST_RSRC_GRP_67_RSRC_TYPE_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_DST_RSRC_GRP_67_RSRC_TYPE_n_ADDR(n), mask) +#define HWIO_IPA_DST_RSRC_GRP_67_RSRC_TYPE_n_OUTI(n,val) \ + out_dword(HWIO_IPA_DST_RSRC_GRP_67_RSRC_TYPE_n_ADDR(n),val) +#define HWIO_IPA_DST_RSRC_GRP_67_RSRC_TYPE_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_DST_RSRC_GRP_67_RSRC_TYPE_n_ADDR(n),mask,val,HWIO_IPA_DST_RSRC_GRP_67_RSRC_TYPE_n_INI(n)) +#define HWIO_IPA_DST_RSRC_GRP_67_RSRC_TYPE_n_DST_RSRC_GRP_6_MAX_LIMIT_BMSK 0x3f00 +#define HWIO_IPA_DST_RSRC_GRP_67_RSRC_TYPE_n_DST_RSRC_GRP_6_MAX_LIMIT_SHFT 0x8 +#define HWIO_IPA_DST_RSRC_GRP_67_RSRC_TYPE_n_DST_RSRC_GRP_6_MIN_LIMIT_BMSK 0x3f +#define HWIO_IPA_DST_RSRC_GRP_67_RSRC_TYPE_n_DST_RSRC_GRP_6_MIN_LIMIT_SHFT 0x0 + +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000610 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000610 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000610 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_RMSK 0x3f3f3f3f +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_MAXn 2 +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_ATTR 0x1 +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_INI(n) \ + in_dword_masked(HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_ADDR(n), HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_RMSK, HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_ATTR) +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_ADDR(n), mask, HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_ATTR) +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_DST_RSRC_GRP_3_CNT_BMSK 0x3f000000 +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_DST_RSRC_GRP_3_CNT_SHFT 0x18 +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_DST_RSRC_GRP_2_CNT_BMSK 0x3f0000 +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_DST_RSRC_GRP_2_CNT_SHFT 0x10 +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_DST_RSRC_GRP_1_CNT_BMSK 0x3f00 +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_DST_RSRC_GRP_1_CNT_SHFT 0x8 +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_DST_RSRC_GRP_0_CNT_BMSK 0x3f +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_DST_RSRC_GRP_0_CNT_SHFT 0x0 + +#define HWIO_IPA_DST_RSRC_GRP_4567_RSRC_TYPE_CNT_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000614 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_4567_RSRC_TYPE_CNT_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000614 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_4567_RSRC_TYPE_CNT_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000614 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_4567_RSRC_TYPE_CNT_n_RMSK 0xffffff +#define HWIO_IPA_DST_RSRC_GRP_4567_RSRC_TYPE_CNT_n_MAXn 2 +#define HWIO_IPA_DST_RSRC_GRP_4567_RSRC_TYPE_CNT_n_ATTR 0x1 +#define HWIO_IPA_DST_RSRC_GRP_4567_RSRC_TYPE_CNT_n_INI(n) \ + in_dword_masked(HWIO_IPA_DST_RSRC_GRP_4567_RSRC_TYPE_CNT_n_ADDR(n), HWIO_IPA_DST_RSRC_GRP_4567_RSRC_TYPE_CNT_n_RMSK) +#define HWIO_IPA_DST_RSRC_GRP_4567_RSRC_TYPE_CNT_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_DST_RSRC_GRP_4567_RSRC_TYPE_CNT_n_ADDR(n), mask) +#define HWIO_IPA_DST_RSRC_GRP_4567_RSRC_TYPE_CNT_n_DST_RSRC_GRP_6_CNT_BMSK 0xff0000 +#define HWIO_IPA_DST_RSRC_GRP_4567_RSRC_TYPE_CNT_n_DST_RSRC_GRP_6_CNT_SHFT 0x10 +#define HWIO_IPA_DST_RSRC_GRP_4567_RSRC_TYPE_CNT_n_DST_RSRC_GRP_5_CNT_BMSK 0xff00 +#define HWIO_IPA_DST_RSRC_GRP_4567_RSRC_TYPE_CNT_n_DST_RSRC_GRP_5_CNT_SHFT 0x8 +#define HWIO_IPA_DST_RSRC_GRP_4567_RSRC_TYPE_CNT_n_DST_RSRC_GRP_4_CNT_BMSK 0xff +#define HWIO_IPA_DST_RSRC_GRP_4567_RSRC_TYPE_CNT_n_DST_RSRC_GRP_4_CNT_SHFT 0x0 + +#define HWIO_IPA_DST_RSRC_TYPE_AMOUNT_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000618 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_TYPE_AMOUNT_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000618 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_TYPE_AMOUNT_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000618 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_TYPE_AMOUNT_n_RMSK 0x3f +#define HWIO_IPA_DST_RSRC_TYPE_AMOUNT_n_MAXn 2 +#define HWIO_IPA_DST_RSRC_TYPE_AMOUNT_n_ATTR 0x1 +#define HWIO_IPA_DST_RSRC_TYPE_AMOUNT_n_INI(n) \ + in_dword_masked(HWIO_IPA_DST_RSRC_TYPE_AMOUNT_n_ADDR(n), HWIO_IPA_DST_RSRC_TYPE_AMOUNT_n_RMSK) +#define HWIO_IPA_DST_RSRC_TYPE_AMOUNT_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_DST_RSRC_TYPE_AMOUNT_n_ADDR(n), mask) +#define HWIO_IPA_DST_RSRC_TYPE_AMOUNT_n_DST_RSRC_TYPE_AMOUNT_BMSK 0x3f +#define HWIO_IPA_DST_RSRC_TYPE_AMOUNT_n_DST_RSRC_TYPE_AMOUNT_SHFT 0x0 + +#define HWIO_IPA_RX_CFG_ADDR (IPA_CFG_REG_BASE + 0x00000698) +#define HWIO_IPA_RX_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000698) +#define HWIO_IPA_RX_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000698) +#define HWIO_IPA_RX_CFG_RMSK 0x3 +#define HWIO_IPA_RX_CFG_ATTR 0x3 +#define HWIO_IPA_RX_CFG_IN \ + in_dword_masked(HWIO_IPA_RX_CFG_ADDR, HWIO_IPA_RX_CFG_RMSK) +#define HWIO_IPA_RX_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_RX_CFG_ADDR, m) +#define HWIO_IPA_RX_CFG_OUT(v) \ + out_dword(HWIO_IPA_RX_CFG_ADDR,v) +#define HWIO_IPA_RX_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_RX_CFG_ADDR,m,v,HWIO_IPA_RX_CFG_IN) +#define HWIO_IPA_RX_CFG_RX_CMDQ_SPLITTER_CMDQ_PENDING_MUX_DISABLE_BMSK 0x2 +#define HWIO_IPA_RX_CFG_RX_CMDQ_SPLITTER_CMDQ_PENDING_MUX_DISABLE_SHFT 0x1 +#define HWIO_IPA_RX_CFG_CMDQ_SPLIT_NOT_WAIT_DATA_DESC_PRIOR_HDR_PUSH_BMSK 0x1 +#define HWIO_IPA_RX_CFG_CMDQ_SPLIT_NOT_WAIT_DATA_DESC_PRIOR_HDR_PUSH_SHFT 0x0 + +#define HWIO_IPA_RSRC_GRP_CFG_ADDR (IPA_CFG_REG_BASE + 0x000006a0) +#define HWIO_IPA_RSRC_GRP_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000006a0) +#define HWIO_IPA_RSRC_GRP_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000006a0) +#define HWIO_IPA_RSRC_GRP_CFG_RMSK 0x3f1ff171 +#define HWIO_IPA_RSRC_GRP_CFG_ATTR 0x3 +#define HWIO_IPA_RSRC_GRP_CFG_IN \ + in_dword_masked(HWIO_IPA_RSRC_GRP_CFG_ADDR, HWIO_IPA_RSRC_GRP_CFG_RMSK) +#define HWIO_IPA_RSRC_GRP_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_RSRC_GRP_CFG_ADDR, m) +#define HWIO_IPA_RSRC_GRP_CFG_OUT(v) \ + out_dword(HWIO_IPA_RSRC_GRP_CFG_ADDR,v) +#define HWIO_IPA_RSRC_GRP_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_RSRC_GRP_CFG_ADDR,m,v,HWIO_IPA_RSRC_GRP_CFG_IN) +#define HWIO_IPA_RSRC_GRP_CFG_DST_GRP_SPECIAL_INDEX_BMSK 0x3f000000 +#define HWIO_IPA_RSRC_GRP_CFG_DST_GRP_SPECIAL_INDEX_SHFT 0x18 +#define HWIO_IPA_RSRC_GRP_CFG_DST_GRP_SPECIAL_VALID_BMSK 0x100000 +#define HWIO_IPA_RSRC_GRP_CFG_DST_GRP_SPECIAL_VALID_SHFT 0x14 +#define HWIO_IPA_RSRC_GRP_CFG_DST_PIPE_SPECIAL_INDEX_BMSK 0xff000 +#define HWIO_IPA_RSRC_GRP_CFG_DST_PIPE_SPECIAL_INDEX_SHFT 0xc +#define HWIO_IPA_RSRC_GRP_CFG_DST_PIPE_SPECIAL_VALID_BMSK 0x100 +#define HWIO_IPA_RSRC_GRP_CFG_DST_PIPE_SPECIAL_VALID_SHFT 0x8 +#define HWIO_IPA_RSRC_GRP_CFG_SRC_GRP_SPECIAL_INDEX_BMSK 0x70 +#define HWIO_IPA_RSRC_GRP_CFG_SRC_GRP_SPECIAL_INDEX_SHFT 0x4 +#define HWIO_IPA_RSRC_GRP_CFG_SRC_GRP_SPECIAL_VALID_BMSK 0x1 +#define HWIO_IPA_RSRC_GRP_CFG_SRC_GRP_SPECIAL_VALID_SHFT 0x0 + +#define HWIO_IPA_RSRC_GRP_CFG_EXT_ADDR (IPA_CFG_REG_BASE + 0x000006a4) +#define HWIO_IPA_RSRC_GRP_CFG_EXT_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000006a4) +#define HWIO_IPA_RSRC_GRP_CFG_EXT_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000006a4) +#define HWIO_IPA_RSRC_GRP_CFG_EXT_RMSK 0x71 +#define HWIO_IPA_RSRC_GRP_CFG_EXT_ATTR 0x3 +#define HWIO_IPA_RSRC_GRP_CFG_EXT_IN \ + in_dword_masked(HWIO_IPA_RSRC_GRP_CFG_EXT_ADDR, HWIO_IPA_RSRC_GRP_CFG_EXT_RMSK) +#define HWIO_IPA_RSRC_GRP_CFG_EXT_INM(m) \ + in_dword_masked(HWIO_IPA_RSRC_GRP_CFG_EXT_ADDR, m) +#define HWIO_IPA_RSRC_GRP_CFG_EXT_OUT(v) \ + out_dword(HWIO_IPA_RSRC_GRP_CFG_EXT_ADDR,v) +#define HWIO_IPA_RSRC_GRP_CFG_EXT_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_RSRC_GRP_CFG_EXT_ADDR,m,v,HWIO_IPA_RSRC_GRP_CFG_EXT_IN) +#define HWIO_IPA_RSRC_GRP_CFG_EXT_SRC_GRP_2ND_PRIORITY_SPECIAL_INDEX_BMSK 0x70 +#define HWIO_IPA_RSRC_GRP_CFG_EXT_SRC_GRP_2ND_PRIORITY_SPECIAL_INDEX_SHFT 0x4 +#define HWIO_IPA_RSRC_GRP_CFG_EXT_SRC_GRP_2ND_PRIORITY_SPECIAL_VALID_BMSK 0x1 +#define HWIO_IPA_RSRC_GRP_CFG_EXT_SRC_GRP_2ND_PRIORITY_SPECIAL_VALID_SHFT 0x0 + +#define HWIO_IPA_AXI_CFG_ADDR (IPA_CFG_REG_BASE + 0x000006ac) +#define HWIO_IPA_AXI_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000006ac) +#define HWIO_IPA_AXI_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000006ac) +#define HWIO_IPA_AXI_CFG_RMSK 0xf +#define HWIO_IPA_AXI_CFG_ATTR 0x3 +#define HWIO_IPA_AXI_CFG_IN \ + in_dword_masked(HWIO_IPA_AXI_CFG_ADDR, HWIO_IPA_AXI_CFG_RMSK) +#define HWIO_IPA_AXI_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_AXI_CFG_ADDR, m) +#define HWIO_IPA_AXI_CFG_OUT(v) \ + out_dword(HWIO_IPA_AXI_CFG_ADDR,v) +#define HWIO_IPA_AXI_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_AXI_CFG_ADDR,m,v,HWIO_IPA_AXI_CFG_IN) +#define HWIO_IPA_AXI_CFG_RELAXED_ORDERING_IPA_WR_BMSK 0x8 +#define HWIO_IPA_AXI_CFG_RELAXED_ORDERING_IPA_WR_SHFT 0x3 +#define HWIO_IPA_AXI_CFG_RELAXED_ORDERING_IPA_RD_BMSK 0x4 +#define HWIO_IPA_AXI_CFG_RELAXED_ORDERING_IPA_RD_SHFT 0x2 +#define HWIO_IPA_AXI_CFG_RELAXED_ORDERING_GSI_WR_BMSK 0x2 +#define HWIO_IPA_AXI_CFG_RELAXED_ORDERING_GSI_WR_SHFT 0x1 +#define HWIO_IPA_AXI_CFG_RELAXED_ORDERING_GSI_RD_BMSK 0x1 +#define HWIO_IPA_AXI_CFG_RELAXED_ORDERING_GSI_RD_SHFT 0x0 + +#define HWIO_IPA_AGGR_FORCE_CLOSE_n_ADDR(n) (IPA_CFG_REG_BASE + 0x000006b0 + 0x4 * (n)) +#define HWIO_IPA_AGGR_FORCE_CLOSE_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x000006b0 + 0x4 * (n)) +#define HWIO_IPA_AGGR_FORCE_CLOSE_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x000006b0 + 0x4 * (n)) +#define HWIO_IPA_AGGR_FORCE_CLOSE_n_RMSK 0xffffffff +#define HWIO_IPA_AGGR_FORCE_CLOSE_n_MAXn 1 +#define HWIO_IPA_AGGR_FORCE_CLOSE_n_ATTR 0x2 +#define HWIO_IPA_AGGR_FORCE_CLOSE_n_OUTI(n,val) \ + out_dword(HWIO_IPA_AGGR_FORCE_CLOSE_n_ADDR(n),val) +#define HWIO_IPA_AGGR_FORCE_CLOSE_n_AGGR_FORCE_CLOSE_PIPE_BITMAP_BMSK 0xffffffff +#define HWIO_IPA_AGGR_FORCE_CLOSE_n_AGGR_FORCE_CLOSE_PIPE_BITMAP_SHFT 0x0 + +#define HWIO_IPA_STAT_QUOTA_BASE_n_ADDR(n) (IPA_CFG_REG_BASE + 0x000006d0 + 0x4 * (n)) +#define HWIO_IPA_STAT_QUOTA_BASE_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x000006d0 + 0x4 * (n)) +#define HWIO_IPA_STAT_QUOTA_BASE_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x000006d0 + 0x4 * (n)) +#define HWIO_IPA_STAT_QUOTA_BASE_n_RMSK 0x7ffff +#define HWIO_IPA_STAT_QUOTA_BASE_n_MAXn 1 +#define HWIO_IPA_STAT_QUOTA_BASE_n_ATTR 0x3 +#define HWIO_IPA_STAT_QUOTA_BASE_n_INI(n) \ + in_dword_masked(HWIO_IPA_STAT_QUOTA_BASE_n_ADDR(n), HWIO_IPA_STAT_QUOTA_BASE_n_RMSK) +#define HWIO_IPA_STAT_QUOTA_BASE_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_STAT_QUOTA_BASE_n_ADDR(n), mask) +#define HWIO_IPA_STAT_QUOTA_BASE_n_OUTI(n,val) \ + out_dword(HWIO_IPA_STAT_QUOTA_BASE_n_ADDR(n),val) +#define HWIO_IPA_STAT_QUOTA_BASE_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_STAT_QUOTA_BASE_n_ADDR(n),mask,val,HWIO_IPA_STAT_QUOTA_BASE_n_INI(n)) +#define HWIO_IPA_STAT_QUOTA_BASE_n_BASE_ADDR_BMSK 0x7fff8 +#define HWIO_IPA_STAT_QUOTA_BASE_n_BASE_ADDR_SHFT 0x3 +#define HWIO_IPA_STAT_QUOTA_BASE_n_BASE_ADDR_OFFSET_BMSK 0x7 +#define HWIO_IPA_STAT_QUOTA_BASE_n_BASE_ADDR_OFFSET_SHFT 0x0 + +#define HWIO_IPA_STAT_TETHERING_BASE_n_ADDR(n) (IPA_CFG_REG_BASE + 0x000006e0 + 0x4 * (n)) +#define HWIO_IPA_STAT_TETHERING_BASE_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x000006e0 + 0x4 * (n)) +#define HWIO_IPA_STAT_TETHERING_BASE_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x000006e0 + 0x4 * (n)) +#define HWIO_IPA_STAT_TETHERING_BASE_n_RMSK 0x7ffff +#define HWIO_IPA_STAT_TETHERING_BASE_n_MAXn 1 +#define HWIO_IPA_STAT_TETHERING_BASE_n_ATTR 0x3 +#define HWIO_IPA_STAT_TETHERING_BASE_n_INI(n) \ + in_dword_masked(HWIO_IPA_STAT_TETHERING_BASE_n_ADDR(n), HWIO_IPA_STAT_TETHERING_BASE_n_RMSK) +#define HWIO_IPA_STAT_TETHERING_BASE_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_STAT_TETHERING_BASE_n_ADDR(n), mask) +#define HWIO_IPA_STAT_TETHERING_BASE_n_OUTI(n,val) \ + out_dword(HWIO_IPA_STAT_TETHERING_BASE_n_ADDR(n),val) +#define HWIO_IPA_STAT_TETHERING_BASE_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_STAT_TETHERING_BASE_n_ADDR(n),mask,val,HWIO_IPA_STAT_TETHERING_BASE_n_INI(n)) +#define HWIO_IPA_STAT_TETHERING_BASE_n_BASE_ADDR_BMSK 0x7fff8 +#define HWIO_IPA_STAT_TETHERING_BASE_n_BASE_ADDR_SHFT 0x3 +#define HWIO_IPA_STAT_TETHERING_BASE_n_BASE_ADDR_OFFSET_BMSK 0x7 +#define HWIO_IPA_STAT_TETHERING_BASE_n_BASE_ADDR_OFFSET_SHFT 0x0 + +#define HWIO_IPA_STAT_DROP_CNT_BASE_n_ADDR(n) (IPA_CFG_REG_BASE + 0x000006f0 + 0x4 * (n)) +#define HWIO_IPA_STAT_DROP_CNT_BASE_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x000006f0 + 0x4 * (n)) +#define HWIO_IPA_STAT_DROP_CNT_BASE_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x000006f0 + 0x4 * (n)) +#define HWIO_IPA_STAT_DROP_CNT_BASE_n_RMSK 0x7ffff +#define HWIO_IPA_STAT_DROP_CNT_BASE_n_MAXn 1 +#define HWIO_IPA_STAT_DROP_CNT_BASE_n_ATTR 0x3 +#define HWIO_IPA_STAT_DROP_CNT_BASE_n_INI(n) \ + in_dword_masked(HWIO_IPA_STAT_DROP_CNT_BASE_n_ADDR(n), HWIO_IPA_STAT_DROP_CNT_BASE_n_RMSK) +#define HWIO_IPA_STAT_DROP_CNT_BASE_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_STAT_DROP_CNT_BASE_n_ADDR(n), mask) +#define HWIO_IPA_STAT_DROP_CNT_BASE_n_OUTI(n,val) \ + out_dword(HWIO_IPA_STAT_DROP_CNT_BASE_n_ADDR(n),val) +#define HWIO_IPA_STAT_DROP_CNT_BASE_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_STAT_DROP_CNT_BASE_n_ADDR(n),mask,val,HWIO_IPA_STAT_DROP_CNT_BASE_n_INI(n)) +#define HWIO_IPA_STAT_DROP_CNT_BASE_n_BASE_ADDR_BMSK 0x7fff8 +#define HWIO_IPA_STAT_DROP_CNT_BASE_n_BASE_ADDR_SHFT 0x3 +#define HWIO_IPA_STAT_DROP_CNT_BASE_n_BASE_ADDR_OFFSET_BMSK 0x7 +#define HWIO_IPA_STAT_DROP_CNT_BASE_n_BASE_ADDR_OFFSET_SHFT 0x0 + +#define HWIO_IPA_STAT_FILTER_IPV4_BASE_ADDR (IPA_CFG_REG_BASE + 0x00000700) +#define HWIO_IPA_STAT_FILTER_IPV4_BASE_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000700) +#define HWIO_IPA_STAT_FILTER_IPV4_BASE_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000700) +#define HWIO_IPA_STAT_FILTER_IPV4_BASE_RMSK 0x7ffff +#define HWIO_IPA_STAT_FILTER_IPV4_BASE_ATTR 0x3 +#define HWIO_IPA_STAT_FILTER_IPV4_BASE_IN \ + in_dword_masked(HWIO_IPA_STAT_FILTER_IPV4_BASE_ADDR, HWIO_IPA_STAT_FILTER_IPV4_BASE_RMSK) +#define HWIO_IPA_STAT_FILTER_IPV4_BASE_INM(m) \ + in_dword_masked(HWIO_IPA_STAT_FILTER_IPV4_BASE_ADDR, m) +#define HWIO_IPA_STAT_FILTER_IPV4_BASE_OUT(v) \ + out_dword(HWIO_IPA_STAT_FILTER_IPV4_BASE_ADDR,v) +#define HWIO_IPA_STAT_FILTER_IPV4_BASE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_STAT_FILTER_IPV4_BASE_ADDR,m,v,HWIO_IPA_STAT_FILTER_IPV4_BASE_IN) +#define HWIO_IPA_STAT_FILTER_IPV4_BASE_BASE_ADDR_BMSK 0x7fff8 +#define HWIO_IPA_STAT_FILTER_IPV4_BASE_BASE_ADDR_SHFT 0x3 +#define HWIO_IPA_STAT_FILTER_IPV4_BASE_BASE_ADDR_OFFSET_BMSK 0x7 +#define HWIO_IPA_STAT_FILTER_IPV4_BASE_BASE_ADDR_OFFSET_SHFT 0x0 + +#define HWIO_IPA_STAT_FILTER_IPV6_BASE_ADDR (IPA_CFG_REG_BASE + 0x00000704) +#define HWIO_IPA_STAT_FILTER_IPV6_BASE_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000704) +#define HWIO_IPA_STAT_FILTER_IPV6_BASE_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000704) +#define HWIO_IPA_STAT_FILTER_IPV6_BASE_RMSK 0x7ffff +#define HWIO_IPA_STAT_FILTER_IPV6_BASE_ATTR 0x3 +#define HWIO_IPA_STAT_FILTER_IPV6_BASE_IN \ + in_dword_masked(HWIO_IPA_STAT_FILTER_IPV6_BASE_ADDR, HWIO_IPA_STAT_FILTER_IPV6_BASE_RMSK) +#define HWIO_IPA_STAT_FILTER_IPV6_BASE_INM(m) \ + in_dword_masked(HWIO_IPA_STAT_FILTER_IPV6_BASE_ADDR, m) +#define HWIO_IPA_STAT_FILTER_IPV6_BASE_OUT(v) \ + out_dword(HWIO_IPA_STAT_FILTER_IPV6_BASE_ADDR,v) +#define HWIO_IPA_STAT_FILTER_IPV6_BASE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_STAT_FILTER_IPV6_BASE_ADDR,m,v,HWIO_IPA_STAT_FILTER_IPV6_BASE_IN) +#define HWIO_IPA_STAT_FILTER_IPV6_BASE_BASE_ADDR_BMSK 0x7fff8 +#define HWIO_IPA_STAT_FILTER_IPV6_BASE_BASE_ADDR_SHFT 0x3 +#define HWIO_IPA_STAT_FILTER_IPV6_BASE_BASE_ADDR_OFFSET_BMSK 0x7 +#define HWIO_IPA_STAT_FILTER_IPV6_BASE_BASE_ADDR_OFFSET_SHFT 0x0 + +#define HWIO_IPA_STAT_ROUTER_IPV4_BASE_ADDR (IPA_CFG_REG_BASE + 0x00000708) +#define HWIO_IPA_STAT_ROUTER_IPV4_BASE_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000708) +#define HWIO_IPA_STAT_ROUTER_IPV4_BASE_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000708) +#define HWIO_IPA_STAT_ROUTER_IPV4_BASE_RMSK 0x7ffff +#define HWIO_IPA_STAT_ROUTER_IPV4_BASE_ATTR 0x3 +#define HWIO_IPA_STAT_ROUTER_IPV4_BASE_IN \ + in_dword_masked(HWIO_IPA_STAT_ROUTER_IPV4_BASE_ADDR, HWIO_IPA_STAT_ROUTER_IPV4_BASE_RMSK) +#define HWIO_IPA_STAT_ROUTER_IPV4_BASE_INM(m) \ + in_dword_masked(HWIO_IPA_STAT_ROUTER_IPV4_BASE_ADDR, m) +#define HWIO_IPA_STAT_ROUTER_IPV4_BASE_OUT(v) \ + out_dword(HWIO_IPA_STAT_ROUTER_IPV4_BASE_ADDR,v) +#define HWIO_IPA_STAT_ROUTER_IPV4_BASE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_STAT_ROUTER_IPV4_BASE_ADDR,m,v,HWIO_IPA_STAT_ROUTER_IPV4_BASE_IN) +#define HWIO_IPA_STAT_ROUTER_IPV4_BASE_BASE_ADDR_BMSK 0x7fff8 +#define HWIO_IPA_STAT_ROUTER_IPV4_BASE_BASE_ADDR_SHFT 0x3 +#define HWIO_IPA_STAT_ROUTER_IPV4_BASE_BASE_ADDR_OFFSET_BMSK 0x7 +#define HWIO_IPA_STAT_ROUTER_IPV4_BASE_BASE_ADDR_OFFSET_SHFT 0x0 + +#define HWIO_IPA_STAT_ROUTER_IPV6_BASE_ADDR (IPA_CFG_REG_BASE + 0x0000070c) +#define HWIO_IPA_STAT_ROUTER_IPV6_BASE_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000070c) +#define HWIO_IPA_STAT_ROUTER_IPV6_BASE_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000070c) +#define HWIO_IPA_STAT_ROUTER_IPV6_BASE_RMSK 0x7ffff +#define HWIO_IPA_STAT_ROUTER_IPV6_BASE_ATTR 0x3 +#define HWIO_IPA_STAT_ROUTER_IPV6_BASE_IN \ + in_dword_masked(HWIO_IPA_STAT_ROUTER_IPV6_BASE_ADDR, HWIO_IPA_STAT_ROUTER_IPV6_BASE_RMSK) +#define HWIO_IPA_STAT_ROUTER_IPV6_BASE_INM(m) \ + in_dword_masked(HWIO_IPA_STAT_ROUTER_IPV6_BASE_ADDR, m) +#define HWIO_IPA_STAT_ROUTER_IPV6_BASE_OUT(v) \ + out_dword(HWIO_IPA_STAT_ROUTER_IPV6_BASE_ADDR,v) +#define HWIO_IPA_STAT_ROUTER_IPV6_BASE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_STAT_ROUTER_IPV6_BASE_ADDR,m,v,HWIO_IPA_STAT_ROUTER_IPV6_BASE_IN) +#define HWIO_IPA_STAT_ROUTER_IPV6_BASE_BASE_ADDR_BMSK 0x7fff8 +#define HWIO_IPA_STAT_ROUTER_IPV6_BASE_BASE_ADDR_SHFT 0x3 +#define HWIO_IPA_STAT_ROUTER_IPV6_BASE_BASE_ADDR_OFFSET_BMSK 0x7 +#define HWIO_IPA_STAT_ROUTER_IPV6_BASE_BASE_ADDR_OFFSET_SHFT 0x0 + +#define HWIO_IPA_STAT_QUOTA_MASK_EE_n_REG_k_ADDR(n,k) (IPA_CFG_REG_BASE + 0x00000710 + 0x4 * (n) + 0x8 * (k)) +#define HWIO_IPA_STAT_QUOTA_MASK_EE_n_REG_k_PHYS(n,k) (IPA_CFG_REG_BASE_PHYS + 0x00000710 + 0x4 * (n) + 0x8 * (k)) +#define HWIO_IPA_STAT_QUOTA_MASK_EE_n_REG_k_OFFS(n,k) (IPA_CFG_REG_BASE_OFFS + 0x00000710 + 0x4 * (n) + 0x8 * (k)) +#define HWIO_IPA_STAT_QUOTA_MASK_EE_n_REG_k_RMSK 0xffffffff +#define HWIO_IPA_STAT_QUOTA_MASK_EE_n_REG_k_MAXn 1 +#define HWIO_IPA_STAT_QUOTA_MASK_EE_n_REG_k_MAXk 1 +#define HWIO_IPA_STAT_QUOTA_MASK_EE_n_REG_k_ATTR 0x3 +#define HWIO_IPA_STAT_QUOTA_MASK_EE_n_REG_k_INI2(n,k) \ + in_dword_masked(HWIO_IPA_STAT_QUOTA_MASK_EE_n_REG_k_ADDR(n,k), HWIO_IPA_STAT_QUOTA_MASK_EE_n_REG_k_RMSK) +#define HWIO_IPA_STAT_QUOTA_MASK_EE_n_REG_k_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_STAT_QUOTA_MASK_EE_n_REG_k_ADDR(n,k), mask) +#define HWIO_IPA_STAT_QUOTA_MASK_EE_n_REG_k_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_STAT_QUOTA_MASK_EE_n_REG_k_ADDR(n,k),val) +#define HWIO_IPA_STAT_QUOTA_MASK_EE_n_REG_k_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_STAT_QUOTA_MASK_EE_n_REG_k_ADDR(n,k),mask,val,HWIO_IPA_STAT_QUOTA_MASK_EE_n_REG_k_INI2(n,k)) +#define HWIO_IPA_STAT_QUOTA_MASK_EE_n_REG_k_PIPE_MASK_BMSK 0xffffffff +#define HWIO_IPA_STAT_QUOTA_MASK_EE_n_REG_k_PIPE_MASK_SHFT 0x0 + +#define HWIO_IPA_STAT_TETHERING_MASK_EE_n_REG_k_ADDR(n,k) (IPA_CFG_REG_BASE + 0x00000750 + 0x4 * (n) + 0x8 * (k)) +#define HWIO_IPA_STAT_TETHERING_MASK_EE_n_REG_k_PHYS(n,k) (IPA_CFG_REG_BASE_PHYS + 0x00000750 + 0x4 * (n) + 0x8 * (k)) +#define HWIO_IPA_STAT_TETHERING_MASK_EE_n_REG_k_OFFS(n,k) (IPA_CFG_REG_BASE_OFFS + 0x00000750 + 0x4 * (n) + 0x8 * (k)) +#define HWIO_IPA_STAT_TETHERING_MASK_EE_n_REG_k_RMSK 0xffffffff +#define HWIO_IPA_STAT_TETHERING_MASK_EE_n_REG_k_MAXn 1 +#define HWIO_IPA_STAT_TETHERING_MASK_EE_n_REG_k_MAXk 1 +#define HWIO_IPA_STAT_TETHERING_MASK_EE_n_REG_k_ATTR 0x3 +#define HWIO_IPA_STAT_TETHERING_MASK_EE_n_REG_k_INI2(n,k) \ + in_dword_masked(HWIO_IPA_STAT_TETHERING_MASK_EE_n_REG_k_ADDR(n,k), HWIO_IPA_STAT_TETHERING_MASK_EE_n_REG_k_RMSK) +#define HWIO_IPA_STAT_TETHERING_MASK_EE_n_REG_k_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_STAT_TETHERING_MASK_EE_n_REG_k_ADDR(n,k), mask) +#define HWIO_IPA_STAT_TETHERING_MASK_EE_n_REG_k_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_STAT_TETHERING_MASK_EE_n_REG_k_ADDR(n,k),val) +#define HWIO_IPA_STAT_TETHERING_MASK_EE_n_REG_k_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_STAT_TETHERING_MASK_EE_n_REG_k_ADDR(n,k),mask,val,HWIO_IPA_STAT_TETHERING_MASK_EE_n_REG_k_INI2(n,k)) +#define HWIO_IPA_STAT_TETHERING_MASK_EE_n_REG_k_PIPE_MASK_BMSK 0xffffffff +#define HWIO_IPA_STAT_TETHERING_MASK_EE_n_REG_k_PIPE_MASK_SHFT 0x0 + +#define HWIO_IPA_STAT_DROP_CNT_MASK_EE_n_REG_k_ADDR(n,k) (IPA_CFG_REG_BASE + 0x00000790 + 0x4 * (n) + 0x8 * (k)) +#define HWIO_IPA_STAT_DROP_CNT_MASK_EE_n_REG_k_PHYS(n,k) (IPA_CFG_REG_BASE_PHYS + 0x00000790 + 0x4 * (n) + 0x8 * (k)) +#define HWIO_IPA_STAT_DROP_CNT_MASK_EE_n_REG_k_OFFS(n,k) (IPA_CFG_REG_BASE_OFFS + 0x00000790 + 0x4 * (n) + 0x8 * (k)) +#define HWIO_IPA_STAT_DROP_CNT_MASK_EE_n_REG_k_RMSK 0xffffffff +#define HWIO_IPA_STAT_DROP_CNT_MASK_EE_n_REG_k_MAXn 1 +#define HWIO_IPA_STAT_DROP_CNT_MASK_EE_n_REG_k_MAXk 1 +#define HWIO_IPA_STAT_DROP_CNT_MASK_EE_n_REG_k_ATTR 0x3 +#define HWIO_IPA_STAT_DROP_CNT_MASK_EE_n_REG_k_INI2(n,k) \ + in_dword_masked(HWIO_IPA_STAT_DROP_CNT_MASK_EE_n_REG_k_ADDR(n,k), HWIO_IPA_STAT_DROP_CNT_MASK_EE_n_REG_k_RMSK) +#define HWIO_IPA_STAT_DROP_CNT_MASK_EE_n_REG_k_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_STAT_DROP_CNT_MASK_EE_n_REG_k_ADDR(n,k), mask) +#define HWIO_IPA_STAT_DROP_CNT_MASK_EE_n_REG_k_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_STAT_DROP_CNT_MASK_EE_n_REG_k_ADDR(n,k),val) +#define HWIO_IPA_STAT_DROP_CNT_MASK_EE_n_REG_k_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_STAT_DROP_CNT_MASK_EE_n_REG_k_ADDR(n,k),mask,val,HWIO_IPA_STAT_DROP_CNT_MASK_EE_n_REG_k_INI2(n,k)) +#define HWIO_IPA_STAT_DROP_CNT_MASK_EE_n_REG_k_PIPE_MASK_BMSK 0xffffffff +#define HWIO_IPA_STAT_DROP_CNT_MASK_EE_n_REG_k_PIPE_MASK_SHFT 0x0 + +#define HWIO_IPA_NLO_PP_CFG1_ADDR (IPA_CFG_REG_BASE + 0x000007d0) +#define HWIO_IPA_NLO_PP_CFG1_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000007d0) +#define HWIO_IPA_NLO_PP_CFG1_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000007d0) +#define HWIO_IPA_NLO_PP_CFG1_RMSK 0xffffffff +#define HWIO_IPA_NLO_PP_CFG1_ATTR 0x3 +#define HWIO_IPA_NLO_PP_CFG1_IN \ + in_dword_masked(HWIO_IPA_NLO_PP_CFG1_ADDR, HWIO_IPA_NLO_PP_CFG1_RMSK) +#define HWIO_IPA_NLO_PP_CFG1_INM(m) \ + in_dword_masked(HWIO_IPA_NLO_PP_CFG1_ADDR, m) +#define HWIO_IPA_NLO_PP_CFG1_OUT(v) \ + out_dword(HWIO_IPA_NLO_PP_CFG1_ADDR,v) +#define HWIO_IPA_NLO_PP_CFG1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_NLO_PP_CFG1_ADDR,m,v,HWIO_IPA_NLO_PP_CFG1_IN) +#define HWIO_IPA_NLO_PP_CFG1_NLO_ACK_MAX_VP_BMSK 0xff000000 +#define HWIO_IPA_NLO_PP_CFG1_NLO_ACK_MAX_VP_SHFT 0x18 +#define HWIO_IPA_NLO_PP_CFG1_NLO_STATUS_PP_BMSK 0xff0000 +#define HWIO_IPA_NLO_PP_CFG1_NLO_STATUS_PP_SHFT 0x10 +#define HWIO_IPA_NLO_PP_CFG1_NLO_DATA_PP_BMSK 0xff00 +#define HWIO_IPA_NLO_PP_CFG1_NLO_DATA_PP_SHFT 0x8 +#define HWIO_IPA_NLO_PP_CFG1_NLO_ACK_PP_BMSK 0xff +#define HWIO_IPA_NLO_PP_CFG1_NLO_ACK_PP_SHFT 0x0 + +#define HWIO_IPA_NLO_PP_CFG2_ADDR (IPA_CFG_REG_BASE + 0x000007d4) +#define HWIO_IPA_NLO_PP_CFG2_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000007d4) +#define HWIO_IPA_NLO_PP_CFG2_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000007d4) +#define HWIO_IPA_NLO_PP_CFG2_RMSK 0x7ffff +#define HWIO_IPA_NLO_PP_CFG2_ATTR 0x3 +#define HWIO_IPA_NLO_PP_CFG2_IN \ + in_dword_masked(HWIO_IPA_NLO_PP_CFG2_ADDR, HWIO_IPA_NLO_PP_CFG2_RMSK) +#define HWIO_IPA_NLO_PP_CFG2_INM(m) \ + in_dword_masked(HWIO_IPA_NLO_PP_CFG2_ADDR, m) +#define HWIO_IPA_NLO_PP_CFG2_OUT(v) \ + out_dword(HWIO_IPA_NLO_PP_CFG2_ADDR,v) +#define HWIO_IPA_NLO_PP_CFG2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_NLO_PP_CFG2_ADDR,m,v,HWIO_IPA_NLO_PP_CFG2_IN) +#define HWIO_IPA_NLO_PP_CFG2_NLO_STATUS_BUFFER_MODE_BMSK 0x40000 +#define HWIO_IPA_NLO_PP_CFG2_NLO_STATUS_BUFFER_MODE_SHFT 0x12 +#define HWIO_IPA_NLO_PP_CFG2_NLO_DATA_BUFFER_MODE_BMSK 0x20000 +#define HWIO_IPA_NLO_PP_CFG2_NLO_DATA_BUFFER_MODE_SHFT 0x11 +#define HWIO_IPA_NLO_PP_CFG2_NLO_ACK_BUFFER_MODE_BMSK 0x10000 +#define HWIO_IPA_NLO_PP_CFG2_NLO_ACK_BUFFER_MODE_SHFT 0x10 +#define HWIO_IPA_NLO_PP_CFG2_NLO_DATA_CLOSE_PADD_BMSK 0xff00 +#define HWIO_IPA_NLO_PP_CFG2_NLO_DATA_CLOSE_PADD_SHFT 0x8 +#define HWIO_IPA_NLO_PP_CFG2_NLO_ACK_CLOSE_PADD_BMSK 0xff +#define HWIO_IPA_NLO_PP_CFG2_NLO_ACK_CLOSE_PADD_SHFT 0x0 + +#define HWIO_IPA_NLO_MIN_DSM_CFG_ADDR (IPA_CFG_REG_BASE + 0x000007d8) +#define HWIO_IPA_NLO_MIN_DSM_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000007d8) +#define HWIO_IPA_NLO_MIN_DSM_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000007d8) +#define HWIO_IPA_NLO_MIN_DSM_CFG_RMSK 0xffffffff +#define HWIO_IPA_NLO_MIN_DSM_CFG_ATTR 0x3 +#define HWIO_IPA_NLO_MIN_DSM_CFG_IN \ + in_dword_masked(HWIO_IPA_NLO_MIN_DSM_CFG_ADDR, HWIO_IPA_NLO_MIN_DSM_CFG_RMSK) +#define HWIO_IPA_NLO_MIN_DSM_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_NLO_MIN_DSM_CFG_ADDR, m) +#define HWIO_IPA_NLO_MIN_DSM_CFG_OUT(v) \ + out_dword(HWIO_IPA_NLO_MIN_DSM_CFG_ADDR,v) +#define HWIO_IPA_NLO_MIN_DSM_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_NLO_MIN_DSM_CFG_ADDR,m,v,HWIO_IPA_NLO_MIN_DSM_CFG_IN) +#define HWIO_IPA_NLO_MIN_DSM_CFG_NLO_DATA_MIN_DSM_LEN_BMSK 0xffff0000 +#define HWIO_IPA_NLO_MIN_DSM_CFG_NLO_DATA_MIN_DSM_LEN_SHFT 0x10 +#define HWIO_IPA_NLO_MIN_DSM_CFG_NLO_ACK_MIN_DSM_LEN_BMSK 0xffff +#define HWIO_IPA_NLO_MIN_DSM_CFG_NLO_ACK_MIN_DSM_LEN_SHFT 0x0 + +#define HWIO_IPA_NLO_VP_AGGR_CFG_LSB_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000800 + 0x8 * (n)) +#define HWIO_IPA_NLO_VP_AGGR_CFG_LSB_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000800 + 0x8 * (n)) +#define HWIO_IPA_NLO_VP_AGGR_CFG_LSB_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000800 + 0x8 * (n)) +#define HWIO_IPA_NLO_VP_AGGR_CFG_LSB_n_RMSK 0x7ffff +#define HWIO_IPA_NLO_VP_AGGR_CFG_LSB_n_MAXn 31 +#define HWIO_IPA_NLO_VP_AGGR_CFG_LSB_n_ATTR 0x3 +#define HWIO_IPA_NLO_VP_AGGR_CFG_LSB_n_INI(n) \ + in_dword_masked(HWIO_IPA_NLO_VP_AGGR_CFG_LSB_n_ADDR(n), HWIO_IPA_NLO_VP_AGGR_CFG_LSB_n_RMSK) +#define HWIO_IPA_NLO_VP_AGGR_CFG_LSB_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_NLO_VP_AGGR_CFG_LSB_n_ADDR(n), mask) +#define HWIO_IPA_NLO_VP_AGGR_CFG_LSB_n_OUTI(n,val) \ + out_dword(HWIO_IPA_NLO_VP_AGGR_CFG_LSB_n_ADDR(n),val) +#define HWIO_IPA_NLO_VP_AGGR_CFG_LSB_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_NLO_VP_AGGR_CFG_LSB_n_ADDR(n),mask,val,HWIO_IPA_NLO_VP_AGGR_CFG_LSB_n_INI(n)) +#define HWIO_IPA_NLO_VP_AGGR_CFG_LSB_n_VP_AGGR_GRAN_SEL_BMSK 0x40000 +#define HWIO_IPA_NLO_VP_AGGR_CFG_LSB_n_VP_AGGR_GRAN_SEL_SHFT 0x12 +#define HWIO_IPA_NLO_VP_AGGR_CFG_LSB_n_VP_HARD_BYTE_LIMIT_EN_BMSK 0x20000 +#define HWIO_IPA_NLO_VP_AGGR_CFG_LSB_n_VP_HARD_BYTE_LIMIT_EN_SHFT 0x11 +#define HWIO_IPA_NLO_VP_AGGR_CFG_LSB_n_VP_BYTE_LIMIT_BMSK 0x1f800 +#define HWIO_IPA_NLO_VP_AGGR_CFG_LSB_n_VP_BYTE_LIMIT_SHFT 0xb +#define HWIO_IPA_NLO_VP_AGGR_CFG_LSB_n_VP_TIME_LIMIT_BMSK 0x7c0 +#define HWIO_IPA_NLO_VP_AGGR_CFG_LSB_n_VP_TIME_LIMIT_SHFT 0x6 +#define HWIO_IPA_NLO_VP_AGGR_CFG_LSB_n_VP_PKT_LIMIT_BMSK 0x3f +#define HWIO_IPA_NLO_VP_AGGR_CFG_LSB_n_VP_PKT_LIMIT_SHFT 0x0 + +#define HWIO_IPA_NLO_VP_LIMIT_CFG_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000804 + 0x8 * (n)) +#define HWIO_IPA_NLO_VP_LIMIT_CFG_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000804 + 0x8 * (n)) +#define HWIO_IPA_NLO_VP_LIMIT_CFG_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000804 + 0x8 * (n)) +#define HWIO_IPA_NLO_VP_LIMIT_CFG_n_RMSK 0xffffffff +#define HWIO_IPA_NLO_VP_LIMIT_CFG_n_MAXn 31 +#define HWIO_IPA_NLO_VP_LIMIT_CFG_n_ATTR 0x3 +#define HWIO_IPA_NLO_VP_LIMIT_CFG_n_INI(n) \ + in_dword_masked(HWIO_IPA_NLO_VP_LIMIT_CFG_n_ADDR(n), HWIO_IPA_NLO_VP_LIMIT_CFG_n_RMSK) +#define HWIO_IPA_NLO_VP_LIMIT_CFG_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_NLO_VP_LIMIT_CFG_n_ADDR(n), mask) +#define HWIO_IPA_NLO_VP_LIMIT_CFG_n_OUTI(n,val) \ + out_dword(HWIO_IPA_NLO_VP_LIMIT_CFG_n_ADDR(n),val) +#define HWIO_IPA_NLO_VP_LIMIT_CFG_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_NLO_VP_LIMIT_CFG_n_ADDR(n),mask,val,HWIO_IPA_NLO_VP_LIMIT_CFG_n_INI(n)) +#define HWIO_IPA_NLO_VP_LIMIT_CFG_n_UPPER_SIZE_BMSK 0xffff0000 +#define HWIO_IPA_NLO_VP_LIMIT_CFG_n_UPPER_SIZE_SHFT 0x10 +#define HWIO_IPA_NLO_VP_LIMIT_CFG_n_LOWER_SIZE_BMSK 0xffff +#define HWIO_IPA_NLO_VP_LIMIT_CFG_n_LOWER_SIZE_SHFT 0x0 + +#define HWIO_IPA_NLO_VP_FLUSH_REQ_ADDR (IPA_CFG_REG_BASE + 0x00000900) +#define HWIO_IPA_NLO_VP_FLUSH_REQ_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000900) +#define HWIO_IPA_NLO_VP_FLUSH_REQ_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000900) +#define HWIO_IPA_NLO_VP_FLUSH_REQ_RMSK 0x80ff00ff +#define HWIO_IPA_NLO_VP_FLUSH_REQ_ATTR 0x3 +#define HWIO_IPA_NLO_VP_FLUSH_REQ_IN \ + in_dword_masked(HWIO_IPA_NLO_VP_FLUSH_REQ_ADDR, HWIO_IPA_NLO_VP_FLUSH_REQ_RMSK) +#define HWIO_IPA_NLO_VP_FLUSH_REQ_INM(m) \ + in_dword_masked(HWIO_IPA_NLO_VP_FLUSH_REQ_ADDR, m) +#define HWIO_IPA_NLO_VP_FLUSH_REQ_OUT(v) \ + out_dword(HWIO_IPA_NLO_VP_FLUSH_REQ_ADDR,v) +#define HWIO_IPA_NLO_VP_FLUSH_REQ_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_NLO_VP_FLUSH_REQ_ADDR,m,v,HWIO_IPA_NLO_VP_FLUSH_REQ_IN) +#define HWIO_IPA_NLO_VP_FLUSH_REQ_VP_FLUSH_REQ_BMSK 0x80000000 +#define HWIO_IPA_NLO_VP_FLUSH_REQ_VP_FLUSH_REQ_SHFT 0x1f +#define HWIO_IPA_NLO_VP_FLUSH_REQ_VP_FLUSH_VP_INDX_BMSK 0xff0000 +#define HWIO_IPA_NLO_VP_FLUSH_REQ_VP_FLUSH_VP_INDX_SHFT 0x10 +#define HWIO_IPA_NLO_VP_FLUSH_REQ_VP_FLUSH_PP_INDX_BMSK 0xff +#define HWIO_IPA_NLO_VP_FLUSH_REQ_VP_FLUSH_PP_INDX_SHFT 0x0 + +#define HWIO_IPA_NLO_VP_FLUSH_COOKIE_ADDR (IPA_CFG_REG_BASE + 0x00000904) +#define HWIO_IPA_NLO_VP_FLUSH_COOKIE_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000904) +#define HWIO_IPA_NLO_VP_FLUSH_COOKIE_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000904) +#define HWIO_IPA_NLO_VP_FLUSH_COOKIE_RMSK 0xffffffff +#define HWIO_IPA_NLO_VP_FLUSH_COOKIE_ATTR 0x1 +#define HWIO_IPA_NLO_VP_FLUSH_COOKIE_IN \ + in_dword_masked(HWIO_IPA_NLO_VP_FLUSH_COOKIE_ADDR, HWIO_IPA_NLO_VP_FLUSH_COOKIE_RMSK) +#define HWIO_IPA_NLO_VP_FLUSH_COOKIE_INM(m) \ + in_dword_masked(HWIO_IPA_NLO_VP_FLUSH_COOKIE_ADDR, m) +#define HWIO_IPA_NLO_VP_FLUSH_COOKIE_VP_FLUSH_COOKIE_BMSK 0xffffffff +#define HWIO_IPA_NLO_VP_FLUSH_COOKIE_VP_FLUSH_COOKIE_SHFT 0x0 + +#define HWIO_IPA_NLO_VP_FLUSH_ACK_ADDR (IPA_CFG_REG_BASE + 0x00000908) +#define HWIO_IPA_NLO_VP_FLUSH_ACK_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000908) +#define HWIO_IPA_NLO_VP_FLUSH_ACK_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000908) +#define HWIO_IPA_NLO_VP_FLUSH_ACK_RMSK 0x1 +#define HWIO_IPA_NLO_VP_FLUSH_ACK_ATTR 0x1 +#define HWIO_IPA_NLO_VP_FLUSH_ACK_IN \ + in_dword_masked(HWIO_IPA_NLO_VP_FLUSH_ACK_ADDR, HWIO_IPA_NLO_VP_FLUSH_ACK_RMSK) +#define HWIO_IPA_NLO_VP_FLUSH_ACK_INM(m) \ + in_dword_masked(HWIO_IPA_NLO_VP_FLUSH_ACK_ADDR, m) +#define HWIO_IPA_NLO_VP_FLUSH_ACK_VP_FLUSH_ACK_BMSK 0x1 +#define HWIO_IPA_NLO_VP_FLUSH_ACK_VP_FLUSH_ACK_SHFT 0x0 + +#define HWIO_IPA_NLO_VP_DSM_OPEN_ADDR (IPA_CFG_REG_BASE + 0x0000090c) +#define HWIO_IPA_NLO_VP_DSM_OPEN_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000090c) +#define HWIO_IPA_NLO_VP_DSM_OPEN_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000090c) +#define HWIO_IPA_NLO_VP_DSM_OPEN_RMSK 0xffffffff +#define HWIO_IPA_NLO_VP_DSM_OPEN_ATTR 0x1 +#define HWIO_IPA_NLO_VP_DSM_OPEN_IN \ + in_dword_masked(HWIO_IPA_NLO_VP_DSM_OPEN_ADDR, HWIO_IPA_NLO_VP_DSM_OPEN_RMSK) +#define HWIO_IPA_NLO_VP_DSM_OPEN_INM(m) \ + in_dword_masked(HWIO_IPA_NLO_VP_DSM_OPEN_ADDR, m) +#define HWIO_IPA_NLO_VP_DSM_OPEN_VP_DSM_OPEN_BMSK 0xffffffff +#define HWIO_IPA_NLO_VP_DSM_OPEN_VP_DSM_OPEN_SHFT 0x0 + +#define HWIO_IPA_NLO_VP_QBAP_OPEN_ADDR (IPA_CFG_REG_BASE + 0x00000910) +#define HWIO_IPA_NLO_VP_QBAP_OPEN_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000910) +#define HWIO_IPA_NLO_VP_QBAP_OPEN_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000910) +#define HWIO_IPA_NLO_VP_QBAP_OPEN_RMSK 0xffffffff +#define HWIO_IPA_NLO_VP_QBAP_OPEN_ATTR 0x1 +#define HWIO_IPA_NLO_VP_QBAP_OPEN_IN \ + in_dword_masked(HWIO_IPA_NLO_VP_QBAP_OPEN_ADDR, HWIO_IPA_NLO_VP_QBAP_OPEN_RMSK) +#define HWIO_IPA_NLO_VP_QBAP_OPEN_INM(m) \ + in_dword_masked(HWIO_IPA_NLO_VP_QBAP_OPEN_ADDR, m) +#define HWIO_IPA_NLO_VP_QBAP_OPEN_VP_QBAP_OPEN_BMSK 0xffffffff +#define HWIO_IPA_NLO_VP_QBAP_OPEN_VP_QBAP_OPEN_SHFT 0x0 + +#define HWIO_IPA_COAL_MASTER_CFG_ADDR (IPA_CFG_REG_BASE + 0x00000914) +#define HWIO_IPA_COAL_MASTER_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000914) +#define HWIO_IPA_COAL_MASTER_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000914) +#define HWIO_IPA_COAL_MASTER_CFG_RMSK 0x3 +#define HWIO_IPA_COAL_MASTER_CFG_ATTR 0x3 +#define HWIO_IPA_COAL_MASTER_CFG_IN \ + in_dword_masked(HWIO_IPA_COAL_MASTER_CFG_ADDR, HWIO_IPA_COAL_MASTER_CFG_RMSK) +#define HWIO_IPA_COAL_MASTER_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_COAL_MASTER_CFG_ADDR, m) +#define HWIO_IPA_COAL_MASTER_CFG_OUT(v) \ + out_dword(HWIO_IPA_COAL_MASTER_CFG_ADDR,v) +#define HWIO_IPA_COAL_MASTER_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_COAL_MASTER_CFG_ADDR,m,v,HWIO_IPA_COAL_MASTER_CFG_IN) +#define HWIO_IPA_COAL_MASTER_CFG_COAL_ENHANCED_IPV4_ID_EN_BMSK 0x2 +#define HWIO_IPA_COAL_MASTER_CFG_COAL_ENHANCED_IPV4_ID_EN_SHFT 0x1 +#define HWIO_IPA_COAL_MASTER_CFG_COAL_FORCE_TO_DEFAULT_BMSK 0x1 +#define HWIO_IPA_COAL_MASTER_CFG_COAL_FORCE_TO_DEFAULT_SHFT 0x0 + +#define HWIO_IPA_COAL_EVICT_LRU_ADDR (IPA_CFG_REG_BASE + 0x00000918) +#define HWIO_IPA_COAL_EVICT_LRU_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000918) +#define HWIO_IPA_COAL_EVICT_LRU_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000918) +#define HWIO_IPA_COAL_EVICT_LRU_RMSK 0x3f +#define HWIO_IPA_COAL_EVICT_LRU_ATTR 0x3 +#define HWIO_IPA_COAL_EVICT_LRU_IN \ + in_dword_masked(HWIO_IPA_COAL_EVICT_LRU_ADDR, HWIO_IPA_COAL_EVICT_LRU_RMSK) +#define HWIO_IPA_COAL_EVICT_LRU_INM(m) \ + in_dword_masked(HWIO_IPA_COAL_EVICT_LRU_ADDR, m) +#define HWIO_IPA_COAL_EVICT_LRU_OUT(v) \ + out_dword(HWIO_IPA_COAL_EVICT_LRU_ADDR,v) +#define HWIO_IPA_COAL_EVICT_LRU_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_COAL_EVICT_LRU_ADDR,m,v,HWIO_IPA_COAL_EVICT_LRU_IN) +#define HWIO_IPA_COAL_EVICT_LRU_COAL_VP_LRU_THRSHLD_BMSK 0x3e +#define HWIO_IPA_COAL_EVICT_LRU_COAL_VP_LRU_THRSHLD_SHFT 0x1 +#define HWIO_IPA_COAL_EVICT_LRU_COAL_EVICTION_EN_BMSK 0x1 +#define HWIO_IPA_COAL_EVICT_LRU_COAL_EVICTION_EN_SHFT 0x0 + +#define HWIO_IPA_COAL_QMAP_CFG_ADDR (IPA_CFG_REG_BASE + 0x0000091c) +#define HWIO_IPA_COAL_QMAP_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000091c) +#define HWIO_IPA_COAL_QMAP_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000091c) +#define HWIO_IPA_COAL_QMAP_CFG_RMSK 0x3 +#define HWIO_IPA_COAL_QMAP_CFG_ATTR 0x3 +#define HWIO_IPA_COAL_QMAP_CFG_IN \ + in_dword_masked(HWIO_IPA_COAL_QMAP_CFG_ADDR, HWIO_IPA_COAL_QMAP_CFG_RMSK) +#define HWIO_IPA_COAL_QMAP_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_COAL_QMAP_CFG_ADDR, m) +#define HWIO_IPA_COAL_QMAP_CFG_OUT(v) \ + out_dword(HWIO_IPA_COAL_QMAP_CFG_ADDR,v) +#define HWIO_IPA_COAL_QMAP_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_COAL_QMAP_CFG_ADDR,m,v,HWIO_IPA_COAL_QMAP_CFG_IN) +#define HWIO_IPA_COAL_QMAP_CFG_MUX_ID_BYTE_SEL_BMSK 0x3 +#define HWIO_IPA_COAL_QMAP_CFG_MUX_ID_BYTE_SEL_SHFT 0x0 + +#define HWIO_IPA_SNIFFER_QMB_SEL_ADDR (IPA_CFG_REG_BASE + 0x00000920) +#define HWIO_IPA_SNIFFER_QMB_SEL_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000920) +#define HWIO_IPA_SNIFFER_QMB_SEL_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000920) +#define HWIO_IPA_SNIFFER_QMB_SEL_RMSK 0x1 +#define HWIO_IPA_SNIFFER_QMB_SEL_ATTR 0x3 +#define HWIO_IPA_SNIFFER_QMB_SEL_IN \ + in_dword_masked(HWIO_IPA_SNIFFER_QMB_SEL_ADDR, HWIO_IPA_SNIFFER_QMB_SEL_RMSK) +#define HWIO_IPA_SNIFFER_QMB_SEL_INM(m) \ + in_dword_masked(HWIO_IPA_SNIFFER_QMB_SEL_ADDR, m) +#define HWIO_IPA_SNIFFER_QMB_SEL_OUT(v) \ + out_dword(HWIO_IPA_SNIFFER_QMB_SEL_ADDR,v) +#define HWIO_IPA_SNIFFER_QMB_SEL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_SNIFFER_QMB_SEL_ADDR,m,v,HWIO_IPA_SNIFFER_QMB_SEL_IN) +#define HWIO_IPA_SNIFFER_QMB_SEL_SNIF_QMB_SEL_BMSK 0x1 +#define HWIO_IPA_SNIFFER_QMB_SEL_SNIF_QMB_SEL_SHFT 0x0 + +#define HWIO_IPA_ULSO_CFG_IP_ID_MAX_VALUE_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000924 + 0x4 * (n)) +#define HWIO_IPA_ULSO_CFG_IP_ID_MAX_VALUE_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000924 + 0x4 * (n)) +#define HWIO_IPA_ULSO_CFG_IP_ID_MAX_VALUE_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000924 + 0x4 * (n)) +#define HWIO_IPA_ULSO_CFG_IP_ID_MAX_VALUE_n_RMSK 0xffff +#define HWIO_IPA_ULSO_CFG_IP_ID_MAX_VALUE_n_MAXn 2 +#define HWIO_IPA_ULSO_CFG_IP_ID_MAX_VALUE_n_ATTR 0x3 +#define HWIO_IPA_ULSO_CFG_IP_ID_MAX_VALUE_n_INI(n) \ + in_dword_masked(HWIO_IPA_ULSO_CFG_IP_ID_MAX_VALUE_n_ADDR(n), HWIO_IPA_ULSO_CFG_IP_ID_MAX_VALUE_n_RMSK) +#define HWIO_IPA_ULSO_CFG_IP_ID_MAX_VALUE_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ULSO_CFG_IP_ID_MAX_VALUE_n_ADDR(n), mask) +#define HWIO_IPA_ULSO_CFG_IP_ID_MAX_VALUE_n_OUTI(n,val) \ + out_dword(HWIO_IPA_ULSO_CFG_IP_ID_MAX_VALUE_n_ADDR(n),val) +#define HWIO_IPA_ULSO_CFG_IP_ID_MAX_VALUE_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_ULSO_CFG_IP_ID_MAX_VALUE_n_ADDR(n),mask,val,HWIO_IPA_ULSO_CFG_IP_ID_MAX_VALUE_n_INI(n)) +#define HWIO_IPA_ULSO_CFG_IP_ID_MAX_VALUE_n_IP_ID_MAX_VALUE_BMSK 0xffff +#define HWIO_IPA_ULSO_CFG_IP_ID_MAX_VALUE_n_IP_ID_MAX_VALUE_SHFT 0x0 + +#define HWIO_IPA_ULSO_CFG_IP_ID_MIN_VALUE_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000934 + 0x4 * (n)) +#define HWIO_IPA_ULSO_CFG_IP_ID_MIN_VALUE_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000934 + 0x4 * (n)) +#define HWIO_IPA_ULSO_CFG_IP_ID_MIN_VALUE_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000934 + 0x4 * (n)) +#define HWIO_IPA_ULSO_CFG_IP_ID_MIN_VALUE_n_RMSK 0xffff +#define HWIO_IPA_ULSO_CFG_IP_ID_MIN_VALUE_n_MAXn 2 +#define HWIO_IPA_ULSO_CFG_IP_ID_MIN_VALUE_n_ATTR 0x3 +#define HWIO_IPA_ULSO_CFG_IP_ID_MIN_VALUE_n_INI(n) \ + in_dword_masked(HWIO_IPA_ULSO_CFG_IP_ID_MIN_VALUE_n_ADDR(n), HWIO_IPA_ULSO_CFG_IP_ID_MIN_VALUE_n_RMSK) +#define HWIO_IPA_ULSO_CFG_IP_ID_MIN_VALUE_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ULSO_CFG_IP_ID_MIN_VALUE_n_ADDR(n), mask) +#define HWIO_IPA_ULSO_CFG_IP_ID_MIN_VALUE_n_OUTI(n,val) \ + out_dword(HWIO_IPA_ULSO_CFG_IP_ID_MIN_VALUE_n_ADDR(n),val) +#define HWIO_IPA_ULSO_CFG_IP_ID_MIN_VALUE_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_ULSO_CFG_IP_ID_MIN_VALUE_n_ADDR(n),mask,val,HWIO_IPA_ULSO_CFG_IP_ID_MIN_VALUE_n_INI(n)) +#define HWIO_IPA_ULSO_CFG_IP_ID_MIN_VALUE_n_IP_ID_MIN_VALUE_BMSK 0xffff +#define HWIO_IPA_ULSO_CFG_IP_ID_MIN_VALUE_n_IP_ID_MIN_VALUE_SHFT 0x0 + +#define HWIO_IPA_ENDP_INIT_CTRL_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00001000 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_CTRL_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00001000 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_CTRL_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00001000 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_CTRL_n_RMSK 0x2 +#define HWIO_IPA_ENDP_INIT_CTRL_n_MAXn 35 +#define HWIO_IPA_ENDP_INIT_CTRL_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_CTRL_n_INI(n) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_CTRL_n_ADDR(n), HWIO_IPA_ENDP_INIT_CTRL_n_RMSK) +#define HWIO_IPA_ENDP_INIT_CTRL_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_CTRL_n_ADDR(n), mask) +#define HWIO_IPA_ENDP_INIT_CTRL_n_OUTI(n,val) \ + out_dword(HWIO_IPA_ENDP_INIT_CTRL_n_ADDR(n),val) +#define HWIO_IPA_ENDP_INIT_CTRL_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_ENDP_INIT_CTRL_n_ADDR(n),mask,val,HWIO_IPA_ENDP_INIT_CTRL_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_CTRL_n_ENDP_DELAY_BMSK 0x2 +#define HWIO_IPA_ENDP_INIT_CTRL_n_ENDP_DELAY_SHFT 0x1 + +#define HWIO_IPA_ENDP_INIT_CTRL_SCND_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00001004 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_CTRL_SCND_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00001004 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_CTRL_SCND_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00001004 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_CTRL_SCND_n_RMSK 0x2 +#define HWIO_IPA_ENDP_INIT_CTRL_SCND_n_MAXn 35 +#define HWIO_IPA_ENDP_INIT_CTRL_SCND_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_CTRL_SCND_n_INI(n) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_CTRL_SCND_n_ADDR(n), HWIO_IPA_ENDP_INIT_CTRL_SCND_n_RMSK) +#define HWIO_IPA_ENDP_INIT_CTRL_SCND_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_CTRL_SCND_n_ADDR(n), mask) +#define HWIO_IPA_ENDP_INIT_CTRL_SCND_n_OUTI(n,val) \ + out_dword(HWIO_IPA_ENDP_INIT_CTRL_SCND_n_ADDR(n),val) +#define HWIO_IPA_ENDP_INIT_CTRL_SCND_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_ENDP_INIT_CTRL_SCND_n_ADDR(n),mask,val,HWIO_IPA_ENDP_INIT_CTRL_SCND_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_CTRL_SCND_n_ENDP_DELAY_BMSK 0x2 +#define HWIO_IPA_ENDP_INIT_CTRL_SCND_n_ENDP_DELAY_SHFT 0x1 + +#define HWIO_IPA_ENDP_INIT_CFG_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00001008 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_CFG_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00001008 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_CFG_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00001008 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_CFG_n_RMSK 0x17f +#define HWIO_IPA_ENDP_INIT_CFG_n_MAXn 35 +#define HWIO_IPA_ENDP_INIT_CFG_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_CFG_n_INI(n) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_CFG_n_ADDR(n), HWIO_IPA_ENDP_INIT_CFG_n_RMSK) +#define HWIO_IPA_ENDP_INIT_CFG_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_CFG_n_ADDR(n), mask) +#define HWIO_IPA_ENDP_INIT_CFG_n_OUTI(n,val) \ + out_dword(HWIO_IPA_ENDP_INIT_CFG_n_ADDR(n),val) +#define HWIO_IPA_ENDP_INIT_CFG_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_ENDP_INIT_CFG_n_ADDR(n),mask,val,HWIO_IPA_ENDP_INIT_CFG_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_CFG_n_GEN_QMB_MASTER_SEL_BMSK 0x100 +#define HWIO_IPA_ENDP_INIT_CFG_n_GEN_QMB_MASTER_SEL_SHFT 0x8 +#define HWIO_IPA_ENDP_INIT_CFG_n_CS_METADATA_HDR_OFFSET_BMSK 0x78 +#define HWIO_IPA_ENDP_INIT_CFG_n_CS_METADATA_HDR_OFFSET_SHFT 0x3 +#define HWIO_IPA_ENDP_INIT_CFG_n_CS_OFFLOAD_EN_BMSK 0x6 +#define HWIO_IPA_ENDP_INIT_CFG_n_CS_OFFLOAD_EN_SHFT 0x1 +#define HWIO_IPA_ENDP_INIT_CFG_n_FRAG_OFFLOAD_EN_BMSK 0x1 +#define HWIO_IPA_ENDP_INIT_CFG_n_FRAG_OFFLOAD_EN_SHFT 0x0 + +#define HWIO_IPA_ENDP_INIT_NAT_n_ADDR(n) (IPA_CFG_REG_BASE + 0x0000100c + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_NAT_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x0000100c + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_NAT_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x0000100c + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_NAT_n_RMSK 0x3 +#define HWIO_IPA_ENDP_INIT_NAT_n_MAXn 15 +#define HWIO_IPA_ENDP_INIT_NAT_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_NAT_n_INI(n) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_NAT_n_ADDR(n), HWIO_IPA_ENDP_INIT_NAT_n_RMSK) +#define HWIO_IPA_ENDP_INIT_NAT_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_NAT_n_ADDR(n), mask) +#define HWIO_IPA_ENDP_INIT_NAT_n_OUTI(n,val) \ + out_dword(HWIO_IPA_ENDP_INIT_NAT_n_ADDR(n),val) +#define HWIO_IPA_ENDP_INIT_NAT_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_ENDP_INIT_NAT_n_ADDR(n),mask,val,HWIO_IPA_ENDP_INIT_NAT_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_NAT_n_NAT_EN_BMSK 0x3 +#define HWIO_IPA_ENDP_INIT_NAT_n_NAT_EN_SHFT 0x0 + +#define HWIO_IPA_ENDP_INIT_HDR_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00001010 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_HDR_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00001010 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_HDR_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00001010 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_HDR_n_RMSK 0xfbffffff +#define HWIO_IPA_ENDP_INIT_HDR_n_MAXn 35 +#define HWIO_IPA_ENDP_INIT_HDR_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_HDR_n_INI(n) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_HDR_n_ADDR(n), HWIO_IPA_ENDP_INIT_HDR_n_RMSK) +#define HWIO_IPA_ENDP_INIT_HDR_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_HDR_n_ADDR(n), mask) +#define HWIO_IPA_ENDP_INIT_HDR_n_OUTI(n,val) \ + out_dword(HWIO_IPA_ENDP_INIT_HDR_n_ADDR(n),val) +#define HWIO_IPA_ENDP_INIT_HDR_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_ENDP_INIT_HDR_n_ADDR(n),mask,val,HWIO_IPA_ENDP_INIT_HDR_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_MSB_BMSK 0xc0000000 +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_MSB_SHFT 0x1e +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_LEN_MSB_BMSK 0x30000000 +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_LEN_MSB_SHFT 0x1c +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_LEN_INC_DEAGG_HDR_BMSK 0x8000000 +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_LEN_INC_DEAGG_HDR_SHFT 0x1b +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_OFST_PKT_SIZE_BMSK 0x3f00000 +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_OFST_PKT_SIZE_SHFT 0x14 +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_OFST_PKT_SIZE_VALID_BMSK 0x80000 +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_OFST_PKT_SIZE_VALID_SHFT 0x13 +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_ADDITIONAL_CONST_LEN_BMSK 0x7e000 +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_ADDITIONAL_CONST_LEN_SHFT 0xd +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_BMSK 0x1f80 +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_SHFT 0x7 +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_VALID_BMSK 0x40 +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_VALID_SHFT 0x6 +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_LEN_BMSK 0x3f +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_LEN_SHFT 0x0 + +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00001014 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00001014 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00001014 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_RMSK 0xff7f3fff +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_MAXn 35 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_INI(n) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_HDR_EXT_n_ADDR(n), HWIO_IPA_ENDP_INIT_HDR_EXT_n_RMSK) +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_HDR_EXT_n_ADDR(n), mask) +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_OUTI(n,val) \ + out_dword(HWIO_IPA_ENDP_INIT_HDR_EXT_n_ADDR(n),val) +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_ENDP_INIT_HDR_EXT_n_ADDR(n),mask,val,HWIO_IPA_ENDP_INIT_HDR_EXT_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_BYTES_TO_REMOVE_BMSK 0xff000000 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_BYTES_TO_REMOVE_SHFT 0x18 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_BYTES_TO_REMOVE_VALID_BMSK 0x400000 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_BYTES_TO_REMOVE_VALID_SHFT 0x16 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_ADDITIONAL_CONST_LEN_MSB_BMSK 0x300000 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_ADDITIONAL_CONST_LEN_MSB_SHFT 0x14 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_OFST_PKT_SIZE_MSB_BMSK 0xc0000 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_OFST_PKT_SIZE_MSB_SHFT 0x12 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB_BMSK 0x30000 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB_SHFT 0x10 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_PAD_TO_ALIGNMENT_BMSK 0x3c00 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_PAD_TO_ALIGNMENT_SHFT 0xa +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_OFFSET_BMSK 0x3f0 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_OFFSET_SHFT 0x4 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_PAYLOAD_LEN_INC_PADDING_BMSK 0x8 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_PAYLOAD_LEN_INC_PADDING_SHFT 0x3 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_BMSK 0x4 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_SHFT 0x2 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_VALID_BMSK 0x2 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_VALID_SHFT 0x1 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_ENDIANESS_BMSK 0x1 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_ENDIANESS_SHFT 0x0 + +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00001018 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00001018 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00001018 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_RMSK 0xffffffff +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_MAXn 35 +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_INI(n) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_ADDR(n), HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_RMSK) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_ADDR(n), mask) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_OUTI(n,val) \ + out_dword(HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_ADDR(n),val) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_ADDR(n),mask,val,HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_METADATA_MASK_BMSK 0xffffffff +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_METADATA_MASK_SHFT 0x0 + +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_n_ADDR(n) (IPA_CFG_REG_BASE + 0x0000101c + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x0000101c + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x0000101c + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_n_RMSK 0xffffffff +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_n_MAXn 15 +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_n_INI(n) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_HDR_METADATA_n_ADDR(n), HWIO_IPA_ENDP_INIT_HDR_METADATA_n_RMSK) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_HDR_METADATA_n_ADDR(n), mask) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_n_OUTI(n,val) \ + out_dword(HWIO_IPA_ENDP_INIT_HDR_METADATA_n_ADDR(n),val) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_ENDP_INIT_HDR_METADATA_n_ADDR(n),mask,val,HWIO_IPA_ENDP_INIT_HDR_METADATA_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_n_METADATA_BMSK 0xffffffff +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_n_METADATA_SHFT 0x0 + +#define HWIO_IPA_ENDP_INIT_MODE_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00001020 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_MODE_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00001020 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_MODE_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00001020 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_MODE_n_RMSK 0x7fffffff +#define HWIO_IPA_ENDP_INIT_MODE_n_MAXn 15 +#define HWIO_IPA_ENDP_INIT_MODE_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_MODE_n_INI(n) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_MODE_n_ADDR(n), HWIO_IPA_ENDP_INIT_MODE_n_RMSK) +#define HWIO_IPA_ENDP_INIT_MODE_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_MODE_n_ADDR(n), mask) +#define HWIO_IPA_ENDP_INIT_MODE_n_OUTI(n,val) \ + out_dword(HWIO_IPA_ENDP_INIT_MODE_n_ADDR(n),val) +#define HWIO_IPA_ENDP_INIT_MODE_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_ENDP_INIT_MODE_n_ADDR(n),mask,val,HWIO_IPA_ENDP_INIT_MODE_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_MODE_n_DRBIP_ACL_ENABLE_BMSK 0x40000000 +#define HWIO_IPA_ENDP_INIT_MODE_n_DRBIP_ACL_ENABLE_SHFT 0x1e +#define HWIO_IPA_ENDP_INIT_MODE_n_PAD_EN_BMSK 0x20000000 +#define HWIO_IPA_ENDP_INIT_MODE_n_PAD_EN_SHFT 0x1d +#define HWIO_IPA_ENDP_INIT_MODE_n_PIPE_REPLICATE_EN_BMSK 0x10000000 +#define HWIO_IPA_ENDP_INIT_MODE_n_PIPE_REPLICATE_EN_SHFT 0x1c +#define HWIO_IPA_ENDP_INIT_MODE_n_BYTE_THRESHOLD_BMSK 0xffff000 +#define HWIO_IPA_ENDP_INIT_MODE_n_BYTE_THRESHOLD_SHFT 0xc +#define HWIO_IPA_ENDP_INIT_MODE_n_DEST_PIPE_INDEX_BMSK 0xff0 +#define HWIO_IPA_ENDP_INIT_MODE_n_DEST_PIPE_INDEX_SHFT 0x4 +#define HWIO_IPA_ENDP_INIT_MODE_n_BEARER_CNTX_ENABLE_BMSK 0x8 +#define HWIO_IPA_ENDP_INIT_MODE_n_BEARER_CNTX_ENABLE_SHFT 0x3 +#define HWIO_IPA_ENDP_INIT_MODE_n_MODE_BMSK 0x7 +#define HWIO_IPA_ENDP_INIT_MODE_n_MODE_SHFT 0x0 + +#define HWIO_IPA_ENDP_INIT_AGGR_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00001024 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_AGGR_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00001024 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_AGGR_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00001024 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_AGGR_n_RMSK 0xdfff7ff +#define HWIO_IPA_ENDP_INIT_AGGR_n_MAXn 35 +#define HWIO_IPA_ENDP_INIT_AGGR_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_AGGR_n_INI(n) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_AGGR_n_ADDR(n), HWIO_IPA_ENDP_INIT_AGGR_n_RMSK) +#define HWIO_IPA_ENDP_INIT_AGGR_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_AGGR_n_ADDR(n), mask) +#define HWIO_IPA_ENDP_INIT_AGGR_n_OUTI(n,val) \ + out_dword(HWIO_IPA_ENDP_INIT_AGGR_n_ADDR(n),val) +#define HWIO_IPA_ENDP_INIT_AGGR_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_ENDP_INIT_AGGR_n_ADDR(n),mask,val,HWIO_IPA_ENDP_INIT_AGGR_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_GRAN_SEL_BMSK 0x8000000 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_GRAN_SEL_SHFT 0x1b +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_HARD_BYTE_LIMIT_ENABLE_BMSK 0x4000000 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_HARD_BYTE_LIMIT_ENABLE_SHFT 0x1a +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_FORCE_CLOSE_BMSK 0x1000000 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_FORCE_CLOSE_SHFT 0x18 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_SW_EOF_ACTIVE_BMSK 0x800000 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_SW_EOF_ACTIVE_SHFT 0x17 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_PKT_LIMIT_BMSK 0x7e0000 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_PKT_LIMIT_SHFT 0x11 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_TIME_LIMIT_BMSK 0x1f000 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_TIME_LIMIT_SHFT 0xc +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_BYTE_LIMIT_BMSK 0x7e0 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_BYTE_LIMIT_SHFT 0x5 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_TYPE_BMSK 0x1c +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_TYPE_SHFT 0x2 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_EN_BMSK 0x3 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_EN_SHFT 0x0 + +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_ADDR(n) (IPA_CFG_REG_BASE + 0x0000102c + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x0000102c + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x0000102c + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_RMSK 0x1 +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_MAXn 35 +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_INI(n) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_ADDR(n), HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_RMSK) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_ADDR(n), mask) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_OUTI(n,val) \ + out_dword(HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_ADDR(n),val) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_ADDR(n),mask,val,HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_EN_BMSK 0x1 +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_EN_SHFT 0x0 + +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00001030 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00001030 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00001030 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_RMSK 0x31f +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_MAXn 35 +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_INI(n) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_ADDR(n), HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_RMSK) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_ADDR(n), mask) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_OUTI(n,val) \ + out_dword(HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_ADDR(n),val) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_ADDR(n),mask,val,HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_GRAN_SEL_BMSK 0x300 +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_GRAN_SEL_SHFT 0x8 +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_TIME_LIMIT_BMSK 0x1f +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_TIME_LIMIT_SHFT 0x0 + +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00001034 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00001034 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00001034 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_RMSK 0xffff7fff +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_MAXn 15 +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_INI(n) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_DEAGGR_n_ADDR(n), HWIO_IPA_ENDP_INIT_DEAGGR_n_RMSK) +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_DEAGGR_n_ADDR(n), mask) +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_OUTI(n,val) \ + out_dword(HWIO_IPA_ENDP_INIT_DEAGGR_n_ADDR(n),val) +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_ENDP_INIT_DEAGGR_n_ADDR(n),mask,val,HWIO_IPA_ENDP_INIT_DEAGGR_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_MAX_PACKET_LEN_BMSK 0xffff0000 +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_MAX_PACKET_LEN_SHFT 0x10 +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_IGNORE_MIN_PKT_ERR_BMSK 0x4000 +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_IGNORE_MIN_PKT_ERR_SHFT 0xe +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_PACKET_OFFSET_LOCATION_BMSK 0x3f00 +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_PACKET_OFFSET_LOCATION_SHFT 0x8 +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_PACKET_OFFSET_VALID_BMSK 0x80 +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_PACKET_OFFSET_VALID_SHFT 0x7 +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_SYSPIPE_ERR_DETECTION_BMSK 0x40 +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_SYSPIPE_ERR_DETECTION_SHFT 0x6 +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_DEAGGR_HDR_LEN_BMSK 0x3f +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_DEAGGR_HDR_LEN_SHFT 0x0 + +#define HWIO_IPA_ENDP_INIT_RSRC_GRP_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00001038 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_RSRC_GRP_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00001038 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_RSRC_GRP_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00001038 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_RSRC_GRP_n_RMSK 0x7 +#define HWIO_IPA_ENDP_INIT_RSRC_GRP_n_MAXn 35 +#define HWIO_IPA_ENDP_INIT_RSRC_GRP_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_RSRC_GRP_n_INI(n) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_RSRC_GRP_n_ADDR(n), HWIO_IPA_ENDP_INIT_RSRC_GRP_n_RMSK) +#define HWIO_IPA_ENDP_INIT_RSRC_GRP_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_RSRC_GRP_n_ADDR(n), mask) +#define HWIO_IPA_ENDP_INIT_RSRC_GRP_n_OUTI(n,val) \ + out_dword(HWIO_IPA_ENDP_INIT_RSRC_GRP_n_ADDR(n),val) +#define HWIO_IPA_ENDP_INIT_RSRC_GRP_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_ENDP_INIT_RSRC_GRP_n_ADDR(n),mask,val,HWIO_IPA_ENDP_INIT_RSRC_GRP_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_BMSK 0x7 +#define HWIO_IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_SHFT 0x0 + +#define HWIO_IPA_ENDP_INIT_SEQ_n_ADDR(n) (IPA_CFG_REG_BASE + 0x0000103c + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_SEQ_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x0000103c + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_SEQ_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x0000103c + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_SEQ_n_RMSK 0x1f1f +#define HWIO_IPA_ENDP_INIT_SEQ_n_MAXn 15 +#define HWIO_IPA_ENDP_INIT_SEQ_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_SEQ_n_INI(n) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_SEQ_n_ADDR(n), HWIO_IPA_ENDP_INIT_SEQ_n_RMSK) +#define HWIO_IPA_ENDP_INIT_SEQ_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_SEQ_n_ADDR(n), mask) +#define HWIO_IPA_ENDP_INIT_SEQ_n_OUTI(n,val) \ + out_dword(HWIO_IPA_ENDP_INIT_SEQ_n_ADDR(n),val) +#define HWIO_IPA_ENDP_INIT_SEQ_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_ENDP_INIT_SEQ_n_ADDR(n),mask,val,HWIO_IPA_ENDP_INIT_SEQ_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_SEQ_n_DPS_SEQ_TYPE_BMSK 0x1f00 +#define HWIO_IPA_ENDP_INIT_SEQ_n_DPS_SEQ_TYPE_SHFT 0x8 +#define HWIO_IPA_ENDP_INIT_SEQ_n_HPS_SEQ_TYPE_BMSK 0x1f +#define HWIO_IPA_ENDP_INIT_SEQ_n_HPS_SEQ_TYPE_SHFT 0x0 + +#define HWIO_IPA_ENDP_STATUS_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00001040 + 0x80 * (n)) +#define HWIO_IPA_ENDP_STATUS_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00001040 + 0x80 * (n)) +#define HWIO_IPA_ENDP_STATUS_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00001040 + 0x80 * (n)) +#define HWIO_IPA_ENDP_STATUS_n_RMSK 0x3ff +#define HWIO_IPA_ENDP_STATUS_n_MAXn 35 +#define HWIO_IPA_ENDP_STATUS_n_ATTR 0x3 +#define HWIO_IPA_ENDP_STATUS_n_INI(n) \ + in_dword_masked(HWIO_IPA_ENDP_STATUS_n_ADDR(n), HWIO_IPA_ENDP_STATUS_n_RMSK) +#define HWIO_IPA_ENDP_STATUS_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ENDP_STATUS_n_ADDR(n), mask) +#define HWIO_IPA_ENDP_STATUS_n_OUTI(n,val) \ + out_dword(HWIO_IPA_ENDP_STATUS_n_ADDR(n),val) +#define HWIO_IPA_ENDP_STATUS_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_ENDP_STATUS_n_ADDR(n),mask,val,HWIO_IPA_ENDP_STATUS_n_INI(n)) +#define HWIO_IPA_ENDP_STATUS_n_STATUS_PKT_SUPRESS_BMSK 0x200 +#define HWIO_IPA_ENDP_STATUS_n_STATUS_PKT_SUPRESS_SHFT 0x9 +#define HWIO_IPA_ENDP_STATUS_n_STATUS_ENDP_BMSK 0x1fe +#define HWIO_IPA_ENDP_STATUS_n_STATUS_ENDP_SHFT 0x1 +#define HWIO_IPA_ENDP_STATUS_n_STATUS_EN_BMSK 0x1 +#define HWIO_IPA_ENDP_STATUS_n_STATUS_EN_SHFT 0x0 + +#define HWIO_IPA_ENDP_SRC_ID_WRITE_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00001048 + 0x80 * (n)) +#define HWIO_IPA_ENDP_SRC_ID_WRITE_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00001048 + 0x80 * (n)) +#define HWIO_IPA_ENDP_SRC_ID_WRITE_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00001048 + 0x80 * (n)) +#define HWIO_IPA_ENDP_SRC_ID_WRITE_n_RMSK 0xff +#define HWIO_IPA_ENDP_SRC_ID_WRITE_n_MAXn 15 +#define HWIO_IPA_ENDP_SRC_ID_WRITE_n_ATTR 0x2 +#define HWIO_IPA_ENDP_SRC_ID_WRITE_n_OUTI(n,val) \ + out_dword(HWIO_IPA_ENDP_SRC_ID_WRITE_n_ADDR(n),val) +#define HWIO_IPA_ENDP_SRC_ID_WRITE_n_SRC_ID_WRITE_VALUE_BMSK 0xff +#define HWIO_IPA_ENDP_SRC_ID_WRITE_n_SRC_ID_WRITE_VALUE_SHFT 0x0 + +#define HWIO_IPA_ENDP_SRC_ID_READ_n_ADDR(n) (IPA_CFG_REG_BASE + 0x0000104c + 0x80 * (n)) +#define HWIO_IPA_ENDP_SRC_ID_READ_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x0000104c + 0x80 * (n)) +#define HWIO_IPA_ENDP_SRC_ID_READ_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x0000104c + 0x80 * (n)) +#define HWIO_IPA_ENDP_SRC_ID_READ_n_RMSK 0xff +#define HWIO_IPA_ENDP_SRC_ID_READ_n_MAXn 15 +#define HWIO_IPA_ENDP_SRC_ID_READ_n_ATTR 0x1 +#define HWIO_IPA_ENDP_SRC_ID_READ_n_INI(n) \ + in_dword_masked(HWIO_IPA_ENDP_SRC_ID_READ_n_ADDR(n), HWIO_IPA_ENDP_SRC_ID_READ_n_RMSK) +#define HWIO_IPA_ENDP_SRC_ID_READ_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ENDP_SRC_ID_READ_n_ADDR(n), mask) +#define HWIO_IPA_ENDP_SRC_ID_READ_n_SRC_ID_READ_VALUE_BMSK 0xff +#define HWIO_IPA_ENDP_SRC_ID_READ_n_SRC_ID_READ_VALUE_SHFT 0x0 + +#define HWIO_IPA_ENDP_INIT_CONN_TRACK_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00001050 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_CONN_TRACK_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00001050 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_CONN_TRACK_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00001050 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_CONN_TRACK_n_RMSK 0x1 +#define HWIO_IPA_ENDP_INIT_CONN_TRACK_n_MAXn 15 +#define HWIO_IPA_ENDP_INIT_CONN_TRACK_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_CONN_TRACK_n_INI(n) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_CONN_TRACK_n_ADDR(n), HWIO_IPA_ENDP_INIT_CONN_TRACK_n_RMSK) +#define HWIO_IPA_ENDP_INIT_CONN_TRACK_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_CONN_TRACK_n_ADDR(n), mask) +#define HWIO_IPA_ENDP_INIT_CONN_TRACK_n_OUTI(n,val) \ + out_dword(HWIO_IPA_ENDP_INIT_CONN_TRACK_n_ADDR(n),val) +#define HWIO_IPA_ENDP_INIT_CONN_TRACK_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_ENDP_INIT_CONN_TRACK_n_ADDR(n),mask,val,HWIO_IPA_ENDP_INIT_CONN_TRACK_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_CONN_TRACK_n_CONN_TRACK_EN_BMSK 0x1 +#define HWIO_IPA_ENDP_INIT_CONN_TRACK_n_CONN_TRACK_EN_SHFT 0x0 + +#define HWIO_IPA_ENDP_INIT_DRBIP_CFG_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00001054 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_DRBIP_CFG_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00001054 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_DRBIP_CFG_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00001054 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_DRBIP_CFG_n_RMSK 0x3f +#define HWIO_IPA_ENDP_INIT_DRBIP_CFG_n_MAXn 15 +#define HWIO_IPA_ENDP_INIT_DRBIP_CFG_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_DRBIP_CFG_n_INI(n) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_DRBIP_CFG_n_ADDR(n), HWIO_IPA_ENDP_INIT_DRBIP_CFG_n_RMSK) +#define HWIO_IPA_ENDP_INIT_DRBIP_CFG_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_DRBIP_CFG_n_ADDR(n), mask) +#define HWIO_IPA_ENDP_INIT_DRBIP_CFG_n_OUTI(n,val) \ + out_dword(HWIO_IPA_ENDP_INIT_DRBIP_CFG_n_ADDR(n),val) +#define HWIO_IPA_ENDP_INIT_DRBIP_CFG_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_ENDP_INIT_DRBIP_CFG_n_ADDR(n),mask,val,HWIO_IPA_ENDP_INIT_DRBIP_CFG_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_DRBIP_CFG_n_DATA_SECTORS_FOR_IMM_CMD_BMSK 0x3f +#define HWIO_IPA_ENDP_INIT_DRBIP_CFG_n_DATA_SECTORS_FOR_IMM_CMD_SHFT 0x0 + +#define HWIO_IPA_FILTER_CACHE_CFG_n_ADDR(n) (IPA_CFG_REG_BASE + 0x0000105c + 0x80 * (n)) +#define HWIO_IPA_FILTER_CACHE_CFG_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x0000105c + 0x80 * (n)) +#define HWIO_IPA_FILTER_CACHE_CFG_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x0000105c + 0x80 * (n)) +#define HWIO_IPA_FILTER_CACHE_CFG_n_RMSK 0x7f +#define HWIO_IPA_FILTER_CACHE_CFG_n_MAXn 15 +#define HWIO_IPA_FILTER_CACHE_CFG_n_ATTR 0x3 +#define HWIO_IPA_FILTER_CACHE_CFG_n_INI(n) \ + in_dword_masked(HWIO_IPA_FILTER_CACHE_CFG_n_ADDR(n), HWIO_IPA_FILTER_CACHE_CFG_n_RMSK) +#define HWIO_IPA_FILTER_CACHE_CFG_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_FILTER_CACHE_CFG_n_ADDR(n), mask) +#define HWIO_IPA_FILTER_CACHE_CFG_n_OUTI(n,val) \ + out_dword(HWIO_IPA_FILTER_CACHE_CFG_n_ADDR(n),val) +#define HWIO_IPA_FILTER_CACHE_CFG_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_FILTER_CACHE_CFG_n_ADDR(n),mask,val,HWIO_IPA_FILTER_CACHE_CFG_n_INI(n)) +#define HWIO_IPA_FILTER_CACHE_CFG_n_FILTER_CACHE_MSK_METADATA_BMSK 0x40 +#define HWIO_IPA_FILTER_CACHE_CFG_n_FILTER_CACHE_MSK_METADATA_SHFT 0x6 +#define HWIO_IPA_FILTER_CACHE_CFG_n_FILTER_CACHE_MSK_PROTOCOL_BMSK 0x20 +#define HWIO_IPA_FILTER_CACHE_CFG_n_FILTER_CACHE_MSK_PROTOCOL_SHFT 0x5 +#define HWIO_IPA_FILTER_CACHE_CFG_n_FILTER_CACHE_MSK_DST_PORT_BMSK 0x10 +#define HWIO_IPA_FILTER_CACHE_CFG_n_FILTER_CACHE_MSK_DST_PORT_SHFT 0x4 +#define HWIO_IPA_FILTER_CACHE_CFG_n_FILTER_CACHE_MSK_SRC_PORT_BMSK 0x8 +#define HWIO_IPA_FILTER_CACHE_CFG_n_FILTER_CACHE_MSK_SRC_PORT_SHFT 0x3 +#define HWIO_IPA_FILTER_CACHE_CFG_n_FILTER_CACHE_MSK_DST_IP_ADD_BMSK 0x4 +#define HWIO_IPA_FILTER_CACHE_CFG_n_FILTER_CACHE_MSK_DST_IP_ADD_SHFT 0x2 +#define HWIO_IPA_FILTER_CACHE_CFG_n_FILTER_CACHE_MSK_SRC_IP_ADD_BMSK 0x2 +#define HWIO_IPA_FILTER_CACHE_CFG_n_FILTER_CACHE_MSK_SRC_IP_ADD_SHFT 0x1 +#define HWIO_IPA_FILTER_CACHE_CFG_n_FILTER_CACHE_MSK_SRC_ID_BMSK 0x1 +#define HWIO_IPA_FILTER_CACHE_CFG_n_FILTER_CACHE_MSK_SRC_ID_SHFT 0x0 + +#define HWIO_IPA_ROUTER_CACHE_CFG_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00001070 + 0x80 * (n)) +#define HWIO_IPA_ROUTER_CACHE_CFG_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00001070 + 0x80 * (n)) +#define HWIO_IPA_ROUTER_CACHE_CFG_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00001070 + 0x80 * (n)) +#define HWIO_IPA_ROUTER_CACHE_CFG_n_RMSK 0x7f +#define HWIO_IPA_ROUTER_CACHE_CFG_n_MAXn 35 +#define HWIO_IPA_ROUTER_CACHE_CFG_n_ATTR 0x3 +#define HWIO_IPA_ROUTER_CACHE_CFG_n_INI(n) \ + in_dword_masked(HWIO_IPA_ROUTER_CACHE_CFG_n_ADDR(n), HWIO_IPA_ROUTER_CACHE_CFG_n_RMSK) +#define HWIO_IPA_ROUTER_CACHE_CFG_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ROUTER_CACHE_CFG_n_ADDR(n), mask) +#define HWIO_IPA_ROUTER_CACHE_CFG_n_OUTI(n,val) \ + out_dword(HWIO_IPA_ROUTER_CACHE_CFG_n_ADDR(n),val) +#define HWIO_IPA_ROUTER_CACHE_CFG_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_ROUTER_CACHE_CFG_n_ADDR(n),mask,val,HWIO_IPA_ROUTER_CACHE_CFG_n_INI(n)) +#define HWIO_IPA_ROUTER_CACHE_CFG_n_ROUTER_CACHE_MSK_METADATA_BMSK 0x40 +#define HWIO_IPA_ROUTER_CACHE_CFG_n_ROUTER_CACHE_MSK_METADATA_SHFT 0x6 +#define HWIO_IPA_ROUTER_CACHE_CFG_n_ROUTER_CACHE_MSK_PROTOCOL_BMSK 0x20 +#define HWIO_IPA_ROUTER_CACHE_CFG_n_ROUTER_CACHE_MSK_PROTOCOL_SHFT 0x5 +#define HWIO_IPA_ROUTER_CACHE_CFG_n_ROUTER_CACHE_MSK_DST_PORT_BMSK 0x10 +#define HWIO_IPA_ROUTER_CACHE_CFG_n_ROUTER_CACHE_MSK_DST_PORT_SHFT 0x4 +#define HWIO_IPA_ROUTER_CACHE_CFG_n_ROUTER_CACHE_MSK_SRC_PORT_BMSK 0x8 +#define HWIO_IPA_ROUTER_CACHE_CFG_n_ROUTER_CACHE_MSK_SRC_PORT_SHFT 0x3 +#define HWIO_IPA_ROUTER_CACHE_CFG_n_ROUTER_CACHE_MSK_DST_IP_ADD_BMSK 0x4 +#define HWIO_IPA_ROUTER_CACHE_CFG_n_ROUTER_CACHE_MSK_DST_IP_ADD_SHFT 0x2 +#define HWIO_IPA_ROUTER_CACHE_CFG_n_ROUTER_CACHE_MSK_SRC_IP_ADD_BMSK 0x2 +#define HWIO_IPA_ROUTER_CACHE_CFG_n_ROUTER_CACHE_MSK_SRC_IP_ADD_SHFT 0x1 +#define HWIO_IPA_ROUTER_CACHE_CFG_n_ROUTER_CACHE_MSK_SRC_ID_BMSK 0x1 +#define HWIO_IPA_ROUTER_CACHE_CFG_n_ROUTER_CACHE_MSK_SRC_ID_SHFT 0x0 + +#define HWIO_IPA_ENDP_YELLOW_RED_MARKER_CFG_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00001060 + 0x80 * (n)) +#define HWIO_IPA_ENDP_YELLOW_RED_MARKER_CFG_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00001060 + 0x80 * (n)) +#define HWIO_IPA_ENDP_YELLOW_RED_MARKER_CFG_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00001060 + 0x80 * (n)) +#define HWIO_IPA_ENDP_YELLOW_RED_MARKER_CFG_n_RMSK 0xfc00fc00 +#define HWIO_IPA_ENDP_YELLOW_RED_MARKER_CFG_n_MAXn 35 +#define HWIO_IPA_ENDP_YELLOW_RED_MARKER_CFG_n_ATTR 0x3 +#define HWIO_IPA_ENDP_YELLOW_RED_MARKER_CFG_n_INI(n) \ + in_dword_masked(HWIO_IPA_ENDP_YELLOW_RED_MARKER_CFG_n_ADDR(n), HWIO_IPA_ENDP_YELLOW_RED_MARKER_CFG_n_RMSK) +#define HWIO_IPA_ENDP_YELLOW_RED_MARKER_CFG_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ENDP_YELLOW_RED_MARKER_CFG_n_ADDR(n), mask) +#define HWIO_IPA_ENDP_YELLOW_RED_MARKER_CFG_n_OUTI(n,val) \ + out_dword(HWIO_IPA_ENDP_YELLOW_RED_MARKER_CFG_n_ADDR(n),val) +#define HWIO_IPA_ENDP_YELLOW_RED_MARKER_CFG_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_ENDP_YELLOW_RED_MARKER_CFG_n_ADDR(n),mask,val,HWIO_IPA_ENDP_YELLOW_RED_MARKER_CFG_n_INI(n)) +#define HWIO_IPA_ENDP_YELLOW_RED_MARKER_CFG_n_IPA_RED_MARKER_CFG_BMSK 0xfc000000 +#define HWIO_IPA_ENDP_YELLOW_RED_MARKER_CFG_n_IPA_RED_MARKER_CFG_SHFT 0x1a +#define HWIO_IPA_ENDP_YELLOW_RED_MARKER_CFG_n_IPA_YELLOW_MARKER_CFG_BMSK 0xfc00 +#define HWIO_IPA_ENDP_YELLOW_RED_MARKER_CFG_n_IPA_YELLOW_MARKER_CFG_SHFT 0xa + +#define HWIO_IPA_ENDP_INIT_CTRL_STATUS_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00001064 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_CTRL_STATUS_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00001064 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_CTRL_STATUS_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00001064 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_CTRL_STATUS_n_RMSK 0x3 +#define HWIO_IPA_ENDP_INIT_CTRL_STATUS_n_MAXn 35 +#define HWIO_IPA_ENDP_INIT_CTRL_STATUS_n_ATTR 0x1 +#define HWIO_IPA_ENDP_INIT_CTRL_STATUS_n_INI(n) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_CTRL_STATUS_n_ADDR(n), HWIO_IPA_ENDP_INIT_CTRL_STATUS_n_RMSK) +#define HWIO_IPA_ENDP_INIT_CTRL_STATUS_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_CTRL_STATUS_n_ADDR(n), mask) +#define HWIO_IPA_ENDP_INIT_CTRL_STATUS_n_ENDP_DELAY_STATUS_BMSK 0x2 +#define HWIO_IPA_ENDP_INIT_CTRL_STATUS_n_ENDP_DELAY_STATUS_SHFT 0x1 +#define HWIO_IPA_ENDP_INIT_CTRL_STATUS_n_ENDP_SUSPEND_STATUS_BMSK 0x1 +#define HWIO_IPA_ENDP_INIT_CTRL_STATUS_n_ENDP_SUSPEND_STATUS_SHFT 0x0 + +#define HWIO_IPA_ENDP_INIT_PROD_CFG_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00001068 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_PROD_CFG_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00001068 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_PROD_CFG_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00001068 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_PROD_CFG_n_RMSK 0x1 +#define HWIO_IPA_ENDP_INIT_PROD_CFG_n_MAXn 35 +#define HWIO_IPA_ENDP_INIT_PROD_CFG_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_PROD_CFG_n_INI(n) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_PROD_CFG_n_ADDR(n), HWIO_IPA_ENDP_INIT_PROD_CFG_n_RMSK) +#define HWIO_IPA_ENDP_INIT_PROD_CFG_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_PROD_CFG_n_ADDR(n), mask) +#define HWIO_IPA_ENDP_INIT_PROD_CFG_n_OUTI(n,val) \ + out_dword(HWIO_IPA_ENDP_INIT_PROD_CFG_n_ADDR(n),val) +#define HWIO_IPA_ENDP_INIT_PROD_CFG_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_ENDP_INIT_PROD_CFG_n_ADDR(n),mask,val,HWIO_IPA_ENDP_INIT_PROD_CFG_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_PROD_CFG_n_TX_SEL_BMSK 0x1 +#define HWIO_IPA_ENDP_INIT_PROD_CFG_n_TX_SEL_SHFT 0x0 + +#define HWIO_IPA_ENDP_INIT_ULSO_CFG_n_ADDR(n) (IPA_CFG_REG_BASE + 0x0000106c + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_ULSO_CFG_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x0000106c + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_ULSO_CFG_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x0000106c + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_ULSO_CFG_n_RMSK 0x3 +#define HWIO_IPA_ENDP_INIT_ULSO_CFG_n_MAXn 15 +#define HWIO_IPA_ENDP_INIT_ULSO_CFG_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_ULSO_CFG_n_INI(n) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_ULSO_CFG_n_ADDR(n), HWIO_IPA_ENDP_INIT_ULSO_CFG_n_RMSK) +#define HWIO_IPA_ENDP_INIT_ULSO_CFG_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_ULSO_CFG_n_ADDR(n), mask) +#define HWIO_IPA_ENDP_INIT_ULSO_CFG_n_OUTI(n,val) \ + out_dword(HWIO_IPA_ENDP_INIT_ULSO_CFG_n_ADDR(n),val) +#define HWIO_IPA_ENDP_INIT_ULSO_CFG_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_ENDP_INIT_ULSO_CFG_n_ADDR(n),mask,val,HWIO_IPA_ENDP_INIT_ULSO_CFG_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_ULSO_CFG_n_IPV4_ID_MIN_MAX_VAL_INDEX_BMSK 0x3 +#define HWIO_IPA_ENDP_INIT_ULSO_CFG_n_IPV4_ID_MIN_MAX_VAL_INDEX_SHFT 0x0 + +#define HWIO_IPA_ENDP_INIT_UCP_CFG_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00001074 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_UCP_CFG_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00001074 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_UCP_CFG_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00001074 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_UCP_CFG_n_RMSK 0x1ffff +#define HWIO_IPA_ENDP_INIT_UCP_CFG_n_MAXn 15 +#define HWIO_IPA_ENDP_INIT_UCP_CFG_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_UCP_CFG_n_INI(n) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_UCP_CFG_n_ADDR(n), HWIO_IPA_ENDP_INIT_UCP_CFG_n_RMSK) +#define HWIO_IPA_ENDP_INIT_UCP_CFG_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_UCP_CFG_n_ADDR(n), mask) +#define HWIO_IPA_ENDP_INIT_UCP_CFG_n_OUTI(n,val) \ + out_dword(HWIO_IPA_ENDP_INIT_UCP_CFG_n_ADDR(n),val) +#define HWIO_IPA_ENDP_INIT_UCP_CFG_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_ENDP_INIT_UCP_CFG_n_ADDR(n),mask,val,HWIO_IPA_ENDP_INIT_UCP_CFG_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_UCP_CFG_n_UCP_TRIGGER_EN_BMSK 0x10000 +#define HWIO_IPA_ENDP_INIT_UCP_CFG_n_UCP_TRIGGER_EN_SHFT 0x10 +#define HWIO_IPA_ENDP_INIT_UCP_CFG_n_UCP_COMMAND_ID_BMSK 0xffff +#define HWIO_IPA_ENDP_INIT_UCP_CFG_n_UCP_COMMAND_ID_SHFT 0x0 + +/*---------------------------------------------------------------------------- + * MODULE: IPA_VMIDMT + *--------------------------------------------------------------------------*/ + +#define IPA_VMIDMT_REG_BASE (IPA_0_IPA_WRAPPER_BASE + 0x00130000) +#define IPA_VMIDMT_REG_BASE_PHYS (IPA_0_IPA_WRAPPER_BASE_PHYS + 0x00130000) +#define IPA_VMIDMT_REG_BASE_OFFS 0x00130000 + +#define HWIO_IPA_VMIDMT_SCR0_ADDR (IPA_VMIDMT_REG_BASE + 0x00000000) +#define HWIO_IPA_VMIDMT_SCR0_PHYS (IPA_VMIDMT_REG_BASE_PHYS + 0x00000000) +#define HWIO_IPA_VMIDMT_SCR0_OFFS (IPA_VMIDMT_REG_BASE_OFFS + 0x00000000) +#define HWIO_IPA_VMIDMT_SCR0_RMSK 0x3ff707f5 +#define HWIO_IPA_VMIDMT_SCR0_ATTR 0x3 +#define HWIO_IPA_VMIDMT_SCR0_IN \ + in_dword_masked(HWIO_IPA_VMIDMT_SCR0_ADDR, HWIO_IPA_VMIDMT_SCR0_RMSK) +#define HWIO_IPA_VMIDMT_SCR0_INM(m) \ + in_dword_masked(HWIO_IPA_VMIDMT_SCR0_ADDR, m) +#define HWIO_IPA_VMIDMT_SCR0_OUT(v) \ + out_dword(HWIO_IPA_VMIDMT_SCR0_ADDR,v) +#define HWIO_IPA_VMIDMT_SCR0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_VMIDMT_SCR0_ADDR,m,v,HWIO_IPA_VMIDMT_SCR0_IN) +#define HWIO_IPA_VMIDMT_SCR0_NSCFG_BMSK 0x30000000 +#define HWIO_IPA_VMIDMT_SCR0_NSCFG_SHFT 0x1c +#define HWIO_IPA_VMIDMT_SCR0_WACFG_BMSK 0xc000000 +#define HWIO_IPA_VMIDMT_SCR0_WACFG_SHFT 0x1a +#define HWIO_IPA_VMIDMT_SCR0_RACFG_BMSK 0x3000000 +#define HWIO_IPA_VMIDMT_SCR0_RACFG_SHFT 0x18 +#define HWIO_IPA_VMIDMT_SCR0_SHCFG_BMSK 0xc00000 +#define HWIO_IPA_VMIDMT_SCR0_SHCFG_SHFT 0x16 +#define HWIO_IPA_VMIDMT_SCR0_SMCFCFG_BMSK 0x200000 +#define HWIO_IPA_VMIDMT_SCR0_SMCFCFG_SHFT 0x15 +#define HWIO_IPA_VMIDMT_SCR0_MTCFG_BMSK 0x100000 +#define HWIO_IPA_VMIDMT_SCR0_MTCFG_SHFT 0x14 +#define HWIO_IPA_VMIDMT_SCR0_MEMATTR_BMSK 0x70000 +#define HWIO_IPA_VMIDMT_SCR0_MEMATTR_SHFT 0x10 +#define HWIO_IPA_VMIDMT_SCR0_USFCFG_BMSK 0x400 +#define HWIO_IPA_VMIDMT_SCR0_USFCFG_SHFT 0xa +#define HWIO_IPA_VMIDMT_SCR0_GSE_BMSK 0x200 +#define HWIO_IPA_VMIDMT_SCR0_GSE_SHFT 0x9 +#define HWIO_IPA_VMIDMT_SCR0_STALLD_BMSK 0x100 +#define HWIO_IPA_VMIDMT_SCR0_STALLD_SHFT 0x8 +#define HWIO_IPA_VMIDMT_SCR0_TRANSIENTCFG_BMSK 0xc0 +#define HWIO_IPA_VMIDMT_SCR0_TRANSIENTCFG_SHFT 0x6 +#define HWIO_IPA_VMIDMT_SCR0_GCFGFIE_BMSK 0x20 +#define HWIO_IPA_VMIDMT_SCR0_GCFGFIE_SHFT 0x5 +#define HWIO_IPA_VMIDMT_SCR0_GCFGERE_BMSK 0x10 +#define HWIO_IPA_VMIDMT_SCR0_GCFGERE_SHFT 0x4 +#define HWIO_IPA_VMIDMT_SCR0_GFIE_BMSK 0x4 +#define HWIO_IPA_VMIDMT_SCR0_GFIE_SHFT 0x2 +#define HWIO_IPA_VMIDMT_SCR0_CLIENTPD_BMSK 0x1 +#define HWIO_IPA_VMIDMT_SCR0_CLIENTPD_SHFT 0x0 + +#define HWIO_IPA_VMIDMT_SCR1_ADDR (IPA_VMIDMT_REG_BASE + 0x00000004) +#define HWIO_IPA_VMIDMT_SCR1_PHYS (IPA_VMIDMT_REG_BASE_PHYS + 0x00000004) +#define HWIO_IPA_VMIDMT_SCR1_OFFS (IPA_VMIDMT_REG_BASE_OFFS + 0x00000004) +#define HWIO_IPA_VMIDMT_SCR1_RMSK 0x1003f00 +#define HWIO_IPA_VMIDMT_SCR1_ATTR 0x3 +#define HWIO_IPA_VMIDMT_SCR1_IN \ + in_dword_masked(HWIO_IPA_VMIDMT_SCR1_ADDR, HWIO_IPA_VMIDMT_SCR1_RMSK) +#define HWIO_IPA_VMIDMT_SCR1_INM(m) \ + in_dword_masked(HWIO_IPA_VMIDMT_SCR1_ADDR, m) +#define HWIO_IPA_VMIDMT_SCR1_OUT(v) \ + out_dword(HWIO_IPA_VMIDMT_SCR1_ADDR,v) +#define HWIO_IPA_VMIDMT_SCR1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_VMIDMT_SCR1_ADDR,m,v,HWIO_IPA_VMIDMT_SCR1_IN) +#define HWIO_IPA_VMIDMT_SCR1_GASRAE_BMSK 0x1000000 +#define HWIO_IPA_VMIDMT_SCR1_GASRAE_SHFT 0x18 +#define HWIO_IPA_VMIDMT_SCR1_NSNUMSMRGO_BMSK 0x3f00 +#define HWIO_IPA_VMIDMT_SCR1_NSNUMSMRGO_SHFT 0x8 + +#define HWIO_IPA_VMIDMT_SCR2_ADDR (IPA_VMIDMT_REG_BASE + 0x00000008) +#define HWIO_IPA_VMIDMT_SCR2_PHYS (IPA_VMIDMT_REG_BASE_PHYS + 0x00000008) +#define HWIO_IPA_VMIDMT_SCR2_OFFS (IPA_VMIDMT_REG_BASE_OFFS + 0x00000008) +#define HWIO_IPA_VMIDMT_SCR2_RMSK 0x1f +#define HWIO_IPA_VMIDMT_SCR2_ATTR 0x3 +#define HWIO_IPA_VMIDMT_SCR2_IN \ + in_dword_masked(HWIO_IPA_VMIDMT_SCR2_ADDR, HWIO_IPA_VMIDMT_SCR2_RMSK) +#define HWIO_IPA_VMIDMT_SCR2_INM(m) \ + in_dword_masked(HWIO_IPA_VMIDMT_SCR2_ADDR, m) +#define HWIO_IPA_VMIDMT_SCR2_OUT(v) \ + out_dword(HWIO_IPA_VMIDMT_SCR2_ADDR,v) +#define HWIO_IPA_VMIDMT_SCR2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_VMIDMT_SCR2_ADDR,m,v,HWIO_IPA_VMIDMT_SCR2_IN) +#define HWIO_IPA_VMIDMT_SCR2_BPVMID_BMSK 0x1f +#define HWIO_IPA_VMIDMT_SCR2_BPVMID_SHFT 0x0 + +#define HWIO_IPA_VMIDMT_SACR_ADDR (IPA_VMIDMT_REG_BASE + 0x00000010) +#define HWIO_IPA_VMIDMT_SACR_PHYS (IPA_VMIDMT_REG_BASE_PHYS + 0x00000010) +#define HWIO_IPA_VMIDMT_SACR_OFFS (IPA_VMIDMT_REG_BASE_OFFS + 0x00000010) +#define HWIO_IPA_VMIDMT_SACR_RMSK 0x70000013 +#define HWIO_IPA_VMIDMT_SACR_ATTR 0x3 +#define HWIO_IPA_VMIDMT_SACR_IN \ + in_dword_masked(HWIO_IPA_VMIDMT_SACR_ADDR, HWIO_IPA_VMIDMT_SACR_RMSK) +#define HWIO_IPA_VMIDMT_SACR_INM(m) \ + in_dword_masked(HWIO_IPA_VMIDMT_SACR_ADDR, m) +#define HWIO_IPA_VMIDMT_SACR_OUT(v) \ + out_dword(HWIO_IPA_VMIDMT_SACR_ADDR,v) +#define HWIO_IPA_VMIDMT_SACR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_VMIDMT_SACR_ADDR,m,v,HWIO_IPA_VMIDMT_SACR_IN) +#define HWIO_IPA_VMIDMT_SACR_BPRCNSH_BMSK 0x40000000 +#define HWIO_IPA_VMIDMT_SACR_BPRCNSH_SHFT 0x1e +#define HWIO_IPA_VMIDMT_SACR_BPRCISH_BMSK 0x20000000 +#define HWIO_IPA_VMIDMT_SACR_BPRCISH_SHFT 0x1d +#define HWIO_IPA_VMIDMT_SACR_BPRCOSH_BMSK 0x10000000 +#define HWIO_IPA_VMIDMT_SACR_BPRCOSH_SHFT 0x1c +#define HWIO_IPA_VMIDMT_SACR_BPREQPRIORITYCFG_BMSK 0x10 +#define HWIO_IPA_VMIDMT_SACR_BPREQPRIORITYCFG_SHFT 0x4 +#define HWIO_IPA_VMIDMT_SACR_BPREQPRIORITY_BMSK 0x3 +#define HWIO_IPA_VMIDMT_SACR_BPREQPRIORITY_SHFT 0x0 + +#define HWIO_IPA_VMIDMT_SIDR0_ADDR (IPA_VMIDMT_REG_BASE + 0x00000020) +#define HWIO_IPA_VMIDMT_SIDR0_PHYS (IPA_VMIDMT_REG_BASE_PHYS + 0x00000020) +#define HWIO_IPA_VMIDMT_SIDR0_OFFS (IPA_VMIDMT_REG_BASE_OFFS + 0x00000020) +#define HWIO_IPA_VMIDMT_SIDR0_RMSK 0x88001eff +#define HWIO_IPA_VMIDMT_SIDR0_ATTR 0x1 +#define HWIO_IPA_VMIDMT_SIDR0_IN \ + in_dword_masked(HWIO_IPA_VMIDMT_SIDR0_ADDR, HWIO_IPA_VMIDMT_SIDR0_RMSK) +#define HWIO_IPA_VMIDMT_SIDR0_INM(m) \ + in_dword_masked(HWIO_IPA_VMIDMT_SIDR0_ADDR, m) +#define HWIO_IPA_VMIDMT_SIDR0_SES_BMSK 0x80000000 +#define HWIO_IPA_VMIDMT_SIDR0_SES_SHFT 0x1f +#define HWIO_IPA_VMIDMT_SIDR0_SMS_BMSK 0x8000000 +#define HWIO_IPA_VMIDMT_SIDR0_SMS_SHFT 0x1b +#define HWIO_IPA_VMIDMT_SIDR0_NUMSIDB_BMSK 0x1e00 +#define HWIO_IPA_VMIDMT_SIDR0_NUMSIDB_SHFT 0x9 +#define HWIO_IPA_VMIDMT_SIDR0_NUMSMRG_BMSK 0xff +#define HWIO_IPA_VMIDMT_SIDR0_NUMSMRG_SHFT 0x0 + +#define HWIO_IPA_VMIDMT_SIDR1_ADDR (IPA_VMIDMT_REG_BASE + 0x00000024) +#define HWIO_IPA_VMIDMT_SIDR1_PHYS (IPA_VMIDMT_REG_BASE_PHYS + 0x00000024) +#define HWIO_IPA_VMIDMT_SIDR1_OFFS (IPA_VMIDMT_REG_BASE_OFFS + 0x00000024) +#define HWIO_IPA_VMIDMT_SIDR1_RMSK 0x9f00 +#define HWIO_IPA_VMIDMT_SIDR1_ATTR 0x1 +#define HWIO_IPA_VMIDMT_SIDR1_IN \ + in_dword_masked(HWIO_IPA_VMIDMT_SIDR1_ADDR, HWIO_IPA_VMIDMT_SIDR1_RMSK) +#define HWIO_IPA_VMIDMT_SIDR1_INM(m) \ + in_dword_masked(HWIO_IPA_VMIDMT_SIDR1_ADDR, m) +#define HWIO_IPA_VMIDMT_SIDR1_SMCD_BMSK 0x8000 +#define HWIO_IPA_VMIDMT_SIDR1_SMCD_SHFT 0xf +#define HWIO_IPA_VMIDMT_SIDR1_SSDTP_BMSK 0x1000 +#define HWIO_IPA_VMIDMT_SIDR1_SSDTP_SHFT 0xc +#define HWIO_IPA_VMIDMT_SIDR1_NUMSSDNDX_BMSK 0xf00 +#define HWIO_IPA_VMIDMT_SIDR1_NUMSSDNDX_SHFT 0x8 + +#define HWIO_IPA_VMIDMT_SIDR2_ADDR (IPA_VMIDMT_REG_BASE + 0x00000028) +#define HWIO_IPA_VMIDMT_SIDR2_PHYS (IPA_VMIDMT_REG_BASE_PHYS + 0x00000028) +#define HWIO_IPA_VMIDMT_SIDR2_OFFS (IPA_VMIDMT_REG_BASE_OFFS + 0x00000028) +#define HWIO_IPA_VMIDMT_SIDR2_RMSK 0xff +#define HWIO_IPA_VMIDMT_SIDR2_ATTR 0x1 +#define HWIO_IPA_VMIDMT_SIDR2_IN \ + in_dword_masked(HWIO_IPA_VMIDMT_SIDR2_ADDR, HWIO_IPA_VMIDMT_SIDR2_RMSK) +#define HWIO_IPA_VMIDMT_SIDR2_INM(m) \ + in_dword_masked(HWIO_IPA_VMIDMT_SIDR2_ADDR, m) +#define HWIO_IPA_VMIDMT_SIDR2_OAS_BMSK 0xf0 +#define HWIO_IPA_VMIDMT_SIDR2_OAS_SHFT 0x4 +#define HWIO_IPA_VMIDMT_SIDR2_IAS_BMSK 0xf +#define HWIO_IPA_VMIDMT_SIDR2_IAS_SHFT 0x0 + +#define HWIO_IPA_VMIDMT_SIDR4_ADDR (IPA_VMIDMT_REG_BASE + 0x00000030) +#define HWIO_IPA_VMIDMT_SIDR4_PHYS (IPA_VMIDMT_REG_BASE_PHYS + 0x00000030) +#define HWIO_IPA_VMIDMT_SIDR4_OFFS (IPA_VMIDMT_REG_BASE_OFFS + 0x00000030) +#define HWIO_IPA_VMIDMT_SIDR4_RMSK 0xffffffff +#define HWIO_IPA_VMIDMT_SIDR4_ATTR 0x1 +#define HWIO_IPA_VMIDMT_SIDR4_IN \ + in_dword_masked(HWIO_IPA_VMIDMT_SIDR4_ADDR, HWIO_IPA_VMIDMT_SIDR4_RMSK) +#define HWIO_IPA_VMIDMT_SIDR4_INM(m) \ + in_dword_masked(HWIO_IPA_VMIDMT_SIDR4_ADDR, m) +#define HWIO_IPA_VMIDMT_SIDR4_MAJOR_BMSK 0xf0000000 +#define HWIO_IPA_VMIDMT_SIDR4_MAJOR_SHFT 0x1c +#define HWIO_IPA_VMIDMT_SIDR4_MINOR_BMSK 0xfff0000 +#define HWIO_IPA_VMIDMT_SIDR4_MINOR_SHFT 0x10 +#define HWIO_IPA_VMIDMT_SIDR4_STEP_BMSK 0xffff +#define HWIO_IPA_VMIDMT_SIDR4_STEP_SHFT 0x0 + +#define HWIO_IPA_VMIDMT_SIDR5_ADDR (IPA_VMIDMT_REG_BASE + 0x00000034) +#define HWIO_IPA_VMIDMT_SIDR5_PHYS (IPA_VMIDMT_REG_BASE_PHYS + 0x00000034) +#define HWIO_IPA_VMIDMT_SIDR5_OFFS (IPA_VMIDMT_REG_BASE_OFFS + 0x00000034) +#define HWIO_IPA_VMIDMT_SIDR5_RMSK 0xff03ff +#define HWIO_IPA_VMIDMT_SIDR5_ATTR 0x1 +#define HWIO_IPA_VMIDMT_SIDR5_IN \ + in_dword_masked(HWIO_IPA_VMIDMT_SIDR5_ADDR, HWIO_IPA_VMIDMT_SIDR5_RMSK) +#define HWIO_IPA_VMIDMT_SIDR5_INM(m) \ + in_dword_masked(HWIO_IPA_VMIDMT_SIDR5_ADDR, m) +#define HWIO_IPA_VMIDMT_SIDR5_NUMMSDRB_BMSK 0xff0000 +#define HWIO_IPA_VMIDMT_SIDR5_NUMMSDRB_SHFT 0x10 +#define HWIO_IPA_VMIDMT_SIDR5_MSAE_BMSK 0x200 +#define HWIO_IPA_VMIDMT_SIDR5_MSAE_SHFT 0x9 +#define HWIO_IPA_VMIDMT_SIDR5_QRIBE_BMSK 0x100 +#define HWIO_IPA_VMIDMT_SIDR5_QRIBE_SHFT 0x8 +#define HWIO_IPA_VMIDMT_SIDR5_NVMID_BMSK 0xff +#define HWIO_IPA_VMIDMT_SIDR5_NVMID_SHFT 0x0 + +#define HWIO_IPA_VMIDMT_SIDR7_ADDR (IPA_VMIDMT_REG_BASE + 0x0000003c) +#define HWIO_IPA_VMIDMT_SIDR7_PHYS (IPA_VMIDMT_REG_BASE_PHYS + 0x0000003c) +#define HWIO_IPA_VMIDMT_SIDR7_OFFS (IPA_VMIDMT_REG_BASE_OFFS + 0x0000003c) +#define HWIO_IPA_VMIDMT_SIDR7_RMSK 0xff +#define HWIO_IPA_VMIDMT_SIDR7_ATTR 0x1 +#define HWIO_IPA_VMIDMT_SIDR7_IN \ + in_dword_masked(HWIO_IPA_VMIDMT_SIDR7_ADDR, HWIO_IPA_VMIDMT_SIDR7_RMSK) +#define HWIO_IPA_VMIDMT_SIDR7_INM(m) \ + in_dword_masked(HWIO_IPA_VMIDMT_SIDR7_ADDR, m) +#define HWIO_IPA_VMIDMT_SIDR7_MAJOR_BMSK 0xf0 +#define HWIO_IPA_VMIDMT_SIDR7_MAJOR_SHFT 0x4 +#define HWIO_IPA_VMIDMT_SIDR7_MINOR_BMSK 0xf +#define HWIO_IPA_VMIDMT_SIDR7_MINOR_SHFT 0x0 + +#define HWIO_IPA_VMIDMT_SGFAR0_ADDR (IPA_VMIDMT_REG_BASE + 0x00000040) +#define HWIO_IPA_VMIDMT_SGFAR0_PHYS (IPA_VMIDMT_REG_BASE_PHYS + 0x00000040) +#define HWIO_IPA_VMIDMT_SGFAR0_OFFS (IPA_VMIDMT_REG_BASE_OFFS + 0x00000040) +#define HWIO_IPA_VMIDMT_SGFAR0_RMSK 0xffffffff +#define HWIO_IPA_VMIDMT_SGFAR0_ATTR 0x1 +#define HWIO_IPA_VMIDMT_SGFAR0_IN \ + in_dword_masked(HWIO_IPA_VMIDMT_SGFAR0_ADDR, HWIO_IPA_VMIDMT_SGFAR0_RMSK) +#define HWIO_IPA_VMIDMT_SGFAR0_INM(m) \ + in_dword_masked(HWIO_IPA_VMIDMT_SGFAR0_ADDR, m) +#define HWIO_IPA_VMIDMT_SGFAR0_SGFEA0_BMSK 0xffffffff +#define HWIO_IPA_VMIDMT_SGFAR0_SGFEA0_SHFT 0x0 + +#define HWIO_IPA_VMIDMT_SGFAR1_ADDR (IPA_VMIDMT_REG_BASE + 0x00000044) +#define HWIO_IPA_VMIDMT_SGFAR1_PHYS (IPA_VMIDMT_REG_BASE_PHYS + 0x00000044) +#define HWIO_IPA_VMIDMT_SGFAR1_OFFS (IPA_VMIDMT_REG_BASE_OFFS + 0x00000044) +#define HWIO_IPA_VMIDMT_SGFAR1_RMSK 0xff +#define HWIO_IPA_VMIDMT_SGFAR1_ATTR 0x1 +#define HWIO_IPA_VMIDMT_SGFAR1_IN \ + in_dword_masked(HWIO_IPA_VMIDMT_SGFAR1_ADDR, HWIO_IPA_VMIDMT_SGFAR1_RMSK) +#define HWIO_IPA_VMIDMT_SGFAR1_INM(m) \ + in_dword_masked(HWIO_IPA_VMIDMT_SGFAR1_ADDR, m) +#define HWIO_IPA_VMIDMT_SGFAR1_SGFEA1_BMSK 0xff +#define HWIO_IPA_VMIDMT_SGFAR1_SGFEA1_SHFT 0x0 + +#define HWIO_IPA_VMIDMT_SGFSR_ADDR (IPA_VMIDMT_REG_BASE + 0x00000048) +#define HWIO_IPA_VMIDMT_SGFSR_PHYS (IPA_VMIDMT_REG_BASE_PHYS + 0x00000048) +#define HWIO_IPA_VMIDMT_SGFSR_OFFS (IPA_VMIDMT_REG_BASE_OFFS + 0x00000048) +#define HWIO_IPA_VMIDMT_SGFSR_RMSK 0xc0000026 +#define HWIO_IPA_VMIDMT_SGFSR_ATTR 0x3 +#define HWIO_IPA_VMIDMT_SGFSR_IN \ + in_dword_masked(HWIO_IPA_VMIDMT_SGFSR_ADDR, HWIO_IPA_VMIDMT_SGFSR_RMSK) +#define HWIO_IPA_VMIDMT_SGFSR_INM(m) \ + in_dword_masked(HWIO_IPA_VMIDMT_SGFSR_ADDR, m) +#define HWIO_IPA_VMIDMT_SGFSR_OUT(v) \ + out_dword(HWIO_IPA_VMIDMT_SGFSR_ADDR,v) +#define HWIO_IPA_VMIDMT_SGFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_VMIDMT_SGFSR_ADDR,m,v,HWIO_IPA_VMIDMT_SGFSR_IN) +#define HWIO_IPA_VMIDMT_SGFSR_MULTI_CLIENT_BMSK 0x80000000 +#define HWIO_IPA_VMIDMT_SGFSR_MULTI_CLIENT_SHFT 0x1f +#define HWIO_IPA_VMIDMT_SGFSR_MULTI_CFG_BMSK 0x40000000 +#define HWIO_IPA_VMIDMT_SGFSR_MULTI_CFG_SHFT 0x1e +#define HWIO_IPA_VMIDMT_SGFSR_CAF_BMSK 0x20 +#define HWIO_IPA_VMIDMT_SGFSR_CAF_SHFT 0x5 +#define HWIO_IPA_VMIDMT_SGFSR_SMCF_BMSK 0x4 +#define HWIO_IPA_VMIDMT_SGFSR_SMCF_SHFT 0x2 +#define HWIO_IPA_VMIDMT_SGFSR_USF_BMSK 0x2 +#define HWIO_IPA_VMIDMT_SGFSR_USF_SHFT 0x1 + +#define HWIO_IPA_VMIDMT_SGFSRRESTORE_ADDR (IPA_VMIDMT_REG_BASE + 0x0000004c) +#define HWIO_IPA_VMIDMT_SGFSRRESTORE_PHYS (IPA_VMIDMT_REG_BASE_PHYS + 0x0000004c) +#define HWIO_IPA_VMIDMT_SGFSRRESTORE_OFFS (IPA_VMIDMT_REG_BASE_OFFS + 0x0000004c) +#define HWIO_IPA_VMIDMT_SGFSRRESTORE_RMSK 0xc0000026 +#define HWIO_IPA_VMIDMT_SGFSRRESTORE_ATTR 0x3 +#define HWIO_IPA_VMIDMT_SGFSRRESTORE_IN \ + in_dword_masked(HWIO_IPA_VMIDMT_SGFSRRESTORE_ADDR, HWIO_IPA_VMIDMT_SGFSRRESTORE_RMSK) +#define HWIO_IPA_VMIDMT_SGFSRRESTORE_INM(m) \ + in_dword_masked(HWIO_IPA_VMIDMT_SGFSRRESTORE_ADDR, m) +#define HWIO_IPA_VMIDMT_SGFSRRESTORE_OUT(v) \ + out_dword(HWIO_IPA_VMIDMT_SGFSRRESTORE_ADDR,v) +#define HWIO_IPA_VMIDMT_SGFSRRESTORE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_VMIDMT_SGFSRRESTORE_ADDR,m,v,HWIO_IPA_VMIDMT_SGFSRRESTORE_IN) +#define HWIO_IPA_VMIDMT_SGFSRRESTORE_MULTI_CLIENT_BMSK 0x80000000 +#define HWIO_IPA_VMIDMT_SGFSRRESTORE_MULTI_CLIENT_SHFT 0x1f +#define HWIO_IPA_VMIDMT_SGFSRRESTORE_MULTI_CFG_BMSK 0x40000000 +#define HWIO_IPA_VMIDMT_SGFSRRESTORE_MULTI_CFG_SHFT 0x1e +#define HWIO_IPA_VMIDMT_SGFSRRESTORE_CAF_BMSK 0x20 +#define HWIO_IPA_VMIDMT_SGFSRRESTORE_CAF_SHFT 0x5 +#define HWIO_IPA_VMIDMT_SGFSRRESTORE_SMCF_BMSK 0x4 +#define HWIO_IPA_VMIDMT_SGFSRRESTORE_SMCF_SHFT 0x2 +#define HWIO_IPA_VMIDMT_SGFSRRESTORE_USF_BMSK 0x2 +#define HWIO_IPA_VMIDMT_SGFSRRESTORE_USF_SHFT 0x1 + +#define HWIO_IPA_VMIDMT_SGFSYNDR0_ADDR (IPA_VMIDMT_REG_BASE + 0x00000050) +#define HWIO_IPA_VMIDMT_SGFSYNDR0_PHYS (IPA_VMIDMT_REG_BASE_PHYS + 0x00000050) +#define HWIO_IPA_VMIDMT_SGFSYNDR0_OFFS (IPA_VMIDMT_REG_BASE_OFFS + 0x00000050) +#define HWIO_IPA_VMIDMT_SGFSYNDR0_RMSK 0x132 +#define HWIO_IPA_VMIDMT_SGFSYNDR0_ATTR 0x1 +#define HWIO_IPA_VMIDMT_SGFSYNDR0_IN \ + in_dword_masked(HWIO_IPA_VMIDMT_SGFSYNDR0_ADDR, HWIO_IPA_VMIDMT_SGFSYNDR0_RMSK) +#define HWIO_IPA_VMIDMT_SGFSYNDR0_INM(m) \ + in_dword_masked(HWIO_IPA_VMIDMT_SGFSYNDR0_ADDR, m) +#define HWIO_IPA_VMIDMT_SGFSYNDR0_MSSSELFAUTH_BMSK 0x100 +#define HWIO_IPA_VMIDMT_SGFSYNDR0_MSSSELFAUTH_SHFT 0x8 +#define HWIO_IPA_VMIDMT_SGFSYNDR0_NSATTR_BMSK 0x20 +#define HWIO_IPA_VMIDMT_SGFSYNDR0_NSATTR_SHFT 0x5 +#define HWIO_IPA_VMIDMT_SGFSYNDR0_NSSTATE_BMSK 0x10 +#define HWIO_IPA_VMIDMT_SGFSYNDR0_NSSTATE_SHFT 0x4 +#define HWIO_IPA_VMIDMT_SGFSYNDR0_WNR_BMSK 0x2 +#define HWIO_IPA_VMIDMT_SGFSYNDR0_WNR_SHFT 0x1 + +#define HWIO_IPA_VMIDMT_SGFSYNDR1_ADDR (IPA_VMIDMT_REG_BASE + 0x00000054) +#define HWIO_IPA_VMIDMT_SGFSYNDR1_PHYS (IPA_VMIDMT_REG_BASE_PHYS + 0x00000054) +#define HWIO_IPA_VMIDMT_SGFSYNDR1_OFFS (IPA_VMIDMT_REG_BASE_OFFS + 0x00000054) +#define HWIO_IPA_VMIDMT_SGFSYNDR1_RMSK 0x7fff00ff +#define HWIO_IPA_VMIDMT_SGFSYNDR1_ATTR 0x1 +#define HWIO_IPA_VMIDMT_SGFSYNDR1_IN \ + in_dword_masked(HWIO_IPA_VMIDMT_SGFSYNDR1_ADDR, HWIO_IPA_VMIDMT_SGFSYNDR1_RMSK) +#define HWIO_IPA_VMIDMT_SGFSYNDR1_INM(m) \ + in_dword_masked(HWIO_IPA_VMIDMT_SGFSYNDR1_ADDR, m) +#define HWIO_IPA_VMIDMT_SGFSYNDR1_MSDINDEX_BMSK 0x7f000000 +#define HWIO_IPA_VMIDMT_SGFSYNDR1_MSDINDEX_SHFT 0x18 +#define HWIO_IPA_VMIDMT_SGFSYNDR1_SSDINDEX_BMSK 0xff0000 +#define HWIO_IPA_VMIDMT_SGFSYNDR1_SSDINDEX_SHFT 0x10 +#define HWIO_IPA_VMIDMT_SGFSYNDR1_STREAMINDEX_BMSK 0xff +#define HWIO_IPA_VMIDMT_SGFSYNDR1_STREAMINDEX_SHFT 0x0 + +#define HWIO_IPA_VMIDMT_SGFSYNDR2_ADDR (IPA_VMIDMT_REG_BASE + 0x00000058) +#define HWIO_IPA_VMIDMT_SGFSYNDR2_PHYS (IPA_VMIDMT_REG_BASE_PHYS + 0x00000058) +#define HWIO_IPA_VMIDMT_SGFSYNDR2_OFFS (IPA_VMIDMT_REG_BASE_OFFS + 0x00000058) +#define HWIO_IPA_VMIDMT_SGFSYNDR2_RMSK 0x1f1fffff +#define HWIO_IPA_VMIDMT_SGFSYNDR2_ATTR 0x1 +#define HWIO_IPA_VMIDMT_SGFSYNDR2_IN \ + in_dword_masked(HWIO_IPA_VMIDMT_SGFSYNDR2_ADDR, HWIO_IPA_VMIDMT_SGFSYNDR2_RMSK) +#define HWIO_IPA_VMIDMT_SGFSYNDR2_INM(m) \ + in_dword_masked(HWIO_IPA_VMIDMT_SGFSYNDR2_ADDR, m) +#define HWIO_IPA_VMIDMT_SGFSYNDR2_ATID_BMSK 0x1f000000 +#define HWIO_IPA_VMIDMT_SGFSYNDR2_ATID_SHFT 0x18 +#define HWIO_IPA_VMIDMT_SGFSYNDR2_AVMID_BMSK 0x1f0000 +#define HWIO_IPA_VMIDMT_SGFSYNDR2_AVMID_SHFT 0x10 +#define HWIO_IPA_VMIDMT_SGFSYNDR2_ABID_BMSK 0xe000 +#define HWIO_IPA_VMIDMT_SGFSYNDR2_ABID_SHFT 0xd +#define HWIO_IPA_VMIDMT_SGFSYNDR2_APID_BMSK 0x1f00 +#define HWIO_IPA_VMIDMT_SGFSYNDR2_APID_SHFT 0x8 +#define HWIO_IPA_VMIDMT_SGFSYNDR2_AMID_BMSK 0xff +#define HWIO_IPA_VMIDMT_SGFSYNDR2_AMID_SHFT 0x0 + +#define HWIO_IPA_VMIDMT_VMIDMTSCR0_ADDR (IPA_VMIDMT_REG_BASE + 0x00000090) +#define HWIO_IPA_VMIDMT_VMIDMTSCR0_PHYS (IPA_VMIDMT_REG_BASE_PHYS + 0x00000090) +#define HWIO_IPA_VMIDMT_VMIDMTSCR0_OFFS (IPA_VMIDMT_REG_BASE_OFFS + 0x00000090) +#define HWIO_IPA_VMIDMT_VMIDMTSCR0_RMSK 0x1 +#define HWIO_IPA_VMIDMT_VMIDMTSCR0_ATTR 0x3 +#define HWIO_IPA_VMIDMT_VMIDMTSCR0_IN \ + in_dword_masked(HWIO_IPA_VMIDMT_VMIDMTSCR0_ADDR, HWIO_IPA_VMIDMT_VMIDMTSCR0_RMSK) +#define HWIO_IPA_VMIDMT_VMIDMTSCR0_INM(m) \ + in_dword_masked(HWIO_IPA_VMIDMT_VMIDMTSCR0_ADDR, m) +#define HWIO_IPA_VMIDMT_VMIDMTSCR0_OUT(v) \ + out_dword(HWIO_IPA_VMIDMT_VMIDMTSCR0_ADDR,v) +#define HWIO_IPA_VMIDMT_VMIDMTSCR0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_VMIDMT_VMIDMTSCR0_ADDR,m,v,HWIO_IPA_VMIDMT_VMIDMTSCR0_IN) +#define HWIO_IPA_VMIDMT_VMIDMTSCR0_CLKONOFFE_BMSK 0x1 +#define HWIO_IPA_VMIDMT_VMIDMTSCR0_CLKONOFFE_SHFT 0x0 + +#define HWIO_IPA_VMIDMT_CR0_ADDR (IPA_VMIDMT_REG_BASE + 0x00000000) +#define HWIO_IPA_VMIDMT_CR0_PHYS (IPA_VMIDMT_REG_BASE_PHYS + 0x00000000) +#define HWIO_IPA_VMIDMT_CR0_OFFS (IPA_VMIDMT_REG_BASE_OFFS + 0x00000000) +#define HWIO_IPA_VMIDMT_CR0_RMSK 0xff70ff5 +#define HWIO_IPA_VMIDMT_CR0_ATTR 0x3 +#define HWIO_IPA_VMIDMT_CR0_IN \ + in_dword_masked(HWIO_IPA_VMIDMT_CR0_ADDR, HWIO_IPA_VMIDMT_CR0_RMSK) +#define HWIO_IPA_VMIDMT_CR0_INM(m) \ + in_dword_masked(HWIO_IPA_VMIDMT_CR0_ADDR, m) +#define HWIO_IPA_VMIDMT_CR0_OUT(v) \ + out_dword(HWIO_IPA_VMIDMT_CR0_ADDR,v) +#define HWIO_IPA_VMIDMT_CR0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_VMIDMT_CR0_ADDR,m,v,HWIO_IPA_VMIDMT_CR0_IN) +#define HWIO_IPA_VMIDMT_CR0_WACFG_BMSK 0xc000000 +#define HWIO_IPA_VMIDMT_CR0_WACFG_SHFT 0x1a +#define HWIO_IPA_VMIDMT_CR0_RACFG_BMSK 0x3000000 +#define HWIO_IPA_VMIDMT_CR0_RACFG_SHFT 0x18 +#define HWIO_IPA_VMIDMT_CR0_SHCFG_BMSK 0xc00000 +#define HWIO_IPA_VMIDMT_CR0_SHCFG_SHFT 0x16 +#define HWIO_IPA_VMIDMT_CR0_SMCFCFG_BMSK 0x200000 +#define HWIO_IPA_VMIDMT_CR0_SMCFCFG_SHFT 0x15 +#define HWIO_IPA_VMIDMT_CR0_MTCFG_BMSK 0x100000 +#define HWIO_IPA_VMIDMT_CR0_MTCFG_SHFT 0x14 +#define HWIO_IPA_VMIDMT_CR0_MEMATTR_BMSK 0x70000 +#define HWIO_IPA_VMIDMT_CR0_MEMATTR_SHFT 0x10 +#define HWIO_IPA_VMIDMT_CR0_VMIDPNE_BMSK 0x800 +#define HWIO_IPA_VMIDMT_CR0_VMIDPNE_SHFT 0xb +#define HWIO_IPA_VMIDMT_CR0_USFCFG_BMSK 0x400 +#define HWIO_IPA_VMIDMT_CR0_USFCFG_SHFT 0xa +#define HWIO_IPA_VMIDMT_CR0_GSE_BMSK 0x200 +#define HWIO_IPA_VMIDMT_CR0_GSE_SHFT 0x9 +#define HWIO_IPA_VMIDMT_CR0_STALLD_BMSK 0x100 +#define HWIO_IPA_VMIDMT_CR0_STALLD_SHFT 0x8 +#define HWIO_IPA_VMIDMT_CR0_TRANSIENTCFG_BMSK 0xc0 +#define HWIO_IPA_VMIDMT_CR0_TRANSIENTCFG_SHFT 0x6 +#define HWIO_IPA_VMIDMT_CR0_GCFGFIE_BMSK 0x20 +#define HWIO_IPA_VMIDMT_CR0_GCFGFIE_SHFT 0x5 +#define HWIO_IPA_VMIDMT_CR0_GCFGERE_BMSK 0x10 +#define HWIO_IPA_VMIDMT_CR0_GCFGERE_SHFT 0x4 +#define HWIO_IPA_VMIDMT_CR0_GFIE_BMSK 0x4 +#define HWIO_IPA_VMIDMT_CR0_GFIE_SHFT 0x2 +#define HWIO_IPA_VMIDMT_CR0_CLIENTPD_BMSK 0x1 +#define HWIO_IPA_VMIDMT_CR0_CLIENTPD_SHFT 0x0 + +#define HWIO_IPA_VMIDMT_CR2_ADDR (IPA_VMIDMT_REG_BASE + 0x00000008) +#define HWIO_IPA_VMIDMT_CR2_PHYS (IPA_VMIDMT_REG_BASE_PHYS + 0x00000008) +#define HWIO_IPA_VMIDMT_CR2_OFFS (IPA_VMIDMT_REG_BASE_OFFS + 0x00000008) +#define HWIO_IPA_VMIDMT_CR2_RMSK 0x1f +#define HWIO_IPA_VMIDMT_CR2_ATTR 0x3 +#define HWIO_IPA_VMIDMT_CR2_IN \ + in_dword_masked(HWIO_IPA_VMIDMT_CR2_ADDR, HWIO_IPA_VMIDMT_CR2_RMSK) +#define HWIO_IPA_VMIDMT_CR2_INM(m) \ + in_dword_masked(HWIO_IPA_VMIDMT_CR2_ADDR, m) +#define HWIO_IPA_VMIDMT_CR2_OUT(v) \ + out_dword(HWIO_IPA_VMIDMT_CR2_ADDR,v) +#define HWIO_IPA_VMIDMT_CR2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_VMIDMT_CR2_ADDR,m,v,HWIO_IPA_VMIDMT_CR2_IN) +#define HWIO_IPA_VMIDMT_CR2_BPVMID_BMSK 0x1f +#define HWIO_IPA_VMIDMT_CR2_BPVMID_SHFT 0x0 + +#define HWIO_IPA_VMIDMT_ACR_ADDR (IPA_VMIDMT_REG_BASE + 0x00000010) +#define HWIO_IPA_VMIDMT_ACR_PHYS (IPA_VMIDMT_REG_BASE_PHYS + 0x00000010) +#define HWIO_IPA_VMIDMT_ACR_OFFS (IPA_VMIDMT_REG_BASE_OFFS + 0x00000010) +#define HWIO_IPA_VMIDMT_ACR_RMSK 0x70000013 +#define HWIO_IPA_VMIDMT_ACR_ATTR 0x3 +#define HWIO_IPA_VMIDMT_ACR_IN \ + in_dword_masked(HWIO_IPA_VMIDMT_ACR_ADDR, HWIO_IPA_VMIDMT_ACR_RMSK) +#define HWIO_IPA_VMIDMT_ACR_INM(m) \ + in_dword_masked(HWIO_IPA_VMIDMT_ACR_ADDR, m) +#define HWIO_IPA_VMIDMT_ACR_OUT(v) \ + out_dword(HWIO_IPA_VMIDMT_ACR_ADDR,v) +#define HWIO_IPA_VMIDMT_ACR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_VMIDMT_ACR_ADDR,m,v,HWIO_IPA_VMIDMT_ACR_IN) +#define HWIO_IPA_VMIDMT_ACR_BPRCNSH_BMSK 0x40000000 +#define HWIO_IPA_VMIDMT_ACR_BPRCNSH_SHFT 0x1e +#define HWIO_IPA_VMIDMT_ACR_BPRCISH_BMSK 0x20000000 +#define HWIO_IPA_VMIDMT_ACR_BPRCISH_SHFT 0x1d +#define HWIO_IPA_VMIDMT_ACR_BPRCOSH_BMSK 0x10000000 +#define HWIO_IPA_VMIDMT_ACR_BPRCOSH_SHFT 0x1c +#define HWIO_IPA_VMIDMT_ACR_BPREQPRIORITYCFG_BMSK 0x10 +#define HWIO_IPA_VMIDMT_ACR_BPREQPRIORITYCFG_SHFT 0x4 +#define HWIO_IPA_VMIDMT_ACR_BPREQPRIORITY_BMSK 0x3 +#define HWIO_IPA_VMIDMT_ACR_BPREQPRIORITY_SHFT 0x0 + +#define HWIO_IPA_VMIDMT_IDR0_ADDR (IPA_VMIDMT_REG_BASE + 0x00000020) +#define HWIO_IPA_VMIDMT_IDR0_PHYS (IPA_VMIDMT_REG_BASE_PHYS + 0x00000020) +#define HWIO_IPA_VMIDMT_IDR0_OFFS (IPA_VMIDMT_REG_BASE_OFFS + 0x00000020) +#define HWIO_IPA_VMIDMT_IDR0_RMSK 0x8001eff +#define HWIO_IPA_VMIDMT_IDR0_ATTR 0x1 +#define HWIO_IPA_VMIDMT_IDR0_IN \ + in_dword_masked(HWIO_IPA_VMIDMT_IDR0_ADDR, HWIO_IPA_VMIDMT_IDR0_RMSK) +#define HWIO_IPA_VMIDMT_IDR0_INM(m) \ + in_dword_masked(HWIO_IPA_VMIDMT_IDR0_ADDR, m) +#define HWIO_IPA_VMIDMT_IDR0_SMS_BMSK 0x8000000 +#define HWIO_IPA_VMIDMT_IDR0_SMS_SHFT 0x1b +#define HWIO_IPA_VMIDMT_IDR0_NUMSIDB_BMSK 0x1e00 +#define HWIO_IPA_VMIDMT_IDR0_NUMSIDB_SHFT 0x9 +#define HWIO_IPA_VMIDMT_IDR0_NUMSMRG_BMSK 0xff +#define HWIO_IPA_VMIDMT_IDR0_NUMSMRG_SHFT 0x0 + +#define HWIO_IPA_VMIDMT_IDR1_ADDR (IPA_VMIDMT_REG_BASE + 0x00000024) +#define HWIO_IPA_VMIDMT_IDR1_PHYS (IPA_VMIDMT_REG_BASE_PHYS + 0x00000024) +#define HWIO_IPA_VMIDMT_IDR1_OFFS (IPA_VMIDMT_REG_BASE_OFFS + 0x00000024) +#define HWIO_IPA_VMIDMT_IDR1_RMSK 0x9f00 +#define HWIO_IPA_VMIDMT_IDR1_ATTR 0x1 +#define HWIO_IPA_VMIDMT_IDR1_IN \ + in_dword_masked(HWIO_IPA_VMIDMT_IDR1_ADDR, HWIO_IPA_VMIDMT_IDR1_RMSK) +#define HWIO_IPA_VMIDMT_IDR1_INM(m) \ + in_dword_masked(HWIO_IPA_VMIDMT_IDR1_ADDR, m) +#define HWIO_IPA_VMIDMT_IDR1_SMCD_BMSK 0x8000 +#define HWIO_IPA_VMIDMT_IDR1_SMCD_SHFT 0xf +#define HWIO_IPA_VMIDMT_IDR1_SSDTP_BMSK 0x1000 +#define HWIO_IPA_VMIDMT_IDR1_SSDTP_SHFT 0xc +#define HWIO_IPA_VMIDMT_IDR1_NUMSSDNDX_BMSK 0xf00 +#define HWIO_IPA_VMIDMT_IDR1_NUMSSDNDX_SHFT 0x8 + +#define HWIO_IPA_VMIDMT_IDR2_ADDR (IPA_VMIDMT_REG_BASE + 0x00000028) +#define HWIO_IPA_VMIDMT_IDR2_PHYS (IPA_VMIDMT_REG_BASE_PHYS + 0x00000028) +#define HWIO_IPA_VMIDMT_IDR2_OFFS (IPA_VMIDMT_REG_BASE_OFFS + 0x00000028) +#define HWIO_IPA_VMIDMT_IDR2_RMSK 0xff +#define HWIO_IPA_VMIDMT_IDR2_ATTR 0x1 +#define HWIO_IPA_VMIDMT_IDR2_IN \ + in_dword_masked(HWIO_IPA_VMIDMT_IDR2_ADDR, HWIO_IPA_VMIDMT_IDR2_RMSK) +#define HWIO_IPA_VMIDMT_IDR2_INM(m) \ + in_dword_masked(HWIO_IPA_VMIDMT_IDR2_ADDR, m) +#define HWIO_IPA_VMIDMT_IDR2_OAS_BMSK 0xf0 +#define HWIO_IPA_VMIDMT_IDR2_OAS_SHFT 0x4 +#define HWIO_IPA_VMIDMT_IDR2_IAS_BMSK 0xf +#define HWIO_IPA_VMIDMT_IDR2_IAS_SHFT 0x0 + +#define HWIO_IPA_VMIDMT_IDR4_ADDR (IPA_VMIDMT_REG_BASE + 0x00000030) +#define HWIO_IPA_VMIDMT_IDR4_PHYS (IPA_VMIDMT_REG_BASE_PHYS + 0x00000030) +#define HWIO_IPA_VMIDMT_IDR4_OFFS (IPA_VMIDMT_REG_BASE_OFFS + 0x00000030) +#define HWIO_IPA_VMIDMT_IDR4_RMSK 0xffffffff +#define HWIO_IPA_VMIDMT_IDR4_ATTR 0x1 +#define HWIO_IPA_VMIDMT_IDR4_IN \ + in_dword_masked(HWIO_IPA_VMIDMT_IDR4_ADDR, HWIO_IPA_VMIDMT_IDR4_RMSK) +#define HWIO_IPA_VMIDMT_IDR4_INM(m) \ + in_dword_masked(HWIO_IPA_VMIDMT_IDR4_ADDR, m) +#define HWIO_IPA_VMIDMT_IDR4_MAJOR_BMSK 0xf0000000 +#define HWIO_IPA_VMIDMT_IDR4_MAJOR_SHFT 0x1c +#define HWIO_IPA_VMIDMT_IDR4_MINOR_BMSK 0xfff0000 +#define HWIO_IPA_VMIDMT_IDR4_MINOR_SHFT 0x10 +#define HWIO_IPA_VMIDMT_IDR4_STEP_BMSK 0xffff +#define HWIO_IPA_VMIDMT_IDR4_STEP_SHFT 0x0 + +#define HWIO_IPA_VMIDMT_IDR5_ADDR (IPA_VMIDMT_REG_BASE + 0x00000034) +#define HWIO_IPA_VMIDMT_IDR5_PHYS (IPA_VMIDMT_REG_BASE_PHYS + 0x00000034) +#define HWIO_IPA_VMIDMT_IDR5_OFFS (IPA_VMIDMT_REG_BASE_OFFS + 0x00000034) +#define HWIO_IPA_VMIDMT_IDR5_RMSK 0xff03ff +#define HWIO_IPA_VMIDMT_IDR5_ATTR 0x1 +#define HWIO_IPA_VMIDMT_IDR5_IN \ + in_dword_masked(HWIO_IPA_VMIDMT_IDR5_ADDR, HWIO_IPA_VMIDMT_IDR5_RMSK) +#define HWIO_IPA_VMIDMT_IDR5_INM(m) \ + in_dword_masked(HWIO_IPA_VMIDMT_IDR5_ADDR, m) +#define HWIO_IPA_VMIDMT_IDR5_NUMMSDRB_BMSK 0xff0000 +#define HWIO_IPA_VMIDMT_IDR5_NUMMSDRB_SHFT 0x10 +#define HWIO_IPA_VMIDMT_IDR5_MSAE_BMSK 0x200 +#define HWIO_IPA_VMIDMT_IDR5_MSAE_SHFT 0x9 +#define HWIO_IPA_VMIDMT_IDR5_QRIBE_BMSK 0x100 +#define HWIO_IPA_VMIDMT_IDR5_QRIBE_SHFT 0x8 +#define HWIO_IPA_VMIDMT_IDR5_NVMID_BMSK 0xff +#define HWIO_IPA_VMIDMT_IDR5_NVMID_SHFT 0x0 + +#define HWIO_IPA_VMIDMT_IDR7_ADDR (IPA_VMIDMT_REG_BASE + 0x0000003c) +#define HWIO_IPA_VMIDMT_IDR7_PHYS (IPA_VMIDMT_REG_BASE_PHYS + 0x0000003c) +#define HWIO_IPA_VMIDMT_IDR7_OFFS (IPA_VMIDMT_REG_BASE_OFFS + 0x0000003c) +#define HWIO_IPA_VMIDMT_IDR7_RMSK 0xff +#define HWIO_IPA_VMIDMT_IDR7_ATTR 0x1 +#define HWIO_IPA_VMIDMT_IDR7_IN \ + in_dword_masked(HWIO_IPA_VMIDMT_IDR7_ADDR, HWIO_IPA_VMIDMT_IDR7_RMSK) +#define HWIO_IPA_VMIDMT_IDR7_INM(m) \ + in_dword_masked(HWIO_IPA_VMIDMT_IDR7_ADDR, m) +#define HWIO_IPA_VMIDMT_IDR7_MAJOR_BMSK 0xf0 +#define HWIO_IPA_VMIDMT_IDR7_MAJOR_SHFT 0x4 +#define HWIO_IPA_VMIDMT_IDR7_MINOR_BMSK 0xf +#define HWIO_IPA_VMIDMT_IDR7_MINOR_SHFT 0x0 + +#define HWIO_IPA_VMIDMT_GFAR0_ADDR (IPA_VMIDMT_REG_BASE + 0x00000040) +#define HWIO_IPA_VMIDMT_GFAR0_PHYS (IPA_VMIDMT_REG_BASE_PHYS + 0x00000040) +#define HWIO_IPA_VMIDMT_GFAR0_OFFS (IPA_VMIDMT_REG_BASE_OFFS + 0x00000040) +#define HWIO_IPA_VMIDMT_GFAR0_RMSK 0xffffffff +#define HWIO_IPA_VMIDMT_GFAR0_ATTR 0x1 +#define HWIO_IPA_VMIDMT_GFAR0_IN \ + in_dword_masked(HWIO_IPA_VMIDMT_GFAR0_ADDR, HWIO_IPA_VMIDMT_GFAR0_RMSK) +#define HWIO_IPA_VMIDMT_GFAR0_INM(m) \ + in_dword_masked(HWIO_IPA_VMIDMT_GFAR0_ADDR, m) +#define HWIO_IPA_VMIDMT_GFAR0_GFEA0_BMSK 0xffffffff +#define HWIO_IPA_VMIDMT_GFAR0_GFEA0_SHFT 0x0 + +#define HWIO_IPA_VMIDMT_GFAR1_ADDR (IPA_VMIDMT_REG_BASE + 0x00000044) +#define HWIO_IPA_VMIDMT_GFAR1_PHYS (IPA_VMIDMT_REG_BASE_PHYS + 0x00000044) +#define HWIO_IPA_VMIDMT_GFAR1_OFFS (IPA_VMIDMT_REG_BASE_OFFS + 0x00000044) +#define HWIO_IPA_VMIDMT_GFAR1_RMSK 0xff +#define HWIO_IPA_VMIDMT_GFAR1_ATTR 0x1 +#define HWIO_IPA_VMIDMT_GFAR1_IN \ + in_dword_masked(HWIO_IPA_VMIDMT_GFAR1_ADDR, HWIO_IPA_VMIDMT_GFAR1_RMSK) +#define HWIO_IPA_VMIDMT_GFAR1_INM(m) \ + in_dword_masked(HWIO_IPA_VMIDMT_GFAR1_ADDR, m) +#define HWIO_IPA_VMIDMT_GFAR1_GFEA1_BMSK 0xff +#define HWIO_IPA_VMIDMT_GFAR1_GFEA1_SHFT 0x0 + +#define HWIO_IPA_VMIDMT_GFSR_ADDR (IPA_VMIDMT_REG_BASE + 0x00000048) +#define HWIO_IPA_VMIDMT_GFSR_PHYS (IPA_VMIDMT_REG_BASE_PHYS + 0x00000048) +#define HWIO_IPA_VMIDMT_GFSR_OFFS (IPA_VMIDMT_REG_BASE_OFFS + 0x00000048) +#define HWIO_IPA_VMIDMT_GFSR_RMSK 0xc00000a6 +#define HWIO_IPA_VMIDMT_GFSR_ATTR 0x3 +#define HWIO_IPA_VMIDMT_GFSR_IN \ + in_dword_masked(HWIO_IPA_VMIDMT_GFSR_ADDR, HWIO_IPA_VMIDMT_GFSR_RMSK) +#define HWIO_IPA_VMIDMT_GFSR_INM(m) \ + in_dword_masked(HWIO_IPA_VMIDMT_GFSR_ADDR, m) +#define HWIO_IPA_VMIDMT_GFSR_OUT(v) \ + out_dword(HWIO_IPA_VMIDMT_GFSR_ADDR,v) +#define HWIO_IPA_VMIDMT_GFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_VMIDMT_GFSR_ADDR,m,v,HWIO_IPA_VMIDMT_GFSR_IN) +#define HWIO_IPA_VMIDMT_GFSR_MULTI_CLIENT_BMSK 0x80000000 +#define HWIO_IPA_VMIDMT_GFSR_MULTI_CLIENT_SHFT 0x1f +#define HWIO_IPA_VMIDMT_GFSR_MULTI_CFG_BMSK 0x40000000 +#define HWIO_IPA_VMIDMT_GFSR_MULTI_CFG_SHFT 0x1e +#define HWIO_IPA_VMIDMT_GFSR_PF_BMSK 0x80 +#define HWIO_IPA_VMIDMT_GFSR_PF_SHFT 0x7 +#define HWIO_IPA_VMIDMT_GFSR_CAF_BMSK 0x20 +#define HWIO_IPA_VMIDMT_GFSR_CAF_SHFT 0x5 +#define HWIO_IPA_VMIDMT_GFSR_SMCF_BMSK 0x4 +#define HWIO_IPA_VMIDMT_GFSR_SMCF_SHFT 0x2 +#define HWIO_IPA_VMIDMT_GFSR_USF_BMSK 0x2 +#define HWIO_IPA_VMIDMT_GFSR_USF_SHFT 0x1 + +#define HWIO_IPA_VMIDMT_GFSRRESTORE_ADDR (IPA_VMIDMT_REG_BASE + 0x0000004c) +#define HWIO_IPA_VMIDMT_GFSRRESTORE_PHYS (IPA_VMIDMT_REG_BASE_PHYS + 0x0000004c) +#define HWIO_IPA_VMIDMT_GFSRRESTORE_OFFS (IPA_VMIDMT_REG_BASE_OFFS + 0x0000004c) +#define HWIO_IPA_VMIDMT_GFSRRESTORE_RMSK 0xc00000a6 +#define HWIO_IPA_VMIDMT_GFSRRESTORE_ATTR 0x3 +#define HWIO_IPA_VMIDMT_GFSRRESTORE_IN \ + in_dword_masked(HWIO_IPA_VMIDMT_GFSRRESTORE_ADDR, HWIO_IPA_VMIDMT_GFSRRESTORE_RMSK) +#define HWIO_IPA_VMIDMT_GFSRRESTORE_INM(m) \ + in_dword_masked(HWIO_IPA_VMIDMT_GFSRRESTORE_ADDR, m) +#define HWIO_IPA_VMIDMT_GFSRRESTORE_OUT(v) \ + out_dword(HWIO_IPA_VMIDMT_GFSRRESTORE_ADDR,v) +#define HWIO_IPA_VMIDMT_GFSRRESTORE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_VMIDMT_GFSRRESTORE_ADDR,m,v,HWIO_IPA_VMIDMT_GFSRRESTORE_IN) +#define HWIO_IPA_VMIDMT_GFSRRESTORE_MULTI_CLIENT_BMSK 0x80000000 +#define HWIO_IPA_VMIDMT_GFSRRESTORE_MULTI_CLIENT_SHFT 0x1f +#define HWIO_IPA_VMIDMT_GFSRRESTORE_MULTI_CFG_BMSK 0x40000000 +#define HWIO_IPA_VMIDMT_GFSRRESTORE_MULTI_CFG_SHFT 0x1e +#define HWIO_IPA_VMIDMT_GFSRRESTORE_PF_BMSK 0x80 +#define HWIO_IPA_VMIDMT_GFSRRESTORE_PF_SHFT 0x7 +#define HWIO_IPA_VMIDMT_GFSRRESTORE_CAF_BMSK 0x20 +#define HWIO_IPA_VMIDMT_GFSRRESTORE_CAF_SHFT 0x5 +#define HWIO_IPA_VMIDMT_GFSRRESTORE_SMCF_BMSK 0x4 +#define HWIO_IPA_VMIDMT_GFSRRESTORE_SMCF_SHFT 0x2 +#define HWIO_IPA_VMIDMT_GFSRRESTORE_USF_BMSK 0x2 +#define HWIO_IPA_VMIDMT_GFSRRESTORE_USF_SHFT 0x1 + +#define HWIO_IPA_VMIDMT_GFSYNDR0_ADDR (IPA_VMIDMT_REG_BASE + 0x00000050) +#define HWIO_IPA_VMIDMT_GFSYNDR0_PHYS (IPA_VMIDMT_REG_BASE_PHYS + 0x00000050) +#define HWIO_IPA_VMIDMT_GFSYNDR0_OFFS (IPA_VMIDMT_REG_BASE_OFFS + 0x00000050) +#define HWIO_IPA_VMIDMT_GFSYNDR0_RMSK 0x132 +#define HWIO_IPA_VMIDMT_GFSYNDR0_ATTR 0x1 +#define HWIO_IPA_VMIDMT_GFSYNDR0_IN \ + in_dword_masked(HWIO_IPA_VMIDMT_GFSYNDR0_ADDR, HWIO_IPA_VMIDMT_GFSYNDR0_RMSK) +#define HWIO_IPA_VMIDMT_GFSYNDR0_INM(m) \ + in_dword_masked(HWIO_IPA_VMIDMT_GFSYNDR0_ADDR, m) +#define HWIO_IPA_VMIDMT_GFSYNDR0_MSSSELFAUTH_BMSK 0x100 +#define HWIO_IPA_VMIDMT_GFSYNDR0_MSSSELFAUTH_SHFT 0x8 +#define HWIO_IPA_VMIDMT_GFSYNDR0_NSATTR_BMSK 0x20 +#define HWIO_IPA_VMIDMT_GFSYNDR0_NSATTR_SHFT 0x5 +#define HWIO_IPA_VMIDMT_GFSYNDR0_NSSTATE_BMSK 0x10 +#define HWIO_IPA_VMIDMT_GFSYNDR0_NSSTATE_SHFT 0x4 +#define HWIO_IPA_VMIDMT_GFSYNDR0_WNR_BMSK 0x2 +#define HWIO_IPA_VMIDMT_GFSYNDR0_WNR_SHFT 0x1 + +#define HWIO_IPA_VMIDMT_GFSYNDR1_ADDR (IPA_VMIDMT_REG_BASE + 0x00000054) +#define HWIO_IPA_VMIDMT_GFSYNDR1_PHYS (IPA_VMIDMT_REG_BASE_PHYS + 0x00000054) +#define HWIO_IPA_VMIDMT_GFSYNDR1_OFFS (IPA_VMIDMT_REG_BASE_OFFS + 0x00000054) +#define HWIO_IPA_VMIDMT_GFSYNDR1_RMSK 0x7fff00ff +#define HWIO_IPA_VMIDMT_GFSYNDR1_ATTR 0x1 +#define HWIO_IPA_VMIDMT_GFSYNDR1_IN \ + in_dword_masked(HWIO_IPA_VMIDMT_GFSYNDR1_ADDR, HWIO_IPA_VMIDMT_GFSYNDR1_RMSK) +#define HWIO_IPA_VMIDMT_GFSYNDR1_INM(m) \ + in_dword_masked(HWIO_IPA_VMIDMT_GFSYNDR1_ADDR, m) +#define HWIO_IPA_VMIDMT_GFSYNDR1_MSDINDEX_BMSK 0x7f000000 +#define HWIO_IPA_VMIDMT_GFSYNDR1_MSDINDEX_SHFT 0x18 +#define HWIO_IPA_VMIDMT_GFSYNDR1_SSDINDEX_BMSK 0xff0000 +#define HWIO_IPA_VMIDMT_GFSYNDR1_SSDINDEX_SHFT 0x10 +#define HWIO_IPA_VMIDMT_GFSYNDR1_STREAMINDEX_BMSK 0xff +#define HWIO_IPA_VMIDMT_GFSYNDR1_STREAMINDEX_SHFT 0x0 + +#define HWIO_IPA_VMIDMT_GFSYNDR2_ADDR (IPA_VMIDMT_REG_BASE + 0x00000058) +#define HWIO_IPA_VMIDMT_GFSYNDR2_PHYS (IPA_VMIDMT_REG_BASE_PHYS + 0x00000058) +#define HWIO_IPA_VMIDMT_GFSYNDR2_OFFS (IPA_VMIDMT_REG_BASE_OFFS + 0x00000058) +#define HWIO_IPA_VMIDMT_GFSYNDR2_RMSK 0x1f1fffff +#define HWIO_IPA_VMIDMT_GFSYNDR2_ATTR 0x1 +#define HWIO_IPA_VMIDMT_GFSYNDR2_IN \ + in_dword_masked(HWIO_IPA_VMIDMT_GFSYNDR2_ADDR, HWIO_IPA_VMIDMT_GFSYNDR2_RMSK) +#define HWIO_IPA_VMIDMT_GFSYNDR2_INM(m) \ + in_dword_masked(HWIO_IPA_VMIDMT_GFSYNDR2_ADDR, m) +#define HWIO_IPA_VMIDMT_GFSYNDR2_ATID_BMSK 0x1f000000 +#define HWIO_IPA_VMIDMT_GFSYNDR2_ATID_SHFT 0x18 +#define HWIO_IPA_VMIDMT_GFSYNDR2_AVMID_BMSK 0x1f0000 +#define HWIO_IPA_VMIDMT_GFSYNDR2_AVMID_SHFT 0x10 +#define HWIO_IPA_VMIDMT_GFSYNDR2_ABID_BMSK 0xe000 +#define HWIO_IPA_VMIDMT_GFSYNDR2_ABID_SHFT 0xd +#define HWIO_IPA_VMIDMT_GFSYNDR2_APID_BMSK 0x1f00 +#define HWIO_IPA_VMIDMT_GFSYNDR2_APID_SHFT 0x8 +#define HWIO_IPA_VMIDMT_GFSYNDR2_AMID_BMSK 0xff +#define HWIO_IPA_VMIDMT_GFSYNDR2_AMID_SHFT 0x0 + +#define HWIO_IPA_VMIDMT_VMIDMTCR0_ADDR (IPA_VMIDMT_REG_BASE + 0x00000090) +#define HWIO_IPA_VMIDMT_VMIDMTCR0_PHYS (IPA_VMIDMT_REG_BASE_PHYS + 0x00000090) +#define HWIO_IPA_VMIDMT_VMIDMTCR0_OFFS (IPA_VMIDMT_REG_BASE_OFFS + 0x00000090) +#define HWIO_IPA_VMIDMT_VMIDMTCR0_RMSK 0x1 +#define HWIO_IPA_VMIDMT_VMIDMTCR0_ATTR 0x3 +#define HWIO_IPA_VMIDMT_VMIDMTCR0_IN \ + in_dword_masked(HWIO_IPA_VMIDMT_VMIDMTCR0_ADDR, HWIO_IPA_VMIDMT_VMIDMTCR0_RMSK) +#define HWIO_IPA_VMIDMT_VMIDMTCR0_INM(m) \ + in_dword_masked(HWIO_IPA_VMIDMT_VMIDMTCR0_ADDR, m) +#define HWIO_IPA_VMIDMT_VMIDMTCR0_OUT(v) \ + out_dword(HWIO_IPA_VMIDMT_VMIDMTCR0_ADDR,v) +#define HWIO_IPA_VMIDMT_VMIDMTCR0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_VMIDMT_VMIDMTCR0_ADDR,m,v,HWIO_IPA_VMIDMT_VMIDMTCR0_IN) +#define HWIO_IPA_VMIDMT_VMIDMTCR0_CLKONOFFE_BMSK 0x1 +#define HWIO_IPA_VMIDMT_VMIDMTCR0_CLKONOFFE_SHFT 0x0 + +#define HWIO_IPA_VMIDMT_VMIDMTACR_ADDR (IPA_VMIDMT_REG_BASE + 0x0000009c) +#define HWIO_IPA_VMIDMT_VMIDMTACR_PHYS (IPA_VMIDMT_REG_BASE_PHYS + 0x0000009c) +#define HWIO_IPA_VMIDMT_VMIDMTACR_OFFS (IPA_VMIDMT_REG_BASE_OFFS + 0x0000009c) +#define HWIO_IPA_VMIDMT_VMIDMTACR_RMSK 0xffffffff +#define HWIO_IPA_VMIDMT_VMIDMTACR_ATTR 0x3 +#define HWIO_IPA_VMIDMT_VMIDMTACR_IN \ + in_dword_masked(HWIO_IPA_VMIDMT_VMIDMTACR_ADDR, HWIO_IPA_VMIDMT_VMIDMTACR_RMSK) +#define HWIO_IPA_VMIDMT_VMIDMTACR_INM(m) \ + in_dword_masked(HWIO_IPA_VMIDMT_VMIDMTACR_ADDR, m) +#define HWIO_IPA_VMIDMT_VMIDMTACR_OUT(v) \ + out_dword(HWIO_IPA_VMIDMT_VMIDMTACR_ADDR,v) +#define HWIO_IPA_VMIDMT_VMIDMTACR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_VMIDMT_VMIDMTACR_ADDR,m,v,HWIO_IPA_VMIDMT_VMIDMTACR_IN) +#define HWIO_IPA_VMIDMT_VMIDMTACR_RWE_BMSK 0xffffffff +#define HWIO_IPA_VMIDMT_VMIDMTACR_RWE_SHFT 0x0 + +#define HWIO_IPA_VMIDMT_NSCR0_ADDR (IPA_VMIDMT_REG_BASE + 0x00000400) +#define HWIO_IPA_VMIDMT_NSCR0_PHYS (IPA_VMIDMT_REG_BASE_PHYS + 0x00000400) +#define HWIO_IPA_VMIDMT_NSCR0_OFFS (IPA_VMIDMT_REG_BASE_OFFS + 0x00000400) +#define HWIO_IPA_VMIDMT_NSCR0_RMSK 0xff70ff5 +#define HWIO_IPA_VMIDMT_NSCR0_ATTR 0x3 +#define HWIO_IPA_VMIDMT_NSCR0_IN \ + in_dword_masked(HWIO_IPA_VMIDMT_NSCR0_ADDR, HWIO_IPA_VMIDMT_NSCR0_RMSK) +#define HWIO_IPA_VMIDMT_NSCR0_INM(m) \ + in_dword_masked(HWIO_IPA_VMIDMT_NSCR0_ADDR, m) +#define HWIO_IPA_VMIDMT_NSCR0_OUT(v) \ + out_dword(HWIO_IPA_VMIDMT_NSCR0_ADDR,v) +#define HWIO_IPA_VMIDMT_NSCR0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_VMIDMT_NSCR0_ADDR,m,v,HWIO_IPA_VMIDMT_NSCR0_IN) +#define HWIO_IPA_VMIDMT_NSCR0_WACFG_BMSK 0xc000000 +#define HWIO_IPA_VMIDMT_NSCR0_WACFG_SHFT 0x1a +#define HWIO_IPA_VMIDMT_NSCR0_RACFG_BMSK 0x3000000 +#define HWIO_IPA_VMIDMT_NSCR0_RACFG_SHFT 0x18 +#define HWIO_IPA_VMIDMT_NSCR0_SHCFG_BMSK 0xc00000 +#define HWIO_IPA_VMIDMT_NSCR0_SHCFG_SHFT 0x16 +#define HWIO_IPA_VMIDMT_NSCR0_SMCFCFG_BMSK 0x200000 +#define HWIO_IPA_VMIDMT_NSCR0_SMCFCFG_SHFT 0x15 +#define HWIO_IPA_VMIDMT_NSCR0_MTCFG_BMSK 0x100000 +#define HWIO_IPA_VMIDMT_NSCR0_MTCFG_SHFT 0x14 +#define HWIO_IPA_VMIDMT_NSCR0_MEMATTR_BMSK 0x70000 +#define HWIO_IPA_VMIDMT_NSCR0_MEMATTR_SHFT 0x10 +#define HWIO_IPA_VMIDMT_NSCR0_VMIDPNE_BMSK 0x800 +#define HWIO_IPA_VMIDMT_NSCR0_VMIDPNE_SHFT 0xb +#define HWIO_IPA_VMIDMT_NSCR0_USFCFG_BMSK 0x400 +#define HWIO_IPA_VMIDMT_NSCR0_USFCFG_SHFT 0xa +#define HWIO_IPA_VMIDMT_NSCR0_GSE_BMSK 0x200 +#define HWIO_IPA_VMIDMT_NSCR0_GSE_SHFT 0x9 +#define HWIO_IPA_VMIDMT_NSCR0_STALLD_BMSK 0x100 +#define HWIO_IPA_VMIDMT_NSCR0_STALLD_SHFT 0x8 +#define HWIO_IPA_VMIDMT_NSCR0_TRANSIENTCFG_BMSK 0xc0 +#define HWIO_IPA_VMIDMT_NSCR0_TRANSIENTCFG_SHFT 0x6 +#define HWIO_IPA_VMIDMT_NSCR0_GCFGFIE_BMSK 0x20 +#define HWIO_IPA_VMIDMT_NSCR0_GCFGFIE_SHFT 0x5 +#define HWIO_IPA_VMIDMT_NSCR0_GCFGERE_BMSK 0x10 +#define HWIO_IPA_VMIDMT_NSCR0_GCFGERE_SHFT 0x4 +#define HWIO_IPA_VMIDMT_NSCR0_GFIE_BMSK 0x4 +#define HWIO_IPA_VMIDMT_NSCR0_GFIE_SHFT 0x2 +#define HWIO_IPA_VMIDMT_NSCR0_CLIENTPD_BMSK 0x1 +#define HWIO_IPA_VMIDMT_NSCR0_CLIENTPD_SHFT 0x0 + +#define HWIO_IPA_VMIDMT_NSCR2_ADDR (IPA_VMIDMT_REG_BASE + 0x00000408) +#define HWIO_IPA_VMIDMT_NSCR2_PHYS (IPA_VMIDMT_REG_BASE_PHYS + 0x00000408) +#define HWIO_IPA_VMIDMT_NSCR2_OFFS (IPA_VMIDMT_REG_BASE_OFFS + 0x00000408) +#define HWIO_IPA_VMIDMT_NSCR2_RMSK 0x1f +#define HWIO_IPA_VMIDMT_NSCR2_ATTR 0x3 +#define HWIO_IPA_VMIDMT_NSCR2_IN \ + in_dword_masked(HWIO_IPA_VMIDMT_NSCR2_ADDR, HWIO_IPA_VMIDMT_NSCR2_RMSK) +#define HWIO_IPA_VMIDMT_NSCR2_INM(m) \ + in_dword_masked(HWIO_IPA_VMIDMT_NSCR2_ADDR, m) +#define HWIO_IPA_VMIDMT_NSCR2_OUT(v) \ + out_dword(HWIO_IPA_VMIDMT_NSCR2_ADDR,v) +#define HWIO_IPA_VMIDMT_NSCR2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_VMIDMT_NSCR2_ADDR,m,v,HWIO_IPA_VMIDMT_NSCR2_IN) +#define HWIO_IPA_VMIDMT_NSCR2_BPVMID_BMSK 0x1f +#define HWIO_IPA_VMIDMT_NSCR2_BPVMID_SHFT 0x0 + +#define HWIO_IPA_VMIDMT_NSACR_ADDR (IPA_VMIDMT_REG_BASE + 0x00000410) +#define HWIO_IPA_VMIDMT_NSACR_PHYS (IPA_VMIDMT_REG_BASE_PHYS + 0x00000410) +#define HWIO_IPA_VMIDMT_NSACR_OFFS (IPA_VMIDMT_REG_BASE_OFFS + 0x00000410) +#define HWIO_IPA_VMIDMT_NSACR_RMSK 0x70000013 +#define HWIO_IPA_VMIDMT_NSACR_ATTR 0x3 +#define HWIO_IPA_VMIDMT_NSACR_IN \ + in_dword_masked(HWIO_IPA_VMIDMT_NSACR_ADDR, HWIO_IPA_VMIDMT_NSACR_RMSK) +#define HWIO_IPA_VMIDMT_NSACR_INM(m) \ + in_dword_masked(HWIO_IPA_VMIDMT_NSACR_ADDR, m) +#define HWIO_IPA_VMIDMT_NSACR_OUT(v) \ + out_dword(HWIO_IPA_VMIDMT_NSACR_ADDR,v) +#define HWIO_IPA_VMIDMT_NSACR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_VMIDMT_NSACR_ADDR,m,v,HWIO_IPA_VMIDMT_NSACR_IN) +#define HWIO_IPA_VMIDMT_NSACR_BPRCNSH_BMSK 0x40000000 +#define HWIO_IPA_VMIDMT_NSACR_BPRCNSH_SHFT 0x1e +#define HWIO_IPA_VMIDMT_NSACR_BPRCISH_BMSK 0x20000000 +#define HWIO_IPA_VMIDMT_NSACR_BPRCISH_SHFT 0x1d +#define HWIO_IPA_VMIDMT_NSACR_BPRCOSH_BMSK 0x10000000 +#define HWIO_IPA_VMIDMT_NSACR_BPRCOSH_SHFT 0x1c +#define HWIO_IPA_VMIDMT_NSACR_BPREQPRIORITYCFG_BMSK 0x10 +#define HWIO_IPA_VMIDMT_NSACR_BPREQPRIORITYCFG_SHFT 0x4 +#define HWIO_IPA_VMIDMT_NSACR_BPREQPRIORITY_BMSK 0x3 +#define HWIO_IPA_VMIDMT_NSACR_BPREQPRIORITY_SHFT 0x0 + +#define HWIO_IPA_VMIDMT_NSGFAR0_ADDR (IPA_VMIDMT_REG_BASE + 0x00000440) +#define HWIO_IPA_VMIDMT_NSGFAR0_PHYS (IPA_VMIDMT_REG_BASE_PHYS + 0x00000440) +#define HWIO_IPA_VMIDMT_NSGFAR0_OFFS (IPA_VMIDMT_REG_BASE_OFFS + 0x00000440) +#define HWIO_IPA_VMIDMT_NSGFAR0_RMSK 0xffffffff +#define HWIO_IPA_VMIDMT_NSGFAR0_ATTR 0x1 +#define HWIO_IPA_VMIDMT_NSGFAR0_IN \ + in_dword_masked(HWIO_IPA_VMIDMT_NSGFAR0_ADDR, HWIO_IPA_VMIDMT_NSGFAR0_RMSK) +#define HWIO_IPA_VMIDMT_NSGFAR0_INM(m) \ + in_dword_masked(HWIO_IPA_VMIDMT_NSGFAR0_ADDR, m) +#define HWIO_IPA_VMIDMT_NSGFAR0_GFEA0_BMSK 0xffffffff +#define HWIO_IPA_VMIDMT_NSGFAR0_GFEA0_SHFT 0x0 + +#define HWIO_IPA_VMIDMT_NSGFAR1_ADDR (IPA_VMIDMT_REG_BASE + 0x00000444) +#define HWIO_IPA_VMIDMT_NSGFAR1_PHYS (IPA_VMIDMT_REG_BASE_PHYS + 0x00000444) +#define HWIO_IPA_VMIDMT_NSGFAR1_OFFS (IPA_VMIDMT_REG_BASE_OFFS + 0x00000444) +#define HWIO_IPA_VMIDMT_NSGFAR1_RMSK 0xff +#define HWIO_IPA_VMIDMT_NSGFAR1_ATTR 0x1 +#define HWIO_IPA_VMIDMT_NSGFAR1_IN \ + in_dword_masked(HWIO_IPA_VMIDMT_NSGFAR1_ADDR, HWIO_IPA_VMIDMT_NSGFAR1_RMSK) +#define HWIO_IPA_VMIDMT_NSGFAR1_INM(m) \ + in_dword_masked(HWIO_IPA_VMIDMT_NSGFAR1_ADDR, m) +#define HWIO_IPA_VMIDMT_NSGFAR1_GFEA1_BMSK 0xff +#define HWIO_IPA_VMIDMT_NSGFAR1_GFEA1_SHFT 0x0 + +#define HWIO_IPA_VMIDMT_NSGFSR_ADDR (IPA_VMIDMT_REG_BASE + 0x00000448) +#define HWIO_IPA_VMIDMT_NSGFSR_PHYS (IPA_VMIDMT_REG_BASE_PHYS + 0x00000448) +#define HWIO_IPA_VMIDMT_NSGFSR_OFFS (IPA_VMIDMT_REG_BASE_OFFS + 0x00000448) +#define HWIO_IPA_VMIDMT_NSGFSR_RMSK 0xc00000a6 +#define HWIO_IPA_VMIDMT_NSGFSR_ATTR 0x3 +#define HWIO_IPA_VMIDMT_NSGFSR_IN \ + in_dword_masked(HWIO_IPA_VMIDMT_NSGFSR_ADDR, HWIO_IPA_VMIDMT_NSGFSR_RMSK) +#define HWIO_IPA_VMIDMT_NSGFSR_INM(m) \ + in_dword_masked(HWIO_IPA_VMIDMT_NSGFSR_ADDR, m) +#define HWIO_IPA_VMIDMT_NSGFSR_OUT(v) \ + out_dword(HWIO_IPA_VMIDMT_NSGFSR_ADDR,v) +#define HWIO_IPA_VMIDMT_NSGFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_VMIDMT_NSGFSR_ADDR,m,v,HWIO_IPA_VMIDMT_NSGFSR_IN) +#define HWIO_IPA_VMIDMT_NSGFSR_MULTI_CLIENT_BMSK 0x80000000 +#define HWIO_IPA_VMIDMT_NSGFSR_MULTI_CLIENT_SHFT 0x1f +#define HWIO_IPA_VMIDMT_NSGFSR_MULTI_CFG_BMSK 0x40000000 +#define HWIO_IPA_VMIDMT_NSGFSR_MULTI_CFG_SHFT 0x1e +#define HWIO_IPA_VMIDMT_NSGFSR_PF_BMSK 0x80 +#define HWIO_IPA_VMIDMT_NSGFSR_PF_SHFT 0x7 +#define HWIO_IPA_VMIDMT_NSGFSR_CAF_BMSK 0x20 +#define HWIO_IPA_VMIDMT_NSGFSR_CAF_SHFT 0x5 +#define HWIO_IPA_VMIDMT_NSGFSR_SMCF_BMSK 0x4 +#define HWIO_IPA_VMIDMT_NSGFSR_SMCF_SHFT 0x2 +#define HWIO_IPA_VMIDMT_NSGFSR_USF_BMSK 0x2 +#define HWIO_IPA_VMIDMT_NSGFSR_USF_SHFT 0x1 + +#define HWIO_IPA_VMIDMT_NSGFSRRESTORE_ADDR (IPA_VMIDMT_REG_BASE + 0x0000044c) +#define HWIO_IPA_VMIDMT_NSGFSRRESTORE_PHYS (IPA_VMIDMT_REG_BASE_PHYS + 0x0000044c) +#define HWIO_IPA_VMIDMT_NSGFSRRESTORE_OFFS (IPA_VMIDMT_REG_BASE_OFFS + 0x0000044c) +#define HWIO_IPA_VMIDMT_NSGFSRRESTORE_RMSK 0xc00000a6 +#define HWIO_IPA_VMIDMT_NSGFSRRESTORE_ATTR 0x3 +#define HWIO_IPA_VMIDMT_NSGFSRRESTORE_IN \ + in_dword_masked(HWIO_IPA_VMIDMT_NSGFSRRESTORE_ADDR, HWIO_IPA_VMIDMT_NSGFSRRESTORE_RMSK) +#define HWIO_IPA_VMIDMT_NSGFSRRESTORE_INM(m) \ + in_dword_masked(HWIO_IPA_VMIDMT_NSGFSRRESTORE_ADDR, m) +#define HWIO_IPA_VMIDMT_NSGFSRRESTORE_OUT(v) \ + out_dword(HWIO_IPA_VMIDMT_NSGFSRRESTORE_ADDR,v) +#define HWIO_IPA_VMIDMT_NSGFSRRESTORE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_VMIDMT_NSGFSRRESTORE_ADDR,m,v,HWIO_IPA_VMIDMT_NSGFSRRESTORE_IN) +#define HWIO_IPA_VMIDMT_NSGFSRRESTORE_MULTI_CLIENT_BMSK 0x80000000 +#define HWIO_IPA_VMIDMT_NSGFSRRESTORE_MULTI_CLIENT_SHFT 0x1f +#define HWIO_IPA_VMIDMT_NSGFSRRESTORE_MULTI_CFG_BMSK 0x40000000 +#define HWIO_IPA_VMIDMT_NSGFSRRESTORE_MULTI_CFG_SHFT 0x1e +#define HWIO_IPA_VMIDMT_NSGFSRRESTORE_PF_BMSK 0x80 +#define HWIO_IPA_VMIDMT_NSGFSRRESTORE_PF_SHFT 0x7 +#define HWIO_IPA_VMIDMT_NSGFSRRESTORE_CAF_BMSK 0x20 +#define HWIO_IPA_VMIDMT_NSGFSRRESTORE_CAF_SHFT 0x5 +#define HWIO_IPA_VMIDMT_NSGFSRRESTORE_SMCF_BMSK 0x4 +#define HWIO_IPA_VMIDMT_NSGFSRRESTORE_SMCF_SHFT 0x2 +#define HWIO_IPA_VMIDMT_NSGFSRRESTORE_USF_BMSK 0x2 +#define HWIO_IPA_VMIDMT_NSGFSRRESTORE_USF_SHFT 0x1 + +#define HWIO_IPA_VMIDMT_NSGFSYNDR0_ADDR (IPA_VMIDMT_REG_BASE + 0x00000450) +#define HWIO_IPA_VMIDMT_NSGFSYNDR0_PHYS (IPA_VMIDMT_REG_BASE_PHYS + 0x00000450) +#define HWIO_IPA_VMIDMT_NSGFSYNDR0_OFFS (IPA_VMIDMT_REG_BASE_OFFS + 0x00000450) +#define HWIO_IPA_VMIDMT_NSGFSYNDR0_RMSK 0x132 +#define HWIO_IPA_VMIDMT_NSGFSYNDR0_ATTR 0x1 +#define HWIO_IPA_VMIDMT_NSGFSYNDR0_IN \ + in_dword_masked(HWIO_IPA_VMIDMT_NSGFSYNDR0_ADDR, HWIO_IPA_VMIDMT_NSGFSYNDR0_RMSK) +#define HWIO_IPA_VMIDMT_NSGFSYNDR0_INM(m) \ + in_dword_masked(HWIO_IPA_VMIDMT_NSGFSYNDR0_ADDR, m) +#define HWIO_IPA_VMIDMT_NSGFSYNDR0_MSSSELFAUTH_BMSK 0x100 +#define HWIO_IPA_VMIDMT_NSGFSYNDR0_MSSSELFAUTH_SHFT 0x8 +#define HWIO_IPA_VMIDMT_NSGFSYNDR0_NSATTR_BMSK 0x20 +#define HWIO_IPA_VMIDMT_NSGFSYNDR0_NSATTR_SHFT 0x5 +#define HWIO_IPA_VMIDMT_NSGFSYNDR0_NSSTATE_BMSK 0x10 +#define HWIO_IPA_VMIDMT_NSGFSYNDR0_NSSTATE_SHFT 0x4 +#define HWIO_IPA_VMIDMT_NSGFSYNDR0_WNR_BMSK 0x2 +#define HWIO_IPA_VMIDMT_NSGFSYNDR0_WNR_SHFT 0x1 + +#define HWIO_IPA_VMIDMT_NSGFSYNDR1_ADDR (IPA_VMIDMT_REG_BASE + 0x00000454) +#define HWIO_IPA_VMIDMT_NSGFSYNDR1_PHYS (IPA_VMIDMT_REG_BASE_PHYS + 0x00000454) +#define HWIO_IPA_VMIDMT_NSGFSYNDR1_OFFS (IPA_VMIDMT_REG_BASE_OFFS + 0x00000454) +#define HWIO_IPA_VMIDMT_NSGFSYNDR1_RMSK 0x7fff00ff +#define HWIO_IPA_VMIDMT_NSGFSYNDR1_ATTR 0x1 +#define HWIO_IPA_VMIDMT_NSGFSYNDR1_IN \ + in_dword_masked(HWIO_IPA_VMIDMT_NSGFSYNDR1_ADDR, HWIO_IPA_VMIDMT_NSGFSYNDR1_RMSK) +#define HWIO_IPA_VMIDMT_NSGFSYNDR1_INM(m) \ + in_dword_masked(HWIO_IPA_VMIDMT_NSGFSYNDR1_ADDR, m) +#define HWIO_IPA_VMIDMT_NSGFSYNDR1_MSDINDEX_BMSK 0x7f000000 +#define HWIO_IPA_VMIDMT_NSGFSYNDR1_MSDINDEX_SHFT 0x18 +#define HWIO_IPA_VMIDMT_NSGFSYNDR1_SSDINDEX_BMSK 0xff0000 +#define HWIO_IPA_VMIDMT_NSGFSYNDR1_SSDINDEX_SHFT 0x10 +#define HWIO_IPA_VMIDMT_NSGFSYNDR1_STREAMINDEX_BMSK 0xff +#define HWIO_IPA_VMIDMT_NSGFSYNDR1_STREAMINDEX_SHFT 0x0 + +#define HWIO_IPA_VMIDMT_NSGFSYNDR2_ADDR (IPA_VMIDMT_REG_BASE + 0x00000458) +#define HWIO_IPA_VMIDMT_NSGFSYNDR2_PHYS (IPA_VMIDMT_REG_BASE_PHYS + 0x00000458) +#define HWIO_IPA_VMIDMT_NSGFSYNDR2_OFFS (IPA_VMIDMT_REG_BASE_OFFS + 0x00000458) +#define HWIO_IPA_VMIDMT_NSGFSYNDR2_RMSK 0x1f1fffff +#define HWIO_IPA_VMIDMT_NSGFSYNDR2_ATTR 0x1 +#define HWIO_IPA_VMIDMT_NSGFSYNDR2_IN \ + in_dword_masked(HWIO_IPA_VMIDMT_NSGFSYNDR2_ADDR, HWIO_IPA_VMIDMT_NSGFSYNDR2_RMSK) +#define HWIO_IPA_VMIDMT_NSGFSYNDR2_INM(m) \ + in_dword_masked(HWIO_IPA_VMIDMT_NSGFSYNDR2_ADDR, m) +#define HWIO_IPA_VMIDMT_NSGFSYNDR2_ATID_BMSK 0x1f000000 +#define HWIO_IPA_VMIDMT_NSGFSYNDR2_ATID_SHFT 0x18 +#define HWIO_IPA_VMIDMT_NSGFSYNDR2_AVMID_BMSK 0x1f0000 +#define HWIO_IPA_VMIDMT_NSGFSYNDR2_AVMID_SHFT 0x10 +#define HWIO_IPA_VMIDMT_NSGFSYNDR2_ABID_BMSK 0xe000 +#define HWIO_IPA_VMIDMT_NSGFSYNDR2_ABID_SHFT 0xd +#define HWIO_IPA_VMIDMT_NSGFSYNDR2_APID_BMSK 0x1f00 +#define HWIO_IPA_VMIDMT_NSGFSYNDR2_APID_SHFT 0x8 +#define HWIO_IPA_VMIDMT_NSGFSYNDR2_AMID_BMSK 0xff +#define HWIO_IPA_VMIDMT_NSGFSYNDR2_AMID_SHFT 0x0 + +#define HWIO_IPA_VMIDMT_NSVMIDMTCR0_ADDR (IPA_VMIDMT_REG_BASE + 0x00000490) +#define HWIO_IPA_VMIDMT_NSVMIDMTCR0_PHYS (IPA_VMIDMT_REG_BASE_PHYS + 0x00000490) +#define HWIO_IPA_VMIDMT_NSVMIDMTCR0_OFFS (IPA_VMIDMT_REG_BASE_OFFS + 0x00000490) +#define HWIO_IPA_VMIDMT_NSVMIDMTCR0_RMSK 0x1 +#define HWIO_IPA_VMIDMT_NSVMIDMTCR0_ATTR 0x3 +#define HWIO_IPA_VMIDMT_NSVMIDMTCR0_IN \ + in_dword_masked(HWIO_IPA_VMIDMT_NSVMIDMTCR0_ADDR, HWIO_IPA_VMIDMT_NSVMIDMTCR0_RMSK) +#define HWIO_IPA_VMIDMT_NSVMIDMTCR0_INM(m) \ + in_dword_masked(HWIO_IPA_VMIDMT_NSVMIDMTCR0_ADDR, m) +#define HWIO_IPA_VMIDMT_NSVMIDMTCR0_OUT(v) \ + out_dword(HWIO_IPA_VMIDMT_NSVMIDMTCR0_ADDR,v) +#define HWIO_IPA_VMIDMT_NSVMIDMTCR0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_VMIDMT_NSVMIDMTCR0_ADDR,m,v,HWIO_IPA_VMIDMT_NSVMIDMTCR0_IN) +#define HWIO_IPA_VMIDMT_NSVMIDMTCR0_CLKONOFFE_BMSK 0x1 +#define HWIO_IPA_VMIDMT_NSVMIDMTCR0_CLKONOFFE_SHFT 0x0 + +#define HWIO_IPA_VMIDMT_SSDR0_ADDR (IPA_VMIDMT_REG_BASE + 0x00000080) +#define HWIO_IPA_VMIDMT_SSDR0_PHYS (IPA_VMIDMT_REG_BASE_PHYS + 0x00000080) +#define HWIO_IPA_VMIDMT_SSDR0_OFFS (IPA_VMIDMT_REG_BASE_OFFS + 0x00000080) +#define HWIO_IPA_VMIDMT_SSDR0_RMSK 0xffffffff +#define HWIO_IPA_VMIDMT_SSDR0_ATTR 0x3 +#define HWIO_IPA_VMIDMT_SSDR0_IN \ + in_dword_masked(HWIO_IPA_VMIDMT_SSDR0_ADDR, HWIO_IPA_VMIDMT_SSDR0_RMSK) +#define HWIO_IPA_VMIDMT_SSDR0_INM(m) \ + in_dword_masked(HWIO_IPA_VMIDMT_SSDR0_ADDR, m) +#define HWIO_IPA_VMIDMT_SSDR0_OUT(v) \ + out_dword(HWIO_IPA_VMIDMT_SSDR0_ADDR,v) +#define HWIO_IPA_VMIDMT_SSDR0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_VMIDMT_SSDR0_ADDR,m,v,HWIO_IPA_VMIDMT_SSDR0_IN) +#define HWIO_IPA_VMIDMT_SSDR0_RWE_BMSK 0xffffffff +#define HWIO_IPA_VMIDMT_SSDR0_RWE_SHFT 0x0 + +#define HWIO_IPA_VMIDMT_SSDR1_ADDR (IPA_VMIDMT_REG_BASE + 0x00000084) +#define HWIO_IPA_VMIDMT_SSDR1_PHYS (IPA_VMIDMT_REG_BASE_PHYS + 0x00000084) +#define HWIO_IPA_VMIDMT_SSDR1_OFFS (IPA_VMIDMT_REG_BASE_OFFS + 0x00000084) +#define HWIO_IPA_VMIDMT_SSDR1_RMSK 0xffffffff +#define HWIO_IPA_VMIDMT_SSDR1_ATTR 0x3 +#define HWIO_IPA_VMIDMT_SSDR1_IN \ + in_dword_masked(HWIO_IPA_VMIDMT_SSDR1_ADDR, HWIO_IPA_VMIDMT_SSDR1_RMSK) +#define HWIO_IPA_VMIDMT_SSDR1_INM(m) \ + in_dword_masked(HWIO_IPA_VMIDMT_SSDR1_ADDR, m) +#define HWIO_IPA_VMIDMT_SSDR1_OUT(v) \ + out_dword(HWIO_IPA_VMIDMT_SSDR1_ADDR,v) +#define HWIO_IPA_VMIDMT_SSDR1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_VMIDMT_SSDR1_ADDR,m,v,HWIO_IPA_VMIDMT_SSDR1_IN) +#define HWIO_IPA_VMIDMT_SSDR1_RWE_BMSK 0xffffffff +#define HWIO_IPA_VMIDMT_SSDR1_RWE_SHFT 0x0 + +#define HWIO_IPA_VMIDMT_SSDR2_ADDR (IPA_VMIDMT_REG_BASE + 0x00000088) +#define HWIO_IPA_VMIDMT_SSDR2_PHYS (IPA_VMIDMT_REG_BASE_PHYS + 0x00000088) +#define HWIO_IPA_VMIDMT_SSDR2_OFFS (IPA_VMIDMT_REG_BASE_OFFS + 0x00000088) +#define HWIO_IPA_VMIDMT_SSDR2_RMSK 0xffffffff +#define HWIO_IPA_VMIDMT_SSDR2_ATTR 0x3 +#define HWIO_IPA_VMIDMT_SSDR2_IN \ + in_dword_masked(HWIO_IPA_VMIDMT_SSDR2_ADDR, HWIO_IPA_VMIDMT_SSDR2_RMSK) +#define HWIO_IPA_VMIDMT_SSDR2_INM(m) \ + in_dword_masked(HWIO_IPA_VMIDMT_SSDR2_ADDR, m) +#define HWIO_IPA_VMIDMT_SSDR2_OUT(v) \ + out_dword(HWIO_IPA_VMIDMT_SSDR2_ADDR,v) +#define HWIO_IPA_VMIDMT_SSDR2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_VMIDMT_SSDR2_ADDR,m,v,HWIO_IPA_VMIDMT_SSDR2_IN) +#define HWIO_IPA_VMIDMT_SSDR2_RWE_BMSK 0xffffffff +#define HWIO_IPA_VMIDMT_SSDR2_RWE_SHFT 0x0 + +#define HWIO_IPA_VMIDMT_SSDR3_ADDR (IPA_VMIDMT_REG_BASE + 0x0000008c) +#define HWIO_IPA_VMIDMT_SSDR3_PHYS (IPA_VMIDMT_REG_BASE_PHYS + 0x0000008c) +#define HWIO_IPA_VMIDMT_SSDR3_OFFS (IPA_VMIDMT_REG_BASE_OFFS + 0x0000008c) +#define HWIO_IPA_VMIDMT_SSDR3_RMSK 0xffffffff +#define HWIO_IPA_VMIDMT_SSDR3_ATTR 0x3 +#define HWIO_IPA_VMIDMT_SSDR3_IN \ + in_dword_masked(HWIO_IPA_VMIDMT_SSDR3_ADDR, HWIO_IPA_VMIDMT_SSDR3_RMSK) +#define HWIO_IPA_VMIDMT_SSDR3_INM(m) \ + in_dword_masked(HWIO_IPA_VMIDMT_SSDR3_ADDR, m) +#define HWIO_IPA_VMIDMT_SSDR3_OUT(v) \ + out_dword(HWIO_IPA_VMIDMT_SSDR3_ADDR,v) +#define HWIO_IPA_VMIDMT_SSDR3_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_VMIDMT_SSDR3_ADDR,m,v,HWIO_IPA_VMIDMT_SSDR3_IN) +#define HWIO_IPA_VMIDMT_SSDR3_RWE_BMSK 0xffffffff +#define HWIO_IPA_VMIDMT_SSDR3_RWE_SHFT 0x0 + +#define HWIO_IPA_VMIDMT_MSDR0_ADDR (IPA_VMIDMT_REG_BASE + 0x00000480) +#define HWIO_IPA_VMIDMT_MSDR0_PHYS (IPA_VMIDMT_REG_BASE_PHYS + 0x00000480) +#define HWIO_IPA_VMIDMT_MSDR0_OFFS (IPA_VMIDMT_REG_BASE_OFFS + 0x00000480) +#define HWIO_IPA_VMIDMT_MSDR0_RMSK 0xffffffff +#define HWIO_IPA_VMIDMT_MSDR0_ATTR 0x3 +#define HWIO_IPA_VMIDMT_MSDR0_IN \ + in_dword_masked(HWIO_IPA_VMIDMT_MSDR0_ADDR, HWIO_IPA_VMIDMT_MSDR0_RMSK) +#define HWIO_IPA_VMIDMT_MSDR0_INM(m) \ + in_dword_masked(HWIO_IPA_VMIDMT_MSDR0_ADDR, m) +#define HWIO_IPA_VMIDMT_MSDR0_OUT(v) \ + out_dword(HWIO_IPA_VMIDMT_MSDR0_ADDR,v) +#define HWIO_IPA_VMIDMT_MSDR0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_VMIDMT_MSDR0_ADDR,m,v,HWIO_IPA_VMIDMT_MSDR0_IN) +#define HWIO_IPA_VMIDMT_MSDR0_RWE_BMSK 0xffffffff +#define HWIO_IPA_VMIDMT_MSDR0_RWE_SHFT 0x0 + +#define HWIO_IPA_VMIDMT_MSDR1_ADDR (IPA_VMIDMT_REG_BASE + 0x00000484) +#define HWIO_IPA_VMIDMT_MSDR1_PHYS (IPA_VMIDMT_REG_BASE_PHYS + 0x00000484) +#define HWIO_IPA_VMIDMT_MSDR1_OFFS (IPA_VMIDMT_REG_BASE_OFFS + 0x00000484) +#define HWIO_IPA_VMIDMT_MSDR1_RMSK 0xffffffff +#define HWIO_IPA_VMIDMT_MSDR1_ATTR 0x3 +#define HWIO_IPA_VMIDMT_MSDR1_IN \ + in_dword_masked(HWIO_IPA_VMIDMT_MSDR1_ADDR, HWIO_IPA_VMIDMT_MSDR1_RMSK) +#define HWIO_IPA_VMIDMT_MSDR1_INM(m) \ + in_dword_masked(HWIO_IPA_VMIDMT_MSDR1_ADDR, m) +#define HWIO_IPA_VMIDMT_MSDR1_OUT(v) \ + out_dword(HWIO_IPA_VMIDMT_MSDR1_ADDR,v) +#define HWIO_IPA_VMIDMT_MSDR1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_VMIDMT_MSDR1_ADDR,m,v,HWIO_IPA_VMIDMT_MSDR1_IN) +#define HWIO_IPA_VMIDMT_MSDR1_RWE_BMSK 0xffffffff +#define HWIO_IPA_VMIDMT_MSDR1_RWE_SHFT 0x0 + +#define HWIO_IPA_VMIDMT_MSDR2_ADDR (IPA_VMIDMT_REG_BASE + 0x00000488) +#define HWIO_IPA_VMIDMT_MSDR2_PHYS (IPA_VMIDMT_REG_BASE_PHYS + 0x00000488) +#define HWIO_IPA_VMIDMT_MSDR2_OFFS (IPA_VMIDMT_REG_BASE_OFFS + 0x00000488) +#define HWIO_IPA_VMIDMT_MSDR2_RMSK 0xffffffff +#define HWIO_IPA_VMIDMT_MSDR2_ATTR 0x3 +#define HWIO_IPA_VMIDMT_MSDR2_IN \ + in_dword_masked(HWIO_IPA_VMIDMT_MSDR2_ADDR, HWIO_IPA_VMIDMT_MSDR2_RMSK) +#define HWIO_IPA_VMIDMT_MSDR2_INM(m) \ + in_dword_masked(HWIO_IPA_VMIDMT_MSDR2_ADDR, m) +#define HWIO_IPA_VMIDMT_MSDR2_OUT(v) \ + out_dword(HWIO_IPA_VMIDMT_MSDR2_ADDR,v) +#define HWIO_IPA_VMIDMT_MSDR2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_VMIDMT_MSDR2_ADDR,m,v,HWIO_IPA_VMIDMT_MSDR2_IN) +#define HWIO_IPA_VMIDMT_MSDR2_RWE_BMSK 0xffffffff +#define HWIO_IPA_VMIDMT_MSDR2_RWE_SHFT 0x0 + +#define HWIO_IPA_VMIDMT_MSDR3_ADDR (IPA_VMIDMT_REG_BASE + 0x0000048c) +#define HWIO_IPA_VMIDMT_MSDR3_PHYS (IPA_VMIDMT_REG_BASE_PHYS + 0x0000048c) +#define HWIO_IPA_VMIDMT_MSDR3_OFFS (IPA_VMIDMT_REG_BASE_OFFS + 0x0000048c) +#define HWIO_IPA_VMIDMT_MSDR3_RMSK 0xffffffff +#define HWIO_IPA_VMIDMT_MSDR3_ATTR 0x3 +#define HWIO_IPA_VMIDMT_MSDR3_IN \ + in_dword_masked(HWIO_IPA_VMIDMT_MSDR3_ADDR, HWIO_IPA_VMIDMT_MSDR3_RMSK) +#define HWIO_IPA_VMIDMT_MSDR3_INM(m) \ + in_dword_masked(HWIO_IPA_VMIDMT_MSDR3_ADDR, m) +#define HWIO_IPA_VMIDMT_MSDR3_OUT(v) \ + out_dword(HWIO_IPA_VMIDMT_MSDR3_ADDR,v) +#define HWIO_IPA_VMIDMT_MSDR3_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_VMIDMT_MSDR3_ADDR,m,v,HWIO_IPA_VMIDMT_MSDR3_IN) +#define HWIO_IPA_VMIDMT_MSDR3_RWE_BMSK 0xffffffff +#define HWIO_IPA_VMIDMT_MSDR3_RWE_SHFT 0x0 + +#define HWIO_IPA_VMIDMT_MCR_ADDR (IPA_VMIDMT_REG_BASE + 0x00000494) +#define HWIO_IPA_VMIDMT_MCR_PHYS (IPA_VMIDMT_REG_BASE_PHYS + 0x00000494) +#define HWIO_IPA_VMIDMT_MCR_OFFS (IPA_VMIDMT_REG_BASE_OFFS + 0x00000494) +#define HWIO_IPA_VMIDMT_MCR_RMSK 0x7 +#define HWIO_IPA_VMIDMT_MCR_ATTR 0x3 +#define HWIO_IPA_VMIDMT_MCR_IN \ + in_dword_masked(HWIO_IPA_VMIDMT_MCR_ADDR, HWIO_IPA_VMIDMT_MCR_RMSK) +#define HWIO_IPA_VMIDMT_MCR_INM(m) \ + in_dword_masked(HWIO_IPA_VMIDMT_MCR_ADDR, m) +#define HWIO_IPA_VMIDMT_MCR_OUT(v) \ + out_dword(HWIO_IPA_VMIDMT_MCR_ADDR,v) +#define HWIO_IPA_VMIDMT_MCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_VMIDMT_MCR_ADDR,m,v,HWIO_IPA_VMIDMT_MCR_IN) +#define HWIO_IPA_VMIDMT_MCR_CLKONOFFE_BMSK 0x4 +#define HWIO_IPA_VMIDMT_MCR_CLKONOFFE_SHFT 0x2 +#define HWIO_IPA_VMIDMT_MCR_BPMSACFG_BMSK 0x2 +#define HWIO_IPA_VMIDMT_MCR_BPMSACFG_SHFT 0x1 +#define HWIO_IPA_VMIDMT_MCR_BPSMSACFG_BMSK 0x1 +#define HWIO_IPA_VMIDMT_MCR_BPSMSACFG_SHFT 0x0 + +#define HWIO_IPA_VMIDMT_S2VRn_ADDR(n) (IPA_VMIDMT_REG_BASE + 0x00000c00 + 0x4 * (n)) +#define HWIO_IPA_VMIDMT_S2VRn_PHYS(n) (IPA_VMIDMT_REG_BASE_PHYS + 0x00000c00 + 0x4 * (n)) +#define HWIO_IPA_VMIDMT_S2VRn_OFFS(n) (IPA_VMIDMT_REG_BASE_OFFS + 0x00000c00 + 0x4 * (n)) +#define HWIO_IPA_VMIDMT_S2VRn_RMSK 0x30ff7b1f +#define HWIO_IPA_VMIDMT_S2VRn_MAXn 47 +#define HWIO_IPA_VMIDMT_S2VRn_ATTR 0x3 +#define HWIO_IPA_VMIDMT_S2VRn_INI(n) \ + in_dword_masked(HWIO_IPA_VMIDMT_S2VRn_ADDR(n), HWIO_IPA_VMIDMT_S2VRn_RMSK) +#define HWIO_IPA_VMIDMT_S2VRn_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_VMIDMT_S2VRn_ADDR(n), mask) +#define HWIO_IPA_VMIDMT_S2VRn_OUTI(n,val) \ + out_dword(HWIO_IPA_VMIDMT_S2VRn_ADDR(n),val) +#define HWIO_IPA_VMIDMT_S2VRn_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_VMIDMT_S2VRn_ADDR(n),mask,val,HWIO_IPA_VMIDMT_S2VRn_INI(n)) +#define HWIO_IPA_VMIDMT_S2VRn_TRANSIENTCFG_BMSK 0x30000000 +#define HWIO_IPA_VMIDMT_S2VRn_TRANSIENTCFG_SHFT 0x1c +#define HWIO_IPA_VMIDMT_S2VRn_WACFG_BMSK 0xc00000 +#define HWIO_IPA_VMIDMT_S2VRn_WACFG_SHFT 0x16 +#define HWIO_IPA_VMIDMT_S2VRn_RACFG_BMSK 0x300000 +#define HWIO_IPA_VMIDMT_S2VRn_RACFG_SHFT 0x14 +#define HWIO_IPA_VMIDMT_S2VRn_NSCFG_BMSK 0xc0000 +#define HWIO_IPA_VMIDMT_S2VRn_NSCFG_SHFT 0x12 +#define HWIO_IPA_VMIDMT_S2VRn_TYPE_BMSK 0x30000 +#define HWIO_IPA_VMIDMT_S2VRn_TYPE_SHFT 0x10 +#define HWIO_IPA_VMIDMT_S2VRn_MEMATTR_BMSK 0x7000 +#define HWIO_IPA_VMIDMT_S2VRn_MEMATTR_SHFT 0xc +#define HWIO_IPA_VMIDMT_S2VRn_MTCFG_BMSK 0x800 +#define HWIO_IPA_VMIDMT_S2VRn_MTCFG_SHFT 0xb +#define HWIO_IPA_VMIDMT_S2VRn_SHCFG_BMSK 0x300 +#define HWIO_IPA_VMIDMT_S2VRn_SHCFG_SHFT 0x8 +#define HWIO_IPA_VMIDMT_S2VRn_VMID_BMSK 0x1f +#define HWIO_IPA_VMIDMT_S2VRn_VMID_SHFT 0x0 + +#define HWIO_IPA_VMIDMT_AS2VRn_ADDR(n) (IPA_VMIDMT_REG_BASE + 0x00000e00 + 0x4 * (n)) +#define HWIO_IPA_VMIDMT_AS2VRn_PHYS(n) (IPA_VMIDMT_REG_BASE_PHYS + 0x00000e00 + 0x4 * (n)) +#define HWIO_IPA_VMIDMT_AS2VRn_OFFS(n) (IPA_VMIDMT_REG_BASE_OFFS + 0x00000e00 + 0x4 * (n)) +#define HWIO_IPA_VMIDMT_AS2VRn_RMSK 0x70000013 +#define HWIO_IPA_VMIDMT_AS2VRn_MAXn 47 +#define HWIO_IPA_VMIDMT_AS2VRn_ATTR 0x3 +#define HWIO_IPA_VMIDMT_AS2VRn_INI(n) \ + in_dword_masked(HWIO_IPA_VMIDMT_AS2VRn_ADDR(n), HWIO_IPA_VMIDMT_AS2VRn_RMSK) +#define HWIO_IPA_VMIDMT_AS2VRn_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_VMIDMT_AS2VRn_ADDR(n), mask) +#define HWIO_IPA_VMIDMT_AS2VRn_OUTI(n,val) \ + out_dword(HWIO_IPA_VMIDMT_AS2VRn_ADDR(n),val) +#define HWIO_IPA_VMIDMT_AS2VRn_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_VMIDMT_AS2VRn_ADDR(n),mask,val,HWIO_IPA_VMIDMT_AS2VRn_INI(n)) +#define HWIO_IPA_VMIDMT_AS2VRn_RCNSH_BMSK 0x40000000 +#define HWIO_IPA_VMIDMT_AS2VRn_RCNSH_SHFT 0x1e +#define HWIO_IPA_VMIDMT_AS2VRn_RCISH_BMSK 0x20000000 +#define HWIO_IPA_VMIDMT_AS2VRn_RCISH_SHFT 0x1d +#define HWIO_IPA_VMIDMT_AS2VRn_RCOSH_BMSK 0x10000000 +#define HWIO_IPA_VMIDMT_AS2VRn_RCOSH_SHFT 0x1c +#define HWIO_IPA_VMIDMT_AS2VRn_REQPRIORITYCFG_BMSK 0x10 +#define HWIO_IPA_VMIDMT_AS2VRn_REQPRIORITYCFG_SHFT 0x4 +#define HWIO_IPA_VMIDMT_AS2VRn_REQPRIORITY_BMSK 0x3 +#define HWIO_IPA_VMIDMT_AS2VRn_REQPRIORITY_SHFT 0x0 + +#define HWIO_IPA_VMIDMT_SMRn_ADDR(n) (IPA_VMIDMT_REG_BASE + 0x00000800 + 0x4 * (n)) +#define HWIO_IPA_VMIDMT_SMRn_PHYS(n) (IPA_VMIDMT_REG_BASE_PHYS + 0x00000800 + 0x4 * (n)) +#define HWIO_IPA_VMIDMT_SMRn_OFFS(n) (IPA_VMIDMT_REG_BASE_OFFS + 0x00000800 + 0x4 * (n)) +#define HWIO_IPA_VMIDMT_SMRn_RMSK 0x80ff00ff +#define HWIO_IPA_VMIDMT_SMRn_MAXn 47 +#define HWIO_IPA_VMIDMT_SMRn_ATTR 0x3 +#define HWIO_IPA_VMIDMT_SMRn_INI(n) \ + in_dword_masked(HWIO_IPA_VMIDMT_SMRn_ADDR(n), HWIO_IPA_VMIDMT_SMRn_RMSK) +#define HWIO_IPA_VMIDMT_SMRn_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_VMIDMT_SMRn_ADDR(n), mask) +#define HWIO_IPA_VMIDMT_SMRn_OUTI(n,val) \ + out_dword(HWIO_IPA_VMIDMT_SMRn_ADDR(n),val) +#define HWIO_IPA_VMIDMT_SMRn_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_VMIDMT_SMRn_ADDR(n),mask,val,HWIO_IPA_VMIDMT_SMRn_INI(n)) +#define HWIO_IPA_VMIDMT_SMRn_VALID_BMSK 0x80000000 +#define HWIO_IPA_VMIDMT_SMRn_VALID_SHFT 0x1f +#define HWIO_IPA_VMIDMT_SMRn_MASK_BMSK 0xff0000 +#define HWIO_IPA_VMIDMT_SMRn_MASK_SHFT 0x10 +#define HWIO_IPA_VMIDMT_SMRn_ID_BMSK 0xff +#define HWIO_IPA_VMIDMT_SMRn_ID_SHFT 0x0 + +/*---------------------------------------------------------------------------- + * MODULE: IPA_0_GSI_TOP + *--------------------------------------------------------------------------*/ + +#define IPA_0_GSI_TOP_REG_BASE (IPA_0_IPA_WRAPPER_BASE + 0x00000000) +#define IPA_0_GSI_TOP_REG_BASE_PHYS (IPA_0_IPA_WRAPPER_BASE_PHYS + 0x00000000) +#define IPA_0_GSI_TOP_REG_BASE_OFFS 0x00000000 + +/*---------------------------------------------------------------------------- + * MODULE: IPA_GSI_TOP_GSI + *--------------------------------------------------------------------------*/ + +#define IPA_GSI_TOP_GSI_REG_BASE (IPA_0_IPA_WRAPPER_BASE + 0x00004000) +#define IPA_GSI_TOP_GSI_REG_BASE_PHYS (IPA_0_IPA_WRAPPER_BASE_PHYS + 0x00004000) +#define IPA_GSI_TOP_GSI_REG_BASE_OFFS 0x00004000 + +#define HWIO_IPA_GSI_TOP_GSI_CFG_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00000000) +#define HWIO_IPA_GSI_TOP_GSI_CFG_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000000) +#define HWIO_IPA_GSI_TOP_GSI_CFG_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000000) +#define HWIO_IPA_GSI_TOP_GSI_CFG_RMSK 0xf3f +#define HWIO_IPA_GSI_TOP_GSI_CFG_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_CFG_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_CFG_ADDR, HWIO_IPA_GSI_TOP_GSI_CFG_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_CFG_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_CFG_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_CFG_ADDR,v) +#define HWIO_IPA_GSI_TOP_GSI_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_CFG_ADDR,m,v,HWIO_IPA_GSI_TOP_GSI_CFG_IN) +#define HWIO_IPA_GSI_TOP_GSI_CFG_SLEEP_CLK_DIV_BMSK 0xf00 +#define HWIO_IPA_GSI_TOP_GSI_CFG_SLEEP_CLK_DIV_SHFT 0x8 +#define HWIO_IPA_GSI_TOP_GSI_CFG_BP_MTRIX_DISABLE_BMSK 0x20 +#define HWIO_IPA_GSI_TOP_GSI_CFG_BP_MTRIX_DISABLE_SHFT 0x5 +#define HWIO_IPA_GSI_TOP_GSI_CFG_GSI_PWR_CLPS_BMSK 0x10 +#define HWIO_IPA_GSI_TOP_GSI_CFG_GSI_PWR_CLPS_SHFT 0x4 +#define HWIO_IPA_GSI_TOP_GSI_CFG_UC_IS_MCS_BMSK 0x8 +#define HWIO_IPA_GSI_TOP_GSI_CFG_UC_IS_MCS_SHFT 0x3 +#define HWIO_IPA_GSI_TOP_GSI_CFG_DOUBLE_MCS_CLK_FREQ_BMSK 0x4 +#define HWIO_IPA_GSI_TOP_GSI_CFG_DOUBLE_MCS_CLK_FREQ_SHFT 0x2 +#define HWIO_IPA_GSI_TOP_GSI_CFG_MCS_ENABLE_BMSK 0x2 +#define HWIO_IPA_GSI_TOP_GSI_CFG_MCS_ENABLE_SHFT 0x1 +#define HWIO_IPA_GSI_TOP_GSI_CFG_GSI_ENABLE_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_GSI_CFG_GSI_ENABLE_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_MCS_CODE_VER_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00000008) +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_MCS_CODE_VER_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000008) +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_MCS_CODE_VER_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000008) +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_MCS_CODE_VER_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_MCS_CODE_VER_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_MCS_CODE_VER_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_MANAGER_MCS_CODE_VER_ADDR, HWIO_IPA_GSI_TOP_GSI_MANAGER_MCS_CODE_VER_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_MCS_CODE_VER_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_MANAGER_MCS_CODE_VER_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_MCS_CODE_VER_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_MANAGER_MCS_CODE_VER_ADDR,v) +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_MCS_CODE_VER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_MANAGER_MCS_CODE_VER_ADDR,m,v,HWIO_IPA_GSI_TOP_GSI_MANAGER_MCS_CODE_VER_IN) +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_MCS_CODE_VER_VER_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_MCS_CODE_VER_VER_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_ZEROS_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00000010) +#define HWIO_IPA_GSI_TOP_GSI_ZEROS_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000010) +#define HWIO_IPA_GSI_TOP_GSI_ZEROS_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000010) +#define HWIO_IPA_GSI_TOP_GSI_ZEROS_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_ZEROS_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_GSI_ZEROS_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_ZEROS_ADDR, HWIO_IPA_GSI_TOP_GSI_ZEROS_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_ZEROS_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_ZEROS_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_ZEROS_ZEROS_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_ZEROS_ZEROS_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_PERIPH_BASE_ADDR_LSB_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00000018) +#define HWIO_IPA_GSI_TOP_GSI_PERIPH_BASE_ADDR_LSB_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000018) +#define HWIO_IPA_GSI_TOP_GSI_PERIPH_BASE_ADDR_LSB_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000018) +#define HWIO_IPA_GSI_TOP_GSI_PERIPH_BASE_ADDR_LSB_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_PERIPH_BASE_ADDR_LSB_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_PERIPH_BASE_ADDR_LSB_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_PERIPH_BASE_ADDR_LSB_ADDR, HWIO_IPA_GSI_TOP_GSI_PERIPH_BASE_ADDR_LSB_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_PERIPH_BASE_ADDR_LSB_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_PERIPH_BASE_ADDR_LSB_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_PERIPH_BASE_ADDR_LSB_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_PERIPH_BASE_ADDR_LSB_ADDR,v) +#define HWIO_IPA_GSI_TOP_GSI_PERIPH_BASE_ADDR_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_PERIPH_BASE_ADDR_LSB_ADDR,m,v,HWIO_IPA_GSI_TOP_GSI_PERIPH_BASE_ADDR_LSB_IN) +#define HWIO_IPA_GSI_TOP_GSI_PERIPH_BASE_ADDR_LSB_BASE_ADDR_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_PERIPH_BASE_ADDR_LSB_BASE_ADDR_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_PERIPH_BASE_ADDR_MSB_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x0000001c) +#define HWIO_IPA_GSI_TOP_GSI_PERIPH_BASE_ADDR_MSB_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000001c) +#define HWIO_IPA_GSI_TOP_GSI_PERIPH_BASE_ADDR_MSB_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000001c) +#define HWIO_IPA_GSI_TOP_GSI_PERIPH_BASE_ADDR_MSB_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_PERIPH_BASE_ADDR_MSB_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_PERIPH_BASE_ADDR_MSB_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_PERIPH_BASE_ADDR_MSB_ADDR, HWIO_IPA_GSI_TOP_GSI_PERIPH_BASE_ADDR_MSB_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_PERIPH_BASE_ADDR_MSB_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_PERIPH_BASE_ADDR_MSB_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_PERIPH_BASE_ADDR_MSB_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_PERIPH_BASE_ADDR_MSB_ADDR,v) +#define HWIO_IPA_GSI_TOP_GSI_PERIPH_BASE_ADDR_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_PERIPH_BASE_ADDR_MSB_ADDR,m,v,HWIO_IPA_GSI_TOP_GSI_PERIPH_BASE_ADDR_MSB_IN) +#define HWIO_IPA_GSI_TOP_GSI_PERIPH_BASE_ADDR_MSB_BASE_ADDR_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_PERIPH_BASE_ADDR_MSB_BASE_ADDR_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_CGC_CTRL_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00000020) +#define HWIO_IPA_GSI_TOP_GSI_CGC_CTRL_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000020) +#define HWIO_IPA_GSI_TOP_GSI_CGC_CTRL_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000020) +#define HWIO_IPA_GSI_TOP_GSI_CGC_CTRL_RMSK 0xffff +#define HWIO_IPA_GSI_TOP_GSI_CGC_CTRL_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_CGC_CTRL_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_CGC_CTRL_ADDR, HWIO_IPA_GSI_TOP_GSI_CGC_CTRL_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_CGC_CTRL_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_CGC_CTRL_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_CGC_CTRL_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_CGC_CTRL_ADDR,v) +#define HWIO_IPA_GSI_TOP_GSI_CGC_CTRL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_CGC_CTRL_ADDR,m,v,HWIO_IPA_GSI_TOP_GSI_CGC_CTRL_IN) +#define HWIO_IPA_GSI_TOP_GSI_CGC_CTRL_REGION_16_HW_CGC_EN_BMSK 0x8000 +#define HWIO_IPA_GSI_TOP_GSI_CGC_CTRL_REGION_16_HW_CGC_EN_SHFT 0xf +#define HWIO_IPA_GSI_TOP_GSI_CGC_CTRL_REGION_15_HW_CGC_EN_BMSK 0x4000 +#define HWIO_IPA_GSI_TOP_GSI_CGC_CTRL_REGION_15_HW_CGC_EN_SHFT 0xe +#define HWIO_IPA_GSI_TOP_GSI_CGC_CTRL_REGION_14_HW_CGC_EN_BMSK 0x2000 +#define HWIO_IPA_GSI_TOP_GSI_CGC_CTRL_REGION_14_HW_CGC_EN_SHFT 0xd +#define HWIO_IPA_GSI_TOP_GSI_CGC_CTRL_REGION_13_HW_CGC_EN_BMSK 0x1000 +#define HWIO_IPA_GSI_TOP_GSI_CGC_CTRL_REGION_13_HW_CGC_EN_SHFT 0xc +#define HWIO_IPA_GSI_TOP_GSI_CGC_CTRL_REGION_12_HW_CGC_EN_BMSK 0x800 +#define HWIO_IPA_GSI_TOP_GSI_CGC_CTRL_REGION_12_HW_CGC_EN_SHFT 0xb +#define HWIO_IPA_GSI_TOP_GSI_CGC_CTRL_REGION_11_HW_CGC_EN_BMSK 0x400 +#define HWIO_IPA_GSI_TOP_GSI_CGC_CTRL_REGION_11_HW_CGC_EN_SHFT 0xa +#define HWIO_IPA_GSI_TOP_GSI_CGC_CTRL_REGION_10_HW_CGC_EN_BMSK 0x200 +#define HWIO_IPA_GSI_TOP_GSI_CGC_CTRL_REGION_10_HW_CGC_EN_SHFT 0x9 +#define HWIO_IPA_GSI_TOP_GSI_CGC_CTRL_REGION_9_HW_CGC_EN_BMSK 0x100 +#define HWIO_IPA_GSI_TOP_GSI_CGC_CTRL_REGION_9_HW_CGC_EN_SHFT 0x8 +#define HWIO_IPA_GSI_TOP_GSI_CGC_CTRL_REGION_8_HW_CGC_EN_BMSK 0x80 +#define HWIO_IPA_GSI_TOP_GSI_CGC_CTRL_REGION_8_HW_CGC_EN_SHFT 0x7 +#define HWIO_IPA_GSI_TOP_GSI_CGC_CTRL_REGION_7_HW_CGC_EN_BMSK 0x40 +#define HWIO_IPA_GSI_TOP_GSI_CGC_CTRL_REGION_7_HW_CGC_EN_SHFT 0x6 +#define HWIO_IPA_GSI_TOP_GSI_CGC_CTRL_REGION_6_HW_CGC_EN_BMSK 0x20 +#define HWIO_IPA_GSI_TOP_GSI_CGC_CTRL_REGION_6_HW_CGC_EN_SHFT 0x5 +#define HWIO_IPA_GSI_TOP_GSI_CGC_CTRL_REGION_5_HW_CGC_EN_BMSK 0x10 +#define HWIO_IPA_GSI_TOP_GSI_CGC_CTRL_REGION_5_HW_CGC_EN_SHFT 0x4 +#define HWIO_IPA_GSI_TOP_GSI_CGC_CTRL_REGION_4_HW_CGC_EN_BMSK 0x8 +#define HWIO_IPA_GSI_TOP_GSI_CGC_CTRL_REGION_4_HW_CGC_EN_SHFT 0x3 +#define HWIO_IPA_GSI_TOP_GSI_CGC_CTRL_REGION_3_HW_CGC_EN_BMSK 0x4 +#define HWIO_IPA_GSI_TOP_GSI_CGC_CTRL_REGION_3_HW_CGC_EN_SHFT 0x2 +#define HWIO_IPA_GSI_TOP_GSI_CGC_CTRL_REGION_2_HW_CGC_EN_BMSK 0x2 +#define HWIO_IPA_GSI_TOP_GSI_CGC_CTRL_REGION_2_HW_CGC_EN_SHFT 0x1 +#define HWIO_IPA_GSI_TOP_GSI_CGC_CTRL_REGION_1_HW_CGC_EN_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_GSI_CGC_CTRL_REGION_1_HW_CGC_EN_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_MOQA_CFG_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00000030) +#define HWIO_IPA_GSI_TOP_GSI_MOQA_CFG_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000030) +#define HWIO_IPA_GSI_TOP_GSI_MOQA_CFG_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000030) +#define HWIO_IPA_GSI_TOP_GSI_MOQA_CFG_RMSK 0xffffff +#define HWIO_IPA_GSI_TOP_GSI_MOQA_CFG_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_MOQA_CFG_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_MOQA_CFG_ADDR, HWIO_IPA_GSI_TOP_GSI_MOQA_CFG_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_MOQA_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_MOQA_CFG_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_MOQA_CFG_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_MOQA_CFG_ADDR,v) +#define HWIO_IPA_GSI_TOP_GSI_MOQA_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_MOQA_CFG_ADDR,m,v,HWIO_IPA_GSI_TOP_GSI_MOQA_CFG_IN) +#define HWIO_IPA_GSI_TOP_GSI_MOQA_CFG_CLIENT_OOWR_BMSK 0xff0000 +#define HWIO_IPA_GSI_TOP_GSI_MOQA_CFG_CLIENT_OOWR_SHFT 0x10 +#define HWIO_IPA_GSI_TOP_GSI_MOQA_CFG_CLIENT_OORD_BMSK 0xff00 +#define HWIO_IPA_GSI_TOP_GSI_MOQA_CFG_CLIENT_OORD_SHFT 0x8 +#define HWIO_IPA_GSI_TOP_GSI_MOQA_CFG_CLIENT_REQ_PRIO_BMSK 0xff +#define HWIO_IPA_GSI_TOP_GSI_MOQA_CFG_CLIENT_REQ_PRIO_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_REE_CFG_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00000038) +#define HWIO_IPA_GSI_TOP_GSI_REE_CFG_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000038) +#define HWIO_IPA_GSI_TOP_GSI_REE_CFG_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000038) +#define HWIO_IPA_GSI_TOP_GSI_REE_CFG_RMSK 0xff03 +#define HWIO_IPA_GSI_TOP_GSI_REE_CFG_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_REE_CFG_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_REE_CFG_ADDR, HWIO_IPA_GSI_TOP_GSI_REE_CFG_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_REE_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_REE_CFG_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_REE_CFG_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_REE_CFG_ADDR,v) +#define HWIO_IPA_GSI_TOP_GSI_REE_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_REE_CFG_ADDR,m,v,HWIO_IPA_GSI_TOP_GSI_REE_CFG_IN) +#define HWIO_IPA_GSI_TOP_GSI_REE_CFG_MAX_BURST_SIZE_BMSK 0xff00 +#define HWIO_IPA_GSI_TOP_GSI_REE_CFG_MAX_BURST_SIZE_SHFT 0x8 +#define HWIO_IPA_GSI_TOP_GSI_REE_CFG_CHANNEL_EMPTY_INT_ENABLE_BMSK 0x2 +#define HWIO_IPA_GSI_TOP_GSI_REE_CFG_CHANNEL_EMPTY_INT_ENABLE_SHFT 0x1 +#define HWIO_IPA_GSI_TOP_GSI_REE_CFG_MOVE_TO_ESC_CLR_MODE_TRSH_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_GSI_REE_CFG_MOVE_TO_ESC_CLR_MODE_TRSH_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_PERIPH_PENDING_k_ADDR(k) (IPA_GSI_TOP_GSI_REG_BASE + 0x00000060 + 0x4 * (k)) +#define HWIO_IPA_GSI_TOP_GSI_PERIPH_PENDING_k_PHYS(k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000060 + 0x4 * (k)) +#define HWIO_IPA_GSI_TOP_GSI_PERIPH_PENDING_k_OFFS(k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000060 + 0x4 * (k)) +#define HWIO_IPA_GSI_TOP_GSI_PERIPH_PENDING_k_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_PERIPH_PENDING_k_MAXk 1 +#define HWIO_IPA_GSI_TOP_GSI_PERIPH_PENDING_k_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_GSI_PERIPH_PENDING_k_INI(k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_PERIPH_PENDING_k_ADDR(k), HWIO_IPA_GSI_TOP_GSI_PERIPH_PENDING_k_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_PERIPH_PENDING_k_INMI(k,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_PERIPH_PENDING_k_ADDR(k), mask) +#define HWIO_IPA_GSI_TOP_GSI_PERIPH_PENDING_k_CHID_BIT_MAP_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_PERIPH_PENDING_k_CHID_BIT_MAP_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_MSI_CACHEATTR_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00000080) +#define HWIO_IPA_GSI_TOP_GSI_MSI_CACHEATTR_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000080) +#define HWIO_IPA_GSI_TOP_GSI_MSI_CACHEATTR_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000080) +#define HWIO_IPA_GSI_TOP_GSI_MSI_CACHEATTR_RMSK 0x3f +#define HWIO_IPA_GSI_TOP_GSI_MSI_CACHEATTR_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_MSI_CACHEATTR_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_MSI_CACHEATTR_ADDR, HWIO_IPA_GSI_TOP_GSI_MSI_CACHEATTR_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_MSI_CACHEATTR_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_MSI_CACHEATTR_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_MSI_CACHEATTR_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_MSI_CACHEATTR_ADDR,v) +#define HWIO_IPA_GSI_TOP_GSI_MSI_CACHEATTR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_MSI_CACHEATTR_ADDR,m,v,HWIO_IPA_GSI_TOP_GSI_MSI_CACHEATTR_IN) +#define HWIO_IPA_GSI_TOP_GSI_MSI_CACHEATTR_AREQPRIORITY_BMSK 0x30 +#define HWIO_IPA_GSI_TOP_GSI_MSI_CACHEATTR_AREQPRIORITY_SHFT 0x4 +#define HWIO_IPA_GSI_TOP_GSI_MSI_CACHEATTR_ATRANSIENT_BMSK 0x8 +#define HWIO_IPA_GSI_TOP_GSI_MSI_CACHEATTR_ATRANSIENT_SHFT 0x3 +#define HWIO_IPA_GSI_TOP_GSI_MSI_CACHEATTR_ANOALLOCATE_BMSK 0x4 +#define HWIO_IPA_GSI_TOP_GSI_MSI_CACHEATTR_ANOALLOCATE_SHFT 0x2 +#define HWIO_IPA_GSI_TOP_GSI_MSI_CACHEATTR_AINNERSHARED_BMSK 0x2 +#define HWIO_IPA_GSI_TOP_GSI_MSI_CACHEATTR_AINNERSHARED_SHFT 0x1 +#define HWIO_IPA_GSI_TOP_GSI_MSI_CACHEATTR_ASHARED_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_GSI_MSI_CACHEATTR_ASHARED_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_EVENT_CACHEATTR_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00000084) +#define HWIO_IPA_GSI_TOP_GSI_EVENT_CACHEATTR_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000084) +#define HWIO_IPA_GSI_TOP_GSI_EVENT_CACHEATTR_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000084) +#define HWIO_IPA_GSI_TOP_GSI_EVENT_CACHEATTR_RMSK 0x3f +#define HWIO_IPA_GSI_TOP_GSI_EVENT_CACHEATTR_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_EVENT_CACHEATTR_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_EVENT_CACHEATTR_ADDR, HWIO_IPA_GSI_TOP_GSI_EVENT_CACHEATTR_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_EVENT_CACHEATTR_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_EVENT_CACHEATTR_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_EVENT_CACHEATTR_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_EVENT_CACHEATTR_ADDR,v) +#define HWIO_IPA_GSI_TOP_GSI_EVENT_CACHEATTR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_EVENT_CACHEATTR_ADDR,m,v,HWIO_IPA_GSI_TOP_GSI_EVENT_CACHEATTR_IN) +#define HWIO_IPA_GSI_TOP_GSI_EVENT_CACHEATTR_AREQPRIORITY_BMSK 0x30 +#define HWIO_IPA_GSI_TOP_GSI_EVENT_CACHEATTR_AREQPRIORITY_SHFT 0x4 +#define HWIO_IPA_GSI_TOP_GSI_EVENT_CACHEATTR_ATRANSIENT_BMSK 0x8 +#define HWIO_IPA_GSI_TOP_GSI_EVENT_CACHEATTR_ATRANSIENT_SHFT 0x3 +#define HWIO_IPA_GSI_TOP_GSI_EVENT_CACHEATTR_ANOALLOCATE_BMSK 0x4 +#define HWIO_IPA_GSI_TOP_GSI_EVENT_CACHEATTR_ANOALLOCATE_SHFT 0x2 +#define HWIO_IPA_GSI_TOP_GSI_EVENT_CACHEATTR_AINNERSHARED_BMSK 0x2 +#define HWIO_IPA_GSI_TOP_GSI_EVENT_CACHEATTR_AINNERSHARED_SHFT 0x1 +#define HWIO_IPA_GSI_TOP_GSI_EVENT_CACHEATTR_ASHARED_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_GSI_EVENT_CACHEATTR_ASHARED_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_DATA_CACHEATTR_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00000088) +#define HWIO_IPA_GSI_TOP_GSI_DATA_CACHEATTR_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000088) +#define HWIO_IPA_GSI_TOP_GSI_DATA_CACHEATTR_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000088) +#define HWIO_IPA_GSI_TOP_GSI_DATA_CACHEATTR_RMSK 0x3f +#define HWIO_IPA_GSI_TOP_GSI_DATA_CACHEATTR_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_DATA_CACHEATTR_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_DATA_CACHEATTR_ADDR, HWIO_IPA_GSI_TOP_GSI_DATA_CACHEATTR_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_DATA_CACHEATTR_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_DATA_CACHEATTR_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_DATA_CACHEATTR_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_DATA_CACHEATTR_ADDR,v) +#define HWIO_IPA_GSI_TOP_GSI_DATA_CACHEATTR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_DATA_CACHEATTR_ADDR,m,v,HWIO_IPA_GSI_TOP_GSI_DATA_CACHEATTR_IN) +#define HWIO_IPA_GSI_TOP_GSI_DATA_CACHEATTR_AREQPRIORITY_BMSK 0x30 +#define HWIO_IPA_GSI_TOP_GSI_DATA_CACHEATTR_AREQPRIORITY_SHFT 0x4 +#define HWIO_IPA_GSI_TOP_GSI_DATA_CACHEATTR_ATRANSIENT_BMSK 0x8 +#define HWIO_IPA_GSI_TOP_GSI_DATA_CACHEATTR_ATRANSIENT_SHFT 0x3 +#define HWIO_IPA_GSI_TOP_GSI_DATA_CACHEATTR_ANOALLOCATE_BMSK 0x4 +#define HWIO_IPA_GSI_TOP_GSI_DATA_CACHEATTR_ANOALLOCATE_SHFT 0x2 +#define HWIO_IPA_GSI_TOP_GSI_DATA_CACHEATTR_AINNERSHARED_BMSK 0x2 +#define HWIO_IPA_GSI_TOP_GSI_DATA_CACHEATTR_AINNERSHARED_SHFT 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DATA_CACHEATTR_ASHARED_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DATA_CACHEATTR_ASHARED_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_TRE_CACHEATTR_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00000090) +#define HWIO_IPA_GSI_TOP_GSI_TRE_CACHEATTR_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000090) +#define HWIO_IPA_GSI_TOP_GSI_TRE_CACHEATTR_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000090) +#define HWIO_IPA_GSI_TOP_GSI_TRE_CACHEATTR_RMSK 0x3f +#define HWIO_IPA_GSI_TOP_GSI_TRE_CACHEATTR_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_TRE_CACHEATTR_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_TRE_CACHEATTR_ADDR, HWIO_IPA_GSI_TOP_GSI_TRE_CACHEATTR_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_TRE_CACHEATTR_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_TRE_CACHEATTR_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_TRE_CACHEATTR_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_TRE_CACHEATTR_ADDR,v) +#define HWIO_IPA_GSI_TOP_GSI_TRE_CACHEATTR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_TRE_CACHEATTR_ADDR,m,v,HWIO_IPA_GSI_TOP_GSI_TRE_CACHEATTR_IN) +#define HWIO_IPA_GSI_TOP_GSI_TRE_CACHEATTR_AREQPRIORITY_BMSK 0x30 +#define HWIO_IPA_GSI_TOP_GSI_TRE_CACHEATTR_AREQPRIORITY_SHFT 0x4 +#define HWIO_IPA_GSI_TOP_GSI_TRE_CACHEATTR_ATRANSIENT_BMSK 0x8 +#define HWIO_IPA_GSI_TOP_GSI_TRE_CACHEATTR_ATRANSIENT_SHFT 0x3 +#define HWIO_IPA_GSI_TOP_GSI_TRE_CACHEATTR_ANOALLOCATE_BMSK 0x4 +#define HWIO_IPA_GSI_TOP_GSI_TRE_CACHEATTR_ANOALLOCATE_SHFT 0x2 +#define HWIO_IPA_GSI_TOP_GSI_TRE_CACHEATTR_AINNERSHARED_BMSK 0x2 +#define HWIO_IPA_GSI_TOP_GSI_TRE_CACHEATTR_AINNERSHARED_SHFT 0x1 +#define HWIO_IPA_GSI_TOP_GSI_TRE_CACHEATTR_ASHARED_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_GSI_TRE_CACHEATTR_ASHARED_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_REE_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00000100) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_REE_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000100) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_REE_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000100) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_REE_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_REE_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_REE_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_REE_ADDR, HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_REE_RMSK) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_REE_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_REE_ADDR, m) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_REE_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_REE_ADDR,v) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_REE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_REE_ADDR,m,v,HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_REE_IN) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_REE_CH_EMPTY_INT_WEIGHT_BMSK 0xf00 +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_REE_CH_EMPTY_INT_WEIGHT_SHFT 0x8 +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_REE_NEW_RE_INT_WEIGHT_BMSK 0xf0 +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_REE_NEW_RE_INT_WEIGHT_SHFT 0x4 +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_REE_STOP_CH_COMP_INT_WEIGHT_BMSK 0xf +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_REE_STOP_CH_COMP_INT_WEIGHT_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_EVT_ENG_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00000104) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_EVT_ENG_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000104) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_EVT_ENG_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000104) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_EVT_ENG_RMSK 0xf +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_EVT_ENG_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_EVT_ENG_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_EVT_ENG_ADDR, HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_EVT_ENG_RMSK) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_EVT_ENG_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_EVT_ENG_ADDR, m) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_EVT_ENG_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_EVT_ENG_ADDR,v) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_EVT_ENG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_EVT_ENG_ADDR,m,v,HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_EVT_ENG_IN) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_EVT_ENG_EVNT_ENG_INT_WEIGHT_BMSK 0xf +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_EVT_ENG_EVNT_ENG_INT_WEIGHT_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_INT_ENG_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00000108) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_INT_ENG_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000108) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_INT_ENG_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000108) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_INT_ENG_RMSK 0xf +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_INT_ENG_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_INT_ENG_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_INT_ENG_ADDR, HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_INT_ENG_RMSK) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_INT_ENG_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_INT_ENG_ADDR, m) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_INT_ENG_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_INT_ENG_ADDR,v) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_INT_ENG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_INT_ENG_ADDR,m,v,HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_INT_ENG_IN) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_INT_ENG_INT_ENG_INT_WEIGHT_BMSK 0xf +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_INT_ENG_INT_ENG_INT_WEIGHT_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_CSR_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x0000010c) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_CSR_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000010c) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_CSR_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000010c) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_CSR_RMSK 0xff +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_CSR_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_CSR_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_CSR_ADDR, HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_CSR_RMSK) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_CSR_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_CSR_ADDR, m) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_CSR_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_CSR_ADDR,v) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_CSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_CSR_ADDR,m,v,HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_CSR_IN) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_CSR_EE_GENERIC_INT_WEIGHT_BMSK 0xf0 +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_CSR_EE_GENERIC_INT_WEIGHT_SHFT 0x4 +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_CSR_CH_CMD_INT_WEIGHT_BMSK 0xf +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_CSR_CH_CMD_INT_WEIGHT_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_TLV_ENG_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00000110) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_TLV_ENG_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000110) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_TLV_ENG_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000110) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_TLV_ENG_RMSK 0xffff +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_TLV_ENG_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_TLV_ENG_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_TLV_ENG_ADDR, HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_TLV_ENG_RMSK) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_TLV_ENG_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_TLV_ENG_ADDR, m) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_TLV_ENG_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_TLV_ENG_ADDR,v) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_TLV_ENG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_TLV_ENG_ADDR,m,v,HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_TLV_ENG_IN) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_TLV_ENG_CH_NOT_FULL_INT_WEIGHT_BMSK 0xf000 +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_TLV_ENG_CH_NOT_FULL_INT_WEIGHT_SHFT 0xc +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_TLV_ENG_TLV_2_INT_WEIGHT_BMSK 0xf00 +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_TLV_ENG_TLV_2_INT_WEIGHT_SHFT 0x8 +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_TLV_ENG_TLV_1_INT_WEIGHT_BMSK 0xf0 +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_TLV_ENG_TLV_1_INT_WEIGHT_SHFT 0x4 +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_TLV_ENG_TLV_0_INT_WEIGHT_BMSK 0xf +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_TLV_ENG_TLV_0_INT_WEIGHT_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_TIMER_ENG_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00000114) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_TIMER_ENG_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000114) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_TIMER_ENG_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000114) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_TIMER_ENG_RMSK 0xf +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_TIMER_ENG_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_TIMER_ENG_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_TIMER_ENG_ADDR, HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_TIMER_ENG_RMSK) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_TIMER_ENG_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_TIMER_ENG_ADDR, m) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_TIMER_ENG_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_TIMER_ENG_ADDR,v) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_TIMER_ENG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_TIMER_ENG_ADDR,m,v,HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_TIMER_ENG_IN) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_TIMER_ENG_TIMER_INT_WEIGHT_BMSK 0xf +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_TIMER_ENG_TIMER_INT_WEIGHT_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_DB_ENG_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00000118) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_DB_ENG_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000118) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_DB_ENG_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000118) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_DB_ENG_RMSK 0xf +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_DB_ENG_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_DB_ENG_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_DB_ENG_ADDR, HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_DB_ENG_RMSK) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_DB_ENG_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_DB_ENG_ADDR, m) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_DB_ENG_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_DB_ENG_ADDR,v) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_DB_ENG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_DB_ENG_ADDR,m,v,HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_DB_ENG_IN) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_DB_ENG_NEW_DB_INT_WEIGHT_BMSK 0xf +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_DB_ENG_NEW_DB_INT_WEIGHT_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_RD_WR_ENG_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x0000011c) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_RD_WR_ENG_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000011c) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_RD_WR_ENG_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000011c) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_RD_WR_ENG_RMSK 0xff +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_RD_WR_ENG_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_RD_WR_ENG_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_RD_WR_ENG_ADDR, HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_RD_WR_ENG_RMSK) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_RD_WR_ENG_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_RD_WR_ENG_ADDR, m) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_RD_WR_ENG_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_RD_WR_ENG_ADDR,v) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_RD_WR_ENG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_RD_WR_ENG_ADDR,m,v,HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_RD_WR_ENG_IN) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_RD_WR_ENG_WRITE_INT_WEIGHT_BMSK 0xf0 +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_RD_WR_ENG_WRITE_INT_WEIGHT_SHFT 0x4 +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_RD_WR_ENG_READ_INT_WEIGHT_BMSK 0xf +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_RD_WR_ENG_READ_INT_WEIGHT_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_UCONTROLLER_ENG_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00000120) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_UCONTROLLER_ENG_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000120) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_UCONTROLLER_ENG_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000120) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_UCONTROLLER_ENG_RMSK 0xf +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_UCONTROLLER_ENG_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_UCONTROLLER_ENG_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_UCONTROLLER_ENG_ADDR, HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_UCONTROLLER_ENG_RMSK) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_UCONTROLLER_ENG_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_UCONTROLLER_ENG_ADDR, m) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_UCONTROLLER_ENG_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_UCONTROLLER_ENG_ADDR,v) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_UCONTROLLER_ENG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_UCONTROLLER_ENG_ADDR,m,v,HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_UCONTROLLER_ENG_IN) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_UCONTROLLER_ENG_UCONTROLLER_GP_INT_WEIGHT_BMSK 0xf +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_UCONTROLLER_ENG_UCONTROLLER_GP_INT_WEIGHT_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_LOW_LATENCY_ARB_WEIGHT_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00000128) +#define HWIO_IPA_GSI_TOP_LOW_LATENCY_ARB_WEIGHT_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000128) +#define HWIO_IPA_GSI_TOP_LOW_LATENCY_ARB_WEIGHT_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000128) +#define HWIO_IPA_GSI_TOP_LOW_LATENCY_ARB_WEIGHT_RMSK 0x13f3f +#define HWIO_IPA_GSI_TOP_LOW_LATENCY_ARB_WEIGHT_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_LOW_LATENCY_ARB_WEIGHT_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_LOW_LATENCY_ARB_WEIGHT_ADDR, HWIO_IPA_GSI_TOP_LOW_LATENCY_ARB_WEIGHT_RMSK) +#define HWIO_IPA_GSI_TOP_LOW_LATENCY_ARB_WEIGHT_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_LOW_LATENCY_ARB_WEIGHT_ADDR, m) +#define HWIO_IPA_GSI_TOP_LOW_LATENCY_ARB_WEIGHT_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_LOW_LATENCY_ARB_WEIGHT_ADDR,v) +#define HWIO_IPA_GSI_TOP_LOW_LATENCY_ARB_WEIGHT_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_LOW_LATENCY_ARB_WEIGHT_ADDR,m,v,HWIO_IPA_GSI_TOP_LOW_LATENCY_ARB_WEIGHT_IN) +#define HWIO_IPA_GSI_TOP_LOW_LATENCY_ARB_WEIGHT_LL_NON_LL_FIX_PRIORITY_BMSK 0x10000 +#define HWIO_IPA_GSI_TOP_LOW_LATENCY_ARB_WEIGHT_LL_NON_LL_FIX_PRIORITY_SHFT 0x10 +#define HWIO_IPA_GSI_TOP_LOW_LATENCY_ARB_WEIGHT_NON_LL_WEIGHT_BMSK 0x3f00 +#define HWIO_IPA_GSI_TOP_LOW_LATENCY_ARB_WEIGHT_NON_LL_WEIGHT_SHFT 0x8 +#define HWIO_IPA_GSI_TOP_LOW_LATENCY_ARB_WEIGHT_LL_WEIGHT_BMSK 0x3f +#define HWIO_IPA_GSI_TOP_LOW_LATENCY_ARB_WEIGHT_LL_WEIGHT_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_ADDR(n) (IPA_GSI_TOP_GSI_REG_BASE + 0x00000300 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_PHYS(n) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000300 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_OFFS(n) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000300 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_RMSK 0xffff03 +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_MAXn 2 +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_ATTR 0x0 +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_INI(n) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_ADDR(n), HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_ADDR(n), mask) +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_OUTI(n,val) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_ADDR(n),val) +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_ADDR(n),mask,val,HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_INI(n)) +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_MAX_EV_ALLOC_BMSK 0xff0000 +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_MAX_EV_ALLOC_SHFT 0x10 +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_MAX_CH_ALLOC_BMSK 0xff00 +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_MAX_CH_ALLOC_SHFT 0x8 +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_EE_PRIO_BMSK 0x3 +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_EE_PRIO_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00000200) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000200) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000200) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_RMSK 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_ADDR, HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_ADDR,v) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_ADDR,m,v,HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_IN) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00000204) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000204) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000204) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_RMSK 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_ADDR, HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_ADDR,v) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_ADDR,m,v,HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_IN) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00000208) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000208) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000208) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_RMSK 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_ADDR, HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_ADDR,v) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_ADDR,m,v,HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_IN) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x0000020c) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000020c) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000020c) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_RMSK 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_ADDR, HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_ADDR,v) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_ADDR,m,v,HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_IN) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00000240) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000240) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000240) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_RMSK 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_ADDR, HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_ADDR,v) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_ADDR,m,v,HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_IN) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00000244) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000244) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000244) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_RMSK 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_ADDR, HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_ADDR,v) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_ADDR,m,v,HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_IN) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00000210) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000210) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000210) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_RMSK 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_ADDR, HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_ADDR,v) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_ADDR,m,v,HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_IN) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00000214) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000214) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000214) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_RMSK 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_ADDR, HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_ADDR,v) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_ADDR,m,v,HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_IN) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00000218) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000218) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000218) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_RMSK 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_ADDR, HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_ADDR,v) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_ADDR,m,v,HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_IN) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x0000021c) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000021c) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000021c) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_RMSK 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_ADDR, HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_ADDR,v) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_ADDR,m,v,HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_IN) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00000254) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000254) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000254) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_RMSK 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_ADDR, HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_ADDR,v) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_ADDR,m,v,HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_IN) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00000258) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000258) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000258) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_RMSK 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_ADDR, HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_ADDR,v) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_ADDR,m,v,HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_IN) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x0000025c) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000025c) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000025c) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_RMSK 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_ADDR, HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_ADDR,v) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_ADDR,m,v,HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_IN) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00000260) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000260) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000260) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_RMSK 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_ADDR, HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_ADDR,v) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_ADDR,m,v,HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_IN) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00000264) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000264) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000264) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_RMSK 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_ADDR, HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_ADDR,v) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_ADDR,m,v,HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_IN) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00000268) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000268) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000268) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_RMSK 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_ADDR, HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_ADDR,v) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_ADDR,m,v,HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_IN) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00000400) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000400) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000400) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_ADDR, HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_ADDR,v) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_ADDR,m,v,HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_IN) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_IRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00000404) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000404) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000404) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_ADDR, HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_ADDR,v) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_ADDR,m,v,HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_IN) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_IRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TLV_CH_NOT_FULL_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00000408) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TLV_CH_NOT_FULL_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000408) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TLV_CH_NOT_FULL_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000408) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TLV_CH_NOT_FULL_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TLV_CH_NOT_FULL_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TLV_CH_NOT_FULL_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TLV_CH_NOT_FULL_ADDR, HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TLV_CH_NOT_FULL_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TLV_CH_NOT_FULL_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TLV_CH_NOT_FULL_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TLV_CH_NOT_FULL_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TLV_CH_NOT_FULL_ADDR,v) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TLV_CH_NOT_FULL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TLV_CH_NOT_FULL_ADDR,m,v,HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TLV_CH_NOT_FULL_IN) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TLV_CH_NOT_FULL_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TLV_CH_NOT_FULL_IRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_MSI_DB_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00000414) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_MSI_DB_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000414) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_MSI_DB_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000414) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_MSI_DB_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_MSI_DB_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_MSI_DB_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_MSI_DB_ADDR, HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_MSI_DB_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_MSI_DB_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_MSI_DB_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_MSI_DB_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_MSI_DB_ADDR,v) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_MSI_DB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_MSI_DB_ADDR,m,v,HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_MSI_DB_IN) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_MSI_DB_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_MSI_DB_IRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00000418) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000418) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000418) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_ADDR, HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_ADDR,v) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_ADDR,m,v,HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_IN) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_IRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x0000041c) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000041c) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000041c) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_ADDR, HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_ADDR,v) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_ADDR,m,v,HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_IN) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_IRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00000420) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000420) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000420) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_ADDR, HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_ADDR,v) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_ADDR,m,v,HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_IN) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_IRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00000424) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000424) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000424) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_ADDR, HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_ADDR,v) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_ADDR,m,v,HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_IN) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_IRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00000428) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000428) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000428) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_ADDR, HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_ADDR,v) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_ADDR,m,v,HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_IN) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_IRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x0000042c) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000042c) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000042c) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_ADDR, HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_ADDR,v) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_ADDR,m,v,HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_IN) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_IRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00000430) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000430) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000430) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_ADDR, HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_ADDR,v) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_ADDR,m,v,HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_IN) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_IRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00000434) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000434) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000434) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_ADDR, HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_ADDR,v) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_ADDR,m,v,HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_IN) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_IRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00000438) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000438) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000438) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_ADDR, HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_ADDR,v) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_ADDR,m,v,HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_IN) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_IRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x0000043c) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000043c) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000043c) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_ADDR, HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_ADDR,v) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_ADDR,m,v,HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_IN) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_IRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00000440) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000440) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000440) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_ADDR, HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_ADDR,v) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_ADDR,m,v,HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_IN) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_IRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00000444) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000444) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000444) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_ADDR, HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_ADDR,v) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_ADDR,m,v,HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_IN) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_IRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00000448) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000448) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000448) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_ADDR, HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_ADDR,v) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_ADDR,m,v,HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_IN) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_IRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPED_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x0000044c) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPED_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000044c) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPED_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000044c) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPED_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPED_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPED_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPED_ADDR, HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPED_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPED_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPED_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPED_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPED_ADDR,v) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPED_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPED_ADDR,m,v,HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPED_IN) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPED_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPED_IRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_NOTIFY_MCS_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00000470) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_NOTIFY_MCS_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000470) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_NOTIFY_MCS_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000470) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_NOTIFY_MCS_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_NOTIFY_MCS_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_NOTIFY_MCS_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_NOTIFY_MCS_ADDR, HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_NOTIFY_MCS_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_NOTIFY_MCS_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_NOTIFY_MCS_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_NOTIFY_MCS_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_NOTIFY_MCS_ADDR,v) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_NOTIFY_MCS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_NOTIFY_MCS_ADDR,m,v,HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_NOTIFY_MCS_IN) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_NOTIFY_MCS_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_NOTIFY_MCS_IRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_ADDR(n) (IPA_GSI_TOP_GSI_REG_BASE + 0x000a4000 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_PHYS(n) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000a4000 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_OFFS(n) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000a4000 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_MAXn 8255 +#define HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_INI(n) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_ADDR(n), HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_RMSK, HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_ATTR) +#define HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_ADDR(n), mask, HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_ATTR) +#define HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_OUTI(n,val) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_ADDR(n),val) +#define HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_ADDR(n),mask,val,HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_INI(n)) +#define HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_INST_BYTE_3_BMSK 0xff000000 +#define HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_INST_BYTE_3_SHFT 0x18 +#define HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_INST_BYTE_2_BMSK 0xff0000 +#define HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_INST_BYTE_2_SHFT 0x10 +#define HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_INST_BYTE_1_BMSK 0xff00 +#define HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_INST_BYTE_1_SHFT 0x8 +#define HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_INST_BYTE_0_BMSK 0xff +#define HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_INST_BYTE_0_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_n_ADDR(n) (IPA_GSI_TOP_GSI_REG_BASE + 0x00002000 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_n_PHYS(n) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00002000 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_n_OFFS(n) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00002000 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_n_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_n_MAXn 2047 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_n_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_n_INI(n) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_SHRAM_n_ADDR(n), HWIO_IPA_GSI_TOP_GSI_SHRAM_n_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_SHRAM_n_ADDR(n), mask) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_n_OUTI(n,val) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_SHRAM_n_ADDR(n),val) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_SHRAM_n_ADDR(n),mask,val,HWIO_IPA_GSI_TOP_GSI_SHRAM_n_INI(n)) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_n_SHRAM_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_n_SHRAM_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x00009000 + 0x400 * (n) + 0x4 * (k)) +#define HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00009000 + 0x400 * (n) + 0x4 * (k)) +#define HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00009000 + 0x400 * (n) + 0x4 * (k)) +#define HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_RMSK 0x1ff +#define HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_MAXn 2 +#define HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_MAXk 27 +#define HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_INI2(n,k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_ADDR(n,k), HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_ADDR(n,k), mask) +#define HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_ADDR(n,k),val) +#define HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_ADDR(n,k),mask,val,HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_INI2(n,k)) +#define HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_VALID_BMSK 0x100 +#define HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_VALID_SHFT 0x8 +#define HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_PHY_CH_BMSK 0xff +#define HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_PHY_CH_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00001000) +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001000) +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001000) +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_RMSK 0xf00ff +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_ADDR, HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_ADDR,v) +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_ADDR,m,v,HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_IN) +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_HW_EVENTS_SEL_BMSK 0xf0000 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_HW_EVENTS_SEL_SHFT 0x10 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_BMSK 0xff +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_ZEROS_FVAL 0x0 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MCS_0_FVAL 0x1 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MCS_1_FVAL 0x2 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MCS_2_FVAL 0x3 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MCS_3_FVAL 0x4 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MCS_4_FVAL 0x5 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_DB_ENG_FVAL 0x9 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_0_FVAL 0xb +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_1_FVAL 0xc +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_2_FVAL 0xd +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_3_FVAL 0xe +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_4_FVAL 0xf +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_5_FVAL 0x10 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_6_FVAL 0x11 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_7_FVAL 0x12 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_EVE_0_FVAL 0x13 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_EVE_1_FVAL 0x14 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_EVE_2_FVAL 0x15 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_EVE_3_FVAL 0x16 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_EVE_4_FVAL 0x17 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_EVE_5_FVAL 0x18 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IE_0_FVAL 0x1b +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IE_1_FVAL 0x1c +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IE_2_FVAL 0x1d +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IC_0_FVAL 0x1f +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IC_1_FVAL 0x20 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IC_2_FVAL 0x21 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IC_3_FVAL 0x22 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IC_4_FVAL 0x23 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MOQA_0_FVAL 0x27 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MOQA_1_FVAL 0x28 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MOQA_2_FVAL 0x29 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MOQA_3_FVAL 0x2a +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_TMR_0_FVAL 0x2b +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_TMR_1_FVAL 0x2c +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_TMR_2_FVAL 0x2d +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_TMR_3_FVAL 0x2e +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_RD_WR_0_FVAL 0x33 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_RD_WR_1_FVAL 0x34 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_RD_WR_2_FVAL 0x35 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_RD_WR_3_FVAL 0x36 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_CSR_FVAL 0x3a +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_SDMA_0_FVAL 0x3c +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_SMDA_1_FVAL 0x3d +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_CSR_1_FVAL 0x3e +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_CSR_2_FVAL 0x3f +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MCS_5_FVAL 0x40 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IC_5_FVAL 0x41 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_CSR_3_FVAL 0x42 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_TLV_0_FVAL 0x43 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_8_FVAL 0x44 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IE_NOTIFY_FVAL 0x45 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_DB_MSI_FVAL 0x46 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_9_FVAL 0x47 + +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_REG_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00001008) +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_REG_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001008) +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_REG_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001008) +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_REG_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_REG_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_REG_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_TEST_BUS_REG_ADDR, HWIO_IPA_GSI_TOP_GSI_TEST_BUS_REG_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_REG_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_TEST_BUS_REG_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_REG_GSI_TESTBUS_REG_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_REG_GSI_TESTBUS_REG_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00001010) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001010) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001010) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_RMSK 0x1fff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_ADDR, HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_SDMA_BUSY_BMSK 0x1000 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_SDMA_BUSY_SHFT 0xc +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_IC_BUSY_BMSK 0x800 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_IC_BUSY_SHFT 0xb +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_UC_BUSY_BMSK 0x400 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_UC_BUSY_SHFT 0xa +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_DBG_CNT_BUSY_BMSK 0x200 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_DBG_CNT_BUSY_SHFT 0x9 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_DB_ENG_BUSY_BMSK 0x100 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_DB_ENG_BUSY_SHFT 0x8 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_REE_PWR_CLPS_BUSY_BMSK 0x80 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_REE_PWR_CLPS_BUSY_SHFT 0x7 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_INT_ENG_BUSY_BMSK 0x40 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_INT_ENG_BUSY_SHFT 0x6 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_EV_ENG_BUSY_BMSK 0x20 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_EV_ENG_BUSY_SHFT 0x5 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_RD_WR_BUSY_BMSK 0x10 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_RD_WR_BUSY_SHFT 0x4 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_TIMER_BUSY_BMSK 0x8 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_TIMER_BUSY_SHFT 0x3 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_MCS_BUSY_BMSK 0x4 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_MCS_BUSY_SHFT 0x2 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_REE_BUSY_BMSK 0x2 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_REE_BUSY_SHFT 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_CSR_BUSY_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_CSR_BUSY_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EVENT_PENDING_k_ADDR(k) (IPA_GSI_TOP_GSI_REG_BASE + 0x00001a80 + 0x4 * (k)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EVENT_PENDING_k_PHYS(k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001a80 + 0x4 * (k)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EVENT_PENDING_k_OFFS(k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001a80 + 0x4 * (k)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EVENT_PENDING_k_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EVENT_PENDING_k_MAXk 1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EVENT_PENDING_k_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EVENT_PENDING_k_INI(k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_DEBUG_EVENT_PENDING_k_ADDR(k), HWIO_IPA_GSI_TOP_GSI_DEBUG_EVENT_PENDING_k_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EVENT_PENDING_k_INMI(k,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_DEBUG_EVENT_PENDING_k_ADDR(k), mask) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EVENT_PENDING_k_CHID_BIT_MAP_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EVENT_PENDING_k_CHID_BIT_MAP_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_TIMER_PENDING_k_ADDR(k) (IPA_GSI_TOP_GSI_REG_BASE + 0x00001aa0 + 0x4 * (k)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_TIMER_PENDING_k_PHYS(k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001aa0 + 0x4 * (k)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_TIMER_PENDING_k_OFFS(k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001aa0 + 0x4 * (k)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_TIMER_PENDING_k_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_TIMER_PENDING_k_MAXk 1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_TIMER_PENDING_k_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_TIMER_PENDING_k_INI(k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_DEBUG_TIMER_PENDING_k_ADDR(k), HWIO_IPA_GSI_TOP_GSI_DEBUG_TIMER_PENDING_k_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_TIMER_PENDING_k_INMI(k,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_DEBUG_TIMER_PENDING_k_ADDR(k), mask) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_TIMER_PENDING_k_CHID_BIT_MAP_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_TIMER_PENDING_k_CHID_BIT_MAP_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_k_ADDR(k) (IPA_GSI_TOP_GSI_REG_BASE + 0x00001ac0 + 0x4 * (k)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_k_PHYS(k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001ac0 + 0x4 * (k)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_k_OFFS(k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001ac0 + 0x4 * (k)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_k_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_k_MAXk 1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_k_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_k_INI(k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_k_ADDR(k), HWIO_IPA_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_k_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_k_INMI(k,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_k_ADDR(k), mask) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_k_CHID_BIT_MAP_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_k_CHID_BIT_MAP_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_SPARE_REG_1_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00001030) +#define HWIO_IPA_GSI_TOP_GSI_SPARE_REG_1_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001030) +#define HWIO_IPA_GSI_TOP_GSI_SPARE_REG_1_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001030) +#define HWIO_IPA_GSI_TOP_GSI_SPARE_REG_1_RMSK 0x1 +#define HWIO_IPA_GSI_TOP_GSI_SPARE_REG_1_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_SPARE_REG_1_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_SPARE_REG_1_ADDR, HWIO_IPA_GSI_TOP_GSI_SPARE_REG_1_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_SPARE_REG_1_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_SPARE_REG_1_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_SPARE_REG_1_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_SPARE_REG_1_ADDR,v) +#define HWIO_IPA_GSI_TOP_GSI_SPARE_REG_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_SPARE_REG_1_ADDR,m,v,HWIO_IPA_GSI_TOP_GSI_SPARE_REG_1_IN) +#define HWIO_IPA_GSI_TOP_GSI_SPARE_REG_1_FIX_IEOB_WRONG_MSK_DISABLE_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_GSI_SPARE_REG_1_FIX_IEOB_WRONG_MSK_DISABLE_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00001040) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001040) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001040) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_ADDR, HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_ADDR,v) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_ADDR,m,v,HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_IN) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_IRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00001044) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001044) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001044) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_RMSK 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_ADDR, HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_ADDR,v) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_ADDR,m,v,HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_IN) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_MCS_STALL_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_MCS_STALL_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00001048) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001048) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001048) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG_ADDR, HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG_IRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_SEL_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00001050) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_SEL_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001050) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_SEL_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001050) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_SEL_RMSK 0xffff01 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_SEL_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_SEL_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_SEL_ADDR, HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_SEL_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_SEL_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_SEL_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_SEL_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_SEL_ADDR,v) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_SEL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_SEL_ADDR,m,v,HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_SEL_IN) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_SEL_SEL_MID_BMSK 0xff0000 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_SEL_SEL_MID_SHFT 0x10 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_SEL_SEL_TID_BMSK 0xff00 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_SEL_SEL_TID_SHFT 0x8 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_SEL_SEL_WRITE_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_SEL_SEL_WRITE_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_CLR_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00001058) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_CLR_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001058) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_CLR_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001058) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_CLR_RMSK 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_CLR_ATTR 0x2 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_CLR_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_CLR_ADDR,v) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_CLR_LOG_CLR_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_CLR_LOG_CLR_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00001060) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001060) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001060) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_RMSK 0x1ffff01 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ADDR, HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ERR_SAVED_BMSK 0x1000000 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ERR_SAVED_SHFT 0x18 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ERR_MID_BMSK 0xff0000 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ERR_MID_SHFT 0x10 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ERR_TID_BMSK 0xff00 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ERR_TID_SHFT 0x8 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ERR_WRITE_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ERR_WRITE_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_0_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00001064) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_0_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001064) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_0_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001064) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_0_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_0_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_0_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_0_ADDR, HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_0_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_0_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_0_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_0_ADDR_31_0_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_0_ADDR_31_0_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_1_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00001068) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_1_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001068) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_1_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001068) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_1_RMSK 0xfff7ffff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_1_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_1_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_1_ADDR, HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_1_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_1_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_1_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_1_AREQPRIORITY_BMSK 0xf0000000 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_1_AREQPRIORITY_SHFT 0x1c +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_1_ASIZE_BMSK 0xf000000 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_1_ASIZE_SHFT 0x18 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_1_ALEN_BMSK 0xf00000 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_1_ALEN_SHFT 0x14 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_1_AOOOWR_BMSK 0x40000 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_1_AOOOWR_SHFT 0x12 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_1_AOOORD_BMSK 0x20000 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_1_AOOORD_SHFT 0x11 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_1_ATRANSIENT_BMSK 0x10000 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_1_ATRANSIENT_SHFT 0x10 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_1_ACACHEABLE_BMSK 0x8000 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_1_ACACHEABLE_SHFT 0xf +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_1_ASHARED_BMSK 0x4000 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_1_ASHARED_SHFT 0xe +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_1_ANOALLOCATE_BMSK 0x2000 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_1_ANOALLOCATE_SHFT 0xd +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_1_AINNERSHARED_BMSK 0x1000 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_1_AINNERSHARED_SHFT 0xc +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_1_ADDR_43_32_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_1_ADDR_43_32_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_2_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x0000106c) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_2_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000106c) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_2_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000106c) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_2_RMSK 0xffff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_2_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_2_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_2_ADDR, HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_2_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_2_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_2_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_2_AMEMTYPE_BMSK 0xf000 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_2_AMEMTYPE_SHFT 0xc +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_2_AMMUSID_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_2_AMMUSID_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_ADDR(n) (IPA_GSI_TOP_GSI_REG_BASE + 0x00001070 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_PHYS(n) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001070 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_OFFS(n) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001070 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_MAXn 3 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_INI(n) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_ADDR(n), HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_ADDR(n), mask) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_MID_BMSK 0xf8000000 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_MID_SHFT 0x1b +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_TID_BMSK 0x7c00000 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_TID_SHFT 0x16 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_WRITE_BMSK 0x200000 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_WRITE_SHFT 0x15 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_ADDR_20_0_BMSK 0x1fffff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_ADDR_20_0_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_WRITE_ADDR(n) (IPA_GSI_TOP_GSI_REG_BASE + 0x00001080 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_WRITE_PHYS(n) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001080 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_WRITE_OFFS(n) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001080 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_WRITE_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_WRITE_MAXn 31 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_WRITE_ATTR 0x2 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_WRITE_OUTI(n,val) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_WRITE_ADDR(n),val) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_WRITE_DATA_IN_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_WRITE_DATA_IN_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_ADDR(n) (IPA_GSI_TOP_GSI_REG_BASE + 0x00001100 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_PHYS(n) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001100 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_OFFS(n) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001100 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_MAXn 31 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_INI(n) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_ADDR(n), HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_ADDR(n), mask) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_RF_REG_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_RF_REG_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_ADDR(n) (IPA_GSI_TOP_GSI_REG_BASE + 0x00001180 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_PHYS(n) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001180 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_OFFS(n) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001180 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_RMSK 0x1fffff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_MAXn 7 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_INI(n) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_ADDR(n), HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_ADDR(n), mask) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_OUTI(n,val) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_ADDR(n),val) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_ADDR(n),mask,val,HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_INI(n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_CHAIN_BMSK 0x100000 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_CHAIN_SHFT 0x14 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_VIRTUAL_CHNL_BMSK 0xff000 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_VIRTUAL_CHNL_SHFT 0xc +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_EE_BMSK 0xf00 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_EE_SHFT 0x8 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_EVNT_TYPE_BMSK 0xf8 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_EVNT_TYPE_SHFT 0x3 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_CLR_AT_READ_BMSK 0x4 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_CLR_AT_READ_SHFT 0x2 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_STOP_AT_WRAP_ARND_BMSK 0x2 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_STOP_AT_WRAP_ARND_SHFT 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_ENABLE_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_ENABLE_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTERn_ADDR(n) (IPA_GSI_TOP_GSI_REG_BASE + 0x000011a0 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTERn_PHYS(n) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000011a0 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTERn_OFFS(n) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000011a0 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTERn_RMSK 0xffff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTERn_MAXn 7 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTERn_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTERn_INI(n) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTERn_ADDR(n), HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTERn_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTERn_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTERn_ADDR(n), mask) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTERn_COUNTER_VALUE_BMSK 0xffff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTERn_COUNTER_VALUE_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_MSK_REG_n_SEC_k_WR_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x000011c0 + 0x4 * (n) + 0x24 * (k)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_MSK_REG_n_SEC_k_WR_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000011c0 + 0x4 * (n) + 0x24 * (k)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_MSK_REG_n_SEC_k_WR_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000011c0 + 0x4 * (n) + 0x24 * (k)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_MSK_REG_n_SEC_k_WR_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_MSK_REG_n_SEC_k_WR_MAXn 8 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_MSK_REG_n_SEC_k_WR_MAXk 1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_MSK_REG_n_SEC_k_WR_ATTR 0x2 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_MSK_REG_n_SEC_k_WR_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_MSK_REG_n_SEC_k_WR_ADDR(n,k),val) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_MSK_REG_n_SEC_k_WR_DATA_IN_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_MSK_REG_n_SEC_k_WR_DATA_IN_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x000012e0 + 0x4 * (n) + 0x24 * (k)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000012e0 + 0x4 * (n) + 0x24 * (k)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000012e0 + 0x4 * (n) + 0x24 * (k)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD_MAXn 8 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD_MAXk 1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD_INI2(n,k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD_ADDR(n,k), HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD_ADDR(n,k), mask) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD_MSK_REG_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD_MSK_REG_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x00001400 + 0x80 * (n) + 0x4 * (k)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001400 + 0x80 * (n) + 0x4 * (k)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001400 + 0x80 * (n) + 0x4 * (k)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_RMSK 0x1ff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_MAXn 3 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_MAXk 27 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_INI2(n,k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_ADDR(n,k), HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_ADDR(n,k), mask) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_VALID_BMSK 0x100 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_VALID_SHFT 0x8 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_PHY_CH_BMSK 0xff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_PHY_CH_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x00001600 + 0x100 * (n) + 0x4 * (k)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001600 + 0x100 * (n) + 0x4 * (k)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001600 + 0x100 * (n) + 0x4 * (k)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_RMSK 0x1ff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_MAXn 3 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_MAXk 26 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_INI2(n,k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_ADDR(n,k), HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_ADDR(n,k), mask) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_VALID_BMSK 0x100 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_VALID_SHFT 0x8 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_PHY_EV_CH_BMSK 0xff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_PHY_EV_CH_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00001a54) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001a54) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001a54) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_RMSK 0xff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_ADDR, HWIO_IPA_GSI_TOP_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_ADDR,v) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_ADDR,m,v,HWIO_IPA_GSI_TOP_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_IN) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_PREFETCH_BUF_CH_ID_BMSK 0xff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_PREFETCH_BUF_CH_ID_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_REE_PREFETCH_BUF_STATUS_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00001a58) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_REE_PREFETCH_BUF_STATUS_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001a58) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_REE_PREFETCH_BUF_STATUS_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001a58) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_REE_PREFETCH_BUF_STATUS_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_REE_PREFETCH_BUF_STATUS_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_REE_PREFETCH_BUF_STATUS_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_DEBUG_REE_PREFETCH_BUF_STATUS_ADDR, HWIO_IPA_GSI_TOP_GSI_DEBUG_REE_PREFETCH_BUF_STATUS_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_REE_PREFETCH_BUF_STATUS_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_DEBUG_REE_PREFETCH_BUF_STATUS_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_REE_PREFETCH_BUF_STATUS_PREFETCH_BUF_STATUS_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_REE_PREFETCH_BUF_STATUS_PREFETCH_BUF_STATUS_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_BP_CNT_LSB_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00001a5c) +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_BP_CNT_LSB_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001a5c) +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_BP_CNT_LSB_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001a5c) +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_BP_CNT_LSB_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_BP_CNT_LSB_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_BP_CNT_LSB_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_BP_CNT_LSB_ADDR, HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_BP_CNT_LSB_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_BP_CNT_LSB_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_BP_CNT_LSB_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_BP_CNT_LSB_BP_CNT_LSB_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_BP_CNT_LSB_BP_CNT_LSB_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_BP_CNT_MSB_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00001a60) +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_BP_CNT_MSB_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001a60) +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_BP_CNT_MSB_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001a60) +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_BP_CNT_MSB_RMSK 0xf +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_BP_CNT_MSB_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_BP_CNT_MSB_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_BP_CNT_MSB_ADDR, HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_BP_CNT_MSB_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_BP_CNT_MSB_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_BP_CNT_MSB_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_BP_CNT_MSB_BP_CNT_MSB_BMSK 0xf +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_BP_CNT_MSB_BP_CNT_MSB_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00001a64) +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001a64) +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001a64) +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB_ADDR, HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB_BP_AND_PENDING_CNT_LSB_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB_BP_AND_PENDING_CNT_LSB_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00001a68) +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001a68) +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001a68) +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB_RMSK 0xf +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB_ADDR, HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB_BP_AND_PENDING_CNT_MSB_BMSK 0xf +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB_BP_AND_PENDING_CNT_MSB_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00001a6c) +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001a6c) +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001a6c) +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB_ADDR, HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB_MCS_BUSY_CNT_LSB_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB_MCS_BUSY_CNT_LSB_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00001a70) +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001a70) +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001a70) +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB_RMSK 0xf +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB_ADDR, HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB_MCS_BUSY_CNT_MSB_BMSK 0xf +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB_MCS_BUSY_CNT_MSB_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00001a74) +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001a74) +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001a74) +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB_ADDR, HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB_MCS_IDLE_CNT_LSB_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB_MCS_IDLE_CNT_LSB_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x00001a78) +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001a78) +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001a78) +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_RMSK 0xf +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_ADDR, HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_MCS_IDLE_CNT_MSB_BMSK 0xf +#define HWIO_IPA_GSI_TOP_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_MCS_IDLE_CNT_MSB_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x00014000 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00014000 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00014000 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_MAXk 27 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_INI2(n,k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_ADDR(n,k), HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_ADDR(n,k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_ADDR(n,k),val) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_ADDR(n,k),mask,val,HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_INI2(n,k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_ELEMENT_SIZE_BMSK 0xff000000 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_ELEMENT_SIZE_SHFT 0x18 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_BMSK 0xf00000 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_SHFT 0x14 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_NOT_ALLOCATED_FVAL 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_ALLOCATED_FVAL 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_STARTED_FVAL 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_STOPED_FVAL 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_STOP_IN_PROC_FVAL 0x4 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_ERROR_FVAL 0xf +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHID_BMSK 0xff000 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHID_SHFT 0xc +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_EE_BMSK 0xf00 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_EE_SHFT 0x8 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_DIR_BMSK 0x80 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_DIR_SHFT 0x7 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_DIR_INBOUND_FVAL 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_DIR_OUTBOUND_FVAL 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_BMSK 0x7f +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_MHI_FVAL 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_XHCI_FVAL 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_GPI_FVAL 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_XDCI_FVAL 0x3 + +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x00014004 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00014004 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00014004 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_MAXk 27 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_INI2(n,k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_ADDR(n,k), HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_ADDR(n,k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_ADDR(n,k),val) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_ADDR(n,k),mask,val,HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_INI2(n,k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_ERINDEX_BMSK 0xff000000 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_ERINDEX_SHFT 0x18 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_R_LENGTH_BMSK 0xffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_R_LENGTH_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x00014008 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00014008 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00014008 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_MAXk 27 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_INI2(n,k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_ADDR(n,k), HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_ADDR(n,k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_ADDR(n,k),val) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_ADDR(n,k),mask,val,HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_INI2(n,k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_R_BASE_ADDR_LSBS_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_R_BASE_ADDR_LSBS_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x0001400c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001400c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001400c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_MAXk 27 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_INI2(n,k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_ADDR(n,k), HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_ADDR(n,k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_ADDR(n,k),val) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_ADDR(n,k),mask,val,HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_INI2(n,k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_R_BASE_ADDR_MSBS_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_R_BASE_ADDR_MSBS_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x00014010 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00014010 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00014010 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_MAXk 27 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_INI2(n,k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_ADDR(n,k), HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_ADDR(n,k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_ADDR(n,k),val) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_ADDR(n,k),mask,val,HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_INI2(n,k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_READ_PTR_LSB_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_READ_PTR_LSB_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x00014014 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00014014 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00014014 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_MAXk 27 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_INI2(n,k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_ADDR(n,k), HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_ADDR(n,k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_READ_PTR_MSB_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_READ_PTR_MSB_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x00014018 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00014018 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00014018 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_MAXk 27 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_INI2(n,k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_ADDR(n,k), HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_ADDR(n,k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_WRITE_PTR_LSB_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_WRITE_PTR_LSB_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x0001401c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001401c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001401c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_MAXk 27 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_INI2(n,k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_ADDR(n,k), HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_ADDR(n,k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_WRITE_PTR_MSB_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_WRITE_PTR_MSB_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_8_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x00014020 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_8_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00014020 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_8_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00014020 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_8_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_8_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_8_MAXk 27 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_8_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_8_INI2(n,k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_8_ADDR(n,k), HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_8_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_8_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_8_ADDR(n,k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_8_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_8_ADDR(n,k),val) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_8_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_8_ADDR(n,k),mask,val,HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_8_INI2(n,k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_8_DB_MSI_DATA_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_8_DB_MSI_DATA_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x00014024 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00014024 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00014024 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_RMSK 0xf +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_MAXk 27 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_INI2(n,k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_ADDR(n,k), HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_ADDR(n,k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_ELEM_SIZE_SHIFT_BMSK 0xf +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_ELEM_SIZE_SHIFT_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_ELEM_SIZE_SHIFT_TWO_FVAL 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_ELEM_SIZE_SHIFT_THREE_FVAL 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_ELEM_SIZE_SHIFT_FOUR_FVAL 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_ELEM_SIZE_SHIFT_FIVE_FVAL 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_ELEM_SIZE_SHIFT_SIX_FVAL 0x4 + +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x00014028 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00014028 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00014028 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_RMSK 0xffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_MAXk 27 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_INI2(n,k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_ADDR(n,k), HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_ADDR(n,k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_ADDR(n,k),val) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_ADDR(n,k),mask,val,HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_INI2(n,k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_CH_ALMST_EMPTY_THRSHOLD_BMSK 0xffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_CH_ALMST_EMPTY_THRSHOLD_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x00014040 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00014040 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00014040 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_RMSK 0xffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_MAXk 27 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_INI2(n,k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_ADDR(n,k), HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_ADDR(n,k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_ADDR(n,k),val) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_ADDR(n,k),mask,val,HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_INI2(n,k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_READ_PTR_BMSK 0xffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_READ_PTR_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x00014044 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00014044 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00014044 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_RMSK 0xffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_MAXk 27 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_INI2(n,k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_ADDR(n,k), HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_ADDR(n,k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_ADDR(n,k),val) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_ADDR(n,k),mask,val,HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_INI2(n,k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_RE_INTR_DB_BMSK 0xffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_RE_INTR_DB_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x00014048 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00014048 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00014048 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_RMSK 0x3ff3f0f +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_MAXk 27 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_INI2(n,k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_ADDR(n,k), HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_ADDR(n,k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_ADDR(n,k),val) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_ADDR(n,k),mask,val,HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_INI2(n,k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_LOW_LATENCY_EN_BMSK 0x2000000 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_LOW_LATENCY_EN_SHFT 0x19 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_DB_IN_BYTES_BMSK 0x1000000 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_DB_IN_BYTES_SHFT 0x18 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_EMPTY_LVL_THRSHOLD_BMSK 0xff0000 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_EMPTY_LVL_THRSHOLD_SHFT 0x10 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_PREFETCH_MODE_BMSK 0x3c00 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_PREFETCH_MODE_SHFT 0xa +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_PREFETCH_MODE_USE_PREFETCH_BUFS_FVAL 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_PREFETCH_MODE_ESCAPE_BUF_ONLY_FVAL 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_PREFETCH_MODE_SMART_PRE_FETCH_FVAL 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_PREFETCH_MODE_FREE_PRE_FETCH_FVAL 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_USE_DB_ENG_BMSK 0x200 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_USE_DB_ENG_SHFT 0x9 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_MAX_PREFETCH_BMSK 0x100 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_MAX_PREFETCH_SHFT 0x8 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_MAX_PREFETCH_ONE_PREFETCH_SEG_FVAL 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_MAX_PREFETCH_TWO_PREFETCH_SEG_FVAL 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_WRR_WEIGHT_BMSK 0xf +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_WRR_WEIGHT_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x0001404c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001404c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001404c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_MAXk 27 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_INI2(n,k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_ADDR(n,k), HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_ADDR(n,k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_ADDR(n,k),val) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_ADDR(n,k),mask,val,HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_INI2(n,k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_SCRATCH_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_SCRATCH_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x00014050 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00014050 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00014050 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_MAXk 27 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_INI2(n,k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_ADDR(n,k), HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_ADDR(n,k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_ADDR(n,k),val) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_ADDR(n,k),mask,val,HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_INI2(n,k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_SCRATCH_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_SCRATCH_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x00014054 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00014054 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00014054 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_MAXk 27 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_INI2(n,k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_ADDR(n,k), HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_ADDR(n,k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_ADDR(n,k),val) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_ADDR(n,k),mask,val,HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_INI2(n,k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_SCRATCH_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_SCRATCH_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x00014058 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00014058 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00014058 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_MAXk 27 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_INI2(n,k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_ADDR(n,k), HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_ADDR(n,k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_ADDR(n,k),val) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_ADDR(n,k),mask,val,HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_INI2(n,k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_SCRATCH_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_SCRATCH_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_4_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x0001405c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_4_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001405c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_4_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001405c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_4_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_4_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_4_MAXk 27 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_4_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_4_INI2(n,k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_4_ADDR(n,k), HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_4_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_4_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_4_ADDR(n,k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_4_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_4_ADDR(n,k),val) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_4_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_4_ADDR(n,k),mask,val,HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_4_INI2(n,k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_4_SCRATCH_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_4_SCRATCH_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_5_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x00014060 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_5_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00014060 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_5_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00014060 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_5_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_5_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_5_MAXk 27 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_5_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_5_INI2(n,k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_5_ADDR(n,k), HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_5_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_5_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_5_ADDR(n,k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_5_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_5_ADDR(n,k),val) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_5_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_5_ADDR(n,k),mask,val,HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_5_INI2(n,k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_5_SCRATCH_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_5_SCRATCH_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_6_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x00014064 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_6_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00014064 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_6_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00014064 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_6_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_6_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_6_MAXk 27 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_6_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_6_INI2(n,k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_6_ADDR(n,k), HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_6_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_6_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_6_ADDR(n,k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_6_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_6_ADDR(n,k),val) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_6_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_6_ADDR(n,k),mask,val,HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_6_INI2(n,k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_6_SCRATCH_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_6_SCRATCH_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_7_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x00014068 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_7_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00014068 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_7_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00014068 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_7_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_7_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_7_MAXk 27 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_7_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_7_INI2(n,k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_7_ADDR(n,k), HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_7_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_7_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_7_ADDR(n,k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_7_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_7_ADDR(n,k),val) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_7_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_7_ADDR(n,k),mask,val,HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_7_INI2(n,k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_7_SCRATCH_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_7_SCRATCH_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_8_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x0001406c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_8_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001406c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_8_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001406c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_8_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_8_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_8_MAXk 27 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_8_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_8_INI2(n,k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_8_ADDR(n,k), HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_8_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_8_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_8_ADDR(n,k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_8_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_8_ADDR(n,k),val) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_8_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_8_ADDR(n,k),mask,val,HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_8_INI2(n,k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_8_SCRATCH_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_8_SCRATCH_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_9_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x00014070 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_9_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00014070 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_9_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00014070 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_9_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_9_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_9_MAXk 27 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_9_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_9_INI2(n,k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_9_ADDR(n,k), HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_9_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_9_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_9_ADDR(n,k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_9_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_9_ADDR(n,k),val) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_9_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_9_ADDR(n,k),mask,val,HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_9_INI2(n,k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_9_SCRATCH_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_9_SCRATCH_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x00014074 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00014074 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00014074 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_RMSK 0xffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_MAXk 27 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_INI2(n,k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_ADDR(n,k), HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_ADDR(n,k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_ADDR(n,k),val) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_ADDR(n,k),mask,val,HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_INI2(n,k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_LAST_DB_2_MCS_BMSK 0xffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_LAST_DB_2_MCS_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x0001c000 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c000 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c000 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_MAXk 26 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_INI2(n,k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_ADDR(n,k), HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_ADDR(n,k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_ADDR(n,k),val) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_ADDR(n,k),mask,val,HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_INI2(n,k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_ELEMENT_SIZE_BMSK 0xff000000 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_ELEMENT_SIZE_SHFT 0x18 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_CHSTATE_BMSK 0xf00000 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_CHSTATE_SHFT 0x14 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_CHSTATE_NOT_ALLOCATED_FVAL 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_CHSTATE_ALLOCATED_FVAL 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_EE_BMSK 0xf0000 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_EE_SHFT 0x10 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_EVCHID_BMSK 0xff00 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_EVCHID_SHFT 0x8 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_INTYPE_BMSK 0x80 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_INTYPE_SHFT 0x7 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_INTYPE_MSI_FVAL 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_INTYPE_IRQ_FVAL 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_CHTYPE_BMSK 0x7f +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_CHTYPE_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_CHTYPE_MHI_EV_FVAL 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_CHTYPE_XHCI_EV_FVAL 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_CHTYPE_GPI_EV_FVAL 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_CHTYPE_XDCI_FVAL 0x3 + +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x0001c004 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c004 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c004 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_RMSK 0xffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_MAXk 26 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_INI2(n,k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_ADDR(n,k), HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_ADDR(n,k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_ADDR(n,k),val) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_ADDR(n,k),mask,val,HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_INI2(n,k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_R_LENGTH_BMSK 0xffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_R_LENGTH_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x0001c008 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c008 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c008 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_MAXk 26 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_INI2(n,k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_ADDR(n,k), HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_ADDR(n,k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_ADDR(n,k),val) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_ADDR(n,k),mask,val,HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_INI2(n,k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_R_BASE_ADDR_LSBS_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_R_BASE_ADDR_LSBS_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x0001c00c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c00c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c00c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_MAXk 26 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_INI2(n,k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_ADDR(n,k), HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_ADDR(n,k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_ADDR(n,k),val) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_ADDR(n,k),mask,val,HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_INI2(n,k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_R_BASE_ADDR_MSBS_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_R_BASE_ADDR_MSBS_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x0001c010 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c010 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c010 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_MAXk 26 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_INI2(n,k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_ADDR(n,k), HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_ADDR(n,k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_ADDR(n,k),val) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_ADDR(n,k),mask,val,HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_INI2(n,k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_READ_PTR_LSB_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_READ_PTR_LSB_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x0001c014 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c014 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c014 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_MAXk 26 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_INI2(n,k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_ADDR(n,k), HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_ADDR(n,k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_READ_PTR_MSB_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_READ_PTR_MSB_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x0001c018 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c018 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c018 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_MAXk 26 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_INI2(n,k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_ADDR(n,k), HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_ADDR(n,k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_WRITE_PTR_LSB_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_WRITE_PTR_LSB_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x0001c01c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c01c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c01c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_MAXk 26 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_INI2(n,k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_ADDR(n,k), HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_ADDR(n,k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_WRITE_PTR_MSB_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_WRITE_PTR_MSB_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x0001c020 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c020 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c020 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_MAXk 26 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_INI2(n,k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_ADDR(n,k), HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_ADDR(n,k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_ADDR(n,k),val) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_ADDR(n,k),mask,val,HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_INI2(n,k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_INT_MOD_CNT_BMSK 0xff000000 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_INT_MOD_CNT_SHFT 0x18 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_INT_MODC_BMSK 0xff0000 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_INT_MODC_SHFT 0x10 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_INT_MODT_BMSK 0xffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_INT_MODT_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x0001c024 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c024 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c024 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_MAXk 26 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_INI2(n,k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_ADDR(n,k), HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_ADDR(n,k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_ADDR(n,k),val) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_ADDR(n,k),mask,val,HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_INI2(n,k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_INTVEC_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_INTVEC_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x0001c028 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c028 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c028 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_MAXk 26 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_INI2(n,k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_ADDR(n,k), HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_ADDR(n,k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_ADDR(n,k),val) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_ADDR(n,k),mask,val,HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_INI2(n,k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_MSI_ADDR_LSB_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_MSI_ADDR_LSB_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x0001c02c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c02c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c02c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_MAXk 26 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_INI2(n,k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_ADDR(n,k), HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_ADDR(n,k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_ADDR(n,k),val) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_ADDR(n,k),mask,val,HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_INI2(n,k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_MSI_ADDR_MSB_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_MSI_ADDR_MSB_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x0001c030 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c030 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c030 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_MAXk 26 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_INI2(n,k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_ADDR(n,k), HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_ADDR(n,k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_ADDR(n,k),val) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_ADDR(n,k),mask,val,HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_INI2(n,k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_RP_UPDATE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_RP_UPDATE_ADDR_LSB_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x0001c034 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c034 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c034 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_MAXk 26 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_INI2(n,k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_ADDR(n,k), HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_ADDR(n,k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_ADDR(n,k),val) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_ADDR(n,k),mask,val,HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_INI2(n,k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_RP_UPDATE_ADDR_MSB_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_RP_UPDATE_ADDR_MSB_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x0001c038 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c038 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c038 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_RMSK 0xf +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_MAXk 26 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_INI2(n,k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_ADDR(n,k), HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_ADDR(n,k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_ELEM_SIZE_SHIFT_BMSK 0xf +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_ELEM_SIZE_SHIFT_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_ELEM_SIZE_SHIFT_TWO_FVAL 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_ELEM_SIZE_SHIFT_THREE_FVAL 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_ELEM_SIZE_SHIFT_FOUR_FVAL 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_ELEM_SIZE_SHIFT_FIVE_FVAL 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_ELEM_SIZE_SHIFT_SIX_FVAL 0x4 + +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x0001c048 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c048 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c048 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_MAXk 26 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_INI2(n,k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_ADDR(n,k), HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_ADDR(n,k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_ADDR(n,k),val) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_ADDR(n,k),mask,val,HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_INI2(n,k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_SCRATCH_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_SCRATCH_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x0001c04c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c04c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c04c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_MAXk 26 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_INI2(n,k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_ADDR(n,k), HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_ADDR(n,k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_ADDR(n,k),val) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_ADDR(n,k),mask,val,HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_INI2(n,k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_SCRATCH_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_SCRATCH_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_2_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x0001c050 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_2_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c050 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_2_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c050 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_2_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_2_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_2_MAXk 26 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_2_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_2_INI2(n,k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_2_ADDR(n,k), HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_2_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_2_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_2_ADDR(n,k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_2_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_2_ADDR(n,k),val) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_2_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_2_ADDR(n,k),mask,val,HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_2_INI2(n,k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_2_SCRATCH_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_2_SCRATCH_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_0_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x00024000 + 0x12000 * (n) + 0x8 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_0_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00024000 + 0x12000 * (n) + 0x8 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_0_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00024000 + 0x12000 * (n) + 0x8 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_0_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_0_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_0_MAXk 27 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_0_ATTR 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_0_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_0_ADDR(n,k),val) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_0_WRITE_PTR_LSB_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_0_WRITE_PTR_LSB_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_1_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x00024004 + 0x12000 * (n) + 0x8 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_1_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00024004 + 0x12000 * (n) + 0x8 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_1_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00024004 + 0x12000 * (n) + 0x8 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_1_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_1_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_1_MAXk 27 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_1_ATTR 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_1_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_1_ADDR(n,k),val) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_1_WRITE_PTR_MSB_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_1_WRITE_PTR_MSB_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_DOORBELL_0_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x00024800 + 0x12000 * (n) + 0x8 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_DOORBELL_0_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00024800 + 0x12000 * (n) + 0x8 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_DOORBELL_0_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00024800 + 0x12000 * (n) + 0x8 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_DOORBELL_0_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_DOORBELL_0_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_DOORBELL_0_MAXk 26 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_DOORBELL_0_ATTR 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_DOORBELL_0_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_DOORBELL_0_ADDR(n,k),val) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_DOORBELL_0_WRITE_PTR_LSB_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_DOORBELL_0_WRITE_PTR_LSB_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_DOORBELL_1_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x00024804 + 0x12000 * (n) + 0x8 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_DOORBELL_1_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00024804 + 0x12000 * (n) + 0x8 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_DOORBELL_1_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00024804 + 0x12000 * (n) + 0x8 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_DOORBELL_1_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_DOORBELL_1_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_DOORBELL_1_MAXk 26 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_DOORBELL_1_ATTR 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_DOORBELL_1_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_DOORBELL_1_ADDR(n,k),val) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_DOORBELL_1_WRITE_PTR_MSB_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_DOORBELL_1_WRITE_PTR_MSB_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_GSI_STATUS_ADDR(n) (IPA_GSI_TOP_GSI_REG_BASE + 0x00025000 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_STATUS_PHYS(n) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00025000 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_STATUS_OFFS(n) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00025000 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_STATUS_RMSK 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_STATUS_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_STATUS_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_STATUS_INI(n) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_STATUS_ADDR(n), HWIO_IPA_GSI_TOP_EE_n_GSI_STATUS_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_STATUS_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_STATUS_ADDR(n), mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_STATUS_ENABLED_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_STATUS_ENABLED_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_CMD_ADDR(n) (IPA_GSI_TOP_GSI_REG_BASE + 0x00025008 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_CMD_PHYS(n) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00025008 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_CMD_OFFS(n) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00025008 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_CMD_RMSK 0xff0000ff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_CMD_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_CMD_ATTR 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_CMD_OUTI(n,val) \ + out_dword(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_CMD_ADDR(n),val) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_CMD_OPCODE_BMSK 0xff000000 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_CMD_OPCODE_SHFT 0x18 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_CMD_OPCODE_ALLOCATE_FVAL 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_CMD_OPCODE_START_FVAL 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_CMD_OPCODE_STOP_FVAL 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_CMD_OPCODE_RESET_FVAL 0x9 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_CMD_OPCODE_DE_ALLOC_FVAL 0xa +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_CMD_OPCODE_DB_STOP_FVAL 0xb +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_CMD_CHID_BMSK 0xff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_CMD_CHID_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_CMD_ADDR(n) (IPA_GSI_TOP_GSI_REG_BASE + 0x00025010 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_CMD_PHYS(n) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00025010 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_CMD_OFFS(n) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00025010 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_CMD_RMSK 0xff0000ff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_CMD_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_CMD_ATTR 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_CMD_OUTI(n,val) \ + out_dword(HWIO_IPA_GSI_TOP_EE_n_EV_CH_CMD_ADDR(n),val) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_CMD_OPCODE_BMSK 0xff000000 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_CMD_OPCODE_SHFT 0x18 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_CMD_OPCODE_ALLOCATE_FVAL 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_CMD_OPCODE_RESET_FVAL 0x9 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_CMD_OPCODE_DE_ALLOC_FVAL 0xa +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_CMD_CHID_BMSK 0xff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_CMD_CHID_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_GSI_EE_GENERIC_CMD_ADDR(n) (IPA_GSI_TOP_GSI_REG_BASE + 0x00025018 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_EE_GENERIC_CMD_PHYS(n) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00025018 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_EE_GENERIC_CMD_OFFS(n) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00025018 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_EE_GENERIC_CMD_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_EE_GENERIC_CMD_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_EE_GENERIC_CMD_ATTR 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_EE_GENERIC_CMD_OUTI(n,val) \ + out_dword(HWIO_IPA_GSI_TOP_EE_n_GSI_EE_GENERIC_CMD_ADDR(n),val) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_EE_GENERIC_CMD_OPCODE_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_EE_GENERIC_CMD_OPCODE_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_0_ADDR(n) (IPA_GSI_TOP_GSI_REG_BASE + 0x00025038 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_0_PHYS(n) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00025038 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_0_OFFS(n) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00025038 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_0_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_0_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_0_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_0_INI(n) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_0_ADDR(n), HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_0_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_0_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_0_ADDR(n), mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_0_USE_AXI_M_BMSK 0x80000000 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_0_USE_AXI_M_SHFT 0x1f +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_0_PERIPH_SEC_GRP_BMSK 0x7c000000 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_0_PERIPH_SEC_GRP_SHFT 0x1a +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_0_PERIPH_CONF_ADDR_BUS_W_BMSK 0x3e00000 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_0_PERIPH_CONF_ADDR_BUS_W_SHFT 0x15 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_0_NUM_EES_BMSK 0x1f0000 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_0_NUM_EES_SHFT 0x10 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_0_GSI_CH_NUM_BMSK 0xff00 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_0_GSI_CH_NUM_SHFT 0x8 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_0_GSI_EV_CH_NUM_BMSK 0xff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_0_GSI_EV_CH_NUM_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_1_ADDR(n) (IPA_GSI_TOP_GSI_REG_BASE + 0x0002503c + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_1_PHYS(n) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0002503c + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_1_OFFS(n) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0002503c + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_1_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_1_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_1_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_1_INI(n) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_1_ADDR(n), HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_1_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_1_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_1_ADDR(n), mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_1_GSI_BLK_INT_ACCESS_REGION_2_EN_BMSK 0x80000000 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_1_GSI_BLK_INT_ACCESS_REGION_2_EN_SHFT 0x1f +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_1_GSI_BLK_INT_ACCESS_REGION_1_EN_BMSK 0x40000000 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_1_GSI_BLK_INT_ACCESS_REGION_1_EN_SHFT 0x1e +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_1_GSI_SIMPLE_RD_WR_BMSK 0x20000000 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_1_GSI_SIMPLE_RD_WR_SHFT 0x1d +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_1_GSI_ESCAPE_BUF_ONLY_BMSK 0x10000000 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_1_GSI_ESCAPE_BUF_ONLY_SHFT 0x1c +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_1_GSI_USE_UC_IF_BMSK 0x8000000 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_1_GSI_USE_UC_IF_SHFT 0x1b +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_1_GSI_USE_DB_ENG_BMSK 0x4000000 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_1_GSI_USE_DB_ENG_SHFT 0x1a +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_1_GSI_USE_BP_MTRIX_BMSK 0x2000000 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_1_GSI_USE_BP_MTRIX_SHFT 0x19 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_1_GSI_NUM_TIMERS_BMSK 0x1f00000 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_1_GSI_NUM_TIMERS_SHFT 0x14 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_1_GSI_USE_XPU_BMSK 0x80000 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_1_GSI_USE_XPU_SHFT 0x13 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_1_GSI_QRIB_EN_BMSK 0x40000 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_1_GSI_QRIB_EN_SHFT 0x12 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_1_GSI_VMIDACR_EN_BMSK 0x20000 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_1_GSI_VMIDACR_EN_SHFT 0x11 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_1_GSI_SEC_EN_BMSK 0x10000 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_1_GSI_SEC_EN_SHFT 0x10 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_1_GSI_NONSEC_EN_BMSK 0xf000 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_1_GSI_NONSEC_EN_SHFT 0xc +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_1_GSI_NUM_QAD_BMSK 0xf00 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_1_GSI_NUM_QAD_SHFT 0x8 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_1_GSI_M_DATA_BUS_W_BMSK 0xff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_1_GSI_M_DATA_BUS_W_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_2_ADDR(n) (IPA_GSI_TOP_GSI_REG_BASE + 0x00025040 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_2_PHYS(n) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00025040 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_2_OFFS(n) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00025040 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_2_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_2_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_2_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_2_INI(n) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_2_ADDR(n), HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_2_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_2_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_2_ADDR(n), mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_2_GSI_USE_INTER_EE_BMSK 0x80000000 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_2_GSI_USE_INTER_EE_SHFT 0x1f +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_2_GSI_USE_RD_WR_ENG_BMSK 0x40000000 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_2_GSI_USE_RD_WR_ENG_SHFT 0x1e +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_2_GSI_SDMA_N_IOVEC_BMSK 0x38000000 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_2_GSI_SDMA_N_IOVEC_SHFT 0x1b +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_2_GSI_SDMA_MAX_BURST_BMSK 0x7f80000 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_2_GSI_SDMA_MAX_BURST_SHFT 0x13 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_2_GSI_SDMA_N_INT_BMSK 0x70000 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_2_GSI_SDMA_N_INT_SHFT 0x10 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_2_GSI_USE_SDMA_BMSK 0x8000 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_2_GSI_USE_SDMA_SHFT 0xf +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_2_GSI_CH_FULL_LOGIC_BMSK 0x4000 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_2_GSI_CH_FULL_LOGIC_SHFT 0xe +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_2_GSI_CH_PEND_TRANSLATE_BMSK 0x2000 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_2_GSI_CH_PEND_TRANSLATE_SHFT 0xd +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_BMSK 0x1f00 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_SHFT 0x8 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_ONE_KB_FVAL 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_TWO_KB_FVAL 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_TWO_N_HALF_KB_FVAL 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_THREE_KB_FVAL 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_THREE_N_HALF_KB_FVAL 0x4 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_FOUR_KB_FVAL 0x5 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_2_GSI_NUM_CH_PER_EE_BMSK 0xff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_2_GSI_NUM_CH_PER_EE_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_GSI_SW_VERSION_ADDR(n) (IPA_GSI_TOP_GSI_REG_BASE + 0x00025044 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_SW_VERSION_PHYS(n) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00025044 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_SW_VERSION_OFFS(n) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00025044 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_SW_VERSION_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_SW_VERSION_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_SW_VERSION_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_SW_VERSION_INI(n) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_SW_VERSION_ADDR(n), HWIO_IPA_GSI_TOP_EE_n_GSI_SW_VERSION_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_SW_VERSION_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_SW_VERSION_ADDR(n), mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_SW_VERSION_MAJOR_BMSK 0xf0000000 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_SW_VERSION_MAJOR_SHFT 0x1c +#define HWIO_IPA_GSI_TOP_EE_n_GSI_SW_VERSION_MINOR_BMSK 0xfff0000 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_SW_VERSION_MINOR_SHFT 0x10 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_SW_VERSION_STEP_BMSK 0xffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_SW_VERSION_STEP_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_GSI_MCS_CODE_VER_ADDR(n) (IPA_GSI_TOP_GSI_REG_BASE + 0x00025048 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_MCS_CODE_VER_PHYS(n) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00025048 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_MCS_CODE_VER_OFFS(n) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00025048 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_MCS_CODE_VER_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_MCS_CODE_VER_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_MCS_CODE_VER_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_MCS_CODE_VER_INI(n) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_MCS_CODE_VER_ADDR(n), HWIO_IPA_GSI_TOP_EE_n_GSI_MCS_CODE_VER_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_MCS_CODE_VER_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_MCS_CODE_VER_ADDR(n), mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_MCS_CODE_VER_VER_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_MCS_CODE_VER_VER_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_3_ADDR(n) (IPA_GSI_TOP_GSI_REG_BASE + 0x0002504c + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_3_PHYS(n) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0002504c + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_3_OFFS(n) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0002504c + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_3_RMSK 0x1fffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_3_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_3_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_3_INI(n) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_3_ADDR(n), HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_3_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_3_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_3_ADDR(n), mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_3_GSI_USE_DB_MSI_MODE_BMSK 0x10000000 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_3_GSI_USE_DB_MSI_MODE_SHFT 0x1c +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_3_GSI_USE_SLEEP_CLK_DIV_BMSK 0x8000000 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_3_GSI_USE_SLEEP_CLK_DIV_SHFT 0x1b +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_3_GSI_USE_VIR_CH_IF_BMSK 0x4000000 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_3_GSI_USE_VIR_CH_IF_SHFT 0x1a +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_3_GSI_USE_IROM_BMSK 0x2000000 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_3_GSI_USE_IROM_SHFT 0x19 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_3_GSI_REE_MAX_BURST_LEN_BMSK 0x1f00000 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_3_GSI_REE_MAX_BURST_LEN_SHFT 0x14 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_3_GSI_M_ADDR_BUS_W_BMSK 0xff000 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_3_GSI_M_ADDR_BUS_W_SHFT 0xc +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_3_GSI_NUM_PREFETCH_BUFS_BMSK 0xf00 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_3_GSI_NUM_PREFETCH_BUFS_SHFT 0x8 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_3_GSI_SDMA_MAX_OS_WR_BMSK 0xf0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_3_GSI_SDMA_MAX_OS_WR_SHFT 0x4 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_3_GSI_SDMA_MAX_OS_RD_BMSK 0xf +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_3_GSI_SDMA_MAX_OS_RD_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_4_ADDR(n) (IPA_GSI_TOP_GSI_REG_BASE + 0x00025050 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_4_PHYS(n) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00025050 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_4_OFFS(n) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00025050 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_4_RMSK 0xffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_4_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_4_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_4_INI(n) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_4_ADDR(n), HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_4_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_4_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_4_ADDR(n), mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_4_GSI_IRAM_PROTCOL_CNT_BMSK 0xff00 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_4_GSI_IRAM_PROTCOL_CNT_SHFT 0x8 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_4_GSI_NUM_EV_PER_EE_BMSK 0xff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_4_GSI_NUM_EV_PER_EE_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_ADDR(n) (IPA_GSI_TOP_GSI_REG_BASE + 0x00025080 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_PHYS(n) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00025080 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_OFFS(n) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00025080 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_RMSK 0x7f +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_INI(n) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_ADDR(n), HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_ADDR(n), mask) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_GENERAL_BMSK 0x40 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_GENERAL_SHFT 0x6 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_INTER_EE_EV_CTRL_BMSK 0x20 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_INTER_EE_EV_CTRL_SHFT 0x5 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_INTER_EE_CH_CTRL_BMSK 0x10 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_INTER_EE_CH_CTRL_SHFT 0x4 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_IEOB_BMSK 0x8 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_IEOB_SHFT 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_GLOB_EE_BMSK 0x4 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_GLOB_EE_SHFT 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_EV_CTRL_BMSK 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_EV_CTRL_SHFT 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_CH_CTRL_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_CH_CTRL_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_ADDR(n) (IPA_GSI_TOP_GSI_REG_BASE + 0x00025088 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_PHYS(n) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00025088 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_OFFS(n) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00025088 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_RMSK 0x7f +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_INI(n) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_ADDR(n), HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_ADDR(n), mask) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_OUTI(n,val) \ + out_dword(HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_ADDR(n),val) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_ADDR(n),mask,val,HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_INI(n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_GENERAL_BMSK 0x40 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_GENERAL_SHFT 0x6 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_INTER_EE_EV_CTRL_BMSK 0x20 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_INTER_EE_EV_CTRL_SHFT 0x5 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_INTER_EE_CH_CTRL_BMSK 0x10 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_INTER_EE_CH_CTRL_SHFT 0x4 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_IEOB_BMSK 0x8 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_IEOB_SHFT 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_GLOB_EE_BMSK 0x4 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_GLOB_EE_SHFT 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_EV_CTRL_BMSK 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_EV_CTRL_SHFT 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_CH_CTRL_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_CH_CTRL_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_k_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x00025090 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_k_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00025090 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_k_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00025090 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_k_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_k_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_k_MAXk 0 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_k_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_k_INI2(n,k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_k_ADDR(n,k), HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_k_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_k_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_k_ADDR(n,k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_k_GSI_CH_BIT_MAP_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_k_GSI_CH_BIT_MAP_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x00025094 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00025094 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00025094 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_MAXk 0 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_INI2(n,k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_ADDR(n,k), HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_ADDR(n,k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_ADDR(n,k),val) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_ADDR(n,k),mask,val,HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_INI2(n,k)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_GSI_CH_BIT_MAP_MSK_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_GSI_CH_BIT_MAP_MSK_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_k_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x00025098 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_k_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00025098 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_k_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00025098 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_k_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_k_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_k_MAXk 0 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_k_ATTR 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_k_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_k_ADDR(n,k),val) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_k_GSI_CH_BIT_MAP_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_k_GSI_CH_BIT_MAP_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_k_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x0002509c + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_k_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0002509c + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_k_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0002509c + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_k_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_k_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_k_MAXk 0 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_k_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_k_INI2(n,k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_k_ADDR(n,k), HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_k_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_k_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_k_ADDR(n,k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_k_EV_CH_BIT_MAP_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_k_EV_CH_BIT_MAP_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x000250a0 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000250a0 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000250a0 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_MAXk 0 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_INI2(n,k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_ADDR(n,k), HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_ADDR(n,k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_ADDR(n,k),val) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_ADDR(n,k),mask,val,HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_INI2(n,k)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_EV_CH_BIT_MAP_MSK_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_EV_CH_BIT_MAP_MSK_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_k_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x000250a4 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_k_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000250a4 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_k_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000250a4 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_k_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_k_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_k_MAXk 0 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_k_ATTR 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_k_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_k_ADDR(n,k),val) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_k_EV_CH_BIT_MAP_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_k_EV_CH_BIT_MAP_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_k_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x000250a8 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_k_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000250a8 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_k_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000250a8 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_k_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_k_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_k_MAXk 0 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_k_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_k_INI2(n,k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_k_ADDR(n,k), HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_k_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_k_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_k_ADDR(n,k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_k_EV_CH_BIT_MAP_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_k_EV_CH_BIT_MAP_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x000250ac + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000250ac + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000250ac + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_MAXk 0 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_INI2(n,k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_ADDR(n,k), HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_ADDR(n,k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_ADDR(n,k),val) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_ADDR(n,k),mask,val,HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_INI2(n,k)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_EV_CH_BIT_MAP_MSK_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_EV_CH_BIT_MAP_MSK_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_k_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x000250b0 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_k_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000250b0 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_k_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000250b0 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_k_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_k_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_k_MAXk 0 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_k_ATTR 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_k_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_k_ADDR(n,k),val) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_k_EV_CH_BIT_MAP_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_k_EV_CH_BIT_MAP_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_ADDR(n) (IPA_GSI_TOP_GSI_REG_BASE + 0x00025200 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_PHYS(n) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00025200 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_OFFS(n) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00025200 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_RMSK 0xf +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_INI(n) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_ADDR(n), HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_ADDR(n), mask) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT3_BMSK 0x8 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT3_SHFT 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT2_BMSK 0x4 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT2_SHFT 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT1_BMSK 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT1_SHFT 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_ERROR_INT_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_ERROR_INT_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_EN_ADDR(n) (IPA_GSI_TOP_GSI_REG_BASE + 0x00025204 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_EN_PHYS(n) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00025204 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_EN_OFFS(n) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00025204 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_EN_RMSK 0xf +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_EN_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_EN_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_EN_INI(n) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_EN_ADDR(n), HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_EN_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_EN_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_EN_ADDR(n), mask) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_EN_OUTI(n,val) \ + out_dword(HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_EN_ADDR(n),val) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_EN_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_EN_ADDR(n),mask,val,HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_EN_INI(n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_EN_GP_INT3_BMSK 0x8 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_EN_GP_INT3_SHFT 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_EN_GP_INT2_BMSK 0x4 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_EN_GP_INT2_SHFT 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_EN_GP_INT1_BMSK 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_EN_GP_INT1_SHFT 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_EN_ERROR_INT_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_EN_ERROR_INT_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_CLR_ADDR(n) (IPA_GSI_TOP_GSI_REG_BASE + 0x00025208 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_CLR_PHYS(n) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00025208 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_CLR_OFFS(n) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00025208 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_CLR_RMSK 0xf +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_CLR_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_CLR_ATTR 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_CLR_OUTI(n,val) \ + out_dword(HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_CLR_ADDR(n),val) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_CLR_GP_INT3_BMSK 0x8 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_CLR_GP_INT3_SHFT 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_CLR_GP_INT2_BMSK 0x4 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_CLR_GP_INT2_SHFT 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_CLR_GP_INT1_BMSK 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_CLR_GP_INT1_SHFT 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_CLR_ERROR_INT_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_CLR_ERROR_INT_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_ADDR(n) (IPA_GSI_TOP_GSI_REG_BASE + 0x0002520c + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_PHYS(n) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0002520c + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_OFFS(n) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0002520c + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_RMSK 0xf +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_INI(n) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_ADDR(n), HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_ADDR(n), mask) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_GSI_MCS_STACK_OVRFLOW_BMSK 0x8 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_GSI_MCS_STACK_OVRFLOW_SHFT 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_GSI_CMD_FIFO_OVRFLOW_BMSK 0x4 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_GSI_CMD_FIFO_OVRFLOW_SHFT 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_GSI_BUS_ERROR_BMSK 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_GSI_BUS_ERROR_SHFT 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_GSI_BREAK_POINT_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_GSI_BREAK_POINT_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_EN_ADDR(n) (IPA_GSI_TOP_GSI_REG_BASE + 0x00025210 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_EN_PHYS(n) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00025210 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_EN_OFFS(n) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00025210 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_EN_RMSK 0xf +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_EN_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_EN_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_EN_INI(n) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_EN_ADDR(n), HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_EN_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_EN_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_EN_ADDR(n), mask) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_EN_OUTI(n,val) \ + out_dword(HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_EN_ADDR(n),val) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_EN_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_EN_ADDR(n),mask,val,HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_EN_INI(n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_EN_GSI_MCS_STACK_OVRFLOW_BMSK 0x8 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_EN_GSI_MCS_STACK_OVRFLOW_SHFT 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_EN_GSI_CMD_FIFO_OVRFLOW_BMSK 0x4 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_EN_GSI_CMD_FIFO_OVRFLOW_SHFT 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_EN_GSI_BUS_ERROR_BMSK 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_EN_GSI_BUS_ERROR_SHFT 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_EN_GSI_BREAK_POINT_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_EN_GSI_BREAK_POINT_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_CLR_ADDR(n) (IPA_GSI_TOP_GSI_REG_BASE + 0x00025214 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_CLR_PHYS(n) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00025214 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_CLR_OFFS(n) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00025214 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_CLR_RMSK 0xf +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_CLR_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_CLR_ATTR 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_CLR_OUTI(n,val) \ + out_dword(HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_CLR_ADDR(n),val) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_CLR_GSI_MCS_STACK_OVRFLOW_BMSK 0x8 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_CLR_GSI_MCS_STACK_OVRFLOW_SHFT 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_CLR_GSI_CMD_FIFO_OVRFLOW_BMSK 0x4 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_CLR_GSI_CMD_FIFO_OVRFLOW_SHFT 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_CLR_GSI_BUS_ERROR_BMSK 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_CLR_GSI_BUS_ERROR_SHFT 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_CLR_GSI_BREAK_POINT_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_CLR_GSI_BREAK_POINT_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_INTSET_ADDR(n) (IPA_GSI_TOP_GSI_REG_BASE + 0x00025220 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_INTSET_PHYS(n) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00025220 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_INTSET_OFFS(n) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00025220 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_INTSET_RMSK 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_INTSET_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_INTSET_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_INTSET_INI(n) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_CNTXT_INTSET_ADDR(n), HWIO_IPA_GSI_TOP_EE_n_CNTXT_INTSET_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_INTSET_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_CNTXT_INTSET_ADDR(n), mask) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_INTSET_OUTI(n,val) \ + out_dword(HWIO_IPA_GSI_TOP_EE_n_CNTXT_INTSET_ADDR(n),val) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_INTSET_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_CNTXT_INTSET_ADDR(n),mask,val,HWIO_IPA_GSI_TOP_EE_n_CNTXT_INTSET_INI(n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_INTSET_INTYPE_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_INTSET_INTYPE_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_INTSET_INTYPE_MSI_FVAL 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_INTSET_INTYPE_IRQ_FVAL 0x1 + +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB_ADDR(n) (IPA_GSI_TOP_GSI_REG_BASE + 0x00025230 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB_PHYS(n) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00025230 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB_OFFS(n) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00025230 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB_INI(n) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB_ADDR(n), HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB_ADDR(n), mask) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB_OUTI(n,val) \ + out_dword(HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB_ADDR(n),val) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB_ADDR(n),mask,val,HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB_INI(n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB_MSI_ADDR_LSB_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB_MSI_ADDR_LSB_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_MSB_ADDR(n) (IPA_GSI_TOP_GSI_REG_BASE + 0x00025234 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_MSB_PHYS(n) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00025234 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_MSB_OFFS(n) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00025234 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_MSB_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_MSB_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_MSB_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_MSB_INI(n) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_MSB_ADDR(n), HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_MSB_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_MSB_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_MSB_ADDR(n), mask) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_MSB_OUTI(n,val) \ + out_dword(HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_MSB_ADDR(n),val) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_MSB_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_MSB_ADDR(n),mask,val,HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_MSB_INI(n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_MSB_MSI_ADDR_MSB_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_MSB_MSI_ADDR_MSB_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_INT_VEC_ADDR(n) (IPA_GSI_TOP_GSI_REG_BASE + 0x00025238 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_INT_VEC_PHYS(n) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00025238 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_INT_VEC_OFFS(n) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00025238 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_INT_VEC_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_INT_VEC_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_INT_VEC_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_INT_VEC_INI(n) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_CNTXT_INT_VEC_ADDR(n), HWIO_IPA_GSI_TOP_EE_n_CNTXT_INT_VEC_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_INT_VEC_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_CNTXT_INT_VEC_ADDR(n), mask) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_INT_VEC_OUTI(n,val) \ + out_dword(HWIO_IPA_GSI_TOP_EE_n_CNTXT_INT_VEC_ADDR(n),val) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_INT_VEC_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_CNTXT_INT_VEC_ADDR(n),mask,val,HWIO_IPA_GSI_TOP_EE_n_CNTXT_INT_VEC_INI(n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_INT_VEC_INT_VEC_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_INT_VEC_INT_VEC_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_ADDR(n) (IPA_GSI_TOP_GSI_REG_BASE + 0x00025240 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_PHYS(n) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00025240 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_OFFS(n) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00025240 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_INI(n) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_ADDR(n), HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_ADDR(n), mask) +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_OUTI(n,val) \ + out_dword(HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_ADDR(n),val) +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_ADDR(n),mask,val,HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_INI(n)) +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_ERROR_LOG_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_ERROR_LOG_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_CLR_ADDR(n) (IPA_GSI_TOP_GSI_REG_BASE + 0x00025244 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_CLR_PHYS(n) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00025244 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_CLR_OFFS(n) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00025244 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_CLR_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_CLR_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_CLR_ATTR 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_CLR_OUTI(n,val) \ + out_dword(HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_CLR_ADDR(n),val) +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_CLR_ERROR_LOG_CLR_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_CLR_ERROR_LOG_CLR_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_ADDR(n) (IPA_GSI_TOP_GSI_REG_BASE + 0x00025400 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_PHYS(n) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00025400 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_OFFS(n) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00025400 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_INI(n) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_ADDR(n), HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_ADDR(n), mask) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_OUTI(n,val) \ + out_dword(HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_ADDR(n),val) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_ADDR(n),mask,val,HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_INI(n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_SCRATCH_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_SCRATCH_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_ADDR(n) (IPA_GSI_TOP_GSI_REG_BASE + 0x00025404 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_PHYS(n) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00025404 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_OFFS(n) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00025404 + 0x12000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_INI(n) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_ADDR(n), HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_ADDR(n), mask) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_OUTI(n,val) \ + out_dword(HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_ADDR(n),val) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_ADDR(n),mask,val,HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_INI(n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_SCRATCH_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_SCRATCH_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_MCS_CFG_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x0000b000) +#define HWIO_IPA_GSI_TOP_GSI_MCS_CFG_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000b000) +#define HWIO_IPA_GSI_TOP_GSI_MCS_CFG_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000b000) +#define HWIO_IPA_GSI_TOP_GSI_MCS_CFG_RMSK 0x1 +#define HWIO_IPA_GSI_TOP_GSI_MCS_CFG_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_MCS_CFG_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_MCS_CFG_ADDR, HWIO_IPA_GSI_TOP_GSI_MCS_CFG_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_MCS_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_MCS_CFG_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_MCS_CFG_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_MCS_CFG_ADDR,v) +#define HWIO_IPA_GSI_TOP_GSI_MCS_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_MCS_CFG_ADDR,m,v,HWIO_IPA_GSI_TOP_GSI_MCS_CFG_IN) +#define HWIO_IPA_GSI_TOP_GSI_MCS_CFG_MCS_ENABLE_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_GSI_MCS_CFG_MCS_ENABLE_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_TZ_FW_AUTH_LOCK_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x0000b008) +#define HWIO_IPA_GSI_TOP_GSI_TZ_FW_AUTH_LOCK_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000b008) +#define HWIO_IPA_GSI_TOP_GSI_TZ_FW_AUTH_LOCK_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000b008) +#define HWIO_IPA_GSI_TOP_GSI_TZ_FW_AUTH_LOCK_RMSK 0x3 +#define HWIO_IPA_GSI_TOP_GSI_TZ_FW_AUTH_LOCK_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_TZ_FW_AUTH_LOCK_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_TZ_FW_AUTH_LOCK_ADDR, HWIO_IPA_GSI_TOP_GSI_TZ_FW_AUTH_LOCK_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_TZ_FW_AUTH_LOCK_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_TZ_FW_AUTH_LOCK_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_TZ_FW_AUTH_LOCK_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_TZ_FW_AUTH_LOCK_ADDR,v) +#define HWIO_IPA_GSI_TOP_GSI_TZ_FW_AUTH_LOCK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_TZ_FW_AUTH_LOCK_ADDR,m,v,HWIO_IPA_GSI_TOP_GSI_TZ_FW_AUTH_LOCK_IN) +#define HWIO_IPA_GSI_TOP_GSI_TZ_FW_AUTH_LOCK_DIS_DEBUG_SHRAM_WRITE_BMSK 0x2 +#define HWIO_IPA_GSI_TOP_GSI_TZ_FW_AUTH_LOCK_DIS_DEBUG_SHRAM_WRITE_SHFT 0x1 +#define HWIO_IPA_GSI_TOP_GSI_TZ_FW_AUTH_LOCK_DIS_IRAM_WRITE_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_GSI_TZ_FW_AUTH_LOCK_DIS_IRAM_WRITE_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_MSA_FW_AUTH_LOCK_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x0000b010) +#define HWIO_IPA_GSI_TOP_GSI_MSA_FW_AUTH_LOCK_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000b010) +#define HWIO_IPA_GSI_TOP_GSI_MSA_FW_AUTH_LOCK_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000b010) +#define HWIO_IPA_GSI_TOP_GSI_MSA_FW_AUTH_LOCK_RMSK 0x3 +#define HWIO_IPA_GSI_TOP_GSI_MSA_FW_AUTH_LOCK_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_MSA_FW_AUTH_LOCK_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_MSA_FW_AUTH_LOCK_ADDR, HWIO_IPA_GSI_TOP_GSI_MSA_FW_AUTH_LOCK_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_MSA_FW_AUTH_LOCK_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_MSA_FW_AUTH_LOCK_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_MSA_FW_AUTH_LOCK_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_MSA_FW_AUTH_LOCK_ADDR,v) +#define HWIO_IPA_GSI_TOP_GSI_MSA_FW_AUTH_LOCK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_MSA_FW_AUTH_LOCK_ADDR,m,v,HWIO_IPA_GSI_TOP_GSI_MSA_FW_AUTH_LOCK_IN) +#define HWIO_IPA_GSI_TOP_GSI_MSA_FW_AUTH_LOCK_DIS_DEBUG_SHRAM_WRITE_BMSK 0x2 +#define HWIO_IPA_GSI_TOP_GSI_MSA_FW_AUTH_LOCK_DIS_DEBUG_SHRAM_WRITE_SHFT 0x1 +#define HWIO_IPA_GSI_TOP_GSI_MSA_FW_AUTH_LOCK_DIS_IRAM_WRITE_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_GSI_MSA_FW_AUTH_LOCK_DIS_IRAM_WRITE_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_SP_FW_AUTH_LOCK_ADDR (IPA_GSI_TOP_GSI_REG_BASE + 0x0000b018) +#define HWIO_IPA_GSI_TOP_GSI_SP_FW_AUTH_LOCK_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000b018) +#define HWIO_IPA_GSI_TOP_GSI_SP_FW_AUTH_LOCK_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000b018) +#define HWIO_IPA_GSI_TOP_GSI_SP_FW_AUTH_LOCK_RMSK 0x3 +#define HWIO_IPA_GSI_TOP_GSI_SP_FW_AUTH_LOCK_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_SP_FW_AUTH_LOCK_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_SP_FW_AUTH_LOCK_ADDR, HWIO_IPA_GSI_TOP_GSI_SP_FW_AUTH_LOCK_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_SP_FW_AUTH_LOCK_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_SP_FW_AUTH_LOCK_ADDR, m) +#define HWIO_IPA_GSI_TOP_GSI_SP_FW_AUTH_LOCK_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_SP_FW_AUTH_LOCK_ADDR,v) +#define HWIO_IPA_GSI_TOP_GSI_SP_FW_AUTH_LOCK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_SP_FW_AUTH_LOCK_ADDR,m,v,HWIO_IPA_GSI_TOP_GSI_SP_FW_AUTH_LOCK_IN) +#define HWIO_IPA_GSI_TOP_GSI_SP_FW_AUTH_LOCK_DIS_DEBUG_SHRAM_WRITE_BMSK 0x2 +#define HWIO_IPA_GSI_TOP_GSI_SP_FW_AUTH_LOCK_DIS_DEBUG_SHRAM_WRITE_SHFT 0x1 +#define HWIO_IPA_GSI_TOP_GSI_SP_FW_AUTH_LOCK_DIS_IRAM_WRITE_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_GSI_SP_FW_AUTH_LOCK_DIS_IRAM_WRITE_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_INTER_EE_n_ORIGINATOR_EE_ADDR(n) (IPA_GSI_TOP_GSI_REG_BASE + 0x0000c000 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_ORIGINATOR_EE_PHYS(n) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000c000 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_ORIGINATOR_EE_OFFS(n) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000c000 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_ORIGINATOR_EE_RMSK 0xf +#define HWIO_IPA_GSI_TOP_INTER_EE_n_ORIGINATOR_EE_MAXn 2 +#define HWIO_IPA_GSI_TOP_INTER_EE_n_ORIGINATOR_EE_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_INTER_EE_n_ORIGINATOR_EE_INI(n) \ + in_dword_masked(HWIO_IPA_GSI_TOP_INTER_EE_n_ORIGINATOR_EE_ADDR(n), HWIO_IPA_GSI_TOP_INTER_EE_n_ORIGINATOR_EE_RMSK) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_ORIGINATOR_EE_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_INTER_EE_n_ORIGINATOR_EE_ADDR(n), mask) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_ORIGINATOR_EE_OUTI(n,val) \ + out_dword(HWIO_IPA_GSI_TOP_INTER_EE_n_ORIGINATOR_EE_ADDR(n),val) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_ORIGINATOR_EE_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_INTER_EE_n_ORIGINATOR_EE_ADDR(n),mask,val,HWIO_IPA_GSI_TOP_INTER_EE_n_ORIGINATOR_EE_INI(n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_ORIGINATOR_EE_EE_NUMBER_BMSK 0xf +#define HWIO_IPA_GSI_TOP_INTER_EE_n_ORIGINATOR_EE_EE_NUMBER_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_INTER_EE_n_GSI_CH_CMD_ADDR(n) (IPA_GSI_TOP_GSI_REG_BASE + 0x0000c008 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_GSI_CH_CMD_PHYS(n) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000c008 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_GSI_CH_CMD_OFFS(n) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000c008 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_GSI_CH_CMD_RMSK 0xff0000ff +#define HWIO_IPA_GSI_TOP_INTER_EE_n_GSI_CH_CMD_MAXn 2 +#define HWIO_IPA_GSI_TOP_INTER_EE_n_GSI_CH_CMD_ATTR 0x2 +#define HWIO_IPA_GSI_TOP_INTER_EE_n_GSI_CH_CMD_OUTI(n,val) \ + out_dword(HWIO_IPA_GSI_TOP_INTER_EE_n_GSI_CH_CMD_ADDR(n),val) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_GSI_CH_CMD_OPCODE_BMSK 0xff000000 +#define HWIO_IPA_GSI_TOP_INTER_EE_n_GSI_CH_CMD_OPCODE_SHFT 0x18 +#define HWIO_IPA_GSI_TOP_INTER_EE_n_GSI_CH_CMD_OPCODE_START_FVAL 0x1 +#define HWIO_IPA_GSI_TOP_INTER_EE_n_GSI_CH_CMD_OPCODE_STOP_FVAL 0x2 +#define HWIO_IPA_GSI_TOP_INTER_EE_n_GSI_CH_CMD_OPCODE_RESET_FVAL 0x9 +#define HWIO_IPA_GSI_TOP_INTER_EE_n_GSI_CH_CMD_OPCODE_DE_ALLOC_FVAL 0xa +#define HWIO_IPA_GSI_TOP_INTER_EE_n_GSI_CH_CMD_OPCODE_DB_STOP_FVAL 0xb +#define HWIO_IPA_GSI_TOP_INTER_EE_n_GSI_CH_CMD_CHID_BMSK 0xff +#define HWIO_IPA_GSI_TOP_INTER_EE_n_GSI_CH_CMD_CHID_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_INTER_EE_n_EV_CH_CMD_ADDR(n) (IPA_GSI_TOP_GSI_REG_BASE + 0x0000c010 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_EV_CH_CMD_PHYS(n) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000c010 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_EV_CH_CMD_OFFS(n) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000c010 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_EV_CH_CMD_RMSK 0xff0000ff +#define HWIO_IPA_GSI_TOP_INTER_EE_n_EV_CH_CMD_MAXn 2 +#define HWIO_IPA_GSI_TOP_INTER_EE_n_EV_CH_CMD_ATTR 0x2 +#define HWIO_IPA_GSI_TOP_INTER_EE_n_EV_CH_CMD_OUTI(n,val) \ + out_dword(HWIO_IPA_GSI_TOP_INTER_EE_n_EV_CH_CMD_ADDR(n),val) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_EV_CH_CMD_OPCODE_BMSK 0xff000000 +#define HWIO_IPA_GSI_TOP_INTER_EE_n_EV_CH_CMD_OPCODE_SHFT 0x18 +#define HWIO_IPA_GSI_TOP_INTER_EE_n_EV_CH_CMD_OPCODE_RESET_FVAL 0x9 +#define HWIO_IPA_GSI_TOP_INTER_EE_n_EV_CH_CMD_OPCODE_DE_ALLOC_FVAL 0xa +#define HWIO_IPA_GSI_TOP_INTER_EE_n_EV_CH_CMD_CHID_BMSK 0xff +#define HWIO_IPA_GSI_TOP_INTER_EE_n_EV_CH_CMD_CHID_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_k_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x0000c018 + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_k_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000c018 + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_k_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000c018 + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_k_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_k_MAXn 2 +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_k_MAXk 0 +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_k_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_k_INI2(n,k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_k_ADDR(n,k), HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_k_RMSK) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_k_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_k_ADDR(n,k), mask) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_k_GSI_CH_BIT_MAP_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_k_GSI_CH_BIT_MAP_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x0000c01c + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000c01c + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000c01c + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_MAXn 2 +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_MAXk 0 +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_INI2(n,k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_ADDR(n,k), HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_RMSK) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_ADDR(n,k), mask) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_ADDR(n,k),val) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_ADDR(n,k),mask,val,HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_INI2(n,k)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_GSI_CH_BIT_MAP_MSK_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_GSI_CH_BIT_MAP_MSK_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_k_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x0000c020 + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_k_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000c020 + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_k_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000c020 + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_k_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_k_MAXn 2 +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_k_MAXk 0 +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_k_ATTR 0x2 +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_k_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_k_ADDR(n,k),val) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_k_GSI_CH_BIT_MAP_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_k_GSI_CH_BIT_MAP_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_k_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x0000c024 + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_k_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000c024 + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_k_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000c024 + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_k_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_k_MAXn 2 +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_k_MAXk 0 +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_k_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_k_INI2(n,k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_k_ADDR(n,k), HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_k_RMSK) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_k_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_k_ADDR(n,k), mask) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_k_EV_CH_BIT_MAP_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_k_EV_CH_BIT_MAP_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x0000c028 + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000c028 + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000c028 + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_MAXn 2 +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_MAXk 0 +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_INI2(n,k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_ADDR(n,k), HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_RMSK) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_ADDR(n,k), mask) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_ADDR(n,k),val) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_ADDR(n,k),mask,val,HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_INI2(n,k)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_EV_CH_BIT_MAP_MSK_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_EV_CH_BIT_MAP_MSK_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_CLR_k_ADDR(n,k) (IPA_GSI_TOP_GSI_REG_BASE + 0x0000c02c + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_CLR_k_PHYS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000c02c + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_CLR_k_OFFS(n,k) (IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000c02c + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_CLR_k_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_CLR_k_MAXn 2 +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_CLR_k_MAXk 0 +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_CLR_k_ATTR 0x2 +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_CLR_k_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_CLR_k_ADDR(n,k),val) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_CLR_k_EV_CH_BIT_MAP_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_CLR_k_EV_CH_BIT_MAP_SHFT 0x0 + +/*---------------------------------------------------------------------------- + * MODULE: IPA_GSI_TOP_XPU3 + *--------------------------------------------------------------------------*/ + +#define IPA_GSI_TOP_XPU3_REG_BASE (IPA_0_IPA_WRAPPER_BASE + 0x00000000) +#define IPA_GSI_TOP_XPU3_REG_BASE_PHYS (IPA_0_IPA_WRAPPER_BASE_PHYS + 0x00000000) +#define IPA_GSI_TOP_XPU3_REG_BASE_OFFS 0x00000000 + +#define HWIO_IPA_GSI_TOP_XPU3_GCR0_ADDR (IPA_GSI_TOP_XPU3_REG_BASE + 0x00000000) +#define HWIO_IPA_GSI_TOP_XPU3_GCR0_PHYS (IPA_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000000) +#define HWIO_IPA_GSI_TOP_XPU3_GCR0_OFFS (IPA_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000000) +#define HWIO_IPA_GSI_TOP_XPU3_GCR0_RMSK 0x3 +#define HWIO_IPA_GSI_TOP_XPU3_GCR0_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_XPU3_GCR0_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_GCR0_ADDR, HWIO_IPA_GSI_TOP_XPU3_GCR0_RMSK) +#define HWIO_IPA_GSI_TOP_XPU3_GCR0_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_GCR0_ADDR, m) +#define HWIO_IPA_GSI_TOP_XPU3_GCR0_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_XPU3_GCR0_ADDR,v) +#define HWIO_IPA_GSI_TOP_XPU3_GCR0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_XPU3_GCR0_ADDR,m,v,HWIO_IPA_GSI_TOP_XPU3_GCR0_IN) +#define HWIO_IPA_GSI_TOP_XPU3_GCR0_AALOG_MODE_DIS_BMSK 0x2 +#define HWIO_IPA_GSI_TOP_XPU3_GCR0_AALOG_MODE_DIS_SHFT 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_GCR0_AADEN_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_GCR0_AADEN_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_XPU3_SCR0_ADDR (IPA_GSI_TOP_XPU3_REG_BASE + 0x00000008) +#define HWIO_IPA_GSI_TOP_XPU3_SCR0_PHYS (IPA_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000008) +#define HWIO_IPA_GSI_TOP_XPU3_SCR0_OFFS (IPA_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000008) +#define HWIO_IPA_GSI_TOP_XPU3_SCR0_RMSK 0x10f +#define HWIO_IPA_GSI_TOP_XPU3_SCR0_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_XPU3_SCR0_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_SCR0_ADDR, HWIO_IPA_GSI_TOP_XPU3_SCR0_RMSK) +#define HWIO_IPA_GSI_TOP_XPU3_SCR0_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_SCR0_ADDR, m) +#define HWIO_IPA_GSI_TOP_XPU3_SCR0_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_XPU3_SCR0_ADDR,v) +#define HWIO_IPA_GSI_TOP_XPU3_SCR0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_XPU3_SCR0_ADDR,m,v,HWIO_IPA_GSI_TOP_XPU3_SCR0_IN) +#define HWIO_IPA_GSI_TOP_XPU3_SCR0_DYNAMIC_CLK_EN_BMSK 0x100 +#define HWIO_IPA_GSI_TOP_XPU3_SCR0_DYNAMIC_CLK_EN_SHFT 0x8 +#define HWIO_IPA_GSI_TOP_XPU3_SCR0_SCLEIE_BMSK 0x8 +#define HWIO_IPA_GSI_TOP_XPU3_SCR0_SCLEIE_SHFT 0x3 +#define HWIO_IPA_GSI_TOP_XPU3_SCR0_SCFGEIE_BMSK 0x4 +#define HWIO_IPA_GSI_TOP_XPU3_SCR0_SCFGEIE_SHFT 0x2 +#define HWIO_IPA_GSI_TOP_XPU3_SCR0_SCLERE_BMSK 0x2 +#define HWIO_IPA_GSI_TOP_XPU3_SCR0_SCLERE_SHFT 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_SCR0_SCFGERE_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_SCR0_SCFGERE_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_XPU3_CR0_ADDR (IPA_GSI_TOP_XPU3_REG_BASE + 0x00000010) +#define HWIO_IPA_GSI_TOP_XPU3_CR0_PHYS (IPA_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000010) +#define HWIO_IPA_GSI_TOP_XPU3_CR0_OFFS (IPA_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000010) +#define HWIO_IPA_GSI_TOP_XPU3_CR0_RMSK 0x18f +#define HWIO_IPA_GSI_TOP_XPU3_CR0_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_XPU3_CR0_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_CR0_ADDR, HWIO_IPA_GSI_TOP_XPU3_CR0_RMSK) +#define HWIO_IPA_GSI_TOP_XPU3_CR0_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_CR0_ADDR, m) +#define HWIO_IPA_GSI_TOP_XPU3_CR0_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_XPU3_CR0_ADDR,v) +#define HWIO_IPA_GSI_TOP_XPU3_CR0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_XPU3_CR0_ADDR,m,v,HWIO_IPA_GSI_TOP_XPU3_CR0_IN) +#define HWIO_IPA_GSI_TOP_XPU3_CR0_DYNAMIC_CLK_EN_BMSK 0x100 +#define HWIO_IPA_GSI_TOP_XPU3_CR0_DYNAMIC_CLK_EN_SHFT 0x8 +#define HWIO_IPA_GSI_TOP_XPU3_CR0_VMIDEN_BMSK 0x80 +#define HWIO_IPA_GSI_TOP_XPU3_CR0_VMIDEN_SHFT 0x7 +#define HWIO_IPA_GSI_TOP_XPU3_CR0_CLEIE_BMSK 0x8 +#define HWIO_IPA_GSI_TOP_XPU3_CR0_CLEIE_SHFT 0x3 +#define HWIO_IPA_GSI_TOP_XPU3_CR0_CFGEIE_BMSK 0x4 +#define HWIO_IPA_GSI_TOP_XPU3_CR0_CFGEIE_SHFT 0x2 +#define HWIO_IPA_GSI_TOP_XPU3_CR0_CLERE_BMSK 0x2 +#define HWIO_IPA_GSI_TOP_XPU3_CR0_CLERE_SHFT 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_CR0_CFGERE_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_CR0_CFGERE_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_XPU3_RPU_ACR0_ADDR (IPA_GSI_TOP_XPU3_REG_BASE + 0x00000020) +#define HWIO_IPA_GSI_TOP_XPU3_RPU_ACR0_PHYS (IPA_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000020) +#define HWIO_IPA_GSI_TOP_XPU3_RPU_ACR0_OFFS (IPA_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000020) +#define HWIO_IPA_GSI_TOP_XPU3_RPU_ACR0_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_XPU3_RPU_ACR0_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_XPU3_RPU_ACR0_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_RPU_ACR0_ADDR, HWIO_IPA_GSI_TOP_XPU3_RPU_ACR0_RMSK) +#define HWIO_IPA_GSI_TOP_XPU3_RPU_ACR0_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_RPU_ACR0_ADDR, m) +#define HWIO_IPA_GSI_TOP_XPU3_RPU_ACR0_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_XPU3_RPU_ACR0_ADDR,v) +#define HWIO_IPA_GSI_TOP_XPU3_RPU_ACR0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_XPU3_RPU_ACR0_ADDR,m,v,HWIO_IPA_GSI_TOP_XPU3_RPU_ACR0_IN) +#define HWIO_IPA_GSI_TOP_XPU3_RPU_ACR0_SUVMID_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_XPU3_RPU_ACR0_SUVMID_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_GCR0_ADDR (IPA_GSI_TOP_XPU3_REG_BASE + 0x00000080) +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_GCR0_PHYS (IPA_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000080) +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_GCR0_OFFS (IPA_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000080) +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_GCR0_RMSK 0x3 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_GCR0_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_GCR0_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_QAD0_GCR0_ADDR, HWIO_IPA_GSI_TOP_XPU3_QAD0_GCR0_RMSK) +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_GCR0_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_QAD0_GCR0_ADDR, m) +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_GCR0_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_XPU3_QAD0_GCR0_ADDR,v) +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_GCR0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_XPU3_QAD0_GCR0_ADDR,m,v,HWIO_IPA_GSI_TOP_XPU3_QAD0_GCR0_IN) +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_GCR0_QAD0LOG_MODE_DIS_BMSK 0x2 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_GCR0_QAD0LOG_MODE_DIS_SHFT 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_GCR0_QAD0DEN_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_GCR0_QAD0DEN_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_CR0_ADDR (IPA_GSI_TOP_XPU3_REG_BASE + 0x00000090) +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_CR0_PHYS (IPA_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000090) +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_CR0_OFFS (IPA_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000090) +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_CR0_RMSK 0x10f +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_CR0_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_CR0_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_QAD0_CR0_ADDR, HWIO_IPA_GSI_TOP_XPU3_QAD0_CR0_RMSK) +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_CR0_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_QAD0_CR0_ADDR, m) +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_CR0_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_XPU3_QAD0_CR0_ADDR,v) +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_CR0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_XPU3_QAD0_CR0_ADDR,m,v,HWIO_IPA_GSI_TOP_XPU3_QAD0_CR0_IN) +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_CR0_DYNAMIC_CLK_EN_BMSK 0x100 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_CR0_DYNAMIC_CLK_EN_SHFT 0x8 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_CR0_CLEIE_BMSK 0x8 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_CR0_CLEIE_SHFT 0x3 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_CR0_CFGEIE_BMSK 0x4 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_CR0_CFGEIE_SHFT 0x2 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_CR0_CLERE_BMSK 0x2 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_CR0_CLERE_SHFT 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_CR0_CFGERE_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_CR0_CFGERE_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_GCR0_ADDR (IPA_GSI_TOP_XPU3_REG_BASE + 0x00000100) +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_GCR0_PHYS (IPA_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000100) +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_GCR0_OFFS (IPA_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000100) +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_GCR0_RMSK 0x3 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_GCR0_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_GCR0_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_QAD1_GCR0_ADDR, HWIO_IPA_GSI_TOP_XPU3_QAD1_GCR0_RMSK) +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_GCR0_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_QAD1_GCR0_ADDR, m) +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_GCR0_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_XPU3_QAD1_GCR0_ADDR,v) +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_GCR0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_XPU3_QAD1_GCR0_ADDR,m,v,HWIO_IPA_GSI_TOP_XPU3_QAD1_GCR0_IN) +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_GCR0_QAD1LOG_MODE_DIS_BMSK 0x2 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_GCR0_QAD1LOG_MODE_DIS_SHFT 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_GCR0_QAD1DEN_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_GCR0_QAD1DEN_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_CR0_ADDR (IPA_GSI_TOP_XPU3_REG_BASE + 0x00000110) +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_CR0_PHYS (IPA_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000110) +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_CR0_OFFS (IPA_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000110) +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_CR0_RMSK 0x10f +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_CR0_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_CR0_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_QAD1_CR0_ADDR, HWIO_IPA_GSI_TOP_XPU3_QAD1_CR0_RMSK) +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_CR0_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_QAD1_CR0_ADDR, m) +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_CR0_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_XPU3_QAD1_CR0_ADDR,v) +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_CR0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_XPU3_QAD1_CR0_ADDR,m,v,HWIO_IPA_GSI_TOP_XPU3_QAD1_CR0_IN) +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_CR0_DYNAMIC_CLK_EN_BMSK 0x100 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_CR0_DYNAMIC_CLK_EN_SHFT 0x8 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_CR0_CLEIE_BMSK 0x8 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_CR0_CLEIE_SHFT 0x3 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_CR0_CFGEIE_BMSK 0x4 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_CR0_CFGEIE_SHFT 0x2 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_CR0_CLERE_BMSK 0x2 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_CR0_CLERE_SHFT 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_CR0_CFGERE_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_CR0_CFGERE_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_XPU3_IDR3_ADDR (IPA_GSI_TOP_XPU3_REG_BASE + 0x000003ec) +#define HWIO_IPA_GSI_TOP_XPU3_IDR3_PHYS (IPA_GSI_TOP_XPU3_REG_BASE_PHYS + 0x000003ec) +#define HWIO_IPA_GSI_TOP_XPU3_IDR3_OFFS (IPA_GSI_TOP_XPU3_REG_BASE_OFFS + 0x000003ec) +#define HWIO_IPA_GSI_TOP_XPU3_IDR3_RMSK 0x3ff +#define HWIO_IPA_GSI_TOP_XPU3_IDR3_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_IDR3_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_IDR3_ADDR, HWIO_IPA_GSI_TOP_XPU3_IDR3_RMSK) +#define HWIO_IPA_GSI_TOP_XPU3_IDR3_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_IDR3_ADDR, m) +#define HWIO_IPA_GSI_TOP_XPU3_IDR3_PT_BMSK 0x200 +#define HWIO_IPA_GSI_TOP_XPU3_IDR3_PT_SHFT 0x9 +#define HWIO_IPA_GSI_TOP_XPU3_IDR3_MV_BMSK 0x100 +#define HWIO_IPA_GSI_TOP_XPU3_IDR3_MV_SHFT 0x8 +#define HWIO_IPA_GSI_TOP_XPU3_IDR3_NVMID_BMSK 0xff +#define HWIO_IPA_GSI_TOP_XPU3_IDR3_NVMID_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_XPU3_IDR2_ADDR (IPA_GSI_TOP_XPU3_REG_BASE + 0x000003f0) +#define HWIO_IPA_GSI_TOP_XPU3_IDR2_PHYS (IPA_GSI_TOP_XPU3_REG_BASE_PHYS + 0x000003f0) +#define HWIO_IPA_GSI_TOP_XPU3_IDR2_OFFS (IPA_GSI_TOP_XPU3_REG_BASE_OFFS + 0x000003f0) +#define HWIO_IPA_GSI_TOP_XPU3_IDR2_RMSK 0xffffff0f +#define HWIO_IPA_GSI_TOP_XPU3_IDR2_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_IDR2_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_IDR2_ADDR, HWIO_IPA_GSI_TOP_XPU3_IDR2_RMSK) +#define HWIO_IPA_GSI_TOP_XPU3_IDR2_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_IDR2_ADDR, m) +#define HWIO_IPA_GSI_TOP_XPU3_IDR2_NONSEC_EN_BMSK 0xff000000 +#define HWIO_IPA_GSI_TOP_XPU3_IDR2_NONSEC_EN_SHFT 0x18 +#define HWIO_IPA_GSI_TOP_XPU3_IDR2_SEC_EN_BMSK 0xff0000 +#define HWIO_IPA_GSI_TOP_XPU3_IDR2_SEC_EN_SHFT 0x10 +#define HWIO_IPA_GSI_TOP_XPU3_IDR2_VMIDACR_EN_BMSK 0xff00 +#define HWIO_IPA_GSI_TOP_XPU3_IDR2_VMIDACR_EN_SHFT 0x8 +#define HWIO_IPA_GSI_TOP_XPU3_IDR2_NUM_QAD_BMSK 0xf +#define HWIO_IPA_GSI_TOP_XPU3_IDR2_NUM_QAD_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_XPU3_IDR1_ADDR (IPA_GSI_TOP_XPU3_REG_BASE + 0x000003f4) +#define HWIO_IPA_GSI_TOP_XPU3_IDR1_PHYS (IPA_GSI_TOP_XPU3_REG_BASE_PHYS + 0x000003f4) +#define HWIO_IPA_GSI_TOP_XPU3_IDR1_OFFS (IPA_GSI_TOP_XPU3_REG_BASE_OFFS + 0x000003f4) +#define HWIO_IPA_GSI_TOP_XPU3_IDR1_RMSK 0x3f3f0000 +#define HWIO_IPA_GSI_TOP_XPU3_IDR1_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_IDR1_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_IDR1_ADDR, HWIO_IPA_GSI_TOP_XPU3_IDR1_RMSK) +#define HWIO_IPA_GSI_TOP_XPU3_IDR1_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_IDR1_ADDR, m) +#define HWIO_IPA_GSI_TOP_XPU3_IDR1_CLIENT_ADDR_WIDTH_BMSK 0x3f000000 +#define HWIO_IPA_GSI_TOP_XPU3_IDR1_CLIENT_ADDR_WIDTH_SHFT 0x18 +#define HWIO_IPA_GSI_TOP_XPU3_IDR1_CONFIG_ADDR_WIDTH_BMSK 0x3f0000 +#define HWIO_IPA_GSI_TOP_XPU3_IDR1_CONFIG_ADDR_WIDTH_SHFT 0x10 + +#define HWIO_IPA_GSI_TOP_XPU3_IDR0_ADDR (IPA_GSI_TOP_XPU3_REG_BASE + 0x000003f8) +#define HWIO_IPA_GSI_TOP_XPU3_IDR0_PHYS (IPA_GSI_TOP_XPU3_REG_BASE_PHYS + 0x000003f8) +#define HWIO_IPA_GSI_TOP_XPU3_IDR0_OFFS (IPA_GSI_TOP_XPU3_REG_BASE_OFFS + 0x000003f8) +#define HWIO_IPA_GSI_TOP_XPU3_IDR0_RMSK 0x3ff0023 +#define HWIO_IPA_GSI_TOP_XPU3_IDR0_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_IDR0_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_IDR0_ADDR, HWIO_IPA_GSI_TOP_XPU3_IDR0_RMSK) +#define HWIO_IPA_GSI_TOP_XPU3_IDR0_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_IDR0_ADDR, m) +#define HWIO_IPA_GSI_TOP_XPU3_IDR0_NRG_BMSK 0x3ff0000 +#define HWIO_IPA_GSI_TOP_XPU3_IDR0_NRG_SHFT 0x10 +#define HWIO_IPA_GSI_TOP_XPU3_IDR0_CLIENTREQ_HALT_ACK_HW_EN_BMSK 0x20 +#define HWIO_IPA_GSI_TOP_XPU3_IDR0_CLIENTREQ_HALT_ACK_HW_EN_SHFT 0x5 +#define HWIO_IPA_GSI_TOP_XPU3_IDR0_XPUTYPE_BMSK 0x3 +#define HWIO_IPA_GSI_TOP_XPU3_IDR0_XPUTYPE_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_XPU3_REV_ADDR (IPA_GSI_TOP_XPU3_REG_BASE + 0x000003fc) +#define HWIO_IPA_GSI_TOP_XPU3_REV_PHYS (IPA_GSI_TOP_XPU3_REG_BASE_PHYS + 0x000003fc) +#define HWIO_IPA_GSI_TOP_XPU3_REV_OFFS (IPA_GSI_TOP_XPU3_REG_BASE_OFFS + 0x000003fc) +#define HWIO_IPA_GSI_TOP_XPU3_REV_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_XPU3_REV_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_REV_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_REV_ADDR, HWIO_IPA_GSI_TOP_XPU3_REV_RMSK) +#define HWIO_IPA_GSI_TOP_XPU3_REV_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_REV_ADDR, m) +#define HWIO_IPA_GSI_TOP_XPU3_REV_MAJOR_BMSK 0xf0000000 +#define HWIO_IPA_GSI_TOP_XPU3_REV_MAJOR_SHFT 0x1c +#define HWIO_IPA_GSI_TOP_XPU3_REV_MINOR_BMSK 0xfff0000 +#define HWIO_IPA_GSI_TOP_XPU3_REV_MINOR_SHFT 0x10 +#define HWIO_IPA_GSI_TOP_XPU3_REV_STEP_BMSK 0xffff +#define HWIO_IPA_GSI_TOP_XPU3_REV_STEP_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_XPU3_LOG_MODE_DIS_ADDR (IPA_GSI_TOP_XPU3_REG_BASE + 0x00000400) +#define HWIO_IPA_GSI_TOP_XPU3_LOG_MODE_DIS_PHYS (IPA_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000400) +#define HWIO_IPA_GSI_TOP_XPU3_LOG_MODE_DIS_OFFS (IPA_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000400) +#define HWIO_IPA_GSI_TOP_XPU3_LOG_MODE_DIS_RMSK 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_LOG_MODE_DIS_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_XPU3_LOG_MODE_DIS_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_LOG_MODE_DIS_ADDR, HWIO_IPA_GSI_TOP_XPU3_LOG_MODE_DIS_RMSK) +#define HWIO_IPA_GSI_TOP_XPU3_LOG_MODE_DIS_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_LOG_MODE_DIS_ADDR, m) +#define HWIO_IPA_GSI_TOP_XPU3_LOG_MODE_DIS_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_XPU3_LOG_MODE_DIS_ADDR,v) +#define HWIO_IPA_GSI_TOP_XPU3_LOG_MODE_DIS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_XPU3_LOG_MODE_DIS_ADDR,m,v,HWIO_IPA_GSI_TOP_XPU3_LOG_MODE_DIS_IN) +#define HWIO_IPA_GSI_TOP_XPU3_LOG_MODE_DIS_LOG_MODE_DIS_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_LOG_MODE_DIS_LOG_MODE_DIS_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_XPU3_RGN_FREESTATUSr_ADDR(r) (IPA_GSI_TOP_XPU3_REG_BASE + 0x00000500 + 0x4 * (r)) +#define HWIO_IPA_GSI_TOP_XPU3_RGN_FREESTATUSr_PHYS(r) (IPA_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000500 + 0x4 * (r)) +#define HWIO_IPA_GSI_TOP_XPU3_RGN_FREESTATUSr_OFFS(r) (IPA_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000500 + 0x4 * (r)) +#define HWIO_IPA_GSI_TOP_XPU3_RGN_FREESTATUSr_RMSK 0x1fffff +#define HWIO_IPA_GSI_TOP_XPU3_RGN_FREESTATUSr_MAXr 0 +#define HWIO_IPA_GSI_TOP_XPU3_RGN_FREESTATUSr_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_RGN_FREESTATUSr_INI(r) \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_RGN_FREESTATUSr_ADDR(r), HWIO_IPA_GSI_TOP_XPU3_RGN_FREESTATUSr_RMSK) +#define HWIO_IPA_GSI_TOP_XPU3_RGN_FREESTATUSr_INMI(r,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_RGN_FREESTATUSr_ADDR(r), mask) +#define HWIO_IPA_GSI_TOP_XPU3_RGN_FREESTATUSr_RGFREESTATUS_BMSK 0x1fffff +#define HWIO_IPA_GSI_TOP_XPU3_RGN_FREESTATUSr_RGFREESTATUS_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_XPU3_SEAR0_ADDR (IPA_GSI_TOP_XPU3_REG_BASE + 0x00000800) +#define HWIO_IPA_GSI_TOP_XPU3_SEAR0_PHYS (IPA_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000800) +#define HWIO_IPA_GSI_TOP_XPU3_SEAR0_OFFS (IPA_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000800) +#define HWIO_IPA_GSI_TOP_XPU3_SEAR0_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_XPU3_SEAR0_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_SEAR0_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_SEAR0_ADDR, HWIO_IPA_GSI_TOP_XPU3_SEAR0_RMSK) +#define HWIO_IPA_GSI_TOP_XPU3_SEAR0_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_SEAR0_ADDR, m) +#define HWIO_IPA_GSI_TOP_XPU3_SEAR0_ADDR_31_0_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_XPU3_SEAR0_ADDR_31_0_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_XPU3_SESR_ADDR (IPA_GSI_TOP_XPU3_REG_BASE + 0x00000808) +#define HWIO_IPA_GSI_TOP_XPU3_SESR_PHYS (IPA_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000808) +#define HWIO_IPA_GSI_TOP_XPU3_SESR_OFFS (IPA_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000808) +#define HWIO_IPA_GSI_TOP_XPU3_SESR_RMSK 0xf +#define HWIO_IPA_GSI_TOP_XPU3_SESR_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_XPU3_SESR_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_SESR_ADDR, HWIO_IPA_GSI_TOP_XPU3_SESR_RMSK) +#define HWIO_IPA_GSI_TOP_XPU3_SESR_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_SESR_ADDR, m) +#define HWIO_IPA_GSI_TOP_XPU3_SESR_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_XPU3_SESR_ADDR,v) +#define HWIO_IPA_GSI_TOP_XPU3_SESR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_XPU3_SESR_ADDR,m,v,HWIO_IPA_GSI_TOP_XPU3_SESR_IN) +#define HWIO_IPA_GSI_TOP_XPU3_SESR_CLMULTI_BMSK 0x8 +#define HWIO_IPA_GSI_TOP_XPU3_SESR_CLMULTI_SHFT 0x3 +#define HWIO_IPA_GSI_TOP_XPU3_SESR_CFGMULTI_BMSK 0x4 +#define HWIO_IPA_GSI_TOP_XPU3_SESR_CFGMULTI_SHFT 0x2 +#define HWIO_IPA_GSI_TOP_XPU3_SESR_CLIENT_BMSK 0x2 +#define HWIO_IPA_GSI_TOP_XPU3_SESR_CLIENT_SHFT 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_SESR_CFG_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_SESR_CFG_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_XPU3_SESRRESTORE_ADDR (IPA_GSI_TOP_XPU3_REG_BASE + 0x0000080c) +#define HWIO_IPA_GSI_TOP_XPU3_SESRRESTORE_PHYS (IPA_GSI_TOP_XPU3_REG_BASE_PHYS + 0x0000080c) +#define HWIO_IPA_GSI_TOP_XPU3_SESRRESTORE_OFFS (IPA_GSI_TOP_XPU3_REG_BASE_OFFS + 0x0000080c) +#define HWIO_IPA_GSI_TOP_XPU3_SESRRESTORE_RMSK 0xf +#define HWIO_IPA_GSI_TOP_XPU3_SESRRESTORE_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_XPU3_SESRRESTORE_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_SESRRESTORE_ADDR, HWIO_IPA_GSI_TOP_XPU3_SESRRESTORE_RMSK) +#define HWIO_IPA_GSI_TOP_XPU3_SESRRESTORE_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_SESRRESTORE_ADDR, m) +#define HWIO_IPA_GSI_TOP_XPU3_SESRRESTORE_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_XPU3_SESRRESTORE_ADDR,v) +#define HWIO_IPA_GSI_TOP_XPU3_SESRRESTORE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_XPU3_SESRRESTORE_ADDR,m,v,HWIO_IPA_GSI_TOP_XPU3_SESRRESTORE_IN) +#define HWIO_IPA_GSI_TOP_XPU3_SESRRESTORE_CLMULTI_BMSK 0x8 +#define HWIO_IPA_GSI_TOP_XPU3_SESRRESTORE_CLMULTI_SHFT 0x3 +#define HWIO_IPA_GSI_TOP_XPU3_SESRRESTORE_CFGMULTI_BMSK 0x4 +#define HWIO_IPA_GSI_TOP_XPU3_SESRRESTORE_CFGMULTI_SHFT 0x2 +#define HWIO_IPA_GSI_TOP_XPU3_SESRRESTORE_CLIENT_BMSK 0x2 +#define HWIO_IPA_GSI_TOP_XPU3_SESRRESTORE_CLIENT_SHFT 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_SESRRESTORE_CFG_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_SESRRESTORE_CFG_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR0_ADDR (IPA_GSI_TOP_XPU3_REG_BASE + 0x00000810) +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR0_PHYS (IPA_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000810) +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR0_OFFS (IPA_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000810) +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR0_RMSK 0x67ffff0f +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR0_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR0_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_SESYNR0_ADDR, HWIO_IPA_GSI_TOP_XPU3_SESYNR0_RMSK) +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR0_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_SESYNR0_ADDR, m) +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR0_AC_BMSK 0x40000000 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR0_AC_SHFT 0x1e +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR0_BURSTLEN_BMSK 0x20000000 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR0_BURSTLEN_SHFT 0x1d +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR0_ASIZE_BMSK 0x7000000 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR0_ASIZE_SHFT 0x18 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR0_ALEN_BMSK 0xff0000 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR0_ALEN_SHFT 0x10 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR0_QAD_BMSK 0xff00 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR0_QAD_SHFT 0x8 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR0_XPRIV_BMSK 0x8 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR0_XPRIV_SHFT 0x3 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR0_XINST_BMSK 0x4 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR0_XINST_SHFT 0x2 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR0_AWRITE_BMSK 0x2 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR0_AWRITE_SHFT 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR0_XPROTNS_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR0_XPROTNS_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR1_ADDR (IPA_GSI_TOP_XPU3_REG_BASE + 0x00000814) +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR1_PHYS (IPA_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000814) +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR1_OFFS (IPA_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000814) +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR1_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR1_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR1_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_SESYNR1_ADDR, HWIO_IPA_GSI_TOP_XPU3_SESYNR1_RMSK) +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR1_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_SESYNR1_ADDR, m) +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR1_TID_BMSK 0xff000000 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR1_TID_SHFT 0x18 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR1_VMID_BMSK 0xff0000 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR1_VMID_SHFT 0x10 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR1_BID_BMSK 0xe000 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR1_BID_SHFT 0xd +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR1_PID_BMSK 0x1f00 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR1_PID_SHFT 0x8 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR1_MID_BMSK 0xff +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR1_MID_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR2_ADDR (IPA_GSI_TOP_XPU3_REG_BASE + 0x00000818) +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR2_PHYS (IPA_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000818) +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR2_OFFS (IPA_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000818) +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR2_RMSK 0xffffff87 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR2_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR2_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_SESYNR2_ADDR, HWIO_IPA_GSI_TOP_XPU3_SESYNR2_RMSK) +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR2_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_SESYNR2_ADDR, m) +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR2_BAR_BMSK 0xc0000000 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR2_BAR_SHFT 0x1e +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR2_BURST_BMSK 0x20000000 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR2_BURST_SHFT 0x1d +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR2_CACHEABLE_BMSK 0x10000000 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR2_CACHEABLE_SHFT 0x1c +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR2_DEVICE_BMSK 0x8000000 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR2_DEVICE_SHFT 0x1b +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR2_DEVICE_TYPE_BMSK 0x6000000 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR2_DEVICE_TYPE_SHFT 0x19 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR2_EARLYWRRESP_BMSK 0x1000000 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR2_EARLYWRRESP_SHFT 0x18 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR2_ERROR_BMSK 0x800000 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR2_ERROR_SHFT 0x17 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR2_EXCLUSIVE_BMSK 0x400000 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR2_EXCLUSIVE_SHFT 0x16 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR2_FULL_BMSK 0x200000 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR2_FULL_SHFT 0x15 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR2_SHARED_BMSK 0x100000 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR2_SHARED_SHFT 0x14 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR2_WRITETHROUGH_BMSK 0x80000 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR2_WRITETHROUGH_SHFT 0x13 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR2_INNERNOALLOCATE_BMSK 0x40000 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR2_INNERNOALLOCATE_SHFT 0x12 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR2_INNERCACHEABLE_BMSK 0x20000 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR2_INNERCACHEABLE_SHFT 0x11 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR2_INNERSHARED_BMSK 0x10000 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR2_INNERSHARED_SHFT 0x10 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR2_INNERTRANSIENT_BMSK 0x8000 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR2_INNERTRANSIENT_SHFT 0xf +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR2_INNERWRITETHROUGH_BMSK 0x4000 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR2_INNERWRITETHROUGH_SHFT 0xe +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR2_PORTMREL_BMSK 0x2000 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR2_PORTMREL_SHFT 0xd +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR2_ORDEREDRD_BMSK 0x1000 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR2_ORDEREDRD_SHFT 0xc +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR2_ORDEREDWR_BMSK 0x800 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR2_ORDEREDWR_SHFT 0xb +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR2_OOORD_BMSK 0x400 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR2_OOORD_SHFT 0xa +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR2_OOOWR_BMSK 0x200 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR2_OOOWR_SHFT 0x9 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR2_NOALLOCATE_BMSK 0x100 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR2_NOALLOCATE_SHFT 0x8 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR2_TRANSIENT_BMSK 0x80 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR2_TRANSIENT_SHFT 0x7 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR2_MEMTYPE_BMSK 0x7 +#define HWIO_IPA_GSI_TOP_XPU3_SESYNR2_MEMTYPE_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_XPU3_SEAR1_ADDR (IPA_GSI_TOP_XPU3_REG_BASE + 0x00000804) +#define HWIO_IPA_GSI_TOP_XPU3_SEAR1_PHYS (IPA_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000804) +#define HWIO_IPA_GSI_TOP_XPU3_SEAR1_OFFS (IPA_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000804) +#define HWIO_IPA_GSI_TOP_XPU3_SEAR1_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_XPU3_SEAR1_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_SEAR1_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_SEAR1_ADDR, HWIO_IPA_GSI_TOP_XPU3_SEAR1_RMSK) +#define HWIO_IPA_GSI_TOP_XPU3_SEAR1_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_SEAR1_ADDR, m) +#define HWIO_IPA_GSI_TOP_XPU3_SEAR1_ADDR_63_32_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_XPU3_SEAR1_ADDR_63_32_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_XPU3_EAR0_ADDR (IPA_GSI_TOP_XPU3_REG_BASE + 0x00000880) +#define HWIO_IPA_GSI_TOP_XPU3_EAR0_PHYS (IPA_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000880) +#define HWIO_IPA_GSI_TOP_XPU3_EAR0_OFFS (IPA_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000880) +#define HWIO_IPA_GSI_TOP_XPU3_EAR0_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_XPU3_EAR0_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_EAR0_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_EAR0_ADDR, HWIO_IPA_GSI_TOP_XPU3_EAR0_RMSK) +#define HWIO_IPA_GSI_TOP_XPU3_EAR0_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_EAR0_ADDR, m) +#define HWIO_IPA_GSI_TOP_XPU3_EAR0_ADDR_31_0_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_XPU3_EAR0_ADDR_31_0_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_XPU3_ESR_ADDR (IPA_GSI_TOP_XPU3_REG_BASE + 0x00000888) +#define HWIO_IPA_GSI_TOP_XPU3_ESR_PHYS (IPA_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000888) +#define HWIO_IPA_GSI_TOP_XPU3_ESR_OFFS (IPA_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000888) +#define HWIO_IPA_GSI_TOP_XPU3_ESR_RMSK 0xf +#define HWIO_IPA_GSI_TOP_XPU3_ESR_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_XPU3_ESR_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_ESR_ADDR, HWIO_IPA_GSI_TOP_XPU3_ESR_RMSK) +#define HWIO_IPA_GSI_TOP_XPU3_ESR_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_ESR_ADDR, m) +#define HWIO_IPA_GSI_TOP_XPU3_ESR_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_XPU3_ESR_ADDR,v) +#define HWIO_IPA_GSI_TOP_XPU3_ESR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_XPU3_ESR_ADDR,m,v,HWIO_IPA_GSI_TOP_XPU3_ESR_IN) +#define HWIO_IPA_GSI_TOP_XPU3_ESR_CLMULTI_BMSK 0x8 +#define HWIO_IPA_GSI_TOP_XPU3_ESR_CLMULTI_SHFT 0x3 +#define HWIO_IPA_GSI_TOP_XPU3_ESR_CFGMULTI_BMSK 0x4 +#define HWIO_IPA_GSI_TOP_XPU3_ESR_CFGMULTI_SHFT 0x2 +#define HWIO_IPA_GSI_TOP_XPU3_ESR_CLIENT_BMSK 0x2 +#define HWIO_IPA_GSI_TOP_XPU3_ESR_CLIENT_SHFT 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_ESR_CFG_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_ESR_CFG_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_XPU3_ESRRESTORE_ADDR (IPA_GSI_TOP_XPU3_REG_BASE + 0x0000088c) +#define HWIO_IPA_GSI_TOP_XPU3_ESRRESTORE_PHYS (IPA_GSI_TOP_XPU3_REG_BASE_PHYS + 0x0000088c) +#define HWIO_IPA_GSI_TOP_XPU3_ESRRESTORE_OFFS (IPA_GSI_TOP_XPU3_REG_BASE_OFFS + 0x0000088c) +#define HWIO_IPA_GSI_TOP_XPU3_ESRRESTORE_RMSK 0xf +#define HWIO_IPA_GSI_TOP_XPU3_ESRRESTORE_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_XPU3_ESRRESTORE_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_ESRRESTORE_ADDR, HWIO_IPA_GSI_TOP_XPU3_ESRRESTORE_RMSK) +#define HWIO_IPA_GSI_TOP_XPU3_ESRRESTORE_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_ESRRESTORE_ADDR, m) +#define HWIO_IPA_GSI_TOP_XPU3_ESRRESTORE_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_XPU3_ESRRESTORE_ADDR,v) +#define HWIO_IPA_GSI_TOP_XPU3_ESRRESTORE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_XPU3_ESRRESTORE_ADDR,m,v,HWIO_IPA_GSI_TOP_XPU3_ESRRESTORE_IN) +#define HWIO_IPA_GSI_TOP_XPU3_ESRRESTORE_CLMULTI_BMSK 0x8 +#define HWIO_IPA_GSI_TOP_XPU3_ESRRESTORE_CLMULTI_SHFT 0x3 +#define HWIO_IPA_GSI_TOP_XPU3_ESRRESTORE_CFGMULTI_BMSK 0x4 +#define HWIO_IPA_GSI_TOP_XPU3_ESRRESTORE_CFGMULTI_SHFT 0x2 +#define HWIO_IPA_GSI_TOP_XPU3_ESRRESTORE_CLIENT_BMSK 0x2 +#define HWIO_IPA_GSI_TOP_XPU3_ESRRESTORE_CLIENT_SHFT 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_ESRRESTORE_CFG_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_ESRRESTORE_CFG_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR0_ADDR (IPA_GSI_TOP_XPU3_REG_BASE + 0x00000890) +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR0_PHYS (IPA_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000890) +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR0_OFFS (IPA_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000890) +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR0_RMSK 0x67ffff0f +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR0_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR0_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_ESYNR0_ADDR, HWIO_IPA_GSI_TOP_XPU3_ESYNR0_RMSK) +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR0_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_ESYNR0_ADDR, m) +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR0_AC_BMSK 0x40000000 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR0_AC_SHFT 0x1e +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR0_BURSTLEN_BMSK 0x20000000 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR0_BURSTLEN_SHFT 0x1d +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR0_ASIZE_BMSK 0x7000000 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR0_ASIZE_SHFT 0x18 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR0_ALEN_BMSK 0xff0000 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR0_ALEN_SHFT 0x10 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR0_QAD_BMSK 0xff00 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR0_QAD_SHFT 0x8 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR0_XPRIV_BMSK 0x8 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR0_XPRIV_SHFT 0x3 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR0_XINST_BMSK 0x4 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR0_XINST_SHFT 0x2 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR0_AWRITE_BMSK 0x2 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR0_AWRITE_SHFT 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR0_XPROTNS_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR0_XPROTNS_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR1_ADDR (IPA_GSI_TOP_XPU3_REG_BASE + 0x00000894) +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR1_PHYS (IPA_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000894) +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR1_OFFS (IPA_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000894) +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR1_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR1_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR1_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_ESYNR1_ADDR, HWIO_IPA_GSI_TOP_XPU3_ESYNR1_RMSK) +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR1_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_ESYNR1_ADDR, m) +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR1_TID_BMSK 0xff000000 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR1_TID_SHFT 0x18 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR1_VMID_BMSK 0xff0000 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR1_VMID_SHFT 0x10 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR1_BID_BMSK 0xe000 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR1_BID_SHFT 0xd +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR1_PID_BMSK 0x1f00 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR1_PID_SHFT 0x8 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR1_MID_BMSK 0xff +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR1_MID_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR2_ADDR (IPA_GSI_TOP_XPU3_REG_BASE + 0x00000898) +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR2_PHYS (IPA_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000898) +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR2_OFFS (IPA_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000898) +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR2_RMSK 0xffffff87 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR2_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR2_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_ESYNR2_ADDR, HWIO_IPA_GSI_TOP_XPU3_ESYNR2_RMSK) +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR2_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_ESYNR2_ADDR, m) +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR2_BAR_BMSK 0xc0000000 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR2_BAR_SHFT 0x1e +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR2_BURST_BMSK 0x20000000 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR2_BURST_SHFT 0x1d +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR2_CACHEABLE_BMSK 0x10000000 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR2_CACHEABLE_SHFT 0x1c +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR2_DEVICE_BMSK 0x8000000 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR2_DEVICE_SHFT 0x1b +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR2_DEVICE_TYPE_BMSK 0x6000000 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR2_DEVICE_TYPE_SHFT 0x19 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR2_EARLYWRRESP_BMSK 0x1000000 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR2_EARLYWRRESP_SHFT 0x18 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR2_ERROR_BMSK 0x800000 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR2_ERROR_SHFT 0x17 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR2_EXCLUSIVE_BMSK 0x400000 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR2_EXCLUSIVE_SHFT 0x16 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR2_FULL_BMSK 0x200000 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR2_FULL_SHFT 0x15 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR2_SHARED_BMSK 0x100000 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR2_SHARED_SHFT 0x14 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR2_WRITETHROUGH_BMSK 0x80000 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR2_WRITETHROUGH_SHFT 0x13 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR2_INNERNOALLOCATE_BMSK 0x40000 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR2_INNERNOALLOCATE_SHFT 0x12 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR2_INNERCACHEABLE_BMSK 0x20000 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR2_INNERCACHEABLE_SHFT 0x11 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR2_INNERSHARED_BMSK 0x10000 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR2_INNERSHARED_SHFT 0x10 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR2_INNERTRANSIENT_BMSK 0x8000 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR2_INNERTRANSIENT_SHFT 0xf +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR2_INNERWRITETHROUGH_BMSK 0x4000 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR2_INNERWRITETHROUGH_SHFT 0xe +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR2_PORTMREL_BMSK 0x2000 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR2_PORTMREL_SHFT 0xd +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR2_ORDEREDRD_BMSK 0x1000 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR2_ORDEREDRD_SHFT 0xc +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR2_ORDEREDWR_BMSK 0x800 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR2_ORDEREDWR_SHFT 0xb +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR2_OOORD_BMSK 0x400 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR2_OOORD_SHFT 0xa +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR2_OOOWR_BMSK 0x200 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR2_OOOWR_SHFT 0x9 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR2_NOALLOCATE_BMSK 0x100 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR2_NOALLOCATE_SHFT 0x8 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR2_TRANSIENT_BMSK 0x80 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR2_TRANSIENT_SHFT 0x7 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR2_MEMTYPE_BMSK 0x7 +#define HWIO_IPA_GSI_TOP_XPU3_ESYNR2_MEMTYPE_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_XPU3_EAR1_ADDR (IPA_GSI_TOP_XPU3_REG_BASE + 0x00000884) +#define HWIO_IPA_GSI_TOP_XPU3_EAR1_PHYS (IPA_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000884) +#define HWIO_IPA_GSI_TOP_XPU3_EAR1_OFFS (IPA_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000884) +#define HWIO_IPA_GSI_TOP_XPU3_EAR1_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_XPU3_EAR1_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_EAR1_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_EAR1_ADDR, HWIO_IPA_GSI_TOP_XPU3_EAR1_RMSK) +#define HWIO_IPA_GSI_TOP_XPU3_EAR1_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_EAR1_ADDR, m) +#define HWIO_IPA_GSI_TOP_XPU3_EAR1_ADDR_63_32_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_XPU3_EAR1_ADDR_63_32_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_EAR0_ADDR (IPA_GSI_TOP_XPU3_REG_BASE + 0x00000880) +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_EAR0_PHYS (IPA_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000880) +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_EAR0_OFFS (IPA_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000880) +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_EAR0_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_EAR0_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_EAR0_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_QAD0_EAR0_ADDR, HWIO_IPA_GSI_TOP_XPU3_QAD0_EAR0_RMSK) +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_EAR0_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_QAD0_EAR0_ADDR, m) +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_EAR0_ADDR_31_0_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_EAR0_ADDR_31_0_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESR_ADDR (IPA_GSI_TOP_XPU3_REG_BASE + 0x00000888) +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESR_PHYS (IPA_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000888) +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESR_OFFS (IPA_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000888) +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESR_RMSK 0xf +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESR_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESR_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_QAD0_ESR_ADDR, HWIO_IPA_GSI_TOP_XPU3_QAD0_ESR_RMSK) +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESR_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_QAD0_ESR_ADDR, m) +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESR_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_XPU3_QAD0_ESR_ADDR,v) +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_XPU3_QAD0_ESR_ADDR,m,v,HWIO_IPA_GSI_TOP_XPU3_QAD0_ESR_IN) +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESR_CLMULTI_BMSK 0x8 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESR_CLMULTI_SHFT 0x3 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESR_CFGMULTI_BMSK 0x4 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESR_CFGMULTI_SHFT 0x2 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESR_CLIENT_BMSK 0x2 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESR_CLIENT_SHFT 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESR_CFG_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESR_CFG_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESRRESTORE_ADDR (IPA_GSI_TOP_XPU3_REG_BASE + 0x0000088c) +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESRRESTORE_PHYS (IPA_GSI_TOP_XPU3_REG_BASE_PHYS + 0x0000088c) +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESRRESTORE_OFFS (IPA_GSI_TOP_XPU3_REG_BASE_OFFS + 0x0000088c) +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESRRESTORE_RMSK 0xf +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESRRESTORE_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESRRESTORE_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_QAD0_ESRRESTORE_ADDR, HWIO_IPA_GSI_TOP_XPU3_QAD0_ESRRESTORE_RMSK) +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESRRESTORE_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_QAD0_ESRRESTORE_ADDR, m) +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESRRESTORE_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_XPU3_QAD0_ESRRESTORE_ADDR,v) +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESRRESTORE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_XPU3_QAD0_ESRRESTORE_ADDR,m,v,HWIO_IPA_GSI_TOP_XPU3_QAD0_ESRRESTORE_IN) +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESRRESTORE_CLMULTI_BMSK 0x8 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESRRESTORE_CLMULTI_SHFT 0x3 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESRRESTORE_CFGMULTI_BMSK 0x4 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESRRESTORE_CFGMULTI_SHFT 0x2 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESRRESTORE_CLIENT_BMSK 0x2 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESRRESTORE_CLIENT_SHFT 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESRRESTORE_CFG_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESRRESTORE_CFG_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR0_ADDR (IPA_GSI_TOP_XPU3_REG_BASE + 0x00000890) +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR0_PHYS (IPA_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000890) +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR0_OFFS (IPA_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000890) +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR0_RMSK 0x67ffff0f +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR0_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR0_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR0_ADDR, HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR0_RMSK) +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR0_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR0_ADDR, m) +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR0_AC_BMSK 0x40000000 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR0_AC_SHFT 0x1e +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR0_BURSTLEN_BMSK 0x20000000 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR0_BURSTLEN_SHFT 0x1d +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR0_ASIZE_BMSK 0x7000000 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR0_ASIZE_SHFT 0x18 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR0_ALEN_BMSK 0xff0000 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR0_ALEN_SHFT 0x10 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR0_QAD_BMSK 0xff00 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR0_QAD_SHFT 0x8 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR0_XPRIV_BMSK 0x8 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR0_XPRIV_SHFT 0x3 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR0_XINST_BMSK 0x4 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR0_XINST_SHFT 0x2 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR0_AWRITE_BMSK 0x2 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR0_AWRITE_SHFT 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR0_XPROTNS_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR0_XPROTNS_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR1_ADDR (IPA_GSI_TOP_XPU3_REG_BASE + 0x00000894) +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR1_PHYS (IPA_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000894) +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR1_OFFS (IPA_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000894) +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR1_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR1_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR1_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR1_ADDR, HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR1_RMSK) +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR1_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR1_ADDR, m) +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR1_TID_BMSK 0xff000000 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR1_TID_SHFT 0x18 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR1_VMID_BMSK 0xff0000 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR1_VMID_SHFT 0x10 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR1_BID_BMSK 0xe000 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR1_BID_SHFT 0xd +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR1_PID_BMSK 0x1f00 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR1_PID_SHFT 0x8 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR1_MID_BMSK 0xff +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR1_MID_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR2_ADDR (IPA_GSI_TOP_XPU3_REG_BASE + 0x00000898) +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR2_PHYS (IPA_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000898) +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR2_OFFS (IPA_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000898) +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR2_RMSK 0xffffff87 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR2_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR2_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR2_ADDR, HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR2_RMSK) +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR2_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR2_ADDR, m) +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR2_BAR_BMSK 0xc0000000 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR2_BAR_SHFT 0x1e +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR2_BURST_BMSK 0x20000000 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR2_BURST_SHFT 0x1d +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR2_CACHEABLE_BMSK 0x10000000 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR2_CACHEABLE_SHFT 0x1c +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR2_DEVICE_BMSK 0x8000000 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR2_DEVICE_SHFT 0x1b +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR2_DEVICE_TYPE_BMSK 0x6000000 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR2_DEVICE_TYPE_SHFT 0x19 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR2_EARLYWRRESP_BMSK 0x1000000 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR2_EARLYWRRESP_SHFT 0x18 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR2_ERROR_BMSK 0x800000 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR2_ERROR_SHFT 0x17 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR2_EXCLUSIVE_BMSK 0x400000 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR2_EXCLUSIVE_SHFT 0x16 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR2_FULL_BMSK 0x200000 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR2_FULL_SHFT 0x15 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR2_SHARED_BMSK 0x100000 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR2_SHARED_SHFT 0x14 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR2_WRITETHROUGH_BMSK 0x80000 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR2_WRITETHROUGH_SHFT 0x13 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR2_INNERNOALLOCATE_BMSK 0x40000 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR2_INNERNOALLOCATE_SHFT 0x12 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR2_INNERCACHEABLE_BMSK 0x20000 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR2_INNERCACHEABLE_SHFT 0x11 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR2_INNERSHARED_BMSK 0x10000 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR2_INNERSHARED_SHFT 0x10 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR2_INNERTRANSIENT_BMSK 0x8000 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR2_INNERTRANSIENT_SHFT 0xf +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR2_INNERWRITETHROUGH_BMSK 0x4000 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR2_INNERWRITETHROUGH_SHFT 0xe +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR2_PORTMREL_BMSK 0x2000 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR2_PORTMREL_SHFT 0xd +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR2_ORDEREDRD_BMSK 0x1000 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR2_ORDEREDRD_SHFT 0xc +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR2_ORDEREDWR_BMSK 0x800 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR2_ORDEREDWR_SHFT 0xb +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR2_OOORD_BMSK 0x400 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR2_OOORD_SHFT 0xa +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR2_OOOWR_BMSK 0x200 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR2_OOOWR_SHFT 0x9 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR2_NOALLOCATE_BMSK 0x100 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR2_NOALLOCATE_SHFT 0x8 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR2_TRANSIENT_BMSK 0x80 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR2_TRANSIENT_SHFT 0x7 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR2_MEMTYPE_BMSK 0x7 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_ESYNR2_MEMTYPE_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_EAR1_ADDR (IPA_GSI_TOP_XPU3_REG_BASE + 0x00000884) +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_EAR1_PHYS (IPA_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000884) +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_EAR1_OFFS (IPA_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000884) +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_EAR1_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_EAR1_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_EAR1_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_QAD0_EAR1_ADDR, HWIO_IPA_GSI_TOP_XPU3_QAD0_EAR1_RMSK) +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_EAR1_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_QAD0_EAR1_ADDR, m) +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_EAR1_ADDR_63_32_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_XPU3_QAD0_EAR1_ADDR_63_32_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_EAR0_ADDR (IPA_GSI_TOP_XPU3_REG_BASE + 0x00000880) +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_EAR0_PHYS (IPA_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000880) +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_EAR0_OFFS (IPA_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000880) +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_EAR0_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_EAR0_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_EAR0_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_QAD1_EAR0_ADDR, HWIO_IPA_GSI_TOP_XPU3_QAD1_EAR0_RMSK) +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_EAR0_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_QAD1_EAR0_ADDR, m) +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_EAR0_ADDR_31_0_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_EAR0_ADDR_31_0_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESR_ADDR (IPA_GSI_TOP_XPU3_REG_BASE + 0x00000888) +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESR_PHYS (IPA_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000888) +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESR_OFFS (IPA_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000888) +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESR_RMSK 0xf +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESR_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESR_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_QAD1_ESR_ADDR, HWIO_IPA_GSI_TOP_XPU3_QAD1_ESR_RMSK) +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESR_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_QAD1_ESR_ADDR, m) +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESR_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_XPU3_QAD1_ESR_ADDR,v) +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_XPU3_QAD1_ESR_ADDR,m,v,HWIO_IPA_GSI_TOP_XPU3_QAD1_ESR_IN) +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESR_CLMULTI_BMSK 0x8 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESR_CLMULTI_SHFT 0x3 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESR_CFGMULTI_BMSK 0x4 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESR_CFGMULTI_SHFT 0x2 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESR_CLIENT_BMSK 0x2 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESR_CLIENT_SHFT 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESR_CFG_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESR_CFG_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESRRESTORE_ADDR (IPA_GSI_TOP_XPU3_REG_BASE + 0x0000088c) +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESRRESTORE_PHYS (IPA_GSI_TOP_XPU3_REG_BASE_PHYS + 0x0000088c) +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESRRESTORE_OFFS (IPA_GSI_TOP_XPU3_REG_BASE_OFFS + 0x0000088c) +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESRRESTORE_RMSK 0xf +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESRRESTORE_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESRRESTORE_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_QAD1_ESRRESTORE_ADDR, HWIO_IPA_GSI_TOP_XPU3_QAD1_ESRRESTORE_RMSK) +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESRRESTORE_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_QAD1_ESRRESTORE_ADDR, m) +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESRRESTORE_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_XPU3_QAD1_ESRRESTORE_ADDR,v) +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESRRESTORE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_XPU3_QAD1_ESRRESTORE_ADDR,m,v,HWIO_IPA_GSI_TOP_XPU3_QAD1_ESRRESTORE_IN) +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESRRESTORE_CLMULTI_BMSK 0x8 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESRRESTORE_CLMULTI_SHFT 0x3 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESRRESTORE_CFGMULTI_BMSK 0x4 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESRRESTORE_CFGMULTI_SHFT 0x2 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESRRESTORE_CLIENT_BMSK 0x2 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESRRESTORE_CLIENT_SHFT 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESRRESTORE_CFG_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESRRESTORE_CFG_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR0_ADDR (IPA_GSI_TOP_XPU3_REG_BASE + 0x00000890) +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR0_PHYS (IPA_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000890) +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR0_OFFS (IPA_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000890) +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR0_RMSK 0x67ffff0f +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR0_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR0_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR0_ADDR, HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR0_RMSK) +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR0_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR0_ADDR, m) +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR0_AC_BMSK 0x40000000 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR0_AC_SHFT 0x1e +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR0_BURSTLEN_BMSK 0x20000000 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR0_BURSTLEN_SHFT 0x1d +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR0_ASIZE_BMSK 0x7000000 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR0_ASIZE_SHFT 0x18 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR0_ALEN_BMSK 0xff0000 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR0_ALEN_SHFT 0x10 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR0_QAD_BMSK 0xff00 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR0_QAD_SHFT 0x8 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR0_XPRIV_BMSK 0x8 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR0_XPRIV_SHFT 0x3 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR0_XINST_BMSK 0x4 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR0_XINST_SHFT 0x2 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR0_AWRITE_BMSK 0x2 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR0_AWRITE_SHFT 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR0_XPROTNS_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR0_XPROTNS_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR1_ADDR (IPA_GSI_TOP_XPU3_REG_BASE + 0x00000894) +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR1_PHYS (IPA_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000894) +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR1_OFFS (IPA_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000894) +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR1_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR1_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR1_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR1_ADDR, HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR1_RMSK) +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR1_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR1_ADDR, m) +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR1_TID_BMSK 0xff000000 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR1_TID_SHFT 0x18 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR1_VMID_BMSK 0xff0000 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR1_VMID_SHFT 0x10 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR1_BID_BMSK 0xe000 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR1_BID_SHFT 0xd +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR1_PID_BMSK 0x1f00 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR1_PID_SHFT 0x8 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR1_MID_BMSK 0xff +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR1_MID_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR2_ADDR (IPA_GSI_TOP_XPU3_REG_BASE + 0x00000898) +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR2_PHYS (IPA_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000898) +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR2_OFFS (IPA_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000898) +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR2_RMSK 0xffffff87 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR2_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR2_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR2_ADDR, HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR2_RMSK) +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR2_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR2_ADDR, m) +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR2_BAR_BMSK 0xc0000000 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR2_BAR_SHFT 0x1e +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR2_BURST_BMSK 0x20000000 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR2_BURST_SHFT 0x1d +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR2_CACHEABLE_BMSK 0x10000000 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR2_CACHEABLE_SHFT 0x1c +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR2_DEVICE_BMSK 0x8000000 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR2_DEVICE_SHFT 0x1b +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR2_DEVICE_TYPE_BMSK 0x6000000 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR2_DEVICE_TYPE_SHFT 0x19 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR2_EARLYWRRESP_BMSK 0x1000000 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR2_EARLYWRRESP_SHFT 0x18 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR2_ERROR_BMSK 0x800000 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR2_ERROR_SHFT 0x17 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR2_EXCLUSIVE_BMSK 0x400000 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR2_EXCLUSIVE_SHFT 0x16 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR2_FULL_BMSK 0x200000 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR2_FULL_SHFT 0x15 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR2_SHARED_BMSK 0x100000 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR2_SHARED_SHFT 0x14 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR2_WRITETHROUGH_BMSK 0x80000 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR2_WRITETHROUGH_SHFT 0x13 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR2_INNERNOALLOCATE_BMSK 0x40000 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR2_INNERNOALLOCATE_SHFT 0x12 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR2_INNERCACHEABLE_BMSK 0x20000 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR2_INNERCACHEABLE_SHFT 0x11 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR2_INNERSHARED_BMSK 0x10000 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR2_INNERSHARED_SHFT 0x10 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR2_INNERTRANSIENT_BMSK 0x8000 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR2_INNERTRANSIENT_SHFT 0xf +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR2_INNERWRITETHROUGH_BMSK 0x4000 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR2_INNERWRITETHROUGH_SHFT 0xe +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR2_PORTMREL_BMSK 0x2000 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR2_PORTMREL_SHFT 0xd +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR2_ORDEREDRD_BMSK 0x1000 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR2_ORDEREDRD_SHFT 0xc +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR2_ORDEREDWR_BMSK 0x800 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR2_ORDEREDWR_SHFT 0xb +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR2_OOORD_BMSK 0x400 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR2_OOORD_SHFT 0xa +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR2_OOOWR_BMSK 0x200 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR2_OOOWR_SHFT 0x9 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR2_NOALLOCATE_BMSK 0x100 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR2_NOALLOCATE_SHFT 0x8 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR2_TRANSIENT_BMSK 0x80 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR2_TRANSIENT_SHFT 0x7 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR2_MEMTYPE_BMSK 0x7 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_ESYNR2_MEMTYPE_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_EAR1_ADDR (IPA_GSI_TOP_XPU3_REG_BASE + 0x00000884) +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_EAR1_PHYS (IPA_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000884) +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_EAR1_OFFS (IPA_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000884) +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_EAR1_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_EAR1_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_EAR1_IN \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_QAD1_EAR1_ADDR, HWIO_IPA_GSI_TOP_XPU3_QAD1_EAR1_RMSK) +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_EAR1_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_QAD1_EAR1_ADDR, m) +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_EAR1_ADDR_63_32_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_XPU3_QAD1_EAR1_ADDR_63_32_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_XPU3_RGN_OWNERSTATUSr_ADDR(r) (IPA_GSI_TOP_XPU3_REG_BASE + 0x00000900 + 0x4 * (r)) +#define HWIO_IPA_GSI_TOP_XPU3_RGN_OWNERSTATUSr_PHYS(r) (IPA_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00000900 + 0x4 * (r)) +#define HWIO_IPA_GSI_TOP_XPU3_RGN_OWNERSTATUSr_OFFS(r) (IPA_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00000900 + 0x4 * (r)) +#define HWIO_IPA_GSI_TOP_XPU3_RGN_OWNERSTATUSr_RMSK 0x1fffff +#define HWIO_IPA_GSI_TOP_XPU3_RGN_OWNERSTATUSr_MAXr 0 +#define HWIO_IPA_GSI_TOP_XPU3_RGN_OWNERSTATUSr_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_RGN_OWNERSTATUSr_INI(r) \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_RGN_OWNERSTATUSr_ADDR(r), HWIO_IPA_GSI_TOP_XPU3_RGN_OWNERSTATUSr_RMSK) +#define HWIO_IPA_GSI_TOP_XPU3_RGN_OWNERSTATUSr_INMI(r,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_RGN_OWNERSTATUSr_ADDR(r), mask) +#define HWIO_IPA_GSI_TOP_XPU3_RGN_OWNERSTATUSr_RGOWNERSTATUS_BMSK 0x1fffff +#define HWIO_IPA_GSI_TOP_XPU3_RGN_OWNERSTATUSr_RGOWNERSTATUS_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_XPU3_RGn_GCR0_ADDR(n) (IPA_GSI_TOP_XPU3_REG_BASE + 0x00001000 + 0x80 * (n)) +#define HWIO_IPA_GSI_TOP_XPU3_RGn_GCR0_PHYS(n) (IPA_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00001000 + 0x80 * (n)) +#define HWIO_IPA_GSI_TOP_XPU3_RGn_GCR0_OFFS(n) (IPA_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00001000 + 0x80 * (n)) +#define HWIO_IPA_GSI_TOP_XPU3_RGn_GCR0_RMSK 0x107 +#define HWIO_IPA_GSI_TOP_XPU3_RGn_GCR0_MAXn 20 +#define HWIO_IPA_GSI_TOP_XPU3_RGn_GCR0_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_XPU3_RGn_GCR0_INI(n) \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_RGn_GCR0_ADDR(n), HWIO_IPA_GSI_TOP_XPU3_RGn_GCR0_RMSK) +#define HWIO_IPA_GSI_TOP_XPU3_RGn_GCR0_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_RGn_GCR0_ADDR(n), mask) +#define HWIO_IPA_GSI_TOP_XPU3_RGn_GCR0_OUTI(n,val) \ + out_dword(HWIO_IPA_GSI_TOP_XPU3_RGn_GCR0_ADDR(n),val) +#define HWIO_IPA_GSI_TOP_XPU3_RGn_GCR0_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_XPU3_RGn_GCR0_ADDR(n),mask,val,HWIO_IPA_GSI_TOP_XPU3_RGn_GCR0_INI(n)) +#define HWIO_IPA_GSI_TOP_XPU3_RGn_GCR0_RG_SEC_APPS_BMSK 0x100 +#define HWIO_IPA_GSI_TOP_XPU3_RGn_GCR0_RG_SEC_APPS_SHFT 0x8 +#define HWIO_IPA_GSI_TOP_XPU3_RGn_GCR0_RG_OWNER_BMSK 0x7 +#define HWIO_IPA_GSI_TOP_XPU3_RGn_GCR0_RG_OWNER_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_XPU3_RGn_GCR3_ADDR(n) (IPA_GSI_TOP_XPU3_REG_BASE + 0x0000100c + 0x80 * (n)) +#define HWIO_IPA_GSI_TOP_XPU3_RGn_GCR3_PHYS(n) (IPA_GSI_TOP_XPU3_REG_BASE_PHYS + 0x0000100c + 0x80 * (n)) +#define HWIO_IPA_GSI_TOP_XPU3_RGn_GCR3_OFFS(n) (IPA_GSI_TOP_XPU3_REG_BASE_OFFS + 0x0000100c + 0x80 * (n)) +#define HWIO_IPA_GSI_TOP_XPU3_RGn_GCR3_RMSK 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_RGn_GCR3_MAXn 20 +#define HWIO_IPA_GSI_TOP_XPU3_RGn_GCR3_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_XPU3_RGn_GCR3_INI(n) \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_RGn_GCR3_ADDR(n), HWIO_IPA_GSI_TOP_XPU3_RGn_GCR3_RMSK) +#define HWIO_IPA_GSI_TOP_XPU3_RGn_GCR3_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_RGn_GCR3_ADDR(n), mask) +#define HWIO_IPA_GSI_TOP_XPU3_RGn_GCR3_OUTI(n,val) \ + out_dword(HWIO_IPA_GSI_TOP_XPU3_RGn_GCR3_ADDR(n),val) +#define HWIO_IPA_GSI_TOP_XPU3_RGn_GCR3_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_XPU3_RGn_GCR3_ADDR(n),mask,val,HWIO_IPA_GSI_TOP_XPU3_RGn_GCR3_INI(n)) +#define HWIO_IPA_GSI_TOP_XPU3_RGn_GCR3_SECURE_ACCESS_LOCK_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_RGn_GCR3_SECURE_ACCESS_LOCK_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_XPU3_RGn_CR0_ADDR(n) (IPA_GSI_TOP_XPU3_REG_BASE + 0x00001010 + 0x80 * (n)) +#define HWIO_IPA_GSI_TOP_XPU3_RGn_CR0_PHYS(n) (IPA_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00001010 + 0x80 * (n)) +#define HWIO_IPA_GSI_TOP_XPU3_RGn_CR0_OFFS(n) (IPA_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00001010 + 0x80 * (n)) +#define HWIO_IPA_GSI_TOP_XPU3_RGn_CR0_RMSK 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_RGn_CR0_MAXn 20 +#define HWIO_IPA_GSI_TOP_XPU3_RGn_CR0_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_XPU3_RGn_CR0_INI(n) \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_RGn_CR0_ADDR(n), HWIO_IPA_GSI_TOP_XPU3_RGn_CR0_RMSK) +#define HWIO_IPA_GSI_TOP_XPU3_RGn_CR0_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_RGn_CR0_ADDR(n), mask) +#define HWIO_IPA_GSI_TOP_XPU3_RGn_CR0_OUTI(n,val) \ + out_dword(HWIO_IPA_GSI_TOP_XPU3_RGn_CR0_ADDR(n),val) +#define HWIO_IPA_GSI_TOP_XPU3_RGn_CR0_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_XPU3_RGn_CR0_ADDR(n),mask,val,HWIO_IPA_GSI_TOP_XPU3_RGn_CR0_INI(n)) +#define HWIO_IPA_GSI_TOP_XPU3_RGn_CR0_RGSCLRDEN_APPS_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_RGn_CR0_RGSCLRDEN_APPS_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_XPU3_RGn_CR1_ADDR(n) (IPA_GSI_TOP_XPU3_REG_BASE + 0x00001014 + 0x80 * (n)) +#define HWIO_IPA_GSI_TOP_XPU3_RGn_CR1_PHYS(n) (IPA_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00001014 + 0x80 * (n)) +#define HWIO_IPA_GSI_TOP_XPU3_RGn_CR1_OFFS(n) (IPA_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00001014 + 0x80 * (n)) +#define HWIO_IPA_GSI_TOP_XPU3_RGn_CR1_RMSK 0x7 +#define HWIO_IPA_GSI_TOP_XPU3_RGn_CR1_MAXn 20 +#define HWIO_IPA_GSI_TOP_XPU3_RGn_CR1_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_XPU3_RGn_CR1_INI(n) \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_RGn_CR1_ADDR(n), HWIO_IPA_GSI_TOP_XPU3_RGn_CR1_RMSK) +#define HWIO_IPA_GSI_TOP_XPU3_RGn_CR1_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_RGn_CR1_ADDR(n), mask) +#define HWIO_IPA_GSI_TOP_XPU3_RGn_CR1_OUTI(n,val) \ + out_dword(HWIO_IPA_GSI_TOP_XPU3_RGn_CR1_ADDR(n),val) +#define HWIO_IPA_GSI_TOP_XPU3_RGn_CR1_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_XPU3_RGn_CR1_ADDR(n),mask,val,HWIO_IPA_GSI_TOP_XPU3_RGn_CR1_INI(n)) +#define HWIO_IPA_GSI_TOP_XPU3_RGn_CR1_RGCLRDEN_BMSK 0x7 +#define HWIO_IPA_GSI_TOP_XPU3_RGn_CR1_RGCLRDEN_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_XPU3_RGn_CR2_ADDR(n) (IPA_GSI_TOP_XPU3_REG_BASE + 0x00001018 + 0x80 * (n)) +#define HWIO_IPA_GSI_TOP_XPU3_RGn_CR2_PHYS(n) (IPA_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00001018 + 0x80 * (n)) +#define HWIO_IPA_GSI_TOP_XPU3_RGn_CR2_OFFS(n) (IPA_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00001018 + 0x80 * (n)) +#define HWIO_IPA_GSI_TOP_XPU3_RGn_CR2_RMSK 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_RGn_CR2_MAXn 20 +#define HWIO_IPA_GSI_TOP_XPU3_RGn_CR2_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_XPU3_RGn_CR2_INI(n) \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_RGn_CR2_ADDR(n), HWIO_IPA_GSI_TOP_XPU3_RGn_CR2_RMSK) +#define HWIO_IPA_GSI_TOP_XPU3_RGn_CR2_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_RGn_CR2_ADDR(n), mask) +#define HWIO_IPA_GSI_TOP_XPU3_RGn_CR2_OUTI(n,val) \ + out_dword(HWIO_IPA_GSI_TOP_XPU3_RGn_CR2_ADDR(n),val) +#define HWIO_IPA_GSI_TOP_XPU3_RGn_CR2_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_XPU3_RGn_CR2_ADDR(n),mask,val,HWIO_IPA_GSI_TOP_XPU3_RGn_CR2_INI(n)) +#define HWIO_IPA_GSI_TOP_XPU3_RGn_CR2_RGSCLWREN_APPS_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_XPU3_RGn_CR2_RGSCLWREN_APPS_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_XPU3_RGn_CR3_ADDR(n) (IPA_GSI_TOP_XPU3_REG_BASE + 0x0000101c + 0x80 * (n)) +#define HWIO_IPA_GSI_TOP_XPU3_RGn_CR3_PHYS(n) (IPA_GSI_TOP_XPU3_REG_BASE_PHYS + 0x0000101c + 0x80 * (n)) +#define HWIO_IPA_GSI_TOP_XPU3_RGn_CR3_OFFS(n) (IPA_GSI_TOP_XPU3_REG_BASE_OFFS + 0x0000101c + 0x80 * (n)) +#define HWIO_IPA_GSI_TOP_XPU3_RGn_CR3_RMSK 0x7 +#define HWIO_IPA_GSI_TOP_XPU3_RGn_CR3_MAXn 20 +#define HWIO_IPA_GSI_TOP_XPU3_RGn_CR3_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_XPU3_RGn_CR3_INI(n) \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_RGn_CR3_ADDR(n), HWIO_IPA_GSI_TOP_XPU3_RGn_CR3_RMSK) +#define HWIO_IPA_GSI_TOP_XPU3_RGn_CR3_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_RGn_CR3_ADDR(n), mask) +#define HWIO_IPA_GSI_TOP_XPU3_RGn_CR3_OUTI(n,val) \ + out_dword(HWIO_IPA_GSI_TOP_XPU3_RGn_CR3_ADDR(n),val) +#define HWIO_IPA_GSI_TOP_XPU3_RGn_CR3_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_XPU3_RGn_CR3_ADDR(n),mask,val,HWIO_IPA_GSI_TOP_XPU3_RGn_CR3_INI(n)) +#define HWIO_IPA_GSI_TOP_XPU3_RGn_CR3_RGCLWREN_BMSK 0x7 +#define HWIO_IPA_GSI_TOP_XPU3_RGn_CR3_RGCLWREN_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_XPU3_RGn_RACR_ADDR(n) (IPA_GSI_TOP_XPU3_REG_BASE + 0x00001040 + 0x80 * (n)) +#define HWIO_IPA_GSI_TOP_XPU3_RGn_RACR_PHYS(n) (IPA_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00001040 + 0x80 * (n)) +#define HWIO_IPA_GSI_TOP_XPU3_RGn_RACR_OFFS(n) (IPA_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00001040 + 0x80 * (n)) +#define HWIO_IPA_GSI_TOP_XPU3_RGn_RACR_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_XPU3_RGn_RACR_MAXn 20 +#define HWIO_IPA_GSI_TOP_XPU3_RGn_RACR_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_XPU3_RGn_RACR_INI(n) \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_RGn_RACR_ADDR(n), HWIO_IPA_GSI_TOP_XPU3_RGn_RACR_RMSK) +#define HWIO_IPA_GSI_TOP_XPU3_RGn_RACR_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_RGn_RACR_ADDR(n), mask) +#define HWIO_IPA_GSI_TOP_XPU3_RGn_RACR_OUTI(n,val) \ + out_dword(HWIO_IPA_GSI_TOP_XPU3_RGn_RACR_ADDR(n),val) +#define HWIO_IPA_GSI_TOP_XPU3_RGn_RACR_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_XPU3_RGn_RACR_ADDR(n),mask,val,HWIO_IPA_GSI_TOP_XPU3_RGn_RACR_INI(n)) +#define HWIO_IPA_GSI_TOP_XPU3_RGn_RACR_RE_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_XPU3_RGn_RACR_RE_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_XPU3_RGn_WACR_ADDR(n) (IPA_GSI_TOP_XPU3_REG_BASE + 0x00001060 + 0x80 * (n)) +#define HWIO_IPA_GSI_TOP_XPU3_RGn_WACR_PHYS(n) (IPA_GSI_TOP_XPU3_REG_BASE_PHYS + 0x00001060 + 0x80 * (n)) +#define HWIO_IPA_GSI_TOP_XPU3_RGn_WACR_OFFS(n) (IPA_GSI_TOP_XPU3_REG_BASE_OFFS + 0x00001060 + 0x80 * (n)) +#define HWIO_IPA_GSI_TOP_XPU3_RGn_WACR_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_XPU3_RGn_WACR_MAXn 20 +#define HWIO_IPA_GSI_TOP_XPU3_RGn_WACR_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_XPU3_RGn_WACR_INI(n) \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_RGn_WACR_ADDR(n), HWIO_IPA_GSI_TOP_XPU3_RGn_WACR_RMSK) +#define HWIO_IPA_GSI_TOP_XPU3_RGn_WACR_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_XPU3_RGn_WACR_ADDR(n), mask) +#define HWIO_IPA_GSI_TOP_XPU3_RGn_WACR_OUTI(n,val) \ + out_dword(HWIO_IPA_GSI_TOP_XPU3_RGn_WACR_ADDR(n),val) +#define HWIO_IPA_GSI_TOP_XPU3_RGn_WACR_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_XPU3_RGn_WACR_ADDR(n),mask,val,HWIO_IPA_GSI_TOP_XPU3_RGn_WACR_INI(n)) +#define HWIO_IPA_GSI_TOP_XPU3_RGn_WACR_WE_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_XPU3_RGn_WACR_WE_SHFT 0x0 + +/*---------------------------------------------------------------------------- + * MODULE: IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG + *--------------------------------------------------------------------------*/ + +#define IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE (SNOC_IPA_MS_MPU_CFG_BASE + 0x00000000) +#define IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS (SNOC_IPA_MS_MPU_CFG_BASE_PHYS + 0x00000000) +#define IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS 0x00000000 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_GCR0_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x00000000) +#define HWIO_IPA_MS_MPU_CFG_XPU3_GCR0_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x00000000) +#define HWIO_IPA_MS_MPU_CFG_XPU3_GCR0_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x00000000) +#define HWIO_IPA_MS_MPU_CFG_XPU3_GCR0_RMSK 0x3 +#define HWIO_IPA_MS_MPU_CFG_XPU3_GCR0_ATTR 0x3 +#define HWIO_IPA_MS_MPU_CFG_XPU3_GCR0_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_GCR0_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_GCR0_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_GCR0_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_GCR0_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_GCR0_OUT(v) \ + out_dword(HWIO_IPA_MS_MPU_CFG_XPU3_GCR0_ADDR,v) +#define HWIO_IPA_MS_MPU_CFG_XPU3_GCR0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_MS_MPU_CFG_XPU3_GCR0_ADDR,m,v,HWIO_IPA_MS_MPU_CFG_XPU3_GCR0_IN) +#define HWIO_IPA_MS_MPU_CFG_XPU3_GCR0_AALOG_MODE_DIS_BMSK 0x2 +#define HWIO_IPA_MS_MPU_CFG_XPU3_GCR0_AALOG_MODE_DIS_SHFT 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_GCR0_AADEN_BMSK 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_GCR0_AADEN_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_SCR0_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x00000008) +#define HWIO_IPA_MS_MPU_CFG_XPU3_SCR0_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x00000008) +#define HWIO_IPA_MS_MPU_CFG_XPU3_SCR0_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x00000008) +#define HWIO_IPA_MS_MPU_CFG_XPU3_SCR0_RMSK 0x10f +#define HWIO_IPA_MS_MPU_CFG_XPU3_SCR0_ATTR 0x3 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SCR0_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_SCR0_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_SCR0_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_SCR0_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_SCR0_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_SCR0_OUT(v) \ + out_dword(HWIO_IPA_MS_MPU_CFG_XPU3_SCR0_ADDR,v) +#define HWIO_IPA_MS_MPU_CFG_XPU3_SCR0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_MS_MPU_CFG_XPU3_SCR0_ADDR,m,v,HWIO_IPA_MS_MPU_CFG_XPU3_SCR0_IN) +#define HWIO_IPA_MS_MPU_CFG_XPU3_SCR0_DYNAMIC_CLK_EN_BMSK 0x100 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SCR0_DYNAMIC_CLK_EN_SHFT 0x8 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SCR0_SCLEIE_BMSK 0x8 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SCR0_SCLEIE_SHFT 0x3 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SCR0_SCFGEIE_BMSK 0x4 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SCR0_SCFGEIE_SHFT 0x2 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SCR0_SCLERE_BMSK 0x2 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SCR0_SCLERE_SHFT 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SCR0_SCFGERE_BMSK 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SCR0_SCFGERE_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_CR0_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x00000010) +#define HWIO_IPA_MS_MPU_CFG_XPU3_CR0_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x00000010) +#define HWIO_IPA_MS_MPU_CFG_XPU3_CR0_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x00000010) +#define HWIO_IPA_MS_MPU_CFG_XPU3_CR0_RMSK 0x10f +#define HWIO_IPA_MS_MPU_CFG_XPU3_CR0_ATTR 0x3 +#define HWIO_IPA_MS_MPU_CFG_XPU3_CR0_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_CR0_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_CR0_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_CR0_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_CR0_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_CR0_OUT(v) \ + out_dword(HWIO_IPA_MS_MPU_CFG_XPU3_CR0_ADDR,v) +#define HWIO_IPA_MS_MPU_CFG_XPU3_CR0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_MS_MPU_CFG_XPU3_CR0_ADDR,m,v,HWIO_IPA_MS_MPU_CFG_XPU3_CR0_IN) +#define HWIO_IPA_MS_MPU_CFG_XPU3_CR0_DYNAMIC_CLK_EN_BMSK 0x100 +#define HWIO_IPA_MS_MPU_CFG_XPU3_CR0_DYNAMIC_CLK_EN_SHFT 0x8 +#define HWIO_IPA_MS_MPU_CFG_XPU3_CR0_CLEIE_BMSK 0x8 +#define HWIO_IPA_MS_MPU_CFG_XPU3_CR0_CLEIE_SHFT 0x3 +#define HWIO_IPA_MS_MPU_CFG_XPU3_CR0_CFGEIE_BMSK 0x4 +#define HWIO_IPA_MS_MPU_CFG_XPU3_CR0_CFGEIE_SHFT 0x2 +#define HWIO_IPA_MS_MPU_CFG_XPU3_CR0_CLERE_BMSK 0x2 +#define HWIO_IPA_MS_MPU_CFG_XPU3_CR0_CLERE_SHFT 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_CR0_CFGERE_BMSK 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_CR0_CFGERE_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_GCR0_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x00000080) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_GCR0_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x00000080) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_GCR0_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x00000080) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_GCR0_RMSK 0x3 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_GCR0_ATTR 0x3 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_GCR0_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_GCR0_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_GCR0_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_GCR0_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_GCR0_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_GCR0_OUT(v) \ + out_dword(HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_GCR0_ADDR,v) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_GCR0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_GCR0_ADDR,m,v,HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_GCR0_IN) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_GCR0_QAD0LOG_MODE_DIS_BMSK 0x2 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_GCR0_QAD0LOG_MODE_DIS_SHFT 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_GCR0_QAD0DEN_BMSK 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_GCR0_QAD0DEN_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_CR0_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x00000090) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_CR0_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x00000090) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_CR0_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x00000090) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_CR0_RMSK 0x10f +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_CR0_ATTR 0x3 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_CR0_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_CR0_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_CR0_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_CR0_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_CR0_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_CR0_OUT(v) \ + out_dword(HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_CR0_ADDR,v) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_CR0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_CR0_ADDR,m,v,HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_CR0_IN) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_CR0_DYNAMIC_CLK_EN_BMSK 0x100 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_CR0_DYNAMIC_CLK_EN_SHFT 0x8 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_CR0_CLEIE_BMSK 0x8 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_CR0_CLEIE_SHFT 0x3 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_CR0_CFGEIE_BMSK 0x4 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_CR0_CFGEIE_SHFT 0x2 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_CR0_CLERE_BMSK 0x2 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_CR0_CLERE_SHFT 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_CR0_CFGERE_BMSK 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_CR0_CFGERE_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_GCR0_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x00000100) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_GCR0_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x00000100) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_GCR0_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x00000100) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_GCR0_RMSK 0x3 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_GCR0_ATTR 0x3 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_GCR0_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_GCR0_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_GCR0_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_GCR0_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_GCR0_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_GCR0_OUT(v) \ + out_dword(HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_GCR0_ADDR,v) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_GCR0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_GCR0_ADDR,m,v,HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_GCR0_IN) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_GCR0_QAD1LOG_MODE_DIS_BMSK 0x2 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_GCR0_QAD1LOG_MODE_DIS_SHFT 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_GCR0_QAD1DEN_BMSK 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_GCR0_QAD1DEN_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_CR0_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x00000110) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_CR0_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x00000110) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_CR0_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x00000110) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_CR0_RMSK 0x10f +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_CR0_ATTR 0x3 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_CR0_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_CR0_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_CR0_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_CR0_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_CR0_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_CR0_OUT(v) \ + out_dword(HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_CR0_ADDR,v) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_CR0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_CR0_ADDR,m,v,HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_CR0_IN) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_CR0_DYNAMIC_CLK_EN_BMSK 0x100 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_CR0_DYNAMIC_CLK_EN_SHFT 0x8 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_CR0_CLEIE_BMSK 0x8 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_CR0_CLEIE_SHFT 0x3 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_CR0_CFGEIE_BMSK 0x4 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_CR0_CFGEIE_SHFT 0x2 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_CR0_CLERE_BMSK 0x2 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_CR0_CLERE_SHFT 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_CR0_CFGERE_BMSK 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_CR0_CFGERE_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_GCR0_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x00000300) +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_GCR0_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x00000300) +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_GCR0_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x00000300) +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_GCR0_RMSK 0x107 +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_GCR0_ATTR 0x3 +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_GCR0_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_UMR_GCR0_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_UMR_GCR0_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_GCR0_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_UMR_GCR0_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_GCR0_OUT(v) \ + out_dword(HWIO_IPA_MS_MPU_CFG_XPU3_UMR_GCR0_ADDR,v) +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_GCR0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_MS_MPU_CFG_XPU3_UMR_GCR0_ADDR,m,v,HWIO_IPA_MS_MPU_CFG_XPU3_UMR_GCR0_IN) +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_GCR0_UMR_SEC_APPS_BMSK 0x100 +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_GCR0_UMR_SEC_APPS_SHFT 0x8 +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_GCR0_UMR_OWNER_BMSK 0x7 +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_GCR0_UMR_OWNER_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_GCR3_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x0000030c) +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_GCR3_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x0000030c) +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_GCR3_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x0000030c) +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_GCR3_RMSK 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_GCR3_ATTR 0x3 +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_GCR3_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_UMR_GCR3_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_UMR_GCR3_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_GCR3_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_UMR_GCR3_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_GCR3_OUT(v) \ + out_dword(HWIO_IPA_MS_MPU_CFG_XPU3_UMR_GCR3_ADDR,v) +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_GCR3_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_MS_MPU_CFG_XPU3_UMR_GCR3_ADDR,m,v,HWIO_IPA_MS_MPU_CFG_XPU3_UMR_GCR3_IN) +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_GCR3_UMR_SECURE_ACCESS_LOCK_BMSK 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_GCR3_UMR_SECURE_ACCESS_LOCK_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR0_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x00000310) +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR0_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x00000310) +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR0_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x00000310) +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR0_RMSK 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR0_ATTR 0x3 +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR0_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR0_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR0_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR0_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR0_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR0_OUT(v) \ + out_dword(HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR0_ADDR,v) +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR0_ADDR,m,v,HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR0_IN) +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR0_UMRSCLRDEN_APPS_BMSK 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR0_UMRSCLRDEN_APPS_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR1_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x00000314) +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR1_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x00000314) +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR1_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x00000314) +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR1_RMSK 0xf +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR1_ATTR 0x3 +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR1_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR1_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR1_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR1_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR1_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR1_OUT(v) \ + out_dword(HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR1_ADDR,v) +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR1_ADDR,m,v,HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR1_IN) +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR1_ARM_QC_APPROACH_BMSK 0x8 +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR1_ARM_QC_APPROACH_SHFT 0x3 +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR1_UMRCLRDEN_BMSK 0x7 +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR1_UMRCLRDEN_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR2_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x00000318) +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR2_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x00000318) +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR2_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x00000318) +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR2_RMSK 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR2_ATTR 0x3 +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR2_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR2_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR2_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR2_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR2_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR2_OUT(v) \ + out_dword(HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR2_ADDR,v) +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR2_ADDR,m,v,HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR2_IN) +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR2_UMRSCLWREN_APPS_BMSK 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR2_UMRSCLWREN_APPS_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR3_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x0000031c) +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR3_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x0000031c) +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR3_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x0000031c) +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR3_RMSK 0x7 +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR3_ATTR 0x3 +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR3_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR3_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR3_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR3_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR3_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR3_OUT(v) \ + out_dword(HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR3_ADDR,v) +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR3_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR3_ADDR,m,v,HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR3_IN) +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR3_UMRCLWREN_BMSK 0x7 +#define HWIO_IPA_MS_MPU_CFG_XPU3_UMR_CR3_UMRCLWREN_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_IDR3_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x000003ec) +#define HWIO_IPA_MS_MPU_CFG_XPU3_IDR3_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x000003ec) +#define HWIO_IPA_MS_MPU_CFG_XPU3_IDR3_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x000003ec) +#define HWIO_IPA_MS_MPU_CFG_XPU3_IDR3_RMSK 0x3ff +#define HWIO_IPA_MS_MPU_CFG_XPU3_IDR3_ATTR 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_IDR3_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_IDR3_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_IDR3_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_IDR3_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_IDR3_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_IDR3_PT_BMSK 0x200 +#define HWIO_IPA_MS_MPU_CFG_XPU3_IDR3_PT_SHFT 0x9 +#define HWIO_IPA_MS_MPU_CFG_XPU3_IDR3_MV_BMSK 0x100 +#define HWIO_IPA_MS_MPU_CFG_XPU3_IDR3_MV_SHFT 0x8 +#define HWIO_IPA_MS_MPU_CFG_XPU3_IDR3_NVMID_BMSK 0xff +#define HWIO_IPA_MS_MPU_CFG_XPU3_IDR3_NVMID_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_IDR2_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x000003f0) +#define HWIO_IPA_MS_MPU_CFG_XPU3_IDR2_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x000003f0) +#define HWIO_IPA_MS_MPU_CFG_XPU3_IDR2_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x000003f0) +#define HWIO_IPA_MS_MPU_CFG_XPU3_IDR2_RMSK 0xffffff0f +#define HWIO_IPA_MS_MPU_CFG_XPU3_IDR2_ATTR 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_IDR2_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_IDR2_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_IDR2_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_IDR2_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_IDR2_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_IDR2_NONSEC_EN_BMSK 0xff000000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_IDR2_NONSEC_EN_SHFT 0x18 +#define HWIO_IPA_MS_MPU_CFG_XPU3_IDR2_SEC_EN_BMSK 0xff0000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_IDR2_SEC_EN_SHFT 0x10 +#define HWIO_IPA_MS_MPU_CFG_XPU3_IDR2_VMIDACR_EN_BMSK 0xff00 +#define HWIO_IPA_MS_MPU_CFG_XPU3_IDR2_VMIDACR_EN_SHFT 0x8 +#define HWIO_IPA_MS_MPU_CFG_XPU3_IDR2_NUM_QAD_BMSK 0xf +#define HWIO_IPA_MS_MPU_CFG_XPU3_IDR2_NUM_QAD_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_IDR1_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x000003f4) +#define HWIO_IPA_MS_MPU_CFG_XPU3_IDR1_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x000003f4) +#define HWIO_IPA_MS_MPU_CFG_XPU3_IDR1_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x000003f4) +#define HWIO_IPA_MS_MPU_CFG_XPU3_IDR1_RMSK 0x3f3f3f3f +#define HWIO_IPA_MS_MPU_CFG_XPU3_IDR1_ATTR 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_IDR1_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_IDR1_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_IDR1_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_IDR1_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_IDR1_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_IDR1_CLIENT_ADDR_WIDTH_BMSK 0x3f000000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_IDR1_CLIENT_ADDR_WIDTH_SHFT 0x18 +#define HWIO_IPA_MS_MPU_CFG_XPU3_IDR1_CONFIG_ADDR_WIDTH_BMSK 0x3f0000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_IDR1_CONFIG_ADDR_WIDTH_SHFT 0x10 +#define HWIO_IPA_MS_MPU_CFG_XPU3_IDR1_MSB_MPU_BMSK 0x3f00 +#define HWIO_IPA_MS_MPU_CFG_XPU3_IDR1_MSB_MPU_SHFT 0x8 +#define HWIO_IPA_MS_MPU_CFG_XPU3_IDR1_LSB_BMSK 0x3f +#define HWIO_IPA_MS_MPU_CFG_XPU3_IDR1_LSB_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_IDR0_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x000003f8) +#define HWIO_IPA_MS_MPU_CFG_XPU3_IDR0_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x000003f8) +#define HWIO_IPA_MS_MPU_CFG_XPU3_IDR0_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x000003f8) +#define HWIO_IPA_MS_MPU_CFG_XPU3_IDR0_RMSK 0x3ff0073 +#define HWIO_IPA_MS_MPU_CFG_XPU3_IDR0_ATTR 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_IDR0_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_IDR0_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_IDR0_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_IDR0_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_IDR0_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_IDR0_NRG_BMSK 0x3ff0000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_IDR0_NRG_SHFT 0x10 +#define HWIO_IPA_MS_MPU_CFG_XPU3_IDR0_BLED_BMSK 0x40 +#define HWIO_IPA_MS_MPU_CFG_XPU3_IDR0_BLED_SHFT 0x6 +#define HWIO_IPA_MS_MPU_CFG_XPU3_IDR0_CLIENTREQ_HALT_ACK_HW_EN_BMSK 0x20 +#define HWIO_IPA_MS_MPU_CFG_XPU3_IDR0_CLIENTREQ_HALT_ACK_HW_EN_SHFT 0x5 +#define HWIO_IPA_MS_MPU_CFG_XPU3_IDR0_XPU_CLIENT_PIPELINE_EN_BMSK 0x10 +#define HWIO_IPA_MS_MPU_CFG_XPU3_IDR0_XPU_CLIENT_PIPELINE_EN_SHFT 0x4 +#define HWIO_IPA_MS_MPU_CFG_XPU3_IDR0_XPUTYPE_BMSK 0x3 +#define HWIO_IPA_MS_MPU_CFG_XPU3_IDR0_XPUTYPE_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_REV_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x000003fc) +#define HWIO_IPA_MS_MPU_CFG_XPU3_REV_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x000003fc) +#define HWIO_IPA_MS_MPU_CFG_XPU3_REV_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x000003fc) +#define HWIO_IPA_MS_MPU_CFG_XPU3_REV_RMSK 0xffffffff +#define HWIO_IPA_MS_MPU_CFG_XPU3_REV_ATTR 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_REV_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_REV_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_REV_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_REV_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_REV_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_REV_MAJOR_BMSK 0xf0000000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_REV_MAJOR_SHFT 0x1c +#define HWIO_IPA_MS_MPU_CFG_XPU3_REV_MINOR_BMSK 0xfff0000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_REV_MINOR_SHFT 0x10 +#define HWIO_IPA_MS_MPU_CFG_XPU3_REV_STEP_BMSK 0xffff +#define HWIO_IPA_MS_MPU_CFG_XPU3_REV_STEP_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_LOG_MODE_DIS_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x00000400) +#define HWIO_IPA_MS_MPU_CFG_XPU3_LOG_MODE_DIS_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x00000400) +#define HWIO_IPA_MS_MPU_CFG_XPU3_LOG_MODE_DIS_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x00000400) +#define HWIO_IPA_MS_MPU_CFG_XPU3_LOG_MODE_DIS_RMSK 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_LOG_MODE_DIS_ATTR 0x3 +#define HWIO_IPA_MS_MPU_CFG_XPU3_LOG_MODE_DIS_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_LOG_MODE_DIS_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_LOG_MODE_DIS_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_LOG_MODE_DIS_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_LOG_MODE_DIS_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_LOG_MODE_DIS_OUT(v) \ + out_dword(HWIO_IPA_MS_MPU_CFG_XPU3_LOG_MODE_DIS_ADDR,v) +#define HWIO_IPA_MS_MPU_CFG_XPU3_LOG_MODE_DIS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_MS_MPU_CFG_XPU3_LOG_MODE_DIS_ADDR,m,v,HWIO_IPA_MS_MPU_CFG_XPU3_LOG_MODE_DIS_IN) +#define HWIO_IPA_MS_MPU_CFG_XPU3_LOG_MODE_DIS_LOG_MODE_DIS_BMSK 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_LOG_MODE_DIS_LOG_MODE_DIS_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_FREESTATUSr_ADDR(r) (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x00000500 + 0x4 * (r)) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_FREESTATUSr_PHYS(r) (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x00000500 + 0x4 * (r)) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_FREESTATUSr_OFFS(r) (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x00000500 + 0x4 * (r)) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_FREESTATUSr_RMSK 0x3ff +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_FREESTATUSr_MAXr 0 +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_FREESTATUSr_ATTR 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_FREESTATUSr_INI(r) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_RGN_FREESTATUSr_ADDR(r), HWIO_IPA_MS_MPU_CFG_XPU3_RGN_FREESTATUSr_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_FREESTATUSr_INMI(r,mask) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_RGN_FREESTATUSr_ADDR(r), mask) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_FREESTATUSr_RGFREESTATUS_BMSK 0x3ff +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_FREESTATUSr_RGFREESTATUS_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_SEAR0_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x00000800) +#define HWIO_IPA_MS_MPU_CFG_XPU3_SEAR0_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x00000800) +#define HWIO_IPA_MS_MPU_CFG_XPU3_SEAR0_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x00000800) +#define HWIO_IPA_MS_MPU_CFG_XPU3_SEAR0_RMSK 0xffffffff +#define HWIO_IPA_MS_MPU_CFG_XPU3_SEAR0_ATTR 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SEAR0_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_SEAR0_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_SEAR0_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_SEAR0_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_SEAR0_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_SEAR0_ADDR_31_0_BMSK 0xffffffff +#define HWIO_IPA_MS_MPU_CFG_XPU3_SEAR0_ADDR_31_0_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESR_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x00000808) +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESR_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x00000808) +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESR_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x00000808) +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESR_RMSK 0xf +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESR_ATTR 0x3 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESR_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_SESR_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_SESR_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESR_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_SESR_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESR_OUT(v) \ + out_dword(HWIO_IPA_MS_MPU_CFG_XPU3_SESR_ADDR,v) +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_MS_MPU_CFG_XPU3_SESR_ADDR,m,v,HWIO_IPA_MS_MPU_CFG_XPU3_SESR_IN) +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESR_CLMULTI_BMSK 0x8 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESR_CLMULTI_SHFT 0x3 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESR_CFGMULTI_BMSK 0x4 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESR_CFGMULTI_SHFT 0x2 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESR_CLIENT_BMSK 0x2 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESR_CLIENT_SHFT 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESR_CFG_BMSK 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESR_CFG_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESRRESTORE_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x0000080c) +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESRRESTORE_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x0000080c) +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESRRESTORE_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x0000080c) +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESRRESTORE_RMSK 0xf +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESRRESTORE_ATTR 0x3 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESRRESTORE_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_SESRRESTORE_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_SESRRESTORE_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESRRESTORE_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_SESRRESTORE_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESRRESTORE_OUT(v) \ + out_dword(HWIO_IPA_MS_MPU_CFG_XPU3_SESRRESTORE_ADDR,v) +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESRRESTORE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_MS_MPU_CFG_XPU3_SESRRESTORE_ADDR,m,v,HWIO_IPA_MS_MPU_CFG_XPU3_SESRRESTORE_IN) +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESRRESTORE_CLMULTI_BMSK 0x8 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESRRESTORE_CLMULTI_SHFT 0x3 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESRRESTORE_CFGMULTI_BMSK 0x4 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESRRESTORE_CFGMULTI_SHFT 0x2 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESRRESTORE_CLIENT_BMSK 0x2 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESRRESTORE_CLIENT_SHFT 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESRRESTORE_CFG_BMSK 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESRRESTORE_CFG_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR0_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x00000810) +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR0_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x00000810) +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR0_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x00000810) +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR0_RMSK 0x67ffff0f +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR0_ATTR 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR0_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR0_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR0_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR0_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR0_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR0_AC_BMSK 0x40000000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR0_AC_SHFT 0x1e +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR0_BURSTLEN_BMSK 0x20000000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR0_BURSTLEN_SHFT 0x1d +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR0_ASIZE_BMSK 0x7000000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR0_ASIZE_SHFT 0x18 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR0_ALEN_BMSK 0xff0000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR0_ALEN_SHFT 0x10 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR0_QAD_BMSK 0xff00 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR0_QAD_SHFT 0x8 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR0_XPRIV_BMSK 0x8 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR0_XPRIV_SHFT 0x3 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR0_XINST_BMSK 0x4 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR0_XINST_SHFT 0x2 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR0_AWRITE_BMSK 0x2 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR0_AWRITE_SHFT 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR0_XPROTNS_BMSK 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR0_XPROTNS_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR1_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x00000814) +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR1_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x00000814) +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR1_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x00000814) +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR1_RMSK 0xffffffff +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR1_ATTR 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR1_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR1_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR1_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR1_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR1_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR1_TID_BMSK 0xff000000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR1_TID_SHFT 0x18 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR1_VMID_BMSK 0xff0000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR1_VMID_SHFT 0x10 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR1_BID_BMSK 0xe000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR1_BID_SHFT 0xd +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR1_PID_BMSK 0x1f00 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR1_PID_SHFT 0x8 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR1_MID_BMSK 0xff +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR1_MID_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR2_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x00000818) +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR2_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x00000818) +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR2_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x00000818) +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR2_RMSK 0xffffff87 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR2_ATTR 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR2_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR2_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR2_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR2_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR2_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR2_BAR_BMSK 0xc0000000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR2_BAR_SHFT 0x1e +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR2_BURST_BMSK 0x20000000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR2_BURST_SHFT 0x1d +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR2_CACHEABLE_BMSK 0x10000000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR2_CACHEABLE_SHFT 0x1c +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR2_DEVICE_BMSK 0x8000000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR2_DEVICE_SHFT 0x1b +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR2_DEVICE_TYPE_BMSK 0x6000000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR2_DEVICE_TYPE_SHFT 0x19 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR2_EARLYWRRESP_BMSK 0x1000000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR2_EARLYWRRESP_SHFT 0x18 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR2_ERROR_BMSK 0x800000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR2_ERROR_SHFT 0x17 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR2_EXCLUSIVE_BMSK 0x400000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR2_EXCLUSIVE_SHFT 0x16 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR2_FULL_BMSK 0x200000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR2_FULL_SHFT 0x15 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR2_SHARED_BMSK 0x100000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR2_SHARED_SHFT 0x14 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR2_WRITETHROUGH_BMSK 0x80000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR2_WRITETHROUGH_SHFT 0x13 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR2_INNERNOALLOCATE_BMSK 0x40000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR2_INNERNOALLOCATE_SHFT 0x12 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR2_INNERCACHEABLE_BMSK 0x20000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR2_INNERCACHEABLE_SHFT 0x11 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR2_INNERSHARED_BMSK 0x10000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR2_INNERSHARED_SHFT 0x10 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR2_INNERTRANSIENT_BMSK 0x8000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR2_INNERTRANSIENT_SHFT 0xf +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR2_INNERWRITETHROUGH_BMSK 0x4000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR2_INNERWRITETHROUGH_SHFT 0xe +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR2_PORTMREL_BMSK 0x2000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR2_PORTMREL_SHFT 0xd +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR2_ORDEREDRD_BMSK 0x1000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR2_ORDEREDRD_SHFT 0xc +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR2_ORDEREDWR_BMSK 0x800 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR2_ORDEREDWR_SHFT 0xb +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR2_OOORD_BMSK 0x400 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR2_OOORD_SHFT 0xa +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR2_OOOWR_BMSK 0x200 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR2_OOOWR_SHFT 0x9 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR2_NOALLOCATE_BMSK 0x100 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR2_NOALLOCATE_SHFT 0x8 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR2_TRANSIENT_BMSK 0x80 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR2_TRANSIENT_SHFT 0x7 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR2_MEMTYPE_BMSK 0x7 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR2_MEMTYPE_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_SEAR1_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x00000804) +#define HWIO_IPA_MS_MPU_CFG_XPU3_SEAR1_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x00000804) +#define HWIO_IPA_MS_MPU_CFG_XPU3_SEAR1_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x00000804) +#define HWIO_IPA_MS_MPU_CFG_XPU3_SEAR1_RMSK 0xffffffff +#define HWIO_IPA_MS_MPU_CFG_XPU3_SEAR1_ATTR 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SEAR1_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_SEAR1_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_SEAR1_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_SEAR1_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_SEAR1_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_SEAR1_ADDR_63_32_BMSK 0xffffffff +#define HWIO_IPA_MS_MPU_CFG_XPU3_SEAR1_ADDR_63_32_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR3_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x0000081c) +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR3_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x0000081c) +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR3_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x0000081c) +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR3_RMSK 0xffff +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR3_ATTR 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR3_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR3_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR3_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR3_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR3_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR3_SEC_AD_RG_MATCH_BMSK 0xff00 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR3_SEC_AD_RG_MATCH_SHFT 0x8 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR3_NONSEC_AD_RG_MATCH_BMSK 0xff +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR3_NONSEC_AD_RG_MATCH_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR4_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x00000820) +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR4_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x00000820) +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR4_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x00000820) +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR4_RMSK 0x3ffffff +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR4_ATTR 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR4_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR4_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR4_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR4_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR4_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR4_ACACHEOPTYPE_BMSK 0x3c00000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR4_ACACHEOPTYPE_SHFT 0x16 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR4_ASID_BMSK 0x3e0000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR4_ASID_SHFT 0x11 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR4_ACGRANULETRANS_BMSK 0x10000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR4_ACGRANULETRANS_SHFT 0x10 +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR4_AUATTR_BMSK 0xffff +#define HWIO_IPA_MS_MPU_CFG_XPU3_SESYNR4_AUATTR_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_START0_SSHADOW_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x00000830) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_START0_SSHADOW_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x00000830) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_START0_SSHADOW_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x00000830) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_START0_SSHADOW_RMSK 0xfffff000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_START0_SSHADOW_ATTR 0x3 +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_START0_SSHADOW_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_RGN_START0_SSHADOW_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_RGN_START0_SSHADOW_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_START0_SSHADOW_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_RGN_START0_SSHADOW_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_START0_SSHADOW_OUT(v) \ + out_dword(HWIO_IPA_MS_MPU_CFG_XPU3_RGN_START0_SSHADOW_ADDR,v) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_START0_SSHADOW_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_MS_MPU_CFG_XPU3_RGN_START0_SSHADOW_ADDR,m,v,HWIO_IPA_MS_MPU_CFG_XPU3_RGN_START0_SSHADOW_IN) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_START0_SSHADOW_ADDR_31_0_BMSK 0xfffff000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_START0_SSHADOW_ADDR_31_0_SHFT 0xc + +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_END0_SSHADOW_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x00000838) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_END0_SSHADOW_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x00000838) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_END0_SSHADOW_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x00000838) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_END0_SSHADOW_RMSK 0xfffff000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_END0_SSHADOW_ATTR 0x3 +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_END0_SSHADOW_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_RGN_END0_SSHADOW_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_RGN_END0_SSHADOW_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_END0_SSHADOW_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_RGN_END0_SSHADOW_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_END0_SSHADOW_OUT(v) \ + out_dword(HWIO_IPA_MS_MPU_CFG_XPU3_RGN_END0_SSHADOW_ADDR,v) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_END0_SSHADOW_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_MS_MPU_CFG_XPU3_RGN_END0_SSHADOW_ADDR,m,v,HWIO_IPA_MS_MPU_CFG_XPU3_RGN_END0_SSHADOW_IN) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_END0_SSHADOW_ADDR_31_0_BMSK 0xfffff000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_END0_SSHADOW_ADDR_31_0_SHFT 0xc + +#define HWIO_IPA_MS_MPU_CFG_XPU3_EAR0_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x00000880) +#define HWIO_IPA_MS_MPU_CFG_XPU3_EAR0_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x00000880) +#define HWIO_IPA_MS_MPU_CFG_XPU3_EAR0_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x00000880) +#define HWIO_IPA_MS_MPU_CFG_XPU3_EAR0_RMSK 0xffffffff +#define HWIO_IPA_MS_MPU_CFG_XPU3_EAR0_ATTR 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_EAR0_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_EAR0_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_EAR0_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_EAR0_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_EAR0_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_EAR0_ADDR_31_0_BMSK 0xffffffff +#define HWIO_IPA_MS_MPU_CFG_XPU3_EAR0_ADDR_31_0_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESR_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x00000888) +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESR_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x00000888) +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESR_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x00000888) +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESR_RMSK 0xf +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESR_ATTR 0x3 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESR_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_ESR_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_ESR_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESR_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_ESR_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESR_OUT(v) \ + out_dword(HWIO_IPA_MS_MPU_CFG_XPU3_ESR_ADDR,v) +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_MS_MPU_CFG_XPU3_ESR_ADDR,m,v,HWIO_IPA_MS_MPU_CFG_XPU3_ESR_IN) +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESR_CLMULTI_BMSK 0x8 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESR_CLMULTI_SHFT 0x3 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESR_CFGMULTI_BMSK 0x4 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESR_CFGMULTI_SHFT 0x2 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESR_CLIENT_BMSK 0x2 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESR_CLIENT_SHFT 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESR_CFG_BMSK 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESR_CFG_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESRRESTORE_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x0000088c) +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESRRESTORE_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x0000088c) +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESRRESTORE_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x0000088c) +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESRRESTORE_RMSK 0xf +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESRRESTORE_ATTR 0x3 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESRRESTORE_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_ESRRESTORE_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_ESRRESTORE_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESRRESTORE_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_ESRRESTORE_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESRRESTORE_OUT(v) \ + out_dword(HWIO_IPA_MS_MPU_CFG_XPU3_ESRRESTORE_ADDR,v) +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESRRESTORE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_MS_MPU_CFG_XPU3_ESRRESTORE_ADDR,m,v,HWIO_IPA_MS_MPU_CFG_XPU3_ESRRESTORE_IN) +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESRRESTORE_CLMULTI_BMSK 0x8 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESRRESTORE_CLMULTI_SHFT 0x3 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESRRESTORE_CFGMULTI_BMSK 0x4 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESRRESTORE_CFGMULTI_SHFT 0x2 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESRRESTORE_CLIENT_BMSK 0x2 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESRRESTORE_CLIENT_SHFT 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESRRESTORE_CFG_BMSK 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESRRESTORE_CFG_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR0_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x00000890) +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR0_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x00000890) +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR0_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x00000890) +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR0_RMSK 0x67ffff0f +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR0_ATTR 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR0_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR0_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR0_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR0_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR0_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR0_AC_BMSK 0x40000000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR0_AC_SHFT 0x1e +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR0_BURSTLEN_BMSK 0x20000000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR0_BURSTLEN_SHFT 0x1d +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR0_ASIZE_BMSK 0x7000000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR0_ASIZE_SHFT 0x18 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR0_ALEN_BMSK 0xff0000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR0_ALEN_SHFT 0x10 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR0_QAD_BMSK 0xff00 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR0_QAD_SHFT 0x8 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR0_XPRIV_BMSK 0x8 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR0_XPRIV_SHFT 0x3 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR0_XINST_BMSK 0x4 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR0_XINST_SHFT 0x2 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR0_AWRITE_BMSK 0x2 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR0_AWRITE_SHFT 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR0_XPROTNS_BMSK 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR0_XPROTNS_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR1_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x00000894) +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR1_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x00000894) +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR1_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x00000894) +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR1_RMSK 0xffffffff +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR1_ATTR 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR1_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR1_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR1_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR1_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR1_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR1_TID_BMSK 0xff000000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR1_TID_SHFT 0x18 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR1_VMID_BMSK 0xff0000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR1_VMID_SHFT 0x10 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR1_BID_BMSK 0xe000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR1_BID_SHFT 0xd +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR1_PID_BMSK 0x1f00 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR1_PID_SHFT 0x8 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR1_MID_BMSK 0xff +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR1_MID_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR2_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x00000898) +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR2_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x00000898) +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR2_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x00000898) +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR2_RMSK 0xffffff87 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR2_ATTR 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR2_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR2_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR2_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR2_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR2_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR2_BAR_BMSK 0xc0000000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR2_BAR_SHFT 0x1e +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR2_BURST_BMSK 0x20000000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR2_BURST_SHFT 0x1d +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR2_CACHEABLE_BMSK 0x10000000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR2_CACHEABLE_SHFT 0x1c +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR2_DEVICE_BMSK 0x8000000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR2_DEVICE_SHFT 0x1b +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR2_DEVICE_TYPE_BMSK 0x6000000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR2_DEVICE_TYPE_SHFT 0x19 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR2_EARLYWRRESP_BMSK 0x1000000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR2_EARLYWRRESP_SHFT 0x18 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR2_ERROR_BMSK 0x800000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR2_ERROR_SHFT 0x17 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR2_EXCLUSIVE_BMSK 0x400000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR2_EXCLUSIVE_SHFT 0x16 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR2_FULL_BMSK 0x200000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR2_FULL_SHFT 0x15 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR2_SHARED_BMSK 0x100000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR2_SHARED_SHFT 0x14 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR2_WRITETHROUGH_BMSK 0x80000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR2_WRITETHROUGH_SHFT 0x13 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR2_INNERNOALLOCATE_BMSK 0x40000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR2_INNERNOALLOCATE_SHFT 0x12 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR2_INNERCACHEABLE_BMSK 0x20000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR2_INNERCACHEABLE_SHFT 0x11 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR2_INNERSHARED_BMSK 0x10000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR2_INNERSHARED_SHFT 0x10 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR2_INNERTRANSIENT_BMSK 0x8000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR2_INNERTRANSIENT_SHFT 0xf +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR2_INNERWRITETHROUGH_BMSK 0x4000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR2_INNERWRITETHROUGH_SHFT 0xe +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR2_PORTMREL_BMSK 0x2000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR2_PORTMREL_SHFT 0xd +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR2_ORDEREDRD_BMSK 0x1000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR2_ORDEREDRD_SHFT 0xc +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR2_ORDEREDWR_BMSK 0x800 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR2_ORDEREDWR_SHFT 0xb +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR2_OOORD_BMSK 0x400 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR2_OOORD_SHFT 0xa +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR2_OOOWR_BMSK 0x200 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR2_OOOWR_SHFT 0x9 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR2_NOALLOCATE_BMSK 0x100 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR2_NOALLOCATE_SHFT 0x8 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR2_TRANSIENT_BMSK 0x80 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR2_TRANSIENT_SHFT 0x7 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR2_MEMTYPE_BMSK 0x7 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR2_MEMTYPE_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_EAR1_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x00000884) +#define HWIO_IPA_MS_MPU_CFG_XPU3_EAR1_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x00000884) +#define HWIO_IPA_MS_MPU_CFG_XPU3_EAR1_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x00000884) +#define HWIO_IPA_MS_MPU_CFG_XPU3_EAR1_RMSK 0xffffffff +#define HWIO_IPA_MS_MPU_CFG_XPU3_EAR1_ATTR 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_EAR1_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_EAR1_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_EAR1_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_EAR1_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_EAR1_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_EAR1_ADDR_63_32_BMSK 0xffffffff +#define HWIO_IPA_MS_MPU_CFG_XPU3_EAR1_ADDR_63_32_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR3_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x0000089c) +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR3_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x0000089c) +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR3_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x0000089c) +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR3_RMSK 0xffff +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR3_ATTR 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR3_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR3_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR3_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR3_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR3_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR3_SEC_AD_RG_MATCH_BMSK 0xff00 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR3_SEC_AD_RG_MATCH_SHFT 0x8 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR3_NONSEC_AD_RG_MATCH_BMSK 0xff +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR3_NONSEC_AD_RG_MATCH_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR4_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x000008a0) +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR4_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x000008a0) +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR4_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x000008a0) +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR4_RMSK 0x3ffffff +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR4_ATTR 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR4_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR4_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR4_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR4_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR4_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR4_ACACHEOPTYPE_BMSK 0x3c00000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR4_ACACHEOPTYPE_SHFT 0x16 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR4_ASID_BMSK 0x3e0000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR4_ASID_SHFT 0x11 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR4_ACGRANULETRANS_BMSK 0x10000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR4_ACGRANULETRANS_SHFT 0x10 +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR4_AUATTR_BMSK 0xffff +#define HWIO_IPA_MS_MPU_CFG_XPU3_ESYNR4_AUATTR_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_START0_SHADOW_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x000008b0) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_START0_SHADOW_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x000008b0) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_START0_SHADOW_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x000008b0) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_START0_SHADOW_RMSK 0xfffff000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_START0_SHADOW_ATTR 0x3 +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_START0_SHADOW_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_RGN_START0_SHADOW_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_RGN_START0_SHADOW_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_START0_SHADOW_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_RGN_START0_SHADOW_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_START0_SHADOW_OUT(v) \ + out_dword(HWIO_IPA_MS_MPU_CFG_XPU3_RGN_START0_SHADOW_ADDR,v) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_START0_SHADOW_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_MS_MPU_CFG_XPU3_RGN_START0_SHADOW_ADDR,m,v,HWIO_IPA_MS_MPU_CFG_XPU3_RGN_START0_SHADOW_IN) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_START0_SHADOW_ADDR_31_0_BMSK 0xfffff000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_START0_SHADOW_ADDR_31_0_SHFT 0xc + +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_END0_SHADOW_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x000008b8) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_END0_SHADOW_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x000008b8) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_END0_SHADOW_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x000008b8) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_END0_SHADOW_RMSK 0xfffff000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_END0_SHADOW_ATTR 0x3 +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_END0_SHADOW_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_RGN_END0_SHADOW_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_RGN_END0_SHADOW_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_END0_SHADOW_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_RGN_END0_SHADOW_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_END0_SHADOW_OUT(v) \ + out_dword(HWIO_IPA_MS_MPU_CFG_XPU3_RGN_END0_SHADOW_ADDR,v) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_END0_SHADOW_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_MS_MPU_CFG_XPU3_RGN_END0_SHADOW_ADDR,m,v,HWIO_IPA_MS_MPU_CFG_XPU3_RGN_END0_SHADOW_IN) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_END0_SHADOW_ADDR_31_0_BMSK 0xfffff000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_END0_SHADOW_ADDR_31_0_SHFT 0xc + +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_EAR0_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x00000880) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_EAR0_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x00000880) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_EAR0_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x00000880) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_EAR0_RMSK 0xffffffff +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_EAR0_ATTR 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_EAR0_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_EAR0_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_EAR0_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_EAR0_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_EAR0_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_EAR0_ADDR_31_0_BMSK 0xffffffff +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_EAR0_ADDR_31_0_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESR_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x00000888) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESR_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x00000888) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESR_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x00000888) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESR_RMSK 0xf +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESR_ATTR 0x3 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESR_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESR_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESR_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESR_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESR_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESR_OUT(v) \ + out_dword(HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESR_ADDR,v) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESR_ADDR,m,v,HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESR_IN) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESR_CLMULTI_BMSK 0x8 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESR_CLMULTI_SHFT 0x3 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESR_CFGMULTI_BMSK 0x4 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESR_CFGMULTI_SHFT 0x2 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESR_CLIENT_BMSK 0x2 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESR_CLIENT_SHFT 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESR_CFG_BMSK 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESR_CFG_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESRRESTORE_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x0000088c) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESRRESTORE_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x0000088c) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESRRESTORE_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x0000088c) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESRRESTORE_RMSK 0xf +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESRRESTORE_ATTR 0x3 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESRRESTORE_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESRRESTORE_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESRRESTORE_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESRRESTORE_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESRRESTORE_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESRRESTORE_OUT(v) \ + out_dword(HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESRRESTORE_ADDR,v) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESRRESTORE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESRRESTORE_ADDR,m,v,HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESRRESTORE_IN) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESRRESTORE_CLMULTI_BMSK 0x8 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESRRESTORE_CLMULTI_SHFT 0x3 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESRRESTORE_CFGMULTI_BMSK 0x4 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESRRESTORE_CFGMULTI_SHFT 0x2 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESRRESTORE_CLIENT_BMSK 0x2 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESRRESTORE_CLIENT_SHFT 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESRRESTORE_CFG_BMSK 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESRRESTORE_CFG_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR0_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x00000890) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR0_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x00000890) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR0_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x00000890) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR0_RMSK 0x67ffff0f +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR0_ATTR 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR0_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR0_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR0_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR0_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR0_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR0_AC_BMSK 0x40000000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR0_AC_SHFT 0x1e +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR0_BURSTLEN_BMSK 0x20000000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR0_BURSTLEN_SHFT 0x1d +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR0_ASIZE_BMSK 0x7000000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR0_ASIZE_SHFT 0x18 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR0_ALEN_BMSK 0xff0000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR0_ALEN_SHFT 0x10 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR0_QAD_BMSK 0xff00 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR0_QAD_SHFT 0x8 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR0_XPRIV_BMSK 0x8 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR0_XPRIV_SHFT 0x3 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR0_XINST_BMSK 0x4 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR0_XINST_SHFT 0x2 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR0_AWRITE_BMSK 0x2 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR0_AWRITE_SHFT 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR0_XPROTNS_BMSK 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR0_XPROTNS_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR1_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x00000894) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR1_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x00000894) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR1_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x00000894) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR1_RMSK 0xffffffff +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR1_ATTR 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR1_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR1_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR1_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR1_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR1_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR1_TID_BMSK 0xff000000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR1_TID_SHFT 0x18 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR1_VMID_BMSK 0xff0000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR1_VMID_SHFT 0x10 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR1_BID_BMSK 0xe000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR1_BID_SHFT 0xd +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR1_PID_BMSK 0x1f00 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR1_PID_SHFT 0x8 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR1_MID_BMSK 0xff +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR1_MID_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR2_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x00000898) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR2_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x00000898) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR2_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x00000898) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR2_RMSK 0xffffff87 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR2_ATTR 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR2_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR2_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR2_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR2_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR2_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR2_BAR_BMSK 0xc0000000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR2_BAR_SHFT 0x1e +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR2_BURST_BMSK 0x20000000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR2_BURST_SHFT 0x1d +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR2_CACHEABLE_BMSK 0x10000000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR2_CACHEABLE_SHFT 0x1c +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR2_DEVICE_BMSK 0x8000000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR2_DEVICE_SHFT 0x1b +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR2_DEVICE_TYPE_BMSK 0x6000000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR2_DEVICE_TYPE_SHFT 0x19 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR2_EARLYWRRESP_BMSK 0x1000000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR2_EARLYWRRESP_SHFT 0x18 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR2_ERROR_BMSK 0x800000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR2_ERROR_SHFT 0x17 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR2_EXCLUSIVE_BMSK 0x400000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR2_EXCLUSIVE_SHFT 0x16 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR2_FULL_BMSK 0x200000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR2_FULL_SHFT 0x15 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR2_SHARED_BMSK 0x100000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR2_SHARED_SHFT 0x14 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR2_WRITETHROUGH_BMSK 0x80000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR2_WRITETHROUGH_SHFT 0x13 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR2_INNERNOALLOCATE_BMSK 0x40000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR2_INNERNOALLOCATE_SHFT 0x12 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR2_INNERCACHEABLE_BMSK 0x20000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR2_INNERCACHEABLE_SHFT 0x11 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR2_INNERSHARED_BMSK 0x10000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR2_INNERSHARED_SHFT 0x10 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR2_INNERTRANSIENT_BMSK 0x8000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR2_INNERTRANSIENT_SHFT 0xf +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR2_INNERWRITETHROUGH_BMSK 0x4000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR2_INNERWRITETHROUGH_SHFT 0xe +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR2_PORTMREL_BMSK 0x2000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR2_PORTMREL_SHFT 0xd +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR2_ORDEREDRD_BMSK 0x1000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR2_ORDEREDRD_SHFT 0xc +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR2_ORDEREDWR_BMSK 0x800 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR2_ORDEREDWR_SHFT 0xb +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR2_OOORD_BMSK 0x400 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR2_OOORD_SHFT 0xa +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR2_OOOWR_BMSK 0x200 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR2_OOOWR_SHFT 0x9 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR2_NOALLOCATE_BMSK 0x100 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR2_NOALLOCATE_SHFT 0x8 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR2_TRANSIENT_BMSK 0x80 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR2_TRANSIENT_SHFT 0x7 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR2_MEMTYPE_BMSK 0x7 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR2_MEMTYPE_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_EAR1_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x00000884) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_EAR1_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x00000884) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_EAR1_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x00000884) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_EAR1_RMSK 0xffffffff +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_EAR1_ATTR 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_EAR1_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_EAR1_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_EAR1_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_EAR1_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_EAR1_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_EAR1_ADDR_63_32_BMSK 0xffffffff +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_EAR1_ADDR_63_32_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR3_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x0000089c) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR3_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x0000089c) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR3_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x0000089c) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR3_RMSK 0xffff +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR3_ATTR 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR3_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR3_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR3_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR3_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR3_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR3_SEC_AD_RG_MATCH_BMSK 0xff00 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR3_SEC_AD_RG_MATCH_SHFT 0x8 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR3_NONSEC_AD_RG_MATCH_BMSK 0xff +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR3_NONSEC_AD_RG_MATCH_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR4_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x000008a0) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR4_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x000008a0) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR4_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x000008a0) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR4_RMSK 0x3ffffff +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR4_ATTR 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR4_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR4_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR4_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR4_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR4_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR4_ACACHEOPTYPE_BMSK 0x3c00000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR4_ACACHEOPTYPE_SHFT 0x16 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR4_ASID_BMSK 0x3e0000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR4_ASID_SHFT 0x11 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR4_ACGRANULETRANS_BMSK 0x10000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR4_ACGRANULETRANS_SHFT 0x10 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR4_AUATTR_BMSK 0xffff +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR4_AUATTR_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_RGN_START0_SHADOW_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x000008b0) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_RGN_START0_SHADOW_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x000008b0) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_RGN_START0_SHADOW_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x000008b0) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_RGN_START0_SHADOW_RMSK 0xfffff000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_RGN_START0_SHADOW_ATTR 0x3 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_RGN_START0_SHADOW_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_RGN_START0_SHADOW_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_RGN_START0_SHADOW_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_RGN_START0_SHADOW_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_RGN_START0_SHADOW_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_RGN_START0_SHADOW_OUT(v) \ + out_dword(HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_RGN_START0_SHADOW_ADDR,v) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_RGN_START0_SHADOW_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_RGN_START0_SHADOW_ADDR,m,v,HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_RGN_START0_SHADOW_IN) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_RGN_START0_SHADOW_ADDR_31_0_BMSK 0xfffff000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_RGN_START0_SHADOW_ADDR_31_0_SHFT 0xc + +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_RGN_END0_SHADOW_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x000008b8) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_RGN_END0_SHADOW_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x000008b8) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_RGN_END0_SHADOW_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x000008b8) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_RGN_END0_SHADOW_RMSK 0xfffff000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_RGN_END0_SHADOW_ATTR 0x3 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_RGN_END0_SHADOW_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_RGN_END0_SHADOW_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_RGN_END0_SHADOW_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_RGN_END0_SHADOW_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_RGN_END0_SHADOW_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_RGN_END0_SHADOW_OUT(v) \ + out_dword(HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_RGN_END0_SHADOW_ADDR,v) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_RGN_END0_SHADOW_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_RGN_END0_SHADOW_ADDR,m,v,HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_RGN_END0_SHADOW_IN) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_RGN_END0_SHADOW_ADDR_31_0_BMSK 0xfffff000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD0_RGN_END0_SHADOW_ADDR_31_0_SHFT 0xc + +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_EAR0_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x00000880) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_EAR0_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x00000880) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_EAR0_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x00000880) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_EAR0_RMSK 0xffffffff +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_EAR0_ATTR 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_EAR0_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_EAR0_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_EAR0_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_EAR0_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_EAR0_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_EAR0_ADDR_31_0_BMSK 0xffffffff +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_EAR0_ADDR_31_0_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESR_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x00000888) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESR_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x00000888) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESR_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x00000888) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESR_RMSK 0xf +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESR_ATTR 0x3 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESR_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESR_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESR_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESR_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESR_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESR_OUT(v) \ + out_dword(HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESR_ADDR,v) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESR_ADDR,m,v,HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESR_IN) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESR_CLMULTI_BMSK 0x8 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESR_CLMULTI_SHFT 0x3 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESR_CFGMULTI_BMSK 0x4 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESR_CFGMULTI_SHFT 0x2 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESR_CLIENT_BMSK 0x2 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESR_CLIENT_SHFT 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESR_CFG_BMSK 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESR_CFG_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESRRESTORE_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x0000088c) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESRRESTORE_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x0000088c) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESRRESTORE_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x0000088c) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESRRESTORE_RMSK 0xf +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESRRESTORE_ATTR 0x3 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESRRESTORE_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESRRESTORE_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESRRESTORE_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESRRESTORE_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESRRESTORE_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESRRESTORE_OUT(v) \ + out_dword(HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESRRESTORE_ADDR,v) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESRRESTORE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESRRESTORE_ADDR,m,v,HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESRRESTORE_IN) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESRRESTORE_CLMULTI_BMSK 0x8 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESRRESTORE_CLMULTI_SHFT 0x3 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESRRESTORE_CFGMULTI_BMSK 0x4 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESRRESTORE_CFGMULTI_SHFT 0x2 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESRRESTORE_CLIENT_BMSK 0x2 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESRRESTORE_CLIENT_SHFT 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESRRESTORE_CFG_BMSK 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESRRESTORE_CFG_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR0_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x00000890) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR0_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x00000890) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR0_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x00000890) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR0_RMSK 0x67ffff0f +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR0_ATTR 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR0_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR0_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR0_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR0_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR0_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR0_AC_BMSK 0x40000000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR0_AC_SHFT 0x1e +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR0_BURSTLEN_BMSK 0x20000000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR0_BURSTLEN_SHFT 0x1d +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR0_ASIZE_BMSK 0x7000000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR0_ASIZE_SHFT 0x18 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR0_ALEN_BMSK 0xff0000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR0_ALEN_SHFT 0x10 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR0_QAD_BMSK 0xff00 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR0_QAD_SHFT 0x8 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR0_XPRIV_BMSK 0x8 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR0_XPRIV_SHFT 0x3 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR0_XINST_BMSK 0x4 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR0_XINST_SHFT 0x2 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR0_AWRITE_BMSK 0x2 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR0_AWRITE_SHFT 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR0_XPROTNS_BMSK 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR0_XPROTNS_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR1_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x00000894) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR1_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x00000894) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR1_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x00000894) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR1_RMSK 0xffffffff +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR1_ATTR 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR1_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR1_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR1_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR1_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR1_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR1_TID_BMSK 0xff000000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR1_TID_SHFT 0x18 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR1_VMID_BMSK 0xff0000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR1_VMID_SHFT 0x10 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR1_BID_BMSK 0xe000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR1_BID_SHFT 0xd +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR1_PID_BMSK 0x1f00 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR1_PID_SHFT 0x8 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR1_MID_BMSK 0xff +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR1_MID_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR2_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x00000898) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR2_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x00000898) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR2_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x00000898) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR2_RMSK 0xffffff87 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR2_ATTR 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR2_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR2_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR2_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR2_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR2_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR2_BAR_BMSK 0xc0000000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR2_BAR_SHFT 0x1e +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR2_BURST_BMSK 0x20000000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR2_BURST_SHFT 0x1d +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR2_CACHEABLE_BMSK 0x10000000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR2_CACHEABLE_SHFT 0x1c +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR2_DEVICE_BMSK 0x8000000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR2_DEVICE_SHFT 0x1b +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR2_DEVICE_TYPE_BMSK 0x6000000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR2_DEVICE_TYPE_SHFT 0x19 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR2_EARLYWRRESP_BMSK 0x1000000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR2_EARLYWRRESP_SHFT 0x18 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR2_ERROR_BMSK 0x800000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR2_ERROR_SHFT 0x17 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR2_EXCLUSIVE_BMSK 0x400000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR2_EXCLUSIVE_SHFT 0x16 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR2_FULL_BMSK 0x200000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR2_FULL_SHFT 0x15 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR2_SHARED_BMSK 0x100000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR2_SHARED_SHFT 0x14 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR2_WRITETHROUGH_BMSK 0x80000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR2_WRITETHROUGH_SHFT 0x13 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR2_INNERNOALLOCATE_BMSK 0x40000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR2_INNERNOALLOCATE_SHFT 0x12 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR2_INNERCACHEABLE_BMSK 0x20000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR2_INNERCACHEABLE_SHFT 0x11 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR2_INNERSHARED_BMSK 0x10000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR2_INNERSHARED_SHFT 0x10 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR2_INNERTRANSIENT_BMSK 0x8000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR2_INNERTRANSIENT_SHFT 0xf +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR2_INNERWRITETHROUGH_BMSK 0x4000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR2_INNERWRITETHROUGH_SHFT 0xe +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR2_PORTMREL_BMSK 0x2000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR2_PORTMREL_SHFT 0xd +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR2_ORDEREDRD_BMSK 0x1000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR2_ORDEREDRD_SHFT 0xc +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR2_ORDEREDWR_BMSK 0x800 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR2_ORDEREDWR_SHFT 0xb +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR2_OOORD_BMSK 0x400 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR2_OOORD_SHFT 0xa +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR2_OOOWR_BMSK 0x200 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR2_OOOWR_SHFT 0x9 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR2_NOALLOCATE_BMSK 0x100 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR2_NOALLOCATE_SHFT 0x8 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR2_TRANSIENT_BMSK 0x80 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR2_TRANSIENT_SHFT 0x7 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR2_MEMTYPE_BMSK 0x7 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR2_MEMTYPE_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_EAR1_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x00000884) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_EAR1_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x00000884) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_EAR1_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x00000884) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_EAR1_RMSK 0xffffffff +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_EAR1_ATTR 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_EAR1_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_EAR1_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_EAR1_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_EAR1_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_EAR1_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_EAR1_ADDR_63_32_BMSK 0xffffffff +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_EAR1_ADDR_63_32_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR3_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x0000089c) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR3_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x0000089c) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR3_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x0000089c) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR3_RMSK 0xffff +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR3_ATTR 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR3_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR3_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR3_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR3_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR3_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR3_SEC_AD_RG_MATCH_BMSK 0xff00 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR3_SEC_AD_RG_MATCH_SHFT 0x8 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR3_NONSEC_AD_RG_MATCH_BMSK 0xff +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR3_NONSEC_AD_RG_MATCH_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR4_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x000008a0) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR4_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x000008a0) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR4_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x000008a0) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR4_RMSK 0x3ffffff +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR4_ATTR 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR4_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR4_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR4_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR4_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR4_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR4_ACACHEOPTYPE_BMSK 0x3c00000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR4_ACACHEOPTYPE_SHFT 0x16 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR4_ASID_BMSK 0x3e0000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR4_ASID_SHFT 0x11 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR4_ACGRANULETRANS_BMSK 0x10000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR4_ACGRANULETRANS_SHFT 0x10 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR4_AUATTR_BMSK 0xffff +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR4_AUATTR_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_RGN_START0_SHADOW_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x000008b0) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_RGN_START0_SHADOW_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x000008b0) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_RGN_START0_SHADOW_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x000008b0) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_RGN_START0_SHADOW_RMSK 0xfffff000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_RGN_START0_SHADOW_ATTR 0x3 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_RGN_START0_SHADOW_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_RGN_START0_SHADOW_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_RGN_START0_SHADOW_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_RGN_START0_SHADOW_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_RGN_START0_SHADOW_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_RGN_START0_SHADOW_OUT(v) \ + out_dword(HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_RGN_START0_SHADOW_ADDR,v) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_RGN_START0_SHADOW_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_RGN_START0_SHADOW_ADDR,m,v,HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_RGN_START0_SHADOW_IN) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_RGN_START0_SHADOW_ADDR_31_0_BMSK 0xfffff000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_RGN_START0_SHADOW_ADDR_31_0_SHFT 0xc + +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_RGN_END0_SHADOW_ADDR (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x000008b8) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_RGN_END0_SHADOW_PHYS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x000008b8) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_RGN_END0_SHADOW_OFFS (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x000008b8) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_RGN_END0_SHADOW_RMSK 0xfffff000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_RGN_END0_SHADOW_ATTR 0x3 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_RGN_END0_SHADOW_IN \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_RGN_END0_SHADOW_ADDR, HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_RGN_END0_SHADOW_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_RGN_END0_SHADOW_INM(m) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_RGN_END0_SHADOW_ADDR, m) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_RGN_END0_SHADOW_OUT(v) \ + out_dword(HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_RGN_END0_SHADOW_ADDR,v) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_RGN_END0_SHADOW_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_RGN_END0_SHADOW_ADDR,m,v,HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_RGN_END0_SHADOW_IN) +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_RGN_END0_SHADOW_ADDR_31_0_BMSK 0xfffff000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_QAD1_RGN_END0_SHADOW_ADDR_31_0_SHFT 0xc + +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_OWNERSTATUSr_ADDR(r) (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x00000900 + 0x4 * (r)) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_OWNERSTATUSr_PHYS(r) (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x00000900 + 0x4 * (r)) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_OWNERSTATUSr_OFFS(r) (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x00000900 + 0x4 * (r)) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_OWNERSTATUSr_RMSK 0x3ff +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_OWNERSTATUSr_MAXr 0 +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_OWNERSTATUSr_ATTR 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_OWNERSTATUSr_INI(r) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_RGN_OWNERSTATUSr_ADDR(r), HWIO_IPA_MS_MPU_CFG_XPU3_RGN_OWNERSTATUSr_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_OWNERSTATUSr_INMI(r,mask) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_RGN_OWNERSTATUSr_ADDR(r), mask) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_OWNERSTATUSr_RGOWNERSTATUS_BMSK 0x3ff +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGN_OWNERSTATUSr_RGOWNERSTATUS_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR0_ADDR(n) (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x00001000 + 0x80 * (n)) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR0_PHYS(n) (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x00001000 + 0x80 * (n)) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR0_OFFS(n) (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x00001000 + 0x80 * (n)) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR0_RMSK 0x107 +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR0_MAXn 9 +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR0_ATTR 0x3 +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR0_INI(n) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR0_ADDR(n), HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR0_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR0_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR0_ADDR(n), mask) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR0_OUTI(n,val) \ + out_dword(HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR0_ADDR(n),val) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR0_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR0_ADDR(n),mask,val,HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR0_INI(n)) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR0_RG_SEC_APPS_BMSK 0x100 +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR0_RG_SEC_APPS_SHFT 0x8 +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR0_RG_OWNER_BMSK 0x7 +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR0_RG_OWNER_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR1_ADDR(n) (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x00001004 + 0x80 * (n)) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR1_PHYS(n) (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x00001004 + 0x80 * (n)) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR1_OFFS(n) (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x00001004 + 0x80 * (n)) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR1_RMSK 0x80000000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR1_MAXn 9 +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR1_ATTR 0x3 +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR1_INI(n) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR1_ADDR(n), HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR1_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR1_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR1_ADDR(n), mask) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR1_OUTI(n,val) \ + out_dword(HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR1_ADDR(n),val) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR1_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR1_ADDR(n),mask,val,HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR1_INI(n)) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR1_PD_BMSK 0x80000000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR1_PD_SHFT 0x1f + +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR2_ADDR(n) (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x00001008 + 0x80 * (n)) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR2_PHYS(n) (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x00001008 + 0x80 * (n)) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR2_OFFS(n) (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x00001008 + 0x80 * (n)) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR2_RMSK 0x3 +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR2_MAXn 9 +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR2_ATTR 0x3 +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR2_INI(n) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR2_ADDR(n), HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR2_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR2_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR2_ADDR(n), mask) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR2_OUTI(n,val) \ + out_dword(HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR2_ADDR(n),val) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR2_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR2_ADDR(n),mask,val,HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR2_INI(n)) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR2_ASRC_BMSK 0x2 +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR2_ASRC_SHFT 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR2_CSRC_BMSK 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR2_CSRC_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR3_ADDR(n) (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x0000100c + 0x80 * (n)) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR3_PHYS(n) (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x0000100c + 0x80 * (n)) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR3_OFFS(n) (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x0000100c + 0x80 * (n)) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR3_RMSK 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR3_MAXn 9 +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR3_ATTR 0x3 +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR3_INI(n) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR3_ADDR(n), HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR3_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR3_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR3_ADDR(n), mask) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR3_OUTI(n,val) \ + out_dword(HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR3_ADDR(n),val) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR3_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR3_ADDR(n),mask,val,HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR3_INI(n)) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR3_SECURE_ACCESS_LOCK_BMSK 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_GCR3_SECURE_ACCESS_LOCK_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR0_ADDR(n) (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x00001010 + 0x80 * (n)) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR0_PHYS(n) (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x00001010 + 0x80 * (n)) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR0_OFFS(n) (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x00001010 + 0x80 * (n)) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR0_RMSK 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR0_MAXn 9 +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR0_ATTR 0x3 +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR0_INI(n) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR0_ADDR(n), HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR0_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR0_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR0_ADDR(n), mask) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR0_OUTI(n,val) \ + out_dword(HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR0_ADDR(n),val) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR0_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR0_ADDR(n),mask,val,HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR0_INI(n)) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR0_RGSCLRDEN_APPS_BMSK 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR0_RGSCLRDEN_APPS_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR1_ADDR(n) (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x00001014 + 0x80 * (n)) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR1_PHYS(n) (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x00001014 + 0x80 * (n)) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR1_OFFS(n) (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x00001014 + 0x80 * (n)) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR1_RMSK 0x7 +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR1_MAXn 9 +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR1_ATTR 0x3 +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR1_INI(n) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR1_ADDR(n), HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR1_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR1_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR1_ADDR(n), mask) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR1_OUTI(n,val) \ + out_dword(HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR1_ADDR(n),val) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR1_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR1_ADDR(n),mask,val,HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR1_INI(n)) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR1_RGCLRDEN_BMSK 0x7 +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR1_RGCLRDEN_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR2_ADDR(n) (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x00001018 + 0x80 * (n)) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR2_PHYS(n) (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x00001018 + 0x80 * (n)) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR2_OFFS(n) (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x00001018 + 0x80 * (n)) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR2_RMSK 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR2_MAXn 9 +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR2_ATTR 0x3 +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR2_INI(n) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR2_ADDR(n), HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR2_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR2_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR2_ADDR(n), mask) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR2_OUTI(n,val) \ + out_dword(HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR2_ADDR(n),val) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR2_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR2_ADDR(n),mask,val,HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR2_INI(n)) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR2_RGSCLWREN_APPS_BMSK 0x1 +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR2_RGSCLWREN_APPS_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR3_ADDR(n) (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x0000101c + 0x80 * (n)) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR3_PHYS(n) (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x0000101c + 0x80 * (n)) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR3_OFFS(n) (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x0000101c + 0x80 * (n)) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR3_RMSK 0x7 +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR3_MAXn 9 +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR3_ATTR 0x3 +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR3_INI(n) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR3_ADDR(n), HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR3_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR3_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR3_ADDR(n), mask) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR3_OUTI(n,val) \ + out_dword(HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR3_ADDR(n),val) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR3_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR3_ADDR(n),mask,val,HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR3_INI(n)) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR3_RGCLWREN_BMSK 0x7 +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_CR3_RGCLWREN_SHFT 0x0 + +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_START0_ADDR(n) (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x00001030 + 0x80 * (n)) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_START0_PHYS(n) (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x00001030 + 0x80 * (n)) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_START0_OFFS(n) (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x00001030 + 0x80 * (n)) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_START0_RMSK 0xfffff000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_START0_MAXn 9 +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_START0_ATTR 0x3 +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_START0_INI(n) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_RGn_START0_ADDR(n), HWIO_IPA_MS_MPU_CFG_XPU3_RGn_START0_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_START0_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_RGn_START0_ADDR(n), mask) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_START0_OUTI(n,val) \ + out_dword(HWIO_IPA_MS_MPU_CFG_XPU3_RGn_START0_ADDR(n),val) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_START0_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_MS_MPU_CFG_XPU3_RGn_START0_ADDR(n),mask,val,HWIO_IPA_MS_MPU_CFG_XPU3_RGn_START0_INI(n)) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_START0_ADDR_31_0_BMSK 0xfffff000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_START0_ADDR_31_0_SHFT 0xc + +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_END0_ADDR(n) (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE + 0x00001038 + 0x80 * (n)) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_END0_PHYS(n) (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_PHYS + 0x00001038 + 0x80 * (n)) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_END0_OFFS(n) (IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG_REG_BASE_OFFS + 0x00001038 + 0x80 * (n)) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_END0_RMSK 0xfffff000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_END0_MAXn 9 +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_END0_ATTR 0x3 +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_END0_INI(n) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_RGn_END0_ADDR(n), HWIO_IPA_MS_MPU_CFG_XPU3_RGn_END0_RMSK) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_END0_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_MS_MPU_CFG_XPU3_RGn_END0_ADDR(n), mask) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_END0_OUTI(n,val) \ + out_dword(HWIO_IPA_MS_MPU_CFG_XPU3_RGn_END0_ADDR(n),val) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_END0_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_MS_MPU_CFG_XPU3_RGn_END0_ADDR(n),mask,val,HWIO_IPA_MS_MPU_CFG_XPU3_RGn_END0_INI(n)) +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_END0_ADDR_31_0_BMSK 0xfffff000 +#define HWIO_IPA_MS_MPU_CFG_XPU3_RGn_END0_ADDR_31_0_SHFT 0xc + + +#endif /* __IPA_HWIO_H__ */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.0/ipa_hwio_def.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.0/ipa_hwio_def.h new file mode 100644 index 0000000000..4719245063 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.0/ipa_hwio_def.h @@ -0,0 +1,19091 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ + +#ifndef __IPA_HWIO_DEF_H__ +#define __IPA_HWIO_DEF_H__ +/** + @file ipa_hwio.h + @brief Auto-generated HWIO interface include file. + + This file contains HWIO register definitions for the following modules: + IPA.* + + 'Include' filters applied: + 'Exclude' filters applied: RESERVED DUMMY +*/ + +/*---------------------------------------------------------------------------- + * MODULE: IPA_UC_IPA_UC + *--------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------- + * MODULE: IPA_UC_IPA_UC_RAM + *--------------------------------------------------------------------------*/ + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_IRAM_START +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_iram_start_s +{ + u32 data : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_iram_start_u +{ + struct ipa_hwio_def_ipa_uc_iram_start_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_DRAM_START +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_dram_start_s +{ + u32 data : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_dram_start_u +{ + struct ipa_hwio_def_ipa_uc_dram_start_s def; + u32 value; +}; + +/*---------------------------------------------------------------------------- + * MODULE: IPA_UC_IPA_UC_PER + *--------------------------------------------------------------------------*/ + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_status_s +{ + u32 sleepdeep : 1; + u32 sleep : 1; + u32 lockup : 1; + u32 uc_enable : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_status_u +{ + struct ipa_hwio_def_ipa_uc_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_CONTROL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_control_s +{ + u32 reserved0 : 1; + u32 uc_dsmode : 1; + u32 qmb_snoc_bypass_dis : 1; + u32 uc_clock_gating_dis : 1; + u32 mbox_dis : 8; + u32 reserved1 : 12; + u32 warmboot_dis : 1; + u32 reserved2 : 2; + u32 uc_ram_rd_cli_cache_dis : 1; + u32 reserved3 : 4; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_control_u +{ + struct ipa_hwio_def_ipa_uc_control_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_SYS_BUS_ATTRIB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_sys_bus_attrib_s +{ + u32 memtype : 3; + u32 reserved0 : 1; + u32 noallocate : 1; + u32 reserved1 : 3; + u32 innershared : 1; + u32 reserved2 : 3; + u32 shared : 1; + u32 reserved3 : 19; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_sys_bus_attrib_u +{ + struct ipa_hwio_def_ipa_uc_sys_bus_attrib_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_PEND_IRQ +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_pend_irq_s +{ + u32 pend_irq : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_pend_irq_u +{ + struct ipa_hwio_def_ipa_uc_pend_irq_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_TRACE_BUFFER +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_trace_buffer_s +{ + u32 trace_buffer : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_trace_buffer_u +{ + struct ipa_hwio_def_ipa_uc_trace_buffer_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_PC +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_pc_s +{ + u32 pc : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_pc_u +{ + struct ipa_hwio_def_ipa_uc_pc_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_VUIC_INT_ADDRESS_LSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_vuic_int_address_lsb_s +{ + u32 addrress : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_vuic_int_address_lsb_u +{ + struct ipa_hwio_def_ipa_uc_vuic_int_address_lsb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_VUIC_INT_ADDRESS_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_vuic_int_address_msb_s +{ + u32 addrress : 9; + u32 reserved0 : 23; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_vuic_int_address_msb_u +{ + struct ipa_hwio_def_ipa_uc_vuic_int_address_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_QMB_SYS_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_qmb_sys_addr_s +{ + u32 addr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_qmb_sys_addr_u +{ + struct ipa_hwio_def_ipa_uc_qmb_sys_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_QMB_SYS_ADDR_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_qmb_sys_addr_msb_s +{ + u32 addr_msb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_qmb_sys_addr_msb_u +{ + struct ipa_hwio_def_ipa_uc_qmb_sys_addr_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_QMB_LOCAL_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_qmb_local_addr_s +{ + u32 addr : 18; + u32 reserved0 : 14; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_qmb_local_addr_u +{ + struct ipa_hwio_def_ipa_uc_qmb_local_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_QMB_LENGTH +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_qmb_length_s +{ + u32 length : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_qmb_length_u +{ + struct ipa_hwio_def_ipa_uc_qmb_length_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_QMB_TRIGGER +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_qmb_trigger_s +{ + u32 rsv : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_qmb_trigger_u +{ + struct ipa_hwio_def_ipa_uc_qmb_trigger_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_QMB_COMMAND_ATTR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_qmb_command_attr_s +{ + u32 direction : 1; + u32 inorder : 1; + u32 wait_for_response_mode : 1; + u32 sync : 1; + u32 interrupt_on_completion : 1; + u32 queue_number : 1; + u32 reserved0 : 10; + u32 user : 11; + u32 reserved1 : 5; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_qmb_command_attr_u +{ + struct ipa_hwio_def_ipa_uc_qmb_command_attr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_QMB_COMMAND_UCTAG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_qmb_command_uctag_s +{ + u32 uctag : 18; + u32 reserved0 : 14; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_qmb_command_uctag_u +{ + struct ipa_hwio_def_ipa_uc_qmb_command_uctag_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_QMB_COMPLETED_FIFO_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_qmb_completed_fifo_n_s +{ + u32 uctag : 18; + u32 fifo_size : 4; + u32 fifo_cnt : 4; + u32 error : 1; + u32 reserved0 : 3; + u32 empty : 1; + u32 full : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_qmb_completed_fifo_n_u +{ + struct ipa_hwio_def_ipa_uc_qmb_completed_fifo_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_QMB_COMPLETED_FIFO_PEEK_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_qmb_completed_fifo_peek_n_s +{ + u32 uctag : 18; + u32 fifo_size : 4; + u32 fifo_cnt : 4; + u32 error : 1; + u32 reserved0 : 3; + u32 empty : 1; + u32 full : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_qmb_completed_fifo_peek_n_u +{ + struct ipa_hwio_def_ipa_uc_qmb_completed_fifo_peek_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_QMB_CMD_FIFO_STATUS_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_qmb_cmd_fifo_status_n_s +{ + u32 fifo_size : 4; + u32 fifo_cnt : 4; + u32 reserved0 : 8; + u32 empty : 1; + u32 full : 1; + u32 reserved1 : 14; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_qmb_cmd_fifo_status_n_u +{ + struct ipa_hwio_def_ipa_uc_qmb_cmd_fifo_status_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_QMB_SYNC_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_qmb_sync_status_s +{ + u32 error_queue_0 : 1; + u32 reserved0 : 15; + u32 error_queue_1 : 1; + u32 reserved1 : 15; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_qmb_sync_status_u +{ + struct ipa_hwio_def_ipa_uc_qmb_sync_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_QMB_BUS_ATTRIB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_qmb_bus_attrib_s +{ + u32 memtype : 3; + u32 reserved0 : 1; + u32 noallocate : 1; + u32 reserved1 : 3; + u32 innershared : 1; + u32 reserved2 : 3; + u32 shared : 1; + u32 reserved3 : 19; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_qmb_bus_attrib_u +{ + struct ipa_hwio_def_ipa_uc_qmb_bus_attrib_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_QMB_OUTSTANDING_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_qmb_outstanding_cfg_s +{ + u32 max_ot_overall : 8; + u32 max_ot_rd : 8; + u32 max_ot_wr : 8; + u32 reserved0 : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_qmb_outstanding_cfg_u +{ + struct ipa_hwio_def_ipa_uc_qmb_outstanding_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_QMB_OUTSTANDING_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_qmb_outstanding_status_s +{ + u32 current_ot_overall : 8; + u32 current_ot_rd : 8; + u32 current_ot_wr : 8; + u32 reserved0 : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_qmb_outstanding_status_u +{ + struct ipa_hwio_def_ipa_uc_qmb_outstanding_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_QMB_COMP_FIFO_INT_EN +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_qmb_comp_fifo_int_en_s +{ + u32 comp_fifo_0_not_empty : 1; + u32 comp_fifo_0_full : 1; + u32 comp_fifo_0_ioc_cmd : 1; + u32 reserved0 : 13; + u32 comp_fifo_1_not_empty : 1; + u32 comp_fifo_1_full : 1; + u32 comp_fifo_1_ioc_cmd : 1; + u32 reserved1 : 13; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_qmb_comp_fifo_int_en_u +{ + struct ipa_hwio_def_ipa_uc_qmb_comp_fifo_int_en_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_QMB_COMP_FIFO_INT_CLR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_qmb_comp_fifo_int_clr_s +{ + u32 comp_fifo_0_not_empty : 1; + u32 comp_fifo_0_full : 1; + u32 comp_fifo_0_ioc_cmd : 1; + u32 reserved0 : 13; + u32 comp_fifo_1_not_empty : 1; + u32 comp_fifo_1_full : 1; + u32 comp_fifo_1_ioc_cmd : 1; + u32 reserved1 : 13; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_qmb_comp_fifo_int_clr_u +{ + struct ipa_hwio_def_ipa_uc_qmb_comp_fifo_int_clr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_QMB_COMP_FIFO_INT_STTS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_qmb_comp_fifo_int_stts_s +{ + u32 comp_fifo_0_not_empty : 1; + u32 comp_fifo_0_full : 1; + u32 comp_fifo_0_ioc_cmd : 1; + u32 reserved0 : 13; + u32 comp_fifo_1_not_empty : 1; + u32 comp_fifo_1_full : 1; + u32 comp_fifo_1_ioc_cmd : 1; + u32 reserved1 : 13; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_qmb_comp_fifo_int_stts_u +{ + struct ipa_hwio_def_ipa_uc_qmb_comp_fifo_int_stts_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_QMB_SYNC_COMPLETE_INT_EN +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_qmb_sync_complete_int_en_s +{ + u32 sync_completed_0 : 1; + u32 sync_completed_1 : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_qmb_sync_complete_int_en_u +{ + struct ipa_hwio_def_ipa_uc_qmb_sync_complete_int_en_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_QMB_SYNC_COMPLETE_INT_CLR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_qmb_sync_complete_int_clr_s +{ + u32 sync_completed_0 : 1; + u32 sync_completed_1 : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_qmb_sync_complete_int_clr_u +{ + struct ipa_hwio_def_ipa_uc_qmb_sync_complete_int_clr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_QMB_SYNC_COMPLETE_INT_STTS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_qmb_sync_complete_int_stts_s +{ + u32 sync_completed_0 : 1; + u32 sync_completed_1 : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_qmb_sync_complete_int_stts_u +{ + struct ipa_hwio_def_ipa_uc_qmb_sync_complete_int_stts_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_MBOX_INT_STTS_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_mbox_int_stts_n_s +{ + u32 irq_status : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_mbox_int_stts_n_u +{ + struct ipa_hwio_def_ipa_uc_mbox_int_stts_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_MBOX_INT_EN_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_mbox_int_en_n_s +{ + u32 irq_en : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_mbox_int_en_n_u +{ + struct ipa_hwio_def_ipa_uc_mbox_int_en_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_MBOX_INT_CLR_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_mbox_int_clr_n_s +{ + u32 irq_clr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_mbox_int_clr_n_u +{ + struct ipa_hwio_def_ipa_uc_mbox_int_clr_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_IPA_INT_STTS_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_ipa_int_stts_n_s +{ + u32 irq_status : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_ipa_int_stts_n_u +{ + struct ipa_hwio_def_ipa_uc_ipa_int_stts_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_IPA_INT_EN_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_ipa_int_en_n_s +{ + u32 irq_en : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_ipa_int_en_n_u +{ + struct ipa_hwio_def_ipa_uc_ipa_int_en_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_IPA_INT_CLR_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_ipa_int_clr_n_s +{ + u32 irq_clr : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_ipa_int_clr_n_u +{ + struct ipa_hwio_def_ipa_uc_ipa_int_clr_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_HWEV_INT_STTS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_hwev_int_stts_s +{ + u32 irq_status : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_hwev_int_stts_u +{ + struct ipa_hwio_def_ipa_uc_hwev_int_stts_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_HWEV_INT_EN +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_hwev_int_en_s +{ + u32 irq_en : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_hwev_int_en_u +{ + struct ipa_hwio_def_ipa_uc_hwev_int_en_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_HWEV_INT_CLR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_hwev_int_clr_s +{ + u32 irq_clr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_hwev_int_clr_u +{ + struct ipa_hwio_def_ipa_uc_hwev_int_clr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_SWEV_INT_STTS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_swev_int_stts_s +{ + u32 irq_status : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_swev_int_stts_u +{ + struct ipa_hwio_def_ipa_uc_swev_int_stts_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_SWEV_INT_EN +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_swev_int_en_s +{ + u32 irq_en : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_swev_int_en_u +{ + struct ipa_hwio_def_ipa_uc_swev_int_en_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_SWEV_INT_CLR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_swev_int_clr_s +{ + u32 irq_clr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_swev_int_clr_u +{ + struct ipa_hwio_def_ipa_uc_swev_int_clr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_VUIC_INT_STTS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_vuic_int_stts_s +{ + u32 irq_status : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_vuic_int_stts_u +{ + struct ipa_hwio_def_ipa_uc_vuic_int_stts_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_VUIC_INT_CLR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_vuic_int_clr_s +{ + u32 irq_clr : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_vuic_int_clr_u +{ + struct ipa_hwio_def_ipa_uc_vuic_int_clr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_TIMER_CTRL_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_timer_ctrl_n_s +{ + u32 count : 16; + u32 event_sel : 7; + u32 reserved0 : 1; + u32 retrig : 1; + u32 reserved1 : 5; + u32 gran_sel : 2; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_timer_ctrl_n_u +{ + struct ipa_hwio_def_ipa_uc_timer_ctrl_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_TIMER_STATUS_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_timer_status_n_s +{ + u32 count : 16; + u32 reserved0 : 8; + u32 active : 1; + u32 reserved1 : 7; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_timer_status_n_u +{ + struct ipa_hwio_def_ipa_uc_timer_status_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_EVENTS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_events_s +{ + u32 events : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_events_u +{ + struct ipa_hwio_def_ipa_uc_events_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_VUIC_BUS_ADDR_TRANSLATE_EN +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_vuic_bus_addr_translate_en_s +{ + u32 qmb_addr_translate : 1; + u32 direct_addr_translate : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_vuic_bus_addr_translate_en_u +{ + struct ipa_hwio_def_ipa_uc_vuic_bus_addr_translate_en_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_SYS_ADDR_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_sys_addr_msb_s +{ + u32 sys_addr_msb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_sys_addr_msb_u +{ + struct ipa_hwio_def_ipa_uc_sys_addr_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_PC_RESTORE_WR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_pc_restore_wr_s +{ + u32 set_ipa_pc_ack : 1; + u32 clear_ipa_pc_ack : 1; + u32 set_ipa_restore_ack : 1; + u32 clear_ipa_restore_ack : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_pc_restore_wr_u +{ + struct ipa_hwio_def_ipa_uc_pc_restore_wr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_PC_RESTORE_RD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_pc_restore_rd_s +{ + u32 ipa_pc_req : 1; + u32 ipa_pc_ack : 1; + u32 ipa_restore_req : 1; + u32 ipa_restore_ack : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_pc_restore_rd_u +{ + struct ipa_hwio_def_ipa_uc_pc_restore_rd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_CNT_GLOBAL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_cnt_global_s +{ + u32 count_en : 1; + u32 count_cgc_open : 1; + u32 reserved0 : 29; + u32 clear_all : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_cnt_global_u +{ + struct ipa_hwio_def_ipa_uc_cnt_global_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_CNT_CTL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_cnt_ctl_s +{ + u32 cycle_cnt_en : 1; + u32 reserved0 : 1; + u32 cycle_cnt_clr : 1; + u32 reserved1 : 1; + u32 idle_cnt_en : 1; + u32 reserved2 : 1; + u32 idle_cnt_clr : 1; + u32 reserved3 : 1; + u32 inst_cnt_en : 1; + u32 inst_clr_after_rd : 1; + u32 inst_cnt_clr : 1; + u32 reserved4 : 1; + u32 vuic_rd_cnt_en : 1; + u32 vuic_wr_cnt_en : 1; + u32 vuic_clr_after_rd : 1; + u32 vuic_cnt_clr : 1; + u32 dram_rd_cnt_en : 1; + u32 dram_wr_cnt_en : 1; + u32 dram_clr_after_rd : 1; + u32 dram_cnt_clr : 1; + u32 reserved5 : 12; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_cnt_ctl_u +{ + struct ipa_hwio_def_ipa_uc_cnt_ctl_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_CNT_CLK_CYCLE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_cnt_clk_cycle_s +{ + u32 counter : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_cnt_clk_cycle_u +{ + struct ipa_hwio_def_ipa_uc_cnt_clk_cycle_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_CNT_CLK_CYCLE_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_cnt_clk_cycle_msb_s +{ + u32 counter : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_cnt_clk_cycle_msb_u +{ + struct ipa_hwio_def_ipa_uc_cnt_clk_cycle_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_CNT_IDLE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_cnt_idle_s +{ + u32 counter : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_cnt_idle_u +{ + struct ipa_hwio_def_ipa_uc_cnt_idle_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_CNT_IDLE_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_cnt_idle_msb_s +{ + u32 counter : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_cnt_idle_msb_u +{ + struct ipa_hwio_def_ipa_uc_cnt_idle_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_CNT_INST +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_cnt_inst_s +{ + u32 counter : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_cnt_inst_u +{ + struct ipa_hwio_def_ipa_uc_cnt_inst_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_CNT_DRAM +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_cnt_dram_s +{ + u32 counter : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_cnt_dram_u +{ + struct ipa_hwio_def_ipa_uc_cnt_dram_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_CNT_VUIC +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_cnt_vuic_s +{ + u32 counter : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_cnt_vuic_u +{ + struct ipa_hwio_def_ipa_uc_cnt_vuic_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_SPARE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_spare_s +{ + u32 spare : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_spare_u +{ + struct ipa_hwio_def_ipa_uc_spare_s def; + u32 value; +}; + +/*---------------------------------------------------------------------------- + * MODULE: IPA_UC_IPA_UC_MBOX + *--------------------------------------------------------------------------*/ + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_MAILBOX_m_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_mailbox_m_n_s +{ + u32 data : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_mailbox_m_n_u +{ + struct ipa_hwio_def_ipa_uc_mailbox_m_n_s def; + u32 value; +}; + +/*---------------------------------------------------------------------------- + * MODULE: IPA_RAM + *--------------------------------------------------------------------------*/ + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_SW_AREA_RAM_DIRECT_ACCESS_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_sw_area_ram_direct_access_n_s +{ + u32 data_word : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_sw_area_ram_direct_access_n_u +{ + struct ipa_hwio_def_ipa_sw_area_ram_direct_access_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_HW_AREA_RAM_DIRECT_ACCESS_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_hw_area_ram_direct_access_n_s +{ + u32 data_word : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_hw_area_ram_direct_access_n_u +{ + struct ipa_hwio_def_ipa_hw_area_ram_direct_access_n_s def; + u32 value; +}; + +/*---------------------------------------------------------------------------- + * MODULE: IPA_EE + *--------------------------------------------------------------------------*/ + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_IRQ_STTS_EE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_irq_stts_ee_n_s +{ + u32 bad_snoc_access_irq : 1; + u32 reserved0 : 1; + u32 uc_irq_0 : 1; + u32 uc_irq_1 : 1; + u32 uc_irq_2 : 1; + u32 uc_irq_3 : 1; + u32 uc_in_q_not_empty_irq : 1; + u32 uc_rx_cmd_q_not_full_irq : 1; + u32 proc_to_uc_ack_q_not_empty_irq : 1; + u32 rx_err_irq : 1; + u32 deaggr_err_irq : 1; + u32 tx_err_irq : 1; + u32 step_mode_irq : 1; + u32 proc_err_irq : 1; + u32 tx_suspend_irq : 1; + u32 tx_holb_drop_irq : 1; + u32 bam_gsi_idle_irq : 1; + u32 pipe_yellow_marker_below_irq : 1; + u32 pipe_red_marker_below_irq : 1; + u32 pipe_yellow_marker_above_irq : 1; + u32 pipe_red_marker_above_irq : 1; + u32 ucp_irq : 1; + u32 reserved1 : 1; + u32 gsi_ee_irq : 1; + u32 gsi_ipa_if_tlv_rcvd_irq : 1; + u32 gsi_uc_irq : 1; + u32 tlv_len_min_dsm_irq : 1; + u32 drbip_pkt_exceed_max_size_irq : 1; + u32 drbip_data_sctr_cfg_error_irq : 1; + u32 drbip_imm_cmd_no_flsh_hzrd_irq : 1; + u32 reserved2 : 2; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_irq_stts_ee_n_u +{ + struct ipa_hwio_def_ipa_irq_stts_ee_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_IRQ_EN_EE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_irq_en_ee_n_s +{ + u32 bad_snoc_access_irq_en : 1; + u32 reserved0 : 1; + u32 uc_irq_0_irq_en : 1; + u32 uc_irq_1_irq_en : 1; + u32 uc_irq_2_irq_en : 1; + u32 uc_irq_3_irq_en : 1; + u32 uc_in_q_not_empty_irq_en : 1; + u32 uc_rx_cmd_q_not_full_irq_en : 1; + u32 proc_to_uc_ack_q_not_empty_irq_en : 1; + u32 rx_err_irq_en : 1; + u32 deaggr_err_irq_en : 1; + u32 tx_err_irq_en : 1; + u32 step_mode_irq_en : 1; + u32 proc_err_irq_en : 1; + u32 tx_suspend_irq_en : 1; + u32 tx_holb_drop_irq_en : 1; + u32 bam_gsi_idle_irq_en : 1; + u32 pipe_yellow_marker_below_irq_en : 1; + u32 pipe_red_marker_below_irq_en : 1; + u32 pipe_yellow_marker_above_irq_en : 1; + u32 pipe_red_marker_above_irq_en : 1; + u32 ucp_irq_en : 1; + u32 reserved1 : 1; + u32 gsi_ee_irq_en : 1; + u32 gsi_ipa_if_tlv_rcvd_irq_en : 1; + u32 gsi_uc_irq_en : 1; + u32 tlv_len_min_dsm_irq_en : 1; + u32 drbip_pkt_exceed_max_size_irq_en : 1; + u32 drbip_data_sctr_cfg_error_irq_en : 1; + u32 drbip_imm_cmd_no_flsh_hzrd_irq_en : 1; + u32 reserved2 : 2; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_irq_en_ee_n_u +{ + struct ipa_hwio_def_ipa_irq_en_ee_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_IRQ_CLR_EE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_irq_clr_ee_n_s +{ + u32 bad_snoc_access_irq_clr : 1; + u32 reserved0 : 1; + u32 uc_irq_0_clr : 1; + u32 uc_irq_1_clr : 1; + u32 uc_irq_2_clr : 1; + u32 uc_irq_3_clr : 1; + u32 uc_in_q_not_empty_irq_clr : 1; + u32 uc_rx_cmd_q_not_full_irq_clr : 1; + u32 proc_to_uc_ack_q_not_empty_irq_clr : 1; + u32 rx_err_irq_clr : 1; + u32 deaggr_err_irq_clr : 1; + u32 tx_err_irq_clr : 1; + u32 step_mode_irq_clr : 1; + u32 proc_err_irq_clr : 1; + u32 tx_suspend_irq_clr : 1; + u32 tx_holb_drop_irq_clr : 1; + u32 bam_gsi_idle_irq_clr : 1; + u32 pipe_yellow_marker_below_irq_clr : 1; + u32 pipe_red_marker_below_irq_clr : 1; + u32 pipe_yellow_marker_above_irq_clr : 1; + u32 pipe_red_marker_above_irq_clr : 1; + u32 ucp_irq_clr : 1; + u32 reserved1 : 1; + u32 gsi_ee_irq_clr : 1; + u32 gsi_ipa_if_tlv_rcvd_irq_clr : 1; + u32 gsi_uc_irq_clr : 1; + u32 tlv_len_min_dsm_irq_clr : 1; + u32 drbip_pkt_exceed_max_size_irq_clr : 1; + u32 drbip_data_sctr_cfg_error_irq_clr : 1; + u32 drbip_imm_cmd_no_flsh_hzrd_irq_clr : 1; + u32 reserved2 : 2; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_irq_clr_ee_n_u +{ + struct ipa_hwio_def_ipa_irq_clr_ee_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_SNOC_FEC_EE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_snoc_fec_ee_n_s +{ + u32 client : 8; + u32 noc_port : 1; + u32 noc_master : 3; + u32 tid : 5; + u32 reserved0 : 11; + u32 valid : 1; + u32 clear : 1; + u32 reserved1 : 1; + u32 direction : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_snoc_fec_ee_n_u +{ + struct ipa_hwio_def_ipa_snoc_fec_ee_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_IRQ_EE_UC_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_irq_ee_uc_n_s +{ + u32 intr : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_irq_ee_uc_n_u +{ + struct ipa_hwio_def_ipa_irq_ee_uc_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_FEC_ADDR_EE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_fec_addr_ee_n_s +{ + u32 addr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_fec_addr_ee_n_u +{ + struct ipa_hwio_def_ipa_fec_addr_ee_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_FEC_ADDR_MSB_EE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_fec_addr_msb_ee_n_s +{ + u32 addr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_fec_addr_msb_ee_n_u +{ + struct ipa_hwio_def_ipa_fec_addr_msb_ee_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_FEC_ATTR_EE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_fec_attr_ee_n_s +{ + u32 opcode : 6; + u32 error_info : 26; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_fec_attr_ee_n_u +{ + struct ipa_hwio_def_ipa_fec_attr_ee_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DRBIP_FEC_INFO_EE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_drbip_fec_info_ee_n_s +{ + u32 error_code : 4; + u32 src_grp : 4; + u32 src_pipe : 8; + u32 required_data_sectors : 8; + u32 avail_data_sectors : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_drbip_fec_info_ee_n_u +{ + struct ipa_hwio_def_ipa_drbip_fec_info_ee_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DRBIP_FEC_INFO_EXT_EE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_drbip_fec_info_ext_ee_n_s +{ + u32 size : 16; + u32 opocode : 8; + u32 reserved0 : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_drbip_fec_info_ext_ee_n_u +{ + struct ipa_hwio_def_ipa_drbip_fec_info_ext_ee_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_SUSPEND_IRQ_INFO_EE_n_REG_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_suspend_irq_info_ee_n_reg_k_s +{ + u32 endpoints : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_suspend_irq_info_ee_n_reg_k_u +{ + struct ipa_hwio_def_ipa_suspend_irq_info_ee_n_reg_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_SUSPEND_IRQ_EN_EE_n_REG_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_suspend_irq_en_ee_n_reg_k_s +{ + u32 endpoints : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_suspend_irq_en_ee_n_reg_k_u +{ + struct ipa_hwio_def_ipa_suspend_irq_en_ee_n_reg_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_SUSPEND_IRQ_CLR_EE_n_REG_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_suspend_irq_clr_ee_n_reg_k_s +{ + u32 endpoints : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_suspend_irq_clr_ee_n_reg_k_u +{ + struct ipa_hwio_def_ipa_suspend_irq_clr_ee_n_reg_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_HOLB_DROP_IRQ_INFO_EE_n_REG_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_holb_drop_irq_info_ee_n_reg_k_s +{ + u32 endpoints : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_holb_drop_irq_info_ee_n_reg_k_u +{ + struct ipa_hwio_def_ipa_holb_drop_irq_info_ee_n_reg_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_HOLB_DROP_IRQ_EN_EE_n_REG_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_holb_drop_irq_en_ee_n_reg_k_s +{ + u32 endpoints : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_holb_drop_irq_en_ee_n_reg_k_u +{ + struct ipa_hwio_def_ipa_holb_drop_irq_en_ee_n_reg_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_HOLB_DROP_IRQ_CLR_EE_n_REG_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_holb_drop_irq_clr_ee_n_reg_k_s +{ + u32 endpoints : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_holb_drop_irq_clr_ee_n_reg_k_u +{ + struct ipa_hwio_def_ipa_holb_drop_irq_clr_ee_n_reg_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MODEM_BEARER_INIT_VALUES_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_modem_bearer_init_values_0_s +{ + u32 modem_bearer_init_l2_hdr_size : 8; + u32 reserved0 : 4; + u32 modem_bearer_init_cphr_algorithm : 4; + u32 modem_bearer_init_cphr_key_indx : 5; + u32 reserved1 : 3; + u32 modem_bearer_init_bearer : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_modem_bearer_init_values_0_u +{ + struct ipa_hwio_def_ipa_modem_bearer_init_values_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MODEM_BEARER_INIT_VALUES_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_modem_bearer_init_values_1_s +{ + u32 modem_bearer_init_cphr_ofst_keystrm : 16; + u32 modem_bearer_init_cphr_ofst_start : 14; + u32 modem_bearer_init_direction : 1; + u32 modem_bearer_init_bearer_sel : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_modem_bearer_init_values_1_u +{ + struct ipa_hwio_def_ipa_modem_bearer_init_values_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MODEM_BEARER_INIT_VALUES_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_modem_bearer_init_values_2_s +{ + u32 modem_bearer_init_ip_algorithm : 4; + u32 modem_bearer_init_ip_key_indx : 5; + u32 reserved0 : 3; + u32 modem_bearer_init_ip_maci_size : 2; + u32 reserved1 : 18; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_modem_bearer_init_values_2_u +{ + struct ipa_hwio_def_ipa_modem_bearer_init_values_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MODEM_BEARER_CONFIG_VALUES_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_modem_bearer_config_values_0_s +{ + u32 modem_bearer_config_count_f : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_modem_bearer_config_values_0_u +{ + struct ipa_hwio_def_ipa_modem_bearer_config_values_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MODEM_BEARER_CONFIG_VALUES_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_modem_bearer_config_values_1_s +{ + u32 modem_bearer_config_size_f : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_modem_bearer_config_values_1_u +{ + struct ipa_hwio_def_ipa_modem_bearer_config_values_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_SECURED_PIPES_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_secured_pipes_n_s +{ + u32 endpoints : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_secured_pipes_n_u +{ + struct ipa_hwio_def_ipa_secured_pipes_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MODEM_BEARER_INIT_VALUES_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_modem_bearer_init_values_cfg_s +{ + u32 bearer_context_index_sel : 2; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_modem_bearer_init_values_cfg_u +{ + struct ipa_hwio_def_ipa_modem_bearer_init_values_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_REGS_INSIDE_IPA__CONTROL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_regs_inside_ipa__control_s +{ + u32 uc_enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_regs_inside_ipa__control_u +{ + struct ipa_hwio_def_ipa_uc_regs_inside_ipa__control_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_REGS_INSIDE_IPA__NMI +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_regs_inside_ipa__nmi_s +{ + u32 pulse : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_regs_inside_ipa__nmi_u +{ + struct ipa_hwio_def_ipa_uc_regs_inside_ipa__nmi_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DRBIP_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_drbip_cfg_s +{ + u32 operation_mode : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_drbip_cfg_u +{ + struct ipa_hwio_def_ipa_drbip_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_SET_UC_IRQ_EE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_set_uc_irq_ee_n_s +{ + u32 set_uc_irq_0 : 1; + u32 set_uc_irq_1 : 1; + u32 set_uc_irq_2 : 1; + u32 set_uc_irq_3 : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_set_uc_irq_ee_n_u +{ + struct ipa_hwio_def_ipa_set_uc_irq_ee_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_SET_UC_IRQ_ALL_EES +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_set_uc_irq_all_ees_s +{ + u32 set_uc_irq_0 : 1; + u32 set_uc_irq_1 : 1; + u32 set_uc_irq_2 : 1; + u32 set_uc_irq_3 : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_set_uc_irq_all_ees_u +{ + struct ipa_hwio_def_ipa_set_uc_irq_all_ees_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UCP_RESUME +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ucp_resume_s +{ + u32 reserved0 : 1; + u32 next_round_en : 1; + u32 dest_pipe_override : 1; + u32 reserved1 : 1; + u32 ip_checksum_fix_en : 1; + u32 tport_checksum_fix_en : 1; + u32 reserved2 : 2; + u32 dest_pipe_value : 8; + u32 exception : 1; + u32 reserved3 : 2; + u32 next_pkt_parser_dis : 1; + u32 metadata_override : 1; + u32 reserved4 : 11; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ucp_resume_u +{ + struct ipa_hwio_def_ipa_ucp_resume_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UCP_RESUME_METADATA +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ucp_resume_metadata_s +{ + u32 metadata : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ucp_resume_metadata_u +{ + struct ipa_hwio_def_ipa_ucp_resume_metadata_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_PROC_UCP_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_proc_ucp_cfg_s +{ + u32 ipa_ucp_irq_sw_events_uc_mux_en : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_proc_ucp_cfg_u +{ + struct ipa_hwio_def_ipa_proc_ucp_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_PKT_PROCESS_BASE_ADDR_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_pkt_process_base_addr_0_s +{ + u32 ipa_uc_pkt_process_context_base : 18; + u32 reserved0 : 14; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_pkt_process_base_addr_0_u +{ + struct ipa_hwio_def_ipa_uc_pkt_process_base_addr_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_PKT_PROCESS_BASE_ADDR_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_pkt_process_base_addr_1_s +{ + u32 ipa_uc_pkt_process_pkt_base : 18; + u32 reserved0 : 14; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_pkt_process_base_addr_1_u +{ + struct ipa_hwio_def_ipa_uc_pkt_process_base_addr_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_PKT_PROCESS_BASE_ADDR_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_pkt_process_base_addr_2_s +{ + u32 ipa_uc_pkt_process_hdr_base : 18; + u32 reserved0 : 14; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_pkt_process_base_addr_2_u +{ + struct ipa_hwio_def_ipa_uc_pkt_process_base_addr_2_s def; + u32 value; +}; + +/*---------------------------------------------------------------------------- + * MODULE: IPA_DEBUG + *--------------------------------------------------------------------------*/ + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rsrc_mngr_sw_access_alloc_cfg_s +{ + u32 alloc_rsrc_type : 3; + u32 reserved0 : 1; + u32 alloc_rsrc_grp : 3; + u32 reserved1 : 1; + u32 alloc_rsrc_id_curr : 6; + u32 reserved2 : 2; + u32 alloc_list_id : 6; + u32 reserved3 : 2; + u32 alloc_hold : 1; + u32 alloc_reserved : 1; + u32 alloc_list_type : 2; + u32 reserved4 : 4; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rsrc_mngr_sw_access_alloc_cfg_u +{ + struct ipa_hwio_def_ipa_rsrc_mngr_sw_access_alloc_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RSRC_MNGR_SW_ACCESS_SRCH_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rsrc_mngr_sw_access_srch_cfg_s +{ + u32 srch_rsrc_type : 3; + u32 reserved0 : 1; + u32 srch_rsrc_cnt : 7; + u32 reserved1 : 1; + u32 srch_list_id : 6; + u32 srch_list_type : 2; + u32 reserved2 : 12; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rsrc_mngr_sw_access_srch_cfg_u +{ + struct ipa_hwio_def_ipa_rsrc_mngr_sw_access_srch_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RSRC_MNGR_SW_ACCESS_REL_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rsrc_mngr_sw_access_rel_cfg_s +{ + u32 rel_rsrc_type : 3; + u32 reserved0 : 1; + u32 rel_rsrc_grp : 3; + u32 reserved1 : 1; + u32 rel_rsrc_id : 6; + u32 reserved2 : 2; + u32 rel_list_id : 6; + u32 rel_list_type : 2; + u32 reserved3 : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rsrc_mngr_sw_access_rel_cfg_u +{ + struct ipa_hwio_def_ipa_rsrc_mngr_sw_access_rel_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RSRC_MNGR_SW_ACCESS_RSRV_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rsrc_mngr_sw_access_rsrv_cfg_s +{ + u32 rsrv_rsrc_type : 3; + u32 reserved0 : 1; + u32 rsrv_rsrc_grp : 3; + u32 reserved1 : 1; + u32 rsrv_rsrc_amount : 6; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rsrc_mngr_sw_access_rsrv_cfg_u +{ + struct ipa_hwio_def_ipa_rsrc_mngr_sw_access_rsrv_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RSRC_MNGR_SW_ACCESS_CMD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rsrc_mngr_sw_access_cmd_s +{ + u32 alloc_valid : 1; + u32 srch_valid : 1; + u32 rel_valid : 1; + u32 rsrv_valid : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rsrc_mngr_sw_access_cmd_u +{ + struct ipa_hwio_def_ipa_rsrc_mngr_sw_access_cmd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RSRC_MNGR_SW_ACCESS_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rsrc_mngr_sw_access_status_s +{ + u32 alloc_ready : 1; + u32 srch_ready : 1; + u32 rel_ready : 1; + u32 rsrv_ready : 1; + u32 alloc_rsrc_id_next : 6; + u32 reserved0 : 2; + u32 srch_rsrc_id_next : 6; + u32 reserved1 : 14; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rsrc_mngr_sw_access_status_u +{ + struct ipa_hwio_def_ipa_rsrc_mngr_sw_access_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RSRC_MNGR_DB_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rsrc_mngr_db_cfg_s +{ + u32 rsrc_grp_sel : 3; + u32 reserved0 : 1; + u32 rsrc_type_sel : 3; + u32 reserved1 : 1; + u32 rsrc_id_sel : 6; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rsrc_mngr_db_cfg_u +{ + struct ipa_hwio_def_ipa_rsrc_mngr_db_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RSRC_MNGR_DB_RSRC_READ +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rsrc_mngr_db_rsrc_read_s +{ + u32 rsrc_occupied : 1; + u32 rsrc_next_valid : 1; + u32 reserved0 : 2; + u32 rsrc_next_index : 6; + u32 reserved1 : 22; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rsrc_mngr_db_rsrc_read_u +{ + struct ipa_hwio_def_ipa_rsrc_mngr_db_rsrc_read_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RSRC_MNGR_DB_LIST_READ +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rsrc_mngr_db_list_read_s +{ + u32 rsrc_list_valid : 1; + u32 rsrc_list_hold : 1; + u32 reserved0 : 2; + u32 rsrc_list_head_rsrc : 6; + u32 reserved1 : 2; + u32 rsrc_list_head_cnt : 7; + u32 reserved2 : 1; + u32 rsrc_list_entry_cnt : 7; + u32 reserved3 : 5; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rsrc_mngr_db_list_read_u +{ + struct ipa_hwio_def_ipa_rsrc_mngr_db_list_read_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RSRC_MNGR_CONTEXTS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rsrc_mngr_contexts_s +{ + u32 rsrc_occupied_contexts_bitmap : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rsrc_mngr_contexts_u +{ + struct ipa_hwio_def_ipa_rsrc_mngr_contexts_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_BRESP_DB_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_bresp_db_cfg_s +{ + u32 sel_entry : 3; + u32 sel_pipe : 8; + u32 reserved0 : 21; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_bresp_db_cfg_u +{ + struct ipa_hwio_def_ipa_bresp_db_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_BRESP_DB_DATA +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_bresp_db_data_s +{ + u32 data : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_bresp_db_data_u +{ + struct ipa_hwio_def_ipa_bresp_db_data_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_SNOC_MONITORING_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_snoc_monitoring_cfg_s +{ + u32 enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_snoc_monitoring_cfg_u +{ + struct ipa_hwio_def_ipa_snoc_monitoring_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_PCIE_SNOC_MONITOR_CNT +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_pcie_snoc_monitor_cnt_s +{ + u32 ar_value : 5; + u32 reserved0 : 1; + u32 aw_value : 5; + u32 reserved1 : 1; + u32 r_value : 5; + u32 reserved2 : 1; + u32 w_value : 5; + u32 reserved3 : 1; + u32 b_value : 5; + u32 reserved4 : 3; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_pcie_snoc_monitor_cnt_u +{ + struct ipa_hwio_def_ipa_pcie_snoc_monitor_cnt_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DDR_SNOC_MONITOR_CNT +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ddr_snoc_monitor_cnt_s +{ + u32 ar_value : 5; + u32 reserved0 : 1; + u32 aw_value : 5; + u32 reserved1 : 1; + u32 r_value : 5; + u32 reserved2 : 1; + u32 w_value : 5; + u32 reserved3 : 1; + u32 b_value : 5; + u32 reserved4 : 3; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ddr_snoc_monitor_cnt_u +{ + struct ipa_hwio_def_ipa_ddr_snoc_monitor_cnt_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_SNOC_MONITOR_CNT +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_snoc_monitor_cnt_s +{ + u32 ar_value : 5; + u32 reserved0 : 1; + u32 aw_value : 5; + u32 reserved1 : 1; + u32 r_value : 5; + u32 reserved2 : 1; + u32 w_value : 5; + u32 reserved3 : 1; + u32 b_value : 5; + u32 reserved4 : 3; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_snoc_monitor_cnt_u +{ + struct ipa_hwio_def_ipa_gsi_snoc_monitor_cnt_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DEBUG_DATA +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_debug_data_s +{ + u32 debug_data : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_debug_data_u +{ + struct ipa_hwio_def_ipa_debug_data_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_TESTBUS_SEL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_testbus_sel_s +{ + u32 testbus_en : 1; + u32 reserved0 : 3; + u32 external_block_select : 8; + u32 internal_block_select : 8; + u32 reserved1 : 12; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_testbus_sel_u +{ + struct ipa_hwio_def_ipa_testbus_sel_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STEP_MODE_BREAKPOINTS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_step_mode_breakpoints_s +{ + u32 hw_en : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_step_mode_breakpoints_u +{ + struct ipa_hwio_def_ipa_step_mode_breakpoints_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STEP_MODE_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_step_mode_status_s +{ + u32 hw_en : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_step_mode_status_u +{ + struct ipa_hwio_def_ipa_step_mode_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STEP_MODE_GO +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_step_mode_go_s +{ + u32 hw_en : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_step_mode_go_u +{ + struct ipa_hwio_def_ipa_step_mode_go_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_HW_EVENTS_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_hw_events_cfg_s +{ + u32 hw_events_select : 4; + u32 rx_events_pipe_select : 8; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_hw_events_cfg_u +{ + struct ipa_hwio_def_ipa_hw_events_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_LOG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_log_s +{ + u32 reserved0 : 1; + u32 log_en : 1; + u32 reserved1 : 2; + u32 log_pipe : 8; + u32 log_length : 8; + u32 log_reduction_en : 1; + u32 log_dpl_l2_remove_en : 1; + u32 reserved2 : 10; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_log_u +{ + struct ipa_hwio_def_ipa_log_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_LOG_BUF_HW_CMD_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_log_buf_hw_cmd_addr_s +{ + u32 start_addr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_log_buf_hw_cmd_addr_u +{ + struct ipa_hwio_def_ipa_log_buf_hw_cmd_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_LOG_BUF_HW_CMD_ADDR_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_log_buf_hw_cmd_addr_msb_s +{ + u32 start_addr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_log_buf_hw_cmd_addr_msb_u +{ + struct ipa_hwio_def_ipa_log_buf_hw_cmd_addr_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_LOG_BUF_HW_CMD_WRITE_PTR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_log_buf_hw_cmd_write_ptr_s +{ + u32 writr_addr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_log_buf_hw_cmd_write_ptr_u +{ + struct ipa_hwio_def_ipa_log_buf_hw_cmd_write_ptr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_LOG_BUF_HW_CMD_WRITE_PTR_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_log_buf_hw_cmd_write_ptr_msb_s +{ + u32 writr_addr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_log_buf_hw_cmd_write_ptr_msb_u +{ + struct ipa_hwio_def_ipa_log_buf_hw_cmd_write_ptr_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_LOG_BUF_HW_CMD_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_log_buf_hw_cmd_cfg_s +{ + u32 size : 16; + u32 enable : 1; + u32 skip_ddr_dma : 1; + u32 tpdm_enable : 1; + u32 reserved0 : 13; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_log_buf_hw_cmd_cfg_u +{ + struct ipa_hwio_def_ipa_log_buf_hw_cmd_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_LOG_BUF_HW_CMD_RAM_PTR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_log_buf_hw_cmd_ram_ptr_s +{ + u32 read_ptr : 14; + u32 reserved0 : 2; + u32 write_ptr : 14; + u32 full : 1; + u32 skip_ddr_wrap_happened : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_log_buf_hw_cmd_ram_ptr_u +{ + struct ipa_hwio_def_ipa_log_buf_hw_cmd_ram_ptr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_log_buf_hw_cmd_noc_master_sel_s +{ + u32 noc_port_sel : 1; + u32 qmb_rd_en : 1; + u32 qmb_wr_en : 1; + u32 gsi_rd_en : 1; + u32 gsi_wr_en : 1; + u32 uc_rd_en : 1; + u32 uc_wr_en : 1; + u32 qmb_resp_en : 1; + u32 gsi_resp_en : 1; + u32 uc_resp_en : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_log_buf_hw_cmd_noc_master_sel_u +{ + struct ipa_hwio_def_ipa_log_buf_hw_cmd_noc_master_sel_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STEP_MODE_HFETCHER_ADDR_LSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_step_mode_hfetcher_addr_lsb_s +{ + u32 addr_lsb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_step_mode_hfetcher_addr_lsb_u +{ + struct ipa_hwio_def_ipa_step_mode_hfetcher_addr_lsb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STEP_MODE_HFETCHER_ADDR_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_step_mode_hfetcher_addr_msb_s +{ + u32 addr_msb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_step_mode_hfetcher_addr_msb_u +{ + struct ipa_hwio_def_ipa_step_mode_hfetcher_addr_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STEP_MODE_HFETCHER_ADDR_RESULT +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_step_mode_hfetcher_addr_result_s +{ + u32 ctx_id_f : 4; + u32 src_id_f : 8; + u32 src_pipe_f : 8; + u32 opcode_f : 2; + u32 type_f : 1; + u32 reserved0 : 9; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_step_mode_hfetcher_addr_result_u +{ + struct ipa_hwio_def_ipa_step_mode_hfetcher_addr_result_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STEP_MODE_HSEQ_BREAKPOINT +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_step_mode_hseq_breakpoint_s +{ + u32 ctx_id_f : 4; + u32 src_id_f : 8; + u32 src_pipe_f : 8; + u32 opcode_f : 2; + u32 type_f : 1; + u32 acl_id_f : 6; + u32 reserved0 : 3; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_step_mode_hseq_breakpoint_u +{ + struct ipa_hwio_def_ipa_step_mode_hseq_breakpoint_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STEP_MODE_HSEQ_BREAKPOINT_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_step_mode_hseq_breakpoint_1_s +{ + u32 ctx_id_v : 1; + u32 src_id_v : 1; + u32 src_pipe_v : 1; + u32 opcode_v : 1; + u32 type_v : 1; + u32 acl_id_v : 1; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_step_mode_hseq_breakpoint_1_u +{ + struct ipa_hwio_def_ipa_step_mode_hseq_breakpoint_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STEP_MODE_HSEQ_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_step_mode_hseq_status_s +{ + u32 ctx_id_f : 4; + u32 src_id_f : 8; + u32 src_pipe_f : 8; + u32 opcode_f : 2; + u32 type_f : 1; + u32 acl_id_f : 6; + u32 reserved0 : 3; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_step_mode_hseq_status_u +{ + struct ipa_hwio_def_ipa_step_mode_hseq_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STEP_MODE_DSEQ_BREAKPOINT +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_step_mode_dseq_breakpoint_s +{ + u32 ctx_id_f : 4; + u32 src_id_f : 8; + u32 src_pipe_f : 8; + u32 opcode_f : 2; + u32 type_f : 1; + u32 acl_id_f : 6; + u32 reserved0 : 3; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_step_mode_dseq_breakpoint_u +{ + struct ipa_hwio_def_ipa_step_mode_dseq_breakpoint_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STEP_MODE_DSEQ_BREAKPOINT_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_step_mode_dseq_breakpoint_1_s +{ + u32 ctx_id_v : 1; + u32 src_id_v : 1; + u32 src_pipe_v : 1; + u32 opcode_v : 1; + u32 type_v : 1; + u32 acl_id_v : 1; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_step_mode_dseq_breakpoint_1_u +{ + struct ipa_hwio_def_ipa_step_mode_dseq_breakpoint_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STEP_MODE_DSEQ_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_step_mode_dseq_status_s +{ + u32 ctx_id_f : 4; + u32 src_id_f : 8; + u32 src_pipe_f : 8; + u32 opcode_f : 2; + u32 type_f : 1; + u32 acl_id_f : 6; + u32 reserved0 : 3; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_step_mode_dseq_status_u +{ + struct ipa_hwio_def_ipa_step_mode_dseq_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_ACKQ_CMD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_ackq_cmd_s +{ + u32 write_cmd : 1; + u32 pop_cmd : 1; + u32 release_rd_cmd : 1; + u32 release_wr_cmd : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_ackq_cmd_u +{ + struct ipa_hwio_def_ipa_rx_ackq_cmd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_ACKQ_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_ackq_cfg_s +{ + u32 block_rd_req : 1; + u32 block_wr : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_ackq_cfg_u +{ + struct ipa_hwio_def_ipa_rx_ackq_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_ACKQ_DATA_WR_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_ackq_data_wr_0_s +{ + u32 ack_value1 : 16; + u32 ack_value2 : 8; + u32 ack_value1_type : 1; + u32 reserved0 : 7; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_ackq_data_wr_0_u +{ + struct ipa_hwio_def_ipa_rx_ackq_data_wr_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_ACKQ_DATA_RD_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_ackq_data_rd_0_s +{ + u32 ack_value1 : 16; + u32 ack_value2 : 8; + u32 ack_value1_type : 1; + u32 reserved0 : 7; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_ackq_data_rd_0_u +{ + struct ipa_hwio_def_ipa_rx_ackq_data_rd_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_ACKQ_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_ackq_status_s +{ + u32 status : 1; + u32 ackq_empty : 1; + u32 ackq_full : 1; + u32 reserved0 : 1; + u32 ackq_count : 4; + u32 ackq_depth : 4; + u32 block_rd_ack : 1; + u32 reserved1 : 19; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_ackq_status_u +{ + struct ipa_hwio_def_ipa_rx_ackq_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_ACKQ_CMD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_ackq_cmd_s +{ + u32 write_cmd : 1; + u32 pop_cmd : 1; + u32 release_rd_cmd : 1; + u32 release_wr_cmd : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_ackq_cmd_u +{ + struct ipa_hwio_def_ipa_uc_ackq_cmd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_ACKQ_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_ackq_cfg_s +{ + u32 block_rd : 1; + u32 block_wr : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_ackq_cfg_u +{ + struct ipa_hwio_def_ipa_uc_ackq_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_ACKQ_DATA_WR_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_ackq_data_wr_0_s +{ + u32 ack_value1 : 16; + u32 ack_value2 : 8; + u32 ack_value1_type : 1; + u32 reserved0 : 7; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_ackq_data_wr_0_u +{ + struct ipa_hwio_def_ipa_uc_ackq_data_wr_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_ACKQ_DATA_RD_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_ackq_data_rd_0_s +{ + u32 ack_value1 : 16; + u32 ack_value2 : 8; + u32 ack_value1_type : 1; + u32 reserved0 : 7; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_ackq_data_rd_0_u +{ + struct ipa_hwio_def_ipa_uc_ackq_data_rd_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_ACKQ_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_ackq_status_s +{ + u32 status : 1; + u32 ackq_empty : 1; + u32 ackq_full : 1; + u32 reserved0 : 1; + u32 ackq_count : 5; + u32 reserved1 : 3; + u32 ackq_depth : 5; + u32 reserved2 : 15; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_ackq_status_u +{ + struct ipa_hwio_def_ipa_uc_ackq_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_SPLT_CMDQ_CMD_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_splt_cmdq_cmd_n_s +{ + u32 write_cmd : 1; + u32 pop_cmd : 1; + u32 release_rd_cmd : 1; + u32 release_wr_cmd : 1; + u32 release_rd_pkt : 1; + u32 release_wr_pkt : 1; + u32 release_rd_pkt_enhanced : 1; + u32 reserved0 : 25; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_splt_cmdq_cmd_n_u +{ + struct ipa_hwio_def_ipa_rx_splt_cmdq_cmd_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_SPLT_CMDQ_CFG_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_splt_cmdq_cfg_n_s +{ + u32 block_rd : 1; + u32 block_wr : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_splt_cmdq_cfg_n_u +{ + struct ipa_hwio_def_ipa_rx_splt_cmdq_cfg_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_SPLT_CMDQ_DATA_WR_0_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_splt_cmdq_data_wr_0_n_s +{ + u32 cmdq_packet_len_f : 16; + u32 cmdq_src_len_f : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_splt_cmdq_data_wr_0_n_u +{ + struct ipa_hwio_def_ipa_rx_splt_cmdq_data_wr_0_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_SPLT_CMDQ_DATA_WR_1_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_splt_cmdq_data_wr_1_n_s +{ + u32 cmdq_src_pipe_f : 8; + u32 cmdq_order_f : 2; + u32 cmdq_flags_f : 6; + u32 cmdq_opcode_f : 8; + u32 cmdq_metadata_f : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_splt_cmdq_data_wr_1_n_u +{ + struct ipa_hwio_def_ipa_rx_splt_cmdq_data_wr_1_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_SPLT_CMDQ_DATA_WR_2_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_splt_cmdq_data_wr_2_n_s +{ + u32 cmdq_addr_lsb_f : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_splt_cmdq_data_wr_2_n_u +{ + struct ipa_hwio_def_ipa_rx_splt_cmdq_data_wr_2_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_SPLT_CMDQ_DATA_WR_3_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_splt_cmdq_data_wr_3_n_s +{ + u32 cmdq_addr_msb_f : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_splt_cmdq_data_wr_3_n_u +{ + struct ipa_hwio_def_ipa_rx_splt_cmdq_data_wr_3_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_SPLT_CMDQ_DATA_RD_0_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_splt_cmdq_data_rd_0_n_s +{ + u32 cmdq_packet_len_f : 16; + u32 cmdq_src_len_f : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_splt_cmdq_data_rd_0_n_u +{ + struct ipa_hwio_def_ipa_rx_splt_cmdq_data_rd_0_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_SPLT_CMDQ_DATA_RD_1_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_splt_cmdq_data_rd_1_n_s +{ + u32 cmdq_src_pipe_f : 8; + u32 cmdq_order_f : 2; + u32 cmdq_flags_f : 6; + u32 cmdq_opcode_f : 8; + u32 cmdq_metadata_f : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_splt_cmdq_data_rd_1_n_u +{ + struct ipa_hwio_def_ipa_rx_splt_cmdq_data_rd_1_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_SPLT_CMDQ_DATA_RD_2_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_splt_cmdq_data_rd_2_n_s +{ + u32 cmdq_addr_lsb_f : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_splt_cmdq_data_rd_2_n_u +{ + struct ipa_hwio_def_ipa_rx_splt_cmdq_data_rd_2_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_SPLT_CMDQ_DATA_RD_3_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_splt_cmdq_data_rd_3_n_s +{ + u32 cmdq_addr_msb_f : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_splt_cmdq_data_rd_3_n_u +{ + struct ipa_hwio_def_ipa_rx_splt_cmdq_data_rd_3_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_SPLT_CMDQ_STATUS_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_splt_cmdq_status_n_s +{ + u32 status : 1; + u32 cmdq_empty : 1; + u32 cmdq_full : 1; + u32 cmdq_count : 2; + u32 cmdq_depth : 2; + u32 reserved0 : 25; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_splt_cmdq_status_n_u +{ + struct ipa_hwio_def_ipa_rx_splt_cmdq_status_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_TX_COMMANDER_CMDQ_CMD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_tx_commander_cmdq_cmd_s +{ + u32 write_cmd : 1; + u32 pop_cmd : 1; + u32 release_wr_cmd : 1; + u32 reserved0 : 1; + u32 release_wr_pkt : 1; + u32 reserved1 : 27; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_tx_commander_cmdq_cmd_u +{ + struct ipa_hwio_def_ipa_tx_commander_cmdq_cmd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_TX_COMMANDER_CMDQ_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_tx_commander_cmdq_cfg_s +{ + u32 block_wr : 1; + u32 reserved0 : 3; + u32 tx_select : 1; + u32 reserved1 : 27; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_tx_commander_cmdq_cfg_u +{ + struct ipa_hwio_def_ipa_tx_commander_cmdq_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_TX_COMMANDER_CMDQ_DATA_WR_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_tx_commander_cmdq_data_wr_0_s +{ + u32 cmdq_packet_len_f : 16; + u32 cmdq_dest_len_f : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_tx_commander_cmdq_data_wr_0_u +{ + struct ipa_hwio_def_ipa_tx_commander_cmdq_data_wr_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_TX_COMMANDER_CMDQ_DATA_WR_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_tx_commander_cmdq_data_wr_1_s +{ + u32 cmdq_dest_pipe_f : 8; + u32 cmdq_order_f : 2; + u32 cmdq_flags_f : 6; + u32 cmdq_rsrc_type_f : 8; + u32 cmdq_rsrc_arg_f : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_tx_commander_cmdq_data_wr_1_u +{ + struct ipa_hwio_def_ipa_tx_commander_cmdq_data_wr_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_TX_COMMANDER_CMDQ_DATA_WR_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_tx_commander_cmdq_data_wr_2_s +{ + u32 cmdq_addr_f : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_tx_commander_cmdq_data_wr_2_u +{ + struct ipa_hwio_def_ipa_tx_commander_cmdq_data_wr_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_TX_COMMANDER_CMDQ_DATA_RD_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_tx_commander_cmdq_data_rd_0_s +{ + u32 cmdq_packet_len_f : 16; + u32 cmdq_dest_len_f : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_tx_commander_cmdq_data_rd_0_u +{ + struct ipa_hwio_def_ipa_tx_commander_cmdq_data_rd_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_TX_COMMANDER_CMDQ_DATA_RD_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_tx_commander_cmdq_data_rd_1_s +{ + u32 cmdq_dest_pipe_f : 8; + u32 cmdq_order_f : 2; + u32 cmdq_flags_f : 6; + u32 cmdq_rsrc_type_f : 8; + u32 cmdq_rsrc_arg_f : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_tx_commander_cmdq_data_rd_1_u +{ + struct ipa_hwio_def_ipa_tx_commander_cmdq_data_rd_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_TX_COMMANDER_CMDQ_DATA_RD_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_tx_commander_cmdq_data_rd_2_s +{ + u32 cmdq_addr_f : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_tx_commander_cmdq_data_rd_2_u +{ + struct ipa_hwio_def_ipa_tx_commander_cmdq_data_rd_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_TX_COMMANDER_CMDQ_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_tx_commander_cmdq_status_s +{ + u32 status : 1; + u32 cmdq_empty : 1; + u32 cmdq_full : 1; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_tx_commander_cmdq_status_u +{ + struct ipa_hwio_def_ipa_tx_commander_cmdq_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_HPS_CMDQ_CMD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_hps_cmdq_cmd_s +{ + u32 write_cmd : 1; + u32 pop_cmd : 1; + u32 cmd_client : 3; + u32 rd_req : 1; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_hps_cmdq_cmd_u +{ + struct ipa_hwio_def_ipa_rx_hps_cmdq_cmd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_HPS_CMDQ_RELEASE_WR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_hps_cmdq_release_wr_s +{ + u32 release_wr_cmd : 6; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_hps_cmdq_release_wr_u +{ + struct ipa_hwio_def_ipa_rx_hps_cmdq_release_wr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_HPS_CMDQ_RELEASE_RD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_hps_cmdq_release_rd_s +{ + u32 release_rd_cmd : 6; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_hps_cmdq_release_rd_u +{ + struct ipa_hwio_def_ipa_rx_hps_cmdq_release_rd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_HPS_CMDQ_CFG_WR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_hps_cmdq_cfg_wr_s +{ + u32 block_wr : 6; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_hps_cmdq_cfg_wr_u +{ + struct ipa_hwio_def_ipa_rx_hps_cmdq_cfg_wr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_HPS_CMDQ_CFG_RD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_hps_cmdq_cfg_rd_s +{ + u32 block_rd : 6; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_hps_cmdq_cfg_rd_u +{ + struct ipa_hwio_def_ipa_rx_hps_cmdq_cfg_rd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_HPS_CMDQ_DATA_WR_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_hps_cmdq_data_wr_0_s +{ + u32 cmdq_packet_len_f : 16; + u32 cmdq_dest_len_f : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_hps_cmdq_data_wr_0_u +{ + struct ipa_hwio_def_ipa_rx_hps_cmdq_data_wr_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_HPS_CMDQ_DATA_WR_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_hps_cmdq_data_wr_1_s +{ + u32 cmdq_src_pipe_f : 8; + u32 cmdq_order_f : 2; + u32 cmdq_flags_f : 6; + u32 cmdq_opcode_f : 8; + u32 cmdq_metadata_f : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_hps_cmdq_data_wr_1_u +{ + struct ipa_hwio_def_ipa_rx_hps_cmdq_data_wr_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_HPS_CMDQ_DATA_WR_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_hps_cmdq_data_wr_2_s +{ + u32 cmdq_addr_lsb_f : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_hps_cmdq_data_wr_2_u +{ + struct ipa_hwio_def_ipa_rx_hps_cmdq_data_wr_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_HPS_CMDQ_DATA_WR_3 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_hps_cmdq_data_wr_3_s +{ + u32 cmdq_addr_msb_f : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_hps_cmdq_data_wr_3_u +{ + struct ipa_hwio_def_ipa_rx_hps_cmdq_data_wr_3_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_HPS_CMDQ_DATA_RD_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_0_s +{ + u32 cmdq_packet_len_f : 16; + u32 cmdq_dest_len_f : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_0_u +{ + struct ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_HPS_CMDQ_DATA_RD_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_1_s +{ + u32 cmdq_src_pipe_f : 8; + u32 cmdq_order_f : 2; + u32 cmdq_flags_f : 6; + u32 cmdq_opcode_f : 8; + u32 cmdq_metadata_f : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_1_u +{ + struct ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_HPS_CMDQ_DATA_RD_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_2_s +{ + u32 cmdq_addr_lsb_f : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_2_u +{ + struct ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_HPS_CMDQ_DATA_RD_3 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_3_s +{ + u32 cmdq_addr_msb_f : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_3_u +{ + struct ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_3_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_HPS_CMDQ_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_hps_cmdq_status_s +{ + u32 status : 1; + u32 cmdq_full : 1; + u32 cmdq_depth : 7; + u32 reserved0 : 23; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_hps_cmdq_status_u +{ + struct ipa_hwio_def_ipa_rx_hps_cmdq_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_HPS_CMDQ_STATUS_EMPTY +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_hps_cmdq_status_empty_s +{ + u32 cmdq_empty : 6; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_hps_cmdq_status_empty_u +{ + struct ipa_hwio_def_ipa_rx_hps_cmdq_status_empty_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_HPS_SNP +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_hps_snp_s +{ + u32 snp_last : 1; + u32 snp_write : 1; + u32 snp_valid : 1; + u32 snp_next_is_valid : 1; + u32 snp_next : 4; + u32 snp_head : 4; + u32 snp_addr : 4; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_hps_snp_u +{ + struct ipa_hwio_def_ipa_rx_hps_snp_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_HPS_CMDQ_COUNT +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_hps_cmdq_count_s +{ + u32 fifo_count : 7; + u32 reserved0 : 25; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_hps_cmdq_count_u +{ + struct ipa_hwio_def_ipa_rx_hps_cmdq_count_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_HPS_CLIENTS_MIN_DEPTH_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_hps_clients_min_depth_0_s +{ + u32 client_0_min_depth : 4; + u32 reserved0 : 4; + u32 client_1_min_depth : 4; + u32 reserved1 : 4; + u32 client_2_min_depth : 4; + u32 reserved2 : 4; + u32 client_3_min_depth : 4; + u32 client_4_min_depth : 4; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_hps_clients_min_depth_0_u +{ + struct ipa_hwio_def_ipa_rx_hps_clients_min_depth_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_HPS_CLIENTS_MIN_DEPTH_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_hps_clients_min_depth_1_s +{ + u32 client_5_min_depth : 4; + u32 reserved0 : 4; + u32 client_6_min_depth : 4; + u32 reserved1 : 4; + u32 client_7_min_depth : 4; + u32 reserved2 : 4; + u32 client_8_min_depth : 4; + u32 client_9_min_depth : 4; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_hps_clients_min_depth_1_u +{ + struct ipa_hwio_def_ipa_rx_hps_clients_min_depth_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_HPS_CLIENTS_MAX_DEPTH_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_hps_clients_max_depth_0_s +{ + u32 client_0_max_depth : 4; + u32 reserved0 : 4; + u32 client_1_max_depth : 4; + u32 reserved1 : 4; + u32 client_2_max_depth : 4; + u32 reserved2 : 4; + u32 client_3_max_depth : 4; + u32 client_4_max_depth : 4; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_hps_clients_max_depth_0_u +{ + struct ipa_hwio_def_ipa_rx_hps_clients_max_depth_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_HPS_CLIENTS_MAX_DEPTH_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_hps_clients_max_depth_1_s +{ + u32 client_5_max_depth : 4; + u32 reserved0 : 4; + u32 client_6_max_depth : 4; + u32 reserved1 : 4; + u32 client_7_max_depth : 4; + u32 reserved2 : 4; + u32 client_8_max_depth : 4; + u32 client_9_max_depth : 4; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_hps_clients_max_depth_1_u +{ + struct ipa_hwio_def_ipa_rx_hps_clients_max_depth_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_HPS_DPS_CMDQ_CMD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_hps_dps_cmdq_cmd_s +{ + u32 write_cmd : 1; + u32 pop_cmd : 1; + u32 rd_req : 1; + u32 reserved0 : 1; + u32 cmd_client : 8; + u32 reserved1 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_hps_dps_cmdq_cmd_u +{ + struct ipa_hwio_def_ipa_hps_dps_cmdq_cmd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_HPS_DPS_CMDQ_DATA_WR_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_hps_dps_cmdq_data_wr_0_s +{ + u32 cmdq_ctx_id_f : 4; + u32 cmdq_src_id_f : 8; + u32 cmdq_src_pipe_f : 8; + u32 cmdq_opcode_f : 2; + u32 cmdq_type_f : 1; + u32 cmdq_virt_cod_f : 1; + u32 reserved0 : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_hps_dps_cmdq_data_wr_0_u +{ + struct ipa_hwio_def_ipa_hps_dps_cmdq_data_wr_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_HPS_DPS_CMDQ_DATA_RD_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_hps_dps_cmdq_data_rd_0_s +{ + u32 cmdq_ctx_id_f : 4; + u32 cmdq_src_id_f : 8; + u32 cmdq_src_pipe_f : 8; + u32 cmdq_opcode_f : 2; + u32 cmdq_type_f : 1; + u32 cmdq_virt_cod_f : 1; + u32 reserved0 : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_hps_dps_cmdq_data_rd_0_u +{ + struct ipa_hwio_def_ipa_hps_dps_cmdq_data_rd_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_HPS_DPS_CMDQ_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_hps_dps_cmdq_status_s +{ + u32 status : 1; + u32 cmdq_full : 1; + u32 reserved0 : 2; + u32 cmdq_depth : 8; + u32 reserved1 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_hps_dps_cmdq_status_u +{ + struct ipa_hwio_def_ipa_hps_dps_cmdq_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_HPS_DPS_SNP +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_hps_dps_snp_s +{ + u32 snp_last : 1; + u32 snp_write : 1; + u32 snp_valid : 1; + u32 snp_next_is_valid : 1; + u32 snp_next : 8; + u32 snp_head : 8; + u32 snp_addr : 8; + u32 reserved0 : 4; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_hps_dps_snp_u +{ + struct ipa_hwio_def_ipa_hps_dps_snp_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_HPS_DPS_CMDQ_COUNT +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_hps_dps_cmdq_count_s +{ + u32 fifo_count : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_hps_dps_cmdq_count_u +{ + struct ipa_hwio_def_ipa_hps_dps_cmdq_count_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_HPS_DPS_CMDQ_RELEASE_WR_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_hps_dps_cmdq_release_wr_n_s +{ + u32 release_wr_cmd : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_hps_dps_cmdq_release_wr_n_u +{ + struct ipa_hwio_def_ipa_hps_dps_cmdq_release_wr_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_HPS_DPS_CMDQ_RELEASE_RD_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_hps_dps_cmdq_release_rd_n_s +{ + u32 release_rd_cmd : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_hps_dps_cmdq_release_rd_n_u +{ + struct ipa_hwio_def_ipa_hps_dps_cmdq_release_rd_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_HPS_DPS_CMDQ_CFG_WR_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_hps_dps_cmdq_cfg_wr_n_s +{ + u32 block_wr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_hps_dps_cmdq_cfg_wr_n_u +{ + struct ipa_hwio_def_ipa_hps_dps_cmdq_cfg_wr_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_HPS_DPS_CMDQ_CFG_RD_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_hps_dps_cmdq_cfg_rd_n_s +{ + u32 block_rd : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_hps_dps_cmdq_cfg_rd_n_u +{ + struct ipa_hwio_def_ipa_hps_dps_cmdq_cfg_rd_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_HPS_DPS_CMDQ_STATUS_EMPTY_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_hps_dps_cmdq_status_empty_n_s +{ + u32 cmdq_empty : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_hps_dps_cmdq_status_empty_n_u +{ + struct ipa_hwio_def_ipa_hps_dps_cmdq_status_empty_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DPS_TX_CMDQ_CMD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_dps_tx_cmdq_cmd_s +{ + u32 write_cmd : 1; + u32 pop_cmd : 1; + u32 rd_req : 1; + u32 cmd_client : 4; + u32 reserved0 : 25; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_dps_tx_cmdq_cmd_u +{ + struct ipa_hwio_def_ipa_dps_tx_cmdq_cmd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DPS_TX_CMDQ_RELEASE_WR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_dps_tx_cmdq_release_wr_s +{ + u32 release_wr_cmd : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_dps_tx_cmdq_release_wr_u +{ + struct ipa_hwio_def_ipa_dps_tx_cmdq_release_wr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DPS_TX_CMDQ_RELEASE_RD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_dps_tx_cmdq_release_rd_s +{ + u32 release_rd_cmd : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_dps_tx_cmdq_release_rd_u +{ + struct ipa_hwio_def_ipa_dps_tx_cmdq_release_rd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DPS_TX_CMDQ_CFG_WR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_dps_tx_cmdq_cfg_wr_s +{ + u32 block_wr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_dps_tx_cmdq_cfg_wr_u +{ + struct ipa_hwio_def_ipa_dps_tx_cmdq_cfg_wr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DPS_TX_CMDQ_CFG_RD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_dps_tx_cmdq_cfg_rd_s +{ + u32 block_rd : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_dps_tx_cmdq_cfg_rd_u +{ + struct ipa_hwio_def_ipa_dps_tx_cmdq_cfg_rd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DPS_TX_CMDQ_DATA_WR_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_dps_tx_cmdq_data_wr_0_s +{ + u32 cmdq_ctx_id_f : 4; + u32 cmdq_src_id_f : 8; + u32 cmdq_src_pipe_f : 8; + u32 cmdq_opcode_f : 2; + u32 cmdq_type_f : 1; + u32 cmdq_virt_cod_f : 1; + u32 seg_valid_f : 1; + u32 seg_ctx_id_f : 2; + u32 reserved0 : 5; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_dps_tx_cmdq_data_wr_0_u +{ + struct ipa_hwio_def_ipa_dps_tx_cmdq_data_wr_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DPS_TX_CMDQ_DATA_RD_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_dps_tx_cmdq_data_rd_0_s +{ + u32 cmdq_ctx_id_f : 4; + u32 cmdq_src_id_f : 8; + u32 cmdq_src_pipe_f : 8; + u32 cmdq_opcode_f : 2; + u32 cmdq_type_f : 1; + u32 cmdq_virt_cod_f : 1; + u32 seg_valid_f : 1; + u32 seg_ctx_id_f : 2; + u32 reserved0 : 5; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_dps_tx_cmdq_data_rd_0_u +{ + struct ipa_hwio_def_ipa_dps_tx_cmdq_data_rd_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DPS_TX_CMDQ_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_dps_tx_cmdq_status_s +{ + u32 status : 1; + u32 cmdq_full : 1; + u32 reserved0 : 2; + u32 cmdq_depth : 8; + u32 reserved1 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_dps_tx_cmdq_status_u +{ + struct ipa_hwio_def_ipa_dps_tx_cmdq_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DPS_TX_CMDQ_STATUS_EMPTY +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_dps_tx_cmdq_status_empty_s +{ + u32 cmdq_empty : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_dps_tx_cmdq_status_empty_u +{ + struct ipa_hwio_def_ipa_dps_tx_cmdq_status_empty_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DPS_TX_SNP +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_dps_tx_snp_s +{ + u32 snp_last : 1; + u32 snp_write : 1; + u32 snp_valid : 1; + u32 snp_next_is_valid : 1; + u32 snp_next : 8; + u32 snp_head : 8; + u32 snp_addr : 8; + u32 reserved0 : 4; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_dps_tx_snp_u +{ + struct ipa_hwio_def_ipa_dps_tx_snp_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DPS_TX_CMDQ_COUNT +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_dps_tx_cmdq_count_s +{ + u32 fifo_count : 7; + u32 reserved0 : 25; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_dps_tx_cmdq_count_u +{ + struct ipa_hwio_def_ipa_dps_tx_cmdq_count_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_LOG_BUF_HW_SNIF_EL_EN +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_log_buf_hw_snif_el_en_s +{ + u32 bitmap : 3; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_log_buf_hw_snif_el_en_u +{ + struct ipa_hwio_def_ipa_log_buf_hw_snif_el_en_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_log_buf_hw_snif_el_wr_n_rd_sel_s +{ + u32 bitmap : 3; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_log_buf_hw_snif_el_wr_n_rd_sel_u +{ + struct ipa_hwio_def_ipa_log_buf_hw_snif_el_wr_n_rd_sel_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_log_buf_hw_snif_el_cli_mux_s +{ + u32 all_cli_mux_concat : 15; + u32 reserved0 : 17; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_log_buf_hw_snif_el_cli_mux_u +{ + struct ipa_hwio_def_ipa_log_buf_hw_snif_el_cli_mux_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_log_buf_hw_snif_el_comp_val_0_cli_n_s +{ + u32 value : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_log_buf_hw_snif_el_comp_val_0_cli_n_u +{ + struct ipa_hwio_def_ipa_log_buf_hw_snif_el_comp_val_0_cli_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_log_buf_hw_snif_el_comp_val_1_cli_n_s +{ + u32 value : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_log_buf_hw_snif_el_comp_val_1_cli_n_u +{ + struct ipa_hwio_def_ipa_log_buf_hw_snif_el_comp_val_1_cli_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_log_buf_hw_snif_el_comp_val_2_cli_n_s +{ + u32 value : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_log_buf_hw_snif_el_comp_val_2_cli_n_u +{ + struct ipa_hwio_def_ipa_log_buf_hw_snif_el_comp_val_2_cli_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_log_buf_hw_snif_el_comp_val_3_cli_n_s +{ + u32 value : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_log_buf_hw_snif_el_comp_val_3_cli_n_u +{ + struct ipa_hwio_def_ipa_log_buf_hw_snif_el_comp_val_3_cli_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_log_buf_hw_snif_el_mask_val_0_cli_n_s +{ + u32 value : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_log_buf_hw_snif_el_mask_val_0_cli_n_u +{ + struct ipa_hwio_def_ipa_log_buf_hw_snif_el_mask_val_0_cli_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_log_buf_hw_snif_el_mask_val_1_cli_n_s +{ + u32 value : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_log_buf_hw_snif_el_mask_val_1_cli_n_u +{ + struct ipa_hwio_def_ipa_log_buf_hw_snif_el_mask_val_1_cli_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_log_buf_hw_snif_el_mask_val_2_cli_n_s +{ + u32 value : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_log_buf_hw_snif_el_mask_val_2_cli_n_u +{ + struct ipa_hwio_def_ipa_log_buf_hw_snif_el_mask_val_2_cli_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_log_buf_hw_snif_el_mask_val_3_cli_n_s +{ + u32 value : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_log_buf_hw_snif_el_mask_val_3_cli_n_u +{ + struct ipa_hwio_def_ipa_log_buf_hw_snif_el_mask_val_3_cli_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_LOG_BUF_HW_SNIF_LEGACY_RX +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_log_buf_hw_snif_legacy_rx_s +{ + u32 src_group_sel : 3; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_log_buf_hw_snif_legacy_rx_u +{ + struct ipa_hwio_def_ipa_log_buf_hw_snif_legacy_rx_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ACKMNGR_CMDQ_CMD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ackmngr_cmdq_cmd_s +{ + u32 write_cmd : 1; + u32 pop_cmd : 1; + u32 cmd_client : 8; + u32 rd_req : 1; + u32 reserved0 : 21; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ackmngr_cmdq_cmd_u +{ + struct ipa_hwio_def_ipa_ackmngr_cmdq_cmd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ACKMNGR_CMDQ_DATA_RD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ackmngr_cmdq_data_rd_s +{ + u32 cmdq_src_id : 8; + u32 cmdq_length : 16; + u32 cmdq_origin : 1; + u32 cmdq_sent : 1; + u32 cmdq_src_id_valid : 1; + u32 cmdq_error : 1; + u32 reserved0 : 4; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ackmngr_cmdq_data_rd_u +{ + struct ipa_hwio_def_ipa_ackmngr_cmdq_data_rd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ACKMNGR_CMDQ_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ackmngr_cmdq_status_s +{ + u32 status : 1; + u32 cmdq_full : 1; + u32 cmdq_depth : 7; + u32 reserved0 : 23; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ackmngr_cmdq_status_u +{ + struct ipa_hwio_def_ipa_ackmngr_cmdq_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ACKMNGR_CMDQ_STATUS_EMPTY_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ackmngr_cmdq_status_empty_n_s +{ + u32 cmdq_empty : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ackmngr_cmdq_status_empty_n_u +{ + struct ipa_hwio_def_ipa_ackmngr_cmdq_status_empty_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ACKMNGR_CMDQ_COUNT +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ackmngr_cmdq_count_s +{ + u32 fifo_count : 7; + u32 reserved0 : 25; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ackmngr_cmdq_count_u +{ + struct ipa_hwio_def_ipa_ackmngr_cmdq_count_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_FIFO_STATUS_CTRL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_fifo_status_ctrl_s +{ + u32 ipa_gsi_fifo_status_port_sel : 5; + u32 ipa_gsi_fifo_status_en : 1; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_fifo_status_ctrl_u +{ + struct ipa_hwio_def_ipa_gsi_fifo_status_ctrl_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TLV_FIFO_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_tlv_fifo_status_s +{ + u32 fifo_wr_ptr : 8; + u32 fifo_rd_ptr : 8; + u32 fifo_rd_pub_ptr : 8; + u32 fifo_empty : 1; + u32 fifo_empty_pub : 1; + u32 fifo_almost_full : 1; + u32 fifo_full : 1; + u32 fifo_almost_full_pub : 1; + u32 fifo_full_pub : 1; + u32 fifo_head_is_bubble : 1; + u32 reserved0 : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_tlv_fifo_status_u +{ + struct ipa_hwio_def_ipa_gsi_tlv_fifo_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_AOS_FIFO_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_aos_fifo_status_s +{ + u32 fifo_wr_ptr : 8; + u32 fifo_rd_ptr : 8; + u32 fifo_rd_pub_ptr : 8; + u32 fifo_empty : 1; + u32 fifo_empty_pub : 1; + u32 fifo_almost_full : 1; + u32 fifo_full : 1; + u32 fifo_almost_full_pub : 1; + u32 fifo_full_pub : 1; + u32 fifo_head_is_bubble : 1; + u32 reserved0 : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_aos_fifo_status_u +{ + struct ipa_hwio_def_ipa_gsi_aos_fifo_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ENDP_GSI_CONS_BYTES_TLV +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_endp_gsi_cons_bytes_tlv_s +{ + u32 cons_bytes : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_endp_gsi_cons_bytes_tlv_u +{ + struct ipa_hwio_def_ipa_endp_gsi_cons_bytes_tlv_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ENDP_GSI_CONS_BYTES_AOS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_endp_gsi_cons_bytes_aos_s +{ + u32 cons_bytes : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_endp_gsi_cons_bytes_aos_u +{ + struct ipa_hwio_def_ipa_endp_gsi_cons_bytes_aos_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_LOG_BUF_HW_GEN_RAM_OFFSET +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_log_buf_hw_gen_ram_offset_s +{ + u32 ram_region_baddr : 19; + u32 reserved0 : 1; + u32 ram_region_size : 4; + u32 reserved1 : 7; + u32 enable : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_log_buf_hw_gen_ram_offset_u +{ + struct ipa_hwio_def_ipa_log_buf_hw_gen_ram_offset_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_RX_HND_CMDQ_CMD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_rx_hnd_cmdq_cmd_s +{ + u32 write_cmd : 1; + u32 pop_cmd : 1; + u32 release_rd_cmd : 1; + u32 release_wr_cmd : 1; + u32 release_rd_pkt : 1; + u32 release_wr_pkt : 1; + u32 release_rd_pkt_enhanced : 1; + u32 reserved0 : 25; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_rx_hnd_cmdq_cmd_u +{ + struct ipa_hwio_def_ipa_uc_rx_hnd_cmdq_cmd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_RX_HND_CMDQ_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_rx_hnd_cmdq_cfg_s +{ + u32 block_rd : 1; + u32 block_wr : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_rx_hnd_cmdq_cfg_u +{ + struct ipa_hwio_def_ipa_uc_rx_hnd_cmdq_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_RX_HND_CMDQ_DATA_WR_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_rx_hnd_cmdq_data_wr_0_s +{ + u32 cmdq_packet_len_f : 16; + u32 cmdq_src_len_f : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_rx_hnd_cmdq_data_wr_0_u +{ + struct ipa_hwio_def_ipa_uc_rx_hnd_cmdq_data_wr_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_RX_HND_CMDQ_DATA_WR_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_rx_hnd_cmdq_data_wr_1_s +{ + u32 cmdq_src_pipe_f : 8; + u32 cmdq_order_f : 2; + u32 cmdq_flags_f : 6; + u32 cmdq_opcode_f : 8; + u32 cmdq_metadata_f : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_rx_hnd_cmdq_data_wr_1_u +{ + struct ipa_hwio_def_ipa_uc_rx_hnd_cmdq_data_wr_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_RX_HND_CMDQ_DATA_WR_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_rx_hnd_cmdq_data_wr_2_s +{ + u32 cmdq_addr_lsb_f : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_rx_hnd_cmdq_data_wr_2_u +{ + struct ipa_hwio_def_ipa_uc_rx_hnd_cmdq_data_wr_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_RX_HND_CMDQ_DATA_WR_3 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_rx_hnd_cmdq_data_wr_3_s +{ + u32 cmdq_addr_msb_f : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_rx_hnd_cmdq_data_wr_3_u +{ + struct ipa_hwio_def_ipa_uc_rx_hnd_cmdq_data_wr_3_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_RX_HND_CMDQ_DATA_RD_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_rx_hnd_cmdq_data_rd_0_s +{ + u32 cmdq_packet_len_f : 16; + u32 cmdq_src_len_f : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_rx_hnd_cmdq_data_rd_0_u +{ + struct ipa_hwio_def_ipa_uc_rx_hnd_cmdq_data_rd_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_RX_HND_CMDQ_DATA_RD_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_rx_hnd_cmdq_data_rd_1_s +{ + u32 cmdq_src_pipe_f : 8; + u32 cmdq_order_f : 2; + u32 cmdq_flags_f : 6; + u32 cmdq_opcode_f : 8; + u32 cmdq_metadata_f : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_rx_hnd_cmdq_data_rd_1_u +{ + struct ipa_hwio_def_ipa_uc_rx_hnd_cmdq_data_rd_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_RX_HND_CMDQ_DATA_RD_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_rx_hnd_cmdq_data_rd_2_s +{ + u32 cmdq_addr_lsb_f : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_rx_hnd_cmdq_data_rd_2_u +{ + struct ipa_hwio_def_ipa_uc_rx_hnd_cmdq_data_rd_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_RX_HND_CMDQ_DATA_RD_3 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_rx_hnd_cmdq_data_rd_3_s +{ + u32 cmdq_addr_msb_f : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_rx_hnd_cmdq_data_rd_3_u +{ + struct ipa_hwio_def_ipa_uc_rx_hnd_cmdq_data_rd_3_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_RX_HND_CMDQ_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_rx_hnd_cmdq_status_s +{ + u32 status : 1; + u32 cmdq_empty : 1; + u32 cmdq_full : 1; + u32 cmdq_count : 4; + u32 cmdq_depth : 4; + u32 reserved0 : 21; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_rx_hnd_cmdq_status_u +{ + struct ipa_hwio_def_ipa_uc_rx_hnd_cmdq_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RAM_HW_FIRST +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ram_hw_first_s +{ + u32 address : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ram_hw_first_u +{ + struct ipa_hwio_def_ipa_ram_hw_first_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RAM_HW_LAST +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ram_hw_last_s +{ + u32 address : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ram_hw_last_u +{ + struct ipa_hwio_def_ipa_ram_hw_last_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RAM_FRAG_FRST_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ram_frag_frst_base_addr_s +{ + u32 address : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ram_frag_frst_base_addr_u +{ + struct ipa_hwio_def_ipa_ram_frag_frst_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RAM_FRAG_SCND_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ram_frag_scnd_base_addr_s +{ + u32 address : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ram_frag_scnd_base_addr_u +{ + struct ipa_hwio_def_ipa_ram_frag_scnd_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RAM_GSI_TLV_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ram_gsi_tlv_base_addr_s +{ + u32 address : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ram_gsi_tlv_base_addr_u +{ + struct ipa_hwio_def_ipa_ram_gsi_tlv_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RAM_DCPH_KEYS_FIRST +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ram_dcph_keys_first_s +{ + u32 address : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ram_dcph_keys_first_u +{ + struct ipa_hwio_def_ipa_ram_dcph_keys_first_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RAM_DCPH_KEYS_LAST +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ram_dcph_keys_last_s +{ + u32 address : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ram_dcph_keys_last_u +{ + struct ipa_hwio_def_ipa_ram_dcph_keys_last_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DPS_SEQUENCER_FIRST +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_dps_sequencer_first_s +{ + u32 address : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_dps_sequencer_first_u +{ + struct ipa_hwio_def_ipa_dps_sequencer_first_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DPS_SEQUENCER_LAST +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_dps_sequencer_last_s +{ + u32 address : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_dps_sequencer_last_u +{ + struct ipa_hwio_def_ipa_dps_sequencer_last_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_HPS_SEQUENCER_FIRST +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_hps_sequencer_first_s +{ + u32 address : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_hps_sequencer_first_u +{ + struct ipa_hwio_def_ipa_hps_sequencer_first_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_HPS_SEQUENCER_LAST +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_hps_sequencer_last_s +{ + u32 address : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_hps_sequencer_last_u +{ + struct ipa_hwio_def_ipa_hps_sequencer_last_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RAM_PKT_CTX_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ram_pkt_ctx_base_addr_s +{ + u32 address : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ram_pkt_ctx_base_addr_u +{ + struct ipa_hwio_def_ipa_ram_pkt_ctx_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RAM_SW_AREA_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ram_sw_area_base_addr_s +{ + u32 address : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ram_sw_area_base_addr_u +{ + struct ipa_hwio_def_ipa_ram_sw_area_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RAM_HDRI_TYPE1_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ram_hdri_type1_base_addr_s +{ + u32 address : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ram_hdri_type1_base_addr_u +{ + struct ipa_hwio_def_ipa_ram_hdri_type1_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RAM_AGGR_NLO_COUNTERS_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ram_aggr_nlo_counters_base_addr_s +{ + u32 address : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ram_aggr_nlo_counters_base_addr_u +{ + struct ipa_hwio_def_ipa_ram_aggr_nlo_counters_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RAM_NLO_VP_CACHE_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ram_nlo_vp_cache_base_addr_s +{ + u32 address : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ram_nlo_vp_cache_base_addr_u +{ + struct ipa_hwio_def_ipa_ram_nlo_vp_cache_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RAM_COAL_VP_CACHE_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ram_coal_vp_cache_base_addr_s +{ + u32 address : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ram_coal_vp_cache_base_addr_u +{ + struct ipa_hwio_def_ipa_ram_coal_vp_cache_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RAM_COAL_VP_FIFO_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ram_coal_vp_fifo_base_addr_s +{ + u32 address : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ram_coal_vp_fifo_base_addr_u +{ + struct ipa_hwio_def_ipa_ram_coal_vp_fifo_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RAM_AGGR_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ram_aggr_base_addr_s +{ + u32 address : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ram_aggr_base_addr_u +{ + struct ipa_hwio_def_ipa_ram_aggr_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RAM_TX_COUNTERS_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ram_tx_counters_base_addr_s +{ + u32 address : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ram_tx_counters_base_addr_u +{ + struct ipa_hwio_def_ipa_ram_tx_counters_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RAM_DPL_FIFO_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ram_dpl_fifo_base_addr_s +{ + u32 address : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ram_dpl_fifo_base_addr_u +{ + struct ipa_hwio_def_ipa_ram_dpl_fifo_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RAM_COAL_MASTER_VP_CTX_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ram_coal_master_vp_ctx_base_addr_s +{ + u32 address : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ram_coal_master_vp_ctx_base_addr_u +{ + struct ipa_hwio_def_ipa_ram_coal_master_vp_ctx_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RAM_COAL_MASTER_VP_AGGR_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ram_coal_master_vp_aggr_base_addr_s +{ + u32 address : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ram_coal_master_vp_aggr_base_addr_u +{ + struct ipa_hwio_def_ipa_ram_coal_master_vp_aggr_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RAM_COAL_SLAVE_VP_CTX_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ram_coal_slave_vp_ctx_base_addr_s +{ + u32 address : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ram_coal_slave_vp_ctx_base_addr_u +{ + struct ipa_hwio_def_ipa_ram_coal_slave_vp_ctx_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RAM_UL_NLO_AGGR_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ram_ul_nlo_aggr_base_addr_s +{ + u32 address : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ram_ul_nlo_aggr_base_addr_u +{ + struct ipa_hwio_def_ipa_ram_ul_nlo_aggr_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RAM_UC_IRAM_ADDR_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ram_uc_iram_addr_base_addr_s +{ + u32 address : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ram_uc_iram_addr_base_addr_u +{ + struct ipa_hwio_def_ipa_ram_uc_iram_addr_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RAM_SNIFFER_HW_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ram_sniffer_hw_base_addr_s +{ + u32 address : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ram_sniffer_hw_base_addr_u +{ + struct ipa_hwio_def_ipa_ram_sniffer_hw_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RAM_FILTER_ROUTER_CACHE_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ram_filter_router_cache_base_addr_s +{ + u32 address : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ram_filter_router_cache_base_addr_u +{ + struct ipa_hwio_def_ipa_ram_filter_router_cache_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_SPARE_REG_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_spare_reg_1_s +{ + u32 spare_bits : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_spare_reg_1_u +{ + struct ipa_hwio_def_ipa_spare_reg_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_HPS_UC2SEQ_PUSH +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_hps_uc2seq_push_s +{ + u32 src_pipe : 8; + u32 src_flags : 2; + u32 src_id : 8; + u32 ctx_id : 4; + u32 reserved0 : 8; + u32 virt_opcode : 1; + u32 type : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_hps_uc2seq_push_u +{ + struct ipa_hwio_def_ipa_hps_uc2seq_push_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_HPS_UC2SEQ_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_hps_uc2seq_status_s +{ + u32 fill_level : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_hps_uc2seq_status_u +{ + struct ipa_hwio_def_ipa_hps_uc2seq_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_HPS_SEQ2UC_RD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_hps_seq2uc_rd_s +{ + u32 src_pipe : 8; + u32 src_flags : 2; + u32 src_id : 8; + u32 ctx_id : 4; + u32 reserved0 : 9; + u32 type : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_hps_seq2uc_rd_u +{ + struct ipa_hwio_def_ipa_hps_seq2uc_rd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_HPS_SEQ2UC_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_hps_seq2uc_status_s +{ + u32 fill_level : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_hps_seq2uc_status_u +{ + struct ipa_hwio_def_ipa_hps_seq2uc_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_HPS_SEQ2UC_CMD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_hps_seq2uc_cmd_s +{ + u32 pop : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_hps_seq2uc_cmd_u +{ + struct ipa_hwio_def_ipa_hps_seq2uc_cmd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DPS_UC2SEQ_PUSH +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_dps_uc2seq_push_s +{ + u32 src_pipe : 8; + u32 src_flags : 2; + u32 src_id : 8; + u32 ctx_id : 4; + u32 dest_pipe : 8; + u32 reserved0 : 1; + u32 type : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_dps_uc2seq_push_u +{ + struct ipa_hwio_def_ipa_dps_uc2seq_push_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DPS_UC2SEQ_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_dps_uc2seq_status_s +{ + u32 fill_level : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_dps_uc2seq_status_u +{ + struct ipa_hwio_def_ipa_dps_uc2seq_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DPS_SEQ2UC_RD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_dps_seq2uc_rd_s +{ + u32 src_pipe : 8; + u32 src_flags : 2; + u32 src_id : 8; + u32 ctx_id : 4; + u32 dest_pipe : 8; + u32 reserved0 : 1; + u32 type : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_dps_seq2uc_rd_u +{ + struct ipa_hwio_def_ipa_dps_seq2uc_rd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DPS_SEQ2UC_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_dps_seq2uc_status_s +{ + u32 fill_level : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_dps_seq2uc_status_u +{ + struct ipa_hwio_def_ipa_dps_seq2uc_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DPS_SEQ2UC_CMD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_dps_seq2uc_cmd_s +{ + u32 pop : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_dps_seq2uc_cmd_u +{ + struct ipa_hwio_def_ipa_dps_seq2uc_cmd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_NTF_TX_CMDQ_CMD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ntf_tx_cmdq_cmd_s +{ + u32 write_cmd : 1; + u32 pop_cmd : 1; + u32 rd_req : 1; + u32 reserved0 : 1; + u32 cmd_client : 8; + u32 reserved1 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ntf_tx_cmdq_cmd_u +{ + struct ipa_hwio_def_ipa_ntf_tx_cmdq_cmd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_NTF_TX_CMDQ_DATA_WR_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ntf_tx_cmdq_data_wr_0_s +{ + u32 cmdq_ctx_id_f : 4; + u32 cmdq_src_id_f : 8; + u32 cmdq_src_pipe_f : 8; + u32 cmdq_opcode_f : 2; + u32 cmdq_type_f : 1; + u32 cmdq_virt_cod_f : 1; + u32 seg_valid_f : 1; + u32 seg_ctx_id_f : 2; + u32 reserved0 : 5; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ntf_tx_cmdq_data_wr_0_u +{ + struct ipa_hwio_def_ipa_ntf_tx_cmdq_data_wr_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_NTF_TX_CMDQ_DATA_RD_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ntf_tx_cmdq_data_rd_0_s +{ + u32 cmdq_ctx_id_f : 4; + u32 cmdq_src_id_f : 8; + u32 cmdq_src_pipe_f : 8; + u32 cmdq_opcode_f : 2; + u32 cmdq_type_f : 1; + u32 cmdq_virt_cod_f : 1; + u32 seg_valid_f : 1; + u32 seg_ctx_id_f : 2; + u32 reserved0 : 5; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ntf_tx_cmdq_data_rd_0_u +{ + struct ipa_hwio_def_ipa_ntf_tx_cmdq_data_rd_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_NTF_TX_CMDQ_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ntf_tx_cmdq_status_s +{ + u32 status : 1; + u32 cmdq_full : 1; + u32 cmdq_depth : 7; + u32 reserved0 : 23; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ntf_tx_cmdq_status_u +{ + struct ipa_hwio_def_ipa_ntf_tx_cmdq_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_NTF_TX_SNP +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ntf_tx_snp_s +{ + u32 snp_last : 1; + u32 snp_write : 1; + u32 snp_valid : 1; + u32 snp_next_is_valid : 1; + u32 snp_next : 8; + u32 snp_head : 8; + u32 snp_addr : 8; + u32 reserved0 : 4; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ntf_tx_snp_u +{ + struct ipa_hwio_def_ipa_ntf_tx_snp_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_NTF_TX_CMDQ_COUNT +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ntf_tx_cmdq_count_s +{ + u32 fifo_count : 7; + u32 reserved0 : 25; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ntf_tx_cmdq_count_u +{ + struct ipa_hwio_def_ipa_ntf_tx_cmdq_count_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_PROD_ACKMNGR_CMDQ_CMD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_cmd_s +{ + u32 write_cmd : 1; + u32 pop_cmd : 1; + u32 cmd_client : 8; + u32 rd_req : 1; + u32 reserved0 : 21; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_prod_ackmngr_cmdq_cmd_u +{ + struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_cmd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_PROD_ACKMNGR_CMDQ_DATA_RD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_data_rd_s +{ + u32 cmdq_src_id : 8; + u32 cmdq_length : 16; + u32 cmdq_origin : 1; + u32 cmdq_sent : 1; + u32 cmdq_src_id_valid : 1; + u32 cmdq_userdata : 5; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_prod_ackmngr_cmdq_data_rd_u +{ + struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_data_rd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_PROD_ACKMNGR_CMDQ_DATA_RD_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_data_rd_1_s +{ + u32 cmdq_fnr_aggr_fc : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_prod_ackmngr_cmdq_data_rd_1_u +{ + struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_data_rd_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_status_empty_n_s +{ + u32 cmdq_empty : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_prod_ackmngr_cmdq_status_empty_n_u +{ + struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_status_empty_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_PROD_ACKMNGR_CMDQ_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_status_s +{ + u32 status : 1; + u32 cmdq_full : 1; + u32 cmdq_depth : 7; + u32 reserved0 : 23; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_prod_ackmngr_cmdq_status_u +{ + struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_PROD_ACKMNGR_CMDQ_COUNT +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_count_s +{ + u32 fifo_count : 7; + u32 reserved0 : 25; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_prod_ackmngr_cmdq_count_u +{ + struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_count_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ACKMNGR_SW_ACCESS_ACKINJ_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ackmngr_sw_access_ackinj_cfg_s +{ + u32 reserved0 : 5; + u32 ackinj_src_id_valid : 1; + u32 ackinj_origin : 1; + u32 ackinj_sent : 1; + u32 ackinj_src_id : 8; + u32 ackinj_length : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ackmngr_sw_access_ackinj_cfg_u +{ + struct ipa_hwio_def_ipa_ackmngr_sw_access_ackinj_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ACKMNGR_SW_ACCESS_ACKINJ_PIPE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ackmngr_sw_access_ackinj_pipe_s +{ + u32 cons_ackinj_src_pipe : 8; + u32 prod_ackinj_src_pipe : 8; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ackmngr_sw_access_ackinj_pipe_u +{ + struct ipa_hwio_def_ipa_ackmngr_sw_access_ackinj_pipe_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ACKMNGR_SW_ACCESS_ACKUPD_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ackmngr_sw_access_ackupd_cfg_s +{ + u32 ackupd_src_pipe : 8; + u32 ackupd_src_id : 8; + u32 ackupd_error : 1; + u32 reserved0 : 15; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ackmngr_sw_access_ackupd_cfg_u +{ + struct ipa_hwio_def_ipa_ackmngr_sw_access_ackupd_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ACKMNGR_SW_ACCESS_CMD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ackmngr_sw_access_cmd_s +{ + u32 ackinj_valid : 1; + u32 ackupd_valid : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ackmngr_sw_access_cmd_u +{ + struct ipa_hwio_def_ipa_ackmngr_sw_access_cmd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ACKMNGR_SW_ACCESS_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ackmngr_sw_access_status_s +{ + u32 ackinj_ready : 1; + u32 ackupd_ready : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ackmngr_sw_access_status_u +{ + struct ipa_hwio_def_ipa_ackmngr_sw_access_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_prod_ackmngr_sw_access_ackinj_cfg_s +{ + u32 reserved0 : 5; + u32 ackinj_src_id_valid : 1; + u32 ackinj_origin : 1; + u32 ackinj_sent : 1; + u32 ackinj_src_id : 8; + u32 ackinj_length : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_prod_ackmngr_sw_access_ackinj_cfg_u +{ + struct ipa_hwio_def_ipa_prod_ackmngr_sw_access_ackinj_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_PROD_ACKMNGR_SW_ACCESS_ACKUPD_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_prod_ackmngr_sw_access_ackupd_cfg_s +{ + u32 ackupd_src_pipe : 8; + u32 ackupd_src_id : 8; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_prod_ackmngr_sw_access_ackupd_cfg_u +{ + struct ipa_hwio_def_ipa_prod_ackmngr_sw_access_ackupd_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_PROD_ACKMNGR_SW_ACCESS_CMD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_prod_ackmngr_sw_access_cmd_s +{ + u32 ackinj_valid : 1; + u32 ackupd_valid : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_prod_ackmngr_sw_access_cmd_u +{ + struct ipa_hwio_def_ipa_prod_ackmngr_sw_access_cmd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_PROD_ACKMNGR_SW_ACCESS_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_prod_ackmngr_sw_access_status_s +{ + u32 ackinj_ready : 1; + u32 ackupd_ready : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_prod_ackmngr_sw_access_status_u +{ + struct ipa_hwio_def_ipa_prod_ackmngr_sw_access_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_prod_ackmngr_sw_access_ackinj_cfg1_s +{ + u32 ackinj_userdata : 6; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_prod_ackmngr_sw_access_ackinj_cfg1_u +{ + struct ipa_hwio_def_ipa_prod_ackmngr_sw_access_ackinj_cfg1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_NTF_TX_CMDQ_RELEASE_WR_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ntf_tx_cmdq_release_wr_n_s +{ + u32 release_wr_cmd : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ntf_tx_cmdq_release_wr_n_u +{ + struct ipa_hwio_def_ipa_ntf_tx_cmdq_release_wr_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_NTF_TX_CMDQ_RELEASE_RD_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ntf_tx_cmdq_release_rd_n_s +{ + u32 release_rd_cmd : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ntf_tx_cmdq_release_rd_n_u +{ + struct ipa_hwio_def_ipa_ntf_tx_cmdq_release_rd_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_NTF_TX_CMDQ_CFG_WR_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ntf_tx_cmdq_cfg_wr_n_s +{ + u32 block_wr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ntf_tx_cmdq_cfg_wr_n_u +{ + struct ipa_hwio_def_ipa_ntf_tx_cmdq_cfg_wr_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_NTF_TX_CMDQ_CFG_RD_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ntf_tx_cmdq_cfg_rd_n_s +{ + u32 block_rd : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ntf_tx_cmdq_cfg_rd_n_u +{ + struct ipa_hwio_def_ipa_ntf_tx_cmdq_cfg_rd_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_NTF_TX_CMDQ_STATUS_EMPTY_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ntf_tx_cmdq_status_empty_n_s +{ + u32 cmdq_empty : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ntf_tx_cmdq_status_empty_n_u +{ + struct ipa_hwio_def_ipa_ntf_tx_cmdq_status_empty_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_base_addr_s +{ + u32 zero : 21; + u32 base : 11; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_base_addr_u +{ + struct ipa_hwio_def_ipa_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_BASE_ADDR_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_base_addr_msb_s +{ + u32 base_msb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_base_addr_msb_u +{ + struct ipa_hwio_def_ipa_base_addr_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ENDP_GSI_CFG1_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_endp_gsi_cfg1_n_s +{ + u32 reserved0 : 16; + u32 endp_en : 1; + u32 reserved1 : 14; + u32 init_endp : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_endp_gsi_cfg1_n_u +{ + struct ipa_hwio_def_ipa_endp_gsi_cfg1_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_ipa_if_tlv_out_generator_1_s +{ + u32 gen_tlv_out_addr_lsb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_ipa_if_tlv_out_generator_1_u +{ + struct ipa_hwio_def_ipa_gsi_ipa_if_tlv_out_generator_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_ipa_if_tlv_out_generator_2_s +{ + u32 gen_tlv_out_addr_msb : 8; + u32 gen_tlv_out_length : 16; + u32 gen_tlv_out_routine : 4; + u32 gen_tlv_out_ee : 4; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_ipa_if_tlv_out_generator_2_u +{ + struct ipa_hwio_def_ipa_gsi_ipa_if_tlv_out_generator_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_3 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_ipa_if_tlv_out_generator_3_s +{ + u32 gen_tlv_out_chid : 8; + u32 gen_tlv_out_type : 4; + u32 gen_tlv_out_direction : 1; + u32 gen_tlv_out_top_addr_bit : 1; + u32 reserved0 : 2; + u32 gen_tlv_out_chain : 1; + u32 gen_tlv_out_user_data : 15; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_ipa_if_tlv_out_generator_3_u +{ + struct ipa_hwio_def_ipa_gsi_ipa_if_tlv_out_generator_3_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_CTRL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_ipa_if_tlv_out_generator_ctrl_s +{ + u32 gen_tlv_out_rdy : 1; + u32 reserved0 : 3; + u32 gen_tlv_out_status : 4; + u32 reserved1 : 8; + u32 gen_tlv_out_activate : 1; + u32 reserved2 : 3; + u32 gen_tlv_out_en : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_ipa_if_tlv_out_generator_ctrl_u +{ + struct ipa_hwio_def_ipa_gsi_ipa_if_tlv_out_generator_ctrl_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_IPA_IF_TLV_IN_RDY +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_ipa_if_tlv_in_rdy_s +{ + u32 gen_tlv_in_rdy : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_ipa_if_tlv_in_rdy_u +{ + struct ipa_hwio_def_ipa_gsi_ipa_if_tlv_in_rdy_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_IPA_IF_TLV_IN_DATA_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_ipa_if_tlv_in_data_1_s +{ + u32 gen_tlv_in_user_data : 16; + u32 gen_tlv_in_length : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_ipa_if_tlv_in_data_1_u +{ + struct ipa_hwio_def_ipa_gsi_ipa_if_tlv_in_data_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_IPA_IF_TLV_IN_DATA_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_ipa_if_tlv_in_data_2_s +{ + u32 gen_tlv_in_eot : 1; + u32 reserved0 : 3; + u32 gen_tlv_in_ee : 4; + u32 gen_tlv_in_chid : 8; + u32 gen_tlv_in_status : 4; + u32 reserved1 : 8; + u32 gen_tlv_in_routine : 4; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_ipa_if_tlv_in_data_2_u +{ + struct ipa_hwio_def_ipa_gsi_ipa_if_tlv_in_data_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ENDP_GSI_CFG_TLV_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_endp_gsi_cfg_tlv_n_s +{ + u32 fifo_base_addr : 16; + u32 fifo_size : 8; + u32 reserved0 : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_endp_gsi_cfg_tlv_n_u +{ + struct ipa_hwio_def_ipa_endp_gsi_cfg_tlv_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ENDP_GSI_CFG_AOS_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_endp_gsi_cfg_aos_n_s +{ + u32 fifo_base_addr : 16; + u32 fifo_size : 8; + u32 reserved0 : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_endp_gsi_cfg_aos_n_u +{ + struct ipa_hwio_def_ipa_endp_gsi_cfg_aos_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_COAL_VP_AOS_FIFO_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_coal_vp_aos_fifo_n_s +{ + u32 fifo_base_addr : 16; + u32 fifo_size : 8; + u32 reserved0 : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_coal_vp_aos_fifo_n_u +{ + struct ipa_hwio_def_ipa_coal_vp_aos_fifo_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_QMB_DEBUG_CTRL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_qmb_debug_ctrl_s +{ + u32 ram_slaveway_access_protection_disable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_qmb_debug_ctrl_u +{ + struct ipa_hwio_def_ipa_qmb_debug_ctrl_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_CTXH_CTRL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ctxh_ctrl_s +{ + u32 ctxh_lock_id : 4; + u32 reserved0 : 25; + u32 ctxh_wr_block_on_noc_err : 1; + u32 ctxh_lock_active : 1; + u32 ctxh_lock : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ctxh_ctrl_u +{ + struct ipa_hwio_def_ipa_ctxh_ctrl_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_CTX_ID_m_CTX_NUM_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ctx_id_m_ctx_num_n_s +{ + u32 ipa_ctxh_data : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ctx_id_m_ctx_num_n_u +{ + struct ipa_hwio_def_ipa_ctx_id_m_ctx_num_n_s def; + u32 value; +}; + +/*---------------------------------------------------------------------------- + * MODULE: IPA_CFG + *--------------------------------------------------------------------------*/ + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_FLAVOR_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_flavor_0_s +{ + u32 ipa_pipes : 8; + u32 ipa_cons_pipes : 8; + u32 ipa_prod_pipes : 8; + u32 ipa_prod_lowest : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_flavor_0_u +{ + struct ipa_hwio_def_ipa_flavor_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_FLAVOR_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_flavor_1_s +{ + u32 ctx_n : 6; + u32 reserved0 : 2; + u32 mbim_deagg_en : 1; + u32 ucp_en : 1; + u32 d_dcph_2_en : 1; + u32 d_dcph_en : 1; + u32 h_dcph_en : 1; + u32 reserved1 : 1; + u32 filter_router_cache_gen : 1; + u32 nat_acl_en : 1; + u32 vmidmt_en : 1; + u32 uc_en : 1; + u32 cpr_en : 1; + u32 dpl_en : 1; + u32 qmb0_slaveway_en : 1; + u32 qmb1_slaveway_en : 1; + u32 qmb1_en : 1; + u32 dual_tx_en : 1; + u32 rx_uc_handler_en : 1; + u32 gsi_slaveway_en : 1; + u32 pcie_path_en : 1; + u32 d_dcph_engine_num : 2; + u32 reserved2 : 3; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_flavor_1_u +{ + struct ipa_hwio_def_ipa_flavor_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_FLAVOR_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_flavor_2_s +{ + u32 qmb0_outst_wr : 6; + u32 reserved0 : 2; + u32 qmb0_outst_rd : 6; + u32 reserved1 : 2; + u32 qmb1_outst_wr : 6; + u32 reserved2 : 2; + u32 qmb1_outst_rd : 6; + u32 reserved3 : 2; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_flavor_2_u +{ + struct ipa_hwio_def_ipa_flavor_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_FLAVOR_3 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_flavor_3_s +{ + u32 rsrc_grp_src_num_wout_uc : 4; + u32 rsrc_grp_src_num_uc : 4; + u32 rsrc_grp_dst_num_wo_uc_n_drbip : 4; + u32 rsrc_grp_dst_num_uc : 4; + u32 pkt_ctx_size : 8; + u32 rsrc_grp_dst_num_drbip : 4; + u32 reserved0 : 4; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_flavor_3_u +{ + struct ipa_hwio_def_ipa_flavor_3_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_FLAVOR_4 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_flavor_4_s +{ + u32 generic_agg_pipes : 8; + u32 generic_deagg_pipes : 8; + u32 bearer_init_ctx_num : 4; + u32 mbim_agg_pipes : 4; + u32 reserved0 : 4; + u32 frag_tables_num : 2; + u32 reserved1 : 2; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_flavor_4_u +{ + struct ipa_hwio_def_ipa_flavor_4_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_FLAVOR_5 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_flavor_5_s +{ + u32 consumer_ack_mngr_db_depth : 6; + u32 reserved0 : 2; + u32 producer_ack_mngr_db_depth : 6; + u32 reserved1 : 2; + u32 ipa_num_ees : 4; + u32 gsi_num_ees : 4; + u32 rx_hps_cmdq_q_depth : 6; + u32 reserved2 : 2; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_flavor_5_u +{ + struct ipa_hwio_def_ipa_flavor_5_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_FLAVOR_6 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_flavor_6_s +{ + u32 hps_dmar_num : 4; + u32 dps_dmar_num : 4; + u32 data_descriptor_lists : 6; + u32 reserved0 : 2; + u32 data_descriptor_buffers : 8; + u32 data_sectors : 6; + u32 reserved1 : 2; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_flavor_6_u +{ + struct ipa_hwio_def_ipa_flavor_6_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_FLAVOR_7 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_flavor_7_s +{ + u32 tlv_entry_num : 10; + u32 reserved0 : 6; + u32 aos_entry_num : 10; + u32 coal_vp_num : 4; + u32 reserved1 : 2; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_flavor_7_u +{ + struct ipa_hwio_def_ipa_flavor_7_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_FLAVOR_8 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_flavor_8_s +{ + u32 multi_drbip_dmar_engine_num : 4; + u32 multi_drbip_dcph_engine_num : 4; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_flavor_8_u +{ + struct ipa_hwio_def_ipa_flavor_8_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_COMP_HW_VERSION +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_comp_hw_version_s +{ + u32 step : 16; + u32 minor : 12; + u32 major : 4; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_comp_hw_version_u +{ + struct ipa_hwio_def_ipa_comp_hw_version_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_VERSION +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_version_s +{ + u32 ipa_r_rev : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_version_u +{ + struct ipa_hwio_def_ipa_version_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_COMP_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_comp_cfg_s +{ + u32 ram_arb_priority_client_samp_fix_disable : 1; + u32 gsi_snoc_bypass_dis : 1; + u32 gen_qmb_0_snoc_bypass_dis : 1; + u32 gen_qmb_1_snoc_bypass_dis : 1; + u32 reserved0 : 1; + u32 ipa_qmb_select_by_address_cons_en : 1; + u32 ipa_qmb_select_by_address_prod_en : 1; + u32 gsi_multi_inorder_rd_dis : 1; + u32 gsi_multi_inorder_wr_dis : 1; + u32 gen_qmb_0_multi_inorder_rd_dis : 1; + u32 gen_qmb_1_multi_inorder_rd_dis : 1; + u32 gen_qmb_0_multi_inorder_wr_dis : 1; + u32 gen_qmb_1_multi_inorder_wr_dis : 1; + u32 gen_qmb_0_snoc_cnoc_loop_protection_disable : 1; + u32 gsi_snoc_cnoc_loop_protection_disable : 1; + u32 gsi_multi_axi_masters_dis : 1; + u32 ipa_qmb_select_by_address_global_en : 1; + u32 ipa_full_flush_wait_rsc_closure_en : 1; + u32 reserved1 : 1; + u32 qmb_ram_rd_cache_disable : 1; + u32 genqmb_aooowr : 1; + u32 gsi_if_out_of_buf_stop_reset_mask_enable : 1; + u32 ipa_atomic_fetcher_arb_lock_dis : 6; + u32 reserved2 : 2; + u32 gen_qmb_1_dynamic_asize : 1; + u32 gen_qmb_0_dynamic_asize : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_comp_cfg_u +{ + struct ipa_hwio_def_ipa_comp_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_CLKON_CFG_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_clkon_cfg_1_s +{ + u32 cgc_open_ipa_core_clk_phase : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_clkon_cfg_1_u +{ + struct ipa_hwio_def_ipa_clkon_cfg_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_CLKON_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_clkon_cfg_s +{ + u32 cgc_open_rx : 1; + u32 cgc_open_proc : 1; + u32 cgc_open_tx_wrapper : 1; + u32 cgc_open_misc : 1; + u32 cgc_open_ram_arb : 1; + u32 cgc_open_ftch_hps : 1; + u32 cgc_open_ftch_dps : 1; + u32 cgc_open_hps : 1; + u32 cgc_open_dps : 1; + u32 cgc_open_rx_hps_cmdqs : 1; + u32 cgc_open_hps_dps_cmdqs : 1; + u32 cgc_open_dps_tx_cmdqs : 1; + u32 cgc_open_rsrc_mngr : 1; + u32 cgc_open_ctx_handler : 1; + u32 cgc_open_ack_mngr : 1; + u32 cgc_open_d_dcph : 1; + u32 cgc_open_h_dcph : 1; + u32 reserved0 : 1; + u32 cgc_open_ntf_tx_cmdqs : 1; + u32 cgc_open_tx_0 : 1; + u32 cgc_open_tx_1 : 1; + u32 cgc_open_fnr : 1; + u32 cgc_open_qsb2axi_cmdq_l : 1; + u32 cgc_open_aggr_wrapper : 1; + u32 cgc_open_ram_slaveway : 1; + u32 cgc_open_qmb : 1; + u32 cgc_open_weight_arb : 1; + u32 cgc_open_gsi_if : 1; + u32 cgc_open_global : 1; + u32 cgc_open_global_2x_clk : 1; + u32 cgc_open_dpl_fifo : 1; + u32 cgc_open_drbip : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_clkon_cfg_u +{ + struct ipa_hwio_def_ipa_clkon_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ROUTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_route_s +{ + u32 route_def_pipe : 8; + u32 route_frag_def_pipe : 8; + u32 route_def_hdr_ofst : 10; + u32 route_def_hdr_table : 1; + u32 route_def_retain_hdr : 1; + u32 route_dis : 1; + u32 reserved0 : 3; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_route_u +{ + struct ipa_hwio_def_ipa_route_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MASTER_PRIORITY +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_master_priority_s +{ + u32 qmb_0_rd : 2; + u32 qmb_1_rd : 2; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_master_priority_u +{ + struct ipa_hwio_def_ipa_master_priority_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_SHARED_MEM_SIZE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_shared_mem_size_s +{ + u32 shared_mem_size : 16; + u32 shared_mem_baddr : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_shared_mem_size_u +{ + struct ipa_hwio_def_ipa_shared_mem_size_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_NAT_TIMER +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_nat_timer_s +{ + u32 nat_timer : 24; + u32 reserved0 : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_nat_timer_u +{ + struct ipa_hwio_def_ipa_nat_timer_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_TAG_TIMER +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_tag_timer_s +{ + u32 tag_timer : 24; + u32 reserved0 : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_tag_timer_u +{ + struct ipa_hwio_def_ipa_tag_timer_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_FRAG_RULES_CLR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_frag_rules_clr_s +{ + u32 clr : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_frag_rules_clr_u +{ + struct ipa_hwio_def_ipa_frag_rules_clr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_PROC_IPH_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_proc_iph_cfg_s +{ + u32 reserved0 : 8; + u32 iph_pkt_parser_protocol_stop_enable : 1; + u32 iph_pkt_parser_protocol_stop_hop : 1; + u32 iph_pkt_parser_protocol_stop_dest : 1; + u32 iph_pkt_parser_ihl_to_2nd_frag_en : 1; + u32 reserved1 : 4; + u32 iph_pkt_parser_protocol_stop_value : 8; + u32 d_dcph_multi_engine_disable : 1; + u32 reserved2 : 7; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_proc_iph_cfg_u +{ + struct ipa_hwio_def_ipa_proc_iph_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_QSB_MAX_WRITES +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_qsb_max_writes_s +{ + u32 gen_qmb_0_max_writes : 4; + u32 gen_qmb_1_max_writes : 4; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_qsb_max_writes_u +{ + struct ipa_hwio_def_ipa_qsb_max_writes_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_QSB_MAX_READS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_qsb_max_reads_s +{ + u32 gen_qmb_0_max_reads : 4; + u32 gen_qmb_1_max_reads : 4; + u32 reserved0 : 8; + u32 gen_qmb_0_max_read_beats : 8; + u32 gen_qmb_1_max_read_beats : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_qsb_max_reads_u +{ + struct ipa_hwio_def_ipa_qsb_max_reads_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_QSB_OUTSTANDING_COUNTER +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_qsb_outstanding_counter_s +{ + u32 gen_qmb_0_reads_cnt : 5; + u32 reserved0 : 3; + u32 gen_qmb_1_reads_cnt : 5; + u32 reserved1 : 3; + u32 gen_qmb_0_writes_cnt : 5; + u32 reserved2 : 3; + u32 gen_qmb_1_writes_cnt : 5; + u32 reserved3 : 3; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_qsb_outstanding_counter_u +{ + struct ipa_hwio_def_ipa_qsb_outstanding_counter_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_QSB_OUTSTANDING_BEATS_COUNTER +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_qsb_outstanding_beats_counter_s +{ + u32 gen_qmb_0_read_beats_cnt : 8; + u32 gen_qmb_1_read_beats_cnt : 8; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_qsb_outstanding_beats_counter_u +{ + struct ipa_hwio_def_ipa_qsb_outstanding_beats_counter_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DPL_TIMER_LSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_dpl_timer_lsb_s +{ + u32 tod_lsb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_dpl_timer_lsb_u +{ + struct ipa_hwio_def_ipa_dpl_timer_lsb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DPL_TIMER_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_dpl_timer_msb_s +{ + u32 tod_msb : 16; + u32 reserved0 : 11; + u32 gran_sel : 4; + u32 timer_en : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_dpl_timer_msb_u +{ + struct ipa_hwio_def_ipa_dpl_timer_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_RX_ACTIVE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_rx_active_n_s +{ + u32 endpoints : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_rx_active_n_u +{ + struct ipa_hwio_def_ipa_state_rx_active_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_TX_WRAPPER +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_tx_wrapper_s +{ + u32 tx0_idle : 1; + u32 tx1_idle : 1; + u32 ipa_prod_ackmngr_db_empty : 1; + u32 ipa_prod_ackmngr_state_idle : 1; + u32 ipa_prod_bresp_empty : 1; + u32 reserved0 : 13; + u32 coal_slave_idle : 1; + u32 coal_slave_ctx_idle : 1; + u32 reserved1 : 8; + u32 coal_slave_open_frame : 4; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_tx_wrapper_u +{ + struct ipa_hwio_def_ipa_state_tx_wrapper_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_TX0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_tx0_s +{ + u32 flopped_arbit_type : 3; + u32 arbit_type : 3; + u32 pa_idle : 1; + u32 pa_ctx_idle : 1; + u32 pa_rst_idle : 1; + u32 pa_pub_cnt_empty : 1; + u32 tx_cmd_main_idle : 1; + u32 tx_cmd_trnseq_idle : 1; + u32 tx_cmd_snif_idle : 1; + u32 tx_cmd_bresp_aloc_idle : 1; + u32 tx_cmd_bresp_inj_idle : 1; + u32 ar_idle : 1; + u32 dmaw_idle : 1; + u32 dmaw_last_outsd_idle : 1; + u32 pf_idle : 1; + u32 pf_empty : 1; + u32 aligner_empty : 1; + u32 holb_idle : 1; + u32 holb_mask_idle : 1; + u32 rsrcrel_idle : 1; + u32 suspend_empty : 1; + u32 cs_snif_idle : 1; + u32 suspend_req_empty : 1; + u32 reserved0 : 5; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_tx0_u +{ + struct ipa_hwio_def_ipa_state_tx0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_TX1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_tx1_s +{ + u32 flopped_arbit_type : 3; + u32 arbit_type : 3; + u32 pa_idle : 1; + u32 pa_ctx_idle : 1; + u32 pa_rst_idle : 1; + u32 pa_pub_cnt_empty : 1; + u32 tx_cmd_main_idle : 1; + u32 tx_cmd_trnseq_idle : 1; + u32 tx_cmd_snif_idle : 1; + u32 tx_cmd_bresp_aloc_idle : 1; + u32 tx_cmd_bresp_inj_idle : 1; + u32 ar_idle : 1; + u32 dmaw_idle : 1; + u32 dmaw_last_outsd_idle : 1; + u32 pf_idle : 1; + u32 pf_empty : 1; + u32 aligner_empty : 1; + u32 holb_idle : 1; + u32 holb_mask_idle : 1; + u32 rsrcrel_idle : 1; + u32 suspend_empty : 1; + u32 cs_snif_idle : 1; + u32 suspend_req_empty : 1; + u32 reserved0 : 5; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_tx1_u +{ + struct ipa_hwio_def_ipa_state_tx1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_TX0_MISC +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_tx0_misc_s +{ + u32 ipa_mbim_pkt_fms_idle : 1; + u32 mbim_direct_dma : 1; + u32 trnseq_force_valid : 1; + u32 pkt_drop_cnt_idle : 1; + u32 nlo_direct_dma : 1; + u32 coal_direct_dma : 1; + u32 last_cmd_pipe : 8; + u32 reserved0 : 18; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_tx0_misc_u +{ + struct ipa_hwio_def_ipa_state_tx0_misc_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_TX1_MISC +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_tx1_misc_s +{ + u32 ipa_mbim_pkt_fms_idle : 1; + u32 mbim_direct_dma : 1; + u32 trnseq_force_valid : 1; + u32 pkt_drop_cnt_idle : 1; + u32 nlo_direct_dma : 1; + u32 coal_direct_dma : 1; + u32 last_cmd_pipe : 8; + u32 reserved0 : 18; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_tx1_misc_u +{ + struct ipa_hwio_def_ipa_state_tx1_misc_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_FETCHER +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_fetcher_s +{ + u32 ipa_hps_ftch_state_idle : 1; + u32 ipa_hps_ftch_alloc_state_idle : 1; + u32 ipa_hps_ftch_pkt_state_idle : 1; + u32 ipa_hps_ftch_imm_state_idle : 1; + u32 ipa_hps_ftch_cmplt_state_idle : 1; + u32 ipa_hps_dmar_state_idle : 7; + u32 ipa_hps_dmar_slot_state_idle : 7; + u32 ipa_hps_imm_cmd_exec_state_idle : 1; + u32 reserved0 : 12; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_fetcher_u +{ + struct ipa_hwio_def_ipa_state_fetcher_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_FETCHER_MASK_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_fetcher_mask_0_s +{ + u32 mask_queue_dmar_uses_queue : 8; + u32 mask_queue_imm_exec : 8; + u32 mask_queue_no_resources_context : 8; + u32 mask_queue_no_resources_hps_dmar : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_fetcher_mask_0_u +{ + struct ipa_hwio_def_ipa_state_fetcher_mask_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_DFETCHER +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_dfetcher_s +{ + u32 ipa_dps_ftch_pkt_state_idle : 1; + u32 ipa_dps_ftch_cmplt_state_idle : 1; + u32 reserved0 : 2; + u32 ipa_dps_dmar_state_idle : 7; + u32 reserved1 : 5; + u32 ipa_dps_dmar_slot_state_idle : 7; + u32 reserved2 : 9; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_dfetcher_u +{ + struct ipa_hwio_def_ipa_state_dfetcher_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_ACL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_acl_s +{ + u32 ipa_hps_h_dcph_empty : 1; + u32 ipa_hps_h_dcph_active : 1; + u32 ipa_hps_pkt_parser_empty : 1; + u32 ipa_hps_pkt_parser_active : 1; + u32 ipa_hps_filter_nat_empty : 1; + u32 ipa_hps_filter_nat_active : 1; + u32 ipa_hps_router_empty : 1; + u32 ipa_hps_router_active : 1; + u32 ipa_hps_hdri_empty : 1; + u32 ipa_hps_hdri_active : 1; + u32 ipa_hps_ucp_empty : 1; + u32 ipa_hps_ucp_active : 1; + u32 ipa_hps_enqueuer_empty : 1; + u32 ipa_hps_enqueuer_active : 1; + u32 ipa_dps_d_dcph_empty : 1; + u32 ipa_dps_d_dcph_active : 1; + u32 reserved0 : 2; + u32 ipa_dps_dispatcher_empty : 1; + u32 ipa_dps_dispatcher_active : 1; + u32 ipa_dps_d_dcph_2_empty : 1; + u32 ipa_dps_d_dcph_2_active : 1; + u32 ipa_hps_sequencer_idle : 1; + u32 ipa_dps_sequencer_idle : 1; + u32 ipa_dps_d_dcph_2nd_empty : 1; + u32 ipa_dps_d_dcph_2nd_active : 1; + u32 ipa_hps_coal_master_empty : 1; + u32 ipa_hps_coal_master_active : 1; + u32 ipa_hps_multi_drbip_empty : 1; + u32 ipa_hps_multi_drbip_active : 1; + u32 reserved1 : 2; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_acl_u +{ + struct ipa_hwio_def_ipa_state_acl_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_s +{ + u32 rx_wait : 1; + u32 rx_idle : 1; + u32 tx_idle : 1; + u32 dpl_fifo_idle : 1; + u32 bam_gsi_idle : 1; + u32 ipa_status_sniffer_idle : 1; + u32 ipa_noc_idle : 1; + u32 aggr_idle : 1; + u32 mbim_aggr_idle : 1; + u32 ipa_rsrc_mngr_db_empty : 1; + u32 ipa_rsrc_state_idle : 1; + u32 ipa_ackmngr_db_empty : 1; + u32 ipa_ackmngr_state_idle : 1; + u32 ipa_tx_ackq_full : 1; + u32 ipa_prod_ackmngr_db_empty : 1; + u32 ipa_prod_ackmngr_state_idle : 1; + u32 ipa_prod_bresp_idle : 1; + u32 ipa_full_idle : 1; + u32 ipa_ntf_tx_empty : 1; + u32 ipa_tx_ackq_empty : 1; + u32 ipa_uc_ackq_empty : 1; + u32 ipa_rx_ackq_empty : 1; + u32 ipa_tx_commander_cmdq_empty : 1; + u32 ipa_rx_splt_cmdq_empty : 5; + u32 ipa_rx_hps_empty : 1; + u32 ipa_hps_dps_empty : 1; + u32 ipa_dps_tx_empty : 1; + u32 ipa_uc_rx_hnd_cmdq_empty : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_u +{ + struct ipa_hwio_def_ipa_state_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_GSI_AOS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_gsi_aos_s +{ + u32 ipa_gsi_aos_fsm_idle : 1; + u32 ipa_gsi_aos_nlo_fsm_idle : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_gsi_aos_u +{ + struct ipa_hwio_def_ipa_state_gsi_aos_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_GSI_IF +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_gsi_if_s +{ + u32 ipa_gsi_prod_fsm_tx_0 : 4; + u32 ipa_gsi_prod_fsm_tx_1 : 4; + u32 ipa_gsi_toggle_fsm_idle : 1; + u32 reserved0 : 7; + u32 ipa_gsi_skip_fsm : 2; + u32 reserved1 : 14; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_gsi_if_u +{ + struct ipa_hwio_def_ipa_state_gsi_if_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_GSI_IF_CONS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_gsi_if_cons_s +{ + u32 state_idle : 1; + u32 cache_vld : 7; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_gsi_if_cons_u +{ + struct ipa_hwio_def_ipa_state_gsi_if_cons_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_FETCHER_MASK_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_fetcher_mask_1_s +{ + u32 mask_queue_no_resources_ack_entry : 8; + u32 mask_queue_arb_lock : 8; + u32 mask_queue_step_mode : 8; + u32 mask_queue_no_space_dpl_fifo : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_fetcher_mask_1_u +{ + struct ipa_hwio_def_ipa_state_fetcher_mask_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_FETCHER_MASK_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_fetcher_mask_2_s +{ + u32 mask_queue_drbip_no_data_sectors : 8; + u32 mask_queue_drbip_pkt_exceed_max_size : 8; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_fetcher_mask_2_u +{ + struct ipa_hwio_def_ipa_state_fetcher_mask_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_DPL_FIFO +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_dpl_fifo_s +{ + u32 pop_fsm_state : 3; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_dpl_fifo_u +{ + struct ipa_hwio_def_ipa_state_dpl_fifo_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_COAL_MASTER +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_coal_master_s +{ + u32 vp_vld : 4; + u32 main_fsm_state : 4; + u32 find_open_fsm_state : 4; + u32 hash_calc_fsm_state : 4; + u32 check_fit_fsm_state : 4; + u32 init_vp_fsm_state : 4; + u32 lru_vp : 4; + u32 vp_timer_expired : 4; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_coal_master_u +{ + struct ipa_hwio_def_ipa_state_coal_master_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_COAL_MASTER_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_coal_master_1_s +{ + u32 init_vp_wr_ctx_line : 6; + u32 init_vp_rd_pkt_line : 6; + u32 init_vp_fsm_state : 4; + u32 check_fit_rd_ctx_line : 6; + u32 check_fit_fsm_state : 4; + u32 arbiter_state : 4; + u32 reserved0 : 2; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_coal_master_1_u +{ + struct ipa_hwio_def_ipa_state_coal_master_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_NLO_AGGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_nlo_aggr_s +{ + u32 nlo_aggr_state : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_nlo_aggr_u +{ + struct ipa_hwio_def_ipa_state_nlo_aggr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_CTXH +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_ctxh_s +{ + u32 ipa_ctxh_rd_idle : 1; + u32 ipa_ctxh_wr_idle : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_ctxh_u +{ + struct ipa_hwio_def_ipa_state_ctxh_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_UC_QMB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_uc_qmb_s +{ + u32 ctrl_fsm_state_queue_0 : 2; + u32 ot_table_empty_queue_0 : 1; + u32 ot_table_full_queue_0 : 1; + u32 comp_fifo_empty_queue_0 : 1; + u32 comp_fifo_full_queue_0 : 1; + u32 cmd_fifo_empty_queue_0 : 1; + u32 cmd_fifo_full_queue_0 : 1; + u32 queue_0_idle : 1; + u32 reserved0 : 7; + u32 ctrl_fsm_state_queue_1 : 2; + u32 ot_table_empty_queue_1 : 1; + u32 ot_table_full_queue_1 : 1; + u32 comp_fifo_empty_queue_1 : 1; + u32 comp_fifo_full_queue_1 : 1; + u32 cmd_fifo_empty_queue_1 : 1; + u32 cmd_fifo_full_queue_1 : 1; + u32 queue_1_idle : 1; + u32 reserved1 : 7; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_uc_qmb_u +{ + struct ipa_hwio_def_ipa_state_uc_qmb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_DRBIP +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_drbip_s +{ + u32 drbip_dmar_idle : 3; + u32 reserved0 : 5; + u32 drbip_dcph_idle : 1; + u32 reserved1 : 7; + u32 drbip_pkt_idle : 4; + u32 reserved2 : 12; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_drbip_u +{ + struct ipa_hwio_def_ipa_state_drbip_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_AGGR_ACTIVE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_aggr_active_n_s +{ + u32 endpoints : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_aggr_active_n_u +{ + struct ipa_hwio_def_ipa_state_aggr_active_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_GSI_TLV_FIFO_EMPTY_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_gsi_tlv_fifo_empty_n_s +{ + u32 pipe_fifo_empty : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_gsi_tlv_fifo_empty_n_u +{ + struct ipa_hwio_def_ipa_state_gsi_tlv_fifo_empty_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_GSI_AOS_FIFO_EMPTY_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_gsi_aos_fifo_empty_n_s +{ + u32 pipe_fifo_empty : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_gsi_aos_fifo_empty_n_u +{ + struct ipa_hwio_def_ipa_state_gsi_aos_fifo_empty_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_DRBIP_DROP_STATE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_drbip_drop_state_n_s +{ + u32 consumer_pipe_drop_state : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_drbip_drop_state_n_u +{ + struct ipa_hwio_def_ipa_state_drbip_drop_state_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_DFETCHER_MASK_0_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_dfetcher_mask_0_n_s +{ + u32 mask_queue_dst_grp_dmar_outstanding : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_dfetcher_mask_0_n_u +{ + struct ipa_hwio_def_ipa_state_dfetcher_mask_0_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_DFETCHER_MASK_1_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_dfetcher_mask_1_n_s +{ + u32 mask_queue_no_resources_data_sectors : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_dfetcher_mask_1_n_u +{ + struct ipa_hwio_def_ipa_state_dfetcher_mask_1_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_DFETCHER_MASK_2_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_dfetcher_mask_2_n_s +{ + u32 mask_queue_no_resources_dps_dmar : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_dfetcher_mask_2_n_u +{ + struct ipa_hwio_def_ipa_state_dfetcher_mask_2_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_DFETCHER_MASK_3_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_dfetcher_mask_3_n_s +{ + u32 mask_queue_no_resources_seg_ctx : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_dfetcher_mask_3_n_u +{ + struct ipa_hwio_def_ipa_state_dfetcher_mask_3_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_BAM_ACTIVATED_PORTS_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_bam_activated_ports_n_s +{ + u32 endpoints : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_bam_activated_ports_n_u +{ + struct ipa_hwio_def_ipa_bam_activated_ports_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_YELLOW_MARKER_BELOW_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_yellow_marker_below_n_s +{ + u32 endpoints : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_yellow_marker_below_n_u +{ + struct ipa_hwio_def_ipa_yellow_marker_below_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_YELLOW_MARKER_BELOW_EN_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_yellow_marker_below_en_n_s +{ + u32 endpoints : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_yellow_marker_below_en_n_u +{ + struct ipa_hwio_def_ipa_yellow_marker_below_en_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_YELLOW_MARKER_BELOW_CLR_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_yellow_marker_below_clr_n_s +{ + u32 endpoints : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_yellow_marker_below_clr_n_u +{ + struct ipa_hwio_def_ipa_yellow_marker_below_clr_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RED_MARKER_BELOW_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_red_marker_below_n_s +{ + u32 endpoints : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_red_marker_below_n_u +{ + struct ipa_hwio_def_ipa_red_marker_below_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RED_MARKER_BELOW_EN_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_red_marker_below_en_n_s +{ + u32 endpoints : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_red_marker_below_en_n_u +{ + struct ipa_hwio_def_ipa_red_marker_below_en_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RED_MARKER_BELOW_CLR_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_red_marker_below_clr_n_s +{ + u32 endpoints : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_red_marker_below_clr_n_u +{ + struct ipa_hwio_def_ipa_red_marker_below_clr_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_YELLOW_MARKER_SHADOW_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_yellow_marker_shadow_n_s +{ + u32 endpoints : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_yellow_marker_shadow_n_u +{ + struct ipa_hwio_def_ipa_yellow_marker_shadow_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RED_MARKER_SHADOW_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_red_marker_shadow_n_s +{ + u32 endpoints : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_red_marker_shadow_n_u +{ + struct ipa_hwio_def_ipa_red_marker_shadow_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_YELLOW_MARKER_ABOVE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_yellow_marker_above_n_s +{ + u32 endpoints : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_yellow_marker_above_n_u +{ + struct ipa_hwio_def_ipa_yellow_marker_above_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_YELLOW_MARKER_ABOVE_EN_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_yellow_marker_above_en_n_s +{ + u32 endpoints : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_yellow_marker_above_en_n_u +{ + struct ipa_hwio_def_ipa_yellow_marker_above_en_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_YELLOW_MARKER_ABOVE_CLR_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_yellow_marker_above_clr_n_s +{ + u32 endpoints : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_yellow_marker_above_clr_n_u +{ + struct ipa_hwio_def_ipa_yellow_marker_above_clr_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RED_MARKER_ABOVE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_red_marker_above_n_s +{ + u32 endpoints : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_red_marker_above_n_u +{ + struct ipa_hwio_def_ipa_red_marker_above_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RED_MARKER_ABOVE_EN_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_red_marker_above_en_n_s +{ + u32 endpoints : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_red_marker_above_en_n_u +{ + struct ipa_hwio_def_ipa_red_marker_above_en_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RED_MARKER_ABOVE_CLR_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_red_marker_above_clr_n_s +{ + u32 endpoints : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_red_marker_above_clr_n_u +{ + struct ipa_hwio_def_ipa_red_marker_above_clr_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_FILT_ROUT_CACHE_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_filt_rout_cache_cfg_s +{ + u32 ipa_router_cache_en : 1; + u32 reserved0 : 3; + u32 ipa_filter_cache_en : 1; + u32 reserved1 : 3; + u32 cache_low_priority_hashable_hit_disable : 1; + u32 reserved2 : 7; + u32 cache_lru_eviction_threshold : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_filt_rout_cache_cfg_u +{ + struct ipa_hwio_def_ipa_filt_rout_cache_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_FILT_ROUT_CACHE_REDUCE_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_filt_rout_cache_reduce_cfg_s +{ + u32 ipa_router_cache_reduce_en : 1; + u32 reserved0 : 3; + u32 ipa_filter_cache_reduce_en : 1; + u32 reserved1 : 3; + u32 ipa_router_cache_reduce_level : 8; + u32 ipa_filter_cache_reduce_level : 8; + u32 reserved2 : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_filt_rout_cache_reduce_cfg_u +{ + struct ipa_hwio_def_ipa_filt_rout_cache_reduce_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_FILT_ROUT_CACHE_FLUSH +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_filt_rout_cache_flush_s +{ + u32 ipa_router_cache_flush : 1; + u32 reserved0 : 3; + u32 ipa_filter_cache_flush : 1; + u32 reserved1 : 27; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_filt_rout_cache_flush_u +{ + struct ipa_hwio_def_ipa_filt_rout_cache_flush_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_FILT_ROUT_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_filt_rout_cfg_s +{ + u32 router_prefetch_en : 1; + u32 reserved0 : 3; + u32 filter_prefetch_en : 1; + u32 reserved1 : 3; + u32 filt_rout_data_cache_en : 1; + u32 reserved2 : 23; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_filt_rout_cfg_u +{ + struct ipa_hwio_def_ipa_filt_rout_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_IPV4_FILTER_INIT_VALUES +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ipv4_filter_init_values_s +{ + u32 ip_v4_filter_init_hashed_addr : 16; + u32 ip_v4_filter_init_non_hashed_addr : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ipv4_filter_init_values_u +{ + struct ipa_hwio_def_ipa_ipv4_filter_init_values_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_IPV6_FILTER_INIT_VALUES +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ipv6_filter_init_values_s +{ + u32 ip_v6_filter_init_hashed_addr : 16; + u32 ip_v6_filter_init_non_hashed_addr : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ipv6_filter_init_values_u +{ + struct ipa_hwio_def_ipa_ipv6_filter_init_values_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_IPV4_NAT_INIT_VALUES_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ipv4_nat_init_values_0_s +{ + u32 ip_v4_nat_init_rules_addr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ipv4_nat_init_values_0_u +{ + struct ipa_hwio_def_ipa_ipv4_nat_init_values_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_IPV4_NAT_INIT_VALUES_0_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ipv4_nat_init_values_0_msb_s +{ + u32 ip_v4_nat_init_rules_addr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ipv4_nat_init_values_0_msb_u +{ + struct ipa_hwio_def_ipa_ipv4_nat_init_values_0_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_IPV4_NAT_INIT_VALUES_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ipv4_nat_init_values_1_s +{ + u32 ip_v4_nat_init_exp_rules_addr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ipv4_nat_init_values_1_u +{ + struct ipa_hwio_def_ipa_ipv4_nat_init_values_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_IPV4_NAT_INIT_VALUES_1_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ipv4_nat_init_values_1_msb_s +{ + u32 ip_v4_nat_init_exp_rules_addr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ipv4_nat_init_values_1_msb_u +{ + struct ipa_hwio_def_ipa_ipv4_nat_init_values_1_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_IPV4_NAT_INIT_VALUES_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ipv4_nat_init_values_2_s +{ + u32 ip_v4_nat_init_index_table_addr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ipv4_nat_init_values_2_u +{ + struct ipa_hwio_def_ipa_ipv4_nat_init_values_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_IPV4_NAT_INIT_VALUES_2_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ipv4_nat_init_values_2_msb_s +{ + u32 ip_v4_nat_init_index_table_addr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ipv4_nat_init_values_2_msb_u +{ + struct ipa_hwio_def_ipa_ipv4_nat_init_values_2_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_IPV4_NAT_INIT_VALUES_3 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ipv4_nat_init_values_3_s +{ + u32 ip_v4_nat_init_index_table_exp_addr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ipv4_nat_init_values_3_u +{ + struct ipa_hwio_def_ipa_ipv4_nat_init_values_3_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_IPV4_NAT_INIT_VALUES_3_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ipv4_nat_init_values_3_msb_s +{ + u32 ip_v4_nat_init_index_table_exp_addr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ipv4_nat_init_values_3_msb_u +{ + struct ipa_hwio_def_ipa_ipv4_nat_init_values_3_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_IPV4_NAT_INIT_VALUES_4 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ipv4_nat_init_values_4_s +{ + u32 ip_v4_nat_init_table_index : 3; + u32 reserved0 : 1; + u32 ip_v4_nat_init_rules_addr_type : 1; + u32 ip_v4_nat_init_exp_rules_addr_type : 1; + u32 ip_v4_nat_init_index_table_addr_type : 1; + u32 ip_v4_nat_init_index_table_exp_addr_type : 1; + u32 ip_v4_nat_init_size_base_tables : 12; + u32 ip_v4_nat_init_size_exp_tables : 10; + u32 reserved1 : 2; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ipv4_nat_init_values_4_u +{ + struct ipa_hwio_def_ipa_ipv4_nat_init_values_4_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_IPV4_NAT_INIT_VALUES_5 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ipv4_nat_init_values_5_s +{ + u32 ip_v4_nat_init_pdn_config_table_addr : 20; + u32 reserved0 : 12; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ipv4_nat_init_values_5_u +{ + struct ipa_hwio_def_ipa_ipv4_nat_init_values_5_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_IPV4_ROUTE_INIT_VALUES +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ipv4_route_init_values_s +{ + u32 ip_v4_route_init_hashed_addr : 16; + u32 ip_v4_route_init_non_hashed_addr : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ipv4_route_init_values_u +{ + struct ipa_hwio_def_ipa_ipv4_route_init_values_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_IPV6_ROUTE_INIT_VALUES +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ipv6_route_init_values_s +{ + u32 ip_v6_route_init_hashed_addr : 16; + u32 ip_v6_route_init_non_hashed_addr : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ipv6_route_init_values_u +{ + struct ipa_hwio_def_ipa_ipv6_route_init_values_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_IPV6_CONN_TRACK_INIT_VALUES_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ipv6_conn_track_init_values_0_s +{ + u32 ip_v6_conn_track_init_table_addr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ipv6_conn_track_init_values_0_u +{ + struct ipa_hwio_def_ipa_ipv6_conn_track_init_values_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_IPV6_CONN_TRACK_INIT_VALUES_0_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ipv6_conn_track_init_values_0_msb_s +{ + u32 ip_v6_conn_track_init_table_addr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ipv6_conn_track_init_values_0_msb_u +{ + struct ipa_hwio_def_ipa_ipv6_conn_track_init_values_0_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_IPV6_CONN_TRACK_INIT_VALUES_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ipv6_conn_track_init_values_1_s +{ + u32 ip_v6_conn_track_init_exp_table_addr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ipv6_conn_track_init_values_1_u +{ + struct ipa_hwio_def_ipa_ipv6_conn_track_init_values_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_IPV6_CONN_TRACK_INIT_VALUES_1_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ipv6_conn_track_init_values_1_msb_s +{ + u32 ip_v6_conn_track_init_exp_table_addr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ipv6_conn_track_init_values_1_msb_u +{ + struct ipa_hwio_def_ipa_ipv6_conn_track_init_values_1_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_IPV6_CONN_TRACK_INIT_VALUES_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ipv6_conn_track_init_values_2_s +{ + u32 ip_v6_conn_track_init_table_index : 3; + u32 reserved0 : 1; + u32 ip_v6_conn_track_init_table_addr_type : 1; + u32 ip_v6_conn_track_init_exp_table_addr_type : 1; + u32 reserved1 : 2; + u32 ip_v6_conn_track_init_size_base_tables : 12; + u32 ip_v6_conn_track_init_size_exp_tables : 10; + u32 reserved2 : 2; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ipv6_conn_track_init_values_2_u +{ + struct ipa_hwio_def_ipa_ipv6_conn_track_init_values_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_HDR_INIT_LOCAL_VALUES +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_hdr_init_local_values_s +{ + u32 reserved0 : 12; + u32 hdr_init_local_hdr_addr : 16; + u32 reserved1 : 4; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_hdr_init_local_values_u +{ + struct ipa_hwio_def_ipa_hdr_init_local_values_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_HDR_INIT_SYSTEM_VALUES +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_hdr_init_system_values_s +{ + u32 hdr_init_system_hdr_table_addr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_hdr_init_system_values_u +{ + struct ipa_hwio_def_ipa_hdr_init_system_values_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_HDR_INIT_SYSTEM_VALUES_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_hdr_init_system_values_msb_s +{ + u32 hdr_init_system_hdr_table_addr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_hdr_init_system_values_msb_u +{ + struct ipa_hwio_def_ipa_hdr_init_system_values_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_IMM_CMD_ACCESS_PIPE_VALUES +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_imm_cmd_access_pipe_values_s +{ + u32 imm_cmd_filter_router_pipe : 8; + u32 imm_cmd_nat_pipe : 8; + u32 imm_cmd_conn_track_pipe : 8; + u32 imm_cmd_hdri_pipe : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_imm_cmd_access_pipe_values_u +{ + struct ipa_hwio_def_ipa_imm_cmd_access_pipe_values_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_IMM_CMD_ACCESS_PIPE_VALUES_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_imm_cmd_access_pipe_values_1_s +{ + u32 imm_cmd_gen_pipe : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_imm_cmd_access_pipe_values_1_u +{ + struct ipa_hwio_def_ipa_imm_cmd_access_pipe_values_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_FRAG_VALUES +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_frag_values_s +{ + u32 ipa_frag_ram_last_addr : 16; + u32 reserved0 : 8; + u32 ipa_frag_fairness_cnt : 4; + u32 reserved1 : 4; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_frag_values_u +{ + struct ipa_hwio_def_ipa_frag_values_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_SYS_PKT_PROC_CNTXT_BASE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_sys_pkt_proc_cntxt_base_s +{ + u32 zero : 3; + u32 addr : 29; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_sys_pkt_proc_cntxt_base_u +{ + struct ipa_hwio_def_ipa_sys_pkt_proc_cntxt_base_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_SYS_PKT_PROC_CNTXT_BASE_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_sys_pkt_proc_cntxt_base_msb_s +{ + u32 addr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_sys_pkt_proc_cntxt_base_msb_u +{ + struct ipa_hwio_def_ipa_sys_pkt_proc_cntxt_base_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_LOCAL_PKT_PROC_CNTXT_BASE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_local_pkt_proc_cntxt_base_s +{ + u32 zero : 3; + u32 addr : 15; + u32 reserved0 : 14; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_local_pkt_proc_cntxt_base_u +{ + struct ipa_hwio_def_ipa_local_pkt_proc_cntxt_base_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_SCND_FRAG_VALUES +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_scnd_frag_values_s +{ + u32 ipa_scnd_frag_ram_last_addr : 16; + u32 reserved0 : 8; + u32 ipa_scnd_frag_fairness_cnt : 4; + u32 reserved1 : 4; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_scnd_frag_values_u +{ + struct ipa_hwio_def_ipa_scnd_frag_values_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_AOS_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_aos_cfg_s +{ + u32 ipa_aos_tx_rx_priority : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_aos_cfg_u +{ + struct ipa_hwio_def_ipa_aos_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_TX_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_tx_cfg_s +{ + u32 reserved0 : 2; + u32 prefetch_almost_empty_size_tx0 : 4; + u32 dmaw_scnd_outsd_pred_threshold : 4; + u32 dmaw_scnd_outsd_pred_en : 1; + u32 dmaw_max_beats_256_dis : 1; + u32 pa_mask_en : 1; + u32 prefetch_almost_empty_size_tx1 : 4; + u32 dual_tx_enable : 1; + u32 sspnd_pa_no_start_state : 1; + u32 reserved1 : 1; + u32 holb_sticky_drop_en : 1; + u32 reserved2 : 11; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_tx_cfg_u +{ + struct ipa_hwio_def_ipa_tx_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_NAT_UC_EXTERNAL_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_nat_uc_external_cfg_s +{ + u32 ipa_nat_uc_external_table_addr_lsb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_nat_uc_external_cfg_u +{ + struct ipa_hwio_def_ipa_nat_uc_external_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_NAT_UC_LOCAL_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_nat_uc_local_cfg_s +{ + u32 ipa_nat_uc_local_table_addr_lsb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_nat_uc_local_cfg_u +{ + struct ipa_hwio_def_ipa_nat_uc_local_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_NAT_UC_SHARED_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_nat_uc_shared_cfg_s +{ + u32 ipa_nat_uc_external_table_addr_msb : 16; + u32 ipa_nat_uc_local_table_addr_msb : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_nat_uc_shared_cfg_u +{ + struct ipa_hwio_def_ipa_nat_uc_shared_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RAM_INTLV_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ram_intlv_cfg_s +{ + u32 ipa_ram_intlv_cfg : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ram_intlv_cfg_u +{ + struct ipa_hwio_def_ipa_ram_intlv_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_CONN_TRACK_UC_EXTERNAL_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_conn_track_uc_external_cfg_s +{ + u32 ipa_conn_track_uc_external_table_addr_lsb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_conn_track_uc_external_cfg_u +{ + struct ipa_hwio_def_ipa_conn_track_uc_external_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_CONN_TRACK_UC_LOCAL_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_conn_track_uc_local_cfg_s +{ + u32 ipa_conn_track_uc_local_table_addr_lsb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_conn_track_uc_local_cfg_u +{ + struct ipa_hwio_def_ipa_conn_track_uc_local_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_CONN_TRACK_UC_SHARED_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_conn_track_uc_shared_cfg_s +{ + u32 ipa_conn_track_uc_external_table_addr_msb : 16; + u32 ipa_conn_track_uc_local_table_addr_msb : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_conn_track_uc_shared_cfg_u +{ + struct ipa_hwio_def_ipa_conn_track_uc_shared_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_IDLE_INDICATION_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_idle_indication_cfg_s +{ + u32 enter_idle_debounce_thresh : 16; + u32 idle_indication_enable : 1; + u32 reserved0 : 15; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_idle_indication_cfg_u +{ + struct ipa_hwio_def_ipa_idle_indication_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_QTIME_TIMESTAMP_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_qtime_timestamp_cfg_s +{ + u32 dpl_timestamp_lsb : 5; + u32 reserved0 : 2; + u32 dpl_timestamp_sel : 1; + u32 tag_timestamp_lsb : 5; + u32 reserved1 : 3; + u32 nat_timestamp_lsb : 5; + u32 reserved2 : 11; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_qtime_timestamp_cfg_u +{ + struct ipa_hwio_def_ipa_qtime_timestamp_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_TIMERS_XO_CLK_DIV_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_timers_xo_clk_div_cfg_s +{ + u32 value : 9; + u32 reserved0 : 22; + u32 enable : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_timers_xo_clk_div_cfg_u +{ + struct ipa_hwio_def_ipa_timers_xo_clk_div_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_TIMERS_PULSE_GRAN_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_timers_pulse_gran_cfg_s +{ + u32 gran_0 : 3; + u32 gran_1 : 3; + u32 gran_2 : 3; + u32 gran_3 : 3; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_timers_pulse_gran_cfg_u +{ + struct ipa_hwio_def_ipa_timers_pulse_gran_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_QTIME_SMP +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_qtime_smp_s +{ + u32 pulse : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_qtime_smp_u +{ + struct ipa_hwio_def_ipa_qtime_smp_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_QTIME_LSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_qtime_lsb_s +{ + u32 value : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_qtime_lsb_u +{ + struct ipa_hwio_def_ipa_qtime_lsb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_QTIME_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_qtime_msb_s +{ + u32 value : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_qtime_msb_u +{ + struct ipa_hwio_def_ipa_qtime_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_SRC_RSRC_AMOUNT_REDUCE_EN +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_src_rsrc_amount_reduce_en_s +{ + u32 ipa_src_rsrc_amount_reduce_en : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_src_rsrc_amount_reduce_en_u +{ + struct ipa_hwio_def_ipa_src_rsrc_amount_reduce_en_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_src_rsrc_amount_reduce_values_0_s +{ + u32 ipa_src_rsrc_amount_reduce_value_rsrc_type_0 : 6; + u32 reserved0 : 2; + u32 ipa_src_rsrc_amount_reduce_value_rsrc_type_1 : 6; + u32 reserved1 : 2; + u32 ipa_src_rsrc_amount_reduce_value_rsrc_type_2 : 6; + u32 reserved2 : 2; + u32 ipa_src_rsrc_amount_reduce_value_rsrc_type_3 : 6; + u32 reserved3 : 2; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_src_rsrc_amount_reduce_values_0_u +{ + struct ipa_hwio_def_ipa_src_rsrc_amount_reduce_values_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_src_rsrc_amount_reduce_values_1_s +{ + u32 ipa_src_rsrc_amount_reduce_value_rsrc_type_4 : 6; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_src_rsrc_amount_reduce_values_1_u +{ + struct ipa_hwio_def_ipa_src_rsrc_amount_reduce_values_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DST_RSRC_AMOUNT_REDUCE_EN +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_dst_rsrc_amount_reduce_en_s +{ + u32 ipa_dst_rsrc_amount_reduce_en : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_dst_rsrc_amount_reduce_en_u +{ + struct ipa_hwio_def_ipa_dst_rsrc_amount_reduce_en_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DST_RSRC_AMOUNT_REDUCE_VALUES_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_dst_rsrc_amount_reduce_values_0_s +{ + u32 ipa_dst_rsrc_amount_reduce_value_rsrc_type_0 : 6; + u32 reserved0 : 2; + u32 ipa_dst_rsrc_amount_reduce_value_rsrc_type_1 : 6; + u32 reserved1 : 18; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_dst_rsrc_amount_reduce_values_0_u +{ + struct ipa_hwio_def_ipa_dst_rsrc_amount_reduce_values_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ATOMIC_LOCK_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_atomic_lock_cfg_s +{ + u32 groups_to_mask : 6; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_atomic_lock_cfg_u +{ + struct ipa_hwio_def_ipa_atomic_lock_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GENERIC_RAM_ARBITER_PRIORITY +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_generic_ram_arbiter_priority_s +{ + u32 rd_priority_valid : 1; + u32 wr_priority_valid : 1; + u32 reserved0 : 2; + u32 rd_priority_index : 8; + u32 wr_priority_index : 8; + u32 reserved1 : 12; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_generic_ram_arbiter_priority_u +{ + struct ipa_hwio_def_ipa_generic_ram_arbiter_priority_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_src_rsrc_grp_01_rsrc_type_n_s +{ + u32 src_rsrc_grp_0_min_limit : 6; + u32 reserved0 : 2; + u32 src_rsrc_grp_0_max_limit : 6; + u32 reserved1 : 2; + u32 src_rsrc_grp_1_min_limit : 6; + u32 reserved2 : 2; + u32 src_rsrc_grp_1_max_limit : 6; + u32 reserved3 : 2; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_src_rsrc_grp_01_rsrc_type_n_u +{ + struct ipa_hwio_def_ipa_src_rsrc_grp_01_rsrc_type_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_src_rsrc_grp_23_rsrc_type_n_s +{ + u32 src_rsrc_grp_2_min_limit : 6; + u32 reserved0 : 2; + u32 src_rsrc_grp_2_max_limit : 6; + u32 reserved1 : 2; + u32 src_rsrc_grp_3_min_limit : 6; + u32 reserved2 : 2; + u32 src_rsrc_grp_3_max_limit : 6; + u32 reserved3 : 2; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_src_rsrc_grp_23_rsrc_type_n_u +{ + struct ipa_hwio_def_ipa_src_rsrc_grp_23_rsrc_type_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_src_rsrc_grp_45_rsrc_type_n_s +{ + u32 src_rsrc_grp_4_min_limit : 6; + u32 reserved0 : 2; + u32 src_rsrc_grp_4_max_limit : 6; + u32 reserved1 : 2; + u32 src_rsrc_grp_5_min_limit : 6; + u32 reserved2 : 2; + u32 src_rsrc_grp_5_max_limit : 6; + u32 reserved3 : 2; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_src_rsrc_grp_45_rsrc_type_n_u +{ + struct ipa_hwio_def_ipa_src_rsrc_grp_45_rsrc_type_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_src_rsrc_grp_67_rsrc_type_n_s +{ + u32 src_rsrc_grp_6_min_limit : 6; + u32 reserved0 : 2; + u32 src_rsrc_grp_6_max_limit : 6; + u32 reserved1 : 2; + u32 src_rsrc_grp_7_min_limit : 6; + u32 reserved2 : 2; + u32 src_rsrc_grp_7_max_limit : 6; + u32 reserved3 : 2; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_src_rsrc_grp_67_rsrc_type_n_u +{ + struct ipa_hwio_def_ipa_src_rsrc_grp_67_rsrc_type_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_src_rsrc_grp_0123_rsrc_type_cnt_n_s +{ + u32 src_rsrc_grp_0_cnt : 6; + u32 reserved0 : 2; + u32 src_rsrc_grp_1_cnt : 6; + u32 reserved1 : 2; + u32 src_rsrc_grp_2_cnt : 6; + u32 reserved2 : 2; + u32 src_rsrc_grp_3_cnt : 6; + u32 reserved3 : 2; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_src_rsrc_grp_0123_rsrc_type_cnt_n_u +{ + struct ipa_hwio_def_ipa_src_rsrc_grp_0123_rsrc_type_cnt_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_SRC_RSRC_GRP_4567_RSRC_TYPE_CNT_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_src_rsrc_grp_4567_rsrc_type_cnt_n_s +{ + u32 src_rsrc_grp_4_cnt : 6; + u32 reserved0 : 2; + u32 src_rsrc_grp_5_cnt : 6; + u32 reserved1 : 18; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_src_rsrc_grp_4567_rsrc_type_cnt_n_u +{ + struct ipa_hwio_def_ipa_src_rsrc_grp_4567_rsrc_type_cnt_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_SRC_RSRC_TYPE_AMOUNT_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_src_rsrc_type_amount_n_s +{ + u32 src_rsrc_type_amount : 6; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_src_rsrc_type_amount_n_u +{ + struct ipa_hwio_def_ipa_src_rsrc_type_amount_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DST_RSRC_GRP_01_RSRC_TYPE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_dst_rsrc_grp_01_rsrc_type_n_s +{ + u32 dst_rsrc_grp_0_min_limit : 6; + u32 reserved0 : 2; + u32 dst_rsrc_grp_0_max_limit : 6; + u32 reserved1 : 2; + u32 dst_rsrc_grp_1_min_limit : 6; + u32 reserved2 : 2; + u32 dst_rsrc_grp_1_max_limit : 6; + u32 reserved3 : 2; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_dst_rsrc_grp_01_rsrc_type_n_u +{ + struct ipa_hwio_def_ipa_dst_rsrc_grp_01_rsrc_type_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DST_RSRC_GRP_23_RSRC_TYPE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_dst_rsrc_grp_23_rsrc_type_n_s +{ + u32 dst_rsrc_grp_2_min_limit : 6; + u32 reserved0 : 2; + u32 dst_rsrc_grp_2_max_limit : 6; + u32 reserved1 : 2; + u32 dst_rsrc_grp_3_min_limit : 6; + u32 reserved2 : 2; + u32 dst_rsrc_grp_3_max_limit : 6; + u32 reserved3 : 2; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_dst_rsrc_grp_23_rsrc_type_n_u +{ + struct ipa_hwio_def_ipa_dst_rsrc_grp_23_rsrc_type_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DST_RSRC_GRP_45_RSRC_TYPE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_dst_rsrc_grp_45_rsrc_type_n_s +{ + u32 dst_rsrc_grp_4_min_limit : 6; + u32 reserved0 : 2; + u32 dst_rsrc_grp_4_max_limit : 6; + u32 reserved1 : 2; + u32 dst_rsrc_grp_5_min_limit : 6; + u32 reserved2 : 2; + u32 dst_rsrc_grp_5_max_limit : 6; + u32 reserved3 : 2; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_dst_rsrc_grp_45_rsrc_type_n_u +{ + struct ipa_hwio_def_ipa_dst_rsrc_grp_45_rsrc_type_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DST_RSRC_GRP_67_RSRC_TYPE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_dst_rsrc_grp_67_rsrc_type_n_s +{ + u32 dst_rsrc_grp_6_min_limit : 6; + u32 reserved0 : 2; + u32 dst_rsrc_grp_6_max_limit : 6; + u32 reserved1 : 18; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_dst_rsrc_grp_67_rsrc_type_n_u +{ + struct ipa_hwio_def_ipa_dst_rsrc_grp_67_rsrc_type_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_dst_rsrc_grp_0123_rsrc_type_cnt_n_s +{ + u32 dst_rsrc_grp_0_cnt : 6; + u32 reserved0 : 2; + u32 dst_rsrc_grp_1_cnt : 6; + u32 reserved1 : 2; + u32 dst_rsrc_grp_2_cnt : 6; + u32 reserved2 : 2; + u32 dst_rsrc_grp_3_cnt : 6; + u32 reserved3 : 2; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_dst_rsrc_grp_0123_rsrc_type_cnt_n_u +{ + struct ipa_hwio_def_ipa_dst_rsrc_grp_0123_rsrc_type_cnt_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DST_RSRC_GRP_4567_RSRC_TYPE_CNT_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_dst_rsrc_grp_4567_rsrc_type_cnt_n_s +{ + u32 dst_rsrc_grp_4_cnt : 8; + u32 dst_rsrc_grp_5_cnt : 8; + u32 dst_rsrc_grp_6_cnt : 8; + u32 reserved0 : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_dst_rsrc_grp_4567_rsrc_type_cnt_n_u +{ + struct ipa_hwio_def_ipa_dst_rsrc_grp_4567_rsrc_type_cnt_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DST_RSRC_TYPE_AMOUNT_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_dst_rsrc_type_amount_n_s +{ + u32 dst_rsrc_type_amount : 6; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_dst_rsrc_type_amount_n_u +{ + struct ipa_hwio_def_ipa_dst_rsrc_type_amount_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_cfg_s +{ + u32 cmdq_split_not_wait_data_desc_prior_hdr_push : 1; + u32 rx_cmdq_splitter_cmdq_pending_mux_disable : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_cfg_u +{ + struct ipa_hwio_def_ipa_rx_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RSRC_GRP_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rsrc_grp_cfg_s +{ + u32 src_grp_special_valid : 1; + u32 reserved0 : 3; + u32 src_grp_special_index : 3; + u32 reserved1 : 1; + u32 dst_pipe_special_valid : 1; + u32 reserved2 : 3; + u32 dst_pipe_special_index : 8; + u32 dst_grp_special_valid : 1; + u32 reserved3 : 3; + u32 dst_grp_special_index : 6; + u32 reserved4 : 2; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rsrc_grp_cfg_u +{ + struct ipa_hwio_def_ipa_rsrc_grp_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RSRC_GRP_CFG_EXT +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rsrc_grp_cfg_ext_s +{ + u32 src_grp_2nd_priority_special_valid : 1; + u32 reserved0 : 3; + u32 src_grp_2nd_priority_special_index : 3; + u32 reserved1 : 25; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rsrc_grp_cfg_ext_u +{ + struct ipa_hwio_def_ipa_rsrc_grp_cfg_ext_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_AXI_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_axi_cfg_s +{ + u32 relaxed_ordering_gsi_rd : 1; + u32 relaxed_ordering_gsi_wr : 1; + u32 relaxed_ordering_ipa_rd : 1; + u32 relaxed_ordering_ipa_wr : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_axi_cfg_u +{ + struct ipa_hwio_def_ipa_axi_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_AGGR_FORCE_CLOSE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_aggr_force_close_n_s +{ + u32 aggr_force_close_pipe_bitmap : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_aggr_force_close_n_u +{ + struct ipa_hwio_def_ipa_aggr_force_close_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STAT_QUOTA_BASE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_stat_quota_base_n_s +{ + u32 base_addr_offset : 3; + u32 base_addr : 16; + u32 reserved0 : 13; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_stat_quota_base_n_u +{ + struct ipa_hwio_def_ipa_stat_quota_base_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STAT_TETHERING_BASE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_stat_tethering_base_n_s +{ + u32 base_addr_offset : 3; + u32 base_addr : 16; + u32 reserved0 : 13; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_stat_tethering_base_n_u +{ + struct ipa_hwio_def_ipa_stat_tethering_base_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STAT_DROP_CNT_BASE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_stat_drop_cnt_base_n_s +{ + u32 base_addr_offset : 3; + u32 base_addr : 16; + u32 reserved0 : 13; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_stat_drop_cnt_base_n_u +{ + struct ipa_hwio_def_ipa_stat_drop_cnt_base_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STAT_FILTER_IPV4_BASE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_stat_filter_ipv4_base_s +{ + u32 base_addr_offset : 3; + u32 base_addr : 16; + u32 reserved0 : 13; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_stat_filter_ipv4_base_u +{ + struct ipa_hwio_def_ipa_stat_filter_ipv4_base_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STAT_FILTER_IPV6_BASE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_stat_filter_ipv6_base_s +{ + u32 base_addr_offset : 3; + u32 base_addr : 16; + u32 reserved0 : 13; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_stat_filter_ipv6_base_u +{ + struct ipa_hwio_def_ipa_stat_filter_ipv6_base_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STAT_ROUTER_IPV4_BASE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_stat_router_ipv4_base_s +{ + u32 base_addr_offset : 3; + u32 base_addr : 16; + u32 reserved0 : 13; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_stat_router_ipv4_base_u +{ + struct ipa_hwio_def_ipa_stat_router_ipv4_base_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STAT_ROUTER_IPV6_BASE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_stat_router_ipv6_base_s +{ + u32 base_addr_offset : 3; + u32 base_addr : 16; + u32 reserved0 : 13; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_stat_router_ipv6_base_u +{ + struct ipa_hwio_def_ipa_stat_router_ipv6_base_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STAT_QUOTA_MASK_EE_n_REG_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_stat_quota_mask_ee_n_reg_k_s +{ + u32 pipe_mask : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_stat_quota_mask_ee_n_reg_k_u +{ + struct ipa_hwio_def_ipa_stat_quota_mask_ee_n_reg_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STAT_TETHERING_MASK_EE_n_REG_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_stat_tethering_mask_ee_n_reg_k_s +{ + u32 pipe_mask : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_stat_tethering_mask_ee_n_reg_k_u +{ + struct ipa_hwio_def_ipa_stat_tethering_mask_ee_n_reg_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STAT_DROP_CNT_MASK_EE_n_REG_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_stat_drop_cnt_mask_ee_n_reg_k_s +{ + u32 pipe_mask : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_stat_drop_cnt_mask_ee_n_reg_k_u +{ + struct ipa_hwio_def_ipa_stat_drop_cnt_mask_ee_n_reg_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_NLO_PP_CFG1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_nlo_pp_cfg1_s +{ + u32 nlo_ack_pp : 8; + u32 nlo_data_pp : 8; + u32 nlo_status_pp : 8; + u32 nlo_ack_max_vp : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_nlo_pp_cfg1_u +{ + struct ipa_hwio_def_ipa_nlo_pp_cfg1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_NLO_PP_CFG2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_nlo_pp_cfg2_s +{ + u32 nlo_ack_close_padd : 8; + u32 nlo_data_close_padd : 8; + u32 nlo_ack_buffer_mode : 1; + u32 nlo_data_buffer_mode : 1; + u32 nlo_status_buffer_mode : 1; + u32 reserved0 : 13; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_nlo_pp_cfg2_u +{ + struct ipa_hwio_def_ipa_nlo_pp_cfg2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_NLO_MIN_DSM_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_nlo_min_dsm_cfg_s +{ + u32 nlo_ack_min_dsm_len : 16; + u32 nlo_data_min_dsm_len : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_nlo_min_dsm_cfg_u +{ + struct ipa_hwio_def_ipa_nlo_min_dsm_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_NLO_VP_AGGR_CFG_LSB_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_nlo_vp_aggr_cfg_lsb_n_s +{ + u32 vp_pkt_limit : 6; + u32 vp_time_limit : 5; + u32 vp_byte_limit : 6; + u32 vp_hard_byte_limit_en : 1; + u32 vp_aggr_gran_sel : 1; + u32 reserved0 : 13; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_nlo_vp_aggr_cfg_lsb_n_u +{ + struct ipa_hwio_def_ipa_nlo_vp_aggr_cfg_lsb_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_NLO_VP_LIMIT_CFG_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_nlo_vp_limit_cfg_n_s +{ + u32 lower_size : 16; + u32 upper_size : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_nlo_vp_limit_cfg_n_u +{ + struct ipa_hwio_def_ipa_nlo_vp_limit_cfg_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_NLO_VP_FLUSH_REQ +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_nlo_vp_flush_req_s +{ + u32 vp_flush_pp_indx : 8; + u32 reserved0 : 8; + u32 vp_flush_vp_indx : 8; + u32 reserved1 : 7; + u32 vp_flush_req : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_nlo_vp_flush_req_u +{ + struct ipa_hwio_def_ipa_nlo_vp_flush_req_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_NLO_VP_FLUSH_COOKIE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_nlo_vp_flush_cookie_s +{ + u32 vp_flush_cookie : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_nlo_vp_flush_cookie_u +{ + struct ipa_hwio_def_ipa_nlo_vp_flush_cookie_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_NLO_VP_FLUSH_ACK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_nlo_vp_flush_ack_s +{ + u32 vp_flush_ack : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_nlo_vp_flush_ack_u +{ + struct ipa_hwio_def_ipa_nlo_vp_flush_ack_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_NLO_VP_DSM_OPEN +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_nlo_vp_dsm_open_s +{ + u32 vp_dsm_open : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_nlo_vp_dsm_open_u +{ + struct ipa_hwio_def_ipa_nlo_vp_dsm_open_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_NLO_VP_QBAP_OPEN +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_nlo_vp_qbap_open_s +{ + u32 vp_qbap_open : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_nlo_vp_qbap_open_u +{ + struct ipa_hwio_def_ipa_nlo_vp_qbap_open_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_COAL_MASTER_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_coal_master_cfg_s +{ + u32 coal_force_to_default : 1; + u32 coal_enhanced_ipv4_id_en : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_coal_master_cfg_u +{ + struct ipa_hwio_def_ipa_coal_master_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_COAL_EVICT_LRU +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_coal_evict_lru_s +{ + u32 coal_eviction_en : 1; + u32 coal_vp_lru_thrshld : 5; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_coal_evict_lru_u +{ + struct ipa_hwio_def_ipa_coal_evict_lru_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_COAL_QMAP_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_coal_qmap_cfg_s +{ + u32 mux_id_byte_sel : 2; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_coal_qmap_cfg_u +{ + struct ipa_hwio_def_ipa_coal_qmap_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_SNIFFER_QMB_SEL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_sniffer_qmb_sel_s +{ + u32 snif_qmb_sel : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_sniffer_qmb_sel_u +{ + struct ipa_hwio_def_ipa_sniffer_qmb_sel_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ULSO_CFG_IP_ID_MAX_VALUE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ulso_cfg_ip_id_max_value_n_s +{ + u32 ip_id_max_value : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ulso_cfg_ip_id_max_value_n_u +{ + struct ipa_hwio_def_ipa_ulso_cfg_ip_id_max_value_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ULSO_CFG_IP_ID_MIN_VALUE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ulso_cfg_ip_id_min_value_n_s +{ + u32 ip_id_min_value : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ulso_cfg_ip_id_min_value_n_u +{ + struct ipa_hwio_def_ipa_ulso_cfg_ip_id_min_value_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ENDP_INIT_CTRL_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_endp_init_ctrl_n_s +{ + u32 reserved0 : 1; + u32 endp_delay : 1; + u32 reserved1 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_endp_init_ctrl_n_u +{ + struct ipa_hwio_def_ipa_endp_init_ctrl_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ENDP_INIT_CTRL_SCND_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_endp_init_ctrl_scnd_n_s +{ + u32 reserved0 : 1; + u32 endp_delay : 1; + u32 reserved1 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_endp_init_ctrl_scnd_n_u +{ + struct ipa_hwio_def_ipa_endp_init_ctrl_scnd_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ENDP_INIT_CFG_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_endp_init_cfg_n_s +{ + u32 frag_offload_en : 1; + u32 cs_offload_en : 2; + u32 cs_metadata_hdr_offset : 4; + u32 reserved0 : 1; + u32 gen_qmb_master_sel : 1; + u32 reserved1 : 23; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_endp_init_cfg_n_u +{ + struct ipa_hwio_def_ipa_endp_init_cfg_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ENDP_INIT_NAT_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_endp_init_nat_n_s +{ + u32 nat_en : 2; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_endp_init_nat_n_u +{ + struct ipa_hwio_def_ipa_endp_init_nat_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ENDP_INIT_HDR_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_endp_init_hdr_n_s +{ + u32 hdr_len : 6; + u32 hdr_ofst_metadata_valid : 1; + u32 hdr_ofst_metadata : 6; + u32 hdr_additional_const_len : 6; + u32 hdr_ofst_pkt_size_valid : 1; + u32 hdr_ofst_pkt_size : 6; + u32 reserved0 : 1; + u32 hdr_len_inc_deagg_hdr : 1; + u32 hdr_len_msb : 2; + u32 hdr_ofst_metadata_msb : 2; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_endp_init_hdr_n_u +{ + struct ipa_hwio_def_ipa_endp_init_hdr_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ENDP_INIT_HDR_EXT_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_endp_init_hdr_ext_n_s +{ + u32 hdr_endianess : 1; + u32 hdr_total_len_or_pad_valid : 1; + u32 hdr_total_len_or_pad : 1; + u32 hdr_payload_len_inc_padding : 1; + u32 hdr_total_len_or_pad_offset : 6; + u32 hdr_pad_to_alignment : 4; + u32 reserved0 : 2; + u32 hdr_total_len_or_pad_offset_msb : 2; + u32 hdr_ofst_pkt_size_msb : 2; + u32 hdr_additional_const_len_msb : 2; + u32 hdr_bytes_to_remove_valid : 1; + u32 reserved1 : 1; + u32 hdr_bytes_to_remove : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_endp_init_hdr_ext_n_u +{ + struct ipa_hwio_def_ipa_endp_init_hdr_ext_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ENDP_INIT_HDR_METADATA_MASK_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_endp_init_hdr_metadata_mask_n_s +{ + u32 metadata_mask : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_endp_init_hdr_metadata_mask_n_u +{ + struct ipa_hwio_def_ipa_endp_init_hdr_metadata_mask_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ENDP_INIT_HDR_METADATA_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_endp_init_hdr_metadata_n_s +{ + u32 metadata : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_endp_init_hdr_metadata_n_u +{ + struct ipa_hwio_def_ipa_endp_init_hdr_metadata_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ENDP_INIT_MODE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_endp_init_mode_n_s +{ + u32 mode : 3; + u32 bearer_cntx_enable : 1; + u32 dest_pipe_index : 8; + u32 byte_threshold : 16; + u32 pipe_replicate_en : 1; + u32 pad_en : 1; + u32 drbip_acl_enable : 1; + u32 reserved0 : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_endp_init_mode_n_u +{ + struct ipa_hwio_def_ipa_endp_init_mode_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ENDP_INIT_AGGR_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_endp_init_aggr_n_s +{ + u32 aggr_en : 2; + u32 aggr_type : 3; + u32 aggr_byte_limit : 6; + u32 reserved0 : 1; + u32 aggr_time_limit : 5; + u32 aggr_pkt_limit : 6; + u32 aggr_sw_eof_active : 1; + u32 aggr_force_close : 1; + u32 reserved1 : 1; + u32 aggr_hard_byte_limit_enable : 1; + u32 aggr_gran_sel : 1; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_endp_init_aggr_n_u +{ + struct ipa_hwio_def_ipa_endp_init_aggr_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ENDP_INIT_HOL_BLOCK_EN_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_endp_init_hol_block_en_n_s +{ + u32 en : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_endp_init_hol_block_en_n_u +{ + struct ipa_hwio_def_ipa_endp_init_hol_block_en_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ENDP_INIT_HOL_BLOCK_TIMER_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_endp_init_hol_block_timer_n_s +{ + u32 time_limit : 5; + u32 reserved0 : 3; + u32 gran_sel : 2; + u32 reserved1 : 22; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_endp_init_hol_block_timer_n_u +{ + struct ipa_hwio_def_ipa_endp_init_hol_block_timer_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ENDP_INIT_DEAGGR_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_endp_init_deaggr_n_s +{ + u32 deaggr_hdr_len : 6; + u32 syspipe_err_detection : 1; + u32 packet_offset_valid : 1; + u32 packet_offset_location : 6; + u32 ignore_min_pkt_err : 1; + u32 reserved0 : 1; + u32 max_packet_len : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_endp_init_deaggr_n_u +{ + struct ipa_hwio_def_ipa_endp_init_deaggr_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ENDP_INIT_RSRC_GRP_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_endp_init_rsrc_grp_n_s +{ + u32 rsrc_grp : 3; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_endp_init_rsrc_grp_n_u +{ + struct ipa_hwio_def_ipa_endp_init_rsrc_grp_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ENDP_INIT_SEQ_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_endp_init_seq_n_s +{ + u32 hps_seq_type : 5; + u32 reserved0 : 3; + u32 dps_seq_type : 5; + u32 reserved1 : 19; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_endp_init_seq_n_u +{ + struct ipa_hwio_def_ipa_endp_init_seq_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ENDP_STATUS_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_endp_status_n_s +{ + u32 status_en : 1; + u32 status_endp : 8; + u32 status_pkt_supress : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_endp_status_n_u +{ + struct ipa_hwio_def_ipa_endp_status_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ENDP_SRC_ID_WRITE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_endp_src_id_write_n_s +{ + u32 src_id_write_value : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_endp_src_id_write_n_u +{ + struct ipa_hwio_def_ipa_endp_src_id_write_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ENDP_SRC_ID_READ_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_endp_src_id_read_n_s +{ + u32 src_id_read_value : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_endp_src_id_read_n_u +{ + struct ipa_hwio_def_ipa_endp_src_id_read_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ENDP_INIT_CONN_TRACK_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_endp_init_conn_track_n_s +{ + u32 conn_track_en : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_endp_init_conn_track_n_u +{ + struct ipa_hwio_def_ipa_endp_init_conn_track_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ENDP_INIT_DRBIP_CFG_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_endp_init_drbip_cfg_n_s +{ + u32 data_sectors_for_imm_cmd : 6; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_endp_init_drbip_cfg_n_u +{ + struct ipa_hwio_def_ipa_endp_init_drbip_cfg_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_FILTER_CACHE_CFG_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_filter_cache_cfg_n_s +{ + u32 filter_cache_msk_src_id : 1; + u32 filter_cache_msk_src_ip_add : 1; + u32 filter_cache_msk_dst_ip_add : 1; + u32 filter_cache_msk_src_port : 1; + u32 filter_cache_msk_dst_port : 1; + u32 filter_cache_msk_protocol : 1; + u32 filter_cache_msk_metadata : 1; + u32 reserved0 : 25; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_filter_cache_cfg_n_u +{ + struct ipa_hwio_def_ipa_filter_cache_cfg_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ROUTER_CACHE_CFG_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_router_cache_cfg_n_s +{ + u32 router_cache_msk_src_id : 1; + u32 router_cache_msk_src_ip_add : 1; + u32 router_cache_msk_dst_ip_add : 1; + u32 router_cache_msk_src_port : 1; + u32 router_cache_msk_dst_port : 1; + u32 router_cache_msk_protocol : 1; + u32 router_cache_msk_metadata : 1; + u32 reserved0 : 25; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_router_cache_cfg_n_u +{ + struct ipa_hwio_def_ipa_router_cache_cfg_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ENDP_YELLOW_RED_MARKER_CFG_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_endp_yellow_red_marker_cfg_n_s +{ + u32 reserved0 : 10; + u32 ipa_yellow_marker_cfg : 6; + u32 reserved1 : 10; + u32 ipa_red_marker_cfg : 6; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_endp_yellow_red_marker_cfg_n_u +{ + struct ipa_hwio_def_ipa_endp_yellow_red_marker_cfg_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ENDP_INIT_CTRL_STATUS_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_endp_init_ctrl_status_n_s +{ + u32 endp_suspend_status : 1; + u32 endp_delay_status : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_endp_init_ctrl_status_n_u +{ + struct ipa_hwio_def_ipa_endp_init_ctrl_status_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ENDP_INIT_PROD_CFG_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_endp_init_prod_cfg_n_s +{ + u32 tx_sel : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_endp_init_prod_cfg_n_u +{ + struct ipa_hwio_def_ipa_endp_init_prod_cfg_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ENDP_INIT_ULSO_CFG_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_endp_init_ulso_cfg_n_s +{ + u32 ipv4_id_min_max_val_index : 2; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_endp_init_ulso_cfg_n_u +{ + struct ipa_hwio_def_ipa_endp_init_ulso_cfg_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ENDP_INIT_UCP_CFG_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_endp_init_ucp_cfg_n_s +{ + u32 ucp_command_id : 16; + u32 ucp_trigger_en : 1; + u32 reserved0 : 15; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_endp_init_ucp_cfg_n_u +{ + struct ipa_hwio_def_ipa_endp_init_ucp_cfg_n_s def; + u32 value; +}; + +/*---------------------------------------------------------------------------- + * MODULE: IPA_VMIDMT + *--------------------------------------------------------------------------*/ + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_VMIDMT_SCR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_vmidmt_scr0_s +{ + u32 clientpd : 1; + u32 reserved0 : 1; + u32 gfie : 1; + u32 reserved1 : 1; + u32 gcfgere : 1; + u32 gcfgfie : 1; + u32 transientcfg : 2; + u32 stalld : 1; + u32 gse : 1; + u32 usfcfg : 1; + u32 reserved2 : 5; + u32 memattr : 3; + u32 reserved3 : 1; + u32 mtcfg : 1; + u32 smcfcfg : 1; + u32 shcfg : 2; + u32 racfg : 2; + u32 wacfg : 2; + u32 nscfg : 2; + u32 reserved4 : 2; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_vmidmt_scr0_u +{ + struct ipa_hwio_def_ipa_vmidmt_scr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_VMIDMT_SCR1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_vmidmt_scr1_s +{ + u32 reserved0 : 8; + u32 nsnumsmrgo : 6; + u32 reserved1 : 10; + u32 gasrae : 1; + u32 reserved2 : 7; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_vmidmt_scr1_u +{ + struct ipa_hwio_def_ipa_vmidmt_scr1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_VMIDMT_SCR2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_vmidmt_scr2_s +{ + u32 bpvmid : 5; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_vmidmt_scr2_u +{ + struct ipa_hwio_def_ipa_vmidmt_scr2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_VMIDMT_SACR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_vmidmt_sacr_s +{ + u32 bpreqpriority : 2; + u32 reserved0 : 2; + u32 bpreqprioritycfg : 1; + u32 reserved1 : 23; + u32 bprcosh : 1; + u32 bprcish : 1; + u32 bprcnsh : 1; + u32 reserved2 : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_vmidmt_sacr_u +{ + struct ipa_hwio_def_ipa_vmidmt_sacr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_VMIDMT_SIDR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_vmidmt_sidr0_s +{ + u32 numsmrg : 8; + u32 reserved0 : 1; + u32 numsidb : 4; + u32 reserved1 : 14; + u32 sms : 1; + u32 reserved2 : 3; + u32 ses : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_vmidmt_sidr0_u +{ + struct ipa_hwio_def_ipa_vmidmt_sidr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_VMIDMT_SIDR1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_vmidmt_sidr1_s +{ + u32 reserved0 : 8; + u32 numssdndx : 4; + u32 ssdtp : 1; + u32 reserved1 : 2; + u32 smcd : 1; + u32 reserved2 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_vmidmt_sidr1_u +{ + struct ipa_hwio_def_ipa_vmidmt_sidr1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_VMIDMT_SIDR2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_vmidmt_sidr2_s +{ + u32 ias : 4; + u32 oas : 4; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_vmidmt_sidr2_u +{ + struct ipa_hwio_def_ipa_vmidmt_sidr2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_VMIDMT_SIDR4 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_vmidmt_sidr4_s +{ + u32 step : 16; + u32 minor : 12; + u32 major : 4; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_vmidmt_sidr4_u +{ + struct ipa_hwio_def_ipa_vmidmt_sidr4_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_VMIDMT_SIDR5 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_vmidmt_sidr5_s +{ + u32 nvmid : 8; + u32 qribe : 1; + u32 msae : 1; + u32 reserved0 : 6; + u32 nummsdrb : 8; + u32 reserved1 : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_vmidmt_sidr5_u +{ + struct ipa_hwio_def_ipa_vmidmt_sidr5_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_VMIDMT_SIDR7 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_vmidmt_sidr7_s +{ + u32 minor : 4; + u32 major : 4; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_vmidmt_sidr7_u +{ + struct ipa_hwio_def_ipa_vmidmt_sidr7_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_VMIDMT_SGFAR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_vmidmt_sgfar0_s +{ + u32 sgfea0 : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_vmidmt_sgfar0_u +{ + struct ipa_hwio_def_ipa_vmidmt_sgfar0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_VMIDMT_SGFAR1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_vmidmt_sgfar1_s +{ + u32 sgfea1 : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_vmidmt_sgfar1_u +{ + struct ipa_hwio_def_ipa_vmidmt_sgfar1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_VMIDMT_SGFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_vmidmt_sgfsr_s +{ + u32 reserved0 : 1; + u32 usf : 1; + u32 smcf : 1; + u32 reserved1 : 2; + u32 caf : 1; + u32 reserved2 : 24; + u32 multi_cfg : 1; + u32 multi_client : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_vmidmt_sgfsr_u +{ + struct ipa_hwio_def_ipa_vmidmt_sgfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_VMIDMT_SGFSRRESTORE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_vmidmt_sgfsrrestore_s +{ + u32 reserved0 : 1; + u32 usf : 1; + u32 smcf : 1; + u32 reserved1 : 2; + u32 caf : 1; + u32 reserved2 : 24; + u32 multi_cfg : 1; + u32 multi_client : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_vmidmt_sgfsrrestore_u +{ + struct ipa_hwio_def_ipa_vmidmt_sgfsrrestore_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_VMIDMT_SGFSYNDR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_vmidmt_sgfsyndr0_s +{ + u32 reserved0 : 1; + u32 wnr : 1; + u32 reserved1 : 2; + u32 nsstate : 1; + u32 nsattr : 1; + u32 reserved2 : 2; + u32 mssselfauth : 1; + u32 reserved3 : 23; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_vmidmt_sgfsyndr0_u +{ + struct ipa_hwio_def_ipa_vmidmt_sgfsyndr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_VMIDMT_SGFSYNDR1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_vmidmt_sgfsyndr1_s +{ + u32 streamindex : 8; + u32 reserved0 : 8; + u32 ssdindex : 8; + u32 msdindex : 7; + u32 reserved1 : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_vmidmt_sgfsyndr1_u +{ + struct ipa_hwio_def_ipa_vmidmt_sgfsyndr1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_VMIDMT_SGFSYNDR2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_vmidmt_sgfsyndr2_s +{ + u32 amid : 8; + u32 apid : 5; + u32 abid : 3; + u32 avmid : 5; + u32 reserved0 : 3; + u32 atid : 5; + u32 reserved1 : 3; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_vmidmt_sgfsyndr2_u +{ + struct ipa_hwio_def_ipa_vmidmt_sgfsyndr2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_VMIDMT_VMIDMTSCR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_vmidmt_vmidmtscr0_s +{ + u32 clkonoffe : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_vmidmt_vmidmtscr0_u +{ + struct ipa_hwio_def_ipa_vmidmt_vmidmtscr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_VMIDMT_CR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_vmidmt_cr0_s +{ + u32 clientpd : 1; + u32 reserved0 : 1; + u32 gfie : 1; + u32 reserved1 : 1; + u32 gcfgere : 1; + u32 gcfgfie : 1; + u32 transientcfg : 2; + u32 stalld : 1; + u32 gse : 1; + u32 usfcfg : 1; + u32 vmidpne : 1; + u32 reserved2 : 4; + u32 memattr : 3; + u32 reserved3 : 1; + u32 mtcfg : 1; + u32 smcfcfg : 1; + u32 shcfg : 2; + u32 racfg : 2; + u32 wacfg : 2; + u32 reserved4 : 4; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_vmidmt_cr0_u +{ + struct ipa_hwio_def_ipa_vmidmt_cr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_VMIDMT_CR2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_vmidmt_cr2_s +{ + u32 bpvmid : 5; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_vmidmt_cr2_u +{ + struct ipa_hwio_def_ipa_vmidmt_cr2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_VMIDMT_ACR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_vmidmt_acr_s +{ + u32 bpreqpriority : 2; + u32 reserved0 : 2; + u32 bpreqprioritycfg : 1; + u32 reserved1 : 23; + u32 bprcosh : 1; + u32 bprcish : 1; + u32 bprcnsh : 1; + u32 reserved2 : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_vmidmt_acr_u +{ + struct ipa_hwio_def_ipa_vmidmt_acr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_VMIDMT_IDR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_vmidmt_idr0_s +{ + u32 numsmrg : 8; + u32 reserved0 : 1; + u32 numsidb : 4; + u32 reserved1 : 14; + u32 sms : 1; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_vmidmt_idr0_u +{ + struct ipa_hwio_def_ipa_vmidmt_idr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_VMIDMT_IDR1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_vmidmt_idr1_s +{ + u32 reserved0 : 8; + u32 numssdndx : 4; + u32 ssdtp : 1; + u32 reserved1 : 2; + u32 smcd : 1; + u32 reserved2 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_vmidmt_idr1_u +{ + struct ipa_hwio_def_ipa_vmidmt_idr1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_VMIDMT_IDR2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_vmidmt_idr2_s +{ + u32 ias : 4; + u32 oas : 4; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_vmidmt_idr2_u +{ + struct ipa_hwio_def_ipa_vmidmt_idr2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_VMIDMT_IDR4 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_vmidmt_idr4_s +{ + u32 step : 16; + u32 minor : 12; + u32 major : 4; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_vmidmt_idr4_u +{ + struct ipa_hwio_def_ipa_vmidmt_idr4_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_VMIDMT_IDR5 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_vmidmt_idr5_s +{ + u32 nvmid : 8; + u32 qribe : 1; + u32 msae : 1; + u32 reserved0 : 6; + u32 nummsdrb : 8; + u32 reserved1 : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_vmidmt_idr5_u +{ + struct ipa_hwio_def_ipa_vmidmt_idr5_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_VMIDMT_IDR7 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_vmidmt_idr7_s +{ + u32 minor : 4; + u32 major : 4; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_vmidmt_idr7_u +{ + struct ipa_hwio_def_ipa_vmidmt_idr7_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_VMIDMT_GFAR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_vmidmt_gfar0_s +{ + u32 gfea0 : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_vmidmt_gfar0_u +{ + struct ipa_hwio_def_ipa_vmidmt_gfar0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_VMIDMT_GFAR1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_vmidmt_gfar1_s +{ + u32 gfea1 : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_vmidmt_gfar1_u +{ + struct ipa_hwio_def_ipa_vmidmt_gfar1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_VMIDMT_GFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_vmidmt_gfsr_s +{ + u32 reserved0 : 1; + u32 usf : 1; + u32 smcf : 1; + u32 reserved1 : 2; + u32 caf : 1; + u32 reserved2 : 1; + u32 pf : 1; + u32 reserved3 : 22; + u32 multi_cfg : 1; + u32 multi_client : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_vmidmt_gfsr_u +{ + struct ipa_hwio_def_ipa_vmidmt_gfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_VMIDMT_GFSRRESTORE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_vmidmt_gfsrrestore_s +{ + u32 reserved0 : 1; + u32 usf : 1; + u32 smcf : 1; + u32 reserved1 : 2; + u32 caf : 1; + u32 reserved2 : 1; + u32 pf : 1; + u32 reserved3 : 22; + u32 multi_cfg : 1; + u32 multi_client : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_vmidmt_gfsrrestore_u +{ + struct ipa_hwio_def_ipa_vmidmt_gfsrrestore_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_VMIDMT_GFSYNDR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_vmidmt_gfsyndr0_s +{ + u32 reserved0 : 1; + u32 wnr : 1; + u32 reserved1 : 2; + u32 nsstate : 1; + u32 nsattr : 1; + u32 reserved2 : 2; + u32 mssselfauth : 1; + u32 reserved3 : 23; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_vmidmt_gfsyndr0_u +{ + struct ipa_hwio_def_ipa_vmidmt_gfsyndr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_VMIDMT_GFSYNDR1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_vmidmt_gfsyndr1_s +{ + u32 streamindex : 8; + u32 reserved0 : 8; + u32 ssdindex : 8; + u32 msdindex : 7; + u32 reserved1 : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_vmidmt_gfsyndr1_u +{ + struct ipa_hwio_def_ipa_vmidmt_gfsyndr1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_VMIDMT_GFSYNDR2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_vmidmt_gfsyndr2_s +{ + u32 amid : 8; + u32 apid : 5; + u32 abid : 3; + u32 avmid : 5; + u32 reserved0 : 3; + u32 atid : 5; + u32 reserved1 : 3; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_vmidmt_gfsyndr2_u +{ + struct ipa_hwio_def_ipa_vmidmt_gfsyndr2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_VMIDMT_VMIDMTCR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_vmidmt_vmidmtcr0_s +{ + u32 clkonoffe : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_vmidmt_vmidmtcr0_u +{ + struct ipa_hwio_def_ipa_vmidmt_vmidmtcr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_VMIDMT_VMIDMTACR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_vmidmt_vmidmtacr_s +{ + u32 rwe : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_vmidmt_vmidmtacr_u +{ + struct ipa_hwio_def_ipa_vmidmt_vmidmtacr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_VMIDMT_NSCR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_vmidmt_nscr0_s +{ + u32 clientpd : 1; + u32 reserved0 : 1; + u32 gfie : 1; + u32 reserved1 : 1; + u32 gcfgere : 1; + u32 gcfgfie : 1; + u32 transientcfg : 2; + u32 stalld : 1; + u32 gse : 1; + u32 usfcfg : 1; + u32 vmidpne : 1; + u32 reserved2 : 4; + u32 memattr : 3; + u32 reserved3 : 1; + u32 mtcfg : 1; + u32 smcfcfg : 1; + u32 shcfg : 2; + u32 racfg : 2; + u32 wacfg : 2; + u32 reserved4 : 4; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_vmidmt_nscr0_u +{ + struct ipa_hwio_def_ipa_vmidmt_nscr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_VMIDMT_NSCR2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_vmidmt_nscr2_s +{ + u32 bpvmid : 5; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_vmidmt_nscr2_u +{ + struct ipa_hwio_def_ipa_vmidmt_nscr2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_VMIDMT_NSACR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_vmidmt_nsacr_s +{ + u32 bpreqpriority : 2; + u32 reserved0 : 2; + u32 bpreqprioritycfg : 1; + u32 reserved1 : 23; + u32 bprcosh : 1; + u32 bprcish : 1; + u32 bprcnsh : 1; + u32 reserved2 : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_vmidmt_nsacr_u +{ + struct ipa_hwio_def_ipa_vmidmt_nsacr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_VMIDMT_NSGFAR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_vmidmt_nsgfar0_s +{ + u32 gfea0 : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_vmidmt_nsgfar0_u +{ + struct ipa_hwio_def_ipa_vmidmt_nsgfar0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_VMIDMT_NSGFAR1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_vmidmt_nsgfar1_s +{ + u32 gfea1 : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_vmidmt_nsgfar1_u +{ + struct ipa_hwio_def_ipa_vmidmt_nsgfar1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_VMIDMT_NSGFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_vmidmt_nsgfsr_s +{ + u32 reserved0 : 1; + u32 usf : 1; + u32 smcf : 1; + u32 reserved1 : 2; + u32 caf : 1; + u32 reserved2 : 1; + u32 pf : 1; + u32 reserved3 : 22; + u32 multi_cfg : 1; + u32 multi_client : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_vmidmt_nsgfsr_u +{ + struct ipa_hwio_def_ipa_vmidmt_nsgfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_VMIDMT_NSGFSRRESTORE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_vmidmt_nsgfsrrestore_s +{ + u32 reserved0 : 1; + u32 usf : 1; + u32 smcf : 1; + u32 reserved1 : 2; + u32 caf : 1; + u32 reserved2 : 1; + u32 pf : 1; + u32 reserved3 : 22; + u32 multi_cfg : 1; + u32 multi_client : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_vmidmt_nsgfsrrestore_u +{ + struct ipa_hwio_def_ipa_vmidmt_nsgfsrrestore_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_VMIDMT_NSGFSYNDR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_vmidmt_nsgfsyndr0_s +{ + u32 reserved0 : 1; + u32 wnr : 1; + u32 reserved1 : 2; + u32 nsstate : 1; + u32 nsattr : 1; + u32 reserved2 : 2; + u32 mssselfauth : 1; + u32 reserved3 : 23; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_vmidmt_nsgfsyndr0_u +{ + struct ipa_hwio_def_ipa_vmidmt_nsgfsyndr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_VMIDMT_NSGFSYNDR1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_vmidmt_nsgfsyndr1_s +{ + u32 streamindex : 8; + u32 reserved0 : 8; + u32 ssdindex : 8; + u32 msdindex : 7; + u32 reserved1 : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_vmidmt_nsgfsyndr1_u +{ + struct ipa_hwio_def_ipa_vmidmt_nsgfsyndr1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_VMIDMT_NSGFSYNDR2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_vmidmt_nsgfsyndr2_s +{ + u32 amid : 8; + u32 apid : 5; + u32 abid : 3; + u32 avmid : 5; + u32 reserved0 : 3; + u32 atid : 5; + u32 reserved1 : 3; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_vmidmt_nsgfsyndr2_u +{ + struct ipa_hwio_def_ipa_vmidmt_nsgfsyndr2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_VMIDMT_NSVMIDMTCR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_vmidmt_nsvmidmtcr0_s +{ + u32 clkonoffe : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_vmidmt_nsvmidmtcr0_u +{ + struct ipa_hwio_def_ipa_vmidmt_nsvmidmtcr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_VMIDMT_SSDR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_vmidmt_ssdr0_s +{ + u32 rwe : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_vmidmt_ssdr0_u +{ + struct ipa_hwio_def_ipa_vmidmt_ssdr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_VMIDMT_SSDR1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_vmidmt_ssdr1_s +{ + u32 rwe : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_vmidmt_ssdr1_u +{ + struct ipa_hwio_def_ipa_vmidmt_ssdr1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_VMIDMT_SSDR2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_vmidmt_ssdr2_s +{ + u32 rwe : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_vmidmt_ssdr2_u +{ + struct ipa_hwio_def_ipa_vmidmt_ssdr2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_VMIDMT_SSDR3 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_vmidmt_ssdr3_s +{ + u32 rwe : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_vmidmt_ssdr3_u +{ + struct ipa_hwio_def_ipa_vmidmt_ssdr3_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_VMIDMT_MSDR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_vmidmt_msdr0_s +{ + u32 rwe : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_vmidmt_msdr0_u +{ + struct ipa_hwio_def_ipa_vmidmt_msdr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_VMIDMT_MSDR1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_vmidmt_msdr1_s +{ + u32 rwe : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_vmidmt_msdr1_u +{ + struct ipa_hwio_def_ipa_vmidmt_msdr1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_VMIDMT_MSDR2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_vmidmt_msdr2_s +{ + u32 rwe : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_vmidmt_msdr2_u +{ + struct ipa_hwio_def_ipa_vmidmt_msdr2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_VMIDMT_MSDR3 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_vmidmt_msdr3_s +{ + u32 rwe : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_vmidmt_msdr3_u +{ + struct ipa_hwio_def_ipa_vmidmt_msdr3_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_VMIDMT_MCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_vmidmt_mcr_s +{ + u32 bpsmsacfg : 1; + u32 bpmsacfg : 1; + u32 clkonoffe : 1; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_vmidmt_mcr_u +{ + struct ipa_hwio_def_ipa_vmidmt_mcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_VMIDMT_S2VRn +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_vmidmt_s2vrn_s +{ + u32 vmid : 5; + u32 reserved0 : 3; + u32 shcfg : 2; + u32 reserved1 : 1; + u32 mtcfg : 1; + u32 memattr : 3; + u32 reserved2 : 1; + u32 type : 2; + u32 nscfg : 2; + u32 racfg : 2; + u32 wacfg : 2; + u32 reserved3 : 4; + u32 transientcfg : 2; + u32 reserved4 : 2; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_vmidmt_s2vrn_u +{ + struct ipa_hwio_def_ipa_vmidmt_s2vrn_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_VMIDMT_AS2VRn +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_vmidmt_as2vrn_s +{ + u32 reqpriority : 2; + u32 reserved0 : 2; + u32 reqprioritycfg : 1; + u32 reserved1 : 23; + u32 rcosh : 1; + u32 rcish : 1; + u32 rcnsh : 1; + u32 reserved2 : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_vmidmt_as2vrn_u +{ + struct ipa_hwio_def_ipa_vmidmt_as2vrn_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_VMIDMT_SMRn +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_vmidmt_smrn_s +{ + u32 id : 8; + u32 reserved0 : 8; + u32 mask : 8; + u32 reserved1 : 7; + u32 valid : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_vmidmt_smrn_u +{ + struct ipa_hwio_def_ipa_vmidmt_smrn_s def; + u32 value; +}; + +/*---------------------------------------------------------------------------- + * MODULE: IPA_0_GSI_TOP + *--------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------- + * MODULE: IPA_GSI_TOP_GSI + *--------------------------------------------------------------------------*/ + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_cfg_s +{ + u32 gsi_enable : 1; + u32 mcs_enable : 1; + u32 double_mcs_clk_freq : 1; + u32 uc_is_mcs : 1; + u32 gsi_pwr_clps : 1; + u32 bp_mtrix_disable : 1; + u32 reserved0 : 2; + u32 sleep_clk_div : 4; + u32 reserved1 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_cfg_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_MANAGER_MCS_CODE_VER +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_manager_mcs_code_ver_s +{ + u32 ver : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_manager_mcs_code_ver_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_manager_mcs_code_ver_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_ZEROS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_zeros_s +{ + u32 zeros : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_zeros_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_zeros_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_PERIPH_BASE_ADDR_LSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_periph_base_addr_lsb_s +{ + u32 base_addr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_periph_base_addr_lsb_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_periph_base_addr_lsb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_PERIPH_BASE_ADDR_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_periph_base_addr_msb_s +{ + u32 base_addr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_periph_base_addr_msb_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_periph_base_addr_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_CGC_CTRL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_cgc_ctrl_s +{ + u32 region_1_hw_cgc_en : 1; + u32 region_2_hw_cgc_en : 1; + u32 region_3_hw_cgc_en : 1; + u32 region_4_hw_cgc_en : 1; + u32 region_5_hw_cgc_en : 1; + u32 region_6_hw_cgc_en : 1; + u32 region_7_hw_cgc_en : 1; + u32 region_8_hw_cgc_en : 1; + u32 region_9_hw_cgc_en : 1; + u32 region_10_hw_cgc_en : 1; + u32 region_11_hw_cgc_en : 1; + u32 region_12_hw_cgc_en : 1; + u32 region_13_hw_cgc_en : 1; + u32 region_14_hw_cgc_en : 1; + u32 region_15_hw_cgc_en : 1; + u32 region_16_hw_cgc_en : 1; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_cgc_ctrl_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_cgc_ctrl_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_MOQA_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_moqa_cfg_s +{ + u32 client_req_prio : 8; + u32 client_oord : 8; + u32 client_oowr : 8; + u32 reserved0 : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_moqa_cfg_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_moqa_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_REE_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_ree_cfg_s +{ + u32 move_to_esc_clr_mode_trsh : 1; + u32 channel_empty_int_enable : 1; + u32 reserved0 : 6; + u32 max_burst_size : 8; + u32 reserved1 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_ree_cfg_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_ree_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_PERIPH_PENDING_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_periph_pending_k_s +{ + u32 chid_bit_map : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_periph_pending_k_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_periph_pending_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_MSI_CACHEATTR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_msi_cacheattr_s +{ + u32 ashared : 1; + u32 ainnershared : 1; + u32 anoallocate : 1; + u32 atransient : 1; + u32 areqpriority : 2; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_msi_cacheattr_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_msi_cacheattr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_EVENT_CACHEATTR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_event_cacheattr_s +{ + u32 ashared : 1; + u32 ainnershared : 1; + u32 anoallocate : 1; + u32 atransient : 1; + u32 areqpriority : 2; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_event_cacheattr_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_event_cacheattr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_DATA_CACHEATTR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_data_cacheattr_s +{ + u32 ashared : 1; + u32 ainnershared : 1; + u32 anoallocate : 1; + u32 atransient : 1; + u32 areqpriority : 2; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_data_cacheattr_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_data_cacheattr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_TRE_CACHEATTR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_tre_cacheattr_s +{ + u32 ashared : 1; + u32 ainnershared : 1; + u32 anoallocate : 1; + u32 atransient : 1; + u32 areqpriority : 2; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_tre_cacheattr_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_tre_cacheattr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_IC_INT_WEIGHT_REE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ic_int_weight_ree_s +{ + u32 stop_ch_comp_int_weight : 4; + u32 new_re_int_weight : 4; + u32 ch_empty_int_weight : 4; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ic_int_weight_ree_u +{ + struct ipa_hwio_def_ipa_gsi_top_ic_int_weight_ree_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_IC_INT_WEIGHT_EVT_ENG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ic_int_weight_evt_eng_s +{ + u32 evnt_eng_int_weight : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ic_int_weight_evt_eng_u +{ + struct ipa_hwio_def_ipa_gsi_top_ic_int_weight_evt_eng_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_IC_INT_WEIGHT_INT_ENG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ic_int_weight_int_eng_s +{ + u32 int_eng_int_weight : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ic_int_weight_int_eng_u +{ + struct ipa_hwio_def_ipa_gsi_top_ic_int_weight_int_eng_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_IC_INT_WEIGHT_CSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ic_int_weight_csr_s +{ + u32 ch_cmd_int_weight : 4; + u32 ee_generic_int_weight : 4; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ic_int_weight_csr_u +{ + struct ipa_hwio_def_ipa_gsi_top_ic_int_weight_csr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_IC_INT_WEIGHT_TLV_ENG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ic_int_weight_tlv_eng_s +{ + u32 tlv_0_int_weight : 4; + u32 tlv_1_int_weight : 4; + u32 tlv_2_int_weight : 4; + u32 ch_not_full_int_weight : 4; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ic_int_weight_tlv_eng_u +{ + struct ipa_hwio_def_ipa_gsi_top_ic_int_weight_tlv_eng_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_IC_INT_WEIGHT_TIMER_ENG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ic_int_weight_timer_eng_s +{ + u32 timer_int_weight : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ic_int_weight_timer_eng_u +{ + struct ipa_hwio_def_ipa_gsi_top_ic_int_weight_timer_eng_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_IC_INT_WEIGHT_DB_ENG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ic_int_weight_db_eng_s +{ + u32 new_db_int_weight : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ic_int_weight_db_eng_u +{ + struct ipa_hwio_def_ipa_gsi_top_ic_int_weight_db_eng_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_IC_INT_WEIGHT_RD_WR_ENG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ic_int_weight_rd_wr_eng_s +{ + u32 read_int_weight : 4; + u32 write_int_weight : 4; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ic_int_weight_rd_wr_eng_u +{ + struct ipa_hwio_def_ipa_gsi_top_ic_int_weight_rd_wr_eng_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_IC_INT_WEIGHT_UCONTROLLER_ENG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ic_int_weight_ucontroller_eng_s +{ + u32 ucontroller_gp_int_weight : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ic_int_weight_ucontroller_eng_u +{ + struct ipa_hwio_def_ipa_gsi_top_ic_int_weight_ucontroller_eng_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_LOW_LATENCY_ARB_WEIGHT +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_low_latency_arb_weight_s +{ + u32 ll_weight : 6; + u32 reserved0 : 2; + u32 non_ll_weight : 6; + u32 reserved1 : 2; + u32 ll_non_ll_fix_priority : 1; + u32 reserved2 : 15; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_low_latency_arb_weight_u +{ + struct ipa_hwio_def_ipa_gsi_top_low_latency_arb_weight_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_manager_ee_qos_n_s +{ + u32 ee_prio : 2; + u32 reserved0 : 6; + u32 max_ch_alloc : 8; + u32 max_ev_alloc : 8; + u32 reserved1 : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_manager_ee_qos_n_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_manager_ee_qos_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_ch_cntxt_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_ch_cntxt_base_addr_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_ch_cntxt_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_ev_cntxt_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_ev_cntxt_base_addr_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_ev_cntxt_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_re_storage_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_re_storage_base_addr_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_re_storage_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_re_esc_buf_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_re_esc_buf_base_addr_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_re_esc_buf_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_ee_scrach_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_ee_scrach_base_addr_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_ee_scrach_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_func_stack_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_func_stack_base_addr_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_func_stack_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_mcs_scratch_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_mcs_scratch_base_addr_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_mcs_scratch_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_mcs_scratch1_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_mcs_scratch1_base_addr_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_mcs_scratch1_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_mcs_scratch2_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_mcs_scratch2_base_addr_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_mcs_scratch2_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_mcs_scratch3_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_mcs_scratch3_base_addr_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_mcs_scratch3_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_ch_vp_trans_table_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_ch_vp_trans_table_base_addr_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_ch_vp_trans_table_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_ev_vp_trans_table_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_ev_vp_trans_table_base_addr_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_ev_vp_trans_table_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_user_info_data_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_user_info_data_base_addr_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_user_info_data_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_ee_cmd_fifo_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_ee_cmd_fifo_base_addr_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_ee_cmd_fifo_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_ch_cmd_fifo_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_ch_cmd_fifo_base_addr_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_ch_cmd_fifo_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_eve_ed_storage_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_eve_ed_storage_base_addr_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_eve_ed_storage_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ch_cmd_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ch_cmd_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ch_cmd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ee_generic_cmd_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ee_generic_cmd_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ee_generic_cmd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_IRAM_PTR_TLV_CH_NOT_FULL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_tlv_ch_not_full_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_tlv_ch_not_full_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_tlv_ch_not_full_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_IRAM_PTR_MSI_DB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_msi_db_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_msi_db_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_msi_db_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ch_db_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ch_db_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ch_db_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ev_db_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ev_db_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ev_db_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_new_re_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_new_re_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_new_re_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ch_dis_comp_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ch_dis_comp_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ch_dis_comp_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ch_empty_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ch_empty_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ch_empty_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_event_gen_comp_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_event_gen_comp_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_event_gen_comp_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_periph_if_tlv_in_0_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_periph_if_tlv_in_0_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_periph_if_tlv_in_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_periph_if_tlv_in_2_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_periph_if_tlv_in_2_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_periph_if_tlv_in_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_periph_if_tlv_in_1_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_periph_if_tlv_in_1_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_periph_if_tlv_in_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_timer_expired_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_timer_expired_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_timer_expired_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_write_eng_comp_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_write_eng_comp_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_write_eng_comp_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_read_eng_comp_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_read_eng_comp_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_read_eng_comp_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_uc_gp_int_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_uc_gp_int_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_uc_gp_int_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPED +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_int_mod_stoped_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_int_mod_stoped_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_int_mod_stoped_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_IRAM_PTR_INT_NOTIFY_MCS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_int_notify_mcs_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_int_notify_mcs_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_int_notify_mcs_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_INST_RAM_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_inst_ram_n_s +{ + u32 inst_byte_0 : 8; + u32 inst_byte_1 : 8; + u32 inst_byte_2 : 8; + u32 inst_byte_3 : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_inst_ram_n_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_inst_ram_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_SHRAM_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_shram_n_s +{ + u32 shram : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_shram_n_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_shram_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_map_ee_n_ch_k_vp_table_s +{ + u32 phy_ch : 8; + u32 valid : 1; + u32 reserved0 : 23; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_map_ee_n_ch_k_vp_table_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_map_ee_n_ch_k_vp_table_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_TEST_BUS_SEL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_test_bus_sel_s +{ + u32 gsi_testbus_sel : 8; + u32 reserved0 : 8; + u32 gsi_hw_events_sel : 4; + u32 reserved1 : 12; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_test_bus_sel_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_test_bus_sel_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_TEST_BUS_REG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_test_bus_reg_s +{ + u32 gsi_testbus_reg : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_test_bus_reg_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_test_bus_reg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_DEBUG_BUSY_REG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_debug_busy_reg_s +{ + u32 csr_busy : 1; + u32 ree_busy : 1; + u32 mcs_busy : 1; + u32 timer_busy : 1; + u32 rd_wr_busy : 1; + u32 ev_eng_busy : 1; + u32 int_eng_busy : 1; + u32 ree_pwr_clps_busy : 1; + u32 db_eng_busy : 1; + u32 dbg_cnt_busy : 1; + u32 uc_busy : 1; + u32 ic_busy : 1; + u32 sdma_busy : 1; + u32 reserved0 : 19; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_debug_busy_reg_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_busy_reg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_DEBUG_EVENT_PENDING_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_debug_event_pending_k_s +{ + u32 chid_bit_map : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_debug_event_pending_k_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_event_pending_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_DEBUG_TIMER_PENDING_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_debug_timer_pending_k_s +{ + u32 chid_bit_map : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_debug_timer_pending_k_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_timer_pending_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_debug_rd_wr_pending_k_s +{ + u32 chid_bit_map : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_debug_rd_wr_pending_k_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_rd_wr_pending_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_SPARE_REG_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_spare_reg_1_s +{ + u32 fix_ieob_wrong_msk_disable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_spare_reg_1_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_spare_reg_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_debug_pc_from_sw_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_debug_pc_from_sw_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_pc_from_sw_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_DEBUG_SW_STALL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_debug_sw_stall_s +{ + u32 mcs_stall : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_debug_sw_stall_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_sw_stall_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_debug_pc_for_debug_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_debug_pc_for_debug_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_pc_for_debug_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_SEL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_debug_qsb_log_sel_s +{ + u32 sel_write : 1; + u32 reserved0 : 7; + u32 sel_tid : 8; + u32 sel_mid : 8; + u32 reserved1 : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_debug_qsb_log_sel_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_qsb_log_sel_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_CLR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_debug_qsb_log_clr_s +{ + u32 log_clr : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_debug_qsb_log_clr_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_qsb_log_clr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_debug_qsb_log_err_trns_id_s +{ + u32 err_write : 1; + u32 reserved0 : 7; + u32 err_tid : 8; + u32 err_mid : 8; + u32 err_saved : 1; + u32 reserved1 : 7; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_debug_qsb_log_err_trns_id_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_qsb_log_err_trns_id_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_debug_qsb_log_0_s +{ + u32 addr_31_0 : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_debug_qsb_log_0_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_qsb_log_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_debug_qsb_log_1_s +{ + u32 addr_43_32 : 12; + u32 ainnershared : 1; + u32 anoallocate : 1; + u32 ashared : 1; + u32 acacheable : 1; + u32 atransient : 1; + u32 aooord : 1; + u32 aooowr : 1; + u32 reserved0 : 1; + u32 alen : 4; + u32 asize : 4; + u32 areqpriority : 4; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_debug_qsb_log_1_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_qsb_log_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_debug_qsb_log_2_s +{ + u32 ammusid : 12; + u32 amemtype : 4; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_debug_qsb_log_2_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_qsb_log_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_debug_qsb_log_last_misc_idn_s +{ + u32 addr_20_0 : 21; + u32 write : 1; + u32 tid : 5; + u32 mid : 5; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_debug_qsb_log_last_misc_idn_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_qsb_log_last_misc_idn_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_WRITE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_debug_sw_rf_n_write_s +{ + u32 data_in : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_debug_sw_rf_n_write_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_sw_rf_n_write_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_READ +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_debug_sw_rf_n_read_s +{ + u32 rf_reg : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_debug_sw_rf_n_read_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_sw_rf_n_read_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_DEBUG_COUNTER_CFGn +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_debug_counter_cfgn_s +{ + u32 enable : 1; + u32 stop_at_wrap_arnd : 1; + u32 clr_at_read : 1; + u32 evnt_type : 5; + u32 ee : 4; + u32 virtual_chnl : 8; + u32 chain : 1; + u32 reserved0 : 11; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_debug_counter_cfgn_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_counter_cfgn_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_DEBUG_COUNTERn +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_debug_countern_s +{ + u32 counter_value : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_debug_countern_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_countern_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_DEBUG_SW_MSK_REG_n_SEC_k_WR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_debug_sw_msk_reg_n_sec_k_wr_s +{ + u32 data_in : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_debug_sw_msk_reg_n_sec_k_wr_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_sw_msk_reg_n_sec_k_wr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_debug_sw_msk_reg_n_sec_k_rd_s +{ + u32 msk_reg : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_debug_sw_msk_reg_n_sec_k_rd_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_sw_msk_reg_n_sec_k_rd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_debug_ee_n_ch_k_vp_table_s +{ + u32 phy_ch : 8; + u32 valid : 1; + u32 reserved0 : 23; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_debug_ee_n_ch_k_vp_table_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_ee_n_ch_k_vp_table_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_debug_ee_n_ev_k_vp_table_s +{ + u32 phy_ev_ch : 8; + u32 valid : 1; + u32 reserved0 : 23; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_debug_ee_n_ev_k_vp_table_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_ee_n_ev_k_vp_table_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_debug_ree_prefetch_buf_ch_id_s +{ + u32 prefetch_buf_ch_id : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_debug_ree_prefetch_buf_ch_id_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_ree_prefetch_buf_ch_id_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_DEBUG_REE_PREFETCH_BUF_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_debug_ree_prefetch_buf_status_s +{ + u32 prefetch_buf_status : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_debug_ree_prefetch_buf_status_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_ree_prefetch_buf_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_MCS_PROFILING_BP_CNT_LSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_mcs_profiling_bp_cnt_lsb_s +{ + u32 bp_cnt_lsb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_mcs_profiling_bp_cnt_lsb_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_mcs_profiling_bp_cnt_lsb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_MCS_PROFILING_BP_CNT_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_mcs_profiling_bp_cnt_msb_s +{ + u32 bp_cnt_msb : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_mcs_profiling_bp_cnt_msb_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_mcs_profiling_bp_cnt_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_mcs_profiling_bp_and_pending_cnt_lsb_s +{ + u32 bp_and_pending_cnt_lsb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_mcs_profiling_bp_and_pending_cnt_lsb_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_mcs_profiling_bp_and_pending_cnt_lsb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_mcs_profiling_bp_and_pending_cnt_msb_s +{ + u32 bp_and_pending_cnt_msb : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_mcs_profiling_bp_and_pending_cnt_msb_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_mcs_profiling_bp_and_pending_cnt_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_mcs_profiling_mcs_busy_cnt_lsb_s +{ + u32 mcs_busy_cnt_lsb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_mcs_profiling_mcs_busy_cnt_lsb_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_mcs_profiling_mcs_busy_cnt_lsb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_mcs_profiling_mcs_busy_cnt_msb_s +{ + u32 mcs_busy_cnt_msb : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_mcs_profiling_mcs_busy_cnt_msb_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_mcs_profiling_mcs_busy_cnt_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_mcs_profiling_mcs_idle_cnt_lsb_s +{ + u32 mcs_idle_cnt_lsb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_mcs_profiling_mcs_idle_cnt_lsb_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_mcs_profiling_mcs_idle_cnt_lsb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_mcs_profiling_mcs_idle_cnt_msb_s +{ + u32 mcs_idle_cnt_msb : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_mcs_profiling_mcs_idle_cnt_msb_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_mcs_profiling_mcs_idle_cnt_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_0_s +{ + u32 chtype_protocol : 7; + u32 chtype_dir : 1; + u32 ee : 4; + u32 chid : 8; + u32 chstate : 4; + u32 element_size : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_0_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_1_s +{ + u32 r_length : 24; + u32 erindex : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_1_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_2_s +{ + u32 r_base_addr_lsbs : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_2_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_3_s +{ + u32 r_base_addr_msbs : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_3_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_3_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_4_s +{ + u32 read_ptr_lsb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_4_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_4_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_5_s +{ + u32 read_ptr_msb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_5_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_5_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_6_s +{ + u32 write_ptr_lsb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_6_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_6_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_7_s +{ + u32 write_ptr_msb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_7_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_7_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_8 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_8_s +{ + u32 db_msi_data : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_8_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_8_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_elem_size_shift_s +{ + u32 elem_size_shift : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_elem_size_shift_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_elem_size_shift_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_ch_almst_empty_thrshold_s +{ + u32 ch_almst_empty_thrshold : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_ch_almst_empty_thrshold_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_ch_almst_empty_thrshold_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_re_fetch_read_ptr_s +{ + u32 read_ptr : 24; + u32 reserved0 : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_re_fetch_read_ptr_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_re_fetch_read_ptr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_re_fetch_write_ptr_s +{ + u32 re_intr_db : 24; + u32 reserved0 : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_re_fetch_write_ptr_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_re_fetch_write_ptr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_GSI_CH_k_QOS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_qos_s +{ + u32 wrr_weight : 4; + u32 reserved0 : 4; + u32 max_prefetch : 1; + u32 use_db_eng : 1; + u32 prefetch_mode : 4; + u32 reserved1 : 2; + u32 empty_lvl_thrshold : 8; + u32 db_in_bytes : 1; + u32 low_latency_en : 1; + u32 reserved2 : 6; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_qos_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_qos_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_0_s +{ + u32 scratch : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_0_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_1_s +{ + u32 scratch : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_1_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_2_s +{ + u32 scratch : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_2_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_3_s +{ + u32 scratch : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_3_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_3_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_4 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_4_s +{ + u32 scratch : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_4_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_4_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_5 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_5_s +{ + u32 scratch : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_5_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_5_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_6 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_6_s +{ + u32 scratch : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_6_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_6_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_7 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_7_s +{ + u32 scratch : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_7_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_7_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_8 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_8_s +{ + u32 scratch : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_8_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_8_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_9 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_9_s +{ + u32 scratch : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_9_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_9_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_db_eng_write_ptr_s +{ + u32 last_db_2_mcs : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_db_eng_write_ptr_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_db_eng_write_ptr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_0_s +{ + u32 chtype : 7; + u32 intype : 1; + u32 evchid : 8; + u32 ee : 4; + u32 chstate : 4; + u32 element_size : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_0_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_1_s +{ + u32 r_length : 24; + u32 reserved0 : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_1_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_2_s +{ + u32 r_base_addr_lsbs : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_2_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_3_s +{ + u32 r_base_addr_msbs : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_3_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_3_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_4_s +{ + u32 read_ptr_lsb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_4_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_4_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_5 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_5_s +{ + u32 read_ptr_msb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_5_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_5_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_6 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_6_s +{ + u32 write_ptr_lsb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_6_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_6_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_7 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_7_s +{ + u32 write_ptr_msb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_7_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_7_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_8_s +{ + u32 int_modt : 16; + u32 int_modc : 8; + u32 int_mod_cnt : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_8_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_8_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_9_s +{ + u32 intvec : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_9_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_9_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_10_s +{ + u32 msi_addr_lsb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_10_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_10_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_11_s +{ + u32 msi_addr_msb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_11_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_11_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_12_s +{ + u32 rp_update_addr_lsb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_12_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_12_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_13_s +{ + u32 rp_update_addr_msb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_13_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_13_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_EV_CH_k_ELEM_SIZE_SHIFT +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_elem_size_shift_s +{ + u32 elem_size_shift : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_elem_size_shift_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_elem_size_shift_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_scratch_0_s +{ + u32 scratch : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_scratch_0_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_scratch_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_scratch_1_s +{ + u32 scratch : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_scratch_1_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_scratch_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_scratch_2_s +{ + u32 scratch : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_scratch_2_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_scratch_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_doorbell_0_s +{ + u32 write_ptr_lsb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_doorbell_0_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_doorbell_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_doorbell_1_s +{ + u32 write_ptr_msb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_doorbell_1_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_doorbell_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_EV_CH_k_DOORBELL_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_doorbell_0_s +{ + u32 write_ptr_lsb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_doorbell_0_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_doorbell_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_EV_CH_k_DOORBELL_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_doorbell_1_s +{ + u32 write_ptr_msb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_doorbell_1_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_doorbell_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_GSI_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_status_s +{ + u32 enabled : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_status_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_GSI_CH_CMD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_cmd_s +{ + u32 chid : 8; + u32 reserved0 : 16; + u32 opcode : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_cmd_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_cmd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_EV_CH_CMD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_cmd_s +{ + u32 chid : 8; + u32 reserved0 : 16; + u32 opcode : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_cmd_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_cmd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_GSI_EE_GENERIC_CMD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ee_generic_cmd_s +{ + u32 opcode : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ee_generic_cmd_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ee_generic_cmd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_GSI_HW_PARAM_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_hw_param_0_s +{ + u32 gsi_ev_ch_num : 8; + u32 gsi_ch_num : 8; + u32 num_ees : 5; + u32 periph_conf_addr_bus_w : 5; + u32 periph_sec_grp : 5; + u32 use_axi_m : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_hw_param_0_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_hw_param_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_GSI_HW_PARAM_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_hw_param_1_s +{ + u32 gsi_m_data_bus_w : 8; + u32 gsi_num_qad : 4; + u32 gsi_nonsec_en : 4; + u32 gsi_sec_en : 1; + u32 gsi_vmidacr_en : 1; + u32 gsi_qrib_en : 1; + u32 gsi_use_xpu : 1; + u32 gsi_num_timers : 5; + u32 gsi_use_bp_mtrix : 1; + u32 gsi_use_db_eng : 1; + u32 gsi_use_uc_if : 1; + u32 gsi_escape_buf_only : 1; + u32 gsi_simple_rd_wr : 1; + u32 gsi_blk_int_access_region_1_en : 1; + u32 gsi_blk_int_access_region_2_en : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_hw_param_1_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_hw_param_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_GSI_HW_PARAM_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_hw_param_2_s +{ + u32 gsi_num_ch_per_ee : 8; + u32 gsi_iram_size : 5; + u32 gsi_ch_pend_translate : 1; + u32 gsi_ch_full_logic : 1; + u32 gsi_use_sdma : 1; + u32 gsi_sdma_n_int : 3; + u32 gsi_sdma_max_burst : 8; + u32 gsi_sdma_n_iovec : 3; + u32 gsi_use_rd_wr_eng : 1; + u32 gsi_use_inter_ee : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_hw_param_2_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_hw_param_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_GSI_SW_VERSION +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_sw_version_s +{ + u32 step : 16; + u32 minor : 12; + u32 major : 4; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_sw_version_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_sw_version_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_GSI_MCS_CODE_VER +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_mcs_code_ver_s +{ + u32 ver : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_mcs_code_ver_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_mcs_code_ver_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_GSI_HW_PARAM_3 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_hw_param_3_s +{ + u32 gsi_sdma_max_os_rd : 4; + u32 gsi_sdma_max_os_wr : 4; + u32 gsi_num_prefetch_bufs : 4; + u32 gsi_m_addr_bus_w : 8; + u32 gsi_ree_max_burst_len : 5; + u32 gsi_use_irom : 1; + u32 gsi_use_vir_ch_if : 1; + u32 gsi_use_sleep_clk_div : 1; + u32 gsi_use_db_msi_mode : 1; + u32 reserved0 : 3; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_hw_param_3_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_hw_param_3_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_GSI_HW_PARAM_4 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_hw_param_4_s +{ + u32 gsi_num_ev_per_ee : 8; + u32 gsi_iram_protcol_cnt : 8; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_hw_param_4_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_hw_param_4_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_type_irq_s +{ + u32 ch_ctrl : 1; + u32 ev_ctrl : 1; + u32 glob_ee : 1; + u32 ieob : 1; + u32 inter_ee_ch_ctrl : 1; + u32 inter_ee_ev_ctrl : 1; + u32 general : 1; + u32 reserved0 : 25; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_type_irq_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_type_irq_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_type_irq_msk_s +{ + u32 ch_ctrl : 1; + u32 ev_ctrl : 1; + u32 glob_ee : 1; + u32 ieob : 1; + u32 inter_ee_ch_ctrl : 1; + u32 inter_ee_ev_ctrl : 1; + u32 general : 1; + u32 reserved0 : 25; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_type_irq_msk_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_type_irq_msk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_gsi_ch_irq_k_s +{ + u32 gsi_ch_bit_map : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_gsi_ch_irq_k_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_gsi_ch_irq_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_gsi_ch_irq_msk_k_s +{ + u32 gsi_ch_bit_map_msk : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_gsi_ch_irq_msk_k_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_gsi_ch_irq_msk_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_gsi_ch_irq_clr_k_s +{ + u32 gsi_ch_bit_map : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_gsi_ch_irq_clr_k_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_gsi_ch_irq_clr_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ev_ch_irq_k_s +{ + u32 ev_ch_bit_map : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ev_ch_irq_k_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ev_ch_irq_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ev_ch_irq_msk_k_s +{ + u32 ev_ch_bit_map_msk : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ev_ch_irq_msk_k_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ev_ch_irq_msk_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ev_ch_irq_clr_k_s +{ + u32 ev_ch_bit_map : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ev_ch_irq_clr_k_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ev_ch_irq_clr_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ieob_irq_k_s +{ + u32 ev_ch_bit_map : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ieob_irq_k_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ieob_irq_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ieob_irq_msk_k_s +{ + u32 ev_ch_bit_map_msk : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ieob_irq_msk_k_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ieob_irq_msk_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ieob_irq_clr_k_s +{ + u32 ev_ch_bit_map : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ieob_irq_clr_k_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ieob_irq_clr_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_glob_irq_stts_s +{ + u32 error_int : 1; + u32 gp_int1 : 1; + u32 gp_int2 : 1; + u32 gp_int3 : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_glob_irq_stts_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_glob_irq_stts_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_EN +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_glob_irq_en_s +{ + u32 error_int : 1; + u32 gp_int1 : 1; + u32 gp_int2 : 1; + u32 gp_int3 : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_glob_irq_en_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_glob_irq_en_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_CLR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_glob_irq_clr_s +{ + u32 error_int : 1; + u32 gp_int1 : 1; + u32 gp_int2 : 1; + u32 gp_int3 : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_glob_irq_clr_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_glob_irq_clr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_gsi_irq_stts_s +{ + u32 gsi_break_point : 1; + u32 gsi_bus_error : 1; + u32 gsi_cmd_fifo_ovrflow : 1; + u32 gsi_mcs_stack_ovrflow : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_gsi_irq_stts_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_gsi_irq_stts_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_EN +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_gsi_irq_en_s +{ + u32 gsi_break_point : 1; + u32 gsi_bus_error : 1; + u32 gsi_cmd_fifo_ovrflow : 1; + u32 gsi_mcs_stack_ovrflow : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_gsi_irq_en_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_gsi_irq_en_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_CLR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_gsi_irq_clr_s +{ + u32 gsi_break_point : 1; + u32 gsi_bus_error : 1; + u32 gsi_cmd_fifo_ovrflow : 1; + u32 gsi_mcs_stack_ovrflow : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_gsi_irq_clr_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_gsi_irq_clr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_CNTXT_INTSET +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_intset_s +{ + u32 intype : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_intset_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_intset_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_msi_base_lsb_s +{ + u32 msi_addr_lsb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_msi_base_lsb_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_msi_base_lsb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_msi_base_msb_s +{ + u32 msi_addr_msb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_msi_base_msb_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_msi_base_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_CNTXT_INT_VEC +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_int_vec_s +{ + u32 int_vec : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_int_vec_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_int_vec_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_ERROR_LOG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_error_log_s +{ + u32 error_log : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_error_log_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_error_log_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_ERROR_LOG_CLR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_error_log_clr_s +{ + u32 error_log_clr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_error_log_clr_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_error_log_clr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_scratch_0_s +{ + u32 scratch : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_scratch_0_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_scratch_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_scratch_1_s +{ + u32 scratch : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_scratch_1_u +{ + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_scratch_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_MCS_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_mcs_cfg_s +{ + u32 mcs_enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_mcs_cfg_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_mcs_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_TZ_FW_AUTH_LOCK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_tz_fw_auth_lock_s +{ + u32 dis_iram_write : 1; + u32 dis_debug_shram_write : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_tz_fw_auth_lock_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_tz_fw_auth_lock_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_MSA_FW_AUTH_LOCK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_msa_fw_auth_lock_s +{ + u32 dis_iram_write : 1; + u32 dis_debug_shram_write : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_msa_fw_auth_lock_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_msa_fw_auth_lock_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_GSI_SP_FW_AUTH_LOCK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_gsi_sp_fw_auth_lock_s +{ + u32 dis_iram_write : 1; + u32 dis_debug_shram_write : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_gsi_sp_fw_auth_lock_u +{ + struct ipa_hwio_def_ipa_gsi_top_gsi_sp_fw_auth_lock_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_INTER_EE_n_ORIGINATOR_EE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_inter_ee_n_originator_ee_s +{ + u32 ee_number : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_inter_ee_n_originator_ee_u +{ + struct ipa_hwio_def_ipa_gsi_top_inter_ee_n_originator_ee_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_INTER_EE_n_GSI_CH_CMD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_inter_ee_n_gsi_ch_cmd_s +{ + u32 chid : 8; + u32 reserved0 : 16; + u32 opcode : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_inter_ee_n_gsi_ch_cmd_u +{ + struct ipa_hwio_def_ipa_gsi_top_inter_ee_n_gsi_ch_cmd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_INTER_EE_n_EV_CH_CMD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_inter_ee_n_ev_ch_cmd_s +{ + u32 chid : 8; + u32 reserved0 : 16; + u32 opcode : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_inter_ee_n_ev_ch_cmd_u +{ + struct ipa_hwio_def_ipa_gsi_top_inter_ee_n_ev_ch_cmd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_inter_ee_n_src_gsi_ch_irq_k_s +{ + u32 gsi_ch_bit_map : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_inter_ee_n_src_gsi_ch_irq_k_u +{ + struct ipa_hwio_def_ipa_gsi_top_inter_ee_n_src_gsi_ch_irq_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_inter_ee_n_src_gsi_ch_irq_msk_k_s +{ + u32 gsi_ch_bit_map_msk : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_inter_ee_n_src_gsi_ch_irq_msk_k_u +{ + struct ipa_hwio_def_ipa_gsi_top_inter_ee_n_src_gsi_ch_irq_msk_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_inter_ee_n_src_gsi_ch_irq_clr_k_s +{ + u32 gsi_ch_bit_map : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_inter_ee_n_src_gsi_ch_irq_clr_k_u +{ + struct ipa_hwio_def_ipa_gsi_top_inter_ee_n_src_gsi_ch_irq_clr_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_inter_ee_n_src_ev_ch_irq_k_s +{ + u32 ev_ch_bit_map : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_inter_ee_n_src_ev_ch_irq_k_u +{ + struct ipa_hwio_def_ipa_gsi_top_inter_ee_n_src_ev_ch_irq_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_inter_ee_n_src_ev_ch_irq_msk_k_s +{ + u32 ev_ch_bit_map_msk : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_inter_ee_n_src_ev_ch_irq_msk_k_u +{ + struct ipa_hwio_def_ipa_gsi_top_inter_ee_n_src_ev_ch_irq_msk_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_CLR_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_inter_ee_n_src_ev_ch_irq_clr_k_s +{ + u32 ev_ch_bit_map : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_inter_ee_n_src_ev_ch_irq_clr_k_u +{ + struct ipa_hwio_def_ipa_gsi_top_inter_ee_n_src_ev_ch_irq_clr_k_s def; + u32 value; +}; + +/*---------------------------------------------------------------------------- + * MODULE: IPA_GSI_TOP_XPU3 + *--------------------------------------------------------------------------*/ + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_XPU3_GCR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_xpu3_gcr0_s +{ + u32 aaden : 1; + u32 aalog_mode_dis : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_xpu3_gcr0_u +{ + struct ipa_hwio_def_ipa_gsi_top_xpu3_gcr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_XPU3_SCR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_xpu3_scr0_s +{ + u32 scfgere : 1; + u32 sclere : 1; + u32 scfgeie : 1; + u32 scleie : 1; + u32 reserved0 : 4; + u32 dynamic_clk_en : 1; + u32 reserved1 : 23; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_xpu3_scr0_u +{ + struct ipa_hwio_def_ipa_gsi_top_xpu3_scr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_XPU3_CR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_xpu3_cr0_s +{ + u32 cfgere : 1; + u32 clere : 1; + u32 cfgeie : 1; + u32 cleie : 1; + u32 reserved0 : 3; + u32 vmiden : 1; + u32 dynamic_clk_en : 1; + u32 reserved1 : 23; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_xpu3_cr0_u +{ + struct ipa_hwio_def_ipa_gsi_top_xpu3_cr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_XPU3_RPU_ACR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_xpu3_rpu_acr0_s +{ + u32 suvmid : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_xpu3_rpu_acr0_u +{ + struct ipa_hwio_def_ipa_gsi_top_xpu3_rpu_acr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_XPU3_QAD0_GCR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_xpu3_qad0_gcr0_s +{ + u32 qad0den : 1; + u32 qad0log_mode_dis : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_xpu3_qad0_gcr0_u +{ + struct ipa_hwio_def_ipa_gsi_top_xpu3_qad0_gcr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_XPU3_QAD0_CR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_xpu3_qad0_cr0_s +{ + u32 cfgere : 1; + u32 clere : 1; + u32 cfgeie : 1; + u32 cleie : 1; + u32 reserved0 : 4; + u32 dynamic_clk_en : 1; + u32 reserved1 : 23; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_xpu3_qad0_cr0_u +{ + struct ipa_hwio_def_ipa_gsi_top_xpu3_qad0_cr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_XPU3_QAD1_GCR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_xpu3_qad1_gcr0_s +{ + u32 qad1den : 1; + u32 qad1log_mode_dis : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_xpu3_qad1_gcr0_u +{ + struct ipa_hwio_def_ipa_gsi_top_xpu3_qad1_gcr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_XPU3_QAD1_CR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_xpu3_qad1_cr0_s +{ + u32 cfgere : 1; + u32 clere : 1; + u32 cfgeie : 1; + u32 cleie : 1; + u32 reserved0 : 4; + u32 dynamic_clk_en : 1; + u32 reserved1 : 23; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_xpu3_qad1_cr0_u +{ + struct ipa_hwio_def_ipa_gsi_top_xpu3_qad1_cr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_XPU3_IDR3 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_xpu3_idr3_s +{ + u32 nvmid : 8; + u32 mv : 1; + u32 pt : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_xpu3_idr3_u +{ + struct ipa_hwio_def_ipa_gsi_top_xpu3_idr3_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_XPU3_IDR2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_xpu3_idr2_s +{ + u32 num_qad : 4; + u32 reserved0 : 4; + u32 vmidacr_en : 8; + u32 sec_en : 8; + u32 nonsec_en : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_xpu3_idr2_u +{ + struct ipa_hwio_def_ipa_gsi_top_xpu3_idr2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_XPU3_IDR1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_xpu3_idr1_s +{ + u32 reserved0 : 16; + u32 config_addr_width : 6; + u32 reserved1 : 2; + u32 client_addr_width : 6; + u32 reserved2 : 2; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_xpu3_idr1_u +{ + struct ipa_hwio_def_ipa_gsi_top_xpu3_idr1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_XPU3_IDR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_xpu3_idr0_s +{ + u32 xputype : 2; + u32 reserved0 : 3; + u32 clientreq_halt_ack_hw_en : 1; + u32 reserved1 : 10; + u32 nrg : 10; + u32 reserved2 : 6; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_xpu3_idr0_u +{ + struct ipa_hwio_def_ipa_gsi_top_xpu3_idr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_XPU3_REV +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_xpu3_rev_s +{ + u32 step : 16; + u32 minor : 12; + u32 major : 4; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_xpu3_rev_u +{ + struct ipa_hwio_def_ipa_gsi_top_xpu3_rev_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_XPU3_LOG_MODE_DIS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_xpu3_log_mode_dis_s +{ + u32 log_mode_dis : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_xpu3_log_mode_dis_u +{ + struct ipa_hwio_def_ipa_gsi_top_xpu3_log_mode_dis_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_XPU3_RGN_FREESTATUSr +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_xpu3_rgn_freestatusr_s +{ + u32 rgfreestatus : 21; + u32 reserved0 : 11; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_xpu3_rgn_freestatusr_u +{ + struct ipa_hwio_def_ipa_gsi_top_xpu3_rgn_freestatusr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_XPU3_SEAR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_xpu3_sear0_s +{ + u32 addr_31_0 : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_xpu3_sear0_u +{ + struct ipa_hwio_def_ipa_gsi_top_xpu3_sear0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_XPU3_SESR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_xpu3_sesr_s +{ + u32 cfg : 1; + u32 client : 1; + u32 cfgmulti : 1; + u32 clmulti : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_xpu3_sesr_u +{ + struct ipa_hwio_def_ipa_gsi_top_xpu3_sesr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_XPU3_SESRRESTORE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_xpu3_sesrrestore_s +{ + u32 cfg : 1; + u32 client : 1; + u32 cfgmulti : 1; + u32 clmulti : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_xpu3_sesrrestore_u +{ + struct ipa_hwio_def_ipa_gsi_top_xpu3_sesrrestore_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_XPU3_SESYNR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_xpu3_sesynr0_s +{ + u32 xprotns : 1; + u32 awrite : 1; + u32 xinst : 1; + u32 xpriv : 1; + u32 reserved0 : 4; + u32 qad : 8; + u32 alen : 8; + u32 asize : 3; + u32 reserved1 : 2; + u32 burstlen : 1; + u32 ac : 1; + u32 reserved2 : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_xpu3_sesynr0_u +{ + struct ipa_hwio_def_ipa_gsi_top_xpu3_sesynr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_XPU3_SESYNR1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_xpu3_sesynr1_s +{ + u32 mid : 8; + u32 pid : 5; + u32 bid : 3; + u32 vmid : 8; + u32 tid : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_xpu3_sesynr1_u +{ + struct ipa_hwio_def_ipa_gsi_top_xpu3_sesynr1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_XPU3_SESYNR2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_xpu3_sesynr2_s +{ + u32 memtype : 3; + u32 reserved0 : 4; + u32 transient : 1; + u32 noallocate : 1; + u32 ooowr : 1; + u32 ooord : 1; + u32 orderedwr : 1; + u32 orderedrd : 1; + u32 portmrel : 1; + u32 innerwritethrough : 1; + u32 innertransient : 1; + u32 innershared : 1; + u32 innercacheable : 1; + u32 innernoallocate : 1; + u32 writethrough : 1; + u32 shared : 1; + u32 full : 1; + u32 exclusive : 1; + u32 error : 1; + u32 earlywrresp : 1; + u32 device_type : 2; + u32 device : 1; + u32 cacheable : 1; + u32 burst : 1; + u32 bar : 2; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_xpu3_sesynr2_u +{ + struct ipa_hwio_def_ipa_gsi_top_xpu3_sesynr2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_XPU3_SEAR1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_xpu3_sear1_s +{ + u32 addr_63_32 : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_xpu3_sear1_u +{ + struct ipa_hwio_def_ipa_gsi_top_xpu3_sear1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_XPU3_EAR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_xpu3_ear0_s +{ + u32 addr_31_0 : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_xpu3_ear0_u +{ + struct ipa_hwio_def_ipa_gsi_top_xpu3_ear0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_XPU3_ESR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_xpu3_esr_s +{ + u32 cfg : 1; + u32 client : 1; + u32 cfgmulti : 1; + u32 clmulti : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_xpu3_esr_u +{ + struct ipa_hwio_def_ipa_gsi_top_xpu3_esr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_XPU3_ESRRESTORE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_xpu3_esrrestore_s +{ + u32 cfg : 1; + u32 client : 1; + u32 cfgmulti : 1; + u32 clmulti : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_xpu3_esrrestore_u +{ + struct ipa_hwio_def_ipa_gsi_top_xpu3_esrrestore_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_XPU3_ESYNR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_xpu3_esynr0_s +{ + u32 xprotns : 1; + u32 awrite : 1; + u32 xinst : 1; + u32 xpriv : 1; + u32 reserved0 : 4; + u32 qad : 8; + u32 alen : 8; + u32 asize : 3; + u32 reserved1 : 2; + u32 burstlen : 1; + u32 ac : 1; + u32 reserved2 : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_xpu3_esynr0_u +{ + struct ipa_hwio_def_ipa_gsi_top_xpu3_esynr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_XPU3_ESYNR1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_xpu3_esynr1_s +{ + u32 mid : 8; + u32 pid : 5; + u32 bid : 3; + u32 vmid : 8; + u32 tid : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_xpu3_esynr1_u +{ + struct ipa_hwio_def_ipa_gsi_top_xpu3_esynr1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_XPU3_ESYNR2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_xpu3_esynr2_s +{ + u32 memtype : 3; + u32 reserved0 : 4; + u32 transient : 1; + u32 noallocate : 1; + u32 ooowr : 1; + u32 ooord : 1; + u32 orderedwr : 1; + u32 orderedrd : 1; + u32 portmrel : 1; + u32 innerwritethrough : 1; + u32 innertransient : 1; + u32 innershared : 1; + u32 innercacheable : 1; + u32 innernoallocate : 1; + u32 writethrough : 1; + u32 shared : 1; + u32 full : 1; + u32 exclusive : 1; + u32 error : 1; + u32 earlywrresp : 1; + u32 device_type : 2; + u32 device : 1; + u32 cacheable : 1; + u32 burst : 1; + u32 bar : 2; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_xpu3_esynr2_u +{ + struct ipa_hwio_def_ipa_gsi_top_xpu3_esynr2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_XPU3_EAR1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_xpu3_ear1_s +{ + u32 addr_63_32 : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_xpu3_ear1_u +{ + struct ipa_hwio_def_ipa_gsi_top_xpu3_ear1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_XPU3_QAD0_EAR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_xpu3_qad0_ear0_s +{ + u32 addr_31_0 : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_xpu3_qad0_ear0_u +{ + struct ipa_hwio_def_ipa_gsi_top_xpu3_qad0_ear0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_XPU3_QAD0_ESR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_xpu3_qad0_esr_s +{ + u32 cfg : 1; + u32 client : 1; + u32 cfgmulti : 1; + u32 clmulti : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_xpu3_qad0_esr_u +{ + struct ipa_hwio_def_ipa_gsi_top_xpu3_qad0_esr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_XPU3_QAD0_ESRRESTORE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_xpu3_qad0_esrrestore_s +{ + u32 cfg : 1; + u32 client : 1; + u32 cfgmulti : 1; + u32 clmulti : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_xpu3_qad0_esrrestore_u +{ + struct ipa_hwio_def_ipa_gsi_top_xpu3_qad0_esrrestore_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_XPU3_QAD0_ESYNR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_xpu3_qad0_esynr0_s +{ + u32 xprotns : 1; + u32 awrite : 1; + u32 xinst : 1; + u32 xpriv : 1; + u32 reserved0 : 4; + u32 qad : 8; + u32 alen : 8; + u32 asize : 3; + u32 reserved1 : 2; + u32 burstlen : 1; + u32 ac : 1; + u32 reserved2 : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_xpu3_qad0_esynr0_u +{ + struct ipa_hwio_def_ipa_gsi_top_xpu3_qad0_esynr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_XPU3_QAD0_ESYNR1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_xpu3_qad0_esynr1_s +{ + u32 mid : 8; + u32 pid : 5; + u32 bid : 3; + u32 vmid : 8; + u32 tid : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_xpu3_qad0_esynr1_u +{ + struct ipa_hwio_def_ipa_gsi_top_xpu3_qad0_esynr1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_XPU3_QAD0_ESYNR2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_xpu3_qad0_esynr2_s +{ + u32 memtype : 3; + u32 reserved0 : 4; + u32 transient : 1; + u32 noallocate : 1; + u32 ooowr : 1; + u32 ooord : 1; + u32 orderedwr : 1; + u32 orderedrd : 1; + u32 portmrel : 1; + u32 innerwritethrough : 1; + u32 innertransient : 1; + u32 innershared : 1; + u32 innercacheable : 1; + u32 innernoallocate : 1; + u32 writethrough : 1; + u32 shared : 1; + u32 full : 1; + u32 exclusive : 1; + u32 error : 1; + u32 earlywrresp : 1; + u32 device_type : 2; + u32 device : 1; + u32 cacheable : 1; + u32 burst : 1; + u32 bar : 2; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_xpu3_qad0_esynr2_u +{ + struct ipa_hwio_def_ipa_gsi_top_xpu3_qad0_esynr2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_XPU3_QAD0_EAR1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_xpu3_qad0_ear1_s +{ + u32 addr_63_32 : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_xpu3_qad0_ear1_u +{ + struct ipa_hwio_def_ipa_gsi_top_xpu3_qad0_ear1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_XPU3_QAD1_EAR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_xpu3_qad1_ear0_s +{ + u32 addr_31_0 : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_xpu3_qad1_ear0_u +{ + struct ipa_hwio_def_ipa_gsi_top_xpu3_qad1_ear0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_XPU3_QAD1_ESR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_xpu3_qad1_esr_s +{ + u32 cfg : 1; + u32 client : 1; + u32 cfgmulti : 1; + u32 clmulti : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_xpu3_qad1_esr_u +{ + struct ipa_hwio_def_ipa_gsi_top_xpu3_qad1_esr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_XPU3_QAD1_ESRRESTORE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_xpu3_qad1_esrrestore_s +{ + u32 cfg : 1; + u32 client : 1; + u32 cfgmulti : 1; + u32 clmulti : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_xpu3_qad1_esrrestore_u +{ + struct ipa_hwio_def_ipa_gsi_top_xpu3_qad1_esrrestore_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_XPU3_QAD1_ESYNR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_xpu3_qad1_esynr0_s +{ + u32 xprotns : 1; + u32 awrite : 1; + u32 xinst : 1; + u32 xpriv : 1; + u32 reserved0 : 4; + u32 qad : 8; + u32 alen : 8; + u32 asize : 3; + u32 reserved1 : 2; + u32 burstlen : 1; + u32 ac : 1; + u32 reserved2 : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_xpu3_qad1_esynr0_u +{ + struct ipa_hwio_def_ipa_gsi_top_xpu3_qad1_esynr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_XPU3_QAD1_ESYNR1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_xpu3_qad1_esynr1_s +{ + u32 mid : 8; + u32 pid : 5; + u32 bid : 3; + u32 vmid : 8; + u32 tid : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_xpu3_qad1_esynr1_u +{ + struct ipa_hwio_def_ipa_gsi_top_xpu3_qad1_esynr1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_XPU3_QAD1_ESYNR2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_xpu3_qad1_esynr2_s +{ + u32 memtype : 3; + u32 reserved0 : 4; + u32 transient : 1; + u32 noallocate : 1; + u32 ooowr : 1; + u32 ooord : 1; + u32 orderedwr : 1; + u32 orderedrd : 1; + u32 portmrel : 1; + u32 innerwritethrough : 1; + u32 innertransient : 1; + u32 innershared : 1; + u32 innercacheable : 1; + u32 innernoallocate : 1; + u32 writethrough : 1; + u32 shared : 1; + u32 full : 1; + u32 exclusive : 1; + u32 error : 1; + u32 earlywrresp : 1; + u32 device_type : 2; + u32 device : 1; + u32 cacheable : 1; + u32 burst : 1; + u32 bar : 2; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_xpu3_qad1_esynr2_u +{ + struct ipa_hwio_def_ipa_gsi_top_xpu3_qad1_esynr2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_XPU3_QAD1_EAR1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_xpu3_qad1_ear1_s +{ + u32 addr_63_32 : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_xpu3_qad1_ear1_u +{ + struct ipa_hwio_def_ipa_gsi_top_xpu3_qad1_ear1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_XPU3_RGN_OWNERSTATUSr +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_xpu3_rgn_ownerstatusr_s +{ + u32 rgownerstatus : 21; + u32 reserved0 : 11; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_xpu3_rgn_ownerstatusr_u +{ + struct ipa_hwio_def_ipa_gsi_top_xpu3_rgn_ownerstatusr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_XPU3_RGn_GCR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_xpu3_rgn_gcr0_s +{ + u32 rg_owner : 3; + u32 reserved0 : 5; + u32 rg_sec_apps : 1; + u32 reserved1 : 23; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_xpu3_rgn_gcr0_u +{ + struct ipa_hwio_def_ipa_gsi_top_xpu3_rgn_gcr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_XPU3_RGn_GCR3 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_xpu3_rgn_gcr3_s +{ + u32 secure_access_lock : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_xpu3_rgn_gcr3_u +{ + struct ipa_hwio_def_ipa_gsi_top_xpu3_rgn_gcr3_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_XPU3_RGn_CR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_xpu3_rgn_cr0_s +{ + u32 rgsclrden_apps : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_xpu3_rgn_cr0_u +{ + struct ipa_hwio_def_ipa_gsi_top_xpu3_rgn_cr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_XPU3_RGn_CR1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_xpu3_rgn_cr1_s +{ + u32 rgclrden : 3; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_xpu3_rgn_cr1_u +{ + struct ipa_hwio_def_ipa_gsi_top_xpu3_rgn_cr1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_XPU3_RGn_CR2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_xpu3_rgn_cr2_s +{ + u32 rgsclwren_apps : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_xpu3_rgn_cr2_u +{ + struct ipa_hwio_def_ipa_gsi_top_xpu3_rgn_cr2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_XPU3_RGn_CR3 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_xpu3_rgn_cr3_s +{ + u32 rgclwren : 3; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_xpu3_rgn_cr3_u +{ + struct ipa_hwio_def_ipa_gsi_top_xpu3_rgn_cr3_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_XPU3_RGn_RACR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_xpu3_rgn_racr_s +{ + u32 re : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_xpu3_rgn_racr_u +{ + struct ipa_hwio_def_ipa_gsi_top_xpu3_rgn_racr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TOP_XPU3_RGn_WACR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_top_xpu3_rgn_wacr_s +{ + u32 we : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_top_xpu3_rgn_wacr_u +{ + struct ipa_hwio_def_ipa_gsi_top_xpu3_rgn_wacr_s def; + u32 value; +}; + +/*---------------------------------------------------------------------------- + * MODULE: IPA_MS_MPU_CFG_SNOC_IPA_MS_MPU_CFG + *--------------------------------------------------------------------------*/ + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_GCR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_gcr0_s +{ + u32 aaden : 1; + u32 aalog_mode_dis : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_gcr0_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_gcr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_SCR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_scr0_s +{ + u32 scfgere : 1; + u32 sclere : 1; + u32 scfgeie : 1; + u32 scleie : 1; + u32 reserved0 : 4; + u32 dynamic_clk_en : 1; + u32 reserved1 : 23; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_scr0_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_scr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_CR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_cr0_s +{ + u32 cfgere : 1; + u32 clere : 1; + u32 cfgeie : 1; + u32 cleie : 1; + u32 reserved0 : 4; + u32 dynamic_clk_en : 1; + u32 reserved1 : 23; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_cr0_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_cr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_QAD0_GCR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad0_gcr0_s +{ + u32 qad0den : 1; + u32 qad0log_mode_dis : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad0_gcr0_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad0_gcr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_QAD0_CR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad0_cr0_s +{ + u32 cfgere : 1; + u32 clere : 1; + u32 cfgeie : 1; + u32 cleie : 1; + u32 reserved0 : 4; + u32 dynamic_clk_en : 1; + u32 reserved1 : 23; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad0_cr0_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad0_cr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_QAD1_GCR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad1_gcr0_s +{ + u32 qad1den : 1; + u32 qad1log_mode_dis : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad1_gcr0_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad1_gcr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_QAD1_CR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad1_cr0_s +{ + u32 cfgere : 1; + u32 clere : 1; + u32 cfgeie : 1; + u32 cleie : 1; + u32 reserved0 : 4; + u32 dynamic_clk_en : 1; + u32 reserved1 : 23; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad1_cr0_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad1_cr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_UMR_GCR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_umr_gcr0_s +{ + u32 umr_owner : 3; + u32 reserved0 : 5; + u32 umr_sec_apps : 1; + u32 reserved1 : 23; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_umr_gcr0_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_umr_gcr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_UMR_GCR3 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_umr_gcr3_s +{ + u32 umr_secure_access_lock : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_umr_gcr3_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_umr_gcr3_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_UMR_CR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_umr_cr0_s +{ + u32 umrsclrden_apps : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_umr_cr0_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_umr_cr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_UMR_CR1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_umr_cr1_s +{ + u32 umrclrden : 3; + u32 arm_qc_approach : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_umr_cr1_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_umr_cr1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_UMR_CR2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_umr_cr2_s +{ + u32 umrsclwren_apps : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_umr_cr2_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_umr_cr2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_UMR_CR3 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_umr_cr3_s +{ + u32 umrclwren : 3; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_umr_cr3_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_umr_cr3_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_IDR3 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_idr3_s +{ + u32 nvmid : 8; + u32 mv : 1; + u32 pt : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_idr3_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_idr3_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_IDR2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_idr2_s +{ + u32 num_qad : 4; + u32 reserved0 : 4; + u32 vmidacr_en : 8; + u32 sec_en : 8; + u32 nonsec_en : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_idr2_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_idr2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_IDR1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_idr1_s +{ + u32 lsb : 6; + u32 reserved0 : 2; + u32 msb_mpu : 6; + u32 reserved1 : 2; + u32 config_addr_width : 6; + u32 reserved2 : 2; + u32 client_addr_width : 6; + u32 reserved3 : 2; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_idr1_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_idr1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_IDR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_idr0_s +{ + u32 xputype : 2; + u32 reserved0 : 2; + u32 xpu_client_pipeline_en : 1; + u32 clientreq_halt_ack_hw_en : 1; + u32 bled : 1; + u32 reserved1 : 9; + u32 nrg : 10; + u32 reserved2 : 6; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_idr0_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_idr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_REV +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_rev_s +{ + u32 step : 16; + u32 minor : 12; + u32 major : 4; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_rev_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_rev_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_LOG_MODE_DIS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_log_mode_dis_s +{ + u32 log_mode_dis : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_log_mode_dis_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_log_mode_dis_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_RGN_FREESTATUSr +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_rgn_freestatusr_s +{ + u32 rgfreestatus : 10; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_rgn_freestatusr_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_rgn_freestatusr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_SEAR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_sear0_s +{ + u32 addr_31_0 : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_sear0_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_sear0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_SESR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_sesr_s +{ + u32 cfg : 1; + u32 client : 1; + u32 cfgmulti : 1; + u32 clmulti : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_sesr_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_sesr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_SESRRESTORE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_sesrrestore_s +{ + u32 cfg : 1; + u32 client : 1; + u32 cfgmulti : 1; + u32 clmulti : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_sesrrestore_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_sesrrestore_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_SESYNR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_sesynr0_s +{ + u32 xprotns : 1; + u32 awrite : 1; + u32 xinst : 1; + u32 xpriv : 1; + u32 reserved0 : 4; + u32 qad : 8; + u32 alen : 8; + u32 asize : 3; + u32 reserved1 : 2; + u32 burstlen : 1; + u32 ac : 1; + u32 reserved2 : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_sesynr0_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_sesynr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_SESYNR1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_sesynr1_s +{ + u32 mid : 8; + u32 pid : 5; + u32 bid : 3; + u32 vmid : 8; + u32 tid : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_sesynr1_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_sesynr1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_SESYNR2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_sesynr2_s +{ + u32 memtype : 3; + u32 reserved0 : 4; + u32 transient : 1; + u32 noallocate : 1; + u32 ooowr : 1; + u32 ooord : 1; + u32 orderedwr : 1; + u32 orderedrd : 1; + u32 portmrel : 1; + u32 innerwritethrough : 1; + u32 innertransient : 1; + u32 innershared : 1; + u32 innercacheable : 1; + u32 innernoallocate : 1; + u32 writethrough : 1; + u32 shared : 1; + u32 full : 1; + u32 exclusive : 1; + u32 error : 1; + u32 earlywrresp : 1; + u32 device_type : 2; + u32 device : 1; + u32 cacheable : 1; + u32 burst : 1; + u32 bar : 2; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_sesynr2_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_sesynr2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_SEAR1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_sear1_s +{ + u32 addr_63_32 : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_sear1_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_sear1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_SESYNR3 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_sesynr3_s +{ + u32 nonsec_ad_rg_match : 8; + u32 sec_ad_rg_match : 8; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_sesynr3_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_sesynr3_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_SESYNR4 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_sesynr4_s +{ + u32 auattr : 16; + u32 acgranuletrans : 1; + u32 asid : 5; + u32 acacheoptype : 4; + u32 reserved0 : 6; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_sesynr4_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_sesynr4_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_RGN_START0_SSHADOW +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_rgn_start0_sshadow_s +{ + u32 reserved0 : 12; + u32 addr_31_0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_rgn_start0_sshadow_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_rgn_start0_sshadow_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_RGN_END0_SSHADOW +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_rgn_end0_sshadow_s +{ + u32 reserved0 : 12; + u32 addr_31_0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_rgn_end0_sshadow_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_rgn_end0_sshadow_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_EAR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_ear0_s +{ + u32 addr_31_0 : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_ear0_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_ear0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_ESR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_esr_s +{ + u32 cfg : 1; + u32 client : 1; + u32 cfgmulti : 1; + u32 clmulti : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_esr_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_esr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_ESRRESTORE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_esrrestore_s +{ + u32 cfg : 1; + u32 client : 1; + u32 cfgmulti : 1; + u32 clmulti : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_esrrestore_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_esrrestore_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_ESYNR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_esynr0_s +{ + u32 xprotns : 1; + u32 awrite : 1; + u32 xinst : 1; + u32 xpriv : 1; + u32 reserved0 : 4; + u32 qad : 8; + u32 alen : 8; + u32 asize : 3; + u32 reserved1 : 2; + u32 burstlen : 1; + u32 ac : 1; + u32 reserved2 : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_esynr0_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_esynr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_ESYNR1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_esynr1_s +{ + u32 mid : 8; + u32 pid : 5; + u32 bid : 3; + u32 vmid : 8; + u32 tid : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_esynr1_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_esynr1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_ESYNR2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_esynr2_s +{ + u32 memtype : 3; + u32 reserved0 : 4; + u32 transient : 1; + u32 noallocate : 1; + u32 ooowr : 1; + u32 ooord : 1; + u32 orderedwr : 1; + u32 orderedrd : 1; + u32 portmrel : 1; + u32 innerwritethrough : 1; + u32 innertransient : 1; + u32 innershared : 1; + u32 innercacheable : 1; + u32 innernoallocate : 1; + u32 writethrough : 1; + u32 shared : 1; + u32 full : 1; + u32 exclusive : 1; + u32 error : 1; + u32 earlywrresp : 1; + u32 device_type : 2; + u32 device : 1; + u32 cacheable : 1; + u32 burst : 1; + u32 bar : 2; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_esynr2_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_esynr2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_EAR1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_ear1_s +{ + u32 addr_63_32 : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_ear1_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_ear1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_ESYNR3 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_esynr3_s +{ + u32 nonsec_ad_rg_match : 8; + u32 sec_ad_rg_match : 8; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_esynr3_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_esynr3_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_ESYNR4 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_esynr4_s +{ + u32 auattr : 16; + u32 acgranuletrans : 1; + u32 asid : 5; + u32 acacheoptype : 4; + u32 reserved0 : 6; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_esynr4_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_esynr4_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_RGN_START0_SHADOW +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_rgn_start0_shadow_s +{ + u32 reserved0 : 12; + u32 addr_31_0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_rgn_start0_shadow_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_rgn_start0_shadow_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_RGN_END0_SHADOW +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_rgn_end0_shadow_s +{ + u32 reserved0 : 12; + u32 addr_31_0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_rgn_end0_shadow_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_rgn_end0_shadow_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_QAD0_EAR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad0_ear0_s +{ + u32 addr_31_0 : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad0_ear0_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad0_ear0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_QAD0_ESR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad0_esr_s +{ + u32 cfg : 1; + u32 client : 1; + u32 cfgmulti : 1; + u32 clmulti : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad0_esr_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad0_esr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_QAD0_ESRRESTORE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad0_esrrestore_s +{ + u32 cfg : 1; + u32 client : 1; + u32 cfgmulti : 1; + u32 clmulti : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad0_esrrestore_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad0_esrrestore_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad0_esynr0_s +{ + u32 xprotns : 1; + u32 awrite : 1; + u32 xinst : 1; + u32 xpriv : 1; + u32 reserved0 : 4; + u32 qad : 8; + u32 alen : 8; + u32 asize : 3; + u32 reserved1 : 2; + u32 burstlen : 1; + u32 ac : 1; + u32 reserved2 : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad0_esynr0_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad0_esynr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad0_esynr1_s +{ + u32 mid : 8; + u32 pid : 5; + u32 bid : 3; + u32 vmid : 8; + u32 tid : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad0_esynr1_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad0_esynr1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad0_esynr2_s +{ + u32 memtype : 3; + u32 reserved0 : 4; + u32 transient : 1; + u32 noallocate : 1; + u32 ooowr : 1; + u32 ooord : 1; + u32 orderedwr : 1; + u32 orderedrd : 1; + u32 portmrel : 1; + u32 innerwritethrough : 1; + u32 innertransient : 1; + u32 innershared : 1; + u32 innercacheable : 1; + u32 innernoallocate : 1; + u32 writethrough : 1; + u32 shared : 1; + u32 full : 1; + u32 exclusive : 1; + u32 error : 1; + u32 earlywrresp : 1; + u32 device_type : 2; + u32 device : 1; + u32 cacheable : 1; + u32 burst : 1; + u32 bar : 2; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad0_esynr2_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad0_esynr2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_QAD0_EAR1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad0_ear1_s +{ + u32 addr_63_32 : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad0_ear1_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad0_ear1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR3 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad0_esynr3_s +{ + u32 nonsec_ad_rg_match : 8; + u32 sec_ad_rg_match : 8; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad0_esynr3_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad0_esynr3_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_QAD0_ESYNR4 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad0_esynr4_s +{ + u32 auattr : 16; + u32 acgranuletrans : 1; + u32 asid : 5; + u32 acacheoptype : 4; + u32 reserved0 : 6; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad0_esynr4_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad0_esynr4_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_QAD0_RGN_START0_SHADOW +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad0_rgn_start0_shadow_s +{ + u32 reserved0 : 12; + u32 addr_31_0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad0_rgn_start0_shadow_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad0_rgn_start0_shadow_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_QAD0_RGN_END0_SHADOW +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad0_rgn_end0_shadow_s +{ + u32 reserved0 : 12; + u32 addr_31_0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad0_rgn_end0_shadow_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad0_rgn_end0_shadow_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_QAD1_EAR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad1_ear0_s +{ + u32 addr_31_0 : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad1_ear0_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad1_ear0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_QAD1_ESR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad1_esr_s +{ + u32 cfg : 1; + u32 client : 1; + u32 cfgmulti : 1; + u32 clmulti : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad1_esr_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad1_esr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_QAD1_ESRRESTORE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad1_esrrestore_s +{ + u32 cfg : 1; + u32 client : 1; + u32 cfgmulti : 1; + u32 clmulti : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad1_esrrestore_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad1_esrrestore_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad1_esynr0_s +{ + u32 xprotns : 1; + u32 awrite : 1; + u32 xinst : 1; + u32 xpriv : 1; + u32 reserved0 : 4; + u32 qad : 8; + u32 alen : 8; + u32 asize : 3; + u32 reserved1 : 2; + u32 burstlen : 1; + u32 ac : 1; + u32 reserved2 : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad1_esynr0_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad1_esynr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad1_esynr1_s +{ + u32 mid : 8; + u32 pid : 5; + u32 bid : 3; + u32 vmid : 8; + u32 tid : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad1_esynr1_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad1_esynr1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad1_esynr2_s +{ + u32 memtype : 3; + u32 reserved0 : 4; + u32 transient : 1; + u32 noallocate : 1; + u32 ooowr : 1; + u32 ooord : 1; + u32 orderedwr : 1; + u32 orderedrd : 1; + u32 portmrel : 1; + u32 innerwritethrough : 1; + u32 innertransient : 1; + u32 innershared : 1; + u32 innercacheable : 1; + u32 innernoallocate : 1; + u32 writethrough : 1; + u32 shared : 1; + u32 full : 1; + u32 exclusive : 1; + u32 error : 1; + u32 earlywrresp : 1; + u32 device_type : 2; + u32 device : 1; + u32 cacheable : 1; + u32 burst : 1; + u32 bar : 2; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad1_esynr2_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad1_esynr2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_QAD1_EAR1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad1_ear1_s +{ + u32 addr_63_32 : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad1_ear1_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad1_ear1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR3 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad1_esynr3_s +{ + u32 nonsec_ad_rg_match : 8; + u32 sec_ad_rg_match : 8; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad1_esynr3_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad1_esynr3_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_QAD1_ESYNR4 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad1_esynr4_s +{ + u32 auattr : 16; + u32 acgranuletrans : 1; + u32 asid : 5; + u32 acacheoptype : 4; + u32 reserved0 : 6; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad1_esynr4_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad1_esynr4_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_QAD1_RGN_START0_SHADOW +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad1_rgn_start0_shadow_s +{ + u32 reserved0 : 12; + u32 addr_31_0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad1_rgn_start0_shadow_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad1_rgn_start0_shadow_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_QAD1_RGN_END0_SHADOW +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad1_rgn_end0_shadow_s +{ + u32 reserved0 : 12; + u32 addr_31_0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad1_rgn_end0_shadow_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_qad1_rgn_end0_shadow_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_RGN_OWNERSTATUSr +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_rgn_ownerstatusr_s +{ + u32 rgownerstatus : 10; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_rgn_ownerstatusr_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_rgn_ownerstatusr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_RGn_GCR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_rgn_gcr0_s +{ + u32 rg_owner : 3; + u32 reserved0 : 5; + u32 rg_sec_apps : 1; + u32 reserved1 : 23; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_rgn_gcr0_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_rgn_gcr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_RGn_GCR1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_rgn_gcr1_s +{ + u32 reserved0 : 31; + u32 pd : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_rgn_gcr1_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_rgn_gcr1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_RGn_GCR2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_rgn_gcr2_s +{ + u32 csrc : 1; + u32 asrc : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_rgn_gcr2_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_rgn_gcr2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_RGn_GCR3 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_rgn_gcr3_s +{ + u32 secure_access_lock : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_rgn_gcr3_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_rgn_gcr3_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_RGn_CR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_rgn_cr0_s +{ + u32 rgsclrden_apps : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_rgn_cr0_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_rgn_cr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_RGn_CR1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_rgn_cr1_s +{ + u32 rgclrden : 3; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_rgn_cr1_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_rgn_cr1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_RGn_CR2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_rgn_cr2_s +{ + u32 rgsclwren_apps : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_rgn_cr2_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_rgn_cr2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_RGn_CR3 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_rgn_cr3_s +{ + u32 rgclwren : 3; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_rgn_cr3_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_rgn_cr3_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_RGn_START0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_rgn_start0_s +{ + u32 reserved0 : 12; + u32 addr_31_0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_rgn_start0_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_rgn_start0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MS_MPU_CFG_XPU3_RGn_END0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_rgn_end0_s +{ + u32 reserved0 : 12; + u32 addr_31_0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_rgn_end0_u +{ + struct ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_rgn_end0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_RSRC_GRP_CFG_EXT +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_rsrc_grp_cfg_ext_s +{ + u32 src_grp_2nd_priority_special_valid : 1; + u32 reserved0 : 3; + u32 src_grp_2nd_priority_special_index : 3; + u32 reserved1 : 25; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_rsrc_grp_cfg_ext_u +{ + struct ipa_hwio_def_ipa_0_ipa_rsrc_grp_cfg_ext_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of fc_stats +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_fc_stats_state_s +{ + u32 reserved0 : 16; + u32 flow_control : 1; + u32 flow_control_primary : 1; + u32 flow_control_secondary : 1; + u32 pending_flow_control : 1; + u32 reserved1 : 12; +}; + +/* Union definition of register */ +union ipa_hwio_def_fc_stats_state_u +{ + struct ipa_hwio_def_fc_stats_state_s def; + u32 value; +}; + +#endif /* __IPA_HWIO_DEF_H__ */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.0/ipa_pkt_cntxt.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.0/ipa_pkt_cntxt.h new file mode 100644 index 0000000000..535ec6ceb8 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.0/ipa_pkt_cntxt.h @@ -0,0 +1,256 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ +#if !defined(_IPA_PKT_CNTXT_H_) +#define _IPA_PKT_CNTXT_H_ + +#define IPA_HW_PKT_CTNTX_MAX 0x10 + +/* + * Packet Context States + */ +enum ipa_hw_pkt_cntxt_state_e { + IPA_HW_PKT_CNTXT_STATE_HFETCHER_INIT = 1, + IPA_HW_PKT_CNTXT_STATE_HFETCHER_DMAR = 2, + IPA_HW_PKT_CNTXT_STATE_H_DCPH = 3, + IPA_HW_PKT_CNTXT_STATE_MULTI_DRBIP = 4, + IPA_HW_PKT_CNTXT_STATE_PKT_PARSER = 5, + IPA_HW_PKT_CNTXT_STATE_FILTER_NAT = 6, + IPA_HW_PKT_CNTXT_STATE_ROUTER = 7, + IPA_HW_PKT_CNTXT_STATE_HDRI = 8, + IPA_HW_PKT_CNTXT_STATE_UCP = 9, + IPA_HW_PKT_CNTXT_STATE_COAL_MASTER = 10, + IPA_HW_PKT_CNTXT_STATE_ENQUEUER = 11, + IPA_HW_PKT_CNTXT_STATE_DFETCHER = 12, + IPA_HW_PKT_CNTXT_STATE_D_DCPH = 13, + IPA_HW_PKT_CNTXT_STATE_DISPATCHER = 14, + IPA_HW_PKT_CNTXT_STATE_TX = 15, + IPA_HW_PKT_CNTXT_STATE_TX_ZLT = 16, + IPA_HW_PKT_CNTXT_STATE_DFETCHER_DMAR = 17, + IPA_HW_PKT_CNTXT_STATE_D_DCPH_2 = 19, + IPA_HW_PKT_CNTXT_STATE_TX_RSRCREL = 20, +}; + +/* + * Packet Context fields as received from VI/Design + */ +struct ipa_pkt_ctntx_s { + u64 opcode : 8; /* Word 0 Bits 0-7 */ + u64 state : 5; /* Word 0 Bits 8-12 */ + u64 stats_disable : 1; /* Word 0 Bit 13 */ + u64 exc_ucp : 1; /* Word 0 Bit 14 */ + u64 tx_pkt_dma_done : 1; /* Word 0 Bit 15 */ + u64 exc_deagg : 1; /* Word 0 Bit 16 */ + u64 exc_pkt_version : 1; /* Word 0 Bit 17 */ + u64 exc_pkt_len : 1; /* Word 0 Bit 18 */ + u64 exc_threshold : 1; /* Word 0 Bit 19 */ + u64 exc_sw : 1; /* Word 0 Bit 20 */ + u64 exc_nat : 1; /* Word 0 Bit 21 */ + u64 exc_frag_miss : 1; /* Word 0 Bit 22 */ + u64 filter_bypass : 1; /* Word 0 Bit 23 */ + u64 router_bypass : 1; /* Word 0 Bit 24 */ + u64 nat_bypass : 1; /* Word 0 Bit 25 */ + u64 hdri_bypass : 1; /* Word 0 Bit 26 */ + u64 dcph_bypass : 1; /* Word 0 Bit 27 */ + u64 security_credentials_select : 1; /* Word 0 Bit 28 */ + u64 dcph_valid : 1; /* Word 0 Bit 29 */ + u64 round_bypass : 1; /* Word 0 Bit 30 */ + u64 bearer_valid : 1; /* Word 0 Bit 31 */ + u64 ucp_on : 1; /* Word 0 Bit 32 */ + u64 replication : 1; /* Word 0 Bit 33 */ + u64 src_status_en : 1; /* Word 0 Bit 34 */ + u64 dest_status_en : 1; /* Word 0 Bit 35 */ + u64 frag_status_en : 1; /* Word 0 Bit 36 */ + u64 eot_dest : 1; /* Word 0 Bit 37 */ + u64 eot_notif : 1; /* Word 0 Bit 38 */ + u64 prev_eot_dest : 1; /* Word 0 Bit 39 */ + u64 l2_len : 9; /* Word 0 Bits 40-48 */ + u64 dispatcher_pass : 1; /* Word 0 Bit 49 */ + u64 ucp_on_for_rts : 1; /* Word 0 Bit 50 */ + u64 exc_hdri : 1; /* Word 0 Bit 51 */ + u64 pkt_parser_bypass : 1; /* Word 0 Bit 52 */ + u64 exc_pipe : 1; /* Word 0 Bit 53 */ + u64 nat_in_hdrs : 1; /* Word 0 Bit 54 */ + u64 pkt_has_padding : 1; /* Word 0 Bit 55 */ + u64 rx_flags : 8; /* Word 0 Bits 56-63 */ + u64 rx_packet_length : 16; /* Word 1 Bits 0-15 */ + u64 revised_packet_length : 16; /* Word 1 Bits 16-31 */ + u64 frag_en : 1; /* Word 1 Bit 32 */ + u64 frag_bypass : 1; /* Word 1 Bit 33 */ + u64 frag_process : 1; /* Word 1 Bit 34 */ + u64 tx_pkt_transferred : 1; /* Word 1 Bit 35 */ + u64 filter_aggr_force_close : 1; /* Word 1 Bit 36 */ + u64 router_aggr_force_close : 1; /* Word 1 Bit 37 */ + u64 not_used1 : 2; /* Word 1 Bits 38-39 */ + u64 src_id : 8; /* Word 1 Bits 40-47 */ + u64 src_pipe : 8; /* Word 1 Bits 48-55 */ + u64 dest_pipe : 8; /* Word 1 Bits 56-63 */ + u64 ihl_offset : 6; /* Word 2 Bits 0-5 */ + u64 d_dcph_pass : 1; /* Word 2 Bit 6 */ + u64 not_used2 : 1; /* Word 2 Bit 7 */ + u64 protocol : 8; /* Word 2 Bits 8-15 */ + u64 tos : 8; /* Word 2 Bits 16-23 */ + u64 id : 16; /* Word 2 Bits 24-39 */ + u64 v6_reserved : 4; /* Word 2 Bits 40-43 */ + u64 ff : 1; /* Word 2 Bit 44 */ + u64 mf : 1; /* Word 2 Bit 45 */ + u64 pkt_is_frag : 1; /* Word 2 Bit 46 */ + u64 cs_disavle_trailer_valid_bit : 1; /* Word 2 Bit 47 */ + u64 exc_checksum : 1; /* Word 2 Bit 48 */ + u64 trnseq_0 : 3; /* Word 2 Bits 49-51 */ + u64 trnseq_1 : 3; /* Word 2 Bits 52-54 */ + u64 trnseq_2 : 3; /* Word 2 Bits 55-57 */ + u64 trnseq_3 : 3; /* Word 2 Bits 58-60 */ + u64 trnseq_4 : 3; /* Word 2 Bits 61-63 */ + u64 trnseq_ex_length : 8; /* Word 3 Bits 0-7 */ + u64 trnseq_4_length : 8; /* Word 3 Bits 8-15 */ + u64 trnseq_4_offset : 8; /* Word 3 Bits 16-23 */ + u64 dps_tx_pop_cnt : 2; /* Word 3 Bits 24-25 */ + u64 dps_tx_push_cnt : 2; /* Word 3 Bits 26-27 */ + u64 vol_ic_dcph_cfg : 1; /* Word 3 Bit 28 */ + u64 vol_ic_tag_stts : 1; /* Word 3 Bit 29 */ + u64 vol_ic_pxkt_init_ex : 1; /* Word 3 Bit 30 */ + u64 vol_ic_pkt_init : 1; /* Word 3 Bit 31 */ + u64 trnseq_0_preucp : 1; /* Word 3 Bit 32 */ + u64 dest_pipe_overridden_ucp : 1; /* Word 3 Bit 33 */ + u64 force_to_default : 1; /* Word 3 Bit 34 */ + u64 close_vp_before : 1; /* Word 3 Bit 35 */ + u64 vol_ic_eob_bubble : 1; /* Word 3 Bit 36 */ + u64 not_used3 : 5; /* Word 3 Bits 37-41 */ + u64 maci_bytes_in_trnseq : 1; /* Word 3 Bit 42 */ + u64 drop_drbip : 1; /* Word 3 Bit 43 */ + u64 exc_drbip : 1; /* Word 3 Bit 44 */ + u64 drbip_valid : 1; /* Word 3 Bit 45 */ + u64 tx_pkt_suspended : 1; /* Word 3 Bit 46 */ + u64 rb : 1; /* Word 3 Bit 47 */ + u64 tcp_win_size : 16; /* Word 3 Bits 48-63 */ + u64 trnseq_0_length : 8; /* Word 4 Bits 0-7 */ + u64 trnseq_0_offset : 8; /* Word 4 Bits 8-15 */ + u64 trnseq_1_length : 8; /* Word 4 Bits 16-23 */ + u64 trnseq_1_offset : 8; /* Word 4 Bits 24-31 */ + u64 trnseq_2_length : 8; /* Word 4 Bits 32-39 */ + u64 trnseq_2_offset : 8; /* Word 4 Bits 40-47 */ + u64 trnseq_3_length : 8; /* Word 4 Bits 48-55 */ + u64 trnseq_3_offset : 8; /* Word 4 Bits 56-63 */ + u64 dmar_valid_length : 16; /* Word 5 Bits 0-15 */ + u64 dcph_valid_length : 16; /* Word 5 Bits 16-31 */ + u64 frag_pipe : 8; /* Word 5 Bits 32-39 */ + u64 notif_pipe : 8; /* Word 5 Bits 40-47 */ + u64 not_used4 : 8; /* Word 5 Bits 48-55 */ + u64 vp_index : 8; /* Word 5 Bits 56-63 */ + u64 l4_payload_checksum : 16; /* Word 6 Bits 0-15 */ + u64 l4_pseudo_hdr_checksum : 16; /* Word 6 Bits 16-31 */ + u64 frag_hdr_offset : 9; /* Word 6 Bits 32-40 */ + u64 not_used5 : 1; /* Word 6 Bit 41 */ + u64 ece : 1; /* Word 6 Bit 42 */ + u64 udp_with_zero_checksum : 1; /* Word 6 Bit 43 */ + u64 router_rule_table_hit : 1; /* Word 6 Bit 44 */ + u64 filter_rule_table_hit : 1; /* Word 6 Bit 45 */ + u64 hps_round_cnt : 2; /* Word 6 Bits 46-47 */ + u64 first_pkt_parser_done : 1; /* Word 6 Bit 48 */ + u64 frag_hit_2nd : 1; /* Word 6 Bit 49 */ + u64 frag_rule : 4; /* Word 6 Bits 50-53 */ + u64 frag_table : 1; /* Word 6 Bit 54 */ + u64 frag_hit : 1; /* Word 6 Bit 55 */ + u64 data_cmdq_ptr : 8; /* Word 6 Bits 56-63 */ + u64 filter_result : 6; /* Word 7 Bits 0-5 */ + u64 nat_result : 6; /* Word 7 Bits 6-11 */ + u64 tx_pkt_dropped : 1; /* Word 7 Bit 12 */ + u64 not_used6 : 2; /* Word 7 Bits 13-14 */ + u64 original_hdr_size : 9; /* Word 7 Bits 15-23 */ + u64 frag_dest_pipe : 8; /* Word 7 Bits 24-31 */ + u64 filter_action_params : 5; /* Word 7 Bits 32-36 */ + u64 pure_ack : 1; /* Word 7 Bit 37 */ + u64 syn : 1; /* Word 7 Bit 38 */ + u64 fin : 1; /* Word 7 Bit 39 */ + u64 ipv4_vld_checksum : 1; /* Word 7 Bit 40 */ + u64 metadata_type : 3; /* Word 7 Bits 41-43 */ + u64 qmap_cs_valid_bit : 1; /* Word 7 Bit 44 */ + u64 df : 1; /* Word 7 Bit 45 */ + u64 ttl : 8; /* Word 7 Bits 46-53 */ + u64 original_ip_version : 2; /* Word 7 Bits 54-55 */ + u64 original_src_hdr_len : 8; /* Word 7 Bits 56-63 */ + u64 fl_l : 1; /* Word 8 Bit 0 */ + u64 fl_h : 1; /* Word 8 Bit 1 */ + u64 fr_g : 1; /* Word 8 Bit 2 */ + u64 fr_ret : 1; /* Word 8 Bit 3 */ + u64 fr_rule_id : 10; /* Word 8 Bits 4-13 */ + u64 rt_l : 1; /* Word 8 Bit 14 */ + u64 rt_h : 1; /* Word 8 Bit 15 */ + u64 hdri_payload_length_includes_padding : 1; /* Word 8 Bit 16 */ + u64 hdri_pdding_or_total_length : 1; /* Word 8 Bit 17 */ + u64 hdri_payload_len_valid : 1; /* Word 8 Bit 18 */ + u64 hdri_padding_valid : 1; /* Word 8 Bit 19 */ + u64 hdri_endianess : 1; /* Word 8 Bit 20 */ + u64 rt_match : 1; /* Word 8 Bit 21 */ + u64 rt_rule_id : 10; /* Word 8 Bits 22-31 */ + u64 nat_tbl_index : 13; /* Word 8 Bits 32-42 */ + u64 nat_type : 2; /* Word 8 Bits 43-44 */ + u64 hdr_l : 1; /* Word 8 Bit 45 */ + u64 header_offset : 10; /* Word 8 Bits 48-57 */ + u64 filter_process : 1; /* Word 8 Bit 58 */ + u64 filter_result_valid : 1; /* Word 8 Bit 59 */ + u64 nat_result_valid : 1; /* Word 8 Bit 60 */ + u64 nat_process : 1; /* Word 8 Bit 61 */ + u64 urg : 1; /* Word 8 Bit 62 */ + u64 cwr : 1; /* Word 8 Bit 63 */ + u64 push : 1; /* Word 9 Bit 0 */ + u64 rst : 1; /* Word 9 Bit 1 */ + u64 ip_checksum_fix : 1; /* Word 9 Bit 2 */ + u64 tport_checksum_fix : 1; /* Word 9 Bit 3 */ + u64 ack : 1; /* Word 9 Bit 4 */ + u64 tcp_data_offset : 4; /* Word 9 Bits 5-8 */ + u64 router_process : 1; /* Word 9 Bit 9 */ + u64 frag_router_aggr_fc : 1; /* Word 9 Bit 10 */ + u64 frag_exception : 1; /* Word 9 Bit 11 */ + u64 bearer_context_index : 2; /* Word 9 Bits 12-13 */ + u64 dcph_cfg_size : 16; /* Word 9 Bits 14-29 */ + u64 bearer_cfg_count : 32; /* Word 9 Bits 30-61 */ + u64 maci_size : 2; /* Word 9 Bits 62-63 */ + u64 tag_info : 48; /* Word 10 Bits 0-47 */ + u64 ucp_cmd_id : 16; /* Word 10 Bits 48-63 */ + u64 metadata : 32; /* Word 11 Bits 0-31 */ + u64 ucp_cmd_params : 32; /* Word 11 Bits 32-63 */ + u64 frag_nat_ip_address : 32; /* Word 12 Bits 0-31 */ + u64 frag_nat_ip_cs_diff : 16; /* Word 12 Bits 32-47 */ + u64 ulso_ipv4_id_mode : 2; /* Word 12 Bits 48-49 */ + u64 ulso_udp_checksum_zero : 1; /* Word 12 Bit 50 */ + u64 ulso_frame_valid : 1; /* Word 12 Bit 51 */ + u64 not_used7 : 1; /* Word 12 Bit 52 */ + u64 frag_nat_type : 2; /* Word 12 Bits 53-54 */ + u64 fragr_fr_ret : 1; /* Word 12 Bit 55 */ + u64 frag_protocol : 8; /* Word 12 Bits 56-63 */ + u64 frag_src_ip_address : 32; /* Word 13 Bits 0-31 */ + u64 frag_dest_ip_address : 32; /* Word 13 Bits 32-63 */ + u64 router_stats_index : 8; /* Word 14 Bits 0-7 */ + u64 filter_stats_index : 8; /* Word 14 Bits 8-15 */ + u64 frag_filter_aggr_fc : 1; /* Word 14 Bit 16 */ + u64 close_deafault : 1; /* Word 14 Bit 17 */ + u64 close_vp_after_value : 8; /* Word 14 Bits 18-25 */ + u64 close_vp_before_value : 8; /* Word 14 Bits 26-33 */ + u64 close_vp_after : 1; /* Word 14 Bit 34 */ + u64 inc_ipv4_id : 1; /* Word 14 Bit 35 */ + u64 open_vp : 1; /* Word 14 Bit 36 */ + u64 frag_hdr_l : 1; /* Word 14 Bit 37*/ + u64 frag_header_offset : 10; /* Word 14 Bits 38-47 */ + u64 frag_id : 16; /* Word 14 Bits 48-63 */ + u64 metadata_pre_nat : 32; /* Word 15 Bits 0-31 */ + u64 ipv4_cs_without_total_len : 16; /* Word 15 Bits 32-47 */ + u64 frag_router_stats_index : 8; /* Word 15 Bits 48-55 */ + u64 frag_filter_stats_index : 8; /* Word 15 Bits 56-63 */ + u64 bearer_id : 8; /* Word 16 Bits 0-7 */ + u64 rt_table_index : 8; /* Word 16 Bits 8-15 */ + u64 hdri_offset_padding_total_length : 8; /* Word 16 Bits 16-23 */ + u64 hdri_offset_payload_len : 8; /* Word 16 Bits 24-31 */ + u64 hdri_dst_len : 8; /* Word 16 Bits 32-39 */ + u64 hdri_additional_const_length : 8; /* Word 16 Bits 40-47 */ + u64 ulso_mss : 16; /* Word 16 Bits 48-63 */ + u64 maci_calculated_lsbs : 64; /* Word 17 Bits 0-63 */ + u64 maci_calculated_msbs : 64; /* Word 18 Bits 0-63 */ + u64 padding_bytes_cnt : 16; /* Word 19 Bits 0-15 */ + u64 not_used8 : 48; /* Word 19 Bits 16-63 */ + +} __packed; + +#endif /* #if !defined(_IPA_PKT_CNTXT_H_) */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.0/ipa_reg_dump.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.0/ipa_reg_dump.c new file mode 100644 index 0000000000..456c8ce5f9 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.0/ipa_reg_dump.c @@ -0,0 +1,2040 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ +#include "ipa_reg_dump.h" +#include "ipa_access_control.h" +#include + +/* Total size required for test bus */ +#define IPA_MEM_OVERLAY_SIZE 0x66000 + +#define CONFIG_IPA3_REGDUMP_NUM_EXTRA_ENDP_REGS 0 + +/* + * The following structure contains a hierarchy of structures that + * ultimately leads to a series of leafs. The leafs are structures + * containing detailed, bit level, register definitions. + */ +static struct regs_save_hierarchy_s ipa_reg_save; + +static unsigned int ipa_testbus_mem[IPA_MEM_OVERLAY_SIZE]; + +/* + * The following data structure contains a list of the registers + * (whose data are to be copied) and the locations (within + * ipa_reg_save above) into which the registers' values need to be + * copied. + */ +static struct map_src_dst_addr_s ipa_regs_to_save_array[] = { + /* + * ===================================================================== + * IPA register definitions begin here... + * ===================================================================== + */ + + /* IPA General Registers */ + GEN_SRC_DST_ADDR_MAP(IPA_STATE, + ipa.gen, + ipa_state), +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + GEN_SRC_DST_ADDR_MAP(IPA_STATE_RX_ACTIVE, + ipa.gen, + ipa_state_rx_active), +#else + GEN_SRC_DST_ADDR_MAP_ARR(IPA_STATE_RX_ACTIVE_n, + ipa.gen, + ipa_state_rx_active_n), +#endif + GEN_SRC_DST_ADDR_MAP(IPA_STATE_TX_WRAPPER, + ipa.gen, + ipa_state_tx_wrapper), + GEN_SRC_DST_ADDR_MAP(IPA_STATE_TX0, + ipa.gen, + ipa_state_tx0), +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + GEN_SRC_DST_ADDR_MAP(IPA_STATE_TX0_MISC, + ipa.gen, + ipa_state_tx0_misc), +#endif + GEN_SRC_DST_ADDR_MAP(IPA_STATE_TX1, + ipa.gen, + ipa_state_tx1), +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + GEN_SRC_DST_ADDR_MAP(IPA_STATE_AGGR_ACTIVE, + ipa.gen, + ipa_state_aggr_active), +#else + GEN_SRC_DST_ADDR_MAP(IPA_STATE_TX1_MISC, + ipa.gen, + ipa_state_tx1_misc), + GEN_SRC_DST_ADDR_MAP_ARR(IPA_STATE_AGGR_ACTIVE_n, + ipa.gen, + ipa_state_aggr_active_n), +#endif + GEN_SRC_DST_ADDR_MAP(IPA_STATE_DFETCHER, + ipa.gen, + ipa_state_dfetcher), + GEN_SRC_DST_ADDR_MAP(IPA_STATE_FETCHER_MASK_0, + ipa.gen, + ipa_state_fetcher_mask_0), + GEN_SRC_DST_ADDR_MAP(IPA_STATE_FETCHER_MASK_1, + ipa.gen, + ipa_state_fetcher_mask_1), +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + GEN_SRC_DST_ADDR_MAP(IPA_STATE_FETCHER_MASK_2, + ipa.gen, + ipa_state_fetcher_mask_2), +#endif + GEN_SRC_DST_ADDR_MAP(IPA_STATE_GSI_AOS, + ipa.gen, + ipa_state_gsi_aos), + GEN_SRC_DST_ADDR_MAP(IPA_STATE_GSI_IF, + ipa.gen, + ipa_state_gsi_if), +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + GEN_SRC_DST_ADDR_MAP(IPA_STATE_GSI_SKIP, + ipa.gen, + ipa_state_gsi_skip), + GEN_SRC_DST_ADDR_MAP(IPA_STATE_GSI_TLV, + ipa.gen, + ipa_state_gsi_tlv), +#endif + GEN_SRC_DST_ADDR_MAP(IPA_DPL_TIMER_LSB, + ipa.gen, + ipa_dpl_timer_lsb), + GEN_SRC_DST_ADDR_MAP(IPA_DPL_TIMER_MSB, + ipa.gen, + ipa_dpl_timer_msb), + GEN_SRC_DST_ADDR_MAP(IPA_PROC_IPH_CFG, + ipa.gen, + ipa_proc_iph_cfg), + GEN_SRC_DST_ADDR_MAP(IPA_ROUTE, + ipa.gen, + ipa_route), + GEN_SRC_DST_ADDR_MAP(IPA_SPARE_REG_1, + ipa.gen, + ipa_spare_reg_1), +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + GEN_SRC_DST_ADDR_MAP(IPA_SPARE_REG_2, + ipa.gen, + ipa_spare_reg_2), +#endif + GEN_SRC_DST_ADDR_MAP(IPA_LOG, + ipa.gen, + ipa_log), +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + GEN_SRC_DST_ADDR_MAP(IPA_LOG_BUF_STATUS_CFG, + ipa.gen, + ipa_log_buf_status_cfg), + GEN_SRC_DST_ADDR_MAP(IPA_LOG_BUF_STATUS_ADDR, + ipa.gen, + ipa_log_buf_status_addr), + GEN_SRC_DST_ADDR_MAP(IPA_LOG_BUF_STATUS_WRITE_PTR, + ipa.gen, + ipa_log_buf_status_write_ptr), + GEN_SRC_DST_ADDR_MAP(IPA_LOG_BUF_STATUS_RAM_PTR, + ipa.gen, + ipa_log_buf_status_ram_ptr), +#endif + GEN_SRC_DST_ADDR_MAP(IPA_LOG_BUF_HW_CMD_CFG, + ipa.gen, + ipa_log_buf_hw_cmd_cfg), + GEN_SRC_DST_ADDR_MAP(IPA_LOG_BUF_HW_CMD_ADDR, + ipa.gen, + ipa_log_buf_hw_cmd_addr), + GEN_SRC_DST_ADDR_MAP(IPA_LOG_BUF_HW_CMD_WRITE_PTR, + ipa.gen, + ipa_log_buf_hw_cmd_write_ptr), + GEN_SRC_DST_ADDR_MAP(IPA_LOG_BUF_HW_CMD_RAM_PTR, + ipa.gen, + ipa_log_buf_hw_cmd_ram_ptr), + GEN_SRC_DST_ADDR_MAP(IPA_STATE_DPL_FIFO, + ipa.gen, + ipa_state_dpl_fifo), + GEN_SRC_DST_ADDR_MAP(IPA_COMP_HW_VERSION, + ipa.gen, + ipa_comp_hw_version), +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + GEN_SRC_DST_ADDR_MAP(IPA_FILT_ROUT_HASH_EN, + ipa.gen, + ipa_filt_rout_hash_en), + GEN_SRC_DST_ADDR_MAP(IPA_FILT_ROUT_HASH_FLUSH, + ipa.gen, + ipa_filt_rout_hash_flush), +#else + GEN_SRC_DST_ADDR_MAP(IPA_FILT_ROUT_CACHE_CFG, + ipa.gen, + ipa_filt_rout_cache_cfg), + GEN_SRC_DST_ADDR_MAP(IPA_FILT_ROUT_CACHE_FLUSH, + ipa.gen, + ipa_filt_rout_cache_flush), +#endif + GEN_SRC_DST_ADDR_MAP(IPA_STATE_FETCHER, + ipa.gen, + ipa_state_fetcher), + GEN_SRC_DST_ADDR_MAP(IPA_IPV4_FILTER_INIT_VALUES, + ipa.gen, + ipa_ipv4_filter_init_values), + GEN_SRC_DST_ADDR_MAP(IPA_IPV6_FILTER_INIT_VALUES, + ipa.gen, + ipa_ipv6_filter_init_values), + GEN_SRC_DST_ADDR_MAP(IPA_IPV4_ROUTE_INIT_VALUES, + ipa.gen, + ipa_ipv4_route_init_values), + GEN_SRC_DST_ADDR_MAP(IPA_IPV6_ROUTE_INIT_VALUES, + ipa.gen, + ipa_ipv6_route_init_values), +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + GEN_SRC_DST_ADDR_MAP(IPA_BAM_ACTIVATED_PORTS, + ipa.gen, + ipa_bam_activated_ports), +#else + GEN_SRC_DST_ADDR_MAP_ARR(IPA_BAM_ACTIVATED_PORTS_n, + ipa.gen, + ipa_bam_activated_ports_n), +#endif + GEN_SRC_DST_ADDR_MAP(IPA_TX_COMMANDER_CMDQ_STATUS, + ipa.gen, + ipa_tx_commander_cmdq_status), + GEN_SRC_DST_ADDR_MAP(IPA_LOG_BUF_HW_SNIF_EL_EN, + ipa.gen, + ipa_log_buf_hw_snif_el_en), + GEN_SRC_DST_ADDR_MAP(IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL, + ipa.gen, + ipa_log_buf_hw_snif_el_wr_n_rd_sel), + GEN_SRC_DST_ADDR_MAP(IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX, + ipa.gen, + ipa_log_buf_hw_snif_el_cli_mux), +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + GEN_SRC_DST_ADDR_MAP(IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL, + ipa.gen, + ipa_log_buf_hw_cmd_noc_master_sel), +#endif + GEN_SRC_DST_ADDR_MAP(IPA_STATE_ACL, + ipa.gen, + ipa_state_acl), + GEN_SRC_DST_ADDR_MAP(IPA_SYS_PKT_PROC_CNTXT_BASE, + ipa.gen, + ipa_sys_pkt_proc_cntxt_base), + GEN_SRC_DST_ADDR_MAP(IPA_SYS_PKT_PROC_CNTXT_BASE_MSB, + ipa.gen, + ipa_sys_pkt_proc_cntxt_base_msb), + GEN_SRC_DST_ADDR_MAP(IPA_LOCAL_PKT_PROC_CNTXT_BASE, + ipa.gen, + ipa_local_pkt_proc_cntxt_base), + GEN_SRC_DST_ADDR_MAP(IPA_RSRC_GRP_CFG, + ipa.gen, + ipa_rsrc_grp_cfg), +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + GEN_SRC_DST_ADDR_MAP(IPA_PIPELINE_DISABLE, + ipa.gen, + ipa_pipeline_disable), +#endif + GEN_SRC_DST_ADDR_MAP(IPA_COMP_CFG, + ipa.gen, + ipa_comp_cfg), + GEN_SRC_DST_ADDR_MAP(IPA_STATE_NLO_AGGR, + ipa.gen, + ipa_state_nlo_aggr), +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + GEN_SRC_DST_ADDR_MAP(IPA_STATE_COAL_MASTER, + ipa.gen, + ipa_state_coal_master), + GEN_SRC_DST_ADDR_MAP(IPA_STATE_COAL_MASTER_1, + ipa.gen, + ipa_state_coal_master_1), + GEN_SRC_DST_ADDR_MAP(IPA_COAL_EVICT_LRU, + ipa.gen, + ipa_coal_evict_lru), + GEN_SRC_DST_ADDR_MAP(IPA_COAL_QMAP_CFG, + ipa.gen, + ipa_coal_qmap_cfg), + GEN_SRC_DST_ADDR_MAP(IPA_TAG_TIMER, + ipa.gen, + ipa_tag_timer), +#endif + GEN_SRC_DST_ADDR_MAP(IPA_NLO_PP_CFG1, + ipa.gen, + ipa_nlo_pp_cfg1), + GEN_SRC_DST_ADDR_MAP(IPA_NLO_PP_CFG2, + ipa.gen, + ipa_nlo_pp_cfg2), +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + GEN_SRC_DST_ADDR_MAP(IPA_NLO_PP_ACK_LIMIT_CFG, + ipa.gen, + ipa_nlo_pp_ack_limit_cfg), + GEN_SRC_DST_ADDR_MAP(IPA_NLO_PP_DATA_LIMIT_CFG, + ipa.gen, + ipa_nlo_pp_data_limit_cfg), +#endif + GEN_SRC_DST_ADDR_MAP(IPA_NLO_MIN_DSM_CFG, + ipa.gen, + ipa_nlo_min_dsm_cfg), +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + GEN_SRC_DST_ADDR_MAP_ARR(IPA_NLO_VP_AGGR_CFG_LSB_n, + ipa.gen, + ipa_nlo_vp_aggr_cfg_lsb_n), + GEN_SRC_DST_ADDR_MAP_ARR(IPA_NLO_VP_LIMIT_CFG_n, + ipa.gen, + ipa_nlo_vp_limit_cfg_n), +#endif + GEN_SRC_DST_ADDR_MAP(IPA_NLO_VP_FLUSH_REQ, + ipa.gen, + ipa_nlo_vp_flush_req), + GEN_SRC_DST_ADDR_MAP(IPA_NLO_VP_FLUSH_COOKIE, + ipa.gen, + ipa_nlo_vp_flush_cookie), + GEN_SRC_DST_ADDR_MAP(IPA_NLO_VP_FLUSH_ACK, + ipa.gen, + ipa_nlo_vp_flush_ack), + GEN_SRC_DST_ADDR_MAP(IPA_NLO_VP_DSM_OPEN, + ipa.gen, + ipa_nlo_vp_dsm_open), + GEN_SRC_DST_ADDR_MAP(IPA_NLO_VP_QBAP_OPEN, + ipa.gen, + ipa_nlo_vp_qbap_open), +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + GEN_SRC_DST_ADDR_MAP(IPA_QSB_MAX_READS, + ipa.gen, + ipa_qsb_max_reads), + GEN_SRC_DST_ADDR_MAP(IPA_QSB_MAX_WRITES, + ipa.gen, + ipa_qsb_max_writes), + GEN_SRC_DST_ADDR_MAP(IPA_IDLE_INDICATION_CFG, + ipa.gen, + ipa_idle_indication_cfg), + GEN_SRC_DST_ADDR_MAP(IPA_CLKON_CFG, + ipa.gen, + ipa_clkon_cfg), + GEN_SRC_DST_ADDR_MAP(IPA_TIMERS_XO_CLK_DIV_CFG, + ipa.gen, + ipa_timers_xo_clk_div_cfg), + GEN_SRC_DST_ADDR_MAP(IPA_TIMERS_PULSE_GRAN_CFG, + ipa.gen, + ipa_timers_pulse_gran_cfg), + GEN_SRC_DST_ADDR_MAP(IPA_QTIME_TIMESTAMP_CFG, + ipa.gen, + ipa_qtime_timestamp_cfg), + GEN_SRC_DST_ADDR_MAP(IPA_FLAVOR_0, + ipa.gen, + ipa_flavor_0), + GEN_SRC_DST_ADDR_MAP(IPA_FLAVOR_1, + ipa.gen, + ipa_flavor_1), + GEN_SRC_DST_ADDR_MAP(IPA_FILT_ROUT_CFG, + ipa.gen, + ipa_filt_rout_cfg), +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + GEN_SRC_DST_ADDR_MAP(IPA_RSRC_GRP_CFG_EXT, + ipa.gen, + ipa_rsrc_grp_cfg_ext), +#endif +#endif + + /* Debug Registers */ + GEN_SRC_DST_ADDR_MAP(IPA_DEBUG_DATA, + ipa.dbg, + ipa_debug_data), + GEN_SRC_DST_ADDR_MAP(IPA_STEP_MODE_BREAKPOINTS, + ipa.dbg, + ipa_step_mode_breakpoints), + GEN_SRC_DST_ADDR_MAP(IPA_STEP_MODE_STATUS, + ipa.dbg, + ipa_step_mode_status), + + IPA_REG_SAVE_RX_SPLT_CMDQ( + IPA_RX_SPLT_CMDQ_CMD_n, ipa_rx_splt_cmdq_cmd_n), + IPA_REG_SAVE_RX_SPLT_CMDQ( + IPA_RX_SPLT_CMDQ_CFG_n, ipa_rx_splt_cmdq_cfg_n), + IPA_REG_SAVE_RX_SPLT_CMDQ( + IPA_RX_SPLT_CMDQ_DATA_WR_0_n, ipa_rx_splt_cmdq_data_wr_0_n), + IPA_REG_SAVE_RX_SPLT_CMDQ( + IPA_RX_SPLT_CMDQ_DATA_WR_1_n, ipa_rx_splt_cmdq_data_wr_1_n), + IPA_REG_SAVE_RX_SPLT_CMDQ( + IPA_RX_SPLT_CMDQ_DATA_WR_2_n, ipa_rx_splt_cmdq_data_wr_2_n), + IPA_REG_SAVE_RX_SPLT_CMDQ( + IPA_RX_SPLT_CMDQ_DATA_WR_3_n, ipa_rx_splt_cmdq_data_wr_3_n), + IPA_REG_SAVE_RX_SPLT_CMDQ( + IPA_RX_SPLT_CMDQ_DATA_RD_0_n, ipa_rx_splt_cmdq_data_rd_0_n), + IPA_REG_SAVE_RX_SPLT_CMDQ( + IPA_RX_SPLT_CMDQ_DATA_RD_1_n, ipa_rx_splt_cmdq_data_rd_1_n), + IPA_REG_SAVE_RX_SPLT_CMDQ( + IPA_RX_SPLT_CMDQ_DATA_RD_2_n, ipa_rx_splt_cmdq_data_rd_2_n), + IPA_REG_SAVE_RX_SPLT_CMDQ( + IPA_RX_SPLT_CMDQ_DATA_RD_3_n, ipa_rx_splt_cmdq_data_rd_3_n), + IPA_REG_SAVE_RX_SPLT_CMDQ( + IPA_RX_SPLT_CMDQ_STATUS_n, ipa_rx_splt_cmdq_status_n), + + GEN_SRC_DST_ADDR_MAP(IPA_RX_HPS_CMDQ_CFG_WR, + ipa.dbg, + ipa_rx_hps_cmdq_cfg_wr), + GEN_SRC_DST_ADDR_MAP(IPA_RX_HPS_CMDQ_CFG_RD, + ipa.dbg, + ipa_rx_hps_cmdq_cfg_rd), + GEN_SRC_DST_ADDR_MAP(IPA_RX_HPS_CMDQ_CMD, + ipa.dbg, + ipa_rx_hps_cmdq_cmd), +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + GEN_SRC_DST_ADDR_MAP(IPA_STAT_FILTER_IPV4_BASE, + ipa.dbg, + ipa_stat_filter_ipv4_base), + GEN_SRC_DST_ADDR_MAP(IPA_STAT_FILTER_IPV6_BASE, + ipa.dbg, + ipa_stat_filter_ipv6_base), + GEN_SRC_DST_ADDR_MAP(IPA_STAT_ROUTER_IPV4_BASE, + ipa.dbg, + ipa_stat_router_ipv4_base), + GEN_SRC_DST_ADDR_MAP(IPA_STAT_ROUTER_IPV6_BASE, + ipa.dbg, + ipa_stat_router_ipv6_base), + GEN_SRC_DST_ADDR_MAP(IPA_RSRC_MNGR_CONTEXTS, + ipa.dbg, + ipa_rsrc_mngr_contexts), + GEN_SRC_DST_ADDR_MAP(IPA_SNOC_MONITORING_CFG, + ipa.dbg, + ipa_snoc_monitoring_cfg), + GEN_SRC_DST_ADDR_MAP(IPA_PCIE_SNOC_MONITOR_CNT, + ipa.dbg, + ipa_pcie_snoc_monitor_cnt), + GEN_SRC_DST_ADDR_MAP(IPA_DDR_SNOC_MONITOR_CNT, + ipa.dbg, + ipa_ddr_snoc_monitor_cnt), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_SNOC_MONITOR_CNT, + ipa.dbg, + ipa_gsi_snoc_monitor_cnt), + + GEN_SRC_DST_ADDR_MAP(IPA_RAM_SNIFFER_HW_BASE_ADDR, + ipa.dbg, + ipa_ram_sniffer_hw_base_addr), + GEN_SRC_DST_ADDR_MAP(IPA_BRESP_DB_CFG, + ipa.dbg, + ipa_bresp_db_cfg), + GEN_SRC_DST_ADDR_MAP(IPA_BRESP_DB_DATA, + ipa.dbg, + ipa_bresp_db_data), + + GEN_SRC_DST_ADDR_MAP(IPA_ENDP_GSI_CONS_BYTES_TLV, + ipa.dbg, + ipa_endp_gsi_cons_bytes_tlv), + GEN_SRC_DST_ADDR_MAP(IPA_RAM_GSI_TLV_BASE_ADDR, + ipa.dbg, + ipa_ram_gsi_tlv_base_addr), + GEN_SRC_DST_ADDR_MAP(IPA_ACKMNGR_CMDQ_CMD, + ipa.dbg, + ipa_ackmngr_cmdq_cmd), +#endif + GEN_SRC_DST_ADDR_MAP(IPA_RX_HPS_CMDQ_STATUS_EMPTY, + ipa.dbg, + ipa_rx_hps_cmdq_status_empty), + GEN_SRC_DST_ADDR_MAP(IPA_RX_HPS_CLIENTS_MIN_DEPTH_0, + ipa.dbg, + ipa_rx_hps_clients_min_depth_0), + GEN_SRC_DST_ADDR_MAP(IPA_RX_HPS_CLIENTS_MAX_DEPTH_0, + ipa.dbg, + ipa_rx_hps_clients_max_depth_0), + GEN_SRC_DST_ADDR_MAP(IPA_HPS_DPS_CMDQ_CMD, + ipa.dbg, + ipa_hps_dps_cmdq_cmd), +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + GEN_SRC_DST_ADDR_MAP(IPA_HPS_DPS_CMDQ_STATUS_EMPTY, + ipa.dbg, + ipa_hps_dps_cmdq_status_empty), +#else + GEN_SRC_DST_ADDR_MAP_ARR(IPA_HPS_DPS_CMDQ_STATUS_EMPTY_n, + ipa.dbg, + ipa_hps_dps_cmdq_status_empty_n), +#endif + GEN_SRC_DST_ADDR_MAP(IPA_DPS_TX_CMDQ_CMD, + ipa.dbg, + ipa_dps_tx_cmdq_cmd), + GEN_SRC_DST_ADDR_MAP(IPA_DPS_TX_CMDQ_STATUS_EMPTY, + ipa.dbg, + ipa_dps_tx_cmdq_status_empty), + GEN_SRC_DST_ADDR_MAP(IPA_ACKMNGR_CMDQ_CMD, + ipa.dbg, + ipa_ackmngr_cmdq_cmd), +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + GEN_SRC_DST_ADDR_MAP(IPA_ACKMNGR_CMDQ_STATUS_EMPTY, + ipa.dbg, + ipa_ackmngr_cmdq_status_empty), +#else + GEN_SRC_DST_ADDR_MAP_ARR(IPA_ACKMNGR_CMDQ_STATUS_EMPTY_n, + ipa.dbg, + ipa_ackmngr_cmdq_status_empty_n), + GEN_SRC_DST_ADDR_MAP_ARR(IPA_NTF_TX_CMDQ_STATUS_EMPTY_n, + ipa.dbg, + ipa_ntf_tx_cmdq_status_empty_n), +#endif + /* + * NOTE: That GEN_SRC_DST_ADDR_MAP() not used below. This is + * because the following registers are not scaler, rather + * they are register arrays... + */ + IPA_REG_SAVE_CFG_ENTRY_GEN_EE(IPA_IRQ_STTS_EE_n, + ipa_irq_stts_ee_n), + IPA_REG_SAVE_CFG_ENTRY_GEN_EE(IPA_IRQ_EN_EE_n, + ipa_irq_en_ee_n), + IPA_REG_SAVE_CFG_ENTRY_GEN_EE(IPA_FEC_ADDR_EE_n, + ipa_fec_addr_ee_n), + IPA_REG_SAVE_CFG_ENTRY_GEN_EE(IPA_FEC_ATTR_EE_n, + ipa_fec_attr_ee_n), + IPA_REG_SAVE_CFG_ENTRY_GEN_EE(IPA_SNOC_FEC_EE_n, + ipa_snoc_fec_ee_n), +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + IPA_REG_SAVE_CFG_ENTRY_GEN_EE(IPA_HOLB_DROP_IRQ_INFO_EE_n, + ipa_holb_drop_irq_info_ee_n), + IPA_REG_SAVE_CFG_ENTRY_GEN_EE(IPA_SUSPEND_IRQ_INFO_EE_n, + ipa_suspend_irq_info_ee_n), + IPA_REG_SAVE_CFG_ENTRY_GEN_EE(IPA_SUSPEND_IRQ_EN_EE_n, + ipa_suspend_irq_en_ee_n), +#else + GEN_SRC_DST_ADDR_MAP_EE_n_REG_k_ARR(IPA_HOLB_DROP_IRQ_INFO_EE_n_REG_k, + ipa.gen_ee, ipa_holb_drop_irq_info_ee_n_reg_k), + GEN_SRC_DST_ADDR_MAP_EE_n_REG_k_ARR(IPA_SUSPEND_IRQ_INFO_EE_n_REG_k, + ipa.gen_ee, ipa_suspend_irq_info_ee_n_reg_k), + GEN_SRC_DST_ADDR_MAP_EE_n_REG_k_ARR(IPA_SUSPEND_IRQ_EN_EE_n_REG_k, + ipa.gen_ee, ipa_suspend_irq_en_ee_n_reg_k), +#endif + +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + GEN_SRC_DST_ADDR_MAP_EE_n_ARR(IPA_STAT_QUOTA_BASE_n, + ipa.stat_ee, ipa_stat_quota_base_n), + GEN_SRC_DST_ADDR_MAP_EE_n_ARR(IPA_STAT_TETHERING_BASE_n, + ipa.stat_ee, ipa_stat_tethering_base_n), + GEN_SRC_DST_ADDR_MAP_EE_n_ARR(IPA_STAT_DROP_CNT_BASE_n, + ipa.stat_ee, ipa_stat_drop_cnt_base_n), + GEN_SRC_DST_ADDR_MAP_EE_n_REG_k_ARR(IPA_STAT_QUOTA_MASK_EE_n_REG_k, + ipa.stat_ee, ipa_stat_quota_mask_ee_n_reg_k), + GEN_SRC_DST_ADDR_MAP_EE_n_REG_k_ARR(IPA_STAT_TETHERING_MASK_EE_n_REG_k, + ipa.stat_ee, ipa_stat_tethering_mask_ee_n_reg_k), + GEN_SRC_DST_ADDR_MAP_EE_n_REG_k_ARR(IPA_STAT_DROP_CNT_MASK_EE_n_REG_k, + ipa.stat_ee, ipa_stat_drop_cnt_mask_ee_n_reg_k), +#endif + + /* Pipe Endp Registers */ + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_CTRL_n, + ipa_endp_init_ctrl_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_CTRL_SCND_n, + ipa_endp_init_ctrl_scnd_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_CFG_n, + ipa_endp_init_cfg_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_NAT_n, + ipa_endp_init_nat_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_HDR_n, + ipa_endp_init_hdr_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_HDR_EXT_n, + ipa_endp_init_hdr_ext_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_HDR_METADATA_MASK_n, + ipa_endp_init_hdr_metadata_mask_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_HDR_METADATA_n, + ipa_endp_init_hdr_metadata_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_MODE_n, + ipa_endp_init_mode_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_AGGR_n, + ipa_endp_init_aggr_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_HOL_BLOCK_EN_n, + ipa_endp_init_hol_block_en_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_HOL_BLOCK_TIMER_n, + ipa_endp_init_hol_block_timer_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_DEAGGR_n, + ipa_endp_init_deaggr_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_STATUS_n, + ipa_endp_status_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_RSRC_GRP_n, + ipa_endp_init_rsrc_grp_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_SEQ_n, + ipa_endp_init_seq_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_GSI_CFG_TLV_n, + ipa_endp_gsi_cfg_tlv_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_GSI_CFG_AOS_n, + ipa_endp_gsi_cfg_aos_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_GSI_CFG1_n, + ipa_endp_gsi_cfg1_n), +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_FILTER_ROUTER_HSH_CFG_n, + ipa_endp_filter_router_hsh_cfg_n), +#else + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_FILTER_CACHE_CFG_n, + ipa_filter_cache_cfg_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ROUTER_CACHE_CFG_n, + ipa_router_cache_cfg_n), +#endif + + /* Source Resource Group Config Registers */ + IPA_REG_SAVE_CFG_ENTRY_SRC_RSRC_GRP(IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n, + ipa_src_rsrc_grp_01_rsrc_type_n), + IPA_REG_SAVE_CFG_ENTRY_SRC_RSRC_GRP(IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n, + ipa_src_rsrc_grp_23_rsrc_type_n), + IPA_REG_SAVE_CFG_ENTRY_SRC_RSRC_GRP(IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n, + ipa_src_rsrc_grp_45_rsrc_type_n), +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + IPA_REG_SAVE_CFG_ENTRY_SRC_RSRC_GRP(IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n, + ipa_src_rsrc_grp_67_rsrc_type_n), + IPA_REG_SAVE_CFG_ENTRY_SRC_RSRC_GRP(IPA_SRC_RSRC_TYPE_AMOUNT_n, + ipa_src_rsrc_type_amount), +#endif + + /* Destination Resource Group Config Registers */ + IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_GRP(IPA_DST_RSRC_GRP_01_RSRC_TYPE_n, + ipa_dst_rsrc_grp_01_rsrc_type_n), + IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_GRP(IPA_DST_RSRC_GRP_23_RSRC_TYPE_n, + ipa_dst_rsrc_grp_23_rsrc_type_n), + IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_GRP(IPA_DST_RSRC_GRP_45_RSRC_TYPE_n, + ipa_dst_rsrc_grp_45_rsrc_type_n), +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_GRP(IPA_DST_RSRC_GRP_67_RSRC_TYPE_n, + ipa_dst_rsrc_grp_67_rsrc_type_n), + IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_GRP(IPA_DST_RSRC_TYPE_AMOUNT_n, + ipa_dst_rsrc_type_amount), +#endif + + /* Source Resource Group Count Registers */ + IPA_REG_SAVE_CFG_ENTRY_SRC_RSRC_CNT_GRP( + IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n, + ipa_src_rsrc_grp_0123_rsrc_type_cnt_n), + IPA_REG_SAVE_CFG_ENTRY_SRC_RSRC_CNT_GRP( + IPA_SRC_RSRC_GRP_4567_RSRC_TYPE_CNT_n, + ipa_src_rsrc_grp_4567_rsrc_type_cnt_n), + + /* Destination Resource Group Count Registers */ + IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_CNT_GRP( + IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n, + ipa_dst_rsrc_grp_0123_rsrc_type_cnt_n), + IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_CNT_GRP( + IPA_DST_RSRC_GRP_4567_RSRC_TYPE_CNT_n, + ipa_dst_rsrc_grp_4567_rsrc_type_cnt_n), + + /* + * ===================================================================== + * GSI register definitions begin here... + * ===================================================================== + */ + + /* GSI General Registers */ + GEN_SRC_DST_ADDR_MAP(GSI_CFG, + gsi.gen, + gsi_cfg), + GEN_SRC_DST_ADDR_MAP(GSI_REE_CFG, + gsi.gen, + gsi_ree_cfg), + IPA_REG_SAVE_GSI_VER( + IPA_GSI_TOP_GSI_INST_RAM_n, + ipa_gsi_top_gsi_inst_ram_n), + + /* GSI Debug Registers */ + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_DEBUG_BUSY_REG, + gsi.debug, + ipa_gsi_top_gsi_debug_busy_reg), +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_DEBUG_EVENT_PENDING, + gsi.debug, + ipa_gsi_top_gsi_debug_event_pending), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_DEBUG_TIMER_PENDING, + gsi.debug, + ipa_gsi_top_gsi_debug_timer_pending), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_DEBUG_RD_WR_PENDING, + gsi.debug, + ipa_gsi_top_gsi_debug_rd_wr_pending), +#endif + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW, + gsi.debug, + ipa_gsi_top_gsi_debug_pc_from_sw), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_DEBUG_SW_STALL, + gsi.debug, + ipa_gsi_top_gsi_debug_sw_stall), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG, + gsi.debug, + ipa_gsi_top_gsi_debug_pc_for_debug), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID, + gsi.debug, + ipa_gsi_top_gsi_debug_qsb_log_err_trns_id), +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + GEN_SRC_DST_ADDR_MAP(GSI_MCS_PROFILING_BP_CNT_LSB, + gsi.debug.gsi_mcs_prof_regs, + gsi_top_gsi_mcs_profiling_bp_cnt_lsb), + GEN_SRC_DST_ADDR_MAP(GSI_MCS_PROFILING_BP_CNT_MSB, + gsi.debug.gsi_mcs_prof_regs, + gsi_top_gsi_mcs_profiling_bp_cnt_msb), + GEN_SRC_DST_ADDR_MAP(GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB, + gsi.debug.gsi_mcs_prof_regs, + gsi_top_gsi_mcs_profiling_bp_and_pending_cnt_lsb), + GEN_SRC_DST_ADDR_MAP(GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB, + gsi.debug.gsi_mcs_prof_regs, + gsi_top_gsi_mcs_profiling_bp_and_pending_cnt_msb), + GEN_SRC_DST_ADDR_MAP(GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB, + gsi.debug.gsi_mcs_prof_regs, + gsi_top_gsi_mcs_profiling_mcs_busy_cnt_lsb), + GEN_SRC_DST_ADDR_MAP(GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB, + gsi.debug.gsi_mcs_prof_regs, + gsi_top_gsi_mcs_profiling_mcs_busy_cnt_msb), + GEN_SRC_DST_ADDR_MAP(GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB, + gsi.debug.gsi_mcs_prof_regs, + gsi_top_gsi_mcs_profiling_mcs_idle_cnt_lsb), + GEN_SRC_DST_ADDR_MAP(GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB, + gsi.debug.gsi_mcs_prof_regs, + gsi_top_gsi_mcs_profiling_mcs_idle_cnt_msb), +#endif + IPA_REG_SAVE_CFG_ENTRY_GSI_QSB_DEBUG( + GSI_DEBUG_QSB_LOG_LAST_MISC_IDn, qsb_log_last_misc), + + /* GSI IRAM pointers Registers */ + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD, + gsi.debug.gsi_iram_ptrs, + ipa_gsi_top_gsi_iram_ptr_ch_cmd), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD, + gsi.debug.gsi_iram_ptrs, + ipa_gsi_top_gsi_iram_ptr_ee_generic_cmd), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB, + gsi.debug.gsi_iram_ptrs, + ipa_gsi_top_gsi_iram_ptr_ch_db), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB, + gsi.debug.gsi_iram_ptrs, + ipa_gsi_top_gsi_iram_ptr_ev_db), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE, + gsi.debug.gsi_iram_ptrs, + ipa_gsi_top_gsi_iram_ptr_new_re), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP, + gsi.debug.gsi_iram_ptrs, + ipa_gsi_top_gsi_iram_ptr_ch_dis_comp), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY, + gsi.debug.gsi_iram_ptrs, + ipa_gsi_top_gsi_iram_ptr_ch_empty), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP, + gsi.debug.gsi_iram_ptrs, + ipa_gsi_top_gsi_iram_ptr_event_gen_comp), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED, + gsi.debug.gsi_iram_ptrs, + ipa_gsi_top_gsi_iram_ptr_timer_expired), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP, + gsi.debug.gsi_iram_ptrs, + ipa_gsi_top_gsi_iram_ptr_write_eng_comp), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP, + gsi.debug.gsi_iram_ptrs, + ipa_gsi_top_gsi_iram_ptr_read_eng_comp), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT, + gsi.debug.gsi_iram_ptrs, + ipa_gsi_top_gsi_iram_ptr_uc_gp_int), +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPPED, + gsi.debug.gsi_iram_ptrs, + ipa_gsi_top_gsi_iram_ptr_int_mod_stopped), +#else + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPED, + gsi.debug.gsi_iram_ptrs, + ipa_gsi_top_gsi_iram_ptr_int_mod_stoped), +#endif + + /* GSI SHRAM pointers Registers */ + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR, + gsi.debug.gsi_shram_ptrs, + ipa_gsi_top_gsi_shram_ptr_ch_cntxt_base_addr), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR, + gsi.debug.gsi_shram_ptrs, + ipa_gsi_top_gsi_shram_ptr_ev_cntxt_base_addr), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR, + gsi.debug.gsi_shram_ptrs, + ipa_gsi_top_gsi_shram_ptr_re_storage_base_addr), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR, + gsi.debug.gsi_shram_ptrs, + ipa_gsi_top_gsi_shram_ptr_re_esc_buf_base_addr), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR, + gsi.debug.gsi_shram_ptrs, + ipa_gsi_top_gsi_shram_ptr_ee_scrach_base_addr), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR, + gsi.debug.gsi_shram_ptrs, + ipa_gsi_top_gsi_shram_ptr_func_stack_base_addr), + + /* + * NOTE: That GEN_SRC_DST_ADDR_MAP() not used below. This is + * because the following registers are not scaler, rather + * they are register arrays... + */ + + /* GSI General EE Registers */ + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(GSI_MANAGER_EE_QOS_n, + gsi_manager_ee_qos_n), + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_GSI_STATUS, + ee_n_gsi_status), + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_CNTXT_TYPE_IRQ, + ee_n_cntxt_type_irq), + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_CNTXT_TYPE_IRQ_MSK, + ee_n_cntxt_type_irq_msk), +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_CNTXT_SRC_GSI_CH_IRQ, + ee_n_cntxt_src_gsi_ch_irq), + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_CNTXT_SRC_EV_CH_IRQ, + ee_n_cntxt_src_ev_ch_irq), + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK, + ee_n_cntxt_src_gsi_ch_irq_msk), + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_CNTXT_SRC_EV_CH_IRQ_MSK, + ee_n_cntxt_src_ev_ch_irq_msk), + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_CNTXT_SRC_IEOB_IRQ, + ee_n_cntxt_src_ieob_irq), + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_CNTXT_SRC_IEOB_IRQ_MSK, + ee_n_cntxt_src_ieob_irq_msk), +#else + GEN_SRC_DST_ADDR_MAP_EE_n_REG_k_ARR(EE_n_CNTXT_SRC_GSI_CH_IRQ_k, + gsi.gen_ee, + ee_n_cntxt_src_gsi_ch_irq_k), + GEN_SRC_DST_ADDR_MAP_EE_n_REG_k_ARR(EE_n_CNTXT_SRC_EV_CH_IRQ_k, + gsi.gen_ee, + ee_n_cntxt_src_ev_ch_irq_k), + GEN_SRC_DST_ADDR_MAP_EE_n_REG_k_ARR(EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k, + gsi.gen_ee, + ee_n_cntxt_src_gsi_ch_irq_msk_k), + GEN_SRC_DST_ADDR_MAP_EE_n_REG_k_ARR(EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k, + gsi.gen_ee, + ee_n_cntxt_src_ev_ch_irq_msk_k), + GEN_SRC_DST_ADDR_MAP_EE_n_REG_k_ARR(EE_n_CNTXT_SRC_IEOB_IRQ_k, + gsi.gen_ee, + ee_n_cntxt_src_ieob_irq_k), + GEN_SRC_DST_ADDR_MAP_EE_n_REG_k_ARR(EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k, + gsi.gen_ee, + ee_n_cntxt_src_ieob_irq_msk_k), +#endif + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_CNTXT_GSI_IRQ_STTS, + ee_n_cntxt_gsi_irq_stts), + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_CNTXT_GLOB_IRQ_STTS, + ee_n_cntxt_glob_irq_stts), + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_ERROR_LOG, + ee_n_error_log), + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_CNTXT_SCRATCH_0, + ee_n_cntxt_scratch_0), + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_CNTXT_SCRATCH_1, + ee_n_cntxt_scratch_1), + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_CNTXT_INTSET, + ee_n_cntxt_intset), + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_CNTXT_MSI_BASE_LSB, + ee_n_cntxt_msi_base_lsb), + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_CNTXT_MSI_BASE_MSB, + ee_n_cntxt_msi_base_msb), + + /* GSI Channel Context Registers */ + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_CNTXT_0, + ee_n_gsi_ch_k_cntxt_0), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_CNTXT_1, + ee_n_gsi_ch_k_cntxt_1), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_CNTXT_2, + ee_n_gsi_ch_k_cntxt_2), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_CNTXT_3, + ee_n_gsi_ch_k_cntxt_3), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_CNTXT_4, + ee_n_gsi_ch_k_cntxt_4), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_CNTXT_5, + ee_n_gsi_ch_k_cntxt_5), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_CNTXT_6, + ee_n_gsi_ch_k_cntxt_6), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_CNTXT_7, + ee_n_gsi_ch_k_cntxt_7), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_RE_FETCH_READ_PTR, + ee_n_gsi_ch_k_re_fetch_read_ptr), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR, + ee_n_gsi_ch_k_re_fetch_write_ptr), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_QOS, + ee_n_gsi_ch_k_qos), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_SCRATCH_0, + ee_n_gsi_ch_k_scratch_0), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_SCRATCH_1, + ee_n_gsi_ch_k_scratch_1), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_SCRATCH_2, + ee_n_gsi_ch_k_scratch_2), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_SCRATCH_3, + ee_n_gsi_ch_k_scratch_3), +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_SCRATCH_4, + ee_n_gsi_ch_k_scratch_4), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_SCRATCH_5, + ee_n_gsi_ch_k_scratch_5), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_SCRATCH_6, + ee_n_gsi_ch_k_scratch_6), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_SCRATCH_7, + ee_n_gsi_ch_k_scratch_7), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_SCRATCH_8, + ee_n_gsi_ch_k_scratch_8), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_SCRATCH_9, + ee_n_gsi_ch_k_scratch_9), +#endif + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(GSI_MAP_EE_n_CH_k_VP_TABLE, + gsi_map_ee_n_ch_k_vp_table), + + /* GSI Channel Event Context Registers */ + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_CNTXT_0, + ee_n_ev_ch_k_cntxt_0), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_CNTXT_1, + ee_n_ev_ch_k_cntxt_1), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_CNTXT_2, + ee_n_ev_ch_k_cntxt_2), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_CNTXT_3, + ee_n_ev_ch_k_cntxt_3), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_CNTXT_4, + ee_n_ev_ch_k_cntxt_4), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_CNTXT_5, + ee_n_ev_ch_k_cntxt_5), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_CNTXT_6, + ee_n_ev_ch_k_cntxt_6), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_CNTXT_7, + ee_n_ev_ch_k_cntxt_7), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_CNTXT_8, + ee_n_ev_ch_k_cntxt_8), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_CNTXT_9, + ee_n_ev_ch_k_cntxt_9), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_CNTXT_10, + ee_n_ev_ch_k_cntxt_10), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_CNTXT_11, + ee_n_ev_ch_k_cntxt_11), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_CNTXT_12, + ee_n_ev_ch_k_cntxt_12), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_CNTXT_13, + ee_n_ev_ch_k_cntxt_13), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_SCRATCH_0, + ee_n_ev_ch_k_scratch_0), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_SCRATCH_1, + ee_n_ev_ch_k_scratch_1), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(GSI_DEBUG_EE_n_EV_k_VP_TABLE, + gsi_debug_ee_n_ev_k_vp_table), + +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 +/* GSI Debug SW MSK Registers */ + IPA_REG_SAVE_GSI_DEBUG_MSK_REG_ENTRY(GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD, + regs), +#endif + +#if defined(CONFIG_IPA3_REGDUMP_NUM_EXTRA_ENDP_REGS) && \ + CONFIG_IPA3_REGDUMP_NUM_EXTRA_ENDP_REGS > 0 + /* Endp Registers for remaining pipes */ + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_INIT_CTRL_n, + ipa_endp_init_ctrl_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_INIT_CTRL_SCND_n, + ipa_endp_init_ctrl_scnd_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_INIT_CFG_n, + ipa_endp_init_cfg_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_INIT_NAT_n, + ipa_endp_init_nat_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_INIT_HDR_n, + ipa_endp_init_hdr_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_INIT_HDR_EXT_n, + ipa_endp_init_hdr_ext_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA + (IPA_ENDP_INIT_HDR_METADATA_MASK_n, + ipa_endp_init_hdr_metadata_mask_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_INIT_HDR_METADATA_n, + ipa_endp_init_hdr_metadata_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_INIT_MODE_n, + ipa_endp_init_mode_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_INIT_AGGR_n, + ipa_endp_init_aggr_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_INIT_HOL_BLOCK_EN_n, + ipa_endp_init_hol_block_en_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_INIT_HOL_BLOCK_TIMER_n, + ipa_endp_init_hol_block_timer_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_INIT_DEAGGR_n, + ipa_endp_init_deaggr_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_STATUS_n, + ipa_endp_status_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_INIT_RSRC_GRP_n, + ipa_endp_init_rsrc_grp_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_INIT_SEQ_n, + ipa_endp_init_seq_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_GSI_CFG_TLV_n, + ipa_endp_gsi_cfg_tlv_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_GSI_CFG_AOS_n, + ipa_endp_gsi_cfg_aos_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_GSI_CFG1_n, + ipa_endp_gsi_cfg1_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA + (IPA_ENDP_FILTER_ROUTER_HSH_CFG_n, + ipa_endp_filter_router_hsh_cfg_n), +#endif +}; + +/* IPA uC PER registers save Cfg array */ +static struct map_src_dst_addr_s ipa_uc_regs_to_save_array[] = { + /* HWP registers */ + GEN_SRC_DST_ADDR_MAP(IPA_UC_QMB_SYS_ADDR, + ipa.hwp, + ipa_uc_qmb_sys_addr), + GEN_SRC_DST_ADDR_MAP(IPA_UC_QMB_LOCAL_ADDR, + ipa.hwp, + ipa_uc_qmb_local_addr), + GEN_SRC_DST_ADDR_MAP(IPA_UC_QMB_LENGTH, + ipa.hwp, + ipa_uc_qmb_length), + GEN_SRC_DST_ADDR_MAP(IPA_UC_QMB_TRIGGER, + ipa.hwp, + ipa_uc_qmb_trigger), +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + GEN_SRC_DST_ADDR_MAP(IPA_UC_QMB_PENDING_TID, + ipa.hwp, + ipa_uc_qmb_pending_tid), + GEN_SRC_DST_ADDR_MAP(IPA_UC_QMB_COMPLETED_RD_FIFO_PEEK, + ipa.hwp, + ipa_uc_qmb_completed_rd_fifo_peek), + GEN_SRC_DST_ADDR_MAP(IPA_UC_QMB_COMPLETED_WR_FIFO_PEEK, + ipa.hwp, + ipa_uc_qmb_completed_wr_fifo_peek), + GEN_SRC_DST_ADDR_MAP(IPA_UC_QMB_MISC, + ipa.hwp, + ipa_uc_qmb_misc), + GEN_SRC_DST_ADDR_MAP(IPA_UC_QMB_STATUS, + ipa.hwp, + ipa_uc_qmb_status), +#endif + GEN_SRC_DST_ADDR_MAP(IPA_UC_QMB_BUS_ATTRIB, + ipa.hwp, + ipa_uc_qmb_bus_attrib), +}; + +static void ipa_hal_save_regs_save_ipa_testbus(void); +static void ipa_reg_save_gsi_fifo_status(void); +static void ipa_reg_save_rsrc_cnts(void); +static void ipa_hal_save_regs_ipa_cmdq(void); +static void ipa_hal_save_regs_rsrc_db(void); +static void ipa_reg_save_anomaly_check(void); + +static struct reg_access_funcs_s *get_access_funcs(u32 addr) +{ + u32 i, asub = ipa3_ctx->sd_state; + + for (i = 0; i < ARRAY_SIZE(mem_access_map); i++) { + if (addr >= mem_access_map[i].addr_range_begin && + addr < mem_access_map[i].addr_range_end) { + return mem_access_map[i].access[asub]; + } + } + + IPAERR("Unknown register offset(0x%08X). Using dflt access methods\n", + addr); + + return &io_matrix[AA_COMBO]; +} + +static u32 in_dword( + u32 addr, + u8 perm) +{ + struct reg_access_funcs_s *io = get_access_funcs(addr); + + if (perm & REG_READ_PERM) { + if (io->read == nop_read) + IPADBG_LOW("nop read action for address 0x%X\n", addr); + return io->read(ipa3_ctx->reg_collection_base + addr); + } else { + IPADBG_LOW("not permitted to read addr 0x%X\n", addr); + return nop_read(ipa3_ctx->reg_collection_base + addr); + } +} + +static u32 in_dword_masked( + u32 addr, + u32 mask, + u8 perm) +{ + struct reg_access_funcs_s *io = get_access_funcs(addr); + u32 val; + + if (perm & REG_READ_PERM) { + if (io->read == nop_read) + IPADBG_LOW("nop read action for address 0x%X\n", addr); + + val = io->read(ipa3_ctx->reg_collection_base + addr); + if (io->read == act_read) + return val & mask; + } else { + IPADBG_LOW("not permitted to read addr 0x%X\n", addr); + val = nop_read(ipa3_ctx->reg_collection_base + addr); + } + + return val; +} + +static void out_dword( + u32 addr, + u32 val, + u8 perm) +{ + struct reg_access_funcs_s *io = get_access_funcs(addr); + + if (perm & REG_WRITE_PERM) { + io->write(ipa3_ctx->reg_collection_base + addr, val); + if (io->write == nop_write) + IPADBG_LOW("nop write action for address 0x%X\n", addr); + } else { + IPADBG_LOW("not permitted to write addr 0x%X\n", addr); + return; + } +} + +/* + * FUNCTION: ipa_save_gsi_ver + * + * Saves the gsi version + * + * @return + * None + */ +void ipa_save_gsi_ver(void) +{ + u32 gsi_fw_ver; + + if (!ipa3_ctx->do_register_collection_on_crash) + return; + + if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0) + gsi_fw_ver = + IPA_READ_1xVECTOR_REG(IPA_GSI_TOP_GSI_INST_RAM_n, 0); + if (ipa3_ctx->ipa_hw_type == IPA_HW_v5_0) + gsi_fw_ver = + IPA_READ_1xVECTOR_REG(IPA_GSI_TOP_GSI_INST_RAM_n, 64); + + ipa_reg_save.gsi.fw_ver.raw_version = gsi_fw_ver; + ipa_reg_save.gsi.fw_ver.hw_version = (gsi_fw_ver & GSI_INST_RAM_FW_VER_HW_MASK) >> + GSI_INST_RAM_FW_VER_HW_SHIFT; + ipa_reg_save.gsi.fw_ver.flavor = (gsi_fw_ver & GSI_INST_RAM_FW_VER_FLAVOR_MASK) >> + GSI_INST_RAM_FW_VER_FLAVOR_SHIFT; + ipa_reg_save.gsi.fw_ver.fw_version = (gsi_fw_ver & GSI_INST_RAM_FW_VER_FW_MASK) >> + GSI_INST_RAM_FW_VER_FW_SHIFT; +} + +/* + * FUNCTION: ipa_save_registers + * + * Saves all the IPA register values which are configured + * + * @return + * None + */ +void ipa_save_registers(void) +{ + u32 i = 0; + u32 phys_ch_idx = 0; + u32 n = 0; + /* Fetch the number of registers configured to be saved */ + u32 num_regs = ARRAY_SIZE(ipa_regs_to_save_array); + u32 num_uc_per_regs = ARRAY_SIZE(ipa_uc_regs_to_save_array); + union ipa_hwio_def_ipa_rsrc_mngr_db_cfg_u for_cfg; + union ipa_hwio_def_ipa_rsrc_mngr_db_rsrc_read_u for_read; + + if (!ipa3_ctx->do_register_collection_on_crash) + return; + + IPAERR("Commencing\n"); + + /* + * Remove the GSI FIFO and the endp registers for extra pipes for + * now. These would be saved later + */ + num_regs -= (CONFIG_IPA3_REGDUMP_NUM_EXTRA_ENDP_REGS * + IPA_REG_SAVE_NUM_EXTRA_ENDP_REGS); + + memset(&for_cfg, 0, sizeof(for_cfg)); + memset(&for_read, 0, sizeof(for_read)); + + IPAERR("reading %d registers\n", num_regs); + /* Now save all the configured registers */ + for (i = 0; i < num_regs; i++) { + /* Copy reg value to our data struct */ + *(ipa_regs_to_save_array[i].dst_addr) = + in_dword(ipa_regs_to_save_array[i].src_addr, + ipa_regs_to_save_array[i].perm); + } + + /* + * Set the active flag for all active pipe indexed registers. + */ + for (i = 0; i < IPA_HW_PIPE_ID_MAX; i++) + ipa_reg_save.ipa.pipes[i].active = true; + + /* Now save the per endp registers for the remaining pipes */ + for (i = 0; i < (CONFIG_IPA3_REGDUMP_NUM_EXTRA_ENDP_REGS * + IPA_REG_SAVE_NUM_EXTRA_ENDP_REGS); i++) { + /* Copy reg value to our data struct */ + *(ipa_regs_to_save_array[num_regs + i].dst_addr) = + in_dword(ipa_regs_to_save_array[num_regs + i].src_addr, + ipa_regs_to_save_array[num_regs + i].perm); + } + + IPA_HW_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA_ACTIVE(); + + num_regs += (CONFIG_IPA3_REGDUMP_NUM_EXTRA_ENDP_REGS * + IPA_REG_SAVE_NUM_EXTRA_ENDP_REGS); + + /* Saving GSI FIFO Status registers */ + ipa_reg_save_gsi_fifo_status(); + + /* + * On targets that support SSR, we generally want to disable + * the following reg save functionality as it may cause stalls + * in IPA after the SSR. + * + * To override this, set do_non_tn_collection_on_crash to + * true, via dtsi, and the collection will be done. + */ + if (ipa3_ctx->do_non_tn_collection_on_crash) { + /* Save all the uC PER configured registers */ + for (i = 0; i < num_uc_per_regs; i++) { + /* Copy reg value to our data struct */ + *(ipa_uc_regs_to_save_array[i].dst_addr) = + in_dword(ipa_uc_regs_to_save_array[i].src_addr, + ipa_uc_regs_to_save_array[i].perm); + } + + /* Saving CMD Queue registers */ + ipa_hal_save_regs_ipa_cmdq(); + + /* Collecting resource DB information */ + ipa_hal_save_regs_rsrc_db(); + + /* Save IPA testbus */ + if (ipa3_ctx->do_testbus_collection_on_crash) + ipa_hal_save_regs_save_ipa_testbus(); + } + + /* GSI test bus */ + for (i = 0; + i < ARRAY_SIZE(ipa_reg_save_gsi_ch_test_bus_selector_array); + i++) { + ipa_reg_save.gsi.debug.gsi_test_bus.test_bus_selector[i] = + ipa_reg_save_gsi_ch_test_bus_selector_array[i]; + + /* Write test bus selector */ + IPA_WRITE_SCALER_REG( + GSI_TEST_BUS_SEL, + ipa_reg_save_gsi_ch_test_bus_selector_array[i]); + + ipa_reg_save.gsi.debug.gsi_test_bus.test_bus_reg[ + i].gsi_testbus_reg = + (u32) IPA_READ_SCALER_REG(GSI_TEST_BUS_REG); + } + + ipa_reg_save_rsrc_cnts(); + + for (i = 0; i < HWIO_GSI_DEBUG_SW_RF_n_READ_MAXn + 1; i++) + ipa_reg_save.gsi.debug.gsi_mcs_regs.mcs_reg[i].rf_reg = + IPA_READ_1xVECTOR_REG(GSI_DEBUG_SW_RF_n_READ, i); + + for (i = 0; i < HWIO_GSI_DEBUG_COUNTERn_MAXn + 1; i++) + ipa_reg_save.gsi.debug.gsi_cnt_regs.cnt[i].counter_value = + (u16)IPA_READ_1xVECTOR_REG(GSI_DEBUG_COUNTERn, i); + + for (i = 0; i < IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_A7; i++) { + phys_ch_idx = ipa_reg_save.gsi.ch_cntxt.a7[ + i].gsi_map_ee_n_ch_k_vp_table.phy_ch; + n = phys_ch_idx * IPA_REG_SAVE_BYTES_PER_CHNL_SHRAM; + + if (!ipa_reg_save.gsi.ch_cntxt.a7[ + i].gsi_map_ee_n_ch_k_vp_table.valid) + continue; + + ipa_reg_save.gsi.ch_cntxt.a7[ + i].mcs_channel_scratch.scratch_for_seq_low.shram = + IPA_READ_1xVECTOR_REG( + GSI_SHRAM_n, + n + IPA_GSI_OFFSET_WORDS_SCRATCH_FOR_SEQ_LOW); + + ipa_reg_save.gsi.ch_cntxt.a7[ + i].mcs_channel_scratch.scratch_for_seq_high.shram = + IPA_READ_1xVECTOR_REG( + GSI_SHRAM_n, + n + IPA_GSI_OFFSET_WORDS_SCRATCH_FOR_SEQ_HIGH); +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + ipa_reg_save.gsi.ch_cntxt.a7[ + i].fc_stats_state.value = IPA_READ_1xVECTOR_REG( + GSI_SHRAM_n, + n + IPA_REG_SAVE_FC_STATE_OFFSET); + } +#endif + + for (i = 0; i < IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_UC; i++) { + phys_ch_idx = ipa_reg_save.gsi.ch_cntxt.uc[ + i].gsi_map_ee_n_ch_k_vp_table.phy_ch; + n = phys_ch_idx * IPA_REG_SAVE_BYTES_PER_CHNL_SHRAM; + + if (!ipa_reg_save.gsi.ch_cntxt.uc[ + i].gsi_map_ee_n_ch_k_vp_table.valid) + continue; + + ipa_reg_save.gsi.ch_cntxt.uc[ + i].mcs_channel_scratch.scratch_for_seq_low.shram = + IPA_READ_1xVECTOR_REG( + GSI_SHRAM_n, + n + IPA_GSI_OFFSET_WORDS_SCRATCH_FOR_SEQ_LOW); + + ipa_reg_save.gsi.ch_cntxt.uc[ + i].mcs_channel_scratch.scratch_for_seq_high.shram = + IPA_READ_1xVECTOR_REG( + GSI_SHRAM_n, + n + IPA_GSI_OFFSET_WORDS_SCRATCH_FOR_SEQ_HIGH); + +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + ipa_reg_save.gsi.ch_cntxt.uc[ + i].fc_stats_state.value = IPA_READ_1xVECTOR_REG( + GSI_SHRAM_n, + n + IPA_REG_SAVE_FC_STATE_OFFSET); + } +#endif + + for (i = 0; i < IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_Q6; i++) { + phys_ch_idx = ipa_reg_save.gsi.ch_cntxt.q6[ + i].gsi_map_ee_n_ch_k_vp_table.phy_ch; + n = phys_ch_idx * IPA_REG_SAVE_BYTES_PER_CHNL_SHRAM; + + if (!ipa_reg_save.gsi.ch_cntxt.q6[ + i].gsi_map_ee_n_ch_k_vp_table.valid) + continue; + + ipa_reg_save.gsi.ch_cntxt.q6[ + i].mcs_channel_scratch.scratch_for_seq_low.shram = + IPA_READ_1xVECTOR_REG( + GSI_SHRAM_n, + n + IPA_GSI_OFFSET_WORDS_SCRATCH_FOR_SEQ_LOW); + + ipa_reg_save.gsi.ch_cntxt.q6[ + i].mcs_channel_scratch.scratch_for_seq_high.shram = + IPA_READ_1xVECTOR_REG( + GSI_SHRAM_n, + n + IPA_GSI_OFFSET_WORDS_SCRATCH_FOR_SEQ_HIGH); + +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + ipa_reg_save.gsi.ch_cntxt.q6[ + i].fc_stats_state.value = IPA_READ_1xVECTOR_REG( + GSI_SHRAM_n, + n + IPA_REG_SAVE_FC_STATE_OFFSET); + } +#endif + + /* + * On targets that support SSR, we generally want to disable + * the following reg save functionality as it may cause stalls + * in IPA after the SSR. + * + * To override this, set do_non_tn_collection_on_crash to + * true, via dtsi, and the collection will be done. + */ + if (ipa3_ctx->do_non_tn_collection_on_crash) { + u32 ofst = GEN_2xVECTOR_REG_OFST(IPA_CTX_ID_m_CTX_NUM_n, 0, 0); + struct reg_access_funcs_s *io = get_access_funcs(ofst); + /* + * If the memory is accessible, copy pkt context directly from + * IPA_CTX_ID register space + */ + if (io->read == act_read) { + for (i = 0; i < IPA_HW_PKT_CTNTX_MAX; i++) { + memcpy((void *)(&(ipa_reg_save.pkt_ctntx[i])), + (void*)(ipa3_ctx->reg_collection_base + HWIO_IPA_CTX_ID_m_CTX_NUM_n_ADDR(i, 0)), + sizeof(ipa_reg_save.pkt_ctntx[0])); + } + + for_cfg.value = + IPA_READ_SCALER_REG(IPA_RSRC_MNGR_DB_CFG); + + for_cfg.def.rsrc_type_sel = 0; + + IPA_MASKED_WRITE_SCALER_REG( + IPA_RSRC_MNGR_DB_CFG, + for_cfg.value); + + for (i = 0; i < IPA_HW_PKT_CTNTX_MAX; i++) { + for_cfg.def.rsrc_id_sel = i; + + IPA_MASKED_WRITE_SCALER_REG( + IPA_RSRC_MNGR_DB_CFG, + for_cfg.value); + + for_read.value = + IPA_READ_SCALER_REG( + IPA_RSRC_MNGR_DB_RSRC_READ); + + if (for_read.def.rsrc_occupied) { + ipa_reg_save.pkt_ctntx_active[i] = true; + ipa_reg_save.pkt_cntxt_state[i] = + (enum ipa_hw_pkt_cntxt_state_e) + ipa_reg_save.pkt_ctntx[i].state; + } + } + } else { + IPAERR("IPA_CTX_ID is not currently accessible\n"); + } + } + + if (ipa3_ctx->do_ram_collection_on_crash) { + for (i = 0; i < IPA_IU_SIZE / sizeof(u32); i++) { + ipa_reg_save.ipa.ipa_iu_ptr[i] = + in_dword(IPA_IU_ADDR + (i * sizeof(u32)), + REG_READ_PERM); + } + for (i = 0; i < IPA_SRAM_SIZE / sizeof(u32); i++) { + ipa_reg_save.ipa.ipa_sram_ptr[i] = + in_dword(IPA_SRAM_ADDR + (i * sizeof(u32)), + REG_READ_PERM); + } + for (i = 0; i < IPA_MBOX_SIZE / sizeof(u32); i++) { + ipa_reg_save.ipa.ipa_mbox_ptr[i] = + in_dword(IPA_MBOX_ADDR + (i * sizeof(u32)), + REG_READ_PERM); + } + for (i = 0; i < IPA_HRAM_SIZE / sizeof(u32); i++) { + ipa_reg_save.ipa.ipa_hram_ptr[i] = + in_dword(IPA_HRAM_ADDR + (i * sizeof(u32)), + REG_READ_PERM); + } + for (i = 0; i < IPA_SEQ_SIZE / sizeof(u32); i++) { + ipa_reg_save.ipa.ipa_seq_ptr[i] = + in_dword(IPA_SEQ_ADDR + (i * sizeof(u32)), + REG_READ_PERM); + } + for (i = 0; i < IPA_GSI_SIZE / sizeof(u32); i++) { + ipa_reg_save.ipa.ipa_gsi_ptr[i] = + in_dword(IPA_GSI_ADDR + (i * sizeof(u32)), + REG_READ_PERM); + } + IPALOG_VnP_ADDRS(ipa_reg_save.ipa.ipa_iu_ptr); + IPALOG_VnP_ADDRS(ipa_reg_save.ipa.ipa_sram_ptr); + IPALOG_VnP_ADDRS(ipa_reg_save.ipa.ipa_mbox_ptr); + IPALOG_VnP_ADDRS(ipa_reg_save.ipa.ipa_hram_ptr); + IPALOG_VnP_ADDRS(ipa_reg_save.ipa.ipa_seq_ptr); + IPALOG_VnP_ADDRS(ipa_reg_save.ipa.ipa_gsi_ptr); + } + + ipa_reg_save_anomaly_check(); + + IPAERR("Completed\n"); +} + +/* + * FUNCTION: ipa_reg_save_gsi_fifo_status + * + * This function saves the GSI FIFO Status registers for all endpoints + * + * @param + * + * @return + */ +static void ipa_reg_save_gsi_fifo_status(void) +{ + u8 i; + for (i = 0; i < IPA_HW_PIPE_ID_MAX; i++) { + memset(&ipa_reg_save.gsi_fifo_status[i].gsi_fifo_status_ctrl, + 0, sizeof(ipa_reg_save.gsi_fifo_status[i].gsi_fifo_status_ctrl)); + + ipa_reg_save.gsi_fifo_status[i].gsi_fifo_status_ctrl.def.ipa_gsi_fifo_status_en = 1; + ipa_reg_save.gsi_fifo_status[i].gsi_fifo_status_ctrl.def.ipa_gsi_fifo_status_port_sel = i; + + IPA_MASKED_WRITE_SCALER_REG(IPA_GSI_FIFO_STATUS_CTRL, + ipa_reg_save.gsi_fifo_status[i].gsi_fifo_status_ctrl.value); + + ipa_reg_save.gsi_fifo_status[i].gsi_tlv_fifo_status.value = + IPA_READ_SCALER_REG(IPA_GSI_TLV_FIFO_STATUS); + ipa_reg_save.gsi_fifo_status[i].gsi_aos_fifo_status.value = + IPA_READ_SCALER_REG(IPA_GSI_AOS_FIFO_STATUS); + } +} + +/* + * FUNCTION: ipa_reg_save_rsrc_cnts + * + * This function saves the resource counts for all PCIE and DDR + * resource groups. + * + * @param + * @return + */ +static void ipa_reg_save_rsrc_cnts(void) +{ + union ipa_hwio_def_ipa_src_rsrc_grp_0123_rsrc_type_cnt_n_u + src_0123_rsrc_cnt; + union ipa_hwio_def_ipa_dst_rsrc_grp_0123_rsrc_type_cnt_n_u + dst_0123_rsrc_cnt; + + ipa_reg_save.rsrc_cnts.pcie.resource_group = IPA_HW_PCIE_SRC_RSRP_GRP; + ipa_reg_save.rsrc_cnts.ddr.resource_group = IPA_HW_DDR_SRC_RSRP_GRP; + + src_0123_rsrc_cnt.value = + IPA_READ_1xVECTOR_REG(IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n, 0); + + ipa_reg_save.rsrc_cnts.pcie.src.pkt_cntxt = + src_0123_rsrc_cnt.def.src_rsrc_grp_0_cnt; + ipa_reg_save.rsrc_cnts.ddr.src.pkt_cntxt = + src_0123_rsrc_cnt.def.src_rsrc_grp_1_cnt; + + src_0123_rsrc_cnt.value = + IPA_READ_1xVECTOR_REG(IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n, 1); + + ipa_reg_save.rsrc_cnts.pcie.src.descriptor_list = + src_0123_rsrc_cnt.def.src_rsrc_grp_0_cnt; + ipa_reg_save.rsrc_cnts.ddr.src.descriptor_list = + src_0123_rsrc_cnt.def.src_rsrc_grp_1_cnt; + + src_0123_rsrc_cnt.value = + IPA_READ_1xVECTOR_REG(IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n, 2); + + ipa_reg_save.rsrc_cnts.pcie.src.data_descriptor_buffer = + src_0123_rsrc_cnt.def.src_rsrc_grp_0_cnt; + ipa_reg_save.rsrc_cnts.ddr.src.data_descriptor_buffer = + src_0123_rsrc_cnt.def.src_rsrc_grp_1_cnt; + + src_0123_rsrc_cnt.value = + IPA_READ_1xVECTOR_REG(IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n, 3); + + ipa_reg_save.rsrc_cnts.pcie.src.hps_dmars = + src_0123_rsrc_cnt.def.src_rsrc_grp_0_cnt; + ipa_reg_save.rsrc_cnts.ddr.src.hps_dmars = + src_0123_rsrc_cnt.def.src_rsrc_grp_1_cnt; + + src_0123_rsrc_cnt.value = + IPA_READ_1xVECTOR_REG(IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n, 4); + + ipa_reg_save.rsrc_cnts.pcie.src.reserved_acks = + src_0123_rsrc_cnt.def.src_rsrc_grp_0_cnt; + ipa_reg_save.rsrc_cnts.ddr.src.reserved_acks = + src_0123_rsrc_cnt.def.src_rsrc_grp_1_cnt; + + dst_0123_rsrc_cnt.value = + IPA_READ_1xVECTOR_REG(IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n, 0); + + ipa_reg_save.rsrc_cnts.pcie.dst.reserved_sectors = + dst_0123_rsrc_cnt.def.dst_rsrc_grp_0_cnt; + ipa_reg_save.rsrc_cnts.ddr.dst.reserved_sectors = + dst_0123_rsrc_cnt.def.dst_rsrc_grp_1_cnt; + + dst_0123_rsrc_cnt.value = + IPA_READ_1xVECTOR_REG(IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n, 1); + + ipa_reg_save.rsrc_cnts.pcie.dst.dps_dmars = + dst_0123_rsrc_cnt.def.dst_rsrc_grp_0_cnt; + ipa_reg_save.rsrc_cnts.ddr.dst.dps_dmars = + dst_0123_rsrc_cnt.def.dst_rsrc_grp_1_cnt; +} + +/* + * FUNCTION: ipa_reg_save_rsrc_cnts_test_bus + * + * This function saves the resource counts for all PCIE and DDR + * resource groups collected from test bus. + * + * @param + * + * @return + */ +void ipa_reg_save_rsrc_cnts_test_bus(void) +{ + int32_t rsrc_type = 0; + + ipa_reg_save.rsrc_cnts.pcie.resource_group = IPA_HW_PCIE_SRC_RSRP_GRP; + ipa_reg_save.rsrc_cnts.ddr.resource_group = IPA_HW_DDR_SRC_RSRP_GRP; + + rsrc_type = 0; + ipa_reg_save.rsrc_cnts.pcie.src.pkt_cntxt = + IPA_DEBUG_TESTBUS_GET_RSRC_TYPE_CNT(rsrc_type, + IPA_HW_PCIE_SRC_RSRP_GRP); + + ipa_reg_save.rsrc_cnts.ddr.src.pkt_cntxt = + IPA_DEBUG_TESTBUS_GET_RSRC_TYPE_CNT(rsrc_type, + IPA_HW_DDR_SRC_RSRP_GRP); + + rsrc_type = 1; + ipa_reg_save.rsrc_cnts.pcie.src.descriptor_list = + IPA_DEBUG_TESTBUS_GET_RSRC_TYPE_CNT(rsrc_type, + IPA_HW_PCIE_SRC_RSRP_GRP); + + ipa_reg_save.rsrc_cnts.ddr.src.descriptor_list = + IPA_DEBUG_TESTBUS_GET_RSRC_TYPE_CNT(rsrc_type, + IPA_HW_DDR_SRC_RSRP_GRP); + + rsrc_type = 2; + ipa_reg_save.rsrc_cnts.pcie.src.data_descriptor_buffer = + IPA_DEBUG_TESTBUS_GET_RSRC_TYPE_CNT(rsrc_type, + IPA_HW_PCIE_SRC_RSRP_GRP); + + ipa_reg_save.rsrc_cnts.ddr.src.data_descriptor_buffer = + IPA_DEBUG_TESTBUS_GET_RSRC_TYPE_CNT(rsrc_type, + IPA_HW_DDR_SRC_RSRP_GRP); + + rsrc_type = 3; + ipa_reg_save.rsrc_cnts.pcie.src.hps_dmars = + IPA_DEBUG_TESTBUS_GET_RSRC_TYPE_CNT(rsrc_type, + IPA_HW_PCIE_SRC_RSRP_GRP); + + ipa_reg_save.rsrc_cnts.ddr.src.hps_dmars = + IPA_DEBUG_TESTBUS_GET_RSRC_TYPE_CNT(rsrc_type, + IPA_HW_DDR_SRC_RSRP_GRP); + + rsrc_type = 4; + ipa_reg_save.rsrc_cnts.pcie.src.reserved_acks = + IPA_DEBUG_TESTBUS_GET_RSRC_TYPE_CNT(rsrc_type, + IPA_HW_PCIE_SRC_RSRP_GRP); + + ipa_reg_save.rsrc_cnts.ddr.src.reserved_acks = + IPA_DEBUG_TESTBUS_GET_RSRC_TYPE_CNT(rsrc_type, + IPA_HW_DDR_SRC_RSRP_GRP); + + rsrc_type = 5; + ipa_reg_save.rsrc_cnts.pcie.dst.reserved_sectors = + IPA_DEBUG_TESTBUS_GET_RSRC_TYPE_CNT(rsrc_type, + IPA_HW_PCIE_DEST_RSRP_GRP); + + ipa_reg_save.rsrc_cnts.ddr.dst.reserved_sectors = + IPA_DEBUG_TESTBUS_GET_RSRC_TYPE_CNT(rsrc_type, + IPA_HW_DDR_DEST_RSRP_GRP); + + rsrc_type = 6; + ipa_reg_save.rsrc_cnts.pcie.dst.dps_dmars = + IPA_DEBUG_TESTBUS_GET_RSRC_TYPE_CNT(rsrc_type, + IPA_HW_PCIE_DEST_RSRP_GRP); + + ipa_reg_save.rsrc_cnts.ddr.dst.dps_dmars = + IPA_DEBUG_TESTBUS_GET_RSRC_TYPE_CNT(rsrc_type, + IPA_HW_DDR_DEST_RSRP_GRP); +} + +/* + * FUNCTION: ipa_hal_save_regs_ipa_cmdq + * + * This function saves the various IPA CMDQ registers + * + * @param + * + * @return + */ +static void ipa_hal_save_regs_ipa_cmdq(void) +{ + int32_t i; + union ipa_hwio_def_ipa_rx_hps_cmdq_cmd_u rx_hps_cmdq_cmd = { { 0 } }; + union ipa_hwio_def_ipa_hps_dps_cmdq_cmd_u hps_dps_cmdq_cmd = { { 0 } }; + union ipa_hwio_def_ipa_dps_tx_cmdq_cmd_u dps_tx_cmdq_cmd = { { 0 } }; + union ipa_hwio_def_ipa_ackmngr_cmdq_cmd_u ackmngr_cmdq_cmd = { { 0 } }; + union ipa_hwio_def_ipa_prod_ackmngr_cmdq_cmd_u + prod_ackmngr_cmdq_cmd = { { 0 } }; + union ipa_hwio_def_ipa_ntf_tx_cmdq_cmd_u ntf_tx_cmdq_cmd = { { 0 } }; + + /* Save RX_HPS CMDQ */ + for (i = 0; i < IPA_DEBUG_CMDQ_HPS_SELECT_NUM_GROUPS; i++) { + rx_hps_cmdq_cmd.def.rd_req = 0; + rx_hps_cmdq_cmd.def.cmd_client = i; + IPA_MASKED_WRITE_SCALER_REG(IPA_RX_HPS_CMDQ_CMD, + rx_hps_cmdq_cmd.value); + ipa_reg_save.ipa.dbg.ipa_rx_hps_cmdq_count_arr[i].value = + IPA_READ_SCALER_REG(IPA_RX_HPS_CMDQ_COUNT); + ipa_reg_save.ipa.dbg.ipa_rx_hps_cmdq_status_arr[i].value = + IPA_READ_SCALER_REG(IPA_RX_HPS_CMDQ_STATUS); + rx_hps_cmdq_cmd.def.rd_req = 1; + rx_hps_cmdq_cmd.def.cmd_client = i; + IPA_MASKED_WRITE_SCALER_REG(IPA_RX_HPS_CMDQ_CMD, + rx_hps_cmdq_cmd.value); + ipa_reg_save.ipa.dbg.ipa_rx_hps_cmdq_data_rd_0_arr[i].value = + IPA_READ_SCALER_REG(IPA_RX_HPS_CMDQ_DATA_RD_0); + ipa_reg_save.ipa.dbg.ipa_rx_hps_cmdq_data_rd_1_arr[i].value = + IPA_READ_SCALER_REG(IPA_RX_HPS_CMDQ_DATA_RD_1); + ipa_reg_save.ipa.dbg.ipa_rx_hps_cmdq_data_rd_2_arr[i].value = + IPA_READ_SCALER_REG(IPA_RX_HPS_CMDQ_DATA_RD_2); + ipa_reg_save.ipa.dbg.ipa_rx_hps_cmdq_data_rd_3_arr[i].value = + IPA_READ_SCALER_REG(IPA_RX_HPS_CMDQ_DATA_RD_3); + } + + /* Save HPS_DPS CMDQ */ + for (i = 0; i < IPA_TESTBUS_SEL_EP_MAX + 1; i++) { + hps_dps_cmdq_cmd.def.rd_req = 0; + hps_dps_cmdq_cmd.def.cmd_client = i; + IPA_MASKED_WRITE_SCALER_REG(IPA_HPS_DPS_CMDQ_CMD, + hps_dps_cmdq_cmd.value); + ipa_reg_save.ipa.dbg.ipa_hps_dps_cmdq_status_arr[i].value = + IPA_READ_SCALER_REG(IPA_HPS_DPS_CMDQ_STATUS); + ipa_reg_save.ipa.dbg.ipa_hps_dps_cmdq_count_arr[i].value = + IPA_READ_SCALER_REG(IPA_HPS_DPS_CMDQ_COUNT); + + hps_dps_cmdq_cmd.def.rd_req = 1; + hps_dps_cmdq_cmd.def.cmd_client = i; + IPA_MASKED_WRITE_SCALER_REG(IPA_HPS_DPS_CMDQ_CMD, + hps_dps_cmdq_cmd.value); + ipa_reg_save.ipa.dbg.ipa_hps_dps_cmdq_data_rd_0_arr[i].value = + IPA_READ_SCALER_REG(IPA_HPS_DPS_CMDQ_DATA_RD_0); + } + + /* Save DPS_TX CMDQ */ + for (i = 0; i < IPA_DEBUG_CMDQ_DPS_SELECT_NUM_GROUPS; i++) { + dps_tx_cmdq_cmd.def.cmd_client = i; + dps_tx_cmdq_cmd.def.rd_req = 0; + IPA_MASKED_WRITE_SCALER_REG(IPA_DPS_TX_CMDQ_CMD, + dps_tx_cmdq_cmd.value); + ipa_reg_save.ipa.dbg.ipa_dps_tx_cmdq_status_arr[i].value = + IPA_READ_SCALER_REG(IPA_DPS_TX_CMDQ_STATUS); + ipa_reg_save.ipa.dbg.ipa_dps_tx_cmdq_count_arr[i].value = + IPA_READ_SCALER_REG(IPA_DPS_TX_CMDQ_COUNT); + + dps_tx_cmdq_cmd.def.cmd_client = i; + dps_tx_cmdq_cmd.def.rd_req = 1; + IPA_MASKED_WRITE_SCALER_REG(IPA_DPS_TX_CMDQ_CMD, + dps_tx_cmdq_cmd.value); + ipa_reg_save.ipa.dbg.ipa_dps_tx_cmdq_data_rd_0_arr[i].value = + IPA_READ_SCALER_REG(IPA_DPS_TX_CMDQ_DATA_RD_0); + } + + /* Save ACKMNGR CMDQ */ + for (i = 0; i < IPA_DEBUG_CMDQ_DPS_SELECT_NUM_GROUPS; i++) { + ackmngr_cmdq_cmd.def.rd_req = 0; + ackmngr_cmdq_cmd.def.cmd_client = i; + IPA_MASKED_WRITE_SCALER_REG(IPA_ACKMNGR_CMDQ_CMD, + ackmngr_cmdq_cmd.value); + ipa_reg_save.ipa.dbg.ipa_ackmngr_cmdq_status_arr[i].value = + IPA_READ_SCALER_REG(IPA_ACKMNGR_CMDQ_STATUS); + ipa_reg_save.ipa.dbg.ipa_ackmngr_cmdq_count_arr[i].value = + IPA_READ_SCALER_REG(IPA_ACKMNGR_CMDQ_COUNT); + + ackmngr_cmdq_cmd.def.rd_req = 1; + ackmngr_cmdq_cmd.def.cmd_client = i; + IPA_MASKED_WRITE_SCALER_REG(IPA_ACKMNGR_CMDQ_CMD, + ackmngr_cmdq_cmd.value); + ipa_reg_save.ipa.dbg.ipa_ackmngr_cmdq_data_rd_arr[i].value = + IPA_READ_SCALER_REG(IPA_ACKMNGR_CMDQ_DATA_RD); + } + + /* Save PROD ACKMNGR CMDQ */ + for (i = 0; i < IPA_TESTBUS_SEL_EP_MAX + 1; i++) { + prod_ackmngr_cmdq_cmd.def.rd_req = 0; + prod_ackmngr_cmdq_cmd.def.cmd_client = i; + IPA_MASKED_WRITE_SCALER_REG(IPA_PROD_ACKMNGR_CMDQ_CMD, + prod_ackmngr_cmdq_cmd.value); + ipa_reg_save.ipa.dbg.ipa_prod_ackmngr_cmdq_status_arr[i].value + = IPA_READ_SCALER_REG( + IPA_PROD_ACKMNGR_CMDQ_STATUS); + ipa_reg_save.ipa.dbg.ipa_prod_ackmngr_cmdq_count_arr[i].value = + IPA_READ_SCALER_REG(IPA_PROD_ACKMNGR_CMDQ_COUNT); + prod_ackmngr_cmdq_cmd.def.rd_req = 1; + prod_ackmngr_cmdq_cmd.def.cmd_client = i; + IPA_MASKED_WRITE_SCALER_REG(IPA_PROD_ACKMNGR_CMDQ_CMD, + prod_ackmngr_cmdq_cmd.value); + ipa_reg_save.ipa.dbg.ipa_prod_ackmngr_cmdq_data_rd_arr[ + i].value = + IPA_READ_SCALER_REG( + IPA_PROD_ACKMNGR_CMDQ_DATA_RD); + } + + /* Save NTF_TX CMDQ */ + for (i = 0; i < IPA_TESTBUS_SEL_EP_MAX + 1; i++) { + ntf_tx_cmdq_cmd.def.rd_req = 0; + ntf_tx_cmdq_cmd.def.cmd_client = i; + IPA_MASKED_WRITE_SCALER_REG(IPA_NTF_TX_CMDQ_CMD, + ntf_tx_cmdq_cmd.value); + ipa_reg_save.ipa.dbg.ipa_ntf_tx_cmdq_status_arr[i].value = + IPA_READ_SCALER_REG(IPA_NTF_TX_CMDQ_STATUS); + ipa_reg_save.ipa.dbg.ipa_ntf_tx_cmdq_count_arr[i].value = + IPA_READ_SCALER_REG(IPA_NTF_TX_CMDQ_COUNT); + ntf_tx_cmdq_cmd.def.rd_req = 1; + ntf_tx_cmdq_cmd.def.cmd_client = i; + IPA_MASKED_WRITE_SCALER_REG(IPA_NTF_TX_CMDQ_CMD, + ntf_tx_cmdq_cmd.value); + ipa_reg_save.ipa.dbg.ipa_ntf_tx_cmdq_data_rd_0_arr[i].value = + IPA_READ_SCALER_REG(IPA_NTF_TX_CMDQ_DATA_RD_0); + } +} + +/* + * FUNCTION: ipa_hal_save_regs_save_ipa_testbus + * + * This function saves the IPA testbus + * + * @param + * + * @return + */ +static void ipa_hal_save_regs_save_ipa_testbus(void) +{ + s32 sel_internal, sel_external, sel_ep; + union ipa_hwio_def_ipa_testbus_sel_u testbus_sel = { { 0 } }; + + if (ipa_reg_save.ipa.testbus == NULL) { + /* + * Test-bus structure not allocated - exit test-bus collection + */ + IPADBG("ipa_reg_save.ipa.testbus was not allocated\n"); + return; + } + + /* Enable Test-bus */ + testbus_sel.value = 0; + testbus_sel.def.testbus_en = true; + + IPA_WRITE_SCALER_REG(IPA_TESTBUS_SEL, testbus_sel.value); + + for (sel_external = 0; + sel_external <= IPA_TESTBUS_SEL_EXTERNAL_MAX; + sel_external++) { + + for (sel_internal = 0; + sel_internal <= IPA_TESTBUS_SEL_INTERNAL_MAX; + sel_internal++) { + + testbus_sel.value = 0; +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + testbus_sel.def.pipe_select = 0; +#endif + testbus_sel.def.external_block_select = + sel_external; + testbus_sel.def.internal_block_select = + sel_internal; + + IPA_MASKED_WRITE_SCALER_REG( + IPA_TESTBUS_SEL, + testbus_sel.value); + + ipa_reg_save.ipa.testbus->global.global[ + sel_internal][sel_external].testbus_sel.value = + testbus_sel.value; + + ipa_reg_save.ipa.testbus->global.global[ + sel_internal][sel_external].testbus_data.value = + IPA_READ_SCALER_REG(IPA_DEBUG_DATA); + } + } + + /* Collect per EP test bus */ + for (sel_ep = 0; + sel_ep <= IPA_TESTBUS_SEL_EP_MAX; + sel_ep++) { + + for (sel_external = 0; + sel_external <= + IPA_TESTBUS_SEL_EXTERNAL_MAX; + sel_external++) { + + for (sel_internal = 0; + sel_internal <= + IPA_TESTBUS_SEL_INTERNAL_PIPE_MAX; + sel_internal++) { + + testbus_sel.value = 0; +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + testbus_sel.def.pipe_select = sel_ep; +#endif + testbus_sel.def.external_block_select = + sel_external; + testbus_sel.def.internal_block_select = + sel_internal; + + IPA_MASKED_WRITE_SCALER_REG( + IPA_TESTBUS_SEL, + testbus_sel.value); + + ipa_reg_save.ipa.testbus->ep[sel_ep].entry_ep[ + sel_internal][sel_external]. + testbus_sel.value = + testbus_sel.value; + + ipa_reg_save.ipa.testbus->ep[sel_ep].entry_ep[ + sel_internal][sel_external]. + testbus_data.value = + IPA_READ_SCALER_REG( + IPA_DEBUG_DATA); + } + } + } + + /* Disable Test-bus */ + testbus_sel.value = 0; + + IPA_WRITE_SCALER_REG( + IPA_TESTBUS_SEL, + testbus_sel.value); +} + +/* + * FUNCTION: ipa_reg_save_init + * + * This function initializes and memsets the register save struct. + * + * @param + * + * @return + */ +int ipa_reg_save_init(u32 value) +{ + u32 i, num_regs = ARRAY_SIZE(ipa_regs_to_save_array); + + if (!ipa3_ctx->do_register_collection_on_crash) + return 0; + + memset(&ipa_reg_save, value, sizeof(ipa_reg_save)); + + ipa_reg_save.ipa.testbus = NULL; + + if (ipa3_ctx->do_testbus_collection_on_crash) { + memset(ipa_testbus_mem, value, sizeof(ipa_testbus_mem)); + ipa_reg_save.ipa.testbus = + (struct ipa_reg_save_ipa_testbus_s *) ipa_testbus_mem; + } + + /* setup access for register collection/dump on crash */ + IPADBG("Mapping 0x%x bytes starting at 0x%x\n", + ipa3_ctx->entire_ipa_block_size, + ipa3_ctx->ipa_wrapper_base); + + ipa3_ctx->reg_collection_base = + ioremap(ipa3_ctx->ipa_wrapper_base, + ipa3_ctx->entire_ipa_block_size); + + if (!ipa3_ctx->reg_collection_base) { + IPAERR(":register collection ioremap err\n"); + goto alloc_fail1; + } + + num_regs -= + (CONFIG_IPA3_REGDUMP_NUM_EXTRA_ENDP_REGS * + IPA_REG_SAVE_NUM_EXTRA_ENDP_REGS); + + for (i = 0; + i < (CONFIG_IPA3_REGDUMP_NUM_EXTRA_ENDP_REGS * + IPA_REG_SAVE_NUM_EXTRA_ENDP_REGS); + i++) + *(ipa_regs_to_save_array[num_regs + i].dst_addr) = 0x0; + + ipa_reg_save.ipa.ipa_gsi_ptr = NULL; + ipa_reg_save.ipa.ipa_seq_ptr = NULL; + ipa_reg_save.ipa.ipa_hram_ptr = NULL; + ipa_reg_save.ipa.ipa_mbox_ptr = NULL; + ipa_reg_save.ipa.ipa_sram_ptr = NULL; + ipa_reg_save.ipa.ipa_iu_ptr = NULL; + + if (ipa3_ctx->do_ram_collection_on_crash) { + ipa_reg_save.ipa.ipa_iu_ptr = + alloc_and_init(IPA_IU_SIZE, value); + if (!ipa_reg_save.ipa.ipa_iu_ptr) { + IPAERR("ipa_iu_ptr memory alloc failed\n"); + goto alloc_fail2; + } + + ipa_reg_save.ipa.ipa_sram_ptr = + alloc_and_init(IPA_SRAM_SIZE, value); + if (!ipa_reg_save.ipa.ipa_sram_ptr) { + IPAERR("ipa_sram_ptr memory alloc failed\n"); + goto alloc_fail2; + } + + ipa_reg_save.ipa.ipa_mbox_ptr = + alloc_and_init(IPA_MBOX_SIZE, value); + if (!ipa_reg_save.ipa.ipa_mbox_ptr) { + IPAERR("ipa_mbox_ptr memory alloc failed\n"); + goto alloc_fail2; + } + + ipa_reg_save.ipa.ipa_hram_ptr = + alloc_and_init(IPA_HRAM_SIZE, value); + if (!ipa_reg_save.ipa.ipa_hram_ptr) { + IPAERR("ipa_hram_ptr memory alloc failed\n"); + goto alloc_fail2; + } + + ipa_reg_save.ipa.ipa_seq_ptr = + alloc_and_init(IPA_SEQ_SIZE, value); + if (!ipa_reg_save.ipa.ipa_seq_ptr) { + IPAERR("ipa_seq_ptr memory alloc failed\n"); + goto alloc_fail2; + } + + ipa_reg_save.ipa.ipa_gsi_ptr = + alloc_and_init(IPA_GSI_SIZE, value); + if (!ipa_reg_save.ipa.ipa_gsi_ptr) { + IPAERR("ipa_gsi_ptr memory alloc failed\n"); + goto alloc_fail2; + } + } + + return 0; + +alloc_fail2: + kfree(ipa_reg_save.ipa.ipa_seq_ptr); + kfree(ipa_reg_save.ipa.ipa_hram_ptr); + kfree(ipa_reg_save.ipa.ipa_mbox_ptr); + kfree(ipa_reg_save.ipa.ipa_sram_ptr); + kfree(ipa_reg_save.ipa.ipa_iu_ptr); + iounmap(ipa3_ctx->reg_collection_base); +alloc_fail1: + return -ENOMEM; +} + +/* + * FUNCTION: ipa_hal_save_regs_rsrc_db + * + * This function saves the various IPA RSRC_MNGR_DB registers + * + * @param + * + * @return + */ +static void ipa_hal_save_regs_rsrc_db(void) +{ + u32 rsrc_type = 0; + u32 rsrc_id = 0; + u32 rsrc_group = 0; + union ipa_hwio_def_ipa_rsrc_mngr_db_cfg_u + ipa_rsrc_mngr_db_cfg = { { 0 } }; + + ipa_rsrc_mngr_db_cfg.def.rsrc_grp_sel = rsrc_group; + + for (rsrc_type = 0; rsrc_type <= IPA_RSCR_MNGR_DB_RSRC_TYPE_MAX; + rsrc_type++) { + for (rsrc_id = 0; rsrc_id <= IPA_RSCR_MNGR_DB_RSRC_ID_MAX; + rsrc_id++) { + ipa_rsrc_mngr_db_cfg.def.rsrc_id_sel = rsrc_id; + ipa_rsrc_mngr_db_cfg.def.rsrc_type_sel = rsrc_type; + IPA_MASKED_WRITE_SCALER_REG(IPA_RSRC_MNGR_DB_CFG, + ipa_rsrc_mngr_db_cfg.value); + ipa_reg_save.ipa.dbg.ipa_rsrc_mngr_db_rsrc_read_arr + [rsrc_type][rsrc_id].value = + IPA_READ_SCALER_REG( + IPA_RSRC_MNGR_DB_RSRC_READ); + ipa_reg_save.ipa.dbg.ipa_rsrc_mngr_db_list_read_arr + [rsrc_type][rsrc_id].value = + IPA_READ_SCALER_REG( + IPA_RSRC_MNGR_DB_LIST_READ); + } + } +} + +/* + * FUNCTION: ipa_reg_save_anomaly_check + * + * Checks RX state and TX state upon crash dump collection and prints + * anomalies. + * + * TBD- Add more anomaly checks in the future. + * + * @return + */ +static void ipa_reg_save_anomaly_check(void) +{ + if ((ipa_reg_save.ipa.gen.ipa_state.rx_wait != 0) + || (ipa_reg_save.ipa.gen.ipa_state.rx_idle != 1)) { +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + IPADBG( + "RX ACTIVITY, ipa_state.rx_wait = %d, ipa_state.rx_idle = %d, ipa_state_rx_active.endpoints = %d (bitmask)\n", + ipa_reg_save.ipa.gen.ipa_state.rx_wait, + ipa_reg_save.ipa.gen.ipa_state.rx_idle, + ipa_reg_save.ipa.gen.ipa_state_rx_active.endpoints); +#else + int i = 0; + + for (i = 0; i < GEN_MAX_n(IPA_STATE_RX_ACTIVE_n) + 1; i++) { + IPADBG( + "RX ACTIVITY_%d, ipa_state.rx_wait = %d, ipa_state.rx_idle = %d, ipa_state_rx_active.endpoints = %d (bitmask)\n", + i, + ipa_reg_save.ipa.gen.ipa_state.rx_wait, + ipa_reg_save.ipa.gen.ipa_state.rx_idle, + ipa_reg_save.ipa.gen.ipa_state_rx_active_n[i].endpoints); + } +#endif + + if (ipa_reg_save.ipa.gen.ipa_state.tx_idle != 1) { + IPADBG( + "TX ACTIVITY, ipa_state.idle = %d, ipa_state_tx_wrapper.tx0_idle = %d, ipa_state_tx_wrapper.tx1_idle = %d\n", + ipa_reg_save.ipa.gen.ipa_state.tx_idle, + ipa_reg_save.ipa.gen.ipa_state_tx_wrapper.tx0_idle, + ipa_reg_save.ipa.gen.ipa_state_tx_wrapper.tx1_idle); +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + IPADBG( + "ipa_state_tx0.last_cmd_pipe = %d, ipa_state_tx1.last_cmd_pipe = %d\n", + ipa_reg_save.ipa.gen.ipa_state_tx0.last_cmd_pipe, + ipa_reg_save.ipa.gen.ipa_state_tx1.last_cmd_pipe); +#endif + } + } +} diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.0/ipa_reg_dump.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.0/ipa_reg_dump.h new file mode 100644 index 0000000000..398914f209 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.0/ipa_reg_dump.h @@ -0,0 +1,2215 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + */ +#if !defined(_IPA_REG_DUMP_H_) +#define _IPA_REG_DUMP_H_ + +#include +#include + +#include "ipa_i.h" +#include "gsihal.h" +#include "gsihal_reg.h" + +#include "ipa_pkt_cntxt.h" +#include "ipa_hw_common_ex.h" + +#define IPA_0_IPA_WRAPPER_BASE 0 /* required by following includes */ + +#include "ipa_hwio.h" +#include "gsi_hwio.h" +#include "ipa_gcc_hwio.h" + +#include "ipa_hwio_def.h" +#include "gsi_hwio_def.h" +#include "ipa_gcc_hwio_def.h" + +#define IPA_DEBUG_CMDQ_DPS_SELECT_NUM_GROUPS 0x6 +#define IPA_DEBUG_CMDQ_HPS_SELECT_NUM_GROUPS 0x4 +#define IPA_DEBUG_TESTBUS_RSRC_NUM_EP 7 +#define IPA_DEBUG_TESTBUS_RSRC_NUM_GRP 3 +#define IPA_TESTBUS_SEL_EP_MAX 0x1F +#define IPA_TESTBUS_SEL_EXTERNAL_MAX 0x40 +#define IPA_TESTBUS_SEL_INTERNAL_MAX 0xFF +#define IPA_TESTBUS_SEL_INTERNAL_PIPE_MAX 0x40 +#define IPA_DEBUG_CMDQ_ACK_SELECT_NUM_GROUPS 0x9 +#define IPA_RSCR_MNGR_DB_RSRC_ID_MAX 0x3F +#define IPA_RSCR_MNGR_DB_RSRC_TYPE_MAX 0xA +#define IPA_REG_SAVE_FC_STATE_OFFSET 7 +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_ZEROS (0x0) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MCS_0 (0x1) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MCS_1 (0x2) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MCS_2 (0x3) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MCS_3 (0x4) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MCS_4 (0x5) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_DB_ENG (0x9) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_0 (0xB) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_1 (0xC) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_2 (0xD) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_3 (0xE) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_4 (0xF) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_5 (0x10) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_6 (0x11) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_7 (0x12) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_EVE_0 (0x13) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_EVE_1 (0x14) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_EVE_2 (0x15) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_EVE_3 (0x16) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_EVE_4 (0x17) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_EVE_5 (0x18) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IE_0 (0x1B) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IE_1 (0x1C) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IC_0 (0x1F) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IC_1 (0x20) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IC_2 (0x21) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IC_3 (0x22) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IC_4 (0x23) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MOQA_0 (0x27) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MOQA_1 (0x28) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MOQA_2 (0x29) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MOQA_3 (0x2A) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_TMR_0 (0x2B) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_TMR_1 (0x2C) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_TMR_2 (0x2D) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_TMR_3 (0x2E) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_RD_WR_0 (0x33) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_RD_WR_1 (0x34) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_RD_WR_2 (0x35) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_RD_WR_3 (0x36) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_CSR (0x3A) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_SDMA_0 (0x3C) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_SDMA_1 (0x3D) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IE_2 (0x1D) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_CSR_1 (0x3E) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_CSR_2 (0x3F) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MCS_5 (0x40) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IC_5 (0x41) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_CSR_3 (0x42) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_TLV_0 (0x43) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_8 (0x44) +#define IPA_DEBUG_TESTBUS_DEF_EXTERNAL 50 +#define IPA_DEBUG_TESTBUS_DEF_INTERNAL 6 +#define IPA_REG_SAVE_GSI_NUM_EE 3 +#define IPA_REG_SAVE_NUM_EXTRA_ENDP_REGS 22 +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 +#define IPA_GSI_OFFSET_WORDS_SCRATCH_FOR_SEQ_LOW 18 +#define IPA_GSI_OFFSET_WORDS_SCRATCH_FOR_SEQ_HIGH 19 +#else +#define IPA_GSI_OFFSET_WORDS_SCRATCH_FOR_SEQ_LOW 6 +#define IPA_GSI_OFFSET_WORDS_SCRATCH_FOR_SEQ_HIGH 7 +#endif +#define IPA_DEBUG_TESTBUS_RSRC_TYPE_CNT_BIT_MASK 0x7E000 +#define IPA_DEBUG_TESTBUS_RSRC_TYPE_CNT_SHIFT 13 +#define IPA_REG_SAVE_HWP_GSI_EE 2 +#define GSI_HW_DEBUG_SW_MSK_REG_ARRAY_LENGTH 9 +#define GSI_HW_DEBUG_SW_MSK_REG_MAXk 2 + +/* + * A structure used to map a source address to destination address... + */ +struct map_src_dst_addr_s { + u32 src_addr; /* register offset to copy value from */ + u32 *dst_addr; /* memory address to copy register value to */ + u8 perm; /* r\w permission as parsed from hwio */ +}; + +/* a macro to generate a number of MAX n allowed in a register + * who has suffix of _n + */ +#define GEN_MAX_n(reg_name) \ + HWIO_ ## reg_name ## _MAXn + +/* a macro to generate a number of MAX k allowed in a register + * who has suffix of _k + */ +#define GEN_MAX_k(reg_name) \ + HWIO_ ## reg_name ## _MAXk + +/* + * A macro to generate the names of scaler (ie. non-vector) registers + * that reside in the *hwio.h files (said files contain the manifest + * constants for the registers' offsets in the register memory map). + */ +#define GEN_SCALER_REG_OFST(reg_name) \ + (HWIO_ ## reg_name ## _ADDR) + +/* + * A macro designed to generate the rmsk associated with reg_name + */ +#define GEN_SCALER_REG_RMSK(reg_name) \ + (HWIO_ ## reg_name ## _RMSK) + +/* + * A macro designed to generate the attr associated with reg_name + * this is actually r\w permissions, bits [1][0] ==> [W][R] + */ +#define REG_READ_PERM BIT(0) +#define REG_WRITE_PERM BIT(1) +#define GEN_REG_ATTR(reg_name) \ + (HWIO_ ## reg_name ## _ATTR) + +/* + * A macro to generate the names of vector registers that reside in + * the *hwio.h files (said files contain the manifest constants for + * the registers' offsets in the register memory map). More + * specifically, this macro will generate access to registers that are + * addressed via one dimension. + */ +#define GEN_1xVECTOR_REG_OFST(reg_name, row) \ + (HWIO_ ## reg_name ## _ADDR(row)) + +/* + * A macro to generate the names of vector registers that reside in + * the *hwio.h files (said files contain the manifest constants for + * the registers' offsets in the register memory map). More + * specifically, this macro will generate access to registers that are + * addressed via two dimensions. + */ +#define GEN_2xVECTOR_REG_OFST(reg_name, row, col) \ + (HWIO_ ## reg_name ## _ADDR(row, col)) + +/* + * A macro to generate the access to scaler registers that reside in + * the *hwio.h files (said files contain the manifest constants for + * the registers' offsets in the register memory map). More + * specifically, this macro will generate read access from a scaler + * register.. + */ +#define IPA_READ_SCALER_REG(reg_name) \ + HWIO_ ## reg_name ## _IN + +/* + * A macro to generate the access to vector registers that reside in + * the *hwio.h files (said files contain the manifest constants for + * the registers' offsets in the register memory map). More + * specifically, this macro will generate read access from a one + * dimensional vector register... + */ +#define IPA_READ_1xVECTOR_REG(reg_name, row) \ + HWIO_ ## reg_name ## _INI(row) + +/* + * A macro to generate the access to vector registers that reside in + * the *hwio.h files (said files contain the manifest constants for + * the registers' offsets in the register memory map). More + * specifically, this macro will generate read access from a two + * dimensional vector register... + */ +#define IPA_READ_2xVECTOR_REG(reg_name, row, col) \ + HWIO_ ## reg_name ## _INI2(row, col) + +/* + * A macro to generate the access to scaler registers that reside in + * the *hwio.h files (said files contain the manifest constants for + * the registers' offsets in the register memory map). More + * specifically, this macro will generate write access to a scaler + * register.. + */ +#define IPA_WRITE_SCALER_REG(reg_name, val) \ + HWIO_ ## reg_name ## _OUT(val) + +/* + * Similar to the above, but with val masked by the register's rmsk... + */ +#define IPA_MASKED_WRITE_SCALER_REG(reg_name, val) \ + out_dword(GEN_SCALER_REG_OFST(reg_name), \ + (GEN_SCALER_REG_RMSK(reg_name) & val), \ + GEN_REG_ATTR(reg_name)) + +/* + * A macro to generate the access to vector registers that reside in + * the *hwio.h files (said files contain the manifest constants for + * the registers' offsets in the register memory map). More + * specifically, this macro will generate write access to a one + * dimensional vector register... + */ +#define IPA_WRITE_1xVECTOR_REG(reg_name, row, val) \ + HWIO_ ## reg_name ## _OUTI(row, val) + +/* + * A macro to generate the access to vector registers that reside in + * the *hwio.h files (said files contain the manifest constants for + * the registers' offsets in the register memory map). More + * specifically, this macro will generate write access to a two + * dimensional vector register... + */ +#define IPA_WRITE_2xVECTOR_REG(reg_name, row, col, val) \ + HWIO_ ## reg_name ## _OUTI2(row, col, val) + + /* + * Macro that helps generate a mapping between a register's address + * and where the register's value will get stored (ie. source and + * destination address mapping) upon dump... + */ +#define GEN_SRC_DST_ADDR_MAP(reg_name, sub_struct, field_name) \ + { GEN_SCALER_REG_OFST(reg_name), \ + (u32 *)&ipa_reg_save.sub_struct.field_name , \ + GEN_REG_ATTR(reg_name) } + +/* + * Macro to get value of bits 18:13, used tp get rsrc cnts from + * IPA_DEBUG_DATA + */ +#define IPA_DEBUG_TESTBUS_DATA_GET_RSRC_CNT_BITS_FROM_DEBUG_DATA(x) \ + ((x & IPA_DEBUG_TESTBUS_RSRC_TYPE_CNT_BIT_MASK) >> \ + IPA_DEBUG_TESTBUS_RSRC_TYPE_CNT_SHIFT) + +/* + * Macro to get rsrc cnt of specific rsrc type and rsrc grp from test + * bus collected data + */ +#define IPA_DEBUG_TESTBUS_GET_RSRC_TYPE_CNT(rsrc_type, rsrc_grp) \ + IPA_DEBUG_TESTBUS_DATA_GET_RSRC_CNT_BITS_FROM_DEBUG_DATA( \ + ipa_reg_save.ipa.testbus->ep_rsrc[rsrc_type].entry_ep \ + [rsrc_grp].testbus_data.value) + +/* + * Macro to pluck the gsi version from ram. + */ +#define IPA_REG_SAVE_GSI_VER(reg_name, var_name) \ + { GEN_1xVECTOR_REG_OFST(reg_name, 0), \ + (u32 *)&ipa_reg_save.gsi.gen.var_name,\ + GEN_REG_ATTR(reg_name) } +/* + * Macro to define a particular register cfg entry for all 3 EE + * indexed register + */ +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 +#define IPA_REG_SAVE_CFG_ENTRY_GEN_EE(reg_name, var_name) \ + { GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE), \ + (u32 *)&ipa_reg_save.ipa.gen_ee[IPA_HW_Q6_EE].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE), \ + (u32 *)&ipa_reg_save.ipa.gen_ee[IPA_HW_A7_EE].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_UC_EE), \ + (u32 *)&ipa_reg_save.ipa.gen_ee[IPA_HW_UC_EE].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_HWP_EE), \ + (u32 *)&ipa_reg_save.ipa.gen_ee[IPA_HW_HWP_EE].var_name, \ + GEN_REG_ATTR(reg_name) } +#else +#define IPA_REG_SAVE_CFG_ENTRY_GEN_EE(reg_name, var_name) \ + { GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE), \ + (u32 *)&ipa_reg_save.ipa.gen_ee[IPA_HW_Q6_EE].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE), \ + (u32 *)&ipa_reg_save.ipa.gen_ee[IPA_HW_A7_EE].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_HWP_EE), \ + (u32 *)&ipa_reg_save.ipa.gen_ee[IPA_HW_HWP_EE].var_name, \ + GEN_REG_ATTR(reg_name) } +#endif + +#define IPA_REG_SAVE_CFG_ENTRY_GSI_FIFO(reg_name, var_name, index) \ + { GEN_SCALER_REG_OFST(reg_name), \ + (u32 *)&ipa_reg_save.ipa.gsi_fifo_status[index].var_name, \ + GEN_REG_ATTR(reg_name) } + +/* + * Macro to define a particular register cfg entry for all pipe + * indexed register + */ +#define IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(reg_name, var_name) \ + { 0, 0 } + +/* + * Macro to define a particular register cfg entry for all resource + * group register + */ +#define IPA_REG_SAVE_CFG_ENTRY_SRC_RSRC_GRP(reg_name, var_name) \ + { GEN_1xVECTOR_REG_OFST(reg_name, 0), \ + (u32 *)&ipa_reg_save.ipa.src_rsrc_grp[0].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 1), \ + (u32 *)&ipa_reg_save.ipa.src_rsrc_grp[1].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 2), \ + (u32 *)&ipa_reg_save.ipa.src_rsrc_grp[2].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 3), \ + (u32 *)&ipa_reg_save.ipa.src_rsrc_grp[3].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 4), \ + (u32 *)&ipa_reg_save.ipa.src_rsrc_grp[4].var_name, \ + GEN_REG_ATTR(reg_name) } + +/* + * Macro to define a particular register cfg entry for all resource + * group register + */ +#define IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_GRP(reg_name, var_name) \ + { GEN_1xVECTOR_REG_OFST(reg_name, 0), \ + (u32 *)&ipa_reg_save.ipa.dst_rsrc_grp[0].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 1), \ + (u32 *)&ipa_reg_save.ipa.dst_rsrc_grp[1].var_name, \ + GEN_REG_ATTR(reg_name) } + +/* + * Macro to define a particular register cfg entry for all source + * resource group count register + */ +#define IPA_REG_SAVE_CFG_ENTRY_SRC_RSRC_CNT_GRP(reg_name, var_name) \ + { GEN_1xVECTOR_REG_OFST(reg_name, 0), \ + (u32 *)&ipa_reg_save.ipa.src_rsrc_cnt[0].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 1), \ + (u32 *)&ipa_reg_save.ipa.src_rsrc_cnt[1].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 2), \ + (u32 *)&ipa_reg_save.ipa.src_rsrc_cnt[2].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 3), \ + (u32 *)&ipa_reg_save.ipa.src_rsrc_cnt[3].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 4), \ + (u32 *)&ipa_reg_save.ipa.src_rsrc_cnt[4].var_name, \ + GEN_REG_ATTR(reg_name) } + +/* + * Macro to define a particular register cfg entry for all dest + * resource group count register + */ +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 +#define IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_CNT_GRP(reg_name, var_name) \ + { GEN_1xVECTOR_REG_OFST(reg_name, 0), \ + (u32 *)&ipa_reg_save.ipa.dst_rsrc_cnt[0].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 1), \ + (u32 *)&ipa_reg_save.ipa.dst_rsrc_cnt[1].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 2), \ + (u32 *)&ipa_reg_save.ipa.dst_rsrc_cnt[2].var_name, \ + GEN_REG_ATTR(reg_name) } +#else +#define IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_CNT_GRP(reg_name, var_name) \ + { GEN_1xVECTOR_REG_OFST(reg_name, 0), \ + (u32 *)&ipa_reg_save.ipa.dst_rsrc_cnt[0].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 1), \ + (u32 *)&ipa_reg_save.ipa.dst_rsrc_cnt[1].var_name, \ + GEN_REG_ATTR(reg_name) } +#endif + +#define IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(reg_name, var_name) \ + { GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE), \ + (u32 *)&ipa_reg_save.gsi.gen_ee[IPA_HW_A7_EE].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE), \ + (u32 *)&ipa_reg_save.gsi.gen_ee[IPA_HW_Q6_EE].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE), \ + (u32 *)&ipa_reg_save.gsi.gen_ee[IPA_REG_SAVE_HWP_GSI_EE].\ + var_name, \ + GEN_REG_ATTR(reg_name) } + +/* + * Macro to define a particular register cfg entry for all GSI EE + * register + */ +#define IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(reg_name, var_name) \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 0), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[0].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 1), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[1].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 2), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[2].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 3), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[3].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 4), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[4].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 5), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[5].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 6), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[6].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 7), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[7].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 8), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[8].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 9), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[9].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 10), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[10].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 11), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[11].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 12), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[12].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 13), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[13].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 14), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[14].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 15), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[15].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 16), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[16].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 17), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[17].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 18), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[18].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 19), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[19].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 20), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[20].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 21), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[21].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 22), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[22].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 23), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[23].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 24), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[24].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 25), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[25].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 26), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[26].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_UC_EE, 1), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[0].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_UC_EE, 3), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[1].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 0), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[0].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 1), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[1].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 2), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[2].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 3), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[3].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 4), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[4].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 5), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[5].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 6), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[6].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 7), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[7].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 8), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[8].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 9), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[9].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 10), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[10].var_name, \ + GEN_REG_ATTR(reg_name) } + +/* + * Macro to define a debug SW MSK register entry for all (n, k) + * k bound by GSI_HW_DEBUG_SW_MSK_REG_MAXk + */ +#define IPA_REG_SAVE_GSI_DEBUG_MSK_REG_ENTRY(reg_name, var_name) \ + { GEN_2xVECTOR_REG_OFST(reg_name, 0, 0), \ + (u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[0].var_name[0], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, 0, 1), \ + (u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[0].var_name[1], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, 1, 0), \ + (u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[1].var_name[0], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, 1, 1), \ + (u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[1].var_name[1], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, 2, 0), \ + (u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[2].var_name[0], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, 2, 1), \ + (u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[2].var_name[1], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, 3, 0), \ + (u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[3].var_name[0], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, 3, 1), \ + (u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[3].var_name[1], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, 4, 0), \ + (u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[4].var_name[0], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, 4, 1), \ + (u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[4].var_name[1], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, 5, 0), \ + (u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[5].var_name[0], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, 5, 1), \ + (u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[5].var_name[1], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, 6, 0), \ + (u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[6].var_name[0], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, 6, 1), \ + (u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[6].var_name[1], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, 7, 0), \ + (u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[7].var_name[0], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, 7, 1), \ + (u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[7].var_name[1], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, 8, 0), \ + (u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[8].var_name[0], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, 8, 1), \ + (u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[8].var_name[1], \ + GEN_REG_ATTR(reg_name) } + +#define IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(reg_name, var_name) \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 0), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[0].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 1), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[1].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 2), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[2].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 3), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[3].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 4), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[4].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 5), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[5].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 6), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[6].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 7), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[7].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 8), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[8].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 9), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[9].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 10), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[10].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 11), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[11].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 12), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[12].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 13), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[13].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 14), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[14].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 15), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[15].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 16), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[16].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 17), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[17].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 18), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[18].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 19), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[19].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 20), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[20].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 21), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[21].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 22), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[22].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 23), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[23].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 24), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[24].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 25), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[25].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 26), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[26].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 1), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.uc[0].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 0), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[0].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 1), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[1].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 2), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[2].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 3), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[3].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 4), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[4].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 5), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[5].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 6), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[6].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 7), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[7].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 8), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[8].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 9), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[9].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 10), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[10].var_name, \ + GEN_REG_ATTR(reg_name) } + +/* + * Macro to define a particular register cfg entry for GSI QSB debug + * registers + */ +#define IPA_REG_SAVE_CFG_ENTRY_GSI_QSB_DEBUG(reg_name, var_name) \ + { GEN_1xVECTOR_REG_OFST(reg_name, 0), \ + (u32 *)&ipa_reg_save.gsi.debug.gsi_qsb_debug.var_name[0], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 1), \ + (u32 *)&ipa_reg_save.gsi.debug.gsi_qsb_debug.var_name[1], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 2), \ + (u32 *)&ipa_reg_save.gsi.debug.gsi_qsb_debug.var_name[2], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 3), \ + (u32 *)&ipa_reg_save.gsi.debug.gsi_qsb_debug.var_name[3], \ + GEN_REG_ATTR(reg_name) } + +#define IPA_REG_SAVE_RX_SPLT_CMDQ(reg_name, var_name) \ + { GEN_1xVECTOR_REG_OFST(reg_name, 0), \ + (u32 *)&ipa_reg_save.ipa.dbg.var_name[0], \ + GEN_REG_ATTR(reg_name)}, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 1), \ + (u32 *)&ipa_reg_save.ipa.dbg.var_name[1], \ + GEN_REG_ATTR(reg_name)}, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 2), \ + (u32 *)&ipa_reg_save.ipa.dbg.var_name[2], \ + GEN_REG_ATTR(reg_name)}, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 3), \ + (u32 *)&ipa_reg_save.ipa.dbg.var_name[3], \ + GEN_REG_ATTR(reg_name) } + +/* + * Macros to save array registers + */ + +/* + * helper macro to save array register of MAXn = 0 + */ +#define GEN_SRC_DST_ADDR_MAP_ARR_0(reg_name, sub_struct, var_name) \ + { GEN_1xVECTOR_REG_OFST(reg_name, 0), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[0], \ + GEN_REG_ATTR(reg_name) } + +/* + * helper macro to save array register of MAXn = 1 + */ +#define GEN_SRC_DST_ADDR_MAP_ARR_1(reg_name, sub_struct, var_name) \ + { GEN_1xVECTOR_REG_OFST(reg_name, 0), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[0], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 1), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[1], \ + GEN_REG_ATTR(reg_name) } + /* + * helper macro to save array register of MAXn = 31 + */ +#define GEN_SRC_DST_ADDR_MAP_ARR_31(reg_name, sub_struct, var_name) \ + { GEN_1xVECTOR_REG_OFST(reg_name, 0), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[0], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 1), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[1], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 2), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[2], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 3), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[3], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 4), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[4], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 5), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[5], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 6), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[6], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 7), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[7], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 8), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[8], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 9), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[9], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 10), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[10], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 11), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[11], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 12), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[12], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 13), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[13], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 14), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[14], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 15), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[15], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 16), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[16], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 17), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[17], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 18), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[18], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 19), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[19], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 20), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[20], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 21), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[21], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 22), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[22], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 23), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[23], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 24), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[24], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 25), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[25], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 26), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[26], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 27), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[27], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 28), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[28], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 29), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[29], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 30), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[30], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 31), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[31], \ + GEN_REG_ATTR(reg_name) } + + +#define __IPA_CONCATENATE(A, B) A ## B +#define IPA_CONCATENATE(A, B) __IPA_CONCATENATE(A, B) + +/* + * helper macro to save array register + */ +#define GEN_SRC_DST_ADDR_MAP_ARR(reg_name, sub_struct, var_name) \ + IPA_CONCATENATE(GEN_SRC_DST_ADDR_MAP_ARR_, \ + GEN_MAX_n(reg_name))(reg_name, sub_struct, var_name) + + +/* + * Macros to save multi EE array registers + */ + +/* + * helper macro to save EE array register of MAXk = 0 + */ +#define GEN_SRC_DST_ADDR_MAP_EE_n_REG_k_ARR_0(reg_name, sub_struct, var_name) \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 0), \ + (u32 *)&ipa_reg_save.sub_struct[IPA_HW_A7_EE].var_name.arr[0].value, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 0), \ + (u32 *)&ipa_reg_save.sub_struct[IPA_HW_Q6_EE].var_name.arr[0].value, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_UC_EE, 0), \ + (u32 *)&ipa_reg_save.sub_struct[IPA_HW_UC_EE].var_name.arr[0].value, \ + GEN_REG_ATTR(reg_name) } + +/* + * helper macro to save EE array register of MAXk = 1 + */ +#define GEN_SRC_DST_ADDR_MAP_EE_n_REG_k_ARR_1(reg_name, sub_struct, var_name) \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 0), \ + (u32 *)&ipa_reg_save.sub_struct[IPA_HW_A7_EE].var_name.arr[0].value, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 1), \ + (u32 *)&ipa_reg_save.sub_struct[IPA_HW_A7_EE].var_name.arr[1].value, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 0), \ + (u32 *)&ipa_reg_save.sub_struct[IPA_HW_Q6_EE].var_name.arr[0].value, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 1), \ + (u32 *)&ipa_reg_save.sub_struct[IPA_HW_Q6_EE].var_name.arr[1].value, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_UC_EE, 0), \ + (u32 *)&ipa_reg_save.sub_struct[IPA_HW_UC_EE].var_name.arr[0].value, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_UC_EE, 1), \ + (u32 *)&ipa_reg_save.sub_struct[IPA_HW_UC_EE].var_name.arr[1].value, \ + GEN_REG_ATTR(reg_name) } + +/* + * helper macro to save EE n reg k array register + */ +#define GEN_SRC_DST_ADDR_MAP_EE_n_REG_k_ARR(reg_name, sub_struct, var_name) \ + IPA_CONCATENATE(GEN_SRC_DST_ADDR_MAP_EE_n_REG_k_ARR_, \ + GEN_MAX_k(reg_name))(reg_name, sub_struct, var_name) + +/* + * helper macro to save EE n array register + */ +#define GEN_SRC_DST_ADDR_MAP_EE_n_ARR(reg_name, sub_struct, var_name) \ + { GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE), \ + (u32 *)&ipa_reg_save.sub_struct[IPA_HW_Q6_EE].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE), \ + (u32 *)&ipa_reg_save.sub_struct[IPA_HW_A7_EE].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_UC_EE), \ + (u32 *)&ipa_reg_save.sub_struct[IPA_HW_UC_EE].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE), \ + (u32 *)&ipa_reg_save.sub_struct[IPA_REG_SAVE_HWP_GSI_EE].\ + var_name, \ + GEN_REG_ATTR(reg_name) } + +/* + * helper macro to wrap struct intended for array as regs array + * in order to create array with max_k == 1 we need to declare + * it as arr[max_k + 1] -> arr[2] + */ +#define GEN_REGS_ARRAY(struct_name, reg_name) \ + struct IPA_CONCATENATE(struct_name, _arr) { \ + union struct_name arr[GEN_MAX_k(reg_name) + 1]; \ + } + +//#define REGS_ARRAY struct struct_name regs[GEN_MAX_k(reg_name)] + +/* + * IPA HW Platform Type + */ +enum ipa_hw_ee_e { + IPA_HW_A7_EE = 0, /* A7's execution environment */ + IPA_HW_Q6_EE = 1, /* Q6's execution environment */ + IPA_HW_UC_EE = 2, /* uC's execution environment */ + IPA_HW_HWP_EE = 3, /* HWP's execution environment */ + IPA_HW_EE_MAX, /* Max EE to support */ +}; + +#define IPA_MAX_EE_TO_COLLECT IPA_HW_UC_EE + +/* + * General IPA register save data struct (ie. this is where register + * values, once read, get placed... + */ +struct ipa_gen_regs_s { + struct ipa_hwio_def_ipa_state_s + ipa_state; +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_hwio_def_ipa_state_rx_active_n_s + ipa_state_rx_active_n[GEN_MAX_n(IPA_STATE_RX_ACTIVE_n) + 1]; +#else + struct ipa_hwio_def_ipa_state_rx_active_s + ipa_state_rx_active; +#endif + struct ipa_hwio_def_ipa_state_tx_wrapper_s + ipa_state_tx_wrapper; + struct ipa_hwio_def_ipa_state_tx0_s + ipa_state_tx0; +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_hwio_def_ipa_state_tx0_misc_s + ipa_state_tx0_misc; +#endif + struct ipa_hwio_def_ipa_state_tx1_s + ipa_state_tx1; +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_hwio_def_ipa_state_tx1_misc_s + ipa_state_tx1_misc; + struct ipa_hwio_def_ipa_state_aggr_active_n_s + ipa_state_aggr_active_n[GEN_MAX_n(IPA_STATE_AGGR_ACTIVE_n) + 1]; +#else + struct ipa_hwio_def_ipa_state_aggr_active_s + ipa_state_aggr_active; +#endif + struct ipa_hwio_def_ipa_state_dfetcher_s + ipa_state_dfetcher; + struct ipa_hwio_def_ipa_state_fetcher_mask_0_s + ipa_state_fetcher_mask_0; + struct ipa_hwio_def_ipa_state_fetcher_mask_1_s + ipa_state_fetcher_mask_1; +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_hwio_def_ipa_state_fetcher_mask_2_s + ipa_state_fetcher_mask_2; +#endif + struct ipa_hwio_def_ipa_state_gsi_aos_s + ipa_state_gsi_aos; + struct ipa_hwio_def_ipa_state_gsi_if_s + ipa_state_gsi_if; +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_hwio_def_ipa_state_gsi_skip_s + ipa_state_gsi_skip; + struct ipa_hwio_def_ipa_state_gsi_tlv_s + ipa_state_gsi_tlv; +#endif + struct ipa_hwio_def_ipa_dpl_timer_lsb_s + ipa_dpl_timer_lsb; + struct ipa_hwio_def_ipa_dpl_timer_msb_s + ipa_dpl_timer_msb; + struct ipa_hwio_def_ipa_proc_iph_cfg_s + ipa_proc_iph_cfg; + struct ipa_hwio_def_ipa_route_s + ipa_route; + struct ipa_hwio_def_ipa_spare_reg_1_s + ipa_spare_reg_1; +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_hwio_def_ipa_spare_reg_2_s + ipa_spare_reg_2; +#endif + struct ipa_hwio_def_ipa_log_s + ipa_log; +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_hwio_def_ipa_log_buf_status_cfg_s + ipa_log_buf_status_cfg; + struct ipa_hwio_def_ipa_log_buf_status_addr_s + ipa_log_buf_status_addr; + struct ipa_hwio_def_ipa_log_buf_status_write_ptr_s + ipa_log_buf_status_write_ptr; + struct ipa_hwio_def_ipa_log_buf_status_ram_ptr_s + ipa_log_buf_status_ram_ptr; +#endif + struct ipa_hwio_def_ipa_log_buf_hw_cmd_cfg_s + ipa_log_buf_hw_cmd_cfg; + struct ipa_hwio_def_ipa_log_buf_hw_cmd_addr_s + ipa_log_buf_hw_cmd_addr; + struct ipa_hwio_def_ipa_log_buf_hw_cmd_write_ptr_s + ipa_log_buf_hw_cmd_write_ptr; + struct ipa_hwio_def_ipa_log_buf_hw_cmd_ram_ptr_s + ipa_log_buf_hw_cmd_ram_ptr; + struct ipa_hwio_def_ipa_comp_hw_version_s + ipa_comp_hw_version; +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_hwio_def_ipa_filt_rout_hash_en_s + ipa_filt_rout_hash_en; + struct ipa_hwio_def_ipa_filt_rout_hash_flush_s + ipa_filt_rout_hash_flush; +#else + struct ipa_hwio_def_ipa_filt_rout_cache_cfg_s + ipa_filt_rout_cache_cfg; + struct ipa_hwio_def_ipa_filt_rout_cache_flush_s + ipa_filt_rout_cache_flush; +#endif + struct ipa_hwio_def_ipa_state_fetcher_s + ipa_state_fetcher; + struct ipa_hwio_def_ipa_ipv4_filter_init_values_s + ipa_ipv4_filter_init_values; + struct ipa_hwio_def_ipa_ipv6_filter_init_values_s + ipa_ipv6_filter_init_values; + struct ipa_hwio_def_ipa_ipv4_route_init_values_s + ipa_ipv4_route_init_values; + struct ipa_hwio_def_ipa_ipv6_route_init_values_s + ipa_ipv6_route_init_values; +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_hwio_def_ipa_bam_activated_ports_s + ipa_bam_activated_ports; +#else + struct ipa_hwio_def_ipa_bam_activated_ports_n_s + ipa_bam_activated_ports_n[GEN_MAX_n(IPA_BAM_ACTIVATED_PORTS_n) + + 1]; +#endif + struct ipa_hwio_def_ipa_tx_commander_cmdq_status_s + ipa_tx_commander_cmdq_status; + struct ipa_hwio_def_ipa_log_buf_hw_snif_el_en_s + ipa_log_buf_hw_snif_el_en; + struct ipa_hwio_def_ipa_log_buf_hw_snif_el_wr_n_rd_sel_s + ipa_log_buf_hw_snif_el_wr_n_rd_sel; + struct ipa_hwio_def_ipa_log_buf_hw_snif_el_cli_mux_s + ipa_log_buf_hw_snif_el_cli_mux; +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_hwio_def_ipa_log_buf_hw_cmd_noc_master_sel_s + ipa_log_buf_hw_cmd_noc_master_sel; +#endif + struct ipa_hwio_def_ipa_state_acl_s + ipa_state_acl; + struct ipa_hwio_def_ipa_sys_pkt_proc_cntxt_base_s + ipa_sys_pkt_proc_cntxt_base; + struct ipa_hwio_def_ipa_sys_pkt_proc_cntxt_base_msb_s + ipa_sys_pkt_proc_cntxt_base_msb; + struct ipa_hwio_def_ipa_local_pkt_proc_cntxt_base_s + ipa_local_pkt_proc_cntxt_base; + struct ipa_hwio_def_ipa_rsrc_grp_cfg_s + ipa_rsrc_grp_cfg; +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_hwio_def_ipa_0_ipa_rsrc_grp_cfg_ext_s + ipa_rsrc_grp_cfg_ext; +#endif + struct ipa_hwio_def_ipa_comp_cfg_s + ipa_comp_cfg; + struct ipa_hwio_def_ipa_state_dpl_fifo_s + ipa_state_dpl_fifo; +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_hwio_def_ipa_pipeline_disable_s + ipa_pipeline_disable; +#endif + struct ipa_hwio_def_ipa_state_nlo_aggr_s + ipa_state_nlo_aggr; +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_hwio_def_ipa_state_coal_master_s + ipa_state_coal_master; + struct ipa_hwio_def_ipa_state_coal_master_1_s + ipa_state_coal_master_1; + struct ipa_hwio_def_ipa_coal_evict_lru_s + ipa_coal_evict_lru; + struct ipa_hwio_def_ipa_coal_qmap_cfg_s + ipa_coal_qmap_cfg; + struct ipa_hwio_def_ipa_tag_timer_s + ipa_tag_timer; +#endif + struct ipa_hwio_def_ipa_nlo_pp_cfg1_s + ipa_nlo_pp_cfg1; + struct ipa_hwio_def_ipa_nlo_pp_cfg2_s + ipa_nlo_pp_cfg2; +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_hwio_def_ipa_nlo_pp_ack_limit_cfg_s + ipa_nlo_pp_ack_limit_cfg; + struct ipa_hwio_def_ipa_nlo_pp_data_limit_cfg_s + ipa_nlo_pp_data_limit_cfg; +#endif + struct ipa_hwio_def_ipa_nlo_min_dsm_cfg_s + ipa_nlo_min_dsm_cfg; +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_hwio_def_ipa_nlo_vp_aggr_cfg_lsb_n_s + ipa_nlo_vp_aggr_cfg_lsb_n[GEN_MAX_n(IPA_NLO_VP_AGGR_CFG_LSB_n) + 1]; + struct ipa_hwio_def_ipa_nlo_vp_limit_cfg_n_s + ipa_nlo_vp_limit_cfg_n[GEN_MAX_n(IPA_NLO_VP_LIMIT_CFG_n) + 1]; +#endif + struct ipa_hwio_def_ipa_nlo_vp_flush_req_s + ipa_nlo_vp_flush_req; + struct ipa_hwio_def_ipa_nlo_vp_flush_cookie_s + ipa_nlo_vp_flush_cookie; + struct ipa_hwio_def_ipa_nlo_vp_flush_ack_s + ipa_nlo_vp_flush_ack; + struct ipa_hwio_def_ipa_nlo_vp_dsm_open_s + ipa_nlo_vp_dsm_open; + struct ipa_hwio_def_ipa_nlo_vp_qbap_open_s + ipa_nlo_vp_qbap_open; +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_hwio_def_ipa_qsb_max_reads_s + ipa_qsb_max_reads; + struct ipa_hwio_def_ipa_qsb_max_writes_s + ipa_qsb_max_writes; + struct ipa_hwio_def_ipa_idle_indication_cfg_s + ipa_idle_indication_cfg; + struct ipa_hwio_def_ipa_clkon_cfg_s + ipa_clkon_cfg; + struct ipa_hwio_def_ipa_timers_xo_clk_div_cfg_s + ipa_timers_xo_clk_div_cfg; + struct ipa_hwio_def_ipa_timers_pulse_gran_cfg_s + ipa_timers_pulse_gran_cfg; + struct ipa_hwio_def_ipa_qtime_timestamp_cfg_s + ipa_qtime_timestamp_cfg; + struct ipa_hwio_def_ipa_flavor_0_s + ipa_flavor_0; + struct ipa_hwio_def_ipa_flavor_1_s + ipa_flavor_1; + struct ipa_hwio_def_ipa_filt_rout_cfg_s + ipa_filt_rout_cfg; +#endif +}; + +/* + * General IPA register save data struct + */ +struct ipa_reg_save_gen_ee_s { + struct ipa_hwio_def_ipa_irq_stts_ee_n_s + ipa_irq_stts_ee_n; + struct ipa_hwio_def_ipa_irq_en_ee_n_s + ipa_irq_en_ee_n; + struct ipa_hwio_def_ipa_fec_addr_ee_n_s + ipa_fec_addr_ee_n; + struct ipa_hwio_def_ipa_fec_attr_ee_n_s + ipa_fec_attr_ee_n; + struct ipa_hwio_def_ipa_snoc_fec_ee_n_s + ipa_snoc_fec_ee_n; +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_hwio_def_ipa_holb_drop_irq_info_ee_n_s + ipa_holb_drop_irq_info_ee_n; + struct ipa_hwio_def_ipa_suspend_irq_info_ee_n_s + ipa_suspend_irq_info_ee_n; + struct ipa_hwio_def_ipa_suspend_irq_en_ee_n_s + ipa_suspend_irq_en_ee_n; +#else + GEN_REGS_ARRAY(ipa_hwio_def_ipa_holb_drop_irq_info_ee_n_reg_k_u, + IPA_HOLB_DROP_IRQ_INFO_EE_n_REG_k) + ipa_holb_drop_irq_info_ee_n_reg_k; + GEN_REGS_ARRAY(ipa_hwio_def_ipa_suspend_irq_info_ee_n_reg_k_u, + IPA_SUSPEND_IRQ_INFO_EE_n_REG_k) + ipa_suspend_irq_info_ee_n_reg_k; + GEN_REGS_ARRAY(ipa_hwio_def_ipa_suspend_irq_en_ee_n_reg_k_u, + IPA_SUSPEND_IRQ_EN_EE_n_REG_k) + ipa_suspend_irq_en_ee_n_reg_k; +#endif +}; + +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 +/* + * statistics IPA register save data struct + */ + +struct ipa_reg_save_stat_ee_s { + struct ipa_hwio_def_ipa_stat_quota_base_n_s + ipa_stat_quota_base_n; + struct ipa_hwio_def_ipa_stat_tethering_base_n_s + ipa_stat_tethering_base_n; + struct ipa_hwio_def_ipa_stat_drop_cnt_base_n_s + ipa_stat_drop_cnt_base_n; + GEN_REGS_ARRAY(ipa_hwio_def_ipa_stat_quota_mask_ee_n_reg_k_u, + IPA_STAT_QUOTA_MASK_EE_n_REG_k) + ipa_stat_quota_mask_ee_n_reg_k; + GEN_REGS_ARRAY(ipa_hwio_def_ipa_stat_tethering_mask_ee_n_reg_k_u, + IPA_STAT_TETHERING_MASK_EE_n_REG_k) + ipa_stat_tethering_mask_ee_n_reg_k; + GEN_REGS_ARRAY(ipa_hwio_def_ipa_stat_drop_cnt_mask_ee_n_reg_k_u, + IPA_STAT_DROP_CNT_MASK_EE_n_REG_k) + ipa_stat_drop_cnt_mask_ee_n_reg_k; +}; +#endif + +/* + * Pipe Endp IPA register save data struct + */ +struct ipa_reg_save_pipe_endp_s { + struct ipa_hwio_def_ipa_endp_init_ctrl_n_s + ipa_endp_init_ctrl_n; + struct ipa_hwio_def_ipa_endp_init_ctrl_scnd_n_s + ipa_endp_init_ctrl_scnd_n; + struct ipa_hwio_def_ipa_endp_init_cfg_n_s + ipa_endp_init_cfg_n; + struct ipa_hwio_def_ipa_endp_init_nat_n_s + ipa_endp_init_nat_n; + struct ipa_hwio_def_ipa_endp_init_hdr_n_s + ipa_endp_init_hdr_n; + struct ipa_hwio_def_ipa_endp_init_hdr_ext_n_s + ipa_endp_init_hdr_ext_n; + struct ipa_hwio_def_ipa_endp_init_hdr_metadata_mask_n_s + ipa_endp_init_hdr_metadata_mask_n; + struct ipa_hwio_def_ipa_endp_init_hdr_metadata_n_s + ipa_endp_init_hdr_metadata_n; + struct ipa_hwio_def_ipa_endp_init_mode_n_s + ipa_endp_init_mode_n; + struct ipa_hwio_def_ipa_endp_init_aggr_n_s + ipa_endp_init_aggr_n; + struct ipa_hwio_def_ipa_endp_init_hol_block_en_n_s + ipa_endp_init_hol_block_en_n; + struct ipa_hwio_def_ipa_endp_init_hol_block_timer_n_s + ipa_endp_init_hol_block_timer_n; + struct ipa_hwio_def_ipa_endp_init_deaggr_n_s + ipa_endp_init_deaggr_n; + struct ipa_hwio_def_ipa_endp_status_n_s + ipa_endp_status_n; + struct ipa_hwio_def_ipa_endp_init_rsrc_grp_n_s + ipa_endp_init_rsrc_grp_n; + struct ipa_hwio_def_ipa_endp_init_seq_n_s + ipa_endp_init_seq_n; + struct ipa_hwio_def_ipa_endp_gsi_cfg_tlv_n_s + ipa_endp_gsi_cfg_tlv_n; + struct ipa_hwio_def_ipa_endp_gsi_cfg_aos_n_s + ipa_endp_gsi_cfg_aos_n; + struct ipa_hwio_def_ipa_endp_gsi_cfg1_n_s + ipa_endp_gsi_cfg1_n; +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_hwio_def_ipa_endp_filter_router_hsh_cfg_n_s + ipa_endp_filter_router_hsh_cfg_n; +#else + struct ipa_hwio_def_ipa_filter_cache_cfg_n_s + ipa_filter_cache_cfg_n; + struct ipa_hwio_def_ipa_router_cache_cfg_n_s + ipa_router_cache_cfg_n; +#endif +}; + +/* + * Pipe IPA register save data struct + */ +struct ipa_reg_save_pipe_s { + u8 active; + struct ipa_reg_save_pipe_endp_s endp; +}; + +/* + * HWP IPA register save data struct + */ +struct ipa_reg_save_hwp_s { + struct ipa_hwio_def_ipa_uc_qmb_sys_addr_s + ipa_uc_qmb_sys_addr; + struct ipa_hwio_def_ipa_uc_qmb_local_addr_s + ipa_uc_qmb_local_addr; + struct ipa_hwio_def_ipa_uc_qmb_length_s + ipa_uc_qmb_length; + struct ipa_hwio_def_ipa_uc_qmb_trigger_s + ipa_uc_qmb_trigger; +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_hwio_def_ipa_uc_qmb_pending_tid_s + ipa_uc_qmb_pending_tid; + struct ipa_hwio_def_ipa_uc_qmb_completed_rd_fifo_peek_s + ipa_uc_qmb_completed_rd_fifo_peek; + struct ipa_hwio_def_ipa_uc_qmb_completed_wr_fifo_peek_s + ipa_uc_qmb_completed_wr_fifo_peek; + struct ipa_hwio_def_ipa_uc_qmb_misc_s + ipa_uc_qmb_misc; + struct ipa_hwio_def_ipa_uc_qmb_status_s + ipa_uc_qmb_status; +#endif + struct ipa_hwio_def_ipa_uc_qmb_bus_attrib_s + ipa_uc_qmb_bus_attrib; +}; + +/* + * IPA TESTBUS entry struct + */ +struct ipa_reg_save_ipa_testbus_entry_s { + union ipa_hwio_def_ipa_testbus_sel_u testbus_sel; + union ipa_hwio_def_ipa_debug_data_u testbus_data; +}; + +/* IPA TESTBUS global struct */ +struct ipa_reg_save_ipa_testbus_global_s { + struct ipa_reg_save_ipa_testbus_entry_s + global[IPA_TESTBUS_SEL_INTERNAL_MAX + 1] + [IPA_TESTBUS_SEL_EXTERNAL_MAX + 1]; +}; + +/* IPA TESTBUS per EP struct */ +struct ipa_reg_save_ipa_testbus_ep_s { + struct ipa_reg_save_ipa_testbus_entry_s + entry_ep[IPA_TESTBUS_SEL_INTERNAL_PIPE_MAX + 1] + [IPA_TESTBUS_SEL_EXTERNAL_MAX + 1]; +}; + +/* IPA TESTBUS per EP struct */ +struct ipa_reg_save_ipa_testbus_ep_rsrc_s { + struct ipa_reg_save_ipa_testbus_entry_s + entry_ep[IPA_DEBUG_TESTBUS_RSRC_NUM_GRP]; +}; + +/* IPA TESTBUS save data struct */ +struct ipa_reg_save_ipa_testbus_s { + struct ipa_reg_save_ipa_testbus_global_s global; + struct ipa_reg_save_ipa_testbus_ep_s + ep[IPA_TESTBUS_SEL_EP_MAX + 1]; + struct ipa_reg_save_ipa_testbus_ep_rsrc_s + ep_rsrc[IPA_DEBUG_TESTBUS_RSRC_NUM_EP]; +}; + +/* + * Debug IPA register save data struct + */ +struct ipa_reg_save_dbg_s { + struct ipa_hwio_def_ipa_debug_data_s + ipa_debug_data; + struct ipa_hwio_def_ipa_step_mode_status_s + ipa_step_mode_status; + struct ipa_hwio_def_ipa_step_mode_breakpoints_s + ipa_step_mode_breakpoints; + struct ipa_hwio_def_ipa_rx_splt_cmdq_cmd_n_s + ipa_rx_splt_cmdq_cmd_n[IPA_RX_SPLT_CMDQ_MAX]; + struct ipa_hwio_def_ipa_rx_splt_cmdq_cfg_n_s + ipa_rx_splt_cmdq_cfg_n[IPA_RX_SPLT_CMDQ_MAX]; + struct ipa_hwio_def_ipa_rx_splt_cmdq_data_wr_0_n_s + ipa_rx_splt_cmdq_data_wr_0_n[IPA_RX_SPLT_CMDQ_MAX]; + struct ipa_hwio_def_ipa_rx_splt_cmdq_data_wr_1_n_s + ipa_rx_splt_cmdq_data_wr_1_n[IPA_RX_SPLT_CMDQ_MAX]; + struct ipa_hwio_def_ipa_rx_splt_cmdq_data_wr_2_n_s + ipa_rx_splt_cmdq_data_wr_2_n[IPA_RX_SPLT_CMDQ_MAX]; + struct ipa_hwio_def_ipa_rx_splt_cmdq_data_wr_3_n_s + ipa_rx_splt_cmdq_data_wr_3_n[IPA_RX_SPLT_CMDQ_MAX]; + struct ipa_hwio_def_ipa_rx_splt_cmdq_data_rd_0_n_s + ipa_rx_splt_cmdq_data_rd_0_n[IPA_RX_SPLT_CMDQ_MAX]; + struct ipa_hwio_def_ipa_rx_splt_cmdq_data_rd_1_n_s + ipa_rx_splt_cmdq_data_rd_1_n[IPA_RX_SPLT_CMDQ_MAX]; + struct ipa_hwio_def_ipa_rx_splt_cmdq_data_rd_2_n_s + ipa_rx_splt_cmdq_data_rd_2_n[IPA_RX_SPLT_CMDQ_MAX]; + struct ipa_hwio_def_ipa_rx_splt_cmdq_data_rd_3_n_s + ipa_rx_splt_cmdq_data_rd_3_n[IPA_RX_SPLT_CMDQ_MAX]; + struct ipa_hwio_def_ipa_rx_splt_cmdq_status_n_s + ipa_rx_splt_cmdq_status_n[IPA_RX_SPLT_CMDQ_MAX]; + + union ipa_hwio_def_ipa_rx_hps_cmdq_cfg_wr_u + ipa_rx_hps_cmdq_cfg_wr; + union ipa_hwio_def_ipa_rx_hps_cmdq_cfg_rd_u + ipa_rx_hps_cmdq_cfg_rd; + + struct ipa_hwio_def_ipa_rx_hps_cmdq_cmd_s + ipa_rx_hps_cmdq_cmd; +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_hwio_def_ipa_stat_filter_ipv4_base_s + ipa_stat_filter_ipv4_base; + struct ipa_hwio_def_ipa_stat_filter_ipv6_base_s + ipa_stat_filter_ipv6_base; + struct ipa_hwio_def_ipa_stat_router_ipv4_base_s + ipa_stat_router_ipv4_base; + struct ipa_hwio_def_ipa_stat_router_ipv6_base_s + ipa_stat_router_ipv6_base; +#endif + union ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_0_u + ipa_rx_hps_cmdq_data_rd_0_arr[ + IPA_DEBUG_CMDQ_HPS_SELECT_NUM_GROUPS]; + union ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_1_u + ipa_rx_hps_cmdq_data_rd_1_arr[ + IPA_DEBUG_CMDQ_HPS_SELECT_NUM_GROUPS]; + union ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_2_u + ipa_rx_hps_cmdq_data_rd_2_arr[ + IPA_DEBUG_CMDQ_HPS_SELECT_NUM_GROUPS]; + union ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_3_u + ipa_rx_hps_cmdq_data_rd_3_arr[ + IPA_DEBUG_CMDQ_HPS_SELECT_NUM_GROUPS]; + union ipa_hwio_def_ipa_rx_hps_cmdq_count_u + ipa_rx_hps_cmdq_count_arr[IPA_DEBUG_CMDQ_HPS_SELECT_NUM_GROUPS]; + union ipa_hwio_def_ipa_rx_hps_cmdq_status_u + ipa_rx_hps_cmdq_status_arr[IPA_DEBUG_CMDQ_HPS_SELECT_NUM_GROUPS]; + struct ipa_hwio_def_ipa_rx_hps_cmdq_status_empty_s + ipa_rx_hps_cmdq_status_empty; +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_hwio_def_ipa_rsrc_mngr_contexts_s + ipa_rsrc_mngr_contexts; + struct ipa_hwio_def_ipa_snoc_monitoring_cfg_s + ipa_snoc_monitoring_cfg; + struct ipa_hwio_def_ipa_pcie_snoc_monitor_cnt_s + ipa_pcie_snoc_monitor_cnt; + struct ipa_hwio_def_ipa_ddr_snoc_monitor_cnt_s + ipa_ddr_snoc_monitor_cnt; + struct ipa_hwio_def_ipa_gsi_snoc_monitor_cnt_s + ipa_gsi_snoc_monitor_cnt; + struct ipa_hwio_def_ipa_ram_sniffer_hw_base_addr_s + ipa_ram_sniffer_hw_base_addr; + struct ipa_hwio_def_ipa_bresp_db_cfg_s + ipa_bresp_db_cfg; + struct ipa_hwio_def_ipa_bresp_db_data_s + ipa_bresp_db_data; + struct ipa_hwio_def_ipa_endp_gsi_cons_bytes_tlv_s + ipa_endp_gsi_cons_bytes_tlv; + struct ipa_hwio_def_ipa_ram_gsi_tlv_base_addr_s + ipa_ram_gsi_tlv_base_addr; +#endif + struct ipa_hwio_def_ipa_rx_hps_clients_min_depth_0_s + ipa_rx_hps_clients_min_depth_0; + struct ipa_hwio_def_ipa_rx_hps_clients_max_depth_0_s + ipa_rx_hps_clients_max_depth_0; + struct ipa_hwio_def_ipa_hps_dps_cmdq_cmd_s + ipa_hps_dps_cmdq_cmd; + union ipa_hwio_def_ipa_hps_dps_cmdq_data_rd_0_u + ipa_hps_dps_cmdq_data_rd_0_arr[IPA_TESTBUS_SEL_EP_MAX + 1]; + union ipa_hwio_def_ipa_hps_dps_cmdq_count_u + ipa_hps_dps_cmdq_count_arr[IPA_TESTBUS_SEL_EP_MAX + 1]; + union ipa_hwio_def_ipa_hps_dps_cmdq_status_u + ipa_hps_dps_cmdq_status_arr[IPA_TESTBUS_SEL_EP_MAX + 1]; +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_hwio_def_ipa_hps_dps_cmdq_status_empty_s + ipa_hps_dps_cmdq_status_empty; +#else + struct ipa_hwio_def_ipa_hps_dps_cmdq_status_empty_n_s + ipa_hps_dps_cmdq_status_empty_n[ + GEN_MAX_n(IPA_HPS_DPS_CMDQ_STATUS_EMPTY_n) + 1]; +#endif + struct ipa_hwio_def_ipa_dps_tx_cmdq_cmd_s + ipa_dps_tx_cmdq_cmd; + union ipa_hwio_def_ipa_dps_tx_cmdq_data_rd_0_u + ipa_dps_tx_cmdq_data_rd_0_arr[ + IPA_DEBUG_CMDQ_DPS_SELECT_NUM_GROUPS]; + union ipa_hwio_def_ipa_dps_tx_cmdq_count_u + ipa_dps_tx_cmdq_count_arr[IPA_DEBUG_CMDQ_DPS_SELECT_NUM_GROUPS]; + union ipa_hwio_def_ipa_dps_tx_cmdq_status_u + ipa_dps_tx_cmdq_status_arr[IPA_DEBUG_CMDQ_DPS_SELECT_NUM_GROUPS]; + struct ipa_hwio_def_ipa_dps_tx_cmdq_status_empty_s + ipa_dps_tx_cmdq_status_empty; + + struct ipa_hwio_def_ipa_ackmngr_cmdq_cmd_s + ipa_ackmngr_cmdq_cmd; + union ipa_hwio_def_ipa_ackmngr_cmdq_data_rd_u + ipa_ackmngr_cmdq_data_rd_arr[ + IPA_DEBUG_CMDQ_ACK_SELECT_NUM_GROUPS]; + union ipa_hwio_def_ipa_ackmngr_cmdq_count_u + ipa_ackmngr_cmdq_count_arr[IPA_DEBUG_CMDQ_ACK_SELECT_NUM_GROUPS]; + union ipa_hwio_def_ipa_ackmngr_cmdq_status_u + ipa_ackmngr_cmdq_status_arr[ + IPA_DEBUG_CMDQ_ACK_SELECT_NUM_GROUPS]; +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_hwio_def_ipa_ackmngr_cmdq_status_empty_s + ipa_ackmngr_cmdq_status_empty; +#else + struct ipa_hwio_def_ipa_ackmngr_cmdq_status_empty_n_s + ipa_ackmngr_cmdq_status_empty_n[ + GEN_MAX_n(IPA_ACKMNGR_CMDQ_STATUS_EMPTY_n) + 1]; +#endif + struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_cmd_s + ipa_prod_ackmngr_cmdq_cmd; + union ipa_hwio_def_ipa_prod_ackmngr_cmdq_data_rd_u + ipa_prod_ackmngr_cmdq_data_rd_arr[IPA_TESTBUS_SEL_EP_MAX + 1]; + union ipa_hwio_def_ipa_prod_ackmngr_cmdq_count_u + ipa_prod_ackmngr_cmdq_count_arr[IPA_TESTBUS_SEL_EP_MAX + 1]; + union ipa_hwio_def_ipa_prod_ackmngr_cmdq_status_u + ipa_prod_ackmngr_cmdq_status_arr[IPA_TESTBUS_SEL_EP_MAX + 1]; +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_status_empty_s + ipa_prod_ackmngr_cmdq_status_empty; +#else + struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_status_empty_n_s + ipa_prod_ackmngr_cmdq_status_empty_n[GEN_MAX_n( + IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_n) + 1]; +#endif + struct ipa_hwio_def_ipa_ntf_tx_cmdq_cmd_s + ipa_ntf_tx_cmdq_cmd; + union ipa_hwio_def_ipa_ntf_tx_cmdq_data_rd_0_u + ipa_ntf_tx_cmdq_data_rd_0_arr[IPA_TESTBUS_SEL_EP_MAX + 1]; + union ipa_hwio_def_ipa_ntf_tx_cmdq_count_u + ipa_ntf_tx_cmdq_count_arr[IPA_TESTBUS_SEL_EP_MAX + 1]; + union ipa_hwio_def_ipa_ntf_tx_cmdq_status_u + ipa_ntf_tx_cmdq_status_arr[IPA_TESTBUS_SEL_EP_MAX + 1]; +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_hwio_def_ipa_ntf_tx_cmdq_status_empty_s + ipa_ntf_tx_cmdq_status_empty; +#else + struct ipa_hwio_def_ipa_ntf_tx_cmdq_status_empty_n_s + ipa_ntf_tx_cmdq_status_empty_n[GEN_MAX_n( + IPA_NTF_TX_CMDQ_STATUS_EMPTY_n) + 1]; +#endif + union ipa_hwio_def_ipa_rsrc_mngr_db_rsrc_read_u + ipa_rsrc_mngr_db_rsrc_read_arr[IPA_RSCR_MNGR_DB_RSRC_TYPE_MAX + + 1][IPA_RSCR_MNGR_DB_RSRC_ID_MAX + + 1]; + union ipa_hwio_def_ipa_rsrc_mngr_db_list_read_u + ipa_rsrc_mngr_db_list_read_arr[IPA_RSCR_MNGR_DB_RSRC_TYPE_MAX + + 1][IPA_RSCR_MNGR_DB_RSRC_ID_MAX + + 1]; +}; + +/* Source Resource Group IPA register save data struct */ +struct ipa_reg_save_src_rsrc_grp_s { + struct ipa_hwio_def_ipa_src_rsrc_grp_01_rsrc_type_n_s + ipa_src_rsrc_grp_01_rsrc_type_n; + struct ipa_hwio_def_ipa_src_rsrc_grp_23_rsrc_type_n_s + ipa_src_rsrc_grp_23_rsrc_type_n; + struct ipa_hwio_def_ipa_src_rsrc_grp_45_rsrc_type_n_s + ipa_src_rsrc_grp_45_rsrc_type_n; +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_hwio_def_ipa_src_rsrc_grp_67_rsrc_type_n_s + ipa_src_rsrc_grp_67_rsrc_type_n; + struct ipa_hwio_def_ipa_src_rsrc_type_amount_n_s + ipa_src_rsrc_type_amount; +#endif +}; + +/* Source Resource Group IPA register save data struct */ +struct ipa_reg_save_dst_rsrc_grp_s { + struct ipa_hwio_def_ipa_dst_rsrc_grp_01_rsrc_type_n_s + ipa_dst_rsrc_grp_01_rsrc_type_n; + struct ipa_hwio_def_ipa_dst_rsrc_grp_23_rsrc_type_n_s + ipa_dst_rsrc_grp_23_rsrc_type_n; + struct ipa_hwio_def_ipa_dst_rsrc_grp_45_rsrc_type_n_s + ipa_dst_rsrc_grp_45_rsrc_type_n; +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_hwio_def_ipa_dst_rsrc_grp_67_rsrc_type_n_s + ipa_dst_rsrc_grp_67_rsrc_type_n; + struct ipa_hwio_def_ipa_dst_rsrc_type_amount_n_s + ipa_dst_rsrc_type_amount; +#endif +}; + +/* Source Resource Group Count IPA register save data struct */ +struct ipa_reg_save_src_rsrc_cnt_s { + struct ipa_hwio_def_ipa_src_rsrc_grp_0123_rsrc_type_cnt_n_s + ipa_src_rsrc_grp_0123_rsrc_type_cnt_n; + struct ipa_hwio_def_ipa_src_rsrc_grp_4567_rsrc_type_cnt_n_s + ipa_src_rsrc_grp_4567_rsrc_type_cnt_n; +}; + +/* Destination Resource Group Count IPA register save data struct */ +struct ipa_reg_save_dst_rsrc_cnt_s { + struct ipa_hwio_def_ipa_dst_rsrc_grp_0123_rsrc_type_cnt_n_s + ipa_dst_rsrc_grp_0123_rsrc_type_cnt_n; + struct ipa_hwio_def_ipa_dst_rsrc_grp_4567_rsrc_type_cnt_n_s + ipa_dst_rsrc_grp_4567_rsrc_type_cnt_n; +}; + +/* GSI General register save data struct */ +struct ipa_reg_save_gsi_gen_s { + struct gsi_hwio_def_gsi_cfg_s + gsi_cfg; + struct gsi_hwio_def_gsi_ree_cfg_s + gsi_ree_cfg; + struct ipa_hwio_def_ipa_gsi_top_gsi_inst_ram_n_s + ipa_gsi_top_gsi_inst_ram_n; +}; + +/* GSI fw version data */ +struct ipa_reg_save_gsi_fw_version_s { + u32 raw_version; + u32 hw_version; + u32 flavor; + u32 fw_version; +}; + +/* GSI General EE register save data struct */ +struct ipa_reg_save_gsi_gen_ee_s { + struct gsi_hwio_def_gsi_manager_ee_qos_n_s + gsi_manager_ee_qos_n; + struct gsi_hwio_def_ee_n_gsi_status_s + ee_n_gsi_status; + struct gsi_hwio_def_ee_n_cntxt_type_irq_s + ee_n_cntxt_type_irq; + struct gsi_hwio_def_ee_n_cntxt_type_irq_msk_s + ee_n_cntxt_type_irq_msk; +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_s + ee_n_cntxt_src_gsi_ch_irq; + struct gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_s + ee_n_cntxt_src_ev_ch_irq; + struct gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_msk_s + ee_n_cntxt_src_gsi_ch_irq_msk; + struct gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_msk_s + ee_n_cntxt_src_ev_ch_irq_msk; + struct gsi_hwio_def_ee_n_cntxt_src_ieob_irq_s + ee_n_cntxt_src_ieob_irq; + struct gsi_hwio_def_ee_n_cntxt_src_ieob_irq_msk_s + ee_n_cntxt_src_ieob_irq_msk; +#else + GEN_REGS_ARRAY(gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_k_u, + EE_n_CNTXT_SRC_GSI_CH_IRQ_k) + ee_n_cntxt_src_gsi_ch_irq_k; + GEN_REGS_ARRAY(gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_k_u, + EE_n_CNTXT_SRC_EV_CH_IRQ_k) + ee_n_cntxt_src_ev_ch_irq_k; + GEN_REGS_ARRAY(gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_msk_k_u, + EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k) + ee_n_cntxt_src_gsi_ch_irq_msk_k; + GEN_REGS_ARRAY(gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_msk_k_u, + EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k) + ee_n_cntxt_src_ev_ch_irq_msk_k; + GEN_REGS_ARRAY(gsi_hwio_def_ee_n_cntxt_src_ieob_irq_k_u, + EE_n_CNTXT_SRC_IEOB_IRQ_k) + ee_n_cntxt_src_ieob_irq_k; + GEN_REGS_ARRAY(gsi_hwio_def_ee_n_cntxt_src_ieob_irq_msk_k_u, + EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k) + ee_n_cntxt_src_ieob_irq_msk_k; +#endif + struct gsi_hwio_def_ee_n_cntxt_gsi_irq_stts_s + ee_n_cntxt_gsi_irq_stts; + struct gsi_hwio_def_ee_n_cntxt_glob_irq_stts_s + ee_n_cntxt_glob_irq_stts; + struct gsi_hwio_def_ee_n_error_log_s + ee_n_error_log; + struct gsi_hwio_def_ee_n_cntxt_scratch_0_s + ee_n_cntxt_scratch_0; + struct gsi_hwio_def_ee_n_cntxt_scratch_1_s + ee_n_cntxt_scratch_1; + struct gsi_hwio_def_ee_n_cntxt_intset_s + ee_n_cntxt_intset; + struct gsi_hwio_def_ee_n_cntxt_msi_base_lsb_s + ee_n_cntxt_msi_base_lsb; + struct gsi_hwio_def_ee_n_cntxt_msi_base_msb_s + ee_n_cntxt_msi_base_msb; +}; + +/* GSI QSB debug register save data struct */ +struct ipa_reg_save_gsi_qsb_debug_s { + struct gsi_hwio_def_gsi_debug_qsb_log_last_misc_idn_s + qsb_log_last_misc[GSI_HW_QSB_LOG_MISC_MAX]; +}; + +static u32 ipa_reg_save_gsi_ch_test_bus_selector_array[] = { + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_ZEROS, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MCS_0, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MCS_1, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MCS_2, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MCS_3, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MCS_4, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_DB_ENG, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_0, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_1, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_2, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_3, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_4, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_5, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_6, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_7, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_EVE_0, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_EVE_1, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_EVE_2, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_EVE_3, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_EVE_4, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_EVE_5, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IE_0, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IE_1, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IC_0, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IC_1, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IC_2, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IC_3, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IC_4, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MOQA_0, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MOQA_1, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MOQA_2, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MOQA_3, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_TMR_0, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_TMR_1, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_TMR_2, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_TMR_3, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_RD_WR_0, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_RD_WR_1, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_RD_WR_2, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_RD_WR_3, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_CSR, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_SDMA_0, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_SDMA_1, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IE_2, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_CSR_1, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_CSR_2, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MCS_5, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IC_5, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_CSR_3, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_TLV_0, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_8, +}; + +/* + * GSI QSB debug bus register save data struct + */ +struct ipa_reg_save_gsi_test_bus_s { + u32 test_bus_selector[ + ARRAY_SIZE(ipa_reg_save_gsi_ch_test_bus_selector_array)]; + struct + gsi_hwio_def_gsi_test_bus_reg_s + test_bus_reg[ARRAY_SIZE(ipa_reg_save_gsi_ch_test_bus_selector_array)]; +}; + +/* GSI debug MCS registers save data struct */ +struct ipa_reg_save_gsi_mcs_regs_s { + struct + gsi_hwio_def_gsi_debug_sw_rf_n_read_s + mcs_reg[HWIO_GSI_DEBUG_SW_RF_n_READ_MAXn + 1]; +}; + +struct ipa_reg_save_gsi_mcs_prof_regs_s { + struct gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_bp_cnt_lsb_s + gsi_top_gsi_mcs_profiling_bp_cnt_lsb; + struct gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_bp_cnt_msb_s + gsi_top_gsi_mcs_profiling_bp_cnt_msb; + struct gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_bp_and_pending_cnt_lsb_s + gsi_top_gsi_mcs_profiling_bp_and_pending_cnt_lsb; + struct gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_bp_and_pending_cnt_msb_s + gsi_top_gsi_mcs_profiling_bp_and_pending_cnt_msb; + struct gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_mcs_busy_cnt_lsb_s + gsi_top_gsi_mcs_profiling_mcs_busy_cnt_lsb; + struct gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_mcs_busy_cnt_msb_s + gsi_top_gsi_mcs_profiling_mcs_busy_cnt_msb; + struct gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_mcs_idle_cnt_lsb_s + gsi_top_gsi_mcs_profiling_mcs_idle_cnt_lsb; + struct gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_mcs_idle_cnt_msb_s + gsi_top_gsi_mcs_profiling_mcs_idle_cnt_msb; +}; + +/* GSI debug counters save data struct */ +struct ipa_reg_save_gsi_debug_cnt_s { + struct + gsi_hwio_def_gsi_debug_countern_s + cnt[HWIO_GSI_DEBUG_COUNTERn_MAXn + 1]; +}; + +/* GSI IRAM pointers (IEP) save data struct */ +struct ipa_reg_save_gsi_iram_ptr_regs_s { + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ch_cmd_s + ipa_gsi_top_gsi_iram_ptr_ch_cmd; + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ee_generic_cmd_s + ipa_gsi_top_gsi_iram_ptr_ee_generic_cmd; + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ch_db_s + ipa_gsi_top_gsi_iram_ptr_ch_db; + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ev_db_s + ipa_gsi_top_gsi_iram_ptr_ev_db; + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_new_re_s + ipa_gsi_top_gsi_iram_ptr_new_re; + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ch_dis_comp_s + ipa_gsi_top_gsi_iram_ptr_ch_dis_comp; + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ch_empty_s + ipa_gsi_top_gsi_iram_ptr_ch_empty; + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_event_gen_comp_s + ipa_gsi_top_gsi_iram_ptr_event_gen_comp; + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_timer_expired_s + ipa_gsi_top_gsi_iram_ptr_timer_expired; + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_write_eng_comp_s + ipa_gsi_top_gsi_iram_ptr_write_eng_comp; + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_read_eng_comp_s + ipa_gsi_top_gsi_iram_ptr_read_eng_comp; + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_uc_gp_int_s + ipa_gsi_top_gsi_iram_ptr_uc_gp_int; +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_int_mod_stopped_s + ipa_gsi_top_gsi_iram_ptr_int_mod_stopped; +#else + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_int_mod_stoped_s + ipa_gsi_top_gsi_iram_ptr_int_mod_stoped; +#endif +}; + +/* GSI Debug SW registers save data struct */ +struct gsi_hwio_gsi_top_gsi_debug_sw_msk_regs_entry_rd_s{ + struct gsi_hwio_def_ipa_0_gsi_top_gsi_debug_sw_msk_reg_n_sec_k_rd_s + regs[GSI_HW_DEBUG_SW_MSK_REG_MAXk]; +}; + +struct gsi_hwio_gsi_top_gsi_debug_sw_msk_regs_rd_s{ + struct gsi_hwio_gsi_top_gsi_debug_sw_msk_regs_entry_rd_s + mask_reg[GSI_HW_DEBUG_SW_MSK_REG_ARRAY_LENGTH]; +}; + +/* GSI SHRAM pointers save data struct */ +struct ipa_reg_save_gsi_shram_ptr_regs_s { + struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_ch_cntxt_base_addr_s + ipa_gsi_top_gsi_shram_ptr_ch_cntxt_base_addr; + struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_ev_cntxt_base_addr_s + ipa_gsi_top_gsi_shram_ptr_ev_cntxt_base_addr; + struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_re_storage_base_addr_s + ipa_gsi_top_gsi_shram_ptr_re_storage_base_addr; + struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_re_esc_buf_base_addr_s + ipa_gsi_top_gsi_shram_ptr_re_esc_buf_base_addr; + struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_ee_scrach_base_addr_s + ipa_gsi_top_gsi_shram_ptr_ee_scrach_base_addr; + struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_func_stack_base_addr_s + ipa_gsi_top_gsi_shram_ptr_func_stack_base_addr; +}; + +/* GSI debug register save data struct */ +struct ipa_reg_save_gsi_debug_s { + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_busy_reg_s + ipa_gsi_top_gsi_debug_busy_reg; +#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_event_pending_s + ipa_gsi_top_gsi_debug_event_pending; + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_timer_pending_s + ipa_gsi_top_gsi_debug_timer_pending; + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_rd_wr_pending_s + ipa_gsi_top_gsi_debug_rd_wr_pending; +#endif + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_pc_from_sw_s + ipa_gsi_top_gsi_debug_pc_from_sw; + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_sw_stall_s + ipa_gsi_top_gsi_debug_sw_stall; + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_pc_for_debug_s + ipa_gsi_top_gsi_debug_pc_for_debug; + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_qsb_log_err_trns_id_s + ipa_gsi_top_gsi_debug_qsb_log_err_trns_id; + struct ipa_reg_save_gsi_qsb_debug_s gsi_qsb_debug; + struct ipa_reg_save_gsi_test_bus_s gsi_test_bus; + struct ipa_reg_save_gsi_mcs_regs_s gsi_mcs_regs; +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_reg_save_gsi_mcs_prof_regs_s gsi_mcs_prof_regs; +#endif + struct ipa_reg_save_gsi_debug_cnt_s gsi_cnt_regs; + struct ipa_reg_save_gsi_iram_ptr_regs_s gsi_iram_ptrs; + struct ipa_reg_save_gsi_shram_ptr_regs_s gsi_shram_ptrs; +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct gsi_hwio_gsi_top_gsi_debug_sw_msk_regs_rd_s + debug_sw_msk; +#endif +}; + +/* GSI MCS channel scratch registers save data struct */ +struct ipa_reg_save_gsi_mcs_channel_scratch_regs_s { + struct gsi_hwio_def_gsi_shram_n_s + scratch_for_seq_low; + struct gsi_hwio_def_gsi_shram_n_s + scratch_for_seq_high; +}; + +/* GSI Channel Context register save data struct */ +struct ipa_reg_save_gsi_ch_cntxt_per_ep_s { + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_0_s + ee_n_gsi_ch_k_cntxt_0; + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_1_s + ee_n_gsi_ch_k_cntxt_1; + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_2_s + ee_n_gsi_ch_k_cntxt_2; + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_3_s + ee_n_gsi_ch_k_cntxt_3; + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_4_s + ee_n_gsi_ch_k_cntxt_4; + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_5_s + ee_n_gsi_ch_k_cntxt_5; + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_6_s + ee_n_gsi_ch_k_cntxt_6; + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_7_s + ee_n_gsi_ch_k_cntxt_7; + struct gsi_hwio_def_ee_n_gsi_ch_k_re_fetch_read_ptr_s + ee_n_gsi_ch_k_re_fetch_read_ptr; + struct gsi_hwio_def_ee_n_gsi_ch_k_re_fetch_write_ptr_s + ee_n_gsi_ch_k_re_fetch_write_ptr; + struct gsi_hwio_def_ee_n_gsi_ch_k_qos_s + ee_n_gsi_ch_k_qos; + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_0_s + ee_n_gsi_ch_k_scratch_0; + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_1_s + ee_n_gsi_ch_k_scratch_1; + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_2_s + ee_n_gsi_ch_k_scratch_2; + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_3_s + ee_n_gsi_ch_k_scratch_3; +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_4_s + ee_n_gsi_ch_k_scratch_4; + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_5_s + ee_n_gsi_ch_k_scratch_5; + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_6_s + ee_n_gsi_ch_k_scratch_6; + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_7_s + ee_n_gsi_ch_k_scratch_7; + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_8_s + ee_n_gsi_ch_k_scratch_8; + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_9_s + ee_n_gsi_ch_k_scratch_9; +#endif + struct gsi_hwio_def_gsi_map_ee_n_ch_k_vp_table_s + gsi_map_ee_n_ch_k_vp_table; + struct ipa_reg_save_gsi_mcs_channel_scratch_regs_s + mcs_channel_scratch; +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + union ipa_hwio_def_fc_stats_state_u + fc_stats_state; +#endif +}; + +/* GSI Event Context register save data struct */ +struct ipa_reg_save_gsi_evt_cntxt_per_ep_s { + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_0_s + ee_n_ev_ch_k_cntxt_0; + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_1_s + ee_n_ev_ch_k_cntxt_1; + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_2_s + ee_n_ev_ch_k_cntxt_2; + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_3_s + ee_n_ev_ch_k_cntxt_3; + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_4_s + ee_n_ev_ch_k_cntxt_4; + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_5_s + ee_n_ev_ch_k_cntxt_5; + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_6_s + ee_n_ev_ch_k_cntxt_6; + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_7_s + ee_n_ev_ch_k_cntxt_7; + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_8_s + ee_n_ev_ch_k_cntxt_8; + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_9_s + ee_n_ev_ch_k_cntxt_9; + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_10_s + ee_n_ev_ch_k_cntxt_10; + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_11_s + ee_n_ev_ch_k_cntxt_11; + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_12_s + ee_n_ev_ch_k_cntxt_12; + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_13_s + ee_n_ev_ch_k_cntxt_13; + struct gsi_hwio_def_ee_n_ev_ch_k_scratch_0_s + ee_n_ev_ch_k_scratch_0; + struct gsi_hwio_def_ee_n_ev_ch_k_scratch_1_s + ee_n_ev_ch_k_scratch_1; + struct gsi_hwio_def_gsi_debug_ee_n_ev_k_vp_table_s + gsi_debug_ee_n_ev_k_vp_table; +}; + +/* GSI FIFO status register save data struct */ +struct ipa_reg_save_gsi_fifo_status_s { + union ipa_hwio_def_ipa_gsi_fifo_status_ctrl_u + gsi_fifo_status_ctrl; + union ipa_hwio_def_ipa_gsi_tlv_fifo_status_u + gsi_tlv_fifo_status; + union ipa_hwio_def_ipa_gsi_aos_fifo_status_u + gsi_aos_fifo_status; +}; + +/* GSI Channel Context register save top level data struct */ +struct ipa_reg_save_gsi_ch_cntxt_s { + struct ipa_reg_save_gsi_ch_cntxt_per_ep_s + a7[IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_A7]; + struct ipa_reg_save_gsi_ch_cntxt_per_ep_s + uc[IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_UC]; +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_reg_save_gsi_ch_cntxt_per_ep_s + q6[IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_Q6]; +#endif +}; + +/* GSI Event Context register save top level data struct */ +struct ipa_reg_save_gsi_evt_cntxt_s { + struct ipa_reg_save_gsi_evt_cntxt_per_ep_s + a7[IPA_HW_REG_SAVE_GSI_NUM_EVT_CNTXT_A7]; + struct ipa_reg_save_gsi_evt_cntxt_per_ep_s + uc[IPA_HW_REG_SAVE_GSI_NUM_EVT_CNTXT_UC]; +#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0 + struct ipa_reg_save_gsi_evt_cntxt_per_ep_s + q6[IPA_HW_REG_SAVE_GSI_NUM_EVT_CNTXT_Q6]; +#endif +}; + +/* Top level IPA register save data struct */ +struct ipa_regs_save_hierarchy_s { + struct ipa_gen_regs_s + gen; + struct ipa_reg_save_gen_ee_s + gen_ee[IPA_HW_EE_MAX]; + struct ipa_reg_save_stat_ee_s + stat_ee[IPA_HW_EE_MAX]; + struct ipa_reg_save_hwp_s + hwp; + struct ipa_reg_save_dbg_s + dbg; + struct ipa_reg_save_ipa_testbus_s + *testbus; + struct ipa_reg_save_pipe_s + pipes[IPA_HW_PIPE_ID_MAX]; + struct ipa_reg_save_src_rsrc_grp_s + src_rsrc_grp[IPA_HW_SRC_RSRP_TYPE_MAX]; + struct ipa_reg_save_dst_rsrc_grp_s + dst_rsrc_grp[IPA_HW_DST_RSRP_TYPE_MAX]; + struct ipa_reg_save_src_rsrc_cnt_s + src_rsrc_cnt[IPA_HW_SRC_RSRP_TYPE_MAX]; + struct ipa_reg_save_dst_rsrc_cnt_s + dst_rsrc_cnt[IPA_HW_DST_RSRP_TYPE_MAX]; + u32 *ipa_iu_ptr; + u32 *ipa_sram_ptr; + u32 *ipa_mbox_ptr; + u32 *ipa_hram_ptr; + u32 *ipa_seq_ptr; + u32 *ipa_gsi_ptr; +}; + +/* Top level GSI register save data struct */ +struct gsi_regs_save_hierarchy_s { + struct ipa_reg_save_gsi_fw_version_s fw_ver; + struct ipa_reg_save_gsi_gen_s gen; + struct ipa_reg_save_gsi_gen_ee_s gen_ee[IPA_REG_SAVE_GSI_NUM_EE]; + struct ipa_reg_save_gsi_ch_cntxt_s ch_cntxt; + struct ipa_reg_save_gsi_evt_cntxt_s evt_cntxt; + struct ipa_reg_save_gsi_debug_s debug; +}; + +/* Source resources for a resource group */ +struct ipa_reg_save_src_rsrc_cnts_s { + u8 pkt_cntxt; + u8 descriptor_list; + u8 data_descriptor_buffer; + u8 hps_dmars; + u8 reserved_acks; +}; + +/* Destination resources for a resource group */ +struct ipa_reg_save_dst_rsrc_cnts_s { + u8 reserved_sectors; + u8 dps_dmars; +}; + +/* Resource count structure for a resource group */ +struct ipa_reg_save_rsrc_cnts_per_grp_s { + /* Resource group number */ + u8 resource_group; + /* Source resources for a resource group */ + struct ipa_reg_save_src_rsrc_cnts_s src; + /* Destination resources for a resource group */ + struct ipa_reg_save_dst_rsrc_cnts_s dst; +}; + +/* Top level resource count structure */ +struct ipa_reg_save_rsrc_cnts_s { + /* Resource count structure for PCIE group */ + struct ipa_reg_save_rsrc_cnts_per_grp_s pcie; + /* Resource count structure for DDR group */ + struct ipa_reg_save_rsrc_cnts_per_grp_s ddr; +}; + +/* + * Top level IPA and GSI registers save data struct + */ +struct regs_save_hierarchy_s { + struct ipa_regs_save_hierarchy_s + ipa; + struct gsi_regs_save_hierarchy_s + gsi; + bool + pkt_ctntx_active[IPA_HW_PKT_CTNTX_MAX]; + union ipa_hwio_def_ipa_ctxh_ctrl_u + pkt_ctntxt_lock; + enum ipa_hw_pkt_cntxt_state_e + pkt_cntxt_state[IPA_HW_PKT_CTNTX_MAX]; + struct ipa_pkt_ctntx_s + pkt_ctntx[IPA_HW_PKT_CTNTX_MAX]; + struct ipa_reg_save_rsrc_cnts_s + rsrc_cnts; + struct ipa_reg_save_gsi_fifo_status_s + gsi_fifo_status[IPA_HW_PIPE_ID_MAX]; +}; + +/* + * The following section deals with handling IPA registers' memory + * access relative to pre-defined memory protection schemes + * (ie. "access control"). + * + * In a nut shell, the intent of the data stuctures below is to allow + * higher level register accessors to be unaware of what really is + * going on at the lowest level (ie. real vs non-real access). This + * methodology is also designed to allow for platform specific "access + * maps." + */ + +/* + * Function for doing an actual read + */ +static inline u32 +act_read(void __iomem *addr) +{ + u32 val = ioread32(addr); + + return val; +} + +/* + * Function for doing an actual write + */ +static inline void +act_write(void __iomem *addr, u32 val) +{ + iowrite32(val, addr); +} + +/* + * Function that pretends to do a read + */ +static inline u32 +nop_read(void __iomem *addr) +{ + return IPA_MEM_INIT_VAL; +} + +/* + * Function that pretends to do a write + */ +static inline void +nop_write(void __iomem *addr, u32 val) +{ +} + +/* + * The following are used to define struct reg_access_funcs_s below... + */ +typedef u32 (*reg_read_func_t)( + void __iomem *addr); +typedef void (*reg_write_func_t)( + void __iomem *addr, + u32 val); + +/* + * The following in used to define io_matrix[] below... + */ +struct reg_access_funcs_s { + reg_read_func_t read; + reg_write_func_t write; +}; + +/* + * The following will be used to appropriately index into the + * read/write combos defined in io_matrix[] below... + */ +#define AA_COMBO 0 /* actual read, actual write */ +#define AN_COMBO 1 /* actual read, no-op write */ +#define NA_COMBO 2 /* no-op read, actual write */ +#define NN_COMBO 3 /* no-op read, no-op write */ + +/* + * The following will be used to dictate registers' access methods + * relative to the state of secure debug...whether it's enabled or + * disabled. + * + * NOTE: The table below defines all access combinations. + */ +static struct reg_access_funcs_s io_matrix[] = { + { act_read, act_write }, /* the AA_COMBO */ + { act_read, nop_write }, /* the AN_COMBO */ + { nop_read, act_write }, /* the NA_COMBO */ + { nop_read, nop_write }, /* the NN_COMBO */ +}; + +/* + * The following will be used to define and drive IPA's register + * access rules. + */ +struct reg_mem_access_map_t { + u32 addr_range_begin; + u32 addr_range_end; + struct reg_access_funcs_s *access[2]; +}; + +#endif /* #if !defined(_IPA_REG_DUMP_H_) */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.5/gsi_hwio.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.5/gsi_hwio.h new file mode 100644 index 0000000000..efbdf4805d --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.5/gsi_hwio.h @@ -0,0 +1,3455 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef __GSI_HWIO_H__ +#define __GSI_HWIO_H__ +/** + @file gsi_hwio.h + @brief Auto-generated HWIO interface include file. + + This file contains HWIO register definitions for the following modules: + IPA_0_GSI_TOP_.* + GSI_TOP.* + + 'Include' filters applied: + 'Exclude' filters applied: RESERVED DUMMY + + Attribute definitions for the HWIO_*_ATTR macros are as follows: + 0x0: Command register + 0x1: Read-Only + 0x2: Write-Only + 0x3: Read/Write +*/ + +/*---------------------------------------------------------------------------- + * MODULE: GSI + *--------------------------------------------------------------------------*/ + +#define GSI_REG_BASE (IPA_0_IPA_WRAPPER_BASE + 0x00004000) +#define GSI_REG_BASE_PHYS (IPA_0_IPA_WRAPPER_BASE_PHYS + 0x00004000) +#define GSI_REG_BASE_OFFS 0x00004000 + +#define HWIO_GSI_CFG_ADDR (GSI_REG_BASE + 0x00000000) +#define HWIO_GSI_CFG_PHYS (GSI_REG_BASE_PHYS + 0x00000000) +#define HWIO_GSI_CFG_OFFS (GSI_REG_BASE_OFFS + 0x00000000) +#define HWIO_GSI_CFG_RMSK 0xf3f +#define HWIO_GSI_CFG_ATTR 0x3 +#define HWIO_GSI_CFG_IN \ + in_dword_masked(HWIO_GSI_CFG_ADDR, HWIO_GSI_CFG_RMSK) +#define HWIO_GSI_CFG_INM(m) \ + in_dword_masked(HWIO_GSI_CFG_ADDR, m) +#define HWIO_GSI_CFG_OUT(v) \ + out_dword(HWIO_GSI_CFG_ADDR,v) +#define HWIO_GSI_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_CFG_ADDR,m,v,HWIO_GSI_CFG_IN) +#define HWIO_GSI_CFG_SLEEP_CLK_DIV_BMSK 0xf00 +#define HWIO_GSI_CFG_SLEEP_CLK_DIV_SHFT 0x8 +#define HWIO_GSI_CFG_BP_MTRIX_DISABLE_BMSK 0x20 +#define HWIO_GSI_CFG_BP_MTRIX_DISABLE_SHFT 0x5 +#define HWIO_GSI_CFG_GSI_PWR_CLPS_BMSK 0x10 +#define HWIO_GSI_CFG_GSI_PWR_CLPS_SHFT 0x4 +#define HWIO_GSI_CFG_UC_IS_MCS_BMSK 0x8 +#define HWIO_GSI_CFG_UC_IS_MCS_SHFT 0x3 +#define HWIO_GSI_CFG_DOUBLE_MCS_CLK_FREQ_BMSK 0x4 +#define HWIO_GSI_CFG_DOUBLE_MCS_CLK_FREQ_SHFT 0x2 +#define HWIO_GSI_CFG_MCS_ENABLE_BMSK 0x2 +#define HWIO_GSI_CFG_MCS_ENABLE_SHFT 0x1 +#define HWIO_GSI_CFG_GSI_ENABLE_BMSK 0x1 +#define HWIO_GSI_CFG_GSI_ENABLE_SHFT 0x0 + +#define HWIO_GSI_MANAGER_MCS_CODE_VER_ADDR (GSI_REG_BASE + 0x00000008) +#define HWIO_GSI_MANAGER_MCS_CODE_VER_PHYS (GSI_REG_BASE_PHYS + 0x00000008) +#define HWIO_GSI_MANAGER_MCS_CODE_VER_OFFS (GSI_REG_BASE_OFFS + 0x00000008) +#define HWIO_GSI_MANAGER_MCS_CODE_VER_RMSK 0xffffffff +#define HWIO_GSI_MANAGER_MCS_CODE_VER_ATTR 0x3 +#define HWIO_GSI_MANAGER_MCS_CODE_VER_IN \ + in_dword_masked(HWIO_GSI_MANAGER_MCS_CODE_VER_ADDR, HWIO_GSI_MANAGER_MCS_CODE_VER_RMSK) +#define HWIO_GSI_MANAGER_MCS_CODE_VER_INM(m) \ + in_dword_masked(HWIO_GSI_MANAGER_MCS_CODE_VER_ADDR, m) +#define HWIO_GSI_MANAGER_MCS_CODE_VER_OUT(v) \ + out_dword(HWIO_GSI_MANAGER_MCS_CODE_VER_ADDR,v) +#define HWIO_GSI_MANAGER_MCS_CODE_VER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_MANAGER_MCS_CODE_VER_ADDR,m,v,HWIO_GSI_MANAGER_MCS_CODE_VER_IN) +#define HWIO_GSI_MANAGER_MCS_CODE_VER_VER_BMSK 0xffffffff +#define HWIO_GSI_MANAGER_MCS_CODE_VER_VER_SHFT 0x0 + +#define HWIO_GSI_ZEROS_ADDR (GSI_REG_BASE + 0x00000010) +#define HWIO_GSI_ZEROS_PHYS (GSI_REG_BASE_PHYS + 0x00000010) +#define HWIO_GSI_ZEROS_OFFS (GSI_REG_BASE_OFFS + 0x00000010) +#define HWIO_GSI_ZEROS_RMSK 0xffffffff +#define HWIO_GSI_ZEROS_ATTR 0x1 +#define HWIO_GSI_ZEROS_IN \ + in_dword_masked(HWIO_GSI_ZEROS_ADDR, HWIO_GSI_ZEROS_RMSK) +#define HWIO_GSI_ZEROS_INM(m) \ + in_dword_masked(HWIO_GSI_ZEROS_ADDR, m) +#define HWIO_GSI_ZEROS_ZEROS_BMSK 0xffffffff +#define HWIO_GSI_ZEROS_ZEROS_SHFT 0x0 + +#define HWIO_GSI_PERIPH_BASE_ADDR_LSB_ADDR (GSI_REG_BASE + 0x00000018) +#define HWIO_GSI_PERIPH_BASE_ADDR_LSB_PHYS (GSI_REG_BASE_PHYS + 0x00000018) +#define HWIO_GSI_PERIPH_BASE_ADDR_LSB_OFFS (GSI_REG_BASE_OFFS + 0x00000018) +#define HWIO_GSI_PERIPH_BASE_ADDR_LSB_RMSK 0xffffffff +#define HWIO_GSI_PERIPH_BASE_ADDR_LSB_ATTR 0x3 +#define HWIO_GSI_PERIPH_BASE_ADDR_LSB_IN \ + in_dword_masked(HWIO_GSI_PERIPH_BASE_ADDR_LSB_ADDR, HWIO_GSI_PERIPH_BASE_ADDR_LSB_RMSK) +#define HWIO_GSI_PERIPH_BASE_ADDR_LSB_INM(m) \ + in_dword_masked(HWIO_GSI_PERIPH_BASE_ADDR_LSB_ADDR, m) +#define HWIO_GSI_PERIPH_BASE_ADDR_LSB_OUT(v) \ + out_dword(HWIO_GSI_PERIPH_BASE_ADDR_LSB_ADDR,v) +#define HWIO_GSI_PERIPH_BASE_ADDR_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_PERIPH_BASE_ADDR_LSB_ADDR,m,v,HWIO_GSI_PERIPH_BASE_ADDR_LSB_IN) +#define HWIO_GSI_PERIPH_BASE_ADDR_LSB_BASE_ADDR_BMSK 0xffffffff +#define HWIO_GSI_PERIPH_BASE_ADDR_LSB_BASE_ADDR_SHFT 0x0 + +#define HWIO_GSI_PERIPH_BASE_ADDR_MSB_ADDR (GSI_REG_BASE + 0x0000001c) +#define HWIO_GSI_PERIPH_BASE_ADDR_MSB_PHYS (GSI_REG_BASE_PHYS + 0x0000001c) +#define HWIO_GSI_PERIPH_BASE_ADDR_MSB_OFFS (GSI_REG_BASE_OFFS + 0x0000001c) +#define HWIO_GSI_PERIPH_BASE_ADDR_MSB_RMSK 0xffffffff +#define HWIO_GSI_PERIPH_BASE_ADDR_MSB_ATTR 0x3 +#define HWIO_GSI_PERIPH_BASE_ADDR_MSB_IN \ + in_dword_masked(HWIO_GSI_PERIPH_BASE_ADDR_MSB_ADDR, HWIO_GSI_PERIPH_BASE_ADDR_MSB_RMSK) +#define HWIO_GSI_PERIPH_BASE_ADDR_MSB_INM(m) \ + in_dword_masked(HWIO_GSI_PERIPH_BASE_ADDR_MSB_ADDR, m) +#define HWIO_GSI_PERIPH_BASE_ADDR_MSB_OUT(v) \ + out_dword(HWIO_GSI_PERIPH_BASE_ADDR_MSB_ADDR,v) +#define HWIO_GSI_PERIPH_BASE_ADDR_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_PERIPH_BASE_ADDR_MSB_ADDR,m,v,HWIO_GSI_PERIPH_BASE_ADDR_MSB_IN) +#define HWIO_GSI_PERIPH_BASE_ADDR_MSB_BASE_ADDR_BMSK 0xffffffff +#define HWIO_GSI_PERIPH_BASE_ADDR_MSB_BASE_ADDR_SHFT 0x0 + +#define HWIO_GSI_CGC_CTRL_ADDR (GSI_REG_BASE + 0x00000020) +#define HWIO_GSI_CGC_CTRL_PHYS (GSI_REG_BASE_PHYS + 0x00000020) +#define HWIO_GSI_CGC_CTRL_OFFS (GSI_REG_BASE_OFFS + 0x00000020) +#define HWIO_GSI_CGC_CTRL_RMSK 0xffff +#define HWIO_GSI_CGC_CTRL_ATTR 0x3 +#define HWIO_GSI_CGC_CTRL_IN \ + in_dword_masked(HWIO_GSI_CGC_CTRL_ADDR, HWIO_GSI_CGC_CTRL_RMSK) +#define HWIO_GSI_CGC_CTRL_INM(m) \ + in_dword_masked(HWIO_GSI_CGC_CTRL_ADDR, m) +#define HWIO_GSI_CGC_CTRL_OUT(v) \ + out_dword(HWIO_GSI_CGC_CTRL_ADDR,v) +#define HWIO_GSI_CGC_CTRL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_CGC_CTRL_ADDR,m,v,HWIO_GSI_CGC_CTRL_IN) +#define HWIO_GSI_CGC_CTRL_REGION_16_HW_CGC_EN_BMSK 0x8000 +#define HWIO_GSI_CGC_CTRL_REGION_16_HW_CGC_EN_SHFT 0xf +#define HWIO_GSI_CGC_CTRL_REGION_15_HW_CGC_EN_BMSK 0x4000 +#define HWIO_GSI_CGC_CTRL_REGION_15_HW_CGC_EN_SHFT 0xe +#define HWIO_GSI_CGC_CTRL_REGION_14_HW_CGC_EN_BMSK 0x2000 +#define HWIO_GSI_CGC_CTRL_REGION_14_HW_CGC_EN_SHFT 0xd +#define HWIO_GSI_CGC_CTRL_REGION_13_HW_CGC_EN_BMSK 0x1000 +#define HWIO_GSI_CGC_CTRL_REGION_13_HW_CGC_EN_SHFT 0xc +#define HWIO_GSI_CGC_CTRL_REGION_12_HW_CGC_EN_BMSK 0x800 +#define HWIO_GSI_CGC_CTRL_REGION_12_HW_CGC_EN_SHFT 0xb +#define HWIO_GSI_CGC_CTRL_REGION_11_HW_CGC_EN_BMSK 0x400 +#define HWIO_GSI_CGC_CTRL_REGION_11_HW_CGC_EN_SHFT 0xa +#define HWIO_GSI_CGC_CTRL_REGION_10_HW_CGC_EN_BMSK 0x200 +#define HWIO_GSI_CGC_CTRL_REGION_10_HW_CGC_EN_SHFT 0x9 +#define HWIO_GSI_CGC_CTRL_REGION_9_HW_CGC_EN_BMSK 0x100 +#define HWIO_GSI_CGC_CTRL_REGION_9_HW_CGC_EN_SHFT 0x8 +#define HWIO_GSI_CGC_CTRL_REGION_8_HW_CGC_EN_BMSK 0x80 +#define HWIO_GSI_CGC_CTRL_REGION_8_HW_CGC_EN_SHFT 0x7 +#define HWIO_GSI_CGC_CTRL_REGION_7_HW_CGC_EN_BMSK 0x40 +#define HWIO_GSI_CGC_CTRL_REGION_7_HW_CGC_EN_SHFT 0x6 +#define HWIO_GSI_CGC_CTRL_REGION_6_HW_CGC_EN_BMSK 0x20 +#define HWIO_GSI_CGC_CTRL_REGION_6_HW_CGC_EN_SHFT 0x5 +#define HWIO_GSI_CGC_CTRL_REGION_5_HW_CGC_EN_BMSK 0x10 +#define HWIO_GSI_CGC_CTRL_REGION_5_HW_CGC_EN_SHFT 0x4 +#define HWIO_GSI_CGC_CTRL_REGION_4_HW_CGC_EN_BMSK 0x8 +#define HWIO_GSI_CGC_CTRL_REGION_4_HW_CGC_EN_SHFT 0x3 +#define HWIO_GSI_CGC_CTRL_REGION_3_HW_CGC_EN_BMSK 0x4 +#define HWIO_GSI_CGC_CTRL_REGION_3_HW_CGC_EN_SHFT 0x2 +#define HWIO_GSI_CGC_CTRL_REGION_2_HW_CGC_EN_BMSK 0x2 +#define HWIO_GSI_CGC_CTRL_REGION_2_HW_CGC_EN_SHFT 0x1 +#define HWIO_GSI_CGC_CTRL_REGION_1_HW_CGC_EN_BMSK 0x1 +#define HWIO_GSI_CGC_CTRL_REGION_1_HW_CGC_EN_SHFT 0x0 + +#define HWIO_GSI_MOQA_CFG_ADDR (GSI_REG_BASE + 0x00000030) +#define HWIO_GSI_MOQA_CFG_PHYS (GSI_REG_BASE_PHYS + 0x00000030) +#define HWIO_GSI_MOQA_CFG_OFFS (GSI_REG_BASE_OFFS + 0x00000030) +#define HWIO_GSI_MOQA_CFG_RMSK 0xffffff +#define HWIO_GSI_MOQA_CFG_ATTR 0x3 +#define HWIO_GSI_MOQA_CFG_IN \ + in_dword_masked(HWIO_GSI_MOQA_CFG_ADDR, HWIO_GSI_MOQA_CFG_RMSK) +#define HWIO_GSI_MOQA_CFG_INM(m) \ + in_dword_masked(HWIO_GSI_MOQA_CFG_ADDR, m) +#define HWIO_GSI_MOQA_CFG_OUT(v) \ + out_dword(HWIO_GSI_MOQA_CFG_ADDR,v) +#define HWIO_GSI_MOQA_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_MOQA_CFG_ADDR,m,v,HWIO_GSI_MOQA_CFG_IN) +#define HWIO_GSI_MOQA_CFG_CLIENT_OOWR_BMSK 0xff0000 +#define HWIO_GSI_MOQA_CFG_CLIENT_OOWR_SHFT 0x10 +#define HWIO_GSI_MOQA_CFG_CLIENT_OORD_BMSK 0xff00 +#define HWIO_GSI_MOQA_CFG_CLIENT_OORD_SHFT 0x8 +#define HWIO_GSI_MOQA_CFG_CLIENT_REQ_PRIO_BMSK 0xff +#define HWIO_GSI_MOQA_CFG_CLIENT_REQ_PRIO_SHFT 0x0 + +#define HWIO_GSI_REE_CFG_ADDR (GSI_REG_BASE + 0x00000038) +#define HWIO_GSI_REE_CFG_PHYS (GSI_REG_BASE_PHYS + 0x00000038) +#define HWIO_GSI_REE_CFG_OFFS (GSI_REG_BASE_OFFS + 0x00000038) +#define HWIO_GSI_REE_CFG_RMSK 0xff03 +#define HWIO_GSI_REE_CFG_ATTR 0x3 +#define HWIO_GSI_REE_CFG_IN \ + in_dword_masked(HWIO_GSI_REE_CFG_ADDR, HWIO_GSI_REE_CFG_RMSK) +#define HWIO_GSI_REE_CFG_INM(m) \ + in_dword_masked(HWIO_GSI_REE_CFG_ADDR, m) +#define HWIO_GSI_REE_CFG_OUT(v) \ + out_dword(HWIO_GSI_REE_CFG_ADDR,v) +#define HWIO_GSI_REE_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_REE_CFG_ADDR,m,v,HWIO_GSI_REE_CFG_IN) +#define HWIO_GSI_REE_CFG_MAX_BURST_SIZE_BMSK 0xff00 +#define HWIO_GSI_REE_CFG_MAX_BURST_SIZE_SHFT 0x8 +#define HWIO_GSI_REE_CFG_CHANNEL_EMPTY_INT_ENABLE_BMSK 0x2 +#define HWIO_GSI_REE_CFG_CHANNEL_EMPTY_INT_ENABLE_SHFT 0x1 +#define HWIO_GSI_REE_CFG_MOVE_TO_ESC_CLR_MODE_TRSH_BMSK 0x1 +#define HWIO_GSI_REE_CFG_MOVE_TO_ESC_CLR_MODE_TRSH_SHFT 0x0 + +#define HWIO_GSI_PERIPH_PENDING_k_ADDR(k) (GSI_REG_BASE + 0x00000060 + 0x4 * (k)) +#define HWIO_GSI_PERIPH_PENDING_k_PHYS(k) (GSI_REG_BASE_PHYS + 0x00000060 + 0x4 * (k)) +#define HWIO_GSI_PERIPH_PENDING_k_OFFS(k) (GSI_REG_BASE_OFFS + 0x00000060 + 0x4 * (k)) +#define HWIO_GSI_PERIPH_PENDING_k_RMSK 0xffffffff +#define HWIO_GSI_PERIPH_PENDING_k_MAXk 1 +#define HWIO_GSI_PERIPH_PENDING_k_ATTR 0x1 +#define HWIO_GSI_PERIPH_PENDING_k_INI(k) \ + in_dword_masked(HWIO_GSI_PERIPH_PENDING_k_ADDR(k), HWIO_GSI_PERIPH_PENDING_k_RMSK) +#define HWIO_GSI_PERIPH_PENDING_k_INMI(k,mask) \ + in_dword_masked(HWIO_GSI_PERIPH_PENDING_k_ADDR(k), mask) +#define HWIO_GSI_PERIPH_PENDING_k_CHID_BIT_MAP_BMSK 0xffffffff +#define HWIO_GSI_PERIPH_PENDING_k_CHID_BIT_MAP_SHFT 0x0 + +#define HWIO_GSI_MSI_CACHEATTR_ADDR (GSI_REG_BASE + 0x00000080) +#define HWIO_GSI_MSI_CACHEATTR_PHYS (GSI_REG_BASE_PHYS + 0x00000080) +#define HWIO_GSI_MSI_CACHEATTR_OFFS (GSI_REG_BASE_OFFS + 0x00000080) +#define HWIO_GSI_MSI_CACHEATTR_RMSK 0x3f +#define HWIO_GSI_MSI_CACHEATTR_ATTR 0x3 +#define HWIO_GSI_MSI_CACHEATTR_IN \ + in_dword_masked(HWIO_GSI_MSI_CACHEATTR_ADDR, HWIO_GSI_MSI_CACHEATTR_RMSK) +#define HWIO_GSI_MSI_CACHEATTR_INM(m) \ + in_dword_masked(HWIO_GSI_MSI_CACHEATTR_ADDR, m) +#define HWIO_GSI_MSI_CACHEATTR_OUT(v) \ + out_dword(HWIO_GSI_MSI_CACHEATTR_ADDR,v) +#define HWIO_GSI_MSI_CACHEATTR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_MSI_CACHEATTR_ADDR,m,v,HWIO_GSI_MSI_CACHEATTR_IN) +#define HWIO_GSI_MSI_CACHEATTR_AREQPRIORITY_BMSK 0x30 +#define HWIO_GSI_MSI_CACHEATTR_AREQPRIORITY_SHFT 0x4 +#define HWIO_GSI_MSI_CACHEATTR_ATRANSIENT_BMSK 0x8 +#define HWIO_GSI_MSI_CACHEATTR_ATRANSIENT_SHFT 0x3 +#define HWIO_GSI_MSI_CACHEATTR_ANOALLOCATE_BMSK 0x4 +#define HWIO_GSI_MSI_CACHEATTR_ANOALLOCATE_SHFT 0x2 +#define HWIO_GSI_MSI_CACHEATTR_AINNERSHARED_BMSK 0x2 +#define HWIO_GSI_MSI_CACHEATTR_AINNERSHARED_SHFT 0x1 +#define HWIO_GSI_MSI_CACHEATTR_ASHARED_BMSK 0x1 +#define HWIO_GSI_MSI_CACHEATTR_ASHARED_SHFT 0x0 + +#define HWIO_GSI_EVENT_CACHEATTR_ADDR (GSI_REG_BASE + 0x00000084) +#define HWIO_GSI_EVENT_CACHEATTR_PHYS (GSI_REG_BASE_PHYS + 0x00000084) +#define HWIO_GSI_EVENT_CACHEATTR_OFFS (GSI_REG_BASE_OFFS + 0x00000084) +#define HWIO_GSI_EVENT_CACHEATTR_RMSK 0x3f +#define HWIO_GSI_EVENT_CACHEATTR_ATTR 0x3 +#define HWIO_GSI_EVENT_CACHEATTR_IN \ + in_dword_masked(HWIO_GSI_EVENT_CACHEATTR_ADDR, HWIO_GSI_EVENT_CACHEATTR_RMSK) +#define HWIO_GSI_EVENT_CACHEATTR_INM(m) \ + in_dword_masked(HWIO_GSI_EVENT_CACHEATTR_ADDR, m) +#define HWIO_GSI_EVENT_CACHEATTR_OUT(v) \ + out_dword(HWIO_GSI_EVENT_CACHEATTR_ADDR,v) +#define HWIO_GSI_EVENT_CACHEATTR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_EVENT_CACHEATTR_ADDR,m,v,HWIO_GSI_EVENT_CACHEATTR_IN) +#define HWIO_GSI_EVENT_CACHEATTR_AREQPRIORITY_BMSK 0x30 +#define HWIO_GSI_EVENT_CACHEATTR_AREQPRIORITY_SHFT 0x4 +#define HWIO_GSI_EVENT_CACHEATTR_ATRANSIENT_BMSK 0x8 +#define HWIO_GSI_EVENT_CACHEATTR_ATRANSIENT_SHFT 0x3 +#define HWIO_GSI_EVENT_CACHEATTR_ANOALLOCATE_BMSK 0x4 +#define HWIO_GSI_EVENT_CACHEATTR_ANOALLOCATE_SHFT 0x2 +#define HWIO_GSI_EVENT_CACHEATTR_AINNERSHARED_BMSK 0x2 +#define HWIO_GSI_EVENT_CACHEATTR_AINNERSHARED_SHFT 0x1 +#define HWIO_GSI_EVENT_CACHEATTR_ASHARED_BMSK 0x1 +#define HWIO_GSI_EVENT_CACHEATTR_ASHARED_SHFT 0x0 + +#define HWIO_GSI_DATA_CACHEATTR_ADDR (GSI_REG_BASE + 0x00000088) +#define HWIO_GSI_DATA_CACHEATTR_PHYS (GSI_REG_BASE_PHYS + 0x00000088) +#define HWIO_GSI_DATA_CACHEATTR_OFFS (GSI_REG_BASE_OFFS + 0x00000088) +#define HWIO_GSI_DATA_CACHEATTR_RMSK 0x3f +#define HWIO_GSI_DATA_CACHEATTR_ATTR 0x3 +#define HWIO_GSI_DATA_CACHEATTR_IN \ + in_dword_masked(HWIO_GSI_DATA_CACHEATTR_ADDR, HWIO_GSI_DATA_CACHEATTR_RMSK) +#define HWIO_GSI_DATA_CACHEATTR_INM(m) \ + in_dword_masked(HWIO_GSI_DATA_CACHEATTR_ADDR, m) +#define HWIO_GSI_DATA_CACHEATTR_OUT(v) \ + out_dword(HWIO_GSI_DATA_CACHEATTR_ADDR,v) +#define HWIO_GSI_DATA_CACHEATTR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_DATA_CACHEATTR_ADDR,m,v,HWIO_GSI_DATA_CACHEATTR_IN) +#define HWIO_GSI_DATA_CACHEATTR_AREQPRIORITY_BMSK 0x30 +#define HWIO_GSI_DATA_CACHEATTR_AREQPRIORITY_SHFT 0x4 +#define HWIO_GSI_DATA_CACHEATTR_ATRANSIENT_BMSK 0x8 +#define HWIO_GSI_DATA_CACHEATTR_ATRANSIENT_SHFT 0x3 +#define HWIO_GSI_DATA_CACHEATTR_ANOALLOCATE_BMSK 0x4 +#define HWIO_GSI_DATA_CACHEATTR_ANOALLOCATE_SHFT 0x2 +#define HWIO_GSI_DATA_CACHEATTR_AINNERSHARED_BMSK 0x2 +#define HWIO_GSI_DATA_CACHEATTR_AINNERSHARED_SHFT 0x1 +#define HWIO_GSI_DATA_CACHEATTR_ASHARED_BMSK 0x1 +#define HWIO_GSI_DATA_CACHEATTR_ASHARED_SHFT 0x0 + +#define HWIO_GSI_TRE_CACHEATTR_ADDR (GSI_REG_BASE + 0x00000090) +#define HWIO_GSI_TRE_CACHEATTR_PHYS (GSI_REG_BASE_PHYS + 0x00000090) +#define HWIO_GSI_TRE_CACHEATTR_OFFS (GSI_REG_BASE_OFFS + 0x00000090) +#define HWIO_GSI_TRE_CACHEATTR_RMSK 0x3f +#define HWIO_GSI_TRE_CACHEATTR_ATTR 0x3 +#define HWIO_GSI_TRE_CACHEATTR_IN \ + in_dword_masked(HWIO_GSI_TRE_CACHEATTR_ADDR, HWIO_GSI_TRE_CACHEATTR_RMSK) +#define HWIO_GSI_TRE_CACHEATTR_INM(m) \ + in_dword_masked(HWIO_GSI_TRE_CACHEATTR_ADDR, m) +#define HWIO_GSI_TRE_CACHEATTR_OUT(v) \ + out_dword(HWIO_GSI_TRE_CACHEATTR_ADDR,v) +#define HWIO_GSI_TRE_CACHEATTR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_TRE_CACHEATTR_ADDR,m,v,HWIO_GSI_TRE_CACHEATTR_IN) +#define HWIO_GSI_TRE_CACHEATTR_AREQPRIORITY_BMSK 0x30 +#define HWIO_GSI_TRE_CACHEATTR_AREQPRIORITY_SHFT 0x4 +#define HWIO_GSI_TRE_CACHEATTR_ATRANSIENT_BMSK 0x8 +#define HWIO_GSI_TRE_CACHEATTR_ATRANSIENT_SHFT 0x3 +#define HWIO_GSI_TRE_CACHEATTR_ANOALLOCATE_BMSK 0x4 +#define HWIO_GSI_TRE_CACHEATTR_ANOALLOCATE_SHFT 0x2 +#define HWIO_GSI_TRE_CACHEATTR_AINNERSHARED_BMSK 0x2 +#define HWIO_GSI_TRE_CACHEATTR_AINNERSHARED_SHFT 0x1 +#define HWIO_GSI_TRE_CACHEATTR_ASHARED_BMSK 0x1 +#define HWIO_GSI_TRE_CACHEATTR_ASHARED_SHFT 0x0 + +#define HWIO_IC_INT_WEIGHT_REE_ADDR (GSI_REG_BASE + 0x00000100) +#define HWIO_IC_INT_WEIGHT_REE_PHYS (GSI_REG_BASE_PHYS + 0x00000100) +#define HWIO_IC_INT_WEIGHT_REE_OFFS (GSI_REG_BASE_OFFS + 0x00000100) +#define HWIO_IC_INT_WEIGHT_REE_RMSK 0xfff +#define HWIO_IC_INT_WEIGHT_REE_ATTR 0x3 +#define HWIO_IC_INT_WEIGHT_REE_IN \ + in_dword_masked(HWIO_IC_INT_WEIGHT_REE_ADDR, HWIO_IC_INT_WEIGHT_REE_RMSK) +#define HWIO_IC_INT_WEIGHT_REE_INM(m) \ + in_dword_masked(HWIO_IC_INT_WEIGHT_REE_ADDR, m) +#define HWIO_IC_INT_WEIGHT_REE_OUT(v) \ + out_dword(HWIO_IC_INT_WEIGHT_REE_ADDR,v) +#define HWIO_IC_INT_WEIGHT_REE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IC_INT_WEIGHT_REE_ADDR,m,v,HWIO_IC_INT_WEIGHT_REE_IN) +#define HWIO_IC_INT_WEIGHT_REE_CH_EMPTY_INT_WEIGHT_BMSK 0xf00 +#define HWIO_IC_INT_WEIGHT_REE_CH_EMPTY_INT_WEIGHT_SHFT 0x8 +#define HWIO_IC_INT_WEIGHT_REE_NEW_RE_INT_WEIGHT_BMSK 0xf0 +#define HWIO_IC_INT_WEIGHT_REE_NEW_RE_INT_WEIGHT_SHFT 0x4 +#define HWIO_IC_INT_WEIGHT_REE_STOP_CH_COMP_INT_WEIGHT_BMSK 0xf +#define HWIO_IC_INT_WEIGHT_REE_STOP_CH_COMP_INT_WEIGHT_SHFT 0x0 + +#define HWIO_IC_INT_WEIGHT_EVT_ENG_ADDR (GSI_REG_BASE + 0x00000104) +#define HWIO_IC_INT_WEIGHT_EVT_ENG_PHYS (GSI_REG_BASE_PHYS + 0x00000104) +#define HWIO_IC_INT_WEIGHT_EVT_ENG_OFFS (GSI_REG_BASE_OFFS + 0x00000104) +#define HWIO_IC_INT_WEIGHT_EVT_ENG_RMSK 0xf +#define HWIO_IC_INT_WEIGHT_EVT_ENG_ATTR 0x3 +#define HWIO_IC_INT_WEIGHT_EVT_ENG_IN \ + in_dword_masked(HWIO_IC_INT_WEIGHT_EVT_ENG_ADDR, HWIO_IC_INT_WEIGHT_EVT_ENG_RMSK) +#define HWIO_IC_INT_WEIGHT_EVT_ENG_INM(m) \ + in_dword_masked(HWIO_IC_INT_WEIGHT_EVT_ENG_ADDR, m) +#define HWIO_IC_INT_WEIGHT_EVT_ENG_OUT(v) \ + out_dword(HWIO_IC_INT_WEIGHT_EVT_ENG_ADDR,v) +#define HWIO_IC_INT_WEIGHT_EVT_ENG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IC_INT_WEIGHT_EVT_ENG_ADDR,m,v,HWIO_IC_INT_WEIGHT_EVT_ENG_IN) +#define HWIO_IC_INT_WEIGHT_EVT_ENG_EVNT_ENG_INT_WEIGHT_BMSK 0xf +#define HWIO_IC_INT_WEIGHT_EVT_ENG_EVNT_ENG_INT_WEIGHT_SHFT 0x0 + +#define HWIO_IC_INT_WEIGHT_INT_ENG_ADDR (GSI_REG_BASE + 0x00000108) +#define HWIO_IC_INT_WEIGHT_INT_ENG_PHYS (GSI_REG_BASE_PHYS + 0x00000108) +#define HWIO_IC_INT_WEIGHT_INT_ENG_OFFS (GSI_REG_BASE_OFFS + 0x00000108) +#define HWIO_IC_INT_WEIGHT_INT_ENG_RMSK 0xf +#define HWIO_IC_INT_WEIGHT_INT_ENG_ATTR 0x3 +#define HWIO_IC_INT_WEIGHT_INT_ENG_IN \ + in_dword_masked(HWIO_IC_INT_WEIGHT_INT_ENG_ADDR, HWIO_IC_INT_WEIGHT_INT_ENG_RMSK) +#define HWIO_IC_INT_WEIGHT_INT_ENG_INM(m) \ + in_dword_masked(HWIO_IC_INT_WEIGHT_INT_ENG_ADDR, m) +#define HWIO_IC_INT_WEIGHT_INT_ENG_OUT(v) \ + out_dword(HWIO_IC_INT_WEIGHT_INT_ENG_ADDR,v) +#define HWIO_IC_INT_WEIGHT_INT_ENG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IC_INT_WEIGHT_INT_ENG_ADDR,m,v,HWIO_IC_INT_WEIGHT_INT_ENG_IN) +#define HWIO_IC_INT_WEIGHT_INT_ENG_INT_ENG_INT_WEIGHT_BMSK 0xf +#define HWIO_IC_INT_WEIGHT_INT_ENG_INT_ENG_INT_WEIGHT_SHFT 0x0 + +#define HWIO_IC_INT_WEIGHT_CSR_ADDR (GSI_REG_BASE + 0x0000010c) +#define HWIO_IC_INT_WEIGHT_CSR_PHYS (GSI_REG_BASE_PHYS + 0x0000010c) +#define HWIO_IC_INT_WEIGHT_CSR_OFFS (GSI_REG_BASE_OFFS + 0x0000010c) +#define HWIO_IC_INT_WEIGHT_CSR_RMSK 0xff +#define HWIO_IC_INT_WEIGHT_CSR_ATTR 0x3 +#define HWIO_IC_INT_WEIGHT_CSR_IN \ + in_dword_masked(HWIO_IC_INT_WEIGHT_CSR_ADDR, HWIO_IC_INT_WEIGHT_CSR_RMSK) +#define HWIO_IC_INT_WEIGHT_CSR_INM(m) \ + in_dword_masked(HWIO_IC_INT_WEIGHT_CSR_ADDR, m) +#define HWIO_IC_INT_WEIGHT_CSR_OUT(v) \ + out_dword(HWIO_IC_INT_WEIGHT_CSR_ADDR,v) +#define HWIO_IC_INT_WEIGHT_CSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IC_INT_WEIGHT_CSR_ADDR,m,v,HWIO_IC_INT_WEIGHT_CSR_IN) +#define HWIO_IC_INT_WEIGHT_CSR_EE_GENERIC_INT_WEIGHT_BMSK 0xf0 +#define HWIO_IC_INT_WEIGHT_CSR_EE_GENERIC_INT_WEIGHT_SHFT 0x4 +#define HWIO_IC_INT_WEIGHT_CSR_CH_CMD_INT_WEIGHT_BMSK 0xf +#define HWIO_IC_INT_WEIGHT_CSR_CH_CMD_INT_WEIGHT_SHFT 0x0 + +#define HWIO_IC_INT_WEIGHT_TLV_ENG_ADDR (GSI_REG_BASE + 0x00000110) +#define HWIO_IC_INT_WEIGHT_TLV_ENG_PHYS (GSI_REG_BASE_PHYS + 0x00000110) +#define HWIO_IC_INT_WEIGHT_TLV_ENG_OFFS (GSI_REG_BASE_OFFS + 0x00000110) +#define HWIO_IC_INT_WEIGHT_TLV_ENG_RMSK 0xffff +#define HWIO_IC_INT_WEIGHT_TLV_ENG_ATTR 0x3 +#define HWIO_IC_INT_WEIGHT_TLV_ENG_IN \ + in_dword_masked(HWIO_IC_INT_WEIGHT_TLV_ENG_ADDR, HWIO_IC_INT_WEIGHT_TLV_ENG_RMSK) +#define HWIO_IC_INT_WEIGHT_TLV_ENG_INM(m) \ + in_dword_masked(HWIO_IC_INT_WEIGHT_TLV_ENG_ADDR, m) +#define HWIO_IC_INT_WEIGHT_TLV_ENG_OUT(v) \ + out_dword(HWIO_IC_INT_WEIGHT_TLV_ENG_ADDR,v) +#define HWIO_IC_INT_WEIGHT_TLV_ENG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IC_INT_WEIGHT_TLV_ENG_ADDR,m,v,HWIO_IC_INT_WEIGHT_TLV_ENG_IN) +#define HWIO_IC_INT_WEIGHT_TLV_ENG_CH_NOT_FULL_INT_WEIGHT_BMSK 0xf000 +#define HWIO_IC_INT_WEIGHT_TLV_ENG_CH_NOT_FULL_INT_WEIGHT_SHFT 0xc +#define HWIO_IC_INT_WEIGHT_TLV_ENG_TLV_2_INT_WEIGHT_BMSK 0xf00 +#define HWIO_IC_INT_WEIGHT_TLV_ENG_TLV_2_INT_WEIGHT_SHFT 0x8 +#define HWIO_IC_INT_WEIGHT_TLV_ENG_TLV_1_INT_WEIGHT_BMSK 0xf0 +#define HWIO_IC_INT_WEIGHT_TLV_ENG_TLV_1_INT_WEIGHT_SHFT 0x4 +#define HWIO_IC_INT_WEIGHT_TLV_ENG_TLV_0_INT_WEIGHT_BMSK 0xf +#define HWIO_IC_INT_WEIGHT_TLV_ENG_TLV_0_INT_WEIGHT_SHFT 0x0 + +#define HWIO_IC_INT_WEIGHT_TIMER_ENG_ADDR (GSI_REG_BASE + 0x00000114) +#define HWIO_IC_INT_WEIGHT_TIMER_ENG_PHYS (GSI_REG_BASE_PHYS + 0x00000114) +#define HWIO_IC_INT_WEIGHT_TIMER_ENG_OFFS (GSI_REG_BASE_OFFS + 0x00000114) +#define HWIO_IC_INT_WEIGHT_TIMER_ENG_RMSK 0xf +#define HWIO_IC_INT_WEIGHT_TIMER_ENG_ATTR 0x3 +#define HWIO_IC_INT_WEIGHT_TIMER_ENG_IN \ + in_dword_masked(HWIO_IC_INT_WEIGHT_TIMER_ENG_ADDR, HWIO_IC_INT_WEIGHT_TIMER_ENG_RMSK) +#define HWIO_IC_INT_WEIGHT_TIMER_ENG_INM(m) \ + in_dword_masked(HWIO_IC_INT_WEIGHT_TIMER_ENG_ADDR, m) +#define HWIO_IC_INT_WEIGHT_TIMER_ENG_OUT(v) \ + out_dword(HWIO_IC_INT_WEIGHT_TIMER_ENG_ADDR,v) +#define HWIO_IC_INT_WEIGHT_TIMER_ENG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IC_INT_WEIGHT_TIMER_ENG_ADDR,m,v,HWIO_IC_INT_WEIGHT_TIMER_ENG_IN) +#define HWIO_IC_INT_WEIGHT_TIMER_ENG_TIMER_INT_WEIGHT_BMSK 0xf +#define HWIO_IC_INT_WEIGHT_TIMER_ENG_TIMER_INT_WEIGHT_SHFT 0x0 + +#define HWIO_IC_INT_WEIGHT_DB_ENG_ADDR (GSI_REG_BASE + 0x00000118) +#define HWIO_IC_INT_WEIGHT_DB_ENG_PHYS (GSI_REG_BASE_PHYS + 0x00000118) +#define HWIO_IC_INT_WEIGHT_DB_ENG_OFFS (GSI_REG_BASE_OFFS + 0x00000118) +#define HWIO_IC_INT_WEIGHT_DB_ENG_RMSK 0xf +#define HWIO_IC_INT_WEIGHT_DB_ENG_ATTR 0x3 +#define HWIO_IC_INT_WEIGHT_DB_ENG_IN \ + in_dword_masked(HWIO_IC_INT_WEIGHT_DB_ENG_ADDR, HWIO_IC_INT_WEIGHT_DB_ENG_RMSK) +#define HWIO_IC_INT_WEIGHT_DB_ENG_INM(m) \ + in_dword_masked(HWIO_IC_INT_WEIGHT_DB_ENG_ADDR, m) +#define HWIO_IC_INT_WEIGHT_DB_ENG_OUT(v) \ + out_dword(HWIO_IC_INT_WEIGHT_DB_ENG_ADDR,v) +#define HWIO_IC_INT_WEIGHT_DB_ENG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IC_INT_WEIGHT_DB_ENG_ADDR,m,v,HWIO_IC_INT_WEIGHT_DB_ENG_IN) +#define HWIO_IC_INT_WEIGHT_DB_ENG_NEW_DB_INT_WEIGHT_BMSK 0xf +#define HWIO_IC_INT_WEIGHT_DB_ENG_NEW_DB_INT_WEIGHT_SHFT 0x0 + +#define HWIO_IC_INT_WEIGHT_RD_WR_ENG_ADDR (GSI_REG_BASE + 0x0000011c) +#define HWIO_IC_INT_WEIGHT_RD_WR_ENG_PHYS (GSI_REG_BASE_PHYS + 0x0000011c) +#define HWIO_IC_INT_WEIGHT_RD_WR_ENG_OFFS (GSI_REG_BASE_OFFS + 0x0000011c) +#define HWIO_IC_INT_WEIGHT_RD_WR_ENG_RMSK 0xff +#define HWIO_IC_INT_WEIGHT_RD_WR_ENG_ATTR 0x3 +#define HWIO_IC_INT_WEIGHT_RD_WR_ENG_IN \ + in_dword_masked(HWIO_IC_INT_WEIGHT_RD_WR_ENG_ADDR, HWIO_IC_INT_WEIGHT_RD_WR_ENG_RMSK) +#define HWIO_IC_INT_WEIGHT_RD_WR_ENG_INM(m) \ + in_dword_masked(HWIO_IC_INT_WEIGHT_RD_WR_ENG_ADDR, m) +#define HWIO_IC_INT_WEIGHT_RD_WR_ENG_OUT(v) \ + out_dword(HWIO_IC_INT_WEIGHT_RD_WR_ENG_ADDR,v) +#define HWIO_IC_INT_WEIGHT_RD_WR_ENG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IC_INT_WEIGHT_RD_WR_ENG_ADDR,m,v,HWIO_IC_INT_WEIGHT_RD_WR_ENG_IN) +#define HWIO_IC_INT_WEIGHT_RD_WR_ENG_WRITE_INT_WEIGHT_BMSK 0xf0 +#define HWIO_IC_INT_WEIGHT_RD_WR_ENG_WRITE_INT_WEIGHT_SHFT 0x4 +#define HWIO_IC_INT_WEIGHT_RD_WR_ENG_READ_INT_WEIGHT_BMSK 0xf +#define HWIO_IC_INT_WEIGHT_RD_WR_ENG_READ_INT_WEIGHT_SHFT 0x0 + +#define HWIO_IC_INT_WEIGHT_UCONTROLLER_ENG_ADDR (GSI_REG_BASE + 0x00000120) +#define HWIO_IC_INT_WEIGHT_UCONTROLLER_ENG_PHYS (GSI_REG_BASE_PHYS + 0x00000120) +#define HWIO_IC_INT_WEIGHT_UCONTROLLER_ENG_OFFS (GSI_REG_BASE_OFFS + 0x00000120) +#define HWIO_IC_INT_WEIGHT_UCONTROLLER_ENG_RMSK 0xf +#define HWIO_IC_INT_WEIGHT_UCONTROLLER_ENG_ATTR 0x3 +#define HWIO_IC_INT_WEIGHT_UCONTROLLER_ENG_IN \ + in_dword_masked(HWIO_IC_INT_WEIGHT_UCONTROLLER_ENG_ADDR, HWIO_IC_INT_WEIGHT_UCONTROLLER_ENG_RMSK) +#define HWIO_IC_INT_WEIGHT_UCONTROLLER_ENG_INM(m) \ + in_dword_masked(HWIO_IC_INT_WEIGHT_UCONTROLLER_ENG_ADDR, m) +#define HWIO_IC_INT_WEIGHT_UCONTROLLER_ENG_OUT(v) \ + out_dword(HWIO_IC_INT_WEIGHT_UCONTROLLER_ENG_ADDR,v) +#define HWIO_IC_INT_WEIGHT_UCONTROLLER_ENG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IC_INT_WEIGHT_UCONTROLLER_ENG_ADDR,m,v,HWIO_IC_INT_WEIGHT_UCONTROLLER_ENG_IN) +#define HWIO_IC_INT_WEIGHT_UCONTROLLER_ENG_UCONTROLLER_GP_INT_WEIGHT_BMSK 0xf +#define HWIO_IC_INT_WEIGHT_UCONTROLLER_ENG_UCONTROLLER_GP_INT_WEIGHT_SHFT 0x0 + +#define HWIO_LOW_LATENCY_ARB_WEIGHT_ADDR (GSI_REG_BASE + 0x00000128) +#define HWIO_LOW_LATENCY_ARB_WEIGHT_PHYS (GSI_REG_BASE_PHYS + 0x00000128) +#define HWIO_LOW_LATENCY_ARB_WEIGHT_OFFS (GSI_REG_BASE_OFFS + 0x00000128) +#define HWIO_LOW_LATENCY_ARB_WEIGHT_RMSK 0x13f3f +#define HWIO_LOW_LATENCY_ARB_WEIGHT_ATTR 0x3 +#define HWIO_LOW_LATENCY_ARB_WEIGHT_IN \ + in_dword_masked(HWIO_LOW_LATENCY_ARB_WEIGHT_ADDR, HWIO_LOW_LATENCY_ARB_WEIGHT_RMSK) +#define HWIO_LOW_LATENCY_ARB_WEIGHT_INM(m) \ + in_dword_masked(HWIO_LOW_LATENCY_ARB_WEIGHT_ADDR, m) +#define HWIO_LOW_LATENCY_ARB_WEIGHT_OUT(v) \ + out_dword(HWIO_LOW_LATENCY_ARB_WEIGHT_ADDR,v) +#define HWIO_LOW_LATENCY_ARB_WEIGHT_OUTM(m,v) \ + out_dword_masked_ns(HWIO_LOW_LATENCY_ARB_WEIGHT_ADDR,m,v,HWIO_LOW_LATENCY_ARB_WEIGHT_IN) +#define HWIO_LOW_LATENCY_ARB_WEIGHT_LL_NON_LL_FIX_PRIORITY_BMSK 0x10000 +#define HWIO_LOW_LATENCY_ARB_WEIGHT_LL_NON_LL_FIX_PRIORITY_SHFT 0x10 +#define HWIO_LOW_LATENCY_ARB_WEIGHT_NON_LL_WEIGHT_BMSK 0x3f00 +#define HWIO_LOW_LATENCY_ARB_WEIGHT_NON_LL_WEIGHT_SHFT 0x8 +#define HWIO_LOW_LATENCY_ARB_WEIGHT_LL_WEIGHT_BMSK 0x3f +#define HWIO_LOW_LATENCY_ARB_WEIGHT_LL_WEIGHT_SHFT 0x0 + +#define HWIO_GSI_MANAGER_EE_QOS_n_ADDR(n) (GSI_REG_BASE + 0x00000300 + 0x4 * (n)) +#define HWIO_GSI_MANAGER_EE_QOS_n_PHYS(n) (GSI_REG_BASE_PHYS + 0x00000300 + 0x4 * (n)) +#define HWIO_GSI_MANAGER_EE_QOS_n_OFFS(n) (GSI_REG_BASE_OFFS + 0x00000300 + 0x4 * (n)) +#define HWIO_GSI_MANAGER_EE_QOS_n_RMSK 0xffff03 +#define HWIO_GSI_MANAGER_EE_QOS_n_MAXn 2 +#define HWIO_GSI_MANAGER_EE_QOS_n_ATTR 0x0 +#define HWIO_GSI_MANAGER_EE_QOS_n_INI(n) \ + in_dword_masked(HWIO_GSI_MANAGER_EE_QOS_n_ADDR(n), HWIO_GSI_MANAGER_EE_QOS_n_RMSK) +#define HWIO_GSI_MANAGER_EE_QOS_n_INMI(n,mask) \ + in_dword_masked(HWIO_GSI_MANAGER_EE_QOS_n_ADDR(n), mask) +#define HWIO_GSI_MANAGER_EE_QOS_n_OUTI(n,val) \ + out_dword(HWIO_GSI_MANAGER_EE_QOS_n_ADDR(n),val) +#define HWIO_GSI_MANAGER_EE_QOS_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_GSI_MANAGER_EE_QOS_n_ADDR(n),mask,val,HWIO_GSI_MANAGER_EE_QOS_n_INI(n)) +#define HWIO_GSI_MANAGER_EE_QOS_n_MAX_EV_ALLOC_BMSK 0xff0000 +#define HWIO_GSI_MANAGER_EE_QOS_n_MAX_EV_ALLOC_SHFT 0x10 +#define HWIO_GSI_MANAGER_EE_QOS_n_MAX_CH_ALLOC_BMSK 0xff00 +#define HWIO_GSI_MANAGER_EE_QOS_n_MAX_CH_ALLOC_SHFT 0x8 +#define HWIO_GSI_MANAGER_EE_QOS_n_EE_PRIO_BMSK 0x3 +#define HWIO_GSI_MANAGER_EE_QOS_n_EE_PRIO_SHFT 0x0 + +#define HWIO_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_ADDR (GSI_REG_BASE + 0x00000200) +#define HWIO_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_PHYS (GSI_REG_BASE_PHYS + 0x00000200) +#define HWIO_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_OFFS (GSI_REG_BASE_OFFS + 0x00000200) +#define HWIO_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_RMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_ATTR 0x3 +#define HWIO_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_IN \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_ADDR, HWIO_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_RMSK) +#define HWIO_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_ADDR, m) +#define HWIO_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_OUT(v) \ + out_dword(HWIO_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_ADDR,v) +#define HWIO_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_ADDR,m,v,HWIO_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_IN) +#define HWIO_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_ADDR (GSI_REG_BASE + 0x00000204) +#define HWIO_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_PHYS (GSI_REG_BASE_PHYS + 0x00000204) +#define HWIO_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_OFFS (GSI_REG_BASE_OFFS + 0x00000204) +#define HWIO_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_RMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_ATTR 0x3 +#define HWIO_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_IN \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_ADDR, HWIO_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_RMSK) +#define HWIO_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_ADDR, m) +#define HWIO_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_OUT(v) \ + out_dword(HWIO_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_ADDR,v) +#define HWIO_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_ADDR,m,v,HWIO_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_IN) +#define HWIO_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_ADDR (GSI_REG_BASE + 0x00000208) +#define HWIO_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_PHYS (GSI_REG_BASE_PHYS + 0x00000208) +#define HWIO_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_OFFS (GSI_REG_BASE_OFFS + 0x00000208) +#define HWIO_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_RMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_ATTR 0x3 +#define HWIO_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_IN \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_ADDR, HWIO_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_RMSK) +#define HWIO_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_ADDR, m) +#define HWIO_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_OUT(v) \ + out_dword(HWIO_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_ADDR,v) +#define HWIO_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_ADDR,m,v,HWIO_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_IN) +#define HWIO_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_ADDR (GSI_REG_BASE + 0x0000020c) +#define HWIO_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_PHYS (GSI_REG_BASE_PHYS + 0x0000020c) +#define HWIO_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_OFFS (GSI_REG_BASE_OFFS + 0x0000020c) +#define HWIO_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_RMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_ATTR 0x3 +#define HWIO_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_IN \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_ADDR, HWIO_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_RMSK) +#define HWIO_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_ADDR, m) +#define HWIO_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_OUT(v) \ + out_dword(HWIO_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_ADDR,v) +#define HWIO_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_ADDR,m,v,HWIO_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_IN) +#define HWIO_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_ADDR (GSI_REG_BASE + 0x00000240) +#define HWIO_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_PHYS (GSI_REG_BASE_PHYS + 0x00000240) +#define HWIO_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_OFFS (GSI_REG_BASE_OFFS + 0x00000240) +#define HWIO_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_RMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_ATTR 0x3 +#define HWIO_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_IN \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_ADDR, HWIO_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_RMSK) +#define HWIO_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_ADDR, m) +#define HWIO_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_OUT(v) \ + out_dword(HWIO_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_ADDR,v) +#define HWIO_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_ADDR,m,v,HWIO_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_IN) +#define HWIO_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_ADDR (GSI_REG_BASE + 0x00000244) +#define HWIO_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_PHYS (GSI_REG_BASE_PHYS + 0x00000244) +#define HWIO_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_OFFS (GSI_REG_BASE_OFFS + 0x00000244) +#define HWIO_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_RMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_ATTR 0x3 +#define HWIO_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_IN \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_ADDR, HWIO_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_RMSK) +#define HWIO_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_ADDR, m) +#define HWIO_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_OUT(v) \ + out_dword(HWIO_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_ADDR,v) +#define HWIO_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_ADDR,m,v,HWIO_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_IN) +#define HWIO_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_ADDR (GSI_REG_BASE + 0x00000210) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_PHYS (GSI_REG_BASE_PHYS + 0x00000210) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_OFFS (GSI_REG_BASE_OFFS + 0x00000210) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_RMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_ATTR 0x3 +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_IN \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_ADDR, HWIO_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_RMSK) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_ADDR, m) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_OUT(v) \ + out_dword(HWIO_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_ADDR,v) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_ADDR,m,v,HWIO_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_IN) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_ADDR (GSI_REG_BASE + 0x00000214) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_PHYS (GSI_REG_BASE_PHYS + 0x00000214) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_OFFS (GSI_REG_BASE_OFFS + 0x00000214) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_RMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_ATTR 0x3 +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_IN \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_ADDR, HWIO_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_RMSK) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_ADDR, m) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_OUT(v) \ + out_dword(HWIO_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_ADDR,v) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_ADDR,m,v,HWIO_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_IN) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_ADDR (GSI_REG_BASE + 0x00000218) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_PHYS (GSI_REG_BASE_PHYS + 0x00000218) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_OFFS (GSI_REG_BASE_OFFS + 0x00000218) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_RMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_ATTR 0x3 +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_IN \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_ADDR, HWIO_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_RMSK) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_ADDR, m) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_OUT(v) \ + out_dword(HWIO_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_ADDR,v) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_ADDR,m,v,HWIO_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_IN) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_ADDR (GSI_REG_BASE + 0x0000021c) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_PHYS (GSI_REG_BASE_PHYS + 0x0000021c) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_OFFS (GSI_REG_BASE_OFFS + 0x0000021c) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_RMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_ATTR 0x3 +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_IN \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_ADDR, HWIO_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_RMSK) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_ADDR, m) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_OUT(v) \ + out_dword(HWIO_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_ADDR,v) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_ADDR,m,v,HWIO_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_IN) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_ADDR (GSI_REG_BASE + 0x00000254) +#define HWIO_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_PHYS (GSI_REG_BASE_PHYS + 0x00000254) +#define HWIO_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_OFFS (GSI_REG_BASE_OFFS + 0x00000254) +#define HWIO_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_RMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_ATTR 0x3 +#define HWIO_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_IN \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_ADDR, HWIO_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_RMSK) +#define HWIO_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_ADDR, m) +#define HWIO_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_OUT(v) \ + out_dword(HWIO_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_ADDR,v) +#define HWIO_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_ADDR,m,v,HWIO_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_IN) +#define HWIO_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_ADDR (GSI_REG_BASE + 0x00000258) +#define HWIO_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_PHYS (GSI_REG_BASE_PHYS + 0x00000258) +#define HWIO_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_OFFS (GSI_REG_BASE_OFFS + 0x00000258) +#define HWIO_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_RMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_ATTR 0x3 +#define HWIO_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_IN \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_ADDR, HWIO_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_RMSK) +#define HWIO_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_ADDR, m) +#define HWIO_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_OUT(v) \ + out_dword(HWIO_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_ADDR,v) +#define HWIO_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_ADDR,m,v,HWIO_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_IN) +#define HWIO_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_ADDR (GSI_REG_BASE + 0x0000025c) +#define HWIO_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_PHYS (GSI_REG_BASE_PHYS + 0x0000025c) +#define HWIO_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_OFFS (GSI_REG_BASE_OFFS + 0x0000025c) +#define HWIO_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_RMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_ATTR 0x3 +#define HWIO_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_IN \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_ADDR, HWIO_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_RMSK) +#define HWIO_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_ADDR, m) +#define HWIO_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_OUT(v) \ + out_dword(HWIO_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_ADDR,v) +#define HWIO_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_ADDR,m,v,HWIO_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_IN) +#define HWIO_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_ADDR (GSI_REG_BASE + 0x00000260) +#define HWIO_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_PHYS (GSI_REG_BASE_PHYS + 0x00000260) +#define HWIO_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_OFFS (GSI_REG_BASE_OFFS + 0x00000260) +#define HWIO_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_RMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_ATTR 0x3 +#define HWIO_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_IN \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_ADDR, HWIO_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_RMSK) +#define HWIO_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_ADDR, m) +#define HWIO_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_OUT(v) \ + out_dword(HWIO_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_ADDR,v) +#define HWIO_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_ADDR,m,v,HWIO_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_IN) +#define HWIO_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_ADDR (GSI_REG_BASE + 0x00000264) +#define HWIO_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_PHYS (GSI_REG_BASE_PHYS + 0x00000264) +#define HWIO_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_OFFS (GSI_REG_BASE_OFFS + 0x00000264) +#define HWIO_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_RMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_ATTR 0x3 +#define HWIO_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_IN \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_ADDR, HWIO_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_RMSK) +#define HWIO_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_ADDR, m) +#define HWIO_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_OUT(v) \ + out_dword(HWIO_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_ADDR,v) +#define HWIO_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_ADDR,m,v,HWIO_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_IN) +#define HWIO_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_ADDR (GSI_REG_BASE + 0x00000268) +#define HWIO_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_PHYS (GSI_REG_BASE_PHYS + 0x00000268) +#define HWIO_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_OFFS (GSI_REG_BASE_OFFS + 0x00000268) +#define HWIO_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_RMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_ATTR 0x3 +#define HWIO_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_IN \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_ADDR, HWIO_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_RMSK) +#define HWIO_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_ADDR, m) +#define HWIO_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_OUT(v) \ + out_dword(HWIO_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_ADDR,v) +#define HWIO_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_ADDR,m,v,HWIO_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_IN) +#define HWIO_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_IRAM_PTR_CH_CMD_ADDR (GSI_REG_BASE + 0x00000400) +#define HWIO_GSI_IRAM_PTR_CH_CMD_PHYS (GSI_REG_BASE_PHYS + 0x00000400) +#define HWIO_GSI_IRAM_PTR_CH_CMD_OFFS (GSI_REG_BASE_OFFS + 0x00000400) +#define HWIO_GSI_IRAM_PTR_CH_CMD_RMSK 0xfff +#define HWIO_GSI_IRAM_PTR_CH_CMD_ATTR 0x3 +#define HWIO_GSI_IRAM_PTR_CH_CMD_IN \ + in_dword_masked(HWIO_GSI_IRAM_PTR_CH_CMD_ADDR, HWIO_GSI_IRAM_PTR_CH_CMD_RMSK) +#define HWIO_GSI_IRAM_PTR_CH_CMD_INM(m) \ + in_dword_masked(HWIO_GSI_IRAM_PTR_CH_CMD_ADDR, m) +#define HWIO_GSI_IRAM_PTR_CH_CMD_OUT(v) \ + out_dword(HWIO_GSI_IRAM_PTR_CH_CMD_ADDR,v) +#define HWIO_GSI_IRAM_PTR_CH_CMD_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_IRAM_PTR_CH_CMD_ADDR,m,v,HWIO_GSI_IRAM_PTR_CH_CMD_IN) +#define HWIO_GSI_IRAM_PTR_CH_CMD_IRAM_PTR_BMSK 0xfff +#define HWIO_GSI_IRAM_PTR_CH_CMD_IRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_IRAM_PTR_EE_GENERIC_CMD_ADDR (GSI_REG_BASE + 0x00000404) +#define HWIO_GSI_IRAM_PTR_EE_GENERIC_CMD_PHYS (GSI_REG_BASE_PHYS + 0x00000404) +#define HWIO_GSI_IRAM_PTR_EE_GENERIC_CMD_OFFS (GSI_REG_BASE_OFFS + 0x00000404) +#define HWIO_GSI_IRAM_PTR_EE_GENERIC_CMD_RMSK 0xfff +#define HWIO_GSI_IRAM_PTR_EE_GENERIC_CMD_ATTR 0x3 +#define HWIO_GSI_IRAM_PTR_EE_GENERIC_CMD_IN \ + in_dword_masked(HWIO_GSI_IRAM_PTR_EE_GENERIC_CMD_ADDR, HWIO_GSI_IRAM_PTR_EE_GENERIC_CMD_RMSK) +#define HWIO_GSI_IRAM_PTR_EE_GENERIC_CMD_INM(m) \ + in_dword_masked(HWIO_GSI_IRAM_PTR_EE_GENERIC_CMD_ADDR, m) +#define HWIO_GSI_IRAM_PTR_EE_GENERIC_CMD_OUT(v) \ + out_dword(HWIO_GSI_IRAM_PTR_EE_GENERIC_CMD_ADDR,v) +#define HWIO_GSI_IRAM_PTR_EE_GENERIC_CMD_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_IRAM_PTR_EE_GENERIC_CMD_ADDR,m,v,HWIO_GSI_IRAM_PTR_EE_GENERIC_CMD_IN) +#define HWIO_GSI_IRAM_PTR_EE_GENERIC_CMD_IRAM_PTR_BMSK 0xfff +#define HWIO_GSI_IRAM_PTR_EE_GENERIC_CMD_IRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_IRAM_PTR_TLV_CH_NOT_FULL_ADDR (GSI_REG_BASE + 0x00000408) +#define HWIO_GSI_IRAM_PTR_TLV_CH_NOT_FULL_PHYS (GSI_REG_BASE_PHYS + 0x00000408) +#define HWIO_GSI_IRAM_PTR_TLV_CH_NOT_FULL_OFFS (GSI_REG_BASE_OFFS + 0x00000408) +#define HWIO_GSI_IRAM_PTR_TLV_CH_NOT_FULL_RMSK 0xfff +#define HWIO_GSI_IRAM_PTR_TLV_CH_NOT_FULL_ATTR 0x3 +#define HWIO_GSI_IRAM_PTR_TLV_CH_NOT_FULL_IN \ + in_dword_masked(HWIO_GSI_IRAM_PTR_TLV_CH_NOT_FULL_ADDR, HWIO_GSI_IRAM_PTR_TLV_CH_NOT_FULL_RMSK) +#define HWIO_GSI_IRAM_PTR_TLV_CH_NOT_FULL_INM(m) \ + in_dword_masked(HWIO_GSI_IRAM_PTR_TLV_CH_NOT_FULL_ADDR, m) +#define HWIO_GSI_IRAM_PTR_TLV_CH_NOT_FULL_OUT(v) \ + out_dword(HWIO_GSI_IRAM_PTR_TLV_CH_NOT_FULL_ADDR,v) +#define HWIO_GSI_IRAM_PTR_TLV_CH_NOT_FULL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_IRAM_PTR_TLV_CH_NOT_FULL_ADDR,m,v,HWIO_GSI_IRAM_PTR_TLV_CH_NOT_FULL_IN) +#define HWIO_GSI_IRAM_PTR_TLV_CH_NOT_FULL_IRAM_PTR_BMSK 0xfff +#define HWIO_GSI_IRAM_PTR_TLV_CH_NOT_FULL_IRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_IRAM_PTR_MSI_DB_ADDR (GSI_REG_BASE + 0x00000414) +#define HWIO_GSI_IRAM_PTR_MSI_DB_PHYS (GSI_REG_BASE_PHYS + 0x00000414) +#define HWIO_GSI_IRAM_PTR_MSI_DB_OFFS (GSI_REG_BASE_OFFS + 0x00000414) +#define HWIO_GSI_IRAM_PTR_MSI_DB_RMSK 0xfff +#define HWIO_GSI_IRAM_PTR_MSI_DB_ATTR 0x3 +#define HWIO_GSI_IRAM_PTR_MSI_DB_IN \ + in_dword_masked(HWIO_GSI_IRAM_PTR_MSI_DB_ADDR, HWIO_GSI_IRAM_PTR_MSI_DB_RMSK) +#define HWIO_GSI_IRAM_PTR_MSI_DB_INM(m) \ + in_dword_masked(HWIO_GSI_IRAM_PTR_MSI_DB_ADDR, m) +#define HWIO_GSI_IRAM_PTR_MSI_DB_OUT(v) \ + out_dword(HWIO_GSI_IRAM_PTR_MSI_DB_ADDR,v) +#define HWIO_GSI_IRAM_PTR_MSI_DB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_IRAM_PTR_MSI_DB_ADDR,m,v,HWIO_GSI_IRAM_PTR_MSI_DB_IN) +#define HWIO_GSI_IRAM_PTR_MSI_DB_IRAM_PTR_BMSK 0xfff +#define HWIO_GSI_IRAM_PTR_MSI_DB_IRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_IRAM_PTR_CH_DB_ADDR (GSI_REG_BASE + 0x00000418) +#define HWIO_GSI_IRAM_PTR_CH_DB_PHYS (GSI_REG_BASE_PHYS + 0x00000418) +#define HWIO_GSI_IRAM_PTR_CH_DB_OFFS (GSI_REG_BASE_OFFS + 0x00000418) +#define HWIO_GSI_IRAM_PTR_CH_DB_RMSK 0xfff +#define HWIO_GSI_IRAM_PTR_CH_DB_ATTR 0x3 +#define HWIO_GSI_IRAM_PTR_CH_DB_IN \ + in_dword_masked(HWIO_GSI_IRAM_PTR_CH_DB_ADDR, HWIO_GSI_IRAM_PTR_CH_DB_RMSK) +#define HWIO_GSI_IRAM_PTR_CH_DB_INM(m) \ + in_dword_masked(HWIO_GSI_IRAM_PTR_CH_DB_ADDR, m) +#define HWIO_GSI_IRAM_PTR_CH_DB_OUT(v) \ + out_dword(HWIO_GSI_IRAM_PTR_CH_DB_ADDR,v) +#define HWIO_GSI_IRAM_PTR_CH_DB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_IRAM_PTR_CH_DB_ADDR,m,v,HWIO_GSI_IRAM_PTR_CH_DB_IN) +#define HWIO_GSI_IRAM_PTR_CH_DB_IRAM_PTR_BMSK 0xfff +#define HWIO_GSI_IRAM_PTR_CH_DB_IRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_IRAM_PTR_EV_DB_ADDR (GSI_REG_BASE + 0x0000041c) +#define HWIO_GSI_IRAM_PTR_EV_DB_PHYS (GSI_REG_BASE_PHYS + 0x0000041c) +#define HWIO_GSI_IRAM_PTR_EV_DB_OFFS (GSI_REG_BASE_OFFS + 0x0000041c) +#define HWIO_GSI_IRAM_PTR_EV_DB_RMSK 0xfff +#define HWIO_GSI_IRAM_PTR_EV_DB_ATTR 0x3 +#define HWIO_GSI_IRAM_PTR_EV_DB_IN \ + in_dword_masked(HWIO_GSI_IRAM_PTR_EV_DB_ADDR, HWIO_GSI_IRAM_PTR_EV_DB_RMSK) +#define HWIO_GSI_IRAM_PTR_EV_DB_INM(m) \ + in_dword_masked(HWIO_GSI_IRAM_PTR_EV_DB_ADDR, m) +#define HWIO_GSI_IRAM_PTR_EV_DB_OUT(v) \ + out_dword(HWIO_GSI_IRAM_PTR_EV_DB_ADDR,v) +#define HWIO_GSI_IRAM_PTR_EV_DB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_IRAM_PTR_EV_DB_ADDR,m,v,HWIO_GSI_IRAM_PTR_EV_DB_IN) +#define HWIO_GSI_IRAM_PTR_EV_DB_IRAM_PTR_BMSK 0xfff +#define HWIO_GSI_IRAM_PTR_EV_DB_IRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_IRAM_PTR_NEW_RE_ADDR (GSI_REG_BASE + 0x00000420) +#define HWIO_GSI_IRAM_PTR_NEW_RE_PHYS (GSI_REG_BASE_PHYS + 0x00000420) +#define HWIO_GSI_IRAM_PTR_NEW_RE_OFFS (GSI_REG_BASE_OFFS + 0x00000420) +#define HWIO_GSI_IRAM_PTR_NEW_RE_RMSK 0xfff +#define HWIO_GSI_IRAM_PTR_NEW_RE_ATTR 0x3 +#define HWIO_GSI_IRAM_PTR_NEW_RE_IN \ + in_dword_masked(HWIO_GSI_IRAM_PTR_NEW_RE_ADDR, HWIO_GSI_IRAM_PTR_NEW_RE_RMSK) +#define HWIO_GSI_IRAM_PTR_NEW_RE_INM(m) \ + in_dword_masked(HWIO_GSI_IRAM_PTR_NEW_RE_ADDR, m) +#define HWIO_GSI_IRAM_PTR_NEW_RE_OUT(v) \ + out_dword(HWIO_GSI_IRAM_PTR_NEW_RE_ADDR,v) +#define HWIO_GSI_IRAM_PTR_NEW_RE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_IRAM_PTR_NEW_RE_ADDR,m,v,HWIO_GSI_IRAM_PTR_NEW_RE_IN) +#define HWIO_GSI_IRAM_PTR_NEW_RE_IRAM_PTR_BMSK 0xfff +#define HWIO_GSI_IRAM_PTR_NEW_RE_IRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_IRAM_PTR_CH_DIS_COMP_ADDR (GSI_REG_BASE + 0x00000424) +#define HWIO_GSI_IRAM_PTR_CH_DIS_COMP_PHYS (GSI_REG_BASE_PHYS + 0x00000424) +#define HWIO_GSI_IRAM_PTR_CH_DIS_COMP_OFFS (GSI_REG_BASE_OFFS + 0x00000424) +#define HWIO_GSI_IRAM_PTR_CH_DIS_COMP_RMSK 0xfff +#define HWIO_GSI_IRAM_PTR_CH_DIS_COMP_ATTR 0x3 +#define HWIO_GSI_IRAM_PTR_CH_DIS_COMP_IN \ + in_dword_masked(HWIO_GSI_IRAM_PTR_CH_DIS_COMP_ADDR, HWIO_GSI_IRAM_PTR_CH_DIS_COMP_RMSK) +#define HWIO_GSI_IRAM_PTR_CH_DIS_COMP_INM(m) \ + in_dword_masked(HWIO_GSI_IRAM_PTR_CH_DIS_COMP_ADDR, m) +#define HWIO_GSI_IRAM_PTR_CH_DIS_COMP_OUT(v) \ + out_dword(HWIO_GSI_IRAM_PTR_CH_DIS_COMP_ADDR,v) +#define HWIO_GSI_IRAM_PTR_CH_DIS_COMP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_IRAM_PTR_CH_DIS_COMP_ADDR,m,v,HWIO_GSI_IRAM_PTR_CH_DIS_COMP_IN) +#define HWIO_GSI_IRAM_PTR_CH_DIS_COMP_IRAM_PTR_BMSK 0xfff +#define HWIO_GSI_IRAM_PTR_CH_DIS_COMP_IRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_IRAM_PTR_CH_EMPTY_ADDR (GSI_REG_BASE + 0x00000428) +#define HWIO_GSI_IRAM_PTR_CH_EMPTY_PHYS (GSI_REG_BASE_PHYS + 0x00000428) +#define HWIO_GSI_IRAM_PTR_CH_EMPTY_OFFS (GSI_REG_BASE_OFFS + 0x00000428) +#define HWIO_GSI_IRAM_PTR_CH_EMPTY_RMSK 0xfff +#define HWIO_GSI_IRAM_PTR_CH_EMPTY_ATTR 0x3 +#define HWIO_GSI_IRAM_PTR_CH_EMPTY_IN \ + in_dword_masked(HWIO_GSI_IRAM_PTR_CH_EMPTY_ADDR, HWIO_GSI_IRAM_PTR_CH_EMPTY_RMSK) +#define HWIO_GSI_IRAM_PTR_CH_EMPTY_INM(m) \ + in_dword_masked(HWIO_GSI_IRAM_PTR_CH_EMPTY_ADDR, m) +#define HWIO_GSI_IRAM_PTR_CH_EMPTY_OUT(v) \ + out_dword(HWIO_GSI_IRAM_PTR_CH_EMPTY_ADDR,v) +#define HWIO_GSI_IRAM_PTR_CH_EMPTY_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_IRAM_PTR_CH_EMPTY_ADDR,m,v,HWIO_GSI_IRAM_PTR_CH_EMPTY_IN) +#define HWIO_GSI_IRAM_PTR_CH_EMPTY_IRAM_PTR_BMSK 0xfff +#define HWIO_GSI_IRAM_PTR_CH_EMPTY_IRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_IRAM_PTR_EVENT_GEN_COMP_ADDR (GSI_REG_BASE + 0x0000042c) +#define HWIO_GSI_IRAM_PTR_EVENT_GEN_COMP_PHYS (GSI_REG_BASE_PHYS + 0x0000042c) +#define HWIO_GSI_IRAM_PTR_EVENT_GEN_COMP_OFFS (GSI_REG_BASE_OFFS + 0x0000042c) +#define HWIO_GSI_IRAM_PTR_EVENT_GEN_COMP_RMSK 0xfff +#define HWIO_GSI_IRAM_PTR_EVENT_GEN_COMP_ATTR 0x3 +#define HWIO_GSI_IRAM_PTR_EVENT_GEN_COMP_IN \ + in_dword_masked(HWIO_GSI_IRAM_PTR_EVENT_GEN_COMP_ADDR, HWIO_GSI_IRAM_PTR_EVENT_GEN_COMP_RMSK) +#define HWIO_GSI_IRAM_PTR_EVENT_GEN_COMP_INM(m) \ + in_dword_masked(HWIO_GSI_IRAM_PTR_EVENT_GEN_COMP_ADDR, m) +#define HWIO_GSI_IRAM_PTR_EVENT_GEN_COMP_OUT(v) \ + out_dword(HWIO_GSI_IRAM_PTR_EVENT_GEN_COMP_ADDR,v) +#define HWIO_GSI_IRAM_PTR_EVENT_GEN_COMP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_IRAM_PTR_EVENT_GEN_COMP_ADDR,m,v,HWIO_GSI_IRAM_PTR_EVENT_GEN_COMP_IN) +#define HWIO_GSI_IRAM_PTR_EVENT_GEN_COMP_IRAM_PTR_BMSK 0xfff +#define HWIO_GSI_IRAM_PTR_EVENT_GEN_COMP_IRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_ADDR (GSI_REG_BASE + 0x00000430) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_PHYS (GSI_REG_BASE_PHYS + 0x00000430) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_OFFS (GSI_REG_BASE_OFFS + 0x00000430) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_RMSK 0xfff +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_ATTR 0x3 +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_IN \ + in_dword_masked(HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_ADDR, HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_RMSK) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_INM(m) \ + in_dword_masked(HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_ADDR, m) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_OUT(v) \ + out_dword(HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_ADDR,v) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_ADDR,m,v,HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_IN) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_IRAM_PTR_BMSK 0xfff +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_IRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_ADDR (GSI_REG_BASE + 0x00000434) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_PHYS (GSI_REG_BASE_PHYS + 0x00000434) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_OFFS (GSI_REG_BASE_OFFS + 0x00000434) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_RMSK 0xfff +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_ATTR 0x3 +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_IN \ + in_dword_masked(HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_ADDR, HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_RMSK) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_INM(m) \ + in_dword_masked(HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_ADDR, m) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_OUT(v) \ + out_dword(HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_ADDR,v) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_ADDR,m,v,HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_IN) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_IRAM_PTR_BMSK 0xfff +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_IRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_ADDR (GSI_REG_BASE + 0x00000438) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_PHYS (GSI_REG_BASE_PHYS + 0x00000438) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_OFFS (GSI_REG_BASE_OFFS + 0x00000438) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_RMSK 0xfff +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_ATTR 0x3 +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_IN \ + in_dword_masked(HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_ADDR, HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_RMSK) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_INM(m) \ + in_dword_masked(HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_ADDR, m) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_OUT(v) \ + out_dword(HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_ADDR,v) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_ADDR,m,v,HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_IN) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_IRAM_PTR_BMSK 0xfff +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_IRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_IRAM_PTR_TIMER_EXPIRED_ADDR (GSI_REG_BASE + 0x0000043c) +#define HWIO_GSI_IRAM_PTR_TIMER_EXPIRED_PHYS (GSI_REG_BASE_PHYS + 0x0000043c) +#define HWIO_GSI_IRAM_PTR_TIMER_EXPIRED_OFFS (GSI_REG_BASE_OFFS + 0x0000043c) +#define HWIO_GSI_IRAM_PTR_TIMER_EXPIRED_RMSK 0xfff +#define HWIO_GSI_IRAM_PTR_TIMER_EXPIRED_ATTR 0x3 +#define HWIO_GSI_IRAM_PTR_TIMER_EXPIRED_IN \ + in_dword_masked(HWIO_GSI_IRAM_PTR_TIMER_EXPIRED_ADDR, HWIO_GSI_IRAM_PTR_TIMER_EXPIRED_RMSK) +#define HWIO_GSI_IRAM_PTR_TIMER_EXPIRED_INM(m) \ + in_dword_masked(HWIO_GSI_IRAM_PTR_TIMER_EXPIRED_ADDR, m) +#define HWIO_GSI_IRAM_PTR_TIMER_EXPIRED_OUT(v) \ + out_dword(HWIO_GSI_IRAM_PTR_TIMER_EXPIRED_ADDR,v) +#define HWIO_GSI_IRAM_PTR_TIMER_EXPIRED_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_IRAM_PTR_TIMER_EXPIRED_ADDR,m,v,HWIO_GSI_IRAM_PTR_TIMER_EXPIRED_IN) +#define HWIO_GSI_IRAM_PTR_TIMER_EXPIRED_IRAM_PTR_BMSK 0xfff +#define HWIO_GSI_IRAM_PTR_TIMER_EXPIRED_IRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_IRAM_PTR_WRITE_ENG_COMP_ADDR (GSI_REG_BASE + 0x00000440) +#define HWIO_GSI_IRAM_PTR_WRITE_ENG_COMP_PHYS (GSI_REG_BASE_PHYS + 0x00000440) +#define HWIO_GSI_IRAM_PTR_WRITE_ENG_COMP_OFFS (GSI_REG_BASE_OFFS + 0x00000440) +#define HWIO_GSI_IRAM_PTR_WRITE_ENG_COMP_RMSK 0xfff +#define HWIO_GSI_IRAM_PTR_WRITE_ENG_COMP_ATTR 0x3 +#define HWIO_GSI_IRAM_PTR_WRITE_ENG_COMP_IN \ + in_dword_masked(HWIO_GSI_IRAM_PTR_WRITE_ENG_COMP_ADDR, HWIO_GSI_IRAM_PTR_WRITE_ENG_COMP_RMSK) +#define HWIO_GSI_IRAM_PTR_WRITE_ENG_COMP_INM(m) \ + in_dword_masked(HWIO_GSI_IRAM_PTR_WRITE_ENG_COMP_ADDR, m) +#define HWIO_GSI_IRAM_PTR_WRITE_ENG_COMP_OUT(v) \ + out_dword(HWIO_GSI_IRAM_PTR_WRITE_ENG_COMP_ADDR,v) +#define HWIO_GSI_IRAM_PTR_WRITE_ENG_COMP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_IRAM_PTR_WRITE_ENG_COMP_ADDR,m,v,HWIO_GSI_IRAM_PTR_WRITE_ENG_COMP_IN) +#define HWIO_GSI_IRAM_PTR_WRITE_ENG_COMP_IRAM_PTR_BMSK 0xfff +#define HWIO_GSI_IRAM_PTR_WRITE_ENG_COMP_IRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_IRAM_PTR_READ_ENG_COMP_ADDR (GSI_REG_BASE + 0x00000444) +#define HWIO_GSI_IRAM_PTR_READ_ENG_COMP_PHYS (GSI_REG_BASE_PHYS + 0x00000444) +#define HWIO_GSI_IRAM_PTR_READ_ENG_COMP_OFFS (GSI_REG_BASE_OFFS + 0x00000444) +#define HWIO_GSI_IRAM_PTR_READ_ENG_COMP_RMSK 0xfff +#define HWIO_GSI_IRAM_PTR_READ_ENG_COMP_ATTR 0x3 +#define HWIO_GSI_IRAM_PTR_READ_ENG_COMP_IN \ + in_dword_masked(HWIO_GSI_IRAM_PTR_READ_ENG_COMP_ADDR, HWIO_GSI_IRAM_PTR_READ_ENG_COMP_RMSK) +#define HWIO_GSI_IRAM_PTR_READ_ENG_COMP_INM(m) \ + in_dword_masked(HWIO_GSI_IRAM_PTR_READ_ENG_COMP_ADDR, m) +#define HWIO_GSI_IRAM_PTR_READ_ENG_COMP_OUT(v) \ + out_dword(HWIO_GSI_IRAM_PTR_READ_ENG_COMP_ADDR,v) +#define HWIO_GSI_IRAM_PTR_READ_ENG_COMP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_IRAM_PTR_READ_ENG_COMP_ADDR,m,v,HWIO_GSI_IRAM_PTR_READ_ENG_COMP_IN) +#define HWIO_GSI_IRAM_PTR_READ_ENG_COMP_IRAM_PTR_BMSK 0xfff +#define HWIO_GSI_IRAM_PTR_READ_ENG_COMP_IRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_IRAM_PTR_UC_GP_INT_ADDR (GSI_REG_BASE + 0x00000448) +#define HWIO_GSI_IRAM_PTR_UC_GP_INT_PHYS (GSI_REG_BASE_PHYS + 0x00000448) +#define HWIO_GSI_IRAM_PTR_UC_GP_INT_OFFS (GSI_REG_BASE_OFFS + 0x00000448) +#define HWIO_GSI_IRAM_PTR_UC_GP_INT_RMSK 0xfff +#define HWIO_GSI_IRAM_PTR_UC_GP_INT_ATTR 0x3 +#define HWIO_GSI_IRAM_PTR_UC_GP_INT_IN \ + in_dword_masked(HWIO_GSI_IRAM_PTR_UC_GP_INT_ADDR, HWIO_GSI_IRAM_PTR_UC_GP_INT_RMSK) +#define HWIO_GSI_IRAM_PTR_UC_GP_INT_INM(m) \ + in_dword_masked(HWIO_GSI_IRAM_PTR_UC_GP_INT_ADDR, m) +#define HWIO_GSI_IRAM_PTR_UC_GP_INT_OUT(v) \ + out_dword(HWIO_GSI_IRAM_PTR_UC_GP_INT_ADDR,v) +#define HWIO_GSI_IRAM_PTR_UC_GP_INT_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_IRAM_PTR_UC_GP_INT_ADDR,m,v,HWIO_GSI_IRAM_PTR_UC_GP_INT_IN) +#define HWIO_GSI_IRAM_PTR_UC_GP_INT_IRAM_PTR_BMSK 0xfff +#define HWIO_GSI_IRAM_PTR_UC_GP_INT_IRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_IRAM_PTR_INT_MOD_STOPED_ADDR (GSI_REG_BASE + 0x0000044c) +#define HWIO_GSI_IRAM_PTR_INT_MOD_STOPED_PHYS (GSI_REG_BASE_PHYS + 0x0000044c) +#define HWIO_GSI_IRAM_PTR_INT_MOD_STOPED_OFFS (GSI_REG_BASE_OFFS + 0x0000044c) +#define HWIO_GSI_IRAM_PTR_INT_MOD_STOPED_RMSK 0xfff +#define HWIO_GSI_IRAM_PTR_INT_MOD_STOPED_ATTR 0x3 +#define HWIO_GSI_IRAM_PTR_INT_MOD_STOPED_IN \ + in_dword_masked(HWIO_GSI_IRAM_PTR_INT_MOD_STOPED_ADDR, HWIO_GSI_IRAM_PTR_INT_MOD_STOPED_RMSK) +#define HWIO_GSI_IRAM_PTR_INT_MOD_STOPED_INM(m) \ + in_dword_masked(HWIO_GSI_IRAM_PTR_INT_MOD_STOPED_ADDR, m) +#define HWIO_GSI_IRAM_PTR_INT_MOD_STOPED_OUT(v) \ + out_dword(HWIO_GSI_IRAM_PTR_INT_MOD_STOPED_ADDR,v) +#define HWIO_GSI_IRAM_PTR_INT_MOD_STOPED_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_IRAM_PTR_INT_MOD_STOPED_ADDR,m,v,HWIO_GSI_IRAM_PTR_INT_MOD_STOPED_IN) +#define HWIO_GSI_IRAM_PTR_INT_MOD_STOPED_IRAM_PTR_BMSK 0xfff +#define HWIO_GSI_IRAM_PTR_INT_MOD_STOPED_IRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_IRAM_PTR_INT_NOTIFY_MCS_ADDR (GSI_REG_BASE + 0x00000470) +#define HWIO_GSI_IRAM_PTR_INT_NOTIFY_MCS_PHYS (GSI_REG_BASE_PHYS + 0x00000470) +#define HWIO_GSI_IRAM_PTR_INT_NOTIFY_MCS_OFFS (GSI_REG_BASE_OFFS + 0x00000470) +#define HWIO_GSI_IRAM_PTR_INT_NOTIFY_MCS_RMSK 0xfff +#define HWIO_GSI_IRAM_PTR_INT_NOTIFY_MCS_ATTR 0x3 +#define HWIO_GSI_IRAM_PTR_INT_NOTIFY_MCS_IN \ + in_dword_masked(HWIO_GSI_IRAM_PTR_INT_NOTIFY_MCS_ADDR, HWIO_GSI_IRAM_PTR_INT_NOTIFY_MCS_RMSK) +#define HWIO_GSI_IRAM_PTR_INT_NOTIFY_MCS_INM(m) \ + in_dword_masked(HWIO_GSI_IRAM_PTR_INT_NOTIFY_MCS_ADDR, m) +#define HWIO_GSI_IRAM_PTR_INT_NOTIFY_MCS_OUT(v) \ + out_dword(HWIO_GSI_IRAM_PTR_INT_NOTIFY_MCS_ADDR,v) +#define HWIO_GSI_IRAM_PTR_INT_NOTIFY_MCS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_IRAM_PTR_INT_NOTIFY_MCS_ADDR,m,v,HWIO_GSI_IRAM_PTR_INT_NOTIFY_MCS_IN) +#define HWIO_GSI_IRAM_PTR_INT_NOTIFY_MCS_IRAM_PTR_BMSK 0xfff +#define HWIO_GSI_IRAM_PTR_INT_NOTIFY_MCS_IRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_INST_RAM_n_ADDR(n) (GSI_REG_BASE + 0x000a4000 + 0x4 * (n)) +#define HWIO_GSI_INST_RAM_n_PHYS(n) (GSI_REG_BASE_PHYS + 0x000a4000 + 0x4 * (n)) +#define HWIO_GSI_INST_RAM_n_OFFS(n) (GSI_REG_BASE_OFFS + 0x000a4000 + 0x4 * (n)) +#define HWIO_GSI_INST_RAM_n_RMSK 0xffffffff +#define HWIO_GSI_INST_RAM_n_MAXn 8257 +#define HWIO_GSI_INST_RAM_n_ATTR 0x3 +#define HWIO_GSI_INST_RAM_n_INI(n) \ + in_dword_masked(HWIO_GSI_INST_RAM_n_ADDR(n), HWIO_GSI_INST_RAM_n_RMSK) +#define HWIO_GSI_INST_RAM_n_INMI(n,mask) \ + in_dword_masked(HWIO_GSI_INST_RAM_n_ADDR(n), mask) +#define HWIO_GSI_INST_RAM_n_OUTI(n,val) \ + out_dword(HWIO_GSI_INST_RAM_n_ADDR(n),val) +#define HWIO_GSI_INST_RAM_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_GSI_INST_RAM_n_ADDR(n),mask,val,HWIO_GSI_INST_RAM_n_INI(n)) +#define HWIO_GSI_INST_RAM_n_INST_BYTE_3_BMSK 0xff000000 +#define HWIO_GSI_INST_RAM_n_INST_BYTE_3_SHFT 0x18 +#define HWIO_GSI_INST_RAM_n_INST_BYTE_2_BMSK 0xff0000 +#define HWIO_GSI_INST_RAM_n_INST_BYTE_2_SHFT 0x10 +#define HWIO_GSI_INST_RAM_n_INST_BYTE_1_BMSK 0xff00 +#define HWIO_GSI_INST_RAM_n_INST_BYTE_1_SHFT 0x8 +#define HWIO_GSI_INST_RAM_n_INST_BYTE_0_BMSK 0xff +#define HWIO_GSI_INST_RAM_n_INST_BYTE_0_SHFT 0x0 + +#define HWIO_GSI_SHRAM_n_ADDR(n) (GSI_REG_BASE + 0x00002000 + 0x4 * (n)) +#define HWIO_GSI_SHRAM_n_PHYS(n) (GSI_REG_BASE_PHYS + 0x00002000 + 0x4 * (n)) +#define HWIO_GSI_SHRAM_n_OFFS(n) (GSI_REG_BASE_OFFS + 0x00002000 + 0x4 * (n)) +#define HWIO_GSI_SHRAM_n_RMSK 0xffffffff +#define HWIO_GSI_SHRAM_n_MAXn 2037 +#define HWIO_GSI_SHRAM_n_ATTR 0x3 +#define HWIO_GSI_SHRAM_n_INI(n) \ + in_dword_masked(HWIO_GSI_SHRAM_n_ADDR(n), HWIO_GSI_SHRAM_n_RMSK, HWIO_GSI_SHRAM_n_ATTR) +#define HWIO_GSI_SHRAM_n_INMI(n,mask) \ + in_dword_masked(HWIO_GSI_SHRAM_n_ADDR(n), mask, HWIO_GSI_SHRAM_n_ATTR) +#define HWIO_GSI_SHRAM_n_OUTI(n,val) \ + out_dword(HWIO_GSI_SHRAM_n_ADDR(n),val, HWIO_GSI_SHRAM_n_ATTR) +#define HWIO_GSI_SHRAM_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_GSI_SHRAM_n_ADDR(n),mask,val,HWIO_GSI_SHRAM_n_INI(n)) +#define HWIO_GSI_SHRAM_n_SHRAM_BMSK 0xffffffff +#define HWIO_GSI_SHRAM_n_SHRAM_SHFT 0x0 + +#define HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_ADDR(n,k) (GSI_REG_BASE + 0x00009000 + 0x400 * (n) + 0x4 * (k)) +#define HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x00009000 + 0x400 * (n) + 0x4 * (k)) +#define HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x00009000 + 0x400 * (n) + 0x4 * (k)) +#define HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_RMSK 0x1ff +#define HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_MAXn 2 +#define HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_MAXk 27 +#define HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_ATTR 0x3 +#define HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_INI2(n,k) \ + in_dword_masked(HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_ADDR(n,k), HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_RMSK) +#define HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_INMI2(n,k,mask) \ + in_dword_masked(HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_ADDR(n,k), mask) +#define HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_OUTI2(n,k,val) \ + out_dword(HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_ADDR(n,k),val) +#define HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_ADDR(n,k),mask,val,HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_INI2(n,k)) +#define HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_VALID_BMSK 0x100 +#define HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_VALID_SHFT 0x8 +#define HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_PHY_CH_BMSK 0xff +#define HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_PHY_CH_SHFT 0x0 + +#define HWIO_GSI_TEST_BUS_SEL_ADDR (GSI_REG_BASE + 0x00001000) +#define HWIO_GSI_TEST_BUS_SEL_PHYS (GSI_REG_BASE_PHYS + 0x00001000) +#define HWIO_GSI_TEST_BUS_SEL_OFFS (GSI_REG_BASE_OFFS + 0x00001000) +#define HWIO_GSI_TEST_BUS_SEL_RMSK 0xf00ff +#define HWIO_GSI_TEST_BUS_SEL_ATTR 0x3 +#define HWIO_GSI_TEST_BUS_SEL_IN \ + in_dword_masked(HWIO_GSI_TEST_BUS_SEL_ADDR, HWIO_GSI_TEST_BUS_SEL_RMSK) +#define HWIO_GSI_TEST_BUS_SEL_INM(m) \ + in_dword_masked(HWIO_GSI_TEST_BUS_SEL_ADDR, m) +#define HWIO_GSI_TEST_BUS_SEL_OUT(v) \ + out_dword(HWIO_GSI_TEST_BUS_SEL_ADDR, v, HWIO_GSI_TEST_BUS_SEL_ATTR) +#define HWIO_GSI_TEST_BUS_SEL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_TEST_BUS_SEL_ADDR,m,v,HWIO_GSI_TEST_BUS_SEL_IN) +#define HWIO_GSI_TEST_BUS_SEL_GSI_HW_EVENTS_SEL_BMSK 0xf0000 +#define HWIO_GSI_TEST_BUS_SEL_GSI_HW_EVENTS_SEL_SHFT 0x10 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_BMSK 0xff +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_SHFT 0x0 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_ZEROS_FVAL 0x0 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MCS_0_FVAL 0x1 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MCS_1_FVAL 0x2 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MCS_2_FVAL 0x3 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MCS_3_FVAL 0x4 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MCS_4_FVAL 0x5 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_DB_ENG_FVAL 0x9 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_0_FVAL 0xb +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_1_FVAL 0xc +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_2_FVAL 0xd +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_3_FVAL 0xe +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_4_FVAL 0xf +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_5_FVAL 0x10 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_6_FVAL 0x11 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_7_FVAL 0x12 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_EVE_0_FVAL 0x13 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_EVE_1_FVAL 0x14 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_EVE_2_FVAL 0x15 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_EVE_3_FVAL 0x16 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_EVE_4_FVAL 0x17 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_EVE_5_FVAL 0x18 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IE_0_FVAL 0x1b +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IE_1_FVAL 0x1c +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IE_2_FVAL 0x1d +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IC_0_FVAL 0x1f +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IC_1_FVAL 0x20 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IC_2_FVAL 0x21 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IC_3_FVAL 0x22 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IC_4_FVAL 0x23 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MOQA_0_FVAL 0x27 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MOQA_1_FVAL 0x28 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MOQA_2_FVAL 0x29 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MOQA_3_FVAL 0x2a +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_TMR_0_FVAL 0x2b +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_TMR_1_FVAL 0x2c +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_TMR_2_FVAL 0x2d +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_TMR_3_FVAL 0x2e +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_RD_WR_0_FVAL 0x33 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_RD_WR_1_FVAL 0x34 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_RD_WR_2_FVAL 0x35 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_RD_WR_3_FVAL 0x36 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_CSR_FVAL 0x3a +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_SDMA_0_FVAL 0x3c +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_SMDA_1_FVAL 0x3d +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_CSR_1_FVAL 0x3e +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_CSR_2_FVAL 0x3f +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MCS_5_FVAL 0x40 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IC_5_FVAL 0x41 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_CSR_3_FVAL 0x42 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_TLV_0_FVAL 0x43 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_8_FVAL 0x44 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IE_NOTIFY_FVAL 0x45 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_DB_MSI_FVAL 0x46 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_9_FVAL 0x47 + +#define HWIO_GSI_TEST_BUS_REG_ADDR (GSI_REG_BASE + 0x00001008) +#define HWIO_GSI_TEST_BUS_REG_PHYS (GSI_REG_BASE_PHYS + 0x00001008) +#define HWIO_GSI_TEST_BUS_REG_OFFS (GSI_REG_BASE_OFFS + 0x00001008) +#define HWIO_GSI_TEST_BUS_REG_RMSK 0xffffffff +#define HWIO_GSI_TEST_BUS_REG_ATTR 0x1 +#define HWIO_GSI_TEST_BUS_REG_IN \ + in_dword_masked(HWIO_GSI_TEST_BUS_REG_ADDR, HWIO_GSI_TEST_BUS_REG_RMSK, HWIO_GSI_TEST_BUS_REG_ATTR) +#define HWIO_GSI_TEST_BUS_REG_INM(m) \ + in_dword_masked(HWIO_GSI_TEST_BUS_REG_ADDR, m, HWIO_GSI_TEST_BUS_REG_ATTR) +#define HWIO_GSI_TEST_BUS_REG_GSI_TESTBUS_REG_BMSK 0xffffffff +#define HWIO_GSI_TEST_BUS_REG_GSI_TESTBUS_REG_SHFT 0x0 + +#define HWIO_GSI_DEBUG_BUSY_REG_ADDR (GSI_REG_BASE + 0x00001010) +#define HWIO_GSI_DEBUG_BUSY_REG_PHYS (GSI_REG_BASE_PHYS + 0x00001010) +#define HWIO_GSI_DEBUG_BUSY_REG_OFFS (GSI_REG_BASE_OFFS + 0x00001010) +#define HWIO_GSI_DEBUG_BUSY_REG_RMSK 0x1fff +#define HWIO_GSI_DEBUG_BUSY_REG_ATTR 0x1 +#define HWIO_GSI_DEBUG_BUSY_REG_IN \ + in_dword_masked(HWIO_GSI_DEBUG_BUSY_REG_ADDR, HWIO_GSI_DEBUG_BUSY_REG_RMSK) +#define HWIO_GSI_DEBUG_BUSY_REG_INM(m) \ + in_dword_masked(HWIO_GSI_DEBUG_BUSY_REG_ADDR, m) +#define HWIO_GSI_DEBUG_BUSY_REG_SDMA_BUSY_BMSK 0x1000 +#define HWIO_GSI_DEBUG_BUSY_REG_SDMA_BUSY_SHFT 0xc +#define HWIO_GSI_DEBUG_BUSY_REG_IC_BUSY_BMSK 0x800 +#define HWIO_GSI_DEBUG_BUSY_REG_IC_BUSY_SHFT 0xb +#define HWIO_GSI_DEBUG_BUSY_REG_UC_BUSY_BMSK 0x400 +#define HWIO_GSI_DEBUG_BUSY_REG_UC_BUSY_SHFT 0xa +#define HWIO_GSI_DEBUG_BUSY_REG_DBG_CNT_BUSY_BMSK 0x200 +#define HWIO_GSI_DEBUG_BUSY_REG_DBG_CNT_BUSY_SHFT 0x9 +#define HWIO_GSI_DEBUG_BUSY_REG_DB_ENG_BUSY_BMSK 0x100 +#define HWIO_GSI_DEBUG_BUSY_REG_DB_ENG_BUSY_SHFT 0x8 +#define HWIO_GSI_DEBUG_BUSY_REG_REE_PWR_CLPS_BUSY_BMSK 0x80 +#define HWIO_GSI_DEBUG_BUSY_REG_REE_PWR_CLPS_BUSY_SHFT 0x7 +#define HWIO_GSI_DEBUG_BUSY_REG_INT_ENG_BUSY_BMSK 0x40 +#define HWIO_GSI_DEBUG_BUSY_REG_INT_ENG_BUSY_SHFT 0x6 +#define HWIO_GSI_DEBUG_BUSY_REG_EV_ENG_BUSY_BMSK 0x20 +#define HWIO_GSI_DEBUG_BUSY_REG_EV_ENG_BUSY_SHFT 0x5 +#define HWIO_GSI_DEBUG_BUSY_REG_RD_WR_BUSY_BMSK 0x10 +#define HWIO_GSI_DEBUG_BUSY_REG_RD_WR_BUSY_SHFT 0x4 +#define HWIO_GSI_DEBUG_BUSY_REG_TIMER_BUSY_BMSK 0x8 +#define HWIO_GSI_DEBUG_BUSY_REG_TIMER_BUSY_SHFT 0x3 +#define HWIO_GSI_DEBUG_BUSY_REG_MCS_BUSY_BMSK 0x4 +#define HWIO_GSI_DEBUG_BUSY_REG_MCS_BUSY_SHFT 0x2 +#define HWIO_GSI_DEBUG_BUSY_REG_REE_BUSY_BMSK 0x2 +#define HWIO_GSI_DEBUG_BUSY_REG_REE_BUSY_SHFT 0x1 +#define HWIO_GSI_DEBUG_BUSY_REG_CSR_BUSY_BMSK 0x1 +#define HWIO_GSI_DEBUG_BUSY_REG_CSR_BUSY_SHFT 0x0 + +#define HWIO_GSI_DEBUG_EVENT_PENDING_k_ADDR(k) (GSI_REG_BASE + 0x00001a80 + 0x4 * (k)) +#define HWIO_GSI_DEBUG_EVENT_PENDING_k_PHYS(k) (GSI_REG_BASE_PHYS + 0x00001a80 + 0x4 * (k)) +#define HWIO_GSI_DEBUG_EVENT_PENDING_k_OFFS(k) (GSI_REG_BASE_OFFS + 0x00001a80 + 0x4 * (k)) +#define HWIO_GSI_DEBUG_EVENT_PENDING_k_RMSK 0xffffffff +#define HWIO_GSI_DEBUG_EVENT_PENDING_k_MAXk 1 +#define HWIO_GSI_DEBUG_EVENT_PENDING_k_ATTR 0x1 +#define HWIO_GSI_DEBUG_EVENT_PENDING_k_INI(k) \ + in_dword_masked(HWIO_GSI_DEBUG_EVENT_PENDING_k_ADDR(k), HWIO_GSI_DEBUG_EVENT_PENDING_k_RMSK) +#define HWIO_GSI_DEBUG_EVENT_PENDING_k_INMI(k,mask) \ + in_dword_masked(HWIO_GSI_DEBUG_EVENT_PENDING_k_ADDR(k), mask) +#define HWIO_GSI_DEBUG_EVENT_PENDING_k_CHID_BIT_MAP_BMSK 0xffffffff +#define HWIO_GSI_DEBUG_EVENT_PENDING_k_CHID_BIT_MAP_SHFT 0x0 + +#define HWIO_GSI_DEBUG_TIMER_PENDING_k_ADDR(k) (GSI_REG_BASE + 0x00001aa0 + 0x4 * (k)) +#define HWIO_GSI_DEBUG_TIMER_PENDING_k_PHYS(k) (GSI_REG_BASE_PHYS + 0x00001aa0 + 0x4 * (k)) +#define HWIO_GSI_DEBUG_TIMER_PENDING_k_OFFS(k) (GSI_REG_BASE_OFFS + 0x00001aa0 + 0x4 * (k)) +#define HWIO_GSI_DEBUG_TIMER_PENDING_k_RMSK 0xffffffff +#define HWIO_GSI_DEBUG_TIMER_PENDING_k_MAXk 1 +#define HWIO_GSI_DEBUG_TIMER_PENDING_k_ATTR 0x1 +#define HWIO_GSI_DEBUG_TIMER_PENDING_k_INI(k) \ + in_dword_masked(HWIO_GSI_DEBUG_TIMER_PENDING_k_ADDR(k), HWIO_GSI_DEBUG_TIMER_PENDING_k_RMSK) +#define HWIO_GSI_DEBUG_TIMER_PENDING_k_INMI(k,mask) \ + in_dword_masked(HWIO_GSI_DEBUG_TIMER_PENDING_k_ADDR(k), mask) +#define HWIO_GSI_DEBUG_TIMER_PENDING_k_CHID_BIT_MAP_BMSK 0xffffffff +#define HWIO_GSI_DEBUG_TIMER_PENDING_k_CHID_BIT_MAP_SHFT 0x0 + +#define HWIO_GSI_DEBUG_RD_WR_PENDING_k_ADDR(k) (GSI_REG_BASE + 0x00001ac0 + 0x4 * (k)) +#define HWIO_GSI_DEBUG_RD_WR_PENDING_k_PHYS(k) (GSI_REG_BASE_PHYS + 0x00001ac0 + 0x4 * (k)) +#define HWIO_GSI_DEBUG_RD_WR_PENDING_k_OFFS(k) (GSI_REG_BASE_OFFS + 0x00001ac0 + 0x4 * (k)) +#define HWIO_GSI_DEBUG_RD_WR_PENDING_k_RMSK 0xffffffff +#define HWIO_GSI_DEBUG_RD_WR_PENDING_k_MAXk 1 +#define HWIO_GSI_DEBUG_RD_WR_PENDING_k_ATTR 0x1 +#define HWIO_GSI_DEBUG_RD_WR_PENDING_k_INI(k) \ + in_dword_masked(HWIO_GSI_DEBUG_RD_WR_PENDING_k_ADDR(k), HWIO_GSI_DEBUG_RD_WR_PENDING_k_RMSK) +#define HWIO_GSI_DEBUG_RD_WR_PENDING_k_INMI(k,mask) \ + in_dword_masked(HWIO_GSI_DEBUG_RD_WR_PENDING_k_ADDR(k), mask) +#define HWIO_GSI_DEBUG_RD_WR_PENDING_k_CHID_BIT_MAP_BMSK 0xffffffff +#define HWIO_GSI_DEBUG_RD_WR_PENDING_k_CHID_BIT_MAP_SHFT 0x0 + +#define HWIO_GSI_SPARE_REG_1_ADDR (GSI_REG_BASE + 0x00001030) +#define HWIO_GSI_SPARE_REG_1_PHYS (GSI_REG_BASE_PHYS + 0x00001030) +#define HWIO_GSI_SPARE_REG_1_OFFS (GSI_REG_BASE_OFFS + 0x00001030) +#define HWIO_GSI_SPARE_REG_1_RMSK 0x1 +#define HWIO_GSI_SPARE_REG_1_ATTR 0x3 +#define HWIO_GSI_SPARE_REG_1_IN \ + in_dword_masked(HWIO_GSI_SPARE_REG_1_ADDR, HWIO_GSI_SPARE_REG_1_RMSK) +#define HWIO_GSI_SPARE_REG_1_INM(m) \ + in_dword_masked(HWIO_GSI_SPARE_REG_1_ADDR, m) +#define HWIO_GSI_SPARE_REG_1_OUT(v) \ + out_dword(HWIO_GSI_SPARE_REG_1_ADDR,v) +#define HWIO_GSI_SPARE_REG_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_SPARE_REG_1_ADDR,m,v,HWIO_GSI_SPARE_REG_1_IN) +#define HWIO_GSI_SPARE_REG_1_FIX_IEOB_WRONG_MSK_DISABLE_BMSK 0x1 +#define HWIO_GSI_SPARE_REG_1_FIX_IEOB_WRONG_MSK_DISABLE_SHFT 0x0 + +#define HWIO_GSI_DEBUG_PC_FROM_SW_ADDR (GSI_REG_BASE + 0x00001040) +#define HWIO_GSI_DEBUG_PC_FROM_SW_PHYS (GSI_REG_BASE_PHYS + 0x00001040) +#define HWIO_GSI_DEBUG_PC_FROM_SW_OFFS (GSI_REG_BASE_OFFS + 0x00001040) +#define HWIO_GSI_DEBUG_PC_FROM_SW_RMSK 0xfff +#define HWIO_GSI_DEBUG_PC_FROM_SW_ATTR 0x3 +#define HWIO_GSI_DEBUG_PC_FROM_SW_IN \ + in_dword_masked(HWIO_GSI_DEBUG_PC_FROM_SW_ADDR, HWIO_GSI_DEBUG_PC_FROM_SW_RMSK) +#define HWIO_GSI_DEBUG_PC_FROM_SW_INM(m) \ + in_dword_masked(HWIO_GSI_DEBUG_PC_FROM_SW_ADDR, m) +#define HWIO_GSI_DEBUG_PC_FROM_SW_OUT(v) \ + out_dword(HWIO_GSI_DEBUG_PC_FROM_SW_ADDR,v) +#define HWIO_GSI_DEBUG_PC_FROM_SW_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_DEBUG_PC_FROM_SW_ADDR,m,v,HWIO_GSI_DEBUG_PC_FROM_SW_IN) +#define HWIO_GSI_DEBUG_PC_FROM_SW_IRAM_PTR_BMSK 0xfff +#define HWIO_GSI_DEBUG_PC_FROM_SW_IRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_DEBUG_SW_STALL_ADDR (GSI_REG_BASE + 0x00001044) +#define HWIO_GSI_DEBUG_SW_STALL_PHYS (GSI_REG_BASE_PHYS + 0x00001044) +#define HWIO_GSI_DEBUG_SW_STALL_OFFS (GSI_REG_BASE_OFFS + 0x00001044) +#define HWIO_GSI_DEBUG_SW_STALL_RMSK 0x1 +#define HWIO_GSI_DEBUG_SW_STALL_ATTR 0x3 +#define HWIO_GSI_DEBUG_SW_STALL_IN \ + in_dword_masked(HWIO_GSI_DEBUG_SW_STALL_ADDR, HWIO_GSI_DEBUG_SW_STALL_RMSK) +#define HWIO_GSI_DEBUG_SW_STALL_INM(m) \ + in_dword_masked(HWIO_GSI_DEBUG_SW_STALL_ADDR, m) +#define HWIO_GSI_DEBUG_SW_STALL_OUT(v) \ + out_dword(HWIO_GSI_DEBUG_SW_STALL_ADDR,v) +#define HWIO_GSI_DEBUG_SW_STALL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_DEBUG_SW_STALL_ADDR,m,v,HWIO_GSI_DEBUG_SW_STALL_IN) +#define HWIO_GSI_DEBUG_SW_STALL_MCS_STALL_BMSK 0x1 +#define HWIO_GSI_DEBUG_SW_STALL_MCS_STALL_SHFT 0x0 + +#define HWIO_GSI_DEBUG_PC_FOR_DEBUG_ADDR (GSI_REG_BASE + 0x00001048) +#define HWIO_GSI_DEBUG_PC_FOR_DEBUG_PHYS (GSI_REG_BASE_PHYS + 0x00001048) +#define HWIO_GSI_DEBUG_PC_FOR_DEBUG_OFFS (GSI_REG_BASE_OFFS + 0x00001048) +#define HWIO_GSI_DEBUG_PC_FOR_DEBUG_RMSK 0xfff +#define HWIO_GSI_DEBUG_PC_FOR_DEBUG_ATTR 0x1 +#define HWIO_GSI_DEBUG_PC_FOR_DEBUG_IN \ + in_dword_masked(HWIO_GSI_DEBUG_PC_FOR_DEBUG_ADDR, HWIO_GSI_DEBUG_PC_FOR_DEBUG_RMSK) +#define HWIO_GSI_DEBUG_PC_FOR_DEBUG_INM(m) \ + in_dword_masked(HWIO_GSI_DEBUG_PC_FOR_DEBUG_ADDR, m) +#define HWIO_GSI_DEBUG_PC_FOR_DEBUG_IRAM_PTR_BMSK 0xfff +#define HWIO_GSI_DEBUG_PC_FOR_DEBUG_IRAM_PTR_SHFT 0x0 + +#define HWIO_GSI_DEBUG_QSB_LOG_SEL_ADDR (GSI_REG_BASE + 0x00001050) +#define HWIO_GSI_DEBUG_QSB_LOG_SEL_PHYS (GSI_REG_BASE_PHYS + 0x00001050) +#define HWIO_GSI_DEBUG_QSB_LOG_SEL_OFFS (GSI_REG_BASE_OFFS + 0x00001050) +#define HWIO_GSI_DEBUG_QSB_LOG_SEL_RMSK 0xffff01 +#define HWIO_GSI_DEBUG_QSB_LOG_SEL_ATTR 0x3 +#define HWIO_GSI_DEBUG_QSB_LOG_SEL_IN \ + in_dword_masked(HWIO_GSI_DEBUG_QSB_LOG_SEL_ADDR, HWIO_GSI_DEBUG_QSB_LOG_SEL_RMSK) +#define HWIO_GSI_DEBUG_QSB_LOG_SEL_INM(m) \ + in_dword_masked(HWIO_GSI_DEBUG_QSB_LOG_SEL_ADDR, m) +#define HWIO_GSI_DEBUG_QSB_LOG_SEL_OUT(v) \ + out_dword(HWIO_GSI_DEBUG_QSB_LOG_SEL_ADDR,v) +#define HWIO_GSI_DEBUG_QSB_LOG_SEL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_DEBUG_QSB_LOG_SEL_ADDR,m,v,HWIO_GSI_DEBUG_QSB_LOG_SEL_IN) +#define HWIO_GSI_DEBUG_QSB_LOG_SEL_SEL_MID_BMSK 0xff0000 +#define HWIO_GSI_DEBUG_QSB_LOG_SEL_SEL_MID_SHFT 0x10 +#define HWIO_GSI_DEBUG_QSB_LOG_SEL_SEL_TID_BMSK 0xff00 +#define HWIO_GSI_DEBUG_QSB_LOG_SEL_SEL_TID_SHFT 0x8 +#define HWIO_GSI_DEBUG_QSB_LOG_SEL_SEL_WRITE_BMSK 0x1 +#define HWIO_GSI_DEBUG_QSB_LOG_SEL_SEL_WRITE_SHFT 0x0 + +#define HWIO_GSI_DEBUG_QSB_LOG_CLR_ADDR (GSI_REG_BASE + 0x00001058) +#define HWIO_GSI_DEBUG_QSB_LOG_CLR_PHYS (GSI_REG_BASE_PHYS + 0x00001058) +#define HWIO_GSI_DEBUG_QSB_LOG_CLR_OFFS (GSI_REG_BASE_OFFS + 0x00001058) +#define HWIO_GSI_DEBUG_QSB_LOG_CLR_RMSK 0x1 +#define HWIO_GSI_DEBUG_QSB_LOG_CLR_ATTR 0x2 +#define HWIO_GSI_DEBUG_QSB_LOG_CLR_OUT(v) \ + out_dword(HWIO_GSI_DEBUG_QSB_LOG_CLR_ADDR,v) +#define HWIO_GSI_DEBUG_QSB_LOG_CLR_LOG_CLR_BMSK 0x1 +#define HWIO_GSI_DEBUG_QSB_LOG_CLR_LOG_CLR_SHFT 0x0 + +#define HWIO_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ADDR (GSI_REG_BASE + 0x00001060) +#define HWIO_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_PHYS (GSI_REG_BASE_PHYS + 0x00001060) +#define HWIO_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_OFFS (GSI_REG_BASE_OFFS + 0x00001060) +#define HWIO_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_RMSK 0x1ffff01 +#define HWIO_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ATTR 0x1 +#define HWIO_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_IN \ + in_dword_masked(HWIO_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ADDR, HWIO_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_RMSK) +#define HWIO_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_INM(m) \ + in_dword_masked(HWIO_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ADDR, m) +#define HWIO_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ERR_SAVED_BMSK 0x1000000 +#define HWIO_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ERR_SAVED_SHFT 0x18 +#define HWIO_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ERR_MID_BMSK 0xff0000 +#define HWIO_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ERR_MID_SHFT 0x10 +#define HWIO_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ERR_TID_BMSK 0xff00 +#define HWIO_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ERR_TID_SHFT 0x8 +#define HWIO_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ERR_WRITE_BMSK 0x1 +#define HWIO_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ERR_WRITE_SHFT 0x0 + +#define HWIO_GSI_DEBUG_QSB_LOG_0_ADDR (GSI_REG_BASE + 0x00001064) +#define HWIO_GSI_DEBUG_QSB_LOG_0_PHYS (GSI_REG_BASE_PHYS + 0x00001064) +#define HWIO_GSI_DEBUG_QSB_LOG_0_OFFS (GSI_REG_BASE_OFFS + 0x00001064) +#define HWIO_GSI_DEBUG_QSB_LOG_0_RMSK 0xffffffff +#define HWIO_GSI_DEBUG_QSB_LOG_0_ATTR 0x1 +#define HWIO_GSI_DEBUG_QSB_LOG_0_IN \ + in_dword_masked(HWIO_GSI_DEBUG_QSB_LOG_0_ADDR, HWIO_GSI_DEBUG_QSB_LOG_0_RMSK) +#define HWIO_GSI_DEBUG_QSB_LOG_0_INM(m) \ + in_dword_masked(HWIO_GSI_DEBUG_QSB_LOG_0_ADDR, m) +#define HWIO_GSI_DEBUG_QSB_LOG_0_ADDR_31_0_BMSK 0xffffffff +#define HWIO_GSI_DEBUG_QSB_LOG_0_ADDR_31_0_SHFT 0x0 + +#define HWIO_GSI_DEBUG_QSB_LOG_1_ADDR (GSI_REG_BASE + 0x00001068) +#define HWIO_GSI_DEBUG_QSB_LOG_1_PHYS (GSI_REG_BASE_PHYS + 0x00001068) +#define HWIO_GSI_DEBUG_QSB_LOG_1_OFFS (GSI_REG_BASE_OFFS + 0x00001068) +#define HWIO_GSI_DEBUG_QSB_LOG_1_RMSK 0xfff7ffff +#define HWIO_GSI_DEBUG_QSB_LOG_1_ATTR 0x1 +#define HWIO_GSI_DEBUG_QSB_LOG_1_IN \ + in_dword_masked(HWIO_GSI_DEBUG_QSB_LOG_1_ADDR, HWIO_GSI_DEBUG_QSB_LOG_1_RMSK) +#define HWIO_GSI_DEBUG_QSB_LOG_1_INM(m) \ + in_dword_masked(HWIO_GSI_DEBUG_QSB_LOG_1_ADDR, m) +#define HWIO_GSI_DEBUG_QSB_LOG_1_AREQPRIORITY_BMSK 0xf0000000 +#define HWIO_GSI_DEBUG_QSB_LOG_1_AREQPRIORITY_SHFT 0x1c +#define HWIO_GSI_DEBUG_QSB_LOG_1_ASIZE_BMSK 0xf000000 +#define HWIO_GSI_DEBUG_QSB_LOG_1_ASIZE_SHFT 0x18 +#define HWIO_GSI_DEBUG_QSB_LOG_1_ALEN_BMSK 0xf00000 +#define HWIO_GSI_DEBUG_QSB_LOG_1_ALEN_SHFT 0x14 +#define HWIO_GSI_DEBUG_QSB_LOG_1_AOOOWR_BMSK 0x40000 +#define HWIO_GSI_DEBUG_QSB_LOG_1_AOOOWR_SHFT 0x12 +#define HWIO_GSI_DEBUG_QSB_LOG_1_AOOORD_BMSK 0x20000 +#define HWIO_GSI_DEBUG_QSB_LOG_1_AOOORD_SHFT 0x11 +#define HWIO_GSI_DEBUG_QSB_LOG_1_ATRANSIENT_BMSK 0x10000 +#define HWIO_GSI_DEBUG_QSB_LOG_1_ATRANSIENT_SHFT 0x10 +#define HWIO_GSI_DEBUG_QSB_LOG_1_ACACHEABLE_BMSK 0x8000 +#define HWIO_GSI_DEBUG_QSB_LOG_1_ACACHEABLE_SHFT 0xf +#define HWIO_GSI_DEBUG_QSB_LOG_1_ASHARED_BMSK 0x4000 +#define HWIO_GSI_DEBUG_QSB_LOG_1_ASHARED_SHFT 0xe +#define HWIO_GSI_DEBUG_QSB_LOG_1_ANOALLOCATE_BMSK 0x2000 +#define HWIO_GSI_DEBUG_QSB_LOG_1_ANOALLOCATE_SHFT 0xd +#define HWIO_GSI_DEBUG_QSB_LOG_1_AINNERSHARED_BMSK 0x1000 +#define HWIO_GSI_DEBUG_QSB_LOG_1_AINNERSHARED_SHFT 0xc +#define HWIO_GSI_DEBUG_QSB_LOG_1_ADDR_43_32_BMSK 0xfff +#define HWIO_GSI_DEBUG_QSB_LOG_1_ADDR_43_32_SHFT 0x0 + +#define HWIO_GSI_DEBUG_QSB_LOG_2_ADDR (GSI_REG_BASE + 0x0000106c) +#define HWIO_GSI_DEBUG_QSB_LOG_2_PHYS (GSI_REG_BASE_PHYS + 0x0000106c) +#define HWIO_GSI_DEBUG_QSB_LOG_2_OFFS (GSI_REG_BASE_OFFS + 0x0000106c) +#define HWIO_GSI_DEBUG_QSB_LOG_2_RMSK 0xffff +#define HWIO_GSI_DEBUG_QSB_LOG_2_ATTR 0x1 +#define HWIO_GSI_DEBUG_QSB_LOG_2_IN \ + in_dword_masked(HWIO_GSI_DEBUG_QSB_LOG_2_ADDR, HWIO_GSI_DEBUG_QSB_LOG_2_RMSK) +#define HWIO_GSI_DEBUG_QSB_LOG_2_INM(m) \ + in_dword_masked(HWIO_GSI_DEBUG_QSB_LOG_2_ADDR, m) +#define HWIO_GSI_DEBUG_QSB_LOG_2_AMEMTYPE_BMSK 0xf000 +#define HWIO_GSI_DEBUG_QSB_LOG_2_AMEMTYPE_SHFT 0xc +#define HWIO_GSI_DEBUG_QSB_LOG_2_AMMUSID_BMSK 0xfff +#define HWIO_GSI_DEBUG_QSB_LOG_2_AMMUSID_SHFT 0x0 + +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_ADDR(n) (GSI_REG_BASE + 0x00001070 + 0x4 * (n)) +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_PHYS(n) (GSI_REG_BASE_PHYS + 0x00001070 + 0x4 * (n)) +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_OFFS(n) (GSI_REG_BASE_OFFS + 0x00001070 + 0x4 * (n)) +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_RMSK 0xffffffff +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_MAXn 3 +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_ATTR 0x1 +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_INI(n) \ + in_dword_masked(HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_ADDR(n), HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_RMSK) +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_INMI(n,mask) \ + in_dword_masked(HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_ADDR(n), mask) +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_MID_BMSK 0xf8000000 +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_MID_SHFT 0x1b +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_TID_BMSK 0x7c00000 +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_TID_SHFT 0x16 +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_WRITE_BMSK 0x200000 +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_WRITE_SHFT 0x15 +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_ADDR_20_0_BMSK 0x1fffff +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_ADDR_20_0_SHFT 0x0 + +#define HWIO_GSI_DEBUG_SW_RF_n_WRITE_ADDR(n) (GSI_REG_BASE + 0x00001080 + 0x4 * (n)) +#define HWIO_GSI_DEBUG_SW_RF_n_WRITE_PHYS(n) (GSI_REG_BASE_PHYS + 0x00001080 + 0x4 * (n)) +#define HWIO_GSI_DEBUG_SW_RF_n_WRITE_OFFS(n) (GSI_REG_BASE_OFFS + 0x00001080 + 0x4 * (n)) +#define HWIO_GSI_DEBUG_SW_RF_n_WRITE_RMSK 0xffffffff +#define HWIO_GSI_DEBUG_SW_RF_n_WRITE_MAXn 31 +#define HWIO_GSI_DEBUG_SW_RF_n_WRITE_ATTR 0x2 +#define HWIO_GSI_DEBUG_SW_RF_n_WRITE_OUTI(n,val) \ + out_dword(HWIO_GSI_DEBUG_SW_RF_n_WRITE_ADDR(n),val) +#define HWIO_GSI_DEBUG_SW_RF_n_WRITE_DATA_IN_BMSK 0xffffffff +#define HWIO_GSI_DEBUG_SW_RF_n_WRITE_DATA_IN_SHFT 0x0 + +#define HWIO_GSI_DEBUG_SW_RF_n_READ_ADDR(n) (GSI_REG_BASE + 0x00001100 + 0x4 * (n)) +#define HWIO_GSI_DEBUG_SW_RF_n_READ_PHYS(n) (GSI_REG_BASE_PHYS + 0x00001100 + 0x4 * (n)) +#define HWIO_GSI_DEBUG_SW_RF_n_READ_OFFS(n) (GSI_REG_BASE_OFFS + 0x00001100 + 0x4 * (n)) +#define HWIO_GSI_DEBUG_SW_RF_n_READ_RMSK 0xffffffff +#define HWIO_GSI_DEBUG_SW_RF_n_READ_MAXn 31 +#define HWIO_GSI_DEBUG_SW_RF_n_READ_ATTR 0x1 +#define HWIO_GSI_DEBUG_SW_RF_n_READ_INI(n) \ + in_dword_masked(HWIO_GSI_DEBUG_SW_RF_n_READ_ADDR(n), HWIO_GSI_DEBUG_SW_RF_n_READ_RMSK, HWIO_GSI_DEBUG_SW_RF_n_READ_ATTR) +#define HWIO_GSI_DEBUG_SW_RF_n_READ_INMI(n,mask) \ + in_dword_masked(HWIO_GSI_DEBUG_SW_RF_n_READ_ADDR(n), mask, HWIO_GSI_DEBUG_SW_RF_n_READ_ATTR) +#define HWIO_GSI_DEBUG_SW_RF_n_READ_RF_REG_BMSK 0xffffffff +#define HWIO_GSI_DEBUG_SW_RF_n_READ_RF_REG_SHFT 0x0 + +#define HWIO_GSI_DEBUG_COUNTER_CFGn_ADDR(n) (GSI_REG_BASE + 0x00001180 + 0x4 * (n)) +#define HWIO_GSI_DEBUG_COUNTER_CFGn_PHYS(n) (GSI_REG_BASE_PHYS + 0x00001180 + 0x4 * (n)) +#define HWIO_GSI_DEBUG_COUNTER_CFGn_OFFS(n) (GSI_REG_BASE_OFFS + 0x00001180 + 0x4 * (n)) +#define HWIO_GSI_DEBUG_COUNTER_CFGn_RMSK 0x1fffff +#define HWIO_GSI_DEBUG_COUNTER_CFGn_MAXn 7 +#define HWIO_GSI_DEBUG_COUNTER_CFGn_ATTR 0x3 +#define HWIO_GSI_DEBUG_COUNTER_CFGn_INI(n) \ + in_dword_masked(HWIO_GSI_DEBUG_COUNTER_CFGn_ADDR(n), HWIO_GSI_DEBUG_COUNTER_CFGn_RMSK) +#define HWIO_GSI_DEBUG_COUNTER_CFGn_INMI(n,mask) \ + in_dword_masked(HWIO_GSI_DEBUG_COUNTER_CFGn_ADDR(n), mask) +#define HWIO_GSI_DEBUG_COUNTER_CFGn_OUTI(n,val) \ + out_dword(HWIO_GSI_DEBUG_COUNTER_CFGn_ADDR(n),val) +#define HWIO_GSI_DEBUG_COUNTER_CFGn_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_GSI_DEBUG_COUNTER_CFGn_ADDR(n),mask,val,HWIO_GSI_DEBUG_COUNTER_CFGn_INI(n)) +#define HWIO_GSI_DEBUG_COUNTER_CFGn_CHAIN_BMSK 0x100000 +#define HWIO_GSI_DEBUG_COUNTER_CFGn_CHAIN_SHFT 0x14 +#define HWIO_GSI_DEBUG_COUNTER_CFGn_VIRTUAL_CHNL_BMSK 0xff000 +#define HWIO_GSI_DEBUG_COUNTER_CFGn_VIRTUAL_CHNL_SHFT 0xc +#define HWIO_GSI_DEBUG_COUNTER_CFGn_EE_BMSK 0xf00 +#define HWIO_GSI_DEBUG_COUNTER_CFGn_EE_SHFT 0x8 +#define HWIO_GSI_DEBUG_COUNTER_CFGn_EVNT_TYPE_BMSK 0xf8 +#define HWIO_GSI_DEBUG_COUNTER_CFGn_EVNT_TYPE_SHFT 0x3 +#define HWIO_GSI_DEBUG_COUNTER_CFGn_CLR_AT_READ_BMSK 0x4 +#define HWIO_GSI_DEBUG_COUNTER_CFGn_CLR_AT_READ_SHFT 0x2 +#define HWIO_GSI_DEBUG_COUNTER_CFGn_STOP_AT_WRAP_ARND_BMSK 0x2 +#define HWIO_GSI_DEBUG_COUNTER_CFGn_STOP_AT_WRAP_ARND_SHFT 0x1 +#define HWIO_GSI_DEBUG_COUNTER_CFGn_ENABLE_BMSK 0x1 +#define HWIO_GSI_DEBUG_COUNTER_CFGn_ENABLE_SHFT 0x0 + +#define HWIO_GSI_DEBUG_COUNTERn_ADDR(n) (GSI_REG_BASE + 0x000011a0 + 0x4 * (n)) +#define HWIO_GSI_DEBUG_COUNTERn_PHYS(n) (GSI_REG_BASE_PHYS + 0x000011a0 + 0x4 * (n)) +#define HWIO_GSI_DEBUG_COUNTERn_OFFS(n) (GSI_REG_BASE_OFFS + 0x000011a0 + 0x4 * (n)) +#define HWIO_GSI_DEBUG_COUNTERn_RMSK 0xffff +#define HWIO_GSI_DEBUG_COUNTERn_MAXn 7 +#define HWIO_GSI_DEBUG_COUNTERn_ATTR 0x1 +#define HWIO_GSI_DEBUG_COUNTERn_INI(n) \ + in_dword_masked(HWIO_GSI_DEBUG_COUNTERn_ADDR(n), HWIO_GSI_DEBUG_COUNTERn_RMSK, HWIO_GSI_DEBUG_COUNTERn_ATTR) +#define HWIO_GSI_DEBUG_COUNTERn_INMI(n,mask) \ + in_dword_masked(HWIO_GSI_DEBUG_COUNTERn_ADDR(n), mask, HWIO_GSI_DEBUG_COUNTERn_ATTR) +#define HWIO_GSI_DEBUG_COUNTERn_COUNTER_VALUE_BMSK 0xffff +#define HWIO_GSI_DEBUG_COUNTERn_COUNTER_VALUE_SHFT 0x0 + +#define HWIO_GSI_DEBUG_SW_MSK_REG_n_SEC_k_WR_ADDR(n,k) (GSI_REG_BASE + 0x000011c0 + 0x4 * (n) + 0x24 * (k)) +#define HWIO_GSI_DEBUG_SW_MSK_REG_n_SEC_k_WR_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x000011c0 + 0x4 * (n) + 0x24 * (k)) +#define HWIO_GSI_DEBUG_SW_MSK_REG_n_SEC_k_WR_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x000011c0 + 0x4 * (n) + 0x24 * (k)) +#define HWIO_GSI_DEBUG_SW_MSK_REG_n_SEC_k_WR_RMSK 0xffffffff +#define HWIO_GSI_DEBUG_SW_MSK_REG_n_SEC_k_WR_MAXn 8 +#define HWIO_GSI_DEBUG_SW_MSK_REG_n_SEC_k_WR_MAXk 1 +#define HWIO_GSI_DEBUG_SW_MSK_REG_n_SEC_k_WR_ATTR 0x2 +#define HWIO_GSI_DEBUG_SW_MSK_REG_n_SEC_k_WR_OUTI2(n,k,val) \ + out_dword(HWIO_GSI_DEBUG_SW_MSK_REG_n_SEC_k_WR_ADDR(n,k),val) +#define HWIO_GSI_DEBUG_SW_MSK_REG_n_SEC_k_WR_DATA_IN_BMSK 0xffffffff +#define HWIO_GSI_DEBUG_SW_MSK_REG_n_SEC_k_WR_DATA_IN_SHFT 0x0 + +#define HWIO_GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD_ADDR(n,k) (GSI_REG_BASE + 0x000012e0 + 0x4 * (n) + 0x24 * (k)) +#define HWIO_GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x000012e0 + 0x4 * (n) + 0x24 * (k)) +#define HWIO_GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x000012e0 + 0x4 * (n) + 0x24 * (k)) +#define HWIO_GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD_RMSK 0xffffffff +#define HWIO_GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD_MAXn 8 +#define HWIO_GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD_MAXk 1 +#define HWIO_GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD_ATTR 0x1 +#define HWIO_GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD_INI2(n,k) \ + in_dword_masked(HWIO_GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD_ADDR(n,k), HWIO_GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD_RMSK) +#define HWIO_GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD_INMI2(n,k,mask) \ + in_dword_masked(HWIO_GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD_ADDR(n,k), mask) +#define HWIO_GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD_MSK_REG_BMSK 0xffffffff +#define HWIO_GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD_MSK_REG_SHFT 0x0 + +#define HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_ADDR(n,k) (GSI_REG_BASE + 0x00001400 + 0x80 * (n) + 0x4 * (k)) +#define HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x00001400 + 0x80 * (n) + 0x4 * (k)) +#define HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x00001400 + 0x80 * (n) + 0x4 * (k)) +#define HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_RMSK 0x1ff +#define HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_MAXn 3 +#define HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_MAXk 27 +#define HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_ATTR 0x1 +#define HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_INI2(n,k) \ + in_dword_masked(HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_ADDR(n,k), HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_RMSK) +#define HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_INMI2(n,k,mask) \ + in_dword_masked(HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_ADDR(n,k), mask) +#define HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_VALID_BMSK 0x100 +#define HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_VALID_SHFT 0x8 +#define HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_PHY_CH_BMSK 0xff +#define HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_PHY_CH_SHFT 0x0 + +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_ADDR(n,k) (GSI_REG_BASE + 0x00001600 + 0x100 * (n) + 0x4 * (k)) +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x00001600 + 0x100 * (n) + 0x4 * (k)) +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x00001600 + 0x100 * (n) + 0x4 * (k)) +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_RMSK 0x1ff +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_MAXn 3 +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_MAXk 26 +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_ATTR 0x1 +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_INI2(n,k) \ + in_dword_masked(HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_ADDR(n,k), HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_RMSK) +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_INMI2(n,k,mask) \ + in_dword_masked(HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_ADDR(n,k), mask) +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_VALID_BMSK 0x100 +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_VALID_SHFT 0x8 +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_PHY_EV_CH_BMSK 0xff +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_PHY_EV_CH_SHFT 0x0 + +#define HWIO_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_ADDR (GSI_REG_BASE + 0x00001a54) +#define HWIO_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_PHYS (GSI_REG_BASE_PHYS + 0x00001a54) +#define HWIO_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_OFFS (GSI_REG_BASE_OFFS + 0x00001a54) +#define HWIO_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_RMSK 0xff +#define HWIO_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_ATTR 0x3 +#define HWIO_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_IN \ + in_dword_masked(HWIO_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_ADDR, HWIO_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_RMSK) +#define HWIO_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_INM(m) \ + in_dword_masked(HWIO_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_ADDR, m) +#define HWIO_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_OUT(v) \ + out_dword(HWIO_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_ADDR,v) +#define HWIO_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_ADDR,m,v,HWIO_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_IN) +#define HWIO_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_PREFETCH_BUF_CH_ID_BMSK 0xff +#define HWIO_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_PREFETCH_BUF_CH_ID_SHFT 0x0 + +#define HWIO_GSI_DEBUG_REE_PREFETCH_BUF_STATUS_ADDR (GSI_REG_BASE + 0x00001a58) +#define HWIO_GSI_DEBUG_REE_PREFETCH_BUF_STATUS_PHYS (GSI_REG_BASE_PHYS + 0x00001a58) +#define HWIO_GSI_DEBUG_REE_PREFETCH_BUF_STATUS_OFFS (GSI_REG_BASE_OFFS + 0x00001a58) +#define HWIO_GSI_DEBUG_REE_PREFETCH_BUF_STATUS_RMSK 0xffffffff +#define HWIO_GSI_DEBUG_REE_PREFETCH_BUF_STATUS_ATTR 0x1 +#define HWIO_GSI_DEBUG_REE_PREFETCH_BUF_STATUS_IN \ + in_dword_masked(HWIO_GSI_DEBUG_REE_PREFETCH_BUF_STATUS_ADDR, HWIO_GSI_DEBUG_REE_PREFETCH_BUF_STATUS_RMSK) +#define HWIO_GSI_DEBUG_REE_PREFETCH_BUF_STATUS_INM(m) \ + in_dword_masked(HWIO_GSI_DEBUG_REE_PREFETCH_BUF_STATUS_ADDR, m) +#define HWIO_GSI_DEBUG_REE_PREFETCH_BUF_STATUS_PREFETCH_BUF_STATUS_BMSK 0xffffffff +#define HWIO_GSI_DEBUG_REE_PREFETCH_BUF_STATUS_PREFETCH_BUF_STATUS_SHFT 0x0 + +#define HWIO_GSI_MCS_PROFILING_BP_CNT_LSB_ADDR (GSI_REG_BASE + 0x00001a5c) +#define HWIO_GSI_MCS_PROFILING_BP_CNT_LSB_PHYS (GSI_REG_BASE_PHYS + 0x00001a5c) +#define HWIO_GSI_MCS_PROFILING_BP_CNT_LSB_OFFS (GSI_REG_BASE_OFFS + 0x00001a5c) +#define HWIO_GSI_MCS_PROFILING_BP_CNT_LSB_RMSK 0xffffffff +#define HWIO_GSI_MCS_PROFILING_BP_CNT_LSB_ATTR 0x1 +#define HWIO_GSI_MCS_PROFILING_BP_CNT_LSB_IN \ + in_dword_masked(HWIO_GSI_MCS_PROFILING_BP_CNT_LSB_ADDR, HWIO_GSI_MCS_PROFILING_BP_CNT_LSB_RMSK) +#define HWIO_GSI_MCS_PROFILING_BP_CNT_LSB_INM(m) \ + in_dword_masked(HWIO_GSI_MCS_PROFILING_BP_CNT_LSB_ADDR, m) +#define HWIO_GSI_MCS_PROFILING_BP_CNT_LSB_BP_CNT_LSB_BMSK 0xffffffff +#define HWIO_GSI_MCS_PROFILING_BP_CNT_LSB_BP_CNT_LSB_SHFT 0x0 + +#define HWIO_GSI_MCS_PROFILING_BP_CNT_MSB_ADDR (GSI_REG_BASE + 0x00001a60) +#define HWIO_GSI_MCS_PROFILING_BP_CNT_MSB_PHYS (GSI_REG_BASE_PHYS + 0x00001a60) +#define HWIO_GSI_MCS_PROFILING_BP_CNT_MSB_OFFS (GSI_REG_BASE_OFFS + 0x00001a60) +#define HWIO_GSI_MCS_PROFILING_BP_CNT_MSB_RMSK 0xffff +#define HWIO_GSI_MCS_PROFILING_BP_CNT_MSB_ATTR 0x1 +#define HWIO_GSI_MCS_PROFILING_BP_CNT_MSB_IN \ + in_dword_masked(HWIO_GSI_MCS_PROFILING_BP_CNT_MSB_ADDR, HWIO_GSI_MCS_PROFILING_BP_CNT_MSB_RMSK) +#define HWIO_GSI_MCS_PROFILING_BP_CNT_MSB_INM(m) \ + in_dword_masked(HWIO_GSI_MCS_PROFILING_BP_CNT_MSB_ADDR, m) +#define HWIO_GSI_MCS_PROFILING_BP_CNT_MSB_BP_CNT_MSB_BMSK 0xffff +#define HWIO_GSI_MCS_PROFILING_BP_CNT_MSB_BP_CNT_MSB_SHFT 0x0 + +#define HWIO_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB_ADDR (GSI_REG_BASE + 0x00001a64) +#define HWIO_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB_PHYS (GSI_REG_BASE_PHYS + 0x00001a64) +#define HWIO_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB_OFFS (GSI_REG_BASE_OFFS + 0x00001a64) +#define HWIO_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB_RMSK 0xffffffff +#define HWIO_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB_ATTR 0x1 +#define HWIO_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB_IN \ + in_dword_masked(HWIO_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB_ADDR, HWIO_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB_RMSK) +#define HWIO_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB_INM(m) \ + in_dword_masked(HWIO_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB_ADDR, m) +#define HWIO_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB_BP_AND_PENDING_CNT_LSB_BMSK 0xffffffff +#define HWIO_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB_BP_AND_PENDING_CNT_LSB_SHFT 0x0 + +#define HWIO_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB_ADDR (GSI_REG_BASE + 0x00001a68) +#define HWIO_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB_PHYS (GSI_REG_BASE_PHYS + 0x00001a68) +#define HWIO_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB_OFFS (GSI_REG_BASE_OFFS + 0x00001a68) +#define HWIO_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB_RMSK 0xffff +#define HWIO_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB_ATTR 0x1 +#define HWIO_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB_IN \ + in_dword_masked(HWIO_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB_ADDR, HWIO_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB_RMSK) +#define HWIO_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB_INM(m) \ + in_dword_masked(HWIO_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB_ADDR, m) +#define HWIO_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB_BP_AND_PENDING_CNT_MSB_BMSK 0xffff +#define HWIO_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB_BP_AND_PENDING_CNT_MSB_SHFT 0x0 + +#define HWIO_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB_ADDR (GSI_REG_BASE + 0x00001a6c) +#define HWIO_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB_PHYS (GSI_REG_BASE_PHYS + 0x00001a6c) +#define HWIO_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB_OFFS (GSI_REG_BASE_OFFS + 0x00001a6c) +#define HWIO_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB_RMSK 0xffffffff +#define HWIO_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB_ATTR 0x1 +#define HWIO_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB_IN \ + in_dword_masked(HWIO_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB_ADDR, HWIO_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB_RMSK) +#define HWIO_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB_INM(m) \ + in_dword_masked(HWIO_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB_ADDR, m) +#define HWIO_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB_MCS_BUSY_CNT_LSB_BMSK 0xffffffff +#define HWIO_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB_MCS_BUSY_CNT_LSB_SHFT 0x0 + +#define HWIO_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB_ADDR (GSI_REG_BASE + 0x00001a70) +#define HWIO_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB_PHYS (GSI_REG_BASE_PHYS + 0x00001a70) +#define HWIO_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB_OFFS (GSI_REG_BASE_OFFS + 0x00001a70) +#define HWIO_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB_RMSK 0xffff +#define HWIO_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB_ATTR 0x1 +#define HWIO_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB_IN \ + in_dword_masked(HWIO_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB_ADDR, HWIO_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB_RMSK) +#define HWIO_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB_INM(m) \ + in_dword_masked(HWIO_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB_ADDR, m) +#define HWIO_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB_MCS_BUSY_CNT_MSB_BMSK 0xffff +#define HWIO_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB_MCS_BUSY_CNT_MSB_SHFT 0x0 + +#define HWIO_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB_ADDR (GSI_REG_BASE + 0x00001a74) +#define HWIO_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB_PHYS (GSI_REG_BASE_PHYS + 0x00001a74) +#define HWIO_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB_OFFS (GSI_REG_BASE_OFFS + 0x00001a74) +#define HWIO_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB_RMSK 0xffffffff +#define HWIO_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB_ATTR 0x1 +#define HWIO_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB_IN \ + in_dword_masked(HWIO_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB_ADDR, HWIO_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB_RMSK) +#define HWIO_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB_INM(m) \ + in_dword_masked(HWIO_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB_ADDR, m) +#define HWIO_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB_MCS_IDLE_CNT_LSB_BMSK 0xffffffff +#define HWIO_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB_MCS_IDLE_CNT_LSB_SHFT 0x0 + +#define HWIO_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_ADDR (GSI_REG_BASE + 0x00001a78) +#define HWIO_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_PHYS (GSI_REG_BASE_PHYS + 0x00001a78) +#define HWIO_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_OFFS (GSI_REG_BASE_OFFS + 0x00001a78) +#define HWIO_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_RMSK 0xffff +#define HWIO_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_ATTR 0x1 +#define HWIO_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_IN \ + in_dword_masked(HWIO_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_ADDR, HWIO_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_RMSK) +#define HWIO_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_INM(m) \ + in_dword_masked(HWIO_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_ADDR, m) +#define HWIO_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_MCS_IDLE_CNT_MSB_BMSK 0xffff +#define HWIO_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_MCS_IDLE_CNT_MSB_SHFT 0x0 + +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_ADDR(n,k) (GSI_REG_BASE + 0x00014000 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x00014000 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x00014000 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_MAXk 27 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_CNTXT_0_ADDR(n,k), HWIO_EE_n_GSI_CH_k_CNTXT_0_RMSK) +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_CNTXT_0_ADDR(n,k), mask) +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_GSI_CH_k_CNTXT_0_ADDR(n,k),val) +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_GSI_CH_k_CNTXT_0_ADDR(n,k),mask,val,HWIO_EE_n_GSI_CH_k_CNTXT_0_INI2(n,k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_ELEMENT_SIZE_BMSK 0xff000000 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_ELEMENT_SIZE_SHFT 0x18 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_BMSK 0xf00000 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_SHFT 0x14 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_NOT_ALLOCATED_FVAL 0x0 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_ALLOCATED_FVAL 0x1 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_STARTED_FVAL 0x2 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_STOPED_FVAL 0x3 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_STOP_IN_PROC_FVAL 0x4 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_ERROR_FVAL 0xf +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHID_BMSK 0xff000 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHID_SHFT 0xc +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_EE_BMSK 0xf00 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_EE_SHFT 0x8 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_DIR_BMSK 0x80 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_DIR_SHFT 0x7 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_DIR_INBOUND_FVAL 0x0 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_DIR_OUTBOUND_FVAL 0x1 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_BMSK 0x7f +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_SHFT 0x0 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_MHI_FVAL 0x0 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_XHCI_FVAL 0x1 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_GPI_FVAL 0x2 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_XDCI_FVAL 0x3 + +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_ADDR(n,k) (GSI_REG_BASE + 0x00014004 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x00014004 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x00014004 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_MAXk 27 +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_CNTXT_1_ADDR(n,k), HWIO_EE_n_GSI_CH_k_CNTXT_1_RMSK) +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_CNTXT_1_ADDR(n,k), mask) +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_GSI_CH_k_CNTXT_1_ADDR(n,k),val) +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_GSI_CH_k_CNTXT_1_ADDR(n,k),mask,val,HWIO_EE_n_GSI_CH_k_CNTXT_1_INI2(n,k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_ERINDEX_BMSK 0xff000000 +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_ERINDEX_SHFT 0x18 +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_R_LENGTH_BMSK 0xffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_R_LENGTH_SHFT 0x0 + +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_ADDR(n,k) (GSI_REG_BASE + 0x00014008 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x00014008 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x00014008 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_MAXk 27 +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_CNTXT_2_ADDR(n,k), HWIO_EE_n_GSI_CH_k_CNTXT_2_RMSK) +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_CNTXT_2_ADDR(n,k), mask) +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_GSI_CH_k_CNTXT_2_ADDR(n,k),val) +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_GSI_CH_k_CNTXT_2_ADDR(n,k),mask,val,HWIO_EE_n_GSI_CH_k_CNTXT_2_INI2(n,k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_R_BASE_ADDR_LSBS_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_R_BASE_ADDR_LSBS_SHFT 0x0 + +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_ADDR(n,k) (GSI_REG_BASE + 0x0001400c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x0001400c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x0001400c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_MAXk 27 +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_CNTXT_3_ADDR(n,k), HWIO_EE_n_GSI_CH_k_CNTXT_3_RMSK) +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_CNTXT_3_ADDR(n,k), mask) +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_GSI_CH_k_CNTXT_3_ADDR(n,k),val) +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_GSI_CH_k_CNTXT_3_ADDR(n,k),mask,val,HWIO_EE_n_GSI_CH_k_CNTXT_3_INI2(n,k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_R_BASE_ADDR_MSBS_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_R_BASE_ADDR_MSBS_SHFT 0x0 + +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_ADDR(n,k) (GSI_REG_BASE + 0x00014010 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x00014010 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x00014010 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_MAXk 27 +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_CNTXT_4_ADDR(n,k), HWIO_EE_n_GSI_CH_k_CNTXT_4_RMSK) +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_CNTXT_4_ADDR(n,k), mask) +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_GSI_CH_k_CNTXT_4_ADDR(n,k),val) +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_GSI_CH_k_CNTXT_4_ADDR(n,k),mask,val,HWIO_EE_n_GSI_CH_k_CNTXT_4_INI2(n,k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_READ_PTR_LSB_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_READ_PTR_LSB_SHFT 0x0 + +#define HWIO_EE_n_GSI_CH_k_CNTXT_5_ADDR(n,k) (GSI_REG_BASE + 0x00014014 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_5_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x00014014 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_5_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x00014014 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_5_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_5_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_CNTXT_5_MAXk 27 +#define HWIO_EE_n_GSI_CH_k_CNTXT_5_ATTR 0x1 +#define HWIO_EE_n_GSI_CH_k_CNTXT_5_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_CNTXT_5_ADDR(n,k), HWIO_EE_n_GSI_CH_k_CNTXT_5_RMSK) +#define HWIO_EE_n_GSI_CH_k_CNTXT_5_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_CNTXT_5_ADDR(n,k), mask) +#define HWIO_EE_n_GSI_CH_k_CNTXT_5_READ_PTR_MSB_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_5_READ_PTR_MSB_SHFT 0x0 + +#define HWIO_EE_n_GSI_CH_k_CNTXT_6_ADDR(n,k) (GSI_REG_BASE + 0x00014018 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_6_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x00014018 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_6_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x00014018 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_6_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_6_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_CNTXT_6_MAXk 27 +#define HWIO_EE_n_GSI_CH_k_CNTXT_6_ATTR 0x1 +#define HWIO_EE_n_GSI_CH_k_CNTXT_6_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_CNTXT_6_ADDR(n,k), HWIO_EE_n_GSI_CH_k_CNTXT_6_RMSK) +#define HWIO_EE_n_GSI_CH_k_CNTXT_6_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_CNTXT_6_ADDR(n,k), mask) +#define HWIO_EE_n_GSI_CH_k_CNTXT_6_WRITE_PTR_LSB_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_6_WRITE_PTR_LSB_SHFT 0x0 + +#define HWIO_EE_n_GSI_CH_k_CNTXT_7_ADDR(n,k) (GSI_REG_BASE + 0x0001401c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_7_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x0001401c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_7_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x0001401c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_7_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_7_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_CNTXT_7_MAXk 27 +#define HWIO_EE_n_GSI_CH_k_CNTXT_7_ATTR 0x1 +#define HWIO_EE_n_GSI_CH_k_CNTXT_7_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_CNTXT_7_ADDR(n,k), HWIO_EE_n_GSI_CH_k_CNTXT_7_RMSK) +#define HWIO_EE_n_GSI_CH_k_CNTXT_7_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_CNTXT_7_ADDR(n,k), mask) +#define HWIO_EE_n_GSI_CH_k_CNTXT_7_WRITE_PTR_MSB_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_7_WRITE_PTR_MSB_SHFT 0x0 + +#define HWIO_EE_n_GSI_CH_k_CNTXT_8_ADDR(n,k) (GSI_REG_BASE + 0x00014020 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_8_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x00014020 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_8_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x00014020 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_8_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_8_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_CNTXT_8_MAXk 27 +#define HWIO_EE_n_GSI_CH_k_CNTXT_8_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_CNTXT_8_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_CNTXT_8_ADDR(n,k), HWIO_EE_n_GSI_CH_k_CNTXT_8_RMSK) +#define HWIO_EE_n_GSI_CH_k_CNTXT_8_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_CNTXT_8_ADDR(n,k), mask) +#define HWIO_EE_n_GSI_CH_k_CNTXT_8_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_GSI_CH_k_CNTXT_8_ADDR(n,k),val) +#define HWIO_EE_n_GSI_CH_k_CNTXT_8_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_GSI_CH_k_CNTXT_8_ADDR(n,k),mask,val,HWIO_EE_n_GSI_CH_k_CNTXT_8_INI2(n,k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_8_DB_MSI_DATA_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_8_DB_MSI_DATA_SHFT 0x0 + +#define HWIO_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_ADDR(n,k) (GSI_REG_BASE + 0x00014024 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x00014024 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x00014024 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_RMSK 0xf +#define HWIO_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_MAXk 27 +#define HWIO_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_ATTR 0x1 +#define HWIO_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_ADDR(n,k), HWIO_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_RMSK) +#define HWIO_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_ADDR(n,k), mask) +#define HWIO_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_ELEM_SIZE_SHIFT_BMSK 0xf +#define HWIO_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_ELEM_SIZE_SHIFT_SHFT 0x0 +#define HWIO_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_ELEM_SIZE_SHIFT_TWO_FVAL 0x0 +#define HWIO_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_ELEM_SIZE_SHIFT_THREE_FVAL 0x1 +#define HWIO_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_ELEM_SIZE_SHIFT_FOUR_FVAL 0x2 +#define HWIO_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_ELEM_SIZE_SHIFT_FIVE_FVAL 0x3 +#define HWIO_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_ELEM_SIZE_SHIFT_SIX_FVAL 0x4 + +#define HWIO_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_ADDR(n,k) (GSI_REG_BASE + 0x00014028 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x00014028 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x00014028 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_RMSK 0xffff +#define HWIO_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_MAXk 27 +#define HWIO_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_ADDR(n,k), HWIO_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_RMSK) +#define HWIO_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_ADDR(n,k), mask) +#define HWIO_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_ADDR(n,k),val) +#define HWIO_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_ADDR(n,k),mask,val,HWIO_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_INI2(n,k)) +#define HWIO_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_CH_ALMST_EMPTY_THRSHOLD_BMSK 0xffff +#define HWIO_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_CH_ALMST_EMPTY_THRSHOLD_SHFT 0x0 + +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_ADDR(n,k) (GSI_REG_BASE + 0x00014040 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x00014040 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x00014040 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_RMSK 0xffffff +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_MAXk 27 +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_ADDR(n,k), HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_RMSK) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_ADDR(n,k), mask) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_ADDR(n,k),val) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_ADDR(n,k),mask,val,HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_INI2(n,k)) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_READ_PTR_BMSK 0xffffff +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_READ_PTR_SHFT 0x0 + +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_ADDR(n,k) (GSI_REG_BASE + 0x00014044 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x00014044 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x00014044 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_RMSK 0xffffff +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_MAXk 27 +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_ADDR(n,k), HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_RMSK) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_ADDR(n,k), mask) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_ADDR(n,k),val) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_ADDR(n,k),mask,val,HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_INI2(n,k)) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_RE_INTR_DB_BMSK 0xffffff +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_RE_INTR_DB_SHFT 0x0 + +#define HWIO_EE_n_GSI_CH_k_QOS_ADDR(n,k) (GSI_REG_BASE + 0x00014048 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_QOS_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x00014048 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_QOS_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x00014048 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_QOS_RMSK 0x3ff3f0f +#define HWIO_EE_n_GSI_CH_k_QOS_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_QOS_MAXk 27 +#define HWIO_EE_n_GSI_CH_k_QOS_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_QOS_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_QOS_ADDR(n,k), HWIO_EE_n_GSI_CH_k_QOS_RMSK) +#define HWIO_EE_n_GSI_CH_k_QOS_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_QOS_ADDR(n,k), mask) +#define HWIO_EE_n_GSI_CH_k_QOS_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_GSI_CH_k_QOS_ADDR(n,k),val) +#define HWIO_EE_n_GSI_CH_k_QOS_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_GSI_CH_k_QOS_ADDR(n,k),mask,val,HWIO_EE_n_GSI_CH_k_QOS_INI2(n,k)) +#define HWIO_EE_n_GSI_CH_k_QOS_LOW_LATENCY_EN_BMSK 0x2000000 +#define HWIO_EE_n_GSI_CH_k_QOS_LOW_LATENCY_EN_SHFT 0x19 +#define HWIO_EE_n_GSI_CH_k_QOS_DB_IN_BYTES_BMSK 0x1000000 +#define HWIO_EE_n_GSI_CH_k_QOS_DB_IN_BYTES_SHFT 0x18 +#define HWIO_EE_n_GSI_CH_k_QOS_EMPTY_LVL_THRSHOLD_BMSK 0xff0000 +#define HWIO_EE_n_GSI_CH_k_QOS_EMPTY_LVL_THRSHOLD_SHFT 0x10 +#define HWIO_EE_n_GSI_CH_k_QOS_PREFETCH_MODE_BMSK 0x3c00 +#define HWIO_EE_n_GSI_CH_k_QOS_PREFETCH_MODE_SHFT 0xa +#define HWIO_EE_n_GSI_CH_k_QOS_PREFETCH_MODE_USE_PREFETCH_BUFS_FVAL 0x0 +#define HWIO_EE_n_GSI_CH_k_QOS_PREFETCH_MODE_ESCAPE_BUF_ONLY_FVAL 0x1 +#define HWIO_EE_n_GSI_CH_k_QOS_PREFETCH_MODE_SMART_PRE_FETCH_FVAL 0x2 +#define HWIO_EE_n_GSI_CH_k_QOS_PREFETCH_MODE_FREE_PRE_FETCH_FVAL 0x3 +#define HWIO_EE_n_GSI_CH_k_QOS_USE_DB_ENG_BMSK 0x200 +#define HWIO_EE_n_GSI_CH_k_QOS_USE_DB_ENG_SHFT 0x9 +#define HWIO_EE_n_GSI_CH_k_QOS_MAX_PREFETCH_BMSK 0x100 +#define HWIO_EE_n_GSI_CH_k_QOS_MAX_PREFETCH_SHFT 0x8 +#define HWIO_EE_n_GSI_CH_k_QOS_MAX_PREFETCH_ONE_PREFETCH_SEG_FVAL 0x0 +#define HWIO_EE_n_GSI_CH_k_QOS_MAX_PREFETCH_TWO_PREFETCH_SEG_FVAL 0x1 +#define HWIO_EE_n_GSI_CH_k_QOS_WRR_WEIGHT_BMSK 0xf +#define HWIO_EE_n_GSI_CH_k_QOS_WRR_WEIGHT_SHFT 0x0 + +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_ADDR(n,k) (GSI_REG_BASE + 0x0001404c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x0001404c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x0001404c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_MAXk 27 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_SCRATCH_0_ADDR(n,k), HWIO_EE_n_GSI_CH_k_SCRATCH_0_RMSK) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_SCRATCH_0_ADDR(n,k), mask) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_GSI_CH_k_SCRATCH_0_ADDR(n,k),val) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_GSI_CH_k_SCRATCH_0_ADDR(n,k),mask,val,HWIO_EE_n_GSI_CH_k_SCRATCH_0_INI2(n,k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_SCRATCH_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_SCRATCH_SHFT 0x0 + +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_ADDR(n,k) (GSI_REG_BASE + 0x00014050 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x00014050 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x00014050 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_MAXk 27 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_SCRATCH_1_ADDR(n,k), HWIO_EE_n_GSI_CH_k_SCRATCH_1_RMSK) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_SCRATCH_1_ADDR(n,k), mask) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_GSI_CH_k_SCRATCH_1_ADDR(n,k),val) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_GSI_CH_k_SCRATCH_1_ADDR(n,k),mask,val,HWIO_EE_n_GSI_CH_k_SCRATCH_1_INI2(n,k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_SCRATCH_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_SCRATCH_SHFT 0x0 + +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_ADDR(n,k) (GSI_REG_BASE + 0x00014054 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x00014054 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x00014054 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_MAXk 27 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_SCRATCH_2_ADDR(n,k), HWIO_EE_n_GSI_CH_k_SCRATCH_2_RMSK) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_SCRATCH_2_ADDR(n,k), mask) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_GSI_CH_k_SCRATCH_2_ADDR(n,k),val) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_GSI_CH_k_SCRATCH_2_ADDR(n,k),mask,val,HWIO_EE_n_GSI_CH_k_SCRATCH_2_INI2(n,k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_SCRATCH_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_SCRATCH_SHFT 0x0 + +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_ADDR(n,k) (GSI_REG_BASE + 0x00014058 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x00014058 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x00014058 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_MAXk 27 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_SCRATCH_3_ADDR(n,k), HWIO_EE_n_GSI_CH_k_SCRATCH_3_RMSK) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_SCRATCH_3_ADDR(n,k), mask) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_GSI_CH_k_SCRATCH_3_ADDR(n,k),val) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_GSI_CH_k_SCRATCH_3_ADDR(n,k),mask,val,HWIO_EE_n_GSI_CH_k_SCRATCH_3_INI2(n,k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_SCRATCH_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_SCRATCH_SHFT 0x0 + +#define HWIO_EE_n_GSI_CH_k_SCRATCH_4_ADDR(n,k) (GSI_REG_BASE + 0x0001405c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_4_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x0001405c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_4_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x0001405c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_4_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_4_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_4_MAXk 27 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_4_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_4_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_SCRATCH_4_ADDR(n,k), HWIO_EE_n_GSI_CH_k_SCRATCH_4_RMSK) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_4_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_SCRATCH_4_ADDR(n,k), mask) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_4_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_GSI_CH_k_SCRATCH_4_ADDR(n,k),val) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_4_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_GSI_CH_k_SCRATCH_4_ADDR(n,k),mask,val,HWIO_EE_n_GSI_CH_k_SCRATCH_4_INI2(n,k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_4_SCRATCH_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_4_SCRATCH_SHFT 0x0 + +#define HWIO_EE_n_GSI_CH_k_SCRATCH_5_ADDR(n,k) (GSI_REG_BASE + 0x00014060 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_5_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x00014060 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_5_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x00014060 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_5_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_5_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_5_MAXk 27 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_5_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_5_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_SCRATCH_5_ADDR(n,k), HWIO_EE_n_GSI_CH_k_SCRATCH_5_RMSK) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_5_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_SCRATCH_5_ADDR(n,k), mask) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_5_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_GSI_CH_k_SCRATCH_5_ADDR(n,k),val) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_5_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_GSI_CH_k_SCRATCH_5_ADDR(n,k),mask,val,HWIO_EE_n_GSI_CH_k_SCRATCH_5_INI2(n,k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_5_SCRATCH_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_5_SCRATCH_SHFT 0x0 + +#define HWIO_EE_n_GSI_CH_k_SCRATCH_6_ADDR(n,k) (GSI_REG_BASE + 0x00014064 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_6_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x00014064 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_6_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x00014064 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_6_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_6_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_6_MAXk 27 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_6_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_6_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_SCRATCH_6_ADDR(n,k), HWIO_EE_n_GSI_CH_k_SCRATCH_6_RMSK) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_6_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_SCRATCH_6_ADDR(n,k), mask) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_6_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_GSI_CH_k_SCRATCH_6_ADDR(n,k),val) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_6_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_GSI_CH_k_SCRATCH_6_ADDR(n,k),mask,val,HWIO_EE_n_GSI_CH_k_SCRATCH_6_INI2(n,k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_6_SCRATCH_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_6_SCRATCH_SHFT 0x0 + +#define HWIO_EE_n_GSI_CH_k_SCRATCH_7_ADDR(n,k) (GSI_REG_BASE + 0x00014068 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_7_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x00014068 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_7_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x00014068 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_7_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_7_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_7_MAXk 27 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_7_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_7_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_SCRATCH_7_ADDR(n,k), HWIO_EE_n_GSI_CH_k_SCRATCH_7_RMSK) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_7_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_SCRATCH_7_ADDR(n,k), mask) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_7_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_GSI_CH_k_SCRATCH_7_ADDR(n,k),val) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_7_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_GSI_CH_k_SCRATCH_7_ADDR(n,k),mask,val,HWIO_EE_n_GSI_CH_k_SCRATCH_7_INI2(n,k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_7_SCRATCH_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_7_SCRATCH_SHFT 0x0 + +#define HWIO_EE_n_GSI_CH_k_SCRATCH_8_ADDR(n,k) (GSI_REG_BASE + 0x0001406c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_8_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x0001406c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_8_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x0001406c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_8_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_8_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_8_MAXk 27 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_8_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_8_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_SCRATCH_8_ADDR(n,k), HWIO_EE_n_GSI_CH_k_SCRATCH_8_RMSK) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_8_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_SCRATCH_8_ADDR(n,k), mask) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_8_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_GSI_CH_k_SCRATCH_8_ADDR(n,k),val) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_8_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_GSI_CH_k_SCRATCH_8_ADDR(n,k),mask,val,HWIO_EE_n_GSI_CH_k_SCRATCH_8_INI2(n,k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_8_SCRATCH_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_8_SCRATCH_SHFT 0x0 + +#define HWIO_EE_n_GSI_CH_k_SCRATCH_9_ADDR(n,k) (GSI_REG_BASE + 0x00014070 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_9_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x00014070 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_9_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x00014070 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_9_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_9_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_9_MAXk 27 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_9_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_9_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_SCRATCH_9_ADDR(n,k), HWIO_EE_n_GSI_CH_k_SCRATCH_9_RMSK) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_9_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_SCRATCH_9_ADDR(n,k), mask) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_9_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_GSI_CH_k_SCRATCH_9_ADDR(n,k),val) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_9_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_GSI_CH_k_SCRATCH_9_ADDR(n,k),mask,val,HWIO_EE_n_GSI_CH_k_SCRATCH_9_INI2(n,k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_9_SCRATCH_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_9_SCRATCH_SHFT 0x0 + +#define HWIO_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_ADDR(n,k) (GSI_REG_BASE + 0x00014074 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x00014074 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x00014074 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_RMSK 0xffff +#define HWIO_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_MAXk 27 +#define HWIO_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_ADDR(n,k), HWIO_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_RMSK) +#define HWIO_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_ADDR(n,k), mask) +#define HWIO_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_ADDR(n,k),val) +#define HWIO_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_ADDR(n,k),mask,val,HWIO_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_INI2(n,k)) +#define HWIO_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_LAST_DB_2_MCS_BMSK 0xffff +#define HWIO_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_LAST_DB_2_MCS_SHFT 0x0 + +#define HWIO_EE_n_EV_CH_k_CNTXT_0_ADDR(n,k) (GSI_REG_BASE + 0x0001c000 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_0_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x0001c000 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_0_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x0001c000 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_0_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_0_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_MAXk 26 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_CNTXT_0_ADDR(n,k), HWIO_EE_n_EV_CH_k_CNTXT_0_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_0_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_CNTXT_0_ADDR(n,k), mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_0_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_EV_CH_k_CNTXT_0_ADDR(n,k),val) +#define HWIO_EE_n_EV_CH_k_CNTXT_0_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_EV_CH_k_CNTXT_0_ADDR(n,k),mask,val,HWIO_EE_n_EV_CH_k_CNTXT_0_INI2(n,k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_0_ELEMENT_SIZE_BMSK 0xff000000 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_ELEMENT_SIZE_SHFT 0x18 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_CHSTATE_BMSK 0xf00000 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_CHSTATE_SHFT 0x14 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_CHSTATE_NOT_ALLOCATED_FVAL 0x0 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_CHSTATE_ALLOCATED_FVAL 0x1 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_EE_BMSK 0xf0000 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_EE_SHFT 0x10 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_EVCHID_BMSK 0xff00 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_EVCHID_SHFT 0x8 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_INTYPE_BMSK 0x80 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_INTYPE_SHFT 0x7 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_INTYPE_MSI_FVAL 0x0 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_INTYPE_IRQ_FVAL 0x1 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_CHTYPE_BMSK 0x7f +#define HWIO_EE_n_EV_CH_k_CNTXT_0_CHTYPE_SHFT 0x0 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_CHTYPE_MHI_EV_FVAL 0x0 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_CHTYPE_XHCI_EV_FVAL 0x1 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_CHTYPE_GPI_EV_FVAL 0x2 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_CHTYPE_XDCI_FVAL 0x3 + +#define HWIO_EE_n_EV_CH_k_CNTXT_1_ADDR(n,k) (GSI_REG_BASE + 0x0001c004 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_1_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x0001c004 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_1_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x0001c004 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_1_RMSK 0xffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_1_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_1_MAXk 26 +#define HWIO_EE_n_EV_CH_k_CNTXT_1_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_CNTXT_1_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_CNTXT_1_ADDR(n,k), HWIO_EE_n_EV_CH_k_CNTXT_1_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_1_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_CNTXT_1_ADDR(n,k), mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_1_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_EV_CH_k_CNTXT_1_ADDR(n,k),val) +#define HWIO_EE_n_EV_CH_k_CNTXT_1_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_EV_CH_k_CNTXT_1_ADDR(n,k),mask,val,HWIO_EE_n_EV_CH_k_CNTXT_1_INI2(n,k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_1_R_LENGTH_BMSK 0xffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_1_R_LENGTH_SHFT 0x0 + +#define HWIO_EE_n_EV_CH_k_CNTXT_2_ADDR(n,k) (GSI_REG_BASE + 0x0001c008 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_2_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x0001c008 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_2_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x0001c008 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_2_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_2_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_2_MAXk 26 +#define HWIO_EE_n_EV_CH_k_CNTXT_2_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_CNTXT_2_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_CNTXT_2_ADDR(n,k), HWIO_EE_n_EV_CH_k_CNTXT_2_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_2_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_CNTXT_2_ADDR(n,k), mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_2_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_EV_CH_k_CNTXT_2_ADDR(n,k),val) +#define HWIO_EE_n_EV_CH_k_CNTXT_2_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_EV_CH_k_CNTXT_2_ADDR(n,k),mask,val,HWIO_EE_n_EV_CH_k_CNTXT_2_INI2(n,k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_2_R_BASE_ADDR_LSBS_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_2_R_BASE_ADDR_LSBS_SHFT 0x0 + +#define HWIO_EE_n_EV_CH_k_CNTXT_3_ADDR(n,k) (GSI_REG_BASE + 0x0001c00c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_3_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x0001c00c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_3_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x0001c00c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_3_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_3_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_3_MAXk 26 +#define HWIO_EE_n_EV_CH_k_CNTXT_3_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_CNTXT_3_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_CNTXT_3_ADDR(n,k), HWIO_EE_n_EV_CH_k_CNTXT_3_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_3_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_CNTXT_3_ADDR(n,k), mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_3_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_EV_CH_k_CNTXT_3_ADDR(n,k),val) +#define HWIO_EE_n_EV_CH_k_CNTXT_3_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_EV_CH_k_CNTXT_3_ADDR(n,k),mask,val,HWIO_EE_n_EV_CH_k_CNTXT_3_INI2(n,k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_3_R_BASE_ADDR_MSBS_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_3_R_BASE_ADDR_MSBS_SHFT 0x0 + +#define HWIO_EE_n_EV_CH_k_CNTXT_4_ADDR(n,k) (GSI_REG_BASE + 0x0001c010 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_4_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x0001c010 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_4_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x0001c010 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_4_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_4_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_4_MAXk 26 +#define HWIO_EE_n_EV_CH_k_CNTXT_4_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_CNTXT_4_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_CNTXT_4_ADDR(n,k), HWIO_EE_n_EV_CH_k_CNTXT_4_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_4_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_CNTXT_4_ADDR(n,k), mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_4_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_EV_CH_k_CNTXT_4_ADDR(n,k),val) +#define HWIO_EE_n_EV_CH_k_CNTXT_4_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_EV_CH_k_CNTXT_4_ADDR(n,k),mask,val,HWIO_EE_n_EV_CH_k_CNTXT_4_INI2(n,k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_4_READ_PTR_LSB_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_4_READ_PTR_LSB_SHFT 0x0 + +#define HWIO_EE_n_EV_CH_k_CNTXT_5_ADDR(n,k) (GSI_REG_BASE + 0x0001c014 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_5_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x0001c014 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_5_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x0001c014 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_5_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_5_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_5_MAXk 26 +#define HWIO_EE_n_EV_CH_k_CNTXT_5_ATTR 0x1 +#define HWIO_EE_n_EV_CH_k_CNTXT_5_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_CNTXT_5_ADDR(n,k), HWIO_EE_n_EV_CH_k_CNTXT_5_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_5_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_CNTXT_5_ADDR(n,k), mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_5_READ_PTR_MSB_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_5_READ_PTR_MSB_SHFT 0x0 + +#define HWIO_EE_n_EV_CH_k_CNTXT_6_ADDR(n,k) (GSI_REG_BASE + 0x0001c018 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_6_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x0001c018 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_6_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x0001c018 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_6_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_6_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_6_MAXk 26 +#define HWIO_EE_n_EV_CH_k_CNTXT_6_ATTR 0x1 +#define HWIO_EE_n_EV_CH_k_CNTXT_6_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_CNTXT_6_ADDR(n,k), HWIO_EE_n_EV_CH_k_CNTXT_6_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_6_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_CNTXT_6_ADDR(n,k), mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_6_WRITE_PTR_LSB_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_6_WRITE_PTR_LSB_SHFT 0x0 + +#define HWIO_EE_n_EV_CH_k_CNTXT_7_ADDR(n,k) (GSI_REG_BASE + 0x0001c01c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_7_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x0001c01c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_7_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x0001c01c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_7_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_7_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_7_MAXk 26 +#define HWIO_EE_n_EV_CH_k_CNTXT_7_ATTR 0x1 +#define HWIO_EE_n_EV_CH_k_CNTXT_7_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_CNTXT_7_ADDR(n,k), HWIO_EE_n_EV_CH_k_CNTXT_7_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_7_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_CNTXT_7_ADDR(n,k), mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_7_WRITE_PTR_MSB_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_7_WRITE_PTR_MSB_SHFT 0x0 + +#define HWIO_EE_n_EV_CH_k_CNTXT_8_ADDR(n,k) (GSI_REG_BASE + 0x0001c020 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_8_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x0001c020 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_8_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x0001c020 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_8_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_8_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_8_MAXk 26 +#define HWIO_EE_n_EV_CH_k_CNTXT_8_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_CNTXT_8_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_CNTXT_8_ADDR(n,k), HWIO_EE_n_EV_CH_k_CNTXT_8_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_8_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_CNTXT_8_ADDR(n,k), mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_8_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_EV_CH_k_CNTXT_8_ADDR(n,k),val) +#define HWIO_EE_n_EV_CH_k_CNTXT_8_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_EV_CH_k_CNTXT_8_ADDR(n,k),mask,val,HWIO_EE_n_EV_CH_k_CNTXT_8_INI2(n,k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_8_INT_MOD_CNT_BMSK 0xff000000 +#define HWIO_EE_n_EV_CH_k_CNTXT_8_INT_MOD_CNT_SHFT 0x18 +#define HWIO_EE_n_EV_CH_k_CNTXT_8_INT_MODC_BMSK 0xff0000 +#define HWIO_EE_n_EV_CH_k_CNTXT_8_INT_MODC_SHFT 0x10 +#define HWIO_EE_n_EV_CH_k_CNTXT_8_INT_MODT_BMSK 0xffff +#define HWIO_EE_n_EV_CH_k_CNTXT_8_INT_MODT_SHFT 0x0 + +#define HWIO_EE_n_EV_CH_k_CNTXT_9_ADDR(n,k) (GSI_REG_BASE + 0x0001c024 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_9_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x0001c024 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_9_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x0001c024 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_9_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_9_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_9_MAXk 26 +#define HWIO_EE_n_EV_CH_k_CNTXT_9_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_CNTXT_9_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_CNTXT_9_ADDR(n,k), HWIO_EE_n_EV_CH_k_CNTXT_9_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_9_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_CNTXT_9_ADDR(n,k), mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_9_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_EV_CH_k_CNTXT_9_ADDR(n,k),val) +#define HWIO_EE_n_EV_CH_k_CNTXT_9_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_EV_CH_k_CNTXT_9_ADDR(n,k),mask,val,HWIO_EE_n_EV_CH_k_CNTXT_9_INI2(n,k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_9_INTVEC_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_9_INTVEC_SHFT 0x0 + +#define HWIO_EE_n_EV_CH_k_CNTXT_10_ADDR(n,k) (GSI_REG_BASE + 0x0001c028 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_10_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x0001c028 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_10_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x0001c028 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_10_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_10_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_10_MAXk 26 +#define HWIO_EE_n_EV_CH_k_CNTXT_10_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_CNTXT_10_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_CNTXT_10_ADDR(n,k), HWIO_EE_n_EV_CH_k_CNTXT_10_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_10_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_CNTXT_10_ADDR(n,k), mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_10_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_EV_CH_k_CNTXT_10_ADDR(n,k),val) +#define HWIO_EE_n_EV_CH_k_CNTXT_10_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_EV_CH_k_CNTXT_10_ADDR(n,k),mask,val,HWIO_EE_n_EV_CH_k_CNTXT_10_INI2(n,k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_10_MSI_ADDR_LSB_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_10_MSI_ADDR_LSB_SHFT 0x0 + +#define HWIO_EE_n_EV_CH_k_CNTXT_11_ADDR(n,k) (GSI_REG_BASE + 0x0001c02c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_11_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x0001c02c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_11_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x0001c02c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_11_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_11_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_11_MAXk 26 +#define HWIO_EE_n_EV_CH_k_CNTXT_11_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_CNTXT_11_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_CNTXT_11_ADDR(n,k), HWIO_EE_n_EV_CH_k_CNTXT_11_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_11_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_CNTXT_11_ADDR(n,k), mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_11_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_EV_CH_k_CNTXT_11_ADDR(n,k),val) +#define HWIO_EE_n_EV_CH_k_CNTXT_11_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_EV_CH_k_CNTXT_11_ADDR(n,k),mask,val,HWIO_EE_n_EV_CH_k_CNTXT_11_INI2(n,k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_11_MSI_ADDR_MSB_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_11_MSI_ADDR_MSB_SHFT 0x0 + +#define HWIO_EE_n_EV_CH_k_CNTXT_12_ADDR(n,k) (GSI_REG_BASE + 0x0001c030 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_12_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x0001c030 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_12_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x0001c030 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_12_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_12_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_12_MAXk 26 +#define HWIO_EE_n_EV_CH_k_CNTXT_12_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_CNTXT_12_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_CNTXT_12_ADDR(n,k), HWIO_EE_n_EV_CH_k_CNTXT_12_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_12_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_CNTXT_12_ADDR(n,k), mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_12_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_EV_CH_k_CNTXT_12_ADDR(n,k),val) +#define HWIO_EE_n_EV_CH_k_CNTXT_12_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_EV_CH_k_CNTXT_12_ADDR(n,k),mask,val,HWIO_EE_n_EV_CH_k_CNTXT_12_INI2(n,k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_12_RP_UPDATE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_12_RP_UPDATE_ADDR_LSB_SHFT 0x0 + +#define HWIO_EE_n_EV_CH_k_CNTXT_13_ADDR(n,k) (GSI_REG_BASE + 0x0001c034 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_13_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x0001c034 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_13_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x0001c034 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_13_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_13_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_13_MAXk 26 +#define HWIO_EE_n_EV_CH_k_CNTXT_13_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_CNTXT_13_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_CNTXT_13_ADDR(n,k), HWIO_EE_n_EV_CH_k_CNTXT_13_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_13_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_CNTXT_13_ADDR(n,k), mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_13_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_EV_CH_k_CNTXT_13_ADDR(n,k),val) +#define HWIO_EE_n_EV_CH_k_CNTXT_13_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_EV_CH_k_CNTXT_13_ADDR(n,k),mask,val,HWIO_EE_n_EV_CH_k_CNTXT_13_INI2(n,k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_13_RP_UPDATE_ADDR_MSB_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_13_RP_UPDATE_ADDR_MSB_SHFT 0x0 + +#define HWIO_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_ADDR(n,k) (GSI_REG_BASE + 0x0001c038 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x0001c038 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x0001c038 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_RMSK 0xf +#define HWIO_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_MAXn 2 +#define HWIO_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_MAXk 26 +#define HWIO_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_ATTR 0x1 +#define HWIO_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_ADDR(n,k), HWIO_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_RMSK) +#define HWIO_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_ADDR(n,k), mask) +#define HWIO_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_ELEM_SIZE_SHIFT_BMSK 0xf +#define HWIO_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_ELEM_SIZE_SHIFT_SHFT 0x0 +#define HWIO_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_ELEM_SIZE_SHIFT_TWO_FVAL 0x0 +#define HWIO_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_ELEM_SIZE_SHIFT_THREE_FVAL 0x1 +#define HWIO_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_ELEM_SIZE_SHIFT_FOUR_FVAL 0x2 +#define HWIO_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_ELEM_SIZE_SHIFT_FIVE_FVAL 0x3 +#define HWIO_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_ELEM_SIZE_SHIFT_SIX_FVAL 0x4 + +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_ADDR(n,k) (GSI_REG_BASE + 0x0001c048 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x0001c048 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x0001c048 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_MAXn 2 +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_MAXk 26 +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_SCRATCH_0_ADDR(n,k), HWIO_EE_n_EV_CH_k_SCRATCH_0_RMSK) +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_SCRATCH_0_ADDR(n,k), mask) +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_EV_CH_k_SCRATCH_0_ADDR(n,k),val) +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_EV_CH_k_SCRATCH_0_ADDR(n,k),mask,val,HWIO_EE_n_EV_CH_k_SCRATCH_0_INI2(n,k)) +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_SCRATCH_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_SCRATCH_SHFT 0x0 + +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_ADDR(n,k) (GSI_REG_BASE + 0x0001c04c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x0001c04c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x0001c04c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_MAXn 2 +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_MAXk 26 +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_SCRATCH_1_ADDR(n,k), HWIO_EE_n_EV_CH_k_SCRATCH_1_RMSK) +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_SCRATCH_1_ADDR(n,k), mask) +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_EV_CH_k_SCRATCH_1_ADDR(n,k),val) +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_EV_CH_k_SCRATCH_1_ADDR(n,k),mask,val,HWIO_EE_n_EV_CH_k_SCRATCH_1_INI2(n,k)) +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_SCRATCH_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_SCRATCH_SHFT 0x0 + +#define HWIO_EE_n_EV_CH_k_SCRATCH_2_ADDR(n,k) (GSI_REG_BASE + 0x0001c050 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_SCRATCH_2_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x0001c050 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_SCRATCH_2_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x0001c050 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_SCRATCH_2_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_SCRATCH_2_MAXn 2 +#define HWIO_EE_n_EV_CH_k_SCRATCH_2_MAXk 26 +#define HWIO_EE_n_EV_CH_k_SCRATCH_2_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_SCRATCH_2_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_SCRATCH_2_ADDR(n,k), HWIO_EE_n_EV_CH_k_SCRATCH_2_RMSK) +#define HWIO_EE_n_EV_CH_k_SCRATCH_2_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_EV_CH_k_SCRATCH_2_ADDR(n,k), mask) +#define HWIO_EE_n_EV_CH_k_SCRATCH_2_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_EV_CH_k_SCRATCH_2_ADDR(n,k),val) +#define HWIO_EE_n_EV_CH_k_SCRATCH_2_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_EV_CH_k_SCRATCH_2_ADDR(n,k),mask,val,HWIO_EE_n_EV_CH_k_SCRATCH_2_INI2(n,k)) +#define HWIO_EE_n_EV_CH_k_SCRATCH_2_SCRATCH_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_SCRATCH_2_SCRATCH_SHFT 0x0 + +#define HWIO_EE_n_GSI_CH_k_DOORBELL_0_ADDR(n,k) (GSI_REG_BASE + 0x00024000 + 0x12000 * (n) + 0x8 * (k)) +#define HWIO_EE_n_GSI_CH_k_DOORBELL_0_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x00024000 + 0x12000 * (n) + 0x8 * (k)) +#define HWIO_EE_n_GSI_CH_k_DOORBELL_0_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x00024000 + 0x12000 * (n) + 0x8 * (k)) +#define HWIO_EE_n_GSI_CH_k_DOORBELL_0_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_DOORBELL_0_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_DOORBELL_0_MAXk 27 +#define HWIO_EE_n_GSI_CH_k_DOORBELL_0_ATTR 0x2 +#define HWIO_EE_n_GSI_CH_k_DOORBELL_0_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_GSI_CH_k_DOORBELL_0_ADDR(n,k),val) +#define HWIO_EE_n_GSI_CH_k_DOORBELL_0_WRITE_PTR_LSB_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_DOORBELL_0_WRITE_PTR_LSB_SHFT 0x0 + +#define HWIO_EE_n_GSI_CH_k_DOORBELL_1_ADDR(n,k) (GSI_REG_BASE + 0x00024004 + 0x12000 * (n) + 0x8 * (k)) +#define HWIO_EE_n_GSI_CH_k_DOORBELL_1_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x00024004 + 0x12000 * (n) + 0x8 * (k)) +#define HWIO_EE_n_GSI_CH_k_DOORBELL_1_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x00024004 + 0x12000 * (n) + 0x8 * (k)) +#define HWIO_EE_n_GSI_CH_k_DOORBELL_1_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_DOORBELL_1_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_DOORBELL_1_MAXk 27 +#define HWIO_EE_n_GSI_CH_k_DOORBELL_1_ATTR 0x2 +#define HWIO_EE_n_GSI_CH_k_DOORBELL_1_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_GSI_CH_k_DOORBELL_1_ADDR(n,k),val) +#define HWIO_EE_n_GSI_CH_k_DOORBELL_1_WRITE_PTR_MSB_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_DOORBELL_1_WRITE_PTR_MSB_SHFT 0x0 + +#define HWIO_EE_n_EV_CH_k_DOORBELL_0_ADDR(n,k) (GSI_REG_BASE + 0x00024800 + 0x12000 * (n) + 0x8 * (k)) +#define HWIO_EE_n_EV_CH_k_DOORBELL_0_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x00024800 + 0x12000 * (n) + 0x8 * (k)) +#define HWIO_EE_n_EV_CH_k_DOORBELL_0_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x00024800 + 0x12000 * (n) + 0x8 * (k)) +#define HWIO_EE_n_EV_CH_k_DOORBELL_0_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_DOORBELL_0_MAXn 2 +#define HWIO_EE_n_EV_CH_k_DOORBELL_0_MAXk 26 +#define HWIO_EE_n_EV_CH_k_DOORBELL_0_ATTR 0x2 +#define HWIO_EE_n_EV_CH_k_DOORBELL_0_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_EV_CH_k_DOORBELL_0_ADDR(n,k),val) +#define HWIO_EE_n_EV_CH_k_DOORBELL_0_WRITE_PTR_LSB_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_DOORBELL_0_WRITE_PTR_LSB_SHFT 0x0 + +#define HWIO_EE_n_EV_CH_k_DOORBELL_1_ADDR(n,k) (GSI_REG_BASE + 0x00024804 + 0x12000 * (n) + 0x8 * (k)) +#define HWIO_EE_n_EV_CH_k_DOORBELL_1_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x00024804 + 0x12000 * (n) + 0x8 * (k)) +#define HWIO_EE_n_EV_CH_k_DOORBELL_1_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x00024804 + 0x12000 * (n) + 0x8 * (k)) +#define HWIO_EE_n_EV_CH_k_DOORBELL_1_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_DOORBELL_1_MAXn 2 +#define HWIO_EE_n_EV_CH_k_DOORBELL_1_MAXk 26 +#define HWIO_EE_n_EV_CH_k_DOORBELL_1_ATTR 0x2 +#define HWIO_EE_n_EV_CH_k_DOORBELL_1_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_EV_CH_k_DOORBELL_1_ADDR(n,k),val) +#define HWIO_EE_n_EV_CH_k_DOORBELL_1_WRITE_PTR_MSB_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_DOORBELL_1_WRITE_PTR_MSB_SHFT 0x0 + +#define HWIO_EE_n_GSI_STATUS_ADDR(n) (GSI_REG_BASE + 0x00025000 + 0x12000 * (n)) +#define HWIO_EE_n_GSI_STATUS_PHYS(n) (GSI_REG_BASE_PHYS + 0x00025000 + 0x12000 * (n)) +#define HWIO_EE_n_GSI_STATUS_OFFS(n) (GSI_REG_BASE_OFFS + 0x00025000 + 0x12000 * (n)) +#define HWIO_EE_n_GSI_STATUS_RMSK 0x1 +#define HWIO_EE_n_GSI_STATUS_MAXn 2 +#define HWIO_EE_n_GSI_STATUS_ATTR 0x1 +#define HWIO_EE_n_GSI_STATUS_INI(n) \ + in_dword_masked(HWIO_EE_n_GSI_STATUS_ADDR(n), HWIO_EE_n_GSI_STATUS_RMSK) +#define HWIO_EE_n_GSI_STATUS_INMI(n,mask) \ + in_dword_masked(HWIO_EE_n_GSI_STATUS_ADDR(n), mask) +#define HWIO_EE_n_GSI_STATUS_ENABLED_BMSK 0x1 +#define HWIO_EE_n_GSI_STATUS_ENABLED_SHFT 0x0 + +#define HWIO_EE_n_GSI_CH_CMD_ADDR(n) (GSI_REG_BASE + 0x00025008 + 0x12000 * (n)) +#define HWIO_EE_n_GSI_CH_CMD_PHYS(n) (GSI_REG_BASE_PHYS + 0x00025008 + 0x12000 * (n)) +#define HWIO_EE_n_GSI_CH_CMD_OFFS(n) (GSI_REG_BASE_OFFS + 0x00025008 + 0x12000 * (n)) +#define HWIO_EE_n_GSI_CH_CMD_RMSK 0xff0000ff +#define HWIO_EE_n_GSI_CH_CMD_MAXn 2 +#define HWIO_EE_n_GSI_CH_CMD_ATTR 0x2 +#define HWIO_EE_n_GSI_CH_CMD_OUTI(n,val) \ + out_dword(HWIO_EE_n_GSI_CH_CMD_ADDR(n),val) +#define HWIO_EE_n_GSI_CH_CMD_OPCODE_BMSK 0xff000000 +#define HWIO_EE_n_GSI_CH_CMD_OPCODE_SHFT 0x18 +#define HWIO_EE_n_GSI_CH_CMD_OPCODE_ALLOCATE_FVAL 0x0 +#define HWIO_EE_n_GSI_CH_CMD_OPCODE_START_FVAL 0x1 +#define HWIO_EE_n_GSI_CH_CMD_OPCODE_STOP_FVAL 0x2 +#define HWIO_EE_n_GSI_CH_CMD_OPCODE_RESET_FVAL 0x9 +#define HWIO_EE_n_GSI_CH_CMD_OPCODE_DE_ALLOC_FVAL 0xa +#define HWIO_EE_n_GSI_CH_CMD_OPCODE_DB_STOP_FVAL 0xb +#define HWIO_EE_n_GSI_CH_CMD_CHID_BMSK 0xff +#define HWIO_EE_n_GSI_CH_CMD_CHID_SHFT 0x0 + +#define HWIO_EE_n_EV_CH_CMD_ADDR(n) (GSI_REG_BASE + 0x00025010 + 0x12000 * (n)) +#define HWIO_EE_n_EV_CH_CMD_PHYS(n) (GSI_REG_BASE_PHYS + 0x00025010 + 0x12000 * (n)) +#define HWIO_EE_n_EV_CH_CMD_OFFS(n) (GSI_REG_BASE_OFFS + 0x00025010 + 0x12000 * (n)) +#define HWIO_EE_n_EV_CH_CMD_RMSK 0xff0000ff +#define HWIO_EE_n_EV_CH_CMD_MAXn 2 +#define HWIO_EE_n_EV_CH_CMD_ATTR 0x2 +#define HWIO_EE_n_EV_CH_CMD_OUTI(n,val) \ + out_dword(HWIO_EE_n_EV_CH_CMD_ADDR(n),val) +#define HWIO_EE_n_EV_CH_CMD_OPCODE_BMSK 0xff000000 +#define HWIO_EE_n_EV_CH_CMD_OPCODE_SHFT 0x18 +#define HWIO_EE_n_EV_CH_CMD_OPCODE_ALLOCATE_FVAL 0x0 +#define HWIO_EE_n_EV_CH_CMD_OPCODE_RESET_FVAL 0x9 +#define HWIO_EE_n_EV_CH_CMD_OPCODE_DE_ALLOC_FVAL 0xa +#define HWIO_EE_n_EV_CH_CMD_CHID_BMSK 0xff +#define HWIO_EE_n_EV_CH_CMD_CHID_SHFT 0x0 + +#define HWIO_EE_n_GSI_EE_GENERIC_CMD_ADDR(n) (GSI_REG_BASE + 0x00025018 + 0x12000 * (n)) +#define HWIO_EE_n_GSI_EE_GENERIC_CMD_PHYS(n) (GSI_REG_BASE_PHYS + 0x00025018 + 0x12000 * (n)) +#define HWIO_EE_n_GSI_EE_GENERIC_CMD_OFFS(n) (GSI_REG_BASE_OFFS + 0x00025018 + 0x12000 * (n)) +#define HWIO_EE_n_GSI_EE_GENERIC_CMD_RMSK 0xffffffff +#define HWIO_EE_n_GSI_EE_GENERIC_CMD_MAXn 2 +#define HWIO_EE_n_GSI_EE_GENERIC_CMD_ATTR 0x2 +#define HWIO_EE_n_GSI_EE_GENERIC_CMD_OUTI(n,val) \ + out_dword(HWIO_EE_n_GSI_EE_GENERIC_CMD_ADDR(n),val) +#define HWIO_EE_n_GSI_EE_GENERIC_CMD_OPCODE_BMSK 0xffffffff +#define HWIO_EE_n_GSI_EE_GENERIC_CMD_OPCODE_SHFT 0x0 + +#define HWIO_EE_n_GSI_HW_PARAM_0_ADDR(n) (GSI_REG_BASE + 0x00025038 + 0x12000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_0_PHYS(n) (GSI_REG_BASE_PHYS + 0x00025038 + 0x12000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_0_OFFS(n) (GSI_REG_BASE_OFFS + 0x00025038 + 0x12000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_0_RMSK 0xffffffff +#define HWIO_EE_n_GSI_HW_PARAM_0_MAXn 2 +#define HWIO_EE_n_GSI_HW_PARAM_0_ATTR 0x1 +#define HWIO_EE_n_GSI_HW_PARAM_0_INI(n) \ + in_dword_masked(HWIO_EE_n_GSI_HW_PARAM_0_ADDR(n), HWIO_EE_n_GSI_HW_PARAM_0_RMSK) +#define HWIO_EE_n_GSI_HW_PARAM_0_INMI(n,mask) \ + in_dword_masked(HWIO_EE_n_GSI_HW_PARAM_0_ADDR(n), mask) +#define HWIO_EE_n_GSI_HW_PARAM_0_USE_AXI_M_BMSK 0x80000000 +#define HWIO_EE_n_GSI_HW_PARAM_0_USE_AXI_M_SHFT 0x1f +#define HWIO_EE_n_GSI_HW_PARAM_0_PERIPH_SEC_GRP_BMSK 0x7c000000 +#define HWIO_EE_n_GSI_HW_PARAM_0_PERIPH_SEC_GRP_SHFT 0x1a +#define HWIO_EE_n_GSI_HW_PARAM_0_PERIPH_CONF_ADDR_BUS_W_BMSK 0x3e00000 +#define HWIO_EE_n_GSI_HW_PARAM_0_PERIPH_CONF_ADDR_BUS_W_SHFT 0x15 +#define HWIO_EE_n_GSI_HW_PARAM_0_NUM_EES_BMSK 0x1f0000 +#define HWIO_EE_n_GSI_HW_PARAM_0_NUM_EES_SHFT 0x10 +#define HWIO_EE_n_GSI_HW_PARAM_0_GSI_CH_NUM_BMSK 0xff00 +#define HWIO_EE_n_GSI_HW_PARAM_0_GSI_CH_NUM_SHFT 0x8 +#define HWIO_EE_n_GSI_HW_PARAM_0_GSI_EV_CH_NUM_BMSK 0xff +#define HWIO_EE_n_GSI_HW_PARAM_0_GSI_EV_CH_NUM_SHFT 0x0 + +#define HWIO_EE_n_GSI_HW_PARAM_1_ADDR(n) (GSI_REG_BASE + 0x0002503c + 0x12000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_1_PHYS(n) (GSI_REG_BASE_PHYS + 0x0002503c + 0x12000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_1_OFFS(n) (GSI_REG_BASE_OFFS + 0x0002503c + 0x12000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_1_RMSK 0xffffffff +#define HWIO_EE_n_GSI_HW_PARAM_1_MAXn 2 +#define HWIO_EE_n_GSI_HW_PARAM_1_ATTR 0x1 +#define HWIO_EE_n_GSI_HW_PARAM_1_INI(n) \ + in_dword_masked(HWIO_EE_n_GSI_HW_PARAM_1_ADDR(n), HWIO_EE_n_GSI_HW_PARAM_1_RMSK) +#define HWIO_EE_n_GSI_HW_PARAM_1_INMI(n,mask) \ + in_dword_masked(HWIO_EE_n_GSI_HW_PARAM_1_ADDR(n), mask) +#define HWIO_EE_n_GSI_HW_PARAM_1_GSI_BLK_INT_ACCESS_REGION_2_EN_BMSK 0x80000000 +#define HWIO_EE_n_GSI_HW_PARAM_1_GSI_BLK_INT_ACCESS_REGION_2_EN_SHFT 0x1f +#define HWIO_EE_n_GSI_HW_PARAM_1_GSI_BLK_INT_ACCESS_REGION_1_EN_BMSK 0x40000000 +#define HWIO_EE_n_GSI_HW_PARAM_1_GSI_BLK_INT_ACCESS_REGION_1_EN_SHFT 0x1e +#define HWIO_EE_n_GSI_HW_PARAM_1_GSI_SIMPLE_RD_WR_BMSK 0x20000000 +#define HWIO_EE_n_GSI_HW_PARAM_1_GSI_SIMPLE_RD_WR_SHFT 0x1d +#define HWIO_EE_n_GSI_HW_PARAM_1_GSI_ESCAPE_BUF_ONLY_BMSK 0x10000000 +#define HWIO_EE_n_GSI_HW_PARAM_1_GSI_ESCAPE_BUF_ONLY_SHFT 0x1c +#define HWIO_EE_n_GSI_HW_PARAM_1_GSI_USE_UC_IF_BMSK 0x8000000 +#define HWIO_EE_n_GSI_HW_PARAM_1_GSI_USE_UC_IF_SHFT 0x1b +#define HWIO_EE_n_GSI_HW_PARAM_1_GSI_USE_DB_ENG_BMSK 0x4000000 +#define HWIO_EE_n_GSI_HW_PARAM_1_GSI_USE_DB_ENG_SHFT 0x1a +#define HWIO_EE_n_GSI_HW_PARAM_1_GSI_USE_BP_MTRIX_BMSK 0x2000000 +#define HWIO_EE_n_GSI_HW_PARAM_1_GSI_USE_BP_MTRIX_SHFT 0x19 +#define HWIO_EE_n_GSI_HW_PARAM_1_GSI_NUM_TIMERS_BMSK 0x1f00000 +#define HWIO_EE_n_GSI_HW_PARAM_1_GSI_NUM_TIMERS_SHFT 0x14 +#define HWIO_EE_n_GSI_HW_PARAM_1_GSI_USE_XPU_BMSK 0x80000 +#define HWIO_EE_n_GSI_HW_PARAM_1_GSI_USE_XPU_SHFT 0x13 +#define HWIO_EE_n_GSI_HW_PARAM_1_GSI_QRIB_EN_BMSK 0x40000 +#define HWIO_EE_n_GSI_HW_PARAM_1_GSI_QRIB_EN_SHFT 0x12 +#define HWIO_EE_n_GSI_HW_PARAM_1_GSI_VMIDACR_EN_BMSK 0x20000 +#define HWIO_EE_n_GSI_HW_PARAM_1_GSI_VMIDACR_EN_SHFT 0x11 +#define HWIO_EE_n_GSI_HW_PARAM_1_GSI_SEC_EN_BMSK 0x10000 +#define HWIO_EE_n_GSI_HW_PARAM_1_GSI_SEC_EN_SHFT 0x10 +#define HWIO_EE_n_GSI_HW_PARAM_1_GSI_NONSEC_EN_BMSK 0xf000 +#define HWIO_EE_n_GSI_HW_PARAM_1_GSI_NONSEC_EN_SHFT 0xc +#define HWIO_EE_n_GSI_HW_PARAM_1_GSI_NUM_QAD_BMSK 0xf00 +#define HWIO_EE_n_GSI_HW_PARAM_1_GSI_NUM_QAD_SHFT 0x8 +#define HWIO_EE_n_GSI_HW_PARAM_1_GSI_M_DATA_BUS_W_BMSK 0xff +#define HWIO_EE_n_GSI_HW_PARAM_1_GSI_M_DATA_BUS_W_SHFT 0x0 + +#define HWIO_EE_n_GSI_HW_PARAM_2_ADDR(n) (GSI_REG_BASE + 0x00025040 + 0x12000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_2_PHYS(n) (GSI_REG_BASE_PHYS + 0x00025040 + 0x12000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_2_OFFS(n) (GSI_REG_BASE_OFFS + 0x00025040 + 0x12000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_2_RMSK 0xffffffff +#define HWIO_EE_n_GSI_HW_PARAM_2_MAXn 2 +#define HWIO_EE_n_GSI_HW_PARAM_2_ATTR 0x1 +#define HWIO_EE_n_GSI_HW_PARAM_2_INI(n) \ + in_dword_masked(HWIO_EE_n_GSI_HW_PARAM_2_ADDR(n), HWIO_EE_n_GSI_HW_PARAM_2_RMSK) +#define HWIO_EE_n_GSI_HW_PARAM_2_INMI(n,mask) \ + in_dword_masked(HWIO_EE_n_GSI_HW_PARAM_2_ADDR(n), mask) +#define HWIO_EE_n_GSI_HW_PARAM_2_GSI_USE_INTER_EE_BMSK 0x80000000 +#define HWIO_EE_n_GSI_HW_PARAM_2_GSI_USE_INTER_EE_SHFT 0x1f +#define HWIO_EE_n_GSI_HW_PARAM_2_GSI_USE_RD_WR_ENG_BMSK 0x40000000 +#define HWIO_EE_n_GSI_HW_PARAM_2_GSI_USE_RD_WR_ENG_SHFT 0x1e +#define HWIO_EE_n_GSI_HW_PARAM_2_GSI_SDMA_N_IOVEC_BMSK 0x38000000 +#define HWIO_EE_n_GSI_HW_PARAM_2_GSI_SDMA_N_IOVEC_SHFT 0x1b +#define HWIO_EE_n_GSI_HW_PARAM_2_GSI_SDMA_MAX_BURST_BMSK 0x7f80000 +#define HWIO_EE_n_GSI_HW_PARAM_2_GSI_SDMA_MAX_BURST_SHFT 0x13 +#define HWIO_EE_n_GSI_HW_PARAM_2_GSI_SDMA_N_INT_BMSK 0x70000 +#define HWIO_EE_n_GSI_HW_PARAM_2_GSI_SDMA_N_INT_SHFT 0x10 +#define HWIO_EE_n_GSI_HW_PARAM_2_GSI_USE_SDMA_BMSK 0x8000 +#define HWIO_EE_n_GSI_HW_PARAM_2_GSI_USE_SDMA_SHFT 0xf +#define HWIO_EE_n_GSI_HW_PARAM_2_GSI_CH_FULL_LOGIC_BMSK 0x4000 +#define HWIO_EE_n_GSI_HW_PARAM_2_GSI_CH_FULL_LOGIC_SHFT 0xe +#define HWIO_EE_n_GSI_HW_PARAM_2_GSI_CH_PEND_TRANSLATE_BMSK 0x2000 +#define HWIO_EE_n_GSI_HW_PARAM_2_GSI_CH_PEND_TRANSLATE_SHFT 0xd +#define HWIO_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_BMSK 0x1f00 +#define HWIO_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_SHFT 0x8 +#define HWIO_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_ONE_KB_FVAL 0x0 +#define HWIO_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_TWO_KB_FVAL 0x1 +#define HWIO_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_TWO_N_HALF_KB_FVAL 0x2 +#define HWIO_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_THREE_KB_FVAL 0x3 +#define HWIO_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_THREE_N_HALF_KB_FVAL 0x4 +#define HWIO_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_FOUR_KB_FVAL 0x5 +#define HWIO_EE_n_GSI_HW_PARAM_2_GSI_NUM_CH_PER_EE_BMSK 0xff +#define HWIO_EE_n_GSI_HW_PARAM_2_GSI_NUM_CH_PER_EE_SHFT 0x0 + +#define HWIO_EE_n_GSI_MCS_CODE_VER_ADDR(n) (GSI_REG_BASE + 0x00025048 + 0x12000 * (n)) +#define HWIO_EE_n_GSI_MCS_CODE_VER_PHYS(n) (GSI_REG_BASE_PHYS + 0x00025048 + 0x12000 * (n)) +#define HWIO_EE_n_GSI_MCS_CODE_VER_OFFS(n) (GSI_REG_BASE_OFFS + 0x00025048 + 0x12000 * (n)) +#define HWIO_EE_n_GSI_MCS_CODE_VER_RMSK 0xffffffff +#define HWIO_EE_n_GSI_MCS_CODE_VER_MAXn 2 +#define HWIO_EE_n_GSI_MCS_CODE_VER_ATTR 0x1 +#define HWIO_EE_n_GSI_MCS_CODE_VER_INI(n) \ + in_dword_masked(HWIO_EE_n_GSI_MCS_CODE_VER_ADDR(n), HWIO_EE_n_GSI_MCS_CODE_VER_RMSK) +#define HWIO_EE_n_GSI_MCS_CODE_VER_INMI(n,mask) \ + in_dword_masked(HWIO_EE_n_GSI_MCS_CODE_VER_ADDR(n), mask) +#define HWIO_EE_n_GSI_MCS_CODE_VER_VER_BMSK 0xffffffff +#define HWIO_EE_n_GSI_MCS_CODE_VER_VER_SHFT 0x0 + +#define HWIO_EE_n_GSI_HW_PARAM_3_ADDR(n) (GSI_REG_BASE + 0x0002504c + 0x12000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_3_PHYS(n) (GSI_REG_BASE_PHYS + 0x0002504c + 0x12000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_3_OFFS(n) (GSI_REG_BASE_OFFS + 0x0002504c + 0x12000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_3_RMSK 0x1fffffff +#define HWIO_EE_n_GSI_HW_PARAM_3_MAXn 2 +#define HWIO_EE_n_GSI_HW_PARAM_3_ATTR 0x1 +#define HWIO_EE_n_GSI_HW_PARAM_3_INI(n) \ + in_dword_masked(HWIO_EE_n_GSI_HW_PARAM_3_ADDR(n), HWIO_EE_n_GSI_HW_PARAM_3_RMSK) +#define HWIO_EE_n_GSI_HW_PARAM_3_INMI(n,mask) \ + in_dword_masked(HWIO_EE_n_GSI_HW_PARAM_3_ADDR(n), mask) +#define HWIO_EE_n_GSI_HW_PARAM_3_GSI_USE_DB_MSI_MODE_BMSK 0x10000000 +#define HWIO_EE_n_GSI_HW_PARAM_3_GSI_USE_DB_MSI_MODE_SHFT 0x1c +#define HWIO_EE_n_GSI_HW_PARAM_3_GSI_USE_SLEEP_CLK_DIV_BMSK 0x8000000 +#define HWIO_EE_n_GSI_HW_PARAM_3_GSI_USE_SLEEP_CLK_DIV_SHFT 0x1b +#define HWIO_EE_n_GSI_HW_PARAM_3_GSI_USE_VIR_CH_IF_BMSK 0x4000000 +#define HWIO_EE_n_GSI_HW_PARAM_3_GSI_USE_VIR_CH_IF_SHFT 0x1a +#define HWIO_EE_n_GSI_HW_PARAM_3_GSI_USE_IROM_BMSK 0x2000000 +#define HWIO_EE_n_GSI_HW_PARAM_3_GSI_USE_IROM_SHFT 0x19 +#define HWIO_EE_n_GSI_HW_PARAM_3_GSI_REE_MAX_BURST_LEN_BMSK 0x1f00000 +#define HWIO_EE_n_GSI_HW_PARAM_3_GSI_REE_MAX_BURST_LEN_SHFT 0x14 +#define HWIO_EE_n_GSI_HW_PARAM_3_GSI_M_ADDR_BUS_W_BMSK 0xff000 +#define HWIO_EE_n_GSI_HW_PARAM_3_GSI_M_ADDR_BUS_W_SHFT 0xc +#define HWIO_EE_n_GSI_HW_PARAM_3_GSI_NUM_PREFETCH_BUFS_BMSK 0xf00 +#define HWIO_EE_n_GSI_HW_PARAM_3_GSI_NUM_PREFETCH_BUFS_SHFT 0x8 +#define HWIO_EE_n_GSI_HW_PARAM_3_GSI_SDMA_MAX_OS_WR_BMSK 0xf0 +#define HWIO_EE_n_GSI_HW_PARAM_3_GSI_SDMA_MAX_OS_WR_SHFT 0x4 +#define HWIO_EE_n_GSI_HW_PARAM_3_GSI_SDMA_MAX_OS_RD_BMSK 0xf +#define HWIO_EE_n_GSI_HW_PARAM_3_GSI_SDMA_MAX_OS_RD_SHFT 0x0 + +#define HWIO_EE_n_GSI_HW_PARAM_4_ADDR(n) (GSI_REG_BASE + 0x00025050 + 0x12000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_4_PHYS(n) (GSI_REG_BASE_PHYS + 0x00025050 + 0x12000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_4_OFFS(n) (GSI_REG_BASE_OFFS + 0x00025050 + 0x12000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_4_RMSK 0xffff +#define HWIO_EE_n_GSI_HW_PARAM_4_MAXn 2 +#define HWIO_EE_n_GSI_HW_PARAM_4_ATTR 0x1 +#define HWIO_EE_n_GSI_HW_PARAM_4_INI(n) \ + in_dword_masked(HWIO_EE_n_GSI_HW_PARAM_4_ADDR(n), HWIO_EE_n_GSI_HW_PARAM_4_RMSK) +#define HWIO_EE_n_GSI_HW_PARAM_4_INMI(n,mask) \ + in_dword_masked(HWIO_EE_n_GSI_HW_PARAM_4_ADDR(n), mask) +#define HWIO_EE_n_GSI_HW_PARAM_4_GSI_IRAM_PROTCOL_CNT_BMSK 0xff00 +#define HWIO_EE_n_GSI_HW_PARAM_4_GSI_IRAM_PROTCOL_CNT_SHFT 0x8 +#define HWIO_EE_n_GSI_HW_PARAM_4_GSI_NUM_EV_PER_EE_BMSK 0xff +#define HWIO_EE_n_GSI_HW_PARAM_4_GSI_NUM_EV_PER_EE_SHFT 0x0 + +#define HWIO_EE_n_CNTXT_TYPE_IRQ_ADDR(n) (GSI_REG_BASE + 0x00025080 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_PHYS(n) (GSI_REG_BASE_PHYS + 0x00025080 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_OFFS(n) (GSI_REG_BASE_OFFS + 0x00025080 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_RMSK 0x7f +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MAXn 2 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_ATTR 0x1 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_INI(n) \ + in_dword_masked(HWIO_EE_n_CNTXT_TYPE_IRQ_ADDR(n), HWIO_EE_n_CNTXT_TYPE_IRQ_RMSK) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_INMI(n,mask) \ + in_dword_masked(HWIO_EE_n_CNTXT_TYPE_IRQ_ADDR(n), mask) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_GENERAL_BMSK 0x40 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_GENERAL_SHFT 0x6 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_INTER_EE_EV_CTRL_BMSK 0x20 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_INTER_EE_EV_CTRL_SHFT 0x5 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_INTER_EE_CH_CTRL_BMSK 0x10 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_INTER_EE_CH_CTRL_SHFT 0x4 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_IEOB_BMSK 0x8 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_IEOB_SHFT 0x3 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_GLOB_EE_BMSK 0x4 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_GLOB_EE_SHFT 0x2 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_EV_CTRL_BMSK 0x2 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_EV_CTRL_SHFT 0x1 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_CH_CTRL_BMSK 0x1 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_CH_CTRL_SHFT 0x0 + +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_ADDR(n) (GSI_REG_BASE + 0x00025088 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_PHYS(n) (GSI_REG_BASE_PHYS + 0x00025088 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_OFFS(n) (GSI_REG_BASE_OFFS + 0x00025088 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_RMSK 0x7f +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_MAXn 2 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_ATTR 0x3 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_INI(n) \ + in_dword_masked(HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_ADDR(n), HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_RMSK) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_INMI(n,mask) \ + in_dword_masked(HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_ADDR(n), mask) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_OUTI(n,val) \ + out_dword(HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_ADDR(n),val) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_ADDR(n),mask,val,HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_INI(n)) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_GENERAL_BMSK 0x40 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_GENERAL_SHFT 0x6 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_INTER_EE_EV_CTRL_BMSK 0x20 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_INTER_EE_EV_CTRL_SHFT 0x5 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_INTER_EE_CH_CTRL_BMSK 0x10 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_INTER_EE_CH_CTRL_SHFT 0x4 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_IEOB_BMSK 0x8 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_IEOB_SHFT 0x3 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_GLOB_EE_BMSK 0x4 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_GLOB_EE_SHFT 0x2 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_EV_CTRL_BMSK 0x2 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_EV_CTRL_SHFT 0x1 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_CH_CTRL_BMSK 0x1 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_CH_CTRL_SHFT 0x0 + +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_k_ADDR(n,k) (GSI_REG_BASE + 0x00025090 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_k_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x00025090 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_k_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x00025090 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_k_RMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_k_MAXn 2 +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_k_MAXk 0 +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_k_ATTR 0x1 +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_k_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_k_ADDR(n,k), HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_k_RMSK) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_k_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_k_ADDR(n,k), mask) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_k_GSI_CH_BIT_MAP_BMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_k_GSI_CH_BIT_MAP_SHFT 0x0 + +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_ADDR(n,k) (GSI_REG_BASE + 0x00025094 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x00025094 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x00025094 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_RMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_MAXn 2 +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_MAXk 0 +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_ATTR 0x3 +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_ADDR(n,k), HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_RMSK) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_ADDR(n,k), mask) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_ADDR(n,k),val) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_ADDR(n,k),mask,val,HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_INI2(n,k)) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_GSI_CH_BIT_MAP_MSK_BMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_GSI_CH_BIT_MAP_MSK_SHFT 0x0 + +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_k_ADDR(n,k) (GSI_REG_BASE + 0x00025098 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_k_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x00025098 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_k_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x00025098 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_k_RMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_k_MAXn 2 +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_k_MAXk 0 +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_k_ATTR 0x2 +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_k_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_k_ADDR(n,k),val) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_k_GSI_CH_BIT_MAP_BMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_k_GSI_CH_BIT_MAP_SHFT 0x0 + +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_k_ADDR(n,k) (GSI_REG_BASE + 0x0002509c + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_k_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x0002509c + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_k_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x0002509c + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_k_RMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_k_MAXn 2 +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_k_MAXk 0 +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_k_ATTR 0x1 +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_k_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_k_ADDR(n,k), HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_k_RMSK) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_k_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_k_ADDR(n,k), mask) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_k_EV_CH_BIT_MAP_BMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_k_EV_CH_BIT_MAP_SHFT 0x0 + +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_ADDR(n,k) (GSI_REG_BASE + 0x000250a0 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x000250a0 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x000250a0 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_RMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_MAXn 2 +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_MAXk 0 +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_ATTR 0x3 +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_ADDR(n,k), HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_RMSK) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_ADDR(n,k), mask) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_ADDR(n,k),val) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_ADDR(n,k),mask,val,HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_INI2(n,k)) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_EV_CH_BIT_MAP_MSK_BMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_EV_CH_BIT_MAP_MSK_SHFT 0x0 + +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_k_ADDR(n,k) (GSI_REG_BASE + 0x000250a4 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_k_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x000250a4 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_k_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x000250a4 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_k_RMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_k_MAXn 2 +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_k_MAXk 0 +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_k_ATTR 0x2 +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_k_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_k_ADDR(n,k),val) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_k_EV_CH_BIT_MAP_BMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_k_EV_CH_BIT_MAP_SHFT 0x0 + +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_k_ADDR(n,k) (GSI_REG_BASE + 0x000250a8 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_k_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x000250a8 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_k_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x000250a8 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_k_RMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_k_MAXn 2 +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_k_MAXk 0 +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_k_ATTR 0x1 +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_k_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_k_ADDR(n,k), HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_k_RMSK) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_k_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_k_ADDR(n,k), mask) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_k_EV_CH_BIT_MAP_BMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_k_EV_CH_BIT_MAP_SHFT 0x0 + +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_ADDR(n,k) (GSI_REG_BASE + 0x000250ac + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x000250ac + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x000250ac + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_RMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_MAXn 2 +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_MAXk 0 +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_ATTR 0x3 +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_INI2(n,k) \ + in_dword_masked(HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_ADDR(n,k), HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_RMSK) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_INMI2(n,k,mask) \ + in_dword_masked(HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_ADDR(n,k), mask) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_ADDR(n,k),val) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_ADDR(n,k),mask,val,HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_INI2(n,k)) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_EV_CH_BIT_MAP_MSK_BMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_EV_CH_BIT_MAP_MSK_SHFT 0x0 + +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_k_ADDR(n,k) (GSI_REG_BASE + 0x000250b0 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_k_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x000250b0 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_k_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x000250b0 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_k_RMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_k_MAXn 2 +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_k_MAXk 0 +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_k_ATTR 0x2 +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_k_OUTI2(n,k,val) \ + out_dword(HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_k_ADDR(n,k),val) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_k_EV_CH_BIT_MAP_BMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_k_EV_CH_BIT_MAP_SHFT 0x0 + +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_ADDR(n) (GSI_REG_BASE + 0x00025200 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_PHYS(n) (GSI_REG_BASE_PHYS + 0x00025200 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_OFFS(n) (GSI_REG_BASE_OFFS + 0x00025200 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_RMSK 0xf +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_MAXn 2 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_ATTR 0x1 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_INI(n) \ + in_dword_masked(HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_ADDR(n), HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_RMSK) +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_INMI(n,mask) \ + in_dword_masked(HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_ADDR(n), mask) +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT3_BMSK 0x8 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT3_SHFT 0x3 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT2_BMSK 0x4 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT2_SHFT 0x2 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT1_BMSK 0x2 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT1_SHFT 0x1 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_ERROR_INT_BMSK 0x1 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_ERROR_INT_SHFT 0x0 + +#define HWIO_EE_n_CNTXT_GLOB_IRQ_EN_ADDR(n) (GSI_REG_BASE + 0x00025204 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_GLOB_IRQ_EN_PHYS(n) (GSI_REG_BASE_PHYS + 0x00025204 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_GLOB_IRQ_EN_OFFS(n) (GSI_REG_BASE_OFFS + 0x00025204 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_GLOB_IRQ_EN_RMSK 0xf +#define HWIO_EE_n_CNTXT_GLOB_IRQ_EN_MAXn 2 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_EN_ATTR 0x3 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_EN_INI(n) \ + in_dword_masked(HWIO_EE_n_CNTXT_GLOB_IRQ_EN_ADDR(n), HWIO_EE_n_CNTXT_GLOB_IRQ_EN_RMSK) +#define HWIO_EE_n_CNTXT_GLOB_IRQ_EN_INMI(n,mask) \ + in_dword_masked(HWIO_EE_n_CNTXT_GLOB_IRQ_EN_ADDR(n), mask) +#define HWIO_EE_n_CNTXT_GLOB_IRQ_EN_OUTI(n,val) \ + out_dword(HWIO_EE_n_CNTXT_GLOB_IRQ_EN_ADDR(n),val) +#define HWIO_EE_n_CNTXT_GLOB_IRQ_EN_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_CNTXT_GLOB_IRQ_EN_ADDR(n),mask,val,HWIO_EE_n_CNTXT_GLOB_IRQ_EN_INI(n)) +#define HWIO_EE_n_CNTXT_GLOB_IRQ_EN_GP_INT3_BMSK 0x8 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_EN_GP_INT3_SHFT 0x3 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_EN_GP_INT2_BMSK 0x4 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_EN_GP_INT2_SHFT 0x2 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_EN_GP_INT1_BMSK 0x2 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_EN_GP_INT1_SHFT 0x1 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_EN_ERROR_INT_BMSK 0x1 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_EN_ERROR_INT_SHFT 0x0 + +#define HWIO_EE_n_CNTXT_GLOB_IRQ_CLR_ADDR(n) (GSI_REG_BASE + 0x00025208 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_GLOB_IRQ_CLR_PHYS(n) (GSI_REG_BASE_PHYS + 0x00025208 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_GLOB_IRQ_CLR_OFFS(n) (GSI_REG_BASE_OFFS + 0x00025208 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_GLOB_IRQ_CLR_RMSK 0xf +#define HWIO_EE_n_CNTXT_GLOB_IRQ_CLR_MAXn 2 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_CLR_ATTR 0x2 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_CLR_OUTI(n,val) \ + out_dword(HWIO_EE_n_CNTXT_GLOB_IRQ_CLR_ADDR(n),val) +#define HWIO_EE_n_CNTXT_GLOB_IRQ_CLR_GP_INT3_BMSK 0x8 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_CLR_GP_INT3_SHFT 0x3 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_CLR_GP_INT2_BMSK 0x4 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_CLR_GP_INT2_SHFT 0x2 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_CLR_GP_INT1_BMSK 0x2 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_CLR_GP_INT1_SHFT 0x1 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_CLR_ERROR_INT_BMSK 0x1 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_CLR_ERROR_INT_SHFT 0x0 + +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_ADDR(n) (GSI_REG_BASE + 0x0002520c + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_PHYS(n) (GSI_REG_BASE_PHYS + 0x0002520c + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_OFFS(n) (GSI_REG_BASE_OFFS + 0x0002520c + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_RMSK 0xf +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_MAXn 2 +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_ATTR 0x1 +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_INI(n) \ + in_dword_masked(HWIO_EE_n_CNTXT_GSI_IRQ_STTS_ADDR(n), HWIO_EE_n_CNTXT_GSI_IRQ_STTS_RMSK) +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_INMI(n,mask) \ + in_dword_masked(HWIO_EE_n_CNTXT_GSI_IRQ_STTS_ADDR(n), mask) +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_GSI_MCS_STACK_OVRFLOW_BMSK 0x8 +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_GSI_MCS_STACK_OVRFLOW_SHFT 0x3 +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_GSI_CMD_FIFO_OVRFLOW_BMSK 0x4 +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_GSI_CMD_FIFO_OVRFLOW_SHFT 0x2 +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_GSI_BUS_ERROR_BMSK 0x2 +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_GSI_BUS_ERROR_SHFT 0x1 +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_GSI_BREAK_POINT_BMSK 0x1 +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_GSI_BREAK_POINT_SHFT 0x0 + +#define HWIO_EE_n_CNTXT_GSI_IRQ_EN_ADDR(n) (GSI_REG_BASE + 0x00025210 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_GSI_IRQ_EN_PHYS(n) (GSI_REG_BASE_PHYS + 0x00025210 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_GSI_IRQ_EN_OFFS(n) (GSI_REG_BASE_OFFS + 0x00025210 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_GSI_IRQ_EN_RMSK 0xf +#define HWIO_EE_n_CNTXT_GSI_IRQ_EN_MAXn 2 +#define HWIO_EE_n_CNTXT_GSI_IRQ_EN_ATTR 0x3 +#define HWIO_EE_n_CNTXT_GSI_IRQ_EN_INI(n) \ + in_dword_masked(HWIO_EE_n_CNTXT_GSI_IRQ_EN_ADDR(n), HWIO_EE_n_CNTXT_GSI_IRQ_EN_RMSK) +#define HWIO_EE_n_CNTXT_GSI_IRQ_EN_INMI(n,mask) \ + in_dword_masked(HWIO_EE_n_CNTXT_GSI_IRQ_EN_ADDR(n), mask) +#define HWIO_EE_n_CNTXT_GSI_IRQ_EN_OUTI(n,val) \ + out_dword(HWIO_EE_n_CNTXT_GSI_IRQ_EN_ADDR(n),val) +#define HWIO_EE_n_CNTXT_GSI_IRQ_EN_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_CNTXT_GSI_IRQ_EN_ADDR(n),mask,val,HWIO_EE_n_CNTXT_GSI_IRQ_EN_INI(n)) +#define HWIO_EE_n_CNTXT_GSI_IRQ_EN_GSI_MCS_STACK_OVRFLOW_BMSK 0x8 +#define HWIO_EE_n_CNTXT_GSI_IRQ_EN_GSI_MCS_STACK_OVRFLOW_SHFT 0x3 +#define HWIO_EE_n_CNTXT_GSI_IRQ_EN_GSI_CMD_FIFO_OVRFLOW_BMSK 0x4 +#define HWIO_EE_n_CNTXT_GSI_IRQ_EN_GSI_CMD_FIFO_OVRFLOW_SHFT 0x2 +#define HWIO_EE_n_CNTXT_GSI_IRQ_EN_GSI_BUS_ERROR_BMSK 0x2 +#define HWIO_EE_n_CNTXT_GSI_IRQ_EN_GSI_BUS_ERROR_SHFT 0x1 +#define HWIO_EE_n_CNTXT_GSI_IRQ_EN_GSI_BREAK_POINT_BMSK 0x1 +#define HWIO_EE_n_CNTXT_GSI_IRQ_EN_GSI_BREAK_POINT_SHFT 0x0 + +#define HWIO_EE_n_CNTXT_GSI_IRQ_CLR_ADDR(n) (GSI_REG_BASE + 0x00025214 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_GSI_IRQ_CLR_PHYS(n) (GSI_REG_BASE_PHYS + 0x00025214 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_GSI_IRQ_CLR_OFFS(n) (GSI_REG_BASE_OFFS + 0x00025214 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_GSI_IRQ_CLR_RMSK 0xf +#define HWIO_EE_n_CNTXT_GSI_IRQ_CLR_MAXn 2 +#define HWIO_EE_n_CNTXT_GSI_IRQ_CLR_ATTR 0x2 +#define HWIO_EE_n_CNTXT_GSI_IRQ_CLR_OUTI(n,val) \ + out_dword(HWIO_EE_n_CNTXT_GSI_IRQ_CLR_ADDR(n),val) +#define HWIO_EE_n_CNTXT_GSI_IRQ_CLR_GSI_MCS_STACK_OVRFLOW_BMSK 0x8 +#define HWIO_EE_n_CNTXT_GSI_IRQ_CLR_GSI_MCS_STACK_OVRFLOW_SHFT 0x3 +#define HWIO_EE_n_CNTXT_GSI_IRQ_CLR_GSI_CMD_FIFO_OVRFLOW_BMSK 0x4 +#define HWIO_EE_n_CNTXT_GSI_IRQ_CLR_GSI_CMD_FIFO_OVRFLOW_SHFT 0x2 +#define HWIO_EE_n_CNTXT_GSI_IRQ_CLR_GSI_BUS_ERROR_BMSK 0x2 +#define HWIO_EE_n_CNTXT_GSI_IRQ_CLR_GSI_BUS_ERROR_SHFT 0x1 +#define HWIO_EE_n_CNTXT_GSI_IRQ_CLR_GSI_BREAK_POINT_BMSK 0x1 +#define HWIO_EE_n_CNTXT_GSI_IRQ_CLR_GSI_BREAK_POINT_SHFT 0x0 + +#define HWIO_EE_n_CNTXT_INTSET_ADDR(n) (GSI_REG_BASE + 0x00025220 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_INTSET_PHYS(n) (GSI_REG_BASE_PHYS + 0x00025220 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_INTSET_OFFS(n) (GSI_REG_BASE_OFFS + 0x00025220 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_INTSET_RMSK 0x1 +#define HWIO_EE_n_CNTXT_INTSET_MAXn 2 +#define HWIO_EE_n_CNTXT_INTSET_ATTR 0x3 +#define HWIO_EE_n_CNTXT_INTSET_INI(n) \ + in_dword_masked(HWIO_EE_n_CNTXT_INTSET_ADDR(n), HWIO_EE_n_CNTXT_INTSET_RMSK) +#define HWIO_EE_n_CNTXT_INTSET_INMI(n,mask) \ + in_dword_masked(HWIO_EE_n_CNTXT_INTSET_ADDR(n), mask) +#define HWIO_EE_n_CNTXT_INTSET_OUTI(n,val) \ + out_dword(HWIO_EE_n_CNTXT_INTSET_ADDR(n),val) +#define HWIO_EE_n_CNTXT_INTSET_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_CNTXT_INTSET_ADDR(n),mask,val,HWIO_EE_n_CNTXT_INTSET_INI(n)) +#define HWIO_EE_n_CNTXT_INTSET_INTYPE_BMSK 0x1 +#define HWIO_EE_n_CNTXT_INTSET_INTYPE_SHFT 0x0 +#define HWIO_EE_n_CNTXT_INTSET_INTYPE_MSI_FVAL 0x0 +#define HWIO_EE_n_CNTXT_INTSET_INTYPE_IRQ_FVAL 0x1 + +#define HWIO_EE_n_CNTXT_MSI_BASE_LSB_ADDR(n) (GSI_REG_BASE + 0x00025230 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_MSI_BASE_LSB_PHYS(n) (GSI_REG_BASE_PHYS + 0x00025230 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_MSI_BASE_LSB_OFFS(n) (GSI_REG_BASE_OFFS + 0x00025230 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_MSI_BASE_LSB_RMSK 0xffffffff +#define HWIO_EE_n_CNTXT_MSI_BASE_LSB_MAXn 2 +#define HWIO_EE_n_CNTXT_MSI_BASE_LSB_ATTR 0x3 +#define HWIO_EE_n_CNTXT_MSI_BASE_LSB_INI(n) \ + in_dword_masked(HWIO_EE_n_CNTXT_MSI_BASE_LSB_ADDR(n), HWIO_EE_n_CNTXT_MSI_BASE_LSB_RMSK) +#define HWIO_EE_n_CNTXT_MSI_BASE_LSB_INMI(n,mask) \ + in_dword_masked(HWIO_EE_n_CNTXT_MSI_BASE_LSB_ADDR(n), mask) +#define HWIO_EE_n_CNTXT_MSI_BASE_LSB_OUTI(n,val) \ + out_dword(HWIO_EE_n_CNTXT_MSI_BASE_LSB_ADDR(n),val) +#define HWIO_EE_n_CNTXT_MSI_BASE_LSB_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_CNTXT_MSI_BASE_LSB_ADDR(n),mask,val,HWIO_EE_n_CNTXT_MSI_BASE_LSB_INI(n)) +#define HWIO_EE_n_CNTXT_MSI_BASE_LSB_MSI_ADDR_LSB_BMSK 0xffffffff +#define HWIO_EE_n_CNTXT_MSI_BASE_LSB_MSI_ADDR_LSB_SHFT 0x0 + +#define HWIO_EE_n_CNTXT_MSI_BASE_MSB_ADDR(n) (GSI_REG_BASE + 0x00025234 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_MSI_BASE_MSB_PHYS(n) (GSI_REG_BASE_PHYS + 0x00025234 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_MSI_BASE_MSB_OFFS(n) (GSI_REG_BASE_OFFS + 0x00025234 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_MSI_BASE_MSB_RMSK 0xffffffff +#define HWIO_EE_n_CNTXT_MSI_BASE_MSB_MAXn 2 +#define HWIO_EE_n_CNTXT_MSI_BASE_MSB_ATTR 0x3 +#define HWIO_EE_n_CNTXT_MSI_BASE_MSB_INI(n) \ + in_dword_masked(HWIO_EE_n_CNTXT_MSI_BASE_MSB_ADDR(n), HWIO_EE_n_CNTXT_MSI_BASE_MSB_RMSK) +#define HWIO_EE_n_CNTXT_MSI_BASE_MSB_INMI(n,mask) \ + in_dword_masked(HWIO_EE_n_CNTXT_MSI_BASE_MSB_ADDR(n), mask) +#define HWIO_EE_n_CNTXT_MSI_BASE_MSB_OUTI(n,val) \ + out_dword(HWIO_EE_n_CNTXT_MSI_BASE_MSB_ADDR(n),val) +#define HWIO_EE_n_CNTXT_MSI_BASE_MSB_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_CNTXT_MSI_BASE_MSB_ADDR(n),mask,val,HWIO_EE_n_CNTXT_MSI_BASE_MSB_INI(n)) +#define HWIO_EE_n_CNTXT_MSI_BASE_MSB_MSI_ADDR_MSB_BMSK 0xffffffff +#define HWIO_EE_n_CNTXT_MSI_BASE_MSB_MSI_ADDR_MSB_SHFT 0x0 + +#define HWIO_EE_n_CNTXT_INT_VEC_ADDR(n) (GSI_REG_BASE + 0x00025238 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_INT_VEC_PHYS(n) (GSI_REG_BASE_PHYS + 0x00025238 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_INT_VEC_OFFS(n) (GSI_REG_BASE_OFFS + 0x00025238 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_INT_VEC_RMSK 0xffffffff +#define HWIO_EE_n_CNTXT_INT_VEC_MAXn 2 +#define HWIO_EE_n_CNTXT_INT_VEC_ATTR 0x3 +#define HWIO_EE_n_CNTXT_INT_VEC_INI(n) \ + in_dword_masked(HWIO_EE_n_CNTXT_INT_VEC_ADDR(n), HWIO_EE_n_CNTXT_INT_VEC_RMSK) +#define HWIO_EE_n_CNTXT_INT_VEC_INMI(n,mask) \ + in_dword_masked(HWIO_EE_n_CNTXT_INT_VEC_ADDR(n), mask) +#define HWIO_EE_n_CNTXT_INT_VEC_OUTI(n,val) \ + out_dword(HWIO_EE_n_CNTXT_INT_VEC_ADDR(n),val) +#define HWIO_EE_n_CNTXT_INT_VEC_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_CNTXT_INT_VEC_ADDR(n),mask,val,HWIO_EE_n_CNTXT_INT_VEC_INI(n)) +#define HWIO_EE_n_CNTXT_INT_VEC_INT_VEC_BMSK 0xffffffff +#define HWIO_EE_n_CNTXT_INT_VEC_INT_VEC_SHFT 0x0 + +#define HWIO_EE_n_ERROR_LOG_ADDR(n) (GSI_REG_BASE + 0x00025240 + 0x12000 * (n)) +#define HWIO_EE_n_ERROR_LOG_PHYS(n) (GSI_REG_BASE_PHYS + 0x00025240 + 0x12000 * (n)) +#define HWIO_EE_n_ERROR_LOG_OFFS(n) (GSI_REG_BASE_OFFS + 0x00025240 + 0x12000 * (n)) +#define HWIO_EE_n_ERROR_LOG_RMSK 0xffffffff +#define HWIO_EE_n_ERROR_LOG_MAXn 2 +#define HWIO_EE_n_ERROR_LOG_ATTR 0x3 +#define HWIO_EE_n_ERROR_LOG_INI(n) \ + in_dword_masked(HWIO_EE_n_ERROR_LOG_ADDR(n), HWIO_EE_n_ERROR_LOG_RMSK) +#define HWIO_EE_n_ERROR_LOG_INMI(n,mask) \ + in_dword_masked(HWIO_EE_n_ERROR_LOG_ADDR(n), mask) +#define HWIO_EE_n_ERROR_LOG_OUTI(n,val) \ + out_dword(HWIO_EE_n_ERROR_LOG_ADDR(n),val) +#define HWIO_EE_n_ERROR_LOG_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_ERROR_LOG_ADDR(n),mask,val,HWIO_EE_n_ERROR_LOG_INI(n)) +#define HWIO_EE_n_ERROR_LOG_ERROR_LOG_BMSK 0xffffffff +#define HWIO_EE_n_ERROR_LOG_ERROR_LOG_SHFT 0x0 + +#define HWIO_EE_n_ERROR_LOG_CLR_ADDR(n) (GSI_REG_BASE + 0x00025244 + 0x12000 * (n)) +#define HWIO_EE_n_ERROR_LOG_CLR_PHYS(n) (GSI_REG_BASE_PHYS + 0x00025244 + 0x12000 * (n)) +#define HWIO_EE_n_ERROR_LOG_CLR_OFFS(n) (GSI_REG_BASE_OFFS + 0x00025244 + 0x12000 * (n)) +#define HWIO_EE_n_ERROR_LOG_CLR_RMSK 0xffffffff +#define HWIO_EE_n_ERROR_LOG_CLR_MAXn 2 +#define HWIO_EE_n_ERROR_LOG_CLR_ATTR 0x2 +#define HWIO_EE_n_ERROR_LOG_CLR_OUTI(n,val) \ + out_dword(HWIO_EE_n_ERROR_LOG_CLR_ADDR(n),val) +#define HWIO_EE_n_ERROR_LOG_CLR_ERROR_LOG_CLR_BMSK 0xffffffff +#define HWIO_EE_n_ERROR_LOG_CLR_ERROR_LOG_CLR_SHFT 0x0 + +#define HWIO_EE_n_CNTXT_SCRATCH_0_ADDR(n) (GSI_REG_BASE + 0x00025400 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SCRATCH_0_PHYS(n) (GSI_REG_BASE_PHYS + 0x00025400 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SCRATCH_0_OFFS(n) (GSI_REG_BASE_OFFS + 0x00025400 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SCRATCH_0_RMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SCRATCH_0_MAXn 2 +#define HWIO_EE_n_CNTXT_SCRATCH_0_ATTR 0x3 +#define HWIO_EE_n_CNTXT_SCRATCH_0_INI(n) \ + in_dword_masked(HWIO_EE_n_CNTXT_SCRATCH_0_ADDR(n), HWIO_EE_n_CNTXT_SCRATCH_0_RMSK) +#define HWIO_EE_n_CNTXT_SCRATCH_0_INMI(n,mask) \ + in_dword_masked(HWIO_EE_n_CNTXT_SCRATCH_0_ADDR(n), mask) +#define HWIO_EE_n_CNTXT_SCRATCH_0_OUTI(n,val) \ + out_dword(HWIO_EE_n_CNTXT_SCRATCH_0_ADDR(n),val) +#define HWIO_EE_n_CNTXT_SCRATCH_0_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_CNTXT_SCRATCH_0_ADDR(n),mask,val,HWIO_EE_n_CNTXT_SCRATCH_0_INI(n)) +#define HWIO_EE_n_CNTXT_SCRATCH_0_SCRATCH_BMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SCRATCH_0_SCRATCH_SHFT 0x0 + +#define HWIO_EE_n_CNTXT_SCRATCH_1_ADDR(n) (GSI_REG_BASE + 0x00025404 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SCRATCH_1_PHYS(n) (GSI_REG_BASE_PHYS + 0x00025404 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SCRATCH_1_OFFS(n) (GSI_REG_BASE_OFFS + 0x00025404 + 0x12000 * (n)) +#define HWIO_EE_n_CNTXT_SCRATCH_1_RMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SCRATCH_1_MAXn 2 +#define HWIO_EE_n_CNTXT_SCRATCH_1_ATTR 0x3 +#define HWIO_EE_n_CNTXT_SCRATCH_1_INI(n) \ + in_dword_masked(HWIO_EE_n_CNTXT_SCRATCH_1_ADDR(n), HWIO_EE_n_CNTXT_SCRATCH_1_RMSK) +#define HWIO_EE_n_CNTXT_SCRATCH_1_INMI(n,mask) \ + in_dword_masked(HWIO_EE_n_CNTXT_SCRATCH_1_ADDR(n), mask) +#define HWIO_EE_n_CNTXT_SCRATCH_1_OUTI(n,val) \ + out_dword(HWIO_EE_n_CNTXT_SCRATCH_1_ADDR(n),val) +#define HWIO_EE_n_CNTXT_SCRATCH_1_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_EE_n_CNTXT_SCRATCH_1_ADDR(n),mask,val,HWIO_EE_n_CNTXT_SCRATCH_1_INI(n)) +#define HWIO_EE_n_CNTXT_SCRATCH_1_SCRATCH_BMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SCRATCH_1_SCRATCH_SHFT 0x0 + +#define HWIO_GSI_MCS_CFG_ADDR (GSI_REG_BASE + 0x0000b000) +#define HWIO_GSI_MCS_CFG_PHYS (GSI_REG_BASE_PHYS + 0x0000b000) +#define HWIO_GSI_MCS_CFG_OFFS (GSI_REG_BASE_OFFS + 0x0000b000) +#define HWIO_GSI_MCS_CFG_RMSK 0x1 +#define HWIO_GSI_MCS_CFG_ATTR 0x3 +#define HWIO_GSI_MCS_CFG_IN \ + in_dword_masked(HWIO_GSI_MCS_CFG_ADDR, HWIO_GSI_MCS_CFG_RMSK) +#define HWIO_GSI_MCS_CFG_INM(m) \ + in_dword_masked(HWIO_GSI_MCS_CFG_ADDR, m) +#define HWIO_GSI_MCS_CFG_OUT(v) \ + out_dword(HWIO_GSI_MCS_CFG_ADDR,v) +#define HWIO_GSI_MCS_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_MCS_CFG_ADDR,m,v,HWIO_GSI_MCS_CFG_IN) +#define HWIO_GSI_MCS_CFG_MCS_ENABLE_BMSK 0x1 +#define HWIO_GSI_MCS_CFG_MCS_ENABLE_SHFT 0x0 + +#define HWIO_GSI_TZ_FW_AUTH_LOCK_ADDR (GSI_REG_BASE + 0x0000b008) +#define HWIO_GSI_TZ_FW_AUTH_LOCK_PHYS (GSI_REG_BASE_PHYS + 0x0000b008) +#define HWIO_GSI_TZ_FW_AUTH_LOCK_OFFS (GSI_REG_BASE_OFFS + 0x0000b008) +#define HWIO_GSI_TZ_FW_AUTH_LOCK_RMSK 0x3 +#define HWIO_GSI_TZ_FW_AUTH_LOCK_ATTR 0x3 +#define HWIO_GSI_TZ_FW_AUTH_LOCK_IN \ + in_dword_masked(HWIO_GSI_TZ_FW_AUTH_LOCK_ADDR, HWIO_GSI_TZ_FW_AUTH_LOCK_RMSK) +#define HWIO_GSI_TZ_FW_AUTH_LOCK_INM(m) \ + in_dword_masked(HWIO_GSI_TZ_FW_AUTH_LOCK_ADDR, m) +#define HWIO_GSI_TZ_FW_AUTH_LOCK_OUT(v) \ + out_dword(HWIO_GSI_TZ_FW_AUTH_LOCK_ADDR,v) +#define HWIO_GSI_TZ_FW_AUTH_LOCK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_TZ_FW_AUTH_LOCK_ADDR,m,v,HWIO_GSI_TZ_FW_AUTH_LOCK_IN) +#define HWIO_GSI_TZ_FW_AUTH_LOCK_DIS_DEBUG_SHRAM_WRITE_BMSK 0x2 +#define HWIO_GSI_TZ_FW_AUTH_LOCK_DIS_DEBUG_SHRAM_WRITE_SHFT 0x1 +#define HWIO_GSI_TZ_FW_AUTH_LOCK_DIS_IRAM_WRITE_BMSK 0x1 +#define HWIO_GSI_TZ_FW_AUTH_LOCK_DIS_IRAM_WRITE_SHFT 0x0 + +#define HWIO_GSI_MSA_FW_AUTH_LOCK_ADDR (GSI_REG_BASE + 0x0000b010) +#define HWIO_GSI_MSA_FW_AUTH_LOCK_PHYS (GSI_REG_BASE_PHYS + 0x0000b010) +#define HWIO_GSI_MSA_FW_AUTH_LOCK_OFFS (GSI_REG_BASE_OFFS + 0x0000b010) +#define HWIO_GSI_MSA_FW_AUTH_LOCK_RMSK 0x3 +#define HWIO_GSI_MSA_FW_AUTH_LOCK_ATTR 0x3 +#define HWIO_GSI_MSA_FW_AUTH_LOCK_IN \ + in_dword_masked(HWIO_GSI_MSA_FW_AUTH_LOCK_ADDR, HWIO_GSI_MSA_FW_AUTH_LOCK_RMSK) +#define HWIO_GSI_MSA_FW_AUTH_LOCK_INM(m) \ + in_dword_masked(HWIO_GSI_MSA_FW_AUTH_LOCK_ADDR, m) +#define HWIO_GSI_MSA_FW_AUTH_LOCK_OUT(v) \ + out_dword(HWIO_GSI_MSA_FW_AUTH_LOCK_ADDR,v) +#define HWIO_GSI_MSA_FW_AUTH_LOCK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_MSA_FW_AUTH_LOCK_ADDR,m,v,HWIO_GSI_MSA_FW_AUTH_LOCK_IN) +#define HWIO_GSI_MSA_FW_AUTH_LOCK_DIS_DEBUG_SHRAM_WRITE_BMSK 0x2 +#define HWIO_GSI_MSA_FW_AUTH_LOCK_DIS_DEBUG_SHRAM_WRITE_SHFT 0x1 +#define HWIO_GSI_MSA_FW_AUTH_LOCK_DIS_IRAM_WRITE_BMSK 0x1 +#define HWIO_GSI_MSA_FW_AUTH_LOCK_DIS_IRAM_WRITE_SHFT 0x0 + +#define HWIO_GSI_SP_FW_AUTH_LOCK_ADDR (GSI_REG_BASE + 0x0000b018) +#define HWIO_GSI_SP_FW_AUTH_LOCK_PHYS (GSI_REG_BASE_PHYS + 0x0000b018) +#define HWIO_GSI_SP_FW_AUTH_LOCK_OFFS (GSI_REG_BASE_OFFS + 0x0000b018) +#define HWIO_GSI_SP_FW_AUTH_LOCK_RMSK 0x3 +#define HWIO_GSI_SP_FW_AUTH_LOCK_ATTR 0x3 +#define HWIO_GSI_SP_FW_AUTH_LOCK_IN \ + in_dword_masked(HWIO_GSI_SP_FW_AUTH_LOCK_ADDR, HWIO_GSI_SP_FW_AUTH_LOCK_RMSK) +#define HWIO_GSI_SP_FW_AUTH_LOCK_INM(m) \ + in_dword_masked(HWIO_GSI_SP_FW_AUTH_LOCK_ADDR, m) +#define HWIO_GSI_SP_FW_AUTH_LOCK_OUT(v) \ + out_dword(HWIO_GSI_SP_FW_AUTH_LOCK_ADDR,v) +#define HWIO_GSI_SP_FW_AUTH_LOCK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GSI_SP_FW_AUTH_LOCK_ADDR,m,v,HWIO_GSI_SP_FW_AUTH_LOCK_IN) +#define HWIO_GSI_SP_FW_AUTH_LOCK_DIS_DEBUG_SHRAM_WRITE_BMSK 0x2 +#define HWIO_GSI_SP_FW_AUTH_LOCK_DIS_DEBUG_SHRAM_WRITE_SHFT 0x1 +#define HWIO_GSI_SP_FW_AUTH_LOCK_DIS_IRAM_WRITE_BMSK 0x1 +#define HWIO_GSI_SP_FW_AUTH_LOCK_DIS_IRAM_WRITE_SHFT 0x0 + +#define HWIO_INTER_EE_n_ORIGINATOR_EE_ADDR(n) (GSI_REG_BASE + 0x0000c000 + 0x1000 * (n)) +#define HWIO_INTER_EE_n_ORIGINATOR_EE_PHYS(n) (GSI_REG_BASE_PHYS + 0x0000c000 + 0x1000 * (n)) +#define HWIO_INTER_EE_n_ORIGINATOR_EE_OFFS(n) (GSI_REG_BASE_OFFS + 0x0000c000 + 0x1000 * (n)) +#define HWIO_INTER_EE_n_ORIGINATOR_EE_RMSK 0xf +#define HWIO_INTER_EE_n_ORIGINATOR_EE_MAXn 2 +#define HWIO_INTER_EE_n_ORIGINATOR_EE_ATTR 0x3 +#define HWIO_INTER_EE_n_ORIGINATOR_EE_INI(n) \ + in_dword_masked(HWIO_INTER_EE_n_ORIGINATOR_EE_ADDR(n), HWIO_INTER_EE_n_ORIGINATOR_EE_RMSK) +#define HWIO_INTER_EE_n_ORIGINATOR_EE_INMI(n,mask) \ + in_dword_masked(HWIO_INTER_EE_n_ORIGINATOR_EE_ADDR(n), mask) +#define HWIO_INTER_EE_n_ORIGINATOR_EE_OUTI(n,val) \ + out_dword(HWIO_INTER_EE_n_ORIGINATOR_EE_ADDR(n),val) +#define HWIO_INTER_EE_n_ORIGINATOR_EE_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_INTER_EE_n_ORIGINATOR_EE_ADDR(n),mask,val,HWIO_INTER_EE_n_ORIGINATOR_EE_INI(n)) +#define HWIO_INTER_EE_n_ORIGINATOR_EE_EE_NUMBER_BMSK 0xf +#define HWIO_INTER_EE_n_ORIGINATOR_EE_EE_NUMBER_SHFT 0x0 + +#define HWIO_INTER_EE_n_GSI_CH_CMD_ADDR(n) (GSI_REG_BASE + 0x0000c008 + 0x1000 * (n)) +#define HWIO_INTER_EE_n_GSI_CH_CMD_PHYS(n) (GSI_REG_BASE_PHYS + 0x0000c008 + 0x1000 * (n)) +#define HWIO_INTER_EE_n_GSI_CH_CMD_OFFS(n) (GSI_REG_BASE_OFFS + 0x0000c008 + 0x1000 * (n)) +#define HWIO_INTER_EE_n_GSI_CH_CMD_RMSK 0xff0000ff +#define HWIO_INTER_EE_n_GSI_CH_CMD_MAXn 2 +#define HWIO_INTER_EE_n_GSI_CH_CMD_ATTR 0x2 +#define HWIO_INTER_EE_n_GSI_CH_CMD_OUTI(n,val) \ + out_dword(HWIO_INTER_EE_n_GSI_CH_CMD_ADDR(n),val) +#define HWIO_INTER_EE_n_GSI_CH_CMD_OPCODE_BMSK 0xff000000 +#define HWIO_INTER_EE_n_GSI_CH_CMD_OPCODE_SHFT 0x18 +#define HWIO_INTER_EE_n_GSI_CH_CMD_OPCODE_START_FVAL 0x1 +#define HWIO_INTER_EE_n_GSI_CH_CMD_OPCODE_STOP_FVAL 0x2 +#define HWIO_INTER_EE_n_GSI_CH_CMD_OPCODE_RESET_FVAL 0x9 +#define HWIO_INTER_EE_n_GSI_CH_CMD_OPCODE_DE_ALLOC_FVAL 0xa +#define HWIO_INTER_EE_n_GSI_CH_CMD_OPCODE_DB_STOP_FVAL 0xb +#define HWIO_INTER_EE_n_GSI_CH_CMD_CHID_BMSK 0xff +#define HWIO_INTER_EE_n_GSI_CH_CMD_CHID_SHFT 0x0 + +#define HWIO_INTER_EE_n_EV_CH_CMD_ADDR(n) (GSI_REG_BASE + 0x0000c010 + 0x1000 * (n)) +#define HWIO_INTER_EE_n_EV_CH_CMD_PHYS(n) (GSI_REG_BASE_PHYS + 0x0000c010 + 0x1000 * (n)) +#define HWIO_INTER_EE_n_EV_CH_CMD_OFFS(n) (GSI_REG_BASE_OFFS + 0x0000c010 + 0x1000 * (n)) +#define HWIO_INTER_EE_n_EV_CH_CMD_RMSK 0xff0000ff +#define HWIO_INTER_EE_n_EV_CH_CMD_MAXn 2 +#define HWIO_INTER_EE_n_EV_CH_CMD_ATTR 0x2 +#define HWIO_INTER_EE_n_EV_CH_CMD_OUTI(n,val) \ + out_dword(HWIO_INTER_EE_n_EV_CH_CMD_ADDR(n),val) +#define HWIO_INTER_EE_n_EV_CH_CMD_OPCODE_BMSK 0xff000000 +#define HWIO_INTER_EE_n_EV_CH_CMD_OPCODE_SHFT 0x18 +#define HWIO_INTER_EE_n_EV_CH_CMD_OPCODE_RESET_FVAL 0x9 +#define HWIO_INTER_EE_n_EV_CH_CMD_OPCODE_DE_ALLOC_FVAL 0xa +#define HWIO_INTER_EE_n_EV_CH_CMD_CHID_BMSK 0xff +#define HWIO_INTER_EE_n_EV_CH_CMD_CHID_SHFT 0x0 + +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_k_ADDR(n,k) (GSI_REG_BASE + 0x0000c018 + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_k_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x0000c018 + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_k_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x0000c018 + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_k_RMSK 0xffffffff +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_k_MAXn 2 +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_k_MAXk 0 +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_k_ATTR 0x1 +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_k_INI2(n,k) \ + in_dword_masked(HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_k_ADDR(n,k), HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_k_RMSK) +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_k_INMI2(n,k,mask) \ + in_dword_masked(HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_k_ADDR(n,k), mask) +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_k_GSI_CH_BIT_MAP_BMSK 0xffffffff +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_k_GSI_CH_BIT_MAP_SHFT 0x0 + +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_ADDR(n,k) (GSI_REG_BASE + 0x0000c01c + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x0000c01c + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x0000c01c + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_RMSK 0xffffffff +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_MAXn 2 +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_MAXk 0 +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_ATTR 0x3 +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_INI2(n,k) \ + in_dword_masked(HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_ADDR(n,k), HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_RMSK) +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_INMI2(n,k,mask) \ + in_dword_masked(HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_ADDR(n,k), mask) +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_OUTI2(n,k,val) \ + out_dword(HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_ADDR(n,k),val) +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_ADDR(n,k),mask,val,HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_INI2(n,k)) +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_GSI_CH_BIT_MAP_MSK_BMSK 0xffffffff +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_GSI_CH_BIT_MAP_MSK_SHFT 0x0 + +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_k_ADDR(n,k) (GSI_REG_BASE + 0x0000c020 + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_k_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x0000c020 + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_k_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x0000c020 + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_k_RMSK 0xffffffff +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_k_MAXn 2 +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_k_MAXk 0 +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_k_ATTR 0x2 +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_k_OUTI2(n,k,val) \ + out_dword(HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_k_ADDR(n,k),val) +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_k_GSI_CH_BIT_MAP_BMSK 0xffffffff +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_k_GSI_CH_BIT_MAP_SHFT 0x0 + +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_k_ADDR(n,k) (GSI_REG_BASE + 0x0000c024 + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_k_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x0000c024 + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_k_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x0000c024 + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_k_RMSK 0xffffffff +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_k_MAXn 2 +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_k_MAXk 0 +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_k_ATTR 0x1 +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_k_INI2(n,k) \ + in_dword_masked(HWIO_INTER_EE_n_SRC_EV_CH_IRQ_k_ADDR(n,k), HWIO_INTER_EE_n_SRC_EV_CH_IRQ_k_RMSK) +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_k_INMI2(n,k,mask) \ + in_dword_masked(HWIO_INTER_EE_n_SRC_EV_CH_IRQ_k_ADDR(n,k), mask) +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_k_EV_CH_BIT_MAP_BMSK 0xffffffff +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_k_EV_CH_BIT_MAP_SHFT 0x0 + +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_ADDR(n,k) (GSI_REG_BASE + 0x0000c028 + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x0000c028 + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x0000c028 + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_RMSK 0xffffffff +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_MAXn 2 +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_MAXk 0 +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_ATTR 0x3 +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_INI2(n,k) \ + in_dword_masked(HWIO_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_ADDR(n,k), HWIO_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_RMSK) +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_INMI2(n,k,mask) \ + in_dword_masked(HWIO_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_ADDR(n,k), mask) +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_OUTI2(n,k,val) \ + out_dword(HWIO_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_ADDR(n,k),val) +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_ADDR(n,k),mask,val,HWIO_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_INI2(n,k)) +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_EV_CH_BIT_MAP_MSK_BMSK 0xffffffff +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_EV_CH_BIT_MAP_MSK_SHFT 0x0 + +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_CLR_k_ADDR(n,k) (GSI_REG_BASE + 0x0000c02c + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_CLR_k_PHYS(n,k) (GSI_REG_BASE_PHYS + 0x0000c02c + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_CLR_k_OFFS(n,k) (GSI_REG_BASE_OFFS + 0x0000c02c + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_CLR_k_RMSK 0xffffffff +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_CLR_k_MAXn 2 +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_CLR_k_MAXk 0 +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_CLR_k_ATTR 0x2 +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_CLR_k_OUTI2(n,k,val) \ + out_dword(HWIO_INTER_EE_n_SRC_EV_CH_IRQ_CLR_k_ADDR(n,k),val) +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_CLR_k_EV_CH_BIT_MAP_BMSK 0xffffffff +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_CLR_k_EV_CH_BIT_MAP_SHFT 0x0 + + +#endif /* __GSI_HWIO_H__ */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.5/gsi_hwio_def.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.5/gsi_hwio_def.h new file mode 100644 index 0000000000..55a66d7bae --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.5/gsi_hwio_def.h @@ -0,0 +1,3785 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef __GSI_HWIO_DEF_H__ +#define __GSI_HWIO_DEF_H__ +/** + @file gsi_hwio.h + @brief Auto-generated HWIO interface include file. + + This file contains HWIO register definitions for the following modules: + IPA_0_GSI_TOP_.* + GSI_TOP.* + + 'Include' filters applied: + 'Exclude' filters applied: RESERVED DUMMY +*/ + +/*---------------------------------------------------------------------------- + * MODULE: GSI + *--------------------------------------------------------------------------*/ + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_cfg_s +{ + u32 gsi_enable : 1; + u32 mcs_enable : 1; + u32 double_mcs_clk_freq : 1; + u32 uc_is_mcs : 1; + u32 gsi_pwr_clps : 1; + u32 bp_mtrix_disable : 1; + u32 reserved0 : 2; + u32 sleep_clk_div : 4; + u32 reserved1 : 20; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_cfg_u +{ + struct gsi_hwio_def_gsi_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_MANAGER_MCS_CODE_VER +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_manager_mcs_code_ver_s +{ + u32 ver : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_manager_mcs_code_ver_u +{ + struct gsi_hwio_def_gsi_manager_mcs_code_ver_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_ZEROS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_zeros_s +{ + u32 zeros : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_zeros_u +{ + struct gsi_hwio_def_gsi_zeros_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_PERIPH_BASE_ADDR_LSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_periph_base_addr_lsb_s +{ + u32 base_addr : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_periph_base_addr_lsb_u +{ + struct gsi_hwio_def_gsi_periph_base_addr_lsb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_PERIPH_BASE_ADDR_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_periph_base_addr_msb_s +{ + u32 base_addr : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_periph_base_addr_msb_u +{ + struct gsi_hwio_def_gsi_periph_base_addr_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_CGC_CTRL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_cgc_ctrl_s +{ + u32 region_1_hw_cgc_en : 1; + u32 region_2_hw_cgc_en : 1; + u32 region_3_hw_cgc_en : 1; + u32 region_4_hw_cgc_en : 1; + u32 region_5_hw_cgc_en : 1; + u32 region_6_hw_cgc_en : 1; + u32 region_7_hw_cgc_en : 1; + u32 region_8_hw_cgc_en : 1; + u32 region_9_hw_cgc_en : 1; + u32 region_10_hw_cgc_en : 1; + u32 region_11_hw_cgc_en : 1; + u32 region_12_hw_cgc_en : 1; + u32 region_13_hw_cgc_en : 1; + u32 region_14_hw_cgc_en : 1; + u32 region_15_hw_cgc_en : 1; + u32 region_16_hw_cgc_en : 1; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_cgc_ctrl_u +{ + struct gsi_hwio_def_gsi_cgc_ctrl_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_MOQA_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_moqa_cfg_s +{ + u32 client_req_prio : 8; + u32 client_oord : 8; + u32 client_oowr : 8; + u32 reserved0 : 8; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_moqa_cfg_u +{ + struct gsi_hwio_def_gsi_moqa_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_REE_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_ree_cfg_s +{ + u32 move_to_esc_clr_mode_trsh : 1; + u32 channel_empty_int_enable : 1; + u32 reserved0 : 6; + u32 max_burst_size : 8; + u32 reserved1 : 16; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_ree_cfg_u +{ + struct gsi_hwio_def_gsi_ree_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_PERIPH_PENDING_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_periph_pending_k_s +{ + u32 chid_bit_map : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_periph_pending_k_u +{ + struct gsi_hwio_def_gsi_periph_pending_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_MSI_CACHEATTR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_msi_cacheattr_s +{ + u32 ashared : 1; + u32 ainnershared : 1; + u32 anoallocate : 1; + u32 atransient : 1; + u32 areqpriority : 2; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_msi_cacheattr_u +{ + struct gsi_hwio_def_gsi_msi_cacheattr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_EVENT_CACHEATTR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_event_cacheattr_s +{ + u32 ashared : 1; + u32 ainnershared : 1; + u32 anoallocate : 1; + u32 atransient : 1; + u32 areqpriority : 2; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_event_cacheattr_u +{ + struct gsi_hwio_def_gsi_event_cacheattr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_DATA_CACHEATTR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_data_cacheattr_s +{ + u32 ashared : 1; + u32 ainnershared : 1; + u32 anoallocate : 1; + u32 atransient : 1; + u32 areqpriority : 2; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_data_cacheattr_u +{ + struct gsi_hwio_def_gsi_data_cacheattr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_TRE_CACHEATTR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_tre_cacheattr_s +{ + u32 ashared : 1; + u32 ainnershared : 1; + u32 anoallocate : 1; + u32 atransient : 1; + u32 areqpriority : 2; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_tre_cacheattr_u +{ + struct gsi_hwio_def_gsi_tre_cacheattr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IC_INT_WEIGHT_REE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ic_int_weight_ree_s +{ + u32 stop_ch_comp_int_weight : 4; + u32 new_re_int_weight : 4; + u32 ch_empty_int_weight : 4; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union gsi_hwio_def_ic_int_weight_ree_u +{ + struct gsi_hwio_def_ic_int_weight_ree_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IC_INT_WEIGHT_EVT_ENG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ic_int_weight_evt_eng_s +{ + u32 evnt_eng_int_weight : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union gsi_hwio_def_ic_int_weight_evt_eng_u +{ + struct gsi_hwio_def_ic_int_weight_evt_eng_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IC_INT_WEIGHT_INT_ENG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ic_int_weight_int_eng_s +{ + u32 int_eng_int_weight : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union gsi_hwio_def_ic_int_weight_int_eng_u +{ + struct gsi_hwio_def_ic_int_weight_int_eng_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IC_INT_WEIGHT_CSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ic_int_weight_csr_s +{ + u32 ch_cmd_int_weight : 4; + u32 ee_generic_int_weight : 4; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union gsi_hwio_def_ic_int_weight_csr_u +{ + struct gsi_hwio_def_ic_int_weight_csr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IC_INT_WEIGHT_TLV_ENG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ic_int_weight_tlv_eng_s +{ + u32 tlv_0_int_weight : 4; + u32 tlv_1_int_weight : 4; + u32 tlv_2_int_weight : 4; + u32 ch_not_full_int_weight : 4; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union gsi_hwio_def_ic_int_weight_tlv_eng_u +{ + struct gsi_hwio_def_ic_int_weight_tlv_eng_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IC_INT_WEIGHT_TIMER_ENG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ic_int_weight_timer_eng_s +{ + u32 timer_int_weight : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union gsi_hwio_def_ic_int_weight_timer_eng_u +{ + struct gsi_hwio_def_ic_int_weight_timer_eng_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IC_INT_WEIGHT_DB_ENG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ic_int_weight_db_eng_s +{ + u32 new_db_int_weight : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union gsi_hwio_def_ic_int_weight_db_eng_u +{ + struct gsi_hwio_def_ic_int_weight_db_eng_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IC_INT_WEIGHT_RD_WR_ENG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ic_int_weight_rd_wr_eng_s +{ + u32 read_int_weight : 4; + u32 write_int_weight : 4; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union gsi_hwio_def_ic_int_weight_rd_wr_eng_u +{ + struct gsi_hwio_def_ic_int_weight_rd_wr_eng_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IC_INT_WEIGHT_UCONTROLLER_ENG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ic_int_weight_ucontroller_eng_s +{ + u32 ucontroller_gp_int_weight : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union gsi_hwio_def_ic_int_weight_ucontroller_eng_u +{ + struct gsi_hwio_def_ic_int_weight_ucontroller_eng_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: LOW_LATENCY_ARB_WEIGHT +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_low_latency_arb_weight_s +{ + u32 ll_weight : 6; + u32 reserved0 : 2; + u32 non_ll_weight : 6; + u32 reserved1 : 2; + u32 ll_non_ll_fix_priority : 1; + u32 reserved2 : 15; +}; + +/* Union definition of register */ +union gsi_hwio_def_low_latency_arb_weight_u +{ + struct gsi_hwio_def_low_latency_arb_weight_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_MANAGER_EE_QOS_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_manager_ee_qos_n_s +{ + u32 ee_prio : 2; + u32 reserved0 : 6; + u32 max_ch_alloc : 8; + u32 max_ev_alloc : 8; + u32 reserved1 : 8; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_manager_ee_qos_n_u +{ + struct gsi_hwio_def_gsi_manager_ee_qos_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_shram_ptr_ch_cntxt_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_shram_ptr_ch_cntxt_base_addr_u +{ + struct gsi_hwio_def_gsi_shram_ptr_ch_cntxt_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_shram_ptr_ev_cntxt_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_shram_ptr_ev_cntxt_base_addr_u +{ + struct gsi_hwio_def_gsi_shram_ptr_ev_cntxt_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_shram_ptr_re_storage_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_shram_ptr_re_storage_base_addr_u +{ + struct gsi_hwio_def_gsi_shram_ptr_re_storage_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_shram_ptr_re_esc_buf_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_shram_ptr_re_esc_buf_base_addr_u +{ + struct gsi_hwio_def_gsi_shram_ptr_re_esc_buf_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_shram_ptr_ee_scrach_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_shram_ptr_ee_scrach_base_addr_u +{ + struct gsi_hwio_def_gsi_shram_ptr_ee_scrach_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_shram_ptr_func_stack_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_shram_ptr_func_stack_base_addr_u +{ + struct gsi_hwio_def_gsi_shram_ptr_func_stack_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_shram_ptr_mcs_scratch_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_shram_ptr_mcs_scratch_base_addr_u +{ + struct gsi_hwio_def_gsi_shram_ptr_mcs_scratch_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_shram_ptr_mcs_scratch1_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_shram_ptr_mcs_scratch1_base_addr_u +{ + struct gsi_hwio_def_gsi_shram_ptr_mcs_scratch1_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_shram_ptr_mcs_scratch2_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_shram_ptr_mcs_scratch2_base_addr_u +{ + struct gsi_hwio_def_gsi_shram_ptr_mcs_scratch2_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_shram_ptr_mcs_scratch3_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_shram_ptr_mcs_scratch3_base_addr_u +{ + struct gsi_hwio_def_gsi_shram_ptr_mcs_scratch3_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_shram_ptr_ch_vp_trans_table_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_shram_ptr_ch_vp_trans_table_base_addr_u +{ + struct gsi_hwio_def_gsi_shram_ptr_ch_vp_trans_table_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_shram_ptr_ev_vp_trans_table_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_shram_ptr_ev_vp_trans_table_base_addr_u +{ + struct gsi_hwio_def_gsi_shram_ptr_ev_vp_trans_table_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_shram_ptr_user_info_data_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_shram_ptr_user_info_data_base_addr_u +{ + struct gsi_hwio_def_gsi_shram_ptr_user_info_data_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_shram_ptr_ee_cmd_fifo_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_shram_ptr_ee_cmd_fifo_base_addr_u +{ + struct gsi_hwio_def_gsi_shram_ptr_ee_cmd_fifo_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_shram_ptr_ch_cmd_fifo_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_shram_ptr_ch_cmd_fifo_base_addr_u +{ + struct gsi_hwio_def_gsi_shram_ptr_ch_cmd_fifo_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_shram_ptr_eve_ed_storage_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_shram_ptr_eve_ed_storage_base_addr_u +{ + struct gsi_hwio_def_gsi_shram_ptr_eve_ed_storage_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_IRAM_PTR_CH_CMD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_iram_ptr_ch_cmd_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_iram_ptr_ch_cmd_u +{ + struct gsi_hwio_def_gsi_iram_ptr_ch_cmd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_IRAM_PTR_EE_GENERIC_CMD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_iram_ptr_ee_generic_cmd_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_iram_ptr_ee_generic_cmd_u +{ + struct gsi_hwio_def_gsi_iram_ptr_ee_generic_cmd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_IRAM_PTR_TLV_CH_NOT_FULL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_iram_ptr_tlv_ch_not_full_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_iram_ptr_tlv_ch_not_full_u +{ + struct gsi_hwio_def_gsi_iram_ptr_tlv_ch_not_full_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_IRAM_PTR_MSI_DB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_iram_ptr_msi_db_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_iram_ptr_msi_db_u +{ + struct gsi_hwio_def_gsi_iram_ptr_msi_db_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_IRAM_PTR_CH_DB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_iram_ptr_ch_db_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_iram_ptr_ch_db_u +{ + struct gsi_hwio_def_gsi_iram_ptr_ch_db_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_IRAM_PTR_EV_DB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_iram_ptr_ev_db_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_iram_ptr_ev_db_u +{ + struct gsi_hwio_def_gsi_iram_ptr_ev_db_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_IRAM_PTR_NEW_RE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_iram_ptr_new_re_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_iram_ptr_new_re_u +{ + struct gsi_hwio_def_gsi_iram_ptr_new_re_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_IRAM_PTR_CH_DIS_COMP +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_iram_ptr_ch_dis_comp_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_iram_ptr_ch_dis_comp_u +{ + struct gsi_hwio_def_gsi_iram_ptr_ch_dis_comp_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_IRAM_PTR_CH_EMPTY +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_iram_ptr_ch_empty_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_iram_ptr_ch_empty_u +{ + struct gsi_hwio_def_gsi_iram_ptr_ch_empty_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_IRAM_PTR_EVENT_GEN_COMP +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_iram_ptr_event_gen_comp_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_iram_ptr_event_gen_comp_u +{ + struct gsi_hwio_def_gsi_iram_ptr_event_gen_comp_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_iram_ptr_periph_if_tlv_in_0_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_iram_ptr_periph_if_tlv_in_0_u +{ + struct gsi_hwio_def_gsi_iram_ptr_periph_if_tlv_in_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_iram_ptr_periph_if_tlv_in_2_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_iram_ptr_periph_if_tlv_in_2_u +{ + struct gsi_hwio_def_gsi_iram_ptr_periph_if_tlv_in_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_iram_ptr_periph_if_tlv_in_1_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_iram_ptr_periph_if_tlv_in_1_u +{ + struct gsi_hwio_def_gsi_iram_ptr_periph_if_tlv_in_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_IRAM_PTR_TIMER_EXPIRED +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_iram_ptr_timer_expired_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_iram_ptr_timer_expired_u +{ + struct gsi_hwio_def_gsi_iram_ptr_timer_expired_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_IRAM_PTR_WRITE_ENG_COMP +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_iram_ptr_write_eng_comp_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_iram_ptr_write_eng_comp_u +{ + struct gsi_hwio_def_gsi_iram_ptr_write_eng_comp_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_IRAM_PTR_READ_ENG_COMP +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_iram_ptr_read_eng_comp_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_iram_ptr_read_eng_comp_u +{ + struct gsi_hwio_def_gsi_iram_ptr_read_eng_comp_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_IRAM_PTR_UC_GP_INT +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_iram_ptr_uc_gp_int_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_iram_ptr_uc_gp_int_u +{ + struct gsi_hwio_def_gsi_iram_ptr_uc_gp_int_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_IRAM_PTR_INT_MOD_STOPED +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_iram_ptr_int_mod_stoped_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_iram_ptr_int_mod_stoped_u +{ + struct gsi_hwio_def_gsi_iram_ptr_int_mod_stoped_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_IRAM_PTR_INT_NOTIFY_MCS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_iram_ptr_int_notify_mcs_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_iram_ptr_int_notify_mcs_u +{ + struct gsi_hwio_def_gsi_iram_ptr_int_notify_mcs_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_INST_RAM_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_inst_ram_n_s +{ + u32 inst_byte_0 : 8; + u32 inst_byte_1 : 8; + u32 inst_byte_2 : 8; + u32 inst_byte_3 : 8; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_inst_ram_n_u +{ + struct gsi_hwio_def_gsi_inst_ram_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_SHRAM_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_shram_n_s +{ + u32 shram : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_shram_n_u +{ + struct gsi_hwio_def_gsi_shram_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_MAP_EE_n_CH_k_VP_TABLE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_map_ee_n_ch_k_vp_table_s +{ + u32 phy_ch : 8; + u32 valid : 1; + u32 reserved0 : 23; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_map_ee_n_ch_k_vp_table_u +{ + struct gsi_hwio_def_gsi_map_ee_n_ch_k_vp_table_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_TEST_BUS_SEL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_test_bus_sel_s +{ + u32 gsi_testbus_sel : 8; + u32 reserved0 : 8; + u32 gsi_hw_events_sel : 4; + u32 reserved1 : 12; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_test_bus_sel_u +{ + struct gsi_hwio_def_gsi_test_bus_sel_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_TEST_BUS_REG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_test_bus_reg_s +{ + u32 gsi_testbus_reg : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_test_bus_reg_u +{ + struct gsi_hwio_def_gsi_test_bus_reg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_DEBUG_BUSY_REG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_debug_busy_reg_s +{ + u32 csr_busy : 1; + u32 ree_busy : 1; + u32 mcs_busy : 1; + u32 timer_busy : 1; + u32 rd_wr_busy : 1; + u32 ev_eng_busy : 1; + u32 int_eng_busy : 1; + u32 ree_pwr_clps_busy : 1; + u32 db_eng_busy : 1; + u32 dbg_cnt_busy : 1; + u32 uc_busy : 1; + u32 ic_busy : 1; + u32 sdma_busy : 1; + u32 reserved0 : 19; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_debug_busy_reg_u +{ + struct gsi_hwio_def_gsi_debug_busy_reg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_DEBUG_EVENT_PENDING_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_debug_event_pending_k_s +{ + u32 chid_bit_map : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_debug_event_pending_k_u +{ + struct gsi_hwio_def_gsi_debug_event_pending_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_DEBUG_TIMER_PENDING_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_debug_timer_pending_k_s +{ + u32 chid_bit_map : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_debug_timer_pending_k_u +{ + struct gsi_hwio_def_gsi_debug_timer_pending_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_DEBUG_RD_WR_PENDING_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_debug_rd_wr_pending_k_s +{ + u32 chid_bit_map : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_debug_rd_wr_pending_k_u +{ + struct gsi_hwio_def_gsi_debug_rd_wr_pending_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_SPARE_REG_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_spare_reg_1_s +{ + u32 fix_ieob_wrong_msk_disable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_spare_reg_1_u +{ + struct gsi_hwio_def_gsi_spare_reg_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_DEBUG_PC_FROM_SW +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_debug_pc_from_sw_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_debug_pc_from_sw_u +{ + struct gsi_hwio_def_gsi_debug_pc_from_sw_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_DEBUG_SW_STALL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_debug_sw_stall_s +{ + u32 mcs_stall : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_debug_sw_stall_u +{ + struct gsi_hwio_def_gsi_debug_sw_stall_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_DEBUG_PC_FOR_DEBUG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_debug_pc_for_debug_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_debug_pc_for_debug_u +{ + struct gsi_hwio_def_gsi_debug_pc_for_debug_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_DEBUG_QSB_LOG_SEL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_debug_qsb_log_sel_s +{ + u32 sel_write : 1; + u32 reserved0 : 7; + u32 sel_tid : 8; + u32 sel_mid : 8; + u32 reserved1 : 8; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_debug_qsb_log_sel_u +{ + struct gsi_hwio_def_gsi_debug_qsb_log_sel_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_DEBUG_QSB_LOG_CLR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_debug_qsb_log_clr_s +{ + u32 log_clr : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_debug_qsb_log_clr_u +{ + struct gsi_hwio_def_gsi_debug_qsb_log_clr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_DEBUG_QSB_LOG_ERR_TRNS_ID +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_debug_qsb_log_err_trns_id_s +{ + u32 err_write : 1; + u32 reserved0 : 7; + u32 err_tid : 8; + u32 err_mid : 8; + u32 err_saved : 1; + u32 reserved1 : 7; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_debug_qsb_log_err_trns_id_u +{ + struct gsi_hwio_def_gsi_debug_qsb_log_err_trns_id_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_DEBUG_QSB_LOG_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_debug_qsb_log_0_s +{ + u32 addr_31_0 : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_debug_qsb_log_0_u +{ + struct gsi_hwio_def_gsi_debug_qsb_log_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_DEBUG_QSB_LOG_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_debug_qsb_log_1_s +{ + u32 addr_43_32 : 12; + u32 ainnershared : 1; + u32 anoallocate : 1; + u32 ashared : 1; + u32 acacheable : 1; + u32 atransient : 1; + u32 aooord : 1; + u32 aooowr : 1; + u32 reserved0 : 1; + u32 alen : 4; + u32 asize : 4; + u32 areqpriority : 4; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_debug_qsb_log_1_u +{ + struct gsi_hwio_def_gsi_debug_qsb_log_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_DEBUG_QSB_LOG_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_debug_qsb_log_2_s +{ + u32 ammusid : 12; + u32 amemtype : 4; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_debug_qsb_log_2_u +{ + struct gsi_hwio_def_gsi_debug_qsb_log_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_DEBUG_QSB_LOG_LAST_MISC_IDn +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_debug_qsb_log_last_misc_idn_s +{ + u32 addr_20_0 : 21; + u32 write : 1; + u32 tid : 5; + u32 mid : 5; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_debug_qsb_log_last_misc_idn_u +{ + struct gsi_hwio_def_gsi_debug_qsb_log_last_misc_idn_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_DEBUG_SW_RF_n_WRITE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_debug_sw_rf_n_write_s +{ + u32 data_in : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_debug_sw_rf_n_write_u +{ + struct gsi_hwio_def_gsi_debug_sw_rf_n_write_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_DEBUG_SW_RF_n_READ +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_debug_sw_rf_n_read_s +{ + u32 rf_reg : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_debug_sw_rf_n_read_u +{ + struct gsi_hwio_def_gsi_debug_sw_rf_n_read_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_DEBUG_COUNTER_CFGn +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_debug_counter_cfgn_s +{ + u32 enable : 1; + u32 stop_at_wrap_arnd : 1; + u32 clr_at_read : 1; + u32 evnt_type : 5; + u32 ee : 4; + u32 virtual_chnl : 8; + u32 chain : 1; + u32 reserved0 : 11; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_debug_counter_cfgn_u +{ + struct gsi_hwio_def_gsi_debug_counter_cfgn_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_DEBUG_COUNTERn +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_debug_countern_s +{ + u32 counter_value : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_debug_countern_u +{ + struct gsi_hwio_def_gsi_debug_countern_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_DEBUG_SW_MSK_REG_n_SEC_k_WR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_debug_sw_msk_reg_n_sec_k_wr_s +{ + u32 data_in : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_debug_sw_msk_reg_n_sec_k_wr_u +{ + struct gsi_hwio_def_gsi_debug_sw_msk_reg_n_sec_k_wr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_debug_sw_msk_reg_n_sec_k_rd_s +{ + u32 msk_reg : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_debug_sw_msk_reg_n_sec_k_rd_u +{ + struct gsi_hwio_def_gsi_debug_sw_msk_reg_n_sec_k_rd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_DEBUG_EE_n_CH_k_VP_TABLE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_debug_ee_n_ch_k_vp_table_s +{ + u32 phy_ch : 8; + u32 valid : 1; + u32 reserved0 : 23; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_debug_ee_n_ch_k_vp_table_u +{ + struct gsi_hwio_def_gsi_debug_ee_n_ch_k_vp_table_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_DEBUG_EE_n_EV_k_VP_TABLE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_debug_ee_n_ev_k_vp_table_s +{ + u32 phy_ev_ch : 8; + u32 valid : 1; + u32 reserved0 : 23; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_debug_ee_n_ev_k_vp_table_u +{ + struct gsi_hwio_def_gsi_debug_ee_n_ev_k_vp_table_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_DEBUG_REE_PREFETCH_BUF_CH_ID +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_debug_ree_prefetch_buf_ch_id_s +{ + u32 prefetch_buf_ch_id : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_debug_ree_prefetch_buf_ch_id_u +{ + struct gsi_hwio_def_gsi_debug_ree_prefetch_buf_ch_id_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_DEBUG_REE_PREFETCH_BUF_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_debug_ree_prefetch_buf_status_s +{ + u32 prefetch_buf_status : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_debug_ree_prefetch_buf_status_u +{ + struct gsi_hwio_def_gsi_debug_ree_prefetch_buf_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_MCS_PROFILING_BP_CNT_LSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_mcs_profiling_bp_cnt_lsb_s +{ + u32 bp_cnt_lsb : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_mcs_profiling_bp_cnt_lsb_u +{ + struct gsi_hwio_def_gsi_mcs_profiling_bp_cnt_lsb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_MCS_PROFILING_BP_CNT_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_mcs_profiling_bp_cnt_msb_s +{ + u32 bp_cnt_msb : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_mcs_profiling_bp_cnt_msb_u +{ + struct gsi_hwio_def_gsi_mcs_profiling_bp_cnt_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_mcs_profiling_bp_and_pending_cnt_lsb_s +{ + u32 bp_and_pending_cnt_lsb : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_mcs_profiling_bp_and_pending_cnt_lsb_u +{ + struct gsi_hwio_def_gsi_mcs_profiling_bp_and_pending_cnt_lsb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_mcs_profiling_bp_and_pending_cnt_msb_s +{ + u32 bp_and_pending_cnt_msb : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_mcs_profiling_bp_and_pending_cnt_msb_u +{ + struct gsi_hwio_def_gsi_mcs_profiling_bp_and_pending_cnt_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_mcs_profiling_mcs_busy_cnt_lsb_s +{ + u32 mcs_busy_cnt_lsb : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_mcs_profiling_mcs_busy_cnt_lsb_u +{ + struct gsi_hwio_def_gsi_mcs_profiling_mcs_busy_cnt_lsb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_mcs_profiling_mcs_busy_cnt_msb_s +{ + u32 mcs_busy_cnt_msb : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_mcs_profiling_mcs_busy_cnt_msb_u +{ + struct gsi_hwio_def_gsi_mcs_profiling_mcs_busy_cnt_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_mcs_profiling_mcs_idle_cnt_lsb_s +{ + u32 mcs_idle_cnt_lsb : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_mcs_profiling_mcs_idle_cnt_lsb_u +{ + struct gsi_hwio_def_gsi_mcs_profiling_mcs_idle_cnt_lsb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_mcs_profiling_mcs_idle_cnt_msb_s +{ + u32 mcs_idle_cnt_msb : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_mcs_profiling_mcs_idle_cnt_msb_u +{ + struct gsi_hwio_def_gsi_mcs_profiling_mcs_idle_cnt_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_CH_k_CNTXT_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_0_s +{ + u32 chtype_protocol : 7; + u32 chtype_dir : 1; + u32 ee : 4; + u32 chid : 8; + u32 chstate : 4; + u32 element_size : 8; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_0_u +{ + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_CH_k_CNTXT_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_1_s +{ + u32 r_length : 24; + u32 erindex : 8; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_1_u +{ + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_CH_k_CNTXT_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_2_s +{ + u32 r_base_addr_lsbs : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_2_u +{ + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_CH_k_CNTXT_3 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_3_s +{ + u32 r_base_addr_msbs : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_3_u +{ + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_3_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_CH_k_CNTXT_4 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_4_s +{ + u32 read_ptr_lsb : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_4_u +{ + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_4_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_CH_k_CNTXT_5 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_5_s +{ + u32 read_ptr_msb : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_5_u +{ + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_5_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_CH_k_CNTXT_6 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_6_s +{ + u32 write_ptr_lsb : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_6_u +{ + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_6_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_CH_k_CNTXT_7 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_7_s +{ + u32 write_ptr_msb : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_7_u +{ + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_7_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_CH_k_CNTXT_8 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_8_s +{ + u32 db_msi_data : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_8_u +{ + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_8_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_CH_k_ELEM_SIZE_SHIFT +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_ch_k_elem_size_shift_s +{ + u32 elem_size_shift : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_ch_k_elem_size_shift_u +{ + struct gsi_hwio_def_ee_n_gsi_ch_k_elem_size_shift_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_ch_k_ch_almst_empty_thrshold_s +{ + u32 ch_almst_empty_thrshold : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_ch_k_ch_almst_empty_thrshold_u +{ + struct gsi_hwio_def_ee_n_gsi_ch_k_ch_almst_empty_thrshold_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_CH_k_RE_FETCH_READ_PTR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_ch_k_re_fetch_read_ptr_s +{ + u32 read_ptr : 24; + u32 reserved0 : 8; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_ch_k_re_fetch_read_ptr_u +{ + struct gsi_hwio_def_ee_n_gsi_ch_k_re_fetch_read_ptr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_ch_k_re_fetch_write_ptr_s +{ + u32 re_intr_db : 24; + u32 reserved0 : 8; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_ch_k_re_fetch_write_ptr_u +{ + struct gsi_hwio_def_ee_n_gsi_ch_k_re_fetch_write_ptr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_CH_k_QOS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_ch_k_qos_s +{ + u32 wrr_weight : 4; + u32 reserved0 : 4; + u32 max_prefetch : 1; + u32 use_db_eng : 1; + u32 prefetch_mode : 4; + u32 reserved1 : 2; + u32 empty_lvl_thrshold : 8; + u32 db_in_bytes : 1; + u32 low_latency_en : 1; + u32 reserved2 : 6; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_ch_k_qos_u +{ + struct gsi_hwio_def_ee_n_gsi_ch_k_qos_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_CH_k_SCRATCH_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_0_s +{ + u32 scratch : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_ch_k_scratch_0_u +{ + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_CH_k_SCRATCH_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_1_s +{ + u32 scratch : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_ch_k_scratch_1_u +{ + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_CH_k_SCRATCH_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_2_s +{ + u32 scratch : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_ch_k_scratch_2_u +{ + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_CH_k_SCRATCH_3 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_3_s +{ + u32 scratch : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_ch_k_scratch_3_u +{ + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_3_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_CH_k_SCRATCH_4 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_4_s +{ + u32 scratch : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_ch_k_scratch_4_u +{ + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_4_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_CH_k_SCRATCH_5 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_5_s +{ + u32 scratch : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_ch_k_scratch_5_u +{ + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_5_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_CH_k_SCRATCH_6 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_6_s +{ + u32 scratch : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_ch_k_scratch_6_u +{ + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_6_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_CH_k_SCRATCH_7 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_7_s +{ + u32 scratch : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_ch_k_scratch_7_u +{ + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_7_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_CH_k_SCRATCH_8 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_8_s +{ + u32 scratch : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_ch_k_scratch_8_u +{ + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_8_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_CH_k_SCRATCH_9 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_9_s +{ + u32 scratch : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_ch_k_scratch_9_u +{ + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_9_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_CH_k_DB_ENG_WRITE_PTR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_ch_k_db_eng_write_ptr_s +{ + u32 last_db_2_mcs : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_ch_k_db_eng_write_ptr_u +{ + struct gsi_hwio_def_ee_n_gsi_ch_k_db_eng_write_ptr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_EV_CH_k_CNTXT_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_0_s +{ + u32 chtype : 7; + u32 intype : 1; + u32 evchid : 8; + u32 ee : 4; + u32 chstate : 4; + u32 element_size : 8; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_0_u +{ + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_EV_CH_k_CNTXT_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_1_s +{ + u32 r_length : 24; + u32 reserved0 : 8; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_1_u +{ + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_EV_CH_k_CNTXT_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_2_s +{ + u32 r_base_addr_lsbs : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_2_u +{ + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_EV_CH_k_CNTXT_3 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_3_s +{ + u32 r_base_addr_msbs : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_3_u +{ + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_3_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_EV_CH_k_CNTXT_4 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_4_s +{ + u32 read_ptr_lsb : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_4_u +{ + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_4_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_EV_CH_k_CNTXT_5 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_5_s +{ + u32 read_ptr_msb : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_5_u +{ + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_5_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_EV_CH_k_CNTXT_6 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_6_s +{ + u32 write_ptr_lsb : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_6_u +{ + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_6_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_EV_CH_k_CNTXT_7 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_7_s +{ + u32 write_ptr_msb : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_7_u +{ + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_7_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_EV_CH_k_CNTXT_8 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_8_s +{ + u32 int_modt : 16; + u32 int_modc : 8; + u32 int_mod_cnt : 8; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_8_u +{ + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_8_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_EV_CH_k_CNTXT_9 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_9_s +{ + u32 intvec : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_9_u +{ + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_9_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_EV_CH_k_CNTXT_10 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_10_s +{ + u32 msi_addr_lsb : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_10_u +{ + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_10_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_EV_CH_k_CNTXT_11 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_11_s +{ + u32 msi_addr_msb : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_11_u +{ + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_11_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_EV_CH_k_CNTXT_12 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_12_s +{ + u32 rp_update_addr_lsb : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_12_u +{ + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_12_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_EV_CH_k_CNTXT_13 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_13_s +{ + u32 rp_update_addr_msb : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_13_u +{ + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_13_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_EV_CH_k_ELEM_SIZE_SHIFT +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_ev_ch_k_elem_size_shift_s +{ + u32 elem_size_shift : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_ev_ch_k_elem_size_shift_u +{ + struct gsi_hwio_def_ee_n_ev_ch_k_elem_size_shift_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_EV_CH_k_SCRATCH_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_ev_ch_k_scratch_0_s +{ + u32 scratch : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_ev_ch_k_scratch_0_u +{ + struct gsi_hwio_def_ee_n_ev_ch_k_scratch_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_EV_CH_k_SCRATCH_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_ev_ch_k_scratch_1_s +{ + u32 scratch : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_ev_ch_k_scratch_1_u +{ + struct gsi_hwio_def_ee_n_ev_ch_k_scratch_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_EV_CH_k_SCRATCH_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_ev_ch_k_scratch_2_s +{ + u32 scratch : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_ev_ch_k_scratch_2_u +{ + struct gsi_hwio_def_ee_n_ev_ch_k_scratch_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_CH_k_DOORBELL_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_ch_k_doorbell_0_s +{ + u32 write_ptr_lsb : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_ch_k_doorbell_0_u +{ + struct gsi_hwio_def_ee_n_gsi_ch_k_doorbell_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_CH_k_DOORBELL_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_ch_k_doorbell_1_s +{ + u32 write_ptr_msb : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_ch_k_doorbell_1_u +{ + struct gsi_hwio_def_ee_n_gsi_ch_k_doorbell_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_EV_CH_k_DOORBELL_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_ev_ch_k_doorbell_0_s +{ + u32 write_ptr_lsb : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_ev_ch_k_doorbell_0_u +{ + struct gsi_hwio_def_ee_n_ev_ch_k_doorbell_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_EV_CH_k_DOORBELL_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_ev_ch_k_doorbell_1_s +{ + u32 write_ptr_msb : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_ev_ch_k_doorbell_1_u +{ + struct gsi_hwio_def_ee_n_ev_ch_k_doorbell_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_status_s +{ + u32 enabled : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_status_u +{ + struct gsi_hwio_def_ee_n_gsi_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_CH_CMD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_ch_cmd_s +{ + u32 chid : 8; + u32 reserved0 : 16; + u32 opcode : 8; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_ch_cmd_u +{ + struct gsi_hwio_def_ee_n_gsi_ch_cmd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_EV_CH_CMD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_ev_ch_cmd_s +{ + u32 chid : 8; + u32 reserved0 : 16; + u32 opcode : 8; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_ev_ch_cmd_u +{ + struct gsi_hwio_def_ee_n_ev_ch_cmd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_EE_GENERIC_CMD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_ee_generic_cmd_s +{ + u32 opcode : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_ee_generic_cmd_u +{ + struct gsi_hwio_def_ee_n_gsi_ee_generic_cmd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_HW_PARAM_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_hw_param_0_s +{ + u32 gsi_ev_ch_num : 8; + u32 gsi_ch_num : 8; + u32 num_ees : 5; + u32 periph_conf_addr_bus_w : 5; + u32 periph_sec_grp : 5; + u32 use_axi_m : 1; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_hw_param_0_u +{ + struct gsi_hwio_def_ee_n_gsi_hw_param_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_HW_PARAM_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_hw_param_1_s +{ + u32 gsi_m_data_bus_w : 8; + u32 gsi_num_qad : 4; + u32 gsi_nonsec_en : 4; + u32 gsi_sec_en : 1; + u32 gsi_vmidacr_en : 1; + u32 gsi_qrib_en : 1; + u32 gsi_use_xpu : 1; + u32 gsi_num_timers : 5; + u32 gsi_use_bp_mtrix : 1; + u32 gsi_use_db_eng : 1; + u32 gsi_use_uc_if : 1; + u32 gsi_escape_buf_only : 1; + u32 gsi_simple_rd_wr : 1; + u32 gsi_blk_int_access_region_1_en : 1; + u32 gsi_blk_int_access_region_2_en : 1; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_hw_param_1_u +{ + struct gsi_hwio_def_ee_n_gsi_hw_param_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_HW_PARAM_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_hw_param_2_s +{ + u32 gsi_num_ch_per_ee : 8; + u32 gsi_iram_size : 5; + u32 gsi_ch_pend_translate : 1; + u32 gsi_ch_full_logic : 1; + u32 gsi_use_sdma : 1; + u32 gsi_sdma_n_int : 3; + u32 gsi_sdma_max_burst : 8; + u32 gsi_sdma_n_iovec : 3; + u32 gsi_use_rd_wr_eng : 1; + u32 gsi_use_inter_ee : 1; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_hw_param_2_u +{ + struct gsi_hwio_def_ee_n_gsi_hw_param_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_MCS_CODE_VER +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_mcs_code_ver_s +{ + u32 ver : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_mcs_code_ver_u +{ + struct gsi_hwio_def_ee_n_gsi_mcs_code_ver_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_HW_PARAM_3 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_hw_param_3_s +{ + u32 gsi_sdma_max_os_rd : 4; + u32 gsi_sdma_max_os_wr : 4; + u32 gsi_num_prefetch_bufs : 4; + u32 gsi_m_addr_bus_w : 8; + u32 gsi_ree_max_burst_len : 5; + u32 gsi_use_irom : 1; + u32 gsi_use_vir_ch_if : 1; + u32 gsi_use_sleep_clk_div : 1; + u32 gsi_use_db_msi_mode : 1; + u32 reserved0 : 3; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_hw_param_3_u +{ + struct gsi_hwio_def_ee_n_gsi_hw_param_3_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_GSI_HW_PARAM_4 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_gsi_hw_param_4_s +{ + u32 gsi_num_ev_per_ee : 8; + u32 gsi_iram_protcol_cnt : 8; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_gsi_hw_param_4_u +{ + struct gsi_hwio_def_ee_n_gsi_hw_param_4_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_CNTXT_TYPE_IRQ +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_cntxt_type_irq_s +{ + u32 ch_ctrl : 1; + u32 ev_ctrl : 1; + u32 glob_ee : 1; + u32 ieob : 1; + u32 inter_ee_ch_ctrl : 1; + u32 inter_ee_ev_ctrl : 1; + u32 general : 1; + u32 reserved0 : 25; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_cntxt_type_irq_u +{ + struct gsi_hwio_def_ee_n_cntxt_type_irq_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_CNTXT_TYPE_IRQ_MSK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_cntxt_type_irq_msk_s +{ + u32 ch_ctrl : 1; + u32 ev_ctrl : 1; + u32 glob_ee : 1; + u32 ieob : 1; + u32 inter_ee_ch_ctrl : 1; + u32 inter_ee_ev_ctrl : 1; + u32 general : 1; + u32 reserved0 : 25; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_cntxt_type_irq_msk_u +{ + struct gsi_hwio_def_ee_n_cntxt_type_irq_msk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_CNTXT_SRC_GSI_CH_IRQ_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_k_s +{ + u32 gsi_ch_bit_map : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_k_u +{ + struct gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_msk_k_s +{ + u32 gsi_ch_bit_map_msk : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_msk_k_u +{ + struct gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_msk_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_clr_k_s +{ + u32 gsi_ch_bit_map : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_clr_k_u +{ + struct gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_clr_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_CNTXT_SRC_EV_CH_IRQ_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_k_s +{ + u32 ev_ch_bit_map : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_k_u +{ + struct gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_msk_k_s +{ + u32 ev_ch_bit_map_msk : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_msk_k_u +{ + struct gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_msk_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_clr_k_s +{ + u32 ev_ch_bit_map : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_clr_k_u +{ + struct gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_clr_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_CNTXT_SRC_IEOB_IRQ_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_cntxt_src_ieob_irq_k_s +{ + u32 ev_ch_bit_map : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_cntxt_src_ieob_irq_k_u +{ + struct gsi_hwio_def_ee_n_cntxt_src_ieob_irq_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_cntxt_src_ieob_irq_msk_k_s +{ + u32 ev_ch_bit_map_msk : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_cntxt_src_ieob_irq_msk_k_u +{ + struct gsi_hwio_def_ee_n_cntxt_src_ieob_irq_msk_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_CNTXT_SRC_IEOB_IRQ_CLR_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_cntxt_src_ieob_irq_clr_k_s +{ + u32 ev_ch_bit_map : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_cntxt_src_ieob_irq_clr_k_u +{ + struct gsi_hwio_def_ee_n_cntxt_src_ieob_irq_clr_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_CNTXT_GLOB_IRQ_STTS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_cntxt_glob_irq_stts_s +{ + u32 error_int : 1; + u32 gp_int1 : 1; + u32 gp_int2 : 1; + u32 gp_int3 : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_cntxt_glob_irq_stts_u +{ + struct gsi_hwio_def_ee_n_cntxt_glob_irq_stts_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_CNTXT_GLOB_IRQ_EN +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_cntxt_glob_irq_en_s +{ + u32 error_int : 1; + u32 gp_int1 : 1; + u32 gp_int2 : 1; + u32 gp_int3 : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_cntxt_glob_irq_en_u +{ + struct gsi_hwio_def_ee_n_cntxt_glob_irq_en_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_CNTXT_GLOB_IRQ_CLR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_cntxt_glob_irq_clr_s +{ + u32 error_int : 1; + u32 gp_int1 : 1; + u32 gp_int2 : 1; + u32 gp_int3 : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_cntxt_glob_irq_clr_u +{ + struct gsi_hwio_def_ee_n_cntxt_glob_irq_clr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_CNTXT_GSI_IRQ_STTS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_cntxt_gsi_irq_stts_s +{ + u32 gsi_break_point : 1; + u32 gsi_bus_error : 1; + u32 gsi_cmd_fifo_ovrflow : 1; + u32 gsi_mcs_stack_ovrflow : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_cntxt_gsi_irq_stts_u +{ + struct gsi_hwio_def_ee_n_cntxt_gsi_irq_stts_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_CNTXT_GSI_IRQ_EN +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_cntxt_gsi_irq_en_s +{ + u32 gsi_break_point : 1; + u32 gsi_bus_error : 1; + u32 gsi_cmd_fifo_ovrflow : 1; + u32 gsi_mcs_stack_ovrflow : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_cntxt_gsi_irq_en_u +{ + struct gsi_hwio_def_ee_n_cntxt_gsi_irq_en_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_CNTXT_GSI_IRQ_CLR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_cntxt_gsi_irq_clr_s +{ + u32 gsi_break_point : 1; + u32 gsi_bus_error : 1; + u32 gsi_cmd_fifo_ovrflow : 1; + u32 gsi_mcs_stack_ovrflow : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_cntxt_gsi_irq_clr_u +{ + struct gsi_hwio_def_ee_n_cntxt_gsi_irq_clr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_CNTXT_INTSET +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_cntxt_intset_s +{ + u32 intype : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_cntxt_intset_u +{ + struct gsi_hwio_def_ee_n_cntxt_intset_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_CNTXT_MSI_BASE_LSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_cntxt_msi_base_lsb_s +{ + u32 msi_addr_lsb : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_cntxt_msi_base_lsb_u +{ + struct gsi_hwio_def_ee_n_cntxt_msi_base_lsb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_CNTXT_MSI_BASE_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_cntxt_msi_base_msb_s +{ + u32 msi_addr_msb : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_cntxt_msi_base_msb_u +{ + struct gsi_hwio_def_ee_n_cntxt_msi_base_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_CNTXT_INT_VEC +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_cntxt_int_vec_s +{ + u32 int_vec : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_cntxt_int_vec_u +{ + struct gsi_hwio_def_ee_n_cntxt_int_vec_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_ERROR_LOG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_error_log_s +{ + u32 error_log : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_error_log_u +{ + struct gsi_hwio_def_ee_n_error_log_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_ERROR_LOG_CLR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_error_log_clr_s +{ + u32 error_log_clr : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_error_log_clr_u +{ + struct gsi_hwio_def_ee_n_error_log_clr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_CNTXT_SCRATCH_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_cntxt_scratch_0_s +{ + u32 scratch : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_cntxt_scratch_0_u +{ + struct gsi_hwio_def_ee_n_cntxt_scratch_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: EE_n_CNTXT_SCRATCH_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_ee_n_cntxt_scratch_1_s +{ + u32 scratch : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_ee_n_cntxt_scratch_1_u +{ + struct gsi_hwio_def_ee_n_cntxt_scratch_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_MCS_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_mcs_cfg_s +{ + u32 mcs_enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_mcs_cfg_u +{ + struct gsi_hwio_def_gsi_mcs_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_TZ_FW_AUTH_LOCK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_tz_fw_auth_lock_s +{ + u32 dis_iram_write : 1; + u32 dis_debug_shram_write : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_tz_fw_auth_lock_u +{ + struct gsi_hwio_def_gsi_tz_fw_auth_lock_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_MSA_FW_AUTH_LOCK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_msa_fw_auth_lock_s +{ + u32 dis_iram_write : 1; + u32 dis_debug_shram_write : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_msa_fw_auth_lock_u +{ + struct gsi_hwio_def_gsi_msa_fw_auth_lock_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GSI_SP_FW_AUTH_LOCK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_gsi_sp_fw_auth_lock_s +{ + u32 dis_iram_write : 1; + u32 dis_debug_shram_write : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union gsi_hwio_def_gsi_sp_fw_auth_lock_u +{ + struct gsi_hwio_def_gsi_sp_fw_auth_lock_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: INTER_EE_n_ORIGINATOR_EE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_inter_ee_n_originator_ee_s +{ + u32 ee_number : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union gsi_hwio_def_inter_ee_n_originator_ee_u +{ + struct gsi_hwio_def_inter_ee_n_originator_ee_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: INTER_EE_n_GSI_CH_CMD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_inter_ee_n_gsi_ch_cmd_s +{ + u32 chid : 8; + u32 reserved0 : 16; + u32 opcode : 8; +}; + +/* Union definition of register */ +union gsi_hwio_def_inter_ee_n_gsi_ch_cmd_u +{ + struct gsi_hwio_def_inter_ee_n_gsi_ch_cmd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: INTER_EE_n_EV_CH_CMD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_inter_ee_n_ev_ch_cmd_s +{ + u32 chid : 8; + u32 reserved0 : 16; + u32 opcode : 8; +}; + +/* Union definition of register */ +union gsi_hwio_def_inter_ee_n_ev_ch_cmd_u +{ + struct gsi_hwio_def_inter_ee_n_ev_ch_cmd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: INTER_EE_n_SRC_GSI_CH_IRQ_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_inter_ee_n_src_gsi_ch_irq_k_s +{ + u32 gsi_ch_bit_map : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_inter_ee_n_src_gsi_ch_irq_k_u +{ + struct gsi_hwio_def_inter_ee_n_src_gsi_ch_irq_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_inter_ee_n_src_gsi_ch_irq_msk_k_s +{ + u32 gsi_ch_bit_map_msk : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_inter_ee_n_src_gsi_ch_irq_msk_k_u +{ + struct gsi_hwio_def_inter_ee_n_src_gsi_ch_irq_msk_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: INTER_EE_n_SRC_GSI_CH_IRQ_CLR_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_inter_ee_n_src_gsi_ch_irq_clr_k_s +{ + u32 gsi_ch_bit_map : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_inter_ee_n_src_gsi_ch_irq_clr_k_u +{ + struct gsi_hwio_def_inter_ee_n_src_gsi_ch_irq_clr_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: INTER_EE_n_SRC_EV_CH_IRQ_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_inter_ee_n_src_ev_ch_irq_k_s +{ + u32 ev_ch_bit_map : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_inter_ee_n_src_ev_ch_irq_k_u +{ + struct gsi_hwio_def_inter_ee_n_src_ev_ch_irq_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: INTER_EE_n_SRC_EV_CH_IRQ_MSK_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_inter_ee_n_src_ev_ch_irq_msk_k_s +{ + u32 ev_ch_bit_map_msk : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_inter_ee_n_src_ev_ch_irq_msk_k_u +{ + struct gsi_hwio_def_inter_ee_n_src_ev_ch_irq_msk_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: INTER_EE_n_SRC_EV_CH_IRQ_CLR_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct gsi_hwio_def_inter_ee_n_src_ev_ch_irq_clr_k_s +{ + u32 ev_ch_bit_map : 32; +}; + +/* Union definition of register */ +union gsi_hwio_def_inter_ee_n_src_ev_ch_irq_clr_k_u +{ + struct gsi_hwio_def_inter_ee_n_src_ev_ch_irq_clr_k_s def; + u32 value; +}; + + +#endif /* __GSI_HWIO_DEF_H__ */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.5/ipa_access_control.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.5/ipa_access_control.h new file mode 100644 index 0000000000..d9c618a37c --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.5/ipa_access_control.h @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ +#if !defined(_IPA_ACCESS_CONTROL_H_) +#define _IPA_ACCESS_CONTROL_H_ + +#include "ipa_reg_dump.h" + +/* + * AA_COMBO - actual read, actual write + * AN_COMBO - actual read, no-op write + * NA_COMBO - no-op read, actual write + * NN_COMBO - no-op read, no-op write + */ + +/* + * The following is target specific. + */ +static struct reg_mem_access_map_t mem_access_map[] = { + /*------------------------------------------------------------*/ + /* Range Use when Use when */ + /* Begin End SD_ENABLED SD_DISABLED */ + /*------------------------------------------------------------*/ + { 0x04000, 0x04FFF, { &io_matrix[AN_COMBO], &io_matrix[AN_COMBO] } }, + { 0xA8000, 0xB8000, { &io_matrix[AN_COMBO], &io_matrix[AN_COMBO] } }, + { 0x05000, 0x0F000, { &io_matrix[AN_COMBO], &io_matrix[AN_COMBO] } }, + { 0x0F000, 0x10000, { &io_matrix[AN_COMBO], &io_matrix[AN_COMBO] } }, + { 0x18000, 0x2A000, { &io_matrix[AA_COMBO], &io_matrix[AA_COMBO] } }, + { 0x2A000, 0x3C000, { &io_matrix[AN_COMBO], &io_matrix[AN_COMBO] } }, + { 0x3C000, 0x4E000, { &io_matrix[AN_COMBO], &io_matrix[AN_COMBO] } }, + { 0x10000, 0x11000, { &io_matrix[AA_COMBO], &io_matrix[AA_COMBO] } }, + { 0x11000, 0x12000, { &io_matrix[NN_COMBO], &io_matrix[NN_COMBO] } }, + { 0x12000, 0x13000, { &io_matrix[NN_COMBO], &io_matrix[NN_COMBO] } }, + { 0x14C000, 0x14D000, { &io_matrix[AA_COMBO], &io_matrix[AA_COMBO] } }, + { 0x14D000, 0x14E000, { &io_matrix[NN_COMBO], &io_matrix[NN_COMBO] } }, + { 0x14E000, 0x150000, { &io_matrix[NN_COMBO], &io_matrix[NN_COMBO] } }, + { 0x140000, 0x148000, { &io_matrix[AA_COMBO], &io_matrix[AA_COMBO] } }, + { 0x148000, 0x14C000, { &io_matrix[AN_COMBO], &io_matrix[AN_COMBO] } }, + { 0x150000, 0x160000, { &io_matrix[AA_COMBO], &io_matrix[AA_COMBO] } }, + { 0x160000, 0x180000, { &io_matrix[AN_COMBO], &io_matrix[NN_COMBO] } }, + { 0x180000, 0x181000, { &io_matrix[NN_COMBO], &io_matrix[NN_COMBO] } }, + { 0x181000, 0x1A0000, { &io_matrix[AN_COMBO], &io_matrix[AN_COMBO] } }, + { 0x1A0000, 0x1C0000, { &io_matrix[AN_COMBO], &io_matrix[NN_COMBO] } }, + { 0x1C0000, 0x1C2000, { &io_matrix[NN_COMBO], &io_matrix[NN_COMBO] } }, + { 0x1C2000, 0x1C4000, { &io_matrix[AA_COMBO], &io_matrix[AA_COMBO] } }, + { 0x120000, 0x128000, { &io_matrix[NN_COMBO], &io_matrix[NN_COMBO] } }, +}; + +#endif /* #if !defined(_IPA_ACCESS_CONTROL_H_) */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.5/ipa_gcc_hwio.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.5/ipa_gcc_hwio.h new file mode 100644 index 0000000000..ffa3314ad0 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.5/ipa_gcc_hwio.h @@ -0,0 +1,108497 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef __IPA_GCC_HWIO_H__ +#define __IPA_GCC_HWIO_H__ +/** + @file ipa_gcc_hwio.h + @brief Auto-generated HWIO interface include file. + + This file contains HWIO register definitions for the following modules: + GCC_CLK_CTL_REG.* + + 'Include' filters applied: + 'Exclude' filters applied: RESERVED DUMMY + + Attribute definitions for the HWIO_*_ATTR macros are as follows: + 0x0: Command register + 0x1: Read-Only + 0x2: Write-Only + 0x3: Read/Write +*/ + +/*---------------------------------------------------------------------------- + * MODULE: GCC_CLK_CTL_REG + *--------------------------------------------------------------------------*/ + +#define GCC_CLK_CTL_REG_REG_BASE (CLK_CTL_BASE + 0x00010000) +#define GCC_CLK_CTL_REG_REG_BASE_PHYS (CLK_CTL_BASE_PHYS + 0x00010000) +#define GCC_CLK_CTL_REG_REG_BASE_OFFS 0x00010000 + +#define HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_ACGCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00067048) +#define HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_ACGCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00067048) +#define HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_ACGCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00067048) +#define HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_ACGCR_RMSK 0x1 +#define HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_ACGCR_ATTR 0x3 +#define HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_ACGCR_IN \ + in_dword_masked(HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_ACGCR_ADDR, HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_ACGCR_RMSK) +#define HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_ACGCR_INM(m) \ + in_dword_masked(HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_ACGCR_ADDR, m) +#define HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_ACGCR_OUT(v) \ + out_dword(HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_ACGCR_ADDR,v) +#define HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_ACGCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_ACGCR_IN) +#define HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_ACGCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_ACGCR_CLK_ENABLE_SHFT 0x0 + +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_ACGCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00067058) +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_ACGCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00067058) +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_ACGCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00067058) +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_ACGCR_RMSK 0x1 +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_ACGCR_ATTR 0x3 +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_ACGCR_IN \ + in_dword_masked(HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_ACGCR_ADDR, HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_ACGCR_RMSK) +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_ACGCR_INM(m) \ + in_dword_masked(HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_ACGCR_ADDR, m) +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_ACGCR_OUT(v) \ + out_dword(HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_ACGCR_ADDR,v) +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_ACGCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_ACGCR_IN) +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_ACGCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_ACGCR_CLK_ENABLE_SHFT 0x0 + +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_ACGCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000670d4) +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_ACGCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000670d4) +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_ACGCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000670d4) +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_ACGCR_RMSK 0x1 +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_ACGCR_ATTR 0x3 +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_ACGCR_IN \ + in_dword_masked(HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_ACGCR_ADDR, HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_ACGCR_RMSK) +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_ACGCR_INM(m) \ + in_dword_masked(HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_ACGCR_ADDR, m) +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_ACGCR_OUT(v) \ + out_dword(HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_ACGCR_ADDR,v) +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_ACGCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_ACGCR_IN) +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_ACGCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_ACGCR_CLK_ENABLE_SHFT 0x0 + +#define HWIO_GCC_USB3_PRIM_PHY_PIPE_MUXR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002906c) +#define HWIO_GCC_USB3_PRIM_PHY_PIPE_MUXR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002906c) +#define HWIO_GCC_USB3_PRIM_PHY_PIPE_MUXR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002906c) +#define HWIO_GCC_USB3_PRIM_PHY_PIPE_MUXR_RMSK 0x3 +#define HWIO_GCC_USB3_PRIM_PHY_PIPE_MUXR_ATTR 0x3 +#define HWIO_GCC_USB3_PRIM_PHY_PIPE_MUXR_IN \ + in_dword_masked(HWIO_GCC_USB3_PRIM_PHY_PIPE_MUXR_ADDR, HWIO_GCC_USB3_PRIM_PHY_PIPE_MUXR_RMSK) +#define HWIO_GCC_USB3_PRIM_PHY_PIPE_MUXR_INM(m) \ + in_dword_masked(HWIO_GCC_USB3_PRIM_PHY_PIPE_MUXR_ADDR, m) +#define HWIO_GCC_USB3_PRIM_PHY_PIPE_MUXR_OUT(v) \ + out_dword(HWIO_GCC_USB3_PRIM_PHY_PIPE_MUXR_ADDR,v) +#define HWIO_GCC_USB3_PRIM_PHY_PIPE_MUXR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB3_PRIM_PHY_PIPE_MUXR_ADDR,m,v,HWIO_GCC_USB3_PRIM_PHY_PIPE_MUXR_IN) +#define HWIO_GCC_USB3_PRIM_PHY_PIPE_MUXR_MUX_SEL_BMSK 0x3 +#define HWIO_GCC_USB3_PRIM_PHY_PIPE_MUXR_MUX_SEL_SHFT 0x0 + +#define HWIO_GCC_PCIE_0_PIPE_MUXR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005b070) +#define HWIO_GCC_PCIE_0_PIPE_MUXR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005b070) +#define HWIO_GCC_PCIE_0_PIPE_MUXR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005b070) +#define HWIO_GCC_PCIE_0_PIPE_MUXR_RMSK 0x3 +#define HWIO_GCC_PCIE_0_PIPE_MUXR_ATTR 0x3 +#define HWIO_GCC_PCIE_0_PIPE_MUXR_IN \ + in_dword_masked(HWIO_GCC_PCIE_0_PIPE_MUXR_ADDR, HWIO_GCC_PCIE_0_PIPE_MUXR_RMSK) +#define HWIO_GCC_PCIE_0_PIPE_MUXR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_0_PIPE_MUXR_ADDR, m) +#define HWIO_GCC_PCIE_0_PIPE_MUXR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_0_PIPE_MUXR_ADDR,v) +#define HWIO_GCC_PCIE_0_PIPE_MUXR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_0_PIPE_MUXR_ADDR,m,v,HWIO_GCC_PCIE_0_PIPE_MUXR_IN) +#define HWIO_GCC_PCIE_0_PIPE_MUXR_MUX_SEL_BMSK 0x3 +#define HWIO_GCC_PCIE_0_PIPE_MUXR_MUX_SEL_SHFT 0x0 + +#define HWIO_GCC_PCIE_0_MBIST_MUXR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005b08c) +#define HWIO_GCC_PCIE_0_MBIST_MUXR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005b08c) +#define HWIO_GCC_PCIE_0_MBIST_MUXR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005b08c) +#define HWIO_GCC_PCIE_0_MBIST_MUXR_RMSK 0x1 +#define HWIO_GCC_PCIE_0_MBIST_MUXR_ATTR 0x3 +#define HWIO_GCC_PCIE_0_MBIST_MUXR_IN \ + in_dword_masked(HWIO_GCC_PCIE_0_MBIST_MUXR_ADDR, HWIO_GCC_PCIE_0_MBIST_MUXR_RMSK) +#define HWIO_GCC_PCIE_0_MBIST_MUXR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_0_MBIST_MUXR_ADDR, m) +#define HWIO_GCC_PCIE_0_MBIST_MUXR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_0_MBIST_MUXR_ADDR,v) +#define HWIO_GCC_PCIE_0_MBIST_MUXR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_0_MBIST_MUXR_ADDR,m,v,HWIO_GCC_PCIE_0_MBIST_MUXR_IN) +#define HWIO_GCC_PCIE_0_MBIST_MUXR_MUX_SEL_BMSK 0x1 +#define HWIO_GCC_PCIE_0_MBIST_MUXR_MUX_SEL_SHFT 0x0 + +#define HWIO_GCC_PCIE_0_MBIST_PLL_TEST_SE_MUXR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005b090) +#define HWIO_GCC_PCIE_0_MBIST_PLL_TEST_SE_MUXR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005b090) +#define HWIO_GCC_PCIE_0_MBIST_PLL_TEST_SE_MUXR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005b090) +#define HWIO_GCC_PCIE_0_MBIST_PLL_TEST_SE_MUXR_RMSK 0x1 +#define HWIO_GCC_PCIE_0_MBIST_PLL_TEST_SE_MUXR_ATTR 0x3 +#define HWIO_GCC_PCIE_0_MBIST_PLL_TEST_SE_MUXR_IN \ + in_dword_masked(HWIO_GCC_PCIE_0_MBIST_PLL_TEST_SE_MUXR_ADDR, HWIO_GCC_PCIE_0_MBIST_PLL_TEST_SE_MUXR_RMSK) +#define HWIO_GCC_PCIE_0_MBIST_PLL_TEST_SE_MUXR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_0_MBIST_PLL_TEST_SE_MUXR_ADDR, m) +#define HWIO_GCC_PCIE_0_MBIST_PLL_TEST_SE_MUXR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_0_MBIST_PLL_TEST_SE_MUXR_ADDR,v) +#define HWIO_GCC_PCIE_0_MBIST_PLL_TEST_SE_MUXR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_0_MBIST_PLL_TEST_SE_MUXR_ADDR,m,v,HWIO_GCC_PCIE_0_MBIST_PLL_TEST_SE_MUXR_IN) +#define HWIO_GCC_PCIE_0_MBIST_PLL_TEST_SE_MUXR_MUX_SEL_BMSK 0x1 +#define HWIO_GCC_PCIE_0_MBIST_PLL_TEST_SE_MUXR_MUX_SEL_SHFT 0x0 + +#define HWIO_GCC_PCIE_1_PIPE_MUXR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007d078) +#define HWIO_GCC_PCIE_1_PIPE_MUXR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d078) +#define HWIO_GCC_PCIE_1_PIPE_MUXR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d078) +#define HWIO_GCC_PCIE_1_PIPE_MUXR_RMSK 0x3 +#define HWIO_GCC_PCIE_1_PIPE_MUXR_ATTR 0x3 +#define HWIO_GCC_PCIE_1_PIPE_MUXR_IN \ + in_dword_masked(HWIO_GCC_PCIE_1_PIPE_MUXR_ADDR, HWIO_GCC_PCIE_1_PIPE_MUXR_RMSK) +#define HWIO_GCC_PCIE_1_PIPE_MUXR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_1_PIPE_MUXR_ADDR, m) +#define HWIO_GCC_PCIE_1_PIPE_MUXR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_1_PIPE_MUXR_ADDR,v) +#define HWIO_GCC_PCIE_1_PIPE_MUXR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_1_PIPE_MUXR_ADDR,m,v,HWIO_GCC_PCIE_1_PIPE_MUXR_IN) +#define HWIO_GCC_PCIE_1_PIPE_MUXR_MUX_SEL_BMSK 0x3 +#define HWIO_GCC_PCIE_1_PIPE_MUXR_MUX_SEL_SHFT 0x0 + +#define HWIO_GCC_PCIE_1_PHY_AUX_MUXR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007d094) +#define HWIO_GCC_PCIE_1_PHY_AUX_MUXR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d094) +#define HWIO_GCC_PCIE_1_PHY_AUX_MUXR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d094) +#define HWIO_GCC_PCIE_1_PHY_AUX_MUXR_RMSK 0x3 +#define HWIO_GCC_PCIE_1_PHY_AUX_MUXR_ATTR 0x3 +#define HWIO_GCC_PCIE_1_PHY_AUX_MUXR_IN \ + in_dword_masked(HWIO_GCC_PCIE_1_PHY_AUX_MUXR_ADDR, HWIO_GCC_PCIE_1_PHY_AUX_MUXR_RMSK) +#define HWIO_GCC_PCIE_1_PHY_AUX_MUXR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_1_PHY_AUX_MUXR_ADDR, m) +#define HWIO_GCC_PCIE_1_PHY_AUX_MUXR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_1_PHY_AUX_MUXR_ADDR,v) +#define HWIO_GCC_PCIE_1_PHY_AUX_MUXR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_1_PHY_AUX_MUXR_ADDR,m,v,HWIO_GCC_PCIE_1_PHY_AUX_MUXR_IN) +#define HWIO_GCC_PCIE_1_PHY_AUX_MUXR_MUX_SEL_BMSK 0x3 +#define HWIO_GCC_PCIE_1_PHY_AUX_MUXR_MUX_SEL_SHFT 0x0 + +#define HWIO_GCC_PCIE_1_MBIST_MUXR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007d098) +#define HWIO_GCC_PCIE_1_MBIST_MUXR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d098) +#define HWIO_GCC_PCIE_1_MBIST_MUXR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d098) +#define HWIO_GCC_PCIE_1_MBIST_MUXR_RMSK 0x1 +#define HWIO_GCC_PCIE_1_MBIST_MUXR_ATTR 0x3 +#define HWIO_GCC_PCIE_1_MBIST_MUXR_IN \ + in_dword_masked(HWIO_GCC_PCIE_1_MBIST_MUXR_ADDR, HWIO_GCC_PCIE_1_MBIST_MUXR_RMSK) +#define HWIO_GCC_PCIE_1_MBIST_MUXR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_1_MBIST_MUXR_ADDR, m) +#define HWIO_GCC_PCIE_1_MBIST_MUXR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_1_MBIST_MUXR_ADDR,v) +#define HWIO_GCC_PCIE_1_MBIST_MUXR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_1_MBIST_MUXR_ADDR,m,v,HWIO_GCC_PCIE_1_MBIST_MUXR_IN) +#define HWIO_GCC_PCIE_1_MBIST_MUXR_MUX_SEL_BMSK 0x1 +#define HWIO_GCC_PCIE_1_MBIST_MUXR_MUX_SEL_SHFT 0x0 + +#define HWIO_GCC_PCIE_1_MBIST_PLL_TEST_SE_MUXR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007d09c) +#define HWIO_GCC_PCIE_1_MBIST_PLL_TEST_SE_MUXR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d09c) +#define HWIO_GCC_PCIE_1_MBIST_PLL_TEST_SE_MUXR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d09c) +#define HWIO_GCC_PCIE_1_MBIST_PLL_TEST_SE_MUXR_RMSK 0x1 +#define HWIO_GCC_PCIE_1_MBIST_PLL_TEST_SE_MUXR_ATTR 0x3 +#define HWIO_GCC_PCIE_1_MBIST_PLL_TEST_SE_MUXR_IN \ + in_dword_masked(HWIO_GCC_PCIE_1_MBIST_PLL_TEST_SE_MUXR_ADDR, HWIO_GCC_PCIE_1_MBIST_PLL_TEST_SE_MUXR_RMSK) +#define HWIO_GCC_PCIE_1_MBIST_PLL_TEST_SE_MUXR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_1_MBIST_PLL_TEST_SE_MUXR_ADDR, m) +#define HWIO_GCC_PCIE_1_MBIST_PLL_TEST_SE_MUXR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_1_MBIST_PLL_TEST_SE_MUXR_ADDR,v) +#define HWIO_GCC_PCIE_1_MBIST_PLL_TEST_SE_MUXR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_1_MBIST_PLL_TEST_SE_MUXR_ADDR,m,v,HWIO_GCC_PCIE_1_MBIST_PLL_TEST_SE_MUXR_IN) +#define HWIO_GCC_PCIE_1_MBIST_PLL_TEST_SE_MUXR_MUX_SEL_BMSK 0x1 +#define HWIO_GCC_PCIE_1_MBIST_PLL_TEST_SE_MUXR_MUX_SEL_SHFT 0x0 + +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_TX_SYMBOL_0_MUX_MUXR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00067050) +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_TX_SYMBOL_0_MUX_MUXR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00067050) +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_TX_SYMBOL_0_MUX_MUXR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00067050) +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_TX_SYMBOL_0_MUX_MUXR_RMSK 0x1 +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_TX_SYMBOL_0_MUX_MUXR_ATTR 0x3 +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_TX_SYMBOL_0_MUX_MUXR_IN \ + in_dword_masked(HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_TX_SYMBOL_0_MUX_MUXR_ADDR, HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_TX_SYMBOL_0_MUX_MUXR_RMSK) +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_TX_SYMBOL_0_MUX_MUXR_INM(m) \ + in_dword_masked(HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_TX_SYMBOL_0_MUX_MUXR_ADDR, m) +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_TX_SYMBOL_0_MUX_MUXR_OUT(v) \ + out_dword(HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_TX_SYMBOL_0_MUX_MUXR_ADDR,v) +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_TX_SYMBOL_0_MUX_MUXR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_TX_SYMBOL_0_MUX_MUXR_ADDR,m,v,HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_TX_SYMBOL_0_MUX_MUXR_IN) +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_TX_SYMBOL_0_MUX_MUXR_MUX_SEL_BMSK 0x1 +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_TX_SYMBOL_0_MUX_MUXR_MUX_SEL_SHFT 0x0 + +#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_MUXR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00067054) +#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_MUXR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00067054) +#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_MUXR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00067054) +#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_MUXR_RMSK 0x3 +#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_MUXR_ATTR 0x3 +#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_MUXR_IN \ + in_dword_masked(HWIO_GCC_UFS_PHY_TX_SYMBOL_0_MUXR_ADDR, HWIO_GCC_UFS_PHY_TX_SYMBOL_0_MUXR_RMSK) +#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_MUXR_INM(m) \ + in_dword_masked(HWIO_GCC_UFS_PHY_TX_SYMBOL_0_MUXR_ADDR, m) +#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_MUXR_OUT(v) \ + out_dword(HWIO_GCC_UFS_PHY_TX_SYMBOL_0_MUXR_ADDR,v) +#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_MUXR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_UFS_PHY_TX_SYMBOL_0_MUXR_ADDR,m,v,HWIO_GCC_UFS_PHY_TX_SYMBOL_0_MUXR_IN) +#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_MUXR_MUX_SEL_BMSK 0x3 +#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_MUXR_MUX_SEL_SHFT 0x0 + +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_0_MUX_MUXR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00067060) +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_0_MUX_MUXR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00067060) +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_0_MUX_MUXR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00067060) +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_0_MUX_MUXR_RMSK 0x1 +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_0_MUX_MUXR_ATTR 0x3 +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_0_MUX_MUXR_IN \ + in_dword_masked(HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_0_MUX_MUXR_ADDR, HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_0_MUX_MUXR_RMSK) +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_0_MUX_MUXR_INM(m) \ + in_dword_masked(HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_0_MUX_MUXR_ADDR, m) +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_0_MUX_MUXR_OUT(v) \ + out_dword(HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_0_MUX_MUXR_ADDR,v) +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_0_MUX_MUXR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_0_MUX_MUXR_ADDR,m,v,HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_0_MUX_MUXR_IN) +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_0_MUX_MUXR_MUX_SEL_BMSK 0x1 +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_0_MUX_MUXR_MUX_SEL_SHFT 0x0 + +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_MUXR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00067064) +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_MUXR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00067064) +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_MUXR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00067064) +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_MUXR_RMSK 0x3 +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_MUXR_ATTR 0x3 +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_MUXR_IN \ + in_dword_masked(HWIO_GCC_UFS_PHY_RX_SYMBOL_0_MUXR_ADDR, HWIO_GCC_UFS_PHY_RX_SYMBOL_0_MUXR_RMSK) +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_MUXR_INM(m) \ + in_dword_masked(HWIO_GCC_UFS_PHY_RX_SYMBOL_0_MUXR_ADDR, m) +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_MUXR_OUT(v) \ + out_dword(HWIO_GCC_UFS_PHY_RX_SYMBOL_0_MUXR_ADDR,v) +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_MUXR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_UFS_PHY_RX_SYMBOL_0_MUXR_ADDR,m,v,HWIO_GCC_UFS_PHY_RX_SYMBOL_0_MUXR_IN) +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_MUXR_MUX_SEL_BMSK 0x3 +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_MUXR_MUX_SEL_SHFT 0x0 + +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_1_MUX_MUXR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000670dc) +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_1_MUX_MUXR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000670dc) +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_1_MUX_MUXR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000670dc) +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_1_MUX_MUXR_RMSK 0x1 +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_1_MUX_MUXR_ATTR 0x3 +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_1_MUX_MUXR_IN \ + in_dword_masked(HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_1_MUX_MUXR_ADDR, HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_1_MUX_MUXR_RMSK) +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_1_MUX_MUXR_INM(m) \ + in_dword_masked(HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_1_MUX_MUXR_ADDR, m) +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_1_MUX_MUXR_OUT(v) \ + out_dword(HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_1_MUX_MUXR_ADDR,v) +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_1_MUX_MUXR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_1_MUX_MUXR_ADDR,m,v,HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_1_MUX_MUXR_IN) +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_1_MUX_MUXR_MUX_SEL_BMSK 0x1 +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_1_MUX_MUXR_MUX_SEL_SHFT 0x0 + +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_MUXR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000670e0) +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_MUXR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000670e0) +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_MUXR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000670e0) +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_MUXR_RMSK 0x3 +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_MUXR_ATTR 0x3 +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_MUXR_IN \ + in_dword_masked(HWIO_GCC_UFS_PHY_RX_SYMBOL_1_MUXR_ADDR, HWIO_GCC_UFS_PHY_RX_SYMBOL_1_MUXR_RMSK) +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_MUXR_INM(m) \ + in_dword_masked(HWIO_GCC_UFS_PHY_RX_SYMBOL_1_MUXR_ADDR, m) +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_MUXR_OUT(v) \ + out_dword(HWIO_GCC_UFS_PHY_RX_SYMBOL_1_MUXR_ADDR,v) +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_MUXR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_UFS_PHY_RX_SYMBOL_1_MUXR_ADDR,m,v,HWIO_GCC_UFS_PHY_RX_SYMBOL_1_MUXR_IN) +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_MUXR_MUX_SEL_BMSK 0x3 +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_MUXR_MUX_SEL_SHFT 0x0 + +#define HWIO_GCC_SYSTEM_NOC_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00066000) +#define HWIO_GCC_SYSTEM_NOC_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00066000) +#define HWIO_GCC_SYSTEM_NOC_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00066000) +#define HWIO_GCC_SYSTEM_NOC_BCR_RMSK 0x1 +#define HWIO_GCC_SYSTEM_NOC_BCR_ATTR 0x3 +#define HWIO_GCC_SYSTEM_NOC_BCR_IN \ + in_dword_masked(HWIO_GCC_SYSTEM_NOC_BCR_ADDR, HWIO_GCC_SYSTEM_NOC_BCR_RMSK) +#define HWIO_GCC_SYSTEM_NOC_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_SYSTEM_NOC_BCR_ADDR, m) +#define HWIO_GCC_SYSTEM_NOC_BCR_OUT(v) \ + out_dword(HWIO_GCC_SYSTEM_NOC_BCR_ADDR,v) +#define HWIO_GCC_SYSTEM_NOC_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SYSTEM_NOC_BCR_ADDR,m,v,HWIO_GCC_SYSTEM_NOC_BCR_IN) +#define HWIO_GCC_SYSTEM_NOC_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_SYSTEM_NOC_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_SYSTEM_NOC_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_SYSTEM_NOC_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003817c) +#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003817c) +#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003817c) +#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_RMSK 0x81c0000e +#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_ADDR, HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_RMSK) +#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_ADDR, m) +#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_ADDR,v) +#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_ADDR,m,v,HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_IN) +#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SYS_NOC_NAV_QX_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00005008) +#define HWIO_GCC_SYS_NOC_NAV_QX_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00005008) +#define HWIO_GCC_SYS_NOC_NAV_QX_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00005008) +#define HWIO_GCC_SYS_NOC_NAV_QX_CBCR_RMSK 0x81d00005 +#define HWIO_GCC_SYS_NOC_NAV_QX_CBCR_ATTR 0x3 +#define HWIO_GCC_SYS_NOC_NAV_QX_CBCR_IN \ + in_dword_masked(HWIO_GCC_SYS_NOC_NAV_QX_CBCR_ADDR, HWIO_GCC_SYS_NOC_NAV_QX_CBCR_RMSK) +#define HWIO_GCC_SYS_NOC_NAV_QX_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_SYS_NOC_NAV_QX_CBCR_ADDR, m) +#define HWIO_GCC_SYS_NOC_NAV_QX_CBCR_OUT(v) \ + out_dword(HWIO_GCC_SYS_NOC_NAV_QX_CBCR_ADDR,v) +#define HWIO_GCC_SYS_NOC_NAV_QX_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SYS_NOC_NAV_QX_CBCR_ADDR,m,v,HWIO_GCC_SYS_NOC_NAV_QX_CBCR_IN) +#define HWIO_GCC_SYS_NOC_NAV_QX_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SYS_NOC_NAV_QX_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SYS_NOC_NAV_QX_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_SYS_NOC_NAV_QX_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_SYS_NOC_NAV_QX_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_SYS_NOC_NAV_QX_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_SYS_NOC_NAV_QX_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_SYS_NOC_NAV_QX_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_SYS_NOC_NAV_QX_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_SYS_NOC_NAV_QX_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_SYS_NOC_NAV_QX_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_SYS_NOC_NAV_QX_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_SYS_NOC_NAV_QX_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_NAV_QX_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_NAV_QX_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SYS_NOC_NAV_QX_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SYS_NOC_NAV_QX_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_NAV_QX_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SYS_NOC_TME_QXM_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00024018) +#define HWIO_GCC_SYS_NOC_TME_QXM_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00024018) +#define HWIO_GCC_SYS_NOC_TME_QXM_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00024018) +#define HWIO_GCC_SYS_NOC_TME_QXM_CBCR_RMSK 0x81d00005 +#define HWIO_GCC_SYS_NOC_TME_QXM_CBCR_ATTR 0x3 +#define HWIO_GCC_SYS_NOC_TME_QXM_CBCR_IN \ + in_dword_masked(HWIO_GCC_SYS_NOC_TME_QXM_CBCR_ADDR, HWIO_GCC_SYS_NOC_TME_QXM_CBCR_RMSK) +#define HWIO_GCC_SYS_NOC_TME_QXM_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_SYS_NOC_TME_QXM_CBCR_ADDR, m) +#define HWIO_GCC_SYS_NOC_TME_QXM_CBCR_OUT(v) \ + out_dword(HWIO_GCC_SYS_NOC_TME_QXM_CBCR_ADDR,v) +#define HWIO_GCC_SYS_NOC_TME_QXM_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SYS_NOC_TME_QXM_CBCR_ADDR,m,v,HWIO_GCC_SYS_NOC_TME_QXM_CBCR_IN) +#define HWIO_GCC_SYS_NOC_TME_QXM_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SYS_NOC_TME_QXM_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SYS_NOC_TME_QXM_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_SYS_NOC_TME_QXM_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_SYS_NOC_TME_QXM_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_SYS_NOC_TME_QXM_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_SYS_NOC_TME_QXM_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_SYS_NOC_TME_QXM_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_SYS_NOC_TME_QXM_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_SYS_NOC_TME_QXM_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_SYS_NOC_TME_QXM_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_SYS_NOC_TME_QXM_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_SYS_NOC_TME_QXM_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_TME_QXM_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_TME_QXM_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SYS_NOC_TME_QXM_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SYS_NOC_TME_QXM_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_TME_QXM_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SYS_NOC_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00066004) +#define HWIO_GCC_SYS_NOC_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00066004) +#define HWIO_GCC_SYS_NOC_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00066004) +#define HWIO_GCC_SYS_NOC_AXI_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_SYS_NOC_AXI_CBCR_ATTR 0x3 +#define HWIO_GCC_SYS_NOC_AXI_CBCR_IN \ + in_dword_masked(HWIO_GCC_SYS_NOC_AXI_CBCR_ADDR, HWIO_GCC_SYS_NOC_AXI_CBCR_RMSK) +#define HWIO_GCC_SYS_NOC_AXI_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_SYS_NOC_AXI_CBCR_ADDR, m) +#define HWIO_GCC_SYS_NOC_AXI_CBCR_OUT(v) \ + out_dword(HWIO_GCC_SYS_NOC_AXI_CBCR_ADDR,v) +#define HWIO_GCC_SYS_NOC_AXI_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SYS_NOC_AXI_CBCR_ADDR,m,v,HWIO_GCC_SYS_NOC_AXI_CBCR_IN) +#define HWIO_GCC_SYS_NOC_AXI_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SYS_NOC_AXI_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SYS_NOC_AXI_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_SYS_NOC_AXI_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_SYS_NOC_AXI_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_SYS_NOC_AXI_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_SYS_NOC_AXI_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_SYS_NOC_AXI_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_SYS_NOC_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_SYS_NOC_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_SYS_NOC_AXI_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_SYS_NOC_AXI_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_SYS_NOC_AXI_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_SYS_NOC_AXI_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_SYS_NOC_AXI_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_AXI_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_AXI_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_SYS_NOC_AXI_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_SYS_NOC_AXI_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_AXI_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_AXI_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SYS_NOC_AXI_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SYS_NOC_AXI_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_AXI_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SYS_NOC_GC_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00066008) +#define HWIO_GCC_SYS_NOC_GC_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00066008) +#define HWIO_GCC_SYS_NOC_GC_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00066008) +#define HWIO_GCC_SYS_NOC_GC_AXI_CBCR_RMSK 0x81f0000f +#define HWIO_GCC_SYS_NOC_GC_AXI_CBCR_ATTR 0x3 +#define HWIO_GCC_SYS_NOC_GC_AXI_CBCR_IN \ + in_dword_masked(HWIO_GCC_SYS_NOC_GC_AXI_CBCR_ADDR, HWIO_GCC_SYS_NOC_GC_AXI_CBCR_RMSK) +#define HWIO_GCC_SYS_NOC_GC_AXI_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_SYS_NOC_GC_AXI_CBCR_ADDR, m) +#define HWIO_GCC_SYS_NOC_GC_AXI_CBCR_OUT(v) \ + out_dword(HWIO_GCC_SYS_NOC_GC_AXI_CBCR_ADDR,v) +#define HWIO_GCC_SYS_NOC_GC_AXI_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SYS_NOC_GC_AXI_CBCR_ADDR,m,v,HWIO_GCC_SYS_NOC_GC_AXI_CBCR_IN) +#define HWIO_GCC_SYS_NOC_GC_AXI_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SYS_NOC_GC_AXI_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SYS_NOC_GC_AXI_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_SYS_NOC_GC_AXI_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_SYS_NOC_GC_AXI_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_SYS_NOC_GC_AXI_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_SYS_NOC_GC_AXI_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_SYS_NOC_GC_AXI_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_SYS_NOC_GC_AXI_CBCR_IGNORE_PMU_CLK_DIS_BMSK 0x200000 +#define HWIO_GCC_SYS_NOC_GC_AXI_CBCR_IGNORE_PMU_CLK_DIS_SHFT 0x15 +#define HWIO_GCC_SYS_NOC_GC_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_SYS_NOC_GC_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_SYS_NOC_GC_AXI_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_SYS_NOC_GC_AXI_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_SYS_NOC_GC_AXI_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_SYS_NOC_GC_AXI_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_SYS_NOC_GC_AXI_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_GC_AXI_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_GC_AXI_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_SYS_NOC_GC_AXI_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_SYS_NOC_GC_AXI_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_GC_AXI_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_GC_AXI_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SYS_NOC_GC_AXI_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SYS_NOC_GC_AXI_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_GC_AXI_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006600c) +#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006600c) +#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006600c) +#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_RMSK 0x81f0700f +#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_ATTR 0x3 +#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_IN \ + in_dword_masked(HWIO_GCC_SYS_NOC_SF_AXI_CBCR_ADDR, HWIO_GCC_SYS_NOC_SF_AXI_CBCR_RMSK) +#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_SYS_NOC_SF_AXI_CBCR_ADDR, m) +#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_OUT(v) \ + out_dword(HWIO_GCC_SYS_NOC_SF_AXI_CBCR_ADDR,v) +#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SYS_NOC_SF_AXI_CBCR_ADDR,m,v,HWIO_GCC_SYS_NOC_SF_AXI_CBCR_IN) +#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_IGNORE_PMU_CLK_DIS_BMSK 0x200000 +#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_IGNORE_PMU_CLK_DIS_SHFT 0x15 +#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00066010) +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00066010) +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00066010) +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_RMSK 0xf1ffffe +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_ATTR 0x3 +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_IN \ + in_dword_masked(HWIO_GCC_SYS_NOC_SF_AXI_SREGR_ADDR, HWIO_GCC_SYS_NOC_SF_AXI_SREGR_RMSK) +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_SYS_NOC_SF_AXI_SREGR_ADDR, m) +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_OUT(v) \ + out_dword(HWIO_GCC_SYS_NOC_SF_AXI_SREGR_ADDR,v) +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SYS_NOC_SF_AXI_SREGR_ADDR,m,v,HWIO_GCC_SYS_NOC_SF_AXI_SREGR_IN) +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xf000000 +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_PWR_FSM_CLK_SEL_BMSK 0x100000 +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_PWR_FSM_CLK_SEL_SHFT 0x14 +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xf0000 +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_SF_AXI_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00066014) +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00066014) +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00066014) +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_SREGR_RMSK 0xffffffff +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_SREGR_ATTR 0x3 +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_SREGR_IN \ + in_dword_masked(HWIO_GCC_SYS_NOC_SF_AXI_CFG_SREGR_ADDR, HWIO_GCC_SYS_NOC_SF_AXI_CFG_SREGR_RMSK) +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_SYS_NOC_SF_AXI_CFG_SREGR_ADDR, m) +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_SREGR_OUT(v) \ + out_dword(HWIO_GCC_SYS_NOC_SF_AXI_CFG_SREGR_ADDR,v) +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SYS_NOC_SF_AXI_CFG_SREGR_ADDR,m,v,HWIO_GCC_SYS_NOC_SF_AXI_CFG_SREGR_IN) +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_SREGR_MEM_CORE_OFF_TIMER_BMSK 0xfc000000 +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_SREGR_MEM_CORE_OFF_TIMER_SHFT 0x1a +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_BMSK 0x2000000 +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_SHFT 0x19 +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_BMSK 0x1000000 +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_SHFT 0x18 +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_SREGR_MEM_PERIPH_ON_STATUS_BMSK 0x800000 +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_SREGR_MEM_PERIPH_ON_STATUS_SHFT 0x17 +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_SREGR_MEM_CORE_ON_STATUS_BMSK 0x400000 +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_SREGR_MEM_CORE_ON_STATUS_SHFT 0x16 +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_SREGR_MEM_CPH_TIMER_BMSK 0x3f0000 +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_SREGR_MEM_CPH_TIMER_SHFT 0x10 +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_SREGR_SLEEP_TIMER_BMSK 0xff00 +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_SREGR_SLEEP_TIMER_SHFT 0x8 +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_SREGR_WAKEUP_TIMER_BMSK 0xff +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_SREGR_WAKEUP_TIMER_SHFT 0x0 + +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00066018) +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00066018) +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00066018) +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_ATTR 0x3 +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_IN \ + in_dword_masked(HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_ADDR, HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_RMSK) +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_ADDR, m) +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_OUT(v) \ + out_dword(HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_ADDR,v) +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_ADDR,m,v,HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_IN) +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SYS_NOC_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006601c) +#define HWIO_GCC_SYS_NOC_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006601c) +#define HWIO_GCC_SYS_NOC_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006601c) +#define HWIO_GCC_SYS_NOC_AT_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_SYS_NOC_AT_CBCR_ATTR 0x3 +#define HWIO_GCC_SYS_NOC_AT_CBCR_IN \ + in_dword_masked(HWIO_GCC_SYS_NOC_AT_CBCR_ADDR, HWIO_GCC_SYS_NOC_AT_CBCR_RMSK) +#define HWIO_GCC_SYS_NOC_AT_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_SYS_NOC_AT_CBCR_ADDR, m) +#define HWIO_GCC_SYS_NOC_AT_CBCR_OUT(v) \ + out_dword(HWIO_GCC_SYS_NOC_AT_CBCR_ADDR,v) +#define HWIO_GCC_SYS_NOC_AT_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SYS_NOC_AT_CBCR_ADDR,m,v,HWIO_GCC_SYS_NOC_AT_CBCR_IN) +#define HWIO_GCC_SYS_NOC_AT_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SYS_NOC_AT_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SYS_NOC_AT_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_SYS_NOC_AT_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_SYS_NOC_AT_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_SYS_NOC_AT_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_SYS_NOC_AT_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_SYS_NOC_AT_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_SYS_NOC_AT_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_SYS_NOC_AT_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_SYS_NOC_AT_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_SYS_NOC_AT_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_SYS_NOC_AT_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_SYS_NOC_AT_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_SYS_NOC_AT_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_AT_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_AT_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_SYS_NOC_AT_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_SYS_NOC_AT_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_AT_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_AT_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SYS_NOC_AT_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SYS_NOC_AT_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_AT_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SYS_NOC_QOSGEN_EXTREF_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00066020) +#define HWIO_GCC_SYS_NOC_QOSGEN_EXTREF_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00066020) +#define HWIO_GCC_SYS_NOC_QOSGEN_EXTREF_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00066020) +#define HWIO_GCC_SYS_NOC_QOSGEN_EXTREF_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_SYS_NOC_QOSGEN_EXTREF_CBCR_ATTR 0x3 +#define HWIO_GCC_SYS_NOC_QOSGEN_EXTREF_CBCR_IN \ + in_dword_masked(HWIO_GCC_SYS_NOC_QOSGEN_EXTREF_CBCR_ADDR, HWIO_GCC_SYS_NOC_QOSGEN_EXTREF_CBCR_RMSK) +#define HWIO_GCC_SYS_NOC_QOSGEN_EXTREF_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_SYS_NOC_QOSGEN_EXTREF_CBCR_ADDR, m) +#define HWIO_GCC_SYS_NOC_QOSGEN_EXTREF_CBCR_OUT(v) \ + out_dword(HWIO_GCC_SYS_NOC_QOSGEN_EXTREF_CBCR_ADDR,v) +#define HWIO_GCC_SYS_NOC_QOSGEN_EXTREF_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SYS_NOC_QOSGEN_EXTREF_CBCR_ADDR,m,v,HWIO_GCC_SYS_NOC_QOSGEN_EXTREF_CBCR_IN) +#define HWIO_GCC_SYS_NOC_QOSGEN_EXTREF_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SYS_NOC_QOSGEN_EXTREF_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SYS_NOC_QOSGEN_EXTREF_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_SYS_NOC_QOSGEN_EXTREF_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_SYS_NOC_QOSGEN_EXTREF_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_SYS_NOC_QOSGEN_EXTREF_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_SYS_NOC_QOSGEN_EXTREF_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_SYS_NOC_QOSGEN_EXTREF_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_SYS_NOC_QOSGEN_EXTREF_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_SYS_NOC_QOSGEN_EXTREF_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_SYS_NOC_QOSGEN_EXTREF_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_QOSGEN_EXTREF_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_QOSGEN_EXTREF_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SYS_NOC_QOSGEN_EXTREF_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SYS_NOC_QOSGEN_EXTREF_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_QOSGEN_EXTREF_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SYS_NOC_TME_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00066024) +#define HWIO_GCC_SYS_NOC_TME_DCD_CDIV_DCDR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00066024) +#define HWIO_GCC_SYS_NOC_TME_DCD_CDIV_DCDR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00066024) +#define HWIO_GCC_SYS_NOC_TME_DCD_CDIV_DCDR_RMSK 0x1 +#define HWIO_GCC_SYS_NOC_TME_DCD_CDIV_DCDR_ATTR 0x3 +#define HWIO_GCC_SYS_NOC_TME_DCD_CDIV_DCDR_IN \ + in_dword_masked(HWIO_GCC_SYS_NOC_TME_DCD_CDIV_DCDR_ADDR, HWIO_GCC_SYS_NOC_TME_DCD_CDIV_DCDR_RMSK) +#define HWIO_GCC_SYS_NOC_TME_DCD_CDIV_DCDR_INM(m) \ + in_dword_masked(HWIO_GCC_SYS_NOC_TME_DCD_CDIV_DCDR_ADDR, m) +#define HWIO_GCC_SYS_NOC_TME_DCD_CDIV_DCDR_OUT(v) \ + out_dword(HWIO_GCC_SYS_NOC_TME_DCD_CDIV_DCDR_ADDR,v) +#define HWIO_GCC_SYS_NOC_TME_DCD_CDIV_DCDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SYS_NOC_TME_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_SYS_NOC_TME_DCD_CDIV_DCDR_IN) +#define HWIO_GCC_SYS_NOC_TME_DCD_CDIV_DCDR_DCD_ENABLE_BMSK 0x1 +#define HWIO_GCC_SYS_NOC_TME_DCD_CDIV_DCDR_DCD_ENABLE_SHFT 0x0 +#define HWIO_GCC_SYS_NOC_TME_DCD_CDIV_DCDR_DCD_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_TME_DCD_CDIV_DCDR_DCD_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SYS_NOC_NAV_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00066028) +#define HWIO_GCC_SYS_NOC_NAV_DCD_CDIV_DCDR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00066028) +#define HWIO_GCC_SYS_NOC_NAV_DCD_CDIV_DCDR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00066028) +#define HWIO_GCC_SYS_NOC_NAV_DCD_CDIV_DCDR_RMSK 0x1 +#define HWIO_GCC_SYS_NOC_NAV_DCD_CDIV_DCDR_ATTR 0x3 +#define HWIO_GCC_SYS_NOC_NAV_DCD_CDIV_DCDR_IN \ + in_dword_masked(HWIO_GCC_SYS_NOC_NAV_DCD_CDIV_DCDR_ADDR, HWIO_GCC_SYS_NOC_NAV_DCD_CDIV_DCDR_RMSK) +#define HWIO_GCC_SYS_NOC_NAV_DCD_CDIV_DCDR_INM(m) \ + in_dword_masked(HWIO_GCC_SYS_NOC_NAV_DCD_CDIV_DCDR_ADDR, m) +#define HWIO_GCC_SYS_NOC_NAV_DCD_CDIV_DCDR_OUT(v) \ + out_dword(HWIO_GCC_SYS_NOC_NAV_DCD_CDIV_DCDR_ADDR,v) +#define HWIO_GCC_SYS_NOC_NAV_DCD_CDIV_DCDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SYS_NOC_NAV_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_SYS_NOC_NAV_DCD_CDIV_DCDR_IN) +#define HWIO_GCC_SYS_NOC_NAV_DCD_CDIV_DCDR_DCD_ENABLE_BMSK 0x1 +#define HWIO_GCC_SYS_NOC_NAV_DCD_CDIV_DCDR_DCD_ENABLE_SHFT 0x0 +#define HWIO_GCC_SYS_NOC_NAV_DCD_CDIV_DCDR_DCD_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_NAV_DCD_CDIV_DCDR_DCD_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00066040) +#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00066040) +#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00066040) +#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_RMSK 0x3fffff +#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_RCG_SW_CTRL_BMSK 0x3f8000 +#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_RCG_SW_CTRL_SHFT 0xf +#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_SW_PERF_STATE_BMSK 0x7800 +#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_SW_PERF_STATE_SHFT 0xb +#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_SW_OVERRIDE_BMSK 0x400 +#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_SW_OVERRIDE_SHFT 0xa +#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK 0x200 +#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_DFS_FSM_STATE_BMSK 0x1c0 +#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_DFS_FSM_STATE_SHFT 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_HW_CLK_CONTROL_BMSK 0x20 +#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_HW_CLK_CONTROL_SHFT 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_CURR_PERF_STATE_BMSK 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_CURR_PERF_STATE_SHFT 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_DFS_EN_BMSK 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_DFS_EN_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_DFS_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_DFS_EN_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00066048) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00066048) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00066048) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006604c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006604c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006604c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00066050) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00066050) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00066050) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00066054) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00066054) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00066054) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00066058) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00066058) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00066058) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006605c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006605c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006605c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00066060) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00066060) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00066060) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00066064) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00066064) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00066064) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00066068) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00066068) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00066068) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006606c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006606c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006606c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00066070) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00066070) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00066070) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00066074) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00066074) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00066074) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00066078) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00066078) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00066078) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006607c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006607c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006607c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00066080) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00066080) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00066080) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00066084) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00066084) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00066084) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_SYS_NOC_GC_AXI_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006602c) +#define HWIO_GCC_SYS_NOC_GC_AXI_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006602c) +#define HWIO_GCC_SYS_NOC_GC_AXI_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006602c) +#define HWIO_GCC_SYS_NOC_GC_AXI_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_SYS_NOC_GC_AXI_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_SYS_NOC_GC_AXI_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_SYS_NOC_GC_AXI_CMD_RCGR_ADDR, HWIO_GCC_SYS_NOC_GC_AXI_CMD_RCGR_RMSK) +#define HWIO_GCC_SYS_NOC_GC_AXI_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_SYS_NOC_GC_AXI_CMD_RCGR_ADDR, m) +#define HWIO_GCC_SYS_NOC_GC_AXI_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_SYS_NOC_GC_AXI_CMD_RCGR_ADDR,v) +#define HWIO_GCC_SYS_NOC_GC_AXI_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SYS_NOC_GC_AXI_CMD_RCGR_ADDR,m,v,HWIO_GCC_SYS_NOC_GC_AXI_CMD_RCGR_IN) +#define HWIO_GCC_SYS_NOC_GC_AXI_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_SYS_NOC_GC_AXI_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_SYS_NOC_GC_AXI_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_SYS_NOC_GC_AXI_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_SYS_NOC_GC_AXI_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_SYS_NOC_GC_AXI_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_SYS_NOC_GC_AXI_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_GC_AXI_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_GC_AXI_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_SYS_NOC_GC_AXI_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_SYS_NOC_GC_AXI_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_GC_AXI_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00066030) +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00066030) +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00066030) +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_ADDR, HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_RMSK) +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_ADDR, m) +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_ADDR,v) +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_ADDR,m,v,HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_IN) +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_SYS_NOC_GC_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00066158) +#define HWIO_GCC_SYS_NOC_GC_DCD_CDIV_DCDR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00066158) +#define HWIO_GCC_SYS_NOC_GC_DCD_CDIV_DCDR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00066158) +#define HWIO_GCC_SYS_NOC_GC_DCD_CDIV_DCDR_RMSK 0x1 +#define HWIO_GCC_SYS_NOC_GC_DCD_CDIV_DCDR_ATTR 0x3 +#define HWIO_GCC_SYS_NOC_GC_DCD_CDIV_DCDR_IN \ + in_dword_masked(HWIO_GCC_SYS_NOC_GC_DCD_CDIV_DCDR_ADDR, HWIO_GCC_SYS_NOC_GC_DCD_CDIV_DCDR_RMSK) +#define HWIO_GCC_SYS_NOC_GC_DCD_CDIV_DCDR_INM(m) \ + in_dword_masked(HWIO_GCC_SYS_NOC_GC_DCD_CDIV_DCDR_ADDR, m) +#define HWIO_GCC_SYS_NOC_GC_DCD_CDIV_DCDR_OUT(v) \ + out_dword(HWIO_GCC_SYS_NOC_GC_DCD_CDIV_DCDR_ADDR,v) +#define HWIO_GCC_SYS_NOC_GC_DCD_CDIV_DCDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SYS_NOC_GC_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_SYS_NOC_GC_DCD_CDIV_DCDR_IN) +#define HWIO_GCC_SYS_NOC_GC_DCD_CDIV_DCDR_DCD_ENABLE_BMSK 0x1 +#define HWIO_GCC_SYS_NOC_GC_DCD_CDIV_DCDR_DCD_ENABLE_SHFT 0x0 +#define HWIO_GCC_SYS_NOC_GC_DCD_CDIV_DCDR_DCD_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_GC_DCD_CDIV_DCDR_DCD_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00066178) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00066178) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00066178) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006617c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006617c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006617c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00066180) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00066180) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00066180) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00066184) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00066184) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00066184) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00066188) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00066188) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00066188) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006618c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006618c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006618c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00066190) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00066190) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00066190) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00066194) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00066194) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00066194) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00066198) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00066198) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00066198) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006619c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006619c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006619c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000661a0) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000661a0) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000661a0) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000661a4) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000661a4) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000661a4) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000661a8) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000661a8) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000661a8) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000661ac) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000661ac) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000661ac) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000661b0) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000661b0) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000661b0) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000661b4) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000661b4) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000661b4) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_SYS_NOC_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006615c) +#define HWIO_GCC_SYS_NOC_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006615c) +#define HWIO_GCC_SYS_NOC_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006615c) +#define HWIO_GCC_SYS_NOC_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_SYS_NOC_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_SYS_NOC_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_SYS_NOC_CMD_RCGR_ADDR, HWIO_GCC_SYS_NOC_CMD_RCGR_RMSK) +#define HWIO_GCC_SYS_NOC_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_SYS_NOC_CMD_RCGR_ADDR, m) +#define HWIO_GCC_SYS_NOC_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_SYS_NOC_CMD_RCGR_ADDR,v) +#define HWIO_GCC_SYS_NOC_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SYS_NOC_CMD_RCGR_ADDR,m,v,HWIO_GCC_SYS_NOC_CMD_RCGR_IN) +#define HWIO_GCC_SYS_NOC_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_SYS_NOC_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_SYS_NOC_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_SYS_NOC_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_SYS_NOC_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_SYS_NOC_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_SYS_NOC_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_SYS_NOC_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_SYS_NOC_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SYS_NOC_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00066160) +#define HWIO_GCC_SYS_NOC_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00066160) +#define HWIO_GCC_SYS_NOC_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00066160) +#define HWIO_GCC_SYS_NOC_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_SYS_NOC_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_SYS_NOC_CFG_RCGR_ADDR, HWIO_GCC_SYS_NOC_CFG_RCGR_RMSK) +#define HWIO_GCC_SYS_NOC_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_SYS_NOC_CFG_RCGR_ADDR, m) +#define HWIO_GCC_SYS_NOC_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_SYS_NOC_CFG_RCGR_ADDR,v) +#define HWIO_GCC_SYS_NOC_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SYS_NOC_CFG_RCGR_ADDR,m,v,HWIO_GCC_SYS_NOC_CFG_RCGR_IN) +#define HWIO_GCC_SYS_NOC_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_SYS_NOC_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00066288) +#define HWIO_GCC_SYS_NOC_DCD_CDIV_DCDR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00066288) +#define HWIO_GCC_SYS_NOC_DCD_CDIV_DCDR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00066288) +#define HWIO_GCC_SYS_NOC_DCD_CDIV_DCDR_RMSK 0x1 +#define HWIO_GCC_SYS_NOC_DCD_CDIV_DCDR_ATTR 0x3 +#define HWIO_GCC_SYS_NOC_DCD_CDIV_DCDR_IN \ + in_dword_masked(HWIO_GCC_SYS_NOC_DCD_CDIV_DCDR_ADDR, HWIO_GCC_SYS_NOC_DCD_CDIV_DCDR_RMSK) +#define HWIO_GCC_SYS_NOC_DCD_CDIV_DCDR_INM(m) \ + in_dword_masked(HWIO_GCC_SYS_NOC_DCD_CDIV_DCDR_ADDR, m) +#define HWIO_GCC_SYS_NOC_DCD_CDIV_DCDR_OUT(v) \ + out_dword(HWIO_GCC_SYS_NOC_DCD_CDIV_DCDR_ADDR,v) +#define HWIO_GCC_SYS_NOC_DCD_CDIV_DCDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SYS_NOC_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_SYS_NOC_DCD_CDIV_DCDR_IN) +#define HWIO_GCC_SYS_NOC_DCD_CDIV_DCDR_DCD_ENABLE_BMSK 0x1 +#define HWIO_GCC_SYS_NOC_DCD_CDIV_DCDR_DCD_ENABLE_SHFT 0x0 +#define HWIO_GCC_SYS_NOC_DCD_CDIV_DCDR_DCD_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_DCD_CDIV_DCDR_DCD_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000662a8) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000662a8) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000662a8) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000662ac) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000662ac) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000662ac) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000662b0) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000662b0) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000662b0) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000662b4) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000662b4) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000662b4) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000662b8) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000662b8) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000662b8) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000662bc) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000662bc) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000662bc) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000662c0) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000662c0) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000662c0) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000662c4) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000662c4) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000662c4) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000662c8) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000662c8) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000662c8) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000662cc) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000662cc) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000662cc) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000662d0) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000662d0) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000662d0) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000662d4) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000662d4) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000662d4) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000662d8) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000662d8) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000662d8) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000662dc) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000662dc) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000662dc) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000662e0) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000662e0) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000662e0) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000662e4) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000662e4) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000662e4) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_SYS_NOC_SF_AXI_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006628c) +#define HWIO_GCC_SYS_NOC_SF_AXI_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006628c) +#define HWIO_GCC_SYS_NOC_SF_AXI_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006628c) +#define HWIO_GCC_SYS_NOC_SF_AXI_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_SYS_NOC_SF_AXI_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_SYS_NOC_SF_AXI_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_SYS_NOC_SF_AXI_CMD_RCGR_ADDR, HWIO_GCC_SYS_NOC_SF_AXI_CMD_RCGR_RMSK) +#define HWIO_GCC_SYS_NOC_SF_AXI_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_SYS_NOC_SF_AXI_CMD_RCGR_ADDR, m) +#define HWIO_GCC_SYS_NOC_SF_AXI_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_SYS_NOC_SF_AXI_CMD_RCGR_ADDR,v) +#define HWIO_GCC_SYS_NOC_SF_AXI_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SYS_NOC_SF_AXI_CMD_RCGR_ADDR,m,v,HWIO_GCC_SYS_NOC_SF_AXI_CMD_RCGR_IN) +#define HWIO_GCC_SYS_NOC_SF_AXI_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_SYS_NOC_SF_AXI_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_SYS_NOC_SF_AXI_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_SYS_NOC_SF_AXI_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_SYS_NOC_SF_AXI_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_SYS_NOC_SF_AXI_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_SYS_NOC_SF_AXI_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_SF_AXI_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_SF_AXI_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_SYS_NOC_SF_AXI_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_SYS_NOC_SF_AXI_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_SF_AXI_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00066290) +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00066290) +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00066290) +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_ADDR, HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_RMSK) +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_ADDR, m) +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_ADDR,v) +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_ADDR,m,v,HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_IN) +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_SYS_NOC_SF_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000663b8) +#define HWIO_GCC_SYS_NOC_SF_DCD_CDIV_DCDR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000663b8) +#define HWIO_GCC_SYS_NOC_SF_DCD_CDIV_DCDR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000663b8) +#define HWIO_GCC_SYS_NOC_SF_DCD_CDIV_DCDR_RMSK 0x1 +#define HWIO_GCC_SYS_NOC_SF_DCD_CDIV_DCDR_ATTR 0x3 +#define HWIO_GCC_SYS_NOC_SF_DCD_CDIV_DCDR_IN \ + in_dword_masked(HWIO_GCC_SYS_NOC_SF_DCD_CDIV_DCDR_ADDR, HWIO_GCC_SYS_NOC_SF_DCD_CDIV_DCDR_RMSK) +#define HWIO_GCC_SYS_NOC_SF_DCD_CDIV_DCDR_INM(m) \ + in_dword_masked(HWIO_GCC_SYS_NOC_SF_DCD_CDIV_DCDR_ADDR, m) +#define HWIO_GCC_SYS_NOC_SF_DCD_CDIV_DCDR_OUT(v) \ + out_dword(HWIO_GCC_SYS_NOC_SF_DCD_CDIV_DCDR_ADDR,v) +#define HWIO_GCC_SYS_NOC_SF_DCD_CDIV_DCDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SYS_NOC_SF_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_SYS_NOC_SF_DCD_CDIV_DCDR_IN) +#define HWIO_GCC_SYS_NOC_SF_DCD_CDIV_DCDR_DCD_ENABLE_BMSK 0x1 +#define HWIO_GCC_SYS_NOC_SF_DCD_CDIV_DCDR_DCD_ENABLE_SHFT 0x0 +#define HWIO_GCC_SYS_NOC_SF_DCD_CDIV_DCDR_DCD_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SYS_NOC_SF_DCD_CDIV_DCDR_DCD_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CONFIG_NOC_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064000) +#define HWIO_GCC_CONFIG_NOC_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064000) +#define HWIO_GCC_CONFIG_NOC_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064000) +#define HWIO_GCC_CONFIG_NOC_BCR_RMSK 0x1 +#define HWIO_GCC_CONFIG_NOC_BCR_ATTR 0x3 +#define HWIO_GCC_CONFIG_NOC_BCR_IN \ + in_dword_masked(HWIO_GCC_CONFIG_NOC_BCR_ADDR, HWIO_GCC_CONFIG_NOC_BCR_RMSK) +#define HWIO_GCC_CONFIG_NOC_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_CONFIG_NOC_BCR_ADDR, m) +#define HWIO_GCC_CONFIG_NOC_BCR_OUT(v) \ + out_dword(HWIO_GCC_CONFIG_NOC_BCR_ADDR,v) +#define HWIO_GCC_CONFIG_NOC_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CONFIG_NOC_BCR_ADDR,m,v,HWIO_GCC_CONFIG_NOC_BCR_IN) +#define HWIO_GCC_CONFIG_NOC_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_CONFIG_NOC_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_CONFIG_NOC_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_CONFIG_NOC_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CNOC_APSS_QH_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038180) +#define HWIO_GCC_CNOC_APSS_QH_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038180) +#define HWIO_GCC_CNOC_APSS_QH_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038180) +#define HWIO_GCC_CNOC_APSS_QH_CBCR_RMSK 0x81c0000f +#define HWIO_GCC_CNOC_APSS_QH_CBCR_ATTR 0x3 +#define HWIO_GCC_CNOC_APSS_QH_CBCR_IN \ + in_dword_masked(HWIO_GCC_CNOC_APSS_QH_CBCR_ADDR, HWIO_GCC_CNOC_APSS_QH_CBCR_RMSK) +#define HWIO_GCC_CNOC_APSS_QH_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_CNOC_APSS_QH_CBCR_ADDR, m) +#define HWIO_GCC_CNOC_APSS_QH_CBCR_OUT(v) \ + out_dword(HWIO_GCC_CNOC_APSS_QH_CBCR_ADDR,v) +#define HWIO_GCC_CNOC_APSS_QH_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CNOC_APSS_QH_CBCR_ADDR,m,v,HWIO_GCC_CNOC_APSS_QH_CBCR_IN) +#define HWIO_GCC_CNOC_APSS_QH_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_CNOC_APSS_QH_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_CNOC_APSS_QH_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_CNOC_APSS_QH_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_CNOC_APSS_QH_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_CNOC_APSS_QH_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_CNOC_APSS_QH_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_CNOC_APSS_QH_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_CNOC_APSS_QH_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_CNOC_APSS_QH_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_CNOC_APSS_QH_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_CNOC_APSS_QH_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_CNOC_APSS_QH_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_CNOC_APSS_QH_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_CNOC_APSS_QH_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_CNOC_APSS_QH_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_CNOC_APSS_QH_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_CNOC_APSS_QH_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_CNOC_APSS_QH_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_CNOC_APSS_QH_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_CNOC_APSS_QH_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CNOC_APSS_QH_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CNOC_CENTER_QX_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064004) +#define HWIO_GCC_CNOC_CENTER_QX_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064004) +#define HWIO_GCC_CNOC_CENTER_QX_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064004) +#define HWIO_GCC_CNOC_CENTER_QX_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_CNOC_CENTER_QX_CBCR_ATTR 0x3 +#define HWIO_GCC_CNOC_CENTER_QX_CBCR_IN \ + in_dword_masked(HWIO_GCC_CNOC_CENTER_QX_CBCR_ADDR, HWIO_GCC_CNOC_CENTER_QX_CBCR_RMSK) +#define HWIO_GCC_CNOC_CENTER_QX_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_CNOC_CENTER_QX_CBCR_ADDR, m) +#define HWIO_GCC_CNOC_CENTER_QX_CBCR_OUT(v) \ + out_dword(HWIO_GCC_CNOC_CENTER_QX_CBCR_ADDR,v) +#define HWIO_GCC_CNOC_CENTER_QX_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CNOC_CENTER_QX_CBCR_ADDR,m,v,HWIO_GCC_CNOC_CENTER_QX_CBCR_IN) +#define HWIO_GCC_CNOC_CENTER_QX_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_CNOC_CENTER_QX_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_CNOC_CENTER_QX_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_CNOC_CENTER_QX_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_CNOC_CENTER_QX_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_CNOC_CENTER_QX_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_CNOC_CENTER_QX_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_CNOC_CENTER_QX_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_CNOC_CENTER_QX_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_CNOC_CENTER_QX_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_CNOC_CENTER_QX_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_CNOC_CENTER_QX_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_CNOC_CENTER_QX_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_CNOC_CENTER_QX_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_CNOC_CENTER_QX_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_CNOC_CENTER_QX_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_CNOC_CENTER_QX_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_CNOC_CENTER_QX_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_CNOC_CENTER_QX_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_CNOC_CENTER_QX_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_CNOC_CENTER_QX_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_CNOC_CENTER_QX_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_CNOC_CENTER_QX_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CNOC_CENTER_QX_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CNOC_SF_QX_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064008) +#define HWIO_GCC_CNOC_SF_QX_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064008) +#define HWIO_GCC_CNOC_SF_QX_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064008) +#define HWIO_GCC_CNOC_SF_QX_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_CNOC_SF_QX_CBCR_ATTR 0x3 +#define HWIO_GCC_CNOC_SF_QX_CBCR_IN \ + in_dword_masked(HWIO_GCC_CNOC_SF_QX_CBCR_ADDR, HWIO_GCC_CNOC_SF_QX_CBCR_RMSK) +#define HWIO_GCC_CNOC_SF_QX_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_CNOC_SF_QX_CBCR_ADDR, m) +#define HWIO_GCC_CNOC_SF_QX_CBCR_OUT(v) \ + out_dword(HWIO_GCC_CNOC_SF_QX_CBCR_ADDR,v) +#define HWIO_GCC_CNOC_SF_QX_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CNOC_SF_QX_CBCR_ADDR,m,v,HWIO_GCC_CNOC_SF_QX_CBCR_IN) +#define HWIO_GCC_CNOC_SF_QX_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_CNOC_SF_QX_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_CNOC_SF_QX_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_CNOC_SF_QX_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_CNOC_SF_QX_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_CNOC_SF_QX_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_CNOC_SF_QX_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_CNOC_SF_QX_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_CNOC_SF_QX_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_CNOC_SF_QX_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_CNOC_SF_QX_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_CNOC_SF_QX_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_CNOC_SF_QX_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_CNOC_SF_QX_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_CNOC_SF_QX_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_CNOC_SF_QX_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_CNOC_SF_QX_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_CNOC_SF_QX_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_CNOC_SF_QX_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_CNOC_SF_QX_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_CNOC_SF_QX_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_CNOC_SF_QX_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_CNOC_SF_QX_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CNOC_SF_QX_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CNOC_NORTH_QX_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006400c) +#define HWIO_GCC_CNOC_NORTH_QX_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006400c) +#define HWIO_GCC_CNOC_NORTH_QX_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006400c) +#define HWIO_GCC_CNOC_NORTH_QX_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_CNOC_NORTH_QX_CBCR_ATTR 0x3 +#define HWIO_GCC_CNOC_NORTH_QX_CBCR_IN \ + in_dword_masked(HWIO_GCC_CNOC_NORTH_QX_CBCR_ADDR, HWIO_GCC_CNOC_NORTH_QX_CBCR_RMSK) +#define HWIO_GCC_CNOC_NORTH_QX_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_CNOC_NORTH_QX_CBCR_ADDR, m) +#define HWIO_GCC_CNOC_NORTH_QX_CBCR_OUT(v) \ + out_dword(HWIO_GCC_CNOC_NORTH_QX_CBCR_ADDR,v) +#define HWIO_GCC_CNOC_NORTH_QX_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CNOC_NORTH_QX_CBCR_ADDR,m,v,HWIO_GCC_CNOC_NORTH_QX_CBCR_IN) +#define HWIO_GCC_CNOC_NORTH_QX_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_CNOC_NORTH_QX_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_CNOC_NORTH_QX_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_CNOC_NORTH_QX_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_CNOC_NORTH_QX_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_CNOC_NORTH_QX_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_CNOC_NORTH_QX_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_CNOC_NORTH_QX_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_CNOC_NORTH_QX_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_CNOC_NORTH_QX_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_CNOC_NORTH_QX_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_CNOC_NORTH_QX_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_CNOC_NORTH_QX_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_CNOC_NORTH_QX_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_CNOC_NORTH_QX_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_CNOC_NORTH_QX_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_CNOC_NORTH_QX_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_CNOC_NORTH_QX_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_CNOC_NORTH_QX_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_CNOC_NORTH_QX_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_CNOC_NORTH_QX_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_CNOC_NORTH_QX_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_CNOC_NORTH_QX_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CNOC_NORTH_QX_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CNOC_PERIPH_SOUTH_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064010) +#define HWIO_GCC_CNOC_PERIPH_SOUTH_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064010) +#define HWIO_GCC_CNOC_PERIPH_SOUTH_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064010) +#define HWIO_GCC_CNOC_PERIPH_SOUTH_CBCR_RMSK 0x81d00005 +#define HWIO_GCC_CNOC_PERIPH_SOUTH_CBCR_ATTR 0x3 +#define HWIO_GCC_CNOC_PERIPH_SOUTH_CBCR_IN \ + in_dword_masked(HWIO_GCC_CNOC_PERIPH_SOUTH_CBCR_ADDR, HWIO_GCC_CNOC_PERIPH_SOUTH_CBCR_RMSK) +#define HWIO_GCC_CNOC_PERIPH_SOUTH_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_CNOC_PERIPH_SOUTH_CBCR_ADDR, m) +#define HWIO_GCC_CNOC_PERIPH_SOUTH_CBCR_OUT(v) \ + out_dword(HWIO_GCC_CNOC_PERIPH_SOUTH_CBCR_ADDR,v) +#define HWIO_GCC_CNOC_PERIPH_SOUTH_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CNOC_PERIPH_SOUTH_CBCR_ADDR,m,v,HWIO_GCC_CNOC_PERIPH_SOUTH_CBCR_IN) +#define HWIO_GCC_CNOC_PERIPH_SOUTH_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_CNOC_PERIPH_SOUTH_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_CNOC_PERIPH_SOUTH_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_CNOC_PERIPH_SOUTH_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_CNOC_PERIPH_SOUTH_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_CNOC_PERIPH_SOUTH_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_CNOC_PERIPH_SOUTH_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_CNOC_PERIPH_SOUTH_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_CNOC_PERIPH_SOUTH_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_CNOC_PERIPH_SOUTH_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_CNOC_PERIPH_SOUTH_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_CNOC_PERIPH_SOUTH_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_CNOC_PERIPH_SOUTH_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_CNOC_PERIPH_SOUTH_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_CNOC_PERIPH_SOUTH_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_CNOC_PERIPH_SOUTH_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_CNOC_PERIPH_SOUTH_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CNOC_PERIPH_SOUTH_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CNOC_PERIPH_NORTH_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064014) +#define HWIO_GCC_CNOC_PERIPH_NORTH_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064014) +#define HWIO_GCC_CNOC_PERIPH_NORTH_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064014) +#define HWIO_GCC_CNOC_PERIPH_NORTH_CBCR_RMSK 0x81d00005 +#define HWIO_GCC_CNOC_PERIPH_NORTH_CBCR_ATTR 0x3 +#define HWIO_GCC_CNOC_PERIPH_NORTH_CBCR_IN \ + in_dword_masked(HWIO_GCC_CNOC_PERIPH_NORTH_CBCR_ADDR, HWIO_GCC_CNOC_PERIPH_NORTH_CBCR_RMSK) +#define HWIO_GCC_CNOC_PERIPH_NORTH_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_CNOC_PERIPH_NORTH_CBCR_ADDR, m) +#define HWIO_GCC_CNOC_PERIPH_NORTH_CBCR_OUT(v) \ + out_dword(HWIO_GCC_CNOC_PERIPH_NORTH_CBCR_ADDR,v) +#define HWIO_GCC_CNOC_PERIPH_NORTH_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CNOC_PERIPH_NORTH_CBCR_ADDR,m,v,HWIO_GCC_CNOC_PERIPH_NORTH_CBCR_IN) +#define HWIO_GCC_CNOC_PERIPH_NORTH_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_CNOC_PERIPH_NORTH_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_CNOC_PERIPH_NORTH_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_CNOC_PERIPH_NORTH_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_CNOC_PERIPH_NORTH_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_CNOC_PERIPH_NORTH_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_CNOC_PERIPH_NORTH_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_CNOC_PERIPH_NORTH_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_CNOC_PERIPH_NORTH_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_CNOC_PERIPH_NORTH_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_CNOC_PERIPH_NORTH_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_CNOC_PERIPH_NORTH_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_CNOC_PERIPH_NORTH_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_CNOC_PERIPH_NORTH_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_CNOC_PERIPH_NORTH_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_CNOC_PERIPH_NORTH_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_CNOC_PERIPH_NORTH_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CNOC_PERIPH_NORTH_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CFG_NOC_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064018) +#define HWIO_GCC_CFG_NOC_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064018) +#define HWIO_GCC_CFG_NOC_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064018) +#define HWIO_GCC_CFG_NOC_AHB_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_CFG_NOC_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_CFG_NOC_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_CFG_NOC_AHB_CBCR_ADDR, HWIO_GCC_CFG_NOC_AHB_CBCR_RMSK) +#define HWIO_GCC_CFG_NOC_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_CFG_NOC_AHB_CBCR_ADDR, m) +#define HWIO_GCC_CFG_NOC_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_CFG_NOC_AHB_CBCR_ADDR,v) +#define HWIO_GCC_CFG_NOC_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CFG_NOC_AHB_CBCR_ADDR,m,v,HWIO_GCC_CFG_NOC_AHB_CBCR_IN) +#define HWIO_GCC_CFG_NOC_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_CFG_NOC_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_CFG_NOC_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_CFG_NOC_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_CFG_NOC_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_CFG_NOC_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_CFG_NOC_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_CFG_NOC_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_CFG_NOC_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_CFG_NOC_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_CFG_NOC_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_CFG_NOC_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_CFG_NOC_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_CFG_NOC_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_CFG_NOC_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_CFG_NOC_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_CFG_NOC_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_CFG_NOC_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_CFG_NOC_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_CFG_NOC_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_CFG_NOC_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_CFG_NOC_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_CFG_NOC_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CFG_NOC_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006401c) +#define HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006401c) +#define HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006401c) +#define HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_ADDR, HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_RMSK) +#define HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_ADDR, m) +#define HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_ADDR,v) +#define HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_ADDR,m,v,HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_IN) +#define HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000030) +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000030) +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000030) +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CBCR_RMSK 0x81d0700e +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CBCR_ATTR 0x3 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CBCR_IN \ + in_dword_masked(HWIO_GCC_CNOC_PCIE_SF_AXI_CBCR_ADDR, HWIO_GCC_CNOC_PCIE_SF_AXI_CBCR_RMSK) +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_CNOC_PCIE_SF_AXI_CBCR_ADDR, m) +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CBCR_OUT(v) \ + out_dword(HWIO_GCC_CNOC_PCIE_SF_AXI_CBCR_ADDR,v) +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CNOC_PCIE_SF_AXI_CBCR_ADDR,m,v,HWIO_GCC_CNOC_PCIE_SF_AXI_CBCR_IN) +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CBCR_HW_CTL_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000034) +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000034) +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000034) +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_RMSK 0xf1ffffe +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_ATTR 0x3 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_IN \ + in_dword_masked(HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_ADDR, HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_RMSK) +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_ADDR, m) +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_OUT(v) \ + out_dword(HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_ADDR,v) +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_ADDR,m,v,HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_IN) +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xf000000 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_PWR_FSM_CLK_SEL_BMSK 0x100000 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_PWR_FSM_CLK_SEL_SHFT 0x14 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xf0000 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CFG_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000038) +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CFG_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000038) +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CFG_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000038) +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CFG_SREGR_RMSK 0xffffffff +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CFG_SREGR_ATTR 0x3 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CFG_SREGR_IN \ + in_dword_masked(HWIO_GCC_CNOC_PCIE_SF_AXI_CFG_SREGR_ADDR, HWIO_GCC_CNOC_PCIE_SF_AXI_CFG_SREGR_RMSK) +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CFG_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_CNOC_PCIE_SF_AXI_CFG_SREGR_ADDR, m) +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CFG_SREGR_OUT(v) \ + out_dword(HWIO_GCC_CNOC_PCIE_SF_AXI_CFG_SREGR_ADDR,v) +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CFG_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CNOC_PCIE_SF_AXI_CFG_SREGR_ADDR,m,v,HWIO_GCC_CNOC_PCIE_SF_AXI_CFG_SREGR_IN) +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CFG_SREGR_MEM_CORE_OFF_TIMER_BMSK 0xfc000000 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CFG_SREGR_MEM_CORE_OFF_TIMER_SHFT 0x1a +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_BMSK 0x2000000 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_SHFT 0x19 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_BMSK 0x1000000 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_SHFT 0x18 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CFG_SREGR_MEM_PERIPH_ON_STATUS_BMSK 0x800000 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CFG_SREGR_MEM_PERIPH_ON_STATUS_SHFT 0x17 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CFG_SREGR_MEM_CORE_ON_STATUS_BMSK 0x400000 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CFG_SREGR_MEM_CORE_ON_STATUS_SHFT 0x16 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CFG_SREGR_MEM_CPH_TIMER_BMSK 0x3f0000 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CFG_SREGR_MEM_CPH_TIMER_SHFT 0x10 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CFG_SREGR_SLEEP_TIMER_BMSK 0xff00 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CFG_SREGR_SLEEP_TIMER_SHFT 0x8 +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CFG_SREGR_WAKEUP_TIMER_BMSK 0xff +#define HWIO_GCC_CNOC_PCIE_SF_AXI_CFG_SREGR_WAKEUP_TIMER_SHFT 0x0 + +#define HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064020) +#define HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064020) +#define HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064020) +#define HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_ADDR, HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_RMSK) +#define HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_ADDR, m) +#define HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_ADDR,v) +#define HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_ADDR,m,v,HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_IN) +#define HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CFG_NOC_EAST_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064024) +#define HWIO_GCC_CFG_NOC_EAST_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064024) +#define HWIO_GCC_CFG_NOC_EAST_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064024) +#define HWIO_GCC_CFG_NOC_EAST_AHB_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_CFG_NOC_EAST_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_CFG_NOC_EAST_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_CFG_NOC_EAST_AHB_CBCR_ADDR, HWIO_GCC_CFG_NOC_EAST_AHB_CBCR_RMSK) +#define HWIO_GCC_CFG_NOC_EAST_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_CFG_NOC_EAST_AHB_CBCR_ADDR, m) +#define HWIO_GCC_CFG_NOC_EAST_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_CFG_NOC_EAST_AHB_CBCR_ADDR,v) +#define HWIO_GCC_CFG_NOC_EAST_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CFG_NOC_EAST_AHB_CBCR_ADDR,m,v,HWIO_GCC_CFG_NOC_EAST_AHB_CBCR_IN) +#define HWIO_GCC_CFG_NOC_EAST_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_CFG_NOC_EAST_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_CFG_NOC_EAST_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_CFG_NOC_EAST_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_CFG_NOC_EAST_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_CFG_NOC_EAST_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_CFG_NOC_EAST_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_CFG_NOC_EAST_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_CFG_NOC_EAST_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_CFG_NOC_EAST_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_CFG_NOC_EAST_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_CFG_NOC_EAST_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_CFG_NOC_EAST_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_CFG_NOC_EAST_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_CFG_NOC_EAST_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_CFG_NOC_EAST_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_CFG_NOC_EAST_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_CFG_NOC_EAST_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_CFG_NOC_EAST_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_CFG_NOC_EAST_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_CFG_NOC_EAST_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_CFG_NOC_EAST_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_CFG_NOC_EAST_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CFG_NOC_EAST_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064028) +#define HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064028) +#define HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064028) +#define HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_ADDR, HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_RMSK) +#define HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_ADDR, m) +#define HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_ADDR,v) +#define HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_ADDR,m,v,HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_IN) +#define HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006402c) +#define HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006402c) +#define HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006402c) +#define HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_ADDR, HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_RMSK) +#define HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_ADDR, m) +#define HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_ADDR,v) +#define HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_ADDR,m,v,HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_IN) +#define HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CNOC_QDSS_STM_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064030) +#define HWIO_GCC_CNOC_QDSS_STM_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064030) +#define HWIO_GCC_CNOC_QDSS_STM_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064030) +#define HWIO_GCC_CNOC_QDSS_STM_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_CNOC_QDSS_STM_CBCR_ATTR 0x3 +#define HWIO_GCC_CNOC_QDSS_STM_CBCR_IN \ + in_dword_masked(HWIO_GCC_CNOC_QDSS_STM_CBCR_ADDR, HWIO_GCC_CNOC_QDSS_STM_CBCR_RMSK) +#define HWIO_GCC_CNOC_QDSS_STM_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_CNOC_QDSS_STM_CBCR_ADDR, m) +#define HWIO_GCC_CNOC_QDSS_STM_CBCR_OUT(v) \ + out_dword(HWIO_GCC_CNOC_QDSS_STM_CBCR_ADDR,v) +#define HWIO_GCC_CNOC_QDSS_STM_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CNOC_QDSS_STM_CBCR_ADDR,m,v,HWIO_GCC_CNOC_QDSS_STM_CBCR_IN) +#define HWIO_GCC_CNOC_QDSS_STM_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_CNOC_QDSS_STM_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_CNOC_QDSS_STM_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_CNOC_QDSS_STM_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_CNOC_QDSS_STM_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_CNOC_QDSS_STM_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_CNOC_QDSS_STM_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_CNOC_QDSS_STM_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_CNOC_QDSS_STM_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_CNOC_QDSS_STM_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_CNOC_QDSS_STM_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_CNOC_QDSS_STM_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_CNOC_QDSS_STM_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_CNOC_QDSS_STM_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_CNOC_QDSS_STM_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_CNOC_QDSS_STM_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_CNOC_QDSS_STM_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_CNOC_QDSS_STM_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_CNOC_QDSS_STM_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_CNOC_QDSS_STM_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_CNOC_QDSS_STM_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_CNOC_QDSS_STM_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_CNOC_QDSS_STM_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CNOC_QDSS_STM_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CFG_NOC_USB3_PRIM_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00029088) +#define HWIO_GCC_CFG_NOC_USB3_PRIM_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00029088) +#define HWIO_GCC_CFG_NOC_USB3_PRIM_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00029088) +#define HWIO_GCC_CFG_NOC_USB3_PRIM_AXI_CBCR_RMSK 0x81c0000f +#define HWIO_GCC_CFG_NOC_USB3_PRIM_AXI_CBCR_ATTR 0x3 +#define HWIO_GCC_CFG_NOC_USB3_PRIM_AXI_CBCR_IN \ + in_dword_masked(HWIO_GCC_CFG_NOC_USB3_PRIM_AXI_CBCR_ADDR, HWIO_GCC_CFG_NOC_USB3_PRIM_AXI_CBCR_RMSK) +#define HWIO_GCC_CFG_NOC_USB3_PRIM_AXI_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_CFG_NOC_USB3_PRIM_AXI_CBCR_ADDR, m) +#define HWIO_GCC_CFG_NOC_USB3_PRIM_AXI_CBCR_OUT(v) \ + out_dword(HWIO_GCC_CFG_NOC_USB3_PRIM_AXI_CBCR_ADDR,v) +#define HWIO_GCC_CFG_NOC_USB3_PRIM_AXI_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CFG_NOC_USB3_PRIM_AXI_CBCR_ADDR,m,v,HWIO_GCC_CFG_NOC_USB3_PRIM_AXI_CBCR_IN) +#define HWIO_GCC_CFG_NOC_USB3_PRIM_AXI_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_CFG_NOC_USB3_PRIM_AXI_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_CFG_NOC_USB3_PRIM_AXI_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_CFG_NOC_USB3_PRIM_AXI_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_CFG_NOC_USB3_PRIM_AXI_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_CFG_NOC_USB3_PRIM_AXI_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_CFG_NOC_USB3_PRIM_AXI_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_CFG_NOC_USB3_PRIM_AXI_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_CFG_NOC_USB3_PRIM_AXI_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_CFG_NOC_USB3_PRIM_AXI_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_CFG_NOC_USB3_PRIM_AXI_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_CFG_NOC_USB3_PRIM_AXI_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_CFG_NOC_USB3_PRIM_AXI_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_CFG_NOC_USB3_PRIM_AXI_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_CFG_NOC_USB3_PRIM_AXI_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_CFG_NOC_USB3_PRIM_AXI_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_CFG_NOC_USB3_PRIM_AXI_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_CFG_NOC_USB3_PRIM_AXI_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_CFG_NOC_USB3_PRIM_AXI_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_CFG_NOC_USB3_PRIM_AXI_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_CFG_NOC_USB3_PRIM_AXI_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CFG_NOC_USB3_PRIM_AXI_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CFG_NOC_LPASS_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003715c) +#define HWIO_GCC_CFG_NOC_LPASS_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003715c) +#define HWIO_GCC_CFG_NOC_LPASS_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003715c) +#define HWIO_GCC_CFG_NOC_LPASS_CBCR_RMSK 0x81d00005 +#define HWIO_GCC_CFG_NOC_LPASS_CBCR_ATTR 0x3 +#define HWIO_GCC_CFG_NOC_LPASS_CBCR_IN \ + in_dword_masked(HWIO_GCC_CFG_NOC_LPASS_CBCR_ADDR, HWIO_GCC_CFG_NOC_LPASS_CBCR_RMSK) +#define HWIO_GCC_CFG_NOC_LPASS_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_CFG_NOC_LPASS_CBCR_ADDR, m) +#define HWIO_GCC_CFG_NOC_LPASS_CBCR_OUT(v) \ + out_dword(HWIO_GCC_CFG_NOC_LPASS_CBCR_ADDR,v) +#define HWIO_GCC_CFG_NOC_LPASS_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CFG_NOC_LPASS_CBCR_ADDR,m,v,HWIO_GCC_CFG_NOC_LPASS_CBCR_IN) +#define HWIO_GCC_CFG_NOC_LPASS_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_CFG_NOC_LPASS_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_CFG_NOC_LPASS_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_CFG_NOC_LPASS_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_CFG_NOC_LPASS_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_CFG_NOC_LPASS_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_CFG_NOC_LPASS_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_CFG_NOC_LPASS_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_CFG_NOC_LPASS_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_CFG_NOC_LPASS_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_CFG_NOC_LPASS_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_CFG_NOC_LPASS_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_CFG_NOC_LPASS_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_CFG_NOC_LPASS_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_CFG_NOC_LPASS_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_CFG_NOC_LPASS_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_CFG_NOC_LPASS_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CFG_NOC_LPASS_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_NOC_WEST_DCD_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064034) +#define HWIO_GCC_NOC_WEST_DCD_XO_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064034) +#define HWIO_GCC_NOC_WEST_DCD_XO_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064034) +#define HWIO_GCC_NOC_WEST_DCD_XO_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_NOC_WEST_DCD_XO_CBCR_ATTR 0x3 +#define HWIO_GCC_NOC_WEST_DCD_XO_CBCR_IN \ + in_dword_masked(HWIO_GCC_NOC_WEST_DCD_XO_CBCR_ADDR, HWIO_GCC_NOC_WEST_DCD_XO_CBCR_RMSK) +#define HWIO_GCC_NOC_WEST_DCD_XO_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_NOC_WEST_DCD_XO_CBCR_ADDR, m) +#define HWIO_GCC_NOC_WEST_DCD_XO_CBCR_OUT(v) \ + out_dword(HWIO_GCC_NOC_WEST_DCD_XO_CBCR_ADDR,v) +#define HWIO_GCC_NOC_WEST_DCD_XO_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_NOC_WEST_DCD_XO_CBCR_ADDR,m,v,HWIO_GCC_NOC_WEST_DCD_XO_CBCR_IN) +#define HWIO_GCC_NOC_WEST_DCD_XO_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_NOC_WEST_DCD_XO_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_NOC_WEST_DCD_XO_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_NOC_WEST_DCD_XO_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_NOC_WEST_DCD_XO_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_NOC_WEST_DCD_XO_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_NOC_WEST_DCD_XO_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_NOC_WEST_DCD_XO_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_NOC_WEST_DCD_XO_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_NOC_WEST_DCD_XO_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_NOC_WEST_DCD_XO_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_NOC_WEST_DCD_XO_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_NOC_WEST_DCD_XO_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_NOC_WEST_DCD_XO_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_NOC_WEST_DCD_XO_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_NOC_WEST_DCD_XO_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_NOC_EAST_DCD_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064038) +#define HWIO_GCC_NOC_EAST_DCD_XO_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064038) +#define HWIO_GCC_NOC_EAST_DCD_XO_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064038) +#define HWIO_GCC_NOC_EAST_DCD_XO_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_NOC_EAST_DCD_XO_CBCR_ATTR 0x3 +#define HWIO_GCC_NOC_EAST_DCD_XO_CBCR_IN \ + in_dword_masked(HWIO_GCC_NOC_EAST_DCD_XO_CBCR_ADDR, HWIO_GCC_NOC_EAST_DCD_XO_CBCR_RMSK) +#define HWIO_GCC_NOC_EAST_DCD_XO_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_NOC_EAST_DCD_XO_CBCR_ADDR, m) +#define HWIO_GCC_NOC_EAST_DCD_XO_CBCR_OUT(v) \ + out_dword(HWIO_GCC_NOC_EAST_DCD_XO_CBCR_ADDR,v) +#define HWIO_GCC_NOC_EAST_DCD_XO_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_NOC_EAST_DCD_XO_CBCR_ADDR,m,v,HWIO_GCC_NOC_EAST_DCD_XO_CBCR_IN) +#define HWIO_GCC_NOC_EAST_DCD_XO_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_NOC_EAST_DCD_XO_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_NOC_EAST_DCD_XO_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_NOC_EAST_DCD_XO_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_NOC_EAST_DCD_XO_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_NOC_EAST_DCD_XO_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_NOC_EAST_DCD_XO_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_NOC_EAST_DCD_XO_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_NOC_EAST_DCD_XO_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_NOC_EAST_DCD_XO_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_NOC_EAST_DCD_XO_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_NOC_EAST_DCD_XO_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_NOC_EAST_DCD_XO_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_NOC_EAST_DCD_XO_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_NOC_EAST_DCD_XO_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_NOC_EAST_DCD_XO_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_NOC_NORTH_DCD_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006403c) +#define HWIO_GCC_NOC_NORTH_DCD_XO_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006403c) +#define HWIO_GCC_NOC_NORTH_DCD_XO_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006403c) +#define HWIO_GCC_NOC_NORTH_DCD_XO_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_NOC_NORTH_DCD_XO_CBCR_ATTR 0x3 +#define HWIO_GCC_NOC_NORTH_DCD_XO_CBCR_IN \ + in_dword_masked(HWIO_GCC_NOC_NORTH_DCD_XO_CBCR_ADDR, HWIO_GCC_NOC_NORTH_DCD_XO_CBCR_RMSK) +#define HWIO_GCC_NOC_NORTH_DCD_XO_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_NOC_NORTH_DCD_XO_CBCR_ADDR, m) +#define HWIO_GCC_NOC_NORTH_DCD_XO_CBCR_OUT(v) \ + out_dword(HWIO_GCC_NOC_NORTH_DCD_XO_CBCR_ADDR,v) +#define HWIO_GCC_NOC_NORTH_DCD_XO_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_NOC_NORTH_DCD_XO_CBCR_ADDR,m,v,HWIO_GCC_NOC_NORTH_DCD_XO_CBCR_IN) +#define HWIO_GCC_NOC_NORTH_DCD_XO_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_NOC_NORTH_DCD_XO_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_NOC_NORTH_DCD_XO_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_NOC_NORTH_DCD_XO_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_NOC_NORTH_DCD_XO_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_NOC_NORTH_DCD_XO_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_NOC_NORTH_DCD_XO_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_NOC_NORTH_DCD_XO_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_NOC_NORTH_DCD_XO_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_NOC_NORTH_DCD_XO_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_NOC_NORTH_DCD_XO_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_NOC_NORTH_DCD_XO_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_NOC_NORTH_DCD_XO_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_NOC_NORTH_DCD_XO_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_NOC_NORTH_DCD_XO_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_NOC_NORTH_DCD_XO_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_NOC_PCIE_NORTH_DCD_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000024) +#define HWIO_GCC_NOC_PCIE_NORTH_DCD_XO_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000024) +#define HWIO_GCC_NOC_PCIE_NORTH_DCD_XO_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000024) +#define HWIO_GCC_NOC_PCIE_NORTH_DCD_XO_CBCR_RMSK 0x81c00004 +#define HWIO_GCC_NOC_PCIE_NORTH_DCD_XO_CBCR_ATTR 0x3 +#define HWIO_GCC_NOC_PCIE_NORTH_DCD_XO_CBCR_IN \ + in_dword_masked(HWIO_GCC_NOC_PCIE_NORTH_DCD_XO_CBCR_ADDR, HWIO_GCC_NOC_PCIE_NORTH_DCD_XO_CBCR_RMSK) +#define HWIO_GCC_NOC_PCIE_NORTH_DCD_XO_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_NOC_PCIE_NORTH_DCD_XO_CBCR_ADDR, m) +#define HWIO_GCC_NOC_PCIE_NORTH_DCD_XO_CBCR_OUT(v) \ + out_dword(HWIO_GCC_NOC_PCIE_NORTH_DCD_XO_CBCR_ADDR,v) +#define HWIO_GCC_NOC_PCIE_NORTH_DCD_XO_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_NOC_PCIE_NORTH_DCD_XO_CBCR_ADDR,m,v,HWIO_GCC_NOC_PCIE_NORTH_DCD_XO_CBCR_IN) +#define HWIO_GCC_NOC_PCIE_NORTH_DCD_XO_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_NOC_PCIE_NORTH_DCD_XO_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_NOC_PCIE_NORTH_DCD_XO_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_NOC_PCIE_NORTH_DCD_XO_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_NOC_PCIE_NORTH_DCD_XO_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_NOC_PCIE_NORTH_DCD_XO_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_NOC_PCIE_NORTH_DCD_XO_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_NOC_PCIE_NORTH_DCD_XO_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_NOC_PCIE_NORTH_DCD_XO_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_NOC_PCIE_NORTH_DCD_XO_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_NOC_PCIE_NORTH_DCD_XO_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_NOC_PCIE_NORTH_DCD_XO_CBCR_CLK_ARES_RESET_FVAL 0x1 + +#define HWIO_GCC_NOC_SOUTH_DCD_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064040) +#define HWIO_GCC_NOC_SOUTH_DCD_XO_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064040) +#define HWIO_GCC_NOC_SOUTH_DCD_XO_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064040) +#define HWIO_GCC_NOC_SOUTH_DCD_XO_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_NOC_SOUTH_DCD_XO_CBCR_ATTR 0x3 +#define HWIO_GCC_NOC_SOUTH_DCD_XO_CBCR_IN \ + in_dword_masked(HWIO_GCC_NOC_SOUTH_DCD_XO_CBCR_ADDR, HWIO_GCC_NOC_SOUTH_DCD_XO_CBCR_RMSK) +#define HWIO_GCC_NOC_SOUTH_DCD_XO_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_NOC_SOUTH_DCD_XO_CBCR_ADDR, m) +#define HWIO_GCC_NOC_SOUTH_DCD_XO_CBCR_OUT(v) \ + out_dword(HWIO_GCC_NOC_SOUTH_DCD_XO_CBCR_ADDR,v) +#define HWIO_GCC_NOC_SOUTH_DCD_XO_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_NOC_SOUTH_DCD_XO_CBCR_ADDR,m,v,HWIO_GCC_NOC_SOUTH_DCD_XO_CBCR_IN) +#define HWIO_GCC_NOC_SOUTH_DCD_XO_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_NOC_SOUTH_DCD_XO_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_NOC_SOUTH_DCD_XO_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_NOC_SOUTH_DCD_XO_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_NOC_SOUTH_DCD_XO_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_NOC_SOUTH_DCD_XO_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_NOC_SOUTH_DCD_XO_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_NOC_SOUTH_DCD_XO_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_NOC_SOUTH_DCD_XO_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_NOC_SOUTH_DCD_XO_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_NOC_SOUTH_DCD_XO_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_NOC_SOUTH_DCD_XO_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_NOC_SOUTH_DCD_XO_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_NOC_SOUTH_DCD_XO_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_NOC_SOUTH_DCD_XO_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_NOC_SOUTH_DCD_XO_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_NOC_CENTER_DCD_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064044) +#define HWIO_GCC_NOC_CENTER_DCD_XO_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064044) +#define HWIO_GCC_NOC_CENTER_DCD_XO_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064044) +#define HWIO_GCC_NOC_CENTER_DCD_XO_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_NOC_CENTER_DCD_XO_CBCR_ATTR 0x3 +#define HWIO_GCC_NOC_CENTER_DCD_XO_CBCR_IN \ + in_dword_masked(HWIO_GCC_NOC_CENTER_DCD_XO_CBCR_ADDR, HWIO_GCC_NOC_CENTER_DCD_XO_CBCR_RMSK) +#define HWIO_GCC_NOC_CENTER_DCD_XO_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_NOC_CENTER_DCD_XO_CBCR_ADDR, m) +#define HWIO_GCC_NOC_CENTER_DCD_XO_CBCR_OUT(v) \ + out_dword(HWIO_GCC_NOC_CENTER_DCD_XO_CBCR_ADDR,v) +#define HWIO_GCC_NOC_CENTER_DCD_XO_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_NOC_CENTER_DCD_XO_CBCR_ADDR,m,v,HWIO_GCC_NOC_CENTER_DCD_XO_CBCR_IN) +#define HWIO_GCC_NOC_CENTER_DCD_XO_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_NOC_CENTER_DCD_XO_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_NOC_CENTER_DCD_XO_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_NOC_CENTER_DCD_XO_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_NOC_CENTER_DCD_XO_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_NOC_CENTER_DCD_XO_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_NOC_CENTER_DCD_XO_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_NOC_CENTER_DCD_XO_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_NOC_CENTER_DCD_XO_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_NOC_CENTER_DCD_XO_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_NOC_CENTER_DCD_XO_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_NOC_CENTER_DCD_XO_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_NOC_CENTER_DCD_XO_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_NOC_CENTER_DCD_XO_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_NOC_CENTER_DCD_XO_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_NOC_CENTER_DCD_XO_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CFG_NOC_AH2PHY_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064048) +#define HWIO_GCC_CFG_NOC_AH2PHY_XO_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064048) +#define HWIO_GCC_CFG_NOC_AH2PHY_XO_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064048) +#define HWIO_GCC_CFG_NOC_AH2PHY_XO_CBCR_RMSK 0x81c0000f +#define HWIO_GCC_CFG_NOC_AH2PHY_XO_CBCR_ATTR 0x3 +#define HWIO_GCC_CFG_NOC_AH2PHY_XO_CBCR_IN \ + in_dword_masked(HWIO_GCC_CFG_NOC_AH2PHY_XO_CBCR_ADDR, HWIO_GCC_CFG_NOC_AH2PHY_XO_CBCR_RMSK) +#define HWIO_GCC_CFG_NOC_AH2PHY_XO_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_CFG_NOC_AH2PHY_XO_CBCR_ADDR, m) +#define HWIO_GCC_CFG_NOC_AH2PHY_XO_CBCR_OUT(v) \ + out_dword(HWIO_GCC_CFG_NOC_AH2PHY_XO_CBCR_ADDR,v) +#define HWIO_GCC_CFG_NOC_AH2PHY_XO_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CFG_NOC_AH2PHY_XO_CBCR_ADDR,m,v,HWIO_GCC_CFG_NOC_AH2PHY_XO_CBCR_IN) +#define HWIO_GCC_CFG_NOC_AH2PHY_XO_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_CFG_NOC_AH2PHY_XO_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_CFG_NOC_AH2PHY_XO_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_CFG_NOC_AH2PHY_XO_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_CFG_NOC_AH2PHY_XO_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_CFG_NOC_AH2PHY_XO_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_CFG_NOC_AH2PHY_XO_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_CFG_NOC_AH2PHY_XO_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_CFG_NOC_AH2PHY_XO_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_CFG_NOC_AH2PHY_XO_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_CFG_NOC_AH2PHY_XO_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_CFG_NOC_AH2PHY_XO_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_CFG_NOC_AH2PHY_XO_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_CFG_NOC_AH2PHY_XO_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_CFG_NOC_AH2PHY_XO_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_CFG_NOC_AH2PHY_XO_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_CFG_NOC_AH2PHY_XO_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_CFG_NOC_AH2PHY_XO_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_CFG_NOC_AH2PHY_XO_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_CFG_NOC_AH2PHY_XO_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_CFG_NOC_AH2PHY_XO_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CFG_NOC_AH2PHY_XO_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_NOC_LPASS_DCD_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00035148) +#define HWIO_GCC_NOC_LPASS_DCD_XO_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00035148) +#define HWIO_GCC_NOC_LPASS_DCD_XO_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00035148) +#define HWIO_GCC_NOC_LPASS_DCD_XO_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_NOC_LPASS_DCD_XO_CBCR_ATTR 0x3 +#define HWIO_GCC_NOC_LPASS_DCD_XO_CBCR_IN \ + in_dword_masked(HWIO_GCC_NOC_LPASS_DCD_XO_CBCR_ADDR, HWIO_GCC_NOC_LPASS_DCD_XO_CBCR_RMSK) +#define HWIO_GCC_NOC_LPASS_DCD_XO_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_NOC_LPASS_DCD_XO_CBCR_ADDR, m) +#define HWIO_GCC_NOC_LPASS_DCD_XO_CBCR_OUT(v) \ + out_dword(HWIO_GCC_NOC_LPASS_DCD_XO_CBCR_ADDR,v) +#define HWIO_GCC_NOC_LPASS_DCD_XO_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_NOC_LPASS_DCD_XO_CBCR_ADDR,m,v,HWIO_GCC_NOC_LPASS_DCD_XO_CBCR_IN) +#define HWIO_GCC_NOC_LPASS_DCD_XO_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_NOC_LPASS_DCD_XO_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_NOC_LPASS_DCD_XO_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_NOC_LPASS_DCD_XO_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_NOC_LPASS_DCD_XO_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_NOC_LPASS_DCD_XO_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_NOC_LPASS_DCD_XO_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_NOC_LPASS_DCD_XO_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_NOC_LPASS_DCD_XO_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_NOC_LPASS_DCD_XO_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_NOC_LPASS_DCD_XO_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_NOC_LPASS_DCD_XO_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_NOC_LPASS_DCD_XO_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_NOC_LPASS_DCD_XO_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_NOC_LPASS_DCD_XO_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_NOC_LPASS_DCD_XO_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_NOC_MMNOC_CNOC_DCD_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006404c) +#define HWIO_GCC_NOC_MMNOC_CNOC_DCD_XO_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006404c) +#define HWIO_GCC_NOC_MMNOC_CNOC_DCD_XO_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006404c) +#define HWIO_GCC_NOC_MMNOC_CNOC_DCD_XO_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_NOC_MMNOC_CNOC_DCD_XO_CBCR_ATTR 0x3 +#define HWIO_GCC_NOC_MMNOC_CNOC_DCD_XO_CBCR_IN \ + in_dword_masked(HWIO_GCC_NOC_MMNOC_CNOC_DCD_XO_CBCR_ADDR, HWIO_GCC_NOC_MMNOC_CNOC_DCD_XO_CBCR_RMSK) +#define HWIO_GCC_NOC_MMNOC_CNOC_DCD_XO_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_NOC_MMNOC_CNOC_DCD_XO_CBCR_ADDR, m) +#define HWIO_GCC_NOC_MMNOC_CNOC_DCD_XO_CBCR_OUT(v) \ + out_dword(HWIO_GCC_NOC_MMNOC_CNOC_DCD_XO_CBCR_ADDR,v) +#define HWIO_GCC_NOC_MMNOC_CNOC_DCD_XO_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_NOC_MMNOC_CNOC_DCD_XO_CBCR_ADDR,m,v,HWIO_GCC_NOC_MMNOC_CNOC_DCD_XO_CBCR_IN) +#define HWIO_GCC_NOC_MMNOC_CNOC_DCD_XO_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_NOC_MMNOC_CNOC_DCD_XO_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_NOC_MMNOC_CNOC_DCD_XO_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_NOC_MMNOC_CNOC_DCD_XO_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_NOC_MMNOC_CNOC_DCD_XO_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_NOC_MMNOC_CNOC_DCD_XO_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_NOC_MMNOC_CNOC_DCD_XO_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_NOC_MMNOC_CNOC_DCD_XO_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_NOC_MMNOC_CNOC_DCD_XO_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_NOC_MMNOC_CNOC_DCD_XO_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_NOC_MMNOC_CNOC_DCD_XO_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_NOC_MMNOC_CNOC_DCD_XO_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_NOC_MMNOC_CNOC_DCD_XO_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_NOC_MMNOC_CNOC_DCD_XO_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_NOC_MMNOC_CNOC_DCD_XO_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_NOC_MMNOC_CNOC_DCD_XO_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CNOC_PERIPH_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064050) +#define HWIO_GCC_CNOC_PERIPH_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064050) +#define HWIO_GCC_CNOC_PERIPH_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064050) +#define HWIO_GCC_CNOC_PERIPH_CBCR_RMSK 0x81d00005 +#define HWIO_GCC_CNOC_PERIPH_CBCR_ATTR 0x3 +#define HWIO_GCC_CNOC_PERIPH_CBCR_IN \ + in_dword_masked(HWIO_GCC_CNOC_PERIPH_CBCR_ADDR, HWIO_GCC_CNOC_PERIPH_CBCR_RMSK) +#define HWIO_GCC_CNOC_PERIPH_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_CNOC_PERIPH_CBCR_ADDR, m) +#define HWIO_GCC_CNOC_PERIPH_CBCR_OUT(v) \ + out_dword(HWIO_GCC_CNOC_PERIPH_CBCR_ADDR,v) +#define HWIO_GCC_CNOC_PERIPH_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CNOC_PERIPH_CBCR_ADDR,m,v,HWIO_GCC_CNOC_PERIPH_CBCR_IN) +#define HWIO_GCC_CNOC_PERIPH_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_CNOC_PERIPH_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_CNOC_PERIPH_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_CNOC_PERIPH_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_CNOC_PERIPH_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_CNOC_PERIPH_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_CNOC_PERIPH_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_CNOC_PERIPH_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_CNOC_PERIPH_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_CNOC_PERIPH_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_CNOC_PERIPH_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_CNOC_PERIPH_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_CNOC_PERIPH_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_CNOC_PERIPH_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_CNOC_PERIPH_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_CNOC_PERIPH_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_CNOC_PERIPH_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CNOC_PERIPH_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CONFIG_NOC_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064054) +#define HWIO_GCC_CONFIG_NOC_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064054) +#define HWIO_GCC_CONFIG_NOC_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064054) +#define HWIO_GCC_CONFIG_NOC_AT_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_CONFIG_NOC_AT_CBCR_ATTR 0x3 +#define HWIO_GCC_CONFIG_NOC_AT_CBCR_IN \ + in_dword_masked(HWIO_GCC_CONFIG_NOC_AT_CBCR_ADDR, HWIO_GCC_CONFIG_NOC_AT_CBCR_RMSK) +#define HWIO_GCC_CONFIG_NOC_AT_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_CONFIG_NOC_AT_CBCR_ADDR, m) +#define HWIO_GCC_CONFIG_NOC_AT_CBCR_OUT(v) \ + out_dword(HWIO_GCC_CONFIG_NOC_AT_CBCR_ADDR,v) +#define HWIO_GCC_CONFIG_NOC_AT_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CONFIG_NOC_AT_CBCR_ADDR,m,v,HWIO_GCC_CONFIG_NOC_AT_CBCR_IN) +#define HWIO_GCC_CONFIG_NOC_AT_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_CONFIG_NOC_AT_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_CONFIG_NOC_AT_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_CONFIG_NOC_AT_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_CONFIG_NOC_AT_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_CONFIG_NOC_AT_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_CONFIG_NOC_AT_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_CONFIG_NOC_AT_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_CONFIG_NOC_AT_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_CONFIG_NOC_AT_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_CONFIG_NOC_AT_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_CONFIG_NOC_AT_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_CONFIG_NOC_AT_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_CONFIG_NOC_AT_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_CONFIG_NOC_AT_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_CONFIG_NOC_AT_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_CONFIG_NOC_AT_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_CONFIG_NOC_AT_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_CONFIG_NOC_AT_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_CONFIG_NOC_AT_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_CONFIG_NOC_AT_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_CONFIG_NOC_AT_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_CONFIG_NOC_AT_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CONFIG_NOC_AT_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006406c) +#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006406c) +#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006406c) +#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_RMSK 0x1fffff +#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CMD_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CMD_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CMD_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CMD_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CMD_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CMD_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_RCG_SW_CTRL_BMSK 0x1f8000 +#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_RCG_SW_CTRL_SHFT 0xf +#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_SW_PERF_STATE_BMSK 0x7800 +#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_SW_PERF_STATE_SHFT 0xb +#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_SW_OVERRIDE_BMSK 0x400 +#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_SW_OVERRIDE_SHFT 0xa +#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK 0x200 +#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT 0x9 +#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_DFS_FSM_STATE_BMSK 0x1c0 +#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_DFS_FSM_STATE_SHFT 0x6 +#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_HW_CLK_CONTROL_BMSK 0x20 +#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_HW_CLK_CONTROL_SHFT 0x5 +#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_CURR_PERF_STATE_BMSK 0x1e +#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_CURR_PERF_STATE_SHFT 0x1 +#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_DFS_EN_BMSK 0x1 +#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_DFS_EN_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_DFS_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_DFS_EN_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064074) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064074) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064074) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF0_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF0_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF0_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF0_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064078) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064078) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064078) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF1_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF1_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF1_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF1_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006407c) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006407c) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006407c) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF2_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF2_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF2_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF2_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064080) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064080) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064080) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF3_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF3_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF3_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF3_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064084) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064084) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064084) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF4_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF4_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF4_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF4_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064088) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064088) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064088) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF5_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF5_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF5_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF5_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006408c) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006408c) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006408c) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF6_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF6_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF6_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF6_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064090) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064090) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064090) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF7_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF7_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF7_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF7_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF8_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064094) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF8_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064094) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF8_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064094) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF8_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF8_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF8_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF8_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF8_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF8_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF8_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF8_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF8_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF8_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF8_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF8_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF8_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF8_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF8_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF8_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF8_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF8_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF8_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF8_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF8_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF8_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF8_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF8_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF8_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF8_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF8_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF8_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF8_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF8_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF8_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF8_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF8_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF8_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF8_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF8_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF8_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF8_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF8_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF8_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF8_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF8_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF8_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF8_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF8_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF8_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF8_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF8_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF8_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF8_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF8_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF8_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF8_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF8_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF8_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF9_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064098) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF9_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064098) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF9_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064098) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF9_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF9_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF9_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF9_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF9_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF9_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF9_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF9_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF9_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF9_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF9_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF9_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF9_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF9_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF9_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF9_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF9_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF9_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF9_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF9_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF9_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF9_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF9_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF9_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF9_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF9_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF9_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF9_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF9_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF9_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF9_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF9_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF9_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF9_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF9_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF9_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF9_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF9_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF9_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF9_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF9_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF9_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF9_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF9_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF9_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF9_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF9_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF9_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF9_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF9_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF9_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF9_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF9_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF9_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF9_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF10_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006409c) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF10_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006409c) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF10_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006409c) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF10_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF10_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF10_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF10_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF10_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF10_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF10_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF10_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF10_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF10_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF10_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF10_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF10_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF10_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF10_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF10_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF10_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF10_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF10_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF10_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF10_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF10_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF10_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF10_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF10_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF10_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF10_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF10_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF10_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF10_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF10_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF10_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF10_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF10_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF10_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF10_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF10_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF10_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF10_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF10_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF10_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF10_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF10_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF10_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF10_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF10_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF10_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF10_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF10_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF10_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF10_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF10_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF10_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF10_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF10_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF11_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000640a0) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF11_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000640a0) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF11_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000640a0) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF11_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF11_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF11_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF11_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF11_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF11_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF11_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF11_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF11_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF11_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF11_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF11_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF11_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF11_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF11_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF11_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF11_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF11_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF11_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF11_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF11_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF11_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF11_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF11_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF11_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF11_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF11_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF11_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF11_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF11_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF11_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF11_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF11_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF11_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF11_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF11_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF11_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF11_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF11_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF11_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF11_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF11_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF11_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF11_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF11_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF11_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF11_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF11_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF11_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF11_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF11_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF11_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF11_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF11_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF11_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF12_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000640a4) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF12_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000640a4) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF12_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000640a4) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF12_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF12_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF12_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF12_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF12_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF12_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF12_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF12_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF12_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF12_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF12_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF12_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF12_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF12_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF12_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF12_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF12_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF12_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF12_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF12_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF12_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF12_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF12_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF12_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF12_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF12_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF12_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF12_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF12_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF12_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF12_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF12_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF12_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF12_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF12_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF12_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF12_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF12_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF12_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF12_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF12_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF12_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF12_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF12_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF12_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF12_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF12_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF12_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF12_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF12_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF12_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF12_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF12_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF12_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF12_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF13_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000640a8) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF13_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000640a8) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF13_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000640a8) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF13_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF13_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF13_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF13_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF13_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF13_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF13_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF13_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF13_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF13_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF13_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF13_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF13_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF13_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF13_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF13_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF13_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF13_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF13_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF13_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF13_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF13_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF13_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF13_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF13_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF13_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF13_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF13_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF13_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF13_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF13_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF13_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF13_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF13_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF13_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF13_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF13_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF13_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF13_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF13_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF13_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF13_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF13_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF13_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF13_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF13_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF13_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF13_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF13_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF13_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF13_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF13_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF13_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF13_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF13_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF14_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000640ac) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF14_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000640ac) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF14_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000640ac) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF14_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF14_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF14_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF14_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF14_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF14_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF14_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF14_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF14_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF14_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF14_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF14_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF14_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF14_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF14_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF14_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF14_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF14_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF14_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF14_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF14_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF14_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF14_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF14_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF14_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF14_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF14_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF14_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF14_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF14_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF14_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF14_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF14_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF14_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF14_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF14_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF14_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF14_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF14_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF14_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF14_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF14_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF14_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF14_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF14_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF14_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF14_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF14_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF14_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF14_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF14_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF14_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF14_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF14_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF14_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF15_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000640b0) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF15_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000640b0) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF15_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000640b0) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF15_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF15_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF15_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF15_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF15_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF15_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF15_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF15_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF15_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF15_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF15_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF15_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF15_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF15_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF15_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF15_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF15_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF15_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF15_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF15_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF15_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF15_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF15_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF15_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF15_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF15_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF15_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF15_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF15_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF15_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF15_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF15_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF15_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF15_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF15_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF15_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF15_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF15_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF15_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF15_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF15_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF15_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF15_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF15_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF15_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF15_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF15_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF15_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF15_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF15_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF15_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF15_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF15_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF15_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF15_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_CNOC_NORTH_QX_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064058) +#define HWIO_GCC_CNOC_NORTH_QX_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064058) +#define HWIO_GCC_CNOC_NORTH_QX_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064058) +#define HWIO_GCC_CNOC_NORTH_QX_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_CNOC_NORTH_QX_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_CNOC_NORTH_QX_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_CNOC_NORTH_QX_CMD_RCGR_ADDR, HWIO_GCC_CNOC_NORTH_QX_CMD_RCGR_RMSK) +#define HWIO_GCC_CNOC_NORTH_QX_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_CNOC_NORTH_QX_CMD_RCGR_ADDR, m) +#define HWIO_GCC_CNOC_NORTH_QX_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_CNOC_NORTH_QX_CMD_RCGR_ADDR,v) +#define HWIO_GCC_CNOC_NORTH_QX_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CNOC_NORTH_QX_CMD_RCGR_ADDR,m,v,HWIO_GCC_CNOC_NORTH_QX_CMD_RCGR_IN) +#define HWIO_GCC_CNOC_NORTH_QX_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_CNOC_NORTH_QX_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_CNOC_NORTH_QX_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_CNOC_NORTH_QX_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_CNOC_NORTH_QX_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_CNOC_NORTH_QX_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_CNOC_NORTH_QX_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_CNOC_NORTH_QX_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_CNOC_NORTH_QX_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_CNOC_NORTH_QX_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_CNOC_NORTH_QX_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CNOC_NORTH_QX_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006405c) +#define HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006405c) +#define HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006405c) +#define HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_ADDR, HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_RMSK) +#define HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_ADDR, m) +#define HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_ADDR,v) +#define HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_ADDR,m,v,HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_IN) +#define HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_CNOC_NORTH_QX_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000641a0) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000641a0) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000641a0) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF0_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF0_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF0_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF0_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000641a4) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000641a4) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000641a4) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF1_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF1_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF1_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF1_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000641a8) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000641a8) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000641a8) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF2_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF2_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF2_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF2_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000641ac) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000641ac) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000641ac) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF3_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF3_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF3_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF3_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000641b0) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000641b0) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000641b0) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF4_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF4_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF4_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF4_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000641b4) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000641b4) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000641b4) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF5_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF5_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF5_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF5_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000641b8) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000641b8) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000641b8) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF6_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF6_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF6_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF6_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000641bc) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000641bc) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000641bc) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF7_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF7_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF7_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF7_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF8_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000641c0) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF8_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000641c0) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF8_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000641c0) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF8_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF8_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF8_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF8_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF8_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF8_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF8_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF8_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF8_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF8_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF8_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF8_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF8_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF8_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF8_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF8_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF8_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF8_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF8_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF8_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF8_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF8_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF8_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF8_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF8_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF8_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF8_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF8_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF8_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF8_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF8_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF8_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF8_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF8_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF8_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF8_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF8_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF8_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF8_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF8_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF8_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF8_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF8_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF8_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF8_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF8_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF8_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF8_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF8_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF8_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF8_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF8_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF8_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF8_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF8_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF9_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000641c4) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF9_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000641c4) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF9_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000641c4) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF9_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF9_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF9_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF9_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF9_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF9_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF9_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF9_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF9_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF9_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF9_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF9_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF9_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF9_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF9_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF9_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF9_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF9_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF9_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF9_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF9_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF9_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF9_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF9_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF9_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF9_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF9_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF9_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF9_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF9_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF9_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF9_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF9_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF9_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF9_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF9_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF9_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF9_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF9_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF9_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF9_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF9_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF9_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF9_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF9_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF9_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF9_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF9_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF9_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF9_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF9_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF9_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF9_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF9_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF9_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF10_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000641c8) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF10_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000641c8) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF10_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000641c8) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF10_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF10_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF10_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF10_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF10_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF10_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF10_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF10_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF10_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF10_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF10_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF10_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF10_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF10_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF10_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF10_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF10_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF10_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF10_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF10_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF10_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF10_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF10_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF10_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF10_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF10_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF10_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF10_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF10_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF10_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF10_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF10_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF10_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF10_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF10_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF10_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF10_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF10_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF10_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF10_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF10_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF10_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF10_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF10_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF10_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF10_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF10_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF10_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF10_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF10_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF10_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF10_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF10_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF10_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF10_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF11_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000641cc) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF11_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000641cc) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF11_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000641cc) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF11_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF11_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF11_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF11_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF11_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF11_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF11_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF11_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF11_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF11_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF11_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF11_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF11_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF11_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF11_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF11_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF11_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF11_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF11_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF11_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF11_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF11_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF11_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF11_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF11_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF11_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF11_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF11_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF11_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF11_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF11_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF11_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF11_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF11_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF11_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF11_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF11_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF11_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF11_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF11_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF11_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF11_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF11_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF11_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF11_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF11_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF11_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF11_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF11_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF11_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF11_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF11_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF11_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF11_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF11_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF12_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000641d0) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF12_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000641d0) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF12_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000641d0) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF12_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF12_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF12_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF12_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF12_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF12_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF12_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF12_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF12_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF12_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF12_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF12_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF12_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF12_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF12_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF12_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF12_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF12_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF12_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF12_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF12_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF12_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF12_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF12_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF12_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF12_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF12_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF12_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF12_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF12_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF12_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF12_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF12_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF12_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF12_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF12_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF12_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF12_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF12_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF12_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF12_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF12_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF12_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF12_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF12_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF12_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF12_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF12_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF12_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF12_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF12_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF12_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF12_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF12_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF12_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF13_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000641d4) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF13_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000641d4) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF13_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000641d4) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF13_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF13_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF13_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF13_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF13_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF13_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF13_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF13_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF13_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF13_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF13_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF13_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF13_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF13_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF13_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF13_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF13_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF13_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF13_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF13_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF13_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF13_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF13_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF13_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF13_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF13_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF13_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF13_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF13_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF13_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF13_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF13_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF13_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF13_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF13_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF13_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF13_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF13_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF13_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF13_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF13_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF13_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF13_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF13_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF13_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF13_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF13_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF13_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF13_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF13_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF13_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF13_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF13_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF13_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF13_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF14_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000641d8) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF14_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000641d8) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF14_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000641d8) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF14_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF14_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF14_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF14_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF14_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF14_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF14_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF14_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF14_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF14_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF14_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF14_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF14_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF14_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF14_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF14_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF14_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF14_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF14_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF14_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF14_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF14_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF14_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF14_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF14_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF14_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF14_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF14_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF14_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF14_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF14_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF14_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF14_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF14_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF14_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF14_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF14_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF14_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF14_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF14_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF14_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF14_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF14_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF14_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF14_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF14_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF14_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF14_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF14_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF14_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF14_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF14_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF14_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF14_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF14_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF15_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000641dc) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF15_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000641dc) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF15_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000641dc) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF15_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF15_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF15_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF15_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF15_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF15_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF15_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF15_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF15_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF15_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF15_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF15_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF15_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF15_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF15_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF15_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF15_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF15_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF15_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF15_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF15_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF15_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF15_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF15_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF15_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF15_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF15_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF15_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF15_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF15_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF15_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF15_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF15_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF15_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF15_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF15_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF15_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF15_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF15_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF15_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF15_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF15_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF15_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF15_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF15_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF15_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF15_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF15_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF15_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF15_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF15_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF15_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF15_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF15_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF15_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_CNOC_CENTER_QX_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064184) +#define HWIO_GCC_CNOC_CENTER_QX_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064184) +#define HWIO_GCC_CNOC_CENTER_QX_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064184) +#define HWIO_GCC_CNOC_CENTER_QX_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_CNOC_CENTER_QX_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_CNOC_CENTER_QX_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_CNOC_CENTER_QX_CMD_RCGR_ADDR, HWIO_GCC_CNOC_CENTER_QX_CMD_RCGR_RMSK) +#define HWIO_GCC_CNOC_CENTER_QX_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_CNOC_CENTER_QX_CMD_RCGR_ADDR, m) +#define HWIO_GCC_CNOC_CENTER_QX_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_CNOC_CENTER_QX_CMD_RCGR_ADDR,v) +#define HWIO_GCC_CNOC_CENTER_QX_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CNOC_CENTER_QX_CMD_RCGR_ADDR,m,v,HWIO_GCC_CNOC_CENTER_QX_CMD_RCGR_IN) +#define HWIO_GCC_CNOC_CENTER_QX_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_CNOC_CENTER_QX_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_CNOC_CENTER_QX_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_CNOC_CENTER_QX_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_CNOC_CENTER_QX_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_CNOC_CENTER_QX_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_CNOC_CENTER_QX_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_CNOC_CENTER_QX_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_CNOC_CENTER_QX_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_CNOC_CENTER_QX_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_CNOC_CENTER_QX_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CNOC_CENTER_QX_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064188) +#define HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064188) +#define HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064188) +#define HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_ADDR, HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_RMSK) +#define HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_ADDR, m) +#define HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_ADDR,v) +#define HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_ADDR,m,v,HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_IN) +#define HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_CNOC_CENTER_QX_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000642cc) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000642cc) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000642cc) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000642d0) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000642d0) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000642d0) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000642d4) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000642d4) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000642d4) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000642d8) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000642d8) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000642d8) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000642dc) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000642dc) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000642dc) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000642e0) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000642e0) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000642e0) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000642e4) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000642e4) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000642e4) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000642e8) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000642e8) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000642e8) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000642ec) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000642ec) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000642ec) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000642f0) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000642f0) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000642f0) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000642f4) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000642f4) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000642f4) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000642f8) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000642f8) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000642f8) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000642fc) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000642fc) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000642fc) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064300) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064300) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064300) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064304) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064304) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064304) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064308) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064308) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064308) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_CONFIG_NOC_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000642b0) +#define HWIO_GCC_CONFIG_NOC_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000642b0) +#define HWIO_GCC_CONFIG_NOC_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000642b0) +#define HWIO_GCC_CONFIG_NOC_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_CONFIG_NOC_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_CONFIG_NOC_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_CONFIG_NOC_CMD_RCGR_ADDR, HWIO_GCC_CONFIG_NOC_CMD_RCGR_RMSK) +#define HWIO_GCC_CONFIG_NOC_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_CONFIG_NOC_CMD_RCGR_ADDR, m) +#define HWIO_GCC_CONFIG_NOC_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_CONFIG_NOC_CMD_RCGR_ADDR,v) +#define HWIO_GCC_CONFIG_NOC_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CONFIG_NOC_CMD_RCGR_ADDR,m,v,HWIO_GCC_CONFIG_NOC_CMD_RCGR_IN) +#define HWIO_GCC_CONFIG_NOC_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_CONFIG_NOC_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_CONFIG_NOC_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_CONFIG_NOC_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_CONFIG_NOC_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_CONFIG_NOC_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_CONFIG_NOC_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_CONFIG_NOC_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_CONFIG_NOC_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_CONFIG_NOC_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_CONFIG_NOC_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CONFIG_NOC_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000642b4) +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000642b4) +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000642b4) +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_CONFIG_NOC_CFG_RCGR_ADDR, HWIO_GCC_CONFIG_NOC_CFG_RCGR_RMSK) +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_CONFIG_NOC_CFG_RCGR_ADDR, m) +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_CONFIG_NOC_CFG_RCGR_ADDR,v) +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CONFIG_NOC_CFG_RCGR_ADDR,m,v,HWIO_GCC_CONFIG_NOC_CFG_RCGR_IN) +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000643f8) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000643f8) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000643f8) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000643fc) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000643fc) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000643fc) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064400) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064400) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064400) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064404) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064404) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064404) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064408) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064408) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064408) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006440c) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006440c) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006440c) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064410) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064410) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064410) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064414) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064414) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064414) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064418) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064418) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064418) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006441c) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006441c) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006441c) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064420) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064420) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064420) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064424) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064424) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064424) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064428) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064428) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064428) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006442c) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006442c) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006442c) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064430) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064430) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064430) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064434) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064434) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064434) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_CNOC_PERIPH_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000643dc) +#define HWIO_GCC_CNOC_PERIPH_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000643dc) +#define HWIO_GCC_CNOC_PERIPH_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000643dc) +#define HWIO_GCC_CNOC_PERIPH_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_CNOC_PERIPH_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_CNOC_PERIPH_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_CNOC_PERIPH_CMD_RCGR_ADDR, HWIO_GCC_CNOC_PERIPH_CMD_RCGR_RMSK) +#define HWIO_GCC_CNOC_PERIPH_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_CNOC_PERIPH_CMD_RCGR_ADDR, m) +#define HWIO_GCC_CNOC_PERIPH_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_CNOC_PERIPH_CMD_RCGR_ADDR,v) +#define HWIO_GCC_CNOC_PERIPH_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CNOC_PERIPH_CMD_RCGR_ADDR,m,v,HWIO_GCC_CNOC_PERIPH_CMD_RCGR_IN) +#define HWIO_GCC_CNOC_PERIPH_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_CNOC_PERIPH_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_CNOC_PERIPH_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_CNOC_PERIPH_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_CNOC_PERIPH_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_CNOC_PERIPH_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_CNOC_PERIPH_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_CNOC_PERIPH_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_CNOC_PERIPH_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_CNOC_PERIPH_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_CNOC_PERIPH_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CNOC_PERIPH_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000643e0) +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000643e0) +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000643e0) +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_CNOC_PERIPH_CFG_RCGR_ADDR, HWIO_GCC_CNOC_PERIPH_CFG_RCGR_RMSK) +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_CNOC_PERIPH_CFG_RCGR_ADDR, m) +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_CNOC_PERIPH_CFG_RCGR_ADDR,v) +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CNOC_PERIPH_CFG_RCGR_ADDR,m,v,HWIO_GCC_CNOC_PERIPH_CFG_RCGR_IN) +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064524) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064524) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064524) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF0_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF0_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF0_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF0_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064528) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064528) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064528) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF1_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF1_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF1_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF1_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006452c) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006452c) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006452c) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF2_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF2_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF2_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF2_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064530) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064530) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064530) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF3_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF3_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF3_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF3_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064534) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064534) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064534) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF4_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF4_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF4_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF4_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064538) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064538) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064538) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF5_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF5_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF5_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF5_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006453c) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006453c) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006453c) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF6_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF6_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF6_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF6_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064540) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064540) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064540) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF7_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF7_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF7_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF7_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF8_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064544) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF8_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064544) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF8_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064544) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF8_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF8_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF8_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF8_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF8_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF8_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF8_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF8_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF8_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF8_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF8_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF8_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF8_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF8_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF8_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF8_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF8_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF8_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF8_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF8_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF8_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF8_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF8_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF8_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF8_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF8_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF8_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF8_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF8_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF8_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF8_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF8_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF8_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF8_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF8_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF8_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF8_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF8_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF8_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF8_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF8_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF8_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF8_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF8_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF8_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF8_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF8_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF8_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF8_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF8_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF8_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF8_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF8_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF8_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF8_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF9_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064548) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF9_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064548) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF9_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064548) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF9_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF9_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF9_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF9_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF9_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF9_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF9_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF9_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF9_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF9_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF9_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF9_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF9_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF9_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF9_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF9_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF9_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF9_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF9_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF9_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF9_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF9_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF9_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF9_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF9_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF9_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF9_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF9_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF9_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF9_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF9_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF9_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF9_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF9_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF9_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF9_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF9_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF9_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF9_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF9_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF9_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF9_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF9_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF9_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF9_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF9_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF9_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF9_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF9_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF9_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF9_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF9_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF9_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF9_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF9_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF10_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006454c) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF10_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006454c) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF10_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006454c) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF10_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF10_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF10_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF10_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF10_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF10_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF10_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF10_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF10_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF10_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF10_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF10_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF10_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF10_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF10_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF10_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF10_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF10_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF10_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF10_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF10_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF10_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF10_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF10_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF10_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF10_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF10_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF10_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF10_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF10_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF10_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF10_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF10_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF10_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF10_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF10_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF10_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF10_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF10_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF10_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF10_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF10_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF10_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF10_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF10_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF10_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF10_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF10_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF10_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF10_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF10_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF10_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF10_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF10_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF10_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF11_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064550) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF11_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064550) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF11_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064550) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF11_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF11_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF11_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF11_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF11_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF11_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF11_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF11_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF11_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF11_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF11_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF11_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF11_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF11_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF11_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF11_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF11_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF11_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF11_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF11_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF11_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF11_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF11_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF11_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF11_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF11_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF11_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF11_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF11_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF11_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF11_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF11_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF11_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF11_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF11_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF11_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF11_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF11_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF11_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF11_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF11_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF11_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF11_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF11_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF11_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF11_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF11_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF11_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF11_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF11_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF11_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF11_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF11_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF11_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF11_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF12_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064554) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF12_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064554) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF12_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064554) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF12_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF12_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF12_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF12_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF12_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF12_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF12_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF12_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF12_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF12_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF12_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF12_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF12_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF12_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF12_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF12_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF12_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF12_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF12_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF12_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF12_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF12_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF12_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF12_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF12_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF12_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF12_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF12_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF12_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF12_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF12_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF12_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF12_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF12_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF12_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF12_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF12_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF12_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF12_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF12_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF12_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF12_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF12_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF12_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF12_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF12_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF12_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF12_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF12_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF12_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF12_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF12_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF12_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF12_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF12_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF13_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064558) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF13_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064558) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF13_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064558) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF13_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF13_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF13_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF13_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF13_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF13_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF13_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF13_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF13_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF13_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF13_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF13_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF13_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF13_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF13_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF13_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF13_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF13_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF13_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF13_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF13_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF13_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF13_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF13_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF13_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF13_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF13_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF13_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF13_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF13_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF13_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF13_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF13_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF13_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF13_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF13_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF13_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF13_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF13_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF13_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF13_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF13_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF13_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF13_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF13_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF13_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF13_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF13_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF13_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF13_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF13_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF13_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF13_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF13_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF13_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF14_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006455c) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF14_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006455c) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF14_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006455c) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF14_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF14_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF14_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF14_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF14_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF14_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF14_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF14_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF14_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF14_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF14_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF14_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF14_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF14_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF14_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF14_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF14_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF14_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF14_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF14_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF14_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF14_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF14_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF14_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF14_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF14_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF14_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF14_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF14_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF14_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF14_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF14_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF14_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF14_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF14_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF14_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF14_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF14_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF14_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF14_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF14_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF14_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF14_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF14_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF14_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF14_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF14_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF14_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF14_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF14_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF14_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF14_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF14_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF14_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF14_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF15_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064560) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF15_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064560) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF15_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064560) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF15_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF15_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF15_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF15_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF15_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF15_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF15_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF15_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF15_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF15_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF15_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF15_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF15_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF15_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF15_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF15_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF15_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF15_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF15_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF15_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF15_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF15_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF15_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF15_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF15_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF15_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF15_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF15_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF15_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF15_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF15_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF15_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF15_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF15_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF15_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF15_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF15_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF15_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF15_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF15_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF15_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF15_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF15_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF15_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF15_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF15_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF15_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF15_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF15_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF15_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF15_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF15_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF15_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF15_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF15_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064508) +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064508) +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064508) +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_CONFIG_NOC_DDRSS_SF_CMD_RCGR_ADDR, HWIO_GCC_CONFIG_NOC_DDRSS_SF_CMD_RCGR_RMSK) +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_CONFIG_NOC_DDRSS_SF_CMD_RCGR_ADDR, m) +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_CONFIG_NOC_DDRSS_SF_CMD_RCGR_ADDR,v) +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CONFIG_NOC_DDRSS_SF_CMD_RCGR_ADDR,m,v,HWIO_GCC_CONFIG_NOC_DDRSS_SF_CMD_RCGR_IN) +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006450c) +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006450c) +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006450c) +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_ADDR, HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_RMSK) +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_ADDR, m) +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_ADDR,v) +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_ADDR,m,v,HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_IN) +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064650) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064650) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064650) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064654) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064654) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064654) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064658) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064658) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064658) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006465c) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006465c) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006465c) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064660) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064660) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064660) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064664) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064664) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064664) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064668) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064668) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064668) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006466c) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006466c) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006466c) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064670) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064670) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064670) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064674) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064674) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064674) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064678) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064678) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064678) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006467c) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006467c) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006467c) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064680) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064680) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064680) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064684) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064684) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064684) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064688) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064688) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064688) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006468c) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006468c) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006468c) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_ADDR, HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_RMSK) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_IN) +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_CFG_NOC_LPASS_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064634) +#define HWIO_GCC_CFG_NOC_LPASS_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064634) +#define HWIO_GCC_CFG_NOC_LPASS_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064634) +#define HWIO_GCC_CFG_NOC_LPASS_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_CFG_NOC_LPASS_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_CFG_NOC_LPASS_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_CFG_NOC_LPASS_CMD_RCGR_ADDR, HWIO_GCC_CFG_NOC_LPASS_CMD_RCGR_RMSK) +#define HWIO_GCC_CFG_NOC_LPASS_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_CFG_NOC_LPASS_CMD_RCGR_ADDR, m) +#define HWIO_GCC_CFG_NOC_LPASS_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_CFG_NOC_LPASS_CMD_RCGR_ADDR,v) +#define HWIO_GCC_CFG_NOC_LPASS_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CFG_NOC_LPASS_CMD_RCGR_ADDR,m,v,HWIO_GCC_CFG_NOC_LPASS_CMD_RCGR_IN) +#define HWIO_GCC_CFG_NOC_LPASS_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_CFG_NOC_LPASS_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_CFG_NOC_LPASS_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_CFG_NOC_LPASS_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_CFG_NOC_LPASS_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_CFG_NOC_LPASS_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_CFG_NOC_LPASS_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_CFG_NOC_LPASS_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_CFG_NOC_LPASS_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_CFG_NOC_LPASS_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_CFG_NOC_LPASS_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CFG_NOC_LPASS_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064638) +#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064638) +#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064638) +#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_ADDR, HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_RMSK) +#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_ADDR, m) +#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_ADDR,v) +#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_ADDR,m,v,HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_IN) +#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_CNOC_PERIPH_SOUTH_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064760) +#define HWIO_GCC_CNOC_PERIPH_SOUTH_DCD_CDIV_DCDR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064760) +#define HWIO_GCC_CNOC_PERIPH_SOUTH_DCD_CDIV_DCDR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064760) +#define HWIO_GCC_CNOC_PERIPH_SOUTH_DCD_CDIV_DCDR_RMSK 0x1 +#define HWIO_GCC_CNOC_PERIPH_SOUTH_DCD_CDIV_DCDR_ATTR 0x3 +#define HWIO_GCC_CNOC_PERIPH_SOUTH_DCD_CDIV_DCDR_IN \ + in_dword_masked(HWIO_GCC_CNOC_PERIPH_SOUTH_DCD_CDIV_DCDR_ADDR, HWIO_GCC_CNOC_PERIPH_SOUTH_DCD_CDIV_DCDR_RMSK) +#define HWIO_GCC_CNOC_PERIPH_SOUTH_DCD_CDIV_DCDR_INM(m) \ + in_dword_masked(HWIO_GCC_CNOC_PERIPH_SOUTH_DCD_CDIV_DCDR_ADDR, m) +#define HWIO_GCC_CNOC_PERIPH_SOUTH_DCD_CDIV_DCDR_OUT(v) \ + out_dword(HWIO_GCC_CNOC_PERIPH_SOUTH_DCD_CDIV_DCDR_ADDR,v) +#define HWIO_GCC_CNOC_PERIPH_SOUTH_DCD_CDIV_DCDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CNOC_PERIPH_SOUTH_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_CNOC_PERIPH_SOUTH_DCD_CDIV_DCDR_IN) +#define HWIO_GCC_CNOC_PERIPH_SOUTH_DCD_CDIV_DCDR_DCD_ENABLE_BMSK 0x1 +#define HWIO_GCC_CNOC_PERIPH_SOUTH_DCD_CDIV_DCDR_DCD_ENABLE_SHFT 0x0 +#define HWIO_GCC_CNOC_PERIPH_SOUTH_DCD_CDIV_DCDR_DCD_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CNOC_PERIPH_SOUTH_DCD_CDIV_DCDR_DCD_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CNOC_PERIPH_NORTH_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064764) +#define HWIO_GCC_CNOC_PERIPH_NORTH_DCD_CDIV_DCDR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064764) +#define HWIO_GCC_CNOC_PERIPH_NORTH_DCD_CDIV_DCDR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064764) +#define HWIO_GCC_CNOC_PERIPH_NORTH_DCD_CDIV_DCDR_RMSK 0x1 +#define HWIO_GCC_CNOC_PERIPH_NORTH_DCD_CDIV_DCDR_ATTR 0x3 +#define HWIO_GCC_CNOC_PERIPH_NORTH_DCD_CDIV_DCDR_IN \ + in_dword_masked(HWIO_GCC_CNOC_PERIPH_NORTH_DCD_CDIV_DCDR_ADDR, HWIO_GCC_CNOC_PERIPH_NORTH_DCD_CDIV_DCDR_RMSK) +#define HWIO_GCC_CNOC_PERIPH_NORTH_DCD_CDIV_DCDR_INM(m) \ + in_dword_masked(HWIO_GCC_CNOC_PERIPH_NORTH_DCD_CDIV_DCDR_ADDR, m) +#define HWIO_GCC_CNOC_PERIPH_NORTH_DCD_CDIV_DCDR_OUT(v) \ + out_dword(HWIO_GCC_CNOC_PERIPH_NORTH_DCD_CDIV_DCDR_ADDR,v) +#define HWIO_GCC_CNOC_PERIPH_NORTH_DCD_CDIV_DCDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CNOC_PERIPH_NORTH_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_CNOC_PERIPH_NORTH_DCD_CDIV_DCDR_IN) +#define HWIO_GCC_CNOC_PERIPH_NORTH_DCD_CDIV_DCDR_DCD_ENABLE_BMSK 0x1 +#define HWIO_GCC_CNOC_PERIPH_NORTH_DCD_CDIV_DCDR_DCD_ENABLE_SHFT 0x0 +#define HWIO_GCC_CNOC_PERIPH_NORTH_DCD_CDIV_DCDR_DCD_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CNOC_PERIPH_NORTH_DCD_CDIV_DCDR_DCD_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CNOC_PERIPH_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064768) +#define HWIO_GCC_CNOC_PERIPH_DCD_CDIV_DCDR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064768) +#define HWIO_GCC_CNOC_PERIPH_DCD_CDIV_DCDR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064768) +#define HWIO_GCC_CNOC_PERIPH_DCD_CDIV_DCDR_RMSK 0x1 +#define HWIO_GCC_CNOC_PERIPH_DCD_CDIV_DCDR_ATTR 0x3 +#define HWIO_GCC_CNOC_PERIPH_DCD_CDIV_DCDR_IN \ + in_dword_masked(HWIO_GCC_CNOC_PERIPH_DCD_CDIV_DCDR_ADDR, HWIO_GCC_CNOC_PERIPH_DCD_CDIV_DCDR_RMSK) +#define HWIO_GCC_CNOC_PERIPH_DCD_CDIV_DCDR_INM(m) \ + in_dword_masked(HWIO_GCC_CNOC_PERIPH_DCD_CDIV_DCDR_ADDR, m) +#define HWIO_GCC_CNOC_PERIPH_DCD_CDIV_DCDR_OUT(v) \ + out_dword(HWIO_GCC_CNOC_PERIPH_DCD_CDIV_DCDR_ADDR,v) +#define HWIO_GCC_CNOC_PERIPH_DCD_CDIV_DCDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CNOC_PERIPH_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_CNOC_PERIPH_DCD_CDIV_DCDR_IN) +#define HWIO_GCC_CNOC_PERIPH_DCD_CDIV_DCDR_DCD_ENABLE_BMSK 0x1 +#define HWIO_GCC_CNOC_PERIPH_DCD_CDIV_DCDR_DCD_ENABLE_SHFT 0x0 +#define HWIO_GCC_CNOC_PERIPH_DCD_CDIV_DCDR_DCD_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CNOC_PERIPH_DCD_CDIV_DCDR_DCD_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CFG_NOC_LPASS_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006476c) +#define HWIO_GCC_CFG_NOC_LPASS_DCD_CDIV_DCDR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006476c) +#define HWIO_GCC_CFG_NOC_LPASS_DCD_CDIV_DCDR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006476c) +#define HWIO_GCC_CFG_NOC_LPASS_DCD_CDIV_DCDR_RMSK 0x1 +#define HWIO_GCC_CFG_NOC_LPASS_DCD_CDIV_DCDR_ATTR 0x3 +#define HWIO_GCC_CFG_NOC_LPASS_DCD_CDIV_DCDR_IN \ + in_dword_masked(HWIO_GCC_CFG_NOC_LPASS_DCD_CDIV_DCDR_ADDR, HWIO_GCC_CFG_NOC_LPASS_DCD_CDIV_DCDR_RMSK) +#define HWIO_GCC_CFG_NOC_LPASS_DCD_CDIV_DCDR_INM(m) \ + in_dword_masked(HWIO_GCC_CFG_NOC_LPASS_DCD_CDIV_DCDR_ADDR, m) +#define HWIO_GCC_CFG_NOC_LPASS_DCD_CDIV_DCDR_OUT(v) \ + out_dword(HWIO_GCC_CFG_NOC_LPASS_DCD_CDIV_DCDR_ADDR,v) +#define HWIO_GCC_CFG_NOC_LPASS_DCD_CDIV_DCDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CFG_NOC_LPASS_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_CFG_NOC_LPASS_DCD_CDIV_DCDR_IN) +#define HWIO_GCC_CFG_NOC_LPASS_DCD_CDIV_DCDR_DCD_ENABLE_BMSK 0x1 +#define HWIO_GCC_CFG_NOC_LPASS_DCD_CDIV_DCDR_DCD_ENABLE_SHFT 0x0 +#define HWIO_GCC_CFG_NOC_LPASS_DCD_CDIV_DCDR_DCD_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CFG_NOC_LPASS_DCD_CDIV_DCDR_DCD_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064770) +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_DCD_CDIV_DCDR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064770) +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_DCD_CDIV_DCDR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064770) +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_DCD_CDIV_DCDR_RMSK 0x1 +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_DCD_CDIV_DCDR_ATTR 0x3 +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_DCD_CDIV_DCDR_IN \ + in_dword_masked(HWIO_GCC_CONFIG_NOC_DDRSS_SF_DCD_CDIV_DCDR_ADDR, HWIO_GCC_CONFIG_NOC_DDRSS_SF_DCD_CDIV_DCDR_RMSK) +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_DCD_CDIV_DCDR_INM(m) \ + in_dword_masked(HWIO_GCC_CONFIG_NOC_DDRSS_SF_DCD_CDIV_DCDR_ADDR, m) +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_DCD_CDIV_DCDR_OUT(v) \ + out_dword(HWIO_GCC_CONFIG_NOC_DDRSS_SF_DCD_CDIV_DCDR_ADDR,v) +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_DCD_CDIV_DCDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CONFIG_NOC_DDRSS_SF_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_CONFIG_NOC_DDRSS_SF_DCD_CDIV_DCDR_IN) +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_DCD_CDIV_DCDR_DCD_ENABLE_BMSK 0x1 +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_DCD_CDIV_DCDR_DCD_ENABLE_SHFT 0x0 +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_DCD_CDIV_DCDR_DCD_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CONFIG_NOC_DDRSS_SF_DCD_CDIV_DCDR_DCD_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CONFIG_NOC_CENTER_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064774) +#define HWIO_GCC_CONFIG_NOC_CENTER_DCD_CDIV_DCDR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064774) +#define HWIO_GCC_CONFIG_NOC_CENTER_DCD_CDIV_DCDR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064774) +#define HWIO_GCC_CONFIG_NOC_CENTER_DCD_CDIV_DCDR_RMSK 0x1 +#define HWIO_GCC_CONFIG_NOC_CENTER_DCD_CDIV_DCDR_ATTR 0x3 +#define HWIO_GCC_CONFIG_NOC_CENTER_DCD_CDIV_DCDR_IN \ + in_dword_masked(HWIO_GCC_CONFIG_NOC_CENTER_DCD_CDIV_DCDR_ADDR, HWIO_GCC_CONFIG_NOC_CENTER_DCD_CDIV_DCDR_RMSK) +#define HWIO_GCC_CONFIG_NOC_CENTER_DCD_CDIV_DCDR_INM(m) \ + in_dword_masked(HWIO_GCC_CONFIG_NOC_CENTER_DCD_CDIV_DCDR_ADDR, m) +#define HWIO_GCC_CONFIG_NOC_CENTER_DCD_CDIV_DCDR_OUT(v) \ + out_dword(HWIO_GCC_CONFIG_NOC_CENTER_DCD_CDIV_DCDR_ADDR,v) +#define HWIO_GCC_CONFIG_NOC_CENTER_DCD_CDIV_DCDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CONFIG_NOC_CENTER_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_CONFIG_NOC_CENTER_DCD_CDIV_DCDR_IN) +#define HWIO_GCC_CONFIG_NOC_CENTER_DCD_CDIV_DCDR_DCD_ENABLE_BMSK 0x1 +#define HWIO_GCC_CONFIG_NOC_CENTER_DCD_CDIV_DCDR_DCD_ENABLE_SHFT 0x0 +#define HWIO_GCC_CONFIG_NOC_CENTER_DCD_CDIV_DCDR_DCD_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CONFIG_NOC_CENTER_DCD_CDIV_DCDR_DCD_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CONFIG_NOC_WEST_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064778) +#define HWIO_GCC_CONFIG_NOC_WEST_DCD_CDIV_DCDR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064778) +#define HWIO_GCC_CONFIG_NOC_WEST_DCD_CDIV_DCDR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064778) +#define HWIO_GCC_CONFIG_NOC_WEST_DCD_CDIV_DCDR_RMSK 0x1 +#define HWIO_GCC_CONFIG_NOC_WEST_DCD_CDIV_DCDR_ATTR 0x3 +#define HWIO_GCC_CONFIG_NOC_WEST_DCD_CDIV_DCDR_IN \ + in_dword_masked(HWIO_GCC_CONFIG_NOC_WEST_DCD_CDIV_DCDR_ADDR, HWIO_GCC_CONFIG_NOC_WEST_DCD_CDIV_DCDR_RMSK) +#define HWIO_GCC_CONFIG_NOC_WEST_DCD_CDIV_DCDR_INM(m) \ + in_dword_masked(HWIO_GCC_CONFIG_NOC_WEST_DCD_CDIV_DCDR_ADDR, m) +#define HWIO_GCC_CONFIG_NOC_WEST_DCD_CDIV_DCDR_OUT(v) \ + out_dword(HWIO_GCC_CONFIG_NOC_WEST_DCD_CDIV_DCDR_ADDR,v) +#define HWIO_GCC_CONFIG_NOC_WEST_DCD_CDIV_DCDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CONFIG_NOC_WEST_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_CONFIG_NOC_WEST_DCD_CDIV_DCDR_IN) +#define HWIO_GCC_CONFIG_NOC_WEST_DCD_CDIV_DCDR_DCD_ENABLE_BMSK 0x1 +#define HWIO_GCC_CONFIG_NOC_WEST_DCD_CDIV_DCDR_DCD_ENABLE_SHFT 0x0 +#define HWIO_GCC_CONFIG_NOC_WEST_DCD_CDIV_DCDR_DCD_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CONFIG_NOC_WEST_DCD_CDIV_DCDR_DCD_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CONFIG_NOC_NORTH_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006477c) +#define HWIO_GCC_CONFIG_NOC_NORTH_DCD_CDIV_DCDR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006477c) +#define HWIO_GCC_CONFIG_NOC_NORTH_DCD_CDIV_DCDR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006477c) +#define HWIO_GCC_CONFIG_NOC_NORTH_DCD_CDIV_DCDR_RMSK 0x1 +#define HWIO_GCC_CONFIG_NOC_NORTH_DCD_CDIV_DCDR_ATTR 0x3 +#define HWIO_GCC_CONFIG_NOC_NORTH_DCD_CDIV_DCDR_IN \ + in_dword_masked(HWIO_GCC_CONFIG_NOC_NORTH_DCD_CDIV_DCDR_ADDR, HWIO_GCC_CONFIG_NOC_NORTH_DCD_CDIV_DCDR_RMSK) +#define HWIO_GCC_CONFIG_NOC_NORTH_DCD_CDIV_DCDR_INM(m) \ + in_dword_masked(HWIO_GCC_CONFIG_NOC_NORTH_DCD_CDIV_DCDR_ADDR, m) +#define HWIO_GCC_CONFIG_NOC_NORTH_DCD_CDIV_DCDR_OUT(v) \ + out_dword(HWIO_GCC_CONFIG_NOC_NORTH_DCD_CDIV_DCDR_ADDR,v) +#define HWIO_GCC_CONFIG_NOC_NORTH_DCD_CDIV_DCDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CONFIG_NOC_NORTH_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_CONFIG_NOC_NORTH_DCD_CDIV_DCDR_IN) +#define HWIO_GCC_CONFIG_NOC_NORTH_DCD_CDIV_DCDR_DCD_ENABLE_BMSK 0x1 +#define HWIO_GCC_CONFIG_NOC_NORTH_DCD_CDIV_DCDR_DCD_ENABLE_SHFT 0x0 +#define HWIO_GCC_CONFIG_NOC_NORTH_DCD_CDIV_DCDR_DCD_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CONFIG_NOC_NORTH_DCD_CDIV_DCDR_DCD_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CONFIG_NOC_EAST_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064780) +#define HWIO_GCC_CONFIG_NOC_EAST_DCD_CDIV_DCDR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064780) +#define HWIO_GCC_CONFIG_NOC_EAST_DCD_CDIV_DCDR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064780) +#define HWIO_GCC_CONFIG_NOC_EAST_DCD_CDIV_DCDR_RMSK 0x1 +#define HWIO_GCC_CONFIG_NOC_EAST_DCD_CDIV_DCDR_ATTR 0x3 +#define HWIO_GCC_CONFIG_NOC_EAST_DCD_CDIV_DCDR_IN \ + in_dword_masked(HWIO_GCC_CONFIG_NOC_EAST_DCD_CDIV_DCDR_ADDR, HWIO_GCC_CONFIG_NOC_EAST_DCD_CDIV_DCDR_RMSK) +#define HWIO_GCC_CONFIG_NOC_EAST_DCD_CDIV_DCDR_INM(m) \ + in_dword_masked(HWIO_GCC_CONFIG_NOC_EAST_DCD_CDIV_DCDR_ADDR, m) +#define HWIO_GCC_CONFIG_NOC_EAST_DCD_CDIV_DCDR_OUT(v) \ + out_dword(HWIO_GCC_CONFIG_NOC_EAST_DCD_CDIV_DCDR_ADDR,v) +#define HWIO_GCC_CONFIG_NOC_EAST_DCD_CDIV_DCDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CONFIG_NOC_EAST_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_CONFIG_NOC_EAST_DCD_CDIV_DCDR_IN) +#define HWIO_GCC_CONFIG_NOC_EAST_DCD_CDIV_DCDR_DCD_ENABLE_BMSK 0x1 +#define HWIO_GCC_CONFIG_NOC_EAST_DCD_CDIV_DCDR_DCD_ENABLE_SHFT 0x0 +#define HWIO_GCC_CONFIG_NOC_EAST_DCD_CDIV_DCDR_DCD_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CONFIG_NOC_EAST_DCD_CDIV_DCDR_DCD_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CONFIG_NOC_SOUTH_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064784) +#define HWIO_GCC_CONFIG_NOC_SOUTH_DCD_CDIV_DCDR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064784) +#define HWIO_GCC_CONFIG_NOC_SOUTH_DCD_CDIV_DCDR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064784) +#define HWIO_GCC_CONFIG_NOC_SOUTH_DCD_CDIV_DCDR_RMSK 0x1 +#define HWIO_GCC_CONFIG_NOC_SOUTH_DCD_CDIV_DCDR_ATTR 0x3 +#define HWIO_GCC_CONFIG_NOC_SOUTH_DCD_CDIV_DCDR_IN \ + in_dword_masked(HWIO_GCC_CONFIG_NOC_SOUTH_DCD_CDIV_DCDR_ADDR, HWIO_GCC_CONFIG_NOC_SOUTH_DCD_CDIV_DCDR_RMSK) +#define HWIO_GCC_CONFIG_NOC_SOUTH_DCD_CDIV_DCDR_INM(m) \ + in_dword_masked(HWIO_GCC_CONFIG_NOC_SOUTH_DCD_CDIV_DCDR_ADDR, m) +#define HWIO_GCC_CONFIG_NOC_SOUTH_DCD_CDIV_DCDR_OUT(v) \ + out_dword(HWIO_GCC_CONFIG_NOC_SOUTH_DCD_CDIV_DCDR_ADDR,v) +#define HWIO_GCC_CONFIG_NOC_SOUTH_DCD_CDIV_DCDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CONFIG_NOC_SOUTH_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_CONFIG_NOC_SOUTH_DCD_CDIV_DCDR_IN) +#define HWIO_GCC_CONFIG_NOC_SOUTH_DCD_CDIV_DCDR_DCD_ENABLE_BMSK 0x1 +#define HWIO_GCC_CONFIG_NOC_SOUTH_DCD_CDIV_DCDR_DCD_ENABLE_SHFT 0x0 +#define HWIO_GCC_CONFIG_NOC_SOUTH_DCD_CDIV_DCDR_DCD_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CONFIG_NOC_SOUTH_DCD_CDIV_DCDR_DCD_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CONFIG_NOC_MMNOC_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064788) +#define HWIO_GCC_CONFIG_NOC_MMNOC_DCD_CDIV_DCDR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064788) +#define HWIO_GCC_CONFIG_NOC_MMNOC_DCD_CDIV_DCDR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064788) +#define HWIO_GCC_CONFIG_NOC_MMNOC_DCD_CDIV_DCDR_RMSK 0x1 +#define HWIO_GCC_CONFIG_NOC_MMNOC_DCD_CDIV_DCDR_ATTR 0x3 +#define HWIO_GCC_CONFIG_NOC_MMNOC_DCD_CDIV_DCDR_IN \ + in_dword_masked(HWIO_GCC_CONFIG_NOC_MMNOC_DCD_CDIV_DCDR_ADDR, HWIO_GCC_CONFIG_NOC_MMNOC_DCD_CDIV_DCDR_RMSK) +#define HWIO_GCC_CONFIG_NOC_MMNOC_DCD_CDIV_DCDR_INM(m) \ + in_dword_masked(HWIO_GCC_CONFIG_NOC_MMNOC_DCD_CDIV_DCDR_ADDR, m) +#define HWIO_GCC_CONFIG_NOC_MMNOC_DCD_CDIV_DCDR_OUT(v) \ + out_dword(HWIO_GCC_CONFIG_NOC_MMNOC_DCD_CDIV_DCDR_ADDR,v) +#define HWIO_GCC_CONFIG_NOC_MMNOC_DCD_CDIV_DCDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CONFIG_NOC_MMNOC_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_CONFIG_NOC_MMNOC_DCD_CDIV_DCDR_IN) +#define HWIO_GCC_CONFIG_NOC_MMNOC_DCD_CDIV_DCDR_DCD_ENABLE_BMSK 0x1 +#define HWIO_GCC_CONFIG_NOC_MMNOC_DCD_CDIV_DCDR_DCD_ENABLE_SHFT 0x0 +#define HWIO_GCC_CONFIG_NOC_MMNOC_DCD_CDIV_DCDR_DCD_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CONFIG_NOC_MMNOC_DCD_CDIV_DCDR_DCD_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CNOC_CENTER_QX_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006478c) +#define HWIO_GCC_CNOC_CENTER_QX_DCD_CDIV_DCDR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006478c) +#define HWIO_GCC_CNOC_CENTER_QX_DCD_CDIV_DCDR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006478c) +#define HWIO_GCC_CNOC_CENTER_QX_DCD_CDIV_DCDR_RMSK 0x1 +#define HWIO_GCC_CNOC_CENTER_QX_DCD_CDIV_DCDR_ATTR 0x3 +#define HWIO_GCC_CNOC_CENTER_QX_DCD_CDIV_DCDR_IN \ + in_dword_masked(HWIO_GCC_CNOC_CENTER_QX_DCD_CDIV_DCDR_ADDR, HWIO_GCC_CNOC_CENTER_QX_DCD_CDIV_DCDR_RMSK) +#define HWIO_GCC_CNOC_CENTER_QX_DCD_CDIV_DCDR_INM(m) \ + in_dword_masked(HWIO_GCC_CNOC_CENTER_QX_DCD_CDIV_DCDR_ADDR, m) +#define HWIO_GCC_CNOC_CENTER_QX_DCD_CDIV_DCDR_OUT(v) \ + out_dword(HWIO_GCC_CNOC_CENTER_QX_DCD_CDIV_DCDR_ADDR,v) +#define HWIO_GCC_CNOC_CENTER_QX_DCD_CDIV_DCDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CNOC_CENTER_QX_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_CNOC_CENTER_QX_DCD_CDIV_DCDR_IN) +#define HWIO_GCC_CNOC_CENTER_QX_DCD_CDIV_DCDR_DCD_ENABLE_BMSK 0x1 +#define HWIO_GCC_CNOC_CENTER_QX_DCD_CDIV_DCDR_DCD_ENABLE_SHFT 0x0 +#define HWIO_GCC_CNOC_CENTER_QX_DCD_CDIV_DCDR_DCD_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CNOC_CENTER_QX_DCD_CDIV_DCDR_DCD_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CNOC_NORTH_QX_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064790) +#define HWIO_GCC_CNOC_NORTH_QX_DCD_CDIV_DCDR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064790) +#define HWIO_GCC_CNOC_NORTH_QX_DCD_CDIV_DCDR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064790) +#define HWIO_GCC_CNOC_NORTH_QX_DCD_CDIV_DCDR_RMSK 0x1 +#define HWIO_GCC_CNOC_NORTH_QX_DCD_CDIV_DCDR_ATTR 0x3 +#define HWIO_GCC_CNOC_NORTH_QX_DCD_CDIV_DCDR_IN \ + in_dword_masked(HWIO_GCC_CNOC_NORTH_QX_DCD_CDIV_DCDR_ADDR, HWIO_GCC_CNOC_NORTH_QX_DCD_CDIV_DCDR_RMSK) +#define HWIO_GCC_CNOC_NORTH_QX_DCD_CDIV_DCDR_INM(m) \ + in_dword_masked(HWIO_GCC_CNOC_NORTH_QX_DCD_CDIV_DCDR_ADDR, m) +#define HWIO_GCC_CNOC_NORTH_QX_DCD_CDIV_DCDR_OUT(v) \ + out_dword(HWIO_GCC_CNOC_NORTH_QX_DCD_CDIV_DCDR_ADDR,v) +#define HWIO_GCC_CNOC_NORTH_QX_DCD_CDIV_DCDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CNOC_NORTH_QX_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_CNOC_NORTH_QX_DCD_CDIV_DCDR_IN) +#define HWIO_GCC_CNOC_NORTH_QX_DCD_CDIV_DCDR_DCD_ENABLE_BMSK 0x1 +#define HWIO_GCC_CNOC_NORTH_QX_DCD_CDIV_DCDR_DCD_ENABLE_SHFT 0x0 +#define HWIO_GCC_CNOC_NORTH_QX_DCD_CDIV_DCDR_DCD_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CNOC_NORTH_QX_DCD_CDIV_DCDR_DCD_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_AGGRE_NOC_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00072000) +#define HWIO_GCC_AGGRE_NOC_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00072000) +#define HWIO_GCC_AGGRE_NOC_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00072000) +#define HWIO_GCC_AGGRE_NOC_BCR_RMSK 0x1 +#define HWIO_GCC_AGGRE_NOC_BCR_ATTR 0x3 +#define HWIO_GCC_AGGRE_NOC_BCR_IN \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_BCR_ADDR, HWIO_GCC_AGGRE_NOC_BCR_RMSK) +#define HWIO_GCC_AGGRE_NOC_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_BCR_ADDR, m) +#define HWIO_GCC_AGGRE_NOC_BCR_OUT(v) \ + out_dword(HWIO_GCC_AGGRE_NOC_BCR_ADDR,v) +#define HWIO_GCC_AGGRE_NOC_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_BCR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_BCR_IN) +#define HWIO_GCC_AGGRE_NOC_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_AGGRE_NOC_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_AGGRE_NOC_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CFG_NOC_PCIE_ANOC_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000028) +#define HWIO_GCC_CFG_NOC_PCIE_ANOC_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000028) +#define HWIO_GCC_CFG_NOC_PCIE_ANOC_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000028) +#define HWIO_GCC_CFG_NOC_PCIE_ANOC_AHB_CBCR_RMSK 0x81d0000e +#define HWIO_GCC_CFG_NOC_PCIE_ANOC_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_CFG_NOC_PCIE_ANOC_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_CFG_NOC_PCIE_ANOC_AHB_CBCR_ADDR, HWIO_GCC_CFG_NOC_PCIE_ANOC_AHB_CBCR_RMSK) +#define HWIO_GCC_CFG_NOC_PCIE_ANOC_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_CFG_NOC_PCIE_ANOC_AHB_CBCR_ADDR, m) +#define HWIO_GCC_CFG_NOC_PCIE_ANOC_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_CFG_NOC_PCIE_ANOC_AHB_CBCR_ADDR,v) +#define HWIO_GCC_CFG_NOC_PCIE_ANOC_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CFG_NOC_PCIE_ANOC_AHB_CBCR_ADDR,m,v,HWIO_GCC_CFG_NOC_PCIE_ANOC_AHB_CBCR_IN) +#define HWIO_GCC_CFG_NOC_PCIE_ANOC_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_CFG_NOC_PCIE_ANOC_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_CFG_NOC_PCIE_ANOC_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_CFG_NOC_PCIE_ANOC_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_CFG_NOC_PCIE_ANOC_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_CFG_NOC_PCIE_ANOC_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_CFG_NOC_PCIE_ANOC_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_CFG_NOC_PCIE_ANOC_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_CFG_NOC_PCIE_ANOC_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_CFG_NOC_PCIE_ANOC_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_CFG_NOC_PCIE_ANOC_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_CFG_NOC_PCIE_ANOC_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_CFG_NOC_PCIE_ANOC_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_CFG_NOC_PCIE_ANOC_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_CFG_NOC_PCIE_ANOC_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_CFG_NOC_PCIE_ANOC_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_CFG_NOC_PCIE_ANOC_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_CFG_NOC_PCIE_ANOC_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_CFG_NOC_PCIE_ANOC_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_CFG_NOC_PCIE_ANOC_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 + +#define HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00072004) +#define HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00072004) +#define HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00072004) +#define HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_ATTR 0x3 +#define HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_IN \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_ADDR, HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_RMSK) +#define HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_ADDR, m) +#define HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_OUT(v) \ + out_dword(HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_ADDR,v) +#define HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_IN) +#define HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_AGGRE_NOC_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00072008) +#define HWIO_GCC_AGGRE_NOC_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00072008) +#define HWIO_GCC_AGGRE_NOC_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00072008) +#define HWIO_GCC_AGGRE_NOC_AHB_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_AGGRE_NOC_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_AGGRE_NOC_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_AHB_CBCR_ADDR, HWIO_GCC_AGGRE_NOC_AHB_CBCR_RMSK) +#define HWIO_GCC_AGGRE_NOC_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_AHB_CBCR_ADDR, m) +#define HWIO_GCC_AGGRE_NOC_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_AGGRE_NOC_AHB_CBCR_ADDR,v) +#define HWIO_GCC_AGGRE_NOC_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_AHB_CBCR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_AHB_CBCR_IN) +#define HWIO_GCC_AGGRE_NOC_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_AGGRE_NOC_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_AGGRE_NOC_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_AGGRE_NOC_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_AGGRE_NOC_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_AGGRE_NOC_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_AGGRE_NOC_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_AGGRE_NOC_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_AGGRE_NOC_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_AGGRE_NOC_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_AGGRE_NOC_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_AGGRE_NOC_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_AGGRE_NOC_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_AGGRE_NOC_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_AGGRE_NOC_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_AGGRE_NOC_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_AGGRE_NOC_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_AGGRE_NOC_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_AGGRE_NOC_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QMIP_AGGRE_NOC_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007200c) +#define HWIO_GCC_QMIP_AGGRE_NOC_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007200c) +#define HWIO_GCC_QMIP_AGGRE_NOC_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007200c) +#define HWIO_GCC_QMIP_AGGRE_NOC_AHB_CBCR_RMSK 0x81d0000e +#define HWIO_GCC_QMIP_AGGRE_NOC_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_QMIP_AGGRE_NOC_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_QMIP_AGGRE_NOC_AHB_CBCR_ADDR, HWIO_GCC_QMIP_AGGRE_NOC_AHB_CBCR_RMSK) +#define HWIO_GCC_QMIP_AGGRE_NOC_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QMIP_AGGRE_NOC_AHB_CBCR_ADDR, m) +#define HWIO_GCC_QMIP_AGGRE_NOC_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QMIP_AGGRE_NOC_AHB_CBCR_ADDR,v) +#define HWIO_GCC_QMIP_AGGRE_NOC_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QMIP_AGGRE_NOC_AHB_CBCR_ADDR,m,v,HWIO_GCC_QMIP_AGGRE_NOC_AHB_CBCR_IN) +#define HWIO_GCC_QMIP_AGGRE_NOC_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QMIP_AGGRE_NOC_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QMIP_AGGRE_NOC_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QMIP_AGGRE_NOC_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QMIP_AGGRE_NOC_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QMIP_AGGRE_NOC_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QMIP_AGGRE_NOC_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QMIP_AGGRE_NOC_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QMIP_AGGRE_NOC_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_QMIP_AGGRE_NOC_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_QMIP_AGGRE_NOC_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_QMIP_AGGRE_NOC_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_QMIP_AGGRE_NOC_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QMIP_AGGRE_NOC_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QMIP_AGGRE_NOC_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QMIP_AGGRE_NOC_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_QMIP_AGGRE_NOC_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_QMIP_AGGRE_NOC_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_QMIP_AGGRE_NOC_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QMIP_AGGRE_NOC_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 + +#define HWIO_GCC_AGGRE_CNOC_PERIPH_NORTH_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00072010) +#define HWIO_GCC_AGGRE_CNOC_PERIPH_NORTH_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00072010) +#define HWIO_GCC_AGGRE_CNOC_PERIPH_NORTH_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00072010) +#define HWIO_GCC_AGGRE_CNOC_PERIPH_NORTH_AHB_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_AGGRE_CNOC_PERIPH_NORTH_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_AGGRE_CNOC_PERIPH_NORTH_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_AGGRE_CNOC_PERIPH_NORTH_AHB_CBCR_ADDR, HWIO_GCC_AGGRE_CNOC_PERIPH_NORTH_AHB_CBCR_RMSK) +#define HWIO_GCC_AGGRE_CNOC_PERIPH_NORTH_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_AGGRE_CNOC_PERIPH_NORTH_AHB_CBCR_ADDR, m) +#define HWIO_GCC_AGGRE_CNOC_PERIPH_NORTH_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_AGGRE_CNOC_PERIPH_NORTH_AHB_CBCR_ADDR,v) +#define HWIO_GCC_AGGRE_CNOC_PERIPH_NORTH_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AGGRE_CNOC_PERIPH_NORTH_AHB_CBCR_ADDR,m,v,HWIO_GCC_AGGRE_CNOC_PERIPH_NORTH_AHB_CBCR_IN) +#define HWIO_GCC_AGGRE_CNOC_PERIPH_NORTH_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_AGGRE_CNOC_PERIPH_NORTH_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_AGGRE_CNOC_PERIPH_NORTH_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_AGGRE_CNOC_PERIPH_NORTH_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_AGGRE_CNOC_PERIPH_NORTH_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_AGGRE_CNOC_PERIPH_NORTH_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_AGGRE_CNOC_PERIPH_NORTH_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_AGGRE_CNOC_PERIPH_NORTH_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_AGGRE_CNOC_PERIPH_NORTH_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_AGGRE_CNOC_PERIPH_NORTH_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_AGGRE_CNOC_PERIPH_NORTH_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_AGGRE_CNOC_PERIPH_NORTH_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_AGGRE_CNOC_PERIPH_NORTH_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_AGGRE_CNOC_PERIPH_NORTH_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_AGGRE_CNOC_PERIPH_NORTH_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_AGGRE_CNOC_PERIPH_NORTH_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_AGGRE_CNOC_PERIPH_NORTH_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_AGGRE_CNOC_PERIPH_NORTH_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_AGGRE_CNOC_PERIPH_NORTH_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_CNOC_PERIPH_NORTH_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_AGGRE_CNOC_PERIPH_NORTH_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_AGGRE_CNOC_PERIPH_NORTH_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_AGGRE_CNOC_PERIPH_NORTH_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_CNOC_PERIPH_NORTH_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_AGGRE_CNOC_PERIPH_SOUTH_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00072014) +#define HWIO_GCC_AGGRE_CNOC_PERIPH_SOUTH_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00072014) +#define HWIO_GCC_AGGRE_CNOC_PERIPH_SOUTH_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00072014) +#define HWIO_GCC_AGGRE_CNOC_PERIPH_SOUTH_AHB_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_AGGRE_CNOC_PERIPH_SOUTH_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_AGGRE_CNOC_PERIPH_SOUTH_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_AGGRE_CNOC_PERIPH_SOUTH_AHB_CBCR_ADDR, HWIO_GCC_AGGRE_CNOC_PERIPH_SOUTH_AHB_CBCR_RMSK) +#define HWIO_GCC_AGGRE_CNOC_PERIPH_SOUTH_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_AGGRE_CNOC_PERIPH_SOUTH_AHB_CBCR_ADDR, m) +#define HWIO_GCC_AGGRE_CNOC_PERIPH_SOUTH_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_AGGRE_CNOC_PERIPH_SOUTH_AHB_CBCR_ADDR,v) +#define HWIO_GCC_AGGRE_CNOC_PERIPH_SOUTH_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AGGRE_CNOC_PERIPH_SOUTH_AHB_CBCR_ADDR,m,v,HWIO_GCC_AGGRE_CNOC_PERIPH_SOUTH_AHB_CBCR_IN) +#define HWIO_GCC_AGGRE_CNOC_PERIPH_SOUTH_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_AGGRE_CNOC_PERIPH_SOUTH_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_AGGRE_CNOC_PERIPH_SOUTH_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_AGGRE_CNOC_PERIPH_SOUTH_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_AGGRE_CNOC_PERIPH_SOUTH_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_AGGRE_CNOC_PERIPH_SOUTH_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_AGGRE_CNOC_PERIPH_SOUTH_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_AGGRE_CNOC_PERIPH_SOUTH_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_AGGRE_CNOC_PERIPH_SOUTH_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_AGGRE_CNOC_PERIPH_SOUTH_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_AGGRE_CNOC_PERIPH_SOUTH_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_AGGRE_CNOC_PERIPH_SOUTH_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_AGGRE_CNOC_PERIPH_SOUTH_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_AGGRE_CNOC_PERIPH_SOUTH_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_AGGRE_CNOC_PERIPH_SOUTH_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_AGGRE_CNOC_PERIPH_SOUTH_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_AGGRE_CNOC_PERIPH_SOUTH_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_AGGRE_CNOC_PERIPH_SOUTH_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_AGGRE_CNOC_PERIPH_SOUTH_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_CNOC_PERIPH_SOUTH_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_AGGRE_CNOC_PERIPH_SOUTH_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_AGGRE_CNOC_PERIPH_SOUTH_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_AGGRE_CNOC_PERIPH_SOUTH_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_CNOC_PERIPH_SOUTH_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_AGGRE_NOC_QOSGEN_EXTREF_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00072018) +#define HWIO_GCC_AGGRE_NOC_QOSGEN_EXTREF_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00072018) +#define HWIO_GCC_AGGRE_NOC_QOSGEN_EXTREF_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00072018) +#define HWIO_GCC_AGGRE_NOC_QOSGEN_EXTREF_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_AGGRE_NOC_QOSGEN_EXTREF_CBCR_ATTR 0x3 +#define HWIO_GCC_AGGRE_NOC_QOSGEN_EXTREF_CBCR_IN \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_QOSGEN_EXTREF_CBCR_ADDR, HWIO_GCC_AGGRE_NOC_QOSGEN_EXTREF_CBCR_RMSK) +#define HWIO_GCC_AGGRE_NOC_QOSGEN_EXTREF_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_QOSGEN_EXTREF_CBCR_ADDR, m) +#define HWIO_GCC_AGGRE_NOC_QOSGEN_EXTREF_CBCR_OUT(v) \ + out_dword(HWIO_GCC_AGGRE_NOC_QOSGEN_EXTREF_CBCR_ADDR,v) +#define HWIO_GCC_AGGRE_NOC_QOSGEN_EXTREF_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_QOSGEN_EXTREF_CBCR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_QOSGEN_EXTREF_CBCR_IN) +#define HWIO_GCC_AGGRE_NOC_QOSGEN_EXTREF_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_AGGRE_NOC_QOSGEN_EXTREF_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_AGGRE_NOC_QOSGEN_EXTREF_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_AGGRE_NOC_QOSGEN_EXTREF_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_AGGRE_NOC_QOSGEN_EXTREF_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_AGGRE_NOC_QOSGEN_EXTREF_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_AGGRE_NOC_QOSGEN_EXTREF_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_AGGRE_NOC_QOSGEN_EXTREF_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_AGGRE_NOC_QOSGEN_EXTREF_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_AGGRE_NOC_QOSGEN_EXTREF_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_AGGRE_NOC_QOSGEN_EXTREF_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_QOSGEN_EXTREF_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_QOSGEN_EXTREF_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_AGGRE_NOC_QOSGEN_EXTREF_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_AGGRE_NOC_QOSGEN_EXTREF_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_QOSGEN_EXTREF_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007201c) +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007201c) +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007201c) +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_RMSK 0x81d0700f +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_ATTR 0x3 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_IN \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_ADDR, HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_RMSK) +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_ADDR, m) +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_OUT(v) \ + out_dword(HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_ADDR,v) +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_IN) +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00072020) +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00072020) +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00072020) +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_RMSK 0xf1ffffe +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_ATTR 0x3 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_IN \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_ADDR, HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_RMSK) +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_ADDR, m) +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_OUT(v) \ + out_dword(HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_ADDR,v) +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_IN) +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xf000000 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_PWR_FSM_CLK_SEL_BMSK 0x100000 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_PWR_FSM_CLK_SEL_SHFT 0x14 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xf0000 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CFG_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00072024) +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CFG_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00072024) +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CFG_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00072024) +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CFG_SREGR_RMSK 0xffffffff +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CFG_SREGR_ATTR 0x3 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CFG_SREGR_IN \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_CENTER_AXI_CFG_SREGR_ADDR, HWIO_GCC_AGGRE_NOC_CENTER_AXI_CFG_SREGR_RMSK) +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CFG_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_CENTER_AXI_CFG_SREGR_ADDR, m) +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CFG_SREGR_OUT(v) \ + out_dword(HWIO_GCC_AGGRE_NOC_CENTER_AXI_CFG_SREGR_ADDR,v) +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CFG_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_CENTER_AXI_CFG_SREGR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_CENTER_AXI_CFG_SREGR_IN) +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CFG_SREGR_MEM_CORE_OFF_TIMER_BMSK 0xfc000000 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CFG_SREGR_MEM_CORE_OFF_TIMER_SHFT 0x1a +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_BMSK 0x2000000 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_SHFT 0x19 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_BMSK 0x1000000 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_SHFT 0x18 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CFG_SREGR_MEM_PERIPH_ON_STATUS_BMSK 0x800000 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CFG_SREGR_MEM_PERIPH_ON_STATUS_SHFT 0x17 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CFG_SREGR_MEM_CORE_ON_STATUS_BMSK 0x400000 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CFG_SREGR_MEM_CORE_ON_STATUS_SHFT 0x16 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CFG_SREGR_MEM_CPH_TIMER_BMSK 0x3f0000 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CFG_SREGR_MEM_CPH_TIMER_SHFT 0x10 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CFG_SREGR_SLEEP_TIMER_BMSK 0xff00 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CFG_SREGR_SLEEP_TIMER_SHFT 0x8 +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CFG_SREGR_WAKEUP_TIMER_BMSK 0xff +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CFG_SREGR_WAKEUP_TIMER_SHFT 0x0 + +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00072028) +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00072028) +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00072028) +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CBCR_RMSK 0x81d0700f +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CBCR_ATTR 0x3 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CBCR_IN \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_QDSS_BAM_CBCR_ADDR, HWIO_GCC_AGGRE_NOC_QDSS_BAM_CBCR_RMSK) +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_QDSS_BAM_CBCR_ADDR, m) +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CBCR_OUT(v) \ + out_dword(HWIO_GCC_AGGRE_NOC_QDSS_BAM_CBCR_ADDR,v) +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_QDSS_BAM_CBCR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_QDSS_BAM_CBCR_IN) +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007202c) +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007202c) +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007202c) +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_RMSK 0xf1ffffe +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_ATTR 0x3 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_IN \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_ADDR, HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_RMSK) +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_ADDR, m) +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_OUT(v) \ + out_dword(HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_ADDR,v) +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_IN) +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xf000000 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_PWR_FSM_CLK_SEL_BMSK 0x100000 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_PWR_FSM_CLK_SEL_SHFT 0x14 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xf0000 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CFG_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00072030) +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CFG_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00072030) +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CFG_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00072030) +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CFG_SREGR_RMSK 0xffffffff +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CFG_SREGR_ATTR 0x3 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CFG_SREGR_IN \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_QDSS_BAM_CFG_SREGR_ADDR, HWIO_GCC_AGGRE_NOC_QDSS_BAM_CFG_SREGR_RMSK) +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CFG_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_QDSS_BAM_CFG_SREGR_ADDR, m) +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CFG_SREGR_OUT(v) \ + out_dword(HWIO_GCC_AGGRE_NOC_QDSS_BAM_CFG_SREGR_ADDR,v) +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CFG_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_QDSS_BAM_CFG_SREGR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_QDSS_BAM_CFG_SREGR_IN) +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CFG_SREGR_MEM_CORE_OFF_TIMER_BMSK 0xfc000000 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CFG_SREGR_MEM_CORE_OFF_TIMER_SHFT 0x1a +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_BMSK 0x2000000 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_SHFT 0x19 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_BMSK 0x1000000 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_SHFT 0x18 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CFG_SREGR_MEM_PERIPH_ON_STATUS_BMSK 0x800000 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CFG_SREGR_MEM_PERIPH_ON_STATUS_SHFT 0x17 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CFG_SREGR_MEM_CORE_ON_STATUS_BMSK 0x400000 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CFG_SREGR_MEM_CORE_ON_STATUS_SHFT 0x16 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CFG_SREGR_MEM_CPH_TIMER_BMSK 0x3f0000 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CFG_SREGR_MEM_CPH_TIMER_SHFT 0x10 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CFG_SREGR_SLEEP_TIMER_BMSK 0xff00 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CFG_SREGR_SLEEP_TIMER_SHFT 0x8 +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CFG_SREGR_WAKEUP_TIMER_BMSK 0xff +#define HWIO_GCC_AGGRE_NOC_QDSS_BAM_CFG_SREGR_WAKEUP_TIMER_SHFT 0x0 + +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00072034) +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00072034) +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00072034) +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CBCR_RMSK 0x81d0700f +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CBCR_ATTR 0x3 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CBCR_IN \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CBCR_ADDR, HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CBCR_RMSK) +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CBCR_ADDR, m) +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CBCR_OUT(v) \ + out_dword(HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CBCR_ADDR,v) +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CBCR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CBCR_IN) +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00072038) +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00072038) +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00072038) +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_RMSK 0xf1ffffe +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_ATTR 0x3 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_IN \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_ADDR, HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_RMSK) +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_ADDR, m) +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_OUT(v) \ + out_dword(HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_ADDR,v) +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_IN) +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xf000000 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_PWR_FSM_CLK_SEL_BMSK 0x100000 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_PWR_FSM_CLK_SEL_SHFT 0x14 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xf0000 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CFG_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007203c) +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CFG_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007203c) +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CFG_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007203c) +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CFG_SREGR_RMSK 0xffffffff +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CFG_SREGR_ATTR 0x3 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CFG_SREGR_IN \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CFG_SREGR_ADDR, HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CFG_SREGR_RMSK) +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CFG_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CFG_SREGR_ADDR, m) +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CFG_SREGR_OUT(v) \ + out_dword(HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CFG_SREGR_ADDR,v) +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CFG_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CFG_SREGR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CFG_SREGR_IN) +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CFG_SREGR_MEM_CORE_OFF_TIMER_BMSK 0xfc000000 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CFG_SREGR_MEM_CORE_OFF_TIMER_SHFT 0x1a +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_BMSK 0x2000000 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_SHFT 0x19 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_BMSK 0x1000000 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_SHFT 0x18 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CFG_SREGR_MEM_PERIPH_ON_STATUS_BMSK 0x800000 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CFG_SREGR_MEM_PERIPH_ON_STATUS_SHFT 0x17 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CFG_SREGR_MEM_CORE_ON_STATUS_BMSK 0x400000 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CFG_SREGR_MEM_CORE_ON_STATUS_SHFT 0x16 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CFG_SREGR_MEM_CPH_TIMER_BMSK 0x3f0000 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CFG_SREGR_MEM_CPH_TIMER_SHFT 0x10 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CFG_SREGR_SLEEP_TIMER_BMSK 0xff00 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CFG_SREGR_SLEEP_TIMER_SHFT 0x8 +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CFG_SREGR_WAKEUP_TIMER_BMSK 0xff +#define HWIO_GCC_AGGRE_NOC_CENTER_HS_AXI_CFG_SREGR_WAKEUP_TIMER_SHFT 0x0 + +#define HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00072040) +#define HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00072040) +#define HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00072040) +#define HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_ATTR 0x3 +#define HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_IN \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_ADDR, HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_RMSK) +#define HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_ADDR, m) +#define HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_OUT(v) \ + out_dword(HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_ADDR,v) +#define HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_IN) +#define HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_AGGRE_NOC_WEST_TUNNEL_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00072044) +#define HWIO_GCC_AGGRE_NOC_WEST_TUNNEL_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00072044) +#define HWIO_GCC_AGGRE_NOC_WEST_TUNNEL_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00072044) +#define HWIO_GCC_AGGRE_NOC_WEST_TUNNEL_CBCR_RMSK 0x81d00005 +#define HWIO_GCC_AGGRE_NOC_WEST_TUNNEL_CBCR_ATTR 0x3 +#define HWIO_GCC_AGGRE_NOC_WEST_TUNNEL_CBCR_IN \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_WEST_TUNNEL_CBCR_ADDR, HWIO_GCC_AGGRE_NOC_WEST_TUNNEL_CBCR_RMSK) +#define HWIO_GCC_AGGRE_NOC_WEST_TUNNEL_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_WEST_TUNNEL_CBCR_ADDR, m) +#define HWIO_GCC_AGGRE_NOC_WEST_TUNNEL_CBCR_OUT(v) \ + out_dword(HWIO_GCC_AGGRE_NOC_WEST_TUNNEL_CBCR_ADDR,v) +#define HWIO_GCC_AGGRE_NOC_WEST_TUNNEL_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_WEST_TUNNEL_CBCR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_WEST_TUNNEL_CBCR_IN) +#define HWIO_GCC_AGGRE_NOC_WEST_TUNNEL_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_AGGRE_NOC_WEST_TUNNEL_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_AGGRE_NOC_WEST_TUNNEL_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_AGGRE_NOC_WEST_TUNNEL_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_AGGRE_NOC_WEST_TUNNEL_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_AGGRE_NOC_WEST_TUNNEL_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_AGGRE_NOC_WEST_TUNNEL_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_AGGRE_NOC_WEST_TUNNEL_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_AGGRE_NOC_WEST_TUNNEL_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_AGGRE_NOC_WEST_TUNNEL_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_AGGRE_NOC_WEST_TUNNEL_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_AGGRE_NOC_WEST_TUNNEL_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_AGGRE_NOC_WEST_TUNNEL_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_WEST_TUNNEL_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_WEST_TUNNEL_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_AGGRE_NOC_WEST_TUNNEL_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_AGGRE_NOC_WEST_TUNNEL_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_WEST_TUNNEL_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_AGGRE_NOC_EAST_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00072048) +#define HWIO_GCC_AGGRE_NOC_EAST_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00072048) +#define HWIO_GCC_AGGRE_NOC_EAST_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00072048) +#define HWIO_GCC_AGGRE_NOC_EAST_AXI_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_AGGRE_NOC_EAST_AXI_CBCR_ATTR 0x3 +#define HWIO_GCC_AGGRE_NOC_EAST_AXI_CBCR_IN \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_EAST_AXI_CBCR_ADDR, HWIO_GCC_AGGRE_NOC_EAST_AXI_CBCR_RMSK) +#define HWIO_GCC_AGGRE_NOC_EAST_AXI_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_EAST_AXI_CBCR_ADDR, m) +#define HWIO_GCC_AGGRE_NOC_EAST_AXI_CBCR_OUT(v) \ + out_dword(HWIO_GCC_AGGRE_NOC_EAST_AXI_CBCR_ADDR,v) +#define HWIO_GCC_AGGRE_NOC_EAST_AXI_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_EAST_AXI_CBCR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_EAST_AXI_CBCR_IN) +#define HWIO_GCC_AGGRE_NOC_EAST_AXI_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_AGGRE_NOC_EAST_AXI_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_AGGRE_NOC_EAST_AXI_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_AGGRE_NOC_EAST_AXI_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_AGGRE_NOC_EAST_AXI_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_AGGRE_NOC_EAST_AXI_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_AGGRE_NOC_EAST_AXI_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_AGGRE_NOC_EAST_AXI_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_AGGRE_NOC_EAST_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_AGGRE_NOC_EAST_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_AGGRE_NOC_EAST_AXI_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_AGGRE_NOC_EAST_AXI_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_AGGRE_NOC_EAST_AXI_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_AGGRE_NOC_EAST_AXI_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_AGGRE_NOC_EAST_AXI_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_EAST_AXI_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_EAST_AXI_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_AGGRE_NOC_EAST_AXI_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_AGGRE_NOC_EAST_AXI_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_EAST_AXI_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_EAST_AXI_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_AGGRE_NOC_EAST_AXI_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_AGGRE_NOC_EAST_AXI_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_EAST_AXI_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_AGGRE_NOC_EAST_TUNNEL_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007204c) +#define HWIO_GCC_AGGRE_NOC_EAST_TUNNEL_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007204c) +#define HWIO_GCC_AGGRE_NOC_EAST_TUNNEL_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007204c) +#define HWIO_GCC_AGGRE_NOC_EAST_TUNNEL_CBCR_RMSK 0x81d00005 +#define HWIO_GCC_AGGRE_NOC_EAST_TUNNEL_CBCR_ATTR 0x3 +#define HWIO_GCC_AGGRE_NOC_EAST_TUNNEL_CBCR_IN \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_EAST_TUNNEL_CBCR_ADDR, HWIO_GCC_AGGRE_NOC_EAST_TUNNEL_CBCR_RMSK) +#define HWIO_GCC_AGGRE_NOC_EAST_TUNNEL_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_EAST_TUNNEL_CBCR_ADDR, m) +#define HWIO_GCC_AGGRE_NOC_EAST_TUNNEL_CBCR_OUT(v) \ + out_dword(HWIO_GCC_AGGRE_NOC_EAST_TUNNEL_CBCR_ADDR,v) +#define HWIO_GCC_AGGRE_NOC_EAST_TUNNEL_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_EAST_TUNNEL_CBCR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_EAST_TUNNEL_CBCR_IN) +#define HWIO_GCC_AGGRE_NOC_EAST_TUNNEL_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_AGGRE_NOC_EAST_TUNNEL_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_AGGRE_NOC_EAST_TUNNEL_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_AGGRE_NOC_EAST_TUNNEL_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_AGGRE_NOC_EAST_TUNNEL_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_AGGRE_NOC_EAST_TUNNEL_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_AGGRE_NOC_EAST_TUNNEL_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_AGGRE_NOC_EAST_TUNNEL_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_AGGRE_NOC_EAST_TUNNEL_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_AGGRE_NOC_EAST_TUNNEL_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_AGGRE_NOC_EAST_TUNNEL_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_AGGRE_NOC_EAST_TUNNEL_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_AGGRE_NOC_EAST_TUNNEL_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_EAST_TUNNEL_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_EAST_TUNNEL_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_AGGRE_NOC_EAST_TUNNEL_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_AGGRE_NOC_EAST_TUNNEL_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_EAST_TUNNEL_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_AGGRE_NOC_SOUTH_HS_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00072050) +#define HWIO_GCC_AGGRE_NOC_SOUTH_HS_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00072050) +#define HWIO_GCC_AGGRE_NOC_SOUTH_HS_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00072050) +#define HWIO_GCC_AGGRE_NOC_SOUTH_HS_AXI_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_AGGRE_NOC_SOUTH_HS_AXI_CBCR_ATTR 0x3 +#define HWIO_GCC_AGGRE_NOC_SOUTH_HS_AXI_CBCR_IN \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_SOUTH_HS_AXI_CBCR_ADDR, HWIO_GCC_AGGRE_NOC_SOUTH_HS_AXI_CBCR_RMSK) +#define HWIO_GCC_AGGRE_NOC_SOUTH_HS_AXI_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_SOUTH_HS_AXI_CBCR_ADDR, m) +#define HWIO_GCC_AGGRE_NOC_SOUTH_HS_AXI_CBCR_OUT(v) \ + out_dword(HWIO_GCC_AGGRE_NOC_SOUTH_HS_AXI_CBCR_ADDR,v) +#define HWIO_GCC_AGGRE_NOC_SOUTH_HS_AXI_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_SOUTH_HS_AXI_CBCR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_SOUTH_HS_AXI_CBCR_IN) +#define HWIO_GCC_AGGRE_NOC_SOUTH_HS_AXI_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_AGGRE_NOC_SOUTH_HS_AXI_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_AGGRE_NOC_SOUTH_HS_AXI_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_AGGRE_NOC_SOUTH_HS_AXI_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_AGGRE_NOC_SOUTH_HS_AXI_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_AGGRE_NOC_SOUTH_HS_AXI_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_AGGRE_NOC_SOUTH_HS_AXI_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_AGGRE_NOC_SOUTH_HS_AXI_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_AGGRE_NOC_SOUTH_HS_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_AGGRE_NOC_SOUTH_HS_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_AGGRE_NOC_SOUTH_HS_AXI_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_AGGRE_NOC_SOUTH_HS_AXI_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_AGGRE_NOC_SOUTH_HS_AXI_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_AGGRE_NOC_SOUTH_HS_AXI_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_AGGRE_NOC_SOUTH_HS_AXI_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_SOUTH_HS_AXI_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_SOUTH_HS_AXI_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_AGGRE_NOC_SOUTH_HS_AXI_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_AGGRE_NOC_SOUTH_HS_AXI_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_SOUTH_HS_AXI_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_SOUTH_HS_AXI_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_AGGRE_NOC_SOUTH_HS_AXI_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_AGGRE_NOC_SOUTH_HS_AXI_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_SOUTH_HS_AXI_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_AGGRE_NOC_SOUTH_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001313c) +#define HWIO_GCC_AGGRE_NOC_SOUTH_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001313c) +#define HWIO_GCC_AGGRE_NOC_SOUTH_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001313c) +#define HWIO_GCC_AGGRE_NOC_SOUTH_AXI_CBCR_RMSK 0x81d00004 +#define HWIO_GCC_AGGRE_NOC_SOUTH_AXI_CBCR_ATTR 0x3 +#define HWIO_GCC_AGGRE_NOC_SOUTH_AXI_CBCR_IN \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_SOUTH_AXI_CBCR_ADDR, HWIO_GCC_AGGRE_NOC_SOUTH_AXI_CBCR_RMSK) +#define HWIO_GCC_AGGRE_NOC_SOUTH_AXI_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_SOUTH_AXI_CBCR_ADDR, m) +#define HWIO_GCC_AGGRE_NOC_SOUTH_AXI_CBCR_OUT(v) \ + out_dword(HWIO_GCC_AGGRE_NOC_SOUTH_AXI_CBCR_ADDR,v) +#define HWIO_GCC_AGGRE_NOC_SOUTH_AXI_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_SOUTH_AXI_CBCR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_SOUTH_AXI_CBCR_IN) +#define HWIO_GCC_AGGRE_NOC_SOUTH_AXI_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_AGGRE_NOC_SOUTH_AXI_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_AGGRE_NOC_SOUTH_AXI_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_AGGRE_NOC_SOUTH_AXI_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_AGGRE_NOC_SOUTH_AXI_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_AGGRE_NOC_SOUTH_AXI_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_AGGRE_NOC_SOUTH_AXI_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_AGGRE_NOC_SOUTH_AXI_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_AGGRE_NOC_SOUTH_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_AGGRE_NOC_SOUTH_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_AGGRE_NOC_SOUTH_AXI_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_AGGRE_NOC_SOUTH_AXI_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_AGGRE_NOC_SOUTH_AXI_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_SOUTH_AXI_CBCR_CLK_ARES_RESET_FVAL 0x1 + +#define HWIO_GCC_AGGRE_NOC_SOUTH_TUNNEL_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00072054) +#define HWIO_GCC_AGGRE_NOC_SOUTH_TUNNEL_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00072054) +#define HWIO_GCC_AGGRE_NOC_SOUTH_TUNNEL_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00072054) +#define HWIO_GCC_AGGRE_NOC_SOUTH_TUNNEL_CBCR_RMSK 0x81d00005 +#define HWIO_GCC_AGGRE_NOC_SOUTH_TUNNEL_CBCR_ATTR 0x3 +#define HWIO_GCC_AGGRE_NOC_SOUTH_TUNNEL_CBCR_IN \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_SOUTH_TUNNEL_CBCR_ADDR, HWIO_GCC_AGGRE_NOC_SOUTH_TUNNEL_CBCR_RMSK) +#define HWIO_GCC_AGGRE_NOC_SOUTH_TUNNEL_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_SOUTH_TUNNEL_CBCR_ADDR, m) +#define HWIO_GCC_AGGRE_NOC_SOUTH_TUNNEL_CBCR_OUT(v) \ + out_dword(HWIO_GCC_AGGRE_NOC_SOUTH_TUNNEL_CBCR_ADDR,v) +#define HWIO_GCC_AGGRE_NOC_SOUTH_TUNNEL_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_SOUTH_TUNNEL_CBCR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_SOUTH_TUNNEL_CBCR_IN) +#define HWIO_GCC_AGGRE_NOC_SOUTH_TUNNEL_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_AGGRE_NOC_SOUTH_TUNNEL_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_AGGRE_NOC_SOUTH_TUNNEL_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_AGGRE_NOC_SOUTH_TUNNEL_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_AGGRE_NOC_SOUTH_TUNNEL_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_AGGRE_NOC_SOUTH_TUNNEL_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_AGGRE_NOC_SOUTH_TUNNEL_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_AGGRE_NOC_SOUTH_TUNNEL_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_AGGRE_NOC_SOUTH_TUNNEL_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_AGGRE_NOC_SOUTH_TUNNEL_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_AGGRE_NOC_SOUTH_TUNNEL_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_AGGRE_NOC_SOUTH_TUNNEL_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_AGGRE_NOC_SOUTH_TUNNEL_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_SOUTH_TUNNEL_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_SOUTH_TUNNEL_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_AGGRE_NOC_SOUTH_TUNNEL_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_AGGRE_NOC_SOUTH_TUNNEL_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_SOUTH_TUNNEL_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00072058) +#define HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00072058) +#define HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00072058) +#define HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_ATTR 0x3 +#define HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_IN \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_ADDR, HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_RMSK) +#define HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_ADDR, m) +#define HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_OUT(v) \ + out_dword(HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_ADDR,v) +#define HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_IN) +#define HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_AGGRE_NOC_NORTH_TUNNEL_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007205c) +#define HWIO_GCC_AGGRE_NOC_NORTH_TUNNEL_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007205c) +#define HWIO_GCC_AGGRE_NOC_NORTH_TUNNEL_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007205c) +#define HWIO_GCC_AGGRE_NOC_NORTH_TUNNEL_CBCR_RMSK 0x81d00005 +#define HWIO_GCC_AGGRE_NOC_NORTH_TUNNEL_CBCR_ATTR 0x3 +#define HWIO_GCC_AGGRE_NOC_NORTH_TUNNEL_CBCR_IN \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_NORTH_TUNNEL_CBCR_ADDR, HWIO_GCC_AGGRE_NOC_NORTH_TUNNEL_CBCR_RMSK) +#define HWIO_GCC_AGGRE_NOC_NORTH_TUNNEL_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_NORTH_TUNNEL_CBCR_ADDR, m) +#define HWIO_GCC_AGGRE_NOC_NORTH_TUNNEL_CBCR_OUT(v) \ + out_dword(HWIO_GCC_AGGRE_NOC_NORTH_TUNNEL_CBCR_ADDR,v) +#define HWIO_GCC_AGGRE_NOC_NORTH_TUNNEL_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_NORTH_TUNNEL_CBCR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_NORTH_TUNNEL_CBCR_IN) +#define HWIO_GCC_AGGRE_NOC_NORTH_TUNNEL_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_AGGRE_NOC_NORTH_TUNNEL_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_AGGRE_NOC_NORTH_TUNNEL_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_AGGRE_NOC_NORTH_TUNNEL_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_AGGRE_NOC_NORTH_TUNNEL_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_AGGRE_NOC_NORTH_TUNNEL_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_AGGRE_NOC_NORTH_TUNNEL_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_AGGRE_NOC_NORTH_TUNNEL_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_AGGRE_NOC_NORTH_TUNNEL_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_AGGRE_NOC_NORTH_TUNNEL_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_AGGRE_NOC_NORTH_TUNNEL_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_AGGRE_NOC_NORTH_TUNNEL_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_AGGRE_NOC_NORTH_TUNNEL_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_NORTH_TUNNEL_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_NORTH_TUNNEL_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_AGGRE_NOC_NORTH_TUNNEL_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_AGGRE_NOC_NORTH_TUNNEL_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_NORTH_TUNNEL_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000003c) +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000003c) +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000003c) +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CBCR_RMSK 0x81f0700e +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CBCR_ATTR 0x3 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CBCR_IN \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_PCIE_AXI_CBCR_ADDR, HWIO_GCC_AGGRE_NOC_PCIE_AXI_CBCR_RMSK) +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_PCIE_AXI_CBCR_ADDR, m) +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CBCR_OUT(v) \ + out_dword(HWIO_GCC_AGGRE_NOC_PCIE_AXI_CBCR_ADDR,v) +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_PCIE_AXI_CBCR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_PCIE_AXI_CBCR_IN) +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CBCR_IGNORE_PMU_CLK_DIS_BMSK 0x200000 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CBCR_IGNORE_PMU_CLK_DIS_SHFT 0x15 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CBCR_HW_CTL_ENABLE_FVAL 0x1 + +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000040) +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000040) +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000040) +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_RMSK 0xf1ffffe +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_ATTR 0x3 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_IN \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_ADDR, HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_RMSK) +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_ADDR, m) +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_OUT(v) \ + out_dword(HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_ADDR,v) +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_IN) +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xf000000 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_PWR_FSM_CLK_SEL_BMSK 0x100000 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_PWR_FSM_CLK_SEL_SHFT 0x14 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xf0000 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CFG_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000044) +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CFG_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000044) +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CFG_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000044) +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CFG_SREGR_RMSK 0xffffffff +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CFG_SREGR_ATTR 0x3 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CFG_SREGR_IN \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_PCIE_AXI_CFG_SREGR_ADDR, HWIO_GCC_AGGRE_NOC_PCIE_AXI_CFG_SREGR_RMSK) +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CFG_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_PCIE_AXI_CFG_SREGR_ADDR, m) +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CFG_SREGR_OUT(v) \ + out_dword(HWIO_GCC_AGGRE_NOC_PCIE_AXI_CFG_SREGR_ADDR,v) +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CFG_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_PCIE_AXI_CFG_SREGR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_PCIE_AXI_CFG_SREGR_IN) +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CFG_SREGR_MEM_CORE_OFF_TIMER_BMSK 0xfc000000 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CFG_SREGR_MEM_CORE_OFF_TIMER_SHFT 0x1a +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_BMSK 0x2000000 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_SHFT 0x19 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_BMSK 0x1000000 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_SHFT 0x18 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CFG_SREGR_MEM_PERIPH_ON_STATUS_BMSK 0x800000 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CFG_SREGR_MEM_PERIPH_ON_STATUS_SHFT 0x17 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CFG_SREGR_MEM_CORE_ON_STATUS_BMSK 0x400000 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CFG_SREGR_MEM_CORE_ON_STATUS_SHFT 0x16 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CFG_SREGR_MEM_CPH_TIMER_BMSK 0x3f0000 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CFG_SREGR_MEM_CPH_TIMER_SHFT 0x10 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CFG_SREGR_SLEEP_TIMER_BMSK 0xff00 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CFG_SREGR_SLEEP_TIMER_SHFT 0x8 +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CFG_SREGR_WAKEUP_TIMER_BMSK 0xff +#define HWIO_GCC_AGGRE_NOC_PCIE_AXI_CFG_SREGR_WAKEUP_TIMER_SHFT 0x0 + +#define HWIO_GCC_AGGRE_USB3_PRIM_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002908c) +#define HWIO_GCC_AGGRE_USB3_PRIM_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002908c) +#define HWIO_GCC_AGGRE_USB3_PRIM_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002908c) +#define HWIO_GCC_AGGRE_USB3_PRIM_AXI_CBCR_RMSK 0x81c0000f +#define HWIO_GCC_AGGRE_USB3_PRIM_AXI_CBCR_ATTR 0x3 +#define HWIO_GCC_AGGRE_USB3_PRIM_AXI_CBCR_IN \ + in_dword_masked(HWIO_GCC_AGGRE_USB3_PRIM_AXI_CBCR_ADDR, HWIO_GCC_AGGRE_USB3_PRIM_AXI_CBCR_RMSK) +#define HWIO_GCC_AGGRE_USB3_PRIM_AXI_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_AGGRE_USB3_PRIM_AXI_CBCR_ADDR, m) +#define HWIO_GCC_AGGRE_USB3_PRIM_AXI_CBCR_OUT(v) \ + out_dword(HWIO_GCC_AGGRE_USB3_PRIM_AXI_CBCR_ADDR,v) +#define HWIO_GCC_AGGRE_USB3_PRIM_AXI_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AGGRE_USB3_PRIM_AXI_CBCR_ADDR,m,v,HWIO_GCC_AGGRE_USB3_PRIM_AXI_CBCR_IN) +#define HWIO_GCC_AGGRE_USB3_PRIM_AXI_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_AGGRE_USB3_PRIM_AXI_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_AGGRE_USB3_PRIM_AXI_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_AGGRE_USB3_PRIM_AXI_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_AGGRE_USB3_PRIM_AXI_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_AGGRE_USB3_PRIM_AXI_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_AGGRE_USB3_PRIM_AXI_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_AGGRE_USB3_PRIM_AXI_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_AGGRE_USB3_PRIM_AXI_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_AGGRE_USB3_PRIM_AXI_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_AGGRE_USB3_PRIM_AXI_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_AGGRE_USB3_PRIM_AXI_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_AGGRE_USB3_PRIM_AXI_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_AGGRE_USB3_PRIM_AXI_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_AGGRE_USB3_PRIM_AXI_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_AGGRE_USB3_PRIM_AXI_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_AGGRE_USB3_PRIM_AXI_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_USB3_PRIM_AXI_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_AGGRE_USB3_PRIM_AXI_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_AGGRE_USB3_PRIM_AXI_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_AGGRE_USB3_PRIM_AXI_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_USB3_PRIM_AXI_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_AGGRE_UFS_PHY_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000670e4) +#define HWIO_GCC_AGGRE_UFS_PHY_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000670e4) +#define HWIO_GCC_AGGRE_UFS_PHY_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000670e4) +#define HWIO_GCC_AGGRE_UFS_PHY_AXI_CBCR_RMSK 0x81c0000f +#define HWIO_GCC_AGGRE_UFS_PHY_AXI_CBCR_ATTR 0x3 +#define HWIO_GCC_AGGRE_UFS_PHY_AXI_CBCR_IN \ + in_dword_masked(HWIO_GCC_AGGRE_UFS_PHY_AXI_CBCR_ADDR, HWIO_GCC_AGGRE_UFS_PHY_AXI_CBCR_RMSK) +#define HWIO_GCC_AGGRE_UFS_PHY_AXI_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_AGGRE_UFS_PHY_AXI_CBCR_ADDR, m) +#define HWIO_GCC_AGGRE_UFS_PHY_AXI_CBCR_OUT(v) \ + out_dword(HWIO_GCC_AGGRE_UFS_PHY_AXI_CBCR_ADDR,v) +#define HWIO_GCC_AGGRE_UFS_PHY_AXI_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AGGRE_UFS_PHY_AXI_CBCR_ADDR,m,v,HWIO_GCC_AGGRE_UFS_PHY_AXI_CBCR_IN) +#define HWIO_GCC_AGGRE_UFS_PHY_AXI_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_AGGRE_UFS_PHY_AXI_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_AGGRE_UFS_PHY_AXI_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_AGGRE_UFS_PHY_AXI_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_AGGRE_UFS_PHY_AXI_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_AGGRE_UFS_PHY_AXI_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_AGGRE_UFS_PHY_AXI_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_AGGRE_UFS_PHY_AXI_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_AGGRE_UFS_PHY_AXI_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_AGGRE_UFS_PHY_AXI_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_AGGRE_UFS_PHY_AXI_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_AGGRE_UFS_PHY_AXI_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_AGGRE_UFS_PHY_AXI_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_AGGRE_UFS_PHY_AXI_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_AGGRE_UFS_PHY_AXI_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_AGGRE_UFS_PHY_AXI_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_AGGRE_UFS_PHY_AXI_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_UFS_PHY_AXI_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_AGGRE_UFS_PHY_AXI_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_AGGRE_UFS_PHY_AXI_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_AGGRE_UFS_PHY_AXI_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_UFS_PHY_AXI_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_AGGRE_NOC_IPA_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00079174) +#define HWIO_GCC_AGGRE_NOC_IPA_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00079174) +#define HWIO_GCC_AGGRE_NOC_IPA_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00079174) +#define HWIO_GCC_AGGRE_NOC_IPA_CBCR_RMSK 0x81d00005 +#define HWIO_GCC_AGGRE_NOC_IPA_CBCR_ATTR 0x3 +#define HWIO_GCC_AGGRE_NOC_IPA_CBCR_IN \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_IPA_CBCR_ADDR, HWIO_GCC_AGGRE_NOC_IPA_CBCR_RMSK) +#define HWIO_GCC_AGGRE_NOC_IPA_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_IPA_CBCR_ADDR, m) +#define HWIO_GCC_AGGRE_NOC_IPA_CBCR_OUT(v) \ + out_dword(HWIO_GCC_AGGRE_NOC_IPA_CBCR_ADDR,v) +#define HWIO_GCC_AGGRE_NOC_IPA_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_IPA_CBCR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_IPA_CBCR_IN) +#define HWIO_GCC_AGGRE_NOC_IPA_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_AGGRE_NOC_IPA_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_AGGRE_NOC_IPA_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_AGGRE_NOC_IPA_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_AGGRE_NOC_IPA_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_AGGRE_NOC_IPA_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_AGGRE_NOC_IPA_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_AGGRE_NOC_IPA_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_AGGRE_NOC_IPA_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_AGGRE_NOC_IPA_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_AGGRE_NOC_IPA_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_AGGRE_NOC_IPA_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_AGGRE_NOC_IPA_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_IPA_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_IPA_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_AGGRE_NOC_IPA_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_AGGRE_NOC_IPA_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_IPA_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_ANOC_PCIE_PWRCTL_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000002c) +#define HWIO_GCC_ANOC_PCIE_PWRCTL_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000002c) +#define HWIO_GCC_ANOC_PCIE_PWRCTL_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000002c) +#define HWIO_GCC_ANOC_PCIE_PWRCTL_CBCR_RMSK 0x81d0000e +#define HWIO_GCC_ANOC_PCIE_PWRCTL_CBCR_ATTR 0x3 +#define HWIO_GCC_ANOC_PCIE_PWRCTL_CBCR_IN \ + in_dword_masked(HWIO_GCC_ANOC_PCIE_PWRCTL_CBCR_ADDR, HWIO_GCC_ANOC_PCIE_PWRCTL_CBCR_RMSK) +#define HWIO_GCC_ANOC_PCIE_PWRCTL_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_ANOC_PCIE_PWRCTL_CBCR_ADDR, m) +#define HWIO_GCC_ANOC_PCIE_PWRCTL_CBCR_OUT(v) \ + out_dword(HWIO_GCC_ANOC_PCIE_PWRCTL_CBCR_ADDR,v) +#define HWIO_GCC_ANOC_PCIE_PWRCTL_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ANOC_PCIE_PWRCTL_CBCR_ADDR,m,v,HWIO_GCC_ANOC_PCIE_PWRCTL_CBCR_IN) +#define HWIO_GCC_ANOC_PCIE_PWRCTL_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_ANOC_PCIE_PWRCTL_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_ANOC_PCIE_PWRCTL_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_ANOC_PCIE_PWRCTL_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_ANOC_PCIE_PWRCTL_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_ANOC_PCIE_PWRCTL_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_ANOC_PCIE_PWRCTL_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_ANOC_PCIE_PWRCTL_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_ANOC_PCIE_PWRCTL_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_ANOC_PCIE_PWRCTL_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_ANOC_PCIE_PWRCTL_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_ANOC_PCIE_PWRCTL_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_ANOC_PCIE_PWRCTL_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_ANOC_PCIE_PWRCTL_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_ANOC_PCIE_PWRCTL_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_ANOC_PCIE_PWRCTL_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_ANOC_PCIE_PWRCTL_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_ANOC_PCIE_PWRCTL_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_ANOC_PCIE_PWRCTL_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_ANOC_PCIE_PWRCTL_CBCR_HW_CTL_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007207c) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007207c) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007207c) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00072080) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00072080) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00072080) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00072084) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00072084) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00072084) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00072088) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00072088) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00072088) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007208c) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007208c) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007208c) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00072090) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00072090) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00072090) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00072094) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00072094) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00072094) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00072098) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00072098) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00072098) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007209c) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007209c) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007209c) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000720a0) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000720a0) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000720a0) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000720a4) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000720a4) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000720a4) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000720a8) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000720a8) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000720a8) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000720ac) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000720ac) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000720ac) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000720b0) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000720b0) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000720b0) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000720b4) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000720b4) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000720b4) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000720b8) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000720b8) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000720b8) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_AGGRE_NOC_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00072060) +#define HWIO_GCC_AGGRE_NOC_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00072060) +#define HWIO_GCC_AGGRE_NOC_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00072060) +#define HWIO_GCC_AGGRE_NOC_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_AGGRE_NOC_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_AGGRE_NOC_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_CMD_RCGR_ADDR, HWIO_GCC_AGGRE_NOC_CMD_RCGR_RMSK) +#define HWIO_GCC_AGGRE_NOC_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_CMD_RCGR_ADDR, m) +#define HWIO_GCC_AGGRE_NOC_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_AGGRE_NOC_CMD_RCGR_ADDR,v) +#define HWIO_GCC_AGGRE_NOC_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_CMD_RCGR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_CMD_RCGR_IN) +#define HWIO_GCC_AGGRE_NOC_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_AGGRE_NOC_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_AGGRE_NOC_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_AGGRE_NOC_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_AGGRE_NOC_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_AGGRE_NOC_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_AGGRE_NOC_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_AGGRE_NOC_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_AGGRE_NOC_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00072064) +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00072064) +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00072064) +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_CFG_RCGR_ADDR, HWIO_GCC_AGGRE_NOC_CFG_RCGR_RMSK) +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_CFG_RCGR_ADDR, m) +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_AGGRE_NOC_CFG_RCGR_ADDR,v) +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_CFG_RCGR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_CFG_RCGR_IN) +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000721a8) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000721a8) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000721a8) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000721ac) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000721ac) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000721ac) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000721b0) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000721b0) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000721b0) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000721b4) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000721b4) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000721b4) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000721b8) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000721b8) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000721b8) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000721bc) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000721bc) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000721bc) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000721c0) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000721c0) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000721c0) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000721c4) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000721c4) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000721c4) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000721c8) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000721c8) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000721c8) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000721cc) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000721cc) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000721cc) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000721d0) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000721d0) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000721d0) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000721d4) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000721d4) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000721d4) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000721d8) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000721d8) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000721d8) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000721dc) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000721dc) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000721dc) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000721e0) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000721e0) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000721e0) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000721e4) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000721e4) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000721e4) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007218c) +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007218c) +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007218c) +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_NORTH_SF_CMD_RCGR_ADDR, HWIO_GCC_AGGRE_NOC_NORTH_SF_CMD_RCGR_RMSK) +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_NORTH_SF_CMD_RCGR_ADDR, m) +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_AGGRE_NOC_NORTH_SF_CMD_RCGR_ADDR,v) +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_NORTH_SF_CMD_RCGR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_NORTH_SF_CMD_RCGR_IN) +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00072190) +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00072190) +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00072190) +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_ADDR, HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_RMSK) +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_ADDR, m) +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_ADDR,v) +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_IN) +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_AGGRE_NOC_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000722b8) +#define HWIO_GCC_AGGRE_NOC_DCD_CDIV_DCDR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000722b8) +#define HWIO_GCC_AGGRE_NOC_DCD_CDIV_DCDR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000722b8) +#define HWIO_GCC_AGGRE_NOC_DCD_CDIV_DCDR_RMSK 0x1 +#define HWIO_GCC_AGGRE_NOC_DCD_CDIV_DCDR_ATTR 0x3 +#define HWIO_GCC_AGGRE_NOC_DCD_CDIV_DCDR_IN \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_DCD_CDIV_DCDR_ADDR, HWIO_GCC_AGGRE_NOC_DCD_CDIV_DCDR_RMSK) +#define HWIO_GCC_AGGRE_NOC_DCD_CDIV_DCDR_INM(m) \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_DCD_CDIV_DCDR_ADDR, m) +#define HWIO_GCC_AGGRE_NOC_DCD_CDIV_DCDR_OUT(v) \ + out_dword(HWIO_GCC_AGGRE_NOC_DCD_CDIV_DCDR_ADDR,v) +#define HWIO_GCC_AGGRE_NOC_DCD_CDIV_DCDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_DCD_CDIV_DCDR_IN) +#define HWIO_GCC_AGGRE_NOC_DCD_CDIV_DCDR_DCD_ENABLE_BMSK 0x1 +#define HWIO_GCC_AGGRE_NOC_DCD_CDIV_DCDR_DCD_ENABLE_SHFT 0x0 +#define HWIO_GCC_AGGRE_NOC_DCD_CDIV_DCDR_DCD_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_DCD_CDIV_DCDR_DCD_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_AGGRE_NOC_WEST_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000722bc) +#define HWIO_GCC_AGGRE_NOC_WEST_DCD_CDIV_DCDR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000722bc) +#define HWIO_GCC_AGGRE_NOC_WEST_DCD_CDIV_DCDR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000722bc) +#define HWIO_GCC_AGGRE_NOC_WEST_DCD_CDIV_DCDR_RMSK 0x1 +#define HWIO_GCC_AGGRE_NOC_WEST_DCD_CDIV_DCDR_ATTR 0x3 +#define HWIO_GCC_AGGRE_NOC_WEST_DCD_CDIV_DCDR_IN \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_WEST_DCD_CDIV_DCDR_ADDR, HWIO_GCC_AGGRE_NOC_WEST_DCD_CDIV_DCDR_RMSK) +#define HWIO_GCC_AGGRE_NOC_WEST_DCD_CDIV_DCDR_INM(m) \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_WEST_DCD_CDIV_DCDR_ADDR, m) +#define HWIO_GCC_AGGRE_NOC_WEST_DCD_CDIV_DCDR_OUT(v) \ + out_dword(HWIO_GCC_AGGRE_NOC_WEST_DCD_CDIV_DCDR_ADDR,v) +#define HWIO_GCC_AGGRE_NOC_WEST_DCD_CDIV_DCDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_WEST_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_WEST_DCD_CDIV_DCDR_IN) +#define HWIO_GCC_AGGRE_NOC_WEST_DCD_CDIV_DCDR_DCD_ENABLE_BMSK 0x1 +#define HWIO_GCC_AGGRE_NOC_WEST_DCD_CDIV_DCDR_DCD_ENABLE_SHFT 0x0 +#define HWIO_GCC_AGGRE_NOC_WEST_DCD_CDIV_DCDR_DCD_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_WEST_DCD_CDIV_DCDR_DCD_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_AGGRE_NOC_EAST_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000722c0) +#define HWIO_GCC_AGGRE_NOC_EAST_DCD_CDIV_DCDR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000722c0) +#define HWIO_GCC_AGGRE_NOC_EAST_DCD_CDIV_DCDR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000722c0) +#define HWIO_GCC_AGGRE_NOC_EAST_DCD_CDIV_DCDR_RMSK 0x1 +#define HWIO_GCC_AGGRE_NOC_EAST_DCD_CDIV_DCDR_ATTR 0x3 +#define HWIO_GCC_AGGRE_NOC_EAST_DCD_CDIV_DCDR_IN \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_EAST_DCD_CDIV_DCDR_ADDR, HWIO_GCC_AGGRE_NOC_EAST_DCD_CDIV_DCDR_RMSK) +#define HWIO_GCC_AGGRE_NOC_EAST_DCD_CDIV_DCDR_INM(m) \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_EAST_DCD_CDIV_DCDR_ADDR, m) +#define HWIO_GCC_AGGRE_NOC_EAST_DCD_CDIV_DCDR_OUT(v) \ + out_dword(HWIO_GCC_AGGRE_NOC_EAST_DCD_CDIV_DCDR_ADDR,v) +#define HWIO_GCC_AGGRE_NOC_EAST_DCD_CDIV_DCDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_EAST_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_EAST_DCD_CDIV_DCDR_IN) +#define HWIO_GCC_AGGRE_NOC_EAST_DCD_CDIV_DCDR_DCD_ENABLE_BMSK 0x1 +#define HWIO_GCC_AGGRE_NOC_EAST_DCD_CDIV_DCDR_DCD_ENABLE_SHFT 0x0 +#define HWIO_GCC_AGGRE_NOC_EAST_DCD_CDIV_DCDR_DCD_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_EAST_DCD_CDIV_DCDR_DCD_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_AGGRE_NOC_NORTH_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000722c4) +#define HWIO_GCC_AGGRE_NOC_NORTH_DCD_CDIV_DCDR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000722c4) +#define HWIO_GCC_AGGRE_NOC_NORTH_DCD_CDIV_DCDR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000722c4) +#define HWIO_GCC_AGGRE_NOC_NORTH_DCD_CDIV_DCDR_RMSK 0x1 +#define HWIO_GCC_AGGRE_NOC_NORTH_DCD_CDIV_DCDR_ATTR 0x3 +#define HWIO_GCC_AGGRE_NOC_NORTH_DCD_CDIV_DCDR_IN \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_NORTH_DCD_CDIV_DCDR_ADDR, HWIO_GCC_AGGRE_NOC_NORTH_DCD_CDIV_DCDR_RMSK) +#define HWIO_GCC_AGGRE_NOC_NORTH_DCD_CDIV_DCDR_INM(m) \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_NORTH_DCD_CDIV_DCDR_ADDR, m) +#define HWIO_GCC_AGGRE_NOC_NORTH_DCD_CDIV_DCDR_OUT(v) \ + out_dword(HWIO_GCC_AGGRE_NOC_NORTH_DCD_CDIV_DCDR_ADDR,v) +#define HWIO_GCC_AGGRE_NOC_NORTH_DCD_CDIV_DCDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_NORTH_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_NORTH_DCD_CDIV_DCDR_IN) +#define HWIO_GCC_AGGRE_NOC_NORTH_DCD_CDIV_DCDR_DCD_ENABLE_BMSK 0x1 +#define HWIO_GCC_AGGRE_NOC_NORTH_DCD_CDIV_DCDR_DCD_ENABLE_SHFT 0x0 +#define HWIO_GCC_AGGRE_NOC_NORTH_DCD_CDIV_DCDR_DCD_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_NORTH_DCD_CDIV_DCDR_DCD_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_AGGRE_NOC_SOUTH_HS_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000722c8) +#define HWIO_GCC_AGGRE_NOC_SOUTH_HS_DCD_CDIV_DCDR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000722c8) +#define HWIO_GCC_AGGRE_NOC_SOUTH_HS_DCD_CDIV_DCDR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000722c8) +#define HWIO_GCC_AGGRE_NOC_SOUTH_HS_DCD_CDIV_DCDR_RMSK 0x1 +#define HWIO_GCC_AGGRE_NOC_SOUTH_HS_DCD_CDIV_DCDR_ATTR 0x3 +#define HWIO_GCC_AGGRE_NOC_SOUTH_HS_DCD_CDIV_DCDR_IN \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_SOUTH_HS_DCD_CDIV_DCDR_ADDR, HWIO_GCC_AGGRE_NOC_SOUTH_HS_DCD_CDIV_DCDR_RMSK) +#define HWIO_GCC_AGGRE_NOC_SOUTH_HS_DCD_CDIV_DCDR_INM(m) \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_SOUTH_HS_DCD_CDIV_DCDR_ADDR, m) +#define HWIO_GCC_AGGRE_NOC_SOUTH_HS_DCD_CDIV_DCDR_OUT(v) \ + out_dword(HWIO_GCC_AGGRE_NOC_SOUTH_HS_DCD_CDIV_DCDR_ADDR,v) +#define HWIO_GCC_AGGRE_NOC_SOUTH_HS_DCD_CDIV_DCDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_SOUTH_HS_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_SOUTH_HS_DCD_CDIV_DCDR_IN) +#define HWIO_GCC_AGGRE_NOC_SOUTH_HS_DCD_CDIV_DCDR_DCD_ENABLE_BMSK 0x1 +#define HWIO_GCC_AGGRE_NOC_SOUTH_HS_DCD_CDIV_DCDR_DCD_ENABLE_SHFT 0x0 +#define HWIO_GCC_AGGRE_NOC_SOUTH_HS_DCD_CDIV_DCDR_DCD_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_SOUTH_HS_DCD_CDIV_DCDR_DCD_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_AGGRE_NOC_SOUTH_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000722cc) +#define HWIO_GCC_AGGRE_NOC_SOUTH_DCD_CDIV_DCDR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000722cc) +#define HWIO_GCC_AGGRE_NOC_SOUTH_DCD_CDIV_DCDR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000722cc) +#define HWIO_GCC_AGGRE_NOC_SOUTH_DCD_CDIV_DCDR_RMSK 0x1 +#define HWIO_GCC_AGGRE_NOC_SOUTH_DCD_CDIV_DCDR_ATTR 0x3 +#define HWIO_GCC_AGGRE_NOC_SOUTH_DCD_CDIV_DCDR_IN \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_SOUTH_DCD_CDIV_DCDR_ADDR, HWIO_GCC_AGGRE_NOC_SOUTH_DCD_CDIV_DCDR_RMSK) +#define HWIO_GCC_AGGRE_NOC_SOUTH_DCD_CDIV_DCDR_INM(m) \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_SOUTH_DCD_CDIV_DCDR_ADDR, m) +#define HWIO_GCC_AGGRE_NOC_SOUTH_DCD_CDIV_DCDR_OUT(v) \ + out_dword(HWIO_GCC_AGGRE_NOC_SOUTH_DCD_CDIV_DCDR_ADDR,v) +#define HWIO_GCC_AGGRE_NOC_SOUTH_DCD_CDIV_DCDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_SOUTH_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_SOUTH_DCD_CDIV_DCDR_IN) +#define HWIO_GCC_AGGRE_NOC_SOUTH_DCD_CDIV_DCDR_DCD_ENABLE_BMSK 0x1 +#define HWIO_GCC_AGGRE_NOC_SOUTH_DCD_CDIV_DCDR_DCD_ENABLE_SHFT 0x0 +#define HWIO_GCC_AGGRE_NOC_SOUTH_DCD_CDIV_DCDR_DCD_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_SOUTH_DCD_CDIV_DCDR_DCD_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_AGGRE_NOC_WEST_TUNNEL_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000722d0) +#define HWIO_GCC_AGGRE_NOC_WEST_TUNNEL_DCD_CDIV_DCDR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000722d0) +#define HWIO_GCC_AGGRE_NOC_WEST_TUNNEL_DCD_CDIV_DCDR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000722d0) +#define HWIO_GCC_AGGRE_NOC_WEST_TUNNEL_DCD_CDIV_DCDR_RMSK 0x1 +#define HWIO_GCC_AGGRE_NOC_WEST_TUNNEL_DCD_CDIV_DCDR_ATTR 0x3 +#define HWIO_GCC_AGGRE_NOC_WEST_TUNNEL_DCD_CDIV_DCDR_IN \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_WEST_TUNNEL_DCD_CDIV_DCDR_ADDR, HWIO_GCC_AGGRE_NOC_WEST_TUNNEL_DCD_CDIV_DCDR_RMSK) +#define HWIO_GCC_AGGRE_NOC_WEST_TUNNEL_DCD_CDIV_DCDR_INM(m) \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_WEST_TUNNEL_DCD_CDIV_DCDR_ADDR, m) +#define HWIO_GCC_AGGRE_NOC_WEST_TUNNEL_DCD_CDIV_DCDR_OUT(v) \ + out_dword(HWIO_GCC_AGGRE_NOC_WEST_TUNNEL_DCD_CDIV_DCDR_ADDR,v) +#define HWIO_GCC_AGGRE_NOC_WEST_TUNNEL_DCD_CDIV_DCDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_WEST_TUNNEL_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_WEST_TUNNEL_DCD_CDIV_DCDR_IN) +#define HWIO_GCC_AGGRE_NOC_WEST_TUNNEL_DCD_CDIV_DCDR_DCD_ENABLE_BMSK 0x1 +#define HWIO_GCC_AGGRE_NOC_WEST_TUNNEL_DCD_CDIV_DCDR_DCD_ENABLE_SHFT 0x0 +#define HWIO_GCC_AGGRE_NOC_WEST_TUNNEL_DCD_CDIV_DCDR_DCD_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_WEST_TUNNEL_DCD_CDIV_DCDR_DCD_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_AGGRE_NOC_EAST_TUNNEL_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000722d4) +#define HWIO_GCC_AGGRE_NOC_EAST_TUNNEL_DCD_CDIV_DCDR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000722d4) +#define HWIO_GCC_AGGRE_NOC_EAST_TUNNEL_DCD_CDIV_DCDR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000722d4) +#define HWIO_GCC_AGGRE_NOC_EAST_TUNNEL_DCD_CDIV_DCDR_RMSK 0x1 +#define HWIO_GCC_AGGRE_NOC_EAST_TUNNEL_DCD_CDIV_DCDR_ATTR 0x3 +#define HWIO_GCC_AGGRE_NOC_EAST_TUNNEL_DCD_CDIV_DCDR_IN \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_EAST_TUNNEL_DCD_CDIV_DCDR_ADDR, HWIO_GCC_AGGRE_NOC_EAST_TUNNEL_DCD_CDIV_DCDR_RMSK) +#define HWIO_GCC_AGGRE_NOC_EAST_TUNNEL_DCD_CDIV_DCDR_INM(m) \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_EAST_TUNNEL_DCD_CDIV_DCDR_ADDR, m) +#define HWIO_GCC_AGGRE_NOC_EAST_TUNNEL_DCD_CDIV_DCDR_OUT(v) \ + out_dword(HWIO_GCC_AGGRE_NOC_EAST_TUNNEL_DCD_CDIV_DCDR_ADDR,v) +#define HWIO_GCC_AGGRE_NOC_EAST_TUNNEL_DCD_CDIV_DCDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_EAST_TUNNEL_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_EAST_TUNNEL_DCD_CDIV_DCDR_IN) +#define HWIO_GCC_AGGRE_NOC_EAST_TUNNEL_DCD_CDIV_DCDR_DCD_ENABLE_BMSK 0x1 +#define HWIO_GCC_AGGRE_NOC_EAST_TUNNEL_DCD_CDIV_DCDR_DCD_ENABLE_SHFT 0x0 +#define HWIO_GCC_AGGRE_NOC_EAST_TUNNEL_DCD_CDIV_DCDR_DCD_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_EAST_TUNNEL_DCD_CDIV_DCDR_DCD_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_AGGRE_NOC_NORTH_TUNNEL_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000722d8) +#define HWIO_GCC_AGGRE_NOC_NORTH_TUNNEL_DCD_CDIV_DCDR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000722d8) +#define HWIO_GCC_AGGRE_NOC_NORTH_TUNNEL_DCD_CDIV_DCDR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000722d8) +#define HWIO_GCC_AGGRE_NOC_NORTH_TUNNEL_DCD_CDIV_DCDR_RMSK 0x1 +#define HWIO_GCC_AGGRE_NOC_NORTH_TUNNEL_DCD_CDIV_DCDR_ATTR 0x3 +#define HWIO_GCC_AGGRE_NOC_NORTH_TUNNEL_DCD_CDIV_DCDR_IN \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_NORTH_TUNNEL_DCD_CDIV_DCDR_ADDR, HWIO_GCC_AGGRE_NOC_NORTH_TUNNEL_DCD_CDIV_DCDR_RMSK) +#define HWIO_GCC_AGGRE_NOC_NORTH_TUNNEL_DCD_CDIV_DCDR_INM(m) \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_NORTH_TUNNEL_DCD_CDIV_DCDR_ADDR, m) +#define HWIO_GCC_AGGRE_NOC_NORTH_TUNNEL_DCD_CDIV_DCDR_OUT(v) \ + out_dword(HWIO_GCC_AGGRE_NOC_NORTH_TUNNEL_DCD_CDIV_DCDR_ADDR,v) +#define HWIO_GCC_AGGRE_NOC_NORTH_TUNNEL_DCD_CDIV_DCDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_NORTH_TUNNEL_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_NORTH_TUNNEL_DCD_CDIV_DCDR_IN) +#define HWIO_GCC_AGGRE_NOC_NORTH_TUNNEL_DCD_CDIV_DCDR_DCD_ENABLE_BMSK 0x1 +#define HWIO_GCC_AGGRE_NOC_NORTH_TUNNEL_DCD_CDIV_DCDR_DCD_ENABLE_SHFT 0x0 +#define HWIO_GCC_AGGRE_NOC_NORTH_TUNNEL_DCD_CDIV_DCDR_DCD_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_NORTH_TUNNEL_DCD_CDIV_DCDR_DCD_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_AGGRE_NOC_SOUTH_TUNNEL_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000722dc) +#define HWIO_GCC_AGGRE_NOC_SOUTH_TUNNEL_DCD_CDIV_DCDR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000722dc) +#define HWIO_GCC_AGGRE_NOC_SOUTH_TUNNEL_DCD_CDIV_DCDR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000722dc) +#define HWIO_GCC_AGGRE_NOC_SOUTH_TUNNEL_DCD_CDIV_DCDR_RMSK 0x1 +#define HWIO_GCC_AGGRE_NOC_SOUTH_TUNNEL_DCD_CDIV_DCDR_ATTR 0x3 +#define HWIO_GCC_AGGRE_NOC_SOUTH_TUNNEL_DCD_CDIV_DCDR_IN \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_SOUTH_TUNNEL_DCD_CDIV_DCDR_ADDR, HWIO_GCC_AGGRE_NOC_SOUTH_TUNNEL_DCD_CDIV_DCDR_RMSK) +#define HWIO_GCC_AGGRE_NOC_SOUTH_TUNNEL_DCD_CDIV_DCDR_INM(m) \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_SOUTH_TUNNEL_DCD_CDIV_DCDR_ADDR, m) +#define HWIO_GCC_AGGRE_NOC_SOUTH_TUNNEL_DCD_CDIV_DCDR_OUT(v) \ + out_dword(HWIO_GCC_AGGRE_NOC_SOUTH_TUNNEL_DCD_CDIV_DCDR_ADDR,v) +#define HWIO_GCC_AGGRE_NOC_SOUTH_TUNNEL_DCD_CDIV_DCDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_SOUTH_TUNNEL_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_SOUTH_TUNNEL_DCD_CDIV_DCDR_IN) +#define HWIO_GCC_AGGRE_NOC_SOUTH_TUNNEL_DCD_CDIV_DCDR_DCD_ENABLE_BMSK 0x1 +#define HWIO_GCC_AGGRE_NOC_SOUTH_TUNNEL_DCD_CDIV_DCDR_DCD_ENABLE_SHFT 0x0 +#define HWIO_GCC_AGGRE_NOC_SOUTH_TUNNEL_DCD_CDIV_DCDR_DCD_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_SOUTH_TUNNEL_DCD_CDIV_DCDR_DCD_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000722e0) +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_DCD_CDIV_DCDR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000722e0) +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_DCD_CDIV_DCDR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000722e0) +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_DCD_CDIV_DCDR_RMSK 0x1 +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_DCD_CDIV_DCDR_ATTR 0x3 +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_DCD_CDIV_DCDR_IN \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_NORTH_SF_DCD_CDIV_DCDR_ADDR, HWIO_GCC_AGGRE_NOC_NORTH_SF_DCD_CDIV_DCDR_RMSK) +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_DCD_CDIV_DCDR_INM(m) \ + in_dword_masked(HWIO_GCC_AGGRE_NOC_NORTH_SF_DCD_CDIV_DCDR_ADDR, m) +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_DCD_CDIV_DCDR_OUT(v) \ + out_dword(HWIO_GCC_AGGRE_NOC_NORTH_SF_DCD_CDIV_DCDR_ADDR,v) +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_DCD_CDIV_DCDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_NORTH_SF_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_NORTH_SF_DCD_CDIV_DCDR_IN) +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_DCD_CDIV_DCDR_DCD_ENABLE_BMSK 0x1 +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_DCD_CDIV_DCDR_DCD_ENABLE_SHFT 0x0 +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_DCD_CDIV_DCDR_DCD_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_DCD_CDIV_DCDR_DCD_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TIC_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00011000) +#define HWIO_GCC_TIC_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00011000) +#define HWIO_GCC_TIC_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00011000) +#define HWIO_GCC_TIC_CBCR_RMSK 0x81c0000f +#define HWIO_GCC_TIC_CBCR_ATTR 0x3 +#define HWIO_GCC_TIC_CBCR_IN \ + in_dword_masked(HWIO_GCC_TIC_CBCR_ADDR, HWIO_GCC_TIC_CBCR_RMSK) +#define HWIO_GCC_TIC_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_TIC_CBCR_ADDR, m) +#define HWIO_GCC_TIC_CBCR_OUT(v) \ + out_dword(HWIO_GCC_TIC_CBCR_ADDR,v) +#define HWIO_GCC_TIC_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TIC_CBCR_ADDR,m,v,HWIO_GCC_TIC_CBCR_IN) +#define HWIO_GCC_TIC_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TIC_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TIC_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_TIC_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_TIC_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_TIC_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_TIC_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_TIC_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_TIC_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_TIC_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_TIC_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_TIC_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_TIC_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_TIC_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_TIC_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_TIC_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_TIC_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_TIC_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_TIC_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_TIC_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_TIC_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TIC_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TIC_CFG_QX_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00011004) +#define HWIO_GCC_TIC_CFG_QX_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00011004) +#define HWIO_GCC_TIC_CFG_QX_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00011004) +#define HWIO_GCC_TIC_CFG_QX_CBCR_RMSK 0x81d0700f +#define HWIO_GCC_TIC_CFG_QX_CBCR_ATTR 0x3 +#define HWIO_GCC_TIC_CFG_QX_CBCR_IN \ + in_dword_masked(HWIO_GCC_TIC_CFG_QX_CBCR_ADDR, HWIO_GCC_TIC_CFG_QX_CBCR_RMSK) +#define HWIO_GCC_TIC_CFG_QX_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_TIC_CFG_QX_CBCR_ADDR, m) +#define HWIO_GCC_TIC_CFG_QX_CBCR_OUT(v) \ + out_dword(HWIO_GCC_TIC_CFG_QX_CBCR_ADDR,v) +#define HWIO_GCC_TIC_CFG_QX_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TIC_CFG_QX_CBCR_ADDR,m,v,HWIO_GCC_TIC_CFG_QX_CBCR_IN) +#define HWIO_GCC_TIC_CFG_QX_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TIC_CFG_QX_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TIC_CFG_QX_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_TIC_CFG_QX_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_TIC_CFG_QX_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_TIC_CFG_QX_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_TIC_CFG_QX_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_TIC_CFG_QX_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_TIC_CFG_QX_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_TIC_CFG_QX_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_TIC_CFG_QX_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_TIC_CFG_QX_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_TIC_CFG_QX_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TIC_CFG_QX_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TIC_CFG_QX_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_TIC_CFG_QX_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_TIC_CFG_QX_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TIC_CFG_QX_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TIC_CFG_QX_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_TIC_CFG_QX_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_TIC_CFG_QX_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TIC_CFG_QX_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TIC_CFG_QX_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_TIC_CFG_QX_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_TIC_CFG_QX_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_TIC_CFG_QX_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_TIC_CFG_QX_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_TIC_CFG_QX_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_TIC_CFG_QX_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_TIC_CFG_QX_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_TIC_CFG_QX_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_TIC_CFG_QX_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_TIC_CFG_QX_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_TIC_CFG_QX_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_TIC_CFG_QX_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TIC_CFG_QX_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TIC_CFG_QX_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00011008) +#define HWIO_GCC_TIC_CFG_QX_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00011008) +#define HWIO_GCC_TIC_CFG_QX_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00011008) +#define HWIO_GCC_TIC_CFG_QX_SREGR_RMSK 0xf1ffffe +#define HWIO_GCC_TIC_CFG_QX_SREGR_ATTR 0x3 +#define HWIO_GCC_TIC_CFG_QX_SREGR_IN \ + in_dword_masked(HWIO_GCC_TIC_CFG_QX_SREGR_ADDR, HWIO_GCC_TIC_CFG_QX_SREGR_RMSK) +#define HWIO_GCC_TIC_CFG_QX_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_TIC_CFG_QX_SREGR_ADDR, m) +#define HWIO_GCC_TIC_CFG_QX_SREGR_OUT(v) \ + out_dword(HWIO_GCC_TIC_CFG_QX_SREGR_ADDR,v) +#define HWIO_GCC_TIC_CFG_QX_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TIC_CFG_QX_SREGR_ADDR,m,v,HWIO_GCC_TIC_CFG_QX_SREGR_IN) +#define HWIO_GCC_TIC_CFG_QX_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xf000000 +#define HWIO_GCC_TIC_CFG_QX_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_TIC_CFG_QX_SREGR_PWR_FSM_CLK_SEL_BMSK 0x100000 +#define HWIO_GCC_TIC_CFG_QX_SREGR_PWR_FSM_CLK_SEL_SHFT 0x14 +#define HWIO_GCC_TIC_CFG_QX_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xf0000 +#define HWIO_GCC_TIC_CFG_QX_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_TIC_CFG_QX_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_TIC_CFG_QX_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_TIC_CFG_QX_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_TIC_CFG_QX_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_TIC_CFG_QX_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_TIC_CFG_QX_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_TIC_CFG_QX_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_TIC_CFG_QX_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_TIC_CFG_QX_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_TIC_CFG_QX_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_TIC_CFG_QX_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_TIC_CFG_QX_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_TIC_CFG_QX_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_TIC_CFG_QX_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_TIC_CFG_QX_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_TIC_CFG_QX_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_TIC_CFG_QX_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_TIC_CFG_QX_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_TIC_CFG_QX_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_TIC_CFG_QX_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_TIC_CFG_QX_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_TIC_CFG_QX_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_TIC_CFG_QX_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_TIC_CFG_QX_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_TIC_CFG_QX_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_TIC_CFG_QX_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_TIC_CFG_QX_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_TIC_CFG_QX_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_TIC_CFG_QX_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TIC_CFG_QX_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TIC_CFG_QX_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_TIC_CFG_QX_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_TIC_CFG_QX_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_TIC_CFG_QX_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TIC_CFG_QX_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_TIC_CFG_QX_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_TIC_CFG_QX_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_TIC_CFG_QX_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_TIC_CFG_QX_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_TIC_CFG_QX_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_TIC_CFG_QX_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_TIC_CFG_QX_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_TIC_CFG_QX_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_TIC_CFG_QX_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_TIC_CFG_QX_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_TIC_CFG_QX_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_TIC_CFG_QX_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_TIC_CFG_QX_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_TIC_CFG_QX_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_TIC_CFG_QX_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_TIC_CFG_QX_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_TIC_CFG_QX_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_TIC_CFG_QX_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_TIC_CFG_QX_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TIC_CFG_QX_CFG_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001100c) +#define HWIO_GCC_TIC_CFG_QX_CFG_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001100c) +#define HWIO_GCC_TIC_CFG_QX_CFG_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001100c) +#define HWIO_GCC_TIC_CFG_QX_CFG_SREGR_RMSK 0xffffffff +#define HWIO_GCC_TIC_CFG_QX_CFG_SREGR_ATTR 0x3 +#define HWIO_GCC_TIC_CFG_QX_CFG_SREGR_IN \ + in_dword_masked(HWIO_GCC_TIC_CFG_QX_CFG_SREGR_ADDR, HWIO_GCC_TIC_CFG_QX_CFG_SREGR_RMSK) +#define HWIO_GCC_TIC_CFG_QX_CFG_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_TIC_CFG_QX_CFG_SREGR_ADDR, m) +#define HWIO_GCC_TIC_CFG_QX_CFG_SREGR_OUT(v) \ + out_dword(HWIO_GCC_TIC_CFG_QX_CFG_SREGR_ADDR,v) +#define HWIO_GCC_TIC_CFG_QX_CFG_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TIC_CFG_QX_CFG_SREGR_ADDR,m,v,HWIO_GCC_TIC_CFG_QX_CFG_SREGR_IN) +#define HWIO_GCC_TIC_CFG_QX_CFG_SREGR_MEM_CORE_OFF_TIMER_BMSK 0xfc000000 +#define HWIO_GCC_TIC_CFG_QX_CFG_SREGR_MEM_CORE_OFF_TIMER_SHFT 0x1a +#define HWIO_GCC_TIC_CFG_QX_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_BMSK 0x2000000 +#define HWIO_GCC_TIC_CFG_QX_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_SHFT 0x19 +#define HWIO_GCC_TIC_CFG_QX_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_BMSK 0x1000000 +#define HWIO_GCC_TIC_CFG_QX_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_SHFT 0x18 +#define HWIO_GCC_TIC_CFG_QX_CFG_SREGR_MEM_PERIPH_ON_STATUS_BMSK 0x800000 +#define HWIO_GCC_TIC_CFG_QX_CFG_SREGR_MEM_PERIPH_ON_STATUS_SHFT 0x17 +#define HWIO_GCC_TIC_CFG_QX_CFG_SREGR_MEM_CORE_ON_STATUS_BMSK 0x400000 +#define HWIO_GCC_TIC_CFG_QX_CFG_SREGR_MEM_CORE_ON_STATUS_SHFT 0x16 +#define HWIO_GCC_TIC_CFG_QX_CFG_SREGR_MEM_CPH_TIMER_BMSK 0x3f0000 +#define HWIO_GCC_TIC_CFG_QX_CFG_SREGR_MEM_CPH_TIMER_SHFT 0x10 +#define HWIO_GCC_TIC_CFG_QX_CFG_SREGR_SLEEP_TIMER_BMSK 0xff00 +#define HWIO_GCC_TIC_CFG_QX_CFG_SREGR_SLEEP_TIMER_SHFT 0x8 +#define HWIO_GCC_TIC_CFG_QX_CFG_SREGR_WAKEUP_TIMER_BMSK 0xff +#define HWIO_GCC_TIC_CFG_QX_CFG_SREGR_WAKEUP_TIMER_SHFT 0x0 + +#define HWIO_GCC_IMEM_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000b000) +#define HWIO_GCC_IMEM_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000b000) +#define HWIO_GCC_IMEM_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000b000) +#define HWIO_GCC_IMEM_BCR_RMSK 0x1 +#define HWIO_GCC_IMEM_BCR_ATTR 0x3 +#define HWIO_GCC_IMEM_BCR_IN \ + in_dword_masked(HWIO_GCC_IMEM_BCR_ADDR, HWIO_GCC_IMEM_BCR_RMSK) +#define HWIO_GCC_IMEM_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_IMEM_BCR_ADDR, m) +#define HWIO_GCC_IMEM_BCR_OUT(v) \ + out_dword(HWIO_GCC_IMEM_BCR_ADDR,v) +#define HWIO_GCC_IMEM_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_IMEM_BCR_ADDR,m,v,HWIO_GCC_IMEM_BCR_IN) +#define HWIO_GCC_IMEM_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_IMEM_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_IMEM_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_IMEM_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_IMEM_CFG_QX_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000b004) +#define HWIO_GCC_IMEM_CFG_QX_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000b004) +#define HWIO_GCC_IMEM_CFG_QX_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000b004) +#define HWIO_GCC_IMEM_CFG_QX_CBCR_RMSK 0x81d07005 +#define HWIO_GCC_IMEM_CFG_QX_CBCR_ATTR 0x3 +#define HWIO_GCC_IMEM_CFG_QX_CBCR_IN \ + in_dword_masked(HWIO_GCC_IMEM_CFG_QX_CBCR_ADDR, HWIO_GCC_IMEM_CFG_QX_CBCR_RMSK) +#define HWIO_GCC_IMEM_CFG_QX_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_IMEM_CFG_QX_CBCR_ADDR, m) +#define HWIO_GCC_IMEM_CFG_QX_CBCR_OUT(v) \ + out_dword(HWIO_GCC_IMEM_CFG_QX_CBCR_ADDR,v) +#define HWIO_GCC_IMEM_CFG_QX_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_IMEM_CFG_QX_CBCR_ADDR,m,v,HWIO_GCC_IMEM_CFG_QX_CBCR_IN) +#define HWIO_GCC_IMEM_CFG_QX_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_IMEM_CFG_QX_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_IMEM_CFG_QX_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_IMEM_CFG_QX_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_IMEM_CFG_QX_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_IMEM_CFG_QX_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_IMEM_CFG_QX_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_IMEM_CFG_QX_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_IMEM_CFG_QX_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_IMEM_CFG_QX_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_IMEM_CFG_QX_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_IMEM_CFG_QX_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_IMEM_CFG_QX_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IMEM_CFG_QX_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_IMEM_CFG_QX_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_IMEM_CFG_QX_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_IMEM_CFG_QX_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IMEM_CFG_QX_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_IMEM_CFG_QX_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_IMEM_CFG_QX_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_IMEM_CFG_QX_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IMEM_CFG_QX_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_IMEM_CFG_QX_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_IMEM_CFG_QX_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_IMEM_CFG_QX_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_IMEM_CFG_QX_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_IMEM_CFG_QX_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_IMEM_CFG_QX_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_IMEM_CFG_QX_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IMEM_CFG_QX_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_IMEM_CFG_QX_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000b008) +#define HWIO_GCC_IMEM_CFG_QX_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000b008) +#define HWIO_GCC_IMEM_CFG_QX_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000b008) +#define HWIO_GCC_IMEM_CFG_QX_SREGR_RMSK 0xf1ffffe +#define HWIO_GCC_IMEM_CFG_QX_SREGR_ATTR 0x3 +#define HWIO_GCC_IMEM_CFG_QX_SREGR_IN \ + in_dword_masked(HWIO_GCC_IMEM_CFG_QX_SREGR_ADDR, HWIO_GCC_IMEM_CFG_QX_SREGR_RMSK) +#define HWIO_GCC_IMEM_CFG_QX_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_IMEM_CFG_QX_SREGR_ADDR, m) +#define HWIO_GCC_IMEM_CFG_QX_SREGR_OUT(v) \ + out_dword(HWIO_GCC_IMEM_CFG_QX_SREGR_ADDR,v) +#define HWIO_GCC_IMEM_CFG_QX_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_IMEM_CFG_QX_SREGR_ADDR,m,v,HWIO_GCC_IMEM_CFG_QX_SREGR_IN) +#define HWIO_GCC_IMEM_CFG_QX_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xf000000 +#define HWIO_GCC_IMEM_CFG_QX_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_IMEM_CFG_QX_SREGR_PWR_FSM_CLK_SEL_BMSK 0x100000 +#define HWIO_GCC_IMEM_CFG_QX_SREGR_PWR_FSM_CLK_SEL_SHFT 0x14 +#define HWIO_GCC_IMEM_CFG_QX_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xf0000 +#define HWIO_GCC_IMEM_CFG_QX_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_IMEM_CFG_QX_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_IMEM_CFG_QX_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_IMEM_CFG_QX_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_IMEM_CFG_QX_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_IMEM_CFG_QX_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_IMEM_CFG_QX_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_IMEM_CFG_QX_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_IMEM_CFG_QX_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_IMEM_CFG_QX_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_IMEM_CFG_QX_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_IMEM_CFG_QX_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_IMEM_CFG_QX_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_IMEM_CFG_QX_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_IMEM_CFG_QX_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_IMEM_CFG_QX_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_IMEM_CFG_QX_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_IMEM_CFG_QX_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_IMEM_CFG_QX_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_IMEM_CFG_QX_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_IMEM_CFG_QX_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_IMEM_CFG_QX_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_IMEM_CFG_QX_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_IMEM_CFG_QX_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_IMEM_CFG_QX_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_IMEM_CFG_QX_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_IMEM_CFG_QX_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_IMEM_CFG_QX_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_IMEM_CFG_QX_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_IMEM_CFG_QX_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IMEM_CFG_QX_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_IMEM_CFG_QX_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_IMEM_CFG_QX_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_IMEM_CFG_QX_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_IMEM_CFG_QX_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_IMEM_CFG_QX_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_IMEM_CFG_QX_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_IMEM_CFG_QX_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_IMEM_CFG_QX_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_IMEM_CFG_QX_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_IMEM_CFG_QX_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_IMEM_CFG_QX_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_IMEM_CFG_QX_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_IMEM_CFG_QX_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_IMEM_CFG_QX_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_IMEM_CFG_QX_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_IMEM_CFG_QX_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_IMEM_CFG_QX_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_IMEM_CFG_QX_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_IMEM_CFG_QX_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_IMEM_CFG_QX_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_IMEM_CFG_QX_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_IMEM_CFG_QX_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_IMEM_CFG_QX_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_IMEM_CFG_QX_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_IMEM_CFG_QX_CFG_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000b00c) +#define HWIO_GCC_IMEM_CFG_QX_CFG_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000b00c) +#define HWIO_GCC_IMEM_CFG_QX_CFG_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000b00c) +#define HWIO_GCC_IMEM_CFG_QX_CFG_SREGR_RMSK 0xffffffff +#define HWIO_GCC_IMEM_CFG_QX_CFG_SREGR_ATTR 0x3 +#define HWIO_GCC_IMEM_CFG_QX_CFG_SREGR_IN \ + in_dword_masked(HWIO_GCC_IMEM_CFG_QX_CFG_SREGR_ADDR, HWIO_GCC_IMEM_CFG_QX_CFG_SREGR_RMSK) +#define HWIO_GCC_IMEM_CFG_QX_CFG_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_IMEM_CFG_QX_CFG_SREGR_ADDR, m) +#define HWIO_GCC_IMEM_CFG_QX_CFG_SREGR_OUT(v) \ + out_dword(HWIO_GCC_IMEM_CFG_QX_CFG_SREGR_ADDR,v) +#define HWIO_GCC_IMEM_CFG_QX_CFG_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_IMEM_CFG_QX_CFG_SREGR_ADDR,m,v,HWIO_GCC_IMEM_CFG_QX_CFG_SREGR_IN) +#define HWIO_GCC_IMEM_CFG_QX_CFG_SREGR_MEM_CORE_OFF_TIMER_BMSK 0xfc000000 +#define HWIO_GCC_IMEM_CFG_QX_CFG_SREGR_MEM_CORE_OFF_TIMER_SHFT 0x1a +#define HWIO_GCC_IMEM_CFG_QX_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_BMSK 0x2000000 +#define HWIO_GCC_IMEM_CFG_QX_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_SHFT 0x19 +#define HWIO_GCC_IMEM_CFG_QX_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_BMSK 0x1000000 +#define HWIO_GCC_IMEM_CFG_QX_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_SHFT 0x18 +#define HWIO_GCC_IMEM_CFG_QX_CFG_SREGR_MEM_PERIPH_ON_STATUS_BMSK 0x800000 +#define HWIO_GCC_IMEM_CFG_QX_CFG_SREGR_MEM_PERIPH_ON_STATUS_SHFT 0x17 +#define HWIO_GCC_IMEM_CFG_QX_CFG_SREGR_MEM_CORE_ON_STATUS_BMSK 0x400000 +#define HWIO_GCC_IMEM_CFG_QX_CFG_SREGR_MEM_CORE_ON_STATUS_SHFT 0x16 +#define HWIO_GCC_IMEM_CFG_QX_CFG_SREGR_MEM_CPH_TIMER_BMSK 0x3f0000 +#define HWIO_GCC_IMEM_CFG_QX_CFG_SREGR_MEM_CPH_TIMER_SHFT 0x10 +#define HWIO_GCC_IMEM_CFG_QX_CFG_SREGR_SLEEP_TIMER_BMSK 0xff00 +#define HWIO_GCC_IMEM_CFG_QX_CFG_SREGR_SLEEP_TIMER_SHFT 0x8 +#define HWIO_GCC_IMEM_CFG_QX_CFG_SREGR_WAKEUP_TIMER_BMSK 0xff +#define HWIO_GCC_IMEM_CFG_QX_CFG_SREGR_WAKEUP_TIMER_SHFT 0x0 + +#define HWIO_GCC_IMEM_CFG_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000b010) +#define HWIO_GCC_IMEM_CFG_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000b010) +#define HWIO_GCC_IMEM_CFG_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000b010) +#define HWIO_GCC_IMEM_CFG_AHB_CBCR_RMSK 0x81d00005 +#define HWIO_GCC_IMEM_CFG_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_IMEM_CFG_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_IMEM_CFG_AHB_CBCR_ADDR, HWIO_GCC_IMEM_CFG_AHB_CBCR_RMSK) +#define HWIO_GCC_IMEM_CFG_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_IMEM_CFG_AHB_CBCR_ADDR, m) +#define HWIO_GCC_IMEM_CFG_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_IMEM_CFG_AHB_CBCR_ADDR,v) +#define HWIO_GCC_IMEM_CFG_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_IMEM_CFG_AHB_CBCR_ADDR,m,v,HWIO_GCC_IMEM_CFG_AHB_CBCR_IN) +#define HWIO_GCC_IMEM_CFG_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_IMEM_CFG_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_IMEM_CFG_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_IMEM_CFG_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_IMEM_CFG_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_IMEM_CFG_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_IMEM_CFG_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_IMEM_CFG_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_IMEM_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_IMEM_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_IMEM_CFG_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_IMEM_CFG_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_IMEM_CFG_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_IMEM_CFG_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_IMEM_CFG_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_IMEM_CFG_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_IMEM_CFG_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IMEM_CFG_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MMU_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00073000) +#define HWIO_GCC_MMU_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00073000) +#define HWIO_GCC_MMU_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00073000) +#define HWIO_GCC_MMU_BCR_RMSK 0x1 +#define HWIO_GCC_MMU_BCR_ATTR 0x3 +#define HWIO_GCC_MMU_BCR_IN \ + in_dword_masked(HWIO_GCC_MMU_BCR_ADDR, HWIO_GCC_MMU_BCR_RMSK) +#define HWIO_GCC_MMU_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_MMU_BCR_ADDR, m) +#define HWIO_GCC_MMU_BCR_OUT(v) \ + out_dword(HWIO_GCC_MMU_BCR_ADDR,v) +#define HWIO_GCC_MMU_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MMU_BCR_ADDR,m,v,HWIO_GCC_MMU_BCR_IN) +#define HWIO_GCC_MMU_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_MMU_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_MMU_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMU_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MMU_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00073004) +#define HWIO_GCC_MMU_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00073004) +#define HWIO_GCC_MMU_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00073004) +#define HWIO_GCC_MMU_GDSCR_RMSK 0xf8ffffff +#define HWIO_GCC_MMU_GDSCR_ATTR 0x3 +#define HWIO_GCC_MMU_GDSCR_IN \ + in_dword_masked(HWIO_GCC_MMU_GDSCR_ADDR, HWIO_GCC_MMU_GDSCR_RMSK) +#define HWIO_GCC_MMU_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_MMU_GDSCR_ADDR, m) +#define HWIO_GCC_MMU_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_MMU_GDSCR_ADDR,v) +#define HWIO_GCC_MMU_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MMU_GDSCR_ADDR,m,v,HWIO_GCC_MMU_GDSCR_IN) +#define HWIO_GCC_MMU_GDSCR_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_MMU_GDSCR_PWR_ON_SHFT 0x1f +#define HWIO_GCC_MMU_GDSCR_GDSC_STATE_BMSK 0x78000000 +#define HWIO_GCC_MMU_GDSCR_GDSC_STATE_SHFT 0x1b +#define HWIO_GCC_MMU_GDSCR_EN_REST_WAIT_BMSK 0xf00000 +#define HWIO_GCC_MMU_GDSCR_EN_REST_WAIT_SHFT 0x14 +#define HWIO_GCC_MMU_GDSCR_EN_FEW_WAIT_BMSK 0xf0000 +#define HWIO_GCC_MMU_GDSCR_EN_FEW_WAIT_SHFT 0x10 +#define HWIO_GCC_MMU_GDSCR_CLK_DIS_WAIT_BMSK 0xf000 +#define HWIO_GCC_MMU_GDSCR_CLK_DIS_WAIT_SHFT 0xc +#define HWIO_GCC_MMU_GDSCR_RETAIN_FF_ENABLE_BMSK 0x800 +#define HWIO_GCC_MMU_GDSCR_RETAIN_FF_ENABLE_SHFT 0xb +#define HWIO_GCC_MMU_GDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMU_GDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMU_GDSCR_RESTORE_BMSK 0x400 +#define HWIO_GCC_MMU_GDSCR_RESTORE_SHFT 0xa +#define HWIO_GCC_MMU_GDSCR_RESTORE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMU_GDSCR_RESTORE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMU_GDSCR_SAVE_BMSK 0x200 +#define HWIO_GCC_MMU_GDSCR_SAVE_SHFT 0x9 +#define HWIO_GCC_MMU_GDSCR_SAVE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMU_GDSCR_SAVE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMU_GDSCR_RETAIN_BMSK 0x100 +#define HWIO_GCC_MMU_GDSCR_RETAIN_SHFT 0x8 +#define HWIO_GCC_MMU_GDSCR_RETAIN_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMU_GDSCR_RETAIN_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMU_GDSCR_EN_REST_BMSK 0x80 +#define HWIO_GCC_MMU_GDSCR_EN_REST_SHFT 0x7 +#define HWIO_GCC_MMU_GDSCR_EN_REST_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMU_GDSCR_EN_REST_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMU_GDSCR_EN_FEW_BMSK 0x40 +#define HWIO_GCC_MMU_GDSCR_EN_FEW_SHFT 0x6 +#define HWIO_GCC_MMU_GDSCR_EN_FEW_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMU_GDSCR_EN_FEW_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMU_GDSCR_CLAMP_IO_BMSK 0x20 +#define HWIO_GCC_MMU_GDSCR_CLAMP_IO_SHFT 0x5 +#define HWIO_GCC_MMU_GDSCR_CLAMP_IO_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMU_GDSCR_CLAMP_IO_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMU_GDSCR_CLK_DISABLE_BMSK 0x10 +#define HWIO_GCC_MMU_GDSCR_CLK_DISABLE_SHFT 0x4 +#define HWIO_GCC_MMU_GDSCR_CLK_DISABLE_CLK_NOT_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMU_GDSCR_CLK_DISABLE_CLK_IS_DISABLE_FVAL 0x1 +#define HWIO_GCC_MMU_GDSCR_PD_ARES_BMSK 0x8 +#define HWIO_GCC_MMU_GDSCR_PD_ARES_SHFT 0x3 +#define HWIO_GCC_MMU_GDSCR_PD_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_MMU_GDSCR_PD_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_MMU_GDSCR_SW_OVERRIDE_BMSK 0x4 +#define HWIO_GCC_MMU_GDSCR_SW_OVERRIDE_SHFT 0x2 +#define HWIO_GCC_MMU_GDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMU_GDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMU_GDSCR_HW_CONTROL_BMSK 0x2 +#define HWIO_GCC_MMU_GDSCR_HW_CONTROL_SHFT 0x1 +#define HWIO_GCC_MMU_GDSCR_HW_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMU_GDSCR_HW_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMU_GDSCR_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_MMU_GDSCR_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_MMU_GDSCR_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMU_GDSCR_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MMU_CFG_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00073008) +#define HWIO_GCC_MMU_CFG_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00073008) +#define HWIO_GCC_MMU_CFG_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00073008) +#define HWIO_GCC_MMU_CFG_GDSCR_RMSK 0x7ffffff +#define HWIO_GCC_MMU_CFG_GDSCR_ATTR 0x3 +#define HWIO_GCC_MMU_CFG_GDSCR_IN \ + in_dword_masked(HWIO_GCC_MMU_CFG_GDSCR_ADDR, HWIO_GCC_MMU_CFG_GDSCR_RMSK) +#define HWIO_GCC_MMU_CFG_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_MMU_CFG_GDSCR_ADDR, m) +#define HWIO_GCC_MMU_CFG_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_MMU_CFG_GDSCR_ADDR,v) +#define HWIO_GCC_MMU_CFG_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MMU_CFG_GDSCR_ADDR,m,v,HWIO_GCC_MMU_CFG_GDSCR_IN) +#define HWIO_GCC_MMU_CFG_GDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4000000 +#define HWIO_GCC_MMU_CFG_GDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x1a +#define HWIO_GCC_MMU_CFG_GDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMU_CFG_GDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMU_CFG_GDSCR_GDSC_PWR_DWN_START_BMSK 0x2000000 +#define HWIO_GCC_MMU_CFG_GDSCR_GDSC_PWR_DWN_START_SHFT 0x19 +#define HWIO_GCC_MMU_CFG_GDSCR_GDSC_PWR_UP_START_BMSK 0x1000000 +#define HWIO_GCC_MMU_CFG_GDSCR_GDSC_PWR_UP_START_SHFT 0x18 +#define HWIO_GCC_MMU_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_BMSK 0xf00000 +#define HWIO_GCC_MMU_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_SHFT 0x14 +#define HWIO_GCC_MMU_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_BMSK 0x80000 +#define HWIO_GCC_MMU_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_SHFT 0x13 +#define HWIO_GCC_MMU_CFG_GDSCR_GDSC_ENR_ACK_STATUS_BMSK 0x40000 +#define HWIO_GCC_MMU_CFG_GDSCR_GDSC_ENR_ACK_STATUS_SHFT 0x12 +#define HWIO_GCC_MMU_CFG_GDSCR_GDSC_ENF_ACK_STATUS_BMSK 0x20000 +#define HWIO_GCC_MMU_CFG_GDSCR_GDSC_ENF_ACK_STATUS_SHFT 0x11 +#define HWIO_GCC_MMU_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_BMSK 0x10000 +#define HWIO_GCC_MMU_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_SHFT 0x10 +#define HWIO_GCC_MMU_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_BMSK 0x8000 +#define HWIO_GCC_MMU_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_SHFT 0xf +#define HWIO_GCC_MMU_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_BMSK 0x7800 +#define HWIO_GCC_MMU_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_SHFT 0xb +#define HWIO_GCC_MMU_CFG_GDSCR_GDSC_HANDSHAKE_DIS_BMSK 0x400 +#define HWIO_GCC_MMU_CFG_GDSCR_GDSC_HANDSHAKE_DIS_SHFT 0xa +#define HWIO_GCC_MMU_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_BMSK 0x200 +#define HWIO_GCC_MMU_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_SHFT 0x9 +#define HWIO_GCC_MMU_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_BMSK 0x100 +#define HWIO_GCC_MMU_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_SHFT 0x8 +#define HWIO_GCC_MMU_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_BMSK 0x80 +#define HWIO_GCC_MMU_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_SHFT 0x7 +#define HWIO_GCC_MMU_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_BMSK 0x60 +#define HWIO_GCC_MMU_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_SHFT 0x5 +#define HWIO_GCC_MMU_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_BMSK 0x10 +#define HWIO_GCC_MMU_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_SHFT 0x4 +#define HWIO_GCC_MMU_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_BMSK 0x8 +#define HWIO_GCC_MMU_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_SHFT 0x3 +#define HWIO_GCC_MMU_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_BMSK 0x4 +#define HWIO_GCC_MMU_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_SHFT 0x2 +#define HWIO_GCC_MMU_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_BMSK 0x2 +#define HWIO_GCC_MMU_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_SHFT 0x1 +#define HWIO_GCC_MMU_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_MMU_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_SHFT 0x0 + +#define HWIO_GCC_MMU_CFG2_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007300c) +#define HWIO_GCC_MMU_CFG2_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007300c) +#define HWIO_GCC_MMU_CFG2_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007300c) +#define HWIO_GCC_MMU_CFG2_GDSCR_RMSK 0x7ffff +#define HWIO_GCC_MMU_CFG2_GDSCR_ATTR 0x3 +#define HWIO_GCC_MMU_CFG2_GDSCR_IN \ + in_dword_masked(HWIO_GCC_MMU_CFG2_GDSCR_ADDR, HWIO_GCC_MMU_CFG2_GDSCR_RMSK) +#define HWIO_GCC_MMU_CFG2_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_MMU_CFG2_GDSCR_ADDR, m) +#define HWIO_GCC_MMU_CFG2_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_MMU_CFG2_GDSCR_ADDR,v) +#define HWIO_GCC_MMU_CFG2_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MMU_CFG2_GDSCR_ADDR,m,v,HWIO_GCC_MMU_CFG2_GDSCR_IN) +#define HWIO_GCC_MMU_CFG2_GDSCR_GDSC_MEM_PWRUP_ACK_OVERRIDE_BMSK 0x40000 +#define HWIO_GCC_MMU_CFG2_GDSCR_GDSC_MEM_PWRUP_ACK_OVERRIDE_SHFT 0x12 +#define HWIO_GCC_MMU_CFG2_GDSCR_GDSC_PWRDWN_ENABLE_ACK_OVERRIDE_BMSK 0x20000 +#define HWIO_GCC_MMU_CFG2_GDSCR_GDSC_PWRDWN_ENABLE_ACK_OVERRIDE_SHFT 0x11 +#define HWIO_GCC_MMU_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_BMSK 0x10000 +#define HWIO_GCC_MMU_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_SHFT 0x10 +#define HWIO_GCC_MMU_CFG2_GDSCR_DLY_MEM_PWR_UP_BMSK 0xf000 +#define HWIO_GCC_MMU_CFG2_GDSCR_DLY_MEM_PWR_UP_SHFT 0xc +#define HWIO_GCC_MMU_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_BMSK 0xf00 +#define HWIO_GCC_MMU_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_SHFT 0x8 +#define HWIO_GCC_MMU_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_BMSK 0xf0 +#define HWIO_GCC_MMU_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_SHFT 0x4 +#define HWIO_GCC_MMU_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_BMSK 0xf +#define HWIO_GCC_MMU_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_SHFT 0x0 + +#define HWIO_GCC_MMU_CFG3_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00073010) +#define HWIO_GCC_MMU_CFG3_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00073010) +#define HWIO_GCC_MMU_CFG3_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00073010) +#define HWIO_GCC_MMU_CFG3_GDSCR_RMSK 0x7ffffff +#define HWIO_GCC_MMU_CFG3_GDSCR_ATTR 0x3 +#define HWIO_GCC_MMU_CFG3_GDSCR_IN \ + in_dword_masked(HWIO_GCC_MMU_CFG3_GDSCR_ADDR, HWIO_GCC_MMU_CFG3_GDSCR_RMSK) +#define HWIO_GCC_MMU_CFG3_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_MMU_CFG3_GDSCR_ADDR, m) +#define HWIO_GCC_MMU_CFG3_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_MMU_CFG3_GDSCR_ADDR,v) +#define HWIO_GCC_MMU_CFG3_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MMU_CFG3_GDSCR_ADDR,m,v,HWIO_GCC_MMU_CFG3_GDSCR_IN) +#define HWIO_GCC_MMU_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_STATUS_BMSK 0x4000000 +#define HWIO_GCC_MMU_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_STATUS_SHFT 0x1a +#define HWIO_GCC_MMU_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_BMSK 0x2000000 +#define HWIO_GCC_MMU_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_SHFT 0x19 +#define HWIO_GCC_MMU_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMU_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMU_CFG3_GDSCR_DLY_ACCU_RED_SHIFTER_DONE_BMSK 0x1e00000 +#define HWIO_GCC_MMU_CFG3_GDSCR_DLY_ACCU_RED_SHIFTER_DONE_SHFT 0x15 +#define HWIO_GCC_MMU_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_BMSK 0x100000 +#define HWIO_GCC_MMU_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_SHFT 0x14 +#define HWIO_GCC_MMU_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMU_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMU_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_BMSK 0x80000 +#define HWIO_GCC_MMU_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_SHFT 0x13 +#define HWIO_GCC_MMU_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMU_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMU_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_BMSK 0x40000 +#define HWIO_GCC_MMU_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_SHFT 0x12 +#define HWIO_GCC_MMU_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMU_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMU_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_BMSK 0x20000 +#define HWIO_GCC_MMU_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_SHFT 0x11 +#define HWIO_GCC_MMU_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMU_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMU_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_BMSK 0x10000 +#define HWIO_GCC_MMU_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_SHFT 0x10 +#define HWIO_GCC_MMU_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMU_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMU_CFG3_GDSCR_GDSC_SPARE_CTRL_IN_BMSK 0xff00 +#define HWIO_GCC_MMU_CFG3_GDSCR_GDSC_SPARE_CTRL_IN_SHFT 0x8 +#define HWIO_GCC_MMU_CFG3_GDSCR_GDSC_SPARE_CTRL_OUT_BMSK 0xff +#define HWIO_GCC_MMU_CFG3_GDSCR_GDSC_SPARE_CTRL_OUT_SHFT 0x0 + +#define HWIO_GCC_MMU_CFG4_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00073014) +#define HWIO_GCC_MMU_CFG4_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00073014) +#define HWIO_GCC_MMU_CFG4_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00073014) +#define HWIO_GCC_MMU_CFG4_GDSCR_RMSK 0xffffff +#define HWIO_GCC_MMU_CFG4_GDSCR_ATTR 0x3 +#define HWIO_GCC_MMU_CFG4_GDSCR_IN \ + in_dword_masked(HWIO_GCC_MMU_CFG4_GDSCR_ADDR, HWIO_GCC_MMU_CFG4_GDSCR_RMSK) +#define HWIO_GCC_MMU_CFG4_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_MMU_CFG4_GDSCR_ADDR, m) +#define HWIO_GCC_MMU_CFG4_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_MMU_CFG4_GDSCR_ADDR,v) +#define HWIO_GCC_MMU_CFG4_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MMU_CFG4_GDSCR_ADDR,m,v,HWIO_GCC_MMU_CFG4_GDSCR_IN) +#define HWIO_GCC_MMU_CFG4_GDSCR_DLY_UNCLAMPIO_BMSK 0xf00000 +#define HWIO_GCC_MMU_CFG4_GDSCR_DLY_UNCLAMPIO_SHFT 0x14 +#define HWIO_GCC_MMU_CFG4_GDSCR_DLY_RESTOREFF_BMSK 0xf0000 +#define HWIO_GCC_MMU_CFG4_GDSCR_DLY_RESTOREFF_SHFT 0x10 +#define HWIO_GCC_MMU_CFG4_GDSCR_DLY_NORETAINFF_BMSK 0xf000 +#define HWIO_GCC_MMU_CFG4_GDSCR_DLY_NORETAINFF_SHFT 0xc +#define HWIO_GCC_MMU_CFG4_GDSCR_DLY_DEASSERTARES_BMSK 0xf00 +#define HWIO_GCC_MMU_CFG4_GDSCR_DLY_DEASSERTARES_SHFT 0x8 +#define HWIO_GCC_MMU_CFG4_GDSCR_DLY_CLAMPIO_BMSK 0xf0 +#define HWIO_GCC_MMU_CFG4_GDSCR_DLY_CLAMPIO_SHFT 0x4 +#define HWIO_GCC_MMU_CFG4_GDSCR_DLY_RETAINFF_BMSK 0xf +#define HWIO_GCC_MMU_CFG4_GDSCR_DLY_RETAINFF_SHFT 0x0 + +#define HWIO_GCC_TCU_CFG_QX_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00073018) +#define HWIO_GCC_TCU_CFG_QX_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00073018) +#define HWIO_GCC_TCU_CFG_QX_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00073018) +#define HWIO_GCC_TCU_CFG_QX_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_TCU_CFG_QX_CBCR_ATTR 0x3 +#define HWIO_GCC_TCU_CFG_QX_CBCR_IN \ + in_dword_masked(HWIO_GCC_TCU_CFG_QX_CBCR_ADDR, HWIO_GCC_TCU_CFG_QX_CBCR_RMSK) +#define HWIO_GCC_TCU_CFG_QX_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_TCU_CFG_QX_CBCR_ADDR, m) +#define HWIO_GCC_TCU_CFG_QX_CBCR_OUT(v) \ + out_dword(HWIO_GCC_TCU_CFG_QX_CBCR_ADDR,v) +#define HWIO_GCC_TCU_CFG_QX_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TCU_CFG_QX_CBCR_ADDR,m,v,HWIO_GCC_TCU_CFG_QX_CBCR_IN) +#define HWIO_GCC_TCU_CFG_QX_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TCU_CFG_QX_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TCU_CFG_QX_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_TCU_CFG_QX_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_TCU_CFG_QX_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_TCU_CFG_QX_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_TCU_CFG_QX_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_TCU_CFG_QX_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_TCU_CFG_QX_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_TCU_CFG_QX_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_TCU_CFG_QX_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_TCU_CFG_QX_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_TCU_CFG_QX_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_TCU_CFG_QX_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_TCU_CFG_QX_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_TCU_CFG_QX_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_TCU_CFG_QX_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_TCU_CFG_QX_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_TCU_CFG_QX_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_TCU_CFG_QX_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_TCU_CFG_QX_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_TCU_CFG_QX_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_TCU_CFG_QX_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TCU_CFG_QX_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MMU_TCU_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007301c) +#define HWIO_GCC_MMU_TCU_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007301c) +#define HWIO_GCC_MMU_TCU_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007301c) +#define HWIO_GCC_MMU_TCU_CBCR_RMSK 0x81f0700f +#define HWIO_GCC_MMU_TCU_CBCR_ATTR 0x3 +#define HWIO_GCC_MMU_TCU_CBCR_IN \ + in_dword_masked(HWIO_GCC_MMU_TCU_CBCR_ADDR, HWIO_GCC_MMU_TCU_CBCR_RMSK) +#define HWIO_GCC_MMU_TCU_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_MMU_TCU_CBCR_ADDR, m) +#define HWIO_GCC_MMU_TCU_CBCR_OUT(v) \ + out_dword(HWIO_GCC_MMU_TCU_CBCR_ADDR,v) +#define HWIO_GCC_MMU_TCU_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MMU_TCU_CBCR_ADDR,m,v,HWIO_GCC_MMU_TCU_CBCR_IN) +#define HWIO_GCC_MMU_TCU_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_MMU_TCU_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_MMU_TCU_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_MMU_TCU_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_MMU_TCU_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_MMU_TCU_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_MMU_TCU_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_MMU_TCU_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_MMU_TCU_CBCR_IGNORE_PMU_CLK_DIS_BMSK 0x200000 +#define HWIO_GCC_MMU_TCU_CBCR_IGNORE_PMU_CLK_DIS_SHFT 0x15 +#define HWIO_GCC_MMU_TCU_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_MMU_TCU_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_MMU_TCU_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_MMU_TCU_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_MMU_TCU_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMU_TCU_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMU_TCU_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_MMU_TCU_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_MMU_TCU_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMU_TCU_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMU_TCU_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_MMU_TCU_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_MMU_TCU_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMU_TCU_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMU_TCU_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_MMU_TCU_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_MMU_TCU_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_MMU_TCU_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_MMU_TCU_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_MMU_TCU_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_MMU_TCU_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_MMU_TCU_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_MMU_TCU_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMU_TCU_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMU_TCU_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_MMU_TCU_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_MMU_TCU_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMU_TCU_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MMU_TCU_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00073020) +#define HWIO_GCC_MMU_TCU_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00073020) +#define HWIO_GCC_MMU_TCU_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00073020) +#define HWIO_GCC_MMU_TCU_SREGR_RMSK 0xf1ffffe +#define HWIO_GCC_MMU_TCU_SREGR_ATTR 0x3 +#define HWIO_GCC_MMU_TCU_SREGR_IN \ + in_dword_masked(HWIO_GCC_MMU_TCU_SREGR_ADDR, HWIO_GCC_MMU_TCU_SREGR_RMSK) +#define HWIO_GCC_MMU_TCU_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_MMU_TCU_SREGR_ADDR, m) +#define HWIO_GCC_MMU_TCU_SREGR_OUT(v) \ + out_dword(HWIO_GCC_MMU_TCU_SREGR_ADDR,v) +#define HWIO_GCC_MMU_TCU_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MMU_TCU_SREGR_ADDR,m,v,HWIO_GCC_MMU_TCU_SREGR_IN) +#define HWIO_GCC_MMU_TCU_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xf000000 +#define HWIO_GCC_MMU_TCU_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_MMU_TCU_SREGR_PWR_FSM_CLK_SEL_BMSK 0x100000 +#define HWIO_GCC_MMU_TCU_SREGR_PWR_FSM_CLK_SEL_SHFT 0x14 +#define HWIO_GCC_MMU_TCU_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xf0000 +#define HWIO_GCC_MMU_TCU_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_MMU_TCU_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_MMU_TCU_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_MMU_TCU_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_MMU_TCU_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_MMU_TCU_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_MMU_TCU_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_MMU_TCU_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_MMU_TCU_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_MMU_TCU_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_MMU_TCU_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_MMU_TCU_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_MMU_TCU_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_MMU_TCU_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_MMU_TCU_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_MMU_TCU_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_MMU_TCU_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_MMU_TCU_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_MMU_TCU_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_MMU_TCU_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_MMU_TCU_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_MMU_TCU_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_MMU_TCU_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_MMU_TCU_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_MMU_TCU_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_MMU_TCU_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_MMU_TCU_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_MMU_TCU_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_MMU_TCU_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_MMU_TCU_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMU_TCU_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMU_TCU_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_MMU_TCU_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_MMU_TCU_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_MMU_TCU_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMU_TCU_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_MMU_TCU_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_MMU_TCU_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_MMU_TCU_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_MMU_TCU_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_MMU_TCU_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_MMU_TCU_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_MMU_TCU_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_MMU_TCU_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_MMU_TCU_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_MMU_TCU_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_MMU_TCU_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_MMU_TCU_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_MMU_TCU_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_MMU_TCU_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_MMU_TCU_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_MMU_TCU_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_MMU_TCU_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_MMU_TCU_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMU_TCU_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MMU_TCU_CFG_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00073024) +#define HWIO_GCC_MMU_TCU_CFG_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00073024) +#define HWIO_GCC_MMU_TCU_CFG_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00073024) +#define HWIO_GCC_MMU_TCU_CFG_SREGR_RMSK 0xffffffff +#define HWIO_GCC_MMU_TCU_CFG_SREGR_ATTR 0x3 +#define HWIO_GCC_MMU_TCU_CFG_SREGR_IN \ + in_dword_masked(HWIO_GCC_MMU_TCU_CFG_SREGR_ADDR, HWIO_GCC_MMU_TCU_CFG_SREGR_RMSK) +#define HWIO_GCC_MMU_TCU_CFG_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_MMU_TCU_CFG_SREGR_ADDR, m) +#define HWIO_GCC_MMU_TCU_CFG_SREGR_OUT(v) \ + out_dword(HWIO_GCC_MMU_TCU_CFG_SREGR_ADDR,v) +#define HWIO_GCC_MMU_TCU_CFG_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MMU_TCU_CFG_SREGR_ADDR,m,v,HWIO_GCC_MMU_TCU_CFG_SREGR_IN) +#define HWIO_GCC_MMU_TCU_CFG_SREGR_MEM_CORE_OFF_TIMER_BMSK 0xfc000000 +#define HWIO_GCC_MMU_TCU_CFG_SREGR_MEM_CORE_OFF_TIMER_SHFT 0x1a +#define HWIO_GCC_MMU_TCU_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_BMSK 0x2000000 +#define HWIO_GCC_MMU_TCU_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_SHFT 0x19 +#define HWIO_GCC_MMU_TCU_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_BMSK 0x1000000 +#define HWIO_GCC_MMU_TCU_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_SHFT 0x18 +#define HWIO_GCC_MMU_TCU_CFG_SREGR_MEM_PERIPH_ON_STATUS_BMSK 0x800000 +#define HWIO_GCC_MMU_TCU_CFG_SREGR_MEM_PERIPH_ON_STATUS_SHFT 0x17 +#define HWIO_GCC_MMU_TCU_CFG_SREGR_MEM_CORE_ON_STATUS_BMSK 0x400000 +#define HWIO_GCC_MMU_TCU_CFG_SREGR_MEM_CORE_ON_STATUS_SHFT 0x16 +#define HWIO_GCC_MMU_TCU_CFG_SREGR_MEM_CPH_TIMER_BMSK 0x3f0000 +#define HWIO_GCC_MMU_TCU_CFG_SREGR_MEM_CPH_TIMER_SHFT 0x10 +#define HWIO_GCC_MMU_TCU_CFG_SREGR_SLEEP_TIMER_BMSK 0xff00 +#define HWIO_GCC_MMU_TCU_CFG_SREGR_SLEEP_TIMER_SHFT 0x8 +#define HWIO_GCC_MMU_TCU_CFG_SREGR_WAKEUP_TIMER_BMSK 0xff +#define HWIO_GCC_MMU_TCU_CFG_SREGR_WAKEUP_TIMER_SHFT 0x0 + +#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007303c) +#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007303c) +#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007303c) +#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_RMSK 0x3ffffff +#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_CMD_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_CMD_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_CMD_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_CMD_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_CMD_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_CMD_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_RCG_SW_CTRL_BMSK 0x3ff8000 +#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_RCG_SW_CTRL_SHFT 0xf +#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_SW_PERF_STATE_BMSK 0x7800 +#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_SW_PERF_STATE_SHFT 0xb +#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_SW_OVERRIDE_BMSK 0x400 +#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_SW_OVERRIDE_SHFT 0xa +#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK 0x200 +#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT 0x9 +#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_DFS_FSM_STATE_BMSK 0x1c0 +#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_DFS_FSM_STATE_SHFT 0x6 +#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_HW_CLK_CONTROL_BMSK 0x20 +#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_HW_CLK_CONTROL_SHFT 0x5 +#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_CURR_PERF_STATE_BMSK 0x1e +#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_CURR_PERF_STATE_SHFT 0x1 +#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_DFS_EN_BMSK 0x1 +#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_DFS_EN_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_DFS_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_DFS_EN_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00073044) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00073044) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00073044) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00073048) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00073048) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00073048) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007304c) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007304c) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007304c) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00073050) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00073050) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00073050) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00073054) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00073054) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00073054) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00073058) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00073058) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00073058) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007305c) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007305c) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007305c) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00073060) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00073060) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00073060) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00073064) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00073064) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00073064) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00073068) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00073068) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00073068) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007306c) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007306c) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007306c) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00073070) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00073070) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00073070) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00073074) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00073074) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00073074) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00073078) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00073078) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00073078) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007307c) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007307c) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007307c) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00073080) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00073080) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00073080) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_MMU_TCU_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00073028) +#define HWIO_GCC_MMU_TCU_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00073028) +#define HWIO_GCC_MMU_TCU_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00073028) +#define HWIO_GCC_MMU_TCU_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_MMU_TCU_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_MMU_TCU_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_MMU_TCU_CMD_RCGR_ADDR, HWIO_GCC_MMU_TCU_CMD_RCGR_RMSK) +#define HWIO_GCC_MMU_TCU_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_MMU_TCU_CMD_RCGR_ADDR, m) +#define HWIO_GCC_MMU_TCU_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_MMU_TCU_CMD_RCGR_ADDR,v) +#define HWIO_GCC_MMU_TCU_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MMU_TCU_CMD_RCGR_ADDR,m,v,HWIO_GCC_MMU_TCU_CMD_RCGR_IN) +#define HWIO_GCC_MMU_TCU_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_MMU_TCU_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_MMU_TCU_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_MMU_TCU_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_MMU_TCU_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_MMU_TCU_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_MMU_TCU_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMU_TCU_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMU_TCU_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_MMU_TCU_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_MMU_TCU_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMU_TCU_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MMU_TCU_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007302c) +#define HWIO_GCC_MMU_TCU_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007302c) +#define HWIO_GCC_MMU_TCU_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007302c) +#define HWIO_GCC_MMU_TCU_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_MMU_TCU_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_MMU_TCU_CFG_RCGR_ADDR, HWIO_GCC_MMU_TCU_CFG_RCGR_RMSK) +#define HWIO_GCC_MMU_TCU_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_MMU_TCU_CFG_RCGR_ADDR, m) +#define HWIO_GCC_MMU_TCU_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_MMU_TCU_CFG_RCGR_ADDR,v) +#define HWIO_GCC_MMU_TCU_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MMU_TCU_CFG_RCGR_ADDR,m,v,HWIO_GCC_MMU_TCU_CFG_RCGR_IN) +#define HWIO_GCC_MMU_TCU_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_MMU_TCU_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00073154) +#define HWIO_GCC_MMU_TCU_DCD_CDIV_DCDR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00073154) +#define HWIO_GCC_MMU_TCU_DCD_CDIV_DCDR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00073154) +#define HWIO_GCC_MMU_TCU_DCD_CDIV_DCDR_RMSK 0x1 +#define HWIO_GCC_MMU_TCU_DCD_CDIV_DCDR_ATTR 0x3 +#define HWIO_GCC_MMU_TCU_DCD_CDIV_DCDR_IN \ + in_dword_masked(HWIO_GCC_MMU_TCU_DCD_CDIV_DCDR_ADDR, HWIO_GCC_MMU_TCU_DCD_CDIV_DCDR_RMSK) +#define HWIO_GCC_MMU_TCU_DCD_CDIV_DCDR_INM(m) \ + in_dword_masked(HWIO_GCC_MMU_TCU_DCD_CDIV_DCDR_ADDR, m) +#define HWIO_GCC_MMU_TCU_DCD_CDIV_DCDR_OUT(v) \ + out_dword(HWIO_GCC_MMU_TCU_DCD_CDIV_DCDR_ADDR,v) +#define HWIO_GCC_MMU_TCU_DCD_CDIV_DCDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MMU_TCU_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_MMU_TCU_DCD_CDIV_DCDR_IN) +#define HWIO_GCC_MMU_TCU_DCD_CDIV_DCDR_DCD_ENABLE_BMSK 0x1 +#define HWIO_GCC_MMU_TCU_DCD_CDIV_DCDR_DCD_ENABLE_SHFT 0x0 +#define HWIO_GCC_MMU_TCU_DCD_CDIV_DCDR_DCD_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMU_TCU_DCD_CDIV_DCDR_DCD_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TCU_ANOC_QTB1_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00073158) +#define HWIO_GCC_TCU_ANOC_QTB1_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00073158) +#define HWIO_GCC_TCU_ANOC_QTB1_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00073158) +#define HWIO_GCC_TCU_ANOC_QTB1_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_TCU_ANOC_QTB1_CBCR_ATTR 0x3 +#define HWIO_GCC_TCU_ANOC_QTB1_CBCR_IN \ + in_dword_masked(HWIO_GCC_TCU_ANOC_QTB1_CBCR_ADDR, HWIO_GCC_TCU_ANOC_QTB1_CBCR_RMSK) +#define HWIO_GCC_TCU_ANOC_QTB1_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_TCU_ANOC_QTB1_CBCR_ADDR, m) +#define HWIO_GCC_TCU_ANOC_QTB1_CBCR_OUT(v) \ + out_dword(HWIO_GCC_TCU_ANOC_QTB1_CBCR_ADDR,v) +#define HWIO_GCC_TCU_ANOC_QTB1_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TCU_ANOC_QTB1_CBCR_ADDR,m,v,HWIO_GCC_TCU_ANOC_QTB1_CBCR_IN) +#define HWIO_GCC_TCU_ANOC_QTB1_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TCU_ANOC_QTB1_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TCU_ANOC_QTB1_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_TCU_ANOC_QTB1_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_TCU_ANOC_QTB1_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_TCU_ANOC_QTB1_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_TCU_ANOC_QTB1_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_TCU_ANOC_QTB1_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_TCU_ANOC_QTB1_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_TCU_ANOC_QTB1_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_TCU_ANOC_QTB1_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_TCU_ANOC_QTB1_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_TCU_ANOC_QTB1_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_TCU_ANOC_QTB1_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_TCU_ANOC_QTB1_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_TCU_ANOC_QTB1_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_TCU_ANOC_QTB1_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_TCU_ANOC_QTB1_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_TCU_ANOC_QTB1_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_TCU_ANOC_QTB1_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_TCU_ANOC_QTB1_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_TCU_ANOC_QTB1_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_TCU_ANOC_QTB1_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TCU_ANOC_QTB1_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TCU_ANOC_QTB2_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007315c) +#define HWIO_GCC_TCU_ANOC_QTB2_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007315c) +#define HWIO_GCC_TCU_ANOC_QTB2_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007315c) +#define HWIO_GCC_TCU_ANOC_QTB2_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_TCU_ANOC_QTB2_CBCR_ATTR 0x3 +#define HWIO_GCC_TCU_ANOC_QTB2_CBCR_IN \ + in_dword_masked(HWIO_GCC_TCU_ANOC_QTB2_CBCR_ADDR, HWIO_GCC_TCU_ANOC_QTB2_CBCR_RMSK) +#define HWIO_GCC_TCU_ANOC_QTB2_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_TCU_ANOC_QTB2_CBCR_ADDR, m) +#define HWIO_GCC_TCU_ANOC_QTB2_CBCR_OUT(v) \ + out_dword(HWIO_GCC_TCU_ANOC_QTB2_CBCR_ADDR,v) +#define HWIO_GCC_TCU_ANOC_QTB2_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TCU_ANOC_QTB2_CBCR_ADDR,m,v,HWIO_GCC_TCU_ANOC_QTB2_CBCR_IN) +#define HWIO_GCC_TCU_ANOC_QTB2_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TCU_ANOC_QTB2_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TCU_ANOC_QTB2_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_TCU_ANOC_QTB2_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_TCU_ANOC_QTB2_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_TCU_ANOC_QTB2_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_TCU_ANOC_QTB2_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_TCU_ANOC_QTB2_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_TCU_ANOC_QTB2_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_TCU_ANOC_QTB2_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_TCU_ANOC_QTB2_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_TCU_ANOC_QTB2_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_TCU_ANOC_QTB2_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_TCU_ANOC_QTB2_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_TCU_ANOC_QTB2_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_TCU_ANOC_QTB2_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_TCU_ANOC_QTB2_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_TCU_ANOC_QTB2_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_TCU_ANOC_QTB2_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_TCU_ANOC_QTB2_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_TCU_ANOC_QTB2_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_TCU_ANOC_QTB2_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_TCU_ANOC_QTB2_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TCU_ANOC_QTB2_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TCU_MMNOC_QTB_SF_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00073160) +#define HWIO_GCC_TCU_MMNOC_QTB_SF_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00073160) +#define HWIO_GCC_TCU_MMNOC_QTB_SF_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00073160) +#define HWIO_GCC_TCU_MMNOC_QTB_SF_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_TCU_MMNOC_QTB_SF_CBCR_ATTR 0x3 +#define HWIO_GCC_TCU_MMNOC_QTB_SF_CBCR_IN \ + in_dword_masked(HWIO_GCC_TCU_MMNOC_QTB_SF_CBCR_ADDR, HWIO_GCC_TCU_MMNOC_QTB_SF_CBCR_RMSK) +#define HWIO_GCC_TCU_MMNOC_QTB_SF_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_TCU_MMNOC_QTB_SF_CBCR_ADDR, m) +#define HWIO_GCC_TCU_MMNOC_QTB_SF_CBCR_OUT(v) \ + out_dword(HWIO_GCC_TCU_MMNOC_QTB_SF_CBCR_ADDR,v) +#define HWIO_GCC_TCU_MMNOC_QTB_SF_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TCU_MMNOC_QTB_SF_CBCR_ADDR,m,v,HWIO_GCC_TCU_MMNOC_QTB_SF_CBCR_IN) +#define HWIO_GCC_TCU_MMNOC_QTB_SF_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TCU_MMNOC_QTB_SF_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TCU_MMNOC_QTB_SF_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_TCU_MMNOC_QTB_SF_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_TCU_MMNOC_QTB_SF_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_TCU_MMNOC_QTB_SF_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_TCU_MMNOC_QTB_SF_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_TCU_MMNOC_QTB_SF_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_TCU_MMNOC_QTB_SF_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_TCU_MMNOC_QTB_SF_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_TCU_MMNOC_QTB_SF_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_TCU_MMNOC_QTB_SF_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_TCU_MMNOC_QTB_SF_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_TCU_MMNOC_QTB_SF_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_TCU_MMNOC_QTB_SF_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_TCU_MMNOC_QTB_SF_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_TCU_MMNOC_QTB_SF_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_TCU_MMNOC_QTB_SF_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_TCU_MMNOC_QTB_SF_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_TCU_MMNOC_QTB_SF_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_TCU_MMNOC_QTB_SF_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_TCU_MMNOC_QTB_SF_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_TCU_MMNOC_QTB_SF_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TCU_MMNOC_QTB_SF_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TCU_MMNOC_QTB_HF01_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00073164) +#define HWIO_GCC_TCU_MMNOC_QTB_HF01_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00073164) +#define HWIO_GCC_TCU_MMNOC_QTB_HF01_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00073164) +#define HWIO_GCC_TCU_MMNOC_QTB_HF01_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_TCU_MMNOC_QTB_HF01_CBCR_ATTR 0x3 +#define HWIO_GCC_TCU_MMNOC_QTB_HF01_CBCR_IN \ + in_dword_masked(HWIO_GCC_TCU_MMNOC_QTB_HF01_CBCR_ADDR, HWIO_GCC_TCU_MMNOC_QTB_HF01_CBCR_RMSK) +#define HWIO_GCC_TCU_MMNOC_QTB_HF01_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_TCU_MMNOC_QTB_HF01_CBCR_ADDR, m) +#define HWIO_GCC_TCU_MMNOC_QTB_HF01_CBCR_OUT(v) \ + out_dword(HWIO_GCC_TCU_MMNOC_QTB_HF01_CBCR_ADDR,v) +#define HWIO_GCC_TCU_MMNOC_QTB_HF01_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TCU_MMNOC_QTB_HF01_CBCR_ADDR,m,v,HWIO_GCC_TCU_MMNOC_QTB_HF01_CBCR_IN) +#define HWIO_GCC_TCU_MMNOC_QTB_HF01_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TCU_MMNOC_QTB_HF01_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TCU_MMNOC_QTB_HF01_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_TCU_MMNOC_QTB_HF01_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_TCU_MMNOC_QTB_HF01_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_TCU_MMNOC_QTB_HF01_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_TCU_MMNOC_QTB_HF01_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_TCU_MMNOC_QTB_HF01_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_TCU_MMNOC_QTB_HF01_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_TCU_MMNOC_QTB_HF01_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_TCU_MMNOC_QTB_HF01_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_TCU_MMNOC_QTB_HF01_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_TCU_MMNOC_QTB_HF01_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_TCU_MMNOC_QTB_HF01_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_TCU_MMNOC_QTB_HF01_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_TCU_MMNOC_QTB_HF01_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_TCU_MMNOC_QTB_HF01_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_TCU_MMNOC_QTB_HF01_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_TCU_MMNOC_QTB_HF01_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_TCU_MMNOC_QTB_HF01_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_TCU_MMNOC_QTB_HF01_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_TCU_MMNOC_QTB_HF01_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_TCU_MMNOC_QTB_HF01_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TCU_MMNOC_QTB_HF01_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TCU_MMNOC_QTB_HF23_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00073168) +#define HWIO_GCC_TCU_MMNOC_QTB_HF23_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00073168) +#define HWIO_GCC_TCU_MMNOC_QTB_HF23_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00073168) +#define HWIO_GCC_TCU_MMNOC_QTB_HF23_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_TCU_MMNOC_QTB_HF23_CBCR_ATTR 0x3 +#define HWIO_GCC_TCU_MMNOC_QTB_HF23_CBCR_IN \ + in_dword_masked(HWIO_GCC_TCU_MMNOC_QTB_HF23_CBCR_ADDR, HWIO_GCC_TCU_MMNOC_QTB_HF23_CBCR_RMSK) +#define HWIO_GCC_TCU_MMNOC_QTB_HF23_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_TCU_MMNOC_QTB_HF23_CBCR_ADDR, m) +#define HWIO_GCC_TCU_MMNOC_QTB_HF23_CBCR_OUT(v) \ + out_dword(HWIO_GCC_TCU_MMNOC_QTB_HF23_CBCR_ADDR,v) +#define HWIO_GCC_TCU_MMNOC_QTB_HF23_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TCU_MMNOC_QTB_HF23_CBCR_ADDR,m,v,HWIO_GCC_TCU_MMNOC_QTB_HF23_CBCR_IN) +#define HWIO_GCC_TCU_MMNOC_QTB_HF23_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TCU_MMNOC_QTB_HF23_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TCU_MMNOC_QTB_HF23_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_TCU_MMNOC_QTB_HF23_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_TCU_MMNOC_QTB_HF23_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_TCU_MMNOC_QTB_HF23_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_TCU_MMNOC_QTB_HF23_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_TCU_MMNOC_QTB_HF23_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_TCU_MMNOC_QTB_HF23_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_TCU_MMNOC_QTB_HF23_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_TCU_MMNOC_QTB_HF23_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_TCU_MMNOC_QTB_HF23_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_TCU_MMNOC_QTB_HF23_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_TCU_MMNOC_QTB_HF23_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_TCU_MMNOC_QTB_HF23_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_TCU_MMNOC_QTB_HF23_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_TCU_MMNOC_QTB_HF23_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_TCU_MMNOC_QTB_HF23_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_TCU_MMNOC_QTB_HF23_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_TCU_MMNOC_QTB_HF23_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_TCU_MMNOC_QTB_HF23_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_TCU_MMNOC_QTB_HF23_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_TCU_MMNOC_QTB_HF23_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TCU_MMNOC_QTB_HF23_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_MMNOC_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00073180) +#define HWIO_GCC_RPMH_MMNOC_CMD_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00073180) +#define HWIO_GCC_RPMH_MMNOC_CMD_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00073180) +#define HWIO_GCC_RPMH_MMNOC_CMD_DFSR_RMSK 0x1ffff +#define HWIO_GCC_RPMH_MMNOC_CMD_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_MMNOC_CMD_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_CMD_DFSR_ADDR, HWIO_GCC_RPMH_MMNOC_CMD_DFSR_RMSK) +#define HWIO_GCC_RPMH_MMNOC_CMD_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_CMD_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_MMNOC_CMD_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_MMNOC_CMD_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_MMNOC_CMD_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_CMD_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_CMD_DFSR_IN) +#define HWIO_GCC_RPMH_MMNOC_CMD_DFSR_RCG_SW_CTRL_BMSK 0x18000 +#define HWIO_GCC_RPMH_MMNOC_CMD_DFSR_RCG_SW_CTRL_SHFT 0xf +#define HWIO_GCC_RPMH_MMNOC_CMD_DFSR_SW_PERF_STATE_BMSK 0x7800 +#define HWIO_GCC_RPMH_MMNOC_CMD_DFSR_SW_PERF_STATE_SHFT 0xb +#define HWIO_GCC_RPMH_MMNOC_CMD_DFSR_SW_OVERRIDE_BMSK 0x400 +#define HWIO_GCC_RPMH_MMNOC_CMD_DFSR_SW_OVERRIDE_SHFT 0xa +#define HWIO_GCC_RPMH_MMNOC_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK 0x200 +#define HWIO_GCC_RPMH_MMNOC_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT 0x9 +#define HWIO_GCC_RPMH_MMNOC_CMD_DFSR_DFS_FSM_STATE_BMSK 0x1c0 +#define HWIO_GCC_RPMH_MMNOC_CMD_DFSR_DFS_FSM_STATE_SHFT 0x6 +#define HWIO_GCC_RPMH_MMNOC_CMD_DFSR_HW_CLK_CONTROL_BMSK 0x20 +#define HWIO_GCC_RPMH_MMNOC_CMD_DFSR_HW_CLK_CONTROL_SHFT 0x5 +#define HWIO_GCC_RPMH_MMNOC_CMD_DFSR_CURR_PERF_STATE_BMSK 0x1e +#define HWIO_GCC_RPMH_MMNOC_CMD_DFSR_CURR_PERF_STATE_SHFT 0x1 +#define HWIO_GCC_RPMH_MMNOC_CMD_DFSR_DFS_EN_BMSK 0x1 +#define HWIO_GCC_RPMH_MMNOC_CMD_DFSR_DFS_EN_SHFT 0x0 +#define HWIO_GCC_RPMH_MMNOC_CMD_DFSR_DFS_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_CMD_DFSR_DFS_EN_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00073188) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00073188) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00073188) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_ADDR, HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_RMSK) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_IN) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007318c) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007318c) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007318c) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_ADDR, HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_RMSK) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_IN) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00073190) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00073190) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00073190) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_ADDR, HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_RMSK) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_IN) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00073194) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00073194) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00073194) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_ADDR, HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_RMSK) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_IN) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00073198) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00073198) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00073198) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_ADDR, HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_RMSK) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_IN) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007319c) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007319c) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007319c) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_ADDR, HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_RMSK) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_IN) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000731a0) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000731a0) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000731a0) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_ADDR, HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_RMSK) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_IN) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000731a4) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000731a4) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000731a4) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_ADDR, HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_RMSK) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_IN) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000731a8) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000731a8) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000731a8) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_ADDR, HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_RMSK) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_IN) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000731ac) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000731ac) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000731ac) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_ADDR, HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_RMSK) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_IN) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000731b0) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000731b0) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000731b0) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_ADDR, HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_RMSK) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_IN) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000731b4) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000731b4) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000731b4) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_ADDR, HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_RMSK) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_IN) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000731b8) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000731b8) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000731b8) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_ADDR, HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_RMSK) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_IN) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000731bc) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000731bc) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000731bc) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_ADDR, HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_RMSK) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_IN) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000731c0) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000731c0) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000731c0) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_ADDR, HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_RMSK) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_IN) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000731c4) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000731c4) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000731c4) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_ADDR, HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_RMSK) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_IN) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_MMNOC_HF_QX_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007316c) +#define HWIO_GCC_MMNOC_HF_QX_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007316c) +#define HWIO_GCC_MMNOC_HF_QX_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007316c) +#define HWIO_GCC_MMNOC_HF_QX_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_MMNOC_HF_QX_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_MMNOC_HF_QX_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_MMNOC_HF_QX_CMD_RCGR_ADDR, HWIO_GCC_MMNOC_HF_QX_CMD_RCGR_RMSK) +#define HWIO_GCC_MMNOC_HF_QX_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_MMNOC_HF_QX_CMD_RCGR_ADDR, m) +#define HWIO_GCC_MMNOC_HF_QX_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_MMNOC_HF_QX_CMD_RCGR_ADDR,v) +#define HWIO_GCC_MMNOC_HF_QX_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MMNOC_HF_QX_CMD_RCGR_ADDR,m,v,HWIO_GCC_MMNOC_HF_QX_CMD_RCGR_IN) +#define HWIO_GCC_MMNOC_HF_QX_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_MMNOC_HF_QX_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_MMNOC_HF_QX_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_MMNOC_HF_QX_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_MMNOC_HF_QX_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_MMNOC_HF_QX_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_MMNOC_HF_QX_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMNOC_HF_QX_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMNOC_HF_QX_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_MMNOC_HF_QX_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_MMNOC_HF_QX_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMNOC_HF_QX_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00073170) +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00073170) +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00073170) +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_ADDR, HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_RMSK) +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_ADDR, m) +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_ADDR,v) +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_ADDR,m,v,HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_IN) +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_MMNOC_HF_QX_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00073298) +#define HWIO_GCC_MMNOC_HF_QX_DCD_CDIV_DCDR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00073298) +#define HWIO_GCC_MMNOC_HF_QX_DCD_CDIV_DCDR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00073298) +#define HWIO_GCC_MMNOC_HF_QX_DCD_CDIV_DCDR_RMSK 0x1 +#define HWIO_GCC_MMNOC_HF_QX_DCD_CDIV_DCDR_ATTR 0x3 +#define HWIO_GCC_MMNOC_HF_QX_DCD_CDIV_DCDR_IN \ + in_dword_masked(HWIO_GCC_MMNOC_HF_QX_DCD_CDIV_DCDR_ADDR, HWIO_GCC_MMNOC_HF_QX_DCD_CDIV_DCDR_RMSK) +#define HWIO_GCC_MMNOC_HF_QX_DCD_CDIV_DCDR_INM(m) \ + in_dword_masked(HWIO_GCC_MMNOC_HF_QX_DCD_CDIV_DCDR_ADDR, m) +#define HWIO_GCC_MMNOC_HF_QX_DCD_CDIV_DCDR_OUT(v) \ + out_dword(HWIO_GCC_MMNOC_HF_QX_DCD_CDIV_DCDR_ADDR,v) +#define HWIO_GCC_MMNOC_HF_QX_DCD_CDIV_DCDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MMNOC_HF_QX_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_MMNOC_HF_QX_DCD_CDIV_DCDR_IN) +#define HWIO_GCC_MMNOC_HF_QX_DCD_CDIV_DCDR_DCD_ENABLE_BMSK 0x1 +#define HWIO_GCC_MMNOC_HF_QX_DCD_CDIV_DCDR_DCD_ENABLE_SHFT 0x0 +#define HWIO_GCC_MMNOC_HF_QX_DCD_CDIV_DCDR_DCD_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMNOC_HF_QX_DCD_CDIV_DCDR_DCD_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000732b8) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000732b8) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000732b8) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_ADDR, HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_RMSK) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_IN) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000732bc) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000732bc) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000732bc) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_ADDR, HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_RMSK) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_IN) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000732c0) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000732c0) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000732c0) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_ADDR, HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_RMSK) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_IN) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000732c4) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000732c4) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000732c4) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_ADDR, HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_RMSK) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_IN) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000732c8) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000732c8) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000732c8) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_ADDR, HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_RMSK) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_IN) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000732cc) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000732cc) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000732cc) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_ADDR, HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_RMSK) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_IN) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000732d0) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000732d0) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000732d0) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_ADDR, HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_RMSK) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_IN) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000732d4) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000732d4) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000732d4) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_ADDR, HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_RMSK) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_IN) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000732d8) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000732d8) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000732d8) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_ADDR, HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_RMSK) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_IN) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000732dc) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000732dc) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000732dc) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_ADDR, HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_RMSK) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_IN) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000732e0) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000732e0) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000732e0) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_ADDR, HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_RMSK) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_IN) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000732e4) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000732e4) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000732e4) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_ADDR, HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_RMSK) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_IN) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000732e8) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000732e8) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000732e8) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_ADDR, HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_RMSK) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_IN) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000732ec) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000732ec) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000732ec) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_ADDR, HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_RMSK) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_IN) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000732f0) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000732f0) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000732f0) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_ADDR, HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_RMSK) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_IN) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000732f4) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000732f4) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000732f4) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_ADDR, HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_RMSK) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_IN) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_MMNOC_SF_QX_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007329c) +#define HWIO_GCC_MMNOC_SF_QX_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007329c) +#define HWIO_GCC_MMNOC_SF_QX_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007329c) +#define HWIO_GCC_MMNOC_SF_QX_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_MMNOC_SF_QX_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_MMNOC_SF_QX_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_MMNOC_SF_QX_CMD_RCGR_ADDR, HWIO_GCC_MMNOC_SF_QX_CMD_RCGR_RMSK) +#define HWIO_GCC_MMNOC_SF_QX_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_MMNOC_SF_QX_CMD_RCGR_ADDR, m) +#define HWIO_GCC_MMNOC_SF_QX_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_MMNOC_SF_QX_CMD_RCGR_ADDR,v) +#define HWIO_GCC_MMNOC_SF_QX_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MMNOC_SF_QX_CMD_RCGR_ADDR,m,v,HWIO_GCC_MMNOC_SF_QX_CMD_RCGR_IN) +#define HWIO_GCC_MMNOC_SF_QX_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_MMNOC_SF_QX_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_MMNOC_SF_QX_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_MMNOC_SF_QX_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_MMNOC_SF_QX_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_MMNOC_SF_QX_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_MMNOC_SF_QX_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMNOC_SF_QX_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMNOC_SF_QX_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_MMNOC_SF_QX_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_MMNOC_SF_QX_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMNOC_SF_QX_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000732a0) +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000732a0) +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000732a0) +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_ADDR, HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_RMSK) +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_ADDR, m) +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_ADDR,v) +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_ADDR,m,v,HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_IN) +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_MMNOC_SF_QX_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000733c8) +#define HWIO_GCC_MMNOC_SF_QX_DCD_CDIV_DCDR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000733c8) +#define HWIO_GCC_MMNOC_SF_QX_DCD_CDIV_DCDR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000733c8) +#define HWIO_GCC_MMNOC_SF_QX_DCD_CDIV_DCDR_RMSK 0x1 +#define HWIO_GCC_MMNOC_SF_QX_DCD_CDIV_DCDR_ATTR 0x3 +#define HWIO_GCC_MMNOC_SF_QX_DCD_CDIV_DCDR_IN \ + in_dword_masked(HWIO_GCC_MMNOC_SF_QX_DCD_CDIV_DCDR_ADDR, HWIO_GCC_MMNOC_SF_QX_DCD_CDIV_DCDR_RMSK) +#define HWIO_GCC_MMNOC_SF_QX_DCD_CDIV_DCDR_INM(m) \ + in_dword_masked(HWIO_GCC_MMNOC_SF_QX_DCD_CDIV_DCDR_ADDR, m) +#define HWIO_GCC_MMNOC_SF_QX_DCD_CDIV_DCDR_OUT(v) \ + out_dword(HWIO_GCC_MMNOC_SF_QX_DCD_CDIV_DCDR_ADDR,v) +#define HWIO_GCC_MMNOC_SF_QX_DCD_CDIV_DCDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MMNOC_SF_QX_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_MMNOC_SF_QX_DCD_CDIV_DCDR_IN) +#define HWIO_GCC_MMNOC_SF_QX_DCD_CDIV_DCDR_DCD_ENABLE_BMSK 0x1 +#define HWIO_GCC_MMNOC_SF_QX_DCD_CDIV_DCDR_DCD_ENABLE_SHFT 0x0 +#define HWIO_GCC_MMNOC_SF_QX_DCD_CDIV_DCDR_DCD_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMNOC_SF_QX_DCD_CDIV_DCDR_DCD_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TCU_ANOC_PCIE_QTB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000048) +#define HWIO_GCC_TCU_ANOC_PCIE_QTB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000048) +#define HWIO_GCC_TCU_ANOC_PCIE_QTB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000048) +#define HWIO_GCC_TCU_ANOC_PCIE_QTB_CBCR_RMSK 0x81d0000e +#define HWIO_GCC_TCU_ANOC_PCIE_QTB_CBCR_ATTR 0x3 +#define HWIO_GCC_TCU_ANOC_PCIE_QTB_CBCR_IN \ + in_dword_masked(HWIO_GCC_TCU_ANOC_PCIE_QTB_CBCR_ADDR, HWIO_GCC_TCU_ANOC_PCIE_QTB_CBCR_RMSK) +#define HWIO_GCC_TCU_ANOC_PCIE_QTB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_TCU_ANOC_PCIE_QTB_CBCR_ADDR, m) +#define HWIO_GCC_TCU_ANOC_PCIE_QTB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_TCU_ANOC_PCIE_QTB_CBCR_ADDR,v) +#define HWIO_GCC_TCU_ANOC_PCIE_QTB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TCU_ANOC_PCIE_QTB_CBCR_ADDR,m,v,HWIO_GCC_TCU_ANOC_PCIE_QTB_CBCR_IN) +#define HWIO_GCC_TCU_ANOC_PCIE_QTB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TCU_ANOC_PCIE_QTB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TCU_ANOC_PCIE_QTB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_TCU_ANOC_PCIE_QTB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_TCU_ANOC_PCIE_QTB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_TCU_ANOC_PCIE_QTB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_TCU_ANOC_PCIE_QTB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_TCU_ANOC_PCIE_QTB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_TCU_ANOC_PCIE_QTB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_TCU_ANOC_PCIE_QTB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_TCU_ANOC_PCIE_QTB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_TCU_ANOC_PCIE_QTB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_TCU_ANOC_PCIE_QTB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_TCU_ANOC_PCIE_QTB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_TCU_ANOC_PCIE_QTB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_TCU_ANOC_PCIE_QTB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_TCU_ANOC_PCIE_QTB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_TCU_ANOC_PCIE_QTB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_TCU_ANOC_PCIE_QTB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_TCU_ANOC_PCIE_QTB_CBCR_HW_CTL_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TCU_TURING_Q6_QTB0_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008d038) +#define HWIO_GCC_TCU_TURING_Q6_QTB0_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008d038) +#define HWIO_GCC_TCU_TURING_Q6_QTB0_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008d038) +#define HWIO_GCC_TCU_TURING_Q6_QTB0_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_TCU_TURING_Q6_QTB0_CBCR_ATTR 0x3 +#define HWIO_GCC_TCU_TURING_Q6_QTB0_CBCR_IN \ + in_dword_masked(HWIO_GCC_TCU_TURING_Q6_QTB0_CBCR_ADDR, HWIO_GCC_TCU_TURING_Q6_QTB0_CBCR_RMSK) +#define HWIO_GCC_TCU_TURING_Q6_QTB0_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_TCU_TURING_Q6_QTB0_CBCR_ADDR, m) +#define HWIO_GCC_TCU_TURING_Q6_QTB0_CBCR_OUT(v) \ + out_dword(HWIO_GCC_TCU_TURING_Q6_QTB0_CBCR_ADDR,v) +#define HWIO_GCC_TCU_TURING_Q6_QTB0_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TCU_TURING_Q6_QTB0_CBCR_ADDR,m,v,HWIO_GCC_TCU_TURING_Q6_QTB0_CBCR_IN) +#define HWIO_GCC_TCU_TURING_Q6_QTB0_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TCU_TURING_Q6_QTB0_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TCU_TURING_Q6_QTB0_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_TCU_TURING_Q6_QTB0_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_TCU_TURING_Q6_QTB0_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_TCU_TURING_Q6_QTB0_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_TCU_TURING_Q6_QTB0_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_TCU_TURING_Q6_QTB0_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_TCU_TURING_Q6_QTB0_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_TCU_TURING_Q6_QTB0_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_TCU_TURING_Q6_QTB0_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_TCU_TURING_Q6_QTB0_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_TCU_TURING_Q6_QTB0_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_TCU_TURING_Q6_QTB0_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_TCU_TURING_Q6_QTB0_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_TCU_TURING_Q6_QTB0_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_TCU_TURING_Q6_QTB0_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_TCU_TURING_Q6_QTB0_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_TCU_TURING_Q6_QTB0_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_TCU_TURING_Q6_QTB0_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_TCU_TURING_Q6_QTB0_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_TCU_TURING_Q6_QTB0_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_TCU_TURING_Q6_QTB0_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TCU_TURING_Q6_QTB0_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TCU_LPASS_AUDIO_QTB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00089038) +#define HWIO_GCC_TCU_LPASS_AUDIO_QTB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00089038) +#define HWIO_GCC_TCU_LPASS_AUDIO_QTB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00089038) +#define HWIO_GCC_TCU_LPASS_AUDIO_QTB_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_TCU_LPASS_AUDIO_QTB_CBCR_ATTR 0x3 +#define HWIO_GCC_TCU_LPASS_AUDIO_QTB_CBCR_IN \ + in_dword_masked(HWIO_GCC_TCU_LPASS_AUDIO_QTB_CBCR_ADDR, HWIO_GCC_TCU_LPASS_AUDIO_QTB_CBCR_RMSK) +#define HWIO_GCC_TCU_LPASS_AUDIO_QTB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_TCU_LPASS_AUDIO_QTB_CBCR_ADDR, m) +#define HWIO_GCC_TCU_LPASS_AUDIO_QTB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_TCU_LPASS_AUDIO_QTB_CBCR_ADDR,v) +#define HWIO_GCC_TCU_LPASS_AUDIO_QTB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TCU_LPASS_AUDIO_QTB_CBCR_ADDR,m,v,HWIO_GCC_TCU_LPASS_AUDIO_QTB_CBCR_IN) +#define HWIO_GCC_TCU_LPASS_AUDIO_QTB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TCU_LPASS_AUDIO_QTB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TCU_LPASS_AUDIO_QTB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_TCU_LPASS_AUDIO_QTB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_TCU_LPASS_AUDIO_QTB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_TCU_LPASS_AUDIO_QTB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_TCU_LPASS_AUDIO_QTB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_TCU_LPASS_AUDIO_QTB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_TCU_LPASS_AUDIO_QTB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_TCU_LPASS_AUDIO_QTB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_TCU_LPASS_AUDIO_QTB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_TCU_LPASS_AUDIO_QTB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_TCU_LPASS_AUDIO_QTB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_TCU_LPASS_AUDIO_QTB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_TCU_LPASS_AUDIO_QTB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_TCU_LPASS_AUDIO_QTB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_TCU_LPASS_AUDIO_QTB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_TCU_LPASS_AUDIO_QTB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_TCU_LPASS_AUDIO_QTB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_TCU_LPASS_AUDIO_QTB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_TCU_LPASS_AUDIO_QTB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_TCU_LPASS_AUDIO_QTB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_TCU_LPASS_AUDIO_QTB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TCU_LPASS_AUDIO_QTB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_ANOC_PCIE_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000000) +#define HWIO_GCC_ANOC_PCIE_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000000) +#define HWIO_GCC_ANOC_PCIE_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000000) +#define HWIO_GCC_ANOC_PCIE_BCR_RMSK 0x1 +#define HWIO_GCC_ANOC_PCIE_BCR_ATTR 0x3 +#define HWIO_GCC_ANOC_PCIE_BCR_IN \ + in_dword_masked(HWIO_GCC_ANOC_PCIE_BCR_ADDR, HWIO_GCC_ANOC_PCIE_BCR_RMSK) +#define HWIO_GCC_ANOC_PCIE_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_ANOC_PCIE_BCR_ADDR, m) +#define HWIO_GCC_ANOC_PCIE_BCR_OUT(v) \ + out_dword(HWIO_GCC_ANOC_PCIE_BCR_ADDR,v) +#define HWIO_GCC_ANOC_PCIE_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ANOC_PCIE_BCR_ADDR,m,v,HWIO_GCC_ANOC_PCIE_BCR_IN) +#define HWIO_GCC_ANOC_PCIE_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_ANOC_PCIE_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_ANOC_PCIE_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_ANOC_PCIE_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_ANOC_PCIE_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000004) +#define HWIO_GCC_ANOC_PCIE_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000004) +#define HWIO_GCC_ANOC_PCIE_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000004) +#define HWIO_GCC_ANOC_PCIE_GDSCR_RMSK 0xf8ffffff +#define HWIO_GCC_ANOC_PCIE_GDSCR_ATTR 0x3 +#define HWIO_GCC_ANOC_PCIE_GDSCR_IN \ + in_dword_masked(HWIO_GCC_ANOC_PCIE_GDSCR_ADDR, HWIO_GCC_ANOC_PCIE_GDSCR_RMSK) +#define HWIO_GCC_ANOC_PCIE_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_ANOC_PCIE_GDSCR_ADDR, m) +#define HWIO_GCC_ANOC_PCIE_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_ANOC_PCIE_GDSCR_ADDR,v) +#define HWIO_GCC_ANOC_PCIE_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ANOC_PCIE_GDSCR_ADDR,m,v,HWIO_GCC_ANOC_PCIE_GDSCR_IN) +#define HWIO_GCC_ANOC_PCIE_GDSCR_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_ANOC_PCIE_GDSCR_PWR_ON_SHFT 0x1f +#define HWIO_GCC_ANOC_PCIE_GDSCR_GDSC_STATE_BMSK 0x78000000 +#define HWIO_GCC_ANOC_PCIE_GDSCR_GDSC_STATE_SHFT 0x1b +#define HWIO_GCC_ANOC_PCIE_GDSCR_EN_REST_WAIT_BMSK 0xf00000 +#define HWIO_GCC_ANOC_PCIE_GDSCR_EN_REST_WAIT_SHFT 0x14 +#define HWIO_GCC_ANOC_PCIE_GDSCR_EN_FEW_WAIT_BMSK 0xf0000 +#define HWIO_GCC_ANOC_PCIE_GDSCR_EN_FEW_WAIT_SHFT 0x10 +#define HWIO_GCC_ANOC_PCIE_GDSCR_CLK_DIS_WAIT_BMSK 0xf000 +#define HWIO_GCC_ANOC_PCIE_GDSCR_CLK_DIS_WAIT_SHFT 0xc +#define HWIO_GCC_ANOC_PCIE_GDSCR_RETAIN_FF_ENABLE_BMSK 0x800 +#define HWIO_GCC_ANOC_PCIE_GDSCR_RETAIN_FF_ENABLE_SHFT 0xb +#define HWIO_GCC_ANOC_PCIE_GDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_ANOC_PCIE_GDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_ANOC_PCIE_GDSCR_RESTORE_BMSK 0x400 +#define HWIO_GCC_ANOC_PCIE_GDSCR_RESTORE_SHFT 0xa +#define HWIO_GCC_ANOC_PCIE_GDSCR_RESTORE_DISABLE_FVAL 0x0 +#define HWIO_GCC_ANOC_PCIE_GDSCR_RESTORE_ENABLE_FVAL 0x1 +#define HWIO_GCC_ANOC_PCIE_GDSCR_SAVE_BMSK 0x200 +#define HWIO_GCC_ANOC_PCIE_GDSCR_SAVE_SHFT 0x9 +#define HWIO_GCC_ANOC_PCIE_GDSCR_SAVE_DISABLE_FVAL 0x0 +#define HWIO_GCC_ANOC_PCIE_GDSCR_SAVE_ENABLE_FVAL 0x1 +#define HWIO_GCC_ANOC_PCIE_GDSCR_RETAIN_BMSK 0x100 +#define HWIO_GCC_ANOC_PCIE_GDSCR_RETAIN_SHFT 0x8 +#define HWIO_GCC_ANOC_PCIE_GDSCR_RETAIN_DISABLE_FVAL 0x0 +#define HWIO_GCC_ANOC_PCIE_GDSCR_RETAIN_ENABLE_FVAL 0x1 +#define HWIO_GCC_ANOC_PCIE_GDSCR_EN_REST_BMSK 0x80 +#define HWIO_GCC_ANOC_PCIE_GDSCR_EN_REST_SHFT 0x7 +#define HWIO_GCC_ANOC_PCIE_GDSCR_EN_REST_DISABLE_FVAL 0x0 +#define HWIO_GCC_ANOC_PCIE_GDSCR_EN_REST_ENABLE_FVAL 0x1 +#define HWIO_GCC_ANOC_PCIE_GDSCR_EN_FEW_BMSK 0x40 +#define HWIO_GCC_ANOC_PCIE_GDSCR_EN_FEW_SHFT 0x6 +#define HWIO_GCC_ANOC_PCIE_GDSCR_EN_FEW_DISABLE_FVAL 0x0 +#define HWIO_GCC_ANOC_PCIE_GDSCR_EN_FEW_ENABLE_FVAL 0x1 +#define HWIO_GCC_ANOC_PCIE_GDSCR_CLAMP_IO_BMSK 0x20 +#define HWIO_GCC_ANOC_PCIE_GDSCR_CLAMP_IO_SHFT 0x5 +#define HWIO_GCC_ANOC_PCIE_GDSCR_CLAMP_IO_DISABLE_FVAL 0x0 +#define HWIO_GCC_ANOC_PCIE_GDSCR_CLAMP_IO_ENABLE_FVAL 0x1 +#define HWIO_GCC_ANOC_PCIE_GDSCR_CLK_DISABLE_BMSK 0x10 +#define HWIO_GCC_ANOC_PCIE_GDSCR_CLK_DISABLE_SHFT 0x4 +#define HWIO_GCC_ANOC_PCIE_GDSCR_CLK_DISABLE_CLK_NOT_DISABLE_FVAL 0x0 +#define HWIO_GCC_ANOC_PCIE_GDSCR_CLK_DISABLE_CLK_IS_DISABLE_FVAL 0x1 +#define HWIO_GCC_ANOC_PCIE_GDSCR_PD_ARES_BMSK 0x8 +#define HWIO_GCC_ANOC_PCIE_GDSCR_PD_ARES_SHFT 0x3 +#define HWIO_GCC_ANOC_PCIE_GDSCR_PD_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_ANOC_PCIE_GDSCR_PD_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_ANOC_PCIE_GDSCR_SW_OVERRIDE_BMSK 0x4 +#define HWIO_GCC_ANOC_PCIE_GDSCR_SW_OVERRIDE_SHFT 0x2 +#define HWIO_GCC_ANOC_PCIE_GDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_ANOC_PCIE_GDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 +#define HWIO_GCC_ANOC_PCIE_GDSCR_HW_CONTROL_BMSK 0x2 +#define HWIO_GCC_ANOC_PCIE_GDSCR_HW_CONTROL_SHFT 0x1 +#define HWIO_GCC_ANOC_PCIE_GDSCR_HW_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_ANOC_PCIE_GDSCR_HW_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_ANOC_PCIE_GDSCR_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_ANOC_PCIE_GDSCR_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_ANOC_PCIE_GDSCR_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_ANOC_PCIE_GDSCR_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_ANOC_PCIE_CFG_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000008) +#define HWIO_GCC_ANOC_PCIE_CFG_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000008) +#define HWIO_GCC_ANOC_PCIE_CFG_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000008) +#define HWIO_GCC_ANOC_PCIE_CFG_GDSCR_RMSK 0x7ffffff +#define HWIO_GCC_ANOC_PCIE_CFG_GDSCR_ATTR 0x3 +#define HWIO_GCC_ANOC_PCIE_CFG_GDSCR_IN \ + in_dword_masked(HWIO_GCC_ANOC_PCIE_CFG_GDSCR_ADDR, HWIO_GCC_ANOC_PCIE_CFG_GDSCR_RMSK) +#define HWIO_GCC_ANOC_PCIE_CFG_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_ANOC_PCIE_CFG_GDSCR_ADDR, m) +#define HWIO_GCC_ANOC_PCIE_CFG_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_ANOC_PCIE_CFG_GDSCR_ADDR,v) +#define HWIO_GCC_ANOC_PCIE_CFG_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ANOC_PCIE_CFG_GDSCR_ADDR,m,v,HWIO_GCC_ANOC_PCIE_CFG_GDSCR_IN) +#define HWIO_GCC_ANOC_PCIE_CFG_GDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4000000 +#define HWIO_GCC_ANOC_PCIE_CFG_GDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x1a +#define HWIO_GCC_ANOC_PCIE_CFG_GDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_ANOC_PCIE_CFG_GDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_ANOC_PCIE_CFG_GDSCR_GDSC_PWR_DWN_START_BMSK 0x2000000 +#define HWIO_GCC_ANOC_PCIE_CFG_GDSCR_GDSC_PWR_DWN_START_SHFT 0x19 +#define HWIO_GCC_ANOC_PCIE_CFG_GDSCR_GDSC_PWR_UP_START_BMSK 0x1000000 +#define HWIO_GCC_ANOC_PCIE_CFG_GDSCR_GDSC_PWR_UP_START_SHFT 0x18 +#define HWIO_GCC_ANOC_PCIE_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_BMSK 0xf00000 +#define HWIO_GCC_ANOC_PCIE_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_SHFT 0x14 +#define HWIO_GCC_ANOC_PCIE_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_BMSK 0x80000 +#define HWIO_GCC_ANOC_PCIE_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_SHFT 0x13 +#define HWIO_GCC_ANOC_PCIE_CFG_GDSCR_GDSC_ENR_ACK_STATUS_BMSK 0x40000 +#define HWIO_GCC_ANOC_PCIE_CFG_GDSCR_GDSC_ENR_ACK_STATUS_SHFT 0x12 +#define HWIO_GCC_ANOC_PCIE_CFG_GDSCR_GDSC_ENF_ACK_STATUS_BMSK 0x20000 +#define HWIO_GCC_ANOC_PCIE_CFG_GDSCR_GDSC_ENF_ACK_STATUS_SHFT 0x11 +#define HWIO_GCC_ANOC_PCIE_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_BMSK 0x10000 +#define HWIO_GCC_ANOC_PCIE_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_SHFT 0x10 +#define HWIO_GCC_ANOC_PCIE_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_BMSK 0x8000 +#define HWIO_GCC_ANOC_PCIE_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_SHFT 0xf +#define HWIO_GCC_ANOC_PCIE_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_BMSK 0x7800 +#define HWIO_GCC_ANOC_PCIE_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_SHFT 0xb +#define HWIO_GCC_ANOC_PCIE_CFG_GDSCR_GDSC_HANDSHAKE_DIS_BMSK 0x400 +#define HWIO_GCC_ANOC_PCIE_CFG_GDSCR_GDSC_HANDSHAKE_DIS_SHFT 0xa +#define HWIO_GCC_ANOC_PCIE_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_BMSK 0x200 +#define HWIO_GCC_ANOC_PCIE_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_SHFT 0x9 +#define HWIO_GCC_ANOC_PCIE_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_BMSK 0x100 +#define HWIO_GCC_ANOC_PCIE_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_SHFT 0x8 +#define HWIO_GCC_ANOC_PCIE_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_BMSK 0x80 +#define HWIO_GCC_ANOC_PCIE_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_SHFT 0x7 +#define HWIO_GCC_ANOC_PCIE_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_BMSK 0x60 +#define HWIO_GCC_ANOC_PCIE_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_SHFT 0x5 +#define HWIO_GCC_ANOC_PCIE_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_BMSK 0x10 +#define HWIO_GCC_ANOC_PCIE_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_SHFT 0x4 +#define HWIO_GCC_ANOC_PCIE_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_BMSK 0x8 +#define HWIO_GCC_ANOC_PCIE_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_SHFT 0x3 +#define HWIO_GCC_ANOC_PCIE_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_BMSK 0x4 +#define HWIO_GCC_ANOC_PCIE_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_SHFT 0x2 +#define HWIO_GCC_ANOC_PCIE_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_BMSK 0x2 +#define HWIO_GCC_ANOC_PCIE_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_SHFT 0x1 +#define HWIO_GCC_ANOC_PCIE_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_ANOC_PCIE_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_SHFT 0x0 + +#define HWIO_GCC_ANOC_PCIE_CFG2_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000000c) +#define HWIO_GCC_ANOC_PCIE_CFG2_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000000c) +#define HWIO_GCC_ANOC_PCIE_CFG2_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000000c) +#define HWIO_GCC_ANOC_PCIE_CFG2_GDSCR_RMSK 0x7ffff +#define HWIO_GCC_ANOC_PCIE_CFG2_GDSCR_ATTR 0x3 +#define HWIO_GCC_ANOC_PCIE_CFG2_GDSCR_IN \ + in_dword_masked(HWIO_GCC_ANOC_PCIE_CFG2_GDSCR_ADDR, HWIO_GCC_ANOC_PCIE_CFG2_GDSCR_RMSK) +#define HWIO_GCC_ANOC_PCIE_CFG2_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_ANOC_PCIE_CFG2_GDSCR_ADDR, m) +#define HWIO_GCC_ANOC_PCIE_CFG2_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_ANOC_PCIE_CFG2_GDSCR_ADDR,v) +#define HWIO_GCC_ANOC_PCIE_CFG2_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ANOC_PCIE_CFG2_GDSCR_ADDR,m,v,HWIO_GCC_ANOC_PCIE_CFG2_GDSCR_IN) +#define HWIO_GCC_ANOC_PCIE_CFG2_GDSCR_GDSC_MEM_PWRUP_ACK_OVERRIDE_BMSK 0x40000 +#define HWIO_GCC_ANOC_PCIE_CFG2_GDSCR_GDSC_MEM_PWRUP_ACK_OVERRIDE_SHFT 0x12 +#define HWIO_GCC_ANOC_PCIE_CFG2_GDSCR_GDSC_PWRDWN_ENABLE_ACK_OVERRIDE_BMSK 0x20000 +#define HWIO_GCC_ANOC_PCIE_CFG2_GDSCR_GDSC_PWRDWN_ENABLE_ACK_OVERRIDE_SHFT 0x11 +#define HWIO_GCC_ANOC_PCIE_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_BMSK 0x10000 +#define HWIO_GCC_ANOC_PCIE_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_SHFT 0x10 +#define HWIO_GCC_ANOC_PCIE_CFG2_GDSCR_DLY_MEM_PWR_UP_BMSK 0xf000 +#define HWIO_GCC_ANOC_PCIE_CFG2_GDSCR_DLY_MEM_PWR_UP_SHFT 0xc +#define HWIO_GCC_ANOC_PCIE_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_BMSK 0xf00 +#define HWIO_GCC_ANOC_PCIE_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_SHFT 0x8 +#define HWIO_GCC_ANOC_PCIE_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_BMSK 0xf0 +#define HWIO_GCC_ANOC_PCIE_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_SHFT 0x4 +#define HWIO_GCC_ANOC_PCIE_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_BMSK 0xf +#define HWIO_GCC_ANOC_PCIE_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_SHFT 0x0 + +#define HWIO_GCC_ANOC_PCIE_CFG3_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000010) +#define HWIO_GCC_ANOC_PCIE_CFG3_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000010) +#define HWIO_GCC_ANOC_PCIE_CFG3_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000010) +#define HWIO_GCC_ANOC_PCIE_CFG3_GDSCR_RMSK 0x7ffffff +#define HWIO_GCC_ANOC_PCIE_CFG3_GDSCR_ATTR 0x3 +#define HWIO_GCC_ANOC_PCIE_CFG3_GDSCR_IN \ + in_dword_masked(HWIO_GCC_ANOC_PCIE_CFG3_GDSCR_ADDR, HWIO_GCC_ANOC_PCIE_CFG3_GDSCR_RMSK) +#define HWIO_GCC_ANOC_PCIE_CFG3_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_ANOC_PCIE_CFG3_GDSCR_ADDR, m) +#define HWIO_GCC_ANOC_PCIE_CFG3_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_ANOC_PCIE_CFG3_GDSCR_ADDR,v) +#define HWIO_GCC_ANOC_PCIE_CFG3_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ANOC_PCIE_CFG3_GDSCR_ADDR,m,v,HWIO_GCC_ANOC_PCIE_CFG3_GDSCR_IN) +#define HWIO_GCC_ANOC_PCIE_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_STATUS_BMSK 0x4000000 +#define HWIO_GCC_ANOC_PCIE_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_STATUS_SHFT 0x1a +#define HWIO_GCC_ANOC_PCIE_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_BMSK 0x2000000 +#define HWIO_GCC_ANOC_PCIE_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_SHFT 0x19 +#define HWIO_GCC_ANOC_PCIE_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_ANOC_PCIE_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_ANOC_PCIE_CFG3_GDSCR_DLY_ACCU_RED_SHIFTER_DONE_BMSK 0x1e00000 +#define HWIO_GCC_ANOC_PCIE_CFG3_GDSCR_DLY_ACCU_RED_SHIFTER_DONE_SHFT 0x15 +#define HWIO_GCC_ANOC_PCIE_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_BMSK 0x100000 +#define HWIO_GCC_ANOC_PCIE_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_SHFT 0x14 +#define HWIO_GCC_ANOC_PCIE_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_DISABLE_FVAL 0x0 +#define HWIO_GCC_ANOC_PCIE_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_ENABLE_FVAL 0x1 +#define HWIO_GCC_ANOC_PCIE_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_BMSK 0x80000 +#define HWIO_GCC_ANOC_PCIE_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_SHFT 0x13 +#define HWIO_GCC_ANOC_PCIE_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_ANOC_PCIE_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_ENABLE_FVAL 0x1 +#define HWIO_GCC_ANOC_PCIE_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_BMSK 0x40000 +#define HWIO_GCC_ANOC_PCIE_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_SHFT 0x12 +#define HWIO_GCC_ANOC_PCIE_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_DISABLE_FVAL 0x0 +#define HWIO_GCC_ANOC_PCIE_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_ENABLE_FVAL 0x1 +#define HWIO_GCC_ANOC_PCIE_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_BMSK 0x20000 +#define HWIO_GCC_ANOC_PCIE_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_SHFT 0x11 +#define HWIO_GCC_ANOC_PCIE_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_DISABLE_FVAL 0x0 +#define HWIO_GCC_ANOC_PCIE_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_ENABLE_FVAL 0x1 +#define HWIO_GCC_ANOC_PCIE_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_BMSK 0x10000 +#define HWIO_GCC_ANOC_PCIE_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_SHFT 0x10 +#define HWIO_GCC_ANOC_PCIE_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_ANOC_PCIE_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_ENABLE_FVAL 0x1 +#define HWIO_GCC_ANOC_PCIE_CFG3_GDSCR_GDSC_SPARE_CTRL_IN_BMSK 0xff00 +#define HWIO_GCC_ANOC_PCIE_CFG3_GDSCR_GDSC_SPARE_CTRL_IN_SHFT 0x8 +#define HWIO_GCC_ANOC_PCIE_CFG3_GDSCR_GDSC_SPARE_CTRL_OUT_BMSK 0xff +#define HWIO_GCC_ANOC_PCIE_CFG3_GDSCR_GDSC_SPARE_CTRL_OUT_SHFT 0x0 + +#define HWIO_GCC_ANOC_PCIE_CFG4_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000014) +#define HWIO_GCC_ANOC_PCIE_CFG4_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000014) +#define HWIO_GCC_ANOC_PCIE_CFG4_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000014) +#define HWIO_GCC_ANOC_PCIE_CFG4_GDSCR_RMSK 0xffffff +#define HWIO_GCC_ANOC_PCIE_CFG4_GDSCR_ATTR 0x3 +#define HWIO_GCC_ANOC_PCIE_CFG4_GDSCR_IN \ + in_dword_masked(HWIO_GCC_ANOC_PCIE_CFG4_GDSCR_ADDR, HWIO_GCC_ANOC_PCIE_CFG4_GDSCR_RMSK) +#define HWIO_GCC_ANOC_PCIE_CFG4_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_ANOC_PCIE_CFG4_GDSCR_ADDR, m) +#define HWIO_GCC_ANOC_PCIE_CFG4_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_ANOC_PCIE_CFG4_GDSCR_ADDR,v) +#define HWIO_GCC_ANOC_PCIE_CFG4_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ANOC_PCIE_CFG4_GDSCR_ADDR,m,v,HWIO_GCC_ANOC_PCIE_CFG4_GDSCR_IN) +#define HWIO_GCC_ANOC_PCIE_CFG4_GDSCR_DLY_UNCLAMPIO_BMSK 0xf00000 +#define HWIO_GCC_ANOC_PCIE_CFG4_GDSCR_DLY_UNCLAMPIO_SHFT 0x14 +#define HWIO_GCC_ANOC_PCIE_CFG4_GDSCR_DLY_RESTOREFF_BMSK 0xf0000 +#define HWIO_GCC_ANOC_PCIE_CFG4_GDSCR_DLY_RESTOREFF_SHFT 0x10 +#define HWIO_GCC_ANOC_PCIE_CFG4_GDSCR_DLY_NORETAINFF_BMSK 0xf000 +#define HWIO_GCC_ANOC_PCIE_CFG4_GDSCR_DLY_NORETAINFF_SHFT 0xc +#define HWIO_GCC_ANOC_PCIE_CFG4_GDSCR_DLY_DEASSERTARES_BMSK 0xf00 +#define HWIO_GCC_ANOC_PCIE_CFG4_GDSCR_DLY_DEASSERTARES_SHFT 0x8 +#define HWIO_GCC_ANOC_PCIE_CFG4_GDSCR_DLY_CLAMPIO_BMSK 0xf0 +#define HWIO_GCC_ANOC_PCIE_CFG4_GDSCR_DLY_CLAMPIO_SHFT 0x4 +#define HWIO_GCC_ANOC_PCIE_CFG4_GDSCR_DLY_RETAINFF_BMSK 0xf +#define HWIO_GCC_ANOC_PCIE_CFG4_GDSCR_DLY_RETAINFF_SHFT 0x0 + +#define HWIO_GCC_ANOC_PCIE_NORTH_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000018) +#define HWIO_GCC_ANOC_PCIE_NORTH_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000018) +#define HWIO_GCC_ANOC_PCIE_NORTH_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000018) +#define HWIO_GCC_ANOC_PCIE_NORTH_AT_CBCR_RMSK 0x81d0000e +#define HWIO_GCC_ANOC_PCIE_NORTH_AT_CBCR_ATTR 0x3 +#define HWIO_GCC_ANOC_PCIE_NORTH_AT_CBCR_IN \ + in_dword_masked(HWIO_GCC_ANOC_PCIE_NORTH_AT_CBCR_ADDR, HWIO_GCC_ANOC_PCIE_NORTH_AT_CBCR_RMSK) +#define HWIO_GCC_ANOC_PCIE_NORTH_AT_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_ANOC_PCIE_NORTH_AT_CBCR_ADDR, m) +#define HWIO_GCC_ANOC_PCIE_NORTH_AT_CBCR_OUT(v) \ + out_dword(HWIO_GCC_ANOC_PCIE_NORTH_AT_CBCR_ADDR,v) +#define HWIO_GCC_ANOC_PCIE_NORTH_AT_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ANOC_PCIE_NORTH_AT_CBCR_ADDR,m,v,HWIO_GCC_ANOC_PCIE_NORTH_AT_CBCR_IN) +#define HWIO_GCC_ANOC_PCIE_NORTH_AT_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_ANOC_PCIE_NORTH_AT_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_ANOC_PCIE_NORTH_AT_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_ANOC_PCIE_NORTH_AT_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_ANOC_PCIE_NORTH_AT_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_ANOC_PCIE_NORTH_AT_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_ANOC_PCIE_NORTH_AT_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_ANOC_PCIE_NORTH_AT_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_ANOC_PCIE_NORTH_AT_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_ANOC_PCIE_NORTH_AT_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_ANOC_PCIE_NORTH_AT_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_ANOC_PCIE_NORTH_AT_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_ANOC_PCIE_NORTH_AT_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_ANOC_PCIE_NORTH_AT_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_ANOC_PCIE_NORTH_AT_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_ANOC_PCIE_NORTH_AT_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_ANOC_PCIE_NORTH_AT_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_ANOC_PCIE_NORTH_AT_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_ANOC_PCIE_NORTH_AT_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_ANOC_PCIE_NORTH_AT_CBCR_HW_CTL_ENABLE_FVAL 0x1 + +#define HWIO_GCC_ANOC_PCIE_TSCTR_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000001c) +#define HWIO_GCC_ANOC_PCIE_TSCTR_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000001c) +#define HWIO_GCC_ANOC_PCIE_TSCTR_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000001c) +#define HWIO_GCC_ANOC_PCIE_TSCTR_CBCR_RMSK 0x81c0000e +#define HWIO_GCC_ANOC_PCIE_TSCTR_CBCR_ATTR 0x3 +#define HWIO_GCC_ANOC_PCIE_TSCTR_CBCR_IN \ + in_dword_masked(HWIO_GCC_ANOC_PCIE_TSCTR_CBCR_ADDR, HWIO_GCC_ANOC_PCIE_TSCTR_CBCR_RMSK) +#define HWIO_GCC_ANOC_PCIE_TSCTR_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_ANOC_PCIE_TSCTR_CBCR_ADDR, m) +#define HWIO_GCC_ANOC_PCIE_TSCTR_CBCR_OUT(v) \ + out_dword(HWIO_GCC_ANOC_PCIE_TSCTR_CBCR_ADDR,v) +#define HWIO_GCC_ANOC_PCIE_TSCTR_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ANOC_PCIE_TSCTR_CBCR_ADDR,m,v,HWIO_GCC_ANOC_PCIE_TSCTR_CBCR_IN) +#define HWIO_GCC_ANOC_PCIE_TSCTR_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_ANOC_PCIE_TSCTR_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_ANOC_PCIE_TSCTR_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_ANOC_PCIE_TSCTR_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_ANOC_PCIE_TSCTR_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_ANOC_PCIE_TSCTR_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_ANOC_PCIE_TSCTR_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_ANOC_PCIE_TSCTR_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_ANOC_PCIE_TSCTR_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_ANOC_PCIE_TSCTR_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_ANOC_PCIE_TSCTR_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_ANOC_PCIE_TSCTR_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_ANOC_PCIE_TSCTR_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_ANOC_PCIE_TSCTR_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_ANOC_PCIE_TSCTR_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_ANOC_PCIE_TSCTR_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_ANOC_PCIE_TSCTR_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_ANOC_PCIE_TSCTR_CBCR_HW_CTL_ENABLE_FVAL 0x1 + +#define HWIO_GCC_ANOC_PCIE_QOSGEN_EXTREF_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000020) +#define HWIO_GCC_ANOC_PCIE_QOSGEN_EXTREF_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000020) +#define HWIO_GCC_ANOC_PCIE_QOSGEN_EXTREF_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000020) +#define HWIO_GCC_ANOC_PCIE_QOSGEN_EXTREF_CBCR_RMSK 0x81c00004 +#define HWIO_GCC_ANOC_PCIE_QOSGEN_EXTREF_CBCR_ATTR 0x3 +#define HWIO_GCC_ANOC_PCIE_QOSGEN_EXTREF_CBCR_IN \ + in_dword_masked(HWIO_GCC_ANOC_PCIE_QOSGEN_EXTREF_CBCR_ADDR, HWIO_GCC_ANOC_PCIE_QOSGEN_EXTREF_CBCR_RMSK) +#define HWIO_GCC_ANOC_PCIE_QOSGEN_EXTREF_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_ANOC_PCIE_QOSGEN_EXTREF_CBCR_ADDR, m) +#define HWIO_GCC_ANOC_PCIE_QOSGEN_EXTREF_CBCR_OUT(v) \ + out_dword(HWIO_GCC_ANOC_PCIE_QOSGEN_EXTREF_CBCR_ADDR,v) +#define HWIO_GCC_ANOC_PCIE_QOSGEN_EXTREF_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ANOC_PCIE_QOSGEN_EXTREF_CBCR_ADDR,m,v,HWIO_GCC_ANOC_PCIE_QOSGEN_EXTREF_CBCR_IN) +#define HWIO_GCC_ANOC_PCIE_QOSGEN_EXTREF_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_ANOC_PCIE_QOSGEN_EXTREF_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_ANOC_PCIE_QOSGEN_EXTREF_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_ANOC_PCIE_QOSGEN_EXTREF_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_ANOC_PCIE_QOSGEN_EXTREF_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_ANOC_PCIE_QOSGEN_EXTREF_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_ANOC_PCIE_QOSGEN_EXTREF_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_ANOC_PCIE_QOSGEN_EXTREF_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_ANOC_PCIE_QOSGEN_EXTREF_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_ANOC_PCIE_QOSGEN_EXTREF_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_ANOC_PCIE_QOSGEN_EXTREF_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_ANOC_PCIE_QOSGEN_EXTREF_CBCR_CLK_ARES_RESET_FVAL 0x1 + +#define HWIO_GCC_MMNOC_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000c000) +#define HWIO_GCC_MMNOC_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c000) +#define HWIO_GCC_MMNOC_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c000) +#define HWIO_GCC_MMNOC_BCR_RMSK 0x1 +#define HWIO_GCC_MMNOC_BCR_ATTR 0x3 +#define HWIO_GCC_MMNOC_BCR_IN \ + in_dword_masked(HWIO_GCC_MMNOC_BCR_ADDR, HWIO_GCC_MMNOC_BCR_RMSK) +#define HWIO_GCC_MMNOC_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_MMNOC_BCR_ADDR, m) +#define HWIO_GCC_MMNOC_BCR_OUT(v) \ + out_dword(HWIO_GCC_MMNOC_BCR_ADDR,v) +#define HWIO_GCC_MMNOC_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MMNOC_BCR_ADDR,m,v,HWIO_GCC_MMNOC_BCR_IN) +#define HWIO_GCC_MMNOC_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_MMNOC_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_MMNOC_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMNOC_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MMNOC_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000c004) +#define HWIO_GCC_MMNOC_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c004) +#define HWIO_GCC_MMNOC_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c004) +#define HWIO_GCC_MMNOC_GDSCR_RMSK 0xf8ffffff +#define HWIO_GCC_MMNOC_GDSCR_ATTR 0x3 +#define HWIO_GCC_MMNOC_GDSCR_IN \ + in_dword_masked(HWIO_GCC_MMNOC_GDSCR_ADDR, HWIO_GCC_MMNOC_GDSCR_RMSK) +#define HWIO_GCC_MMNOC_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_MMNOC_GDSCR_ADDR, m) +#define HWIO_GCC_MMNOC_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_MMNOC_GDSCR_ADDR,v) +#define HWIO_GCC_MMNOC_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MMNOC_GDSCR_ADDR,m,v,HWIO_GCC_MMNOC_GDSCR_IN) +#define HWIO_GCC_MMNOC_GDSCR_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_MMNOC_GDSCR_PWR_ON_SHFT 0x1f +#define HWIO_GCC_MMNOC_GDSCR_GDSC_STATE_BMSK 0x78000000 +#define HWIO_GCC_MMNOC_GDSCR_GDSC_STATE_SHFT 0x1b +#define HWIO_GCC_MMNOC_GDSCR_EN_REST_WAIT_BMSK 0xf00000 +#define HWIO_GCC_MMNOC_GDSCR_EN_REST_WAIT_SHFT 0x14 +#define HWIO_GCC_MMNOC_GDSCR_EN_FEW_WAIT_BMSK 0xf0000 +#define HWIO_GCC_MMNOC_GDSCR_EN_FEW_WAIT_SHFT 0x10 +#define HWIO_GCC_MMNOC_GDSCR_CLK_DIS_WAIT_BMSK 0xf000 +#define HWIO_GCC_MMNOC_GDSCR_CLK_DIS_WAIT_SHFT 0xc +#define HWIO_GCC_MMNOC_GDSCR_RETAIN_FF_ENABLE_BMSK 0x800 +#define HWIO_GCC_MMNOC_GDSCR_RETAIN_FF_ENABLE_SHFT 0xb +#define HWIO_GCC_MMNOC_GDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMNOC_GDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMNOC_GDSCR_RESTORE_BMSK 0x400 +#define HWIO_GCC_MMNOC_GDSCR_RESTORE_SHFT 0xa +#define HWIO_GCC_MMNOC_GDSCR_RESTORE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMNOC_GDSCR_RESTORE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMNOC_GDSCR_SAVE_BMSK 0x200 +#define HWIO_GCC_MMNOC_GDSCR_SAVE_SHFT 0x9 +#define HWIO_GCC_MMNOC_GDSCR_SAVE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMNOC_GDSCR_SAVE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMNOC_GDSCR_RETAIN_BMSK 0x100 +#define HWIO_GCC_MMNOC_GDSCR_RETAIN_SHFT 0x8 +#define HWIO_GCC_MMNOC_GDSCR_RETAIN_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMNOC_GDSCR_RETAIN_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMNOC_GDSCR_EN_REST_BMSK 0x80 +#define HWIO_GCC_MMNOC_GDSCR_EN_REST_SHFT 0x7 +#define HWIO_GCC_MMNOC_GDSCR_EN_REST_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMNOC_GDSCR_EN_REST_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMNOC_GDSCR_EN_FEW_BMSK 0x40 +#define HWIO_GCC_MMNOC_GDSCR_EN_FEW_SHFT 0x6 +#define HWIO_GCC_MMNOC_GDSCR_EN_FEW_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMNOC_GDSCR_EN_FEW_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMNOC_GDSCR_CLAMP_IO_BMSK 0x20 +#define HWIO_GCC_MMNOC_GDSCR_CLAMP_IO_SHFT 0x5 +#define HWIO_GCC_MMNOC_GDSCR_CLAMP_IO_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMNOC_GDSCR_CLAMP_IO_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMNOC_GDSCR_CLK_DISABLE_BMSK 0x10 +#define HWIO_GCC_MMNOC_GDSCR_CLK_DISABLE_SHFT 0x4 +#define HWIO_GCC_MMNOC_GDSCR_CLK_DISABLE_CLK_NOT_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMNOC_GDSCR_CLK_DISABLE_CLK_IS_DISABLE_FVAL 0x1 +#define HWIO_GCC_MMNOC_GDSCR_PD_ARES_BMSK 0x8 +#define HWIO_GCC_MMNOC_GDSCR_PD_ARES_SHFT 0x3 +#define HWIO_GCC_MMNOC_GDSCR_PD_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_MMNOC_GDSCR_PD_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_MMNOC_GDSCR_SW_OVERRIDE_BMSK 0x4 +#define HWIO_GCC_MMNOC_GDSCR_SW_OVERRIDE_SHFT 0x2 +#define HWIO_GCC_MMNOC_GDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMNOC_GDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMNOC_GDSCR_HW_CONTROL_BMSK 0x2 +#define HWIO_GCC_MMNOC_GDSCR_HW_CONTROL_SHFT 0x1 +#define HWIO_GCC_MMNOC_GDSCR_HW_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMNOC_GDSCR_HW_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMNOC_GDSCR_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_MMNOC_GDSCR_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_MMNOC_GDSCR_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMNOC_GDSCR_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MMNOC_CFG_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000c008) +#define HWIO_GCC_MMNOC_CFG_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c008) +#define HWIO_GCC_MMNOC_CFG_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c008) +#define HWIO_GCC_MMNOC_CFG_GDSCR_RMSK 0x7ffffff +#define HWIO_GCC_MMNOC_CFG_GDSCR_ATTR 0x3 +#define HWIO_GCC_MMNOC_CFG_GDSCR_IN \ + in_dword_masked(HWIO_GCC_MMNOC_CFG_GDSCR_ADDR, HWIO_GCC_MMNOC_CFG_GDSCR_RMSK) +#define HWIO_GCC_MMNOC_CFG_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_MMNOC_CFG_GDSCR_ADDR, m) +#define HWIO_GCC_MMNOC_CFG_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_MMNOC_CFG_GDSCR_ADDR,v) +#define HWIO_GCC_MMNOC_CFG_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MMNOC_CFG_GDSCR_ADDR,m,v,HWIO_GCC_MMNOC_CFG_GDSCR_IN) +#define HWIO_GCC_MMNOC_CFG_GDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4000000 +#define HWIO_GCC_MMNOC_CFG_GDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x1a +#define HWIO_GCC_MMNOC_CFG_GDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMNOC_CFG_GDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMNOC_CFG_GDSCR_GDSC_PWR_DWN_START_BMSK 0x2000000 +#define HWIO_GCC_MMNOC_CFG_GDSCR_GDSC_PWR_DWN_START_SHFT 0x19 +#define HWIO_GCC_MMNOC_CFG_GDSCR_GDSC_PWR_UP_START_BMSK 0x1000000 +#define HWIO_GCC_MMNOC_CFG_GDSCR_GDSC_PWR_UP_START_SHFT 0x18 +#define HWIO_GCC_MMNOC_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_BMSK 0xf00000 +#define HWIO_GCC_MMNOC_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_SHFT 0x14 +#define HWIO_GCC_MMNOC_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_BMSK 0x80000 +#define HWIO_GCC_MMNOC_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_SHFT 0x13 +#define HWIO_GCC_MMNOC_CFG_GDSCR_GDSC_ENR_ACK_STATUS_BMSK 0x40000 +#define HWIO_GCC_MMNOC_CFG_GDSCR_GDSC_ENR_ACK_STATUS_SHFT 0x12 +#define HWIO_GCC_MMNOC_CFG_GDSCR_GDSC_ENF_ACK_STATUS_BMSK 0x20000 +#define HWIO_GCC_MMNOC_CFG_GDSCR_GDSC_ENF_ACK_STATUS_SHFT 0x11 +#define HWIO_GCC_MMNOC_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_BMSK 0x10000 +#define HWIO_GCC_MMNOC_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_SHFT 0x10 +#define HWIO_GCC_MMNOC_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_BMSK 0x8000 +#define HWIO_GCC_MMNOC_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_SHFT 0xf +#define HWIO_GCC_MMNOC_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_BMSK 0x7800 +#define HWIO_GCC_MMNOC_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_SHFT 0xb +#define HWIO_GCC_MMNOC_CFG_GDSCR_GDSC_HANDSHAKE_DIS_BMSK 0x400 +#define HWIO_GCC_MMNOC_CFG_GDSCR_GDSC_HANDSHAKE_DIS_SHFT 0xa +#define HWIO_GCC_MMNOC_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_BMSK 0x200 +#define HWIO_GCC_MMNOC_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_SHFT 0x9 +#define HWIO_GCC_MMNOC_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_BMSK 0x100 +#define HWIO_GCC_MMNOC_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_SHFT 0x8 +#define HWIO_GCC_MMNOC_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_BMSK 0x80 +#define HWIO_GCC_MMNOC_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_SHFT 0x7 +#define HWIO_GCC_MMNOC_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_BMSK 0x60 +#define HWIO_GCC_MMNOC_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_SHFT 0x5 +#define HWIO_GCC_MMNOC_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_BMSK 0x10 +#define HWIO_GCC_MMNOC_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_SHFT 0x4 +#define HWIO_GCC_MMNOC_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_BMSK 0x8 +#define HWIO_GCC_MMNOC_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_SHFT 0x3 +#define HWIO_GCC_MMNOC_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_BMSK 0x4 +#define HWIO_GCC_MMNOC_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_SHFT 0x2 +#define HWIO_GCC_MMNOC_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_BMSK 0x2 +#define HWIO_GCC_MMNOC_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_SHFT 0x1 +#define HWIO_GCC_MMNOC_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_MMNOC_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_SHFT 0x0 + +#define HWIO_GCC_MMNOC_CFG2_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000c00c) +#define HWIO_GCC_MMNOC_CFG2_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c00c) +#define HWIO_GCC_MMNOC_CFG2_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c00c) +#define HWIO_GCC_MMNOC_CFG2_GDSCR_RMSK 0x7ffff +#define HWIO_GCC_MMNOC_CFG2_GDSCR_ATTR 0x3 +#define HWIO_GCC_MMNOC_CFG2_GDSCR_IN \ + in_dword_masked(HWIO_GCC_MMNOC_CFG2_GDSCR_ADDR, HWIO_GCC_MMNOC_CFG2_GDSCR_RMSK) +#define HWIO_GCC_MMNOC_CFG2_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_MMNOC_CFG2_GDSCR_ADDR, m) +#define HWIO_GCC_MMNOC_CFG2_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_MMNOC_CFG2_GDSCR_ADDR,v) +#define HWIO_GCC_MMNOC_CFG2_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MMNOC_CFG2_GDSCR_ADDR,m,v,HWIO_GCC_MMNOC_CFG2_GDSCR_IN) +#define HWIO_GCC_MMNOC_CFG2_GDSCR_GDSC_MEM_PWRUP_ACK_OVERRIDE_BMSK 0x40000 +#define HWIO_GCC_MMNOC_CFG2_GDSCR_GDSC_MEM_PWRUP_ACK_OVERRIDE_SHFT 0x12 +#define HWIO_GCC_MMNOC_CFG2_GDSCR_GDSC_PWRDWN_ENABLE_ACK_OVERRIDE_BMSK 0x20000 +#define HWIO_GCC_MMNOC_CFG2_GDSCR_GDSC_PWRDWN_ENABLE_ACK_OVERRIDE_SHFT 0x11 +#define HWIO_GCC_MMNOC_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_BMSK 0x10000 +#define HWIO_GCC_MMNOC_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_SHFT 0x10 +#define HWIO_GCC_MMNOC_CFG2_GDSCR_DLY_MEM_PWR_UP_BMSK 0xf000 +#define HWIO_GCC_MMNOC_CFG2_GDSCR_DLY_MEM_PWR_UP_SHFT 0xc +#define HWIO_GCC_MMNOC_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_BMSK 0xf00 +#define HWIO_GCC_MMNOC_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_SHFT 0x8 +#define HWIO_GCC_MMNOC_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_BMSK 0xf0 +#define HWIO_GCC_MMNOC_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_SHFT 0x4 +#define HWIO_GCC_MMNOC_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_BMSK 0xf +#define HWIO_GCC_MMNOC_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_SHFT 0x0 + +#define HWIO_GCC_MMNOC_CFG3_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000c010) +#define HWIO_GCC_MMNOC_CFG3_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c010) +#define HWIO_GCC_MMNOC_CFG3_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c010) +#define HWIO_GCC_MMNOC_CFG3_GDSCR_RMSK 0x7ffffff +#define HWIO_GCC_MMNOC_CFG3_GDSCR_ATTR 0x3 +#define HWIO_GCC_MMNOC_CFG3_GDSCR_IN \ + in_dword_masked(HWIO_GCC_MMNOC_CFG3_GDSCR_ADDR, HWIO_GCC_MMNOC_CFG3_GDSCR_RMSK) +#define HWIO_GCC_MMNOC_CFG3_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_MMNOC_CFG3_GDSCR_ADDR, m) +#define HWIO_GCC_MMNOC_CFG3_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_MMNOC_CFG3_GDSCR_ADDR,v) +#define HWIO_GCC_MMNOC_CFG3_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MMNOC_CFG3_GDSCR_ADDR,m,v,HWIO_GCC_MMNOC_CFG3_GDSCR_IN) +#define HWIO_GCC_MMNOC_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_STATUS_BMSK 0x4000000 +#define HWIO_GCC_MMNOC_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_STATUS_SHFT 0x1a +#define HWIO_GCC_MMNOC_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_BMSK 0x2000000 +#define HWIO_GCC_MMNOC_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_SHFT 0x19 +#define HWIO_GCC_MMNOC_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMNOC_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMNOC_CFG3_GDSCR_DLY_ACCU_RED_SHIFTER_DONE_BMSK 0x1e00000 +#define HWIO_GCC_MMNOC_CFG3_GDSCR_DLY_ACCU_RED_SHIFTER_DONE_SHFT 0x15 +#define HWIO_GCC_MMNOC_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_BMSK 0x100000 +#define HWIO_GCC_MMNOC_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_SHFT 0x14 +#define HWIO_GCC_MMNOC_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMNOC_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMNOC_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_BMSK 0x80000 +#define HWIO_GCC_MMNOC_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_SHFT 0x13 +#define HWIO_GCC_MMNOC_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMNOC_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMNOC_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_BMSK 0x40000 +#define HWIO_GCC_MMNOC_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_SHFT 0x12 +#define HWIO_GCC_MMNOC_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMNOC_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMNOC_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_BMSK 0x20000 +#define HWIO_GCC_MMNOC_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_SHFT 0x11 +#define HWIO_GCC_MMNOC_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMNOC_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMNOC_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_BMSK 0x10000 +#define HWIO_GCC_MMNOC_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_SHFT 0x10 +#define HWIO_GCC_MMNOC_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMNOC_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMNOC_CFG3_GDSCR_GDSC_SPARE_CTRL_IN_BMSK 0xff00 +#define HWIO_GCC_MMNOC_CFG3_GDSCR_GDSC_SPARE_CTRL_IN_SHFT 0x8 +#define HWIO_GCC_MMNOC_CFG3_GDSCR_GDSC_SPARE_CTRL_OUT_BMSK 0xff +#define HWIO_GCC_MMNOC_CFG3_GDSCR_GDSC_SPARE_CTRL_OUT_SHFT 0x0 + +#define HWIO_GCC_MMNOC_CFG4_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000c014) +#define HWIO_GCC_MMNOC_CFG4_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c014) +#define HWIO_GCC_MMNOC_CFG4_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c014) +#define HWIO_GCC_MMNOC_CFG4_GDSCR_RMSK 0xffffff +#define HWIO_GCC_MMNOC_CFG4_GDSCR_ATTR 0x3 +#define HWIO_GCC_MMNOC_CFG4_GDSCR_IN \ + in_dword_masked(HWIO_GCC_MMNOC_CFG4_GDSCR_ADDR, HWIO_GCC_MMNOC_CFG4_GDSCR_RMSK) +#define HWIO_GCC_MMNOC_CFG4_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_MMNOC_CFG4_GDSCR_ADDR, m) +#define HWIO_GCC_MMNOC_CFG4_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_MMNOC_CFG4_GDSCR_ADDR,v) +#define HWIO_GCC_MMNOC_CFG4_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MMNOC_CFG4_GDSCR_ADDR,m,v,HWIO_GCC_MMNOC_CFG4_GDSCR_IN) +#define HWIO_GCC_MMNOC_CFG4_GDSCR_DLY_UNCLAMPIO_BMSK 0xf00000 +#define HWIO_GCC_MMNOC_CFG4_GDSCR_DLY_UNCLAMPIO_SHFT 0x14 +#define HWIO_GCC_MMNOC_CFG4_GDSCR_DLY_RESTOREFF_BMSK 0xf0000 +#define HWIO_GCC_MMNOC_CFG4_GDSCR_DLY_RESTOREFF_SHFT 0x10 +#define HWIO_GCC_MMNOC_CFG4_GDSCR_DLY_NORETAINFF_BMSK 0xf000 +#define HWIO_GCC_MMNOC_CFG4_GDSCR_DLY_NORETAINFF_SHFT 0xc +#define HWIO_GCC_MMNOC_CFG4_GDSCR_DLY_DEASSERTARES_BMSK 0xf00 +#define HWIO_GCC_MMNOC_CFG4_GDSCR_DLY_DEASSERTARES_SHFT 0x8 +#define HWIO_GCC_MMNOC_CFG4_GDSCR_DLY_CLAMPIO_BMSK 0xf0 +#define HWIO_GCC_MMNOC_CFG4_GDSCR_DLY_CLAMPIO_SHFT 0x4 +#define HWIO_GCC_MMNOC_CFG4_GDSCR_DLY_RETAINFF_BMSK 0xf +#define HWIO_GCC_MMNOC_CFG4_GDSCR_DLY_RETAINFF_SHFT 0x0 + +#define HWIO_GCC_MMNOC_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000c018) +#define HWIO_GCC_MMNOC_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c018) +#define HWIO_GCC_MMNOC_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c018) +#define HWIO_GCC_MMNOC_AT_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_MMNOC_AT_CBCR_ATTR 0x3 +#define HWIO_GCC_MMNOC_AT_CBCR_IN \ + in_dword_masked(HWIO_GCC_MMNOC_AT_CBCR_ADDR, HWIO_GCC_MMNOC_AT_CBCR_RMSK) +#define HWIO_GCC_MMNOC_AT_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_MMNOC_AT_CBCR_ADDR, m) +#define HWIO_GCC_MMNOC_AT_CBCR_OUT(v) \ + out_dword(HWIO_GCC_MMNOC_AT_CBCR_ADDR,v) +#define HWIO_GCC_MMNOC_AT_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MMNOC_AT_CBCR_ADDR,m,v,HWIO_GCC_MMNOC_AT_CBCR_IN) +#define HWIO_GCC_MMNOC_AT_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_MMNOC_AT_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_MMNOC_AT_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_MMNOC_AT_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_MMNOC_AT_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_MMNOC_AT_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_MMNOC_AT_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_MMNOC_AT_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_MMNOC_AT_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_MMNOC_AT_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_MMNOC_AT_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_MMNOC_AT_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_MMNOC_AT_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_MMNOC_AT_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_MMNOC_AT_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_MMNOC_AT_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_MMNOC_AT_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_MMNOC_AT_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_MMNOC_AT_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMNOC_AT_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMNOC_AT_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_MMNOC_AT_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_MMNOC_AT_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMNOC_AT_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MMNOC_AHB_CFG_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000c01c) +#define HWIO_GCC_MMNOC_AHB_CFG_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c01c) +#define HWIO_GCC_MMNOC_AHB_CFG_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c01c) +#define HWIO_GCC_MMNOC_AHB_CFG_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_MMNOC_AHB_CFG_CBCR_ATTR 0x3 +#define HWIO_GCC_MMNOC_AHB_CFG_CBCR_IN \ + in_dword_masked(HWIO_GCC_MMNOC_AHB_CFG_CBCR_ADDR, HWIO_GCC_MMNOC_AHB_CFG_CBCR_RMSK) +#define HWIO_GCC_MMNOC_AHB_CFG_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_MMNOC_AHB_CFG_CBCR_ADDR, m) +#define HWIO_GCC_MMNOC_AHB_CFG_CBCR_OUT(v) \ + out_dword(HWIO_GCC_MMNOC_AHB_CFG_CBCR_ADDR,v) +#define HWIO_GCC_MMNOC_AHB_CFG_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MMNOC_AHB_CFG_CBCR_ADDR,m,v,HWIO_GCC_MMNOC_AHB_CFG_CBCR_IN) +#define HWIO_GCC_MMNOC_AHB_CFG_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_MMNOC_AHB_CFG_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_MMNOC_AHB_CFG_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_MMNOC_AHB_CFG_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_MMNOC_AHB_CFG_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_MMNOC_AHB_CFG_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_MMNOC_AHB_CFG_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_MMNOC_AHB_CFG_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_MMNOC_AHB_CFG_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_MMNOC_AHB_CFG_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_MMNOC_AHB_CFG_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_MMNOC_AHB_CFG_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_MMNOC_AHB_CFG_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_MMNOC_AHB_CFG_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_MMNOC_AHB_CFG_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_MMNOC_AHB_CFG_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_MMNOC_AHB_CFG_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_MMNOC_AHB_CFG_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_MMNOC_AHB_CFG_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMNOC_AHB_CFG_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMNOC_AHB_CFG_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_MMNOC_AHB_CFG_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_MMNOC_AHB_CFG_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMNOC_AHB_CFG_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_NOC_MMNOC_DCD_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000c020) +#define HWIO_GCC_NOC_MMNOC_DCD_XO_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c020) +#define HWIO_GCC_NOC_MMNOC_DCD_XO_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c020) +#define HWIO_GCC_NOC_MMNOC_DCD_XO_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_NOC_MMNOC_DCD_XO_CBCR_ATTR 0x3 +#define HWIO_GCC_NOC_MMNOC_DCD_XO_CBCR_IN \ + in_dword_masked(HWIO_GCC_NOC_MMNOC_DCD_XO_CBCR_ADDR, HWIO_GCC_NOC_MMNOC_DCD_XO_CBCR_RMSK) +#define HWIO_GCC_NOC_MMNOC_DCD_XO_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_NOC_MMNOC_DCD_XO_CBCR_ADDR, m) +#define HWIO_GCC_NOC_MMNOC_DCD_XO_CBCR_OUT(v) \ + out_dword(HWIO_GCC_NOC_MMNOC_DCD_XO_CBCR_ADDR,v) +#define HWIO_GCC_NOC_MMNOC_DCD_XO_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_NOC_MMNOC_DCD_XO_CBCR_ADDR,m,v,HWIO_GCC_NOC_MMNOC_DCD_XO_CBCR_IN) +#define HWIO_GCC_NOC_MMNOC_DCD_XO_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_NOC_MMNOC_DCD_XO_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_NOC_MMNOC_DCD_XO_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_NOC_MMNOC_DCD_XO_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_NOC_MMNOC_DCD_XO_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_NOC_MMNOC_DCD_XO_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_NOC_MMNOC_DCD_XO_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_NOC_MMNOC_DCD_XO_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_NOC_MMNOC_DCD_XO_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_NOC_MMNOC_DCD_XO_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_NOC_MMNOC_DCD_XO_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_NOC_MMNOC_DCD_XO_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_NOC_MMNOC_DCD_XO_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_NOC_MMNOC_DCD_XO_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_NOC_MMNOC_DCD_XO_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_NOC_MMNOC_DCD_XO_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MMNOC_TSCTR_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000c024) +#define HWIO_GCC_MMNOC_TSCTR_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c024) +#define HWIO_GCC_MMNOC_TSCTR_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c024) +#define HWIO_GCC_MMNOC_TSCTR_CBCR_RMSK 0x81c0000f +#define HWIO_GCC_MMNOC_TSCTR_CBCR_ATTR 0x3 +#define HWIO_GCC_MMNOC_TSCTR_CBCR_IN \ + in_dword_masked(HWIO_GCC_MMNOC_TSCTR_CBCR_ADDR, HWIO_GCC_MMNOC_TSCTR_CBCR_RMSK) +#define HWIO_GCC_MMNOC_TSCTR_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_MMNOC_TSCTR_CBCR_ADDR, m) +#define HWIO_GCC_MMNOC_TSCTR_CBCR_OUT(v) \ + out_dword(HWIO_GCC_MMNOC_TSCTR_CBCR_ADDR,v) +#define HWIO_GCC_MMNOC_TSCTR_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MMNOC_TSCTR_CBCR_ADDR,m,v,HWIO_GCC_MMNOC_TSCTR_CBCR_IN) +#define HWIO_GCC_MMNOC_TSCTR_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_MMNOC_TSCTR_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_MMNOC_TSCTR_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_MMNOC_TSCTR_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_MMNOC_TSCTR_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_MMNOC_TSCTR_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_MMNOC_TSCTR_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_MMNOC_TSCTR_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_MMNOC_TSCTR_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_MMNOC_TSCTR_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_MMNOC_TSCTR_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_MMNOC_TSCTR_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_MMNOC_TSCTR_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_MMNOC_TSCTR_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_MMNOC_TSCTR_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_MMNOC_TSCTR_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_MMNOC_TSCTR_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMNOC_TSCTR_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMNOC_TSCTR_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_MMNOC_TSCTR_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_MMNOC_TSCTR_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMNOC_TSCTR_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MMNOC_SF_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000c028) +#define HWIO_GCC_MMNOC_SF_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c028) +#define HWIO_GCC_MMNOC_SF_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c028) +#define HWIO_GCC_MMNOC_SF_CBCR_RMSK 0x81f0700f +#define HWIO_GCC_MMNOC_SF_CBCR_ATTR 0x3 +#define HWIO_GCC_MMNOC_SF_CBCR_IN \ + in_dword_masked(HWIO_GCC_MMNOC_SF_CBCR_ADDR, HWIO_GCC_MMNOC_SF_CBCR_RMSK) +#define HWIO_GCC_MMNOC_SF_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_MMNOC_SF_CBCR_ADDR, m) +#define HWIO_GCC_MMNOC_SF_CBCR_OUT(v) \ + out_dword(HWIO_GCC_MMNOC_SF_CBCR_ADDR,v) +#define HWIO_GCC_MMNOC_SF_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MMNOC_SF_CBCR_ADDR,m,v,HWIO_GCC_MMNOC_SF_CBCR_IN) +#define HWIO_GCC_MMNOC_SF_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_MMNOC_SF_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_MMNOC_SF_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_MMNOC_SF_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_MMNOC_SF_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_MMNOC_SF_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_MMNOC_SF_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_MMNOC_SF_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_MMNOC_SF_CBCR_IGNORE_PMU_CLK_DIS_BMSK 0x200000 +#define HWIO_GCC_MMNOC_SF_CBCR_IGNORE_PMU_CLK_DIS_SHFT 0x15 +#define HWIO_GCC_MMNOC_SF_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_MMNOC_SF_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_MMNOC_SF_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_MMNOC_SF_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_MMNOC_SF_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMNOC_SF_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMNOC_SF_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_MMNOC_SF_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_MMNOC_SF_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMNOC_SF_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMNOC_SF_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_MMNOC_SF_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_MMNOC_SF_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMNOC_SF_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMNOC_SF_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_MMNOC_SF_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_MMNOC_SF_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_MMNOC_SF_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_MMNOC_SF_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_MMNOC_SF_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_MMNOC_SF_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_MMNOC_SF_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_MMNOC_SF_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMNOC_SF_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMNOC_SF_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_MMNOC_SF_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_MMNOC_SF_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMNOC_SF_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MMNOC_SF_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000c02c) +#define HWIO_GCC_MMNOC_SF_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c02c) +#define HWIO_GCC_MMNOC_SF_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c02c) +#define HWIO_GCC_MMNOC_SF_SREGR_RMSK 0xf1ffffe +#define HWIO_GCC_MMNOC_SF_SREGR_ATTR 0x3 +#define HWIO_GCC_MMNOC_SF_SREGR_IN \ + in_dword_masked(HWIO_GCC_MMNOC_SF_SREGR_ADDR, HWIO_GCC_MMNOC_SF_SREGR_RMSK) +#define HWIO_GCC_MMNOC_SF_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_MMNOC_SF_SREGR_ADDR, m) +#define HWIO_GCC_MMNOC_SF_SREGR_OUT(v) \ + out_dword(HWIO_GCC_MMNOC_SF_SREGR_ADDR,v) +#define HWIO_GCC_MMNOC_SF_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MMNOC_SF_SREGR_ADDR,m,v,HWIO_GCC_MMNOC_SF_SREGR_IN) +#define HWIO_GCC_MMNOC_SF_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xf000000 +#define HWIO_GCC_MMNOC_SF_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_MMNOC_SF_SREGR_PWR_FSM_CLK_SEL_BMSK 0x100000 +#define HWIO_GCC_MMNOC_SF_SREGR_PWR_FSM_CLK_SEL_SHFT 0x14 +#define HWIO_GCC_MMNOC_SF_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xf0000 +#define HWIO_GCC_MMNOC_SF_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_MMNOC_SF_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_MMNOC_SF_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_MMNOC_SF_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_MMNOC_SF_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_MMNOC_SF_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_MMNOC_SF_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_MMNOC_SF_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_MMNOC_SF_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_MMNOC_SF_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_MMNOC_SF_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_MMNOC_SF_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_MMNOC_SF_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_MMNOC_SF_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_MMNOC_SF_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_MMNOC_SF_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_MMNOC_SF_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_MMNOC_SF_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_MMNOC_SF_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_MMNOC_SF_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_MMNOC_SF_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_MMNOC_SF_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_MMNOC_SF_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_MMNOC_SF_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_MMNOC_SF_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_MMNOC_SF_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_MMNOC_SF_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_MMNOC_SF_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_MMNOC_SF_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_MMNOC_SF_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMNOC_SF_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMNOC_SF_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_MMNOC_SF_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_MMNOC_SF_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_MMNOC_SF_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMNOC_SF_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_MMNOC_SF_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_MMNOC_SF_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_MMNOC_SF_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_MMNOC_SF_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_MMNOC_SF_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_MMNOC_SF_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_MMNOC_SF_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_MMNOC_SF_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_MMNOC_SF_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_MMNOC_SF_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_MMNOC_SF_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_MMNOC_SF_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_MMNOC_SF_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_MMNOC_SF_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_MMNOC_SF_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_MMNOC_SF_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_MMNOC_SF_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_MMNOC_SF_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMNOC_SF_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MMNOC_SF_CFG_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000c030) +#define HWIO_GCC_MMNOC_SF_CFG_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c030) +#define HWIO_GCC_MMNOC_SF_CFG_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c030) +#define HWIO_GCC_MMNOC_SF_CFG_SREGR_RMSK 0xffffffff +#define HWIO_GCC_MMNOC_SF_CFG_SREGR_ATTR 0x3 +#define HWIO_GCC_MMNOC_SF_CFG_SREGR_IN \ + in_dword_masked(HWIO_GCC_MMNOC_SF_CFG_SREGR_ADDR, HWIO_GCC_MMNOC_SF_CFG_SREGR_RMSK) +#define HWIO_GCC_MMNOC_SF_CFG_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_MMNOC_SF_CFG_SREGR_ADDR, m) +#define HWIO_GCC_MMNOC_SF_CFG_SREGR_OUT(v) \ + out_dword(HWIO_GCC_MMNOC_SF_CFG_SREGR_ADDR,v) +#define HWIO_GCC_MMNOC_SF_CFG_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MMNOC_SF_CFG_SREGR_ADDR,m,v,HWIO_GCC_MMNOC_SF_CFG_SREGR_IN) +#define HWIO_GCC_MMNOC_SF_CFG_SREGR_MEM_CORE_OFF_TIMER_BMSK 0xfc000000 +#define HWIO_GCC_MMNOC_SF_CFG_SREGR_MEM_CORE_OFF_TIMER_SHFT 0x1a +#define HWIO_GCC_MMNOC_SF_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_BMSK 0x2000000 +#define HWIO_GCC_MMNOC_SF_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_SHFT 0x19 +#define HWIO_GCC_MMNOC_SF_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_BMSK 0x1000000 +#define HWIO_GCC_MMNOC_SF_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_SHFT 0x18 +#define HWIO_GCC_MMNOC_SF_CFG_SREGR_MEM_PERIPH_ON_STATUS_BMSK 0x800000 +#define HWIO_GCC_MMNOC_SF_CFG_SREGR_MEM_PERIPH_ON_STATUS_SHFT 0x17 +#define HWIO_GCC_MMNOC_SF_CFG_SREGR_MEM_CORE_ON_STATUS_BMSK 0x400000 +#define HWIO_GCC_MMNOC_SF_CFG_SREGR_MEM_CORE_ON_STATUS_SHFT 0x16 +#define HWIO_GCC_MMNOC_SF_CFG_SREGR_MEM_CPH_TIMER_BMSK 0x3f0000 +#define HWIO_GCC_MMNOC_SF_CFG_SREGR_MEM_CPH_TIMER_SHFT 0x10 +#define HWIO_GCC_MMNOC_SF_CFG_SREGR_SLEEP_TIMER_BMSK 0xff00 +#define HWIO_GCC_MMNOC_SF_CFG_SREGR_SLEEP_TIMER_SHFT 0x8 +#define HWIO_GCC_MMNOC_SF_CFG_SREGR_WAKEUP_TIMER_BMSK 0xff +#define HWIO_GCC_MMNOC_SF_CFG_SREGR_WAKEUP_TIMER_SHFT 0x0 + +#define HWIO_GCC_MMNOC_HF_QX_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000c034) +#define HWIO_GCC_MMNOC_HF_QX_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c034) +#define HWIO_GCC_MMNOC_HF_QX_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c034) +#define HWIO_GCC_MMNOC_HF_QX_CBCR_RMSK 0x81f0700f +#define HWIO_GCC_MMNOC_HF_QX_CBCR_ATTR 0x3 +#define HWIO_GCC_MMNOC_HF_QX_CBCR_IN \ + in_dword_masked(HWIO_GCC_MMNOC_HF_QX_CBCR_ADDR, HWIO_GCC_MMNOC_HF_QX_CBCR_RMSK) +#define HWIO_GCC_MMNOC_HF_QX_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_MMNOC_HF_QX_CBCR_ADDR, m) +#define HWIO_GCC_MMNOC_HF_QX_CBCR_OUT(v) \ + out_dword(HWIO_GCC_MMNOC_HF_QX_CBCR_ADDR,v) +#define HWIO_GCC_MMNOC_HF_QX_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MMNOC_HF_QX_CBCR_ADDR,m,v,HWIO_GCC_MMNOC_HF_QX_CBCR_IN) +#define HWIO_GCC_MMNOC_HF_QX_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_MMNOC_HF_QX_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_MMNOC_HF_QX_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_MMNOC_HF_QX_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_MMNOC_HF_QX_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_MMNOC_HF_QX_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_MMNOC_HF_QX_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_MMNOC_HF_QX_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_MMNOC_HF_QX_CBCR_IGNORE_PMU_CLK_DIS_BMSK 0x200000 +#define HWIO_GCC_MMNOC_HF_QX_CBCR_IGNORE_PMU_CLK_DIS_SHFT 0x15 +#define HWIO_GCC_MMNOC_HF_QX_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_MMNOC_HF_QX_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_MMNOC_HF_QX_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_MMNOC_HF_QX_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_MMNOC_HF_QX_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMNOC_HF_QX_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMNOC_HF_QX_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_MMNOC_HF_QX_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_MMNOC_HF_QX_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMNOC_HF_QX_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMNOC_HF_QX_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_MMNOC_HF_QX_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_MMNOC_HF_QX_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMNOC_HF_QX_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMNOC_HF_QX_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_MMNOC_HF_QX_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_MMNOC_HF_QX_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_MMNOC_HF_QX_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_MMNOC_HF_QX_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_MMNOC_HF_QX_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_MMNOC_HF_QX_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_MMNOC_HF_QX_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_MMNOC_HF_QX_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMNOC_HF_QX_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMNOC_HF_QX_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_MMNOC_HF_QX_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_MMNOC_HF_QX_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMNOC_HF_QX_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MMNOC_HF_QX_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000c038) +#define HWIO_GCC_MMNOC_HF_QX_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c038) +#define HWIO_GCC_MMNOC_HF_QX_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c038) +#define HWIO_GCC_MMNOC_HF_QX_SREGR_RMSK 0xf1ffffe +#define HWIO_GCC_MMNOC_HF_QX_SREGR_ATTR 0x3 +#define HWIO_GCC_MMNOC_HF_QX_SREGR_IN \ + in_dword_masked(HWIO_GCC_MMNOC_HF_QX_SREGR_ADDR, HWIO_GCC_MMNOC_HF_QX_SREGR_RMSK) +#define HWIO_GCC_MMNOC_HF_QX_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_MMNOC_HF_QX_SREGR_ADDR, m) +#define HWIO_GCC_MMNOC_HF_QX_SREGR_OUT(v) \ + out_dword(HWIO_GCC_MMNOC_HF_QX_SREGR_ADDR,v) +#define HWIO_GCC_MMNOC_HF_QX_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MMNOC_HF_QX_SREGR_ADDR,m,v,HWIO_GCC_MMNOC_HF_QX_SREGR_IN) +#define HWIO_GCC_MMNOC_HF_QX_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xf000000 +#define HWIO_GCC_MMNOC_HF_QX_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_MMNOC_HF_QX_SREGR_PWR_FSM_CLK_SEL_BMSK 0x100000 +#define HWIO_GCC_MMNOC_HF_QX_SREGR_PWR_FSM_CLK_SEL_SHFT 0x14 +#define HWIO_GCC_MMNOC_HF_QX_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xf0000 +#define HWIO_GCC_MMNOC_HF_QX_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_MMNOC_HF_QX_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_MMNOC_HF_QX_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_MMNOC_HF_QX_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_MMNOC_HF_QX_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_MMNOC_HF_QX_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_MMNOC_HF_QX_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_MMNOC_HF_QX_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_MMNOC_HF_QX_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_MMNOC_HF_QX_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_MMNOC_HF_QX_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_MMNOC_HF_QX_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_MMNOC_HF_QX_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_MMNOC_HF_QX_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_MMNOC_HF_QX_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_MMNOC_HF_QX_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_MMNOC_HF_QX_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_MMNOC_HF_QX_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_MMNOC_HF_QX_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_MMNOC_HF_QX_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_MMNOC_HF_QX_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_MMNOC_HF_QX_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_MMNOC_HF_QX_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_MMNOC_HF_QX_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_MMNOC_HF_QX_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_MMNOC_HF_QX_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_MMNOC_HF_QX_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_MMNOC_HF_QX_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_MMNOC_HF_QX_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_MMNOC_HF_QX_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMNOC_HF_QX_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMNOC_HF_QX_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_MMNOC_HF_QX_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_MMNOC_HF_QX_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_MMNOC_HF_QX_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMNOC_HF_QX_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_MMNOC_HF_QX_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_MMNOC_HF_QX_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_MMNOC_HF_QX_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_MMNOC_HF_QX_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_MMNOC_HF_QX_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_MMNOC_HF_QX_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_MMNOC_HF_QX_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_MMNOC_HF_QX_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_MMNOC_HF_QX_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_MMNOC_HF_QX_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_MMNOC_HF_QX_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_MMNOC_HF_QX_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_MMNOC_HF_QX_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_MMNOC_HF_QX_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_MMNOC_HF_QX_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_MMNOC_HF_QX_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_MMNOC_HF_QX_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_MMNOC_HF_QX_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMNOC_HF_QX_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MMNOC_HF_QX_CFG_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000c03c) +#define HWIO_GCC_MMNOC_HF_QX_CFG_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c03c) +#define HWIO_GCC_MMNOC_HF_QX_CFG_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c03c) +#define HWIO_GCC_MMNOC_HF_QX_CFG_SREGR_RMSK 0xffffffff +#define HWIO_GCC_MMNOC_HF_QX_CFG_SREGR_ATTR 0x3 +#define HWIO_GCC_MMNOC_HF_QX_CFG_SREGR_IN \ + in_dword_masked(HWIO_GCC_MMNOC_HF_QX_CFG_SREGR_ADDR, HWIO_GCC_MMNOC_HF_QX_CFG_SREGR_RMSK) +#define HWIO_GCC_MMNOC_HF_QX_CFG_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_MMNOC_HF_QX_CFG_SREGR_ADDR, m) +#define HWIO_GCC_MMNOC_HF_QX_CFG_SREGR_OUT(v) \ + out_dword(HWIO_GCC_MMNOC_HF_QX_CFG_SREGR_ADDR,v) +#define HWIO_GCC_MMNOC_HF_QX_CFG_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MMNOC_HF_QX_CFG_SREGR_ADDR,m,v,HWIO_GCC_MMNOC_HF_QX_CFG_SREGR_IN) +#define HWIO_GCC_MMNOC_HF_QX_CFG_SREGR_MEM_CORE_OFF_TIMER_BMSK 0xfc000000 +#define HWIO_GCC_MMNOC_HF_QX_CFG_SREGR_MEM_CORE_OFF_TIMER_SHFT 0x1a +#define HWIO_GCC_MMNOC_HF_QX_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_BMSK 0x2000000 +#define HWIO_GCC_MMNOC_HF_QX_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_SHFT 0x19 +#define HWIO_GCC_MMNOC_HF_QX_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_BMSK 0x1000000 +#define HWIO_GCC_MMNOC_HF_QX_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_SHFT 0x18 +#define HWIO_GCC_MMNOC_HF_QX_CFG_SREGR_MEM_PERIPH_ON_STATUS_BMSK 0x800000 +#define HWIO_GCC_MMNOC_HF_QX_CFG_SREGR_MEM_PERIPH_ON_STATUS_SHFT 0x17 +#define HWIO_GCC_MMNOC_HF_QX_CFG_SREGR_MEM_CORE_ON_STATUS_BMSK 0x400000 +#define HWIO_GCC_MMNOC_HF_QX_CFG_SREGR_MEM_CORE_ON_STATUS_SHFT 0x16 +#define HWIO_GCC_MMNOC_HF_QX_CFG_SREGR_MEM_CPH_TIMER_BMSK 0x3f0000 +#define HWIO_GCC_MMNOC_HF_QX_CFG_SREGR_MEM_CPH_TIMER_SHFT 0x10 +#define HWIO_GCC_MMNOC_HF_QX_CFG_SREGR_SLEEP_TIMER_BMSK 0xff00 +#define HWIO_GCC_MMNOC_HF_QX_CFG_SREGR_SLEEP_TIMER_SHFT 0x8 +#define HWIO_GCC_MMNOC_HF_QX_CFG_SREGR_WAKEUP_TIMER_BMSK 0xff +#define HWIO_GCC_MMNOC_HF_QX_CFG_SREGR_WAKEUP_TIMER_SHFT 0x0 + +#define HWIO_GCC_MMNOC_PWRCTL_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000c040) +#define HWIO_GCC_MMNOC_PWRCTL_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c040) +#define HWIO_GCC_MMNOC_PWRCTL_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c040) +#define HWIO_GCC_MMNOC_PWRCTL_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_MMNOC_PWRCTL_CBCR_ATTR 0x3 +#define HWIO_GCC_MMNOC_PWRCTL_CBCR_IN \ + in_dword_masked(HWIO_GCC_MMNOC_PWRCTL_CBCR_ADDR, HWIO_GCC_MMNOC_PWRCTL_CBCR_RMSK) +#define HWIO_GCC_MMNOC_PWRCTL_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_MMNOC_PWRCTL_CBCR_ADDR, m) +#define HWIO_GCC_MMNOC_PWRCTL_CBCR_OUT(v) \ + out_dword(HWIO_GCC_MMNOC_PWRCTL_CBCR_ADDR,v) +#define HWIO_GCC_MMNOC_PWRCTL_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MMNOC_PWRCTL_CBCR_ADDR,m,v,HWIO_GCC_MMNOC_PWRCTL_CBCR_IN) +#define HWIO_GCC_MMNOC_PWRCTL_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_MMNOC_PWRCTL_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_MMNOC_PWRCTL_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_MMNOC_PWRCTL_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_MMNOC_PWRCTL_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_MMNOC_PWRCTL_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_MMNOC_PWRCTL_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_MMNOC_PWRCTL_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_MMNOC_PWRCTL_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_MMNOC_PWRCTL_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_MMNOC_PWRCTL_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_MMNOC_PWRCTL_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_MMNOC_PWRCTL_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_MMNOC_PWRCTL_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_MMNOC_PWRCTL_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_MMNOC_PWRCTL_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_MMNOC_PWRCTL_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_MMNOC_PWRCTL_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_MMNOC_PWRCTL_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMNOC_PWRCTL_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMNOC_PWRCTL_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_MMNOC_PWRCTL_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_MMNOC_PWRCTL_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMNOC_PWRCTL_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MMNOC_QOSGEN_EXTREF_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000c044) +#define HWIO_GCC_MMNOC_QOSGEN_EXTREF_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c044) +#define HWIO_GCC_MMNOC_QOSGEN_EXTREF_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c044) +#define HWIO_GCC_MMNOC_QOSGEN_EXTREF_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_MMNOC_QOSGEN_EXTREF_CBCR_ATTR 0x3 +#define HWIO_GCC_MMNOC_QOSGEN_EXTREF_CBCR_IN \ + in_dword_masked(HWIO_GCC_MMNOC_QOSGEN_EXTREF_CBCR_ADDR, HWIO_GCC_MMNOC_QOSGEN_EXTREF_CBCR_RMSK) +#define HWIO_GCC_MMNOC_QOSGEN_EXTREF_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_MMNOC_QOSGEN_EXTREF_CBCR_ADDR, m) +#define HWIO_GCC_MMNOC_QOSGEN_EXTREF_CBCR_OUT(v) \ + out_dword(HWIO_GCC_MMNOC_QOSGEN_EXTREF_CBCR_ADDR,v) +#define HWIO_GCC_MMNOC_QOSGEN_EXTREF_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MMNOC_QOSGEN_EXTREF_CBCR_ADDR,m,v,HWIO_GCC_MMNOC_QOSGEN_EXTREF_CBCR_IN) +#define HWIO_GCC_MMNOC_QOSGEN_EXTREF_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_MMNOC_QOSGEN_EXTREF_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_MMNOC_QOSGEN_EXTREF_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_MMNOC_QOSGEN_EXTREF_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_MMNOC_QOSGEN_EXTREF_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_MMNOC_QOSGEN_EXTREF_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_MMNOC_QOSGEN_EXTREF_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_MMNOC_QOSGEN_EXTREF_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_MMNOC_QOSGEN_EXTREF_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_MMNOC_QOSGEN_EXTREF_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_MMNOC_QOSGEN_EXTREF_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_MMNOC_QOSGEN_EXTREF_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_MMNOC_QOSGEN_EXTREF_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_MMNOC_QOSGEN_EXTREF_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_MMNOC_QOSGEN_EXTREF_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMNOC_QOSGEN_EXTREF_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MMSS_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002b000) +#define HWIO_GCC_MMSS_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002b000) +#define HWIO_GCC_MMSS_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002b000) +#define HWIO_GCC_MMSS_BCR_RMSK 0x1 +#define HWIO_GCC_MMSS_BCR_ATTR 0x3 +#define HWIO_GCC_MMSS_BCR_IN \ + in_dword_masked(HWIO_GCC_MMSS_BCR_ADDR, HWIO_GCC_MMSS_BCR_RMSK) +#define HWIO_GCC_MMSS_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_MMSS_BCR_ADDR, m) +#define HWIO_GCC_MMSS_BCR_OUT(v) \ + out_dword(HWIO_GCC_MMSS_BCR_ADDR,v) +#define HWIO_GCC_MMSS_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MMSS_BCR_ADDR,m,v,HWIO_GCC_MMSS_BCR_IN) +#define HWIO_GCC_MMSS_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_MMSS_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_MMSS_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMSS_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MMSS_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002b004) +#define HWIO_GCC_MMSS_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002b004) +#define HWIO_GCC_MMSS_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002b004) +#define HWIO_GCC_MMSS_AT_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_MMSS_AT_CBCR_ATTR 0x3 +#define HWIO_GCC_MMSS_AT_CBCR_IN \ + in_dword_masked(HWIO_GCC_MMSS_AT_CBCR_ADDR, HWIO_GCC_MMSS_AT_CBCR_RMSK) +#define HWIO_GCC_MMSS_AT_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_MMSS_AT_CBCR_ADDR, m) +#define HWIO_GCC_MMSS_AT_CBCR_OUT(v) \ + out_dword(HWIO_GCC_MMSS_AT_CBCR_ADDR,v) +#define HWIO_GCC_MMSS_AT_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MMSS_AT_CBCR_ADDR,m,v,HWIO_GCC_MMSS_AT_CBCR_IN) +#define HWIO_GCC_MMSS_AT_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_MMSS_AT_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_MMSS_AT_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_MMSS_AT_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_MMSS_AT_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_MMSS_AT_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_MMSS_AT_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_MMSS_AT_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_MMSS_AT_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_MMSS_AT_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_MMSS_AT_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_MMSS_AT_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_MMSS_AT_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_MMSS_AT_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_MMSS_AT_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_MMSS_AT_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_MMSS_AT_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_MMSS_AT_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_MMSS_AT_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMSS_AT_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMSS_AT_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_MMSS_AT_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_MMSS_AT_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMSS_AT_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MMSS_QMIP_CORE_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002b008) +#define HWIO_GCC_MMSS_QMIP_CORE_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002b008) +#define HWIO_GCC_MMSS_QMIP_CORE_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002b008) +#define HWIO_GCC_MMSS_QMIP_CORE_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_MMSS_QMIP_CORE_CBCR_ATTR 0x3 +#define HWIO_GCC_MMSS_QMIP_CORE_CBCR_IN \ + in_dword_masked(HWIO_GCC_MMSS_QMIP_CORE_CBCR_ADDR, HWIO_GCC_MMSS_QMIP_CORE_CBCR_RMSK) +#define HWIO_GCC_MMSS_QMIP_CORE_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_MMSS_QMIP_CORE_CBCR_ADDR, m) +#define HWIO_GCC_MMSS_QMIP_CORE_CBCR_OUT(v) \ + out_dword(HWIO_GCC_MMSS_QMIP_CORE_CBCR_ADDR,v) +#define HWIO_GCC_MMSS_QMIP_CORE_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MMSS_QMIP_CORE_CBCR_ADDR,m,v,HWIO_GCC_MMSS_QMIP_CORE_CBCR_IN) +#define HWIO_GCC_MMSS_QMIP_CORE_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_MMSS_QMIP_CORE_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_MMSS_QMIP_CORE_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_MMSS_QMIP_CORE_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_MMSS_QMIP_CORE_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_MMSS_QMIP_CORE_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_MMSS_QMIP_CORE_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_MMSS_QMIP_CORE_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_MMSS_QMIP_CORE_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_MMSS_QMIP_CORE_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_MMSS_QMIP_CORE_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_MMSS_QMIP_CORE_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_MMSS_QMIP_CORE_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_MMSS_QMIP_CORE_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_MMSS_QMIP_CORE_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMSS_QMIP_CORE_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MMSS_TRIG_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002b00c) +#define HWIO_GCC_MMSS_TRIG_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002b00c) +#define HWIO_GCC_MMSS_TRIG_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002b00c) +#define HWIO_GCC_MMSS_TRIG_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_MMSS_TRIG_CBCR_ATTR 0x3 +#define HWIO_GCC_MMSS_TRIG_CBCR_IN \ + in_dword_masked(HWIO_GCC_MMSS_TRIG_CBCR_ADDR, HWIO_GCC_MMSS_TRIG_CBCR_RMSK) +#define HWIO_GCC_MMSS_TRIG_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_MMSS_TRIG_CBCR_ADDR, m) +#define HWIO_GCC_MMSS_TRIG_CBCR_OUT(v) \ + out_dword(HWIO_GCC_MMSS_TRIG_CBCR_ADDR,v) +#define HWIO_GCC_MMSS_TRIG_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MMSS_TRIG_CBCR_ADDR,m,v,HWIO_GCC_MMSS_TRIG_CBCR_IN) +#define HWIO_GCC_MMSS_TRIG_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_MMSS_TRIG_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_MMSS_TRIG_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_MMSS_TRIG_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_MMSS_TRIG_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_MMSS_TRIG_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_MMSS_TRIG_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_MMSS_TRIG_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_MMSS_TRIG_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_MMSS_TRIG_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_MMSS_TRIG_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_MMSS_TRIG_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_MMSS_TRIG_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_MMSS_TRIG_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_MMSS_TRIG_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_MMSS_TRIG_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_MMSS_TRIG_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_MMSS_TRIG_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_MMSS_TRIG_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMSS_TRIG_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMSS_TRIG_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_MMSS_TRIG_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_MMSS_TRIG_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMSS_TRIG_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MMSS_QMIP_CORE_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002b010) +#define HWIO_GCC_MMSS_QMIP_CORE_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002b010) +#define HWIO_GCC_MMSS_QMIP_CORE_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002b010) +#define HWIO_GCC_MMSS_QMIP_CORE_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_MMSS_QMIP_CORE_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_MMSS_QMIP_CORE_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_MMSS_QMIP_CORE_CMD_RCGR_ADDR, HWIO_GCC_MMSS_QMIP_CORE_CMD_RCGR_RMSK) +#define HWIO_GCC_MMSS_QMIP_CORE_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_MMSS_QMIP_CORE_CMD_RCGR_ADDR, m) +#define HWIO_GCC_MMSS_QMIP_CORE_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_MMSS_QMIP_CORE_CMD_RCGR_ADDR,v) +#define HWIO_GCC_MMSS_QMIP_CORE_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MMSS_QMIP_CORE_CMD_RCGR_ADDR,m,v,HWIO_GCC_MMSS_QMIP_CORE_CMD_RCGR_IN) +#define HWIO_GCC_MMSS_QMIP_CORE_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_MMSS_QMIP_CORE_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_MMSS_QMIP_CORE_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_MMSS_QMIP_CORE_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_MMSS_QMIP_CORE_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_MMSS_QMIP_CORE_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_MMSS_QMIP_CORE_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMSS_QMIP_CORE_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMSS_QMIP_CORE_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_MMSS_QMIP_CORE_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_MMSS_QMIP_CORE_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMSS_QMIP_CORE_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002b014) +#define HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002b014) +#define HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002b014) +#define HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_ADDR, HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_RMSK) +#define HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_ADDR, m) +#define HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_ADDR,v) +#define HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_ADDR,m,v,HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_IN) +#define HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_MMSS_QMIP_CORE_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_MMSS_QM_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002b028) +#define HWIO_GCC_MMSS_QM_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002b028) +#define HWIO_GCC_MMSS_QM_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002b028) +#define HWIO_GCC_MMSS_QM_AHB_CBCR_RMSK 0x81d00005 +#define HWIO_GCC_MMSS_QM_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_MMSS_QM_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_MMSS_QM_AHB_CBCR_ADDR, HWIO_GCC_MMSS_QM_AHB_CBCR_RMSK) +#define HWIO_GCC_MMSS_QM_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_MMSS_QM_AHB_CBCR_ADDR, m) +#define HWIO_GCC_MMSS_QM_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_MMSS_QM_AHB_CBCR_ADDR,v) +#define HWIO_GCC_MMSS_QM_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MMSS_QM_AHB_CBCR_ADDR,m,v,HWIO_GCC_MMSS_QM_AHB_CBCR_IN) +#define HWIO_GCC_MMSS_QM_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_MMSS_QM_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_MMSS_QM_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_MMSS_QM_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_MMSS_QM_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_MMSS_QM_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_MMSS_QM_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_MMSS_QM_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_MMSS_QM_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_MMSS_QM_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_MMSS_QM_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_MMSS_QM_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_MMSS_QM_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_MMSS_QM_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_MMSS_QM_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_MMSS_QM_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_MMSS_QM_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMSS_QM_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CAMERA_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00016000) +#define HWIO_GCC_CAMERA_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00016000) +#define HWIO_GCC_CAMERA_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00016000) +#define HWIO_GCC_CAMERA_BCR_RMSK 0x1 +#define HWIO_GCC_CAMERA_BCR_ATTR 0x3 +#define HWIO_GCC_CAMERA_BCR_IN \ + in_dword_masked(HWIO_GCC_CAMERA_BCR_ADDR, HWIO_GCC_CAMERA_BCR_RMSK) +#define HWIO_GCC_CAMERA_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_CAMERA_BCR_ADDR, m) +#define HWIO_GCC_CAMERA_BCR_OUT(v) \ + out_dword(HWIO_GCC_CAMERA_BCR_ADDR,v) +#define HWIO_GCC_CAMERA_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CAMERA_BCR_ADDR,m,v,HWIO_GCC_CAMERA_BCR_IN) +#define HWIO_GCC_CAMERA_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_CAMERA_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_CAMERA_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_CAMERA_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CAMERA_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00016004) +#define HWIO_GCC_CAMERA_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00016004) +#define HWIO_GCC_CAMERA_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00016004) +#define HWIO_GCC_CAMERA_AHB_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_CAMERA_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_CAMERA_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_CAMERA_AHB_CBCR_ADDR, HWIO_GCC_CAMERA_AHB_CBCR_RMSK) +#define HWIO_GCC_CAMERA_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_CAMERA_AHB_CBCR_ADDR, m) +#define HWIO_GCC_CAMERA_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_CAMERA_AHB_CBCR_ADDR,v) +#define HWIO_GCC_CAMERA_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CAMERA_AHB_CBCR_ADDR,m,v,HWIO_GCC_CAMERA_AHB_CBCR_IN) +#define HWIO_GCC_CAMERA_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_CAMERA_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_CAMERA_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_CAMERA_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_CAMERA_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_CAMERA_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_CAMERA_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_CAMERA_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_CAMERA_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_CAMERA_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_CAMERA_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_CAMERA_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_CAMERA_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_CAMERA_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_CAMERA_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_CAMERA_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_CAMERA_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_CAMERA_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_CAMERA_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_CAMERA_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_CAMERA_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_CAMERA_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_CAMERA_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CAMERA_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00016008) +#define HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00016008) +#define HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00016008) +#define HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_ADDR, HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_RMSK) +#define HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_ADDR, m) +#define HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_ADDR,v) +#define HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_ADDR,m,v,HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_IN) +#define HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001600c) +#define HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001600c) +#define HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001600c) +#define HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_ADDR, HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_RMSK) +#define HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_ADDR, m) +#define HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_ADDR,v) +#define HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_ADDR,m,v,HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_IN) +#define HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CAMERA_HF_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00016010) +#define HWIO_GCC_CAMERA_HF_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00016010) +#define HWIO_GCC_CAMERA_HF_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00016010) +#define HWIO_GCC_CAMERA_HF_AXI_CBCR_RMSK 0x81f0700f +#define HWIO_GCC_CAMERA_HF_AXI_CBCR_ATTR 0x3 +#define HWIO_GCC_CAMERA_HF_AXI_CBCR_IN \ + in_dword_masked(HWIO_GCC_CAMERA_HF_AXI_CBCR_ADDR, HWIO_GCC_CAMERA_HF_AXI_CBCR_RMSK) +#define HWIO_GCC_CAMERA_HF_AXI_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_CAMERA_HF_AXI_CBCR_ADDR, m) +#define HWIO_GCC_CAMERA_HF_AXI_CBCR_OUT(v) \ + out_dword(HWIO_GCC_CAMERA_HF_AXI_CBCR_ADDR,v) +#define HWIO_GCC_CAMERA_HF_AXI_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CAMERA_HF_AXI_CBCR_ADDR,m,v,HWIO_GCC_CAMERA_HF_AXI_CBCR_IN) +#define HWIO_GCC_CAMERA_HF_AXI_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_CAMERA_HF_AXI_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_CAMERA_HF_AXI_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_CAMERA_HF_AXI_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_CAMERA_HF_AXI_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_CAMERA_HF_AXI_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_CAMERA_HF_AXI_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_CAMERA_HF_AXI_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_CAMERA_HF_AXI_CBCR_IGNORE_PMU_CLK_DIS_BMSK 0x200000 +#define HWIO_GCC_CAMERA_HF_AXI_CBCR_IGNORE_PMU_CLK_DIS_SHFT 0x15 +#define HWIO_GCC_CAMERA_HF_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_CAMERA_HF_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_CAMERA_HF_AXI_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_CAMERA_HF_AXI_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_CAMERA_HF_AXI_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CAMERA_HF_AXI_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_CAMERA_HF_AXI_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_CAMERA_HF_AXI_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_CAMERA_HF_AXI_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CAMERA_HF_AXI_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_CAMERA_HF_AXI_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_CAMERA_HF_AXI_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_CAMERA_HF_AXI_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CAMERA_HF_AXI_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_CAMERA_HF_AXI_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_CAMERA_HF_AXI_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_CAMERA_HF_AXI_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_CAMERA_HF_AXI_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_CAMERA_HF_AXI_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_CAMERA_HF_AXI_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_CAMERA_HF_AXI_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_CAMERA_HF_AXI_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_CAMERA_HF_AXI_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_CAMERA_HF_AXI_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_CAMERA_HF_AXI_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_CAMERA_HF_AXI_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_CAMERA_HF_AXI_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CAMERA_HF_AXI_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00016014) +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00016014) +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00016014) +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_RMSK 0xf1ffffe +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_ATTR 0x3 +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_IN \ + in_dword_masked(HWIO_GCC_CAMERA_HF_AXI_SREGR_ADDR, HWIO_GCC_CAMERA_HF_AXI_SREGR_RMSK) +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_CAMERA_HF_AXI_SREGR_ADDR, m) +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_OUT(v) \ + out_dword(HWIO_GCC_CAMERA_HF_AXI_SREGR_ADDR,v) +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CAMERA_HF_AXI_SREGR_ADDR,m,v,HWIO_GCC_CAMERA_HF_AXI_SREGR_IN) +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xf000000 +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_PWR_FSM_CLK_SEL_BMSK 0x100000 +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_PWR_FSM_CLK_SEL_SHFT 0x14 +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xf0000 +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_CAMERA_HF_AXI_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CAMERA_HF_AXI_CFG_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00016018) +#define HWIO_GCC_CAMERA_HF_AXI_CFG_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00016018) +#define HWIO_GCC_CAMERA_HF_AXI_CFG_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00016018) +#define HWIO_GCC_CAMERA_HF_AXI_CFG_SREGR_RMSK 0xffffffff +#define HWIO_GCC_CAMERA_HF_AXI_CFG_SREGR_ATTR 0x3 +#define HWIO_GCC_CAMERA_HF_AXI_CFG_SREGR_IN \ + in_dword_masked(HWIO_GCC_CAMERA_HF_AXI_CFG_SREGR_ADDR, HWIO_GCC_CAMERA_HF_AXI_CFG_SREGR_RMSK) +#define HWIO_GCC_CAMERA_HF_AXI_CFG_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_CAMERA_HF_AXI_CFG_SREGR_ADDR, m) +#define HWIO_GCC_CAMERA_HF_AXI_CFG_SREGR_OUT(v) \ + out_dword(HWIO_GCC_CAMERA_HF_AXI_CFG_SREGR_ADDR,v) +#define HWIO_GCC_CAMERA_HF_AXI_CFG_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CAMERA_HF_AXI_CFG_SREGR_ADDR,m,v,HWIO_GCC_CAMERA_HF_AXI_CFG_SREGR_IN) +#define HWIO_GCC_CAMERA_HF_AXI_CFG_SREGR_MEM_CORE_OFF_TIMER_BMSK 0xfc000000 +#define HWIO_GCC_CAMERA_HF_AXI_CFG_SREGR_MEM_CORE_OFF_TIMER_SHFT 0x1a +#define HWIO_GCC_CAMERA_HF_AXI_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_BMSK 0x2000000 +#define HWIO_GCC_CAMERA_HF_AXI_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_SHFT 0x19 +#define HWIO_GCC_CAMERA_HF_AXI_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_BMSK 0x1000000 +#define HWIO_GCC_CAMERA_HF_AXI_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_SHFT 0x18 +#define HWIO_GCC_CAMERA_HF_AXI_CFG_SREGR_MEM_PERIPH_ON_STATUS_BMSK 0x800000 +#define HWIO_GCC_CAMERA_HF_AXI_CFG_SREGR_MEM_PERIPH_ON_STATUS_SHFT 0x17 +#define HWIO_GCC_CAMERA_HF_AXI_CFG_SREGR_MEM_CORE_ON_STATUS_BMSK 0x400000 +#define HWIO_GCC_CAMERA_HF_AXI_CFG_SREGR_MEM_CORE_ON_STATUS_SHFT 0x16 +#define HWIO_GCC_CAMERA_HF_AXI_CFG_SREGR_MEM_CPH_TIMER_BMSK 0x3f0000 +#define HWIO_GCC_CAMERA_HF_AXI_CFG_SREGR_MEM_CPH_TIMER_SHFT 0x10 +#define HWIO_GCC_CAMERA_HF_AXI_CFG_SREGR_SLEEP_TIMER_BMSK 0xff00 +#define HWIO_GCC_CAMERA_HF_AXI_CFG_SREGR_SLEEP_TIMER_SHFT 0x8 +#define HWIO_GCC_CAMERA_HF_AXI_CFG_SREGR_WAKEUP_TIMER_BMSK 0xff +#define HWIO_GCC_CAMERA_HF_AXI_CFG_SREGR_WAKEUP_TIMER_SHFT 0x0 + +#define HWIO_GCC_CAMERA_SF_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001601c) +#define HWIO_GCC_CAMERA_SF_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001601c) +#define HWIO_GCC_CAMERA_SF_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001601c) +#define HWIO_GCC_CAMERA_SF_AXI_CBCR_RMSK 0x81f0700f +#define HWIO_GCC_CAMERA_SF_AXI_CBCR_ATTR 0x3 +#define HWIO_GCC_CAMERA_SF_AXI_CBCR_IN \ + in_dword_masked(HWIO_GCC_CAMERA_SF_AXI_CBCR_ADDR, HWIO_GCC_CAMERA_SF_AXI_CBCR_RMSK) +#define HWIO_GCC_CAMERA_SF_AXI_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_CAMERA_SF_AXI_CBCR_ADDR, m) +#define HWIO_GCC_CAMERA_SF_AXI_CBCR_OUT(v) \ + out_dword(HWIO_GCC_CAMERA_SF_AXI_CBCR_ADDR,v) +#define HWIO_GCC_CAMERA_SF_AXI_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CAMERA_SF_AXI_CBCR_ADDR,m,v,HWIO_GCC_CAMERA_SF_AXI_CBCR_IN) +#define HWIO_GCC_CAMERA_SF_AXI_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_CAMERA_SF_AXI_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_CAMERA_SF_AXI_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_CAMERA_SF_AXI_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_CAMERA_SF_AXI_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_CAMERA_SF_AXI_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_CAMERA_SF_AXI_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_CAMERA_SF_AXI_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_CAMERA_SF_AXI_CBCR_IGNORE_PMU_CLK_DIS_BMSK 0x200000 +#define HWIO_GCC_CAMERA_SF_AXI_CBCR_IGNORE_PMU_CLK_DIS_SHFT 0x15 +#define HWIO_GCC_CAMERA_SF_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_CAMERA_SF_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_CAMERA_SF_AXI_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_CAMERA_SF_AXI_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_CAMERA_SF_AXI_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CAMERA_SF_AXI_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_CAMERA_SF_AXI_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_CAMERA_SF_AXI_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_CAMERA_SF_AXI_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CAMERA_SF_AXI_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_CAMERA_SF_AXI_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_CAMERA_SF_AXI_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_CAMERA_SF_AXI_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CAMERA_SF_AXI_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_CAMERA_SF_AXI_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_CAMERA_SF_AXI_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_CAMERA_SF_AXI_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_CAMERA_SF_AXI_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_CAMERA_SF_AXI_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_CAMERA_SF_AXI_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_CAMERA_SF_AXI_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_CAMERA_SF_AXI_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_CAMERA_SF_AXI_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_CAMERA_SF_AXI_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_CAMERA_SF_AXI_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_CAMERA_SF_AXI_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_CAMERA_SF_AXI_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CAMERA_SF_AXI_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00016020) +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00016020) +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00016020) +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_RMSK 0xf1ffffe +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_ATTR 0x3 +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_IN \ + in_dword_masked(HWIO_GCC_CAMERA_SF_AXI_SREGR_ADDR, HWIO_GCC_CAMERA_SF_AXI_SREGR_RMSK) +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_CAMERA_SF_AXI_SREGR_ADDR, m) +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_OUT(v) \ + out_dword(HWIO_GCC_CAMERA_SF_AXI_SREGR_ADDR,v) +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CAMERA_SF_AXI_SREGR_ADDR,m,v,HWIO_GCC_CAMERA_SF_AXI_SREGR_IN) +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xf000000 +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_PWR_FSM_CLK_SEL_BMSK 0x100000 +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_PWR_FSM_CLK_SEL_SHFT 0x14 +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xf0000 +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_CAMERA_SF_AXI_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CAMERA_SF_AXI_CFG_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00016024) +#define HWIO_GCC_CAMERA_SF_AXI_CFG_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00016024) +#define HWIO_GCC_CAMERA_SF_AXI_CFG_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00016024) +#define HWIO_GCC_CAMERA_SF_AXI_CFG_SREGR_RMSK 0xffffffff +#define HWIO_GCC_CAMERA_SF_AXI_CFG_SREGR_ATTR 0x3 +#define HWIO_GCC_CAMERA_SF_AXI_CFG_SREGR_IN \ + in_dword_masked(HWIO_GCC_CAMERA_SF_AXI_CFG_SREGR_ADDR, HWIO_GCC_CAMERA_SF_AXI_CFG_SREGR_RMSK) +#define HWIO_GCC_CAMERA_SF_AXI_CFG_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_CAMERA_SF_AXI_CFG_SREGR_ADDR, m) +#define HWIO_GCC_CAMERA_SF_AXI_CFG_SREGR_OUT(v) \ + out_dword(HWIO_GCC_CAMERA_SF_AXI_CFG_SREGR_ADDR,v) +#define HWIO_GCC_CAMERA_SF_AXI_CFG_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CAMERA_SF_AXI_CFG_SREGR_ADDR,m,v,HWIO_GCC_CAMERA_SF_AXI_CFG_SREGR_IN) +#define HWIO_GCC_CAMERA_SF_AXI_CFG_SREGR_MEM_CORE_OFF_TIMER_BMSK 0xfc000000 +#define HWIO_GCC_CAMERA_SF_AXI_CFG_SREGR_MEM_CORE_OFF_TIMER_SHFT 0x1a +#define HWIO_GCC_CAMERA_SF_AXI_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_BMSK 0x2000000 +#define HWIO_GCC_CAMERA_SF_AXI_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_SHFT 0x19 +#define HWIO_GCC_CAMERA_SF_AXI_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_BMSK 0x1000000 +#define HWIO_GCC_CAMERA_SF_AXI_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_SHFT 0x18 +#define HWIO_GCC_CAMERA_SF_AXI_CFG_SREGR_MEM_PERIPH_ON_STATUS_BMSK 0x800000 +#define HWIO_GCC_CAMERA_SF_AXI_CFG_SREGR_MEM_PERIPH_ON_STATUS_SHFT 0x17 +#define HWIO_GCC_CAMERA_SF_AXI_CFG_SREGR_MEM_CORE_ON_STATUS_BMSK 0x400000 +#define HWIO_GCC_CAMERA_SF_AXI_CFG_SREGR_MEM_CORE_ON_STATUS_SHFT 0x16 +#define HWIO_GCC_CAMERA_SF_AXI_CFG_SREGR_MEM_CPH_TIMER_BMSK 0x3f0000 +#define HWIO_GCC_CAMERA_SF_AXI_CFG_SREGR_MEM_CPH_TIMER_SHFT 0x10 +#define HWIO_GCC_CAMERA_SF_AXI_CFG_SREGR_SLEEP_TIMER_BMSK 0xff00 +#define HWIO_GCC_CAMERA_SF_AXI_CFG_SREGR_SLEEP_TIMER_SHFT 0x8 +#define HWIO_GCC_CAMERA_SF_AXI_CFG_SREGR_WAKEUP_TIMER_BMSK 0xff +#define HWIO_GCC_CAMERA_SF_AXI_CFG_SREGR_WAKEUP_TIMER_SHFT 0x0 + +#define HWIO_GCC_CAMERA_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00016028) +#define HWIO_GCC_CAMERA_XO_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00016028) +#define HWIO_GCC_CAMERA_XO_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00016028) +#define HWIO_GCC_CAMERA_XO_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_CAMERA_XO_CBCR_ATTR 0x3 +#define HWIO_GCC_CAMERA_XO_CBCR_IN \ + in_dword_masked(HWIO_GCC_CAMERA_XO_CBCR_ADDR, HWIO_GCC_CAMERA_XO_CBCR_RMSK) +#define HWIO_GCC_CAMERA_XO_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_CAMERA_XO_CBCR_ADDR, m) +#define HWIO_GCC_CAMERA_XO_CBCR_OUT(v) \ + out_dword(HWIO_GCC_CAMERA_XO_CBCR_ADDR,v) +#define HWIO_GCC_CAMERA_XO_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CAMERA_XO_CBCR_ADDR,m,v,HWIO_GCC_CAMERA_XO_CBCR_IN) +#define HWIO_GCC_CAMERA_XO_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_CAMERA_XO_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_CAMERA_XO_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_CAMERA_XO_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_CAMERA_XO_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_CAMERA_XO_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_CAMERA_XO_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_CAMERA_XO_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_CAMERA_XO_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_CAMERA_XO_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_CAMERA_XO_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_CAMERA_XO_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_CAMERA_XO_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_CAMERA_XO_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_CAMERA_XO_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CAMERA_XO_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_DISPLAY_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00017000) +#define HWIO_GCC_DISPLAY_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017000) +#define HWIO_GCC_DISPLAY_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017000) +#define HWIO_GCC_DISPLAY_BCR_RMSK 0x1 +#define HWIO_GCC_DISPLAY_BCR_ATTR 0x3 +#define HWIO_GCC_DISPLAY_BCR_IN \ + in_dword_masked(HWIO_GCC_DISPLAY_BCR_ADDR, HWIO_GCC_DISPLAY_BCR_RMSK) +#define HWIO_GCC_DISPLAY_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_DISPLAY_BCR_ADDR, m) +#define HWIO_GCC_DISPLAY_BCR_OUT(v) \ + out_dword(HWIO_GCC_DISPLAY_BCR_ADDR,v) +#define HWIO_GCC_DISPLAY_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DISPLAY_BCR_ADDR,m,v,HWIO_GCC_DISPLAY_BCR_IN) +#define HWIO_GCC_DISPLAY_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_DISPLAY_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_DISPLAY_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_DISPLAY_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_DISP_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00017004) +#define HWIO_GCC_DISP_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017004) +#define HWIO_GCC_DISP_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017004) +#define HWIO_GCC_DISP_AHB_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_DISP_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_DISP_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_DISP_AHB_CBCR_ADDR, HWIO_GCC_DISP_AHB_CBCR_RMSK) +#define HWIO_GCC_DISP_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_DISP_AHB_CBCR_ADDR, m) +#define HWIO_GCC_DISP_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_DISP_AHB_CBCR_ADDR,v) +#define HWIO_GCC_DISP_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DISP_AHB_CBCR_ADDR,m,v,HWIO_GCC_DISP_AHB_CBCR_IN) +#define HWIO_GCC_DISP_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_DISP_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_DISP_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_DISP_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_DISP_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_DISP_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_DISP_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_DISP_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_DISP_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_DISP_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_DISP_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_DISP_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_DISP_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_DISP_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_DISP_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_DISP_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_DISP_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_DISP_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_DISP_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_DISP_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_DISP_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_DISP_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_DISP_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DISP_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QMIP_DISP_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00017008) +#define HWIO_GCC_QMIP_DISP_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017008) +#define HWIO_GCC_QMIP_DISP_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017008) +#define HWIO_GCC_QMIP_DISP_AHB_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_QMIP_DISP_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_QMIP_DISP_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_QMIP_DISP_AHB_CBCR_ADDR, HWIO_GCC_QMIP_DISP_AHB_CBCR_RMSK) +#define HWIO_GCC_QMIP_DISP_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QMIP_DISP_AHB_CBCR_ADDR, m) +#define HWIO_GCC_QMIP_DISP_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QMIP_DISP_AHB_CBCR_ADDR,v) +#define HWIO_GCC_QMIP_DISP_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QMIP_DISP_AHB_CBCR_ADDR,m,v,HWIO_GCC_QMIP_DISP_AHB_CBCR_IN) +#define HWIO_GCC_QMIP_DISP_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QMIP_DISP_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QMIP_DISP_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QMIP_DISP_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QMIP_DISP_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QMIP_DISP_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QMIP_DISP_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QMIP_DISP_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QMIP_DISP_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_QMIP_DISP_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_QMIP_DISP_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_QMIP_DISP_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_QMIP_DISP_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QMIP_DISP_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QMIP_DISP_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QMIP_DISP_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_QMIP_DISP_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_QMIP_DISP_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_QMIP_DISP_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QMIP_DISP_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QMIP_DISP_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_QMIP_DISP_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_QMIP_DISP_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QMIP_DISP_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_DISP_HF_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001700c) +#define HWIO_GCC_DISP_HF_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001700c) +#define HWIO_GCC_DISP_HF_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001700c) +#define HWIO_GCC_DISP_HF_AXI_CBCR_RMSK 0x81f0700f +#define HWIO_GCC_DISP_HF_AXI_CBCR_ATTR 0x3 +#define HWIO_GCC_DISP_HF_AXI_CBCR_IN \ + in_dword_masked(HWIO_GCC_DISP_HF_AXI_CBCR_ADDR, HWIO_GCC_DISP_HF_AXI_CBCR_RMSK) +#define HWIO_GCC_DISP_HF_AXI_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_DISP_HF_AXI_CBCR_ADDR, m) +#define HWIO_GCC_DISP_HF_AXI_CBCR_OUT(v) \ + out_dword(HWIO_GCC_DISP_HF_AXI_CBCR_ADDR,v) +#define HWIO_GCC_DISP_HF_AXI_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DISP_HF_AXI_CBCR_ADDR,m,v,HWIO_GCC_DISP_HF_AXI_CBCR_IN) +#define HWIO_GCC_DISP_HF_AXI_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_DISP_HF_AXI_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_DISP_HF_AXI_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_DISP_HF_AXI_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_DISP_HF_AXI_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_DISP_HF_AXI_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_DISP_HF_AXI_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_DISP_HF_AXI_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_DISP_HF_AXI_CBCR_IGNORE_PMU_CLK_DIS_BMSK 0x200000 +#define HWIO_GCC_DISP_HF_AXI_CBCR_IGNORE_PMU_CLK_DIS_SHFT 0x15 +#define HWIO_GCC_DISP_HF_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_DISP_HF_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_DISP_HF_AXI_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_DISP_HF_AXI_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_DISP_HF_AXI_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DISP_HF_AXI_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_DISP_HF_AXI_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_DISP_HF_AXI_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_DISP_HF_AXI_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DISP_HF_AXI_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_DISP_HF_AXI_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_DISP_HF_AXI_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_DISP_HF_AXI_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DISP_HF_AXI_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_DISP_HF_AXI_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_DISP_HF_AXI_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_DISP_HF_AXI_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_DISP_HF_AXI_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_DISP_HF_AXI_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_DISP_HF_AXI_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_DISP_HF_AXI_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_DISP_HF_AXI_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_DISP_HF_AXI_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_DISP_HF_AXI_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_DISP_HF_AXI_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_DISP_HF_AXI_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_DISP_HF_AXI_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DISP_HF_AXI_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_DISP_HF_AXI_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00017010) +#define HWIO_GCC_DISP_HF_AXI_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017010) +#define HWIO_GCC_DISP_HF_AXI_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017010) +#define HWIO_GCC_DISP_HF_AXI_SREGR_RMSK 0xf1ffffe +#define HWIO_GCC_DISP_HF_AXI_SREGR_ATTR 0x3 +#define HWIO_GCC_DISP_HF_AXI_SREGR_IN \ + in_dword_masked(HWIO_GCC_DISP_HF_AXI_SREGR_ADDR, HWIO_GCC_DISP_HF_AXI_SREGR_RMSK) +#define HWIO_GCC_DISP_HF_AXI_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_DISP_HF_AXI_SREGR_ADDR, m) +#define HWIO_GCC_DISP_HF_AXI_SREGR_OUT(v) \ + out_dword(HWIO_GCC_DISP_HF_AXI_SREGR_ADDR,v) +#define HWIO_GCC_DISP_HF_AXI_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DISP_HF_AXI_SREGR_ADDR,m,v,HWIO_GCC_DISP_HF_AXI_SREGR_IN) +#define HWIO_GCC_DISP_HF_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xf000000 +#define HWIO_GCC_DISP_HF_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_DISP_HF_AXI_SREGR_PWR_FSM_CLK_SEL_BMSK 0x100000 +#define HWIO_GCC_DISP_HF_AXI_SREGR_PWR_FSM_CLK_SEL_SHFT 0x14 +#define HWIO_GCC_DISP_HF_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xf0000 +#define HWIO_GCC_DISP_HF_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_DISP_HF_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_DISP_HF_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_DISP_HF_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_DISP_HF_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_DISP_HF_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_DISP_HF_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_DISP_HF_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_DISP_HF_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_DISP_HF_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_DISP_HF_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_DISP_HF_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_DISP_HF_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_DISP_HF_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_DISP_HF_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_DISP_HF_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_DISP_HF_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_DISP_HF_AXI_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_DISP_HF_AXI_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_DISP_HF_AXI_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_DISP_HF_AXI_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_DISP_HF_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_DISP_HF_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_DISP_HF_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_DISP_HF_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_DISP_HF_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_DISP_HF_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_DISP_HF_AXI_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_DISP_HF_AXI_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_DISP_HF_AXI_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DISP_HF_AXI_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_DISP_HF_AXI_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_DISP_HF_AXI_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_DISP_HF_AXI_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_DISP_HF_AXI_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_DISP_HF_AXI_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_DISP_HF_AXI_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_DISP_HF_AXI_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_DISP_HF_AXI_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_DISP_HF_AXI_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_DISP_HF_AXI_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_DISP_HF_AXI_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_DISP_HF_AXI_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_DISP_HF_AXI_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_DISP_HF_AXI_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_DISP_HF_AXI_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_DISP_HF_AXI_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_DISP_HF_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_DISP_HF_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_DISP_HF_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_DISP_HF_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_DISP_HF_AXI_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_DISP_HF_AXI_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_DISP_HF_AXI_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_DISP_HF_AXI_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_DISP_HF_AXI_CFG_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00017014) +#define HWIO_GCC_DISP_HF_AXI_CFG_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017014) +#define HWIO_GCC_DISP_HF_AXI_CFG_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017014) +#define HWIO_GCC_DISP_HF_AXI_CFG_SREGR_RMSK 0xffffffff +#define HWIO_GCC_DISP_HF_AXI_CFG_SREGR_ATTR 0x3 +#define HWIO_GCC_DISP_HF_AXI_CFG_SREGR_IN \ + in_dword_masked(HWIO_GCC_DISP_HF_AXI_CFG_SREGR_ADDR, HWIO_GCC_DISP_HF_AXI_CFG_SREGR_RMSK) +#define HWIO_GCC_DISP_HF_AXI_CFG_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_DISP_HF_AXI_CFG_SREGR_ADDR, m) +#define HWIO_GCC_DISP_HF_AXI_CFG_SREGR_OUT(v) \ + out_dword(HWIO_GCC_DISP_HF_AXI_CFG_SREGR_ADDR,v) +#define HWIO_GCC_DISP_HF_AXI_CFG_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DISP_HF_AXI_CFG_SREGR_ADDR,m,v,HWIO_GCC_DISP_HF_AXI_CFG_SREGR_IN) +#define HWIO_GCC_DISP_HF_AXI_CFG_SREGR_MEM_CORE_OFF_TIMER_BMSK 0xfc000000 +#define HWIO_GCC_DISP_HF_AXI_CFG_SREGR_MEM_CORE_OFF_TIMER_SHFT 0x1a +#define HWIO_GCC_DISP_HF_AXI_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_BMSK 0x2000000 +#define HWIO_GCC_DISP_HF_AXI_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_SHFT 0x19 +#define HWIO_GCC_DISP_HF_AXI_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_BMSK 0x1000000 +#define HWIO_GCC_DISP_HF_AXI_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_SHFT 0x18 +#define HWIO_GCC_DISP_HF_AXI_CFG_SREGR_MEM_PERIPH_ON_STATUS_BMSK 0x800000 +#define HWIO_GCC_DISP_HF_AXI_CFG_SREGR_MEM_PERIPH_ON_STATUS_SHFT 0x17 +#define HWIO_GCC_DISP_HF_AXI_CFG_SREGR_MEM_CORE_ON_STATUS_BMSK 0x400000 +#define HWIO_GCC_DISP_HF_AXI_CFG_SREGR_MEM_CORE_ON_STATUS_SHFT 0x16 +#define HWIO_GCC_DISP_HF_AXI_CFG_SREGR_MEM_CPH_TIMER_BMSK 0x3f0000 +#define HWIO_GCC_DISP_HF_AXI_CFG_SREGR_MEM_CPH_TIMER_SHFT 0x10 +#define HWIO_GCC_DISP_HF_AXI_CFG_SREGR_SLEEP_TIMER_BMSK 0xff00 +#define HWIO_GCC_DISP_HF_AXI_CFG_SREGR_SLEEP_TIMER_SHFT 0x8 +#define HWIO_GCC_DISP_HF_AXI_CFG_SREGR_WAKEUP_TIMER_BMSK 0xff +#define HWIO_GCC_DISP_HF_AXI_CFG_SREGR_WAKEUP_TIMER_SHFT 0x0 + +#define HWIO_GCC_DISP_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00017018) +#define HWIO_GCC_DISP_XO_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017018) +#define HWIO_GCC_DISP_XO_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017018) +#define HWIO_GCC_DISP_XO_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_DISP_XO_CBCR_ATTR 0x3 +#define HWIO_GCC_DISP_XO_CBCR_IN \ + in_dword_masked(HWIO_GCC_DISP_XO_CBCR_ADDR, HWIO_GCC_DISP_XO_CBCR_RMSK) +#define HWIO_GCC_DISP_XO_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_DISP_XO_CBCR_ADDR, m) +#define HWIO_GCC_DISP_XO_CBCR_OUT(v) \ + out_dword(HWIO_GCC_DISP_XO_CBCR_ADDR,v) +#define HWIO_GCC_DISP_XO_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DISP_XO_CBCR_ADDR,m,v,HWIO_GCC_DISP_XO_CBCR_IN) +#define HWIO_GCC_DISP_XO_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_DISP_XO_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_DISP_XO_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_DISP_XO_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_DISP_XO_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_DISP_XO_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_DISP_XO_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_DISP_XO_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_DISP_XO_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_DISP_XO_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_DISP_XO_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_DISP_XO_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_DISP_XO_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_DISP_XO_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_DISP_XO_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DISP_XO_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_VIDEO_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00022000) +#define HWIO_GCC_VIDEO_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00022000) +#define HWIO_GCC_VIDEO_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00022000) +#define HWIO_GCC_VIDEO_BCR_RMSK 0x1 +#define HWIO_GCC_VIDEO_BCR_ATTR 0x3 +#define HWIO_GCC_VIDEO_BCR_IN \ + in_dword_masked(HWIO_GCC_VIDEO_BCR_ADDR, HWIO_GCC_VIDEO_BCR_RMSK) +#define HWIO_GCC_VIDEO_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_VIDEO_BCR_ADDR, m) +#define HWIO_GCC_VIDEO_BCR_OUT(v) \ + out_dword(HWIO_GCC_VIDEO_BCR_ADDR,v) +#define HWIO_GCC_VIDEO_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_VIDEO_BCR_ADDR,m,v,HWIO_GCC_VIDEO_BCR_IN) +#define HWIO_GCC_VIDEO_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_VIDEO_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_VIDEO_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_VIDEO_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_VIDEO_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00022004) +#define HWIO_GCC_VIDEO_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00022004) +#define HWIO_GCC_VIDEO_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00022004) +#define HWIO_GCC_VIDEO_AHB_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_VIDEO_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_VIDEO_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_VIDEO_AHB_CBCR_ADDR, HWIO_GCC_VIDEO_AHB_CBCR_RMSK) +#define HWIO_GCC_VIDEO_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_VIDEO_AHB_CBCR_ADDR, m) +#define HWIO_GCC_VIDEO_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_VIDEO_AHB_CBCR_ADDR,v) +#define HWIO_GCC_VIDEO_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_VIDEO_AHB_CBCR_ADDR,m,v,HWIO_GCC_VIDEO_AHB_CBCR_IN) +#define HWIO_GCC_VIDEO_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_VIDEO_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_VIDEO_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_VIDEO_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_VIDEO_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_VIDEO_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_VIDEO_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_VIDEO_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_VIDEO_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_VIDEO_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_VIDEO_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_VIDEO_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_VIDEO_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_VIDEO_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_VIDEO_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_VIDEO_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_VIDEO_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_VIDEO_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_VIDEO_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_VIDEO_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_VIDEO_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_VIDEO_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_VIDEO_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_VIDEO_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00022008) +#define HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00022008) +#define HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00022008) +#define HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_ADDR, HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_RMSK) +#define HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_ADDR, m) +#define HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_ADDR,v) +#define HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_ADDR,m,v,HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_IN) +#define HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002200c) +#define HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002200c) +#define HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002200c) +#define HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_ADDR, HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_RMSK) +#define HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_ADDR, m) +#define HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_ADDR,v) +#define HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_ADDR,m,v,HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_IN) +#define HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QMIP_VIDEO_V_CPU_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00022010) +#define HWIO_GCC_QMIP_VIDEO_V_CPU_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00022010) +#define HWIO_GCC_QMIP_VIDEO_V_CPU_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00022010) +#define HWIO_GCC_QMIP_VIDEO_V_CPU_AHB_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_QMIP_VIDEO_V_CPU_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_QMIP_VIDEO_V_CPU_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_QMIP_VIDEO_V_CPU_AHB_CBCR_ADDR, HWIO_GCC_QMIP_VIDEO_V_CPU_AHB_CBCR_RMSK) +#define HWIO_GCC_QMIP_VIDEO_V_CPU_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QMIP_VIDEO_V_CPU_AHB_CBCR_ADDR, m) +#define HWIO_GCC_QMIP_VIDEO_V_CPU_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QMIP_VIDEO_V_CPU_AHB_CBCR_ADDR,v) +#define HWIO_GCC_QMIP_VIDEO_V_CPU_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QMIP_VIDEO_V_CPU_AHB_CBCR_ADDR,m,v,HWIO_GCC_QMIP_VIDEO_V_CPU_AHB_CBCR_IN) +#define HWIO_GCC_QMIP_VIDEO_V_CPU_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QMIP_VIDEO_V_CPU_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QMIP_VIDEO_V_CPU_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QMIP_VIDEO_V_CPU_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QMIP_VIDEO_V_CPU_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QMIP_VIDEO_V_CPU_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QMIP_VIDEO_V_CPU_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QMIP_VIDEO_V_CPU_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QMIP_VIDEO_V_CPU_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_QMIP_VIDEO_V_CPU_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_QMIP_VIDEO_V_CPU_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_QMIP_VIDEO_V_CPU_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_QMIP_VIDEO_V_CPU_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QMIP_VIDEO_V_CPU_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QMIP_VIDEO_V_CPU_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QMIP_VIDEO_V_CPU_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_QMIP_VIDEO_V_CPU_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_QMIP_VIDEO_V_CPU_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_QMIP_VIDEO_V_CPU_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QMIP_VIDEO_V_CPU_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QMIP_VIDEO_V_CPU_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_QMIP_VIDEO_V_CPU_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_QMIP_VIDEO_V_CPU_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QMIP_VIDEO_V_CPU_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QMIP_VIDEO_CV_CPU_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00022014) +#define HWIO_GCC_QMIP_VIDEO_CV_CPU_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00022014) +#define HWIO_GCC_QMIP_VIDEO_CV_CPU_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00022014) +#define HWIO_GCC_QMIP_VIDEO_CV_CPU_AHB_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_QMIP_VIDEO_CV_CPU_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_QMIP_VIDEO_CV_CPU_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_QMIP_VIDEO_CV_CPU_AHB_CBCR_ADDR, HWIO_GCC_QMIP_VIDEO_CV_CPU_AHB_CBCR_RMSK) +#define HWIO_GCC_QMIP_VIDEO_CV_CPU_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QMIP_VIDEO_CV_CPU_AHB_CBCR_ADDR, m) +#define HWIO_GCC_QMIP_VIDEO_CV_CPU_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QMIP_VIDEO_CV_CPU_AHB_CBCR_ADDR,v) +#define HWIO_GCC_QMIP_VIDEO_CV_CPU_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QMIP_VIDEO_CV_CPU_AHB_CBCR_ADDR,m,v,HWIO_GCC_QMIP_VIDEO_CV_CPU_AHB_CBCR_IN) +#define HWIO_GCC_QMIP_VIDEO_CV_CPU_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QMIP_VIDEO_CV_CPU_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QMIP_VIDEO_CV_CPU_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QMIP_VIDEO_CV_CPU_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QMIP_VIDEO_CV_CPU_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QMIP_VIDEO_CV_CPU_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QMIP_VIDEO_CV_CPU_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QMIP_VIDEO_CV_CPU_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QMIP_VIDEO_CV_CPU_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_QMIP_VIDEO_CV_CPU_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_QMIP_VIDEO_CV_CPU_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_QMIP_VIDEO_CV_CPU_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_QMIP_VIDEO_CV_CPU_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QMIP_VIDEO_CV_CPU_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QMIP_VIDEO_CV_CPU_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QMIP_VIDEO_CV_CPU_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_QMIP_VIDEO_CV_CPU_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_QMIP_VIDEO_CV_CPU_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_QMIP_VIDEO_CV_CPU_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QMIP_VIDEO_CV_CPU_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QMIP_VIDEO_CV_CPU_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_QMIP_VIDEO_CV_CPU_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_QMIP_VIDEO_CV_CPU_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QMIP_VIDEO_CV_CPU_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_VIDEO_AXI0_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00022018) +#define HWIO_GCC_VIDEO_AXI0_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00022018) +#define HWIO_GCC_VIDEO_AXI0_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00022018) +#define HWIO_GCC_VIDEO_AXI0_CBCR_RMSK 0x81f0700f +#define HWIO_GCC_VIDEO_AXI0_CBCR_ATTR 0x3 +#define HWIO_GCC_VIDEO_AXI0_CBCR_IN \ + in_dword_masked(HWIO_GCC_VIDEO_AXI0_CBCR_ADDR, HWIO_GCC_VIDEO_AXI0_CBCR_RMSK) +#define HWIO_GCC_VIDEO_AXI0_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_VIDEO_AXI0_CBCR_ADDR, m) +#define HWIO_GCC_VIDEO_AXI0_CBCR_OUT(v) \ + out_dword(HWIO_GCC_VIDEO_AXI0_CBCR_ADDR,v) +#define HWIO_GCC_VIDEO_AXI0_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_VIDEO_AXI0_CBCR_ADDR,m,v,HWIO_GCC_VIDEO_AXI0_CBCR_IN) +#define HWIO_GCC_VIDEO_AXI0_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_VIDEO_AXI0_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_VIDEO_AXI0_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_VIDEO_AXI0_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_VIDEO_AXI0_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_VIDEO_AXI0_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_VIDEO_AXI0_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_VIDEO_AXI0_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_VIDEO_AXI0_CBCR_IGNORE_PMU_CLK_DIS_BMSK 0x200000 +#define HWIO_GCC_VIDEO_AXI0_CBCR_IGNORE_PMU_CLK_DIS_SHFT 0x15 +#define HWIO_GCC_VIDEO_AXI0_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_VIDEO_AXI0_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_VIDEO_AXI0_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_VIDEO_AXI0_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_VIDEO_AXI0_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_VIDEO_AXI0_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_VIDEO_AXI0_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_VIDEO_AXI0_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_VIDEO_AXI0_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_VIDEO_AXI0_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_VIDEO_AXI0_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_VIDEO_AXI0_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_VIDEO_AXI0_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_VIDEO_AXI0_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_VIDEO_AXI0_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_VIDEO_AXI0_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_VIDEO_AXI0_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_VIDEO_AXI0_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_VIDEO_AXI0_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_VIDEO_AXI0_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_VIDEO_AXI0_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_VIDEO_AXI0_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_VIDEO_AXI0_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_VIDEO_AXI0_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_VIDEO_AXI0_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_VIDEO_AXI0_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_VIDEO_AXI0_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_VIDEO_AXI0_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_VIDEO_AXI0_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002201c) +#define HWIO_GCC_VIDEO_AXI0_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002201c) +#define HWIO_GCC_VIDEO_AXI0_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002201c) +#define HWIO_GCC_VIDEO_AXI0_SREGR_RMSK 0xf1ffffe +#define HWIO_GCC_VIDEO_AXI0_SREGR_ATTR 0x3 +#define HWIO_GCC_VIDEO_AXI0_SREGR_IN \ + in_dword_masked(HWIO_GCC_VIDEO_AXI0_SREGR_ADDR, HWIO_GCC_VIDEO_AXI0_SREGR_RMSK) +#define HWIO_GCC_VIDEO_AXI0_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_VIDEO_AXI0_SREGR_ADDR, m) +#define HWIO_GCC_VIDEO_AXI0_SREGR_OUT(v) \ + out_dword(HWIO_GCC_VIDEO_AXI0_SREGR_ADDR,v) +#define HWIO_GCC_VIDEO_AXI0_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_VIDEO_AXI0_SREGR_ADDR,m,v,HWIO_GCC_VIDEO_AXI0_SREGR_IN) +#define HWIO_GCC_VIDEO_AXI0_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xf000000 +#define HWIO_GCC_VIDEO_AXI0_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_VIDEO_AXI0_SREGR_PWR_FSM_CLK_SEL_BMSK 0x100000 +#define HWIO_GCC_VIDEO_AXI0_SREGR_PWR_FSM_CLK_SEL_SHFT 0x14 +#define HWIO_GCC_VIDEO_AXI0_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xf0000 +#define HWIO_GCC_VIDEO_AXI0_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_VIDEO_AXI0_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_VIDEO_AXI0_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_VIDEO_AXI0_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_VIDEO_AXI0_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_VIDEO_AXI0_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_VIDEO_AXI0_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_VIDEO_AXI0_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_VIDEO_AXI0_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_VIDEO_AXI0_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_VIDEO_AXI0_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_VIDEO_AXI0_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_VIDEO_AXI0_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_VIDEO_AXI0_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_VIDEO_AXI0_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_VIDEO_AXI0_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_VIDEO_AXI0_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_VIDEO_AXI0_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_VIDEO_AXI0_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_VIDEO_AXI0_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_VIDEO_AXI0_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_VIDEO_AXI0_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_VIDEO_AXI0_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_VIDEO_AXI0_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_VIDEO_AXI0_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_VIDEO_AXI0_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_VIDEO_AXI0_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_VIDEO_AXI0_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_VIDEO_AXI0_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_VIDEO_AXI0_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_VIDEO_AXI0_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_VIDEO_AXI0_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_VIDEO_AXI0_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_VIDEO_AXI0_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_VIDEO_AXI0_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_VIDEO_AXI0_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_VIDEO_AXI0_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_VIDEO_AXI0_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_VIDEO_AXI0_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_VIDEO_AXI0_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_VIDEO_AXI0_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_VIDEO_AXI0_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_VIDEO_AXI0_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_VIDEO_AXI0_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_VIDEO_AXI0_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_VIDEO_AXI0_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_VIDEO_AXI0_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_VIDEO_AXI0_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_VIDEO_AXI0_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_VIDEO_AXI0_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_VIDEO_AXI0_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_VIDEO_AXI0_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_VIDEO_AXI0_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_VIDEO_AXI0_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_VIDEO_AXI0_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_VIDEO_AXI0_CFG_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00022020) +#define HWIO_GCC_VIDEO_AXI0_CFG_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00022020) +#define HWIO_GCC_VIDEO_AXI0_CFG_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00022020) +#define HWIO_GCC_VIDEO_AXI0_CFG_SREGR_RMSK 0xffffffff +#define HWIO_GCC_VIDEO_AXI0_CFG_SREGR_ATTR 0x3 +#define HWIO_GCC_VIDEO_AXI0_CFG_SREGR_IN \ + in_dword_masked(HWIO_GCC_VIDEO_AXI0_CFG_SREGR_ADDR, HWIO_GCC_VIDEO_AXI0_CFG_SREGR_RMSK) +#define HWIO_GCC_VIDEO_AXI0_CFG_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_VIDEO_AXI0_CFG_SREGR_ADDR, m) +#define HWIO_GCC_VIDEO_AXI0_CFG_SREGR_OUT(v) \ + out_dword(HWIO_GCC_VIDEO_AXI0_CFG_SREGR_ADDR,v) +#define HWIO_GCC_VIDEO_AXI0_CFG_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_VIDEO_AXI0_CFG_SREGR_ADDR,m,v,HWIO_GCC_VIDEO_AXI0_CFG_SREGR_IN) +#define HWIO_GCC_VIDEO_AXI0_CFG_SREGR_MEM_CORE_OFF_TIMER_BMSK 0xfc000000 +#define HWIO_GCC_VIDEO_AXI0_CFG_SREGR_MEM_CORE_OFF_TIMER_SHFT 0x1a +#define HWIO_GCC_VIDEO_AXI0_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_BMSK 0x2000000 +#define HWIO_GCC_VIDEO_AXI0_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_SHFT 0x19 +#define HWIO_GCC_VIDEO_AXI0_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_BMSK 0x1000000 +#define HWIO_GCC_VIDEO_AXI0_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_SHFT 0x18 +#define HWIO_GCC_VIDEO_AXI0_CFG_SREGR_MEM_PERIPH_ON_STATUS_BMSK 0x800000 +#define HWIO_GCC_VIDEO_AXI0_CFG_SREGR_MEM_PERIPH_ON_STATUS_SHFT 0x17 +#define HWIO_GCC_VIDEO_AXI0_CFG_SREGR_MEM_CORE_ON_STATUS_BMSK 0x400000 +#define HWIO_GCC_VIDEO_AXI0_CFG_SREGR_MEM_CORE_ON_STATUS_SHFT 0x16 +#define HWIO_GCC_VIDEO_AXI0_CFG_SREGR_MEM_CPH_TIMER_BMSK 0x3f0000 +#define HWIO_GCC_VIDEO_AXI0_CFG_SREGR_MEM_CPH_TIMER_SHFT 0x10 +#define HWIO_GCC_VIDEO_AXI0_CFG_SREGR_SLEEP_TIMER_BMSK 0xff00 +#define HWIO_GCC_VIDEO_AXI0_CFG_SREGR_SLEEP_TIMER_SHFT 0x8 +#define HWIO_GCC_VIDEO_AXI0_CFG_SREGR_WAKEUP_TIMER_BMSK 0xff +#define HWIO_GCC_VIDEO_AXI0_CFG_SREGR_WAKEUP_TIMER_SHFT 0x0 + +#define HWIO_GCC_VIDEO_AXI1_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00022024) +#define HWIO_GCC_VIDEO_AXI1_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00022024) +#define HWIO_GCC_VIDEO_AXI1_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00022024) +#define HWIO_GCC_VIDEO_AXI1_CBCR_RMSK 0x81f0700f +#define HWIO_GCC_VIDEO_AXI1_CBCR_ATTR 0x3 +#define HWIO_GCC_VIDEO_AXI1_CBCR_IN \ + in_dword_masked(HWIO_GCC_VIDEO_AXI1_CBCR_ADDR, HWIO_GCC_VIDEO_AXI1_CBCR_RMSK) +#define HWIO_GCC_VIDEO_AXI1_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_VIDEO_AXI1_CBCR_ADDR, m) +#define HWIO_GCC_VIDEO_AXI1_CBCR_OUT(v) \ + out_dword(HWIO_GCC_VIDEO_AXI1_CBCR_ADDR,v) +#define HWIO_GCC_VIDEO_AXI1_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_VIDEO_AXI1_CBCR_ADDR,m,v,HWIO_GCC_VIDEO_AXI1_CBCR_IN) +#define HWIO_GCC_VIDEO_AXI1_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_VIDEO_AXI1_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_VIDEO_AXI1_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_VIDEO_AXI1_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_VIDEO_AXI1_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_VIDEO_AXI1_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_VIDEO_AXI1_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_VIDEO_AXI1_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_VIDEO_AXI1_CBCR_IGNORE_PMU_CLK_DIS_BMSK 0x200000 +#define HWIO_GCC_VIDEO_AXI1_CBCR_IGNORE_PMU_CLK_DIS_SHFT 0x15 +#define HWIO_GCC_VIDEO_AXI1_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_VIDEO_AXI1_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_VIDEO_AXI1_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_VIDEO_AXI1_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_VIDEO_AXI1_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_VIDEO_AXI1_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_VIDEO_AXI1_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_VIDEO_AXI1_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_VIDEO_AXI1_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_VIDEO_AXI1_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_VIDEO_AXI1_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_VIDEO_AXI1_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_VIDEO_AXI1_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_VIDEO_AXI1_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_VIDEO_AXI1_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_VIDEO_AXI1_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_VIDEO_AXI1_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_VIDEO_AXI1_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_VIDEO_AXI1_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_VIDEO_AXI1_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_VIDEO_AXI1_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_VIDEO_AXI1_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_VIDEO_AXI1_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_VIDEO_AXI1_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_VIDEO_AXI1_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_VIDEO_AXI1_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_VIDEO_AXI1_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_VIDEO_AXI1_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_VIDEO_AXI1_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00022028) +#define HWIO_GCC_VIDEO_AXI1_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00022028) +#define HWIO_GCC_VIDEO_AXI1_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00022028) +#define HWIO_GCC_VIDEO_AXI1_SREGR_RMSK 0xf1ffffe +#define HWIO_GCC_VIDEO_AXI1_SREGR_ATTR 0x3 +#define HWIO_GCC_VIDEO_AXI1_SREGR_IN \ + in_dword_masked(HWIO_GCC_VIDEO_AXI1_SREGR_ADDR, HWIO_GCC_VIDEO_AXI1_SREGR_RMSK) +#define HWIO_GCC_VIDEO_AXI1_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_VIDEO_AXI1_SREGR_ADDR, m) +#define HWIO_GCC_VIDEO_AXI1_SREGR_OUT(v) \ + out_dword(HWIO_GCC_VIDEO_AXI1_SREGR_ADDR,v) +#define HWIO_GCC_VIDEO_AXI1_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_VIDEO_AXI1_SREGR_ADDR,m,v,HWIO_GCC_VIDEO_AXI1_SREGR_IN) +#define HWIO_GCC_VIDEO_AXI1_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xf000000 +#define HWIO_GCC_VIDEO_AXI1_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_VIDEO_AXI1_SREGR_PWR_FSM_CLK_SEL_BMSK 0x100000 +#define HWIO_GCC_VIDEO_AXI1_SREGR_PWR_FSM_CLK_SEL_SHFT 0x14 +#define HWIO_GCC_VIDEO_AXI1_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xf0000 +#define HWIO_GCC_VIDEO_AXI1_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_VIDEO_AXI1_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_VIDEO_AXI1_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_VIDEO_AXI1_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_VIDEO_AXI1_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_VIDEO_AXI1_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_VIDEO_AXI1_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_VIDEO_AXI1_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_VIDEO_AXI1_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_VIDEO_AXI1_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_VIDEO_AXI1_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_VIDEO_AXI1_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_VIDEO_AXI1_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_VIDEO_AXI1_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_VIDEO_AXI1_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_VIDEO_AXI1_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_VIDEO_AXI1_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_VIDEO_AXI1_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_VIDEO_AXI1_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_VIDEO_AXI1_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_VIDEO_AXI1_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_VIDEO_AXI1_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_VIDEO_AXI1_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_VIDEO_AXI1_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_VIDEO_AXI1_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_VIDEO_AXI1_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_VIDEO_AXI1_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_VIDEO_AXI1_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_VIDEO_AXI1_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_VIDEO_AXI1_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_VIDEO_AXI1_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_VIDEO_AXI1_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_VIDEO_AXI1_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_VIDEO_AXI1_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_VIDEO_AXI1_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_VIDEO_AXI1_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_VIDEO_AXI1_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_VIDEO_AXI1_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_VIDEO_AXI1_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_VIDEO_AXI1_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_VIDEO_AXI1_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_VIDEO_AXI1_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_VIDEO_AXI1_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_VIDEO_AXI1_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_VIDEO_AXI1_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_VIDEO_AXI1_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_VIDEO_AXI1_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_VIDEO_AXI1_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_VIDEO_AXI1_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_VIDEO_AXI1_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_VIDEO_AXI1_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_VIDEO_AXI1_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_VIDEO_AXI1_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_VIDEO_AXI1_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_VIDEO_AXI1_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_VIDEO_AXI1_CFG_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002202c) +#define HWIO_GCC_VIDEO_AXI1_CFG_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002202c) +#define HWIO_GCC_VIDEO_AXI1_CFG_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002202c) +#define HWIO_GCC_VIDEO_AXI1_CFG_SREGR_RMSK 0xffffffff +#define HWIO_GCC_VIDEO_AXI1_CFG_SREGR_ATTR 0x3 +#define HWIO_GCC_VIDEO_AXI1_CFG_SREGR_IN \ + in_dword_masked(HWIO_GCC_VIDEO_AXI1_CFG_SREGR_ADDR, HWIO_GCC_VIDEO_AXI1_CFG_SREGR_RMSK) +#define HWIO_GCC_VIDEO_AXI1_CFG_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_VIDEO_AXI1_CFG_SREGR_ADDR, m) +#define HWIO_GCC_VIDEO_AXI1_CFG_SREGR_OUT(v) \ + out_dword(HWIO_GCC_VIDEO_AXI1_CFG_SREGR_ADDR,v) +#define HWIO_GCC_VIDEO_AXI1_CFG_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_VIDEO_AXI1_CFG_SREGR_ADDR,m,v,HWIO_GCC_VIDEO_AXI1_CFG_SREGR_IN) +#define HWIO_GCC_VIDEO_AXI1_CFG_SREGR_MEM_CORE_OFF_TIMER_BMSK 0xfc000000 +#define HWIO_GCC_VIDEO_AXI1_CFG_SREGR_MEM_CORE_OFF_TIMER_SHFT 0x1a +#define HWIO_GCC_VIDEO_AXI1_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_BMSK 0x2000000 +#define HWIO_GCC_VIDEO_AXI1_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_SHFT 0x19 +#define HWIO_GCC_VIDEO_AXI1_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_BMSK 0x1000000 +#define HWIO_GCC_VIDEO_AXI1_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_SHFT 0x18 +#define HWIO_GCC_VIDEO_AXI1_CFG_SREGR_MEM_PERIPH_ON_STATUS_BMSK 0x800000 +#define HWIO_GCC_VIDEO_AXI1_CFG_SREGR_MEM_PERIPH_ON_STATUS_SHFT 0x17 +#define HWIO_GCC_VIDEO_AXI1_CFG_SREGR_MEM_CORE_ON_STATUS_BMSK 0x400000 +#define HWIO_GCC_VIDEO_AXI1_CFG_SREGR_MEM_CORE_ON_STATUS_SHFT 0x16 +#define HWIO_GCC_VIDEO_AXI1_CFG_SREGR_MEM_CPH_TIMER_BMSK 0x3f0000 +#define HWIO_GCC_VIDEO_AXI1_CFG_SREGR_MEM_CPH_TIMER_SHFT 0x10 +#define HWIO_GCC_VIDEO_AXI1_CFG_SREGR_SLEEP_TIMER_BMSK 0xff00 +#define HWIO_GCC_VIDEO_AXI1_CFG_SREGR_SLEEP_TIMER_SHFT 0x8 +#define HWIO_GCC_VIDEO_AXI1_CFG_SREGR_WAKEUP_TIMER_BMSK 0xff +#define HWIO_GCC_VIDEO_AXI1_CFG_SREGR_WAKEUP_TIMER_SHFT 0x0 + +#define HWIO_GCC_VIDEO_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00022030) +#define HWIO_GCC_VIDEO_XO_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00022030) +#define HWIO_GCC_VIDEO_XO_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00022030) +#define HWIO_GCC_VIDEO_XO_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_VIDEO_XO_CBCR_ATTR 0x3 +#define HWIO_GCC_VIDEO_XO_CBCR_IN \ + in_dword_masked(HWIO_GCC_VIDEO_XO_CBCR_ADDR, HWIO_GCC_VIDEO_XO_CBCR_RMSK) +#define HWIO_GCC_VIDEO_XO_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_VIDEO_XO_CBCR_ADDR, m) +#define HWIO_GCC_VIDEO_XO_CBCR_OUT(v) \ + out_dword(HWIO_GCC_VIDEO_XO_CBCR_ADDR,v) +#define HWIO_GCC_VIDEO_XO_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_VIDEO_XO_CBCR_ADDR,m,v,HWIO_GCC_VIDEO_XO_CBCR_IN) +#define HWIO_GCC_VIDEO_XO_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_VIDEO_XO_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_VIDEO_XO_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_VIDEO_XO_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_VIDEO_XO_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_VIDEO_XO_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_VIDEO_XO_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_VIDEO_XO_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_VIDEO_XO_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_VIDEO_XO_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_VIDEO_XO_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_VIDEO_XO_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_VIDEO_XO_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_VIDEO_XO_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_VIDEO_XO_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_VIDEO_XO_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QDSS_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f000) +#define HWIO_GCC_QDSS_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f000) +#define HWIO_GCC_QDSS_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f000) +#define HWIO_GCC_QDSS_BCR_RMSK 0x1 +#define HWIO_GCC_QDSS_BCR_ATTR 0x3 +#define HWIO_GCC_QDSS_BCR_IN \ + in_dword_masked(HWIO_GCC_QDSS_BCR_ADDR, HWIO_GCC_QDSS_BCR_RMSK) +#define HWIO_GCC_QDSS_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_QDSS_BCR_ADDR, m) +#define HWIO_GCC_QDSS_BCR_OUT(v) \ + out_dword(HWIO_GCC_QDSS_BCR_ADDR,v) +#define HWIO_GCC_QDSS_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QDSS_BCR_ADDR,m,v,HWIO_GCC_QDSS_BCR_IN) +#define HWIO_GCC_QDSS_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_QDSS_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_QDSS_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f004) +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f004) +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f004) +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_QDSS_DAP_AHB_CBCR_ADDR, HWIO_GCC_QDSS_DAP_AHB_CBCR_RMSK) +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QDSS_DAP_AHB_CBCR_ADDR, m) +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QDSS_DAP_AHB_CBCR_ADDR,v) +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QDSS_DAP_AHB_CBCR_ADDR,m,v,HWIO_GCC_QDSS_DAP_AHB_CBCR_IN) +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f008) +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f008) +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f008) +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_RMSK 0x81d0000e +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_QDSS_CFG_AHB_CBCR_ADDR, HWIO_GCC_QDSS_CFG_AHB_CBCR_RMSK) +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QDSS_CFG_AHB_CBCR_ADDR, m) +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QDSS_CFG_AHB_CBCR_ADDR,v) +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QDSS_CFG_AHB_CBCR_ADDR,m,v,HWIO_GCC_QDSS_CFG_AHB_CBCR_IN) +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QDSS_CENTER_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f00c) +#define HWIO_GCC_QDSS_CENTER_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f00c) +#define HWIO_GCC_QDSS_CENTER_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f00c) +#define HWIO_GCC_QDSS_CENTER_AT_CBCR_RMSK 0x81d0700f +#define HWIO_GCC_QDSS_CENTER_AT_CBCR_ATTR 0x3 +#define HWIO_GCC_QDSS_CENTER_AT_CBCR_IN \ + in_dword_masked(HWIO_GCC_QDSS_CENTER_AT_CBCR_ADDR, HWIO_GCC_QDSS_CENTER_AT_CBCR_RMSK) +#define HWIO_GCC_QDSS_CENTER_AT_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QDSS_CENTER_AT_CBCR_ADDR, m) +#define HWIO_GCC_QDSS_CENTER_AT_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QDSS_CENTER_AT_CBCR_ADDR,v) +#define HWIO_GCC_QDSS_CENTER_AT_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QDSS_CENTER_AT_CBCR_ADDR,m,v,HWIO_GCC_QDSS_CENTER_AT_CBCR_IN) +#define HWIO_GCC_QDSS_CENTER_AT_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QDSS_CENTER_AT_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QDSS_CENTER_AT_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QDSS_CENTER_AT_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QDSS_CENTER_AT_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QDSS_CENTER_AT_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QDSS_CENTER_AT_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QDSS_CENTER_AT_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QDSS_CENTER_AT_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_QDSS_CENTER_AT_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_QDSS_CENTER_AT_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_QDSS_CENTER_AT_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_QDSS_CENTER_AT_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_CENTER_AT_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QDSS_CENTER_AT_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_QDSS_CENTER_AT_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_QDSS_CENTER_AT_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_CENTER_AT_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QDSS_CENTER_AT_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_QDSS_CENTER_AT_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_QDSS_CENTER_AT_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_CENTER_AT_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QDSS_CENTER_AT_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_QDSS_CENTER_AT_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_QDSS_CENTER_AT_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QDSS_CENTER_AT_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QDSS_CENTER_AT_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QDSS_CENTER_AT_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_QDSS_CENTER_AT_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_QDSS_CENTER_AT_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_QDSS_CENTER_AT_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_CENTER_AT_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QDSS_CENTER_AT_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_QDSS_CENTER_AT_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_QDSS_CENTER_AT_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_CENTER_AT_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f010) +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f010) +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f010) +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_RMSK 0xf1ffffe +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_ATTR 0x3 +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_IN \ + in_dword_masked(HWIO_GCC_QDSS_CENTER_AT_SREGR_ADDR, HWIO_GCC_QDSS_CENTER_AT_SREGR_RMSK) +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_QDSS_CENTER_AT_SREGR_ADDR, m) +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_OUT(v) \ + out_dword(HWIO_GCC_QDSS_CENTER_AT_SREGR_ADDR,v) +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QDSS_CENTER_AT_SREGR_ADDR,m,v,HWIO_GCC_QDSS_CENTER_AT_SREGR_IN) +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xf000000 +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_PWR_FSM_CLK_SEL_BMSK 0x100000 +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_PWR_FSM_CLK_SEL_SHFT 0x14 +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xf0000 +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_CENTER_AT_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QDSS_CENTER_AT_CFG_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f014) +#define HWIO_GCC_QDSS_CENTER_AT_CFG_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f014) +#define HWIO_GCC_QDSS_CENTER_AT_CFG_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f014) +#define HWIO_GCC_QDSS_CENTER_AT_CFG_SREGR_RMSK 0xffffffff +#define HWIO_GCC_QDSS_CENTER_AT_CFG_SREGR_ATTR 0x3 +#define HWIO_GCC_QDSS_CENTER_AT_CFG_SREGR_IN \ + in_dword_masked(HWIO_GCC_QDSS_CENTER_AT_CFG_SREGR_ADDR, HWIO_GCC_QDSS_CENTER_AT_CFG_SREGR_RMSK) +#define HWIO_GCC_QDSS_CENTER_AT_CFG_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_QDSS_CENTER_AT_CFG_SREGR_ADDR, m) +#define HWIO_GCC_QDSS_CENTER_AT_CFG_SREGR_OUT(v) \ + out_dword(HWIO_GCC_QDSS_CENTER_AT_CFG_SREGR_ADDR,v) +#define HWIO_GCC_QDSS_CENTER_AT_CFG_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QDSS_CENTER_AT_CFG_SREGR_ADDR,m,v,HWIO_GCC_QDSS_CENTER_AT_CFG_SREGR_IN) +#define HWIO_GCC_QDSS_CENTER_AT_CFG_SREGR_MEM_CORE_OFF_TIMER_BMSK 0xfc000000 +#define HWIO_GCC_QDSS_CENTER_AT_CFG_SREGR_MEM_CORE_OFF_TIMER_SHFT 0x1a +#define HWIO_GCC_QDSS_CENTER_AT_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_BMSK 0x2000000 +#define HWIO_GCC_QDSS_CENTER_AT_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_SHFT 0x19 +#define HWIO_GCC_QDSS_CENTER_AT_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_BMSK 0x1000000 +#define HWIO_GCC_QDSS_CENTER_AT_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_SHFT 0x18 +#define HWIO_GCC_QDSS_CENTER_AT_CFG_SREGR_MEM_PERIPH_ON_STATUS_BMSK 0x800000 +#define HWIO_GCC_QDSS_CENTER_AT_CFG_SREGR_MEM_PERIPH_ON_STATUS_SHFT 0x17 +#define HWIO_GCC_QDSS_CENTER_AT_CFG_SREGR_MEM_CORE_ON_STATUS_BMSK 0x400000 +#define HWIO_GCC_QDSS_CENTER_AT_CFG_SREGR_MEM_CORE_ON_STATUS_SHFT 0x16 +#define HWIO_GCC_QDSS_CENTER_AT_CFG_SREGR_MEM_CPH_TIMER_BMSK 0x3f0000 +#define HWIO_GCC_QDSS_CENTER_AT_CFG_SREGR_MEM_CPH_TIMER_SHFT 0x10 +#define HWIO_GCC_QDSS_CENTER_AT_CFG_SREGR_SLEEP_TIMER_BMSK 0xff00 +#define HWIO_GCC_QDSS_CENTER_AT_CFG_SREGR_SLEEP_TIMER_SHFT 0x8 +#define HWIO_GCC_QDSS_CENTER_AT_CFG_SREGR_WAKEUP_TIMER_BMSK 0xff +#define HWIO_GCC_QDSS_CENTER_AT_CFG_SREGR_WAKEUP_TIMER_SHFT 0x0 + +#define HWIO_GCC_SOUTH_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f018) +#define HWIO_GCC_SOUTH_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f018) +#define HWIO_GCC_SOUTH_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f018) +#define HWIO_GCC_SOUTH_AT_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_SOUTH_AT_CBCR_ATTR 0x3 +#define HWIO_GCC_SOUTH_AT_CBCR_IN \ + in_dword_masked(HWIO_GCC_SOUTH_AT_CBCR_ADDR, HWIO_GCC_SOUTH_AT_CBCR_RMSK) +#define HWIO_GCC_SOUTH_AT_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_SOUTH_AT_CBCR_ADDR, m) +#define HWIO_GCC_SOUTH_AT_CBCR_OUT(v) \ + out_dword(HWIO_GCC_SOUTH_AT_CBCR_ADDR,v) +#define HWIO_GCC_SOUTH_AT_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SOUTH_AT_CBCR_ADDR,m,v,HWIO_GCC_SOUTH_AT_CBCR_IN) +#define HWIO_GCC_SOUTH_AT_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SOUTH_AT_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SOUTH_AT_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_SOUTH_AT_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_SOUTH_AT_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_SOUTH_AT_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_SOUTH_AT_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_SOUTH_AT_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_SOUTH_AT_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_SOUTH_AT_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_SOUTH_AT_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_SOUTH_AT_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_SOUTH_AT_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_SOUTH_AT_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_SOUTH_AT_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SOUTH_AT_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_SOUTH_AT_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_SOUTH_AT_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_SOUTH_AT_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_SOUTH_AT_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_SOUTH_AT_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SOUTH_AT_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SOUTH_AT_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SOUTH_AT_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_WEST_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f01c) +#define HWIO_GCC_WEST_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f01c) +#define HWIO_GCC_WEST_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f01c) +#define HWIO_GCC_WEST_AT_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_WEST_AT_CBCR_ATTR 0x3 +#define HWIO_GCC_WEST_AT_CBCR_IN \ + in_dword_masked(HWIO_GCC_WEST_AT_CBCR_ADDR, HWIO_GCC_WEST_AT_CBCR_RMSK) +#define HWIO_GCC_WEST_AT_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_WEST_AT_CBCR_ADDR, m) +#define HWIO_GCC_WEST_AT_CBCR_OUT(v) \ + out_dword(HWIO_GCC_WEST_AT_CBCR_ADDR,v) +#define HWIO_GCC_WEST_AT_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_WEST_AT_CBCR_ADDR,m,v,HWIO_GCC_WEST_AT_CBCR_IN) +#define HWIO_GCC_WEST_AT_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_WEST_AT_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_WEST_AT_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_WEST_AT_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_WEST_AT_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_WEST_AT_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_WEST_AT_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_WEST_AT_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_WEST_AT_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_WEST_AT_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_WEST_AT_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_WEST_AT_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_WEST_AT_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_WEST_AT_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_WEST_AT_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_WEST_AT_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_WEST_AT_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_WEST_AT_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_WEST_AT_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_WEST_AT_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_WEST_AT_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_WEST_AT_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_WEST_AT_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_WEST_AT_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_NORTH_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f020) +#define HWIO_GCC_NORTH_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f020) +#define HWIO_GCC_NORTH_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f020) +#define HWIO_GCC_NORTH_AT_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_NORTH_AT_CBCR_ATTR 0x3 +#define HWIO_GCC_NORTH_AT_CBCR_IN \ + in_dword_masked(HWIO_GCC_NORTH_AT_CBCR_ADDR, HWIO_GCC_NORTH_AT_CBCR_RMSK) +#define HWIO_GCC_NORTH_AT_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_NORTH_AT_CBCR_ADDR, m) +#define HWIO_GCC_NORTH_AT_CBCR_OUT(v) \ + out_dword(HWIO_GCC_NORTH_AT_CBCR_ADDR,v) +#define HWIO_GCC_NORTH_AT_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_NORTH_AT_CBCR_ADDR,m,v,HWIO_GCC_NORTH_AT_CBCR_IN) +#define HWIO_GCC_NORTH_AT_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_NORTH_AT_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_NORTH_AT_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_NORTH_AT_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_NORTH_AT_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_NORTH_AT_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_NORTH_AT_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_NORTH_AT_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_NORTH_AT_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_NORTH_AT_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_NORTH_AT_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_NORTH_AT_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_NORTH_AT_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_NORTH_AT_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_NORTH_AT_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_NORTH_AT_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_NORTH_AT_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_NORTH_AT_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_NORTH_AT_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_NORTH_AT_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_NORTH_AT_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_NORTH_AT_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_NORTH_AT_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_NORTH_AT_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PHY_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f024) +#define HWIO_GCC_PHY_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f024) +#define HWIO_GCC_PHY_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f024) +#define HWIO_GCC_PHY_AT_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_PHY_AT_CBCR_ATTR 0x3 +#define HWIO_GCC_PHY_AT_CBCR_IN \ + in_dword_masked(HWIO_GCC_PHY_AT_CBCR_ADDR, HWIO_GCC_PHY_AT_CBCR_RMSK) +#define HWIO_GCC_PHY_AT_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_PHY_AT_CBCR_ADDR, m) +#define HWIO_GCC_PHY_AT_CBCR_OUT(v) \ + out_dword(HWIO_GCC_PHY_AT_CBCR_ADDR,v) +#define HWIO_GCC_PHY_AT_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PHY_AT_CBCR_ADDR,m,v,HWIO_GCC_PHY_AT_CBCR_IN) +#define HWIO_GCC_PHY_AT_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_PHY_AT_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_PHY_AT_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_PHY_AT_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_PHY_AT_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_PHY_AT_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_PHY_AT_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_PHY_AT_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_PHY_AT_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_PHY_AT_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_PHY_AT_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_PHY_AT_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_PHY_AT_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_PHY_AT_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_PHY_AT_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_PHY_AT_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_PHY_AT_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_PHY_AT_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_PHY_AT_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_PHY_AT_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_PHY_AT_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_PHY_AT_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_PHY_AT_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PHY_AT_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QDSS_ETR_USB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00029094) +#define HWIO_GCC_QDSS_ETR_USB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00029094) +#define HWIO_GCC_QDSS_ETR_USB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00029094) +#define HWIO_GCC_QDSS_ETR_USB_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_QDSS_ETR_USB_CBCR_ATTR 0x3 +#define HWIO_GCC_QDSS_ETR_USB_CBCR_IN \ + in_dword_masked(HWIO_GCC_QDSS_ETR_USB_CBCR_ADDR, HWIO_GCC_QDSS_ETR_USB_CBCR_RMSK) +#define HWIO_GCC_QDSS_ETR_USB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QDSS_ETR_USB_CBCR_ADDR, m) +#define HWIO_GCC_QDSS_ETR_USB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QDSS_ETR_USB_CBCR_ADDR,v) +#define HWIO_GCC_QDSS_ETR_USB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QDSS_ETR_USB_CBCR_ADDR,m,v,HWIO_GCC_QDSS_ETR_USB_CBCR_IN) +#define HWIO_GCC_QDSS_ETR_USB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QDSS_ETR_USB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QDSS_ETR_USB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QDSS_ETR_USB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QDSS_ETR_USB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QDSS_ETR_USB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QDSS_ETR_USB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QDSS_ETR_USB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QDSS_ETR_USB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_QDSS_ETR_USB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_QDSS_ETR_USB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_QDSS_ETR_USB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_QDSS_ETR_USB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QDSS_ETR_USB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QDSS_ETR_USB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QDSS_ETR_USB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_QDSS_ETR_USB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_QDSS_ETR_USB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_QDSS_ETR_USB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_ETR_USB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QDSS_ETR_USB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_QDSS_ETR_USB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_QDSS_ETR_USB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_ETR_USB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QDSS_ETR_DDR_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f028) +#define HWIO_GCC_QDSS_ETR_DDR_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f028) +#define HWIO_GCC_QDSS_ETR_DDR_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f028) +#define HWIO_GCC_QDSS_ETR_DDR_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_QDSS_ETR_DDR_CBCR_ATTR 0x3 +#define HWIO_GCC_QDSS_ETR_DDR_CBCR_IN \ + in_dword_masked(HWIO_GCC_QDSS_ETR_DDR_CBCR_ADDR, HWIO_GCC_QDSS_ETR_DDR_CBCR_RMSK) +#define HWIO_GCC_QDSS_ETR_DDR_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QDSS_ETR_DDR_CBCR_ADDR, m) +#define HWIO_GCC_QDSS_ETR_DDR_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QDSS_ETR_DDR_CBCR_ADDR,v) +#define HWIO_GCC_QDSS_ETR_DDR_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QDSS_ETR_DDR_CBCR_ADDR,m,v,HWIO_GCC_QDSS_ETR_DDR_CBCR_IN) +#define HWIO_GCC_QDSS_ETR_DDR_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QDSS_ETR_DDR_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QDSS_ETR_DDR_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QDSS_ETR_DDR_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QDSS_ETR_DDR_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QDSS_ETR_DDR_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QDSS_ETR_DDR_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QDSS_ETR_DDR_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QDSS_ETR_DDR_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_QDSS_ETR_DDR_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_QDSS_ETR_DDR_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_QDSS_ETR_DDR_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_QDSS_ETR_DDR_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QDSS_ETR_DDR_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QDSS_ETR_DDR_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QDSS_ETR_DDR_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_QDSS_ETR_DDR_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_QDSS_ETR_DDR_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_QDSS_ETR_DDR_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_ETR_DDR_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QDSS_ETR_DDR_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_QDSS_ETR_DDR_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_QDSS_ETR_DDR_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_ETR_DDR_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QDSS_STM_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f02c) +#define HWIO_GCC_QDSS_STM_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f02c) +#define HWIO_GCC_QDSS_STM_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f02c) +#define HWIO_GCC_QDSS_STM_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_QDSS_STM_CBCR_ATTR 0x3 +#define HWIO_GCC_QDSS_STM_CBCR_IN \ + in_dword_masked(HWIO_GCC_QDSS_STM_CBCR_ADDR, HWIO_GCC_QDSS_STM_CBCR_RMSK) +#define HWIO_GCC_QDSS_STM_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QDSS_STM_CBCR_ADDR, m) +#define HWIO_GCC_QDSS_STM_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QDSS_STM_CBCR_ADDR,v) +#define HWIO_GCC_QDSS_STM_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QDSS_STM_CBCR_ADDR,m,v,HWIO_GCC_QDSS_STM_CBCR_IN) +#define HWIO_GCC_QDSS_STM_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QDSS_STM_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QDSS_STM_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QDSS_STM_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QDSS_STM_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QDSS_STM_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QDSS_STM_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QDSS_STM_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QDSS_STM_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_QDSS_STM_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_QDSS_STM_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_QDSS_STM_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_QDSS_STM_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QDSS_STM_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QDSS_STM_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QDSS_STM_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_QDSS_STM_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_QDSS_STM_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_QDSS_STM_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_STM_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QDSS_STM_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_QDSS_STM_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_QDSS_STM_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_STM_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f030) +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f030) +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f030) +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_ATTR 0x3 +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_IN \ + in_dword_masked(HWIO_GCC_QDSS_TRACECLKIN_CBCR_ADDR, HWIO_GCC_QDSS_TRACECLKIN_CBCR_RMSK) +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QDSS_TRACECLKIN_CBCR_ADDR, m) +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QDSS_TRACECLKIN_CBCR_ADDR,v) +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QDSS_TRACECLKIN_CBCR_ADDR,m,v,HWIO_GCC_QDSS_TRACECLKIN_CBCR_IN) +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QDSS_TSCTR_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f034) +#define HWIO_GCC_QDSS_TSCTR_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f034) +#define HWIO_GCC_QDSS_TSCTR_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f034) +#define HWIO_GCC_QDSS_TSCTR_CBCR_RMSK 0x81c0000f +#define HWIO_GCC_QDSS_TSCTR_CBCR_ATTR 0x3 +#define HWIO_GCC_QDSS_TSCTR_CBCR_IN \ + in_dword_masked(HWIO_GCC_QDSS_TSCTR_CBCR_ADDR, HWIO_GCC_QDSS_TSCTR_CBCR_RMSK) +#define HWIO_GCC_QDSS_TSCTR_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QDSS_TSCTR_CBCR_ADDR, m) +#define HWIO_GCC_QDSS_TSCTR_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QDSS_TSCTR_CBCR_ADDR,v) +#define HWIO_GCC_QDSS_TSCTR_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QDSS_TSCTR_CBCR_ADDR,m,v,HWIO_GCC_QDSS_TSCTR_CBCR_IN) +#define HWIO_GCC_QDSS_TSCTR_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QDSS_TSCTR_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QDSS_TSCTR_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QDSS_TSCTR_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QDSS_TSCTR_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QDSS_TSCTR_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QDSS_TSCTR_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QDSS_TSCTR_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QDSS_TSCTR_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_QDSS_TSCTR_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_QDSS_TSCTR_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QDSS_TSCTR_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QDSS_TSCTR_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QDSS_TSCTR_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_QDSS_TSCTR_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_QDSS_TSCTR_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_QDSS_TSCTR_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_TSCTR_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QDSS_TSCTR_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_QDSS_TSCTR_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_QDSS_TSCTR_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_TSCTR_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QDSS_TRIG_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f038) +#define HWIO_GCC_QDSS_TRIG_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f038) +#define HWIO_GCC_QDSS_TRIG_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f038) +#define HWIO_GCC_QDSS_TRIG_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_QDSS_TRIG_CBCR_ATTR 0x3 +#define HWIO_GCC_QDSS_TRIG_CBCR_IN \ + in_dword_masked(HWIO_GCC_QDSS_TRIG_CBCR_ADDR, HWIO_GCC_QDSS_TRIG_CBCR_RMSK) +#define HWIO_GCC_QDSS_TRIG_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QDSS_TRIG_CBCR_ADDR, m) +#define HWIO_GCC_QDSS_TRIG_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QDSS_TRIG_CBCR_ADDR,v) +#define HWIO_GCC_QDSS_TRIG_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QDSS_TRIG_CBCR_ADDR,m,v,HWIO_GCC_QDSS_TRIG_CBCR_IN) +#define HWIO_GCC_QDSS_TRIG_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QDSS_TRIG_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QDSS_TRIG_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QDSS_TRIG_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QDSS_TRIG_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QDSS_TRIG_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QDSS_TRIG_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QDSS_TRIG_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QDSS_TRIG_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_QDSS_TRIG_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_QDSS_TRIG_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_QDSS_TRIG_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_QDSS_TRIG_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QDSS_TRIG_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QDSS_TRIG_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QDSS_TRIG_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_QDSS_TRIG_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_QDSS_TRIG_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_QDSS_TRIG_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_TRIG_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QDSS_TRIG_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_QDSS_TRIG_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_QDSS_TRIG_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_TRIG_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QDSS_DAP_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f03c) +#define HWIO_GCC_QDSS_DAP_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f03c) +#define HWIO_GCC_QDSS_DAP_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f03c) +#define HWIO_GCC_QDSS_DAP_CBCR_RMSK 0x81c0000f +#define HWIO_GCC_QDSS_DAP_CBCR_ATTR 0x3 +#define HWIO_GCC_QDSS_DAP_CBCR_IN \ + in_dword_masked(HWIO_GCC_QDSS_DAP_CBCR_ADDR, HWIO_GCC_QDSS_DAP_CBCR_RMSK) +#define HWIO_GCC_QDSS_DAP_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QDSS_DAP_CBCR_ADDR, m) +#define HWIO_GCC_QDSS_DAP_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QDSS_DAP_CBCR_ADDR,v) +#define HWIO_GCC_QDSS_DAP_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QDSS_DAP_CBCR_ADDR,m,v,HWIO_GCC_QDSS_DAP_CBCR_IN) +#define HWIO_GCC_QDSS_DAP_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QDSS_DAP_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QDSS_DAP_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QDSS_DAP_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QDSS_DAP_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QDSS_DAP_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QDSS_DAP_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QDSS_DAP_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QDSS_DAP_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_QDSS_DAP_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_QDSS_DAP_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QDSS_DAP_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QDSS_DAP_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QDSS_DAP_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_QDSS_DAP_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_QDSS_DAP_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_QDSS_DAP_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_DAP_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QDSS_DAP_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_QDSS_DAP_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_QDSS_DAP_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_DAP_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CENTER_APB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f040) +#define HWIO_GCC_CENTER_APB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f040) +#define HWIO_GCC_CENTER_APB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f040) +#define HWIO_GCC_CENTER_APB_CBCR_RMSK 0x81c0000f +#define HWIO_GCC_CENTER_APB_CBCR_ATTR 0x3 +#define HWIO_GCC_CENTER_APB_CBCR_IN \ + in_dword_masked(HWIO_GCC_CENTER_APB_CBCR_ADDR, HWIO_GCC_CENTER_APB_CBCR_RMSK) +#define HWIO_GCC_CENTER_APB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_CENTER_APB_CBCR_ADDR, m) +#define HWIO_GCC_CENTER_APB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_CENTER_APB_CBCR_ADDR,v) +#define HWIO_GCC_CENTER_APB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CENTER_APB_CBCR_ADDR,m,v,HWIO_GCC_CENTER_APB_CBCR_IN) +#define HWIO_GCC_CENTER_APB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_CENTER_APB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_CENTER_APB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_CENTER_APB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_CENTER_APB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_CENTER_APB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_CENTER_APB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_CENTER_APB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_CENTER_APB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_CENTER_APB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_CENTER_APB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_CENTER_APB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_CENTER_APB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_CENTER_APB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_CENTER_APB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_CENTER_APB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_CENTER_APB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_CENTER_APB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_CENTER_APB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_CENTER_APB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_CENTER_APB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CENTER_APB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_NORTH_APB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f044) +#define HWIO_GCC_NORTH_APB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f044) +#define HWIO_GCC_NORTH_APB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f044) +#define HWIO_GCC_NORTH_APB_CBCR_RMSK 0x81c0000f +#define HWIO_GCC_NORTH_APB_CBCR_ATTR 0x3 +#define HWIO_GCC_NORTH_APB_CBCR_IN \ + in_dword_masked(HWIO_GCC_NORTH_APB_CBCR_ADDR, HWIO_GCC_NORTH_APB_CBCR_RMSK) +#define HWIO_GCC_NORTH_APB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_NORTH_APB_CBCR_ADDR, m) +#define HWIO_GCC_NORTH_APB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_NORTH_APB_CBCR_ADDR,v) +#define HWIO_GCC_NORTH_APB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_NORTH_APB_CBCR_ADDR,m,v,HWIO_GCC_NORTH_APB_CBCR_IN) +#define HWIO_GCC_NORTH_APB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_NORTH_APB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_NORTH_APB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_NORTH_APB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_NORTH_APB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_NORTH_APB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_NORTH_APB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_NORTH_APB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_NORTH_APB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_NORTH_APB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_NORTH_APB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_NORTH_APB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_NORTH_APB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_NORTH_APB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_NORTH_APB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_NORTH_APB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_NORTH_APB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_NORTH_APB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_NORTH_APB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_NORTH_APB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_NORTH_APB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_NORTH_APB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SOUTH_APB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f048) +#define HWIO_GCC_SOUTH_APB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f048) +#define HWIO_GCC_SOUTH_APB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f048) +#define HWIO_GCC_SOUTH_APB_CBCR_RMSK 0x81c0000f +#define HWIO_GCC_SOUTH_APB_CBCR_ATTR 0x3 +#define HWIO_GCC_SOUTH_APB_CBCR_IN \ + in_dword_masked(HWIO_GCC_SOUTH_APB_CBCR_ADDR, HWIO_GCC_SOUTH_APB_CBCR_RMSK) +#define HWIO_GCC_SOUTH_APB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_SOUTH_APB_CBCR_ADDR, m) +#define HWIO_GCC_SOUTH_APB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_SOUTH_APB_CBCR_ADDR,v) +#define HWIO_GCC_SOUTH_APB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SOUTH_APB_CBCR_ADDR,m,v,HWIO_GCC_SOUTH_APB_CBCR_IN) +#define HWIO_GCC_SOUTH_APB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SOUTH_APB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SOUTH_APB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_SOUTH_APB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_SOUTH_APB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_SOUTH_APB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_SOUTH_APB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_SOUTH_APB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_SOUTH_APB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_SOUTH_APB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_SOUTH_APB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_SOUTH_APB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_SOUTH_APB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SOUTH_APB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_SOUTH_APB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_SOUTH_APB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_SOUTH_APB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_SOUTH_APB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_SOUTH_APB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SOUTH_APB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SOUTH_APB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SOUTH_APB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_WEST_APB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f04c) +#define HWIO_GCC_WEST_APB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f04c) +#define HWIO_GCC_WEST_APB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f04c) +#define HWIO_GCC_WEST_APB_CBCR_RMSK 0x81c0000f +#define HWIO_GCC_WEST_APB_CBCR_ATTR 0x3 +#define HWIO_GCC_WEST_APB_CBCR_IN \ + in_dword_masked(HWIO_GCC_WEST_APB_CBCR_ADDR, HWIO_GCC_WEST_APB_CBCR_RMSK) +#define HWIO_GCC_WEST_APB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_WEST_APB_CBCR_ADDR, m) +#define HWIO_GCC_WEST_APB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_WEST_APB_CBCR_ADDR,v) +#define HWIO_GCC_WEST_APB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_WEST_APB_CBCR_ADDR,m,v,HWIO_GCC_WEST_APB_CBCR_IN) +#define HWIO_GCC_WEST_APB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_WEST_APB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_WEST_APB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_WEST_APB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_WEST_APB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_WEST_APB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_WEST_APB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_WEST_APB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_WEST_APB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_WEST_APB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_WEST_APB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_WEST_APB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_WEST_APB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_WEST_APB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_WEST_APB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_WEST_APB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_WEST_APB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_WEST_APB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_WEST_APB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_WEST_APB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_WEST_APB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_WEST_APB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_EAST_APB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f050) +#define HWIO_GCC_EAST_APB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f050) +#define HWIO_GCC_EAST_APB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f050) +#define HWIO_GCC_EAST_APB_CBCR_RMSK 0x81c0000f +#define HWIO_GCC_EAST_APB_CBCR_ATTR 0x3 +#define HWIO_GCC_EAST_APB_CBCR_IN \ + in_dword_masked(HWIO_GCC_EAST_APB_CBCR_ADDR, HWIO_GCC_EAST_APB_CBCR_RMSK) +#define HWIO_GCC_EAST_APB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_EAST_APB_CBCR_ADDR, m) +#define HWIO_GCC_EAST_APB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_EAST_APB_CBCR_ADDR,v) +#define HWIO_GCC_EAST_APB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_EAST_APB_CBCR_ADDR,m,v,HWIO_GCC_EAST_APB_CBCR_IN) +#define HWIO_GCC_EAST_APB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_EAST_APB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_EAST_APB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_EAST_APB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_EAST_APB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_EAST_APB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_EAST_APB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_EAST_APB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_EAST_APB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_EAST_APB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_EAST_APB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_EAST_APB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_EAST_APB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_EAST_APB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_EAST_APB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_EAST_APB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_EAST_APB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_EAST_APB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_EAST_APB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_EAST_APB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_EAST_APB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_EAST_APB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MMNOC_APB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f054) +#define HWIO_GCC_MMNOC_APB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f054) +#define HWIO_GCC_MMNOC_APB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f054) +#define HWIO_GCC_MMNOC_APB_CBCR_RMSK 0x81c0000f +#define HWIO_GCC_MMNOC_APB_CBCR_ATTR 0x3 +#define HWIO_GCC_MMNOC_APB_CBCR_IN \ + in_dword_masked(HWIO_GCC_MMNOC_APB_CBCR_ADDR, HWIO_GCC_MMNOC_APB_CBCR_RMSK) +#define HWIO_GCC_MMNOC_APB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_MMNOC_APB_CBCR_ADDR, m) +#define HWIO_GCC_MMNOC_APB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_MMNOC_APB_CBCR_ADDR,v) +#define HWIO_GCC_MMNOC_APB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MMNOC_APB_CBCR_ADDR,m,v,HWIO_GCC_MMNOC_APB_CBCR_IN) +#define HWIO_GCC_MMNOC_APB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_MMNOC_APB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_MMNOC_APB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_MMNOC_APB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_MMNOC_APB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_MMNOC_APB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_MMNOC_APB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_MMNOC_APB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_MMNOC_APB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_MMNOC_APB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_MMNOC_APB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_MMNOC_APB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_MMNOC_APB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_MMNOC_APB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_MMNOC_APB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_MMNOC_APB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_MMNOC_APB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMNOC_APB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_MMNOC_APB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_MMNOC_APB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_MMNOC_APB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MMNOC_APB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QDSS_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f058) +#define HWIO_GCC_QDSS_XO_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f058) +#define HWIO_GCC_QDSS_XO_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f058) +#define HWIO_GCC_QDSS_XO_CBCR_RMSK 0x81c0000f +#define HWIO_GCC_QDSS_XO_CBCR_ATTR 0x3 +#define HWIO_GCC_QDSS_XO_CBCR_IN \ + in_dword_masked(HWIO_GCC_QDSS_XO_CBCR_ADDR, HWIO_GCC_QDSS_XO_CBCR_RMSK) +#define HWIO_GCC_QDSS_XO_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QDSS_XO_CBCR_ADDR, m) +#define HWIO_GCC_QDSS_XO_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QDSS_XO_CBCR_ADDR,v) +#define HWIO_GCC_QDSS_XO_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QDSS_XO_CBCR_ADDR,m,v,HWIO_GCC_QDSS_XO_CBCR_IN) +#define HWIO_GCC_QDSS_XO_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QDSS_XO_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QDSS_XO_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QDSS_XO_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QDSS_XO_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QDSS_XO_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QDSS_XO_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QDSS_XO_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QDSS_XO_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_QDSS_XO_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_QDSS_XO_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QDSS_XO_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QDSS_XO_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QDSS_XO_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_QDSS_XO_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_QDSS_XO_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_QDSS_XO_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_XO_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QDSS_XO_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_QDSS_XO_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_QDSS_XO_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_XO_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QDSS_USB_PRIM_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00029090) +#define HWIO_GCC_QDSS_USB_PRIM_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00029090) +#define HWIO_GCC_QDSS_USB_PRIM_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00029090) +#define HWIO_GCC_QDSS_USB_PRIM_CBCR_RMSK 0x81c0000f +#define HWIO_GCC_QDSS_USB_PRIM_CBCR_ATTR 0x3 +#define HWIO_GCC_QDSS_USB_PRIM_CBCR_IN \ + in_dword_masked(HWIO_GCC_QDSS_USB_PRIM_CBCR_ADDR, HWIO_GCC_QDSS_USB_PRIM_CBCR_RMSK) +#define HWIO_GCC_QDSS_USB_PRIM_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QDSS_USB_PRIM_CBCR_ADDR, m) +#define HWIO_GCC_QDSS_USB_PRIM_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QDSS_USB_PRIM_CBCR_ADDR,v) +#define HWIO_GCC_QDSS_USB_PRIM_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QDSS_USB_PRIM_CBCR_ADDR,m,v,HWIO_GCC_QDSS_USB_PRIM_CBCR_IN) +#define HWIO_GCC_QDSS_USB_PRIM_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QDSS_USB_PRIM_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QDSS_USB_PRIM_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QDSS_USB_PRIM_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QDSS_USB_PRIM_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QDSS_USB_PRIM_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QDSS_USB_PRIM_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QDSS_USB_PRIM_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QDSS_USB_PRIM_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_QDSS_USB_PRIM_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_QDSS_USB_PRIM_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QDSS_USB_PRIM_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QDSS_USB_PRIM_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QDSS_USB_PRIM_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_QDSS_USB_PRIM_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_QDSS_USB_PRIM_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_QDSS_USB_PRIM_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_USB_PRIM_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QDSS_USB_PRIM_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_QDSS_USB_PRIM_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_QDSS_USB_PRIM_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_USB_PRIM_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f078) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f078) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f078) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f07c) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f07c) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f07c) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f080) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f080) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f080) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f084) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f084) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f084) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f088) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f088) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f088) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f08c) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f08c) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f08c) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f090) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f090) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f090) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f094) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f094) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f094) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f098) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f098) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f098) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f09c) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f09c) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f09c) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f0a0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f0a0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f0a0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f0a4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f0a4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f0a4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f0a8) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f0a8) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f0a8) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f0ac) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f0ac) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f0ac) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f0b0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f0b0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f0b0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f0b4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f0b4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f0b4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QDSS_ATB_A_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f05c) +#define HWIO_GCC_QDSS_ATB_A_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f05c) +#define HWIO_GCC_QDSS_ATB_A_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f05c) +#define HWIO_GCC_QDSS_ATB_A_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_QDSS_ATB_A_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_QDSS_ATB_A_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_QDSS_ATB_A_CMD_RCGR_ADDR, HWIO_GCC_QDSS_ATB_A_CMD_RCGR_RMSK) +#define HWIO_GCC_QDSS_ATB_A_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QDSS_ATB_A_CMD_RCGR_ADDR, m) +#define HWIO_GCC_QDSS_ATB_A_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QDSS_ATB_A_CMD_RCGR_ADDR,v) +#define HWIO_GCC_QDSS_ATB_A_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QDSS_ATB_A_CMD_RCGR_ADDR,m,v,HWIO_GCC_QDSS_ATB_A_CMD_RCGR_IN) +#define HWIO_GCC_QDSS_ATB_A_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_QDSS_ATB_A_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_QDSS_ATB_A_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_QDSS_ATB_A_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_QDSS_ATB_A_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_QDSS_ATB_A_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_QDSS_ATB_A_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_ATB_A_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_QDSS_ATB_A_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_QDSS_ATB_A_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_QDSS_ATB_A_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_ATB_A_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f060) +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f060) +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f060) +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_QDSS_ATB_A_CFG_RCGR_ADDR, HWIO_GCC_QDSS_ATB_A_CFG_RCGR_RMSK) +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QDSS_ATB_A_CFG_RCGR_ADDR, m) +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QDSS_ATB_A_CFG_RCGR_ADDR,v) +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QDSS_ATB_A_CFG_RCGR_ADDR,m,v,HWIO_GCC_QDSS_ATB_A_CFG_RCGR_IN) +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f1a4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f1a4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f1a4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f1a8) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f1a8) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f1a8) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f1ac) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f1ac) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f1ac) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f1b0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f1b0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f1b0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f1b4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f1b4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f1b4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f1b8) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f1b8) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f1b8) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f1bc) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f1bc) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f1bc) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f1c0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f1c0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f1c0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f1c4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f1c4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f1c4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f1c8) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f1c8) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f1c8) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f1cc) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f1cc) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f1cc) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f1d0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f1d0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f1d0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f1d4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f1d4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f1d4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f1d8) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f1d8) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f1d8) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f1dc) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f1dc) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f1dc) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f1e0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f1e0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f1e0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QDSS_ATB_B_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f188) +#define HWIO_GCC_QDSS_ATB_B_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f188) +#define HWIO_GCC_QDSS_ATB_B_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f188) +#define HWIO_GCC_QDSS_ATB_B_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_QDSS_ATB_B_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_QDSS_ATB_B_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_QDSS_ATB_B_CMD_RCGR_ADDR, HWIO_GCC_QDSS_ATB_B_CMD_RCGR_RMSK) +#define HWIO_GCC_QDSS_ATB_B_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QDSS_ATB_B_CMD_RCGR_ADDR, m) +#define HWIO_GCC_QDSS_ATB_B_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QDSS_ATB_B_CMD_RCGR_ADDR,v) +#define HWIO_GCC_QDSS_ATB_B_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QDSS_ATB_B_CMD_RCGR_ADDR,m,v,HWIO_GCC_QDSS_ATB_B_CMD_RCGR_IN) +#define HWIO_GCC_QDSS_ATB_B_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_QDSS_ATB_B_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_QDSS_ATB_B_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_QDSS_ATB_B_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_QDSS_ATB_B_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_QDSS_ATB_B_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_QDSS_ATB_B_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_ATB_B_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_QDSS_ATB_B_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_QDSS_ATB_B_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_QDSS_ATB_B_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_ATB_B_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f18c) +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f18c) +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f18c) +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_QDSS_ATB_B_CFG_RCGR_ADDR, HWIO_GCC_QDSS_ATB_B_CFG_RCGR_RMSK) +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QDSS_ATB_B_CFG_RCGR_ADDR, m) +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QDSS_ATB_B_CFG_RCGR_ADDR,v) +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QDSS_ATB_B_CFG_RCGR_ADDR,m,v,HWIO_GCC_QDSS_ATB_B_CFG_RCGR_IN) +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f2d0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f2d0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f2d0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f2d4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f2d4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f2d4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f2d8) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f2d8) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f2d8) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f2dc) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f2dc) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f2dc) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f2e0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f2e0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f2e0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f2e4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f2e4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f2e4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f2e8) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f2e8) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f2e8) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f2ec) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f2ec) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f2ec) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f2f0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f2f0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f2f0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f2f4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f2f4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f2f4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f2f8) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f2f8) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f2f8) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f2fc) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f2fc) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f2fc) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f300) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f300) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f300) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f304) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f304) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f304) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f308) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f308) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f308) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f30c) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f30c) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f30c) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QDSS_ATB_C_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f2b4) +#define HWIO_GCC_QDSS_ATB_C_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f2b4) +#define HWIO_GCC_QDSS_ATB_C_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f2b4) +#define HWIO_GCC_QDSS_ATB_C_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_QDSS_ATB_C_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_QDSS_ATB_C_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_QDSS_ATB_C_CMD_RCGR_ADDR, HWIO_GCC_QDSS_ATB_C_CMD_RCGR_RMSK) +#define HWIO_GCC_QDSS_ATB_C_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QDSS_ATB_C_CMD_RCGR_ADDR, m) +#define HWIO_GCC_QDSS_ATB_C_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QDSS_ATB_C_CMD_RCGR_ADDR,v) +#define HWIO_GCC_QDSS_ATB_C_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QDSS_ATB_C_CMD_RCGR_ADDR,m,v,HWIO_GCC_QDSS_ATB_C_CMD_RCGR_IN) +#define HWIO_GCC_QDSS_ATB_C_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_QDSS_ATB_C_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_QDSS_ATB_C_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_QDSS_ATB_C_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_QDSS_ATB_C_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_QDSS_ATB_C_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_QDSS_ATB_C_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_ATB_C_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_QDSS_ATB_C_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_QDSS_ATB_C_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_QDSS_ATB_C_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_ATB_C_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f2b8) +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f2b8) +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f2b8) +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_QDSS_ATB_C_CFG_RCGR_ADDR, HWIO_GCC_QDSS_ATB_C_CFG_RCGR_RMSK) +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QDSS_ATB_C_CFG_RCGR_ADDR, m) +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QDSS_ATB_C_CFG_RCGR_ADDR,v) +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QDSS_ATB_C_CFG_RCGR_ADDR,m,v,HWIO_GCC_QDSS_ATB_C_CFG_RCGR_IN) +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f3fc) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f3fc) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f3fc) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f400) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f400) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f400) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f404) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f404) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f404) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f408) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f408) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f408) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f40c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f40c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f40c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f410) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f410) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f410) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f414) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f414) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f414) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f418) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f418) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f418) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f41c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f41c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f41c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f420) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f420) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f420) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f424) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f424) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f424) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f428) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f428) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f428) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f42c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f42c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f42c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f430) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f430) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f430) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f434) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f434) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f434) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f438) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f438) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f438) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QDSS_STM_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f3e0) +#define HWIO_GCC_QDSS_STM_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f3e0) +#define HWIO_GCC_QDSS_STM_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f3e0) +#define HWIO_GCC_QDSS_STM_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_QDSS_STM_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_QDSS_STM_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_QDSS_STM_CMD_RCGR_ADDR, HWIO_GCC_QDSS_STM_CMD_RCGR_RMSK) +#define HWIO_GCC_QDSS_STM_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QDSS_STM_CMD_RCGR_ADDR, m) +#define HWIO_GCC_QDSS_STM_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QDSS_STM_CMD_RCGR_ADDR,v) +#define HWIO_GCC_QDSS_STM_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QDSS_STM_CMD_RCGR_ADDR,m,v,HWIO_GCC_QDSS_STM_CMD_RCGR_IN) +#define HWIO_GCC_QDSS_STM_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_QDSS_STM_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_QDSS_STM_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_QDSS_STM_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_QDSS_STM_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_QDSS_STM_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_QDSS_STM_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_STM_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_QDSS_STM_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_QDSS_STM_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_QDSS_STM_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_STM_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QDSS_STM_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f3e4) +#define HWIO_GCC_QDSS_STM_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f3e4) +#define HWIO_GCC_QDSS_STM_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f3e4) +#define HWIO_GCC_QDSS_STM_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_QDSS_STM_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_QDSS_STM_CFG_RCGR_ADDR, HWIO_GCC_QDSS_STM_CFG_RCGR_RMSK) +#define HWIO_GCC_QDSS_STM_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QDSS_STM_CFG_RCGR_ADDR, m) +#define HWIO_GCC_QDSS_STM_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QDSS_STM_CFG_RCGR_ADDR,v) +#define HWIO_GCC_QDSS_STM_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QDSS_STM_CFG_RCGR_ADDR,m,v,HWIO_GCC_QDSS_STM_CFG_RCGR_IN) +#define HWIO_GCC_QDSS_STM_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f528) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f528) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f528) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f52c) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f52c) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f52c) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f530) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f530) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f530) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f534) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f534) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f534) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f538) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f538) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f538) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f53c) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f53c) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f53c) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f540) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f540) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f540) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f544) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f544) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f544) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f548) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f548) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f548) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f54c) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f54c) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f54c) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f550) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f550) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f550) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f554) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f554) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f554) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f558) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f558) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f558) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f55c) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f55c) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f55c) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f560) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f560) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f560) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f564) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f564) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f564) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f50c) +#define HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f50c) +#define HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f50c) +#define HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_ADDR, HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_RMSK) +#define HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_ADDR, m) +#define HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_ADDR,v) +#define HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_ADDR,m,v,HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_IN) +#define HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f510) +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f510) +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f510) +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_ADDR, HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_RMSK) +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_ADDR, m) +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_ADDR,v) +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_ADDR,m,v,HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_IN) +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f638) +#define HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f638) +#define HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f638) +#define HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_ADDR, HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_RMSK) +#define HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_ADDR, m) +#define HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_ADDR,v) +#define HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_ADDR,m,v,HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_IN) +#define HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f63c) +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f63c) +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f63c) +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_ADDR, HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_RMSK) +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_ADDR, m) +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_ADDR,v) +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_ADDR,m,v,HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_IN) +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f66c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f66c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f66c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f670) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f670) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f670) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f674) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f674) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f674) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f678) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f678) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f678) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f67c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f67c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f67c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f680) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f680) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f680) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f684) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f684) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f684) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f688) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f688) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f688) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f68c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f68c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f68c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f690) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f690) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f690) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f694) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f694) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f694) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f698) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f698) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f698) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f69c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f69c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f69c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f6a0) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f6a0) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f6a0) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f6a4) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f6a4) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f6a4) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f6a8) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f6a8) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f6a8) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_ADDR, HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_IN) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QDSS_TRIG_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f650) +#define HWIO_GCC_QDSS_TRIG_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f650) +#define HWIO_GCC_QDSS_TRIG_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f650) +#define HWIO_GCC_QDSS_TRIG_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_QDSS_TRIG_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_QDSS_TRIG_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_QDSS_TRIG_CMD_RCGR_ADDR, HWIO_GCC_QDSS_TRIG_CMD_RCGR_RMSK) +#define HWIO_GCC_QDSS_TRIG_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QDSS_TRIG_CMD_RCGR_ADDR, m) +#define HWIO_GCC_QDSS_TRIG_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QDSS_TRIG_CMD_RCGR_ADDR,v) +#define HWIO_GCC_QDSS_TRIG_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QDSS_TRIG_CMD_RCGR_ADDR,m,v,HWIO_GCC_QDSS_TRIG_CMD_RCGR_IN) +#define HWIO_GCC_QDSS_TRIG_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_QDSS_TRIG_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_QDSS_TRIG_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_QDSS_TRIG_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_QDSS_TRIG_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_QDSS_TRIG_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_QDSS_TRIG_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_TRIG_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_QDSS_TRIG_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_QDSS_TRIG_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_QDSS_TRIG_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_TRIG_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000f654) +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f654) +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f654) +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_QDSS_TRIG_CFG_RCGR_ADDR, HWIO_GCC_QDSS_TRIG_CFG_RCGR_RMSK) +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QDSS_TRIG_CFG_RCGR_ADDR, m) +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QDSS_TRIG_CFG_RCGR_ADDR,v) +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QDSS_TRIG_CFG_RCGR_ADDR,m,v,HWIO_GCC_QDSS_TRIG_CFG_RCGR_IN) +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_USB30_PRIM_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00029000) +#define HWIO_GCC_USB30_PRIM_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00029000) +#define HWIO_GCC_USB30_PRIM_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00029000) +#define HWIO_GCC_USB30_PRIM_BCR_RMSK 0x1 +#define HWIO_GCC_USB30_PRIM_BCR_ATTR 0x3 +#define HWIO_GCC_USB30_PRIM_BCR_IN \ + in_dword_masked(HWIO_GCC_USB30_PRIM_BCR_ADDR, HWIO_GCC_USB30_PRIM_BCR_RMSK) +#define HWIO_GCC_USB30_PRIM_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_USB30_PRIM_BCR_ADDR, m) +#define HWIO_GCC_USB30_PRIM_BCR_OUT(v) \ + out_dword(HWIO_GCC_USB30_PRIM_BCR_ADDR,v) +#define HWIO_GCC_USB30_PRIM_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB30_PRIM_BCR_ADDR,m,v,HWIO_GCC_USB30_PRIM_BCR_IN) +#define HWIO_GCC_USB30_PRIM_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_USB30_PRIM_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_USB30_PRIM_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_PRIM_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_USB30_PRIM_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00029004) +#define HWIO_GCC_USB30_PRIM_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00029004) +#define HWIO_GCC_USB30_PRIM_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00029004) +#define HWIO_GCC_USB30_PRIM_GDSCR_RMSK 0xf8ffffff +#define HWIO_GCC_USB30_PRIM_GDSCR_ATTR 0x3 +#define HWIO_GCC_USB30_PRIM_GDSCR_IN \ + in_dword_masked(HWIO_GCC_USB30_PRIM_GDSCR_ADDR, HWIO_GCC_USB30_PRIM_GDSCR_RMSK) +#define HWIO_GCC_USB30_PRIM_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_USB30_PRIM_GDSCR_ADDR, m) +#define HWIO_GCC_USB30_PRIM_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_USB30_PRIM_GDSCR_ADDR,v) +#define HWIO_GCC_USB30_PRIM_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB30_PRIM_GDSCR_ADDR,m,v,HWIO_GCC_USB30_PRIM_GDSCR_IN) +#define HWIO_GCC_USB30_PRIM_GDSCR_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_USB30_PRIM_GDSCR_PWR_ON_SHFT 0x1f +#define HWIO_GCC_USB30_PRIM_GDSCR_GDSC_STATE_BMSK 0x78000000 +#define HWIO_GCC_USB30_PRIM_GDSCR_GDSC_STATE_SHFT 0x1b +#define HWIO_GCC_USB30_PRIM_GDSCR_EN_REST_WAIT_BMSK 0xf00000 +#define HWIO_GCC_USB30_PRIM_GDSCR_EN_REST_WAIT_SHFT 0x14 +#define HWIO_GCC_USB30_PRIM_GDSCR_EN_FEW_WAIT_BMSK 0xf0000 +#define HWIO_GCC_USB30_PRIM_GDSCR_EN_FEW_WAIT_SHFT 0x10 +#define HWIO_GCC_USB30_PRIM_GDSCR_CLK_DIS_WAIT_BMSK 0xf000 +#define HWIO_GCC_USB30_PRIM_GDSCR_CLK_DIS_WAIT_SHFT 0xc +#define HWIO_GCC_USB30_PRIM_GDSCR_RETAIN_FF_ENABLE_BMSK 0x800 +#define HWIO_GCC_USB30_PRIM_GDSCR_RETAIN_FF_ENABLE_SHFT 0xb +#define HWIO_GCC_USB30_PRIM_GDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_PRIM_GDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB30_PRIM_GDSCR_RESTORE_BMSK 0x400 +#define HWIO_GCC_USB30_PRIM_GDSCR_RESTORE_SHFT 0xa +#define HWIO_GCC_USB30_PRIM_GDSCR_RESTORE_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_PRIM_GDSCR_RESTORE_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB30_PRIM_GDSCR_SAVE_BMSK 0x200 +#define HWIO_GCC_USB30_PRIM_GDSCR_SAVE_SHFT 0x9 +#define HWIO_GCC_USB30_PRIM_GDSCR_SAVE_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_PRIM_GDSCR_SAVE_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB30_PRIM_GDSCR_RETAIN_BMSK 0x100 +#define HWIO_GCC_USB30_PRIM_GDSCR_RETAIN_SHFT 0x8 +#define HWIO_GCC_USB30_PRIM_GDSCR_RETAIN_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_PRIM_GDSCR_RETAIN_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB30_PRIM_GDSCR_EN_REST_BMSK 0x80 +#define HWIO_GCC_USB30_PRIM_GDSCR_EN_REST_SHFT 0x7 +#define HWIO_GCC_USB30_PRIM_GDSCR_EN_REST_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_PRIM_GDSCR_EN_REST_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB30_PRIM_GDSCR_EN_FEW_BMSK 0x40 +#define HWIO_GCC_USB30_PRIM_GDSCR_EN_FEW_SHFT 0x6 +#define HWIO_GCC_USB30_PRIM_GDSCR_EN_FEW_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_PRIM_GDSCR_EN_FEW_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB30_PRIM_GDSCR_CLAMP_IO_BMSK 0x20 +#define HWIO_GCC_USB30_PRIM_GDSCR_CLAMP_IO_SHFT 0x5 +#define HWIO_GCC_USB30_PRIM_GDSCR_CLAMP_IO_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_PRIM_GDSCR_CLAMP_IO_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB30_PRIM_GDSCR_CLK_DISABLE_BMSK 0x10 +#define HWIO_GCC_USB30_PRIM_GDSCR_CLK_DISABLE_SHFT 0x4 +#define HWIO_GCC_USB30_PRIM_GDSCR_CLK_DISABLE_CLK_NOT_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_PRIM_GDSCR_CLK_DISABLE_CLK_IS_DISABLE_FVAL 0x1 +#define HWIO_GCC_USB30_PRIM_GDSCR_PD_ARES_BMSK 0x8 +#define HWIO_GCC_USB30_PRIM_GDSCR_PD_ARES_SHFT 0x3 +#define HWIO_GCC_USB30_PRIM_GDSCR_PD_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_USB30_PRIM_GDSCR_PD_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_USB30_PRIM_GDSCR_SW_OVERRIDE_BMSK 0x4 +#define HWIO_GCC_USB30_PRIM_GDSCR_SW_OVERRIDE_SHFT 0x2 +#define HWIO_GCC_USB30_PRIM_GDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_PRIM_GDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB30_PRIM_GDSCR_HW_CONTROL_BMSK 0x2 +#define HWIO_GCC_USB30_PRIM_GDSCR_HW_CONTROL_SHFT 0x1 +#define HWIO_GCC_USB30_PRIM_GDSCR_HW_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_PRIM_GDSCR_HW_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB30_PRIM_GDSCR_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_USB30_PRIM_GDSCR_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_USB30_PRIM_GDSCR_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_PRIM_GDSCR_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00029008) +#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00029008) +#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00029008) +#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_RMSK 0x7ffffff +#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_ATTR 0x3 +#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_IN \ + in_dword_masked(HWIO_GCC_USB30_PRIM_CFG_GDSCR_ADDR, HWIO_GCC_USB30_PRIM_CFG_GDSCR_RMSK) +#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_USB30_PRIM_CFG_GDSCR_ADDR, m) +#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_USB30_PRIM_CFG_GDSCR_ADDR,v) +#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB30_PRIM_CFG_GDSCR_ADDR,m,v,HWIO_GCC_USB30_PRIM_CFG_GDSCR_IN) +#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4000000 +#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x1a +#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_GDSC_PWR_DWN_START_BMSK 0x2000000 +#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_GDSC_PWR_DWN_START_SHFT 0x19 +#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_GDSC_PWR_UP_START_BMSK 0x1000000 +#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_GDSC_PWR_UP_START_SHFT 0x18 +#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_BMSK 0xf00000 +#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_SHFT 0x14 +#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_BMSK 0x80000 +#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_SHFT 0x13 +#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_GDSC_ENR_ACK_STATUS_BMSK 0x40000 +#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_GDSC_ENR_ACK_STATUS_SHFT 0x12 +#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_GDSC_ENF_ACK_STATUS_BMSK 0x20000 +#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_GDSC_ENF_ACK_STATUS_SHFT 0x11 +#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_BMSK 0x10000 +#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_SHFT 0x10 +#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_BMSK 0x8000 +#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_SHFT 0xf +#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_BMSK 0x7800 +#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_SHFT 0xb +#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_GDSC_HANDSHAKE_DIS_BMSK 0x400 +#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_GDSC_HANDSHAKE_DIS_SHFT 0xa +#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_BMSK 0x200 +#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_SHFT 0x9 +#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_BMSK 0x100 +#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_SHFT 0x8 +#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_BMSK 0x80 +#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_SHFT 0x7 +#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_BMSK 0x60 +#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_SHFT 0x5 +#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_BMSK 0x10 +#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_SHFT 0x4 +#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_BMSK 0x8 +#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_SHFT 0x3 +#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_BMSK 0x4 +#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_SHFT 0x2 +#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_BMSK 0x2 +#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_SHFT 0x1 +#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_SHFT 0x0 + +#define HWIO_GCC_USB30_PRIM_CFG2_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002900c) +#define HWIO_GCC_USB30_PRIM_CFG2_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002900c) +#define HWIO_GCC_USB30_PRIM_CFG2_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002900c) +#define HWIO_GCC_USB30_PRIM_CFG2_GDSCR_RMSK 0x7ffff +#define HWIO_GCC_USB30_PRIM_CFG2_GDSCR_ATTR 0x3 +#define HWIO_GCC_USB30_PRIM_CFG2_GDSCR_IN \ + in_dword_masked(HWIO_GCC_USB30_PRIM_CFG2_GDSCR_ADDR, HWIO_GCC_USB30_PRIM_CFG2_GDSCR_RMSK) +#define HWIO_GCC_USB30_PRIM_CFG2_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_USB30_PRIM_CFG2_GDSCR_ADDR, m) +#define HWIO_GCC_USB30_PRIM_CFG2_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_USB30_PRIM_CFG2_GDSCR_ADDR,v) +#define HWIO_GCC_USB30_PRIM_CFG2_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB30_PRIM_CFG2_GDSCR_ADDR,m,v,HWIO_GCC_USB30_PRIM_CFG2_GDSCR_IN) +#define HWIO_GCC_USB30_PRIM_CFG2_GDSCR_GDSC_MEM_PWRUP_ACK_OVERRIDE_BMSK 0x40000 +#define HWIO_GCC_USB30_PRIM_CFG2_GDSCR_GDSC_MEM_PWRUP_ACK_OVERRIDE_SHFT 0x12 +#define HWIO_GCC_USB30_PRIM_CFG2_GDSCR_GDSC_PWRDWN_ENABLE_ACK_OVERRIDE_BMSK 0x20000 +#define HWIO_GCC_USB30_PRIM_CFG2_GDSCR_GDSC_PWRDWN_ENABLE_ACK_OVERRIDE_SHFT 0x11 +#define HWIO_GCC_USB30_PRIM_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_BMSK 0x10000 +#define HWIO_GCC_USB30_PRIM_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_SHFT 0x10 +#define HWIO_GCC_USB30_PRIM_CFG2_GDSCR_DLY_MEM_PWR_UP_BMSK 0xf000 +#define HWIO_GCC_USB30_PRIM_CFG2_GDSCR_DLY_MEM_PWR_UP_SHFT 0xc +#define HWIO_GCC_USB30_PRIM_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_BMSK 0xf00 +#define HWIO_GCC_USB30_PRIM_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_SHFT 0x8 +#define HWIO_GCC_USB30_PRIM_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_BMSK 0xf0 +#define HWIO_GCC_USB30_PRIM_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_SHFT 0x4 +#define HWIO_GCC_USB30_PRIM_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_BMSK 0xf +#define HWIO_GCC_USB30_PRIM_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_SHFT 0x0 + +#define HWIO_GCC_USB30_PRIM_CFG3_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00029010) +#define HWIO_GCC_USB30_PRIM_CFG3_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00029010) +#define HWIO_GCC_USB30_PRIM_CFG3_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00029010) +#define HWIO_GCC_USB30_PRIM_CFG3_GDSCR_RMSK 0x7ffffff +#define HWIO_GCC_USB30_PRIM_CFG3_GDSCR_ATTR 0x3 +#define HWIO_GCC_USB30_PRIM_CFG3_GDSCR_IN \ + in_dword_masked(HWIO_GCC_USB30_PRIM_CFG3_GDSCR_ADDR, HWIO_GCC_USB30_PRIM_CFG3_GDSCR_RMSK) +#define HWIO_GCC_USB30_PRIM_CFG3_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_USB30_PRIM_CFG3_GDSCR_ADDR, m) +#define HWIO_GCC_USB30_PRIM_CFG3_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_USB30_PRIM_CFG3_GDSCR_ADDR,v) +#define HWIO_GCC_USB30_PRIM_CFG3_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB30_PRIM_CFG3_GDSCR_ADDR,m,v,HWIO_GCC_USB30_PRIM_CFG3_GDSCR_IN) +#define HWIO_GCC_USB30_PRIM_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_STATUS_BMSK 0x4000000 +#define HWIO_GCC_USB30_PRIM_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_STATUS_SHFT 0x1a +#define HWIO_GCC_USB30_PRIM_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_BMSK 0x2000000 +#define HWIO_GCC_USB30_PRIM_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_SHFT 0x19 +#define HWIO_GCC_USB30_PRIM_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_PRIM_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB30_PRIM_CFG3_GDSCR_DLY_ACCU_RED_SHIFTER_DONE_BMSK 0x1e00000 +#define HWIO_GCC_USB30_PRIM_CFG3_GDSCR_DLY_ACCU_RED_SHIFTER_DONE_SHFT 0x15 +#define HWIO_GCC_USB30_PRIM_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_BMSK 0x100000 +#define HWIO_GCC_USB30_PRIM_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_SHFT 0x14 +#define HWIO_GCC_USB30_PRIM_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_PRIM_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB30_PRIM_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_BMSK 0x80000 +#define HWIO_GCC_USB30_PRIM_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_SHFT 0x13 +#define HWIO_GCC_USB30_PRIM_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_PRIM_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB30_PRIM_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_BMSK 0x40000 +#define HWIO_GCC_USB30_PRIM_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_SHFT 0x12 +#define HWIO_GCC_USB30_PRIM_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_PRIM_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB30_PRIM_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_BMSK 0x20000 +#define HWIO_GCC_USB30_PRIM_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_SHFT 0x11 +#define HWIO_GCC_USB30_PRIM_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_PRIM_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB30_PRIM_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_BMSK 0x10000 +#define HWIO_GCC_USB30_PRIM_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_SHFT 0x10 +#define HWIO_GCC_USB30_PRIM_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_PRIM_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB30_PRIM_CFG3_GDSCR_GDSC_SPARE_CTRL_IN_BMSK 0xff00 +#define HWIO_GCC_USB30_PRIM_CFG3_GDSCR_GDSC_SPARE_CTRL_IN_SHFT 0x8 +#define HWIO_GCC_USB30_PRIM_CFG3_GDSCR_GDSC_SPARE_CTRL_OUT_BMSK 0xff +#define HWIO_GCC_USB30_PRIM_CFG3_GDSCR_GDSC_SPARE_CTRL_OUT_SHFT 0x0 + +#define HWIO_GCC_USB30_PRIM_CFG4_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00029014) +#define HWIO_GCC_USB30_PRIM_CFG4_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00029014) +#define HWIO_GCC_USB30_PRIM_CFG4_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00029014) +#define HWIO_GCC_USB30_PRIM_CFG4_GDSCR_RMSK 0xffffff +#define HWIO_GCC_USB30_PRIM_CFG4_GDSCR_ATTR 0x3 +#define HWIO_GCC_USB30_PRIM_CFG4_GDSCR_IN \ + in_dword_masked(HWIO_GCC_USB30_PRIM_CFG4_GDSCR_ADDR, HWIO_GCC_USB30_PRIM_CFG4_GDSCR_RMSK) +#define HWIO_GCC_USB30_PRIM_CFG4_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_USB30_PRIM_CFG4_GDSCR_ADDR, m) +#define HWIO_GCC_USB30_PRIM_CFG4_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_USB30_PRIM_CFG4_GDSCR_ADDR,v) +#define HWIO_GCC_USB30_PRIM_CFG4_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB30_PRIM_CFG4_GDSCR_ADDR,m,v,HWIO_GCC_USB30_PRIM_CFG4_GDSCR_IN) +#define HWIO_GCC_USB30_PRIM_CFG4_GDSCR_DLY_UNCLAMPIO_BMSK 0xf00000 +#define HWIO_GCC_USB30_PRIM_CFG4_GDSCR_DLY_UNCLAMPIO_SHFT 0x14 +#define HWIO_GCC_USB30_PRIM_CFG4_GDSCR_DLY_RESTOREFF_BMSK 0xf0000 +#define HWIO_GCC_USB30_PRIM_CFG4_GDSCR_DLY_RESTOREFF_SHFT 0x10 +#define HWIO_GCC_USB30_PRIM_CFG4_GDSCR_DLY_NORETAINFF_BMSK 0xf000 +#define HWIO_GCC_USB30_PRIM_CFG4_GDSCR_DLY_NORETAINFF_SHFT 0xc +#define HWIO_GCC_USB30_PRIM_CFG4_GDSCR_DLY_DEASSERTARES_BMSK 0xf00 +#define HWIO_GCC_USB30_PRIM_CFG4_GDSCR_DLY_DEASSERTARES_SHFT 0x8 +#define HWIO_GCC_USB30_PRIM_CFG4_GDSCR_DLY_CLAMPIO_BMSK 0xf0 +#define HWIO_GCC_USB30_PRIM_CFG4_GDSCR_DLY_CLAMPIO_SHFT 0x4 +#define HWIO_GCC_USB30_PRIM_CFG4_GDSCR_DLY_RETAINFF_BMSK 0xf +#define HWIO_GCC_USB30_PRIM_CFG4_GDSCR_DLY_RETAINFF_SHFT 0x0 + +#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00029018) +#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00029018) +#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00029018) +#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_RMSK 0x81c07005 +#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_ATTR 0x3 +#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_IN \ + in_dword_masked(HWIO_GCC_USB30_PRIM_MASTER_CBCR_ADDR, HWIO_GCC_USB30_PRIM_MASTER_CBCR_RMSK) +#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_USB30_PRIM_MASTER_CBCR_ADDR, m) +#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_OUT(v) \ + out_dword(HWIO_GCC_USB30_PRIM_MASTER_CBCR_ADDR,v) +#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB30_PRIM_MASTER_CBCR_ADDR,m,v,HWIO_GCC_USB30_PRIM_MASTER_CBCR_IN) +#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002901c) +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002901c) +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002901c) +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_RMSK 0xf1ffffe +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_ATTR 0x3 +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_IN \ + in_dword_masked(HWIO_GCC_USB30_PRIM_MASTER_SREGR_ADDR, HWIO_GCC_USB30_PRIM_MASTER_SREGR_RMSK) +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_USB30_PRIM_MASTER_SREGR_ADDR, m) +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_OUT(v) \ + out_dword(HWIO_GCC_USB30_PRIM_MASTER_SREGR_ADDR,v) +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB30_PRIM_MASTER_SREGR_ADDR,m,v,HWIO_GCC_USB30_PRIM_MASTER_SREGR_IN) +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xf000000 +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_PWR_FSM_CLK_SEL_BMSK 0x100000 +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_PWR_FSM_CLK_SEL_SHFT 0x14 +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xf0000 +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00029020) +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00029020) +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00029020) +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_SREGR_RMSK 0xffffffff +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_SREGR_ATTR 0x3 +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_SREGR_IN \ + in_dword_masked(HWIO_GCC_USB30_PRIM_MASTER_CFG_SREGR_ADDR, HWIO_GCC_USB30_PRIM_MASTER_CFG_SREGR_RMSK) +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_USB30_PRIM_MASTER_CFG_SREGR_ADDR, m) +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_SREGR_OUT(v) \ + out_dword(HWIO_GCC_USB30_PRIM_MASTER_CFG_SREGR_ADDR,v) +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB30_PRIM_MASTER_CFG_SREGR_ADDR,m,v,HWIO_GCC_USB30_PRIM_MASTER_CFG_SREGR_IN) +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_SREGR_MEM_CORE_OFF_TIMER_BMSK 0xfc000000 +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_SREGR_MEM_CORE_OFF_TIMER_SHFT 0x1a +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_BMSK 0x2000000 +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_SHFT 0x19 +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_BMSK 0x1000000 +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_SHFT 0x18 +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_SREGR_MEM_PERIPH_ON_STATUS_BMSK 0x800000 +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_SREGR_MEM_PERIPH_ON_STATUS_SHFT 0x17 +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_SREGR_MEM_CORE_ON_STATUS_BMSK 0x400000 +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_SREGR_MEM_CORE_ON_STATUS_SHFT 0x16 +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_SREGR_MEM_CPH_TIMER_BMSK 0x3f0000 +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_SREGR_MEM_CPH_TIMER_SHFT 0x10 +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_SREGR_SLEEP_TIMER_BMSK 0xff00 +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_SREGR_SLEEP_TIMER_SHFT 0x8 +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_SREGR_WAKEUP_TIMER_BMSK 0xff +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_SREGR_WAKEUP_TIMER_SHFT 0x0 + +#define HWIO_GCC_USB30_PRIM_SLEEP_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00029024) +#define HWIO_GCC_USB30_PRIM_SLEEP_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00029024) +#define HWIO_GCC_USB30_PRIM_SLEEP_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00029024) +#define HWIO_GCC_USB30_PRIM_SLEEP_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_USB30_PRIM_SLEEP_CBCR_ATTR 0x3 +#define HWIO_GCC_USB30_PRIM_SLEEP_CBCR_IN \ + in_dword_masked(HWIO_GCC_USB30_PRIM_SLEEP_CBCR_ADDR, HWIO_GCC_USB30_PRIM_SLEEP_CBCR_RMSK) +#define HWIO_GCC_USB30_PRIM_SLEEP_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_USB30_PRIM_SLEEP_CBCR_ADDR, m) +#define HWIO_GCC_USB30_PRIM_SLEEP_CBCR_OUT(v) \ + out_dword(HWIO_GCC_USB30_PRIM_SLEEP_CBCR_ADDR,v) +#define HWIO_GCC_USB30_PRIM_SLEEP_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB30_PRIM_SLEEP_CBCR_ADDR,m,v,HWIO_GCC_USB30_PRIM_SLEEP_CBCR_IN) +#define HWIO_GCC_USB30_PRIM_SLEEP_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_USB30_PRIM_SLEEP_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_USB30_PRIM_SLEEP_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_USB30_PRIM_SLEEP_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_USB30_PRIM_SLEEP_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_USB30_PRIM_SLEEP_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_USB30_PRIM_SLEEP_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_USB30_PRIM_SLEEP_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_USB30_PRIM_SLEEP_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_USB30_PRIM_SLEEP_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_USB30_PRIM_SLEEP_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_USB30_PRIM_SLEEP_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_USB30_PRIM_SLEEP_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_USB30_PRIM_SLEEP_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_USB30_PRIM_SLEEP_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_PRIM_SLEEP_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00029028) +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00029028) +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00029028) +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CBCR_ATTR 0x3 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CBCR_IN \ + in_dword_masked(HWIO_GCC_USB30_PRIM_MOCK_UTMI_CBCR_ADDR, HWIO_GCC_USB30_PRIM_MOCK_UTMI_CBCR_RMSK) +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_USB30_PRIM_MOCK_UTMI_CBCR_ADDR, m) +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CBCR_OUT(v) \ + out_dword(HWIO_GCC_USB30_PRIM_MOCK_UTMI_CBCR_ADDR,v) +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB30_PRIM_MOCK_UTMI_CBCR_ADDR,m,v,HWIO_GCC_USB30_PRIM_MOCK_UTMI_CBCR_IN) +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002902c) +#define HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002902c) +#define HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002902c) +#define HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_RMSK 0x800000f3 +#define HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_ADDR, HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_RMSK) +#define HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_ADDR, m) +#define HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_ADDR,v) +#define HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_ADDR,m,v,HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_IN) +#define HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_DIRTY_D_BMSK 0x80 +#define HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_DIRTY_D_SHFT 0x7 +#define HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_DIRTY_N_BMSK 0x40 +#define HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_DIRTY_N_SHFT 0x6 +#define HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_DIRTY_M_BMSK 0x20 +#define HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_DIRTY_M_SHFT 0x5 +#define HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00029030) +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00029030) +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00029030) +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_RMSK 0x10371f +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_ADDR, HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_RMSK) +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_ADDR, m) +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_ADDR,v) +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_ADDR,m,v,HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_IN) +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_MODE_BMSK 0x3000 +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_MODE_SHFT 0xc +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_USB30_PRIM_MASTER_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00029034) +#define HWIO_GCC_USB30_PRIM_MASTER_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00029034) +#define HWIO_GCC_USB30_PRIM_MASTER_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00029034) +#define HWIO_GCC_USB30_PRIM_MASTER_M_RMSK 0xff +#define HWIO_GCC_USB30_PRIM_MASTER_M_ATTR 0x3 +#define HWIO_GCC_USB30_PRIM_MASTER_M_IN \ + in_dword_masked(HWIO_GCC_USB30_PRIM_MASTER_M_ADDR, HWIO_GCC_USB30_PRIM_MASTER_M_RMSK) +#define HWIO_GCC_USB30_PRIM_MASTER_M_INM(m) \ + in_dword_masked(HWIO_GCC_USB30_PRIM_MASTER_M_ADDR, m) +#define HWIO_GCC_USB30_PRIM_MASTER_M_OUT(v) \ + out_dword(HWIO_GCC_USB30_PRIM_MASTER_M_ADDR,v) +#define HWIO_GCC_USB30_PRIM_MASTER_M_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB30_PRIM_MASTER_M_ADDR,m,v,HWIO_GCC_USB30_PRIM_MASTER_M_IN) +#define HWIO_GCC_USB30_PRIM_MASTER_M_M_BMSK 0xff +#define HWIO_GCC_USB30_PRIM_MASTER_M_M_SHFT 0x0 + +#define HWIO_GCC_USB30_PRIM_MASTER_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00029038) +#define HWIO_GCC_USB30_PRIM_MASTER_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00029038) +#define HWIO_GCC_USB30_PRIM_MASTER_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00029038) +#define HWIO_GCC_USB30_PRIM_MASTER_N_RMSK 0xff +#define HWIO_GCC_USB30_PRIM_MASTER_N_ATTR 0x3 +#define HWIO_GCC_USB30_PRIM_MASTER_N_IN \ + in_dword_masked(HWIO_GCC_USB30_PRIM_MASTER_N_ADDR, HWIO_GCC_USB30_PRIM_MASTER_N_RMSK) +#define HWIO_GCC_USB30_PRIM_MASTER_N_INM(m) \ + in_dword_masked(HWIO_GCC_USB30_PRIM_MASTER_N_ADDR, m) +#define HWIO_GCC_USB30_PRIM_MASTER_N_OUT(v) \ + out_dword(HWIO_GCC_USB30_PRIM_MASTER_N_ADDR,v) +#define HWIO_GCC_USB30_PRIM_MASTER_N_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB30_PRIM_MASTER_N_ADDR,m,v,HWIO_GCC_USB30_PRIM_MASTER_N_IN) +#define HWIO_GCC_USB30_PRIM_MASTER_N_NOT_N_MINUS_M_BMSK 0xff +#define HWIO_GCC_USB30_PRIM_MASTER_N_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_USB30_PRIM_MASTER_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002903c) +#define HWIO_GCC_USB30_PRIM_MASTER_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002903c) +#define HWIO_GCC_USB30_PRIM_MASTER_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002903c) +#define HWIO_GCC_USB30_PRIM_MASTER_D_RMSK 0xff +#define HWIO_GCC_USB30_PRIM_MASTER_D_ATTR 0x3 +#define HWIO_GCC_USB30_PRIM_MASTER_D_IN \ + in_dword_masked(HWIO_GCC_USB30_PRIM_MASTER_D_ADDR, HWIO_GCC_USB30_PRIM_MASTER_D_RMSK) +#define HWIO_GCC_USB30_PRIM_MASTER_D_INM(m) \ + in_dword_masked(HWIO_GCC_USB30_PRIM_MASTER_D_ADDR, m) +#define HWIO_GCC_USB30_PRIM_MASTER_D_OUT(v) \ + out_dword(HWIO_GCC_USB30_PRIM_MASTER_D_ADDR,v) +#define HWIO_GCC_USB30_PRIM_MASTER_D_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB30_PRIM_MASTER_D_ADDR,m,v,HWIO_GCC_USB30_PRIM_MASTER_D_IN) +#define HWIO_GCC_USB30_PRIM_MASTER_D_NOT_2D_BMSK 0xff +#define HWIO_GCC_USB30_PRIM_MASTER_D_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00029044) +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00029044) +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00029044) +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR_ADDR, HWIO_GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR_RMSK) +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR_ADDR, m) +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR_ADDR,v) +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR_ADDR,m,v,HWIO_GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR_IN) +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00029048) +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00029048) +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00029048) +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_ADDR, HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_RMSK) +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_ADDR, m) +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_ADDR,v) +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_ADDR,m,v,HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_IN) +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002905c) +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002905c) +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002905c) +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CDIVR_RMSK 0xf +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CDIVR_ATTR 0x3 +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CDIVR_IN \ + in_dword_masked(HWIO_GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CDIVR_ADDR, HWIO_GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CDIVR_RMSK) +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CDIVR_INM(m) \ + in_dword_masked(HWIO_GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CDIVR_ADDR, m) +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CDIVR_OUT(v) \ + out_dword(HWIO_GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CDIVR_ADDR,v) +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CDIVR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CDIVR_ADDR,m,v,HWIO_GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CDIVR_IN) +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CDIVR_CLK_DIV_BMSK 0xf +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CDIVR_CLK_DIV_SHFT 0x0 + +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00029060) +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00029060) +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00029060) +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CBCR_ATTR 0x3 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CBCR_IN \ + in_dword_masked(HWIO_GCC_USB3_PRIM_PHY_AUX_CBCR_ADDR, HWIO_GCC_USB3_PRIM_PHY_AUX_CBCR_RMSK) +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_USB3_PRIM_PHY_AUX_CBCR_ADDR, m) +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CBCR_OUT(v) \ + out_dword(HWIO_GCC_USB3_PRIM_PHY_AUX_CBCR_ADDR,v) +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB3_PRIM_PHY_AUX_CBCR_ADDR,m,v,HWIO_GCC_USB3_PRIM_PHY_AUX_CBCR_IN) +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_USB3_PRIM_PHY_COM_AUX_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00029064) +#define HWIO_GCC_USB3_PRIM_PHY_COM_AUX_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00029064) +#define HWIO_GCC_USB3_PRIM_PHY_COM_AUX_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00029064) +#define HWIO_GCC_USB3_PRIM_PHY_COM_AUX_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_USB3_PRIM_PHY_COM_AUX_CBCR_ATTR 0x3 +#define HWIO_GCC_USB3_PRIM_PHY_COM_AUX_CBCR_IN \ + in_dword_masked(HWIO_GCC_USB3_PRIM_PHY_COM_AUX_CBCR_ADDR, HWIO_GCC_USB3_PRIM_PHY_COM_AUX_CBCR_RMSK) +#define HWIO_GCC_USB3_PRIM_PHY_COM_AUX_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_USB3_PRIM_PHY_COM_AUX_CBCR_ADDR, m) +#define HWIO_GCC_USB3_PRIM_PHY_COM_AUX_CBCR_OUT(v) \ + out_dword(HWIO_GCC_USB3_PRIM_PHY_COM_AUX_CBCR_ADDR,v) +#define HWIO_GCC_USB3_PRIM_PHY_COM_AUX_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB3_PRIM_PHY_COM_AUX_CBCR_ADDR,m,v,HWIO_GCC_USB3_PRIM_PHY_COM_AUX_CBCR_IN) +#define HWIO_GCC_USB3_PRIM_PHY_COM_AUX_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_USB3_PRIM_PHY_COM_AUX_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_USB3_PRIM_PHY_COM_AUX_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_USB3_PRIM_PHY_COM_AUX_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_USB3_PRIM_PHY_COM_AUX_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_USB3_PRIM_PHY_COM_AUX_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_USB3_PRIM_PHY_COM_AUX_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_USB3_PRIM_PHY_COM_AUX_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_USB3_PRIM_PHY_COM_AUX_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_USB3_PRIM_PHY_COM_AUX_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_USB3_PRIM_PHY_COM_AUX_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_USB3_PRIM_PHY_COM_AUX_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_USB3_PRIM_PHY_COM_AUX_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_USB3_PRIM_PHY_COM_AUX_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_USB3_PRIM_PHY_COM_AUX_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB3_PRIM_PHY_COM_AUX_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_USB3_PRIM_PHY_PIPE_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00029068) +#define HWIO_GCC_USB3_PRIM_PHY_PIPE_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00029068) +#define HWIO_GCC_USB3_PRIM_PHY_PIPE_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00029068) +#define HWIO_GCC_USB3_PRIM_PHY_PIPE_CBCR_RMSK 0x81c0000f +#define HWIO_GCC_USB3_PRIM_PHY_PIPE_CBCR_ATTR 0x3 +#define HWIO_GCC_USB3_PRIM_PHY_PIPE_CBCR_IN \ + in_dword_masked(HWIO_GCC_USB3_PRIM_PHY_PIPE_CBCR_ADDR, HWIO_GCC_USB3_PRIM_PHY_PIPE_CBCR_RMSK) +#define HWIO_GCC_USB3_PRIM_PHY_PIPE_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_USB3_PRIM_PHY_PIPE_CBCR_ADDR, m) +#define HWIO_GCC_USB3_PRIM_PHY_PIPE_CBCR_OUT(v) \ + out_dword(HWIO_GCC_USB3_PRIM_PHY_PIPE_CBCR_ADDR,v) +#define HWIO_GCC_USB3_PRIM_PHY_PIPE_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB3_PRIM_PHY_PIPE_CBCR_ADDR,m,v,HWIO_GCC_USB3_PRIM_PHY_PIPE_CBCR_IN) +#define HWIO_GCC_USB3_PRIM_PHY_PIPE_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_USB3_PRIM_PHY_PIPE_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_USB3_PRIM_PHY_PIPE_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_USB3_PRIM_PHY_PIPE_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_USB3_PRIM_PHY_PIPE_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_USB3_PRIM_PHY_PIPE_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_USB3_PRIM_PHY_PIPE_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_USB3_PRIM_PHY_PIPE_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_USB3_PRIM_PHY_PIPE_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_USB3_PRIM_PHY_PIPE_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_USB3_PRIM_PHY_PIPE_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_USB3_PRIM_PHY_PIPE_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_USB3_PRIM_PHY_PIPE_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_USB3_PRIM_PHY_PIPE_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_USB3_PRIM_PHY_PIPE_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_USB3_PRIM_PHY_PIPE_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_USB3_PRIM_PHY_PIPE_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB3_PRIM_PHY_PIPE_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB3_PRIM_PHY_PIPE_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_USB3_PRIM_PHY_PIPE_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_USB3_PRIM_PHY_PIPE_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB3_PRIM_PHY_PIPE_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00029070) +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00029070) +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00029070) +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_USB3_PRIM_PHY_AUX_CMD_RCGR_ADDR, HWIO_GCC_USB3_PRIM_PHY_AUX_CMD_RCGR_RMSK) +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_USB3_PRIM_PHY_AUX_CMD_RCGR_ADDR, m) +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_USB3_PRIM_PHY_AUX_CMD_RCGR_ADDR,v) +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB3_PRIM_PHY_AUX_CMD_RCGR_ADDR,m,v,HWIO_GCC_USB3_PRIM_PHY_AUX_CMD_RCGR_IN) +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00029074) +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00029074) +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00029074) +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_ADDR, HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_RMSK) +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_ADDR, m) +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_ADDR,v) +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_ADDR,m,v,HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_IN) +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_USB3_PHY_PRIM_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00040000) +#define HWIO_GCC_USB3_PHY_PRIM_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00040000) +#define HWIO_GCC_USB3_PHY_PRIM_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00040000) +#define HWIO_GCC_USB3_PHY_PRIM_BCR_RMSK 0x1 +#define HWIO_GCC_USB3_PHY_PRIM_BCR_ATTR 0x3 +#define HWIO_GCC_USB3_PHY_PRIM_BCR_IN \ + in_dword_masked(HWIO_GCC_USB3_PHY_PRIM_BCR_ADDR, HWIO_GCC_USB3_PHY_PRIM_BCR_RMSK) +#define HWIO_GCC_USB3_PHY_PRIM_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_USB3_PHY_PRIM_BCR_ADDR, m) +#define HWIO_GCC_USB3_PHY_PRIM_BCR_OUT(v) \ + out_dword(HWIO_GCC_USB3_PHY_PRIM_BCR_ADDR,v) +#define HWIO_GCC_USB3_PHY_PRIM_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB3_PHY_PRIM_BCR_ADDR,m,v,HWIO_GCC_USB3_PHY_PRIM_BCR_IN) +#define HWIO_GCC_USB3_PHY_PRIM_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_USB3_PHY_PRIM_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_USB3_PHY_PRIM_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB3_PHY_PRIM_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_USB3PHY_PHY_PRIM_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00040004) +#define HWIO_GCC_USB3PHY_PHY_PRIM_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00040004) +#define HWIO_GCC_USB3PHY_PHY_PRIM_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00040004) +#define HWIO_GCC_USB3PHY_PHY_PRIM_BCR_RMSK 0x1 +#define HWIO_GCC_USB3PHY_PHY_PRIM_BCR_ATTR 0x3 +#define HWIO_GCC_USB3PHY_PHY_PRIM_BCR_IN \ + in_dword_masked(HWIO_GCC_USB3PHY_PHY_PRIM_BCR_ADDR, HWIO_GCC_USB3PHY_PHY_PRIM_BCR_RMSK) +#define HWIO_GCC_USB3PHY_PHY_PRIM_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_USB3PHY_PHY_PRIM_BCR_ADDR, m) +#define HWIO_GCC_USB3PHY_PHY_PRIM_BCR_OUT(v) \ + out_dword(HWIO_GCC_USB3PHY_PHY_PRIM_BCR_ADDR,v) +#define HWIO_GCC_USB3PHY_PHY_PRIM_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB3PHY_PHY_PRIM_BCR_ADDR,m,v,HWIO_GCC_USB3PHY_PHY_PRIM_BCR_IN) +#define HWIO_GCC_USB3PHY_PHY_PRIM_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_USB3PHY_PHY_PRIM_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_USB3PHY_PHY_PRIM_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB3PHY_PHY_PRIM_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_USB3_DP_PHY_PRIM_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00040008) +#define HWIO_GCC_USB3_DP_PHY_PRIM_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00040008) +#define HWIO_GCC_USB3_DP_PHY_PRIM_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00040008) +#define HWIO_GCC_USB3_DP_PHY_PRIM_BCR_RMSK 0x1 +#define HWIO_GCC_USB3_DP_PHY_PRIM_BCR_ATTR 0x3 +#define HWIO_GCC_USB3_DP_PHY_PRIM_BCR_IN \ + in_dword_masked(HWIO_GCC_USB3_DP_PHY_PRIM_BCR_ADDR, HWIO_GCC_USB3_DP_PHY_PRIM_BCR_RMSK) +#define HWIO_GCC_USB3_DP_PHY_PRIM_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_USB3_DP_PHY_PRIM_BCR_ADDR, m) +#define HWIO_GCC_USB3_DP_PHY_PRIM_BCR_OUT(v) \ + out_dword(HWIO_GCC_USB3_DP_PHY_PRIM_BCR_ADDR,v) +#define HWIO_GCC_USB3_DP_PHY_PRIM_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB3_DP_PHY_PRIM_BCR_ADDR,m,v,HWIO_GCC_USB3_DP_PHY_PRIM_BCR_IN) +#define HWIO_GCC_USB3_DP_PHY_PRIM_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_USB3_DP_PHY_PRIM_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_USB3_DP_PHY_PRIM_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB3_DP_PHY_PRIM_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_USB3_PHY_SEC_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004000c) +#define HWIO_GCC_USB3_PHY_SEC_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004000c) +#define HWIO_GCC_USB3_PHY_SEC_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004000c) +#define HWIO_GCC_USB3_PHY_SEC_BCR_RMSK 0x1 +#define HWIO_GCC_USB3_PHY_SEC_BCR_ATTR 0x3 +#define HWIO_GCC_USB3_PHY_SEC_BCR_IN \ + in_dword_masked(HWIO_GCC_USB3_PHY_SEC_BCR_ADDR, HWIO_GCC_USB3_PHY_SEC_BCR_RMSK) +#define HWIO_GCC_USB3_PHY_SEC_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_USB3_PHY_SEC_BCR_ADDR, m) +#define HWIO_GCC_USB3_PHY_SEC_BCR_OUT(v) \ + out_dword(HWIO_GCC_USB3_PHY_SEC_BCR_ADDR,v) +#define HWIO_GCC_USB3_PHY_SEC_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB3_PHY_SEC_BCR_ADDR,m,v,HWIO_GCC_USB3_PHY_SEC_BCR_IN) +#define HWIO_GCC_USB3_PHY_SEC_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_USB3_PHY_SEC_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_USB3_PHY_SEC_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB3_PHY_SEC_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_USB3PHY_PHY_SEC_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00040010) +#define HWIO_GCC_USB3PHY_PHY_SEC_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00040010) +#define HWIO_GCC_USB3PHY_PHY_SEC_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00040010) +#define HWIO_GCC_USB3PHY_PHY_SEC_BCR_RMSK 0x1 +#define HWIO_GCC_USB3PHY_PHY_SEC_BCR_ATTR 0x3 +#define HWIO_GCC_USB3PHY_PHY_SEC_BCR_IN \ + in_dword_masked(HWIO_GCC_USB3PHY_PHY_SEC_BCR_ADDR, HWIO_GCC_USB3PHY_PHY_SEC_BCR_RMSK) +#define HWIO_GCC_USB3PHY_PHY_SEC_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_USB3PHY_PHY_SEC_BCR_ADDR, m) +#define HWIO_GCC_USB3PHY_PHY_SEC_BCR_OUT(v) \ + out_dword(HWIO_GCC_USB3PHY_PHY_SEC_BCR_ADDR,v) +#define HWIO_GCC_USB3PHY_PHY_SEC_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB3PHY_PHY_SEC_BCR_ADDR,m,v,HWIO_GCC_USB3PHY_PHY_SEC_BCR_IN) +#define HWIO_GCC_USB3PHY_PHY_SEC_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_USB3PHY_PHY_SEC_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_USB3PHY_PHY_SEC_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB3PHY_PHY_SEC_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_USB3_DP_PHY_SEC_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00040014) +#define HWIO_GCC_USB3_DP_PHY_SEC_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00040014) +#define HWIO_GCC_USB3_DP_PHY_SEC_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00040014) +#define HWIO_GCC_USB3_DP_PHY_SEC_BCR_RMSK 0x1 +#define HWIO_GCC_USB3_DP_PHY_SEC_BCR_ATTR 0x3 +#define HWIO_GCC_USB3_DP_PHY_SEC_BCR_IN \ + in_dword_masked(HWIO_GCC_USB3_DP_PHY_SEC_BCR_ADDR, HWIO_GCC_USB3_DP_PHY_SEC_BCR_RMSK) +#define HWIO_GCC_USB3_DP_PHY_SEC_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_USB3_DP_PHY_SEC_BCR_ADDR, m) +#define HWIO_GCC_USB3_DP_PHY_SEC_BCR_OUT(v) \ + out_dword(HWIO_GCC_USB3_DP_PHY_SEC_BCR_ADDR,v) +#define HWIO_GCC_USB3_DP_PHY_SEC_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB3_DP_PHY_SEC_BCR_ADDR,m,v,HWIO_GCC_USB3_DP_PHY_SEC_BCR_IN) +#define HWIO_GCC_USB3_DP_PHY_SEC_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_USB3_DP_PHY_SEC_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_USB3_DP_PHY_SEC_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB3_DP_PHY_SEC_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_USB3_PHY_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00040018) +#define HWIO_GCC_USB3_PHY_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00040018) +#define HWIO_GCC_USB3_PHY_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00040018) +#define HWIO_GCC_USB3_PHY_GDSCR_RMSK 0xf8ffffff +#define HWIO_GCC_USB3_PHY_GDSCR_ATTR 0x3 +#define HWIO_GCC_USB3_PHY_GDSCR_IN \ + in_dword_masked(HWIO_GCC_USB3_PHY_GDSCR_ADDR, HWIO_GCC_USB3_PHY_GDSCR_RMSK) +#define HWIO_GCC_USB3_PHY_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_USB3_PHY_GDSCR_ADDR, m) +#define HWIO_GCC_USB3_PHY_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_USB3_PHY_GDSCR_ADDR,v) +#define HWIO_GCC_USB3_PHY_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB3_PHY_GDSCR_ADDR,m,v,HWIO_GCC_USB3_PHY_GDSCR_IN) +#define HWIO_GCC_USB3_PHY_GDSCR_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_USB3_PHY_GDSCR_PWR_ON_SHFT 0x1f +#define HWIO_GCC_USB3_PHY_GDSCR_GDSC_STATE_BMSK 0x78000000 +#define HWIO_GCC_USB3_PHY_GDSCR_GDSC_STATE_SHFT 0x1b +#define HWIO_GCC_USB3_PHY_GDSCR_EN_REST_WAIT_BMSK 0xf00000 +#define HWIO_GCC_USB3_PHY_GDSCR_EN_REST_WAIT_SHFT 0x14 +#define HWIO_GCC_USB3_PHY_GDSCR_EN_FEW_WAIT_BMSK 0xf0000 +#define HWIO_GCC_USB3_PHY_GDSCR_EN_FEW_WAIT_SHFT 0x10 +#define HWIO_GCC_USB3_PHY_GDSCR_CLK_DIS_WAIT_BMSK 0xf000 +#define HWIO_GCC_USB3_PHY_GDSCR_CLK_DIS_WAIT_SHFT 0xc +#define HWIO_GCC_USB3_PHY_GDSCR_RETAIN_FF_ENABLE_BMSK 0x800 +#define HWIO_GCC_USB3_PHY_GDSCR_RETAIN_FF_ENABLE_SHFT 0xb +#define HWIO_GCC_USB3_PHY_GDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB3_PHY_GDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB3_PHY_GDSCR_RESTORE_BMSK 0x400 +#define HWIO_GCC_USB3_PHY_GDSCR_RESTORE_SHFT 0xa +#define HWIO_GCC_USB3_PHY_GDSCR_RESTORE_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB3_PHY_GDSCR_RESTORE_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB3_PHY_GDSCR_SAVE_BMSK 0x200 +#define HWIO_GCC_USB3_PHY_GDSCR_SAVE_SHFT 0x9 +#define HWIO_GCC_USB3_PHY_GDSCR_SAVE_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB3_PHY_GDSCR_SAVE_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB3_PHY_GDSCR_RETAIN_BMSK 0x100 +#define HWIO_GCC_USB3_PHY_GDSCR_RETAIN_SHFT 0x8 +#define HWIO_GCC_USB3_PHY_GDSCR_RETAIN_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB3_PHY_GDSCR_RETAIN_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB3_PHY_GDSCR_EN_REST_BMSK 0x80 +#define HWIO_GCC_USB3_PHY_GDSCR_EN_REST_SHFT 0x7 +#define HWIO_GCC_USB3_PHY_GDSCR_EN_REST_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB3_PHY_GDSCR_EN_REST_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB3_PHY_GDSCR_EN_FEW_BMSK 0x40 +#define HWIO_GCC_USB3_PHY_GDSCR_EN_FEW_SHFT 0x6 +#define HWIO_GCC_USB3_PHY_GDSCR_EN_FEW_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB3_PHY_GDSCR_EN_FEW_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB3_PHY_GDSCR_CLAMP_IO_BMSK 0x20 +#define HWIO_GCC_USB3_PHY_GDSCR_CLAMP_IO_SHFT 0x5 +#define HWIO_GCC_USB3_PHY_GDSCR_CLAMP_IO_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB3_PHY_GDSCR_CLAMP_IO_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB3_PHY_GDSCR_CLK_DISABLE_BMSK 0x10 +#define HWIO_GCC_USB3_PHY_GDSCR_CLK_DISABLE_SHFT 0x4 +#define HWIO_GCC_USB3_PHY_GDSCR_CLK_DISABLE_CLK_NOT_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB3_PHY_GDSCR_CLK_DISABLE_CLK_IS_DISABLE_FVAL 0x1 +#define HWIO_GCC_USB3_PHY_GDSCR_PD_ARES_BMSK 0x8 +#define HWIO_GCC_USB3_PHY_GDSCR_PD_ARES_SHFT 0x3 +#define HWIO_GCC_USB3_PHY_GDSCR_PD_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_USB3_PHY_GDSCR_PD_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_USB3_PHY_GDSCR_SW_OVERRIDE_BMSK 0x4 +#define HWIO_GCC_USB3_PHY_GDSCR_SW_OVERRIDE_SHFT 0x2 +#define HWIO_GCC_USB3_PHY_GDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB3_PHY_GDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB3_PHY_GDSCR_HW_CONTROL_BMSK 0x2 +#define HWIO_GCC_USB3_PHY_GDSCR_HW_CONTROL_SHFT 0x1 +#define HWIO_GCC_USB3_PHY_GDSCR_HW_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB3_PHY_GDSCR_HW_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB3_PHY_GDSCR_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_USB3_PHY_GDSCR_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_USB3_PHY_GDSCR_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB3_PHY_GDSCR_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_USB3_PHY_CFG_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004001c) +#define HWIO_GCC_USB3_PHY_CFG_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004001c) +#define HWIO_GCC_USB3_PHY_CFG_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004001c) +#define HWIO_GCC_USB3_PHY_CFG_GDSCR_RMSK 0x7ffffff +#define HWIO_GCC_USB3_PHY_CFG_GDSCR_ATTR 0x3 +#define HWIO_GCC_USB3_PHY_CFG_GDSCR_IN \ + in_dword_masked(HWIO_GCC_USB3_PHY_CFG_GDSCR_ADDR, HWIO_GCC_USB3_PHY_CFG_GDSCR_RMSK) +#define HWIO_GCC_USB3_PHY_CFG_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_USB3_PHY_CFG_GDSCR_ADDR, m) +#define HWIO_GCC_USB3_PHY_CFG_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_USB3_PHY_CFG_GDSCR_ADDR,v) +#define HWIO_GCC_USB3_PHY_CFG_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB3_PHY_CFG_GDSCR_ADDR,m,v,HWIO_GCC_USB3_PHY_CFG_GDSCR_IN) +#define HWIO_GCC_USB3_PHY_CFG_GDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4000000 +#define HWIO_GCC_USB3_PHY_CFG_GDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x1a +#define HWIO_GCC_USB3_PHY_CFG_GDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB3_PHY_CFG_GDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB3_PHY_CFG_GDSCR_GDSC_PWR_DWN_START_BMSK 0x2000000 +#define HWIO_GCC_USB3_PHY_CFG_GDSCR_GDSC_PWR_DWN_START_SHFT 0x19 +#define HWIO_GCC_USB3_PHY_CFG_GDSCR_GDSC_PWR_UP_START_BMSK 0x1000000 +#define HWIO_GCC_USB3_PHY_CFG_GDSCR_GDSC_PWR_UP_START_SHFT 0x18 +#define HWIO_GCC_USB3_PHY_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_BMSK 0xf00000 +#define HWIO_GCC_USB3_PHY_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_SHFT 0x14 +#define HWIO_GCC_USB3_PHY_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_BMSK 0x80000 +#define HWIO_GCC_USB3_PHY_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_SHFT 0x13 +#define HWIO_GCC_USB3_PHY_CFG_GDSCR_GDSC_ENR_ACK_STATUS_BMSK 0x40000 +#define HWIO_GCC_USB3_PHY_CFG_GDSCR_GDSC_ENR_ACK_STATUS_SHFT 0x12 +#define HWIO_GCC_USB3_PHY_CFG_GDSCR_GDSC_ENF_ACK_STATUS_BMSK 0x20000 +#define HWIO_GCC_USB3_PHY_CFG_GDSCR_GDSC_ENF_ACK_STATUS_SHFT 0x11 +#define HWIO_GCC_USB3_PHY_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_BMSK 0x10000 +#define HWIO_GCC_USB3_PHY_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_SHFT 0x10 +#define HWIO_GCC_USB3_PHY_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_BMSK 0x8000 +#define HWIO_GCC_USB3_PHY_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_SHFT 0xf +#define HWIO_GCC_USB3_PHY_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_BMSK 0x7800 +#define HWIO_GCC_USB3_PHY_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_SHFT 0xb +#define HWIO_GCC_USB3_PHY_CFG_GDSCR_GDSC_HANDSHAKE_DIS_BMSK 0x400 +#define HWIO_GCC_USB3_PHY_CFG_GDSCR_GDSC_HANDSHAKE_DIS_SHFT 0xa +#define HWIO_GCC_USB3_PHY_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_BMSK 0x200 +#define HWIO_GCC_USB3_PHY_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_SHFT 0x9 +#define HWIO_GCC_USB3_PHY_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_BMSK 0x100 +#define HWIO_GCC_USB3_PHY_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_SHFT 0x8 +#define HWIO_GCC_USB3_PHY_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_BMSK 0x80 +#define HWIO_GCC_USB3_PHY_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_SHFT 0x7 +#define HWIO_GCC_USB3_PHY_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_BMSK 0x60 +#define HWIO_GCC_USB3_PHY_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_SHFT 0x5 +#define HWIO_GCC_USB3_PHY_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_BMSK 0x10 +#define HWIO_GCC_USB3_PHY_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_SHFT 0x4 +#define HWIO_GCC_USB3_PHY_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_BMSK 0x8 +#define HWIO_GCC_USB3_PHY_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_SHFT 0x3 +#define HWIO_GCC_USB3_PHY_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_BMSK 0x4 +#define HWIO_GCC_USB3_PHY_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_SHFT 0x2 +#define HWIO_GCC_USB3_PHY_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_BMSK 0x2 +#define HWIO_GCC_USB3_PHY_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_SHFT 0x1 +#define HWIO_GCC_USB3_PHY_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_USB3_PHY_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_SHFT 0x0 + +#define HWIO_GCC_USB3_PHY_CFG2_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00040020) +#define HWIO_GCC_USB3_PHY_CFG2_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00040020) +#define HWIO_GCC_USB3_PHY_CFG2_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00040020) +#define HWIO_GCC_USB3_PHY_CFG2_GDSCR_RMSK 0x7ffff +#define HWIO_GCC_USB3_PHY_CFG2_GDSCR_ATTR 0x3 +#define HWIO_GCC_USB3_PHY_CFG2_GDSCR_IN \ + in_dword_masked(HWIO_GCC_USB3_PHY_CFG2_GDSCR_ADDR, HWIO_GCC_USB3_PHY_CFG2_GDSCR_RMSK) +#define HWIO_GCC_USB3_PHY_CFG2_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_USB3_PHY_CFG2_GDSCR_ADDR, m) +#define HWIO_GCC_USB3_PHY_CFG2_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_USB3_PHY_CFG2_GDSCR_ADDR,v) +#define HWIO_GCC_USB3_PHY_CFG2_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB3_PHY_CFG2_GDSCR_ADDR,m,v,HWIO_GCC_USB3_PHY_CFG2_GDSCR_IN) +#define HWIO_GCC_USB3_PHY_CFG2_GDSCR_GDSC_MEM_PWRUP_ACK_OVERRIDE_BMSK 0x40000 +#define HWIO_GCC_USB3_PHY_CFG2_GDSCR_GDSC_MEM_PWRUP_ACK_OVERRIDE_SHFT 0x12 +#define HWIO_GCC_USB3_PHY_CFG2_GDSCR_GDSC_PWRDWN_ENABLE_ACK_OVERRIDE_BMSK 0x20000 +#define HWIO_GCC_USB3_PHY_CFG2_GDSCR_GDSC_PWRDWN_ENABLE_ACK_OVERRIDE_SHFT 0x11 +#define HWIO_GCC_USB3_PHY_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_BMSK 0x10000 +#define HWIO_GCC_USB3_PHY_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_SHFT 0x10 +#define HWIO_GCC_USB3_PHY_CFG2_GDSCR_DLY_MEM_PWR_UP_BMSK 0xf000 +#define HWIO_GCC_USB3_PHY_CFG2_GDSCR_DLY_MEM_PWR_UP_SHFT 0xc +#define HWIO_GCC_USB3_PHY_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_BMSK 0xf00 +#define HWIO_GCC_USB3_PHY_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_SHFT 0x8 +#define HWIO_GCC_USB3_PHY_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_BMSK 0xf0 +#define HWIO_GCC_USB3_PHY_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_SHFT 0x4 +#define HWIO_GCC_USB3_PHY_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_BMSK 0xf +#define HWIO_GCC_USB3_PHY_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_SHFT 0x0 + +#define HWIO_GCC_USB3_PHY_CFG3_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00040024) +#define HWIO_GCC_USB3_PHY_CFG3_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00040024) +#define HWIO_GCC_USB3_PHY_CFG3_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00040024) +#define HWIO_GCC_USB3_PHY_CFG3_GDSCR_RMSK 0x7ffffff +#define HWIO_GCC_USB3_PHY_CFG3_GDSCR_ATTR 0x3 +#define HWIO_GCC_USB3_PHY_CFG3_GDSCR_IN \ + in_dword_masked(HWIO_GCC_USB3_PHY_CFG3_GDSCR_ADDR, HWIO_GCC_USB3_PHY_CFG3_GDSCR_RMSK) +#define HWIO_GCC_USB3_PHY_CFG3_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_USB3_PHY_CFG3_GDSCR_ADDR, m) +#define HWIO_GCC_USB3_PHY_CFG3_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_USB3_PHY_CFG3_GDSCR_ADDR,v) +#define HWIO_GCC_USB3_PHY_CFG3_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB3_PHY_CFG3_GDSCR_ADDR,m,v,HWIO_GCC_USB3_PHY_CFG3_GDSCR_IN) +#define HWIO_GCC_USB3_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_STATUS_BMSK 0x4000000 +#define HWIO_GCC_USB3_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_STATUS_SHFT 0x1a +#define HWIO_GCC_USB3_PHY_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_BMSK 0x2000000 +#define HWIO_GCC_USB3_PHY_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_SHFT 0x19 +#define HWIO_GCC_USB3_PHY_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB3_PHY_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB3_PHY_CFG3_GDSCR_DLY_ACCU_RED_SHIFTER_DONE_BMSK 0x1e00000 +#define HWIO_GCC_USB3_PHY_CFG3_GDSCR_DLY_ACCU_RED_SHIFTER_DONE_SHFT 0x15 +#define HWIO_GCC_USB3_PHY_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_BMSK 0x100000 +#define HWIO_GCC_USB3_PHY_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_SHFT 0x14 +#define HWIO_GCC_USB3_PHY_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB3_PHY_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB3_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_BMSK 0x80000 +#define HWIO_GCC_USB3_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_SHFT 0x13 +#define HWIO_GCC_USB3_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB3_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB3_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_BMSK 0x40000 +#define HWIO_GCC_USB3_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_SHFT 0x12 +#define HWIO_GCC_USB3_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB3_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB3_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_BMSK 0x20000 +#define HWIO_GCC_USB3_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_SHFT 0x11 +#define HWIO_GCC_USB3_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB3_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB3_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_BMSK 0x10000 +#define HWIO_GCC_USB3_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_SHFT 0x10 +#define HWIO_GCC_USB3_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB3_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_ENABLE_FVAL 0x1 +#define HWIO_GCC_USB3_PHY_CFG3_GDSCR_GDSC_SPARE_CTRL_IN_BMSK 0xff00 +#define HWIO_GCC_USB3_PHY_CFG3_GDSCR_GDSC_SPARE_CTRL_IN_SHFT 0x8 +#define HWIO_GCC_USB3_PHY_CFG3_GDSCR_GDSC_SPARE_CTRL_OUT_BMSK 0xff +#define HWIO_GCC_USB3_PHY_CFG3_GDSCR_GDSC_SPARE_CTRL_OUT_SHFT 0x0 + +#define HWIO_GCC_USB3_PHY_CFG4_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00040028) +#define HWIO_GCC_USB3_PHY_CFG4_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00040028) +#define HWIO_GCC_USB3_PHY_CFG4_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00040028) +#define HWIO_GCC_USB3_PHY_CFG4_GDSCR_RMSK 0xffffff +#define HWIO_GCC_USB3_PHY_CFG4_GDSCR_ATTR 0x3 +#define HWIO_GCC_USB3_PHY_CFG4_GDSCR_IN \ + in_dword_masked(HWIO_GCC_USB3_PHY_CFG4_GDSCR_ADDR, HWIO_GCC_USB3_PHY_CFG4_GDSCR_RMSK) +#define HWIO_GCC_USB3_PHY_CFG4_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_USB3_PHY_CFG4_GDSCR_ADDR, m) +#define HWIO_GCC_USB3_PHY_CFG4_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_USB3_PHY_CFG4_GDSCR_ADDR,v) +#define HWIO_GCC_USB3_PHY_CFG4_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB3_PHY_CFG4_GDSCR_ADDR,m,v,HWIO_GCC_USB3_PHY_CFG4_GDSCR_IN) +#define HWIO_GCC_USB3_PHY_CFG4_GDSCR_DLY_UNCLAMPIO_BMSK 0xf00000 +#define HWIO_GCC_USB3_PHY_CFG4_GDSCR_DLY_UNCLAMPIO_SHFT 0x14 +#define HWIO_GCC_USB3_PHY_CFG4_GDSCR_DLY_RESTOREFF_BMSK 0xf0000 +#define HWIO_GCC_USB3_PHY_CFG4_GDSCR_DLY_RESTOREFF_SHFT 0x10 +#define HWIO_GCC_USB3_PHY_CFG4_GDSCR_DLY_NORETAINFF_BMSK 0xf000 +#define HWIO_GCC_USB3_PHY_CFG4_GDSCR_DLY_NORETAINFF_SHFT 0xc +#define HWIO_GCC_USB3_PHY_CFG4_GDSCR_DLY_DEASSERTARES_BMSK 0xf00 +#define HWIO_GCC_USB3_PHY_CFG4_GDSCR_DLY_DEASSERTARES_SHFT 0x8 +#define HWIO_GCC_USB3_PHY_CFG4_GDSCR_DLY_CLAMPIO_BMSK 0xf0 +#define HWIO_GCC_USB3_PHY_CFG4_GDSCR_DLY_CLAMPIO_SHFT 0x4 +#define HWIO_GCC_USB3_PHY_CFG4_GDSCR_DLY_RETAINFF_BMSK 0xf +#define HWIO_GCC_USB3_PHY_CFG4_GDSCR_DLY_RETAINFF_SHFT 0x0 + +#define HWIO_GCC_QUSB2PHY_PRIM_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00002000) +#define HWIO_GCC_QUSB2PHY_PRIM_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00002000) +#define HWIO_GCC_QUSB2PHY_PRIM_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00002000) +#define HWIO_GCC_QUSB2PHY_PRIM_BCR_RMSK 0x1 +#define HWIO_GCC_QUSB2PHY_PRIM_BCR_ATTR 0x3 +#define HWIO_GCC_QUSB2PHY_PRIM_BCR_IN \ + in_dword_masked(HWIO_GCC_QUSB2PHY_PRIM_BCR_ADDR, HWIO_GCC_QUSB2PHY_PRIM_BCR_RMSK) +#define HWIO_GCC_QUSB2PHY_PRIM_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_QUSB2PHY_PRIM_BCR_ADDR, m) +#define HWIO_GCC_QUSB2PHY_PRIM_BCR_OUT(v) \ + out_dword(HWIO_GCC_QUSB2PHY_PRIM_BCR_ADDR,v) +#define HWIO_GCC_QUSB2PHY_PRIM_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUSB2PHY_PRIM_BCR_ADDR,m,v,HWIO_GCC_QUSB2PHY_PRIM_BCR_IN) +#define HWIO_GCC_QUSB2PHY_PRIM_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_QUSB2PHY_PRIM_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_QUSB2PHY_PRIM_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUSB2PHY_PRIM_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUSB2PHY_SEC_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00002004) +#define HWIO_GCC_QUSB2PHY_SEC_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00002004) +#define HWIO_GCC_QUSB2PHY_SEC_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00002004) +#define HWIO_GCC_QUSB2PHY_SEC_BCR_RMSK 0x1 +#define HWIO_GCC_QUSB2PHY_SEC_BCR_ATTR 0x3 +#define HWIO_GCC_QUSB2PHY_SEC_BCR_IN \ + in_dword_masked(HWIO_GCC_QUSB2PHY_SEC_BCR_ADDR, HWIO_GCC_QUSB2PHY_SEC_BCR_RMSK) +#define HWIO_GCC_QUSB2PHY_SEC_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_QUSB2PHY_SEC_BCR_ADDR, m) +#define HWIO_GCC_QUSB2PHY_SEC_BCR_OUT(v) \ + out_dword(HWIO_GCC_QUSB2PHY_SEC_BCR_ADDR,v) +#define HWIO_GCC_QUSB2PHY_SEC_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUSB2PHY_SEC_BCR_ADDR,m,v,HWIO_GCC_QUSB2PHY_SEC_BCR_IN) +#define HWIO_GCC_QUSB2PHY_SEC_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_QUSB2PHY_SEC_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_QUSB2PHY_SEC_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUSB2PHY_SEC_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005a000) +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005a000) +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005a000) +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_BCR_RMSK 0x1 +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_BCR_ATTR 0x3 +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_BCR_IN \ + in_dword_masked(HWIO_GCC_USB_PHY_CFG_AHB2PHY_BCR_ADDR, HWIO_GCC_USB_PHY_CFG_AHB2PHY_BCR_RMSK) +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_USB_PHY_CFG_AHB2PHY_BCR_ADDR, m) +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_BCR_OUT(v) \ + out_dword(HWIO_GCC_USB_PHY_CFG_AHB2PHY_BCR_ADDR,v) +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_USB_PHY_CFG_AHB2PHY_BCR_ADDR,m,v,HWIO_GCC_USB_PHY_CFG_AHB2PHY_BCR_IN) +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_AHB2PHY_0_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005a004) +#define HWIO_GCC_AHB2PHY_0_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005a004) +#define HWIO_GCC_AHB2PHY_0_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005a004) +#define HWIO_GCC_AHB2PHY_0_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_AHB2PHY_0_CBCR_ATTR 0x3 +#define HWIO_GCC_AHB2PHY_0_CBCR_IN \ + in_dword_masked(HWIO_GCC_AHB2PHY_0_CBCR_ADDR, HWIO_GCC_AHB2PHY_0_CBCR_RMSK) +#define HWIO_GCC_AHB2PHY_0_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_AHB2PHY_0_CBCR_ADDR, m) +#define HWIO_GCC_AHB2PHY_0_CBCR_OUT(v) \ + out_dword(HWIO_GCC_AHB2PHY_0_CBCR_ADDR,v) +#define HWIO_GCC_AHB2PHY_0_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AHB2PHY_0_CBCR_ADDR,m,v,HWIO_GCC_AHB2PHY_0_CBCR_IN) +#define HWIO_GCC_AHB2PHY_0_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_AHB2PHY_0_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_AHB2PHY_0_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_AHB2PHY_0_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_AHB2PHY_0_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_AHB2PHY_0_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_AHB2PHY_0_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_AHB2PHY_0_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_AHB2PHY_0_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_AHB2PHY_0_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_AHB2PHY_0_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_AHB2PHY_0_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_AHB2PHY_0_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_AHB2PHY_0_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_AHB2PHY_0_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_AHB2PHY_0_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_AHB2PHY_0_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_AHB2PHY_0_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_AHB2PHY_0_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_AHB2PHY_0_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_AHB2PHY_0_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_AHB2PHY_0_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_AHB2PHY_0_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AHB2PHY_0_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SDCC2_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00004000) +#define HWIO_GCC_SDCC2_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004000) +#define HWIO_GCC_SDCC2_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004000) +#define HWIO_GCC_SDCC2_BCR_RMSK 0x1 +#define HWIO_GCC_SDCC2_BCR_ATTR 0x3 +#define HWIO_GCC_SDCC2_BCR_IN \ + in_dword_masked(HWIO_GCC_SDCC2_BCR_ADDR, HWIO_GCC_SDCC2_BCR_RMSK) +#define HWIO_GCC_SDCC2_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_SDCC2_BCR_ADDR, m) +#define HWIO_GCC_SDCC2_BCR_OUT(v) \ + out_dword(HWIO_GCC_SDCC2_BCR_ADDR,v) +#define HWIO_GCC_SDCC2_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SDCC2_BCR_ADDR,m,v,HWIO_GCC_SDCC2_BCR_IN) +#define HWIO_GCC_SDCC2_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_SDCC2_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_SDCC2_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_SDCC2_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SDCC2_APPS_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00004004) +#define HWIO_GCC_SDCC2_APPS_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004004) +#define HWIO_GCC_SDCC2_APPS_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004004) +#define HWIO_GCC_SDCC2_APPS_CBCR_RMSK 0x81c07005 +#define HWIO_GCC_SDCC2_APPS_CBCR_ATTR 0x3 +#define HWIO_GCC_SDCC2_APPS_CBCR_IN \ + in_dword_masked(HWIO_GCC_SDCC2_APPS_CBCR_ADDR, HWIO_GCC_SDCC2_APPS_CBCR_RMSK) +#define HWIO_GCC_SDCC2_APPS_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_SDCC2_APPS_CBCR_ADDR, m) +#define HWIO_GCC_SDCC2_APPS_CBCR_OUT(v) \ + out_dword(HWIO_GCC_SDCC2_APPS_CBCR_ADDR,v) +#define HWIO_GCC_SDCC2_APPS_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SDCC2_APPS_CBCR_ADDR,m,v,HWIO_GCC_SDCC2_APPS_CBCR_IN) +#define HWIO_GCC_SDCC2_APPS_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SDCC2_APPS_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SDCC2_APPS_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_SDCC2_APPS_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_SDCC2_APPS_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_SDCC2_APPS_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_SDCC2_APPS_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_SDCC2_APPS_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_SDCC2_APPS_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_SDCC2_APPS_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_SDCC2_APPS_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SDCC2_APPS_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SDCC2_APPS_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_SDCC2_APPS_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_SDCC2_APPS_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SDCC2_APPS_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SDCC2_APPS_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_SDCC2_APPS_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_SDCC2_APPS_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SDCC2_APPS_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SDCC2_APPS_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_SDCC2_APPS_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_SDCC2_APPS_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SDCC2_APPS_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_SDCC2_APPS_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SDCC2_APPS_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SDCC2_APPS_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SDCC2_APPS_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SDCC2_APPS_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00004008) +#define HWIO_GCC_SDCC2_APPS_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004008) +#define HWIO_GCC_SDCC2_APPS_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004008) +#define HWIO_GCC_SDCC2_APPS_SREGR_RMSK 0xf1ffffe +#define HWIO_GCC_SDCC2_APPS_SREGR_ATTR 0x3 +#define HWIO_GCC_SDCC2_APPS_SREGR_IN \ + in_dword_masked(HWIO_GCC_SDCC2_APPS_SREGR_ADDR, HWIO_GCC_SDCC2_APPS_SREGR_RMSK) +#define HWIO_GCC_SDCC2_APPS_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_SDCC2_APPS_SREGR_ADDR, m) +#define HWIO_GCC_SDCC2_APPS_SREGR_OUT(v) \ + out_dword(HWIO_GCC_SDCC2_APPS_SREGR_ADDR,v) +#define HWIO_GCC_SDCC2_APPS_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SDCC2_APPS_SREGR_ADDR,m,v,HWIO_GCC_SDCC2_APPS_SREGR_IN) +#define HWIO_GCC_SDCC2_APPS_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xf000000 +#define HWIO_GCC_SDCC2_APPS_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_SDCC2_APPS_SREGR_PWR_FSM_CLK_SEL_BMSK 0x100000 +#define HWIO_GCC_SDCC2_APPS_SREGR_PWR_FSM_CLK_SEL_SHFT 0x14 +#define HWIO_GCC_SDCC2_APPS_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xf0000 +#define HWIO_GCC_SDCC2_APPS_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_SDCC2_APPS_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_SDCC2_APPS_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_SDCC2_APPS_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_SDCC2_APPS_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_SDCC2_APPS_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_SDCC2_APPS_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_SDCC2_APPS_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_SDCC2_APPS_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_SDCC2_APPS_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_SDCC2_APPS_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_SDCC2_APPS_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_SDCC2_APPS_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_SDCC2_APPS_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_SDCC2_APPS_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_SDCC2_APPS_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SDCC2_APPS_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_SDCC2_APPS_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_SDCC2_APPS_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_SDCC2_APPS_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_SDCC2_APPS_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_SDCC2_APPS_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_SDCC2_APPS_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_SDCC2_APPS_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_SDCC2_APPS_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_SDCC2_APPS_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_SDCC2_APPS_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_SDCC2_APPS_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_SDCC2_APPS_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_SDCC2_APPS_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SDCC2_APPS_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SDCC2_APPS_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_SDCC2_APPS_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_SDCC2_APPS_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_SDCC2_APPS_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SDCC2_APPS_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_SDCC2_APPS_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_SDCC2_APPS_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_SDCC2_APPS_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_SDCC2_APPS_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_SDCC2_APPS_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_SDCC2_APPS_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_SDCC2_APPS_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_SDCC2_APPS_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_SDCC2_APPS_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_SDCC2_APPS_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_SDCC2_APPS_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_SDCC2_APPS_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_SDCC2_APPS_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_SDCC2_APPS_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_SDCC2_APPS_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_SDCC2_APPS_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_SDCC2_APPS_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_SDCC2_APPS_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_SDCC2_APPS_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SDCC2_APPS_CFG_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000400c) +#define HWIO_GCC_SDCC2_APPS_CFG_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000400c) +#define HWIO_GCC_SDCC2_APPS_CFG_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000400c) +#define HWIO_GCC_SDCC2_APPS_CFG_SREGR_RMSK 0xffffffff +#define HWIO_GCC_SDCC2_APPS_CFG_SREGR_ATTR 0x3 +#define HWIO_GCC_SDCC2_APPS_CFG_SREGR_IN \ + in_dword_masked(HWIO_GCC_SDCC2_APPS_CFG_SREGR_ADDR, HWIO_GCC_SDCC2_APPS_CFG_SREGR_RMSK) +#define HWIO_GCC_SDCC2_APPS_CFG_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_SDCC2_APPS_CFG_SREGR_ADDR, m) +#define HWIO_GCC_SDCC2_APPS_CFG_SREGR_OUT(v) \ + out_dword(HWIO_GCC_SDCC2_APPS_CFG_SREGR_ADDR,v) +#define HWIO_GCC_SDCC2_APPS_CFG_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SDCC2_APPS_CFG_SREGR_ADDR,m,v,HWIO_GCC_SDCC2_APPS_CFG_SREGR_IN) +#define HWIO_GCC_SDCC2_APPS_CFG_SREGR_MEM_CORE_OFF_TIMER_BMSK 0xfc000000 +#define HWIO_GCC_SDCC2_APPS_CFG_SREGR_MEM_CORE_OFF_TIMER_SHFT 0x1a +#define HWIO_GCC_SDCC2_APPS_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_BMSK 0x2000000 +#define HWIO_GCC_SDCC2_APPS_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_SHFT 0x19 +#define HWIO_GCC_SDCC2_APPS_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_BMSK 0x1000000 +#define HWIO_GCC_SDCC2_APPS_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_SHFT 0x18 +#define HWIO_GCC_SDCC2_APPS_CFG_SREGR_MEM_PERIPH_ON_STATUS_BMSK 0x800000 +#define HWIO_GCC_SDCC2_APPS_CFG_SREGR_MEM_PERIPH_ON_STATUS_SHFT 0x17 +#define HWIO_GCC_SDCC2_APPS_CFG_SREGR_MEM_CORE_ON_STATUS_BMSK 0x400000 +#define HWIO_GCC_SDCC2_APPS_CFG_SREGR_MEM_CORE_ON_STATUS_SHFT 0x16 +#define HWIO_GCC_SDCC2_APPS_CFG_SREGR_MEM_CPH_TIMER_BMSK 0x3f0000 +#define HWIO_GCC_SDCC2_APPS_CFG_SREGR_MEM_CPH_TIMER_SHFT 0x10 +#define HWIO_GCC_SDCC2_APPS_CFG_SREGR_SLEEP_TIMER_BMSK 0xff00 +#define HWIO_GCC_SDCC2_APPS_CFG_SREGR_SLEEP_TIMER_SHFT 0x8 +#define HWIO_GCC_SDCC2_APPS_CFG_SREGR_WAKEUP_TIMER_BMSK 0xff +#define HWIO_GCC_SDCC2_APPS_CFG_SREGR_WAKEUP_TIMER_SHFT 0x0 + +#define HWIO_GCC_SDCC2_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00004010) +#define HWIO_GCC_SDCC2_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004010) +#define HWIO_GCC_SDCC2_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004010) +#define HWIO_GCC_SDCC2_AHB_CBCR_RMSK 0x81d00005 +#define HWIO_GCC_SDCC2_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_SDCC2_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_SDCC2_AHB_CBCR_ADDR, HWIO_GCC_SDCC2_AHB_CBCR_RMSK) +#define HWIO_GCC_SDCC2_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_SDCC2_AHB_CBCR_ADDR, m) +#define HWIO_GCC_SDCC2_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_SDCC2_AHB_CBCR_ADDR,v) +#define HWIO_GCC_SDCC2_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SDCC2_AHB_CBCR_ADDR,m,v,HWIO_GCC_SDCC2_AHB_CBCR_IN) +#define HWIO_GCC_SDCC2_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SDCC2_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SDCC2_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_SDCC2_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_SDCC2_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_SDCC2_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_SDCC2_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_SDCC2_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_SDCC2_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_SDCC2_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_SDCC2_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_SDCC2_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_SDCC2_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SDCC2_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_SDCC2_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SDCC2_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SDCC2_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SDCC2_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SDCC2_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00004014) +#define HWIO_GCC_SDCC2_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004014) +#define HWIO_GCC_SDCC2_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004014) +#define HWIO_GCC_SDCC2_AT_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_SDCC2_AT_CBCR_ATTR 0x3 +#define HWIO_GCC_SDCC2_AT_CBCR_IN \ + in_dword_masked(HWIO_GCC_SDCC2_AT_CBCR_ADDR, HWIO_GCC_SDCC2_AT_CBCR_RMSK) +#define HWIO_GCC_SDCC2_AT_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_SDCC2_AT_CBCR_ADDR, m) +#define HWIO_GCC_SDCC2_AT_CBCR_OUT(v) \ + out_dword(HWIO_GCC_SDCC2_AT_CBCR_ADDR,v) +#define HWIO_GCC_SDCC2_AT_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SDCC2_AT_CBCR_ADDR,m,v,HWIO_GCC_SDCC2_AT_CBCR_IN) +#define HWIO_GCC_SDCC2_AT_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SDCC2_AT_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SDCC2_AT_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_SDCC2_AT_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_SDCC2_AT_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_SDCC2_AT_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_SDCC2_AT_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_SDCC2_AT_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_SDCC2_AT_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_SDCC2_AT_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_SDCC2_AT_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_SDCC2_AT_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_SDCC2_AT_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_SDCC2_AT_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_SDCC2_AT_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SDCC2_AT_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_SDCC2_AT_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_SDCC2_AT_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_SDCC2_AT_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_SDCC2_AT_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_SDCC2_AT_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SDCC2_AT_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SDCC2_AT_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SDCC2_AT_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SDCC2_APPS_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00004018) +#define HWIO_GCC_SDCC2_APPS_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004018) +#define HWIO_GCC_SDCC2_APPS_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004018) +#define HWIO_GCC_SDCC2_APPS_CMD_RCGR_RMSK 0x800000f3 +#define HWIO_GCC_SDCC2_APPS_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_SDCC2_APPS_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_SDCC2_APPS_CMD_RCGR_ADDR, HWIO_GCC_SDCC2_APPS_CMD_RCGR_RMSK) +#define HWIO_GCC_SDCC2_APPS_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_SDCC2_APPS_CMD_RCGR_ADDR, m) +#define HWIO_GCC_SDCC2_APPS_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_SDCC2_APPS_CMD_RCGR_ADDR,v) +#define HWIO_GCC_SDCC2_APPS_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SDCC2_APPS_CMD_RCGR_ADDR,m,v,HWIO_GCC_SDCC2_APPS_CMD_RCGR_IN) +#define HWIO_GCC_SDCC2_APPS_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_SDCC2_APPS_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_SDCC2_APPS_CMD_RCGR_DIRTY_D_BMSK 0x80 +#define HWIO_GCC_SDCC2_APPS_CMD_RCGR_DIRTY_D_SHFT 0x7 +#define HWIO_GCC_SDCC2_APPS_CMD_RCGR_DIRTY_N_BMSK 0x40 +#define HWIO_GCC_SDCC2_APPS_CMD_RCGR_DIRTY_N_SHFT 0x6 +#define HWIO_GCC_SDCC2_APPS_CMD_RCGR_DIRTY_M_BMSK 0x20 +#define HWIO_GCC_SDCC2_APPS_CMD_RCGR_DIRTY_M_SHFT 0x5 +#define HWIO_GCC_SDCC2_APPS_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_SDCC2_APPS_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_SDCC2_APPS_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_SDCC2_APPS_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_SDCC2_APPS_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_SDCC2_APPS_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_SDCC2_APPS_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_SDCC2_APPS_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_SDCC2_APPS_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SDCC2_APPS_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000401c) +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000401c) +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000401c) +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_RMSK 0x10371f +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_SDCC2_APPS_CFG_RCGR_ADDR, HWIO_GCC_SDCC2_APPS_CFG_RCGR_RMSK) +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_SDCC2_APPS_CFG_RCGR_ADDR, m) +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_SDCC2_APPS_CFG_RCGR_ADDR,v) +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SDCC2_APPS_CFG_RCGR_ADDR,m,v,HWIO_GCC_SDCC2_APPS_CFG_RCGR_IN) +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_MODE_BMSK 0x3000 +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_MODE_SHFT 0xc +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_SDCC2_APPS_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00004020) +#define HWIO_GCC_SDCC2_APPS_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004020) +#define HWIO_GCC_SDCC2_APPS_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004020) +#define HWIO_GCC_SDCC2_APPS_M_RMSK 0xff +#define HWIO_GCC_SDCC2_APPS_M_ATTR 0x3 +#define HWIO_GCC_SDCC2_APPS_M_IN \ + in_dword_masked(HWIO_GCC_SDCC2_APPS_M_ADDR, HWIO_GCC_SDCC2_APPS_M_RMSK) +#define HWIO_GCC_SDCC2_APPS_M_INM(m) \ + in_dword_masked(HWIO_GCC_SDCC2_APPS_M_ADDR, m) +#define HWIO_GCC_SDCC2_APPS_M_OUT(v) \ + out_dword(HWIO_GCC_SDCC2_APPS_M_ADDR,v) +#define HWIO_GCC_SDCC2_APPS_M_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SDCC2_APPS_M_ADDR,m,v,HWIO_GCC_SDCC2_APPS_M_IN) +#define HWIO_GCC_SDCC2_APPS_M_M_BMSK 0xff +#define HWIO_GCC_SDCC2_APPS_M_M_SHFT 0x0 + +#define HWIO_GCC_SDCC2_APPS_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00004024) +#define HWIO_GCC_SDCC2_APPS_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004024) +#define HWIO_GCC_SDCC2_APPS_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004024) +#define HWIO_GCC_SDCC2_APPS_N_RMSK 0xff +#define HWIO_GCC_SDCC2_APPS_N_ATTR 0x3 +#define HWIO_GCC_SDCC2_APPS_N_IN \ + in_dword_masked(HWIO_GCC_SDCC2_APPS_N_ADDR, HWIO_GCC_SDCC2_APPS_N_RMSK) +#define HWIO_GCC_SDCC2_APPS_N_INM(m) \ + in_dword_masked(HWIO_GCC_SDCC2_APPS_N_ADDR, m) +#define HWIO_GCC_SDCC2_APPS_N_OUT(v) \ + out_dword(HWIO_GCC_SDCC2_APPS_N_ADDR,v) +#define HWIO_GCC_SDCC2_APPS_N_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SDCC2_APPS_N_ADDR,m,v,HWIO_GCC_SDCC2_APPS_N_IN) +#define HWIO_GCC_SDCC2_APPS_N_NOT_N_MINUS_M_BMSK 0xff +#define HWIO_GCC_SDCC2_APPS_N_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_SDCC2_APPS_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00004028) +#define HWIO_GCC_SDCC2_APPS_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004028) +#define HWIO_GCC_SDCC2_APPS_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004028) +#define HWIO_GCC_SDCC2_APPS_D_RMSK 0xff +#define HWIO_GCC_SDCC2_APPS_D_ATTR 0x3 +#define HWIO_GCC_SDCC2_APPS_D_IN \ + in_dword_masked(HWIO_GCC_SDCC2_APPS_D_ADDR, HWIO_GCC_SDCC2_APPS_D_RMSK) +#define HWIO_GCC_SDCC2_APPS_D_INM(m) \ + in_dword_masked(HWIO_GCC_SDCC2_APPS_D_ADDR, m) +#define HWIO_GCC_SDCC2_APPS_D_OUT(v) \ + out_dword(HWIO_GCC_SDCC2_APPS_D_ADDR,v) +#define HWIO_GCC_SDCC2_APPS_D_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SDCC2_APPS_D_ADDR,m,v,HWIO_GCC_SDCC2_APPS_D_IN) +#define HWIO_GCC_SDCC2_APPS_D_NOT_2D_BMSK 0xff +#define HWIO_GCC_SDCC2_APPS_D_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_SDCC4_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006000) +#define HWIO_GCC_SDCC4_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00006000) +#define HWIO_GCC_SDCC4_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00006000) +#define HWIO_GCC_SDCC4_BCR_RMSK 0x1 +#define HWIO_GCC_SDCC4_BCR_ATTR 0x3 +#define HWIO_GCC_SDCC4_BCR_IN \ + in_dword_masked(HWIO_GCC_SDCC4_BCR_ADDR, HWIO_GCC_SDCC4_BCR_RMSK) +#define HWIO_GCC_SDCC4_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_SDCC4_BCR_ADDR, m) +#define HWIO_GCC_SDCC4_BCR_OUT(v) \ + out_dword(HWIO_GCC_SDCC4_BCR_ADDR,v) +#define HWIO_GCC_SDCC4_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SDCC4_BCR_ADDR,m,v,HWIO_GCC_SDCC4_BCR_IN) +#define HWIO_GCC_SDCC4_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_SDCC4_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_SDCC4_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_SDCC4_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SDCC4_APPS_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006004) +#define HWIO_GCC_SDCC4_APPS_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00006004) +#define HWIO_GCC_SDCC4_APPS_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00006004) +#define HWIO_GCC_SDCC4_APPS_CBCR_RMSK 0x81c07005 +#define HWIO_GCC_SDCC4_APPS_CBCR_ATTR 0x3 +#define HWIO_GCC_SDCC4_APPS_CBCR_IN \ + in_dword_masked(HWIO_GCC_SDCC4_APPS_CBCR_ADDR, HWIO_GCC_SDCC4_APPS_CBCR_RMSK) +#define HWIO_GCC_SDCC4_APPS_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_SDCC4_APPS_CBCR_ADDR, m) +#define HWIO_GCC_SDCC4_APPS_CBCR_OUT(v) \ + out_dword(HWIO_GCC_SDCC4_APPS_CBCR_ADDR,v) +#define HWIO_GCC_SDCC4_APPS_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SDCC4_APPS_CBCR_ADDR,m,v,HWIO_GCC_SDCC4_APPS_CBCR_IN) +#define HWIO_GCC_SDCC4_APPS_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SDCC4_APPS_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SDCC4_APPS_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_SDCC4_APPS_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_SDCC4_APPS_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_SDCC4_APPS_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_SDCC4_APPS_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_SDCC4_APPS_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_SDCC4_APPS_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_SDCC4_APPS_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_SDCC4_APPS_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SDCC4_APPS_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SDCC4_APPS_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_SDCC4_APPS_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_SDCC4_APPS_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SDCC4_APPS_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SDCC4_APPS_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_SDCC4_APPS_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_SDCC4_APPS_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SDCC4_APPS_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SDCC4_APPS_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_SDCC4_APPS_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_SDCC4_APPS_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SDCC4_APPS_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_SDCC4_APPS_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SDCC4_APPS_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SDCC4_APPS_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SDCC4_APPS_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SDCC4_APPS_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006008) +#define HWIO_GCC_SDCC4_APPS_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00006008) +#define HWIO_GCC_SDCC4_APPS_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00006008) +#define HWIO_GCC_SDCC4_APPS_SREGR_RMSK 0xf1ffffe +#define HWIO_GCC_SDCC4_APPS_SREGR_ATTR 0x3 +#define HWIO_GCC_SDCC4_APPS_SREGR_IN \ + in_dword_masked(HWIO_GCC_SDCC4_APPS_SREGR_ADDR, HWIO_GCC_SDCC4_APPS_SREGR_RMSK) +#define HWIO_GCC_SDCC4_APPS_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_SDCC4_APPS_SREGR_ADDR, m) +#define HWIO_GCC_SDCC4_APPS_SREGR_OUT(v) \ + out_dword(HWIO_GCC_SDCC4_APPS_SREGR_ADDR,v) +#define HWIO_GCC_SDCC4_APPS_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SDCC4_APPS_SREGR_ADDR,m,v,HWIO_GCC_SDCC4_APPS_SREGR_IN) +#define HWIO_GCC_SDCC4_APPS_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xf000000 +#define HWIO_GCC_SDCC4_APPS_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_SDCC4_APPS_SREGR_PWR_FSM_CLK_SEL_BMSK 0x100000 +#define HWIO_GCC_SDCC4_APPS_SREGR_PWR_FSM_CLK_SEL_SHFT 0x14 +#define HWIO_GCC_SDCC4_APPS_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xf0000 +#define HWIO_GCC_SDCC4_APPS_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_SDCC4_APPS_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_SDCC4_APPS_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_SDCC4_APPS_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_SDCC4_APPS_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_SDCC4_APPS_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_SDCC4_APPS_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_SDCC4_APPS_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_SDCC4_APPS_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_SDCC4_APPS_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_SDCC4_APPS_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_SDCC4_APPS_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_SDCC4_APPS_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_SDCC4_APPS_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_SDCC4_APPS_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_SDCC4_APPS_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SDCC4_APPS_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_SDCC4_APPS_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_SDCC4_APPS_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_SDCC4_APPS_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_SDCC4_APPS_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_SDCC4_APPS_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_SDCC4_APPS_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_SDCC4_APPS_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_SDCC4_APPS_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_SDCC4_APPS_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_SDCC4_APPS_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_SDCC4_APPS_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_SDCC4_APPS_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_SDCC4_APPS_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SDCC4_APPS_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SDCC4_APPS_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_SDCC4_APPS_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_SDCC4_APPS_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_SDCC4_APPS_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SDCC4_APPS_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_SDCC4_APPS_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_SDCC4_APPS_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_SDCC4_APPS_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_SDCC4_APPS_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_SDCC4_APPS_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_SDCC4_APPS_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_SDCC4_APPS_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_SDCC4_APPS_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_SDCC4_APPS_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_SDCC4_APPS_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_SDCC4_APPS_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_SDCC4_APPS_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_SDCC4_APPS_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_SDCC4_APPS_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_SDCC4_APPS_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_SDCC4_APPS_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_SDCC4_APPS_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_SDCC4_APPS_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_SDCC4_APPS_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SDCC4_APPS_CFG_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000600c) +#define HWIO_GCC_SDCC4_APPS_CFG_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000600c) +#define HWIO_GCC_SDCC4_APPS_CFG_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000600c) +#define HWIO_GCC_SDCC4_APPS_CFG_SREGR_RMSK 0xffffffff +#define HWIO_GCC_SDCC4_APPS_CFG_SREGR_ATTR 0x3 +#define HWIO_GCC_SDCC4_APPS_CFG_SREGR_IN \ + in_dword_masked(HWIO_GCC_SDCC4_APPS_CFG_SREGR_ADDR, HWIO_GCC_SDCC4_APPS_CFG_SREGR_RMSK) +#define HWIO_GCC_SDCC4_APPS_CFG_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_SDCC4_APPS_CFG_SREGR_ADDR, m) +#define HWIO_GCC_SDCC4_APPS_CFG_SREGR_OUT(v) \ + out_dword(HWIO_GCC_SDCC4_APPS_CFG_SREGR_ADDR,v) +#define HWIO_GCC_SDCC4_APPS_CFG_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SDCC4_APPS_CFG_SREGR_ADDR,m,v,HWIO_GCC_SDCC4_APPS_CFG_SREGR_IN) +#define HWIO_GCC_SDCC4_APPS_CFG_SREGR_MEM_CORE_OFF_TIMER_BMSK 0xfc000000 +#define HWIO_GCC_SDCC4_APPS_CFG_SREGR_MEM_CORE_OFF_TIMER_SHFT 0x1a +#define HWIO_GCC_SDCC4_APPS_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_BMSK 0x2000000 +#define HWIO_GCC_SDCC4_APPS_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_SHFT 0x19 +#define HWIO_GCC_SDCC4_APPS_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_BMSK 0x1000000 +#define HWIO_GCC_SDCC4_APPS_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_SHFT 0x18 +#define HWIO_GCC_SDCC4_APPS_CFG_SREGR_MEM_PERIPH_ON_STATUS_BMSK 0x800000 +#define HWIO_GCC_SDCC4_APPS_CFG_SREGR_MEM_PERIPH_ON_STATUS_SHFT 0x17 +#define HWIO_GCC_SDCC4_APPS_CFG_SREGR_MEM_CORE_ON_STATUS_BMSK 0x400000 +#define HWIO_GCC_SDCC4_APPS_CFG_SREGR_MEM_CORE_ON_STATUS_SHFT 0x16 +#define HWIO_GCC_SDCC4_APPS_CFG_SREGR_MEM_CPH_TIMER_BMSK 0x3f0000 +#define HWIO_GCC_SDCC4_APPS_CFG_SREGR_MEM_CPH_TIMER_SHFT 0x10 +#define HWIO_GCC_SDCC4_APPS_CFG_SREGR_SLEEP_TIMER_BMSK 0xff00 +#define HWIO_GCC_SDCC4_APPS_CFG_SREGR_SLEEP_TIMER_SHFT 0x8 +#define HWIO_GCC_SDCC4_APPS_CFG_SREGR_WAKEUP_TIMER_BMSK 0xff +#define HWIO_GCC_SDCC4_APPS_CFG_SREGR_WAKEUP_TIMER_SHFT 0x0 + +#define HWIO_GCC_SDCC4_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006010) +#define HWIO_GCC_SDCC4_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00006010) +#define HWIO_GCC_SDCC4_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00006010) +#define HWIO_GCC_SDCC4_AHB_CBCR_RMSK 0x81d00005 +#define HWIO_GCC_SDCC4_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_SDCC4_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_SDCC4_AHB_CBCR_ADDR, HWIO_GCC_SDCC4_AHB_CBCR_RMSK) +#define HWIO_GCC_SDCC4_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_SDCC4_AHB_CBCR_ADDR, m) +#define HWIO_GCC_SDCC4_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_SDCC4_AHB_CBCR_ADDR,v) +#define HWIO_GCC_SDCC4_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SDCC4_AHB_CBCR_ADDR,m,v,HWIO_GCC_SDCC4_AHB_CBCR_IN) +#define HWIO_GCC_SDCC4_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SDCC4_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SDCC4_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_SDCC4_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_SDCC4_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_SDCC4_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_SDCC4_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_SDCC4_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_SDCC4_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_SDCC4_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_SDCC4_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_SDCC4_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_SDCC4_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SDCC4_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_SDCC4_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SDCC4_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SDCC4_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SDCC4_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SDCC4_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006014) +#define HWIO_GCC_SDCC4_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00006014) +#define HWIO_GCC_SDCC4_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00006014) +#define HWIO_GCC_SDCC4_AT_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_SDCC4_AT_CBCR_ATTR 0x3 +#define HWIO_GCC_SDCC4_AT_CBCR_IN \ + in_dword_masked(HWIO_GCC_SDCC4_AT_CBCR_ADDR, HWIO_GCC_SDCC4_AT_CBCR_RMSK) +#define HWIO_GCC_SDCC4_AT_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_SDCC4_AT_CBCR_ADDR, m) +#define HWIO_GCC_SDCC4_AT_CBCR_OUT(v) \ + out_dword(HWIO_GCC_SDCC4_AT_CBCR_ADDR,v) +#define HWIO_GCC_SDCC4_AT_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SDCC4_AT_CBCR_ADDR,m,v,HWIO_GCC_SDCC4_AT_CBCR_IN) +#define HWIO_GCC_SDCC4_AT_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SDCC4_AT_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SDCC4_AT_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_SDCC4_AT_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_SDCC4_AT_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_SDCC4_AT_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_SDCC4_AT_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_SDCC4_AT_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_SDCC4_AT_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_SDCC4_AT_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_SDCC4_AT_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_SDCC4_AT_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_SDCC4_AT_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_SDCC4_AT_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_SDCC4_AT_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SDCC4_AT_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_SDCC4_AT_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_SDCC4_AT_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_SDCC4_AT_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_SDCC4_AT_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_SDCC4_AT_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SDCC4_AT_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SDCC4_AT_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SDCC4_AT_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SDCC4_APPS_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006018) +#define HWIO_GCC_SDCC4_APPS_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00006018) +#define HWIO_GCC_SDCC4_APPS_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00006018) +#define HWIO_GCC_SDCC4_APPS_CMD_RCGR_RMSK 0x800000f3 +#define HWIO_GCC_SDCC4_APPS_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_SDCC4_APPS_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_SDCC4_APPS_CMD_RCGR_ADDR, HWIO_GCC_SDCC4_APPS_CMD_RCGR_RMSK) +#define HWIO_GCC_SDCC4_APPS_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_SDCC4_APPS_CMD_RCGR_ADDR, m) +#define HWIO_GCC_SDCC4_APPS_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_SDCC4_APPS_CMD_RCGR_ADDR,v) +#define HWIO_GCC_SDCC4_APPS_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SDCC4_APPS_CMD_RCGR_ADDR,m,v,HWIO_GCC_SDCC4_APPS_CMD_RCGR_IN) +#define HWIO_GCC_SDCC4_APPS_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_SDCC4_APPS_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_SDCC4_APPS_CMD_RCGR_DIRTY_D_BMSK 0x80 +#define HWIO_GCC_SDCC4_APPS_CMD_RCGR_DIRTY_D_SHFT 0x7 +#define HWIO_GCC_SDCC4_APPS_CMD_RCGR_DIRTY_N_BMSK 0x40 +#define HWIO_GCC_SDCC4_APPS_CMD_RCGR_DIRTY_N_SHFT 0x6 +#define HWIO_GCC_SDCC4_APPS_CMD_RCGR_DIRTY_M_BMSK 0x20 +#define HWIO_GCC_SDCC4_APPS_CMD_RCGR_DIRTY_M_SHFT 0x5 +#define HWIO_GCC_SDCC4_APPS_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_SDCC4_APPS_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_SDCC4_APPS_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_SDCC4_APPS_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_SDCC4_APPS_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_SDCC4_APPS_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_SDCC4_APPS_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_SDCC4_APPS_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_SDCC4_APPS_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SDCC4_APPS_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000601c) +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000601c) +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000601c) +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_RMSK 0x10371f +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_SDCC4_APPS_CFG_RCGR_ADDR, HWIO_GCC_SDCC4_APPS_CFG_RCGR_RMSK) +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_SDCC4_APPS_CFG_RCGR_ADDR, m) +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_SDCC4_APPS_CFG_RCGR_ADDR,v) +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SDCC4_APPS_CFG_RCGR_ADDR,m,v,HWIO_GCC_SDCC4_APPS_CFG_RCGR_IN) +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_MODE_BMSK 0x3000 +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_MODE_SHFT 0xc +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_SDCC4_APPS_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006020) +#define HWIO_GCC_SDCC4_APPS_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00006020) +#define HWIO_GCC_SDCC4_APPS_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00006020) +#define HWIO_GCC_SDCC4_APPS_M_RMSK 0xff +#define HWIO_GCC_SDCC4_APPS_M_ATTR 0x3 +#define HWIO_GCC_SDCC4_APPS_M_IN \ + in_dword_masked(HWIO_GCC_SDCC4_APPS_M_ADDR, HWIO_GCC_SDCC4_APPS_M_RMSK) +#define HWIO_GCC_SDCC4_APPS_M_INM(m) \ + in_dword_masked(HWIO_GCC_SDCC4_APPS_M_ADDR, m) +#define HWIO_GCC_SDCC4_APPS_M_OUT(v) \ + out_dword(HWIO_GCC_SDCC4_APPS_M_ADDR,v) +#define HWIO_GCC_SDCC4_APPS_M_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SDCC4_APPS_M_ADDR,m,v,HWIO_GCC_SDCC4_APPS_M_IN) +#define HWIO_GCC_SDCC4_APPS_M_M_BMSK 0xff +#define HWIO_GCC_SDCC4_APPS_M_M_SHFT 0x0 + +#define HWIO_GCC_SDCC4_APPS_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006024) +#define HWIO_GCC_SDCC4_APPS_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00006024) +#define HWIO_GCC_SDCC4_APPS_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00006024) +#define HWIO_GCC_SDCC4_APPS_N_RMSK 0xff +#define HWIO_GCC_SDCC4_APPS_N_ATTR 0x3 +#define HWIO_GCC_SDCC4_APPS_N_IN \ + in_dword_masked(HWIO_GCC_SDCC4_APPS_N_ADDR, HWIO_GCC_SDCC4_APPS_N_RMSK) +#define HWIO_GCC_SDCC4_APPS_N_INM(m) \ + in_dword_masked(HWIO_GCC_SDCC4_APPS_N_ADDR, m) +#define HWIO_GCC_SDCC4_APPS_N_OUT(v) \ + out_dword(HWIO_GCC_SDCC4_APPS_N_ADDR,v) +#define HWIO_GCC_SDCC4_APPS_N_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SDCC4_APPS_N_ADDR,m,v,HWIO_GCC_SDCC4_APPS_N_IN) +#define HWIO_GCC_SDCC4_APPS_N_NOT_N_MINUS_M_BMSK 0xff +#define HWIO_GCC_SDCC4_APPS_N_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_SDCC4_APPS_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006028) +#define HWIO_GCC_SDCC4_APPS_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00006028) +#define HWIO_GCC_SDCC4_APPS_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00006028) +#define HWIO_GCC_SDCC4_APPS_D_RMSK 0xff +#define HWIO_GCC_SDCC4_APPS_D_ATTR 0x3 +#define HWIO_GCC_SDCC4_APPS_D_IN \ + in_dword_masked(HWIO_GCC_SDCC4_APPS_D_ADDR, HWIO_GCC_SDCC4_APPS_D_RMSK) +#define HWIO_GCC_SDCC4_APPS_D_INM(m) \ + in_dword_masked(HWIO_GCC_SDCC4_APPS_D_ADDR, m) +#define HWIO_GCC_SDCC4_APPS_D_OUT(v) \ + out_dword(HWIO_GCC_SDCC4_APPS_D_ADDR,v) +#define HWIO_GCC_SDCC4_APPS_D_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SDCC4_APPS_D_ADDR,m,v,HWIO_GCC_SDCC4_APPS_D_IN) +#define HWIO_GCC_SDCC4_APPS_D_NOT_2D_BMSK 0xff +#define HWIO_GCC_SDCC4_APPS_D_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAPPER_I2C_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00007000) +#define HWIO_GCC_QUPV3_WRAPPER_I2C_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00007000) +#define HWIO_GCC_QUPV3_WRAPPER_I2C_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00007000) +#define HWIO_GCC_QUPV3_WRAPPER_I2C_BCR_RMSK 0x1 +#define HWIO_GCC_QUPV3_WRAPPER_I2C_BCR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAPPER_I2C_BCR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAPPER_I2C_BCR_ADDR, HWIO_GCC_QUPV3_WRAPPER_I2C_BCR_RMSK) +#define HWIO_GCC_QUPV3_WRAPPER_I2C_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAPPER_I2C_BCR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAPPER_I2C_BCR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAPPER_I2C_BCR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAPPER_I2C_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAPPER_I2C_BCR_ADDR,m,v,HWIO_GCC_QUPV3_WRAPPER_I2C_BCR_IN) +#define HWIO_GCC_QUPV3_WRAPPER_I2C_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_QUPV3_WRAPPER_I2C_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAPPER_I2C_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAPPER_I2C_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_I2C_S_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00013140) +#define HWIO_GCC_QUPV3_I2C_S_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00013140) +#define HWIO_GCC_QUPV3_I2C_S_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00013140) +#define HWIO_GCC_QUPV3_I2C_S_AHB_CBCR_RMSK 0x81d0000e +#define HWIO_GCC_QUPV3_I2C_S_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_QUPV3_I2C_S_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_S_AHB_CBCR_ADDR, HWIO_GCC_QUPV3_I2C_S_AHB_CBCR_RMSK) +#define HWIO_GCC_QUPV3_I2C_S_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_S_AHB_CBCR_ADDR, m) +#define HWIO_GCC_QUPV3_I2C_S_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_I2C_S_AHB_CBCR_ADDR,v) +#define HWIO_GCC_QUPV3_I2C_S_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_I2C_S_AHB_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_I2C_S_AHB_CBCR_IN) +#define HWIO_GCC_QUPV3_I2C_S_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_I2C_S_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_I2C_S_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QUPV3_I2C_S_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QUPV3_I2C_S_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QUPV3_I2C_S_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QUPV3_I2C_S_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QUPV3_I2C_S_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QUPV3_I2C_S_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_QUPV3_I2C_S_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_QUPV3_I2C_S_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_QUPV3_I2C_S_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_QUPV3_I2C_S_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QUPV3_I2C_S_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QUPV3_I2C_S_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_S_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_QUPV3_I2C_S_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_QUPV3_I2C_S_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_I2C_CORE_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00013144) +#define HWIO_GCC_QUPV3_I2C_CORE_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00013144) +#define HWIO_GCC_QUPV3_I2C_CORE_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00013144) +#define HWIO_GCC_QUPV3_I2C_CORE_CBCR_RMSK 0x81d07004 +#define HWIO_GCC_QUPV3_I2C_CORE_CBCR_ATTR 0x3 +#define HWIO_GCC_QUPV3_I2C_CORE_CBCR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_CORE_CBCR_ADDR, HWIO_GCC_QUPV3_I2C_CORE_CBCR_RMSK) +#define HWIO_GCC_QUPV3_I2C_CORE_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_CORE_CBCR_ADDR, m) +#define HWIO_GCC_QUPV3_I2C_CORE_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_I2C_CORE_CBCR_ADDR,v) +#define HWIO_GCC_QUPV3_I2C_CORE_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_I2C_CORE_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_I2C_CORE_CBCR_IN) +#define HWIO_GCC_QUPV3_I2C_CORE_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_I2C_CORE_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_I2C_CORE_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QUPV3_I2C_CORE_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QUPV3_I2C_CORE_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QUPV3_I2C_CORE_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QUPV3_I2C_CORE_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QUPV3_I2C_CORE_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QUPV3_I2C_CORE_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_QUPV3_I2C_CORE_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_QUPV3_I2C_CORE_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_QUPV3_I2C_CORE_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_QUPV3_I2C_CORE_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_CORE_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_CORE_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_QUPV3_I2C_CORE_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_QUPV3_I2C_CORE_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_CORE_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_CORE_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_QUPV3_I2C_CORE_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_QUPV3_I2C_CORE_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_CORE_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_CORE_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QUPV3_I2C_CORE_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QUPV3_I2C_CORE_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_CORE_CBCR_CLK_ARES_RESET_FVAL 0x1 + +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00013148) +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00013148) +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00013148) +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_RMSK 0xf1ffffe +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_CORE_SREGR_ADDR, HWIO_GCC_QUPV3_I2C_CORE_SREGR_RMSK) +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_CORE_SREGR_ADDR, m) +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_I2C_CORE_SREGR_ADDR,v) +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_I2C_CORE_SREGR_ADDR,m,v,HWIO_GCC_QUPV3_I2C_CORE_SREGR_IN) +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xf000000 +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_PWR_FSM_CLK_SEL_BMSK 0x100000 +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_PWR_FSM_CLK_SEL_SHFT 0x14 +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xf0000 +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_CORE_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001314c) +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001314c) +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001314c) +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_SREGR_RMSK 0xffffffff +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_SREGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_SREGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_CORE_CFG_SREGR_ADDR, HWIO_GCC_QUPV3_I2C_CORE_CFG_SREGR_RMSK) +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_CORE_CFG_SREGR_ADDR, m) +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_SREGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_I2C_CORE_CFG_SREGR_ADDR,v) +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_I2C_CORE_CFG_SREGR_ADDR,m,v,HWIO_GCC_QUPV3_I2C_CORE_CFG_SREGR_IN) +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_SREGR_MEM_CORE_OFF_TIMER_BMSK 0xfc000000 +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_SREGR_MEM_CORE_OFF_TIMER_SHFT 0x1a +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_BMSK 0x2000000 +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_SHFT 0x19 +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_BMSK 0x1000000 +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_SHFT 0x18 +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_SREGR_MEM_PERIPH_ON_STATUS_BMSK 0x800000 +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_SREGR_MEM_PERIPH_ON_STATUS_SHFT 0x17 +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_SREGR_MEM_CORE_ON_STATUS_BMSK 0x400000 +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_SREGR_MEM_CORE_ON_STATUS_SHFT 0x16 +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_SREGR_MEM_CPH_TIMER_BMSK 0x3f0000 +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_SREGR_MEM_CPH_TIMER_SHFT 0x10 +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_SREGR_SLEEP_TIMER_BMSK 0xff00 +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_SREGR_SLEEP_TIMER_SHFT 0x8 +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_SREGR_WAKEUP_TIMER_BMSK 0xff +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_SREGR_WAKEUP_TIMER_SHFT 0x0 + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00013164) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00013164) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00013164) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_RMSK 0x3ffff +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_RCG_SW_CTRL_BMSK 0x38000 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_RCG_SW_CTRL_SHFT 0xf +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_SW_PERF_STATE_BMSK 0x7800 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_SW_PERF_STATE_SHFT 0xb +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_SW_OVERRIDE_BMSK 0x400 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_SW_OVERRIDE_SHFT 0xa +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK 0x200 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_DFS_FSM_STATE_BMSK 0x1c0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_DFS_FSM_STATE_SHFT 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_HW_CLK_CONTROL_BMSK 0x20 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_HW_CLK_CONTROL_SHFT 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_CURR_PERF_STATE_BMSK 0x1e +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_CURR_PERF_STATE_SHFT 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_DFS_EN_BMSK 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_DFS_EN_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_DFS_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_DFS_EN_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001316c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001316c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001316c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF0_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF0_DFSR_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF0_DFSR_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF0_DFSR_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00013170) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00013170) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00013170) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF1_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF1_DFSR_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF1_DFSR_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF1_DFSR_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00013174) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00013174) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00013174) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF2_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF2_DFSR_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF2_DFSR_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF2_DFSR_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00013178) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00013178) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00013178) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF3_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF3_DFSR_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF3_DFSR_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF3_DFSR_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001317c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001317c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001317c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF4_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF4_DFSR_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF4_DFSR_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF4_DFSR_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00013180) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00013180) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00013180) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF5_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF5_DFSR_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF5_DFSR_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF5_DFSR_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00013184) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00013184) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00013184) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF6_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF6_DFSR_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF6_DFSR_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF6_DFSR_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00013188) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00013188) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00013188) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF7_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF7_DFSR_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF7_DFSR_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF7_DFSR_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF8_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001318c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF8_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001318c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF8_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001318c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF8_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF8_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF8_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF8_DFSR_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF8_DFSR_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF8_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF8_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF8_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF8_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF8_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF8_DFSR_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF8_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF8_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF8_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF8_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF8_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF8_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF8_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF8_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF8_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF8_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF8_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF8_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF8_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF8_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF8_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF8_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF8_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF8_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF8_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF8_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF8_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF8_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF8_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF8_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF8_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF8_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF8_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF8_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF8_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF8_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF8_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF8_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF8_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF8_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF8_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF8_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF8_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF8_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF8_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF8_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF8_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF8_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF8_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF8_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF9_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00013190) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF9_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00013190) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF9_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00013190) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF9_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF9_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF9_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF9_DFSR_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF9_DFSR_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF9_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF9_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF9_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF9_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF9_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF9_DFSR_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF9_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF9_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF9_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF9_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF9_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF9_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF9_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF9_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF9_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF9_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF9_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF9_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF9_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF9_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF9_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF9_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF9_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF9_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF9_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF9_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF9_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF9_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF9_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF9_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF9_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF9_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF9_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF9_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF9_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF9_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF9_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF9_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF9_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF9_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF9_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF9_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF9_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF9_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF9_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF9_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF9_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF9_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF9_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF9_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF10_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00013194) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF10_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00013194) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF10_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00013194) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF10_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF10_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF10_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF10_DFSR_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF10_DFSR_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF10_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF10_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF10_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF10_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF10_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF10_DFSR_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF10_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF10_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF10_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF10_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF10_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF10_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF10_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF10_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF10_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF10_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF10_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF10_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF10_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF10_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF10_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF10_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF10_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF10_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF10_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF10_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF10_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF10_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF10_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF10_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF10_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF10_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF10_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF10_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF10_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF10_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF10_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF10_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF10_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF10_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF10_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF10_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF10_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF10_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF10_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF10_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF10_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF10_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF10_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF10_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF11_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00013198) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF11_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00013198) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF11_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00013198) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF11_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF11_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF11_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF11_DFSR_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF11_DFSR_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF11_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF11_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF11_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF11_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF11_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF11_DFSR_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF11_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF11_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF11_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF11_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF11_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF11_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF11_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF11_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF11_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF11_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF11_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF11_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF11_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF11_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF11_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF11_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF11_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF11_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF11_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF11_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF11_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF11_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF11_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF11_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF11_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF11_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF11_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF11_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF11_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF11_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF11_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF11_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF11_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF11_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF11_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF11_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF11_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF11_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF11_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF11_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF11_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF11_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF11_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF11_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF12_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001319c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF12_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001319c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF12_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001319c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF12_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF12_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF12_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF12_DFSR_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF12_DFSR_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF12_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF12_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF12_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF12_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF12_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF12_DFSR_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF12_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF12_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF12_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF12_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF12_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF12_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF12_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF12_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF12_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF12_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF12_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF12_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF12_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF12_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF12_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF12_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF12_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF12_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF12_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF12_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF12_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF12_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF12_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF12_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF12_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF12_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF12_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF12_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF12_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF12_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF12_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF12_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF12_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF12_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF12_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF12_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF12_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF12_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF12_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF12_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF12_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF12_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF12_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF12_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF13_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000131a0) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF13_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000131a0) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF13_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000131a0) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF13_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF13_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF13_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF13_DFSR_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF13_DFSR_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF13_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF13_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF13_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF13_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF13_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF13_DFSR_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF13_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF13_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF13_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF13_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF13_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF13_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF13_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF13_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF13_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF13_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF13_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF13_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF13_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF13_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF13_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF13_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF13_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF13_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF13_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF13_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF13_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF13_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF13_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF13_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF13_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF13_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF13_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF13_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF13_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF13_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF13_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF13_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF13_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF13_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF13_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF13_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF13_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF13_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF13_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF13_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF13_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF13_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF13_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF13_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF14_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000131a4) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF14_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000131a4) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF14_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000131a4) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF14_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF14_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF14_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF14_DFSR_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF14_DFSR_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF14_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF14_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF14_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF14_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF14_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF14_DFSR_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF14_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF14_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF14_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF14_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF14_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF14_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF14_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF14_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF14_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF14_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF14_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF14_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF14_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF14_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF14_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF14_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF14_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF14_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF14_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF14_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF14_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF14_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF14_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF14_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF14_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF14_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF14_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF14_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF14_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF14_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF14_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF14_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF14_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF14_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF14_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF14_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF14_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF14_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF14_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF14_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF14_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF14_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF14_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF14_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF15_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000131a8) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF15_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000131a8) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF15_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000131a8) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF15_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF15_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF15_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF15_DFSR_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF15_DFSR_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF15_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF15_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF15_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF15_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF15_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF15_DFSR_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF15_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF15_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF15_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF15_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF15_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF15_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF15_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF15_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF15_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF15_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF15_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF15_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF15_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF15_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF15_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF15_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF15_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF15_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF15_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF15_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF15_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF15_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF15_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF15_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF15_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF15_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF15_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF15_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF15_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF15_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF15_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF15_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF15_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF15_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF15_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF15_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF15_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF15_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF15_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF15_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF15_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF15_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF15_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF15_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_I2C_CORE_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00013150) +#define HWIO_GCC_QUPV3_I2C_CORE_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00013150) +#define HWIO_GCC_QUPV3_I2C_CORE_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00013150) +#define HWIO_GCC_QUPV3_I2C_CORE_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_QUPV3_I2C_CORE_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_I2C_CORE_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_CORE_CMD_RCGR_ADDR, HWIO_GCC_QUPV3_I2C_CORE_CMD_RCGR_RMSK) +#define HWIO_GCC_QUPV3_I2C_CORE_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_CORE_CMD_RCGR_ADDR, m) +#define HWIO_GCC_QUPV3_I2C_CORE_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_I2C_CORE_CMD_RCGR_ADDR,v) +#define HWIO_GCC_QUPV3_I2C_CORE_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_I2C_CORE_CMD_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_I2C_CORE_CMD_RCGR_IN) +#define HWIO_GCC_QUPV3_I2C_CORE_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_I2C_CORE_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_I2C_CORE_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_QUPV3_I2C_CORE_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_QUPV3_I2C_CORE_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_QUPV3_I2C_CORE_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_QUPV3_I2C_CORE_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_CORE_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_CORE_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_QUPV3_I2C_CORE_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_QUPV3_I2C_CORE_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_CORE_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00013154) +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00013154) +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00013154) +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_ADDR, HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_RMSK) +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_ADDR, m) +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_ADDR,v) +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_IN) +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_I2C_CORE_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_I2C_S0_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00007004) +#define HWIO_GCC_QUPV3_I2C_S0_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00007004) +#define HWIO_GCC_QUPV3_I2C_S0_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00007004) +#define HWIO_GCC_QUPV3_I2C_S0_CBCR_RMSK 0x81c00004 +#define HWIO_GCC_QUPV3_I2C_S0_CBCR_ATTR 0x3 +#define HWIO_GCC_QUPV3_I2C_S0_CBCR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_S0_CBCR_ADDR, HWIO_GCC_QUPV3_I2C_S0_CBCR_RMSK) +#define HWIO_GCC_QUPV3_I2C_S0_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_S0_CBCR_ADDR, m) +#define HWIO_GCC_QUPV3_I2C_S0_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_I2C_S0_CBCR_ADDR,v) +#define HWIO_GCC_QUPV3_I2C_S0_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_I2C_S0_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_I2C_S0_CBCR_IN) +#define HWIO_GCC_QUPV3_I2C_S0_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_I2C_S0_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_I2C_S0_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QUPV3_I2C_S0_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QUPV3_I2C_S0_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QUPV3_I2C_S0_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QUPV3_I2C_S0_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QUPV3_I2C_S0_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QUPV3_I2C_S0_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QUPV3_I2C_S0_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QUPV3_I2C_S0_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S0_CBCR_CLK_ARES_RESET_FVAL 0x1 + +#define HWIO_GCC_QUPV3_I2C_S0_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00007008) +#define HWIO_GCC_QUPV3_I2C_S0_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00007008) +#define HWIO_GCC_QUPV3_I2C_S0_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00007008) +#define HWIO_GCC_QUPV3_I2C_S0_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_QUPV3_I2C_S0_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_I2C_S0_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_S0_CMD_RCGR_ADDR, HWIO_GCC_QUPV3_I2C_S0_CMD_RCGR_RMSK) +#define HWIO_GCC_QUPV3_I2C_S0_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_S0_CMD_RCGR_ADDR, m) +#define HWIO_GCC_QUPV3_I2C_S0_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_I2C_S0_CMD_RCGR_ADDR,v) +#define HWIO_GCC_QUPV3_I2C_S0_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_I2C_S0_CMD_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_I2C_S0_CMD_RCGR_IN) +#define HWIO_GCC_QUPV3_I2C_S0_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_I2C_S0_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_I2C_S0_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_QUPV3_I2C_S0_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_QUPV3_I2C_S0_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_QUPV3_I2C_S0_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_QUPV3_I2C_S0_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S0_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_S0_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_QUPV3_I2C_S0_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_QUPV3_I2C_S0_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S0_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000700c) +#define HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000700c) +#define HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000700c) +#define HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_ADDR, HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_RMSK) +#define HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_ADDR, m) +#define HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_ADDR,v) +#define HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_IN) +#define HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_I2C_S0_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_I2C_S1_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00007020) +#define HWIO_GCC_QUPV3_I2C_S1_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00007020) +#define HWIO_GCC_QUPV3_I2C_S1_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00007020) +#define HWIO_GCC_QUPV3_I2C_S1_CBCR_RMSK 0x81c00004 +#define HWIO_GCC_QUPV3_I2C_S1_CBCR_ATTR 0x3 +#define HWIO_GCC_QUPV3_I2C_S1_CBCR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_S1_CBCR_ADDR, HWIO_GCC_QUPV3_I2C_S1_CBCR_RMSK) +#define HWIO_GCC_QUPV3_I2C_S1_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_S1_CBCR_ADDR, m) +#define HWIO_GCC_QUPV3_I2C_S1_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_I2C_S1_CBCR_ADDR,v) +#define HWIO_GCC_QUPV3_I2C_S1_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_I2C_S1_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_I2C_S1_CBCR_IN) +#define HWIO_GCC_QUPV3_I2C_S1_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_I2C_S1_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_I2C_S1_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QUPV3_I2C_S1_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QUPV3_I2C_S1_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QUPV3_I2C_S1_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QUPV3_I2C_S1_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QUPV3_I2C_S1_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QUPV3_I2C_S1_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QUPV3_I2C_S1_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QUPV3_I2C_S1_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S1_CBCR_CLK_ARES_RESET_FVAL 0x1 + +#define HWIO_GCC_QUPV3_I2C_S1_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00007024) +#define HWIO_GCC_QUPV3_I2C_S1_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00007024) +#define HWIO_GCC_QUPV3_I2C_S1_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00007024) +#define HWIO_GCC_QUPV3_I2C_S1_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_QUPV3_I2C_S1_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_I2C_S1_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_S1_CMD_RCGR_ADDR, HWIO_GCC_QUPV3_I2C_S1_CMD_RCGR_RMSK) +#define HWIO_GCC_QUPV3_I2C_S1_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_S1_CMD_RCGR_ADDR, m) +#define HWIO_GCC_QUPV3_I2C_S1_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_I2C_S1_CMD_RCGR_ADDR,v) +#define HWIO_GCC_QUPV3_I2C_S1_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_I2C_S1_CMD_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_I2C_S1_CMD_RCGR_IN) +#define HWIO_GCC_QUPV3_I2C_S1_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_I2C_S1_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_I2C_S1_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_QUPV3_I2C_S1_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_QUPV3_I2C_S1_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_QUPV3_I2C_S1_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_QUPV3_I2C_S1_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S1_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_S1_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_QUPV3_I2C_S1_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_QUPV3_I2C_S1_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S1_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00007028) +#define HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00007028) +#define HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00007028) +#define HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_ADDR, HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_RMSK) +#define HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_ADDR, m) +#define HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_ADDR,v) +#define HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_IN) +#define HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_I2C_S1_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_I2C_S2_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000703c) +#define HWIO_GCC_QUPV3_I2C_S2_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000703c) +#define HWIO_GCC_QUPV3_I2C_S2_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000703c) +#define HWIO_GCC_QUPV3_I2C_S2_CBCR_RMSK 0x81c00004 +#define HWIO_GCC_QUPV3_I2C_S2_CBCR_ATTR 0x3 +#define HWIO_GCC_QUPV3_I2C_S2_CBCR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_S2_CBCR_ADDR, HWIO_GCC_QUPV3_I2C_S2_CBCR_RMSK) +#define HWIO_GCC_QUPV3_I2C_S2_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_S2_CBCR_ADDR, m) +#define HWIO_GCC_QUPV3_I2C_S2_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_I2C_S2_CBCR_ADDR,v) +#define HWIO_GCC_QUPV3_I2C_S2_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_I2C_S2_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_I2C_S2_CBCR_IN) +#define HWIO_GCC_QUPV3_I2C_S2_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_I2C_S2_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_I2C_S2_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QUPV3_I2C_S2_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QUPV3_I2C_S2_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QUPV3_I2C_S2_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QUPV3_I2C_S2_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QUPV3_I2C_S2_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QUPV3_I2C_S2_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QUPV3_I2C_S2_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QUPV3_I2C_S2_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S2_CBCR_CLK_ARES_RESET_FVAL 0x1 + +#define HWIO_GCC_QUPV3_I2C_S2_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00007040) +#define HWIO_GCC_QUPV3_I2C_S2_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00007040) +#define HWIO_GCC_QUPV3_I2C_S2_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00007040) +#define HWIO_GCC_QUPV3_I2C_S2_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_QUPV3_I2C_S2_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_I2C_S2_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_S2_CMD_RCGR_ADDR, HWIO_GCC_QUPV3_I2C_S2_CMD_RCGR_RMSK) +#define HWIO_GCC_QUPV3_I2C_S2_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_S2_CMD_RCGR_ADDR, m) +#define HWIO_GCC_QUPV3_I2C_S2_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_I2C_S2_CMD_RCGR_ADDR,v) +#define HWIO_GCC_QUPV3_I2C_S2_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_I2C_S2_CMD_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_I2C_S2_CMD_RCGR_IN) +#define HWIO_GCC_QUPV3_I2C_S2_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_I2C_S2_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_I2C_S2_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_QUPV3_I2C_S2_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_QUPV3_I2C_S2_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_QUPV3_I2C_S2_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_QUPV3_I2C_S2_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S2_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_S2_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_QUPV3_I2C_S2_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_QUPV3_I2C_S2_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S2_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00007044) +#define HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00007044) +#define HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00007044) +#define HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_ADDR, HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_RMSK) +#define HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_ADDR, m) +#define HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_ADDR,v) +#define HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_IN) +#define HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_I2C_S2_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_I2C_S3_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00007058) +#define HWIO_GCC_QUPV3_I2C_S3_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00007058) +#define HWIO_GCC_QUPV3_I2C_S3_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00007058) +#define HWIO_GCC_QUPV3_I2C_S3_CBCR_RMSK 0x81c00004 +#define HWIO_GCC_QUPV3_I2C_S3_CBCR_ATTR 0x3 +#define HWIO_GCC_QUPV3_I2C_S3_CBCR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_S3_CBCR_ADDR, HWIO_GCC_QUPV3_I2C_S3_CBCR_RMSK) +#define HWIO_GCC_QUPV3_I2C_S3_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_S3_CBCR_ADDR, m) +#define HWIO_GCC_QUPV3_I2C_S3_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_I2C_S3_CBCR_ADDR,v) +#define HWIO_GCC_QUPV3_I2C_S3_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_I2C_S3_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_I2C_S3_CBCR_IN) +#define HWIO_GCC_QUPV3_I2C_S3_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_I2C_S3_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_I2C_S3_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QUPV3_I2C_S3_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QUPV3_I2C_S3_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QUPV3_I2C_S3_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QUPV3_I2C_S3_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QUPV3_I2C_S3_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QUPV3_I2C_S3_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QUPV3_I2C_S3_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QUPV3_I2C_S3_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S3_CBCR_CLK_ARES_RESET_FVAL 0x1 + +#define HWIO_GCC_QUPV3_I2C_S3_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000705c) +#define HWIO_GCC_QUPV3_I2C_S3_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000705c) +#define HWIO_GCC_QUPV3_I2C_S3_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000705c) +#define HWIO_GCC_QUPV3_I2C_S3_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_QUPV3_I2C_S3_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_I2C_S3_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_S3_CMD_RCGR_ADDR, HWIO_GCC_QUPV3_I2C_S3_CMD_RCGR_RMSK) +#define HWIO_GCC_QUPV3_I2C_S3_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_S3_CMD_RCGR_ADDR, m) +#define HWIO_GCC_QUPV3_I2C_S3_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_I2C_S3_CMD_RCGR_ADDR,v) +#define HWIO_GCC_QUPV3_I2C_S3_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_I2C_S3_CMD_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_I2C_S3_CMD_RCGR_IN) +#define HWIO_GCC_QUPV3_I2C_S3_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_I2C_S3_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_I2C_S3_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_QUPV3_I2C_S3_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_QUPV3_I2C_S3_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_QUPV3_I2C_S3_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_QUPV3_I2C_S3_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S3_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_S3_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_QUPV3_I2C_S3_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_QUPV3_I2C_S3_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S3_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00007060) +#define HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00007060) +#define HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00007060) +#define HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_ADDR, HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_RMSK) +#define HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_ADDR, m) +#define HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_ADDR,v) +#define HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_IN) +#define HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_I2C_S3_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_I2C_S4_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00007074) +#define HWIO_GCC_QUPV3_I2C_S4_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00007074) +#define HWIO_GCC_QUPV3_I2C_S4_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00007074) +#define HWIO_GCC_QUPV3_I2C_S4_CBCR_RMSK 0x81c00004 +#define HWIO_GCC_QUPV3_I2C_S4_CBCR_ATTR 0x3 +#define HWIO_GCC_QUPV3_I2C_S4_CBCR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_S4_CBCR_ADDR, HWIO_GCC_QUPV3_I2C_S4_CBCR_RMSK) +#define HWIO_GCC_QUPV3_I2C_S4_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_S4_CBCR_ADDR, m) +#define HWIO_GCC_QUPV3_I2C_S4_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_I2C_S4_CBCR_ADDR,v) +#define HWIO_GCC_QUPV3_I2C_S4_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_I2C_S4_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_I2C_S4_CBCR_IN) +#define HWIO_GCC_QUPV3_I2C_S4_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_I2C_S4_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_I2C_S4_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QUPV3_I2C_S4_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QUPV3_I2C_S4_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QUPV3_I2C_S4_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QUPV3_I2C_S4_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QUPV3_I2C_S4_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QUPV3_I2C_S4_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QUPV3_I2C_S4_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QUPV3_I2C_S4_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S4_CBCR_CLK_ARES_RESET_FVAL 0x1 + +#define HWIO_GCC_QUPV3_I2C_S4_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00007078) +#define HWIO_GCC_QUPV3_I2C_S4_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00007078) +#define HWIO_GCC_QUPV3_I2C_S4_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00007078) +#define HWIO_GCC_QUPV3_I2C_S4_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_QUPV3_I2C_S4_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_I2C_S4_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_S4_CMD_RCGR_ADDR, HWIO_GCC_QUPV3_I2C_S4_CMD_RCGR_RMSK) +#define HWIO_GCC_QUPV3_I2C_S4_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_S4_CMD_RCGR_ADDR, m) +#define HWIO_GCC_QUPV3_I2C_S4_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_I2C_S4_CMD_RCGR_ADDR,v) +#define HWIO_GCC_QUPV3_I2C_S4_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_I2C_S4_CMD_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_I2C_S4_CMD_RCGR_IN) +#define HWIO_GCC_QUPV3_I2C_S4_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_I2C_S4_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_I2C_S4_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_QUPV3_I2C_S4_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_QUPV3_I2C_S4_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_QUPV3_I2C_S4_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_QUPV3_I2C_S4_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S4_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_S4_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_QUPV3_I2C_S4_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_QUPV3_I2C_S4_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S4_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000707c) +#define HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000707c) +#define HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000707c) +#define HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_ADDR, HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_RMSK) +#define HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_ADDR, m) +#define HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_ADDR,v) +#define HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_IN) +#define HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_I2C_S4_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_I2C_S5_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00007090) +#define HWIO_GCC_QUPV3_I2C_S5_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00007090) +#define HWIO_GCC_QUPV3_I2C_S5_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00007090) +#define HWIO_GCC_QUPV3_I2C_S5_CBCR_RMSK 0x81c00004 +#define HWIO_GCC_QUPV3_I2C_S5_CBCR_ATTR 0x3 +#define HWIO_GCC_QUPV3_I2C_S5_CBCR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_S5_CBCR_ADDR, HWIO_GCC_QUPV3_I2C_S5_CBCR_RMSK) +#define HWIO_GCC_QUPV3_I2C_S5_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_S5_CBCR_ADDR, m) +#define HWIO_GCC_QUPV3_I2C_S5_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_I2C_S5_CBCR_ADDR,v) +#define HWIO_GCC_QUPV3_I2C_S5_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_I2C_S5_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_I2C_S5_CBCR_IN) +#define HWIO_GCC_QUPV3_I2C_S5_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_I2C_S5_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_I2C_S5_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QUPV3_I2C_S5_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QUPV3_I2C_S5_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QUPV3_I2C_S5_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QUPV3_I2C_S5_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QUPV3_I2C_S5_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QUPV3_I2C_S5_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QUPV3_I2C_S5_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QUPV3_I2C_S5_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S5_CBCR_CLK_ARES_RESET_FVAL 0x1 + +#define HWIO_GCC_QUPV3_I2C_S5_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00007094) +#define HWIO_GCC_QUPV3_I2C_S5_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00007094) +#define HWIO_GCC_QUPV3_I2C_S5_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00007094) +#define HWIO_GCC_QUPV3_I2C_S5_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_QUPV3_I2C_S5_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_I2C_S5_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_S5_CMD_RCGR_ADDR, HWIO_GCC_QUPV3_I2C_S5_CMD_RCGR_RMSK) +#define HWIO_GCC_QUPV3_I2C_S5_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_S5_CMD_RCGR_ADDR, m) +#define HWIO_GCC_QUPV3_I2C_S5_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_I2C_S5_CMD_RCGR_ADDR,v) +#define HWIO_GCC_QUPV3_I2C_S5_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_I2C_S5_CMD_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_I2C_S5_CMD_RCGR_IN) +#define HWIO_GCC_QUPV3_I2C_S5_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_I2C_S5_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_I2C_S5_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_QUPV3_I2C_S5_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_QUPV3_I2C_S5_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_QUPV3_I2C_S5_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_QUPV3_I2C_S5_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S5_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_S5_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_QUPV3_I2C_S5_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_QUPV3_I2C_S5_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S5_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00007098) +#define HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00007098) +#define HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00007098) +#define HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_ADDR, HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_RMSK) +#define HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_ADDR, m) +#define HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_ADDR,v) +#define HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_IN) +#define HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_I2C_S5_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_I2C_S6_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000070ac) +#define HWIO_GCC_QUPV3_I2C_S6_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000070ac) +#define HWIO_GCC_QUPV3_I2C_S6_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000070ac) +#define HWIO_GCC_QUPV3_I2C_S6_CBCR_RMSK 0x81c00004 +#define HWIO_GCC_QUPV3_I2C_S6_CBCR_ATTR 0x3 +#define HWIO_GCC_QUPV3_I2C_S6_CBCR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_S6_CBCR_ADDR, HWIO_GCC_QUPV3_I2C_S6_CBCR_RMSK) +#define HWIO_GCC_QUPV3_I2C_S6_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_S6_CBCR_ADDR, m) +#define HWIO_GCC_QUPV3_I2C_S6_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_I2C_S6_CBCR_ADDR,v) +#define HWIO_GCC_QUPV3_I2C_S6_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_I2C_S6_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_I2C_S6_CBCR_IN) +#define HWIO_GCC_QUPV3_I2C_S6_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_I2C_S6_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_I2C_S6_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QUPV3_I2C_S6_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QUPV3_I2C_S6_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QUPV3_I2C_S6_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QUPV3_I2C_S6_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QUPV3_I2C_S6_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QUPV3_I2C_S6_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QUPV3_I2C_S6_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QUPV3_I2C_S6_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S6_CBCR_CLK_ARES_RESET_FVAL 0x1 + +#define HWIO_GCC_QUPV3_I2C_S6_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000070b0) +#define HWIO_GCC_QUPV3_I2C_S6_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000070b0) +#define HWIO_GCC_QUPV3_I2C_S6_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000070b0) +#define HWIO_GCC_QUPV3_I2C_S6_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_QUPV3_I2C_S6_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_I2C_S6_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_S6_CMD_RCGR_ADDR, HWIO_GCC_QUPV3_I2C_S6_CMD_RCGR_RMSK) +#define HWIO_GCC_QUPV3_I2C_S6_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_S6_CMD_RCGR_ADDR, m) +#define HWIO_GCC_QUPV3_I2C_S6_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_I2C_S6_CMD_RCGR_ADDR,v) +#define HWIO_GCC_QUPV3_I2C_S6_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_I2C_S6_CMD_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_I2C_S6_CMD_RCGR_IN) +#define HWIO_GCC_QUPV3_I2C_S6_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_I2C_S6_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_I2C_S6_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_QUPV3_I2C_S6_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_QUPV3_I2C_S6_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_QUPV3_I2C_S6_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_QUPV3_I2C_S6_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S6_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_S6_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_QUPV3_I2C_S6_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_QUPV3_I2C_S6_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S6_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000070b4) +#define HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000070b4) +#define HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000070b4) +#define HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_ADDR, HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_RMSK) +#define HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_ADDR, m) +#define HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_ADDR,v) +#define HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_IN) +#define HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_I2C_S6_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_I2C_S7_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000070c8) +#define HWIO_GCC_QUPV3_I2C_S7_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000070c8) +#define HWIO_GCC_QUPV3_I2C_S7_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000070c8) +#define HWIO_GCC_QUPV3_I2C_S7_CBCR_RMSK 0x81c00004 +#define HWIO_GCC_QUPV3_I2C_S7_CBCR_ATTR 0x3 +#define HWIO_GCC_QUPV3_I2C_S7_CBCR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_S7_CBCR_ADDR, HWIO_GCC_QUPV3_I2C_S7_CBCR_RMSK) +#define HWIO_GCC_QUPV3_I2C_S7_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_S7_CBCR_ADDR, m) +#define HWIO_GCC_QUPV3_I2C_S7_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_I2C_S7_CBCR_ADDR,v) +#define HWIO_GCC_QUPV3_I2C_S7_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_I2C_S7_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_I2C_S7_CBCR_IN) +#define HWIO_GCC_QUPV3_I2C_S7_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_I2C_S7_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_I2C_S7_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QUPV3_I2C_S7_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QUPV3_I2C_S7_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QUPV3_I2C_S7_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QUPV3_I2C_S7_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QUPV3_I2C_S7_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QUPV3_I2C_S7_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QUPV3_I2C_S7_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QUPV3_I2C_S7_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S7_CBCR_CLK_ARES_RESET_FVAL 0x1 + +#define HWIO_GCC_QUPV3_I2C_S7_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000070cc) +#define HWIO_GCC_QUPV3_I2C_S7_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000070cc) +#define HWIO_GCC_QUPV3_I2C_S7_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000070cc) +#define HWIO_GCC_QUPV3_I2C_S7_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_QUPV3_I2C_S7_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_I2C_S7_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_S7_CMD_RCGR_ADDR, HWIO_GCC_QUPV3_I2C_S7_CMD_RCGR_RMSK) +#define HWIO_GCC_QUPV3_I2C_S7_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_S7_CMD_RCGR_ADDR, m) +#define HWIO_GCC_QUPV3_I2C_S7_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_I2C_S7_CMD_RCGR_ADDR,v) +#define HWIO_GCC_QUPV3_I2C_S7_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_I2C_S7_CMD_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_I2C_S7_CMD_RCGR_IN) +#define HWIO_GCC_QUPV3_I2C_S7_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_I2C_S7_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_I2C_S7_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_QUPV3_I2C_S7_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_QUPV3_I2C_S7_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_QUPV3_I2C_S7_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_QUPV3_I2C_S7_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S7_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_S7_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_QUPV3_I2C_S7_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_QUPV3_I2C_S7_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S7_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000070d0) +#define HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000070d0) +#define HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000070d0) +#define HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_ADDR, HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_RMSK) +#define HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_ADDR, m) +#define HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_ADDR,v) +#define HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_IN) +#define HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_I2C_S7_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_I2C_S8_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000070e4) +#define HWIO_GCC_QUPV3_I2C_S8_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000070e4) +#define HWIO_GCC_QUPV3_I2C_S8_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000070e4) +#define HWIO_GCC_QUPV3_I2C_S8_CBCR_RMSK 0x81c00004 +#define HWIO_GCC_QUPV3_I2C_S8_CBCR_ATTR 0x3 +#define HWIO_GCC_QUPV3_I2C_S8_CBCR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_S8_CBCR_ADDR, HWIO_GCC_QUPV3_I2C_S8_CBCR_RMSK) +#define HWIO_GCC_QUPV3_I2C_S8_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_S8_CBCR_ADDR, m) +#define HWIO_GCC_QUPV3_I2C_S8_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_I2C_S8_CBCR_ADDR,v) +#define HWIO_GCC_QUPV3_I2C_S8_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_I2C_S8_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_I2C_S8_CBCR_IN) +#define HWIO_GCC_QUPV3_I2C_S8_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_I2C_S8_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_I2C_S8_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QUPV3_I2C_S8_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QUPV3_I2C_S8_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QUPV3_I2C_S8_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QUPV3_I2C_S8_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QUPV3_I2C_S8_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QUPV3_I2C_S8_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QUPV3_I2C_S8_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QUPV3_I2C_S8_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S8_CBCR_CLK_ARES_RESET_FVAL 0x1 + +#define HWIO_GCC_QUPV3_I2C_S8_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000070e8) +#define HWIO_GCC_QUPV3_I2C_S8_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000070e8) +#define HWIO_GCC_QUPV3_I2C_S8_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000070e8) +#define HWIO_GCC_QUPV3_I2C_S8_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_QUPV3_I2C_S8_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_I2C_S8_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_S8_CMD_RCGR_ADDR, HWIO_GCC_QUPV3_I2C_S8_CMD_RCGR_RMSK) +#define HWIO_GCC_QUPV3_I2C_S8_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_S8_CMD_RCGR_ADDR, m) +#define HWIO_GCC_QUPV3_I2C_S8_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_I2C_S8_CMD_RCGR_ADDR,v) +#define HWIO_GCC_QUPV3_I2C_S8_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_I2C_S8_CMD_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_I2C_S8_CMD_RCGR_IN) +#define HWIO_GCC_QUPV3_I2C_S8_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_I2C_S8_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_I2C_S8_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_QUPV3_I2C_S8_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_QUPV3_I2C_S8_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_QUPV3_I2C_S8_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_QUPV3_I2C_S8_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S8_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_S8_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_QUPV3_I2C_S8_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_QUPV3_I2C_S8_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S8_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000070ec) +#define HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000070ec) +#define HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000070ec) +#define HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_ADDR, HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_RMSK) +#define HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_ADDR, m) +#define HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_ADDR,v) +#define HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_IN) +#define HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_I2C_S8_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_I2C_S9_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00007100) +#define HWIO_GCC_QUPV3_I2C_S9_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00007100) +#define HWIO_GCC_QUPV3_I2C_S9_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00007100) +#define HWIO_GCC_QUPV3_I2C_S9_CBCR_RMSK 0x81c00004 +#define HWIO_GCC_QUPV3_I2C_S9_CBCR_ATTR 0x3 +#define HWIO_GCC_QUPV3_I2C_S9_CBCR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_S9_CBCR_ADDR, HWIO_GCC_QUPV3_I2C_S9_CBCR_RMSK) +#define HWIO_GCC_QUPV3_I2C_S9_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_S9_CBCR_ADDR, m) +#define HWIO_GCC_QUPV3_I2C_S9_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_I2C_S9_CBCR_ADDR,v) +#define HWIO_GCC_QUPV3_I2C_S9_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_I2C_S9_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_I2C_S9_CBCR_IN) +#define HWIO_GCC_QUPV3_I2C_S9_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_I2C_S9_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_I2C_S9_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QUPV3_I2C_S9_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QUPV3_I2C_S9_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QUPV3_I2C_S9_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QUPV3_I2C_S9_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QUPV3_I2C_S9_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QUPV3_I2C_S9_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QUPV3_I2C_S9_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QUPV3_I2C_S9_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S9_CBCR_CLK_ARES_RESET_FVAL 0x1 + +#define HWIO_GCC_QUPV3_I2C_S9_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00007104) +#define HWIO_GCC_QUPV3_I2C_S9_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00007104) +#define HWIO_GCC_QUPV3_I2C_S9_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00007104) +#define HWIO_GCC_QUPV3_I2C_S9_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_QUPV3_I2C_S9_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_I2C_S9_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_S9_CMD_RCGR_ADDR, HWIO_GCC_QUPV3_I2C_S9_CMD_RCGR_RMSK) +#define HWIO_GCC_QUPV3_I2C_S9_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_S9_CMD_RCGR_ADDR, m) +#define HWIO_GCC_QUPV3_I2C_S9_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_I2C_S9_CMD_RCGR_ADDR,v) +#define HWIO_GCC_QUPV3_I2C_S9_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_I2C_S9_CMD_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_I2C_S9_CMD_RCGR_IN) +#define HWIO_GCC_QUPV3_I2C_S9_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_I2C_S9_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_I2C_S9_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_QUPV3_I2C_S9_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_QUPV3_I2C_S9_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_QUPV3_I2C_S9_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_QUPV3_I2C_S9_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S9_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_S9_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_QUPV3_I2C_S9_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_QUPV3_I2C_S9_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S9_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00007108) +#define HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00007108) +#define HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00007108) +#define HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_ADDR, HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_RMSK) +#define HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_ADDR, m) +#define HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_ADDR,v) +#define HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_IN) +#define HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_I2C_S9_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAPPER_1_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008000) +#define HWIO_GCC_QUPV3_WRAPPER_1_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008000) +#define HWIO_GCC_QUPV3_WRAPPER_1_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008000) +#define HWIO_GCC_QUPV3_WRAPPER_1_BCR_RMSK 0x1 +#define HWIO_GCC_QUPV3_WRAPPER_1_BCR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAPPER_1_BCR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAPPER_1_BCR_ADDR, HWIO_GCC_QUPV3_WRAPPER_1_BCR_RMSK) +#define HWIO_GCC_QUPV3_WRAPPER_1_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAPPER_1_BCR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAPPER_1_BCR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAPPER_1_BCR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAPPER_1_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAPPER_1_BCR_ADDR,m,v,HWIO_GCC_QUPV3_WRAPPER_1_BCR_IN) +#define HWIO_GCC_QUPV3_WRAPPER_1_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_QUPV3_WRAPPER_1_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAPPER_1_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAPPER_1_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP_1_M_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001327c) +#define HWIO_GCC_QUPV3_WRAP_1_M_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001327c) +#define HWIO_GCC_QUPV3_WRAP_1_M_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001327c) +#define HWIO_GCC_QUPV3_WRAP_1_M_AHB_CBCR_RMSK 0x81d0000e +#define HWIO_GCC_QUPV3_WRAP_1_M_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP_1_M_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP_1_M_AHB_CBCR_ADDR, HWIO_GCC_QUPV3_WRAP_1_M_AHB_CBCR_RMSK) +#define HWIO_GCC_QUPV3_WRAP_1_M_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP_1_M_AHB_CBCR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP_1_M_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP_1_M_AHB_CBCR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP_1_M_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP_1_M_AHB_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP_1_M_AHB_CBCR_IN) +#define HWIO_GCC_QUPV3_WRAP_1_M_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_WRAP_1_M_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_WRAP_1_M_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QUPV3_WRAP_1_M_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP_1_M_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QUPV3_WRAP_1_M_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QUPV3_WRAP_1_M_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QUPV3_WRAP_1_M_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QUPV3_WRAP_1_M_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_QUPV3_WRAP_1_M_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_QUPV3_WRAP_1_M_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_QUPV3_WRAP_1_M_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_QUPV3_WRAP_1_M_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QUPV3_WRAP_1_M_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QUPV3_WRAP_1_M_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP_1_M_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP_1_M_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_QUPV3_WRAP_1_M_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_QUPV3_WRAP_1_M_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP_1_M_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP_1_S_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00013280) +#define HWIO_GCC_QUPV3_WRAP_1_S_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00013280) +#define HWIO_GCC_QUPV3_WRAP_1_S_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00013280) +#define HWIO_GCC_QUPV3_WRAP_1_S_AHB_CBCR_RMSK 0x81d0000e +#define HWIO_GCC_QUPV3_WRAP_1_S_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP_1_S_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP_1_S_AHB_CBCR_ADDR, HWIO_GCC_QUPV3_WRAP_1_S_AHB_CBCR_RMSK) +#define HWIO_GCC_QUPV3_WRAP_1_S_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP_1_S_AHB_CBCR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP_1_S_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP_1_S_AHB_CBCR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP_1_S_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP_1_S_AHB_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP_1_S_AHB_CBCR_IN) +#define HWIO_GCC_QUPV3_WRAP_1_S_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_WRAP_1_S_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_WRAP_1_S_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QUPV3_WRAP_1_S_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP_1_S_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QUPV3_WRAP_1_S_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QUPV3_WRAP_1_S_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QUPV3_WRAP_1_S_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QUPV3_WRAP_1_S_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_QUPV3_WRAP_1_S_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_QUPV3_WRAP_1_S_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_QUPV3_WRAP_1_S_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_QUPV3_WRAP_1_S_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QUPV3_WRAP_1_S_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QUPV3_WRAP_1_S_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP_1_S_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP_1_S_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_QUPV3_WRAP_1_S_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_QUPV3_WRAP_1_S_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP_1_S_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00013284) +#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00013284) +#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00013284) +#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_RMSK 0x81d07004 +#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_ADDR, HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_IN) +#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_CLK_ARES_RESET_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00013288) +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00013288) +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00013288) +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_RMSK 0xf1ffffe +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_ADDR, HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_IN) +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xf000000 +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_PWR_FSM_CLK_SEL_BMSK 0x100000 +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_PWR_FSM_CLK_SEL_SHFT 0x14 +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xf0000 +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_CORE_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP1_CORE_CFG_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001328c) +#define HWIO_GCC_QUPV3_WRAP1_CORE_CFG_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001328c) +#define HWIO_GCC_QUPV3_WRAP1_CORE_CFG_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001328c) +#define HWIO_GCC_QUPV3_WRAP1_CORE_CFG_SREGR_RMSK 0xffffffff +#define HWIO_GCC_QUPV3_WRAP1_CORE_CFG_SREGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_CORE_CFG_SREGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_CORE_CFG_SREGR_ADDR, HWIO_GCC_QUPV3_WRAP1_CORE_CFG_SREGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_CORE_CFG_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_CORE_CFG_SREGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_CORE_CFG_SREGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_CORE_CFG_SREGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_CORE_CFG_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_CORE_CFG_SREGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_CORE_CFG_SREGR_IN) +#define HWIO_GCC_QUPV3_WRAP1_CORE_CFG_SREGR_MEM_CORE_OFF_TIMER_BMSK 0xfc000000 +#define HWIO_GCC_QUPV3_WRAP1_CORE_CFG_SREGR_MEM_CORE_OFF_TIMER_SHFT 0x1a +#define HWIO_GCC_QUPV3_WRAP1_CORE_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_BMSK 0x2000000 +#define HWIO_GCC_QUPV3_WRAP1_CORE_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_SHFT 0x19 +#define HWIO_GCC_QUPV3_WRAP1_CORE_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_BMSK 0x1000000 +#define HWIO_GCC_QUPV3_WRAP1_CORE_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP1_CORE_CFG_SREGR_MEM_PERIPH_ON_STATUS_BMSK 0x800000 +#define HWIO_GCC_QUPV3_WRAP1_CORE_CFG_SREGR_MEM_PERIPH_ON_STATUS_SHFT 0x17 +#define HWIO_GCC_QUPV3_WRAP1_CORE_CFG_SREGR_MEM_CORE_ON_STATUS_BMSK 0x400000 +#define HWIO_GCC_QUPV3_WRAP1_CORE_CFG_SREGR_MEM_CORE_ON_STATUS_SHFT 0x16 +#define HWIO_GCC_QUPV3_WRAP1_CORE_CFG_SREGR_MEM_CPH_TIMER_BMSK 0x3f0000 +#define HWIO_GCC_QUPV3_WRAP1_CORE_CFG_SREGR_MEM_CPH_TIMER_SHFT 0x10 +#define HWIO_GCC_QUPV3_WRAP1_CORE_CFG_SREGR_SLEEP_TIMER_BMSK 0xff00 +#define HWIO_GCC_QUPV3_WRAP1_CORE_CFG_SREGR_SLEEP_TIMER_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_CORE_CFG_SREGR_WAKEUP_TIMER_BMSK 0xff +#define HWIO_GCC_QUPV3_WRAP1_CORE_CFG_SREGR_WAKEUP_TIMER_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_CORE_DIV_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00013290) +#define HWIO_GCC_QUPV3_WRAP1_CORE_DIV_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00013290) +#define HWIO_GCC_QUPV3_WRAP1_CORE_DIV_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00013290) +#define HWIO_GCC_QUPV3_WRAP1_CORE_DIV_CDIVR_RMSK 0xf +#define HWIO_GCC_QUPV3_WRAP1_CORE_DIV_CDIVR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_CORE_DIV_CDIVR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_CORE_DIV_CDIVR_ADDR, HWIO_GCC_QUPV3_WRAP1_CORE_DIV_CDIVR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_CORE_DIV_CDIVR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_CORE_DIV_CDIVR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_CORE_DIV_CDIVR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_CORE_DIV_CDIVR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_CORE_DIV_CDIVR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_CORE_DIV_CDIVR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_CORE_DIV_CDIVR_IN) +#define HWIO_GCC_QUPV3_WRAP1_CORE_DIV_CDIVR_CLK_DIV_BMSK 0xf +#define HWIO_GCC_QUPV3_WRAP1_CORE_DIV_CDIVR_CLK_DIV_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00013294) +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00013294) +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00013294) +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_RMSK 0x81d07004 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_ADDR, HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_IN) +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_CLK_ARES_RESET_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00013298) +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00013298) +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00013298) +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_RMSK 0xf1ffffe +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_ADDR, HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_IN) +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xf000000 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_PWR_FSM_CLK_SEL_BMSK 0x100000 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_PWR_FSM_CLK_SEL_SHFT 0x14 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xf0000 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001329c) +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001329c) +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001329c) +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_SREGR_RMSK 0xffffffff +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_SREGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_SREGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_SREGR_ADDR, HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_SREGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_SREGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_SREGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_SREGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_SREGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_SREGR_IN) +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_SREGR_MEM_CORE_OFF_TIMER_BMSK 0xfc000000 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_SREGR_MEM_CORE_OFF_TIMER_SHFT 0x1a +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_BMSK 0x2000000 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_SHFT 0x19 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_BMSK 0x1000000 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_SREGR_MEM_PERIPH_ON_STATUS_BMSK 0x800000 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_SREGR_MEM_PERIPH_ON_STATUS_SHFT 0x17 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_SREGR_MEM_CORE_ON_STATUS_BMSK 0x400000 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_SREGR_MEM_CORE_ON_STATUS_SHFT 0x16 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_SREGR_MEM_CPH_TIMER_BMSK 0x3f0000 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_SREGR_MEM_CPH_TIMER_SHFT 0x10 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_SREGR_SLEEP_TIMER_BMSK 0xff00 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_SREGR_SLEEP_TIMER_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_SREGR_WAKEUP_TIMER_BMSK 0xff +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_SREGR_WAKEUP_TIMER_SHFT 0x0 + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000132bc) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000132bc) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000132bc) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000132c0) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000132c0) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000132c0) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000132c4) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000132c4) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000132c4) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000132c8) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000132c8) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000132c8) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000132cc) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000132cc) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000132cc) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000132d0) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000132d0) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000132d0) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000132d4) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000132d4) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000132d4) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000132d8) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000132d8) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000132d8) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000132dc) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000132dc) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000132dc) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000132e0) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000132e0) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000132e0) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000132e4) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000132e4) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000132e4) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000132e8) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000132e8) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000132e8) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000132ec) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000132ec) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000132ec) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000132f0) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000132f0) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000132f0) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000132f4) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000132f4) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000132f4) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000132f8) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000132f8) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000132f8) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000132a0) +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000132a0) +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000132a0) +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR_ADDR, HWIO_GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR_IN) +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000132a4) +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000132a4) +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000132a4) +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_ADDR, HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_IN) +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_S0_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008004) +#define HWIO_GCC_QUPV3_WRAP1_S0_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008004) +#define HWIO_GCC_QUPV3_WRAP1_S0_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008004) +#define HWIO_GCC_QUPV3_WRAP1_S0_CBCR_RMSK 0x81c07004 +#define HWIO_GCC_QUPV3_WRAP1_S0_CBCR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S0_CBCR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S0_CBCR_ADDR, HWIO_GCC_QUPV3_WRAP1_S0_CBCR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S0_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S0_CBCR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S0_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S0_CBCR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S0_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S0_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S0_CBCR_IN) +#define HWIO_GCC_QUPV3_WRAP1_S0_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_WRAP1_S0_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_WRAP1_S0_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QUPV3_WRAP1_S0_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP1_S0_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QUPV3_WRAP1_S0_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QUPV3_WRAP1_S0_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QUPV3_WRAP1_S0_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QUPV3_WRAP1_S0_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_QUPV3_WRAP1_S0_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_QUPV3_WRAP1_S0_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S0_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S0_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_QUPV3_WRAP1_S0_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_QUPV3_WRAP1_S0_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S0_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S0_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_QUPV3_WRAP1_S0_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_S0_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S0_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S0_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QUPV3_WRAP1_S0_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S0_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S0_CBCR_CLK_ARES_RESET_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008008) +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008008) +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008008) +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_RMSK 0xf1ffffe +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S0_SREGR_ADDR, HWIO_GCC_QUPV3_WRAP1_S0_SREGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S0_SREGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S0_SREGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S0_SREGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S0_SREGR_IN) +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xf000000 +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_PWR_FSM_CLK_SEL_BMSK 0x100000 +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_PWR_FSM_CLK_SEL_SHFT 0x14 +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xf0000 +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S0_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000800c) +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000800c) +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000800c) +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_SREGR_RMSK 0xffffffff +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_SREGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_SREGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S0_CFG_SREGR_ADDR, HWIO_GCC_QUPV3_WRAP1_S0_CFG_SREGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S0_CFG_SREGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_SREGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S0_CFG_SREGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S0_CFG_SREGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S0_CFG_SREGR_IN) +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_SREGR_MEM_CORE_OFF_TIMER_BMSK 0xfc000000 +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_SREGR_MEM_CORE_OFF_TIMER_SHFT 0x1a +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_BMSK 0x2000000 +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_SHFT 0x19 +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_BMSK 0x1000000 +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_SREGR_MEM_PERIPH_ON_STATUS_BMSK 0x800000 +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_SREGR_MEM_PERIPH_ON_STATUS_SHFT 0x17 +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_SREGR_MEM_CORE_ON_STATUS_BMSK 0x400000 +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_SREGR_MEM_CORE_ON_STATUS_SHFT 0x16 +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_SREGR_MEM_CPH_TIMER_BMSK 0x3f0000 +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_SREGR_MEM_CPH_TIMER_SHFT 0x10 +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_SREGR_SLEEP_TIMER_BMSK 0xff00 +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_SREGR_SLEEP_TIMER_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_SREGR_WAKEUP_TIMER_BMSK 0xff +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_SREGR_WAKEUP_TIMER_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008024) +#define HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008024) +#define HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008024) +#define HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_RCG_SW_CTRL_BMSK 0x8000 +#define HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_RCG_SW_CTRL_SHFT 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_SW_PERF_STATE_BMSK 0x7800 +#define HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_SW_PERF_STATE_SHFT 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_SW_OVERRIDE_BMSK 0x400 +#define HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_SW_OVERRIDE_SHFT 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK 0x200 +#define HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_DFS_FSM_STATE_BMSK 0x1c0 +#define HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_DFS_FSM_STATE_SHFT 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_HW_CLK_CONTROL_BMSK 0x20 +#define HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_HW_CLK_CONTROL_SHFT 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_CURR_PERF_STATE_BMSK 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_CURR_PERF_STATE_SHFT 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_DFS_EN_BMSK 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_DFS_EN_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_DFS_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_DFS_EN_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000802c) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000802c) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000802c) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008030) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008030) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008030) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008034) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008034) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008034) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008038) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008038) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008038) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000803c) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000803c) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000803c) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008040) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008040) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008040) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008044) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008044) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008044) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008048) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008048) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008048) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000806c) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000806c) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000806c) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008070) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008070) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008070) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008074) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008074) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008074) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008078) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008078) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008078) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000807c) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000807c) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000807c) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008080) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008080) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008080) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008084) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008084) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008084) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008088) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008088) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008088) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000080ac) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000080ac) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000080ac) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000080b0) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000080b0) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000080b0) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000080b4) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000080b4) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000080b4) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000080b8) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000080b8) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000080b8) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000080bc) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000080bc) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000080bc) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000080c0) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000080c0) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000080c0) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000080c4) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000080c4) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000080c4) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000080c8) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000080c8) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000080c8) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000080ec) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000080ec) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000080ec) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000080f0) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000080f0) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000080f0) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000080f4) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000080f4) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000080f4) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000080f8) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000080f8) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000080f8) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000080fc) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000080fc) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000080fc) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008100) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008100) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008100) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008104) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008104) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008104) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008108) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008108) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008108) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008010) +#define HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008010) +#define HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008010) +#define HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_RMSK 0x800000f3 +#define HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_ADDR, HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_IN) +#define HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_DIRTY_D_BMSK 0x80 +#define HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_DIRTY_D_SHFT 0x7 +#define HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_DIRTY_N_BMSK 0x40 +#define HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_DIRTY_N_SHFT 0x6 +#define HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_DIRTY_M_BMSK 0x20 +#define HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_DIRTY_M_SHFT 0x5 +#define HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008014) +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008014) +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008014) +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_RMSK 0x10371f +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_ADDR, HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_IN) +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_S0_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008018) +#define HWIO_GCC_QUPV3_WRAP1_S0_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008018) +#define HWIO_GCC_QUPV3_WRAP1_S0_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008018) +#define HWIO_GCC_QUPV3_WRAP1_S0_M_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_S0_M_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S0_M_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S0_M_ADDR, HWIO_GCC_QUPV3_WRAP1_S0_M_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S0_M_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S0_M_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S0_M_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S0_M_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S0_M_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S0_M_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S0_M_IN) +#define HWIO_GCC_QUPV3_WRAP1_S0_M_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_S0_M_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_S0_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000801c) +#define HWIO_GCC_QUPV3_WRAP1_S0_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000801c) +#define HWIO_GCC_QUPV3_WRAP1_S0_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000801c) +#define HWIO_GCC_QUPV3_WRAP1_S0_N_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_S0_N_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S0_N_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S0_N_ADDR, HWIO_GCC_QUPV3_WRAP1_S0_N_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S0_N_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S0_N_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S0_N_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S0_N_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S0_N_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S0_N_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S0_N_IN) +#define HWIO_GCC_QUPV3_WRAP1_S0_N_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_S0_N_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_S0_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008020) +#define HWIO_GCC_QUPV3_WRAP1_S0_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008020) +#define HWIO_GCC_QUPV3_WRAP1_S0_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008020) +#define HWIO_GCC_QUPV3_WRAP1_S0_D_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_S0_D_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S0_D_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S0_D_ADDR, HWIO_GCC_QUPV3_WRAP1_S0_D_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S0_D_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S0_D_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S0_D_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S0_D_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S0_D_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S0_D_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S0_D_IN) +#define HWIO_GCC_QUPV3_WRAP1_S0_D_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_S0_D_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_S1_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000813c) +#define HWIO_GCC_QUPV3_WRAP1_S1_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000813c) +#define HWIO_GCC_QUPV3_WRAP1_S1_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000813c) +#define HWIO_GCC_QUPV3_WRAP1_S1_CBCR_RMSK 0x81c07004 +#define HWIO_GCC_QUPV3_WRAP1_S1_CBCR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S1_CBCR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S1_CBCR_ADDR, HWIO_GCC_QUPV3_WRAP1_S1_CBCR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S1_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S1_CBCR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S1_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S1_CBCR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S1_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S1_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S1_CBCR_IN) +#define HWIO_GCC_QUPV3_WRAP1_S1_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_WRAP1_S1_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_WRAP1_S1_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QUPV3_WRAP1_S1_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP1_S1_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QUPV3_WRAP1_S1_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QUPV3_WRAP1_S1_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QUPV3_WRAP1_S1_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QUPV3_WRAP1_S1_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_QUPV3_WRAP1_S1_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_QUPV3_WRAP1_S1_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S1_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S1_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_QUPV3_WRAP1_S1_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_QUPV3_WRAP1_S1_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S1_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S1_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_QUPV3_WRAP1_S1_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_S1_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S1_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S1_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QUPV3_WRAP1_S1_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S1_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S1_CBCR_CLK_ARES_RESET_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008140) +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008140) +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008140) +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_RMSK 0xf1ffffe +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S1_SREGR_ADDR, HWIO_GCC_QUPV3_WRAP1_S1_SREGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S1_SREGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S1_SREGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S1_SREGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S1_SREGR_IN) +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xf000000 +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_PWR_FSM_CLK_SEL_BMSK 0x100000 +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_PWR_FSM_CLK_SEL_SHFT 0x14 +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xf0000 +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S1_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008144) +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008144) +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008144) +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_SREGR_RMSK 0xffffffff +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_SREGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_SREGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S1_CFG_SREGR_ADDR, HWIO_GCC_QUPV3_WRAP1_S1_CFG_SREGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S1_CFG_SREGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_SREGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S1_CFG_SREGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S1_CFG_SREGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S1_CFG_SREGR_IN) +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_SREGR_MEM_CORE_OFF_TIMER_BMSK 0xfc000000 +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_SREGR_MEM_CORE_OFF_TIMER_SHFT 0x1a +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_BMSK 0x2000000 +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_SHFT 0x19 +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_BMSK 0x1000000 +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_SREGR_MEM_PERIPH_ON_STATUS_BMSK 0x800000 +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_SREGR_MEM_PERIPH_ON_STATUS_SHFT 0x17 +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_SREGR_MEM_CORE_ON_STATUS_BMSK 0x400000 +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_SREGR_MEM_CORE_ON_STATUS_SHFT 0x16 +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_SREGR_MEM_CPH_TIMER_BMSK 0x3f0000 +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_SREGR_MEM_CPH_TIMER_SHFT 0x10 +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_SREGR_SLEEP_TIMER_BMSK 0xff00 +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_SREGR_SLEEP_TIMER_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_SREGR_WAKEUP_TIMER_BMSK 0xff +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_SREGR_WAKEUP_TIMER_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000815c) +#define HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000815c) +#define HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000815c) +#define HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_RCG_SW_CTRL_BMSK 0x8000 +#define HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_RCG_SW_CTRL_SHFT 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_SW_PERF_STATE_BMSK 0x7800 +#define HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_SW_PERF_STATE_SHFT 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_SW_OVERRIDE_BMSK 0x400 +#define HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_SW_OVERRIDE_SHFT 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK 0x200 +#define HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_DFS_FSM_STATE_BMSK 0x1c0 +#define HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_DFS_FSM_STATE_SHFT 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_HW_CLK_CONTROL_BMSK 0x20 +#define HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_HW_CLK_CONTROL_SHFT 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_CURR_PERF_STATE_BMSK 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_CURR_PERF_STATE_SHFT 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_DFS_EN_BMSK 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_DFS_EN_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_DFS_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_DFS_EN_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008164) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008164) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008164) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008168) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008168) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008168) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000816c) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000816c) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000816c) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008170) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008170) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008170) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008174) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008174) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008174) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008178) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008178) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008178) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000817c) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000817c) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000817c) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008180) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008180) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008180) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000081a4) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000081a4) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000081a4) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000081a8) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000081a8) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000081a8) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000081ac) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000081ac) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000081ac) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000081b0) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000081b0) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000081b0) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000081b4) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000081b4) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000081b4) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000081b8) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000081b8) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000081b8) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000081bc) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000081bc) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000081bc) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000081c0) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000081c0) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000081c0) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000081e4) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000081e4) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000081e4) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000081e8) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000081e8) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000081e8) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000081ec) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000081ec) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000081ec) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000081f0) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000081f0) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000081f0) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000081f4) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000081f4) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000081f4) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000081f8) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000081f8) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000081f8) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000081fc) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000081fc) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000081fc) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008200) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008200) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008200) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008224) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008224) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008224) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008228) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008228) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008228) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000822c) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000822c) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000822c) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008230) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008230) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008230) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008234) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008234) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008234) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008238) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008238) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008238) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000823c) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000823c) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000823c) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008240) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008240) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008240) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008148) +#define HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008148) +#define HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008148) +#define HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_RMSK 0x800000f3 +#define HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_ADDR, HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_IN) +#define HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_DIRTY_D_BMSK 0x80 +#define HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_DIRTY_D_SHFT 0x7 +#define HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_DIRTY_N_BMSK 0x40 +#define HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_DIRTY_N_SHFT 0x6 +#define HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_DIRTY_M_BMSK 0x20 +#define HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_DIRTY_M_SHFT 0x5 +#define HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000814c) +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000814c) +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000814c) +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_RMSK 0x10371f +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_ADDR, HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_IN) +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_S1_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008150) +#define HWIO_GCC_QUPV3_WRAP1_S1_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008150) +#define HWIO_GCC_QUPV3_WRAP1_S1_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008150) +#define HWIO_GCC_QUPV3_WRAP1_S1_M_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_S1_M_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S1_M_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S1_M_ADDR, HWIO_GCC_QUPV3_WRAP1_S1_M_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S1_M_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S1_M_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S1_M_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S1_M_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S1_M_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S1_M_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S1_M_IN) +#define HWIO_GCC_QUPV3_WRAP1_S1_M_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_S1_M_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_S1_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008154) +#define HWIO_GCC_QUPV3_WRAP1_S1_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008154) +#define HWIO_GCC_QUPV3_WRAP1_S1_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008154) +#define HWIO_GCC_QUPV3_WRAP1_S1_N_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_S1_N_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S1_N_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S1_N_ADDR, HWIO_GCC_QUPV3_WRAP1_S1_N_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S1_N_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S1_N_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S1_N_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S1_N_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S1_N_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S1_N_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S1_N_IN) +#define HWIO_GCC_QUPV3_WRAP1_S1_N_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_S1_N_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_S1_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008158) +#define HWIO_GCC_QUPV3_WRAP1_S1_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008158) +#define HWIO_GCC_QUPV3_WRAP1_S1_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008158) +#define HWIO_GCC_QUPV3_WRAP1_S1_D_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_S1_D_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S1_D_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S1_D_ADDR, HWIO_GCC_QUPV3_WRAP1_S1_D_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S1_D_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S1_D_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S1_D_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S1_D_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S1_D_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S1_D_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S1_D_IN) +#define HWIO_GCC_QUPV3_WRAP1_S1_D_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_S1_D_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_S2_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008274) +#define HWIO_GCC_QUPV3_WRAP1_S2_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008274) +#define HWIO_GCC_QUPV3_WRAP1_S2_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008274) +#define HWIO_GCC_QUPV3_WRAP1_S2_CBCR_RMSK 0x81c07004 +#define HWIO_GCC_QUPV3_WRAP1_S2_CBCR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S2_CBCR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S2_CBCR_ADDR, HWIO_GCC_QUPV3_WRAP1_S2_CBCR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S2_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S2_CBCR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S2_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S2_CBCR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S2_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S2_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S2_CBCR_IN) +#define HWIO_GCC_QUPV3_WRAP1_S2_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_WRAP1_S2_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_WRAP1_S2_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QUPV3_WRAP1_S2_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP1_S2_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QUPV3_WRAP1_S2_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QUPV3_WRAP1_S2_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QUPV3_WRAP1_S2_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QUPV3_WRAP1_S2_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_QUPV3_WRAP1_S2_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_QUPV3_WRAP1_S2_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S2_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S2_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_QUPV3_WRAP1_S2_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_QUPV3_WRAP1_S2_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S2_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S2_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_QUPV3_WRAP1_S2_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_S2_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S2_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S2_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QUPV3_WRAP1_S2_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S2_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S2_CBCR_CLK_ARES_RESET_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008278) +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008278) +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008278) +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_RMSK 0xf1ffffe +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S2_SREGR_ADDR, HWIO_GCC_QUPV3_WRAP1_S2_SREGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S2_SREGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S2_SREGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S2_SREGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S2_SREGR_IN) +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xf000000 +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_PWR_FSM_CLK_SEL_BMSK 0x100000 +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_PWR_FSM_CLK_SEL_SHFT 0x14 +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xf0000 +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S2_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000827c) +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000827c) +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000827c) +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_SREGR_RMSK 0xffffffff +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_SREGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_SREGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S2_CFG_SREGR_ADDR, HWIO_GCC_QUPV3_WRAP1_S2_CFG_SREGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S2_CFG_SREGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_SREGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S2_CFG_SREGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S2_CFG_SREGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S2_CFG_SREGR_IN) +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_SREGR_MEM_CORE_OFF_TIMER_BMSK 0xfc000000 +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_SREGR_MEM_CORE_OFF_TIMER_SHFT 0x1a +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_BMSK 0x2000000 +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_SHFT 0x19 +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_BMSK 0x1000000 +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_SREGR_MEM_PERIPH_ON_STATUS_BMSK 0x800000 +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_SREGR_MEM_PERIPH_ON_STATUS_SHFT 0x17 +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_SREGR_MEM_CORE_ON_STATUS_BMSK 0x400000 +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_SREGR_MEM_CORE_ON_STATUS_SHFT 0x16 +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_SREGR_MEM_CPH_TIMER_BMSK 0x3f0000 +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_SREGR_MEM_CPH_TIMER_SHFT 0x10 +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_SREGR_SLEEP_TIMER_BMSK 0xff00 +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_SREGR_SLEEP_TIMER_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_SREGR_WAKEUP_TIMER_BMSK 0xff +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_SREGR_WAKEUP_TIMER_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008294) +#define HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008294) +#define HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008294) +#define HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_RCG_SW_CTRL_BMSK 0x8000 +#define HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_RCG_SW_CTRL_SHFT 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_SW_PERF_STATE_BMSK 0x7800 +#define HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_SW_PERF_STATE_SHFT 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_SW_OVERRIDE_BMSK 0x400 +#define HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_SW_OVERRIDE_SHFT 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK 0x200 +#define HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_DFS_FSM_STATE_BMSK 0x1c0 +#define HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_DFS_FSM_STATE_SHFT 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_HW_CLK_CONTROL_BMSK 0x20 +#define HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_HW_CLK_CONTROL_SHFT 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_CURR_PERF_STATE_BMSK 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_CURR_PERF_STATE_SHFT 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_DFS_EN_BMSK 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_DFS_EN_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_DFS_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_DFS_EN_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000829c) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000829c) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000829c) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000082a0) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000082a0) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000082a0) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000082a4) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000082a4) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000082a4) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000082a8) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000082a8) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000082a8) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000082ac) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000082ac) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000082ac) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000082b0) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000082b0) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000082b0) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000082b4) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000082b4) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000082b4) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000082b8) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000082b8) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000082b8) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000082dc) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000082dc) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000082dc) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000082e0) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000082e0) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000082e0) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000082e4) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000082e4) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000082e4) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000082e8) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000082e8) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000082e8) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000082ec) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000082ec) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000082ec) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000082f0) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000082f0) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000082f0) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000082f4) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000082f4) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000082f4) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000082f8) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000082f8) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000082f8) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000831c) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000831c) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000831c) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008320) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008320) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008320) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008324) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008324) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008324) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008328) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008328) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008328) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000832c) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000832c) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000832c) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008330) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008330) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008330) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008334) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008334) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008334) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008338) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008338) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008338) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000835c) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000835c) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000835c) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008360) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008360) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008360) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008364) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008364) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008364) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008368) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008368) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008368) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000836c) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000836c) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000836c) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008370) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008370) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008370) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008374) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008374) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008374) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008378) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008378) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008378) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008280) +#define HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008280) +#define HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008280) +#define HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_RMSK 0x800000f3 +#define HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_ADDR, HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_IN) +#define HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_DIRTY_D_BMSK 0x80 +#define HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_DIRTY_D_SHFT 0x7 +#define HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_DIRTY_N_BMSK 0x40 +#define HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_DIRTY_N_SHFT 0x6 +#define HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_DIRTY_M_BMSK 0x20 +#define HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_DIRTY_M_SHFT 0x5 +#define HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008284) +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008284) +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008284) +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_RMSK 0x10371f +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_ADDR, HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_IN) +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_S2_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008288) +#define HWIO_GCC_QUPV3_WRAP1_S2_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008288) +#define HWIO_GCC_QUPV3_WRAP1_S2_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008288) +#define HWIO_GCC_QUPV3_WRAP1_S2_M_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_S2_M_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S2_M_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S2_M_ADDR, HWIO_GCC_QUPV3_WRAP1_S2_M_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S2_M_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S2_M_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S2_M_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S2_M_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S2_M_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S2_M_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S2_M_IN) +#define HWIO_GCC_QUPV3_WRAP1_S2_M_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_S2_M_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_S2_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000828c) +#define HWIO_GCC_QUPV3_WRAP1_S2_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000828c) +#define HWIO_GCC_QUPV3_WRAP1_S2_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000828c) +#define HWIO_GCC_QUPV3_WRAP1_S2_N_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_S2_N_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S2_N_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S2_N_ADDR, HWIO_GCC_QUPV3_WRAP1_S2_N_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S2_N_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S2_N_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S2_N_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S2_N_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S2_N_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S2_N_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S2_N_IN) +#define HWIO_GCC_QUPV3_WRAP1_S2_N_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_S2_N_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_S2_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008290) +#define HWIO_GCC_QUPV3_WRAP1_S2_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008290) +#define HWIO_GCC_QUPV3_WRAP1_S2_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008290) +#define HWIO_GCC_QUPV3_WRAP1_S2_D_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_S2_D_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S2_D_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S2_D_ADDR, HWIO_GCC_QUPV3_WRAP1_S2_D_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S2_D_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S2_D_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S2_D_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S2_D_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S2_D_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S2_D_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S2_D_IN) +#define HWIO_GCC_QUPV3_WRAP1_S2_D_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_S2_D_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_S3_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000083ac) +#define HWIO_GCC_QUPV3_WRAP1_S3_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000083ac) +#define HWIO_GCC_QUPV3_WRAP1_S3_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000083ac) +#define HWIO_GCC_QUPV3_WRAP1_S3_CBCR_RMSK 0x81c07004 +#define HWIO_GCC_QUPV3_WRAP1_S3_CBCR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S3_CBCR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S3_CBCR_ADDR, HWIO_GCC_QUPV3_WRAP1_S3_CBCR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S3_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S3_CBCR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S3_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S3_CBCR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S3_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S3_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S3_CBCR_IN) +#define HWIO_GCC_QUPV3_WRAP1_S3_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_WRAP1_S3_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_WRAP1_S3_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QUPV3_WRAP1_S3_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP1_S3_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QUPV3_WRAP1_S3_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QUPV3_WRAP1_S3_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QUPV3_WRAP1_S3_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QUPV3_WRAP1_S3_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_QUPV3_WRAP1_S3_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_QUPV3_WRAP1_S3_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S3_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S3_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_QUPV3_WRAP1_S3_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_QUPV3_WRAP1_S3_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S3_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S3_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_QUPV3_WRAP1_S3_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_S3_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S3_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S3_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QUPV3_WRAP1_S3_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S3_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S3_CBCR_CLK_ARES_RESET_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000083b0) +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000083b0) +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000083b0) +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_RMSK 0xf1ffffe +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S3_SREGR_ADDR, HWIO_GCC_QUPV3_WRAP1_S3_SREGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S3_SREGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S3_SREGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S3_SREGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S3_SREGR_IN) +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xf000000 +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_PWR_FSM_CLK_SEL_BMSK 0x100000 +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_PWR_FSM_CLK_SEL_SHFT 0x14 +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xf0000 +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S3_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000083b4) +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000083b4) +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000083b4) +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_SREGR_RMSK 0xffffffff +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_SREGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_SREGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S3_CFG_SREGR_ADDR, HWIO_GCC_QUPV3_WRAP1_S3_CFG_SREGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S3_CFG_SREGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_SREGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S3_CFG_SREGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S3_CFG_SREGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S3_CFG_SREGR_IN) +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_SREGR_MEM_CORE_OFF_TIMER_BMSK 0xfc000000 +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_SREGR_MEM_CORE_OFF_TIMER_SHFT 0x1a +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_BMSK 0x2000000 +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_SHFT 0x19 +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_BMSK 0x1000000 +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_SREGR_MEM_PERIPH_ON_STATUS_BMSK 0x800000 +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_SREGR_MEM_PERIPH_ON_STATUS_SHFT 0x17 +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_SREGR_MEM_CORE_ON_STATUS_BMSK 0x400000 +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_SREGR_MEM_CORE_ON_STATUS_SHFT 0x16 +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_SREGR_MEM_CPH_TIMER_BMSK 0x3f0000 +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_SREGR_MEM_CPH_TIMER_SHFT 0x10 +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_SREGR_SLEEP_TIMER_BMSK 0xff00 +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_SREGR_SLEEP_TIMER_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_SREGR_WAKEUP_TIMER_BMSK 0xff +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_SREGR_WAKEUP_TIMER_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000083cc) +#define HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000083cc) +#define HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000083cc) +#define HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_RCG_SW_CTRL_BMSK 0x8000 +#define HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_RCG_SW_CTRL_SHFT 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_SW_PERF_STATE_BMSK 0x7800 +#define HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_SW_PERF_STATE_SHFT 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_SW_OVERRIDE_BMSK 0x400 +#define HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_SW_OVERRIDE_SHFT 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK 0x200 +#define HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_DFS_FSM_STATE_BMSK 0x1c0 +#define HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_DFS_FSM_STATE_SHFT 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_HW_CLK_CONTROL_BMSK 0x20 +#define HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_HW_CLK_CONTROL_SHFT 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_CURR_PERF_STATE_BMSK 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_CURR_PERF_STATE_SHFT 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_DFS_EN_BMSK 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_DFS_EN_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_DFS_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_DFS_EN_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000083d4) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000083d4) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000083d4) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000083d8) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000083d8) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000083d8) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000083dc) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000083dc) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000083dc) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000083e0) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000083e0) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000083e0) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000083e4) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000083e4) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000083e4) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000083e8) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000083e8) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000083e8) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000083ec) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000083ec) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000083ec) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000083f0) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000083f0) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000083f0) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008414) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008414) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008414) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008418) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008418) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008418) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000841c) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000841c) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000841c) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008420) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008420) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008420) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008424) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008424) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008424) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008428) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008428) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008428) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000842c) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000842c) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000842c) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008430) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008430) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008430) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008454) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008454) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008454) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008458) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008458) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008458) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000845c) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000845c) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000845c) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008460) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008460) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008460) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008464) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008464) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008464) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008468) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008468) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008468) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000846c) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000846c) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000846c) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008470) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008470) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008470) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008494) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008494) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008494) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008498) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008498) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008498) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000849c) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000849c) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000849c) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000084a0) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000084a0) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000084a0) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000084a4) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000084a4) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000084a4) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000084a8) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000084a8) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000084a8) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000084ac) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000084ac) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000084ac) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000084b0) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000084b0) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000084b0) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000083b8) +#define HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000083b8) +#define HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000083b8) +#define HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_RMSK 0x800000f3 +#define HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_ADDR, HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_IN) +#define HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_DIRTY_D_BMSK 0x80 +#define HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_DIRTY_D_SHFT 0x7 +#define HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_DIRTY_N_BMSK 0x40 +#define HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_DIRTY_N_SHFT 0x6 +#define HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_DIRTY_M_BMSK 0x20 +#define HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_DIRTY_M_SHFT 0x5 +#define HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000083bc) +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000083bc) +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000083bc) +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_RMSK 0x10371f +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_ADDR, HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_IN) +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_S3_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000083c0) +#define HWIO_GCC_QUPV3_WRAP1_S3_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000083c0) +#define HWIO_GCC_QUPV3_WRAP1_S3_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000083c0) +#define HWIO_GCC_QUPV3_WRAP1_S3_M_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_S3_M_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S3_M_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S3_M_ADDR, HWIO_GCC_QUPV3_WRAP1_S3_M_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S3_M_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S3_M_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S3_M_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S3_M_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S3_M_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S3_M_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S3_M_IN) +#define HWIO_GCC_QUPV3_WRAP1_S3_M_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_S3_M_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_S3_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000083c4) +#define HWIO_GCC_QUPV3_WRAP1_S3_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000083c4) +#define HWIO_GCC_QUPV3_WRAP1_S3_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000083c4) +#define HWIO_GCC_QUPV3_WRAP1_S3_N_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_S3_N_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S3_N_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S3_N_ADDR, HWIO_GCC_QUPV3_WRAP1_S3_N_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S3_N_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S3_N_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S3_N_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S3_N_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S3_N_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S3_N_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S3_N_IN) +#define HWIO_GCC_QUPV3_WRAP1_S3_N_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_S3_N_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_S3_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000083c8) +#define HWIO_GCC_QUPV3_WRAP1_S3_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000083c8) +#define HWIO_GCC_QUPV3_WRAP1_S3_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000083c8) +#define HWIO_GCC_QUPV3_WRAP1_S3_D_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_S3_D_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S3_D_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S3_D_ADDR, HWIO_GCC_QUPV3_WRAP1_S3_D_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S3_D_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S3_D_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S3_D_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S3_D_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S3_D_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S3_D_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S3_D_IN) +#define HWIO_GCC_QUPV3_WRAP1_S3_D_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_S3_D_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_S4_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000084e4) +#define HWIO_GCC_QUPV3_WRAP1_S4_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000084e4) +#define HWIO_GCC_QUPV3_WRAP1_S4_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000084e4) +#define HWIO_GCC_QUPV3_WRAP1_S4_CBCR_RMSK 0x81c07004 +#define HWIO_GCC_QUPV3_WRAP1_S4_CBCR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S4_CBCR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S4_CBCR_ADDR, HWIO_GCC_QUPV3_WRAP1_S4_CBCR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S4_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S4_CBCR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S4_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S4_CBCR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S4_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S4_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S4_CBCR_IN) +#define HWIO_GCC_QUPV3_WRAP1_S4_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_WRAP1_S4_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_WRAP1_S4_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QUPV3_WRAP1_S4_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP1_S4_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QUPV3_WRAP1_S4_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QUPV3_WRAP1_S4_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QUPV3_WRAP1_S4_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QUPV3_WRAP1_S4_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_QUPV3_WRAP1_S4_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_QUPV3_WRAP1_S4_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S4_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S4_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_QUPV3_WRAP1_S4_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_QUPV3_WRAP1_S4_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S4_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S4_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_QUPV3_WRAP1_S4_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_S4_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S4_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S4_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QUPV3_WRAP1_S4_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S4_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S4_CBCR_CLK_ARES_RESET_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000084e8) +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000084e8) +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000084e8) +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_RMSK 0xf1ffffe +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S4_SREGR_ADDR, HWIO_GCC_QUPV3_WRAP1_S4_SREGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S4_SREGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S4_SREGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S4_SREGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S4_SREGR_IN) +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xf000000 +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_PWR_FSM_CLK_SEL_BMSK 0x100000 +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_PWR_FSM_CLK_SEL_SHFT 0x14 +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xf0000 +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S4_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000084ec) +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000084ec) +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000084ec) +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_SREGR_RMSK 0xffffffff +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_SREGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_SREGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S4_CFG_SREGR_ADDR, HWIO_GCC_QUPV3_WRAP1_S4_CFG_SREGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S4_CFG_SREGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_SREGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S4_CFG_SREGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S4_CFG_SREGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S4_CFG_SREGR_IN) +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_SREGR_MEM_CORE_OFF_TIMER_BMSK 0xfc000000 +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_SREGR_MEM_CORE_OFF_TIMER_SHFT 0x1a +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_BMSK 0x2000000 +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_SHFT 0x19 +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_BMSK 0x1000000 +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_SREGR_MEM_PERIPH_ON_STATUS_BMSK 0x800000 +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_SREGR_MEM_PERIPH_ON_STATUS_SHFT 0x17 +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_SREGR_MEM_CORE_ON_STATUS_BMSK 0x400000 +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_SREGR_MEM_CORE_ON_STATUS_SHFT 0x16 +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_SREGR_MEM_CPH_TIMER_BMSK 0x3f0000 +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_SREGR_MEM_CPH_TIMER_SHFT 0x10 +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_SREGR_SLEEP_TIMER_BMSK 0xff00 +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_SREGR_SLEEP_TIMER_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_SREGR_WAKEUP_TIMER_BMSK 0xff +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_SREGR_WAKEUP_TIMER_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008504) +#define HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008504) +#define HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008504) +#define HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_RCG_SW_CTRL_BMSK 0x8000 +#define HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_RCG_SW_CTRL_SHFT 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_SW_PERF_STATE_BMSK 0x7800 +#define HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_SW_PERF_STATE_SHFT 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_SW_OVERRIDE_BMSK 0x400 +#define HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_SW_OVERRIDE_SHFT 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK 0x200 +#define HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_DFS_FSM_STATE_BMSK 0x1c0 +#define HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_DFS_FSM_STATE_SHFT 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_HW_CLK_CONTROL_BMSK 0x20 +#define HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_HW_CLK_CONTROL_SHFT 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_CURR_PERF_STATE_BMSK 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_CURR_PERF_STATE_SHFT 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_DFS_EN_BMSK 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_DFS_EN_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_DFS_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_DFS_EN_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000850c) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000850c) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000850c) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008510) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008510) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008510) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008514) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008514) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008514) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008518) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008518) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008518) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000851c) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000851c) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000851c) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008520) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008520) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008520) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008524) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008524) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008524) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008528) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008528) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008528) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000854c) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000854c) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000854c) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008550) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008550) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008550) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008554) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008554) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008554) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008558) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008558) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008558) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000855c) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000855c) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000855c) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008560) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008560) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008560) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008564) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008564) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008564) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008568) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008568) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008568) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000858c) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000858c) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000858c) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008590) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008590) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008590) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008594) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008594) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008594) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008598) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008598) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008598) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000859c) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000859c) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000859c) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000085a0) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000085a0) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000085a0) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000085a4) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000085a4) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000085a4) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000085a8) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000085a8) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000085a8) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000085cc) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000085cc) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000085cc) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000085d0) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000085d0) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000085d0) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000085d4) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000085d4) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000085d4) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000085d8) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000085d8) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000085d8) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000085dc) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000085dc) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000085dc) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000085e0) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000085e0) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000085e0) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000085e4) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000085e4) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000085e4) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000085e8) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000085e8) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000085e8) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000084f0) +#define HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000084f0) +#define HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000084f0) +#define HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_RMSK 0x800000f3 +#define HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_ADDR, HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_IN) +#define HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_DIRTY_D_BMSK 0x80 +#define HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_DIRTY_D_SHFT 0x7 +#define HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_DIRTY_N_BMSK 0x40 +#define HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_DIRTY_N_SHFT 0x6 +#define HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_DIRTY_M_BMSK 0x20 +#define HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_DIRTY_M_SHFT 0x5 +#define HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000084f4) +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000084f4) +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000084f4) +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_RMSK 0x10371f +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_ADDR, HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_IN) +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_S4_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000084f8) +#define HWIO_GCC_QUPV3_WRAP1_S4_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000084f8) +#define HWIO_GCC_QUPV3_WRAP1_S4_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000084f8) +#define HWIO_GCC_QUPV3_WRAP1_S4_M_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_S4_M_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S4_M_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S4_M_ADDR, HWIO_GCC_QUPV3_WRAP1_S4_M_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S4_M_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S4_M_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S4_M_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S4_M_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S4_M_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S4_M_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S4_M_IN) +#define HWIO_GCC_QUPV3_WRAP1_S4_M_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_S4_M_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_S4_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000084fc) +#define HWIO_GCC_QUPV3_WRAP1_S4_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000084fc) +#define HWIO_GCC_QUPV3_WRAP1_S4_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000084fc) +#define HWIO_GCC_QUPV3_WRAP1_S4_N_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_S4_N_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S4_N_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S4_N_ADDR, HWIO_GCC_QUPV3_WRAP1_S4_N_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S4_N_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S4_N_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S4_N_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S4_N_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S4_N_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S4_N_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S4_N_IN) +#define HWIO_GCC_QUPV3_WRAP1_S4_N_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_S4_N_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_S4_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008500) +#define HWIO_GCC_QUPV3_WRAP1_S4_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008500) +#define HWIO_GCC_QUPV3_WRAP1_S4_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008500) +#define HWIO_GCC_QUPV3_WRAP1_S4_D_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_S4_D_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S4_D_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S4_D_ADDR, HWIO_GCC_QUPV3_WRAP1_S4_D_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S4_D_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S4_D_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S4_D_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S4_D_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S4_D_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S4_D_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S4_D_IN) +#define HWIO_GCC_QUPV3_WRAP1_S4_D_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_S4_D_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_S5_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000861c) +#define HWIO_GCC_QUPV3_WRAP1_S5_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000861c) +#define HWIO_GCC_QUPV3_WRAP1_S5_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000861c) +#define HWIO_GCC_QUPV3_WRAP1_S5_CBCR_RMSK 0x81c07004 +#define HWIO_GCC_QUPV3_WRAP1_S5_CBCR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S5_CBCR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S5_CBCR_ADDR, HWIO_GCC_QUPV3_WRAP1_S5_CBCR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S5_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S5_CBCR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S5_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S5_CBCR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S5_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S5_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S5_CBCR_IN) +#define HWIO_GCC_QUPV3_WRAP1_S5_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_WRAP1_S5_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_WRAP1_S5_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QUPV3_WRAP1_S5_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP1_S5_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QUPV3_WRAP1_S5_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QUPV3_WRAP1_S5_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QUPV3_WRAP1_S5_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QUPV3_WRAP1_S5_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_QUPV3_WRAP1_S5_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_QUPV3_WRAP1_S5_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S5_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S5_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_QUPV3_WRAP1_S5_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_QUPV3_WRAP1_S5_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S5_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S5_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_QUPV3_WRAP1_S5_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_S5_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S5_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S5_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QUPV3_WRAP1_S5_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S5_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S5_CBCR_CLK_ARES_RESET_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008620) +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008620) +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008620) +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_RMSK 0xf1ffffe +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S5_SREGR_ADDR, HWIO_GCC_QUPV3_WRAP1_S5_SREGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S5_SREGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S5_SREGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S5_SREGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S5_SREGR_IN) +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xf000000 +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_PWR_FSM_CLK_SEL_BMSK 0x100000 +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_PWR_FSM_CLK_SEL_SHFT 0x14 +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xf0000 +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S5_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008624) +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008624) +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008624) +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_SREGR_RMSK 0xffffffff +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_SREGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_SREGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S5_CFG_SREGR_ADDR, HWIO_GCC_QUPV3_WRAP1_S5_CFG_SREGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S5_CFG_SREGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_SREGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S5_CFG_SREGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S5_CFG_SREGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S5_CFG_SREGR_IN) +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_SREGR_MEM_CORE_OFF_TIMER_BMSK 0xfc000000 +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_SREGR_MEM_CORE_OFF_TIMER_SHFT 0x1a +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_BMSK 0x2000000 +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_SHFT 0x19 +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_BMSK 0x1000000 +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_SREGR_MEM_PERIPH_ON_STATUS_BMSK 0x800000 +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_SREGR_MEM_PERIPH_ON_STATUS_SHFT 0x17 +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_SREGR_MEM_CORE_ON_STATUS_BMSK 0x400000 +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_SREGR_MEM_CORE_ON_STATUS_SHFT 0x16 +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_SREGR_MEM_CPH_TIMER_BMSK 0x3f0000 +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_SREGR_MEM_CPH_TIMER_SHFT 0x10 +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_SREGR_SLEEP_TIMER_BMSK 0xff00 +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_SREGR_SLEEP_TIMER_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_SREGR_WAKEUP_TIMER_BMSK 0xff +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_SREGR_WAKEUP_TIMER_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000863c) +#define HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000863c) +#define HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000863c) +#define HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_RCG_SW_CTRL_BMSK 0x8000 +#define HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_RCG_SW_CTRL_SHFT 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_SW_PERF_STATE_BMSK 0x7800 +#define HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_SW_PERF_STATE_SHFT 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_SW_OVERRIDE_BMSK 0x400 +#define HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_SW_OVERRIDE_SHFT 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK 0x200 +#define HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_DFS_FSM_STATE_BMSK 0x1c0 +#define HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_DFS_FSM_STATE_SHFT 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_HW_CLK_CONTROL_BMSK 0x20 +#define HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_HW_CLK_CONTROL_SHFT 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_CURR_PERF_STATE_BMSK 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_CURR_PERF_STATE_SHFT 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_DFS_EN_BMSK 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_DFS_EN_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_DFS_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_DFS_EN_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008644) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008644) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008644) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008648) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008648) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008648) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000864c) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000864c) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000864c) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008650) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008650) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008650) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008654) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008654) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008654) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008658) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008658) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008658) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000865c) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000865c) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000865c) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008660) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008660) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008660) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008684) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008684) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008684) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008688) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008688) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008688) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000868c) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000868c) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000868c) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008690) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008690) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008690) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008694) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008694) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008694) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008698) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008698) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008698) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000869c) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000869c) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000869c) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000086a0) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000086a0) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000086a0) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000086c4) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000086c4) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000086c4) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000086c8) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000086c8) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000086c8) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000086cc) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000086cc) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000086cc) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000086d0) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000086d0) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000086d0) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000086d4) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000086d4) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000086d4) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000086d8) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000086d8) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000086d8) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000086dc) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000086dc) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000086dc) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000086e0) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000086e0) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000086e0) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008704) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008704) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008704) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008708) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008708) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008708) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000870c) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000870c) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000870c) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008710) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008710) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008710) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008714) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008714) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008714) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008718) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008718) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008718) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000871c) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000871c) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000871c) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008720) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008720) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008720) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008628) +#define HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008628) +#define HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008628) +#define HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_RMSK 0x800000f3 +#define HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_ADDR, HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_IN) +#define HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_DIRTY_D_BMSK 0x80 +#define HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_DIRTY_D_SHFT 0x7 +#define HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_DIRTY_N_BMSK 0x40 +#define HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_DIRTY_N_SHFT 0x6 +#define HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_DIRTY_M_BMSK 0x20 +#define HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_DIRTY_M_SHFT 0x5 +#define HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000862c) +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000862c) +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000862c) +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_RMSK 0x10371f +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_ADDR, HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_IN) +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_S5_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008630) +#define HWIO_GCC_QUPV3_WRAP1_S5_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008630) +#define HWIO_GCC_QUPV3_WRAP1_S5_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008630) +#define HWIO_GCC_QUPV3_WRAP1_S5_M_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_S5_M_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S5_M_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S5_M_ADDR, HWIO_GCC_QUPV3_WRAP1_S5_M_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S5_M_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S5_M_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S5_M_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S5_M_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S5_M_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S5_M_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S5_M_IN) +#define HWIO_GCC_QUPV3_WRAP1_S5_M_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_S5_M_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_S5_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008634) +#define HWIO_GCC_QUPV3_WRAP1_S5_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008634) +#define HWIO_GCC_QUPV3_WRAP1_S5_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008634) +#define HWIO_GCC_QUPV3_WRAP1_S5_N_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_S5_N_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S5_N_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S5_N_ADDR, HWIO_GCC_QUPV3_WRAP1_S5_N_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S5_N_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S5_N_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S5_N_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S5_N_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S5_N_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S5_N_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S5_N_IN) +#define HWIO_GCC_QUPV3_WRAP1_S5_N_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_S5_N_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_S5_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008638) +#define HWIO_GCC_QUPV3_WRAP1_S5_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008638) +#define HWIO_GCC_QUPV3_WRAP1_S5_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008638) +#define HWIO_GCC_QUPV3_WRAP1_S5_D_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_S5_D_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S5_D_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S5_D_ADDR, HWIO_GCC_QUPV3_WRAP1_S5_D_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S5_D_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S5_D_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S5_D_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S5_D_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S5_D_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S5_D_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S5_D_IN) +#define HWIO_GCC_QUPV3_WRAP1_S5_D_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_S5_D_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_S6_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008754) +#define HWIO_GCC_QUPV3_WRAP1_S6_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008754) +#define HWIO_GCC_QUPV3_WRAP1_S6_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008754) +#define HWIO_GCC_QUPV3_WRAP1_S6_CBCR_RMSK 0x81c07004 +#define HWIO_GCC_QUPV3_WRAP1_S6_CBCR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S6_CBCR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S6_CBCR_ADDR, HWIO_GCC_QUPV3_WRAP1_S6_CBCR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S6_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S6_CBCR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S6_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S6_CBCR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S6_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S6_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S6_CBCR_IN) +#define HWIO_GCC_QUPV3_WRAP1_S6_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_WRAP1_S6_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_WRAP1_S6_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QUPV3_WRAP1_S6_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP1_S6_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QUPV3_WRAP1_S6_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QUPV3_WRAP1_S6_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QUPV3_WRAP1_S6_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QUPV3_WRAP1_S6_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_QUPV3_WRAP1_S6_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_QUPV3_WRAP1_S6_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S6_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S6_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_QUPV3_WRAP1_S6_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_QUPV3_WRAP1_S6_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S6_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S6_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_QUPV3_WRAP1_S6_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_S6_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S6_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S6_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QUPV3_WRAP1_S6_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S6_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S6_CBCR_CLK_ARES_RESET_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008758) +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008758) +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008758) +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_RMSK 0xf1ffffe +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S6_SREGR_ADDR, HWIO_GCC_QUPV3_WRAP1_S6_SREGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S6_SREGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S6_SREGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S6_SREGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S6_SREGR_IN) +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xf000000 +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_PWR_FSM_CLK_SEL_BMSK 0x100000 +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_PWR_FSM_CLK_SEL_SHFT 0x14 +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xf0000 +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S6_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000875c) +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000875c) +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000875c) +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_SREGR_RMSK 0xffffffff +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_SREGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_SREGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S6_CFG_SREGR_ADDR, HWIO_GCC_QUPV3_WRAP1_S6_CFG_SREGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S6_CFG_SREGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_SREGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S6_CFG_SREGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S6_CFG_SREGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S6_CFG_SREGR_IN) +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_SREGR_MEM_CORE_OFF_TIMER_BMSK 0xfc000000 +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_SREGR_MEM_CORE_OFF_TIMER_SHFT 0x1a +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_BMSK 0x2000000 +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_SHFT 0x19 +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_BMSK 0x1000000 +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_SREGR_MEM_PERIPH_ON_STATUS_BMSK 0x800000 +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_SREGR_MEM_PERIPH_ON_STATUS_SHFT 0x17 +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_SREGR_MEM_CORE_ON_STATUS_BMSK 0x400000 +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_SREGR_MEM_CORE_ON_STATUS_SHFT 0x16 +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_SREGR_MEM_CPH_TIMER_BMSK 0x3f0000 +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_SREGR_MEM_CPH_TIMER_SHFT 0x10 +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_SREGR_SLEEP_TIMER_BMSK 0xff00 +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_SREGR_SLEEP_TIMER_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_SREGR_WAKEUP_TIMER_BMSK 0xff +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_SREGR_WAKEUP_TIMER_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE6_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008774) +#define HWIO_GCC_QUPV3_WRAP1_SE6_CMD_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008774) +#define HWIO_GCC_QUPV3_WRAP1_SE6_CMD_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008774) +#define HWIO_GCC_QUPV3_WRAP1_SE6_CMD_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE6_CMD_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE6_CMD_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_CMD_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE6_CMD_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE6_CMD_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_CMD_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE6_CMD_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE6_CMD_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE6_CMD_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE6_CMD_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE6_CMD_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE6_CMD_DFSR_RCG_SW_CTRL_BMSK 0x8000 +#define HWIO_GCC_QUPV3_WRAP1_SE6_CMD_DFSR_RCG_SW_CTRL_SHFT 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE6_CMD_DFSR_SW_PERF_STATE_BMSK 0x7800 +#define HWIO_GCC_QUPV3_WRAP1_SE6_CMD_DFSR_SW_PERF_STATE_SHFT 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE6_CMD_DFSR_SW_OVERRIDE_BMSK 0x400 +#define HWIO_GCC_QUPV3_WRAP1_SE6_CMD_DFSR_SW_OVERRIDE_SHFT 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE6_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK 0x200 +#define HWIO_GCC_QUPV3_WRAP1_SE6_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE6_CMD_DFSR_DFS_FSM_STATE_BMSK 0x1c0 +#define HWIO_GCC_QUPV3_WRAP1_SE6_CMD_DFSR_DFS_FSM_STATE_SHFT 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE6_CMD_DFSR_HW_CLK_CONTROL_BMSK 0x20 +#define HWIO_GCC_QUPV3_WRAP1_SE6_CMD_DFSR_HW_CLK_CONTROL_SHFT 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE6_CMD_DFSR_CURR_PERF_STATE_BMSK 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE6_CMD_DFSR_CURR_PERF_STATE_SHFT 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE6_CMD_DFSR_DFS_EN_BMSK 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE6_CMD_DFSR_DFS_EN_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE6_CMD_DFSR_DFS_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE6_CMD_DFSR_DFS_EN_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000877c) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000877c) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000877c) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008780) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008780) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008780) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008784) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008784) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008784) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008788) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008788) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008788) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000878c) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000878c) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000878c) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008790) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008790) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008790) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008794) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008794) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008794) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008798) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008798) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008798) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000087bc) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000087bc) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000087bc) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000087c0) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000087c0) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000087c0) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000087c4) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000087c4) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000087c4) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000087c8) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000087c8) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000087c8) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000087cc) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000087cc) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000087cc) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000087d0) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000087d0) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000087d0) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000087d4) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000087d4) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000087d4) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000087d8) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000087d8) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000087d8) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000087fc) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000087fc) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000087fc) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008800) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008800) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008800) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008804) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008804) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008804) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008808) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008808) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008808) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000880c) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000880c) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000880c) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008810) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008810) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008810) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008814) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008814) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008814) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008818) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008818) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008818) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000883c) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000883c) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000883c) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008840) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008840) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008840) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008844) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008844) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008844) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008848) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008848) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008848) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000884c) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000884c) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000884c) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008850) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008850) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008850) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008854) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008854) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008854) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008858) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008858) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008858) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_S6_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008760) +#define HWIO_GCC_QUPV3_WRAP1_S6_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008760) +#define HWIO_GCC_QUPV3_WRAP1_S6_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008760) +#define HWIO_GCC_QUPV3_WRAP1_S6_CMD_RCGR_RMSK 0x800000f3 +#define HWIO_GCC_QUPV3_WRAP1_S6_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S6_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S6_CMD_RCGR_ADDR, HWIO_GCC_QUPV3_WRAP1_S6_CMD_RCGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S6_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S6_CMD_RCGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S6_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S6_CMD_RCGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S6_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S6_CMD_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S6_CMD_RCGR_IN) +#define HWIO_GCC_QUPV3_WRAP1_S6_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_WRAP1_S6_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_WRAP1_S6_CMD_RCGR_DIRTY_D_BMSK 0x80 +#define HWIO_GCC_QUPV3_WRAP1_S6_CMD_RCGR_DIRTY_D_SHFT 0x7 +#define HWIO_GCC_QUPV3_WRAP1_S6_CMD_RCGR_DIRTY_N_BMSK 0x40 +#define HWIO_GCC_QUPV3_WRAP1_S6_CMD_RCGR_DIRTY_N_SHFT 0x6 +#define HWIO_GCC_QUPV3_WRAP1_S6_CMD_RCGR_DIRTY_M_BMSK 0x20 +#define HWIO_GCC_QUPV3_WRAP1_S6_CMD_RCGR_DIRTY_M_SHFT 0x5 +#define HWIO_GCC_QUPV3_WRAP1_S6_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_QUPV3_WRAP1_S6_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_QUPV3_WRAP1_S6_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S6_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S6_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S6_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S6_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S6_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S6_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S6_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008764) +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008764) +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008764) +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_RMSK 0x10371f +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_ADDR, HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_IN) +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_S6_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_S6_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008768) +#define HWIO_GCC_QUPV3_WRAP1_S6_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008768) +#define HWIO_GCC_QUPV3_WRAP1_S6_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008768) +#define HWIO_GCC_QUPV3_WRAP1_S6_M_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_S6_M_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S6_M_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S6_M_ADDR, HWIO_GCC_QUPV3_WRAP1_S6_M_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S6_M_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S6_M_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S6_M_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S6_M_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S6_M_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S6_M_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S6_M_IN) +#define HWIO_GCC_QUPV3_WRAP1_S6_M_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_S6_M_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_S6_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000876c) +#define HWIO_GCC_QUPV3_WRAP1_S6_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000876c) +#define HWIO_GCC_QUPV3_WRAP1_S6_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000876c) +#define HWIO_GCC_QUPV3_WRAP1_S6_N_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_S6_N_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S6_N_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S6_N_ADDR, HWIO_GCC_QUPV3_WRAP1_S6_N_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S6_N_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S6_N_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S6_N_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S6_N_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S6_N_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S6_N_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S6_N_IN) +#define HWIO_GCC_QUPV3_WRAP1_S6_N_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_S6_N_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_S6_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008770) +#define HWIO_GCC_QUPV3_WRAP1_S6_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008770) +#define HWIO_GCC_QUPV3_WRAP1_S6_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008770) +#define HWIO_GCC_QUPV3_WRAP1_S6_D_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_S6_D_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S6_D_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S6_D_ADDR, HWIO_GCC_QUPV3_WRAP1_S6_D_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S6_D_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S6_D_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S6_D_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S6_D_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S6_D_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S6_D_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S6_D_IN) +#define HWIO_GCC_QUPV3_WRAP1_S6_D_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_S6_D_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_S7_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000888c) +#define HWIO_GCC_QUPV3_WRAP1_S7_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000888c) +#define HWIO_GCC_QUPV3_WRAP1_S7_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000888c) +#define HWIO_GCC_QUPV3_WRAP1_S7_CBCR_RMSK 0x81c07004 +#define HWIO_GCC_QUPV3_WRAP1_S7_CBCR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S7_CBCR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S7_CBCR_ADDR, HWIO_GCC_QUPV3_WRAP1_S7_CBCR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S7_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S7_CBCR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S7_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S7_CBCR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S7_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S7_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S7_CBCR_IN) +#define HWIO_GCC_QUPV3_WRAP1_S7_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_WRAP1_S7_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_WRAP1_S7_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QUPV3_WRAP1_S7_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP1_S7_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QUPV3_WRAP1_S7_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QUPV3_WRAP1_S7_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QUPV3_WRAP1_S7_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QUPV3_WRAP1_S7_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_QUPV3_WRAP1_S7_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_QUPV3_WRAP1_S7_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S7_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S7_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_QUPV3_WRAP1_S7_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_QUPV3_WRAP1_S7_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S7_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S7_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_QUPV3_WRAP1_S7_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_S7_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S7_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S7_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QUPV3_WRAP1_S7_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S7_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S7_CBCR_CLK_ARES_RESET_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008890) +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008890) +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008890) +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_RMSK 0xf1ffffe +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S7_SREGR_ADDR, HWIO_GCC_QUPV3_WRAP1_S7_SREGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S7_SREGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S7_SREGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S7_SREGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S7_SREGR_IN) +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xf000000 +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_PWR_FSM_CLK_SEL_BMSK 0x100000 +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_PWR_FSM_CLK_SEL_SHFT 0x14 +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xf0000 +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S7_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008894) +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008894) +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008894) +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_SREGR_RMSK 0xffffffff +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_SREGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_SREGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S7_CFG_SREGR_ADDR, HWIO_GCC_QUPV3_WRAP1_S7_CFG_SREGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S7_CFG_SREGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_SREGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S7_CFG_SREGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S7_CFG_SREGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S7_CFG_SREGR_IN) +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_SREGR_MEM_CORE_OFF_TIMER_BMSK 0xfc000000 +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_SREGR_MEM_CORE_OFF_TIMER_SHFT 0x1a +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_BMSK 0x2000000 +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_SHFT 0x19 +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_BMSK 0x1000000 +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_SREGR_MEM_PERIPH_ON_STATUS_BMSK 0x800000 +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_SREGR_MEM_PERIPH_ON_STATUS_SHFT 0x17 +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_SREGR_MEM_CORE_ON_STATUS_BMSK 0x400000 +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_SREGR_MEM_CORE_ON_STATUS_SHFT 0x16 +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_SREGR_MEM_CPH_TIMER_BMSK 0x3f0000 +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_SREGR_MEM_CPH_TIMER_SHFT 0x10 +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_SREGR_SLEEP_TIMER_BMSK 0xff00 +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_SREGR_SLEEP_TIMER_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_SREGR_WAKEUP_TIMER_BMSK 0xff +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_SREGR_WAKEUP_TIMER_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE7_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000088ac) +#define HWIO_GCC_QUPV3_WRAP1_SE7_CMD_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000088ac) +#define HWIO_GCC_QUPV3_WRAP1_SE7_CMD_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000088ac) +#define HWIO_GCC_QUPV3_WRAP1_SE7_CMD_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE7_CMD_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE7_CMD_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_CMD_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE7_CMD_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE7_CMD_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_CMD_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE7_CMD_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE7_CMD_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE7_CMD_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE7_CMD_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE7_CMD_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE7_CMD_DFSR_RCG_SW_CTRL_BMSK 0x8000 +#define HWIO_GCC_QUPV3_WRAP1_SE7_CMD_DFSR_RCG_SW_CTRL_SHFT 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE7_CMD_DFSR_SW_PERF_STATE_BMSK 0x7800 +#define HWIO_GCC_QUPV3_WRAP1_SE7_CMD_DFSR_SW_PERF_STATE_SHFT 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE7_CMD_DFSR_SW_OVERRIDE_BMSK 0x400 +#define HWIO_GCC_QUPV3_WRAP1_SE7_CMD_DFSR_SW_OVERRIDE_SHFT 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE7_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK 0x200 +#define HWIO_GCC_QUPV3_WRAP1_SE7_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE7_CMD_DFSR_DFS_FSM_STATE_BMSK 0x1c0 +#define HWIO_GCC_QUPV3_WRAP1_SE7_CMD_DFSR_DFS_FSM_STATE_SHFT 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE7_CMD_DFSR_HW_CLK_CONTROL_BMSK 0x20 +#define HWIO_GCC_QUPV3_WRAP1_SE7_CMD_DFSR_HW_CLK_CONTROL_SHFT 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE7_CMD_DFSR_CURR_PERF_STATE_BMSK 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE7_CMD_DFSR_CURR_PERF_STATE_SHFT 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE7_CMD_DFSR_DFS_EN_BMSK 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE7_CMD_DFSR_DFS_EN_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE7_CMD_DFSR_DFS_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE7_CMD_DFSR_DFS_EN_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000088b4) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000088b4) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000088b4) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000088b8) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000088b8) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000088b8) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000088bc) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000088bc) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000088bc) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000088c0) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000088c0) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000088c0) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000088c4) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000088c4) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000088c4) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000088c8) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000088c8) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000088c8) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000088cc) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000088cc) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000088cc) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000088d0) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000088d0) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000088d0) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000088f4) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000088f4) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000088f4) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000088f8) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000088f8) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000088f8) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000088fc) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000088fc) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000088fc) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008900) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008900) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008900) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008904) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008904) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008904) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008908) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008908) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008908) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000890c) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000890c) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000890c) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008910) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008910) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008910) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008934) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008934) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008934) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008938) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008938) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008938) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000893c) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000893c) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000893c) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008940) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008940) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008940) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008944) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008944) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008944) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008948) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008948) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008948) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000894c) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000894c) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000894c) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008950) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008950) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008950) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008974) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008974) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008974) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008978) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008978) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008978) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000897c) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000897c) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000897c) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008980) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008980) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008980) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008984) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008984) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008984) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008988) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008988) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008988) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000898c) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000898c) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000898c) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008990) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008990) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008990) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_S7_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008898) +#define HWIO_GCC_QUPV3_WRAP1_S7_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008898) +#define HWIO_GCC_QUPV3_WRAP1_S7_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008898) +#define HWIO_GCC_QUPV3_WRAP1_S7_CMD_RCGR_RMSK 0x800000f3 +#define HWIO_GCC_QUPV3_WRAP1_S7_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S7_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S7_CMD_RCGR_ADDR, HWIO_GCC_QUPV3_WRAP1_S7_CMD_RCGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S7_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S7_CMD_RCGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S7_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S7_CMD_RCGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S7_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S7_CMD_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S7_CMD_RCGR_IN) +#define HWIO_GCC_QUPV3_WRAP1_S7_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_WRAP1_S7_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_WRAP1_S7_CMD_RCGR_DIRTY_D_BMSK 0x80 +#define HWIO_GCC_QUPV3_WRAP1_S7_CMD_RCGR_DIRTY_D_SHFT 0x7 +#define HWIO_GCC_QUPV3_WRAP1_S7_CMD_RCGR_DIRTY_N_BMSK 0x40 +#define HWIO_GCC_QUPV3_WRAP1_S7_CMD_RCGR_DIRTY_N_SHFT 0x6 +#define HWIO_GCC_QUPV3_WRAP1_S7_CMD_RCGR_DIRTY_M_BMSK 0x20 +#define HWIO_GCC_QUPV3_WRAP1_S7_CMD_RCGR_DIRTY_M_SHFT 0x5 +#define HWIO_GCC_QUPV3_WRAP1_S7_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_QUPV3_WRAP1_S7_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_QUPV3_WRAP1_S7_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S7_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S7_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S7_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S7_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S7_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S7_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S7_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000889c) +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000889c) +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000889c) +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_RMSK 0x10371f +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_ADDR, HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_IN) +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP1_S7_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP1_S7_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000088a0) +#define HWIO_GCC_QUPV3_WRAP1_S7_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000088a0) +#define HWIO_GCC_QUPV3_WRAP1_S7_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000088a0) +#define HWIO_GCC_QUPV3_WRAP1_S7_M_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_S7_M_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S7_M_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S7_M_ADDR, HWIO_GCC_QUPV3_WRAP1_S7_M_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S7_M_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S7_M_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S7_M_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S7_M_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S7_M_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S7_M_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S7_M_IN) +#define HWIO_GCC_QUPV3_WRAP1_S7_M_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_S7_M_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_S7_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000088a4) +#define HWIO_GCC_QUPV3_WRAP1_S7_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000088a4) +#define HWIO_GCC_QUPV3_WRAP1_S7_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000088a4) +#define HWIO_GCC_QUPV3_WRAP1_S7_N_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_S7_N_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S7_N_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S7_N_ADDR, HWIO_GCC_QUPV3_WRAP1_S7_N_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S7_N_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S7_N_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S7_N_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S7_N_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S7_N_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S7_N_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S7_N_IN) +#define HWIO_GCC_QUPV3_WRAP1_S7_N_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_S7_N_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP1_S7_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000088a8) +#define HWIO_GCC_QUPV3_WRAP1_S7_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000088a8) +#define HWIO_GCC_QUPV3_WRAP1_S7_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000088a8) +#define HWIO_GCC_QUPV3_WRAP1_S7_D_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_S7_D_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP1_S7_D_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S7_D_ADDR, HWIO_GCC_QUPV3_WRAP1_S7_D_RMSK) +#define HWIO_GCC_QUPV3_WRAP1_S7_D_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S7_D_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP1_S7_D_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP1_S7_D_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP1_S7_D_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S7_D_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S7_D_IN) +#define HWIO_GCC_QUPV3_WRAP1_S7_D_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP1_S7_D_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAPPER_2_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e000) +#define HWIO_GCC_QUPV3_WRAPPER_2_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e000) +#define HWIO_GCC_QUPV3_WRAPPER_2_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e000) +#define HWIO_GCC_QUPV3_WRAPPER_2_BCR_RMSK 0x1 +#define HWIO_GCC_QUPV3_WRAPPER_2_BCR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAPPER_2_BCR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAPPER_2_BCR_ADDR, HWIO_GCC_QUPV3_WRAPPER_2_BCR_RMSK) +#define HWIO_GCC_QUPV3_WRAPPER_2_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAPPER_2_BCR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAPPER_2_BCR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAPPER_2_BCR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAPPER_2_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAPPER_2_BCR_ADDR,m,v,HWIO_GCC_QUPV3_WRAPPER_2_BCR_IN) +#define HWIO_GCC_QUPV3_WRAPPER_2_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_QUPV3_WRAPPER_2_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAPPER_2_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAPPER_2_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP_2_M_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000133cc) +#define HWIO_GCC_QUPV3_WRAP_2_M_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000133cc) +#define HWIO_GCC_QUPV3_WRAP_2_M_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000133cc) +#define HWIO_GCC_QUPV3_WRAP_2_M_AHB_CBCR_RMSK 0x81d0000e +#define HWIO_GCC_QUPV3_WRAP_2_M_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP_2_M_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP_2_M_AHB_CBCR_ADDR, HWIO_GCC_QUPV3_WRAP_2_M_AHB_CBCR_RMSK) +#define HWIO_GCC_QUPV3_WRAP_2_M_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP_2_M_AHB_CBCR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP_2_M_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP_2_M_AHB_CBCR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP_2_M_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP_2_M_AHB_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP_2_M_AHB_CBCR_IN) +#define HWIO_GCC_QUPV3_WRAP_2_M_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_WRAP_2_M_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_WRAP_2_M_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QUPV3_WRAP_2_M_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP_2_M_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QUPV3_WRAP_2_M_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QUPV3_WRAP_2_M_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QUPV3_WRAP_2_M_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QUPV3_WRAP_2_M_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_QUPV3_WRAP_2_M_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_QUPV3_WRAP_2_M_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_QUPV3_WRAP_2_M_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_QUPV3_WRAP_2_M_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QUPV3_WRAP_2_M_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QUPV3_WRAP_2_M_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP_2_M_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP_2_M_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_QUPV3_WRAP_2_M_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_QUPV3_WRAP_2_M_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP_2_M_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP_2_S_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000133d0) +#define HWIO_GCC_QUPV3_WRAP_2_S_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000133d0) +#define HWIO_GCC_QUPV3_WRAP_2_S_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000133d0) +#define HWIO_GCC_QUPV3_WRAP_2_S_AHB_CBCR_RMSK 0x81d0000e +#define HWIO_GCC_QUPV3_WRAP_2_S_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP_2_S_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP_2_S_AHB_CBCR_ADDR, HWIO_GCC_QUPV3_WRAP_2_S_AHB_CBCR_RMSK) +#define HWIO_GCC_QUPV3_WRAP_2_S_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP_2_S_AHB_CBCR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP_2_S_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP_2_S_AHB_CBCR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP_2_S_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP_2_S_AHB_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP_2_S_AHB_CBCR_IN) +#define HWIO_GCC_QUPV3_WRAP_2_S_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_WRAP_2_S_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_WRAP_2_S_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QUPV3_WRAP_2_S_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP_2_S_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QUPV3_WRAP_2_S_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QUPV3_WRAP_2_S_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QUPV3_WRAP_2_S_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QUPV3_WRAP_2_S_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_QUPV3_WRAP_2_S_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_QUPV3_WRAP_2_S_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_QUPV3_WRAP_2_S_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_QUPV3_WRAP_2_S_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QUPV3_WRAP_2_S_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QUPV3_WRAP_2_S_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP_2_S_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP_2_S_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_QUPV3_WRAP_2_S_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_QUPV3_WRAP_2_S_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP_2_S_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000133d4) +#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000133d4) +#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000133d4) +#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_RMSK 0x81d07004 +#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_ADDR, HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_IN) +#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_CLK_ARES_RESET_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000133d8) +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000133d8) +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000133d8) +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_RMSK 0xf1ffffe +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_ADDR, HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_IN) +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xf000000 +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_PWR_FSM_CLK_SEL_BMSK 0x100000 +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_PWR_FSM_CLK_SEL_SHFT 0x14 +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xf0000 +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_CORE_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP2_CORE_CFG_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000133dc) +#define HWIO_GCC_QUPV3_WRAP2_CORE_CFG_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000133dc) +#define HWIO_GCC_QUPV3_WRAP2_CORE_CFG_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000133dc) +#define HWIO_GCC_QUPV3_WRAP2_CORE_CFG_SREGR_RMSK 0xffffffff +#define HWIO_GCC_QUPV3_WRAP2_CORE_CFG_SREGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_CORE_CFG_SREGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_CORE_CFG_SREGR_ADDR, HWIO_GCC_QUPV3_WRAP2_CORE_CFG_SREGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_CORE_CFG_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_CORE_CFG_SREGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_CORE_CFG_SREGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_CORE_CFG_SREGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_CORE_CFG_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_CORE_CFG_SREGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_CORE_CFG_SREGR_IN) +#define HWIO_GCC_QUPV3_WRAP2_CORE_CFG_SREGR_MEM_CORE_OFF_TIMER_BMSK 0xfc000000 +#define HWIO_GCC_QUPV3_WRAP2_CORE_CFG_SREGR_MEM_CORE_OFF_TIMER_SHFT 0x1a +#define HWIO_GCC_QUPV3_WRAP2_CORE_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_BMSK 0x2000000 +#define HWIO_GCC_QUPV3_WRAP2_CORE_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_SHFT 0x19 +#define HWIO_GCC_QUPV3_WRAP2_CORE_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_BMSK 0x1000000 +#define HWIO_GCC_QUPV3_WRAP2_CORE_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP2_CORE_CFG_SREGR_MEM_PERIPH_ON_STATUS_BMSK 0x800000 +#define HWIO_GCC_QUPV3_WRAP2_CORE_CFG_SREGR_MEM_PERIPH_ON_STATUS_SHFT 0x17 +#define HWIO_GCC_QUPV3_WRAP2_CORE_CFG_SREGR_MEM_CORE_ON_STATUS_BMSK 0x400000 +#define HWIO_GCC_QUPV3_WRAP2_CORE_CFG_SREGR_MEM_CORE_ON_STATUS_SHFT 0x16 +#define HWIO_GCC_QUPV3_WRAP2_CORE_CFG_SREGR_MEM_CPH_TIMER_BMSK 0x3f0000 +#define HWIO_GCC_QUPV3_WRAP2_CORE_CFG_SREGR_MEM_CPH_TIMER_SHFT 0x10 +#define HWIO_GCC_QUPV3_WRAP2_CORE_CFG_SREGR_SLEEP_TIMER_BMSK 0xff00 +#define HWIO_GCC_QUPV3_WRAP2_CORE_CFG_SREGR_SLEEP_TIMER_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_CORE_CFG_SREGR_WAKEUP_TIMER_BMSK 0xff +#define HWIO_GCC_QUPV3_WRAP2_CORE_CFG_SREGR_WAKEUP_TIMER_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_CORE_DIV_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00013000) +#define HWIO_GCC_QUPV3_WRAP2_CORE_DIV_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00013000) +#define HWIO_GCC_QUPV3_WRAP2_CORE_DIV_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00013000) +#define HWIO_GCC_QUPV3_WRAP2_CORE_DIV_CDIVR_RMSK 0xf +#define HWIO_GCC_QUPV3_WRAP2_CORE_DIV_CDIVR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_CORE_DIV_CDIVR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_CORE_DIV_CDIVR_ADDR, HWIO_GCC_QUPV3_WRAP2_CORE_DIV_CDIVR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_CORE_DIV_CDIVR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_CORE_DIV_CDIVR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_CORE_DIV_CDIVR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_CORE_DIV_CDIVR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_CORE_DIV_CDIVR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_CORE_DIV_CDIVR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_CORE_DIV_CDIVR_IN) +#define HWIO_GCC_QUPV3_WRAP2_CORE_DIV_CDIVR_CLK_DIV_BMSK 0xf +#define HWIO_GCC_QUPV3_WRAP2_CORE_DIV_CDIVR_CLK_DIV_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00013004) +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00013004) +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00013004) +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_RMSK 0x81d07004 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_ADDR, HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_IN) +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_CLK_ARES_RESET_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00013008) +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00013008) +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00013008) +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_RMSK 0xf1ffffe +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_ADDR, HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_IN) +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xf000000 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_PWR_FSM_CLK_SEL_BMSK 0x100000 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_PWR_FSM_CLK_SEL_SHFT 0x14 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xf0000 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001300c) +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001300c) +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001300c) +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_SREGR_RMSK 0xffffffff +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_SREGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_SREGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_SREGR_ADDR, HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_SREGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_SREGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_SREGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_SREGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_SREGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_SREGR_IN) +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_SREGR_MEM_CORE_OFF_TIMER_BMSK 0xfc000000 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_SREGR_MEM_CORE_OFF_TIMER_SHFT 0x1a +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_BMSK 0x2000000 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_SHFT 0x19 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_BMSK 0x1000000 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_SREGR_MEM_PERIPH_ON_STATUS_BMSK 0x800000 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_SREGR_MEM_PERIPH_ON_STATUS_SHFT 0x17 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_SREGR_MEM_CORE_ON_STATUS_BMSK 0x400000 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_SREGR_MEM_CORE_ON_STATUS_SHFT 0x16 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_SREGR_MEM_CPH_TIMER_BMSK 0x3f0000 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_SREGR_MEM_CPH_TIMER_SHFT 0x10 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_SREGR_SLEEP_TIMER_BMSK 0xff00 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_SREGR_SLEEP_TIMER_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_SREGR_WAKEUP_TIMER_BMSK 0xff +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_SREGR_WAKEUP_TIMER_SHFT 0x0 + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001302c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001302c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001302c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00013030) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00013030) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00013030) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00013034) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00013034) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00013034) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00013038) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00013038) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00013038) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001303c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001303c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001303c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00013040) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00013040) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00013040) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00013044) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00013044) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00013044) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00013048) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00013048) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00013048) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001304c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001304c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001304c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00013050) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00013050) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00013050) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00013054) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00013054) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00013054) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00013058) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00013058) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00013058) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001305c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001305c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001305c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00013060) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00013060) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00013060) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00013064) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00013064) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00013064) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00013068) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00013068) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00013068) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00013010) +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00013010) +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00013010) +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR_ADDR, HWIO_GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR_IN) +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00013014) +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00013014) +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00013014) +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_ADDR, HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_IN) +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_S0_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e004) +#define HWIO_GCC_QUPV3_WRAP2_S0_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e004) +#define HWIO_GCC_QUPV3_WRAP2_S0_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e004) +#define HWIO_GCC_QUPV3_WRAP2_S0_CBCR_RMSK 0x81c07004 +#define HWIO_GCC_QUPV3_WRAP2_S0_CBCR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S0_CBCR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S0_CBCR_ADDR, HWIO_GCC_QUPV3_WRAP2_S0_CBCR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S0_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S0_CBCR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S0_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S0_CBCR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S0_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S0_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S0_CBCR_IN) +#define HWIO_GCC_QUPV3_WRAP2_S0_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_WRAP2_S0_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_WRAP2_S0_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QUPV3_WRAP2_S0_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP2_S0_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QUPV3_WRAP2_S0_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QUPV3_WRAP2_S0_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QUPV3_WRAP2_S0_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QUPV3_WRAP2_S0_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_QUPV3_WRAP2_S0_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_QUPV3_WRAP2_S0_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S0_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S0_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_QUPV3_WRAP2_S0_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_QUPV3_WRAP2_S0_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S0_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S0_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_QUPV3_WRAP2_S0_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_S0_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S0_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S0_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QUPV3_WRAP2_S0_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S0_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S0_CBCR_CLK_ARES_RESET_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e008) +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e008) +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e008) +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_RMSK 0xf1ffffe +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S0_SREGR_ADDR, HWIO_GCC_QUPV3_WRAP2_S0_SREGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S0_SREGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S0_SREGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S0_SREGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S0_SREGR_IN) +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xf000000 +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_PWR_FSM_CLK_SEL_BMSK 0x100000 +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_PWR_FSM_CLK_SEL_SHFT 0x14 +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xf0000 +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S0_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e00c) +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e00c) +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e00c) +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_SREGR_RMSK 0xffffffff +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_SREGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_SREGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S0_CFG_SREGR_ADDR, HWIO_GCC_QUPV3_WRAP2_S0_CFG_SREGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S0_CFG_SREGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_SREGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S0_CFG_SREGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S0_CFG_SREGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S0_CFG_SREGR_IN) +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_SREGR_MEM_CORE_OFF_TIMER_BMSK 0xfc000000 +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_SREGR_MEM_CORE_OFF_TIMER_SHFT 0x1a +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_BMSK 0x2000000 +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_SHFT 0x19 +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_BMSK 0x1000000 +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_SREGR_MEM_PERIPH_ON_STATUS_BMSK 0x800000 +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_SREGR_MEM_PERIPH_ON_STATUS_SHFT 0x17 +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_SREGR_MEM_CORE_ON_STATUS_BMSK 0x400000 +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_SREGR_MEM_CORE_ON_STATUS_SHFT 0x16 +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_SREGR_MEM_CPH_TIMER_BMSK 0x3f0000 +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_SREGR_MEM_CPH_TIMER_SHFT 0x10 +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_SREGR_SLEEP_TIMER_BMSK 0xff00 +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_SREGR_SLEEP_TIMER_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_SREGR_WAKEUP_TIMER_BMSK 0xff +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_SREGR_WAKEUP_TIMER_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e024) +#define HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e024) +#define HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e024) +#define HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_RCG_SW_CTRL_BMSK 0x8000 +#define HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_RCG_SW_CTRL_SHFT 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_SW_PERF_STATE_BMSK 0x7800 +#define HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_SW_PERF_STATE_SHFT 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_SW_OVERRIDE_BMSK 0x400 +#define HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_SW_OVERRIDE_SHFT 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK 0x200 +#define HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_DFS_FSM_STATE_BMSK 0x1c0 +#define HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_DFS_FSM_STATE_SHFT 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_HW_CLK_CONTROL_BMSK 0x20 +#define HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_HW_CLK_CONTROL_SHFT 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_CURR_PERF_STATE_BMSK 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_CURR_PERF_STATE_SHFT 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_DFS_EN_BMSK 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_DFS_EN_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_DFS_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_DFS_EN_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e02c) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e02c) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e02c) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e030) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e030) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e030) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e034) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e034) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e034) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e038) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e038) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e038) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e03c) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e03c) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e03c) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e040) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e040) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e040) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e044) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e044) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e044) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e048) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e048) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e048) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e06c) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e06c) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e06c) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e070) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e070) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e070) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e074) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e074) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e074) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e078) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e078) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e078) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e07c) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e07c) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e07c) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e080) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e080) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e080) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e084) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e084) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e084) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e088) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e088) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e088) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e0ac) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e0ac) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e0ac) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e0b0) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e0b0) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e0b0) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e0b4) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e0b4) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e0b4) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e0b8) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e0b8) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e0b8) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e0bc) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e0bc) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e0bc) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e0c0) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e0c0) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e0c0) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e0c4) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e0c4) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e0c4) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e0c8) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e0c8) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e0c8) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e0ec) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e0ec) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e0ec) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e0f0) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e0f0) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e0f0) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e0f4) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e0f4) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e0f4) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e0f8) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e0f8) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e0f8) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e0fc) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e0fc) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e0fc) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e100) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e100) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e100) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e104) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e104) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e104) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e108) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e108) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e108) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e010) +#define HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e010) +#define HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e010) +#define HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_RMSK 0x800000f3 +#define HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_ADDR, HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_IN) +#define HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_DIRTY_D_BMSK 0x80 +#define HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_DIRTY_D_SHFT 0x7 +#define HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_DIRTY_N_BMSK 0x40 +#define HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_DIRTY_N_SHFT 0x6 +#define HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_DIRTY_M_BMSK 0x20 +#define HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_DIRTY_M_SHFT 0x5 +#define HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e014) +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e014) +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e014) +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_RMSK 0x10371f +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_ADDR, HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_IN) +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_S0_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e018) +#define HWIO_GCC_QUPV3_WRAP2_S0_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e018) +#define HWIO_GCC_QUPV3_WRAP2_S0_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e018) +#define HWIO_GCC_QUPV3_WRAP2_S0_M_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_S0_M_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S0_M_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S0_M_ADDR, HWIO_GCC_QUPV3_WRAP2_S0_M_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S0_M_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S0_M_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S0_M_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S0_M_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S0_M_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S0_M_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S0_M_IN) +#define HWIO_GCC_QUPV3_WRAP2_S0_M_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_S0_M_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_S0_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e01c) +#define HWIO_GCC_QUPV3_WRAP2_S0_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e01c) +#define HWIO_GCC_QUPV3_WRAP2_S0_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e01c) +#define HWIO_GCC_QUPV3_WRAP2_S0_N_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_S0_N_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S0_N_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S0_N_ADDR, HWIO_GCC_QUPV3_WRAP2_S0_N_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S0_N_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S0_N_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S0_N_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S0_N_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S0_N_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S0_N_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S0_N_IN) +#define HWIO_GCC_QUPV3_WRAP2_S0_N_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_S0_N_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_S0_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e020) +#define HWIO_GCC_QUPV3_WRAP2_S0_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e020) +#define HWIO_GCC_QUPV3_WRAP2_S0_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e020) +#define HWIO_GCC_QUPV3_WRAP2_S0_D_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_S0_D_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S0_D_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S0_D_ADDR, HWIO_GCC_QUPV3_WRAP2_S0_D_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S0_D_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S0_D_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S0_D_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S0_D_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S0_D_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S0_D_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S0_D_IN) +#define HWIO_GCC_QUPV3_WRAP2_S0_D_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_S0_D_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_S1_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e13c) +#define HWIO_GCC_QUPV3_WRAP2_S1_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e13c) +#define HWIO_GCC_QUPV3_WRAP2_S1_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e13c) +#define HWIO_GCC_QUPV3_WRAP2_S1_CBCR_RMSK 0x81c07004 +#define HWIO_GCC_QUPV3_WRAP2_S1_CBCR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S1_CBCR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S1_CBCR_ADDR, HWIO_GCC_QUPV3_WRAP2_S1_CBCR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S1_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S1_CBCR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S1_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S1_CBCR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S1_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S1_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S1_CBCR_IN) +#define HWIO_GCC_QUPV3_WRAP2_S1_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_WRAP2_S1_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_WRAP2_S1_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QUPV3_WRAP2_S1_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP2_S1_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QUPV3_WRAP2_S1_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QUPV3_WRAP2_S1_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QUPV3_WRAP2_S1_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QUPV3_WRAP2_S1_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_QUPV3_WRAP2_S1_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_QUPV3_WRAP2_S1_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S1_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S1_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_QUPV3_WRAP2_S1_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_QUPV3_WRAP2_S1_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S1_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S1_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_QUPV3_WRAP2_S1_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_S1_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S1_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S1_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QUPV3_WRAP2_S1_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S1_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S1_CBCR_CLK_ARES_RESET_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e140) +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e140) +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e140) +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_RMSK 0xf1ffffe +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S1_SREGR_ADDR, HWIO_GCC_QUPV3_WRAP2_S1_SREGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S1_SREGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S1_SREGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S1_SREGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S1_SREGR_IN) +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xf000000 +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_PWR_FSM_CLK_SEL_BMSK 0x100000 +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_PWR_FSM_CLK_SEL_SHFT 0x14 +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xf0000 +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S1_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e144) +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e144) +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e144) +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_SREGR_RMSK 0xffffffff +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_SREGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_SREGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S1_CFG_SREGR_ADDR, HWIO_GCC_QUPV3_WRAP2_S1_CFG_SREGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S1_CFG_SREGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_SREGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S1_CFG_SREGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S1_CFG_SREGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S1_CFG_SREGR_IN) +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_SREGR_MEM_CORE_OFF_TIMER_BMSK 0xfc000000 +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_SREGR_MEM_CORE_OFF_TIMER_SHFT 0x1a +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_BMSK 0x2000000 +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_SHFT 0x19 +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_BMSK 0x1000000 +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_SREGR_MEM_PERIPH_ON_STATUS_BMSK 0x800000 +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_SREGR_MEM_PERIPH_ON_STATUS_SHFT 0x17 +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_SREGR_MEM_CORE_ON_STATUS_BMSK 0x400000 +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_SREGR_MEM_CORE_ON_STATUS_SHFT 0x16 +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_SREGR_MEM_CPH_TIMER_BMSK 0x3f0000 +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_SREGR_MEM_CPH_TIMER_SHFT 0x10 +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_SREGR_SLEEP_TIMER_BMSK 0xff00 +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_SREGR_SLEEP_TIMER_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_SREGR_WAKEUP_TIMER_BMSK 0xff +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_SREGR_WAKEUP_TIMER_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e15c) +#define HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e15c) +#define HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e15c) +#define HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_RCG_SW_CTRL_BMSK 0x8000 +#define HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_RCG_SW_CTRL_SHFT 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_SW_PERF_STATE_BMSK 0x7800 +#define HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_SW_PERF_STATE_SHFT 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_SW_OVERRIDE_BMSK 0x400 +#define HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_SW_OVERRIDE_SHFT 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK 0x200 +#define HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_DFS_FSM_STATE_BMSK 0x1c0 +#define HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_DFS_FSM_STATE_SHFT 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_HW_CLK_CONTROL_BMSK 0x20 +#define HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_HW_CLK_CONTROL_SHFT 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_CURR_PERF_STATE_BMSK 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_CURR_PERF_STATE_SHFT 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_DFS_EN_BMSK 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_DFS_EN_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_DFS_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_DFS_EN_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e164) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e164) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e164) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e168) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e168) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e168) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e16c) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e16c) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e16c) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e170) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e170) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e170) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e174) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e174) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e174) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e178) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e178) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e178) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e17c) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e17c) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e17c) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e180) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e180) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e180) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e1a4) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e1a4) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e1a4) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e1a8) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e1a8) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e1a8) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e1ac) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e1ac) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e1ac) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e1b0) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e1b0) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e1b0) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e1b4) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e1b4) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e1b4) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e1b8) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e1b8) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e1b8) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e1bc) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e1bc) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e1bc) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e1c0) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e1c0) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e1c0) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e1e4) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e1e4) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e1e4) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e1e8) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e1e8) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e1e8) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e1ec) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e1ec) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e1ec) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e1f0) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e1f0) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e1f0) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e1f4) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e1f4) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e1f4) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e1f8) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e1f8) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e1f8) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e1fc) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e1fc) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e1fc) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e200) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e200) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e200) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e224) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e224) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e224) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e228) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e228) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e228) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e22c) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e22c) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e22c) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e230) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e230) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e230) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e234) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e234) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e234) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e238) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e238) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e238) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e23c) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e23c) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e23c) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e240) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e240) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e240) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e148) +#define HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e148) +#define HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e148) +#define HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_RMSK 0x800000f3 +#define HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_ADDR, HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_IN) +#define HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_DIRTY_D_BMSK 0x80 +#define HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_DIRTY_D_SHFT 0x7 +#define HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_DIRTY_N_BMSK 0x40 +#define HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_DIRTY_N_SHFT 0x6 +#define HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_DIRTY_M_BMSK 0x20 +#define HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_DIRTY_M_SHFT 0x5 +#define HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e14c) +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e14c) +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e14c) +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_RMSK 0x10371f +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_ADDR, HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_IN) +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_S1_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e150) +#define HWIO_GCC_QUPV3_WRAP2_S1_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e150) +#define HWIO_GCC_QUPV3_WRAP2_S1_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e150) +#define HWIO_GCC_QUPV3_WRAP2_S1_M_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_S1_M_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S1_M_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S1_M_ADDR, HWIO_GCC_QUPV3_WRAP2_S1_M_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S1_M_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S1_M_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S1_M_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S1_M_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S1_M_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S1_M_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S1_M_IN) +#define HWIO_GCC_QUPV3_WRAP2_S1_M_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_S1_M_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_S1_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e154) +#define HWIO_GCC_QUPV3_WRAP2_S1_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e154) +#define HWIO_GCC_QUPV3_WRAP2_S1_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e154) +#define HWIO_GCC_QUPV3_WRAP2_S1_N_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_S1_N_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S1_N_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S1_N_ADDR, HWIO_GCC_QUPV3_WRAP2_S1_N_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S1_N_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S1_N_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S1_N_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S1_N_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S1_N_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S1_N_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S1_N_IN) +#define HWIO_GCC_QUPV3_WRAP2_S1_N_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_S1_N_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_S1_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e158) +#define HWIO_GCC_QUPV3_WRAP2_S1_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e158) +#define HWIO_GCC_QUPV3_WRAP2_S1_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e158) +#define HWIO_GCC_QUPV3_WRAP2_S1_D_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_S1_D_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S1_D_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S1_D_ADDR, HWIO_GCC_QUPV3_WRAP2_S1_D_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S1_D_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S1_D_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S1_D_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S1_D_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S1_D_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S1_D_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S1_D_IN) +#define HWIO_GCC_QUPV3_WRAP2_S1_D_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_S1_D_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_S2_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e274) +#define HWIO_GCC_QUPV3_WRAP2_S2_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e274) +#define HWIO_GCC_QUPV3_WRAP2_S2_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e274) +#define HWIO_GCC_QUPV3_WRAP2_S2_CBCR_RMSK 0x81c07004 +#define HWIO_GCC_QUPV3_WRAP2_S2_CBCR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S2_CBCR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S2_CBCR_ADDR, HWIO_GCC_QUPV3_WRAP2_S2_CBCR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S2_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S2_CBCR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S2_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S2_CBCR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S2_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S2_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S2_CBCR_IN) +#define HWIO_GCC_QUPV3_WRAP2_S2_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_WRAP2_S2_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_WRAP2_S2_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QUPV3_WRAP2_S2_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP2_S2_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QUPV3_WRAP2_S2_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QUPV3_WRAP2_S2_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QUPV3_WRAP2_S2_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QUPV3_WRAP2_S2_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_QUPV3_WRAP2_S2_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_QUPV3_WRAP2_S2_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S2_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S2_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_QUPV3_WRAP2_S2_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_QUPV3_WRAP2_S2_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S2_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S2_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_QUPV3_WRAP2_S2_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_S2_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S2_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S2_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QUPV3_WRAP2_S2_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S2_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S2_CBCR_CLK_ARES_RESET_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e278) +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e278) +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e278) +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_RMSK 0xf1ffffe +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S2_SREGR_ADDR, HWIO_GCC_QUPV3_WRAP2_S2_SREGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S2_SREGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S2_SREGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S2_SREGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S2_SREGR_IN) +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xf000000 +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_PWR_FSM_CLK_SEL_BMSK 0x100000 +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_PWR_FSM_CLK_SEL_SHFT 0x14 +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xf0000 +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S2_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e27c) +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e27c) +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e27c) +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_SREGR_RMSK 0xffffffff +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_SREGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_SREGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S2_CFG_SREGR_ADDR, HWIO_GCC_QUPV3_WRAP2_S2_CFG_SREGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S2_CFG_SREGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_SREGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S2_CFG_SREGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S2_CFG_SREGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S2_CFG_SREGR_IN) +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_SREGR_MEM_CORE_OFF_TIMER_BMSK 0xfc000000 +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_SREGR_MEM_CORE_OFF_TIMER_SHFT 0x1a +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_BMSK 0x2000000 +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_SHFT 0x19 +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_BMSK 0x1000000 +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_SREGR_MEM_PERIPH_ON_STATUS_BMSK 0x800000 +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_SREGR_MEM_PERIPH_ON_STATUS_SHFT 0x17 +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_SREGR_MEM_CORE_ON_STATUS_BMSK 0x400000 +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_SREGR_MEM_CORE_ON_STATUS_SHFT 0x16 +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_SREGR_MEM_CPH_TIMER_BMSK 0x3f0000 +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_SREGR_MEM_CPH_TIMER_SHFT 0x10 +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_SREGR_SLEEP_TIMER_BMSK 0xff00 +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_SREGR_SLEEP_TIMER_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_SREGR_WAKEUP_TIMER_BMSK 0xff +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_SREGR_WAKEUP_TIMER_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e294) +#define HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e294) +#define HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e294) +#define HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_RCG_SW_CTRL_BMSK 0x8000 +#define HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_RCG_SW_CTRL_SHFT 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_SW_PERF_STATE_BMSK 0x7800 +#define HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_SW_PERF_STATE_SHFT 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_SW_OVERRIDE_BMSK 0x400 +#define HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_SW_OVERRIDE_SHFT 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK 0x200 +#define HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_DFS_FSM_STATE_BMSK 0x1c0 +#define HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_DFS_FSM_STATE_SHFT 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_HW_CLK_CONTROL_BMSK 0x20 +#define HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_HW_CLK_CONTROL_SHFT 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_CURR_PERF_STATE_BMSK 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_CURR_PERF_STATE_SHFT 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_DFS_EN_BMSK 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_DFS_EN_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_DFS_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_DFS_EN_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e29c) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e29c) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e29c) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e2a0) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e2a0) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e2a0) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e2a4) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e2a4) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e2a4) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e2a8) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e2a8) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e2a8) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e2ac) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e2ac) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e2ac) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e2b0) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e2b0) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e2b0) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e2b4) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e2b4) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e2b4) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e2b8) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e2b8) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e2b8) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e2dc) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e2dc) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e2dc) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e2e0) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e2e0) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e2e0) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e2e4) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e2e4) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e2e4) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e2e8) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e2e8) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e2e8) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e2ec) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e2ec) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e2ec) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e2f0) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e2f0) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e2f0) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e2f4) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e2f4) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e2f4) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e2f8) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e2f8) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e2f8) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e31c) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e31c) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e31c) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e320) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e320) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e320) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e324) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e324) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e324) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e328) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e328) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e328) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e32c) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e32c) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e32c) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e330) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e330) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e330) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e334) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e334) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e334) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e338) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e338) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e338) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e35c) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e35c) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e35c) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e360) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e360) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e360) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e364) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e364) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e364) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e368) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e368) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e368) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e36c) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e36c) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e36c) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e370) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e370) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e370) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e374) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e374) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e374) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e378) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e378) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e378) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e280) +#define HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e280) +#define HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e280) +#define HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_RMSK 0x800000f3 +#define HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_ADDR, HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_IN) +#define HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_DIRTY_D_BMSK 0x80 +#define HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_DIRTY_D_SHFT 0x7 +#define HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_DIRTY_N_BMSK 0x40 +#define HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_DIRTY_N_SHFT 0x6 +#define HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_DIRTY_M_BMSK 0x20 +#define HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_DIRTY_M_SHFT 0x5 +#define HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e284) +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e284) +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e284) +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_RMSK 0x10371f +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_ADDR, HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_IN) +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_S2_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e288) +#define HWIO_GCC_QUPV3_WRAP2_S2_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e288) +#define HWIO_GCC_QUPV3_WRAP2_S2_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e288) +#define HWIO_GCC_QUPV3_WRAP2_S2_M_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_S2_M_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S2_M_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S2_M_ADDR, HWIO_GCC_QUPV3_WRAP2_S2_M_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S2_M_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S2_M_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S2_M_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S2_M_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S2_M_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S2_M_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S2_M_IN) +#define HWIO_GCC_QUPV3_WRAP2_S2_M_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_S2_M_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_S2_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e28c) +#define HWIO_GCC_QUPV3_WRAP2_S2_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e28c) +#define HWIO_GCC_QUPV3_WRAP2_S2_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e28c) +#define HWIO_GCC_QUPV3_WRAP2_S2_N_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_S2_N_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S2_N_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S2_N_ADDR, HWIO_GCC_QUPV3_WRAP2_S2_N_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S2_N_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S2_N_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S2_N_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S2_N_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S2_N_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S2_N_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S2_N_IN) +#define HWIO_GCC_QUPV3_WRAP2_S2_N_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_S2_N_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_S2_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e290) +#define HWIO_GCC_QUPV3_WRAP2_S2_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e290) +#define HWIO_GCC_QUPV3_WRAP2_S2_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e290) +#define HWIO_GCC_QUPV3_WRAP2_S2_D_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_S2_D_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S2_D_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S2_D_ADDR, HWIO_GCC_QUPV3_WRAP2_S2_D_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S2_D_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S2_D_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S2_D_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S2_D_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S2_D_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S2_D_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S2_D_IN) +#define HWIO_GCC_QUPV3_WRAP2_S2_D_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_S2_D_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_S3_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e3ac) +#define HWIO_GCC_QUPV3_WRAP2_S3_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e3ac) +#define HWIO_GCC_QUPV3_WRAP2_S3_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e3ac) +#define HWIO_GCC_QUPV3_WRAP2_S3_CBCR_RMSK 0x81c07004 +#define HWIO_GCC_QUPV3_WRAP2_S3_CBCR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S3_CBCR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S3_CBCR_ADDR, HWIO_GCC_QUPV3_WRAP2_S3_CBCR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S3_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S3_CBCR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S3_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S3_CBCR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S3_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S3_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S3_CBCR_IN) +#define HWIO_GCC_QUPV3_WRAP2_S3_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_WRAP2_S3_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_WRAP2_S3_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QUPV3_WRAP2_S3_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP2_S3_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QUPV3_WRAP2_S3_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QUPV3_WRAP2_S3_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QUPV3_WRAP2_S3_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QUPV3_WRAP2_S3_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_QUPV3_WRAP2_S3_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_QUPV3_WRAP2_S3_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S3_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S3_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_QUPV3_WRAP2_S3_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_QUPV3_WRAP2_S3_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S3_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S3_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_QUPV3_WRAP2_S3_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_S3_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S3_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S3_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QUPV3_WRAP2_S3_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S3_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S3_CBCR_CLK_ARES_RESET_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e3b0) +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e3b0) +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e3b0) +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_RMSK 0xf1ffffe +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S3_SREGR_ADDR, HWIO_GCC_QUPV3_WRAP2_S3_SREGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S3_SREGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S3_SREGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S3_SREGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S3_SREGR_IN) +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xf000000 +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_PWR_FSM_CLK_SEL_BMSK 0x100000 +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_PWR_FSM_CLK_SEL_SHFT 0x14 +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xf0000 +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S3_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e3b4) +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e3b4) +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e3b4) +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_SREGR_RMSK 0xffffffff +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_SREGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_SREGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S3_CFG_SREGR_ADDR, HWIO_GCC_QUPV3_WRAP2_S3_CFG_SREGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S3_CFG_SREGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_SREGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S3_CFG_SREGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S3_CFG_SREGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S3_CFG_SREGR_IN) +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_SREGR_MEM_CORE_OFF_TIMER_BMSK 0xfc000000 +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_SREGR_MEM_CORE_OFF_TIMER_SHFT 0x1a +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_BMSK 0x2000000 +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_SHFT 0x19 +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_BMSK 0x1000000 +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_SREGR_MEM_PERIPH_ON_STATUS_BMSK 0x800000 +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_SREGR_MEM_PERIPH_ON_STATUS_SHFT 0x17 +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_SREGR_MEM_CORE_ON_STATUS_BMSK 0x400000 +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_SREGR_MEM_CORE_ON_STATUS_SHFT 0x16 +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_SREGR_MEM_CPH_TIMER_BMSK 0x3f0000 +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_SREGR_MEM_CPH_TIMER_SHFT 0x10 +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_SREGR_SLEEP_TIMER_BMSK 0xff00 +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_SREGR_SLEEP_TIMER_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_SREGR_WAKEUP_TIMER_BMSK 0xff +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_SREGR_WAKEUP_TIMER_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e3cc) +#define HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e3cc) +#define HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e3cc) +#define HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_RCG_SW_CTRL_BMSK 0x8000 +#define HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_RCG_SW_CTRL_SHFT 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_SW_PERF_STATE_BMSK 0x7800 +#define HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_SW_PERF_STATE_SHFT 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_SW_OVERRIDE_BMSK 0x400 +#define HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_SW_OVERRIDE_SHFT 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK 0x200 +#define HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_DFS_FSM_STATE_BMSK 0x1c0 +#define HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_DFS_FSM_STATE_SHFT 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_HW_CLK_CONTROL_BMSK 0x20 +#define HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_HW_CLK_CONTROL_SHFT 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_CURR_PERF_STATE_BMSK 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_CURR_PERF_STATE_SHFT 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_DFS_EN_BMSK 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_DFS_EN_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_DFS_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_DFS_EN_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e3d4) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e3d4) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e3d4) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e3d8) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e3d8) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e3d8) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e3dc) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e3dc) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e3dc) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e3e0) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e3e0) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e3e0) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e3e4) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e3e4) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e3e4) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e3e8) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e3e8) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e3e8) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e3ec) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e3ec) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e3ec) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e3f0) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e3f0) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e3f0) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e414) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e414) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e414) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e418) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e418) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e418) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e41c) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e41c) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e41c) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e420) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e420) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e420) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e424) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e424) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e424) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e428) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e428) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e428) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e42c) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e42c) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e42c) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e430) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e430) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e430) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e454) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e454) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e454) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e458) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e458) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e458) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e45c) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e45c) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e45c) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e460) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e460) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e460) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e464) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e464) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e464) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e468) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e468) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e468) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e46c) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e46c) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e46c) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e470) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e470) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e470) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e494) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e494) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e494) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e498) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e498) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e498) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e49c) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e49c) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e49c) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e4a0) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e4a0) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e4a0) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e4a4) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e4a4) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e4a4) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e4a8) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e4a8) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e4a8) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e4ac) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e4ac) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e4ac) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e4b0) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e4b0) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e4b0) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e3b8) +#define HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e3b8) +#define HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e3b8) +#define HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_RMSK 0x800000f3 +#define HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_ADDR, HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_IN) +#define HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_DIRTY_D_BMSK 0x80 +#define HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_DIRTY_D_SHFT 0x7 +#define HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_DIRTY_N_BMSK 0x40 +#define HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_DIRTY_N_SHFT 0x6 +#define HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_DIRTY_M_BMSK 0x20 +#define HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_DIRTY_M_SHFT 0x5 +#define HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e3bc) +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e3bc) +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e3bc) +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_RMSK 0x10371f +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_ADDR, HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_IN) +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_S3_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e3c0) +#define HWIO_GCC_QUPV3_WRAP2_S3_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e3c0) +#define HWIO_GCC_QUPV3_WRAP2_S3_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e3c0) +#define HWIO_GCC_QUPV3_WRAP2_S3_M_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_S3_M_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S3_M_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S3_M_ADDR, HWIO_GCC_QUPV3_WRAP2_S3_M_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S3_M_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S3_M_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S3_M_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S3_M_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S3_M_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S3_M_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S3_M_IN) +#define HWIO_GCC_QUPV3_WRAP2_S3_M_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_S3_M_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_S3_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e3c4) +#define HWIO_GCC_QUPV3_WRAP2_S3_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e3c4) +#define HWIO_GCC_QUPV3_WRAP2_S3_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e3c4) +#define HWIO_GCC_QUPV3_WRAP2_S3_N_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_S3_N_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S3_N_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S3_N_ADDR, HWIO_GCC_QUPV3_WRAP2_S3_N_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S3_N_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S3_N_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S3_N_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S3_N_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S3_N_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S3_N_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S3_N_IN) +#define HWIO_GCC_QUPV3_WRAP2_S3_N_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_S3_N_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_S3_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e3c8) +#define HWIO_GCC_QUPV3_WRAP2_S3_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e3c8) +#define HWIO_GCC_QUPV3_WRAP2_S3_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e3c8) +#define HWIO_GCC_QUPV3_WRAP2_S3_D_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_S3_D_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S3_D_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S3_D_ADDR, HWIO_GCC_QUPV3_WRAP2_S3_D_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S3_D_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S3_D_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S3_D_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S3_D_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S3_D_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S3_D_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S3_D_IN) +#define HWIO_GCC_QUPV3_WRAP2_S3_D_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_S3_D_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_S4_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e4e4) +#define HWIO_GCC_QUPV3_WRAP2_S4_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e4e4) +#define HWIO_GCC_QUPV3_WRAP2_S4_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e4e4) +#define HWIO_GCC_QUPV3_WRAP2_S4_CBCR_RMSK 0x81c07004 +#define HWIO_GCC_QUPV3_WRAP2_S4_CBCR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S4_CBCR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S4_CBCR_ADDR, HWIO_GCC_QUPV3_WRAP2_S4_CBCR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S4_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S4_CBCR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S4_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S4_CBCR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S4_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S4_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S4_CBCR_IN) +#define HWIO_GCC_QUPV3_WRAP2_S4_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_WRAP2_S4_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_WRAP2_S4_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QUPV3_WRAP2_S4_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP2_S4_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QUPV3_WRAP2_S4_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QUPV3_WRAP2_S4_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QUPV3_WRAP2_S4_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QUPV3_WRAP2_S4_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_QUPV3_WRAP2_S4_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_QUPV3_WRAP2_S4_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S4_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S4_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_QUPV3_WRAP2_S4_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_QUPV3_WRAP2_S4_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S4_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S4_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_QUPV3_WRAP2_S4_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_S4_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S4_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S4_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QUPV3_WRAP2_S4_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S4_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S4_CBCR_CLK_ARES_RESET_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e4e8) +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e4e8) +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e4e8) +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_RMSK 0xf1ffffe +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S4_SREGR_ADDR, HWIO_GCC_QUPV3_WRAP2_S4_SREGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S4_SREGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S4_SREGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S4_SREGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S4_SREGR_IN) +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xf000000 +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_PWR_FSM_CLK_SEL_BMSK 0x100000 +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_PWR_FSM_CLK_SEL_SHFT 0x14 +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xf0000 +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S4_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e4ec) +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e4ec) +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e4ec) +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_SREGR_RMSK 0xffffffff +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_SREGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_SREGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S4_CFG_SREGR_ADDR, HWIO_GCC_QUPV3_WRAP2_S4_CFG_SREGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S4_CFG_SREGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_SREGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S4_CFG_SREGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S4_CFG_SREGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S4_CFG_SREGR_IN) +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_SREGR_MEM_CORE_OFF_TIMER_BMSK 0xfc000000 +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_SREGR_MEM_CORE_OFF_TIMER_SHFT 0x1a +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_BMSK 0x2000000 +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_SHFT 0x19 +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_BMSK 0x1000000 +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_SREGR_MEM_PERIPH_ON_STATUS_BMSK 0x800000 +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_SREGR_MEM_PERIPH_ON_STATUS_SHFT 0x17 +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_SREGR_MEM_CORE_ON_STATUS_BMSK 0x400000 +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_SREGR_MEM_CORE_ON_STATUS_SHFT 0x16 +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_SREGR_MEM_CPH_TIMER_BMSK 0x3f0000 +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_SREGR_MEM_CPH_TIMER_SHFT 0x10 +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_SREGR_SLEEP_TIMER_BMSK 0xff00 +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_SREGR_SLEEP_TIMER_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_SREGR_WAKEUP_TIMER_BMSK 0xff +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_SREGR_WAKEUP_TIMER_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e504) +#define HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e504) +#define HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e504) +#define HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_RCG_SW_CTRL_BMSK 0x8000 +#define HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_RCG_SW_CTRL_SHFT 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_SW_PERF_STATE_BMSK 0x7800 +#define HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_SW_PERF_STATE_SHFT 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_SW_OVERRIDE_BMSK 0x400 +#define HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_SW_OVERRIDE_SHFT 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK 0x200 +#define HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_DFS_FSM_STATE_BMSK 0x1c0 +#define HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_DFS_FSM_STATE_SHFT 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_HW_CLK_CONTROL_BMSK 0x20 +#define HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_HW_CLK_CONTROL_SHFT 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_CURR_PERF_STATE_BMSK 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_CURR_PERF_STATE_SHFT 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_DFS_EN_BMSK 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_DFS_EN_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_DFS_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_DFS_EN_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e50c) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e50c) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e50c) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e510) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e510) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e510) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e514) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e514) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e514) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e518) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e518) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e518) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e51c) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e51c) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e51c) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e520) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e520) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e520) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e524) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e524) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e524) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e528) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e528) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e528) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e54c) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e54c) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e54c) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e550) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e550) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e550) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e554) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e554) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e554) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e558) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e558) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e558) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e55c) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e55c) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e55c) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e560) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e560) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e560) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e564) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e564) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e564) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e568) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e568) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e568) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e58c) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e58c) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e58c) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e590) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e590) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e590) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e594) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e594) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e594) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e598) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e598) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e598) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e59c) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e59c) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e59c) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e5a0) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e5a0) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e5a0) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e5a4) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e5a4) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e5a4) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e5a8) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e5a8) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e5a8) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e5cc) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e5cc) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e5cc) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e5d0) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e5d0) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e5d0) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e5d4) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e5d4) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e5d4) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e5d8) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e5d8) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e5d8) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e5dc) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e5dc) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e5dc) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e5e0) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e5e0) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e5e0) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e5e4) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e5e4) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e5e4) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e5e8) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e5e8) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e5e8) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e4f0) +#define HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e4f0) +#define HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e4f0) +#define HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_RMSK 0x800000f3 +#define HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_ADDR, HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_IN) +#define HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_DIRTY_D_BMSK 0x80 +#define HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_DIRTY_D_SHFT 0x7 +#define HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_DIRTY_N_BMSK 0x40 +#define HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_DIRTY_N_SHFT 0x6 +#define HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_DIRTY_M_BMSK 0x20 +#define HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_DIRTY_M_SHFT 0x5 +#define HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e4f4) +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e4f4) +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e4f4) +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_RMSK 0x10371f +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_ADDR, HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_IN) +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_S4_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e4f8) +#define HWIO_GCC_QUPV3_WRAP2_S4_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e4f8) +#define HWIO_GCC_QUPV3_WRAP2_S4_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e4f8) +#define HWIO_GCC_QUPV3_WRAP2_S4_M_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_S4_M_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S4_M_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S4_M_ADDR, HWIO_GCC_QUPV3_WRAP2_S4_M_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S4_M_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S4_M_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S4_M_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S4_M_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S4_M_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S4_M_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S4_M_IN) +#define HWIO_GCC_QUPV3_WRAP2_S4_M_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_S4_M_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_S4_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e4fc) +#define HWIO_GCC_QUPV3_WRAP2_S4_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e4fc) +#define HWIO_GCC_QUPV3_WRAP2_S4_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e4fc) +#define HWIO_GCC_QUPV3_WRAP2_S4_N_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_S4_N_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S4_N_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S4_N_ADDR, HWIO_GCC_QUPV3_WRAP2_S4_N_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S4_N_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S4_N_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S4_N_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S4_N_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S4_N_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S4_N_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S4_N_IN) +#define HWIO_GCC_QUPV3_WRAP2_S4_N_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_S4_N_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_S4_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e500) +#define HWIO_GCC_QUPV3_WRAP2_S4_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e500) +#define HWIO_GCC_QUPV3_WRAP2_S4_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e500) +#define HWIO_GCC_QUPV3_WRAP2_S4_D_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_S4_D_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S4_D_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S4_D_ADDR, HWIO_GCC_QUPV3_WRAP2_S4_D_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S4_D_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S4_D_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S4_D_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S4_D_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S4_D_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S4_D_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S4_D_IN) +#define HWIO_GCC_QUPV3_WRAP2_S4_D_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_S4_D_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_S5_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e61c) +#define HWIO_GCC_QUPV3_WRAP2_S5_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e61c) +#define HWIO_GCC_QUPV3_WRAP2_S5_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e61c) +#define HWIO_GCC_QUPV3_WRAP2_S5_CBCR_RMSK 0x81c07004 +#define HWIO_GCC_QUPV3_WRAP2_S5_CBCR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S5_CBCR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S5_CBCR_ADDR, HWIO_GCC_QUPV3_WRAP2_S5_CBCR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S5_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S5_CBCR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S5_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S5_CBCR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S5_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S5_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S5_CBCR_IN) +#define HWIO_GCC_QUPV3_WRAP2_S5_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_WRAP2_S5_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_WRAP2_S5_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QUPV3_WRAP2_S5_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP2_S5_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QUPV3_WRAP2_S5_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QUPV3_WRAP2_S5_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QUPV3_WRAP2_S5_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QUPV3_WRAP2_S5_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_QUPV3_WRAP2_S5_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_QUPV3_WRAP2_S5_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S5_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S5_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_QUPV3_WRAP2_S5_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_QUPV3_WRAP2_S5_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S5_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S5_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_QUPV3_WRAP2_S5_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_S5_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S5_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S5_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QUPV3_WRAP2_S5_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S5_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S5_CBCR_CLK_ARES_RESET_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e620) +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e620) +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e620) +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_RMSK 0xf1ffffe +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S5_SREGR_ADDR, HWIO_GCC_QUPV3_WRAP2_S5_SREGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S5_SREGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S5_SREGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S5_SREGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S5_SREGR_IN) +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xf000000 +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_PWR_FSM_CLK_SEL_BMSK 0x100000 +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_PWR_FSM_CLK_SEL_SHFT 0x14 +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xf0000 +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S5_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e624) +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e624) +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e624) +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_SREGR_RMSK 0xffffffff +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_SREGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_SREGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S5_CFG_SREGR_ADDR, HWIO_GCC_QUPV3_WRAP2_S5_CFG_SREGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S5_CFG_SREGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_SREGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S5_CFG_SREGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S5_CFG_SREGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S5_CFG_SREGR_IN) +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_SREGR_MEM_CORE_OFF_TIMER_BMSK 0xfc000000 +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_SREGR_MEM_CORE_OFF_TIMER_SHFT 0x1a +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_BMSK 0x2000000 +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_SHFT 0x19 +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_BMSK 0x1000000 +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_SREGR_MEM_PERIPH_ON_STATUS_BMSK 0x800000 +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_SREGR_MEM_PERIPH_ON_STATUS_SHFT 0x17 +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_SREGR_MEM_CORE_ON_STATUS_BMSK 0x400000 +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_SREGR_MEM_CORE_ON_STATUS_SHFT 0x16 +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_SREGR_MEM_CPH_TIMER_BMSK 0x3f0000 +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_SREGR_MEM_CPH_TIMER_SHFT 0x10 +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_SREGR_SLEEP_TIMER_BMSK 0xff00 +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_SREGR_SLEEP_TIMER_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_SREGR_WAKEUP_TIMER_BMSK 0xff +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_SREGR_WAKEUP_TIMER_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e63c) +#define HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e63c) +#define HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e63c) +#define HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_RCG_SW_CTRL_BMSK 0x8000 +#define HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_RCG_SW_CTRL_SHFT 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_SW_PERF_STATE_BMSK 0x7800 +#define HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_SW_PERF_STATE_SHFT 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_SW_OVERRIDE_BMSK 0x400 +#define HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_SW_OVERRIDE_SHFT 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK 0x200 +#define HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_DFS_FSM_STATE_BMSK 0x1c0 +#define HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_DFS_FSM_STATE_SHFT 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_HW_CLK_CONTROL_BMSK 0x20 +#define HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_HW_CLK_CONTROL_SHFT 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_CURR_PERF_STATE_BMSK 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_CURR_PERF_STATE_SHFT 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_DFS_EN_BMSK 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_DFS_EN_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_DFS_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_DFS_EN_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e644) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e644) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e644) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e648) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e648) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e648) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e64c) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e64c) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e64c) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e650) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e650) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e650) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e654) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e654) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e654) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e658) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e658) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e658) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e65c) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e65c) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e65c) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e660) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e660) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e660) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e684) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e684) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e684) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e688) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e688) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e688) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e68c) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e68c) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e68c) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e690) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e690) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e690) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e694) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e694) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e694) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e698) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e698) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e698) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e69c) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e69c) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e69c) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e6a0) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e6a0) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e6a0) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e6c4) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e6c4) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e6c4) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e6c8) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e6c8) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e6c8) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e6cc) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e6cc) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e6cc) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e6d0) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e6d0) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e6d0) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e6d4) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e6d4) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e6d4) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e6d8) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e6d8) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e6d8) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e6dc) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e6dc) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e6dc) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e6e0) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e6e0) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e6e0) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e704) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e704) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e704) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e708) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e708) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e708) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e70c) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e70c) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e70c) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e710) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e710) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e710) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e714) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e714) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e714) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e718) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e718) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e718) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e71c) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e71c) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e71c) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e720) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e720) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e720) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e628) +#define HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e628) +#define HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e628) +#define HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_RMSK 0x800000f3 +#define HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_ADDR, HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_IN) +#define HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_DIRTY_D_BMSK 0x80 +#define HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_DIRTY_D_SHFT 0x7 +#define HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_DIRTY_N_BMSK 0x40 +#define HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_DIRTY_N_SHFT 0x6 +#define HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_DIRTY_M_BMSK 0x20 +#define HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_DIRTY_M_SHFT 0x5 +#define HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e62c) +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e62c) +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e62c) +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_RMSK 0x10371f +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_ADDR, HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_IN) +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_S5_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e630) +#define HWIO_GCC_QUPV3_WRAP2_S5_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e630) +#define HWIO_GCC_QUPV3_WRAP2_S5_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e630) +#define HWIO_GCC_QUPV3_WRAP2_S5_M_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_S5_M_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S5_M_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S5_M_ADDR, HWIO_GCC_QUPV3_WRAP2_S5_M_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S5_M_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S5_M_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S5_M_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S5_M_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S5_M_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S5_M_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S5_M_IN) +#define HWIO_GCC_QUPV3_WRAP2_S5_M_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_S5_M_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_S5_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e634) +#define HWIO_GCC_QUPV3_WRAP2_S5_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e634) +#define HWIO_GCC_QUPV3_WRAP2_S5_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e634) +#define HWIO_GCC_QUPV3_WRAP2_S5_N_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_S5_N_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S5_N_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S5_N_ADDR, HWIO_GCC_QUPV3_WRAP2_S5_N_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S5_N_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S5_N_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S5_N_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S5_N_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S5_N_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S5_N_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S5_N_IN) +#define HWIO_GCC_QUPV3_WRAP2_S5_N_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_S5_N_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_S5_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e638) +#define HWIO_GCC_QUPV3_WRAP2_S5_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e638) +#define HWIO_GCC_QUPV3_WRAP2_S5_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e638) +#define HWIO_GCC_QUPV3_WRAP2_S5_D_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_S5_D_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S5_D_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S5_D_ADDR, HWIO_GCC_QUPV3_WRAP2_S5_D_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S5_D_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S5_D_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S5_D_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S5_D_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S5_D_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S5_D_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S5_D_IN) +#define HWIO_GCC_QUPV3_WRAP2_S5_D_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_S5_D_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_S6_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e754) +#define HWIO_GCC_QUPV3_WRAP2_S6_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e754) +#define HWIO_GCC_QUPV3_WRAP2_S6_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e754) +#define HWIO_GCC_QUPV3_WRAP2_S6_CBCR_RMSK 0x81c07004 +#define HWIO_GCC_QUPV3_WRAP2_S6_CBCR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S6_CBCR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S6_CBCR_ADDR, HWIO_GCC_QUPV3_WRAP2_S6_CBCR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S6_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S6_CBCR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S6_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S6_CBCR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S6_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S6_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S6_CBCR_IN) +#define HWIO_GCC_QUPV3_WRAP2_S6_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_WRAP2_S6_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_WRAP2_S6_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QUPV3_WRAP2_S6_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP2_S6_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QUPV3_WRAP2_S6_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QUPV3_WRAP2_S6_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QUPV3_WRAP2_S6_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QUPV3_WRAP2_S6_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_QUPV3_WRAP2_S6_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_QUPV3_WRAP2_S6_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S6_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S6_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_QUPV3_WRAP2_S6_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_QUPV3_WRAP2_S6_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S6_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S6_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_QUPV3_WRAP2_S6_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_S6_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S6_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S6_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QUPV3_WRAP2_S6_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S6_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S6_CBCR_CLK_ARES_RESET_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e758) +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e758) +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e758) +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_RMSK 0xf1ffffe +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S6_SREGR_ADDR, HWIO_GCC_QUPV3_WRAP2_S6_SREGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S6_SREGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S6_SREGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S6_SREGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S6_SREGR_IN) +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xf000000 +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_PWR_FSM_CLK_SEL_BMSK 0x100000 +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_PWR_FSM_CLK_SEL_SHFT 0x14 +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xf0000 +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S6_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e75c) +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e75c) +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e75c) +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_SREGR_RMSK 0xffffffff +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_SREGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_SREGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S6_CFG_SREGR_ADDR, HWIO_GCC_QUPV3_WRAP2_S6_CFG_SREGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S6_CFG_SREGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_SREGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S6_CFG_SREGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S6_CFG_SREGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S6_CFG_SREGR_IN) +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_SREGR_MEM_CORE_OFF_TIMER_BMSK 0xfc000000 +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_SREGR_MEM_CORE_OFF_TIMER_SHFT 0x1a +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_BMSK 0x2000000 +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_SHFT 0x19 +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_BMSK 0x1000000 +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_SREGR_MEM_PERIPH_ON_STATUS_BMSK 0x800000 +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_SREGR_MEM_PERIPH_ON_STATUS_SHFT 0x17 +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_SREGR_MEM_CORE_ON_STATUS_BMSK 0x400000 +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_SREGR_MEM_CORE_ON_STATUS_SHFT 0x16 +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_SREGR_MEM_CPH_TIMER_BMSK 0x3f0000 +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_SREGR_MEM_CPH_TIMER_SHFT 0x10 +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_SREGR_SLEEP_TIMER_BMSK 0xff00 +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_SREGR_SLEEP_TIMER_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_SREGR_WAKEUP_TIMER_BMSK 0xff +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_SREGR_WAKEUP_TIMER_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE6_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e774) +#define HWIO_GCC_QUPV3_WRAP2_SE6_CMD_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e774) +#define HWIO_GCC_QUPV3_WRAP2_SE6_CMD_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e774) +#define HWIO_GCC_QUPV3_WRAP2_SE6_CMD_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE6_CMD_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE6_CMD_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_CMD_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE6_CMD_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE6_CMD_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_CMD_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE6_CMD_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE6_CMD_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE6_CMD_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE6_CMD_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE6_CMD_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE6_CMD_DFSR_RCG_SW_CTRL_BMSK 0x8000 +#define HWIO_GCC_QUPV3_WRAP2_SE6_CMD_DFSR_RCG_SW_CTRL_SHFT 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE6_CMD_DFSR_SW_PERF_STATE_BMSK 0x7800 +#define HWIO_GCC_QUPV3_WRAP2_SE6_CMD_DFSR_SW_PERF_STATE_SHFT 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE6_CMD_DFSR_SW_OVERRIDE_BMSK 0x400 +#define HWIO_GCC_QUPV3_WRAP2_SE6_CMD_DFSR_SW_OVERRIDE_SHFT 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE6_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK 0x200 +#define HWIO_GCC_QUPV3_WRAP2_SE6_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE6_CMD_DFSR_DFS_FSM_STATE_BMSK 0x1c0 +#define HWIO_GCC_QUPV3_WRAP2_SE6_CMD_DFSR_DFS_FSM_STATE_SHFT 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE6_CMD_DFSR_HW_CLK_CONTROL_BMSK 0x20 +#define HWIO_GCC_QUPV3_WRAP2_SE6_CMD_DFSR_HW_CLK_CONTROL_SHFT 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE6_CMD_DFSR_CURR_PERF_STATE_BMSK 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE6_CMD_DFSR_CURR_PERF_STATE_SHFT 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE6_CMD_DFSR_DFS_EN_BMSK 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE6_CMD_DFSR_DFS_EN_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE6_CMD_DFSR_DFS_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE6_CMD_DFSR_DFS_EN_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e77c) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e77c) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e77c) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e780) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e780) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e780) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e784) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e784) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e784) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e788) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e788) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e788) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e78c) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e78c) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e78c) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e790) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e790) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e790) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e794) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e794) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e794) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e798) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e798) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e798) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e7bc) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e7bc) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e7bc) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e7c0) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e7c0) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e7c0) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e7c4) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e7c4) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e7c4) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e7c8) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e7c8) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e7c8) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e7cc) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e7cc) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e7cc) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e7d0) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e7d0) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e7d0) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e7d4) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e7d4) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e7d4) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e7d8) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e7d8) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e7d8) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e7fc) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e7fc) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e7fc) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e800) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e800) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e800) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e804) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e804) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e804) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e808) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e808) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e808) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e80c) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e80c) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e80c) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e810) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e810) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e810) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e814) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e814) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e814) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e818) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e818) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e818) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e83c) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e83c) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e83c) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e840) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e840) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e840) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e844) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e844) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e844) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e848) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e848) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e848) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e84c) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e84c) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e84c) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e850) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e850) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e850) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e854) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e854) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e854) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e858) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e858) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e858) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_S6_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e760) +#define HWIO_GCC_QUPV3_WRAP2_S6_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e760) +#define HWIO_GCC_QUPV3_WRAP2_S6_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e760) +#define HWIO_GCC_QUPV3_WRAP2_S6_CMD_RCGR_RMSK 0x800000f3 +#define HWIO_GCC_QUPV3_WRAP2_S6_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S6_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S6_CMD_RCGR_ADDR, HWIO_GCC_QUPV3_WRAP2_S6_CMD_RCGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S6_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S6_CMD_RCGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S6_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S6_CMD_RCGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S6_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S6_CMD_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S6_CMD_RCGR_IN) +#define HWIO_GCC_QUPV3_WRAP2_S6_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_WRAP2_S6_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_WRAP2_S6_CMD_RCGR_DIRTY_D_BMSK 0x80 +#define HWIO_GCC_QUPV3_WRAP2_S6_CMD_RCGR_DIRTY_D_SHFT 0x7 +#define HWIO_GCC_QUPV3_WRAP2_S6_CMD_RCGR_DIRTY_N_BMSK 0x40 +#define HWIO_GCC_QUPV3_WRAP2_S6_CMD_RCGR_DIRTY_N_SHFT 0x6 +#define HWIO_GCC_QUPV3_WRAP2_S6_CMD_RCGR_DIRTY_M_BMSK 0x20 +#define HWIO_GCC_QUPV3_WRAP2_S6_CMD_RCGR_DIRTY_M_SHFT 0x5 +#define HWIO_GCC_QUPV3_WRAP2_S6_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_QUPV3_WRAP2_S6_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_QUPV3_WRAP2_S6_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S6_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S6_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S6_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S6_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S6_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S6_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S6_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e764) +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e764) +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e764) +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_RMSK 0x10371f +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_ADDR, HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_IN) +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_S6_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_S6_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e768) +#define HWIO_GCC_QUPV3_WRAP2_S6_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e768) +#define HWIO_GCC_QUPV3_WRAP2_S6_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e768) +#define HWIO_GCC_QUPV3_WRAP2_S6_M_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_S6_M_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S6_M_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S6_M_ADDR, HWIO_GCC_QUPV3_WRAP2_S6_M_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S6_M_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S6_M_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S6_M_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S6_M_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S6_M_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S6_M_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S6_M_IN) +#define HWIO_GCC_QUPV3_WRAP2_S6_M_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_S6_M_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_S6_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e76c) +#define HWIO_GCC_QUPV3_WRAP2_S6_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e76c) +#define HWIO_GCC_QUPV3_WRAP2_S6_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e76c) +#define HWIO_GCC_QUPV3_WRAP2_S6_N_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_S6_N_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S6_N_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S6_N_ADDR, HWIO_GCC_QUPV3_WRAP2_S6_N_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S6_N_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S6_N_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S6_N_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S6_N_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S6_N_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S6_N_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S6_N_IN) +#define HWIO_GCC_QUPV3_WRAP2_S6_N_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_S6_N_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_S6_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e770) +#define HWIO_GCC_QUPV3_WRAP2_S6_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e770) +#define HWIO_GCC_QUPV3_WRAP2_S6_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e770) +#define HWIO_GCC_QUPV3_WRAP2_S6_D_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_S6_D_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S6_D_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S6_D_ADDR, HWIO_GCC_QUPV3_WRAP2_S6_D_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S6_D_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S6_D_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S6_D_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S6_D_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S6_D_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S6_D_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S6_D_IN) +#define HWIO_GCC_QUPV3_WRAP2_S6_D_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_S6_D_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_S7_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e88c) +#define HWIO_GCC_QUPV3_WRAP2_S7_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e88c) +#define HWIO_GCC_QUPV3_WRAP2_S7_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e88c) +#define HWIO_GCC_QUPV3_WRAP2_S7_CBCR_RMSK 0x81c07004 +#define HWIO_GCC_QUPV3_WRAP2_S7_CBCR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S7_CBCR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S7_CBCR_ADDR, HWIO_GCC_QUPV3_WRAP2_S7_CBCR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S7_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S7_CBCR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S7_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S7_CBCR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S7_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S7_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S7_CBCR_IN) +#define HWIO_GCC_QUPV3_WRAP2_S7_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_WRAP2_S7_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_WRAP2_S7_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QUPV3_WRAP2_S7_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP2_S7_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QUPV3_WRAP2_S7_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QUPV3_WRAP2_S7_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QUPV3_WRAP2_S7_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QUPV3_WRAP2_S7_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_QUPV3_WRAP2_S7_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_QUPV3_WRAP2_S7_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S7_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S7_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_QUPV3_WRAP2_S7_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_QUPV3_WRAP2_S7_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S7_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S7_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_QUPV3_WRAP2_S7_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_S7_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S7_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S7_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QUPV3_WRAP2_S7_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S7_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S7_CBCR_CLK_ARES_RESET_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e890) +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e890) +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e890) +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_RMSK 0xf1ffffe +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S7_SREGR_ADDR, HWIO_GCC_QUPV3_WRAP2_S7_SREGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S7_SREGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S7_SREGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S7_SREGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S7_SREGR_IN) +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xf000000 +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_PWR_FSM_CLK_SEL_BMSK 0x100000 +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_PWR_FSM_CLK_SEL_SHFT 0x14 +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xf0000 +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S7_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e894) +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e894) +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e894) +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_SREGR_RMSK 0xffffffff +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_SREGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_SREGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S7_CFG_SREGR_ADDR, HWIO_GCC_QUPV3_WRAP2_S7_CFG_SREGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S7_CFG_SREGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_SREGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S7_CFG_SREGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S7_CFG_SREGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S7_CFG_SREGR_IN) +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_SREGR_MEM_CORE_OFF_TIMER_BMSK 0xfc000000 +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_SREGR_MEM_CORE_OFF_TIMER_SHFT 0x1a +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_BMSK 0x2000000 +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_SHFT 0x19 +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_BMSK 0x1000000 +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_SHFT 0x18 +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_SREGR_MEM_PERIPH_ON_STATUS_BMSK 0x800000 +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_SREGR_MEM_PERIPH_ON_STATUS_SHFT 0x17 +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_SREGR_MEM_CORE_ON_STATUS_BMSK 0x400000 +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_SREGR_MEM_CORE_ON_STATUS_SHFT 0x16 +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_SREGR_MEM_CPH_TIMER_BMSK 0x3f0000 +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_SREGR_MEM_CPH_TIMER_SHFT 0x10 +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_SREGR_SLEEP_TIMER_BMSK 0xff00 +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_SREGR_SLEEP_TIMER_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_SREGR_WAKEUP_TIMER_BMSK 0xff +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_SREGR_WAKEUP_TIMER_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE7_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e8ac) +#define HWIO_GCC_QUPV3_WRAP2_SE7_CMD_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e8ac) +#define HWIO_GCC_QUPV3_WRAP2_SE7_CMD_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e8ac) +#define HWIO_GCC_QUPV3_WRAP2_SE7_CMD_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE7_CMD_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE7_CMD_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_CMD_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE7_CMD_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE7_CMD_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_CMD_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE7_CMD_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE7_CMD_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE7_CMD_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE7_CMD_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE7_CMD_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE7_CMD_DFSR_RCG_SW_CTRL_BMSK 0x8000 +#define HWIO_GCC_QUPV3_WRAP2_SE7_CMD_DFSR_RCG_SW_CTRL_SHFT 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE7_CMD_DFSR_SW_PERF_STATE_BMSK 0x7800 +#define HWIO_GCC_QUPV3_WRAP2_SE7_CMD_DFSR_SW_PERF_STATE_SHFT 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE7_CMD_DFSR_SW_OVERRIDE_BMSK 0x400 +#define HWIO_GCC_QUPV3_WRAP2_SE7_CMD_DFSR_SW_OVERRIDE_SHFT 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE7_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK 0x200 +#define HWIO_GCC_QUPV3_WRAP2_SE7_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE7_CMD_DFSR_DFS_FSM_STATE_BMSK 0x1c0 +#define HWIO_GCC_QUPV3_WRAP2_SE7_CMD_DFSR_DFS_FSM_STATE_SHFT 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE7_CMD_DFSR_HW_CLK_CONTROL_BMSK 0x20 +#define HWIO_GCC_QUPV3_WRAP2_SE7_CMD_DFSR_HW_CLK_CONTROL_SHFT 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE7_CMD_DFSR_CURR_PERF_STATE_BMSK 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE7_CMD_DFSR_CURR_PERF_STATE_SHFT 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE7_CMD_DFSR_DFS_EN_BMSK 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE7_CMD_DFSR_DFS_EN_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE7_CMD_DFSR_DFS_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE7_CMD_DFSR_DFS_EN_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e8b4) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e8b4) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e8b4) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e8b8) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e8b8) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e8b8) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e8bc) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e8bc) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e8bc) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e8c0) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e8c0) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e8c0) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e8c4) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e8c4) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e8c4) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e8c8) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e8c8) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e8c8) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e8cc) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e8cc) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e8cc) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e8d0) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e8d0) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e8d0) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_RMSK 0x371f +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e8f4) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e8f4) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e8f4) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e8f8) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e8f8) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e8f8) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e8fc) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e8fc) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e8fc) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e900) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e900) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e900) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e904) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e904) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e904) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e908) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e908) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e908) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e90c) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e90c) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e90c) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_M_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e910) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_M_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e910) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_M_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e910) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_M_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_M_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_M_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_M_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_M_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_M_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_M_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_M_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_M_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_M_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_M_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_M_DFSR_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_M_DFSR_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e934) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e934) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e934) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e938) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e938) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e938) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e93c) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e93c) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e93c) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e940) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e940) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e940) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e944) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e944) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e944) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e948) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e948) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e948) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e94c) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e94c) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e94c) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_N_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e950) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_N_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e950) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_N_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e950) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_N_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_N_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_N_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_N_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_N_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_N_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_N_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_N_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_N_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_N_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_N_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_N_DFSR_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_N_DFSR_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e974) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e974) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e974) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e978) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e978) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e978) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e97c) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e97c) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e97c) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e980) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e980) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e980) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e984) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e984) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e984) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e988) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e988) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e988) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e98c) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e98c) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e98c) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_D_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e990) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_D_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e990) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_D_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e990) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_D_DFSR_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_D_DFSR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_D_DFSR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_D_DFSR_ADDR, HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_D_DFSR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_D_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_D_DFSR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_D_DFSR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_D_DFSR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_D_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_D_DFSR_IN) +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_D_DFSR_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_D_DFSR_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_S7_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e898) +#define HWIO_GCC_QUPV3_WRAP2_S7_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e898) +#define HWIO_GCC_QUPV3_WRAP2_S7_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e898) +#define HWIO_GCC_QUPV3_WRAP2_S7_CMD_RCGR_RMSK 0x800000f3 +#define HWIO_GCC_QUPV3_WRAP2_S7_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S7_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S7_CMD_RCGR_ADDR, HWIO_GCC_QUPV3_WRAP2_S7_CMD_RCGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S7_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S7_CMD_RCGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S7_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S7_CMD_RCGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S7_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S7_CMD_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S7_CMD_RCGR_IN) +#define HWIO_GCC_QUPV3_WRAP2_S7_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_QUPV3_WRAP2_S7_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_QUPV3_WRAP2_S7_CMD_RCGR_DIRTY_D_BMSK 0x80 +#define HWIO_GCC_QUPV3_WRAP2_S7_CMD_RCGR_DIRTY_D_SHFT 0x7 +#define HWIO_GCC_QUPV3_WRAP2_S7_CMD_RCGR_DIRTY_N_BMSK 0x40 +#define HWIO_GCC_QUPV3_WRAP2_S7_CMD_RCGR_DIRTY_N_SHFT 0x6 +#define HWIO_GCC_QUPV3_WRAP2_S7_CMD_RCGR_DIRTY_M_BMSK 0x20 +#define HWIO_GCC_QUPV3_WRAP2_S7_CMD_RCGR_DIRTY_M_SHFT 0x5 +#define HWIO_GCC_QUPV3_WRAP2_S7_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_QUPV3_WRAP2_S7_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_QUPV3_WRAP2_S7_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S7_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S7_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S7_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S7_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S7_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S7_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S7_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e89c) +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e89c) +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e89c) +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_RMSK 0x10371f +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_ADDR, HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_IN) +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_MODE_BMSK 0x3000 +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_MODE_SHFT 0xc +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QUPV3_WRAP2_S7_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_QUPV3_WRAP2_S7_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e8a0) +#define HWIO_GCC_QUPV3_WRAP2_S7_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e8a0) +#define HWIO_GCC_QUPV3_WRAP2_S7_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e8a0) +#define HWIO_GCC_QUPV3_WRAP2_S7_M_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_S7_M_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S7_M_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S7_M_ADDR, HWIO_GCC_QUPV3_WRAP2_S7_M_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S7_M_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S7_M_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S7_M_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S7_M_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S7_M_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S7_M_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S7_M_IN) +#define HWIO_GCC_QUPV3_WRAP2_S7_M_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_S7_M_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_S7_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e8a4) +#define HWIO_GCC_QUPV3_WRAP2_S7_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e8a4) +#define HWIO_GCC_QUPV3_WRAP2_S7_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e8a4) +#define HWIO_GCC_QUPV3_WRAP2_S7_N_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_S7_N_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S7_N_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S7_N_ADDR, HWIO_GCC_QUPV3_WRAP2_S7_N_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S7_N_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S7_N_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S7_N_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S7_N_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S7_N_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S7_N_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S7_N_IN) +#define HWIO_GCC_QUPV3_WRAP2_S7_N_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_S7_N_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_QUPV3_WRAP2_S7_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000e8a8) +#define HWIO_GCC_QUPV3_WRAP2_S7_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000e8a8) +#define HWIO_GCC_QUPV3_WRAP2_S7_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000e8a8) +#define HWIO_GCC_QUPV3_WRAP2_S7_D_RMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_S7_D_ATTR 0x3 +#define HWIO_GCC_QUPV3_WRAP2_S7_D_IN \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S7_D_ADDR, HWIO_GCC_QUPV3_WRAP2_S7_D_RMSK) +#define HWIO_GCC_QUPV3_WRAP2_S7_D_INM(m) \ + in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S7_D_ADDR, m) +#define HWIO_GCC_QUPV3_WRAP2_S7_D_OUT(v) \ + out_dword(HWIO_GCC_QUPV3_WRAP2_S7_D_ADDR,v) +#define HWIO_GCC_QUPV3_WRAP2_S7_D_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S7_D_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S7_D_IN) +#define HWIO_GCC_QUPV3_WRAP2_S7_D_NOT_2D_BMSK 0xffff +#define HWIO_GCC_QUPV3_WRAP2_S7_D_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_PDM_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00023000) +#define HWIO_GCC_PDM_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00023000) +#define HWIO_GCC_PDM_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00023000) +#define HWIO_GCC_PDM_BCR_RMSK 0x1 +#define HWIO_GCC_PDM_BCR_ATTR 0x3 +#define HWIO_GCC_PDM_BCR_IN \ + in_dword_masked(HWIO_GCC_PDM_BCR_ADDR, HWIO_GCC_PDM_BCR_RMSK) +#define HWIO_GCC_PDM_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_PDM_BCR_ADDR, m) +#define HWIO_GCC_PDM_BCR_OUT(v) \ + out_dword(HWIO_GCC_PDM_BCR_ADDR,v) +#define HWIO_GCC_PDM_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PDM_BCR_ADDR,m,v,HWIO_GCC_PDM_BCR_IN) +#define HWIO_GCC_PDM_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_PDM_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_PDM_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_PDM_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PDM_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00023004) +#define HWIO_GCC_PDM_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00023004) +#define HWIO_GCC_PDM_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00023004) +#define HWIO_GCC_PDM_AHB_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_PDM_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_PDM_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_PDM_AHB_CBCR_ADDR, HWIO_GCC_PDM_AHB_CBCR_RMSK) +#define HWIO_GCC_PDM_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_PDM_AHB_CBCR_ADDR, m) +#define HWIO_GCC_PDM_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_PDM_AHB_CBCR_ADDR,v) +#define HWIO_GCC_PDM_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PDM_AHB_CBCR_ADDR,m,v,HWIO_GCC_PDM_AHB_CBCR_IN) +#define HWIO_GCC_PDM_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_PDM_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_PDM_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_PDM_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_PDM_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_PDM_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_PDM_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_PDM_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_PDM_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_PDM_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_PDM_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_PDM_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_PDM_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_PDM_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_PDM_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_PDM_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_PDM_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_PDM_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_PDM_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_PDM_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_PDM_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_PDM_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_PDM_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PDM_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PDM_XO4_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00023008) +#define HWIO_GCC_PDM_XO4_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00023008) +#define HWIO_GCC_PDM_XO4_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00023008) +#define HWIO_GCC_PDM_XO4_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_PDM_XO4_CBCR_ATTR 0x3 +#define HWIO_GCC_PDM_XO4_CBCR_IN \ + in_dword_masked(HWIO_GCC_PDM_XO4_CBCR_ADDR, HWIO_GCC_PDM_XO4_CBCR_RMSK) +#define HWIO_GCC_PDM_XO4_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_PDM_XO4_CBCR_ADDR, m) +#define HWIO_GCC_PDM_XO4_CBCR_OUT(v) \ + out_dword(HWIO_GCC_PDM_XO4_CBCR_ADDR,v) +#define HWIO_GCC_PDM_XO4_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PDM_XO4_CBCR_ADDR,m,v,HWIO_GCC_PDM_XO4_CBCR_IN) +#define HWIO_GCC_PDM_XO4_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_PDM_XO4_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_PDM_XO4_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_PDM_XO4_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_PDM_XO4_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_PDM_XO4_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_PDM_XO4_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_PDM_XO4_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_PDM_XO4_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_PDM_XO4_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_PDM_XO4_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_PDM_XO4_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_PDM_XO4_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_PDM_XO4_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_PDM_XO4_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PDM_XO4_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PDM2_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002300c) +#define HWIO_GCC_PDM2_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002300c) +#define HWIO_GCC_PDM2_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002300c) +#define HWIO_GCC_PDM2_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_PDM2_CBCR_ATTR 0x3 +#define HWIO_GCC_PDM2_CBCR_IN \ + in_dword_masked(HWIO_GCC_PDM2_CBCR_ADDR, HWIO_GCC_PDM2_CBCR_RMSK) +#define HWIO_GCC_PDM2_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_PDM2_CBCR_ADDR, m) +#define HWIO_GCC_PDM2_CBCR_OUT(v) \ + out_dword(HWIO_GCC_PDM2_CBCR_ADDR,v) +#define HWIO_GCC_PDM2_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PDM2_CBCR_ADDR,m,v,HWIO_GCC_PDM2_CBCR_IN) +#define HWIO_GCC_PDM2_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_PDM2_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_PDM2_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_PDM2_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_PDM2_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_PDM2_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_PDM2_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_PDM2_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_PDM2_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_PDM2_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_PDM2_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_PDM2_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_PDM2_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_PDM2_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_PDM2_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PDM2_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PDM2_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00023010) +#define HWIO_GCC_PDM2_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00023010) +#define HWIO_GCC_PDM2_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00023010) +#define HWIO_GCC_PDM2_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_PDM2_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_PDM2_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_PDM2_CMD_RCGR_ADDR, HWIO_GCC_PDM2_CMD_RCGR_RMSK) +#define HWIO_GCC_PDM2_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_PDM2_CMD_RCGR_ADDR, m) +#define HWIO_GCC_PDM2_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_PDM2_CMD_RCGR_ADDR,v) +#define HWIO_GCC_PDM2_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PDM2_CMD_RCGR_ADDR,m,v,HWIO_GCC_PDM2_CMD_RCGR_IN) +#define HWIO_GCC_PDM2_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_PDM2_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_PDM2_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_PDM2_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_PDM2_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_PDM2_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_PDM2_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_PDM2_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_PDM2_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_PDM2_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_PDM2_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PDM2_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PDM2_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00023014) +#define HWIO_GCC_PDM2_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00023014) +#define HWIO_GCC_PDM2_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00023014) +#define HWIO_GCC_PDM2_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_PDM2_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_PDM2_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_PDM2_CFG_RCGR_ADDR, HWIO_GCC_PDM2_CFG_RCGR_RMSK) +#define HWIO_GCC_PDM2_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_PDM2_CFG_RCGR_ADDR, m) +#define HWIO_GCC_PDM2_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_PDM2_CFG_RCGR_ADDR,v) +#define HWIO_GCC_PDM2_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PDM2_CFG_RCGR_ADDR,m,v,HWIO_GCC_PDM2_CFG_RCGR_IN) +#define HWIO_GCC_PDM2_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_PDM2_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_PDM2_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_PDM2_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_PDM2_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_PDM2_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_PDM2_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_PDM2_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_PDM_XO4_DIV_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00023028) +#define HWIO_GCC_PDM_XO4_DIV_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00023028) +#define HWIO_GCC_PDM_XO4_DIV_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00023028) +#define HWIO_GCC_PDM_XO4_DIV_CDIVR_RMSK 0xf +#define HWIO_GCC_PDM_XO4_DIV_CDIVR_ATTR 0x3 +#define HWIO_GCC_PDM_XO4_DIV_CDIVR_IN \ + in_dword_masked(HWIO_GCC_PDM_XO4_DIV_CDIVR_ADDR, HWIO_GCC_PDM_XO4_DIV_CDIVR_RMSK) +#define HWIO_GCC_PDM_XO4_DIV_CDIVR_INM(m) \ + in_dword_masked(HWIO_GCC_PDM_XO4_DIV_CDIVR_ADDR, m) +#define HWIO_GCC_PDM_XO4_DIV_CDIVR_OUT(v) \ + out_dword(HWIO_GCC_PDM_XO4_DIV_CDIVR_ADDR,v) +#define HWIO_GCC_PDM_XO4_DIV_CDIVR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PDM_XO4_DIV_CDIVR_ADDR,m,v,HWIO_GCC_PDM_XO4_DIV_CDIVR_IN) +#define HWIO_GCC_PDM_XO4_DIV_CDIVR_CLK_DIV_BMSK 0xf +#define HWIO_GCC_PDM_XO4_DIV_CDIVR_CLK_DIV_SHFT 0x0 + +#define HWIO_GCC_PMU_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00026000) +#define HWIO_GCC_PMU_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00026000) +#define HWIO_GCC_PMU_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00026000) +#define HWIO_GCC_PMU_BCR_RMSK 0x1 +#define HWIO_GCC_PMU_BCR_ATTR 0x3 +#define HWIO_GCC_PMU_BCR_IN \ + in_dword_masked(HWIO_GCC_PMU_BCR_ADDR, HWIO_GCC_PMU_BCR_RMSK) +#define HWIO_GCC_PMU_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_PMU_BCR_ADDR, m) +#define HWIO_GCC_PMU_BCR_OUT(v) \ + out_dword(HWIO_GCC_PMU_BCR_ADDR,v) +#define HWIO_GCC_PMU_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PMU_BCR_ADDR,m,v,HWIO_GCC_PMU_BCR_IN) +#define HWIO_GCC_PMU_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_PMU_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_PMU_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_PMU_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PMU_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00026004) +#define HWIO_GCC_PMU_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00026004) +#define HWIO_GCC_PMU_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00026004) +#define HWIO_GCC_PMU_AHB_CBCR_RMSK 0x81d00005 +#define HWIO_GCC_PMU_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_PMU_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_PMU_AHB_CBCR_ADDR, HWIO_GCC_PMU_AHB_CBCR_RMSK) +#define HWIO_GCC_PMU_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_PMU_AHB_CBCR_ADDR, m) +#define HWIO_GCC_PMU_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_PMU_AHB_CBCR_ADDR,v) +#define HWIO_GCC_PMU_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PMU_AHB_CBCR_ADDR,m,v,HWIO_GCC_PMU_AHB_CBCR_IN) +#define HWIO_GCC_PMU_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_PMU_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_PMU_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_PMU_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_PMU_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_PMU_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_PMU_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_PMU_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_PMU_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_PMU_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_PMU_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_PMU_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_PMU_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_PMU_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_PMU_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_PMU_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_PMU_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PMU_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PMU_CORE_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00026008) +#define HWIO_GCC_PMU_CORE_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00026008) +#define HWIO_GCC_PMU_CORE_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00026008) +#define HWIO_GCC_PMU_CORE_CBCR_RMSK 0x81d00005 +#define HWIO_GCC_PMU_CORE_CBCR_ATTR 0x3 +#define HWIO_GCC_PMU_CORE_CBCR_IN \ + in_dword_masked(HWIO_GCC_PMU_CORE_CBCR_ADDR, HWIO_GCC_PMU_CORE_CBCR_RMSK) +#define HWIO_GCC_PMU_CORE_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_PMU_CORE_CBCR_ADDR, m) +#define HWIO_GCC_PMU_CORE_CBCR_OUT(v) \ + out_dword(HWIO_GCC_PMU_CORE_CBCR_ADDR,v) +#define HWIO_GCC_PMU_CORE_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PMU_CORE_CBCR_ADDR,m,v,HWIO_GCC_PMU_CORE_CBCR_IN) +#define HWIO_GCC_PMU_CORE_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_PMU_CORE_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_PMU_CORE_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_PMU_CORE_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_PMU_CORE_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_PMU_CORE_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_PMU_CORE_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_PMU_CORE_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_PMU_CORE_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_PMU_CORE_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_PMU_CORE_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_PMU_CORE_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_PMU_CORE_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_PMU_CORE_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_PMU_CORE_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_PMU_CORE_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_PMU_CORE_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PMU_CORE_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_PMU_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00026020) +#define HWIO_GCC_RPMH_PMU_CMD_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00026020) +#define HWIO_GCC_RPMH_PMU_CMD_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00026020) +#define HWIO_GCC_RPMH_PMU_CMD_DFSR_RMSK 0xffff +#define HWIO_GCC_RPMH_PMU_CMD_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_PMU_CMD_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_PMU_CMD_DFSR_ADDR, HWIO_GCC_RPMH_PMU_CMD_DFSR_RMSK) +#define HWIO_GCC_RPMH_PMU_CMD_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PMU_CMD_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_PMU_CMD_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PMU_CMD_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_PMU_CMD_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PMU_CMD_DFSR_ADDR,m,v,HWIO_GCC_RPMH_PMU_CMD_DFSR_IN) +#define HWIO_GCC_RPMH_PMU_CMD_DFSR_RCG_SW_CTRL_BMSK 0x8000 +#define HWIO_GCC_RPMH_PMU_CMD_DFSR_RCG_SW_CTRL_SHFT 0xf +#define HWIO_GCC_RPMH_PMU_CMD_DFSR_SW_PERF_STATE_BMSK 0x7800 +#define HWIO_GCC_RPMH_PMU_CMD_DFSR_SW_PERF_STATE_SHFT 0xb +#define HWIO_GCC_RPMH_PMU_CMD_DFSR_SW_OVERRIDE_BMSK 0x400 +#define HWIO_GCC_RPMH_PMU_CMD_DFSR_SW_OVERRIDE_SHFT 0xa +#define HWIO_GCC_RPMH_PMU_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK 0x200 +#define HWIO_GCC_RPMH_PMU_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT 0x9 +#define HWIO_GCC_RPMH_PMU_CMD_DFSR_DFS_FSM_STATE_BMSK 0x1c0 +#define HWIO_GCC_RPMH_PMU_CMD_DFSR_DFS_FSM_STATE_SHFT 0x6 +#define HWIO_GCC_RPMH_PMU_CMD_DFSR_HW_CLK_CONTROL_BMSK 0x20 +#define HWIO_GCC_RPMH_PMU_CMD_DFSR_HW_CLK_CONTROL_SHFT 0x5 +#define HWIO_GCC_RPMH_PMU_CMD_DFSR_CURR_PERF_STATE_BMSK 0x1e +#define HWIO_GCC_RPMH_PMU_CMD_DFSR_CURR_PERF_STATE_SHFT 0x1 +#define HWIO_GCC_RPMH_PMU_CMD_DFSR_DFS_EN_BMSK 0x1 +#define HWIO_GCC_RPMH_PMU_CMD_DFSR_DFS_EN_SHFT 0x0 +#define HWIO_GCC_RPMH_PMU_CMD_DFSR_DFS_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_CMD_DFSR_DFS_EN_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00026028) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00026028) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00026028) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF0_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF0_DFSR_ADDR, HWIO_GCC_RPMH_PMU_PMU_CORE_PERF0_DFSR_RMSK) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_PMU_PMU_CORE_PERF0_DFSR_IN) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002602c) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002602c) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002602c) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF1_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF1_DFSR_ADDR, HWIO_GCC_RPMH_PMU_PMU_CORE_PERF1_DFSR_RMSK) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_PMU_PMU_CORE_PERF1_DFSR_IN) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00026030) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00026030) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00026030) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF2_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF2_DFSR_ADDR, HWIO_GCC_RPMH_PMU_PMU_CORE_PERF2_DFSR_RMSK) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_PMU_PMU_CORE_PERF2_DFSR_IN) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00026034) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00026034) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00026034) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF3_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF3_DFSR_ADDR, HWIO_GCC_RPMH_PMU_PMU_CORE_PERF3_DFSR_RMSK) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_PMU_PMU_CORE_PERF3_DFSR_IN) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00026038) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00026038) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00026038) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF4_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF4_DFSR_ADDR, HWIO_GCC_RPMH_PMU_PMU_CORE_PERF4_DFSR_RMSK) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_PMU_PMU_CORE_PERF4_DFSR_IN) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002603c) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002603c) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002603c) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF5_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF5_DFSR_ADDR, HWIO_GCC_RPMH_PMU_PMU_CORE_PERF5_DFSR_RMSK) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_PMU_PMU_CORE_PERF5_DFSR_IN) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00026040) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00026040) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00026040) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF6_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF6_DFSR_ADDR, HWIO_GCC_RPMH_PMU_PMU_CORE_PERF6_DFSR_RMSK) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_PMU_PMU_CORE_PERF6_DFSR_IN) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00026044) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00026044) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00026044) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF7_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF7_DFSR_ADDR, HWIO_GCC_RPMH_PMU_PMU_CORE_PERF7_DFSR_RMSK) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_PMU_PMU_CORE_PERF7_DFSR_IN) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF8_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00026048) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF8_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00026048) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF8_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00026048) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF8_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF8_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF8_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF8_DFSR_ADDR, HWIO_GCC_RPMH_PMU_PMU_CORE_PERF8_DFSR_RMSK) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF8_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF8_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF8_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF8_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF8_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_PMU_PMU_CORE_PERF8_DFSR_IN) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF8_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF8_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF8_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF8_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF8_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF8_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF8_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF8_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF8_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF8_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF8_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF8_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF8_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF8_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF8_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF8_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF8_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF8_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF8_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF8_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF8_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF8_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF8_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF8_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF8_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF8_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF8_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF8_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF8_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF8_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF8_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF8_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF8_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF8_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF8_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF8_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF8_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF8_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF8_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF8_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF8_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF8_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF8_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF8_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF9_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002604c) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF9_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002604c) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF9_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002604c) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF9_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF9_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF9_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF9_DFSR_ADDR, HWIO_GCC_RPMH_PMU_PMU_CORE_PERF9_DFSR_RMSK) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF9_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF9_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF9_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF9_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF9_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_PMU_PMU_CORE_PERF9_DFSR_IN) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF9_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF9_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF9_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF9_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF9_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF9_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF9_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF9_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF9_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF9_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF9_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF9_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF9_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF9_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF9_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF9_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF9_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF9_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF9_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF9_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF9_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF9_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF9_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF9_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF9_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF9_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF9_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF9_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF9_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF9_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF9_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF9_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF9_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF9_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF9_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF9_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF9_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF9_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF9_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF9_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF9_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF9_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF9_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF9_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF10_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00026050) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF10_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00026050) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF10_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00026050) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF10_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF10_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF10_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF10_DFSR_ADDR, HWIO_GCC_RPMH_PMU_PMU_CORE_PERF10_DFSR_RMSK) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF10_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF10_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF10_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF10_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF10_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_PMU_PMU_CORE_PERF10_DFSR_IN) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF10_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF10_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF10_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF10_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF10_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF10_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF10_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF10_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF10_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF10_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF10_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF10_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF10_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF10_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF10_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF10_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF10_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF10_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF10_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF10_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF10_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF10_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF10_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF10_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF10_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF10_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF10_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF10_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF10_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF10_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF10_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF10_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF10_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF10_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF10_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF10_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF10_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF10_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF10_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF10_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF10_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF10_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF10_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF10_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF11_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00026054) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF11_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00026054) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF11_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00026054) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF11_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF11_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF11_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF11_DFSR_ADDR, HWIO_GCC_RPMH_PMU_PMU_CORE_PERF11_DFSR_RMSK) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF11_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF11_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF11_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF11_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF11_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_PMU_PMU_CORE_PERF11_DFSR_IN) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF11_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF11_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF11_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF11_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF11_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF11_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF11_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF11_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF11_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF11_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF11_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF11_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF11_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF11_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF11_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF11_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF11_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF11_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF11_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF11_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF11_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF11_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF11_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF11_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF11_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF11_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF11_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF11_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF11_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF11_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF11_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF11_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF11_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF11_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF11_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF11_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF11_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF11_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF11_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF11_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF11_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF11_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF11_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF11_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF12_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00026058) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF12_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00026058) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF12_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00026058) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF12_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF12_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF12_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF12_DFSR_ADDR, HWIO_GCC_RPMH_PMU_PMU_CORE_PERF12_DFSR_RMSK) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF12_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF12_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF12_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF12_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF12_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_PMU_PMU_CORE_PERF12_DFSR_IN) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF12_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF12_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF12_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF12_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF12_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF12_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF12_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF12_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF12_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF12_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF12_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF12_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF12_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF12_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF12_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF12_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF12_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF12_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF12_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF12_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF12_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF12_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF12_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF12_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF12_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF12_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF12_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF12_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF12_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF12_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF12_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF12_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF12_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF12_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF12_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF12_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF12_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF12_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF12_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF12_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF12_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF12_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF12_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF12_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF13_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002605c) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF13_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002605c) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF13_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002605c) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF13_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF13_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF13_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF13_DFSR_ADDR, HWIO_GCC_RPMH_PMU_PMU_CORE_PERF13_DFSR_RMSK) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF13_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF13_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF13_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF13_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF13_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_PMU_PMU_CORE_PERF13_DFSR_IN) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF13_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF13_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF13_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF13_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF13_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF13_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF13_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF13_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF13_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF13_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF13_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF13_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF13_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF13_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF13_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF13_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF13_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF13_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF13_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF13_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF13_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF13_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF13_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF13_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF13_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF13_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF13_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF13_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF13_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF13_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF13_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF13_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF13_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF13_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF13_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF13_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF13_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF13_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF13_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF13_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF13_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF13_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF13_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF13_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF14_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00026060) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF14_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00026060) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF14_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00026060) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF14_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF14_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF14_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF14_DFSR_ADDR, HWIO_GCC_RPMH_PMU_PMU_CORE_PERF14_DFSR_RMSK) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF14_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF14_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF14_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF14_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF14_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_PMU_PMU_CORE_PERF14_DFSR_IN) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF14_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF14_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF14_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF14_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF14_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF14_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF14_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF14_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF14_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF14_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF14_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF14_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF14_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF14_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF14_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF14_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF14_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF14_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF14_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF14_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF14_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF14_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF14_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF14_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF14_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF14_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF14_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF14_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF14_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF14_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF14_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF14_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF14_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF14_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF14_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF14_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF14_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF14_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF14_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF14_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF14_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF14_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF14_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF14_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF15_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00026064) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF15_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00026064) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF15_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00026064) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF15_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF15_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF15_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF15_DFSR_ADDR, HWIO_GCC_RPMH_PMU_PMU_CORE_PERF15_DFSR_RMSK) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF15_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF15_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF15_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF15_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF15_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PMU_PMU_CORE_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_PMU_PMU_CORE_PERF15_DFSR_IN) +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF15_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF15_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF15_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF15_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF15_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF15_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF15_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF15_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF15_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF15_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF15_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF15_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF15_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF15_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF15_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF15_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF15_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF15_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF15_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF15_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF15_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF15_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF15_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF15_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF15_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF15_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF15_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF15_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF15_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF15_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF15_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF15_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF15_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF15_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF15_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF15_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF15_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF15_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF15_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF15_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF15_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF15_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF15_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_PMU_PMU_CORE_PERF15_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_PMU_CORE_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002600c) +#define HWIO_GCC_PMU_CORE_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002600c) +#define HWIO_GCC_PMU_CORE_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002600c) +#define HWIO_GCC_PMU_CORE_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_PMU_CORE_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_PMU_CORE_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_PMU_CORE_CMD_RCGR_ADDR, HWIO_GCC_PMU_CORE_CMD_RCGR_RMSK) +#define HWIO_GCC_PMU_CORE_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_PMU_CORE_CMD_RCGR_ADDR, m) +#define HWIO_GCC_PMU_CORE_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_PMU_CORE_CMD_RCGR_ADDR,v) +#define HWIO_GCC_PMU_CORE_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PMU_CORE_CMD_RCGR_ADDR,m,v,HWIO_GCC_PMU_CORE_CMD_RCGR_IN) +#define HWIO_GCC_PMU_CORE_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_PMU_CORE_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_PMU_CORE_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_PMU_CORE_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_PMU_CORE_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_PMU_CORE_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_PMU_CORE_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_PMU_CORE_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_PMU_CORE_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_PMU_CORE_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_PMU_CORE_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PMU_CORE_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PMU_CORE_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00026010) +#define HWIO_GCC_PMU_CORE_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00026010) +#define HWIO_GCC_PMU_CORE_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00026010) +#define HWIO_GCC_PMU_CORE_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_PMU_CORE_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_PMU_CORE_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_PMU_CORE_CFG_RCGR_ADDR, HWIO_GCC_PMU_CORE_CFG_RCGR_RMSK) +#define HWIO_GCC_PMU_CORE_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_PMU_CORE_CFG_RCGR_ADDR, m) +#define HWIO_GCC_PMU_CORE_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_PMU_CORE_CFG_RCGR_ADDR,v) +#define HWIO_GCC_PMU_CORE_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PMU_CORE_CFG_RCGR_ADDR,m,v,HWIO_GCC_PMU_CORE_CFG_RCGR_IN) +#define HWIO_GCC_PMU_CORE_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_PMU_CORE_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_PMU_CORE_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_PMU_CORE_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_PMU_CORE_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_PMU_CORE_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_PMU_CORE_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_PMU_CORE_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_PMU_CORE_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_PMU_CORE_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_PMU_CORE_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_PMU_CORE_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_PMU_CORE_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_PMU_CORE_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_PMU_CORE_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_PMU_CORE_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_PMU_CORE_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_PMU_CORE_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_PMU_CORE_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_PMU_CORE_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_PMU_CORE_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_PMU_CORE_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_PMU_CORE_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_PMU_CORE_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_PMU_CORE_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_PMU_CORE_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_PMU_CORE_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_PMU_CORE_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_PMU_CORE_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_PMU_CORE_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_PMU_CORE_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_PMU_CORE_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_PMU_CORE_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_PMU_CORE_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_PMU_CORE_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_PMU_CORE_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_PMU_CORE_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_PMU_CORE_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_PMU_CORE_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_PMU_CORE_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_PMU_CORE_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_PMU_CORE_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_PMU_CORE_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_PMU_CORE_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_PMU_CORE_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_PMU_CORE_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_PMU_CORE_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_PMU_CORE_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_PMU_CORE_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_PMU_CORE_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_PMU_CORE_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_PMU_CORE_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_PRNG_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00088000) +#define HWIO_GCC_PRNG_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00088000) +#define HWIO_GCC_PRNG_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00088000) +#define HWIO_GCC_PRNG_BCR_RMSK 0x1 +#define HWIO_GCC_PRNG_BCR_ATTR 0x3 +#define HWIO_GCC_PRNG_BCR_IN \ + in_dword_masked(HWIO_GCC_PRNG_BCR_ADDR, HWIO_GCC_PRNG_BCR_RMSK) +#define HWIO_GCC_PRNG_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_PRNG_BCR_ADDR, m) +#define HWIO_GCC_PRNG_BCR_OUT(v) \ + out_dword(HWIO_GCC_PRNG_BCR_ADDR,v) +#define HWIO_GCC_PRNG_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PRNG_BCR_ADDR,m,v,HWIO_GCC_PRNG_BCR_IN) +#define HWIO_GCC_PRNG_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_PRNG_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_PRNG_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_PRNG_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PRNG_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00088004) +#define HWIO_GCC_PRNG_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00088004) +#define HWIO_GCC_PRNG_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00088004) +#define HWIO_GCC_PRNG_AHB_CBCR_RMSK 0x81d00004 +#define HWIO_GCC_PRNG_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_PRNG_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_PRNG_AHB_CBCR_ADDR, HWIO_GCC_PRNG_AHB_CBCR_RMSK) +#define HWIO_GCC_PRNG_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_PRNG_AHB_CBCR_ADDR, m) +#define HWIO_GCC_PRNG_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_PRNG_AHB_CBCR_ADDR,v) +#define HWIO_GCC_PRNG_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PRNG_AHB_CBCR_ADDR,m,v,HWIO_GCC_PRNG_AHB_CBCR_IN) +#define HWIO_GCC_PRNG_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_PRNG_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_PRNG_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_PRNG_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_PRNG_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_PRNG_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_PRNG_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_PRNG_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_PRNG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_PRNG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_PRNG_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_PRNG_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_PRNG_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_PRNG_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 + +#define HWIO_GCC_TME_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00024000) +#define HWIO_GCC_TME_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00024000) +#define HWIO_GCC_TME_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00024000) +#define HWIO_GCC_TME_BCR_RMSK 0x1 +#define HWIO_GCC_TME_BCR_ATTR 0x3 +#define HWIO_GCC_TME_BCR_IN \ + in_dword_masked(HWIO_GCC_TME_BCR_ADDR, HWIO_GCC_TME_BCR_RMSK) +#define HWIO_GCC_TME_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_TME_BCR_ADDR, m) +#define HWIO_GCC_TME_BCR_OUT(v) \ + out_dword(HWIO_GCC_TME_BCR_ADDR,v) +#define HWIO_GCC_TME_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TME_BCR_ADDR,m,v,HWIO_GCC_TME_BCR_IN) +#define HWIO_GCC_TME_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_TME_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_TME_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TME_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00024004) +#define HWIO_GCC_TME_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00024004) +#define HWIO_GCC_TME_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00024004) +#define HWIO_GCC_TME_AHB_CBCR_RMSK 0x81d00005 +#define HWIO_GCC_TME_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_TME_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_TME_AHB_CBCR_ADDR, HWIO_GCC_TME_AHB_CBCR_RMSK) +#define HWIO_GCC_TME_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_TME_AHB_CBCR_ADDR, m) +#define HWIO_GCC_TME_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_TME_AHB_CBCR_ADDR,v) +#define HWIO_GCC_TME_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TME_AHB_CBCR_ADDR,m,v,HWIO_GCC_TME_AHB_CBCR_IN) +#define HWIO_GCC_TME_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TME_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TME_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_TME_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_TME_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_TME_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_TME_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_TME_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_TME_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_TME_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_TME_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_TME_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_TME_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_TME_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_TME_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_TME_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_TME_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TME_BOOT_ROM_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00024008) +#define HWIO_GCC_TME_BOOT_ROM_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00024008) +#define HWIO_GCC_TME_BOOT_ROM_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00024008) +#define HWIO_GCC_TME_BOOT_ROM_AHB_CBCR_RMSK 0x81d00005 +#define HWIO_GCC_TME_BOOT_ROM_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_TME_BOOT_ROM_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_TME_BOOT_ROM_AHB_CBCR_ADDR, HWIO_GCC_TME_BOOT_ROM_AHB_CBCR_RMSK) +#define HWIO_GCC_TME_BOOT_ROM_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_TME_BOOT_ROM_AHB_CBCR_ADDR, m) +#define HWIO_GCC_TME_BOOT_ROM_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_TME_BOOT_ROM_AHB_CBCR_ADDR,v) +#define HWIO_GCC_TME_BOOT_ROM_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TME_BOOT_ROM_AHB_CBCR_ADDR,m,v,HWIO_GCC_TME_BOOT_ROM_AHB_CBCR_IN) +#define HWIO_GCC_TME_BOOT_ROM_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TME_BOOT_ROM_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TME_BOOT_ROM_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_TME_BOOT_ROM_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_TME_BOOT_ROM_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_TME_BOOT_ROM_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_TME_BOOT_ROM_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_TME_BOOT_ROM_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_TME_BOOT_ROM_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_TME_BOOT_ROM_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_TME_BOOT_ROM_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_TME_BOOT_ROM_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_TME_BOOT_ROM_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_TME_BOOT_ROM_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_TME_BOOT_ROM_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_TME_BOOT_ROM_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_TME_BOOT_ROM_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_BOOT_ROM_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TME_SNOC_QXM_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002400c) +#define HWIO_GCC_TME_SNOC_QXM_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002400c) +#define HWIO_GCC_TME_SNOC_QXM_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002400c) +#define HWIO_GCC_TME_SNOC_QXM_CBCR_RMSK 0x81d00005 +#define HWIO_GCC_TME_SNOC_QXM_CBCR_ATTR 0x3 +#define HWIO_GCC_TME_SNOC_QXM_CBCR_IN \ + in_dword_masked(HWIO_GCC_TME_SNOC_QXM_CBCR_ADDR, HWIO_GCC_TME_SNOC_QXM_CBCR_RMSK) +#define HWIO_GCC_TME_SNOC_QXM_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_TME_SNOC_QXM_CBCR_ADDR, m) +#define HWIO_GCC_TME_SNOC_QXM_CBCR_OUT(v) \ + out_dword(HWIO_GCC_TME_SNOC_QXM_CBCR_ADDR,v) +#define HWIO_GCC_TME_SNOC_QXM_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TME_SNOC_QXM_CBCR_ADDR,m,v,HWIO_GCC_TME_SNOC_QXM_CBCR_IN) +#define HWIO_GCC_TME_SNOC_QXM_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TME_SNOC_QXM_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TME_SNOC_QXM_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_TME_SNOC_QXM_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_TME_SNOC_QXM_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_TME_SNOC_QXM_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_TME_SNOC_QXM_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_TME_SNOC_QXM_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_TME_SNOC_QXM_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_TME_SNOC_QXM_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_TME_SNOC_QXM_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_TME_SNOC_QXM_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_TME_SNOC_QXM_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_TME_SNOC_QXM_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_TME_SNOC_QXM_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_TME_SNOC_QXM_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_TME_SNOC_QXM_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_SNOC_QXM_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TME_TRIG_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00024010) +#define HWIO_GCC_TME_TRIG_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00024010) +#define HWIO_GCC_TME_TRIG_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00024010) +#define HWIO_GCC_TME_TRIG_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_TME_TRIG_CBCR_ATTR 0x3 +#define HWIO_GCC_TME_TRIG_CBCR_IN \ + in_dword_masked(HWIO_GCC_TME_TRIG_CBCR_ADDR, HWIO_GCC_TME_TRIG_CBCR_RMSK) +#define HWIO_GCC_TME_TRIG_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_TME_TRIG_CBCR_ADDR, m) +#define HWIO_GCC_TME_TRIG_CBCR_OUT(v) \ + out_dword(HWIO_GCC_TME_TRIG_CBCR_ADDR,v) +#define HWIO_GCC_TME_TRIG_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TME_TRIG_CBCR_ADDR,m,v,HWIO_GCC_TME_TRIG_CBCR_IN) +#define HWIO_GCC_TME_TRIG_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TME_TRIG_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TME_TRIG_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_TME_TRIG_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_TME_TRIG_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_TME_TRIG_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_TME_TRIG_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_TME_TRIG_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_TME_TRIG_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_TME_TRIG_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_TME_TRIG_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_TME_TRIG_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_TME_TRIG_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_TME_TRIG_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_TME_TRIG_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_TME_TRIG_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_TME_TRIG_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_TME_TRIG_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_TME_TRIG_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_TRIG_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_TRIG_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_TME_TRIG_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_TME_TRIG_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_TRIG_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TME_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00024014) +#define HWIO_GCC_TME_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00024014) +#define HWIO_GCC_TME_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00024014) +#define HWIO_GCC_TME_AT_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_TME_AT_CBCR_ATTR 0x3 +#define HWIO_GCC_TME_AT_CBCR_IN \ + in_dword_masked(HWIO_GCC_TME_AT_CBCR_ADDR, HWIO_GCC_TME_AT_CBCR_RMSK) +#define HWIO_GCC_TME_AT_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_TME_AT_CBCR_ADDR, m) +#define HWIO_GCC_TME_AT_CBCR_OUT(v) \ + out_dword(HWIO_GCC_TME_AT_CBCR_ADDR,v) +#define HWIO_GCC_TME_AT_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TME_AT_CBCR_ADDR,m,v,HWIO_GCC_TME_AT_CBCR_IN) +#define HWIO_GCC_TME_AT_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TME_AT_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TME_AT_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_TME_AT_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_TME_AT_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_TME_AT_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_TME_AT_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_TME_AT_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_TME_AT_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_TME_AT_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_TME_AT_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_TME_AT_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_TME_AT_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_TME_AT_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_TME_AT_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_TME_AT_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_TME_AT_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_TME_AT_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_TME_AT_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_AT_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_AT_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_TME_AT_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_TME_AT_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_AT_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TCSR_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00027000) +#define HWIO_GCC_TCSR_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00027000) +#define HWIO_GCC_TCSR_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00027000) +#define HWIO_GCC_TCSR_BCR_RMSK 0x1 +#define HWIO_GCC_TCSR_BCR_ATTR 0x3 +#define HWIO_GCC_TCSR_BCR_IN \ + in_dword_masked(HWIO_GCC_TCSR_BCR_ADDR, HWIO_GCC_TCSR_BCR_RMSK) +#define HWIO_GCC_TCSR_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_TCSR_BCR_ADDR, m) +#define HWIO_GCC_TCSR_BCR_OUT(v) \ + out_dword(HWIO_GCC_TCSR_BCR_ADDR,v) +#define HWIO_GCC_TCSR_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TCSR_BCR_ADDR,m,v,HWIO_GCC_TCSR_BCR_IN) +#define HWIO_GCC_TCSR_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_TCSR_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_TCSR_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_TCSR_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TCSR_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00027004) +#define HWIO_GCC_TCSR_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00027004) +#define HWIO_GCC_TCSR_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00027004) +#define HWIO_GCC_TCSR_AHB_CBCR_RMSK 0x81d00004 +#define HWIO_GCC_TCSR_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_TCSR_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_TCSR_AHB_CBCR_ADDR, HWIO_GCC_TCSR_AHB_CBCR_RMSK) +#define HWIO_GCC_TCSR_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_TCSR_AHB_CBCR_ADDR, m) +#define HWIO_GCC_TCSR_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_TCSR_AHB_CBCR_ADDR,v) +#define HWIO_GCC_TCSR_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TCSR_AHB_CBCR_ADDR,m,v,HWIO_GCC_TCSR_AHB_CBCR_IN) +#define HWIO_GCC_TCSR_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TCSR_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TCSR_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_TCSR_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_TCSR_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_TCSR_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_TCSR_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_TCSR_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_TCSR_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_TCSR_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_TCSR_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_TCSR_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_TCSR_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_TCSR_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 + +#define HWIO_GCC_TCSR_ACC_SERIAL_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00027008) +#define HWIO_GCC_TCSR_ACC_SERIAL_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00027008) +#define HWIO_GCC_TCSR_ACC_SERIAL_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00027008) +#define HWIO_GCC_TCSR_ACC_SERIAL_CBCR_RMSK 0x81c0000f +#define HWIO_GCC_TCSR_ACC_SERIAL_CBCR_ATTR 0x3 +#define HWIO_GCC_TCSR_ACC_SERIAL_CBCR_IN \ + in_dword_masked(HWIO_GCC_TCSR_ACC_SERIAL_CBCR_ADDR, HWIO_GCC_TCSR_ACC_SERIAL_CBCR_RMSK) +#define HWIO_GCC_TCSR_ACC_SERIAL_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_TCSR_ACC_SERIAL_CBCR_ADDR, m) +#define HWIO_GCC_TCSR_ACC_SERIAL_CBCR_OUT(v) \ + out_dword(HWIO_GCC_TCSR_ACC_SERIAL_CBCR_ADDR,v) +#define HWIO_GCC_TCSR_ACC_SERIAL_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TCSR_ACC_SERIAL_CBCR_ADDR,m,v,HWIO_GCC_TCSR_ACC_SERIAL_CBCR_IN) +#define HWIO_GCC_TCSR_ACC_SERIAL_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TCSR_ACC_SERIAL_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TCSR_ACC_SERIAL_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_TCSR_ACC_SERIAL_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_TCSR_ACC_SERIAL_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_TCSR_ACC_SERIAL_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_TCSR_ACC_SERIAL_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_TCSR_ACC_SERIAL_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_TCSR_ACC_SERIAL_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_TCSR_ACC_SERIAL_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_TCSR_ACC_SERIAL_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_TCSR_ACC_SERIAL_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_TCSR_ACC_SERIAL_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_TCSR_ACC_SERIAL_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_TCSR_ACC_SERIAL_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_TCSR_ACC_SERIAL_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_TCSR_ACC_SERIAL_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_TCSR_ACC_SERIAL_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_TCSR_ACC_SERIAL_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_TCSR_ACC_SERIAL_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_TCSR_ACC_SERIAL_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TCSR_ACC_SERIAL_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MEMRED_P2S_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002d000) +#define HWIO_GCC_MEMRED_P2S_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002d000) +#define HWIO_GCC_MEMRED_P2S_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002d000) +#define HWIO_GCC_MEMRED_P2S_CBCR_RMSK 0x81c0000f +#define HWIO_GCC_MEMRED_P2S_CBCR_ATTR 0x3 +#define HWIO_GCC_MEMRED_P2S_CBCR_IN \ + in_dword_masked(HWIO_GCC_MEMRED_P2S_CBCR_ADDR, HWIO_GCC_MEMRED_P2S_CBCR_RMSK) +#define HWIO_GCC_MEMRED_P2S_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_MEMRED_P2S_CBCR_ADDR, m) +#define HWIO_GCC_MEMRED_P2S_CBCR_OUT(v) \ + out_dword(HWIO_GCC_MEMRED_P2S_CBCR_ADDR,v) +#define HWIO_GCC_MEMRED_P2S_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MEMRED_P2S_CBCR_ADDR,m,v,HWIO_GCC_MEMRED_P2S_CBCR_IN) +#define HWIO_GCC_MEMRED_P2S_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_MEMRED_P2S_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_MEMRED_P2S_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_MEMRED_P2S_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_MEMRED_P2S_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_MEMRED_P2S_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_MEMRED_P2S_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_MEMRED_P2S_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_MEMRED_P2S_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_MEMRED_P2S_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_MEMRED_P2S_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_MEMRED_P2S_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_MEMRED_P2S_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_MEMRED_P2S_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_MEMRED_P2S_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_MEMRED_P2S_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_MEMRED_P2S_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_MEMRED_P2S_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_MEMRED_P2S_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_MEMRED_P2S_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_MEMRED_P2S_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MEMRED_P2S_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MEMRED_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002d004) +#define HWIO_GCC_MEMRED_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002d004) +#define HWIO_GCC_MEMRED_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002d004) +#define HWIO_GCC_MEMRED_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_MEMRED_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_MEMRED_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_MEMRED_CMD_RCGR_ADDR, HWIO_GCC_MEMRED_CMD_RCGR_RMSK) +#define HWIO_GCC_MEMRED_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_MEMRED_CMD_RCGR_ADDR, m) +#define HWIO_GCC_MEMRED_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_MEMRED_CMD_RCGR_ADDR,v) +#define HWIO_GCC_MEMRED_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MEMRED_CMD_RCGR_ADDR,m,v,HWIO_GCC_MEMRED_CMD_RCGR_IN) +#define HWIO_GCC_MEMRED_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_MEMRED_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_MEMRED_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_MEMRED_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_MEMRED_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_MEMRED_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_MEMRED_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_MEMRED_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_MEMRED_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_MEMRED_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_MEMRED_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MEMRED_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MEMRED_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002d008) +#define HWIO_GCC_MEMRED_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002d008) +#define HWIO_GCC_MEMRED_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002d008) +#define HWIO_GCC_MEMRED_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_MEMRED_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_MEMRED_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_MEMRED_CFG_RCGR_ADDR, HWIO_GCC_MEMRED_CFG_RCGR_RMSK) +#define HWIO_GCC_MEMRED_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_MEMRED_CFG_RCGR_ADDR, m) +#define HWIO_GCC_MEMRED_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_MEMRED_CFG_RCGR_ADDR,v) +#define HWIO_GCC_MEMRED_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MEMRED_CFG_RCGR_ADDR,m,v,HWIO_GCC_MEMRED_CFG_RCGR_IN) +#define HWIO_GCC_MEMRED_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_MEMRED_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_MEMRED_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_MEMRED_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_MEMRED_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_MEMRED_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_MEMRED_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_MEMRED_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_MEMRED_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_MEMRED_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_MEMRED_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_MEMRED_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_MEMRED_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_MEMRED_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_MEMRED_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_MEMRED_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_MEMRED_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_MEMRED_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_MEMRED_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_MEMRED_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_MEMRED_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_MEMRED_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_MEMRED_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_MEMRED_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_MEMRED_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_MEMRED_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_MEMRED_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_MEMRED_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_MEMRED_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_MEMRED_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_MEMRED_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_MEMRED_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_MEMRED_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_MEMRED_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_MEMRED_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_MEMRED_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_MEMRED_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_MEMRED_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_MEMRED_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_MEMRED_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_MEMRED_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_MEMRED_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_MEMRED_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_MEMRED_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_MEMRED_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_MEMRED_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_MEMRED_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_MEMRED_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_MEMRED_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_MEMRED_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_MEMRED_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_MEMRED_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_BOOT_ROM_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00028000) +#define HWIO_GCC_BOOT_ROM_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00028000) +#define HWIO_GCC_BOOT_ROM_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00028000) +#define HWIO_GCC_BOOT_ROM_BCR_RMSK 0x1 +#define HWIO_GCC_BOOT_ROM_BCR_ATTR 0x3 +#define HWIO_GCC_BOOT_ROM_BCR_IN \ + in_dword_masked(HWIO_GCC_BOOT_ROM_BCR_ADDR, HWIO_GCC_BOOT_ROM_BCR_RMSK) +#define HWIO_GCC_BOOT_ROM_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_BOOT_ROM_BCR_ADDR, m) +#define HWIO_GCC_BOOT_ROM_BCR_OUT(v) \ + out_dword(HWIO_GCC_BOOT_ROM_BCR_ADDR,v) +#define HWIO_GCC_BOOT_ROM_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BOOT_ROM_BCR_ADDR,m,v,HWIO_GCC_BOOT_ROM_BCR_IN) +#define HWIO_GCC_BOOT_ROM_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_BOOT_ROM_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_BOOT_ROM_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_BOOT_ROM_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00028004) +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00028004) +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00028004) +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_RMSK 0x81d0700e +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_BOOT_ROM_AHB_CBCR_ADDR, HWIO_GCC_BOOT_ROM_AHB_CBCR_RMSK) +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_BOOT_ROM_AHB_CBCR_ADDR, m) +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_BOOT_ROM_AHB_CBCR_ADDR,v) +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BOOT_ROM_AHB_CBCR_ADDR,m,v,HWIO_GCC_BOOT_ROM_AHB_CBCR_IN) +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 + +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00028008) +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00028008) +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00028008) +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_RMSK 0xf1ffffe +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_ATTR 0x3 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_IN \ + in_dword_masked(HWIO_GCC_BOOT_ROM_AHB_SREGR_ADDR, HWIO_GCC_BOOT_ROM_AHB_SREGR_RMSK) +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_BOOT_ROM_AHB_SREGR_ADDR, m) +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_OUT(v) \ + out_dword(HWIO_GCC_BOOT_ROM_AHB_SREGR_ADDR,v) +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BOOT_ROM_AHB_SREGR_ADDR,m,v,HWIO_GCC_BOOT_ROM_AHB_SREGR_IN) +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xf000000 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_PWR_FSM_CLK_SEL_BMSK 0x100000 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_PWR_FSM_CLK_SEL_SHFT 0x14 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xf0000 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_BOOT_ROM_AHB_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_BOOT_ROM_AHB_CFG_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002800c) +#define HWIO_GCC_BOOT_ROM_AHB_CFG_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002800c) +#define HWIO_GCC_BOOT_ROM_AHB_CFG_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002800c) +#define HWIO_GCC_BOOT_ROM_AHB_CFG_SREGR_RMSK 0xffffffff +#define HWIO_GCC_BOOT_ROM_AHB_CFG_SREGR_ATTR 0x3 +#define HWIO_GCC_BOOT_ROM_AHB_CFG_SREGR_IN \ + in_dword_masked(HWIO_GCC_BOOT_ROM_AHB_CFG_SREGR_ADDR, HWIO_GCC_BOOT_ROM_AHB_CFG_SREGR_RMSK) +#define HWIO_GCC_BOOT_ROM_AHB_CFG_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_BOOT_ROM_AHB_CFG_SREGR_ADDR, m) +#define HWIO_GCC_BOOT_ROM_AHB_CFG_SREGR_OUT(v) \ + out_dword(HWIO_GCC_BOOT_ROM_AHB_CFG_SREGR_ADDR,v) +#define HWIO_GCC_BOOT_ROM_AHB_CFG_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_BOOT_ROM_AHB_CFG_SREGR_ADDR,m,v,HWIO_GCC_BOOT_ROM_AHB_CFG_SREGR_IN) +#define HWIO_GCC_BOOT_ROM_AHB_CFG_SREGR_MEM_CORE_OFF_TIMER_BMSK 0xfc000000 +#define HWIO_GCC_BOOT_ROM_AHB_CFG_SREGR_MEM_CORE_OFF_TIMER_SHFT 0x1a +#define HWIO_GCC_BOOT_ROM_AHB_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_BMSK 0x2000000 +#define HWIO_GCC_BOOT_ROM_AHB_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_SHFT 0x19 +#define HWIO_GCC_BOOT_ROM_AHB_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_BMSK 0x1000000 +#define HWIO_GCC_BOOT_ROM_AHB_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_SHFT 0x18 +#define HWIO_GCC_BOOT_ROM_AHB_CFG_SREGR_MEM_PERIPH_ON_STATUS_BMSK 0x800000 +#define HWIO_GCC_BOOT_ROM_AHB_CFG_SREGR_MEM_PERIPH_ON_STATUS_SHFT 0x17 +#define HWIO_GCC_BOOT_ROM_AHB_CFG_SREGR_MEM_CORE_ON_STATUS_BMSK 0x400000 +#define HWIO_GCC_BOOT_ROM_AHB_CFG_SREGR_MEM_CORE_ON_STATUS_SHFT 0x16 +#define HWIO_GCC_BOOT_ROM_AHB_CFG_SREGR_MEM_CPH_TIMER_BMSK 0x3f0000 +#define HWIO_GCC_BOOT_ROM_AHB_CFG_SREGR_MEM_CPH_TIMER_SHFT 0x10 +#define HWIO_GCC_BOOT_ROM_AHB_CFG_SREGR_SLEEP_TIMER_BMSK 0xff00 +#define HWIO_GCC_BOOT_ROM_AHB_CFG_SREGR_SLEEP_TIMER_SHFT 0x8 +#define HWIO_GCC_BOOT_ROM_AHB_CFG_SREGR_WAKEUP_TIMER_BMSK 0xff +#define HWIO_GCC_BOOT_ROM_AHB_CFG_SREGR_WAKEUP_TIMER_SHFT 0x0 + +#define HWIO_GCC_TLMM_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002a000) +#define HWIO_GCC_TLMM_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002a000) +#define HWIO_GCC_TLMM_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002a000) +#define HWIO_GCC_TLMM_BCR_RMSK 0x1 +#define HWIO_GCC_TLMM_BCR_ATTR 0x3 +#define HWIO_GCC_TLMM_BCR_IN \ + in_dword_masked(HWIO_GCC_TLMM_BCR_ADDR, HWIO_GCC_TLMM_BCR_RMSK) +#define HWIO_GCC_TLMM_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_TLMM_BCR_ADDR, m) +#define HWIO_GCC_TLMM_BCR_OUT(v) \ + out_dword(HWIO_GCC_TLMM_BCR_ADDR,v) +#define HWIO_GCC_TLMM_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TLMM_BCR_ADDR,m,v,HWIO_GCC_TLMM_BCR_IN) +#define HWIO_GCC_TLMM_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_TLMM_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_TLMM_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_TLMM_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TLMM_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002a004) +#define HWIO_GCC_TLMM_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002a004) +#define HWIO_GCC_TLMM_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002a004) +#define HWIO_GCC_TLMM_AHB_CBCR_RMSK 0x81d0000e +#define HWIO_GCC_TLMM_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_TLMM_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_TLMM_AHB_CBCR_ADDR, HWIO_GCC_TLMM_AHB_CBCR_RMSK) +#define HWIO_GCC_TLMM_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_TLMM_AHB_CBCR_ADDR, m) +#define HWIO_GCC_TLMM_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_TLMM_AHB_CBCR_ADDR,v) +#define HWIO_GCC_TLMM_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TLMM_AHB_CBCR_ADDR,m,v,HWIO_GCC_TLMM_AHB_CBCR_IN) +#define HWIO_GCC_TLMM_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TLMM_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TLMM_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_TLMM_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_TLMM_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_TLMM_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_TLMM_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_TLMM_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_TLMM_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_TLMM_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_TLMM_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_TLMM_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_TLMM_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_TLMM_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_TLMM_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_TLMM_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_TLMM_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_TLMM_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_TLMM_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_TLMM_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TLMM_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002a008) +#define HWIO_GCC_TLMM_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002a008) +#define HWIO_GCC_TLMM_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002a008) +#define HWIO_GCC_TLMM_CBCR_RMSK 0x81d00004 +#define HWIO_GCC_TLMM_CBCR_ATTR 0x3 +#define HWIO_GCC_TLMM_CBCR_IN \ + in_dword_masked(HWIO_GCC_TLMM_CBCR_ADDR, HWIO_GCC_TLMM_CBCR_RMSK) +#define HWIO_GCC_TLMM_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_TLMM_CBCR_ADDR, m) +#define HWIO_GCC_TLMM_CBCR_OUT(v) \ + out_dword(HWIO_GCC_TLMM_CBCR_ADDR,v) +#define HWIO_GCC_TLMM_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TLMM_CBCR_ADDR,m,v,HWIO_GCC_TLMM_CBCR_IN) +#define HWIO_GCC_TLMM_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TLMM_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TLMM_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_TLMM_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_TLMM_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_TLMM_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_TLMM_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_TLMM_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_TLMM_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_TLMM_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_TLMM_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_TLMM_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_TLMM_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_TLMM_CBCR_CLK_ARES_RESET_FVAL 0x1 + +#define HWIO_GCC_AOSS_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002c000) +#define HWIO_GCC_AOSS_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002c000) +#define HWIO_GCC_AOSS_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002c000) +#define HWIO_GCC_AOSS_BCR_RMSK 0x1 +#define HWIO_GCC_AOSS_BCR_ATTR 0x3 +#define HWIO_GCC_AOSS_BCR_IN \ + in_dword_masked(HWIO_GCC_AOSS_BCR_ADDR, HWIO_GCC_AOSS_BCR_RMSK) +#define HWIO_GCC_AOSS_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_AOSS_BCR_ADDR, m) +#define HWIO_GCC_AOSS_BCR_OUT(v) \ + out_dword(HWIO_GCC_AOSS_BCR_ADDR,v) +#define HWIO_GCC_AOSS_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AOSS_BCR_ADDR,m,v,HWIO_GCC_AOSS_BCR_IN) +#define HWIO_GCC_AOSS_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_AOSS_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_AOSS_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_AOSS_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_AOSS_CNOC_M_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002c004) +#define HWIO_GCC_AOSS_CNOC_M_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002c004) +#define HWIO_GCC_AOSS_CNOC_M_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002c004) +#define HWIO_GCC_AOSS_CNOC_M_AHB_CBCR_RMSK 0x81d00005 +#define HWIO_GCC_AOSS_CNOC_M_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_AOSS_CNOC_M_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_AOSS_CNOC_M_AHB_CBCR_ADDR, HWIO_GCC_AOSS_CNOC_M_AHB_CBCR_RMSK) +#define HWIO_GCC_AOSS_CNOC_M_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_AOSS_CNOC_M_AHB_CBCR_ADDR, m) +#define HWIO_GCC_AOSS_CNOC_M_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_AOSS_CNOC_M_AHB_CBCR_ADDR,v) +#define HWIO_GCC_AOSS_CNOC_M_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AOSS_CNOC_M_AHB_CBCR_ADDR,m,v,HWIO_GCC_AOSS_CNOC_M_AHB_CBCR_IN) +#define HWIO_GCC_AOSS_CNOC_M_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_AOSS_CNOC_M_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_AOSS_CNOC_M_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_AOSS_CNOC_M_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_AOSS_CNOC_M_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_AOSS_CNOC_M_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_AOSS_CNOC_M_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_AOSS_CNOC_M_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_AOSS_CNOC_M_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_AOSS_CNOC_M_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_AOSS_CNOC_M_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_AOSS_CNOC_M_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_AOSS_CNOC_M_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_AOSS_CNOC_M_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_AOSS_CNOC_M_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_AOSS_CNOC_M_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_AOSS_CNOC_M_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AOSS_CNOC_M_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_AOSS_CNOC_S_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002c008) +#define HWIO_GCC_AOSS_CNOC_S_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002c008) +#define HWIO_GCC_AOSS_CNOC_S_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002c008) +#define HWIO_GCC_AOSS_CNOC_S_AHB_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_AOSS_CNOC_S_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_AOSS_CNOC_S_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_AOSS_CNOC_S_AHB_CBCR_ADDR, HWIO_GCC_AOSS_CNOC_S_AHB_CBCR_RMSK) +#define HWIO_GCC_AOSS_CNOC_S_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_AOSS_CNOC_S_AHB_CBCR_ADDR, m) +#define HWIO_GCC_AOSS_CNOC_S_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_AOSS_CNOC_S_AHB_CBCR_ADDR,v) +#define HWIO_GCC_AOSS_CNOC_S_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AOSS_CNOC_S_AHB_CBCR_ADDR,m,v,HWIO_GCC_AOSS_CNOC_S_AHB_CBCR_IN) +#define HWIO_GCC_AOSS_CNOC_S_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_AOSS_CNOC_S_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_AOSS_CNOC_S_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_AOSS_CNOC_S_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_AOSS_CNOC_S_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_AOSS_CNOC_S_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_AOSS_CNOC_S_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_AOSS_CNOC_S_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_AOSS_CNOC_S_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_AOSS_CNOC_S_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_AOSS_CNOC_S_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_AOSS_CNOC_S_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_AOSS_CNOC_S_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_AOSS_CNOC_S_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_AOSS_CNOC_S_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_AOSS_CNOC_S_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_AOSS_CNOC_S_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_AOSS_CNOC_S_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_AOSS_CNOC_S_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_AOSS_CNOC_S_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_AOSS_CNOC_S_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_AOSS_CNOC_S_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_AOSS_CNOC_S_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AOSS_CNOC_S_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_AOSS_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002c00c) +#define HWIO_GCC_AOSS_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002c00c) +#define HWIO_GCC_AOSS_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002c00c) +#define HWIO_GCC_AOSS_AT_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_AOSS_AT_CBCR_ATTR 0x3 +#define HWIO_GCC_AOSS_AT_CBCR_IN \ + in_dword_masked(HWIO_GCC_AOSS_AT_CBCR_ADDR, HWIO_GCC_AOSS_AT_CBCR_RMSK) +#define HWIO_GCC_AOSS_AT_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_AOSS_AT_CBCR_ADDR, m) +#define HWIO_GCC_AOSS_AT_CBCR_OUT(v) \ + out_dword(HWIO_GCC_AOSS_AT_CBCR_ADDR,v) +#define HWIO_GCC_AOSS_AT_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AOSS_AT_CBCR_ADDR,m,v,HWIO_GCC_AOSS_AT_CBCR_IN) +#define HWIO_GCC_AOSS_AT_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_AOSS_AT_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_AOSS_AT_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_AOSS_AT_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_AOSS_AT_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_AOSS_AT_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_AOSS_AT_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_AOSS_AT_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_AOSS_AT_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_AOSS_AT_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_AOSS_AT_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_AOSS_AT_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_AOSS_AT_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_AOSS_AT_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_AOSS_AT_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_AOSS_AT_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_AOSS_AT_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_AOSS_AT_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_AOSS_AT_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_AOSS_AT_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_AOSS_AT_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_AOSS_AT_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_AOSS_AT_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AOSS_AT_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPDM_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00030000) +#define HWIO_GCC_SPDM_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00030000) +#define HWIO_GCC_SPDM_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00030000) +#define HWIO_GCC_SPDM_BCR_RMSK 0x1 +#define HWIO_GCC_SPDM_BCR_ATTR 0x3 +#define HWIO_GCC_SPDM_BCR_IN \ + in_dword_masked(HWIO_GCC_SPDM_BCR_ADDR, HWIO_GCC_SPDM_BCR_RMSK) +#define HWIO_GCC_SPDM_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_SPDM_BCR_ADDR, m) +#define HWIO_GCC_SPDM_BCR_OUT(v) \ + out_dword(HWIO_GCC_SPDM_BCR_ADDR,v) +#define HWIO_GCC_SPDM_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPDM_BCR_ADDR,m,v,HWIO_GCC_SPDM_BCR_IN) +#define HWIO_GCC_SPDM_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_SPDM_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_SPDM_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPDM_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPDM_FF_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00030004) +#define HWIO_GCC_SPDM_FF_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00030004) +#define HWIO_GCC_SPDM_FF_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00030004) +#define HWIO_GCC_SPDM_FF_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_SPDM_FF_CBCR_ATTR 0x3 +#define HWIO_GCC_SPDM_FF_CBCR_IN \ + in_dword_masked(HWIO_GCC_SPDM_FF_CBCR_ADDR, HWIO_GCC_SPDM_FF_CBCR_RMSK) +#define HWIO_GCC_SPDM_FF_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_SPDM_FF_CBCR_ADDR, m) +#define HWIO_GCC_SPDM_FF_CBCR_OUT(v) \ + out_dword(HWIO_GCC_SPDM_FF_CBCR_ADDR,v) +#define HWIO_GCC_SPDM_FF_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPDM_FF_CBCR_ADDR,m,v,HWIO_GCC_SPDM_FF_CBCR_IN) +#define HWIO_GCC_SPDM_FF_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SPDM_FF_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SPDM_FF_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_SPDM_FF_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_SPDM_FF_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_SPDM_FF_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_SPDM_FF_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_SPDM_FF_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_SPDM_FF_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_SPDM_FF_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_SPDM_FF_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SPDM_FF_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_SPDM_FF_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SPDM_FF_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SPDM_FF_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPDM_FF_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00030008) +#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00030008) +#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00030008) +#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_RMSK 0x81d00005 +#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_ATTR 0x3 +#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_IN \ + in_dword_masked(HWIO_GCC_SPDM_MEMNOC_CY_CBCR_ADDR, HWIO_GCC_SPDM_MEMNOC_CY_CBCR_RMSK) +#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_SPDM_MEMNOC_CY_CBCR_ADDR, m) +#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_OUT(v) \ + out_dword(HWIO_GCC_SPDM_MEMNOC_CY_CBCR_ADDR,v) +#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPDM_MEMNOC_CY_CBCR_ADDR,m,v,HWIO_GCC_SPDM_MEMNOC_CY_CBCR_IN) +#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPDM_SNOC_CY_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003000c) +#define HWIO_GCC_SPDM_SNOC_CY_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003000c) +#define HWIO_GCC_SPDM_SNOC_CY_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003000c) +#define HWIO_GCC_SPDM_SNOC_CY_CBCR_RMSK 0x81d00005 +#define HWIO_GCC_SPDM_SNOC_CY_CBCR_ATTR 0x3 +#define HWIO_GCC_SPDM_SNOC_CY_CBCR_IN \ + in_dword_masked(HWIO_GCC_SPDM_SNOC_CY_CBCR_ADDR, HWIO_GCC_SPDM_SNOC_CY_CBCR_RMSK) +#define HWIO_GCC_SPDM_SNOC_CY_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_SPDM_SNOC_CY_CBCR_ADDR, m) +#define HWIO_GCC_SPDM_SNOC_CY_CBCR_OUT(v) \ + out_dword(HWIO_GCC_SPDM_SNOC_CY_CBCR_ADDR,v) +#define HWIO_GCC_SPDM_SNOC_CY_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPDM_SNOC_CY_CBCR_ADDR,m,v,HWIO_GCC_SPDM_SNOC_CY_CBCR_IN) +#define HWIO_GCC_SPDM_SNOC_CY_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SPDM_SNOC_CY_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SPDM_SNOC_CY_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_SPDM_SNOC_CY_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_SPDM_SNOC_CY_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_SPDM_SNOC_CY_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_SPDM_SNOC_CY_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_SPDM_SNOC_CY_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_SPDM_SNOC_CY_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_SPDM_SNOC_CY_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_SPDM_SNOC_CY_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_SPDM_SNOC_CY_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_SPDM_SNOC_CY_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SPDM_SNOC_CY_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_SPDM_SNOC_CY_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SPDM_SNOC_CY_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SPDM_SNOC_CY_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPDM_SNOC_CY_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00030010) +#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00030010) +#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00030010) +#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_ATTR 0x3 +#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_IN \ + in_dword_masked(HWIO_GCC_SPDM_DEBUG_CY_CBCR_ADDR, HWIO_GCC_SPDM_DEBUG_CY_CBCR_RMSK) +#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_SPDM_DEBUG_CY_CBCR_ADDR, m) +#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_OUT(v) \ + out_dword(HWIO_GCC_SPDM_DEBUG_CY_CBCR_ADDR,v) +#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPDM_DEBUG_CY_CBCR_ADDR,m,v,HWIO_GCC_SPDM_DEBUG_CY_CBCR_IN) +#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPDM_PNOC_CY_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00030014) +#define HWIO_GCC_SPDM_PNOC_CY_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00030014) +#define HWIO_GCC_SPDM_PNOC_CY_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00030014) +#define HWIO_GCC_SPDM_PNOC_CY_CBCR_RMSK 0x81d00005 +#define HWIO_GCC_SPDM_PNOC_CY_CBCR_ATTR 0x3 +#define HWIO_GCC_SPDM_PNOC_CY_CBCR_IN \ + in_dword_masked(HWIO_GCC_SPDM_PNOC_CY_CBCR_ADDR, HWIO_GCC_SPDM_PNOC_CY_CBCR_RMSK) +#define HWIO_GCC_SPDM_PNOC_CY_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_SPDM_PNOC_CY_CBCR_ADDR, m) +#define HWIO_GCC_SPDM_PNOC_CY_CBCR_OUT(v) \ + out_dword(HWIO_GCC_SPDM_PNOC_CY_CBCR_ADDR,v) +#define HWIO_GCC_SPDM_PNOC_CY_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPDM_PNOC_CY_CBCR_ADDR,m,v,HWIO_GCC_SPDM_PNOC_CY_CBCR_IN) +#define HWIO_GCC_SPDM_PNOC_CY_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SPDM_PNOC_CY_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SPDM_PNOC_CY_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_SPDM_PNOC_CY_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_SPDM_PNOC_CY_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_SPDM_PNOC_CY_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_SPDM_PNOC_CY_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_SPDM_PNOC_CY_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_SPDM_PNOC_CY_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_SPDM_PNOC_CY_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_SPDM_PNOC_CY_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_SPDM_PNOC_CY_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_SPDM_PNOC_CY_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SPDM_PNOC_CY_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_SPDM_PNOC_CY_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SPDM_PNOC_CY_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SPDM_PNOC_CY_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPDM_PNOC_CY_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPDM_MEMNOC_CY_DIV_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00030018) +#define HWIO_GCC_SPDM_MEMNOC_CY_DIV_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00030018) +#define HWIO_GCC_SPDM_MEMNOC_CY_DIV_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00030018) +#define HWIO_GCC_SPDM_MEMNOC_CY_DIV_CDIVR_RMSK 0xf +#define HWIO_GCC_SPDM_MEMNOC_CY_DIV_CDIVR_ATTR 0x3 +#define HWIO_GCC_SPDM_MEMNOC_CY_DIV_CDIVR_IN \ + in_dword_masked(HWIO_GCC_SPDM_MEMNOC_CY_DIV_CDIVR_ADDR, HWIO_GCC_SPDM_MEMNOC_CY_DIV_CDIVR_RMSK) +#define HWIO_GCC_SPDM_MEMNOC_CY_DIV_CDIVR_INM(m) \ + in_dword_masked(HWIO_GCC_SPDM_MEMNOC_CY_DIV_CDIVR_ADDR, m) +#define HWIO_GCC_SPDM_MEMNOC_CY_DIV_CDIVR_OUT(v) \ + out_dword(HWIO_GCC_SPDM_MEMNOC_CY_DIV_CDIVR_ADDR,v) +#define HWIO_GCC_SPDM_MEMNOC_CY_DIV_CDIVR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPDM_MEMNOC_CY_DIV_CDIVR_ADDR,m,v,HWIO_GCC_SPDM_MEMNOC_CY_DIV_CDIVR_IN) +#define HWIO_GCC_SPDM_MEMNOC_CY_DIV_CDIVR_CLK_DIV_BMSK 0xf +#define HWIO_GCC_SPDM_MEMNOC_CY_DIV_CDIVR_CLK_DIV_SHFT 0x0 + +#define HWIO_GCC_SPDM_SNOC_CY_DIV_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003001c) +#define HWIO_GCC_SPDM_SNOC_CY_DIV_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003001c) +#define HWIO_GCC_SPDM_SNOC_CY_DIV_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003001c) +#define HWIO_GCC_SPDM_SNOC_CY_DIV_CDIVR_RMSK 0xf +#define HWIO_GCC_SPDM_SNOC_CY_DIV_CDIVR_ATTR 0x3 +#define HWIO_GCC_SPDM_SNOC_CY_DIV_CDIVR_IN \ + in_dword_masked(HWIO_GCC_SPDM_SNOC_CY_DIV_CDIVR_ADDR, HWIO_GCC_SPDM_SNOC_CY_DIV_CDIVR_RMSK) +#define HWIO_GCC_SPDM_SNOC_CY_DIV_CDIVR_INM(m) \ + in_dword_masked(HWIO_GCC_SPDM_SNOC_CY_DIV_CDIVR_ADDR, m) +#define HWIO_GCC_SPDM_SNOC_CY_DIV_CDIVR_OUT(v) \ + out_dword(HWIO_GCC_SPDM_SNOC_CY_DIV_CDIVR_ADDR,v) +#define HWIO_GCC_SPDM_SNOC_CY_DIV_CDIVR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPDM_SNOC_CY_DIV_CDIVR_ADDR,m,v,HWIO_GCC_SPDM_SNOC_CY_DIV_CDIVR_IN) +#define HWIO_GCC_SPDM_SNOC_CY_DIV_CDIVR_CLK_DIV_BMSK 0xf +#define HWIO_GCC_SPDM_SNOC_CY_DIV_CDIVR_CLK_DIV_SHFT 0x0 + +#define HWIO_GCC_SPDM_DEBUG_CY_DIV_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00030020) +#define HWIO_GCC_SPDM_DEBUG_CY_DIV_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00030020) +#define HWIO_GCC_SPDM_DEBUG_CY_DIV_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00030020) +#define HWIO_GCC_SPDM_DEBUG_CY_DIV_CDIVR_RMSK 0xf +#define HWIO_GCC_SPDM_DEBUG_CY_DIV_CDIVR_ATTR 0x3 +#define HWIO_GCC_SPDM_DEBUG_CY_DIV_CDIVR_IN \ + in_dword_masked(HWIO_GCC_SPDM_DEBUG_CY_DIV_CDIVR_ADDR, HWIO_GCC_SPDM_DEBUG_CY_DIV_CDIVR_RMSK) +#define HWIO_GCC_SPDM_DEBUG_CY_DIV_CDIVR_INM(m) \ + in_dword_masked(HWIO_GCC_SPDM_DEBUG_CY_DIV_CDIVR_ADDR, m) +#define HWIO_GCC_SPDM_DEBUG_CY_DIV_CDIVR_OUT(v) \ + out_dword(HWIO_GCC_SPDM_DEBUG_CY_DIV_CDIVR_ADDR,v) +#define HWIO_GCC_SPDM_DEBUG_CY_DIV_CDIVR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPDM_DEBUG_CY_DIV_CDIVR_ADDR,m,v,HWIO_GCC_SPDM_DEBUG_CY_DIV_CDIVR_IN) +#define HWIO_GCC_SPDM_DEBUG_CY_DIV_CDIVR_CLK_DIV_BMSK 0xf +#define HWIO_GCC_SPDM_DEBUG_CY_DIV_CDIVR_CLK_DIV_SHFT 0x0 + +#define HWIO_GCC_CE1_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00031000) +#define HWIO_GCC_CE1_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00031000) +#define HWIO_GCC_CE1_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00031000) +#define HWIO_GCC_CE1_BCR_RMSK 0x1 +#define HWIO_GCC_CE1_BCR_ATTR 0x3 +#define HWIO_GCC_CE1_BCR_IN \ + in_dword_masked(HWIO_GCC_CE1_BCR_ADDR, HWIO_GCC_CE1_BCR_RMSK) +#define HWIO_GCC_CE1_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_CE1_BCR_ADDR, m) +#define HWIO_GCC_CE1_BCR_OUT(v) \ + out_dword(HWIO_GCC_CE1_BCR_ADDR,v) +#define HWIO_GCC_CE1_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CE1_BCR_ADDR,m,v,HWIO_GCC_CE1_BCR_IN) +#define HWIO_GCC_CE1_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_CE1_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_CE1_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_CE1_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CE1_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00031004) +#define HWIO_GCC_CE1_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00031004) +#define HWIO_GCC_CE1_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00031004) +#define HWIO_GCC_CE1_CBCR_RMSK 0x81d07004 +#define HWIO_GCC_CE1_CBCR_ATTR 0x3 +#define HWIO_GCC_CE1_CBCR_IN \ + in_dword_masked(HWIO_GCC_CE1_CBCR_ADDR, HWIO_GCC_CE1_CBCR_RMSK) +#define HWIO_GCC_CE1_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_CE1_CBCR_ADDR, m) +#define HWIO_GCC_CE1_CBCR_OUT(v) \ + out_dword(HWIO_GCC_CE1_CBCR_ADDR,v) +#define HWIO_GCC_CE1_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CE1_CBCR_ADDR,m,v,HWIO_GCC_CE1_CBCR_IN) +#define HWIO_GCC_CE1_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_CE1_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_CE1_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_CE1_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_CE1_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_CE1_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_CE1_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_CE1_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_CE1_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_CE1_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_CE1_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_CE1_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_CE1_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CE1_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_CE1_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_CE1_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_CE1_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CE1_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_CE1_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_CE1_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_CE1_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CE1_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_CE1_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_CE1_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_CE1_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_CE1_CBCR_CLK_ARES_RESET_FVAL 0x1 + +#define HWIO_GCC_CE1_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00031008) +#define HWIO_GCC_CE1_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00031008) +#define HWIO_GCC_CE1_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00031008) +#define HWIO_GCC_CE1_SREGR_RMSK 0xf1ffffe +#define HWIO_GCC_CE1_SREGR_ATTR 0x3 +#define HWIO_GCC_CE1_SREGR_IN \ + in_dword_masked(HWIO_GCC_CE1_SREGR_ADDR, HWIO_GCC_CE1_SREGR_RMSK) +#define HWIO_GCC_CE1_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_CE1_SREGR_ADDR, m) +#define HWIO_GCC_CE1_SREGR_OUT(v) \ + out_dword(HWIO_GCC_CE1_SREGR_ADDR,v) +#define HWIO_GCC_CE1_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CE1_SREGR_ADDR,m,v,HWIO_GCC_CE1_SREGR_IN) +#define HWIO_GCC_CE1_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xf000000 +#define HWIO_GCC_CE1_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_CE1_SREGR_PWR_FSM_CLK_SEL_BMSK 0x100000 +#define HWIO_GCC_CE1_SREGR_PWR_FSM_CLK_SEL_SHFT 0x14 +#define HWIO_GCC_CE1_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xf0000 +#define HWIO_GCC_CE1_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_CE1_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_CE1_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_CE1_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_CE1_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_CE1_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_CE1_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_CE1_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_CE1_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_CE1_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_CE1_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_CE1_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_CE1_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_CE1_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_CE1_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_CE1_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_CE1_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_CE1_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_CE1_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_CE1_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_CE1_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_CE1_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_CE1_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_CE1_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_CE1_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_CE1_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_CE1_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_CE1_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_CE1_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_CE1_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CE1_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_CE1_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_CE1_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_CE1_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_CE1_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_CE1_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_CE1_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_CE1_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_CE1_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_CE1_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_CE1_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_CE1_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_CE1_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_CE1_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_CE1_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_CE1_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_CE1_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_CE1_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_CE1_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_CE1_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_CE1_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_CE1_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_CE1_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_CE1_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_CE1_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CE1_CFG_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003100c) +#define HWIO_GCC_CE1_CFG_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003100c) +#define HWIO_GCC_CE1_CFG_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003100c) +#define HWIO_GCC_CE1_CFG_SREGR_RMSK 0xffffffff +#define HWIO_GCC_CE1_CFG_SREGR_ATTR 0x3 +#define HWIO_GCC_CE1_CFG_SREGR_IN \ + in_dword_masked(HWIO_GCC_CE1_CFG_SREGR_ADDR, HWIO_GCC_CE1_CFG_SREGR_RMSK) +#define HWIO_GCC_CE1_CFG_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_CE1_CFG_SREGR_ADDR, m) +#define HWIO_GCC_CE1_CFG_SREGR_OUT(v) \ + out_dword(HWIO_GCC_CE1_CFG_SREGR_ADDR,v) +#define HWIO_GCC_CE1_CFG_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CE1_CFG_SREGR_ADDR,m,v,HWIO_GCC_CE1_CFG_SREGR_IN) +#define HWIO_GCC_CE1_CFG_SREGR_MEM_CORE_OFF_TIMER_BMSK 0xfc000000 +#define HWIO_GCC_CE1_CFG_SREGR_MEM_CORE_OFF_TIMER_SHFT 0x1a +#define HWIO_GCC_CE1_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_BMSK 0x2000000 +#define HWIO_GCC_CE1_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_SHFT 0x19 +#define HWIO_GCC_CE1_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_BMSK 0x1000000 +#define HWIO_GCC_CE1_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_SHFT 0x18 +#define HWIO_GCC_CE1_CFG_SREGR_MEM_PERIPH_ON_STATUS_BMSK 0x800000 +#define HWIO_GCC_CE1_CFG_SREGR_MEM_PERIPH_ON_STATUS_SHFT 0x17 +#define HWIO_GCC_CE1_CFG_SREGR_MEM_CORE_ON_STATUS_BMSK 0x400000 +#define HWIO_GCC_CE1_CFG_SREGR_MEM_CORE_ON_STATUS_SHFT 0x16 +#define HWIO_GCC_CE1_CFG_SREGR_MEM_CPH_TIMER_BMSK 0x3f0000 +#define HWIO_GCC_CE1_CFG_SREGR_MEM_CPH_TIMER_SHFT 0x10 +#define HWIO_GCC_CE1_CFG_SREGR_SLEEP_TIMER_BMSK 0xff00 +#define HWIO_GCC_CE1_CFG_SREGR_SLEEP_TIMER_SHFT 0x8 +#define HWIO_GCC_CE1_CFG_SREGR_WAKEUP_TIMER_BMSK 0xff +#define HWIO_GCC_CE1_CFG_SREGR_WAKEUP_TIMER_SHFT 0x0 + +#define HWIO_GCC_CE1_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00031010) +#define HWIO_GCC_CE1_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00031010) +#define HWIO_GCC_CE1_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00031010) +#define HWIO_GCC_CE1_AXI_CBCR_RMSK 0x81d00004 +#define HWIO_GCC_CE1_AXI_CBCR_ATTR 0x3 +#define HWIO_GCC_CE1_AXI_CBCR_IN \ + in_dword_masked(HWIO_GCC_CE1_AXI_CBCR_ADDR, HWIO_GCC_CE1_AXI_CBCR_RMSK) +#define HWIO_GCC_CE1_AXI_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_CE1_AXI_CBCR_ADDR, m) +#define HWIO_GCC_CE1_AXI_CBCR_OUT(v) \ + out_dword(HWIO_GCC_CE1_AXI_CBCR_ADDR,v) +#define HWIO_GCC_CE1_AXI_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CE1_AXI_CBCR_ADDR,m,v,HWIO_GCC_CE1_AXI_CBCR_IN) +#define HWIO_GCC_CE1_AXI_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_CE1_AXI_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_CE1_AXI_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_CE1_AXI_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_CE1_AXI_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_CE1_AXI_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_CE1_AXI_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_CE1_AXI_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_CE1_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_CE1_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_CE1_AXI_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_CE1_AXI_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_CE1_AXI_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_CE1_AXI_CBCR_CLK_ARES_RESET_FVAL 0x1 + +#define HWIO_GCC_CE1_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00031014) +#define HWIO_GCC_CE1_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00031014) +#define HWIO_GCC_CE1_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00031014) +#define HWIO_GCC_CE1_AHB_CBCR_RMSK 0x81d0000e +#define HWIO_GCC_CE1_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_CE1_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_CE1_AHB_CBCR_ADDR, HWIO_GCC_CE1_AHB_CBCR_RMSK) +#define HWIO_GCC_CE1_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_CE1_AHB_CBCR_ADDR, m) +#define HWIO_GCC_CE1_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_CE1_AHB_CBCR_ADDR,v) +#define HWIO_GCC_CE1_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CE1_AHB_CBCR_ADDR,m,v,HWIO_GCC_CE1_AHB_CBCR_IN) +#define HWIO_GCC_CE1_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_CE1_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_CE1_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_CE1_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_CE1_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_CE1_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_CE1_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_CE1_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_CE1_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_CE1_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_CE1_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_CE1_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_CE1_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_CE1_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_CE1_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_CE1_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_CE1_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_CE1_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_CE1_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_CE1_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CE_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003102c) +#define HWIO_GCC_RPMH_CE_CMD_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003102c) +#define HWIO_GCC_RPMH_CE_CMD_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003102c) +#define HWIO_GCC_RPMH_CE_CMD_DFSR_RMSK 0xffff +#define HWIO_GCC_RPMH_CE_CMD_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_CMD_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_CMD_DFSR_ADDR, HWIO_GCC_RPMH_CE_CMD_DFSR_RMSK) +#define HWIO_GCC_RPMH_CE_CMD_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_CMD_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CE_CMD_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_CMD_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CE_CMD_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_CMD_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CE_CMD_DFSR_IN) +#define HWIO_GCC_RPMH_CE_CMD_DFSR_RCG_SW_CTRL_BMSK 0x8000 +#define HWIO_GCC_RPMH_CE_CMD_DFSR_RCG_SW_CTRL_SHFT 0xf +#define HWIO_GCC_RPMH_CE_CMD_DFSR_SW_PERF_STATE_BMSK 0x7800 +#define HWIO_GCC_RPMH_CE_CMD_DFSR_SW_PERF_STATE_SHFT 0xb +#define HWIO_GCC_RPMH_CE_CMD_DFSR_SW_OVERRIDE_BMSK 0x400 +#define HWIO_GCC_RPMH_CE_CMD_DFSR_SW_OVERRIDE_SHFT 0xa +#define HWIO_GCC_RPMH_CE_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK 0x200 +#define HWIO_GCC_RPMH_CE_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT 0x9 +#define HWIO_GCC_RPMH_CE_CMD_DFSR_DFS_FSM_STATE_BMSK 0x1c0 +#define HWIO_GCC_RPMH_CE_CMD_DFSR_DFS_FSM_STATE_SHFT 0x6 +#define HWIO_GCC_RPMH_CE_CMD_DFSR_HW_CLK_CONTROL_BMSK 0x20 +#define HWIO_GCC_RPMH_CE_CMD_DFSR_HW_CLK_CONTROL_SHFT 0x5 +#define HWIO_GCC_RPMH_CE_CMD_DFSR_CURR_PERF_STATE_BMSK 0x1e +#define HWIO_GCC_RPMH_CE_CMD_DFSR_CURR_PERF_STATE_SHFT 0x1 +#define HWIO_GCC_RPMH_CE_CMD_DFSR_DFS_EN_BMSK 0x1 +#define HWIO_GCC_RPMH_CE_CMD_DFSR_DFS_EN_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_CMD_DFSR_DFS_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CMD_DFSR_DFS_EN_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00031034) +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00031034) +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00031034) +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_ADDR, HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_RMSK) +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_IN) +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00031038) +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00031038) +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00031038) +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_ADDR, HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_RMSK) +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_IN) +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003103c) +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003103c) +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003103c) +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_ADDR, HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_RMSK) +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_IN) +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00031040) +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00031040) +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00031040) +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_ADDR, HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_RMSK) +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_IN) +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00031044) +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00031044) +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00031044) +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_ADDR, HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_RMSK) +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_IN) +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00031048) +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00031048) +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00031048) +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_ADDR, HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_RMSK) +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_IN) +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003104c) +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003104c) +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003104c) +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_ADDR, HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_RMSK) +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_IN) +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00031050) +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00031050) +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00031050) +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_ADDR, HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_RMSK) +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_IN) +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00031054) +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00031054) +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00031054) +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_ADDR, HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_RMSK) +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_IN) +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00031058) +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00031058) +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00031058) +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_ADDR, HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_RMSK) +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_IN) +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003105c) +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003105c) +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003105c) +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_ADDR, HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_RMSK) +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_IN) +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00031060) +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00031060) +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00031060) +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_ADDR, HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_RMSK) +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_IN) +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00031064) +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00031064) +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00031064) +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_ADDR, HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_RMSK) +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_IN) +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00031068) +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00031068) +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00031068) +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_ADDR, HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_RMSK) +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_IN) +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003106c) +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003106c) +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003106c) +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_ADDR, HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_RMSK) +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_IN) +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00031070) +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00031070) +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00031070) +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_ADDR, HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_RMSK) +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_IN) +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_CE1_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00031018) +#define HWIO_GCC_CE1_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00031018) +#define HWIO_GCC_CE1_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00031018) +#define HWIO_GCC_CE1_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_CE1_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_CE1_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_CE1_CMD_RCGR_ADDR, HWIO_GCC_CE1_CMD_RCGR_RMSK) +#define HWIO_GCC_CE1_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_CE1_CMD_RCGR_ADDR, m) +#define HWIO_GCC_CE1_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_CE1_CMD_RCGR_ADDR,v) +#define HWIO_GCC_CE1_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CE1_CMD_RCGR_ADDR,m,v,HWIO_GCC_CE1_CMD_RCGR_IN) +#define HWIO_GCC_CE1_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_CE1_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_CE1_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_CE1_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_CE1_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_CE1_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_CE1_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_CE1_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_CE1_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_CE1_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_CE1_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CE1_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CE1_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003101c) +#define HWIO_GCC_CE1_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003101c) +#define HWIO_GCC_CE1_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003101c) +#define HWIO_GCC_CE1_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_CE1_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_CE1_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_CE1_CFG_RCGR_ADDR, HWIO_GCC_CE1_CFG_RCGR_RMSK) +#define HWIO_GCC_CE1_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_CE1_CFG_RCGR_ADDR, m) +#define HWIO_GCC_CE1_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_CE1_CFG_RCGR_ADDR,v) +#define HWIO_GCC_CE1_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CE1_CFG_RCGR_ADDR,m,v,HWIO_GCC_CE1_CFG_RCGR_IN) +#define HWIO_GCC_CE1_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_CE1_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_CE1_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_CE1_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_CE1_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_CE1_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_CE1_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_CE1_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00033000) +#define HWIO_GCC_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00033000) +#define HWIO_GCC_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00033000) +#define HWIO_GCC_AT_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_AT_CBCR_ATTR 0x3 +#define HWIO_GCC_AT_CBCR_IN \ + in_dword_masked(HWIO_GCC_AT_CBCR_ADDR, HWIO_GCC_AT_CBCR_RMSK) +#define HWIO_GCC_AT_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_AT_CBCR_ADDR, m) +#define HWIO_GCC_AT_CBCR_OUT(v) \ + out_dword(HWIO_GCC_AT_CBCR_ADDR,v) +#define HWIO_GCC_AT_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AT_CBCR_ADDR,m,v,HWIO_GCC_AT_CBCR_IN) +#define HWIO_GCC_AT_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_AT_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_AT_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_AT_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_AT_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_AT_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_AT_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_AT_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_AT_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_AT_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_AT_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_AT_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_AT_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_AT_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_AT_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_AT_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_AT_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_AT_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_AT_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_AT_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_AT_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_AT_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_AT_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AT_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00033004) +#define HWIO_GCC_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00033004) +#define HWIO_GCC_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00033004) +#define HWIO_GCC_AHB_CBCR_RMSK 0x81d00004 +#define HWIO_GCC_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_AHB_CBCR_ADDR, HWIO_GCC_AHB_CBCR_RMSK) +#define HWIO_GCC_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_AHB_CBCR_ADDR, m) +#define HWIO_GCC_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_AHB_CBCR_ADDR,v) +#define HWIO_GCC_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AHB_CBCR_ADDR,m,v,HWIO_GCC_AHB_CBCR_IN) +#define HWIO_GCC_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 + +#define HWIO_GCC_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00033008) +#define HWIO_GCC_XO_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00033008) +#define HWIO_GCC_XO_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00033008) +#define HWIO_GCC_XO_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_XO_CBCR_ATTR 0x3 +#define HWIO_GCC_XO_CBCR_IN \ + in_dword_masked(HWIO_GCC_XO_CBCR_ADDR, HWIO_GCC_XO_CBCR_RMSK) +#define HWIO_GCC_XO_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_XO_CBCR_ADDR, m) +#define HWIO_GCC_XO_CBCR_OUT(v) \ + out_dword(HWIO_GCC_XO_CBCR_ADDR,v) +#define HWIO_GCC_XO_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_XO_CBCR_ADDR,m,v,HWIO_GCC_XO_CBCR_IN) +#define HWIO_GCC_XO_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_XO_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_XO_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_XO_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_XO_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_XO_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_XO_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_XO_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_XO_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_XO_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_XO_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_XO_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_XO_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_XO_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_XO_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_XO_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_XO_DIV4_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003300c) +#define HWIO_GCC_XO_DIV4_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003300c) +#define HWIO_GCC_XO_DIV4_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003300c) +#define HWIO_GCC_XO_DIV4_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_XO_DIV4_CBCR_ATTR 0x3 +#define HWIO_GCC_XO_DIV4_CBCR_IN \ + in_dword_masked(HWIO_GCC_XO_DIV4_CBCR_ADDR, HWIO_GCC_XO_DIV4_CBCR_RMSK) +#define HWIO_GCC_XO_DIV4_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_XO_DIV4_CBCR_ADDR, m) +#define HWIO_GCC_XO_DIV4_CBCR_OUT(v) \ + out_dword(HWIO_GCC_XO_DIV4_CBCR_ADDR,v) +#define HWIO_GCC_XO_DIV4_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_XO_DIV4_CBCR_ADDR,m,v,HWIO_GCC_XO_DIV4_CBCR_IN) +#define HWIO_GCC_XO_DIV4_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_XO_DIV4_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_XO_DIV4_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_XO_DIV4_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_XO_DIV4_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_XO_DIV4_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_XO_DIV4_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_XO_DIV4_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_XO_DIV4_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_XO_DIV4_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_XO_DIV4_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_XO_DIV4_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_XO_DIV4_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_XO_DIV4_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_XO_DIV4_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_XO_DIV4_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_XO_DIV16_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00033010) +#define HWIO_GCC_XO_DIV16_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00033010) +#define HWIO_GCC_XO_DIV16_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00033010) +#define HWIO_GCC_XO_DIV16_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_XO_DIV16_CBCR_ATTR 0x3 +#define HWIO_GCC_XO_DIV16_CBCR_IN \ + in_dword_masked(HWIO_GCC_XO_DIV16_CBCR_ADDR, HWIO_GCC_XO_DIV16_CBCR_RMSK) +#define HWIO_GCC_XO_DIV16_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_XO_DIV16_CBCR_ADDR, m) +#define HWIO_GCC_XO_DIV16_CBCR_OUT(v) \ + out_dword(HWIO_GCC_XO_DIV16_CBCR_ADDR,v) +#define HWIO_GCC_XO_DIV16_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_XO_DIV16_CBCR_ADDR,m,v,HWIO_GCC_XO_DIV16_CBCR_IN) +#define HWIO_GCC_XO_DIV16_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_XO_DIV16_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_XO_DIV16_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_XO_DIV16_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_XO_DIV16_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_XO_DIV16_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_XO_DIV16_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_XO_DIV16_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_XO_DIV16_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_XO_DIV16_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_XO_DIV16_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_XO_DIV16_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_XO_DIV16_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_XO_DIV16_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_XO_DIV16_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_XO_DIV16_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SLEEP_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00033014) +#define HWIO_GCC_SLEEP_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00033014) +#define HWIO_GCC_SLEEP_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00033014) +#define HWIO_GCC_SLEEP_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_SLEEP_CBCR_ATTR 0x3 +#define HWIO_GCC_SLEEP_CBCR_IN \ + in_dword_masked(HWIO_GCC_SLEEP_CBCR_ADDR, HWIO_GCC_SLEEP_CBCR_RMSK) +#define HWIO_GCC_SLEEP_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_SLEEP_CBCR_ADDR, m) +#define HWIO_GCC_SLEEP_CBCR_OUT(v) \ + out_dword(HWIO_GCC_SLEEP_CBCR_ADDR,v) +#define HWIO_GCC_SLEEP_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SLEEP_CBCR_ADDR,m,v,HWIO_GCC_SLEEP_CBCR_IN) +#define HWIO_GCC_SLEEP_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SLEEP_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SLEEP_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_SLEEP_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_SLEEP_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_SLEEP_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_SLEEP_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_SLEEP_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_SLEEP_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_SLEEP_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_SLEEP_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SLEEP_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_SLEEP_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SLEEP_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SLEEP_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SLEEP_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_XO_DIV16_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00033018) +#define HWIO_GCC_XO_DIV16_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00033018) +#define HWIO_GCC_XO_DIV16_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00033018) +#define HWIO_GCC_XO_DIV16_CDIVR_RMSK 0xf +#define HWIO_GCC_XO_DIV16_CDIVR_ATTR 0x3 +#define HWIO_GCC_XO_DIV16_CDIVR_IN \ + in_dword_masked(HWIO_GCC_XO_DIV16_CDIVR_ADDR, HWIO_GCC_XO_DIV16_CDIVR_RMSK) +#define HWIO_GCC_XO_DIV16_CDIVR_INM(m) \ + in_dword_masked(HWIO_GCC_XO_DIV16_CDIVR_ADDR, m) +#define HWIO_GCC_XO_DIV16_CDIVR_OUT(v) \ + out_dword(HWIO_GCC_XO_DIV16_CDIVR_ADDR,v) +#define HWIO_GCC_XO_DIV16_CDIVR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_XO_DIV16_CDIVR_ADDR,m,v,HWIO_GCC_XO_DIV16_CDIVR_IN) +#define HWIO_GCC_XO_DIV16_CDIVR_CLK_DIV_BMSK 0xf +#define HWIO_GCC_XO_DIV16_CDIVR_CLK_DIV_SHFT 0x0 + +#define HWIO_GCC_XO_DIV4_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003301c) +#define HWIO_GCC_XO_DIV4_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003301c) +#define HWIO_GCC_XO_DIV4_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003301c) +#define HWIO_GCC_XO_DIV4_CDIVR_RMSK 0xf +#define HWIO_GCC_XO_DIV4_CDIVR_ATTR 0x3 +#define HWIO_GCC_XO_DIV4_CDIVR_IN \ + in_dword_masked(HWIO_GCC_XO_DIV4_CDIVR_ADDR, HWIO_GCC_XO_DIV4_CDIVR_RMSK) +#define HWIO_GCC_XO_DIV4_CDIVR_INM(m) \ + in_dword_masked(HWIO_GCC_XO_DIV4_CDIVR_ADDR, m) +#define HWIO_GCC_XO_DIV4_CDIVR_OUT(v) \ + out_dword(HWIO_GCC_XO_DIV4_CDIVR_ADDR,v) +#define HWIO_GCC_XO_DIV4_CDIVR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_XO_DIV4_CDIVR_ADDR,m,v,HWIO_GCC_XO_DIV4_CDIVR_IN) +#define HWIO_GCC_XO_DIV4_CDIVR_CLK_DIV_BMSK 0xf +#define HWIO_GCC_XO_DIV4_CDIVR_CLK_DIV_SHFT 0x0 + +#define HWIO_GCC_SLEEP_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00033020) +#define HWIO_GCC_SLEEP_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00033020) +#define HWIO_GCC_SLEEP_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00033020) +#define HWIO_GCC_SLEEP_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_SLEEP_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_SLEEP_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_SLEEP_CMD_RCGR_ADDR, HWIO_GCC_SLEEP_CMD_RCGR_RMSK) +#define HWIO_GCC_SLEEP_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_SLEEP_CMD_RCGR_ADDR, m) +#define HWIO_GCC_SLEEP_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_SLEEP_CMD_RCGR_ADDR,v) +#define HWIO_GCC_SLEEP_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SLEEP_CMD_RCGR_ADDR,m,v,HWIO_GCC_SLEEP_CMD_RCGR_IN) +#define HWIO_GCC_SLEEP_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_SLEEP_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_SLEEP_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_SLEEP_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_SLEEP_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_SLEEP_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_SLEEP_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_SLEEP_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_SLEEP_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_SLEEP_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_SLEEP_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SLEEP_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SLEEP_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00033024) +#define HWIO_GCC_SLEEP_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00033024) +#define HWIO_GCC_SLEEP_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00033024) +#define HWIO_GCC_SLEEP_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_SLEEP_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_SLEEP_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_SLEEP_CFG_RCGR_ADDR, HWIO_GCC_SLEEP_CFG_RCGR_RMSK) +#define HWIO_GCC_SLEEP_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_SLEEP_CFG_RCGR_ADDR, m) +#define HWIO_GCC_SLEEP_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_SLEEP_CFG_RCGR_ADDR,v) +#define HWIO_GCC_SLEEP_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SLEEP_CFG_RCGR_ADDR,m,v,HWIO_GCC_SLEEP_CFG_RCGR_IN) +#define HWIO_GCC_SLEEP_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_SLEEP_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_SLEEP_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_SLEEP_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_SLEEP_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_SLEEP_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_SLEEP_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_SLEEP_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_XO_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00033038) +#define HWIO_GCC_XO_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00033038) +#define HWIO_GCC_XO_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00033038) +#define HWIO_GCC_XO_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_XO_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_XO_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_XO_CMD_RCGR_ADDR, HWIO_GCC_XO_CMD_RCGR_RMSK) +#define HWIO_GCC_XO_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_XO_CMD_RCGR_ADDR, m) +#define HWIO_GCC_XO_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_XO_CMD_RCGR_ADDR,v) +#define HWIO_GCC_XO_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_XO_CMD_RCGR_ADDR,m,v,HWIO_GCC_XO_CMD_RCGR_IN) +#define HWIO_GCC_XO_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_XO_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_XO_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_XO_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_XO_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_XO_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_XO_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_XO_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_XO_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_XO_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_XO_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_XO_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_XO_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003303c) +#define HWIO_GCC_XO_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003303c) +#define HWIO_GCC_XO_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003303c) +#define HWIO_GCC_XO_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_XO_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_XO_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_XO_CFG_RCGR_ADDR, HWIO_GCC_XO_CFG_RCGR_RMSK) +#define HWIO_GCC_XO_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_XO_CFG_RCGR_ADDR, m) +#define HWIO_GCC_XO_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_XO_CFG_RCGR_ADDR,v) +#define HWIO_GCC_XO_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_XO_CFG_RCGR_ADDR,m,v,HWIO_GCC_XO_CFG_RCGR_IN) +#define HWIO_GCC_XO_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_XO_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_XO_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_XO_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_XO_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_XO_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_XO_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_XO_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_XO_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_XO_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_XO_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_XO_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_XO_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_XO_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_XO_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_XO_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_XO_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_XO_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_DDRSS_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00034000) +#define HWIO_GCC_DDRSS_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00034000) +#define HWIO_GCC_DDRSS_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00034000) +#define HWIO_GCC_DDRSS_BCR_RMSK 0x1 +#define HWIO_GCC_DDRSS_BCR_ATTR 0x3 +#define HWIO_GCC_DDRSS_BCR_IN \ + in_dword_masked(HWIO_GCC_DDRSS_BCR_ADDR, HWIO_GCC_DDRSS_BCR_RMSK) +#define HWIO_GCC_DDRSS_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_DDRSS_BCR_ADDR, m) +#define HWIO_GCC_DDRSS_BCR_OUT(v) \ + out_dword(HWIO_GCC_DDRSS_BCR_ADDR,v) +#define HWIO_GCC_DDRSS_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DDRSS_BCR_ADDR,m,v,HWIO_GCC_DDRSS_BCR_IN) +#define HWIO_GCC_DDRSS_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_DDRSS_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_DDRSS_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_DDRSS_MMNOC_SF_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000c048) +#define HWIO_GCC_DDRSS_MMNOC_SF_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c048) +#define HWIO_GCC_DDRSS_MMNOC_SF_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c048) +#define HWIO_GCC_DDRSS_MMNOC_SF_CBCR_RMSK 0x81f0000f +#define HWIO_GCC_DDRSS_MMNOC_SF_CBCR_ATTR 0x3 +#define HWIO_GCC_DDRSS_MMNOC_SF_CBCR_IN \ + in_dword_masked(HWIO_GCC_DDRSS_MMNOC_SF_CBCR_ADDR, HWIO_GCC_DDRSS_MMNOC_SF_CBCR_RMSK) +#define HWIO_GCC_DDRSS_MMNOC_SF_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_DDRSS_MMNOC_SF_CBCR_ADDR, m) +#define HWIO_GCC_DDRSS_MMNOC_SF_CBCR_OUT(v) \ + out_dword(HWIO_GCC_DDRSS_MMNOC_SF_CBCR_ADDR,v) +#define HWIO_GCC_DDRSS_MMNOC_SF_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DDRSS_MMNOC_SF_CBCR_ADDR,m,v,HWIO_GCC_DDRSS_MMNOC_SF_CBCR_IN) +#define HWIO_GCC_DDRSS_MMNOC_SF_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_DDRSS_MMNOC_SF_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_DDRSS_MMNOC_SF_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_DDRSS_MMNOC_SF_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_DDRSS_MMNOC_SF_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_DDRSS_MMNOC_SF_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_DDRSS_MMNOC_SF_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_DDRSS_MMNOC_SF_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_DDRSS_MMNOC_SF_CBCR_IGNORE_PMU_CLK_DIS_BMSK 0x200000 +#define HWIO_GCC_DDRSS_MMNOC_SF_CBCR_IGNORE_PMU_CLK_DIS_SHFT 0x15 +#define HWIO_GCC_DDRSS_MMNOC_SF_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_DDRSS_MMNOC_SF_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_DDRSS_MMNOC_SF_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_DDRSS_MMNOC_SF_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_DDRSS_MMNOC_SF_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_DDRSS_MMNOC_SF_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_DDRSS_MMNOC_SF_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_DDRSS_MMNOC_SF_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_DDRSS_MMNOC_SF_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_DDRSS_MMNOC_SF_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_DDRSS_MMNOC_SF_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_MMNOC_SF_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_DDRSS_MMNOC_SF_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_DDRSS_MMNOC_SF_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_DDRSS_MMNOC_SF_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_MMNOC_SF_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000c04c) +#define HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c04c) +#define HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c04c) +#define HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_RMSK 0x81f0000f +#define HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_ATTR 0x3 +#define HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_IN \ + in_dword_masked(HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_ADDR, HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_RMSK) +#define HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_ADDR, m) +#define HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_OUT(v) \ + out_dword(HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_ADDR,v) +#define HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_ADDR,m,v,HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_IN) +#define HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_IGNORE_PMU_CLK_DIS_BMSK 0x200000 +#define HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_IGNORE_PMU_CLK_DIS_SHFT 0x15 +#define HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_DDRSS_TCU_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000733cc) +#define HWIO_GCC_DDRSS_TCU_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000733cc) +#define HWIO_GCC_DDRSS_TCU_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000733cc) +#define HWIO_GCC_DDRSS_TCU_CBCR_RMSK 0x81f0000f +#define HWIO_GCC_DDRSS_TCU_CBCR_ATTR 0x3 +#define HWIO_GCC_DDRSS_TCU_CBCR_IN \ + in_dword_masked(HWIO_GCC_DDRSS_TCU_CBCR_ADDR, HWIO_GCC_DDRSS_TCU_CBCR_RMSK) +#define HWIO_GCC_DDRSS_TCU_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_DDRSS_TCU_CBCR_ADDR, m) +#define HWIO_GCC_DDRSS_TCU_CBCR_OUT(v) \ + out_dword(HWIO_GCC_DDRSS_TCU_CBCR_ADDR,v) +#define HWIO_GCC_DDRSS_TCU_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DDRSS_TCU_CBCR_ADDR,m,v,HWIO_GCC_DDRSS_TCU_CBCR_IN) +#define HWIO_GCC_DDRSS_TCU_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_DDRSS_TCU_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_DDRSS_TCU_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_DDRSS_TCU_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_DDRSS_TCU_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_DDRSS_TCU_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_DDRSS_TCU_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_DDRSS_TCU_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_DDRSS_TCU_CBCR_IGNORE_PMU_CLK_DIS_BMSK 0x200000 +#define HWIO_GCC_DDRSS_TCU_CBCR_IGNORE_PMU_CLK_DIS_SHFT 0x15 +#define HWIO_GCC_DDRSS_TCU_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_DDRSS_TCU_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_DDRSS_TCU_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_DDRSS_TCU_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_DDRSS_TCU_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_DDRSS_TCU_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_DDRSS_TCU_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_DDRSS_TCU_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_DDRSS_TCU_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_DDRSS_TCU_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_DDRSS_TCU_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_TCU_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_DDRSS_TCU_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_DDRSS_TCU_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_DDRSS_TCU_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_TCU_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_DDRSS_TURING_Q6_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00034004) +#define HWIO_GCC_DDRSS_TURING_Q6_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00034004) +#define HWIO_GCC_DDRSS_TURING_Q6_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00034004) +#define HWIO_GCC_DDRSS_TURING_Q6_AXI_CBCR_RMSK 0x81f0000f +#define HWIO_GCC_DDRSS_TURING_Q6_AXI_CBCR_ATTR 0x3 +#define HWIO_GCC_DDRSS_TURING_Q6_AXI_CBCR_IN \ + in_dword_masked(HWIO_GCC_DDRSS_TURING_Q6_AXI_CBCR_ADDR, HWIO_GCC_DDRSS_TURING_Q6_AXI_CBCR_RMSK) +#define HWIO_GCC_DDRSS_TURING_Q6_AXI_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_DDRSS_TURING_Q6_AXI_CBCR_ADDR, m) +#define HWIO_GCC_DDRSS_TURING_Q6_AXI_CBCR_OUT(v) \ + out_dword(HWIO_GCC_DDRSS_TURING_Q6_AXI_CBCR_ADDR,v) +#define HWIO_GCC_DDRSS_TURING_Q6_AXI_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DDRSS_TURING_Q6_AXI_CBCR_ADDR,m,v,HWIO_GCC_DDRSS_TURING_Q6_AXI_CBCR_IN) +#define HWIO_GCC_DDRSS_TURING_Q6_AXI_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_DDRSS_TURING_Q6_AXI_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_DDRSS_TURING_Q6_AXI_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_DDRSS_TURING_Q6_AXI_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_DDRSS_TURING_Q6_AXI_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_DDRSS_TURING_Q6_AXI_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_DDRSS_TURING_Q6_AXI_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_DDRSS_TURING_Q6_AXI_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_DDRSS_TURING_Q6_AXI_CBCR_IGNORE_PMU_CLK_DIS_BMSK 0x200000 +#define HWIO_GCC_DDRSS_TURING_Q6_AXI_CBCR_IGNORE_PMU_CLK_DIS_SHFT 0x15 +#define HWIO_GCC_DDRSS_TURING_Q6_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_DDRSS_TURING_Q6_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_DDRSS_TURING_Q6_AXI_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_DDRSS_TURING_Q6_AXI_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_DDRSS_TURING_Q6_AXI_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_DDRSS_TURING_Q6_AXI_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_DDRSS_TURING_Q6_AXI_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_DDRSS_TURING_Q6_AXI_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_DDRSS_TURING_Q6_AXI_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_DDRSS_TURING_Q6_AXI_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_DDRSS_TURING_Q6_AXI_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_TURING_Q6_AXI_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_DDRSS_TURING_Q6_AXI_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_DDRSS_TURING_Q6_AXI_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_DDRSS_TURING_Q6_AXI_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_TURING_Q6_AXI_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a288) +#define HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007a288) +#define HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007a288) +#define HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_RMSK 0x81f0000f +#define HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_ATTR 0x3 +#define HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_IN \ + in_dword_masked(HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_ADDR, HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_RMSK) +#define HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_ADDR, m) +#define HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_OUT(v) \ + out_dword(HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_ADDR,v) +#define HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_ADDR,m,v,HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_IN) +#define HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_IGNORE_PMU_CLK_DIS_BMSK 0x200000 +#define HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_IGNORE_PMU_CLK_DIS_SHFT 0x15 +#define HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_DDRSS_MODEM_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a28c) +#define HWIO_GCC_DDRSS_MODEM_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007a28c) +#define HWIO_GCC_DDRSS_MODEM_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007a28c) +#define HWIO_GCC_DDRSS_MODEM_CBCR_RMSK 0x81f0000f +#define HWIO_GCC_DDRSS_MODEM_CBCR_ATTR 0x3 +#define HWIO_GCC_DDRSS_MODEM_CBCR_IN \ + in_dword_masked(HWIO_GCC_DDRSS_MODEM_CBCR_ADDR, HWIO_GCC_DDRSS_MODEM_CBCR_RMSK) +#define HWIO_GCC_DDRSS_MODEM_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_DDRSS_MODEM_CBCR_ADDR, m) +#define HWIO_GCC_DDRSS_MODEM_CBCR_OUT(v) \ + out_dword(HWIO_GCC_DDRSS_MODEM_CBCR_ADDR,v) +#define HWIO_GCC_DDRSS_MODEM_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DDRSS_MODEM_CBCR_ADDR,m,v,HWIO_GCC_DDRSS_MODEM_CBCR_IN) +#define HWIO_GCC_DDRSS_MODEM_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_DDRSS_MODEM_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_DDRSS_MODEM_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_DDRSS_MODEM_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_DDRSS_MODEM_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_DDRSS_MODEM_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_DDRSS_MODEM_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_DDRSS_MODEM_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_DDRSS_MODEM_CBCR_IGNORE_PMU_CLK_DIS_BMSK 0x200000 +#define HWIO_GCC_DDRSS_MODEM_CBCR_IGNORE_PMU_CLK_DIS_SHFT 0x15 +#define HWIO_GCC_DDRSS_MODEM_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_DDRSS_MODEM_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_DDRSS_MODEM_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_DDRSS_MODEM_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_DDRSS_MODEM_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_DDRSS_MODEM_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_DDRSS_MODEM_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_DDRSS_MODEM_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_DDRSS_MODEM_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_DDRSS_MODEM_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_DDRSS_MODEM_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_MODEM_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_DDRSS_MODEM_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_DDRSS_MODEM_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_DDRSS_MODEM_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_MODEM_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_DDRSS_GPU_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00061154) +#define HWIO_GCC_DDRSS_GPU_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00061154) +#define HWIO_GCC_DDRSS_GPU_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00061154) +#define HWIO_GCC_DDRSS_GPU_AXI_CBCR_RMSK 0x81f0000f +#define HWIO_GCC_DDRSS_GPU_AXI_CBCR_ATTR 0x3 +#define HWIO_GCC_DDRSS_GPU_AXI_CBCR_IN \ + in_dword_masked(HWIO_GCC_DDRSS_GPU_AXI_CBCR_ADDR, HWIO_GCC_DDRSS_GPU_AXI_CBCR_RMSK) +#define HWIO_GCC_DDRSS_GPU_AXI_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_DDRSS_GPU_AXI_CBCR_ADDR, m) +#define HWIO_GCC_DDRSS_GPU_AXI_CBCR_OUT(v) \ + out_dword(HWIO_GCC_DDRSS_GPU_AXI_CBCR_ADDR,v) +#define HWIO_GCC_DDRSS_GPU_AXI_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DDRSS_GPU_AXI_CBCR_ADDR,m,v,HWIO_GCC_DDRSS_GPU_AXI_CBCR_IN) +#define HWIO_GCC_DDRSS_GPU_AXI_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_DDRSS_GPU_AXI_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_DDRSS_GPU_AXI_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_DDRSS_GPU_AXI_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_DDRSS_GPU_AXI_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_DDRSS_GPU_AXI_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_DDRSS_GPU_AXI_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_DDRSS_GPU_AXI_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_DDRSS_GPU_AXI_CBCR_IGNORE_PMU_CLK_DIS_BMSK 0x200000 +#define HWIO_GCC_DDRSS_GPU_AXI_CBCR_IGNORE_PMU_CLK_DIS_SHFT 0x15 +#define HWIO_GCC_DDRSS_GPU_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_DDRSS_GPU_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_DDRSS_GPU_AXI_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_DDRSS_GPU_AXI_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_DDRSS_GPU_AXI_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_DDRSS_GPU_AXI_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_DDRSS_GPU_AXI_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_DDRSS_GPU_AXI_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_DDRSS_GPU_AXI_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_DDRSS_GPU_AXI_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_DDRSS_GPU_AXI_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_GPU_AXI_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_DDRSS_GPU_AXI_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_DDRSS_GPU_AXI_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_DDRSS_GPU_AXI_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_GPU_AXI_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_DDRSS_PCIE_SF_QTB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000004c) +#define HWIO_GCC_DDRSS_PCIE_SF_QTB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000004c) +#define HWIO_GCC_DDRSS_PCIE_SF_QTB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000004c) +#define HWIO_GCC_DDRSS_PCIE_SF_QTB_CBCR_RMSK 0x81f0000e +#define HWIO_GCC_DDRSS_PCIE_SF_QTB_CBCR_ATTR 0x3 +#define HWIO_GCC_DDRSS_PCIE_SF_QTB_CBCR_IN \ + in_dword_masked(HWIO_GCC_DDRSS_PCIE_SF_QTB_CBCR_ADDR, HWIO_GCC_DDRSS_PCIE_SF_QTB_CBCR_RMSK) +#define HWIO_GCC_DDRSS_PCIE_SF_QTB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_DDRSS_PCIE_SF_QTB_CBCR_ADDR, m) +#define HWIO_GCC_DDRSS_PCIE_SF_QTB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_DDRSS_PCIE_SF_QTB_CBCR_ADDR,v) +#define HWIO_GCC_DDRSS_PCIE_SF_QTB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DDRSS_PCIE_SF_QTB_CBCR_ADDR,m,v,HWIO_GCC_DDRSS_PCIE_SF_QTB_CBCR_IN) +#define HWIO_GCC_DDRSS_PCIE_SF_QTB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_DDRSS_PCIE_SF_QTB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_DDRSS_PCIE_SF_QTB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_DDRSS_PCIE_SF_QTB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_DDRSS_PCIE_SF_QTB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_DDRSS_PCIE_SF_QTB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_DDRSS_PCIE_SF_QTB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_DDRSS_PCIE_SF_QTB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_DDRSS_PCIE_SF_QTB_CBCR_IGNORE_PMU_CLK_DIS_BMSK 0x200000 +#define HWIO_GCC_DDRSS_PCIE_SF_QTB_CBCR_IGNORE_PMU_CLK_DIS_SHFT 0x15 +#define HWIO_GCC_DDRSS_PCIE_SF_QTB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_DDRSS_PCIE_SF_QTB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_DDRSS_PCIE_SF_QTB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_DDRSS_PCIE_SF_QTB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_DDRSS_PCIE_SF_QTB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_DDRSS_PCIE_SF_QTB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_DDRSS_PCIE_SF_QTB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_DDRSS_PCIE_SF_QTB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_DDRSS_PCIE_SF_QTB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_DDRSS_PCIE_SF_QTB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_DDRSS_PCIE_SF_QTB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_PCIE_SF_QTB_CBCR_HW_CTL_ENABLE_FVAL 0x1 + +#define HWIO_GCC_DDRSS_SNOC_GC_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00034008) +#define HWIO_GCC_DDRSS_SNOC_GC_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00034008) +#define HWIO_GCC_DDRSS_SNOC_GC_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00034008) +#define HWIO_GCC_DDRSS_SNOC_GC_AXI_CBCR_RMSK 0x81f0000f +#define HWIO_GCC_DDRSS_SNOC_GC_AXI_CBCR_ATTR 0x3 +#define HWIO_GCC_DDRSS_SNOC_GC_AXI_CBCR_IN \ + in_dword_masked(HWIO_GCC_DDRSS_SNOC_GC_AXI_CBCR_ADDR, HWIO_GCC_DDRSS_SNOC_GC_AXI_CBCR_RMSK) +#define HWIO_GCC_DDRSS_SNOC_GC_AXI_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_DDRSS_SNOC_GC_AXI_CBCR_ADDR, m) +#define HWIO_GCC_DDRSS_SNOC_GC_AXI_CBCR_OUT(v) \ + out_dword(HWIO_GCC_DDRSS_SNOC_GC_AXI_CBCR_ADDR,v) +#define HWIO_GCC_DDRSS_SNOC_GC_AXI_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DDRSS_SNOC_GC_AXI_CBCR_ADDR,m,v,HWIO_GCC_DDRSS_SNOC_GC_AXI_CBCR_IN) +#define HWIO_GCC_DDRSS_SNOC_GC_AXI_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_DDRSS_SNOC_GC_AXI_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_DDRSS_SNOC_GC_AXI_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_DDRSS_SNOC_GC_AXI_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_DDRSS_SNOC_GC_AXI_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_DDRSS_SNOC_GC_AXI_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_DDRSS_SNOC_GC_AXI_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_DDRSS_SNOC_GC_AXI_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_DDRSS_SNOC_GC_AXI_CBCR_IGNORE_PMU_CLK_DIS_BMSK 0x200000 +#define HWIO_GCC_DDRSS_SNOC_GC_AXI_CBCR_IGNORE_PMU_CLK_DIS_SHFT 0x15 +#define HWIO_GCC_DDRSS_SNOC_GC_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_DDRSS_SNOC_GC_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_DDRSS_SNOC_GC_AXI_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_DDRSS_SNOC_GC_AXI_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_DDRSS_SNOC_GC_AXI_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_DDRSS_SNOC_GC_AXI_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_DDRSS_SNOC_GC_AXI_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_DDRSS_SNOC_GC_AXI_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_DDRSS_SNOC_GC_AXI_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_DDRSS_SNOC_GC_AXI_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_DDRSS_SNOC_GC_AXI_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_SNOC_GC_AXI_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_DDRSS_SNOC_GC_AXI_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_DDRSS_SNOC_GC_AXI_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_DDRSS_SNOC_GC_AXI_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_SNOC_GC_AXI_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_DDRSS_SNOC_SF_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003400c) +#define HWIO_GCC_DDRSS_SNOC_SF_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003400c) +#define HWIO_GCC_DDRSS_SNOC_SF_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003400c) +#define HWIO_GCC_DDRSS_SNOC_SF_AXI_CBCR_RMSK 0x81f0000f +#define HWIO_GCC_DDRSS_SNOC_SF_AXI_CBCR_ATTR 0x3 +#define HWIO_GCC_DDRSS_SNOC_SF_AXI_CBCR_IN \ + in_dword_masked(HWIO_GCC_DDRSS_SNOC_SF_AXI_CBCR_ADDR, HWIO_GCC_DDRSS_SNOC_SF_AXI_CBCR_RMSK) +#define HWIO_GCC_DDRSS_SNOC_SF_AXI_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_DDRSS_SNOC_SF_AXI_CBCR_ADDR, m) +#define HWIO_GCC_DDRSS_SNOC_SF_AXI_CBCR_OUT(v) \ + out_dword(HWIO_GCC_DDRSS_SNOC_SF_AXI_CBCR_ADDR,v) +#define HWIO_GCC_DDRSS_SNOC_SF_AXI_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DDRSS_SNOC_SF_AXI_CBCR_ADDR,m,v,HWIO_GCC_DDRSS_SNOC_SF_AXI_CBCR_IN) +#define HWIO_GCC_DDRSS_SNOC_SF_AXI_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_DDRSS_SNOC_SF_AXI_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_DDRSS_SNOC_SF_AXI_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_DDRSS_SNOC_SF_AXI_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_DDRSS_SNOC_SF_AXI_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_DDRSS_SNOC_SF_AXI_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_DDRSS_SNOC_SF_AXI_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_DDRSS_SNOC_SF_AXI_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_DDRSS_SNOC_SF_AXI_CBCR_IGNORE_PMU_CLK_DIS_BMSK 0x200000 +#define HWIO_GCC_DDRSS_SNOC_SF_AXI_CBCR_IGNORE_PMU_CLK_DIS_SHFT 0x15 +#define HWIO_GCC_DDRSS_SNOC_SF_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_DDRSS_SNOC_SF_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_DDRSS_SNOC_SF_AXI_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_DDRSS_SNOC_SF_AXI_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_DDRSS_SNOC_SF_AXI_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_DDRSS_SNOC_SF_AXI_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_DDRSS_SNOC_SF_AXI_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_DDRSS_SNOC_SF_AXI_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_DDRSS_SNOC_SF_AXI_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_DDRSS_SNOC_SF_AXI_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_DDRSS_SNOC_SF_AXI_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_SNOC_SF_AXI_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_DDRSS_SNOC_SF_AXI_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_DDRSS_SNOC_SF_AXI_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_DDRSS_SNOC_SF_AXI_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_SNOC_SF_AXI_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_DDRSS_CONFIG_NOC_SF_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00034010) +#define HWIO_GCC_DDRSS_CONFIG_NOC_SF_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00034010) +#define HWIO_GCC_DDRSS_CONFIG_NOC_SF_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00034010) +#define HWIO_GCC_DDRSS_CONFIG_NOC_SF_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_DDRSS_CONFIG_NOC_SF_CBCR_ATTR 0x3 +#define HWIO_GCC_DDRSS_CONFIG_NOC_SF_CBCR_IN \ + in_dword_masked(HWIO_GCC_DDRSS_CONFIG_NOC_SF_CBCR_ADDR, HWIO_GCC_DDRSS_CONFIG_NOC_SF_CBCR_RMSK) +#define HWIO_GCC_DDRSS_CONFIG_NOC_SF_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_DDRSS_CONFIG_NOC_SF_CBCR_ADDR, m) +#define HWIO_GCC_DDRSS_CONFIG_NOC_SF_CBCR_OUT(v) \ + out_dword(HWIO_GCC_DDRSS_CONFIG_NOC_SF_CBCR_ADDR,v) +#define HWIO_GCC_DDRSS_CONFIG_NOC_SF_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DDRSS_CONFIG_NOC_SF_CBCR_ADDR,m,v,HWIO_GCC_DDRSS_CONFIG_NOC_SF_CBCR_IN) +#define HWIO_GCC_DDRSS_CONFIG_NOC_SF_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_DDRSS_CONFIG_NOC_SF_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_DDRSS_CONFIG_NOC_SF_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_DDRSS_CONFIG_NOC_SF_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_DDRSS_CONFIG_NOC_SF_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_DDRSS_CONFIG_NOC_SF_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_DDRSS_CONFIG_NOC_SF_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_DDRSS_CONFIG_NOC_SF_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_DDRSS_CONFIG_NOC_SF_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_DDRSS_CONFIG_NOC_SF_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_DDRSS_CONFIG_NOC_SF_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_DDRSS_CONFIG_NOC_SF_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_DDRSS_CONFIG_NOC_SF_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_DDRSS_CONFIG_NOC_SF_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_DDRSS_CONFIG_NOC_SF_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_DDRSS_CONFIG_NOC_SF_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_DDRSS_CONFIG_NOC_SF_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_DDRSS_CONFIG_NOC_SF_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_DDRSS_CONFIG_NOC_SF_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_CONFIG_NOC_SF_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_DDRSS_CONFIG_NOC_SF_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_DDRSS_CONFIG_NOC_SF_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_DDRSS_CONFIG_NOC_SF_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_CONFIG_NOC_SF_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00034014) +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00034014) +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00034014) +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_DDRSS_CFG_AHB_CBCR_ADDR, HWIO_GCC_DDRSS_CFG_AHB_CBCR_RMSK) +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_DDRSS_CFG_AHB_CBCR_ADDR, m) +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_DDRSS_CFG_AHB_CBCR_ADDR,v) +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DDRSS_CFG_AHB_CBCR_ADDR,m,v,HWIO_GCC_DDRSS_CFG_AHB_CBCR_IN) +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MEMNOC_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00034018) +#define HWIO_GCC_MEMNOC_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00034018) +#define HWIO_GCC_MEMNOC_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00034018) +#define HWIO_GCC_MEMNOC_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_MEMNOC_CBCR_ATTR 0x3 +#define HWIO_GCC_MEMNOC_CBCR_IN \ + in_dword_masked(HWIO_GCC_MEMNOC_CBCR_ADDR, HWIO_GCC_MEMNOC_CBCR_RMSK) +#define HWIO_GCC_MEMNOC_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_MEMNOC_CBCR_ADDR, m) +#define HWIO_GCC_MEMNOC_CBCR_OUT(v) \ + out_dword(HWIO_GCC_MEMNOC_CBCR_ADDR,v) +#define HWIO_GCC_MEMNOC_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MEMNOC_CBCR_ADDR,m,v,HWIO_GCC_MEMNOC_CBCR_IN) +#define HWIO_GCC_MEMNOC_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_MEMNOC_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_MEMNOC_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_MEMNOC_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_MEMNOC_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_MEMNOC_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_MEMNOC_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_MEMNOC_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_MEMNOC_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_MEMNOC_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_MEMNOC_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_MEMNOC_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_MEMNOC_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_MEMNOC_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_MEMNOC_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_MEMNOC_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_MEMNOC_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_MEMNOC_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_MEMNOC_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_MEMNOC_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_MEMNOC_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_MEMNOC_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_MEMNOC_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MEMNOC_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_DDRSS_LPASS_SHUB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003514c) +#define HWIO_GCC_DDRSS_LPASS_SHUB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003514c) +#define HWIO_GCC_DDRSS_LPASS_SHUB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003514c) +#define HWIO_GCC_DDRSS_LPASS_SHUB_CBCR_RMSK 0x81f0000f +#define HWIO_GCC_DDRSS_LPASS_SHUB_CBCR_ATTR 0x3 +#define HWIO_GCC_DDRSS_LPASS_SHUB_CBCR_IN \ + in_dword_masked(HWIO_GCC_DDRSS_LPASS_SHUB_CBCR_ADDR, HWIO_GCC_DDRSS_LPASS_SHUB_CBCR_RMSK) +#define HWIO_GCC_DDRSS_LPASS_SHUB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_DDRSS_LPASS_SHUB_CBCR_ADDR, m) +#define HWIO_GCC_DDRSS_LPASS_SHUB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_DDRSS_LPASS_SHUB_CBCR_ADDR,v) +#define HWIO_GCC_DDRSS_LPASS_SHUB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DDRSS_LPASS_SHUB_CBCR_ADDR,m,v,HWIO_GCC_DDRSS_LPASS_SHUB_CBCR_IN) +#define HWIO_GCC_DDRSS_LPASS_SHUB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_DDRSS_LPASS_SHUB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_DDRSS_LPASS_SHUB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_DDRSS_LPASS_SHUB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_DDRSS_LPASS_SHUB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_DDRSS_LPASS_SHUB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_DDRSS_LPASS_SHUB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_DDRSS_LPASS_SHUB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_DDRSS_LPASS_SHUB_CBCR_IGNORE_PMU_CLK_DIS_BMSK 0x200000 +#define HWIO_GCC_DDRSS_LPASS_SHUB_CBCR_IGNORE_PMU_CLK_DIS_SHFT 0x15 +#define HWIO_GCC_DDRSS_LPASS_SHUB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_DDRSS_LPASS_SHUB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_DDRSS_LPASS_SHUB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_DDRSS_LPASS_SHUB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_DDRSS_LPASS_SHUB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_DDRSS_LPASS_SHUB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_DDRSS_LPASS_SHUB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_DDRSS_LPASS_SHUB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_DDRSS_LPASS_SHUB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_DDRSS_LPASS_SHUB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_DDRSS_LPASS_SHUB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_LPASS_SHUB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_DDRSS_LPASS_SHUB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_DDRSS_LPASS_SHUB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_DDRSS_LPASS_SHUB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_LPASS_SHUB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_DDRSS_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003401c) +#define HWIO_GCC_DDRSS_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003401c) +#define HWIO_GCC_DDRSS_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003401c) +#define HWIO_GCC_DDRSS_AT_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_DDRSS_AT_CBCR_ATTR 0x3 +#define HWIO_GCC_DDRSS_AT_CBCR_IN \ + in_dword_masked(HWIO_GCC_DDRSS_AT_CBCR_ADDR, HWIO_GCC_DDRSS_AT_CBCR_RMSK) +#define HWIO_GCC_DDRSS_AT_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_DDRSS_AT_CBCR_ADDR, m) +#define HWIO_GCC_DDRSS_AT_CBCR_OUT(v) \ + out_dword(HWIO_GCC_DDRSS_AT_CBCR_ADDR,v) +#define HWIO_GCC_DDRSS_AT_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DDRSS_AT_CBCR_ADDR,m,v,HWIO_GCC_DDRSS_AT_CBCR_IN) +#define HWIO_GCC_DDRSS_AT_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_DDRSS_AT_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_DDRSS_AT_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_DDRSS_AT_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_DDRSS_AT_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_DDRSS_AT_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_DDRSS_AT_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_DDRSS_AT_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_DDRSS_AT_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_DDRSS_AT_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_DDRSS_AT_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_DDRSS_AT_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_DDRSS_AT_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_DDRSS_AT_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_DDRSS_AT_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_DDRSS_AT_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_DDRSS_AT_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_DDRSS_AT_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_DDRSS_AT_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_AT_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_DDRSS_AT_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_DDRSS_AT_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_DDRSS_AT_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_AT_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SHRM_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00034020) +#define HWIO_GCC_SHRM_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00034020) +#define HWIO_GCC_SHRM_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00034020) +#define HWIO_GCC_SHRM_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_SHRM_CBCR_ATTR 0x3 +#define HWIO_GCC_SHRM_CBCR_IN \ + in_dword_masked(HWIO_GCC_SHRM_CBCR_ADDR, HWIO_GCC_SHRM_CBCR_RMSK) +#define HWIO_GCC_SHRM_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_SHRM_CBCR_ADDR, m) +#define HWIO_GCC_SHRM_CBCR_OUT(v) \ + out_dword(HWIO_GCC_SHRM_CBCR_ADDR,v) +#define HWIO_GCC_SHRM_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SHRM_CBCR_ADDR,m,v,HWIO_GCC_SHRM_CBCR_IN) +#define HWIO_GCC_SHRM_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SHRM_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SHRM_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_SHRM_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_SHRM_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_SHRM_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_SHRM_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_SHRM_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_SHRM_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_SHRM_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_SHRM_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_SHRM_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_SHRM_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_SHRM_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_SHRM_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SHRM_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_SHRM_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_SHRM_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_SHRM_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_SHRM_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_SHRM_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SHRM_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SHRM_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SHRM_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_DDRSS_PWRCTL_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00034024) +#define HWIO_GCC_DDRSS_PWRCTL_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00034024) +#define HWIO_GCC_DDRSS_PWRCTL_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00034024) +#define HWIO_GCC_DDRSS_PWRCTL_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_DDRSS_PWRCTL_CBCR_ATTR 0x3 +#define HWIO_GCC_DDRSS_PWRCTL_CBCR_IN \ + in_dword_masked(HWIO_GCC_DDRSS_PWRCTL_CBCR_ADDR, HWIO_GCC_DDRSS_PWRCTL_CBCR_RMSK) +#define HWIO_GCC_DDRSS_PWRCTL_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_DDRSS_PWRCTL_CBCR_ADDR, m) +#define HWIO_GCC_DDRSS_PWRCTL_CBCR_OUT(v) \ + out_dword(HWIO_GCC_DDRSS_PWRCTL_CBCR_ADDR,v) +#define HWIO_GCC_DDRSS_PWRCTL_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DDRSS_PWRCTL_CBCR_ADDR,m,v,HWIO_GCC_DDRSS_PWRCTL_CBCR_IN) +#define HWIO_GCC_DDRSS_PWRCTL_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_DDRSS_PWRCTL_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_DDRSS_PWRCTL_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_DDRSS_PWRCTL_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_DDRSS_PWRCTL_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_DDRSS_PWRCTL_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_DDRSS_PWRCTL_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_DDRSS_PWRCTL_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_DDRSS_PWRCTL_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_DDRSS_PWRCTL_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_DDRSS_PWRCTL_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_DDRSS_PWRCTL_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_DDRSS_PWRCTL_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_DDRSS_PWRCTL_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_DDRSS_PWRCTL_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_DDRSS_PWRCTL_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_DDRSS_PWRCTL_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_DDRSS_PWRCTL_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_DDRSS_PWRCTL_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_PWRCTL_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_DDRSS_PWRCTL_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_DDRSS_PWRCTL_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_DDRSS_PWRCTL_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_PWRCTL_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00034044) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00034044) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00034044) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00034048) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00034048) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00034048) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003404c) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003404c) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003404c) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00034050) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00034050) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00034050) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00034054) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00034054) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00034054) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00034058) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00034058) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00034058) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003405c) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003405c) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003405c) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00034060) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00034060) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00034060) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00034064) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00034064) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00034064) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00034068) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00034068) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00034068) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003406c) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003406c) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003406c) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00034070) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00034070) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00034070) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00034074) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00034074) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00034074) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00034078) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00034078) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00034078) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003407c) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003407c) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003407c) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00034080) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00034080) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00034080) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_MEMNOC_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00034028) +#define HWIO_GCC_MEMNOC_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00034028) +#define HWIO_GCC_MEMNOC_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00034028) +#define HWIO_GCC_MEMNOC_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_MEMNOC_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_MEMNOC_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_MEMNOC_CMD_RCGR_ADDR, HWIO_GCC_MEMNOC_CMD_RCGR_RMSK) +#define HWIO_GCC_MEMNOC_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_MEMNOC_CMD_RCGR_ADDR, m) +#define HWIO_GCC_MEMNOC_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_MEMNOC_CMD_RCGR_ADDR,v) +#define HWIO_GCC_MEMNOC_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MEMNOC_CMD_RCGR_ADDR,m,v,HWIO_GCC_MEMNOC_CMD_RCGR_IN) +#define HWIO_GCC_MEMNOC_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_MEMNOC_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_MEMNOC_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_MEMNOC_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_MEMNOC_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_MEMNOC_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_MEMNOC_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_MEMNOC_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_MEMNOC_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_MEMNOC_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_MEMNOC_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MEMNOC_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MEMNOC_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003402c) +#define HWIO_GCC_MEMNOC_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003402c) +#define HWIO_GCC_MEMNOC_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003402c) +#define HWIO_GCC_MEMNOC_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_MEMNOC_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_MEMNOC_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_MEMNOC_CFG_RCGR_ADDR, HWIO_GCC_MEMNOC_CFG_RCGR_RMSK) +#define HWIO_GCC_MEMNOC_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_MEMNOC_CFG_RCGR_ADDR, m) +#define HWIO_GCC_MEMNOC_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_MEMNOC_CFG_RCGR_ADDR,v) +#define HWIO_GCC_MEMNOC_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MEMNOC_CFG_RCGR_ADDR,m,v,HWIO_GCC_MEMNOC_CFG_RCGR_IN) +#define HWIO_GCC_MEMNOC_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_MEMNOC_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_MEMNOC_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_MEMNOC_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_MEMNOC_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_MEMNOC_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_MEMNOC_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_MEMNOC_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00034168) +#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00034168) +#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00034168) +#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_RMSK 0xffff +#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_CMD_DFSR_ADDR, HWIO_GCC_RPMH_SHRM_CMD_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_CMD_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_CMD_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_CMD_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHRM_CMD_DFSR_IN) +#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_RCG_SW_CTRL_BMSK 0x8000 +#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_RCG_SW_CTRL_SHFT 0xf +#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_SW_PERF_STATE_BMSK 0x7800 +#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_SW_PERF_STATE_SHFT 0xb +#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_SW_OVERRIDE_BMSK 0x400 +#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_SW_OVERRIDE_SHFT 0xa +#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK 0x200 +#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT 0x9 +#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_DFS_FSM_STATE_BMSK 0x1c0 +#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_DFS_FSM_STATE_SHFT 0x6 +#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_HW_CLK_CONTROL_BMSK 0x20 +#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_HW_CLK_CONTROL_SHFT 0x5 +#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_CURR_PERF_STATE_BMSK 0x1e +#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_CURR_PERF_STATE_SHFT 0x1 +#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_DFS_EN_BMSK 0x1 +#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_DFS_EN_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_DFS_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_DFS_EN_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00034170) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00034170) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00034170) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_ADDR, HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_IN) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00034174) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00034174) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00034174) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_ADDR, HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_IN) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00034178) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00034178) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00034178) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_ADDR, HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_IN) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003417c) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003417c) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003417c) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_ADDR, HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_IN) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00034180) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00034180) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00034180) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_ADDR, HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_IN) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00034184) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00034184) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00034184) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_ADDR, HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_IN) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00034188) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00034188) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00034188) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_ADDR, HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_IN) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003418c) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003418c) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003418c) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_ADDR, HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_IN) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00034190) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00034190) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00034190) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_ADDR, HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_IN) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00034194) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00034194) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00034194) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_ADDR, HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_IN) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00034198) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00034198) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00034198) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_ADDR, HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_IN) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003419c) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003419c) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003419c) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_ADDR, HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_IN) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000341a0) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000341a0) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000341a0) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_ADDR, HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_IN) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000341a4) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000341a4) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000341a4) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_ADDR, HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_IN) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000341a8) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000341a8) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000341a8) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_ADDR, HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_IN) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000341ac) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000341ac) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000341ac) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_ADDR, HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_IN) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_SHRM_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00034154) +#define HWIO_GCC_SHRM_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00034154) +#define HWIO_GCC_SHRM_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00034154) +#define HWIO_GCC_SHRM_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_SHRM_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_SHRM_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_SHRM_CMD_RCGR_ADDR, HWIO_GCC_SHRM_CMD_RCGR_RMSK) +#define HWIO_GCC_SHRM_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_SHRM_CMD_RCGR_ADDR, m) +#define HWIO_GCC_SHRM_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_SHRM_CMD_RCGR_ADDR,v) +#define HWIO_GCC_SHRM_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SHRM_CMD_RCGR_ADDR,m,v,HWIO_GCC_SHRM_CMD_RCGR_IN) +#define HWIO_GCC_SHRM_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_SHRM_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_SHRM_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_SHRM_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_SHRM_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_SHRM_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_SHRM_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_SHRM_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_SHRM_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_SHRM_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_SHRM_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SHRM_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SHRM_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00034158) +#define HWIO_GCC_SHRM_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00034158) +#define HWIO_GCC_SHRM_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00034158) +#define HWIO_GCC_SHRM_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_SHRM_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_SHRM_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_SHRM_CFG_RCGR_ADDR, HWIO_GCC_SHRM_CFG_RCGR_RMSK) +#define HWIO_GCC_SHRM_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_SHRM_CFG_RCGR_ADDR, m) +#define HWIO_GCC_SHRM_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_SHRM_CFG_RCGR_ADDR,v) +#define HWIO_GCC_SHRM_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SHRM_CFG_RCGR_ADDR,m,v,HWIO_GCC_SHRM_CFG_RCGR_IN) +#define HWIO_GCC_SHRM_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_SHRM_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_SHRM_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_SHRM_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_SHRM_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_SHRM_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_SHRM_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_SHRM_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_SHRM_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00034280) +#define HWIO_GCC_SHRM_DCD_CDIV_DCDR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00034280) +#define HWIO_GCC_SHRM_DCD_CDIV_DCDR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00034280) +#define HWIO_GCC_SHRM_DCD_CDIV_DCDR_RMSK 0x1 +#define HWIO_GCC_SHRM_DCD_CDIV_DCDR_ATTR 0x3 +#define HWIO_GCC_SHRM_DCD_CDIV_DCDR_IN \ + in_dword_masked(HWIO_GCC_SHRM_DCD_CDIV_DCDR_ADDR, HWIO_GCC_SHRM_DCD_CDIV_DCDR_RMSK) +#define HWIO_GCC_SHRM_DCD_CDIV_DCDR_INM(m) \ + in_dword_masked(HWIO_GCC_SHRM_DCD_CDIV_DCDR_ADDR, m) +#define HWIO_GCC_SHRM_DCD_CDIV_DCDR_OUT(v) \ + out_dword(HWIO_GCC_SHRM_DCD_CDIV_DCDR_ADDR,v) +#define HWIO_GCC_SHRM_DCD_CDIV_DCDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SHRM_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_SHRM_DCD_CDIV_DCDR_IN) +#define HWIO_GCC_SHRM_DCD_CDIV_DCDR_DCD_ENABLE_BMSK 0x1 +#define HWIO_GCC_SHRM_DCD_CDIV_DCDR_DCD_ENABLE_SHFT 0x0 +#define HWIO_GCC_SHRM_DCD_CDIV_DCDR_DCD_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SHRM_DCD_CDIV_DCDR_DCD_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MEMNOC_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00034284) +#define HWIO_GCC_MEMNOC_DCD_CDIV_DCDR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00034284) +#define HWIO_GCC_MEMNOC_DCD_CDIV_DCDR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00034284) +#define HWIO_GCC_MEMNOC_DCD_CDIV_DCDR_RMSK 0x1 +#define HWIO_GCC_MEMNOC_DCD_CDIV_DCDR_ATTR 0x3 +#define HWIO_GCC_MEMNOC_DCD_CDIV_DCDR_IN \ + in_dword_masked(HWIO_GCC_MEMNOC_DCD_CDIV_DCDR_ADDR, HWIO_GCC_MEMNOC_DCD_CDIV_DCDR_RMSK) +#define HWIO_GCC_MEMNOC_DCD_CDIV_DCDR_INM(m) \ + in_dword_masked(HWIO_GCC_MEMNOC_DCD_CDIV_DCDR_ADDR, m) +#define HWIO_GCC_MEMNOC_DCD_CDIV_DCDR_OUT(v) \ + out_dword(HWIO_GCC_MEMNOC_DCD_CDIV_DCDR_ADDR,v) +#define HWIO_GCC_MEMNOC_DCD_CDIV_DCDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MEMNOC_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_MEMNOC_DCD_CDIV_DCDR_IN) +#define HWIO_GCC_MEMNOC_DCD_CDIV_DCDR_DCD_ENABLE_BMSK 0x1 +#define HWIO_GCC_MEMNOC_DCD_CDIV_DCDR_DCD_ENABLE_SHFT 0x0 +#define HWIO_GCC_MEMNOC_DCD_CDIV_DCDR_DCD_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MEMNOC_DCD_CDIV_DCDR_DCD_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_DDRSS_GPLL0_MAIN_DIV_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00034288) +#define HWIO_GCC_DDRSS_GPLL0_MAIN_DIV_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00034288) +#define HWIO_GCC_DDRSS_GPLL0_MAIN_DIV_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00034288) +#define HWIO_GCC_DDRSS_GPLL0_MAIN_DIV_CDIVR_RMSK 0xf +#define HWIO_GCC_DDRSS_GPLL0_MAIN_DIV_CDIVR_ATTR 0x3 +#define HWIO_GCC_DDRSS_GPLL0_MAIN_DIV_CDIVR_IN \ + in_dword_masked(HWIO_GCC_DDRSS_GPLL0_MAIN_DIV_CDIVR_ADDR, HWIO_GCC_DDRSS_GPLL0_MAIN_DIV_CDIVR_RMSK) +#define HWIO_GCC_DDRSS_GPLL0_MAIN_DIV_CDIVR_INM(m) \ + in_dword_masked(HWIO_GCC_DDRSS_GPLL0_MAIN_DIV_CDIVR_ADDR, m) +#define HWIO_GCC_DDRSS_GPLL0_MAIN_DIV_CDIVR_OUT(v) \ + out_dword(HWIO_GCC_DDRSS_GPLL0_MAIN_DIV_CDIVR_ADDR,v) +#define HWIO_GCC_DDRSS_GPLL0_MAIN_DIV_CDIVR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DDRSS_GPLL0_MAIN_DIV_CDIVR_ADDR,m,v,HWIO_GCC_DDRSS_GPLL0_MAIN_DIV_CDIVR_IN) +#define HWIO_GCC_DDRSS_GPLL0_MAIN_DIV_CDIVR_CLK_DIV_BMSK 0xf +#define HWIO_GCC_DDRSS_GPLL0_MAIN_DIV_CDIVR_CLK_DIV_SHFT 0x0 + +#define HWIO_GCC_LPASS_CFG_NOC_SWAY_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00037000) +#define HWIO_GCC_LPASS_CFG_NOC_SWAY_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00037000) +#define HWIO_GCC_LPASS_CFG_NOC_SWAY_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00037000) +#define HWIO_GCC_LPASS_CFG_NOC_SWAY_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_LPASS_CFG_NOC_SWAY_CBCR_ATTR 0x3 +#define HWIO_GCC_LPASS_CFG_NOC_SWAY_CBCR_IN \ + in_dword_masked(HWIO_GCC_LPASS_CFG_NOC_SWAY_CBCR_ADDR, HWIO_GCC_LPASS_CFG_NOC_SWAY_CBCR_RMSK) +#define HWIO_GCC_LPASS_CFG_NOC_SWAY_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_LPASS_CFG_NOC_SWAY_CBCR_ADDR, m) +#define HWIO_GCC_LPASS_CFG_NOC_SWAY_CBCR_OUT(v) \ + out_dword(HWIO_GCC_LPASS_CFG_NOC_SWAY_CBCR_ADDR,v) +#define HWIO_GCC_LPASS_CFG_NOC_SWAY_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_LPASS_CFG_NOC_SWAY_CBCR_ADDR,m,v,HWIO_GCC_LPASS_CFG_NOC_SWAY_CBCR_IN) +#define HWIO_GCC_LPASS_CFG_NOC_SWAY_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_LPASS_CFG_NOC_SWAY_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_LPASS_CFG_NOC_SWAY_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_LPASS_CFG_NOC_SWAY_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_LPASS_CFG_NOC_SWAY_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_LPASS_CFG_NOC_SWAY_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_LPASS_CFG_NOC_SWAY_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_LPASS_CFG_NOC_SWAY_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_LPASS_CFG_NOC_SWAY_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_LPASS_CFG_NOC_SWAY_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_LPASS_CFG_NOC_SWAY_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_LPASS_CFG_NOC_SWAY_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_LPASS_CFG_NOC_SWAY_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_LPASS_CFG_NOC_SWAY_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_LPASS_CFG_NOC_SWAY_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_LPASS_CFG_NOC_SWAY_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_LPASS_CFG_NOC_SWAY_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_LPASS_CFG_NOC_SWAY_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_LPASS_CFG_NOC_SWAY_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_CFG_NOC_SWAY_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_CFG_NOC_SWAY_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_LPASS_CFG_NOC_SWAY_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_LPASS_CFG_NOC_SWAY_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_CFG_NOC_SWAY_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QMIP_LPASS_QTB_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00037004) +#define HWIO_GCC_QMIP_LPASS_QTB_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00037004) +#define HWIO_GCC_QMIP_LPASS_QTB_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00037004) +#define HWIO_GCC_QMIP_LPASS_QTB_AHB_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_QMIP_LPASS_QTB_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_QMIP_LPASS_QTB_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_QMIP_LPASS_QTB_AHB_CBCR_ADDR, HWIO_GCC_QMIP_LPASS_QTB_AHB_CBCR_RMSK) +#define HWIO_GCC_QMIP_LPASS_QTB_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QMIP_LPASS_QTB_AHB_CBCR_ADDR, m) +#define HWIO_GCC_QMIP_LPASS_QTB_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QMIP_LPASS_QTB_AHB_CBCR_ADDR,v) +#define HWIO_GCC_QMIP_LPASS_QTB_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QMIP_LPASS_QTB_AHB_CBCR_ADDR,m,v,HWIO_GCC_QMIP_LPASS_QTB_AHB_CBCR_IN) +#define HWIO_GCC_QMIP_LPASS_QTB_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QMIP_LPASS_QTB_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QMIP_LPASS_QTB_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QMIP_LPASS_QTB_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QMIP_LPASS_QTB_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QMIP_LPASS_QTB_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QMIP_LPASS_QTB_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QMIP_LPASS_QTB_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QMIP_LPASS_QTB_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_QMIP_LPASS_QTB_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_QMIP_LPASS_QTB_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_QMIP_LPASS_QTB_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_QMIP_LPASS_QTB_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QMIP_LPASS_QTB_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QMIP_LPASS_QTB_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QMIP_LPASS_QTB_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_QMIP_LPASS_QTB_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_QMIP_LPASS_QTB_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_QMIP_LPASS_QTB_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QMIP_LPASS_QTB_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QMIP_LPASS_QTB_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_QMIP_LPASS_QTB_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_QMIP_LPASS_QTB_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QMIP_LPASS_QTB_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_LPASS_TRIG_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00037008) +#define HWIO_GCC_LPASS_TRIG_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00037008) +#define HWIO_GCC_LPASS_TRIG_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00037008) +#define HWIO_GCC_LPASS_TRIG_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_LPASS_TRIG_CBCR_ATTR 0x3 +#define HWIO_GCC_LPASS_TRIG_CBCR_IN \ + in_dword_masked(HWIO_GCC_LPASS_TRIG_CBCR_ADDR, HWIO_GCC_LPASS_TRIG_CBCR_RMSK) +#define HWIO_GCC_LPASS_TRIG_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_LPASS_TRIG_CBCR_ADDR, m) +#define HWIO_GCC_LPASS_TRIG_CBCR_OUT(v) \ + out_dword(HWIO_GCC_LPASS_TRIG_CBCR_ADDR,v) +#define HWIO_GCC_LPASS_TRIG_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_LPASS_TRIG_CBCR_ADDR,m,v,HWIO_GCC_LPASS_TRIG_CBCR_IN) +#define HWIO_GCC_LPASS_TRIG_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_LPASS_TRIG_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_LPASS_TRIG_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_LPASS_TRIG_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_LPASS_TRIG_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_LPASS_TRIG_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_LPASS_TRIG_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_LPASS_TRIG_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_LPASS_TRIG_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_LPASS_TRIG_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_LPASS_TRIG_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_LPASS_TRIG_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_LPASS_TRIG_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_LPASS_TRIG_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_LPASS_TRIG_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_LPASS_TRIG_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_LPASS_TRIG_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_LPASS_TRIG_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_LPASS_TRIG_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_TRIG_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_TRIG_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_LPASS_TRIG_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_LPASS_TRIG_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_TRIG_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_LPASS_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003700c) +#define HWIO_GCC_LPASS_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003700c) +#define HWIO_GCC_LPASS_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003700c) +#define HWIO_GCC_LPASS_AT_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_LPASS_AT_CBCR_ATTR 0x3 +#define HWIO_GCC_LPASS_AT_CBCR_IN \ + in_dword_masked(HWIO_GCC_LPASS_AT_CBCR_ADDR, HWIO_GCC_LPASS_AT_CBCR_RMSK) +#define HWIO_GCC_LPASS_AT_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_LPASS_AT_CBCR_ADDR, m) +#define HWIO_GCC_LPASS_AT_CBCR_OUT(v) \ + out_dword(HWIO_GCC_LPASS_AT_CBCR_ADDR,v) +#define HWIO_GCC_LPASS_AT_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_LPASS_AT_CBCR_ADDR,m,v,HWIO_GCC_LPASS_AT_CBCR_IN) +#define HWIO_GCC_LPASS_AT_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_LPASS_AT_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_LPASS_AT_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_LPASS_AT_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_LPASS_AT_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_LPASS_AT_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_LPASS_AT_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_LPASS_AT_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_LPASS_AT_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_LPASS_AT_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_LPASS_AT_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_LPASS_AT_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_LPASS_AT_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_LPASS_AT_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_LPASS_AT_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_LPASS_AT_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_LPASS_AT_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_LPASS_AT_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_LPASS_AT_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_AT_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_AT_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_LPASS_AT_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_LPASS_AT_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_AT_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_LPASS_AON_NOC_DDRSS_SHUB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00037010) +#define HWIO_GCC_LPASS_AON_NOC_DDRSS_SHUB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00037010) +#define HWIO_GCC_LPASS_AON_NOC_DDRSS_SHUB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00037010) +#define HWIO_GCC_LPASS_AON_NOC_DDRSS_SHUB_CBCR_RMSK 0x81f0000f +#define HWIO_GCC_LPASS_AON_NOC_DDRSS_SHUB_CBCR_ATTR 0x3 +#define HWIO_GCC_LPASS_AON_NOC_DDRSS_SHUB_CBCR_IN \ + in_dword_masked(HWIO_GCC_LPASS_AON_NOC_DDRSS_SHUB_CBCR_ADDR, HWIO_GCC_LPASS_AON_NOC_DDRSS_SHUB_CBCR_RMSK) +#define HWIO_GCC_LPASS_AON_NOC_DDRSS_SHUB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_LPASS_AON_NOC_DDRSS_SHUB_CBCR_ADDR, m) +#define HWIO_GCC_LPASS_AON_NOC_DDRSS_SHUB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_LPASS_AON_NOC_DDRSS_SHUB_CBCR_ADDR,v) +#define HWIO_GCC_LPASS_AON_NOC_DDRSS_SHUB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_LPASS_AON_NOC_DDRSS_SHUB_CBCR_ADDR,m,v,HWIO_GCC_LPASS_AON_NOC_DDRSS_SHUB_CBCR_IN) +#define HWIO_GCC_LPASS_AON_NOC_DDRSS_SHUB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_LPASS_AON_NOC_DDRSS_SHUB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_LPASS_AON_NOC_DDRSS_SHUB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_LPASS_AON_NOC_DDRSS_SHUB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_LPASS_AON_NOC_DDRSS_SHUB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_LPASS_AON_NOC_DDRSS_SHUB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_LPASS_AON_NOC_DDRSS_SHUB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_LPASS_AON_NOC_DDRSS_SHUB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_LPASS_AON_NOC_DDRSS_SHUB_CBCR_IGNORE_PMU_CLK_DIS_BMSK 0x200000 +#define HWIO_GCC_LPASS_AON_NOC_DDRSS_SHUB_CBCR_IGNORE_PMU_CLK_DIS_SHFT 0x15 +#define HWIO_GCC_LPASS_AON_NOC_DDRSS_SHUB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_LPASS_AON_NOC_DDRSS_SHUB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_LPASS_AON_NOC_DDRSS_SHUB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_LPASS_AON_NOC_DDRSS_SHUB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_LPASS_AON_NOC_DDRSS_SHUB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_LPASS_AON_NOC_DDRSS_SHUB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_LPASS_AON_NOC_DDRSS_SHUB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_LPASS_AON_NOC_DDRSS_SHUB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_LPASS_AON_NOC_DDRSS_SHUB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_LPASS_AON_NOC_DDRSS_SHUB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_LPASS_AON_NOC_DDRSS_SHUB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_AON_NOC_DDRSS_SHUB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_AON_NOC_DDRSS_SHUB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_LPASS_AON_NOC_DDRSS_SHUB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_LPASS_AON_NOC_DDRSS_SHUB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_AON_NOC_DDRSS_SHUB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_LPASS_AGGRE_NOC_MPU_CLIENT_DDRSS_SHUB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00037014) +#define HWIO_GCC_LPASS_AGGRE_NOC_MPU_CLIENT_DDRSS_SHUB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00037014) +#define HWIO_GCC_LPASS_AGGRE_NOC_MPU_CLIENT_DDRSS_SHUB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00037014) +#define HWIO_GCC_LPASS_AGGRE_NOC_MPU_CLIENT_DDRSS_SHUB_CBCR_RMSK 0x81f0000f +#define HWIO_GCC_LPASS_AGGRE_NOC_MPU_CLIENT_DDRSS_SHUB_CBCR_ATTR 0x3 +#define HWIO_GCC_LPASS_AGGRE_NOC_MPU_CLIENT_DDRSS_SHUB_CBCR_IN \ + in_dword_masked(HWIO_GCC_LPASS_AGGRE_NOC_MPU_CLIENT_DDRSS_SHUB_CBCR_ADDR, HWIO_GCC_LPASS_AGGRE_NOC_MPU_CLIENT_DDRSS_SHUB_CBCR_RMSK) +#define HWIO_GCC_LPASS_AGGRE_NOC_MPU_CLIENT_DDRSS_SHUB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_LPASS_AGGRE_NOC_MPU_CLIENT_DDRSS_SHUB_CBCR_ADDR, m) +#define HWIO_GCC_LPASS_AGGRE_NOC_MPU_CLIENT_DDRSS_SHUB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_LPASS_AGGRE_NOC_MPU_CLIENT_DDRSS_SHUB_CBCR_ADDR,v) +#define HWIO_GCC_LPASS_AGGRE_NOC_MPU_CLIENT_DDRSS_SHUB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_LPASS_AGGRE_NOC_MPU_CLIENT_DDRSS_SHUB_CBCR_ADDR,m,v,HWIO_GCC_LPASS_AGGRE_NOC_MPU_CLIENT_DDRSS_SHUB_CBCR_IN) +#define HWIO_GCC_LPASS_AGGRE_NOC_MPU_CLIENT_DDRSS_SHUB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_LPASS_AGGRE_NOC_MPU_CLIENT_DDRSS_SHUB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_LPASS_AGGRE_NOC_MPU_CLIENT_DDRSS_SHUB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_LPASS_AGGRE_NOC_MPU_CLIENT_DDRSS_SHUB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_LPASS_AGGRE_NOC_MPU_CLIENT_DDRSS_SHUB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_LPASS_AGGRE_NOC_MPU_CLIENT_DDRSS_SHUB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_LPASS_AGGRE_NOC_MPU_CLIENT_DDRSS_SHUB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_LPASS_AGGRE_NOC_MPU_CLIENT_DDRSS_SHUB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_LPASS_AGGRE_NOC_MPU_CLIENT_DDRSS_SHUB_CBCR_IGNORE_PMU_CLK_DIS_BMSK 0x200000 +#define HWIO_GCC_LPASS_AGGRE_NOC_MPU_CLIENT_DDRSS_SHUB_CBCR_IGNORE_PMU_CLK_DIS_SHFT 0x15 +#define HWIO_GCC_LPASS_AGGRE_NOC_MPU_CLIENT_DDRSS_SHUB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_LPASS_AGGRE_NOC_MPU_CLIENT_DDRSS_SHUB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_LPASS_AGGRE_NOC_MPU_CLIENT_DDRSS_SHUB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_LPASS_AGGRE_NOC_MPU_CLIENT_DDRSS_SHUB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_LPASS_AGGRE_NOC_MPU_CLIENT_DDRSS_SHUB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_LPASS_AGGRE_NOC_MPU_CLIENT_DDRSS_SHUB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_LPASS_AGGRE_NOC_MPU_CLIENT_DDRSS_SHUB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_LPASS_AGGRE_NOC_MPU_CLIENT_DDRSS_SHUB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_LPASS_AGGRE_NOC_MPU_CLIENT_DDRSS_SHUB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_LPASS_AGGRE_NOC_MPU_CLIENT_DDRSS_SHUB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_LPASS_AGGRE_NOC_MPU_CLIENT_DDRSS_SHUB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_AGGRE_NOC_MPU_CLIENT_DDRSS_SHUB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_AGGRE_NOC_MPU_CLIENT_DDRSS_SHUB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_LPASS_AGGRE_NOC_MPU_CLIENT_DDRSS_SHUB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_LPASS_AGGRE_NOC_MPU_CLIENT_DDRSS_SHUB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_AGGRE_NOC_MPU_CLIENT_DDRSS_SHUB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00037018) +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00037018) +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00037018) +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CBCR_RMSK 0x81f0700f +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CBCR_ATTR 0x3 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CBCR_IN \ + in_dword_masked(HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CBCR_ADDR, HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CBCR_RMSK) +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CBCR_ADDR, m) +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CBCR_ADDR,v) +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CBCR_ADDR,m,v,HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CBCR_IN) +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CBCR_IGNORE_PMU_CLK_DIS_BMSK 0x200000 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CBCR_IGNORE_PMU_CLK_DIS_SHFT 0x15 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003701c) +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003701c) +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003701c) +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_RMSK 0xf1ffffe +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_ATTR 0x3 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_IN \ + in_dword_masked(HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_ADDR, HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_RMSK) +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_ADDR, m) +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_OUT(v) \ + out_dword(HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_ADDR,v) +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_ADDR,m,v,HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_IN) +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xf000000 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_PWR_FSM_CLK_SEL_BMSK 0x100000 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_PWR_FSM_CLK_SEL_SHFT 0x14 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xf0000 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CFG_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00037020) +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CFG_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00037020) +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CFG_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00037020) +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CFG_SREGR_RMSK 0xffffffff +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CFG_SREGR_ATTR 0x3 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CFG_SREGR_IN \ + in_dword_masked(HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CFG_SREGR_ADDR, HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CFG_SREGR_RMSK) +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CFG_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CFG_SREGR_ADDR, m) +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CFG_SREGR_OUT(v) \ + out_dword(HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CFG_SREGR_ADDR,v) +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CFG_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CFG_SREGR_ADDR,m,v,HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CFG_SREGR_IN) +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CFG_SREGR_MEM_CORE_OFF_TIMER_BMSK 0xfc000000 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CFG_SREGR_MEM_CORE_OFF_TIMER_SHFT 0x1a +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_BMSK 0x2000000 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_SHFT 0x19 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_BMSK 0x1000000 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_SHFT 0x18 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CFG_SREGR_MEM_PERIPH_ON_STATUS_BMSK 0x800000 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CFG_SREGR_MEM_PERIPH_ON_STATUS_SHFT 0x17 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CFG_SREGR_MEM_CORE_ON_STATUS_BMSK 0x400000 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CFG_SREGR_MEM_CORE_ON_STATUS_SHFT 0x16 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CFG_SREGR_MEM_CPH_TIMER_BMSK 0x3f0000 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CFG_SREGR_MEM_CPH_TIMER_SHFT 0x10 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CFG_SREGR_SLEEP_TIMER_BMSK 0xff00 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CFG_SREGR_SLEEP_TIMER_SHFT 0x8 +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CFG_SREGR_WAKEUP_TIMER_BMSK 0xff +#define HWIO_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CFG_SREGR_WAKEUP_TIMER_SHFT 0x0 + +#define HWIO_GCC_LPASS_AGGRE_NOC_DDRSS_SHUB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00037024) +#define HWIO_GCC_LPASS_AGGRE_NOC_DDRSS_SHUB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00037024) +#define HWIO_GCC_LPASS_AGGRE_NOC_DDRSS_SHUB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00037024) +#define HWIO_GCC_LPASS_AGGRE_NOC_DDRSS_SHUB_CBCR_RMSK 0x81f0000f +#define HWIO_GCC_LPASS_AGGRE_NOC_DDRSS_SHUB_CBCR_ATTR 0x3 +#define HWIO_GCC_LPASS_AGGRE_NOC_DDRSS_SHUB_CBCR_IN \ + in_dword_masked(HWIO_GCC_LPASS_AGGRE_NOC_DDRSS_SHUB_CBCR_ADDR, HWIO_GCC_LPASS_AGGRE_NOC_DDRSS_SHUB_CBCR_RMSK) +#define HWIO_GCC_LPASS_AGGRE_NOC_DDRSS_SHUB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_LPASS_AGGRE_NOC_DDRSS_SHUB_CBCR_ADDR, m) +#define HWIO_GCC_LPASS_AGGRE_NOC_DDRSS_SHUB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_LPASS_AGGRE_NOC_DDRSS_SHUB_CBCR_ADDR,v) +#define HWIO_GCC_LPASS_AGGRE_NOC_DDRSS_SHUB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_LPASS_AGGRE_NOC_DDRSS_SHUB_CBCR_ADDR,m,v,HWIO_GCC_LPASS_AGGRE_NOC_DDRSS_SHUB_CBCR_IN) +#define HWIO_GCC_LPASS_AGGRE_NOC_DDRSS_SHUB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_LPASS_AGGRE_NOC_DDRSS_SHUB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_LPASS_AGGRE_NOC_DDRSS_SHUB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_LPASS_AGGRE_NOC_DDRSS_SHUB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_LPASS_AGGRE_NOC_DDRSS_SHUB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_LPASS_AGGRE_NOC_DDRSS_SHUB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_LPASS_AGGRE_NOC_DDRSS_SHUB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_LPASS_AGGRE_NOC_DDRSS_SHUB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_LPASS_AGGRE_NOC_DDRSS_SHUB_CBCR_IGNORE_PMU_CLK_DIS_BMSK 0x200000 +#define HWIO_GCC_LPASS_AGGRE_NOC_DDRSS_SHUB_CBCR_IGNORE_PMU_CLK_DIS_SHFT 0x15 +#define HWIO_GCC_LPASS_AGGRE_NOC_DDRSS_SHUB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_LPASS_AGGRE_NOC_DDRSS_SHUB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_LPASS_AGGRE_NOC_DDRSS_SHUB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_LPASS_AGGRE_NOC_DDRSS_SHUB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_LPASS_AGGRE_NOC_DDRSS_SHUB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_LPASS_AGGRE_NOC_DDRSS_SHUB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_LPASS_AGGRE_NOC_DDRSS_SHUB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_LPASS_AGGRE_NOC_DDRSS_SHUB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_LPASS_AGGRE_NOC_DDRSS_SHUB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_LPASS_AGGRE_NOC_DDRSS_SHUB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_LPASS_AGGRE_NOC_DDRSS_SHUB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_AGGRE_NOC_DDRSS_SHUB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_AGGRE_NOC_DDRSS_SHUB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_LPASS_AGGRE_NOC_DDRSS_SHUB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_LPASS_AGGRE_NOC_DDRSS_SHUB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_AGGRE_NOC_DDRSS_SHUB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_LPASS_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00037028) +#define HWIO_GCC_LPASS_DCD_CDIV_DCDR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00037028) +#define HWIO_GCC_LPASS_DCD_CDIV_DCDR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00037028) +#define HWIO_GCC_LPASS_DCD_CDIV_DCDR_RMSK 0x1 +#define HWIO_GCC_LPASS_DCD_CDIV_DCDR_ATTR 0x3 +#define HWIO_GCC_LPASS_DCD_CDIV_DCDR_IN \ + in_dword_masked(HWIO_GCC_LPASS_DCD_CDIV_DCDR_ADDR, HWIO_GCC_LPASS_DCD_CDIV_DCDR_RMSK) +#define HWIO_GCC_LPASS_DCD_CDIV_DCDR_INM(m) \ + in_dword_masked(HWIO_GCC_LPASS_DCD_CDIV_DCDR_ADDR, m) +#define HWIO_GCC_LPASS_DCD_CDIV_DCDR_OUT(v) \ + out_dword(HWIO_GCC_LPASS_DCD_CDIV_DCDR_ADDR,v) +#define HWIO_GCC_LPASS_DCD_CDIV_DCDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_LPASS_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_LPASS_DCD_CDIV_DCDR_IN) +#define HWIO_GCC_LPASS_DCD_CDIV_DCDR_DCD_ENABLE_BMSK 0x1 +#define HWIO_GCC_LPASS_DCD_CDIV_DCDR_DCD_ENABLE_SHFT 0x0 +#define HWIO_GCC_LPASS_DCD_CDIV_DCDR_DCD_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DCD_CDIV_DCDR_DCD_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00037048) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00037048) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00037048) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF0_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF0_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF0_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF0_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003704c) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003704c) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003704c) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF1_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF1_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF1_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF1_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00037050) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00037050) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00037050) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF2_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF2_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF2_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF2_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00037054) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00037054) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00037054) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF3_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF3_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF3_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF3_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00037058) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00037058) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00037058) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF4_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF4_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF4_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF4_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003705c) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003705c) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003705c) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF5_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF5_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF5_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF5_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00037060) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00037060) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00037060) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF6_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF6_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF6_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF6_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00037064) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00037064) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00037064) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF7_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF7_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF7_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF7_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF8_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00037068) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF8_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00037068) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF8_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00037068) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF8_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF8_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF8_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF8_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF8_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF8_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF8_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF8_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF8_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF8_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF8_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF8_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF8_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF8_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF8_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF8_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF8_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF8_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF8_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF8_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF8_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF8_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF8_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF8_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF8_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF8_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF8_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF8_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF8_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF8_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF8_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF8_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF8_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF8_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF8_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF8_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF8_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF8_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF8_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF8_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF8_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF8_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF8_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF8_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF8_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF8_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF8_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF8_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF8_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF8_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF8_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF8_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF8_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF8_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF8_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF9_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003706c) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF9_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003706c) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF9_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003706c) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF9_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF9_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF9_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF9_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF9_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF9_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF9_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF9_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF9_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF9_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF9_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF9_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF9_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF9_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF9_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF9_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF9_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF9_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF9_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF9_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF9_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF9_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF9_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF9_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF9_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF9_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF9_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF9_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF9_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF9_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF9_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF9_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF9_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF9_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF9_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF9_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF9_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF9_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF9_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF9_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF9_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF9_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF9_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF9_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF9_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF9_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF9_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF9_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF9_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF9_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF9_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF9_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF9_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF9_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF9_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF10_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00037070) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF10_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00037070) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF10_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00037070) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF10_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF10_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF10_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF10_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF10_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF10_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF10_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF10_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF10_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF10_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF10_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF10_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF10_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF10_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF10_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF10_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF10_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF10_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF10_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF10_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF10_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF10_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF10_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF10_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF10_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF10_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF10_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF10_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF10_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF10_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF10_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF10_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF10_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF10_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF10_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF10_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF10_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF10_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF10_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF10_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF10_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF10_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF10_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF10_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF10_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF10_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF10_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF10_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF10_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF10_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF10_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF10_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF10_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF10_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF10_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF11_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00037074) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF11_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00037074) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF11_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00037074) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF11_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF11_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF11_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF11_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF11_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF11_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF11_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF11_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF11_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF11_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF11_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF11_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF11_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF11_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF11_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF11_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF11_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF11_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF11_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF11_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF11_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF11_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF11_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF11_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF11_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF11_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF11_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF11_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF11_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF11_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF11_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF11_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF11_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF11_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF11_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF11_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF11_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF11_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF11_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF11_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF11_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF11_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF11_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF11_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF11_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF11_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF11_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF11_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF11_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF11_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF11_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF11_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF11_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF11_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF11_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF12_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00037078) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF12_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00037078) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF12_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00037078) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF12_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF12_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF12_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF12_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF12_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF12_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF12_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF12_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF12_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF12_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF12_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF12_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF12_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF12_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF12_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF12_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF12_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF12_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF12_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF12_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF12_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF12_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF12_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF12_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF12_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF12_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF12_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF12_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF12_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF12_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF12_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF12_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF12_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF12_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF12_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF12_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF12_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF12_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF12_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF12_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF12_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF12_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF12_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF12_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF12_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF12_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF12_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF12_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF12_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF12_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF12_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF12_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF12_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF12_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF12_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF13_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003707c) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF13_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003707c) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF13_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003707c) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF13_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF13_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF13_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF13_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF13_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF13_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF13_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF13_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF13_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF13_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF13_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF13_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF13_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF13_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF13_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF13_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF13_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF13_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF13_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF13_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF13_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF13_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF13_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF13_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF13_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF13_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF13_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF13_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF13_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF13_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF13_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF13_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF13_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF13_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF13_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF13_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF13_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF13_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF13_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF13_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF13_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF13_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF13_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF13_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF13_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF13_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF13_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF13_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF13_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF13_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF13_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF13_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF13_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF13_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF13_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF14_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00037080) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF14_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00037080) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF14_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00037080) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF14_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF14_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF14_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF14_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF14_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF14_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF14_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF14_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF14_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF14_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF14_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF14_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF14_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF14_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF14_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF14_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF14_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF14_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF14_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF14_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF14_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF14_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF14_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF14_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF14_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF14_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF14_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF14_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF14_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF14_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF14_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF14_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF14_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF14_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF14_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF14_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF14_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF14_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF14_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF14_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF14_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF14_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF14_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF14_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF14_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF14_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF14_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF14_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF14_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF14_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF14_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF14_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF14_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF14_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF14_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF15_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00037084) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF15_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00037084) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF15_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00037084) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF15_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF15_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF15_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF15_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF15_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF15_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF15_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF15_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF15_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF15_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF15_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF15_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF15_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF15_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF15_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF15_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF15_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF15_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF15_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF15_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF15_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF15_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF15_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF15_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF15_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF15_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF15_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF15_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF15_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF15_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF15_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF15_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF15_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF15_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF15_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF15_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF15_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF15_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF15_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF15_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF15_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF15_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF15_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF15_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF15_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF15_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF15_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF15_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF15_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF15_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF15_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF15_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF15_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF15_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF15_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_LPASS_DDRSS_SHUB_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003702c) +#define HWIO_GCC_LPASS_DDRSS_SHUB_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003702c) +#define HWIO_GCC_LPASS_DDRSS_SHUB_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003702c) +#define HWIO_GCC_LPASS_DDRSS_SHUB_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_LPASS_DDRSS_SHUB_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_LPASS_DDRSS_SHUB_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_LPASS_DDRSS_SHUB_CMD_RCGR_ADDR, HWIO_GCC_LPASS_DDRSS_SHUB_CMD_RCGR_RMSK) +#define HWIO_GCC_LPASS_DDRSS_SHUB_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_LPASS_DDRSS_SHUB_CMD_RCGR_ADDR, m) +#define HWIO_GCC_LPASS_DDRSS_SHUB_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_LPASS_DDRSS_SHUB_CMD_RCGR_ADDR,v) +#define HWIO_GCC_LPASS_DDRSS_SHUB_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_LPASS_DDRSS_SHUB_CMD_RCGR_ADDR,m,v,HWIO_GCC_LPASS_DDRSS_SHUB_CMD_RCGR_IN) +#define HWIO_GCC_LPASS_DDRSS_SHUB_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_LPASS_DDRSS_SHUB_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_LPASS_DDRSS_SHUB_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_LPASS_DDRSS_SHUB_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_LPASS_DDRSS_SHUB_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_LPASS_DDRSS_SHUB_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_LPASS_DDRSS_SHUB_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DDRSS_SHUB_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DDRSS_SHUB_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_LPASS_DDRSS_SHUB_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_LPASS_DDRSS_SHUB_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DDRSS_SHUB_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00037030) +#define HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00037030) +#define HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00037030) +#define HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_ADDR, HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_RMSK) +#define HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_ADDR, m) +#define HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_ADDR,v) +#define HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_ADDR,m,v,HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_IN) +#define HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_LPASS_DDRSS_SHUB_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_LPASS_QTB_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00089000) +#define HWIO_GCC_LPASS_QTB_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00089000) +#define HWIO_GCC_LPASS_QTB_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00089000) +#define HWIO_GCC_LPASS_QTB_GDSCR_RMSK 0xf8ffffff +#define HWIO_GCC_LPASS_QTB_GDSCR_ATTR 0x3 +#define HWIO_GCC_LPASS_QTB_GDSCR_IN \ + in_dword_masked(HWIO_GCC_LPASS_QTB_GDSCR_ADDR, HWIO_GCC_LPASS_QTB_GDSCR_RMSK) +#define HWIO_GCC_LPASS_QTB_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_LPASS_QTB_GDSCR_ADDR, m) +#define HWIO_GCC_LPASS_QTB_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_LPASS_QTB_GDSCR_ADDR,v) +#define HWIO_GCC_LPASS_QTB_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_LPASS_QTB_GDSCR_ADDR,m,v,HWIO_GCC_LPASS_QTB_GDSCR_IN) +#define HWIO_GCC_LPASS_QTB_GDSCR_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_LPASS_QTB_GDSCR_PWR_ON_SHFT 0x1f +#define HWIO_GCC_LPASS_QTB_GDSCR_GDSC_STATE_BMSK 0x78000000 +#define HWIO_GCC_LPASS_QTB_GDSCR_GDSC_STATE_SHFT 0x1b +#define HWIO_GCC_LPASS_QTB_GDSCR_EN_REST_WAIT_BMSK 0xf00000 +#define HWIO_GCC_LPASS_QTB_GDSCR_EN_REST_WAIT_SHFT 0x14 +#define HWIO_GCC_LPASS_QTB_GDSCR_EN_FEW_WAIT_BMSK 0xf0000 +#define HWIO_GCC_LPASS_QTB_GDSCR_EN_FEW_WAIT_SHFT 0x10 +#define HWIO_GCC_LPASS_QTB_GDSCR_CLK_DIS_WAIT_BMSK 0xf000 +#define HWIO_GCC_LPASS_QTB_GDSCR_CLK_DIS_WAIT_SHFT 0xc +#define HWIO_GCC_LPASS_QTB_GDSCR_RETAIN_FF_ENABLE_BMSK 0x800 +#define HWIO_GCC_LPASS_QTB_GDSCR_RETAIN_FF_ENABLE_SHFT 0xb +#define HWIO_GCC_LPASS_QTB_GDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_QTB_GDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_QTB_GDSCR_RESTORE_BMSK 0x400 +#define HWIO_GCC_LPASS_QTB_GDSCR_RESTORE_SHFT 0xa +#define HWIO_GCC_LPASS_QTB_GDSCR_RESTORE_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_QTB_GDSCR_RESTORE_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_QTB_GDSCR_SAVE_BMSK 0x200 +#define HWIO_GCC_LPASS_QTB_GDSCR_SAVE_SHFT 0x9 +#define HWIO_GCC_LPASS_QTB_GDSCR_SAVE_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_QTB_GDSCR_SAVE_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_QTB_GDSCR_RETAIN_BMSK 0x100 +#define HWIO_GCC_LPASS_QTB_GDSCR_RETAIN_SHFT 0x8 +#define HWIO_GCC_LPASS_QTB_GDSCR_RETAIN_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_QTB_GDSCR_RETAIN_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_QTB_GDSCR_EN_REST_BMSK 0x80 +#define HWIO_GCC_LPASS_QTB_GDSCR_EN_REST_SHFT 0x7 +#define HWIO_GCC_LPASS_QTB_GDSCR_EN_REST_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_QTB_GDSCR_EN_REST_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_QTB_GDSCR_EN_FEW_BMSK 0x40 +#define HWIO_GCC_LPASS_QTB_GDSCR_EN_FEW_SHFT 0x6 +#define HWIO_GCC_LPASS_QTB_GDSCR_EN_FEW_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_QTB_GDSCR_EN_FEW_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_QTB_GDSCR_CLAMP_IO_BMSK 0x20 +#define HWIO_GCC_LPASS_QTB_GDSCR_CLAMP_IO_SHFT 0x5 +#define HWIO_GCC_LPASS_QTB_GDSCR_CLAMP_IO_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_QTB_GDSCR_CLAMP_IO_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_QTB_GDSCR_CLK_DISABLE_BMSK 0x10 +#define HWIO_GCC_LPASS_QTB_GDSCR_CLK_DISABLE_SHFT 0x4 +#define HWIO_GCC_LPASS_QTB_GDSCR_CLK_DISABLE_CLK_NOT_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_QTB_GDSCR_CLK_DISABLE_CLK_IS_DISABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_QTB_GDSCR_PD_ARES_BMSK 0x8 +#define HWIO_GCC_LPASS_QTB_GDSCR_PD_ARES_SHFT 0x3 +#define HWIO_GCC_LPASS_QTB_GDSCR_PD_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_LPASS_QTB_GDSCR_PD_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_LPASS_QTB_GDSCR_SW_OVERRIDE_BMSK 0x4 +#define HWIO_GCC_LPASS_QTB_GDSCR_SW_OVERRIDE_SHFT 0x2 +#define HWIO_GCC_LPASS_QTB_GDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_QTB_GDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_QTB_GDSCR_HW_CONTROL_BMSK 0x2 +#define HWIO_GCC_LPASS_QTB_GDSCR_HW_CONTROL_SHFT 0x1 +#define HWIO_GCC_LPASS_QTB_GDSCR_HW_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_QTB_GDSCR_HW_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_QTB_GDSCR_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_LPASS_QTB_GDSCR_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_LPASS_QTB_GDSCR_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_QTB_GDSCR_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_LPASS_QTB_CFG_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00089004) +#define HWIO_GCC_LPASS_QTB_CFG_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00089004) +#define HWIO_GCC_LPASS_QTB_CFG_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00089004) +#define HWIO_GCC_LPASS_QTB_CFG_GDSCR_RMSK 0x7ffffff +#define HWIO_GCC_LPASS_QTB_CFG_GDSCR_ATTR 0x3 +#define HWIO_GCC_LPASS_QTB_CFG_GDSCR_IN \ + in_dword_masked(HWIO_GCC_LPASS_QTB_CFG_GDSCR_ADDR, HWIO_GCC_LPASS_QTB_CFG_GDSCR_RMSK) +#define HWIO_GCC_LPASS_QTB_CFG_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_LPASS_QTB_CFG_GDSCR_ADDR, m) +#define HWIO_GCC_LPASS_QTB_CFG_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_LPASS_QTB_CFG_GDSCR_ADDR,v) +#define HWIO_GCC_LPASS_QTB_CFG_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_LPASS_QTB_CFG_GDSCR_ADDR,m,v,HWIO_GCC_LPASS_QTB_CFG_GDSCR_IN) +#define HWIO_GCC_LPASS_QTB_CFG_GDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4000000 +#define HWIO_GCC_LPASS_QTB_CFG_GDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x1a +#define HWIO_GCC_LPASS_QTB_CFG_GDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_QTB_CFG_GDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_QTB_CFG_GDSCR_GDSC_PWR_DWN_START_BMSK 0x2000000 +#define HWIO_GCC_LPASS_QTB_CFG_GDSCR_GDSC_PWR_DWN_START_SHFT 0x19 +#define HWIO_GCC_LPASS_QTB_CFG_GDSCR_GDSC_PWR_UP_START_BMSK 0x1000000 +#define HWIO_GCC_LPASS_QTB_CFG_GDSCR_GDSC_PWR_UP_START_SHFT 0x18 +#define HWIO_GCC_LPASS_QTB_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_BMSK 0xf00000 +#define HWIO_GCC_LPASS_QTB_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_SHFT 0x14 +#define HWIO_GCC_LPASS_QTB_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_BMSK 0x80000 +#define HWIO_GCC_LPASS_QTB_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_SHFT 0x13 +#define HWIO_GCC_LPASS_QTB_CFG_GDSCR_GDSC_ENR_ACK_STATUS_BMSK 0x40000 +#define HWIO_GCC_LPASS_QTB_CFG_GDSCR_GDSC_ENR_ACK_STATUS_SHFT 0x12 +#define HWIO_GCC_LPASS_QTB_CFG_GDSCR_GDSC_ENF_ACK_STATUS_BMSK 0x20000 +#define HWIO_GCC_LPASS_QTB_CFG_GDSCR_GDSC_ENF_ACK_STATUS_SHFT 0x11 +#define HWIO_GCC_LPASS_QTB_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_BMSK 0x10000 +#define HWIO_GCC_LPASS_QTB_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_SHFT 0x10 +#define HWIO_GCC_LPASS_QTB_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_BMSK 0x8000 +#define HWIO_GCC_LPASS_QTB_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_SHFT 0xf +#define HWIO_GCC_LPASS_QTB_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_BMSK 0x7800 +#define HWIO_GCC_LPASS_QTB_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_SHFT 0xb +#define HWIO_GCC_LPASS_QTB_CFG_GDSCR_GDSC_HANDSHAKE_DIS_BMSK 0x400 +#define HWIO_GCC_LPASS_QTB_CFG_GDSCR_GDSC_HANDSHAKE_DIS_SHFT 0xa +#define HWIO_GCC_LPASS_QTB_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_BMSK 0x200 +#define HWIO_GCC_LPASS_QTB_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_SHFT 0x9 +#define HWIO_GCC_LPASS_QTB_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_BMSK 0x100 +#define HWIO_GCC_LPASS_QTB_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_SHFT 0x8 +#define HWIO_GCC_LPASS_QTB_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_BMSK 0x80 +#define HWIO_GCC_LPASS_QTB_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_SHFT 0x7 +#define HWIO_GCC_LPASS_QTB_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_BMSK 0x60 +#define HWIO_GCC_LPASS_QTB_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_SHFT 0x5 +#define HWIO_GCC_LPASS_QTB_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_BMSK 0x10 +#define HWIO_GCC_LPASS_QTB_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_SHFT 0x4 +#define HWIO_GCC_LPASS_QTB_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_BMSK 0x8 +#define HWIO_GCC_LPASS_QTB_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_SHFT 0x3 +#define HWIO_GCC_LPASS_QTB_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_BMSK 0x4 +#define HWIO_GCC_LPASS_QTB_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_SHFT 0x2 +#define HWIO_GCC_LPASS_QTB_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_BMSK 0x2 +#define HWIO_GCC_LPASS_QTB_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_SHFT 0x1 +#define HWIO_GCC_LPASS_QTB_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_LPASS_QTB_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_SHFT 0x0 + +#define HWIO_GCC_LPASS_QTB_CFG2_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00089008) +#define HWIO_GCC_LPASS_QTB_CFG2_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00089008) +#define HWIO_GCC_LPASS_QTB_CFG2_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00089008) +#define HWIO_GCC_LPASS_QTB_CFG2_GDSCR_RMSK 0x7ffff +#define HWIO_GCC_LPASS_QTB_CFG2_GDSCR_ATTR 0x3 +#define HWIO_GCC_LPASS_QTB_CFG2_GDSCR_IN \ + in_dword_masked(HWIO_GCC_LPASS_QTB_CFG2_GDSCR_ADDR, HWIO_GCC_LPASS_QTB_CFG2_GDSCR_RMSK) +#define HWIO_GCC_LPASS_QTB_CFG2_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_LPASS_QTB_CFG2_GDSCR_ADDR, m) +#define HWIO_GCC_LPASS_QTB_CFG2_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_LPASS_QTB_CFG2_GDSCR_ADDR,v) +#define HWIO_GCC_LPASS_QTB_CFG2_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_LPASS_QTB_CFG2_GDSCR_ADDR,m,v,HWIO_GCC_LPASS_QTB_CFG2_GDSCR_IN) +#define HWIO_GCC_LPASS_QTB_CFG2_GDSCR_GDSC_MEM_PWRUP_ACK_OVERRIDE_BMSK 0x40000 +#define HWIO_GCC_LPASS_QTB_CFG2_GDSCR_GDSC_MEM_PWRUP_ACK_OVERRIDE_SHFT 0x12 +#define HWIO_GCC_LPASS_QTB_CFG2_GDSCR_GDSC_PWRDWN_ENABLE_ACK_OVERRIDE_BMSK 0x20000 +#define HWIO_GCC_LPASS_QTB_CFG2_GDSCR_GDSC_PWRDWN_ENABLE_ACK_OVERRIDE_SHFT 0x11 +#define HWIO_GCC_LPASS_QTB_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_BMSK 0x10000 +#define HWIO_GCC_LPASS_QTB_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_SHFT 0x10 +#define HWIO_GCC_LPASS_QTB_CFG2_GDSCR_DLY_MEM_PWR_UP_BMSK 0xf000 +#define HWIO_GCC_LPASS_QTB_CFG2_GDSCR_DLY_MEM_PWR_UP_SHFT 0xc +#define HWIO_GCC_LPASS_QTB_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_BMSK 0xf00 +#define HWIO_GCC_LPASS_QTB_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_SHFT 0x8 +#define HWIO_GCC_LPASS_QTB_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_BMSK 0xf0 +#define HWIO_GCC_LPASS_QTB_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_SHFT 0x4 +#define HWIO_GCC_LPASS_QTB_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_BMSK 0xf +#define HWIO_GCC_LPASS_QTB_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_SHFT 0x0 + +#define HWIO_GCC_LPASS_QTB_CFG3_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008900c) +#define HWIO_GCC_LPASS_QTB_CFG3_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008900c) +#define HWIO_GCC_LPASS_QTB_CFG3_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008900c) +#define HWIO_GCC_LPASS_QTB_CFG3_GDSCR_RMSK 0x7ffffff +#define HWIO_GCC_LPASS_QTB_CFG3_GDSCR_ATTR 0x3 +#define HWIO_GCC_LPASS_QTB_CFG3_GDSCR_IN \ + in_dword_masked(HWIO_GCC_LPASS_QTB_CFG3_GDSCR_ADDR, HWIO_GCC_LPASS_QTB_CFG3_GDSCR_RMSK) +#define HWIO_GCC_LPASS_QTB_CFG3_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_LPASS_QTB_CFG3_GDSCR_ADDR, m) +#define HWIO_GCC_LPASS_QTB_CFG3_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_LPASS_QTB_CFG3_GDSCR_ADDR,v) +#define HWIO_GCC_LPASS_QTB_CFG3_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_LPASS_QTB_CFG3_GDSCR_ADDR,m,v,HWIO_GCC_LPASS_QTB_CFG3_GDSCR_IN) +#define HWIO_GCC_LPASS_QTB_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_STATUS_BMSK 0x4000000 +#define HWIO_GCC_LPASS_QTB_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_STATUS_SHFT 0x1a +#define HWIO_GCC_LPASS_QTB_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_BMSK 0x2000000 +#define HWIO_GCC_LPASS_QTB_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_SHFT 0x19 +#define HWIO_GCC_LPASS_QTB_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_QTB_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_QTB_CFG3_GDSCR_DLY_ACCU_RED_SHIFTER_DONE_BMSK 0x1e00000 +#define HWIO_GCC_LPASS_QTB_CFG3_GDSCR_DLY_ACCU_RED_SHIFTER_DONE_SHFT 0x15 +#define HWIO_GCC_LPASS_QTB_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_BMSK 0x100000 +#define HWIO_GCC_LPASS_QTB_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_SHFT 0x14 +#define HWIO_GCC_LPASS_QTB_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_QTB_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_QTB_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_BMSK 0x80000 +#define HWIO_GCC_LPASS_QTB_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_SHFT 0x13 +#define HWIO_GCC_LPASS_QTB_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_QTB_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_QTB_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_BMSK 0x40000 +#define HWIO_GCC_LPASS_QTB_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_SHFT 0x12 +#define HWIO_GCC_LPASS_QTB_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_QTB_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_QTB_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_BMSK 0x20000 +#define HWIO_GCC_LPASS_QTB_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_SHFT 0x11 +#define HWIO_GCC_LPASS_QTB_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_QTB_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_QTB_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_BMSK 0x10000 +#define HWIO_GCC_LPASS_QTB_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_SHFT 0x10 +#define HWIO_GCC_LPASS_QTB_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_QTB_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_QTB_CFG3_GDSCR_GDSC_SPARE_CTRL_IN_BMSK 0xff00 +#define HWIO_GCC_LPASS_QTB_CFG3_GDSCR_GDSC_SPARE_CTRL_IN_SHFT 0x8 +#define HWIO_GCC_LPASS_QTB_CFG3_GDSCR_GDSC_SPARE_CTRL_OUT_BMSK 0xff +#define HWIO_GCC_LPASS_QTB_CFG3_GDSCR_GDSC_SPARE_CTRL_OUT_SHFT 0x0 + +#define HWIO_GCC_LPASS_QTB_CFG4_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00089010) +#define HWIO_GCC_LPASS_QTB_CFG4_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00089010) +#define HWIO_GCC_LPASS_QTB_CFG4_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00089010) +#define HWIO_GCC_LPASS_QTB_CFG4_GDSCR_RMSK 0xffffff +#define HWIO_GCC_LPASS_QTB_CFG4_GDSCR_ATTR 0x3 +#define HWIO_GCC_LPASS_QTB_CFG4_GDSCR_IN \ + in_dword_masked(HWIO_GCC_LPASS_QTB_CFG4_GDSCR_ADDR, HWIO_GCC_LPASS_QTB_CFG4_GDSCR_RMSK) +#define HWIO_GCC_LPASS_QTB_CFG4_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_LPASS_QTB_CFG4_GDSCR_ADDR, m) +#define HWIO_GCC_LPASS_QTB_CFG4_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_LPASS_QTB_CFG4_GDSCR_ADDR,v) +#define HWIO_GCC_LPASS_QTB_CFG4_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_LPASS_QTB_CFG4_GDSCR_ADDR,m,v,HWIO_GCC_LPASS_QTB_CFG4_GDSCR_IN) +#define HWIO_GCC_LPASS_QTB_CFG4_GDSCR_DLY_UNCLAMPIO_BMSK 0xf00000 +#define HWIO_GCC_LPASS_QTB_CFG4_GDSCR_DLY_UNCLAMPIO_SHFT 0x14 +#define HWIO_GCC_LPASS_QTB_CFG4_GDSCR_DLY_RESTOREFF_BMSK 0xf0000 +#define HWIO_GCC_LPASS_QTB_CFG4_GDSCR_DLY_RESTOREFF_SHFT 0x10 +#define HWIO_GCC_LPASS_QTB_CFG4_GDSCR_DLY_NORETAINFF_BMSK 0xf000 +#define HWIO_GCC_LPASS_QTB_CFG4_GDSCR_DLY_NORETAINFF_SHFT 0xc +#define HWIO_GCC_LPASS_QTB_CFG4_GDSCR_DLY_DEASSERTARES_BMSK 0xf00 +#define HWIO_GCC_LPASS_QTB_CFG4_GDSCR_DLY_DEASSERTARES_SHFT 0x8 +#define HWIO_GCC_LPASS_QTB_CFG4_GDSCR_DLY_CLAMPIO_BMSK 0xf0 +#define HWIO_GCC_LPASS_QTB_CFG4_GDSCR_DLY_CLAMPIO_SHFT 0x4 +#define HWIO_GCC_LPASS_QTB_CFG4_GDSCR_DLY_RETAINFF_BMSK 0xf +#define HWIO_GCC_LPASS_QTB_CFG4_GDSCR_DLY_RETAINFF_SHFT 0x0 + +#define HWIO_GCC_LPASS_QTB_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00089014) +#define HWIO_GCC_LPASS_QTB_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00089014) +#define HWIO_GCC_LPASS_QTB_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00089014) +#define HWIO_GCC_LPASS_QTB_AHB_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_LPASS_QTB_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_LPASS_QTB_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_LPASS_QTB_AHB_CBCR_ADDR, HWIO_GCC_LPASS_QTB_AHB_CBCR_RMSK) +#define HWIO_GCC_LPASS_QTB_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_LPASS_QTB_AHB_CBCR_ADDR, m) +#define HWIO_GCC_LPASS_QTB_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_LPASS_QTB_AHB_CBCR_ADDR,v) +#define HWIO_GCC_LPASS_QTB_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_LPASS_QTB_AHB_CBCR_ADDR,m,v,HWIO_GCC_LPASS_QTB_AHB_CBCR_IN) +#define HWIO_GCC_LPASS_QTB_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_LPASS_QTB_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_LPASS_QTB_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_LPASS_QTB_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_LPASS_QTB_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_LPASS_QTB_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_LPASS_QTB_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_LPASS_QTB_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_LPASS_QTB_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_LPASS_QTB_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_LPASS_QTB_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_LPASS_QTB_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_LPASS_QTB_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_LPASS_QTB_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_LPASS_QTB_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_LPASS_QTB_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_LPASS_QTB_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_LPASS_QTB_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_LPASS_QTB_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_QTB_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_QTB_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_LPASS_QTB_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_LPASS_QTB_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_QTB_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_LPASS_AUDIO_QTB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00089018) +#define HWIO_GCC_LPASS_AUDIO_QTB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00089018) +#define HWIO_GCC_LPASS_AUDIO_QTB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00089018) +#define HWIO_GCC_LPASS_AUDIO_QTB_CBCR_RMSK 0x81f0700f +#define HWIO_GCC_LPASS_AUDIO_QTB_CBCR_ATTR 0x3 +#define HWIO_GCC_LPASS_AUDIO_QTB_CBCR_IN \ + in_dword_masked(HWIO_GCC_LPASS_AUDIO_QTB_CBCR_ADDR, HWIO_GCC_LPASS_AUDIO_QTB_CBCR_RMSK) +#define HWIO_GCC_LPASS_AUDIO_QTB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_LPASS_AUDIO_QTB_CBCR_ADDR, m) +#define HWIO_GCC_LPASS_AUDIO_QTB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_LPASS_AUDIO_QTB_CBCR_ADDR,v) +#define HWIO_GCC_LPASS_AUDIO_QTB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_LPASS_AUDIO_QTB_CBCR_ADDR,m,v,HWIO_GCC_LPASS_AUDIO_QTB_CBCR_IN) +#define HWIO_GCC_LPASS_AUDIO_QTB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_LPASS_AUDIO_QTB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_LPASS_AUDIO_QTB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_LPASS_AUDIO_QTB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_LPASS_AUDIO_QTB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_LPASS_AUDIO_QTB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_LPASS_AUDIO_QTB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_LPASS_AUDIO_QTB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_LPASS_AUDIO_QTB_CBCR_IGNORE_PMU_CLK_DIS_BMSK 0x200000 +#define HWIO_GCC_LPASS_AUDIO_QTB_CBCR_IGNORE_PMU_CLK_DIS_SHFT 0x15 +#define HWIO_GCC_LPASS_AUDIO_QTB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_LPASS_AUDIO_QTB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_LPASS_AUDIO_QTB_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_LPASS_AUDIO_QTB_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_LPASS_AUDIO_QTB_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_AUDIO_QTB_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_AUDIO_QTB_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_LPASS_AUDIO_QTB_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_LPASS_AUDIO_QTB_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_AUDIO_QTB_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_AUDIO_QTB_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_LPASS_AUDIO_QTB_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_LPASS_AUDIO_QTB_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_AUDIO_QTB_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_AUDIO_QTB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_LPASS_AUDIO_QTB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_LPASS_AUDIO_QTB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_LPASS_AUDIO_QTB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_LPASS_AUDIO_QTB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_LPASS_AUDIO_QTB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_LPASS_AUDIO_QTB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_LPASS_AUDIO_QTB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_LPASS_AUDIO_QTB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_AUDIO_QTB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_AUDIO_QTB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_LPASS_AUDIO_QTB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_LPASS_AUDIO_QTB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_AUDIO_QTB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008901c) +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008901c) +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008901c) +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_RMSK 0xf1ffffe +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_ATTR 0x3 +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_IN \ + in_dword_masked(HWIO_GCC_LPASS_AUDIO_QTB_SREGR_ADDR, HWIO_GCC_LPASS_AUDIO_QTB_SREGR_RMSK) +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_LPASS_AUDIO_QTB_SREGR_ADDR, m) +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_OUT(v) \ + out_dword(HWIO_GCC_LPASS_AUDIO_QTB_SREGR_ADDR,v) +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_LPASS_AUDIO_QTB_SREGR_ADDR,m,v,HWIO_GCC_LPASS_AUDIO_QTB_SREGR_IN) +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xf000000 +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_PWR_FSM_CLK_SEL_BMSK 0x100000 +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_PWR_FSM_CLK_SEL_SHFT 0x14 +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xf0000 +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_AUDIO_QTB_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_LPASS_AUDIO_QTB_CFG_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00089020) +#define HWIO_GCC_LPASS_AUDIO_QTB_CFG_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00089020) +#define HWIO_GCC_LPASS_AUDIO_QTB_CFG_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00089020) +#define HWIO_GCC_LPASS_AUDIO_QTB_CFG_SREGR_RMSK 0xffffffff +#define HWIO_GCC_LPASS_AUDIO_QTB_CFG_SREGR_ATTR 0x3 +#define HWIO_GCC_LPASS_AUDIO_QTB_CFG_SREGR_IN \ + in_dword_masked(HWIO_GCC_LPASS_AUDIO_QTB_CFG_SREGR_ADDR, HWIO_GCC_LPASS_AUDIO_QTB_CFG_SREGR_RMSK) +#define HWIO_GCC_LPASS_AUDIO_QTB_CFG_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_LPASS_AUDIO_QTB_CFG_SREGR_ADDR, m) +#define HWIO_GCC_LPASS_AUDIO_QTB_CFG_SREGR_OUT(v) \ + out_dword(HWIO_GCC_LPASS_AUDIO_QTB_CFG_SREGR_ADDR,v) +#define HWIO_GCC_LPASS_AUDIO_QTB_CFG_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_LPASS_AUDIO_QTB_CFG_SREGR_ADDR,m,v,HWIO_GCC_LPASS_AUDIO_QTB_CFG_SREGR_IN) +#define HWIO_GCC_LPASS_AUDIO_QTB_CFG_SREGR_MEM_CORE_OFF_TIMER_BMSK 0xfc000000 +#define HWIO_GCC_LPASS_AUDIO_QTB_CFG_SREGR_MEM_CORE_OFF_TIMER_SHFT 0x1a +#define HWIO_GCC_LPASS_AUDIO_QTB_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_BMSK 0x2000000 +#define HWIO_GCC_LPASS_AUDIO_QTB_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_SHFT 0x19 +#define HWIO_GCC_LPASS_AUDIO_QTB_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_BMSK 0x1000000 +#define HWIO_GCC_LPASS_AUDIO_QTB_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_SHFT 0x18 +#define HWIO_GCC_LPASS_AUDIO_QTB_CFG_SREGR_MEM_PERIPH_ON_STATUS_BMSK 0x800000 +#define HWIO_GCC_LPASS_AUDIO_QTB_CFG_SREGR_MEM_PERIPH_ON_STATUS_SHFT 0x17 +#define HWIO_GCC_LPASS_AUDIO_QTB_CFG_SREGR_MEM_CORE_ON_STATUS_BMSK 0x400000 +#define HWIO_GCC_LPASS_AUDIO_QTB_CFG_SREGR_MEM_CORE_ON_STATUS_SHFT 0x16 +#define HWIO_GCC_LPASS_AUDIO_QTB_CFG_SREGR_MEM_CPH_TIMER_BMSK 0x3f0000 +#define HWIO_GCC_LPASS_AUDIO_QTB_CFG_SREGR_MEM_CPH_TIMER_SHFT 0x10 +#define HWIO_GCC_LPASS_AUDIO_QTB_CFG_SREGR_SLEEP_TIMER_BMSK 0xff00 +#define HWIO_GCC_LPASS_AUDIO_QTB_CFG_SREGR_SLEEP_TIMER_SHFT 0x8 +#define HWIO_GCC_LPASS_AUDIO_QTB_CFG_SREGR_WAKEUP_TIMER_BMSK 0xff +#define HWIO_GCC_LPASS_AUDIO_QTB_CFG_SREGR_WAKEUP_TIMER_SHFT 0x0 + +#define HWIO_GCC_LPASS_QOSGEN_EXTREF_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00089024) +#define HWIO_GCC_LPASS_QOSGEN_EXTREF_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00089024) +#define HWIO_GCC_LPASS_QOSGEN_EXTREF_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00089024) +#define HWIO_GCC_LPASS_QOSGEN_EXTREF_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_LPASS_QOSGEN_EXTREF_CBCR_ATTR 0x3 +#define HWIO_GCC_LPASS_QOSGEN_EXTREF_CBCR_IN \ + in_dword_masked(HWIO_GCC_LPASS_QOSGEN_EXTREF_CBCR_ADDR, HWIO_GCC_LPASS_QOSGEN_EXTREF_CBCR_RMSK) +#define HWIO_GCC_LPASS_QOSGEN_EXTREF_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_LPASS_QOSGEN_EXTREF_CBCR_ADDR, m) +#define HWIO_GCC_LPASS_QOSGEN_EXTREF_CBCR_OUT(v) \ + out_dword(HWIO_GCC_LPASS_QOSGEN_EXTREF_CBCR_ADDR,v) +#define HWIO_GCC_LPASS_QOSGEN_EXTREF_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_LPASS_QOSGEN_EXTREF_CBCR_ADDR,m,v,HWIO_GCC_LPASS_QOSGEN_EXTREF_CBCR_IN) +#define HWIO_GCC_LPASS_QOSGEN_EXTREF_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_LPASS_QOSGEN_EXTREF_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_LPASS_QOSGEN_EXTREF_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_LPASS_QOSGEN_EXTREF_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_LPASS_QOSGEN_EXTREF_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_LPASS_QOSGEN_EXTREF_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_LPASS_QOSGEN_EXTREF_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_LPASS_QOSGEN_EXTREF_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_LPASS_QOSGEN_EXTREF_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_LPASS_QOSGEN_EXTREF_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_LPASS_QOSGEN_EXTREF_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_LPASS_QOSGEN_EXTREF_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_LPASS_QOSGEN_EXTREF_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_LPASS_QOSGEN_EXTREF_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_LPASS_QOSGEN_EXTREF_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_QOSGEN_EXTREF_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_LPASS_QDSS_TSCTR_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00089028) +#define HWIO_GCC_LPASS_QDSS_TSCTR_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00089028) +#define HWIO_GCC_LPASS_QDSS_TSCTR_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00089028) +#define HWIO_GCC_LPASS_QDSS_TSCTR_CBCR_RMSK 0x81c0000f +#define HWIO_GCC_LPASS_QDSS_TSCTR_CBCR_ATTR 0x3 +#define HWIO_GCC_LPASS_QDSS_TSCTR_CBCR_IN \ + in_dword_masked(HWIO_GCC_LPASS_QDSS_TSCTR_CBCR_ADDR, HWIO_GCC_LPASS_QDSS_TSCTR_CBCR_RMSK) +#define HWIO_GCC_LPASS_QDSS_TSCTR_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_LPASS_QDSS_TSCTR_CBCR_ADDR, m) +#define HWIO_GCC_LPASS_QDSS_TSCTR_CBCR_OUT(v) \ + out_dword(HWIO_GCC_LPASS_QDSS_TSCTR_CBCR_ADDR,v) +#define HWIO_GCC_LPASS_QDSS_TSCTR_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_LPASS_QDSS_TSCTR_CBCR_ADDR,m,v,HWIO_GCC_LPASS_QDSS_TSCTR_CBCR_IN) +#define HWIO_GCC_LPASS_QDSS_TSCTR_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_LPASS_QDSS_TSCTR_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_LPASS_QDSS_TSCTR_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_LPASS_QDSS_TSCTR_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_LPASS_QDSS_TSCTR_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_LPASS_QDSS_TSCTR_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_LPASS_QDSS_TSCTR_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_LPASS_QDSS_TSCTR_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_LPASS_QDSS_TSCTR_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_LPASS_QDSS_TSCTR_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_LPASS_QDSS_TSCTR_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_LPASS_QDSS_TSCTR_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_LPASS_QDSS_TSCTR_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_LPASS_QDSS_TSCTR_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_LPASS_QDSS_TSCTR_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_LPASS_QDSS_TSCTR_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_LPASS_QDSS_TSCTR_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_QDSS_TSCTR_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_QDSS_TSCTR_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_LPASS_QDSS_TSCTR_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_LPASS_QDSS_TSCTR_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_QDSS_TSCTR_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_LPASS_QTB_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008902c) +#define HWIO_GCC_LPASS_QTB_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008902c) +#define HWIO_GCC_LPASS_QTB_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008902c) +#define HWIO_GCC_LPASS_QTB_AT_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_LPASS_QTB_AT_CBCR_ATTR 0x3 +#define HWIO_GCC_LPASS_QTB_AT_CBCR_IN \ + in_dword_masked(HWIO_GCC_LPASS_QTB_AT_CBCR_ADDR, HWIO_GCC_LPASS_QTB_AT_CBCR_RMSK) +#define HWIO_GCC_LPASS_QTB_AT_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_LPASS_QTB_AT_CBCR_ADDR, m) +#define HWIO_GCC_LPASS_QTB_AT_CBCR_OUT(v) \ + out_dword(HWIO_GCC_LPASS_QTB_AT_CBCR_ADDR,v) +#define HWIO_GCC_LPASS_QTB_AT_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_LPASS_QTB_AT_CBCR_ADDR,m,v,HWIO_GCC_LPASS_QTB_AT_CBCR_IN) +#define HWIO_GCC_LPASS_QTB_AT_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_LPASS_QTB_AT_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_LPASS_QTB_AT_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_LPASS_QTB_AT_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_LPASS_QTB_AT_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_LPASS_QTB_AT_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_LPASS_QTB_AT_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_LPASS_QTB_AT_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_LPASS_QTB_AT_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_LPASS_QTB_AT_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_LPASS_QTB_AT_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_LPASS_QTB_AT_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_LPASS_QTB_AT_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_LPASS_QTB_AT_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_LPASS_QTB_AT_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_LPASS_QTB_AT_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_LPASS_QTB_AT_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_LPASS_QTB_AT_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_LPASS_QTB_AT_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_QTB_AT_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_QTB_AT_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_LPASS_QTB_AT_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_LPASS_QTB_AT_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_QTB_AT_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_LPASS_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00089030) +#define HWIO_GCC_LPASS_XO_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00089030) +#define HWIO_GCC_LPASS_XO_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00089030) +#define HWIO_GCC_LPASS_XO_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_LPASS_XO_CBCR_ATTR 0x3 +#define HWIO_GCC_LPASS_XO_CBCR_IN \ + in_dword_masked(HWIO_GCC_LPASS_XO_CBCR_ADDR, HWIO_GCC_LPASS_XO_CBCR_RMSK) +#define HWIO_GCC_LPASS_XO_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_LPASS_XO_CBCR_ADDR, m) +#define HWIO_GCC_LPASS_XO_CBCR_OUT(v) \ + out_dword(HWIO_GCC_LPASS_XO_CBCR_ADDR,v) +#define HWIO_GCC_LPASS_XO_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_LPASS_XO_CBCR_ADDR,m,v,HWIO_GCC_LPASS_XO_CBCR_IN) +#define HWIO_GCC_LPASS_XO_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_LPASS_XO_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_LPASS_XO_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_LPASS_XO_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_LPASS_XO_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_LPASS_XO_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_LPASS_XO_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_LPASS_XO_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_LPASS_XO_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_LPASS_XO_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_LPASS_XO_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_LPASS_XO_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_LPASS_XO_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_LPASS_XO_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_LPASS_XO_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_XO_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_LPASS_PWRCTL_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00089034) +#define HWIO_GCC_LPASS_PWRCTL_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00089034) +#define HWIO_GCC_LPASS_PWRCTL_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00089034) +#define HWIO_GCC_LPASS_PWRCTL_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_LPASS_PWRCTL_CBCR_ATTR 0x3 +#define HWIO_GCC_LPASS_PWRCTL_CBCR_IN \ + in_dword_masked(HWIO_GCC_LPASS_PWRCTL_CBCR_ADDR, HWIO_GCC_LPASS_PWRCTL_CBCR_RMSK) +#define HWIO_GCC_LPASS_PWRCTL_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_LPASS_PWRCTL_CBCR_ADDR, m) +#define HWIO_GCC_LPASS_PWRCTL_CBCR_OUT(v) \ + out_dword(HWIO_GCC_LPASS_PWRCTL_CBCR_ADDR,v) +#define HWIO_GCC_LPASS_PWRCTL_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_LPASS_PWRCTL_CBCR_ADDR,m,v,HWIO_GCC_LPASS_PWRCTL_CBCR_IN) +#define HWIO_GCC_LPASS_PWRCTL_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_LPASS_PWRCTL_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_LPASS_PWRCTL_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_LPASS_PWRCTL_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_LPASS_PWRCTL_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_LPASS_PWRCTL_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_LPASS_PWRCTL_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_LPASS_PWRCTL_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_LPASS_PWRCTL_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_LPASS_PWRCTL_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_LPASS_PWRCTL_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_LPASS_PWRCTL_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_LPASS_PWRCTL_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_LPASS_PWRCTL_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_LPASS_PWRCTL_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_LPASS_PWRCTL_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_LPASS_PWRCTL_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_LPASS_PWRCTL_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_LPASS_PWRCTL_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_PWRCTL_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_PWRCTL_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_LPASS_PWRCTL_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_LPASS_PWRCTL_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_PWRCTL_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TURING_QTB_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008d000) +#define HWIO_GCC_TURING_QTB_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008d000) +#define HWIO_GCC_TURING_QTB_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008d000) +#define HWIO_GCC_TURING_QTB_GDSCR_RMSK 0xf8ffffff +#define HWIO_GCC_TURING_QTB_GDSCR_ATTR 0x3 +#define HWIO_GCC_TURING_QTB_GDSCR_IN \ + in_dword_masked(HWIO_GCC_TURING_QTB_GDSCR_ADDR, HWIO_GCC_TURING_QTB_GDSCR_RMSK) +#define HWIO_GCC_TURING_QTB_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_TURING_QTB_GDSCR_ADDR, m) +#define HWIO_GCC_TURING_QTB_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_TURING_QTB_GDSCR_ADDR,v) +#define HWIO_GCC_TURING_QTB_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TURING_QTB_GDSCR_ADDR,m,v,HWIO_GCC_TURING_QTB_GDSCR_IN) +#define HWIO_GCC_TURING_QTB_GDSCR_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_TURING_QTB_GDSCR_PWR_ON_SHFT 0x1f +#define HWIO_GCC_TURING_QTB_GDSCR_GDSC_STATE_BMSK 0x78000000 +#define HWIO_GCC_TURING_QTB_GDSCR_GDSC_STATE_SHFT 0x1b +#define HWIO_GCC_TURING_QTB_GDSCR_EN_REST_WAIT_BMSK 0xf00000 +#define HWIO_GCC_TURING_QTB_GDSCR_EN_REST_WAIT_SHFT 0x14 +#define HWIO_GCC_TURING_QTB_GDSCR_EN_FEW_WAIT_BMSK 0xf0000 +#define HWIO_GCC_TURING_QTB_GDSCR_EN_FEW_WAIT_SHFT 0x10 +#define HWIO_GCC_TURING_QTB_GDSCR_CLK_DIS_WAIT_BMSK 0xf000 +#define HWIO_GCC_TURING_QTB_GDSCR_CLK_DIS_WAIT_SHFT 0xc +#define HWIO_GCC_TURING_QTB_GDSCR_RETAIN_FF_ENABLE_BMSK 0x800 +#define HWIO_GCC_TURING_QTB_GDSCR_RETAIN_FF_ENABLE_SHFT 0xb +#define HWIO_GCC_TURING_QTB_GDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_QTB_GDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_QTB_GDSCR_RESTORE_BMSK 0x400 +#define HWIO_GCC_TURING_QTB_GDSCR_RESTORE_SHFT 0xa +#define HWIO_GCC_TURING_QTB_GDSCR_RESTORE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_QTB_GDSCR_RESTORE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_QTB_GDSCR_SAVE_BMSK 0x200 +#define HWIO_GCC_TURING_QTB_GDSCR_SAVE_SHFT 0x9 +#define HWIO_GCC_TURING_QTB_GDSCR_SAVE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_QTB_GDSCR_SAVE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_QTB_GDSCR_RETAIN_BMSK 0x100 +#define HWIO_GCC_TURING_QTB_GDSCR_RETAIN_SHFT 0x8 +#define HWIO_GCC_TURING_QTB_GDSCR_RETAIN_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_QTB_GDSCR_RETAIN_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_QTB_GDSCR_EN_REST_BMSK 0x80 +#define HWIO_GCC_TURING_QTB_GDSCR_EN_REST_SHFT 0x7 +#define HWIO_GCC_TURING_QTB_GDSCR_EN_REST_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_QTB_GDSCR_EN_REST_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_QTB_GDSCR_EN_FEW_BMSK 0x40 +#define HWIO_GCC_TURING_QTB_GDSCR_EN_FEW_SHFT 0x6 +#define HWIO_GCC_TURING_QTB_GDSCR_EN_FEW_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_QTB_GDSCR_EN_FEW_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_QTB_GDSCR_CLAMP_IO_BMSK 0x20 +#define HWIO_GCC_TURING_QTB_GDSCR_CLAMP_IO_SHFT 0x5 +#define HWIO_GCC_TURING_QTB_GDSCR_CLAMP_IO_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_QTB_GDSCR_CLAMP_IO_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_QTB_GDSCR_CLK_DISABLE_BMSK 0x10 +#define HWIO_GCC_TURING_QTB_GDSCR_CLK_DISABLE_SHFT 0x4 +#define HWIO_GCC_TURING_QTB_GDSCR_CLK_DISABLE_CLK_NOT_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_QTB_GDSCR_CLK_DISABLE_CLK_IS_DISABLE_FVAL 0x1 +#define HWIO_GCC_TURING_QTB_GDSCR_PD_ARES_BMSK 0x8 +#define HWIO_GCC_TURING_QTB_GDSCR_PD_ARES_SHFT 0x3 +#define HWIO_GCC_TURING_QTB_GDSCR_PD_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_TURING_QTB_GDSCR_PD_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_TURING_QTB_GDSCR_SW_OVERRIDE_BMSK 0x4 +#define HWIO_GCC_TURING_QTB_GDSCR_SW_OVERRIDE_SHFT 0x2 +#define HWIO_GCC_TURING_QTB_GDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_QTB_GDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_QTB_GDSCR_HW_CONTROL_BMSK 0x2 +#define HWIO_GCC_TURING_QTB_GDSCR_HW_CONTROL_SHFT 0x1 +#define HWIO_GCC_TURING_QTB_GDSCR_HW_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_QTB_GDSCR_HW_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_QTB_GDSCR_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_TURING_QTB_GDSCR_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_TURING_QTB_GDSCR_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_QTB_GDSCR_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TURING_QTB_CFG_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008d004) +#define HWIO_GCC_TURING_QTB_CFG_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008d004) +#define HWIO_GCC_TURING_QTB_CFG_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008d004) +#define HWIO_GCC_TURING_QTB_CFG_GDSCR_RMSK 0x7ffffff +#define HWIO_GCC_TURING_QTB_CFG_GDSCR_ATTR 0x3 +#define HWIO_GCC_TURING_QTB_CFG_GDSCR_IN \ + in_dword_masked(HWIO_GCC_TURING_QTB_CFG_GDSCR_ADDR, HWIO_GCC_TURING_QTB_CFG_GDSCR_RMSK) +#define HWIO_GCC_TURING_QTB_CFG_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_TURING_QTB_CFG_GDSCR_ADDR, m) +#define HWIO_GCC_TURING_QTB_CFG_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_TURING_QTB_CFG_GDSCR_ADDR,v) +#define HWIO_GCC_TURING_QTB_CFG_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TURING_QTB_CFG_GDSCR_ADDR,m,v,HWIO_GCC_TURING_QTB_CFG_GDSCR_IN) +#define HWIO_GCC_TURING_QTB_CFG_GDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4000000 +#define HWIO_GCC_TURING_QTB_CFG_GDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x1a +#define HWIO_GCC_TURING_QTB_CFG_GDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_QTB_CFG_GDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_QTB_CFG_GDSCR_GDSC_PWR_DWN_START_BMSK 0x2000000 +#define HWIO_GCC_TURING_QTB_CFG_GDSCR_GDSC_PWR_DWN_START_SHFT 0x19 +#define HWIO_GCC_TURING_QTB_CFG_GDSCR_GDSC_PWR_UP_START_BMSK 0x1000000 +#define HWIO_GCC_TURING_QTB_CFG_GDSCR_GDSC_PWR_UP_START_SHFT 0x18 +#define HWIO_GCC_TURING_QTB_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_BMSK 0xf00000 +#define HWIO_GCC_TURING_QTB_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_SHFT 0x14 +#define HWIO_GCC_TURING_QTB_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_BMSK 0x80000 +#define HWIO_GCC_TURING_QTB_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_SHFT 0x13 +#define HWIO_GCC_TURING_QTB_CFG_GDSCR_GDSC_ENR_ACK_STATUS_BMSK 0x40000 +#define HWIO_GCC_TURING_QTB_CFG_GDSCR_GDSC_ENR_ACK_STATUS_SHFT 0x12 +#define HWIO_GCC_TURING_QTB_CFG_GDSCR_GDSC_ENF_ACK_STATUS_BMSK 0x20000 +#define HWIO_GCC_TURING_QTB_CFG_GDSCR_GDSC_ENF_ACK_STATUS_SHFT 0x11 +#define HWIO_GCC_TURING_QTB_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_BMSK 0x10000 +#define HWIO_GCC_TURING_QTB_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_SHFT 0x10 +#define HWIO_GCC_TURING_QTB_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_BMSK 0x8000 +#define HWIO_GCC_TURING_QTB_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_SHFT 0xf +#define HWIO_GCC_TURING_QTB_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_BMSK 0x7800 +#define HWIO_GCC_TURING_QTB_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_SHFT 0xb +#define HWIO_GCC_TURING_QTB_CFG_GDSCR_GDSC_HANDSHAKE_DIS_BMSK 0x400 +#define HWIO_GCC_TURING_QTB_CFG_GDSCR_GDSC_HANDSHAKE_DIS_SHFT 0xa +#define HWIO_GCC_TURING_QTB_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_BMSK 0x200 +#define HWIO_GCC_TURING_QTB_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_SHFT 0x9 +#define HWIO_GCC_TURING_QTB_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_BMSK 0x100 +#define HWIO_GCC_TURING_QTB_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_SHFT 0x8 +#define HWIO_GCC_TURING_QTB_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_BMSK 0x80 +#define HWIO_GCC_TURING_QTB_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_SHFT 0x7 +#define HWIO_GCC_TURING_QTB_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_BMSK 0x60 +#define HWIO_GCC_TURING_QTB_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_SHFT 0x5 +#define HWIO_GCC_TURING_QTB_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_BMSK 0x10 +#define HWIO_GCC_TURING_QTB_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_SHFT 0x4 +#define HWIO_GCC_TURING_QTB_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_BMSK 0x8 +#define HWIO_GCC_TURING_QTB_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_SHFT 0x3 +#define HWIO_GCC_TURING_QTB_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_BMSK 0x4 +#define HWIO_GCC_TURING_QTB_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_SHFT 0x2 +#define HWIO_GCC_TURING_QTB_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_BMSK 0x2 +#define HWIO_GCC_TURING_QTB_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_SHFT 0x1 +#define HWIO_GCC_TURING_QTB_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_TURING_QTB_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_SHFT 0x0 + +#define HWIO_GCC_TURING_QTB_CFG2_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008d008) +#define HWIO_GCC_TURING_QTB_CFG2_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008d008) +#define HWIO_GCC_TURING_QTB_CFG2_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008d008) +#define HWIO_GCC_TURING_QTB_CFG2_GDSCR_RMSK 0x7ffff +#define HWIO_GCC_TURING_QTB_CFG2_GDSCR_ATTR 0x3 +#define HWIO_GCC_TURING_QTB_CFG2_GDSCR_IN \ + in_dword_masked(HWIO_GCC_TURING_QTB_CFG2_GDSCR_ADDR, HWIO_GCC_TURING_QTB_CFG2_GDSCR_RMSK) +#define HWIO_GCC_TURING_QTB_CFG2_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_TURING_QTB_CFG2_GDSCR_ADDR, m) +#define HWIO_GCC_TURING_QTB_CFG2_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_TURING_QTB_CFG2_GDSCR_ADDR,v) +#define HWIO_GCC_TURING_QTB_CFG2_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TURING_QTB_CFG2_GDSCR_ADDR,m,v,HWIO_GCC_TURING_QTB_CFG2_GDSCR_IN) +#define HWIO_GCC_TURING_QTB_CFG2_GDSCR_GDSC_MEM_PWRUP_ACK_OVERRIDE_BMSK 0x40000 +#define HWIO_GCC_TURING_QTB_CFG2_GDSCR_GDSC_MEM_PWRUP_ACK_OVERRIDE_SHFT 0x12 +#define HWIO_GCC_TURING_QTB_CFG2_GDSCR_GDSC_PWRDWN_ENABLE_ACK_OVERRIDE_BMSK 0x20000 +#define HWIO_GCC_TURING_QTB_CFG2_GDSCR_GDSC_PWRDWN_ENABLE_ACK_OVERRIDE_SHFT 0x11 +#define HWIO_GCC_TURING_QTB_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_BMSK 0x10000 +#define HWIO_GCC_TURING_QTB_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_SHFT 0x10 +#define HWIO_GCC_TURING_QTB_CFG2_GDSCR_DLY_MEM_PWR_UP_BMSK 0xf000 +#define HWIO_GCC_TURING_QTB_CFG2_GDSCR_DLY_MEM_PWR_UP_SHFT 0xc +#define HWIO_GCC_TURING_QTB_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_BMSK 0xf00 +#define HWIO_GCC_TURING_QTB_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_SHFT 0x8 +#define HWIO_GCC_TURING_QTB_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_BMSK 0xf0 +#define HWIO_GCC_TURING_QTB_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_SHFT 0x4 +#define HWIO_GCC_TURING_QTB_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_BMSK 0xf +#define HWIO_GCC_TURING_QTB_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_SHFT 0x0 + +#define HWIO_GCC_TURING_QTB_CFG3_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008d00c) +#define HWIO_GCC_TURING_QTB_CFG3_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008d00c) +#define HWIO_GCC_TURING_QTB_CFG3_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008d00c) +#define HWIO_GCC_TURING_QTB_CFG3_GDSCR_RMSK 0x7ffffff +#define HWIO_GCC_TURING_QTB_CFG3_GDSCR_ATTR 0x3 +#define HWIO_GCC_TURING_QTB_CFG3_GDSCR_IN \ + in_dword_masked(HWIO_GCC_TURING_QTB_CFG3_GDSCR_ADDR, HWIO_GCC_TURING_QTB_CFG3_GDSCR_RMSK) +#define HWIO_GCC_TURING_QTB_CFG3_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_TURING_QTB_CFG3_GDSCR_ADDR, m) +#define HWIO_GCC_TURING_QTB_CFG3_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_TURING_QTB_CFG3_GDSCR_ADDR,v) +#define HWIO_GCC_TURING_QTB_CFG3_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TURING_QTB_CFG3_GDSCR_ADDR,m,v,HWIO_GCC_TURING_QTB_CFG3_GDSCR_IN) +#define HWIO_GCC_TURING_QTB_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_STATUS_BMSK 0x4000000 +#define HWIO_GCC_TURING_QTB_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_STATUS_SHFT 0x1a +#define HWIO_GCC_TURING_QTB_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_BMSK 0x2000000 +#define HWIO_GCC_TURING_QTB_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_SHFT 0x19 +#define HWIO_GCC_TURING_QTB_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_QTB_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_QTB_CFG3_GDSCR_DLY_ACCU_RED_SHIFTER_DONE_BMSK 0x1e00000 +#define HWIO_GCC_TURING_QTB_CFG3_GDSCR_DLY_ACCU_RED_SHIFTER_DONE_SHFT 0x15 +#define HWIO_GCC_TURING_QTB_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_BMSK 0x100000 +#define HWIO_GCC_TURING_QTB_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_SHFT 0x14 +#define HWIO_GCC_TURING_QTB_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_QTB_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_QTB_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_BMSK 0x80000 +#define HWIO_GCC_TURING_QTB_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_SHFT 0x13 +#define HWIO_GCC_TURING_QTB_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_QTB_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_QTB_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_BMSK 0x40000 +#define HWIO_GCC_TURING_QTB_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_SHFT 0x12 +#define HWIO_GCC_TURING_QTB_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_QTB_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_QTB_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_BMSK 0x20000 +#define HWIO_GCC_TURING_QTB_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_SHFT 0x11 +#define HWIO_GCC_TURING_QTB_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_QTB_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_QTB_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_BMSK 0x10000 +#define HWIO_GCC_TURING_QTB_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_SHFT 0x10 +#define HWIO_GCC_TURING_QTB_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_QTB_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_QTB_CFG3_GDSCR_GDSC_SPARE_CTRL_IN_BMSK 0xff00 +#define HWIO_GCC_TURING_QTB_CFG3_GDSCR_GDSC_SPARE_CTRL_IN_SHFT 0x8 +#define HWIO_GCC_TURING_QTB_CFG3_GDSCR_GDSC_SPARE_CTRL_OUT_BMSK 0xff +#define HWIO_GCC_TURING_QTB_CFG3_GDSCR_GDSC_SPARE_CTRL_OUT_SHFT 0x0 + +#define HWIO_GCC_TURING_QTB_CFG4_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008d010) +#define HWIO_GCC_TURING_QTB_CFG4_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008d010) +#define HWIO_GCC_TURING_QTB_CFG4_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008d010) +#define HWIO_GCC_TURING_QTB_CFG4_GDSCR_RMSK 0xffffff +#define HWIO_GCC_TURING_QTB_CFG4_GDSCR_ATTR 0x3 +#define HWIO_GCC_TURING_QTB_CFG4_GDSCR_IN \ + in_dword_masked(HWIO_GCC_TURING_QTB_CFG4_GDSCR_ADDR, HWIO_GCC_TURING_QTB_CFG4_GDSCR_RMSK) +#define HWIO_GCC_TURING_QTB_CFG4_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_TURING_QTB_CFG4_GDSCR_ADDR, m) +#define HWIO_GCC_TURING_QTB_CFG4_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_TURING_QTB_CFG4_GDSCR_ADDR,v) +#define HWIO_GCC_TURING_QTB_CFG4_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TURING_QTB_CFG4_GDSCR_ADDR,m,v,HWIO_GCC_TURING_QTB_CFG4_GDSCR_IN) +#define HWIO_GCC_TURING_QTB_CFG4_GDSCR_DLY_UNCLAMPIO_BMSK 0xf00000 +#define HWIO_GCC_TURING_QTB_CFG4_GDSCR_DLY_UNCLAMPIO_SHFT 0x14 +#define HWIO_GCC_TURING_QTB_CFG4_GDSCR_DLY_RESTOREFF_BMSK 0xf0000 +#define HWIO_GCC_TURING_QTB_CFG4_GDSCR_DLY_RESTOREFF_SHFT 0x10 +#define HWIO_GCC_TURING_QTB_CFG4_GDSCR_DLY_NORETAINFF_BMSK 0xf000 +#define HWIO_GCC_TURING_QTB_CFG4_GDSCR_DLY_NORETAINFF_SHFT 0xc +#define HWIO_GCC_TURING_QTB_CFG4_GDSCR_DLY_DEASSERTARES_BMSK 0xf00 +#define HWIO_GCC_TURING_QTB_CFG4_GDSCR_DLY_DEASSERTARES_SHFT 0x8 +#define HWIO_GCC_TURING_QTB_CFG4_GDSCR_DLY_CLAMPIO_BMSK 0xf0 +#define HWIO_GCC_TURING_QTB_CFG4_GDSCR_DLY_CLAMPIO_SHFT 0x4 +#define HWIO_GCC_TURING_QTB_CFG4_GDSCR_DLY_RETAINFF_BMSK 0xf +#define HWIO_GCC_TURING_QTB_CFG4_GDSCR_DLY_RETAINFF_SHFT 0x0 + +#define HWIO_GCC_TURING_Q6_QTB0_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008d014) +#define HWIO_GCC_TURING_Q6_QTB0_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008d014) +#define HWIO_GCC_TURING_Q6_QTB0_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008d014) +#define HWIO_GCC_TURING_Q6_QTB0_CBCR_RMSK 0x81f0700f +#define HWIO_GCC_TURING_Q6_QTB0_CBCR_ATTR 0x3 +#define HWIO_GCC_TURING_Q6_QTB0_CBCR_IN \ + in_dword_masked(HWIO_GCC_TURING_Q6_QTB0_CBCR_ADDR, HWIO_GCC_TURING_Q6_QTB0_CBCR_RMSK) +#define HWIO_GCC_TURING_Q6_QTB0_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_TURING_Q6_QTB0_CBCR_ADDR, m) +#define HWIO_GCC_TURING_Q6_QTB0_CBCR_OUT(v) \ + out_dword(HWIO_GCC_TURING_Q6_QTB0_CBCR_ADDR,v) +#define HWIO_GCC_TURING_Q6_QTB0_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TURING_Q6_QTB0_CBCR_ADDR,m,v,HWIO_GCC_TURING_Q6_QTB0_CBCR_IN) +#define HWIO_GCC_TURING_Q6_QTB0_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TURING_Q6_QTB0_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TURING_Q6_QTB0_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_TURING_Q6_QTB0_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_TURING_Q6_QTB0_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_TURING_Q6_QTB0_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_TURING_Q6_QTB0_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_TURING_Q6_QTB0_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_TURING_Q6_QTB0_CBCR_IGNORE_PMU_CLK_DIS_BMSK 0x200000 +#define HWIO_GCC_TURING_Q6_QTB0_CBCR_IGNORE_PMU_CLK_DIS_SHFT 0x15 +#define HWIO_GCC_TURING_Q6_QTB0_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_TURING_Q6_QTB0_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_TURING_Q6_QTB0_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_TURING_Q6_QTB0_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_TURING_Q6_QTB0_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_Q6_QTB0_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_Q6_QTB0_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_TURING_Q6_QTB0_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_TURING_Q6_QTB0_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_Q6_QTB0_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_Q6_QTB0_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_TURING_Q6_QTB0_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_TURING_Q6_QTB0_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_Q6_QTB0_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_Q6_QTB0_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_TURING_Q6_QTB0_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_TURING_Q6_QTB0_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_TURING_Q6_QTB0_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_TURING_Q6_QTB0_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_TURING_Q6_QTB0_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_TURING_Q6_QTB0_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_TURING_Q6_QTB0_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_TURING_Q6_QTB0_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_Q6_QTB0_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_Q6_QTB0_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_TURING_Q6_QTB0_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_TURING_Q6_QTB0_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_Q6_QTB0_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008d018) +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008d018) +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008d018) +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_RMSK 0xf1ffffe +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_ATTR 0x3 +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_IN \ + in_dword_masked(HWIO_GCC_TURING_Q6_QTB0_SREGR_ADDR, HWIO_GCC_TURING_Q6_QTB0_SREGR_RMSK) +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_TURING_Q6_QTB0_SREGR_ADDR, m) +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_OUT(v) \ + out_dword(HWIO_GCC_TURING_Q6_QTB0_SREGR_ADDR,v) +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TURING_Q6_QTB0_SREGR_ADDR,m,v,HWIO_GCC_TURING_Q6_QTB0_SREGR_IN) +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xf000000 +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_PWR_FSM_CLK_SEL_BMSK 0x100000 +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_PWR_FSM_CLK_SEL_SHFT 0x14 +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xf0000 +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_Q6_QTB0_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TURING_Q6_QTB0_CFG_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008d01c) +#define HWIO_GCC_TURING_Q6_QTB0_CFG_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008d01c) +#define HWIO_GCC_TURING_Q6_QTB0_CFG_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008d01c) +#define HWIO_GCC_TURING_Q6_QTB0_CFG_SREGR_RMSK 0xffffffff +#define HWIO_GCC_TURING_Q6_QTB0_CFG_SREGR_ATTR 0x3 +#define HWIO_GCC_TURING_Q6_QTB0_CFG_SREGR_IN \ + in_dword_masked(HWIO_GCC_TURING_Q6_QTB0_CFG_SREGR_ADDR, HWIO_GCC_TURING_Q6_QTB0_CFG_SREGR_RMSK) +#define HWIO_GCC_TURING_Q6_QTB0_CFG_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_TURING_Q6_QTB0_CFG_SREGR_ADDR, m) +#define HWIO_GCC_TURING_Q6_QTB0_CFG_SREGR_OUT(v) \ + out_dword(HWIO_GCC_TURING_Q6_QTB0_CFG_SREGR_ADDR,v) +#define HWIO_GCC_TURING_Q6_QTB0_CFG_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TURING_Q6_QTB0_CFG_SREGR_ADDR,m,v,HWIO_GCC_TURING_Q6_QTB0_CFG_SREGR_IN) +#define HWIO_GCC_TURING_Q6_QTB0_CFG_SREGR_MEM_CORE_OFF_TIMER_BMSK 0xfc000000 +#define HWIO_GCC_TURING_Q6_QTB0_CFG_SREGR_MEM_CORE_OFF_TIMER_SHFT 0x1a +#define HWIO_GCC_TURING_Q6_QTB0_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_BMSK 0x2000000 +#define HWIO_GCC_TURING_Q6_QTB0_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_SHFT 0x19 +#define HWIO_GCC_TURING_Q6_QTB0_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_BMSK 0x1000000 +#define HWIO_GCC_TURING_Q6_QTB0_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_SHFT 0x18 +#define HWIO_GCC_TURING_Q6_QTB0_CFG_SREGR_MEM_PERIPH_ON_STATUS_BMSK 0x800000 +#define HWIO_GCC_TURING_Q6_QTB0_CFG_SREGR_MEM_PERIPH_ON_STATUS_SHFT 0x17 +#define HWIO_GCC_TURING_Q6_QTB0_CFG_SREGR_MEM_CORE_ON_STATUS_BMSK 0x400000 +#define HWIO_GCC_TURING_Q6_QTB0_CFG_SREGR_MEM_CORE_ON_STATUS_SHFT 0x16 +#define HWIO_GCC_TURING_Q6_QTB0_CFG_SREGR_MEM_CPH_TIMER_BMSK 0x3f0000 +#define HWIO_GCC_TURING_Q6_QTB0_CFG_SREGR_MEM_CPH_TIMER_SHFT 0x10 +#define HWIO_GCC_TURING_Q6_QTB0_CFG_SREGR_SLEEP_TIMER_BMSK 0xff00 +#define HWIO_GCC_TURING_Q6_QTB0_CFG_SREGR_SLEEP_TIMER_SHFT 0x8 +#define HWIO_GCC_TURING_Q6_QTB0_CFG_SREGR_WAKEUP_TIMER_BMSK 0xff +#define HWIO_GCC_TURING_Q6_QTB0_CFG_SREGR_WAKEUP_TIMER_SHFT 0x0 + +#define HWIO_GCC_TURING_NSP_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008d020) +#define HWIO_GCC_TURING_NSP_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008d020) +#define HWIO_GCC_TURING_NSP_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008d020) +#define HWIO_GCC_TURING_NSP_AHB_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_TURING_NSP_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_TURING_NSP_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_TURING_NSP_AHB_CBCR_ADDR, HWIO_GCC_TURING_NSP_AHB_CBCR_RMSK) +#define HWIO_GCC_TURING_NSP_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_TURING_NSP_AHB_CBCR_ADDR, m) +#define HWIO_GCC_TURING_NSP_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_TURING_NSP_AHB_CBCR_ADDR,v) +#define HWIO_GCC_TURING_NSP_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TURING_NSP_AHB_CBCR_ADDR,m,v,HWIO_GCC_TURING_NSP_AHB_CBCR_IN) +#define HWIO_GCC_TURING_NSP_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TURING_NSP_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TURING_NSP_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_TURING_NSP_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_TURING_NSP_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_TURING_NSP_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_TURING_NSP_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_TURING_NSP_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_TURING_NSP_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_TURING_NSP_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_TURING_NSP_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_TURING_NSP_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_TURING_NSP_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_TURING_NSP_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_TURING_NSP_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_TURING_NSP_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_TURING_NSP_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_TURING_NSP_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_TURING_NSP_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_NSP_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_NSP_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_TURING_NSP_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_TURING_NSP_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_NSP_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_NSP_QOSGEN_EXTREF_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008d024) +#define HWIO_GCC_NSP_QOSGEN_EXTREF_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008d024) +#define HWIO_GCC_NSP_QOSGEN_EXTREF_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008d024) +#define HWIO_GCC_NSP_QOSGEN_EXTREF_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_NSP_QOSGEN_EXTREF_CBCR_ATTR 0x3 +#define HWIO_GCC_NSP_QOSGEN_EXTREF_CBCR_IN \ + in_dword_masked(HWIO_GCC_NSP_QOSGEN_EXTREF_CBCR_ADDR, HWIO_GCC_NSP_QOSGEN_EXTREF_CBCR_RMSK) +#define HWIO_GCC_NSP_QOSGEN_EXTREF_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_NSP_QOSGEN_EXTREF_CBCR_ADDR, m) +#define HWIO_GCC_NSP_QOSGEN_EXTREF_CBCR_OUT(v) \ + out_dword(HWIO_GCC_NSP_QOSGEN_EXTREF_CBCR_ADDR,v) +#define HWIO_GCC_NSP_QOSGEN_EXTREF_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_NSP_QOSGEN_EXTREF_CBCR_ADDR,m,v,HWIO_GCC_NSP_QOSGEN_EXTREF_CBCR_IN) +#define HWIO_GCC_NSP_QOSGEN_EXTREF_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_NSP_QOSGEN_EXTREF_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_NSP_QOSGEN_EXTREF_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_NSP_QOSGEN_EXTREF_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_NSP_QOSGEN_EXTREF_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_NSP_QOSGEN_EXTREF_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_NSP_QOSGEN_EXTREF_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_NSP_QOSGEN_EXTREF_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_NSP_QOSGEN_EXTREF_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_NSP_QOSGEN_EXTREF_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_NSP_QOSGEN_EXTREF_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_NSP_QOSGEN_EXTREF_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_NSP_QOSGEN_EXTREF_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_NSP_QOSGEN_EXTREF_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_NSP_QOSGEN_EXTREF_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_NSP_QOSGEN_EXTREF_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_NSP_QDSS_TSCTR_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008d028) +#define HWIO_GCC_NSP_QDSS_TSCTR_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008d028) +#define HWIO_GCC_NSP_QDSS_TSCTR_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008d028) +#define HWIO_GCC_NSP_QDSS_TSCTR_CBCR_RMSK 0x81c0000f +#define HWIO_GCC_NSP_QDSS_TSCTR_CBCR_ATTR 0x3 +#define HWIO_GCC_NSP_QDSS_TSCTR_CBCR_IN \ + in_dword_masked(HWIO_GCC_NSP_QDSS_TSCTR_CBCR_ADDR, HWIO_GCC_NSP_QDSS_TSCTR_CBCR_RMSK) +#define HWIO_GCC_NSP_QDSS_TSCTR_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_NSP_QDSS_TSCTR_CBCR_ADDR, m) +#define HWIO_GCC_NSP_QDSS_TSCTR_CBCR_OUT(v) \ + out_dword(HWIO_GCC_NSP_QDSS_TSCTR_CBCR_ADDR,v) +#define HWIO_GCC_NSP_QDSS_TSCTR_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_NSP_QDSS_TSCTR_CBCR_ADDR,m,v,HWIO_GCC_NSP_QDSS_TSCTR_CBCR_IN) +#define HWIO_GCC_NSP_QDSS_TSCTR_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_NSP_QDSS_TSCTR_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_NSP_QDSS_TSCTR_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_NSP_QDSS_TSCTR_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_NSP_QDSS_TSCTR_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_NSP_QDSS_TSCTR_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_NSP_QDSS_TSCTR_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_NSP_QDSS_TSCTR_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_NSP_QDSS_TSCTR_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_NSP_QDSS_TSCTR_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_NSP_QDSS_TSCTR_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_NSP_QDSS_TSCTR_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_NSP_QDSS_TSCTR_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_NSP_QDSS_TSCTR_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_NSP_QDSS_TSCTR_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_NSP_QDSS_TSCTR_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_NSP_QDSS_TSCTR_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_NSP_QDSS_TSCTR_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_NSP_QDSS_TSCTR_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_NSP_QDSS_TSCTR_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_NSP_QDSS_TSCTR_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_NSP_QDSS_TSCTR_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TURING_QTB_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008d02c) +#define HWIO_GCC_TURING_QTB_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008d02c) +#define HWIO_GCC_TURING_QTB_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008d02c) +#define HWIO_GCC_TURING_QTB_AT_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_TURING_QTB_AT_CBCR_ATTR 0x3 +#define HWIO_GCC_TURING_QTB_AT_CBCR_IN \ + in_dword_masked(HWIO_GCC_TURING_QTB_AT_CBCR_ADDR, HWIO_GCC_TURING_QTB_AT_CBCR_RMSK) +#define HWIO_GCC_TURING_QTB_AT_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_TURING_QTB_AT_CBCR_ADDR, m) +#define HWIO_GCC_TURING_QTB_AT_CBCR_OUT(v) \ + out_dword(HWIO_GCC_TURING_QTB_AT_CBCR_ADDR,v) +#define HWIO_GCC_TURING_QTB_AT_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TURING_QTB_AT_CBCR_ADDR,m,v,HWIO_GCC_TURING_QTB_AT_CBCR_IN) +#define HWIO_GCC_TURING_QTB_AT_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TURING_QTB_AT_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TURING_QTB_AT_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_TURING_QTB_AT_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_TURING_QTB_AT_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_TURING_QTB_AT_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_TURING_QTB_AT_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_TURING_QTB_AT_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_TURING_QTB_AT_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_TURING_QTB_AT_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_TURING_QTB_AT_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_TURING_QTB_AT_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_TURING_QTB_AT_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_TURING_QTB_AT_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_TURING_QTB_AT_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_TURING_QTB_AT_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_TURING_QTB_AT_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_TURING_QTB_AT_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_TURING_QTB_AT_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_QTB_AT_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_QTB_AT_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_TURING_QTB_AT_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_TURING_QTB_AT_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_QTB_AT_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TURING_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008d030) +#define HWIO_GCC_TURING_XO_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008d030) +#define HWIO_GCC_TURING_XO_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008d030) +#define HWIO_GCC_TURING_XO_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_TURING_XO_CBCR_ATTR 0x3 +#define HWIO_GCC_TURING_XO_CBCR_IN \ + in_dword_masked(HWIO_GCC_TURING_XO_CBCR_ADDR, HWIO_GCC_TURING_XO_CBCR_RMSK) +#define HWIO_GCC_TURING_XO_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_TURING_XO_CBCR_ADDR, m) +#define HWIO_GCC_TURING_XO_CBCR_OUT(v) \ + out_dword(HWIO_GCC_TURING_XO_CBCR_ADDR,v) +#define HWIO_GCC_TURING_XO_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TURING_XO_CBCR_ADDR,m,v,HWIO_GCC_TURING_XO_CBCR_IN) +#define HWIO_GCC_TURING_XO_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TURING_XO_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TURING_XO_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_TURING_XO_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_TURING_XO_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_TURING_XO_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_TURING_XO_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_TURING_XO_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_TURING_XO_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_TURING_XO_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_TURING_XO_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_TURING_XO_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_TURING_XO_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_TURING_XO_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_TURING_XO_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_XO_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TURING_PWRCTL_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008d034) +#define HWIO_GCC_TURING_PWRCTL_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008d034) +#define HWIO_GCC_TURING_PWRCTL_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008d034) +#define HWIO_GCC_TURING_PWRCTL_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_TURING_PWRCTL_CBCR_ATTR 0x3 +#define HWIO_GCC_TURING_PWRCTL_CBCR_IN \ + in_dword_masked(HWIO_GCC_TURING_PWRCTL_CBCR_ADDR, HWIO_GCC_TURING_PWRCTL_CBCR_RMSK) +#define HWIO_GCC_TURING_PWRCTL_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_TURING_PWRCTL_CBCR_ADDR, m) +#define HWIO_GCC_TURING_PWRCTL_CBCR_OUT(v) \ + out_dword(HWIO_GCC_TURING_PWRCTL_CBCR_ADDR,v) +#define HWIO_GCC_TURING_PWRCTL_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TURING_PWRCTL_CBCR_ADDR,m,v,HWIO_GCC_TURING_PWRCTL_CBCR_IN) +#define HWIO_GCC_TURING_PWRCTL_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TURING_PWRCTL_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TURING_PWRCTL_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_TURING_PWRCTL_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_TURING_PWRCTL_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_TURING_PWRCTL_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_TURING_PWRCTL_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_TURING_PWRCTL_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_TURING_PWRCTL_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_TURING_PWRCTL_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_TURING_PWRCTL_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_TURING_PWRCTL_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_TURING_PWRCTL_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_TURING_PWRCTL_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_TURING_PWRCTL_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_TURING_PWRCTL_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_TURING_PWRCTL_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_TURING_PWRCTL_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_TURING_PWRCTL_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_PWRCTL_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_PWRCTL_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_TURING_PWRCTL_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_TURING_PWRCTL_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_PWRCTL_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TURING_MMNOC_SF_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00035000) +#define HWIO_GCC_TURING_MMNOC_SF_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00035000) +#define HWIO_GCC_TURING_MMNOC_SF_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00035000) +#define HWIO_GCC_TURING_MMNOC_SF_CBCR_RMSK 0x81f0000f +#define HWIO_GCC_TURING_MMNOC_SF_CBCR_ATTR 0x3 +#define HWIO_GCC_TURING_MMNOC_SF_CBCR_IN \ + in_dword_masked(HWIO_GCC_TURING_MMNOC_SF_CBCR_ADDR, HWIO_GCC_TURING_MMNOC_SF_CBCR_RMSK) +#define HWIO_GCC_TURING_MMNOC_SF_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_TURING_MMNOC_SF_CBCR_ADDR, m) +#define HWIO_GCC_TURING_MMNOC_SF_CBCR_OUT(v) \ + out_dword(HWIO_GCC_TURING_MMNOC_SF_CBCR_ADDR,v) +#define HWIO_GCC_TURING_MMNOC_SF_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TURING_MMNOC_SF_CBCR_ADDR,m,v,HWIO_GCC_TURING_MMNOC_SF_CBCR_IN) +#define HWIO_GCC_TURING_MMNOC_SF_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TURING_MMNOC_SF_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TURING_MMNOC_SF_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_TURING_MMNOC_SF_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_TURING_MMNOC_SF_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_TURING_MMNOC_SF_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_TURING_MMNOC_SF_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_TURING_MMNOC_SF_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_TURING_MMNOC_SF_CBCR_IGNORE_PMU_CLK_DIS_BMSK 0x200000 +#define HWIO_GCC_TURING_MMNOC_SF_CBCR_IGNORE_PMU_CLK_DIS_SHFT 0x15 +#define HWIO_GCC_TURING_MMNOC_SF_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_TURING_MMNOC_SF_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_TURING_MMNOC_SF_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_TURING_MMNOC_SF_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_TURING_MMNOC_SF_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_TURING_MMNOC_SF_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_TURING_MMNOC_SF_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_TURING_MMNOC_SF_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_TURING_MMNOC_SF_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_TURING_MMNOC_SF_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_TURING_MMNOC_SF_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_MMNOC_SF_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_MMNOC_SF_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_TURING_MMNOC_SF_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_TURING_MMNOC_SF_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_MMNOC_SF_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TURING_Q6_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00035004) +#define HWIO_GCC_TURING_Q6_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00035004) +#define HWIO_GCC_TURING_Q6_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00035004) +#define HWIO_GCC_TURING_Q6_AXI_CBCR_RMSK 0x81f0000f +#define HWIO_GCC_TURING_Q6_AXI_CBCR_ATTR 0x3 +#define HWIO_GCC_TURING_Q6_AXI_CBCR_IN \ + in_dword_masked(HWIO_GCC_TURING_Q6_AXI_CBCR_ADDR, HWIO_GCC_TURING_Q6_AXI_CBCR_RMSK) +#define HWIO_GCC_TURING_Q6_AXI_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_TURING_Q6_AXI_CBCR_ADDR, m) +#define HWIO_GCC_TURING_Q6_AXI_CBCR_OUT(v) \ + out_dword(HWIO_GCC_TURING_Q6_AXI_CBCR_ADDR,v) +#define HWIO_GCC_TURING_Q6_AXI_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TURING_Q6_AXI_CBCR_ADDR,m,v,HWIO_GCC_TURING_Q6_AXI_CBCR_IN) +#define HWIO_GCC_TURING_Q6_AXI_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TURING_Q6_AXI_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TURING_Q6_AXI_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_TURING_Q6_AXI_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_TURING_Q6_AXI_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_TURING_Q6_AXI_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_TURING_Q6_AXI_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_TURING_Q6_AXI_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_TURING_Q6_AXI_CBCR_IGNORE_PMU_CLK_DIS_BMSK 0x200000 +#define HWIO_GCC_TURING_Q6_AXI_CBCR_IGNORE_PMU_CLK_DIS_SHFT 0x15 +#define HWIO_GCC_TURING_Q6_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_TURING_Q6_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_TURING_Q6_AXI_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_TURING_Q6_AXI_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_TURING_Q6_AXI_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_TURING_Q6_AXI_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_TURING_Q6_AXI_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_TURING_Q6_AXI_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_TURING_Q6_AXI_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_TURING_Q6_AXI_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_TURING_Q6_AXI_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_Q6_AXI_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_Q6_AXI_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_TURING_Q6_AXI_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_TURING_Q6_AXI_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_Q6_AXI_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TURING_CFG_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00035008) +#define HWIO_GCC_TURING_CFG_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00035008) +#define HWIO_GCC_TURING_CFG_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00035008) +#define HWIO_GCC_TURING_CFG_AHB_CBCR_RMSK 0x81d00005 +#define HWIO_GCC_TURING_CFG_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_TURING_CFG_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_TURING_CFG_AHB_CBCR_ADDR, HWIO_GCC_TURING_CFG_AHB_CBCR_RMSK) +#define HWIO_GCC_TURING_CFG_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_TURING_CFG_AHB_CBCR_ADDR, m) +#define HWIO_GCC_TURING_CFG_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_TURING_CFG_AHB_CBCR_ADDR,v) +#define HWIO_GCC_TURING_CFG_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TURING_CFG_AHB_CBCR_ADDR,m,v,HWIO_GCC_TURING_CFG_AHB_CBCR_IN) +#define HWIO_GCC_TURING_CFG_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TURING_CFG_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TURING_CFG_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_TURING_CFG_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_TURING_CFG_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_TURING_CFG_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_TURING_CFG_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_TURING_CFG_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_TURING_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_TURING_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_TURING_CFG_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_TURING_CFG_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_TURING_CFG_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_TURING_CFG_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_TURING_CFG_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_TURING_CFG_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_TURING_CFG_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_CFG_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TURING_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003500c) +#define HWIO_GCC_TURING_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003500c) +#define HWIO_GCC_TURING_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003500c) +#define HWIO_GCC_TURING_AT_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_TURING_AT_CBCR_ATTR 0x3 +#define HWIO_GCC_TURING_AT_CBCR_IN \ + in_dword_masked(HWIO_GCC_TURING_AT_CBCR_ADDR, HWIO_GCC_TURING_AT_CBCR_RMSK) +#define HWIO_GCC_TURING_AT_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_TURING_AT_CBCR_ADDR, m) +#define HWIO_GCC_TURING_AT_CBCR_OUT(v) \ + out_dword(HWIO_GCC_TURING_AT_CBCR_ADDR,v) +#define HWIO_GCC_TURING_AT_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TURING_AT_CBCR_ADDR,m,v,HWIO_GCC_TURING_AT_CBCR_IN) +#define HWIO_GCC_TURING_AT_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TURING_AT_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TURING_AT_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_TURING_AT_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_TURING_AT_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_TURING_AT_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_TURING_AT_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_TURING_AT_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_TURING_AT_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_TURING_AT_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_TURING_AT_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_TURING_AT_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_TURING_AT_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_TURING_AT_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_TURING_AT_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_TURING_AT_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_TURING_AT_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_TURING_AT_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_TURING_AT_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_AT_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_AT_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_TURING_AT_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_TURING_AT_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_AT_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QMIP_TURING_NSP_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00035010) +#define HWIO_GCC_QMIP_TURING_NSP_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00035010) +#define HWIO_GCC_QMIP_TURING_NSP_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00035010) +#define HWIO_GCC_QMIP_TURING_NSP_AHB_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_QMIP_TURING_NSP_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_QMIP_TURING_NSP_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_QMIP_TURING_NSP_AHB_CBCR_ADDR, HWIO_GCC_QMIP_TURING_NSP_AHB_CBCR_RMSK) +#define HWIO_GCC_QMIP_TURING_NSP_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QMIP_TURING_NSP_AHB_CBCR_ADDR, m) +#define HWIO_GCC_QMIP_TURING_NSP_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QMIP_TURING_NSP_AHB_CBCR_ADDR,v) +#define HWIO_GCC_QMIP_TURING_NSP_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QMIP_TURING_NSP_AHB_CBCR_ADDR,m,v,HWIO_GCC_QMIP_TURING_NSP_AHB_CBCR_IN) +#define HWIO_GCC_QMIP_TURING_NSP_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QMIP_TURING_NSP_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QMIP_TURING_NSP_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QMIP_TURING_NSP_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QMIP_TURING_NSP_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QMIP_TURING_NSP_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QMIP_TURING_NSP_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QMIP_TURING_NSP_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QMIP_TURING_NSP_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_QMIP_TURING_NSP_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_QMIP_TURING_NSP_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_QMIP_TURING_NSP_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_QMIP_TURING_NSP_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QMIP_TURING_NSP_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QMIP_TURING_NSP_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QMIP_TURING_NSP_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_QMIP_TURING_NSP_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_QMIP_TURING_NSP_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_QMIP_TURING_NSP_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QMIP_TURING_NSP_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QMIP_TURING_NSP_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_QMIP_TURING_NSP_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_QMIP_TURING_NSP_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QMIP_TURING_NSP_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TURING_TRIG_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00035014) +#define HWIO_GCC_TURING_TRIG_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00035014) +#define HWIO_GCC_TURING_TRIG_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00035014) +#define HWIO_GCC_TURING_TRIG_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_TURING_TRIG_CBCR_ATTR 0x3 +#define HWIO_GCC_TURING_TRIG_CBCR_IN \ + in_dword_masked(HWIO_GCC_TURING_TRIG_CBCR_ADDR, HWIO_GCC_TURING_TRIG_CBCR_RMSK) +#define HWIO_GCC_TURING_TRIG_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_TURING_TRIG_CBCR_ADDR, m) +#define HWIO_GCC_TURING_TRIG_CBCR_OUT(v) \ + out_dword(HWIO_GCC_TURING_TRIG_CBCR_ADDR,v) +#define HWIO_GCC_TURING_TRIG_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TURING_TRIG_CBCR_ADDR,m,v,HWIO_GCC_TURING_TRIG_CBCR_IN) +#define HWIO_GCC_TURING_TRIG_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TURING_TRIG_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TURING_TRIG_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_TURING_TRIG_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_TURING_TRIG_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_TURING_TRIG_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_TURING_TRIG_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_TURING_TRIG_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_TURING_TRIG_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_TURING_TRIG_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_TURING_TRIG_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_TURING_TRIG_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_TURING_TRIG_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_TURING_TRIG_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_TURING_TRIG_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_TURING_TRIG_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_TURING_TRIG_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_TURING_TRIG_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_TURING_TRIG_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_TRIG_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_TRIG_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_TURING_TRIG_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_TURING_TRIG_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_TRIG_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003502c) +#define HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003502c) +#define HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003502c) +#define HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_RMSK 0xffff +#define HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_ADDR, HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_RMSK) +#define HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_IN) +#define HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_RCG_SW_CTRL_BMSK 0x8000 +#define HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_RCG_SW_CTRL_SHFT 0xf +#define HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_SW_PERF_STATE_BMSK 0x7800 +#define HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_SW_PERF_STATE_SHFT 0xb +#define HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_SW_OVERRIDE_BMSK 0x400 +#define HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_SW_OVERRIDE_SHFT 0xa +#define HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK 0x200 +#define HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT 0x9 +#define HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_DFS_FSM_STATE_BMSK 0x1c0 +#define HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_DFS_FSM_STATE_SHFT 0x6 +#define HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_HW_CLK_CONTROL_BMSK 0x20 +#define HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_HW_CLK_CONTROL_SHFT 0x5 +#define HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_CURR_PERF_STATE_BMSK 0x1e +#define HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_CURR_PERF_STATE_SHFT 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_DFS_EN_BMSK 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_DFS_EN_SHFT 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_DFS_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_DFS_EN_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00035034) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00035034) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00035034) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_ADDR, HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_RMSK) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_IN) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00035038) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00035038) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00035038) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_ADDR, HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_RMSK) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_IN) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003503c) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003503c) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003503c) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_ADDR, HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_RMSK) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_IN) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00035040) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00035040) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00035040) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_ADDR, HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_RMSK) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_IN) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00035044) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00035044) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00035044) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_ADDR, HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_RMSK) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_IN) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00035048) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00035048) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00035048) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_ADDR, HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_RMSK) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_IN) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003504c) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003504c) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003504c) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_ADDR, HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_RMSK) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_IN) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00035050) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00035050) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00035050) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_ADDR, HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_RMSK) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_IN) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00035054) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00035054) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00035054) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_ADDR, HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_RMSK) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_IN) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00035058) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00035058) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00035058) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_ADDR, HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_RMSK) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_IN) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003505c) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003505c) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003505c) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_ADDR, HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_RMSK) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_IN) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00035060) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00035060) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00035060) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_ADDR, HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_RMSK) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_IN) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00035064) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00035064) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00035064) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_ADDR, HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_RMSK) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_IN) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00035068) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00035068) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00035068) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_ADDR, HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_RMSK) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_IN) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003506c) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003506c) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003506c) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_ADDR, HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_RMSK) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_IN) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00035070) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00035070) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00035070) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_ADDR, HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_RMSK) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_IN) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_TURING_Q6_AXI_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00035018) +#define HWIO_GCC_TURING_Q6_AXI_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00035018) +#define HWIO_GCC_TURING_Q6_AXI_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00035018) +#define HWIO_GCC_TURING_Q6_AXI_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_TURING_Q6_AXI_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_TURING_Q6_AXI_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_TURING_Q6_AXI_CMD_RCGR_ADDR, HWIO_GCC_TURING_Q6_AXI_CMD_RCGR_RMSK) +#define HWIO_GCC_TURING_Q6_AXI_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_TURING_Q6_AXI_CMD_RCGR_ADDR, m) +#define HWIO_GCC_TURING_Q6_AXI_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_TURING_Q6_AXI_CMD_RCGR_ADDR,v) +#define HWIO_GCC_TURING_Q6_AXI_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TURING_Q6_AXI_CMD_RCGR_ADDR,m,v,HWIO_GCC_TURING_Q6_AXI_CMD_RCGR_IN) +#define HWIO_GCC_TURING_Q6_AXI_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_TURING_Q6_AXI_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_TURING_Q6_AXI_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_TURING_Q6_AXI_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_TURING_Q6_AXI_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_TURING_Q6_AXI_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_TURING_Q6_AXI_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_Q6_AXI_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_Q6_AXI_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_TURING_Q6_AXI_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_TURING_Q6_AXI_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_Q6_AXI_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003501c) +#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003501c) +#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003501c) +#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_ADDR, HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_RMSK) +#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_ADDR, m) +#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_ADDR,v) +#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_ADDR,m,v,HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_IN) +#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_TURING_Q6_AXI_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00035144) +#define HWIO_GCC_TURING_Q6_AXI_DCD_CDIV_DCDR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00035144) +#define HWIO_GCC_TURING_Q6_AXI_DCD_CDIV_DCDR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00035144) +#define HWIO_GCC_TURING_Q6_AXI_DCD_CDIV_DCDR_RMSK 0x1 +#define HWIO_GCC_TURING_Q6_AXI_DCD_CDIV_DCDR_ATTR 0x3 +#define HWIO_GCC_TURING_Q6_AXI_DCD_CDIV_DCDR_IN \ + in_dword_masked(HWIO_GCC_TURING_Q6_AXI_DCD_CDIV_DCDR_ADDR, HWIO_GCC_TURING_Q6_AXI_DCD_CDIV_DCDR_RMSK) +#define HWIO_GCC_TURING_Q6_AXI_DCD_CDIV_DCDR_INM(m) \ + in_dword_masked(HWIO_GCC_TURING_Q6_AXI_DCD_CDIV_DCDR_ADDR, m) +#define HWIO_GCC_TURING_Q6_AXI_DCD_CDIV_DCDR_OUT(v) \ + out_dword(HWIO_GCC_TURING_Q6_AXI_DCD_CDIV_DCDR_ADDR,v) +#define HWIO_GCC_TURING_Q6_AXI_DCD_CDIV_DCDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TURING_Q6_AXI_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_TURING_Q6_AXI_DCD_CDIV_DCDR_IN) +#define HWIO_GCC_TURING_Q6_AXI_DCD_CDIV_DCDR_DCD_ENABLE_BMSK 0x1 +#define HWIO_GCC_TURING_Q6_AXI_DCD_CDIV_DCDR_DCD_ENABLE_SHFT 0x0 +#define HWIO_GCC_TURING_Q6_AXI_DCD_CDIV_DCDR_DCD_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_Q6_AXI_DCD_CDIV_DCDR_DCD_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CPUSS_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038000) +#define HWIO_GCC_CPUSS_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038000) +#define HWIO_GCC_CPUSS_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038000) +#define HWIO_GCC_CPUSS_AHB_CBCR_RMSK 0x81c0000e +#define HWIO_GCC_CPUSS_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_CPUSS_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_CPUSS_AHB_CBCR_ADDR, HWIO_GCC_CPUSS_AHB_CBCR_RMSK) +#define HWIO_GCC_CPUSS_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_CPUSS_AHB_CBCR_ADDR, m) +#define HWIO_GCC_CPUSS_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_CPUSS_AHB_CBCR_ADDR,v) +#define HWIO_GCC_CPUSS_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CPUSS_AHB_CBCR_ADDR,m,v,HWIO_GCC_CPUSS_AHB_CBCR_IN) +#define HWIO_GCC_CPUSS_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_CPUSS_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_CPUSS_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_CPUSS_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_CPUSS_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_CPUSS_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_CPUSS_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_CPUSS_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_CPUSS_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_CPUSS_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_CPUSS_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_CPUSS_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_CPUSS_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_CPUSS_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_CPUSS_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_CPUSS_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_CPUSS_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_CPUSS_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CPUSS_TRIG_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038004) +#define HWIO_GCC_CPUSS_TRIG_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038004) +#define HWIO_GCC_CPUSS_TRIG_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038004) +#define HWIO_GCC_CPUSS_TRIG_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_CPUSS_TRIG_CBCR_ATTR 0x3 +#define HWIO_GCC_CPUSS_TRIG_CBCR_IN \ + in_dword_masked(HWIO_GCC_CPUSS_TRIG_CBCR_ADDR, HWIO_GCC_CPUSS_TRIG_CBCR_RMSK) +#define HWIO_GCC_CPUSS_TRIG_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_CPUSS_TRIG_CBCR_ADDR, m) +#define HWIO_GCC_CPUSS_TRIG_CBCR_OUT(v) \ + out_dword(HWIO_GCC_CPUSS_TRIG_CBCR_ADDR,v) +#define HWIO_GCC_CPUSS_TRIG_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CPUSS_TRIG_CBCR_ADDR,m,v,HWIO_GCC_CPUSS_TRIG_CBCR_IN) +#define HWIO_GCC_CPUSS_TRIG_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_CPUSS_TRIG_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_CPUSS_TRIG_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_CPUSS_TRIG_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_CPUSS_TRIG_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_CPUSS_TRIG_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_CPUSS_TRIG_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_CPUSS_TRIG_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_CPUSS_TRIG_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_CPUSS_TRIG_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_CPUSS_TRIG_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_CPUSS_TRIG_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_CPUSS_TRIG_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_CPUSS_TRIG_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_CPUSS_TRIG_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_CPUSS_TRIG_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_CPUSS_TRIG_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_CPUSS_TRIG_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_CPUSS_TRIG_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_CPUSS_TRIG_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_CPUSS_TRIG_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_CPUSS_TRIG_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_CPUSS_TRIG_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CPUSS_TRIG_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CPUSS_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038008) +#define HWIO_GCC_CPUSS_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038008) +#define HWIO_GCC_CPUSS_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038008) +#define HWIO_GCC_CPUSS_AT_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_CPUSS_AT_CBCR_ATTR 0x3 +#define HWIO_GCC_CPUSS_AT_CBCR_IN \ + in_dword_masked(HWIO_GCC_CPUSS_AT_CBCR_ADDR, HWIO_GCC_CPUSS_AT_CBCR_RMSK) +#define HWIO_GCC_CPUSS_AT_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_CPUSS_AT_CBCR_ADDR, m) +#define HWIO_GCC_CPUSS_AT_CBCR_OUT(v) \ + out_dword(HWIO_GCC_CPUSS_AT_CBCR_ADDR,v) +#define HWIO_GCC_CPUSS_AT_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CPUSS_AT_CBCR_ADDR,m,v,HWIO_GCC_CPUSS_AT_CBCR_IN) +#define HWIO_GCC_CPUSS_AT_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_CPUSS_AT_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_CPUSS_AT_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_CPUSS_AT_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_CPUSS_AT_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_CPUSS_AT_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_CPUSS_AT_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_CPUSS_AT_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_CPUSS_AT_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_CPUSS_AT_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_CPUSS_AT_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_CPUSS_AT_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_CPUSS_AT_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_CPUSS_AT_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_CPUSS_AT_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_CPUSS_AT_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_CPUSS_AT_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_CPUSS_AT_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_CPUSS_AT_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_CPUSS_AT_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_CPUSS_AT_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_CPUSS_AT_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_CPUSS_AT_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CPUSS_AT_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CPUSS_CONFIG_NOC_SF_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003800c) +#define HWIO_GCC_CPUSS_CONFIG_NOC_SF_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003800c) +#define HWIO_GCC_CPUSS_CONFIG_NOC_SF_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003800c) +#define HWIO_GCC_CPUSS_CONFIG_NOC_SF_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_CPUSS_CONFIG_NOC_SF_CBCR_ATTR 0x3 +#define HWIO_GCC_CPUSS_CONFIG_NOC_SF_CBCR_IN \ + in_dword_masked(HWIO_GCC_CPUSS_CONFIG_NOC_SF_CBCR_ADDR, HWIO_GCC_CPUSS_CONFIG_NOC_SF_CBCR_RMSK) +#define HWIO_GCC_CPUSS_CONFIG_NOC_SF_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_CPUSS_CONFIG_NOC_SF_CBCR_ADDR, m) +#define HWIO_GCC_CPUSS_CONFIG_NOC_SF_CBCR_OUT(v) \ + out_dword(HWIO_GCC_CPUSS_CONFIG_NOC_SF_CBCR_ADDR,v) +#define HWIO_GCC_CPUSS_CONFIG_NOC_SF_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CPUSS_CONFIG_NOC_SF_CBCR_ADDR,m,v,HWIO_GCC_CPUSS_CONFIG_NOC_SF_CBCR_IN) +#define HWIO_GCC_CPUSS_CONFIG_NOC_SF_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_CPUSS_CONFIG_NOC_SF_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_CPUSS_CONFIG_NOC_SF_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_CPUSS_CONFIG_NOC_SF_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_CPUSS_CONFIG_NOC_SF_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_CPUSS_CONFIG_NOC_SF_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_CPUSS_CONFIG_NOC_SF_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_CPUSS_CONFIG_NOC_SF_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_CPUSS_CONFIG_NOC_SF_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_CPUSS_CONFIG_NOC_SF_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_CPUSS_CONFIG_NOC_SF_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_CPUSS_CONFIG_NOC_SF_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_CPUSS_CONFIG_NOC_SF_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_CPUSS_CONFIG_NOC_SF_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_CPUSS_CONFIG_NOC_SF_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_CPUSS_CONFIG_NOC_SF_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_CPUSS_CONFIG_NOC_SF_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_CPUSS_CONFIG_NOC_SF_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_CPUSS_CONFIG_NOC_SF_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_CPUSS_CONFIG_NOC_SF_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_CPUSS_CONFIG_NOC_SF_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_CPUSS_CONFIG_NOC_SF_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_CPUSS_CONFIG_NOC_SF_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CPUSS_CONFIG_NOC_SF_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CPUSS_AHB_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038010) +#define HWIO_GCC_CPUSS_AHB_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038010) +#define HWIO_GCC_CPUSS_AHB_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038010) +#define HWIO_GCC_CPUSS_AHB_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_CPUSS_AHB_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_CPUSS_AHB_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_CPUSS_AHB_CMD_RCGR_ADDR, HWIO_GCC_CPUSS_AHB_CMD_RCGR_RMSK) +#define HWIO_GCC_CPUSS_AHB_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_CPUSS_AHB_CMD_RCGR_ADDR, m) +#define HWIO_GCC_CPUSS_AHB_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_CPUSS_AHB_CMD_RCGR_ADDR,v) +#define HWIO_GCC_CPUSS_AHB_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CPUSS_AHB_CMD_RCGR_ADDR,m,v,HWIO_GCC_CPUSS_AHB_CMD_RCGR_IN) +#define HWIO_GCC_CPUSS_AHB_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_CPUSS_AHB_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_CPUSS_AHB_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_CPUSS_AHB_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_CPUSS_AHB_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_CPUSS_AHB_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_CPUSS_AHB_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_CPUSS_AHB_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_CPUSS_AHB_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_CPUSS_AHB_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_CPUSS_AHB_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CPUSS_AHB_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038014) +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038014) +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038014) +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_CPUSS_AHB_CFG_RCGR_ADDR, HWIO_GCC_CPUSS_AHB_CFG_RCGR_RMSK) +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_CPUSS_AHB_CFG_RCGR_ADDR, m) +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_CPUSS_AHB_CFG_RCGR_ADDR,v) +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CPUSS_AHB_CFG_RCGR_ADDR,m,v,HWIO_GCC_CPUSS_AHB_CFG_RCGR_IN) +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_CPUSS_AHB_POSTDIV_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038028) +#define HWIO_GCC_CPUSS_AHB_POSTDIV_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038028) +#define HWIO_GCC_CPUSS_AHB_POSTDIV_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038028) +#define HWIO_GCC_CPUSS_AHB_POSTDIV_CDIVR_RMSK 0xf +#define HWIO_GCC_CPUSS_AHB_POSTDIV_CDIVR_ATTR 0x3 +#define HWIO_GCC_CPUSS_AHB_POSTDIV_CDIVR_IN \ + in_dword_masked(HWIO_GCC_CPUSS_AHB_POSTDIV_CDIVR_ADDR, HWIO_GCC_CPUSS_AHB_POSTDIV_CDIVR_RMSK) +#define HWIO_GCC_CPUSS_AHB_POSTDIV_CDIVR_INM(m) \ + in_dword_masked(HWIO_GCC_CPUSS_AHB_POSTDIV_CDIVR_ADDR, m) +#define HWIO_GCC_CPUSS_AHB_POSTDIV_CDIVR_OUT(v) \ + out_dword(HWIO_GCC_CPUSS_AHB_POSTDIV_CDIVR_ADDR,v) +#define HWIO_GCC_CPUSS_AHB_POSTDIV_CDIVR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CPUSS_AHB_POSTDIV_CDIVR_ADDR,m,v,HWIO_GCC_CPUSS_AHB_POSTDIV_CDIVR_IN) +#define HWIO_GCC_CPUSS_AHB_POSTDIV_CDIVR_CLK_DIV_BMSK 0xf +#define HWIO_GCC_CPUSS_AHB_POSTDIV_CDIVR_CLK_DIV_SHFT 0x0 + +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038048) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038048) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038048) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003804c) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003804c) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003804c) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038050) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038050) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038050) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038054) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038054) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038054) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038058) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038058) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038058) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003805c) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003805c) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003805c) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038060) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038060) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038060) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038064) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038064) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038064) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038068) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038068) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038068) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003806c) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003806c) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003806c) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038070) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038070) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038070) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038074) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038074) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038074) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038078) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038078) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038078) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003807c) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003807c) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003807c) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038080) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038080) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038080) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038084) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038084) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038084) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_CPUSS_AXI_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003802c) +#define HWIO_GCC_CPUSS_AXI_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003802c) +#define HWIO_GCC_CPUSS_AXI_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003802c) +#define HWIO_GCC_CPUSS_AXI_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_CPUSS_AXI_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_CPUSS_AXI_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_CPUSS_AXI_CMD_RCGR_ADDR, HWIO_GCC_CPUSS_AXI_CMD_RCGR_RMSK) +#define HWIO_GCC_CPUSS_AXI_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_CPUSS_AXI_CMD_RCGR_ADDR, m) +#define HWIO_GCC_CPUSS_AXI_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_CPUSS_AXI_CMD_RCGR_ADDR,v) +#define HWIO_GCC_CPUSS_AXI_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CPUSS_AXI_CMD_RCGR_ADDR,m,v,HWIO_GCC_CPUSS_AXI_CMD_RCGR_IN) +#define HWIO_GCC_CPUSS_AXI_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_CPUSS_AXI_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_CPUSS_AXI_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_CPUSS_AXI_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_CPUSS_AXI_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_CPUSS_AXI_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_CPUSS_AXI_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_CPUSS_AXI_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_CPUSS_AXI_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_CPUSS_AXI_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_CPUSS_AXI_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CPUSS_AXI_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038030) +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038030) +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038030) +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_CPUSS_AXI_CFG_RCGR_ADDR, HWIO_GCC_CPUSS_AXI_CFG_RCGR_RMSK) +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_CPUSS_AXI_CFG_RCGR_ADDR, m) +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_CPUSS_AXI_CFG_RCGR_ADDR,v) +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CPUSS_AXI_CFG_RCGR_ADDR,m,v,HWIO_GCC_CPUSS_AXI_CFG_RCGR_IN) +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038158) +#define HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038158) +#define HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038158) +#define HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_ADDR, HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_RMSK) +#define HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_ADDR, m) +#define HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_ADDR,v) +#define HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_ADDR,m,v,HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_IN) +#define HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003815c) +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003815c) +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003815c) +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_ADDR, HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_RMSK) +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_ADDR, m) +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_ADDR,v) +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_ADDR,m,v,HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_IN) +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_CPUSS_AXI_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038170) +#define HWIO_GCC_CPUSS_AXI_DCD_CDIV_DCDR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038170) +#define HWIO_GCC_CPUSS_AXI_DCD_CDIV_DCDR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038170) +#define HWIO_GCC_CPUSS_AXI_DCD_CDIV_DCDR_RMSK 0x1 +#define HWIO_GCC_CPUSS_AXI_DCD_CDIV_DCDR_ATTR 0x3 +#define HWIO_GCC_CPUSS_AXI_DCD_CDIV_DCDR_IN \ + in_dword_masked(HWIO_GCC_CPUSS_AXI_DCD_CDIV_DCDR_ADDR, HWIO_GCC_CPUSS_AXI_DCD_CDIV_DCDR_RMSK) +#define HWIO_GCC_CPUSS_AXI_DCD_CDIV_DCDR_INM(m) \ + in_dword_masked(HWIO_GCC_CPUSS_AXI_DCD_CDIV_DCDR_ADDR, m) +#define HWIO_GCC_CPUSS_AXI_DCD_CDIV_DCDR_OUT(v) \ + out_dword(HWIO_GCC_CPUSS_AXI_DCD_CDIV_DCDR_ADDR,v) +#define HWIO_GCC_CPUSS_AXI_DCD_CDIV_DCDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CPUSS_AXI_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_CPUSS_AXI_DCD_CDIV_DCDR_IN) +#define HWIO_GCC_CPUSS_AXI_DCD_CDIV_DCDR_DCD_ENABLE_BMSK 0x1 +#define HWIO_GCC_CPUSS_AXI_DCD_CDIV_DCDR_DCD_ENABLE_SHFT 0x0 +#define HWIO_GCC_CPUSS_AXI_DCD_CDIV_DCDR_DCD_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CPUSS_AXI_DCD_CDIV_DCDR_DCD_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038174) +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038174) +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038174) +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_RMSK 0x81c0000f +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_ATTR 0x3 +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_IN \ + in_dword_masked(HWIO_GCC_APSS_QDSS_TSCTR_CBCR_ADDR, HWIO_GCC_APSS_QDSS_TSCTR_CBCR_RMSK) +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_APSS_QDSS_TSCTR_CBCR_ADDR, m) +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_OUT(v) \ + out_dword(HWIO_GCC_APSS_QDSS_TSCTR_CBCR_ADDR,v) +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_APSS_QDSS_TSCTR_CBCR_ADDR,m,v,HWIO_GCC_APSS_QDSS_TSCTR_CBCR_IN) +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_APSS_QDSS_APB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038178) +#define HWIO_GCC_APSS_QDSS_APB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038178) +#define HWIO_GCC_APSS_QDSS_APB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038178) +#define HWIO_GCC_APSS_QDSS_APB_CBCR_RMSK 0x81c0000f +#define HWIO_GCC_APSS_QDSS_APB_CBCR_ATTR 0x3 +#define HWIO_GCC_APSS_QDSS_APB_CBCR_IN \ + in_dword_masked(HWIO_GCC_APSS_QDSS_APB_CBCR_ADDR, HWIO_GCC_APSS_QDSS_APB_CBCR_RMSK) +#define HWIO_GCC_APSS_QDSS_APB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_APSS_QDSS_APB_CBCR_ADDR, m) +#define HWIO_GCC_APSS_QDSS_APB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_APSS_QDSS_APB_CBCR_ADDR,v) +#define HWIO_GCC_APSS_QDSS_APB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_APSS_QDSS_APB_CBCR_ADDR,m,v,HWIO_GCC_APSS_QDSS_APB_CBCR_IN) +#define HWIO_GCC_APSS_QDSS_APB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_APSS_QDSS_APB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_APSS_QDSS_APB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_APSS_QDSS_APB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_APSS_QDSS_APB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_APSS_QDSS_APB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_APSS_QDSS_APB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_APSS_QDSS_APB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_APSS_QDSS_APB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_APSS_QDSS_APB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_APSS_QDSS_APB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_APSS_QDSS_APB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_APSS_QDSS_APB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_APSS_QDSS_APB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_APSS_QDSS_APB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_APSS_QDSS_APB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_APSS_QDSS_APB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_APSS_QDSS_APB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_APSS_QDSS_APB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_APSS_QDSS_APB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_APSS_QDSS_APB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APSS_QDSS_APB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00039000) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00039000) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00039000) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_BCR_RMSK 0x1 +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_BCR_ATTR 0x3 +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_BCR_IN \ + in_dword_masked(HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_BCR_ADDR, HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_BCR_RMSK) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_BCR_ADDR, m) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_BCR_OUT(v) \ + out_dword(HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_BCR_ADDR,v) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_BCR_ADDR,m,v,HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_BCR_IN) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00039004) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00039004) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00039004) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_ATTR 0x3 +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_IN \ + in_dword_masked(HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_ADDR, HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_RMSK) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_ADDR, m) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_OUT(v) \ + out_dword(HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_ADDR,v) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_ADDR,m,v,HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_IN) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00039008) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00039008) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00039008) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV_CDIVR_RMSK 0xf +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV_CDIVR_ATTR 0x3 +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV_CDIVR_IN \ + in_dword_masked(HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV_CDIVR_ADDR, HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV_CDIVR_RMSK) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV_CDIVR_INM(m) \ + in_dword_masked(HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV_CDIVR_ADDR, m) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV_CDIVR_OUT(v) \ + out_dword(HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV_CDIVR_ADDR,v) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV_CDIVR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV_CDIVR_ADDR,m,v,HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV_CDIVR_IN) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV_CDIVR_CLK_DIV_BMSK 0xf +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV_CDIVR_CLK_DIV_SHFT 0x0 + +#define HWIO_GCC_QOSGEN_EXTREF_DIV_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003900c) +#define HWIO_GCC_QOSGEN_EXTREF_DIV_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003900c) +#define HWIO_GCC_QOSGEN_EXTREF_DIV_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003900c) +#define HWIO_GCC_QOSGEN_EXTREF_DIV_CDIVR_RMSK 0xf +#define HWIO_GCC_QOSGEN_EXTREF_DIV_CDIVR_ATTR 0x3 +#define HWIO_GCC_QOSGEN_EXTREF_DIV_CDIVR_IN \ + in_dword_masked(HWIO_GCC_QOSGEN_EXTREF_DIV_CDIVR_ADDR, HWIO_GCC_QOSGEN_EXTREF_DIV_CDIVR_RMSK) +#define HWIO_GCC_QOSGEN_EXTREF_DIV_CDIVR_INM(m) \ + in_dword_masked(HWIO_GCC_QOSGEN_EXTREF_DIV_CDIVR_ADDR, m) +#define HWIO_GCC_QOSGEN_EXTREF_DIV_CDIVR_OUT(v) \ + out_dword(HWIO_GCC_QOSGEN_EXTREF_DIV_CDIVR_ADDR,v) +#define HWIO_GCC_QOSGEN_EXTREF_DIV_CDIVR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QOSGEN_EXTREF_DIV_CDIVR_ADDR,m,v,HWIO_GCC_QOSGEN_EXTREF_DIV_CDIVR_IN) +#define HWIO_GCC_QOSGEN_EXTREF_DIV_CDIVR_CLK_DIV_BMSK 0xf +#define HWIO_GCC_QOSGEN_EXTREF_DIV_CDIVR_CLK_DIV_SHFT 0x0 + +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV512_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00039010) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV512_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00039010) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV512_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00039010) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV512_CDIVR_RMSK 0x1ff +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV512_CDIVR_ATTR 0x3 +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV512_CDIVR_IN \ + in_dword_masked(HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV512_CDIVR_ADDR, HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV512_CDIVR_RMSK) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV512_CDIVR_INM(m) \ + in_dword_masked(HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV512_CDIVR_ADDR, m) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV512_CDIVR_OUT(v) \ + out_dword(HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV512_CDIVR_ADDR,v) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV512_CDIVR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV512_CDIVR_ADDR,m,v,HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV512_CDIVR_IN) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV512_CDIVR_CLK_DIV_BMSK 0x1ff +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV512_CDIVR_CLK_DIV_SHFT 0x0 + +#define HWIO_GCC_APB2JTAG_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003c000) +#define HWIO_GCC_APB2JTAG_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003c000) +#define HWIO_GCC_APB2JTAG_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003c000) +#define HWIO_GCC_APB2JTAG_BCR_RMSK 0x1 +#define HWIO_GCC_APB2JTAG_BCR_ATTR 0x3 +#define HWIO_GCC_APB2JTAG_BCR_IN \ + in_dword_masked(HWIO_GCC_APB2JTAG_BCR_ADDR, HWIO_GCC_APB2JTAG_BCR_RMSK) +#define HWIO_GCC_APB2JTAG_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_APB2JTAG_BCR_ADDR, m) +#define HWIO_GCC_APB2JTAG_BCR_OUT(v) \ + out_dword(HWIO_GCC_APB2JTAG_BCR_ADDR,v) +#define HWIO_GCC_APB2JTAG_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_APB2JTAG_BCR_ADDR,m,v,HWIO_GCC_APB2JTAG_BCR_IN) +#define HWIO_GCC_APB2JTAG_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_APB2JTAG_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_APB2JTAG_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_APB2JTAG_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RBCPR_CX_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003e000) +#define HWIO_GCC_RBCPR_CX_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003e000) +#define HWIO_GCC_RBCPR_CX_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003e000) +#define HWIO_GCC_RBCPR_CX_BCR_RMSK 0x1 +#define HWIO_GCC_RBCPR_CX_BCR_ATTR 0x3 +#define HWIO_GCC_RBCPR_CX_BCR_IN \ + in_dword_masked(HWIO_GCC_RBCPR_CX_BCR_ADDR, HWIO_GCC_RBCPR_CX_BCR_RMSK) +#define HWIO_GCC_RBCPR_CX_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_RBCPR_CX_BCR_ADDR, m) +#define HWIO_GCC_RBCPR_CX_BCR_OUT(v) \ + out_dword(HWIO_GCC_RBCPR_CX_BCR_ADDR,v) +#define HWIO_GCC_RBCPR_CX_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RBCPR_CX_BCR_ADDR,m,v,HWIO_GCC_RBCPR_CX_BCR_IN) +#define HWIO_GCC_RBCPR_CX_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_RBCPR_CX_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_RBCPR_CX_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_RBCPR_CX_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RBCPR_CX_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003e004) +#define HWIO_GCC_RBCPR_CX_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003e004) +#define HWIO_GCC_RBCPR_CX_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003e004) +#define HWIO_GCC_RBCPR_CX_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_RBCPR_CX_CBCR_ATTR 0x3 +#define HWIO_GCC_RBCPR_CX_CBCR_IN \ + in_dword_masked(HWIO_GCC_RBCPR_CX_CBCR_ADDR, HWIO_GCC_RBCPR_CX_CBCR_RMSK) +#define HWIO_GCC_RBCPR_CX_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_RBCPR_CX_CBCR_ADDR, m) +#define HWIO_GCC_RBCPR_CX_CBCR_OUT(v) \ + out_dword(HWIO_GCC_RBCPR_CX_CBCR_ADDR,v) +#define HWIO_GCC_RBCPR_CX_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RBCPR_CX_CBCR_ADDR,m,v,HWIO_GCC_RBCPR_CX_CBCR_IN) +#define HWIO_GCC_RBCPR_CX_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_RBCPR_CX_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_RBCPR_CX_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_RBCPR_CX_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_RBCPR_CX_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_RBCPR_CX_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_RBCPR_CX_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_RBCPR_CX_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_RBCPR_CX_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_RBCPR_CX_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_RBCPR_CX_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_RBCPR_CX_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_RBCPR_CX_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_RBCPR_CX_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_RBCPR_CX_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_RBCPR_CX_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003e008) +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003e008) +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003e008) +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_RBCPR_CX_AHB_CBCR_ADDR, HWIO_GCC_RBCPR_CX_AHB_CBCR_RMSK) +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_RBCPR_CX_AHB_CBCR_ADDR, m) +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_RBCPR_CX_AHB_CBCR_ADDR,v) +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RBCPR_CX_AHB_CBCR_ADDR,m,v,HWIO_GCC_RBCPR_CX_AHB_CBCR_IN) +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RBCPR_CX_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003e00c) +#define HWIO_GCC_RBCPR_CX_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003e00c) +#define HWIO_GCC_RBCPR_CX_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003e00c) +#define HWIO_GCC_RBCPR_CX_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_RBCPR_CX_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_RBCPR_CX_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_RBCPR_CX_CMD_RCGR_ADDR, HWIO_GCC_RBCPR_CX_CMD_RCGR_RMSK) +#define HWIO_GCC_RBCPR_CX_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_RBCPR_CX_CMD_RCGR_ADDR, m) +#define HWIO_GCC_RBCPR_CX_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_RBCPR_CX_CMD_RCGR_ADDR,v) +#define HWIO_GCC_RBCPR_CX_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RBCPR_CX_CMD_RCGR_ADDR,m,v,HWIO_GCC_RBCPR_CX_CMD_RCGR_IN) +#define HWIO_GCC_RBCPR_CX_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_RBCPR_CX_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_RBCPR_CX_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_RBCPR_CX_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_RBCPR_CX_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_RBCPR_CX_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_RBCPR_CX_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_RBCPR_CX_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_RBCPR_CX_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_RBCPR_CX_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_RBCPR_CX_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_RBCPR_CX_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003e010) +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003e010) +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003e010) +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_RBCPR_CX_CFG_RCGR_ADDR, HWIO_GCC_RBCPR_CX_CFG_RCGR_RMSK) +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_RBCPR_CX_CFG_RCGR_ADDR, m) +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_RBCPR_CX_CFG_RCGR_ADDR,v) +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RBCPR_CX_CFG_RCGR_ADDR,m,v,HWIO_GCC_RBCPR_CX_CFG_RCGR_IN) +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RBCPR_MXC_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003f000) +#define HWIO_GCC_RBCPR_MXC_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003f000) +#define HWIO_GCC_RBCPR_MXC_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003f000) +#define HWIO_GCC_RBCPR_MXC_BCR_RMSK 0x1 +#define HWIO_GCC_RBCPR_MXC_BCR_ATTR 0x3 +#define HWIO_GCC_RBCPR_MXC_BCR_IN \ + in_dword_masked(HWIO_GCC_RBCPR_MXC_BCR_ADDR, HWIO_GCC_RBCPR_MXC_BCR_RMSK) +#define HWIO_GCC_RBCPR_MXC_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_RBCPR_MXC_BCR_ADDR, m) +#define HWIO_GCC_RBCPR_MXC_BCR_OUT(v) \ + out_dword(HWIO_GCC_RBCPR_MXC_BCR_ADDR,v) +#define HWIO_GCC_RBCPR_MXC_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RBCPR_MXC_BCR_ADDR,m,v,HWIO_GCC_RBCPR_MXC_BCR_IN) +#define HWIO_GCC_RBCPR_MXC_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_RBCPR_MXC_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_RBCPR_MXC_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_RBCPR_MXC_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RBCPR_MXC_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003f004) +#define HWIO_GCC_RBCPR_MXC_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003f004) +#define HWIO_GCC_RBCPR_MXC_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003f004) +#define HWIO_GCC_RBCPR_MXC_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_RBCPR_MXC_CBCR_ATTR 0x3 +#define HWIO_GCC_RBCPR_MXC_CBCR_IN \ + in_dword_masked(HWIO_GCC_RBCPR_MXC_CBCR_ADDR, HWIO_GCC_RBCPR_MXC_CBCR_RMSK) +#define HWIO_GCC_RBCPR_MXC_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_RBCPR_MXC_CBCR_ADDR, m) +#define HWIO_GCC_RBCPR_MXC_CBCR_OUT(v) \ + out_dword(HWIO_GCC_RBCPR_MXC_CBCR_ADDR,v) +#define HWIO_GCC_RBCPR_MXC_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RBCPR_MXC_CBCR_ADDR,m,v,HWIO_GCC_RBCPR_MXC_CBCR_IN) +#define HWIO_GCC_RBCPR_MXC_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_RBCPR_MXC_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_RBCPR_MXC_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_RBCPR_MXC_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_RBCPR_MXC_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_RBCPR_MXC_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_RBCPR_MXC_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_RBCPR_MXC_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_RBCPR_MXC_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_RBCPR_MXC_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_RBCPR_MXC_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_RBCPR_MXC_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_RBCPR_MXC_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_RBCPR_MXC_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_RBCPR_MXC_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_RBCPR_MXC_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RBCPR_MXC_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003f008) +#define HWIO_GCC_RBCPR_MXC_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003f008) +#define HWIO_GCC_RBCPR_MXC_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003f008) +#define HWIO_GCC_RBCPR_MXC_AHB_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_RBCPR_MXC_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_RBCPR_MXC_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_RBCPR_MXC_AHB_CBCR_ADDR, HWIO_GCC_RBCPR_MXC_AHB_CBCR_RMSK) +#define HWIO_GCC_RBCPR_MXC_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_RBCPR_MXC_AHB_CBCR_ADDR, m) +#define HWIO_GCC_RBCPR_MXC_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_RBCPR_MXC_AHB_CBCR_ADDR,v) +#define HWIO_GCC_RBCPR_MXC_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RBCPR_MXC_AHB_CBCR_ADDR,m,v,HWIO_GCC_RBCPR_MXC_AHB_CBCR_IN) +#define HWIO_GCC_RBCPR_MXC_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_RBCPR_MXC_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_RBCPR_MXC_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_RBCPR_MXC_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_RBCPR_MXC_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_RBCPR_MXC_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_RBCPR_MXC_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_RBCPR_MXC_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_RBCPR_MXC_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_RBCPR_MXC_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_RBCPR_MXC_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_RBCPR_MXC_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_RBCPR_MXC_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_RBCPR_MXC_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_RBCPR_MXC_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_RBCPR_MXC_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_RBCPR_MXC_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_RBCPR_MXC_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_RBCPR_MXC_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_RBCPR_MXC_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_RBCPR_MXC_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_RBCPR_MXC_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_RBCPR_MXC_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_RBCPR_MXC_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RBCPR_MXC_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003f00c) +#define HWIO_GCC_RBCPR_MXC_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003f00c) +#define HWIO_GCC_RBCPR_MXC_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003f00c) +#define HWIO_GCC_RBCPR_MXC_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_RBCPR_MXC_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_RBCPR_MXC_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_RBCPR_MXC_CMD_RCGR_ADDR, HWIO_GCC_RBCPR_MXC_CMD_RCGR_RMSK) +#define HWIO_GCC_RBCPR_MXC_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_RBCPR_MXC_CMD_RCGR_ADDR, m) +#define HWIO_GCC_RBCPR_MXC_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_RBCPR_MXC_CMD_RCGR_ADDR,v) +#define HWIO_GCC_RBCPR_MXC_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RBCPR_MXC_CMD_RCGR_ADDR,m,v,HWIO_GCC_RBCPR_MXC_CMD_RCGR_IN) +#define HWIO_GCC_RBCPR_MXC_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_RBCPR_MXC_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_RBCPR_MXC_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_RBCPR_MXC_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_RBCPR_MXC_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_RBCPR_MXC_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_RBCPR_MXC_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_RBCPR_MXC_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_RBCPR_MXC_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_RBCPR_MXC_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_RBCPR_MXC_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_RBCPR_MXC_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003f010) +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003f010) +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003f010) +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_RBCPR_MXC_CFG_RCGR_ADDR, HWIO_GCC_RBCPR_MXC_CFG_RCGR_RMSK) +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_RBCPR_MXC_CFG_RCGR_ADDR, m) +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_RBCPR_MXC_CFG_RCGR_ADDR,v) +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RBCPR_MXC_CFG_RCGR_ADDR,m,v,HWIO_GCC_RBCPR_MXC_CFG_RCGR_IN) +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RBCPR_MXC_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RBCPR_MXA_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000d000) +#define HWIO_GCC_RBCPR_MXA_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000d000) +#define HWIO_GCC_RBCPR_MXA_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000d000) +#define HWIO_GCC_RBCPR_MXA_BCR_RMSK 0x1 +#define HWIO_GCC_RBCPR_MXA_BCR_ATTR 0x3 +#define HWIO_GCC_RBCPR_MXA_BCR_IN \ + in_dword_masked(HWIO_GCC_RBCPR_MXA_BCR_ADDR, HWIO_GCC_RBCPR_MXA_BCR_RMSK) +#define HWIO_GCC_RBCPR_MXA_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_RBCPR_MXA_BCR_ADDR, m) +#define HWIO_GCC_RBCPR_MXA_BCR_OUT(v) \ + out_dword(HWIO_GCC_RBCPR_MXA_BCR_ADDR,v) +#define HWIO_GCC_RBCPR_MXA_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RBCPR_MXA_BCR_ADDR,m,v,HWIO_GCC_RBCPR_MXA_BCR_IN) +#define HWIO_GCC_RBCPR_MXA_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_RBCPR_MXA_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_RBCPR_MXA_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_RBCPR_MXA_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RBCPR_MXA_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000d004) +#define HWIO_GCC_RBCPR_MXA_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000d004) +#define HWIO_GCC_RBCPR_MXA_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000d004) +#define HWIO_GCC_RBCPR_MXA_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_RBCPR_MXA_CBCR_ATTR 0x3 +#define HWIO_GCC_RBCPR_MXA_CBCR_IN \ + in_dword_masked(HWIO_GCC_RBCPR_MXA_CBCR_ADDR, HWIO_GCC_RBCPR_MXA_CBCR_RMSK) +#define HWIO_GCC_RBCPR_MXA_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_RBCPR_MXA_CBCR_ADDR, m) +#define HWIO_GCC_RBCPR_MXA_CBCR_OUT(v) \ + out_dword(HWIO_GCC_RBCPR_MXA_CBCR_ADDR,v) +#define HWIO_GCC_RBCPR_MXA_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RBCPR_MXA_CBCR_ADDR,m,v,HWIO_GCC_RBCPR_MXA_CBCR_IN) +#define HWIO_GCC_RBCPR_MXA_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_RBCPR_MXA_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_RBCPR_MXA_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_RBCPR_MXA_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_RBCPR_MXA_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_RBCPR_MXA_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_RBCPR_MXA_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_RBCPR_MXA_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_RBCPR_MXA_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_RBCPR_MXA_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_RBCPR_MXA_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_RBCPR_MXA_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_RBCPR_MXA_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_RBCPR_MXA_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_RBCPR_MXA_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_RBCPR_MXA_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RBCPR_MXA_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000d008) +#define HWIO_GCC_RBCPR_MXA_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000d008) +#define HWIO_GCC_RBCPR_MXA_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000d008) +#define HWIO_GCC_RBCPR_MXA_AHB_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_RBCPR_MXA_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_RBCPR_MXA_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_RBCPR_MXA_AHB_CBCR_ADDR, HWIO_GCC_RBCPR_MXA_AHB_CBCR_RMSK) +#define HWIO_GCC_RBCPR_MXA_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_RBCPR_MXA_AHB_CBCR_ADDR, m) +#define HWIO_GCC_RBCPR_MXA_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_RBCPR_MXA_AHB_CBCR_ADDR,v) +#define HWIO_GCC_RBCPR_MXA_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RBCPR_MXA_AHB_CBCR_ADDR,m,v,HWIO_GCC_RBCPR_MXA_AHB_CBCR_IN) +#define HWIO_GCC_RBCPR_MXA_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_RBCPR_MXA_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_RBCPR_MXA_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_RBCPR_MXA_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_RBCPR_MXA_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_RBCPR_MXA_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_RBCPR_MXA_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_RBCPR_MXA_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_RBCPR_MXA_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_RBCPR_MXA_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_RBCPR_MXA_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_RBCPR_MXA_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_RBCPR_MXA_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_RBCPR_MXA_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_RBCPR_MXA_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_RBCPR_MXA_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_RBCPR_MXA_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_RBCPR_MXA_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_RBCPR_MXA_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_RBCPR_MXA_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_RBCPR_MXA_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_RBCPR_MXA_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_RBCPR_MXA_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_RBCPR_MXA_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RBCPR_MXA_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000d00c) +#define HWIO_GCC_RBCPR_MXA_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000d00c) +#define HWIO_GCC_RBCPR_MXA_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000d00c) +#define HWIO_GCC_RBCPR_MXA_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_RBCPR_MXA_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_RBCPR_MXA_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_RBCPR_MXA_CMD_RCGR_ADDR, HWIO_GCC_RBCPR_MXA_CMD_RCGR_RMSK) +#define HWIO_GCC_RBCPR_MXA_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_RBCPR_MXA_CMD_RCGR_ADDR, m) +#define HWIO_GCC_RBCPR_MXA_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_RBCPR_MXA_CMD_RCGR_ADDR,v) +#define HWIO_GCC_RBCPR_MXA_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RBCPR_MXA_CMD_RCGR_ADDR,m,v,HWIO_GCC_RBCPR_MXA_CMD_RCGR_IN) +#define HWIO_GCC_RBCPR_MXA_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_RBCPR_MXA_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_RBCPR_MXA_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_RBCPR_MXA_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_RBCPR_MXA_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_RBCPR_MXA_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_RBCPR_MXA_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_RBCPR_MXA_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_RBCPR_MXA_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_RBCPR_MXA_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_RBCPR_MXA_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_RBCPR_MXA_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RBCPR_MXA_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000d010) +#define HWIO_GCC_RBCPR_MXA_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000d010) +#define HWIO_GCC_RBCPR_MXA_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000d010) +#define HWIO_GCC_RBCPR_MXA_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_RBCPR_MXA_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_RBCPR_MXA_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_RBCPR_MXA_CFG_RCGR_ADDR, HWIO_GCC_RBCPR_MXA_CFG_RCGR_RMSK) +#define HWIO_GCC_RBCPR_MXA_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_RBCPR_MXA_CFG_RCGR_ADDR, m) +#define HWIO_GCC_RBCPR_MXA_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_RBCPR_MXA_CFG_RCGR_ADDR,v) +#define HWIO_GCC_RBCPR_MXA_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RBCPR_MXA_CFG_RCGR_ADDR,m,v,HWIO_GCC_RBCPR_MXA_CFG_RCGR_IN) +#define HWIO_GCC_RBCPR_MXA_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_RBCPR_MXA_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_RBCPR_MXA_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_RBCPR_MXA_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_RBCPR_MXA_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_RBCPR_MXA_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_RBCPR_MXA_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_RBCPR_MXA_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_RBCPR_MXA_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RBCPR_MXA_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RBCPR_MXA_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RBCPR_MXA_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RBCPR_MXA_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RBCPR_MXA_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RBCPR_MXA_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RBCPR_MXA_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RBCPR_MXA_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RBCPR_MXA_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RBCPR_MXA_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RBCPR_MXA_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RBCPR_MXA_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RBCPR_MXA_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RBCPR_MXA_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RBCPR_MXA_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RBCPR_MXA_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RBCPR_MXA_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RBCPR_MXA_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RBCPR_MXA_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RBCPR_MXA_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RBCPR_MXA_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RBCPR_MXA_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RBCPR_MXA_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RBCPR_MXA_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RBCPR_MXA_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RBCPR_MXA_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RBCPR_MXA_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RBCPR_MXA_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RBCPR_MXA_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RBCPR_MXA_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RBCPR_MXA_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RBCPR_MXA_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RBCPR_MXA_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RBCPR_MXA_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RBCPR_MXA_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RBCPR_MXA_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RBCPR_MXA_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RBCPR_MXA_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RBCPR_MXA_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RBCPR_MXA_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RBCPR_MXA_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RBCPR_MXA_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RBCPR_MXA_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RBCPR_NSP_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000d024) +#define HWIO_GCC_RBCPR_NSP_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000d024) +#define HWIO_GCC_RBCPR_NSP_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000d024) +#define HWIO_GCC_RBCPR_NSP_BCR_RMSK 0x1 +#define HWIO_GCC_RBCPR_NSP_BCR_ATTR 0x3 +#define HWIO_GCC_RBCPR_NSP_BCR_IN \ + in_dword_masked(HWIO_GCC_RBCPR_NSP_BCR_ADDR, HWIO_GCC_RBCPR_NSP_BCR_RMSK) +#define HWIO_GCC_RBCPR_NSP_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_RBCPR_NSP_BCR_ADDR, m) +#define HWIO_GCC_RBCPR_NSP_BCR_OUT(v) \ + out_dword(HWIO_GCC_RBCPR_NSP_BCR_ADDR,v) +#define HWIO_GCC_RBCPR_NSP_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RBCPR_NSP_BCR_ADDR,m,v,HWIO_GCC_RBCPR_NSP_BCR_IN) +#define HWIO_GCC_RBCPR_NSP_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_RBCPR_NSP_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_RBCPR_NSP_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_RBCPR_NSP_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RBCPR_NSP_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000d028) +#define HWIO_GCC_RBCPR_NSP_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000d028) +#define HWIO_GCC_RBCPR_NSP_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000d028) +#define HWIO_GCC_RBCPR_NSP_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_RBCPR_NSP_CBCR_ATTR 0x3 +#define HWIO_GCC_RBCPR_NSP_CBCR_IN \ + in_dword_masked(HWIO_GCC_RBCPR_NSP_CBCR_ADDR, HWIO_GCC_RBCPR_NSP_CBCR_RMSK) +#define HWIO_GCC_RBCPR_NSP_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_RBCPR_NSP_CBCR_ADDR, m) +#define HWIO_GCC_RBCPR_NSP_CBCR_OUT(v) \ + out_dword(HWIO_GCC_RBCPR_NSP_CBCR_ADDR,v) +#define HWIO_GCC_RBCPR_NSP_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RBCPR_NSP_CBCR_ADDR,m,v,HWIO_GCC_RBCPR_NSP_CBCR_IN) +#define HWIO_GCC_RBCPR_NSP_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_RBCPR_NSP_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_RBCPR_NSP_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_RBCPR_NSP_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_RBCPR_NSP_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_RBCPR_NSP_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_RBCPR_NSP_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_RBCPR_NSP_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_RBCPR_NSP_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_RBCPR_NSP_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_RBCPR_NSP_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_RBCPR_NSP_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_RBCPR_NSP_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_RBCPR_NSP_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_RBCPR_NSP_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_RBCPR_NSP_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RBCPR_NSP_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000d02c) +#define HWIO_GCC_RBCPR_NSP_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000d02c) +#define HWIO_GCC_RBCPR_NSP_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000d02c) +#define HWIO_GCC_RBCPR_NSP_AHB_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_RBCPR_NSP_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_RBCPR_NSP_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_RBCPR_NSP_AHB_CBCR_ADDR, HWIO_GCC_RBCPR_NSP_AHB_CBCR_RMSK) +#define HWIO_GCC_RBCPR_NSP_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_RBCPR_NSP_AHB_CBCR_ADDR, m) +#define HWIO_GCC_RBCPR_NSP_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_RBCPR_NSP_AHB_CBCR_ADDR,v) +#define HWIO_GCC_RBCPR_NSP_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RBCPR_NSP_AHB_CBCR_ADDR,m,v,HWIO_GCC_RBCPR_NSP_AHB_CBCR_IN) +#define HWIO_GCC_RBCPR_NSP_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_RBCPR_NSP_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_RBCPR_NSP_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_RBCPR_NSP_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_RBCPR_NSP_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_RBCPR_NSP_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_RBCPR_NSP_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_RBCPR_NSP_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_RBCPR_NSP_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_RBCPR_NSP_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_RBCPR_NSP_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_RBCPR_NSP_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_RBCPR_NSP_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_RBCPR_NSP_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_RBCPR_NSP_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_RBCPR_NSP_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_RBCPR_NSP_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_RBCPR_NSP_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_RBCPR_NSP_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_RBCPR_NSP_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_RBCPR_NSP_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_RBCPR_NSP_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_RBCPR_NSP_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_RBCPR_NSP_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RBCPR_NSP_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000d030) +#define HWIO_GCC_RBCPR_NSP_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000d030) +#define HWIO_GCC_RBCPR_NSP_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000d030) +#define HWIO_GCC_RBCPR_NSP_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_RBCPR_NSP_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_RBCPR_NSP_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_RBCPR_NSP_CMD_RCGR_ADDR, HWIO_GCC_RBCPR_NSP_CMD_RCGR_RMSK) +#define HWIO_GCC_RBCPR_NSP_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_RBCPR_NSP_CMD_RCGR_ADDR, m) +#define HWIO_GCC_RBCPR_NSP_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_RBCPR_NSP_CMD_RCGR_ADDR,v) +#define HWIO_GCC_RBCPR_NSP_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RBCPR_NSP_CMD_RCGR_ADDR,m,v,HWIO_GCC_RBCPR_NSP_CMD_RCGR_IN) +#define HWIO_GCC_RBCPR_NSP_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_RBCPR_NSP_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_RBCPR_NSP_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_RBCPR_NSP_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_RBCPR_NSP_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_RBCPR_NSP_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_RBCPR_NSP_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_RBCPR_NSP_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_RBCPR_NSP_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_RBCPR_NSP_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_RBCPR_NSP_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_RBCPR_NSP_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RBCPR_NSP_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000d034) +#define HWIO_GCC_RBCPR_NSP_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000d034) +#define HWIO_GCC_RBCPR_NSP_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000d034) +#define HWIO_GCC_RBCPR_NSP_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_RBCPR_NSP_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_RBCPR_NSP_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_RBCPR_NSP_CFG_RCGR_ADDR, HWIO_GCC_RBCPR_NSP_CFG_RCGR_RMSK) +#define HWIO_GCC_RBCPR_NSP_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_RBCPR_NSP_CFG_RCGR_ADDR, m) +#define HWIO_GCC_RBCPR_NSP_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_RBCPR_NSP_CFG_RCGR_ADDR,v) +#define HWIO_GCC_RBCPR_NSP_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RBCPR_NSP_CFG_RCGR_ADDR,m,v,HWIO_GCC_RBCPR_NSP_CFG_RCGR_IN) +#define HWIO_GCC_RBCPR_NSP_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_RBCPR_NSP_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_RBCPR_NSP_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_RBCPR_NSP_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_RBCPR_NSP_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_RBCPR_NSP_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_RBCPR_NSP_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_RBCPR_NSP_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_RBCPR_NSP_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RBCPR_NSP_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RBCPR_NSP_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RBCPR_NSP_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RBCPR_NSP_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RBCPR_NSP_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RBCPR_NSP_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RBCPR_NSP_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RBCPR_NSP_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RBCPR_NSP_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RBCPR_NSP_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RBCPR_NSP_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RBCPR_NSP_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RBCPR_NSP_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RBCPR_NSP_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RBCPR_NSP_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RBCPR_NSP_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RBCPR_NSP_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RBCPR_NSP_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RBCPR_NSP_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RBCPR_NSP_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RBCPR_NSP_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RBCPR_NSP_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RBCPR_NSP_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RBCPR_NSP_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RBCPR_NSP_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RBCPR_NSP_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RBCPR_NSP_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RBCPR_NSP_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RBCPR_NSP_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RBCPR_NSP_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RBCPR_NSP_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RBCPR_NSP_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RBCPR_NSP_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RBCPR_NSP_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RBCPR_NSP_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RBCPR_NSP_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RBCPR_NSP_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RBCPR_NSP_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RBCPR_NSP_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RBCPR_NSP_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RBCPR_NSP_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RBCPR_NSP_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RBCPR_NSP_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_DEBUG_DIV_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00052000) +#define HWIO_GCC_DEBUG_DIV_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00052000) +#define HWIO_GCC_DEBUG_DIV_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00052000) +#define HWIO_GCC_DEBUG_DIV_CDIVR_RMSK 0xf +#define HWIO_GCC_DEBUG_DIV_CDIVR_ATTR 0x3 +#define HWIO_GCC_DEBUG_DIV_CDIVR_IN \ + in_dword_masked(HWIO_GCC_DEBUG_DIV_CDIVR_ADDR, HWIO_GCC_DEBUG_DIV_CDIVR_RMSK) +#define HWIO_GCC_DEBUG_DIV_CDIVR_INM(m) \ + in_dword_masked(HWIO_GCC_DEBUG_DIV_CDIVR_ADDR, m) +#define HWIO_GCC_DEBUG_DIV_CDIVR_OUT(v) \ + out_dword(HWIO_GCC_DEBUG_DIV_CDIVR_ADDR,v) +#define HWIO_GCC_DEBUG_DIV_CDIVR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DEBUG_DIV_CDIVR_ADDR,m,v,HWIO_GCC_DEBUG_DIV_CDIVR_IN) +#define HWIO_GCC_DEBUG_DIV_CDIVR_CLK_DIV_BMSK 0xf +#define HWIO_GCC_DEBUG_DIV_CDIVR_CLK_DIV_SHFT 0x0 + +#define HWIO_GCC_DEBUG_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00052004) +#define HWIO_GCC_DEBUG_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00052004) +#define HWIO_GCC_DEBUG_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00052004) +#define HWIO_GCC_DEBUG_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_DEBUG_CBCR_ATTR 0x3 +#define HWIO_GCC_DEBUG_CBCR_IN \ + in_dword_masked(HWIO_GCC_DEBUG_CBCR_ADDR, HWIO_GCC_DEBUG_CBCR_RMSK) +#define HWIO_GCC_DEBUG_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_DEBUG_CBCR_ADDR, m) +#define HWIO_GCC_DEBUG_CBCR_OUT(v) \ + out_dword(HWIO_GCC_DEBUG_CBCR_ADDR,v) +#define HWIO_GCC_DEBUG_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DEBUG_CBCR_ADDR,m,v,HWIO_GCC_DEBUG_CBCR_IN) +#define HWIO_GCC_DEBUG_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_DEBUG_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_DEBUG_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_DEBUG_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_DEBUG_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_DEBUG_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_DEBUG_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_DEBUG_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_DEBUG_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_DEBUG_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_DEBUG_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_DEBUG_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_DEBUG_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_DEBUG_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_DEBUG_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DEBUG_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_FRQ_MEASURE_REF_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00052008) +#define HWIO_GCC_FRQ_MEASURE_REF_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00052008) +#define HWIO_GCC_FRQ_MEASURE_REF_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00052008) +#define HWIO_GCC_FRQ_MEASURE_REF_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_FRQ_MEASURE_REF_CBCR_ATTR 0x3 +#define HWIO_GCC_FRQ_MEASURE_REF_CBCR_IN \ + in_dword_masked(HWIO_GCC_FRQ_MEASURE_REF_CBCR_ADDR, HWIO_GCC_FRQ_MEASURE_REF_CBCR_RMSK) +#define HWIO_GCC_FRQ_MEASURE_REF_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_FRQ_MEASURE_REF_CBCR_ADDR, m) +#define HWIO_GCC_FRQ_MEASURE_REF_CBCR_OUT(v) \ + out_dword(HWIO_GCC_FRQ_MEASURE_REF_CBCR_ADDR,v) +#define HWIO_GCC_FRQ_MEASURE_REF_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_FRQ_MEASURE_REF_CBCR_ADDR,m,v,HWIO_GCC_FRQ_MEASURE_REF_CBCR_IN) +#define HWIO_GCC_FRQ_MEASURE_REF_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_FRQ_MEASURE_REF_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_FRQ_MEASURE_REF_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_FRQ_MEASURE_REF_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_FRQ_MEASURE_REF_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_FRQ_MEASURE_REF_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_FRQ_MEASURE_REF_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_FRQ_MEASURE_REF_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_FRQ_MEASURE_REF_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_FRQ_MEASURE_REF_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_FRQ_MEASURE_REF_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_FRQ_MEASURE_REF_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_FRQ_MEASURE_REF_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_FRQ_MEASURE_REF_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_FRQ_MEASURE_REF_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_FRQ_MEASURE_REF_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PLL_TEST_DIV_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00052010) +#define HWIO_GCC_PLL_TEST_DIV_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00052010) +#define HWIO_GCC_PLL_TEST_DIV_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00052010) +#define HWIO_GCC_PLL_TEST_DIV_CDIVR_RMSK 0xf +#define HWIO_GCC_PLL_TEST_DIV_CDIVR_ATTR 0x3 +#define HWIO_GCC_PLL_TEST_DIV_CDIVR_IN \ + in_dword_masked(HWIO_GCC_PLL_TEST_DIV_CDIVR_ADDR, HWIO_GCC_PLL_TEST_DIV_CDIVR_RMSK) +#define HWIO_GCC_PLL_TEST_DIV_CDIVR_INM(m) \ + in_dword_masked(HWIO_GCC_PLL_TEST_DIV_CDIVR_ADDR, m) +#define HWIO_GCC_PLL_TEST_DIV_CDIVR_OUT(v) \ + out_dword(HWIO_GCC_PLL_TEST_DIV_CDIVR_ADDR,v) +#define HWIO_GCC_PLL_TEST_DIV_CDIVR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PLL_TEST_DIV_CDIVR_ADDR,m,v,HWIO_GCC_PLL_TEST_DIV_CDIVR_IN) +#define HWIO_GCC_PLL_TEST_DIV_CDIVR_CLK_DIV_BMSK 0xf +#define HWIO_GCC_PLL_TEST_DIV_CDIVR_CLK_DIV_SHFT 0x0 + +#define HWIO_GCC_PLL_TEST_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00052014) +#define HWIO_GCC_PLL_TEST_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00052014) +#define HWIO_GCC_PLL_TEST_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00052014) +#define HWIO_GCC_PLL_TEST_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_PLL_TEST_CBCR_ATTR 0x3 +#define HWIO_GCC_PLL_TEST_CBCR_IN \ + in_dword_masked(HWIO_GCC_PLL_TEST_CBCR_ADDR, HWIO_GCC_PLL_TEST_CBCR_RMSK) +#define HWIO_GCC_PLL_TEST_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_PLL_TEST_CBCR_ADDR, m) +#define HWIO_GCC_PLL_TEST_CBCR_OUT(v) \ + out_dword(HWIO_GCC_PLL_TEST_CBCR_ADDR,v) +#define HWIO_GCC_PLL_TEST_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PLL_TEST_CBCR_ADDR,m,v,HWIO_GCC_PLL_TEST_CBCR_IN) +#define HWIO_GCC_PLL_TEST_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_PLL_TEST_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_PLL_TEST_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_PLL_TEST_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_PLL_TEST_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_PLL_TEST_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_PLL_TEST_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_PLL_TEST_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_PLL_TEST_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_PLL_TEST_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_PLL_TEST_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_PLL_TEST_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_PLL_TEST_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_PLL_TEST_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_PLL_TEST_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PLL_TEST_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GP1_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00054000) +#define HWIO_GCC_GP1_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00054000) +#define HWIO_GCC_GP1_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00054000) +#define HWIO_GCC_GP1_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_GP1_CBCR_ATTR 0x3 +#define HWIO_GCC_GP1_CBCR_IN \ + in_dword_masked(HWIO_GCC_GP1_CBCR_ADDR, HWIO_GCC_GP1_CBCR_RMSK) +#define HWIO_GCC_GP1_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_GP1_CBCR_ADDR, m) +#define HWIO_GCC_GP1_CBCR_OUT(v) \ + out_dword(HWIO_GCC_GP1_CBCR_ADDR,v) +#define HWIO_GCC_GP1_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GP1_CBCR_ADDR,m,v,HWIO_GCC_GP1_CBCR_IN) +#define HWIO_GCC_GP1_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_GP1_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_GP1_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_GP1_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_GP1_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_GP1_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_GP1_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_GP1_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_GP1_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_GP1_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_GP1_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_GP1_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_GP1_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GP1_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_GP1_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GP1_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GP1_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00054004) +#define HWIO_GCC_GP1_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00054004) +#define HWIO_GCC_GP1_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00054004) +#define HWIO_GCC_GP1_CMD_RCGR_RMSK 0x800000f3 +#define HWIO_GCC_GP1_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_GP1_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_GP1_CMD_RCGR_ADDR, HWIO_GCC_GP1_CMD_RCGR_RMSK) +#define HWIO_GCC_GP1_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_GP1_CMD_RCGR_ADDR, m) +#define HWIO_GCC_GP1_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_GP1_CMD_RCGR_ADDR,v) +#define HWIO_GCC_GP1_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GP1_CMD_RCGR_ADDR,m,v,HWIO_GCC_GP1_CMD_RCGR_IN) +#define HWIO_GCC_GP1_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_GP1_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_GP1_CMD_RCGR_DIRTY_D_BMSK 0x80 +#define HWIO_GCC_GP1_CMD_RCGR_DIRTY_D_SHFT 0x7 +#define HWIO_GCC_GP1_CMD_RCGR_DIRTY_N_BMSK 0x40 +#define HWIO_GCC_GP1_CMD_RCGR_DIRTY_N_SHFT 0x6 +#define HWIO_GCC_GP1_CMD_RCGR_DIRTY_M_BMSK 0x20 +#define HWIO_GCC_GP1_CMD_RCGR_DIRTY_M_SHFT 0x5 +#define HWIO_GCC_GP1_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_GP1_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_GP1_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_GP1_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_GP1_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_GP1_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_GP1_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_GP1_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_GP1_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GP1_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GP1_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00054008) +#define HWIO_GCC_GP1_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00054008) +#define HWIO_GCC_GP1_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00054008) +#define HWIO_GCC_GP1_CFG_RCGR_RMSK 0x10371f +#define HWIO_GCC_GP1_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_GP1_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_GP1_CFG_RCGR_ADDR, HWIO_GCC_GP1_CFG_RCGR_RMSK) +#define HWIO_GCC_GP1_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_GP1_CFG_RCGR_ADDR, m) +#define HWIO_GCC_GP1_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_GP1_CFG_RCGR_ADDR,v) +#define HWIO_GCC_GP1_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GP1_CFG_RCGR_ADDR,m,v,HWIO_GCC_GP1_CFG_RCGR_IN) +#define HWIO_GCC_GP1_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_GP1_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_GP1_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_GP1_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_GP1_CFG_RCGR_MODE_BMSK 0x3000 +#define HWIO_GCC_GP1_CFG_RCGR_MODE_SHFT 0xc +#define HWIO_GCC_GP1_CFG_RCGR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_GP1_CFG_RCGR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_GP1_CFG_RCGR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_GP1_CFG_RCGR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_GP1_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005400c) +#define HWIO_GCC_GP1_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005400c) +#define HWIO_GCC_GP1_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005400c) +#define HWIO_GCC_GP1_M_RMSK 0xffff +#define HWIO_GCC_GP1_M_ATTR 0x3 +#define HWIO_GCC_GP1_M_IN \ + in_dword_masked(HWIO_GCC_GP1_M_ADDR, HWIO_GCC_GP1_M_RMSK) +#define HWIO_GCC_GP1_M_INM(m) \ + in_dword_masked(HWIO_GCC_GP1_M_ADDR, m) +#define HWIO_GCC_GP1_M_OUT(v) \ + out_dword(HWIO_GCC_GP1_M_ADDR,v) +#define HWIO_GCC_GP1_M_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GP1_M_ADDR,m,v,HWIO_GCC_GP1_M_IN) +#define HWIO_GCC_GP1_M_M_BMSK 0xffff +#define HWIO_GCC_GP1_M_M_SHFT 0x0 + +#define HWIO_GCC_GP1_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00054010) +#define HWIO_GCC_GP1_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00054010) +#define HWIO_GCC_GP1_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00054010) +#define HWIO_GCC_GP1_N_RMSK 0xffff +#define HWIO_GCC_GP1_N_ATTR 0x3 +#define HWIO_GCC_GP1_N_IN \ + in_dword_masked(HWIO_GCC_GP1_N_ADDR, HWIO_GCC_GP1_N_RMSK) +#define HWIO_GCC_GP1_N_INM(m) \ + in_dword_masked(HWIO_GCC_GP1_N_ADDR, m) +#define HWIO_GCC_GP1_N_OUT(v) \ + out_dword(HWIO_GCC_GP1_N_ADDR,v) +#define HWIO_GCC_GP1_N_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GP1_N_ADDR,m,v,HWIO_GCC_GP1_N_IN) +#define HWIO_GCC_GP1_N_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_GP1_N_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_GP1_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00054014) +#define HWIO_GCC_GP1_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00054014) +#define HWIO_GCC_GP1_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00054014) +#define HWIO_GCC_GP1_D_RMSK 0xffff +#define HWIO_GCC_GP1_D_ATTR 0x3 +#define HWIO_GCC_GP1_D_IN \ + in_dword_masked(HWIO_GCC_GP1_D_ADDR, HWIO_GCC_GP1_D_RMSK) +#define HWIO_GCC_GP1_D_INM(m) \ + in_dword_masked(HWIO_GCC_GP1_D_ADDR, m) +#define HWIO_GCC_GP1_D_OUT(v) \ + out_dword(HWIO_GCC_GP1_D_ADDR,v) +#define HWIO_GCC_GP1_D_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GP1_D_ADDR,m,v,HWIO_GCC_GP1_D_IN) +#define HWIO_GCC_GP1_D_NOT_2D_BMSK 0xffff +#define HWIO_GCC_GP1_D_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_GP2_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00055000) +#define HWIO_GCC_GP2_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00055000) +#define HWIO_GCC_GP2_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00055000) +#define HWIO_GCC_GP2_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_GP2_CBCR_ATTR 0x3 +#define HWIO_GCC_GP2_CBCR_IN \ + in_dword_masked(HWIO_GCC_GP2_CBCR_ADDR, HWIO_GCC_GP2_CBCR_RMSK) +#define HWIO_GCC_GP2_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_GP2_CBCR_ADDR, m) +#define HWIO_GCC_GP2_CBCR_OUT(v) \ + out_dword(HWIO_GCC_GP2_CBCR_ADDR,v) +#define HWIO_GCC_GP2_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GP2_CBCR_ADDR,m,v,HWIO_GCC_GP2_CBCR_IN) +#define HWIO_GCC_GP2_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_GP2_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_GP2_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_GP2_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_GP2_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_GP2_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_GP2_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_GP2_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_GP2_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_GP2_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_GP2_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_GP2_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_GP2_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GP2_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_GP2_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GP2_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GP2_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00055004) +#define HWIO_GCC_GP2_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00055004) +#define HWIO_GCC_GP2_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00055004) +#define HWIO_GCC_GP2_CMD_RCGR_RMSK 0x800000f3 +#define HWIO_GCC_GP2_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_GP2_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_GP2_CMD_RCGR_ADDR, HWIO_GCC_GP2_CMD_RCGR_RMSK) +#define HWIO_GCC_GP2_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_GP2_CMD_RCGR_ADDR, m) +#define HWIO_GCC_GP2_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_GP2_CMD_RCGR_ADDR,v) +#define HWIO_GCC_GP2_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GP2_CMD_RCGR_ADDR,m,v,HWIO_GCC_GP2_CMD_RCGR_IN) +#define HWIO_GCC_GP2_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_GP2_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_GP2_CMD_RCGR_DIRTY_D_BMSK 0x80 +#define HWIO_GCC_GP2_CMD_RCGR_DIRTY_D_SHFT 0x7 +#define HWIO_GCC_GP2_CMD_RCGR_DIRTY_N_BMSK 0x40 +#define HWIO_GCC_GP2_CMD_RCGR_DIRTY_N_SHFT 0x6 +#define HWIO_GCC_GP2_CMD_RCGR_DIRTY_M_BMSK 0x20 +#define HWIO_GCC_GP2_CMD_RCGR_DIRTY_M_SHFT 0x5 +#define HWIO_GCC_GP2_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_GP2_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_GP2_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_GP2_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_GP2_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_GP2_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_GP2_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_GP2_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_GP2_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GP2_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GP2_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00055008) +#define HWIO_GCC_GP2_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00055008) +#define HWIO_GCC_GP2_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00055008) +#define HWIO_GCC_GP2_CFG_RCGR_RMSK 0x10371f +#define HWIO_GCC_GP2_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_GP2_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_GP2_CFG_RCGR_ADDR, HWIO_GCC_GP2_CFG_RCGR_RMSK) +#define HWIO_GCC_GP2_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_GP2_CFG_RCGR_ADDR, m) +#define HWIO_GCC_GP2_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_GP2_CFG_RCGR_ADDR,v) +#define HWIO_GCC_GP2_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GP2_CFG_RCGR_ADDR,m,v,HWIO_GCC_GP2_CFG_RCGR_IN) +#define HWIO_GCC_GP2_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_GP2_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_GP2_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_GP2_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_GP2_CFG_RCGR_MODE_BMSK 0x3000 +#define HWIO_GCC_GP2_CFG_RCGR_MODE_SHFT 0xc +#define HWIO_GCC_GP2_CFG_RCGR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_GP2_CFG_RCGR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_GP2_CFG_RCGR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_GP2_CFG_RCGR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_GP2_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005500c) +#define HWIO_GCC_GP2_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005500c) +#define HWIO_GCC_GP2_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005500c) +#define HWIO_GCC_GP2_M_RMSK 0xffff +#define HWIO_GCC_GP2_M_ATTR 0x3 +#define HWIO_GCC_GP2_M_IN \ + in_dword_masked(HWIO_GCC_GP2_M_ADDR, HWIO_GCC_GP2_M_RMSK) +#define HWIO_GCC_GP2_M_INM(m) \ + in_dword_masked(HWIO_GCC_GP2_M_ADDR, m) +#define HWIO_GCC_GP2_M_OUT(v) \ + out_dword(HWIO_GCC_GP2_M_ADDR,v) +#define HWIO_GCC_GP2_M_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GP2_M_ADDR,m,v,HWIO_GCC_GP2_M_IN) +#define HWIO_GCC_GP2_M_M_BMSK 0xffff +#define HWIO_GCC_GP2_M_M_SHFT 0x0 + +#define HWIO_GCC_GP2_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00055010) +#define HWIO_GCC_GP2_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00055010) +#define HWIO_GCC_GP2_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00055010) +#define HWIO_GCC_GP2_N_RMSK 0xffff +#define HWIO_GCC_GP2_N_ATTR 0x3 +#define HWIO_GCC_GP2_N_IN \ + in_dword_masked(HWIO_GCC_GP2_N_ADDR, HWIO_GCC_GP2_N_RMSK) +#define HWIO_GCC_GP2_N_INM(m) \ + in_dword_masked(HWIO_GCC_GP2_N_ADDR, m) +#define HWIO_GCC_GP2_N_OUT(v) \ + out_dword(HWIO_GCC_GP2_N_ADDR,v) +#define HWIO_GCC_GP2_N_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GP2_N_ADDR,m,v,HWIO_GCC_GP2_N_IN) +#define HWIO_GCC_GP2_N_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_GP2_N_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_GP2_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00055014) +#define HWIO_GCC_GP2_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00055014) +#define HWIO_GCC_GP2_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00055014) +#define HWIO_GCC_GP2_D_RMSK 0xffff +#define HWIO_GCC_GP2_D_ATTR 0x3 +#define HWIO_GCC_GP2_D_IN \ + in_dword_masked(HWIO_GCC_GP2_D_ADDR, HWIO_GCC_GP2_D_RMSK) +#define HWIO_GCC_GP2_D_INM(m) \ + in_dword_masked(HWIO_GCC_GP2_D_ADDR, m) +#define HWIO_GCC_GP2_D_OUT(v) \ + out_dword(HWIO_GCC_GP2_D_ADDR,v) +#define HWIO_GCC_GP2_D_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GP2_D_ADDR,m,v,HWIO_GCC_GP2_D_IN) +#define HWIO_GCC_GP2_D_NOT_2D_BMSK 0xffff +#define HWIO_GCC_GP2_D_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_GP3_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00056000) +#define HWIO_GCC_GP3_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00056000) +#define HWIO_GCC_GP3_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00056000) +#define HWIO_GCC_GP3_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_GP3_CBCR_ATTR 0x3 +#define HWIO_GCC_GP3_CBCR_IN \ + in_dword_masked(HWIO_GCC_GP3_CBCR_ADDR, HWIO_GCC_GP3_CBCR_RMSK) +#define HWIO_GCC_GP3_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_GP3_CBCR_ADDR, m) +#define HWIO_GCC_GP3_CBCR_OUT(v) \ + out_dword(HWIO_GCC_GP3_CBCR_ADDR,v) +#define HWIO_GCC_GP3_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GP3_CBCR_ADDR,m,v,HWIO_GCC_GP3_CBCR_IN) +#define HWIO_GCC_GP3_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_GP3_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_GP3_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_GP3_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_GP3_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_GP3_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_GP3_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_GP3_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_GP3_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_GP3_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_GP3_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_GP3_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_GP3_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GP3_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_GP3_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GP3_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GP3_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00056004) +#define HWIO_GCC_GP3_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00056004) +#define HWIO_GCC_GP3_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00056004) +#define HWIO_GCC_GP3_CMD_RCGR_RMSK 0x800000f3 +#define HWIO_GCC_GP3_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_GP3_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_GP3_CMD_RCGR_ADDR, HWIO_GCC_GP3_CMD_RCGR_RMSK) +#define HWIO_GCC_GP3_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_GP3_CMD_RCGR_ADDR, m) +#define HWIO_GCC_GP3_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_GP3_CMD_RCGR_ADDR,v) +#define HWIO_GCC_GP3_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GP3_CMD_RCGR_ADDR,m,v,HWIO_GCC_GP3_CMD_RCGR_IN) +#define HWIO_GCC_GP3_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_GP3_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_GP3_CMD_RCGR_DIRTY_D_BMSK 0x80 +#define HWIO_GCC_GP3_CMD_RCGR_DIRTY_D_SHFT 0x7 +#define HWIO_GCC_GP3_CMD_RCGR_DIRTY_N_BMSK 0x40 +#define HWIO_GCC_GP3_CMD_RCGR_DIRTY_N_SHFT 0x6 +#define HWIO_GCC_GP3_CMD_RCGR_DIRTY_M_BMSK 0x20 +#define HWIO_GCC_GP3_CMD_RCGR_DIRTY_M_SHFT 0x5 +#define HWIO_GCC_GP3_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_GP3_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_GP3_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_GP3_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_GP3_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_GP3_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_GP3_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_GP3_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_GP3_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GP3_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GP3_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00056008) +#define HWIO_GCC_GP3_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00056008) +#define HWIO_GCC_GP3_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00056008) +#define HWIO_GCC_GP3_CFG_RCGR_RMSK 0x10371f +#define HWIO_GCC_GP3_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_GP3_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_GP3_CFG_RCGR_ADDR, HWIO_GCC_GP3_CFG_RCGR_RMSK) +#define HWIO_GCC_GP3_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_GP3_CFG_RCGR_ADDR, m) +#define HWIO_GCC_GP3_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_GP3_CFG_RCGR_ADDR,v) +#define HWIO_GCC_GP3_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GP3_CFG_RCGR_ADDR,m,v,HWIO_GCC_GP3_CFG_RCGR_IN) +#define HWIO_GCC_GP3_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_GP3_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_GP3_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_GP3_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_GP3_CFG_RCGR_MODE_BMSK 0x3000 +#define HWIO_GCC_GP3_CFG_RCGR_MODE_SHFT 0xc +#define HWIO_GCC_GP3_CFG_RCGR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_GP3_CFG_RCGR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_GP3_CFG_RCGR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_GP3_CFG_RCGR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_GP3_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005600c) +#define HWIO_GCC_GP3_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005600c) +#define HWIO_GCC_GP3_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005600c) +#define HWIO_GCC_GP3_M_RMSK 0xffff +#define HWIO_GCC_GP3_M_ATTR 0x3 +#define HWIO_GCC_GP3_M_IN \ + in_dword_masked(HWIO_GCC_GP3_M_ADDR, HWIO_GCC_GP3_M_RMSK) +#define HWIO_GCC_GP3_M_INM(m) \ + in_dword_masked(HWIO_GCC_GP3_M_ADDR, m) +#define HWIO_GCC_GP3_M_OUT(v) \ + out_dword(HWIO_GCC_GP3_M_ADDR,v) +#define HWIO_GCC_GP3_M_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GP3_M_ADDR,m,v,HWIO_GCC_GP3_M_IN) +#define HWIO_GCC_GP3_M_M_BMSK 0xffff +#define HWIO_GCC_GP3_M_M_SHFT 0x0 + +#define HWIO_GCC_GP3_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00056010) +#define HWIO_GCC_GP3_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00056010) +#define HWIO_GCC_GP3_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00056010) +#define HWIO_GCC_GP3_N_RMSK 0xffff +#define HWIO_GCC_GP3_N_ATTR 0x3 +#define HWIO_GCC_GP3_N_IN \ + in_dword_masked(HWIO_GCC_GP3_N_ADDR, HWIO_GCC_GP3_N_RMSK) +#define HWIO_GCC_GP3_N_INM(m) \ + in_dword_masked(HWIO_GCC_GP3_N_ADDR, m) +#define HWIO_GCC_GP3_N_OUT(v) \ + out_dword(HWIO_GCC_GP3_N_ADDR,v) +#define HWIO_GCC_GP3_N_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GP3_N_ADDR,m,v,HWIO_GCC_GP3_N_IN) +#define HWIO_GCC_GP3_N_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_GP3_N_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_GP3_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00056014) +#define HWIO_GCC_GP3_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00056014) +#define HWIO_GCC_GP3_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00056014) +#define HWIO_GCC_GP3_D_RMSK 0xffff +#define HWIO_GCC_GP3_D_ATTR 0x3 +#define HWIO_GCC_GP3_D_IN \ + in_dword_masked(HWIO_GCC_GP3_D_ADDR, HWIO_GCC_GP3_D_RMSK) +#define HWIO_GCC_GP3_D_INM(m) \ + in_dword_masked(HWIO_GCC_GP3_D_ADDR, m) +#define HWIO_GCC_GP3_D_OUT(v) \ + out_dword(HWIO_GCC_GP3_D_ADDR,v) +#define HWIO_GCC_GP3_D_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GP3_D_ADDR,m,v,HWIO_GCC_GP3_D_IN) +#define HWIO_GCC_GP3_D_NOT_2D_BMSK 0xffff +#define HWIO_GCC_GP3_D_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_PCIE_0_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005b000) +#define HWIO_GCC_PCIE_0_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005b000) +#define HWIO_GCC_PCIE_0_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005b000) +#define HWIO_GCC_PCIE_0_BCR_RMSK 0x1 +#define HWIO_GCC_PCIE_0_BCR_ATTR 0x3 +#define HWIO_GCC_PCIE_0_BCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_0_BCR_ADDR, HWIO_GCC_PCIE_0_BCR_RMSK) +#define HWIO_GCC_PCIE_0_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_0_BCR_ADDR, m) +#define HWIO_GCC_PCIE_0_BCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_0_BCR_ADDR,v) +#define HWIO_GCC_PCIE_0_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_0_BCR_ADDR,m,v,HWIO_GCC_PCIE_0_BCR_IN) +#define HWIO_GCC_PCIE_0_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_PCIE_0_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_PCIE_0_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_0_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005b004) +#define HWIO_GCC_PCIE_0_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005b004) +#define HWIO_GCC_PCIE_0_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005b004) +#define HWIO_GCC_PCIE_0_GDSCR_RMSK 0xf8ffffff +#define HWIO_GCC_PCIE_0_GDSCR_ATTR 0x3 +#define HWIO_GCC_PCIE_0_GDSCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_0_GDSCR_ADDR, HWIO_GCC_PCIE_0_GDSCR_RMSK) +#define HWIO_GCC_PCIE_0_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_0_GDSCR_ADDR, m) +#define HWIO_GCC_PCIE_0_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_0_GDSCR_ADDR,v) +#define HWIO_GCC_PCIE_0_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_0_GDSCR_ADDR,m,v,HWIO_GCC_PCIE_0_GDSCR_IN) +#define HWIO_GCC_PCIE_0_GDSCR_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_PCIE_0_GDSCR_PWR_ON_SHFT 0x1f +#define HWIO_GCC_PCIE_0_GDSCR_GDSC_STATE_BMSK 0x78000000 +#define HWIO_GCC_PCIE_0_GDSCR_GDSC_STATE_SHFT 0x1b +#define HWIO_GCC_PCIE_0_GDSCR_EN_REST_WAIT_BMSK 0xf00000 +#define HWIO_GCC_PCIE_0_GDSCR_EN_REST_WAIT_SHFT 0x14 +#define HWIO_GCC_PCIE_0_GDSCR_EN_FEW_WAIT_BMSK 0xf0000 +#define HWIO_GCC_PCIE_0_GDSCR_EN_FEW_WAIT_SHFT 0x10 +#define HWIO_GCC_PCIE_0_GDSCR_CLK_DIS_WAIT_BMSK 0xf000 +#define HWIO_GCC_PCIE_0_GDSCR_CLK_DIS_WAIT_SHFT 0xc +#define HWIO_GCC_PCIE_0_GDSCR_RETAIN_FF_ENABLE_BMSK 0x800 +#define HWIO_GCC_PCIE_0_GDSCR_RETAIN_FF_ENABLE_SHFT 0xb +#define HWIO_GCC_PCIE_0_GDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_GDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_GDSCR_RESTORE_BMSK 0x400 +#define HWIO_GCC_PCIE_0_GDSCR_RESTORE_SHFT 0xa +#define HWIO_GCC_PCIE_0_GDSCR_RESTORE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_GDSCR_RESTORE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_GDSCR_SAVE_BMSK 0x200 +#define HWIO_GCC_PCIE_0_GDSCR_SAVE_SHFT 0x9 +#define HWIO_GCC_PCIE_0_GDSCR_SAVE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_GDSCR_SAVE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_GDSCR_RETAIN_BMSK 0x100 +#define HWIO_GCC_PCIE_0_GDSCR_RETAIN_SHFT 0x8 +#define HWIO_GCC_PCIE_0_GDSCR_RETAIN_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_GDSCR_RETAIN_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_GDSCR_EN_REST_BMSK 0x80 +#define HWIO_GCC_PCIE_0_GDSCR_EN_REST_SHFT 0x7 +#define HWIO_GCC_PCIE_0_GDSCR_EN_REST_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_GDSCR_EN_REST_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_GDSCR_EN_FEW_BMSK 0x40 +#define HWIO_GCC_PCIE_0_GDSCR_EN_FEW_SHFT 0x6 +#define HWIO_GCC_PCIE_0_GDSCR_EN_FEW_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_GDSCR_EN_FEW_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_GDSCR_CLAMP_IO_BMSK 0x20 +#define HWIO_GCC_PCIE_0_GDSCR_CLAMP_IO_SHFT 0x5 +#define HWIO_GCC_PCIE_0_GDSCR_CLAMP_IO_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_GDSCR_CLAMP_IO_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_GDSCR_CLK_DISABLE_BMSK 0x10 +#define HWIO_GCC_PCIE_0_GDSCR_CLK_DISABLE_SHFT 0x4 +#define HWIO_GCC_PCIE_0_GDSCR_CLK_DISABLE_CLK_NOT_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_GDSCR_CLK_DISABLE_CLK_IS_DISABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_GDSCR_PD_ARES_BMSK 0x8 +#define HWIO_GCC_PCIE_0_GDSCR_PD_ARES_SHFT 0x3 +#define HWIO_GCC_PCIE_0_GDSCR_PD_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_PCIE_0_GDSCR_PD_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_PCIE_0_GDSCR_SW_OVERRIDE_BMSK 0x4 +#define HWIO_GCC_PCIE_0_GDSCR_SW_OVERRIDE_SHFT 0x2 +#define HWIO_GCC_PCIE_0_GDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_GDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_GDSCR_HW_CONTROL_BMSK 0x2 +#define HWIO_GCC_PCIE_0_GDSCR_HW_CONTROL_SHFT 0x1 +#define HWIO_GCC_PCIE_0_GDSCR_HW_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_GDSCR_HW_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_GDSCR_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_PCIE_0_GDSCR_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_PCIE_0_GDSCR_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_GDSCR_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_0_CFG_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005b008) +#define HWIO_GCC_PCIE_0_CFG_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005b008) +#define HWIO_GCC_PCIE_0_CFG_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005b008) +#define HWIO_GCC_PCIE_0_CFG_GDSCR_RMSK 0x7ffffff +#define HWIO_GCC_PCIE_0_CFG_GDSCR_ATTR 0x3 +#define HWIO_GCC_PCIE_0_CFG_GDSCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_0_CFG_GDSCR_ADDR, HWIO_GCC_PCIE_0_CFG_GDSCR_RMSK) +#define HWIO_GCC_PCIE_0_CFG_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_0_CFG_GDSCR_ADDR, m) +#define HWIO_GCC_PCIE_0_CFG_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_0_CFG_GDSCR_ADDR,v) +#define HWIO_GCC_PCIE_0_CFG_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_0_CFG_GDSCR_ADDR,m,v,HWIO_GCC_PCIE_0_CFG_GDSCR_IN) +#define HWIO_GCC_PCIE_0_CFG_GDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4000000 +#define HWIO_GCC_PCIE_0_CFG_GDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x1a +#define HWIO_GCC_PCIE_0_CFG_GDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_CFG_GDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_CFG_GDSCR_GDSC_PWR_DWN_START_BMSK 0x2000000 +#define HWIO_GCC_PCIE_0_CFG_GDSCR_GDSC_PWR_DWN_START_SHFT 0x19 +#define HWIO_GCC_PCIE_0_CFG_GDSCR_GDSC_PWR_UP_START_BMSK 0x1000000 +#define HWIO_GCC_PCIE_0_CFG_GDSCR_GDSC_PWR_UP_START_SHFT 0x18 +#define HWIO_GCC_PCIE_0_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_BMSK 0xf00000 +#define HWIO_GCC_PCIE_0_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_SHFT 0x14 +#define HWIO_GCC_PCIE_0_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_BMSK 0x80000 +#define HWIO_GCC_PCIE_0_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_SHFT 0x13 +#define HWIO_GCC_PCIE_0_CFG_GDSCR_GDSC_ENR_ACK_STATUS_BMSK 0x40000 +#define HWIO_GCC_PCIE_0_CFG_GDSCR_GDSC_ENR_ACK_STATUS_SHFT 0x12 +#define HWIO_GCC_PCIE_0_CFG_GDSCR_GDSC_ENF_ACK_STATUS_BMSK 0x20000 +#define HWIO_GCC_PCIE_0_CFG_GDSCR_GDSC_ENF_ACK_STATUS_SHFT 0x11 +#define HWIO_GCC_PCIE_0_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_BMSK 0x10000 +#define HWIO_GCC_PCIE_0_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_SHFT 0x10 +#define HWIO_GCC_PCIE_0_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_BMSK 0x8000 +#define HWIO_GCC_PCIE_0_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_SHFT 0xf +#define HWIO_GCC_PCIE_0_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_BMSK 0x7800 +#define HWIO_GCC_PCIE_0_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_SHFT 0xb +#define HWIO_GCC_PCIE_0_CFG_GDSCR_GDSC_HANDSHAKE_DIS_BMSK 0x400 +#define HWIO_GCC_PCIE_0_CFG_GDSCR_GDSC_HANDSHAKE_DIS_SHFT 0xa +#define HWIO_GCC_PCIE_0_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_BMSK 0x200 +#define HWIO_GCC_PCIE_0_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_SHFT 0x9 +#define HWIO_GCC_PCIE_0_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_BMSK 0x100 +#define HWIO_GCC_PCIE_0_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_SHFT 0x8 +#define HWIO_GCC_PCIE_0_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_BMSK 0x80 +#define HWIO_GCC_PCIE_0_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_SHFT 0x7 +#define HWIO_GCC_PCIE_0_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_BMSK 0x60 +#define HWIO_GCC_PCIE_0_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_SHFT 0x5 +#define HWIO_GCC_PCIE_0_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_BMSK 0x10 +#define HWIO_GCC_PCIE_0_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_SHFT 0x4 +#define HWIO_GCC_PCIE_0_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_BMSK 0x8 +#define HWIO_GCC_PCIE_0_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_SHFT 0x3 +#define HWIO_GCC_PCIE_0_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_BMSK 0x4 +#define HWIO_GCC_PCIE_0_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_SHFT 0x2 +#define HWIO_GCC_PCIE_0_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_BMSK 0x2 +#define HWIO_GCC_PCIE_0_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_SHFT 0x1 +#define HWIO_GCC_PCIE_0_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_PCIE_0_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_SHFT 0x0 + +#define HWIO_GCC_PCIE_0_CFG2_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005b00c) +#define HWIO_GCC_PCIE_0_CFG2_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005b00c) +#define HWIO_GCC_PCIE_0_CFG2_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005b00c) +#define HWIO_GCC_PCIE_0_CFG2_GDSCR_RMSK 0x7ffff +#define HWIO_GCC_PCIE_0_CFG2_GDSCR_ATTR 0x3 +#define HWIO_GCC_PCIE_0_CFG2_GDSCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_0_CFG2_GDSCR_ADDR, HWIO_GCC_PCIE_0_CFG2_GDSCR_RMSK) +#define HWIO_GCC_PCIE_0_CFG2_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_0_CFG2_GDSCR_ADDR, m) +#define HWIO_GCC_PCIE_0_CFG2_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_0_CFG2_GDSCR_ADDR,v) +#define HWIO_GCC_PCIE_0_CFG2_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_0_CFG2_GDSCR_ADDR,m,v,HWIO_GCC_PCIE_0_CFG2_GDSCR_IN) +#define HWIO_GCC_PCIE_0_CFG2_GDSCR_GDSC_MEM_PWRUP_ACK_OVERRIDE_BMSK 0x40000 +#define HWIO_GCC_PCIE_0_CFG2_GDSCR_GDSC_MEM_PWRUP_ACK_OVERRIDE_SHFT 0x12 +#define HWIO_GCC_PCIE_0_CFG2_GDSCR_GDSC_PWRDWN_ENABLE_ACK_OVERRIDE_BMSK 0x20000 +#define HWIO_GCC_PCIE_0_CFG2_GDSCR_GDSC_PWRDWN_ENABLE_ACK_OVERRIDE_SHFT 0x11 +#define HWIO_GCC_PCIE_0_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_BMSK 0x10000 +#define HWIO_GCC_PCIE_0_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_SHFT 0x10 +#define HWIO_GCC_PCIE_0_CFG2_GDSCR_DLY_MEM_PWR_UP_BMSK 0xf000 +#define HWIO_GCC_PCIE_0_CFG2_GDSCR_DLY_MEM_PWR_UP_SHFT 0xc +#define HWIO_GCC_PCIE_0_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_BMSK 0xf00 +#define HWIO_GCC_PCIE_0_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_SHFT 0x8 +#define HWIO_GCC_PCIE_0_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_BMSK 0xf0 +#define HWIO_GCC_PCIE_0_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_SHFT 0x4 +#define HWIO_GCC_PCIE_0_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_BMSK 0xf +#define HWIO_GCC_PCIE_0_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_SHFT 0x0 + +#define HWIO_GCC_PCIE_0_CFG3_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005b010) +#define HWIO_GCC_PCIE_0_CFG3_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005b010) +#define HWIO_GCC_PCIE_0_CFG3_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005b010) +#define HWIO_GCC_PCIE_0_CFG3_GDSCR_RMSK 0x7ffffff +#define HWIO_GCC_PCIE_0_CFG3_GDSCR_ATTR 0x3 +#define HWIO_GCC_PCIE_0_CFG3_GDSCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_0_CFG3_GDSCR_ADDR, HWIO_GCC_PCIE_0_CFG3_GDSCR_RMSK) +#define HWIO_GCC_PCIE_0_CFG3_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_0_CFG3_GDSCR_ADDR, m) +#define HWIO_GCC_PCIE_0_CFG3_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_0_CFG3_GDSCR_ADDR,v) +#define HWIO_GCC_PCIE_0_CFG3_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_0_CFG3_GDSCR_ADDR,m,v,HWIO_GCC_PCIE_0_CFG3_GDSCR_IN) +#define HWIO_GCC_PCIE_0_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_STATUS_BMSK 0x4000000 +#define HWIO_GCC_PCIE_0_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_STATUS_SHFT 0x1a +#define HWIO_GCC_PCIE_0_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_BMSK 0x2000000 +#define HWIO_GCC_PCIE_0_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_SHFT 0x19 +#define HWIO_GCC_PCIE_0_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_CFG3_GDSCR_DLY_ACCU_RED_SHIFTER_DONE_BMSK 0x1e00000 +#define HWIO_GCC_PCIE_0_CFG3_GDSCR_DLY_ACCU_RED_SHIFTER_DONE_SHFT 0x15 +#define HWIO_GCC_PCIE_0_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_BMSK 0x100000 +#define HWIO_GCC_PCIE_0_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_SHFT 0x14 +#define HWIO_GCC_PCIE_0_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_BMSK 0x80000 +#define HWIO_GCC_PCIE_0_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_SHFT 0x13 +#define HWIO_GCC_PCIE_0_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_BMSK 0x40000 +#define HWIO_GCC_PCIE_0_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_SHFT 0x12 +#define HWIO_GCC_PCIE_0_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_BMSK 0x20000 +#define HWIO_GCC_PCIE_0_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_SHFT 0x11 +#define HWIO_GCC_PCIE_0_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_BMSK 0x10000 +#define HWIO_GCC_PCIE_0_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_SHFT 0x10 +#define HWIO_GCC_PCIE_0_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_CFG3_GDSCR_GDSC_SPARE_CTRL_IN_BMSK 0xff00 +#define HWIO_GCC_PCIE_0_CFG3_GDSCR_GDSC_SPARE_CTRL_IN_SHFT 0x8 +#define HWIO_GCC_PCIE_0_CFG3_GDSCR_GDSC_SPARE_CTRL_OUT_BMSK 0xff +#define HWIO_GCC_PCIE_0_CFG3_GDSCR_GDSC_SPARE_CTRL_OUT_SHFT 0x0 + +#define HWIO_GCC_PCIE_0_CFG4_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005b014) +#define HWIO_GCC_PCIE_0_CFG4_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005b014) +#define HWIO_GCC_PCIE_0_CFG4_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005b014) +#define HWIO_GCC_PCIE_0_CFG4_GDSCR_RMSK 0xffffff +#define HWIO_GCC_PCIE_0_CFG4_GDSCR_ATTR 0x3 +#define HWIO_GCC_PCIE_0_CFG4_GDSCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_0_CFG4_GDSCR_ADDR, HWIO_GCC_PCIE_0_CFG4_GDSCR_RMSK) +#define HWIO_GCC_PCIE_0_CFG4_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_0_CFG4_GDSCR_ADDR, m) +#define HWIO_GCC_PCIE_0_CFG4_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_0_CFG4_GDSCR_ADDR,v) +#define HWIO_GCC_PCIE_0_CFG4_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_0_CFG4_GDSCR_ADDR,m,v,HWIO_GCC_PCIE_0_CFG4_GDSCR_IN) +#define HWIO_GCC_PCIE_0_CFG4_GDSCR_DLY_UNCLAMPIO_BMSK 0xf00000 +#define HWIO_GCC_PCIE_0_CFG4_GDSCR_DLY_UNCLAMPIO_SHFT 0x14 +#define HWIO_GCC_PCIE_0_CFG4_GDSCR_DLY_RESTOREFF_BMSK 0xf0000 +#define HWIO_GCC_PCIE_0_CFG4_GDSCR_DLY_RESTOREFF_SHFT 0x10 +#define HWIO_GCC_PCIE_0_CFG4_GDSCR_DLY_NORETAINFF_BMSK 0xf000 +#define HWIO_GCC_PCIE_0_CFG4_GDSCR_DLY_NORETAINFF_SHFT 0xc +#define HWIO_GCC_PCIE_0_CFG4_GDSCR_DLY_DEASSERTARES_BMSK 0xf00 +#define HWIO_GCC_PCIE_0_CFG4_GDSCR_DLY_DEASSERTARES_SHFT 0x8 +#define HWIO_GCC_PCIE_0_CFG4_GDSCR_DLY_CLAMPIO_BMSK 0xf0 +#define HWIO_GCC_PCIE_0_CFG4_GDSCR_DLY_CLAMPIO_SHFT 0x4 +#define HWIO_GCC_PCIE_0_CFG4_GDSCR_DLY_RETAINFF_BMSK 0xf +#define HWIO_GCC_PCIE_0_CFG4_GDSCR_DLY_RETAINFF_SHFT 0x0 + +#define HWIO_GCC_QMIP_PCIE_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005b018) +#define HWIO_GCC_QMIP_PCIE_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005b018) +#define HWIO_GCC_QMIP_PCIE_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005b018) +#define HWIO_GCC_QMIP_PCIE_AHB_CBCR_RMSK 0x81d0000e +#define HWIO_GCC_QMIP_PCIE_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_QMIP_PCIE_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_QMIP_PCIE_AHB_CBCR_ADDR, HWIO_GCC_QMIP_PCIE_AHB_CBCR_RMSK) +#define HWIO_GCC_QMIP_PCIE_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QMIP_PCIE_AHB_CBCR_ADDR, m) +#define HWIO_GCC_QMIP_PCIE_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QMIP_PCIE_AHB_CBCR_ADDR,v) +#define HWIO_GCC_QMIP_PCIE_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QMIP_PCIE_AHB_CBCR_ADDR,m,v,HWIO_GCC_QMIP_PCIE_AHB_CBCR_IN) +#define HWIO_GCC_QMIP_PCIE_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QMIP_PCIE_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QMIP_PCIE_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QMIP_PCIE_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QMIP_PCIE_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QMIP_PCIE_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QMIP_PCIE_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QMIP_PCIE_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QMIP_PCIE_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_QMIP_PCIE_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_QMIP_PCIE_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_QMIP_PCIE_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_QMIP_PCIE_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QMIP_PCIE_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QMIP_PCIE_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QMIP_PCIE_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_QMIP_PCIE_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_QMIP_PCIE_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_QMIP_PCIE_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QMIP_PCIE_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_0_SLV_Q2A_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005b01c) +#define HWIO_GCC_PCIE_0_SLV_Q2A_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005b01c) +#define HWIO_GCC_PCIE_0_SLV_Q2A_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005b01c) +#define HWIO_GCC_PCIE_0_SLV_Q2A_AXI_CBCR_RMSK 0x81d00004 +#define HWIO_GCC_PCIE_0_SLV_Q2A_AXI_CBCR_ATTR 0x3 +#define HWIO_GCC_PCIE_0_SLV_Q2A_AXI_CBCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_0_SLV_Q2A_AXI_CBCR_ADDR, HWIO_GCC_PCIE_0_SLV_Q2A_AXI_CBCR_RMSK) +#define HWIO_GCC_PCIE_0_SLV_Q2A_AXI_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_0_SLV_Q2A_AXI_CBCR_ADDR, m) +#define HWIO_GCC_PCIE_0_SLV_Q2A_AXI_CBCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_0_SLV_Q2A_AXI_CBCR_ADDR,v) +#define HWIO_GCC_PCIE_0_SLV_Q2A_AXI_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_0_SLV_Q2A_AXI_CBCR_ADDR,m,v,HWIO_GCC_PCIE_0_SLV_Q2A_AXI_CBCR_IN) +#define HWIO_GCC_PCIE_0_SLV_Q2A_AXI_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_PCIE_0_SLV_Q2A_AXI_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_PCIE_0_SLV_Q2A_AXI_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_PCIE_0_SLV_Q2A_AXI_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_PCIE_0_SLV_Q2A_AXI_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_PCIE_0_SLV_Q2A_AXI_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_PCIE_0_SLV_Q2A_AXI_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_PCIE_0_SLV_Q2A_AXI_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_PCIE_0_SLV_Q2A_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_PCIE_0_SLV_Q2A_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_PCIE_0_SLV_Q2A_AXI_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_PCIE_0_SLV_Q2A_AXI_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_PCIE_0_SLV_Q2A_AXI_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_PCIE_0_SLV_Q2A_AXI_CBCR_CLK_ARES_RESET_FVAL 0x1 + +#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005b020) +#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005b020) +#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005b020) +#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_RMSK 0x81d0700e +#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_ATTR 0x3 +#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_0_SLV_AXI_CBCR_ADDR, HWIO_GCC_PCIE_0_SLV_AXI_CBCR_RMSK) +#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_0_SLV_AXI_CBCR_ADDR, m) +#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_0_SLV_AXI_CBCR_ADDR,v) +#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_0_SLV_AXI_CBCR_ADDR,m,v,HWIO_GCC_PCIE_0_SLV_AXI_CBCR_IN) +#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_HW_CTL_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005b024) +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005b024) +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005b024) +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_RMSK 0xf1ffffe +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_ATTR 0x3 +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_IN \ + in_dword_masked(HWIO_GCC_PCIE_0_SLV_AXI_SREGR_ADDR, HWIO_GCC_PCIE_0_SLV_AXI_SREGR_RMSK) +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_0_SLV_AXI_SREGR_ADDR, m) +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_0_SLV_AXI_SREGR_ADDR,v) +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_0_SLV_AXI_SREGR_ADDR,m,v,HWIO_GCC_PCIE_0_SLV_AXI_SREGR_IN) +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xf000000 +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_PWR_FSM_CLK_SEL_BMSK 0x100000 +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_PWR_FSM_CLK_SEL_SHFT 0x14 +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xf0000 +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_0_SLV_AXI_CFG_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005b028) +#define HWIO_GCC_PCIE_0_SLV_AXI_CFG_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005b028) +#define HWIO_GCC_PCIE_0_SLV_AXI_CFG_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005b028) +#define HWIO_GCC_PCIE_0_SLV_AXI_CFG_SREGR_RMSK 0xffffffff +#define HWIO_GCC_PCIE_0_SLV_AXI_CFG_SREGR_ATTR 0x3 +#define HWIO_GCC_PCIE_0_SLV_AXI_CFG_SREGR_IN \ + in_dword_masked(HWIO_GCC_PCIE_0_SLV_AXI_CFG_SREGR_ADDR, HWIO_GCC_PCIE_0_SLV_AXI_CFG_SREGR_RMSK) +#define HWIO_GCC_PCIE_0_SLV_AXI_CFG_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_0_SLV_AXI_CFG_SREGR_ADDR, m) +#define HWIO_GCC_PCIE_0_SLV_AXI_CFG_SREGR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_0_SLV_AXI_CFG_SREGR_ADDR,v) +#define HWIO_GCC_PCIE_0_SLV_AXI_CFG_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_0_SLV_AXI_CFG_SREGR_ADDR,m,v,HWIO_GCC_PCIE_0_SLV_AXI_CFG_SREGR_IN) +#define HWIO_GCC_PCIE_0_SLV_AXI_CFG_SREGR_MEM_CORE_OFF_TIMER_BMSK 0xfc000000 +#define HWIO_GCC_PCIE_0_SLV_AXI_CFG_SREGR_MEM_CORE_OFF_TIMER_SHFT 0x1a +#define HWIO_GCC_PCIE_0_SLV_AXI_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_BMSK 0x2000000 +#define HWIO_GCC_PCIE_0_SLV_AXI_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_SHFT 0x19 +#define HWIO_GCC_PCIE_0_SLV_AXI_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_BMSK 0x1000000 +#define HWIO_GCC_PCIE_0_SLV_AXI_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_SHFT 0x18 +#define HWIO_GCC_PCIE_0_SLV_AXI_CFG_SREGR_MEM_PERIPH_ON_STATUS_BMSK 0x800000 +#define HWIO_GCC_PCIE_0_SLV_AXI_CFG_SREGR_MEM_PERIPH_ON_STATUS_SHFT 0x17 +#define HWIO_GCC_PCIE_0_SLV_AXI_CFG_SREGR_MEM_CORE_ON_STATUS_BMSK 0x400000 +#define HWIO_GCC_PCIE_0_SLV_AXI_CFG_SREGR_MEM_CORE_ON_STATUS_SHFT 0x16 +#define HWIO_GCC_PCIE_0_SLV_AXI_CFG_SREGR_MEM_CPH_TIMER_BMSK 0x3f0000 +#define HWIO_GCC_PCIE_0_SLV_AXI_CFG_SREGR_MEM_CPH_TIMER_SHFT 0x10 +#define HWIO_GCC_PCIE_0_SLV_AXI_CFG_SREGR_SLEEP_TIMER_BMSK 0xff00 +#define HWIO_GCC_PCIE_0_SLV_AXI_CFG_SREGR_SLEEP_TIMER_SHFT 0x8 +#define HWIO_GCC_PCIE_0_SLV_AXI_CFG_SREGR_WAKEUP_TIMER_BMSK 0xff +#define HWIO_GCC_PCIE_0_SLV_AXI_CFG_SREGR_WAKEUP_TIMER_SHFT 0x0 + +#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005b02c) +#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005b02c) +#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005b02c) +#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_RMSK 0x81f0700e +#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_ATTR 0x3 +#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_ADDR, HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_RMSK) +#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_ADDR, m) +#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_ADDR,v) +#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_ADDR,m,v,HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_IN) +#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_IGNORE_PMU_CLK_DIS_BMSK 0x200000 +#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_IGNORE_PMU_CLK_DIS_SHFT 0x15 +#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_HW_CTL_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005b030) +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005b030) +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005b030) +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_RMSK 0xf1ffffe +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_ATTR 0x3 +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_IN \ + in_dword_masked(HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_ADDR, HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_RMSK) +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_ADDR, m) +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_ADDR,v) +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_ADDR,m,v,HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_IN) +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xf000000 +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_PWR_FSM_CLK_SEL_BMSK 0x100000 +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_PWR_FSM_CLK_SEL_SHFT 0x14 +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xf0000 +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_0_MSTR_AXI_CFG_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005b034) +#define HWIO_GCC_PCIE_0_MSTR_AXI_CFG_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005b034) +#define HWIO_GCC_PCIE_0_MSTR_AXI_CFG_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005b034) +#define HWIO_GCC_PCIE_0_MSTR_AXI_CFG_SREGR_RMSK 0xffffffff +#define HWIO_GCC_PCIE_0_MSTR_AXI_CFG_SREGR_ATTR 0x3 +#define HWIO_GCC_PCIE_0_MSTR_AXI_CFG_SREGR_IN \ + in_dword_masked(HWIO_GCC_PCIE_0_MSTR_AXI_CFG_SREGR_ADDR, HWIO_GCC_PCIE_0_MSTR_AXI_CFG_SREGR_RMSK) +#define HWIO_GCC_PCIE_0_MSTR_AXI_CFG_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_0_MSTR_AXI_CFG_SREGR_ADDR, m) +#define HWIO_GCC_PCIE_0_MSTR_AXI_CFG_SREGR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_0_MSTR_AXI_CFG_SREGR_ADDR,v) +#define HWIO_GCC_PCIE_0_MSTR_AXI_CFG_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_0_MSTR_AXI_CFG_SREGR_ADDR,m,v,HWIO_GCC_PCIE_0_MSTR_AXI_CFG_SREGR_IN) +#define HWIO_GCC_PCIE_0_MSTR_AXI_CFG_SREGR_MEM_CORE_OFF_TIMER_BMSK 0xfc000000 +#define HWIO_GCC_PCIE_0_MSTR_AXI_CFG_SREGR_MEM_CORE_OFF_TIMER_SHFT 0x1a +#define HWIO_GCC_PCIE_0_MSTR_AXI_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_BMSK 0x2000000 +#define HWIO_GCC_PCIE_0_MSTR_AXI_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_SHFT 0x19 +#define HWIO_GCC_PCIE_0_MSTR_AXI_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_BMSK 0x1000000 +#define HWIO_GCC_PCIE_0_MSTR_AXI_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_SHFT 0x18 +#define HWIO_GCC_PCIE_0_MSTR_AXI_CFG_SREGR_MEM_PERIPH_ON_STATUS_BMSK 0x800000 +#define HWIO_GCC_PCIE_0_MSTR_AXI_CFG_SREGR_MEM_PERIPH_ON_STATUS_SHFT 0x17 +#define HWIO_GCC_PCIE_0_MSTR_AXI_CFG_SREGR_MEM_CORE_ON_STATUS_BMSK 0x400000 +#define HWIO_GCC_PCIE_0_MSTR_AXI_CFG_SREGR_MEM_CORE_ON_STATUS_SHFT 0x16 +#define HWIO_GCC_PCIE_0_MSTR_AXI_CFG_SREGR_MEM_CPH_TIMER_BMSK 0x3f0000 +#define HWIO_GCC_PCIE_0_MSTR_AXI_CFG_SREGR_MEM_CPH_TIMER_SHFT 0x10 +#define HWIO_GCC_PCIE_0_MSTR_AXI_CFG_SREGR_SLEEP_TIMER_BMSK 0xff00 +#define HWIO_GCC_PCIE_0_MSTR_AXI_CFG_SREGR_SLEEP_TIMER_SHFT 0x8 +#define HWIO_GCC_PCIE_0_MSTR_AXI_CFG_SREGR_WAKEUP_TIMER_BMSK 0xff +#define HWIO_GCC_PCIE_0_MSTR_AXI_CFG_SREGR_WAKEUP_TIMER_SHFT 0x0 + +#define HWIO_GCC_PCIE_0_CFG_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005b038) +#define HWIO_GCC_PCIE_0_CFG_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005b038) +#define HWIO_GCC_PCIE_0_CFG_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005b038) +#define HWIO_GCC_PCIE_0_CFG_AHB_CBCR_RMSK 0x81d0000e +#define HWIO_GCC_PCIE_0_CFG_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_PCIE_0_CFG_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_0_CFG_AHB_CBCR_ADDR, HWIO_GCC_PCIE_0_CFG_AHB_CBCR_RMSK) +#define HWIO_GCC_PCIE_0_CFG_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_0_CFG_AHB_CBCR_ADDR, m) +#define HWIO_GCC_PCIE_0_CFG_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_0_CFG_AHB_CBCR_ADDR,v) +#define HWIO_GCC_PCIE_0_CFG_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_0_CFG_AHB_CBCR_ADDR,m,v,HWIO_GCC_PCIE_0_CFG_AHB_CBCR_IN) +#define HWIO_GCC_PCIE_0_CFG_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_PCIE_0_CFG_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_PCIE_0_CFG_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_PCIE_0_CFG_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_PCIE_0_CFG_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_PCIE_0_CFG_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_PCIE_0_CFG_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_PCIE_0_CFG_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_PCIE_0_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_PCIE_0_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_PCIE_0_CFG_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_PCIE_0_CFG_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_PCIE_0_CFG_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_PCIE_0_CFG_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_PCIE_0_CFG_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_PCIE_0_CFG_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_PCIE_0_CFG_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_PCIE_0_CFG_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_PCIE_0_CFG_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_CFG_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_0_AUX_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005b03c) +#define HWIO_GCC_PCIE_0_AUX_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005b03c) +#define HWIO_GCC_PCIE_0_AUX_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005b03c) +#define HWIO_GCC_PCIE_0_AUX_CBCR_RMSK 0x81c07004 +#define HWIO_GCC_PCIE_0_AUX_CBCR_ATTR 0x3 +#define HWIO_GCC_PCIE_0_AUX_CBCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_0_AUX_CBCR_ADDR, HWIO_GCC_PCIE_0_AUX_CBCR_RMSK) +#define HWIO_GCC_PCIE_0_AUX_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_0_AUX_CBCR_ADDR, m) +#define HWIO_GCC_PCIE_0_AUX_CBCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_0_AUX_CBCR_ADDR,v) +#define HWIO_GCC_PCIE_0_AUX_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_0_AUX_CBCR_ADDR,m,v,HWIO_GCC_PCIE_0_AUX_CBCR_IN) +#define HWIO_GCC_PCIE_0_AUX_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_PCIE_0_AUX_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_PCIE_0_AUX_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_PCIE_0_AUX_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_PCIE_0_AUX_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_PCIE_0_AUX_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_PCIE_0_AUX_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_PCIE_0_AUX_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_PCIE_0_AUX_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_PCIE_0_AUX_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_PCIE_0_AUX_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_AUX_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_AUX_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_PCIE_0_AUX_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_PCIE_0_AUX_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_AUX_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_AUX_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_PCIE_0_AUX_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_PCIE_0_AUX_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_AUX_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_AUX_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_PCIE_0_AUX_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_PCIE_0_AUX_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_PCIE_0_AUX_CBCR_CLK_ARES_RESET_FVAL 0x1 + +#define HWIO_GCC_PCIE_0_AUX_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005b040) +#define HWIO_GCC_PCIE_0_AUX_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005b040) +#define HWIO_GCC_PCIE_0_AUX_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005b040) +#define HWIO_GCC_PCIE_0_AUX_SREGR_RMSK 0xf1ffffe +#define HWIO_GCC_PCIE_0_AUX_SREGR_ATTR 0x3 +#define HWIO_GCC_PCIE_0_AUX_SREGR_IN \ + in_dword_masked(HWIO_GCC_PCIE_0_AUX_SREGR_ADDR, HWIO_GCC_PCIE_0_AUX_SREGR_RMSK) +#define HWIO_GCC_PCIE_0_AUX_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_0_AUX_SREGR_ADDR, m) +#define HWIO_GCC_PCIE_0_AUX_SREGR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_0_AUX_SREGR_ADDR,v) +#define HWIO_GCC_PCIE_0_AUX_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_0_AUX_SREGR_ADDR,m,v,HWIO_GCC_PCIE_0_AUX_SREGR_IN) +#define HWIO_GCC_PCIE_0_AUX_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xf000000 +#define HWIO_GCC_PCIE_0_AUX_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_PCIE_0_AUX_SREGR_PWR_FSM_CLK_SEL_BMSK 0x100000 +#define HWIO_GCC_PCIE_0_AUX_SREGR_PWR_FSM_CLK_SEL_SHFT 0x14 +#define HWIO_GCC_PCIE_0_AUX_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xf0000 +#define HWIO_GCC_PCIE_0_AUX_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_PCIE_0_AUX_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_PCIE_0_AUX_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_PCIE_0_AUX_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_AUX_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_AUX_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_PCIE_0_AUX_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_PCIE_0_AUX_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_AUX_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_AUX_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_PCIE_0_AUX_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_PCIE_0_AUX_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_AUX_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_AUX_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_PCIE_0_AUX_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_PCIE_0_AUX_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_PCIE_0_AUX_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_PCIE_0_AUX_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_PCIE_0_AUX_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_PCIE_0_AUX_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_PCIE_0_AUX_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_PCIE_0_AUX_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_PCIE_0_AUX_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_PCIE_0_AUX_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_PCIE_0_AUX_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_PCIE_0_AUX_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_PCIE_0_AUX_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_PCIE_0_AUX_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_PCIE_0_AUX_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_PCIE_0_AUX_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_AUX_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_AUX_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_PCIE_0_AUX_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_PCIE_0_AUX_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_AUX_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_AUX_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_PCIE_0_AUX_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_PCIE_0_AUX_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_PCIE_0_AUX_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_PCIE_0_AUX_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_PCIE_0_AUX_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_PCIE_0_AUX_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_PCIE_0_AUX_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_PCIE_0_AUX_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_PCIE_0_AUX_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_PCIE_0_AUX_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_PCIE_0_AUX_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_PCIE_0_AUX_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_PCIE_0_AUX_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_PCIE_0_AUX_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_PCIE_0_AUX_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_PCIE_0_AUX_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_PCIE_0_AUX_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_PCIE_0_AUX_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_AUX_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_0_AUX_CFG_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005b044) +#define HWIO_GCC_PCIE_0_AUX_CFG_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005b044) +#define HWIO_GCC_PCIE_0_AUX_CFG_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005b044) +#define HWIO_GCC_PCIE_0_AUX_CFG_SREGR_RMSK 0xffffffff +#define HWIO_GCC_PCIE_0_AUX_CFG_SREGR_ATTR 0x3 +#define HWIO_GCC_PCIE_0_AUX_CFG_SREGR_IN \ + in_dword_masked(HWIO_GCC_PCIE_0_AUX_CFG_SREGR_ADDR, HWIO_GCC_PCIE_0_AUX_CFG_SREGR_RMSK) +#define HWIO_GCC_PCIE_0_AUX_CFG_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_0_AUX_CFG_SREGR_ADDR, m) +#define HWIO_GCC_PCIE_0_AUX_CFG_SREGR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_0_AUX_CFG_SREGR_ADDR,v) +#define HWIO_GCC_PCIE_0_AUX_CFG_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_0_AUX_CFG_SREGR_ADDR,m,v,HWIO_GCC_PCIE_0_AUX_CFG_SREGR_IN) +#define HWIO_GCC_PCIE_0_AUX_CFG_SREGR_MEM_CORE_OFF_TIMER_BMSK 0xfc000000 +#define HWIO_GCC_PCIE_0_AUX_CFG_SREGR_MEM_CORE_OFF_TIMER_SHFT 0x1a +#define HWIO_GCC_PCIE_0_AUX_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_BMSK 0x2000000 +#define HWIO_GCC_PCIE_0_AUX_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_SHFT 0x19 +#define HWIO_GCC_PCIE_0_AUX_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_BMSK 0x1000000 +#define HWIO_GCC_PCIE_0_AUX_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_SHFT 0x18 +#define HWIO_GCC_PCIE_0_AUX_CFG_SREGR_MEM_PERIPH_ON_STATUS_BMSK 0x800000 +#define HWIO_GCC_PCIE_0_AUX_CFG_SREGR_MEM_PERIPH_ON_STATUS_SHFT 0x17 +#define HWIO_GCC_PCIE_0_AUX_CFG_SREGR_MEM_CORE_ON_STATUS_BMSK 0x400000 +#define HWIO_GCC_PCIE_0_AUX_CFG_SREGR_MEM_CORE_ON_STATUS_SHFT 0x16 +#define HWIO_GCC_PCIE_0_AUX_CFG_SREGR_MEM_CPH_TIMER_BMSK 0x3f0000 +#define HWIO_GCC_PCIE_0_AUX_CFG_SREGR_MEM_CPH_TIMER_SHFT 0x10 +#define HWIO_GCC_PCIE_0_AUX_CFG_SREGR_SLEEP_TIMER_BMSK 0xff00 +#define HWIO_GCC_PCIE_0_AUX_CFG_SREGR_SLEEP_TIMER_SHFT 0x8 +#define HWIO_GCC_PCIE_0_AUX_CFG_SREGR_WAKEUP_TIMER_BMSK 0xff +#define HWIO_GCC_PCIE_0_AUX_CFG_SREGR_WAKEUP_TIMER_SHFT 0x0 + +#define HWIO_GCC_PCIE_0_PIPE_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005b048) +#define HWIO_GCC_PCIE_0_PIPE_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005b048) +#define HWIO_GCC_PCIE_0_PIPE_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005b048) +#define HWIO_GCC_PCIE_0_PIPE_CBCR_RMSK 0x81c07004 +#define HWIO_GCC_PCIE_0_PIPE_CBCR_ATTR 0x3 +#define HWIO_GCC_PCIE_0_PIPE_CBCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_0_PIPE_CBCR_ADDR, HWIO_GCC_PCIE_0_PIPE_CBCR_RMSK) +#define HWIO_GCC_PCIE_0_PIPE_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_0_PIPE_CBCR_ADDR, m) +#define HWIO_GCC_PCIE_0_PIPE_CBCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_0_PIPE_CBCR_ADDR,v) +#define HWIO_GCC_PCIE_0_PIPE_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_0_PIPE_CBCR_ADDR,m,v,HWIO_GCC_PCIE_0_PIPE_CBCR_IN) +#define HWIO_GCC_PCIE_0_PIPE_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_PCIE_0_PIPE_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_PCIE_0_PIPE_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_PCIE_0_PIPE_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_PCIE_0_PIPE_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_PCIE_0_PIPE_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_PCIE_0_PIPE_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_PCIE_0_PIPE_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_PCIE_0_PIPE_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_PCIE_0_PIPE_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_PCIE_0_PIPE_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_PIPE_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_PIPE_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_PCIE_0_PIPE_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_PCIE_0_PIPE_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_PIPE_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_PIPE_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_PCIE_0_PIPE_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_PCIE_0_PIPE_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_PIPE_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_PIPE_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_PCIE_0_PIPE_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_PCIE_0_PIPE_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_PCIE_0_PIPE_CBCR_CLK_ARES_RESET_FVAL 0x1 + +#define HWIO_GCC_PCIE_0_PIPE_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005b04c) +#define HWIO_GCC_PCIE_0_PIPE_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005b04c) +#define HWIO_GCC_PCIE_0_PIPE_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005b04c) +#define HWIO_GCC_PCIE_0_PIPE_SREGR_RMSK 0xf1ffffe +#define HWIO_GCC_PCIE_0_PIPE_SREGR_ATTR 0x3 +#define HWIO_GCC_PCIE_0_PIPE_SREGR_IN \ + in_dword_masked(HWIO_GCC_PCIE_0_PIPE_SREGR_ADDR, HWIO_GCC_PCIE_0_PIPE_SREGR_RMSK) +#define HWIO_GCC_PCIE_0_PIPE_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_0_PIPE_SREGR_ADDR, m) +#define HWIO_GCC_PCIE_0_PIPE_SREGR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_0_PIPE_SREGR_ADDR,v) +#define HWIO_GCC_PCIE_0_PIPE_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_0_PIPE_SREGR_ADDR,m,v,HWIO_GCC_PCIE_0_PIPE_SREGR_IN) +#define HWIO_GCC_PCIE_0_PIPE_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xf000000 +#define HWIO_GCC_PCIE_0_PIPE_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_PCIE_0_PIPE_SREGR_PWR_FSM_CLK_SEL_BMSK 0x100000 +#define HWIO_GCC_PCIE_0_PIPE_SREGR_PWR_FSM_CLK_SEL_SHFT 0x14 +#define HWIO_GCC_PCIE_0_PIPE_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xf0000 +#define HWIO_GCC_PCIE_0_PIPE_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_PCIE_0_PIPE_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_PCIE_0_PIPE_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_PCIE_0_PIPE_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_PIPE_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_PIPE_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_PCIE_0_PIPE_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_PCIE_0_PIPE_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_PIPE_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_PIPE_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_PCIE_0_PIPE_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_PCIE_0_PIPE_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_PIPE_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_PIPE_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_PCIE_0_PIPE_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_PCIE_0_PIPE_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_PCIE_0_PIPE_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_PCIE_0_PIPE_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_PCIE_0_PIPE_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_PCIE_0_PIPE_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_PCIE_0_PIPE_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_PCIE_0_PIPE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_PCIE_0_PIPE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_PCIE_0_PIPE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_PCIE_0_PIPE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_PCIE_0_PIPE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_PCIE_0_PIPE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_PCIE_0_PIPE_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_PCIE_0_PIPE_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_PCIE_0_PIPE_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_PIPE_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_PIPE_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_PCIE_0_PIPE_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_PCIE_0_PIPE_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_PIPE_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_PIPE_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_PCIE_0_PIPE_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_PCIE_0_PIPE_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_PCIE_0_PIPE_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_PCIE_0_PIPE_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_PCIE_0_PIPE_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_PCIE_0_PIPE_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_PCIE_0_PIPE_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_PCIE_0_PIPE_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_PCIE_0_PIPE_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_PCIE_0_PIPE_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_PCIE_0_PIPE_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_PCIE_0_PIPE_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_PCIE_0_PIPE_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_PCIE_0_PIPE_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_PCIE_0_PIPE_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_PCIE_0_PIPE_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_PCIE_0_PIPE_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_PCIE_0_PIPE_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_PIPE_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_0_PIPE_CFG_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005b050) +#define HWIO_GCC_PCIE_0_PIPE_CFG_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005b050) +#define HWIO_GCC_PCIE_0_PIPE_CFG_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005b050) +#define HWIO_GCC_PCIE_0_PIPE_CFG_SREGR_RMSK 0xffffffff +#define HWIO_GCC_PCIE_0_PIPE_CFG_SREGR_ATTR 0x3 +#define HWIO_GCC_PCIE_0_PIPE_CFG_SREGR_IN \ + in_dword_masked(HWIO_GCC_PCIE_0_PIPE_CFG_SREGR_ADDR, HWIO_GCC_PCIE_0_PIPE_CFG_SREGR_RMSK) +#define HWIO_GCC_PCIE_0_PIPE_CFG_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_0_PIPE_CFG_SREGR_ADDR, m) +#define HWIO_GCC_PCIE_0_PIPE_CFG_SREGR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_0_PIPE_CFG_SREGR_ADDR,v) +#define HWIO_GCC_PCIE_0_PIPE_CFG_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_0_PIPE_CFG_SREGR_ADDR,m,v,HWIO_GCC_PCIE_0_PIPE_CFG_SREGR_IN) +#define HWIO_GCC_PCIE_0_PIPE_CFG_SREGR_MEM_CORE_OFF_TIMER_BMSK 0xfc000000 +#define HWIO_GCC_PCIE_0_PIPE_CFG_SREGR_MEM_CORE_OFF_TIMER_SHFT 0x1a +#define HWIO_GCC_PCIE_0_PIPE_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_BMSK 0x2000000 +#define HWIO_GCC_PCIE_0_PIPE_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_SHFT 0x19 +#define HWIO_GCC_PCIE_0_PIPE_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_BMSK 0x1000000 +#define HWIO_GCC_PCIE_0_PIPE_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_SHFT 0x18 +#define HWIO_GCC_PCIE_0_PIPE_CFG_SREGR_MEM_PERIPH_ON_STATUS_BMSK 0x800000 +#define HWIO_GCC_PCIE_0_PIPE_CFG_SREGR_MEM_PERIPH_ON_STATUS_SHFT 0x17 +#define HWIO_GCC_PCIE_0_PIPE_CFG_SREGR_MEM_CORE_ON_STATUS_BMSK 0x400000 +#define HWIO_GCC_PCIE_0_PIPE_CFG_SREGR_MEM_CORE_ON_STATUS_SHFT 0x16 +#define HWIO_GCC_PCIE_0_PIPE_CFG_SREGR_MEM_CPH_TIMER_BMSK 0x3f0000 +#define HWIO_GCC_PCIE_0_PIPE_CFG_SREGR_MEM_CPH_TIMER_SHFT 0x10 +#define HWIO_GCC_PCIE_0_PIPE_CFG_SREGR_SLEEP_TIMER_BMSK 0xff00 +#define HWIO_GCC_PCIE_0_PIPE_CFG_SREGR_SLEEP_TIMER_SHFT 0x8 +#define HWIO_GCC_PCIE_0_PIPE_CFG_SREGR_WAKEUP_TIMER_BMSK 0xff +#define HWIO_GCC_PCIE_0_PIPE_CFG_SREGR_WAKEUP_TIMER_SHFT 0x0 + +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005b054) +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005b054) +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005b054) +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CBCR_RMSK 0x81c00004 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CBCR_ATTR 0x3 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CBCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_0_PHY_RCHNG_CBCR_ADDR, HWIO_GCC_PCIE_0_PHY_RCHNG_CBCR_RMSK) +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_0_PHY_RCHNG_CBCR_ADDR, m) +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CBCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_0_PHY_RCHNG_CBCR_ADDR,v) +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_0_PHY_RCHNG_CBCR_ADDR,m,v,HWIO_GCC_PCIE_0_PHY_RCHNG_CBCR_IN) +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CBCR_CLK_ARES_RESET_FVAL 0x1 + +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005b058) +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005b058) +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005b058) +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_PCIE_0_PHY_RCHNG_CMD_RCGR_ADDR, HWIO_GCC_PCIE_0_PHY_RCHNG_CMD_RCGR_RMSK) +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_0_PHY_RCHNG_CMD_RCGR_ADDR, m) +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_0_PHY_RCHNG_CMD_RCGR_ADDR,v) +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_0_PHY_RCHNG_CMD_RCGR_ADDR,m,v,HWIO_GCC_PCIE_0_PHY_RCHNG_CMD_RCGR_IN) +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005b05c) +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005b05c) +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005b05c) +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_ADDR, HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_RMSK) +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_ADDR, m) +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_ADDR,v) +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_ADDR,m,v,HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_IN) +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_PCIE_0_PHY_RCHNG_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_PCIE_0_AUX_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005b074) +#define HWIO_GCC_PCIE_0_AUX_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005b074) +#define HWIO_GCC_PCIE_0_AUX_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005b074) +#define HWIO_GCC_PCIE_0_AUX_CMD_RCGR_RMSK 0x800000f3 +#define HWIO_GCC_PCIE_0_AUX_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_PCIE_0_AUX_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_PCIE_0_AUX_CMD_RCGR_ADDR, HWIO_GCC_PCIE_0_AUX_CMD_RCGR_RMSK) +#define HWIO_GCC_PCIE_0_AUX_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_0_AUX_CMD_RCGR_ADDR, m) +#define HWIO_GCC_PCIE_0_AUX_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_0_AUX_CMD_RCGR_ADDR,v) +#define HWIO_GCC_PCIE_0_AUX_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_0_AUX_CMD_RCGR_ADDR,m,v,HWIO_GCC_PCIE_0_AUX_CMD_RCGR_IN) +#define HWIO_GCC_PCIE_0_AUX_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_PCIE_0_AUX_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_PCIE_0_AUX_CMD_RCGR_DIRTY_D_BMSK 0x80 +#define HWIO_GCC_PCIE_0_AUX_CMD_RCGR_DIRTY_D_SHFT 0x7 +#define HWIO_GCC_PCIE_0_AUX_CMD_RCGR_DIRTY_N_BMSK 0x40 +#define HWIO_GCC_PCIE_0_AUX_CMD_RCGR_DIRTY_N_SHFT 0x6 +#define HWIO_GCC_PCIE_0_AUX_CMD_RCGR_DIRTY_M_BMSK 0x20 +#define HWIO_GCC_PCIE_0_AUX_CMD_RCGR_DIRTY_M_SHFT 0x5 +#define HWIO_GCC_PCIE_0_AUX_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_PCIE_0_AUX_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_PCIE_0_AUX_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_PCIE_0_AUX_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_PCIE_0_AUX_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_AUX_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_AUX_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_PCIE_0_AUX_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_PCIE_0_AUX_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_AUX_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005b078) +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005b078) +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005b078) +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_RMSK 0x10371f +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_PCIE_0_AUX_CFG_RCGR_ADDR, HWIO_GCC_PCIE_0_AUX_CFG_RCGR_RMSK) +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_0_AUX_CFG_RCGR_ADDR, m) +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_0_AUX_CFG_RCGR_ADDR,v) +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_0_AUX_CFG_RCGR_ADDR,m,v,HWIO_GCC_PCIE_0_AUX_CFG_RCGR_IN) +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_MODE_BMSK 0x3000 +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_MODE_SHFT 0xc +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_PCIE_0_AUX_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005b07c) +#define HWIO_GCC_PCIE_0_AUX_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005b07c) +#define HWIO_GCC_PCIE_0_AUX_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005b07c) +#define HWIO_GCC_PCIE_0_AUX_M_RMSK 0xffff +#define HWIO_GCC_PCIE_0_AUX_M_ATTR 0x3 +#define HWIO_GCC_PCIE_0_AUX_M_IN \ + in_dword_masked(HWIO_GCC_PCIE_0_AUX_M_ADDR, HWIO_GCC_PCIE_0_AUX_M_RMSK) +#define HWIO_GCC_PCIE_0_AUX_M_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_0_AUX_M_ADDR, m) +#define HWIO_GCC_PCIE_0_AUX_M_OUT(v) \ + out_dword(HWIO_GCC_PCIE_0_AUX_M_ADDR,v) +#define HWIO_GCC_PCIE_0_AUX_M_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_0_AUX_M_ADDR,m,v,HWIO_GCC_PCIE_0_AUX_M_IN) +#define HWIO_GCC_PCIE_0_AUX_M_M_BMSK 0xffff +#define HWIO_GCC_PCIE_0_AUX_M_M_SHFT 0x0 + +#define HWIO_GCC_PCIE_0_AUX_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005b080) +#define HWIO_GCC_PCIE_0_AUX_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005b080) +#define HWIO_GCC_PCIE_0_AUX_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005b080) +#define HWIO_GCC_PCIE_0_AUX_N_RMSK 0xffff +#define HWIO_GCC_PCIE_0_AUX_N_ATTR 0x3 +#define HWIO_GCC_PCIE_0_AUX_N_IN \ + in_dword_masked(HWIO_GCC_PCIE_0_AUX_N_ADDR, HWIO_GCC_PCIE_0_AUX_N_RMSK) +#define HWIO_GCC_PCIE_0_AUX_N_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_0_AUX_N_ADDR, m) +#define HWIO_GCC_PCIE_0_AUX_N_OUT(v) \ + out_dword(HWIO_GCC_PCIE_0_AUX_N_ADDR,v) +#define HWIO_GCC_PCIE_0_AUX_N_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_0_AUX_N_ADDR,m,v,HWIO_GCC_PCIE_0_AUX_N_IN) +#define HWIO_GCC_PCIE_0_AUX_N_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_PCIE_0_AUX_N_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_PCIE_0_AUX_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005b084) +#define HWIO_GCC_PCIE_0_AUX_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005b084) +#define HWIO_GCC_PCIE_0_AUX_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005b084) +#define HWIO_GCC_PCIE_0_AUX_D_RMSK 0xffff +#define HWIO_GCC_PCIE_0_AUX_D_ATTR 0x3 +#define HWIO_GCC_PCIE_0_AUX_D_IN \ + in_dword_masked(HWIO_GCC_PCIE_0_AUX_D_ADDR, HWIO_GCC_PCIE_0_AUX_D_RMSK) +#define HWIO_GCC_PCIE_0_AUX_D_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_0_AUX_D_ADDR, m) +#define HWIO_GCC_PCIE_0_AUX_D_OUT(v) \ + out_dword(HWIO_GCC_PCIE_0_AUX_D_ADDR,v) +#define HWIO_GCC_PCIE_0_AUX_D_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_0_AUX_D_ADDR,m,v,HWIO_GCC_PCIE_0_AUX_D_IN) +#define HWIO_GCC_PCIE_0_AUX_D_NOT_2D_BMSK 0xffff +#define HWIO_GCC_PCIE_0_AUX_D_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_PCIE_0_PHY_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005c000) +#define HWIO_GCC_PCIE_0_PHY_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005c000) +#define HWIO_GCC_PCIE_0_PHY_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005c000) +#define HWIO_GCC_PCIE_0_PHY_GDSCR_RMSK 0xf8ffffff +#define HWIO_GCC_PCIE_0_PHY_GDSCR_ATTR 0x3 +#define HWIO_GCC_PCIE_0_PHY_GDSCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_0_PHY_GDSCR_ADDR, HWIO_GCC_PCIE_0_PHY_GDSCR_RMSK) +#define HWIO_GCC_PCIE_0_PHY_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_0_PHY_GDSCR_ADDR, m) +#define HWIO_GCC_PCIE_0_PHY_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_0_PHY_GDSCR_ADDR,v) +#define HWIO_GCC_PCIE_0_PHY_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_0_PHY_GDSCR_ADDR,m,v,HWIO_GCC_PCIE_0_PHY_GDSCR_IN) +#define HWIO_GCC_PCIE_0_PHY_GDSCR_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_PCIE_0_PHY_GDSCR_PWR_ON_SHFT 0x1f +#define HWIO_GCC_PCIE_0_PHY_GDSCR_GDSC_STATE_BMSK 0x78000000 +#define HWIO_GCC_PCIE_0_PHY_GDSCR_GDSC_STATE_SHFT 0x1b +#define HWIO_GCC_PCIE_0_PHY_GDSCR_EN_REST_WAIT_BMSK 0xf00000 +#define HWIO_GCC_PCIE_0_PHY_GDSCR_EN_REST_WAIT_SHFT 0x14 +#define HWIO_GCC_PCIE_0_PHY_GDSCR_EN_FEW_WAIT_BMSK 0xf0000 +#define HWIO_GCC_PCIE_0_PHY_GDSCR_EN_FEW_WAIT_SHFT 0x10 +#define HWIO_GCC_PCIE_0_PHY_GDSCR_CLK_DIS_WAIT_BMSK 0xf000 +#define HWIO_GCC_PCIE_0_PHY_GDSCR_CLK_DIS_WAIT_SHFT 0xc +#define HWIO_GCC_PCIE_0_PHY_GDSCR_RETAIN_FF_ENABLE_BMSK 0x800 +#define HWIO_GCC_PCIE_0_PHY_GDSCR_RETAIN_FF_ENABLE_SHFT 0xb +#define HWIO_GCC_PCIE_0_PHY_GDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_PHY_GDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_PHY_GDSCR_RESTORE_BMSK 0x400 +#define HWIO_GCC_PCIE_0_PHY_GDSCR_RESTORE_SHFT 0xa +#define HWIO_GCC_PCIE_0_PHY_GDSCR_RESTORE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_PHY_GDSCR_RESTORE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_PHY_GDSCR_SAVE_BMSK 0x200 +#define HWIO_GCC_PCIE_0_PHY_GDSCR_SAVE_SHFT 0x9 +#define HWIO_GCC_PCIE_0_PHY_GDSCR_SAVE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_PHY_GDSCR_SAVE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_PHY_GDSCR_RETAIN_BMSK 0x100 +#define HWIO_GCC_PCIE_0_PHY_GDSCR_RETAIN_SHFT 0x8 +#define HWIO_GCC_PCIE_0_PHY_GDSCR_RETAIN_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_PHY_GDSCR_RETAIN_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_PHY_GDSCR_EN_REST_BMSK 0x80 +#define HWIO_GCC_PCIE_0_PHY_GDSCR_EN_REST_SHFT 0x7 +#define HWIO_GCC_PCIE_0_PHY_GDSCR_EN_REST_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_PHY_GDSCR_EN_REST_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_PHY_GDSCR_EN_FEW_BMSK 0x40 +#define HWIO_GCC_PCIE_0_PHY_GDSCR_EN_FEW_SHFT 0x6 +#define HWIO_GCC_PCIE_0_PHY_GDSCR_EN_FEW_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_PHY_GDSCR_EN_FEW_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_PHY_GDSCR_CLAMP_IO_BMSK 0x20 +#define HWIO_GCC_PCIE_0_PHY_GDSCR_CLAMP_IO_SHFT 0x5 +#define HWIO_GCC_PCIE_0_PHY_GDSCR_CLAMP_IO_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_PHY_GDSCR_CLAMP_IO_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_PHY_GDSCR_CLK_DISABLE_BMSK 0x10 +#define HWIO_GCC_PCIE_0_PHY_GDSCR_CLK_DISABLE_SHFT 0x4 +#define HWIO_GCC_PCIE_0_PHY_GDSCR_CLK_DISABLE_CLK_NOT_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_PHY_GDSCR_CLK_DISABLE_CLK_IS_DISABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_PHY_GDSCR_PD_ARES_BMSK 0x8 +#define HWIO_GCC_PCIE_0_PHY_GDSCR_PD_ARES_SHFT 0x3 +#define HWIO_GCC_PCIE_0_PHY_GDSCR_PD_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_PCIE_0_PHY_GDSCR_PD_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_PCIE_0_PHY_GDSCR_SW_OVERRIDE_BMSK 0x4 +#define HWIO_GCC_PCIE_0_PHY_GDSCR_SW_OVERRIDE_SHFT 0x2 +#define HWIO_GCC_PCIE_0_PHY_GDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_PHY_GDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_PHY_GDSCR_HW_CONTROL_BMSK 0x2 +#define HWIO_GCC_PCIE_0_PHY_GDSCR_HW_CONTROL_SHFT 0x1 +#define HWIO_GCC_PCIE_0_PHY_GDSCR_HW_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_PHY_GDSCR_HW_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_PHY_GDSCR_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_PCIE_0_PHY_GDSCR_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_PCIE_0_PHY_GDSCR_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_PHY_GDSCR_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_0_PHY_CFG_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005c004) +#define HWIO_GCC_PCIE_0_PHY_CFG_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005c004) +#define HWIO_GCC_PCIE_0_PHY_CFG_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005c004) +#define HWIO_GCC_PCIE_0_PHY_CFG_GDSCR_RMSK 0x7ffffff +#define HWIO_GCC_PCIE_0_PHY_CFG_GDSCR_ATTR 0x3 +#define HWIO_GCC_PCIE_0_PHY_CFG_GDSCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_0_PHY_CFG_GDSCR_ADDR, HWIO_GCC_PCIE_0_PHY_CFG_GDSCR_RMSK) +#define HWIO_GCC_PCIE_0_PHY_CFG_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_0_PHY_CFG_GDSCR_ADDR, m) +#define HWIO_GCC_PCIE_0_PHY_CFG_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_0_PHY_CFG_GDSCR_ADDR,v) +#define HWIO_GCC_PCIE_0_PHY_CFG_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_0_PHY_CFG_GDSCR_ADDR,m,v,HWIO_GCC_PCIE_0_PHY_CFG_GDSCR_IN) +#define HWIO_GCC_PCIE_0_PHY_CFG_GDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4000000 +#define HWIO_GCC_PCIE_0_PHY_CFG_GDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x1a +#define HWIO_GCC_PCIE_0_PHY_CFG_GDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_PHY_CFG_GDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_PHY_CFG_GDSCR_GDSC_PWR_DWN_START_BMSK 0x2000000 +#define HWIO_GCC_PCIE_0_PHY_CFG_GDSCR_GDSC_PWR_DWN_START_SHFT 0x19 +#define HWIO_GCC_PCIE_0_PHY_CFG_GDSCR_GDSC_PWR_UP_START_BMSK 0x1000000 +#define HWIO_GCC_PCIE_0_PHY_CFG_GDSCR_GDSC_PWR_UP_START_SHFT 0x18 +#define HWIO_GCC_PCIE_0_PHY_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_BMSK 0xf00000 +#define HWIO_GCC_PCIE_0_PHY_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_SHFT 0x14 +#define HWIO_GCC_PCIE_0_PHY_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_BMSK 0x80000 +#define HWIO_GCC_PCIE_0_PHY_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_SHFT 0x13 +#define HWIO_GCC_PCIE_0_PHY_CFG_GDSCR_GDSC_ENR_ACK_STATUS_BMSK 0x40000 +#define HWIO_GCC_PCIE_0_PHY_CFG_GDSCR_GDSC_ENR_ACK_STATUS_SHFT 0x12 +#define HWIO_GCC_PCIE_0_PHY_CFG_GDSCR_GDSC_ENF_ACK_STATUS_BMSK 0x20000 +#define HWIO_GCC_PCIE_0_PHY_CFG_GDSCR_GDSC_ENF_ACK_STATUS_SHFT 0x11 +#define HWIO_GCC_PCIE_0_PHY_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_BMSK 0x10000 +#define HWIO_GCC_PCIE_0_PHY_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_SHFT 0x10 +#define HWIO_GCC_PCIE_0_PHY_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_BMSK 0x8000 +#define HWIO_GCC_PCIE_0_PHY_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_SHFT 0xf +#define HWIO_GCC_PCIE_0_PHY_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_BMSK 0x7800 +#define HWIO_GCC_PCIE_0_PHY_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_SHFT 0xb +#define HWIO_GCC_PCIE_0_PHY_CFG_GDSCR_GDSC_HANDSHAKE_DIS_BMSK 0x400 +#define HWIO_GCC_PCIE_0_PHY_CFG_GDSCR_GDSC_HANDSHAKE_DIS_SHFT 0xa +#define HWIO_GCC_PCIE_0_PHY_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_BMSK 0x200 +#define HWIO_GCC_PCIE_0_PHY_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_SHFT 0x9 +#define HWIO_GCC_PCIE_0_PHY_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_BMSK 0x100 +#define HWIO_GCC_PCIE_0_PHY_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_SHFT 0x8 +#define HWIO_GCC_PCIE_0_PHY_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_BMSK 0x80 +#define HWIO_GCC_PCIE_0_PHY_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_SHFT 0x7 +#define HWIO_GCC_PCIE_0_PHY_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_BMSK 0x60 +#define HWIO_GCC_PCIE_0_PHY_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_SHFT 0x5 +#define HWIO_GCC_PCIE_0_PHY_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_BMSK 0x10 +#define HWIO_GCC_PCIE_0_PHY_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_SHFT 0x4 +#define HWIO_GCC_PCIE_0_PHY_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_BMSK 0x8 +#define HWIO_GCC_PCIE_0_PHY_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_SHFT 0x3 +#define HWIO_GCC_PCIE_0_PHY_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_BMSK 0x4 +#define HWIO_GCC_PCIE_0_PHY_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_SHFT 0x2 +#define HWIO_GCC_PCIE_0_PHY_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_BMSK 0x2 +#define HWIO_GCC_PCIE_0_PHY_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_SHFT 0x1 +#define HWIO_GCC_PCIE_0_PHY_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_PCIE_0_PHY_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_SHFT 0x0 + +#define HWIO_GCC_PCIE_0_PHY_CFG2_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005c008) +#define HWIO_GCC_PCIE_0_PHY_CFG2_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005c008) +#define HWIO_GCC_PCIE_0_PHY_CFG2_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005c008) +#define HWIO_GCC_PCIE_0_PHY_CFG2_GDSCR_RMSK 0x7ffff +#define HWIO_GCC_PCIE_0_PHY_CFG2_GDSCR_ATTR 0x3 +#define HWIO_GCC_PCIE_0_PHY_CFG2_GDSCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_0_PHY_CFG2_GDSCR_ADDR, HWIO_GCC_PCIE_0_PHY_CFG2_GDSCR_RMSK) +#define HWIO_GCC_PCIE_0_PHY_CFG2_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_0_PHY_CFG2_GDSCR_ADDR, m) +#define HWIO_GCC_PCIE_0_PHY_CFG2_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_0_PHY_CFG2_GDSCR_ADDR,v) +#define HWIO_GCC_PCIE_0_PHY_CFG2_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_0_PHY_CFG2_GDSCR_ADDR,m,v,HWIO_GCC_PCIE_0_PHY_CFG2_GDSCR_IN) +#define HWIO_GCC_PCIE_0_PHY_CFG2_GDSCR_GDSC_MEM_PWRUP_ACK_OVERRIDE_BMSK 0x40000 +#define HWIO_GCC_PCIE_0_PHY_CFG2_GDSCR_GDSC_MEM_PWRUP_ACK_OVERRIDE_SHFT 0x12 +#define HWIO_GCC_PCIE_0_PHY_CFG2_GDSCR_GDSC_PWRDWN_ENABLE_ACK_OVERRIDE_BMSK 0x20000 +#define HWIO_GCC_PCIE_0_PHY_CFG2_GDSCR_GDSC_PWRDWN_ENABLE_ACK_OVERRIDE_SHFT 0x11 +#define HWIO_GCC_PCIE_0_PHY_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_BMSK 0x10000 +#define HWIO_GCC_PCIE_0_PHY_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_SHFT 0x10 +#define HWIO_GCC_PCIE_0_PHY_CFG2_GDSCR_DLY_MEM_PWR_UP_BMSK 0xf000 +#define HWIO_GCC_PCIE_0_PHY_CFG2_GDSCR_DLY_MEM_PWR_UP_SHFT 0xc +#define HWIO_GCC_PCIE_0_PHY_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_BMSK 0xf00 +#define HWIO_GCC_PCIE_0_PHY_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_SHFT 0x8 +#define HWIO_GCC_PCIE_0_PHY_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_BMSK 0xf0 +#define HWIO_GCC_PCIE_0_PHY_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_SHFT 0x4 +#define HWIO_GCC_PCIE_0_PHY_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_BMSK 0xf +#define HWIO_GCC_PCIE_0_PHY_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_SHFT 0x0 + +#define HWIO_GCC_PCIE_0_PHY_CFG3_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005c00c) +#define HWIO_GCC_PCIE_0_PHY_CFG3_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005c00c) +#define HWIO_GCC_PCIE_0_PHY_CFG3_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005c00c) +#define HWIO_GCC_PCIE_0_PHY_CFG3_GDSCR_RMSK 0x7ffffff +#define HWIO_GCC_PCIE_0_PHY_CFG3_GDSCR_ATTR 0x3 +#define HWIO_GCC_PCIE_0_PHY_CFG3_GDSCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_0_PHY_CFG3_GDSCR_ADDR, HWIO_GCC_PCIE_0_PHY_CFG3_GDSCR_RMSK) +#define HWIO_GCC_PCIE_0_PHY_CFG3_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_0_PHY_CFG3_GDSCR_ADDR, m) +#define HWIO_GCC_PCIE_0_PHY_CFG3_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_0_PHY_CFG3_GDSCR_ADDR,v) +#define HWIO_GCC_PCIE_0_PHY_CFG3_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_0_PHY_CFG3_GDSCR_ADDR,m,v,HWIO_GCC_PCIE_0_PHY_CFG3_GDSCR_IN) +#define HWIO_GCC_PCIE_0_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_STATUS_BMSK 0x4000000 +#define HWIO_GCC_PCIE_0_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_STATUS_SHFT 0x1a +#define HWIO_GCC_PCIE_0_PHY_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_BMSK 0x2000000 +#define HWIO_GCC_PCIE_0_PHY_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_SHFT 0x19 +#define HWIO_GCC_PCIE_0_PHY_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_PHY_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_PHY_CFG3_GDSCR_DLY_ACCU_RED_SHIFTER_DONE_BMSK 0x1e00000 +#define HWIO_GCC_PCIE_0_PHY_CFG3_GDSCR_DLY_ACCU_RED_SHIFTER_DONE_SHFT 0x15 +#define HWIO_GCC_PCIE_0_PHY_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_BMSK 0x100000 +#define HWIO_GCC_PCIE_0_PHY_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_SHFT 0x14 +#define HWIO_GCC_PCIE_0_PHY_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_PHY_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_BMSK 0x80000 +#define HWIO_GCC_PCIE_0_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_SHFT 0x13 +#define HWIO_GCC_PCIE_0_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_BMSK 0x40000 +#define HWIO_GCC_PCIE_0_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_SHFT 0x12 +#define HWIO_GCC_PCIE_0_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_BMSK 0x20000 +#define HWIO_GCC_PCIE_0_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_SHFT 0x11 +#define HWIO_GCC_PCIE_0_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_BMSK 0x10000 +#define HWIO_GCC_PCIE_0_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_SHFT 0x10 +#define HWIO_GCC_PCIE_0_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_PHY_CFG3_GDSCR_GDSC_SPARE_CTRL_IN_BMSK 0xff00 +#define HWIO_GCC_PCIE_0_PHY_CFG3_GDSCR_GDSC_SPARE_CTRL_IN_SHFT 0x8 +#define HWIO_GCC_PCIE_0_PHY_CFG3_GDSCR_GDSC_SPARE_CTRL_OUT_BMSK 0xff +#define HWIO_GCC_PCIE_0_PHY_CFG3_GDSCR_GDSC_SPARE_CTRL_OUT_SHFT 0x0 + +#define HWIO_GCC_PCIE_0_PHY_CFG4_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005c010) +#define HWIO_GCC_PCIE_0_PHY_CFG4_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005c010) +#define HWIO_GCC_PCIE_0_PHY_CFG4_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005c010) +#define HWIO_GCC_PCIE_0_PHY_CFG4_GDSCR_RMSK 0xffffff +#define HWIO_GCC_PCIE_0_PHY_CFG4_GDSCR_ATTR 0x3 +#define HWIO_GCC_PCIE_0_PHY_CFG4_GDSCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_0_PHY_CFG4_GDSCR_ADDR, HWIO_GCC_PCIE_0_PHY_CFG4_GDSCR_RMSK) +#define HWIO_GCC_PCIE_0_PHY_CFG4_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_0_PHY_CFG4_GDSCR_ADDR, m) +#define HWIO_GCC_PCIE_0_PHY_CFG4_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_0_PHY_CFG4_GDSCR_ADDR,v) +#define HWIO_GCC_PCIE_0_PHY_CFG4_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_0_PHY_CFG4_GDSCR_ADDR,m,v,HWIO_GCC_PCIE_0_PHY_CFG4_GDSCR_IN) +#define HWIO_GCC_PCIE_0_PHY_CFG4_GDSCR_DLY_UNCLAMPIO_BMSK 0xf00000 +#define HWIO_GCC_PCIE_0_PHY_CFG4_GDSCR_DLY_UNCLAMPIO_SHFT 0x14 +#define HWIO_GCC_PCIE_0_PHY_CFG4_GDSCR_DLY_RESTOREFF_BMSK 0xf0000 +#define HWIO_GCC_PCIE_0_PHY_CFG4_GDSCR_DLY_RESTOREFF_SHFT 0x10 +#define HWIO_GCC_PCIE_0_PHY_CFG4_GDSCR_DLY_NORETAINFF_BMSK 0xf000 +#define HWIO_GCC_PCIE_0_PHY_CFG4_GDSCR_DLY_NORETAINFF_SHFT 0xc +#define HWIO_GCC_PCIE_0_PHY_CFG4_GDSCR_DLY_DEASSERTARES_BMSK 0xf00 +#define HWIO_GCC_PCIE_0_PHY_CFG4_GDSCR_DLY_DEASSERTARES_SHFT 0x8 +#define HWIO_GCC_PCIE_0_PHY_CFG4_GDSCR_DLY_CLAMPIO_BMSK 0xf0 +#define HWIO_GCC_PCIE_0_PHY_CFG4_GDSCR_DLY_CLAMPIO_SHFT 0x4 +#define HWIO_GCC_PCIE_0_PHY_CFG4_GDSCR_DLY_RETAINFF_BMSK 0xf +#define HWIO_GCC_PCIE_0_PHY_CFG4_GDSCR_DLY_RETAINFF_SHFT 0x0 + +#define HWIO_GCC_PCIE_1_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007d000) +#define HWIO_GCC_PCIE_1_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d000) +#define HWIO_GCC_PCIE_1_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d000) +#define HWIO_GCC_PCIE_1_BCR_RMSK 0x1 +#define HWIO_GCC_PCIE_1_BCR_ATTR 0x3 +#define HWIO_GCC_PCIE_1_BCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_1_BCR_ADDR, HWIO_GCC_PCIE_1_BCR_RMSK) +#define HWIO_GCC_PCIE_1_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_1_BCR_ADDR, m) +#define HWIO_GCC_PCIE_1_BCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_1_BCR_ADDR,v) +#define HWIO_GCC_PCIE_1_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_1_BCR_ADDR,m,v,HWIO_GCC_PCIE_1_BCR_IN) +#define HWIO_GCC_PCIE_1_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_PCIE_1_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_PCIE_1_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_1_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007d004) +#define HWIO_GCC_PCIE_1_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d004) +#define HWIO_GCC_PCIE_1_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d004) +#define HWIO_GCC_PCIE_1_GDSCR_RMSK 0xf8ffffff +#define HWIO_GCC_PCIE_1_GDSCR_ATTR 0x3 +#define HWIO_GCC_PCIE_1_GDSCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_1_GDSCR_ADDR, HWIO_GCC_PCIE_1_GDSCR_RMSK) +#define HWIO_GCC_PCIE_1_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_1_GDSCR_ADDR, m) +#define HWIO_GCC_PCIE_1_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_1_GDSCR_ADDR,v) +#define HWIO_GCC_PCIE_1_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_1_GDSCR_ADDR,m,v,HWIO_GCC_PCIE_1_GDSCR_IN) +#define HWIO_GCC_PCIE_1_GDSCR_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_PCIE_1_GDSCR_PWR_ON_SHFT 0x1f +#define HWIO_GCC_PCIE_1_GDSCR_GDSC_STATE_BMSK 0x78000000 +#define HWIO_GCC_PCIE_1_GDSCR_GDSC_STATE_SHFT 0x1b +#define HWIO_GCC_PCIE_1_GDSCR_EN_REST_WAIT_BMSK 0xf00000 +#define HWIO_GCC_PCIE_1_GDSCR_EN_REST_WAIT_SHFT 0x14 +#define HWIO_GCC_PCIE_1_GDSCR_EN_FEW_WAIT_BMSK 0xf0000 +#define HWIO_GCC_PCIE_1_GDSCR_EN_FEW_WAIT_SHFT 0x10 +#define HWIO_GCC_PCIE_1_GDSCR_CLK_DIS_WAIT_BMSK 0xf000 +#define HWIO_GCC_PCIE_1_GDSCR_CLK_DIS_WAIT_SHFT 0xc +#define HWIO_GCC_PCIE_1_GDSCR_RETAIN_FF_ENABLE_BMSK 0x800 +#define HWIO_GCC_PCIE_1_GDSCR_RETAIN_FF_ENABLE_SHFT 0xb +#define HWIO_GCC_PCIE_1_GDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_GDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_GDSCR_RESTORE_BMSK 0x400 +#define HWIO_GCC_PCIE_1_GDSCR_RESTORE_SHFT 0xa +#define HWIO_GCC_PCIE_1_GDSCR_RESTORE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_GDSCR_RESTORE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_GDSCR_SAVE_BMSK 0x200 +#define HWIO_GCC_PCIE_1_GDSCR_SAVE_SHFT 0x9 +#define HWIO_GCC_PCIE_1_GDSCR_SAVE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_GDSCR_SAVE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_GDSCR_RETAIN_BMSK 0x100 +#define HWIO_GCC_PCIE_1_GDSCR_RETAIN_SHFT 0x8 +#define HWIO_GCC_PCIE_1_GDSCR_RETAIN_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_GDSCR_RETAIN_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_GDSCR_EN_REST_BMSK 0x80 +#define HWIO_GCC_PCIE_1_GDSCR_EN_REST_SHFT 0x7 +#define HWIO_GCC_PCIE_1_GDSCR_EN_REST_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_GDSCR_EN_REST_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_GDSCR_EN_FEW_BMSK 0x40 +#define HWIO_GCC_PCIE_1_GDSCR_EN_FEW_SHFT 0x6 +#define HWIO_GCC_PCIE_1_GDSCR_EN_FEW_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_GDSCR_EN_FEW_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_GDSCR_CLAMP_IO_BMSK 0x20 +#define HWIO_GCC_PCIE_1_GDSCR_CLAMP_IO_SHFT 0x5 +#define HWIO_GCC_PCIE_1_GDSCR_CLAMP_IO_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_GDSCR_CLAMP_IO_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_GDSCR_CLK_DISABLE_BMSK 0x10 +#define HWIO_GCC_PCIE_1_GDSCR_CLK_DISABLE_SHFT 0x4 +#define HWIO_GCC_PCIE_1_GDSCR_CLK_DISABLE_CLK_NOT_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_GDSCR_CLK_DISABLE_CLK_IS_DISABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_GDSCR_PD_ARES_BMSK 0x8 +#define HWIO_GCC_PCIE_1_GDSCR_PD_ARES_SHFT 0x3 +#define HWIO_GCC_PCIE_1_GDSCR_PD_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_PCIE_1_GDSCR_PD_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_PCIE_1_GDSCR_SW_OVERRIDE_BMSK 0x4 +#define HWIO_GCC_PCIE_1_GDSCR_SW_OVERRIDE_SHFT 0x2 +#define HWIO_GCC_PCIE_1_GDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_GDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_GDSCR_HW_CONTROL_BMSK 0x2 +#define HWIO_GCC_PCIE_1_GDSCR_HW_CONTROL_SHFT 0x1 +#define HWIO_GCC_PCIE_1_GDSCR_HW_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_GDSCR_HW_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_GDSCR_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_PCIE_1_GDSCR_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_PCIE_1_GDSCR_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_GDSCR_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_1_CFG_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007d008) +#define HWIO_GCC_PCIE_1_CFG_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d008) +#define HWIO_GCC_PCIE_1_CFG_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d008) +#define HWIO_GCC_PCIE_1_CFG_GDSCR_RMSK 0x7ffffff +#define HWIO_GCC_PCIE_1_CFG_GDSCR_ATTR 0x3 +#define HWIO_GCC_PCIE_1_CFG_GDSCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_1_CFG_GDSCR_ADDR, HWIO_GCC_PCIE_1_CFG_GDSCR_RMSK) +#define HWIO_GCC_PCIE_1_CFG_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_1_CFG_GDSCR_ADDR, m) +#define HWIO_GCC_PCIE_1_CFG_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_1_CFG_GDSCR_ADDR,v) +#define HWIO_GCC_PCIE_1_CFG_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_1_CFG_GDSCR_ADDR,m,v,HWIO_GCC_PCIE_1_CFG_GDSCR_IN) +#define HWIO_GCC_PCIE_1_CFG_GDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4000000 +#define HWIO_GCC_PCIE_1_CFG_GDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x1a +#define HWIO_GCC_PCIE_1_CFG_GDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_CFG_GDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_CFG_GDSCR_GDSC_PWR_DWN_START_BMSK 0x2000000 +#define HWIO_GCC_PCIE_1_CFG_GDSCR_GDSC_PWR_DWN_START_SHFT 0x19 +#define HWIO_GCC_PCIE_1_CFG_GDSCR_GDSC_PWR_UP_START_BMSK 0x1000000 +#define HWIO_GCC_PCIE_1_CFG_GDSCR_GDSC_PWR_UP_START_SHFT 0x18 +#define HWIO_GCC_PCIE_1_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_BMSK 0xf00000 +#define HWIO_GCC_PCIE_1_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_SHFT 0x14 +#define HWIO_GCC_PCIE_1_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_BMSK 0x80000 +#define HWIO_GCC_PCIE_1_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_SHFT 0x13 +#define HWIO_GCC_PCIE_1_CFG_GDSCR_GDSC_ENR_ACK_STATUS_BMSK 0x40000 +#define HWIO_GCC_PCIE_1_CFG_GDSCR_GDSC_ENR_ACK_STATUS_SHFT 0x12 +#define HWIO_GCC_PCIE_1_CFG_GDSCR_GDSC_ENF_ACK_STATUS_BMSK 0x20000 +#define HWIO_GCC_PCIE_1_CFG_GDSCR_GDSC_ENF_ACK_STATUS_SHFT 0x11 +#define HWIO_GCC_PCIE_1_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_BMSK 0x10000 +#define HWIO_GCC_PCIE_1_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_SHFT 0x10 +#define HWIO_GCC_PCIE_1_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_BMSK 0x8000 +#define HWIO_GCC_PCIE_1_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_SHFT 0xf +#define HWIO_GCC_PCIE_1_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_BMSK 0x7800 +#define HWIO_GCC_PCIE_1_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_SHFT 0xb +#define HWIO_GCC_PCIE_1_CFG_GDSCR_GDSC_HANDSHAKE_DIS_BMSK 0x400 +#define HWIO_GCC_PCIE_1_CFG_GDSCR_GDSC_HANDSHAKE_DIS_SHFT 0xa +#define HWIO_GCC_PCIE_1_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_BMSK 0x200 +#define HWIO_GCC_PCIE_1_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_SHFT 0x9 +#define HWIO_GCC_PCIE_1_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_BMSK 0x100 +#define HWIO_GCC_PCIE_1_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_SHFT 0x8 +#define HWIO_GCC_PCIE_1_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_BMSK 0x80 +#define HWIO_GCC_PCIE_1_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_SHFT 0x7 +#define HWIO_GCC_PCIE_1_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_BMSK 0x60 +#define HWIO_GCC_PCIE_1_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_SHFT 0x5 +#define HWIO_GCC_PCIE_1_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_BMSK 0x10 +#define HWIO_GCC_PCIE_1_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_SHFT 0x4 +#define HWIO_GCC_PCIE_1_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_BMSK 0x8 +#define HWIO_GCC_PCIE_1_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_SHFT 0x3 +#define HWIO_GCC_PCIE_1_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_BMSK 0x4 +#define HWIO_GCC_PCIE_1_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_SHFT 0x2 +#define HWIO_GCC_PCIE_1_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_BMSK 0x2 +#define HWIO_GCC_PCIE_1_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_SHFT 0x1 +#define HWIO_GCC_PCIE_1_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_PCIE_1_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_SHFT 0x0 + +#define HWIO_GCC_PCIE_1_CFG2_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007d00c) +#define HWIO_GCC_PCIE_1_CFG2_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d00c) +#define HWIO_GCC_PCIE_1_CFG2_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d00c) +#define HWIO_GCC_PCIE_1_CFG2_GDSCR_RMSK 0x7ffff +#define HWIO_GCC_PCIE_1_CFG2_GDSCR_ATTR 0x3 +#define HWIO_GCC_PCIE_1_CFG2_GDSCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_1_CFG2_GDSCR_ADDR, HWIO_GCC_PCIE_1_CFG2_GDSCR_RMSK) +#define HWIO_GCC_PCIE_1_CFG2_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_1_CFG2_GDSCR_ADDR, m) +#define HWIO_GCC_PCIE_1_CFG2_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_1_CFG2_GDSCR_ADDR,v) +#define HWIO_GCC_PCIE_1_CFG2_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_1_CFG2_GDSCR_ADDR,m,v,HWIO_GCC_PCIE_1_CFG2_GDSCR_IN) +#define HWIO_GCC_PCIE_1_CFG2_GDSCR_GDSC_MEM_PWRUP_ACK_OVERRIDE_BMSK 0x40000 +#define HWIO_GCC_PCIE_1_CFG2_GDSCR_GDSC_MEM_PWRUP_ACK_OVERRIDE_SHFT 0x12 +#define HWIO_GCC_PCIE_1_CFG2_GDSCR_GDSC_PWRDWN_ENABLE_ACK_OVERRIDE_BMSK 0x20000 +#define HWIO_GCC_PCIE_1_CFG2_GDSCR_GDSC_PWRDWN_ENABLE_ACK_OVERRIDE_SHFT 0x11 +#define HWIO_GCC_PCIE_1_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_BMSK 0x10000 +#define HWIO_GCC_PCIE_1_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_SHFT 0x10 +#define HWIO_GCC_PCIE_1_CFG2_GDSCR_DLY_MEM_PWR_UP_BMSK 0xf000 +#define HWIO_GCC_PCIE_1_CFG2_GDSCR_DLY_MEM_PWR_UP_SHFT 0xc +#define HWIO_GCC_PCIE_1_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_BMSK 0xf00 +#define HWIO_GCC_PCIE_1_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_SHFT 0x8 +#define HWIO_GCC_PCIE_1_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_BMSK 0xf0 +#define HWIO_GCC_PCIE_1_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_SHFT 0x4 +#define HWIO_GCC_PCIE_1_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_BMSK 0xf +#define HWIO_GCC_PCIE_1_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_SHFT 0x0 + +#define HWIO_GCC_PCIE_1_CFG3_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007d010) +#define HWIO_GCC_PCIE_1_CFG3_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d010) +#define HWIO_GCC_PCIE_1_CFG3_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d010) +#define HWIO_GCC_PCIE_1_CFG3_GDSCR_RMSK 0x7ffffff +#define HWIO_GCC_PCIE_1_CFG3_GDSCR_ATTR 0x3 +#define HWIO_GCC_PCIE_1_CFG3_GDSCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_1_CFG3_GDSCR_ADDR, HWIO_GCC_PCIE_1_CFG3_GDSCR_RMSK) +#define HWIO_GCC_PCIE_1_CFG3_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_1_CFG3_GDSCR_ADDR, m) +#define HWIO_GCC_PCIE_1_CFG3_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_1_CFG3_GDSCR_ADDR,v) +#define HWIO_GCC_PCIE_1_CFG3_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_1_CFG3_GDSCR_ADDR,m,v,HWIO_GCC_PCIE_1_CFG3_GDSCR_IN) +#define HWIO_GCC_PCIE_1_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_STATUS_BMSK 0x4000000 +#define HWIO_GCC_PCIE_1_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_STATUS_SHFT 0x1a +#define HWIO_GCC_PCIE_1_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_BMSK 0x2000000 +#define HWIO_GCC_PCIE_1_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_SHFT 0x19 +#define HWIO_GCC_PCIE_1_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_CFG3_GDSCR_DLY_ACCU_RED_SHIFTER_DONE_BMSK 0x1e00000 +#define HWIO_GCC_PCIE_1_CFG3_GDSCR_DLY_ACCU_RED_SHIFTER_DONE_SHFT 0x15 +#define HWIO_GCC_PCIE_1_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_BMSK 0x100000 +#define HWIO_GCC_PCIE_1_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_SHFT 0x14 +#define HWIO_GCC_PCIE_1_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_BMSK 0x80000 +#define HWIO_GCC_PCIE_1_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_SHFT 0x13 +#define HWIO_GCC_PCIE_1_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_BMSK 0x40000 +#define HWIO_GCC_PCIE_1_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_SHFT 0x12 +#define HWIO_GCC_PCIE_1_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_BMSK 0x20000 +#define HWIO_GCC_PCIE_1_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_SHFT 0x11 +#define HWIO_GCC_PCIE_1_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_BMSK 0x10000 +#define HWIO_GCC_PCIE_1_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_SHFT 0x10 +#define HWIO_GCC_PCIE_1_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_CFG3_GDSCR_GDSC_SPARE_CTRL_IN_BMSK 0xff00 +#define HWIO_GCC_PCIE_1_CFG3_GDSCR_GDSC_SPARE_CTRL_IN_SHFT 0x8 +#define HWIO_GCC_PCIE_1_CFG3_GDSCR_GDSC_SPARE_CTRL_OUT_BMSK 0xff +#define HWIO_GCC_PCIE_1_CFG3_GDSCR_GDSC_SPARE_CTRL_OUT_SHFT 0x0 + +#define HWIO_GCC_PCIE_1_CFG4_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007d014) +#define HWIO_GCC_PCIE_1_CFG4_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d014) +#define HWIO_GCC_PCIE_1_CFG4_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d014) +#define HWIO_GCC_PCIE_1_CFG4_GDSCR_RMSK 0xffffff +#define HWIO_GCC_PCIE_1_CFG4_GDSCR_ATTR 0x3 +#define HWIO_GCC_PCIE_1_CFG4_GDSCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_1_CFG4_GDSCR_ADDR, HWIO_GCC_PCIE_1_CFG4_GDSCR_RMSK) +#define HWIO_GCC_PCIE_1_CFG4_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_1_CFG4_GDSCR_ADDR, m) +#define HWIO_GCC_PCIE_1_CFG4_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_1_CFG4_GDSCR_ADDR,v) +#define HWIO_GCC_PCIE_1_CFG4_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_1_CFG4_GDSCR_ADDR,m,v,HWIO_GCC_PCIE_1_CFG4_GDSCR_IN) +#define HWIO_GCC_PCIE_1_CFG4_GDSCR_DLY_UNCLAMPIO_BMSK 0xf00000 +#define HWIO_GCC_PCIE_1_CFG4_GDSCR_DLY_UNCLAMPIO_SHFT 0x14 +#define HWIO_GCC_PCIE_1_CFG4_GDSCR_DLY_RESTOREFF_BMSK 0xf0000 +#define HWIO_GCC_PCIE_1_CFG4_GDSCR_DLY_RESTOREFF_SHFT 0x10 +#define HWIO_GCC_PCIE_1_CFG4_GDSCR_DLY_NORETAINFF_BMSK 0xf000 +#define HWIO_GCC_PCIE_1_CFG4_GDSCR_DLY_NORETAINFF_SHFT 0xc +#define HWIO_GCC_PCIE_1_CFG4_GDSCR_DLY_DEASSERTARES_BMSK 0xf00 +#define HWIO_GCC_PCIE_1_CFG4_GDSCR_DLY_DEASSERTARES_SHFT 0x8 +#define HWIO_GCC_PCIE_1_CFG4_GDSCR_DLY_CLAMPIO_BMSK 0xf0 +#define HWIO_GCC_PCIE_1_CFG4_GDSCR_DLY_CLAMPIO_SHFT 0x4 +#define HWIO_GCC_PCIE_1_CFG4_GDSCR_DLY_RETAINFF_BMSK 0xf +#define HWIO_GCC_PCIE_1_CFG4_GDSCR_DLY_RETAINFF_SHFT 0x0 + +#define HWIO_GCC_PCIE_1_SLV_Q2A_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007d018) +#define HWIO_GCC_PCIE_1_SLV_Q2A_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d018) +#define HWIO_GCC_PCIE_1_SLV_Q2A_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d018) +#define HWIO_GCC_PCIE_1_SLV_Q2A_AXI_CBCR_RMSK 0x81d00004 +#define HWIO_GCC_PCIE_1_SLV_Q2A_AXI_CBCR_ATTR 0x3 +#define HWIO_GCC_PCIE_1_SLV_Q2A_AXI_CBCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_1_SLV_Q2A_AXI_CBCR_ADDR, HWIO_GCC_PCIE_1_SLV_Q2A_AXI_CBCR_RMSK) +#define HWIO_GCC_PCIE_1_SLV_Q2A_AXI_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_1_SLV_Q2A_AXI_CBCR_ADDR, m) +#define HWIO_GCC_PCIE_1_SLV_Q2A_AXI_CBCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_1_SLV_Q2A_AXI_CBCR_ADDR,v) +#define HWIO_GCC_PCIE_1_SLV_Q2A_AXI_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_1_SLV_Q2A_AXI_CBCR_ADDR,m,v,HWIO_GCC_PCIE_1_SLV_Q2A_AXI_CBCR_IN) +#define HWIO_GCC_PCIE_1_SLV_Q2A_AXI_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_PCIE_1_SLV_Q2A_AXI_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_PCIE_1_SLV_Q2A_AXI_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_PCIE_1_SLV_Q2A_AXI_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_PCIE_1_SLV_Q2A_AXI_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_PCIE_1_SLV_Q2A_AXI_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_PCIE_1_SLV_Q2A_AXI_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_PCIE_1_SLV_Q2A_AXI_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_PCIE_1_SLV_Q2A_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_PCIE_1_SLV_Q2A_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_PCIE_1_SLV_Q2A_AXI_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_PCIE_1_SLV_Q2A_AXI_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_PCIE_1_SLV_Q2A_AXI_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_PCIE_1_SLV_Q2A_AXI_CBCR_CLK_ARES_RESET_FVAL 0x1 + +#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007d01c) +#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d01c) +#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d01c) +#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_RMSK 0x81d0700e +#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_ATTR 0x3 +#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_1_SLV_AXI_CBCR_ADDR, HWIO_GCC_PCIE_1_SLV_AXI_CBCR_RMSK) +#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_1_SLV_AXI_CBCR_ADDR, m) +#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_1_SLV_AXI_CBCR_ADDR,v) +#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_1_SLV_AXI_CBCR_ADDR,m,v,HWIO_GCC_PCIE_1_SLV_AXI_CBCR_IN) +#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_HW_CTL_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007d020) +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d020) +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d020) +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_RMSK 0xf1ffffe +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_ATTR 0x3 +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_IN \ + in_dword_masked(HWIO_GCC_PCIE_1_SLV_AXI_SREGR_ADDR, HWIO_GCC_PCIE_1_SLV_AXI_SREGR_RMSK) +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_1_SLV_AXI_SREGR_ADDR, m) +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_1_SLV_AXI_SREGR_ADDR,v) +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_1_SLV_AXI_SREGR_ADDR,m,v,HWIO_GCC_PCIE_1_SLV_AXI_SREGR_IN) +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xf000000 +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_PWR_FSM_CLK_SEL_BMSK 0x100000 +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_PWR_FSM_CLK_SEL_SHFT 0x14 +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xf0000 +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_1_SLV_AXI_CFG_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007d024) +#define HWIO_GCC_PCIE_1_SLV_AXI_CFG_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d024) +#define HWIO_GCC_PCIE_1_SLV_AXI_CFG_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d024) +#define HWIO_GCC_PCIE_1_SLV_AXI_CFG_SREGR_RMSK 0xffffffff +#define HWIO_GCC_PCIE_1_SLV_AXI_CFG_SREGR_ATTR 0x3 +#define HWIO_GCC_PCIE_1_SLV_AXI_CFG_SREGR_IN \ + in_dword_masked(HWIO_GCC_PCIE_1_SLV_AXI_CFG_SREGR_ADDR, HWIO_GCC_PCIE_1_SLV_AXI_CFG_SREGR_RMSK) +#define HWIO_GCC_PCIE_1_SLV_AXI_CFG_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_1_SLV_AXI_CFG_SREGR_ADDR, m) +#define HWIO_GCC_PCIE_1_SLV_AXI_CFG_SREGR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_1_SLV_AXI_CFG_SREGR_ADDR,v) +#define HWIO_GCC_PCIE_1_SLV_AXI_CFG_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_1_SLV_AXI_CFG_SREGR_ADDR,m,v,HWIO_GCC_PCIE_1_SLV_AXI_CFG_SREGR_IN) +#define HWIO_GCC_PCIE_1_SLV_AXI_CFG_SREGR_MEM_CORE_OFF_TIMER_BMSK 0xfc000000 +#define HWIO_GCC_PCIE_1_SLV_AXI_CFG_SREGR_MEM_CORE_OFF_TIMER_SHFT 0x1a +#define HWIO_GCC_PCIE_1_SLV_AXI_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_BMSK 0x2000000 +#define HWIO_GCC_PCIE_1_SLV_AXI_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_SHFT 0x19 +#define HWIO_GCC_PCIE_1_SLV_AXI_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_BMSK 0x1000000 +#define HWIO_GCC_PCIE_1_SLV_AXI_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_SHFT 0x18 +#define HWIO_GCC_PCIE_1_SLV_AXI_CFG_SREGR_MEM_PERIPH_ON_STATUS_BMSK 0x800000 +#define HWIO_GCC_PCIE_1_SLV_AXI_CFG_SREGR_MEM_PERIPH_ON_STATUS_SHFT 0x17 +#define HWIO_GCC_PCIE_1_SLV_AXI_CFG_SREGR_MEM_CORE_ON_STATUS_BMSK 0x400000 +#define HWIO_GCC_PCIE_1_SLV_AXI_CFG_SREGR_MEM_CORE_ON_STATUS_SHFT 0x16 +#define HWIO_GCC_PCIE_1_SLV_AXI_CFG_SREGR_MEM_CPH_TIMER_BMSK 0x3f0000 +#define HWIO_GCC_PCIE_1_SLV_AXI_CFG_SREGR_MEM_CPH_TIMER_SHFT 0x10 +#define HWIO_GCC_PCIE_1_SLV_AXI_CFG_SREGR_SLEEP_TIMER_BMSK 0xff00 +#define HWIO_GCC_PCIE_1_SLV_AXI_CFG_SREGR_SLEEP_TIMER_SHFT 0x8 +#define HWIO_GCC_PCIE_1_SLV_AXI_CFG_SREGR_WAKEUP_TIMER_BMSK 0xff +#define HWIO_GCC_PCIE_1_SLV_AXI_CFG_SREGR_WAKEUP_TIMER_SHFT 0x0 + +#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007d028) +#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d028) +#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d028) +#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_RMSK 0x81f0700e +#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_ATTR 0x3 +#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_ADDR, HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_RMSK) +#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_ADDR, m) +#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_ADDR,v) +#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_ADDR,m,v,HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_IN) +#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_IGNORE_PMU_CLK_DIS_BMSK 0x200000 +#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_IGNORE_PMU_CLK_DIS_SHFT 0x15 +#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_HW_CTL_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007d02c) +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d02c) +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d02c) +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_RMSK 0xf1ffffe +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_ATTR 0x3 +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_IN \ + in_dword_masked(HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_ADDR, HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_RMSK) +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_ADDR, m) +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_ADDR,v) +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_ADDR,m,v,HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_IN) +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xf000000 +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_PWR_FSM_CLK_SEL_BMSK 0x100000 +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_PWR_FSM_CLK_SEL_SHFT 0x14 +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xf0000 +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_1_MSTR_AXI_CFG_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007d030) +#define HWIO_GCC_PCIE_1_MSTR_AXI_CFG_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d030) +#define HWIO_GCC_PCIE_1_MSTR_AXI_CFG_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d030) +#define HWIO_GCC_PCIE_1_MSTR_AXI_CFG_SREGR_RMSK 0xffffffff +#define HWIO_GCC_PCIE_1_MSTR_AXI_CFG_SREGR_ATTR 0x3 +#define HWIO_GCC_PCIE_1_MSTR_AXI_CFG_SREGR_IN \ + in_dword_masked(HWIO_GCC_PCIE_1_MSTR_AXI_CFG_SREGR_ADDR, HWIO_GCC_PCIE_1_MSTR_AXI_CFG_SREGR_RMSK) +#define HWIO_GCC_PCIE_1_MSTR_AXI_CFG_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_1_MSTR_AXI_CFG_SREGR_ADDR, m) +#define HWIO_GCC_PCIE_1_MSTR_AXI_CFG_SREGR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_1_MSTR_AXI_CFG_SREGR_ADDR,v) +#define HWIO_GCC_PCIE_1_MSTR_AXI_CFG_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_1_MSTR_AXI_CFG_SREGR_ADDR,m,v,HWIO_GCC_PCIE_1_MSTR_AXI_CFG_SREGR_IN) +#define HWIO_GCC_PCIE_1_MSTR_AXI_CFG_SREGR_MEM_CORE_OFF_TIMER_BMSK 0xfc000000 +#define HWIO_GCC_PCIE_1_MSTR_AXI_CFG_SREGR_MEM_CORE_OFF_TIMER_SHFT 0x1a +#define HWIO_GCC_PCIE_1_MSTR_AXI_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_BMSK 0x2000000 +#define HWIO_GCC_PCIE_1_MSTR_AXI_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_SHFT 0x19 +#define HWIO_GCC_PCIE_1_MSTR_AXI_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_BMSK 0x1000000 +#define HWIO_GCC_PCIE_1_MSTR_AXI_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_SHFT 0x18 +#define HWIO_GCC_PCIE_1_MSTR_AXI_CFG_SREGR_MEM_PERIPH_ON_STATUS_BMSK 0x800000 +#define HWIO_GCC_PCIE_1_MSTR_AXI_CFG_SREGR_MEM_PERIPH_ON_STATUS_SHFT 0x17 +#define HWIO_GCC_PCIE_1_MSTR_AXI_CFG_SREGR_MEM_CORE_ON_STATUS_BMSK 0x400000 +#define HWIO_GCC_PCIE_1_MSTR_AXI_CFG_SREGR_MEM_CORE_ON_STATUS_SHFT 0x16 +#define HWIO_GCC_PCIE_1_MSTR_AXI_CFG_SREGR_MEM_CPH_TIMER_BMSK 0x3f0000 +#define HWIO_GCC_PCIE_1_MSTR_AXI_CFG_SREGR_MEM_CPH_TIMER_SHFT 0x10 +#define HWIO_GCC_PCIE_1_MSTR_AXI_CFG_SREGR_SLEEP_TIMER_BMSK 0xff00 +#define HWIO_GCC_PCIE_1_MSTR_AXI_CFG_SREGR_SLEEP_TIMER_SHFT 0x8 +#define HWIO_GCC_PCIE_1_MSTR_AXI_CFG_SREGR_WAKEUP_TIMER_BMSK 0xff +#define HWIO_GCC_PCIE_1_MSTR_AXI_CFG_SREGR_WAKEUP_TIMER_SHFT 0x0 + +#define HWIO_GCC_PCIE_1_CFG_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007d034) +#define HWIO_GCC_PCIE_1_CFG_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d034) +#define HWIO_GCC_PCIE_1_CFG_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d034) +#define HWIO_GCC_PCIE_1_CFG_AHB_CBCR_RMSK 0x81d0000e +#define HWIO_GCC_PCIE_1_CFG_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_PCIE_1_CFG_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_1_CFG_AHB_CBCR_ADDR, HWIO_GCC_PCIE_1_CFG_AHB_CBCR_RMSK) +#define HWIO_GCC_PCIE_1_CFG_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_1_CFG_AHB_CBCR_ADDR, m) +#define HWIO_GCC_PCIE_1_CFG_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_1_CFG_AHB_CBCR_ADDR,v) +#define HWIO_GCC_PCIE_1_CFG_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_1_CFG_AHB_CBCR_ADDR,m,v,HWIO_GCC_PCIE_1_CFG_AHB_CBCR_IN) +#define HWIO_GCC_PCIE_1_CFG_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_PCIE_1_CFG_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_PCIE_1_CFG_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_PCIE_1_CFG_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_PCIE_1_CFG_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_PCIE_1_CFG_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_PCIE_1_CFG_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_PCIE_1_CFG_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_PCIE_1_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_PCIE_1_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_PCIE_1_CFG_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_PCIE_1_CFG_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_PCIE_1_CFG_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_PCIE_1_CFG_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_PCIE_1_CFG_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_PCIE_1_CFG_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_PCIE_1_CFG_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_PCIE_1_CFG_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_PCIE_1_CFG_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_CFG_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_1_AUX_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007d038) +#define HWIO_GCC_PCIE_1_AUX_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d038) +#define HWIO_GCC_PCIE_1_AUX_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d038) +#define HWIO_GCC_PCIE_1_AUX_CBCR_RMSK 0x81c07004 +#define HWIO_GCC_PCIE_1_AUX_CBCR_ATTR 0x3 +#define HWIO_GCC_PCIE_1_AUX_CBCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_1_AUX_CBCR_ADDR, HWIO_GCC_PCIE_1_AUX_CBCR_RMSK) +#define HWIO_GCC_PCIE_1_AUX_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_1_AUX_CBCR_ADDR, m) +#define HWIO_GCC_PCIE_1_AUX_CBCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_1_AUX_CBCR_ADDR,v) +#define HWIO_GCC_PCIE_1_AUX_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_1_AUX_CBCR_ADDR,m,v,HWIO_GCC_PCIE_1_AUX_CBCR_IN) +#define HWIO_GCC_PCIE_1_AUX_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_PCIE_1_AUX_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_PCIE_1_AUX_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_PCIE_1_AUX_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_PCIE_1_AUX_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_PCIE_1_AUX_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_PCIE_1_AUX_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_PCIE_1_AUX_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_PCIE_1_AUX_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_PCIE_1_AUX_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_PCIE_1_AUX_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_AUX_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_AUX_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_PCIE_1_AUX_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_PCIE_1_AUX_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_AUX_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_AUX_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_PCIE_1_AUX_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_PCIE_1_AUX_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_AUX_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_AUX_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_PCIE_1_AUX_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_PCIE_1_AUX_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_PCIE_1_AUX_CBCR_CLK_ARES_RESET_FVAL 0x1 + +#define HWIO_GCC_PCIE_1_AUX_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007d03c) +#define HWIO_GCC_PCIE_1_AUX_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d03c) +#define HWIO_GCC_PCIE_1_AUX_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d03c) +#define HWIO_GCC_PCIE_1_AUX_SREGR_RMSK 0xf1ffffe +#define HWIO_GCC_PCIE_1_AUX_SREGR_ATTR 0x3 +#define HWIO_GCC_PCIE_1_AUX_SREGR_IN \ + in_dword_masked(HWIO_GCC_PCIE_1_AUX_SREGR_ADDR, HWIO_GCC_PCIE_1_AUX_SREGR_RMSK) +#define HWIO_GCC_PCIE_1_AUX_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_1_AUX_SREGR_ADDR, m) +#define HWIO_GCC_PCIE_1_AUX_SREGR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_1_AUX_SREGR_ADDR,v) +#define HWIO_GCC_PCIE_1_AUX_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_1_AUX_SREGR_ADDR,m,v,HWIO_GCC_PCIE_1_AUX_SREGR_IN) +#define HWIO_GCC_PCIE_1_AUX_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xf000000 +#define HWIO_GCC_PCIE_1_AUX_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_PCIE_1_AUX_SREGR_PWR_FSM_CLK_SEL_BMSK 0x100000 +#define HWIO_GCC_PCIE_1_AUX_SREGR_PWR_FSM_CLK_SEL_SHFT 0x14 +#define HWIO_GCC_PCIE_1_AUX_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xf0000 +#define HWIO_GCC_PCIE_1_AUX_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_PCIE_1_AUX_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_PCIE_1_AUX_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_PCIE_1_AUX_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_AUX_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_AUX_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_PCIE_1_AUX_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_PCIE_1_AUX_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_AUX_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_AUX_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_PCIE_1_AUX_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_PCIE_1_AUX_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_AUX_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_AUX_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_PCIE_1_AUX_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_PCIE_1_AUX_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_PCIE_1_AUX_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_PCIE_1_AUX_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_PCIE_1_AUX_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_PCIE_1_AUX_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_PCIE_1_AUX_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_PCIE_1_AUX_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_PCIE_1_AUX_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_PCIE_1_AUX_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_PCIE_1_AUX_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_PCIE_1_AUX_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_PCIE_1_AUX_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_PCIE_1_AUX_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_PCIE_1_AUX_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_PCIE_1_AUX_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_AUX_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_AUX_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_PCIE_1_AUX_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_PCIE_1_AUX_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_AUX_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_AUX_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_PCIE_1_AUX_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_PCIE_1_AUX_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_PCIE_1_AUX_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_PCIE_1_AUX_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_PCIE_1_AUX_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_PCIE_1_AUX_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_PCIE_1_AUX_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_PCIE_1_AUX_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_PCIE_1_AUX_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_PCIE_1_AUX_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_PCIE_1_AUX_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_PCIE_1_AUX_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_PCIE_1_AUX_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_PCIE_1_AUX_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_PCIE_1_AUX_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_PCIE_1_AUX_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_PCIE_1_AUX_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_PCIE_1_AUX_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_AUX_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_1_AUX_CFG_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007d040) +#define HWIO_GCC_PCIE_1_AUX_CFG_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d040) +#define HWIO_GCC_PCIE_1_AUX_CFG_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d040) +#define HWIO_GCC_PCIE_1_AUX_CFG_SREGR_RMSK 0xffffffff +#define HWIO_GCC_PCIE_1_AUX_CFG_SREGR_ATTR 0x3 +#define HWIO_GCC_PCIE_1_AUX_CFG_SREGR_IN \ + in_dword_masked(HWIO_GCC_PCIE_1_AUX_CFG_SREGR_ADDR, HWIO_GCC_PCIE_1_AUX_CFG_SREGR_RMSK) +#define HWIO_GCC_PCIE_1_AUX_CFG_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_1_AUX_CFG_SREGR_ADDR, m) +#define HWIO_GCC_PCIE_1_AUX_CFG_SREGR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_1_AUX_CFG_SREGR_ADDR,v) +#define HWIO_GCC_PCIE_1_AUX_CFG_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_1_AUX_CFG_SREGR_ADDR,m,v,HWIO_GCC_PCIE_1_AUX_CFG_SREGR_IN) +#define HWIO_GCC_PCIE_1_AUX_CFG_SREGR_MEM_CORE_OFF_TIMER_BMSK 0xfc000000 +#define HWIO_GCC_PCIE_1_AUX_CFG_SREGR_MEM_CORE_OFF_TIMER_SHFT 0x1a +#define HWIO_GCC_PCIE_1_AUX_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_BMSK 0x2000000 +#define HWIO_GCC_PCIE_1_AUX_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_SHFT 0x19 +#define HWIO_GCC_PCIE_1_AUX_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_BMSK 0x1000000 +#define HWIO_GCC_PCIE_1_AUX_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_SHFT 0x18 +#define HWIO_GCC_PCIE_1_AUX_CFG_SREGR_MEM_PERIPH_ON_STATUS_BMSK 0x800000 +#define HWIO_GCC_PCIE_1_AUX_CFG_SREGR_MEM_PERIPH_ON_STATUS_SHFT 0x17 +#define HWIO_GCC_PCIE_1_AUX_CFG_SREGR_MEM_CORE_ON_STATUS_BMSK 0x400000 +#define HWIO_GCC_PCIE_1_AUX_CFG_SREGR_MEM_CORE_ON_STATUS_SHFT 0x16 +#define HWIO_GCC_PCIE_1_AUX_CFG_SREGR_MEM_CPH_TIMER_BMSK 0x3f0000 +#define HWIO_GCC_PCIE_1_AUX_CFG_SREGR_MEM_CPH_TIMER_SHFT 0x10 +#define HWIO_GCC_PCIE_1_AUX_CFG_SREGR_SLEEP_TIMER_BMSK 0xff00 +#define HWIO_GCC_PCIE_1_AUX_CFG_SREGR_SLEEP_TIMER_SHFT 0x8 +#define HWIO_GCC_PCIE_1_AUX_CFG_SREGR_WAKEUP_TIMER_BMSK 0xff +#define HWIO_GCC_PCIE_1_AUX_CFG_SREGR_WAKEUP_TIMER_SHFT 0x0 + +#define HWIO_GCC_PCIE_1_PHY_AUX_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007d044) +#define HWIO_GCC_PCIE_1_PHY_AUX_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d044) +#define HWIO_GCC_PCIE_1_PHY_AUX_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d044) +#define HWIO_GCC_PCIE_1_PHY_AUX_CBCR_RMSK 0x81c07004 +#define HWIO_GCC_PCIE_1_PHY_AUX_CBCR_ATTR 0x3 +#define HWIO_GCC_PCIE_1_PHY_AUX_CBCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_1_PHY_AUX_CBCR_ADDR, HWIO_GCC_PCIE_1_PHY_AUX_CBCR_RMSK) +#define HWIO_GCC_PCIE_1_PHY_AUX_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_1_PHY_AUX_CBCR_ADDR, m) +#define HWIO_GCC_PCIE_1_PHY_AUX_CBCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_1_PHY_AUX_CBCR_ADDR,v) +#define HWIO_GCC_PCIE_1_PHY_AUX_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_1_PHY_AUX_CBCR_ADDR,m,v,HWIO_GCC_PCIE_1_PHY_AUX_CBCR_IN) +#define HWIO_GCC_PCIE_1_PHY_AUX_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_PCIE_1_PHY_AUX_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_PCIE_1_PHY_AUX_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_PCIE_1_PHY_AUX_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_PCIE_1_PHY_AUX_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_PCIE_1_PHY_AUX_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_PCIE_1_PHY_AUX_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_PCIE_1_PHY_AUX_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_PCIE_1_PHY_AUX_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_PCIE_1_PHY_AUX_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_PCIE_1_PHY_AUX_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_PHY_AUX_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_PHY_AUX_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_PCIE_1_PHY_AUX_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_PCIE_1_PHY_AUX_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_PHY_AUX_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_PHY_AUX_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_PCIE_1_PHY_AUX_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_PCIE_1_PHY_AUX_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_PHY_AUX_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_PHY_AUX_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_PCIE_1_PHY_AUX_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_PCIE_1_PHY_AUX_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_PCIE_1_PHY_AUX_CBCR_CLK_ARES_RESET_FVAL 0x1 + +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007d048) +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d048) +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d048) +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_RMSK 0xf1ffffe +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_ATTR 0x3 +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_IN \ + in_dword_masked(HWIO_GCC_PCIE_1_PHY_AUX_SREGR_ADDR, HWIO_GCC_PCIE_1_PHY_AUX_SREGR_RMSK) +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_1_PHY_AUX_SREGR_ADDR, m) +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_1_PHY_AUX_SREGR_ADDR,v) +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_1_PHY_AUX_SREGR_ADDR,m,v,HWIO_GCC_PCIE_1_PHY_AUX_SREGR_IN) +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xf000000 +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_PWR_FSM_CLK_SEL_BMSK 0x100000 +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_PWR_FSM_CLK_SEL_SHFT 0x14 +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xf0000 +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_PHY_AUX_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_1_PHY_AUX_CFG_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007d04c) +#define HWIO_GCC_PCIE_1_PHY_AUX_CFG_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d04c) +#define HWIO_GCC_PCIE_1_PHY_AUX_CFG_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d04c) +#define HWIO_GCC_PCIE_1_PHY_AUX_CFG_SREGR_RMSK 0xffffffff +#define HWIO_GCC_PCIE_1_PHY_AUX_CFG_SREGR_ATTR 0x3 +#define HWIO_GCC_PCIE_1_PHY_AUX_CFG_SREGR_IN \ + in_dword_masked(HWIO_GCC_PCIE_1_PHY_AUX_CFG_SREGR_ADDR, HWIO_GCC_PCIE_1_PHY_AUX_CFG_SREGR_RMSK) +#define HWIO_GCC_PCIE_1_PHY_AUX_CFG_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_1_PHY_AUX_CFG_SREGR_ADDR, m) +#define HWIO_GCC_PCIE_1_PHY_AUX_CFG_SREGR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_1_PHY_AUX_CFG_SREGR_ADDR,v) +#define HWIO_GCC_PCIE_1_PHY_AUX_CFG_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_1_PHY_AUX_CFG_SREGR_ADDR,m,v,HWIO_GCC_PCIE_1_PHY_AUX_CFG_SREGR_IN) +#define HWIO_GCC_PCIE_1_PHY_AUX_CFG_SREGR_MEM_CORE_OFF_TIMER_BMSK 0xfc000000 +#define HWIO_GCC_PCIE_1_PHY_AUX_CFG_SREGR_MEM_CORE_OFF_TIMER_SHFT 0x1a +#define HWIO_GCC_PCIE_1_PHY_AUX_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_BMSK 0x2000000 +#define HWIO_GCC_PCIE_1_PHY_AUX_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_SHFT 0x19 +#define HWIO_GCC_PCIE_1_PHY_AUX_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_BMSK 0x1000000 +#define HWIO_GCC_PCIE_1_PHY_AUX_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_SHFT 0x18 +#define HWIO_GCC_PCIE_1_PHY_AUX_CFG_SREGR_MEM_PERIPH_ON_STATUS_BMSK 0x800000 +#define HWIO_GCC_PCIE_1_PHY_AUX_CFG_SREGR_MEM_PERIPH_ON_STATUS_SHFT 0x17 +#define HWIO_GCC_PCIE_1_PHY_AUX_CFG_SREGR_MEM_CORE_ON_STATUS_BMSK 0x400000 +#define HWIO_GCC_PCIE_1_PHY_AUX_CFG_SREGR_MEM_CORE_ON_STATUS_SHFT 0x16 +#define HWIO_GCC_PCIE_1_PHY_AUX_CFG_SREGR_MEM_CPH_TIMER_BMSK 0x3f0000 +#define HWIO_GCC_PCIE_1_PHY_AUX_CFG_SREGR_MEM_CPH_TIMER_SHFT 0x10 +#define HWIO_GCC_PCIE_1_PHY_AUX_CFG_SREGR_SLEEP_TIMER_BMSK 0xff00 +#define HWIO_GCC_PCIE_1_PHY_AUX_CFG_SREGR_SLEEP_TIMER_SHFT 0x8 +#define HWIO_GCC_PCIE_1_PHY_AUX_CFG_SREGR_WAKEUP_TIMER_BMSK 0xff +#define HWIO_GCC_PCIE_1_PHY_AUX_CFG_SREGR_WAKEUP_TIMER_SHFT 0x0 + +#define HWIO_GCC_PCIE_1_PIPE_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007d050) +#define HWIO_GCC_PCIE_1_PIPE_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d050) +#define HWIO_GCC_PCIE_1_PIPE_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d050) +#define HWIO_GCC_PCIE_1_PIPE_CBCR_RMSK 0x81c07004 +#define HWIO_GCC_PCIE_1_PIPE_CBCR_ATTR 0x3 +#define HWIO_GCC_PCIE_1_PIPE_CBCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_1_PIPE_CBCR_ADDR, HWIO_GCC_PCIE_1_PIPE_CBCR_RMSK) +#define HWIO_GCC_PCIE_1_PIPE_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_1_PIPE_CBCR_ADDR, m) +#define HWIO_GCC_PCIE_1_PIPE_CBCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_1_PIPE_CBCR_ADDR,v) +#define HWIO_GCC_PCIE_1_PIPE_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_1_PIPE_CBCR_ADDR,m,v,HWIO_GCC_PCIE_1_PIPE_CBCR_IN) +#define HWIO_GCC_PCIE_1_PIPE_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_PCIE_1_PIPE_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_PCIE_1_PIPE_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_PCIE_1_PIPE_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_PCIE_1_PIPE_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_PCIE_1_PIPE_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_PCIE_1_PIPE_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_PCIE_1_PIPE_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_PCIE_1_PIPE_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_PCIE_1_PIPE_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_PCIE_1_PIPE_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_PIPE_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_PIPE_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_PCIE_1_PIPE_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_PCIE_1_PIPE_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_PIPE_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_PIPE_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_PCIE_1_PIPE_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_PCIE_1_PIPE_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_PIPE_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_PIPE_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_PCIE_1_PIPE_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_PCIE_1_PIPE_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_PCIE_1_PIPE_CBCR_CLK_ARES_RESET_FVAL 0x1 + +#define HWIO_GCC_PCIE_1_PIPE_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007d054) +#define HWIO_GCC_PCIE_1_PIPE_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d054) +#define HWIO_GCC_PCIE_1_PIPE_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d054) +#define HWIO_GCC_PCIE_1_PIPE_SREGR_RMSK 0xf1ffffe +#define HWIO_GCC_PCIE_1_PIPE_SREGR_ATTR 0x3 +#define HWIO_GCC_PCIE_1_PIPE_SREGR_IN \ + in_dword_masked(HWIO_GCC_PCIE_1_PIPE_SREGR_ADDR, HWIO_GCC_PCIE_1_PIPE_SREGR_RMSK) +#define HWIO_GCC_PCIE_1_PIPE_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_1_PIPE_SREGR_ADDR, m) +#define HWIO_GCC_PCIE_1_PIPE_SREGR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_1_PIPE_SREGR_ADDR,v) +#define HWIO_GCC_PCIE_1_PIPE_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_1_PIPE_SREGR_ADDR,m,v,HWIO_GCC_PCIE_1_PIPE_SREGR_IN) +#define HWIO_GCC_PCIE_1_PIPE_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xf000000 +#define HWIO_GCC_PCIE_1_PIPE_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_PCIE_1_PIPE_SREGR_PWR_FSM_CLK_SEL_BMSK 0x100000 +#define HWIO_GCC_PCIE_1_PIPE_SREGR_PWR_FSM_CLK_SEL_SHFT 0x14 +#define HWIO_GCC_PCIE_1_PIPE_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xf0000 +#define HWIO_GCC_PCIE_1_PIPE_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_PCIE_1_PIPE_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_PCIE_1_PIPE_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_PCIE_1_PIPE_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_PIPE_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_PIPE_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_PCIE_1_PIPE_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_PCIE_1_PIPE_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_PIPE_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_PIPE_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_PCIE_1_PIPE_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_PCIE_1_PIPE_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_PIPE_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_PIPE_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_PCIE_1_PIPE_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_PCIE_1_PIPE_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_PCIE_1_PIPE_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_PCIE_1_PIPE_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_PCIE_1_PIPE_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_PCIE_1_PIPE_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_PCIE_1_PIPE_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_PCIE_1_PIPE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_PCIE_1_PIPE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_PCIE_1_PIPE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_PCIE_1_PIPE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_PCIE_1_PIPE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_PCIE_1_PIPE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_PCIE_1_PIPE_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_PCIE_1_PIPE_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_PCIE_1_PIPE_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_PIPE_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_PIPE_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_PCIE_1_PIPE_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_PCIE_1_PIPE_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_PIPE_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_PIPE_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_PCIE_1_PIPE_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_PCIE_1_PIPE_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_PCIE_1_PIPE_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_PCIE_1_PIPE_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_PCIE_1_PIPE_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_PCIE_1_PIPE_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_PCIE_1_PIPE_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_PCIE_1_PIPE_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_PCIE_1_PIPE_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_PCIE_1_PIPE_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_PCIE_1_PIPE_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_PCIE_1_PIPE_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_PCIE_1_PIPE_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_PCIE_1_PIPE_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_PCIE_1_PIPE_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_PCIE_1_PIPE_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_PCIE_1_PIPE_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_PCIE_1_PIPE_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_PIPE_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_1_PIPE_CFG_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007d058) +#define HWIO_GCC_PCIE_1_PIPE_CFG_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d058) +#define HWIO_GCC_PCIE_1_PIPE_CFG_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d058) +#define HWIO_GCC_PCIE_1_PIPE_CFG_SREGR_RMSK 0xffffffff +#define HWIO_GCC_PCIE_1_PIPE_CFG_SREGR_ATTR 0x3 +#define HWIO_GCC_PCIE_1_PIPE_CFG_SREGR_IN \ + in_dword_masked(HWIO_GCC_PCIE_1_PIPE_CFG_SREGR_ADDR, HWIO_GCC_PCIE_1_PIPE_CFG_SREGR_RMSK) +#define HWIO_GCC_PCIE_1_PIPE_CFG_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_1_PIPE_CFG_SREGR_ADDR, m) +#define HWIO_GCC_PCIE_1_PIPE_CFG_SREGR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_1_PIPE_CFG_SREGR_ADDR,v) +#define HWIO_GCC_PCIE_1_PIPE_CFG_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_1_PIPE_CFG_SREGR_ADDR,m,v,HWIO_GCC_PCIE_1_PIPE_CFG_SREGR_IN) +#define HWIO_GCC_PCIE_1_PIPE_CFG_SREGR_MEM_CORE_OFF_TIMER_BMSK 0xfc000000 +#define HWIO_GCC_PCIE_1_PIPE_CFG_SREGR_MEM_CORE_OFF_TIMER_SHFT 0x1a +#define HWIO_GCC_PCIE_1_PIPE_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_BMSK 0x2000000 +#define HWIO_GCC_PCIE_1_PIPE_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_SHFT 0x19 +#define HWIO_GCC_PCIE_1_PIPE_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_BMSK 0x1000000 +#define HWIO_GCC_PCIE_1_PIPE_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_SHFT 0x18 +#define HWIO_GCC_PCIE_1_PIPE_CFG_SREGR_MEM_PERIPH_ON_STATUS_BMSK 0x800000 +#define HWIO_GCC_PCIE_1_PIPE_CFG_SREGR_MEM_PERIPH_ON_STATUS_SHFT 0x17 +#define HWIO_GCC_PCIE_1_PIPE_CFG_SREGR_MEM_CORE_ON_STATUS_BMSK 0x400000 +#define HWIO_GCC_PCIE_1_PIPE_CFG_SREGR_MEM_CORE_ON_STATUS_SHFT 0x16 +#define HWIO_GCC_PCIE_1_PIPE_CFG_SREGR_MEM_CPH_TIMER_BMSK 0x3f0000 +#define HWIO_GCC_PCIE_1_PIPE_CFG_SREGR_MEM_CPH_TIMER_SHFT 0x10 +#define HWIO_GCC_PCIE_1_PIPE_CFG_SREGR_SLEEP_TIMER_BMSK 0xff00 +#define HWIO_GCC_PCIE_1_PIPE_CFG_SREGR_SLEEP_TIMER_SHFT 0x8 +#define HWIO_GCC_PCIE_1_PIPE_CFG_SREGR_WAKEUP_TIMER_BMSK 0xff +#define HWIO_GCC_PCIE_1_PIPE_CFG_SREGR_WAKEUP_TIMER_SHFT 0x0 + +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007d05c) +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d05c) +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d05c) +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CBCR_RMSK 0x81c00004 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CBCR_ATTR 0x3 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CBCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_1_PHY_RCHNG_CBCR_ADDR, HWIO_GCC_PCIE_1_PHY_RCHNG_CBCR_RMSK) +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_1_PHY_RCHNG_CBCR_ADDR, m) +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CBCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_1_PHY_RCHNG_CBCR_ADDR,v) +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_1_PHY_RCHNG_CBCR_ADDR,m,v,HWIO_GCC_PCIE_1_PHY_RCHNG_CBCR_IN) +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CBCR_CLK_ARES_RESET_FVAL 0x1 + +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007d060) +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d060) +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d060) +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_PCIE_1_PHY_RCHNG_CMD_RCGR_ADDR, HWIO_GCC_PCIE_1_PHY_RCHNG_CMD_RCGR_RMSK) +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_1_PHY_RCHNG_CMD_RCGR_ADDR, m) +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_1_PHY_RCHNG_CMD_RCGR_ADDR,v) +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_1_PHY_RCHNG_CMD_RCGR_ADDR,m,v,HWIO_GCC_PCIE_1_PHY_RCHNG_CMD_RCGR_IN) +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007d064) +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d064) +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d064) +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_ADDR, HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_RMSK) +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_ADDR, m) +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_ADDR,v) +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_ADDR,m,v,HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_IN) +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_PCIE_1_PHY_RCHNG_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_PCIE_1_AUX_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007d07c) +#define HWIO_GCC_PCIE_1_AUX_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d07c) +#define HWIO_GCC_PCIE_1_AUX_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d07c) +#define HWIO_GCC_PCIE_1_AUX_CMD_RCGR_RMSK 0x800000f3 +#define HWIO_GCC_PCIE_1_AUX_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_PCIE_1_AUX_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_PCIE_1_AUX_CMD_RCGR_ADDR, HWIO_GCC_PCIE_1_AUX_CMD_RCGR_RMSK) +#define HWIO_GCC_PCIE_1_AUX_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_1_AUX_CMD_RCGR_ADDR, m) +#define HWIO_GCC_PCIE_1_AUX_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_1_AUX_CMD_RCGR_ADDR,v) +#define HWIO_GCC_PCIE_1_AUX_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_1_AUX_CMD_RCGR_ADDR,m,v,HWIO_GCC_PCIE_1_AUX_CMD_RCGR_IN) +#define HWIO_GCC_PCIE_1_AUX_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_PCIE_1_AUX_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_PCIE_1_AUX_CMD_RCGR_DIRTY_D_BMSK 0x80 +#define HWIO_GCC_PCIE_1_AUX_CMD_RCGR_DIRTY_D_SHFT 0x7 +#define HWIO_GCC_PCIE_1_AUX_CMD_RCGR_DIRTY_N_BMSK 0x40 +#define HWIO_GCC_PCIE_1_AUX_CMD_RCGR_DIRTY_N_SHFT 0x6 +#define HWIO_GCC_PCIE_1_AUX_CMD_RCGR_DIRTY_M_BMSK 0x20 +#define HWIO_GCC_PCIE_1_AUX_CMD_RCGR_DIRTY_M_SHFT 0x5 +#define HWIO_GCC_PCIE_1_AUX_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_PCIE_1_AUX_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_PCIE_1_AUX_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_PCIE_1_AUX_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_PCIE_1_AUX_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_AUX_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_AUX_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_PCIE_1_AUX_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_PCIE_1_AUX_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_AUX_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007d080) +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d080) +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d080) +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_RMSK 0x10371f +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_PCIE_1_AUX_CFG_RCGR_ADDR, HWIO_GCC_PCIE_1_AUX_CFG_RCGR_RMSK) +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_1_AUX_CFG_RCGR_ADDR, m) +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_1_AUX_CFG_RCGR_ADDR,v) +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_1_AUX_CFG_RCGR_ADDR,m,v,HWIO_GCC_PCIE_1_AUX_CFG_RCGR_IN) +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_MODE_BMSK 0x3000 +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_MODE_SHFT 0xc +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_PCIE_1_AUX_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007d084) +#define HWIO_GCC_PCIE_1_AUX_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d084) +#define HWIO_GCC_PCIE_1_AUX_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d084) +#define HWIO_GCC_PCIE_1_AUX_M_RMSK 0xffff +#define HWIO_GCC_PCIE_1_AUX_M_ATTR 0x3 +#define HWIO_GCC_PCIE_1_AUX_M_IN \ + in_dword_masked(HWIO_GCC_PCIE_1_AUX_M_ADDR, HWIO_GCC_PCIE_1_AUX_M_RMSK) +#define HWIO_GCC_PCIE_1_AUX_M_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_1_AUX_M_ADDR, m) +#define HWIO_GCC_PCIE_1_AUX_M_OUT(v) \ + out_dword(HWIO_GCC_PCIE_1_AUX_M_ADDR,v) +#define HWIO_GCC_PCIE_1_AUX_M_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_1_AUX_M_ADDR,m,v,HWIO_GCC_PCIE_1_AUX_M_IN) +#define HWIO_GCC_PCIE_1_AUX_M_M_BMSK 0xffff +#define HWIO_GCC_PCIE_1_AUX_M_M_SHFT 0x0 + +#define HWIO_GCC_PCIE_1_AUX_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007d088) +#define HWIO_GCC_PCIE_1_AUX_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d088) +#define HWIO_GCC_PCIE_1_AUX_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d088) +#define HWIO_GCC_PCIE_1_AUX_N_RMSK 0xffff +#define HWIO_GCC_PCIE_1_AUX_N_ATTR 0x3 +#define HWIO_GCC_PCIE_1_AUX_N_IN \ + in_dword_masked(HWIO_GCC_PCIE_1_AUX_N_ADDR, HWIO_GCC_PCIE_1_AUX_N_RMSK) +#define HWIO_GCC_PCIE_1_AUX_N_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_1_AUX_N_ADDR, m) +#define HWIO_GCC_PCIE_1_AUX_N_OUT(v) \ + out_dword(HWIO_GCC_PCIE_1_AUX_N_ADDR,v) +#define HWIO_GCC_PCIE_1_AUX_N_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_1_AUX_N_ADDR,m,v,HWIO_GCC_PCIE_1_AUX_N_IN) +#define HWIO_GCC_PCIE_1_AUX_N_NOT_N_MINUS_M_BMSK 0xffff +#define HWIO_GCC_PCIE_1_AUX_N_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_PCIE_1_AUX_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007d08c) +#define HWIO_GCC_PCIE_1_AUX_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d08c) +#define HWIO_GCC_PCIE_1_AUX_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d08c) +#define HWIO_GCC_PCIE_1_AUX_D_RMSK 0xffff +#define HWIO_GCC_PCIE_1_AUX_D_ATTR 0x3 +#define HWIO_GCC_PCIE_1_AUX_D_IN \ + in_dword_masked(HWIO_GCC_PCIE_1_AUX_D_ADDR, HWIO_GCC_PCIE_1_AUX_D_RMSK) +#define HWIO_GCC_PCIE_1_AUX_D_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_1_AUX_D_ADDR, m) +#define HWIO_GCC_PCIE_1_AUX_D_OUT(v) \ + out_dword(HWIO_GCC_PCIE_1_AUX_D_ADDR,v) +#define HWIO_GCC_PCIE_1_AUX_D_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_1_AUX_D_ADDR,m,v,HWIO_GCC_PCIE_1_AUX_D_IN) +#define HWIO_GCC_PCIE_1_AUX_D_NOT_2D_BMSK 0xffff +#define HWIO_GCC_PCIE_1_AUX_D_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_PCIE_1_PHY_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007e000) +#define HWIO_GCC_PCIE_1_PHY_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007e000) +#define HWIO_GCC_PCIE_1_PHY_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007e000) +#define HWIO_GCC_PCIE_1_PHY_GDSCR_RMSK 0xf8ffffff +#define HWIO_GCC_PCIE_1_PHY_GDSCR_ATTR 0x3 +#define HWIO_GCC_PCIE_1_PHY_GDSCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_1_PHY_GDSCR_ADDR, HWIO_GCC_PCIE_1_PHY_GDSCR_RMSK) +#define HWIO_GCC_PCIE_1_PHY_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_1_PHY_GDSCR_ADDR, m) +#define HWIO_GCC_PCIE_1_PHY_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_1_PHY_GDSCR_ADDR,v) +#define HWIO_GCC_PCIE_1_PHY_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_1_PHY_GDSCR_ADDR,m,v,HWIO_GCC_PCIE_1_PHY_GDSCR_IN) +#define HWIO_GCC_PCIE_1_PHY_GDSCR_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_PCIE_1_PHY_GDSCR_PWR_ON_SHFT 0x1f +#define HWIO_GCC_PCIE_1_PHY_GDSCR_GDSC_STATE_BMSK 0x78000000 +#define HWIO_GCC_PCIE_1_PHY_GDSCR_GDSC_STATE_SHFT 0x1b +#define HWIO_GCC_PCIE_1_PHY_GDSCR_EN_REST_WAIT_BMSK 0xf00000 +#define HWIO_GCC_PCIE_1_PHY_GDSCR_EN_REST_WAIT_SHFT 0x14 +#define HWIO_GCC_PCIE_1_PHY_GDSCR_EN_FEW_WAIT_BMSK 0xf0000 +#define HWIO_GCC_PCIE_1_PHY_GDSCR_EN_FEW_WAIT_SHFT 0x10 +#define HWIO_GCC_PCIE_1_PHY_GDSCR_CLK_DIS_WAIT_BMSK 0xf000 +#define HWIO_GCC_PCIE_1_PHY_GDSCR_CLK_DIS_WAIT_SHFT 0xc +#define HWIO_GCC_PCIE_1_PHY_GDSCR_RETAIN_FF_ENABLE_BMSK 0x800 +#define HWIO_GCC_PCIE_1_PHY_GDSCR_RETAIN_FF_ENABLE_SHFT 0xb +#define HWIO_GCC_PCIE_1_PHY_GDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_PHY_GDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_PHY_GDSCR_RESTORE_BMSK 0x400 +#define HWIO_GCC_PCIE_1_PHY_GDSCR_RESTORE_SHFT 0xa +#define HWIO_GCC_PCIE_1_PHY_GDSCR_RESTORE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_PHY_GDSCR_RESTORE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_PHY_GDSCR_SAVE_BMSK 0x200 +#define HWIO_GCC_PCIE_1_PHY_GDSCR_SAVE_SHFT 0x9 +#define HWIO_GCC_PCIE_1_PHY_GDSCR_SAVE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_PHY_GDSCR_SAVE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_PHY_GDSCR_RETAIN_BMSK 0x100 +#define HWIO_GCC_PCIE_1_PHY_GDSCR_RETAIN_SHFT 0x8 +#define HWIO_GCC_PCIE_1_PHY_GDSCR_RETAIN_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_PHY_GDSCR_RETAIN_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_PHY_GDSCR_EN_REST_BMSK 0x80 +#define HWIO_GCC_PCIE_1_PHY_GDSCR_EN_REST_SHFT 0x7 +#define HWIO_GCC_PCIE_1_PHY_GDSCR_EN_REST_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_PHY_GDSCR_EN_REST_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_PHY_GDSCR_EN_FEW_BMSK 0x40 +#define HWIO_GCC_PCIE_1_PHY_GDSCR_EN_FEW_SHFT 0x6 +#define HWIO_GCC_PCIE_1_PHY_GDSCR_EN_FEW_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_PHY_GDSCR_EN_FEW_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_PHY_GDSCR_CLAMP_IO_BMSK 0x20 +#define HWIO_GCC_PCIE_1_PHY_GDSCR_CLAMP_IO_SHFT 0x5 +#define HWIO_GCC_PCIE_1_PHY_GDSCR_CLAMP_IO_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_PHY_GDSCR_CLAMP_IO_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_PHY_GDSCR_CLK_DISABLE_BMSK 0x10 +#define HWIO_GCC_PCIE_1_PHY_GDSCR_CLK_DISABLE_SHFT 0x4 +#define HWIO_GCC_PCIE_1_PHY_GDSCR_CLK_DISABLE_CLK_NOT_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_PHY_GDSCR_CLK_DISABLE_CLK_IS_DISABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_PHY_GDSCR_PD_ARES_BMSK 0x8 +#define HWIO_GCC_PCIE_1_PHY_GDSCR_PD_ARES_SHFT 0x3 +#define HWIO_GCC_PCIE_1_PHY_GDSCR_PD_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_PCIE_1_PHY_GDSCR_PD_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_PCIE_1_PHY_GDSCR_SW_OVERRIDE_BMSK 0x4 +#define HWIO_GCC_PCIE_1_PHY_GDSCR_SW_OVERRIDE_SHFT 0x2 +#define HWIO_GCC_PCIE_1_PHY_GDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_PHY_GDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_PHY_GDSCR_HW_CONTROL_BMSK 0x2 +#define HWIO_GCC_PCIE_1_PHY_GDSCR_HW_CONTROL_SHFT 0x1 +#define HWIO_GCC_PCIE_1_PHY_GDSCR_HW_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_PHY_GDSCR_HW_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_PHY_GDSCR_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_PCIE_1_PHY_GDSCR_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_PCIE_1_PHY_GDSCR_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_PHY_GDSCR_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_1_PHY_CFG_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007e004) +#define HWIO_GCC_PCIE_1_PHY_CFG_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007e004) +#define HWIO_GCC_PCIE_1_PHY_CFG_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007e004) +#define HWIO_GCC_PCIE_1_PHY_CFG_GDSCR_RMSK 0x7ffffff +#define HWIO_GCC_PCIE_1_PHY_CFG_GDSCR_ATTR 0x3 +#define HWIO_GCC_PCIE_1_PHY_CFG_GDSCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_1_PHY_CFG_GDSCR_ADDR, HWIO_GCC_PCIE_1_PHY_CFG_GDSCR_RMSK) +#define HWIO_GCC_PCIE_1_PHY_CFG_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_1_PHY_CFG_GDSCR_ADDR, m) +#define HWIO_GCC_PCIE_1_PHY_CFG_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_1_PHY_CFG_GDSCR_ADDR,v) +#define HWIO_GCC_PCIE_1_PHY_CFG_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_1_PHY_CFG_GDSCR_ADDR,m,v,HWIO_GCC_PCIE_1_PHY_CFG_GDSCR_IN) +#define HWIO_GCC_PCIE_1_PHY_CFG_GDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4000000 +#define HWIO_GCC_PCIE_1_PHY_CFG_GDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x1a +#define HWIO_GCC_PCIE_1_PHY_CFG_GDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_PHY_CFG_GDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_PHY_CFG_GDSCR_GDSC_PWR_DWN_START_BMSK 0x2000000 +#define HWIO_GCC_PCIE_1_PHY_CFG_GDSCR_GDSC_PWR_DWN_START_SHFT 0x19 +#define HWIO_GCC_PCIE_1_PHY_CFG_GDSCR_GDSC_PWR_UP_START_BMSK 0x1000000 +#define HWIO_GCC_PCIE_1_PHY_CFG_GDSCR_GDSC_PWR_UP_START_SHFT 0x18 +#define HWIO_GCC_PCIE_1_PHY_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_BMSK 0xf00000 +#define HWIO_GCC_PCIE_1_PHY_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_SHFT 0x14 +#define HWIO_GCC_PCIE_1_PHY_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_BMSK 0x80000 +#define HWIO_GCC_PCIE_1_PHY_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_SHFT 0x13 +#define HWIO_GCC_PCIE_1_PHY_CFG_GDSCR_GDSC_ENR_ACK_STATUS_BMSK 0x40000 +#define HWIO_GCC_PCIE_1_PHY_CFG_GDSCR_GDSC_ENR_ACK_STATUS_SHFT 0x12 +#define HWIO_GCC_PCIE_1_PHY_CFG_GDSCR_GDSC_ENF_ACK_STATUS_BMSK 0x20000 +#define HWIO_GCC_PCIE_1_PHY_CFG_GDSCR_GDSC_ENF_ACK_STATUS_SHFT 0x11 +#define HWIO_GCC_PCIE_1_PHY_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_BMSK 0x10000 +#define HWIO_GCC_PCIE_1_PHY_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_SHFT 0x10 +#define HWIO_GCC_PCIE_1_PHY_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_BMSK 0x8000 +#define HWIO_GCC_PCIE_1_PHY_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_SHFT 0xf +#define HWIO_GCC_PCIE_1_PHY_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_BMSK 0x7800 +#define HWIO_GCC_PCIE_1_PHY_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_SHFT 0xb +#define HWIO_GCC_PCIE_1_PHY_CFG_GDSCR_GDSC_HANDSHAKE_DIS_BMSK 0x400 +#define HWIO_GCC_PCIE_1_PHY_CFG_GDSCR_GDSC_HANDSHAKE_DIS_SHFT 0xa +#define HWIO_GCC_PCIE_1_PHY_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_BMSK 0x200 +#define HWIO_GCC_PCIE_1_PHY_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_SHFT 0x9 +#define HWIO_GCC_PCIE_1_PHY_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_BMSK 0x100 +#define HWIO_GCC_PCIE_1_PHY_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_SHFT 0x8 +#define HWIO_GCC_PCIE_1_PHY_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_BMSK 0x80 +#define HWIO_GCC_PCIE_1_PHY_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_SHFT 0x7 +#define HWIO_GCC_PCIE_1_PHY_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_BMSK 0x60 +#define HWIO_GCC_PCIE_1_PHY_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_SHFT 0x5 +#define HWIO_GCC_PCIE_1_PHY_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_BMSK 0x10 +#define HWIO_GCC_PCIE_1_PHY_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_SHFT 0x4 +#define HWIO_GCC_PCIE_1_PHY_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_BMSK 0x8 +#define HWIO_GCC_PCIE_1_PHY_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_SHFT 0x3 +#define HWIO_GCC_PCIE_1_PHY_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_BMSK 0x4 +#define HWIO_GCC_PCIE_1_PHY_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_SHFT 0x2 +#define HWIO_GCC_PCIE_1_PHY_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_BMSK 0x2 +#define HWIO_GCC_PCIE_1_PHY_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_SHFT 0x1 +#define HWIO_GCC_PCIE_1_PHY_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_PCIE_1_PHY_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_SHFT 0x0 + +#define HWIO_GCC_PCIE_1_PHY_CFG2_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007e008) +#define HWIO_GCC_PCIE_1_PHY_CFG2_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007e008) +#define HWIO_GCC_PCIE_1_PHY_CFG2_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007e008) +#define HWIO_GCC_PCIE_1_PHY_CFG2_GDSCR_RMSK 0x7ffff +#define HWIO_GCC_PCIE_1_PHY_CFG2_GDSCR_ATTR 0x3 +#define HWIO_GCC_PCIE_1_PHY_CFG2_GDSCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_1_PHY_CFG2_GDSCR_ADDR, HWIO_GCC_PCIE_1_PHY_CFG2_GDSCR_RMSK) +#define HWIO_GCC_PCIE_1_PHY_CFG2_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_1_PHY_CFG2_GDSCR_ADDR, m) +#define HWIO_GCC_PCIE_1_PHY_CFG2_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_1_PHY_CFG2_GDSCR_ADDR,v) +#define HWIO_GCC_PCIE_1_PHY_CFG2_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_1_PHY_CFG2_GDSCR_ADDR,m,v,HWIO_GCC_PCIE_1_PHY_CFG2_GDSCR_IN) +#define HWIO_GCC_PCIE_1_PHY_CFG2_GDSCR_GDSC_MEM_PWRUP_ACK_OVERRIDE_BMSK 0x40000 +#define HWIO_GCC_PCIE_1_PHY_CFG2_GDSCR_GDSC_MEM_PWRUP_ACK_OVERRIDE_SHFT 0x12 +#define HWIO_GCC_PCIE_1_PHY_CFG2_GDSCR_GDSC_PWRDWN_ENABLE_ACK_OVERRIDE_BMSK 0x20000 +#define HWIO_GCC_PCIE_1_PHY_CFG2_GDSCR_GDSC_PWRDWN_ENABLE_ACK_OVERRIDE_SHFT 0x11 +#define HWIO_GCC_PCIE_1_PHY_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_BMSK 0x10000 +#define HWIO_GCC_PCIE_1_PHY_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_SHFT 0x10 +#define HWIO_GCC_PCIE_1_PHY_CFG2_GDSCR_DLY_MEM_PWR_UP_BMSK 0xf000 +#define HWIO_GCC_PCIE_1_PHY_CFG2_GDSCR_DLY_MEM_PWR_UP_SHFT 0xc +#define HWIO_GCC_PCIE_1_PHY_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_BMSK 0xf00 +#define HWIO_GCC_PCIE_1_PHY_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_SHFT 0x8 +#define HWIO_GCC_PCIE_1_PHY_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_BMSK 0xf0 +#define HWIO_GCC_PCIE_1_PHY_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_SHFT 0x4 +#define HWIO_GCC_PCIE_1_PHY_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_BMSK 0xf +#define HWIO_GCC_PCIE_1_PHY_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_SHFT 0x0 + +#define HWIO_GCC_PCIE_1_PHY_CFG3_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007e00c) +#define HWIO_GCC_PCIE_1_PHY_CFG3_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007e00c) +#define HWIO_GCC_PCIE_1_PHY_CFG3_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007e00c) +#define HWIO_GCC_PCIE_1_PHY_CFG3_GDSCR_RMSK 0x7ffffff +#define HWIO_GCC_PCIE_1_PHY_CFG3_GDSCR_ATTR 0x3 +#define HWIO_GCC_PCIE_1_PHY_CFG3_GDSCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_1_PHY_CFG3_GDSCR_ADDR, HWIO_GCC_PCIE_1_PHY_CFG3_GDSCR_RMSK) +#define HWIO_GCC_PCIE_1_PHY_CFG3_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_1_PHY_CFG3_GDSCR_ADDR, m) +#define HWIO_GCC_PCIE_1_PHY_CFG3_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_1_PHY_CFG3_GDSCR_ADDR,v) +#define HWIO_GCC_PCIE_1_PHY_CFG3_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_1_PHY_CFG3_GDSCR_ADDR,m,v,HWIO_GCC_PCIE_1_PHY_CFG3_GDSCR_IN) +#define HWIO_GCC_PCIE_1_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_STATUS_BMSK 0x4000000 +#define HWIO_GCC_PCIE_1_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_STATUS_SHFT 0x1a +#define HWIO_GCC_PCIE_1_PHY_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_BMSK 0x2000000 +#define HWIO_GCC_PCIE_1_PHY_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_SHFT 0x19 +#define HWIO_GCC_PCIE_1_PHY_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_PHY_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_PHY_CFG3_GDSCR_DLY_ACCU_RED_SHIFTER_DONE_BMSK 0x1e00000 +#define HWIO_GCC_PCIE_1_PHY_CFG3_GDSCR_DLY_ACCU_RED_SHIFTER_DONE_SHFT 0x15 +#define HWIO_GCC_PCIE_1_PHY_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_BMSK 0x100000 +#define HWIO_GCC_PCIE_1_PHY_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_SHFT 0x14 +#define HWIO_GCC_PCIE_1_PHY_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_PHY_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_BMSK 0x80000 +#define HWIO_GCC_PCIE_1_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_SHFT 0x13 +#define HWIO_GCC_PCIE_1_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_BMSK 0x40000 +#define HWIO_GCC_PCIE_1_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_SHFT 0x12 +#define HWIO_GCC_PCIE_1_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_BMSK 0x20000 +#define HWIO_GCC_PCIE_1_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_SHFT 0x11 +#define HWIO_GCC_PCIE_1_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_BMSK 0x10000 +#define HWIO_GCC_PCIE_1_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_SHFT 0x10 +#define HWIO_GCC_PCIE_1_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_PHY_CFG3_GDSCR_GDSC_SPARE_CTRL_IN_BMSK 0xff00 +#define HWIO_GCC_PCIE_1_PHY_CFG3_GDSCR_GDSC_SPARE_CTRL_IN_SHFT 0x8 +#define HWIO_GCC_PCIE_1_PHY_CFG3_GDSCR_GDSC_SPARE_CTRL_OUT_BMSK 0xff +#define HWIO_GCC_PCIE_1_PHY_CFG3_GDSCR_GDSC_SPARE_CTRL_OUT_SHFT 0x0 + +#define HWIO_GCC_PCIE_1_PHY_CFG4_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007e010) +#define HWIO_GCC_PCIE_1_PHY_CFG4_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007e010) +#define HWIO_GCC_PCIE_1_PHY_CFG4_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007e010) +#define HWIO_GCC_PCIE_1_PHY_CFG4_GDSCR_RMSK 0xffffff +#define HWIO_GCC_PCIE_1_PHY_CFG4_GDSCR_ATTR 0x3 +#define HWIO_GCC_PCIE_1_PHY_CFG4_GDSCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_1_PHY_CFG4_GDSCR_ADDR, HWIO_GCC_PCIE_1_PHY_CFG4_GDSCR_RMSK) +#define HWIO_GCC_PCIE_1_PHY_CFG4_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_1_PHY_CFG4_GDSCR_ADDR, m) +#define HWIO_GCC_PCIE_1_PHY_CFG4_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_1_PHY_CFG4_GDSCR_ADDR,v) +#define HWIO_GCC_PCIE_1_PHY_CFG4_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_1_PHY_CFG4_GDSCR_ADDR,m,v,HWIO_GCC_PCIE_1_PHY_CFG4_GDSCR_IN) +#define HWIO_GCC_PCIE_1_PHY_CFG4_GDSCR_DLY_UNCLAMPIO_BMSK 0xf00000 +#define HWIO_GCC_PCIE_1_PHY_CFG4_GDSCR_DLY_UNCLAMPIO_SHFT 0x14 +#define HWIO_GCC_PCIE_1_PHY_CFG4_GDSCR_DLY_RESTOREFF_BMSK 0xf0000 +#define HWIO_GCC_PCIE_1_PHY_CFG4_GDSCR_DLY_RESTOREFF_SHFT 0x10 +#define HWIO_GCC_PCIE_1_PHY_CFG4_GDSCR_DLY_NORETAINFF_BMSK 0xf000 +#define HWIO_GCC_PCIE_1_PHY_CFG4_GDSCR_DLY_NORETAINFF_SHFT 0xc +#define HWIO_GCC_PCIE_1_PHY_CFG4_GDSCR_DLY_DEASSERTARES_BMSK 0xf00 +#define HWIO_GCC_PCIE_1_PHY_CFG4_GDSCR_DLY_DEASSERTARES_SHFT 0x8 +#define HWIO_GCC_PCIE_1_PHY_CFG4_GDSCR_DLY_CLAMPIO_BMSK 0xf0 +#define HWIO_GCC_PCIE_1_PHY_CFG4_GDSCR_DLY_CLAMPIO_SHFT 0x4 +#define HWIO_GCC_PCIE_1_PHY_CFG4_GDSCR_DLY_RETAINFF_BMSK 0xf +#define HWIO_GCC_PCIE_1_PHY_CFG4_GDSCR_DLY_RETAINFF_SHFT 0x0 + +#define HWIO_GCC_PCIE_PHY_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005f000) +#define HWIO_GCC_PCIE_PHY_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005f000) +#define HWIO_GCC_PCIE_PHY_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005f000) +#define HWIO_GCC_PCIE_PHY_BCR_RMSK 0x1 +#define HWIO_GCC_PCIE_PHY_BCR_ATTR 0x3 +#define HWIO_GCC_PCIE_PHY_BCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_PHY_BCR_ADDR, HWIO_GCC_PCIE_PHY_BCR_RMSK) +#define HWIO_GCC_PCIE_PHY_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_PHY_BCR_ADDR, m) +#define HWIO_GCC_PCIE_PHY_BCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_PHY_BCR_ADDR,v) +#define HWIO_GCC_PCIE_PHY_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_PHY_BCR_ADDR,m,v,HWIO_GCC_PCIE_PHY_BCR_IN) +#define HWIO_GCC_PCIE_PHY_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_PCIE_PHY_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_PCIE_PHY_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_PHY_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008e000) +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008e000) +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008e000) +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_RMSK 0xf8ffffff +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_ATTR 0x3 +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_IN \ + in_dword_masked(HWIO_GCC_UFS_MEM_PHY_GDSCR_ADDR, HWIO_GCC_UFS_MEM_PHY_GDSCR_RMSK) +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_UFS_MEM_PHY_GDSCR_ADDR, m) +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_UFS_MEM_PHY_GDSCR_ADDR,v) +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_UFS_MEM_PHY_GDSCR_ADDR,m,v,HWIO_GCC_UFS_MEM_PHY_GDSCR_IN) +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_PWR_ON_SHFT 0x1f +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_GDSC_STATE_BMSK 0x78000000 +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_GDSC_STATE_SHFT 0x1b +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_EN_REST_WAIT_BMSK 0xf00000 +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_EN_REST_WAIT_SHFT 0x14 +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_EN_FEW_WAIT_BMSK 0xf0000 +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_EN_FEW_WAIT_SHFT 0x10 +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_CLK_DIS_WAIT_BMSK 0xf000 +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_CLK_DIS_WAIT_SHFT 0xc +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_RETAIN_FF_ENABLE_BMSK 0x800 +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_RETAIN_FF_ENABLE_SHFT 0xb +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_RESTORE_BMSK 0x400 +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_RESTORE_SHFT 0xa +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_RESTORE_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_RESTORE_ENABLE_FVAL 0x1 +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_SAVE_BMSK 0x200 +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_SAVE_SHFT 0x9 +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_SAVE_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_SAVE_ENABLE_FVAL 0x1 +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_RETAIN_BMSK 0x100 +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_RETAIN_SHFT 0x8 +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_RETAIN_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_RETAIN_ENABLE_FVAL 0x1 +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_EN_REST_BMSK 0x80 +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_EN_REST_SHFT 0x7 +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_EN_REST_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_EN_REST_ENABLE_FVAL 0x1 +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_EN_FEW_BMSK 0x40 +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_EN_FEW_SHFT 0x6 +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_EN_FEW_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_EN_FEW_ENABLE_FVAL 0x1 +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_CLAMP_IO_BMSK 0x20 +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_CLAMP_IO_SHFT 0x5 +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_CLAMP_IO_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_CLAMP_IO_ENABLE_FVAL 0x1 +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_CLK_DISABLE_BMSK 0x10 +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_CLK_DISABLE_SHFT 0x4 +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_CLK_DISABLE_CLK_NOT_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_CLK_DISABLE_CLK_IS_DISABLE_FVAL 0x1 +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_PD_ARES_BMSK 0x8 +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_PD_ARES_SHFT 0x3 +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_PD_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_PD_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_SW_OVERRIDE_BMSK 0x4 +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_SW_OVERRIDE_SHFT 0x2 +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_HW_CONTROL_BMSK 0x2 +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_HW_CONTROL_SHFT 0x1 +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_HW_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_HW_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_MEM_PHY_GDSCR_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_UFS_MEM_PHY_CFG_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008e004) +#define HWIO_GCC_UFS_MEM_PHY_CFG_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008e004) +#define HWIO_GCC_UFS_MEM_PHY_CFG_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008e004) +#define HWIO_GCC_UFS_MEM_PHY_CFG_GDSCR_RMSK 0x7ffffff +#define HWIO_GCC_UFS_MEM_PHY_CFG_GDSCR_ATTR 0x3 +#define HWIO_GCC_UFS_MEM_PHY_CFG_GDSCR_IN \ + in_dword_masked(HWIO_GCC_UFS_MEM_PHY_CFG_GDSCR_ADDR, HWIO_GCC_UFS_MEM_PHY_CFG_GDSCR_RMSK) +#define HWIO_GCC_UFS_MEM_PHY_CFG_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_UFS_MEM_PHY_CFG_GDSCR_ADDR, m) +#define HWIO_GCC_UFS_MEM_PHY_CFG_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_UFS_MEM_PHY_CFG_GDSCR_ADDR,v) +#define HWIO_GCC_UFS_MEM_PHY_CFG_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_UFS_MEM_PHY_CFG_GDSCR_ADDR,m,v,HWIO_GCC_UFS_MEM_PHY_CFG_GDSCR_IN) +#define HWIO_GCC_UFS_MEM_PHY_CFG_GDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4000000 +#define HWIO_GCC_UFS_MEM_PHY_CFG_GDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x1a +#define HWIO_GCC_UFS_MEM_PHY_CFG_GDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_MEM_PHY_CFG_GDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_UFS_MEM_PHY_CFG_GDSCR_GDSC_PWR_DWN_START_BMSK 0x2000000 +#define HWIO_GCC_UFS_MEM_PHY_CFG_GDSCR_GDSC_PWR_DWN_START_SHFT 0x19 +#define HWIO_GCC_UFS_MEM_PHY_CFG_GDSCR_GDSC_PWR_UP_START_BMSK 0x1000000 +#define HWIO_GCC_UFS_MEM_PHY_CFG_GDSCR_GDSC_PWR_UP_START_SHFT 0x18 +#define HWIO_GCC_UFS_MEM_PHY_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_BMSK 0xf00000 +#define HWIO_GCC_UFS_MEM_PHY_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_SHFT 0x14 +#define HWIO_GCC_UFS_MEM_PHY_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_BMSK 0x80000 +#define HWIO_GCC_UFS_MEM_PHY_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_SHFT 0x13 +#define HWIO_GCC_UFS_MEM_PHY_CFG_GDSCR_GDSC_ENR_ACK_STATUS_BMSK 0x40000 +#define HWIO_GCC_UFS_MEM_PHY_CFG_GDSCR_GDSC_ENR_ACK_STATUS_SHFT 0x12 +#define HWIO_GCC_UFS_MEM_PHY_CFG_GDSCR_GDSC_ENF_ACK_STATUS_BMSK 0x20000 +#define HWIO_GCC_UFS_MEM_PHY_CFG_GDSCR_GDSC_ENF_ACK_STATUS_SHFT 0x11 +#define HWIO_GCC_UFS_MEM_PHY_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_BMSK 0x10000 +#define HWIO_GCC_UFS_MEM_PHY_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_SHFT 0x10 +#define HWIO_GCC_UFS_MEM_PHY_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_BMSK 0x8000 +#define HWIO_GCC_UFS_MEM_PHY_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_SHFT 0xf +#define HWIO_GCC_UFS_MEM_PHY_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_BMSK 0x7800 +#define HWIO_GCC_UFS_MEM_PHY_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_SHFT 0xb +#define HWIO_GCC_UFS_MEM_PHY_CFG_GDSCR_GDSC_HANDSHAKE_DIS_BMSK 0x400 +#define HWIO_GCC_UFS_MEM_PHY_CFG_GDSCR_GDSC_HANDSHAKE_DIS_SHFT 0xa +#define HWIO_GCC_UFS_MEM_PHY_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_BMSK 0x200 +#define HWIO_GCC_UFS_MEM_PHY_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_SHFT 0x9 +#define HWIO_GCC_UFS_MEM_PHY_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_BMSK 0x100 +#define HWIO_GCC_UFS_MEM_PHY_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_SHFT 0x8 +#define HWIO_GCC_UFS_MEM_PHY_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_BMSK 0x80 +#define HWIO_GCC_UFS_MEM_PHY_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_SHFT 0x7 +#define HWIO_GCC_UFS_MEM_PHY_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_BMSK 0x60 +#define HWIO_GCC_UFS_MEM_PHY_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_SHFT 0x5 +#define HWIO_GCC_UFS_MEM_PHY_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_BMSK 0x10 +#define HWIO_GCC_UFS_MEM_PHY_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_SHFT 0x4 +#define HWIO_GCC_UFS_MEM_PHY_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_BMSK 0x8 +#define HWIO_GCC_UFS_MEM_PHY_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_SHFT 0x3 +#define HWIO_GCC_UFS_MEM_PHY_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_BMSK 0x4 +#define HWIO_GCC_UFS_MEM_PHY_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_SHFT 0x2 +#define HWIO_GCC_UFS_MEM_PHY_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_BMSK 0x2 +#define HWIO_GCC_UFS_MEM_PHY_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_SHFT 0x1 +#define HWIO_GCC_UFS_MEM_PHY_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_UFS_MEM_PHY_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_SHFT 0x0 + +#define HWIO_GCC_UFS_MEM_PHY_CFG2_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008e008) +#define HWIO_GCC_UFS_MEM_PHY_CFG2_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008e008) +#define HWIO_GCC_UFS_MEM_PHY_CFG2_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008e008) +#define HWIO_GCC_UFS_MEM_PHY_CFG2_GDSCR_RMSK 0x7ffff +#define HWIO_GCC_UFS_MEM_PHY_CFG2_GDSCR_ATTR 0x3 +#define HWIO_GCC_UFS_MEM_PHY_CFG2_GDSCR_IN \ + in_dword_masked(HWIO_GCC_UFS_MEM_PHY_CFG2_GDSCR_ADDR, HWIO_GCC_UFS_MEM_PHY_CFG2_GDSCR_RMSK) +#define HWIO_GCC_UFS_MEM_PHY_CFG2_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_UFS_MEM_PHY_CFG2_GDSCR_ADDR, m) +#define HWIO_GCC_UFS_MEM_PHY_CFG2_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_UFS_MEM_PHY_CFG2_GDSCR_ADDR,v) +#define HWIO_GCC_UFS_MEM_PHY_CFG2_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_UFS_MEM_PHY_CFG2_GDSCR_ADDR,m,v,HWIO_GCC_UFS_MEM_PHY_CFG2_GDSCR_IN) +#define HWIO_GCC_UFS_MEM_PHY_CFG2_GDSCR_GDSC_MEM_PWRUP_ACK_OVERRIDE_BMSK 0x40000 +#define HWIO_GCC_UFS_MEM_PHY_CFG2_GDSCR_GDSC_MEM_PWRUP_ACK_OVERRIDE_SHFT 0x12 +#define HWIO_GCC_UFS_MEM_PHY_CFG2_GDSCR_GDSC_PWRDWN_ENABLE_ACK_OVERRIDE_BMSK 0x20000 +#define HWIO_GCC_UFS_MEM_PHY_CFG2_GDSCR_GDSC_PWRDWN_ENABLE_ACK_OVERRIDE_SHFT 0x11 +#define HWIO_GCC_UFS_MEM_PHY_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_BMSK 0x10000 +#define HWIO_GCC_UFS_MEM_PHY_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_SHFT 0x10 +#define HWIO_GCC_UFS_MEM_PHY_CFG2_GDSCR_DLY_MEM_PWR_UP_BMSK 0xf000 +#define HWIO_GCC_UFS_MEM_PHY_CFG2_GDSCR_DLY_MEM_PWR_UP_SHFT 0xc +#define HWIO_GCC_UFS_MEM_PHY_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_BMSK 0xf00 +#define HWIO_GCC_UFS_MEM_PHY_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_SHFT 0x8 +#define HWIO_GCC_UFS_MEM_PHY_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_BMSK 0xf0 +#define HWIO_GCC_UFS_MEM_PHY_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_SHFT 0x4 +#define HWIO_GCC_UFS_MEM_PHY_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_BMSK 0xf +#define HWIO_GCC_UFS_MEM_PHY_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_SHFT 0x0 + +#define HWIO_GCC_UFS_MEM_PHY_CFG3_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008e00c) +#define HWIO_GCC_UFS_MEM_PHY_CFG3_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008e00c) +#define HWIO_GCC_UFS_MEM_PHY_CFG3_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008e00c) +#define HWIO_GCC_UFS_MEM_PHY_CFG3_GDSCR_RMSK 0x7ffffff +#define HWIO_GCC_UFS_MEM_PHY_CFG3_GDSCR_ATTR 0x3 +#define HWIO_GCC_UFS_MEM_PHY_CFG3_GDSCR_IN \ + in_dword_masked(HWIO_GCC_UFS_MEM_PHY_CFG3_GDSCR_ADDR, HWIO_GCC_UFS_MEM_PHY_CFG3_GDSCR_RMSK) +#define HWIO_GCC_UFS_MEM_PHY_CFG3_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_UFS_MEM_PHY_CFG3_GDSCR_ADDR, m) +#define HWIO_GCC_UFS_MEM_PHY_CFG3_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_UFS_MEM_PHY_CFG3_GDSCR_ADDR,v) +#define HWIO_GCC_UFS_MEM_PHY_CFG3_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_UFS_MEM_PHY_CFG3_GDSCR_ADDR,m,v,HWIO_GCC_UFS_MEM_PHY_CFG3_GDSCR_IN) +#define HWIO_GCC_UFS_MEM_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_STATUS_BMSK 0x4000000 +#define HWIO_GCC_UFS_MEM_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_STATUS_SHFT 0x1a +#define HWIO_GCC_UFS_MEM_PHY_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_BMSK 0x2000000 +#define HWIO_GCC_UFS_MEM_PHY_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_SHFT 0x19 +#define HWIO_GCC_UFS_MEM_PHY_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_MEM_PHY_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_UFS_MEM_PHY_CFG3_GDSCR_DLY_ACCU_RED_SHIFTER_DONE_BMSK 0x1e00000 +#define HWIO_GCC_UFS_MEM_PHY_CFG3_GDSCR_DLY_ACCU_RED_SHIFTER_DONE_SHFT 0x15 +#define HWIO_GCC_UFS_MEM_PHY_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_BMSK 0x100000 +#define HWIO_GCC_UFS_MEM_PHY_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_SHFT 0x14 +#define HWIO_GCC_UFS_MEM_PHY_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_MEM_PHY_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_ENABLE_FVAL 0x1 +#define HWIO_GCC_UFS_MEM_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_BMSK 0x80000 +#define HWIO_GCC_UFS_MEM_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_SHFT 0x13 +#define HWIO_GCC_UFS_MEM_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_MEM_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_ENABLE_FVAL 0x1 +#define HWIO_GCC_UFS_MEM_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_BMSK 0x40000 +#define HWIO_GCC_UFS_MEM_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_SHFT 0x12 +#define HWIO_GCC_UFS_MEM_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_MEM_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_ENABLE_FVAL 0x1 +#define HWIO_GCC_UFS_MEM_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_BMSK 0x20000 +#define HWIO_GCC_UFS_MEM_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_SHFT 0x11 +#define HWIO_GCC_UFS_MEM_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_MEM_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_ENABLE_FVAL 0x1 +#define HWIO_GCC_UFS_MEM_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_BMSK 0x10000 +#define HWIO_GCC_UFS_MEM_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_SHFT 0x10 +#define HWIO_GCC_UFS_MEM_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_MEM_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_ENABLE_FVAL 0x1 +#define HWIO_GCC_UFS_MEM_PHY_CFG3_GDSCR_GDSC_SPARE_CTRL_IN_BMSK 0xff00 +#define HWIO_GCC_UFS_MEM_PHY_CFG3_GDSCR_GDSC_SPARE_CTRL_IN_SHFT 0x8 +#define HWIO_GCC_UFS_MEM_PHY_CFG3_GDSCR_GDSC_SPARE_CTRL_OUT_BMSK 0xff +#define HWIO_GCC_UFS_MEM_PHY_CFG3_GDSCR_GDSC_SPARE_CTRL_OUT_SHFT 0x0 + +#define HWIO_GCC_UFS_MEM_PHY_CFG4_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008e010) +#define HWIO_GCC_UFS_MEM_PHY_CFG4_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008e010) +#define HWIO_GCC_UFS_MEM_PHY_CFG4_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008e010) +#define HWIO_GCC_UFS_MEM_PHY_CFG4_GDSCR_RMSK 0xffffff +#define HWIO_GCC_UFS_MEM_PHY_CFG4_GDSCR_ATTR 0x3 +#define HWIO_GCC_UFS_MEM_PHY_CFG4_GDSCR_IN \ + in_dword_masked(HWIO_GCC_UFS_MEM_PHY_CFG4_GDSCR_ADDR, HWIO_GCC_UFS_MEM_PHY_CFG4_GDSCR_RMSK) +#define HWIO_GCC_UFS_MEM_PHY_CFG4_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_UFS_MEM_PHY_CFG4_GDSCR_ADDR, m) +#define HWIO_GCC_UFS_MEM_PHY_CFG4_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_UFS_MEM_PHY_CFG4_GDSCR_ADDR,v) +#define HWIO_GCC_UFS_MEM_PHY_CFG4_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_UFS_MEM_PHY_CFG4_GDSCR_ADDR,m,v,HWIO_GCC_UFS_MEM_PHY_CFG4_GDSCR_IN) +#define HWIO_GCC_UFS_MEM_PHY_CFG4_GDSCR_DLY_UNCLAMPIO_BMSK 0xf00000 +#define HWIO_GCC_UFS_MEM_PHY_CFG4_GDSCR_DLY_UNCLAMPIO_SHFT 0x14 +#define HWIO_GCC_UFS_MEM_PHY_CFG4_GDSCR_DLY_RESTOREFF_BMSK 0xf0000 +#define HWIO_GCC_UFS_MEM_PHY_CFG4_GDSCR_DLY_RESTOREFF_SHFT 0x10 +#define HWIO_GCC_UFS_MEM_PHY_CFG4_GDSCR_DLY_NORETAINFF_BMSK 0xf000 +#define HWIO_GCC_UFS_MEM_PHY_CFG4_GDSCR_DLY_NORETAINFF_SHFT 0xc +#define HWIO_GCC_UFS_MEM_PHY_CFG4_GDSCR_DLY_DEASSERTARES_BMSK 0xf00 +#define HWIO_GCC_UFS_MEM_PHY_CFG4_GDSCR_DLY_DEASSERTARES_SHFT 0x8 +#define HWIO_GCC_UFS_MEM_PHY_CFG4_GDSCR_DLY_CLAMPIO_BMSK 0xf0 +#define HWIO_GCC_UFS_MEM_PHY_CFG4_GDSCR_DLY_CLAMPIO_SHFT 0x4 +#define HWIO_GCC_UFS_MEM_PHY_CFG4_GDSCR_DLY_RETAINFF_BMSK 0xf +#define HWIO_GCC_UFS_MEM_PHY_CFG4_GDSCR_DLY_RETAINFF_SHFT 0x0 + +#define HWIO_GCC_UFS_PHY_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00067000) +#define HWIO_GCC_UFS_PHY_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00067000) +#define HWIO_GCC_UFS_PHY_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00067000) +#define HWIO_GCC_UFS_PHY_BCR_RMSK 0x1 +#define HWIO_GCC_UFS_PHY_BCR_ATTR 0x3 +#define HWIO_GCC_UFS_PHY_BCR_IN \ + in_dword_masked(HWIO_GCC_UFS_PHY_BCR_ADDR, HWIO_GCC_UFS_PHY_BCR_RMSK) +#define HWIO_GCC_UFS_PHY_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_UFS_PHY_BCR_ADDR, m) +#define HWIO_GCC_UFS_PHY_BCR_OUT(v) \ + out_dword(HWIO_GCC_UFS_PHY_BCR_ADDR,v) +#define HWIO_GCC_UFS_PHY_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_UFS_PHY_BCR_ADDR,m,v,HWIO_GCC_UFS_PHY_BCR_IN) +#define HWIO_GCC_UFS_PHY_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_UFS_PHY_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_UFS_PHY_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_UFS_PHY_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00067004) +#define HWIO_GCC_UFS_PHY_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00067004) +#define HWIO_GCC_UFS_PHY_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00067004) +#define HWIO_GCC_UFS_PHY_GDSCR_RMSK 0xf8ffffff +#define HWIO_GCC_UFS_PHY_GDSCR_ATTR 0x3 +#define HWIO_GCC_UFS_PHY_GDSCR_IN \ + in_dword_masked(HWIO_GCC_UFS_PHY_GDSCR_ADDR, HWIO_GCC_UFS_PHY_GDSCR_RMSK) +#define HWIO_GCC_UFS_PHY_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_UFS_PHY_GDSCR_ADDR, m) +#define HWIO_GCC_UFS_PHY_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_UFS_PHY_GDSCR_ADDR,v) +#define HWIO_GCC_UFS_PHY_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_UFS_PHY_GDSCR_ADDR,m,v,HWIO_GCC_UFS_PHY_GDSCR_IN) +#define HWIO_GCC_UFS_PHY_GDSCR_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_UFS_PHY_GDSCR_PWR_ON_SHFT 0x1f +#define HWIO_GCC_UFS_PHY_GDSCR_GDSC_STATE_BMSK 0x78000000 +#define HWIO_GCC_UFS_PHY_GDSCR_GDSC_STATE_SHFT 0x1b +#define HWIO_GCC_UFS_PHY_GDSCR_EN_REST_WAIT_BMSK 0xf00000 +#define HWIO_GCC_UFS_PHY_GDSCR_EN_REST_WAIT_SHFT 0x14 +#define HWIO_GCC_UFS_PHY_GDSCR_EN_FEW_WAIT_BMSK 0xf0000 +#define HWIO_GCC_UFS_PHY_GDSCR_EN_FEW_WAIT_SHFT 0x10 +#define HWIO_GCC_UFS_PHY_GDSCR_CLK_DIS_WAIT_BMSK 0xf000 +#define HWIO_GCC_UFS_PHY_GDSCR_CLK_DIS_WAIT_SHFT 0xc +#define HWIO_GCC_UFS_PHY_GDSCR_RETAIN_FF_ENABLE_BMSK 0x800 +#define HWIO_GCC_UFS_PHY_GDSCR_RETAIN_FF_ENABLE_SHFT 0xb +#define HWIO_GCC_UFS_PHY_GDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_GDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_GDSCR_RESTORE_BMSK 0x400 +#define HWIO_GCC_UFS_PHY_GDSCR_RESTORE_SHFT 0xa +#define HWIO_GCC_UFS_PHY_GDSCR_RESTORE_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_GDSCR_RESTORE_ENABLE_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_GDSCR_SAVE_BMSK 0x200 +#define HWIO_GCC_UFS_PHY_GDSCR_SAVE_SHFT 0x9 +#define HWIO_GCC_UFS_PHY_GDSCR_SAVE_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_GDSCR_SAVE_ENABLE_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_GDSCR_RETAIN_BMSK 0x100 +#define HWIO_GCC_UFS_PHY_GDSCR_RETAIN_SHFT 0x8 +#define HWIO_GCC_UFS_PHY_GDSCR_RETAIN_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_GDSCR_RETAIN_ENABLE_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_GDSCR_EN_REST_BMSK 0x80 +#define HWIO_GCC_UFS_PHY_GDSCR_EN_REST_SHFT 0x7 +#define HWIO_GCC_UFS_PHY_GDSCR_EN_REST_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_GDSCR_EN_REST_ENABLE_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_GDSCR_EN_FEW_BMSK 0x40 +#define HWIO_GCC_UFS_PHY_GDSCR_EN_FEW_SHFT 0x6 +#define HWIO_GCC_UFS_PHY_GDSCR_EN_FEW_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_GDSCR_EN_FEW_ENABLE_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_GDSCR_CLAMP_IO_BMSK 0x20 +#define HWIO_GCC_UFS_PHY_GDSCR_CLAMP_IO_SHFT 0x5 +#define HWIO_GCC_UFS_PHY_GDSCR_CLAMP_IO_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_GDSCR_CLAMP_IO_ENABLE_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_GDSCR_CLK_DISABLE_BMSK 0x10 +#define HWIO_GCC_UFS_PHY_GDSCR_CLK_DISABLE_SHFT 0x4 +#define HWIO_GCC_UFS_PHY_GDSCR_CLK_DISABLE_CLK_NOT_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_GDSCR_CLK_DISABLE_CLK_IS_DISABLE_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_GDSCR_PD_ARES_BMSK 0x8 +#define HWIO_GCC_UFS_PHY_GDSCR_PD_ARES_SHFT 0x3 +#define HWIO_GCC_UFS_PHY_GDSCR_PD_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_GDSCR_PD_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_GDSCR_SW_OVERRIDE_BMSK 0x4 +#define HWIO_GCC_UFS_PHY_GDSCR_SW_OVERRIDE_SHFT 0x2 +#define HWIO_GCC_UFS_PHY_GDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_GDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_GDSCR_HW_CONTROL_BMSK 0x2 +#define HWIO_GCC_UFS_PHY_GDSCR_HW_CONTROL_SHFT 0x1 +#define HWIO_GCC_UFS_PHY_GDSCR_HW_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_GDSCR_HW_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_GDSCR_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_UFS_PHY_GDSCR_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_UFS_PHY_GDSCR_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_GDSCR_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_UFS_PHY_CFG_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00067008) +#define HWIO_GCC_UFS_PHY_CFG_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00067008) +#define HWIO_GCC_UFS_PHY_CFG_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00067008) +#define HWIO_GCC_UFS_PHY_CFG_GDSCR_RMSK 0x7ffffff +#define HWIO_GCC_UFS_PHY_CFG_GDSCR_ATTR 0x3 +#define HWIO_GCC_UFS_PHY_CFG_GDSCR_IN \ + in_dword_masked(HWIO_GCC_UFS_PHY_CFG_GDSCR_ADDR, HWIO_GCC_UFS_PHY_CFG_GDSCR_RMSK) +#define HWIO_GCC_UFS_PHY_CFG_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_UFS_PHY_CFG_GDSCR_ADDR, m) +#define HWIO_GCC_UFS_PHY_CFG_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_UFS_PHY_CFG_GDSCR_ADDR,v) +#define HWIO_GCC_UFS_PHY_CFG_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_UFS_PHY_CFG_GDSCR_ADDR,m,v,HWIO_GCC_UFS_PHY_CFG_GDSCR_IN) +#define HWIO_GCC_UFS_PHY_CFG_GDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4000000 +#define HWIO_GCC_UFS_PHY_CFG_GDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x1a +#define HWIO_GCC_UFS_PHY_CFG_GDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_CFG_GDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_CFG_GDSCR_GDSC_PWR_DWN_START_BMSK 0x2000000 +#define HWIO_GCC_UFS_PHY_CFG_GDSCR_GDSC_PWR_DWN_START_SHFT 0x19 +#define HWIO_GCC_UFS_PHY_CFG_GDSCR_GDSC_PWR_UP_START_BMSK 0x1000000 +#define HWIO_GCC_UFS_PHY_CFG_GDSCR_GDSC_PWR_UP_START_SHFT 0x18 +#define HWIO_GCC_UFS_PHY_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_BMSK 0xf00000 +#define HWIO_GCC_UFS_PHY_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_SHFT 0x14 +#define HWIO_GCC_UFS_PHY_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_BMSK 0x80000 +#define HWIO_GCC_UFS_PHY_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_SHFT 0x13 +#define HWIO_GCC_UFS_PHY_CFG_GDSCR_GDSC_ENR_ACK_STATUS_BMSK 0x40000 +#define HWIO_GCC_UFS_PHY_CFG_GDSCR_GDSC_ENR_ACK_STATUS_SHFT 0x12 +#define HWIO_GCC_UFS_PHY_CFG_GDSCR_GDSC_ENF_ACK_STATUS_BMSK 0x20000 +#define HWIO_GCC_UFS_PHY_CFG_GDSCR_GDSC_ENF_ACK_STATUS_SHFT 0x11 +#define HWIO_GCC_UFS_PHY_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_BMSK 0x10000 +#define HWIO_GCC_UFS_PHY_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_SHFT 0x10 +#define HWIO_GCC_UFS_PHY_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_BMSK 0x8000 +#define HWIO_GCC_UFS_PHY_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_SHFT 0xf +#define HWIO_GCC_UFS_PHY_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_BMSK 0x7800 +#define HWIO_GCC_UFS_PHY_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_SHFT 0xb +#define HWIO_GCC_UFS_PHY_CFG_GDSCR_GDSC_HANDSHAKE_DIS_BMSK 0x400 +#define HWIO_GCC_UFS_PHY_CFG_GDSCR_GDSC_HANDSHAKE_DIS_SHFT 0xa +#define HWIO_GCC_UFS_PHY_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_BMSK 0x200 +#define HWIO_GCC_UFS_PHY_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_SHFT 0x9 +#define HWIO_GCC_UFS_PHY_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_BMSK 0x100 +#define HWIO_GCC_UFS_PHY_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_SHFT 0x8 +#define HWIO_GCC_UFS_PHY_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_BMSK 0x80 +#define HWIO_GCC_UFS_PHY_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_SHFT 0x7 +#define HWIO_GCC_UFS_PHY_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_BMSK 0x60 +#define HWIO_GCC_UFS_PHY_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_SHFT 0x5 +#define HWIO_GCC_UFS_PHY_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_BMSK 0x10 +#define HWIO_GCC_UFS_PHY_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_SHFT 0x4 +#define HWIO_GCC_UFS_PHY_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_BMSK 0x8 +#define HWIO_GCC_UFS_PHY_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_SHFT 0x3 +#define HWIO_GCC_UFS_PHY_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_BMSK 0x4 +#define HWIO_GCC_UFS_PHY_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_SHFT 0x2 +#define HWIO_GCC_UFS_PHY_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_BMSK 0x2 +#define HWIO_GCC_UFS_PHY_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_SHFT 0x1 +#define HWIO_GCC_UFS_PHY_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_UFS_PHY_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_SHFT 0x0 + +#define HWIO_GCC_UFS_PHY_CFG2_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006700c) +#define HWIO_GCC_UFS_PHY_CFG2_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006700c) +#define HWIO_GCC_UFS_PHY_CFG2_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006700c) +#define HWIO_GCC_UFS_PHY_CFG2_GDSCR_RMSK 0x7ffff +#define HWIO_GCC_UFS_PHY_CFG2_GDSCR_ATTR 0x3 +#define HWIO_GCC_UFS_PHY_CFG2_GDSCR_IN \ + in_dword_masked(HWIO_GCC_UFS_PHY_CFG2_GDSCR_ADDR, HWIO_GCC_UFS_PHY_CFG2_GDSCR_RMSK) +#define HWIO_GCC_UFS_PHY_CFG2_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_UFS_PHY_CFG2_GDSCR_ADDR, m) +#define HWIO_GCC_UFS_PHY_CFG2_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_UFS_PHY_CFG2_GDSCR_ADDR,v) +#define HWIO_GCC_UFS_PHY_CFG2_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_UFS_PHY_CFG2_GDSCR_ADDR,m,v,HWIO_GCC_UFS_PHY_CFG2_GDSCR_IN) +#define HWIO_GCC_UFS_PHY_CFG2_GDSCR_GDSC_MEM_PWRUP_ACK_OVERRIDE_BMSK 0x40000 +#define HWIO_GCC_UFS_PHY_CFG2_GDSCR_GDSC_MEM_PWRUP_ACK_OVERRIDE_SHFT 0x12 +#define HWIO_GCC_UFS_PHY_CFG2_GDSCR_GDSC_PWRDWN_ENABLE_ACK_OVERRIDE_BMSK 0x20000 +#define HWIO_GCC_UFS_PHY_CFG2_GDSCR_GDSC_PWRDWN_ENABLE_ACK_OVERRIDE_SHFT 0x11 +#define HWIO_GCC_UFS_PHY_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_BMSK 0x10000 +#define HWIO_GCC_UFS_PHY_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_SHFT 0x10 +#define HWIO_GCC_UFS_PHY_CFG2_GDSCR_DLY_MEM_PWR_UP_BMSK 0xf000 +#define HWIO_GCC_UFS_PHY_CFG2_GDSCR_DLY_MEM_PWR_UP_SHFT 0xc +#define HWIO_GCC_UFS_PHY_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_BMSK 0xf00 +#define HWIO_GCC_UFS_PHY_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_SHFT 0x8 +#define HWIO_GCC_UFS_PHY_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_BMSK 0xf0 +#define HWIO_GCC_UFS_PHY_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_SHFT 0x4 +#define HWIO_GCC_UFS_PHY_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_BMSK 0xf +#define HWIO_GCC_UFS_PHY_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_SHFT 0x0 + +#define HWIO_GCC_UFS_PHY_CFG3_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00067010) +#define HWIO_GCC_UFS_PHY_CFG3_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00067010) +#define HWIO_GCC_UFS_PHY_CFG3_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00067010) +#define HWIO_GCC_UFS_PHY_CFG3_GDSCR_RMSK 0x7ffffff +#define HWIO_GCC_UFS_PHY_CFG3_GDSCR_ATTR 0x3 +#define HWIO_GCC_UFS_PHY_CFG3_GDSCR_IN \ + in_dword_masked(HWIO_GCC_UFS_PHY_CFG3_GDSCR_ADDR, HWIO_GCC_UFS_PHY_CFG3_GDSCR_RMSK) +#define HWIO_GCC_UFS_PHY_CFG3_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_UFS_PHY_CFG3_GDSCR_ADDR, m) +#define HWIO_GCC_UFS_PHY_CFG3_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_UFS_PHY_CFG3_GDSCR_ADDR,v) +#define HWIO_GCC_UFS_PHY_CFG3_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_UFS_PHY_CFG3_GDSCR_ADDR,m,v,HWIO_GCC_UFS_PHY_CFG3_GDSCR_IN) +#define HWIO_GCC_UFS_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_STATUS_BMSK 0x4000000 +#define HWIO_GCC_UFS_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_STATUS_SHFT 0x1a +#define HWIO_GCC_UFS_PHY_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_BMSK 0x2000000 +#define HWIO_GCC_UFS_PHY_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_SHFT 0x19 +#define HWIO_GCC_UFS_PHY_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_CFG3_GDSCR_DLY_ACCU_RED_SHIFTER_DONE_BMSK 0x1e00000 +#define HWIO_GCC_UFS_PHY_CFG3_GDSCR_DLY_ACCU_RED_SHIFTER_DONE_SHFT 0x15 +#define HWIO_GCC_UFS_PHY_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_BMSK 0x100000 +#define HWIO_GCC_UFS_PHY_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_SHFT 0x14 +#define HWIO_GCC_UFS_PHY_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_ENABLE_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_BMSK 0x80000 +#define HWIO_GCC_UFS_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_SHFT 0x13 +#define HWIO_GCC_UFS_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_ENABLE_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_BMSK 0x40000 +#define HWIO_GCC_UFS_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_SHFT 0x12 +#define HWIO_GCC_UFS_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_ENABLE_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_BMSK 0x20000 +#define HWIO_GCC_UFS_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_SHFT 0x11 +#define HWIO_GCC_UFS_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_ENABLE_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_BMSK 0x10000 +#define HWIO_GCC_UFS_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_SHFT 0x10 +#define HWIO_GCC_UFS_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_ENABLE_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_CFG3_GDSCR_GDSC_SPARE_CTRL_IN_BMSK 0xff00 +#define HWIO_GCC_UFS_PHY_CFG3_GDSCR_GDSC_SPARE_CTRL_IN_SHFT 0x8 +#define HWIO_GCC_UFS_PHY_CFG3_GDSCR_GDSC_SPARE_CTRL_OUT_BMSK 0xff +#define HWIO_GCC_UFS_PHY_CFG3_GDSCR_GDSC_SPARE_CTRL_OUT_SHFT 0x0 + +#define HWIO_GCC_UFS_PHY_CFG4_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00067014) +#define HWIO_GCC_UFS_PHY_CFG4_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00067014) +#define HWIO_GCC_UFS_PHY_CFG4_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00067014) +#define HWIO_GCC_UFS_PHY_CFG4_GDSCR_RMSK 0xffffff +#define HWIO_GCC_UFS_PHY_CFG4_GDSCR_ATTR 0x3 +#define HWIO_GCC_UFS_PHY_CFG4_GDSCR_IN \ + in_dword_masked(HWIO_GCC_UFS_PHY_CFG4_GDSCR_ADDR, HWIO_GCC_UFS_PHY_CFG4_GDSCR_RMSK) +#define HWIO_GCC_UFS_PHY_CFG4_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_UFS_PHY_CFG4_GDSCR_ADDR, m) +#define HWIO_GCC_UFS_PHY_CFG4_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_UFS_PHY_CFG4_GDSCR_ADDR,v) +#define HWIO_GCC_UFS_PHY_CFG4_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_UFS_PHY_CFG4_GDSCR_ADDR,m,v,HWIO_GCC_UFS_PHY_CFG4_GDSCR_IN) +#define HWIO_GCC_UFS_PHY_CFG4_GDSCR_DLY_UNCLAMPIO_BMSK 0xf00000 +#define HWIO_GCC_UFS_PHY_CFG4_GDSCR_DLY_UNCLAMPIO_SHFT 0x14 +#define HWIO_GCC_UFS_PHY_CFG4_GDSCR_DLY_RESTOREFF_BMSK 0xf0000 +#define HWIO_GCC_UFS_PHY_CFG4_GDSCR_DLY_RESTOREFF_SHFT 0x10 +#define HWIO_GCC_UFS_PHY_CFG4_GDSCR_DLY_NORETAINFF_BMSK 0xf000 +#define HWIO_GCC_UFS_PHY_CFG4_GDSCR_DLY_NORETAINFF_SHFT 0xc +#define HWIO_GCC_UFS_PHY_CFG4_GDSCR_DLY_DEASSERTARES_BMSK 0xf00 +#define HWIO_GCC_UFS_PHY_CFG4_GDSCR_DLY_DEASSERTARES_SHFT 0x8 +#define HWIO_GCC_UFS_PHY_CFG4_GDSCR_DLY_CLAMPIO_BMSK 0xf0 +#define HWIO_GCC_UFS_PHY_CFG4_GDSCR_DLY_CLAMPIO_SHFT 0x4 +#define HWIO_GCC_UFS_PHY_CFG4_GDSCR_DLY_RETAINFF_BMSK 0xf +#define HWIO_GCC_UFS_PHY_CFG4_GDSCR_DLY_RETAINFF_SHFT 0x0 + +#define HWIO_GCC_UFS_PHY_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00067018) +#define HWIO_GCC_UFS_PHY_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00067018) +#define HWIO_GCC_UFS_PHY_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00067018) +#define HWIO_GCC_UFS_PHY_AXI_CBCR_RMSK 0x81c0700f +#define HWIO_GCC_UFS_PHY_AXI_CBCR_ATTR 0x3 +#define HWIO_GCC_UFS_PHY_AXI_CBCR_IN \ + in_dword_masked(HWIO_GCC_UFS_PHY_AXI_CBCR_ADDR, HWIO_GCC_UFS_PHY_AXI_CBCR_RMSK) +#define HWIO_GCC_UFS_PHY_AXI_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_UFS_PHY_AXI_CBCR_ADDR, m) +#define HWIO_GCC_UFS_PHY_AXI_CBCR_OUT(v) \ + out_dword(HWIO_GCC_UFS_PHY_AXI_CBCR_ADDR,v) +#define HWIO_GCC_UFS_PHY_AXI_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_UFS_PHY_AXI_CBCR_ADDR,m,v,HWIO_GCC_UFS_PHY_AXI_CBCR_IN) +#define HWIO_GCC_UFS_PHY_AXI_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_UFS_PHY_AXI_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_UFS_PHY_AXI_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_UFS_PHY_AXI_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_UFS_PHY_AXI_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_UFS_PHY_AXI_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_UFS_PHY_AXI_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_UFS_PHY_AXI_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_UFS_PHY_AXI_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_UFS_PHY_AXI_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_UFS_PHY_AXI_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_AXI_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_AXI_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_UFS_PHY_AXI_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_UFS_PHY_AXI_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_AXI_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_AXI_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_UFS_PHY_AXI_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_UFS_PHY_AXI_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_AXI_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_AXI_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_UFS_PHY_AXI_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_UFS_PHY_AXI_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_UFS_PHY_AXI_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_UFS_PHY_AXI_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_AXI_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_AXI_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_UFS_PHY_AXI_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_UFS_PHY_AXI_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_AXI_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_AXI_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_UFS_PHY_AXI_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_UFS_PHY_AXI_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_AXI_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_UFS_PHY_AXI_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006701c) +#define HWIO_GCC_UFS_PHY_AXI_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006701c) +#define HWIO_GCC_UFS_PHY_AXI_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006701c) +#define HWIO_GCC_UFS_PHY_AXI_SREGR_RMSK 0xf1ffffe +#define HWIO_GCC_UFS_PHY_AXI_SREGR_ATTR 0x3 +#define HWIO_GCC_UFS_PHY_AXI_SREGR_IN \ + in_dword_masked(HWIO_GCC_UFS_PHY_AXI_SREGR_ADDR, HWIO_GCC_UFS_PHY_AXI_SREGR_RMSK) +#define HWIO_GCC_UFS_PHY_AXI_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_UFS_PHY_AXI_SREGR_ADDR, m) +#define HWIO_GCC_UFS_PHY_AXI_SREGR_OUT(v) \ + out_dword(HWIO_GCC_UFS_PHY_AXI_SREGR_ADDR,v) +#define HWIO_GCC_UFS_PHY_AXI_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_UFS_PHY_AXI_SREGR_ADDR,m,v,HWIO_GCC_UFS_PHY_AXI_SREGR_IN) +#define HWIO_GCC_UFS_PHY_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xf000000 +#define HWIO_GCC_UFS_PHY_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_UFS_PHY_AXI_SREGR_PWR_FSM_CLK_SEL_BMSK 0x100000 +#define HWIO_GCC_UFS_PHY_AXI_SREGR_PWR_FSM_CLK_SEL_SHFT 0x14 +#define HWIO_GCC_UFS_PHY_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xf0000 +#define HWIO_GCC_UFS_PHY_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_UFS_PHY_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_UFS_PHY_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_UFS_PHY_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_AXI_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_UFS_PHY_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_UFS_PHY_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_AXI_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_UFS_PHY_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_UFS_PHY_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_AXI_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_UFS_PHY_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_UFS_PHY_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_AXI_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_UFS_PHY_AXI_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_UFS_PHY_AXI_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_UFS_PHY_AXI_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_UFS_PHY_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_UFS_PHY_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_UFS_PHY_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_UFS_PHY_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_UFS_PHY_AXI_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_UFS_PHY_AXI_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_UFS_PHY_AXI_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_AXI_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_AXI_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_UFS_PHY_AXI_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_UFS_PHY_AXI_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_AXI_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_AXI_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_UFS_PHY_AXI_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_UFS_PHY_AXI_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_AXI_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_AXI_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_UFS_PHY_AXI_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_UFS_PHY_AXI_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_AXI_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_AXI_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_UFS_PHY_AXI_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_UFS_PHY_AXI_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_AXI_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_UFS_PHY_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_UFS_PHY_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_AXI_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_UFS_PHY_AXI_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_UFS_PHY_AXI_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_AXI_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_UFS_PHY_AXI_CFG_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00067020) +#define HWIO_GCC_UFS_PHY_AXI_CFG_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00067020) +#define HWIO_GCC_UFS_PHY_AXI_CFG_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00067020) +#define HWIO_GCC_UFS_PHY_AXI_CFG_SREGR_RMSK 0xffffffff +#define HWIO_GCC_UFS_PHY_AXI_CFG_SREGR_ATTR 0x3 +#define HWIO_GCC_UFS_PHY_AXI_CFG_SREGR_IN \ + in_dword_masked(HWIO_GCC_UFS_PHY_AXI_CFG_SREGR_ADDR, HWIO_GCC_UFS_PHY_AXI_CFG_SREGR_RMSK) +#define HWIO_GCC_UFS_PHY_AXI_CFG_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_UFS_PHY_AXI_CFG_SREGR_ADDR, m) +#define HWIO_GCC_UFS_PHY_AXI_CFG_SREGR_OUT(v) \ + out_dword(HWIO_GCC_UFS_PHY_AXI_CFG_SREGR_ADDR,v) +#define HWIO_GCC_UFS_PHY_AXI_CFG_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_UFS_PHY_AXI_CFG_SREGR_ADDR,m,v,HWIO_GCC_UFS_PHY_AXI_CFG_SREGR_IN) +#define HWIO_GCC_UFS_PHY_AXI_CFG_SREGR_MEM_CORE_OFF_TIMER_BMSK 0xfc000000 +#define HWIO_GCC_UFS_PHY_AXI_CFG_SREGR_MEM_CORE_OFF_TIMER_SHFT 0x1a +#define HWIO_GCC_UFS_PHY_AXI_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_BMSK 0x2000000 +#define HWIO_GCC_UFS_PHY_AXI_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_SHFT 0x19 +#define HWIO_GCC_UFS_PHY_AXI_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_BMSK 0x1000000 +#define HWIO_GCC_UFS_PHY_AXI_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_SHFT 0x18 +#define HWIO_GCC_UFS_PHY_AXI_CFG_SREGR_MEM_PERIPH_ON_STATUS_BMSK 0x800000 +#define HWIO_GCC_UFS_PHY_AXI_CFG_SREGR_MEM_PERIPH_ON_STATUS_SHFT 0x17 +#define HWIO_GCC_UFS_PHY_AXI_CFG_SREGR_MEM_CORE_ON_STATUS_BMSK 0x400000 +#define HWIO_GCC_UFS_PHY_AXI_CFG_SREGR_MEM_CORE_ON_STATUS_SHFT 0x16 +#define HWIO_GCC_UFS_PHY_AXI_CFG_SREGR_MEM_CPH_TIMER_BMSK 0x3f0000 +#define HWIO_GCC_UFS_PHY_AXI_CFG_SREGR_MEM_CPH_TIMER_SHFT 0x10 +#define HWIO_GCC_UFS_PHY_AXI_CFG_SREGR_SLEEP_TIMER_BMSK 0xff00 +#define HWIO_GCC_UFS_PHY_AXI_CFG_SREGR_SLEEP_TIMER_SHFT 0x8 +#define HWIO_GCC_UFS_PHY_AXI_CFG_SREGR_WAKEUP_TIMER_BMSK 0xff +#define HWIO_GCC_UFS_PHY_AXI_CFG_SREGR_WAKEUP_TIMER_SHFT 0x0 + +#define HWIO_GCC_UFS_PHY_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00067024) +#define HWIO_GCC_UFS_PHY_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00067024) +#define HWIO_GCC_UFS_PHY_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00067024) +#define HWIO_GCC_UFS_PHY_AHB_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_UFS_PHY_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_UFS_PHY_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_UFS_PHY_AHB_CBCR_ADDR, HWIO_GCC_UFS_PHY_AHB_CBCR_RMSK) +#define HWIO_GCC_UFS_PHY_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_UFS_PHY_AHB_CBCR_ADDR, m) +#define HWIO_GCC_UFS_PHY_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_UFS_PHY_AHB_CBCR_ADDR,v) +#define HWIO_GCC_UFS_PHY_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_UFS_PHY_AHB_CBCR_ADDR,m,v,HWIO_GCC_UFS_PHY_AHB_CBCR_IN) +#define HWIO_GCC_UFS_PHY_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_UFS_PHY_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_UFS_PHY_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_UFS_PHY_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_UFS_PHY_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_UFS_PHY_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_UFS_PHY_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_UFS_PHY_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_UFS_PHY_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_UFS_PHY_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_UFS_PHY_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_UFS_PHY_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_UFS_PHY_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_UFS_PHY_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_UFS_PHY_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_UFS_PHY_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_UFS_PHY_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_UFS_PHY_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_UFS_PHY_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00067028) +#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00067028) +#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00067028) +#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_CBCR_ATTR 0x3 +#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_CBCR_IN \ + in_dword_masked(HWIO_GCC_UFS_PHY_TX_SYMBOL_0_CBCR_ADDR, HWIO_GCC_UFS_PHY_TX_SYMBOL_0_CBCR_RMSK) +#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_UFS_PHY_TX_SYMBOL_0_CBCR_ADDR, m) +#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_CBCR_OUT(v) \ + out_dword(HWIO_GCC_UFS_PHY_TX_SYMBOL_0_CBCR_ADDR,v) +#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_UFS_PHY_TX_SYMBOL_0_CBCR_ADDR,m,v,HWIO_GCC_UFS_PHY_TX_SYMBOL_0_CBCR_IN) +#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006702c) +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006702c) +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006702c) +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_CBCR_ATTR 0x3 +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_CBCR_IN \ + in_dword_masked(HWIO_GCC_UFS_PHY_RX_SYMBOL_0_CBCR_ADDR, HWIO_GCC_UFS_PHY_RX_SYMBOL_0_CBCR_RMSK) +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_UFS_PHY_RX_SYMBOL_0_CBCR_ADDR, m) +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_CBCR_OUT(v) \ + out_dword(HWIO_GCC_UFS_PHY_RX_SYMBOL_0_CBCR_ADDR,v) +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_UFS_PHY_RX_SYMBOL_0_CBCR_ADDR,m,v,HWIO_GCC_UFS_PHY_RX_SYMBOL_0_CBCR_IN) +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00067030) +#define HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00067030) +#define HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00067030) +#define HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_RMSK 0x800000f3 +#define HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_ADDR, HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_RMSK) +#define HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_ADDR, m) +#define HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_ADDR,v) +#define HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_ADDR,m,v,HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_IN) +#define HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_DIRTY_D_BMSK 0x80 +#define HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_DIRTY_D_SHFT 0x7 +#define HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_DIRTY_N_BMSK 0x40 +#define HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_DIRTY_N_SHFT 0x6 +#define HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_DIRTY_M_BMSK 0x20 +#define HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_DIRTY_M_SHFT 0x5 +#define HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00067034) +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00067034) +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00067034) +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_RMSK 0x10371f +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_ADDR, HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_RMSK) +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_ADDR, m) +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_ADDR,v) +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_ADDR,m,v,HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_IN) +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_MODE_BMSK 0x3000 +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_MODE_SHFT 0xc +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_MODE_BYPASS_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_MODE_SWALLOW_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_MODE_DUAL_EDGE_FVAL 0x2 +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_MODE_SINGLE_EDGE_FVAL 0x3 +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_UFS_PHY_AXI_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00067038) +#define HWIO_GCC_UFS_PHY_AXI_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00067038) +#define HWIO_GCC_UFS_PHY_AXI_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00067038) +#define HWIO_GCC_UFS_PHY_AXI_M_RMSK 0xff +#define HWIO_GCC_UFS_PHY_AXI_M_ATTR 0x3 +#define HWIO_GCC_UFS_PHY_AXI_M_IN \ + in_dword_masked(HWIO_GCC_UFS_PHY_AXI_M_ADDR, HWIO_GCC_UFS_PHY_AXI_M_RMSK) +#define HWIO_GCC_UFS_PHY_AXI_M_INM(m) \ + in_dword_masked(HWIO_GCC_UFS_PHY_AXI_M_ADDR, m) +#define HWIO_GCC_UFS_PHY_AXI_M_OUT(v) \ + out_dword(HWIO_GCC_UFS_PHY_AXI_M_ADDR,v) +#define HWIO_GCC_UFS_PHY_AXI_M_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_UFS_PHY_AXI_M_ADDR,m,v,HWIO_GCC_UFS_PHY_AXI_M_IN) +#define HWIO_GCC_UFS_PHY_AXI_M_M_BMSK 0xff +#define HWIO_GCC_UFS_PHY_AXI_M_M_SHFT 0x0 + +#define HWIO_GCC_UFS_PHY_AXI_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006703c) +#define HWIO_GCC_UFS_PHY_AXI_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006703c) +#define HWIO_GCC_UFS_PHY_AXI_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006703c) +#define HWIO_GCC_UFS_PHY_AXI_N_RMSK 0xff +#define HWIO_GCC_UFS_PHY_AXI_N_ATTR 0x3 +#define HWIO_GCC_UFS_PHY_AXI_N_IN \ + in_dword_masked(HWIO_GCC_UFS_PHY_AXI_N_ADDR, HWIO_GCC_UFS_PHY_AXI_N_RMSK) +#define HWIO_GCC_UFS_PHY_AXI_N_INM(m) \ + in_dword_masked(HWIO_GCC_UFS_PHY_AXI_N_ADDR, m) +#define HWIO_GCC_UFS_PHY_AXI_N_OUT(v) \ + out_dword(HWIO_GCC_UFS_PHY_AXI_N_ADDR,v) +#define HWIO_GCC_UFS_PHY_AXI_N_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_UFS_PHY_AXI_N_ADDR,m,v,HWIO_GCC_UFS_PHY_AXI_N_IN) +#define HWIO_GCC_UFS_PHY_AXI_N_NOT_N_MINUS_M_BMSK 0xff +#define HWIO_GCC_UFS_PHY_AXI_N_NOT_N_MINUS_M_SHFT 0x0 + +#define HWIO_GCC_UFS_PHY_AXI_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00067040) +#define HWIO_GCC_UFS_PHY_AXI_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00067040) +#define HWIO_GCC_UFS_PHY_AXI_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00067040) +#define HWIO_GCC_UFS_PHY_AXI_D_RMSK 0xff +#define HWIO_GCC_UFS_PHY_AXI_D_ATTR 0x3 +#define HWIO_GCC_UFS_PHY_AXI_D_IN \ + in_dword_masked(HWIO_GCC_UFS_PHY_AXI_D_ADDR, HWIO_GCC_UFS_PHY_AXI_D_RMSK) +#define HWIO_GCC_UFS_PHY_AXI_D_INM(m) \ + in_dword_masked(HWIO_GCC_UFS_PHY_AXI_D_ADDR, m) +#define HWIO_GCC_UFS_PHY_AXI_D_OUT(v) \ + out_dword(HWIO_GCC_UFS_PHY_AXI_D_ADDR,v) +#define HWIO_GCC_UFS_PHY_AXI_D_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_UFS_PHY_AXI_D_ADDR,m,v,HWIO_GCC_UFS_PHY_AXI_D_IN) +#define HWIO_GCC_UFS_PHY_AXI_D_NOT_2D_BMSK 0xff +#define HWIO_GCC_UFS_PHY_AXI_D_NOT_2D_SHFT 0x0 + +#define HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_DIV_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006704c) +#define HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_DIV_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006704c) +#define HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_DIV_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006704c) +#define HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_DIV_CDIVR_RMSK 0xf +#define HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_DIV_CDIVR_ATTR 0x3 +#define HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_DIV_CDIVR_IN \ + in_dword_masked(HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_DIV_CDIVR_ADDR, HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_DIV_CDIVR_RMSK) +#define HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_DIV_CDIVR_INM(m) \ + in_dword_masked(HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_DIV_CDIVR_ADDR, m) +#define HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_DIV_CDIVR_OUT(v) \ + out_dword(HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_DIV_CDIVR_ADDR,v) +#define HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_DIV_CDIVR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_DIV_CDIVR_ADDR,m,v,HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_DIV_CDIVR_IN) +#define HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_DIV_CDIVR_CLK_DIV_BMSK 0xf +#define HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_DIV_CDIVR_CLK_DIV_SHFT 0x0 + +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_DIV_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006705c) +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_DIV_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006705c) +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_DIV_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006705c) +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_DIV_CDIVR_RMSK 0xf +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_DIV_CDIVR_ATTR 0x3 +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_DIV_CDIVR_IN \ + in_dword_masked(HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_DIV_CDIVR_ADDR, HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_DIV_CDIVR_RMSK) +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_DIV_CDIVR_INM(m) \ + in_dword_masked(HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_DIV_CDIVR_ADDR, m) +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_DIV_CDIVR_OUT(v) \ + out_dword(HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_DIV_CDIVR_ADDR,v) +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_DIV_CDIVR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_DIV_CDIVR_ADDR,m,v,HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_DIV_CDIVR_IN) +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_DIV_CDIVR_CLK_DIV_BMSK 0xf +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_DIV_CDIVR_CLK_DIV_SHFT 0x0 + +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00067068) +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00067068) +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00067068) +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_RMSK 0x81c0700f +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_ATTR 0x3 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_IN \ + in_dword_masked(HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_ADDR, HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_RMSK) +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_ADDR, m) +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_OUT(v) \ + out_dword(HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_ADDR,v) +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_ADDR,m,v,HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_IN) +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006706c) +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006706c) +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006706c) +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_RMSK 0xf1ffffe +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_ATTR 0x3 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_IN \ + in_dword_masked(HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_ADDR, HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_RMSK) +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_ADDR, m) +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_OUT(v) \ + out_dword(HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_ADDR,v) +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_ADDR,m,v,HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_IN) +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xf000000 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_PWR_FSM_CLK_SEL_BMSK 0x100000 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_PWR_FSM_CLK_SEL_SHFT 0x14 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xf0000 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00067070) +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00067070) +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00067070) +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_SREGR_RMSK 0xffffffff +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_SREGR_ATTR 0x3 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_SREGR_IN \ + in_dword_masked(HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_SREGR_ADDR, HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_SREGR_RMSK) +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_SREGR_ADDR, m) +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_SREGR_OUT(v) \ + out_dword(HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_SREGR_ADDR,v) +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_SREGR_ADDR,m,v,HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_SREGR_IN) +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_SREGR_MEM_CORE_OFF_TIMER_BMSK 0xfc000000 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_SREGR_MEM_CORE_OFF_TIMER_SHFT 0x1a +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_BMSK 0x2000000 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_SHFT 0x19 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_BMSK 0x1000000 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_SHFT 0x18 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_SREGR_MEM_PERIPH_ON_STATUS_BMSK 0x800000 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_SREGR_MEM_PERIPH_ON_STATUS_SHFT 0x17 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_SREGR_MEM_CORE_ON_STATUS_BMSK 0x400000 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_SREGR_MEM_CORE_ON_STATUS_SHFT 0x16 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_SREGR_MEM_CPH_TIMER_BMSK 0x3f0000 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_SREGR_MEM_CPH_TIMER_SHFT 0x10 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_SREGR_SLEEP_TIMER_BMSK 0xff00 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_SREGR_SLEEP_TIMER_SHFT 0x8 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_SREGR_WAKEUP_TIMER_BMSK 0xff +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_SREGR_WAKEUP_TIMER_SHFT 0x0 + +#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00067074) +#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00067074) +#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00067074) +#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_RMSK 0x81c0700f +#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_ATTR 0x3 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_IN \ + in_dword_masked(HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_ADDR, HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_RMSK) +#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_ADDR, m) +#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_OUT(v) \ + out_dword(HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_ADDR,v) +#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_ADDR,m,v,HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_IN) +#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00067078) +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00067078) +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00067078) +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_RMSK 0xf1ffffe +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_ATTR 0x3 +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_IN \ + in_dword_masked(HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_ADDR, HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_RMSK) +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_ADDR, m) +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_OUT(v) \ + out_dword(HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_ADDR,v) +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_ADDR,m,v,HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_IN) +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xf000000 +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_PWR_FSM_CLK_SEL_BMSK 0x100000 +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_PWR_FSM_CLK_SEL_SHFT 0x14 +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xf0000 +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006707c) +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006707c) +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006707c) +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_SREGR_RMSK 0xffffffff +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_SREGR_ATTR 0x3 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_SREGR_IN \ + in_dword_masked(HWIO_GCC_UFS_PHY_ICE_CORE_CFG_SREGR_ADDR, HWIO_GCC_UFS_PHY_ICE_CORE_CFG_SREGR_RMSK) +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_UFS_PHY_ICE_CORE_CFG_SREGR_ADDR, m) +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_SREGR_OUT(v) \ + out_dword(HWIO_GCC_UFS_PHY_ICE_CORE_CFG_SREGR_ADDR,v) +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_UFS_PHY_ICE_CORE_CFG_SREGR_ADDR,m,v,HWIO_GCC_UFS_PHY_ICE_CORE_CFG_SREGR_IN) +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_SREGR_MEM_CORE_OFF_TIMER_BMSK 0xfc000000 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_SREGR_MEM_CORE_OFF_TIMER_SHFT 0x1a +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_BMSK 0x2000000 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_SHFT 0x19 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_BMSK 0x1000000 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_SHFT 0x18 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_SREGR_MEM_PERIPH_ON_STATUS_BMSK 0x800000 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_SREGR_MEM_PERIPH_ON_STATUS_SHFT 0x17 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_SREGR_MEM_CORE_ON_STATUS_BMSK 0x400000 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_SREGR_MEM_CORE_ON_STATUS_SHFT 0x16 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_SREGR_MEM_CPH_TIMER_BMSK 0x3f0000 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_SREGR_MEM_CPH_TIMER_SHFT 0x10 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_SREGR_SLEEP_TIMER_BMSK 0xff00 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_SREGR_SLEEP_TIMER_SHFT 0x8 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_SREGR_WAKEUP_TIMER_BMSK 0xff +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_SREGR_WAKEUP_TIMER_SHFT 0x0 + +#define HWIO_GCC_UFS_PHY_ICE_CORE_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00067080) +#define HWIO_GCC_UFS_PHY_ICE_CORE_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00067080) +#define HWIO_GCC_UFS_PHY_ICE_CORE_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00067080) +#define HWIO_GCC_UFS_PHY_ICE_CORE_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_UFS_PHY_ICE_CORE_CMD_RCGR_ADDR, HWIO_GCC_UFS_PHY_ICE_CORE_CMD_RCGR_RMSK) +#define HWIO_GCC_UFS_PHY_ICE_CORE_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_UFS_PHY_ICE_CORE_CMD_RCGR_ADDR, m) +#define HWIO_GCC_UFS_PHY_ICE_CORE_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_UFS_PHY_ICE_CORE_CMD_RCGR_ADDR,v) +#define HWIO_GCC_UFS_PHY_ICE_CORE_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_UFS_PHY_ICE_CORE_CMD_RCGR_ADDR,m,v,HWIO_GCC_UFS_PHY_ICE_CORE_CMD_RCGR_IN) +#define HWIO_GCC_UFS_PHY_ICE_CORE_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_UFS_PHY_ICE_CORE_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00067084) +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00067084) +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00067084) +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_ADDR, HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_RMSK) +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_ADDR, m) +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_ADDR,v) +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_ADDR,m,v,HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_IN) +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00067098) +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00067098) +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00067098) +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR_ADDR, HWIO_GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR_RMSK) +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR_ADDR, m) +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR_ADDR,v) +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR_ADDR,m,v,HWIO_GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR_IN) +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006709c) +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006709c) +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006709c) +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_ADDR, HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_RMSK) +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_ADDR, m) +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_ADDR,v) +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_ADDR,m,v,HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_IN) +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_UFS_PHY_PHY_AUX_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000670b0) +#define HWIO_GCC_UFS_PHY_PHY_AUX_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000670b0) +#define HWIO_GCC_UFS_PHY_PHY_AUX_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000670b0) +#define HWIO_GCC_UFS_PHY_PHY_AUX_CBCR_RMSK 0x81c0000f +#define HWIO_GCC_UFS_PHY_PHY_AUX_CBCR_ATTR 0x3 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CBCR_IN \ + in_dword_masked(HWIO_GCC_UFS_PHY_PHY_AUX_CBCR_ADDR, HWIO_GCC_UFS_PHY_PHY_AUX_CBCR_RMSK) +#define HWIO_GCC_UFS_PHY_PHY_AUX_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_UFS_PHY_PHY_AUX_CBCR_ADDR, m) +#define HWIO_GCC_UFS_PHY_PHY_AUX_CBCR_OUT(v) \ + out_dword(HWIO_GCC_UFS_PHY_PHY_AUX_CBCR_ADDR,v) +#define HWIO_GCC_UFS_PHY_PHY_AUX_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_UFS_PHY_PHY_AUX_CBCR_ADDR,m,v,HWIO_GCC_UFS_PHY_PHY_AUX_CBCR_IN) +#define HWIO_GCC_UFS_PHY_PHY_AUX_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_UFS_PHY_PHY_AUX_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_UFS_PHY_PHY_AUX_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000670b4) +#define HWIO_GCC_UFS_PHY_PHY_AUX_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000670b4) +#define HWIO_GCC_UFS_PHY_PHY_AUX_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000670b4) +#define HWIO_GCC_UFS_PHY_PHY_AUX_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_UFS_PHY_PHY_AUX_CMD_RCGR_ADDR, HWIO_GCC_UFS_PHY_PHY_AUX_CMD_RCGR_RMSK) +#define HWIO_GCC_UFS_PHY_PHY_AUX_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_UFS_PHY_PHY_AUX_CMD_RCGR_ADDR, m) +#define HWIO_GCC_UFS_PHY_PHY_AUX_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_UFS_PHY_PHY_AUX_CMD_RCGR_ADDR,v) +#define HWIO_GCC_UFS_PHY_PHY_AUX_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_UFS_PHY_PHY_AUX_CMD_RCGR_ADDR,m,v,HWIO_GCC_UFS_PHY_PHY_AUX_CMD_RCGR_IN) +#define HWIO_GCC_UFS_PHY_PHY_AUX_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_UFS_PHY_PHY_AUX_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000670b8) +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000670b8) +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000670b8) +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_ADDR, HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_RMSK) +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_ADDR, m) +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_ADDR,v) +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_ADDR,m,v,HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_IN) +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000670cc) +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000670cc) +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000670cc) +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_CBCR_ATTR 0x3 +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_CBCR_IN \ + in_dword_masked(HWIO_GCC_UFS_PHY_RX_SYMBOL_1_CBCR_ADDR, HWIO_GCC_UFS_PHY_RX_SYMBOL_1_CBCR_RMSK) +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_UFS_PHY_RX_SYMBOL_1_CBCR_ADDR, m) +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_CBCR_OUT(v) \ + out_dword(HWIO_GCC_UFS_PHY_RX_SYMBOL_1_CBCR_ADDR,v) +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_UFS_PHY_RX_SYMBOL_1_CBCR_ADDR,m,v,HWIO_GCC_UFS_PHY_RX_SYMBOL_1_CBCR_IN) +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_UFS_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000670d0) +#define HWIO_GCC_UFS_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000670d0) +#define HWIO_GCC_UFS_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000670d0) +#define HWIO_GCC_UFS_AT_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_UFS_AT_CBCR_ATTR 0x3 +#define HWIO_GCC_UFS_AT_CBCR_IN \ + in_dword_masked(HWIO_GCC_UFS_AT_CBCR_ADDR, HWIO_GCC_UFS_AT_CBCR_RMSK) +#define HWIO_GCC_UFS_AT_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_UFS_AT_CBCR_ADDR, m) +#define HWIO_GCC_UFS_AT_CBCR_OUT(v) \ + out_dword(HWIO_GCC_UFS_AT_CBCR_ADDR,v) +#define HWIO_GCC_UFS_AT_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_UFS_AT_CBCR_ADDR,m,v,HWIO_GCC_UFS_AT_CBCR_IN) +#define HWIO_GCC_UFS_AT_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_UFS_AT_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_UFS_AT_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_UFS_AT_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_UFS_AT_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_UFS_AT_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_UFS_AT_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_UFS_AT_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_UFS_AT_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_UFS_AT_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_UFS_AT_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_UFS_AT_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_UFS_AT_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_UFS_AT_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_UFS_AT_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_UFS_AT_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_UFS_AT_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_UFS_AT_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_UFS_AT_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_AT_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_UFS_AT_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_UFS_AT_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_UFS_AT_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_UFS_AT_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_DIV_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000670d8) +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_DIV_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000670d8) +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_DIV_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000670d8) +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_DIV_CDIVR_RMSK 0xf +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_DIV_CDIVR_ATTR 0x3 +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_DIV_CDIVR_IN \ + in_dword_masked(HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_DIV_CDIVR_ADDR, HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_DIV_CDIVR_RMSK) +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_DIV_CDIVR_INM(m) \ + in_dword_masked(HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_DIV_CDIVR_ADDR, m) +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_DIV_CDIVR_OUT(v) \ + out_dword(HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_DIV_CDIVR_ADDR,v) +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_DIV_CDIVR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_DIV_CDIVR_ADDR,m,v,HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_DIV_CDIVR_IN) +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_DIV_CDIVR_CLK_DIV_BMSK 0xf +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_DIV_CDIVR_CLK_DIV_SHFT 0x0 + +#define HWIO_GCC_VS_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006a000) +#define HWIO_GCC_VS_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006a000) +#define HWIO_GCC_VS_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006a000) +#define HWIO_GCC_VS_BCR_RMSK 0x1 +#define HWIO_GCC_VS_BCR_ATTR 0x3 +#define HWIO_GCC_VS_BCR_IN \ + in_dword_masked(HWIO_GCC_VS_BCR_ADDR, HWIO_GCC_VS_BCR_RMSK) +#define HWIO_GCC_VS_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_VS_BCR_ADDR, m) +#define HWIO_GCC_VS_BCR_OUT(v) \ + out_dword(HWIO_GCC_VS_BCR_ADDR,v) +#define HWIO_GCC_VS_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_VS_BCR_ADDR,m,v,HWIO_GCC_VS_BCR_IN) +#define HWIO_GCC_VS_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_VS_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_VS_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_VS_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_VDDMXC_VS_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006a004) +#define HWIO_GCC_VDDMXC_VS_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006a004) +#define HWIO_GCC_VDDMXC_VS_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006a004) +#define HWIO_GCC_VDDMXC_VS_CBCR_RMSK 0x81c0000f +#define HWIO_GCC_VDDMXC_VS_CBCR_ATTR 0x3 +#define HWIO_GCC_VDDMXC_VS_CBCR_IN \ + in_dword_masked(HWIO_GCC_VDDMXC_VS_CBCR_ADDR, HWIO_GCC_VDDMXC_VS_CBCR_RMSK) +#define HWIO_GCC_VDDMXC_VS_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_VDDMXC_VS_CBCR_ADDR, m) +#define HWIO_GCC_VDDMXC_VS_CBCR_OUT(v) \ + out_dword(HWIO_GCC_VDDMXC_VS_CBCR_ADDR,v) +#define HWIO_GCC_VDDMXC_VS_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_VDDMXC_VS_CBCR_ADDR,m,v,HWIO_GCC_VDDMXC_VS_CBCR_IN) +#define HWIO_GCC_VDDMXC_VS_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_VDDMXC_VS_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_VDDMXC_VS_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_VDDMXC_VS_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_VDDMXC_VS_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_VDDMXC_VS_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_VDDMXC_VS_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_VDDMXC_VS_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_VDDMXC_VS_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_VDDMXC_VS_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_VDDMXC_VS_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_VDDMXC_VS_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_VDDMXC_VS_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_VDDMXC_VS_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_VDDMXC_VS_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_VDDMXC_VS_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_VDDMXC_VS_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_VDDMXC_VS_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_VDDMXC_VS_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_VDDMXC_VS_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_VDDMXC_VS_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_VDDMXC_VS_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_VDDCX_VS_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006a008) +#define HWIO_GCC_VDDCX_VS_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006a008) +#define HWIO_GCC_VDDCX_VS_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006a008) +#define HWIO_GCC_VDDCX_VS_CBCR_RMSK 0x81c0000f +#define HWIO_GCC_VDDCX_VS_CBCR_ATTR 0x3 +#define HWIO_GCC_VDDCX_VS_CBCR_IN \ + in_dword_masked(HWIO_GCC_VDDCX_VS_CBCR_ADDR, HWIO_GCC_VDDCX_VS_CBCR_RMSK) +#define HWIO_GCC_VDDCX_VS_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_VDDCX_VS_CBCR_ADDR, m) +#define HWIO_GCC_VDDCX_VS_CBCR_OUT(v) \ + out_dword(HWIO_GCC_VDDCX_VS_CBCR_ADDR,v) +#define HWIO_GCC_VDDCX_VS_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_VDDCX_VS_CBCR_ADDR,m,v,HWIO_GCC_VDDCX_VS_CBCR_IN) +#define HWIO_GCC_VDDCX_VS_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_VDDCX_VS_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_VDDCX_VS_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_VDDCX_VS_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_VDDCX_VS_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_VDDCX_VS_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_VDDCX_VS_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_VDDCX_VS_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_VDDCX_VS_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_VDDCX_VS_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_VDDCX_VS_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_VDDCX_VS_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_VDDCX_VS_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_VDDCX_VS_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_VDDCX_VS_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_VDDCX_VS_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_VDDCX_VS_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_VDDCX_VS_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_VDDCX_VS_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_VDDCX_VS_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_VDDCX_VS_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_VDDCX_VS_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_VDDMX_VS_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006a00c) +#define HWIO_GCC_VDDMX_VS_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006a00c) +#define HWIO_GCC_VDDMX_VS_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006a00c) +#define HWIO_GCC_VDDMX_VS_CBCR_RMSK 0x81c0000f +#define HWIO_GCC_VDDMX_VS_CBCR_ATTR 0x3 +#define HWIO_GCC_VDDMX_VS_CBCR_IN \ + in_dword_masked(HWIO_GCC_VDDMX_VS_CBCR_ADDR, HWIO_GCC_VDDMX_VS_CBCR_RMSK) +#define HWIO_GCC_VDDMX_VS_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_VDDMX_VS_CBCR_ADDR, m) +#define HWIO_GCC_VDDMX_VS_CBCR_OUT(v) \ + out_dword(HWIO_GCC_VDDMX_VS_CBCR_ADDR,v) +#define HWIO_GCC_VDDMX_VS_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_VDDMX_VS_CBCR_ADDR,m,v,HWIO_GCC_VDDMX_VS_CBCR_IN) +#define HWIO_GCC_VDDMX_VS_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_VDDMX_VS_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_VDDMX_VS_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_VDDMX_VS_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_VDDMX_VS_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_VDDMX_VS_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_VDDMX_VS_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_VDDMX_VS_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_VDDMX_VS_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_VDDMX_VS_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_VDDMX_VS_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_VDDMX_VS_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_VDDMX_VS_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_VDDMX_VS_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_VDDMX_VS_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_VDDMX_VS_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_VDDMX_VS_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_VDDMX_VS_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_VDDMX_VS_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_VDDMX_VS_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_VDDMX_VS_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_VDDMX_VS_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_VDDA_VS_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006a010) +#define HWIO_GCC_VDDA_VS_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006a010) +#define HWIO_GCC_VDDA_VS_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006a010) +#define HWIO_GCC_VDDA_VS_CBCR_RMSK 0x81c0000f +#define HWIO_GCC_VDDA_VS_CBCR_ATTR 0x3 +#define HWIO_GCC_VDDA_VS_CBCR_IN \ + in_dword_masked(HWIO_GCC_VDDA_VS_CBCR_ADDR, HWIO_GCC_VDDA_VS_CBCR_RMSK) +#define HWIO_GCC_VDDA_VS_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_VDDA_VS_CBCR_ADDR, m) +#define HWIO_GCC_VDDA_VS_CBCR_OUT(v) \ + out_dword(HWIO_GCC_VDDA_VS_CBCR_ADDR,v) +#define HWIO_GCC_VDDA_VS_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_VDDA_VS_CBCR_ADDR,m,v,HWIO_GCC_VDDA_VS_CBCR_IN) +#define HWIO_GCC_VDDA_VS_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_VDDA_VS_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_VDDA_VS_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_VDDA_VS_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_VDDA_VS_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_VDDA_VS_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_VDDA_VS_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_VDDA_VS_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_VDDA_VS_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_VDDA_VS_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_VDDA_VS_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_VDDA_VS_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_VDDA_VS_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_VDDA_VS_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_VDDA_VS_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_VDDA_VS_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_VDDA_VS_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_VDDA_VS_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_VDDA_VS_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_VDDA_VS_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_VDDA_VS_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_VDDA_VS_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_VS_CTRL_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006a014) +#define HWIO_GCC_VS_CTRL_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006a014) +#define HWIO_GCC_VS_CTRL_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006a014) +#define HWIO_GCC_VS_CTRL_CBCR_RMSK 0x81c0000f +#define HWIO_GCC_VS_CTRL_CBCR_ATTR 0x3 +#define HWIO_GCC_VS_CTRL_CBCR_IN \ + in_dword_masked(HWIO_GCC_VS_CTRL_CBCR_ADDR, HWIO_GCC_VS_CTRL_CBCR_RMSK) +#define HWIO_GCC_VS_CTRL_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_VS_CTRL_CBCR_ADDR, m) +#define HWIO_GCC_VS_CTRL_CBCR_OUT(v) \ + out_dword(HWIO_GCC_VS_CTRL_CBCR_ADDR,v) +#define HWIO_GCC_VS_CTRL_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_VS_CTRL_CBCR_ADDR,m,v,HWIO_GCC_VS_CTRL_CBCR_IN) +#define HWIO_GCC_VS_CTRL_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_VS_CTRL_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_VS_CTRL_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_VS_CTRL_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_VS_CTRL_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_VS_CTRL_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_VS_CTRL_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_VS_CTRL_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_VS_CTRL_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_VS_CTRL_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_VS_CTRL_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_VS_CTRL_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_VS_CTRL_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_VS_CTRL_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_VS_CTRL_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_VS_CTRL_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_VS_CTRL_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_VS_CTRL_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_VS_CTRL_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_VS_CTRL_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_VS_CTRL_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_VS_CTRL_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_VS_CTRL_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006a018) +#define HWIO_GCC_VS_CTRL_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006a018) +#define HWIO_GCC_VS_CTRL_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006a018) +#define HWIO_GCC_VS_CTRL_AHB_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_VS_CTRL_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_VS_CTRL_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_VS_CTRL_AHB_CBCR_ADDR, HWIO_GCC_VS_CTRL_AHB_CBCR_RMSK) +#define HWIO_GCC_VS_CTRL_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_VS_CTRL_AHB_CBCR_ADDR, m) +#define HWIO_GCC_VS_CTRL_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_VS_CTRL_AHB_CBCR_ADDR,v) +#define HWIO_GCC_VS_CTRL_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_VS_CTRL_AHB_CBCR_ADDR,m,v,HWIO_GCC_VS_CTRL_AHB_CBCR_IN) +#define HWIO_GCC_VS_CTRL_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_VS_CTRL_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_VS_CTRL_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_VS_CTRL_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_VS_CTRL_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_VS_CTRL_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_VS_CTRL_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_VS_CTRL_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_VS_CTRL_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_VS_CTRL_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_VS_CTRL_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_VS_CTRL_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_VS_CTRL_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_VS_CTRL_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_VS_CTRL_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_VS_CTRL_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_VS_CTRL_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_VS_CTRL_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_VS_CTRL_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_VS_CTRL_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_VS_CTRL_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_VS_CTRL_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_VS_CTRL_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_VS_CTRL_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_VSENSOR_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006a01c) +#define HWIO_GCC_VSENSOR_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006a01c) +#define HWIO_GCC_VSENSOR_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006a01c) +#define HWIO_GCC_VSENSOR_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_VSENSOR_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_VSENSOR_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_VSENSOR_CMD_RCGR_ADDR, HWIO_GCC_VSENSOR_CMD_RCGR_RMSK) +#define HWIO_GCC_VSENSOR_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_VSENSOR_CMD_RCGR_ADDR, m) +#define HWIO_GCC_VSENSOR_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_VSENSOR_CMD_RCGR_ADDR,v) +#define HWIO_GCC_VSENSOR_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_VSENSOR_CMD_RCGR_ADDR,m,v,HWIO_GCC_VSENSOR_CMD_RCGR_IN) +#define HWIO_GCC_VSENSOR_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_VSENSOR_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_VSENSOR_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_VSENSOR_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_VSENSOR_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_VSENSOR_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_VSENSOR_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_VSENSOR_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_VSENSOR_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_VSENSOR_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_VSENSOR_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_VSENSOR_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_VSENSOR_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006a020) +#define HWIO_GCC_VSENSOR_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006a020) +#define HWIO_GCC_VSENSOR_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006a020) +#define HWIO_GCC_VSENSOR_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_VSENSOR_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_VSENSOR_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_VSENSOR_CFG_RCGR_ADDR, HWIO_GCC_VSENSOR_CFG_RCGR_RMSK) +#define HWIO_GCC_VSENSOR_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_VSENSOR_CFG_RCGR_ADDR, m) +#define HWIO_GCC_VSENSOR_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_VSENSOR_CFG_RCGR_ADDR,v) +#define HWIO_GCC_VSENSOR_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_VSENSOR_CFG_RCGR_ADDR,m,v,HWIO_GCC_VSENSOR_CFG_RCGR_IN) +#define HWIO_GCC_VSENSOR_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_VSENSOR_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_VSENSOR_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_VSENSOR_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_VSENSOR_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_VSENSOR_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_VSENSOR_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_VSENSOR_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_VS_CTRL_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006a034) +#define HWIO_GCC_VS_CTRL_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006a034) +#define HWIO_GCC_VS_CTRL_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006a034) +#define HWIO_GCC_VS_CTRL_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_VS_CTRL_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_VS_CTRL_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_VS_CTRL_CMD_RCGR_ADDR, HWIO_GCC_VS_CTRL_CMD_RCGR_RMSK) +#define HWIO_GCC_VS_CTRL_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_VS_CTRL_CMD_RCGR_ADDR, m) +#define HWIO_GCC_VS_CTRL_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_VS_CTRL_CMD_RCGR_ADDR,v) +#define HWIO_GCC_VS_CTRL_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_VS_CTRL_CMD_RCGR_ADDR,m,v,HWIO_GCC_VS_CTRL_CMD_RCGR_IN) +#define HWIO_GCC_VS_CTRL_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_VS_CTRL_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_VS_CTRL_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_VS_CTRL_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_VS_CTRL_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_VS_CTRL_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_VS_CTRL_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_VS_CTRL_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_VS_CTRL_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_VS_CTRL_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_VS_CTRL_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_VS_CTRL_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_VS_CTRL_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006a038) +#define HWIO_GCC_VS_CTRL_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006a038) +#define HWIO_GCC_VS_CTRL_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006a038) +#define HWIO_GCC_VS_CTRL_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_VS_CTRL_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_VS_CTRL_CFG_RCGR_ADDR, HWIO_GCC_VS_CTRL_CFG_RCGR_RMSK) +#define HWIO_GCC_VS_CTRL_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_VS_CTRL_CFG_RCGR_ADDR, m) +#define HWIO_GCC_VS_CTRL_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_VS_CTRL_CFG_RCGR_ADDR,v) +#define HWIO_GCC_VS_CTRL_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_VS_CTRL_CFG_RCGR_ADDR,m,v,HWIO_GCC_VS_CTRL_CFG_RCGR_IN) +#define HWIO_GCC_VS_CTRL_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_MSS_VS_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006a04c) +#define HWIO_GCC_MSS_VS_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006a04c) +#define HWIO_GCC_MSS_VS_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006a04c) +#define HWIO_GCC_MSS_VS_CBCR_RMSK 0x81c0000f +#define HWIO_GCC_MSS_VS_CBCR_ATTR 0x3 +#define HWIO_GCC_MSS_VS_CBCR_IN \ + in_dword_masked(HWIO_GCC_MSS_VS_CBCR_ADDR, HWIO_GCC_MSS_VS_CBCR_RMSK) +#define HWIO_GCC_MSS_VS_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_VS_CBCR_ADDR, m) +#define HWIO_GCC_MSS_VS_CBCR_OUT(v) \ + out_dword(HWIO_GCC_MSS_VS_CBCR_ADDR,v) +#define HWIO_GCC_MSS_VS_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_VS_CBCR_ADDR,m,v,HWIO_GCC_MSS_VS_CBCR_IN) +#define HWIO_GCC_MSS_VS_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_MSS_VS_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_MSS_VS_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_MSS_VS_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_MSS_VS_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_MSS_VS_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_MSS_VS_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_MSS_VS_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_MSS_VS_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_MSS_VS_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_MSS_VS_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_MSS_VS_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_MSS_VS_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_MSS_VS_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_MSS_VS_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_MSS_VS_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_MSS_VS_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_VS_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_VS_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_MSS_VS_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_MSS_VS_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_VS_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GPU_VS_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006a050) +#define HWIO_GCC_GPU_VS_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006a050) +#define HWIO_GCC_GPU_VS_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006a050) +#define HWIO_GCC_GPU_VS_CBCR_RMSK 0x81c0000f +#define HWIO_GCC_GPU_VS_CBCR_ATTR 0x3 +#define HWIO_GCC_GPU_VS_CBCR_IN \ + in_dword_masked(HWIO_GCC_GPU_VS_CBCR_ADDR, HWIO_GCC_GPU_VS_CBCR_RMSK) +#define HWIO_GCC_GPU_VS_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_GPU_VS_CBCR_ADDR, m) +#define HWIO_GCC_GPU_VS_CBCR_OUT(v) \ + out_dword(HWIO_GCC_GPU_VS_CBCR_ADDR,v) +#define HWIO_GCC_GPU_VS_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPU_VS_CBCR_ADDR,m,v,HWIO_GCC_GPU_VS_CBCR_IN) +#define HWIO_GCC_GPU_VS_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_GPU_VS_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_GPU_VS_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_GPU_VS_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_GPU_VS_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_GPU_VS_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_GPU_VS_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_GPU_VS_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_GPU_VS_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_GPU_VS_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_GPU_VS_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_GPU_VS_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_GPU_VS_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_GPU_VS_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_GPU_VS_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_GPU_VS_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_GPU_VS_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_GPU_VS_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_GPU_VS_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GPU_VS_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_GPU_VS_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GPU_VS_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_APC_VS_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006a054) +#define HWIO_GCC_APC_VS_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006a054) +#define HWIO_GCC_APC_VS_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006a054) +#define HWIO_GCC_APC_VS_CBCR_RMSK 0x81c0000f +#define HWIO_GCC_APC_VS_CBCR_ATTR 0x3 +#define HWIO_GCC_APC_VS_CBCR_IN \ + in_dword_masked(HWIO_GCC_APC_VS_CBCR_ADDR, HWIO_GCC_APC_VS_CBCR_RMSK) +#define HWIO_GCC_APC_VS_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_APC_VS_CBCR_ADDR, m) +#define HWIO_GCC_APC_VS_CBCR_OUT(v) \ + out_dword(HWIO_GCC_APC_VS_CBCR_ADDR,v) +#define HWIO_GCC_APC_VS_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_APC_VS_CBCR_ADDR,m,v,HWIO_GCC_APC_VS_CBCR_IN) +#define HWIO_GCC_APC_VS_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_APC_VS_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_APC_VS_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_APC_VS_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_APC_VS_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_APC_VS_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_APC_VS_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_APC_VS_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_APC_VS_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_APC_VS_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_APC_VS_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_APC_VS_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_APC_VS_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_APC_VS_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_APC_VS_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_APC_VS_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_APC_VS_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_APC_VS_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_APC_VS_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_APC_VS_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_APC_VS_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APC_VS_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MDSS_VS_0_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006a058) +#define HWIO_GCC_MDSS_VS_0_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006a058) +#define HWIO_GCC_MDSS_VS_0_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006a058) +#define HWIO_GCC_MDSS_VS_0_CBCR_RMSK 0x81c0000f +#define HWIO_GCC_MDSS_VS_0_CBCR_ATTR 0x3 +#define HWIO_GCC_MDSS_VS_0_CBCR_IN \ + in_dword_masked(HWIO_GCC_MDSS_VS_0_CBCR_ADDR, HWIO_GCC_MDSS_VS_0_CBCR_RMSK) +#define HWIO_GCC_MDSS_VS_0_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_MDSS_VS_0_CBCR_ADDR, m) +#define HWIO_GCC_MDSS_VS_0_CBCR_OUT(v) \ + out_dword(HWIO_GCC_MDSS_VS_0_CBCR_ADDR,v) +#define HWIO_GCC_MDSS_VS_0_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MDSS_VS_0_CBCR_ADDR,m,v,HWIO_GCC_MDSS_VS_0_CBCR_IN) +#define HWIO_GCC_MDSS_VS_0_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_MDSS_VS_0_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_MDSS_VS_0_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_MDSS_VS_0_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_MDSS_VS_0_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_MDSS_VS_0_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_MDSS_VS_0_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_MDSS_VS_0_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_MDSS_VS_0_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_MDSS_VS_0_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_MDSS_VS_0_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_MDSS_VS_0_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_MDSS_VS_0_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_MDSS_VS_0_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_MDSS_VS_0_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_MDSS_VS_0_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_MDSS_VS_0_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_MDSS_VS_0_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_MDSS_VS_0_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_MDSS_VS_0_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_MDSS_VS_0_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MDSS_VS_0_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MDSS_VS_1_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006a05c) +#define HWIO_GCC_MDSS_VS_1_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006a05c) +#define HWIO_GCC_MDSS_VS_1_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006a05c) +#define HWIO_GCC_MDSS_VS_1_CBCR_RMSK 0x81c0000f +#define HWIO_GCC_MDSS_VS_1_CBCR_ATTR 0x3 +#define HWIO_GCC_MDSS_VS_1_CBCR_IN \ + in_dword_masked(HWIO_GCC_MDSS_VS_1_CBCR_ADDR, HWIO_GCC_MDSS_VS_1_CBCR_RMSK) +#define HWIO_GCC_MDSS_VS_1_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_MDSS_VS_1_CBCR_ADDR, m) +#define HWIO_GCC_MDSS_VS_1_CBCR_OUT(v) \ + out_dword(HWIO_GCC_MDSS_VS_1_CBCR_ADDR,v) +#define HWIO_GCC_MDSS_VS_1_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MDSS_VS_1_CBCR_ADDR,m,v,HWIO_GCC_MDSS_VS_1_CBCR_IN) +#define HWIO_GCC_MDSS_VS_1_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_MDSS_VS_1_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_MDSS_VS_1_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_MDSS_VS_1_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_MDSS_VS_1_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_MDSS_VS_1_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_MDSS_VS_1_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_MDSS_VS_1_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_MDSS_VS_1_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_MDSS_VS_1_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_MDSS_VS_1_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_MDSS_VS_1_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_MDSS_VS_1_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_MDSS_VS_1_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_MDSS_VS_1_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_MDSS_VS_1_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_MDSS_VS_1_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_MDSS_VS_1_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_MDSS_VS_1_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_MDSS_VS_1_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_MDSS_VS_1_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MDSS_VS_1_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_DCC_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00074000) +#define HWIO_GCC_DCC_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00074000) +#define HWIO_GCC_DCC_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00074000) +#define HWIO_GCC_DCC_BCR_RMSK 0x1 +#define HWIO_GCC_DCC_BCR_ATTR 0x3 +#define HWIO_GCC_DCC_BCR_IN \ + in_dword_masked(HWIO_GCC_DCC_BCR_ADDR, HWIO_GCC_DCC_BCR_RMSK) +#define HWIO_GCC_DCC_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_DCC_BCR_ADDR, m) +#define HWIO_GCC_DCC_BCR_OUT(v) \ + out_dword(HWIO_GCC_DCC_BCR_ADDR,v) +#define HWIO_GCC_DCC_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DCC_BCR_ADDR,m,v,HWIO_GCC_DCC_BCR_IN) +#define HWIO_GCC_DCC_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_DCC_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_DCC_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_DCC_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_DCC_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00074004) +#define HWIO_GCC_DCC_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00074004) +#define HWIO_GCC_DCC_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00074004) +#define HWIO_GCC_DCC_AHB_CBCR_RMSK 0x81d0700f +#define HWIO_GCC_DCC_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_DCC_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_DCC_AHB_CBCR_ADDR, HWIO_GCC_DCC_AHB_CBCR_RMSK) +#define HWIO_GCC_DCC_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_DCC_AHB_CBCR_ADDR, m) +#define HWIO_GCC_DCC_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_DCC_AHB_CBCR_ADDR,v) +#define HWIO_GCC_DCC_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DCC_AHB_CBCR_ADDR,m,v,HWIO_GCC_DCC_AHB_CBCR_IN) +#define HWIO_GCC_DCC_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_DCC_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_DCC_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_DCC_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_DCC_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_DCC_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_DCC_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_DCC_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_DCC_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_DCC_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_DCC_AHB_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_DCC_AHB_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_DCC_AHB_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DCC_AHB_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_DCC_AHB_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_DCC_AHB_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_DCC_AHB_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DCC_AHB_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_DCC_AHB_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_DCC_AHB_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_DCC_AHB_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DCC_AHB_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_DCC_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_DCC_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_DCC_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_DCC_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_DCC_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_DCC_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_DCC_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_DCC_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_DCC_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_DCC_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_DCC_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_DCC_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_DCC_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DCC_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_DCC_AHB_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00074008) +#define HWIO_GCC_DCC_AHB_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00074008) +#define HWIO_GCC_DCC_AHB_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00074008) +#define HWIO_GCC_DCC_AHB_SREGR_RMSK 0xf1ffffe +#define HWIO_GCC_DCC_AHB_SREGR_ATTR 0x3 +#define HWIO_GCC_DCC_AHB_SREGR_IN \ + in_dword_masked(HWIO_GCC_DCC_AHB_SREGR_ADDR, HWIO_GCC_DCC_AHB_SREGR_RMSK) +#define HWIO_GCC_DCC_AHB_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_DCC_AHB_SREGR_ADDR, m) +#define HWIO_GCC_DCC_AHB_SREGR_OUT(v) \ + out_dword(HWIO_GCC_DCC_AHB_SREGR_ADDR,v) +#define HWIO_GCC_DCC_AHB_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DCC_AHB_SREGR_ADDR,m,v,HWIO_GCC_DCC_AHB_SREGR_IN) +#define HWIO_GCC_DCC_AHB_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xf000000 +#define HWIO_GCC_DCC_AHB_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_DCC_AHB_SREGR_PWR_FSM_CLK_SEL_BMSK 0x100000 +#define HWIO_GCC_DCC_AHB_SREGR_PWR_FSM_CLK_SEL_SHFT 0x14 +#define HWIO_GCC_DCC_AHB_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xf0000 +#define HWIO_GCC_DCC_AHB_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_DCC_AHB_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_DCC_AHB_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_DCC_AHB_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_DCC_AHB_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_DCC_AHB_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_DCC_AHB_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_DCC_AHB_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_DCC_AHB_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_DCC_AHB_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_DCC_AHB_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_DCC_AHB_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_DCC_AHB_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_DCC_AHB_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_DCC_AHB_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_DCC_AHB_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_DCC_AHB_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_DCC_AHB_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_DCC_AHB_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_DCC_AHB_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_DCC_AHB_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_DCC_AHB_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_DCC_AHB_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_DCC_AHB_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_DCC_AHB_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_DCC_AHB_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_DCC_AHB_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_DCC_AHB_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_DCC_AHB_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_DCC_AHB_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DCC_AHB_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_DCC_AHB_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_DCC_AHB_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_DCC_AHB_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_DCC_AHB_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_DCC_AHB_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_DCC_AHB_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_DCC_AHB_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_DCC_AHB_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_DCC_AHB_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_DCC_AHB_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_DCC_AHB_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_DCC_AHB_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_DCC_AHB_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_DCC_AHB_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_DCC_AHB_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_DCC_AHB_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_DCC_AHB_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_DCC_AHB_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_DCC_AHB_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_DCC_AHB_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_DCC_AHB_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_DCC_AHB_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_DCC_AHB_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_DCC_AHB_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_DCC_AHB_CFG_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007400c) +#define HWIO_GCC_DCC_AHB_CFG_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007400c) +#define HWIO_GCC_DCC_AHB_CFG_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007400c) +#define HWIO_GCC_DCC_AHB_CFG_SREGR_RMSK 0xffffffff +#define HWIO_GCC_DCC_AHB_CFG_SREGR_ATTR 0x3 +#define HWIO_GCC_DCC_AHB_CFG_SREGR_IN \ + in_dword_masked(HWIO_GCC_DCC_AHB_CFG_SREGR_ADDR, HWIO_GCC_DCC_AHB_CFG_SREGR_RMSK) +#define HWIO_GCC_DCC_AHB_CFG_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_DCC_AHB_CFG_SREGR_ADDR, m) +#define HWIO_GCC_DCC_AHB_CFG_SREGR_OUT(v) \ + out_dword(HWIO_GCC_DCC_AHB_CFG_SREGR_ADDR,v) +#define HWIO_GCC_DCC_AHB_CFG_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DCC_AHB_CFG_SREGR_ADDR,m,v,HWIO_GCC_DCC_AHB_CFG_SREGR_IN) +#define HWIO_GCC_DCC_AHB_CFG_SREGR_MEM_CORE_OFF_TIMER_BMSK 0xfc000000 +#define HWIO_GCC_DCC_AHB_CFG_SREGR_MEM_CORE_OFF_TIMER_SHFT 0x1a +#define HWIO_GCC_DCC_AHB_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_BMSK 0x2000000 +#define HWIO_GCC_DCC_AHB_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_SHFT 0x19 +#define HWIO_GCC_DCC_AHB_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_BMSK 0x1000000 +#define HWIO_GCC_DCC_AHB_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_SHFT 0x18 +#define HWIO_GCC_DCC_AHB_CFG_SREGR_MEM_PERIPH_ON_STATUS_BMSK 0x800000 +#define HWIO_GCC_DCC_AHB_CFG_SREGR_MEM_PERIPH_ON_STATUS_SHFT 0x17 +#define HWIO_GCC_DCC_AHB_CFG_SREGR_MEM_CORE_ON_STATUS_BMSK 0x400000 +#define HWIO_GCC_DCC_AHB_CFG_SREGR_MEM_CORE_ON_STATUS_SHFT 0x16 +#define HWIO_GCC_DCC_AHB_CFG_SREGR_MEM_CPH_TIMER_BMSK 0x3f0000 +#define HWIO_GCC_DCC_AHB_CFG_SREGR_MEM_CPH_TIMER_SHFT 0x10 +#define HWIO_GCC_DCC_AHB_CFG_SREGR_SLEEP_TIMER_BMSK 0xff00 +#define HWIO_GCC_DCC_AHB_CFG_SREGR_SLEEP_TIMER_SHFT 0x8 +#define HWIO_GCC_DCC_AHB_CFG_SREGR_WAKEUP_TIMER_BMSK 0xff +#define HWIO_GCC_DCC_AHB_CFG_SREGR_WAKEUP_TIMER_SHFT 0x0 + +#define HWIO_GCC_IPA_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00079000) +#define HWIO_GCC_IPA_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00079000) +#define HWIO_GCC_IPA_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00079000) +#define HWIO_GCC_IPA_BCR_RMSK 0x1 +#define HWIO_GCC_IPA_BCR_ATTR 0x3 +#define HWIO_GCC_IPA_BCR_IN \ + in_dword_masked(HWIO_GCC_IPA_BCR_ADDR, HWIO_GCC_IPA_BCR_RMSK) +#define HWIO_GCC_IPA_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_IPA_BCR_ADDR, m) +#define HWIO_GCC_IPA_BCR_OUT(v) \ + out_dword(HWIO_GCC_IPA_BCR_ADDR,v) +#define HWIO_GCC_IPA_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_IPA_BCR_ADDR,m,v,HWIO_GCC_IPA_BCR_IN) +#define HWIO_GCC_IPA_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_IPA_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_IPA_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_IPA_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00079004) +#define HWIO_GCC_IPA_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00079004) +#define HWIO_GCC_IPA_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00079004) +#define HWIO_GCC_IPA_GDSCR_RMSK 0xf8ffffff +#define HWIO_GCC_IPA_GDSCR_ATTR 0x3 +#define HWIO_GCC_IPA_GDSCR_IN \ + in_dword_masked(HWIO_GCC_IPA_GDSCR_ADDR, HWIO_GCC_IPA_GDSCR_RMSK) +#define HWIO_GCC_IPA_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_IPA_GDSCR_ADDR, m) +#define HWIO_GCC_IPA_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_IPA_GDSCR_ADDR,v) +#define HWIO_GCC_IPA_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_IPA_GDSCR_ADDR,m,v,HWIO_GCC_IPA_GDSCR_IN) +#define HWIO_GCC_IPA_GDSCR_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_IPA_GDSCR_PWR_ON_SHFT 0x1f +#define HWIO_GCC_IPA_GDSCR_GDSC_STATE_BMSK 0x78000000 +#define HWIO_GCC_IPA_GDSCR_GDSC_STATE_SHFT 0x1b +#define HWIO_GCC_IPA_GDSCR_EN_REST_WAIT_BMSK 0xf00000 +#define HWIO_GCC_IPA_GDSCR_EN_REST_WAIT_SHFT 0x14 +#define HWIO_GCC_IPA_GDSCR_EN_FEW_WAIT_BMSK 0xf0000 +#define HWIO_GCC_IPA_GDSCR_EN_FEW_WAIT_SHFT 0x10 +#define HWIO_GCC_IPA_GDSCR_CLK_DIS_WAIT_BMSK 0xf000 +#define HWIO_GCC_IPA_GDSCR_CLK_DIS_WAIT_SHFT 0xc +#define HWIO_GCC_IPA_GDSCR_RETAIN_FF_ENABLE_BMSK 0x800 +#define HWIO_GCC_IPA_GDSCR_RETAIN_FF_ENABLE_SHFT 0xb +#define HWIO_GCC_IPA_GDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_GDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPA_GDSCR_RESTORE_BMSK 0x400 +#define HWIO_GCC_IPA_GDSCR_RESTORE_SHFT 0xa +#define HWIO_GCC_IPA_GDSCR_RESTORE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_GDSCR_RESTORE_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPA_GDSCR_SAVE_BMSK 0x200 +#define HWIO_GCC_IPA_GDSCR_SAVE_SHFT 0x9 +#define HWIO_GCC_IPA_GDSCR_SAVE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_GDSCR_SAVE_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPA_GDSCR_RETAIN_BMSK 0x100 +#define HWIO_GCC_IPA_GDSCR_RETAIN_SHFT 0x8 +#define HWIO_GCC_IPA_GDSCR_RETAIN_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_GDSCR_RETAIN_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPA_GDSCR_EN_REST_BMSK 0x80 +#define HWIO_GCC_IPA_GDSCR_EN_REST_SHFT 0x7 +#define HWIO_GCC_IPA_GDSCR_EN_REST_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_GDSCR_EN_REST_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPA_GDSCR_EN_FEW_BMSK 0x40 +#define HWIO_GCC_IPA_GDSCR_EN_FEW_SHFT 0x6 +#define HWIO_GCC_IPA_GDSCR_EN_FEW_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_GDSCR_EN_FEW_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPA_GDSCR_CLAMP_IO_BMSK 0x20 +#define HWIO_GCC_IPA_GDSCR_CLAMP_IO_SHFT 0x5 +#define HWIO_GCC_IPA_GDSCR_CLAMP_IO_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_GDSCR_CLAMP_IO_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPA_GDSCR_CLK_DISABLE_BMSK 0x10 +#define HWIO_GCC_IPA_GDSCR_CLK_DISABLE_SHFT 0x4 +#define HWIO_GCC_IPA_GDSCR_CLK_DISABLE_CLK_NOT_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_GDSCR_CLK_DISABLE_CLK_IS_DISABLE_FVAL 0x1 +#define HWIO_GCC_IPA_GDSCR_PD_ARES_BMSK 0x8 +#define HWIO_GCC_IPA_GDSCR_PD_ARES_SHFT 0x3 +#define HWIO_GCC_IPA_GDSCR_PD_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_IPA_GDSCR_PD_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_IPA_GDSCR_SW_OVERRIDE_BMSK 0x4 +#define HWIO_GCC_IPA_GDSCR_SW_OVERRIDE_SHFT 0x2 +#define HWIO_GCC_IPA_GDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_GDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPA_GDSCR_HW_CONTROL_BMSK 0x2 +#define HWIO_GCC_IPA_GDSCR_HW_CONTROL_SHFT 0x1 +#define HWIO_GCC_IPA_GDSCR_HW_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_GDSCR_HW_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPA_GDSCR_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_IPA_GDSCR_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_IPA_GDSCR_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_GDSCR_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_IPA_CFG_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00079008) +#define HWIO_GCC_IPA_CFG_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00079008) +#define HWIO_GCC_IPA_CFG_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00079008) +#define HWIO_GCC_IPA_CFG_GDSCR_RMSK 0x7ffffff +#define HWIO_GCC_IPA_CFG_GDSCR_ATTR 0x3 +#define HWIO_GCC_IPA_CFG_GDSCR_IN \ + in_dword_masked(HWIO_GCC_IPA_CFG_GDSCR_ADDR, HWIO_GCC_IPA_CFG_GDSCR_RMSK) +#define HWIO_GCC_IPA_CFG_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_IPA_CFG_GDSCR_ADDR, m) +#define HWIO_GCC_IPA_CFG_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_IPA_CFG_GDSCR_ADDR,v) +#define HWIO_GCC_IPA_CFG_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_IPA_CFG_GDSCR_ADDR,m,v,HWIO_GCC_IPA_CFG_GDSCR_IN) +#define HWIO_GCC_IPA_CFG_GDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4000000 +#define HWIO_GCC_IPA_CFG_GDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x1a +#define HWIO_GCC_IPA_CFG_GDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_CFG_GDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_PWR_DWN_START_BMSK 0x2000000 +#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_PWR_DWN_START_SHFT 0x19 +#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_PWR_UP_START_BMSK 0x1000000 +#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_PWR_UP_START_SHFT 0x18 +#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_BMSK 0xf00000 +#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_SHFT 0x14 +#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_BMSK 0x80000 +#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_SHFT 0x13 +#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_ENR_ACK_STATUS_BMSK 0x40000 +#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_ENR_ACK_STATUS_SHFT 0x12 +#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_ENF_ACK_STATUS_BMSK 0x20000 +#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_ENF_ACK_STATUS_SHFT 0x11 +#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_BMSK 0x10000 +#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_SHFT 0x10 +#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_BMSK 0x8000 +#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_SHFT 0xf +#define HWIO_GCC_IPA_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_BMSK 0x7800 +#define HWIO_GCC_IPA_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_SHFT 0xb +#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_HANDSHAKE_DIS_BMSK 0x400 +#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_HANDSHAKE_DIS_SHFT 0xa +#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_BMSK 0x200 +#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_SHFT 0x9 +#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_BMSK 0x100 +#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_SHFT 0x8 +#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_BMSK 0x80 +#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_SHFT 0x7 +#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_BMSK 0x60 +#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_SHFT 0x5 +#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_BMSK 0x10 +#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_SHFT 0x4 +#define HWIO_GCC_IPA_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_BMSK 0x8 +#define HWIO_GCC_IPA_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_SHFT 0x3 +#define HWIO_GCC_IPA_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_BMSK 0x4 +#define HWIO_GCC_IPA_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_SHFT 0x2 +#define HWIO_GCC_IPA_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_BMSK 0x2 +#define HWIO_GCC_IPA_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_SHFT 0x1 +#define HWIO_GCC_IPA_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_IPA_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_SHFT 0x0 + +#define HWIO_GCC_IPA_CFG2_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007900c) +#define HWIO_GCC_IPA_CFG2_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007900c) +#define HWIO_GCC_IPA_CFG2_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007900c) +#define HWIO_GCC_IPA_CFG2_GDSCR_RMSK 0x7ffff +#define HWIO_GCC_IPA_CFG2_GDSCR_ATTR 0x3 +#define HWIO_GCC_IPA_CFG2_GDSCR_IN \ + in_dword_masked(HWIO_GCC_IPA_CFG2_GDSCR_ADDR, HWIO_GCC_IPA_CFG2_GDSCR_RMSK) +#define HWIO_GCC_IPA_CFG2_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_IPA_CFG2_GDSCR_ADDR, m) +#define HWIO_GCC_IPA_CFG2_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_IPA_CFG2_GDSCR_ADDR,v) +#define HWIO_GCC_IPA_CFG2_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_IPA_CFG2_GDSCR_ADDR,m,v,HWIO_GCC_IPA_CFG2_GDSCR_IN) +#define HWIO_GCC_IPA_CFG2_GDSCR_GDSC_MEM_PWRUP_ACK_OVERRIDE_BMSK 0x40000 +#define HWIO_GCC_IPA_CFG2_GDSCR_GDSC_MEM_PWRUP_ACK_OVERRIDE_SHFT 0x12 +#define HWIO_GCC_IPA_CFG2_GDSCR_GDSC_PWRDWN_ENABLE_ACK_OVERRIDE_BMSK 0x20000 +#define HWIO_GCC_IPA_CFG2_GDSCR_GDSC_PWRDWN_ENABLE_ACK_OVERRIDE_SHFT 0x11 +#define HWIO_GCC_IPA_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_BMSK 0x10000 +#define HWIO_GCC_IPA_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_SHFT 0x10 +#define HWIO_GCC_IPA_CFG2_GDSCR_DLY_MEM_PWR_UP_BMSK 0xf000 +#define HWIO_GCC_IPA_CFG2_GDSCR_DLY_MEM_PWR_UP_SHFT 0xc +#define HWIO_GCC_IPA_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_BMSK 0xf00 +#define HWIO_GCC_IPA_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_SHFT 0x8 +#define HWIO_GCC_IPA_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_BMSK 0xf0 +#define HWIO_GCC_IPA_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_SHFT 0x4 +#define HWIO_GCC_IPA_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_BMSK 0xf +#define HWIO_GCC_IPA_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_SHFT 0x0 + +#define HWIO_GCC_IPA_CFG3_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00079010) +#define HWIO_GCC_IPA_CFG3_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00079010) +#define HWIO_GCC_IPA_CFG3_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00079010) +#define HWIO_GCC_IPA_CFG3_GDSCR_RMSK 0x7ffffff +#define HWIO_GCC_IPA_CFG3_GDSCR_ATTR 0x3 +#define HWIO_GCC_IPA_CFG3_GDSCR_IN \ + in_dword_masked(HWIO_GCC_IPA_CFG3_GDSCR_ADDR, HWIO_GCC_IPA_CFG3_GDSCR_RMSK) +#define HWIO_GCC_IPA_CFG3_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_IPA_CFG3_GDSCR_ADDR, m) +#define HWIO_GCC_IPA_CFG3_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_IPA_CFG3_GDSCR_ADDR,v) +#define HWIO_GCC_IPA_CFG3_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_IPA_CFG3_GDSCR_ADDR,m,v,HWIO_GCC_IPA_CFG3_GDSCR_IN) +#define HWIO_GCC_IPA_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_STATUS_BMSK 0x4000000 +#define HWIO_GCC_IPA_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_STATUS_SHFT 0x1a +#define HWIO_GCC_IPA_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_BMSK 0x2000000 +#define HWIO_GCC_IPA_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_SHFT 0x19 +#define HWIO_GCC_IPA_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_CFG3_GDSCR_GDSC_ACCU_RED_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPA_CFG3_GDSCR_DLY_ACCU_RED_SHIFTER_DONE_BMSK 0x1e00000 +#define HWIO_GCC_IPA_CFG3_GDSCR_DLY_ACCU_RED_SHIFTER_DONE_SHFT 0x15 +#define HWIO_GCC_IPA_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_BMSK 0x100000 +#define HWIO_GCC_IPA_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_SHFT 0x14 +#define HWIO_GCC_IPA_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_CFG3_GDSCR_GDSC_ACCU_RED_TIMER_EN_SW_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPA_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_BMSK 0x80000 +#define HWIO_GCC_IPA_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_SHFT 0x13 +#define HWIO_GCC_IPA_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_DONE_OVERRIDE_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPA_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_BMSK 0x40000 +#define HWIO_GCC_IPA_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_SHFT 0x12 +#define HWIO_GCC_IPA_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_CLK_EN_SW_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPA_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_BMSK 0x20000 +#define HWIO_GCC_IPA_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_SHFT 0x11 +#define HWIO_GCC_IPA_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_CFG3_GDSCR_GDSC_ACCU_RED_SHIFTER_START_SW_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPA_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_BMSK 0x10000 +#define HWIO_GCC_IPA_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_SHFT 0x10 +#define HWIO_GCC_IPA_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_CFG3_GDSCR_GDSC_ACCU_RED_SW_OVERRIDE_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPA_CFG3_GDSCR_GDSC_SPARE_CTRL_IN_BMSK 0xff00 +#define HWIO_GCC_IPA_CFG3_GDSCR_GDSC_SPARE_CTRL_IN_SHFT 0x8 +#define HWIO_GCC_IPA_CFG3_GDSCR_GDSC_SPARE_CTRL_OUT_BMSK 0xff +#define HWIO_GCC_IPA_CFG3_GDSCR_GDSC_SPARE_CTRL_OUT_SHFT 0x0 + +#define HWIO_GCC_IPA_CFG4_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00079014) +#define HWIO_GCC_IPA_CFG4_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00079014) +#define HWIO_GCC_IPA_CFG4_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00079014) +#define HWIO_GCC_IPA_CFG4_GDSCR_RMSK 0xffffff +#define HWIO_GCC_IPA_CFG4_GDSCR_ATTR 0x3 +#define HWIO_GCC_IPA_CFG4_GDSCR_IN \ + in_dword_masked(HWIO_GCC_IPA_CFG4_GDSCR_ADDR, HWIO_GCC_IPA_CFG4_GDSCR_RMSK) +#define HWIO_GCC_IPA_CFG4_GDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_IPA_CFG4_GDSCR_ADDR, m) +#define HWIO_GCC_IPA_CFG4_GDSCR_OUT(v) \ + out_dword(HWIO_GCC_IPA_CFG4_GDSCR_ADDR,v) +#define HWIO_GCC_IPA_CFG4_GDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_IPA_CFG4_GDSCR_ADDR,m,v,HWIO_GCC_IPA_CFG4_GDSCR_IN) +#define HWIO_GCC_IPA_CFG4_GDSCR_DLY_UNCLAMPIO_BMSK 0xf00000 +#define HWIO_GCC_IPA_CFG4_GDSCR_DLY_UNCLAMPIO_SHFT 0x14 +#define HWIO_GCC_IPA_CFG4_GDSCR_DLY_RESTOREFF_BMSK 0xf0000 +#define HWIO_GCC_IPA_CFG4_GDSCR_DLY_RESTOREFF_SHFT 0x10 +#define HWIO_GCC_IPA_CFG4_GDSCR_DLY_NORETAINFF_BMSK 0xf000 +#define HWIO_GCC_IPA_CFG4_GDSCR_DLY_NORETAINFF_SHFT 0xc +#define HWIO_GCC_IPA_CFG4_GDSCR_DLY_DEASSERTARES_BMSK 0xf00 +#define HWIO_GCC_IPA_CFG4_GDSCR_DLY_DEASSERTARES_SHFT 0x8 +#define HWIO_GCC_IPA_CFG4_GDSCR_DLY_CLAMPIO_BMSK 0xf0 +#define HWIO_GCC_IPA_CFG4_GDSCR_DLY_CLAMPIO_SHFT 0x4 +#define HWIO_GCC_IPA_CFG4_GDSCR_DLY_RETAINFF_BMSK 0xf +#define HWIO_GCC_IPA_CFG4_GDSCR_DLY_RETAINFF_SHFT 0x0 + +#define HWIO_GCC_IPA_2X_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00079018) +#define HWIO_GCC_IPA_2X_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00079018) +#define HWIO_GCC_IPA_2X_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00079018) +#define HWIO_GCC_IPA_2X_CBCR_RMSK 0x81d07005 +#define HWIO_GCC_IPA_2X_CBCR_ATTR 0x3 +#define HWIO_GCC_IPA_2X_CBCR_IN \ + in_dword_masked(HWIO_GCC_IPA_2X_CBCR_ADDR, HWIO_GCC_IPA_2X_CBCR_RMSK) +#define HWIO_GCC_IPA_2X_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_IPA_2X_CBCR_ADDR, m) +#define HWIO_GCC_IPA_2X_CBCR_OUT(v) \ + out_dword(HWIO_GCC_IPA_2X_CBCR_ADDR,v) +#define HWIO_GCC_IPA_2X_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_IPA_2X_CBCR_ADDR,m,v,HWIO_GCC_IPA_2X_CBCR_IN) +#define HWIO_GCC_IPA_2X_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_IPA_2X_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_IPA_2X_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_IPA_2X_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_IPA_2X_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_IPA_2X_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_IPA_2X_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_IPA_2X_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_IPA_2X_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_IPA_2X_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_IPA_2X_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_IPA_2X_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_IPA_2X_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_2X_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPA_2X_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_IPA_2X_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_IPA_2X_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_2X_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPA_2X_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_IPA_2X_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_IPA_2X_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_2X_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPA_2X_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_IPA_2X_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_IPA_2X_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_IPA_2X_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_IPA_2X_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_IPA_2X_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_IPA_2X_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_2X_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_IPA_2X_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007901c) +#define HWIO_GCC_IPA_2X_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007901c) +#define HWIO_GCC_IPA_2X_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007901c) +#define HWIO_GCC_IPA_2X_SREGR_RMSK 0xf1ffffe +#define HWIO_GCC_IPA_2X_SREGR_ATTR 0x3 +#define HWIO_GCC_IPA_2X_SREGR_IN \ + in_dword_masked(HWIO_GCC_IPA_2X_SREGR_ADDR, HWIO_GCC_IPA_2X_SREGR_RMSK) +#define HWIO_GCC_IPA_2X_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_IPA_2X_SREGR_ADDR, m) +#define HWIO_GCC_IPA_2X_SREGR_OUT(v) \ + out_dword(HWIO_GCC_IPA_2X_SREGR_ADDR,v) +#define HWIO_GCC_IPA_2X_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_IPA_2X_SREGR_ADDR,m,v,HWIO_GCC_IPA_2X_SREGR_IN) +#define HWIO_GCC_IPA_2X_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xf000000 +#define HWIO_GCC_IPA_2X_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_IPA_2X_SREGR_PWR_FSM_CLK_SEL_BMSK 0x100000 +#define HWIO_GCC_IPA_2X_SREGR_PWR_FSM_CLK_SEL_SHFT 0x14 +#define HWIO_GCC_IPA_2X_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xf0000 +#define HWIO_GCC_IPA_2X_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_IPA_2X_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_IPA_2X_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_IPA_2X_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_IPA_2X_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_IPA_2X_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_IPA_2X_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_IPA_2X_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_IPA_2X_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_IPA_2X_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_IPA_2X_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_IPA_2X_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_IPA_2X_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_IPA_2X_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_IPA_2X_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_IPA_2X_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_IPA_2X_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_IPA_2X_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_IPA_2X_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_IPA_2X_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_IPA_2X_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_IPA_2X_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_IPA_2X_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_IPA_2X_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_IPA_2X_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_IPA_2X_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_IPA_2X_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_IPA_2X_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_IPA_2X_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_IPA_2X_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_2X_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPA_2X_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_IPA_2X_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_IPA_2X_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_IPA_2X_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPA_2X_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_IPA_2X_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_IPA_2X_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_IPA_2X_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_IPA_2X_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_IPA_2X_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_IPA_2X_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_IPA_2X_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_IPA_2X_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_IPA_2X_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_IPA_2X_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_IPA_2X_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_IPA_2X_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_IPA_2X_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_IPA_2X_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_IPA_2X_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_IPA_2X_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_IPA_2X_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_IPA_2X_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_2X_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_IPA_2X_CFG_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00079020) +#define HWIO_GCC_IPA_2X_CFG_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00079020) +#define HWIO_GCC_IPA_2X_CFG_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00079020) +#define HWIO_GCC_IPA_2X_CFG_SREGR_RMSK 0xffffffff +#define HWIO_GCC_IPA_2X_CFG_SREGR_ATTR 0x3 +#define HWIO_GCC_IPA_2X_CFG_SREGR_IN \ + in_dword_masked(HWIO_GCC_IPA_2X_CFG_SREGR_ADDR, HWIO_GCC_IPA_2X_CFG_SREGR_RMSK) +#define HWIO_GCC_IPA_2X_CFG_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_IPA_2X_CFG_SREGR_ADDR, m) +#define HWIO_GCC_IPA_2X_CFG_SREGR_OUT(v) \ + out_dword(HWIO_GCC_IPA_2X_CFG_SREGR_ADDR,v) +#define HWIO_GCC_IPA_2X_CFG_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_IPA_2X_CFG_SREGR_ADDR,m,v,HWIO_GCC_IPA_2X_CFG_SREGR_IN) +#define HWIO_GCC_IPA_2X_CFG_SREGR_MEM_CORE_OFF_TIMER_BMSK 0xfc000000 +#define HWIO_GCC_IPA_2X_CFG_SREGR_MEM_CORE_OFF_TIMER_SHFT 0x1a +#define HWIO_GCC_IPA_2X_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_BMSK 0x2000000 +#define HWIO_GCC_IPA_2X_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_SHFT 0x19 +#define HWIO_GCC_IPA_2X_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_BMSK 0x1000000 +#define HWIO_GCC_IPA_2X_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_SHFT 0x18 +#define HWIO_GCC_IPA_2X_CFG_SREGR_MEM_PERIPH_ON_STATUS_BMSK 0x800000 +#define HWIO_GCC_IPA_2X_CFG_SREGR_MEM_PERIPH_ON_STATUS_SHFT 0x17 +#define HWIO_GCC_IPA_2X_CFG_SREGR_MEM_CORE_ON_STATUS_BMSK 0x400000 +#define HWIO_GCC_IPA_2X_CFG_SREGR_MEM_CORE_ON_STATUS_SHFT 0x16 +#define HWIO_GCC_IPA_2X_CFG_SREGR_MEM_CPH_TIMER_BMSK 0x3f0000 +#define HWIO_GCC_IPA_2X_CFG_SREGR_MEM_CPH_TIMER_SHFT 0x10 +#define HWIO_GCC_IPA_2X_CFG_SREGR_SLEEP_TIMER_BMSK 0xff00 +#define HWIO_GCC_IPA_2X_CFG_SREGR_SLEEP_TIMER_SHFT 0x8 +#define HWIO_GCC_IPA_2X_CFG_SREGR_WAKEUP_TIMER_BMSK 0xff +#define HWIO_GCC_IPA_2X_CFG_SREGR_WAKEUP_TIMER_SHFT 0x0 + +#define HWIO_GCC_IPA_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00079024) +#define HWIO_GCC_IPA_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00079024) +#define HWIO_GCC_IPA_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00079024) +#define HWIO_GCC_IPA_CBCR_RMSK 0x81d07005 +#define HWIO_GCC_IPA_CBCR_ATTR 0x3 +#define HWIO_GCC_IPA_CBCR_IN \ + in_dword_masked(HWIO_GCC_IPA_CBCR_ADDR, HWIO_GCC_IPA_CBCR_RMSK) +#define HWIO_GCC_IPA_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_IPA_CBCR_ADDR, m) +#define HWIO_GCC_IPA_CBCR_OUT(v) \ + out_dword(HWIO_GCC_IPA_CBCR_ADDR,v) +#define HWIO_GCC_IPA_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_IPA_CBCR_ADDR,m,v,HWIO_GCC_IPA_CBCR_IN) +#define HWIO_GCC_IPA_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_IPA_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_IPA_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_IPA_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_IPA_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_IPA_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_IPA_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_IPA_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_IPA_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_IPA_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_IPA_CBCR_FORCE_MEM_CORE_ON_BMSK 0x4000 +#define HWIO_GCC_IPA_CBCR_FORCE_MEM_CORE_ON_SHFT 0xe +#define HWIO_GCC_IPA_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPA_CBCR_FORCE_MEM_PERIPH_ON_BMSK 0x2000 +#define HWIO_GCC_IPA_CBCR_FORCE_MEM_PERIPH_ON_SHFT 0xd +#define HWIO_GCC_IPA_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPA_CBCR_FORCE_MEM_PERIPH_OFF_BMSK 0x1000 +#define HWIO_GCC_IPA_CBCR_FORCE_MEM_PERIPH_OFF_SHFT 0xc +#define HWIO_GCC_IPA_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPA_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_IPA_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_IPA_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_IPA_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_IPA_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_IPA_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_IPA_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_IPA_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00079028) +#define HWIO_GCC_IPA_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00079028) +#define HWIO_GCC_IPA_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00079028) +#define HWIO_GCC_IPA_SREGR_RMSK 0xf1ffffe +#define HWIO_GCC_IPA_SREGR_ATTR 0x3 +#define HWIO_GCC_IPA_SREGR_IN \ + in_dword_masked(HWIO_GCC_IPA_SREGR_ADDR, HWIO_GCC_IPA_SREGR_RMSK) +#define HWIO_GCC_IPA_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_IPA_SREGR_ADDR, m) +#define HWIO_GCC_IPA_SREGR_OUT(v) \ + out_dword(HWIO_GCC_IPA_SREGR_ADDR,v) +#define HWIO_GCC_IPA_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_IPA_SREGR_ADDR,m,v,HWIO_GCC_IPA_SREGR_IN) +#define HWIO_GCC_IPA_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK 0xf000000 +#define HWIO_GCC_IPA_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT 0x18 +#define HWIO_GCC_IPA_SREGR_PWR_FSM_CLK_SEL_BMSK 0x100000 +#define HWIO_GCC_IPA_SREGR_PWR_FSM_CLK_SEL_SHFT 0x14 +#define HWIO_GCC_IPA_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK 0xf0000 +#define HWIO_GCC_IPA_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT 0x10 +#define HWIO_GCC_IPA_SREGR_IGNORE_GDSC_PWR_DWN_CSR_BMSK 0x8000 +#define HWIO_GCC_IPA_SREGR_IGNORE_GDSC_PWR_DWN_CSR_SHFT 0xf +#define HWIO_GCC_IPA_SREGR_IGNORE_GDSC_PWR_DWN_CSR_NO_IGNORE_FVAL 0x0 +#define HWIO_GCC_IPA_SREGR_IGNORE_GDSC_PWR_DWN_CSR_IGNORE_FVAL 0x1 +#define HWIO_GCC_IPA_SREGR_PSCBC_SLP_STG_MODE_CSR_BMSK 0x4000 +#define HWIO_GCC_IPA_SREGR_PSCBC_SLP_STG_MODE_CSR_SHFT 0xe +#define HWIO_GCC_IPA_SREGR_PSCBC_SLP_STG_MODE_CSR_SREG_PSCBC_MODE_FVAL 0x0 +#define HWIO_GCC_IPA_SREGR_PSCBC_SLP_STG_MODE_CSR_PSCBC_SLP_STG_MODE_FVAL 0x1 +#define HWIO_GCC_IPA_SREGR_MEM_CPH_RST_SW_OVERRIDE_BMSK 0x2000 +#define HWIO_GCC_IPA_SREGR_MEM_CPH_RST_SW_OVERRIDE_SHFT 0xd +#define HWIO_GCC_IPA_SREGR_MEM_CPH_RST_SW_OVERRIDE_NO_OVERRIDE_FVAL 0x0 +#define HWIO_GCC_IPA_SREGR_MEM_CPH_RST_SW_OVERRIDE_OVERRIDE_FVAL 0x1 +#define HWIO_GCC_IPA_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK 0x1000 +#define HWIO_GCC_IPA_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT 0xc +#define HWIO_GCC_IPA_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL 0x0 +#define HWIO_GCC_IPA_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL 0x1 +#define HWIO_GCC_IPA_SREGR_MEM_CORE_ON_ACK_BMSK 0x800 +#define HWIO_GCC_IPA_SREGR_MEM_CORE_ON_ACK_SHFT 0xb +#define HWIO_GCC_IPA_SREGR_MEM_PERIPH_ON_ACK_BMSK 0x400 +#define HWIO_GCC_IPA_SREGR_MEM_PERIPH_ON_ACK_SHFT 0xa +#define HWIO_GCC_IPA_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK 0x300 +#define HWIO_GCC_IPA_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT 0x8 +#define HWIO_GCC_IPA_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL 0x0 +#define HWIO_GCC_IPA_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL 0x1 +#define HWIO_GCC_IPA_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL 0x2 +#define HWIO_GCC_IPA_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL 0x3 +#define HWIO_GCC_IPA_SREGR_MEM_CPH_ENABLE_BMSK 0x80 +#define HWIO_GCC_IPA_SREGR_MEM_CPH_ENABLE_SHFT 0x7 +#define HWIO_GCC_IPA_SREGR_MEM_CPH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_SREGR_MEM_CPH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPA_SREGR_FORCE_CLK_ON_BMSK 0x40 +#define HWIO_GCC_IPA_SREGR_FORCE_CLK_ON_SHFT 0x6 +#define HWIO_GCC_IPA_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL 0x0 +#define HWIO_GCC_IPA_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPA_SREGR_SW_RST_SEL_SLP_STG_BMSK 0x20 +#define HWIO_GCC_IPA_SREGR_SW_RST_SEL_SLP_STG_SHFT 0x5 +#define HWIO_GCC_IPA_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL 0x0 +#define HWIO_GCC_IPA_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_IPA_SREGR_SW_RST_SLP_STG_BMSK 0x10 +#define HWIO_GCC_IPA_SREGR_SW_RST_SLP_STG_SHFT 0x4 +#define HWIO_GCC_IPA_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL 0x0 +#define HWIO_GCC_IPA_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL 0x1 +#define HWIO_GCC_IPA_SREGR_SW_CTRL_PWR_DOWN_BMSK 0x8 +#define HWIO_GCC_IPA_SREGR_SW_CTRL_PWR_DOWN_SHFT 0x3 +#define HWIO_GCC_IPA_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL 0x0 +#define HWIO_GCC_IPA_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL 0x1 +#define HWIO_GCC_IPA_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK 0x4 +#define HWIO_GCC_IPA_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT 0x2 +#define HWIO_GCC_IPA_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL 0x0 +#define HWIO_GCC_IPA_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL 0x1 +#define HWIO_GCC_IPA_SREGR_SW_CLK_EN_SLP_STG_BMSK 0x2 +#define HWIO_GCC_IPA_SREGR_SW_CLK_EN_SLP_STG_SHFT 0x1 +#define HWIO_GCC_IPA_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL 0x1 + +#define HWIO_GCC_IPA_CFG_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007902c) +#define HWIO_GCC_IPA_CFG_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007902c) +#define HWIO_GCC_IPA_CFG_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007902c) +#define HWIO_GCC_IPA_CFG_SREGR_RMSK 0xffffffff +#define HWIO_GCC_IPA_CFG_SREGR_ATTR 0x3 +#define HWIO_GCC_IPA_CFG_SREGR_IN \ + in_dword_masked(HWIO_GCC_IPA_CFG_SREGR_ADDR, HWIO_GCC_IPA_CFG_SREGR_RMSK) +#define HWIO_GCC_IPA_CFG_SREGR_INM(m) \ + in_dword_masked(HWIO_GCC_IPA_CFG_SREGR_ADDR, m) +#define HWIO_GCC_IPA_CFG_SREGR_OUT(v) \ + out_dword(HWIO_GCC_IPA_CFG_SREGR_ADDR,v) +#define HWIO_GCC_IPA_CFG_SREGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_IPA_CFG_SREGR_ADDR,m,v,HWIO_GCC_IPA_CFG_SREGR_IN) +#define HWIO_GCC_IPA_CFG_SREGR_MEM_CORE_OFF_TIMER_BMSK 0xfc000000 +#define HWIO_GCC_IPA_CFG_SREGR_MEM_CORE_OFF_TIMER_SHFT 0x1a +#define HWIO_GCC_IPA_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_BMSK 0x2000000 +#define HWIO_GCC_IPA_CFG_SREGR_MEM_PERIPH_ON_ACK_STATUS_SHFT 0x19 +#define HWIO_GCC_IPA_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_BMSK 0x1000000 +#define HWIO_GCC_IPA_CFG_SREGR_MEM_CORE_ON_ACK_STATUS_SHFT 0x18 +#define HWIO_GCC_IPA_CFG_SREGR_MEM_PERIPH_ON_STATUS_BMSK 0x800000 +#define HWIO_GCC_IPA_CFG_SREGR_MEM_PERIPH_ON_STATUS_SHFT 0x17 +#define HWIO_GCC_IPA_CFG_SREGR_MEM_CORE_ON_STATUS_BMSK 0x400000 +#define HWIO_GCC_IPA_CFG_SREGR_MEM_CORE_ON_STATUS_SHFT 0x16 +#define HWIO_GCC_IPA_CFG_SREGR_MEM_CPH_TIMER_BMSK 0x3f0000 +#define HWIO_GCC_IPA_CFG_SREGR_MEM_CPH_TIMER_SHFT 0x10 +#define HWIO_GCC_IPA_CFG_SREGR_SLEEP_TIMER_BMSK 0xff00 +#define HWIO_GCC_IPA_CFG_SREGR_SLEEP_TIMER_SHFT 0x8 +#define HWIO_GCC_IPA_CFG_SREGR_WAKEUP_TIMER_BMSK 0xff +#define HWIO_GCC_IPA_CFG_SREGR_WAKEUP_TIMER_SHFT 0x0 + +#define HWIO_GCC_IPA_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00079030) +#define HWIO_GCC_IPA_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00079030) +#define HWIO_GCC_IPA_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00079030) +#define HWIO_GCC_IPA_AHB_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_IPA_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_IPA_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_IPA_AHB_CBCR_ADDR, HWIO_GCC_IPA_AHB_CBCR_RMSK) +#define HWIO_GCC_IPA_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_IPA_AHB_CBCR_ADDR, m) +#define HWIO_GCC_IPA_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_IPA_AHB_CBCR_ADDR,v) +#define HWIO_GCC_IPA_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_IPA_AHB_CBCR_ADDR,m,v,HWIO_GCC_IPA_AHB_CBCR_IN) +#define HWIO_GCC_IPA_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_IPA_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_IPA_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_IPA_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_IPA_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_IPA_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_IPA_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_IPA_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_IPA_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_IPA_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_IPA_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_IPA_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_IPA_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_IPA_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_IPA_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_IPA_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_IPA_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_IPA_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_IPA_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPA_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_IPA_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_IPA_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_IPA_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00079034) +#define HWIO_GCC_IPA_XO_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00079034) +#define HWIO_GCC_IPA_XO_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00079034) +#define HWIO_GCC_IPA_XO_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_IPA_XO_CBCR_ATTR 0x3 +#define HWIO_GCC_IPA_XO_CBCR_IN \ + in_dword_masked(HWIO_GCC_IPA_XO_CBCR_ADDR, HWIO_GCC_IPA_XO_CBCR_RMSK) +#define HWIO_GCC_IPA_XO_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_IPA_XO_CBCR_ADDR, m) +#define HWIO_GCC_IPA_XO_CBCR_OUT(v) \ + out_dword(HWIO_GCC_IPA_XO_CBCR_ADDR,v) +#define HWIO_GCC_IPA_XO_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_IPA_XO_CBCR_ADDR,m,v,HWIO_GCC_IPA_XO_CBCR_IN) +#define HWIO_GCC_IPA_XO_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_IPA_XO_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_IPA_XO_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_IPA_XO_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_IPA_XO_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_IPA_XO_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_IPA_XO_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_IPA_XO_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_IPA_XO_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_IPA_XO_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_IPA_XO_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_IPA_XO_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_IPA_XO_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_IPA_XO_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_IPA_XO_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_XO_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_IPA_APB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00079038) +#define HWIO_GCC_IPA_APB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00079038) +#define HWIO_GCC_IPA_APB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00079038) +#define HWIO_GCC_IPA_APB_CBCR_RMSK 0x81c0000f +#define HWIO_GCC_IPA_APB_CBCR_ATTR 0x3 +#define HWIO_GCC_IPA_APB_CBCR_IN \ + in_dword_masked(HWIO_GCC_IPA_APB_CBCR_ADDR, HWIO_GCC_IPA_APB_CBCR_RMSK) +#define HWIO_GCC_IPA_APB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_IPA_APB_CBCR_ADDR, m) +#define HWIO_GCC_IPA_APB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_IPA_APB_CBCR_ADDR,v) +#define HWIO_GCC_IPA_APB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_IPA_APB_CBCR_ADDR,m,v,HWIO_GCC_IPA_APB_CBCR_IN) +#define HWIO_GCC_IPA_APB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_IPA_APB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_IPA_APB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_IPA_APB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_IPA_APB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_IPA_APB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_IPA_APB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_IPA_APB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_IPA_APB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_IPA_APB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_IPA_APB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_IPA_APB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_IPA_APB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_IPA_APB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_IPA_APB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_IPA_APB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_IPA_APB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_APB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPA_APB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_IPA_APB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_IPA_APB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_APB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_IPA_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007903c) +#define HWIO_GCC_IPA_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007903c) +#define HWIO_GCC_IPA_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007903c) +#define HWIO_GCC_IPA_AT_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_IPA_AT_CBCR_ATTR 0x3 +#define HWIO_GCC_IPA_AT_CBCR_IN \ + in_dword_masked(HWIO_GCC_IPA_AT_CBCR_ADDR, HWIO_GCC_IPA_AT_CBCR_RMSK) +#define HWIO_GCC_IPA_AT_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_IPA_AT_CBCR_ADDR, m) +#define HWIO_GCC_IPA_AT_CBCR_OUT(v) \ + out_dword(HWIO_GCC_IPA_AT_CBCR_ADDR,v) +#define HWIO_GCC_IPA_AT_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_IPA_AT_CBCR_ADDR,m,v,HWIO_GCC_IPA_AT_CBCR_IN) +#define HWIO_GCC_IPA_AT_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_IPA_AT_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_IPA_AT_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_IPA_AT_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_IPA_AT_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_IPA_AT_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_IPA_AT_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_IPA_AT_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_IPA_AT_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_IPA_AT_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_IPA_AT_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_IPA_AT_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_IPA_AT_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_IPA_AT_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_IPA_AT_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_IPA_AT_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_IPA_AT_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_IPA_AT_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_IPA_AT_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_AT_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPA_AT_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_IPA_AT_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_IPA_AT_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_AT_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_IPA_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00079054) +#define HWIO_GCC_RPMH_IPA_CMD_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00079054) +#define HWIO_GCC_RPMH_IPA_CMD_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00079054) +#define HWIO_GCC_RPMH_IPA_CMD_DFSR_RMSK 0xffff +#define HWIO_GCC_RPMH_IPA_CMD_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_CMD_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_CMD_DFSR_ADDR, HWIO_GCC_RPMH_IPA_CMD_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_CMD_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_CMD_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_CMD_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_CMD_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_CMD_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_CMD_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_CMD_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_CMD_DFSR_RCG_SW_CTRL_BMSK 0x8000 +#define HWIO_GCC_RPMH_IPA_CMD_DFSR_RCG_SW_CTRL_SHFT 0xf +#define HWIO_GCC_RPMH_IPA_CMD_DFSR_SW_PERF_STATE_BMSK 0x7800 +#define HWIO_GCC_RPMH_IPA_CMD_DFSR_SW_PERF_STATE_SHFT 0xb +#define HWIO_GCC_RPMH_IPA_CMD_DFSR_SW_OVERRIDE_BMSK 0x400 +#define HWIO_GCC_RPMH_IPA_CMD_DFSR_SW_OVERRIDE_SHFT 0xa +#define HWIO_GCC_RPMH_IPA_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK 0x200 +#define HWIO_GCC_RPMH_IPA_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT 0x9 +#define HWIO_GCC_RPMH_IPA_CMD_DFSR_DFS_FSM_STATE_BMSK 0x1c0 +#define HWIO_GCC_RPMH_IPA_CMD_DFSR_DFS_FSM_STATE_SHFT 0x6 +#define HWIO_GCC_RPMH_IPA_CMD_DFSR_HW_CLK_CONTROL_BMSK 0x20 +#define HWIO_GCC_RPMH_IPA_CMD_DFSR_HW_CLK_CONTROL_SHFT 0x5 +#define HWIO_GCC_RPMH_IPA_CMD_DFSR_CURR_PERF_STATE_BMSK 0x1e +#define HWIO_GCC_RPMH_IPA_CMD_DFSR_CURR_PERF_STATE_SHFT 0x1 +#define HWIO_GCC_RPMH_IPA_CMD_DFSR_DFS_EN_BMSK 0x1 +#define HWIO_GCC_RPMH_IPA_CMD_DFSR_DFS_EN_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_CMD_DFSR_DFS_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_CMD_DFSR_DFS_EN_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007905c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007905c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007905c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00079060) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00079060) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00079060) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00079064) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00079064) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00079064) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00079068) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00079068) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00079068) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007906c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007906c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007906c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00079070) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00079070) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00079070) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00079074) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00079074) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00079074) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00079078) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00079078) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00079078) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007907c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007907c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007907c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00079080) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00079080) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00079080) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00079084) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00079084) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00079084) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00079088) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00079088) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00079088) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007908c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007908c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007908c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00079090) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00079090) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00079090) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00079094) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00079094) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00079094) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00079098) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00079098) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00079098) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_ADDR, HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_RMSK) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_IN) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_IPA_2X_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00079040) +#define HWIO_GCC_IPA_2X_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00079040) +#define HWIO_GCC_IPA_2X_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00079040) +#define HWIO_GCC_IPA_2X_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_IPA_2X_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_IPA_2X_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_IPA_2X_CMD_RCGR_ADDR, HWIO_GCC_IPA_2X_CMD_RCGR_RMSK) +#define HWIO_GCC_IPA_2X_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_IPA_2X_CMD_RCGR_ADDR, m) +#define HWIO_GCC_IPA_2X_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_IPA_2X_CMD_RCGR_ADDR,v) +#define HWIO_GCC_IPA_2X_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_IPA_2X_CMD_RCGR_ADDR,m,v,HWIO_GCC_IPA_2X_CMD_RCGR_IN) +#define HWIO_GCC_IPA_2X_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_IPA_2X_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_IPA_2X_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_IPA_2X_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_IPA_2X_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_IPA_2X_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_IPA_2X_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_2X_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPA_2X_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_IPA_2X_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_IPA_2X_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_2X_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_IPA_2X_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00079044) +#define HWIO_GCC_IPA_2X_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00079044) +#define HWIO_GCC_IPA_2X_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00079044) +#define HWIO_GCC_IPA_2X_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_IPA_2X_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_IPA_2X_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_IPA_2X_CFG_RCGR_ADDR, HWIO_GCC_IPA_2X_CFG_RCGR_RMSK) +#define HWIO_GCC_IPA_2X_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_IPA_2X_CFG_RCGR_ADDR, m) +#define HWIO_GCC_IPA_2X_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_IPA_2X_CFG_RCGR_ADDR,v) +#define HWIO_GCC_IPA_2X_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_IPA_2X_CFG_RCGR_ADDR,m,v,HWIO_GCC_IPA_2X_CFG_RCGR_IN) +#define HWIO_GCC_IPA_2X_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_IPA_2X_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_IPA_2X_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_2X_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPA_2X_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_IPA_2X_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_IPA_2X_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_IPA_2X_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_IPA_2X_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007916c) +#define HWIO_GCC_IPA_2X_DCD_CDIV_DCDR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007916c) +#define HWIO_GCC_IPA_2X_DCD_CDIV_DCDR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007916c) +#define HWIO_GCC_IPA_2X_DCD_CDIV_DCDR_RMSK 0x1 +#define HWIO_GCC_IPA_2X_DCD_CDIV_DCDR_ATTR 0x3 +#define HWIO_GCC_IPA_2X_DCD_CDIV_DCDR_IN \ + in_dword_masked(HWIO_GCC_IPA_2X_DCD_CDIV_DCDR_ADDR, HWIO_GCC_IPA_2X_DCD_CDIV_DCDR_RMSK) +#define HWIO_GCC_IPA_2X_DCD_CDIV_DCDR_INM(m) \ + in_dword_masked(HWIO_GCC_IPA_2X_DCD_CDIV_DCDR_ADDR, m) +#define HWIO_GCC_IPA_2X_DCD_CDIV_DCDR_OUT(v) \ + out_dword(HWIO_GCC_IPA_2X_DCD_CDIV_DCDR_ADDR,v) +#define HWIO_GCC_IPA_2X_DCD_CDIV_DCDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_IPA_2X_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_IPA_2X_DCD_CDIV_DCDR_IN) +#define HWIO_GCC_IPA_2X_DCD_CDIV_DCDR_DCD_ENABLE_BMSK 0x1 +#define HWIO_GCC_IPA_2X_DCD_CDIV_DCDR_DCD_ENABLE_SHFT 0x0 +#define HWIO_GCC_IPA_2X_DCD_CDIV_DCDR_DCD_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_2X_DCD_CDIV_DCDR_DCD_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_IPA_DIV_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00079170) +#define HWIO_GCC_IPA_DIV_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00079170) +#define HWIO_GCC_IPA_DIV_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00079170) +#define HWIO_GCC_IPA_DIV_CDIVR_RMSK 0xf +#define HWIO_GCC_IPA_DIV_CDIVR_ATTR 0x3 +#define HWIO_GCC_IPA_DIV_CDIVR_IN \ + in_dword_masked(HWIO_GCC_IPA_DIV_CDIVR_ADDR, HWIO_GCC_IPA_DIV_CDIVR_RMSK) +#define HWIO_GCC_IPA_DIV_CDIVR_INM(m) \ + in_dword_masked(HWIO_GCC_IPA_DIV_CDIVR_ADDR, m) +#define HWIO_GCC_IPA_DIV_CDIVR_OUT(v) \ + out_dword(HWIO_GCC_IPA_DIV_CDIVR_ADDR,v) +#define HWIO_GCC_IPA_DIV_CDIVR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_IPA_DIV_CDIVR_ADDR,m,v,HWIO_GCC_IPA_DIV_CDIVR_IN) +#define HWIO_GCC_IPA_DIV_CDIVR_CLK_DIV_BMSK 0xf +#define HWIO_GCC_IPA_DIV_CDIVR_CLK_DIV_SHFT 0x0 + +#define HWIO_GCC_MSS_CFG_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a000) +#define HWIO_GCC_MSS_CFG_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007a000) +#define HWIO_GCC_MSS_CFG_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007a000) +#define HWIO_GCC_MSS_CFG_AHB_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_MSS_CFG_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_MSS_CFG_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_MSS_CFG_AHB_CBCR_ADDR, HWIO_GCC_MSS_CFG_AHB_CBCR_RMSK) +#define HWIO_GCC_MSS_CFG_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_CFG_AHB_CBCR_ADDR, m) +#define HWIO_GCC_MSS_CFG_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_MSS_CFG_AHB_CBCR_ADDR,v) +#define HWIO_GCC_MSS_CFG_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_CFG_AHB_CBCR_ADDR,m,v,HWIO_GCC_MSS_CFG_AHB_CBCR_IN) +#define HWIO_GCC_MSS_CFG_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_MSS_CFG_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_MSS_CFG_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_MSS_CFG_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_MSS_CFG_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_MSS_CFG_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_MSS_CFG_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_MSS_CFG_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_MSS_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_MSS_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_MSS_CFG_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_MSS_CFG_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_MSS_CFG_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_MSS_CFG_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_MSS_CFG_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_MSS_CFG_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_MSS_CFG_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_MSS_CFG_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_MSS_CFG_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_CFG_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_CFG_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_MSS_CFG_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_MSS_CFG_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_CFG_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QMIP_MSS_OFFLINE_CFG_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a004) +#define HWIO_GCC_QMIP_MSS_OFFLINE_CFG_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007a004) +#define HWIO_GCC_QMIP_MSS_OFFLINE_CFG_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007a004) +#define HWIO_GCC_QMIP_MSS_OFFLINE_CFG_AHB_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_QMIP_MSS_OFFLINE_CFG_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_QMIP_MSS_OFFLINE_CFG_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_QMIP_MSS_OFFLINE_CFG_AHB_CBCR_ADDR, HWIO_GCC_QMIP_MSS_OFFLINE_CFG_AHB_CBCR_RMSK) +#define HWIO_GCC_QMIP_MSS_OFFLINE_CFG_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QMIP_MSS_OFFLINE_CFG_AHB_CBCR_ADDR, m) +#define HWIO_GCC_QMIP_MSS_OFFLINE_CFG_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QMIP_MSS_OFFLINE_CFG_AHB_CBCR_ADDR,v) +#define HWIO_GCC_QMIP_MSS_OFFLINE_CFG_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QMIP_MSS_OFFLINE_CFG_AHB_CBCR_ADDR,m,v,HWIO_GCC_QMIP_MSS_OFFLINE_CFG_AHB_CBCR_IN) +#define HWIO_GCC_QMIP_MSS_OFFLINE_CFG_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QMIP_MSS_OFFLINE_CFG_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QMIP_MSS_OFFLINE_CFG_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QMIP_MSS_OFFLINE_CFG_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QMIP_MSS_OFFLINE_CFG_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QMIP_MSS_OFFLINE_CFG_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QMIP_MSS_OFFLINE_CFG_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QMIP_MSS_OFFLINE_CFG_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QMIP_MSS_OFFLINE_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_QMIP_MSS_OFFLINE_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_QMIP_MSS_OFFLINE_CFG_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_QMIP_MSS_OFFLINE_CFG_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_QMIP_MSS_OFFLINE_CFG_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QMIP_MSS_OFFLINE_CFG_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QMIP_MSS_OFFLINE_CFG_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QMIP_MSS_OFFLINE_CFG_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_QMIP_MSS_OFFLINE_CFG_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_QMIP_MSS_OFFLINE_CFG_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_QMIP_MSS_OFFLINE_CFG_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QMIP_MSS_OFFLINE_CFG_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QMIP_MSS_OFFLINE_CFG_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_QMIP_MSS_OFFLINE_CFG_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_QMIP_MSS_OFFLINE_CFG_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QMIP_MSS_OFFLINE_CFG_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QMIP_MSS_Q6_CFG_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a008) +#define HWIO_GCC_QMIP_MSS_Q6_CFG_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007a008) +#define HWIO_GCC_QMIP_MSS_Q6_CFG_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007a008) +#define HWIO_GCC_QMIP_MSS_Q6_CFG_AHB_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_QMIP_MSS_Q6_CFG_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_QMIP_MSS_Q6_CFG_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_QMIP_MSS_Q6_CFG_AHB_CBCR_ADDR, HWIO_GCC_QMIP_MSS_Q6_CFG_AHB_CBCR_RMSK) +#define HWIO_GCC_QMIP_MSS_Q6_CFG_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QMIP_MSS_Q6_CFG_AHB_CBCR_ADDR, m) +#define HWIO_GCC_QMIP_MSS_Q6_CFG_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QMIP_MSS_Q6_CFG_AHB_CBCR_ADDR,v) +#define HWIO_GCC_QMIP_MSS_Q6_CFG_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QMIP_MSS_Q6_CFG_AHB_CBCR_ADDR,m,v,HWIO_GCC_QMIP_MSS_Q6_CFG_AHB_CBCR_IN) +#define HWIO_GCC_QMIP_MSS_Q6_CFG_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QMIP_MSS_Q6_CFG_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QMIP_MSS_Q6_CFG_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QMIP_MSS_Q6_CFG_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QMIP_MSS_Q6_CFG_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QMIP_MSS_Q6_CFG_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QMIP_MSS_Q6_CFG_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QMIP_MSS_Q6_CFG_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QMIP_MSS_Q6_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_QMIP_MSS_Q6_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_QMIP_MSS_Q6_CFG_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_QMIP_MSS_Q6_CFG_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_QMIP_MSS_Q6_CFG_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QMIP_MSS_Q6_CFG_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QMIP_MSS_Q6_CFG_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QMIP_MSS_Q6_CFG_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_QMIP_MSS_Q6_CFG_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_QMIP_MSS_Q6_CFG_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_QMIP_MSS_Q6_CFG_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QMIP_MSS_Q6_CFG_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QMIP_MSS_Q6_CFG_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_QMIP_MSS_Q6_CFG_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_QMIP_MSS_Q6_CFG_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QMIP_MSS_Q6_CFG_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a00c) +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007a00c) +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007a00c) +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_RMSK 0x81f0000f +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_ATTR 0x3 +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_IN \ + in_dword_masked(HWIO_GCC_MSS_OFFLINE_AXI_CBCR_ADDR, HWIO_GCC_MSS_OFFLINE_AXI_CBCR_RMSK) +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_OFFLINE_AXI_CBCR_ADDR, m) +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_OUT(v) \ + out_dword(HWIO_GCC_MSS_OFFLINE_AXI_CBCR_ADDR,v) +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_OFFLINE_AXI_CBCR_ADDR,m,v,HWIO_GCC_MSS_OFFLINE_AXI_CBCR_IN) +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_IGNORE_PMU_CLK_DIS_BMSK 0x200000 +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_IGNORE_PMU_CLK_DIS_SHFT 0x15 +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_OFFLINE_AXI_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_AXIS2_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003d000) +#define HWIO_GCC_MSS_AXIS2_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003d000) +#define HWIO_GCC_MSS_AXIS2_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003d000) +#define HWIO_GCC_MSS_AXIS2_CBCR_RMSK 0x81d00005 +#define HWIO_GCC_MSS_AXIS2_CBCR_ATTR 0x3 +#define HWIO_GCC_MSS_AXIS2_CBCR_IN \ + in_dword_masked(HWIO_GCC_MSS_AXIS2_CBCR_ADDR, HWIO_GCC_MSS_AXIS2_CBCR_RMSK) +#define HWIO_GCC_MSS_AXIS2_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_AXIS2_CBCR_ADDR, m) +#define HWIO_GCC_MSS_AXIS2_CBCR_OUT(v) \ + out_dword(HWIO_GCC_MSS_AXIS2_CBCR_ADDR,v) +#define HWIO_GCC_MSS_AXIS2_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_AXIS2_CBCR_ADDR,m,v,HWIO_GCC_MSS_AXIS2_CBCR_IN) +#define HWIO_GCC_MSS_AXIS2_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_MSS_AXIS2_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_MSS_AXIS2_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_MSS_AXIS2_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_MSS_AXIS2_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_MSS_AXIS2_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_MSS_AXIS2_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_MSS_AXIS2_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_MSS_AXIS2_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_MSS_AXIS2_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_MSS_AXIS2_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_MSS_AXIS2_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_MSS_AXIS2_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_MSS_AXIS2_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_MSS_AXIS2_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_MSS_AXIS2_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_MSS_AXIS2_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_AXIS2_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_TRIG_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a010) +#define HWIO_GCC_MSS_TRIG_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007a010) +#define HWIO_GCC_MSS_TRIG_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007a010) +#define HWIO_GCC_MSS_TRIG_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_MSS_TRIG_CBCR_ATTR 0x3 +#define HWIO_GCC_MSS_TRIG_CBCR_IN \ + in_dword_masked(HWIO_GCC_MSS_TRIG_CBCR_ADDR, HWIO_GCC_MSS_TRIG_CBCR_RMSK) +#define HWIO_GCC_MSS_TRIG_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_TRIG_CBCR_ADDR, m) +#define HWIO_GCC_MSS_TRIG_CBCR_OUT(v) \ + out_dword(HWIO_GCC_MSS_TRIG_CBCR_ADDR,v) +#define HWIO_GCC_MSS_TRIG_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_TRIG_CBCR_ADDR,m,v,HWIO_GCC_MSS_TRIG_CBCR_IN) +#define HWIO_GCC_MSS_TRIG_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_MSS_TRIG_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_MSS_TRIG_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_MSS_TRIG_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_MSS_TRIG_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_MSS_TRIG_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_MSS_TRIG_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_MSS_TRIG_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_MSS_TRIG_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_MSS_TRIG_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_MSS_TRIG_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_MSS_TRIG_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_MSS_TRIG_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_MSS_TRIG_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_MSS_TRIG_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_MSS_TRIG_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_MSS_TRIG_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_MSS_TRIG_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_MSS_TRIG_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_TRIG_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_TRIG_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_MSS_TRIG_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_MSS_TRIG_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_TRIG_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a014) +#define HWIO_GCC_MSS_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007a014) +#define HWIO_GCC_MSS_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007a014) +#define HWIO_GCC_MSS_AT_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_MSS_AT_CBCR_ATTR 0x3 +#define HWIO_GCC_MSS_AT_CBCR_IN \ + in_dword_masked(HWIO_GCC_MSS_AT_CBCR_ADDR, HWIO_GCC_MSS_AT_CBCR_RMSK) +#define HWIO_GCC_MSS_AT_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_AT_CBCR_ADDR, m) +#define HWIO_GCC_MSS_AT_CBCR_OUT(v) \ + out_dword(HWIO_GCC_MSS_AT_CBCR_ADDR,v) +#define HWIO_GCC_MSS_AT_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_AT_CBCR_ADDR,m,v,HWIO_GCC_MSS_AT_CBCR_IN) +#define HWIO_GCC_MSS_AT_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_MSS_AT_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_MSS_AT_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_MSS_AT_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_MSS_AT_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_MSS_AT_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_MSS_AT_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_MSS_AT_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_MSS_AT_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_MSS_AT_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_MSS_AT_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_MSS_AT_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_MSS_AT_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_MSS_AT_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_MSS_AT_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_MSS_AT_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_MSS_AT_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_MSS_AT_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_MSS_AT_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_AT_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_AT_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_MSS_AT_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_MSS_AT_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_AT_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a018) +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007a018) +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007a018) +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_ATTR 0x3 +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_IN \ + in_dword_masked(HWIO_GCC_MSS_SNOC_AXI_CBCR_ADDR, HWIO_GCC_MSS_SNOC_AXI_CBCR_RMSK) +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_SNOC_AXI_CBCR_ADDR, m) +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_OUT(v) \ + out_dword(HWIO_GCC_MSS_SNOC_AXI_CBCR_ADDR,v) +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_SNOC_AXI_CBCR_ADDR,m,v,HWIO_GCC_MSS_SNOC_AXI_CBCR_IN) +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a01c) +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007a01c) +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007a01c) +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_RMSK 0x81f0000f +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_ATTR 0x3 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_IN \ + in_dword_masked(HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_ADDR, HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_RMSK) +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_ADDR, m) +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_OUT(v) \ + out_dword(HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_ADDR,v) +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_ADDR,m,v,HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_IN) +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_IGNORE_PMU_CLK_DIS_BMSK 0x200000 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_IGNORE_PMU_CLK_DIS_SHFT 0x15 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_PLL0_MAIN_DIV_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a020) +#define HWIO_GCC_MSS_PLL0_MAIN_DIV_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007a020) +#define HWIO_GCC_MSS_PLL0_MAIN_DIV_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007a020) +#define HWIO_GCC_MSS_PLL0_MAIN_DIV_CDIVR_RMSK 0xf +#define HWIO_GCC_MSS_PLL0_MAIN_DIV_CDIVR_ATTR 0x3 +#define HWIO_GCC_MSS_PLL0_MAIN_DIV_CDIVR_IN \ + in_dword_masked(HWIO_GCC_MSS_PLL0_MAIN_DIV_CDIVR_ADDR, HWIO_GCC_MSS_PLL0_MAIN_DIV_CDIVR_RMSK) +#define HWIO_GCC_MSS_PLL0_MAIN_DIV_CDIVR_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_PLL0_MAIN_DIV_CDIVR_ADDR, m) +#define HWIO_GCC_MSS_PLL0_MAIN_DIV_CDIVR_OUT(v) \ + out_dword(HWIO_GCC_MSS_PLL0_MAIN_DIV_CDIVR_ADDR,v) +#define HWIO_GCC_MSS_PLL0_MAIN_DIV_CDIVR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_PLL0_MAIN_DIV_CDIVR_ADDR,m,v,HWIO_GCC_MSS_PLL0_MAIN_DIV_CDIVR_IN) +#define HWIO_GCC_MSS_PLL0_MAIN_DIV_CDIVR_CLK_DIV_BMSK 0xf +#define HWIO_GCC_MSS_PLL0_MAIN_DIV_CDIVR_CLK_DIV_SHFT 0x0 + +#define HWIO_GCC_MSS_OFFLINE_AXI_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a024) +#define HWIO_GCC_MSS_OFFLINE_AXI_DCD_CDIV_DCDR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007a024) +#define HWIO_GCC_MSS_OFFLINE_AXI_DCD_CDIV_DCDR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007a024) +#define HWIO_GCC_MSS_OFFLINE_AXI_DCD_CDIV_DCDR_RMSK 0x1 +#define HWIO_GCC_MSS_OFFLINE_AXI_DCD_CDIV_DCDR_ATTR 0x3 +#define HWIO_GCC_MSS_OFFLINE_AXI_DCD_CDIV_DCDR_IN \ + in_dword_masked(HWIO_GCC_MSS_OFFLINE_AXI_DCD_CDIV_DCDR_ADDR, HWIO_GCC_MSS_OFFLINE_AXI_DCD_CDIV_DCDR_RMSK) +#define HWIO_GCC_MSS_OFFLINE_AXI_DCD_CDIV_DCDR_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_OFFLINE_AXI_DCD_CDIV_DCDR_ADDR, m) +#define HWIO_GCC_MSS_OFFLINE_AXI_DCD_CDIV_DCDR_OUT(v) \ + out_dword(HWIO_GCC_MSS_OFFLINE_AXI_DCD_CDIV_DCDR_ADDR,v) +#define HWIO_GCC_MSS_OFFLINE_AXI_DCD_CDIV_DCDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_OFFLINE_AXI_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_MSS_OFFLINE_AXI_DCD_CDIV_DCDR_IN) +#define HWIO_GCC_MSS_OFFLINE_AXI_DCD_CDIV_DCDR_DCD_ENABLE_BMSK 0x1 +#define HWIO_GCC_MSS_OFFLINE_AXI_DCD_CDIV_DCDR_DCD_ENABLE_SHFT 0x0 +#define HWIO_GCC_MSS_OFFLINE_AXI_DCD_CDIV_DCDR_DCD_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_OFFLINE_AXI_DCD_CDIV_DCDR_DCD_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a044) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007a044) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007a044) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a048) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007a048) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007a048) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a04c) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007a04c) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007a04c) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a050) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007a050) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007a050) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a054) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007a054) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007a054) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a058) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007a058) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007a058) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a05c) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007a05c) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007a05c) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a060) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007a060) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007a060) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a064) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007a064) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007a064) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a068) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007a068) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007a068) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a06c) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007a06c) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007a06c) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a070) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007a070) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007a070) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a074) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007a074) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007a074) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a078) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007a078) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007a078) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a07c) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007a07c) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007a07c) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a080) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007a080) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007a080) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a028) +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007a028) +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007a028) +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_MSS_Q6_MEMNOC_AXI_CMD_RCGR_ADDR, HWIO_GCC_MSS_Q6_MEMNOC_AXI_CMD_RCGR_RMSK) +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_Q6_MEMNOC_AXI_CMD_RCGR_ADDR, m) +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_MSS_Q6_MEMNOC_AXI_CMD_RCGR_ADDR,v) +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_Q6_MEMNOC_AXI_CMD_RCGR_ADDR,m,v,HWIO_GCC_MSS_Q6_MEMNOC_AXI_CMD_RCGR_IN) +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a02c) +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007a02c) +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007a02c) +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_ADDR, HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_RMSK) +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_ADDR, m) +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_ADDR,v) +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_ADDR,m,v,HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_IN) +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a154) +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_DCD_CDIV_DCDR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007a154) +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_DCD_CDIV_DCDR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007a154) +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_DCD_CDIV_DCDR_RMSK 0x1 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_DCD_CDIV_DCDR_ATTR 0x3 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_DCD_CDIV_DCDR_IN \ + in_dword_masked(HWIO_GCC_MSS_Q6_MEMNOC_AXI_DCD_CDIV_DCDR_ADDR, HWIO_GCC_MSS_Q6_MEMNOC_AXI_DCD_CDIV_DCDR_RMSK) +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_DCD_CDIV_DCDR_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_Q6_MEMNOC_AXI_DCD_CDIV_DCDR_ADDR, m) +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_DCD_CDIV_DCDR_OUT(v) \ + out_dword(HWIO_GCC_MSS_Q6_MEMNOC_AXI_DCD_CDIV_DCDR_ADDR,v) +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_DCD_CDIV_DCDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_Q6_MEMNOC_AXI_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_MSS_Q6_MEMNOC_AXI_DCD_CDIV_DCDR_IN) +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_DCD_CDIV_DCDR_DCD_ENABLE_BMSK 0x1 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_DCD_CDIV_DCDR_DCD_ENABLE_SHFT 0x0 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_DCD_CDIV_DCDR_DCD_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_DCD_CDIV_DCDR_DCD_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a178) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007a178) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007a178) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF0_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF0_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF0_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF0_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a17c) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007a17c) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007a17c) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF1_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF1_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF1_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF1_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a180) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007a180) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007a180) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF2_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF2_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF2_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF2_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a184) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007a184) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007a184) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF3_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF3_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF3_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF3_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a188) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007a188) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007a188) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF4_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF4_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF4_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF4_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a18c) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007a18c) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007a18c) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF5_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF5_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF5_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF5_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a190) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007a190) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007a190) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF6_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF6_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF6_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF6_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a194) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007a194) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007a194) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF7_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF7_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF7_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF7_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF8_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a198) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF8_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007a198) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF8_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007a198) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF8_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF8_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF8_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF8_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF8_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF8_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF8_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF8_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF8_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF8_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF8_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF8_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF8_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF8_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF8_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF8_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF8_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF8_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF8_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF8_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF8_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF8_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF8_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF8_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF8_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF8_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF8_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF8_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF8_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF8_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF8_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF8_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF8_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF8_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF8_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF8_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF8_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF8_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF8_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF8_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF8_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF8_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF8_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF8_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF8_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF8_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF8_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF8_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF8_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF8_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF8_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF8_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF8_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF8_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF8_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF9_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a19c) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF9_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007a19c) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF9_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007a19c) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF9_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF9_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF9_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF9_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF9_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF9_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF9_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF9_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF9_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF9_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF9_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF9_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF9_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF9_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF9_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF9_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF9_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF9_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF9_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF9_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF9_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF9_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF9_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF9_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF9_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF9_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF9_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF9_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF9_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF9_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF9_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF9_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF9_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF9_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF9_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF9_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF9_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF9_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF9_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF9_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF9_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF9_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF9_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF9_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF9_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF9_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF9_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF9_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF9_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF9_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF9_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF9_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF9_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF9_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF9_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF10_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a1a0) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF10_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007a1a0) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF10_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007a1a0) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF10_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF10_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF10_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF10_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF10_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF10_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF10_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF10_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF10_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF10_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF10_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF10_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF10_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF10_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF10_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF10_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF10_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF10_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF10_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF10_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF10_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF10_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF10_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF10_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF10_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF10_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF10_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF10_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF10_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF10_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF10_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF10_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF10_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF10_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF10_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF10_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF10_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF10_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF10_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF10_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF10_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF10_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF10_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF10_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF10_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF10_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF10_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF10_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF10_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF10_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF10_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF10_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF10_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF10_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF10_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF11_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a1a4) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF11_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007a1a4) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF11_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007a1a4) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF11_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF11_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF11_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF11_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF11_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF11_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF11_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF11_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF11_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF11_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF11_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF11_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF11_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF11_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF11_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF11_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF11_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF11_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF11_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF11_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF11_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF11_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF11_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF11_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF11_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF11_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF11_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF11_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF11_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF11_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF11_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF11_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF11_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF11_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF11_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF11_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF11_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF11_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF11_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF11_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF11_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF11_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF11_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF11_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF11_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF11_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF11_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF11_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF11_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF11_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF11_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF11_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF11_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF11_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF11_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF12_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a1a8) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF12_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007a1a8) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF12_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007a1a8) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF12_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF12_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF12_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF12_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF12_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF12_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF12_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF12_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF12_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF12_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF12_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF12_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF12_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF12_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF12_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF12_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF12_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF12_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF12_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF12_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF12_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF12_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF12_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF12_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF12_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF12_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF12_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF12_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF12_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF12_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF12_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF12_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF12_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF12_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF12_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF12_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF12_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF12_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF12_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF12_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF12_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF12_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF12_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF12_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF12_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF12_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF12_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF12_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF12_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF12_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF12_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF12_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF12_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF12_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF12_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF13_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a1ac) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF13_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007a1ac) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF13_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007a1ac) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF13_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF13_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF13_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF13_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF13_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF13_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF13_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF13_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF13_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF13_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF13_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF13_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF13_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF13_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF13_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF13_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF13_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF13_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF13_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF13_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF13_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF13_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF13_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF13_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF13_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF13_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF13_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF13_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF13_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF13_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF13_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF13_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF13_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF13_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF13_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF13_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF13_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF13_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF13_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF13_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF13_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF13_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF13_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF13_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF13_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF13_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF13_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF13_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF13_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF13_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF13_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF13_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF13_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF13_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF13_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF14_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a1b0) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF14_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007a1b0) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF14_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007a1b0) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF14_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF14_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF14_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF14_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF14_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF14_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF14_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF14_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF14_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF14_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF14_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF14_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF14_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF14_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF14_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF14_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF14_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF14_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF14_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF14_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF14_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF14_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF14_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF14_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF14_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF14_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF14_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF14_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF14_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF14_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF14_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF14_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF14_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF14_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF14_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF14_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF14_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF14_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF14_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF14_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF14_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF14_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF14_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF14_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF14_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF14_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF14_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF14_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF14_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF14_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF14_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF14_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF14_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF14_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF14_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF15_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a1b4) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF15_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007a1b4) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF15_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007a1b4) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF15_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF15_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF15_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF15_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF15_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF15_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF15_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF15_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF15_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF15_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF15_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF15_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF15_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF15_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF15_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF15_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF15_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF15_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF15_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF15_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF15_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF15_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF15_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF15_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF15_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF15_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF15_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF15_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF15_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF15_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF15_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF15_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF15_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF15_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF15_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF15_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF15_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF15_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF15_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF15_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF15_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF15_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF15_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF15_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF15_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF15_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF15_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF15_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF15_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF15_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF15_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF15_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF15_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF15_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF15_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_MSS_OFFLINE_AXI_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a15c) +#define HWIO_GCC_MSS_OFFLINE_AXI_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007a15c) +#define HWIO_GCC_MSS_OFFLINE_AXI_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007a15c) +#define HWIO_GCC_MSS_OFFLINE_AXI_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_MSS_OFFLINE_AXI_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_MSS_OFFLINE_AXI_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_MSS_OFFLINE_AXI_CMD_RCGR_ADDR, HWIO_GCC_MSS_OFFLINE_AXI_CMD_RCGR_RMSK) +#define HWIO_GCC_MSS_OFFLINE_AXI_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_OFFLINE_AXI_CMD_RCGR_ADDR, m) +#define HWIO_GCC_MSS_OFFLINE_AXI_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_MSS_OFFLINE_AXI_CMD_RCGR_ADDR,v) +#define HWIO_GCC_MSS_OFFLINE_AXI_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_OFFLINE_AXI_CMD_RCGR_ADDR,m,v,HWIO_GCC_MSS_OFFLINE_AXI_CMD_RCGR_IN) +#define HWIO_GCC_MSS_OFFLINE_AXI_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_MSS_OFFLINE_AXI_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_MSS_OFFLINE_AXI_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_MSS_OFFLINE_AXI_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_MSS_OFFLINE_AXI_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_MSS_OFFLINE_AXI_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_MSS_OFFLINE_AXI_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_OFFLINE_AXI_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_OFFLINE_AXI_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_MSS_OFFLINE_AXI_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_MSS_OFFLINE_AXI_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_OFFLINE_AXI_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a160) +#define HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007a160) +#define HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007a160) +#define HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_ADDR, HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_RMSK) +#define HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_ADDR, m) +#define HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_ADDR,v) +#define HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_ADDR,m,v,HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_IN) +#define HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_MSS_OFFLINE_AXI_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_GLM_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007b000) +#define HWIO_GCC_GLM_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007b000) +#define HWIO_GCC_GLM_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007b000) +#define HWIO_GCC_GLM_BCR_RMSK 0x1 +#define HWIO_GCC_GLM_BCR_ATTR 0x3 +#define HWIO_GCC_GLM_BCR_IN \ + in_dword_masked(HWIO_GCC_GLM_BCR_ADDR, HWIO_GCC_GLM_BCR_RMSK) +#define HWIO_GCC_GLM_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_GLM_BCR_ADDR, m) +#define HWIO_GCC_GLM_BCR_OUT(v) \ + out_dword(HWIO_GCC_GLM_BCR_ADDR,v) +#define HWIO_GCC_GLM_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GLM_BCR_ADDR,m,v,HWIO_GCC_GLM_BCR_IN) +#define HWIO_GCC_GLM_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_GLM_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_GLM_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_GLM_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GLM_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007b004) +#define HWIO_GCC_GLM_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007b004) +#define HWIO_GCC_GLM_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007b004) +#define HWIO_GCC_GLM_AHB_CBCR_RMSK 0x81d00005 +#define HWIO_GCC_GLM_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_GLM_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_GLM_AHB_CBCR_ADDR, HWIO_GCC_GLM_AHB_CBCR_RMSK) +#define HWIO_GCC_GLM_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_GLM_AHB_CBCR_ADDR, m) +#define HWIO_GCC_GLM_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_GLM_AHB_CBCR_ADDR,v) +#define HWIO_GCC_GLM_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GLM_AHB_CBCR_ADDR,m,v,HWIO_GCC_GLM_AHB_CBCR_IN) +#define HWIO_GCC_GLM_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_GLM_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_GLM_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_GLM_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_GLM_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_GLM_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_GLM_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_GLM_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_GLM_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_GLM_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_GLM_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_GLM_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_GLM_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_GLM_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_GLM_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GLM_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_GLM_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GLM_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GLM_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007b008) +#define HWIO_GCC_GLM_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007b008) +#define HWIO_GCC_GLM_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007b008) +#define HWIO_GCC_GLM_CBCR_RMSK 0x81c0000f +#define HWIO_GCC_GLM_CBCR_ATTR 0x3 +#define HWIO_GCC_GLM_CBCR_IN \ + in_dword_masked(HWIO_GCC_GLM_CBCR_ADDR, HWIO_GCC_GLM_CBCR_RMSK) +#define HWIO_GCC_GLM_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_GLM_CBCR_ADDR, m) +#define HWIO_GCC_GLM_CBCR_OUT(v) \ + out_dword(HWIO_GCC_GLM_CBCR_ADDR,v) +#define HWIO_GCC_GLM_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GLM_CBCR_ADDR,m,v,HWIO_GCC_GLM_CBCR_IN) +#define HWIO_GCC_GLM_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_GLM_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_GLM_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_GLM_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_GLM_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_GLM_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_GLM_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_GLM_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_GLM_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_GLM_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_GLM_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_GLM_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_GLM_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_GLM_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_GLM_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_GLM_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_GLM_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_GLM_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_GLM_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GLM_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_GLM_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GLM_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GLM_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007b00c) +#define HWIO_GCC_GLM_XO_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007b00c) +#define HWIO_GCC_GLM_XO_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007b00c) +#define HWIO_GCC_GLM_XO_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_GLM_XO_CBCR_ATTR 0x3 +#define HWIO_GCC_GLM_XO_CBCR_IN \ + in_dword_masked(HWIO_GCC_GLM_XO_CBCR_ADDR, HWIO_GCC_GLM_XO_CBCR_RMSK) +#define HWIO_GCC_GLM_XO_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_GLM_XO_CBCR_ADDR, m) +#define HWIO_GCC_GLM_XO_CBCR_OUT(v) \ + out_dword(HWIO_GCC_GLM_XO_CBCR_ADDR,v) +#define HWIO_GCC_GLM_XO_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GLM_XO_CBCR_ADDR,m,v,HWIO_GCC_GLM_XO_CBCR_IN) +#define HWIO_GCC_GLM_XO_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_GLM_XO_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_GLM_XO_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_GLM_XO_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_GLM_XO_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_GLM_XO_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_GLM_XO_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_GLM_XO_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_GLM_XO_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_GLM_XO_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_GLM_XO_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_GLM_XO_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_GLM_XO_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GLM_XO_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_GLM_XO_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GLM_XO_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GLM_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007b010) +#define HWIO_GCC_GLM_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007b010) +#define HWIO_GCC_GLM_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007b010) +#define HWIO_GCC_GLM_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_GLM_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_GLM_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_GLM_CMD_RCGR_ADDR, HWIO_GCC_GLM_CMD_RCGR_RMSK) +#define HWIO_GCC_GLM_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_GLM_CMD_RCGR_ADDR, m) +#define HWIO_GCC_GLM_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_GLM_CMD_RCGR_ADDR,v) +#define HWIO_GCC_GLM_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GLM_CMD_RCGR_ADDR,m,v,HWIO_GCC_GLM_CMD_RCGR_IN) +#define HWIO_GCC_GLM_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_GLM_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_GLM_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_GLM_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_GLM_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_GLM_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_GLM_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_GLM_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_GLM_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_GLM_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_GLM_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GLM_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GLM_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007b014) +#define HWIO_GCC_GLM_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007b014) +#define HWIO_GCC_GLM_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007b014) +#define HWIO_GCC_GLM_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_GLM_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_GLM_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_GLM_CFG_RCGR_ADDR, HWIO_GCC_GLM_CFG_RCGR_RMSK) +#define HWIO_GCC_GLM_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_GLM_CFG_RCGR_ADDR, m) +#define HWIO_GCC_GLM_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_GLM_CFG_RCGR_ADDR,v) +#define HWIO_GCC_GLM_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GLM_CFG_RCGR_ADDR,m,v,HWIO_GCC_GLM_CFG_RCGR_IN) +#define HWIO_GCC_GLM_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_GLM_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_GLM_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_GLM_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_GLM_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_GLM_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_GLM_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_GLM_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_GLM_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_GLM_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_GLM_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_GLM_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_GLM_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_GLM_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_GLM_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_GLM_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_GLM_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_GLM_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_GLM_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_GLM_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_GLM_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_GLM_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_GLM_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_GLM_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_GLM_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_GLM_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_GLM_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_GLM_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_GLM_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_GLM_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_GLM_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_GLM_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_GLM_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_GLM_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_GLM_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_GLM_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_GLM_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_GLM_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_GLM_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_GLM_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_GLM_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_GLM_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_GLM_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_GLM_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_GLM_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_GLM_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_GLM_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_GLM_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_GLM_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_GLM_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_GLM_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_GLM_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_GPU_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00061000) +#define HWIO_GCC_GPU_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00061000) +#define HWIO_GCC_GPU_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00061000) +#define HWIO_GCC_GPU_BCR_RMSK 0x1 +#define HWIO_GCC_GPU_BCR_ATTR 0x3 +#define HWIO_GCC_GPU_BCR_IN \ + in_dword_masked(HWIO_GCC_GPU_BCR_ADDR, HWIO_GCC_GPU_BCR_RMSK) +#define HWIO_GCC_GPU_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_GPU_BCR_ADDR, m) +#define HWIO_GCC_GPU_BCR_OUT(v) \ + out_dword(HWIO_GCC_GPU_BCR_ADDR,v) +#define HWIO_GCC_GPU_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPU_BCR_ADDR,m,v,HWIO_GCC_GPU_BCR_IN) +#define HWIO_GCC_GPU_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_GPU_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_GPU_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_GPU_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GPU_CFG_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00061004) +#define HWIO_GCC_GPU_CFG_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00061004) +#define HWIO_GCC_GPU_CFG_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00061004) +#define HWIO_GCC_GPU_CFG_AHB_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_GPU_CFG_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_GPU_CFG_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_GPU_CFG_AHB_CBCR_ADDR, HWIO_GCC_GPU_CFG_AHB_CBCR_RMSK) +#define HWIO_GCC_GPU_CFG_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_GPU_CFG_AHB_CBCR_ADDR, m) +#define HWIO_GCC_GPU_CFG_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_GPU_CFG_AHB_CBCR_ADDR,v) +#define HWIO_GCC_GPU_CFG_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPU_CFG_AHB_CBCR_ADDR,m,v,HWIO_GCC_GPU_CFG_AHB_CBCR_IN) +#define HWIO_GCC_GPU_CFG_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_GPU_CFG_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_GPU_CFG_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_GPU_CFG_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_GPU_CFG_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_GPU_CFG_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_GPU_CFG_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_GPU_CFG_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_GPU_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_GPU_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_GPU_CFG_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_GPU_CFG_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_GPU_CFG_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_GPU_CFG_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_GPU_CFG_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_GPU_CFG_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_GPU_CFG_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_GPU_CFG_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_GPU_CFG_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_GPU_CFG_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_GPU_CFG_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GPU_CFG_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_GPU_CFG_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GPU_CFG_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QMIP_GPU_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00061008) +#define HWIO_GCC_QMIP_GPU_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00061008) +#define HWIO_GCC_QMIP_GPU_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00061008) +#define HWIO_GCC_QMIP_GPU_AHB_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_QMIP_GPU_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_QMIP_GPU_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_QMIP_GPU_AHB_CBCR_ADDR, HWIO_GCC_QMIP_GPU_AHB_CBCR_RMSK) +#define HWIO_GCC_QMIP_GPU_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QMIP_GPU_AHB_CBCR_ADDR, m) +#define HWIO_GCC_QMIP_GPU_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QMIP_GPU_AHB_CBCR_ADDR,v) +#define HWIO_GCC_QMIP_GPU_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QMIP_GPU_AHB_CBCR_ADDR,m,v,HWIO_GCC_QMIP_GPU_AHB_CBCR_IN) +#define HWIO_GCC_QMIP_GPU_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QMIP_GPU_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QMIP_GPU_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QMIP_GPU_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QMIP_GPU_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QMIP_GPU_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QMIP_GPU_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QMIP_GPU_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QMIP_GPU_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_QMIP_GPU_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_QMIP_GPU_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_QMIP_GPU_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_QMIP_GPU_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QMIP_GPU_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QMIP_GPU_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QMIP_GPU_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_QMIP_GPU_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_QMIP_GPU_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_QMIP_GPU_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QMIP_GPU_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QMIP_GPU_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_QMIP_GPU_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_QMIP_GPU_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QMIP_GPU_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GPU_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006100c) +#define HWIO_GCC_GPU_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006100c) +#define HWIO_GCC_GPU_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006100c) +#define HWIO_GCC_GPU_AT_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_GPU_AT_CBCR_ATTR 0x3 +#define HWIO_GCC_GPU_AT_CBCR_IN \ + in_dword_masked(HWIO_GCC_GPU_AT_CBCR_ADDR, HWIO_GCC_GPU_AT_CBCR_RMSK) +#define HWIO_GCC_GPU_AT_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_GPU_AT_CBCR_ADDR, m) +#define HWIO_GCC_GPU_AT_CBCR_OUT(v) \ + out_dword(HWIO_GCC_GPU_AT_CBCR_ADDR,v) +#define HWIO_GCC_GPU_AT_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPU_AT_CBCR_ADDR,m,v,HWIO_GCC_GPU_AT_CBCR_IN) +#define HWIO_GCC_GPU_AT_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_GPU_AT_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_GPU_AT_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_GPU_AT_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_GPU_AT_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_GPU_AT_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_GPU_AT_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_GPU_AT_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_GPU_AT_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_GPU_AT_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_GPU_AT_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_GPU_AT_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_GPU_AT_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_GPU_AT_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_GPU_AT_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_GPU_AT_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_GPU_AT_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_GPU_AT_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_GPU_AT_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_GPU_AT_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_GPU_AT_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GPU_AT_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_GPU_AT_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GPU_AT_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00061010) +#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00061010) +#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00061010) +#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_ATTR 0x3 +#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_IN \ + in_dword_masked(HWIO_GCC_GPU_MEMNOC_GFX_CBCR_ADDR, HWIO_GCC_GPU_MEMNOC_GFX_CBCR_RMSK) +#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_GPU_MEMNOC_GFX_CBCR_ADDR, m) +#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_OUT(v) \ + out_dword(HWIO_GCC_GPU_MEMNOC_GFX_CBCR_ADDR,v) +#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPU_MEMNOC_GFX_CBCR_ADDR,m,v,HWIO_GCC_GPU_MEMNOC_GFX_CBCR_IN) +#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GPU_TRIG_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00061014) +#define HWIO_GCC_GPU_TRIG_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00061014) +#define HWIO_GCC_GPU_TRIG_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00061014) +#define HWIO_GCC_GPU_TRIG_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_GPU_TRIG_CBCR_ATTR 0x3 +#define HWIO_GCC_GPU_TRIG_CBCR_IN \ + in_dword_masked(HWIO_GCC_GPU_TRIG_CBCR_ADDR, HWIO_GCC_GPU_TRIG_CBCR_RMSK) +#define HWIO_GCC_GPU_TRIG_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_GPU_TRIG_CBCR_ADDR, m) +#define HWIO_GCC_GPU_TRIG_CBCR_OUT(v) \ + out_dword(HWIO_GCC_GPU_TRIG_CBCR_ADDR,v) +#define HWIO_GCC_GPU_TRIG_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPU_TRIG_CBCR_ADDR,m,v,HWIO_GCC_GPU_TRIG_CBCR_IN) +#define HWIO_GCC_GPU_TRIG_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_GPU_TRIG_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_GPU_TRIG_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_GPU_TRIG_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_GPU_TRIG_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_GPU_TRIG_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_GPU_TRIG_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_GPU_TRIG_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_GPU_TRIG_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_GPU_TRIG_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_GPU_TRIG_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_GPU_TRIG_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_GPU_TRIG_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_GPU_TRIG_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_GPU_TRIG_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_GPU_TRIG_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_GPU_TRIG_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_GPU_TRIG_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_GPU_TRIG_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_GPU_TRIG_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_GPU_TRIG_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GPU_TRIG_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_GPU_TRIG_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GPU_TRIG_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GPU_SNOC_DVM_GFX_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00061018) +#define HWIO_GCC_GPU_SNOC_DVM_GFX_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00061018) +#define HWIO_GCC_GPU_SNOC_DVM_GFX_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00061018) +#define HWIO_GCC_GPU_SNOC_DVM_GFX_CBCR_RMSK 0x81d00005 +#define HWIO_GCC_GPU_SNOC_DVM_GFX_CBCR_ATTR 0x3 +#define HWIO_GCC_GPU_SNOC_DVM_GFX_CBCR_IN \ + in_dword_masked(HWIO_GCC_GPU_SNOC_DVM_GFX_CBCR_ADDR, HWIO_GCC_GPU_SNOC_DVM_GFX_CBCR_RMSK) +#define HWIO_GCC_GPU_SNOC_DVM_GFX_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_GPU_SNOC_DVM_GFX_CBCR_ADDR, m) +#define HWIO_GCC_GPU_SNOC_DVM_GFX_CBCR_OUT(v) \ + out_dword(HWIO_GCC_GPU_SNOC_DVM_GFX_CBCR_ADDR,v) +#define HWIO_GCC_GPU_SNOC_DVM_GFX_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPU_SNOC_DVM_GFX_CBCR_ADDR,m,v,HWIO_GCC_GPU_SNOC_DVM_GFX_CBCR_IN) +#define HWIO_GCC_GPU_SNOC_DVM_GFX_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_GPU_SNOC_DVM_GFX_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_GPU_SNOC_DVM_GFX_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_GPU_SNOC_DVM_GFX_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_GPU_SNOC_DVM_GFX_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_GPU_SNOC_DVM_GFX_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_GPU_SNOC_DVM_GFX_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_GPU_SNOC_DVM_GFX_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_GPU_SNOC_DVM_GFX_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_GPU_SNOC_DVM_GFX_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_GPU_SNOC_DVM_GFX_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_GPU_SNOC_DVM_GFX_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_GPU_SNOC_DVM_GFX_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_GPU_SNOC_DVM_GFX_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_GPU_SNOC_DVM_GFX_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GPU_SNOC_DVM_GFX_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_GPU_SNOC_DVM_GFX_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GPU_SNOC_DVM_GFX_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00061038) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00061038) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00061038) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006103c) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006103c) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006103c) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00061040) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00061040) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00061040) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00061044) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00061044) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00061044) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00061048) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00061048) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00061048) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006104c) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006104c) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006104c) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00061050) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00061050) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00061050) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00061054) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00061054) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00061054) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00061058) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00061058) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00061058) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006105c) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006105c) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006105c) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00061060) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00061060) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00061060) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00061064) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00061064) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00061064) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00061068) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00061068) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00061068) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006106c) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006106c) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006106c) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00061070) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00061070) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00061070) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00061074) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00061074) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00061074) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_RMSK 0x71f +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_ADDR, HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_RMSK) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_IN) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_GPU_MEMNOC_GFX_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006101c) +#define HWIO_GCC_GPU_MEMNOC_GFX_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006101c) +#define HWIO_GCC_GPU_MEMNOC_GFX_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006101c) +#define HWIO_GCC_GPU_MEMNOC_GFX_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_GPU_MEMNOC_GFX_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_GPU_MEMNOC_GFX_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_GPU_MEMNOC_GFX_CMD_RCGR_ADDR, HWIO_GCC_GPU_MEMNOC_GFX_CMD_RCGR_RMSK) +#define HWIO_GCC_GPU_MEMNOC_GFX_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_GPU_MEMNOC_GFX_CMD_RCGR_ADDR, m) +#define HWIO_GCC_GPU_MEMNOC_GFX_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_GPU_MEMNOC_GFX_CMD_RCGR_ADDR,v) +#define HWIO_GCC_GPU_MEMNOC_GFX_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPU_MEMNOC_GFX_CMD_RCGR_ADDR,m,v,HWIO_GCC_GPU_MEMNOC_GFX_CMD_RCGR_IN) +#define HWIO_GCC_GPU_MEMNOC_GFX_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_GPU_MEMNOC_GFX_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_GPU_MEMNOC_GFX_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_GPU_MEMNOC_GFX_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_GPU_MEMNOC_GFX_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_GPU_MEMNOC_GFX_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_GPU_MEMNOC_GFX_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_GPU_MEMNOC_GFX_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_GPU_MEMNOC_GFX_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_GPU_MEMNOC_GFX_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_GPU_MEMNOC_GFX_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GPU_MEMNOC_GFX_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00061020) +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00061020) +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00061020) +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_ADDR, HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_RMSK) +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_ADDR, m) +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_ADDR,v) +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_ADDR,m,v,HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_IN) +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_GPU_MEMNOC_GFX_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00061148) +#define HWIO_GCC_GPU_MEMNOC_GFX_DCD_CDIV_DCDR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00061148) +#define HWIO_GCC_GPU_MEMNOC_GFX_DCD_CDIV_DCDR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00061148) +#define HWIO_GCC_GPU_MEMNOC_GFX_DCD_CDIV_DCDR_RMSK 0x1 +#define HWIO_GCC_GPU_MEMNOC_GFX_DCD_CDIV_DCDR_ATTR 0x3 +#define HWIO_GCC_GPU_MEMNOC_GFX_DCD_CDIV_DCDR_IN \ + in_dword_masked(HWIO_GCC_GPU_MEMNOC_GFX_DCD_CDIV_DCDR_ADDR, HWIO_GCC_GPU_MEMNOC_GFX_DCD_CDIV_DCDR_RMSK) +#define HWIO_GCC_GPU_MEMNOC_GFX_DCD_CDIV_DCDR_INM(m) \ + in_dword_masked(HWIO_GCC_GPU_MEMNOC_GFX_DCD_CDIV_DCDR_ADDR, m) +#define HWIO_GCC_GPU_MEMNOC_GFX_DCD_CDIV_DCDR_OUT(v) \ + out_dword(HWIO_GCC_GPU_MEMNOC_GFX_DCD_CDIV_DCDR_ADDR,v) +#define HWIO_GCC_GPU_MEMNOC_GFX_DCD_CDIV_DCDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPU_MEMNOC_GFX_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_GPU_MEMNOC_GFX_DCD_CDIV_DCDR_IN) +#define HWIO_GCC_GPU_MEMNOC_GFX_DCD_CDIV_DCDR_DCD_ENABLE_BMSK 0x1 +#define HWIO_GCC_GPU_MEMNOC_GFX_DCD_CDIV_DCDR_DCD_ENABLE_SHFT 0x0 +#define HWIO_GCC_GPU_MEMNOC_GFX_DCD_CDIV_DCDR_DCD_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GPU_MEMNOC_GFX_DCD_CDIV_DCDR_DCD_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GPU_PLL0_MAIN_DIV_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006114c) +#define HWIO_GCC_GPU_PLL0_MAIN_DIV_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006114c) +#define HWIO_GCC_GPU_PLL0_MAIN_DIV_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006114c) +#define HWIO_GCC_GPU_PLL0_MAIN_DIV_CDIVR_RMSK 0xf +#define HWIO_GCC_GPU_PLL0_MAIN_DIV_CDIVR_ATTR 0x3 +#define HWIO_GCC_GPU_PLL0_MAIN_DIV_CDIVR_IN \ + in_dword_masked(HWIO_GCC_GPU_PLL0_MAIN_DIV_CDIVR_ADDR, HWIO_GCC_GPU_PLL0_MAIN_DIV_CDIVR_RMSK) +#define HWIO_GCC_GPU_PLL0_MAIN_DIV_CDIVR_INM(m) \ + in_dword_masked(HWIO_GCC_GPU_PLL0_MAIN_DIV_CDIVR_ADDR, m) +#define HWIO_GCC_GPU_PLL0_MAIN_DIV_CDIVR_OUT(v) \ + out_dword(HWIO_GCC_GPU_PLL0_MAIN_DIV_CDIVR_ADDR,v) +#define HWIO_GCC_GPU_PLL0_MAIN_DIV_CDIVR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPU_PLL0_MAIN_DIV_CDIVR_ADDR,m,v,HWIO_GCC_GPU_PLL0_MAIN_DIV_CDIVR_IN) +#define HWIO_GCC_GPU_PLL0_MAIN_DIV_CDIVR_CLK_DIV_BMSK 0xf +#define HWIO_GCC_GPU_PLL0_MAIN_DIV_CDIVR_CLK_DIV_SHFT 0x0 + +#define HWIO_GCC_GPU_TRIG_DIV_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00061150) +#define HWIO_GCC_GPU_TRIG_DIV_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00061150) +#define HWIO_GCC_GPU_TRIG_DIV_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00061150) +#define HWIO_GCC_GPU_TRIG_DIV_CDIVR_RMSK 0xf +#define HWIO_GCC_GPU_TRIG_DIV_CDIVR_ATTR 0x3 +#define HWIO_GCC_GPU_TRIG_DIV_CDIVR_IN \ + in_dword_masked(HWIO_GCC_GPU_TRIG_DIV_CDIVR_ADDR, HWIO_GCC_GPU_TRIG_DIV_CDIVR_RMSK) +#define HWIO_GCC_GPU_TRIG_DIV_CDIVR_INM(m) \ + in_dword_masked(HWIO_GCC_GPU_TRIG_DIV_CDIVR_ADDR, m) +#define HWIO_GCC_GPU_TRIG_DIV_CDIVR_OUT(v) \ + out_dword(HWIO_GCC_GPU_TRIG_DIV_CDIVR_ADDR,v) +#define HWIO_GCC_GPU_TRIG_DIV_CDIVR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPU_TRIG_DIV_CDIVR_ADDR,m,v,HWIO_GCC_GPU_TRIG_DIV_CDIVR_IN) +#define HWIO_GCC_GPU_TRIG_DIV_CDIVR_CLK_DIV_BMSK 0xf +#define HWIO_GCC_GPU_TRIG_DIV_CDIVR_CLK_DIV_SHFT 0x0 + +#define HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00062000) +#define HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00062000) +#define HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00062000) +#define HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_ATTR 0x3 +#define HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_IN \ + in_dword_masked(HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_ADDR, HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_RMSK) +#define HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_ADDR, m) +#define HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_OUT(v) \ + out_dword(HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_ADDR,v) +#define HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_ADDR,m,v,HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_IN) +#define HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SP_SCR_NIU_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00062004) +#define HWIO_GCC_SP_SCR_NIU_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00062004) +#define HWIO_GCC_SP_SCR_NIU_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00062004) +#define HWIO_GCC_SP_SCR_NIU_CBCR_RMSK 0x81d00005 +#define HWIO_GCC_SP_SCR_NIU_CBCR_ATTR 0x3 +#define HWIO_GCC_SP_SCR_NIU_CBCR_IN \ + in_dword_masked(HWIO_GCC_SP_SCR_NIU_CBCR_ADDR, HWIO_GCC_SP_SCR_NIU_CBCR_RMSK) +#define HWIO_GCC_SP_SCR_NIU_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_SP_SCR_NIU_CBCR_ADDR, m) +#define HWIO_GCC_SP_SCR_NIU_CBCR_OUT(v) \ + out_dword(HWIO_GCC_SP_SCR_NIU_CBCR_ADDR,v) +#define HWIO_GCC_SP_SCR_NIU_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SP_SCR_NIU_CBCR_ADDR,m,v,HWIO_GCC_SP_SCR_NIU_CBCR_IN) +#define HWIO_GCC_SP_SCR_NIU_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SP_SCR_NIU_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SP_SCR_NIU_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_SP_SCR_NIU_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_SP_SCR_NIU_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_SP_SCR_NIU_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_SP_SCR_NIU_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_SP_SCR_NIU_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_SP_SCR_NIU_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_SP_SCR_NIU_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_SP_SCR_NIU_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_SP_SCR_NIU_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_SP_SCR_NIU_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SP_SCR_NIU_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_SP_SCR_NIU_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SP_SCR_NIU_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SP_SCR_NIU_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_SCR_NIU_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SP_CFG_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00062008) +#define HWIO_GCC_SP_CFG_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00062008) +#define HWIO_GCC_SP_CFG_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00062008) +#define HWIO_GCC_SP_CFG_AHB_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_SP_CFG_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_SP_CFG_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_SP_CFG_AHB_CBCR_ADDR, HWIO_GCC_SP_CFG_AHB_CBCR_RMSK) +#define HWIO_GCC_SP_CFG_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_SP_CFG_AHB_CBCR_ADDR, m) +#define HWIO_GCC_SP_CFG_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_SP_CFG_AHB_CBCR_ADDR,v) +#define HWIO_GCC_SP_CFG_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SP_CFG_AHB_CBCR_ADDR,m,v,HWIO_GCC_SP_CFG_AHB_CBCR_IN) +#define HWIO_GCC_SP_CFG_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SP_CFG_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SP_CFG_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_SP_CFG_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_SP_CFG_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_SP_CFG_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_SP_CFG_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_SP_CFG_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_SP_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_SP_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_SP_CFG_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_SP_CFG_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_SP_CFG_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_SP_CFG_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_SP_CFG_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SP_CFG_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_SP_CFG_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_SP_CFG_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_SP_CFG_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CFG_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CFG_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SP_CFG_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SP_CFG_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CFG_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SP_SCSR_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006200c) +#define HWIO_GCC_SP_SCSR_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006200c) +#define HWIO_GCC_SP_SCSR_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006200c) +#define HWIO_GCC_SP_SCSR_CBCR_RMSK 0x81d00005 +#define HWIO_GCC_SP_SCSR_CBCR_ATTR 0x3 +#define HWIO_GCC_SP_SCSR_CBCR_IN \ + in_dword_masked(HWIO_GCC_SP_SCSR_CBCR_ADDR, HWIO_GCC_SP_SCSR_CBCR_RMSK) +#define HWIO_GCC_SP_SCSR_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_SP_SCSR_CBCR_ADDR, m) +#define HWIO_GCC_SP_SCSR_CBCR_OUT(v) \ + out_dword(HWIO_GCC_SP_SCSR_CBCR_ADDR,v) +#define HWIO_GCC_SP_SCSR_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SP_SCSR_CBCR_ADDR,m,v,HWIO_GCC_SP_SCSR_CBCR_IN) +#define HWIO_GCC_SP_SCSR_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SP_SCSR_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SP_SCSR_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_SP_SCSR_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_SP_SCSR_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_SP_SCSR_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_SP_SCSR_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_SP_SCSR_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_SP_SCSR_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_SP_SCSR_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_SP_SCSR_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_SP_SCSR_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_SP_SCSR_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SP_SCSR_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_SP_SCSR_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SP_SCSR_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SP_SCSR_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_SCSR_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SP_GPKT_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00062010) +#define HWIO_GCC_SP_GPKT_XO_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00062010) +#define HWIO_GCC_SP_GPKT_XO_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00062010) +#define HWIO_GCC_SP_GPKT_XO_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_SP_GPKT_XO_CBCR_ATTR 0x3 +#define HWIO_GCC_SP_GPKT_XO_CBCR_IN \ + in_dword_masked(HWIO_GCC_SP_GPKT_XO_CBCR_ADDR, HWIO_GCC_SP_GPKT_XO_CBCR_RMSK) +#define HWIO_GCC_SP_GPKT_XO_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_SP_GPKT_XO_CBCR_ADDR, m) +#define HWIO_GCC_SP_GPKT_XO_CBCR_OUT(v) \ + out_dword(HWIO_GCC_SP_GPKT_XO_CBCR_ADDR,v) +#define HWIO_GCC_SP_GPKT_XO_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SP_GPKT_XO_CBCR_ADDR,m,v,HWIO_GCC_SP_GPKT_XO_CBCR_IN) +#define HWIO_GCC_SP_GPKT_XO_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SP_GPKT_XO_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SP_GPKT_XO_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_SP_GPKT_XO_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_SP_GPKT_XO_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_SP_GPKT_XO_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_SP_GPKT_XO_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_SP_GPKT_XO_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_SP_GPKT_XO_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_SP_GPKT_XO_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_SP_GPKT_XO_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SP_GPKT_XO_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_SP_GPKT_XO_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SP_GPKT_XO_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SP_GPKT_XO_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_GPKT_XO_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SP_TRIG_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00062014) +#define HWIO_GCC_SP_TRIG_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00062014) +#define HWIO_GCC_SP_TRIG_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00062014) +#define HWIO_GCC_SP_TRIG_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_SP_TRIG_CBCR_ATTR 0x3 +#define HWIO_GCC_SP_TRIG_CBCR_IN \ + in_dword_masked(HWIO_GCC_SP_TRIG_CBCR_ADDR, HWIO_GCC_SP_TRIG_CBCR_RMSK) +#define HWIO_GCC_SP_TRIG_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_SP_TRIG_CBCR_ADDR, m) +#define HWIO_GCC_SP_TRIG_CBCR_OUT(v) \ + out_dword(HWIO_GCC_SP_TRIG_CBCR_ADDR,v) +#define HWIO_GCC_SP_TRIG_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SP_TRIG_CBCR_ADDR,m,v,HWIO_GCC_SP_TRIG_CBCR_IN) +#define HWIO_GCC_SP_TRIG_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SP_TRIG_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SP_TRIG_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_SP_TRIG_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_SP_TRIG_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_SP_TRIG_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_SP_TRIG_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_SP_TRIG_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_SP_TRIG_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_SP_TRIG_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_SP_TRIG_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_SP_TRIG_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_SP_TRIG_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_SP_TRIG_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_SP_TRIG_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SP_TRIG_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_SP_TRIG_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_SP_TRIG_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_SP_TRIG_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_TRIG_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_TRIG_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SP_TRIG_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SP_TRIG_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_TRIG_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SP_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00062018) +#define HWIO_GCC_SP_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00062018) +#define HWIO_GCC_SP_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00062018) +#define HWIO_GCC_SP_AT_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_SP_AT_CBCR_ATTR 0x3 +#define HWIO_GCC_SP_AT_CBCR_IN \ + in_dword_masked(HWIO_GCC_SP_AT_CBCR_ADDR, HWIO_GCC_SP_AT_CBCR_RMSK) +#define HWIO_GCC_SP_AT_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_SP_AT_CBCR_ADDR, m) +#define HWIO_GCC_SP_AT_CBCR_OUT(v) \ + out_dword(HWIO_GCC_SP_AT_CBCR_ADDR,v) +#define HWIO_GCC_SP_AT_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SP_AT_CBCR_ADDR,m,v,HWIO_GCC_SP_AT_CBCR_IN) +#define HWIO_GCC_SP_AT_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SP_AT_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SP_AT_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_SP_AT_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_SP_AT_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_SP_AT_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_SP_AT_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_SP_AT_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_SP_AT_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_SP_AT_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_SP_AT_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_SP_AT_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_SP_AT_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_SP_AT_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_SP_AT_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_SP_AT_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_SP_AT_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_SP_AT_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_SP_AT_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_AT_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_AT_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SP_AT_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SP_AT_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_AT_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_NAV_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00005000) +#define HWIO_GCC_NAV_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00005000) +#define HWIO_GCC_NAV_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00005000) +#define HWIO_GCC_NAV_BCR_RMSK 0x1 +#define HWIO_GCC_NAV_BCR_ATTR 0x3 +#define HWIO_GCC_NAV_BCR_IN \ + in_dword_masked(HWIO_GCC_NAV_BCR_ADDR, HWIO_GCC_NAV_BCR_RMSK) +#define HWIO_GCC_NAV_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_NAV_BCR_ADDR, m) +#define HWIO_GCC_NAV_BCR_OUT(v) \ + out_dword(HWIO_GCC_NAV_BCR_ADDR,v) +#define HWIO_GCC_NAV_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_NAV_BCR_ADDR,m,v,HWIO_GCC_NAV_BCR_IN) +#define HWIO_GCC_NAV_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_NAV_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_NAV_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_NAV_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_NAV_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00005004) +#define HWIO_GCC_NAV_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00005004) +#define HWIO_GCC_NAV_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00005004) +#define HWIO_GCC_NAV_AXI_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_NAV_AXI_CBCR_ATTR 0x3 +#define HWIO_GCC_NAV_AXI_CBCR_IN \ + in_dword_masked(HWIO_GCC_NAV_AXI_CBCR_ADDR, HWIO_GCC_NAV_AXI_CBCR_RMSK) +#define HWIO_GCC_NAV_AXI_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_NAV_AXI_CBCR_ADDR, m) +#define HWIO_GCC_NAV_AXI_CBCR_OUT(v) \ + out_dword(HWIO_GCC_NAV_AXI_CBCR_ADDR,v) +#define HWIO_GCC_NAV_AXI_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_NAV_AXI_CBCR_ADDR,m,v,HWIO_GCC_NAV_AXI_CBCR_IN) +#define HWIO_GCC_NAV_AXI_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_NAV_AXI_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_NAV_AXI_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_NAV_AXI_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_NAV_AXI_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_NAV_AXI_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_NAV_AXI_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_NAV_AXI_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_NAV_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_NAV_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_NAV_AXI_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_NAV_AXI_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_NAV_AXI_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_NAV_AXI_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_NAV_AXI_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_NAV_AXI_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_NAV_AXI_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_NAV_AXI_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_NAV_AXI_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_NAV_AXI_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_NAV_AXI_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_NAV_AXI_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_NAV_AXI_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_NAV_AXI_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_AHB2PHY_SOUTH_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000a000) +#define HWIO_GCC_AHB2PHY_SOUTH_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000a000) +#define HWIO_GCC_AHB2PHY_SOUTH_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000a000) +#define HWIO_GCC_AHB2PHY_SOUTH_BCR_RMSK 0x1 +#define HWIO_GCC_AHB2PHY_SOUTH_BCR_ATTR 0x3 +#define HWIO_GCC_AHB2PHY_SOUTH_BCR_IN \ + in_dword_masked(HWIO_GCC_AHB2PHY_SOUTH_BCR_ADDR, HWIO_GCC_AHB2PHY_SOUTH_BCR_RMSK) +#define HWIO_GCC_AHB2PHY_SOUTH_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_AHB2PHY_SOUTH_BCR_ADDR, m) +#define HWIO_GCC_AHB2PHY_SOUTH_BCR_OUT(v) \ + out_dword(HWIO_GCC_AHB2PHY_SOUTH_BCR_ADDR,v) +#define HWIO_GCC_AHB2PHY_SOUTH_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AHB2PHY_SOUTH_BCR_ADDR,m,v,HWIO_GCC_AHB2PHY_SOUTH_BCR_IN) +#define HWIO_GCC_AHB2PHY_SOUTH_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_AHB2PHY_SOUTH_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_AHB2PHY_SOUTH_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_AHB2PHY_SOUTH_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_AHB2PHY_1_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000a004) +#define HWIO_GCC_AHB2PHY_1_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000a004) +#define HWIO_GCC_AHB2PHY_1_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000a004) +#define HWIO_GCC_AHB2PHY_1_CBCR_RMSK 0x81c0000f +#define HWIO_GCC_AHB2PHY_1_CBCR_ATTR 0x3 +#define HWIO_GCC_AHB2PHY_1_CBCR_IN \ + in_dword_masked(HWIO_GCC_AHB2PHY_1_CBCR_ADDR, HWIO_GCC_AHB2PHY_1_CBCR_RMSK) +#define HWIO_GCC_AHB2PHY_1_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_AHB2PHY_1_CBCR_ADDR, m) +#define HWIO_GCC_AHB2PHY_1_CBCR_OUT(v) \ + out_dword(HWIO_GCC_AHB2PHY_1_CBCR_ADDR,v) +#define HWIO_GCC_AHB2PHY_1_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_AHB2PHY_1_CBCR_ADDR,m,v,HWIO_GCC_AHB2PHY_1_CBCR_IN) +#define HWIO_GCC_AHB2PHY_1_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_AHB2PHY_1_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_AHB2PHY_1_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_AHB2PHY_1_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_AHB2PHY_1_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_AHB2PHY_1_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_AHB2PHY_1_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_AHB2PHY_1_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_AHB2PHY_1_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_AHB2PHY_1_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_AHB2PHY_1_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_AHB2PHY_1_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_AHB2PHY_1_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_AHB2PHY_1_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_AHB2PHY_1_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_AHB2PHY_1_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_AHB2PHY_1_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_AHB2PHY_1_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_AHB2PHY_1_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_AHB2PHY_1_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_AHB2PHY_1_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_AHB2PHY_1_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CM_PHY_REFGEN1_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00012000) +#define HWIO_GCC_CM_PHY_REFGEN1_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00012000) +#define HWIO_GCC_CM_PHY_REFGEN1_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00012000) +#define HWIO_GCC_CM_PHY_REFGEN1_BCR_RMSK 0x1 +#define HWIO_GCC_CM_PHY_REFGEN1_BCR_ATTR 0x3 +#define HWIO_GCC_CM_PHY_REFGEN1_BCR_IN \ + in_dword_masked(HWIO_GCC_CM_PHY_REFGEN1_BCR_ADDR, HWIO_GCC_CM_PHY_REFGEN1_BCR_RMSK) +#define HWIO_GCC_CM_PHY_REFGEN1_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_CM_PHY_REFGEN1_BCR_ADDR, m) +#define HWIO_GCC_CM_PHY_REFGEN1_BCR_OUT(v) \ + out_dword(HWIO_GCC_CM_PHY_REFGEN1_BCR_ADDR,v) +#define HWIO_GCC_CM_PHY_REFGEN1_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CM_PHY_REFGEN1_BCR_ADDR,m,v,HWIO_GCC_CM_PHY_REFGEN1_BCR_IN) +#define HWIO_GCC_CM_PHY_REFGEN1_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_CM_PHY_REFGEN1_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_CM_PHY_REFGEN1_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_CM_PHY_REFGEN1_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00012004) +#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00012004) +#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00012004) +#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_ATTR 0x3 +#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_IN \ + in_dword_masked(HWIO_GCC_CM_PHY_REFGEN1_CBCR_ADDR, HWIO_GCC_CM_PHY_REFGEN1_CBCR_RMSK) +#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_CM_PHY_REFGEN1_CBCR_ADDR, m) +#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_OUT(v) \ + out_dword(HWIO_GCC_CM_PHY_REFGEN1_CBCR_ADDR,v) +#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CM_PHY_REFGEN1_CBCR_ADDR,m,v,HWIO_GCC_CM_PHY_REFGEN1_CBCR_IN) +#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CM_PHY_REFGEN2_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00014000) +#define HWIO_GCC_CM_PHY_REFGEN2_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00014000) +#define HWIO_GCC_CM_PHY_REFGEN2_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00014000) +#define HWIO_GCC_CM_PHY_REFGEN2_BCR_RMSK 0x1 +#define HWIO_GCC_CM_PHY_REFGEN2_BCR_ATTR 0x3 +#define HWIO_GCC_CM_PHY_REFGEN2_BCR_IN \ + in_dword_masked(HWIO_GCC_CM_PHY_REFGEN2_BCR_ADDR, HWIO_GCC_CM_PHY_REFGEN2_BCR_RMSK) +#define HWIO_GCC_CM_PHY_REFGEN2_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_CM_PHY_REFGEN2_BCR_ADDR, m) +#define HWIO_GCC_CM_PHY_REFGEN2_BCR_OUT(v) \ + out_dword(HWIO_GCC_CM_PHY_REFGEN2_BCR_ADDR,v) +#define HWIO_GCC_CM_PHY_REFGEN2_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CM_PHY_REFGEN2_BCR_ADDR,m,v,HWIO_GCC_CM_PHY_REFGEN2_BCR_IN) +#define HWIO_GCC_CM_PHY_REFGEN2_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_CM_PHY_REFGEN2_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_CM_PHY_REFGEN2_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_CM_PHY_REFGEN2_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CM_PHY_REFGEN2_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00014004) +#define HWIO_GCC_CM_PHY_REFGEN2_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00014004) +#define HWIO_GCC_CM_PHY_REFGEN2_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00014004) +#define HWIO_GCC_CM_PHY_REFGEN2_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_CM_PHY_REFGEN2_CBCR_ATTR 0x3 +#define HWIO_GCC_CM_PHY_REFGEN2_CBCR_IN \ + in_dword_masked(HWIO_GCC_CM_PHY_REFGEN2_CBCR_ADDR, HWIO_GCC_CM_PHY_REFGEN2_CBCR_RMSK) +#define HWIO_GCC_CM_PHY_REFGEN2_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_CM_PHY_REFGEN2_CBCR_ADDR, m) +#define HWIO_GCC_CM_PHY_REFGEN2_CBCR_OUT(v) \ + out_dword(HWIO_GCC_CM_PHY_REFGEN2_CBCR_ADDR,v) +#define HWIO_GCC_CM_PHY_REFGEN2_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CM_PHY_REFGEN2_CBCR_ADDR,m,v,HWIO_GCC_CM_PHY_REFGEN2_CBCR_IN) +#define HWIO_GCC_CM_PHY_REFGEN2_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_CM_PHY_REFGEN2_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_CM_PHY_REFGEN2_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_CM_PHY_REFGEN2_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_CM_PHY_REFGEN2_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_CM_PHY_REFGEN2_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_CM_PHY_REFGEN2_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_CM_PHY_REFGEN2_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_CM_PHY_REFGEN2_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_CM_PHY_REFGEN2_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_CM_PHY_REFGEN2_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_CM_PHY_REFGEN2_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_CM_PHY_REFGEN2_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_CM_PHY_REFGEN2_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_CM_PHY_REFGEN2_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CM_PHY_REFGEN2_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QSPI_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003b000) +#define HWIO_GCC_QSPI_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003b000) +#define HWIO_GCC_QSPI_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003b000) +#define HWIO_GCC_QSPI_BCR_RMSK 0x1 +#define HWIO_GCC_QSPI_BCR_ATTR 0x3 +#define HWIO_GCC_QSPI_BCR_IN \ + in_dword_masked(HWIO_GCC_QSPI_BCR_ADDR, HWIO_GCC_QSPI_BCR_RMSK) +#define HWIO_GCC_QSPI_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_QSPI_BCR_ADDR, m) +#define HWIO_GCC_QSPI_BCR_OUT(v) \ + out_dword(HWIO_GCC_QSPI_BCR_ADDR,v) +#define HWIO_GCC_QSPI_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QSPI_BCR_ADDR,m,v,HWIO_GCC_QSPI_BCR_IN) +#define HWIO_GCC_QSPI_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_QSPI_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_QSPI_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_QSPI_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003b004) +#define HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003b004) +#define HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003b004) +#define HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_ADDR, HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_RMSK) +#define HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_ADDR, m) +#define HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_ADDR,v) +#define HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_ADDR,m,v,HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_IN) +#define HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QSPI_CORE_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003b008) +#define HWIO_GCC_QSPI_CORE_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003b008) +#define HWIO_GCC_QSPI_CORE_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003b008) +#define HWIO_GCC_QSPI_CORE_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_QSPI_CORE_CBCR_ATTR 0x3 +#define HWIO_GCC_QSPI_CORE_CBCR_IN \ + in_dword_masked(HWIO_GCC_QSPI_CORE_CBCR_ADDR, HWIO_GCC_QSPI_CORE_CBCR_RMSK) +#define HWIO_GCC_QSPI_CORE_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_QSPI_CORE_CBCR_ADDR, m) +#define HWIO_GCC_QSPI_CORE_CBCR_OUT(v) \ + out_dword(HWIO_GCC_QSPI_CORE_CBCR_ADDR,v) +#define HWIO_GCC_QSPI_CORE_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QSPI_CORE_CBCR_ADDR,m,v,HWIO_GCC_QSPI_CORE_CBCR_IN) +#define HWIO_GCC_QSPI_CORE_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_QSPI_CORE_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_QSPI_CORE_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_QSPI_CORE_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_QSPI_CORE_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_QSPI_CORE_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_QSPI_CORE_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_QSPI_CORE_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_QSPI_CORE_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_QSPI_CORE_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_QSPI_CORE_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_QSPI_CORE_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_QSPI_CORE_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_QSPI_CORE_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_QSPI_CORE_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QSPI_CORE_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QSPI_CORE_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003b00c) +#define HWIO_GCC_QSPI_CORE_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003b00c) +#define HWIO_GCC_QSPI_CORE_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003b00c) +#define HWIO_GCC_QSPI_CORE_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_QSPI_CORE_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_QSPI_CORE_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_QSPI_CORE_CMD_RCGR_ADDR, HWIO_GCC_QSPI_CORE_CMD_RCGR_RMSK) +#define HWIO_GCC_QSPI_CORE_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QSPI_CORE_CMD_RCGR_ADDR, m) +#define HWIO_GCC_QSPI_CORE_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QSPI_CORE_CMD_RCGR_ADDR,v) +#define HWIO_GCC_QSPI_CORE_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QSPI_CORE_CMD_RCGR_ADDR,m,v,HWIO_GCC_QSPI_CORE_CMD_RCGR_IN) +#define HWIO_GCC_QSPI_CORE_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_QSPI_CORE_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_QSPI_CORE_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_QSPI_CORE_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_QSPI_CORE_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_QSPI_CORE_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_QSPI_CORE_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_QSPI_CORE_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_QSPI_CORE_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_QSPI_CORE_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_QSPI_CORE_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_QSPI_CORE_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003b010) +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003b010) +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003b010) +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_QSPI_CORE_CFG_RCGR_ADDR, HWIO_GCC_QSPI_CORE_CFG_RCGR_RMSK) +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_QSPI_CORE_CFG_RCGR_ADDR, m) +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_QSPI_CORE_CFG_RCGR_ADDR,v) +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_QSPI_CORE_CFG_RCGR_ADDR,m,v,HWIO_GCC_QSPI_CORE_CFG_RCGR_IN) +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_RBCPR_MMCX_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00010000) +#define HWIO_GCC_RBCPR_MMCX_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00010000) +#define HWIO_GCC_RBCPR_MMCX_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00010000) +#define HWIO_GCC_RBCPR_MMCX_BCR_RMSK 0x1 +#define HWIO_GCC_RBCPR_MMCX_BCR_ATTR 0x3 +#define HWIO_GCC_RBCPR_MMCX_BCR_IN \ + in_dword_masked(HWIO_GCC_RBCPR_MMCX_BCR_ADDR, HWIO_GCC_RBCPR_MMCX_BCR_RMSK) +#define HWIO_GCC_RBCPR_MMCX_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_RBCPR_MMCX_BCR_ADDR, m) +#define HWIO_GCC_RBCPR_MMCX_BCR_OUT(v) \ + out_dword(HWIO_GCC_RBCPR_MMCX_BCR_ADDR,v) +#define HWIO_GCC_RBCPR_MMCX_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RBCPR_MMCX_BCR_ADDR,m,v,HWIO_GCC_RBCPR_MMCX_BCR_IN) +#define HWIO_GCC_RBCPR_MMCX_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_RBCPR_MMCX_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_RBCPR_MMCX_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_RBCPR_MMCX_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RBCPR_MMCX_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00010004) +#define HWIO_GCC_RBCPR_MMCX_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00010004) +#define HWIO_GCC_RBCPR_MMCX_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00010004) +#define HWIO_GCC_RBCPR_MMCX_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_RBCPR_MMCX_CBCR_ATTR 0x3 +#define HWIO_GCC_RBCPR_MMCX_CBCR_IN \ + in_dword_masked(HWIO_GCC_RBCPR_MMCX_CBCR_ADDR, HWIO_GCC_RBCPR_MMCX_CBCR_RMSK) +#define HWIO_GCC_RBCPR_MMCX_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_RBCPR_MMCX_CBCR_ADDR, m) +#define HWIO_GCC_RBCPR_MMCX_CBCR_OUT(v) \ + out_dword(HWIO_GCC_RBCPR_MMCX_CBCR_ADDR,v) +#define HWIO_GCC_RBCPR_MMCX_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RBCPR_MMCX_CBCR_ADDR,m,v,HWIO_GCC_RBCPR_MMCX_CBCR_IN) +#define HWIO_GCC_RBCPR_MMCX_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_RBCPR_MMCX_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_RBCPR_MMCX_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_RBCPR_MMCX_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_RBCPR_MMCX_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_RBCPR_MMCX_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_RBCPR_MMCX_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_RBCPR_MMCX_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_RBCPR_MMCX_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_RBCPR_MMCX_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_RBCPR_MMCX_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_RBCPR_MMCX_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_RBCPR_MMCX_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_RBCPR_MMCX_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_RBCPR_MMCX_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_RBCPR_MMCX_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RBCPR_MMCX_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00010008) +#define HWIO_GCC_RBCPR_MMCX_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00010008) +#define HWIO_GCC_RBCPR_MMCX_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00010008) +#define HWIO_GCC_RBCPR_MMCX_AHB_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_RBCPR_MMCX_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_RBCPR_MMCX_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_RBCPR_MMCX_AHB_CBCR_ADDR, HWIO_GCC_RBCPR_MMCX_AHB_CBCR_RMSK) +#define HWIO_GCC_RBCPR_MMCX_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_RBCPR_MMCX_AHB_CBCR_ADDR, m) +#define HWIO_GCC_RBCPR_MMCX_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_RBCPR_MMCX_AHB_CBCR_ADDR,v) +#define HWIO_GCC_RBCPR_MMCX_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RBCPR_MMCX_AHB_CBCR_ADDR,m,v,HWIO_GCC_RBCPR_MMCX_AHB_CBCR_IN) +#define HWIO_GCC_RBCPR_MMCX_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_RBCPR_MMCX_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_RBCPR_MMCX_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_RBCPR_MMCX_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_RBCPR_MMCX_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_RBCPR_MMCX_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_RBCPR_MMCX_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_RBCPR_MMCX_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_RBCPR_MMCX_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_RBCPR_MMCX_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_RBCPR_MMCX_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_RBCPR_MMCX_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_RBCPR_MMCX_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_RBCPR_MMCX_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_RBCPR_MMCX_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_RBCPR_MMCX_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_RBCPR_MMCX_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_RBCPR_MMCX_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_RBCPR_MMCX_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_RBCPR_MMCX_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_RBCPR_MMCX_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_RBCPR_MMCX_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_RBCPR_MMCX_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_RBCPR_MMCX_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RBCPR_MMCX_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001000c) +#define HWIO_GCC_RBCPR_MMCX_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001000c) +#define HWIO_GCC_RBCPR_MMCX_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001000c) +#define HWIO_GCC_RBCPR_MMCX_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_RBCPR_MMCX_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_RBCPR_MMCX_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_RBCPR_MMCX_CMD_RCGR_ADDR, HWIO_GCC_RBCPR_MMCX_CMD_RCGR_RMSK) +#define HWIO_GCC_RBCPR_MMCX_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_RBCPR_MMCX_CMD_RCGR_ADDR, m) +#define HWIO_GCC_RBCPR_MMCX_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_RBCPR_MMCX_CMD_RCGR_ADDR,v) +#define HWIO_GCC_RBCPR_MMCX_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RBCPR_MMCX_CMD_RCGR_ADDR,m,v,HWIO_GCC_RBCPR_MMCX_CMD_RCGR_IN) +#define HWIO_GCC_RBCPR_MMCX_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_RBCPR_MMCX_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_RBCPR_MMCX_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_RBCPR_MMCX_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_RBCPR_MMCX_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_RBCPR_MMCX_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_RBCPR_MMCX_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_RBCPR_MMCX_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_RBCPR_MMCX_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_RBCPR_MMCX_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_RBCPR_MMCX_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_RBCPR_MMCX_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00010010) +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00010010) +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00010010) +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_RBCPR_MMCX_CFG_RCGR_ADDR, HWIO_GCC_RBCPR_MMCX_CFG_RCGR_RMSK) +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_RBCPR_MMCX_CFG_RCGR_ADDR, m) +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_RBCPR_MMCX_CFG_RCGR_ADDR,v) +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RBCPR_MMCX_CFG_RCGR_ADDR,m,v,HWIO_GCC_RBCPR_MMCX_CFG_RCGR_IN) +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_IPCC_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00015000) +#define HWIO_GCC_IPCC_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00015000) +#define HWIO_GCC_IPCC_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00015000) +#define HWIO_GCC_IPCC_BCR_RMSK 0x1 +#define HWIO_GCC_IPCC_BCR_ATTR 0x3 +#define HWIO_GCC_IPCC_BCR_IN \ + in_dword_masked(HWIO_GCC_IPCC_BCR_ADDR, HWIO_GCC_IPCC_BCR_RMSK) +#define HWIO_GCC_IPCC_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_IPCC_BCR_ADDR, m) +#define HWIO_GCC_IPCC_BCR_OUT(v) \ + out_dword(HWIO_GCC_IPCC_BCR_ADDR,v) +#define HWIO_GCC_IPCC_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_IPCC_BCR_ADDR,m,v,HWIO_GCC_IPCC_BCR_IN) +#define HWIO_GCC_IPCC_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_IPCC_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_IPCC_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPCC_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_IPCC_CORE_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00015004) +#define HWIO_GCC_IPCC_CORE_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00015004) +#define HWIO_GCC_IPCC_CORE_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00015004) +#define HWIO_GCC_IPCC_CORE_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_IPCC_CORE_CBCR_ATTR 0x3 +#define HWIO_GCC_IPCC_CORE_CBCR_IN \ + in_dword_masked(HWIO_GCC_IPCC_CORE_CBCR_ADDR, HWIO_GCC_IPCC_CORE_CBCR_RMSK) +#define HWIO_GCC_IPCC_CORE_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_IPCC_CORE_CBCR_ADDR, m) +#define HWIO_GCC_IPCC_CORE_CBCR_OUT(v) \ + out_dword(HWIO_GCC_IPCC_CORE_CBCR_ADDR,v) +#define HWIO_GCC_IPCC_CORE_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_IPCC_CORE_CBCR_ADDR,m,v,HWIO_GCC_IPCC_CORE_CBCR_IN) +#define HWIO_GCC_IPCC_CORE_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_IPCC_CORE_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_IPCC_CORE_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_IPCC_CORE_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_IPCC_CORE_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_IPCC_CORE_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_IPCC_CORE_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_IPCC_CORE_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_IPCC_CORE_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_IPCC_CORE_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_IPCC_CORE_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_IPCC_CORE_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_IPCC_CORE_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_IPCC_CORE_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_IPCC_CORE_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPCC_CORE_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_IPCC_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00015008) +#define HWIO_GCC_IPCC_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00015008) +#define HWIO_GCC_IPCC_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00015008) +#define HWIO_GCC_IPCC_AHB_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_IPCC_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_IPCC_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_IPCC_AHB_CBCR_ADDR, HWIO_GCC_IPCC_AHB_CBCR_RMSK) +#define HWIO_GCC_IPCC_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_IPCC_AHB_CBCR_ADDR, m) +#define HWIO_GCC_IPCC_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_IPCC_AHB_CBCR_ADDR,v) +#define HWIO_GCC_IPCC_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_IPCC_AHB_CBCR_ADDR,m,v,HWIO_GCC_IPCC_AHB_CBCR_IN) +#define HWIO_GCC_IPCC_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_IPCC_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_IPCC_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_IPCC_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_IPCC_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_IPCC_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_IPCC_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_IPCC_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_IPCC_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_IPCC_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_IPCC_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_IPCC_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_IPCC_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_IPCC_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_IPCC_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_IPCC_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_IPCC_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_IPCC_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_IPCC_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPCC_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPCC_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_IPCC_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_IPCC_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPCC_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_IPCC_CORE_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001500c) +#define HWIO_GCC_IPCC_CORE_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001500c) +#define HWIO_GCC_IPCC_CORE_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001500c) +#define HWIO_GCC_IPCC_CORE_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_IPCC_CORE_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_IPCC_CORE_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_IPCC_CORE_CMD_RCGR_ADDR, HWIO_GCC_IPCC_CORE_CMD_RCGR_RMSK) +#define HWIO_GCC_IPCC_CORE_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_IPCC_CORE_CMD_RCGR_ADDR, m) +#define HWIO_GCC_IPCC_CORE_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_IPCC_CORE_CMD_RCGR_ADDR,v) +#define HWIO_GCC_IPCC_CORE_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_IPCC_CORE_CMD_RCGR_ADDR,m,v,HWIO_GCC_IPCC_CORE_CMD_RCGR_IN) +#define HWIO_GCC_IPCC_CORE_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_IPCC_CORE_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_IPCC_CORE_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_IPCC_CORE_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_IPCC_CORE_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_IPCC_CORE_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_IPCC_CORE_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPCC_CORE_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPCC_CORE_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_IPCC_CORE_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_IPCC_CORE_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPCC_CORE_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_IPCC_CORE_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00015010) +#define HWIO_GCC_IPCC_CORE_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00015010) +#define HWIO_GCC_IPCC_CORE_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00015010) +#define HWIO_GCC_IPCC_CORE_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_IPCC_CORE_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_IPCC_CORE_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_IPCC_CORE_CFG_RCGR_ADDR, HWIO_GCC_IPCC_CORE_CFG_RCGR_RMSK) +#define HWIO_GCC_IPCC_CORE_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_IPCC_CORE_CFG_RCGR_ADDR, m) +#define HWIO_GCC_IPCC_CORE_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_IPCC_CORE_CFG_RCGR_ADDR,v) +#define HWIO_GCC_IPCC_CORE_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_IPCC_CORE_CFG_RCGR_ADDR,m,v,HWIO_GCC_IPCC_CORE_CFG_RCGR_IN) +#define HWIO_GCC_IPCC_CORE_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_IPCC_CORE_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_IPCC_CORE_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPCC_CORE_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPCC_CORE_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_IPCC_CORE_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_IPCC_CORE_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_IPCC_CORE_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_IPCC_CORE_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_IPCC_CORE_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_IPCC_CORE_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_IPCC_CORE_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_IPCC_CORE_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_IPCC_CORE_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_IPCC_CORE_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_IPCC_CORE_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_IPCC_CORE_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_IPCC_CORE_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_IPCC_CORE_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_IPCC_CORE_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_IPCC_CORE_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_IPCC_CORE_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_IPCC_CORE_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_IPCC_CORE_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_IPCC_CORE_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_IPCC_CORE_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_IPCC_CORE_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_IPCC_CORE_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_IPCC_CORE_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_IPCC_CORE_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_IPCC_CORE_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_IPCC_CORE_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_IPCC_CORE_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_IPCC_CORE_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_IPCC_CORE_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_IPCC_CORE_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_IPCC_CORE_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_IPCC_CORE_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_IPCC_CORE_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_IPCC_CORE_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_IPCC_CORE_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_IPCC_CORE_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_IPCC_CORE_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_IPCC_CORE_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_IPCC_CORE_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_IPCC_CORE_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_IPCC_CORE_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_IPCC_CORE_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_IPCC_CORE_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_IPCC_CORE_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_IPCC_CORE_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_IPCC_CORE_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_DPM_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00036000) +#define HWIO_GCC_DPM_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00036000) +#define HWIO_GCC_DPM_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00036000) +#define HWIO_GCC_DPM_BCR_RMSK 0x1 +#define HWIO_GCC_DPM_BCR_ATTR 0x3 +#define HWIO_GCC_DPM_BCR_IN \ + in_dword_masked(HWIO_GCC_DPM_BCR_ADDR, HWIO_GCC_DPM_BCR_RMSK) +#define HWIO_GCC_DPM_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_DPM_BCR_ADDR, m) +#define HWIO_GCC_DPM_BCR_OUT(v) \ + out_dword(HWIO_GCC_DPM_BCR_ADDR,v) +#define HWIO_GCC_DPM_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DPM_BCR_ADDR,m,v,HWIO_GCC_DPM_BCR_IN) +#define HWIO_GCC_DPM_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_DPM_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_DPM_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_DPM_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_DPM_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00036004) +#define HWIO_GCC_DPM_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00036004) +#define HWIO_GCC_DPM_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00036004) +#define HWIO_GCC_DPM_CBCR_RMSK 0x81c0000f +#define HWIO_GCC_DPM_CBCR_ATTR 0x3 +#define HWIO_GCC_DPM_CBCR_IN \ + in_dword_masked(HWIO_GCC_DPM_CBCR_ADDR, HWIO_GCC_DPM_CBCR_RMSK) +#define HWIO_GCC_DPM_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_DPM_CBCR_ADDR, m) +#define HWIO_GCC_DPM_CBCR_OUT(v) \ + out_dword(HWIO_GCC_DPM_CBCR_ADDR,v) +#define HWIO_GCC_DPM_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DPM_CBCR_ADDR,m,v,HWIO_GCC_DPM_CBCR_IN) +#define HWIO_GCC_DPM_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_DPM_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_DPM_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_DPM_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_DPM_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_DPM_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_DPM_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_DPM_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_DPM_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_DPM_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_DPM_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_DPM_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_DPM_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_DPM_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_DPM_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_DPM_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_DPM_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_DPM_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_DPM_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_DPM_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_DPM_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DPM_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_DPM_CX_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00036008) +#define HWIO_GCC_DPM_CX_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00036008) +#define HWIO_GCC_DPM_CX_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00036008) +#define HWIO_GCC_DPM_CX_AHB_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_DPM_CX_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_DPM_CX_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_DPM_CX_AHB_CBCR_ADDR, HWIO_GCC_DPM_CX_AHB_CBCR_RMSK) +#define HWIO_GCC_DPM_CX_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_DPM_CX_AHB_CBCR_ADDR, m) +#define HWIO_GCC_DPM_CX_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_DPM_CX_AHB_CBCR_ADDR,v) +#define HWIO_GCC_DPM_CX_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DPM_CX_AHB_CBCR_ADDR,m,v,HWIO_GCC_DPM_CX_AHB_CBCR_IN) +#define HWIO_GCC_DPM_CX_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_DPM_CX_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_DPM_CX_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_DPM_CX_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_DPM_CX_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_DPM_CX_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_DPM_CX_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_DPM_CX_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_DPM_CX_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_DPM_CX_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_DPM_CX_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_DPM_CX_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_DPM_CX_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_DPM_CX_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_DPM_CX_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_DPM_CX_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_DPM_CX_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_DPM_CX_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_DPM_CX_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_DPM_CX_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_DPM_CX_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_DPM_CX_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_DPM_CX_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DPM_CX_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_DPM_MX_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003600c) +#define HWIO_GCC_DPM_MX_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003600c) +#define HWIO_GCC_DPM_MX_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003600c) +#define HWIO_GCC_DPM_MX_AHB_CBCR_RMSK 0x81d0000f +#define HWIO_GCC_DPM_MX_AHB_CBCR_ATTR 0x3 +#define HWIO_GCC_DPM_MX_AHB_CBCR_IN \ + in_dword_masked(HWIO_GCC_DPM_MX_AHB_CBCR_ADDR, HWIO_GCC_DPM_MX_AHB_CBCR_RMSK) +#define HWIO_GCC_DPM_MX_AHB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_DPM_MX_AHB_CBCR_ADDR, m) +#define HWIO_GCC_DPM_MX_AHB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_DPM_MX_AHB_CBCR_ADDR,v) +#define HWIO_GCC_DPM_MX_AHB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DPM_MX_AHB_CBCR_ADDR,m,v,HWIO_GCC_DPM_MX_AHB_CBCR_IN) +#define HWIO_GCC_DPM_MX_AHB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_DPM_MX_AHB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_DPM_MX_AHB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_DPM_MX_AHB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_DPM_MX_AHB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_DPM_MX_AHB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_DPM_MX_AHB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_DPM_MX_AHB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_DPM_MX_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK 0x100000 +#define HWIO_GCC_DPM_MX_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT 0x14 +#define HWIO_GCC_DPM_MX_AHB_CBCR_SW_ONLY_EN_BMSK 0x8 +#define HWIO_GCC_DPM_MX_AHB_CBCR_SW_ONLY_EN_SHFT 0x3 +#define HWIO_GCC_DPM_MX_AHB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_DPM_MX_AHB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_DPM_MX_AHB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_DPM_MX_AHB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_DPM_MX_AHB_CBCR_HW_CTL_BMSK 0x2 +#define HWIO_GCC_DPM_MX_AHB_CBCR_HW_CTL_SHFT 0x1 +#define HWIO_GCC_DPM_MX_AHB_CBCR_HW_CTL_DISABLE_FVAL 0x0 +#define HWIO_GCC_DPM_MX_AHB_CBCR_HW_CTL_ENABLE_FVAL 0x1 +#define HWIO_GCC_DPM_MX_AHB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_DPM_MX_AHB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_DPM_MX_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DPM_MX_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_DPM_CB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00036010) +#define HWIO_GCC_DPM_CB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00036010) +#define HWIO_GCC_DPM_CB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00036010) +#define HWIO_GCC_DPM_CB_CBCR_RMSK 0x81c00005 +#define HWIO_GCC_DPM_CB_CBCR_ATTR 0x3 +#define HWIO_GCC_DPM_CB_CBCR_IN \ + in_dword_masked(HWIO_GCC_DPM_CB_CBCR_ADDR, HWIO_GCC_DPM_CB_CBCR_RMSK) +#define HWIO_GCC_DPM_CB_CBCR_INM(m) \ + in_dword_masked(HWIO_GCC_DPM_CB_CBCR_ADDR, m) +#define HWIO_GCC_DPM_CB_CBCR_OUT(v) \ + out_dword(HWIO_GCC_DPM_CB_CBCR_ADDR,v) +#define HWIO_GCC_DPM_CB_CBCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DPM_CB_CBCR_ADDR,m,v,HWIO_GCC_DPM_CB_CBCR_IN) +#define HWIO_GCC_DPM_CB_CBCR_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_DPM_CB_CBCR_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_DPM_CB_CBCR_IGNORE_ALL_ARES_BMSK 0x1000000 +#define HWIO_GCC_DPM_CB_CBCR_IGNORE_ALL_ARES_SHFT 0x18 +#define HWIO_GCC_DPM_CB_CBCR_IGNORE_ALL_CLK_DIS_BMSK 0x800000 +#define HWIO_GCC_DPM_CB_CBCR_IGNORE_ALL_CLK_DIS_SHFT 0x17 +#define HWIO_GCC_DPM_CB_CBCR_CLK_DIS_BMSK 0x400000 +#define HWIO_GCC_DPM_CB_CBCR_CLK_DIS_SHFT 0x16 +#define HWIO_GCC_DPM_CB_CBCR_CLK_ARES_BMSK 0x4 +#define HWIO_GCC_DPM_CB_CBCR_CLK_ARES_SHFT 0x2 +#define HWIO_GCC_DPM_CB_CBCR_CLK_ARES_NO_RESET_FVAL 0x0 +#define HWIO_GCC_DPM_CB_CBCR_CLK_ARES_RESET_FVAL 0x1 +#define HWIO_GCC_DPM_CB_CBCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_DPM_CB_CBCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_DPM_CB_CBCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DPM_CB_CBCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_DPM_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00036014) +#define HWIO_GCC_DPM_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00036014) +#define HWIO_GCC_DPM_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00036014) +#define HWIO_GCC_DPM_CMD_RCGR_RMSK 0x80000013 +#define HWIO_GCC_DPM_CMD_RCGR_ATTR 0x3 +#define HWIO_GCC_DPM_CMD_RCGR_IN \ + in_dword_masked(HWIO_GCC_DPM_CMD_RCGR_ADDR, HWIO_GCC_DPM_CMD_RCGR_RMSK) +#define HWIO_GCC_DPM_CMD_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_DPM_CMD_RCGR_ADDR, m) +#define HWIO_GCC_DPM_CMD_RCGR_OUT(v) \ + out_dword(HWIO_GCC_DPM_CMD_RCGR_ADDR,v) +#define HWIO_GCC_DPM_CMD_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DPM_CMD_RCGR_ADDR,m,v,HWIO_GCC_DPM_CMD_RCGR_IN) +#define HWIO_GCC_DPM_CMD_RCGR_ROOT_OFF_BMSK 0x80000000 +#define HWIO_GCC_DPM_CMD_RCGR_ROOT_OFF_SHFT 0x1f +#define HWIO_GCC_DPM_CMD_RCGR_DIRTY_CFG_RCGR_BMSK 0x10 +#define HWIO_GCC_DPM_CMD_RCGR_DIRTY_CFG_RCGR_SHFT 0x4 +#define HWIO_GCC_DPM_CMD_RCGR_ROOT_EN_BMSK 0x2 +#define HWIO_GCC_DPM_CMD_RCGR_ROOT_EN_SHFT 0x1 +#define HWIO_GCC_DPM_CMD_RCGR_ROOT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_DPM_CMD_RCGR_ROOT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_DPM_CMD_RCGR_UPDATE_BMSK 0x1 +#define HWIO_GCC_DPM_CMD_RCGR_UPDATE_SHFT 0x0 +#define HWIO_GCC_DPM_CMD_RCGR_UPDATE_DISABLE_FVAL 0x0 +#define HWIO_GCC_DPM_CMD_RCGR_UPDATE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_DPM_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00036018) +#define HWIO_GCC_DPM_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00036018) +#define HWIO_GCC_DPM_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00036018) +#define HWIO_GCC_DPM_CFG_RCGR_RMSK 0x11071f +#define HWIO_GCC_DPM_CFG_RCGR_ATTR 0x3 +#define HWIO_GCC_DPM_CFG_RCGR_IN \ + in_dword_masked(HWIO_GCC_DPM_CFG_RCGR_ADDR, HWIO_GCC_DPM_CFG_RCGR_RMSK) +#define HWIO_GCC_DPM_CFG_RCGR_INM(m) \ + in_dword_masked(HWIO_GCC_DPM_CFG_RCGR_ADDR, m) +#define HWIO_GCC_DPM_CFG_RCGR_OUT(v) \ + out_dword(HWIO_GCC_DPM_CFG_RCGR_ADDR,v) +#define HWIO_GCC_DPM_CFG_RCGR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DPM_CFG_RCGR_ADDR,m,v,HWIO_GCC_DPM_CFG_RCGR_IN) +#define HWIO_GCC_DPM_CFG_RCGR_HW_CLK_CONTROL_BMSK 0x100000 +#define HWIO_GCC_DPM_CFG_RCGR_HW_CLK_CONTROL_SHFT 0x14 +#define HWIO_GCC_DPM_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL 0x0 +#define HWIO_GCC_DPM_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL 0x1 +#define HWIO_GCC_DPM_CFG_RCGR_RCGLITE_DISABLE_BMSK 0x10000 +#define HWIO_GCC_DPM_CFG_RCGR_RCGLITE_DISABLE_SHFT 0x10 +#define HWIO_GCC_DPM_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL 0x0 +#define HWIO_GCC_DPM_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL 0x1 +#define HWIO_GCC_DPM_CFG_RCGR_SRC_SEL_BMSK 0x700 +#define HWIO_GCC_DPM_CFG_RCGR_SRC_SEL_SHFT 0x8 +#define HWIO_GCC_DPM_CFG_RCGR_SRC_SEL_SRC0_FVAL 0x0 +#define HWIO_GCC_DPM_CFG_RCGR_SRC_SEL_SRC1_FVAL 0x1 +#define HWIO_GCC_DPM_CFG_RCGR_SRC_SEL_SRC2_FVAL 0x2 +#define HWIO_GCC_DPM_CFG_RCGR_SRC_SEL_SRC3_FVAL 0x3 +#define HWIO_GCC_DPM_CFG_RCGR_SRC_SEL_SRC4_FVAL 0x4 +#define HWIO_GCC_DPM_CFG_RCGR_SRC_SEL_SRC5_FVAL 0x5 +#define HWIO_GCC_DPM_CFG_RCGR_SRC_SEL_SRC6_FVAL 0x6 +#define HWIO_GCC_DPM_CFG_RCGR_SRC_SEL_SRC7_FVAL 0x7 +#define HWIO_GCC_DPM_CFG_RCGR_SRC_DIV_BMSK 0x1f +#define HWIO_GCC_DPM_CFG_RCGR_SRC_DIV_SHFT 0x0 +#define HWIO_GCC_DPM_CFG_RCGR_SRC_DIV_BYPASS_FVAL 0x0 +#define HWIO_GCC_DPM_CFG_RCGR_SRC_DIV_DIV1_FVAL 0x1 +#define HWIO_GCC_DPM_CFG_RCGR_SRC_DIV_DIV1_5_FVAL 0x2 +#define HWIO_GCC_DPM_CFG_RCGR_SRC_DIV_DIV2_FVAL 0x3 +#define HWIO_GCC_DPM_CFG_RCGR_SRC_DIV_DIV2_5_FVAL 0x4 +#define HWIO_GCC_DPM_CFG_RCGR_SRC_DIV_DIV3_FVAL 0x5 +#define HWIO_GCC_DPM_CFG_RCGR_SRC_DIV_DIV3_5_FVAL 0x6 +#define HWIO_GCC_DPM_CFG_RCGR_SRC_DIV_DIV4_FVAL 0x7 +#define HWIO_GCC_DPM_CFG_RCGR_SRC_DIV_DIV4_5_FVAL 0x8 +#define HWIO_GCC_DPM_CFG_RCGR_SRC_DIV_DIV5_FVAL 0x9 +#define HWIO_GCC_DPM_CFG_RCGR_SRC_DIV_DIV5_5_FVAL 0xa +#define HWIO_GCC_DPM_CFG_RCGR_SRC_DIV_DIV6_FVAL 0xb +#define HWIO_GCC_DPM_CFG_RCGR_SRC_DIV_DIV6_5_FVAL 0xc +#define HWIO_GCC_DPM_CFG_RCGR_SRC_DIV_DIV7_FVAL 0xd +#define HWIO_GCC_DPM_CFG_RCGR_SRC_DIV_DIV7_5_FVAL 0xe +#define HWIO_GCC_DPM_CFG_RCGR_SRC_DIV_DIV8_FVAL 0xf +#define HWIO_GCC_DPM_CFG_RCGR_SRC_DIV_DIV8_5_FVAL 0x10 +#define HWIO_GCC_DPM_CFG_RCGR_SRC_DIV_DIV9_FVAL 0x11 +#define HWIO_GCC_DPM_CFG_RCGR_SRC_DIV_DIV9_5_FVAL 0x12 +#define HWIO_GCC_DPM_CFG_RCGR_SRC_DIV_DIV10_FVAL 0x13 +#define HWIO_GCC_DPM_CFG_RCGR_SRC_DIV_DIV10_5_FVAL 0x14 +#define HWIO_GCC_DPM_CFG_RCGR_SRC_DIV_DIV11_FVAL 0x15 +#define HWIO_GCC_DPM_CFG_RCGR_SRC_DIV_DIV11_5_FVAL 0x16 +#define HWIO_GCC_DPM_CFG_RCGR_SRC_DIV_DIV12_FVAL 0x17 +#define HWIO_GCC_DPM_CFG_RCGR_SRC_DIV_DIV12_5_FVAL 0x18 +#define HWIO_GCC_DPM_CFG_RCGR_SRC_DIV_DIV13_FVAL 0x19 +#define HWIO_GCC_DPM_CFG_RCGR_SRC_DIV_DIV13_5_FVAL 0x1a +#define HWIO_GCC_DPM_CFG_RCGR_SRC_DIV_DIV14_FVAL 0x1b +#define HWIO_GCC_DPM_CFG_RCGR_SRC_DIV_DIV14_5_FVAL 0x1c +#define HWIO_GCC_DPM_CFG_RCGR_SRC_DIV_DIV15_FVAL 0x1d +#define HWIO_GCC_DPM_CFG_RCGR_SRC_DIV_DIV15_5_FVAL 0x1e +#define HWIO_GCC_DPM_CFG_RCGR_SRC_DIV_DIV16_FVAL 0x1f + +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00018004) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018004) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018004) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_RMSK 0x80000001 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_ATTR 0x3 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_IN \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_ADDR, HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_RMSK) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_INM(m) \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_ADDR, m) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_OUT(v) \ + out_dword(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_ADDR,v) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_IN) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK 0x80000000 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT 0x1f +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00018008) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018008) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018008) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_RMSK 0x80000001 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_ATTR 0x3 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_IN \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_ADDR, HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_RMSK) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_INM(m) \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_ADDR, m) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_OUT(v) \ + out_dword(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_ADDR,v) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_IN) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK 0x80000000 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT 0x1f +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001800c) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001800c) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001800c) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_RMSK 0x80000001 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_ATTR 0x3 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_IN \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_ADDR, HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_RMSK) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_INM(m) \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_ADDR, m) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_OUT(v) \ + out_dword(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_ADDR,v) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_IN) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK 0x80000000 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT 0x1f +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00018010) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018010) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018010) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_RMSK 0x80000001 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_ATTR 0x3 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_IN \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_ADDR, HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_RMSK) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_INM(m) \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_ADDR, m) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_OUT(v) \ + out_dword(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_ADDR,v) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_IN) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK 0x80000000 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT 0x1f +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00018014) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018014) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018014) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_RMSK 0x80000001 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_ATTR 0x3 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_IN \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_ADDR, HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_RMSK) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_INM(m) \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_ADDR, m) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_OUT(v) \ + out_dword(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_ADDR,v) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_IN) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK 0x80000000 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT 0x1f +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00018018) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018018) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018018) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_RMSK 0x80000001 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_ATTR 0x3 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_IN \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_ADDR, HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_RMSK) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_INM(m) \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_ADDR, m) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_OUT(v) \ + out_dword(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_ADDR,v) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_IN) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK 0x80000000 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT 0x1f +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001801c) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001801c) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001801c) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_RMSK 0x80000001 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_ATTR 0x3 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_IN \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_ADDR, HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_RMSK) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_INM(m) \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_ADDR, m) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_OUT(v) \ + out_dword(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_ADDR,v) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_IN) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK 0x80000000 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT 0x1f +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00018020) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018020) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018020) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_RMSK 0x80000001 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_ATTR 0x3 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_IN \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_ADDR, HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_RMSK) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_INM(m) \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_ADDR, m) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_OUT(v) \ + out_dword(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_ADDR,v) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_IN) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK 0x80000000 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT 0x1f +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00018024) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018024) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018024) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_RMSK 0x80000001 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_ATTR 0x3 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_IN \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_ADDR, HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_RMSK) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_INM(m) \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_ADDR, m) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_OUT(v) \ + out_dword(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_ADDR,v) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_IN) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK 0x80000000 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT 0x1f +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00018028) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018028) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018028) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_RMSK 0x80000001 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_ATTR 0x3 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_IN \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_ADDR, HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_RMSK) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_INM(m) \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_ADDR, m) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_OUT(v) \ + out_dword(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_ADDR,v) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_IN) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK 0x80000000 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT 0x1f +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001802c) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001802c) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001802c) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_RMSK 0x80000001 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_ATTR 0x3 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_IN \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_ADDR, HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_RMSK) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_INM(m) \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_ADDR, m) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_OUT(v) \ + out_dword(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_ADDR,v) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_IN) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK 0x80000000 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT 0x1f +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00018030) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018030) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018030) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_RMSK 0x80000001 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_ATTR 0x3 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_IN \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_ADDR, HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_RMSK) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_INM(m) \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_ADDR, m) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_OUT(v) \ + out_dword(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_ADDR,v) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_IN) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK 0x80000000 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT 0x1f +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP13_CLKGEN_ACGC_ACGCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00018034) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP13_CLKGEN_ACGC_ACGCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018034) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP13_CLKGEN_ACGC_ACGCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018034) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP13_CLKGEN_ACGC_ACGCR_RMSK 0x80000001 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP13_CLKGEN_ACGC_ACGCR_ATTR 0x3 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP13_CLKGEN_ACGC_ACGCR_IN \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP13_CLKGEN_ACGC_ACGCR_ADDR, HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP13_CLKGEN_ACGC_ACGCR_RMSK) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP13_CLKGEN_ACGC_ACGCR_INM(m) \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP13_CLKGEN_ACGC_ACGCR_ADDR, m) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP13_CLKGEN_ACGC_ACGCR_OUT(v) \ + out_dword(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP13_CLKGEN_ACGC_ACGCR_ADDR,v) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP13_CLKGEN_ACGC_ACGCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP13_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP13_CLKGEN_ACGC_ACGCR_IN) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP13_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK 0x80000000 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP13_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT 0x1f +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP13_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP13_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP13_CLKGEN_ACGC_ACGCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP13_CLKGEN_ACGC_ACGCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP14_CLKGEN_ACGC_ACGCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00018038) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP14_CLKGEN_ACGC_ACGCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018038) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP14_CLKGEN_ACGC_ACGCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018038) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP14_CLKGEN_ACGC_ACGCR_RMSK 0x80000001 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP14_CLKGEN_ACGC_ACGCR_ATTR 0x3 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP14_CLKGEN_ACGC_ACGCR_IN \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP14_CLKGEN_ACGC_ACGCR_ADDR, HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP14_CLKGEN_ACGC_ACGCR_RMSK) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP14_CLKGEN_ACGC_ACGCR_INM(m) \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP14_CLKGEN_ACGC_ACGCR_ADDR, m) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP14_CLKGEN_ACGC_ACGCR_OUT(v) \ + out_dword(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP14_CLKGEN_ACGC_ACGCR_ADDR,v) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP14_CLKGEN_ACGC_ACGCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP14_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP14_CLKGEN_ACGC_ACGCR_IN) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP14_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK 0x80000000 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP14_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT 0x1f +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP14_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP14_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP14_CLKGEN_ACGC_ACGCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP14_CLKGEN_ACGC_ACGCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001803c) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001803c) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001803c) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_RMSK 0x80000001 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_ATTR 0x3 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_IN \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_ADDR, HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_RMSK) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_INM(m) \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_ADDR, m) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_OUT(v) \ + out_dword(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_ADDR,v) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_IN) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK 0x80000000 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT 0x1f +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP16_CLKGEN_ACGC_ACGCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00018040) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP16_CLKGEN_ACGC_ACGCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018040) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP16_CLKGEN_ACGC_ACGCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018040) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP16_CLKGEN_ACGC_ACGCR_RMSK 0x80000001 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP16_CLKGEN_ACGC_ACGCR_ATTR 0x3 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP16_CLKGEN_ACGC_ACGCR_IN \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP16_CLKGEN_ACGC_ACGCR_ADDR, HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP16_CLKGEN_ACGC_ACGCR_RMSK) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP16_CLKGEN_ACGC_ACGCR_INM(m) \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP16_CLKGEN_ACGC_ACGCR_ADDR, m) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP16_CLKGEN_ACGC_ACGCR_OUT(v) \ + out_dword(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP16_CLKGEN_ACGC_ACGCR_ADDR,v) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP16_CLKGEN_ACGC_ACGCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP16_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP16_CLKGEN_ACGC_ACGCR_IN) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP16_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK 0x80000000 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP16_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT 0x1f +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP16_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP16_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP16_CLKGEN_ACGC_ACGCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP16_CLKGEN_ACGC_ACGCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP17_CLKGEN_ACGC_ACGCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00018044) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP17_CLKGEN_ACGC_ACGCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018044) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP17_CLKGEN_ACGC_ACGCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018044) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP17_CLKGEN_ACGC_ACGCR_RMSK 0x80000001 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP17_CLKGEN_ACGC_ACGCR_ATTR 0x3 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP17_CLKGEN_ACGC_ACGCR_IN \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP17_CLKGEN_ACGC_ACGCR_ADDR, HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP17_CLKGEN_ACGC_ACGCR_RMSK) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP17_CLKGEN_ACGC_ACGCR_INM(m) \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP17_CLKGEN_ACGC_ACGCR_ADDR, m) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP17_CLKGEN_ACGC_ACGCR_OUT(v) \ + out_dword(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP17_CLKGEN_ACGC_ACGCR_ADDR,v) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP17_CLKGEN_ACGC_ACGCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP17_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP17_CLKGEN_ACGC_ACGCR_IN) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP17_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK 0x80000000 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP17_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT 0x1f +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP17_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP17_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP17_CLKGEN_ACGC_ACGCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP17_CLKGEN_ACGC_ACGCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP18_CLKGEN_ACGC_ACGCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00018048) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP18_CLKGEN_ACGC_ACGCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018048) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP18_CLKGEN_ACGC_ACGCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018048) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP18_CLKGEN_ACGC_ACGCR_RMSK 0x80000001 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP18_CLKGEN_ACGC_ACGCR_ATTR 0x3 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP18_CLKGEN_ACGC_ACGCR_IN \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP18_CLKGEN_ACGC_ACGCR_ADDR, HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP18_CLKGEN_ACGC_ACGCR_RMSK) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP18_CLKGEN_ACGC_ACGCR_INM(m) \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP18_CLKGEN_ACGC_ACGCR_ADDR, m) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP18_CLKGEN_ACGC_ACGCR_OUT(v) \ + out_dword(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP18_CLKGEN_ACGC_ACGCR_ADDR,v) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP18_CLKGEN_ACGC_ACGCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP18_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP18_CLKGEN_ACGC_ACGCR_IN) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP18_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK 0x80000000 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP18_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT 0x1f +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP18_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP18_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP18_CLKGEN_ACGC_ACGCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP18_CLKGEN_ACGC_ACGCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP19_CLKGEN_ACGC_ACGCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001804c) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP19_CLKGEN_ACGC_ACGCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001804c) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP19_CLKGEN_ACGC_ACGCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001804c) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP19_CLKGEN_ACGC_ACGCR_RMSK 0x80000001 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP19_CLKGEN_ACGC_ACGCR_ATTR 0x3 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP19_CLKGEN_ACGC_ACGCR_IN \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP19_CLKGEN_ACGC_ACGCR_ADDR, HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP19_CLKGEN_ACGC_ACGCR_RMSK) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP19_CLKGEN_ACGC_ACGCR_INM(m) \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP19_CLKGEN_ACGC_ACGCR_ADDR, m) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP19_CLKGEN_ACGC_ACGCR_OUT(v) \ + out_dword(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP19_CLKGEN_ACGC_ACGCR_ADDR,v) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP19_CLKGEN_ACGC_ACGCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP19_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP19_CLKGEN_ACGC_ACGCR_IN) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP19_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK 0x80000000 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP19_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT 0x1f +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP19_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP19_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP19_CLKGEN_ACGC_ACGCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP19_CLKGEN_ACGC_ACGCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP20_CLKGEN_ACGC_ACGCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00018050) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP20_CLKGEN_ACGC_ACGCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018050) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP20_CLKGEN_ACGC_ACGCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018050) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP20_CLKGEN_ACGC_ACGCR_RMSK 0x80000001 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP20_CLKGEN_ACGC_ACGCR_ATTR 0x3 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP20_CLKGEN_ACGC_ACGCR_IN \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP20_CLKGEN_ACGC_ACGCR_ADDR, HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP20_CLKGEN_ACGC_ACGCR_RMSK) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP20_CLKGEN_ACGC_ACGCR_INM(m) \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP20_CLKGEN_ACGC_ACGCR_ADDR, m) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP20_CLKGEN_ACGC_ACGCR_OUT(v) \ + out_dword(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP20_CLKGEN_ACGC_ACGCR_ADDR,v) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP20_CLKGEN_ACGC_ACGCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP20_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP20_CLKGEN_ACGC_ACGCR_IN) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP20_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK 0x80000000 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP20_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT 0x1f +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP20_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP20_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP20_CLKGEN_ACGC_ACGCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP20_CLKGEN_ACGC_ACGCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP21_CLKGEN_ACGC_ACGCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00018054) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP21_CLKGEN_ACGC_ACGCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018054) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP21_CLKGEN_ACGC_ACGCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018054) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP21_CLKGEN_ACGC_ACGCR_RMSK 0x80000001 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP21_CLKGEN_ACGC_ACGCR_ATTR 0x3 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP21_CLKGEN_ACGC_ACGCR_IN \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP21_CLKGEN_ACGC_ACGCR_ADDR, HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP21_CLKGEN_ACGC_ACGCR_RMSK) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP21_CLKGEN_ACGC_ACGCR_INM(m) \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP21_CLKGEN_ACGC_ACGCR_ADDR, m) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP21_CLKGEN_ACGC_ACGCR_OUT(v) \ + out_dword(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP21_CLKGEN_ACGC_ACGCR_ADDR,v) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP21_CLKGEN_ACGC_ACGCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP21_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP21_CLKGEN_ACGC_ACGCR_IN) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP21_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK 0x80000000 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP21_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT 0x1f +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP21_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP21_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP21_CLKGEN_ACGC_ACGCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP21_CLKGEN_ACGC_ACGCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP22_CLKGEN_ACGC_ACGCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00018058) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP22_CLKGEN_ACGC_ACGCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018058) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP22_CLKGEN_ACGC_ACGCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018058) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP22_CLKGEN_ACGC_ACGCR_RMSK 0x80000001 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP22_CLKGEN_ACGC_ACGCR_ATTR 0x3 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP22_CLKGEN_ACGC_ACGCR_IN \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP22_CLKGEN_ACGC_ACGCR_ADDR, HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP22_CLKGEN_ACGC_ACGCR_RMSK) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP22_CLKGEN_ACGC_ACGCR_INM(m) \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP22_CLKGEN_ACGC_ACGCR_ADDR, m) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP22_CLKGEN_ACGC_ACGCR_OUT(v) \ + out_dword(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP22_CLKGEN_ACGC_ACGCR_ADDR,v) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP22_CLKGEN_ACGC_ACGCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP22_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP22_CLKGEN_ACGC_ACGCR_IN) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP22_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK 0x80000000 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP22_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT 0x1f +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP22_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP22_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP22_CLKGEN_ACGC_ACGCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP22_CLKGEN_ACGC_ACGCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP23_CLKGEN_ACGC_ACGCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001805c) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP23_CLKGEN_ACGC_ACGCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001805c) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP23_CLKGEN_ACGC_ACGCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001805c) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP23_CLKGEN_ACGC_ACGCR_RMSK 0x80000001 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP23_CLKGEN_ACGC_ACGCR_ATTR 0x3 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP23_CLKGEN_ACGC_ACGCR_IN \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP23_CLKGEN_ACGC_ACGCR_ADDR, HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP23_CLKGEN_ACGC_ACGCR_RMSK) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP23_CLKGEN_ACGC_ACGCR_INM(m) \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP23_CLKGEN_ACGC_ACGCR_ADDR, m) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP23_CLKGEN_ACGC_ACGCR_OUT(v) \ + out_dword(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP23_CLKGEN_ACGC_ACGCR_ADDR,v) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP23_CLKGEN_ACGC_ACGCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP23_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP23_CLKGEN_ACGC_ACGCR_IN) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP23_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK 0x80000000 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP23_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT 0x1f +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP23_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP23_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP23_CLKGEN_ACGC_ACGCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP23_CLKGEN_ACGC_ACGCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP24_CLKGEN_ACGC_ACGCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00018060) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP24_CLKGEN_ACGC_ACGCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018060) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP24_CLKGEN_ACGC_ACGCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018060) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP24_CLKGEN_ACGC_ACGCR_RMSK 0x80000001 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP24_CLKGEN_ACGC_ACGCR_ATTR 0x3 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP24_CLKGEN_ACGC_ACGCR_IN \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP24_CLKGEN_ACGC_ACGCR_ADDR, HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP24_CLKGEN_ACGC_ACGCR_RMSK) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP24_CLKGEN_ACGC_ACGCR_INM(m) \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP24_CLKGEN_ACGC_ACGCR_ADDR, m) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP24_CLKGEN_ACGC_ACGCR_OUT(v) \ + out_dword(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP24_CLKGEN_ACGC_ACGCR_ADDR,v) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP24_CLKGEN_ACGC_ACGCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP24_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP24_CLKGEN_ACGC_ACGCR_IN) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP24_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK 0x80000000 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP24_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT 0x1f +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP24_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP24_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP24_CLKGEN_ACGC_ACGCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP24_CLKGEN_ACGC_ACGCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP25_CLKGEN_ACGC_ACGCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00018064) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP25_CLKGEN_ACGC_ACGCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018064) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP25_CLKGEN_ACGC_ACGCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018064) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP25_CLKGEN_ACGC_ACGCR_RMSK 0x80000001 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP25_CLKGEN_ACGC_ACGCR_ATTR 0x3 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP25_CLKGEN_ACGC_ACGCR_IN \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP25_CLKGEN_ACGC_ACGCR_ADDR, HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP25_CLKGEN_ACGC_ACGCR_RMSK) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP25_CLKGEN_ACGC_ACGCR_INM(m) \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP25_CLKGEN_ACGC_ACGCR_ADDR, m) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP25_CLKGEN_ACGC_ACGCR_OUT(v) \ + out_dword(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP25_CLKGEN_ACGC_ACGCR_ADDR,v) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP25_CLKGEN_ACGC_ACGCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP25_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP25_CLKGEN_ACGC_ACGCR_IN) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP25_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK 0x80000000 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP25_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT 0x1f +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP25_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP25_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP25_CLKGEN_ACGC_ACGCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP25_CLKGEN_ACGC_ACGCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP26_CLKGEN_ACGC_ACGCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00018068) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP26_CLKGEN_ACGC_ACGCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018068) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP26_CLKGEN_ACGC_ACGCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018068) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP26_CLKGEN_ACGC_ACGCR_RMSK 0x80000001 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP26_CLKGEN_ACGC_ACGCR_ATTR 0x3 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP26_CLKGEN_ACGC_ACGCR_IN \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP26_CLKGEN_ACGC_ACGCR_ADDR, HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP26_CLKGEN_ACGC_ACGCR_RMSK) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP26_CLKGEN_ACGC_ACGCR_INM(m) \ + in_dword_masked(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP26_CLKGEN_ACGC_ACGCR_ADDR, m) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP26_CLKGEN_ACGC_ACGCR_OUT(v) \ + out_dword(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP26_CLKGEN_ACGC_ACGCR_ADDR,v) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP26_CLKGEN_ACGC_ACGCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP26_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP26_CLKGEN_ACGC_ACGCR_IN) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP26_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK 0x80000000 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP26_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT 0x1f +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP26_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP26_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP26_CLKGEN_ACGC_ACGCR_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP26_CLKGEN_ACGC_ACGCR_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SP_IPA_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002f000) +#define HWIO_GCC_SP_IPA_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002f000) +#define HWIO_GCC_SP_IPA_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002f000) +#define HWIO_GCC_SP_IPA_SGDSCR_RMSK 0x7 +#define HWIO_GCC_SP_IPA_SGDSCR_ATTR 0x3 +#define HWIO_GCC_SP_IPA_SGDSCR_IN \ + in_dword_masked(HWIO_GCC_SP_IPA_SGDSCR_ADDR, HWIO_GCC_SP_IPA_SGDSCR_RMSK) +#define HWIO_GCC_SP_IPA_SGDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_SP_IPA_SGDSCR_ADDR, m) +#define HWIO_GCC_SP_IPA_SGDSCR_OUT(v) \ + out_dword(HWIO_GCC_SP_IPA_SGDSCR_ADDR,v) +#define HWIO_GCC_SP_IPA_SGDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SP_IPA_SGDSCR_ADDR,m,v,HWIO_GCC_SP_IPA_SGDSCR_IN) +#define HWIO_GCC_SP_IPA_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4 +#define HWIO_GCC_SP_IPA_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x2 +#define HWIO_GCC_SP_IPA_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_IPA_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_IPA_SGDSCR_RETAIN_FF_ENABLE_BMSK 0x2 +#define HWIO_GCC_SP_IPA_SGDSCR_RETAIN_FF_ENABLE_SHFT 0x1 +#define HWIO_GCC_SP_IPA_SGDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_IPA_SGDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_IPA_SGDSCR_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_SP_IPA_SGDSCR_SW_OVERRIDE_SHFT 0x0 +#define HWIO_GCC_SP_IPA_SGDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_IPA_SGDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SP_ANOC_PCIE_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002f004) +#define HWIO_GCC_SP_ANOC_PCIE_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002f004) +#define HWIO_GCC_SP_ANOC_PCIE_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002f004) +#define HWIO_GCC_SP_ANOC_PCIE_SGDSCR_RMSK 0x7 +#define HWIO_GCC_SP_ANOC_PCIE_SGDSCR_ATTR 0x3 +#define HWIO_GCC_SP_ANOC_PCIE_SGDSCR_IN \ + in_dword_masked(HWIO_GCC_SP_ANOC_PCIE_SGDSCR_ADDR, HWIO_GCC_SP_ANOC_PCIE_SGDSCR_RMSK) +#define HWIO_GCC_SP_ANOC_PCIE_SGDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_SP_ANOC_PCIE_SGDSCR_ADDR, m) +#define HWIO_GCC_SP_ANOC_PCIE_SGDSCR_OUT(v) \ + out_dword(HWIO_GCC_SP_ANOC_PCIE_SGDSCR_ADDR,v) +#define HWIO_GCC_SP_ANOC_PCIE_SGDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SP_ANOC_PCIE_SGDSCR_ADDR,m,v,HWIO_GCC_SP_ANOC_PCIE_SGDSCR_IN) +#define HWIO_GCC_SP_ANOC_PCIE_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4 +#define HWIO_GCC_SP_ANOC_PCIE_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x2 +#define HWIO_GCC_SP_ANOC_PCIE_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_ANOC_PCIE_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_ANOC_PCIE_SGDSCR_RETAIN_FF_ENABLE_BMSK 0x2 +#define HWIO_GCC_SP_ANOC_PCIE_SGDSCR_RETAIN_FF_ENABLE_SHFT 0x1 +#define HWIO_GCC_SP_ANOC_PCIE_SGDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_ANOC_PCIE_SGDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_ANOC_PCIE_SGDSCR_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_SP_ANOC_PCIE_SGDSCR_SW_OVERRIDE_SHFT 0x0 +#define HWIO_GCC_SP_ANOC_PCIE_SGDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_ANOC_PCIE_SGDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SP_PCIE_1_PHY_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002f008) +#define HWIO_GCC_SP_PCIE_1_PHY_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002f008) +#define HWIO_GCC_SP_PCIE_1_PHY_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002f008) +#define HWIO_GCC_SP_PCIE_1_PHY_SGDSCR_RMSK 0x7 +#define HWIO_GCC_SP_PCIE_1_PHY_SGDSCR_ATTR 0x3 +#define HWIO_GCC_SP_PCIE_1_PHY_SGDSCR_IN \ + in_dword_masked(HWIO_GCC_SP_PCIE_1_PHY_SGDSCR_ADDR, HWIO_GCC_SP_PCIE_1_PHY_SGDSCR_RMSK) +#define HWIO_GCC_SP_PCIE_1_PHY_SGDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_SP_PCIE_1_PHY_SGDSCR_ADDR, m) +#define HWIO_GCC_SP_PCIE_1_PHY_SGDSCR_OUT(v) \ + out_dword(HWIO_GCC_SP_PCIE_1_PHY_SGDSCR_ADDR,v) +#define HWIO_GCC_SP_PCIE_1_PHY_SGDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SP_PCIE_1_PHY_SGDSCR_ADDR,m,v,HWIO_GCC_SP_PCIE_1_PHY_SGDSCR_IN) +#define HWIO_GCC_SP_PCIE_1_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4 +#define HWIO_GCC_SP_PCIE_1_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x2 +#define HWIO_GCC_SP_PCIE_1_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_PCIE_1_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_PCIE_1_PHY_SGDSCR_RETAIN_FF_ENABLE_BMSK 0x2 +#define HWIO_GCC_SP_PCIE_1_PHY_SGDSCR_RETAIN_FF_ENABLE_SHFT 0x1 +#define HWIO_GCC_SP_PCIE_1_PHY_SGDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_PCIE_1_PHY_SGDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_PCIE_1_PHY_SGDSCR_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_SP_PCIE_1_PHY_SGDSCR_SW_OVERRIDE_SHFT 0x0 +#define HWIO_GCC_SP_PCIE_1_PHY_SGDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_PCIE_1_PHY_SGDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SP_USB30_PRIM_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002f00c) +#define HWIO_GCC_SP_USB30_PRIM_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002f00c) +#define HWIO_GCC_SP_USB30_PRIM_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002f00c) +#define HWIO_GCC_SP_USB30_PRIM_SGDSCR_RMSK 0x7 +#define HWIO_GCC_SP_USB30_PRIM_SGDSCR_ATTR 0x3 +#define HWIO_GCC_SP_USB30_PRIM_SGDSCR_IN \ + in_dword_masked(HWIO_GCC_SP_USB30_PRIM_SGDSCR_ADDR, HWIO_GCC_SP_USB30_PRIM_SGDSCR_RMSK) +#define HWIO_GCC_SP_USB30_PRIM_SGDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_SP_USB30_PRIM_SGDSCR_ADDR, m) +#define HWIO_GCC_SP_USB30_PRIM_SGDSCR_OUT(v) \ + out_dword(HWIO_GCC_SP_USB30_PRIM_SGDSCR_ADDR,v) +#define HWIO_GCC_SP_USB30_PRIM_SGDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SP_USB30_PRIM_SGDSCR_ADDR,m,v,HWIO_GCC_SP_USB30_PRIM_SGDSCR_IN) +#define HWIO_GCC_SP_USB30_PRIM_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4 +#define HWIO_GCC_SP_USB30_PRIM_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x2 +#define HWIO_GCC_SP_USB30_PRIM_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_USB30_PRIM_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_USB30_PRIM_SGDSCR_RETAIN_FF_ENABLE_BMSK 0x2 +#define HWIO_GCC_SP_USB30_PRIM_SGDSCR_RETAIN_FF_ENABLE_SHFT 0x1 +#define HWIO_GCC_SP_USB30_PRIM_SGDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_USB30_PRIM_SGDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_USB30_PRIM_SGDSCR_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_SP_USB30_PRIM_SGDSCR_SW_OVERRIDE_SHFT 0x0 +#define HWIO_GCC_SP_USB30_PRIM_SGDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_USB30_PRIM_SGDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SP_UFS_PHY_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002f010) +#define HWIO_GCC_SP_UFS_PHY_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002f010) +#define HWIO_GCC_SP_UFS_PHY_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002f010) +#define HWIO_GCC_SP_UFS_PHY_SGDSCR_RMSK 0x7 +#define HWIO_GCC_SP_UFS_PHY_SGDSCR_ATTR 0x3 +#define HWIO_GCC_SP_UFS_PHY_SGDSCR_IN \ + in_dword_masked(HWIO_GCC_SP_UFS_PHY_SGDSCR_ADDR, HWIO_GCC_SP_UFS_PHY_SGDSCR_RMSK) +#define HWIO_GCC_SP_UFS_PHY_SGDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_SP_UFS_PHY_SGDSCR_ADDR, m) +#define HWIO_GCC_SP_UFS_PHY_SGDSCR_OUT(v) \ + out_dword(HWIO_GCC_SP_UFS_PHY_SGDSCR_ADDR,v) +#define HWIO_GCC_SP_UFS_PHY_SGDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SP_UFS_PHY_SGDSCR_ADDR,m,v,HWIO_GCC_SP_UFS_PHY_SGDSCR_IN) +#define HWIO_GCC_SP_UFS_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4 +#define HWIO_GCC_SP_UFS_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x2 +#define HWIO_GCC_SP_UFS_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_UFS_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_UFS_PHY_SGDSCR_RETAIN_FF_ENABLE_BMSK 0x2 +#define HWIO_GCC_SP_UFS_PHY_SGDSCR_RETAIN_FF_ENABLE_SHFT 0x1 +#define HWIO_GCC_SP_UFS_PHY_SGDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_UFS_PHY_SGDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_UFS_PHY_SGDSCR_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_SP_UFS_PHY_SGDSCR_SW_OVERRIDE_SHFT 0x0 +#define HWIO_GCC_SP_UFS_PHY_SGDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_UFS_PHY_SGDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SP_USB3_PHY_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002f014) +#define HWIO_GCC_SP_USB3_PHY_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002f014) +#define HWIO_GCC_SP_USB3_PHY_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002f014) +#define HWIO_GCC_SP_USB3_PHY_SGDSCR_RMSK 0x7 +#define HWIO_GCC_SP_USB3_PHY_SGDSCR_ATTR 0x3 +#define HWIO_GCC_SP_USB3_PHY_SGDSCR_IN \ + in_dword_masked(HWIO_GCC_SP_USB3_PHY_SGDSCR_ADDR, HWIO_GCC_SP_USB3_PHY_SGDSCR_RMSK) +#define HWIO_GCC_SP_USB3_PHY_SGDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_SP_USB3_PHY_SGDSCR_ADDR, m) +#define HWIO_GCC_SP_USB3_PHY_SGDSCR_OUT(v) \ + out_dword(HWIO_GCC_SP_USB3_PHY_SGDSCR_ADDR,v) +#define HWIO_GCC_SP_USB3_PHY_SGDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SP_USB3_PHY_SGDSCR_ADDR,m,v,HWIO_GCC_SP_USB3_PHY_SGDSCR_IN) +#define HWIO_GCC_SP_USB3_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4 +#define HWIO_GCC_SP_USB3_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x2 +#define HWIO_GCC_SP_USB3_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_USB3_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_USB3_PHY_SGDSCR_RETAIN_FF_ENABLE_BMSK 0x2 +#define HWIO_GCC_SP_USB3_PHY_SGDSCR_RETAIN_FF_ENABLE_SHFT 0x1 +#define HWIO_GCC_SP_USB3_PHY_SGDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_USB3_PHY_SGDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_USB3_PHY_SGDSCR_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_SP_USB3_PHY_SGDSCR_SW_OVERRIDE_SHFT 0x0 +#define HWIO_GCC_SP_USB3_PHY_SGDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_USB3_PHY_SGDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SP_MMU_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002f018) +#define HWIO_GCC_SP_MMU_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002f018) +#define HWIO_GCC_SP_MMU_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002f018) +#define HWIO_GCC_SP_MMU_SGDSCR_RMSK 0x7 +#define HWIO_GCC_SP_MMU_SGDSCR_ATTR 0x3 +#define HWIO_GCC_SP_MMU_SGDSCR_IN \ + in_dword_masked(HWIO_GCC_SP_MMU_SGDSCR_ADDR, HWIO_GCC_SP_MMU_SGDSCR_RMSK) +#define HWIO_GCC_SP_MMU_SGDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_SP_MMU_SGDSCR_ADDR, m) +#define HWIO_GCC_SP_MMU_SGDSCR_OUT(v) \ + out_dword(HWIO_GCC_SP_MMU_SGDSCR_ADDR,v) +#define HWIO_GCC_SP_MMU_SGDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SP_MMU_SGDSCR_ADDR,m,v,HWIO_GCC_SP_MMU_SGDSCR_IN) +#define HWIO_GCC_SP_MMU_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4 +#define HWIO_GCC_SP_MMU_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x2 +#define HWIO_GCC_SP_MMU_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_MMU_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_MMU_SGDSCR_RETAIN_FF_ENABLE_BMSK 0x2 +#define HWIO_GCC_SP_MMU_SGDSCR_RETAIN_FF_ENABLE_SHFT 0x1 +#define HWIO_GCC_SP_MMU_SGDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_MMU_SGDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_MMU_SGDSCR_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_SP_MMU_SGDSCR_SW_OVERRIDE_SHFT 0x0 +#define HWIO_GCC_SP_MMU_SGDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_MMU_SGDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SP_PCIE_1_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002f01c) +#define HWIO_GCC_SP_PCIE_1_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002f01c) +#define HWIO_GCC_SP_PCIE_1_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002f01c) +#define HWIO_GCC_SP_PCIE_1_SGDSCR_RMSK 0x7 +#define HWIO_GCC_SP_PCIE_1_SGDSCR_ATTR 0x3 +#define HWIO_GCC_SP_PCIE_1_SGDSCR_IN \ + in_dword_masked(HWIO_GCC_SP_PCIE_1_SGDSCR_ADDR, HWIO_GCC_SP_PCIE_1_SGDSCR_RMSK) +#define HWIO_GCC_SP_PCIE_1_SGDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_SP_PCIE_1_SGDSCR_ADDR, m) +#define HWIO_GCC_SP_PCIE_1_SGDSCR_OUT(v) \ + out_dword(HWIO_GCC_SP_PCIE_1_SGDSCR_ADDR,v) +#define HWIO_GCC_SP_PCIE_1_SGDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SP_PCIE_1_SGDSCR_ADDR,m,v,HWIO_GCC_SP_PCIE_1_SGDSCR_IN) +#define HWIO_GCC_SP_PCIE_1_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4 +#define HWIO_GCC_SP_PCIE_1_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x2 +#define HWIO_GCC_SP_PCIE_1_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_PCIE_1_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_PCIE_1_SGDSCR_RETAIN_FF_ENABLE_BMSK 0x2 +#define HWIO_GCC_SP_PCIE_1_SGDSCR_RETAIN_FF_ENABLE_SHFT 0x1 +#define HWIO_GCC_SP_PCIE_1_SGDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_PCIE_1_SGDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_PCIE_1_SGDSCR_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_SP_PCIE_1_SGDSCR_SW_OVERRIDE_SHFT 0x0 +#define HWIO_GCC_SP_PCIE_1_SGDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_PCIE_1_SGDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SP_PCIE_0_PHY_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002f020) +#define HWIO_GCC_SP_PCIE_0_PHY_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002f020) +#define HWIO_GCC_SP_PCIE_0_PHY_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002f020) +#define HWIO_GCC_SP_PCIE_0_PHY_SGDSCR_RMSK 0x7 +#define HWIO_GCC_SP_PCIE_0_PHY_SGDSCR_ATTR 0x3 +#define HWIO_GCC_SP_PCIE_0_PHY_SGDSCR_IN \ + in_dword_masked(HWIO_GCC_SP_PCIE_0_PHY_SGDSCR_ADDR, HWIO_GCC_SP_PCIE_0_PHY_SGDSCR_RMSK) +#define HWIO_GCC_SP_PCIE_0_PHY_SGDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_SP_PCIE_0_PHY_SGDSCR_ADDR, m) +#define HWIO_GCC_SP_PCIE_0_PHY_SGDSCR_OUT(v) \ + out_dword(HWIO_GCC_SP_PCIE_0_PHY_SGDSCR_ADDR,v) +#define HWIO_GCC_SP_PCIE_0_PHY_SGDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SP_PCIE_0_PHY_SGDSCR_ADDR,m,v,HWIO_GCC_SP_PCIE_0_PHY_SGDSCR_IN) +#define HWIO_GCC_SP_PCIE_0_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4 +#define HWIO_GCC_SP_PCIE_0_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x2 +#define HWIO_GCC_SP_PCIE_0_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_PCIE_0_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_PCIE_0_PHY_SGDSCR_RETAIN_FF_ENABLE_BMSK 0x2 +#define HWIO_GCC_SP_PCIE_0_PHY_SGDSCR_RETAIN_FF_ENABLE_SHFT 0x1 +#define HWIO_GCC_SP_PCIE_0_PHY_SGDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_PCIE_0_PHY_SGDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_PCIE_0_PHY_SGDSCR_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_SP_PCIE_0_PHY_SGDSCR_SW_OVERRIDE_SHFT 0x0 +#define HWIO_GCC_SP_PCIE_0_PHY_SGDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_PCIE_0_PHY_SGDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SP_TURING_QTB_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002f024) +#define HWIO_GCC_SP_TURING_QTB_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002f024) +#define HWIO_GCC_SP_TURING_QTB_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002f024) +#define HWIO_GCC_SP_TURING_QTB_SGDSCR_RMSK 0x7 +#define HWIO_GCC_SP_TURING_QTB_SGDSCR_ATTR 0x3 +#define HWIO_GCC_SP_TURING_QTB_SGDSCR_IN \ + in_dword_masked(HWIO_GCC_SP_TURING_QTB_SGDSCR_ADDR, HWIO_GCC_SP_TURING_QTB_SGDSCR_RMSK) +#define HWIO_GCC_SP_TURING_QTB_SGDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_SP_TURING_QTB_SGDSCR_ADDR, m) +#define HWIO_GCC_SP_TURING_QTB_SGDSCR_OUT(v) \ + out_dword(HWIO_GCC_SP_TURING_QTB_SGDSCR_ADDR,v) +#define HWIO_GCC_SP_TURING_QTB_SGDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SP_TURING_QTB_SGDSCR_ADDR,m,v,HWIO_GCC_SP_TURING_QTB_SGDSCR_IN) +#define HWIO_GCC_SP_TURING_QTB_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4 +#define HWIO_GCC_SP_TURING_QTB_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x2 +#define HWIO_GCC_SP_TURING_QTB_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_TURING_QTB_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_TURING_QTB_SGDSCR_RETAIN_FF_ENABLE_BMSK 0x2 +#define HWIO_GCC_SP_TURING_QTB_SGDSCR_RETAIN_FF_ENABLE_SHFT 0x1 +#define HWIO_GCC_SP_TURING_QTB_SGDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_TURING_QTB_SGDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_TURING_QTB_SGDSCR_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_SP_TURING_QTB_SGDSCR_SW_OVERRIDE_SHFT 0x0 +#define HWIO_GCC_SP_TURING_QTB_SGDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_TURING_QTB_SGDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SP_UFS_MEM_PHY_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002f028) +#define HWIO_GCC_SP_UFS_MEM_PHY_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002f028) +#define HWIO_GCC_SP_UFS_MEM_PHY_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002f028) +#define HWIO_GCC_SP_UFS_MEM_PHY_SGDSCR_RMSK 0x7 +#define HWIO_GCC_SP_UFS_MEM_PHY_SGDSCR_ATTR 0x3 +#define HWIO_GCC_SP_UFS_MEM_PHY_SGDSCR_IN \ + in_dword_masked(HWIO_GCC_SP_UFS_MEM_PHY_SGDSCR_ADDR, HWIO_GCC_SP_UFS_MEM_PHY_SGDSCR_RMSK) +#define HWIO_GCC_SP_UFS_MEM_PHY_SGDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_SP_UFS_MEM_PHY_SGDSCR_ADDR, m) +#define HWIO_GCC_SP_UFS_MEM_PHY_SGDSCR_OUT(v) \ + out_dword(HWIO_GCC_SP_UFS_MEM_PHY_SGDSCR_ADDR,v) +#define HWIO_GCC_SP_UFS_MEM_PHY_SGDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SP_UFS_MEM_PHY_SGDSCR_ADDR,m,v,HWIO_GCC_SP_UFS_MEM_PHY_SGDSCR_IN) +#define HWIO_GCC_SP_UFS_MEM_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4 +#define HWIO_GCC_SP_UFS_MEM_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x2 +#define HWIO_GCC_SP_UFS_MEM_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_UFS_MEM_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_UFS_MEM_PHY_SGDSCR_RETAIN_FF_ENABLE_BMSK 0x2 +#define HWIO_GCC_SP_UFS_MEM_PHY_SGDSCR_RETAIN_FF_ENABLE_SHFT 0x1 +#define HWIO_GCC_SP_UFS_MEM_PHY_SGDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_UFS_MEM_PHY_SGDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_UFS_MEM_PHY_SGDSCR_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_SP_UFS_MEM_PHY_SGDSCR_SW_OVERRIDE_SHFT 0x0 +#define HWIO_GCC_SP_UFS_MEM_PHY_SGDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_UFS_MEM_PHY_SGDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SP_PCIE_0_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002f02c) +#define HWIO_GCC_SP_PCIE_0_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002f02c) +#define HWIO_GCC_SP_PCIE_0_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002f02c) +#define HWIO_GCC_SP_PCIE_0_SGDSCR_RMSK 0x7 +#define HWIO_GCC_SP_PCIE_0_SGDSCR_ATTR 0x3 +#define HWIO_GCC_SP_PCIE_0_SGDSCR_IN \ + in_dword_masked(HWIO_GCC_SP_PCIE_0_SGDSCR_ADDR, HWIO_GCC_SP_PCIE_0_SGDSCR_RMSK) +#define HWIO_GCC_SP_PCIE_0_SGDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_SP_PCIE_0_SGDSCR_ADDR, m) +#define HWIO_GCC_SP_PCIE_0_SGDSCR_OUT(v) \ + out_dword(HWIO_GCC_SP_PCIE_0_SGDSCR_ADDR,v) +#define HWIO_GCC_SP_PCIE_0_SGDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SP_PCIE_0_SGDSCR_ADDR,m,v,HWIO_GCC_SP_PCIE_0_SGDSCR_IN) +#define HWIO_GCC_SP_PCIE_0_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4 +#define HWIO_GCC_SP_PCIE_0_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x2 +#define HWIO_GCC_SP_PCIE_0_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_PCIE_0_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_PCIE_0_SGDSCR_RETAIN_FF_ENABLE_BMSK 0x2 +#define HWIO_GCC_SP_PCIE_0_SGDSCR_RETAIN_FF_ENABLE_SHFT 0x1 +#define HWIO_GCC_SP_PCIE_0_SGDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_PCIE_0_SGDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_PCIE_0_SGDSCR_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_SP_PCIE_0_SGDSCR_SW_OVERRIDE_SHFT 0x0 +#define HWIO_GCC_SP_PCIE_0_SGDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_PCIE_0_SGDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SP_LPASS_QTB_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002f030) +#define HWIO_GCC_SP_LPASS_QTB_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002f030) +#define HWIO_GCC_SP_LPASS_QTB_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002f030) +#define HWIO_GCC_SP_LPASS_QTB_SGDSCR_RMSK 0x7 +#define HWIO_GCC_SP_LPASS_QTB_SGDSCR_ATTR 0x3 +#define HWIO_GCC_SP_LPASS_QTB_SGDSCR_IN \ + in_dword_masked(HWIO_GCC_SP_LPASS_QTB_SGDSCR_ADDR, HWIO_GCC_SP_LPASS_QTB_SGDSCR_RMSK) +#define HWIO_GCC_SP_LPASS_QTB_SGDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_SP_LPASS_QTB_SGDSCR_ADDR, m) +#define HWIO_GCC_SP_LPASS_QTB_SGDSCR_OUT(v) \ + out_dword(HWIO_GCC_SP_LPASS_QTB_SGDSCR_ADDR,v) +#define HWIO_GCC_SP_LPASS_QTB_SGDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SP_LPASS_QTB_SGDSCR_ADDR,m,v,HWIO_GCC_SP_LPASS_QTB_SGDSCR_IN) +#define HWIO_GCC_SP_LPASS_QTB_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4 +#define HWIO_GCC_SP_LPASS_QTB_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x2 +#define HWIO_GCC_SP_LPASS_QTB_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_LPASS_QTB_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_LPASS_QTB_SGDSCR_RETAIN_FF_ENABLE_BMSK 0x2 +#define HWIO_GCC_SP_LPASS_QTB_SGDSCR_RETAIN_FF_ENABLE_SHFT 0x1 +#define HWIO_GCC_SP_LPASS_QTB_SGDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_LPASS_QTB_SGDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_LPASS_QTB_SGDSCR_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_SP_LPASS_QTB_SGDSCR_SW_OVERRIDE_SHFT 0x0 +#define HWIO_GCC_SP_LPASS_QTB_SGDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_LPASS_QTB_SGDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SP_MMNOC_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002f034) +#define HWIO_GCC_SP_MMNOC_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002f034) +#define HWIO_GCC_SP_MMNOC_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002f034) +#define HWIO_GCC_SP_MMNOC_SGDSCR_RMSK 0x7 +#define HWIO_GCC_SP_MMNOC_SGDSCR_ATTR 0x3 +#define HWIO_GCC_SP_MMNOC_SGDSCR_IN \ + in_dword_masked(HWIO_GCC_SP_MMNOC_SGDSCR_ADDR, HWIO_GCC_SP_MMNOC_SGDSCR_RMSK) +#define HWIO_GCC_SP_MMNOC_SGDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_SP_MMNOC_SGDSCR_ADDR, m) +#define HWIO_GCC_SP_MMNOC_SGDSCR_OUT(v) \ + out_dword(HWIO_GCC_SP_MMNOC_SGDSCR_ADDR,v) +#define HWIO_GCC_SP_MMNOC_SGDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SP_MMNOC_SGDSCR_ADDR,m,v,HWIO_GCC_SP_MMNOC_SGDSCR_IN) +#define HWIO_GCC_SP_MMNOC_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4 +#define HWIO_GCC_SP_MMNOC_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x2 +#define HWIO_GCC_SP_MMNOC_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_MMNOC_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_MMNOC_SGDSCR_RETAIN_FF_ENABLE_BMSK 0x2 +#define HWIO_GCC_SP_MMNOC_SGDSCR_RETAIN_FF_ENABLE_SHFT 0x1 +#define HWIO_GCC_SP_MMNOC_SGDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_MMNOC_SGDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_MMNOC_SGDSCR_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_SP_MMNOC_SGDSCR_SW_OVERRIDE_SHFT 0x0 +#define HWIO_GCC_SP_MMNOC_SGDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_MMNOC_SGDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_APCS_TZ_IPA_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00043000) +#define HWIO_GCC_APCS_TZ_IPA_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00043000) +#define HWIO_GCC_APCS_TZ_IPA_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00043000) +#define HWIO_GCC_APCS_TZ_IPA_SGDSCR_RMSK 0x7 +#define HWIO_GCC_APCS_TZ_IPA_SGDSCR_ATTR 0x3 +#define HWIO_GCC_APCS_TZ_IPA_SGDSCR_IN \ + in_dword_masked(HWIO_GCC_APCS_TZ_IPA_SGDSCR_ADDR, HWIO_GCC_APCS_TZ_IPA_SGDSCR_RMSK) +#define HWIO_GCC_APCS_TZ_IPA_SGDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_APCS_TZ_IPA_SGDSCR_ADDR, m) +#define HWIO_GCC_APCS_TZ_IPA_SGDSCR_OUT(v) \ + out_dword(HWIO_GCC_APCS_TZ_IPA_SGDSCR_ADDR,v) +#define HWIO_GCC_APCS_TZ_IPA_SGDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_APCS_TZ_IPA_SGDSCR_ADDR,m,v,HWIO_GCC_APCS_TZ_IPA_SGDSCR_IN) +#define HWIO_GCC_APCS_TZ_IPA_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4 +#define HWIO_GCC_APCS_TZ_IPA_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x2 +#define HWIO_GCC_APCS_TZ_IPA_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_IPA_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_IPA_SGDSCR_RETAIN_FF_ENABLE_BMSK 0x2 +#define HWIO_GCC_APCS_TZ_IPA_SGDSCR_RETAIN_FF_ENABLE_SHFT 0x1 +#define HWIO_GCC_APCS_TZ_IPA_SGDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_IPA_SGDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_IPA_SGDSCR_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_APCS_TZ_IPA_SGDSCR_SW_OVERRIDE_SHFT 0x0 +#define HWIO_GCC_APCS_TZ_IPA_SGDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_IPA_SGDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_APCS_TZ_ANOC_PCIE_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00043004) +#define HWIO_GCC_APCS_TZ_ANOC_PCIE_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00043004) +#define HWIO_GCC_APCS_TZ_ANOC_PCIE_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00043004) +#define HWIO_GCC_APCS_TZ_ANOC_PCIE_SGDSCR_RMSK 0x7 +#define HWIO_GCC_APCS_TZ_ANOC_PCIE_SGDSCR_ATTR 0x3 +#define HWIO_GCC_APCS_TZ_ANOC_PCIE_SGDSCR_IN \ + in_dword_masked(HWIO_GCC_APCS_TZ_ANOC_PCIE_SGDSCR_ADDR, HWIO_GCC_APCS_TZ_ANOC_PCIE_SGDSCR_RMSK) +#define HWIO_GCC_APCS_TZ_ANOC_PCIE_SGDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_APCS_TZ_ANOC_PCIE_SGDSCR_ADDR, m) +#define HWIO_GCC_APCS_TZ_ANOC_PCIE_SGDSCR_OUT(v) \ + out_dword(HWIO_GCC_APCS_TZ_ANOC_PCIE_SGDSCR_ADDR,v) +#define HWIO_GCC_APCS_TZ_ANOC_PCIE_SGDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_APCS_TZ_ANOC_PCIE_SGDSCR_ADDR,m,v,HWIO_GCC_APCS_TZ_ANOC_PCIE_SGDSCR_IN) +#define HWIO_GCC_APCS_TZ_ANOC_PCIE_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4 +#define HWIO_GCC_APCS_TZ_ANOC_PCIE_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x2 +#define HWIO_GCC_APCS_TZ_ANOC_PCIE_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_ANOC_PCIE_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_ANOC_PCIE_SGDSCR_RETAIN_FF_ENABLE_BMSK 0x2 +#define HWIO_GCC_APCS_TZ_ANOC_PCIE_SGDSCR_RETAIN_FF_ENABLE_SHFT 0x1 +#define HWIO_GCC_APCS_TZ_ANOC_PCIE_SGDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_ANOC_PCIE_SGDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_ANOC_PCIE_SGDSCR_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_APCS_TZ_ANOC_PCIE_SGDSCR_SW_OVERRIDE_SHFT 0x0 +#define HWIO_GCC_APCS_TZ_ANOC_PCIE_SGDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_ANOC_PCIE_SGDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_APCS_TZ_PCIE_1_PHY_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00043008) +#define HWIO_GCC_APCS_TZ_PCIE_1_PHY_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00043008) +#define HWIO_GCC_APCS_TZ_PCIE_1_PHY_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00043008) +#define HWIO_GCC_APCS_TZ_PCIE_1_PHY_SGDSCR_RMSK 0x7 +#define HWIO_GCC_APCS_TZ_PCIE_1_PHY_SGDSCR_ATTR 0x3 +#define HWIO_GCC_APCS_TZ_PCIE_1_PHY_SGDSCR_IN \ + in_dword_masked(HWIO_GCC_APCS_TZ_PCIE_1_PHY_SGDSCR_ADDR, HWIO_GCC_APCS_TZ_PCIE_1_PHY_SGDSCR_RMSK) +#define HWIO_GCC_APCS_TZ_PCIE_1_PHY_SGDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_APCS_TZ_PCIE_1_PHY_SGDSCR_ADDR, m) +#define HWIO_GCC_APCS_TZ_PCIE_1_PHY_SGDSCR_OUT(v) \ + out_dword(HWIO_GCC_APCS_TZ_PCIE_1_PHY_SGDSCR_ADDR,v) +#define HWIO_GCC_APCS_TZ_PCIE_1_PHY_SGDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_APCS_TZ_PCIE_1_PHY_SGDSCR_ADDR,m,v,HWIO_GCC_APCS_TZ_PCIE_1_PHY_SGDSCR_IN) +#define HWIO_GCC_APCS_TZ_PCIE_1_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4 +#define HWIO_GCC_APCS_TZ_PCIE_1_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x2 +#define HWIO_GCC_APCS_TZ_PCIE_1_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_PCIE_1_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_PCIE_1_PHY_SGDSCR_RETAIN_FF_ENABLE_BMSK 0x2 +#define HWIO_GCC_APCS_TZ_PCIE_1_PHY_SGDSCR_RETAIN_FF_ENABLE_SHFT 0x1 +#define HWIO_GCC_APCS_TZ_PCIE_1_PHY_SGDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_PCIE_1_PHY_SGDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_PCIE_1_PHY_SGDSCR_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_APCS_TZ_PCIE_1_PHY_SGDSCR_SW_OVERRIDE_SHFT 0x0 +#define HWIO_GCC_APCS_TZ_PCIE_1_PHY_SGDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_PCIE_1_PHY_SGDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_APCS_TZ_USB30_PRIM_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004300c) +#define HWIO_GCC_APCS_TZ_USB30_PRIM_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004300c) +#define HWIO_GCC_APCS_TZ_USB30_PRIM_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004300c) +#define HWIO_GCC_APCS_TZ_USB30_PRIM_SGDSCR_RMSK 0x7 +#define HWIO_GCC_APCS_TZ_USB30_PRIM_SGDSCR_ATTR 0x3 +#define HWIO_GCC_APCS_TZ_USB30_PRIM_SGDSCR_IN \ + in_dword_masked(HWIO_GCC_APCS_TZ_USB30_PRIM_SGDSCR_ADDR, HWIO_GCC_APCS_TZ_USB30_PRIM_SGDSCR_RMSK) +#define HWIO_GCC_APCS_TZ_USB30_PRIM_SGDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_APCS_TZ_USB30_PRIM_SGDSCR_ADDR, m) +#define HWIO_GCC_APCS_TZ_USB30_PRIM_SGDSCR_OUT(v) \ + out_dword(HWIO_GCC_APCS_TZ_USB30_PRIM_SGDSCR_ADDR,v) +#define HWIO_GCC_APCS_TZ_USB30_PRIM_SGDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_APCS_TZ_USB30_PRIM_SGDSCR_ADDR,m,v,HWIO_GCC_APCS_TZ_USB30_PRIM_SGDSCR_IN) +#define HWIO_GCC_APCS_TZ_USB30_PRIM_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4 +#define HWIO_GCC_APCS_TZ_USB30_PRIM_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x2 +#define HWIO_GCC_APCS_TZ_USB30_PRIM_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_USB30_PRIM_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_USB30_PRIM_SGDSCR_RETAIN_FF_ENABLE_BMSK 0x2 +#define HWIO_GCC_APCS_TZ_USB30_PRIM_SGDSCR_RETAIN_FF_ENABLE_SHFT 0x1 +#define HWIO_GCC_APCS_TZ_USB30_PRIM_SGDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_USB30_PRIM_SGDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_USB30_PRIM_SGDSCR_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_APCS_TZ_USB30_PRIM_SGDSCR_SW_OVERRIDE_SHFT 0x0 +#define HWIO_GCC_APCS_TZ_USB30_PRIM_SGDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_USB30_PRIM_SGDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_APCS_TZ_UFS_PHY_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00043010) +#define HWIO_GCC_APCS_TZ_UFS_PHY_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00043010) +#define HWIO_GCC_APCS_TZ_UFS_PHY_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00043010) +#define HWIO_GCC_APCS_TZ_UFS_PHY_SGDSCR_RMSK 0x7 +#define HWIO_GCC_APCS_TZ_UFS_PHY_SGDSCR_ATTR 0x3 +#define HWIO_GCC_APCS_TZ_UFS_PHY_SGDSCR_IN \ + in_dword_masked(HWIO_GCC_APCS_TZ_UFS_PHY_SGDSCR_ADDR, HWIO_GCC_APCS_TZ_UFS_PHY_SGDSCR_RMSK) +#define HWIO_GCC_APCS_TZ_UFS_PHY_SGDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_APCS_TZ_UFS_PHY_SGDSCR_ADDR, m) +#define HWIO_GCC_APCS_TZ_UFS_PHY_SGDSCR_OUT(v) \ + out_dword(HWIO_GCC_APCS_TZ_UFS_PHY_SGDSCR_ADDR,v) +#define HWIO_GCC_APCS_TZ_UFS_PHY_SGDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_APCS_TZ_UFS_PHY_SGDSCR_ADDR,m,v,HWIO_GCC_APCS_TZ_UFS_PHY_SGDSCR_IN) +#define HWIO_GCC_APCS_TZ_UFS_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4 +#define HWIO_GCC_APCS_TZ_UFS_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x2 +#define HWIO_GCC_APCS_TZ_UFS_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_UFS_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_UFS_PHY_SGDSCR_RETAIN_FF_ENABLE_BMSK 0x2 +#define HWIO_GCC_APCS_TZ_UFS_PHY_SGDSCR_RETAIN_FF_ENABLE_SHFT 0x1 +#define HWIO_GCC_APCS_TZ_UFS_PHY_SGDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_UFS_PHY_SGDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_UFS_PHY_SGDSCR_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_APCS_TZ_UFS_PHY_SGDSCR_SW_OVERRIDE_SHFT 0x0 +#define HWIO_GCC_APCS_TZ_UFS_PHY_SGDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_UFS_PHY_SGDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_APCS_TZ_USB3_PHY_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00043014) +#define HWIO_GCC_APCS_TZ_USB3_PHY_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00043014) +#define HWIO_GCC_APCS_TZ_USB3_PHY_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00043014) +#define HWIO_GCC_APCS_TZ_USB3_PHY_SGDSCR_RMSK 0x7 +#define HWIO_GCC_APCS_TZ_USB3_PHY_SGDSCR_ATTR 0x3 +#define HWIO_GCC_APCS_TZ_USB3_PHY_SGDSCR_IN \ + in_dword_masked(HWIO_GCC_APCS_TZ_USB3_PHY_SGDSCR_ADDR, HWIO_GCC_APCS_TZ_USB3_PHY_SGDSCR_RMSK) +#define HWIO_GCC_APCS_TZ_USB3_PHY_SGDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_APCS_TZ_USB3_PHY_SGDSCR_ADDR, m) +#define HWIO_GCC_APCS_TZ_USB3_PHY_SGDSCR_OUT(v) \ + out_dword(HWIO_GCC_APCS_TZ_USB3_PHY_SGDSCR_ADDR,v) +#define HWIO_GCC_APCS_TZ_USB3_PHY_SGDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_APCS_TZ_USB3_PHY_SGDSCR_ADDR,m,v,HWIO_GCC_APCS_TZ_USB3_PHY_SGDSCR_IN) +#define HWIO_GCC_APCS_TZ_USB3_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4 +#define HWIO_GCC_APCS_TZ_USB3_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x2 +#define HWIO_GCC_APCS_TZ_USB3_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_USB3_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_USB3_PHY_SGDSCR_RETAIN_FF_ENABLE_BMSK 0x2 +#define HWIO_GCC_APCS_TZ_USB3_PHY_SGDSCR_RETAIN_FF_ENABLE_SHFT 0x1 +#define HWIO_GCC_APCS_TZ_USB3_PHY_SGDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_USB3_PHY_SGDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_USB3_PHY_SGDSCR_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_APCS_TZ_USB3_PHY_SGDSCR_SW_OVERRIDE_SHFT 0x0 +#define HWIO_GCC_APCS_TZ_USB3_PHY_SGDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_USB3_PHY_SGDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_APCS_TZ_MMU_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00043018) +#define HWIO_GCC_APCS_TZ_MMU_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00043018) +#define HWIO_GCC_APCS_TZ_MMU_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00043018) +#define HWIO_GCC_APCS_TZ_MMU_SGDSCR_RMSK 0x7 +#define HWIO_GCC_APCS_TZ_MMU_SGDSCR_ATTR 0x3 +#define HWIO_GCC_APCS_TZ_MMU_SGDSCR_IN \ + in_dword_masked(HWIO_GCC_APCS_TZ_MMU_SGDSCR_ADDR, HWIO_GCC_APCS_TZ_MMU_SGDSCR_RMSK) +#define HWIO_GCC_APCS_TZ_MMU_SGDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_APCS_TZ_MMU_SGDSCR_ADDR, m) +#define HWIO_GCC_APCS_TZ_MMU_SGDSCR_OUT(v) \ + out_dword(HWIO_GCC_APCS_TZ_MMU_SGDSCR_ADDR,v) +#define HWIO_GCC_APCS_TZ_MMU_SGDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_APCS_TZ_MMU_SGDSCR_ADDR,m,v,HWIO_GCC_APCS_TZ_MMU_SGDSCR_IN) +#define HWIO_GCC_APCS_TZ_MMU_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4 +#define HWIO_GCC_APCS_TZ_MMU_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x2 +#define HWIO_GCC_APCS_TZ_MMU_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_MMU_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_MMU_SGDSCR_RETAIN_FF_ENABLE_BMSK 0x2 +#define HWIO_GCC_APCS_TZ_MMU_SGDSCR_RETAIN_FF_ENABLE_SHFT 0x1 +#define HWIO_GCC_APCS_TZ_MMU_SGDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_MMU_SGDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_MMU_SGDSCR_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_APCS_TZ_MMU_SGDSCR_SW_OVERRIDE_SHFT 0x0 +#define HWIO_GCC_APCS_TZ_MMU_SGDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_MMU_SGDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_APCS_TZ_PCIE_1_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004301c) +#define HWIO_GCC_APCS_TZ_PCIE_1_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004301c) +#define HWIO_GCC_APCS_TZ_PCIE_1_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004301c) +#define HWIO_GCC_APCS_TZ_PCIE_1_SGDSCR_RMSK 0x7 +#define HWIO_GCC_APCS_TZ_PCIE_1_SGDSCR_ATTR 0x3 +#define HWIO_GCC_APCS_TZ_PCIE_1_SGDSCR_IN \ + in_dword_masked(HWIO_GCC_APCS_TZ_PCIE_1_SGDSCR_ADDR, HWIO_GCC_APCS_TZ_PCIE_1_SGDSCR_RMSK) +#define HWIO_GCC_APCS_TZ_PCIE_1_SGDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_APCS_TZ_PCIE_1_SGDSCR_ADDR, m) +#define HWIO_GCC_APCS_TZ_PCIE_1_SGDSCR_OUT(v) \ + out_dword(HWIO_GCC_APCS_TZ_PCIE_1_SGDSCR_ADDR,v) +#define HWIO_GCC_APCS_TZ_PCIE_1_SGDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_APCS_TZ_PCIE_1_SGDSCR_ADDR,m,v,HWIO_GCC_APCS_TZ_PCIE_1_SGDSCR_IN) +#define HWIO_GCC_APCS_TZ_PCIE_1_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4 +#define HWIO_GCC_APCS_TZ_PCIE_1_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x2 +#define HWIO_GCC_APCS_TZ_PCIE_1_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_PCIE_1_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_PCIE_1_SGDSCR_RETAIN_FF_ENABLE_BMSK 0x2 +#define HWIO_GCC_APCS_TZ_PCIE_1_SGDSCR_RETAIN_FF_ENABLE_SHFT 0x1 +#define HWIO_GCC_APCS_TZ_PCIE_1_SGDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_PCIE_1_SGDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_PCIE_1_SGDSCR_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_APCS_TZ_PCIE_1_SGDSCR_SW_OVERRIDE_SHFT 0x0 +#define HWIO_GCC_APCS_TZ_PCIE_1_SGDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_PCIE_1_SGDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_APCS_TZ_PCIE_0_PHY_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00043020) +#define HWIO_GCC_APCS_TZ_PCIE_0_PHY_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00043020) +#define HWIO_GCC_APCS_TZ_PCIE_0_PHY_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00043020) +#define HWIO_GCC_APCS_TZ_PCIE_0_PHY_SGDSCR_RMSK 0x7 +#define HWIO_GCC_APCS_TZ_PCIE_0_PHY_SGDSCR_ATTR 0x3 +#define HWIO_GCC_APCS_TZ_PCIE_0_PHY_SGDSCR_IN \ + in_dword_masked(HWIO_GCC_APCS_TZ_PCIE_0_PHY_SGDSCR_ADDR, HWIO_GCC_APCS_TZ_PCIE_0_PHY_SGDSCR_RMSK) +#define HWIO_GCC_APCS_TZ_PCIE_0_PHY_SGDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_APCS_TZ_PCIE_0_PHY_SGDSCR_ADDR, m) +#define HWIO_GCC_APCS_TZ_PCIE_0_PHY_SGDSCR_OUT(v) \ + out_dword(HWIO_GCC_APCS_TZ_PCIE_0_PHY_SGDSCR_ADDR,v) +#define HWIO_GCC_APCS_TZ_PCIE_0_PHY_SGDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_APCS_TZ_PCIE_0_PHY_SGDSCR_ADDR,m,v,HWIO_GCC_APCS_TZ_PCIE_0_PHY_SGDSCR_IN) +#define HWIO_GCC_APCS_TZ_PCIE_0_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4 +#define HWIO_GCC_APCS_TZ_PCIE_0_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x2 +#define HWIO_GCC_APCS_TZ_PCIE_0_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_PCIE_0_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_PCIE_0_PHY_SGDSCR_RETAIN_FF_ENABLE_BMSK 0x2 +#define HWIO_GCC_APCS_TZ_PCIE_0_PHY_SGDSCR_RETAIN_FF_ENABLE_SHFT 0x1 +#define HWIO_GCC_APCS_TZ_PCIE_0_PHY_SGDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_PCIE_0_PHY_SGDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_PCIE_0_PHY_SGDSCR_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_APCS_TZ_PCIE_0_PHY_SGDSCR_SW_OVERRIDE_SHFT 0x0 +#define HWIO_GCC_APCS_TZ_PCIE_0_PHY_SGDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_PCIE_0_PHY_SGDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_APCS_TZ_TURING_QTB_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00043024) +#define HWIO_GCC_APCS_TZ_TURING_QTB_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00043024) +#define HWIO_GCC_APCS_TZ_TURING_QTB_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00043024) +#define HWIO_GCC_APCS_TZ_TURING_QTB_SGDSCR_RMSK 0x7 +#define HWIO_GCC_APCS_TZ_TURING_QTB_SGDSCR_ATTR 0x3 +#define HWIO_GCC_APCS_TZ_TURING_QTB_SGDSCR_IN \ + in_dword_masked(HWIO_GCC_APCS_TZ_TURING_QTB_SGDSCR_ADDR, HWIO_GCC_APCS_TZ_TURING_QTB_SGDSCR_RMSK) +#define HWIO_GCC_APCS_TZ_TURING_QTB_SGDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_APCS_TZ_TURING_QTB_SGDSCR_ADDR, m) +#define HWIO_GCC_APCS_TZ_TURING_QTB_SGDSCR_OUT(v) \ + out_dword(HWIO_GCC_APCS_TZ_TURING_QTB_SGDSCR_ADDR,v) +#define HWIO_GCC_APCS_TZ_TURING_QTB_SGDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_APCS_TZ_TURING_QTB_SGDSCR_ADDR,m,v,HWIO_GCC_APCS_TZ_TURING_QTB_SGDSCR_IN) +#define HWIO_GCC_APCS_TZ_TURING_QTB_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4 +#define HWIO_GCC_APCS_TZ_TURING_QTB_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x2 +#define HWIO_GCC_APCS_TZ_TURING_QTB_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_TURING_QTB_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_TURING_QTB_SGDSCR_RETAIN_FF_ENABLE_BMSK 0x2 +#define HWIO_GCC_APCS_TZ_TURING_QTB_SGDSCR_RETAIN_FF_ENABLE_SHFT 0x1 +#define HWIO_GCC_APCS_TZ_TURING_QTB_SGDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_TURING_QTB_SGDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_TURING_QTB_SGDSCR_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_APCS_TZ_TURING_QTB_SGDSCR_SW_OVERRIDE_SHFT 0x0 +#define HWIO_GCC_APCS_TZ_TURING_QTB_SGDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_TURING_QTB_SGDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_APCS_TZ_UFS_MEM_PHY_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00043028) +#define HWIO_GCC_APCS_TZ_UFS_MEM_PHY_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00043028) +#define HWIO_GCC_APCS_TZ_UFS_MEM_PHY_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00043028) +#define HWIO_GCC_APCS_TZ_UFS_MEM_PHY_SGDSCR_RMSK 0x7 +#define HWIO_GCC_APCS_TZ_UFS_MEM_PHY_SGDSCR_ATTR 0x3 +#define HWIO_GCC_APCS_TZ_UFS_MEM_PHY_SGDSCR_IN \ + in_dword_masked(HWIO_GCC_APCS_TZ_UFS_MEM_PHY_SGDSCR_ADDR, HWIO_GCC_APCS_TZ_UFS_MEM_PHY_SGDSCR_RMSK) +#define HWIO_GCC_APCS_TZ_UFS_MEM_PHY_SGDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_APCS_TZ_UFS_MEM_PHY_SGDSCR_ADDR, m) +#define HWIO_GCC_APCS_TZ_UFS_MEM_PHY_SGDSCR_OUT(v) \ + out_dword(HWIO_GCC_APCS_TZ_UFS_MEM_PHY_SGDSCR_ADDR,v) +#define HWIO_GCC_APCS_TZ_UFS_MEM_PHY_SGDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_APCS_TZ_UFS_MEM_PHY_SGDSCR_ADDR,m,v,HWIO_GCC_APCS_TZ_UFS_MEM_PHY_SGDSCR_IN) +#define HWIO_GCC_APCS_TZ_UFS_MEM_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4 +#define HWIO_GCC_APCS_TZ_UFS_MEM_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x2 +#define HWIO_GCC_APCS_TZ_UFS_MEM_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_UFS_MEM_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_UFS_MEM_PHY_SGDSCR_RETAIN_FF_ENABLE_BMSK 0x2 +#define HWIO_GCC_APCS_TZ_UFS_MEM_PHY_SGDSCR_RETAIN_FF_ENABLE_SHFT 0x1 +#define HWIO_GCC_APCS_TZ_UFS_MEM_PHY_SGDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_UFS_MEM_PHY_SGDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_UFS_MEM_PHY_SGDSCR_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_APCS_TZ_UFS_MEM_PHY_SGDSCR_SW_OVERRIDE_SHFT 0x0 +#define HWIO_GCC_APCS_TZ_UFS_MEM_PHY_SGDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_UFS_MEM_PHY_SGDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_APCS_TZ_PCIE_0_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004302c) +#define HWIO_GCC_APCS_TZ_PCIE_0_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004302c) +#define HWIO_GCC_APCS_TZ_PCIE_0_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004302c) +#define HWIO_GCC_APCS_TZ_PCIE_0_SGDSCR_RMSK 0x7 +#define HWIO_GCC_APCS_TZ_PCIE_0_SGDSCR_ATTR 0x3 +#define HWIO_GCC_APCS_TZ_PCIE_0_SGDSCR_IN \ + in_dword_masked(HWIO_GCC_APCS_TZ_PCIE_0_SGDSCR_ADDR, HWIO_GCC_APCS_TZ_PCIE_0_SGDSCR_RMSK) +#define HWIO_GCC_APCS_TZ_PCIE_0_SGDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_APCS_TZ_PCIE_0_SGDSCR_ADDR, m) +#define HWIO_GCC_APCS_TZ_PCIE_0_SGDSCR_OUT(v) \ + out_dword(HWIO_GCC_APCS_TZ_PCIE_0_SGDSCR_ADDR,v) +#define HWIO_GCC_APCS_TZ_PCIE_0_SGDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_APCS_TZ_PCIE_0_SGDSCR_ADDR,m,v,HWIO_GCC_APCS_TZ_PCIE_0_SGDSCR_IN) +#define HWIO_GCC_APCS_TZ_PCIE_0_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4 +#define HWIO_GCC_APCS_TZ_PCIE_0_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x2 +#define HWIO_GCC_APCS_TZ_PCIE_0_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_PCIE_0_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_PCIE_0_SGDSCR_RETAIN_FF_ENABLE_BMSK 0x2 +#define HWIO_GCC_APCS_TZ_PCIE_0_SGDSCR_RETAIN_FF_ENABLE_SHFT 0x1 +#define HWIO_GCC_APCS_TZ_PCIE_0_SGDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_PCIE_0_SGDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_PCIE_0_SGDSCR_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_APCS_TZ_PCIE_0_SGDSCR_SW_OVERRIDE_SHFT 0x0 +#define HWIO_GCC_APCS_TZ_PCIE_0_SGDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_PCIE_0_SGDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_APCS_TZ_LPASS_QTB_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00043030) +#define HWIO_GCC_APCS_TZ_LPASS_QTB_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00043030) +#define HWIO_GCC_APCS_TZ_LPASS_QTB_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00043030) +#define HWIO_GCC_APCS_TZ_LPASS_QTB_SGDSCR_RMSK 0x7 +#define HWIO_GCC_APCS_TZ_LPASS_QTB_SGDSCR_ATTR 0x3 +#define HWIO_GCC_APCS_TZ_LPASS_QTB_SGDSCR_IN \ + in_dword_masked(HWIO_GCC_APCS_TZ_LPASS_QTB_SGDSCR_ADDR, HWIO_GCC_APCS_TZ_LPASS_QTB_SGDSCR_RMSK) +#define HWIO_GCC_APCS_TZ_LPASS_QTB_SGDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_APCS_TZ_LPASS_QTB_SGDSCR_ADDR, m) +#define HWIO_GCC_APCS_TZ_LPASS_QTB_SGDSCR_OUT(v) \ + out_dword(HWIO_GCC_APCS_TZ_LPASS_QTB_SGDSCR_ADDR,v) +#define HWIO_GCC_APCS_TZ_LPASS_QTB_SGDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_APCS_TZ_LPASS_QTB_SGDSCR_ADDR,m,v,HWIO_GCC_APCS_TZ_LPASS_QTB_SGDSCR_IN) +#define HWIO_GCC_APCS_TZ_LPASS_QTB_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4 +#define HWIO_GCC_APCS_TZ_LPASS_QTB_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x2 +#define HWIO_GCC_APCS_TZ_LPASS_QTB_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_LPASS_QTB_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_LPASS_QTB_SGDSCR_RETAIN_FF_ENABLE_BMSK 0x2 +#define HWIO_GCC_APCS_TZ_LPASS_QTB_SGDSCR_RETAIN_FF_ENABLE_SHFT 0x1 +#define HWIO_GCC_APCS_TZ_LPASS_QTB_SGDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_LPASS_QTB_SGDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_LPASS_QTB_SGDSCR_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_APCS_TZ_LPASS_QTB_SGDSCR_SW_OVERRIDE_SHFT 0x0 +#define HWIO_GCC_APCS_TZ_LPASS_QTB_SGDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_LPASS_QTB_SGDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_APCS_TZ_MMNOC_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00043034) +#define HWIO_GCC_APCS_TZ_MMNOC_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00043034) +#define HWIO_GCC_APCS_TZ_MMNOC_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00043034) +#define HWIO_GCC_APCS_TZ_MMNOC_SGDSCR_RMSK 0x7 +#define HWIO_GCC_APCS_TZ_MMNOC_SGDSCR_ATTR 0x3 +#define HWIO_GCC_APCS_TZ_MMNOC_SGDSCR_IN \ + in_dword_masked(HWIO_GCC_APCS_TZ_MMNOC_SGDSCR_ADDR, HWIO_GCC_APCS_TZ_MMNOC_SGDSCR_RMSK) +#define HWIO_GCC_APCS_TZ_MMNOC_SGDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_APCS_TZ_MMNOC_SGDSCR_ADDR, m) +#define HWIO_GCC_APCS_TZ_MMNOC_SGDSCR_OUT(v) \ + out_dword(HWIO_GCC_APCS_TZ_MMNOC_SGDSCR_ADDR,v) +#define HWIO_GCC_APCS_TZ_MMNOC_SGDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_APCS_TZ_MMNOC_SGDSCR_ADDR,m,v,HWIO_GCC_APCS_TZ_MMNOC_SGDSCR_IN) +#define HWIO_GCC_APCS_TZ_MMNOC_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4 +#define HWIO_GCC_APCS_TZ_MMNOC_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x2 +#define HWIO_GCC_APCS_TZ_MMNOC_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_MMNOC_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_MMNOC_SGDSCR_RETAIN_FF_ENABLE_BMSK 0x2 +#define HWIO_GCC_APCS_TZ_MMNOC_SGDSCR_RETAIN_FF_ENABLE_SHFT 0x1 +#define HWIO_GCC_APCS_TZ_MMNOC_SGDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_MMNOC_SGDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_MMNOC_SGDSCR_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_APCS_TZ_MMNOC_SGDSCR_SW_OVERRIDE_SHFT 0x0 +#define HWIO_GCC_APCS_TZ_MMNOC_SGDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_MMNOC_SGDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_Q6_IPA_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00025000) +#define HWIO_GCC_MSS_Q6_IPA_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00025000) +#define HWIO_GCC_MSS_Q6_IPA_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00025000) +#define HWIO_GCC_MSS_Q6_IPA_SGDSCR_RMSK 0x7 +#define HWIO_GCC_MSS_Q6_IPA_SGDSCR_ATTR 0x3 +#define HWIO_GCC_MSS_Q6_IPA_SGDSCR_IN \ + in_dword_masked(HWIO_GCC_MSS_Q6_IPA_SGDSCR_ADDR, HWIO_GCC_MSS_Q6_IPA_SGDSCR_RMSK) +#define HWIO_GCC_MSS_Q6_IPA_SGDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_Q6_IPA_SGDSCR_ADDR, m) +#define HWIO_GCC_MSS_Q6_IPA_SGDSCR_OUT(v) \ + out_dword(HWIO_GCC_MSS_Q6_IPA_SGDSCR_ADDR,v) +#define HWIO_GCC_MSS_Q6_IPA_SGDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_Q6_IPA_SGDSCR_ADDR,m,v,HWIO_GCC_MSS_Q6_IPA_SGDSCR_IN) +#define HWIO_GCC_MSS_Q6_IPA_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4 +#define HWIO_GCC_MSS_Q6_IPA_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x2 +#define HWIO_GCC_MSS_Q6_IPA_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_IPA_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_IPA_SGDSCR_RETAIN_FF_ENABLE_BMSK 0x2 +#define HWIO_GCC_MSS_Q6_IPA_SGDSCR_RETAIN_FF_ENABLE_SHFT 0x1 +#define HWIO_GCC_MSS_Q6_IPA_SGDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_IPA_SGDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_IPA_SGDSCR_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_MSS_Q6_IPA_SGDSCR_SW_OVERRIDE_SHFT 0x0 +#define HWIO_GCC_MSS_Q6_IPA_SGDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_IPA_SGDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_Q6_ANOC_PCIE_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00025004) +#define HWIO_GCC_MSS_Q6_ANOC_PCIE_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00025004) +#define HWIO_GCC_MSS_Q6_ANOC_PCIE_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00025004) +#define HWIO_GCC_MSS_Q6_ANOC_PCIE_SGDSCR_RMSK 0x7 +#define HWIO_GCC_MSS_Q6_ANOC_PCIE_SGDSCR_ATTR 0x3 +#define HWIO_GCC_MSS_Q6_ANOC_PCIE_SGDSCR_IN \ + in_dword_masked(HWIO_GCC_MSS_Q6_ANOC_PCIE_SGDSCR_ADDR, HWIO_GCC_MSS_Q6_ANOC_PCIE_SGDSCR_RMSK) +#define HWIO_GCC_MSS_Q6_ANOC_PCIE_SGDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_Q6_ANOC_PCIE_SGDSCR_ADDR, m) +#define HWIO_GCC_MSS_Q6_ANOC_PCIE_SGDSCR_OUT(v) \ + out_dword(HWIO_GCC_MSS_Q6_ANOC_PCIE_SGDSCR_ADDR,v) +#define HWIO_GCC_MSS_Q6_ANOC_PCIE_SGDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_Q6_ANOC_PCIE_SGDSCR_ADDR,m,v,HWIO_GCC_MSS_Q6_ANOC_PCIE_SGDSCR_IN) +#define HWIO_GCC_MSS_Q6_ANOC_PCIE_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4 +#define HWIO_GCC_MSS_Q6_ANOC_PCIE_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x2 +#define HWIO_GCC_MSS_Q6_ANOC_PCIE_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_ANOC_PCIE_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_ANOC_PCIE_SGDSCR_RETAIN_FF_ENABLE_BMSK 0x2 +#define HWIO_GCC_MSS_Q6_ANOC_PCIE_SGDSCR_RETAIN_FF_ENABLE_SHFT 0x1 +#define HWIO_GCC_MSS_Q6_ANOC_PCIE_SGDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_ANOC_PCIE_SGDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_ANOC_PCIE_SGDSCR_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_MSS_Q6_ANOC_PCIE_SGDSCR_SW_OVERRIDE_SHFT 0x0 +#define HWIO_GCC_MSS_Q6_ANOC_PCIE_SGDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_ANOC_PCIE_SGDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_Q6_PCIE_1_PHY_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00025008) +#define HWIO_GCC_MSS_Q6_PCIE_1_PHY_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00025008) +#define HWIO_GCC_MSS_Q6_PCIE_1_PHY_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00025008) +#define HWIO_GCC_MSS_Q6_PCIE_1_PHY_SGDSCR_RMSK 0x7 +#define HWIO_GCC_MSS_Q6_PCIE_1_PHY_SGDSCR_ATTR 0x3 +#define HWIO_GCC_MSS_Q6_PCIE_1_PHY_SGDSCR_IN \ + in_dword_masked(HWIO_GCC_MSS_Q6_PCIE_1_PHY_SGDSCR_ADDR, HWIO_GCC_MSS_Q6_PCIE_1_PHY_SGDSCR_RMSK) +#define HWIO_GCC_MSS_Q6_PCIE_1_PHY_SGDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_Q6_PCIE_1_PHY_SGDSCR_ADDR, m) +#define HWIO_GCC_MSS_Q6_PCIE_1_PHY_SGDSCR_OUT(v) \ + out_dword(HWIO_GCC_MSS_Q6_PCIE_1_PHY_SGDSCR_ADDR,v) +#define HWIO_GCC_MSS_Q6_PCIE_1_PHY_SGDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_Q6_PCIE_1_PHY_SGDSCR_ADDR,m,v,HWIO_GCC_MSS_Q6_PCIE_1_PHY_SGDSCR_IN) +#define HWIO_GCC_MSS_Q6_PCIE_1_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4 +#define HWIO_GCC_MSS_Q6_PCIE_1_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x2 +#define HWIO_GCC_MSS_Q6_PCIE_1_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_PCIE_1_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_PCIE_1_PHY_SGDSCR_RETAIN_FF_ENABLE_BMSK 0x2 +#define HWIO_GCC_MSS_Q6_PCIE_1_PHY_SGDSCR_RETAIN_FF_ENABLE_SHFT 0x1 +#define HWIO_GCC_MSS_Q6_PCIE_1_PHY_SGDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_PCIE_1_PHY_SGDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_PCIE_1_PHY_SGDSCR_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_MSS_Q6_PCIE_1_PHY_SGDSCR_SW_OVERRIDE_SHFT 0x0 +#define HWIO_GCC_MSS_Q6_PCIE_1_PHY_SGDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_PCIE_1_PHY_SGDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_Q6_USB30_PRIM_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002500c) +#define HWIO_GCC_MSS_Q6_USB30_PRIM_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002500c) +#define HWIO_GCC_MSS_Q6_USB30_PRIM_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002500c) +#define HWIO_GCC_MSS_Q6_USB30_PRIM_SGDSCR_RMSK 0x7 +#define HWIO_GCC_MSS_Q6_USB30_PRIM_SGDSCR_ATTR 0x3 +#define HWIO_GCC_MSS_Q6_USB30_PRIM_SGDSCR_IN \ + in_dword_masked(HWIO_GCC_MSS_Q6_USB30_PRIM_SGDSCR_ADDR, HWIO_GCC_MSS_Q6_USB30_PRIM_SGDSCR_RMSK) +#define HWIO_GCC_MSS_Q6_USB30_PRIM_SGDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_Q6_USB30_PRIM_SGDSCR_ADDR, m) +#define HWIO_GCC_MSS_Q6_USB30_PRIM_SGDSCR_OUT(v) \ + out_dword(HWIO_GCC_MSS_Q6_USB30_PRIM_SGDSCR_ADDR,v) +#define HWIO_GCC_MSS_Q6_USB30_PRIM_SGDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_Q6_USB30_PRIM_SGDSCR_ADDR,m,v,HWIO_GCC_MSS_Q6_USB30_PRIM_SGDSCR_IN) +#define HWIO_GCC_MSS_Q6_USB30_PRIM_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4 +#define HWIO_GCC_MSS_Q6_USB30_PRIM_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x2 +#define HWIO_GCC_MSS_Q6_USB30_PRIM_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_USB30_PRIM_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_USB30_PRIM_SGDSCR_RETAIN_FF_ENABLE_BMSK 0x2 +#define HWIO_GCC_MSS_Q6_USB30_PRIM_SGDSCR_RETAIN_FF_ENABLE_SHFT 0x1 +#define HWIO_GCC_MSS_Q6_USB30_PRIM_SGDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_USB30_PRIM_SGDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_USB30_PRIM_SGDSCR_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_MSS_Q6_USB30_PRIM_SGDSCR_SW_OVERRIDE_SHFT 0x0 +#define HWIO_GCC_MSS_Q6_USB30_PRIM_SGDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_USB30_PRIM_SGDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_Q6_UFS_PHY_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00025010) +#define HWIO_GCC_MSS_Q6_UFS_PHY_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00025010) +#define HWIO_GCC_MSS_Q6_UFS_PHY_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00025010) +#define HWIO_GCC_MSS_Q6_UFS_PHY_SGDSCR_RMSK 0x7 +#define HWIO_GCC_MSS_Q6_UFS_PHY_SGDSCR_ATTR 0x3 +#define HWIO_GCC_MSS_Q6_UFS_PHY_SGDSCR_IN \ + in_dword_masked(HWIO_GCC_MSS_Q6_UFS_PHY_SGDSCR_ADDR, HWIO_GCC_MSS_Q6_UFS_PHY_SGDSCR_RMSK) +#define HWIO_GCC_MSS_Q6_UFS_PHY_SGDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_Q6_UFS_PHY_SGDSCR_ADDR, m) +#define HWIO_GCC_MSS_Q6_UFS_PHY_SGDSCR_OUT(v) \ + out_dword(HWIO_GCC_MSS_Q6_UFS_PHY_SGDSCR_ADDR,v) +#define HWIO_GCC_MSS_Q6_UFS_PHY_SGDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_Q6_UFS_PHY_SGDSCR_ADDR,m,v,HWIO_GCC_MSS_Q6_UFS_PHY_SGDSCR_IN) +#define HWIO_GCC_MSS_Q6_UFS_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4 +#define HWIO_GCC_MSS_Q6_UFS_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x2 +#define HWIO_GCC_MSS_Q6_UFS_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_UFS_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_UFS_PHY_SGDSCR_RETAIN_FF_ENABLE_BMSK 0x2 +#define HWIO_GCC_MSS_Q6_UFS_PHY_SGDSCR_RETAIN_FF_ENABLE_SHFT 0x1 +#define HWIO_GCC_MSS_Q6_UFS_PHY_SGDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_UFS_PHY_SGDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_UFS_PHY_SGDSCR_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_MSS_Q6_UFS_PHY_SGDSCR_SW_OVERRIDE_SHFT 0x0 +#define HWIO_GCC_MSS_Q6_UFS_PHY_SGDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_UFS_PHY_SGDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_Q6_USB3_PHY_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00025014) +#define HWIO_GCC_MSS_Q6_USB3_PHY_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00025014) +#define HWIO_GCC_MSS_Q6_USB3_PHY_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00025014) +#define HWIO_GCC_MSS_Q6_USB3_PHY_SGDSCR_RMSK 0x7 +#define HWIO_GCC_MSS_Q6_USB3_PHY_SGDSCR_ATTR 0x3 +#define HWIO_GCC_MSS_Q6_USB3_PHY_SGDSCR_IN \ + in_dword_masked(HWIO_GCC_MSS_Q6_USB3_PHY_SGDSCR_ADDR, HWIO_GCC_MSS_Q6_USB3_PHY_SGDSCR_RMSK) +#define HWIO_GCC_MSS_Q6_USB3_PHY_SGDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_Q6_USB3_PHY_SGDSCR_ADDR, m) +#define HWIO_GCC_MSS_Q6_USB3_PHY_SGDSCR_OUT(v) \ + out_dword(HWIO_GCC_MSS_Q6_USB3_PHY_SGDSCR_ADDR,v) +#define HWIO_GCC_MSS_Q6_USB3_PHY_SGDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_Q6_USB3_PHY_SGDSCR_ADDR,m,v,HWIO_GCC_MSS_Q6_USB3_PHY_SGDSCR_IN) +#define HWIO_GCC_MSS_Q6_USB3_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4 +#define HWIO_GCC_MSS_Q6_USB3_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x2 +#define HWIO_GCC_MSS_Q6_USB3_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_USB3_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_USB3_PHY_SGDSCR_RETAIN_FF_ENABLE_BMSK 0x2 +#define HWIO_GCC_MSS_Q6_USB3_PHY_SGDSCR_RETAIN_FF_ENABLE_SHFT 0x1 +#define HWIO_GCC_MSS_Q6_USB3_PHY_SGDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_USB3_PHY_SGDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_USB3_PHY_SGDSCR_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_MSS_Q6_USB3_PHY_SGDSCR_SW_OVERRIDE_SHFT 0x0 +#define HWIO_GCC_MSS_Q6_USB3_PHY_SGDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_USB3_PHY_SGDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_Q6_MMU_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00025018) +#define HWIO_GCC_MSS_Q6_MMU_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00025018) +#define HWIO_GCC_MSS_Q6_MMU_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00025018) +#define HWIO_GCC_MSS_Q6_MMU_SGDSCR_RMSK 0x7 +#define HWIO_GCC_MSS_Q6_MMU_SGDSCR_ATTR 0x3 +#define HWIO_GCC_MSS_Q6_MMU_SGDSCR_IN \ + in_dword_masked(HWIO_GCC_MSS_Q6_MMU_SGDSCR_ADDR, HWIO_GCC_MSS_Q6_MMU_SGDSCR_RMSK) +#define HWIO_GCC_MSS_Q6_MMU_SGDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_Q6_MMU_SGDSCR_ADDR, m) +#define HWIO_GCC_MSS_Q6_MMU_SGDSCR_OUT(v) \ + out_dword(HWIO_GCC_MSS_Q6_MMU_SGDSCR_ADDR,v) +#define HWIO_GCC_MSS_Q6_MMU_SGDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_Q6_MMU_SGDSCR_ADDR,m,v,HWIO_GCC_MSS_Q6_MMU_SGDSCR_IN) +#define HWIO_GCC_MSS_Q6_MMU_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4 +#define HWIO_GCC_MSS_Q6_MMU_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x2 +#define HWIO_GCC_MSS_Q6_MMU_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_MMU_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_MMU_SGDSCR_RETAIN_FF_ENABLE_BMSK 0x2 +#define HWIO_GCC_MSS_Q6_MMU_SGDSCR_RETAIN_FF_ENABLE_SHFT 0x1 +#define HWIO_GCC_MSS_Q6_MMU_SGDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_MMU_SGDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_MMU_SGDSCR_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_MSS_Q6_MMU_SGDSCR_SW_OVERRIDE_SHFT 0x0 +#define HWIO_GCC_MSS_Q6_MMU_SGDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_MMU_SGDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_Q6_PCIE_1_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002501c) +#define HWIO_GCC_MSS_Q6_PCIE_1_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002501c) +#define HWIO_GCC_MSS_Q6_PCIE_1_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002501c) +#define HWIO_GCC_MSS_Q6_PCIE_1_SGDSCR_RMSK 0x7 +#define HWIO_GCC_MSS_Q6_PCIE_1_SGDSCR_ATTR 0x3 +#define HWIO_GCC_MSS_Q6_PCIE_1_SGDSCR_IN \ + in_dword_masked(HWIO_GCC_MSS_Q6_PCIE_1_SGDSCR_ADDR, HWIO_GCC_MSS_Q6_PCIE_1_SGDSCR_RMSK) +#define HWIO_GCC_MSS_Q6_PCIE_1_SGDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_Q6_PCIE_1_SGDSCR_ADDR, m) +#define HWIO_GCC_MSS_Q6_PCIE_1_SGDSCR_OUT(v) \ + out_dword(HWIO_GCC_MSS_Q6_PCIE_1_SGDSCR_ADDR,v) +#define HWIO_GCC_MSS_Q6_PCIE_1_SGDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_Q6_PCIE_1_SGDSCR_ADDR,m,v,HWIO_GCC_MSS_Q6_PCIE_1_SGDSCR_IN) +#define HWIO_GCC_MSS_Q6_PCIE_1_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4 +#define HWIO_GCC_MSS_Q6_PCIE_1_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x2 +#define HWIO_GCC_MSS_Q6_PCIE_1_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_PCIE_1_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_PCIE_1_SGDSCR_RETAIN_FF_ENABLE_BMSK 0x2 +#define HWIO_GCC_MSS_Q6_PCIE_1_SGDSCR_RETAIN_FF_ENABLE_SHFT 0x1 +#define HWIO_GCC_MSS_Q6_PCIE_1_SGDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_PCIE_1_SGDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_PCIE_1_SGDSCR_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_MSS_Q6_PCIE_1_SGDSCR_SW_OVERRIDE_SHFT 0x0 +#define HWIO_GCC_MSS_Q6_PCIE_1_SGDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_PCIE_1_SGDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_Q6_PCIE_0_PHY_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00025020) +#define HWIO_GCC_MSS_Q6_PCIE_0_PHY_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00025020) +#define HWIO_GCC_MSS_Q6_PCIE_0_PHY_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00025020) +#define HWIO_GCC_MSS_Q6_PCIE_0_PHY_SGDSCR_RMSK 0x7 +#define HWIO_GCC_MSS_Q6_PCIE_0_PHY_SGDSCR_ATTR 0x3 +#define HWIO_GCC_MSS_Q6_PCIE_0_PHY_SGDSCR_IN \ + in_dword_masked(HWIO_GCC_MSS_Q6_PCIE_0_PHY_SGDSCR_ADDR, HWIO_GCC_MSS_Q6_PCIE_0_PHY_SGDSCR_RMSK) +#define HWIO_GCC_MSS_Q6_PCIE_0_PHY_SGDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_Q6_PCIE_0_PHY_SGDSCR_ADDR, m) +#define HWIO_GCC_MSS_Q6_PCIE_0_PHY_SGDSCR_OUT(v) \ + out_dword(HWIO_GCC_MSS_Q6_PCIE_0_PHY_SGDSCR_ADDR,v) +#define HWIO_GCC_MSS_Q6_PCIE_0_PHY_SGDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_Q6_PCIE_0_PHY_SGDSCR_ADDR,m,v,HWIO_GCC_MSS_Q6_PCIE_0_PHY_SGDSCR_IN) +#define HWIO_GCC_MSS_Q6_PCIE_0_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4 +#define HWIO_GCC_MSS_Q6_PCIE_0_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x2 +#define HWIO_GCC_MSS_Q6_PCIE_0_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_PCIE_0_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_PCIE_0_PHY_SGDSCR_RETAIN_FF_ENABLE_BMSK 0x2 +#define HWIO_GCC_MSS_Q6_PCIE_0_PHY_SGDSCR_RETAIN_FF_ENABLE_SHFT 0x1 +#define HWIO_GCC_MSS_Q6_PCIE_0_PHY_SGDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_PCIE_0_PHY_SGDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_PCIE_0_PHY_SGDSCR_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_MSS_Q6_PCIE_0_PHY_SGDSCR_SW_OVERRIDE_SHFT 0x0 +#define HWIO_GCC_MSS_Q6_PCIE_0_PHY_SGDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_PCIE_0_PHY_SGDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_Q6_TURING_QTB_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00025024) +#define HWIO_GCC_MSS_Q6_TURING_QTB_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00025024) +#define HWIO_GCC_MSS_Q6_TURING_QTB_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00025024) +#define HWIO_GCC_MSS_Q6_TURING_QTB_SGDSCR_RMSK 0x7 +#define HWIO_GCC_MSS_Q6_TURING_QTB_SGDSCR_ATTR 0x3 +#define HWIO_GCC_MSS_Q6_TURING_QTB_SGDSCR_IN \ + in_dword_masked(HWIO_GCC_MSS_Q6_TURING_QTB_SGDSCR_ADDR, HWIO_GCC_MSS_Q6_TURING_QTB_SGDSCR_RMSK) +#define HWIO_GCC_MSS_Q6_TURING_QTB_SGDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_Q6_TURING_QTB_SGDSCR_ADDR, m) +#define HWIO_GCC_MSS_Q6_TURING_QTB_SGDSCR_OUT(v) \ + out_dword(HWIO_GCC_MSS_Q6_TURING_QTB_SGDSCR_ADDR,v) +#define HWIO_GCC_MSS_Q6_TURING_QTB_SGDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_Q6_TURING_QTB_SGDSCR_ADDR,m,v,HWIO_GCC_MSS_Q6_TURING_QTB_SGDSCR_IN) +#define HWIO_GCC_MSS_Q6_TURING_QTB_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4 +#define HWIO_GCC_MSS_Q6_TURING_QTB_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x2 +#define HWIO_GCC_MSS_Q6_TURING_QTB_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_TURING_QTB_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_TURING_QTB_SGDSCR_RETAIN_FF_ENABLE_BMSK 0x2 +#define HWIO_GCC_MSS_Q6_TURING_QTB_SGDSCR_RETAIN_FF_ENABLE_SHFT 0x1 +#define HWIO_GCC_MSS_Q6_TURING_QTB_SGDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_TURING_QTB_SGDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_TURING_QTB_SGDSCR_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_MSS_Q6_TURING_QTB_SGDSCR_SW_OVERRIDE_SHFT 0x0 +#define HWIO_GCC_MSS_Q6_TURING_QTB_SGDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_TURING_QTB_SGDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_Q6_UFS_MEM_PHY_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00025028) +#define HWIO_GCC_MSS_Q6_UFS_MEM_PHY_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00025028) +#define HWIO_GCC_MSS_Q6_UFS_MEM_PHY_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00025028) +#define HWIO_GCC_MSS_Q6_UFS_MEM_PHY_SGDSCR_RMSK 0x7 +#define HWIO_GCC_MSS_Q6_UFS_MEM_PHY_SGDSCR_ATTR 0x3 +#define HWIO_GCC_MSS_Q6_UFS_MEM_PHY_SGDSCR_IN \ + in_dword_masked(HWIO_GCC_MSS_Q6_UFS_MEM_PHY_SGDSCR_ADDR, HWIO_GCC_MSS_Q6_UFS_MEM_PHY_SGDSCR_RMSK) +#define HWIO_GCC_MSS_Q6_UFS_MEM_PHY_SGDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_Q6_UFS_MEM_PHY_SGDSCR_ADDR, m) +#define HWIO_GCC_MSS_Q6_UFS_MEM_PHY_SGDSCR_OUT(v) \ + out_dword(HWIO_GCC_MSS_Q6_UFS_MEM_PHY_SGDSCR_ADDR,v) +#define HWIO_GCC_MSS_Q6_UFS_MEM_PHY_SGDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_Q6_UFS_MEM_PHY_SGDSCR_ADDR,m,v,HWIO_GCC_MSS_Q6_UFS_MEM_PHY_SGDSCR_IN) +#define HWIO_GCC_MSS_Q6_UFS_MEM_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4 +#define HWIO_GCC_MSS_Q6_UFS_MEM_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x2 +#define HWIO_GCC_MSS_Q6_UFS_MEM_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_UFS_MEM_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_UFS_MEM_PHY_SGDSCR_RETAIN_FF_ENABLE_BMSK 0x2 +#define HWIO_GCC_MSS_Q6_UFS_MEM_PHY_SGDSCR_RETAIN_FF_ENABLE_SHFT 0x1 +#define HWIO_GCC_MSS_Q6_UFS_MEM_PHY_SGDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_UFS_MEM_PHY_SGDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_UFS_MEM_PHY_SGDSCR_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_MSS_Q6_UFS_MEM_PHY_SGDSCR_SW_OVERRIDE_SHFT 0x0 +#define HWIO_GCC_MSS_Q6_UFS_MEM_PHY_SGDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_UFS_MEM_PHY_SGDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_Q6_PCIE_0_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002502c) +#define HWIO_GCC_MSS_Q6_PCIE_0_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002502c) +#define HWIO_GCC_MSS_Q6_PCIE_0_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002502c) +#define HWIO_GCC_MSS_Q6_PCIE_0_SGDSCR_RMSK 0x7 +#define HWIO_GCC_MSS_Q6_PCIE_0_SGDSCR_ATTR 0x3 +#define HWIO_GCC_MSS_Q6_PCIE_0_SGDSCR_IN \ + in_dword_masked(HWIO_GCC_MSS_Q6_PCIE_0_SGDSCR_ADDR, HWIO_GCC_MSS_Q6_PCIE_0_SGDSCR_RMSK) +#define HWIO_GCC_MSS_Q6_PCIE_0_SGDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_Q6_PCIE_0_SGDSCR_ADDR, m) +#define HWIO_GCC_MSS_Q6_PCIE_0_SGDSCR_OUT(v) \ + out_dword(HWIO_GCC_MSS_Q6_PCIE_0_SGDSCR_ADDR,v) +#define HWIO_GCC_MSS_Q6_PCIE_0_SGDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_Q6_PCIE_0_SGDSCR_ADDR,m,v,HWIO_GCC_MSS_Q6_PCIE_0_SGDSCR_IN) +#define HWIO_GCC_MSS_Q6_PCIE_0_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4 +#define HWIO_GCC_MSS_Q6_PCIE_0_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x2 +#define HWIO_GCC_MSS_Q6_PCIE_0_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_PCIE_0_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_PCIE_0_SGDSCR_RETAIN_FF_ENABLE_BMSK 0x2 +#define HWIO_GCC_MSS_Q6_PCIE_0_SGDSCR_RETAIN_FF_ENABLE_SHFT 0x1 +#define HWIO_GCC_MSS_Q6_PCIE_0_SGDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_PCIE_0_SGDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_PCIE_0_SGDSCR_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_MSS_Q6_PCIE_0_SGDSCR_SW_OVERRIDE_SHFT 0x0 +#define HWIO_GCC_MSS_Q6_PCIE_0_SGDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_PCIE_0_SGDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_Q6_LPASS_QTB_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00025030) +#define HWIO_GCC_MSS_Q6_LPASS_QTB_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00025030) +#define HWIO_GCC_MSS_Q6_LPASS_QTB_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00025030) +#define HWIO_GCC_MSS_Q6_LPASS_QTB_SGDSCR_RMSK 0x7 +#define HWIO_GCC_MSS_Q6_LPASS_QTB_SGDSCR_ATTR 0x3 +#define HWIO_GCC_MSS_Q6_LPASS_QTB_SGDSCR_IN \ + in_dword_masked(HWIO_GCC_MSS_Q6_LPASS_QTB_SGDSCR_ADDR, HWIO_GCC_MSS_Q6_LPASS_QTB_SGDSCR_RMSK) +#define HWIO_GCC_MSS_Q6_LPASS_QTB_SGDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_Q6_LPASS_QTB_SGDSCR_ADDR, m) +#define HWIO_GCC_MSS_Q6_LPASS_QTB_SGDSCR_OUT(v) \ + out_dword(HWIO_GCC_MSS_Q6_LPASS_QTB_SGDSCR_ADDR,v) +#define HWIO_GCC_MSS_Q6_LPASS_QTB_SGDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_Q6_LPASS_QTB_SGDSCR_ADDR,m,v,HWIO_GCC_MSS_Q6_LPASS_QTB_SGDSCR_IN) +#define HWIO_GCC_MSS_Q6_LPASS_QTB_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4 +#define HWIO_GCC_MSS_Q6_LPASS_QTB_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x2 +#define HWIO_GCC_MSS_Q6_LPASS_QTB_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_LPASS_QTB_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_LPASS_QTB_SGDSCR_RETAIN_FF_ENABLE_BMSK 0x2 +#define HWIO_GCC_MSS_Q6_LPASS_QTB_SGDSCR_RETAIN_FF_ENABLE_SHFT 0x1 +#define HWIO_GCC_MSS_Q6_LPASS_QTB_SGDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_LPASS_QTB_SGDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_LPASS_QTB_SGDSCR_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_MSS_Q6_LPASS_QTB_SGDSCR_SW_OVERRIDE_SHFT 0x0 +#define HWIO_GCC_MSS_Q6_LPASS_QTB_SGDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_LPASS_QTB_SGDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_Q6_MMNOC_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00025034) +#define HWIO_GCC_MSS_Q6_MMNOC_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00025034) +#define HWIO_GCC_MSS_Q6_MMNOC_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00025034) +#define HWIO_GCC_MSS_Q6_MMNOC_SGDSCR_RMSK 0x7 +#define HWIO_GCC_MSS_Q6_MMNOC_SGDSCR_ATTR 0x3 +#define HWIO_GCC_MSS_Q6_MMNOC_SGDSCR_IN \ + in_dword_masked(HWIO_GCC_MSS_Q6_MMNOC_SGDSCR_ADDR, HWIO_GCC_MSS_Q6_MMNOC_SGDSCR_RMSK) +#define HWIO_GCC_MSS_Q6_MMNOC_SGDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_Q6_MMNOC_SGDSCR_ADDR, m) +#define HWIO_GCC_MSS_Q6_MMNOC_SGDSCR_OUT(v) \ + out_dword(HWIO_GCC_MSS_Q6_MMNOC_SGDSCR_ADDR,v) +#define HWIO_GCC_MSS_Q6_MMNOC_SGDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_Q6_MMNOC_SGDSCR_ADDR,m,v,HWIO_GCC_MSS_Q6_MMNOC_SGDSCR_IN) +#define HWIO_GCC_MSS_Q6_MMNOC_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4 +#define HWIO_GCC_MSS_Q6_MMNOC_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x2 +#define HWIO_GCC_MSS_Q6_MMNOC_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_MMNOC_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_MMNOC_SGDSCR_RETAIN_FF_ENABLE_BMSK 0x2 +#define HWIO_GCC_MSS_Q6_MMNOC_SGDSCR_RETAIN_FF_ENABLE_SHFT 0x1 +#define HWIO_GCC_MSS_Q6_MMNOC_SGDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_MMNOC_SGDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_MMNOC_SGDSCR_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_MSS_Q6_MMNOC_SGDSCR_SW_OVERRIDE_SHFT 0x0 +#define HWIO_GCC_MSS_Q6_MMNOC_SGDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_MMNOC_SGDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TME_IPA_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00059000) +#define HWIO_GCC_TME_IPA_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00059000) +#define HWIO_GCC_TME_IPA_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00059000) +#define HWIO_GCC_TME_IPA_SGDSCR_RMSK 0x7 +#define HWIO_GCC_TME_IPA_SGDSCR_ATTR 0x3 +#define HWIO_GCC_TME_IPA_SGDSCR_IN \ + in_dword_masked(HWIO_GCC_TME_IPA_SGDSCR_ADDR, HWIO_GCC_TME_IPA_SGDSCR_RMSK) +#define HWIO_GCC_TME_IPA_SGDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_TME_IPA_SGDSCR_ADDR, m) +#define HWIO_GCC_TME_IPA_SGDSCR_OUT(v) \ + out_dword(HWIO_GCC_TME_IPA_SGDSCR_ADDR,v) +#define HWIO_GCC_TME_IPA_SGDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TME_IPA_SGDSCR_ADDR,m,v,HWIO_GCC_TME_IPA_SGDSCR_IN) +#define HWIO_GCC_TME_IPA_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4 +#define HWIO_GCC_TME_IPA_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x2 +#define HWIO_GCC_TME_IPA_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_IPA_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_IPA_SGDSCR_RETAIN_FF_ENABLE_BMSK 0x2 +#define HWIO_GCC_TME_IPA_SGDSCR_RETAIN_FF_ENABLE_SHFT 0x1 +#define HWIO_GCC_TME_IPA_SGDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_IPA_SGDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_IPA_SGDSCR_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_TME_IPA_SGDSCR_SW_OVERRIDE_SHFT 0x0 +#define HWIO_GCC_TME_IPA_SGDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_IPA_SGDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TME_ANOC_PCIE_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00059004) +#define HWIO_GCC_TME_ANOC_PCIE_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00059004) +#define HWIO_GCC_TME_ANOC_PCIE_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00059004) +#define HWIO_GCC_TME_ANOC_PCIE_SGDSCR_RMSK 0x7 +#define HWIO_GCC_TME_ANOC_PCIE_SGDSCR_ATTR 0x3 +#define HWIO_GCC_TME_ANOC_PCIE_SGDSCR_IN \ + in_dword_masked(HWIO_GCC_TME_ANOC_PCIE_SGDSCR_ADDR, HWIO_GCC_TME_ANOC_PCIE_SGDSCR_RMSK) +#define HWIO_GCC_TME_ANOC_PCIE_SGDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_TME_ANOC_PCIE_SGDSCR_ADDR, m) +#define HWIO_GCC_TME_ANOC_PCIE_SGDSCR_OUT(v) \ + out_dword(HWIO_GCC_TME_ANOC_PCIE_SGDSCR_ADDR,v) +#define HWIO_GCC_TME_ANOC_PCIE_SGDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TME_ANOC_PCIE_SGDSCR_ADDR,m,v,HWIO_GCC_TME_ANOC_PCIE_SGDSCR_IN) +#define HWIO_GCC_TME_ANOC_PCIE_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4 +#define HWIO_GCC_TME_ANOC_PCIE_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x2 +#define HWIO_GCC_TME_ANOC_PCIE_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_ANOC_PCIE_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_ANOC_PCIE_SGDSCR_RETAIN_FF_ENABLE_BMSK 0x2 +#define HWIO_GCC_TME_ANOC_PCIE_SGDSCR_RETAIN_FF_ENABLE_SHFT 0x1 +#define HWIO_GCC_TME_ANOC_PCIE_SGDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_ANOC_PCIE_SGDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_ANOC_PCIE_SGDSCR_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_TME_ANOC_PCIE_SGDSCR_SW_OVERRIDE_SHFT 0x0 +#define HWIO_GCC_TME_ANOC_PCIE_SGDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_ANOC_PCIE_SGDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TME_PCIE_1_PHY_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00059008) +#define HWIO_GCC_TME_PCIE_1_PHY_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00059008) +#define HWIO_GCC_TME_PCIE_1_PHY_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00059008) +#define HWIO_GCC_TME_PCIE_1_PHY_SGDSCR_RMSK 0x7 +#define HWIO_GCC_TME_PCIE_1_PHY_SGDSCR_ATTR 0x3 +#define HWIO_GCC_TME_PCIE_1_PHY_SGDSCR_IN \ + in_dword_masked(HWIO_GCC_TME_PCIE_1_PHY_SGDSCR_ADDR, HWIO_GCC_TME_PCIE_1_PHY_SGDSCR_RMSK) +#define HWIO_GCC_TME_PCIE_1_PHY_SGDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_TME_PCIE_1_PHY_SGDSCR_ADDR, m) +#define HWIO_GCC_TME_PCIE_1_PHY_SGDSCR_OUT(v) \ + out_dword(HWIO_GCC_TME_PCIE_1_PHY_SGDSCR_ADDR,v) +#define HWIO_GCC_TME_PCIE_1_PHY_SGDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TME_PCIE_1_PHY_SGDSCR_ADDR,m,v,HWIO_GCC_TME_PCIE_1_PHY_SGDSCR_IN) +#define HWIO_GCC_TME_PCIE_1_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4 +#define HWIO_GCC_TME_PCIE_1_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x2 +#define HWIO_GCC_TME_PCIE_1_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_PCIE_1_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_PCIE_1_PHY_SGDSCR_RETAIN_FF_ENABLE_BMSK 0x2 +#define HWIO_GCC_TME_PCIE_1_PHY_SGDSCR_RETAIN_FF_ENABLE_SHFT 0x1 +#define HWIO_GCC_TME_PCIE_1_PHY_SGDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_PCIE_1_PHY_SGDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_PCIE_1_PHY_SGDSCR_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_TME_PCIE_1_PHY_SGDSCR_SW_OVERRIDE_SHFT 0x0 +#define HWIO_GCC_TME_PCIE_1_PHY_SGDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_PCIE_1_PHY_SGDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TME_USB30_PRIM_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005900c) +#define HWIO_GCC_TME_USB30_PRIM_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005900c) +#define HWIO_GCC_TME_USB30_PRIM_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005900c) +#define HWIO_GCC_TME_USB30_PRIM_SGDSCR_RMSK 0x7 +#define HWIO_GCC_TME_USB30_PRIM_SGDSCR_ATTR 0x3 +#define HWIO_GCC_TME_USB30_PRIM_SGDSCR_IN \ + in_dword_masked(HWIO_GCC_TME_USB30_PRIM_SGDSCR_ADDR, HWIO_GCC_TME_USB30_PRIM_SGDSCR_RMSK) +#define HWIO_GCC_TME_USB30_PRIM_SGDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_TME_USB30_PRIM_SGDSCR_ADDR, m) +#define HWIO_GCC_TME_USB30_PRIM_SGDSCR_OUT(v) \ + out_dword(HWIO_GCC_TME_USB30_PRIM_SGDSCR_ADDR,v) +#define HWIO_GCC_TME_USB30_PRIM_SGDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TME_USB30_PRIM_SGDSCR_ADDR,m,v,HWIO_GCC_TME_USB30_PRIM_SGDSCR_IN) +#define HWIO_GCC_TME_USB30_PRIM_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4 +#define HWIO_GCC_TME_USB30_PRIM_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x2 +#define HWIO_GCC_TME_USB30_PRIM_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_USB30_PRIM_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_USB30_PRIM_SGDSCR_RETAIN_FF_ENABLE_BMSK 0x2 +#define HWIO_GCC_TME_USB30_PRIM_SGDSCR_RETAIN_FF_ENABLE_SHFT 0x1 +#define HWIO_GCC_TME_USB30_PRIM_SGDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_USB30_PRIM_SGDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_USB30_PRIM_SGDSCR_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_TME_USB30_PRIM_SGDSCR_SW_OVERRIDE_SHFT 0x0 +#define HWIO_GCC_TME_USB30_PRIM_SGDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_USB30_PRIM_SGDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TME_UFS_PHY_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00059010) +#define HWIO_GCC_TME_UFS_PHY_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00059010) +#define HWIO_GCC_TME_UFS_PHY_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00059010) +#define HWIO_GCC_TME_UFS_PHY_SGDSCR_RMSK 0x7 +#define HWIO_GCC_TME_UFS_PHY_SGDSCR_ATTR 0x3 +#define HWIO_GCC_TME_UFS_PHY_SGDSCR_IN \ + in_dword_masked(HWIO_GCC_TME_UFS_PHY_SGDSCR_ADDR, HWIO_GCC_TME_UFS_PHY_SGDSCR_RMSK) +#define HWIO_GCC_TME_UFS_PHY_SGDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_TME_UFS_PHY_SGDSCR_ADDR, m) +#define HWIO_GCC_TME_UFS_PHY_SGDSCR_OUT(v) \ + out_dword(HWIO_GCC_TME_UFS_PHY_SGDSCR_ADDR,v) +#define HWIO_GCC_TME_UFS_PHY_SGDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TME_UFS_PHY_SGDSCR_ADDR,m,v,HWIO_GCC_TME_UFS_PHY_SGDSCR_IN) +#define HWIO_GCC_TME_UFS_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4 +#define HWIO_GCC_TME_UFS_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x2 +#define HWIO_GCC_TME_UFS_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_UFS_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_UFS_PHY_SGDSCR_RETAIN_FF_ENABLE_BMSK 0x2 +#define HWIO_GCC_TME_UFS_PHY_SGDSCR_RETAIN_FF_ENABLE_SHFT 0x1 +#define HWIO_GCC_TME_UFS_PHY_SGDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_UFS_PHY_SGDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_UFS_PHY_SGDSCR_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_TME_UFS_PHY_SGDSCR_SW_OVERRIDE_SHFT 0x0 +#define HWIO_GCC_TME_UFS_PHY_SGDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_UFS_PHY_SGDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TME_USB3_PHY_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00059014) +#define HWIO_GCC_TME_USB3_PHY_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00059014) +#define HWIO_GCC_TME_USB3_PHY_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00059014) +#define HWIO_GCC_TME_USB3_PHY_SGDSCR_RMSK 0x7 +#define HWIO_GCC_TME_USB3_PHY_SGDSCR_ATTR 0x3 +#define HWIO_GCC_TME_USB3_PHY_SGDSCR_IN \ + in_dword_masked(HWIO_GCC_TME_USB3_PHY_SGDSCR_ADDR, HWIO_GCC_TME_USB3_PHY_SGDSCR_RMSK) +#define HWIO_GCC_TME_USB3_PHY_SGDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_TME_USB3_PHY_SGDSCR_ADDR, m) +#define HWIO_GCC_TME_USB3_PHY_SGDSCR_OUT(v) \ + out_dword(HWIO_GCC_TME_USB3_PHY_SGDSCR_ADDR,v) +#define HWIO_GCC_TME_USB3_PHY_SGDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TME_USB3_PHY_SGDSCR_ADDR,m,v,HWIO_GCC_TME_USB3_PHY_SGDSCR_IN) +#define HWIO_GCC_TME_USB3_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4 +#define HWIO_GCC_TME_USB3_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x2 +#define HWIO_GCC_TME_USB3_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_USB3_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_USB3_PHY_SGDSCR_RETAIN_FF_ENABLE_BMSK 0x2 +#define HWIO_GCC_TME_USB3_PHY_SGDSCR_RETAIN_FF_ENABLE_SHFT 0x1 +#define HWIO_GCC_TME_USB3_PHY_SGDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_USB3_PHY_SGDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_USB3_PHY_SGDSCR_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_TME_USB3_PHY_SGDSCR_SW_OVERRIDE_SHFT 0x0 +#define HWIO_GCC_TME_USB3_PHY_SGDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_USB3_PHY_SGDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TME_MMU_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00059018) +#define HWIO_GCC_TME_MMU_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00059018) +#define HWIO_GCC_TME_MMU_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00059018) +#define HWIO_GCC_TME_MMU_SGDSCR_RMSK 0x7 +#define HWIO_GCC_TME_MMU_SGDSCR_ATTR 0x3 +#define HWIO_GCC_TME_MMU_SGDSCR_IN \ + in_dword_masked(HWIO_GCC_TME_MMU_SGDSCR_ADDR, HWIO_GCC_TME_MMU_SGDSCR_RMSK) +#define HWIO_GCC_TME_MMU_SGDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_TME_MMU_SGDSCR_ADDR, m) +#define HWIO_GCC_TME_MMU_SGDSCR_OUT(v) \ + out_dword(HWIO_GCC_TME_MMU_SGDSCR_ADDR,v) +#define HWIO_GCC_TME_MMU_SGDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TME_MMU_SGDSCR_ADDR,m,v,HWIO_GCC_TME_MMU_SGDSCR_IN) +#define HWIO_GCC_TME_MMU_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4 +#define HWIO_GCC_TME_MMU_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x2 +#define HWIO_GCC_TME_MMU_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_MMU_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_MMU_SGDSCR_RETAIN_FF_ENABLE_BMSK 0x2 +#define HWIO_GCC_TME_MMU_SGDSCR_RETAIN_FF_ENABLE_SHFT 0x1 +#define HWIO_GCC_TME_MMU_SGDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_MMU_SGDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_MMU_SGDSCR_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_TME_MMU_SGDSCR_SW_OVERRIDE_SHFT 0x0 +#define HWIO_GCC_TME_MMU_SGDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_MMU_SGDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TME_PCIE_1_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005901c) +#define HWIO_GCC_TME_PCIE_1_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005901c) +#define HWIO_GCC_TME_PCIE_1_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005901c) +#define HWIO_GCC_TME_PCIE_1_SGDSCR_RMSK 0x7 +#define HWIO_GCC_TME_PCIE_1_SGDSCR_ATTR 0x3 +#define HWIO_GCC_TME_PCIE_1_SGDSCR_IN \ + in_dword_masked(HWIO_GCC_TME_PCIE_1_SGDSCR_ADDR, HWIO_GCC_TME_PCIE_1_SGDSCR_RMSK) +#define HWIO_GCC_TME_PCIE_1_SGDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_TME_PCIE_1_SGDSCR_ADDR, m) +#define HWIO_GCC_TME_PCIE_1_SGDSCR_OUT(v) \ + out_dword(HWIO_GCC_TME_PCIE_1_SGDSCR_ADDR,v) +#define HWIO_GCC_TME_PCIE_1_SGDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TME_PCIE_1_SGDSCR_ADDR,m,v,HWIO_GCC_TME_PCIE_1_SGDSCR_IN) +#define HWIO_GCC_TME_PCIE_1_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4 +#define HWIO_GCC_TME_PCIE_1_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x2 +#define HWIO_GCC_TME_PCIE_1_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_PCIE_1_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_PCIE_1_SGDSCR_RETAIN_FF_ENABLE_BMSK 0x2 +#define HWIO_GCC_TME_PCIE_1_SGDSCR_RETAIN_FF_ENABLE_SHFT 0x1 +#define HWIO_GCC_TME_PCIE_1_SGDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_PCIE_1_SGDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_PCIE_1_SGDSCR_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_TME_PCIE_1_SGDSCR_SW_OVERRIDE_SHFT 0x0 +#define HWIO_GCC_TME_PCIE_1_SGDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_PCIE_1_SGDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TME_PCIE_0_PHY_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00059020) +#define HWIO_GCC_TME_PCIE_0_PHY_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00059020) +#define HWIO_GCC_TME_PCIE_0_PHY_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00059020) +#define HWIO_GCC_TME_PCIE_0_PHY_SGDSCR_RMSK 0x7 +#define HWIO_GCC_TME_PCIE_0_PHY_SGDSCR_ATTR 0x3 +#define HWIO_GCC_TME_PCIE_0_PHY_SGDSCR_IN \ + in_dword_masked(HWIO_GCC_TME_PCIE_0_PHY_SGDSCR_ADDR, HWIO_GCC_TME_PCIE_0_PHY_SGDSCR_RMSK) +#define HWIO_GCC_TME_PCIE_0_PHY_SGDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_TME_PCIE_0_PHY_SGDSCR_ADDR, m) +#define HWIO_GCC_TME_PCIE_0_PHY_SGDSCR_OUT(v) \ + out_dword(HWIO_GCC_TME_PCIE_0_PHY_SGDSCR_ADDR,v) +#define HWIO_GCC_TME_PCIE_0_PHY_SGDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TME_PCIE_0_PHY_SGDSCR_ADDR,m,v,HWIO_GCC_TME_PCIE_0_PHY_SGDSCR_IN) +#define HWIO_GCC_TME_PCIE_0_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4 +#define HWIO_GCC_TME_PCIE_0_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x2 +#define HWIO_GCC_TME_PCIE_0_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_PCIE_0_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_PCIE_0_PHY_SGDSCR_RETAIN_FF_ENABLE_BMSK 0x2 +#define HWIO_GCC_TME_PCIE_0_PHY_SGDSCR_RETAIN_FF_ENABLE_SHFT 0x1 +#define HWIO_GCC_TME_PCIE_0_PHY_SGDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_PCIE_0_PHY_SGDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_PCIE_0_PHY_SGDSCR_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_TME_PCIE_0_PHY_SGDSCR_SW_OVERRIDE_SHFT 0x0 +#define HWIO_GCC_TME_PCIE_0_PHY_SGDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_PCIE_0_PHY_SGDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TME_TURING_QTB_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00059024) +#define HWIO_GCC_TME_TURING_QTB_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00059024) +#define HWIO_GCC_TME_TURING_QTB_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00059024) +#define HWIO_GCC_TME_TURING_QTB_SGDSCR_RMSK 0x7 +#define HWIO_GCC_TME_TURING_QTB_SGDSCR_ATTR 0x3 +#define HWIO_GCC_TME_TURING_QTB_SGDSCR_IN \ + in_dword_masked(HWIO_GCC_TME_TURING_QTB_SGDSCR_ADDR, HWIO_GCC_TME_TURING_QTB_SGDSCR_RMSK) +#define HWIO_GCC_TME_TURING_QTB_SGDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_TME_TURING_QTB_SGDSCR_ADDR, m) +#define HWIO_GCC_TME_TURING_QTB_SGDSCR_OUT(v) \ + out_dword(HWIO_GCC_TME_TURING_QTB_SGDSCR_ADDR,v) +#define HWIO_GCC_TME_TURING_QTB_SGDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TME_TURING_QTB_SGDSCR_ADDR,m,v,HWIO_GCC_TME_TURING_QTB_SGDSCR_IN) +#define HWIO_GCC_TME_TURING_QTB_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4 +#define HWIO_GCC_TME_TURING_QTB_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x2 +#define HWIO_GCC_TME_TURING_QTB_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_TURING_QTB_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_TURING_QTB_SGDSCR_RETAIN_FF_ENABLE_BMSK 0x2 +#define HWIO_GCC_TME_TURING_QTB_SGDSCR_RETAIN_FF_ENABLE_SHFT 0x1 +#define HWIO_GCC_TME_TURING_QTB_SGDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_TURING_QTB_SGDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_TURING_QTB_SGDSCR_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_TME_TURING_QTB_SGDSCR_SW_OVERRIDE_SHFT 0x0 +#define HWIO_GCC_TME_TURING_QTB_SGDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_TURING_QTB_SGDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TME_UFS_MEM_PHY_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00059028) +#define HWIO_GCC_TME_UFS_MEM_PHY_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00059028) +#define HWIO_GCC_TME_UFS_MEM_PHY_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00059028) +#define HWIO_GCC_TME_UFS_MEM_PHY_SGDSCR_RMSK 0x7 +#define HWIO_GCC_TME_UFS_MEM_PHY_SGDSCR_ATTR 0x3 +#define HWIO_GCC_TME_UFS_MEM_PHY_SGDSCR_IN \ + in_dword_masked(HWIO_GCC_TME_UFS_MEM_PHY_SGDSCR_ADDR, HWIO_GCC_TME_UFS_MEM_PHY_SGDSCR_RMSK) +#define HWIO_GCC_TME_UFS_MEM_PHY_SGDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_TME_UFS_MEM_PHY_SGDSCR_ADDR, m) +#define HWIO_GCC_TME_UFS_MEM_PHY_SGDSCR_OUT(v) \ + out_dword(HWIO_GCC_TME_UFS_MEM_PHY_SGDSCR_ADDR,v) +#define HWIO_GCC_TME_UFS_MEM_PHY_SGDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TME_UFS_MEM_PHY_SGDSCR_ADDR,m,v,HWIO_GCC_TME_UFS_MEM_PHY_SGDSCR_IN) +#define HWIO_GCC_TME_UFS_MEM_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4 +#define HWIO_GCC_TME_UFS_MEM_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x2 +#define HWIO_GCC_TME_UFS_MEM_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_UFS_MEM_PHY_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_UFS_MEM_PHY_SGDSCR_RETAIN_FF_ENABLE_BMSK 0x2 +#define HWIO_GCC_TME_UFS_MEM_PHY_SGDSCR_RETAIN_FF_ENABLE_SHFT 0x1 +#define HWIO_GCC_TME_UFS_MEM_PHY_SGDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_UFS_MEM_PHY_SGDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_UFS_MEM_PHY_SGDSCR_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_TME_UFS_MEM_PHY_SGDSCR_SW_OVERRIDE_SHFT 0x0 +#define HWIO_GCC_TME_UFS_MEM_PHY_SGDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_UFS_MEM_PHY_SGDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TME_PCIE_0_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005902c) +#define HWIO_GCC_TME_PCIE_0_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005902c) +#define HWIO_GCC_TME_PCIE_0_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005902c) +#define HWIO_GCC_TME_PCIE_0_SGDSCR_RMSK 0x7 +#define HWIO_GCC_TME_PCIE_0_SGDSCR_ATTR 0x3 +#define HWIO_GCC_TME_PCIE_0_SGDSCR_IN \ + in_dword_masked(HWIO_GCC_TME_PCIE_0_SGDSCR_ADDR, HWIO_GCC_TME_PCIE_0_SGDSCR_RMSK) +#define HWIO_GCC_TME_PCIE_0_SGDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_TME_PCIE_0_SGDSCR_ADDR, m) +#define HWIO_GCC_TME_PCIE_0_SGDSCR_OUT(v) \ + out_dword(HWIO_GCC_TME_PCIE_0_SGDSCR_ADDR,v) +#define HWIO_GCC_TME_PCIE_0_SGDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TME_PCIE_0_SGDSCR_ADDR,m,v,HWIO_GCC_TME_PCIE_0_SGDSCR_IN) +#define HWIO_GCC_TME_PCIE_0_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4 +#define HWIO_GCC_TME_PCIE_0_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x2 +#define HWIO_GCC_TME_PCIE_0_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_PCIE_0_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_PCIE_0_SGDSCR_RETAIN_FF_ENABLE_BMSK 0x2 +#define HWIO_GCC_TME_PCIE_0_SGDSCR_RETAIN_FF_ENABLE_SHFT 0x1 +#define HWIO_GCC_TME_PCIE_0_SGDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_PCIE_0_SGDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_PCIE_0_SGDSCR_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_TME_PCIE_0_SGDSCR_SW_OVERRIDE_SHFT 0x0 +#define HWIO_GCC_TME_PCIE_0_SGDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_PCIE_0_SGDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TME_LPASS_QTB_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00059030) +#define HWIO_GCC_TME_LPASS_QTB_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00059030) +#define HWIO_GCC_TME_LPASS_QTB_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00059030) +#define HWIO_GCC_TME_LPASS_QTB_SGDSCR_RMSK 0x7 +#define HWIO_GCC_TME_LPASS_QTB_SGDSCR_ATTR 0x3 +#define HWIO_GCC_TME_LPASS_QTB_SGDSCR_IN \ + in_dword_masked(HWIO_GCC_TME_LPASS_QTB_SGDSCR_ADDR, HWIO_GCC_TME_LPASS_QTB_SGDSCR_RMSK) +#define HWIO_GCC_TME_LPASS_QTB_SGDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_TME_LPASS_QTB_SGDSCR_ADDR, m) +#define HWIO_GCC_TME_LPASS_QTB_SGDSCR_OUT(v) \ + out_dword(HWIO_GCC_TME_LPASS_QTB_SGDSCR_ADDR,v) +#define HWIO_GCC_TME_LPASS_QTB_SGDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TME_LPASS_QTB_SGDSCR_ADDR,m,v,HWIO_GCC_TME_LPASS_QTB_SGDSCR_IN) +#define HWIO_GCC_TME_LPASS_QTB_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4 +#define HWIO_GCC_TME_LPASS_QTB_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x2 +#define HWIO_GCC_TME_LPASS_QTB_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_LPASS_QTB_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_LPASS_QTB_SGDSCR_RETAIN_FF_ENABLE_BMSK 0x2 +#define HWIO_GCC_TME_LPASS_QTB_SGDSCR_RETAIN_FF_ENABLE_SHFT 0x1 +#define HWIO_GCC_TME_LPASS_QTB_SGDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_LPASS_QTB_SGDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_LPASS_QTB_SGDSCR_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_TME_LPASS_QTB_SGDSCR_SW_OVERRIDE_SHFT 0x0 +#define HWIO_GCC_TME_LPASS_QTB_SGDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_LPASS_QTB_SGDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TME_MMNOC_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00059034) +#define HWIO_GCC_TME_MMNOC_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00059034) +#define HWIO_GCC_TME_MMNOC_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00059034) +#define HWIO_GCC_TME_MMNOC_SGDSCR_RMSK 0x7 +#define HWIO_GCC_TME_MMNOC_SGDSCR_ATTR 0x3 +#define HWIO_GCC_TME_MMNOC_SGDSCR_IN \ + in_dword_masked(HWIO_GCC_TME_MMNOC_SGDSCR_ADDR, HWIO_GCC_TME_MMNOC_SGDSCR_RMSK) +#define HWIO_GCC_TME_MMNOC_SGDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_TME_MMNOC_SGDSCR_ADDR, m) +#define HWIO_GCC_TME_MMNOC_SGDSCR_OUT(v) \ + out_dword(HWIO_GCC_TME_MMNOC_SGDSCR_ADDR,v) +#define HWIO_GCC_TME_MMNOC_SGDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TME_MMNOC_SGDSCR_ADDR,m,v,HWIO_GCC_TME_MMNOC_SGDSCR_IN) +#define HWIO_GCC_TME_MMNOC_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4 +#define HWIO_GCC_TME_MMNOC_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x2 +#define HWIO_GCC_TME_MMNOC_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_MMNOC_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_MMNOC_SGDSCR_RETAIN_FF_ENABLE_BMSK 0x2 +#define HWIO_GCC_TME_MMNOC_SGDSCR_RETAIN_FF_ENABLE_SHFT 0x1 +#define HWIO_GCC_TME_MMNOC_SGDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_MMNOC_SGDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_MMNOC_SGDSCR_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_TME_MMNOC_SGDSCR_SW_OVERRIDE_SHFT 0x0 +#define HWIO_GCC_TME_MMNOC_SGDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_MMNOC_SGDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_ACC_MISC_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003e030) +#define HWIO_GCC_ACC_MISC_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003e030) +#define HWIO_GCC_ACC_MISC_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003e030) +#define HWIO_GCC_ACC_MISC_RMSK 0x1 +#define HWIO_GCC_ACC_MISC_ATTR 0x3 +#define HWIO_GCC_ACC_MISC_IN \ + in_dword_masked(HWIO_GCC_ACC_MISC_ADDR, HWIO_GCC_ACC_MISC_RMSK) +#define HWIO_GCC_ACC_MISC_INM(m) \ + in_dword_masked(HWIO_GCC_ACC_MISC_ADDR, m) +#define HWIO_GCC_ACC_MISC_OUT(v) \ + out_dword(HWIO_GCC_ACC_MISC_ADDR,v) +#define HWIO_GCC_ACC_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ACC_MISC_ADDR,m,v,HWIO_GCC_ACC_MISC_IN) +#define HWIO_GCC_ACC_MISC_JTAG_ACC_SRC_SEL_EN_BMSK 0x1 +#define HWIO_GCC_ACC_MISC_JTAG_ACC_SRC_SEL_EN_SHFT 0x0 +#define HWIO_GCC_ACC_MISC_JTAG_ACC_SRC_SEL_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_ACC_MISC_JTAG_ACC_SRC_SEL_EN_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CPUSS_AHB_MISC_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038020) +#define HWIO_GCC_CPUSS_AHB_MISC_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00038020) +#define HWIO_GCC_CPUSS_AHB_MISC_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00038020) +#define HWIO_GCC_CPUSS_AHB_MISC_RMSK 0xf1 +#define HWIO_GCC_CPUSS_AHB_MISC_ATTR 0x3 +#define HWIO_GCC_CPUSS_AHB_MISC_IN \ + in_dword_masked(HWIO_GCC_CPUSS_AHB_MISC_ADDR, HWIO_GCC_CPUSS_AHB_MISC_RMSK) +#define HWIO_GCC_CPUSS_AHB_MISC_INM(m) \ + in_dword_masked(HWIO_GCC_CPUSS_AHB_MISC_ADDR, m) +#define HWIO_GCC_CPUSS_AHB_MISC_OUT(v) \ + out_dword(HWIO_GCC_CPUSS_AHB_MISC_ADDR,v) +#define HWIO_GCC_CPUSS_AHB_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CPUSS_AHB_MISC_ADDR,m,v,HWIO_GCC_CPUSS_AHB_MISC_IN) +#define HWIO_GCC_CPUSS_AHB_MISC_CPUSS_AHB_CLK_AUTO_SCALE_DIV_BMSK 0xf0 +#define HWIO_GCC_CPUSS_AHB_MISC_CPUSS_AHB_CLK_AUTO_SCALE_DIV_SHFT 0x4 +#define HWIO_GCC_CPUSS_AHB_MISC_CPUSS_AHB_CLK_AUTO_SCALE_DIV_DIV1_FVAL 0x0 +#define HWIO_GCC_CPUSS_AHB_MISC_CPUSS_AHB_CLK_AUTO_SCALE_DIV_DIV2_FVAL 0x1 +#define HWIO_GCC_CPUSS_AHB_MISC_CPUSS_AHB_CLK_AUTO_SCALE_DIV_DIV3_FVAL 0x2 +#define HWIO_GCC_CPUSS_AHB_MISC_CPUSS_AHB_CLK_AUTO_SCALE_DIV_DIV4_FVAL 0x3 +#define HWIO_GCC_CPUSS_AHB_MISC_CPUSS_AHB_CLK_AUTO_SCALE_DIV_DIV5_FVAL 0x4 +#define HWIO_GCC_CPUSS_AHB_MISC_CPUSS_AHB_CLK_AUTO_SCALE_DIV_DIV6_FVAL 0x5 +#define HWIO_GCC_CPUSS_AHB_MISC_CPUSS_AHB_CLK_AUTO_SCALE_DIV_DIV7_FVAL 0x6 +#define HWIO_GCC_CPUSS_AHB_MISC_CPUSS_AHB_CLK_AUTO_SCALE_DIV_DIV8_FVAL 0x7 +#define HWIO_GCC_CPUSS_AHB_MISC_CPUSS_AHB_CLK_AUTO_SCALE_DIV_DIV9_FVAL 0x8 +#define HWIO_GCC_CPUSS_AHB_MISC_CPUSS_AHB_CLK_AUTO_SCALE_DIV_DIV10_FVAL 0x9 +#define HWIO_GCC_CPUSS_AHB_MISC_CPUSS_AHB_CLK_AUTO_SCALE_DIV_DIV11_FVAL 0xa +#define HWIO_GCC_CPUSS_AHB_MISC_CPUSS_AHB_CLK_AUTO_SCALE_DIV_DIV12_FVAL 0xb +#define HWIO_GCC_CPUSS_AHB_MISC_CPUSS_AHB_CLK_AUTO_SCALE_DIV_DIV13_FVAL 0xc +#define HWIO_GCC_CPUSS_AHB_MISC_CPUSS_AHB_CLK_AUTO_SCALE_DIV_DIV14_FVAL 0xd +#define HWIO_GCC_CPUSS_AHB_MISC_CPUSS_AHB_CLK_AUTO_SCALE_DIV_DIV15_FVAL 0xe +#define HWIO_GCC_CPUSS_AHB_MISC_CPUSS_AHB_CLK_AUTO_SCALE_DIV_DIV16_FVAL 0xf +#define HWIO_GCC_CPUSS_AHB_MISC_CPUSS_AHB_CLK_AUTO_SCALE_DIS_BMSK 0x1 +#define HWIO_GCC_CPUSS_AHB_MISC_CPUSS_AHB_CLK_AUTO_SCALE_DIS_SHFT 0x0 +#define HWIO_GCC_CPUSS_AHB_MISC_CPUSS_AHB_CLK_AUTO_SCALE_DIS_SCALE_NOT_DISABLE_FVAL 0x0 +#define HWIO_GCC_CPUSS_AHB_MISC_CPUSS_AHB_CLK_AUTO_SCALE_DIS_SCALE_DISABLE_FVAL 0x1 + +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002f038) +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002f038) +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002f038) +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_RMSK 0xfffffd7f +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_ADDR, HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_RMSK) +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_ADDR, m) +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_ADDR,v) +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_IN) +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_ENA_BMSK 0x80000000 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_ENA_SHFT 0x1f +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_BMSK 0x40000000 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_SHFT 0x1e +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_BMSK 0x20000000 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_SHFT 0x1d +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_BMSK 0x10000000 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_SHFT 0x1c +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_BMSK 0x8000000 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_SHFT 0x1b +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_BMSK 0x4000000 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_SHFT 0x1a +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_BMSK 0x2000000 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_SHFT 0x19 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_AUX_CLK_ENA_BMSK 0x1000000 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_AUX_CLK_ENA_SHFT 0x18 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_AUX_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_AUX_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_ENA_BMSK 0x800000 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_ENA_SHFT 0x17 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_ENA_BMSK 0x400000 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_ENA_SHFT 0x16 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_BMSK 0x200000 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_SHFT 0x15 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_ENA_BMSK 0x100000 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_ENA_SHFT 0x14 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_ENA_BMSK 0x80000 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_ENA_SHFT 0x13 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_ENA_BMSK 0x40000 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_ENA_SHFT 0x12 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_BMSK 0x20000 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_SHFT 0x11 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_BMSK 0x10000 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_SHFT 0x10 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_BMSK 0x8000 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_SHFT 0xf +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_TME_GPLL0_CLK_SRC_ENA_BMSK 0x4000 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_TME_GPLL0_CLK_SRC_ENA_SHFT 0xe +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_TME_GPLL0_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_TME_GPLL0_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_BMSK 0x2000 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_SHFT 0xd +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_ENA_BMSK 0x1000 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_ENA_SHFT 0xc +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_QMIP_PCIE_AHB_CLK_ENA_BMSK 0x800 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_QMIP_PCIE_AHB_CLK_ENA_SHFT 0xb +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_QMIP_PCIE_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_QMIP_PCIE_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_BMSK 0x400 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_SHFT 0xa +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_BMSK 0x100 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_SHFT 0x8 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_BMSK 0x40 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_SHFT 0x6 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_BMSK 0x20 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_SHFT 0x5 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_BMSK 0x10 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_SHFT 0x4 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_BMSK 0x8 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_SHFT 0x3 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_BMSK 0x4 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_SHFT 0x2 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_BMSK 0x2 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_SHFT 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_BMSK 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_SHFT 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002f03c) +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002f03c) +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002f03c) +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_RMSK 0xfffffd7f +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_ADDR, HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_RMSK) +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_ADDR, m) +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_ADDR,v) +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_IN) +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_SLEEP_ENA_BMSK 0x80000000 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_SLEEP_ENA_SHFT 0x1f +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_BMSK 0x40000000 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_SHFT 0x1e +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_BMSK 0x20000000 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_SHFT 0x1d +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_BMSK 0x10000000 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_SHFT 0x1c +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_BMSK 0x8000000 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_SHFT 0x1b +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_BMSK 0x4000000 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_SHFT 0x1a +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK 0x2000000 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT 0x19 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_AUX_CLK_SLEEP_ENA_BMSK 0x1000000 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_AUX_CLK_SLEEP_ENA_SHFT 0x18 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_AUX_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_AUX_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_SLEEP_ENA_BMSK 0x800000 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_SLEEP_ENA_SHFT 0x17 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_SLEEP_ENA_BMSK 0x400000 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_SLEEP_ENA_SHFT 0x16 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_BMSK 0x200000 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_SHFT 0x15 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_SLEEP_ENA_BMSK 0x100000 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_SLEEP_ENA_SHFT 0x14 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_SLEEP_ENA_BMSK 0x80000 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_SLEEP_ENA_SHFT 0x13 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_SLEEP_ENA_BMSK 0x40000 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_SLEEP_ENA_SHFT 0x12 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK 0x20000 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT 0x11 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK 0x10000 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT 0x10 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_BMSK 0x8000 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_SHFT 0xf +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_TME_GPLL0_CLK_SRC_SLEEP_ENA_BMSK 0x4000 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_TME_GPLL0_CLK_SRC_SLEEP_ENA_SHFT 0xe +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_TME_GPLL0_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_TME_GPLL0_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_BMSK 0x2000 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_SHFT 0xd +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_SLEEP_ENA_BMSK 0x1000 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_SLEEP_ENA_SHFT 0xc +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_QMIP_PCIE_AHB_CLK_SLEEP_ENA_BMSK 0x800 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_QMIP_PCIE_AHB_CLK_SLEEP_ENA_SHFT 0xb +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_QMIP_PCIE_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_QMIP_PCIE_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_BMSK 0x400 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_SHFT 0xa +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_BMSK 0x100 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_SHFT 0x8 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_BMSK 0x40 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_SHFT 0x6 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_BMSK 0x20 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_SHFT 0x5 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_BMSK 0x10 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_SHFT 0x4 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_BMSK 0x8 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_SHFT 0x3 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_BMSK 0x4 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_SHFT 0x2 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_BMSK 0x2 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_SHFT 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_BMSK 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_SHFT 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002f040) +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002f040) +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002f040) +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_RMSK 0xffffffff +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_ATTR 0x3 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_IN \ + in_dword_masked(HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_ADDR, HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_RMSK) +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_INM(m) \ + in_dword_masked(HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_ADDR, m) +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_OUT(v) \ + out_dword(HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_ADDR,v) +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_ADDR,m,v,HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_IN) +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_ENA_BMSK 0x80000000 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_ENA_SHFT 0x1f +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_ENA_BMSK 0x40000000 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_ENA_SHFT 0x1e +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_ENA_BMSK 0x20000000 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_ENA_SHFT 0x1d +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_ENA_BMSK 0x10000000 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_ENA_SHFT 0x1c +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_BMSK 0x8000000 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_SHFT 0x1b +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_BMSK 0x4000000 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_SHFT 0x1a +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_BMSK 0x2000000 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_SHFT 0x19 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_BMSK 0x1000000 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_SHFT 0x18 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_BMSK 0x800000 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_SHFT 0x17 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_BMSK 0x400000 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_SHFT 0x16 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_BMSK 0x200000 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_SHFT 0x15 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_BMSK 0x100000 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_SHFT 0x14 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_BMSK 0x80000 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_SHFT 0x13 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_BMSK 0x40000 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_SHFT 0x12 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S7_CLK_ENA_BMSK 0x20000 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S7_CLK_ENA_SHFT 0x11 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S7_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S7_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S6_CLK_ENA_BMSK 0x10000 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S6_CLK_ENA_SHFT 0x10 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S6_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S6_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S5_CLK_ENA_BMSK 0x8000 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S5_CLK_ENA_SHFT 0xf +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S5_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S5_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S4_CLK_ENA_BMSK 0x4000 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S4_CLK_ENA_SHFT 0xe +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S4_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S4_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S3_CLK_ENA_BMSK 0x2000 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S3_CLK_ENA_SHFT 0xd +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S3_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S3_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S2_CLK_ENA_BMSK 0x1000 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S2_CLK_ENA_SHFT 0xc +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S2_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S2_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S1_CLK_ENA_BMSK 0x800 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S1_CLK_ENA_SHFT 0xb +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S1_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S1_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S0_CLK_ENA_BMSK 0x400 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S0_CLK_ENA_SHFT 0xa +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S0_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S0_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_ENA_BMSK 0x200 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_ENA_SHFT 0x9 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_ENA_BMSK 0x100 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_ENA_SHFT 0x8 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_ENA_BMSK 0x80 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_ENA_SHFT 0x7 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_ENA_BMSK 0x40 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_ENA_SHFT 0x6 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_BMSK 0x20 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_SHFT 0x5 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_BMSK 0x10 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_SHFT 0x4 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_BMSK 0x8 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_SHFT 0x3 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_BMSK 0x4 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_SHFT 0x2 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_BMSK 0x2 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_SHFT 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_BMSK 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_SHFT 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002f044) +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002f044) +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002f044) +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_RMSK 0xffffffff +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_ATTR 0x3 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_IN \ + in_dword_masked(HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_ADDR, HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_RMSK) +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_INM(m) \ + in_dword_masked(HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_ADDR, m) +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_OUT(v) \ + out_dword(HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_ADDR,v) +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_ADDR,m,v,HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_IN) +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_SLEEP_ENA_BMSK 0x80000000 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_SLEEP_ENA_SHFT 0x1f +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_SLEEP_ENA_BMSK 0x40000000 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_SLEEP_ENA_SHFT 0x1e +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_SLEEP_ENA_BMSK 0x20000000 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_SLEEP_ENA_SHFT 0x1d +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_SLEEP_ENA_BMSK 0x10000000 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_SLEEP_ENA_SHFT 0x1c +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_BMSK 0x8000000 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_SHFT 0x1b +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_BMSK 0x4000000 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_SHFT 0x1a +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_BMSK 0x2000000 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_SHFT 0x19 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_BMSK 0x1000000 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_SHFT 0x18 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_BMSK 0x800000 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_SHFT 0x17 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_BMSK 0x400000 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_SHFT 0x16 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_BMSK 0x200000 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_SHFT 0x15 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_BMSK 0x100000 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_SHFT 0x14 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_BMSK 0x80000 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_SHFT 0x13 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_BMSK 0x40000 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_SHFT 0x12 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S7_CLK_SLEEP_ENA_BMSK 0x20000 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S7_CLK_SLEEP_ENA_SHFT 0x11 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S7_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S7_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S6_CLK_SLEEP_ENA_BMSK 0x10000 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S6_CLK_SLEEP_ENA_SHFT 0x10 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S6_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S6_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S5_CLK_SLEEP_ENA_BMSK 0x8000 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S5_CLK_SLEEP_ENA_SHFT 0xf +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S5_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S5_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S4_CLK_SLEEP_ENA_BMSK 0x4000 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S4_CLK_SLEEP_ENA_SHFT 0xe +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S4_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S4_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S3_CLK_SLEEP_ENA_BMSK 0x2000 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S3_CLK_SLEEP_ENA_SHFT 0xd +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S3_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S3_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S2_CLK_SLEEP_ENA_BMSK 0x1000 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S2_CLK_SLEEP_ENA_SHFT 0xc +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S2_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S2_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S1_CLK_SLEEP_ENA_BMSK 0x800 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S1_CLK_SLEEP_ENA_SHFT 0xb +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S1_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S1_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S0_CLK_SLEEP_ENA_BMSK 0x400 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S0_CLK_SLEEP_ENA_SHFT 0xa +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S0_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S0_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_SLEEP_ENA_BMSK 0x200 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_SLEEP_ENA_SHFT 0x9 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_SLEEP_ENA_BMSK 0x100 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_SLEEP_ENA_SHFT 0x8 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_SLEEP_ENA_BMSK 0x80 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_SLEEP_ENA_SHFT 0x7 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_SLEEP_ENA_BMSK 0x40 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_SLEEP_ENA_SHFT 0x6 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK 0x20 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT 0x5 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_BMSK 0x10 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_SHFT 0x4 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_BMSK 0x8 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_SHFT 0x3 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_BMSK 0x4 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_SHFT 0x2 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_BMSK 0x2 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_SHFT 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_BMSK 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_SHFT 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002f048) +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002f048) +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002f048) +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_RMSK 0x7ffff +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_ATTR 0x3 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_IN \ + in_dword_masked(HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_ADDR, HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_RMSK) +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_INM(m) \ + in_dword_masked(HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_ADDR, m) +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_OUT(v) \ + out_dword(HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_ADDR,v) +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_ADDR,m,v,HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_IN) +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_ENA_BMSK 0x40000 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_ENA_SHFT 0x12 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_ENA_BMSK 0x20000 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_ENA_SHFT 0x11 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_ENA_BMSK 0x10000 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_ENA_SHFT 0x10 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S9_CLK_ENA_BMSK 0x8000 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S9_CLK_ENA_SHFT 0xf +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S9_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S9_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S8_CLK_ENA_BMSK 0x4000 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S8_CLK_ENA_SHFT 0xe +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S8_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S8_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_ENA_BMSK 0x2000 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_ENA_SHFT 0xd +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_ENA_BMSK 0x1000 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_ENA_SHFT 0xc +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_ENA_BMSK 0x800 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_ENA_SHFT 0xb +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_ENA_BMSK 0x400 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_ENA_SHFT 0xa +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_BMSK 0x200 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_SHFT 0x9 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_BMSK 0x100 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_SHFT 0x8 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_BMSK 0x80 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_SHFT 0x7 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_BMSK 0x40 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_SHFT 0x6 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_BMSK 0x20 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_SHFT 0x5 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_BMSK 0x10 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_SHFT 0x4 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_BMSK 0x8 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_SHFT 0x3 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_BMSK 0x4 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_SHFT 0x2 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_BMSK 0x2 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_SHFT 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_BMSK 0x1 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_SHFT 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002f04c) +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002f04c) +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002f04c) +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_RMSK 0x7ffff +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_ATTR 0x3 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_IN \ + in_dword_masked(HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_ADDR, HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_RMSK) +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_INM(m) \ + in_dword_masked(HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_ADDR, m) +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_OUT(v) \ + out_dword(HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_ADDR,v) +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_ADDR,m,v,HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_IN) +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_SLEEP_ENA_BMSK 0x40000 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_SLEEP_ENA_SHFT 0x12 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_SLEEP_ENA_BMSK 0x20000 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_SLEEP_ENA_SHFT 0x11 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_SLEEP_ENA_BMSK 0x10000 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_SLEEP_ENA_SHFT 0x10 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S9_CLK_SLEEP_ENA_BMSK 0x8000 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S9_CLK_SLEEP_ENA_SHFT 0xf +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S9_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S9_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S8_CLK_SLEEP_ENA_BMSK 0x4000 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S8_CLK_SLEEP_ENA_SHFT 0xe +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S8_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S8_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_SLEEP_ENA_BMSK 0x2000 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_SLEEP_ENA_SHFT 0xd +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_SLEEP_ENA_BMSK 0x1000 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_SLEEP_ENA_SHFT 0xc +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_SLEEP_ENA_BMSK 0x800 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_SLEEP_ENA_SHFT 0xb +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_SLEEP_ENA_BMSK 0x400 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_SLEEP_ENA_SHFT 0xa +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_BMSK 0x200 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_SHFT 0x9 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_BMSK 0x100 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_SHFT 0x8 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_BMSK 0x80 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_SHFT 0x7 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_BMSK 0x40 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_SHFT 0x6 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_BMSK 0x20 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_SHFT 0x5 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_BMSK 0x10 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_SHFT 0x4 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_BMSK 0x8 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_SHFT 0x3 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_BMSK 0x4 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_SHFT 0x2 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_BMSK 0x2 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_SHFT 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_BMSK 0x1 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_SHFT 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SP_PLL_BRANCH_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002f050) +#define HWIO_GCC_SP_PLL_BRANCH_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002f050) +#define HWIO_GCC_SP_PLL_BRANCH_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002f050) +#define HWIO_GCC_SP_PLL_BRANCH_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_SP_PLL_BRANCH_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_SP_PLL_BRANCH_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_SP_PLL_BRANCH_ENA_VOTE_ADDR, HWIO_GCC_SP_PLL_BRANCH_ENA_VOTE_RMSK) +#define HWIO_GCC_SP_PLL_BRANCH_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_SP_PLL_BRANCH_ENA_VOTE_ADDR, m) +#define HWIO_GCC_SP_PLL_BRANCH_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_SP_PLL_BRANCH_ENA_VOTE_ADDR,v) +#define HWIO_GCC_SP_PLL_BRANCH_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SP_PLL_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_SP_PLL_BRANCH_ENA_VOTE_IN) +#define HWIO_GCC_SP_PLL_BRANCH_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_SP_PLL_BRANCH_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_SP_PLL_BRANCH_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_PLL_BRANCH_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_PLL_BRANCH_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_SP_PLL_BRANCH_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_SP_PLL_BRANCH_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_PLL_BRANCH_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_PLL_BRANCH_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_SP_PLL_BRANCH_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_SP_PLL_BRANCH_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_PLL_BRANCH_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_PLL_BRANCH_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_SP_PLL_BRANCH_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_SP_PLL_BRANCH_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_PLL_BRANCH_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_PLL_BRANCH_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_SP_PLL_BRANCH_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_SP_PLL_BRANCH_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_PLL_BRANCH_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_PLL_BRANCH_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_SP_PLL_BRANCH_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_SP_PLL_BRANCH_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_PLL_BRANCH_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_PLL_BRANCH_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_SP_PLL_BRANCH_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_SP_PLL_BRANCH_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_PLL_BRANCH_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_PLL_BRANCH_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_SP_PLL_BRANCH_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_SP_PLL_BRANCH_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_PLL_BRANCH_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_PLL_BRANCH_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_SP_PLL_BRANCH_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_SP_PLL_BRANCH_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_PLL_BRANCH_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_PLL_BRANCH_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_SP_PLL_BRANCH_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_SP_PLL_BRANCH_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_PLL_BRANCH_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SP_PLL_SLEEP_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002f054) +#define HWIO_GCC_SP_PLL_SLEEP_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002f054) +#define HWIO_GCC_SP_PLL_SLEEP_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002f054) +#define HWIO_GCC_SP_PLL_SLEEP_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_SP_PLL_SLEEP_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_SP_PLL_SLEEP_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_SP_PLL_SLEEP_ENA_VOTE_ADDR, HWIO_GCC_SP_PLL_SLEEP_ENA_VOTE_RMSK) +#define HWIO_GCC_SP_PLL_SLEEP_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_SP_PLL_SLEEP_ENA_VOTE_ADDR, m) +#define HWIO_GCC_SP_PLL_SLEEP_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_SP_PLL_SLEEP_ENA_VOTE_ADDR,v) +#define HWIO_GCC_SP_PLL_SLEEP_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SP_PLL_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_SP_PLL_SLEEP_ENA_VOTE_IN) +#define HWIO_GCC_SP_PLL_SLEEP_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_SP_PLL_SLEEP_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_SP_PLL_SLEEP_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_PLL_SLEEP_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_PLL_SLEEP_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_SP_PLL_SLEEP_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_SP_PLL_SLEEP_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_PLL_SLEEP_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_PLL_SLEEP_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_SP_PLL_SLEEP_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_SP_PLL_SLEEP_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_PLL_SLEEP_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_PLL_SLEEP_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_SP_PLL_SLEEP_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_SP_PLL_SLEEP_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_PLL_SLEEP_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_PLL_SLEEP_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_SP_PLL_SLEEP_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_SP_PLL_SLEEP_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_PLL_SLEEP_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_PLL_SLEEP_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_SP_PLL_SLEEP_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_SP_PLL_SLEEP_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_PLL_SLEEP_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_PLL_SLEEP_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_SP_PLL_SLEEP_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_SP_PLL_SLEEP_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_PLL_SLEEP_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_PLL_SLEEP_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_SP_PLL_SLEEP_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_SP_PLL_SLEEP_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_PLL_SLEEP_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_PLL_SLEEP_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_SP_PLL_SLEEP_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_SP_PLL_SLEEP_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_PLL_SLEEP_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_PLL_SLEEP_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_SP_PLL_SLEEP_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_SP_PLL_SLEEP_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_PLL_SLEEP_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00041000) +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00041000) +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00041000) +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_RMSK 0xfffffd7f +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_ADDR, HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_RMSK) +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_IN) +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_ENA_BMSK 0x80000000 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_ENA_SHFT 0x1f +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_BMSK 0x40000000 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_SHFT 0x1e +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_BMSK 0x20000000 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_SHFT 0x1d +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_BMSK 0x10000000 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_SHFT 0x1c +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_BMSK 0x8000000 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_SHFT 0x1b +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_BMSK 0x4000000 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_SHFT 0x1a +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_BMSK 0x2000000 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_SHFT 0x19 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_AUX_CLK_ENA_BMSK 0x1000000 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_AUX_CLK_ENA_SHFT 0x18 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_AUX_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_AUX_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_ENA_BMSK 0x800000 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_ENA_SHFT 0x17 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_ENA_BMSK 0x400000 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_ENA_SHFT 0x16 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_BMSK 0x200000 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_SHFT 0x15 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_ENA_BMSK 0x100000 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_ENA_SHFT 0x14 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_ENA_BMSK 0x80000 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_ENA_SHFT 0x13 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_ENA_BMSK 0x40000 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_ENA_SHFT 0x12 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_BMSK 0x20000 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_SHFT 0x11 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_BMSK 0x10000 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_SHFT 0x10 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_BMSK 0x8000 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_SHFT 0xf +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_TME_GPLL0_CLK_SRC_ENA_BMSK 0x4000 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_TME_GPLL0_CLK_SRC_ENA_SHFT 0xe +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_TME_GPLL0_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_TME_GPLL0_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_BMSK 0x2000 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_SHFT 0xd +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_ENA_BMSK 0x1000 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_ENA_SHFT 0xc +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_QMIP_PCIE_AHB_CLK_ENA_BMSK 0x800 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_QMIP_PCIE_AHB_CLK_ENA_SHFT 0xb +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_QMIP_PCIE_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_QMIP_PCIE_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_BMSK 0x400 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_SHFT 0xa +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_BMSK 0x100 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_SHFT 0x8 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_BMSK 0x40 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_SHFT 0x6 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_BMSK 0x20 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_SHFT 0x5 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_BMSK 0x10 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_SHFT 0x4 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_BMSK 0x8 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_SHFT 0x3 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_BMSK 0x4 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_SHFT 0x2 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_BMSK 0x2 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_SHFT 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_BMSK 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_SHFT 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00041004) +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00041004) +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00041004) +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_RMSK 0xfffffd7f +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_ADDR, HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_RMSK) +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_IN) +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_SLEEP_ENA_BMSK 0x80000000 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_SLEEP_ENA_SHFT 0x1f +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_BMSK 0x40000000 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_SHFT 0x1e +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_BMSK 0x20000000 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_SHFT 0x1d +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_BMSK 0x10000000 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_SHFT 0x1c +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_BMSK 0x8000000 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_SHFT 0x1b +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_BMSK 0x4000000 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_SHFT 0x1a +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK 0x2000000 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT 0x19 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_AUX_CLK_SLEEP_ENA_BMSK 0x1000000 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_AUX_CLK_SLEEP_ENA_SHFT 0x18 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_AUX_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_AUX_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_SLEEP_ENA_BMSK 0x800000 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_SLEEP_ENA_SHFT 0x17 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_SLEEP_ENA_BMSK 0x400000 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_SLEEP_ENA_SHFT 0x16 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_BMSK 0x200000 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_SHFT 0x15 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_SLEEP_ENA_BMSK 0x100000 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_SLEEP_ENA_SHFT 0x14 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_SLEEP_ENA_BMSK 0x80000 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_SLEEP_ENA_SHFT 0x13 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_SLEEP_ENA_BMSK 0x40000 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_SLEEP_ENA_SHFT 0x12 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK 0x20000 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT 0x11 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK 0x10000 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT 0x10 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_BMSK 0x8000 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_SHFT 0xf +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_TME_GPLL0_CLK_SRC_SLEEP_ENA_BMSK 0x4000 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_TME_GPLL0_CLK_SRC_SLEEP_ENA_SHFT 0xe +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_TME_GPLL0_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_TME_GPLL0_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_BMSK 0x2000 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_SHFT 0xd +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_SLEEP_ENA_BMSK 0x1000 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_SLEEP_ENA_SHFT 0xc +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_QMIP_PCIE_AHB_CLK_SLEEP_ENA_BMSK 0x800 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_QMIP_PCIE_AHB_CLK_SLEEP_ENA_SHFT 0xb +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_QMIP_PCIE_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_QMIP_PCIE_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_BMSK 0x400 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_SHFT 0xa +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_BMSK 0x100 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_SHFT 0x8 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_BMSK 0x40 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_SHFT 0x6 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_BMSK 0x20 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_SHFT 0x5 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_BMSK 0x10 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_SHFT 0x4 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_BMSK 0x8 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_SHFT 0x3 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_BMSK 0x4 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_SHFT 0x2 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_BMSK 0x2 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_SHFT 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_BMSK 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_SHFT 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00041008) +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00041008) +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00041008) +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_RMSK 0xffffffff +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_ATTR 0x3 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_IN \ + in_dword_masked(HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_ADDR, HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_RMSK) +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_INM(m) \ + in_dword_masked(HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_ADDR, m) +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_OUT(v) \ + out_dword(HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_ADDR,v) +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_ADDR,m,v,HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_IN) +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_ENA_BMSK 0x80000000 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_ENA_SHFT 0x1f +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_ENA_BMSK 0x40000000 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_ENA_SHFT 0x1e +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_ENA_BMSK 0x20000000 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_ENA_SHFT 0x1d +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_ENA_BMSK 0x10000000 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_ENA_SHFT 0x1c +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_BMSK 0x8000000 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_SHFT 0x1b +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_BMSK 0x4000000 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_SHFT 0x1a +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_BMSK 0x2000000 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_SHFT 0x19 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_BMSK 0x1000000 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_SHFT 0x18 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_BMSK 0x800000 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_SHFT 0x17 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_BMSK 0x400000 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_SHFT 0x16 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_BMSK 0x200000 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_SHFT 0x15 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_BMSK 0x100000 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_SHFT 0x14 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_BMSK 0x80000 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_SHFT 0x13 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_BMSK 0x40000 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_SHFT 0x12 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S7_CLK_ENA_BMSK 0x20000 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S7_CLK_ENA_SHFT 0x11 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S7_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S7_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S6_CLK_ENA_BMSK 0x10000 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S6_CLK_ENA_SHFT 0x10 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S6_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S6_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S5_CLK_ENA_BMSK 0x8000 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S5_CLK_ENA_SHFT 0xf +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S5_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S5_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S4_CLK_ENA_BMSK 0x4000 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S4_CLK_ENA_SHFT 0xe +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S4_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S4_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S3_CLK_ENA_BMSK 0x2000 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S3_CLK_ENA_SHFT 0xd +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S3_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S3_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S2_CLK_ENA_BMSK 0x1000 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S2_CLK_ENA_SHFT 0xc +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S2_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S2_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S1_CLK_ENA_BMSK 0x800 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S1_CLK_ENA_SHFT 0xb +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S1_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S1_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S0_CLK_ENA_BMSK 0x400 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S0_CLK_ENA_SHFT 0xa +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S0_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S0_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_ENA_BMSK 0x200 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_ENA_SHFT 0x9 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_ENA_BMSK 0x100 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_ENA_SHFT 0x8 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_ENA_BMSK 0x80 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_ENA_SHFT 0x7 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_ENA_BMSK 0x40 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_ENA_SHFT 0x6 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_BMSK 0x20 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_SHFT 0x5 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_BMSK 0x10 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_SHFT 0x4 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_BMSK 0x8 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_SHFT 0x3 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_BMSK 0x4 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_SHFT 0x2 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_BMSK 0x2 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_SHFT 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_BMSK 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_SHFT 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004100c) +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004100c) +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004100c) +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_RMSK 0xffffffff +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_ATTR 0x3 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_IN \ + in_dword_masked(HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_ADDR, HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_RMSK) +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_INM(m) \ + in_dword_masked(HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_ADDR, m) +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_OUT(v) \ + out_dword(HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_ADDR,v) +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_ADDR,m,v,HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_IN) +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_SLEEP_ENA_BMSK 0x80000000 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_SLEEP_ENA_SHFT 0x1f +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_SLEEP_ENA_BMSK 0x40000000 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_SLEEP_ENA_SHFT 0x1e +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_SLEEP_ENA_BMSK 0x20000000 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_SLEEP_ENA_SHFT 0x1d +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_SLEEP_ENA_BMSK 0x10000000 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_SLEEP_ENA_SHFT 0x1c +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_BMSK 0x8000000 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_SHFT 0x1b +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_BMSK 0x4000000 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_SHFT 0x1a +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_BMSK 0x2000000 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_SHFT 0x19 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_BMSK 0x1000000 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_SHFT 0x18 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_BMSK 0x800000 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_SHFT 0x17 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_BMSK 0x400000 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_SHFT 0x16 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_BMSK 0x200000 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_SHFT 0x15 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_BMSK 0x100000 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_SHFT 0x14 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_BMSK 0x80000 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_SHFT 0x13 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_BMSK 0x40000 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_SHFT 0x12 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S7_CLK_SLEEP_ENA_BMSK 0x20000 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S7_CLK_SLEEP_ENA_SHFT 0x11 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S7_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S7_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S6_CLK_SLEEP_ENA_BMSK 0x10000 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S6_CLK_SLEEP_ENA_SHFT 0x10 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S6_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S6_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S5_CLK_SLEEP_ENA_BMSK 0x8000 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S5_CLK_SLEEP_ENA_SHFT 0xf +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S5_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S5_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S4_CLK_SLEEP_ENA_BMSK 0x4000 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S4_CLK_SLEEP_ENA_SHFT 0xe +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S4_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S4_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S3_CLK_SLEEP_ENA_BMSK 0x2000 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S3_CLK_SLEEP_ENA_SHFT 0xd +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S3_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S3_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S2_CLK_SLEEP_ENA_BMSK 0x1000 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S2_CLK_SLEEP_ENA_SHFT 0xc +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S2_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S2_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S1_CLK_SLEEP_ENA_BMSK 0x800 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S1_CLK_SLEEP_ENA_SHFT 0xb +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S1_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S1_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S0_CLK_SLEEP_ENA_BMSK 0x400 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S0_CLK_SLEEP_ENA_SHFT 0xa +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S0_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S0_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_SLEEP_ENA_BMSK 0x200 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_SLEEP_ENA_SHFT 0x9 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_SLEEP_ENA_BMSK 0x100 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_SLEEP_ENA_SHFT 0x8 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_SLEEP_ENA_BMSK 0x80 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_SLEEP_ENA_SHFT 0x7 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_SLEEP_ENA_BMSK 0x40 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_SLEEP_ENA_SHFT 0x6 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK 0x20 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT 0x5 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_BMSK 0x10 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_SHFT 0x4 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_BMSK 0x8 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_SHFT 0x3 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_BMSK 0x4 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_SHFT 0x2 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_BMSK 0x2 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_SHFT 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_BMSK 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_SHFT 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00041010) +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00041010) +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00041010) +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_RMSK 0x7ffff +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_ATTR 0x3 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_IN \ + in_dword_masked(HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_ADDR, HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_RMSK) +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_INM(m) \ + in_dword_masked(HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_ADDR, m) +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_OUT(v) \ + out_dword(HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_ADDR,v) +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_ADDR,m,v,HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_IN) +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_ENA_BMSK 0x40000 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_ENA_SHFT 0x12 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_ENA_BMSK 0x20000 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_ENA_SHFT 0x11 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_ENA_BMSK 0x10000 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_ENA_SHFT 0x10 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S9_CLK_ENA_BMSK 0x8000 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S9_CLK_ENA_SHFT 0xf +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S9_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S9_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S8_CLK_ENA_BMSK 0x4000 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S8_CLK_ENA_SHFT 0xe +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S8_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S8_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_ENA_BMSK 0x2000 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_ENA_SHFT 0xd +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_ENA_BMSK 0x1000 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_ENA_SHFT 0xc +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_ENA_BMSK 0x800 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_ENA_SHFT 0xb +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_ENA_BMSK 0x400 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_ENA_SHFT 0xa +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_BMSK 0x200 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_SHFT 0x9 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_BMSK 0x100 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_SHFT 0x8 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_BMSK 0x80 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_SHFT 0x7 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_BMSK 0x40 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_SHFT 0x6 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_BMSK 0x20 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_SHFT 0x5 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_BMSK 0x10 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_SHFT 0x4 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_BMSK 0x8 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_SHFT 0x3 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_BMSK 0x4 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_SHFT 0x2 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_BMSK 0x2 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_SHFT 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_BMSK 0x1 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_SHFT 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00041014) +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00041014) +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00041014) +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_RMSK 0x7ffff +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_ATTR 0x3 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_IN \ + in_dword_masked(HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_ADDR, HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_RMSK) +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_INM(m) \ + in_dword_masked(HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_ADDR, m) +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_OUT(v) \ + out_dword(HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_ADDR,v) +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_ADDR,m,v,HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_IN) +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_SLEEP_ENA_BMSK 0x40000 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_SLEEP_ENA_SHFT 0x12 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_SLEEP_ENA_BMSK 0x20000 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_SLEEP_ENA_SHFT 0x11 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_SLEEP_ENA_BMSK 0x10000 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_SLEEP_ENA_SHFT 0x10 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S9_CLK_SLEEP_ENA_BMSK 0x8000 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S9_CLK_SLEEP_ENA_SHFT 0xf +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S9_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S9_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S8_CLK_SLEEP_ENA_BMSK 0x4000 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S8_CLK_SLEEP_ENA_SHFT 0xe +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S8_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S8_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_SLEEP_ENA_BMSK 0x2000 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_SLEEP_ENA_SHFT 0xd +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_SLEEP_ENA_BMSK 0x1000 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_SLEEP_ENA_SHFT 0xc +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_SLEEP_ENA_BMSK 0x800 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_SLEEP_ENA_SHFT 0xb +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_SLEEP_ENA_BMSK 0x400 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_SLEEP_ENA_SHFT 0xa +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_BMSK 0x200 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_SHFT 0x9 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_BMSK 0x100 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_SHFT 0x8 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_BMSK 0x80 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_SHFT 0x7 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_BMSK 0x40 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_SHFT 0x6 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_BMSK 0x20 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_SHFT 0x5 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_BMSK 0x10 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_SHFT 0x4 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_BMSK 0x8 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_SHFT 0x3 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_BMSK 0x4 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_SHFT 0x2 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_BMSK 0x2 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_SHFT 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_BMSK 0x1 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_SHFT 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00041018) +#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00041018) +#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00041018) +#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_ADDR, HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_RMSK) +#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_IN) +#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004101c) +#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004101c) +#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004101c) +#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_ADDR, HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_RMSK) +#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_IN) +#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00042000) +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00042000) +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00042000) +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_RMSK 0xfffffd7f +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_ADDR, HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_RMSK) +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_ADDR, m) +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_ADDR,v) +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_IN) +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_ENA_BMSK 0x80000000 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_ENA_SHFT 0x1f +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_BMSK 0x40000000 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_SHFT 0x1e +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_BMSK 0x20000000 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_SHFT 0x1d +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_BMSK 0x10000000 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_SHFT 0x1c +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_BMSK 0x8000000 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_SHFT 0x1b +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_BMSK 0x4000000 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_SHFT 0x1a +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_BMSK 0x2000000 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_SHFT 0x19 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_AUX_CLK_ENA_BMSK 0x1000000 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_AUX_CLK_ENA_SHFT 0x18 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_AUX_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_AUX_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_ENA_BMSK 0x800000 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_ENA_SHFT 0x17 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_ENA_BMSK 0x400000 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_ENA_SHFT 0x16 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_BMSK 0x200000 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_SHFT 0x15 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_ENA_BMSK 0x100000 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_ENA_SHFT 0x14 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_ENA_BMSK 0x80000 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_ENA_SHFT 0x13 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_ENA_BMSK 0x40000 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_ENA_SHFT 0x12 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_BMSK 0x20000 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_SHFT 0x11 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_BMSK 0x10000 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_SHFT 0x10 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_BMSK 0x8000 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_SHFT 0xf +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_TME_GPLL0_CLK_SRC_ENA_BMSK 0x4000 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_TME_GPLL0_CLK_SRC_ENA_SHFT 0xe +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_TME_GPLL0_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_TME_GPLL0_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_BMSK 0x2000 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_SHFT 0xd +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_ENA_BMSK 0x1000 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_ENA_SHFT 0xc +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_QMIP_PCIE_AHB_CLK_ENA_BMSK 0x800 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_QMIP_PCIE_AHB_CLK_ENA_SHFT 0xb +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_QMIP_PCIE_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_QMIP_PCIE_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_BMSK 0x400 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_SHFT 0xa +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_BMSK 0x100 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_SHFT 0x8 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_BMSK 0x40 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_SHFT 0x6 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_BMSK 0x20 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_SHFT 0x5 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_BMSK 0x10 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_SHFT 0x4 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_BMSK 0x8 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_SHFT 0x3 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_BMSK 0x4 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_SHFT 0x2 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_BMSK 0x2 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_SHFT 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_BMSK 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_SHFT 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00042004) +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00042004) +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00042004) +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_RMSK 0xfffffd7f +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_ADDR, HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_RMSK) +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_ADDR, m) +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_ADDR,v) +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_IN) +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_SLEEP_ENA_BMSK 0x80000000 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_SLEEP_ENA_SHFT 0x1f +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_BMSK 0x40000000 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_SHFT 0x1e +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_BMSK 0x20000000 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_SHFT 0x1d +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_BMSK 0x10000000 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_SHFT 0x1c +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_BMSK 0x8000000 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_SHFT 0x1b +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_BMSK 0x4000000 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_SHFT 0x1a +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK 0x2000000 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT 0x19 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_AUX_CLK_SLEEP_ENA_BMSK 0x1000000 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_AUX_CLK_SLEEP_ENA_SHFT 0x18 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_AUX_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_AUX_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_SLEEP_ENA_BMSK 0x800000 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_SLEEP_ENA_SHFT 0x17 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_SLEEP_ENA_BMSK 0x400000 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_SLEEP_ENA_SHFT 0x16 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_BMSK 0x200000 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_SHFT 0x15 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_SLEEP_ENA_BMSK 0x100000 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_SLEEP_ENA_SHFT 0x14 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_SLEEP_ENA_BMSK 0x80000 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_SLEEP_ENA_SHFT 0x13 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_SLEEP_ENA_BMSK 0x40000 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_SLEEP_ENA_SHFT 0x12 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK 0x20000 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT 0x11 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK 0x10000 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT 0x10 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_BMSK 0x8000 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_SHFT 0xf +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_TME_GPLL0_CLK_SRC_SLEEP_ENA_BMSK 0x4000 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_TME_GPLL0_CLK_SRC_SLEEP_ENA_SHFT 0xe +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_TME_GPLL0_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_TME_GPLL0_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_BMSK 0x2000 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_SHFT 0xd +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_SLEEP_ENA_BMSK 0x1000 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_SLEEP_ENA_SHFT 0xc +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_QMIP_PCIE_AHB_CLK_SLEEP_ENA_BMSK 0x800 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_QMIP_PCIE_AHB_CLK_SLEEP_ENA_SHFT 0xb +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_QMIP_PCIE_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_QMIP_PCIE_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_BMSK 0x400 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_SHFT 0xa +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_BMSK 0x100 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_SHFT 0x8 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_BMSK 0x40 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_SHFT 0x6 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_BMSK 0x20 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_SHFT 0x5 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_BMSK 0x10 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_SHFT 0x4 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_BMSK 0x8 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_SHFT 0x3 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_BMSK 0x4 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_SHFT 0x2 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_BMSK 0x2 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_SHFT 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_BMSK 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_SHFT 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00042008) +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00042008) +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00042008) +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_RMSK 0xffffffff +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_ATTR 0x3 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_IN \ + in_dword_masked(HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_ADDR, HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_RMSK) +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_INM(m) \ + in_dword_masked(HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_ADDR, m) +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_OUT(v) \ + out_dword(HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_ADDR,v) +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_ADDR,m,v,HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_IN) +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_ENA_BMSK 0x80000000 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_ENA_SHFT 0x1f +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_ENA_BMSK 0x40000000 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_ENA_SHFT 0x1e +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_ENA_BMSK 0x20000000 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_ENA_SHFT 0x1d +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_ENA_BMSK 0x10000000 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_ENA_SHFT 0x1c +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_BMSK 0x8000000 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_SHFT 0x1b +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_BMSK 0x4000000 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_SHFT 0x1a +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_BMSK 0x2000000 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_SHFT 0x19 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_BMSK 0x1000000 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_SHFT 0x18 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_BMSK 0x800000 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_SHFT 0x17 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_BMSK 0x400000 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_SHFT 0x16 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_BMSK 0x200000 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_SHFT 0x15 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_BMSK 0x100000 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_SHFT 0x14 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_BMSK 0x80000 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_SHFT 0x13 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_BMSK 0x40000 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_SHFT 0x12 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S7_CLK_ENA_BMSK 0x20000 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S7_CLK_ENA_SHFT 0x11 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S7_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S7_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S6_CLK_ENA_BMSK 0x10000 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S6_CLK_ENA_SHFT 0x10 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S6_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S6_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S5_CLK_ENA_BMSK 0x8000 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S5_CLK_ENA_SHFT 0xf +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S5_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S5_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S4_CLK_ENA_BMSK 0x4000 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S4_CLK_ENA_SHFT 0xe +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S4_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S4_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S3_CLK_ENA_BMSK 0x2000 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S3_CLK_ENA_SHFT 0xd +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S3_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S3_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S2_CLK_ENA_BMSK 0x1000 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S2_CLK_ENA_SHFT 0xc +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S2_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S2_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S1_CLK_ENA_BMSK 0x800 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S1_CLK_ENA_SHFT 0xb +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S1_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S1_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S0_CLK_ENA_BMSK 0x400 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S0_CLK_ENA_SHFT 0xa +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S0_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S0_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_ENA_BMSK 0x200 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_ENA_SHFT 0x9 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_ENA_BMSK 0x100 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_ENA_SHFT 0x8 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_ENA_BMSK 0x80 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_ENA_SHFT 0x7 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_ENA_BMSK 0x40 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_ENA_SHFT 0x6 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_BMSK 0x20 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_SHFT 0x5 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_BMSK 0x10 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_SHFT 0x4 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_BMSK 0x8 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_SHFT 0x3 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_BMSK 0x4 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_SHFT 0x2 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_BMSK 0x2 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_SHFT 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_BMSK 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_SHFT 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004200c) +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004200c) +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004200c) +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_RMSK 0xffffffff +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_ATTR 0x3 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_IN \ + in_dword_masked(HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_ADDR, HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_RMSK) +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_INM(m) \ + in_dword_masked(HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_ADDR, m) +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_OUT(v) \ + out_dword(HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_ADDR,v) +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_ADDR,m,v,HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_IN) +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_SLEEP_ENA_BMSK 0x80000000 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_SLEEP_ENA_SHFT 0x1f +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_SLEEP_ENA_BMSK 0x40000000 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_SLEEP_ENA_SHFT 0x1e +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_SLEEP_ENA_BMSK 0x20000000 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_SLEEP_ENA_SHFT 0x1d +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_SLEEP_ENA_BMSK 0x10000000 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_SLEEP_ENA_SHFT 0x1c +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_BMSK 0x8000000 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_SHFT 0x1b +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_BMSK 0x4000000 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_SHFT 0x1a +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_BMSK 0x2000000 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_SHFT 0x19 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_BMSK 0x1000000 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_SHFT 0x18 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_BMSK 0x800000 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_SHFT 0x17 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_BMSK 0x400000 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_SHFT 0x16 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_BMSK 0x200000 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_SHFT 0x15 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_BMSK 0x100000 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_SHFT 0x14 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_BMSK 0x80000 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_SHFT 0x13 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_BMSK 0x40000 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_SHFT 0x12 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S7_CLK_SLEEP_ENA_BMSK 0x20000 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S7_CLK_SLEEP_ENA_SHFT 0x11 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S7_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S7_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S6_CLK_SLEEP_ENA_BMSK 0x10000 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S6_CLK_SLEEP_ENA_SHFT 0x10 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S6_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S6_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S5_CLK_SLEEP_ENA_BMSK 0x8000 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S5_CLK_SLEEP_ENA_SHFT 0xf +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S5_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S5_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S4_CLK_SLEEP_ENA_BMSK 0x4000 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S4_CLK_SLEEP_ENA_SHFT 0xe +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S4_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S4_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S3_CLK_SLEEP_ENA_BMSK 0x2000 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S3_CLK_SLEEP_ENA_SHFT 0xd +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S3_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S3_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S2_CLK_SLEEP_ENA_BMSK 0x1000 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S2_CLK_SLEEP_ENA_SHFT 0xc +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S2_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S2_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S1_CLK_SLEEP_ENA_BMSK 0x800 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S1_CLK_SLEEP_ENA_SHFT 0xb +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S1_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S1_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S0_CLK_SLEEP_ENA_BMSK 0x400 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S0_CLK_SLEEP_ENA_SHFT 0xa +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S0_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S0_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_SLEEP_ENA_BMSK 0x200 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_SLEEP_ENA_SHFT 0x9 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_SLEEP_ENA_BMSK 0x100 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_SLEEP_ENA_SHFT 0x8 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_SLEEP_ENA_BMSK 0x80 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_SLEEP_ENA_SHFT 0x7 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_SLEEP_ENA_BMSK 0x40 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_SLEEP_ENA_SHFT 0x6 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK 0x20 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT 0x5 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_BMSK 0x10 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_SHFT 0x4 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_BMSK 0x8 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_SHFT 0x3 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_BMSK 0x4 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_SHFT 0x2 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_BMSK 0x2 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_SHFT 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_BMSK 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_SHFT 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00042010) +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00042010) +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00042010) +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_RMSK 0x7ffff +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_ATTR 0x3 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_IN \ + in_dword_masked(HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_ADDR, HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_RMSK) +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_INM(m) \ + in_dword_masked(HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_ADDR, m) +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_OUT(v) \ + out_dword(HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_ADDR,v) +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_ADDR,m,v,HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_IN) +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_ENA_BMSK 0x40000 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_ENA_SHFT 0x12 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_ENA_BMSK 0x20000 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_ENA_SHFT 0x11 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_ENA_BMSK 0x10000 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_ENA_SHFT 0x10 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S9_CLK_ENA_BMSK 0x8000 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S9_CLK_ENA_SHFT 0xf +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S9_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S9_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S8_CLK_ENA_BMSK 0x4000 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S8_CLK_ENA_SHFT 0xe +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S8_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S8_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_ENA_BMSK 0x2000 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_ENA_SHFT 0xd +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_ENA_BMSK 0x1000 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_ENA_SHFT 0xc +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_ENA_BMSK 0x800 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_ENA_SHFT 0xb +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_ENA_BMSK 0x400 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_ENA_SHFT 0xa +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_BMSK 0x200 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_SHFT 0x9 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_BMSK 0x100 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_SHFT 0x8 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_BMSK 0x80 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_SHFT 0x7 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_BMSK 0x40 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_SHFT 0x6 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_BMSK 0x20 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_SHFT 0x5 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_BMSK 0x10 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_SHFT 0x4 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_BMSK 0x8 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_SHFT 0x3 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_BMSK 0x4 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_SHFT 0x2 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_BMSK 0x2 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_SHFT 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_BMSK 0x1 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_SHFT 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00042014) +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00042014) +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00042014) +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_RMSK 0x7ffff +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_ATTR 0x3 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_IN \ + in_dword_masked(HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_ADDR, HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_RMSK) +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_INM(m) \ + in_dword_masked(HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_ADDR, m) +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_OUT(v) \ + out_dword(HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_ADDR,v) +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_ADDR,m,v,HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_IN) +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_SLEEP_ENA_BMSK 0x40000 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_SLEEP_ENA_SHFT 0x12 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_SLEEP_ENA_BMSK 0x20000 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_SLEEP_ENA_SHFT 0x11 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_SLEEP_ENA_BMSK 0x10000 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_SLEEP_ENA_SHFT 0x10 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S9_CLK_SLEEP_ENA_BMSK 0x8000 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S9_CLK_SLEEP_ENA_SHFT 0xf +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S9_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S9_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S8_CLK_SLEEP_ENA_BMSK 0x4000 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S8_CLK_SLEEP_ENA_SHFT 0xe +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S8_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S8_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_SLEEP_ENA_BMSK 0x2000 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_SLEEP_ENA_SHFT 0xd +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_SLEEP_ENA_BMSK 0x1000 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_SLEEP_ENA_SHFT 0xc +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_SLEEP_ENA_BMSK 0x800 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_SLEEP_ENA_SHFT 0xb +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_SLEEP_ENA_BMSK 0x400 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_SLEEP_ENA_SHFT 0xa +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_BMSK 0x200 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_SHFT 0x9 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_BMSK 0x100 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_SHFT 0x8 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_BMSK 0x80 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_SHFT 0x7 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_BMSK 0x40 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_SHFT 0x6 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_BMSK 0x20 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_SHFT 0x5 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_BMSK 0x10 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_SHFT 0x4 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_BMSK 0x8 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_SHFT 0x3 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_BMSK 0x4 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_SHFT 0x2 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_BMSK 0x2 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_SHFT 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_BMSK 0x1 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_SHFT 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00042018) +#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00042018) +#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00042018) +#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_ADDR, HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_RMSK) +#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_ADDR, m) +#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_ADDR,v) +#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_IN) +#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004201c) +#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004201c) +#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004201c) +#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_ADDR, HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_RMSK) +#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_ADDR, m) +#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_ADDR,v) +#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_IN) +#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00043038) +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00043038) +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00043038) +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_RMSK 0xfffffd7f +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_ADDR, HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_RMSK) +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_ADDR, m) +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_ADDR,v) +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_IN) +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_ENA_BMSK 0x80000000 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_ENA_SHFT 0x1f +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_BMSK 0x40000000 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_SHFT 0x1e +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_BMSK 0x20000000 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_SHFT 0x1d +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_BMSK 0x10000000 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_SHFT 0x1c +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_BMSK 0x8000000 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_SHFT 0x1b +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_BMSK 0x4000000 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_SHFT 0x1a +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_BMSK 0x2000000 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_SHFT 0x19 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_AUX_CLK_ENA_BMSK 0x1000000 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_AUX_CLK_ENA_SHFT 0x18 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_AUX_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_AUX_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_ENA_BMSK 0x800000 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_ENA_SHFT 0x17 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_ENA_BMSK 0x400000 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_ENA_SHFT 0x16 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_BMSK 0x200000 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_SHFT 0x15 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_ENA_BMSK 0x100000 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_ENA_SHFT 0x14 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_ENA_BMSK 0x80000 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_ENA_SHFT 0x13 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_ENA_BMSK 0x40000 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_ENA_SHFT 0x12 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_BMSK 0x20000 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_SHFT 0x11 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_BMSK 0x10000 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_SHFT 0x10 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_BMSK 0x8000 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_SHFT 0xf +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_TME_GPLL0_CLK_SRC_ENA_BMSK 0x4000 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_TME_GPLL0_CLK_SRC_ENA_SHFT 0xe +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_TME_GPLL0_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_TME_GPLL0_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_BMSK 0x2000 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_SHFT 0xd +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_ENA_BMSK 0x1000 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_ENA_SHFT 0xc +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_QMIP_PCIE_AHB_CLK_ENA_BMSK 0x800 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_QMIP_PCIE_AHB_CLK_ENA_SHFT 0xb +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_QMIP_PCIE_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_QMIP_PCIE_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_BMSK 0x400 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_SHFT 0xa +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_BMSK 0x100 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_SHFT 0x8 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_BMSK 0x40 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_SHFT 0x6 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_BMSK 0x20 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_SHFT 0x5 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_BMSK 0x10 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_SHFT 0x4 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_BMSK 0x8 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_SHFT 0x3 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_BMSK 0x4 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_SHFT 0x2 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_BMSK 0x2 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_SHFT 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_BMSK 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_SHFT 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004303c) +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004303c) +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004303c) +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_RMSK 0xfffffd7f +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_ADDR, HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_RMSK) +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_ADDR, m) +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_ADDR,v) +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_IN) +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_SLEEP_ENA_BMSK 0x80000000 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_SLEEP_ENA_SHFT 0x1f +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_BMSK 0x40000000 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_SHFT 0x1e +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_BMSK 0x20000000 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_SHFT 0x1d +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_BMSK 0x10000000 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_SHFT 0x1c +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_BMSK 0x8000000 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_SHFT 0x1b +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_BMSK 0x4000000 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_SHFT 0x1a +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK 0x2000000 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT 0x19 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_AUX_CLK_SLEEP_ENA_BMSK 0x1000000 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_AUX_CLK_SLEEP_ENA_SHFT 0x18 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_AUX_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_AUX_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_SLEEP_ENA_BMSK 0x800000 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_SLEEP_ENA_SHFT 0x17 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_SLEEP_ENA_BMSK 0x400000 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_SLEEP_ENA_SHFT 0x16 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_BMSK 0x200000 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_SHFT 0x15 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_SLEEP_ENA_BMSK 0x100000 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_SLEEP_ENA_SHFT 0x14 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_SLEEP_ENA_BMSK 0x80000 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_SLEEP_ENA_SHFT 0x13 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_SLEEP_ENA_BMSK 0x40000 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_SLEEP_ENA_SHFT 0x12 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK 0x20000 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT 0x11 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK 0x10000 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT 0x10 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_BMSK 0x8000 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_SHFT 0xf +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_TME_GPLL0_CLK_SRC_SLEEP_ENA_BMSK 0x4000 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_TME_GPLL0_CLK_SRC_SLEEP_ENA_SHFT 0xe +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_TME_GPLL0_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_TME_GPLL0_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_BMSK 0x2000 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_SHFT 0xd +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_SLEEP_ENA_BMSK 0x1000 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_SLEEP_ENA_SHFT 0xc +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_QMIP_PCIE_AHB_CLK_SLEEP_ENA_BMSK 0x800 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_QMIP_PCIE_AHB_CLK_SLEEP_ENA_SHFT 0xb +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_QMIP_PCIE_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_QMIP_PCIE_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_BMSK 0x400 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_SHFT 0xa +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_BMSK 0x100 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_SHFT 0x8 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_BMSK 0x40 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_SHFT 0x6 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_BMSK 0x20 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_SHFT 0x5 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_BMSK 0x10 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_SHFT 0x4 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_BMSK 0x8 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_SHFT 0x3 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_BMSK 0x4 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_SHFT 0x2 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_BMSK 0x2 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_SHFT 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_BMSK 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_SHFT 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00043040) +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00043040) +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00043040) +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_RMSK 0xffffffff +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_ATTR 0x3 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_IN \ + in_dword_masked(HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_ADDR, HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_RMSK) +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_INM(m) \ + in_dword_masked(HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_ADDR, m) +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_OUT(v) \ + out_dword(HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_ADDR,v) +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_ADDR,m,v,HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_IN) +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_ENA_BMSK 0x80000000 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_ENA_SHFT 0x1f +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_ENA_BMSK 0x40000000 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_ENA_SHFT 0x1e +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_ENA_BMSK 0x20000000 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_ENA_SHFT 0x1d +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_ENA_BMSK 0x10000000 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_ENA_SHFT 0x1c +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_BMSK 0x8000000 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_SHFT 0x1b +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_BMSK 0x4000000 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_SHFT 0x1a +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_BMSK 0x2000000 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_SHFT 0x19 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_BMSK 0x1000000 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_SHFT 0x18 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_BMSK 0x800000 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_SHFT 0x17 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_BMSK 0x400000 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_SHFT 0x16 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_BMSK 0x200000 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_SHFT 0x15 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_BMSK 0x100000 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_SHFT 0x14 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_BMSK 0x80000 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_SHFT 0x13 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_BMSK 0x40000 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_SHFT 0x12 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S7_CLK_ENA_BMSK 0x20000 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S7_CLK_ENA_SHFT 0x11 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S7_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S7_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S6_CLK_ENA_BMSK 0x10000 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S6_CLK_ENA_SHFT 0x10 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S6_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S6_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S5_CLK_ENA_BMSK 0x8000 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S5_CLK_ENA_SHFT 0xf +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S5_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S5_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S4_CLK_ENA_BMSK 0x4000 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S4_CLK_ENA_SHFT 0xe +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S4_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S4_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S3_CLK_ENA_BMSK 0x2000 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S3_CLK_ENA_SHFT 0xd +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S3_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S3_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S2_CLK_ENA_BMSK 0x1000 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S2_CLK_ENA_SHFT 0xc +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S2_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S2_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S1_CLK_ENA_BMSK 0x800 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S1_CLK_ENA_SHFT 0xb +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S1_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S1_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S0_CLK_ENA_BMSK 0x400 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S0_CLK_ENA_SHFT 0xa +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S0_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S0_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_ENA_BMSK 0x200 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_ENA_SHFT 0x9 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_ENA_BMSK 0x100 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_ENA_SHFT 0x8 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_ENA_BMSK 0x80 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_ENA_SHFT 0x7 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_ENA_BMSK 0x40 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_ENA_SHFT 0x6 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_BMSK 0x20 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_SHFT 0x5 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_BMSK 0x10 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_SHFT 0x4 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_BMSK 0x8 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_SHFT 0x3 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_BMSK 0x4 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_SHFT 0x2 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_BMSK 0x2 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_SHFT 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_BMSK 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_SHFT 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00043044) +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00043044) +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00043044) +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_RMSK 0xffffffff +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_ATTR 0x3 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_IN \ + in_dword_masked(HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_ADDR, HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_RMSK) +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_INM(m) \ + in_dword_masked(HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_ADDR, m) +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_OUT(v) \ + out_dword(HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_ADDR,v) +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_ADDR,m,v,HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_IN) +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_SLEEP_ENA_BMSK 0x80000000 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_SLEEP_ENA_SHFT 0x1f +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_SLEEP_ENA_BMSK 0x40000000 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_SLEEP_ENA_SHFT 0x1e +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_SLEEP_ENA_BMSK 0x20000000 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_SLEEP_ENA_SHFT 0x1d +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_SLEEP_ENA_BMSK 0x10000000 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_SLEEP_ENA_SHFT 0x1c +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_BMSK 0x8000000 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_SHFT 0x1b +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_BMSK 0x4000000 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_SHFT 0x1a +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_BMSK 0x2000000 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_SHFT 0x19 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_BMSK 0x1000000 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_SHFT 0x18 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_BMSK 0x800000 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_SHFT 0x17 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_BMSK 0x400000 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_SHFT 0x16 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_BMSK 0x200000 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_SHFT 0x15 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_BMSK 0x100000 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_SHFT 0x14 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_BMSK 0x80000 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_SHFT 0x13 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_BMSK 0x40000 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_SHFT 0x12 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S7_CLK_SLEEP_ENA_BMSK 0x20000 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S7_CLK_SLEEP_ENA_SHFT 0x11 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S7_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S7_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S6_CLK_SLEEP_ENA_BMSK 0x10000 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S6_CLK_SLEEP_ENA_SHFT 0x10 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S6_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S6_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S5_CLK_SLEEP_ENA_BMSK 0x8000 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S5_CLK_SLEEP_ENA_SHFT 0xf +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S5_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S5_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S4_CLK_SLEEP_ENA_BMSK 0x4000 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S4_CLK_SLEEP_ENA_SHFT 0xe +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S4_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S4_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S3_CLK_SLEEP_ENA_BMSK 0x2000 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S3_CLK_SLEEP_ENA_SHFT 0xd +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S3_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S3_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S2_CLK_SLEEP_ENA_BMSK 0x1000 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S2_CLK_SLEEP_ENA_SHFT 0xc +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S2_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S2_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S1_CLK_SLEEP_ENA_BMSK 0x800 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S1_CLK_SLEEP_ENA_SHFT 0xb +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S1_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S1_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S0_CLK_SLEEP_ENA_BMSK 0x400 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S0_CLK_SLEEP_ENA_SHFT 0xa +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S0_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S0_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_SLEEP_ENA_BMSK 0x200 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_SLEEP_ENA_SHFT 0x9 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_SLEEP_ENA_BMSK 0x100 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_SLEEP_ENA_SHFT 0x8 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_SLEEP_ENA_BMSK 0x80 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_SLEEP_ENA_SHFT 0x7 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_SLEEP_ENA_BMSK 0x40 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_SLEEP_ENA_SHFT 0x6 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK 0x20 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT 0x5 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_BMSK 0x10 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_SHFT 0x4 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_BMSK 0x8 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_SHFT 0x3 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_BMSK 0x4 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_SHFT 0x2 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_BMSK 0x2 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_SHFT 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_BMSK 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_SHFT 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00043048) +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00043048) +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00043048) +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_RMSK 0x7ffff +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_ATTR 0x3 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_IN \ + in_dword_masked(HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_ADDR, HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_RMSK) +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_INM(m) \ + in_dword_masked(HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_ADDR, m) +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_OUT(v) \ + out_dword(HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_ADDR,v) +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_ADDR,m,v,HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_IN) +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_ENA_BMSK 0x40000 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_ENA_SHFT 0x12 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_ENA_BMSK 0x20000 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_ENA_SHFT 0x11 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_ENA_BMSK 0x10000 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_ENA_SHFT 0x10 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S9_CLK_ENA_BMSK 0x8000 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S9_CLK_ENA_SHFT 0xf +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S9_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S9_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S8_CLK_ENA_BMSK 0x4000 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S8_CLK_ENA_SHFT 0xe +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S8_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S8_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_ENA_BMSK 0x2000 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_ENA_SHFT 0xd +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_ENA_BMSK 0x1000 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_ENA_SHFT 0xc +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_ENA_BMSK 0x800 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_ENA_SHFT 0xb +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_ENA_BMSK 0x400 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_ENA_SHFT 0xa +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_BMSK 0x200 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_SHFT 0x9 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_BMSK 0x100 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_SHFT 0x8 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_BMSK 0x80 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_SHFT 0x7 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_BMSK 0x40 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_SHFT 0x6 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_BMSK 0x20 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_SHFT 0x5 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_BMSK 0x10 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_SHFT 0x4 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_BMSK 0x8 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_SHFT 0x3 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_BMSK 0x4 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_SHFT 0x2 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_BMSK 0x2 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_SHFT 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_BMSK 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_SHFT 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004304c) +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004304c) +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004304c) +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_RMSK 0x7ffff +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_ATTR 0x3 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_IN \ + in_dword_masked(HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_ADDR, HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_RMSK) +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_INM(m) \ + in_dword_masked(HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_ADDR, m) +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_OUT(v) \ + out_dword(HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_ADDR,v) +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_ADDR,m,v,HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_IN) +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_SLEEP_ENA_BMSK 0x40000 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_SLEEP_ENA_SHFT 0x12 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_SLEEP_ENA_BMSK 0x20000 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_SLEEP_ENA_SHFT 0x11 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_SLEEP_ENA_BMSK 0x10000 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_SLEEP_ENA_SHFT 0x10 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S9_CLK_SLEEP_ENA_BMSK 0x8000 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S9_CLK_SLEEP_ENA_SHFT 0xf +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S9_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S9_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S8_CLK_SLEEP_ENA_BMSK 0x4000 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S8_CLK_SLEEP_ENA_SHFT 0xe +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S8_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S8_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_SLEEP_ENA_BMSK 0x2000 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_SLEEP_ENA_SHFT 0xd +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_SLEEP_ENA_BMSK 0x1000 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_SLEEP_ENA_SHFT 0xc +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_SLEEP_ENA_BMSK 0x800 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_SLEEP_ENA_SHFT 0xb +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_SLEEP_ENA_BMSK 0x400 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_SLEEP_ENA_SHFT 0xa +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_BMSK 0x200 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_SHFT 0x9 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_BMSK 0x100 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_SHFT 0x8 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_BMSK 0x80 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_SHFT 0x7 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_BMSK 0x40 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_SHFT 0x6 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_BMSK 0x20 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_SHFT 0x5 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_BMSK 0x10 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_SHFT 0x4 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_BMSK 0x8 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_SHFT 0x3 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_BMSK 0x4 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_SHFT 0x2 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_BMSK 0x2 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_SHFT 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_BMSK 0x1 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_SHFT 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00043050) +#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00043050) +#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00043050) +#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_ADDR, HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_RMSK) +#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_ADDR, m) +#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_ADDR,v) +#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_IN) +#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00043054) +#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00043054) +#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00043054) +#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_ADDR, HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_RMSK) +#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_ADDR, m) +#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_ADDR,v) +#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_IN) +#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00045000) +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00045000) +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00045000) +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_RMSK 0xfffffd7f +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_ADDR, HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_RMSK) +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_ADDR, m) +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_ADDR,v) +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_IN) +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_ENA_BMSK 0x80000000 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_ENA_SHFT 0x1f +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_BMSK 0x40000000 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_SHFT 0x1e +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_BMSK 0x20000000 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_SHFT 0x1d +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_BMSK 0x10000000 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_SHFT 0x1c +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_BMSK 0x8000000 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_SHFT 0x1b +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_BMSK 0x4000000 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_SHFT 0x1a +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_BMSK 0x2000000 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_SHFT 0x19 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_AUX_CLK_ENA_BMSK 0x1000000 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_AUX_CLK_ENA_SHFT 0x18 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_AUX_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_AUX_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_ENA_BMSK 0x800000 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_ENA_SHFT 0x17 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_ENA_BMSK 0x400000 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_ENA_SHFT 0x16 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_BMSK 0x200000 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_SHFT 0x15 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_ENA_BMSK 0x100000 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_ENA_SHFT 0x14 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_ENA_BMSK 0x80000 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_ENA_SHFT 0x13 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_ENA_BMSK 0x40000 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_ENA_SHFT 0x12 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_BMSK 0x20000 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_SHFT 0x11 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_BMSK 0x10000 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_SHFT 0x10 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_BMSK 0x8000 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_SHFT 0xf +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_TME_GPLL0_CLK_SRC_ENA_BMSK 0x4000 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_TME_GPLL0_CLK_SRC_ENA_SHFT 0xe +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_TME_GPLL0_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_TME_GPLL0_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_BMSK 0x2000 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_SHFT 0xd +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_ENA_BMSK 0x1000 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_ENA_SHFT 0xc +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_QMIP_PCIE_AHB_CLK_ENA_BMSK 0x800 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_QMIP_PCIE_AHB_CLK_ENA_SHFT 0xb +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_QMIP_PCIE_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_QMIP_PCIE_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_BMSK 0x400 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_SHFT 0xa +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_BMSK 0x100 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_SHFT 0x8 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_BMSK 0x40 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_SHFT 0x6 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_BMSK 0x20 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_SHFT 0x5 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_BMSK 0x10 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_SHFT 0x4 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_BMSK 0x8 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_SHFT 0x3 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_BMSK 0x4 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_SHFT 0x2 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_BMSK 0x2 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_SHFT 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_BMSK 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_SHFT 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00045004) +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00045004) +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00045004) +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_RMSK 0xfffffd7f +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_ADDR, HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_RMSK) +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_ADDR, m) +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_ADDR,v) +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_IN) +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_SLEEP_ENA_BMSK 0x80000000 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_SLEEP_ENA_SHFT 0x1f +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_BMSK 0x40000000 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_SHFT 0x1e +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_BMSK 0x20000000 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_SHFT 0x1d +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_BMSK 0x10000000 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_SHFT 0x1c +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_BMSK 0x8000000 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_SHFT 0x1b +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_BMSK 0x4000000 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_SHFT 0x1a +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK 0x2000000 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT 0x19 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_AUX_CLK_SLEEP_ENA_BMSK 0x1000000 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_AUX_CLK_SLEEP_ENA_SHFT 0x18 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_AUX_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_AUX_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_SLEEP_ENA_BMSK 0x800000 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_SLEEP_ENA_SHFT 0x17 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_SLEEP_ENA_BMSK 0x400000 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_SLEEP_ENA_SHFT 0x16 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_BMSK 0x200000 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_SHFT 0x15 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_SLEEP_ENA_BMSK 0x100000 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_SLEEP_ENA_SHFT 0x14 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_SLEEP_ENA_BMSK 0x80000 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_SLEEP_ENA_SHFT 0x13 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_SLEEP_ENA_BMSK 0x40000 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_SLEEP_ENA_SHFT 0x12 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK 0x20000 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT 0x11 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK 0x10000 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT 0x10 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_BMSK 0x8000 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_SHFT 0xf +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_TME_GPLL0_CLK_SRC_SLEEP_ENA_BMSK 0x4000 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_TME_GPLL0_CLK_SRC_SLEEP_ENA_SHFT 0xe +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_TME_GPLL0_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_TME_GPLL0_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_BMSK 0x2000 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_SHFT 0xd +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_SLEEP_ENA_BMSK 0x1000 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_SLEEP_ENA_SHFT 0xc +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_QMIP_PCIE_AHB_CLK_SLEEP_ENA_BMSK 0x800 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_QMIP_PCIE_AHB_CLK_SLEEP_ENA_SHFT 0xb +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_QMIP_PCIE_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_QMIP_PCIE_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_BMSK 0x400 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_SHFT 0xa +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_BMSK 0x100 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_SHFT 0x8 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_BMSK 0x40 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_SHFT 0x6 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_BMSK 0x20 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_SHFT 0x5 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_BMSK 0x10 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_SHFT 0x4 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_BMSK 0x8 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_SHFT 0x3 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_BMSK 0x4 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_SHFT 0x2 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_BMSK 0x2 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_SHFT 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_BMSK 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_SHFT 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00045008) +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00045008) +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00045008) +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_RMSK 0xffffffff +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_ATTR 0x3 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_IN \ + in_dword_masked(HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_ADDR, HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_RMSK) +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_INM(m) \ + in_dword_masked(HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_ADDR, m) +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_OUT(v) \ + out_dword(HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_ADDR,v) +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_ADDR,m,v,HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_IN) +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_ENA_BMSK 0x80000000 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_ENA_SHFT 0x1f +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_ENA_BMSK 0x40000000 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_ENA_SHFT 0x1e +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_ENA_BMSK 0x20000000 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_ENA_SHFT 0x1d +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_ENA_BMSK 0x10000000 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_ENA_SHFT 0x1c +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_BMSK 0x8000000 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_SHFT 0x1b +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_BMSK 0x4000000 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_SHFT 0x1a +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_BMSK 0x2000000 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_SHFT 0x19 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_BMSK 0x1000000 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_SHFT 0x18 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_BMSK 0x800000 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_SHFT 0x17 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_BMSK 0x400000 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_SHFT 0x16 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_BMSK 0x200000 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_SHFT 0x15 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_BMSK 0x100000 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_SHFT 0x14 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_BMSK 0x80000 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_SHFT 0x13 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_BMSK 0x40000 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_SHFT 0x12 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S7_CLK_ENA_BMSK 0x20000 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S7_CLK_ENA_SHFT 0x11 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S7_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S7_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S6_CLK_ENA_BMSK 0x10000 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S6_CLK_ENA_SHFT 0x10 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S6_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S6_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S5_CLK_ENA_BMSK 0x8000 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S5_CLK_ENA_SHFT 0xf +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S5_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S5_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S4_CLK_ENA_BMSK 0x4000 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S4_CLK_ENA_SHFT 0xe +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S4_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S4_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S3_CLK_ENA_BMSK 0x2000 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S3_CLK_ENA_SHFT 0xd +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S3_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S3_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S2_CLK_ENA_BMSK 0x1000 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S2_CLK_ENA_SHFT 0xc +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S2_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S2_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S1_CLK_ENA_BMSK 0x800 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S1_CLK_ENA_SHFT 0xb +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S1_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S1_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S0_CLK_ENA_BMSK 0x400 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S0_CLK_ENA_SHFT 0xa +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S0_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S0_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_ENA_BMSK 0x200 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_ENA_SHFT 0x9 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_ENA_BMSK 0x100 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_ENA_SHFT 0x8 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_ENA_BMSK 0x80 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_ENA_SHFT 0x7 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_ENA_BMSK 0x40 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_ENA_SHFT 0x6 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_BMSK 0x20 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_SHFT 0x5 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_BMSK 0x10 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_SHFT 0x4 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_BMSK 0x8 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_SHFT 0x3 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_BMSK 0x4 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_SHFT 0x2 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_BMSK 0x2 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_SHFT 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_BMSK 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_SHFT 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004500c) +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004500c) +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004500c) +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_RMSK 0xffffffff +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_ATTR 0x3 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_IN \ + in_dword_masked(HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_ADDR, HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_RMSK) +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_INM(m) \ + in_dword_masked(HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_ADDR, m) +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_OUT(v) \ + out_dword(HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_ADDR,v) +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_ADDR,m,v,HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_IN) +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_SLEEP_ENA_BMSK 0x80000000 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_SLEEP_ENA_SHFT 0x1f +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_SLEEP_ENA_BMSK 0x40000000 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_SLEEP_ENA_SHFT 0x1e +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_SLEEP_ENA_BMSK 0x20000000 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_SLEEP_ENA_SHFT 0x1d +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_SLEEP_ENA_BMSK 0x10000000 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_SLEEP_ENA_SHFT 0x1c +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_BMSK 0x8000000 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_SHFT 0x1b +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_BMSK 0x4000000 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_SHFT 0x1a +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_BMSK 0x2000000 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_SHFT 0x19 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_BMSK 0x1000000 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_SHFT 0x18 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_BMSK 0x800000 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_SHFT 0x17 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_BMSK 0x400000 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_SHFT 0x16 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_BMSK 0x200000 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_SHFT 0x15 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_BMSK 0x100000 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_SHFT 0x14 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_BMSK 0x80000 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_SHFT 0x13 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_BMSK 0x40000 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_SHFT 0x12 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S7_CLK_SLEEP_ENA_BMSK 0x20000 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S7_CLK_SLEEP_ENA_SHFT 0x11 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S7_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S7_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S6_CLK_SLEEP_ENA_BMSK 0x10000 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S6_CLK_SLEEP_ENA_SHFT 0x10 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S6_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S6_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S5_CLK_SLEEP_ENA_BMSK 0x8000 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S5_CLK_SLEEP_ENA_SHFT 0xf +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S5_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S5_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S4_CLK_SLEEP_ENA_BMSK 0x4000 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S4_CLK_SLEEP_ENA_SHFT 0xe +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S4_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S4_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S3_CLK_SLEEP_ENA_BMSK 0x2000 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S3_CLK_SLEEP_ENA_SHFT 0xd +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S3_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S3_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S2_CLK_SLEEP_ENA_BMSK 0x1000 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S2_CLK_SLEEP_ENA_SHFT 0xc +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S2_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S2_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S1_CLK_SLEEP_ENA_BMSK 0x800 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S1_CLK_SLEEP_ENA_SHFT 0xb +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S1_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S1_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S0_CLK_SLEEP_ENA_BMSK 0x400 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S0_CLK_SLEEP_ENA_SHFT 0xa +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S0_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S0_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_SLEEP_ENA_BMSK 0x200 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_SLEEP_ENA_SHFT 0x9 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_SLEEP_ENA_BMSK 0x100 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_SLEEP_ENA_SHFT 0x8 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_SLEEP_ENA_BMSK 0x80 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_SLEEP_ENA_SHFT 0x7 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_SLEEP_ENA_BMSK 0x40 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_SLEEP_ENA_SHFT 0x6 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK 0x20 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT 0x5 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_BMSK 0x10 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_SHFT 0x4 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_BMSK 0x8 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_SHFT 0x3 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_BMSK 0x4 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_SHFT 0x2 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_BMSK 0x2 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_SHFT 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_BMSK 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_SHFT 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00045010) +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00045010) +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00045010) +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_RMSK 0x7ffff +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_ATTR 0x3 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_IN \ + in_dword_masked(HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_ADDR, HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_RMSK) +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_INM(m) \ + in_dword_masked(HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_ADDR, m) +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_OUT(v) \ + out_dword(HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_ADDR,v) +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_ADDR,m,v,HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_IN) +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_ENA_BMSK 0x40000 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_ENA_SHFT 0x12 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_ENA_BMSK 0x20000 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_ENA_SHFT 0x11 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_ENA_BMSK 0x10000 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_ENA_SHFT 0x10 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S9_CLK_ENA_BMSK 0x8000 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S9_CLK_ENA_SHFT 0xf +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S9_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S9_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S8_CLK_ENA_BMSK 0x4000 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S8_CLK_ENA_SHFT 0xe +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S8_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S8_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_ENA_BMSK 0x2000 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_ENA_SHFT 0xd +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_ENA_BMSK 0x1000 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_ENA_SHFT 0xc +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_ENA_BMSK 0x800 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_ENA_SHFT 0xb +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_ENA_BMSK 0x400 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_ENA_SHFT 0xa +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_BMSK 0x200 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_SHFT 0x9 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_BMSK 0x100 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_SHFT 0x8 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_BMSK 0x80 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_SHFT 0x7 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_BMSK 0x40 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_SHFT 0x6 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_BMSK 0x20 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_SHFT 0x5 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_BMSK 0x10 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_SHFT 0x4 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_BMSK 0x8 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_SHFT 0x3 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_BMSK 0x4 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_SHFT 0x2 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_BMSK 0x2 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_SHFT 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_BMSK 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_SHFT 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00045014) +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00045014) +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00045014) +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_RMSK 0x7ffff +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_ATTR 0x3 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_IN \ + in_dword_masked(HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_ADDR, HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_RMSK) +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_INM(m) \ + in_dword_masked(HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_ADDR, m) +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_OUT(v) \ + out_dword(HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_ADDR,v) +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_ADDR,m,v,HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_IN) +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_SLEEP_ENA_BMSK 0x40000 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_SLEEP_ENA_SHFT 0x12 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_SLEEP_ENA_BMSK 0x20000 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_SLEEP_ENA_SHFT 0x11 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_SLEEP_ENA_BMSK 0x10000 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_SLEEP_ENA_SHFT 0x10 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S9_CLK_SLEEP_ENA_BMSK 0x8000 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S9_CLK_SLEEP_ENA_SHFT 0xf +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S9_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S9_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S8_CLK_SLEEP_ENA_BMSK 0x4000 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S8_CLK_SLEEP_ENA_SHFT 0xe +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S8_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S8_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_SLEEP_ENA_BMSK 0x2000 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_SLEEP_ENA_SHFT 0xd +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_SLEEP_ENA_BMSK 0x1000 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_SLEEP_ENA_SHFT 0xc +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_SLEEP_ENA_BMSK 0x800 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_SLEEP_ENA_SHFT 0xb +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_SLEEP_ENA_BMSK 0x400 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_SLEEP_ENA_SHFT 0xa +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_BMSK 0x200 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_SHFT 0x9 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_BMSK 0x100 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_SHFT 0x8 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_BMSK 0x80 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_SHFT 0x7 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_BMSK 0x40 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_SHFT 0x6 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_BMSK 0x20 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_SHFT 0x5 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_BMSK 0x10 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_SHFT 0x4 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_BMSK 0x8 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_SHFT 0x3 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_BMSK 0x4 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_SHFT 0x2 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_BMSK 0x2 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_SHFT 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_BMSK 0x1 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_SHFT 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00045018) +#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00045018) +#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00045018) +#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_ADDR, HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_RMSK) +#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_ADDR, m) +#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_ADDR,v) +#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_IN) +#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004501c) +#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004501c) +#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004501c) +#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_ADDR, HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_RMSK) +#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_ADDR, m) +#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_ADDR,v) +#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_IN) +#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004b000) +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004b000) +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004b000) +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_RMSK 0xfffffd7f +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_ADDR, HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_RMSK) +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_ADDR, m) +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_ADDR,v) +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_IN) +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_ENA_BMSK 0x80000000 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_ENA_SHFT 0x1f +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_BMSK 0x40000000 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_SHFT 0x1e +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_BMSK 0x20000000 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_SHFT 0x1d +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_BMSK 0x10000000 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_SHFT 0x1c +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_BMSK 0x8000000 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_SHFT 0x1b +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_BMSK 0x4000000 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_SHFT 0x1a +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_BMSK 0x2000000 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_SHFT 0x19 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_AUX_CLK_ENA_BMSK 0x1000000 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_AUX_CLK_ENA_SHFT 0x18 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_AUX_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_AUX_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_ENA_BMSK 0x800000 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_ENA_SHFT 0x17 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_ENA_BMSK 0x400000 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_ENA_SHFT 0x16 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_BMSK 0x200000 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_SHFT 0x15 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_ENA_BMSK 0x100000 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_ENA_SHFT 0x14 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_ENA_BMSK 0x80000 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_ENA_SHFT 0x13 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_ENA_BMSK 0x40000 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_ENA_SHFT 0x12 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_BMSK 0x20000 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_SHFT 0x11 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_BMSK 0x10000 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_SHFT 0x10 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_BMSK 0x8000 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_SHFT 0xf +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_TME_GPLL0_CLK_SRC_ENA_BMSK 0x4000 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_TME_GPLL0_CLK_SRC_ENA_SHFT 0xe +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_TME_GPLL0_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_TME_GPLL0_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_BMSK 0x2000 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_SHFT 0xd +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_ENA_BMSK 0x1000 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_ENA_SHFT 0xc +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_QMIP_PCIE_AHB_CLK_ENA_BMSK 0x800 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_QMIP_PCIE_AHB_CLK_ENA_SHFT 0xb +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_QMIP_PCIE_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_QMIP_PCIE_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_BMSK 0x400 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_SHFT 0xa +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_BMSK 0x100 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_SHFT 0x8 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_BMSK 0x40 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_SHFT 0x6 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_BMSK 0x20 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_SHFT 0x5 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_BMSK 0x10 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_SHFT 0x4 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_BMSK 0x8 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_SHFT 0x3 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_BMSK 0x4 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_SHFT 0x2 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_BMSK 0x2 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_SHFT 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_BMSK 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_SHFT 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004b004) +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004b004) +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004b004) +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_RMSK 0xfffffd7f +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_ADDR, HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_RMSK) +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_ADDR, m) +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_ADDR,v) +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_IN) +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_SLEEP_ENA_BMSK 0x80000000 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_SLEEP_ENA_SHFT 0x1f +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_BMSK 0x40000000 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_SHFT 0x1e +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_BMSK 0x20000000 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_SHFT 0x1d +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_BMSK 0x10000000 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_SHFT 0x1c +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_BMSK 0x8000000 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_SHFT 0x1b +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_BMSK 0x4000000 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_SHFT 0x1a +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK 0x2000000 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT 0x19 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_AUX_CLK_SLEEP_ENA_BMSK 0x1000000 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_AUX_CLK_SLEEP_ENA_SHFT 0x18 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_AUX_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_AUX_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_SLEEP_ENA_BMSK 0x800000 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_SLEEP_ENA_SHFT 0x17 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_SLEEP_ENA_BMSK 0x400000 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_SLEEP_ENA_SHFT 0x16 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_BMSK 0x200000 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_SHFT 0x15 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_SLEEP_ENA_BMSK 0x100000 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_SLEEP_ENA_SHFT 0x14 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_SLEEP_ENA_BMSK 0x80000 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_SLEEP_ENA_SHFT 0x13 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_SLEEP_ENA_BMSK 0x40000 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_SLEEP_ENA_SHFT 0x12 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK 0x20000 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT 0x11 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK 0x10000 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT 0x10 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_BMSK 0x8000 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_SHFT 0xf +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_TME_GPLL0_CLK_SRC_SLEEP_ENA_BMSK 0x4000 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_TME_GPLL0_CLK_SRC_SLEEP_ENA_SHFT 0xe +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_TME_GPLL0_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_TME_GPLL0_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_BMSK 0x2000 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_SHFT 0xd +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_SLEEP_ENA_BMSK 0x1000 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_SLEEP_ENA_SHFT 0xc +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_QMIP_PCIE_AHB_CLK_SLEEP_ENA_BMSK 0x800 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_QMIP_PCIE_AHB_CLK_SLEEP_ENA_SHFT 0xb +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_QMIP_PCIE_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_QMIP_PCIE_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_BMSK 0x400 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_SHFT 0xa +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_BMSK 0x100 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_SHFT 0x8 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_BMSK 0x40 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_SHFT 0x6 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_BMSK 0x20 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_SHFT 0x5 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_BMSK 0x10 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_SHFT 0x4 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_BMSK 0x8 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_SHFT 0x3 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_BMSK 0x4 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_SHFT 0x2 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_BMSK 0x2 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_SHFT 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_BMSK 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_SHFT 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004b008) +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004b008) +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004b008) +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_RMSK 0xffffffff +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_ATTR 0x3 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_IN \ + in_dword_masked(HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_ADDR, HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_RMSK) +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_INM(m) \ + in_dword_masked(HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_ADDR, m) +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_OUT(v) \ + out_dword(HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_ADDR,v) +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_ADDR,m,v,HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_IN) +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_ENA_BMSK 0x80000000 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_ENA_SHFT 0x1f +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_ENA_BMSK 0x40000000 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_ENA_SHFT 0x1e +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_ENA_BMSK 0x20000000 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_ENA_SHFT 0x1d +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_ENA_BMSK 0x10000000 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_ENA_SHFT 0x1c +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_BMSK 0x8000000 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_SHFT 0x1b +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_BMSK 0x4000000 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_SHFT 0x1a +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_BMSK 0x2000000 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_SHFT 0x19 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_BMSK 0x1000000 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_SHFT 0x18 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_BMSK 0x800000 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_SHFT 0x17 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_BMSK 0x400000 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_SHFT 0x16 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_BMSK 0x200000 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_SHFT 0x15 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_BMSK 0x100000 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_SHFT 0x14 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_BMSK 0x80000 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_SHFT 0x13 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_BMSK 0x40000 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_SHFT 0x12 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S7_CLK_ENA_BMSK 0x20000 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S7_CLK_ENA_SHFT 0x11 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S7_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S7_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S6_CLK_ENA_BMSK 0x10000 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S6_CLK_ENA_SHFT 0x10 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S6_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S6_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S5_CLK_ENA_BMSK 0x8000 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S5_CLK_ENA_SHFT 0xf +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S5_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S5_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S4_CLK_ENA_BMSK 0x4000 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S4_CLK_ENA_SHFT 0xe +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S4_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S4_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S3_CLK_ENA_BMSK 0x2000 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S3_CLK_ENA_SHFT 0xd +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S3_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S3_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S2_CLK_ENA_BMSK 0x1000 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S2_CLK_ENA_SHFT 0xc +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S2_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S2_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S1_CLK_ENA_BMSK 0x800 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S1_CLK_ENA_SHFT 0xb +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S1_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S1_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S0_CLK_ENA_BMSK 0x400 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S0_CLK_ENA_SHFT 0xa +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S0_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S0_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_ENA_BMSK 0x200 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_ENA_SHFT 0x9 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_ENA_BMSK 0x100 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_ENA_SHFT 0x8 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_ENA_BMSK 0x80 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_ENA_SHFT 0x7 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_ENA_BMSK 0x40 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_ENA_SHFT 0x6 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_BMSK 0x20 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_SHFT 0x5 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_BMSK 0x10 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_SHFT 0x4 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_BMSK 0x8 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_SHFT 0x3 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_BMSK 0x4 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_SHFT 0x2 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_BMSK 0x2 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_SHFT 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_BMSK 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_SHFT 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004b00c) +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004b00c) +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004b00c) +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_RMSK 0xffffffff +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_ATTR 0x3 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_IN \ + in_dword_masked(HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_ADDR, HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_RMSK) +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_INM(m) \ + in_dword_masked(HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_ADDR, m) +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_OUT(v) \ + out_dword(HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_ADDR,v) +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_ADDR,m,v,HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_IN) +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_SLEEP_ENA_BMSK 0x80000000 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_SLEEP_ENA_SHFT 0x1f +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_SLEEP_ENA_BMSK 0x40000000 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_SLEEP_ENA_SHFT 0x1e +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_SLEEP_ENA_BMSK 0x20000000 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_SLEEP_ENA_SHFT 0x1d +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_SLEEP_ENA_BMSK 0x10000000 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_SLEEP_ENA_SHFT 0x1c +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_BMSK 0x8000000 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_SHFT 0x1b +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_BMSK 0x4000000 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_SHFT 0x1a +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_BMSK 0x2000000 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_SHFT 0x19 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_BMSK 0x1000000 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_SHFT 0x18 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_BMSK 0x800000 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_SHFT 0x17 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_BMSK 0x400000 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_SHFT 0x16 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_BMSK 0x200000 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_SHFT 0x15 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_BMSK 0x100000 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_SHFT 0x14 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_BMSK 0x80000 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_SHFT 0x13 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_BMSK 0x40000 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_SHFT 0x12 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S7_CLK_SLEEP_ENA_BMSK 0x20000 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S7_CLK_SLEEP_ENA_SHFT 0x11 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S7_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S7_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S6_CLK_SLEEP_ENA_BMSK 0x10000 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S6_CLK_SLEEP_ENA_SHFT 0x10 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S6_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S6_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S5_CLK_SLEEP_ENA_BMSK 0x8000 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S5_CLK_SLEEP_ENA_SHFT 0xf +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S5_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S5_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S4_CLK_SLEEP_ENA_BMSK 0x4000 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S4_CLK_SLEEP_ENA_SHFT 0xe +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S4_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S4_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S3_CLK_SLEEP_ENA_BMSK 0x2000 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S3_CLK_SLEEP_ENA_SHFT 0xd +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S3_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S3_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S2_CLK_SLEEP_ENA_BMSK 0x1000 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S2_CLK_SLEEP_ENA_SHFT 0xc +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S2_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S2_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S1_CLK_SLEEP_ENA_BMSK 0x800 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S1_CLK_SLEEP_ENA_SHFT 0xb +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S1_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S1_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S0_CLK_SLEEP_ENA_BMSK 0x400 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S0_CLK_SLEEP_ENA_SHFT 0xa +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S0_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S0_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_SLEEP_ENA_BMSK 0x200 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_SLEEP_ENA_SHFT 0x9 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_SLEEP_ENA_BMSK 0x100 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_SLEEP_ENA_SHFT 0x8 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_SLEEP_ENA_BMSK 0x80 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_SLEEP_ENA_SHFT 0x7 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_SLEEP_ENA_BMSK 0x40 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_SLEEP_ENA_SHFT 0x6 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK 0x20 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT 0x5 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_BMSK 0x10 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_SHFT 0x4 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_BMSK 0x8 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_SHFT 0x3 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_BMSK 0x4 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_SHFT 0x2 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_BMSK 0x2 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_SHFT 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_BMSK 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_SHFT 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004b010) +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004b010) +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004b010) +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_RMSK 0x7ffff +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_ATTR 0x3 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_IN \ + in_dword_masked(HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_ADDR, HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_RMSK) +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_INM(m) \ + in_dword_masked(HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_ADDR, m) +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_OUT(v) \ + out_dword(HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_ADDR,v) +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_ADDR,m,v,HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_IN) +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_ENA_BMSK 0x40000 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_ENA_SHFT 0x12 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_ENA_BMSK 0x20000 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_ENA_SHFT 0x11 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_ENA_BMSK 0x10000 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_ENA_SHFT 0x10 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S9_CLK_ENA_BMSK 0x8000 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S9_CLK_ENA_SHFT 0xf +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S9_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S9_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S8_CLK_ENA_BMSK 0x4000 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S8_CLK_ENA_SHFT 0xe +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S8_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S8_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_ENA_BMSK 0x2000 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_ENA_SHFT 0xd +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_ENA_BMSK 0x1000 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_ENA_SHFT 0xc +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_ENA_BMSK 0x800 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_ENA_SHFT 0xb +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_ENA_BMSK 0x400 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_ENA_SHFT 0xa +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_BMSK 0x200 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_SHFT 0x9 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_BMSK 0x100 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_SHFT 0x8 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_BMSK 0x80 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_SHFT 0x7 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_BMSK 0x40 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_SHFT 0x6 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_BMSK 0x20 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_SHFT 0x5 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_BMSK 0x10 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_SHFT 0x4 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_BMSK 0x8 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_SHFT 0x3 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_BMSK 0x4 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_SHFT 0x2 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_BMSK 0x2 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_SHFT 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_BMSK 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_SHFT 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004b014) +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004b014) +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004b014) +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_RMSK 0x7ffff +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_ATTR 0x3 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_IN \ + in_dword_masked(HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_ADDR, HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_RMSK) +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_INM(m) \ + in_dword_masked(HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_ADDR, m) +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_OUT(v) \ + out_dword(HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_ADDR,v) +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_ADDR,m,v,HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_IN) +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_SLEEP_ENA_BMSK 0x40000 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_SLEEP_ENA_SHFT 0x12 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_SLEEP_ENA_BMSK 0x20000 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_SLEEP_ENA_SHFT 0x11 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_SLEEP_ENA_BMSK 0x10000 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_SLEEP_ENA_SHFT 0x10 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S9_CLK_SLEEP_ENA_BMSK 0x8000 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S9_CLK_SLEEP_ENA_SHFT 0xf +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S9_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S9_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S8_CLK_SLEEP_ENA_BMSK 0x4000 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S8_CLK_SLEEP_ENA_SHFT 0xe +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S8_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S8_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_SLEEP_ENA_BMSK 0x2000 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_SLEEP_ENA_SHFT 0xd +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_SLEEP_ENA_BMSK 0x1000 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_SLEEP_ENA_SHFT 0xc +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_SLEEP_ENA_BMSK 0x800 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_SLEEP_ENA_SHFT 0xb +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_SLEEP_ENA_BMSK 0x400 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_SLEEP_ENA_SHFT 0xa +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_BMSK 0x200 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_SHFT 0x9 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_BMSK 0x100 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_SHFT 0x8 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_BMSK 0x80 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_SHFT 0x7 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_BMSK 0x40 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_SHFT 0x6 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_BMSK 0x20 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_SHFT 0x5 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_BMSK 0x10 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_SHFT 0x4 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_BMSK 0x8 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_SHFT 0x3 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_BMSK 0x4 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_SHFT 0x2 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_BMSK 0x2 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_SHFT 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_BMSK 0x1 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_SHFT 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004b018) +#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004b018) +#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004b018) +#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_ADDR, HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_RMSK) +#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_ADDR, m) +#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_ADDR,v) +#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_IN) +#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004b01c) +#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004b01c) +#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004b01c) +#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_ADDR, HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_RMSK) +#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_ADDR, m) +#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_ADDR,v) +#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_IN) +#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00047000) +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00047000) +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00047000) +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_RMSK 0xfffffd7f +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_ADDR, HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_RMSK) +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_ADDR, m) +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_ADDR,v) +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_IN) +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_ENA_BMSK 0x80000000 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_ENA_SHFT 0x1f +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_BMSK 0x40000000 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_SHFT 0x1e +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_BMSK 0x20000000 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_SHFT 0x1d +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_BMSK 0x10000000 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_SHFT 0x1c +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_BMSK 0x8000000 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_SHFT 0x1b +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_BMSK 0x4000000 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_SHFT 0x1a +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_BMSK 0x2000000 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_SHFT 0x19 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_AUX_CLK_ENA_BMSK 0x1000000 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_AUX_CLK_ENA_SHFT 0x18 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_AUX_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_AUX_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_ENA_BMSK 0x800000 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_ENA_SHFT 0x17 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_ENA_BMSK 0x400000 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_ENA_SHFT 0x16 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_BMSK 0x200000 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_SHFT 0x15 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_ENA_BMSK 0x100000 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_ENA_SHFT 0x14 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_ENA_BMSK 0x80000 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_ENA_SHFT 0x13 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_ENA_BMSK 0x40000 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_ENA_SHFT 0x12 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_BMSK 0x20000 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_SHFT 0x11 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_BMSK 0x10000 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_SHFT 0x10 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_BMSK 0x8000 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_SHFT 0xf +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_TME_GPLL0_CLK_SRC_ENA_BMSK 0x4000 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_TME_GPLL0_CLK_SRC_ENA_SHFT 0xe +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_TME_GPLL0_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_TME_GPLL0_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_BMSK 0x2000 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_SHFT 0xd +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_ENA_BMSK 0x1000 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_ENA_SHFT 0xc +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_QMIP_PCIE_AHB_CLK_ENA_BMSK 0x800 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_QMIP_PCIE_AHB_CLK_ENA_SHFT 0xb +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_QMIP_PCIE_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_QMIP_PCIE_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_BMSK 0x400 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_SHFT 0xa +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_BMSK 0x100 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_SHFT 0x8 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_BMSK 0x40 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_SHFT 0x6 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_BMSK 0x20 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_SHFT 0x5 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_BMSK 0x10 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_SHFT 0x4 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_BMSK 0x8 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_SHFT 0x3 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_BMSK 0x4 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_SHFT 0x2 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_BMSK 0x2 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_SHFT 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_BMSK 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_SHFT 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00047004) +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00047004) +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00047004) +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_RMSK 0xfffffd7f +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_ADDR, HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_RMSK) +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_ADDR, m) +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_ADDR,v) +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_IN) +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_SLEEP_ENA_BMSK 0x80000000 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_SLEEP_ENA_SHFT 0x1f +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_BMSK 0x40000000 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_SHFT 0x1e +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_BMSK 0x20000000 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_SHFT 0x1d +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_BMSK 0x10000000 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_SHFT 0x1c +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_BMSK 0x8000000 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_SHFT 0x1b +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_BMSK 0x4000000 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_SHFT 0x1a +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK 0x2000000 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT 0x19 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_AUX_CLK_SLEEP_ENA_BMSK 0x1000000 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_AUX_CLK_SLEEP_ENA_SHFT 0x18 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_AUX_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_AUX_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_SLEEP_ENA_BMSK 0x800000 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_SLEEP_ENA_SHFT 0x17 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_SLEEP_ENA_BMSK 0x400000 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_SLEEP_ENA_SHFT 0x16 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_BMSK 0x200000 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_SHFT 0x15 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_SLEEP_ENA_BMSK 0x100000 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_SLEEP_ENA_SHFT 0x14 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_SLEEP_ENA_BMSK 0x80000 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_SLEEP_ENA_SHFT 0x13 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_SLEEP_ENA_BMSK 0x40000 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_SLEEP_ENA_SHFT 0x12 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK 0x20000 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT 0x11 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK 0x10000 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT 0x10 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_BMSK 0x8000 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_SHFT 0xf +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_TME_GPLL0_CLK_SRC_SLEEP_ENA_BMSK 0x4000 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_TME_GPLL0_CLK_SRC_SLEEP_ENA_SHFT 0xe +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_TME_GPLL0_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_TME_GPLL0_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_BMSK 0x2000 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_SHFT 0xd +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_SLEEP_ENA_BMSK 0x1000 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_SLEEP_ENA_SHFT 0xc +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_QMIP_PCIE_AHB_CLK_SLEEP_ENA_BMSK 0x800 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_QMIP_PCIE_AHB_CLK_SLEEP_ENA_SHFT 0xb +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_QMIP_PCIE_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_QMIP_PCIE_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_BMSK 0x400 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_SHFT 0xa +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_BMSK 0x100 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_SHFT 0x8 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_BMSK 0x40 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_SHFT 0x6 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_BMSK 0x20 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_SHFT 0x5 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_BMSK 0x10 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_SHFT 0x4 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_BMSK 0x8 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_SHFT 0x3 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_BMSK 0x4 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_SHFT 0x2 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_BMSK 0x2 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_SHFT 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_BMSK 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_SHFT 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00047008) +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00047008) +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00047008) +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_RMSK 0xffffffff +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_ATTR 0x3 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_IN \ + in_dword_masked(HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_ADDR, HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_RMSK) +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_INM(m) \ + in_dword_masked(HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_ADDR, m) +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_OUT(v) \ + out_dword(HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_ADDR,v) +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_ADDR,m,v,HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_IN) +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_ENA_BMSK 0x80000000 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_ENA_SHFT 0x1f +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_ENA_BMSK 0x40000000 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_ENA_SHFT 0x1e +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_ENA_BMSK 0x20000000 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_ENA_SHFT 0x1d +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_ENA_BMSK 0x10000000 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_ENA_SHFT 0x1c +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_BMSK 0x8000000 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_SHFT 0x1b +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_BMSK 0x4000000 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_SHFT 0x1a +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_BMSK 0x2000000 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_SHFT 0x19 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_BMSK 0x1000000 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_SHFT 0x18 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_BMSK 0x800000 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_SHFT 0x17 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_BMSK 0x400000 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_SHFT 0x16 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_BMSK 0x200000 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_SHFT 0x15 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_BMSK 0x100000 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_SHFT 0x14 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_BMSK 0x80000 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_SHFT 0x13 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_BMSK 0x40000 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_SHFT 0x12 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S7_CLK_ENA_BMSK 0x20000 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S7_CLK_ENA_SHFT 0x11 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S7_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S7_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S6_CLK_ENA_BMSK 0x10000 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S6_CLK_ENA_SHFT 0x10 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S6_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S6_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S5_CLK_ENA_BMSK 0x8000 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S5_CLK_ENA_SHFT 0xf +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S5_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S5_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S4_CLK_ENA_BMSK 0x4000 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S4_CLK_ENA_SHFT 0xe +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S4_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S4_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S3_CLK_ENA_BMSK 0x2000 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S3_CLK_ENA_SHFT 0xd +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S3_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S3_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S2_CLK_ENA_BMSK 0x1000 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S2_CLK_ENA_SHFT 0xc +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S2_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S2_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S1_CLK_ENA_BMSK 0x800 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S1_CLK_ENA_SHFT 0xb +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S1_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S1_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S0_CLK_ENA_BMSK 0x400 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S0_CLK_ENA_SHFT 0xa +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S0_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S0_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_ENA_BMSK 0x200 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_ENA_SHFT 0x9 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_ENA_BMSK 0x100 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_ENA_SHFT 0x8 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_ENA_BMSK 0x80 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_ENA_SHFT 0x7 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_ENA_BMSK 0x40 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_ENA_SHFT 0x6 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_BMSK 0x20 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_SHFT 0x5 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_BMSK 0x10 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_SHFT 0x4 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_BMSK 0x8 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_SHFT 0x3 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_BMSK 0x4 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_SHFT 0x2 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_BMSK 0x2 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_SHFT 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_BMSK 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_SHFT 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004700c) +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004700c) +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004700c) +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_RMSK 0xffffffff +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_ATTR 0x3 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_IN \ + in_dword_masked(HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_ADDR, HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_RMSK) +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_INM(m) \ + in_dword_masked(HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_ADDR, m) +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_OUT(v) \ + out_dword(HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_ADDR,v) +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_ADDR,m,v,HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_IN) +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_SLEEP_ENA_BMSK 0x80000000 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_SLEEP_ENA_SHFT 0x1f +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_SLEEP_ENA_BMSK 0x40000000 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_SLEEP_ENA_SHFT 0x1e +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_SLEEP_ENA_BMSK 0x20000000 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_SLEEP_ENA_SHFT 0x1d +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_SLEEP_ENA_BMSK 0x10000000 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_SLEEP_ENA_SHFT 0x1c +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_BMSK 0x8000000 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_SHFT 0x1b +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_BMSK 0x4000000 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_SHFT 0x1a +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_BMSK 0x2000000 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_SHFT 0x19 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_BMSK 0x1000000 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_SHFT 0x18 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_BMSK 0x800000 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_SHFT 0x17 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_BMSK 0x400000 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_SHFT 0x16 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_BMSK 0x200000 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_SHFT 0x15 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_BMSK 0x100000 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_SHFT 0x14 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_BMSK 0x80000 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_SHFT 0x13 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_BMSK 0x40000 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_SHFT 0x12 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S7_CLK_SLEEP_ENA_BMSK 0x20000 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S7_CLK_SLEEP_ENA_SHFT 0x11 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S7_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S7_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S6_CLK_SLEEP_ENA_BMSK 0x10000 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S6_CLK_SLEEP_ENA_SHFT 0x10 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S6_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S6_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S5_CLK_SLEEP_ENA_BMSK 0x8000 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S5_CLK_SLEEP_ENA_SHFT 0xf +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S5_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S5_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S4_CLK_SLEEP_ENA_BMSK 0x4000 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S4_CLK_SLEEP_ENA_SHFT 0xe +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S4_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S4_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S3_CLK_SLEEP_ENA_BMSK 0x2000 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S3_CLK_SLEEP_ENA_SHFT 0xd +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S3_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S3_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S2_CLK_SLEEP_ENA_BMSK 0x1000 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S2_CLK_SLEEP_ENA_SHFT 0xc +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S2_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S2_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S1_CLK_SLEEP_ENA_BMSK 0x800 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S1_CLK_SLEEP_ENA_SHFT 0xb +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S1_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S1_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S0_CLK_SLEEP_ENA_BMSK 0x400 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S0_CLK_SLEEP_ENA_SHFT 0xa +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S0_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S0_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_SLEEP_ENA_BMSK 0x200 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_SLEEP_ENA_SHFT 0x9 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_SLEEP_ENA_BMSK 0x100 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_SLEEP_ENA_SHFT 0x8 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_SLEEP_ENA_BMSK 0x80 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_SLEEP_ENA_SHFT 0x7 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_SLEEP_ENA_BMSK 0x40 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_SLEEP_ENA_SHFT 0x6 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK 0x20 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT 0x5 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_BMSK 0x10 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_SHFT 0x4 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_BMSK 0x8 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_SHFT 0x3 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_BMSK 0x4 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_SHFT 0x2 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_BMSK 0x2 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_SHFT 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_BMSK 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_SHFT 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00047010) +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00047010) +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00047010) +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_RMSK 0x7ffff +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_ATTR 0x3 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_IN \ + in_dword_masked(HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_ADDR, HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_RMSK) +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_INM(m) \ + in_dword_masked(HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_ADDR, m) +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_OUT(v) \ + out_dword(HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_ADDR,v) +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_ADDR,m,v,HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_IN) +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_ENA_BMSK 0x40000 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_ENA_SHFT 0x12 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_ENA_BMSK 0x20000 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_ENA_SHFT 0x11 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_ENA_BMSK 0x10000 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_ENA_SHFT 0x10 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S9_CLK_ENA_BMSK 0x8000 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S9_CLK_ENA_SHFT 0xf +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S9_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S9_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S8_CLK_ENA_BMSK 0x4000 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S8_CLK_ENA_SHFT 0xe +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S8_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S8_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_ENA_BMSK 0x2000 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_ENA_SHFT 0xd +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_ENA_BMSK 0x1000 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_ENA_SHFT 0xc +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_ENA_BMSK 0x800 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_ENA_SHFT 0xb +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_ENA_BMSK 0x400 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_ENA_SHFT 0xa +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_BMSK 0x200 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_SHFT 0x9 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_BMSK 0x100 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_SHFT 0x8 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_BMSK 0x80 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_SHFT 0x7 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_BMSK 0x40 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_SHFT 0x6 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_BMSK 0x20 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_SHFT 0x5 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_BMSK 0x10 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_SHFT 0x4 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_BMSK 0x8 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_SHFT 0x3 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_BMSK 0x4 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_SHFT 0x2 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_BMSK 0x2 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_SHFT 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_BMSK 0x1 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_SHFT 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00047014) +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00047014) +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00047014) +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_RMSK 0x7ffff +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_ATTR 0x3 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_IN \ + in_dword_masked(HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_ADDR, HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_RMSK) +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_INM(m) \ + in_dword_masked(HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_ADDR, m) +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_OUT(v) \ + out_dword(HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_ADDR,v) +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_ADDR,m,v,HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_IN) +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_SLEEP_ENA_BMSK 0x40000 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_SLEEP_ENA_SHFT 0x12 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_SLEEP_ENA_BMSK 0x20000 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_SLEEP_ENA_SHFT 0x11 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_SLEEP_ENA_BMSK 0x10000 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_SLEEP_ENA_SHFT 0x10 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S9_CLK_SLEEP_ENA_BMSK 0x8000 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S9_CLK_SLEEP_ENA_SHFT 0xf +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S9_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S9_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S8_CLK_SLEEP_ENA_BMSK 0x4000 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S8_CLK_SLEEP_ENA_SHFT 0xe +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S8_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S8_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_SLEEP_ENA_BMSK 0x2000 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_SLEEP_ENA_SHFT 0xd +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_SLEEP_ENA_BMSK 0x1000 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_SLEEP_ENA_SHFT 0xc +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_SLEEP_ENA_BMSK 0x800 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_SLEEP_ENA_SHFT 0xb +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_SLEEP_ENA_BMSK 0x400 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_SLEEP_ENA_SHFT 0xa +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_BMSK 0x200 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_SHFT 0x9 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_BMSK 0x100 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_SHFT 0x8 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_BMSK 0x80 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_SHFT 0x7 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_BMSK 0x40 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_SHFT 0x6 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_BMSK 0x20 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_SHFT 0x5 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_BMSK 0x10 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_SHFT 0x4 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_BMSK 0x8 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_SHFT 0x3 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_BMSK 0x4 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_SHFT 0x2 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_BMSK 0x2 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_SHFT 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_BMSK 0x1 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_SHFT 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00047018) +#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00047018) +#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00047018) +#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_ADDR, HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_RMSK) +#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_ADDR, m) +#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_ADDR,v) +#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_IN) +#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004701c) +#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004701c) +#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004701c) +#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_ADDR, HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_RMSK) +#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_ADDR, m) +#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_ADDR,v) +#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_IN) +#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00025038) +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00025038) +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00025038) +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_RMSK 0xfffffd7f +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_ADDR, HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_RMSK) +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_ADDR, m) +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_ADDR,v) +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_IN) +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_ENA_BMSK 0x80000000 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_ENA_SHFT 0x1f +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_BMSK 0x40000000 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_SHFT 0x1e +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_BMSK 0x20000000 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_SHFT 0x1d +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_BMSK 0x10000000 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_SHFT 0x1c +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_BMSK 0x8000000 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_SHFT 0x1b +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_BMSK 0x4000000 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_SHFT 0x1a +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_BMSK 0x2000000 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_SHFT 0x19 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_AUX_CLK_ENA_BMSK 0x1000000 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_AUX_CLK_ENA_SHFT 0x18 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_AUX_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_AUX_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_ENA_BMSK 0x800000 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_ENA_SHFT 0x17 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_ENA_BMSK 0x400000 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_ENA_SHFT 0x16 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_BMSK 0x200000 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_SHFT 0x15 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_ENA_BMSK 0x100000 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_ENA_SHFT 0x14 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_ENA_BMSK 0x80000 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_ENA_SHFT 0x13 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_ENA_BMSK 0x40000 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_ENA_SHFT 0x12 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_BMSK 0x20000 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_SHFT 0x11 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_BMSK 0x10000 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_SHFT 0x10 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_BMSK 0x8000 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_SHFT 0xf +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_TME_GPLL0_CLK_SRC_ENA_BMSK 0x4000 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_TME_GPLL0_CLK_SRC_ENA_SHFT 0xe +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_TME_GPLL0_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_TME_GPLL0_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_BMSK 0x2000 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_SHFT 0xd +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_ENA_BMSK 0x1000 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_ENA_SHFT 0xc +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_QMIP_PCIE_AHB_CLK_ENA_BMSK 0x800 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_QMIP_PCIE_AHB_CLK_ENA_SHFT 0xb +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_QMIP_PCIE_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_QMIP_PCIE_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_BMSK 0x400 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_SHFT 0xa +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_BMSK 0x100 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_SHFT 0x8 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_BMSK 0x40 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_SHFT 0x6 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_BMSK 0x20 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_SHFT 0x5 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_BMSK 0x10 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_SHFT 0x4 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_BMSK 0x8 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_SHFT 0x3 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_BMSK 0x4 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_SHFT 0x2 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_BMSK 0x2 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_SHFT 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_BMSK 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_SHFT 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002503c) +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002503c) +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002503c) +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_RMSK 0xfffffd7f +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_ADDR, HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_RMSK) +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_ADDR, m) +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_ADDR,v) +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_IN) +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_SLEEP_ENA_BMSK 0x80000000 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_SLEEP_ENA_SHFT 0x1f +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_BMSK 0x40000000 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_SHFT 0x1e +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_BMSK 0x20000000 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_SHFT 0x1d +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_BMSK 0x10000000 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_SHFT 0x1c +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_BMSK 0x8000000 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_SHFT 0x1b +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_BMSK 0x4000000 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_SHFT 0x1a +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK 0x2000000 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT 0x19 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_AUX_CLK_SLEEP_ENA_BMSK 0x1000000 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_AUX_CLK_SLEEP_ENA_SHFT 0x18 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_AUX_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_AUX_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_SLEEP_ENA_BMSK 0x800000 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_SLEEP_ENA_SHFT 0x17 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_SLEEP_ENA_BMSK 0x400000 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_SLEEP_ENA_SHFT 0x16 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_BMSK 0x200000 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_SHFT 0x15 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_SLEEP_ENA_BMSK 0x100000 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_SLEEP_ENA_SHFT 0x14 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_SLEEP_ENA_BMSK 0x80000 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_SLEEP_ENA_SHFT 0x13 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_SLEEP_ENA_BMSK 0x40000 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_SLEEP_ENA_SHFT 0x12 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK 0x20000 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT 0x11 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK 0x10000 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT 0x10 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_BMSK 0x8000 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_SHFT 0xf +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_TME_GPLL0_CLK_SRC_SLEEP_ENA_BMSK 0x4000 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_TME_GPLL0_CLK_SRC_SLEEP_ENA_SHFT 0xe +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_TME_GPLL0_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_TME_GPLL0_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_BMSK 0x2000 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_SHFT 0xd +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_SLEEP_ENA_BMSK 0x1000 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_SLEEP_ENA_SHFT 0xc +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_QMIP_PCIE_AHB_CLK_SLEEP_ENA_BMSK 0x800 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_QMIP_PCIE_AHB_CLK_SLEEP_ENA_SHFT 0xb +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_QMIP_PCIE_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_QMIP_PCIE_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_BMSK 0x400 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_SHFT 0xa +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_BMSK 0x100 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_SHFT 0x8 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_BMSK 0x40 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_SHFT 0x6 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_BMSK 0x20 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_SHFT 0x5 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_BMSK 0x10 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_SHFT 0x4 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_BMSK 0x8 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_SHFT 0x3 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_BMSK 0x4 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_SHFT 0x2 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_BMSK 0x2 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_SHFT 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_BMSK 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_SHFT 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00025040) +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00025040) +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00025040) +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_RMSK 0xffffffff +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_ATTR 0x3 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_IN \ + in_dword_masked(HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_ADDR, HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_RMSK) +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_ADDR, m) +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_OUT(v) \ + out_dword(HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_ADDR,v) +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_ADDR,m,v,HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_IN) +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_ENA_BMSK 0x80000000 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_ENA_SHFT 0x1f +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_ENA_BMSK 0x40000000 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_ENA_SHFT 0x1e +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_ENA_BMSK 0x20000000 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_ENA_SHFT 0x1d +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_ENA_BMSK 0x10000000 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_ENA_SHFT 0x1c +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_BMSK 0x8000000 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_SHFT 0x1b +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_BMSK 0x4000000 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_SHFT 0x1a +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_BMSK 0x2000000 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_SHFT 0x19 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_BMSK 0x1000000 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_SHFT 0x18 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_BMSK 0x800000 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_SHFT 0x17 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_BMSK 0x400000 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_SHFT 0x16 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_BMSK 0x200000 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_SHFT 0x15 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_BMSK 0x100000 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_SHFT 0x14 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_BMSK 0x80000 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_SHFT 0x13 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_BMSK 0x40000 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_SHFT 0x12 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S7_CLK_ENA_BMSK 0x20000 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S7_CLK_ENA_SHFT 0x11 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S7_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S7_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S6_CLK_ENA_BMSK 0x10000 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S6_CLK_ENA_SHFT 0x10 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S6_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S6_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S5_CLK_ENA_BMSK 0x8000 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S5_CLK_ENA_SHFT 0xf +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S5_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S5_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S4_CLK_ENA_BMSK 0x4000 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S4_CLK_ENA_SHFT 0xe +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S4_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S4_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S3_CLK_ENA_BMSK 0x2000 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S3_CLK_ENA_SHFT 0xd +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S3_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S3_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S2_CLK_ENA_BMSK 0x1000 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S2_CLK_ENA_SHFT 0xc +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S2_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S2_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S1_CLK_ENA_BMSK 0x800 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S1_CLK_ENA_SHFT 0xb +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S1_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S1_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S0_CLK_ENA_BMSK 0x400 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S0_CLK_ENA_SHFT 0xa +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S0_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S0_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_ENA_BMSK 0x200 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_ENA_SHFT 0x9 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_ENA_BMSK 0x100 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_ENA_SHFT 0x8 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_ENA_BMSK 0x80 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_ENA_SHFT 0x7 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_ENA_BMSK 0x40 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_ENA_SHFT 0x6 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_BMSK 0x20 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_SHFT 0x5 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_BMSK 0x10 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_SHFT 0x4 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_BMSK 0x8 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_SHFT 0x3 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_BMSK 0x4 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_SHFT 0x2 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_BMSK 0x2 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_SHFT 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_BMSK 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_SHFT 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00025044) +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00025044) +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00025044) +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_RMSK 0xffffffff +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_ATTR 0x3 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_IN \ + in_dword_masked(HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_ADDR, HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_RMSK) +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_ADDR, m) +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_OUT(v) \ + out_dword(HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_ADDR,v) +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_ADDR,m,v,HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_IN) +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_SLEEP_ENA_BMSK 0x80000000 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_SLEEP_ENA_SHFT 0x1f +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_SLEEP_ENA_BMSK 0x40000000 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_SLEEP_ENA_SHFT 0x1e +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_SLEEP_ENA_BMSK 0x20000000 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_SLEEP_ENA_SHFT 0x1d +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_SLEEP_ENA_BMSK 0x10000000 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_SLEEP_ENA_SHFT 0x1c +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_BMSK 0x8000000 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_SHFT 0x1b +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_BMSK 0x4000000 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_SHFT 0x1a +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_BMSK 0x2000000 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_SHFT 0x19 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_BMSK 0x1000000 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_SHFT 0x18 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_BMSK 0x800000 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_SHFT 0x17 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_BMSK 0x400000 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_SHFT 0x16 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_BMSK 0x200000 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_SHFT 0x15 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_BMSK 0x100000 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_SHFT 0x14 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_BMSK 0x80000 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_SHFT 0x13 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_BMSK 0x40000 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_SHFT 0x12 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S7_CLK_SLEEP_ENA_BMSK 0x20000 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S7_CLK_SLEEP_ENA_SHFT 0x11 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S7_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S7_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S6_CLK_SLEEP_ENA_BMSK 0x10000 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S6_CLK_SLEEP_ENA_SHFT 0x10 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S6_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S6_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S5_CLK_SLEEP_ENA_BMSK 0x8000 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S5_CLK_SLEEP_ENA_SHFT 0xf +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S5_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S5_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S4_CLK_SLEEP_ENA_BMSK 0x4000 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S4_CLK_SLEEP_ENA_SHFT 0xe +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S4_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S4_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S3_CLK_SLEEP_ENA_BMSK 0x2000 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S3_CLK_SLEEP_ENA_SHFT 0xd +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S3_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S3_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S2_CLK_SLEEP_ENA_BMSK 0x1000 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S2_CLK_SLEEP_ENA_SHFT 0xc +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S2_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S2_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S1_CLK_SLEEP_ENA_BMSK 0x800 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S1_CLK_SLEEP_ENA_SHFT 0xb +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S1_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S1_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S0_CLK_SLEEP_ENA_BMSK 0x400 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S0_CLK_SLEEP_ENA_SHFT 0xa +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S0_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S0_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_SLEEP_ENA_BMSK 0x200 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_SLEEP_ENA_SHFT 0x9 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_SLEEP_ENA_BMSK 0x100 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_SLEEP_ENA_SHFT 0x8 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_SLEEP_ENA_BMSK 0x80 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_SLEEP_ENA_SHFT 0x7 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_SLEEP_ENA_BMSK 0x40 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_SLEEP_ENA_SHFT 0x6 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK 0x20 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT 0x5 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_BMSK 0x10 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_SHFT 0x4 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_BMSK 0x8 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_SHFT 0x3 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_BMSK 0x4 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_SHFT 0x2 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_BMSK 0x2 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_SHFT 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_BMSK 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_SHFT 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00025048) +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00025048) +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00025048) +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_RMSK 0x7ffff +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_ATTR 0x3 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_IN \ + in_dword_masked(HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_ADDR, HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_RMSK) +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_ADDR, m) +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_OUT(v) \ + out_dword(HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_ADDR,v) +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_ADDR,m,v,HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_IN) +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_ENA_BMSK 0x40000 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_ENA_SHFT 0x12 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_ENA_BMSK 0x20000 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_ENA_SHFT 0x11 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_ENA_BMSK 0x10000 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_ENA_SHFT 0x10 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S9_CLK_ENA_BMSK 0x8000 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S9_CLK_ENA_SHFT 0xf +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S9_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S9_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S8_CLK_ENA_BMSK 0x4000 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S8_CLK_ENA_SHFT 0xe +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S8_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S8_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_ENA_BMSK 0x2000 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_ENA_SHFT 0xd +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_ENA_BMSK 0x1000 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_ENA_SHFT 0xc +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_ENA_BMSK 0x800 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_ENA_SHFT 0xb +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_ENA_BMSK 0x400 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_ENA_SHFT 0xa +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_BMSK 0x200 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_SHFT 0x9 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_BMSK 0x100 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_SHFT 0x8 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_BMSK 0x80 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_SHFT 0x7 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_BMSK 0x40 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_SHFT 0x6 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_BMSK 0x20 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_SHFT 0x5 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_BMSK 0x10 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_SHFT 0x4 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_BMSK 0x8 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_SHFT 0x3 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_BMSK 0x4 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_SHFT 0x2 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_BMSK 0x2 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_SHFT 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_BMSK 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_SHFT 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002504c) +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002504c) +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002504c) +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_RMSK 0x7ffff +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_ATTR 0x3 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_IN \ + in_dword_masked(HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_ADDR, HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_RMSK) +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_ADDR, m) +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_OUT(v) \ + out_dword(HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_ADDR,v) +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_ADDR,m,v,HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_IN) +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_SLEEP_ENA_BMSK 0x40000 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_SLEEP_ENA_SHFT 0x12 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_SLEEP_ENA_BMSK 0x20000 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_SLEEP_ENA_SHFT 0x11 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_SLEEP_ENA_BMSK 0x10000 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_SLEEP_ENA_SHFT 0x10 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S9_CLK_SLEEP_ENA_BMSK 0x8000 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S9_CLK_SLEEP_ENA_SHFT 0xf +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S9_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S9_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S8_CLK_SLEEP_ENA_BMSK 0x4000 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S8_CLK_SLEEP_ENA_SHFT 0xe +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S8_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S8_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_SLEEP_ENA_BMSK 0x2000 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_SLEEP_ENA_SHFT 0xd +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_SLEEP_ENA_BMSK 0x1000 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_SLEEP_ENA_SHFT 0xc +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_SLEEP_ENA_BMSK 0x800 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_SLEEP_ENA_SHFT 0xb +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_SLEEP_ENA_BMSK 0x400 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_SLEEP_ENA_SHFT 0xa +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_BMSK 0x200 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_SHFT 0x9 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_BMSK 0x100 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_SHFT 0x8 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_BMSK 0x80 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_SHFT 0x7 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_BMSK 0x40 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_SHFT 0x6 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_BMSK 0x20 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_SHFT 0x5 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_BMSK 0x10 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_SHFT 0x4 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_BMSK 0x8 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_SHFT 0x3 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_BMSK 0x4 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_SHFT 0x2 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_BMSK 0x2 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_SHFT 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_BMSK 0x1 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_SHFT 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00025050) +#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00025050) +#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00025050) +#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_ADDR, HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_RMSK) +#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_ADDR, m) +#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_ADDR,v) +#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_IN) +#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00025054) +#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00025054) +#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00025054) +#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_ADDR, HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_RMSK) +#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_ADDR, m) +#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_ADDR,v) +#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_IN) +#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00046000) +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00046000) +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00046000) +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_RMSK 0xfffffd7f +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_ADDR, HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_RMSK) +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_ADDR, m) +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_ADDR,v) +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_IN) +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_ENA_BMSK 0x80000000 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_ENA_SHFT 0x1f +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_BMSK 0x40000000 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_SHFT 0x1e +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_BMSK 0x20000000 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_SHFT 0x1d +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_BMSK 0x10000000 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_SHFT 0x1c +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_BMSK 0x8000000 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_SHFT 0x1b +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_BMSK 0x4000000 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_SHFT 0x1a +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_BMSK 0x2000000 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_SHFT 0x19 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_AUX_CLK_ENA_BMSK 0x1000000 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_AUX_CLK_ENA_SHFT 0x18 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_AUX_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_AUX_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_ENA_BMSK 0x800000 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_ENA_SHFT 0x17 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_ENA_BMSK 0x400000 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_ENA_SHFT 0x16 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_BMSK 0x200000 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_SHFT 0x15 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_ENA_BMSK 0x100000 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_ENA_SHFT 0x14 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_ENA_BMSK 0x80000 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_ENA_SHFT 0x13 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_ENA_BMSK 0x40000 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_ENA_SHFT 0x12 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_BMSK 0x20000 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_SHFT 0x11 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_BMSK 0x10000 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_SHFT 0x10 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_BMSK 0x8000 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_SHFT 0xf +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_TME_GPLL0_CLK_SRC_ENA_BMSK 0x4000 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_TME_GPLL0_CLK_SRC_ENA_SHFT 0xe +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_TME_GPLL0_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_TME_GPLL0_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_BMSK 0x2000 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_SHFT 0xd +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_ENA_BMSK 0x1000 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_ENA_SHFT 0xc +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_QMIP_PCIE_AHB_CLK_ENA_BMSK 0x800 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_QMIP_PCIE_AHB_CLK_ENA_SHFT 0xb +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_QMIP_PCIE_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_QMIP_PCIE_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_BMSK 0x400 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_SHFT 0xa +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_BMSK 0x100 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_SHFT 0x8 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_BMSK 0x40 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_SHFT 0x6 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_BMSK 0x20 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_SHFT 0x5 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_BMSK 0x10 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_SHFT 0x4 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_BMSK 0x8 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_SHFT 0x3 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_BMSK 0x4 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_SHFT 0x2 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_BMSK 0x2 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_SHFT 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_BMSK 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_SHFT 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00046004) +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00046004) +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00046004) +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_RMSK 0xfffffd7f +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_ADDR, HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_RMSK) +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_ADDR, m) +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_ADDR,v) +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_IN) +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_SLEEP_ENA_BMSK 0x80000000 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_SLEEP_ENA_SHFT 0x1f +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_BMSK 0x40000000 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_SHFT 0x1e +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_BMSK 0x20000000 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_SHFT 0x1d +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_BMSK 0x10000000 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_SHFT 0x1c +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_BMSK 0x8000000 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_SHFT 0x1b +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_BMSK 0x4000000 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_SHFT 0x1a +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK 0x2000000 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT 0x19 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_AUX_CLK_SLEEP_ENA_BMSK 0x1000000 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_AUX_CLK_SLEEP_ENA_SHFT 0x18 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_AUX_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_AUX_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_SLEEP_ENA_BMSK 0x800000 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_SLEEP_ENA_SHFT 0x17 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_SLEEP_ENA_BMSK 0x400000 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_SLEEP_ENA_SHFT 0x16 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_BMSK 0x200000 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_SHFT 0x15 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_SLEEP_ENA_BMSK 0x100000 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_SLEEP_ENA_SHFT 0x14 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_SLEEP_ENA_BMSK 0x80000 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_SLEEP_ENA_SHFT 0x13 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_SLEEP_ENA_BMSK 0x40000 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_SLEEP_ENA_SHFT 0x12 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK 0x20000 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT 0x11 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK 0x10000 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT 0x10 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_BMSK 0x8000 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_SHFT 0xf +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_TME_GPLL0_CLK_SRC_SLEEP_ENA_BMSK 0x4000 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_TME_GPLL0_CLK_SRC_SLEEP_ENA_SHFT 0xe +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_TME_GPLL0_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_TME_GPLL0_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_BMSK 0x2000 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_SHFT 0xd +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_SLEEP_ENA_BMSK 0x1000 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_SLEEP_ENA_SHFT 0xc +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_QMIP_PCIE_AHB_CLK_SLEEP_ENA_BMSK 0x800 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_QMIP_PCIE_AHB_CLK_SLEEP_ENA_SHFT 0xb +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_QMIP_PCIE_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_QMIP_PCIE_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_BMSK 0x400 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_SHFT 0xa +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_BMSK 0x100 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_SHFT 0x8 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_BMSK 0x40 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_SHFT 0x6 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_BMSK 0x20 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_SHFT 0x5 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_BMSK 0x10 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_SHFT 0x4 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_BMSK 0x8 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_SHFT 0x3 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_BMSK 0x4 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_SHFT 0x2 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_BMSK 0x2 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_SHFT 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_BMSK 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_SHFT 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00046008) +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00046008) +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00046008) +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_RMSK 0xffffffff +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_ATTR 0x3 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_IN \ + in_dword_masked(HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_ADDR, HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_RMSK) +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_INM(m) \ + in_dword_masked(HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_ADDR, m) +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_OUT(v) \ + out_dword(HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_ADDR,v) +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_ADDR,m,v,HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_IN) +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_ENA_BMSK 0x80000000 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_ENA_SHFT 0x1f +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_ENA_BMSK 0x40000000 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_ENA_SHFT 0x1e +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_ENA_BMSK 0x20000000 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_ENA_SHFT 0x1d +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_ENA_BMSK 0x10000000 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_ENA_SHFT 0x1c +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_BMSK 0x8000000 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_SHFT 0x1b +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_BMSK 0x4000000 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_SHFT 0x1a +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_BMSK 0x2000000 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_SHFT 0x19 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_BMSK 0x1000000 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_SHFT 0x18 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_BMSK 0x800000 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_SHFT 0x17 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_BMSK 0x400000 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_SHFT 0x16 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_BMSK 0x200000 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_SHFT 0x15 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_BMSK 0x100000 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_SHFT 0x14 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_BMSK 0x80000 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_SHFT 0x13 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_BMSK 0x40000 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_SHFT 0x12 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S7_CLK_ENA_BMSK 0x20000 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S7_CLK_ENA_SHFT 0x11 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S7_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S7_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S6_CLK_ENA_BMSK 0x10000 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S6_CLK_ENA_SHFT 0x10 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S6_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S6_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S5_CLK_ENA_BMSK 0x8000 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S5_CLK_ENA_SHFT 0xf +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S5_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S5_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S4_CLK_ENA_BMSK 0x4000 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S4_CLK_ENA_SHFT 0xe +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S4_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S4_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S3_CLK_ENA_BMSK 0x2000 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S3_CLK_ENA_SHFT 0xd +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S3_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S3_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S2_CLK_ENA_BMSK 0x1000 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S2_CLK_ENA_SHFT 0xc +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S2_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S2_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S1_CLK_ENA_BMSK 0x800 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S1_CLK_ENA_SHFT 0xb +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S1_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S1_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S0_CLK_ENA_BMSK 0x400 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S0_CLK_ENA_SHFT 0xa +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S0_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S0_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_ENA_BMSK 0x200 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_ENA_SHFT 0x9 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_ENA_BMSK 0x100 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_ENA_SHFT 0x8 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_ENA_BMSK 0x80 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_ENA_SHFT 0x7 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_ENA_BMSK 0x40 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_ENA_SHFT 0x6 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_BMSK 0x20 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_SHFT 0x5 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_BMSK 0x10 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_SHFT 0x4 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_BMSK 0x8 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_SHFT 0x3 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_BMSK 0x4 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_SHFT 0x2 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_BMSK 0x2 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_SHFT 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_BMSK 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_SHFT 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004600c) +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004600c) +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004600c) +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_RMSK 0xffffffff +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_ATTR 0x3 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_IN \ + in_dword_masked(HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_ADDR, HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_RMSK) +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_INM(m) \ + in_dword_masked(HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_ADDR, m) +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_OUT(v) \ + out_dword(HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_ADDR,v) +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_ADDR,m,v,HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_IN) +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_SLEEP_ENA_BMSK 0x80000000 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_SLEEP_ENA_SHFT 0x1f +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_SLEEP_ENA_BMSK 0x40000000 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_SLEEP_ENA_SHFT 0x1e +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_SLEEP_ENA_BMSK 0x20000000 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_SLEEP_ENA_SHFT 0x1d +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_SLEEP_ENA_BMSK 0x10000000 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_SLEEP_ENA_SHFT 0x1c +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_BMSK 0x8000000 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_SHFT 0x1b +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_BMSK 0x4000000 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_SHFT 0x1a +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_BMSK 0x2000000 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_SHFT 0x19 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_BMSK 0x1000000 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_SHFT 0x18 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_BMSK 0x800000 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_SHFT 0x17 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_BMSK 0x400000 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_SHFT 0x16 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_BMSK 0x200000 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_SHFT 0x15 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_BMSK 0x100000 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_SHFT 0x14 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_BMSK 0x80000 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_SHFT 0x13 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_BMSK 0x40000 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_SHFT 0x12 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S7_CLK_SLEEP_ENA_BMSK 0x20000 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S7_CLK_SLEEP_ENA_SHFT 0x11 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S7_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S7_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S6_CLK_SLEEP_ENA_BMSK 0x10000 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S6_CLK_SLEEP_ENA_SHFT 0x10 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S6_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S6_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S5_CLK_SLEEP_ENA_BMSK 0x8000 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S5_CLK_SLEEP_ENA_SHFT 0xf +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S5_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S5_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S4_CLK_SLEEP_ENA_BMSK 0x4000 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S4_CLK_SLEEP_ENA_SHFT 0xe +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S4_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S4_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S3_CLK_SLEEP_ENA_BMSK 0x2000 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S3_CLK_SLEEP_ENA_SHFT 0xd +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S3_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S3_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S2_CLK_SLEEP_ENA_BMSK 0x1000 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S2_CLK_SLEEP_ENA_SHFT 0xc +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S2_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S2_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S1_CLK_SLEEP_ENA_BMSK 0x800 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S1_CLK_SLEEP_ENA_SHFT 0xb +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S1_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S1_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S0_CLK_SLEEP_ENA_BMSK 0x400 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S0_CLK_SLEEP_ENA_SHFT 0xa +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S0_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S0_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_SLEEP_ENA_BMSK 0x200 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_SLEEP_ENA_SHFT 0x9 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_SLEEP_ENA_BMSK 0x100 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_SLEEP_ENA_SHFT 0x8 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_SLEEP_ENA_BMSK 0x80 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_SLEEP_ENA_SHFT 0x7 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_SLEEP_ENA_BMSK 0x40 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_SLEEP_ENA_SHFT 0x6 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK 0x20 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT 0x5 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_BMSK 0x10 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_SHFT 0x4 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_BMSK 0x8 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_SHFT 0x3 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_BMSK 0x4 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_SHFT 0x2 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_BMSK 0x2 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_SHFT 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_BMSK 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_SHFT 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00046010) +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00046010) +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00046010) +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_RMSK 0x7ffff +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_ATTR 0x3 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_IN \ + in_dword_masked(HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_ADDR, HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_RMSK) +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_INM(m) \ + in_dword_masked(HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_ADDR, m) +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_OUT(v) \ + out_dword(HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_ADDR,v) +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_ADDR,m,v,HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_IN) +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_ENA_BMSK 0x40000 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_ENA_SHFT 0x12 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_ENA_BMSK 0x20000 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_ENA_SHFT 0x11 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_ENA_BMSK 0x10000 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_ENA_SHFT 0x10 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S9_CLK_ENA_BMSK 0x8000 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S9_CLK_ENA_SHFT 0xf +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S9_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S9_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S8_CLK_ENA_BMSK 0x4000 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S8_CLK_ENA_SHFT 0xe +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S8_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S8_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_ENA_BMSK 0x2000 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_ENA_SHFT 0xd +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_ENA_BMSK 0x1000 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_ENA_SHFT 0xc +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_ENA_BMSK 0x800 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_ENA_SHFT 0xb +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_ENA_BMSK 0x400 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_ENA_SHFT 0xa +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_BMSK 0x200 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_SHFT 0x9 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_BMSK 0x100 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_SHFT 0x8 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_BMSK 0x80 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_SHFT 0x7 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_BMSK 0x40 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_SHFT 0x6 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_BMSK 0x20 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_SHFT 0x5 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_BMSK 0x10 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_SHFT 0x4 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_BMSK 0x8 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_SHFT 0x3 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_BMSK 0x4 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_SHFT 0x2 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_BMSK 0x2 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_SHFT 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_BMSK 0x1 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_SHFT 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00046014) +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00046014) +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00046014) +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_RMSK 0x7ffff +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_ATTR 0x3 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_IN \ + in_dword_masked(HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_ADDR, HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_RMSK) +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_INM(m) \ + in_dword_masked(HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_ADDR, m) +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_OUT(v) \ + out_dword(HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_ADDR,v) +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_ADDR,m,v,HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_IN) +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_SLEEP_ENA_BMSK 0x40000 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_SLEEP_ENA_SHFT 0x12 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_SLEEP_ENA_BMSK 0x20000 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_SLEEP_ENA_SHFT 0x11 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_SLEEP_ENA_BMSK 0x10000 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_SLEEP_ENA_SHFT 0x10 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S9_CLK_SLEEP_ENA_BMSK 0x8000 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S9_CLK_SLEEP_ENA_SHFT 0xf +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S9_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S9_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S8_CLK_SLEEP_ENA_BMSK 0x4000 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S8_CLK_SLEEP_ENA_SHFT 0xe +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S8_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S8_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_SLEEP_ENA_BMSK 0x2000 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_SLEEP_ENA_SHFT 0xd +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_SLEEP_ENA_BMSK 0x1000 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_SLEEP_ENA_SHFT 0xc +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_SLEEP_ENA_BMSK 0x800 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_SLEEP_ENA_SHFT 0xb +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_SLEEP_ENA_BMSK 0x400 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_SLEEP_ENA_SHFT 0xa +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_BMSK 0x200 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_SHFT 0x9 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_BMSK 0x100 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_SHFT 0x8 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_BMSK 0x80 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_SHFT 0x7 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_BMSK 0x40 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_SHFT 0x6 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_BMSK 0x20 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_SHFT 0x5 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_BMSK 0x10 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_SHFT 0x4 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_BMSK 0x8 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_SHFT 0x3 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_BMSK 0x4 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_SHFT 0x2 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_BMSK 0x2 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_SHFT 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_BMSK 0x1 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_SHFT 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00046018) +#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00046018) +#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00046018) +#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_ADDR, HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_RMSK) +#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_ADDR, m) +#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_ADDR,v) +#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_IN) +#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004601c) +#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004601c) +#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004601c) +#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_ADDR, HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_RMSK) +#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_ADDR, m) +#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_ADDR,v) +#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_IN) +#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004a000) +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004a000) +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004a000) +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_RMSK 0xfffffd7f +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_ADDR, HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_RMSK) +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_ADDR, m) +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_ADDR,v) +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_IN) +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_ENA_BMSK 0x80000000 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_ENA_SHFT 0x1f +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_BMSK 0x40000000 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_SHFT 0x1e +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_BMSK 0x20000000 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_SHFT 0x1d +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_BMSK 0x10000000 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_SHFT 0x1c +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_BMSK 0x8000000 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_SHFT 0x1b +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_BMSK 0x4000000 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_SHFT 0x1a +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_BMSK 0x2000000 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_SHFT 0x19 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_AUX_CLK_ENA_BMSK 0x1000000 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_AUX_CLK_ENA_SHFT 0x18 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_AUX_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_AUX_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_ENA_BMSK 0x800000 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_ENA_SHFT 0x17 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_ENA_BMSK 0x400000 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_ENA_SHFT 0x16 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_BMSK 0x200000 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_SHFT 0x15 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_ENA_BMSK 0x100000 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_ENA_SHFT 0x14 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_ENA_BMSK 0x80000 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_ENA_SHFT 0x13 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_ENA_BMSK 0x40000 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_ENA_SHFT 0x12 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_BMSK 0x20000 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_SHFT 0x11 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_BMSK 0x10000 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_SHFT 0x10 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_BMSK 0x8000 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_SHFT 0xf +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_TME_GPLL0_CLK_SRC_ENA_BMSK 0x4000 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_TME_GPLL0_CLK_SRC_ENA_SHFT 0xe +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_TME_GPLL0_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_TME_GPLL0_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_BMSK 0x2000 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_SHFT 0xd +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_ENA_BMSK 0x1000 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_ENA_SHFT 0xc +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_QMIP_PCIE_AHB_CLK_ENA_BMSK 0x800 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_QMIP_PCIE_AHB_CLK_ENA_SHFT 0xb +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_QMIP_PCIE_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_QMIP_PCIE_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_BMSK 0x400 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_SHFT 0xa +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_BMSK 0x100 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_SHFT 0x8 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_BMSK 0x40 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_SHFT 0x6 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_BMSK 0x20 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_SHFT 0x5 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_BMSK 0x10 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_SHFT 0x4 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_BMSK 0x8 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_SHFT 0x3 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_BMSK 0x4 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_SHFT 0x2 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_BMSK 0x2 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_SHFT 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_BMSK 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_SHFT 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004a004) +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004a004) +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004a004) +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_RMSK 0xfffffd7f +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_ADDR, HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_RMSK) +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_ADDR, m) +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_ADDR,v) +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_IN) +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_SLEEP_ENA_BMSK 0x80000000 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_SLEEP_ENA_SHFT 0x1f +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_BMSK 0x40000000 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_SHFT 0x1e +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_BMSK 0x20000000 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_SHFT 0x1d +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_BMSK 0x10000000 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_SHFT 0x1c +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_BMSK 0x8000000 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_SHFT 0x1b +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_BMSK 0x4000000 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_SHFT 0x1a +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK 0x2000000 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT 0x19 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_AUX_CLK_SLEEP_ENA_BMSK 0x1000000 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_AUX_CLK_SLEEP_ENA_SHFT 0x18 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_AUX_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_AUX_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_SLEEP_ENA_BMSK 0x800000 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_SLEEP_ENA_SHFT 0x17 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_SLEEP_ENA_BMSK 0x400000 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_SLEEP_ENA_SHFT 0x16 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_BMSK 0x200000 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_SHFT 0x15 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_SLEEP_ENA_BMSK 0x100000 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_SLEEP_ENA_SHFT 0x14 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_SLEEP_ENA_BMSK 0x80000 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_SLEEP_ENA_SHFT 0x13 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_SLEEP_ENA_BMSK 0x40000 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_SLEEP_ENA_SHFT 0x12 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK 0x20000 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT 0x11 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK 0x10000 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT 0x10 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_BMSK 0x8000 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_SHFT 0xf +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_TME_GPLL0_CLK_SRC_SLEEP_ENA_BMSK 0x4000 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_TME_GPLL0_CLK_SRC_SLEEP_ENA_SHFT 0xe +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_TME_GPLL0_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_TME_GPLL0_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_BMSK 0x2000 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_SHFT 0xd +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_SLEEP_ENA_BMSK 0x1000 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_SLEEP_ENA_SHFT 0xc +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_QMIP_PCIE_AHB_CLK_SLEEP_ENA_BMSK 0x800 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_QMIP_PCIE_AHB_CLK_SLEEP_ENA_SHFT 0xb +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_QMIP_PCIE_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_QMIP_PCIE_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_BMSK 0x400 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_SHFT 0xa +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_BMSK 0x100 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_SHFT 0x8 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_BMSK 0x40 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_SHFT 0x6 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_BMSK 0x20 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_SHFT 0x5 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_BMSK 0x10 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_SHFT 0x4 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_BMSK 0x8 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_SHFT 0x3 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_BMSK 0x4 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_SHFT 0x2 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_BMSK 0x2 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_SHFT 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_BMSK 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_SHFT 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004a008) +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004a008) +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004a008) +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_RMSK 0xffffffff +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_ATTR 0x3 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_IN \ + in_dword_masked(HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_ADDR, HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_RMSK) +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_INM(m) \ + in_dword_masked(HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_ADDR, m) +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_OUT(v) \ + out_dword(HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_ADDR,v) +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_ADDR,m,v,HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_IN) +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_ENA_BMSK 0x80000000 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_ENA_SHFT 0x1f +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_ENA_BMSK 0x40000000 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_ENA_SHFT 0x1e +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_ENA_BMSK 0x20000000 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_ENA_SHFT 0x1d +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_ENA_BMSK 0x10000000 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_ENA_SHFT 0x1c +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_BMSK 0x8000000 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_SHFT 0x1b +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_BMSK 0x4000000 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_SHFT 0x1a +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_BMSK 0x2000000 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_SHFT 0x19 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_BMSK 0x1000000 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_SHFT 0x18 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_BMSK 0x800000 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_SHFT 0x17 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_BMSK 0x400000 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_SHFT 0x16 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_BMSK 0x200000 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_SHFT 0x15 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_BMSK 0x100000 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_SHFT 0x14 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_BMSK 0x80000 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_SHFT 0x13 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_BMSK 0x40000 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_SHFT 0x12 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S7_CLK_ENA_BMSK 0x20000 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S7_CLK_ENA_SHFT 0x11 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S7_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S7_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S6_CLK_ENA_BMSK 0x10000 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S6_CLK_ENA_SHFT 0x10 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S6_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S6_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S5_CLK_ENA_BMSK 0x8000 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S5_CLK_ENA_SHFT 0xf +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S5_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S5_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S4_CLK_ENA_BMSK 0x4000 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S4_CLK_ENA_SHFT 0xe +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S4_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S4_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S3_CLK_ENA_BMSK 0x2000 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S3_CLK_ENA_SHFT 0xd +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S3_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S3_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S2_CLK_ENA_BMSK 0x1000 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S2_CLK_ENA_SHFT 0xc +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S2_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S2_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S1_CLK_ENA_BMSK 0x800 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S1_CLK_ENA_SHFT 0xb +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S1_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S1_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S0_CLK_ENA_BMSK 0x400 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S0_CLK_ENA_SHFT 0xa +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S0_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S0_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_ENA_BMSK 0x200 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_ENA_SHFT 0x9 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_ENA_BMSK 0x100 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_ENA_SHFT 0x8 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_ENA_BMSK 0x80 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_ENA_SHFT 0x7 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_ENA_BMSK 0x40 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_ENA_SHFT 0x6 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_BMSK 0x20 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_SHFT 0x5 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_BMSK 0x10 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_SHFT 0x4 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_BMSK 0x8 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_SHFT 0x3 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_BMSK 0x4 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_SHFT 0x2 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_BMSK 0x2 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_SHFT 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_BMSK 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_SHFT 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004a00c) +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004a00c) +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004a00c) +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_RMSK 0xffffffff +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_ATTR 0x3 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_IN \ + in_dword_masked(HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_ADDR, HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_RMSK) +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_INM(m) \ + in_dword_masked(HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_ADDR, m) +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_OUT(v) \ + out_dword(HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_ADDR,v) +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_ADDR,m,v,HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_IN) +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_SLEEP_ENA_BMSK 0x80000000 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_SLEEP_ENA_SHFT 0x1f +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_SLEEP_ENA_BMSK 0x40000000 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_SLEEP_ENA_SHFT 0x1e +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_SLEEP_ENA_BMSK 0x20000000 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_SLEEP_ENA_SHFT 0x1d +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_SLEEP_ENA_BMSK 0x10000000 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_SLEEP_ENA_SHFT 0x1c +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_BMSK 0x8000000 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_SHFT 0x1b +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_BMSK 0x4000000 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_SHFT 0x1a +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_BMSK 0x2000000 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_SHFT 0x19 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_BMSK 0x1000000 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_SHFT 0x18 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_BMSK 0x800000 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_SHFT 0x17 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_BMSK 0x400000 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_SHFT 0x16 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_BMSK 0x200000 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_SHFT 0x15 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_BMSK 0x100000 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_SHFT 0x14 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_BMSK 0x80000 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_SHFT 0x13 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_BMSK 0x40000 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_SHFT 0x12 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S7_CLK_SLEEP_ENA_BMSK 0x20000 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S7_CLK_SLEEP_ENA_SHFT 0x11 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S7_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S7_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S6_CLK_SLEEP_ENA_BMSK 0x10000 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S6_CLK_SLEEP_ENA_SHFT 0x10 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S6_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S6_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S5_CLK_SLEEP_ENA_BMSK 0x8000 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S5_CLK_SLEEP_ENA_SHFT 0xf +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S5_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S5_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S4_CLK_SLEEP_ENA_BMSK 0x4000 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S4_CLK_SLEEP_ENA_SHFT 0xe +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S4_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S4_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S3_CLK_SLEEP_ENA_BMSK 0x2000 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S3_CLK_SLEEP_ENA_SHFT 0xd +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S3_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S3_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S2_CLK_SLEEP_ENA_BMSK 0x1000 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S2_CLK_SLEEP_ENA_SHFT 0xc +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S2_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S2_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S1_CLK_SLEEP_ENA_BMSK 0x800 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S1_CLK_SLEEP_ENA_SHFT 0xb +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S1_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S1_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S0_CLK_SLEEP_ENA_BMSK 0x400 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S0_CLK_SLEEP_ENA_SHFT 0xa +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S0_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S0_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_SLEEP_ENA_BMSK 0x200 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_SLEEP_ENA_SHFT 0x9 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_SLEEP_ENA_BMSK 0x100 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_SLEEP_ENA_SHFT 0x8 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_SLEEP_ENA_BMSK 0x80 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_SLEEP_ENA_SHFT 0x7 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_SLEEP_ENA_BMSK 0x40 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_SLEEP_ENA_SHFT 0x6 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK 0x20 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT 0x5 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_BMSK 0x10 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_SHFT 0x4 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_BMSK 0x8 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_SHFT 0x3 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_BMSK 0x4 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_SHFT 0x2 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_BMSK 0x2 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_SHFT 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_BMSK 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_SHFT 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004a010) +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004a010) +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004a010) +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_RMSK 0x7ffff +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_ATTR 0x3 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_IN \ + in_dword_masked(HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_ADDR, HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_RMSK) +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_INM(m) \ + in_dword_masked(HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_ADDR, m) +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_OUT(v) \ + out_dword(HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_ADDR,v) +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_ADDR,m,v,HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_IN) +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_ENA_BMSK 0x40000 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_ENA_SHFT 0x12 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_ENA_BMSK 0x20000 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_ENA_SHFT 0x11 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_ENA_BMSK 0x10000 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_ENA_SHFT 0x10 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S9_CLK_ENA_BMSK 0x8000 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S9_CLK_ENA_SHFT 0xf +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S9_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S9_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S8_CLK_ENA_BMSK 0x4000 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S8_CLK_ENA_SHFT 0xe +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S8_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S8_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_ENA_BMSK 0x2000 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_ENA_SHFT 0xd +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_ENA_BMSK 0x1000 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_ENA_SHFT 0xc +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_ENA_BMSK 0x800 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_ENA_SHFT 0xb +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_ENA_BMSK 0x400 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_ENA_SHFT 0xa +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_BMSK 0x200 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_SHFT 0x9 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_BMSK 0x100 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_SHFT 0x8 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_BMSK 0x80 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_SHFT 0x7 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_BMSK 0x40 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_SHFT 0x6 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_BMSK 0x20 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_SHFT 0x5 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_BMSK 0x10 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_SHFT 0x4 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_BMSK 0x8 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_SHFT 0x3 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_BMSK 0x4 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_SHFT 0x2 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_BMSK 0x2 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_SHFT 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_BMSK 0x1 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_SHFT 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004a014) +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004a014) +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004a014) +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_RMSK 0x7ffff +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_ATTR 0x3 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_IN \ + in_dword_masked(HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_ADDR, HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_RMSK) +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_INM(m) \ + in_dword_masked(HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_ADDR, m) +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_OUT(v) \ + out_dword(HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_ADDR,v) +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_ADDR,m,v,HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_IN) +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_SLEEP_ENA_BMSK 0x40000 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_SLEEP_ENA_SHFT 0x12 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_SLEEP_ENA_BMSK 0x20000 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_SLEEP_ENA_SHFT 0x11 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_SLEEP_ENA_BMSK 0x10000 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_SLEEP_ENA_SHFT 0x10 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S9_CLK_SLEEP_ENA_BMSK 0x8000 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S9_CLK_SLEEP_ENA_SHFT 0xf +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S9_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S9_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S8_CLK_SLEEP_ENA_BMSK 0x4000 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S8_CLK_SLEEP_ENA_SHFT 0xe +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S8_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S8_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_SLEEP_ENA_BMSK 0x2000 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_SLEEP_ENA_SHFT 0xd +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_SLEEP_ENA_BMSK 0x1000 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_SLEEP_ENA_SHFT 0xc +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_SLEEP_ENA_BMSK 0x800 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_SLEEP_ENA_SHFT 0xb +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_SLEEP_ENA_BMSK 0x400 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_SLEEP_ENA_SHFT 0xa +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_BMSK 0x200 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_SHFT 0x9 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_BMSK 0x100 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_SHFT 0x8 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_BMSK 0x80 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_SHFT 0x7 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_BMSK 0x40 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_SHFT 0x6 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_BMSK 0x20 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_SHFT 0x5 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_BMSK 0x10 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_SHFT 0x4 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_BMSK 0x8 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_SHFT 0x3 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_BMSK 0x4 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_SHFT 0x2 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_BMSK 0x2 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_SHFT 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_BMSK 0x1 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_SHFT 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004a018) +#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004a018) +#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004a018) +#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_ADDR, HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_RMSK) +#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_ADDR, m) +#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_ADDR,v) +#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_IN) +#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004a01c) +#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004a01c) +#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004a01c) +#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_ADDR, HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_RMSK) +#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_ADDR, m) +#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_ADDR,v) +#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_IN) +#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00059038) +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00059038) +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00059038) +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_RMSK 0xfffffd7f +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_ADDR, HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_RMSK) +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_ADDR, m) +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_ADDR,v) +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_IN) +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_ENA_BMSK 0x80000000 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_ENA_SHFT 0x1f +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_BMSK 0x40000000 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_SHFT 0x1e +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_BMSK 0x20000000 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_SHFT 0x1d +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_BMSK 0x10000000 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_SHFT 0x1c +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_BMSK 0x8000000 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_SHFT 0x1b +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_BMSK 0x4000000 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_SHFT 0x1a +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_BMSK 0x2000000 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_SHFT 0x19 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_AUX_CLK_ENA_BMSK 0x1000000 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_AUX_CLK_ENA_SHFT 0x18 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_AUX_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_AUX_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_ENA_BMSK 0x800000 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_ENA_SHFT 0x17 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_ENA_BMSK 0x400000 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_ENA_SHFT 0x16 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_BMSK 0x200000 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_SHFT 0x15 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_ENA_BMSK 0x100000 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_ENA_SHFT 0x14 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_ENA_BMSK 0x80000 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_ENA_SHFT 0x13 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_ENA_BMSK 0x40000 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_ENA_SHFT 0x12 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_BMSK 0x20000 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_SHFT 0x11 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_BMSK 0x10000 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_SHFT 0x10 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_BMSK 0x8000 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_SHFT 0xf +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_TME_GPLL0_CLK_SRC_ENA_BMSK 0x4000 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_TME_GPLL0_CLK_SRC_ENA_SHFT 0xe +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_TME_GPLL0_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_TME_GPLL0_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_BMSK 0x2000 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_SHFT 0xd +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_ENA_BMSK 0x1000 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_ENA_SHFT 0xc +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_QMIP_PCIE_AHB_CLK_ENA_BMSK 0x800 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_QMIP_PCIE_AHB_CLK_ENA_SHFT 0xb +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_QMIP_PCIE_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_QMIP_PCIE_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_BMSK 0x400 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_SHFT 0xa +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_BMSK 0x100 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_SHFT 0x8 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_TLMM_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_BMSK 0x40 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_SHFT 0x6 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_BMSK 0x20 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_SHFT 0x5 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_BMSK 0x10 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_SHFT 0x4 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_BMSK 0x8 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_SHFT 0x3 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_BMSK 0x4 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_SHFT 0x2 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_BMSK 0x2 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_SHFT 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_BMSK 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_SHFT 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005903c) +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005903c) +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005903c) +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_RMSK 0xfffffd7f +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_ADDR, HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_RMSK) +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_ADDR, m) +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_ADDR,v) +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_IN) +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_SLEEP_ENA_BMSK 0x80000000 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_SLEEP_ENA_SHFT 0x1f +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_DDRSS_GPLL0_MAIN_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_BMSK 0x40000000 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_SHFT 0x1e +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_BMSK 0x20000000 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_SHFT 0x1d +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_BMSK 0x10000000 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_SHFT 0x1c +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_BMSK 0x8000000 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_SHFT 0x1b +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_BMSK 0x4000000 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_SHFT 0x1a +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK 0x2000000 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT 0x19 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_AUX_CLK_SLEEP_ENA_BMSK 0x1000000 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_AUX_CLK_SLEEP_ENA_SHFT 0x18 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_AUX_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_AUX_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_SLEEP_ENA_BMSK 0x800000 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_SLEEP_ENA_SHFT 0x17 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PHY_RCHNG_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_SLEEP_ENA_BMSK 0x400000 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_SLEEP_ENA_SHFT 0x16 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_PCIE_0_PHY_RCHNG_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_BMSK 0x200000 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_SHFT 0x15 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_SLEEP_ENA_BMSK 0x100000 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_SLEEP_ENA_SHFT 0x14 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_CFG_NOC_PCIE_ANOC_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_SLEEP_ENA_BMSK 0x80000 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_SLEEP_ENA_SHFT 0x13 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_DDRSS_PCIE_SF_QTB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_SLEEP_ENA_BMSK 0x40000 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_SLEEP_ENA_SHFT 0x12 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_TCU_ANOC_PCIE_QTB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK 0x20000 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT 0x11 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK 0x10000 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT 0x10 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_BMSK 0x8000 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_SHFT 0xf +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_TME_GPLL0_CLK_SRC_SLEEP_ENA_BMSK 0x4000 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_TME_GPLL0_CLK_SRC_SLEEP_ENA_SHFT 0xe +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_TME_GPLL0_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_TME_GPLL0_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_BMSK 0x2000 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_SHFT 0xd +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_SLEEP_ENA_BMSK 0x1000 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_SLEEP_ENA_SHFT 0xc +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_AGGRE_NOC_PCIE_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_QMIP_PCIE_AHB_CLK_SLEEP_ENA_BMSK 0x800 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_QMIP_PCIE_AHB_CLK_SLEEP_ENA_SHFT 0xb +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_QMIP_PCIE_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_QMIP_PCIE_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_BMSK 0x400 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_SHFT 0xa +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_BMSK 0x100 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_SHFT 0x8 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_TLMM_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_BMSK 0x40 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_SHFT 0x6 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_BMSK 0x20 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_SHFT 0x5 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_BMSK 0x10 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_SHFT 0x4 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_BMSK 0x8 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_SHFT 0x3 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_BMSK 0x4 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_SHFT 0x2 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_BMSK 0x2 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_SHFT 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_BMSK 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_SHFT 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00059040) +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00059040) +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00059040) +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_RMSK 0xffffffff +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_ATTR 0x3 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_IN \ + in_dword_masked(HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_ADDR, HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_RMSK) +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_INM(m) \ + in_dword_masked(HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_ADDR, m) +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_OUT(v) \ + out_dword(HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_ADDR,v) +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_ADDR,m,v,HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_IN) +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_ENA_BMSK 0x80000000 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_ENA_SHFT 0x1f +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_ENA_BMSK 0x40000000 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_ENA_SHFT 0x1e +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_ENA_BMSK 0x20000000 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_ENA_SHFT 0x1d +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_ENA_BMSK 0x10000000 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_ENA_SHFT 0x1c +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_BMSK 0x8000000 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_SHFT 0x1b +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_BMSK 0x4000000 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_SHFT 0x1a +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_BMSK 0x2000000 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_SHFT 0x19 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_BMSK 0x1000000 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_SHFT 0x18 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_BMSK 0x800000 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_SHFT 0x17 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_BMSK 0x400000 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_SHFT 0x16 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_BMSK 0x200000 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_SHFT 0x15 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_BMSK 0x100000 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_SHFT 0x14 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_BMSK 0x80000 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_SHFT 0x13 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_BMSK 0x40000 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_SHFT 0x12 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S7_CLK_ENA_BMSK 0x20000 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S7_CLK_ENA_SHFT 0x11 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S7_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S7_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S6_CLK_ENA_BMSK 0x10000 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S6_CLK_ENA_SHFT 0x10 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S6_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S6_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S5_CLK_ENA_BMSK 0x8000 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S5_CLK_ENA_SHFT 0xf +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S5_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S5_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S4_CLK_ENA_BMSK 0x4000 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S4_CLK_ENA_SHFT 0xe +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S4_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S4_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S3_CLK_ENA_BMSK 0x2000 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S3_CLK_ENA_SHFT 0xd +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S3_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S3_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S2_CLK_ENA_BMSK 0x1000 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S2_CLK_ENA_SHFT 0xc +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S2_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S2_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S1_CLK_ENA_BMSK 0x800 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S1_CLK_ENA_SHFT 0xb +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S1_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S1_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S0_CLK_ENA_BMSK 0x400 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S0_CLK_ENA_SHFT 0xa +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S0_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S0_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_ENA_BMSK 0x200 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_ENA_SHFT 0x9 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_ENA_BMSK 0x100 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_ENA_SHFT 0x8 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_ENA_BMSK 0x80 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_ENA_SHFT 0x7 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_ENA_BMSK 0x40 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_ENA_SHFT 0x6 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_BMSK 0x20 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_SHFT 0x5 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_BMSK 0x10 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_SHFT 0x4 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_BMSK 0x8 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_SHFT 0x3 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_BMSK 0x4 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_SHFT 0x2 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_BMSK 0x2 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_SHFT 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_BMSK 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_SHFT 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00059044) +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00059044) +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00059044) +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_RMSK 0xffffffff +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_ATTR 0x3 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_IN \ + in_dword_masked(HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_ADDR, HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_RMSK) +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_INM(m) \ + in_dword_masked(HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_ADDR, m) +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_OUT(v) \ + out_dword(HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_ADDR,v) +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_ADDR,m,v,HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_IN) +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_SLEEP_ENA_BMSK 0x80000000 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_SLEEP_ENA_SHFT 0x1f +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_ANOC_PCIE_PWRCTL_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_SLEEP_ENA_BMSK 0x40000000 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_SLEEP_ENA_SHFT 0x1e +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QMIP_AGGRE_NOC_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_SLEEP_ENA_BMSK 0x20000000 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_SLEEP_ENA_SHFT 0x1d +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_NOC_PCIE_NORTH_DCD_XO_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_SLEEP_ENA_BMSK 0x10000000 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_SLEEP_ENA_SHFT 0x1c +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S6_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_BMSK 0x8000000 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_SHFT 0x1b +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_BMSK 0x4000000 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_SHFT 0x1a +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_BMSK 0x2000000 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_SHFT 0x19 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_BMSK 0x1000000 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_SHFT 0x18 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_BMSK 0x800000 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_SHFT 0x17 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_BMSK 0x400000 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_SHFT 0x16 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_BMSK 0x200000 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_SHFT 0x15 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_BMSK 0x100000 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_SHFT 0x14 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_BMSK 0x80000 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_SHFT 0x13 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_BMSK 0x40000 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_SHFT 0x12 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S7_CLK_SLEEP_ENA_BMSK 0x20000 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S7_CLK_SLEEP_ENA_SHFT 0x11 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S7_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S7_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S6_CLK_SLEEP_ENA_BMSK 0x10000 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S6_CLK_SLEEP_ENA_SHFT 0x10 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S6_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S6_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S5_CLK_SLEEP_ENA_BMSK 0x8000 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S5_CLK_SLEEP_ENA_SHFT 0xf +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S5_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S5_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S4_CLK_SLEEP_ENA_BMSK 0x4000 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S4_CLK_SLEEP_ENA_SHFT 0xe +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S4_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S4_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S3_CLK_SLEEP_ENA_BMSK 0x2000 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S3_CLK_SLEEP_ENA_SHFT 0xd +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S3_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S3_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S2_CLK_SLEEP_ENA_BMSK 0x1000 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S2_CLK_SLEEP_ENA_SHFT 0xc +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S2_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S2_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S1_CLK_SLEEP_ENA_BMSK 0x800 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S1_CLK_SLEEP_ENA_SHFT 0xb +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S1_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S1_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S0_CLK_SLEEP_ENA_BMSK 0x400 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S0_CLK_SLEEP_ENA_SHFT 0xa +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S0_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S0_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_SLEEP_ENA_BMSK 0x200 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_SLEEP_ENA_SHFT 0x9 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_AGGRE_NOC_SOUTH_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_SLEEP_ENA_BMSK 0x100 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_SLEEP_ENA_SHFT 0x8 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_CORE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_SLEEP_ENA_BMSK 0x80 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_SLEEP_ENA_SHFT 0x7 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_I2C_S_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_SLEEP_ENA_BMSK 0x40 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_SLEEP_ENA_SHFT 0x6 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_CNOC_PCIE_SF_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK 0x20 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT 0x5 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_BMSK 0x10 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_SHFT 0x4 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_BMSK 0x8 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_SHFT 0x3 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_BMSK 0x4 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_SHFT 0x2 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_BMSK 0x2 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_SHFT 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_BMSK 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_SHFT 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00059048) +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00059048) +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00059048) +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_RMSK 0x7ffff +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_ATTR 0x3 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_IN \ + in_dword_masked(HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_ADDR, HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_RMSK) +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_INM(m) \ + in_dword_masked(HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_ADDR, m) +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_OUT(v) \ + out_dword(HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_ADDR,v) +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_ADDR,m,v,HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_IN) +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_ENA_BMSK 0x40000 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_ENA_SHFT 0x12 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_ENA_BMSK 0x20000 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_ENA_SHFT 0x11 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_ENA_BMSK 0x10000 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_ENA_SHFT 0x10 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S9_CLK_ENA_BMSK 0x8000 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S9_CLK_ENA_SHFT 0xf +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S9_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S9_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S8_CLK_ENA_BMSK 0x4000 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S8_CLK_ENA_SHFT 0xe +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S8_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_I2C_S8_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_ENA_BMSK 0x2000 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_ENA_SHFT 0xd +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_ENA_BMSK 0x1000 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_ENA_SHFT 0xc +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_ENA_BMSK 0x800 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_ENA_SHFT 0xb +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_ENA_BMSK 0x400 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_ENA_SHFT 0xa +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_BMSK 0x200 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_SHFT 0x9 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_BMSK 0x100 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_SHFT 0x8 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_BMSK 0x80 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_SHFT 0x7 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_BMSK 0x40 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_SHFT 0x6 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_BMSK 0x20 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_SHFT 0x5 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_BMSK 0x10 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_SHFT 0x4 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_BMSK 0x8 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_SHFT 0x3 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_BMSK 0x4 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_SHFT 0x2 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_BMSK 0x2 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_SHFT 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_BMSK 0x1 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_SHFT 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005904c) +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005904c) +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005904c) +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_RMSK 0x7ffff +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_ATTR 0x3 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_IN \ + in_dword_masked(HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_ADDR, HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_RMSK) +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_INM(m) \ + in_dword_masked(HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_ADDR, m) +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_OUT(v) \ + out_dword(HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_ADDR,v) +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_ADDR,m,v,HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_IN) +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_SLEEP_ENA_BMSK 0x40000 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_SLEEP_ENA_SHFT 0x12 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_TME_GPLL0_DIV2_CLK_SRC_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_SLEEP_ENA_BMSK 0x20000 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_SLEEP_ENA_SHFT 0x11 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S7_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_SLEEP_ENA_BMSK 0x10000 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_SLEEP_ENA_SHFT 0x10 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP1_S7_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S9_CLK_SLEEP_ENA_BMSK 0x8000 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S9_CLK_SLEEP_ENA_SHFT 0xf +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S9_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S9_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S8_CLK_SLEEP_ENA_BMSK 0x4000 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S8_CLK_SLEEP_ENA_SHFT 0xe +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S8_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_I2C_S8_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_SLEEP_ENA_BMSK 0x2000 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_SLEEP_ENA_SHFT 0xd +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_QOSGEN_EXTREF_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_SLEEP_ENA_BMSK 0x1000 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_SLEEP_ENA_SHFT 0xc +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_TSCTR_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_SLEEP_ENA_BMSK 0x800 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_SLEEP_ENA_SHFT 0xb +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_ANOC_PCIE_NORTH_AT_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_SLEEP_ENA_BMSK 0x400 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_SLEEP_ENA_SHFT 0xa +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S6_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_BMSK 0x200 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_SHFT 0x9 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_BMSK 0x100 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_SHFT 0x8 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_BMSK 0x80 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_SHFT 0x7 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_BMSK 0x40 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_SHFT 0x6 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_BMSK 0x20 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_SHFT 0x5 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_BMSK 0x10 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_SHFT 0x4 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_BMSK 0x8 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_SHFT 0x3 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_BMSK 0x4 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_SHFT 0x2 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_BMSK 0x2 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_SHFT 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_BMSK 0x1 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_SHFT 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TME_PLL_BRANCH_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00059050) +#define HWIO_GCC_TME_PLL_BRANCH_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00059050) +#define HWIO_GCC_TME_PLL_BRANCH_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00059050) +#define HWIO_GCC_TME_PLL_BRANCH_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_TME_PLL_BRANCH_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_TME_PLL_BRANCH_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_TME_PLL_BRANCH_ENA_VOTE_ADDR, HWIO_GCC_TME_PLL_BRANCH_ENA_VOTE_RMSK) +#define HWIO_GCC_TME_PLL_BRANCH_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_TME_PLL_BRANCH_ENA_VOTE_ADDR, m) +#define HWIO_GCC_TME_PLL_BRANCH_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_TME_PLL_BRANCH_ENA_VOTE_ADDR,v) +#define HWIO_GCC_TME_PLL_BRANCH_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TME_PLL_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_TME_PLL_BRANCH_ENA_VOTE_IN) +#define HWIO_GCC_TME_PLL_BRANCH_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_TME_PLL_BRANCH_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_TME_PLL_BRANCH_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_PLL_BRANCH_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_PLL_BRANCH_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_TME_PLL_BRANCH_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_TME_PLL_BRANCH_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_PLL_BRANCH_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_PLL_BRANCH_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_TME_PLL_BRANCH_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_TME_PLL_BRANCH_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_PLL_BRANCH_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_PLL_BRANCH_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_TME_PLL_BRANCH_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_TME_PLL_BRANCH_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_PLL_BRANCH_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_PLL_BRANCH_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_TME_PLL_BRANCH_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_TME_PLL_BRANCH_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_PLL_BRANCH_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_PLL_BRANCH_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_TME_PLL_BRANCH_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_TME_PLL_BRANCH_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_PLL_BRANCH_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_PLL_BRANCH_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_TME_PLL_BRANCH_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_TME_PLL_BRANCH_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_PLL_BRANCH_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_PLL_BRANCH_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_TME_PLL_BRANCH_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_TME_PLL_BRANCH_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_PLL_BRANCH_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_PLL_BRANCH_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_TME_PLL_BRANCH_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_TME_PLL_BRANCH_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_PLL_BRANCH_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_PLL_BRANCH_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_TME_PLL_BRANCH_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_TME_PLL_BRANCH_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_PLL_BRANCH_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TME_PLL_SLEEP_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00059054) +#define HWIO_GCC_TME_PLL_SLEEP_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00059054) +#define HWIO_GCC_TME_PLL_SLEEP_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00059054) +#define HWIO_GCC_TME_PLL_SLEEP_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_TME_PLL_SLEEP_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_TME_PLL_SLEEP_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_TME_PLL_SLEEP_ENA_VOTE_ADDR, HWIO_GCC_TME_PLL_SLEEP_ENA_VOTE_RMSK) +#define HWIO_GCC_TME_PLL_SLEEP_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_TME_PLL_SLEEP_ENA_VOTE_ADDR, m) +#define HWIO_GCC_TME_PLL_SLEEP_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_TME_PLL_SLEEP_ENA_VOTE_ADDR,v) +#define HWIO_GCC_TME_PLL_SLEEP_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TME_PLL_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_TME_PLL_SLEEP_ENA_VOTE_IN) +#define HWIO_GCC_TME_PLL_SLEEP_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_TME_PLL_SLEEP_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_TME_PLL_SLEEP_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_PLL_SLEEP_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_PLL_SLEEP_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_TME_PLL_SLEEP_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_TME_PLL_SLEEP_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_PLL_SLEEP_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_PLL_SLEEP_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_TME_PLL_SLEEP_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_TME_PLL_SLEEP_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_PLL_SLEEP_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_PLL_SLEEP_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_TME_PLL_SLEEP_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_TME_PLL_SLEEP_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_PLL_SLEEP_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_PLL_SLEEP_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_TME_PLL_SLEEP_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_TME_PLL_SLEEP_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_PLL_SLEEP_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_PLL_SLEEP_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_TME_PLL_SLEEP_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_TME_PLL_SLEEP_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_PLL_SLEEP_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_PLL_SLEEP_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_TME_PLL_SLEEP_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_TME_PLL_SLEEP_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_PLL_SLEEP_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_PLL_SLEEP_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_TME_PLL_SLEEP_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_TME_PLL_SLEEP_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_PLL_SLEEP_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_PLL_SLEEP_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_TME_PLL_SLEEP_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_TME_PLL_SLEEP_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_PLL_SLEEP_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_PLL_SLEEP_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_TME_PLL_SLEEP_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_TME_PLL_SLEEP_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_PLL_SLEEP_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_0_LINK_DOWN_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005c014) +#define HWIO_GCC_PCIE_0_LINK_DOWN_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005c014) +#define HWIO_GCC_PCIE_0_LINK_DOWN_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005c014) +#define HWIO_GCC_PCIE_0_LINK_DOWN_BCR_RMSK 0x1 +#define HWIO_GCC_PCIE_0_LINK_DOWN_BCR_ATTR 0x3 +#define HWIO_GCC_PCIE_0_LINK_DOWN_BCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_0_LINK_DOWN_BCR_ADDR, HWIO_GCC_PCIE_0_LINK_DOWN_BCR_RMSK) +#define HWIO_GCC_PCIE_0_LINK_DOWN_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_0_LINK_DOWN_BCR_ADDR, m) +#define HWIO_GCC_PCIE_0_LINK_DOWN_BCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_0_LINK_DOWN_BCR_ADDR,v) +#define HWIO_GCC_PCIE_0_LINK_DOWN_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_0_LINK_DOWN_BCR_ADDR,m,v,HWIO_GCC_PCIE_0_LINK_DOWN_BCR_IN) +#define HWIO_GCC_PCIE_0_LINK_DOWN_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_PCIE_0_LINK_DOWN_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_PCIE_0_LINK_DOWN_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_LINK_DOWN_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_0_MISC_RESET_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005c018) +#define HWIO_GCC_PCIE_0_MISC_RESET_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005c018) +#define HWIO_GCC_PCIE_0_MISC_RESET_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005c018) +#define HWIO_GCC_PCIE_0_MISC_RESET_RMSK 0xff +#define HWIO_GCC_PCIE_0_MISC_RESET_ATTR 0x3 +#define HWIO_GCC_PCIE_0_MISC_RESET_IN \ + in_dword_masked(HWIO_GCC_PCIE_0_MISC_RESET_ADDR, HWIO_GCC_PCIE_0_MISC_RESET_RMSK) +#define HWIO_GCC_PCIE_0_MISC_RESET_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_0_MISC_RESET_ADDR, m) +#define HWIO_GCC_PCIE_0_MISC_RESET_OUT(v) \ + out_dword(HWIO_GCC_PCIE_0_MISC_RESET_ADDR,v) +#define HWIO_GCC_PCIE_0_MISC_RESET_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_0_MISC_RESET_ADDR,m,v,HWIO_GCC_PCIE_0_MISC_RESET_IN) +#define HWIO_GCC_PCIE_0_MISC_RESET_PCIE_0_SLV_AXI_STICKY_BCR_BLK_ARES_BMSK 0x80 +#define HWIO_GCC_PCIE_0_MISC_RESET_PCIE_0_SLV_AXI_STICKY_BCR_BLK_ARES_SHFT 0x7 +#define HWIO_GCC_PCIE_0_MISC_RESET_PCIE_0_SLV_AXI_STICKY_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_MISC_RESET_PCIE_0_SLV_AXI_STICKY_BCR_BLK_ARES_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_MISC_RESET_PCIE_0_CORE_STICKY_BCR_BLK_ARES_BMSK 0x40 +#define HWIO_GCC_PCIE_0_MISC_RESET_PCIE_0_CORE_STICKY_BCR_BLK_ARES_SHFT 0x6 +#define HWIO_GCC_PCIE_0_MISC_RESET_PCIE_0_CORE_STICKY_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_MISC_RESET_PCIE_0_CORE_STICKY_BCR_BLK_ARES_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_MISC_RESET_PCIE_0_MSTR_AXI_STICKY_BCR_BLK_ARES_BMSK 0x20 +#define HWIO_GCC_PCIE_0_MISC_RESET_PCIE_0_MSTR_AXI_STICKY_BCR_BLK_ARES_SHFT 0x5 +#define HWIO_GCC_PCIE_0_MISC_RESET_PCIE_0_MSTR_AXI_STICKY_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_MISC_RESET_PCIE_0_MSTR_AXI_STICKY_BCR_BLK_ARES_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_MISC_RESET_PCIE_0_PIPE_BCR_BLK_ARES_BMSK 0x10 +#define HWIO_GCC_PCIE_0_MISC_RESET_PCIE_0_PIPE_BCR_BLK_ARES_SHFT 0x4 +#define HWIO_GCC_PCIE_0_MISC_RESET_PCIE_0_PIPE_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_MISC_RESET_PCIE_0_PIPE_BCR_BLK_ARES_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_MISC_RESET_PCIE_0_AUX_BCR_BLK_ARES_BMSK 0x8 +#define HWIO_GCC_PCIE_0_MISC_RESET_PCIE_0_AUX_BCR_BLK_ARES_SHFT 0x3 +#define HWIO_GCC_PCIE_0_MISC_RESET_PCIE_0_AUX_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_MISC_RESET_PCIE_0_AUX_BCR_BLK_ARES_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_MISC_RESET_PCIE_0_CFG_AHB_BCR_BLK_ARES_BMSK 0x4 +#define HWIO_GCC_PCIE_0_MISC_RESET_PCIE_0_CFG_AHB_BCR_BLK_ARES_SHFT 0x2 +#define HWIO_GCC_PCIE_0_MISC_RESET_PCIE_0_CFG_AHB_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_MISC_RESET_PCIE_0_CFG_AHB_BCR_BLK_ARES_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_MISC_RESET_PCIE_0_MSTR_AXI_BCR_BLK_ARES_BMSK 0x2 +#define HWIO_GCC_PCIE_0_MISC_RESET_PCIE_0_MSTR_AXI_BCR_BLK_ARES_SHFT 0x1 +#define HWIO_GCC_PCIE_0_MISC_RESET_PCIE_0_MSTR_AXI_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_MISC_RESET_PCIE_0_MSTR_AXI_BCR_BLK_ARES_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_0_MISC_RESET_PCIE_0_SLV_AXI_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_PCIE_0_MISC_RESET_PCIE_0_SLV_AXI_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_PCIE_0_MISC_RESET_PCIE_0_SLV_AXI_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_MISC_RESET_PCIE_0_SLV_AXI_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_0_PHY_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005c01c) +#define HWIO_GCC_PCIE_0_PHY_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005c01c) +#define HWIO_GCC_PCIE_0_PHY_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005c01c) +#define HWIO_GCC_PCIE_0_PHY_BCR_RMSK 0x1 +#define HWIO_GCC_PCIE_0_PHY_BCR_ATTR 0x3 +#define HWIO_GCC_PCIE_0_PHY_BCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_0_PHY_BCR_ADDR, HWIO_GCC_PCIE_0_PHY_BCR_RMSK) +#define HWIO_GCC_PCIE_0_PHY_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_0_PHY_BCR_ADDR, m) +#define HWIO_GCC_PCIE_0_PHY_BCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_0_PHY_BCR_ADDR,v) +#define HWIO_GCC_PCIE_0_PHY_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_0_PHY_BCR_ADDR,m,v,HWIO_GCC_PCIE_0_PHY_BCR_IN) +#define HWIO_GCC_PCIE_0_PHY_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_PCIE_0_PHY_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_PCIE_0_PHY_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_PHY_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_0_NOCSR_COM_PHY_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005c020) +#define HWIO_GCC_PCIE_0_NOCSR_COM_PHY_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005c020) +#define HWIO_GCC_PCIE_0_NOCSR_COM_PHY_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005c020) +#define HWIO_GCC_PCIE_0_NOCSR_COM_PHY_BCR_RMSK 0x1 +#define HWIO_GCC_PCIE_0_NOCSR_COM_PHY_BCR_ATTR 0x3 +#define HWIO_GCC_PCIE_0_NOCSR_COM_PHY_BCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_0_NOCSR_COM_PHY_BCR_ADDR, HWIO_GCC_PCIE_0_NOCSR_COM_PHY_BCR_RMSK) +#define HWIO_GCC_PCIE_0_NOCSR_COM_PHY_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_0_NOCSR_COM_PHY_BCR_ADDR, m) +#define HWIO_GCC_PCIE_0_NOCSR_COM_PHY_BCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_0_NOCSR_COM_PHY_BCR_ADDR,v) +#define HWIO_GCC_PCIE_0_NOCSR_COM_PHY_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_0_NOCSR_COM_PHY_BCR_ADDR,m,v,HWIO_GCC_PCIE_0_NOCSR_COM_PHY_BCR_IN) +#define HWIO_GCC_PCIE_0_NOCSR_COM_PHY_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_PCIE_0_NOCSR_COM_PHY_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_PCIE_0_NOCSR_COM_PHY_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_NOCSR_COM_PHY_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005c028) +#define HWIO_GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005c028) +#define HWIO_GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005c028) +#define HWIO_GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR_RMSK 0x1 +#define HWIO_GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR_ATTR 0x3 +#define HWIO_GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR_ADDR, HWIO_GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR_RMSK) +#define HWIO_GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR_ADDR, m) +#define HWIO_GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR_ADDR,v) +#define HWIO_GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR_ADDR,m,v,HWIO_GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR_IN) +#define HWIO_GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_PHY_CFG_AHB_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005f00c) +#define HWIO_GCC_PCIE_PHY_CFG_AHB_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005f00c) +#define HWIO_GCC_PCIE_PHY_CFG_AHB_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005f00c) +#define HWIO_GCC_PCIE_PHY_CFG_AHB_BCR_RMSK 0x1 +#define HWIO_GCC_PCIE_PHY_CFG_AHB_BCR_ATTR 0x3 +#define HWIO_GCC_PCIE_PHY_CFG_AHB_BCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_PHY_CFG_AHB_BCR_ADDR, HWIO_GCC_PCIE_PHY_CFG_AHB_BCR_RMSK) +#define HWIO_GCC_PCIE_PHY_CFG_AHB_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_PHY_CFG_AHB_BCR_ADDR, m) +#define HWIO_GCC_PCIE_PHY_CFG_AHB_BCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_PHY_CFG_AHB_BCR_ADDR,v) +#define HWIO_GCC_PCIE_PHY_CFG_AHB_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_PHY_CFG_AHB_BCR_ADDR,m,v,HWIO_GCC_PCIE_PHY_CFG_AHB_BCR_IN) +#define HWIO_GCC_PCIE_PHY_CFG_AHB_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_PCIE_PHY_CFG_AHB_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_PCIE_PHY_CFG_AHB_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_PHY_CFG_AHB_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_PHY_COM_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005f010) +#define HWIO_GCC_PCIE_PHY_COM_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005f010) +#define HWIO_GCC_PCIE_PHY_COM_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005f010) +#define HWIO_GCC_PCIE_PHY_COM_BCR_RMSK 0x1 +#define HWIO_GCC_PCIE_PHY_COM_BCR_ATTR 0x3 +#define HWIO_GCC_PCIE_PHY_COM_BCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_PHY_COM_BCR_ADDR, HWIO_GCC_PCIE_PHY_COM_BCR_RMSK) +#define HWIO_GCC_PCIE_PHY_COM_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_PHY_COM_BCR_ADDR, m) +#define HWIO_GCC_PCIE_PHY_COM_BCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_PHY_COM_BCR_ADDR,v) +#define HWIO_GCC_PCIE_PHY_COM_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_PHY_COM_BCR_ADDR,m,v,HWIO_GCC_PCIE_PHY_COM_BCR_IN) +#define HWIO_GCC_PCIE_PHY_COM_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_PCIE_PHY_COM_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_PCIE_PHY_COM_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_PHY_COM_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_1_LINK_DOWN_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007e014) +#define HWIO_GCC_PCIE_1_LINK_DOWN_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007e014) +#define HWIO_GCC_PCIE_1_LINK_DOWN_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007e014) +#define HWIO_GCC_PCIE_1_LINK_DOWN_BCR_RMSK 0x1 +#define HWIO_GCC_PCIE_1_LINK_DOWN_BCR_ATTR 0x3 +#define HWIO_GCC_PCIE_1_LINK_DOWN_BCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_1_LINK_DOWN_BCR_ADDR, HWIO_GCC_PCIE_1_LINK_DOWN_BCR_RMSK) +#define HWIO_GCC_PCIE_1_LINK_DOWN_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_1_LINK_DOWN_BCR_ADDR, m) +#define HWIO_GCC_PCIE_1_LINK_DOWN_BCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_1_LINK_DOWN_BCR_ADDR,v) +#define HWIO_GCC_PCIE_1_LINK_DOWN_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_1_LINK_DOWN_BCR_ADDR,m,v,HWIO_GCC_PCIE_1_LINK_DOWN_BCR_IN) +#define HWIO_GCC_PCIE_1_LINK_DOWN_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_PCIE_1_LINK_DOWN_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_PCIE_1_LINK_DOWN_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_LINK_DOWN_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_1_MISC_RESET_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007e018) +#define HWIO_GCC_PCIE_1_MISC_RESET_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007e018) +#define HWIO_GCC_PCIE_1_MISC_RESET_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007e018) +#define HWIO_GCC_PCIE_1_MISC_RESET_RMSK 0x1ff +#define HWIO_GCC_PCIE_1_MISC_RESET_ATTR 0x3 +#define HWIO_GCC_PCIE_1_MISC_RESET_IN \ + in_dword_masked(HWIO_GCC_PCIE_1_MISC_RESET_ADDR, HWIO_GCC_PCIE_1_MISC_RESET_RMSK) +#define HWIO_GCC_PCIE_1_MISC_RESET_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_1_MISC_RESET_ADDR, m) +#define HWIO_GCC_PCIE_1_MISC_RESET_OUT(v) \ + out_dword(HWIO_GCC_PCIE_1_MISC_RESET_ADDR,v) +#define HWIO_GCC_PCIE_1_MISC_RESET_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_1_MISC_RESET_ADDR,m,v,HWIO_GCC_PCIE_1_MISC_RESET_IN) +#define HWIO_GCC_PCIE_1_MISC_RESET_PCIE_1_PHY_AUX_BCR_BLK_ARES_BMSK 0x100 +#define HWIO_GCC_PCIE_1_MISC_RESET_PCIE_1_PHY_AUX_BCR_BLK_ARES_SHFT 0x8 +#define HWIO_GCC_PCIE_1_MISC_RESET_PCIE_1_PHY_AUX_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_MISC_RESET_PCIE_1_PHY_AUX_BCR_BLK_ARES_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_MISC_RESET_PCIE_1_SLV_AXI_STICKY_BCR_BLK_ARES_BMSK 0x80 +#define HWIO_GCC_PCIE_1_MISC_RESET_PCIE_1_SLV_AXI_STICKY_BCR_BLK_ARES_SHFT 0x7 +#define HWIO_GCC_PCIE_1_MISC_RESET_PCIE_1_SLV_AXI_STICKY_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_MISC_RESET_PCIE_1_SLV_AXI_STICKY_BCR_BLK_ARES_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_MISC_RESET_PCIE_1_CORE_STICKY_BCR_BLK_ARES_BMSK 0x40 +#define HWIO_GCC_PCIE_1_MISC_RESET_PCIE_1_CORE_STICKY_BCR_BLK_ARES_SHFT 0x6 +#define HWIO_GCC_PCIE_1_MISC_RESET_PCIE_1_CORE_STICKY_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_MISC_RESET_PCIE_1_CORE_STICKY_BCR_BLK_ARES_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_MISC_RESET_PCIE_1_MSTR_AXI_STICKY_BCR_BLK_ARES_BMSK 0x20 +#define HWIO_GCC_PCIE_1_MISC_RESET_PCIE_1_MSTR_AXI_STICKY_BCR_BLK_ARES_SHFT 0x5 +#define HWIO_GCC_PCIE_1_MISC_RESET_PCIE_1_MSTR_AXI_STICKY_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_MISC_RESET_PCIE_1_MSTR_AXI_STICKY_BCR_BLK_ARES_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_MISC_RESET_PCIE_1_PIPE_BCR_BLK_ARES_BMSK 0x10 +#define HWIO_GCC_PCIE_1_MISC_RESET_PCIE_1_PIPE_BCR_BLK_ARES_SHFT 0x4 +#define HWIO_GCC_PCIE_1_MISC_RESET_PCIE_1_PIPE_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_MISC_RESET_PCIE_1_PIPE_BCR_BLK_ARES_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_MISC_RESET_PCIE_1_AUX_BCR_BLK_ARES_BMSK 0x8 +#define HWIO_GCC_PCIE_1_MISC_RESET_PCIE_1_AUX_BCR_BLK_ARES_SHFT 0x3 +#define HWIO_GCC_PCIE_1_MISC_RESET_PCIE_1_AUX_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_MISC_RESET_PCIE_1_AUX_BCR_BLK_ARES_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_MISC_RESET_PCIE_1_CFG_AHB_BCR_BLK_ARES_BMSK 0x4 +#define HWIO_GCC_PCIE_1_MISC_RESET_PCIE_1_CFG_AHB_BCR_BLK_ARES_SHFT 0x2 +#define HWIO_GCC_PCIE_1_MISC_RESET_PCIE_1_CFG_AHB_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_MISC_RESET_PCIE_1_CFG_AHB_BCR_BLK_ARES_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_MISC_RESET_PCIE_1_MSTR_AXI_BCR_BLK_ARES_BMSK 0x2 +#define HWIO_GCC_PCIE_1_MISC_RESET_PCIE_1_MSTR_AXI_BCR_BLK_ARES_SHFT 0x1 +#define HWIO_GCC_PCIE_1_MISC_RESET_PCIE_1_MSTR_AXI_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_MISC_RESET_PCIE_1_MSTR_AXI_BCR_BLK_ARES_ENABLE_FVAL 0x1 +#define HWIO_GCC_PCIE_1_MISC_RESET_PCIE_1_SLV_AXI_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_PCIE_1_MISC_RESET_PCIE_1_SLV_AXI_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_PCIE_1_MISC_RESET_PCIE_1_SLV_AXI_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_MISC_RESET_PCIE_1_SLV_AXI_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_1_PHY_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007e01c) +#define HWIO_GCC_PCIE_1_PHY_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007e01c) +#define HWIO_GCC_PCIE_1_PHY_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007e01c) +#define HWIO_GCC_PCIE_1_PHY_BCR_RMSK 0x1 +#define HWIO_GCC_PCIE_1_PHY_BCR_ATTR 0x3 +#define HWIO_GCC_PCIE_1_PHY_BCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_1_PHY_BCR_ADDR, HWIO_GCC_PCIE_1_PHY_BCR_RMSK) +#define HWIO_GCC_PCIE_1_PHY_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_1_PHY_BCR_ADDR, m) +#define HWIO_GCC_PCIE_1_PHY_BCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_1_PHY_BCR_ADDR,v) +#define HWIO_GCC_PCIE_1_PHY_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_1_PHY_BCR_ADDR,m,v,HWIO_GCC_PCIE_1_PHY_BCR_IN) +#define HWIO_GCC_PCIE_1_PHY_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_PCIE_1_PHY_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_PCIE_1_PHY_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_PHY_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_1_NOCSR_COM_PHY_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007e020) +#define HWIO_GCC_PCIE_1_NOCSR_COM_PHY_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007e020) +#define HWIO_GCC_PCIE_1_NOCSR_COM_PHY_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007e020) +#define HWIO_GCC_PCIE_1_NOCSR_COM_PHY_BCR_RMSK 0x1 +#define HWIO_GCC_PCIE_1_NOCSR_COM_PHY_BCR_ATTR 0x3 +#define HWIO_GCC_PCIE_1_NOCSR_COM_PHY_BCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_1_NOCSR_COM_PHY_BCR_ADDR, HWIO_GCC_PCIE_1_NOCSR_COM_PHY_BCR_RMSK) +#define HWIO_GCC_PCIE_1_NOCSR_COM_PHY_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_1_NOCSR_COM_PHY_BCR_ADDR, m) +#define HWIO_GCC_PCIE_1_NOCSR_COM_PHY_BCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_1_NOCSR_COM_PHY_BCR_ADDR,v) +#define HWIO_GCC_PCIE_1_NOCSR_COM_PHY_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_1_NOCSR_COM_PHY_BCR_ADDR,m,v,HWIO_GCC_PCIE_1_NOCSR_COM_PHY_BCR_IN) +#define HWIO_GCC_PCIE_1_NOCSR_COM_PHY_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_PCIE_1_NOCSR_COM_PHY_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_PCIE_1_NOCSR_COM_PHY_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_NOCSR_COM_PHY_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007e024) +#define HWIO_GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007e024) +#define HWIO_GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007e024) +#define HWIO_GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR_RMSK 0x1 +#define HWIO_GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR_ATTR 0x3 +#define HWIO_GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR_IN \ + in_dword_masked(HWIO_GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR_ADDR, HWIO_GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR_RMSK) +#define HWIO_GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR_ADDR, m) +#define HWIO_GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR_OUT(v) \ + out_dword(HWIO_GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR_ADDR,v) +#define HWIO_GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR_ADDR,m,v,HWIO_GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR_IN) +#define HWIO_GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR_BLK_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_LPASS_RESET_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x000370b0) +#define HWIO_GCC_LPASS_RESET_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000370b0) +#define HWIO_GCC_LPASS_RESET_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000370b0) +#define HWIO_GCC_LPASS_RESET_RMSK 0x1 +#define HWIO_GCC_LPASS_RESET_ATTR 0x3 +#define HWIO_GCC_LPASS_RESET_IN \ + in_dword_masked(HWIO_GCC_LPASS_RESET_ADDR, HWIO_GCC_LPASS_RESET_RMSK) +#define HWIO_GCC_LPASS_RESET_INM(m) \ + in_dword_masked(HWIO_GCC_LPASS_RESET_ADDR, m) +#define HWIO_GCC_LPASS_RESET_OUT(v) \ + out_dword(HWIO_GCC_LPASS_RESET_ADDR,v) +#define HWIO_GCC_LPASS_RESET_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_LPASS_RESET_ADDR,m,v,HWIO_GCC_LPASS_RESET_IN) +#define HWIO_GCC_LPASS_RESET_LPASS_ARES_BMSK 0x1 +#define HWIO_GCC_LPASS_RESET_LPASS_ARES_SHFT 0x0 +#define HWIO_GCC_LPASS_RESET_LPASS_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_RESET_LPASS_ARES_ENABLE_FVAL 0x1 + +#define HWIO_GCC_DEBUG_MUX_MUXR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00052024) +#define HWIO_GCC_DEBUG_MUX_MUXR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00052024) +#define HWIO_GCC_DEBUG_MUX_MUXR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00052024) +#define HWIO_GCC_DEBUG_MUX_MUXR_RMSK 0x3ff +#define HWIO_GCC_DEBUG_MUX_MUXR_ATTR 0x3 +#define HWIO_GCC_DEBUG_MUX_MUXR_IN \ + in_dword_masked(HWIO_GCC_DEBUG_MUX_MUXR_ADDR, HWIO_GCC_DEBUG_MUX_MUXR_RMSK) +#define HWIO_GCC_DEBUG_MUX_MUXR_INM(m) \ + in_dword_masked(HWIO_GCC_DEBUG_MUX_MUXR_ADDR, m) +#define HWIO_GCC_DEBUG_MUX_MUXR_OUT(v) \ + out_dword(HWIO_GCC_DEBUG_MUX_MUXR_ADDR,v) +#define HWIO_GCC_DEBUG_MUX_MUXR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DEBUG_MUX_MUXR_ADDR,m,v,HWIO_GCC_DEBUG_MUX_MUXR_IN) +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_BMSK 0x3ff +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_SHFT 0x0 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_BI_TCXO_FVAL 0x1 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_CORE_PI_SLEEP_CLK_FVAL 0x2 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_TIC_CLK_FVAL 0x3 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_AUD_REF_CLK_FVAL 0x4 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_CORE_BI_PLL_TEST_SE_FVAL 0x5 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_JBIST_REF_CLK_FVAL 0x6 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_AOSS_GCC_CB_CLK_FVAL 0x7 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_SYS_NOC_CPUSS_AHB_CLK_FVAL 0x8 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_SYS_NOC_NAV_QX_CLK_FVAL 0x9 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_SYS_NOC_TME_QXM_CLK_FVAL 0xa +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_SYS_NOC_AXI_CLK_FVAL 0xb +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_SYS_NOC_GC_AXI_CLK_FVAL 0xc +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_SYS_NOC_SF_AXI_CLK_FVAL 0xd +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_SYS_NOC_AHB_CFG_CLK_FVAL 0xe +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_SYS_NOC_AT_CLK_FVAL 0xf +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_SYS_NOC_QOSGEN_EXTREF_CLK_FVAL 0x10 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_CNOC_APSS_QH_CLK_FVAL 0x11 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_CNOC_CENTER_QX_CLK_FVAL 0x12 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_CNOC_SF_QX_CLK_FVAL 0x13 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_CNOC_NORTH_QX_CLK_FVAL 0x14 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_CNOC_PERIPH_SOUTH_CLK_FVAL 0x15 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_CNOC_PERIPH_NORTH_CLK_FVAL 0x16 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_CFG_NOC_AHB_CLK_FVAL 0x17 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_CFG_NOC_WEST_AHB_CLK_FVAL 0x18 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_CNOC_PCIE_SF_AXI_CLK_FVAL 0x19 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_CFG_NOC_NORTH_AHB_CLK_FVAL 0x1a +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_CFG_NOC_EAST_AHB_CLK_FVAL 0x1b +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_CFG_NOC_SOUTH_AHB_CLK_FVAL 0x1c +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_CFG_NOC_MMNOC_AHB_CLK_FVAL 0x1d +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_CNOC_QDSS_STM_CLK_FVAL 0x1e +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_CFG_NOC_USB3_PRIM_AXI_CLK_FVAL 0x1f +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_CFG_NOC_LPASS_CLK_FVAL 0x20 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_NOC_WEST_DCD_XO_CLK_FVAL 0x21 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_NOC_EAST_DCD_XO_CLK_FVAL 0x22 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_NOC_NORTH_DCD_XO_CLK_FVAL 0x23 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_NOC_PCIE_NORTH_DCD_XO_CLK_FVAL 0x24 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_NOC_SOUTH_DCD_XO_CLK_FVAL 0x25 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_NOC_CENTER_DCD_XO_CLK_FVAL 0x26 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_CFG_NOC_AH2PHY_XO_CLK_FVAL 0x27 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_NOC_LPASS_DCD_XO_CLK_FVAL 0x28 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_NOC_MMNOC_CNOC_DCD_XO_CLK_FVAL 0x29 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_CNOC_PERIPH_CLK_FVAL 0x2a +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_CONFIG_NOC_AT_CLK_FVAL 0x2b +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_CFG_NOC_PCIE_ANOC_AHB_CLK_FVAL 0x2c +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CLK_FVAL 0x2d +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_AGGRE_NOC_AHB_CLK_FVAL 0x2e +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QMIP_AGGRE_NOC_AHB_CLK_FVAL 0x2f +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_AGGRE_CNOC_PERIPH_NORTH_AHB_CLK_FVAL 0x30 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_AGGRE_CNOC_PERIPH_SOUTH_AHB_CLK_FVAL 0x31 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_AGGRE_NOC_QOSGEN_EXTREF_CLK_FVAL 0x32 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_AGGRE_NOC_CENTER_AXI_CLK_FVAL 0x33 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_AGGRE_NOC_QDSS_BAM_CLK_FVAL 0x34 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_AGGRE_NOC_CENTER_HS_AXI_CLK_FVAL 0x35 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_AGGRE_NOC_WEST_AXI_CLK_FVAL 0x36 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_AGGRE_NOC_WEST_TUNNEL_CLK_FVAL 0x37 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_AGGRE_NOC_EAST_AXI_CLK_FVAL 0x38 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_AGGRE_NOC_EAST_TUNNEL_CLK_FVAL 0x39 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_AGGRE_NOC_SOUTH_HS_AXI_CLK_FVAL 0x3a +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_AGGRE_NOC_SOUTH_TUNNEL_CLK_FVAL 0x3b +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_AGGRE_NOC_NORTH_AXI_CLK_FVAL 0x3c +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_AGGRE_NOC_NORTH_TUNNEL_CLK_FVAL 0x3d +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_AGGRE_NOC_PCIE_AXI_CLK_FVAL 0x3e +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_AGGRE_USB3_PRIM_AXI_CLK_FVAL 0x3f +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_AGGRE_UFS_PHY_AXI_CLK_FVAL 0x40 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_AGGRE_NOC_IPA_CLK_FVAL 0x41 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_ANOC_PCIE_PWRCTL_CLK_FVAL 0x42 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_TIC_CLK_FVAL 0x43 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_TIC_CFG_QX_CLK_FVAL 0x44 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_IMEM_CFG_QX_CLK_FVAL 0x45 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_IMEM_CFG_AHB_CLK_FVAL 0x46 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_TCU_CFG_QX_CLK_FVAL 0x47 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_MMU_TCU_CLK_FVAL 0x48 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_MMU_TCU_SLP_STG_CLK_FVAL 0x49 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_TCU_ANOC_QTB1_CLK_FVAL 0x4a +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_TCU_ANOC_QTB2_CLK_FVAL 0x4b +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_TCU_MMNOC_QTB_SF_CLK_FVAL 0x4c +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_TCU_MMNOC_QTB_HF01_CLK_FVAL 0x4d +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_TCU_MMNOC_QTB_HF23_CLK_FVAL 0x4e +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_TCU_ANOC_PCIE_QTB_CLK_FVAL 0x4f +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_TCU_TURING_Q6_QTB0_CLK_FVAL 0x50 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_TCU_LPASS_AUDIO_QTB_CLK_FVAL 0x51 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_ANOC_PCIE_NORTH_AT_CLK_FVAL 0x52 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_ANOC_PCIE_TSCTR_CLK_FVAL 0x53 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_ANOC_PCIE_QOSGEN_EXTREF_CLK_FVAL 0x54 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_MMNOC_AT_CLK_FVAL 0x55 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_MMNOC_AHB_CFG_CLK_FVAL 0x56 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_NOC_MMNOC_DCD_XO_CLK_FVAL 0x57 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_MMNOC_TSCTR_CLK_FVAL 0x58 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_MMNOC_SF_CLK_FVAL 0x59 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_MMNOC_HF_QX_CLK_FVAL 0x5a +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_MMNOC_PWRCTL_CLK_FVAL 0x5b +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_MMNOC_QOSGEN_EXTREF_CLK_FVAL 0x5c +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_MMSS_AT_CLK_FVAL 0x5d +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_MMSS_QMIP_CORE_CLK_FVAL 0x5e +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_MMSS_TRIG_CLK_FVAL 0x5f +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_MMSS_QM_AHB_CLK_FVAL 0x60 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_CAMERA_AHB_CLK_FVAL 0x61 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QMIP_CAMERA_NRT_AHB_CLK_FVAL 0x62 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QMIP_CAMERA_RT_AHB_CLK_FVAL 0x63 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_CAMERA_HF_AXI_CLK_FVAL 0x64 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_CAMERA_HF_AXI_SLP_STG_CLK_FVAL 0x65 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_CAMERA_SF_AXI_CLK_FVAL 0x66 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_CAMERA_SF_AXI_SLP_STG_CLK_FVAL 0x67 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_CAMERA_XO_CLK_FVAL 0x68 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_CAMERA_GCC_DEBUG_CLK_FVAL 0x69 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_DISP_AHB_CLK_FVAL 0x6a +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QMIP_DISP_AHB_CLK_FVAL 0x6b +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_DISP_HF_AXI_CLK_FVAL 0x6c +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_DISP_XO_CLK_FVAL 0x6d +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_MDSS_GCC_DEBUG_CLK_FVAL 0x6e +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_VIDEO_AHB_CLK_FVAL 0x6f +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QMIP_VIDEO_CVP_AHB_CLK_FVAL 0x70 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QMIP_VIDEO_VCODEC_AHB_CLK_FVAL 0x71 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QMIP_VIDEO_V_CPU_AHB_CLK_FVAL 0x72 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QMIP_VIDEO_CV_CPU_AHB_CLK_FVAL 0x73 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_VIDEO_AXI0_CLK_FVAL 0x74 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_VIDEO_AXI1_CLK_FVAL 0x75 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_VIDEO_XO_CLK_FVAL 0x76 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_VIDEO_GCC_DEBUG_CLK_FVAL 0x77 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QDSS_DAP_AHB_CLK_FVAL 0x78 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QDSS_CFG_AHB_CLK_FVAL 0x79 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QDSS_CENTER_AT_CLK_FVAL 0x7a +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_SOUTH_AT_CLK_FVAL 0x7b +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_WEST_AT_CLK_FVAL 0x7c +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_NORTH_AT_CLK_FVAL 0x7d +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_PHY_AT_CLK_FVAL 0x7e +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QDSS_ETR_USB_CLK_FVAL 0x7f +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QDSS_ETR_DDR_CLK_FVAL 0x80 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QDSS_STM_CLK_FVAL 0x81 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QDSS_TRACECLKIN_CLK_FVAL 0x82 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QDSS_TSCTR_CLK_FVAL 0x83 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QDSS_TRIG_CLK_FVAL 0x84 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QDSS_DAP_CLK_FVAL 0x85 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_CENTER_APB_CLK_FVAL 0x86 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_NORTH_APB_CLK_FVAL 0x87 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_SOUTH_APB_CLK_FVAL 0x88 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_WEST_APB_CLK_FVAL 0x89 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_EAST_APB_CLK_FVAL 0x8a +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_MMNOC_APB_CLK_FVAL 0x8b +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QDSS_XO_CLK_FVAL 0x8c +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QDSS_USB_PRIM_CLK_FVAL 0x8d +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_USB30_PRIM_MASTER_CLK_FVAL 0x8e +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_USB30_PRIM_SLEEP_CLK_FVAL 0x8f +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_USB30_PRIM_MOCK_UTMI_CLK_FVAL 0x90 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_USB3_PRIM_PHY_AUX_CLK_FVAL 0x91 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_USB3_PRIM_PHY_COM_AUX_CLK_FVAL 0x92 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_USB3_PRIM_PHY_PIPE_CLK_FVAL 0x93 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_USB3_PRIM_LPC_GPLL_SRC_0_CLK_SRC_FVAL 0x94 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_USB3_PRIM_LPC_GPLL_SRC_1_CLK_SRC_FVAL 0x95 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_USB3DPPHY_GCC_DEBUG_CLK_FVAL 0x96 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK_FVAL 0x97 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_QUSB2PHY_PRIM_GCC_USB30_UTMI_CLK_FVAL 0x98 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_USB3PHY_GCC_DEBUG_CLK_FVAL 0x99 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_AHB2PHY_0_CLK_FVAL 0x9a +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_SDCC2_APPS_CLK_FVAL 0x9b +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_SDCC2_AHB_CLK_FVAL 0x9c +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_SDCC2_AT_CLK_FVAL 0x9d +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_SDCC4_APPS_CLK_FVAL 0x9e +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_SDCC4_AHB_CLK_FVAL 0x9f +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_SDCC4_AT_CLK_FVAL 0xa0 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QUPV3_I2C_S_AHB_CLK_FVAL 0xa1 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QUPV3_I2C_CORE_CLK_FVAL 0xa2 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QUPV3_I2C_S0_CLK_FVAL 0xa3 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QUPV3_I2C_S1_CLK_FVAL 0xa4 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QUPV3_I2C_S2_CLK_FVAL 0xa5 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QUPV3_I2C_S3_CLK_FVAL 0xa6 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QUPV3_I2C_S4_CLK_FVAL 0xa7 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QUPV3_I2C_S5_CLK_FVAL 0xa8 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QUPV3_I2C_S6_CLK_FVAL 0xa9 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QUPV3_I2C_S7_CLK_FVAL 0xaa +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QUPV3_I2C_S8_CLK_FVAL 0xab +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QUPV3_I2C_S9_CLK_FVAL 0xac +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QUPV3_WRAP_1_M_AHB_CLK_FVAL 0xad +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QUPV3_WRAP_1_S_AHB_CLK_FVAL 0xae +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QUPV3_WRAP1_CORE_CLK_FVAL 0xaf +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QUPV3_WRAP1_CORE_2X_CLK_FVAL 0xb0 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_AGGRE_NOC_SOUTH_AXI_CLK_FVAL 0xb1 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QUPV3_WRAP1_S0_CLK_FVAL 0xb2 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QUPV3_WRAP1_S1_CLK_FVAL 0xb3 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QUPV3_WRAP1_S2_CLK_FVAL 0xb4 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QUPV3_WRAP1_S3_CLK_FVAL 0xb5 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QUPV3_WRAP1_S4_CLK_FVAL 0xb6 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QUPV3_WRAP1_S5_CLK_FVAL 0xb7 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QUPV3_WRAP1_S6_CLK_FVAL 0xb8 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QUPV3_WRAP1_S7_CLK_FVAL 0xb9 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QUPV3_WRAP_2_M_AHB_CLK_FVAL 0xba +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QUPV3_WRAP_2_S_AHB_CLK_FVAL 0xbb +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QUPV3_WRAP2_CORE_CLK_FVAL 0xbc +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QUPV3_WRAP2_CORE_2X_CLK_FVAL 0xbd +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QUPV3_WRAP2_S0_CLK_FVAL 0xbe +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QUPV3_WRAP2_S1_CLK_FVAL 0xbf +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QUPV3_WRAP2_S2_CLK_FVAL 0xc0 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QUPV3_WRAP2_S3_CLK_FVAL 0xc1 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QUPV3_WRAP2_S4_CLK_FVAL 0xc2 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QUPV3_WRAP2_S5_CLK_FVAL 0xc3 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QUPV3_WRAP2_S6_CLK_FVAL 0xc4 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QUPV3_WRAP2_S7_CLK_FVAL 0xc5 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_PDM_AHB_CLK_FVAL 0xc6 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_PDM_XO4_CLK_FVAL 0xc7 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_PDM2_CLK_FVAL 0xc8 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_PMU_AHB_CLK_FVAL 0xc9 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_PMU_CORE_CLK_FVAL 0xca +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_PRNG_AHB_CLK_FVAL 0xcb +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_TME_AHB_CLK_FVAL 0xcc +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_TME_BOOT_ROM_AHB_CLK_FVAL 0xcd +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_TME_SNOC_QXM_CLK_FVAL 0xce +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_TME_GPLL0_CLK_SRC_FVAL 0xcf +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_TME_GPLL0_DIV2_CLK_SRC_FVAL 0xd0 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_TME_TRIG_CLK_FVAL 0xd1 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_TME_AT_CLK_FVAL 0xd2 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_TME_GCC_DEBUG_CLK_FVAL 0xd3 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_TCSR_AHB_CLK_FVAL 0xd4 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_TCSR_ACC_SERIAL_CLK_FVAL 0xd5 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_MEMRED_P2S_CLK_FVAL 0xd6 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_BOOT_ROM_AHB_CLK_FVAL 0xd7 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_TLMM_AHB_CLK_FVAL 0xd8 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_TLMM_CLK_FVAL 0xd9 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_AOSS_CNOC_M_AHB_CLK_FVAL 0xda +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_AOSS_CNOC_S_AHB_CLK_FVAL 0xdb +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_AOSS_AT_CLK_FVAL 0xdc +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_AOSS_GCC_DEBUG_CLK_FVAL 0xdd +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_SPDM_FF_CLK_FVAL 0xde +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_SPDM_MEMNOC_CY_CLK_FVAL 0xdf +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_SPDM_SNOC_CY_CLK_FVAL 0xe0 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_SPDM_PNOC_CY_CLK_FVAL 0xe1 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_CE1_CLK_FVAL 0xe2 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_CE1_AXI_CLK_FVAL 0xe3 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_CE1_AHB_CLK_FVAL 0xe4 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_AT_CLK_FVAL 0xe5 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_AHB_CLK_FVAL 0xe6 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_XO_CLK_FVAL 0xe7 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_XO_DIV4_CLK_FVAL 0xe8 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_XO_DIV16_CLK_FVAL 0xe9 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_SLEEP_CLK_FVAL 0xea +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_DDRSS_MMNOC_SF_CLK_FVAL 0xeb +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_DDRSS_MMNOC_HF_QX_CLK_FVAL 0xec +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_DDRSS_TCU_CLK_FVAL 0xed +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_DDRSS_TURING_Q6_AXI_CLK_FVAL 0xee +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_DDRSS_MSS_Q6_AXI_CLK_FVAL 0xef +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_DDRSS_MODEM_CLK_FVAL 0xf0 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_DDRSS_GPU_AXI_CLK_FVAL 0xf1 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_DDRSS_PCIE_SF_QTB_CLK_FVAL 0xf2 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_DDRSS_SNOC_GC_AXI_CLK_FVAL 0xf3 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_DDRSS_SNOC_SF_AXI_CLK_FVAL 0xf4 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_DDRSS_CONFIG_NOC_SF_CLK_FVAL 0xf5 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_DDRSS_CFG_AHB_CLK_FVAL 0xf6 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_MEMNOC_CLK_FVAL 0xf7 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_DDRSS_LPASS_SHUB_CLK_FVAL 0xf8 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_DDRSS_AT_CLK_FVAL 0xf9 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_SHRM_CLK_FVAL 0xfa +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_DDRSS_PWRCTL_CLK_FVAL 0xfb +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_DDRSS_GPLL0_MAIN_CLK_SRC_FVAL 0xfc +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_DDRSS_GCC_DEBUG_CLK_FVAL 0xfd +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_LPASS_CFG_NOC_SWAY_CLK_FVAL 0xfe +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QMIP_LPASS_QTB_AHB_CLK_FVAL 0xff +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_LPASS_TRIG_CLK_FVAL 0x100 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_LPASS_AT_CLK_FVAL 0x101 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_LPASS_AON_NOC_DDRSS_SHUB_CLK_FVAL 0x102 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_LPASS_AGGRE_NOC_MPU_CLIENT_DDRSS_SHUB_CLK_FVAL 0x103 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CLK_FVAL 0x104 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_LPASS_AGGRE_NOC_DDRSS_SHUB_CLK_FVAL 0x105 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_LPASS_GCC_DEBUG_CLK_FVAL 0x106 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_LPASS_QTB_AHB_CLK_FVAL 0x107 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_LPASS_AUDIO_QTB_CLK_FVAL 0x108 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_LPASS_QOSGEN_EXTREF_CLK_FVAL 0x109 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_LPASS_QDSS_TSCTR_CLK_FVAL 0x10a +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_LPASS_QTB_AT_CLK_FVAL 0x10b +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_LPASS_XO_CLK_FVAL 0x10c +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_LPASS_PWRCTL_CLK_FVAL 0x10d +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_TURING_Q6_QTB0_CLK_FVAL 0x10e +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_TURING_NSP_AHB_CLK_FVAL 0x10f +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_NSP_QOSGEN_EXTREF_CLK_FVAL 0x110 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_NSP_QDSS_TSCTR_CLK_FVAL 0x111 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_TURING_QTB_AT_CLK_FVAL 0x112 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_TURING_XO_CLK_FVAL 0x113 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_TURING_PWRCTL_CLK_FVAL 0x114 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_TURING_MMNOC_SF_CLK_FVAL 0x115 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_TURING_Q6_AXI_CLK_FVAL 0x116 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_TURING_CFG_AHB_CLK_FVAL 0x117 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_TURING_AT_CLK_FVAL 0x118 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QMIP_TURING_NSP_AHB_CLK_FVAL 0x119 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_TURING_TRIG_CLK_FVAL 0x11a +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_TURING_GCC_DEBUG_CLK_FVAL 0x11b +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_CPUSS_AHB_CLK_FVAL 0x11c +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_CPUSS_TRIG_CLK_FVAL 0x11d +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_CPUSS_AT_CLK_FVAL 0x11e +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_CPUSS_CONFIG_NOC_SF_CLK_FVAL 0x11f +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_APSS_QDSS_TSCTR_CLK_FVAL 0x120 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_APSS_QDSS_APB_CLK_FVAL 0x121 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_CPUSS_GCC_DEBUG_CLK_FVAL 0x122 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_NOC_BUS_TIMEOUT_EXTREF_CLK_FVAL 0x123 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_RBCPR_CX_CLK_FVAL 0x124 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_RBCPR_CX_AHB_CLK_FVAL 0x125 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_RBCPR_MXC_CLK_FVAL 0x126 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_RBCPR_MXC_AHB_CLK_FVAL 0x127 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_RBCPR_MXA_CLK_FVAL 0x128 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_RBCPR_MXA_AHB_CLK_FVAL 0x129 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_RBCPR_NSP_CLK_FVAL 0x12a +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_RBCPR_NSP_AHB_CLK_FVAL 0x12b +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_FRQ_MEASURE_REF_CLK_FVAL 0x12c +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_QUSB2PHY_GCC_CLK_TEST_PRIM_FVAL 0x12d +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_QUSB2PHY_GCC_CLK_TEST_SEC_FVAL 0x12e +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_GP1_CLK_FVAL 0x12f +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_GP2_CLK_FVAL 0x130 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_GP3_CLK_FVAL 0x131 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QMIP_PCIE_AHB_CLK_FVAL 0x132 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_PCIE_0_SLV_Q2A_AXI_CLK_FVAL 0x133 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_PCIE_0_SLV_AXI_CLK_FVAL 0x134 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_PCIE_0_MSTR_AXI_CLK_FVAL 0x135 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_PCIE_0_CFG_AHB_CLK_FVAL 0x136 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_PCIE_0_AUX_CLK_FVAL 0x137 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_PCIE_0_PIPE_CLK_FVAL 0x138 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_PCIE_0_PHY_RCHNG_CLK_FVAL 0x139 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_PCIE_0_PIPE_CLK_FVAL 0x13a +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_PCIE_0_GCC_DEBUG_CLK_FVAL 0x13b +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_PCIE_1_SLV_Q2A_AXI_CLK_FVAL 0x13c +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_PCIE_1_SLV_AXI_CLK_FVAL 0x13d +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_PCIE_1_MSTR_AXI_CLK_FVAL 0x13e +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_PCIE_1_CFG_AHB_CLK_FVAL 0x13f +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_PCIE_1_AUX_CLK_FVAL 0x140 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_PCIE_1_PHY_AUX_CLK_FVAL 0x141 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_PCIE_1_PIPE_CLK_FVAL 0x142 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_PCIE_1_PHY_RCHNG_CLK_FVAL 0x143 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_PCIE_1_PIPE_CLK_FVAL 0x144 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_PCIE_1_PHY_AUX_CLK_FVAL 0x145 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_PCIE_1_GCC_DEBUG_CLK_FVAL 0x146 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_UFS_PHY_AXI_CLK_FVAL 0x147 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_UFS_PHY_AHB_CLK_FVAL 0x148 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_UFS_PHY_TX_SYMBOL_0_CLK_FVAL 0x149 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_UFS_PHY_RX_SYMBOL_0_CLK_FVAL 0x14a +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_UFS_PHY_TX_SYMBOL_0_CLK_FVAL 0x14b +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_UFS_PHY_RX_SYMBOL_0_CLK_FVAL 0x14c +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_UFS_PHY_UNIPRO_CORE_CLK_FVAL 0x14d +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_UFS_PHY_ICE_CORE_CLK_FVAL 0x14e +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_UFS_PHY_PHY_AUX_CLK_FVAL 0x14f +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_UFS_PHY_RX_SYMBOL_1_CLK_FVAL 0x150 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_UFS_AT_CLK_FVAL 0x151 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_UFS_PHY_RX_SYMBOL_1_CLK_FVAL 0x152 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_UFS_PHY_GCC_DEBUG_CLK_FVAL 0x153 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_VDDMXC_VS_CLK_FVAL 0x154 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_VDDCX_VS_CLK_FVAL 0x155 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_VDDMX_VS_CLK_FVAL 0x156 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_VDDA_VS_CLK_FVAL 0x157 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_VS_CTRL_CLK_FVAL 0x158 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_VS_CTRL_AHB_CLK_FVAL 0x159 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_MSS_VS_CLK_FVAL 0x15a +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_GPU_VS_CLK_FVAL 0x15b +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_APC_VS_CLK_FVAL 0x15c +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_MDSS_VS_0_CLK_FVAL 0x15d +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_MDSS_VS_1_CLK_FVAL 0x15e +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_SLEEP_CLK_FVAL 0x15f +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_DCC_AHB_CLK_FVAL 0x160 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_IPA_2X_CLK_FVAL 0x161 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_IPA_CLK_FVAL 0x162 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_IPA_AHB_CLK_FVAL 0x163 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_IPA_XO_CLK_FVAL 0x164 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_IPA_APB_CLK_FVAL 0x165 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_IPA_AT_CLK_FVAL 0x166 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_MSS_CFG_AHB_CLK_FVAL 0x167 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QMIP_MSS_OFFLINE_CFG_AHB_CLK_FVAL 0x168 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QMIP_MSS_Q6_CFG_AHB_CLK_FVAL 0x169 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_MSS_OFFLINE_AXI_CLK_FVAL 0x16a +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_MSS_AXIS2_CLK_FVAL 0x16b +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_MSS_TRIG_CLK_FVAL 0x16c +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_MSS_AT_CLK_FVAL 0x16d +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_MSS_SNOC_AXI_CLK_FVAL 0x16e +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_MSS_Q6_MEMNOC_AXI_CLK_FVAL 0x16f +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_MSS_GPLL0_DIV_CLK_SRC_FVAL 0x170 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_MSS_GCC_DEBUG_CLK_FVAL 0x171 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_GLM_AHB_CLK_FVAL 0x172 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_GLM_CLK_FVAL 0x173 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_GLM_XO_CLK_FVAL 0x174 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_GPU_CFG_AHB_CLK_FVAL 0x175 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QMIP_GPU_AHB_CLK_FVAL 0x176 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_GPU_AT_CLK_FVAL 0x177 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GPU_GCC_DEBUG_CLK_FVAL 0x178 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_GPU_MEMNOC_GFX_CLK_FVAL 0x179 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_GPU_TRIG_CLK_FVAL 0x17a +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_GPU_SNOC_DVM_GFX_CLK_FVAL 0x17b +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_GPU_GPLL0_CLK_SRC_FVAL 0x17c +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_GPU_GPLL0_DIV_CLK_SRC_FVAL 0x17d +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_SP_SNOC_ANOC_AXI_CLK_FVAL 0x17e +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_SP_SCR_NIU_CLK_FVAL 0x17f +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_SP_CFG_AHB_CLK_FVAL 0x180 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_SP_SCSR_CLK_FVAL 0x181 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_SP_GPKT_XO_CLK_FVAL 0x182 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_SP_TRIG_CLK_FVAL 0x183 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_SP_AT_CLK_FVAL 0x184 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_SP_GCC_DEBUG_CLK_FVAL 0x185 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_NAV_AXI_CLK_FVAL 0x186 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_NAV_GCC_DEBUG_CLK_FVAL 0x187 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_AHB2PHY_1_CLK_FVAL 0x188 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_CM_PHY_REFGEN1_CLK_FVAL 0x189 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_CM_PHY_REFGEN2_CLK_FVAL 0x18a +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QSPI_CNOC_PERIPH_AHB_CLK_FVAL 0x18b +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_QSPI_CORE_CLK_FVAL 0x18c +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_RBCPR_MMCX_CLK_FVAL 0x18d +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_RBCPR_MMCX_AHB_CLK_FVAL 0x18e +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_IPCC_CORE_CLK_FVAL 0x18f +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_IPCC_AHB_CLK_FVAL 0x190 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_DPM_CLK_FVAL 0x191 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_DPM_CX_AHB_CLK_FVAL 0x192 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_DPM_MX_AHB_CLK_FVAL 0x193 +#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_GCC_DPM_CB_CLK_FVAL 0x194 + +#define HWIO_GCC_PLL_TEST_MUX_MUXR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00052034) +#define HWIO_GCC_PLL_TEST_MUX_MUXR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00052034) +#define HWIO_GCC_PLL_TEST_MUX_MUXR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00052034) +#define HWIO_GCC_PLL_TEST_MUX_MUXR_RMSK 0x3f +#define HWIO_GCC_PLL_TEST_MUX_MUXR_ATTR 0x3 +#define HWIO_GCC_PLL_TEST_MUX_MUXR_IN \ + in_dword_masked(HWIO_GCC_PLL_TEST_MUX_MUXR_ADDR, HWIO_GCC_PLL_TEST_MUX_MUXR_RMSK) +#define HWIO_GCC_PLL_TEST_MUX_MUXR_INM(m) \ + in_dword_masked(HWIO_GCC_PLL_TEST_MUX_MUXR_ADDR, m) +#define HWIO_GCC_PLL_TEST_MUX_MUXR_OUT(v) \ + out_dword(HWIO_GCC_PLL_TEST_MUX_MUXR_ADDR,v) +#define HWIO_GCC_PLL_TEST_MUX_MUXR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PLL_TEST_MUX_MUXR_ADDR,m,v,HWIO_GCC_PLL_TEST_MUX_MUXR_IN) +#define HWIO_GCC_PLL_TEST_MUX_MUXR_OUT_SEL_BMSK 0x3f +#define HWIO_GCC_PLL_TEST_MUX_MUXR_OUT_SEL_SHFT 0x0 +#define HWIO_GCC_PLL_TEST_MUX_MUXR_OUT_SEL_GCC_DEBUG_CLK_FVAL 0x0 +#define HWIO_GCC_PLL_TEST_MUX_MUXR_OUT_SEL_GPLL0_OUT_TEST_FVAL 0x1 +#define HWIO_GCC_PLL_TEST_MUX_MUXR_OUT_SEL_GPLL1_OUT_TEST_FVAL 0x2 +#define HWIO_GCC_PLL_TEST_MUX_MUXR_OUT_SEL_GPLL2_OUT_TEST_FVAL 0x3 +#define HWIO_GCC_PLL_TEST_MUX_MUXR_OUT_SEL_GPLL3_OUT_TEST_FVAL 0x4 +#define HWIO_GCC_PLL_TEST_MUX_MUXR_OUT_SEL_GPLL4_OUT_TEST_FVAL 0x5 +#define HWIO_GCC_PLL_TEST_MUX_MUXR_OUT_SEL_GPLL5_OUT_TEST_FVAL 0x6 +#define HWIO_GCC_PLL_TEST_MUX_MUXR_OUT_SEL_GPLL6_OUT_TEST_FVAL 0x7 +#define HWIO_GCC_PLL_TEST_MUX_MUXR_OUT_SEL_CPUSS_GCC_PLL_TEST_CLK_FVAL 0x8 +#define HWIO_GCC_PLL_TEST_MUX_MUXR_OUT_SEL_MSS_GCC_PLL_TEST_CLK_FVAL 0xa +#define HWIO_GCC_PLL_TEST_MUX_MUXR_OUT_SEL_LPASS_GCC_PLL_TEST_CLK_FVAL 0xb +#define HWIO_GCC_PLL_TEST_MUX_MUXR_OUT_SEL_TURING_GCC_PLL_TEST_CLK_FVAL 0xc +#define HWIO_GCC_PLL_TEST_MUX_MUXR_OUT_SEL_GPU_GCC_PLL_TEST_CLK_FVAL 0xd +#define HWIO_GCC_PLL_TEST_MUX_MUXR_OUT_SEL_NAV_GCC_PLL_TEST_CLK_FVAL 0xe +#define HWIO_GCC_PLL_TEST_MUX_MUXR_OUT_SEL_MSS_GCC_VQ6_LDO_NMO_OUT_FVAL 0x10 +#define HWIO_GCC_PLL_TEST_MUX_MUXR_OUT_SEL_DDRSS_GCC_PLL_TEST_CLK_FVAL 0x11 +#define HWIO_GCC_PLL_TEST_MUX_MUXR_OUT_SEL_MSS_GCC_Q6_LDO_NMO_OUT_FVAL 0x12 +#define HWIO_GCC_PLL_TEST_MUX_MUXR_OUT_SEL_LPASS_GCC_Q6_LDO_NMO_OUT_FVAL 0x13 +#define HWIO_GCC_PLL_TEST_MUX_MUXR_OUT_SEL_SPSS_GCC_PLL_TEST_CLK_FVAL 0x16 +#define HWIO_GCC_PLL_TEST_MUX_MUXR_OUT_SEL_QREFS_GCC_CXO2_RXTAP0_CLK_TEST_SE_FVAL 0x17 +#define HWIO_GCC_PLL_TEST_MUX_MUXR_OUT_SEL_QREFS_GCC_CXO_RXTAP1_CLK_TEST_SE_FVAL 0x18 +#define HWIO_GCC_PLL_TEST_MUX_MUXR_OUT_SEL_QREFS_GCC_CXO_RXTAP2_CLK_TEST_SE_FVAL 0x19 +#define HWIO_GCC_PLL_TEST_MUX_MUXR_OUT_SEL_QREFS_GCC_CXO_RXTAP2A_CLK_TEST_SE_FVAL 0x1a +#define HWIO_GCC_PLL_TEST_MUX_MUXR_OUT_SEL_QREFS_GCC_CXO_RXTAP3_CLK_TEST_SE_FVAL 0x1b +#define HWIO_GCC_PLL_TEST_MUX_MUXR_OUT_SEL_DISP_GCC_PLL_TEST_CLK_FVAL 0x1c +#define HWIO_GCC_PLL_TEST_MUX_MUXR_OUT_SEL_CAM_GCC_PLL_TEST_CLK_FVAL 0x1d +#define HWIO_GCC_PLL_TEST_MUX_MUXR_OUT_SEL_VIDEO_GCC_PLL_TEST_CLK_FVAL 0x1e +#define HWIO_GCC_PLL_TEST_MUX_MUXR_OUT_SEL_AOSS_GCC_PLL_TEST_CLK_FVAL 0x1f +#define HWIO_GCC_PLL_TEST_MUX_MUXR_OUT_SEL_GPLL7_OUT_TEST_FVAL 0x21 +#define HWIO_GCC_PLL_TEST_MUX_MUXR_OUT_SEL_GPLL8_OUT_TEST_FVAL 0x22 +#define HWIO_GCC_PLL_TEST_MUX_MUXR_OUT_SEL_GPLL9_OUT_TEST_FVAL 0x23 +#define HWIO_GCC_PLL_TEST_MUX_MUXR_OUT_SEL_UFS_PHY_GCC_TEST_CLK_FVAL 0x27 + +#define HWIO_GCC_PLL_STATUS_MUXR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005203c) +#define HWIO_GCC_PLL_STATUS_MUXR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005203c) +#define HWIO_GCC_PLL_STATUS_MUXR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005203c) +#define HWIO_GCC_PLL_STATUS_MUXR_RMSK 0x3f +#define HWIO_GCC_PLL_STATUS_MUXR_ATTR 0x3 +#define HWIO_GCC_PLL_STATUS_MUXR_IN \ + in_dword_masked(HWIO_GCC_PLL_STATUS_MUXR_ADDR, HWIO_GCC_PLL_STATUS_MUXR_RMSK) +#define HWIO_GCC_PLL_STATUS_MUXR_INM(m) \ + in_dword_masked(HWIO_GCC_PLL_STATUS_MUXR_ADDR, m) +#define HWIO_GCC_PLL_STATUS_MUXR_OUT(v) \ + out_dword(HWIO_GCC_PLL_STATUS_MUXR_ADDR,v) +#define HWIO_GCC_PLL_STATUS_MUXR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PLL_STATUS_MUXR_ADDR,m,v,HWIO_GCC_PLL_STATUS_MUXR_IN) +#define HWIO_GCC_PLL_STATUS_MUXR_DEBUG_BUS_SEL_BMSK 0x3f +#define HWIO_GCC_PLL_STATUS_MUXR_DEBUG_BUS_SEL_SHFT 0x0 +#define HWIO_GCC_PLL_STATUS_MUXR_DEBUG_BUS_SEL_DEFAULT_ZERO_FVAL 0x0 +#define HWIO_GCC_PLL_STATUS_MUXR_DEBUG_BUS_SEL_GPLL0_STATUS_DEBUG_FVAL 0x1 +#define HWIO_GCC_PLL_STATUS_MUXR_DEBUG_BUS_SEL_GPLL1_STATUS_DEBUG_FVAL 0x2 +#define HWIO_GCC_PLL_STATUS_MUXR_DEBUG_BUS_SEL_GPLL2_STATUS_DEBUG_FVAL 0x3 +#define HWIO_GCC_PLL_STATUS_MUXR_DEBUG_BUS_SEL_GPLL3_STATUS_DEBUG_FVAL 0x4 +#define HWIO_GCC_PLL_STATUS_MUXR_DEBUG_BUS_SEL_GPLL4_STATUS_DEBUG_FVAL 0x5 +#define HWIO_GCC_PLL_STATUS_MUXR_DEBUG_BUS_SEL_GPLL5_STATUS_DEBUG_FVAL 0x6 +#define HWIO_GCC_PLL_STATUS_MUXR_DEBUG_BUS_SEL_GPLL6_STATUS_DEBUG_FVAL 0x7 +#define HWIO_GCC_PLL_STATUS_MUXR_DEBUG_BUS_SEL_GPLL7_STATUS_DEBUG_FVAL 0x8 +#define HWIO_GCC_PLL_STATUS_MUXR_DEBUG_BUS_SEL_GPLL8_STATUS_DEBUG_FVAL 0x9 +#define HWIO_GCC_PLL_STATUS_MUXR_DEBUG_BUS_SEL_GPLL9_STATUS_DEBUG_FVAL 0xa +#define HWIO_GCC_PLL_STATUS_MUXR_DEBUG_BUS_SEL_JBIST_STATUS_DEBUG_FVAL 0xb +#define HWIO_GCC_PLL_STATUS_MUXR_DEBUG_BUS_SEL_SYSTEM_NOC_CLK_SRC_DEBUG_BUS_FVAL 0xc +#define HWIO_GCC_PLL_STATUS_MUXR_DEBUG_BUS_SEL_GPLL_LOCK_DET_STATUS_FVAL 0xd +#define HWIO_GCC_PLL_STATUS_MUXR_DEBUG_BUS_SEL_GCC_RPMH_CE_IPA_STATUS_FVAL 0xe +#define HWIO_GCC_PLL_STATUS_MUXR_DEBUG_BUS_SEL_GCC_RPMH_SHRM_QUPV3_STATUS_FVAL 0xf +#define HWIO_GCC_PLL_STATUS_MUXR_DEBUG_BUS_SEL_GCC_RPMH_SHUB_STATUS_FVAL 0x10 +#define HWIO_GCC_PLL_STATUS_MUXR_DEBUG_BUS_SEL_GCC_RPMH_SNOC_CNOC_STATUS_FVAL 0x11 +#define HWIO_GCC_PLL_STATUS_MUXR_DEBUG_BUS_SEL_GCC_RPMH_MMNOC_CDSPNOC_STATUS_FVAL 0x12 +#define HWIO_GCC_PLL_STATUS_MUXR_DEBUG_BUS_SEL_GCC_USB30_PRIM_GDS_FSM_STATE_FVAL 0x13 +#define HWIO_GCC_PLL_STATUS_MUXR_DEBUG_BUS_SEL_GCC_ANOC_PCIE_GDS_FSM_STATE_FVAL 0x14 +#define HWIO_GCC_PLL_STATUS_MUXR_DEBUG_BUS_SEL_GCC_IPA_GDS_FSM_STATE_FVAL 0x15 +#define HWIO_GCC_PLL_STATUS_MUXR_DEBUG_BUS_SEL_GCC_MMNOC_GDS_FSM_STATE_FVAL 0x16 +#define HWIO_GCC_PLL_STATUS_MUXR_DEBUG_BUS_SEL_GCC_PCIE_0_GDS_FSM_STATE_FVAL 0x17 +#define HWIO_GCC_PLL_STATUS_MUXR_DEBUG_BUS_SEL_GCC_PCIE_1_GDS_FSM_STATE_FVAL 0x18 +#define HWIO_GCC_PLL_STATUS_MUXR_DEBUG_BUS_SEL_GCC_UFS_PHY_GDS_FSM_STATE_FVAL 0x19 +#define HWIO_GCC_PLL_STATUS_MUXR_DEBUG_BUS_SEL_GCC_TURING_QTB_GDS_FSM_STATE_FVAL 0x1a +#define HWIO_GCC_PLL_STATUS_MUXR_DEBUG_BUS_SEL_GCC_MMU_GDS_FSM_STATE_FVAL 0x1b +#define HWIO_GCC_PLL_STATUS_MUXR_DEBUG_BUS_SEL_GCC_USB3_PHY_GDS_FSM_STATE_FVAL 0x1c +#define HWIO_GCC_PLL_STATUS_MUXR_DEBUG_BUS_SEL_GCC_LPASS_QTB_GDS_FSM_STATE_FVAL 0x1d +#define HWIO_GCC_PLL_STATUS_MUXR_DEBUG_BUS_SEL_GCC_PCIE_0_PHY_GDS_FSM_STATE_FVAL 0x1e +#define HWIO_GCC_PLL_STATUS_MUXR_DEBUG_BUS_SEL_GCC_PCIE_1_PHY_GDS_FSM_STATE_FVAL 0x1f +#define HWIO_GCC_PLL_STATUS_MUXR_DEBUG_BUS_SEL_DEBUG_BUG_MISC_FVAL 0x20 +#define HWIO_GCC_PLL_STATUS_MUXR_DEBUG_BUS_SEL_GCC_DEBUG_BUS_SLP_RET_SIGNALS_1_FVAL 0x21 +#define HWIO_GCC_PLL_STATUS_MUXR_DEBUG_BUS_SEL_GCC_DEBUG_BUS_SLP_RET_SIGNALS_2_FVAL 0x22 +#define HWIO_GCC_PLL_STATUS_MUXR_DEBUG_BUS_SEL_GCC_DEBUG_BUS_SLP_RET_SIGNALS_3_FVAL 0x23 +#define HWIO_GCC_PLL_STATUS_MUXR_DEBUG_BUS_SEL_GCC_DEBUG_BUS_SLP_RET_SIGNALS_4_FVAL 0x24 +#define HWIO_GCC_PLL_STATUS_MUXR_DEBUG_BUS_SEL_GCC_UFS_MEM_PHY_GDS_FSM_STATE_FVAL 0x25 +#define HWIO_GCC_PLL_STATUS_MUXR_DEBUG_BUS_SEL_CC_ALL_CLKS_OFF_STATUS_0_FVAL 0x26 +#define HWIO_GCC_PLL_STATUS_MUXR_DEBUG_BUS_SEL_CC_ALL_CLKS_OFF_STATUS_1_FVAL 0x27 +#define HWIO_GCC_PLL_STATUS_MUXR_DEBUG_BUS_SEL_CC_ALL_CLKS_OFF_STATUS_2_FVAL 0x28 +#define HWIO_GCC_PLL_STATUS_MUXR_DEBUG_BUS_SEL_CC_ALL_CLKS_OFF_STATUS_3_FVAL 0x29 +#define HWIO_GCC_PLL_STATUS_MUXR_DEBUG_BUS_SEL_CC_ALL_CLKS_OFF_STATUS_4_FVAL 0x2a + +#define HWIO_GCC_DEBUG_OR_PLL_TEST_MUX_MUXR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00052040) +#define HWIO_GCC_DEBUG_OR_PLL_TEST_MUX_MUXR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00052040) +#define HWIO_GCC_DEBUG_OR_PLL_TEST_MUX_MUXR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00052040) +#define HWIO_GCC_DEBUG_OR_PLL_TEST_MUX_MUXR_RMSK 0x1 +#define HWIO_GCC_DEBUG_OR_PLL_TEST_MUX_MUXR_ATTR 0x3 +#define HWIO_GCC_DEBUG_OR_PLL_TEST_MUX_MUXR_IN \ + in_dword_masked(HWIO_GCC_DEBUG_OR_PLL_TEST_MUX_MUXR_ADDR, HWIO_GCC_DEBUG_OR_PLL_TEST_MUX_MUXR_RMSK) +#define HWIO_GCC_DEBUG_OR_PLL_TEST_MUX_MUXR_INM(m) \ + in_dword_masked(HWIO_GCC_DEBUG_OR_PLL_TEST_MUX_MUXR_ADDR, m) +#define HWIO_GCC_DEBUG_OR_PLL_TEST_MUX_MUXR_OUT(v) \ + out_dword(HWIO_GCC_DEBUG_OR_PLL_TEST_MUX_MUXR_ADDR,v) +#define HWIO_GCC_DEBUG_OR_PLL_TEST_MUX_MUXR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DEBUG_OR_PLL_TEST_MUX_MUXR_ADDR,m,v,HWIO_GCC_DEBUG_OR_PLL_TEST_MUX_MUXR_IN) +#define HWIO_GCC_DEBUG_OR_PLL_TEST_MUX_MUXR_PLLTEST_DE_SEL_BMSK 0x1 +#define HWIO_GCC_DEBUG_OR_PLL_TEST_MUX_MUXR_PLLTEST_DE_SEL_SHFT 0x0 +#define HWIO_GCC_DEBUG_OR_PLL_TEST_MUX_MUXR_PLLTEST_DE_SEL_DEBUG_PREDIV_CLK_FVAL 0x0 +#define HWIO_GCC_DEBUG_OR_PLL_TEST_MUX_MUXR_PLLTEST_DE_SEL_PLLTEST_DE_FVAL 0x1 + +#define HWIO_GCC_PLLTEST_PAD_CFG_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00052044) +#define HWIO_GCC_PLLTEST_PAD_CFG_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00052044) +#define HWIO_GCC_PLLTEST_PAD_CFG_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00052044) +#define HWIO_GCC_PLLTEST_PAD_CFG_RMSK 0x3ffffff +#define HWIO_GCC_PLLTEST_PAD_CFG_ATTR 0x3 +#define HWIO_GCC_PLLTEST_PAD_CFG_IN \ + in_dword_masked(HWIO_GCC_PLLTEST_PAD_CFG_ADDR, HWIO_GCC_PLLTEST_PAD_CFG_RMSK) +#define HWIO_GCC_PLLTEST_PAD_CFG_INM(m) \ + in_dword_masked(HWIO_GCC_PLLTEST_PAD_CFG_ADDR, m) +#define HWIO_GCC_PLLTEST_PAD_CFG_OUT(v) \ + out_dword(HWIO_GCC_PLLTEST_PAD_CFG_ADDR,v) +#define HWIO_GCC_PLLTEST_PAD_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PLLTEST_PAD_CFG_ADDR,m,v,HWIO_GCC_PLLTEST_PAD_CFG_IN) +#define HWIO_GCC_PLLTEST_PAD_CFG_CORE_PLL_B_BMSK 0x3000000 +#define HWIO_GCC_PLLTEST_PAD_CFG_CORE_PLL_B_SHFT 0x18 +#define HWIO_GCC_PLLTEST_PAD_CFG_CORE_PLL_B_NONE_FVAL 0x0 +#define HWIO_GCC_PLLTEST_PAD_CFG_CORE_PLL_B_PULLDOWN_FVAL 0x1 +#define HWIO_GCC_PLLTEST_PAD_CFG_CORE_PLL_B_KEEP_FVAL 0x2 +#define HWIO_GCC_PLLTEST_PAD_CFG_CORE_PLL_B_PULLUP_FVAL 0x3 +#define HWIO_GCC_PLLTEST_PAD_CFG_RESERVE_BITS23_20_BMSK 0xf00000 +#define HWIO_GCC_PLLTEST_PAD_CFG_RESERVE_BITS23_20_SHFT 0x14 +#define HWIO_GCC_PLLTEST_PAD_CFG_CORE_PLL_EN_BMSK 0x80000 +#define HWIO_GCC_PLLTEST_PAD_CFG_CORE_PLL_EN_SHFT 0x13 +#define HWIO_GCC_PLLTEST_PAD_CFG_CORE_PLL_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_PLLTEST_PAD_CFG_CORE_PLL_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_PLLTEST_PAD_CFG_RESERVE_BIT18_BMSK 0x40000 +#define HWIO_GCC_PLLTEST_PAD_CFG_RESERVE_BIT18_SHFT 0x12 +#define HWIO_GCC_PLLTEST_PAD_CFG_CORE_OE_BMSK 0x20000 +#define HWIO_GCC_PLLTEST_PAD_CFG_CORE_OE_SHFT 0x11 +#define HWIO_GCC_PLLTEST_PAD_CFG_CORE_OE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PLLTEST_PAD_CFG_CORE_OE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PLLTEST_PAD_CFG_RESERVE_BIT16_BMSK 0x10000 +#define HWIO_GCC_PLLTEST_PAD_CFG_RESERVE_BIT16_SHFT 0x10 +#define HWIO_GCC_PLLTEST_PAD_CFG_CORE_IE_BMSK 0x8000 +#define HWIO_GCC_PLLTEST_PAD_CFG_CORE_IE_SHFT 0xf +#define HWIO_GCC_PLLTEST_PAD_CFG_CORE_IE_DISABLE_FVAL 0x0 +#define HWIO_GCC_PLLTEST_PAD_CFG_CORE_IE_ENABLE_FVAL 0x1 +#define HWIO_GCC_PLLTEST_PAD_CFG_RESERVE_BIT14_BMSK 0x4000 +#define HWIO_GCC_PLLTEST_PAD_CFG_RESERVE_BIT14_SHFT 0xe +#define HWIO_GCC_PLLTEST_PAD_CFG_HDRIVE_BMSK 0x3800 +#define HWIO_GCC_PLLTEST_PAD_CFG_HDRIVE_SHFT 0xb +#define HWIO_GCC_PLLTEST_PAD_CFG_HDRIVE_DRIVE_150MV_FVAL 0x0 +#define HWIO_GCC_PLLTEST_PAD_CFG_HDRIVE_DRIVE_200MV_FVAL 0x1 +#define HWIO_GCC_PLLTEST_PAD_CFG_HDRIVE_DRIVE_250MV_FVAL 0x2 +#define HWIO_GCC_PLLTEST_PAD_CFG_HDRIVE_DRIVE_300MV_FVAL 0x3 +#define HWIO_GCC_PLLTEST_PAD_CFG_HDRIVE_NEW_A_FVAL 0x4 +#define HWIO_GCC_PLLTEST_PAD_CFG_HDRIVE_NEW_B_FVAL 0x5 +#define HWIO_GCC_PLLTEST_PAD_CFG_HDRIVE_NEW_C_FVAL 0x6 +#define HWIO_GCC_PLLTEST_PAD_CFG_HDRIVE_NEW_D_FVAL 0x7 +#define HWIO_GCC_PLLTEST_PAD_CFG_RESERVE_BITS10_6_BMSK 0x7c0 +#define HWIO_GCC_PLLTEST_PAD_CFG_RESERVE_BITS10_6_SHFT 0x6 +#define HWIO_GCC_PLLTEST_PAD_CFG_RESERVE_BITS5_0_BMSK 0x3f +#define HWIO_GCC_PLLTEST_PAD_CFG_RESERVE_BITS5_0_SHFT 0x0 + +#define HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00052048) +#define HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00052048) +#define HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00052048) +#define HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_RMSK 0x3fffff +#define HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_ATTR 0x3 +#define HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_IN \ + in_dword_masked(HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_ADDR, HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_RMSK) +#define HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_INM(m) \ + in_dword_masked(HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_ADDR, m) +#define HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_OUT(v) \ + out_dword(HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_ADDR,v) +#define HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_ADDR,m,v,HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_IN) +#define HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_CLR_CNT_BMSK 0x200000 +#define HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_CLR_CNT_SHFT 0x15 +#define HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_CLR_CNT_NO_RESET_CNT_FVAL 0x0 +#define HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_CLR_CNT_RESET_CNT_FVAL 0x1 +#define HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_CNT_EN_BMSK 0x100000 +#define HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_CNT_EN_SHFT 0x14 +#define HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_CNT_EN_DISABLE_FVAL 0x0 +#define HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_CNT_EN_ENABLE_FVAL 0x1 +#define HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_XO_DIV4_TERM_CNT_BMSK 0xfffff +#define HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_XO_DIV4_TERM_CNT_SHFT 0x0 + +#define HWIO_GCC_CLOCK_FRQ_MEASURE_STATUS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005204c) +#define HWIO_GCC_CLOCK_FRQ_MEASURE_STATUS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005204c) +#define HWIO_GCC_CLOCK_FRQ_MEASURE_STATUS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005204c) +#define HWIO_GCC_CLOCK_FRQ_MEASURE_STATUS_RMSK 0x3ffffff +#define HWIO_GCC_CLOCK_FRQ_MEASURE_STATUS_ATTR 0x1 +#define HWIO_GCC_CLOCK_FRQ_MEASURE_STATUS_IN \ + in_dword_masked(HWIO_GCC_CLOCK_FRQ_MEASURE_STATUS_ADDR, HWIO_GCC_CLOCK_FRQ_MEASURE_STATUS_RMSK) +#define HWIO_GCC_CLOCK_FRQ_MEASURE_STATUS_INM(m) \ + in_dword_masked(HWIO_GCC_CLOCK_FRQ_MEASURE_STATUS_ADDR, m) +#define HWIO_GCC_CLOCK_FRQ_MEASURE_STATUS_XO_DIV4_CNT_DONE_BMSK 0x2000000 +#define HWIO_GCC_CLOCK_FRQ_MEASURE_STATUS_XO_DIV4_CNT_DONE_SHFT 0x19 +#define HWIO_GCC_CLOCK_FRQ_MEASURE_STATUS_MEASURE_CNT_BMSK 0x1ffffff +#define HWIO_GCC_CLOCK_FRQ_MEASURE_STATUS_MEASURE_CNT_SHFT 0x0 + +#define HWIO_GCC_GDS_HW_CTRL_SW_OVRD_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00068040) +#define HWIO_GCC_GDS_HW_CTRL_SW_OVRD_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00068040) +#define HWIO_GCC_GDS_HW_CTRL_SW_OVRD_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00068040) +#define HWIO_GCC_GDS_HW_CTRL_SW_OVRD_RMSK 0x1 +#define HWIO_GCC_GDS_HW_CTRL_SW_OVRD_ATTR 0x3 +#define HWIO_GCC_GDS_HW_CTRL_SW_OVRD_IN \ + in_dword_masked(HWIO_GCC_GDS_HW_CTRL_SW_OVRD_ADDR, HWIO_GCC_GDS_HW_CTRL_SW_OVRD_RMSK) +#define HWIO_GCC_GDS_HW_CTRL_SW_OVRD_INM(m) \ + in_dword_masked(HWIO_GCC_GDS_HW_CTRL_SW_OVRD_ADDR, m) +#define HWIO_GCC_GDS_HW_CTRL_SW_OVRD_OUT(v) \ + out_dword(HWIO_GCC_GDS_HW_CTRL_SW_OVRD_ADDR,v) +#define HWIO_GCC_GDS_HW_CTRL_SW_OVRD_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GDS_HW_CTRL_SW_OVRD_ADDR,m,v,HWIO_GCC_GDS_HW_CTRL_SW_OVRD_IN) +#define HWIO_GCC_GDS_HW_CTRL_SW_OVRD_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_GDS_HW_CTRL_SW_OVRD_SW_OVERRIDE_SHFT 0x0 + +#define HWIO_GCC_VTT_EN_TIMER_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006300c) +#define HWIO_GCC_VTT_EN_TIMER_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006300c) +#define HWIO_GCC_VTT_EN_TIMER_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006300c) +#define HWIO_GCC_VTT_EN_TIMER_RMSK 0xfffff +#define HWIO_GCC_VTT_EN_TIMER_ATTR 0x3 +#define HWIO_GCC_VTT_EN_TIMER_IN \ + in_dword_masked(HWIO_GCC_VTT_EN_TIMER_ADDR, HWIO_GCC_VTT_EN_TIMER_RMSK) +#define HWIO_GCC_VTT_EN_TIMER_INM(m) \ + in_dword_masked(HWIO_GCC_VTT_EN_TIMER_ADDR, m) +#define HWIO_GCC_VTT_EN_TIMER_OUT(v) \ + out_dword(HWIO_GCC_VTT_EN_TIMER_ADDR,v) +#define HWIO_GCC_VTT_EN_TIMER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_VTT_EN_TIMER_ADDR,m,v,HWIO_GCC_VTT_EN_TIMER_IN) +#define HWIO_GCC_VTT_EN_TIMER_PVC_LOAD_VALUE_BMSK 0xfffff +#define HWIO_GCC_VTT_EN_TIMER_PVC_LOAD_VALUE_SHFT 0x0 + +#define HWIO_GCC_VREF_EN_TIMER_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00063010) +#define HWIO_GCC_VREF_EN_TIMER_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00063010) +#define HWIO_GCC_VREF_EN_TIMER_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00063010) +#define HWIO_GCC_VREF_EN_TIMER_RMSK 0x3fffff +#define HWIO_GCC_VREF_EN_TIMER_ATTR 0x3 +#define HWIO_GCC_VREF_EN_TIMER_IN \ + in_dword_masked(HWIO_GCC_VREF_EN_TIMER_ADDR, HWIO_GCC_VREF_EN_TIMER_RMSK) +#define HWIO_GCC_VREF_EN_TIMER_INM(m) \ + in_dword_masked(HWIO_GCC_VREF_EN_TIMER_ADDR, m) +#define HWIO_GCC_VREF_EN_TIMER_OUT(v) \ + out_dword(HWIO_GCC_VREF_EN_TIMER_ADDR,v) +#define HWIO_GCC_VREF_EN_TIMER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_VREF_EN_TIMER_ADDR,m,v,HWIO_GCC_VREF_EN_TIMER_IN) +#define HWIO_GCC_VREF_EN_TIMER_MAX_INDEX_BMSK 0x300000 +#define HWIO_GCC_VREF_EN_TIMER_MAX_INDEX_SHFT 0x14 +#define HWIO_GCC_VREF_EN_TIMER_PVC_LOAD_VALUE_BMSK 0xfffff +#define HWIO_GCC_VREF_EN_TIMER_PVC_LOAD_VALUE_SHFT 0x0 + +#define HWIO_GCC_PLL_IS_ACTIVE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00063018) +#define HWIO_GCC_PLL_IS_ACTIVE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00063018) +#define HWIO_GCC_PLL_IS_ACTIVE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00063018) +#define HWIO_GCC_PLL_IS_ACTIVE_RMSK 0x33 +#define HWIO_GCC_PLL_IS_ACTIVE_ATTR 0x3 +#define HWIO_GCC_PLL_IS_ACTIVE_IN \ + in_dword_masked(HWIO_GCC_PLL_IS_ACTIVE_ADDR, HWIO_GCC_PLL_IS_ACTIVE_RMSK) +#define HWIO_GCC_PLL_IS_ACTIVE_INM(m) \ + in_dword_masked(HWIO_GCC_PLL_IS_ACTIVE_ADDR, m) +#define HWIO_GCC_PLL_IS_ACTIVE_OUT(v) \ + out_dword(HWIO_GCC_PLL_IS_ACTIVE_ADDR,v) +#define HWIO_GCC_PLL_IS_ACTIVE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PLL_IS_ACTIVE_ADDR,m,v,HWIO_GCC_PLL_IS_ACTIVE_IN) +#define HWIO_GCC_PLL_IS_ACTIVE_GPLL5_SEL_BMSK 0x20 +#define HWIO_GCC_PLL_IS_ACTIVE_GPLL5_SEL_SHFT 0x5 +#define HWIO_GCC_PLL_IS_ACTIVE_GPLL4_SEL_BMSK 0x10 +#define HWIO_GCC_PLL_IS_ACTIVE_GPLL4_SEL_SHFT 0x4 +#define HWIO_GCC_PLL_IS_ACTIVE_GPLL1_SEL_BMSK 0x2 +#define HWIO_GCC_PLL_IS_ACTIVE_GPLL1_SEL_SHFT 0x1 +#define HWIO_GCC_PLL_IS_ACTIVE_GPLL0_SEL_BMSK 0x1 +#define HWIO_GCC_PLL_IS_ACTIVE_GPLL0_SEL_SHFT 0x0 + +#define HWIO_GCC_GDS_HW_CTRL_SPARE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00068030) +#define HWIO_GCC_GDS_HW_CTRL_SPARE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00068030) +#define HWIO_GCC_GDS_HW_CTRL_SPARE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00068030) +#define HWIO_GCC_GDS_HW_CTRL_SPARE_RMSK 0xff +#define HWIO_GCC_GDS_HW_CTRL_SPARE_ATTR 0x3 +#define HWIO_GCC_GDS_HW_CTRL_SPARE_IN \ + in_dword_masked(HWIO_GCC_GDS_HW_CTRL_SPARE_ADDR, HWIO_GCC_GDS_HW_CTRL_SPARE_RMSK) +#define HWIO_GCC_GDS_HW_CTRL_SPARE_INM(m) \ + in_dword_masked(HWIO_GCC_GDS_HW_CTRL_SPARE_ADDR, m) +#define HWIO_GCC_GDS_HW_CTRL_SPARE_OUT(v) \ + out_dword(HWIO_GCC_GDS_HW_CTRL_SPARE_ADDR,v) +#define HWIO_GCC_GDS_HW_CTRL_SPARE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GDS_HW_CTRL_SPARE_ADDR,m,v,HWIO_GCC_GDS_HW_CTRL_SPARE_IN) +#define HWIO_GCC_GDS_HW_CTRL_SPARE_SPARE_BMSK 0xff +#define HWIO_GCC_GDS_HW_CTRL_SPARE_SPARE_SHFT 0x0 + +#define HWIO_GCC_WCSS_PD_CLK_DIS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00011104) +#define HWIO_GCC_WCSS_PD_CLK_DIS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00011104) +#define HWIO_GCC_WCSS_PD_CLK_DIS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00011104) +#define HWIO_GCC_WCSS_PD_CLK_DIS_RMSK 0x1 +#define HWIO_GCC_WCSS_PD_CLK_DIS_ATTR 0x3 +#define HWIO_GCC_WCSS_PD_CLK_DIS_IN \ + in_dword_masked(HWIO_GCC_WCSS_PD_CLK_DIS_ADDR, HWIO_GCC_WCSS_PD_CLK_DIS_RMSK) +#define HWIO_GCC_WCSS_PD_CLK_DIS_INM(m) \ + in_dword_masked(HWIO_GCC_WCSS_PD_CLK_DIS_ADDR, m) +#define HWIO_GCC_WCSS_PD_CLK_DIS_OUT(v) \ + out_dword(HWIO_GCC_WCSS_PD_CLK_DIS_ADDR,v) +#define HWIO_GCC_WCSS_PD_CLK_DIS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_WCSS_PD_CLK_DIS_ADDR,m,v,HWIO_GCC_WCSS_PD_CLK_DIS_IN) +#define HWIO_GCC_WCSS_PD_CLK_DIS_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_WCSS_PD_CLK_DIS_SW_OVERRIDE_SHFT 0x0 + +#define HWIO_GCC_SPARE0_REG_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005d000) +#define HWIO_GCC_SPARE0_REG_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005d000) +#define HWIO_GCC_SPARE0_REG_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005d000) +#define HWIO_GCC_SPARE0_REG_RMSK 0xffffffff +#define HWIO_GCC_SPARE0_REG_ATTR 0x3 +#define HWIO_GCC_SPARE0_REG_IN \ + in_dword_masked(HWIO_GCC_SPARE0_REG_ADDR, HWIO_GCC_SPARE0_REG_RMSK) +#define HWIO_GCC_SPARE0_REG_INM(m) \ + in_dword_masked(HWIO_GCC_SPARE0_REG_ADDR, m) +#define HWIO_GCC_SPARE0_REG_OUT(v) \ + out_dword(HWIO_GCC_SPARE0_REG_ADDR,v) +#define HWIO_GCC_SPARE0_REG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPARE0_REG_ADDR,m,v,HWIO_GCC_SPARE0_REG_IN) +#define HWIO_GCC_SPARE0_REG_SPARE_BITS_BMSK 0xffffffff +#define HWIO_GCC_SPARE0_REG_SPARE_BITS_SHFT 0x0 + +#define HWIO_GCC_SPARE1_REG_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005e000) +#define HWIO_GCC_SPARE1_REG_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005e000) +#define HWIO_GCC_SPARE1_REG_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005e000) +#define HWIO_GCC_SPARE1_REG_RMSK 0xffffffff +#define HWIO_GCC_SPARE1_REG_ATTR 0x3 +#define HWIO_GCC_SPARE1_REG_IN \ + in_dword_masked(HWIO_GCC_SPARE1_REG_ADDR, HWIO_GCC_SPARE1_REG_RMSK) +#define HWIO_GCC_SPARE1_REG_INM(m) \ + in_dword_masked(HWIO_GCC_SPARE1_REG_ADDR, m) +#define HWIO_GCC_SPARE1_REG_OUT(v) \ + out_dword(HWIO_GCC_SPARE1_REG_ADDR,v) +#define HWIO_GCC_SPARE1_REG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPARE1_REG_ADDR,m,v,HWIO_GCC_SPARE1_REG_IN) +#define HWIO_GCC_SPARE1_REG_SPARE_BITS_BMSK 0xffffffff +#define HWIO_GCC_SPARE1_REG_SPARE_BITS_SHFT 0x0 + +#define HWIO_GCC_SPARE2_REG_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00071000) +#define HWIO_GCC_SPARE2_REG_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00071000) +#define HWIO_GCC_SPARE2_REG_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00071000) +#define HWIO_GCC_SPARE2_REG_RMSK 0xffffffff +#define HWIO_GCC_SPARE2_REG_ATTR 0x3 +#define HWIO_GCC_SPARE2_REG_IN \ + in_dword_masked(HWIO_GCC_SPARE2_REG_ADDR, HWIO_GCC_SPARE2_REG_RMSK) +#define HWIO_GCC_SPARE2_REG_INM(m) \ + in_dword_masked(HWIO_GCC_SPARE2_REG_ADDR, m) +#define HWIO_GCC_SPARE2_REG_OUT(v) \ + out_dword(HWIO_GCC_SPARE2_REG_ADDR,v) +#define HWIO_GCC_SPARE2_REG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPARE2_REG_ADDR,m,v,HWIO_GCC_SPARE2_REG_IN) +#define HWIO_GCC_SPARE2_REG_SPARE_BITS_BMSK 0xffffffff +#define HWIO_GCC_SPARE2_REG_SPARE_BITS_SHFT 0x0 + +#define HWIO_GCC_SPARE3_REG_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00032000) +#define HWIO_GCC_SPARE3_REG_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00032000) +#define HWIO_GCC_SPARE3_REG_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00032000) +#define HWIO_GCC_SPARE3_REG_RMSK 0xffffffff +#define HWIO_GCC_SPARE3_REG_ATTR 0x3 +#define HWIO_GCC_SPARE3_REG_IN \ + in_dword_masked(HWIO_GCC_SPARE3_REG_ADDR, HWIO_GCC_SPARE3_REG_RMSK) +#define HWIO_GCC_SPARE3_REG_INM(m) \ + in_dword_masked(HWIO_GCC_SPARE3_REG_ADDR, m) +#define HWIO_GCC_SPARE3_REG_OUT(v) \ + out_dword(HWIO_GCC_SPARE3_REG_ADDR,v) +#define HWIO_GCC_SPARE3_REG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPARE3_REG_ADDR,m,v,HWIO_GCC_SPARE3_REG_IN) +#define HWIO_GCC_SPARE3_REG_SPARE_BITS_BMSK 0xffffffff +#define HWIO_GCC_SPARE3_REG_SPARE_BITS_SHFT 0x0 + +#define HWIO_GCC_SPARE4_REG_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00003000) +#define HWIO_GCC_SPARE4_REG_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00003000) +#define HWIO_GCC_SPARE4_REG_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00003000) +#define HWIO_GCC_SPARE4_REG_RMSK 0xffffffff +#define HWIO_GCC_SPARE4_REG_ATTR 0x3 +#define HWIO_GCC_SPARE4_REG_IN \ + in_dword_masked(HWIO_GCC_SPARE4_REG_ADDR, HWIO_GCC_SPARE4_REG_RMSK) +#define HWIO_GCC_SPARE4_REG_INM(m) \ + in_dword_masked(HWIO_GCC_SPARE4_REG_ADDR, m) +#define HWIO_GCC_SPARE4_REG_OUT(v) \ + out_dword(HWIO_GCC_SPARE4_REG_ADDR,v) +#define HWIO_GCC_SPARE4_REG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPARE4_REG_ADDR,m,v,HWIO_GCC_SPARE4_REG_IN) +#define HWIO_GCC_SPARE4_REG_SPARE_BITS_BMSK 0xffffffff +#define HWIO_GCC_SPARE4_REG_SPARE_BITS_SHFT 0x0 + +#define HWIO_GCC_SPARE5_REG_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002e000) +#define HWIO_GCC_SPARE5_REG_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002e000) +#define HWIO_GCC_SPARE5_REG_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002e000) +#define HWIO_GCC_SPARE5_REG_RMSK 0xffffffff +#define HWIO_GCC_SPARE5_REG_ATTR 0x3 +#define HWIO_GCC_SPARE5_REG_IN \ + in_dword_masked(HWIO_GCC_SPARE5_REG_ADDR, HWIO_GCC_SPARE5_REG_RMSK) +#define HWIO_GCC_SPARE5_REG_INM(m) \ + in_dword_masked(HWIO_GCC_SPARE5_REG_ADDR, m) +#define HWIO_GCC_SPARE5_REG_OUT(v) \ + out_dword(HWIO_GCC_SPARE5_REG_ADDR,v) +#define HWIO_GCC_SPARE5_REG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPARE5_REG_ADDR,m,v,HWIO_GCC_SPARE5_REG_IN) +#define HWIO_GCC_SPARE5_REG_SPARE_BITS_BMSK 0xffffffff +#define HWIO_GCC_SPARE5_REG_SPARE_BITS_SHFT 0x0 + +#define HWIO_GCC_GPU_MISC_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00061028) +#define HWIO_GCC_GPU_MISC_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00061028) +#define HWIO_GCC_GPU_MISC_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00061028) +#define HWIO_GCC_GPU_MISC_RMSK 0x3 +#define HWIO_GCC_GPU_MISC_ATTR 0x3 +#define HWIO_GCC_GPU_MISC_IN \ + in_dword_masked(HWIO_GCC_GPU_MISC_ADDR, HWIO_GCC_GPU_MISC_RMSK) +#define HWIO_GCC_GPU_MISC_INM(m) \ + in_dword_masked(HWIO_GCC_GPU_MISC_ADDR, m) +#define HWIO_GCC_GPU_MISC_OUT(v) \ + out_dword(HWIO_GCC_GPU_MISC_ADDR,v) +#define HWIO_GCC_GPU_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPU_MISC_ADDR,m,v,HWIO_GCC_GPU_MISC_IN) +#define HWIO_GCC_GPU_MISC_GPLL0_SRC_DISABLE_BMSK 0x2 +#define HWIO_GCC_GPU_MISC_GPLL0_SRC_DISABLE_SHFT 0x1 +#define HWIO_GCC_GPU_MISC_GPLL0_SRC_DISABLE_ENABLE_FVAL 0x0 +#define HWIO_GCC_GPU_MISC_GPLL0_SRC_DISABLE_DISABLE_FVAL 0x1 +#define HWIO_GCC_GPU_MISC_GPLL0_DIV_SRC_DISABLE_BMSK 0x1 +#define HWIO_GCC_GPU_MISC_GPLL0_DIV_SRC_DISABLE_SHFT 0x0 +#define HWIO_GCC_GPU_MISC_GPLL0_DIV_SRC_DISABLE_ENABLE_FVAL 0x0 +#define HWIO_GCC_GPU_MISC_GPLL0_DIV_SRC_DISABLE_DISABLE_FVAL 0x1 + +#define HWIO_GCC_TME_MISC_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00024114) +#define HWIO_GCC_TME_MISC_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00024114) +#define HWIO_GCC_TME_MISC_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00024114) +#define HWIO_GCC_TME_MISC_RMSK 0x2 +#define HWIO_GCC_TME_MISC_ATTR 0x3 +#define HWIO_GCC_TME_MISC_IN \ + in_dword_masked(HWIO_GCC_TME_MISC_ADDR, HWIO_GCC_TME_MISC_RMSK) +#define HWIO_GCC_TME_MISC_INM(m) \ + in_dword_masked(HWIO_GCC_TME_MISC_ADDR, m) +#define HWIO_GCC_TME_MISC_OUT(v) \ + out_dword(HWIO_GCC_TME_MISC_ADDR,v) +#define HWIO_GCC_TME_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TME_MISC_ADDR,m,v,HWIO_GCC_TME_MISC_IN) +#define HWIO_GCC_TME_MISC_GPLL0_SRC_DISABLE_BMSK 0x2 +#define HWIO_GCC_TME_MISC_GPLL0_SRC_DISABLE_SHFT 0x1 +#define HWIO_GCC_TME_MISC_GPLL0_SRC_DISABLE_ENABLE_FVAL 0x0 +#define HWIO_GCC_TME_MISC_GPLL0_SRC_DISABLE_DISABLE_FVAL 0x1 + +#define HWIO_GCC_DDRSS_MISC_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00034428) +#define HWIO_GCC_DDRSS_MISC_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00034428) +#define HWIO_GCC_DDRSS_MISC_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00034428) +#define HWIO_GCC_DDRSS_MISC_RMSK 0x2 +#define HWIO_GCC_DDRSS_MISC_ATTR 0x3 +#define HWIO_GCC_DDRSS_MISC_IN \ + in_dword_masked(HWIO_GCC_DDRSS_MISC_ADDR, HWIO_GCC_DDRSS_MISC_RMSK) +#define HWIO_GCC_DDRSS_MISC_INM(m) \ + in_dword_masked(HWIO_GCC_DDRSS_MISC_ADDR, m) +#define HWIO_GCC_DDRSS_MISC_OUT(v) \ + out_dword(HWIO_GCC_DDRSS_MISC_ADDR,v) +#define HWIO_GCC_DDRSS_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DDRSS_MISC_ADDR,m,v,HWIO_GCC_DDRSS_MISC_IN) +#define HWIO_GCC_DDRSS_MISC_GPLL0_SRC_DISABLE_BMSK 0x2 +#define HWIO_GCC_DDRSS_MISC_GPLL0_SRC_DISABLE_SHFT 0x1 +#define HWIO_GCC_DDRSS_MISC_GPLL0_SRC_DISABLE_ENABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_MISC_GPLL0_SRC_DISABLE_DISABLE_FVAL 0x1 + +#define HWIO_GCC_DDRSS_MC_MISC_STATUS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003442c) +#define HWIO_GCC_DDRSS_MC_MISC_STATUS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003442c) +#define HWIO_GCC_DDRSS_MC_MISC_STATUS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003442c) +#define HWIO_GCC_DDRSS_MC_MISC_STATUS_RMSK 0xe +#define HWIO_GCC_DDRSS_MC_MISC_STATUS_ATTR 0x1 +#define HWIO_GCC_DDRSS_MC_MISC_STATUS_IN \ + in_dword_masked(HWIO_GCC_DDRSS_MC_MISC_STATUS_ADDR, HWIO_GCC_DDRSS_MC_MISC_STATUS_RMSK) +#define HWIO_GCC_DDRSS_MC_MISC_STATUS_INM(m) \ + in_dword_masked(HWIO_GCC_DDRSS_MC_MISC_STATUS_ADDR, m) +#define HWIO_GCC_DDRSS_MC_MISC_STATUS_STALL_COMPLETE_BMSK 0x8 +#define HWIO_GCC_DDRSS_MC_MISC_STATUS_STALL_COMPLETE_SHFT 0x3 +#define HWIO_GCC_DDRSS_MC_MISC_STATUS_STALL_COMPLETE_ENABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_MC_MISC_STATUS_STALL_COMPLETE_DISABLE_FVAL 0x1 +#define HWIO_GCC_DDRSS_MC_MISC_STATUS_UNSTALL_BMSK 0x4 +#define HWIO_GCC_DDRSS_MC_MISC_STATUS_UNSTALL_SHFT 0x2 +#define HWIO_GCC_DDRSS_MC_MISC_STATUS_UNSTALL_ENABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_MC_MISC_STATUS_UNSTALL_DISABLE_FVAL 0x1 +#define HWIO_GCC_DDRSS_MC_MISC_STATUS_STALL_REQ_BMSK 0x2 +#define HWIO_GCC_DDRSS_MC_MISC_STATUS_STALL_REQ_SHFT 0x1 +#define HWIO_GCC_DDRSS_MC_MISC_STATUS_STALL_REQ_ENABLE_FVAL 0x0 +#define HWIO_GCC_DDRSS_MC_MISC_STATUS_STALL_REQ_DISABLE_FVAL 0x1 + +#define HWIO_GCC_TZ_VOTE_GPU_SMMU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006b000) +#define HWIO_GCC_TZ_VOTE_GPU_SMMU_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006b000) +#define HWIO_GCC_TZ_VOTE_GPU_SMMU_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006b000) +#define HWIO_GCC_TZ_VOTE_GPU_SMMU_CLK_RMSK 0x80000001 +#define HWIO_GCC_TZ_VOTE_GPU_SMMU_CLK_ATTR 0x3 +#define HWIO_GCC_TZ_VOTE_GPU_SMMU_CLK_IN \ + in_dword_masked(HWIO_GCC_TZ_VOTE_GPU_SMMU_CLK_ADDR, HWIO_GCC_TZ_VOTE_GPU_SMMU_CLK_RMSK) +#define HWIO_GCC_TZ_VOTE_GPU_SMMU_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_TZ_VOTE_GPU_SMMU_CLK_ADDR, m) +#define HWIO_GCC_TZ_VOTE_GPU_SMMU_CLK_OUT(v) \ + out_dword(HWIO_GCC_TZ_VOTE_GPU_SMMU_CLK_ADDR,v) +#define HWIO_GCC_TZ_VOTE_GPU_SMMU_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TZ_VOTE_GPU_SMMU_CLK_ADDR,m,v,HWIO_GCC_TZ_VOTE_GPU_SMMU_CLK_IN) +#define HWIO_GCC_TZ_VOTE_GPU_SMMU_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TZ_VOTE_GPU_SMMU_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TZ_VOTE_GPU_SMMU_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_TZ_VOTE_GPU_SMMU_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_TZ_VOTE_GPU_SMMU_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TZ_VOTE_GPU_SMMU_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TZ_VOTE_LPASS_QTB_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006b004) +#define HWIO_GCC_TZ_VOTE_LPASS_QTB_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006b004) +#define HWIO_GCC_TZ_VOTE_LPASS_QTB_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006b004) +#define HWIO_GCC_TZ_VOTE_LPASS_QTB_CLK_RMSK 0x80000001 +#define HWIO_GCC_TZ_VOTE_LPASS_QTB_CLK_ATTR 0x3 +#define HWIO_GCC_TZ_VOTE_LPASS_QTB_CLK_IN \ + in_dword_masked(HWIO_GCC_TZ_VOTE_LPASS_QTB_CLK_ADDR, HWIO_GCC_TZ_VOTE_LPASS_QTB_CLK_RMSK) +#define HWIO_GCC_TZ_VOTE_LPASS_QTB_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_TZ_VOTE_LPASS_QTB_CLK_ADDR, m) +#define HWIO_GCC_TZ_VOTE_LPASS_QTB_CLK_OUT(v) \ + out_dword(HWIO_GCC_TZ_VOTE_LPASS_QTB_CLK_ADDR,v) +#define HWIO_GCC_TZ_VOTE_LPASS_QTB_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TZ_VOTE_LPASS_QTB_CLK_ADDR,m,v,HWIO_GCC_TZ_VOTE_LPASS_QTB_CLK_IN) +#define HWIO_GCC_TZ_VOTE_LPASS_QTB_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TZ_VOTE_LPASS_QTB_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TZ_VOTE_LPASS_QTB_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_TZ_VOTE_LPASS_QTB_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_TZ_VOTE_LPASS_QTB_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TZ_VOTE_LPASS_QTB_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB1_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006b008) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB1_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006b008) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB1_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006b008) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB1_CLK_RMSK 0x80000001 +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB1_CLK_ATTR 0x3 +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB1_CLK_IN \ + in_dword_masked(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB1_CLK_ADDR, HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB1_CLK_RMSK) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB1_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB1_CLK_ADDR, m) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB1_CLK_OUT(v) \ + out_dword(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB1_CLK_ADDR,v) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB1_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB1_CLK_ADDR,m,v,HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB1_CLK_IN) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB1_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB1_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB1_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB1_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB1_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB1_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB2_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006b00c) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB2_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006b00c) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB2_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006b00c) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB2_CLK_RMSK 0x80000001 +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB2_CLK_ATTR 0x3 +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB2_CLK_IN \ + in_dword_masked(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB2_CLK_ADDR, HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB2_CLK_RMSK) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB2_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB2_CLK_ADDR, m) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB2_CLK_OUT(v) \ + out_dword(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB2_CLK_ADDR,v) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB2_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB2_CLK_ADDR,m,v,HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB2_CLK_IN) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB2_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB2_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB2_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB2_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB2_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB2_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006b010) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006b010) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006b010) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_RMSK 0x80000001 +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_ATTR 0x3 +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_IN \ + in_dword_masked(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_ADDR, HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_RMSK) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_ADDR, m) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_OUT(v) \ + out_dword(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_ADDR,v) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_ADDR,m,v,HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_IN) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_SF_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006b014) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_SF_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006b014) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_SF_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006b014) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_SF_CLK_RMSK 0x80000001 +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_SF_CLK_ATTR 0x3 +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_SF_CLK_IN \ + in_dword_masked(HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_SF_CLK_ADDR, HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_SF_CLK_RMSK) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_SF_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_SF_CLK_ADDR, m) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_SF_CLK_OUT(v) \ + out_dword(HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_SF_CLK_ADDR,v) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_SF_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_SF_CLK_ADDR,m,v,HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_SF_CLK_IN) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_SF_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_SF_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_SF_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_SF_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_SF_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_SF_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF01_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006b018) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF01_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006b018) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF01_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006b018) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF01_CLK_RMSK 0x80000001 +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF01_CLK_ATTR 0x3 +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF01_CLK_IN \ + in_dword_masked(HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF01_CLK_ADDR, HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF01_CLK_RMSK) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF01_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF01_CLK_ADDR, m) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF01_CLK_OUT(v) \ + out_dword(HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF01_CLK_ADDR,v) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF01_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF01_CLK_ADDR,m,v,HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF01_CLK_IN) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF01_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF01_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF01_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF01_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF01_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF01_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TZ_VOTE_TURING_MMU_QTB0_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006b020) +#define HWIO_GCC_TZ_VOTE_TURING_MMU_QTB0_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006b020) +#define HWIO_GCC_TZ_VOTE_TURING_MMU_QTB0_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006b020) +#define HWIO_GCC_TZ_VOTE_TURING_MMU_QTB0_CLK_RMSK 0x80000001 +#define HWIO_GCC_TZ_VOTE_TURING_MMU_QTB0_CLK_ATTR 0x3 +#define HWIO_GCC_TZ_VOTE_TURING_MMU_QTB0_CLK_IN \ + in_dword_masked(HWIO_GCC_TZ_VOTE_TURING_MMU_QTB0_CLK_ADDR, HWIO_GCC_TZ_VOTE_TURING_MMU_QTB0_CLK_RMSK) +#define HWIO_GCC_TZ_VOTE_TURING_MMU_QTB0_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_TZ_VOTE_TURING_MMU_QTB0_CLK_ADDR, m) +#define HWIO_GCC_TZ_VOTE_TURING_MMU_QTB0_CLK_OUT(v) \ + out_dword(HWIO_GCC_TZ_VOTE_TURING_MMU_QTB0_CLK_ADDR,v) +#define HWIO_GCC_TZ_VOTE_TURING_MMU_QTB0_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TZ_VOTE_TURING_MMU_QTB0_CLK_ADDR,m,v,HWIO_GCC_TZ_VOTE_TURING_MMU_QTB0_CLK_IN) +#define HWIO_GCC_TZ_VOTE_TURING_MMU_QTB0_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TZ_VOTE_TURING_MMU_QTB0_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TZ_VOTE_TURING_MMU_QTB0_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_TZ_VOTE_TURING_MMU_QTB0_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_TZ_VOTE_TURING_MMU_QTB0_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TZ_VOTE_TURING_MMU_QTB0_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006b028) +#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006b028) +#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006b028) +#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_RMSK 0x80000001 +#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_ATTR 0x3 +#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_IN \ + in_dword_masked(HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_ADDR, HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_RMSK) +#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_ADDR, m) +#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_OUT(v) \ + out_dword(HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_ADDR,v) +#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_ADDR,m,v,HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_IN) +#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006b02c) +#define HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006b02c) +#define HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006b02c) +#define HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_RMSK 0x80000001 +#define HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_ATTR 0x3 +#define HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_IN \ + in_dword_masked(HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_ADDR, HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_RMSK) +#define HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_ADDR, m) +#define HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_OUT(v) \ + out_dword(HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_ADDR,v) +#define HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_ADDR,m,v,HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_IN) +#define HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TZ_VOTE_GPU_SMMU_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006b03c) +#define HWIO_GCC_TZ_VOTE_GPU_SMMU_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006b03c) +#define HWIO_GCC_TZ_VOTE_GPU_SMMU_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006b03c) +#define HWIO_GCC_TZ_VOTE_GPU_SMMU_GDS_RMSK 0x80000001 +#define HWIO_GCC_TZ_VOTE_GPU_SMMU_GDS_ATTR 0x3 +#define HWIO_GCC_TZ_VOTE_GPU_SMMU_GDS_IN \ + in_dword_masked(HWIO_GCC_TZ_VOTE_GPU_SMMU_GDS_ADDR, HWIO_GCC_TZ_VOTE_GPU_SMMU_GDS_RMSK) +#define HWIO_GCC_TZ_VOTE_GPU_SMMU_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_TZ_VOTE_GPU_SMMU_GDS_ADDR, m) +#define HWIO_GCC_TZ_VOTE_GPU_SMMU_GDS_OUT(v) \ + out_dword(HWIO_GCC_TZ_VOTE_GPU_SMMU_GDS_ADDR,v) +#define HWIO_GCC_TZ_VOTE_GPU_SMMU_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TZ_VOTE_GPU_SMMU_GDS_ADDR,m,v,HWIO_GCC_TZ_VOTE_GPU_SMMU_GDS_IN) +#define HWIO_GCC_TZ_VOTE_GPU_SMMU_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_TZ_VOTE_GPU_SMMU_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_TZ_VOTE_GPU_SMMU_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_TZ_VOTE_GPU_SMMU_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_TZ_VOTE_GPU_SMMU_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TZ_VOTE_GPU_SMMU_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TZ_VOTE_LPASS_QTB_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006b040) +#define HWIO_GCC_TZ_VOTE_LPASS_QTB_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006b040) +#define HWIO_GCC_TZ_VOTE_LPASS_QTB_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006b040) +#define HWIO_GCC_TZ_VOTE_LPASS_QTB_GDS_RMSK 0x80000001 +#define HWIO_GCC_TZ_VOTE_LPASS_QTB_GDS_ATTR 0x3 +#define HWIO_GCC_TZ_VOTE_LPASS_QTB_GDS_IN \ + in_dword_masked(HWIO_GCC_TZ_VOTE_LPASS_QTB_GDS_ADDR, HWIO_GCC_TZ_VOTE_LPASS_QTB_GDS_RMSK) +#define HWIO_GCC_TZ_VOTE_LPASS_QTB_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_TZ_VOTE_LPASS_QTB_GDS_ADDR, m) +#define HWIO_GCC_TZ_VOTE_LPASS_QTB_GDS_OUT(v) \ + out_dword(HWIO_GCC_TZ_VOTE_LPASS_QTB_GDS_ADDR,v) +#define HWIO_GCC_TZ_VOTE_LPASS_QTB_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TZ_VOTE_LPASS_QTB_GDS_ADDR,m,v,HWIO_GCC_TZ_VOTE_LPASS_QTB_GDS_IN) +#define HWIO_GCC_TZ_VOTE_LPASS_QTB_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_TZ_VOTE_LPASS_QTB_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_TZ_VOTE_LPASS_QTB_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_TZ_VOTE_LPASS_QTB_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_TZ_VOTE_LPASS_QTB_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TZ_VOTE_LPASS_QTB_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB1_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006b044) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB1_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006b044) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB1_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006b044) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB1_GDS_RMSK 0x80000001 +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB1_GDS_ATTR 0x3 +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB1_GDS_IN \ + in_dword_masked(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB1_GDS_ADDR, HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB1_GDS_RMSK) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB1_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB1_GDS_ADDR, m) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB1_GDS_OUT(v) \ + out_dword(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB1_GDS_ADDR,v) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB1_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB1_GDS_ADDR,m,v,HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB1_GDS_IN) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB1_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB1_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB1_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB1_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB1_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB1_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB2_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006b048) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB2_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006b048) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB2_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006b048) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB2_GDS_RMSK 0x80000001 +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB2_GDS_ATTR 0x3 +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB2_GDS_IN \ + in_dword_masked(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB2_GDS_ADDR, HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB2_GDS_RMSK) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB2_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB2_GDS_ADDR, m) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB2_GDS_OUT(v) \ + out_dword(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB2_GDS_ADDR,v) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB2_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB2_GDS_ADDR,m,v,HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB2_GDS_IN) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB2_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB2_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB2_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB2_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB2_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB2_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006b04c) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006b04c) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006b04c) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_RMSK 0x80000001 +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_ATTR 0x3 +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_IN \ + in_dword_masked(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_ADDR, HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_RMSK) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_ADDR, m) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_OUT(v) \ + out_dword(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_ADDR,v) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_ADDR,m,v,HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_IN) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF01_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006b050) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF01_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006b050) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF01_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006b050) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF01_GDS_RMSK 0x80000001 +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF01_GDS_ATTR 0x3 +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF01_GDS_IN \ + in_dword_masked(HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF01_GDS_ADDR, HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF01_GDS_RMSK) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF01_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF01_GDS_ADDR, m) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF01_GDS_OUT(v) \ + out_dword(HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF01_GDS_ADDR,v) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF01_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF01_GDS_ADDR,m,v,HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF01_GDS_IN) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF01_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF01_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF01_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF01_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF01_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF01_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_SF_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006b054) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_SF_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006b054) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_SF_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006b054) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_SF_GDS_RMSK 0x80000001 +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_SF_GDS_ATTR 0x3 +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_SF_GDS_IN \ + in_dword_masked(HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_SF_GDS_ADDR, HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_SF_GDS_RMSK) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_SF_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_SF_GDS_ADDR, m) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_SF_GDS_OUT(v) \ + out_dword(HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_SF_GDS_ADDR,v) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_SF_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_SF_GDS_ADDR,m,v,HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_SF_GDS_IN) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_SF_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_SF_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_SF_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_SF_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_SF_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_SF_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TZ_VOTE_TURING_MMU_QTB0_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006b05c) +#define HWIO_GCC_TZ_VOTE_TURING_MMU_QTB0_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006b05c) +#define HWIO_GCC_TZ_VOTE_TURING_MMU_QTB0_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006b05c) +#define HWIO_GCC_TZ_VOTE_TURING_MMU_QTB0_GDS_RMSK 0x80000001 +#define HWIO_GCC_TZ_VOTE_TURING_MMU_QTB0_GDS_ATTR 0x3 +#define HWIO_GCC_TZ_VOTE_TURING_MMU_QTB0_GDS_IN \ + in_dword_masked(HWIO_GCC_TZ_VOTE_TURING_MMU_QTB0_GDS_ADDR, HWIO_GCC_TZ_VOTE_TURING_MMU_QTB0_GDS_RMSK) +#define HWIO_GCC_TZ_VOTE_TURING_MMU_QTB0_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_TZ_VOTE_TURING_MMU_QTB0_GDS_ADDR, m) +#define HWIO_GCC_TZ_VOTE_TURING_MMU_QTB0_GDS_OUT(v) \ + out_dword(HWIO_GCC_TZ_VOTE_TURING_MMU_QTB0_GDS_ADDR,v) +#define HWIO_GCC_TZ_VOTE_TURING_MMU_QTB0_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TZ_VOTE_TURING_MMU_QTB0_GDS_ADDR,m,v,HWIO_GCC_TZ_VOTE_TURING_MMU_QTB0_GDS_IN) +#define HWIO_GCC_TZ_VOTE_TURING_MMU_QTB0_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_TZ_VOTE_TURING_MMU_QTB0_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_TZ_VOTE_TURING_MMU_QTB0_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_TZ_VOTE_TURING_MMU_QTB0_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_TZ_VOTE_TURING_MMU_QTB0_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TZ_VOTE_TURING_MMU_QTB0_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006b064) +#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006b064) +#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006b064) +#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_GDS_RMSK 0x80000001 +#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_GDS_ATTR 0x3 +#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_GDS_IN \ + in_dword_masked(HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_GDS_ADDR, HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_GDS_RMSK) +#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_GDS_ADDR, m) +#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_GDS_OUT(v) \ + out_dword(HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_GDS_ADDR,v) +#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_GDS_ADDR,m,v,HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_GDS_IN) +#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TZ_VOTE_MMU_TCU_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006b068) +#define HWIO_GCC_TZ_VOTE_MMU_TCU_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006b068) +#define HWIO_GCC_TZ_VOTE_MMU_TCU_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006b068) +#define HWIO_GCC_TZ_VOTE_MMU_TCU_GDS_RMSK 0x80000001 +#define HWIO_GCC_TZ_VOTE_MMU_TCU_GDS_ATTR 0x3 +#define HWIO_GCC_TZ_VOTE_MMU_TCU_GDS_IN \ + in_dword_masked(HWIO_GCC_TZ_VOTE_MMU_TCU_GDS_ADDR, HWIO_GCC_TZ_VOTE_MMU_TCU_GDS_RMSK) +#define HWIO_GCC_TZ_VOTE_MMU_TCU_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_TZ_VOTE_MMU_TCU_GDS_ADDR, m) +#define HWIO_GCC_TZ_VOTE_MMU_TCU_GDS_OUT(v) \ + out_dword(HWIO_GCC_TZ_VOTE_MMU_TCU_GDS_ADDR,v) +#define HWIO_GCC_TZ_VOTE_MMU_TCU_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TZ_VOTE_MMU_TCU_GDS_ADDR,m,v,HWIO_GCC_TZ_VOTE_MMU_TCU_GDS_IN) +#define HWIO_GCC_TZ_VOTE_MMU_TCU_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_TZ_VOTE_MMU_TCU_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_TZ_VOTE_MMU_TCU_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_TZ_VOTE_MMU_TCU_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_TZ_VOTE_MMU_TCU_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TZ_VOTE_MMU_TCU_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF23_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006b070) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF23_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006b070) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF23_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006b070) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF23_CLK_RMSK 0x80000001 +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF23_CLK_ATTR 0x3 +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF23_CLK_IN \ + in_dword_masked(HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF23_CLK_ADDR, HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF23_CLK_RMSK) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF23_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF23_CLK_ADDR, m) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF23_CLK_OUT(v) \ + out_dword(HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF23_CLK_ADDR,v) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF23_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF23_CLK_ADDR,m,v,HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF23_CLK_IN) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF23_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF23_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF23_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF23_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF23_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF23_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF23_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006b078) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF23_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006b078) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF23_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006b078) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF23_GDS_RMSK 0x80000001 +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF23_GDS_ATTR 0x3 +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF23_GDS_IN \ + in_dword_masked(HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF23_GDS_ADDR, HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF23_GDS_RMSK) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF23_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF23_GDS_ADDR, m) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF23_GDS_OUT(v) \ + out_dword(HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF23_GDS_ADDR,v) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF23_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF23_GDS_ADDR,m,v,HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF23_GDS_IN) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF23_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF23_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF23_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF23_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF23_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_QTB_HF23_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HYP_VOTE_GPU_SMMU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006c000) +#define HWIO_GCC_HYP_VOTE_GPU_SMMU_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006c000) +#define HWIO_GCC_HYP_VOTE_GPU_SMMU_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006c000) +#define HWIO_GCC_HYP_VOTE_GPU_SMMU_CLK_RMSK 0x80000001 +#define HWIO_GCC_HYP_VOTE_GPU_SMMU_CLK_ATTR 0x3 +#define HWIO_GCC_HYP_VOTE_GPU_SMMU_CLK_IN \ + in_dword_masked(HWIO_GCC_HYP_VOTE_GPU_SMMU_CLK_ADDR, HWIO_GCC_HYP_VOTE_GPU_SMMU_CLK_RMSK) +#define HWIO_GCC_HYP_VOTE_GPU_SMMU_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_HYP_VOTE_GPU_SMMU_CLK_ADDR, m) +#define HWIO_GCC_HYP_VOTE_GPU_SMMU_CLK_OUT(v) \ + out_dword(HWIO_GCC_HYP_VOTE_GPU_SMMU_CLK_ADDR,v) +#define HWIO_GCC_HYP_VOTE_GPU_SMMU_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HYP_VOTE_GPU_SMMU_CLK_ADDR,m,v,HWIO_GCC_HYP_VOTE_GPU_SMMU_CLK_IN) +#define HWIO_GCC_HYP_VOTE_GPU_SMMU_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_HYP_VOTE_GPU_SMMU_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_HYP_VOTE_GPU_SMMU_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_HYP_VOTE_GPU_SMMU_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_HYP_VOTE_GPU_SMMU_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_VOTE_GPU_SMMU_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HYP_VOTE_LPASS_QTB_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006c004) +#define HWIO_GCC_HYP_VOTE_LPASS_QTB_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006c004) +#define HWIO_GCC_HYP_VOTE_LPASS_QTB_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006c004) +#define HWIO_GCC_HYP_VOTE_LPASS_QTB_CLK_RMSK 0x80000001 +#define HWIO_GCC_HYP_VOTE_LPASS_QTB_CLK_ATTR 0x3 +#define HWIO_GCC_HYP_VOTE_LPASS_QTB_CLK_IN \ + in_dword_masked(HWIO_GCC_HYP_VOTE_LPASS_QTB_CLK_ADDR, HWIO_GCC_HYP_VOTE_LPASS_QTB_CLK_RMSK) +#define HWIO_GCC_HYP_VOTE_LPASS_QTB_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_HYP_VOTE_LPASS_QTB_CLK_ADDR, m) +#define HWIO_GCC_HYP_VOTE_LPASS_QTB_CLK_OUT(v) \ + out_dword(HWIO_GCC_HYP_VOTE_LPASS_QTB_CLK_ADDR,v) +#define HWIO_GCC_HYP_VOTE_LPASS_QTB_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HYP_VOTE_LPASS_QTB_CLK_ADDR,m,v,HWIO_GCC_HYP_VOTE_LPASS_QTB_CLK_IN) +#define HWIO_GCC_HYP_VOTE_LPASS_QTB_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_HYP_VOTE_LPASS_QTB_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_HYP_VOTE_LPASS_QTB_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_HYP_VOTE_LPASS_QTB_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_HYP_VOTE_LPASS_QTB_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_VOTE_LPASS_QTB_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006c008) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006c008) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006c008) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_RMSK 0x80000001 +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_ATTR 0x3 +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_IN \ + in_dword_masked(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_ADDR, HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_RMSK) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_ADDR, m) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_OUT(v) \ + out_dword(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_ADDR,v) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_ADDR,m,v,HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_IN) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006c00c) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006c00c) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006c00c) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_RMSK 0x80000001 +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_ATTR 0x3 +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_IN \ + in_dword_masked(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_ADDR, HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_RMSK) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_ADDR, m) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_OUT(v) \ + out_dword(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_ADDR,v) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_ADDR,m,v,HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_IN) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006c010) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006c010) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006c010) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_RMSK 0x80000001 +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_ATTR 0x3 +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_IN \ + in_dword_masked(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_ADDR, HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_RMSK) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_ADDR, m) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_OUT(v) \ + out_dword(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_ADDR,v) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_ADDR,m,v,HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_IN) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_SF_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006c014) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_SF_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006c014) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_SF_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006c014) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_SF_CLK_RMSK 0x80000001 +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_SF_CLK_ATTR 0x3 +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_SF_CLK_IN \ + in_dword_masked(HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_SF_CLK_ADDR, HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_SF_CLK_RMSK) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_SF_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_SF_CLK_ADDR, m) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_SF_CLK_OUT(v) \ + out_dword(HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_SF_CLK_ADDR,v) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_SF_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_SF_CLK_ADDR,m,v,HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_SF_CLK_IN) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_SF_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_SF_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_SF_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_SF_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_SF_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_SF_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF01_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006c018) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF01_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006c018) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF01_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006c018) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF01_CLK_RMSK 0x80000001 +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF01_CLK_ATTR 0x3 +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF01_CLK_IN \ + in_dword_masked(HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF01_CLK_ADDR, HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF01_CLK_RMSK) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF01_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF01_CLK_ADDR, m) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF01_CLK_OUT(v) \ + out_dword(HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF01_CLK_ADDR,v) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF01_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF01_CLK_ADDR,m,v,HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF01_CLK_IN) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF01_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF01_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF01_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF01_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF01_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF01_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HYP_VOTE_TURING_MMU_QTB0_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006c020) +#define HWIO_GCC_HYP_VOTE_TURING_MMU_QTB0_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006c020) +#define HWIO_GCC_HYP_VOTE_TURING_MMU_QTB0_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006c020) +#define HWIO_GCC_HYP_VOTE_TURING_MMU_QTB0_CLK_RMSK 0x80000001 +#define HWIO_GCC_HYP_VOTE_TURING_MMU_QTB0_CLK_ATTR 0x3 +#define HWIO_GCC_HYP_VOTE_TURING_MMU_QTB0_CLK_IN \ + in_dword_masked(HWIO_GCC_HYP_VOTE_TURING_MMU_QTB0_CLK_ADDR, HWIO_GCC_HYP_VOTE_TURING_MMU_QTB0_CLK_RMSK) +#define HWIO_GCC_HYP_VOTE_TURING_MMU_QTB0_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_HYP_VOTE_TURING_MMU_QTB0_CLK_ADDR, m) +#define HWIO_GCC_HYP_VOTE_TURING_MMU_QTB0_CLK_OUT(v) \ + out_dword(HWIO_GCC_HYP_VOTE_TURING_MMU_QTB0_CLK_ADDR,v) +#define HWIO_GCC_HYP_VOTE_TURING_MMU_QTB0_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HYP_VOTE_TURING_MMU_QTB0_CLK_ADDR,m,v,HWIO_GCC_HYP_VOTE_TURING_MMU_QTB0_CLK_IN) +#define HWIO_GCC_HYP_VOTE_TURING_MMU_QTB0_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_HYP_VOTE_TURING_MMU_QTB0_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_HYP_VOTE_TURING_MMU_QTB0_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_HYP_VOTE_TURING_MMU_QTB0_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_HYP_VOTE_TURING_MMU_QTB0_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_VOTE_TURING_MMU_QTB0_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006c028) +#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006c028) +#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006c028) +#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_RMSK 0x80000001 +#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_ATTR 0x3 +#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_IN \ + in_dword_masked(HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_ADDR, HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_RMSK) +#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_ADDR, m) +#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_OUT(v) \ + out_dword(HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_ADDR,v) +#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_ADDR,m,v,HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_IN) +#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006c02c) +#define HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006c02c) +#define HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006c02c) +#define HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_RMSK 0x80000001 +#define HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_ATTR 0x3 +#define HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_IN \ + in_dword_masked(HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_ADDR, HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_RMSK) +#define HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_ADDR, m) +#define HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_OUT(v) \ + out_dword(HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_ADDR,v) +#define HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_ADDR,m,v,HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_IN) +#define HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HYP_VOTE_GPU_SMMU_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006c03c) +#define HWIO_GCC_HYP_VOTE_GPU_SMMU_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006c03c) +#define HWIO_GCC_HYP_VOTE_GPU_SMMU_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006c03c) +#define HWIO_GCC_HYP_VOTE_GPU_SMMU_GDS_RMSK 0x80000001 +#define HWIO_GCC_HYP_VOTE_GPU_SMMU_GDS_ATTR 0x3 +#define HWIO_GCC_HYP_VOTE_GPU_SMMU_GDS_IN \ + in_dword_masked(HWIO_GCC_HYP_VOTE_GPU_SMMU_GDS_ADDR, HWIO_GCC_HYP_VOTE_GPU_SMMU_GDS_RMSK) +#define HWIO_GCC_HYP_VOTE_GPU_SMMU_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_HYP_VOTE_GPU_SMMU_GDS_ADDR, m) +#define HWIO_GCC_HYP_VOTE_GPU_SMMU_GDS_OUT(v) \ + out_dword(HWIO_GCC_HYP_VOTE_GPU_SMMU_GDS_ADDR,v) +#define HWIO_GCC_HYP_VOTE_GPU_SMMU_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HYP_VOTE_GPU_SMMU_GDS_ADDR,m,v,HWIO_GCC_HYP_VOTE_GPU_SMMU_GDS_IN) +#define HWIO_GCC_HYP_VOTE_GPU_SMMU_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_HYP_VOTE_GPU_SMMU_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_HYP_VOTE_GPU_SMMU_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_HYP_VOTE_GPU_SMMU_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_HYP_VOTE_GPU_SMMU_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_VOTE_GPU_SMMU_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HYP_VOTE_LPASS_QTB_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006c040) +#define HWIO_GCC_HYP_VOTE_LPASS_QTB_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006c040) +#define HWIO_GCC_HYP_VOTE_LPASS_QTB_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006c040) +#define HWIO_GCC_HYP_VOTE_LPASS_QTB_GDS_RMSK 0x80000001 +#define HWIO_GCC_HYP_VOTE_LPASS_QTB_GDS_ATTR 0x3 +#define HWIO_GCC_HYP_VOTE_LPASS_QTB_GDS_IN \ + in_dword_masked(HWIO_GCC_HYP_VOTE_LPASS_QTB_GDS_ADDR, HWIO_GCC_HYP_VOTE_LPASS_QTB_GDS_RMSK) +#define HWIO_GCC_HYP_VOTE_LPASS_QTB_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_HYP_VOTE_LPASS_QTB_GDS_ADDR, m) +#define HWIO_GCC_HYP_VOTE_LPASS_QTB_GDS_OUT(v) \ + out_dword(HWIO_GCC_HYP_VOTE_LPASS_QTB_GDS_ADDR,v) +#define HWIO_GCC_HYP_VOTE_LPASS_QTB_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HYP_VOTE_LPASS_QTB_GDS_ADDR,m,v,HWIO_GCC_HYP_VOTE_LPASS_QTB_GDS_IN) +#define HWIO_GCC_HYP_VOTE_LPASS_QTB_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_HYP_VOTE_LPASS_QTB_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_HYP_VOTE_LPASS_QTB_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_HYP_VOTE_LPASS_QTB_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_HYP_VOTE_LPASS_QTB_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_VOTE_LPASS_QTB_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006c044) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006c044) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006c044) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_RMSK 0x80000001 +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_ATTR 0x3 +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_IN \ + in_dword_masked(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_ADDR, HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_RMSK) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_ADDR, m) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_OUT(v) \ + out_dword(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_ADDR,v) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_ADDR,m,v,HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_IN) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006c048) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006c048) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006c048) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_RMSK 0x80000001 +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_ATTR 0x3 +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_IN \ + in_dword_masked(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_ADDR, HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_RMSK) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_ADDR, m) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_OUT(v) \ + out_dword(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_ADDR,v) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_ADDR,m,v,HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_IN) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006c04c) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006c04c) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006c04c) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_RMSK 0x80000001 +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_ATTR 0x3 +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_IN \ + in_dword_masked(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_ADDR, HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_RMSK) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_ADDR, m) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_OUT(v) \ + out_dword(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_ADDR,v) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_ADDR,m,v,HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_IN) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF01_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006c050) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF01_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006c050) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF01_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006c050) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF01_GDS_RMSK 0x80000001 +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF01_GDS_ATTR 0x3 +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF01_GDS_IN \ + in_dword_masked(HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF01_GDS_ADDR, HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF01_GDS_RMSK) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF01_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF01_GDS_ADDR, m) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF01_GDS_OUT(v) \ + out_dword(HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF01_GDS_ADDR,v) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF01_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF01_GDS_ADDR,m,v,HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF01_GDS_IN) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF01_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF01_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF01_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF01_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF01_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF01_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_SF_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006c054) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_SF_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006c054) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_SF_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006c054) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_SF_GDS_RMSK 0x80000001 +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_SF_GDS_ATTR 0x3 +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_SF_GDS_IN \ + in_dword_masked(HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_SF_GDS_ADDR, HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_SF_GDS_RMSK) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_SF_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_SF_GDS_ADDR, m) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_SF_GDS_OUT(v) \ + out_dword(HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_SF_GDS_ADDR,v) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_SF_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_SF_GDS_ADDR,m,v,HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_SF_GDS_IN) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_SF_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_SF_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_SF_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_SF_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_SF_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_SF_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HYP_VOTE_TURING_MMU_QTB0_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006c05c) +#define HWIO_GCC_HYP_VOTE_TURING_MMU_QTB0_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006c05c) +#define HWIO_GCC_HYP_VOTE_TURING_MMU_QTB0_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006c05c) +#define HWIO_GCC_HYP_VOTE_TURING_MMU_QTB0_GDS_RMSK 0x80000001 +#define HWIO_GCC_HYP_VOTE_TURING_MMU_QTB0_GDS_ATTR 0x3 +#define HWIO_GCC_HYP_VOTE_TURING_MMU_QTB0_GDS_IN \ + in_dword_masked(HWIO_GCC_HYP_VOTE_TURING_MMU_QTB0_GDS_ADDR, HWIO_GCC_HYP_VOTE_TURING_MMU_QTB0_GDS_RMSK) +#define HWIO_GCC_HYP_VOTE_TURING_MMU_QTB0_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_HYP_VOTE_TURING_MMU_QTB0_GDS_ADDR, m) +#define HWIO_GCC_HYP_VOTE_TURING_MMU_QTB0_GDS_OUT(v) \ + out_dword(HWIO_GCC_HYP_VOTE_TURING_MMU_QTB0_GDS_ADDR,v) +#define HWIO_GCC_HYP_VOTE_TURING_MMU_QTB0_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HYP_VOTE_TURING_MMU_QTB0_GDS_ADDR,m,v,HWIO_GCC_HYP_VOTE_TURING_MMU_QTB0_GDS_IN) +#define HWIO_GCC_HYP_VOTE_TURING_MMU_QTB0_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_HYP_VOTE_TURING_MMU_QTB0_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_HYP_VOTE_TURING_MMU_QTB0_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_HYP_VOTE_TURING_MMU_QTB0_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_HYP_VOTE_TURING_MMU_QTB0_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_VOTE_TURING_MMU_QTB0_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006c064) +#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006c064) +#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006c064) +#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_GDS_RMSK 0x80000001 +#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_GDS_ATTR 0x3 +#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_GDS_IN \ + in_dword_masked(HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_GDS_ADDR, HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_GDS_RMSK) +#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_GDS_ADDR, m) +#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_GDS_OUT(v) \ + out_dword(HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_GDS_ADDR,v) +#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_GDS_ADDR,m,v,HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_GDS_IN) +#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HYP_VOTE_MMU_TCU_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006c068) +#define HWIO_GCC_HYP_VOTE_MMU_TCU_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006c068) +#define HWIO_GCC_HYP_VOTE_MMU_TCU_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006c068) +#define HWIO_GCC_HYP_VOTE_MMU_TCU_GDS_RMSK 0x80000001 +#define HWIO_GCC_HYP_VOTE_MMU_TCU_GDS_ATTR 0x3 +#define HWIO_GCC_HYP_VOTE_MMU_TCU_GDS_IN \ + in_dword_masked(HWIO_GCC_HYP_VOTE_MMU_TCU_GDS_ADDR, HWIO_GCC_HYP_VOTE_MMU_TCU_GDS_RMSK) +#define HWIO_GCC_HYP_VOTE_MMU_TCU_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_HYP_VOTE_MMU_TCU_GDS_ADDR, m) +#define HWIO_GCC_HYP_VOTE_MMU_TCU_GDS_OUT(v) \ + out_dword(HWIO_GCC_HYP_VOTE_MMU_TCU_GDS_ADDR,v) +#define HWIO_GCC_HYP_VOTE_MMU_TCU_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HYP_VOTE_MMU_TCU_GDS_ADDR,m,v,HWIO_GCC_HYP_VOTE_MMU_TCU_GDS_IN) +#define HWIO_GCC_HYP_VOTE_MMU_TCU_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_HYP_VOTE_MMU_TCU_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_HYP_VOTE_MMU_TCU_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_HYP_VOTE_MMU_TCU_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_HYP_VOTE_MMU_TCU_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_VOTE_MMU_TCU_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF23_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006c070) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF23_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006c070) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF23_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006c070) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF23_CLK_RMSK 0x80000001 +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF23_CLK_ATTR 0x3 +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF23_CLK_IN \ + in_dword_masked(HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF23_CLK_ADDR, HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF23_CLK_RMSK) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF23_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF23_CLK_ADDR, m) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF23_CLK_OUT(v) \ + out_dword(HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF23_CLK_ADDR,v) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF23_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF23_CLK_ADDR,m,v,HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF23_CLK_IN) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF23_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF23_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF23_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF23_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF23_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF23_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF23_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006c078) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF23_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006c078) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF23_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006c078) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF23_GDS_RMSK 0x80000001 +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF23_GDS_ATTR 0x3 +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF23_GDS_IN \ + in_dword_masked(HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF23_GDS_ADDR, HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF23_GDS_RMSK) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF23_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF23_GDS_ADDR, m) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF23_GDS_OUT(v) \ + out_dword(HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF23_GDS_ADDR,v) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF23_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF23_GDS_ADDR,m,v,HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF23_GDS_IN) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF23_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF23_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF23_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF23_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF23_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_QTB_HF23_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HLOS1_VOTE_GPU_SMMU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006d000) +#define HWIO_GCC_HLOS1_VOTE_GPU_SMMU_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006d000) +#define HWIO_GCC_HLOS1_VOTE_GPU_SMMU_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006d000) +#define HWIO_GCC_HLOS1_VOTE_GPU_SMMU_CLK_RMSK 0x80000001 +#define HWIO_GCC_HLOS1_VOTE_GPU_SMMU_CLK_ATTR 0x3 +#define HWIO_GCC_HLOS1_VOTE_GPU_SMMU_CLK_IN \ + in_dword_masked(HWIO_GCC_HLOS1_VOTE_GPU_SMMU_CLK_ADDR, HWIO_GCC_HLOS1_VOTE_GPU_SMMU_CLK_RMSK) +#define HWIO_GCC_HLOS1_VOTE_GPU_SMMU_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_HLOS1_VOTE_GPU_SMMU_CLK_ADDR, m) +#define HWIO_GCC_HLOS1_VOTE_GPU_SMMU_CLK_OUT(v) \ + out_dword(HWIO_GCC_HLOS1_VOTE_GPU_SMMU_CLK_ADDR,v) +#define HWIO_GCC_HLOS1_VOTE_GPU_SMMU_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HLOS1_VOTE_GPU_SMMU_CLK_ADDR,m,v,HWIO_GCC_HLOS1_VOTE_GPU_SMMU_CLK_IN) +#define HWIO_GCC_HLOS1_VOTE_GPU_SMMU_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_HLOS1_VOTE_GPU_SMMU_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_HLOS1_VOTE_GPU_SMMU_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_HLOS1_VOTE_GPU_SMMU_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_HLOS1_VOTE_GPU_SMMU_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HLOS1_VOTE_GPU_SMMU_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HLOS1_VOTE_LPASS_QTB_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006d004) +#define HWIO_GCC_HLOS1_VOTE_LPASS_QTB_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006d004) +#define HWIO_GCC_HLOS1_VOTE_LPASS_QTB_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006d004) +#define HWIO_GCC_HLOS1_VOTE_LPASS_QTB_CLK_RMSK 0x80000001 +#define HWIO_GCC_HLOS1_VOTE_LPASS_QTB_CLK_ATTR 0x3 +#define HWIO_GCC_HLOS1_VOTE_LPASS_QTB_CLK_IN \ + in_dword_masked(HWIO_GCC_HLOS1_VOTE_LPASS_QTB_CLK_ADDR, HWIO_GCC_HLOS1_VOTE_LPASS_QTB_CLK_RMSK) +#define HWIO_GCC_HLOS1_VOTE_LPASS_QTB_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_HLOS1_VOTE_LPASS_QTB_CLK_ADDR, m) +#define HWIO_GCC_HLOS1_VOTE_LPASS_QTB_CLK_OUT(v) \ + out_dword(HWIO_GCC_HLOS1_VOTE_LPASS_QTB_CLK_ADDR,v) +#define HWIO_GCC_HLOS1_VOTE_LPASS_QTB_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HLOS1_VOTE_LPASS_QTB_CLK_ADDR,m,v,HWIO_GCC_HLOS1_VOTE_LPASS_QTB_CLK_IN) +#define HWIO_GCC_HLOS1_VOTE_LPASS_QTB_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_HLOS1_VOTE_LPASS_QTB_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_HLOS1_VOTE_LPASS_QTB_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_HLOS1_VOTE_LPASS_QTB_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_HLOS1_VOTE_LPASS_QTB_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HLOS1_VOTE_LPASS_QTB_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB1_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006d008) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB1_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006d008) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB1_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006d008) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB1_CLK_RMSK 0x80000001 +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB1_CLK_ATTR 0x3 +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB1_CLK_IN \ + in_dword_masked(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB1_CLK_ADDR, HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB1_CLK_RMSK) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB1_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB1_CLK_ADDR, m) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB1_CLK_OUT(v) \ + out_dword(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB1_CLK_ADDR,v) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB1_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB1_CLK_ADDR,m,v,HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB1_CLK_IN) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB1_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB1_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB1_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB1_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB1_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB1_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB2_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006d00c) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB2_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006d00c) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB2_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006d00c) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB2_CLK_RMSK 0x80000001 +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB2_CLK_ATTR 0x3 +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB2_CLK_IN \ + in_dword_masked(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB2_CLK_ADDR, HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB2_CLK_RMSK) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB2_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB2_CLK_ADDR, m) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB2_CLK_OUT(v) \ + out_dword(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB2_CLK_ADDR,v) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB2_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB2_CLK_ADDR,m,v,HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB2_CLK_IN) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB2_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB2_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB2_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB2_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB2_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB2_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006d010) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006d010) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006d010) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_RMSK 0x80000001 +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_ATTR 0x3 +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_IN \ + in_dword_masked(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_ADDR, HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_RMSK) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_ADDR, m) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_OUT(v) \ + out_dword(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_ADDR,v) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_ADDR,m,v,HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_IN) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_SF_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006d014) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_SF_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006d014) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_SF_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006d014) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_SF_CLK_RMSK 0x80000001 +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_SF_CLK_ATTR 0x3 +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_SF_CLK_IN \ + in_dword_masked(HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_SF_CLK_ADDR, HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_SF_CLK_RMSK) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_SF_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_SF_CLK_ADDR, m) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_SF_CLK_OUT(v) \ + out_dword(HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_SF_CLK_ADDR,v) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_SF_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_SF_CLK_ADDR,m,v,HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_SF_CLK_IN) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_SF_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_SF_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_SF_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_SF_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_SF_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_SF_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF01_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006d018) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF01_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006d018) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF01_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006d018) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF01_CLK_RMSK 0x80000001 +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF01_CLK_ATTR 0x3 +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF01_CLK_IN \ + in_dword_masked(HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF01_CLK_ADDR, HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF01_CLK_RMSK) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF01_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF01_CLK_ADDR, m) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF01_CLK_OUT(v) \ + out_dword(HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF01_CLK_ADDR,v) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF01_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF01_CLK_ADDR,m,v,HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF01_CLK_IN) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF01_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF01_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF01_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF01_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF01_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF01_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_QTB0_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006d020) +#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_QTB0_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006d020) +#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_QTB0_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006d020) +#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_QTB0_CLK_RMSK 0x80000001 +#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_QTB0_CLK_ATTR 0x3 +#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_QTB0_CLK_IN \ + in_dword_masked(HWIO_GCC_HLOS1_VOTE_TURING_MMU_QTB0_CLK_ADDR, HWIO_GCC_HLOS1_VOTE_TURING_MMU_QTB0_CLK_RMSK) +#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_QTB0_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_HLOS1_VOTE_TURING_MMU_QTB0_CLK_ADDR, m) +#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_QTB0_CLK_OUT(v) \ + out_dword(HWIO_GCC_HLOS1_VOTE_TURING_MMU_QTB0_CLK_ADDR,v) +#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_QTB0_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HLOS1_VOTE_TURING_MMU_QTB0_CLK_ADDR,m,v,HWIO_GCC_HLOS1_VOTE_TURING_MMU_QTB0_CLK_IN) +#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_QTB0_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_QTB0_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_QTB0_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_QTB0_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_QTB0_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_QTB0_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006d028) +#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006d028) +#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006d028) +#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_RMSK 0x80000001 +#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_ATTR 0x3 +#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_IN \ + in_dword_masked(HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_ADDR, HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_RMSK) +#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_ADDR, m) +#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_OUT(v) \ + out_dword(HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_ADDR,v) +#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_ADDR,m,v,HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_IN) +#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006d02c) +#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006d02c) +#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006d02c) +#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_RMSK 0x80000001 +#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_ATTR 0x3 +#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_IN \ + in_dword_masked(HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_ADDR, HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_RMSK) +#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_ADDR, m) +#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_OUT(v) \ + out_dword(HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_ADDR,v) +#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_ADDR,m,v,HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_IN) +#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HLOS1_VOTE_GPU_SMMU_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006d03c) +#define HWIO_GCC_HLOS1_VOTE_GPU_SMMU_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006d03c) +#define HWIO_GCC_HLOS1_VOTE_GPU_SMMU_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006d03c) +#define HWIO_GCC_HLOS1_VOTE_GPU_SMMU_GDS_RMSK 0x80000001 +#define HWIO_GCC_HLOS1_VOTE_GPU_SMMU_GDS_ATTR 0x3 +#define HWIO_GCC_HLOS1_VOTE_GPU_SMMU_GDS_IN \ + in_dword_masked(HWIO_GCC_HLOS1_VOTE_GPU_SMMU_GDS_ADDR, HWIO_GCC_HLOS1_VOTE_GPU_SMMU_GDS_RMSK) +#define HWIO_GCC_HLOS1_VOTE_GPU_SMMU_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_HLOS1_VOTE_GPU_SMMU_GDS_ADDR, m) +#define HWIO_GCC_HLOS1_VOTE_GPU_SMMU_GDS_OUT(v) \ + out_dword(HWIO_GCC_HLOS1_VOTE_GPU_SMMU_GDS_ADDR,v) +#define HWIO_GCC_HLOS1_VOTE_GPU_SMMU_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HLOS1_VOTE_GPU_SMMU_GDS_ADDR,m,v,HWIO_GCC_HLOS1_VOTE_GPU_SMMU_GDS_IN) +#define HWIO_GCC_HLOS1_VOTE_GPU_SMMU_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_HLOS1_VOTE_GPU_SMMU_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_HLOS1_VOTE_GPU_SMMU_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_HLOS1_VOTE_GPU_SMMU_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_HLOS1_VOTE_GPU_SMMU_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HLOS1_VOTE_GPU_SMMU_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HLOS1_VOTE_LPASS_QTB_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006d040) +#define HWIO_GCC_HLOS1_VOTE_LPASS_QTB_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006d040) +#define HWIO_GCC_HLOS1_VOTE_LPASS_QTB_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006d040) +#define HWIO_GCC_HLOS1_VOTE_LPASS_QTB_GDS_RMSK 0x80000001 +#define HWIO_GCC_HLOS1_VOTE_LPASS_QTB_GDS_ATTR 0x3 +#define HWIO_GCC_HLOS1_VOTE_LPASS_QTB_GDS_IN \ + in_dword_masked(HWIO_GCC_HLOS1_VOTE_LPASS_QTB_GDS_ADDR, HWIO_GCC_HLOS1_VOTE_LPASS_QTB_GDS_RMSK) +#define HWIO_GCC_HLOS1_VOTE_LPASS_QTB_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_HLOS1_VOTE_LPASS_QTB_GDS_ADDR, m) +#define HWIO_GCC_HLOS1_VOTE_LPASS_QTB_GDS_OUT(v) \ + out_dword(HWIO_GCC_HLOS1_VOTE_LPASS_QTB_GDS_ADDR,v) +#define HWIO_GCC_HLOS1_VOTE_LPASS_QTB_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HLOS1_VOTE_LPASS_QTB_GDS_ADDR,m,v,HWIO_GCC_HLOS1_VOTE_LPASS_QTB_GDS_IN) +#define HWIO_GCC_HLOS1_VOTE_LPASS_QTB_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_HLOS1_VOTE_LPASS_QTB_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_HLOS1_VOTE_LPASS_QTB_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_HLOS1_VOTE_LPASS_QTB_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_HLOS1_VOTE_LPASS_QTB_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HLOS1_VOTE_LPASS_QTB_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB1_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006d044) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB1_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006d044) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB1_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006d044) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB1_GDS_RMSK 0x80000001 +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB1_GDS_ATTR 0x3 +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB1_GDS_IN \ + in_dword_masked(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB1_GDS_ADDR, HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB1_GDS_RMSK) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB1_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB1_GDS_ADDR, m) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB1_GDS_OUT(v) \ + out_dword(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB1_GDS_ADDR,v) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB1_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB1_GDS_ADDR,m,v,HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB1_GDS_IN) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB1_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB1_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB1_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB1_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB1_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB1_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB2_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006d048) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB2_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006d048) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB2_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006d048) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB2_GDS_RMSK 0x80000001 +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB2_GDS_ATTR 0x3 +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB2_GDS_IN \ + in_dword_masked(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB2_GDS_ADDR, HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB2_GDS_RMSK) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB2_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB2_GDS_ADDR, m) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB2_GDS_OUT(v) \ + out_dword(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB2_GDS_ADDR,v) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB2_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB2_GDS_ADDR,m,v,HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB2_GDS_IN) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB2_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB2_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB2_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB2_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB2_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB2_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006d04c) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006d04c) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006d04c) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_RMSK 0x80000001 +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_ATTR 0x3 +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_IN \ + in_dword_masked(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_ADDR, HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_RMSK) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_ADDR, m) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_OUT(v) \ + out_dword(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_ADDR,v) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_ADDR,m,v,HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_IN) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF01_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006d050) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF01_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006d050) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF01_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006d050) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF01_GDS_RMSK 0x80000001 +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF01_GDS_ATTR 0x3 +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF01_GDS_IN \ + in_dword_masked(HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF01_GDS_ADDR, HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF01_GDS_RMSK) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF01_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF01_GDS_ADDR, m) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF01_GDS_OUT(v) \ + out_dword(HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF01_GDS_ADDR,v) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF01_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF01_GDS_ADDR,m,v,HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF01_GDS_IN) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF01_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF01_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF01_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF01_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF01_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF01_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_SF_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006d054) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_SF_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006d054) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_SF_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006d054) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_SF_GDS_RMSK 0x80000001 +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_SF_GDS_ATTR 0x3 +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_SF_GDS_IN \ + in_dword_masked(HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_SF_GDS_ADDR, HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_SF_GDS_RMSK) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_SF_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_SF_GDS_ADDR, m) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_SF_GDS_OUT(v) \ + out_dword(HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_SF_GDS_ADDR,v) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_SF_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_SF_GDS_ADDR,m,v,HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_SF_GDS_IN) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_SF_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_SF_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_SF_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_SF_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_SF_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_SF_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_QTB0_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006d05c) +#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_QTB0_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006d05c) +#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_QTB0_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006d05c) +#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_QTB0_GDS_RMSK 0x80000001 +#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_QTB0_GDS_ATTR 0x3 +#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_QTB0_GDS_IN \ + in_dword_masked(HWIO_GCC_HLOS1_VOTE_TURING_MMU_QTB0_GDS_ADDR, HWIO_GCC_HLOS1_VOTE_TURING_MMU_QTB0_GDS_RMSK) +#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_QTB0_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_HLOS1_VOTE_TURING_MMU_QTB0_GDS_ADDR, m) +#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_QTB0_GDS_OUT(v) \ + out_dword(HWIO_GCC_HLOS1_VOTE_TURING_MMU_QTB0_GDS_ADDR,v) +#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_QTB0_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HLOS1_VOTE_TURING_MMU_QTB0_GDS_ADDR,m,v,HWIO_GCC_HLOS1_VOTE_TURING_MMU_QTB0_GDS_IN) +#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_QTB0_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_QTB0_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_QTB0_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_QTB0_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_QTB0_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_QTB0_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006d064) +#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006d064) +#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006d064) +#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_GDS_RMSK 0x80000001 +#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_GDS_ATTR 0x3 +#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_GDS_IN \ + in_dword_masked(HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_GDS_ADDR, HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_GDS_RMSK) +#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_GDS_ADDR, m) +#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_GDS_OUT(v) \ + out_dword(HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_GDS_ADDR,v) +#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_GDS_ADDR,m,v,HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_GDS_IN) +#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006d068) +#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006d068) +#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006d068) +#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_GDS_RMSK 0x80000001 +#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_GDS_ATTR 0x3 +#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_GDS_IN \ + in_dword_masked(HWIO_GCC_HLOS1_VOTE_MMU_TCU_GDS_ADDR, HWIO_GCC_HLOS1_VOTE_MMU_TCU_GDS_RMSK) +#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_HLOS1_VOTE_MMU_TCU_GDS_ADDR, m) +#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_GDS_OUT(v) \ + out_dword(HWIO_GCC_HLOS1_VOTE_MMU_TCU_GDS_ADDR,v) +#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HLOS1_VOTE_MMU_TCU_GDS_ADDR,m,v,HWIO_GCC_HLOS1_VOTE_MMU_TCU_GDS_IN) +#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF23_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006d070) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF23_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006d070) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF23_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006d070) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF23_CLK_RMSK 0x80000001 +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF23_CLK_ATTR 0x3 +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF23_CLK_IN \ + in_dword_masked(HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF23_CLK_ADDR, HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF23_CLK_RMSK) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF23_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF23_CLK_ADDR, m) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF23_CLK_OUT(v) \ + out_dword(HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF23_CLK_ADDR,v) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF23_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF23_CLK_ADDR,m,v,HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF23_CLK_IN) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF23_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF23_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF23_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF23_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF23_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF23_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF23_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006d078) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF23_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006d078) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF23_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006d078) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF23_GDS_RMSK 0x80000001 +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF23_GDS_ATTR 0x3 +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF23_GDS_IN \ + in_dword_masked(HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF23_GDS_ADDR, HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF23_GDS_RMSK) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF23_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF23_GDS_ADDR, m) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF23_GDS_OUT(v) \ + out_dword(HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF23_GDS_ADDR,v) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF23_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF23_GDS_ADDR,m,v,HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF23_GDS_IN) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF23_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF23_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF23_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF23_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF23_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF23_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HLOS2_VOTE_GPU_SMMU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006e000) +#define HWIO_GCC_HLOS2_VOTE_GPU_SMMU_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006e000) +#define HWIO_GCC_HLOS2_VOTE_GPU_SMMU_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006e000) +#define HWIO_GCC_HLOS2_VOTE_GPU_SMMU_CLK_RMSK 0x80000001 +#define HWIO_GCC_HLOS2_VOTE_GPU_SMMU_CLK_ATTR 0x3 +#define HWIO_GCC_HLOS2_VOTE_GPU_SMMU_CLK_IN \ + in_dword_masked(HWIO_GCC_HLOS2_VOTE_GPU_SMMU_CLK_ADDR, HWIO_GCC_HLOS2_VOTE_GPU_SMMU_CLK_RMSK) +#define HWIO_GCC_HLOS2_VOTE_GPU_SMMU_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_HLOS2_VOTE_GPU_SMMU_CLK_ADDR, m) +#define HWIO_GCC_HLOS2_VOTE_GPU_SMMU_CLK_OUT(v) \ + out_dword(HWIO_GCC_HLOS2_VOTE_GPU_SMMU_CLK_ADDR,v) +#define HWIO_GCC_HLOS2_VOTE_GPU_SMMU_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HLOS2_VOTE_GPU_SMMU_CLK_ADDR,m,v,HWIO_GCC_HLOS2_VOTE_GPU_SMMU_CLK_IN) +#define HWIO_GCC_HLOS2_VOTE_GPU_SMMU_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_HLOS2_VOTE_GPU_SMMU_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_HLOS2_VOTE_GPU_SMMU_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_HLOS2_VOTE_GPU_SMMU_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_HLOS2_VOTE_GPU_SMMU_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HLOS2_VOTE_GPU_SMMU_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HLOS2_VOTE_LPASS_QTB_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006e004) +#define HWIO_GCC_HLOS2_VOTE_LPASS_QTB_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006e004) +#define HWIO_GCC_HLOS2_VOTE_LPASS_QTB_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006e004) +#define HWIO_GCC_HLOS2_VOTE_LPASS_QTB_CLK_RMSK 0x80000001 +#define HWIO_GCC_HLOS2_VOTE_LPASS_QTB_CLK_ATTR 0x3 +#define HWIO_GCC_HLOS2_VOTE_LPASS_QTB_CLK_IN \ + in_dword_masked(HWIO_GCC_HLOS2_VOTE_LPASS_QTB_CLK_ADDR, HWIO_GCC_HLOS2_VOTE_LPASS_QTB_CLK_RMSK) +#define HWIO_GCC_HLOS2_VOTE_LPASS_QTB_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_HLOS2_VOTE_LPASS_QTB_CLK_ADDR, m) +#define HWIO_GCC_HLOS2_VOTE_LPASS_QTB_CLK_OUT(v) \ + out_dword(HWIO_GCC_HLOS2_VOTE_LPASS_QTB_CLK_ADDR,v) +#define HWIO_GCC_HLOS2_VOTE_LPASS_QTB_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HLOS2_VOTE_LPASS_QTB_CLK_ADDR,m,v,HWIO_GCC_HLOS2_VOTE_LPASS_QTB_CLK_IN) +#define HWIO_GCC_HLOS2_VOTE_LPASS_QTB_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_HLOS2_VOTE_LPASS_QTB_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_HLOS2_VOTE_LPASS_QTB_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_HLOS2_VOTE_LPASS_QTB_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_HLOS2_VOTE_LPASS_QTB_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HLOS2_VOTE_LPASS_QTB_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB1_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006e008) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB1_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006e008) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB1_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006e008) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB1_CLK_RMSK 0x80000001 +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB1_CLK_ATTR 0x3 +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB1_CLK_IN \ + in_dword_masked(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB1_CLK_ADDR, HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB1_CLK_RMSK) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB1_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB1_CLK_ADDR, m) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB1_CLK_OUT(v) \ + out_dword(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB1_CLK_ADDR,v) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB1_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB1_CLK_ADDR,m,v,HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB1_CLK_IN) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB1_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB1_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB1_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB1_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB1_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB1_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB2_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006e00c) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB2_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006e00c) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB2_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006e00c) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB2_CLK_RMSK 0x80000001 +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB2_CLK_ATTR 0x3 +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB2_CLK_IN \ + in_dword_masked(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB2_CLK_ADDR, HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB2_CLK_RMSK) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB2_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB2_CLK_ADDR, m) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB2_CLK_OUT(v) \ + out_dword(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB2_CLK_ADDR,v) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB2_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB2_CLK_ADDR,m,v,HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB2_CLK_IN) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB2_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB2_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB2_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB2_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB2_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB2_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006e010) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006e010) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006e010) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_RMSK 0x80000001 +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_ATTR 0x3 +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_IN \ + in_dword_masked(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_ADDR, HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_RMSK) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_ADDR, m) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_OUT(v) \ + out_dword(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_ADDR,v) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_ADDR,m,v,HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_IN) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_SF_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006e014) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_SF_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006e014) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_SF_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006e014) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_SF_CLK_RMSK 0x80000001 +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_SF_CLK_ATTR 0x3 +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_SF_CLK_IN \ + in_dword_masked(HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_SF_CLK_ADDR, HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_SF_CLK_RMSK) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_SF_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_SF_CLK_ADDR, m) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_SF_CLK_OUT(v) \ + out_dword(HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_SF_CLK_ADDR,v) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_SF_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_SF_CLK_ADDR,m,v,HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_SF_CLK_IN) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_SF_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_SF_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_SF_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_SF_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_SF_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_SF_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF01_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006e018) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF01_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006e018) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF01_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006e018) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF01_CLK_RMSK 0x80000001 +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF01_CLK_ATTR 0x3 +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF01_CLK_IN \ + in_dword_masked(HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF01_CLK_ADDR, HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF01_CLK_RMSK) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF01_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF01_CLK_ADDR, m) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF01_CLK_OUT(v) \ + out_dword(HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF01_CLK_ADDR,v) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF01_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF01_CLK_ADDR,m,v,HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF01_CLK_IN) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF01_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF01_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF01_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF01_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF01_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF01_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_QTB0_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006e020) +#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_QTB0_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006e020) +#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_QTB0_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006e020) +#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_QTB0_CLK_RMSK 0x80000001 +#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_QTB0_CLK_ATTR 0x3 +#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_QTB0_CLK_IN \ + in_dword_masked(HWIO_GCC_HLOS2_VOTE_TURING_MMU_QTB0_CLK_ADDR, HWIO_GCC_HLOS2_VOTE_TURING_MMU_QTB0_CLK_RMSK) +#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_QTB0_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_HLOS2_VOTE_TURING_MMU_QTB0_CLK_ADDR, m) +#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_QTB0_CLK_OUT(v) \ + out_dword(HWIO_GCC_HLOS2_VOTE_TURING_MMU_QTB0_CLK_ADDR,v) +#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_QTB0_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HLOS2_VOTE_TURING_MMU_QTB0_CLK_ADDR,m,v,HWIO_GCC_HLOS2_VOTE_TURING_MMU_QTB0_CLK_IN) +#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_QTB0_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_QTB0_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_QTB0_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_QTB0_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_QTB0_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_QTB0_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006e028) +#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006e028) +#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006e028) +#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_RMSK 0x80000001 +#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_ATTR 0x3 +#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_IN \ + in_dword_masked(HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_ADDR, HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_RMSK) +#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_ADDR, m) +#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_OUT(v) \ + out_dword(HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_ADDR,v) +#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_ADDR,m,v,HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_IN) +#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006e02c) +#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006e02c) +#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006e02c) +#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_RMSK 0x80000001 +#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_ATTR 0x3 +#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_IN \ + in_dword_masked(HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_ADDR, HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_RMSK) +#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_ADDR, m) +#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_OUT(v) \ + out_dword(HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_ADDR,v) +#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_ADDR,m,v,HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_IN) +#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HLOS2_VOTE_GPU_SMMU_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006e03c) +#define HWIO_GCC_HLOS2_VOTE_GPU_SMMU_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006e03c) +#define HWIO_GCC_HLOS2_VOTE_GPU_SMMU_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006e03c) +#define HWIO_GCC_HLOS2_VOTE_GPU_SMMU_GDS_RMSK 0x80000001 +#define HWIO_GCC_HLOS2_VOTE_GPU_SMMU_GDS_ATTR 0x3 +#define HWIO_GCC_HLOS2_VOTE_GPU_SMMU_GDS_IN \ + in_dword_masked(HWIO_GCC_HLOS2_VOTE_GPU_SMMU_GDS_ADDR, HWIO_GCC_HLOS2_VOTE_GPU_SMMU_GDS_RMSK) +#define HWIO_GCC_HLOS2_VOTE_GPU_SMMU_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_HLOS2_VOTE_GPU_SMMU_GDS_ADDR, m) +#define HWIO_GCC_HLOS2_VOTE_GPU_SMMU_GDS_OUT(v) \ + out_dword(HWIO_GCC_HLOS2_VOTE_GPU_SMMU_GDS_ADDR,v) +#define HWIO_GCC_HLOS2_VOTE_GPU_SMMU_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HLOS2_VOTE_GPU_SMMU_GDS_ADDR,m,v,HWIO_GCC_HLOS2_VOTE_GPU_SMMU_GDS_IN) +#define HWIO_GCC_HLOS2_VOTE_GPU_SMMU_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_HLOS2_VOTE_GPU_SMMU_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_HLOS2_VOTE_GPU_SMMU_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_HLOS2_VOTE_GPU_SMMU_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_HLOS2_VOTE_GPU_SMMU_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HLOS2_VOTE_GPU_SMMU_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HLOS2_VOTE_LPASS_QTB_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006e040) +#define HWIO_GCC_HLOS2_VOTE_LPASS_QTB_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006e040) +#define HWIO_GCC_HLOS2_VOTE_LPASS_QTB_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006e040) +#define HWIO_GCC_HLOS2_VOTE_LPASS_QTB_GDS_RMSK 0x80000001 +#define HWIO_GCC_HLOS2_VOTE_LPASS_QTB_GDS_ATTR 0x3 +#define HWIO_GCC_HLOS2_VOTE_LPASS_QTB_GDS_IN \ + in_dword_masked(HWIO_GCC_HLOS2_VOTE_LPASS_QTB_GDS_ADDR, HWIO_GCC_HLOS2_VOTE_LPASS_QTB_GDS_RMSK) +#define HWIO_GCC_HLOS2_VOTE_LPASS_QTB_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_HLOS2_VOTE_LPASS_QTB_GDS_ADDR, m) +#define HWIO_GCC_HLOS2_VOTE_LPASS_QTB_GDS_OUT(v) \ + out_dword(HWIO_GCC_HLOS2_VOTE_LPASS_QTB_GDS_ADDR,v) +#define HWIO_GCC_HLOS2_VOTE_LPASS_QTB_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HLOS2_VOTE_LPASS_QTB_GDS_ADDR,m,v,HWIO_GCC_HLOS2_VOTE_LPASS_QTB_GDS_IN) +#define HWIO_GCC_HLOS2_VOTE_LPASS_QTB_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_HLOS2_VOTE_LPASS_QTB_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_HLOS2_VOTE_LPASS_QTB_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_HLOS2_VOTE_LPASS_QTB_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_HLOS2_VOTE_LPASS_QTB_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HLOS2_VOTE_LPASS_QTB_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB1_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006e044) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB1_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006e044) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB1_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006e044) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB1_GDS_RMSK 0x80000001 +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB1_GDS_ATTR 0x3 +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB1_GDS_IN \ + in_dword_masked(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB1_GDS_ADDR, HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB1_GDS_RMSK) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB1_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB1_GDS_ADDR, m) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB1_GDS_OUT(v) \ + out_dword(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB1_GDS_ADDR,v) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB1_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB1_GDS_ADDR,m,v,HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB1_GDS_IN) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB1_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB1_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB1_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB1_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB1_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB1_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB2_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006e048) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB2_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006e048) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB2_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006e048) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB2_GDS_RMSK 0x80000001 +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB2_GDS_ATTR 0x3 +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB2_GDS_IN \ + in_dword_masked(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB2_GDS_ADDR, HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB2_GDS_RMSK) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB2_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB2_GDS_ADDR, m) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB2_GDS_OUT(v) \ + out_dword(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB2_GDS_ADDR,v) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB2_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB2_GDS_ADDR,m,v,HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB2_GDS_IN) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB2_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB2_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB2_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB2_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB2_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB2_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006e04c) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006e04c) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006e04c) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_RMSK 0x80000001 +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_ATTR 0x3 +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_IN \ + in_dword_masked(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_ADDR, HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_RMSK) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_ADDR, m) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_OUT(v) \ + out_dword(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_ADDR,v) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_ADDR,m,v,HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_IN) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF01_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006e050) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF01_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006e050) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF01_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006e050) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF01_GDS_RMSK 0x80000001 +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF01_GDS_ATTR 0x3 +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF01_GDS_IN \ + in_dword_masked(HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF01_GDS_ADDR, HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF01_GDS_RMSK) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF01_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF01_GDS_ADDR, m) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF01_GDS_OUT(v) \ + out_dword(HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF01_GDS_ADDR,v) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF01_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF01_GDS_ADDR,m,v,HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF01_GDS_IN) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF01_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF01_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF01_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF01_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF01_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF01_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_SF_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006e054) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_SF_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006e054) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_SF_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006e054) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_SF_GDS_RMSK 0x80000001 +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_SF_GDS_ATTR 0x3 +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_SF_GDS_IN \ + in_dword_masked(HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_SF_GDS_ADDR, HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_SF_GDS_RMSK) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_SF_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_SF_GDS_ADDR, m) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_SF_GDS_OUT(v) \ + out_dword(HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_SF_GDS_ADDR,v) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_SF_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_SF_GDS_ADDR,m,v,HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_SF_GDS_IN) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_SF_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_SF_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_SF_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_SF_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_SF_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_SF_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_QTB0_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006e05c) +#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_QTB0_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006e05c) +#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_QTB0_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006e05c) +#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_QTB0_GDS_RMSK 0x80000001 +#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_QTB0_GDS_ATTR 0x3 +#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_QTB0_GDS_IN \ + in_dword_masked(HWIO_GCC_HLOS2_VOTE_TURING_MMU_QTB0_GDS_ADDR, HWIO_GCC_HLOS2_VOTE_TURING_MMU_QTB0_GDS_RMSK) +#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_QTB0_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_HLOS2_VOTE_TURING_MMU_QTB0_GDS_ADDR, m) +#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_QTB0_GDS_OUT(v) \ + out_dword(HWIO_GCC_HLOS2_VOTE_TURING_MMU_QTB0_GDS_ADDR,v) +#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_QTB0_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HLOS2_VOTE_TURING_MMU_QTB0_GDS_ADDR,m,v,HWIO_GCC_HLOS2_VOTE_TURING_MMU_QTB0_GDS_IN) +#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_QTB0_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_QTB0_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_QTB0_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_QTB0_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_QTB0_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_QTB0_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006e064) +#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006e064) +#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006e064) +#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_GDS_RMSK 0x80000001 +#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_GDS_ATTR 0x3 +#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_GDS_IN \ + in_dword_masked(HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_GDS_ADDR, HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_GDS_RMSK) +#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_GDS_ADDR, m) +#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_GDS_OUT(v) \ + out_dword(HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_GDS_ADDR,v) +#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_GDS_ADDR,m,v,HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_GDS_IN) +#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006e068) +#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006e068) +#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006e068) +#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_GDS_RMSK 0x80000001 +#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_GDS_ATTR 0x3 +#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_GDS_IN \ + in_dword_masked(HWIO_GCC_HLOS2_VOTE_MMU_TCU_GDS_ADDR, HWIO_GCC_HLOS2_VOTE_MMU_TCU_GDS_RMSK) +#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_HLOS2_VOTE_MMU_TCU_GDS_ADDR, m) +#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_GDS_OUT(v) \ + out_dword(HWIO_GCC_HLOS2_VOTE_MMU_TCU_GDS_ADDR,v) +#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HLOS2_VOTE_MMU_TCU_GDS_ADDR,m,v,HWIO_GCC_HLOS2_VOTE_MMU_TCU_GDS_IN) +#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF23_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006e070) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF23_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006e070) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF23_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006e070) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF23_CLK_RMSK 0x80000001 +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF23_CLK_ATTR 0x3 +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF23_CLK_IN \ + in_dword_masked(HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF23_CLK_ADDR, HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF23_CLK_RMSK) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF23_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF23_CLK_ADDR, m) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF23_CLK_OUT(v) \ + out_dword(HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF23_CLK_ADDR,v) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF23_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF23_CLK_ADDR,m,v,HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF23_CLK_IN) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF23_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF23_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF23_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF23_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF23_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF23_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF23_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006e078) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF23_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006e078) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF23_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006e078) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF23_GDS_RMSK 0x80000001 +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF23_GDS_ATTR 0x3 +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF23_GDS_IN \ + in_dword_masked(HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF23_GDS_ADDR, HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF23_GDS_RMSK) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF23_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF23_GDS_ADDR, m) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF23_GDS_OUT(v) \ + out_dword(HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF23_GDS_ADDR,v) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF23_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF23_GDS_ADDR,m,v,HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF23_GDS_IN) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF23_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF23_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF23_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF23_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF23_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF23_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000c484) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c484) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c484) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_RMSK 0xffffbfff +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_ATTR 0x3 +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IN \ + in_dword_masked(HWIO_GCC_MMNOC_GDS_HW_CTRL_ADDR, HWIO_GCC_MMNOC_GDS_HW_CTRL_RMSK) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_INM(m) \ + in_dword_masked(HWIO_GCC_MMNOC_GDS_HW_CTRL_ADDR, m) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_OUT(v) \ + out_dword(HWIO_GCC_MMNOC_GDS_HW_CTRL_ADDR,v) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MMNOC_GDS_HW_CTRL_ADDR,m,v,HWIO_GCC_MMNOC_GDS_HW_CTRL_IN) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_PWR_ON_STATUS_BMSK 0x80000000 +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_PWR_ON_STATUS_SHFT 0x1f +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_RESERVE_30_29_BMSK 0x60000000 +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_RESERVE_30_29_SHFT 0x1d +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_HYS_TIMER_BMSK 0x1fe00000 +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_HYS_TIMER_SHFT 0x15 +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_MAX_RETRY_BMSK 0x1e0000 +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_MAX_RETRY_SHFT 0x11 +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_DENY_ENABLE_BMSK 0x10000 +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_DENY_ENABLE_SHFT 0x10 +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_COLLAPSE_OUT_BMSK 0x8000 +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_COLLAPSE_OUT_SHFT 0xf +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_HALT_ACK_TIMEOUT_BMSK 0x3fc0 +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_HALT_ACK_TIMEOUT_SHFT 0x6 +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_GDS_HW_STATE_BMSK 0x3e +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_GDS_HW_STATE_SHFT 0x1 +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_SW_OVERRIDE_SHFT 0x0 + +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000c488) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c488) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c488) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_RMSK 0xfffff +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_ATTR 0x1 +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_IN \ + in_dword_masked(HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_ADDR, HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_RMSK) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_INM(m) \ + in_dword_masked(HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_ADDR, m) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_HALT1_REQ_STATUS_BMSK 0xc0000 +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_HALT1_REQ_STATUS_SHFT 0x12 +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_HALT2_REQ_STATUS_BMSK 0x20000 +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_HALT2_REQ_STATUS_SHFT 0x11 +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_DVM_HALT1_REQ_STATUS_BMSK 0x18000 +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_DVM_HALT1_REQ_STATUS_SHFT 0xf +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_HALT2_PWR_DOWN_DENY_STATUS_BMSK 0x4000 +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_HALT2_PWR_DOWN_DENY_STATUS_SHFT 0xe +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_DVM_HALT1_PWR_DOWN_ACK_STATUS_BMSK 0x3000 +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_DVM_HALT1_PWR_DOWN_ACK_STATUS_SHFT 0xc +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_DVM_HALT1_PWR_UP_ACK_STATUS_BMSK 0xc00 +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_DVM_HALT1_PWR_UP_ACK_STATUS_SHFT 0xa +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_HALT2_PWR_DOWN_ACK_STATUS_BMSK 0x200 +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_HALT2_PWR_DOWN_ACK_STATUS_SHFT 0x9 +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_HALT2_PWR_UP_ACK_STATUS_BMSK 0x100 +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_HALT2_PWR_UP_ACK_STATUS_SHFT 0x8 +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_HALT1_PWR_DOWN_ACK_STATUS_BMSK 0xc0 +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_HALT1_PWR_DOWN_ACK_STATUS_SHFT 0x6 +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_DVM_HALT1_PWR_DOWN_DENY_STATUS_BMSK 0x30 +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_DVM_HALT1_PWR_DOWN_DENY_STATUS_SHFT 0x4 +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_HALT1_PWR_DOWN_DENY_STATUS_BMSK 0xc +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_HALT1_PWR_DOWN_DENY_STATUS_SHFT 0x2 +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_HALT1_PWR_UP_ACK_STATUS_BMSK 0x3 +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_HALT1_PWR_UP_ACK_STATUS_SHFT 0x0 + +#define HWIO_GCC_MMNOC_HALT_REQ_GDS_HW_CTRL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000c48c) +#define HWIO_GCC_MMNOC_HALT_REQ_GDS_HW_CTRL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c48c) +#define HWIO_GCC_MMNOC_HALT_REQ_GDS_HW_CTRL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c48c) +#define HWIO_GCC_MMNOC_HALT_REQ_GDS_HW_CTRL_RMSK 0x1ffff +#define HWIO_GCC_MMNOC_HALT_REQ_GDS_HW_CTRL_ATTR 0x3 +#define HWIO_GCC_MMNOC_HALT_REQ_GDS_HW_CTRL_IN \ + in_dword_masked(HWIO_GCC_MMNOC_HALT_REQ_GDS_HW_CTRL_ADDR, HWIO_GCC_MMNOC_HALT_REQ_GDS_HW_CTRL_RMSK) +#define HWIO_GCC_MMNOC_HALT_REQ_GDS_HW_CTRL_INM(m) \ + in_dword_masked(HWIO_GCC_MMNOC_HALT_REQ_GDS_HW_CTRL_ADDR, m) +#define HWIO_GCC_MMNOC_HALT_REQ_GDS_HW_CTRL_OUT(v) \ + out_dword(HWIO_GCC_MMNOC_HALT_REQ_GDS_HW_CTRL_ADDR,v) +#define HWIO_GCC_MMNOC_HALT_REQ_GDS_HW_CTRL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MMNOC_HALT_REQ_GDS_HW_CTRL_ADDR,m,v,HWIO_GCC_MMNOC_HALT_REQ_GDS_HW_CTRL_IN) +#define HWIO_GCC_MMNOC_HALT_REQ_GDS_HW_CTRL_RESERVE_4_15_BMSK 0x1ffe0 +#define HWIO_GCC_MMNOC_HALT_REQ_GDS_HW_CTRL_RESERVE_4_15_SHFT 0x5 +#define HWIO_GCC_MMNOC_HALT_REQ_GDS_HW_CTRL_DVM_HALT_REQ_BMSK 0x18 +#define HWIO_GCC_MMNOC_HALT_REQ_GDS_HW_CTRL_DVM_HALT_REQ_SHFT 0x3 +#define HWIO_GCC_MMNOC_HALT_REQ_GDS_HW_CTRL_MMU_QTB_HALT_REQ_BMSK 0x6 +#define HWIO_GCC_MMNOC_HALT_REQ_GDS_HW_CTRL_MMU_QTB_HALT_REQ_SHFT 0x1 +#define HWIO_GCC_MMNOC_HALT_REQ_GDS_HW_CTRL_NOC_HALT_REQ_BMSK 0x1 +#define HWIO_GCC_MMNOC_HALT_REQ_GDS_HW_CTRL_NOC_HALT_REQ_SHFT 0x0 + +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_STATUS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000c490) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_STATUS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c490) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_STATUS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c490) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_STATUS_RMSK 0x1 +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_STATUS_ATTR 0x1 +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_STATUS_IN \ + in_dword_masked(HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_STATUS_ADDR, HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_STATUS_RMSK) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_STATUS_INM(m) \ + in_dword_masked(HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_STATUS_ADDR, m) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_STATUS_STATUS_BMSK 0x1 +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_STATUS_STATUS_SHFT 0x0 + +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_MASK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000c494) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_MASK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c494) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_MASK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c494) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_MASK_RMSK 0x1 +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_MASK_ATTR 0x3 +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_MASK_IN \ + in_dword_masked(HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_MASK_ADDR, HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_MASK_RMSK) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_MASK_INM(m) \ + in_dword_masked(HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_MASK_ADDR, m) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_MASK_OUT(v) \ + out_dword(HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_MASK_ADDR,v) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_MASK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_MASK_ADDR,m,v,HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_MASK_IN) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_MASK_MASK_BMSK 0x1 +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_MASK_MASK_SHFT 0x0 + +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_CLEAR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000c498) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_CLEAR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c498) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_CLEAR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c498) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_CLEAR_RMSK 0x1 +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_CLEAR_ATTR 0x3 +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_CLEAR_IN \ + in_dword_masked(HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_CLEAR_ADDR, HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_CLEAR_RMSK) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_CLEAR_INM(m) \ + in_dword_masked(HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_CLEAR_ADDR, m) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_CLEAR_OUT(v) \ + out_dword(HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_CLEAR_ADDR,v) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_CLEAR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_CLEAR_ADDR,m,v,HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_CLEAR_IN) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_CLEAR_CLEAR_BMSK 0x1 +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_CLEAR_CLEAR_SHFT 0x0 + +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_SPARE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000c49c) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_SPARE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c49c) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_SPARE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c49c) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_SPARE_RMSK 0xff +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_SPARE_ATTR 0x3 +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_SPARE_IN \ + in_dword_masked(HWIO_GCC_MMNOC_GDS_HW_CTRL_SPARE_ADDR, HWIO_GCC_MMNOC_GDS_HW_CTRL_SPARE_RMSK) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_SPARE_INM(m) \ + in_dword_masked(HWIO_GCC_MMNOC_GDS_HW_CTRL_SPARE_ADDR, m) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_SPARE_OUT(v) \ + out_dword(HWIO_GCC_MMNOC_GDS_HW_CTRL_SPARE_ADDR,v) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_SPARE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MMNOC_GDS_HW_CTRL_SPARE_ADDR,m,v,HWIO_GCC_MMNOC_GDS_HW_CTRL_SPARE_IN) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_SPARE_SPARE_BMSK 0xff +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_SPARE_SPARE_SHFT 0x0 + +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000015c) +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000015c) +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000015c) +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_RMSK 0xffffbfff +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_ATTR 0x3 +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_IN \ + in_dword_masked(HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_ADDR, HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_RMSK) +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_INM(m) \ + in_dword_masked(HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_ADDR, m) +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_OUT(v) \ + out_dword(HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_ADDR,v) +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_ADDR,m,v,HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_IN) +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_PWR_ON_STATUS_BMSK 0x80000000 +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_PWR_ON_STATUS_SHFT 0x1f +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_RESERVE_30_29_BMSK 0x60000000 +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_RESERVE_30_29_SHFT 0x1d +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_HYS_TIMER_BMSK 0x1fe00000 +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_HYS_TIMER_SHFT 0x15 +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_MAX_RETRY_BMSK 0x1e0000 +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_MAX_RETRY_SHFT 0x11 +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_DENY_ENABLE_BMSK 0x10000 +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_DENY_ENABLE_SHFT 0x10 +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_COLLAPSE_OUT_BMSK 0x8000 +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_COLLAPSE_OUT_SHFT 0xf +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_HALT_ACK_TIMEOUT_BMSK 0x3fc0 +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_HALT_ACK_TIMEOUT_SHFT 0x6 +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_GDS_HW_STATE_BMSK 0x3e +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_GDS_HW_STATE_SHFT 0x1 +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_SW_OVERRIDE_SHFT 0x0 + +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_STATUS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000160) +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_STATUS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000160) +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_STATUS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000160) +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_STATUS_RMSK 0xffffffff +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_STATUS_ATTR 0x3 +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_STATUS_IN \ + in_dword_masked(HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_STATUS_ADDR, HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_STATUS_RMSK) +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_STATUS_INM(m) \ + in_dword_masked(HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_STATUS_ADDR, m) +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_STATUS_OUT(v) \ + out_dword(HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_STATUS_ADDR,v) +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_STATUS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_STATUS_ADDR,m,v,HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_STATUS_IN) +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_STATUS_RESERVE_24_31_BMSK 0xff000000 +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_STATUS_RESERVE_24_31_SHFT 0x18 +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_STATUS_HALT1_REQ_STATUS_BMSK 0x800000 +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_STATUS_HALT1_REQ_STATUS_SHFT 0x17 +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_STATUS_HALT2_REQ_STATUS_BMSK 0x400000 +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_STATUS_HALT2_REQ_STATUS_SHFT 0x16 +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_STATUS_DVM_HALT1_REQ_STATUS_BMSK 0x200000 +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_STATUS_DVM_HALT1_REQ_STATUS_SHFT 0x15 +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_STATUS_DVM_HALT1_PWR_DOWN_ACK_STATUS_BMSK 0x100000 +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_STATUS_DVM_HALT1_PWR_DOWN_ACK_STATUS_SHFT 0x14 +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_STATUS_RESERVE_19_BMSK 0x80000 +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_STATUS_RESERVE_19_SHFT 0x13 +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_STATUS_DVM_HALT1_PWR_UP_ACK_STATUS_BMSK 0x40000 +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_STATUS_DVM_HALT1_PWR_UP_ACK_STATUS_SHFT 0x12 +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_STATUS_RESERVE_13_17_BMSK 0x3e000 +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_STATUS_RESERVE_13_17_SHFT 0xd +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_STATUS_HALT2_PWR_DOWN_ACK_STATUS_BMSK 0x1000 +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_STATUS_HALT2_PWR_DOWN_ACK_STATUS_SHFT 0xc +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_STATUS_RESERVE_6_11_BMSK 0xfc0 +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_STATUS_RESERVE_6_11_SHFT 0x6 +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_STATUS_HALT2_PWR_DOWN_DENY_STATUS_BMSK 0x20 +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_STATUS_HALT2_PWR_DOWN_DENY_STATUS_SHFT 0x5 +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_STATUS_HALT2_PWR_UP_ACK_STATUS_BMSK 0x10 +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_STATUS_HALT2_PWR_UP_ACK_STATUS_SHFT 0x4 +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_STATUS_HALT1_PWR_DOWN_ACK_STATUS_BMSK 0x8 +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_STATUS_HALT1_PWR_DOWN_ACK_STATUS_SHFT 0x3 +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_STATUS_DVM_HALT1_PWR_DOWN_DENY_STATUS_BMSK 0x4 +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_STATUS_DVM_HALT1_PWR_DOWN_DENY_STATUS_SHFT 0x2 +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_STATUS_HALT1_PWR_DOWN_DENY_STATUS_BMSK 0x2 +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_STATUS_HALT1_PWR_DOWN_DENY_STATUS_SHFT 0x1 +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_STATUS_HALT1_PWR_UP_ACK_STATUS_BMSK 0x1 +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_STATUS_HALT1_PWR_UP_ACK_STATUS_SHFT 0x0 + +#define HWIO_GCC_ANOC_PCIE_HALT_REQ_GDS_HW_CTRL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000464) +#define HWIO_GCC_ANOC_PCIE_HALT_REQ_GDS_HW_CTRL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000464) +#define HWIO_GCC_ANOC_PCIE_HALT_REQ_GDS_HW_CTRL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000464) +#define HWIO_GCC_ANOC_PCIE_HALT_REQ_GDS_HW_CTRL_RMSK 0xffff +#define HWIO_GCC_ANOC_PCIE_HALT_REQ_GDS_HW_CTRL_ATTR 0x3 +#define HWIO_GCC_ANOC_PCIE_HALT_REQ_GDS_HW_CTRL_IN \ + in_dword_masked(HWIO_GCC_ANOC_PCIE_HALT_REQ_GDS_HW_CTRL_ADDR, HWIO_GCC_ANOC_PCIE_HALT_REQ_GDS_HW_CTRL_RMSK) +#define HWIO_GCC_ANOC_PCIE_HALT_REQ_GDS_HW_CTRL_INM(m) \ + in_dword_masked(HWIO_GCC_ANOC_PCIE_HALT_REQ_GDS_HW_CTRL_ADDR, m) +#define HWIO_GCC_ANOC_PCIE_HALT_REQ_GDS_HW_CTRL_OUT(v) \ + out_dword(HWIO_GCC_ANOC_PCIE_HALT_REQ_GDS_HW_CTRL_ADDR,v) +#define HWIO_GCC_ANOC_PCIE_HALT_REQ_GDS_HW_CTRL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ANOC_PCIE_HALT_REQ_GDS_HW_CTRL_ADDR,m,v,HWIO_GCC_ANOC_PCIE_HALT_REQ_GDS_HW_CTRL_IN) +#define HWIO_GCC_ANOC_PCIE_HALT_REQ_GDS_HW_CTRL_RESERVE_3_15_BMSK 0xfff8 +#define HWIO_GCC_ANOC_PCIE_HALT_REQ_GDS_HW_CTRL_RESERVE_3_15_SHFT 0x3 +#define HWIO_GCC_ANOC_PCIE_HALT_REQ_GDS_HW_CTRL_DVM_HALT_REQ_BMSK 0x4 +#define HWIO_GCC_ANOC_PCIE_HALT_REQ_GDS_HW_CTRL_DVM_HALT_REQ_SHFT 0x2 +#define HWIO_GCC_ANOC_PCIE_HALT_REQ_GDS_HW_CTRL_MMU_QTB_HALT_REQ_BMSK 0x2 +#define HWIO_GCC_ANOC_PCIE_HALT_REQ_GDS_HW_CTRL_MMU_QTB_HALT_REQ_SHFT 0x1 +#define HWIO_GCC_ANOC_PCIE_HALT_REQ_GDS_HW_CTRL_NOC_HALT_REQ_BMSK 0x1 +#define HWIO_GCC_ANOC_PCIE_HALT_REQ_GDS_HW_CTRL_NOC_HALT_REQ_SHFT 0x0 + +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_IRQ_STATUS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000468) +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_IRQ_STATUS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000468) +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_IRQ_STATUS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000468) +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_IRQ_STATUS_RMSK 0x1 +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_IRQ_STATUS_ATTR 0x1 +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_IRQ_STATUS_IN \ + in_dword_masked(HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_IRQ_STATUS_ADDR, HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_IRQ_STATUS_RMSK) +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_IRQ_STATUS_INM(m) \ + in_dword_masked(HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_IRQ_STATUS_ADDR, m) +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_IRQ_STATUS_STATUS_BMSK 0x1 +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_IRQ_STATUS_STATUS_SHFT 0x0 + +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_IRQ_MASK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000046c) +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_IRQ_MASK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000046c) +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_IRQ_MASK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000046c) +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_IRQ_MASK_RMSK 0x1 +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_IRQ_MASK_ATTR 0x3 +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_IRQ_MASK_IN \ + in_dword_masked(HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_IRQ_MASK_ADDR, HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_IRQ_MASK_RMSK) +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_IRQ_MASK_INM(m) \ + in_dword_masked(HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_IRQ_MASK_ADDR, m) +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_IRQ_MASK_OUT(v) \ + out_dword(HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_IRQ_MASK_ADDR,v) +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_IRQ_MASK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_IRQ_MASK_ADDR,m,v,HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_IRQ_MASK_IN) +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_IRQ_MASK_MASK_BMSK 0x1 +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_IRQ_MASK_MASK_SHFT 0x0 + +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_IRQ_CLEAR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000470) +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_IRQ_CLEAR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000470) +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_IRQ_CLEAR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000470) +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_IRQ_CLEAR_RMSK 0x1 +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_IRQ_CLEAR_ATTR 0x3 +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_IRQ_CLEAR_IN \ + in_dword_masked(HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_IRQ_CLEAR_ADDR, HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_IRQ_CLEAR_RMSK) +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_IRQ_CLEAR_INM(m) \ + in_dword_masked(HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_IRQ_CLEAR_ADDR, m) +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_IRQ_CLEAR_OUT(v) \ + out_dword(HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_IRQ_CLEAR_ADDR,v) +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_IRQ_CLEAR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_IRQ_CLEAR_ADDR,m,v,HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_IRQ_CLEAR_IN) +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_IRQ_CLEAR_CLEAR_BMSK 0x1 +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_IRQ_CLEAR_CLEAR_SHFT 0x0 + +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_SPARE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000474) +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_SPARE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000474) +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_SPARE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000474) +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_SPARE_RMSK 0xff +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_SPARE_ATTR 0x3 +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_SPARE_IN \ + in_dword_masked(HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_SPARE_ADDR, HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_SPARE_RMSK) +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_SPARE_INM(m) \ + in_dword_masked(HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_SPARE_ADDR, m) +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_SPARE_OUT(v) \ + out_dword(HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_SPARE_ADDR,v) +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_SPARE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_SPARE_ADDR,m,v,HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_SPARE_IN) +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_SPARE_SPARE_BMSK 0xff +#define HWIO_GCC_ANOC_PCIE_GDS_HW_CTRL_SPARE_SPARE_SHFT 0x0 + +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008915c) +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008915c) +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008915c) +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_RMSK 0xffffbfff +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_ATTR 0x3 +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_IN \ + in_dword_masked(HWIO_GCC_TURING_QTB_GDS_HW_CTRL_ADDR, HWIO_GCC_TURING_QTB_GDS_HW_CTRL_RMSK) +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_INM(m) \ + in_dword_masked(HWIO_GCC_TURING_QTB_GDS_HW_CTRL_ADDR, m) +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_OUT(v) \ + out_dword(HWIO_GCC_TURING_QTB_GDS_HW_CTRL_ADDR,v) +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TURING_QTB_GDS_HW_CTRL_ADDR,m,v,HWIO_GCC_TURING_QTB_GDS_HW_CTRL_IN) +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_PWR_ON_STATUS_BMSK 0x80000000 +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_PWR_ON_STATUS_SHFT 0x1f +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_RESERVE_30_29_BMSK 0x60000000 +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_RESERVE_30_29_SHFT 0x1d +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_HYS_TIMER_BMSK 0x1fe00000 +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_HYS_TIMER_SHFT 0x15 +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_MAX_RETRY_BMSK 0x1e0000 +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_MAX_RETRY_SHFT 0x11 +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_DENY_ENABLE_BMSK 0x10000 +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_DENY_ENABLE_SHFT 0x10 +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_COLLAPSE_OUT_BMSK 0x8000 +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_COLLAPSE_OUT_SHFT 0xf +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_HALT_ACK_TIMEOUT_BMSK 0x3fc0 +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_HALT_ACK_TIMEOUT_SHFT 0x6 +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_GDS_HW_STATE_BMSK 0x3e +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_GDS_HW_STATE_SHFT 0x1 +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_SW_OVERRIDE_SHFT 0x0 + +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_STATUS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00089160) +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_STATUS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00089160) +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_STATUS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00089160) +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_STATUS_RMSK 0xfffffffb +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_STATUS_ATTR 0x3 +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_STATUS_IN \ + in_dword_masked(HWIO_GCC_TURING_QTB_GDS_HW_CTRL_STATUS_ADDR, HWIO_GCC_TURING_QTB_GDS_HW_CTRL_STATUS_RMSK) +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_STATUS_INM(m) \ + in_dword_masked(HWIO_GCC_TURING_QTB_GDS_HW_CTRL_STATUS_ADDR, m) +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_STATUS_OUT(v) \ + out_dword(HWIO_GCC_TURING_QTB_GDS_HW_CTRL_STATUS_ADDR,v) +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_STATUS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TURING_QTB_GDS_HW_CTRL_STATUS_ADDR,m,v,HWIO_GCC_TURING_QTB_GDS_HW_CTRL_STATUS_IN) +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_STATUS_RESERVE_24_31_BMSK 0xff000000 +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_STATUS_RESERVE_24_31_SHFT 0x18 +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_STATUS_HALT1_REQ_STATUS_BMSK 0x800000 +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_STATUS_HALT1_REQ_STATUS_SHFT 0x17 +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_STATUS_HALT2_REQ_STATUS_BMSK 0x400000 +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_STATUS_HALT2_REQ_STATUS_SHFT 0x16 +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_STATUS_DVM_HALT1_REQ_STATUS_BMSK 0x200000 +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_STATUS_DVM_HALT1_REQ_STATUS_SHFT 0x15 +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_STATUS_DVM_HALT1_PWR_DOWN_ACK_STATUS_BMSK 0x100000 +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_STATUS_DVM_HALT1_PWR_DOWN_ACK_STATUS_SHFT 0x14 +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_STATUS_RESERVE_19_BMSK 0x80000 +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_STATUS_RESERVE_19_SHFT 0x13 +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_STATUS_DVM_HALT1_PWR_UP_ACK_STATUS_BMSK 0x40000 +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_STATUS_DVM_HALT1_PWR_UP_ACK_STATUS_SHFT 0x12 +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_STATUS_RESERVE_8_17_BMSK 0x3ff00 +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_STATUS_RESERVE_8_17_SHFT 0x8 +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_STATUS_HALT2_PWR_DOWN_ACK_STATUS_BMSK 0x80 +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_STATUS_HALT2_PWR_DOWN_ACK_STATUS_SHFT 0x7 +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_STATUS_HALT2_PWR_DOWN_DENY_STATUS_BMSK 0x40 +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_STATUS_HALT2_PWR_DOWN_DENY_STATUS_SHFT 0x6 +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_STATUS_HALT2_PWR_UP_ACK_STATUS_BMSK 0x20 +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_STATUS_HALT2_PWR_UP_ACK_STATUS_SHFT 0x5 +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_STATUS_HALT1_PWR_DOWN_ACK_STATUS_BMSK 0x10 +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_STATUS_HALT1_PWR_DOWN_ACK_STATUS_SHFT 0x4 +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_STATUS_DVM_HALT1_PWR_DOWN_DENY_STATUS_BMSK 0x8 +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_STATUS_DVM_HALT1_PWR_DOWN_DENY_STATUS_SHFT 0x3 +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_STATUS_HALT1_PWR_DOWN_DENY_STATUS_BMSK 0x2 +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_STATUS_HALT1_PWR_DOWN_DENY_STATUS_SHFT 0x1 +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_STATUS_HALT1_PWR_UP_ACK_STATUS_BMSK 0x1 +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_STATUS_HALT1_PWR_UP_ACK_STATUS_SHFT 0x0 + +#define HWIO_GCC_TURING_QTB_HALT_REQ_GDS_HW_CTRL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00089464) +#define HWIO_GCC_TURING_QTB_HALT_REQ_GDS_HW_CTRL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00089464) +#define HWIO_GCC_TURING_QTB_HALT_REQ_GDS_HW_CTRL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00089464) +#define HWIO_GCC_TURING_QTB_HALT_REQ_GDS_HW_CTRL_RMSK 0xffff +#define HWIO_GCC_TURING_QTB_HALT_REQ_GDS_HW_CTRL_ATTR 0x3 +#define HWIO_GCC_TURING_QTB_HALT_REQ_GDS_HW_CTRL_IN \ + in_dword_masked(HWIO_GCC_TURING_QTB_HALT_REQ_GDS_HW_CTRL_ADDR, HWIO_GCC_TURING_QTB_HALT_REQ_GDS_HW_CTRL_RMSK) +#define HWIO_GCC_TURING_QTB_HALT_REQ_GDS_HW_CTRL_INM(m) \ + in_dword_masked(HWIO_GCC_TURING_QTB_HALT_REQ_GDS_HW_CTRL_ADDR, m) +#define HWIO_GCC_TURING_QTB_HALT_REQ_GDS_HW_CTRL_OUT(v) \ + out_dword(HWIO_GCC_TURING_QTB_HALT_REQ_GDS_HW_CTRL_ADDR,v) +#define HWIO_GCC_TURING_QTB_HALT_REQ_GDS_HW_CTRL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TURING_QTB_HALT_REQ_GDS_HW_CTRL_ADDR,m,v,HWIO_GCC_TURING_QTB_HALT_REQ_GDS_HW_CTRL_IN) +#define HWIO_GCC_TURING_QTB_HALT_REQ_GDS_HW_CTRL_RESERVE_3_15_BMSK 0xfff8 +#define HWIO_GCC_TURING_QTB_HALT_REQ_GDS_HW_CTRL_RESERVE_3_15_SHFT 0x3 +#define HWIO_GCC_TURING_QTB_HALT_REQ_GDS_HW_CTRL_DVM_HALT_REQ_BMSK 0x4 +#define HWIO_GCC_TURING_QTB_HALT_REQ_GDS_HW_CTRL_DVM_HALT_REQ_SHFT 0x2 +#define HWIO_GCC_TURING_QTB_HALT_REQ_GDS_HW_CTRL_MMU_QTB_HALT_REQ_BMSK 0x2 +#define HWIO_GCC_TURING_QTB_HALT_REQ_GDS_HW_CTRL_MMU_QTB_HALT_REQ_SHFT 0x1 +#define HWIO_GCC_TURING_QTB_HALT_REQ_GDS_HW_CTRL_NOC_HALT_REQ_BMSK 0x1 +#define HWIO_GCC_TURING_QTB_HALT_REQ_GDS_HW_CTRL_NOC_HALT_REQ_SHFT 0x0 + +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_IRQ_STATUS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00089468) +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_IRQ_STATUS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00089468) +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_IRQ_STATUS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00089468) +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_IRQ_STATUS_RMSK 0x1 +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_IRQ_STATUS_ATTR 0x1 +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_IRQ_STATUS_IN \ + in_dword_masked(HWIO_GCC_TURING_QTB_GDS_HW_CTRL_IRQ_STATUS_ADDR, HWIO_GCC_TURING_QTB_GDS_HW_CTRL_IRQ_STATUS_RMSK) +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_IRQ_STATUS_INM(m) \ + in_dword_masked(HWIO_GCC_TURING_QTB_GDS_HW_CTRL_IRQ_STATUS_ADDR, m) +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_IRQ_STATUS_STATUS_BMSK 0x1 +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_IRQ_STATUS_STATUS_SHFT 0x0 + +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_IRQ_MASK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008946c) +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_IRQ_MASK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008946c) +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_IRQ_MASK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008946c) +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_IRQ_MASK_RMSK 0x1 +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_IRQ_MASK_ATTR 0x3 +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_IRQ_MASK_IN \ + in_dword_masked(HWIO_GCC_TURING_QTB_GDS_HW_CTRL_IRQ_MASK_ADDR, HWIO_GCC_TURING_QTB_GDS_HW_CTRL_IRQ_MASK_RMSK) +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_IRQ_MASK_INM(m) \ + in_dword_masked(HWIO_GCC_TURING_QTB_GDS_HW_CTRL_IRQ_MASK_ADDR, m) +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_IRQ_MASK_OUT(v) \ + out_dword(HWIO_GCC_TURING_QTB_GDS_HW_CTRL_IRQ_MASK_ADDR,v) +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_IRQ_MASK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TURING_QTB_GDS_HW_CTRL_IRQ_MASK_ADDR,m,v,HWIO_GCC_TURING_QTB_GDS_HW_CTRL_IRQ_MASK_IN) +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_IRQ_MASK_MASK_BMSK 0x1 +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_IRQ_MASK_MASK_SHFT 0x0 + +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_IRQ_CLEAR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00089470) +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_IRQ_CLEAR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00089470) +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_IRQ_CLEAR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00089470) +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_IRQ_CLEAR_RMSK 0x1 +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_IRQ_CLEAR_ATTR 0x3 +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_IRQ_CLEAR_IN \ + in_dword_masked(HWIO_GCC_TURING_QTB_GDS_HW_CTRL_IRQ_CLEAR_ADDR, HWIO_GCC_TURING_QTB_GDS_HW_CTRL_IRQ_CLEAR_RMSK) +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_IRQ_CLEAR_INM(m) \ + in_dword_masked(HWIO_GCC_TURING_QTB_GDS_HW_CTRL_IRQ_CLEAR_ADDR, m) +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_IRQ_CLEAR_OUT(v) \ + out_dword(HWIO_GCC_TURING_QTB_GDS_HW_CTRL_IRQ_CLEAR_ADDR,v) +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_IRQ_CLEAR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TURING_QTB_GDS_HW_CTRL_IRQ_CLEAR_ADDR,m,v,HWIO_GCC_TURING_QTB_GDS_HW_CTRL_IRQ_CLEAR_IN) +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_IRQ_CLEAR_CLEAR_BMSK 0x1 +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_IRQ_CLEAR_CLEAR_SHFT 0x0 + +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_SPARE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00089474) +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_SPARE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00089474) +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_SPARE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00089474) +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_SPARE_RMSK 0xff +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_SPARE_ATTR 0x3 +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_SPARE_IN \ + in_dword_masked(HWIO_GCC_TURING_QTB_GDS_HW_CTRL_SPARE_ADDR, HWIO_GCC_TURING_QTB_GDS_HW_CTRL_SPARE_RMSK) +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_SPARE_INM(m) \ + in_dword_masked(HWIO_GCC_TURING_QTB_GDS_HW_CTRL_SPARE_ADDR, m) +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_SPARE_OUT(v) \ + out_dword(HWIO_GCC_TURING_QTB_GDS_HW_CTRL_SPARE_ADDR,v) +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_SPARE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TURING_QTB_GDS_HW_CTRL_SPARE_ADDR,m,v,HWIO_GCC_TURING_QTB_GDS_HW_CTRL_SPARE_IN) +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_SPARE_SPARE_BMSK 0xff +#define HWIO_GCC_TURING_QTB_GDS_HW_CTRL_SPARE_SPARE_SHFT 0x0 + +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008f000) +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008f000) +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008f000) +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_RMSK 0xffffbfff +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_ATTR 0x3 +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_IN \ + in_dword_masked(HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_ADDR, HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_RMSK) +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_INM(m) \ + in_dword_masked(HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_ADDR, m) +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_OUT(v) \ + out_dword(HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_ADDR,v) +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_ADDR,m,v,HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_IN) +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_PWR_ON_STATUS_BMSK 0x80000000 +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_PWR_ON_STATUS_SHFT 0x1f +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_RESERVE_30_29_BMSK 0x60000000 +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_RESERVE_30_29_SHFT 0x1d +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_HYS_TIMER_BMSK 0x1fe00000 +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_HYS_TIMER_SHFT 0x15 +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_MAX_RETRY_BMSK 0x1e0000 +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_MAX_RETRY_SHFT 0x11 +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_DENY_ENABLE_BMSK 0x10000 +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_DENY_ENABLE_SHFT 0x10 +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_COLLAPSE_OUT_BMSK 0x8000 +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_COLLAPSE_OUT_SHFT 0xf +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_HALT_ACK_TIMEOUT_BMSK 0x3fc0 +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_HALT_ACK_TIMEOUT_SHFT 0x6 +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_GDS_HW_STATE_BMSK 0x3e +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_GDS_HW_STATE_SHFT 0x1 +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_SW_OVERRIDE_SHFT 0x0 + +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_STATUS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008f004) +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_STATUS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008f004) +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_STATUS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008f004) +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_STATUS_RMSK 0xfffffffb +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_STATUS_ATTR 0x3 +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_STATUS_IN \ + in_dword_masked(HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_STATUS_ADDR, HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_STATUS_RMSK) +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_STATUS_INM(m) \ + in_dword_masked(HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_STATUS_ADDR, m) +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_STATUS_OUT(v) \ + out_dword(HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_STATUS_ADDR,v) +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_STATUS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_STATUS_ADDR,m,v,HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_STATUS_IN) +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_STATUS_RESERVE_24_31_BMSK 0xff000000 +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_STATUS_RESERVE_24_31_SHFT 0x18 +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_STATUS_HALT1_REQ_STATUS_BMSK 0x800000 +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_STATUS_HALT1_REQ_STATUS_SHFT 0x17 +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_STATUS_HALT2_REQ_STATUS_BMSK 0x400000 +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_STATUS_HALT2_REQ_STATUS_SHFT 0x16 +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_STATUS_DVM_HALT1_REQ_STATUS_BMSK 0x200000 +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_STATUS_DVM_HALT1_REQ_STATUS_SHFT 0x15 +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_STATUS_DVM_HALT1_PWR_DOWN_ACK_STATUS_BMSK 0x100000 +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_STATUS_DVM_HALT1_PWR_DOWN_ACK_STATUS_SHFT 0x14 +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_STATUS_RESERVE_19_BMSK 0x80000 +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_STATUS_RESERVE_19_SHFT 0x13 +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_STATUS_DVM_HALT1_PWR_UP_ACK_STATUS_BMSK 0x40000 +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_STATUS_DVM_HALT1_PWR_UP_ACK_STATUS_SHFT 0x12 +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_STATUS_RESERVE_8_17_BMSK 0x3ff00 +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_STATUS_RESERVE_8_17_SHFT 0x8 +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_STATUS_HALT2_PWR_DOWN_ACK_STATUS_BMSK 0x80 +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_STATUS_HALT2_PWR_DOWN_ACK_STATUS_SHFT 0x7 +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_STATUS_HALT2_PWR_DOWN_DENY_STATUS_BMSK 0x40 +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_STATUS_HALT2_PWR_DOWN_DENY_STATUS_SHFT 0x6 +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_STATUS_HALT2_PWR_UP_ACK_STATUS_BMSK 0x20 +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_STATUS_HALT2_PWR_UP_ACK_STATUS_SHFT 0x5 +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_STATUS_HALT1_PWR_DOWN_ACK_STATUS_BMSK 0x10 +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_STATUS_HALT1_PWR_DOWN_ACK_STATUS_SHFT 0x4 +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_STATUS_DVM_HALT1_PWR_DOWN_DENY_STATUS_BMSK 0x8 +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_STATUS_DVM_HALT1_PWR_DOWN_DENY_STATUS_SHFT 0x3 +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_STATUS_HALT1_PWR_DOWN_DENY_STATUS_BMSK 0x2 +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_STATUS_HALT1_PWR_DOWN_DENY_STATUS_SHFT 0x1 +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_STATUS_HALT1_PWR_UP_ACK_STATUS_BMSK 0x1 +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_STATUS_HALT1_PWR_UP_ACK_STATUS_SHFT 0x0 + +#define HWIO_GCC_LPASS_QTB_HALT_REQ_GDS_HW_CTRL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008f008) +#define HWIO_GCC_LPASS_QTB_HALT_REQ_GDS_HW_CTRL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008f008) +#define HWIO_GCC_LPASS_QTB_HALT_REQ_GDS_HW_CTRL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008f008) +#define HWIO_GCC_LPASS_QTB_HALT_REQ_GDS_HW_CTRL_RMSK 0xffff +#define HWIO_GCC_LPASS_QTB_HALT_REQ_GDS_HW_CTRL_ATTR 0x3 +#define HWIO_GCC_LPASS_QTB_HALT_REQ_GDS_HW_CTRL_IN \ + in_dword_masked(HWIO_GCC_LPASS_QTB_HALT_REQ_GDS_HW_CTRL_ADDR, HWIO_GCC_LPASS_QTB_HALT_REQ_GDS_HW_CTRL_RMSK) +#define HWIO_GCC_LPASS_QTB_HALT_REQ_GDS_HW_CTRL_INM(m) \ + in_dword_masked(HWIO_GCC_LPASS_QTB_HALT_REQ_GDS_HW_CTRL_ADDR, m) +#define HWIO_GCC_LPASS_QTB_HALT_REQ_GDS_HW_CTRL_OUT(v) \ + out_dword(HWIO_GCC_LPASS_QTB_HALT_REQ_GDS_HW_CTRL_ADDR,v) +#define HWIO_GCC_LPASS_QTB_HALT_REQ_GDS_HW_CTRL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_LPASS_QTB_HALT_REQ_GDS_HW_CTRL_ADDR,m,v,HWIO_GCC_LPASS_QTB_HALT_REQ_GDS_HW_CTRL_IN) +#define HWIO_GCC_LPASS_QTB_HALT_REQ_GDS_HW_CTRL_RESERVE_3_15_BMSK 0xfff8 +#define HWIO_GCC_LPASS_QTB_HALT_REQ_GDS_HW_CTRL_RESERVE_3_15_SHFT 0x3 +#define HWIO_GCC_LPASS_QTB_HALT_REQ_GDS_HW_CTRL_DVM_HALT_REQ_BMSK 0x4 +#define HWIO_GCC_LPASS_QTB_HALT_REQ_GDS_HW_CTRL_DVM_HALT_REQ_SHFT 0x2 +#define HWIO_GCC_LPASS_QTB_HALT_REQ_GDS_HW_CTRL_MMU_QTB_HALT_REQ_BMSK 0x2 +#define HWIO_GCC_LPASS_QTB_HALT_REQ_GDS_HW_CTRL_MMU_QTB_HALT_REQ_SHFT 0x1 +#define HWIO_GCC_LPASS_QTB_HALT_REQ_GDS_HW_CTRL_NOC_HALT_REQ_BMSK 0x1 +#define HWIO_GCC_LPASS_QTB_HALT_REQ_GDS_HW_CTRL_NOC_HALT_REQ_SHFT 0x0 + +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_IRQ_STATUS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008f00c) +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_IRQ_STATUS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008f00c) +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_IRQ_STATUS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008f00c) +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_IRQ_STATUS_RMSK 0x1 +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_IRQ_STATUS_ATTR 0x1 +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_IRQ_STATUS_IN \ + in_dword_masked(HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_IRQ_STATUS_ADDR, HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_IRQ_STATUS_RMSK) +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_IRQ_STATUS_INM(m) \ + in_dword_masked(HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_IRQ_STATUS_ADDR, m) +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_IRQ_STATUS_STATUS_BMSK 0x1 +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_IRQ_STATUS_STATUS_SHFT 0x0 + +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_IRQ_MASK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008f010) +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_IRQ_MASK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008f010) +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_IRQ_MASK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008f010) +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_IRQ_MASK_RMSK 0x1 +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_IRQ_MASK_ATTR 0x3 +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_IRQ_MASK_IN \ + in_dword_masked(HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_IRQ_MASK_ADDR, HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_IRQ_MASK_RMSK) +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_IRQ_MASK_INM(m) \ + in_dword_masked(HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_IRQ_MASK_ADDR, m) +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_IRQ_MASK_OUT(v) \ + out_dword(HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_IRQ_MASK_ADDR,v) +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_IRQ_MASK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_IRQ_MASK_ADDR,m,v,HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_IRQ_MASK_IN) +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_IRQ_MASK_MASK_BMSK 0x1 +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_IRQ_MASK_MASK_SHFT 0x0 + +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_IRQ_CLEAR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008f014) +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_IRQ_CLEAR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008f014) +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_IRQ_CLEAR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008f014) +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_IRQ_CLEAR_RMSK 0x1 +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_IRQ_CLEAR_ATTR 0x3 +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_IRQ_CLEAR_IN \ + in_dword_masked(HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_IRQ_CLEAR_ADDR, HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_IRQ_CLEAR_RMSK) +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_IRQ_CLEAR_INM(m) \ + in_dword_masked(HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_IRQ_CLEAR_ADDR, m) +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_IRQ_CLEAR_OUT(v) \ + out_dword(HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_IRQ_CLEAR_ADDR,v) +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_IRQ_CLEAR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_IRQ_CLEAR_ADDR,m,v,HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_IRQ_CLEAR_IN) +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_IRQ_CLEAR_CLEAR_BMSK 0x1 +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_IRQ_CLEAR_CLEAR_SHFT 0x0 + +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_SPARE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008f018) +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_SPARE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008f018) +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_SPARE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008f018) +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_SPARE_RMSK 0xff +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_SPARE_ATTR 0x3 +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_SPARE_IN \ + in_dword_masked(HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_SPARE_ADDR, HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_SPARE_RMSK) +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_SPARE_INM(m) \ + in_dword_masked(HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_SPARE_ADDR, m) +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_SPARE_OUT(v) \ + out_dword(HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_SPARE_ADDR,v) +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_SPARE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_SPARE_ADDR,m,v,HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_SPARE_IN) +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_SPARE_SPARE_BMSK 0xff +#define HWIO_GCC_LPASS_QTB_GDS_HW_CTRL_SPARE_SPARE_SHFT 0x0 + +#define HWIO_GCC_ANOC_QTB_GDS_HW_CTRL_SPARE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00080890) +#define HWIO_GCC_ANOC_QTB_GDS_HW_CTRL_SPARE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00080890) +#define HWIO_GCC_ANOC_QTB_GDS_HW_CTRL_SPARE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00080890) +#define HWIO_GCC_ANOC_QTB_GDS_HW_CTRL_SPARE_RMSK 0xff +#define HWIO_GCC_ANOC_QTB_GDS_HW_CTRL_SPARE_ATTR 0x3 +#define HWIO_GCC_ANOC_QTB_GDS_HW_CTRL_SPARE_IN \ + in_dword_masked(HWIO_GCC_ANOC_QTB_GDS_HW_CTRL_SPARE_ADDR, HWIO_GCC_ANOC_QTB_GDS_HW_CTRL_SPARE_RMSK) +#define HWIO_GCC_ANOC_QTB_GDS_HW_CTRL_SPARE_INM(m) \ + in_dword_masked(HWIO_GCC_ANOC_QTB_GDS_HW_CTRL_SPARE_ADDR, m) +#define HWIO_GCC_ANOC_QTB_GDS_HW_CTRL_SPARE_OUT(v) \ + out_dword(HWIO_GCC_ANOC_QTB_GDS_HW_CTRL_SPARE_ADDR,v) +#define HWIO_GCC_ANOC_QTB_GDS_HW_CTRL_SPARE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ANOC_QTB_GDS_HW_CTRL_SPARE_ADDR,m,v,HWIO_GCC_ANOC_QTB_GDS_HW_CTRL_SPARE_IN) +#define HWIO_GCC_ANOC_QTB_GDS_HW_CTRL_SPARE_SPARE_BMSK 0xff +#define HWIO_GCC_ANOC_QTB_GDS_HW_CTRL_SPARE_SPARE_SHFT 0x0 + +#define HWIO_GCC_ANOC_QTB_RESET_CNTR_VALUE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00080894) +#define HWIO_GCC_ANOC_QTB_RESET_CNTR_VALUE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00080894) +#define HWIO_GCC_ANOC_QTB_RESET_CNTR_VALUE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00080894) +#define HWIO_GCC_ANOC_QTB_RESET_CNTR_VALUE_RMSK 0x3ff +#define HWIO_GCC_ANOC_QTB_RESET_CNTR_VALUE_ATTR 0x3 +#define HWIO_GCC_ANOC_QTB_RESET_CNTR_VALUE_IN \ + in_dword_masked(HWIO_GCC_ANOC_QTB_RESET_CNTR_VALUE_ADDR, HWIO_GCC_ANOC_QTB_RESET_CNTR_VALUE_RMSK) +#define HWIO_GCC_ANOC_QTB_RESET_CNTR_VALUE_INM(m) \ + in_dword_masked(HWIO_GCC_ANOC_QTB_RESET_CNTR_VALUE_ADDR, m) +#define HWIO_GCC_ANOC_QTB_RESET_CNTR_VALUE_OUT(v) \ + out_dword(HWIO_GCC_ANOC_QTB_RESET_CNTR_VALUE_ADDR,v) +#define HWIO_GCC_ANOC_QTB_RESET_CNTR_VALUE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ANOC_QTB_RESET_CNTR_VALUE_ADDR,m,v,HWIO_GCC_ANOC_QTB_RESET_CNTR_VALUE_IN) +#define HWIO_GCC_ANOC_QTB_RESET_CNTR_VALUE_COUNT_BMSK 0x3ff +#define HWIO_GCC_ANOC_QTB_RESET_CNTR_VALUE_COUNT_SHFT 0x0 + +#define HWIO_GCC_ANOC_QTB_PWR_QCHANNEL_HANDSHAKE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008089c) +#define HWIO_GCC_ANOC_QTB_PWR_QCHANNEL_HANDSHAKE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008089c) +#define HWIO_GCC_ANOC_QTB_PWR_QCHANNEL_HANDSHAKE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008089c) +#define HWIO_GCC_ANOC_QTB_PWR_QCHANNEL_HANDSHAKE_RMSK 0x3f +#define HWIO_GCC_ANOC_QTB_PWR_QCHANNEL_HANDSHAKE_ATTR 0x3 +#define HWIO_GCC_ANOC_QTB_PWR_QCHANNEL_HANDSHAKE_IN \ + in_dword_masked(HWIO_GCC_ANOC_QTB_PWR_QCHANNEL_HANDSHAKE_ADDR, HWIO_GCC_ANOC_QTB_PWR_QCHANNEL_HANDSHAKE_RMSK) +#define HWIO_GCC_ANOC_QTB_PWR_QCHANNEL_HANDSHAKE_INM(m) \ + in_dword_masked(HWIO_GCC_ANOC_QTB_PWR_QCHANNEL_HANDSHAKE_ADDR, m) +#define HWIO_GCC_ANOC_QTB_PWR_QCHANNEL_HANDSHAKE_OUT(v) \ + out_dword(HWIO_GCC_ANOC_QTB_PWR_QCHANNEL_HANDSHAKE_ADDR,v) +#define HWIO_GCC_ANOC_QTB_PWR_QCHANNEL_HANDSHAKE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ANOC_QTB_PWR_QCHANNEL_HANDSHAKE_ADDR,m,v,HWIO_GCC_ANOC_QTB_PWR_QCHANNEL_HANDSHAKE_IN) +#define HWIO_GCC_ANOC_QTB_PWR_QCHANNEL_HANDSHAKE_RESET_ALLOWED_BMSK 0x20 +#define HWIO_GCC_ANOC_QTB_PWR_QCHANNEL_HANDSHAKE_RESET_ALLOWED_SHFT 0x5 +#define HWIO_GCC_ANOC_QTB_PWR_QCHANNEL_HANDSHAKE_FSM_STATE_BMSK 0x1f +#define HWIO_GCC_ANOC_QTB_PWR_QCHANNEL_HANDSHAKE_FSM_STATE_SHFT 0x0 + +#define HWIO_GCC_ANOC_QTB_SREG_MISC_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00080480) +#define HWIO_GCC_ANOC_QTB_SREG_MISC_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00080480) +#define HWIO_GCC_ANOC_QTB_SREG_MISC_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00080480) +#define HWIO_GCC_ANOC_QTB_SREG_MISC_RMSK 0x3 +#define HWIO_GCC_ANOC_QTB_SREG_MISC_ATTR 0x3 +#define HWIO_GCC_ANOC_QTB_SREG_MISC_IN \ + in_dword_masked(HWIO_GCC_ANOC_QTB_SREG_MISC_ADDR, HWIO_GCC_ANOC_QTB_SREG_MISC_RMSK) +#define HWIO_GCC_ANOC_QTB_SREG_MISC_INM(m) \ + in_dword_masked(HWIO_GCC_ANOC_QTB_SREG_MISC_ADDR, m) +#define HWIO_GCC_ANOC_QTB_SREG_MISC_OUT(v) \ + out_dword(HWIO_GCC_ANOC_QTB_SREG_MISC_ADDR,v) +#define HWIO_GCC_ANOC_QTB_SREG_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ANOC_QTB_SREG_MISC_ADDR,m,v,HWIO_GCC_ANOC_QTB_SREG_MISC_IN) +#define HWIO_GCC_ANOC_QTB_SREG_MISC_QTB_2_MICRO_FORCE_MEM_CORE_ON_BMSK 0x2 +#define HWIO_GCC_ANOC_QTB_SREG_MISC_QTB_2_MICRO_FORCE_MEM_CORE_ON_SHFT 0x1 +#define HWIO_GCC_ANOC_QTB_SREG_MISC_QTB_1_MICRO_FORCE_MEM_CORE_ON_BMSK 0x1 +#define HWIO_GCC_ANOC_QTB_SREG_MISC_QTB_1_MICRO_FORCE_MEM_CORE_ON_SHFT 0x0 + +#define HWIO_GCC_LPASS_SREG_MISC_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008f01c) +#define HWIO_GCC_LPASS_SREG_MISC_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008f01c) +#define HWIO_GCC_LPASS_SREG_MISC_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008f01c) +#define HWIO_GCC_LPASS_SREG_MISC_RMSK 0x1 +#define HWIO_GCC_LPASS_SREG_MISC_ATTR 0x3 +#define HWIO_GCC_LPASS_SREG_MISC_IN \ + in_dword_masked(HWIO_GCC_LPASS_SREG_MISC_ADDR, HWIO_GCC_LPASS_SREG_MISC_RMSK) +#define HWIO_GCC_LPASS_SREG_MISC_INM(m) \ + in_dword_masked(HWIO_GCC_LPASS_SREG_MISC_ADDR, m) +#define HWIO_GCC_LPASS_SREG_MISC_OUT(v) \ + out_dword(HWIO_GCC_LPASS_SREG_MISC_ADDR,v) +#define HWIO_GCC_LPASS_SREG_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_LPASS_SREG_MISC_ADDR,m,v,HWIO_GCC_LPASS_SREG_MISC_IN) +#define HWIO_GCC_LPASS_SREG_MISC_AUDIO_QTB_MICRO_FORCE_MEM_CORE_ON_BMSK 0x1 +#define HWIO_GCC_LPASS_SREG_MISC_AUDIO_QTB_MICRO_FORCE_MEM_CORE_ON_SHFT 0x0 + +#define HWIO_GCC_MMNOC_SREG_MISC_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000c480) +#define HWIO_GCC_MMNOC_SREG_MISC_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c480) +#define HWIO_GCC_MMNOC_SREG_MISC_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c480) +#define HWIO_GCC_MMNOC_SREG_MISC_RMSK 0x3 +#define HWIO_GCC_MMNOC_SREG_MISC_ATTR 0x3 +#define HWIO_GCC_MMNOC_SREG_MISC_IN \ + in_dword_masked(HWIO_GCC_MMNOC_SREG_MISC_ADDR, HWIO_GCC_MMNOC_SREG_MISC_RMSK) +#define HWIO_GCC_MMNOC_SREG_MISC_INM(m) \ + in_dword_masked(HWIO_GCC_MMNOC_SREG_MISC_ADDR, m) +#define HWIO_GCC_MMNOC_SREG_MISC_OUT(v) \ + out_dword(HWIO_GCC_MMNOC_SREG_MISC_ADDR,v) +#define HWIO_GCC_MMNOC_SREG_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MMNOC_SREG_MISC_ADDR,m,v,HWIO_GCC_MMNOC_SREG_MISC_IN) +#define HWIO_GCC_MMNOC_SREG_MISC_HF_MICRO_FORCE_MEM_CORE_ON_BMSK 0x2 +#define HWIO_GCC_MMNOC_SREG_MISC_HF_MICRO_FORCE_MEM_CORE_ON_SHFT 0x1 +#define HWIO_GCC_MMNOC_SREG_MISC_SF_MICRO_FORCE_MEM_CORE_ON_BMSK 0x1 +#define HWIO_GCC_MMNOC_SREG_MISC_SF_MICRO_FORCE_MEM_CORE_ON_SHFT 0x0 + +#define HWIO_GCC_ANOC_PCIE_SREG_MISC_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000480) +#define HWIO_GCC_ANOC_PCIE_SREG_MISC_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000480) +#define HWIO_GCC_ANOC_PCIE_SREG_MISC_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000480) +#define HWIO_GCC_ANOC_PCIE_SREG_MISC_RMSK 0x1 +#define HWIO_GCC_ANOC_PCIE_SREG_MISC_ATTR 0x3 +#define HWIO_GCC_ANOC_PCIE_SREG_MISC_IN \ + in_dword_masked(HWIO_GCC_ANOC_PCIE_SREG_MISC_ADDR, HWIO_GCC_ANOC_PCIE_SREG_MISC_RMSK) +#define HWIO_GCC_ANOC_PCIE_SREG_MISC_INM(m) \ + in_dword_masked(HWIO_GCC_ANOC_PCIE_SREG_MISC_ADDR, m) +#define HWIO_GCC_ANOC_PCIE_SREG_MISC_OUT(v) \ + out_dword(HWIO_GCC_ANOC_PCIE_SREG_MISC_ADDR,v) +#define HWIO_GCC_ANOC_PCIE_SREG_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ANOC_PCIE_SREG_MISC_ADDR,m,v,HWIO_GCC_ANOC_PCIE_SREG_MISC_IN) +#define HWIO_GCC_ANOC_PCIE_SREG_MISC_AGGRE_NOC_PCIE_AXI_MICRO_FORCE_MEM_CORE_ON_BMSK 0x1 +#define HWIO_GCC_ANOC_PCIE_SREG_MISC_AGGRE_NOC_PCIE_AXI_MICRO_FORCE_MEM_CORE_ON_SHFT 0x0 + +#define HWIO_GCC_TURING_QTB_SREG_MISC_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00089494) +#define HWIO_GCC_TURING_QTB_SREG_MISC_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00089494) +#define HWIO_GCC_TURING_QTB_SREG_MISC_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00089494) +#define HWIO_GCC_TURING_QTB_SREG_MISC_RMSK 0x3 +#define HWIO_GCC_TURING_QTB_SREG_MISC_ATTR 0x3 +#define HWIO_GCC_TURING_QTB_SREG_MISC_IN \ + in_dword_masked(HWIO_GCC_TURING_QTB_SREG_MISC_ADDR, HWIO_GCC_TURING_QTB_SREG_MISC_RMSK) +#define HWIO_GCC_TURING_QTB_SREG_MISC_INM(m) \ + in_dword_masked(HWIO_GCC_TURING_QTB_SREG_MISC_ADDR, m) +#define HWIO_GCC_TURING_QTB_SREG_MISC_OUT(v) \ + out_dword(HWIO_GCC_TURING_QTB_SREG_MISC_ADDR,v) +#define HWIO_GCC_TURING_QTB_SREG_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TURING_QTB_SREG_MISC_ADDR,m,v,HWIO_GCC_TURING_QTB_SREG_MISC_IN) +#define HWIO_GCC_TURING_QTB_SREG_MISC_QTB_1_MICRO_FORCE_MEM_CORE_ON_BMSK 0x2 +#define HWIO_GCC_TURING_QTB_SREG_MISC_QTB_1_MICRO_FORCE_MEM_CORE_ON_SHFT 0x1 +#define HWIO_GCC_TURING_QTB_SREG_MISC_QTB_0_MICRO_FORCE_MEM_CORE_ON_BMSK 0x1 +#define HWIO_GCC_TURING_QTB_SREG_MISC_QTB_0_MICRO_FORCE_MEM_CORE_ON_SHFT 0x0 + +#define HWIO_GCC_MMU_TCU_SREG_MISC_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00083480) +#define HWIO_GCC_MMU_TCU_SREG_MISC_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00083480) +#define HWIO_GCC_MMU_TCU_SREG_MISC_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00083480) +#define HWIO_GCC_MMU_TCU_SREG_MISC_RMSK 0x1 +#define HWIO_GCC_MMU_TCU_SREG_MISC_ATTR 0x3 +#define HWIO_GCC_MMU_TCU_SREG_MISC_IN \ + in_dword_masked(HWIO_GCC_MMU_TCU_SREG_MISC_ADDR, HWIO_GCC_MMU_TCU_SREG_MISC_RMSK) +#define HWIO_GCC_MMU_TCU_SREG_MISC_INM(m) \ + in_dword_masked(HWIO_GCC_MMU_TCU_SREG_MISC_ADDR, m) +#define HWIO_GCC_MMU_TCU_SREG_MISC_OUT(v) \ + out_dword(HWIO_GCC_MMU_TCU_SREG_MISC_ADDR,v) +#define HWIO_GCC_MMU_TCU_SREG_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MMU_TCU_SREG_MISC_ADDR,m,v,HWIO_GCC_MMU_TCU_SREG_MISC_IN) +#define HWIO_GCC_MMU_TCU_SREG_MISC_MMU_TCU_MICRO_FORCE_MEM_CORE_ON_BMSK 0x1 +#define HWIO_GCC_MMU_TCU_SREG_MISC_MMU_TCU_MICRO_FORCE_MEM_CORE_ON_SHFT 0x0 + +#define HWIO_GCC_CAMERA_SREG_MISC_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00016480) +#define HWIO_GCC_CAMERA_SREG_MISC_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00016480) +#define HWIO_GCC_CAMERA_SREG_MISC_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00016480) +#define HWIO_GCC_CAMERA_SREG_MISC_RMSK 0x3 +#define HWIO_GCC_CAMERA_SREG_MISC_ATTR 0x3 +#define HWIO_GCC_CAMERA_SREG_MISC_IN \ + in_dword_masked(HWIO_GCC_CAMERA_SREG_MISC_ADDR, HWIO_GCC_CAMERA_SREG_MISC_RMSK) +#define HWIO_GCC_CAMERA_SREG_MISC_INM(m) \ + in_dword_masked(HWIO_GCC_CAMERA_SREG_MISC_ADDR, m) +#define HWIO_GCC_CAMERA_SREG_MISC_OUT(v) \ + out_dword(HWIO_GCC_CAMERA_SREG_MISC_ADDR,v) +#define HWIO_GCC_CAMERA_SREG_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CAMERA_SREG_MISC_ADDR,m,v,HWIO_GCC_CAMERA_SREG_MISC_IN) +#define HWIO_GCC_CAMERA_SREG_MISC_HF_AXI_MICRO_FORCE_MEM_CORE_ON_BMSK 0x2 +#define HWIO_GCC_CAMERA_SREG_MISC_HF_AXI_MICRO_FORCE_MEM_CORE_ON_SHFT 0x1 +#define HWIO_GCC_CAMERA_SREG_MISC_SF_AXI_MICRO_FORCE_MEM_CORE_ON_BMSK 0x1 +#define HWIO_GCC_CAMERA_SREG_MISC_SF_AXI_MICRO_FORCE_MEM_CORE_ON_SHFT 0x0 + +#define HWIO_GCC_DISP_SREG_MISC_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00017480) +#define HWIO_GCC_DISP_SREG_MISC_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017480) +#define HWIO_GCC_DISP_SREG_MISC_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017480) +#define HWIO_GCC_DISP_SREG_MISC_RMSK 0x3 +#define HWIO_GCC_DISP_SREG_MISC_ATTR 0x3 +#define HWIO_GCC_DISP_SREG_MISC_IN \ + in_dword_masked(HWIO_GCC_DISP_SREG_MISC_ADDR, HWIO_GCC_DISP_SREG_MISC_RMSK) +#define HWIO_GCC_DISP_SREG_MISC_INM(m) \ + in_dword_masked(HWIO_GCC_DISP_SREG_MISC_ADDR, m) +#define HWIO_GCC_DISP_SREG_MISC_OUT(v) \ + out_dword(HWIO_GCC_DISP_SREG_MISC_ADDR,v) +#define HWIO_GCC_DISP_SREG_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DISP_SREG_MISC_ADDR,m,v,HWIO_GCC_DISP_SREG_MISC_IN) +#define HWIO_GCC_DISP_SREG_MISC_HF_AXI_MICRO_FORCE_MEM_CORE_ON_BMSK 0x2 +#define HWIO_GCC_DISP_SREG_MISC_HF_AXI_MICRO_FORCE_MEM_CORE_ON_SHFT 0x1 +#define HWIO_GCC_DISP_SREG_MISC_SF_AXI_MICRO_FORCE_MEM_CORE_ON_BMSK 0x1 +#define HWIO_GCC_DISP_SREG_MISC_SF_AXI_MICRO_FORCE_MEM_CORE_ON_SHFT 0x0 + +#define HWIO_GCC_VIDEO_SREG_MISC_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00022480) +#define HWIO_GCC_VIDEO_SREG_MISC_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00022480) +#define HWIO_GCC_VIDEO_SREG_MISC_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00022480) +#define HWIO_GCC_VIDEO_SREG_MISC_RMSK 0x3 +#define HWIO_GCC_VIDEO_SREG_MISC_ATTR 0x3 +#define HWIO_GCC_VIDEO_SREG_MISC_IN \ + in_dword_masked(HWIO_GCC_VIDEO_SREG_MISC_ADDR, HWIO_GCC_VIDEO_SREG_MISC_RMSK) +#define HWIO_GCC_VIDEO_SREG_MISC_INM(m) \ + in_dword_masked(HWIO_GCC_VIDEO_SREG_MISC_ADDR, m) +#define HWIO_GCC_VIDEO_SREG_MISC_OUT(v) \ + out_dword(HWIO_GCC_VIDEO_SREG_MISC_ADDR,v) +#define HWIO_GCC_VIDEO_SREG_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_VIDEO_SREG_MISC_ADDR,m,v,HWIO_GCC_VIDEO_SREG_MISC_IN) +#define HWIO_GCC_VIDEO_SREG_MISC_AXI_1_MICRO_FORCE_MEM_CORE_ON_BMSK 0x2 +#define HWIO_GCC_VIDEO_SREG_MISC_AXI_1_MICRO_FORCE_MEM_CORE_ON_SHFT 0x1 +#define HWIO_GCC_VIDEO_SREG_MISC_AXI_0_MICRO_FORCE_MEM_CORE_ON_BMSK 0x1 +#define HWIO_GCC_VIDEO_SREG_MISC_AXI_0_MICRO_FORCE_MEM_CORE_ON_SHFT 0x0 + +#define HWIO_GCC_PCIE_0_SREG_MISC_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005b480) +#define HWIO_GCC_PCIE_0_SREG_MISC_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005b480) +#define HWIO_GCC_PCIE_0_SREG_MISC_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005b480) +#define HWIO_GCC_PCIE_0_SREG_MISC_RMSK 0x1 +#define HWIO_GCC_PCIE_0_SREG_MISC_ATTR 0x3 +#define HWIO_GCC_PCIE_0_SREG_MISC_IN \ + in_dword_masked(HWIO_GCC_PCIE_0_SREG_MISC_ADDR, HWIO_GCC_PCIE_0_SREG_MISC_RMSK) +#define HWIO_GCC_PCIE_0_SREG_MISC_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_0_SREG_MISC_ADDR, m) +#define HWIO_GCC_PCIE_0_SREG_MISC_OUT(v) \ + out_dword(HWIO_GCC_PCIE_0_SREG_MISC_ADDR,v) +#define HWIO_GCC_PCIE_0_SREG_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_0_SREG_MISC_ADDR,m,v,HWIO_GCC_PCIE_0_SREG_MISC_IN) +#define HWIO_GCC_PCIE_0_SREG_MISC_MSTR_AXI_MICRO_FORCE_MEM_CORE_ON_BMSK 0x1 +#define HWIO_GCC_PCIE_0_SREG_MISC_MSTR_AXI_MICRO_FORCE_MEM_CORE_ON_SHFT 0x0 + +#define HWIO_GCC_PCIE_1_SREG_MISC_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007d480) +#define HWIO_GCC_PCIE_1_SREG_MISC_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d480) +#define HWIO_GCC_PCIE_1_SREG_MISC_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d480) +#define HWIO_GCC_PCIE_1_SREG_MISC_RMSK 0x1 +#define HWIO_GCC_PCIE_1_SREG_MISC_ATTR 0x3 +#define HWIO_GCC_PCIE_1_SREG_MISC_IN \ + in_dword_masked(HWIO_GCC_PCIE_1_SREG_MISC_ADDR, HWIO_GCC_PCIE_1_SREG_MISC_RMSK) +#define HWIO_GCC_PCIE_1_SREG_MISC_INM(m) \ + in_dword_masked(HWIO_GCC_PCIE_1_SREG_MISC_ADDR, m) +#define HWIO_GCC_PCIE_1_SREG_MISC_OUT(v) \ + out_dword(HWIO_GCC_PCIE_1_SREG_MISC_ADDR,v) +#define HWIO_GCC_PCIE_1_SREG_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PCIE_1_SREG_MISC_ADDR,m,v,HWIO_GCC_PCIE_1_SREG_MISC_IN) +#define HWIO_GCC_PCIE_1_SREG_MISC_MSTR_AXI_MICRO_FORCE_MEM_CORE_ON_BMSK 0x1 +#define HWIO_GCC_PCIE_1_SREG_MISC_MSTR_AXI_MICRO_FORCE_MEM_CORE_ON_SHFT 0x0 + +#define HWIO_GCC_SP_VOTE_GPU_SMMU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00076000) +#define HWIO_GCC_SP_VOTE_GPU_SMMU_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00076000) +#define HWIO_GCC_SP_VOTE_GPU_SMMU_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00076000) +#define HWIO_GCC_SP_VOTE_GPU_SMMU_CLK_RMSK 0x80000001 +#define HWIO_GCC_SP_VOTE_GPU_SMMU_CLK_ATTR 0x3 +#define HWIO_GCC_SP_VOTE_GPU_SMMU_CLK_IN \ + in_dword_masked(HWIO_GCC_SP_VOTE_GPU_SMMU_CLK_ADDR, HWIO_GCC_SP_VOTE_GPU_SMMU_CLK_RMSK) +#define HWIO_GCC_SP_VOTE_GPU_SMMU_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_SP_VOTE_GPU_SMMU_CLK_ADDR, m) +#define HWIO_GCC_SP_VOTE_GPU_SMMU_CLK_OUT(v) \ + out_dword(HWIO_GCC_SP_VOTE_GPU_SMMU_CLK_ADDR,v) +#define HWIO_GCC_SP_VOTE_GPU_SMMU_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SP_VOTE_GPU_SMMU_CLK_ADDR,m,v,HWIO_GCC_SP_VOTE_GPU_SMMU_CLK_IN) +#define HWIO_GCC_SP_VOTE_GPU_SMMU_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SP_VOTE_GPU_SMMU_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SP_VOTE_GPU_SMMU_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SP_VOTE_GPU_SMMU_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SP_VOTE_GPU_SMMU_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_VOTE_GPU_SMMU_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SP_VOTE_LPASS_QTB_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00076004) +#define HWIO_GCC_SP_VOTE_LPASS_QTB_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00076004) +#define HWIO_GCC_SP_VOTE_LPASS_QTB_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00076004) +#define HWIO_GCC_SP_VOTE_LPASS_QTB_CLK_RMSK 0x80000001 +#define HWIO_GCC_SP_VOTE_LPASS_QTB_CLK_ATTR 0x3 +#define HWIO_GCC_SP_VOTE_LPASS_QTB_CLK_IN \ + in_dword_masked(HWIO_GCC_SP_VOTE_LPASS_QTB_CLK_ADDR, HWIO_GCC_SP_VOTE_LPASS_QTB_CLK_RMSK) +#define HWIO_GCC_SP_VOTE_LPASS_QTB_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_SP_VOTE_LPASS_QTB_CLK_ADDR, m) +#define HWIO_GCC_SP_VOTE_LPASS_QTB_CLK_OUT(v) \ + out_dword(HWIO_GCC_SP_VOTE_LPASS_QTB_CLK_ADDR,v) +#define HWIO_GCC_SP_VOTE_LPASS_QTB_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SP_VOTE_LPASS_QTB_CLK_ADDR,m,v,HWIO_GCC_SP_VOTE_LPASS_QTB_CLK_IN) +#define HWIO_GCC_SP_VOTE_LPASS_QTB_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SP_VOTE_LPASS_QTB_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SP_VOTE_LPASS_QTB_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SP_VOTE_LPASS_QTB_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SP_VOTE_LPASS_QTB_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_VOTE_LPASS_QTB_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00076008) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00076008) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00076008) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_RMSK 0x80000001 +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_ATTR 0x3 +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_IN \ + in_dword_masked(HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_ADDR, HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_RMSK) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_ADDR, m) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_OUT(v) \ + out_dword(HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_ADDR,v) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_ADDR,m,v,HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_IN) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007600c) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007600c) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007600c) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_RMSK 0x80000001 +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_ATTR 0x3 +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_IN \ + in_dword_masked(HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_ADDR, HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_RMSK) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_ADDR, m) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_OUT(v) \ + out_dword(HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_ADDR,v) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_ADDR,m,v,HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_IN) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00076010) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00076010) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00076010) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_RMSK 0x80000001 +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_ATTR 0x3 +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_IN \ + in_dword_masked(HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_ADDR, HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_RMSK) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_ADDR, m) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_OUT(v) \ + out_dword(HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_ADDR,v) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_ADDR,m,v,HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_IN) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_SF_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00076014) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_SF_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00076014) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_SF_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00076014) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_SF_CLK_RMSK 0x80000001 +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_SF_CLK_ATTR 0x3 +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_SF_CLK_IN \ + in_dword_masked(HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_SF_CLK_ADDR, HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_SF_CLK_RMSK) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_SF_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_SF_CLK_ADDR, m) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_SF_CLK_OUT(v) \ + out_dword(HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_SF_CLK_ADDR,v) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_SF_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_SF_CLK_ADDR,m,v,HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_SF_CLK_IN) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_SF_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_SF_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_SF_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_SF_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_SF_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_SF_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF01_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00076018) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF01_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00076018) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF01_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00076018) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF01_CLK_RMSK 0x80000001 +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF01_CLK_ATTR 0x3 +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF01_CLK_IN \ + in_dword_masked(HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF01_CLK_ADDR, HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF01_CLK_RMSK) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF01_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF01_CLK_ADDR, m) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF01_CLK_OUT(v) \ + out_dword(HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF01_CLK_ADDR,v) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF01_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF01_CLK_ADDR,m,v,HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF01_CLK_IN) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF01_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF01_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF01_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF01_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF01_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF01_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SP_VOTE_TURING_MMU_QTB0_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00076020) +#define HWIO_GCC_SP_VOTE_TURING_MMU_QTB0_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00076020) +#define HWIO_GCC_SP_VOTE_TURING_MMU_QTB0_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00076020) +#define HWIO_GCC_SP_VOTE_TURING_MMU_QTB0_CLK_RMSK 0x80000001 +#define HWIO_GCC_SP_VOTE_TURING_MMU_QTB0_CLK_ATTR 0x3 +#define HWIO_GCC_SP_VOTE_TURING_MMU_QTB0_CLK_IN \ + in_dword_masked(HWIO_GCC_SP_VOTE_TURING_MMU_QTB0_CLK_ADDR, HWIO_GCC_SP_VOTE_TURING_MMU_QTB0_CLK_RMSK) +#define HWIO_GCC_SP_VOTE_TURING_MMU_QTB0_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_SP_VOTE_TURING_MMU_QTB0_CLK_ADDR, m) +#define HWIO_GCC_SP_VOTE_TURING_MMU_QTB0_CLK_OUT(v) \ + out_dword(HWIO_GCC_SP_VOTE_TURING_MMU_QTB0_CLK_ADDR,v) +#define HWIO_GCC_SP_VOTE_TURING_MMU_QTB0_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SP_VOTE_TURING_MMU_QTB0_CLK_ADDR,m,v,HWIO_GCC_SP_VOTE_TURING_MMU_QTB0_CLK_IN) +#define HWIO_GCC_SP_VOTE_TURING_MMU_QTB0_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SP_VOTE_TURING_MMU_QTB0_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SP_VOTE_TURING_MMU_QTB0_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SP_VOTE_TURING_MMU_QTB0_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SP_VOTE_TURING_MMU_QTB0_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_VOTE_TURING_MMU_QTB0_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00076028) +#define HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00076028) +#define HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00076028) +#define HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_CLK_RMSK 0x80000001 +#define HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_CLK_ATTR 0x3 +#define HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_CLK_IN \ + in_dword_masked(HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_CLK_ADDR, HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_CLK_RMSK) +#define HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_CLK_ADDR, m) +#define HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_CLK_OUT(v) \ + out_dword(HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_CLK_ADDR,v) +#define HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_CLK_ADDR,m,v,HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_CLK_IN) +#define HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SP_VOTE_MMU_TCU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007602c) +#define HWIO_GCC_SP_VOTE_MMU_TCU_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007602c) +#define HWIO_GCC_SP_VOTE_MMU_TCU_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007602c) +#define HWIO_GCC_SP_VOTE_MMU_TCU_CLK_RMSK 0x80000001 +#define HWIO_GCC_SP_VOTE_MMU_TCU_CLK_ATTR 0x3 +#define HWIO_GCC_SP_VOTE_MMU_TCU_CLK_IN \ + in_dword_masked(HWIO_GCC_SP_VOTE_MMU_TCU_CLK_ADDR, HWIO_GCC_SP_VOTE_MMU_TCU_CLK_RMSK) +#define HWIO_GCC_SP_VOTE_MMU_TCU_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_SP_VOTE_MMU_TCU_CLK_ADDR, m) +#define HWIO_GCC_SP_VOTE_MMU_TCU_CLK_OUT(v) \ + out_dword(HWIO_GCC_SP_VOTE_MMU_TCU_CLK_ADDR,v) +#define HWIO_GCC_SP_VOTE_MMU_TCU_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SP_VOTE_MMU_TCU_CLK_ADDR,m,v,HWIO_GCC_SP_VOTE_MMU_TCU_CLK_IN) +#define HWIO_GCC_SP_VOTE_MMU_TCU_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SP_VOTE_MMU_TCU_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SP_VOTE_MMU_TCU_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SP_VOTE_MMU_TCU_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SP_VOTE_MMU_TCU_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_VOTE_MMU_TCU_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SP_VOTE_GPU_SMMU_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007603c) +#define HWIO_GCC_SP_VOTE_GPU_SMMU_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007603c) +#define HWIO_GCC_SP_VOTE_GPU_SMMU_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007603c) +#define HWIO_GCC_SP_VOTE_GPU_SMMU_GDS_RMSK 0x80000001 +#define HWIO_GCC_SP_VOTE_GPU_SMMU_GDS_ATTR 0x3 +#define HWIO_GCC_SP_VOTE_GPU_SMMU_GDS_IN \ + in_dword_masked(HWIO_GCC_SP_VOTE_GPU_SMMU_GDS_ADDR, HWIO_GCC_SP_VOTE_GPU_SMMU_GDS_RMSK) +#define HWIO_GCC_SP_VOTE_GPU_SMMU_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_SP_VOTE_GPU_SMMU_GDS_ADDR, m) +#define HWIO_GCC_SP_VOTE_GPU_SMMU_GDS_OUT(v) \ + out_dword(HWIO_GCC_SP_VOTE_GPU_SMMU_GDS_ADDR,v) +#define HWIO_GCC_SP_VOTE_GPU_SMMU_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SP_VOTE_GPU_SMMU_GDS_ADDR,m,v,HWIO_GCC_SP_VOTE_GPU_SMMU_GDS_IN) +#define HWIO_GCC_SP_VOTE_GPU_SMMU_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_SP_VOTE_GPU_SMMU_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_SP_VOTE_GPU_SMMU_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_SP_VOTE_GPU_SMMU_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_SP_VOTE_GPU_SMMU_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_VOTE_GPU_SMMU_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SP_VOTE_LPASS_QTB_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00076040) +#define HWIO_GCC_SP_VOTE_LPASS_QTB_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00076040) +#define HWIO_GCC_SP_VOTE_LPASS_QTB_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00076040) +#define HWIO_GCC_SP_VOTE_LPASS_QTB_GDS_RMSK 0x80000001 +#define HWIO_GCC_SP_VOTE_LPASS_QTB_GDS_ATTR 0x3 +#define HWIO_GCC_SP_VOTE_LPASS_QTB_GDS_IN \ + in_dword_masked(HWIO_GCC_SP_VOTE_LPASS_QTB_GDS_ADDR, HWIO_GCC_SP_VOTE_LPASS_QTB_GDS_RMSK) +#define HWIO_GCC_SP_VOTE_LPASS_QTB_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_SP_VOTE_LPASS_QTB_GDS_ADDR, m) +#define HWIO_GCC_SP_VOTE_LPASS_QTB_GDS_OUT(v) \ + out_dword(HWIO_GCC_SP_VOTE_LPASS_QTB_GDS_ADDR,v) +#define HWIO_GCC_SP_VOTE_LPASS_QTB_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SP_VOTE_LPASS_QTB_GDS_ADDR,m,v,HWIO_GCC_SP_VOTE_LPASS_QTB_GDS_IN) +#define HWIO_GCC_SP_VOTE_LPASS_QTB_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_SP_VOTE_LPASS_QTB_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_SP_VOTE_LPASS_QTB_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_SP_VOTE_LPASS_QTB_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_SP_VOTE_LPASS_QTB_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_VOTE_LPASS_QTB_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00076044) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00076044) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00076044) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_RMSK 0x80000001 +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_ATTR 0x3 +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_IN \ + in_dword_masked(HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_ADDR, HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_RMSK) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_ADDR, m) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_OUT(v) \ + out_dword(HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_ADDR,v) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_ADDR,m,v,HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_IN) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00076048) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00076048) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00076048) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_RMSK 0x80000001 +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_ATTR 0x3 +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_IN \ + in_dword_masked(HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_ADDR, HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_RMSK) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_ADDR, m) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_OUT(v) \ + out_dword(HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_ADDR,v) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_ADDR,m,v,HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_IN) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007604c) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007604c) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007604c) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_RMSK 0x80000001 +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_ATTR 0x3 +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_IN \ + in_dword_masked(HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_ADDR, HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_RMSK) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_ADDR, m) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_OUT(v) \ + out_dword(HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_ADDR,v) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_ADDR,m,v,HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_IN) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF01_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00076050) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF01_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00076050) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF01_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00076050) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF01_GDS_RMSK 0x80000001 +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF01_GDS_ATTR 0x3 +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF01_GDS_IN \ + in_dword_masked(HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF01_GDS_ADDR, HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF01_GDS_RMSK) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF01_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF01_GDS_ADDR, m) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF01_GDS_OUT(v) \ + out_dword(HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF01_GDS_ADDR,v) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF01_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF01_GDS_ADDR,m,v,HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF01_GDS_IN) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF01_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF01_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF01_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF01_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF01_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF01_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_SF_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00076054) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_SF_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00076054) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_SF_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00076054) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_SF_GDS_RMSK 0x80000001 +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_SF_GDS_ATTR 0x3 +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_SF_GDS_IN \ + in_dword_masked(HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_SF_GDS_ADDR, HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_SF_GDS_RMSK) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_SF_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_SF_GDS_ADDR, m) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_SF_GDS_OUT(v) \ + out_dword(HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_SF_GDS_ADDR,v) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_SF_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_SF_GDS_ADDR,m,v,HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_SF_GDS_IN) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_SF_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_SF_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_SF_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_SF_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_SF_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_SF_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SP_VOTE_TURING_MMU_QTB0_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007605c) +#define HWIO_GCC_SP_VOTE_TURING_MMU_QTB0_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007605c) +#define HWIO_GCC_SP_VOTE_TURING_MMU_QTB0_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007605c) +#define HWIO_GCC_SP_VOTE_TURING_MMU_QTB0_GDS_RMSK 0x80000001 +#define HWIO_GCC_SP_VOTE_TURING_MMU_QTB0_GDS_ATTR 0x3 +#define HWIO_GCC_SP_VOTE_TURING_MMU_QTB0_GDS_IN \ + in_dword_masked(HWIO_GCC_SP_VOTE_TURING_MMU_QTB0_GDS_ADDR, HWIO_GCC_SP_VOTE_TURING_MMU_QTB0_GDS_RMSK) +#define HWIO_GCC_SP_VOTE_TURING_MMU_QTB0_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_SP_VOTE_TURING_MMU_QTB0_GDS_ADDR, m) +#define HWIO_GCC_SP_VOTE_TURING_MMU_QTB0_GDS_OUT(v) \ + out_dword(HWIO_GCC_SP_VOTE_TURING_MMU_QTB0_GDS_ADDR,v) +#define HWIO_GCC_SP_VOTE_TURING_MMU_QTB0_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SP_VOTE_TURING_MMU_QTB0_GDS_ADDR,m,v,HWIO_GCC_SP_VOTE_TURING_MMU_QTB0_GDS_IN) +#define HWIO_GCC_SP_VOTE_TURING_MMU_QTB0_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_SP_VOTE_TURING_MMU_QTB0_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_SP_VOTE_TURING_MMU_QTB0_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_SP_VOTE_TURING_MMU_QTB0_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_SP_VOTE_TURING_MMU_QTB0_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_VOTE_TURING_MMU_QTB0_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00076064) +#define HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00076064) +#define HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00076064) +#define HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_GDS_RMSK 0x80000001 +#define HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_GDS_ATTR 0x3 +#define HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_GDS_IN \ + in_dword_masked(HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_GDS_ADDR, HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_GDS_RMSK) +#define HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_GDS_ADDR, m) +#define HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_GDS_OUT(v) \ + out_dword(HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_GDS_ADDR,v) +#define HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_GDS_ADDR,m,v,HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_GDS_IN) +#define HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SP_VOTE_MMU_TCU_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00076068) +#define HWIO_GCC_SP_VOTE_MMU_TCU_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00076068) +#define HWIO_GCC_SP_VOTE_MMU_TCU_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00076068) +#define HWIO_GCC_SP_VOTE_MMU_TCU_GDS_RMSK 0x80000001 +#define HWIO_GCC_SP_VOTE_MMU_TCU_GDS_ATTR 0x3 +#define HWIO_GCC_SP_VOTE_MMU_TCU_GDS_IN \ + in_dword_masked(HWIO_GCC_SP_VOTE_MMU_TCU_GDS_ADDR, HWIO_GCC_SP_VOTE_MMU_TCU_GDS_RMSK) +#define HWIO_GCC_SP_VOTE_MMU_TCU_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_SP_VOTE_MMU_TCU_GDS_ADDR, m) +#define HWIO_GCC_SP_VOTE_MMU_TCU_GDS_OUT(v) \ + out_dword(HWIO_GCC_SP_VOTE_MMU_TCU_GDS_ADDR,v) +#define HWIO_GCC_SP_VOTE_MMU_TCU_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SP_VOTE_MMU_TCU_GDS_ADDR,m,v,HWIO_GCC_SP_VOTE_MMU_TCU_GDS_IN) +#define HWIO_GCC_SP_VOTE_MMU_TCU_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_SP_VOTE_MMU_TCU_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_SP_VOTE_MMU_TCU_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_SP_VOTE_MMU_TCU_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_SP_VOTE_MMU_TCU_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_VOTE_MMU_TCU_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF23_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00076070) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF23_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00076070) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF23_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00076070) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF23_CLK_RMSK 0x80000001 +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF23_CLK_ATTR 0x3 +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF23_CLK_IN \ + in_dword_masked(HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF23_CLK_ADDR, HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF23_CLK_RMSK) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF23_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF23_CLK_ADDR, m) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF23_CLK_OUT(v) \ + out_dword(HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF23_CLK_ADDR,v) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF23_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF23_CLK_ADDR,m,v,HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF23_CLK_IN) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF23_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF23_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF23_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF23_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF23_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF23_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF23_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00076078) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF23_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00076078) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF23_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00076078) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF23_GDS_RMSK 0x80000001 +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF23_GDS_ATTR 0x3 +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF23_GDS_IN \ + in_dword_masked(HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF23_GDS_ADDR, HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF23_GDS_RMSK) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF23_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF23_GDS_ADDR, m) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF23_GDS_OUT(v) \ + out_dword(HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF23_GDS_ADDR,v) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF23_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF23_GDS_ADDR,m,v,HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF23_GDS_IN) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF23_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF23_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF23_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF23_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF23_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_QTB_HF23_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_VOTE_GPU_SMMU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00077000) +#define HWIO_GCC_MSS_VOTE_GPU_SMMU_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00077000) +#define HWIO_GCC_MSS_VOTE_GPU_SMMU_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00077000) +#define HWIO_GCC_MSS_VOTE_GPU_SMMU_CLK_RMSK 0x80000001 +#define HWIO_GCC_MSS_VOTE_GPU_SMMU_CLK_ATTR 0x3 +#define HWIO_GCC_MSS_VOTE_GPU_SMMU_CLK_IN \ + in_dword_masked(HWIO_GCC_MSS_VOTE_GPU_SMMU_CLK_ADDR, HWIO_GCC_MSS_VOTE_GPU_SMMU_CLK_RMSK) +#define HWIO_GCC_MSS_VOTE_GPU_SMMU_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_VOTE_GPU_SMMU_CLK_ADDR, m) +#define HWIO_GCC_MSS_VOTE_GPU_SMMU_CLK_OUT(v) \ + out_dword(HWIO_GCC_MSS_VOTE_GPU_SMMU_CLK_ADDR,v) +#define HWIO_GCC_MSS_VOTE_GPU_SMMU_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_VOTE_GPU_SMMU_CLK_ADDR,m,v,HWIO_GCC_MSS_VOTE_GPU_SMMU_CLK_IN) +#define HWIO_GCC_MSS_VOTE_GPU_SMMU_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_MSS_VOTE_GPU_SMMU_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_MSS_VOTE_GPU_SMMU_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_MSS_VOTE_GPU_SMMU_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_MSS_VOTE_GPU_SMMU_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_VOTE_GPU_SMMU_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_VOTE_LPASS_QTB_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00077004) +#define HWIO_GCC_MSS_VOTE_LPASS_QTB_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00077004) +#define HWIO_GCC_MSS_VOTE_LPASS_QTB_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00077004) +#define HWIO_GCC_MSS_VOTE_LPASS_QTB_CLK_RMSK 0x80000001 +#define HWIO_GCC_MSS_VOTE_LPASS_QTB_CLK_ATTR 0x3 +#define HWIO_GCC_MSS_VOTE_LPASS_QTB_CLK_IN \ + in_dword_masked(HWIO_GCC_MSS_VOTE_LPASS_QTB_CLK_ADDR, HWIO_GCC_MSS_VOTE_LPASS_QTB_CLK_RMSK) +#define HWIO_GCC_MSS_VOTE_LPASS_QTB_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_VOTE_LPASS_QTB_CLK_ADDR, m) +#define HWIO_GCC_MSS_VOTE_LPASS_QTB_CLK_OUT(v) \ + out_dword(HWIO_GCC_MSS_VOTE_LPASS_QTB_CLK_ADDR,v) +#define HWIO_GCC_MSS_VOTE_LPASS_QTB_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_VOTE_LPASS_QTB_CLK_ADDR,m,v,HWIO_GCC_MSS_VOTE_LPASS_QTB_CLK_IN) +#define HWIO_GCC_MSS_VOTE_LPASS_QTB_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_MSS_VOTE_LPASS_QTB_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_MSS_VOTE_LPASS_QTB_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_MSS_VOTE_LPASS_QTB_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_MSS_VOTE_LPASS_QTB_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_VOTE_LPASS_QTB_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB1_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00077008) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB1_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00077008) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB1_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00077008) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB1_CLK_RMSK 0x80000001 +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB1_CLK_ATTR 0x3 +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB1_CLK_IN \ + in_dword_masked(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB1_CLK_ADDR, HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB1_CLK_RMSK) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB1_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB1_CLK_ADDR, m) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB1_CLK_OUT(v) \ + out_dword(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB1_CLK_ADDR,v) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB1_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB1_CLK_ADDR,m,v,HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB1_CLK_IN) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB1_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB1_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB1_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB1_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB1_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB1_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB2_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007700c) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB2_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007700c) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB2_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007700c) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB2_CLK_RMSK 0x80000001 +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB2_CLK_ATTR 0x3 +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB2_CLK_IN \ + in_dword_masked(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB2_CLK_ADDR, HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB2_CLK_RMSK) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB2_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB2_CLK_ADDR, m) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB2_CLK_OUT(v) \ + out_dword(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB2_CLK_ADDR,v) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB2_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB2_CLK_ADDR,m,v,HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB2_CLK_IN) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB2_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB2_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB2_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB2_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB2_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB2_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00077010) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00077010) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00077010) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_RMSK 0x80000001 +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_ATTR 0x3 +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_IN \ + in_dword_masked(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_ADDR, HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_RMSK) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_ADDR, m) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_OUT(v) \ + out_dword(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_ADDR,v) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_ADDR,m,v,HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_IN) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_SF_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00077014) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_SF_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00077014) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_SF_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00077014) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_SF_CLK_RMSK 0x80000001 +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_SF_CLK_ATTR 0x3 +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_SF_CLK_IN \ + in_dword_masked(HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_SF_CLK_ADDR, HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_SF_CLK_RMSK) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_SF_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_SF_CLK_ADDR, m) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_SF_CLK_OUT(v) \ + out_dword(HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_SF_CLK_ADDR,v) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_SF_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_SF_CLK_ADDR,m,v,HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_SF_CLK_IN) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_SF_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_SF_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_SF_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_SF_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_SF_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_SF_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF01_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00077018) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF01_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00077018) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF01_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00077018) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF01_CLK_RMSK 0x80000001 +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF01_CLK_ATTR 0x3 +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF01_CLK_IN \ + in_dword_masked(HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF01_CLK_ADDR, HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF01_CLK_RMSK) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF01_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF01_CLK_ADDR, m) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF01_CLK_OUT(v) \ + out_dword(HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF01_CLK_ADDR,v) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF01_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF01_CLK_ADDR,m,v,HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF01_CLK_IN) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF01_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF01_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF01_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF01_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF01_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF01_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_VOTE_TURING_MMU_QTB0_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00077020) +#define HWIO_GCC_MSS_VOTE_TURING_MMU_QTB0_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00077020) +#define HWIO_GCC_MSS_VOTE_TURING_MMU_QTB0_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00077020) +#define HWIO_GCC_MSS_VOTE_TURING_MMU_QTB0_CLK_RMSK 0x80000001 +#define HWIO_GCC_MSS_VOTE_TURING_MMU_QTB0_CLK_ATTR 0x3 +#define HWIO_GCC_MSS_VOTE_TURING_MMU_QTB0_CLK_IN \ + in_dword_masked(HWIO_GCC_MSS_VOTE_TURING_MMU_QTB0_CLK_ADDR, HWIO_GCC_MSS_VOTE_TURING_MMU_QTB0_CLK_RMSK) +#define HWIO_GCC_MSS_VOTE_TURING_MMU_QTB0_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_VOTE_TURING_MMU_QTB0_CLK_ADDR, m) +#define HWIO_GCC_MSS_VOTE_TURING_MMU_QTB0_CLK_OUT(v) \ + out_dword(HWIO_GCC_MSS_VOTE_TURING_MMU_QTB0_CLK_ADDR,v) +#define HWIO_GCC_MSS_VOTE_TURING_MMU_QTB0_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_VOTE_TURING_MMU_QTB0_CLK_ADDR,m,v,HWIO_GCC_MSS_VOTE_TURING_MMU_QTB0_CLK_IN) +#define HWIO_GCC_MSS_VOTE_TURING_MMU_QTB0_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_MSS_VOTE_TURING_MMU_QTB0_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_MSS_VOTE_TURING_MMU_QTB0_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_MSS_VOTE_TURING_MMU_QTB0_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_MSS_VOTE_TURING_MMU_QTB0_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_VOTE_TURING_MMU_QTB0_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00077028) +#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00077028) +#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00077028) +#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_RMSK 0x80000001 +#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_ATTR 0x3 +#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_IN \ + in_dword_masked(HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_ADDR, HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_RMSK) +#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_ADDR, m) +#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_OUT(v) \ + out_dword(HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_ADDR,v) +#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_ADDR,m,v,HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_IN) +#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007702c) +#define HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007702c) +#define HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007702c) +#define HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_RMSK 0x80000001 +#define HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_ATTR 0x3 +#define HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_IN \ + in_dword_masked(HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_ADDR, HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_RMSK) +#define HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_ADDR, m) +#define HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_OUT(v) \ + out_dword(HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_ADDR,v) +#define HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_ADDR,m,v,HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_IN) +#define HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_VOTE_GPU_SMMU_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007703c) +#define HWIO_GCC_MSS_VOTE_GPU_SMMU_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007703c) +#define HWIO_GCC_MSS_VOTE_GPU_SMMU_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007703c) +#define HWIO_GCC_MSS_VOTE_GPU_SMMU_GDS_RMSK 0x80000001 +#define HWIO_GCC_MSS_VOTE_GPU_SMMU_GDS_ATTR 0x3 +#define HWIO_GCC_MSS_VOTE_GPU_SMMU_GDS_IN \ + in_dword_masked(HWIO_GCC_MSS_VOTE_GPU_SMMU_GDS_ADDR, HWIO_GCC_MSS_VOTE_GPU_SMMU_GDS_RMSK) +#define HWIO_GCC_MSS_VOTE_GPU_SMMU_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_VOTE_GPU_SMMU_GDS_ADDR, m) +#define HWIO_GCC_MSS_VOTE_GPU_SMMU_GDS_OUT(v) \ + out_dword(HWIO_GCC_MSS_VOTE_GPU_SMMU_GDS_ADDR,v) +#define HWIO_GCC_MSS_VOTE_GPU_SMMU_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_VOTE_GPU_SMMU_GDS_ADDR,m,v,HWIO_GCC_MSS_VOTE_GPU_SMMU_GDS_IN) +#define HWIO_GCC_MSS_VOTE_GPU_SMMU_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_MSS_VOTE_GPU_SMMU_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_MSS_VOTE_GPU_SMMU_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_MSS_VOTE_GPU_SMMU_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_MSS_VOTE_GPU_SMMU_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_VOTE_GPU_SMMU_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_VOTE_LPASS_QTB_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00077040) +#define HWIO_GCC_MSS_VOTE_LPASS_QTB_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00077040) +#define HWIO_GCC_MSS_VOTE_LPASS_QTB_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00077040) +#define HWIO_GCC_MSS_VOTE_LPASS_QTB_GDS_RMSK 0x80000001 +#define HWIO_GCC_MSS_VOTE_LPASS_QTB_GDS_ATTR 0x3 +#define HWIO_GCC_MSS_VOTE_LPASS_QTB_GDS_IN \ + in_dword_masked(HWIO_GCC_MSS_VOTE_LPASS_QTB_GDS_ADDR, HWIO_GCC_MSS_VOTE_LPASS_QTB_GDS_RMSK) +#define HWIO_GCC_MSS_VOTE_LPASS_QTB_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_VOTE_LPASS_QTB_GDS_ADDR, m) +#define HWIO_GCC_MSS_VOTE_LPASS_QTB_GDS_OUT(v) \ + out_dword(HWIO_GCC_MSS_VOTE_LPASS_QTB_GDS_ADDR,v) +#define HWIO_GCC_MSS_VOTE_LPASS_QTB_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_VOTE_LPASS_QTB_GDS_ADDR,m,v,HWIO_GCC_MSS_VOTE_LPASS_QTB_GDS_IN) +#define HWIO_GCC_MSS_VOTE_LPASS_QTB_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_MSS_VOTE_LPASS_QTB_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_MSS_VOTE_LPASS_QTB_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_MSS_VOTE_LPASS_QTB_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_MSS_VOTE_LPASS_QTB_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_VOTE_LPASS_QTB_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB1_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00077044) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB1_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00077044) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB1_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00077044) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB1_GDS_RMSK 0x80000001 +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB1_GDS_ATTR 0x3 +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB1_GDS_IN \ + in_dword_masked(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB1_GDS_ADDR, HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB1_GDS_RMSK) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB1_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB1_GDS_ADDR, m) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB1_GDS_OUT(v) \ + out_dword(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB1_GDS_ADDR,v) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB1_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB1_GDS_ADDR,m,v,HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB1_GDS_IN) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB1_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB1_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB1_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB1_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB1_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB1_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB2_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00077048) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB2_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00077048) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB2_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00077048) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB2_GDS_RMSK 0x80000001 +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB2_GDS_ATTR 0x3 +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB2_GDS_IN \ + in_dword_masked(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB2_GDS_ADDR, HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB2_GDS_RMSK) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB2_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB2_GDS_ADDR, m) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB2_GDS_OUT(v) \ + out_dword(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB2_GDS_ADDR,v) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB2_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB2_GDS_ADDR,m,v,HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB2_GDS_IN) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB2_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB2_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB2_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB2_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB2_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB2_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007704c) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007704c) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007704c) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_RMSK 0x80000001 +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_ATTR 0x3 +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_IN \ + in_dword_masked(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_ADDR, HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_RMSK) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_ADDR, m) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_OUT(v) \ + out_dword(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_ADDR,v) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_ADDR,m,v,HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_IN) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF01_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00077050) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF01_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00077050) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF01_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00077050) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF01_GDS_RMSK 0x80000001 +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF01_GDS_ATTR 0x3 +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF01_GDS_IN \ + in_dword_masked(HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF01_GDS_ADDR, HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF01_GDS_RMSK) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF01_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF01_GDS_ADDR, m) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF01_GDS_OUT(v) \ + out_dword(HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF01_GDS_ADDR,v) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF01_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF01_GDS_ADDR,m,v,HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF01_GDS_IN) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF01_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF01_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF01_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF01_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF01_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF01_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_SF_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00077054) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_SF_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00077054) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_SF_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00077054) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_SF_GDS_RMSK 0x80000001 +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_SF_GDS_ATTR 0x3 +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_SF_GDS_IN \ + in_dword_masked(HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_SF_GDS_ADDR, HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_SF_GDS_RMSK) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_SF_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_SF_GDS_ADDR, m) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_SF_GDS_OUT(v) \ + out_dword(HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_SF_GDS_ADDR,v) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_SF_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_SF_GDS_ADDR,m,v,HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_SF_GDS_IN) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_SF_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_SF_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_SF_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_SF_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_SF_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_SF_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_VOTE_TURING_MMU_QTB0_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007705c) +#define HWIO_GCC_MSS_VOTE_TURING_MMU_QTB0_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007705c) +#define HWIO_GCC_MSS_VOTE_TURING_MMU_QTB0_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007705c) +#define HWIO_GCC_MSS_VOTE_TURING_MMU_QTB0_GDS_RMSK 0x80000001 +#define HWIO_GCC_MSS_VOTE_TURING_MMU_QTB0_GDS_ATTR 0x3 +#define HWIO_GCC_MSS_VOTE_TURING_MMU_QTB0_GDS_IN \ + in_dword_masked(HWIO_GCC_MSS_VOTE_TURING_MMU_QTB0_GDS_ADDR, HWIO_GCC_MSS_VOTE_TURING_MMU_QTB0_GDS_RMSK) +#define HWIO_GCC_MSS_VOTE_TURING_MMU_QTB0_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_VOTE_TURING_MMU_QTB0_GDS_ADDR, m) +#define HWIO_GCC_MSS_VOTE_TURING_MMU_QTB0_GDS_OUT(v) \ + out_dword(HWIO_GCC_MSS_VOTE_TURING_MMU_QTB0_GDS_ADDR,v) +#define HWIO_GCC_MSS_VOTE_TURING_MMU_QTB0_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_VOTE_TURING_MMU_QTB0_GDS_ADDR,m,v,HWIO_GCC_MSS_VOTE_TURING_MMU_QTB0_GDS_IN) +#define HWIO_GCC_MSS_VOTE_TURING_MMU_QTB0_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_MSS_VOTE_TURING_MMU_QTB0_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_MSS_VOTE_TURING_MMU_QTB0_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_MSS_VOTE_TURING_MMU_QTB0_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_MSS_VOTE_TURING_MMU_QTB0_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_VOTE_TURING_MMU_QTB0_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00077064) +#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00077064) +#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00077064) +#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_GDS_RMSK 0x80000001 +#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_GDS_ATTR 0x3 +#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_GDS_IN \ + in_dword_masked(HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_GDS_ADDR, HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_GDS_RMSK) +#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_GDS_ADDR, m) +#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_GDS_OUT(v) \ + out_dword(HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_GDS_ADDR,v) +#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_GDS_ADDR,m,v,HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_GDS_IN) +#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_VOTE_MMU_TCU_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00077068) +#define HWIO_GCC_MSS_VOTE_MMU_TCU_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00077068) +#define HWIO_GCC_MSS_VOTE_MMU_TCU_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00077068) +#define HWIO_GCC_MSS_VOTE_MMU_TCU_GDS_RMSK 0x80000001 +#define HWIO_GCC_MSS_VOTE_MMU_TCU_GDS_ATTR 0x3 +#define HWIO_GCC_MSS_VOTE_MMU_TCU_GDS_IN \ + in_dword_masked(HWIO_GCC_MSS_VOTE_MMU_TCU_GDS_ADDR, HWIO_GCC_MSS_VOTE_MMU_TCU_GDS_RMSK) +#define HWIO_GCC_MSS_VOTE_MMU_TCU_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_VOTE_MMU_TCU_GDS_ADDR, m) +#define HWIO_GCC_MSS_VOTE_MMU_TCU_GDS_OUT(v) \ + out_dword(HWIO_GCC_MSS_VOTE_MMU_TCU_GDS_ADDR,v) +#define HWIO_GCC_MSS_VOTE_MMU_TCU_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_VOTE_MMU_TCU_GDS_ADDR,m,v,HWIO_GCC_MSS_VOTE_MMU_TCU_GDS_IN) +#define HWIO_GCC_MSS_VOTE_MMU_TCU_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_MSS_VOTE_MMU_TCU_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_MSS_VOTE_MMU_TCU_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_MSS_VOTE_MMU_TCU_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_MSS_VOTE_MMU_TCU_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_VOTE_MMU_TCU_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF23_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00077070) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF23_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00077070) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF23_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00077070) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF23_CLK_RMSK 0x80000001 +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF23_CLK_ATTR 0x3 +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF23_CLK_IN \ + in_dword_masked(HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF23_CLK_ADDR, HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF23_CLK_RMSK) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF23_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF23_CLK_ADDR, m) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF23_CLK_OUT(v) \ + out_dword(HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF23_CLK_ADDR,v) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF23_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF23_CLK_ADDR,m,v,HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF23_CLK_IN) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF23_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF23_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF23_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF23_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF23_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF23_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF23_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00077078) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF23_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00077078) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF23_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00077078) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF23_GDS_RMSK 0x80000001 +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF23_GDS_ATTR 0x3 +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF23_GDS_IN \ + in_dword_masked(HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF23_GDS_ADDR, HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF23_GDS_RMSK) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF23_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF23_GDS_ADDR, m) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF23_GDS_OUT(v) \ + out_dword(HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF23_GDS_ADDR,v) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF23_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF23_GDS_ADDR,m,v,HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF23_GDS_IN) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF23_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF23_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF23_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF23_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF23_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_QTB_HF23_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00019000) +#define HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00019000) +#define HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00019000) +#define HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_CLK_RMSK 0x80000001 +#define HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_CLK_ATTR 0x3 +#define HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_CLK_IN \ + in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_CLK_ADDR, HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_CLK_RMSK) +#define HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_CLK_ADDR, m) +#define HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_CLK_OUT(v) \ + out_dword(HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_CLK_ADDR,v) +#define HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_CLK_ADDR,m,v,HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_CLK_IN) +#define HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TURING_DSP_VOTE_LPASS_QTB_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00019004) +#define HWIO_GCC_TURING_DSP_VOTE_LPASS_QTB_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00019004) +#define HWIO_GCC_TURING_DSP_VOTE_LPASS_QTB_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00019004) +#define HWIO_GCC_TURING_DSP_VOTE_LPASS_QTB_CLK_RMSK 0x80000001 +#define HWIO_GCC_TURING_DSP_VOTE_LPASS_QTB_CLK_ATTR 0x3 +#define HWIO_GCC_TURING_DSP_VOTE_LPASS_QTB_CLK_IN \ + in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_LPASS_QTB_CLK_ADDR, HWIO_GCC_TURING_DSP_VOTE_LPASS_QTB_CLK_RMSK) +#define HWIO_GCC_TURING_DSP_VOTE_LPASS_QTB_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_LPASS_QTB_CLK_ADDR, m) +#define HWIO_GCC_TURING_DSP_VOTE_LPASS_QTB_CLK_OUT(v) \ + out_dword(HWIO_GCC_TURING_DSP_VOTE_LPASS_QTB_CLK_ADDR,v) +#define HWIO_GCC_TURING_DSP_VOTE_LPASS_QTB_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TURING_DSP_VOTE_LPASS_QTB_CLK_ADDR,m,v,HWIO_GCC_TURING_DSP_VOTE_LPASS_QTB_CLK_IN) +#define HWIO_GCC_TURING_DSP_VOTE_LPASS_QTB_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TURING_DSP_VOTE_LPASS_QTB_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TURING_DSP_VOTE_LPASS_QTB_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_TURING_DSP_VOTE_LPASS_QTB_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_TURING_DSP_VOTE_LPASS_QTB_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_VOTE_LPASS_QTB_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00019008) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00019008) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00019008) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_RMSK 0x80000001 +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_ATTR 0x3 +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_IN \ + in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_ADDR, HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_RMSK) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_ADDR, m) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_OUT(v) \ + out_dword(HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_ADDR,v) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_ADDR,m,v,HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_IN) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB1_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001900c) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001900c) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001900c) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_RMSK 0x80000001 +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_ATTR 0x3 +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_IN \ + in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_ADDR, HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_RMSK) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_ADDR, m) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_OUT(v) \ + out_dword(HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_ADDR,v) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_ADDR,m,v,HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_IN) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB2_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00019010) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00019010) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00019010) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_RMSK 0x80000001 +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_ATTR 0x3 +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_IN \ + in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_ADDR, HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_RMSK) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_ADDR, m) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_OUT(v) \ + out_dword(HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_ADDR,v) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_ADDR,m,v,HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_IN) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_SF_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00019014) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_SF_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00019014) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_SF_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00019014) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_SF_CLK_RMSK 0x80000001 +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_SF_CLK_ATTR 0x3 +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_SF_CLK_IN \ + in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_SF_CLK_ADDR, HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_SF_CLK_RMSK) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_SF_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_SF_CLK_ADDR, m) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_SF_CLK_OUT(v) \ + out_dword(HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_SF_CLK_ADDR,v) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_SF_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_SF_CLK_ADDR,m,v,HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_SF_CLK_IN) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_SF_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_SF_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_SF_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_SF_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_SF_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_SF_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF01_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00019018) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF01_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00019018) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF01_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00019018) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF01_CLK_RMSK 0x80000001 +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF01_CLK_ATTR 0x3 +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF01_CLK_IN \ + in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF01_CLK_ADDR, HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF01_CLK_RMSK) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF01_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF01_CLK_ADDR, m) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF01_CLK_OUT(v) \ + out_dword(HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF01_CLK_ADDR,v) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF01_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF01_CLK_ADDR,m,v,HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF01_CLK_IN) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF01_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF01_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF01_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF01_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF01_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF01_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_QTB0_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00019020) +#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_QTB0_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00019020) +#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_QTB0_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00019020) +#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_QTB0_CLK_RMSK 0x80000001 +#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_QTB0_CLK_ATTR 0x3 +#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_QTB0_CLK_IN \ + in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_QTB0_CLK_ADDR, HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_QTB0_CLK_RMSK) +#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_QTB0_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_QTB0_CLK_ADDR, m) +#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_QTB0_CLK_OUT(v) \ + out_dword(HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_QTB0_CLK_ADDR,v) +#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_QTB0_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_QTB0_CLK_ADDR,m,v,HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_QTB0_CLK_IN) +#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_QTB0_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_QTB0_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_QTB0_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_QTB0_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_QTB0_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_QTB0_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00019028) +#define HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00019028) +#define HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00019028) +#define HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_CLK_RMSK 0x80000001 +#define HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_CLK_ATTR 0x3 +#define HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_CLK_IN \ + in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_CLK_ADDR, HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_CLK_RMSK) +#define HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_CLK_ADDR, m) +#define HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_CLK_OUT(v) \ + out_dword(HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_CLK_ADDR,v) +#define HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_CLK_ADDR,m,v,HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_CLK_IN) +#define HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001902c) +#define HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001902c) +#define HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001902c) +#define HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_CLK_RMSK 0x80000001 +#define HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_CLK_ATTR 0x3 +#define HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_CLK_IN \ + in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_CLK_ADDR, HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_CLK_RMSK) +#define HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_CLK_ADDR, m) +#define HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_CLK_OUT(v) \ + out_dword(HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_CLK_ADDR,v) +#define HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_CLK_ADDR,m,v,HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_CLK_IN) +#define HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001903c) +#define HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001903c) +#define HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001903c) +#define HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_GDS_RMSK 0x80000001 +#define HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_GDS_ATTR 0x3 +#define HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_GDS_IN \ + in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_GDS_ADDR, HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_GDS_RMSK) +#define HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_GDS_ADDR, m) +#define HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_GDS_OUT(v) \ + out_dword(HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_GDS_ADDR,v) +#define HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_GDS_ADDR,m,v,HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_GDS_IN) +#define HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TURING_DSP_VOTE_LPASS_QTB_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00019040) +#define HWIO_GCC_TURING_DSP_VOTE_LPASS_QTB_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00019040) +#define HWIO_GCC_TURING_DSP_VOTE_LPASS_QTB_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00019040) +#define HWIO_GCC_TURING_DSP_VOTE_LPASS_QTB_GDS_RMSK 0x80000001 +#define HWIO_GCC_TURING_DSP_VOTE_LPASS_QTB_GDS_ATTR 0x3 +#define HWIO_GCC_TURING_DSP_VOTE_LPASS_QTB_GDS_IN \ + in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_LPASS_QTB_GDS_ADDR, HWIO_GCC_TURING_DSP_VOTE_LPASS_QTB_GDS_RMSK) +#define HWIO_GCC_TURING_DSP_VOTE_LPASS_QTB_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_LPASS_QTB_GDS_ADDR, m) +#define HWIO_GCC_TURING_DSP_VOTE_LPASS_QTB_GDS_OUT(v) \ + out_dword(HWIO_GCC_TURING_DSP_VOTE_LPASS_QTB_GDS_ADDR,v) +#define HWIO_GCC_TURING_DSP_VOTE_LPASS_QTB_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TURING_DSP_VOTE_LPASS_QTB_GDS_ADDR,m,v,HWIO_GCC_TURING_DSP_VOTE_LPASS_QTB_GDS_IN) +#define HWIO_GCC_TURING_DSP_VOTE_LPASS_QTB_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_TURING_DSP_VOTE_LPASS_QTB_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_TURING_DSP_VOTE_LPASS_QTB_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_TURING_DSP_VOTE_LPASS_QTB_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_TURING_DSP_VOTE_LPASS_QTB_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_VOTE_LPASS_QTB_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00019044) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00019044) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00019044) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_RMSK 0x80000001 +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_ATTR 0x3 +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_IN \ + in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_ADDR, HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_RMSK) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_ADDR, m) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_OUT(v) \ + out_dword(HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_ADDR,v) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_ADDR,m,v,HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_IN) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB1_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00019048) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00019048) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00019048) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_RMSK 0x80000001 +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_ATTR 0x3 +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_IN \ + in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_ADDR, HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_RMSK) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_ADDR, m) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_OUT(v) \ + out_dword(HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_ADDR,v) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_ADDR,m,v,HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_IN) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB2_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001904c) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001904c) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001904c) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_RMSK 0x80000001 +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_ATTR 0x3 +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_IN \ + in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_ADDR, HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_RMSK) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_ADDR, m) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_OUT(v) \ + out_dword(HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_ADDR,v) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_ADDR,m,v,HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_IN) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF01_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00019050) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF01_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00019050) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF01_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00019050) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF01_GDS_RMSK 0x80000001 +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF01_GDS_ATTR 0x3 +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF01_GDS_IN \ + in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF01_GDS_ADDR, HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF01_GDS_RMSK) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF01_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF01_GDS_ADDR, m) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF01_GDS_OUT(v) \ + out_dword(HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF01_GDS_ADDR,v) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF01_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF01_GDS_ADDR,m,v,HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF01_GDS_IN) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF01_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF01_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF01_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF01_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF01_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF01_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_SF_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00019054) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_SF_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00019054) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_SF_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00019054) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_SF_GDS_RMSK 0x80000001 +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_SF_GDS_ATTR 0x3 +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_SF_GDS_IN \ + in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_SF_GDS_ADDR, HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_SF_GDS_RMSK) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_SF_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_SF_GDS_ADDR, m) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_SF_GDS_OUT(v) \ + out_dword(HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_SF_GDS_ADDR,v) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_SF_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_SF_GDS_ADDR,m,v,HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_SF_GDS_IN) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_SF_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_SF_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_SF_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_SF_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_SF_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_SF_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_QTB0_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001905c) +#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_QTB0_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001905c) +#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_QTB0_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001905c) +#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_QTB0_GDS_RMSK 0x80000001 +#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_QTB0_GDS_ATTR 0x3 +#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_QTB0_GDS_IN \ + in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_QTB0_GDS_ADDR, HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_QTB0_GDS_RMSK) +#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_QTB0_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_QTB0_GDS_ADDR, m) +#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_QTB0_GDS_OUT(v) \ + out_dword(HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_QTB0_GDS_ADDR,v) +#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_QTB0_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_QTB0_GDS_ADDR,m,v,HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_QTB0_GDS_IN) +#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_QTB0_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_QTB0_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_QTB0_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_QTB0_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_QTB0_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_QTB0_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00019064) +#define HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00019064) +#define HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00019064) +#define HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_GDS_RMSK 0x80000001 +#define HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_GDS_ATTR 0x3 +#define HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_GDS_IN \ + in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_GDS_ADDR, HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_GDS_RMSK) +#define HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_GDS_ADDR, m) +#define HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_GDS_OUT(v) \ + out_dword(HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_GDS_ADDR,v) +#define HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_GDS_ADDR,m,v,HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_GDS_IN) +#define HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00019068) +#define HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00019068) +#define HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00019068) +#define HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_GDS_RMSK 0x80000001 +#define HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_GDS_ATTR 0x3 +#define HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_GDS_IN \ + in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_GDS_ADDR, HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_GDS_RMSK) +#define HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_GDS_ADDR, m) +#define HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_GDS_OUT(v) \ + out_dword(HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_GDS_ADDR,v) +#define HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_GDS_ADDR,m,v,HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_GDS_IN) +#define HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF23_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00019070) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF23_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00019070) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF23_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00019070) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF23_CLK_RMSK 0x80000001 +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF23_CLK_ATTR 0x3 +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF23_CLK_IN \ + in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF23_CLK_ADDR, HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF23_CLK_RMSK) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF23_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF23_CLK_ADDR, m) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF23_CLK_OUT(v) \ + out_dword(HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF23_CLK_ADDR,v) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF23_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF23_CLK_ADDR,m,v,HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF23_CLK_IN) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF23_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF23_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF23_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF23_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF23_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF23_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF23_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00019078) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF23_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00019078) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF23_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00019078) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF23_GDS_RMSK 0x80000001 +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF23_GDS_ATTR 0x3 +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF23_GDS_IN \ + in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF23_GDS_ADDR, HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF23_GDS_RMSK) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF23_GDS_INM(m) \ + in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF23_GDS_ADDR, m) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF23_GDS_OUT(v) \ + out_dword(HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF23_GDS_ADDR,v) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF23_GDS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF23_GDS_ADDR,m,v,HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF23_GDS_IN) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF23_GDS_PWR_ON_BMSK 0x80000000 +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF23_GDS_PWR_ON_SHFT 0x1f +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF23_GDS_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF23_GDS_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF23_GDS_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF23_GDS_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TURING_DSP_VOTE_QDSS_APB_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00019088) +#define HWIO_GCC_TURING_DSP_VOTE_QDSS_APB_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00019088) +#define HWIO_GCC_TURING_DSP_VOTE_QDSS_APB_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00019088) +#define HWIO_GCC_TURING_DSP_VOTE_QDSS_APB_CLK_RMSK 0x80000001 +#define HWIO_GCC_TURING_DSP_VOTE_QDSS_APB_CLK_ATTR 0x3 +#define HWIO_GCC_TURING_DSP_VOTE_QDSS_APB_CLK_IN \ + in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_QDSS_APB_CLK_ADDR, HWIO_GCC_TURING_DSP_VOTE_QDSS_APB_CLK_RMSK) +#define HWIO_GCC_TURING_DSP_VOTE_QDSS_APB_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_QDSS_APB_CLK_ADDR, m) +#define HWIO_GCC_TURING_DSP_VOTE_QDSS_APB_CLK_OUT(v) \ + out_dword(HWIO_GCC_TURING_DSP_VOTE_QDSS_APB_CLK_ADDR,v) +#define HWIO_GCC_TURING_DSP_VOTE_QDSS_APB_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TURING_DSP_VOTE_QDSS_APB_CLK_ADDR,m,v,HWIO_GCC_TURING_DSP_VOTE_QDSS_APB_CLK_IN) +#define HWIO_GCC_TURING_DSP_VOTE_QDSS_APB_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_TURING_DSP_VOTE_QDSS_APB_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_TURING_DSP_VOTE_QDSS_APB_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_TURING_DSP_VOTE_QDSS_APB_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_TURING_DSP_VOTE_QDSS_APB_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_VOTE_QDSS_APB_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00041124) +#define HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00041124) +#define HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00041124) +#define HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_RMSK 0x80000001 +#define HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_ATTR 0x3 +#define HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_IN \ + in_dword_masked(HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_ADDR, HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_RMSK) +#define HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_ADDR, m) +#define HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_OUT(v) \ + out_dword(HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_ADDR,v) +#define HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_ADDR,m,v,HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_IN) +#define HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00025124) +#define HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00025124) +#define HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00025124) +#define HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_RMSK 0x80000001 +#define HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_ATTR 0x3 +#define HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_IN \ + in_dword_masked(HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_ADDR, HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_RMSK) +#define HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_ADDR, m) +#define HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_OUT(v) \ + out_dword(HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_ADDR,v) +#define HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_ADDR,m,v,HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_IN) +#define HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00042124) +#define HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00042124) +#define HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00042124) +#define HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_RMSK 0x80000001 +#define HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_ATTR 0x3 +#define HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_IN \ + in_dword_masked(HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_ADDR, HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_RMSK) +#define HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_ADDR, m) +#define HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_OUT(v) \ + out_dword(HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_ADDR,v) +#define HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_ADDR,m,v,HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_IN) +#define HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00043124) +#define HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00043124) +#define HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00043124) +#define HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_RMSK 0x80000001 +#define HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_ATTR 0x3 +#define HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_IN \ + in_dword_masked(HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_ADDR, HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_RMSK) +#define HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_ADDR, m) +#define HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_OUT(v) \ + out_dword(HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_ADDR,v) +#define HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_ADDR,m,v,HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_IN) +#define HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_LPASS_DSP_VOTE_QDSS_APB_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00045124) +#define HWIO_GCC_LPASS_DSP_VOTE_QDSS_APB_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00045124) +#define HWIO_GCC_LPASS_DSP_VOTE_QDSS_APB_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00045124) +#define HWIO_GCC_LPASS_DSP_VOTE_QDSS_APB_CLK_RMSK 0x80000001 +#define HWIO_GCC_LPASS_DSP_VOTE_QDSS_APB_CLK_ATTR 0x3 +#define HWIO_GCC_LPASS_DSP_VOTE_QDSS_APB_CLK_IN \ + in_dword_masked(HWIO_GCC_LPASS_DSP_VOTE_QDSS_APB_CLK_ADDR, HWIO_GCC_LPASS_DSP_VOTE_QDSS_APB_CLK_RMSK) +#define HWIO_GCC_LPASS_DSP_VOTE_QDSS_APB_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_LPASS_DSP_VOTE_QDSS_APB_CLK_ADDR, m) +#define HWIO_GCC_LPASS_DSP_VOTE_QDSS_APB_CLK_OUT(v) \ + out_dword(HWIO_GCC_LPASS_DSP_VOTE_QDSS_APB_CLK_ADDR,v) +#define HWIO_GCC_LPASS_DSP_VOTE_QDSS_APB_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_LPASS_DSP_VOTE_QDSS_APB_CLK_ADDR,m,v,HWIO_GCC_LPASS_DSP_VOTE_QDSS_APB_CLK_IN) +#define HWIO_GCC_LPASS_DSP_VOTE_QDSS_APB_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_LPASS_DSP_VOTE_QDSS_APB_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_LPASS_DSP_VOTE_QDSS_APB_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_LPASS_DSP_VOTE_QDSS_APB_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_LPASS_DSP_VOTE_QDSS_APB_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_VOTE_QDSS_APB_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00046124) +#define HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00046124) +#define HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00046124) +#define HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_RMSK 0x80000001 +#define HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_ATTR 0x3 +#define HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_IN \ + in_dword_masked(HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_ADDR, HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_RMSK) +#define HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_ADDR, m) +#define HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_OUT(v) \ + out_dword(HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_ADDR,v) +#define HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_ADDR,m,v,HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_IN) +#define HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004a124) +#define HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004a124) +#define HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004a124) +#define HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_RMSK 0x80000001 +#define HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_ATTR 0x3 +#define HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_IN \ + in_dword_masked(HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_ADDR, HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_RMSK) +#define HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_INM(m) \ + in_dword_masked(HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_ADDR, m) +#define HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_OUT(v) \ + out_dword(HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_ADDR,v) +#define HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_ADDR,m,v,HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_IN) +#define HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_CLK_OFF_BMSK 0x80000000 +#define HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_CLK_OFF_SHFT 0x1f +#define HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_CLK_ENABLE_BMSK 0x1 +#define HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_CLK_ENABLE_SHFT 0x0 +#define HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_CLK_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_CLK_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_JBIST_MODE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00070000) +#define HWIO_GCC_JBIST_MODE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00070000) +#define HWIO_GCC_JBIST_MODE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00070000) +#define HWIO_GCC_JBIST_MODE_RMSK 0xffffffff +#define HWIO_GCC_JBIST_MODE_ATTR 0x3 +#define HWIO_GCC_JBIST_MODE_IN \ + in_dword_masked(HWIO_GCC_JBIST_MODE_ADDR, HWIO_GCC_JBIST_MODE_RMSK) +#define HWIO_GCC_JBIST_MODE_INM(m) \ + in_dword_masked(HWIO_GCC_JBIST_MODE_ADDR, m) +#define HWIO_GCC_JBIST_MODE_OUT(v) \ + out_dword(HWIO_GCC_JBIST_MODE_ADDR,v) +#define HWIO_GCC_JBIST_MODE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_JBIST_MODE_ADDR,m,v,HWIO_GCC_JBIST_MODE_IN) +#define HWIO_GCC_JBIST_MODE_RESERVE_BITS31_9_BMSK 0xfffff800 +#define HWIO_GCC_JBIST_MODE_RESERVE_BITS31_9_SHFT 0xb +#define HWIO_GCC_JBIST_MODE_JBIST_PASS_BMSK 0x400 +#define HWIO_GCC_JBIST_MODE_JBIST_PASS_SHFT 0xa +#define HWIO_GCC_JBIST_MODE_JBIST_ENABLE_BMSK 0x200 +#define HWIO_GCC_JBIST_MODE_JBIST_ENABLE_SHFT 0x9 +#define HWIO_GCC_JBIST_MODE_DLL_CLK_EXT2_MUX_SEL_BMSK 0x180 +#define HWIO_GCC_JBIST_MODE_DLL_CLK_EXT2_MUX_SEL_SHFT 0x7 +#define HWIO_GCC_JBIST_MODE_DLL_CLK_EXT1_MUX_SEL_BMSK 0x60 +#define HWIO_GCC_JBIST_MODE_DLL_CLK_EXT1_MUX_SEL_SHFT 0x5 +#define HWIO_GCC_JBIST_MODE_PLL_LOCK_DET_BMSK 0x10 +#define HWIO_GCC_JBIST_MODE_PLL_LOCK_DET_SHFT 0x4 +#define HWIO_GCC_JBIST_MODE_START_MEAS_BMSK 0x8 +#define HWIO_GCC_JBIST_MODE_START_MEAS_SHFT 0x3 +#define HWIO_GCC_JBIST_MODE_JBIST_TEST_BMSK 0x4 +#define HWIO_GCC_JBIST_MODE_JBIST_TEST_SHFT 0x2 +#define HWIO_GCC_JBIST_MODE_RESET_N_BMSK 0x2 +#define HWIO_GCC_JBIST_MODE_RESET_N_SHFT 0x1 +#define HWIO_GCC_JBIST_MODE_SLEEP_N_BMSK 0x1 +#define HWIO_GCC_JBIST_MODE_SLEEP_N_SHFT 0x0 + +#define HWIO_GCC_JBIST_MEAS_DONE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00070018) +#define HWIO_GCC_JBIST_MEAS_DONE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00070018) +#define HWIO_GCC_JBIST_MEAS_DONE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00070018) +#define HWIO_GCC_JBIST_MEAS_DONE_RMSK 0xffffffff +#define HWIO_GCC_JBIST_MEAS_DONE_ATTR 0x3 +#define HWIO_GCC_JBIST_MEAS_DONE_IN \ + in_dword_masked(HWIO_GCC_JBIST_MEAS_DONE_ADDR, HWIO_GCC_JBIST_MEAS_DONE_RMSK) +#define HWIO_GCC_JBIST_MEAS_DONE_INM(m) \ + in_dword_masked(HWIO_GCC_JBIST_MEAS_DONE_ADDR, m) +#define HWIO_GCC_JBIST_MEAS_DONE_OUT(v) \ + out_dword(HWIO_GCC_JBIST_MEAS_DONE_ADDR,v) +#define HWIO_GCC_JBIST_MEAS_DONE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_JBIST_MEAS_DONE_ADDR,m,v,HWIO_GCC_JBIST_MEAS_DONE_IN) +#define HWIO_GCC_JBIST_MEAS_DONE_RESERVE_BITS31_1_BMSK 0xfffffffe +#define HWIO_GCC_JBIST_MEAS_DONE_RESERVE_BITS31_1_SHFT 0x1 +#define HWIO_GCC_JBIST_MEAS_DONE_JBIST_DATA_STREAM_RDY_BMSK 0x1 +#define HWIO_GCC_JBIST_MEAS_DONE_JBIST_DATA_STREAM_RDY_SHFT 0x0 + +#define HWIO_GCC_GLOBAL_EN_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007f000) +#define HWIO_GCC_GLOBAL_EN_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007f000) +#define HWIO_GCC_GLOBAL_EN_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007f000) +#define HWIO_GCC_GLOBAL_EN_RMSK 0xffffffff +#define HWIO_GCC_GLOBAL_EN_ATTR 0x3 +#define HWIO_GCC_GLOBAL_EN_IN \ + in_dword_masked(HWIO_GCC_GLOBAL_EN_ADDR, HWIO_GCC_GLOBAL_EN_RMSK) +#define HWIO_GCC_GLOBAL_EN_INM(m) \ + in_dword_masked(HWIO_GCC_GLOBAL_EN_ADDR, m) +#define HWIO_GCC_GLOBAL_EN_OUT(v) \ + out_dword(HWIO_GCC_GLOBAL_EN_ADDR,v) +#define HWIO_GCC_GLOBAL_EN_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GLOBAL_EN_ADDR,m,v,HWIO_GCC_GLOBAL_EN_IN) +#define HWIO_GCC_GLOBAL_EN_SPARE_ENABLE_BMSK 0xffff8000 +#define HWIO_GCC_GLOBAL_EN_SPARE_ENABLE_SHFT 0xf +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_7_BMSK 0x4000 +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_7_SHFT 0xe +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_7_DISABLE_FVAL 0x0 +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_7_ENABLE_FVAL 0x1 +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_6_BMSK 0x2000 +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_6_SHFT 0xd +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_6_DISABLE_FVAL 0x0 +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_6_ENABLE_FVAL 0x1 +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_5_BMSK 0x1000 +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_5_SHFT 0xc +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_5_DISABLE_FVAL 0x0 +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_5_ENABLE_FVAL 0x1 +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_4_BMSK 0x800 +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_4_SHFT 0xb +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_4_DISABLE_FVAL 0x0 +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_4_ENABLE_FVAL 0x1 +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_3_BMSK 0x400 +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_3_SHFT 0xa +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_3_DISABLE_FVAL 0x0 +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_3_ENABLE_FVAL 0x1 +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_2_BMSK 0x200 +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_2_SHFT 0x9 +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_2_DISABLE_FVAL 0x0 +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_2_ENABLE_FVAL 0x1 +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_1_BMSK 0x100 +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_1_SHFT 0x8 +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_1_DISABLE_FVAL 0x0 +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_1_ENABLE_FVAL 0x1 +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_0_BMSK 0x80 +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_0_SHFT 0x7 +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_0_DISABLE_FVAL 0x0 +#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_0_ENABLE_FVAL 0x1 +#define HWIO_GCC_GLOBAL_EN_REST_ENABLE_BMSK 0x40 +#define HWIO_GCC_GLOBAL_EN_REST_ENABLE_SHFT 0x6 +#define HWIO_GCC_GLOBAL_EN_REST_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GLOBAL_EN_REST_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_GLOBAL_EN_PERIPHERALS_ENABLE_BMSK 0x20 +#define HWIO_GCC_GLOBAL_EN_PERIPHERALS_ENABLE_SHFT 0x5 +#define HWIO_GCC_GLOBAL_EN_PERIPHERALS_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GLOBAL_EN_PERIPHERALS_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_GLOBAL_EN_CENTER_ENABLE_BMSK 0x10 +#define HWIO_GCC_GLOBAL_EN_CENTER_ENABLE_SHFT 0x4 +#define HWIO_GCC_GLOBAL_EN_CENTER_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GLOBAL_EN_CENTER_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_GLOBAL_EN_SOUTH_ENABLE_BMSK 0x8 +#define HWIO_GCC_GLOBAL_EN_SOUTH_ENABLE_SHFT 0x3 +#define HWIO_GCC_GLOBAL_EN_SOUTH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GLOBAL_EN_SOUTH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_GLOBAL_EN_NORTH_ENABLE_BMSK 0x4 +#define HWIO_GCC_GLOBAL_EN_NORTH_ENABLE_SHFT 0x2 +#define HWIO_GCC_GLOBAL_EN_NORTH_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GLOBAL_EN_NORTH_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_GLOBAL_EN_WEST_ENABLE_BMSK 0x2 +#define HWIO_GCC_GLOBAL_EN_WEST_ENABLE_SHFT 0x1 +#define HWIO_GCC_GLOBAL_EN_WEST_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GLOBAL_EN_WEST_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_GLOBAL_EN_EAST_ENABLE_BMSK 0x1 +#define HWIO_GCC_GLOBAL_EN_EAST_ENABLE_SHFT 0x0 +#define HWIO_GCC_GLOBAL_EN_EAST_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_GLOBAL_EN_EAST_ENABLE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_DEBUG_EN_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00075000) +#define HWIO_GCC_DEBUG_EN_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00075000) +#define HWIO_GCC_DEBUG_EN_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00075000) +#define HWIO_GCC_DEBUG_EN_RMSK 0xffffffff +#define HWIO_GCC_DEBUG_EN_ATTR 0x3 +#define HWIO_GCC_DEBUG_EN_IN \ + in_dword_masked(HWIO_GCC_DEBUG_EN_ADDR, HWIO_GCC_DEBUG_EN_RMSK) +#define HWIO_GCC_DEBUG_EN_INM(m) \ + in_dword_masked(HWIO_GCC_DEBUG_EN_ADDR, m) +#define HWIO_GCC_DEBUG_EN_OUT(v) \ + out_dword(HWIO_GCC_DEBUG_EN_ADDR,v) +#define HWIO_GCC_DEBUG_EN_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_DEBUG_EN_ADDR,m,v,HWIO_GCC_DEBUG_EN_IN) +#define HWIO_GCC_DEBUG_EN_CDBGPWRUPACK_BMSK 0x80000000 +#define HWIO_GCC_DEBUG_EN_CDBGPWRUPACK_SHFT 0x1f +#define HWIO_GCC_DEBUG_EN_SPARE_ENABLE_BMSK 0x7ffffffe +#define HWIO_GCC_DEBUG_EN_SPARE_ENABLE_SHFT 0x1 +#define HWIO_GCC_DEBUG_EN_CDBGPWRUPREQ_BMSK 0x1 +#define HWIO_GCC_DEBUG_EN_CDBGPWRUPREQ_SHFT 0x0 +#define HWIO_GCC_DEBUG_EN_CDBGPWRUPREQ_DISABLE_FVAL 0x0 +#define HWIO_GCC_DEBUG_EN_CDBGPWRUPREQ_ENABLE_FVAL 0x1 + +#define HWIO_GCC_CAM_CC_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00016100) +#define HWIO_GCC_CAM_CC_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00016100) +#define HWIO_GCC_CAM_CC_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00016100) +#define HWIO_GCC_CAM_CC_SGDSCR_RMSK 0x7 +#define HWIO_GCC_CAM_CC_SGDSCR_ATTR 0x3 +#define HWIO_GCC_CAM_CC_SGDSCR_IN \ + in_dword_masked(HWIO_GCC_CAM_CC_SGDSCR_ADDR, HWIO_GCC_CAM_CC_SGDSCR_RMSK) +#define HWIO_GCC_CAM_CC_SGDSCR_INM(m) \ + in_dword_masked(HWIO_GCC_CAM_CC_SGDSCR_ADDR, m) +#define HWIO_GCC_CAM_CC_SGDSCR_OUT(v) \ + out_dword(HWIO_GCC_CAM_CC_SGDSCR_ADDR,v) +#define HWIO_GCC_CAM_CC_SGDSCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_CAM_CC_SGDSCR_ADDR,m,v,HWIO_GCC_CAM_CC_SGDSCR_IN) +#define HWIO_GCC_CAM_CC_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_BMSK 0x4 +#define HWIO_GCC_CAM_CC_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_SHFT 0x2 +#define HWIO_GCC_CAM_CC_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CAM_CC_SGDSCR_PRE_PWRUP_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_CAM_CC_SGDSCR_RETAIN_FF_ENABLE_BMSK 0x2 +#define HWIO_GCC_CAM_CC_SGDSCR_RETAIN_FF_ENABLE_SHFT 0x1 +#define HWIO_GCC_CAM_CC_SGDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CAM_CC_SGDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL 0x1 +#define HWIO_GCC_CAM_CC_SGDSCR_SW_OVERRIDE_BMSK 0x1 +#define HWIO_GCC_CAM_CC_SGDSCR_SW_OVERRIDE_SHFT 0x0 +#define HWIO_GCC_CAM_CC_SGDSCR_SW_OVERRIDE_DISABLE_FVAL 0x0 +#define HWIO_GCC_CAM_CC_SGDSCR_SW_OVERRIDE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00081000) +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00081000) +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00081000) +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00081004) +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00081004) +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00081004) +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00081008) +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00081008) +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00081008) +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008100c) +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008100c) +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008100c) +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00081010) +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00081010) +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00081010) +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00081014) +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00081014) +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00081014) +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00081018) +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00081018) +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00081018) +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008101c) +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008101c) +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008101c) +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00081020) +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00081020) +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00081020) +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00081024) +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00081024) +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00081024) +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00081028) +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00081028) +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00081028) +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008102c) +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008102c) +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008102c) +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00081030) +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00081030) +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00081030) +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00081034) +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00081034) +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00081034) +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00081038) +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00081038) +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00081038) +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008103c) +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008103c) +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008103c) +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00082000) +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082000) +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082000) +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00082004) +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082004) +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082004) +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00082008) +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082008) +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082008) +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008200c) +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008200c) +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008200c) +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00082010) +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082010) +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082010) +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00082014) +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082014) +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082014) +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00082018) +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082018) +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082018) +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008201c) +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008201c) +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008201c) +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00082020) +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082020) +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082020) +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00082024) +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082024) +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082024) +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00082028) +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082028) +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082028) +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008202c) +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008202c) +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008202c) +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00082030) +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082030) +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082030) +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00082034) +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082034) +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082034) +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00082038) +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082038) +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082038) +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008203c) +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008203c) +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008203c) +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00086000) +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00086000) +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00086000) +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00086004) +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00086004) +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00086004) +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00086008) +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00086008) +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00086008) +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008600c) +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008600c) +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008600c) +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00086010) +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00086010) +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00086010) +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00086014) +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00086014) +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00086014) +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00086018) +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00086018) +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00086018) +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008601c) +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008601c) +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008601c) +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00086020) +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00086020) +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00086020) +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00086024) +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00086024) +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00086024) +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00086028) +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00086028) +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00086028) +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008602c) +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008602c) +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008602c) +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00086030) +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00086030) +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00086030) +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00086034) +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00086034) +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00086034) +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00086038) +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00086038) +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00086038) +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008603c) +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008603c) +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008603c) +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00085000) +#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00085000) +#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00085000) +#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_ADDR, HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00085004) +#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00085004) +#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00085004) +#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_ADDR, HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00085008) +#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00085008) +#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00085008) +#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_ADDR, HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008500c) +#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008500c) +#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008500c) +#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_ADDR, HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00085010) +#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00085010) +#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00085010) +#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_ADDR, HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00085014) +#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00085014) +#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00085014) +#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_ADDR, HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00085018) +#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00085018) +#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00085018) +#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_ADDR, HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008501c) +#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008501c) +#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008501c) +#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_ADDR, HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00085020) +#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00085020) +#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00085020) +#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_ADDR, HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00085024) +#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00085024) +#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00085024) +#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_ADDR, HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00085028) +#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00085028) +#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00085028) +#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_ADDR, HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008502c) +#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008502c) +#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008502c) +#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_ADDR, HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00085030) +#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00085030) +#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00085030) +#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_ADDR, HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00085034) +#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00085034) +#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00085034) +#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_ADDR, HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00085038) +#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00085038) +#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00085038) +#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_ADDR, HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008503c) +#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008503c) +#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008503c) +#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_ADDR, HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008b000) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008b000) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008b000) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008b004) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008b004) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008b004) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008b008) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008b008) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008b008) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008b00c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008b00c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008b00c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008b010) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008b010) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008b010) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008b014) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008b014) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008b014) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008b018) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008b018) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008b018) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008b01c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008b01c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008b01c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008b020) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008b020) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008b020) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008b024) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008b024) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008b024) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008b028) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008b028) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008b028) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008b02c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008b02c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008b02c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008b030) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008b030) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008b030) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008b034) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008b034) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008b034) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008b038) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008b038) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008b038) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008b03c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008b03c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008b03c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_PMU_PERF0_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008a000) +#define HWIO_GCC_RPMH_PMU_PERF0_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a000) +#define HWIO_GCC_RPMH_PMU_PERF0_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a000) +#define HWIO_GCC_RPMH_PMU_PERF0_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_PMU_PERF0_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_PMU_PERF0_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PERF0_ENA_VOTE_ADDR, HWIO_GCC_RPMH_PMU_PERF0_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_PMU_PERF0_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PERF0_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_PMU_PERF0_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PMU_PERF0_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_PMU_PERF0_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PMU_PERF0_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_PMU_PERF0_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_PMU_PERF0_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_PMU_PERF0_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_PMU_PERF0_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF0_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF0_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_PMU_PERF0_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_PMU_PERF0_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF0_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF0_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_PMU_PERF0_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_PMU_PERF0_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF0_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF0_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_PMU_PERF0_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_PMU_PERF0_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF0_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF0_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_PMU_PERF0_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_PMU_PERF0_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF0_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF0_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_PMU_PERF0_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_PMU_PERF0_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF0_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF0_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_PMU_PERF0_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_PMU_PERF0_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF0_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF0_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_PMU_PERF0_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_PMU_PERF0_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF0_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF0_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_PMU_PERF0_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_PMU_PERF0_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF0_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF0_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_PMU_PERF0_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_PMU_PERF0_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF0_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_PMU_PERF1_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008a004) +#define HWIO_GCC_RPMH_PMU_PERF1_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a004) +#define HWIO_GCC_RPMH_PMU_PERF1_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a004) +#define HWIO_GCC_RPMH_PMU_PERF1_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_PMU_PERF1_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_PMU_PERF1_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PERF1_ENA_VOTE_ADDR, HWIO_GCC_RPMH_PMU_PERF1_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_PMU_PERF1_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PERF1_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_PMU_PERF1_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PMU_PERF1_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_PMU_PERF1_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PMU_PERF1_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_PMU_PERF1_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_PMU_PERF1_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_PMU_PERF1_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_PMU_PERF1_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF1_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF1_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_PMU_PERF1_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_PMU_PERF1_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF1_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF1_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_PMU_PERF1_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_PMU_PERF1_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF1_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF1_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_PMU_PERF1_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_PMU_PERF1_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF1_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF1_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_PMU_PERF1_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_PMU_PERF1_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF1_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF1_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_PMU_PERF1_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_PMU_PERF1_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF1_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF1_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_PMU_PERF1_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_PMU_PERF1_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF1_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF1_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_PMU_PERF1_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_PMU_PERF1_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF1_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF1_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_PMU_PERF1_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_PMU_PERF1_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF1_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF1_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_PMU_PERF1_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_PMU_PERF1_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF1_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_PMU_PERF2_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008a008) +#define HWIO_GCC_RPMH_PMU_PERF2_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a008) +#define HWIO_GCC_RPMH_PMU_PERF2_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a008) +#define HWIO_GCC_RPMH_PMU_PERF2_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_PMU_PERF2_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_PMU_PERF2_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PERF2_ENA_VOTE_ADDR, HWIO_GCC_RPMH_PMU_PERF2_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_PMU_PERF2_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PERF2_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_PMU_PERF2_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PMU_PERF2_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_PMU_PERF2_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PMU_PERF2_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_PMU_PERF2_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_PMU_PERF2_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_PMU_PERF2_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_PMU_PERF2_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF2_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF2_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_PMU_PERF2_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_PMU_PERF2_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF2_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF2_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_PMU_PERF2_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_PMU_PERF2_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF2_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF2_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_PMU_PERF2_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_PMU_PERF2_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF2_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF2_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_PMU_PERF2_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_PMU_PERF2_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF2_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF2_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_PMU_PERF2_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_PMU_PERF2_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF2_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF2_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_PMU_PERF2_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_PMU_PERF2_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF2_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF2_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_PMU_PERF2_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_PMU_PERF2_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF2_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF2_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_PMU_PERF2_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_PMU_PERF2_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF2_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF2_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_PMU_PERF2_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_PMU_PERF2_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF2_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_PMU_PERF3_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008a00c) +#define HWIO_GCC_RPMH_PMU_PERF3_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a00c) +#define HWIO_GCC_RPMH_PMU_PERF3_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a00c) +#define HWIO_GCC_RPMH_PMU_PERF3_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_PMU_PERF3_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_PMU_PERF3_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PERF3_ENA_VOTE_ADDR, HWIO_GCC_RPMH_PMU_PERF3_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_PMU_PERF3_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PERF3_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_PMU_PERF3_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PMU_PERF3_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_PMU_PERF3_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PMU_PERF3_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_PMU_PERF3_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_PMU_PERF3_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_PMU_PERF3_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_PMU_PERF3_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF3_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF3_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_PMU_PERF3_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_PMU_PERF3_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF3_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF3_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_PMU_PERF3_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_PMU_PERF3_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF3_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF3_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_PMU_PERF3_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_PMU_PERF3_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF3_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF3_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_PMU_PERF3_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_PMU_PERF3_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF3_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF3_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_PMU_PERF3_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_PMU_PERF3_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF3_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF3_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_PMU_PERF3_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_PMU_PERF3_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF3_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF3_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_PMU_PERF3_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_PMU_PERF3_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF3_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF3_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_PMU_PERF3_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_PMU_PERF3_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF3_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF3_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_PMU_PERF3_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_PMU_PERF3_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF3_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_PMU_PERF4_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008a010) +#define HWIO_GCC_RPMH_PMU_PERF4_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a010) +#define HWIO_GCC_RPMH_PMU_PERF4_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a010) +#define HWIO_GCC_RPMH_PMU_PERF4_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_PMU_PERF4_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_PMU_PERF4_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PERF4_ENA_VOTE_ADDR, HWIO_GCC_RPMH_PMU_PERF4_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_PMU_PERF4_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PERF4_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_PMU_PERF4_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PMU_PERF4_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_PMU_PERF4_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PMU_PERF4_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_PMU_PERF4_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_PMU_PERF4_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_PMU_PERF4_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_PMU_PERF4_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF4_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF4_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_PMU_PERF4_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_PMU_PERF4_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF4_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF4_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_PMU_PERF4_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_PMU_PERF4_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF4_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF4_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_PMU_PERF4_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_PMU_PERF4_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF4_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF4_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_PMU_PERF4_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_PMU_PERF4_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF4_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF4_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_PMU_PERF4_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_PMU_PERF4_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF4_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF4_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_PMU_PERF4_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_PMU_PERF4_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF4_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF4_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_PMU_PERF4_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_PMU_PERF4_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF4_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF4_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_PMU_PERF4_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_PMU_PERF4_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF4_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF4_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_PMU_PERF4_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_PMU_PERF4_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF4_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_PMU_PERF5_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008a014) +#define HWIO_GCC_RPMH_PMU_PERF5_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a014) +#define HWIO_GCC_RPMH_PMU_PERF5_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a014) +#define HWIO_GCC_RPMH_PMU_PERF5_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_PMU_PERF5_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_PMU_PERF5_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PERF5_ENA_VOTE_ADDR, HWIO_GCC_RPMH_PMU_PERF5_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_PMU_PERF5_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PERF5_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_PMU_PERF5_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PMU_PERF5_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_PMU_PERF5_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PMU_PERF5_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_PMU_PERF5_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_PMU_PERF5_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_PMU_PERF5_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_PMU_PERF5_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF5_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF5_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_PMU_PERF5_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_PMU_PERF5_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF5_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF5_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_PMU_PERF5_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_PMU_PERF5_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF5_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF5_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_PMU_PERF5_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_PMU_PERF5_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF5_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF5_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_PMU_PERF5_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_PMU_PERF5_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF5_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF5_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_PMU_PERF5_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_PMU_PERF5_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF5_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF5_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_PMU_PERF5_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_PMU_PERF5_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF5_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF5_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_PMU_PERF5_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_PMU_PERF5_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF5_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF5_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_PMU_PERF5_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_PMU_PERF5_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF5_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF5_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_PMU_PERF5_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_PMU_PERF5_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF5_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_PMU_PERF6_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008a018) +#define HWIO_GCC_RPMH_PMU_PERF6_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a018) +#define HWIO_GCC_RPMH_PMU_PERF6_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a018) +#define HWIO_GCC_RPMH_PMU_PERF6_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_PMU_PERF6_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_PMU_PERF6_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PERF6_ENA_VOTE_ADDR, HWIO_GCC_RPMH_PMU_PERF6_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_PMU_PERF6_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PERF6_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_PMU_PERF6_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PMU_PERF6_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_PMU_PERF6_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PMU_PERF6_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_PMU_PERF6_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_PMU_PERF6_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_PMU_PERF6_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_PMU_PERF6_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF6_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF6_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_PMU_PERF6_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_PMU_PERF6_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF6_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF6_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_PMU_PERF6_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_PMU_PERF6_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF6_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF6_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_PMU_PERF6_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_PMU_PERF6_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF6_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF6_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_PMU_PERF6_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_PMU_PERF6_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF6_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF6_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_PMU_PERF6_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_PMU_PERF6_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF6_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF6_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_PMU_PERF6_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_PMU_PERF6_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF6_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF6_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_PMU_PERF6_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_PMU_PERF6_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF6_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF6_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_PMU_PERF6_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_PMU_PERF6_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF6_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF6_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_PMU_PERF6_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_PMU_PERF6_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF6_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_PMU_PERF7_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008a01c) +#define HWIO_GCC_RPMH_PMU_PERF7_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a01c) +#define HWIO_GCC_RPMH_PMU_PERF7_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a01c) +#define HWIO_GCC_RPMH_PMU_PERF7_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_PMU_PERF7_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_PMU_PERF7_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PERF7_ENA_VOTE_ADDR, HWIO_GCC_RPMH_PMU_PERF7_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_PMU_PERF7_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PERF7_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_PMU_PERF7_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PMU_PERF7_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_PMU_PERF7_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PMU_PERF7_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_PMU_PERF7_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_PMU_PERF7_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_PMU_PERF7_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_PMU_PERF7_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF7_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF7_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_PMU_PERF7_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_PMU_PERF7_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF7_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF7_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_PMU_PERF7_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_PMU_PERF7_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF7_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF7_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_PMU_PERF7_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_PMU_PERF7_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF7_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF7_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_PMU_PERF7_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_PMU_PERF7_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF7_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF7_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_PMU_PERF7_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_PMU_PERF7_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF7_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF7_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_PMU_PERF7_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_PMU_PERF7_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF7_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF7_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_PMU_PERF7_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_PMU_PERF7_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF7_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF7_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_PMU_PERF7_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_PMU_PERF7_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF7_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF7_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_PMU_PERF7_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_PMU_PERF7_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF7_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_PMU_PERF8_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008a020) +#define HWIO_GCC_RPMH_PMU_PERF8_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a020) +#define HWIO_GCC_RPMH_PMU_PERF8_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a020) +#define HWIO_GCC_RPMH_PMU_PERF8_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_PMU_PERF8_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_PMU_PERF8_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PERF8_ENA_VOTE_ADDR, HWIO_GCC_RPMH_PMU_PERF8_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_PMU_PERF8_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PERF8_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_PMU_PERF8_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PMU_PERF8_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_PMU_PERF8_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PMU_PERF8_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_PMU_PERF8_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_PMU_PERF8_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_PMU_PERF8_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_PMU_PERF8_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF8_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF8_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_PMU_PERF8_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_PMU_PERF8_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF8_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF8_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_PMU_PERF8_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_PMU_PERF8_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF8_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF8_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_PMU_PERF8_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_PMU_PERF8_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF8_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF8_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_PMU_PERF8_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_PMU_PERF8_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF8_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF8_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_PMU_PERF8_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_PMU_PERF8_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF8_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF8_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_PMU_PERF8_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_PMU_PERF8_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF8_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF8_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_PMU_PERF8_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_PMU_PERF8_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF8_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF8_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_PMU_PERF8_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_PMU_PERF8_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF8_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF8_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_PMU_PERF8_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_PMU_PERF8_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF8_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_PMU_PERF9_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008a024) +#define HWIO_GCC_RPMH_PMU_PERF9_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a024) +#define HWIO_GCC_RPMH_PMU_PERF9_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a024) +#define HWIO_GCC_RPMH_PMU_PERF9_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_PMU_PERF9_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_PMU_PERF9_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PERF9_ENA_VOTE_ADDR, HWIO_GCC_RPMH_PMU_PERF9_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_PMU_PERF9_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PERF9_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_PMU_PERF9_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PMU_PERF9_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_PMU_PERF9_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PMU_PERF9_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_PMU_PERF9_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_PMU_PERF9_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_PMU_PERF9_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_PMU_PERF9_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF9_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF9_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_PMU_PERF9_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_PMU_PERF9_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF9_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF9_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_PMU_PERF9_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_PMU_PERF9_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF9_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF9_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_PMU_PERF9_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_PMU_PERF9_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF9_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF9_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_PMU_PERF9_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_PMU_PERF9_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF9_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF9_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_PMU_PERF9_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_PMU_PERF9_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF9_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF9_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_PMU_PERF9_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_PMU_PERF9_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF9_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF9_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_PMU_PERF9_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_PMU_PERF9_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF9_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF9_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_PMU_PERF9_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_PMU_PERF9_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF9_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF9_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_PMU_PERF9_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_PMU_PERF9_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF9_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_PMU_PERF10_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008a028) +#define HWIO_GCC_RPMH_PMU_PERF10_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a028) +#define HWIO_GCC_RPMH_PMU_PERF10_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a028) +#define HWIO_GCC_RPMH_PMU_PERF10_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_PMU_PERF10_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_PMU_PERF10_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PERF10_ENA_VOTE_ADDR, HWIO_GCC_RPMH_PMU_PERF10_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_PMU_PERF10_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PERF10_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_PMU_PERF10_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PMU_PERF10_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_PMU_PERF10_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PMU_PERF10_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_PMU_PERF10_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_PMU_PERF10_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_PMU_PERF10_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_PMU_PERF10_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF10_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF10_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_PMU_PERF10_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_PMU_PERF10_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF10_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF10_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_PMU_PERF10_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_PMU_PERF10_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF10_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF10_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_PMU_PERF10_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_PMU_PERF10_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF10_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF10_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_PMU_PERF10_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_PMU_PERF10_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF10_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF10_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_PMU_PERF10_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_PMU_PERF10_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF10_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF10_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_PMU_PERF10_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_PMU_PERF10_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF10_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF10_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_PMU_PERF10_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_PMU_PERF10_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF10_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF10_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_PMU_PERF10_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_PMU_PERF10_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF10_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF10_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_PMU_PERF10_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_PMU_PERF10_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF10_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_PMU_PERF11_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008a02c) +#define HWIO_GCC_RPMH_PMU_PERF11_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a02c) +#define HWIO_GCC_RPMH_PMU_PERF11_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a02c) +#define HWIO_GCC_RPMH_PMU_PERF11_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_PMU_PERF11_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_PMU_PERF11_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PERF11_ENA_VOTE_ADDR, HWIO_GCC_RPMH_PMU_PERF11_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_PMU_PERF11_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PERF11_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_PMU_PERF11_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PMU_PERF11_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_PMU_PERF11_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PMU_PERF11_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_PMU_PERF11_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_PMU_PERF11_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_PMU_PERF11_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_PMU_PERF11_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF11_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF11_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_PMU_PERF11_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_PMU_PERF11_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF11_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF11_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_PMU_PERF11_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_PMU_PERF11_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF11_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF11_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_PMU_PERF11_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_PMU_PERF11_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF11_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF11_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_PMU_PERF11_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_PMU_PERF11_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF11_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF11_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_PMU_PERF11_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_PMU_PERF11_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF11_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF11_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_PMU_PERF11_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_PMU_PERF11_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF11_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF11_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_PMU_PERF11_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_PMU_PERF11_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF11_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF11_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_PMU_PERF11_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_PMU_PERF11_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF11_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF11_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_PMU_PERF11_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_PMU_PERF11_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF11_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_PMU_PERF12_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008a030) +#define HWIO_GCC_RPMH_PMU_PERF12_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a030) +#define HWIO_GCC_RPMH_PMU_PERF12_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a030) +#define HWIO_GCC_RPMH_PMU_PERF12_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_PMU_PERF12_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_PMU_PERF12_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PERF12_ENA_VOTE_ADDR, HWIO_GCC_RPMH_PMU_PERF12_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_PMU_PERF12_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PERF12_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_PMU_PERF12_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PMU_PERF12_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_PMU_PERF12_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PMU_PERF12_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_PMU_PERF12_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_PMU_PERF12_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_PMU_PERF12_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_PMU_PERF12_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF12_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF12_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_PMU_PERF12_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_PMU_PERF12_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF12_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF12_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_PMU_PERF12_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_PMU_PERF12_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF12_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF12_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_PMU_PERF12_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_PMU_PERF12_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF12_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF12_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_PMU_PERF12_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_PMU_PERF12_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF12_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF12_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_PMU_PERF12_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_PMU_PERF12_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF12_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF12_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_PMU_PERF12_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_PMU_PERF12_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF12_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF12_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_PMU_PERF12_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_PMU_PERF12_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF12_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF12_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_PMU_PERF12_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_PMU_PERF12_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF12_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF12_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_PMU_PERF12_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_PMU_PERF12_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF12_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_PMU_PERF13_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008a034) +#define HWIO_GCC_RPMH_PMU_PERF13_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a034) +#define HWIO_GCC_RPMH_PMU_PERF13_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a034) +#define HWIO_GCC_RPMH_PMU_PERF13_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_PMU_PERF13_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_PMU_PERF13_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PERF13_ENA_VOTE_ADDR, HWIO_GCC_RPMH_PMU_PERF13_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_PMU_PERF13_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PERF13_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_PMU_PERF13_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PMU_PERF13_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_PMU_PERF13_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PMU_PERF13_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_PMU_PERF13_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_PMU_PERF13_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_PMU_PERF13_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_PMU_PERF13_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF13_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF13_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_PMU_PERF13_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_PMU_PERF13_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF13_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF13_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_PMU_PERF13_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_PMU_PERF13_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF13_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF13_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_PMU_PERF13_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_PMU_PERF13_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF13_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF13_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_PMU_PERF13_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_PMU_PERF13_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF13_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF13_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_PMU_PERF13_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_PMU_PERF13_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF13_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF13_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_PMU_PERF13_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_PMU_PERF13_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF13_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF13_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_PMU_PERF13_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_PMU_PERF13_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF13_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF13_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_PMU_PERF13_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_PMU_PERF13_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF13_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF13_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_PMU_PERF13_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_PMU_PERF13_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF13_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_PMU_PERF14_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008a038) +#define HWIO_GCC_RPMH_PMU_PERF14_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a038) +#define HWIO_GCC_RPMH_PMU_PERF14_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a038) +#define HWIO_GCC_RPMH_PMU_PERF14_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_PMU_PERF14_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_PMU_PERF14_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PERF14_ENA_VOTE_ADDR, HWIO_GCC_RPMH_PMU_PERF14_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_PMU_PERF14_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PERF14_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_PMU_PERF14_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PMU_PERF14_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_PMU_PERF14_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PMU_PERF14_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_PMU_PERF14_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_PMU_PERF14_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_PMU_PERF14_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_PMU_PERF14_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF14_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF14_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_PMU_PERF14_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_PMU_PERF14_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF14_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF14_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_PMU_PERF14_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_PMU_PERF14_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF14_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF14_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_PMU_PERF14_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_PMU_PERF14_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF14_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF14_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_PMU_PERF14_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_PMU_PERF14_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF14_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF14_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_PMU_PERF14_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_PMU_PERF14_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF14_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF14_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_PMU_PERF14_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_PMU_PERF14_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF14_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF14_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_PMU_PERF14_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_PMU_PERF14_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF14_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF14_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_PMU_PERF14_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_PMU_PERF14_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF14_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF14_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_PMU_PERF14_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_PMU_PERF14_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF14_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_PMU_PERF15_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008a03c) +#define HWIO_GCC_RPMH_PMU_PERF15_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a03c) +#define HWIO_GCC_RPMH_PMU_PERF15_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a03c) +#define HWIO_GCC_RPMH_PMU_PERF15_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_PMU_PERF15_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_PMU_PERF15_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PERF15_ENA_VOTE_ADDR, HWIO_GCC_RPMH_PMU_PERF15_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_PMU_PERF15_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PMU_PERF15_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_PMU_PERF15_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_PMU_PERF15_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_PMU_PERF15_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_PMU_PERF15_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_PMU_PERF15_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_PMU_PERF15_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_PMU_PERF15_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_PMU_PERF15_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF15_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF15_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_PMU_PERF15_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_PMU_PERF15_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF15_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF15_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_PMU_PERF15_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_PMU_PERF15_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF15_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF15_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_PMU_PERF15_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_PMU_PERF15_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF15_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF15_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_PMU_PERF15_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_PMU_PERF15_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF15_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF15_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_PMU_PERF15_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_PMU_PERF15_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF15_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF15_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_PMU_PERF15_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_PMU_PERF15_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF15_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF15_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_PMU_PERF15_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_PMU_PERF15_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF15_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF15_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_PMU_PERF15_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_PMU_PERF15_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF15_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_PMU_PERF15_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_PMU_PERF15_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_PMU_PERF15_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_PMU_PERF15_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00084000) +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00084000) +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00084000) +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00084004) +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00084004) +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00084004) +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00084008) +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00084008) +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00084008) +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008400c) +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008400c) +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008400c) +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00084010) +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00084010) +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00084010) +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00084014) +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00084014) +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00084014) +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00084018) +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00084018) +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00084018) +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008401c) +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008401c) +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008401c) +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00084020) +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00084020) +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00084020) +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00084024) +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00084024) +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00084024) +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00084028) +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00084028) +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00084028) +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008402c) +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008402c) +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008402c) +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00084030) +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00084030) +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00084030) +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00084034) +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00084034) +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00084034) +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00084038) +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00084038) +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00084038) +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008403c) +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008403c) +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008403c) +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00087000) +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00087000) +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00087000) +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00087004) +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00087004) +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00087004) +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00087008) +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00087008) +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00087008) +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008700c) +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008700c) +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008700c) +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00087010) +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00087010) +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00087010) +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00087014) +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00087014) +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00087014) +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00087018) +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00087018) +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00087018) +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008701c) +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008701c) +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008701c) +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00087020) +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00087020) +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00087020) +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00087024) +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00087024) +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00087024) +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00087028) +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00087028) +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00087028) +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008702c) +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008702c) +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008702c) +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00087030) +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00087030) +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00087030) +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00087034) +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00087034) +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00087034) +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00087038) +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00087038) +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00087038) +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008703c) +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008703c) +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008703c) +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_ADDR, HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008c000) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008c000) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008c000) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008c004) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008c004) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008c004) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008c008) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008c008) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008c008) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008c00c) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008c00c) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008c00c) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008c010) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008c010) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008c010) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008c014) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008c014) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008c014) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008c018) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008c018) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008c018) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008c01c) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008c01c) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008c01c) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008c020) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008c020) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008c020) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008c024) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008c024) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008c024) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008c028) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008c028) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008c028) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008c02c) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008c02c) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008c02c) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008c030) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008c030) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008c030) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008c034) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008c034) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008c034) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008c038) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008c038) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008c038) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008c03c) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008c03c) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008c03c) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_ADDR, HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00083000) +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00083000) +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00083000) +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_ADDR, HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00083004) +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00083004) +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00083004) +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_ADDR, HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00083008) +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00083008) +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00083008) +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_ADDR, HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008300c) +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008300c) +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008300c) +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_ADDR, HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00083010) +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00083010) +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00083010) +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_ADDR, HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00083014) +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00083014) +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00083014) +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_ADDR, HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00083018) +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00083018) +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00083018) +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_ADDR, HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008301c) +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008301c) +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008301c) +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_ADDR, HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00083020) +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00083020) +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00083020) +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_ADDR, HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00083024) +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00083024) +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00083024) +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_ADDR, HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00083028) +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00083028) +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00083028) +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_ADDR, HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008302c) +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008302c) +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008302c) +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_ADDR, HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00083030) +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00083030) +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00083030) +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_ADDR, HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00083034) +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00083034) +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00083034) +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_ADDR, HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00083038) +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00083038) +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00083038) +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_ADDR, HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008303c) +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008303c) +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008303c) +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_RMSK 0x3ff +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_ADDR, HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_RMSK) +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_IN) +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GCC_GPLL9_BMSK 0x200 +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GCC_GPLL9_SHFT 0x9 +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GCC_GPLL9_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GCC_GPLL9_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GCC_GPLL8_BMSK 0x100 +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GCC_GPLL8_SHFT 0x8 +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GCC_GPLL8_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GCC_GPLL8_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GCC_GPLL7_BMSK 0x80 +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GCC_GPLL7_SHFT 0x7 +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GCC_GPLL7_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GCC_GPLL7_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GCC_GPLL6_BMSK 0x40 +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GCC_GPLL6_SHFT 0x6 +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GCC_GPLL6_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GCC_GPLL6_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GCC_GPLL5_BMSK 0x20 +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GCC_GPLL5_SHFT 0x5 +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GCC_GPLL5_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GCC_GPLL5_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GCC_GPLL4_BMSK 0x10 +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GCC_GPLL4_SHFT 0x4 +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GCC_GPLL4_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GCC_GPLL4_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GCC_GPLL3_BMSK 0x8 +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GCC_GPLL3_SHFT 0x3 +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GCC_GPLL3_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GCC_GPLL3_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GCC_GPLL2_BMSK 0x4 +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GCC_GPLL2_SHFT 0x2 +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GCC_GPLL2_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GCC_GPLL2_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GCC_GPLL1_BMSK 0x2 +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GCC_GPLL1_SHFT 0x1 +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GCC_GPLL1_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GCC_GPLL1_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GCC_GPLL0_BMSK 0x1 +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GCC_GPLL0_SHFT 0x0 +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GCC_GPLL0_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GCC_GPLL0_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPMH_SYS_NOC_INTERFACE_FSM_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00081100) +#define HWIO_GCC_RPMH_SYS_NOC_INTERFACE_FSM_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00081100) +#define HWIO_GCC_RPMH_SYS_NOC_INTERFACE_FSM_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00081100) +#define HWIO_GCC_RPMH_SYS_NOC_INTERFACE_FSM_RMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_INTERFACE_FSM_ATTR 0x1 +#define HWIO_GCC_RPMH_SYS_NOC_INTERFACE_FSM_IN \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_INTERFACE_FSM_ADDR, HWIO_GCC_RPMH_SYS_NOC_INTERFACE_FSM_RMSK) +#define HWIO_GCC_RPMH_SYS_NOC_INTERFACE_FSM_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_INTERFACE_FSM_ADDR, m) +#define HWIO_GCC_RPMH_SYS_NOC_INTERFACE_FSM_FSM_STATE_BMSK 0x1f +#define HWIO_GCC_RPMH_SYS_NOC_INTERFACE_FSM_FSM_STATE_SHFT 0x0 + +#define HWIO_GCC_RPMH_CNOC_INTERFACE_FSM_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00082100) +#define HWIO_GCC_RPMH_CNOC_INTERFACE_FSM_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082100) +#define HWIO_GCC_RPMH_CNOC_INTERFACE_FSM_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082100) +#define HWIO_GCC_RPMH_CNOC_INTERFACE_FSM_RMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_INTERFACE_FSM_ATTR 0x1 +#define HWIO_GCC_RPMH_CNOC_INTERFACE_FSM_IN \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_INTERFACE_FSM_ADDR, HWIO_GCC_RPMH_CNOC_INTERFACE_FSM_RMSK) +#define HWIO_GCC_RPMH_CNOC_INTERFACE_FSM_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CNOC_INTERFACE_FSM_ADDR, m) +#define HWIO_GCC_RPMH_CNOC_INTERFACE_FSM_FSM_STATE_BMSK 0x1f +#define HWIO_GCC_RPMH_CNOC_INTERFACE_FSM_FSM_STATE_SHFT 0x0 + +#define HWIO_GCC_RPMH_IPA_INTERFACE_FSM_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00083100) +#define HWIO_GCC_RPMH_IPA_INTERFACE_FSM_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00083100) +#define HWIO_GCC_RPMH_IPA_INTERFACE_FSM_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00083100) +#define HWIO_GCC_RPMH_IPA_INTERFACE_FSM_RMSK 0x1f +#define HWIO_GCC_RPMH_IPA_INTERFACE_FSM_ATTR 0x1 +#define HWIO_GCC_RPMH_IPA_INTERFACE_FSM_IN \ + in_dword_masked(HWIO_GCC_RPMH_IPA_INTERFACE_FSM_ADDR, HWIO_GCC_RPMH_IPA_INTERFACE_FSM_RMSK) +#define HWIO_GCC_RPMH_IPA_INTERFACE_FSM_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_IPA_INTERFACE_FSM_ADDR, m) +#define HWIO_GCC_RPMH_IPA_INTERFACE_FSM_FSM_STATE_BMSK 0x1f +#define HWIO_GCC_RPMH_IPA_INTERFACE_FSM_FSM_STATE_SHFT 0x0 + +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_INTERFACE_FSM_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008b100) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_INTERFACE_FSM_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008b100) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_INTERFACE_FSM_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008b100) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_INTERFACE_FSM_RMSK 0x1f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_INTERFACE_FSM_ATTR 0x1 +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_INTERFACE_FSM_IN \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_INTERFACE_FSM_ADDR, HWIO_GCC_RPMH_QUPV3_CORE_2X_INTERFACE_FSM_RMSK) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_INTERFACE_FSM_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_INTERFACE_FSM_ADDR, m) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_INTERFACE_FSM_FSM_STATE_BMSK 0x1f +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_INTERFACE_FSM_FSM_STATE_SHFT 0x0 + +#define HWIO_GCC_RPMH_CE_INTERFACE_FSM_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00084100) +#define HWIO_GCC_RPMH_CE_INTERFACE_FSM_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00084100) +#define HWIO_GCC_RPMH_CE_INTERFACE_FSM_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00084100) +#define HWIO_GCC_RPMH_CE_INTERFACE_FSM_RMSK 0x1f +#define HWIO_GCC_RPMH_CE_INTERFACE_FSM_ATTR 0x1 +#define HWIO_GCC_RPMH_CE_INTERFACE_FSM_IN \ + in_dword_masked(HWIO_GCC_RPMH_CE_INTERFACE_FSM_ADDR, HWIO_GCC_RPMH_CE_INTERFACE_FSM_RMSK) +#define HWIO_GCC_RPMH_CE_INTERFACE_FSM_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CE_INTERFACE_FSM_ADDR, m) +#define HWIO_GCC_RPMH_CE_INTERFACE_FSM_FSM_STATE_BMSK 0x1f +#define HWIO_GCC_RPMH_CE_INTERFACE_FSM_FSM_STATE_SHFT 0x0 + +#define HWIO_GCC_RPMH_CDSP_NOC_INTERFACE_FSM_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008c100) +#define HWIO_GCC_RPMH_CDSP_NOC_INTERFACE_FSM_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008c100) +#define HWIO_GCC_RPMH_CDSP_NOC_INTERFACE_FSM_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008c100) +#define HWIO_GCC_RPMH_CDSP_NOC_INTERFACE_FSM_RMSK 0x1f +#define HWIO_GCC_RPMH_CDSP_NOC_INTERFACE_FSM_ATTR 0x1 +#define HWIO_GCC_RPMH_CDSP_NOC_INTERFACE_FSM_IN \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_INTERFACE_FSM_ADDR, HWIO_GCC_RPMH_CDSP_NOC_INTERFACE_FSM_RMSK) +#define HWIO_GCC_RPMH_CDSP_NOC_INTERFACE_FSM_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_INTERFACE_FSM_ADDR, m) +#define HWIO_GCC_RPMH_CDSP_NOC_INTERFACE_FSM_FSM_STATE_BMSK 0x1f +#define HWIO_GCC_RPMH_CDSP_NOC_INTERFACE_FSM_FSM_STATE_SHFT 0x0 + +#define HWIO_GCC_RPMH_MMNOC_INTERFACE_FSM_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00085100) +#define HWIO_GCC_RPMH_MMNOC_INTERFACE_FSM_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00085100) +#define HWIO_GCC_RPMH_MMNOC_INTERFACE_FSM_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00085100) +#define HWIO_GCC_RPMH_MMNOC_INTERFACE_FSM_RMSK 0x1f +#define HWIO_GCC_RPMH_MMNOC_INTERFACE_FSM_ATTR 0x1 +#define HWIO_GCC_RPMH_MMNOC_INTERFACE_FSM_IN \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_INTERFACE_FSM_ADDR, HWIO_GCC_RPMH_MMNOC_INTERFACE_FSM_RMSK) +#define HWIO_GCC_RPMH_MMNOC_INTERFACE_FSM_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_MMNOC_INTERFACE_FSM_ADDR, m) +#define HWIO_GCC_RPMH_MMNOC_INTERFACE_FSM_FSM_STATE_BMSK 0x1f +#define HWIO_GCC_RPMH_MMNOC_INTERFACE_FSM_FSM_STATE_SHFT 0x0 + +#define HWIO_GCC_RPMH_SHUB_INTERFACE_FSM_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00086100) +#define HWIO_GCC_RPMH_SHUB_INTERFACE_FSM_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00086100) +#define HWIO_GCC_RPMH_SHUB_INTERFACE_FSM_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00086100) +#define HWIO_GCC_RPMH_SHUB_INTERFACE_FSM_RMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_INTERFACE_FSM_ATTR 0x1 +#define HWIO_GCC_RPMH_SHUB_INTERFACE_FSM_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_INTERFACE_FSM_ADDR, HWIO_GCC_RPMH_SHUB_INTERFACE_FSM_RMSK) +#define HWIO_GCC_RPMH_SHUB_INTERFACE_FSM_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHUB_INTERFACE_FSM_ADDR, m) +#define HWIO_GCC_RPMH_SHUB_INTERFACE_FSM_FSM_STATE_BMSK 0x1f +#define HWIO_GCC_RPMH_SHUB_INTERFACE_FSM_FSM_STATE_SHFT 0x0 + +#define HWIO_GCC_RPMH_SHRM_INTERFACE_FSM_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00087100) +#define HWIO_GCC_RPMH_SHRM_INTERFACE_FSM_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00087100) +#define HWIO_GCC_RPMH_SHRM_INTERFACE_FSM_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00087100) +#define HWIO_GCC_RPMH_SHRM_INTERFACE_FSM_RMSK 0x1f +#define HWIO_GCC_RPMH_SHRM_INTERFACE_FSM_ATTR 0x1 +#define HWIO_GCC_RPMH_SHRM_INTERFACE_FSM_IN \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_INTERFACE_FSM_ADDR, HWIO_GCC_RPMH_SHRM_INTERFACE_FSM_RMSK) +#define HWIO_GCC_RPMH_SHRM_INTERFACE_FSM_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_SHRM_INTERFACE_FSM_ADDR, m) +#define HWIO_GCC_RPMH_SHRM_INTERFACE_FSM_FSM_STATE_BMSK 0x1f +#define HWIO_GCC_RPMH_SHRM_INTERFACE_FSM_FSM_STATE_SHFT 0x0 + +#define HWIO_GCC_RPMH_PMU_INTERFACE_FSM_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008a100) +#define HWIO_GCC_RPMH_PMU_INTERFACE_FSM_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a100) +#define HWIO_GCC_RPMH_PMU_INTERFACE_FSM_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a100) +#define HWIO_GCC_RPMH_PMU_INTERFACE_FSM_RMSK 0x1f +#define HWIO_GCC_RPMH_PMU_INTERFACE_FSM_ATTR 0x1 +#define HWIO_GCC_RPMH_PMU_INTERFACE_FSM_IN \ + in_dword_masked(HWIO_GCC_RPMH_PMU_INTERFACE_FSM_ADDR, HWIO_GCC_RPMH_PMU_INTERFACE_FSM_RMSK) +#define HWIO_GCC_RPMH_PMU_INTERFACE_FSM_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_PMU_INTERFACE_FSM_ADDR, m) +#define HWIO_GCC_RPMH_PMU_INTERFACE_FSM_FSM_STATE_BMSK 0x1f +#define HWIO_GCC_RPMH_PMU_INTERFACE_FSM_FSM_STATE_SHFT 0x0 + +#define HWIO_GCC_GPU_MEMNOC_GFX_CLK_EN_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00061250) +#define HWIO_GCC_GPU_MEMNOC_GFX_CLK_EN_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00061250) +#define HWIO_GCC_GPU_MEMNOC_GFX_CLK_EN_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00061250) +#define HWIO_GCC_GPU_MEMNOC_GFX_CLK_EN_RMSK 0x3 +#define HWIO_GCC_GPU_MEMNOC_GFX_CLK_EN_ATTR 0x3 +#define HWIO_GCC_GPU_MEMNOC_GFX_CLK_EN_IN \ + in_dword_masked(HWIO_GCC_GPU_MEMNOC_GFX_CLK_EN_ADDR, HWIO_GCC_GPU_MEMNOC_GFX_CLK_EN_RMSK) +#define HWIO_GCC_GPU_MEMNOC_GFX_CLK_EN_INM(m) \ + in_dword_masked(HWIO_GCC_GPU_MEMNOC_GFX_CLK_EN_ADDR, m) +#define HWIO_GCC_GPU_MEMNOC_GFX_CLK_EN_OUT(v) \ + out_dword(HWIO_GCC_GPU_MEMNOC_GFX_CLK_EN_ADDR,v) +#define HWIO_GCC_GPU_MEMNOC_GFX_CLK_EN_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GPU_MEMNOC_GFX_CLK_EN_ADDR,m,v,HWIO_GCC_GPU_MEMNOC_GFX_CLK_EN_IN) +#define HWIO_GCC_GPU_MEMNOC_GFX_CLK_EN_MUX_SELECT_BMSK 0x3 +#define HWIO_GCC_GPU_MEMNOC_GFX_CLK_EN_MUX_SELECT_SHFT 0x0 + +#define HWIO_GCC_MMU_MEMNOC_TCU_CLK_EN_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007323c) +#define HWIO_GCC_MMU_MEMNOC_TCU_CLK_EN_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007323c) +#define HWIO_GCC_MMU_MEMNOC_TCU_CLK_EN_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007323c) +#define HWIO_GCC_MMU_MEMNOC_TCU_CLK_EN_RMSK 0x3 +#define HWIO_GCC_MMU_MEMNOC_TCU_CLK_EN_ATTR 0x3 +#define HWIO_GCC_MMU_MEMNOC_TCU_CLK_EN_IN \ + in_dword_masked(HWIO_GCC_MMU_MEMNOC_TCU_CLK_EN_ADDR, HWIO_GCC_MMU_MEMNOC_TCU_CLK_EN_RMSK) +#define HWIO_GCC_MMU_MEMNOC_TCU_CLK_EN_INM(m) \ + in_dword_masked(HWIO_GCC_MMU_MEMNOC_TCU_CLK_EN_ADDR, m) +#define HWIO_GCC_MMU_MEMNOC_TCU_CLK_EN_OUT(v) \ + out_dword(HWIO_GCC_MMU_MEMNOC_TCU_CLK_EN_ADDR,v) +#define HWIO_GCC_MMU_MEMNOC_TCU_CLK_EN_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MMU_MEMNOC_TCU_CLK_EN_ADDR,m,v,HWIO_GCC_MMU_MEMNOC_TCU_CLK_EN_IN) +#define HWIO_GCC_MMU_MEMNOC_TCU_CLK_EN_MUX_SELECT_BMSK 0x3 +#define HWIO_GCC_MMU_MEMNOC_TCU_CLK_EN_MUX_SELECT_SHFT 0x0 + +#define HWIO_GCC_MMU_GDSC_MISC_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007324c) +#define HWIO_GCC_MMU_GDSC_MISC_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007324c) +#define HWIO_GCC_MMU_GDSC_MISC_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007324c) +#define HWIO_GCC_MMU_GDSC_MISC_RMSK 0x3 +#define HWIO_GCC_MMU_GDSC_MISC_ATTR 0x3 +#define HWIO_GCC_MMU_GDSC_MISC_IN \ + in_dword_masked(HWIO_GCC_MMU_GDSC_MISC_ADDR, HWIO_GCC_MMU_GDSC_MISC_RMSK) +#define HWIO_GCC_MMU_GDSC_MISC_INM(m) \ + in_dword_masked(HWIO_GCC_MMU_GDSC_MISC_ADDR, m) +#define HWIO_GCC_MMU_GDSC_MISC_OUT(v) \ + out_dword(HWIO_GCC_MMU_GDSC_MISC_ADDR,v) +#define HWIO_GCC_MMU_GDSC_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MMU_GDSC_MISC_ADDR,m,v,HWIO_GCC_MMU_GDSC_MISC_IN) +#define HWIO_GCC_MMU_GDSC_MISC_WAIT_FOR_LPASS_QTB_PWR_COLLAPSE_BMSK 0x2 +#define HWIO_GCC_MMU_GDSC_MISC_WAIT_FOR_LPASS_QTB_PWR_COLLAPSE_SHFT 0x1 +#define HWIO_GCC_MMU_GDSC_MISC_IGNORE_PMU_PWR_COLLAPSE_REQ_BMSK 0x1 +#define HWIO_GCC_MMU_GDSC_MISC_IGNORE_PMU_PWR_COLLAPSE_REQ_SHFT 0x0 + +#define HWIO_GCC_MEMNOC_TURING_CLK_EN_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00035490) +#define HWIO_GCC_MEMNOC_TURING_CLK_EN_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00035490) +#define HWIO_GCC_MEMNOC_TURING_CLK_EN_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00035490) +#define HWIO_GCC_MEMNOC_TURING_CLK_EN_RMSK 0x3 +#define HWIO_GCC_MEMNOC_TURING_CLK_EN_ATTR 0x3 +#define HWIO_GCC_MEMNOC_TURING_CLK_EN_IN \ + in_dword_masked(HWIO_GCC_MEMNOC_TURING_CLK_EN_ADDR, HWIO_GCC_MEMNOC_TURING_CLK_EN_RMSK) +#define HWIO_GCC_MEMNOC_TURING_CLK_EN_INM(m) \ + in_dword_masked(HWIO_GCC_MEMNOC_TURING_CLK_EN_ADDR, m) +#define HWIO_GCC_MEMNOC_TURING_CLK_EN_OUT(v) \ + out_dword(HWIO_GCC_MEMNOC_TURING_CLK_EN_ADDR,v) +#define HWIO_GCC_MEMNOC_TURING_CLK_EN_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MEMNOC_TURING_CLK_EN_ADDR,m,v,HWIO_GCC_MEMNOC_TURING_CLK_EN_IN) +#define HWIO_GCC_MEMNOC_TURING_CLK_EN_MUX_SELECT_BMSK 0x3 +#define HWIO_GCC_MEMNOC_TURING_CLK_EN_MUX_SELECT_SHFT 0x0 + +#define HWIO_GCC_MEMNOC_MSS_Q6_CLK_EN_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a38c) +#define HWIO_GCC_MEMNOC_MSS_Q6_CLK_EN_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007a38c) +#define HWIO_GCC_MEMNOC_MSS_Q6_CLK_EN_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007a38c) +#define HWIO_GCC_MEMNOC_MSS_Q6_CLK_EN_RMSK 0x3 +#define HWIO_GCC_MEMNOC_MSS_Q6_CLK_EN_ATTR 0x3 +#define HWIO_GCC_MEMNOC_MSS_Q6_CLK_EN_IN \ + in_dword_masked(HWIO_GCC_MEMNOC_MSS_Q6_CLK_EN_ADDR, HWIO_GCC_MEMNOC_MSS_Q6_CLK_EN_RMSK) +#define HWIO_GCC_MEMNOC_MSS_Q6_CLK_EN_INM(m) \ + in_dword_masked(HWIO_GCC_MEMNOC_MSS_Q6_CLK_EN_ADDR, m) +#define HWIO_GCC_MEMNOC_MSS_Q6_CLK_EN_OUT(v) \ + out_dword(HWIO_GCC_MEMNOC_MSS_Q6_CLK_EN_ADDR,v) +#define HWIO_GCC_MEMNOC_MSS_Q6_CLK_EN_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MEMNOC_MSS_Q6_CLK_EN_ADDR,m,v,HWIO_GCC_MEMNOC_MSS_Q6_CLK_EN_IN) +#define HWIO_GCC_MEMNOC_MSS_Q6_CLK_EN_MUX_SELECT_BMSK 0x3 +#define HWIO_GCC_MEMNOC_MSS_Q6_CLK_EN_MUX_SELECT_SHFT 0x0 + +#define HWIO_GCC_MEMNOC_MSS_OFFLINE_CLK_EN_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a390) +#define HWIO_GCC_MEMNOC_MSS_OFFLINE_CLK_EN_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007a390) +#define HWIO_GCC_MEMNOC_MSS_OFFLINE_CLK_EN_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007a390) +#define HWIO_GCC_MEMNOC_MSS_OFFLINE_CLK_EN_RMSK 0x3 +#define HWIO_GCC_MEMNOC_MSS_OFFLINE_CLK_EN_ATTR 0x3 +#define HWIO_GCC_MEMNOC_MSS_OFFLINE_CLK_EN_IN \ + in_dword_masked(HWIO_GCC_MEMNOC_MSS_OFFLINE_CLK_EN_ADDR, HWIO_GCC_MEMNOC_MSS_OFFLINE_CLK_EN_RMSK) +#define HWIO_GCC_MEMNOC_MSS_OFFLINE_CLK_EN_INM(m) \ + in_dword_masked(HWIO_GCC_MEMNOC_MSS_OFFLINE_CLK_EN_ADDR, m) +#define HWIO_GCC_MEMNOC_MSS_OFFLINE_CLK_EN_OUT(v) \ + out_dword(HWIO_GCC_MEMNOC_MSS_OFFLINE_CLK_EN_ADDR,v) +#define HWIO_GCC_MEMNOC_MSS_OFFLINE_CLK_EN_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MEMNOC_MSS_OFFLINE_CLK_EN_ADDR,m,v,HWIO_GCC_MEMNOC_MSS_OFFLINE_CLK_EN_IN) +#define HWIO_GCC_MEMNOC_MSS_OFFLINE_CLK_EN_MUX_SELECT_BMSK 0x3 +#define HWIO_GCC_MEMNOC_MSS_OFFLINE_CLK_EN_MUX_SELECT_SHFT 0x0 + +#define HWIO_GCC_LPASS_Q6SS_BOOT_GPLL0_MUXR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00037110) +#define HWIO_GCC_LPASS_Q6SS_BOOT_GPLL0_MUXR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00037110) +#define HWIO_GCC_LPASS_Q6SS_BOOT_GPLL0_MUXR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00037110) +#define HWIO_GCC_LPASS_Q6SS_BOOT_GPLL0_MUXR_RMSK 0x1 +#define HWIO_GCC_LPASS_Q6SS_BOOT_GPLL0_MUXR_ATTR 0x3 +#define HWIO_GCC_LPASS_Q6SS_BOOT_GPLL0_MUXR_IN \ + in_dword_masked(HWIO_GCC_LPASS_Q6SS_BOOT_GPLL0_MUXR_ADDR, HWIO_GCC_LPASS_Q6SS_BOOT_GPLL0_MUXR_RMSK) +#define HWIO_GCC_LPASS_Q6SS_BOOT_GPLL0_MUXR_INM(m) \ + in_dword_masked(HWIO_GCC_LPASS_Q6SS_BOOT_GPLL0_MUXR_ADDR, m) +#define HWIO_GCC_LPASS_Q6SS_BOOT_GPLL0_MUXR_OUT(v) \ + out_dword(HWIO_GCC_LPASS_Q6SS_BOOT_GPLL0_MUXR_ADDR,v) +#define HWIO_GCC_LPASS_Q6SS_BOOT_GPLL0_MUXR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_LPASS_Q6SS_BOOT_GPLL0_MUXR_ADDR,m,v,HWIO_GCC_LPASS_Q6SS_BOOT_GPLL0_MUXR_IN) +#define HWIO_GCC_LPASS_Q6SS_BOOT_GPLL0_MUXR_MUX_SEL_BMSK 0x1 +#define HWIO_GCC_LPASS_Q6SS_BOOT_GPLL0_MUXR_MUX_SEL_SHFT 0x0 + +#define HWIO_GCC_MSS_Q6SS_BOOT_GPLL0_MUXR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a360) +#define HWIO_GCC_MSS_Q6SS_BOOT_GPLL0_MUXR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007a360) +#define HWIO_GCC_MSS_Q6SS_BOOT_GPLL0_MUXR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007a360) +#define HWIO_GCC_MSS_Q6SS_BOOT_GPLL0_MUXR_RMSK 0x1 +#define HWIO_GCC_MSS_Q6SS_BOOT_GPLL0_MUXR_ATTR 0x3 +#define HWIO_GCC_MSS_Q6SS_BOOT_GPLL0_MUXR_IN \ + in_dword_masked(HWIO_GCC_MSS_Q6SS_BOOT_GPLL0_MUXR_ADDR, HWIO_GCC_MSS_Q6SS_BOOT_GPLL0_MUXR_RMSK) +#define HWIO_GCC_MSS_Q6SS_BOOT_GPLL0_MUXR_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_Q6SS_BOOT_GPLL0_MUXR_ADDR, m) +#define HWIO_GCC_MSS_Q6SS_BOOT_GPLL0_MUXR_OUT(v) \ + out_dword(HWIO_GCC_MSS_Q6SS_BOOT_GPLL0_MUXR_ADDR,v) +#define HWIO_GCC_MSS_Q6SS_BOOT_GPLL0_MUXR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_Q6SS_BOOT_GPLL0_MUXR_ADDR,m,v,HWIO_GCC_MSS_Q6SS_BOOT_GPLL0_MUXR_IN) +#define HWIO_GCC_MSS_Q6SS_BOOT_GPLL0_MUXR_MUX_SEL_BMSK 0x1 +#define HWIO_GCC_MSS_Q6SS_BOOT_GPLL0_MUXR_MUX_SEL_SHFT 0x0 + +#define HWIO_GCC_ACA_FAL10_VETO_ENABLE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003a000) +#define HWIO_GCC_ACA_FAL10_VETO_ENABLE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003a000) +#define HWIO_GCC_ACA_FAL10_VETO_ENABLE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003a000) +#define HWIO_GCC_ACA_FAL10_VETO_ENABLE_RMSK 0xffffffff +#define HWIO_GCC_ACA_FAL10_VETO_ENABLE_ATTR 0x3 +#define HWIO_GCC_ACA_FAL10_VETO_ENABLE_IN \ + in_dword_masked(HWIO_GCC_ACA_FAL10_VETO_ENABLE_ADDR, HWIO_GCC_ACA_FAL10_VETO_ENABLE_RMSK) +#define HWIO_GCC_ACA_FAL10_VETO_ENABLE_INM(m) \ + in_dword_masked(HWIO_GCC_ACA_FAL10_VETO_ENABLE_ADDR, m) +#define HWIO_GCC_ACA_FAL10_VETO_ENABLE_OUT(v) \ + out_dword(HWIO_GCC_ACA_FAL10_VETO_ENABLE_ADDR,v) +#define HWIO_GCC_ACA_FAL10_VETO_ENABLE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_ACA_FAL10_VETO_ENABLE_ADDR,m,v,HWIO_GCC_ACA_FAL10_VETO_ENABLE_IN) +#define HWIO_GCC_ACA_FAL10_VETO_ENABLE_CLK_ON_VETO_ENABLE_BMSK 0xffffffff +#define HWIO_GCC_ACA_FAL10_VETO_ENABLE_CLK_ON_VETO_ENABLE_SHFT 0x0 +#define HWIO_GCC_ACA_FAL10_VETO_ENABLE_CLK_ON_VETO_ENABLE_GCC_TIC_CFG_QX_CLK_ON_FVAL 0x0 +#define HWIO_GCC_ACA_FAL10_VETO_ENABLE_CLK_ON_VETO_ENABLE_GCC_QUPV3_WRAP_0_M_AHB_CLK_ON_FVAL 0x1 +#define HWIO_GCC_ACA_FAL10_VETO_ENABLE_CLK_ON_VETO_ENABLE_GCC_USB30_PRIM_MASTER_CLK_ON_FVAL 0x2 +#define HWIO_GCC_ACA_FAL10_VETO_ENABLE_CLK_ON_VETO_ENABLE_GCC_USB30_SEC_MASTER_CLK_ON_FVAL 0x3 +#define HWIO_GCC_ACA_FAL10_VETO_ENABLE_CLK_ON_VETO_ENABLE_GCC_QUPV3_WRAP_1_M_AHB_CLK_ON_FVAL 0x4 +#define HWIO_GCC_ACA_FAL10_VETO_ENABLE_CLK_ON_VETO_ENABLE_GCC_QUPV3_WRAP_2_M_AHB_CLK_ON_FVAL 0x5 +#define HWIO_GCC_ACA_FAL10_VETO_ENABLE_CLK_ON_VETO_ENABLE_GCC_SDCC2_AHB_CLK_ON_FVAL 0x7 +#define HWIO_GCC_ACA_FAL10_VETO_ENABLE_CLK_ON_VETO_ENABLE_GCC_SDCC4_AHB_CLK_ON_FVAL 0x8 +#define HWIO_GCC_ACA_FAL10_VETO_ENABLE_CLK_ON_VETO_ENABLE_GCC_QSPI_CNOC_PERIPH_AHB_CLK_ON_FVAL 0x9 +#define HWIO_GCC_ACA_FAL10_VETO_ENABLE_CLK_ON_VETO_ENABLE_GCC_IPA_CLK_ON_FVAL 0xa +#define HWIO_GCC_ACA_FAL10_VETO_ENABLE_CLK_ON_VETO_ENABLE_GCC_CE1_AXI_CLK_ON_FVAL 0xb +#define HWIO_GCC_ACA_FAL10_VETO_ENABLE_CLK_ON_VETO_ENABLE_GCC_QDSS_ETR_USB_CLK_ON_FVAL 0xc +#define HWIO_GCC_ACA_FAL10_VETO_ENABLE_CLK_ON_VETO_ENABLE_GCC_SP_SNOC_ANOC_AXI_CLK_ON_FVAL 0xd +#define HWIO_GCC_ACA_FAL10_VETO_ENABLE_CLK_ON_VETO_ENABLE_GCC_UFS_CARD_AXI_CLK_ON_FVAL 0xe +#define HWIO_GCC_ACA_FAL10_VETO_ENABLE_CLK_ON_VETO_ENABLE_GCC_UFS_PHY_AXI_CLK_ON_FVAL 0xf + +#define HWIO_GCC_PLL_MISC_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00048000) +#define HWIO_GCC_PLL_MISC_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00048000) +#define HWIO_GCC_PLL_MISC_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00048000) +#define HWIO_GCC_PLL_MISC_RMSK 0x1 +#define HWIO_GCC_PLL_MISC_ATTR 0x3 +#define HWIO_GCC_PLL_MISC_IN \ + in_dword_masked(HWIO_GCC_PLL_MISC_ADDR, HWIO_GCC_PLL_MISC_RMSK) +#define HWIO_GCC_PLL_MISC_INM(m) \ + in_dword_masked(HWIO_GCC_PLL_MISC_ADDR, m) +#define HWIO_GCC_PLL_MISC_OUT(v) \ + out_dword(HWIO_GCC_PLL_MISC_ADDR,v) +#define HWIO_GCC_PLL_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PLL_MISC_ADDR,m,v,HWIO_GCC_PLL_MISC_IN) +#define HWIO_GCC_PLL_MISC_HW_TRIGGERED_PLL_STBY_DIS_BMSK 0x1 +#define HWIO_GCC_PLL_MISC_HW_TRIGGERED_PLL_STBY_DIS_SHFT 0x0 +#define HWIO_GCC_PLL_MISC_HW_TRIGGERED_PLL_STBY_DIS_FEATURE_ON_FVAL 0x0 +#define HWIO_GCC_PLL_MISC_HW_TRIGGERED_PLL_STBY_DIS_FEATURE_OFF_FVAL 0x1 + +#define HWIO_GCC_RPMH_ALL_CLK_OFF_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00048004) +#define HWIO_GCC_RPMH_ALL_CLK_OFF_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00048004) +#define HWIO_GCC_RPMH_ALL_CLK_OFF_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00048004) +#define HWIO_GCC_RPMH_ALL_CLK_OFF_RMSK 0x1 +#define HWIO_GCC_RPMH_ALL_CLK_OFF_ATTR 0x3 +#define HWIO_GCC_RPMH_ALL_CLK_OFF_IN \ + in_dword_masked(HWIO_GCC_RPMH_ALL_CLK_OFF_ADDR, HWIO_GCC_RPMH_ALL_CLK_OFF_RMSK) +#define HWIO_GCC_RPMH_ALL_CLK_OFF_INM(m) \ + in_dword_masked(HWIO_GCC_RPMH_ALL_CLK_OFF_ADDR, m) +#define HWIO_GCC_RPMH_ALL_CLK_OFF_OUT(v) \ + out_dword(HWIO_GCC_RPMH_ALL_CLK_OFF_ADDR,v) +#define HWIO_GCC_RPMH_ALL_CLK_OFF_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPMH_ALL_CLK_OFF_ADDR,m,v,HWIO_GCC_RPMH_ALL_CLK_OFF_IN) +#define HWIO_GCC_RPMH_ALL_CLK_OFF_MUX_SEL_BMSK 0x1 +#define HWIO_GCC_RPMH_ALL_CLK_OFF_MUX_SEL_SHFT 0x0 +#define HWIO_GCC_RPMH_ALL_CLK_OFF_MUX_SEL_SELECT_GCC_AND_SUBCC_ALL_CLKS_OFF_FVAL 0x0 +#define HWIO_GCC_RPMH_ALL_CLK_OFF_MUX_SEL_SELECT_GCC_ONLY_ALL_CLKS_OFF_FVAL 0x1 + +#define HWIO_GCC_GDSC_ALL_CLK_OFF_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00048008) +#define HWIO_GCC_GDSC_ALL_CLK_OFF_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00048008) +#define HWIO_GCC_GDSC_ALL_CLK_OFF_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00048008) +#define HWIO_GCC_GDSC_ALL_CLK_OFF_RMSK 0x3fff +#define HWIO_GCC_GDSC_ALL_CLK_OFF_ATTR 0x3 +#define HWIO_GCC_GDSC_ALL_CLK_OFF_IN \ + in_dword_masked(HWIO_GCC_GDSC_ALL_CLK_OFF_ADDR, HWIO_GCC_GDSC_ALL_CLK_OFF_RMSK) +#define HWIO_GCC_GDSC_ALL_CLK_OFF_INM(m) \ + in_dword_masked(HWIO_GCC_GDSC_ALL_CLK_OFF_ADDR, m) +#define HWIO_GCC_GDSC_ALL_CLK_OFF_OUT(v) \ + out_dword(HWIO_GCC_GDSC_ALL_CLK_OFF_ADDR,v) +#define HWIO_GCC_GDSC_ALL_CLK_OFF_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_GDSC_ALL_CLK_OFF_ADDR,m,v,HWIO_GCC_GDSC_ALL_CLK_OFF_IN) +#define HWIO_GCC_GDSC_ALL_CLK_OFF_IPA_GDSCR_SW_POWER_DOWN_COMPLETE_BMSK 0x2000 +#define HWIO_GCC_GDSC_ALL_CLK_OFF_IPA_GDSCR_SW_POWER_DOWN_COMPLETE_SHFT 0xd +#define HWIO_GCC_GDSC_ALL_CLK_OFF_ANOC_PCIE_GDSCR_SW_POWER_DOWN_COMPLETE_BMSK 0x1000 +#define HWIO_GCC_GDSC_ALL_CLK_OFF_ANOC_PCIE_GDSCR_SW_POWER_DOWN_COMPLETE_SHFT 0xc +#define HWIO_GCC_GDSC_ALL_CLK_OFF_MMU_GDSCR_SW_POWER_DOWN_COMPLETE_BMSK 0x800 +#define HWIO_GCC_GDSC_ALL_CLK_OFF_MMU_GDSCR_SW_POWER_DOWN_COMPLETE_SHFT 0xb +#define HWIO_GCC_GDSC_ALL_CLK_OFF_MMNOC_GDSCR_SW_POWER_DOWN_COMPLETE_BMSK 0x400 +#define HWIO_GCC_GDSC_ALL_CLK_OFF_MMNOC_GDSCR_SW_POWER_DOWN_COMPLETE_SHFT 0xa +#define HWIO_GCC_GDSC_ALL_CLK_OFF_USB30_PRIM_GDSCR_SW_POWER_DOWN_COMPLETE_BMSK 0x200 +#define HWIO_GCC_GDSC_ALL_CLK_OFF_USB30_PRIM_GDSCR_SW_POWER_DOWN_COMPLETE_SHFT 0x9 +#define HWIO_GCC_GDSC_ALL_CLK_OFF_USB3_PHY_GDSCR_SW_POWER_DOWN_COMPLETE_BMSK 0x100 +#define HWIO_GCC_GDSC_ALL_CLK_OFF_USB3_PHY_GDSCR_SW_POWER_DOWN_COMPLETE_SHFT 0x8 +#define HWIO_GCC_GDSC_ALL_CLK_OFF_LPASS_QTB_GDSCR_SW_POWER_DOWN_COMPLETE_BMSK 0x80 +#define HWIO_GCC_GDSC_ALL_CLK_OFF_LPASS_QTB_GDSCR_SW_POWER_DOWN_COMPLETE_SHFT 0x7 +#define HWIO_GCC_GDSC_ALL_CLK_OFF_TURING_QTB_GDSCR_SW_POWER_DOWN_COMPLETE_BMSK 0x40 +#define HWIO_GCC_GDSC_ALL_CLK_OFF_TURING_QTB_GDSCR_SW_POWER_DOWN_COMPLETE_SHFT 0x6 +#define HWIO_GCC_GDSC_ALL_CLK_OFF_PCIE_0_GDSCR_SW_POWER_DOWN_COMPLETE_BMSK 0x20 +#define HWIO_GCC_GDSC_ALL_CLK_OFF_PCIE_0_GDSCR_SW_POWER_DOWN_COMPLETE_SHFT 0x5 +#define HWIO_GCC_GDSC_ALL_CLK_OFF_PCIE_0_PHY_GDSCR_SW_POWER_DOWN_COMPLETE_BMSK 0x10 +#define HWIO_GCC_GDSC_ALL_CLK_OFF_PCIE_0_PHY_GDSCR_SW_POWER_DOWN_COMPLETE_SHFT 0x4 +#define HWIO_GCC_GDSC_ALL_CLK_OFF_PCIE_1_GDSCR_SW_POWER_DOWN_COMPLETE_BMSK 0x8 +#define HWIO_GCC_GDSC_ALL_CLK_OFF_PCIE_1_GDSCR_SW_POWER_DOWN_COMPLETE_SHFT 0x3 +#define HWIO_GCC_GDSC_ALL_CLK_OFF_PCIE_1_PHY_GDSCR_SW_POWER_DOWN_COMPLETE_BMSK 0x4 +#define HWIO_GCC_GDSC_ALL_CLK_OFF_PCIE_1_PHY_GDSCR_SW_POWER_DOWN_COMPLETE_SHFT 0x2 +#define HWIO_GCC_GDSC_ALL_CLK_OFF_UFS_MEM_PHY_GDSCR_SW_POWER_DOWN_COMPLETE_BMSK 0x2 +#define HWIO_GCC_GDSC_ALL_CLK_OFF_UFS_MEM_PHY_GDSCR_SW_POWER_DOWN_COMPLETE_SHFT 0x1 +#define HWIO_GCC_GDSC_ALL_CLK_OFF_UFS_PHY_GDSCR_SW_POWER_DOWN_COMPLETE_BMSK 0x1 +#define HWIO_GCC_GDSC_ALL_CLK_OFF_UFS_PHY_GDSCR_SW_POWER_DOWN_COMPLETE_SHFT 0x0 + +#define HWIO_GCC_PLL_ALL_CLK_OFF_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004800c) +#define HWIO_GCC_PLL_ALL_CLK_OFF_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004800c) +#define HWIO_GCC_PLL_ALL_CLK_OFF_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004800c) +#define HWIO_GCC_PLL_ALL_CLK_OFF_RMSK 0x1 +#define HWIO_GCC_PLL_ALL_CLK_OFF_ATTR 0x3 +#define HWIO_GCC_PLL_ALL_CLK_OFF_IN \ + in_dword_masked(HWIO_GCC_PLL_ALL_CLK_OFF_ADDR, HWIO_GCC_PLL_ALL_CLK_OFF_RMSK) +#define HWIO_GCC_PLL_ALL_CLK_OFF_INM(m) \ + in_dword_masked(HWIO_GCC_PLL_ALL_CLK_OFF_ADDR, m) +#define HWIO_GCC_PLL_ALL_CLK_OFF_OUT(v) \ + out_dword(HWIO_GCC_PLL_ALL_CLK_OFF_ADDR,v) +#define HWIO_GCC_PLL_ALL_CLK_OFF_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_PLL_ALL_CLK_OFF_ADDR,m,v,HWIO_GCC_PLL_ALL_CLK_OFF_IN) +#define HWIO_GCC_PLL_ALL_CLK_OFF_MUX_SEL_BMSK 0x1 +#define HWIO_GCC_PLL_ALL_CLK_OFF_MUX_SEL_SHFT 0x0 + +#define HWIO_GCC_SP_GDSC_BRANCH_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002f058) +#define HWIO_GCC_SP_GDSC_BRANCH_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002f058) +#define HWIO_GCC_SP_GDSC_BRANCH_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002f058) +#define HWIO_GCC_SP_GDSC_BRANCH_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_SP_GDSC_BRANCH_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_SP_GDSC_BRANCH_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_SP_GDSC_BRANCH_ENA_VOTE_ADDR, HWIO_GCC_SP_GDSC_BRANCH_ENA_VOTE_RMSK) +#define HWIO_GCC_SP_GDSC_BRANCH_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_SP_GDSC_BRANCH_ENA_VOTE_ADDR, m) +#define HWIO_GCC_SP_GDSC_BRANCH_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_SP_GDSC_BRANCH_ENA_VOTE_ADDR,v) +#define HWIO_GCC_SP_GDSC_BRANCH_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SP_GDSC_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_SP_GDSC_BRANCH_ENA_VOTE_IN) +#define HWIO_GCC_SP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_BMSK 0x10 +#define HWIO_GCC_SP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_SHFT 0x4 +#define HWIO_GCC_SP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_BMSK 0x8 +#define HWIO_GCC_SP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_SHFT 0x3 +#define HWIO_GCC_SP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_GDSC_BRANCH_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_BMSK 0x4 +#define HWIO_GCC_SP_GDSC_BRANCH_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_SHFT 0x2 +#define HWIO_GCC_SP_GDSC_BRANCH_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_GDSC_BRANCH_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_BMSK 0x2 +#define HWIO_GCC_SP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_SHFT 0x1 +#define HWIO_GCC_SP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_SP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_SP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SP_GDSC_SLEEP_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002f05c) +#define HWIO_GCC_SP_GDSC_SLEEP_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002f05c) +#define HWIO_GCC_SP_GDSC_SLEEP_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002f05c) +#define HWIO_GCC_SP_GDSC_SLEEP_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_SP_GDSC_SLEEP_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_SP_GDSC_SLEEP_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_SP_GDSC_SLEEP_ENA_VOTE_ADDR, HWIO_GCC_SP_GDSC_SLEEP_ENA_VOTE_RMSK) +#define HWIO_GCC_SP_GDSC_SLEEP_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_SP_GDSC_SLEEP_ENA_VOTE_ADDR, m) +#define HWIO_GCC_SP_GDSC_SLEEP_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_SP_GDSC_SLEEP_ENA_VOTE_ADDR,v) +#define HWIO_GCC_SP_GDSC_SLEEP_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SP_GDSC_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_SP_GDSC_SLEEP_ENA_VOTE_IN) +#define HWIO_GCC_SP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_BMSK 0x10 +#define HWIO_GCC_SP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_SHFT 0x4 +#define HWIO_GCC_SP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_BMSK 0x8 +#define HWIO_GCC_SP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_SHFT 0x3 +#define HWIO_GCC_SP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_GDSC_SLEEP_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_BMSK 0x4 +#define HWIO_GCC_SP_GDSC_SLEEP_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_SHFT 0x2 +#define HWIO_GCC_SP_GDSC_SLEEP_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_GDSC_SLEEP_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_BMSK 0x2 +#define HWIO_GCC_SP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_SHFT 0x1 +#define HWIO_GCC_SP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_SP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_SP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPM_GDSC_BRANCH_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00041020) +#define HWIO_GCC_RPM_GDSC_BRANCH_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00041020) +#define HWIO_GCC_RPM_GDSC_BRANCH_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00041020) +#define HWIO_GCC_RPM_GDSC_BRANCH_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPM_GDSC_BRANCH_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPM_GDSC_BRANCH_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPM_GDSC_BRANCH_ENA_VOTE_ADDR, HWIO_GCC_RPM_GDSC_BRANCH_ENA_VOTE_RMSK) +#define HWIO_GCC_RPM_GDSC_BRANCH_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPM_GDSC_BRANCH_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPM_GDSC_BRANCH_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPM_GDSC_BRANCH_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPM_GDSC_BRANCH_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPM_GDSC_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPM_GDSC_BRANCH_ENA_VOTE_IN) +#define HWIO_GCC_RPM_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_BMSK 0x10 +#define HWIO_GCC_RPM_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_SHFT 0x4 +#define HWIO_GCC_RPM_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_BMSK 0x8 +#define HWIO_GCC_RPM_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_SHFT 0x3 +#define HWIO_GCC_RPM_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_GDSC_BRANCH_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_BMSK 0x4 +#define HWIO_GCC_RPM_GDSC_BRANCH_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_SHFT 0x2 +#define HWIO_GCC_RPM_GDSC_BRANCH_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_GDSC_BRANCH_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_BMSK 0x2 +#define HWIO_GCC_RPM_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_SHFT 0x1 +#define HWIO_GCC_RPM_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_RPM_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_RPM_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_RPM_GDSC_SLEEP_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00041024) +#define HWIO_GCC_RPM_GDSC_SLEEP_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00041024) +#define HWIO_GCC_RPM_GDSC_SLEEP_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00041024) +#define HWIO_GCC_RPM_GDSC_SLEEP_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_RPM_GDSC_SLEEP_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_RPM_GDSC_SLEEP_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_RPM_GDSC_SLEEP_ENA_VOTE_ADDR, HWIO_GCC_RPM_GDSC_SLEEP_ENA_VOTE_RMSK) +#define HWIO_GCC_RPM_GDSC_SLEEP_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_RPM_GDSC_SLEEP_ENA_VOTE_ADDR, m) +#define HWIO_GCC_RPM_GDSC_SLEEP_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_RPM_GDSC_SLEEP_ENA_VOTE_ADDR,v) +#define HWIO_GCC_RPM_GDSC_SLEEP_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_RPM_GDSC_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPM_GDSC_SLEEP_ENA_VOTE_IN) +#define HWIO_GCC_RPM_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_BMSK 0x10 +#define HWIO_GCC_RPM_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_SHFT 0x4 +#define HWIO_GCC_RPM_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_BMSK 0x8 +#define HWIO_GCC_RPM_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_SHFT 0x3 +#define HWIO_GCC_RPM_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_GDSC_SLEEP_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_BMSK 0x4 +#define HWIO_GCC_RPM_GDSC_SLEEP_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_SHFT 0x2 +#define HWIO_GCC_RPM_GDSC_SLEEP_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_GDSC_SLEEP_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_BMSK 0x2 +#define HWIO_GCC_RPM_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_SHFT 0x1 +#define HWIO_GCC_RPM_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_RPM_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_RPM_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_RPM_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_RPM_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_APCS_GDSC_BRANCH_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00042020) +#define HWIO_GCC_APCS_GDSC_BRANCH_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00042020) +#define HWIO_GCC_APCS_GDSC_BRANCH_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00042020) +#define HWIO_GCC_APCS_GDSC_BRANCH_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_APCS_GDSC_BRANCH_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_APCS_GDSC_BRANCH_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_APCS_GDSC_BRANCH_ENA_VOTE_ADDR, HWIO_GCC_APCS_GDSC_BRANCH_ENA_VOTE_RMSK) +#define HWIO_GCC_APCS_GDSC_BRANCH_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_APCS_GDSC_BRANCH_ENA_VOTE_ADDR, m) +#define HWIO_GCC_APCS_GDSC_BRANCH_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_APCS_GDSC_BRANCH_ENA_VOTE_ADDR,v) +#define HWIO_GCC_APCS_GDSC_BRANCH_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_APCS_GDSC_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_APCS_GDSC_BRANCH_ENA_VOTE_IN) +#define HWIO_GCC_APCS_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_BMSK 0x10 +#define HWIO_GCC_APCS_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_SHFT 0x4 +#define HWIO_GCC_APCS_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_BMSK 0x8 +#define HWIO_GCC_APCS_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_SHFT 0x3 +#define HWIO_GCC_APCS_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_GDSC_BRANCH_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_BMSK 0x4 +#define HWIO_GCC_APCS_GDSC_BRANCH_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_SHFT 0x2 +#define HWIO_GCC_APCS_GDSC_BRANCH_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_GDSC_BRANCH_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_BMSK 0x2 +#define HWIO_GCC_APCS_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_SHFT 0x1 +#define HWIO_GCC_APCS_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_APCS_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_APCS_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_APCS_GDSC_SLEEP_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00042024) +#define HWIO_GCC_APCS_GDSC_SLEEP_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00042024) +#define HWIO_GCC_APCS_GDSC_SLEEP_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00042024) +#define HWIO_GCC_APCS_GDSC_SLEEP_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_APCS_GDSC_SLEEP_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_APCS_GDSC_SLEEP_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_APCS_GDSC_SLEEP_ENA_VOTE_ADDR, HWIO_GCC_APCS_GDSC_SLEEP_ENA_VOTE_RMSK) +#define HWIO_GCC_APCS_GDSC_SLEEP_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_APCS_GDSC_SLEEP_ENA_VOTE_ADDR, m) +#define HWIO_GCC_APCS_GDSC_SLEEP_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_APCS_GDSC_SLEEP_ENA_VOTE_ADDR,v) +#define HWIO_GCC_APCS_GDSC_SLEEP_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_APCS_GDSC_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_APCS_GDSC_SLEEP_ENA_VOTE_IN) +#define HWIO_GCC_APCS_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_BMSK 0x10 +#define HWIO_GCC_APCS_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_SHFT 0x4 +#define HWIO_GCC_APCS_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_BMSK 0x8 +#define HWIO_GCC_APCS_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_SHFT 0x3 +#define HWIO_GCC_APCS_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_GDSC_SLEEP_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_BMSK 0x4 +#define HWIO_GCC_APCS_GDSC_SLEEP_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_SHFT 0x2 +#define HWIO_GCC_APCS_GDSC_SLEEP_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_GDSC_SLEEP_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_BMSK 0x2 +#define HWIO_GCC_APCS_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_SHFT 0x1 +#define HWIO_GCC_APCS_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_APCS_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_APCS_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_APCS_TZ_GDSC_BRANCH_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00043058) +#define HWIO_GCC_APCS_TZ_GDSC_BRANCH_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00043058) +#define HWIO_GCC_APCS_TZ_GDSC_BRANCH_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00043058) +#define HWIO_GCC_APCS_TZ_GDSC_BRANCH_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_APCS_TZ_GDSC_BRANCH_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_APCS_TZ_GDSC_BRANCH_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_APCS_TZ_GDSC_BRANCH_ENA_VOTE_ADDR, HWIO_GCC_APCS_TZ_GDSC_BRANCH_ENA_VOTE_RMSK) +#define HWIO_GCC_APCS_TZ_GDSC_BRANCH_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_APCS_TZ_GDSC_BRANCH_ENA_VOTE_ADDR, m) +#define HWIO_GCC_APCS_TZ_GDSC_BRANCH_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_APCS_TZ_GDSC_BRANCH_ENA_VOTE_ADDR,v) +#define HWIO_GCC_APCS_TZ_GDSC_BRANCH_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_APCS_TZ_GDSC_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_APCS_TZ_GDSC_BRANCH_ENA_VOTE_IN) +#define HWIO_GCC_APCS_TZ_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_BMSK 0x10 +#define HWIO_GCC_APCS_TZ_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_SHFT 0x4 +#define HWIO_GCC_APCS_TZ_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_BMSK 0x8 +#define HWIO_GCC_APCS_TZ_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_SHFT 0x3 +#define HWIO_GCC_APCS_TZ_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_GDSC_BRANCH_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_BMSK 0x4 +#define HWIO_GCC_APCS_TZ_GDSC_BRANCH_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_SHFT 0x2 +#define HWIO_GCC_APCS_TZ_GDSC_BRANCH_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_GDSC_BRANCH_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_BMSK 0x2 +#define HWIO_GCC_APCS_TZ_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_SHFT 0x1 +#define HWIO_GCC_APCS_TZ_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_APCS_TZ_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_APCS_TZ_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_APCS_TZ_GDSC_SLEEP_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004305c) +#define HWIO_GCC_APCS_TZ_GDSC_SLEEP_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004305c) +#define HWIO_GCC_APCS_TZ_GDSC_SLEEP_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004305c) +#define HWIO_GCC_APCS_TZ_GDSC_SLEEP_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_APCS_TZ_GDSC_SLEEP_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_APCS_TZ_GDSC_SLEEP_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_APCS_TZ_GDSC_SLEEP_ENA_VOTE_ADDR, HWIO_GCC_APCS_TZ_GDSC_SLEEP_ENA_VOTE_RMSK) +#define HWIO_GCC_APCS_TZ_GDSC_SLEEP_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_APCS_TZ_GDSC_SLEEP_ENA_VOTE_ADDR, m) +#define HWIO_GCC_APCS_TZ_GDSC_SLEEP_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_APCS_TZ_GDSC_SLEEP_ENA_VOTE_ADDR,v) +#define HWIO_GCC_APCS_TZ_GDSC_SLEEP_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_APCS_TZ_GDSC_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_APCS_TZ_GDSC_SLEEP_ENA_VOTE_IN) +#define HWIO_GCC_APCS_TZ_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_BMSK 0x10 +#define HWIO_GCC_APCS_TZ_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_SHFT 0x4 +#define HWIO_GCC_APCS_TZ_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_BMSK 0x8 +#define HWIO_GCC_APCS_TZ_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_SHFT 0x3 +#define HWIO_GCC_APCS_TZ_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_GDSC_SLEEP_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_BMSK 0x4 +#define HWIO_GCC_APCS_TZ_GDSC_SLEEP_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_SHFT 0x2 +#define HWIO_GCC_APCS_TZ_GDSC_SLEEP_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_GDSC_SLEEP_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_BMSK 0x2 +#define HWIO_GCC_APCS_TZ_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_SHFT 0x1 +#define HWIO_GCC_APCS_TZ_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_APCS_TZ_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_APCS_TZ_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_APCS_TZ_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_APCS_TZ_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_LPASS_DSP_GDSC_BRANCH_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00045020) +#define HWIO_GCC_LPASS_DSP_GDSC_BRANCH_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00045020) +#define HWIO_GCC_LPASS_DSP_GDSC_BRANCH_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00045020) +#define HWIO_GCC_LPASS_DSP_GDSC_BRANCH_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_LPASS_DSP_GDSC_BRANCH_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_LPASS_DSP_GDSC_BRANCH_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_LPASS_DSP_GDSC_BRANCH_ENA_VOTE_ADDR, HWIO_GCC_LPASS_DSP_GDSC_BRANCH_ENA_VOTE_RMSK) +#define HWIO_GCC_LPASS_DSP_GDSC_BRANCH_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_LPASS_DSP_GDSC_BRANCH_ENA_VOTE_ADDR, m) +#define HWIO_GCC_LPASS_DSP_GDSC_BRANCH_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_LPASS_DSP_GDSC_BRANCH_ENA_VOTE_ADDR,v) +#define HWIO_GCC_LPASS_DSP_GDSC_BRANCH_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_LPASS_DSP_GDSC_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_LPASS_DSP_GDSC_BRANCH_ENA_VOTE_IN) +#define HWIO_GCC_LPASS_DSP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_BMSK 0x10 +#define HWIO_GCC_LPASS_DSP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_SHFT 0x4 +#define HWIO_GCC_LPASS_DSP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_BMSK 0x8 +#define HWIO_GCC_LPASS_DSP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_SHFT 0x3 +#define HWIO_GCC_LPASS_DSP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_GDSC_BRANCH_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_BMSK 0x4 +#define HWIO_GCC_LPASS_DSP_GDSC_BRANCH_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_SHFT 0x2 +#define HWIO_GCC_LPASS_DSP_GDSC_BRANCH_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_GDSC_BRANCH_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_BMSK 0x2 +#define HWIO_GCC_LPASS_DSP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_SHFT 0x1 +#define HWIO_GCC_LPASS_DSP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_LPASS_DSP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_LPASS_DSP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_LPASS_DSP_GDSC_SLEEP_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00045024) +#define HWIO_GCC_LPASS_DSP_GDSC_SLEEP_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00045024) +#define HWIO_GCC_LPASS_DSP_GDSC_SLEEP_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00045024) +#define HWIO_GCC_LPASS_DSP_GDSC_SLEEP_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_LPASS_DSP_GDSC_SLEEP_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_LPASS_DSP_GDSC_SLEEP_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_LPASS_DSP_GDSC_SLEEP_ENA_VOTE_ADDR, HWIO_GCC_LPASS_DSP_GDSC_SLEEP_ENA_VOTE_RMSK) +#define HWIO_GCC_LPASS_DSP_GDSC_SLEEP_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_LPASS_DSP_GDSC_SLEEP_ENA_VOTE_ADDR, m) +#define HWIO_GCC_LPASS_DSP_GDSC_SLEEP_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_LPASS_DSP_GDSC_SLEEP_ENA_VOTE_ADDR,v) +#define HWIO_GCC_LPASS_DSP_GDSC_SLEEP_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_LPASS_DSP_GDSC_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_LPASS_DSP_GDSC_SLEEP_ENA_VOTE_IN) +#define HWIO_GCC_LPASS_DSP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_BMSK 0x10 +#define HWIO_GCC_LPASS_DSP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_SHFT 0x4 +#define HWIO_GCC_LPASS_DSP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_BMSK 0x8 +#define HWIO_GCC_LPASS_DSP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_SHFT 0x3 +#define HWIO_GCC_LPASS_DSP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_GDSC_SLEEP_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_BMSK 0x4 +#define HWIO_GCC_LPASS_DSP_GDSC_SLEEP_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_SHFT 0x2 +#define HWIO_GCC_LPASS_DSP_GDSC_SLEEP_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_GDSC_SLEEP_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_BMSK 0x2 +#define HWIO_GCC_LPASS_DSP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_SHFT 0x1 +#define HWIO_GCC_LPASS_DSP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_LPASS_DSP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_LPASS_DSP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_LPASS_DSP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_LPASS_DSP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TURING_DSP_GDSC_BRANCH_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004b020) +#define HWIO_GCC_TURING_DSP_GDSC_BRANCH_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004b020) +#define HWIO_GCC_TURING_DSP_GDSC_BRANCH_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004b020) +#define HWIO_GCC_TURING_DSP_GDSC_BRANCH_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_TURING_DSP_GDSC_BRANCH_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_TURING_DSP_GDSC_BRANCH_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_TURING_DSP_GDSC_BRANCH_ENA_VOTE_ADDR, HWIO_GCC_TURING_DSP_GDSC_BRANCH_ENA_VOTE_RMSK) +#define HWIO_GCC_TURING_DSP_GDSC_BRANCH_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_TURING_DSP_GDSC_BRANCH_ENA_VOTE_ADDR, m) +#define HWIO_GCC_TURING_DSP_GDSC_BRANCH_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_TURING_DSP_GDSC_BRANCH_ENA_VOTE_ADDR,v) +#define HWIO_GCC_TURING_DSP_GDSC_BRANCH_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TURING_DSP_GDSC_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_TURING_DSP_GDSC_BRANCH_ENA_VOTE_IN) +#define HWIO_GCC_TURING_DSP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_BMSK 0x10 +#define HWIO_GCC_TURING_DSP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_SHFT 0x4 +#define HWIO_GCC_TURING_DSP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_BMSK 0x8 +#define HWIO_GCC_TURING_DSP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_SHFT 0x3 +#define HWIO_GCC_TURING_DSP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_GDSC_BRANCH_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_BMSK 0x4 +#define HWIO_GCC_TURING_DSP_GDSC_BRANCH_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_SHFT 0x2 +#define HWIO_GCC_TURING_DSP_GDSC_BRANCH_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_GDSC_BRANCH_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_BMSK 0x2 +#define HWIO_GCC_TURING_DSP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_SHFT 0x1 +#define HWIO_GCC_TURING_DSP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_TURING_DSP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_TURING_DSP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TURING_DSP_GDSC_SLEEP_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004b024) +#define HWIO_GCC_TURING_DSP_GDSC_SLEEP_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004b024) +#define HWIO_GCC_TURING_DSP_GDSC_SLEEP_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004b024) +#define HWIO_GCC_TURING_DSP_GDSC_SLEEP_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_TURING_DSP_GDSC_SLEEP_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_TURING_DSP_GDSC_SLEEP_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_TURING_DSP_GDSC_SLEEP_ENA_VOTE_ADDR, HWIO_GCC_TURING_DSP_GDSC_SLEEP_ENA_VOTE_RMSK) +#define HWIO_GCC_TURING_DSP_GDSC_SLEEP_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_TURING_DSP_GDSC_SLEEP_ENA_VOTE_ADDR, m) +#define HWIO_GCC_TURING_DSP_GDSC_SLEEP_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_TURING_DSP_GDSC_SLEEP_ENA_VOTE_ADDR,v) +#define HWIO_GCC_TURING_DSP_GDSC_SLEEP_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TURING_DSP_GDSC_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_TURING_DSP_GDSC_SLEEP_ENA_VOTE_IN) +#define HWIO_GCC_TURING_DSP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_BMSK 0x10 +#define HWIO_GCC_TURING_DSP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_SHFT 0x4 +#define HWIO_GCC_TURING_DSP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_BMSK 0x8 +#define HWIO_GCC_TURING_DSP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_SHFT 0x3 +#define HWIO_GCC_TURING_DSP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_GDSC_SLEEP_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_BMSK 0x4 +#define HWIO_GCC_TURING_DSP_GDSC_SLEEP_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_SHFT 0x2 +#define HWIO_GCC_TURING_DSP_GDSC_SLEEP_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_GDSC_SLEEP_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_BMSK 0x2 +#define HWIO_GCC_TURING_DSP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_SHFT 0x1 +#define HWIO_GCC_TURING_DSP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TURING_DSP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_TURING_DSP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_TURING_DSP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TURING_DSP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPARE_GDSC_BRANCH_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00047020) +#define HWIO_GCC_SPARE_GDSC_BRANCH_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00047020) +#define HWIO_GCC_SPARE_GDSC_BRANCH_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00047020) +#define HWIO_GCC_SPARE_GDSC_BRANCH_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_SPARE_GDSC_BRANCH_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_SPARE_GDSC_BRANCH_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_SPARE_GDSC_BRANCH_ENA_VOTE_ADDR, HWIO_GCC_SPARE_GDSC_BRANCH_ENA_VOTE_RMSK) +#define HWIO_GCC_SPARE_GDSC_BRANCH_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_SPARE_GDSC_BRANCH_ENA_VOTE_ADDR, m) +#define HWIO_GCC_SPARE_GDSC_BRANCH_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_SPARE_GDSC_BRANCH_ENA_VOTE_ADDR,v) +#define HWIO_GCC_SPARE_GDSC_BRANCH_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPARE_GDSC_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_SPARE_GDSC_BRANCH_ENA_VOTE_IN) +#define HWIO_GCC_SPARE_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_BMSK 0x10 +#define HWIO_GCC_SPARE_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_SHFT 0x4 +#define HWIO_GCC_SPARE_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_BMSK 0x8 +#define HWIO_GCC_SPARE_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_SHFT 0x3 +#define HWIO_GCC_SPARE_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_GDSC_BRANCH_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_BMSK 0x4 +#define HWIO_GCC_SPARE_GDSC_BRANCH_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_SHFT 0x2 +#define HWIO_GCC_SPARE_GDSC_BRANCH_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_GDSC_BRANCH_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_BMSK 0x2 +#define HWIO_GCC_SPARE_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_SHFT 0x1 +#define HWIO_GCC_SPARE_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_SPARE_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_SPARE_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPARE_GDSC_SLEEP_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00047024) +#define HWIO_GCC_SPARE_GDSC_SLEEP_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00047024) +#define HWIO_GCC_SPARE_GDSC_SLEEP_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00047024) +#define HWIO_GCC_SPARE_GDSC_SLEEP_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_SPARE_GDSC_SLEEP_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_SPARE_GDSC_SLEEP_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_SPARE_GDSC_SLEEP_ENA_VOTE_ADDR, HWIO_GCC_SPARE_GDSC_SLEEP_ENA_VOTE_RMSK) +#define HWIO_GCC_SPARE_GDSC_SLEEP_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_SPARE_GDSC_SLEEP_ENA_VOTE_ADDR, m) +#define HWIO_GCC_SPARE_GDSC_SLEEP_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_SPARE_GDSC_SLEEP_ENA_VOTE_ADDR,v) +#define HWIO_GCC_SPARE_GDSC_SLEEP_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPARE_GDSC_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_SPARE_GDSC_SLEEP_ENA_VOTE_IN) +#define HWIO_GCC_SPARE_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_BMSK 0x10 +#define HWIO_GCC_SPARE_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_SHFT 0x4 +#define HWIO_GCC_SPARE_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_BMSK 0x8 +#define HWIO_GCC_SPARE_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_SHFT 0x3 +#define HWIO_GCC_SPARE_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_GDSC_SLEEP_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_BMSK 0x4 +#define HWIO_GCC_SPARE_GDSC_SLEEP_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_SHFT 0x2 +#define HWIO_GCC_SPARE_GDSC_SLEEP_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_GDSC_SLEEP_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_BMSK 0x2 +#define HWIO_GCC_SPARE_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_SHFT 0x1 +#define HWIO_GCC_SPARE_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_SPARE_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_SPARE_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_Q6_GDSC_BRANCH_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00025058) +#define HWIO_GCC_MSS_Q6_GDSC_BRANCH_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00025058) +#define HWIO_GCC_MSS_Q6_GDSC_BRANCH_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00025058) +#define HWIO_GCC_MSS_Q6_GDSC_BRANCH_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_MSS_Q6_GDSC_BRANCH_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_MSS_Q6_GDSC_BRANCH_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_MSS_Q6_GDSC_BRANCH_ENA_VOTE_ADDR, HWIO_GCC_MSS_Q6_GDSC_BRANCH_ENA_VOTE_RMSK) +#define HWIO_GCC_MSS_Q6_GDSC_BRANCH_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_Q6_GDSC_BRANCH_ENA_VOTE_ADDR, m) +#define HWIO_GCC_MSS_Q6_GDSC_BRANCH_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_MSS_Q6_GDSC_BRANCH_ENA_VOTE_ADDR,v) +#define HWIO_GCC_MSS_Q6_GDSC_BRANCH_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_Q6_GDSC_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_MSS_Q6_GDSC_BRANCH_ENA_VOTE_IN) +#define HWIO_GCC_MSS_Q6_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_BMSK 0x10 +#define HWIO_GCC_MSS_Q6_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_SHFT 0x4 +#define HWIO_GCC_MSS_Q6_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_BMSK 0x8 +#define HWIO_GCC_MSS_Q6_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_SHFT 0x3 +#define HWIO_GCC_MSS_Q6_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_GDSC_BRANCH_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_BMSK 0x4 +#define HWIO_GCC_MSS_Q6_GDSC_BRANCH_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_SHFT 0x2 +#define HWIO_GCC_MSS_Q6_GDSC_BRANCH_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_GDSC_BRANCH_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_BMSK 0x2 +#define HWIO_GCC_MSS_Q6_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_SHFT 0x1 +#define HWIO_GCC_MSS_Q6_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_MSS_Q6_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_MSS_Q6_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_MSS_Q6_GDSC_SLEEP_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0002505c) +#define HWIO_GCC_MSS_Q6_GDSC_SLEEP_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0002505c) +#define HWIO_GCC_MSS_Q6_GDSC_SLEEP_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0002505c) +#define HWIO_GCC_MSS_Q6_GDSC_SLEEP_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_MSS_Q6_GDSC_SLEEP_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_MSS_Q6_GDSC_SLEEP_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_MSS_Q6_GDSC_SLEEP_ENA_VOTE_ADDR, HWIO_GCC_MSS_Q6_GDSC_SLEEP_ENA_VOTE_RMSK) +#define HWIO_GCC_MSS_Q6_GDSC_SLEEP_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_MSS_Q6_GDSC_SLEEP_ENA_VOTE_ADDR, m) +#define HWIO_GCC_MSS_Q6_GDSC_SLEEP_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_MSS_Q6_GDSC_SLEEP_ENA_VOTE_ADDR,v) +#define HWIO_GCC_MSS_Q6_GDSC_SLEEP_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_MSS_Q6_GDSC_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_MSS_Q6_GDSC_SLEEP_ENA_VOTE_IN) +#define HWIO_GCC_MSS_Q6_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_BMSK 0x10 +#define HWIO_GCC_MSS_Q6_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_SHFT 0x4 +#define HWIO_GCC_MSS_Q6_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_BMSK 0x8 +#define HWIO_GCC_MSS_Q6_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_SHFT 0x3 +#define HWIO_GCC_MSS_Q6_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_GDSC_SLEEP_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_BMSK 0x4 +#define HWIO_GCC_MSS_Q6_GDSC_SLEEP_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_SHFT 0x2 +#define HWIO_GCC_MSS_Q6_GDSC_SLEEP_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_GDSC_SLEEP_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_BMSK 0x2 +#define HWIO_GCC_MSS_Q6_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_SHFT 0x1 +#define HWIO_GCC_MSS_Q6_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_MSS_Q6_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_MSS_Q6_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_MSS_Q6_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_MSS_Q6_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HYP_GDSC_BRANCH_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00046020) +#define HWIO_GCC_HYP_GDSC_BRANCH_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00046020) +#define HWIO_GCC_HYP_GDSC_BRANCH_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00046020) +#define HWIO_GCC_HYP_GDSC_BRANCH_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_HYP_GDSC_BRANCH_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_HYP_GDSC_BRANCH_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_HYP_GDSC_BRANCH_ENA_VOTE_ADDR, HWIO_GCC_HYP_GDSC_BRANCH_ENA_VOTE_RMSK) +#define HWIO_GCC_HYP_GDSC_BRANCH_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_HYP_GDSC_BRANCH_ENA_VOTE_ADDR, m) +#define HWIO_GCC_HYP_GDSC_BRANCH_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_HYP_GDSC_BRANCH_ENA_VOTE_ADDR,v) +#define HWIO_GCC_HYP_GDSC_BRANCH_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HYP_GDSC_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_HYP_GDSC_BRANCH_ENA_VOTE_IN) +#define HWIO_GCC_HYP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_BMSK 0x10 +#define HWIO_GCC_HYP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_SHFT 0x4 +#define HWIO_GCC_HYP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_BMSK 0x8 +#define HWIO_GCC_HYP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_SHFT 0x3 +#define HWIO_GCC_HYP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_GDSC_BRANCH_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_BMSK 0x4 +#define HWIO_GCC_HYP_GDSC_BRANCH_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_SHFT 0x2 +#define HWIO_GCC_HYP_GDSC_BRANCH_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_GDSC_BRANCH_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_BMSK 0x2 +#define HWIO_GCC_HYP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_SHFT 0x1 +#define HWIO_GCC_HYP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_HYP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_HYP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_HYP_GDSC_SLEEP_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00046024) +#define HWIO_GCC_HYP_GDSC_SLEEP_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00046024) +#define HWIO_GCC_HYP_GDSC_SLEEP_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00046024) +#define HWIO_GCC_HYP_GDSC_SLEEP_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_HYP_GDSC_SLEEP_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_HYP_GDSC_SLEEP_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_HYP_GDSC_SLEEP_ENA_VOTE_ADDR, HWIO_GCC_HYP_GDSC_SLEEP_ENA_VOTE_RMSK) +#define HWIO_GCC_HYP_GDSC_SLEEP_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_HYP_GDSC_SLEEP_ENA_VOTE_ADDR, m) +#define HWIO_GCC_HYP_GDSC_SLEEP_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_HYP_GDSC_SLEEP_ENA_VOTE_ADDR,v) +#define HWIO_GCC_HYP_GDSC_SLEEP_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_HYP_GDSC_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_HYP_GDSC_SLEEP_ENA_VOTE_IN) +#define HWIO_GCC_HYP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_BMSK 0x10 +#define HWIO_GCC_HYP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_SHFT 0x4 +#define HWIO_GCC_HYP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_BMSK 0x8 +#define HWIO_GCC_HYP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_SHFT 0x3 +#define HWIO_GCC_HYP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_GDSC_SLEEP_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_BMSK 0x4 +#define HWIO_GCC_HYP_GDSC_SLEEP_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_SHFT 0x2 +#define HWIO_GCC_HYP_GDSC_SLEEP_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_GDSC_SLEEP_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_BMSK 0x2 +#define HWIO_GCC_HYP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_SHFT 0x1 +#define HWIO_GCC_HYP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_HYP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_HYP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_HYP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_HYP_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPARE1_GDSC_BRANCH_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004a020) +#define HWIO_GCC_SPARE1_GDSC_BRANCH_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004a020) +#define HWIO_GCC_SPARE1_GDSC_BRANCH_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004a020) +#define HWIO_GCC_SPARE1_GDSC_BRANCH_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_SPARE1_GDSC_BRANCH_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_SPARE1_GDSC_BRANCH_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_SPARE1_GDSC_BRANCH_ENA_VOTE_ADDR, HWIO_GCC_SPARE1_GDSC_BRANCH_ENA_VOTE_RMSK) +#define HWIO_GCC_SPARE1_GDSC_BRANCH_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_SPARE1_GDSC_BRANCH_ENA_VOTE_ADDR, m) +#define HWIO_GCC_SPARE1_GDSC_BRANCH_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_SPARE1_GDSC_BRANCH_ENA_VOTE_ADDR,v) +#define HWIO_GCC_SPARE1_GDSC_BRANCH_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPARE1_GDSC_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_SPARE1_GDSC_BRANCH_ENA_VOTE_IN) +#define HWIO_GCC_SPARE1_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_BMSK 0x10 +#define HWIO_GCC_SPARE1_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_SHFT 0x4 +#define HWIO_GCC_SPARE1_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_BMSK 0x8 +#define HWIO_GCC_SPARE1_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_SHFT 0x3 +#define HWIO_GCC_SPARE1_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_GDSC_BRANCH_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_BMSK 0x4 +#define HWIO_GCC_SPARE1_GDSC_BRANCH_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_SHFT 0x2 +#define HWIO_GCC_SPARE1_GDSC_BRANCH_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_GDSC_BRANCH_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_BMSK 0x2 +#define HWIO_GCC_SPARE1_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_SHFT 0x1 +#define HWIO_GCC_SPARE1_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_SPARE1_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_SPARE1_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_SPARE1_GDSC_SLEEP_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004a024) +#define HWIO_GCC_SPARE1_GDSC_SLEEP_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004a024) +#define HWIO_GCC_SPARE1_GDSC_SLEEP_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004a024) +#define HWIO_GCC_SPARE1_GDSC_SLEEP_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_SPARE1_GDSC_SLEEP_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_SPARE1_GDSC_SLEEP_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_SPARE1_GDSC_SLEEP_ENA_VOTE_ADDR, HWIO_GCC_SPARE1_GDSC_SLEEP_ENA_VOTE_RMSK) +#define HWIO_GCC_SPARE1_GDSC_SLEEP_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_SPARE1_GDSC_SLEEP_ENA_VOTE_ADDR, m) +#define HWIO_GCC_SPARE1_GDSC_SLEEP_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_SPARE1_GDSC_SLEEP_ENA_VOTE_ADDR,v) +#define HWIO_GCC_SPARE1_GDSC_SLEEP_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_SPARE1_GDSC_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_SPARE1_GDSC_SLEEP_ENA_VOTE_IN) +#define HWIO_GCC_SPARE1_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_BMSK 0x10 +#define HWIO_GCC_SPARE1_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_SHFT 0x4 +#define HWIO_GCC_SPARE1_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_BMSK 0x8 +#define HWIO_GCC_SPARE1_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_SHFT 0x3 +#define HWIO_GCC_SPARE1_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_GDSC_SLEEP_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_BMSK 0x4 +#define HWIO_GCC_SPARE1_GDSC_SLEEP_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_SHFT 0x2 +#define HWIO_GCC_SPARE1_GDSC_SLEEP_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_GDSC_SLEEP_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_BMSK 0x2 +#define HWIO_GCC_SPARE1_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_SHFT 0x1 +#define HWIO_GCC_SPARE1_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_SPARE1_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_SPARE1_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_SPARE1_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_SPARE1_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TME_GDSC_BRANCH_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00059058) +#define HWIO_GCC_TME_GDSC_BRANCH_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00059058) +#define HWIO_GCC_TME_GDSC_BRANCH_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00059058) +#define HWIO_GCC_TME_GDSC_BRANCH_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_TME_GDSC_BRANCH_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_TME_GDSC_BRANCH_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_TME_GDSC_BRANCH_ENA_VOTE_ADDR, HWIO_GCC_TME_GDSC_BRANCH_ENA_VOTE_RMSK) +#define HWIO_GCC_TME_GDSC_BRANCH_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_TME_GDSC_BRANCH_ENA_VOTE_ADDR, m) +#define HWIO_GCC_TME_GDSC_BRANCH_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_TME_GDSC_BRANCH_ENA_VOTE_ADDR,v) +#define HWIO_GCC_TME_GDSC_BRANCH_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TME_GDSC_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_TME_GDSC_BRANCH_ENA_VOTE_IN) +#define HWIO_GCC_TME_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_BMSK 0x10 +#define HWIO_GCC_TME_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_SHFT 0x4 +#define HWIO_GCC_TME_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_BMSK 0x8 +#define HWIO_GCC_TME_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_SHFT 0x3 +#define HWIO_GCC_TME_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_GDSC_BRANCH_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_BMSK 0x4 +#define HWIO_GCC_TME_GDSC_BRANCH_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_SHFT 0x2 +#define HWIO_GCC_TME_GDSC_BRANCH_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_GDSC_BRANCH_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_BMSK 0x2 +#define HWIO_GCC_TME_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_SHFT 0x1 +#define HWIO_GCC_TME_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_TME_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_TME_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_GDSC_BRANCH_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 + +#define HWIO_GCC_TME_GDSC_SLEEP_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0005905c) +#define HWIO_GCC_TME_GDSC_SLEEP_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005905c) +#define HWIO_GCC_TME_GDSC_SLEEP_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005905c) +#define HWIO_GCC_TME_GDSC_SLEEP_ENA_VOTE_RMSK 0x1f +#define HWIO_GCC_TME_GDSC_SLEEP_ENA_VOTE_ATTR 0x3 +#define HWIO_GCC_TME_GDSC_SLEEP_ENA_VOTE_IN \ + in_dword_masked(HWIO_GCC_TME_GDSC_SLEEP_ENA_VOTE_ADDR, HWIO_GCC_TME_GDSC_SLEEP_ENA_VOTE_RMSK) +#define HWIO_GCC_TME_GDSC_SLEEP_ENA_VOTE_INM(m) \ + in_dword_masked(HWIO_GCC_TME_GDSC_SLEEP_ENA_VOTE_ADDR, m) +#define HWIO_GCC_TME_GDSC_SLEEP_ENA_VOTE_OUT(v) \ + out_dword(HWIO_GCC_TME_GDSC_SLEEP_ENA_VOTE_ADDR,v) +#define HWIO_GCC_TME_GDSC_SLEEP_ENA_VOTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_GCC_TME_GDSC_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_TME_GDSC_SLEEP_ENA_VOTE_IN) +#define HWIO_GCC_TME_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_BMSK 0x10 +#define HWIO_GCC_TME_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_SHFT 0x4 +#define HWIO_GCC_TME_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_PHY_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_BMSK 0x8 +#define HWIO_GCC_TME_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_SHFT 0x3 +#define HWIO_GCC_TME_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_PHY_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_GDSC_SLEEP_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_BMSK 0x4 +#define HWIO_GCC_TME_GDSC_SLEEP_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_SHFT 0x2 +#define HWIO_GCC_TME_GDSC_SLEEP_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_GDSC_SLEEP_ENA_VOTE_GCC_ANOC_PCIE_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_BMSK 0x2 +#define HWIO_GCC_TME_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_SHFT 0x1 +#define HWIO_GCC_TME_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_1_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 +#define HWIO_GCC_TME_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_BMSK 0x1 +#define HWIO_GCC_TME_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_SHFT 0x0 +#define HWIO_GCC_TME_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_DISABLE_FVAL 0x0 +#define HWIO_GCC_TME_GDSC_SLEEP_ENA_VOTE_GCC_PCIE_0_GDSC_SW_COLLAPSE_ENABLE_FVAL 0x1 + + +#endif /* __IPA_GCC_HWIO_H__ */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.5/ipa_gcc_hwio_def.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.5/ipa_gcc_hwio_def.h new file mode 100644 index 0000000000..d206e049c6 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.5/ipa_gcc_hwio_def.h @@ -0,0 +1,62964 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef __IPA_GCC_HWIO_DEF_H__ +#define __IPA_GCC_HWIO_DEF_H__ +/** + @file ipa_gcc_hwio.h + @brief Auto-generated HWIO interface include file. + + This file contains HWIO register definitions for the following modules: + GCC_CLK_CTL_REG.* + + 'Include' filters applied: + 'Exclude' filters applied: RESERVED DUMMY +*/ + +/*---------------------------------------------------------------------------- + * MODULE: GCC_CLK_CTL_REG + *--------------------------------------------------------------------------*/ + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_ACGCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpll0_ufs_phy_tx_symbol_0_acgcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpll0_ufs_phy_tx_symbol_0_acgcr_u +{ + struct ipa_gcc_hwio_def_gcc_gpll0_ufs_phy_tx_symbol_0_acgcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_ACGCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpll0_ufs_phy_rx_symbol_0_acgcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpll0_ufs_phy_rx_symbol_0_acgcr_u +{ + struct ipa_gcc_hwio_def_gcc_gpll0_ufs_phy_rx_symbol_0_acgcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_ACGCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpll0_ufs_phy_rx_symbol_1_acgcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpll0_ufs_phy_rx_symbol_1_acgcr_u +{ + struct ipa_gcc_hwio_def_gcc_gpll0_ufs_phy_rx_symbol_1_acgcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB3_PRIM_PHY_PIPE_MUXR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb3_prim_phy_pipe_muxr_s +{ + u32 mux_sel : 2; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb3_prim_phy_pipe_muxr_u +{ + struct ipa_gcc_hwio_def_gcc_usb3_prim_phy_pipe_muxr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_0_PIPE_MUXR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_0_pipe_muxr_s +{ + u32 mux_sel : 2; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_0_pipe_muxr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_0_pipe_muxr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_0_MBIST_MUXR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_0_mbist_muxr_s +{ + u32 mux_sel : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_0_mbist_muxr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_0_mbist_muxr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_0_MBIST_PLL_TEST_SE_MUXR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_0_mbist_pll_test_se_muxr_s +{ + u32 mux_sel : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_0_mbist_pll_test_se_muxr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_0_mbist_pll_test_se_muxr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_1_PIPE_MUXR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_1_pipe_muxr_s +{ + u32 mux_sel : 2; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_1_pipe_muxr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_1_pipe_muxr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_1_PHY_AUX_MUXR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_1_phy_aux_muxr_s +{ + u32 mux_sel : 2; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_1_phy_aux_muxr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_1_phy_aux_muxr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_1_MBIST_MUXR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_1_mbist_muxr_s +{ + u32 mux_sel : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_1_mbist_muxr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_1_mbist_muxr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_1_MBIST_PLL_TEST_SE_MUXR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_1_mbist_pll_test_se_muxr_s +{ + u32 mux_sel : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_1_mbist_pll_test_se_muxr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_1_mbist_pll_test_se_muxr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_TX_SYMBOL_0_MUX_MUXR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpll0_and_pll_test_se_ufs_phy_tx_symbol_0_mux_muxr_s +{ + u32 mux_sel : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpll0_and_pll_test_se_ufs_phy_tx_symbol_0_mux_muxr_u +{ + struct ipa_gcc_hwio_def_gcc_gpll0_and_pll_test_se_ufs_phy_tx_symbol_0_mux_muxr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_UFS_PHY_TX_SYMBOL_0_MUXR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ufs_phy_tx_symbol_0_muxr_s +{ + u32 mux_sel : 2; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ufs_phy_tx_symbol_0_muxr_u +{ + struct ipa_gcc_hwio_def_gcc_ufs_phy_tx_symbol_0_muxr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_0_MUX_MUXR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpll0_and_pll_test_se_ufs_phy_rx_symbol_0_mux_muxr_s +{ + u32 mux_sel : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpll0_and_pll_test_se_ufs_phy_rx_symbol_0_mux_muxr_u +{ + struct ipa_gcc_hwio_def_gcc_gpll0_and_pll_test_se_ufs_phy_rx_symbol_0_mux_muxr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_UFS_PHY_RX_SYMBOL_0_MUXR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ufs_phy_rx_symbol_0_muxr_s +{ + u32 mux_sel : 2; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ufs_phy_rx_symbol_0_muxr_u +{ + struct ipa_gcc_hwio_def_gcc_ufs_phy_rx_symbol_0_muxr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_1_MUX_MUXR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpll0_and_pll_test_se_ufs_phy_rx_symbol_1_mux_muxr_s +{ + u32 mux_sel : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpll0_and_pll_test_se_ufs_phy_rx_symbol_1_mux_muxr_u +{ + struct ipa_gcc_hwio_def_gcc_gpll0_and_pll_test_se_ufs_phy_rx_symbol_1_mux_muxr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_UFS_PHY_RX_SYMBOL_1_MUXR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ufs_phy_rx_symbol_1_muxr_s +{ + u32 mux_sel : 2; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ufs_phy_rx_symbol_1_muxr_u +{ + struct ipa_gcc_hwio_def_gcc_ufs_phy_rx_symbol_1_muxr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SYSTEM_NOC_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_system_noc_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_system_noc_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_system_noc_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SYS_NOC_CPUSS_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sys_noc_cpuss_ahb_cbcr_s +{ + u32 reserved0 : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved1 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sys_noc_cpuss_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_sys_noc_cpuss_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SYS_NOC_NAV_QX_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sys_noc_nav_qx_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sys_noc_nav_qx_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_sys_noc_nav_qx_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SYS_NOC_TME_QXM_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sys_noc_tme_qxm_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sys_noc_tme_qxm_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_sys_noc_tme_qxm_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SYS_NOC_AXI_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sys_noc_axi_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sys_noc_axi_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_sys_noc_axi_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SYS_NOC_GC_AXI_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sys_noc_gc_axi_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 ignore_pmu_clk_dis : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sys_noc_gc_axi_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_sys_noc_gc_axi_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SYS_NOC_SF_AXI_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sys_noc_sf_axi_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 8; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved1 : 5; + u32 ignore_rpmh_clk_dis : 1; + u32 ignore_pmu_clk_dis : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sys_noc_sf_axi_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_sys_noc_sf_axi_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SYS_NOC_SF_AXI_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sys_noc_sf_axi_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 4; + u32 pwr_fsm_clk_sel : 1; + u32 reserved1 : 3; + u32 sreg_pscbc_spare_ctrl_out : 4; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sys_noc_sf_axi_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_sys_noc_sf_axi_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SYS_NOC_SF_AXI_CFG_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sys_noc_sf_axi_cfg_sregr_s +{ + u32 wakeup_timer : 8; + u32 sleep_timer : 8; + u32 mem_cph_timer : 6; + u32 mem_core_on_status : 1; + u32 mem_periph_on_status : 1; + u32 mem_core_on_ack_status : 1; + u32 mem_periph_on_ack_status : 1; + u32 mem_core_off_timer : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sys_noc_sf_axi_cfg_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_sys_noc_sf_axi_cfg_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SYS_NOC_AHB_CFG_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sys_noc_ahb_cfg_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sys_noc_ahb_cfg_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_sys_noc_ahb_cfg_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SYS_NOC_AT_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sys_noc_at_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sys_noc_at_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_sys_noc_at_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SYS_NOC_QOSGEN_EXTREF_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sys_noc_qosgen_extref_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sys_noc_qosgen_extref_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_sys_noc_qosgen_extref_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SYS_NOC_TME_DCD_CDIV_DCDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sys_noc_tme_dcd_cdiv_dcdr_s +{ + u32 dcd_enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sys_noc_tme_dcd_cdiv_dcdr_u +{ + struct ipa_gcc_hwio_def_gcc_sys_noc_tme_dcd_cdiv_dcdr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SYS_NOC_NAV_DCD_CDIV_DCDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sys_noc_nav_dcd_cdiv_dcdr_s +{ + u32 dcd_enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sys_noc_nav_dcd_cdiv_dcdr_u +{ + struct ipa_gcc_hwio_def_gcc_sys_noc_nav_dcd_cdiv_dcdr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_CMD_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_cmd_dfsr_s +{ + u32 dfs_en : 1; + u32 curr_perf_state : 4; + u32 hw_clk_control : 1; + u32 dfs_fsm_state : 3; + u32 perf_state_update_status : 1; + u32 sw_override : 1; + u32 sw_perf_state : 4; + u32 rcg_sw_ctrl : 7; + u32 reserved0 : 10; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_cmd_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_cmd_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_gc_axi_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_gc_axi_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_gc_axi_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_gc_axi_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_gc_axi_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_gc_axi_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_gc_axi_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_gc_axi_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_gc_axi_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_gc_axi_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_gc_axi_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_gc_axi_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_gc_axi_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_gc_axi_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_gc_axi_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_gc_axi_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_gc_axi_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_gc_axi_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_gc_axi_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_gc_axi_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_gc_axi_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_gc_axi_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_gc_axi_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_gc_axi_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_gc_axi_perf8_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_gc_axi_perf8_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_gc_axi_perf8_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_gc_axi_perf9_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_gc_axi_perf9_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_gc_axi_perf9_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_gc_axi_perf10_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_gc_axi_perf10_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_gc_axi_perf10_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_gc_axi_perf11_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_gc_axi_perf11_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_gc_axi_perf11_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_gc_axi_perf12_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_gc_axi_perf12_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_gc_axi_perf12_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_gc_axi_perf13_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_gc_axi_perf13_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_gc_axi_perf13_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_gc_axi_perf14_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_gc_axi_perf14_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_gc_axi_perf14_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_gc_axi_perf15_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_gc_axi_perf15_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_gc_axi_perf15_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SYS_NOC_GC_AXI_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sys_noc_gc_axi_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sys_noc_gc_axi_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_sys_noc_gc_axi_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SYS_NOC_GC_AXI_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sys_noc_gc_axi_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sys_noc_gc_axi_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_sys_noc_gc_axi_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SYS_NOC_GC_DCD_CDIV_DCDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sys_noc_gc_dcd_cdiv_dcdr_s +{ + u32 dcd_enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sys_noc_gc_dcd_cdiv_dcdr_u +{ + struct ipa_gcc_hwio_def_gcc_sys_noc_gc_dcd_cdiv_dcdr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf8_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf8_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf8_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf9_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf9_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf9_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf10_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf10_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf10_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf11_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf11_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf11_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf12_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf12_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf12_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf13_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf13_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf13_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf14_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf14_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf14_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf15_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf15_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_perf15_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SYS_NOC_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sys_noc_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sys_noc_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_sys_noc_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SYS_NOC_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sys_noc_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sys_noc_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_sys_noc_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SYS_NOC_DCD_CDIV_DCDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sys_noc_dcd_cdiv_dcdr_s +{ + u32 dcd_enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sys_noc_dcd_cdiv_dcdr_u +{ + struct ipa_gcc_hwio_def_gcc_sys_noc_dcd_cdiv_dcdr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_sf_axi_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_sf_axi_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_sf_axi_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_sf_axi_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_sf_axi_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_sf_axi_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_sf_axi_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_sf_axi_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_sf_axi_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_sf_axi_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_sf_axi_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_sf_axi_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_sf_axi_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_sf_axi_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_sf_axi_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_sf_axi_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_sf_axi_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_sf_axi_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_sf_axi_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_sf_axi_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_sf_axi_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_sf_axi_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_sf_axi_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_sf_axi_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_sf_axi_perf8_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_sf_axi_perf8_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_sf_axi_perf8_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_sf_axi_perf9_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_sf_axi_perf9_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_sf_axi_perf9_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_sf_axi_perf10_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_sf_axi_perf10_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_sf_axi_perf10_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_sf_axi_perf11_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_sf_axi_perf11_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_sf_axi_perf11_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_sf_axi_perf12_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_sf_axi_perf12_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_sf_axi_perf12_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_sf_axi_perf13_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_sf_axi_perf13_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_sf_axi_perf13_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_sf_axi_perf14_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_sf_axi_perf14_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_sf_axi_perf14_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_sf_axi_perf15_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_sf_axi_perf15_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_sys_noc_sf_axi_perf15_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SYS_NOC_SF_AXI_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sys_noc_sf_axi_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sys_noc_sf_axi_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_sys_noc_sf_axi_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SYS_NOC_SF_AXI_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sys_noc_sf_axi_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sys_noc_sf_axi_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_sys_noc_sf_axi_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SYS_NOC_SF_DCD_CDIV_DCDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sys_noc_sf_dcd_cdiv_dcdr_s +{ + u32 dcd_enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sys_noc_sf_dcd_cdiv_dcdr_u +{ + struct ipa_gcc_hwio_def_gcc_sys_noc_sf_dcd_cdiv_dcdr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CONFIG_NOC_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_config_noc_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_config_noc_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_config_noc_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CNOC_APSS_QH_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cnoc_apss_qh_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cnoc_apss_qh_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_cnoc_apss_qh_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CNOC_CENTER_QX_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cnoc_center_qx_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cnoc_center_qx_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_cnoc_center_qx_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CNOC_SF_QX_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cnoc_sf_qx_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cnoc_sf_qx_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_cnoc_sf_qx_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CNOC_NORTH_QX_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cnoc_north_qx_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cnoc_north_qx_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_cnoc_north_qx_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CNOC_PERIPH_SOUTH_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cnoc_periph_south_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cnoc_periph_south_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_cnoc_periph_south_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CNOC_PERIPH_NORTH_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cnoc_periph_north_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cnoc_periph_north_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_cnoc_periph_north_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CFG_NOC_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cfg_noc_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cfg_noc_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_cfg_noc_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CFG_NOC_WEST_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cfg_noc_west_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cfg_noc_west_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_cfg_noc_west_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CNOC_PCIE_SF_AXI_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cnoc_pcie_sf_axi_cbcr_s +{ + u32 reserved0 : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved1 : 8; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved2 : 5; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved3 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved4 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cnoc_pcie_sf_axi_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_cnoc_pcie_sf_axi_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CNOC_PCIE_SF_AXI_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cnoc_pcie_sf_axi_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 4; + u32 pwr_fsm_clk_sel : 1; + u32 reserved1 : 3; + u32 sreg_pscbc_spare_ctrl_out : 4; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cnoc_pcie_sf_axi_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_cnoc_pcie_sf_axi_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CNOC_PCIE_SF_AXI_CFG_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cnoc_pcie_sf_axi_cfg_sregr_s +{ + u32 wakeup_timer : 8; + u32 sleep_timer : 8; + u32 mem_cph_timer : 6; + u32 mem_core_on_status : 1; + u32 mem_periph_on_status : 1; + u32 mem_core_on_ack_status : 1; + u32 mem_periph_on_ack_status : 1; + u32 mem_core_off_timer : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cnoc_pcie_sf_axi_cfg_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_cnoc_pcie_sf_axi_cfg_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CFG_NOC_NORTH_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cfg_noc_north_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cfg_noc_north_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_cfg_noc_north_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CFG_NOC_EAST_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cfg_noc_east_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cfg_noc_east_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_cfg_noc_east_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CFG_NOC_SOUTH_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cfg_noc_south_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cfg_noc_south_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_cfg_noc_south_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CFG_NOC_MMNOC_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cfg_noc_mmnoc_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cfg_noc_mmnoc_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_cfg_noc_mmnoc_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CNOC_QDSS_STM_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cnoc_qdss_stm_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cnoc_qdss_stm_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_cnoc_qdss_stm_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CFG_NOC_USB3_PRIM_AXI_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cfg_noc_usb3_prim_axi_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cfg_noc_usb3_prim_axi_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_cfg_noc_usb3_prim_axi_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CFG_NOC_LPASS_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cfg_noc_lpass_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cfg_noc_lpass_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_cfg_noc_lpass_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_NOC_WEST_DCD_XO_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_noc_west_dcd_xo_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_noc_west_dcd_xo_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_noc_west_dcd_xo_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_NOC_EAST_DCD_XO_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_noc_east_dcd_xo_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_noc_east_dcd_xo_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_noc_east_dcd_xo_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_NOC_NORTH_DCD_XO_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_noc_north_dcd_xo_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_noc_north_dcd_xo_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_noc_north_dcd_xo_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_NOC_PCIE_NORTH_DCD_XO_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_noc_pcie_north_dcd_xo_cbcr_s +{ + u32 reserved0 : 2; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_noc_pcie_north_dcd_xo_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_noc_pcie_north_dcd_xo_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_NOC_SOUTH_DCD_XO_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_noc_south_dcd_xo_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_noc_south_dcd_xo_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_noc_south_dcd_xo_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_NOC_CENTER_DCD_XO_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_noc_center_dcd_xo_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_noc_center_dcd_xo_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_noc_center_dcd_xo_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CFG_NOC_AH2PHY_XO_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cfg_noc_ah2phy_xo_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cfg_noc_ah2phy_xo_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_cfg_noc_ah2phy_xo_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_NOC_LPASS_DCD_XO_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_noc_lpass_dcd_xo_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_noc_lpass_dcd_xo_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_noc_lpass_dcd_xo_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_NOC_MMNOC_CNOC_DCD_XO_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_noc_mmnoc_cnoc_dcd_xo_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_noc_mmnoc_cnoc_dcd_xo_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_noc_mmnoc_cnoc_dcd_xo_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CNOC_PERIPH_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cnoc_periph_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cnoc_periph_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_cnoc_periph_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CONFIG_NOC_AT_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_config_noc_at_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_config_noc_at_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_config_noc_at_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CMD_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cmd_dfsr_s +{ + u32 dfs_en : 1; + u32 curr_perf_state : 4; + u32 hw_clk_control : 1; + u32 dfs_fsm_state : 3; + u32 perf_state_update_status : 1; + u32 sw_override : 1; + u32 sw_perf_state : 4; + u32 rcg_sw_ctrl : 6; + u32 reserved0 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cmd_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cmd_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_north_qx_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_north_qx_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_north_qx_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_north_qx_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_north_qx_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_north_qx_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_north_qx_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_north_qx_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_north_qx_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_north_qx_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_north_qx_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_north_qx_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_north_qx_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_north_qx_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_north_qx_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_north_qx_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_north_qx_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_north_qx_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_north_qx_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_north_qx_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_north_qx_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_north_qx_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_north_qx_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_north_qx_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF8_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_north_qx_perf8_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_north_qx_perf8_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_north_qx_perf8_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF9_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_north_qx_perf9_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_north_qx_perf9_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_north_qx_perf9_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF10_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_north_qx_perf10_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_north_qx_perf10_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_north_qx_perf10_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF11_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_north_qx_perf11_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_north_qx_perf11_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_north_qx_perf11_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF12_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_north_qx_perf12_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_north_qx_perf12_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_north_qx_perf12_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF13_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_north_qx_perf13_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_north_qx_perf13_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_north_qx_perf13_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF14_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_north_qx_perf14_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_north_qx_perf14_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_north_qx_perf14_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CNOC_NORTH_QX_PERF15_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_north_qx_perf15_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_north_qx_perf15_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_north_qx_perf15_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CNOC_NORTH_QX_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cnoc_north_qx_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cnoc_north_qx_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_cnoc_north_qx_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CNOC_NORTH_QX_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cnoc_north_qx_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cnoc_north_qx_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_cnoc_north_qx_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_center_qx_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_center_qx_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_center_qx_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_center_qx_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_center_qx_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_center_qx_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_center_qx_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_center_qx_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_center_qx_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_center_qx_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_center_qx_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_center_qx_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_center_qx_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_center_qx_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_center_qx_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_center_qx_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_center_qx_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_center_qx_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_center_qx_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_center_qx_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_center_qx_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_center_qx_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_center_qx_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_center_qx_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF8_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_center_qx_perf8_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_center_qx_perf8_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_center_qx_perf8_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF9_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_center_qx_perf9_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_center_qx_perf9_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_center_qx_perf9_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF10_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_center_qx_perf10_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_center_qx_perf10_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_center_qx_perf10_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF11_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_center_qx_perf11_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_center_qx_perf11_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_center_qx_perf11_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF12_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_center_qx_perf12_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_center_qx_perf12_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_center_qx_perf12_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF13_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_center_qx_perf13_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_center_qx_perf13_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_center_qx_perf13_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF14_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_center_qx_perf14_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_center_qx_perf14_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_center_qx_perf14_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CNOC_CENTER_QX_PERF15_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_center_qx_perf15_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_center_qx_perf15_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_center_qx_perf15_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CNOC_CENTER_QX_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cnoc_center_qx_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cnoc_center_qx_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_cnoc_center_qx_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CNOC_CENTER_QX_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cnoc_center_qx_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cnoc_center_qx_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_cnoc_center_qx_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_perf8_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_perf8_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_perf8_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_perf9_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_perf9_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_perf9_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_perf10_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_perf10_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_perf10_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_perf11_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_perf11_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_perf11_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_perf12_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_perf12_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_perf12_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_perf13_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_perf13_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_perf13_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_perf14_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_perf14_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_perf14_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_perf15_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_perf15_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_perf15_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CONFIG_NOC_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_config_noc_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_config_noc_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_config_noc_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CONFIG_NOC_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_config_noc_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_config_noc_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_config_noc_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_periph_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_periph_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_periph_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_periph_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_periph_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_periph_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_periph_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_periph_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_periph_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_periph_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_periph_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_periph_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_periph_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_periph_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_periph_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_periph_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_periph_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_periph_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_periph_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_periph_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_periph_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_periph_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_periph_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_periph_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_periph_perf8_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_periph_perf8_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_periph_perf8_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_periph_perf9_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_periph_perf9_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_periph_perf9_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_periph_perf10_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_periph_perf10_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_periph_perf10_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_periph_perf11_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_periph_perf11_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_periph_perf11_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_periph_perf12_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_periph_perf12_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_periph_perf12_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_periph_perf13_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_periph_perf13_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_periph_perf13_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_periph_perf14_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_periph_perf14_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_periph_perf14_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_periph_perf15_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_periph_perf15_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cnoc_periph_perf15_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CNOC_PERIPH_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cnoc_periph_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cnoc_periph_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_cnoc_periph_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CNOC_PERIPH_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cnoc_periph_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cnoc_periph_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_cnoc_periph_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_ddrss_sf_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_ddrss_sf_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_ddrss_sf_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_ddrss_sf_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_ddrss_sf_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_ddrss_sf_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_ddrss_sf_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_ddrss_sf_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_ddrss_sf_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_ddrss_sf_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_ddrss_sf_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_ddrss_sf_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_ddrss_sf_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_ddrss_sf_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_ddrss_sf_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_ddrss_sf_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_ddrss_sf_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_ddrss_sf_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_ddrss_sf_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_ddrss_sf_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_ddrss_sf_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_ddrss_sf_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_ddrss_sf_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_ddrss_sf_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF8_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_ddrss_sf_perf8_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_ddrss_sf_perf8_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_ddrss_sf_perf8_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF9_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_ddrss_sf_perf9_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_ddrss_sf_perf9_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_ddrss_sf_perf9_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF10_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_ddrss_sf_perf10_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_ddrss_sf_perf10_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_ddrss_sf_perf10_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF11_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_ddrss_sf_perf11_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_ddrss_sf_perf11_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_ddrss_sf_perf11_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF12_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_ddrss_sf_perf12_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_ddrss_sf_perf12_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_ddrss_sf_perf12_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF13_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_ddrss_sf_perf13_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_ddrss_sf_perf13_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_ddrss_sf_perf13_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF14_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_ddrss_sf_perf14_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_ddrss_sf_perf14_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_ddrss_sf_perf14_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CONFIG_NOC_DDRSS_SF_PERF15_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_ddrss_sf_perf15_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_ddrss_sf_perf15_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_config_noc_ddrss_sf_perf15_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CONFIG_NOC_DDRSS_SF_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_config_noc_ddrss_sf_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_config_noc_ddrss_sf_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_config_noc_ddrss_sf_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CONFIG_NOC_DDRSS_SF_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_config_noc_ddrss_sf_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_config_noc_ddrss_sf_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_config_noc_ddrss_sf_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cfg_noc_lpass_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cfg_noc_lpass_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cfg_noc_lpass_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cfg_noc_lpass_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cfg_noc_lpass_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cfg_noc_lpass_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cfg_noc_lpass_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cfg_noc_lpass_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cfg_noc_lpass_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cfg_noc_lpass_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cfg_noc_lpass_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cfg_noc_lpass_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cfg_noc_lpass_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cfg_noc_lpass_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cfg_noc_lpass_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cfg_noc_lpass_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cfg_noc_lpass_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cfg_noc_lpass_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cfg_noc_lpass_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cfg_noc_lpass_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cfg_noc_lpass_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cfg_noc_lpass_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cfg_noc_lpass_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cfg_noc_lpass_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cfg_noc_lpass_perf8_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cfg_noc_lpass_perf8_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cfg_noc_lpass_perf8_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cfg_noc_lpass_perf9_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cfg_noc_lpass_perf9_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cfg_noc_lpass_perf9_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cfg_noc_lpass_perf10_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cfg_noc_lpass_perf10_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cfg_noc_lpass_perf10_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cfg_noc_lpass_perf11_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cfg_noc_lpass_perf11_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cfg_noc_lpass_perf11_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cfg_noc_lpass_perf12_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cfg_noc_lpass_perf12_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cfg_noc_lpass_perf12_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cfg_noc_lpass_perf13_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cfg_noc_lpass_perf13_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cfg_noc_lpass_perf13_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cfg_noc_lpass_perf14_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cfg_noc_lpass_perf14_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cfg_noc_lpass_perf14_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cfg_noc_lpass_perf15_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_cfg_noc_lpass_perf15_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_cfg_noc_lpass_perf15_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CFG_NOC_LPASS_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cfg_noc_lpass_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cfg_noc_lpass_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_cfg_noc_lpass_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CFG_NOC_LPASS_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cfg_noc_lpass_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cfg_noc_lpass_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_cfg_noc_lpass_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CNOC_PERIPH_SOUTH_DCD_CDIV_DCDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cnoc_periph_south_dcd_cdiv_dcdr_s +{ + u32 dcd_enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cnoc_periph_south_dcd_cdiv_dcdr_u +{ + struct ipa_gcc_hwio_def_gcc_cnoc_periph_south_dcd_cdiv_dcdr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CNOC_PERIPH_NORTH_DCD_CDIV_DCDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cnoc_periph_north_dcd_cdiv_dcdr_s +{ + u32 dcd_enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cnoc_periph_north_dcd_cdiv_dcdr_u +{ + struct ipa_gcc_hwio_def_gcc_cnoc_periph_north_dcd_cdiv_dcdr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CNOC_PERIPH_DCD_CDIV_DCDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cnoc_periph_dcd_cdiv_dcdr_s +{ + u32 dcd_enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cnoc_periph_dcd_cdiv_dcdr_u +{ + struct ipa_gcc_hwio_def_gcc_cnoc_periph_dcd_cdiv_dcdr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CFG_NOC_LPASS_DCD_CDIV_DCDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cfg_noc_lpass_dcd_cdiv_dcdr_s +{ + u32 dcd_enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cfg_noc_lpass_dcd_cdiv_dcdr_u +{ + struct ipa_gcc_hwio_def_gcc_cfg_noc_lpass_dcd_cdiv_dcdr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CONFIG_NOC_DDRSS_SF_DCD_CDIV_DCDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_config_noc_ddrss_sf_dcd_cdiv_dcdr_s +{ + u32 dcd_enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_config_noc_ddrss_sf_dcd_cdiv_dcdr_u +{ + struct ipa_gcc_hwio_def_gcc_config_noc_ddrss_sf_dcd_cdiv_dcdr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CONFIG_NOC_CENTER_DCD_CDIV_DCDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_config_noc_center_dcd_cdiv_dcdr_s +{ + u32 dcd_enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_config_noc_center_dcd_cdiv_dcdr_u +{ + struct ipa_gcc_hwio_def_gcc_config_noc_center_dcd_cdiv_dcdr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CONFIG_NOC_WEST_DCD_CDIV_DCDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_config_noc_west_dcd_cdiv_dcdr_s +{ + u32 dcd_enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_config_noc_west_dcd_cdiv_dcdr_u +{ + struct ipa_gcc_hwio_def_gcc_config_noc_west_dcd_cdiv_dcdr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CONFIG_NOC_NORTH_DCD_CDIV_DCDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_config_noc_north_dcd_cdiv_dcdr_s +{ + u32 dcd_enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_config_noc_north_dcd_cdiv_dcdr_u +{ + struct ipa_gcc_hwio_def_gcc_config_noc_north_dcd_cdiv_dcdr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CONFIG_NOC_EAST_DCD_CDIV_DCDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_config_noc_east_dcd_cdiv_dcdr_s +{ + u32 dcd_enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_config_noc_east_dcd_cdiv_dcdr_u +{ + struct ipa_gcc_hwio_def_gcc_config_noc_east_dcd_cdiv_dcdr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CONFIG_NOC_SOUTH_DCD_CDIV_DCDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_config_noc_south_dcd_cdiv_dcdr_s +{ + u32 dcd_enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_config_noc_south_dcd_cdiv_dcdr_u +{ + struct ipa_gcc_hwio_def_gcc_config_noc_south_dcd_cdiv_dcdr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CONFIG_NOC_MMNOC_DCD_CDIV_DCDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_config_noc_mmnoc_dcd_cdiv_dcdr_s +{ + u32 dcd_enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_config_noc_mmnoc_dcd_cdiv_dcdr_u +{ + struct ipa_gcc_hwio_def_gcc_config_noc_mmnoc_dcd_cdiv_dcdr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CNOC_CENTER_QX_DCD_CDIV_DCDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cnoc_center_qx_dcd_cdiv_dcdr_s +{ + u32 dcd_enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cnoc_center_qx_dcd_cdiv_dcdr_u +{ + struct ipa_gcc_hwio_def_gcc_cnoc_center_qx_dcd_cdiv_dcdr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CNOC_NORTH_QX_DCD_CDIV_DCDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cnoc_north_qx_dcd_cdiv_dcdr_s +{ + u32 dcd_enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cnoc_north_qx_dcd_cdiv_dcdr_u +{ + struct ipa_gcc_hwio_def_gcc_cnoc_north_qx_dcd_cdiv_dcdr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AGGRE_NOC_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_aggre_noc_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_aggre_noc_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_aggre_noc_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CFG_NOC_PCIE_ANOC_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cfg_noc_pcie_anoc_ahb_cbcr_s +{ + u32 reserved0 : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved1 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cfg_noc_pcie_anoc_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_cfg_noc_pcie_anoc_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_aggre_noc_south_ahb_cfg_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_aggre_noc_south_ahb_cfg_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_aggre_noc_south_ahb_cfg_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AGGRE_NOC_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_aggre_noc_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_aggre_noc_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_aggre_noc_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QMIP_AGGRE_NOC_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qmip_aggre_noc_ahb_cbcr_s +{ + u32 reserved0 : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved1 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qmip_aggre_noc_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qmip_aggre_noc_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AGGRE_CNOC_PERIPH_NORTH_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_aggre_cnoc_periph_north_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_aggre_cnoc_periph_north_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_aggre_cnoc_periph_north_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AGGRE_CNOC_PERIPH_SOUTH_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_aggre_cnoc_periph_south_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_aggre_cnoc_periph_south_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_aggre_cnoc_periph_south_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AGGRE_NOC_QOSGEN_EXTREF_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_aggre_noc_qosgen_extref_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_aggre_noc_qosgen_extref_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_aggre_noc_qosgen_extref_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AGGRE_NOC_CENTER_AXI_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_aggre_noc_center_axi_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 8; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved1 : 5; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_aggre_noc_center_axi_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_aggre_noc_center_axi_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AGGRE_NOC_CENTER_AXI_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_aggre_noc_center_axi_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 4; + u32 pwr_fsm_clk_sel : 1; + u32 reserved1 : 3; + u32 sreg_pscbc_spare_ctrl_out : 4; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_aggre_noc_center_axi_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_aggre_noc_center_axi_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AGGRE_NOC_CENTER_AXI_CFG_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_aggre_noc_center_axi_cfg_sregr_s +{ + u32 wakeup_timer : 8; + u32 sleep_timer : 8; + u32 mem_cph_timer : 6; + u32 mem_core_on_status : 1; + u32 mem_periph_on_status : 1; + u32 mem_core_on_ack_status : 1; + u32 mem_periph_on_ack_status : 1; + u32 mem_core_off_timer : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_aggre_noc_center_axi_cfg_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_aggre_noc_center_axi_cfg_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AGGRE_NOC_QDSS_BAM_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_aggre_noc_qdss_bam_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 8; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved1 : 5; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_aggre_noc_qdss_bam_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_aggre_noc_qdss_bam_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AGGRE_NOC_QDSS_BAM_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_aggre_noc_qdss_bam_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 4; + u32 pwr_fsm_clk_sel : 1; + u32 reserved1 : 3; + u32 sreg_pscbc_spare_ctrl_out : 4; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_aggre_noc_qdss_bam_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_aggre_noc_qdss_bam_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AGGRE_NOC_QDSS_BAM_CFG_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_aggre_noc_qdss_bam_cfg_sregr_s +{ + u32 wakeup_timer : 8; + u32 sleep_timer : 8; + u32 mem_cph_timer : 6; + u32 mem_core_on_status : 1; + u32 mem_periph_on_status : 1; + u32 mem_core_on_ack_status : 1; + u32 mem_periph_on_ack_status : 1; + u32 mem_core_off_timer : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_aggre_noc_qdss_bam_cfg_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_aggre_noc_qdss_bam_cfg_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AGGRE_NOC_CENTER_HS_AXI_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_aggre_noc_center_hs_axi_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 8; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved1 : 5; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_aggre_noc_center_hs_axi_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_aggre_noc_center_hs_axi_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AGGRE_NOC_CENTER_HS_AXI_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_aggre_noc_center_hs_axi_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 4; + u32 pwr_fsm_clk_sel : 1; + u32 reserved1 : 3; + u32 sreg_pscbc_spare_ctrl_out : 4; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_aggre_noc_center_hs_axi_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_aggre_noc_center_hs_axi_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AGGRE_NOC_CENTER_HS_AXI_CFG_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_aggre_noc_center_hs_axi_cfg_sregr_s +{ + u32 wakeup_timer : 8; + u32 sleep_timer : 8; + u32 mem_cph_timer : 6; + u32 mem_core_on_status : 1; + u32 mem_periph_on_status : 1; + u32 mem_core_on_ack_status : 1; + u32 mem_periph_on_ack_status : 1; + u32 mem_core_off_timer : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_aggre_noc_center_hs_axi_cfg_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_aggre_noc_center_hs_axi_cfg_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AGGRE_NOC_WEST_AXI_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_aggre_noc_west_axi_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_aggre_noc_west_axi_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_aggre_noc_west_axi_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AGGRE_NOC_WEST_TUNNEL_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_aggre_noc_west_tunnel_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_aggre_noc_west_tunnel_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_aggre_noc_west_tunnel_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AGGRE_NOC_EAST_AXI_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_aggre_noc_east_axi_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_aggre_noc_east_axi_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_aggre_noc_east_axi_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AGGRE_NOC_EAST_TUNNEL_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_aggre_noc_east_tunnel_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_aggre_noc_east_tunnel_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_aggre_noc_east_tunnel_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AGGRE_NOC_SOUTH_HS_AXI_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_aggre_noc_south_hs_axi_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_aggre_noc_south_hs_axi_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_aggre_noc_south_hs_axi_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AGGRE_NOC_SOUTH_AXI_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_aggre_noc_south_axi_cbcr_s +{ + u32 reserved0 : 2; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_aggre_noc_south_axi_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_aggre_noc_south_axi_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AGGRE_NOC_SOUTH_TUNNEL_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_aggre_noc_south_tunnel_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_aggre_noc_south_tunnel_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_aggre_noc_south_tunnel_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AGGRE_NOC_NORTH_AXI_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_aggre_noc_north_axi_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_aggre_noc_north_axi_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_aggre_noc_north_axi_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AGGRE_NOC_NORTH_TUNNEL_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_aggre_noc_north_tunnel_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_aggre_noc_north_tunnel_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_aggre_noc_north_tunnel_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AGGRE_NOC_PCIE_AXI_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_aggre_noc_pcie_axi_cbcr_s +{ + u32 reserved0 : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved1 : 8; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved2 : 5; + u32 ignore_rpmh_clk_dis : 1; + u32 ignore_pmu_clk_dis : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_aggre_noc_pcie_axi_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_aggre_noc_pcie_axi_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AGGRE_NOC_PCIE_AXI_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_aggre_noc_pcie_axi_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 4; + u32 pwr_fsm_clk_sel : 1; + u32 reserved1 : 3; + u32 sreg_pscbc_spare_ctrl_out : 4; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_aggre_noc_pcie_axi_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_aggre_noc_pcie_axi_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AGGRE_NOC_PCIE_AXI_CFG_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_aggre_noc_pcie_axi_cfg_sregr_s +{ + u32 wakeup_timer : 8; + u32 sleep_timer : 8; + u32 mem_cph_timer : 6; + u32 mem_core_on_status : 1; + u32 mem_periph_on_status : 1; + u32 mem_core_on_ack_status : 1; + u32 mem_periph_on_ack_status : 1; + u32 mem_core_off_timer : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_aggre_noc_pcie_axi_cfg_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_aggre_noc_pcie_axi_cfg_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AGGRE_USB3_PRIM_AXI_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_aggre_usb3_prim_axi_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_aggre_usb3_prim_axi_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_aggre_usb3_prim_axi_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AGGRE_UFS_PHY_AXI_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_aggre_ufs_phy_axi_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_aggre_ufs_phy_axi_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_aggre_ufs_phy_axi_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AGGRE_NOC_IPA_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_aggre_noc_ipa_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_aggre_noc_ipa_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_aggre_noc_ipa_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ANOC_PCIE_PWRCTL_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_anoc_pcie_pwrctl_cbcr_s +{ + u32 reserved0 : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved1 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_anoc_pcie_pwrctl_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_anoc_pcie_pwrctl_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_perf8_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_perf8_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_perf8_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_perf9_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_perf9_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_perf9_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_perf10_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_perf10_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_perf10_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_perf11_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_perf11_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_perf11_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_perf12_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_perf12_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_perf12_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_perf13_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_perf13_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_perf13_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_perf14_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_perf14_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_perf14_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_perf15_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_perf15_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_perf15_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AGGRE_NOC_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_aggre_noc_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_aggre_noc_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_aggre_noc_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AGGRE_NOC_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_aggre_noc_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_aggre_noc_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_aggre_noc_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_north_sf_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_north_sf_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_north_sf_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_north_sf_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_north_sf_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_north_sf_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_north_sf_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_north_sf_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_north_sf_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_north_sf_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_north_sf_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_north_sf_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_north_sf_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_north_sf_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_north_sf_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_north_sf_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_north_sf_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_north_sf_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_north_sf_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_north_sf_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_north_sf_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_north_sf_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_north_sf_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_north_sf_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_north_sf_perf8_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_north_sf_perf8_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_north_sf_perf8_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_north_sf_perf9_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_north_sf_perf9_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_north_sf_perf9_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_north_sf_perf10_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_north_sf_perf10_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_north_sf_perf10_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_north_sf_perf11_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_north_sf_perf11_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_north_sf_perf11_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_north_sf_perf12_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_north_sf_perf12_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_north_sf_perf12_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_north_sf_perf13_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_north_sf_perf13_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_north_sf_perf13_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_north_sf_perf14_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_north_sf_perf14_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_north_sf_perf14_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_north_sf_perf15_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_north_sf_perf15_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_aggre_noc_north_sf_perf15_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AGGRE_NOC_NORTH_SF_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_aggre_noc_north_sf_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_aggre_noc_north_sf_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_aggre_noc_north_sf_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_aggre_noc_north_sf_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_aggre_noc_north_sf_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_aggre_noc_north_sf_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AGGRE_NOC_DCD_CDIV_DCDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_aggre_noc_dcd_cdiv_dcdr_s +{ + u32 dcd_enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_aggre_noc_dcd_cdiv_dcdr_u +{ + struct ipa_gcc_hwio_def_gcc_aggre_noc_dcd_cdiv_dcdr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AGGRE_NOC_WEST_DCD_CDIV_DCDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_aggre_noc_west_dcd_cdiv_dcdr_s +{ + u32 dcd_enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_aggre_noc_west_dcd_cdiv_dcdr_u +{ + struct ipa_gcc_hwio_def_gcc_aggre_noc_west_dcd_cdiv_dcdr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AGGRE_NOC_EAST_DCD_CDIV_DCDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_aggre_noc_east_dcd_cdiv_dcdr_s +{ + u32 dcd_enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_aggre_noc_east_dcd_cdiv_dcdr_u +{ + struct ipa_gcc_hwio_def_gcc_aggre_noc_east_dcd_cdiv_dcdr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AGGRE_NOC_NORTH_DCD_CDIV_DCDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_aggre_noc_north_dcd_cdiv_dcdr_s +{ + u32 dcd_enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_aggre_noc_north_dcd_cdiv_dcdr_u +{ + struct ipa_gcc_hwio_def_gcc_aggre_noc_north_dcd_cdiv_dcdr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AGGRE_NOC_SOUTH_HS_DCD_CDIV_DCDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_aggre_noc_south_hs_dcd_cdiv_dcdr_s +{ + u32 dcd_enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_aggre_noc_south_hs_dcd_cdiv_dcdr_u +{ + struct ipa_gcc_hwio_def_gcc_aggre_noc_south_hs_dcd_cdiv_dcdr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AGGRE_NOC_SOUTH_DCD_CDIV_DCDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_aggre_noc_south_dcd_cdiv_dcdr_s +{ + u32 dcd_enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_aggre_noc_south_dcd_cdiv_dcdr_u +{ + struct ipa_gcc_hwio_def_gcc_aggre_noc_south_dcd_cdiv_dcdr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AGGRE_NOC_WEST_TUNNEL_DCD_CDIV_DCDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_aggre_noc_west_tunnel_dcd_cdiv_dcdr_s +{ + u32 dcd_enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_aggre_noc_west_tunnel_dcd_cdiv_dcdr_u +{ + struct ipa_gcc_hwio_def_gcc_aggre_noc_west_tunnel_dcd_cdiv_dcdr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AGGRE_NOC_EAST_TUNNEL_DCD_CDIV_DCDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_aggre_noc_east_tunnel_dcd_cdiv_dcdr_s +{ + u32 dcd_enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_aggre_noc_east_tunnel_dcd_cdiv_dcdr_u +{ + struct ipa_gcc_hwio_def_gcc_aggre_noc_east_tunnel_dcd_cdiv_dcdr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AGGRE_NOC_NORTH_TUNNEL_DCD_CDIV_DCDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_aggre_noc_north_tunnel_dcd_cdiv_dcdr_s +{ + u32 dcd_enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_aggre_noc_north_tunnel_dcd_cdiv_dcdr_u +{ + struct ipa_gcc_hwio_def_gcc_aggre_noc_north_tunnel_dcd_cdiv_dcdr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AGGRE_NOC_SOUTH_TUNNEL_DCD_CDIV_DCDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_aggre_noc_south_tunnel_dcd_cdiv_dcdr_s +{ + u32 dcd_enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_aggre_noc_south_tunnel_dcd_cdiv_dcdr_u +{ + struct ipa_gcc_hwio_def_gcc_aggre_noc_south_tunnel_dcd_cdiv_dcdr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AGGRE_NOC_NORTH_SF_DCD_CDIV_DCDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_aggre_noc_north_sf_dcd_cdiv_dcdr_s +{ + u32 dcd_enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_aggre_noc_north_sf_dcd_cdiv_dcdr_u +{ + struct ipa_gcc_hwio_def_gcc_aggre_noc_north_sf_dcd_cdiv_dcdr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TIC_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tic_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tic_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_tic_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TIC_CFG_QX_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tic_cfg_qx_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 8; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved1 : 5; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tic_cfg_qx_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_tic_cfg_qx_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TIC_CFG_QX_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tic_cfg_qx_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 4; + u32 pwr_fsm_clk_sel : 1; + u32 reserved1 : 3; + u32 sreg_pscbc_spare_ctrl_out : 4; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tic_cfg_qx_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_tic_cfg_qx_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TIC_CFG_QX_CFG_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tic_cfg_qx_cfg_sregr_s +{ + u32 wakeup_timer : 8; + u32 sleep_timer : 8; + u32 mem_cph_timer : 6; + u32 mem_core_on_status : 1; + u32 mem_periph_on_status : 1; + u32 mem_core_on_ack_status : 1; + u32 mem_periph_on_ack_status : 1; + u32 mem_core_off_timer : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tic_cfg_qx_cfg_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_tic_cfg_qx_cfg_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_IMEM_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_imem_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_imem_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_imem_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_IMEM_CFG_QX_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_imem_cfg_qx_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 9; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved2 : 5; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved3 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved4 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_imem_cfg_qx_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_imem_cfg_qx_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_IMEM_CFG_QX_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_imem_cfg_qx_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 4; + u32 pwr_fsm_clk_sel : 1; + u32 reserved1 : 3; + u32 sreg_pscbc_spare_ctrl_out : 4; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_imem_cfg_qx_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_imem_cfg_qx_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_IMEM_CFG_QX_CFG_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_imem_cfg_qx_cfg_sregr_s +{ + u32 wakeup_timer : 8; + u32 sleep_timer : 8; + u32 mem_cph_timer : 6; + u32 mem_core_on_status : 1; + u32 mem_periph_on_status : 1; + u32 mem_core_on_ack_status : 1; + u32 mem_periph_on_ack_status : 1; + u32 mem_core_off_timer : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_imem_cfg_qx_cfg_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_imem_cfg_qx_cfg_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_IMEM_CFG_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_imem_cfg_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_imem_cfg_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_imem_cfg_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MMU_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mmu_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mmu_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_mmu_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MMU_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mmu_gdscr_s +{ + u32 sw_collapse : 1; + u32 hw_control : 1; + u32 sw_override : 1; + u32 pd_ares : 1; + u32 clk_disable : 1; + u32 clamp_io : 1; + u32 en_few : 1; + u32 en_rest : 1; + u32 retain : 1; + u32 save : 1; + u32 restore : 1; + u32 retain_ff_enable : 1; + u32 clk_dis_wait : 4; + u32 en_few_wait : 4; + u32 en_rest_wait : 4; + u32 reserved0 : 3; + u32 gdsc_state : 4; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mmu_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_mmu_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MMU_CFG_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mmu_cfg_gdscr_s +{ + u32 disable_clk_software_override : 1; + u32 clamp_io_software_override : 1; + u32 save_restore_software_override : 1; + u32 unclamp_io_software_override : 1; + u32 gdsc_pscbc_pwr_dwn_sw : 1; + u32 gdsc_phase_reset_delay_count_sw : 2; + u32 gdsc_phase_reset_en_sw : 1; + u32 gdsc_mem_core_force_in_sw : 1; + u32 gdsc_mem_peri_force_in_sw : 1; + u32 gdsc_handshake_dis : 1; + u32 software_control_override : 4; + u32 gdsc_power_down_complete : 1; + u32 gdsc_power_up_complete : 1; + u32 gdsc_enf_ack_status : 1; + u32 gdsc_enr_ack_status : 1; + u32 gdsc_mem_pwr_ack_status : 1; + u32 gdsc_cfg_fsm_state_status : 4; + u32 gdsc_pwr_up_start : 1; + u32 gdsc_pwr_dwn_start : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 5; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mmu_cfg_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_mmu_cfg_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MMU_CFG2_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mmu_cfg2_gdscr_s +{ + u32 mem_pwr_dwn_timeout : 4; + u32 dly_assert_clamp_mem : 4; + u32 dly_deassert_clamp_mem : 4; + u32 dly_mem_pwr_up : 4; + u32 gdsc_clamp_mem_sw : 1; + u32 gdsc_pwrdwn_enable_ack_override : 1; + u32 gdsc_mem_pwrup_ack_override : 1; + u32 reserved0 : 13; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mmu_cfg2_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_mmu_cfg2_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MMU_CFG3_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mmu_cfg3_gdscr_s +{ + u32 gdsc_spare_ctrl_out : 8; + u32 gdsc_spare_ctrl_in : 8; + u32 gdsc_accu_red_sw_override : 1; + u32 gdsc_accu_red_shifter_start_sw : 1; + u32 gdsc_accu_red_shifter_clk_en_sw : 1; + u32 gdsc_accu_red_shifter_done_override : 1; + u32 gdsc_accu_red_timer_en_sw : 1; + u32 dly_accu_red_shifter_done : 4; + u32 gdsc_accu_red_enable : 1; + u32 gdsc_accu_red_shifter_done_status : 1; + u32 reserved0 : 5; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mmu_cfg3_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_mmu_cfg3_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MMU_CFG4_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mmu_cfg4_gdscr_s +{ + u32 dly_retainff : 4; + u32 dly_clampio : 4; + u32 dly_deassertares : 4; + u32 dly_noretainff : 4; + u32 dly_restoreff : 4; + u32 dly_unclampio : 4; + u32 reserved0 : 8; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mmu_cfg4_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_mmu_cfg4_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TCU_CFG_QX_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tcu_cfg_qx_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tcu_cfg_qx_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_tcu_cfg_qx_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MMU_TCU_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mmu_tcu_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 8; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved1 : 5; + u32 ignore_rpmh_clk_dis : 1; + u32 ignore_pmu_clk_dis : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mmu_tcu_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_mmu_tcu_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MMU_TCU_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mmu_tcu_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 4; + u32 pwr_fsm_clk_sel : 1; + u32 reserved1 : 3; + u32 sreg_pscbc_spare_ctrl_out : 4; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mmu_tcu_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_mmu_tcu_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MMU_TCU_CFG_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mmu_tcu_cfg_sregr_s +{ + u32 wakeup_timer : 8; + u32 sleep_timer : 8; + u32 mem_cph_timer : 6; + u32 mem_core_on_status : 1; + u32 mem_periph_on_status : 1; + u32 mem_core_on_ack_status : 1; + u32 mem_periph_on_ack_status : 1; + u32 mem_core_off_timer : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mmu_tcu_cfg_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_mmu_tcu_cfg_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_CMD_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_cmd_dfsr_s +{ + u32 dfs_en : 1; + u32 curr_perf_state : 4; + u32 hw_clk_control : 1; + u32 dfs_fsm_state : 3; + u32 perf_state_update_status : 1; + u32 sw_override : 1; + u32 sw_perf_state : 4; + u32 rcg_sw_ctrl : 11; + u32 reserved0 : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_cmd_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_cmd_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf8_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf8_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf8_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf9_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf9_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf9_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf10_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf10_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf10_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf11_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf11_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf11_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf12_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf12_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf12_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf13_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf13_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf13_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf14_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf14_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf14_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf15_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf15_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mmu_tcu_perf15_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MMU_TCU_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mmu_tcu_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mmu_tcu_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_mmu_tcu_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MMU_TCU_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mmu_tcu_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mmu_tcu_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_mmu_tcu_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MMU_TCU_DCD_CDIV_DCDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mmu_tcu_dcd_cdiv_dcdr_s +{ + u32 dcd_enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mmu_tcu_dcd_cdiv_dcdr_u +{ + struct ipa_gcc_hwio_def_gcc_mmu_tcu_dcd_cdiv_dcdr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TCU_ANOC_QTB1_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tcu_anoc_qtb1_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tcu_anoc_qtb1_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_tcu_anoc_qtb1_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TCU_ANOC_QTB2_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tcu_anoc_qtb2_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tcu_anoc_qtb2_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_tcu_anoc_qtb2_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TCU_MMNOC_QTB_SF_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tcu_mmnoc_qtb_sf_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tcu_mmnoc_qtb_sf_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_tcu_mmnoc_qtb_sf_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TCU_MMNOC_QTB_HF01_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tcu_mmnoc_qtb_hf01_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tcu_mmnoc_qtb_hf01_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_tcu_mmnoc_qtb_hf01_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TCU_MMNOC_QTB_HF23_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tcu_mmnoc_qtb_hf23_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tcu_mmnoc_qtb_hf23_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_tcu_mmnoc_qtb_hf23_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_MMNOC_CMD_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_cmd_dfsr_s +{ + u32 dfs_en : 1; + u32 curr_perf_state : 4; + u32 hw_clk_control : 1; + u32 dfs_fsm_state : 3; + u32 perf_state_update_status : 1; + u32 sw_override : 1; + u32 sw_perf_state : 4; + u32 rcg_sw_ctrl : 2; + u32 reserved0 : 15; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_mmnoc_cmd_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_cmd_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_hf_qx_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_hf_qx_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_hf_qx_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_hf_qx_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_hf_qx_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_hf_qx_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_hf_qx_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_hf_qx_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_hf_qx_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_hf_qx_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_hf_qx_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_hf_qx_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_hf_qx_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_hf_qx_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_hf_qx_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_hf_qx_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_hf_qx_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_hf_qx_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_hf_qx_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_hf_qx_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_hf_qx_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_hf_qx_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_hf_qx_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_hf_qx_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_hf_qx_perf8_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_hf_qx_perf8_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_hf_qx_perf8_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_hf_qx_perf9_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_hf_qx_perf9_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_hf_qx_perf9_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_hf_qx_perf10_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_hf_qx_perf10_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_hf_qx_perf10_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_hf_qx_perf11_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_hf_qx_perf11_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_hf_qx_perf11_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_hf_qx_perf12_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_hf_qx_perf12_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_hf_qx_perf12_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_hf_qx_perf13_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_hf_qx_perf13_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_hf_qx_perf13_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_hf_qx_perf14_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_hf_qx_perf14_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_hf_qx_perf14_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_hf_qx_perf15_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_hf_qx_perf15_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_hf_qx_perf15_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MMNOC_HF_QX_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mmnoc_hf_qx_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mmnoc_hf_qx_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_mmnoc_hf_qx_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MMNOC_HF_QX_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mmnoc_hf_qx_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mmnoc_hf_qx_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_mmnoc_hf_qx_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MMNOC_HF_QX_DCD_CDIV_DCDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mmnoc_hf_qx_dcd_cdiv_dcdr_s +{ + u32 dcd_enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mmnoc_hf_qx_dcd_cdiv_dcdr_u +{ + struct ipa_gcc_hwio_def_gcc_mmnoc_hf_qx_dcd_cdiv_dcdr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_sf_qx_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_sf_qx_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_sf_qx_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_sf_qx_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_sf_qx_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_sf_qx_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_sf_qx_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_sf_qx_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_sf_qx_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_sf_qx_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_sf_qx_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_sf_qx_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_sf_qx_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_sf_qx_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_sf_qx_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_sf_qx_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_sf_qx_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_sf_qx_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_sf_qx_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_sf_qx_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_sf_qx_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_sf_qx_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_sf_qx_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_sf_qx_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_sf_qx_perf8_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_sf_qx_perf8_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_sf_qx_perf8_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_sf_qx_perf9_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_sf_qx_perf9_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_sf_qx_perf9_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_sf_qx_perf10_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_sf_qx_perf10_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_sf_qx_perf10_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_sf_qx_perf11_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_sf_qx_perf11_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_sf_qx_perf11_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_sf_qx_perf12_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_sf_qx_perf12_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_sf_qx_perf12_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_sf_qx_perf13_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_sf_qx_perf13_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_sf_qx_perf13_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_sf_qx_perf14_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_sf_qx_perf14_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_sf_qx_perf14_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_sf_qx_perf15_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_sf_qx_perf15_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_mmnoc_sf_qx_perf15_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MMNOC_SF_QX_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mmnoc_sf_qx_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mmnoc_sf_qx_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_mmnoc_sf_qx_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MMNOC_SF_QX_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mmnoc_sf_qx_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mmnoc_sf_qx_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_mmnoc_sf_qx_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MMNOC_SF_QX_DCD_CDIV_DCDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mmnoc_sf_qx_dcd_cdiv_dcdr_s +{ + u32 dcd_enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mmnoc_sf_qx_dcd_cdiv_dcdr_u +{ + struct ipa_gcc_hwio_def_gcc_mmnoc_sf_qx_dcd_cdiv_dcdr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TCU_ANOC_PCIE_QTB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tcu_anoc_pcie_qtb_cbcr_s +{ + u32 reserved0 : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved1 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tcu_anoc_pcie_qtb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_tcu_anoc_pcie_qtb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TCU_TURING_Q6_QTB0_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tcu_turing_q6_qtb0_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tcu_turing_q6_qtb0_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_tcu_turing_q6_qtb0_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TCU_LPASS_AUDIO_QTB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tcu_lpass_audio_qtb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tcu_lpass_audio_qtb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_tcu_lpass_audio_qtb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ANOC_PCIE_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_anoc_pcie_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_anoc_pcie_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_anoc_pcie_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ANOC_PCIE_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_anoc_pcie_gdscr_s +{ + u32 sw_collapse : 1; + u32 hw_control : 1; + u32 sw_override : 1; + u32 pd_ares : 1; + u32 clk_disable : 1; + u32 clamp_io : 1; + u32 en_few : 1; + u32 en_rest : 1; + u32 retain : 1; + u32 save : 1; + u32 restore : 1; + u32 retain_ff_enable : 1; + u32 clk_dis_wait : 4; + u32 en_few_wait : 4; + u32 en_rest_wait : 4; + u32 reserved0 : 3; + u32 gdsc_state : 4; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_anoc_pcie_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_anoc_pcie_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ANOC_PCIE_CFG_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_anoc_pcie_cfg_gdscr_s +{ + u32 disable_clk_software_override : 1; + u32 clamp_io_software_override : 1; + u32 save_restore_software_override : 1; + u32 unclamp_io_software_override : 1; + u32 gdsc_pscbc_pwr_dwn_sw : 1; + u32 gdsc_phase_reset_delay_count_sw : 2; + u32 gdsc_phase_reset_en_sw : 1; + u32 gdsc_mem_core_force_in_sw : 1; + u32 gdsc_mem_peri_force_in_sw : 1; + u32 gdsc_handshake_dis : 1; + u32 software_control_override : 4; + u32 gdsc_power_down_complete : 1; + u32 gdsc_power_up_complete : 1; + u32 gdsc_enf_ack_status : 1; + u32 gdsc_enr_ack_status : 1; + u32 gdsc_mem_pwr_ack_status : 1; + u32 gdsc_cfg_fsm_state_status : 4; + u32 gdsc_pwr_up_start : 1; + u32 gdsc_pwr_dwn_start : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 5; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_anoc_pcie_cfg_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_anoc_pcie_cfg_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ANOC_PCIE_CFG2_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_anoc_pcie_cfg2_gdscr_s +{ + u32 mem_pwr_dwn_timeout : 4; + u32 dly_assert_clamp_mem : 4; + u32 dly_deassert_clamp_mem : 4; + u32 dly_mem_pwr_up : 4; + u32 gdsc_clamp_mem_sw : 1; + u32 gdsc_pwrdwn_enable_ack_override : 1; + u32 gdsc_mem_pwrup_ack_override : 1; + u32 reserved0 : 13; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_anoc_pcie_cfg2_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_anoc_pcie_cfg2_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ANOC_PCIE_CFG3_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_anoc_pcie_cfg3_gdscr_s +{ + u32 gdsc_spare_ctrl_out : 8; + u32 gdsc_spare_ctrl_in : 8; + u32 gdsc_accu_red_sw_override : 1; + u32 gdsc_accu_red_shifter_start_sw : 1; + u32 gdsc_accu_red_shifter_clk_en_sw : 1; + u32 gdsc_accu_red_shifter_done_override : 1; + u32 gdsc_accu_red_timer_en_sw : 1; + u32 dly_accu_red_shifter_done : 4; + u32 gdsc_accu_red_enable : 1; + u32 gdsc_accu_red_shifter_done_status : 1; + u32 reserved0 : 5; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_anoc_pcie_cfg3_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_anoc_pcie_cfg3_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ANOC_PCIE_CFG4_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_anoc_pcie_cfg4_gdscr_s +{ + u32 dly_retainff : 4; + u32 dly_clampio : 4; + u32 dly_deassertares : 4; + u32 dly_noretainff : 4; + u32 dly_restoreff : 4; + u32 dly_unclampio : 4; + u32 reserved0 : 8; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_anoc_pcie_cfg4_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_anoc_pcie_cfg4_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ANOC_PCIE_NORTH_AT_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_anoc_pcie_north_at_cbcr_s +{ + u32 reserved0 : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved1 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_anoc_pcie_north_at_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_anoc_pcie_north_at_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ANOC_PCIE_TSCTR_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_anoc_pcie_tsctr_cbcr_s +{ + u32 reserved0 : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved1 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_anoc_pcie_tsctr_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_anoc_pcie_tsctr_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ANOC_PCIE_QOSGEN_EXTREF_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_anoc_pcie_qosgen_extref_cbcr_s +{ + u32 reserved0 : 2; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_anoc_pcie_qosgen_extref_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_anoc_pcie_qosgen_extref_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MMNOC_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mmnoc_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mmnoc_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_mmnoc_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MMNOC_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mmnoc_gdscr_s +{ + u32 sw_collapse : 1; + u32 hw_control : 1; + u32 sw_override : 1; + u32 pd_ares : 1; + u32 clk_disable : 1; + u32 clamp_io : 1; + u32 en_few : 1; + u32 en_rest : 1; + u32 retain : 1; + u32 save : 1; + u32 restore : 1; + u32 retain_ff_enable : 1; + u32 clk_dis_wait : 4; + u32 en_few_wait : 4; + u32 en_rest_wait : 4; + u32 reserved0 : 3; + u32 gdsc_state : 4; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mmnoc_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_mmnoc_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MMNOC_CFG_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mmnoc_cfg_gdscr_s +{ + u32 disable_clk_software_override : 1; + u32 clamp_io_software_override : 1; + u32 save_restore_software_override : 1; + u32 unclamp_io_software_override : 1; + u32 gdsc_pscbc_pwr_dwn_sw : 1; + u32 gdsc_phase_reset_delay_count_sw : 2; + u32 gdsc_phase_reset_en_sw : 1; + u32 gdsc_mem_core_force_in_sw : 1; + u32 gdsc_mem_peri_force_in_sw : 1; + u32 gdsc_handshake_dis : 1; + u32 software_control_override : 4; + u32 gdsc_power_down_complete : 1; + u32 gdsc_power_up_complete : 1; + u32 gdsc_enf_ack_status : 1; + u32 gdsc_enr_ack_status : 1; + u32 gdsc_mem_pwr_ack_status : 1; + u32 gdsc_cfg_fsm_state_status : 4; + u32 gdsc_pwr_up_start : 1; + u32 gdsc_pwr_dwn_start : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 5; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mmnoc_cfg_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_mmnoc_cfg_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MMNOC_CFG2_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mmnoc_cfg2_gdscr_s +{ + u32 mem_pwr_dwn_timeout : 4; + u32 dly_assert_clamp_mem : 4; + u32 dly_deassert_clamp_mem : 4; + u32 dly_mem_pwr_up : 4; + u32 gdsc_clamp_mem_sw : 1; + u32 gdsc_pwrdwn_enable_ack_override : 1; + u32 gdsc_mem_pwrup_ack_override : 1; + u32 reserved0 : 13; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mmnoc_cfg2_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_mmnoc_cfg2_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MMNOC_CFG3_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mmnoc_cfg3_gdscr_s +{ + u32 gdsc_spare_ctrl_out : 8; + u32 gdsc_spare_ctrl_in : 8; + u32 gdsc_accu_red_sw_override : 1; + u32 gdsc_accu_red_shifter_start_sw : 1; + u32 gdsc_accu_red_shifter_clk_en_sw : 1; + u32 gdsc_accu_red_shifter_done_override : 1; + u32 gdsc_accu_red_timer_en_sw : 1; + u32 dly_accu_red_shifter_done : 4; + u32 gdsc_accu_red_enable : 1; + u32 gdsc_accu_red_shifter_done_status : 1; + u32 reserved0 : 5; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mmnoc_cfg3_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_mmnoc_cfg3_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MMNOC_CFG4_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mmnoc_cfg4_gdscr_s +{ + u32 dly_retainff : 4; + u32 dly_clampio : 4; + u32 dly_deassertares : 4; + u32 dly_noretainff : 4; + u32 dly_restoreff : 4; + u32 dly_unclampio : 4; + u32 reserved0 : 8; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mmnoc_cfg4_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_mmnoc_cfg4_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MMNOC_AT_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mmnoc_at_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mmnoc_at_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_mmnoc_at_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MMNOC_AHB_CFG_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mmnoc_ahb_cfg_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mmnoc_ahb_cfg_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_mmnoc_ahb_cfg_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_NOC_MMNOC_DCD_XO_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_noc_mmnoc_dcd_xo_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_noc_mmnoc_dcd_xo_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_noc_mmnoc_dcd_xo_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MMNOC_TSCTR_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mmnoc_tsctr_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mmnoc_tsctr_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_mmnoc_tsctr_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MMNOC_SF_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mmnoc_sf_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 8; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved1 : 5; + u32 ignore_rpmh_clk_dis : 1; + u32 ignore_pmu_clk_dis : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mmnoc_sf_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_mmnoc_sf_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MMNOC_SF_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mmnoc_sf_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 4; + u32 pwr_fsm_clk_sel : 1; + u32 reserved1 : 3; + u32 sreg_pscbc_spare_ctrl_out : 4; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mmnoc_sf_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_mmnoc_sf_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MMNOC_SF_CFG_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mmnoc_sf_cfg_sregr_s +{ + u32 wakeup_timer : 8; + u32 sleep_timer : 8; + u32 mem_cph_timer : 6; + u32 mem_core_on_status : 1; + u32 mem_periph_on_status : 1; + u32 mem_core_on_ack_status : 1; + u32 mem_periph_on_ack_status : 1; + u32 mem_core_off_timer : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mmnoc_sf_cfg_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_mmnoc_sf_cfg_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MMNOC_HF_QX_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mmnoc_hf_qx_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 8; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved1 : 5; + u32 ignore_rpmh_clk_dis : 1; + u32 ignore_pmu_clk_dis : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mmnoc_hf_qx_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_mmnoc_hf_qx_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MMNOC_HF_QX_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mmnoc_hf_qx_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 4; + u32 pwr_fsm_clk_sel : 1; + u32 reserved1 : 3; + u32 sreg_pscbc_spare_ctrl_out : 4; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mmnoc_hf_qx_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_mmnoc_hf_qx_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MMNOC_HF_QX_CFG_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mmnoc_hf_qx_cfg_sregr_s +{ + u32 wakeup_timer : 8; + u32 sleep_timer : 8; + u32 mem_cph_timer : 6; + u32 mem_core_on_status : 1; + u32 mem_periph_on_status : 1; + u32 mem_core_on_ack_status : 1; + u32 mem_periph_on_ack_status : 1; + u32 mem_core_off_timer : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mmnoc_hf_qx_cfg_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_mmnoc_hf_qx_cfg_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MMNOC_PWRCTL_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mmnoc_pwrctl_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mmnoc_pwrctl_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_mmnoc_pwrctl_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MMNOC_QOSGEN_EXTREF_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mmnoc_qosgen_extref_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mmnoc_qosgen_extref_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_mmnoc_qosgen_extref_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MMSS_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mmss_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mmss_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_mmss_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MMSS_AT_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mmss_at_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mmss_at_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_mmss_at_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MMSS_QMIP_CORE_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mmss_qmip_core_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mmss_qmip_core_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_mmss_qmip_core_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MMSS_TRIG_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mmss_trig_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mmss_trig_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_mmss_trig_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MMSS_QMIP_CORE_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mmss_qmip_core_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mmss_qmip_core_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_mmss_qmip_core_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MMSS_QMIP_CORE_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mmss_qmip_core_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mmss_qmip_core_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_mmss_qmip_core_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MMSS_QM_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mmss_qm_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mmss_qm_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_mmss_qm_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CAMERA_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_camera_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_camera_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_camera_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CAMERA_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_camera_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_camera_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_camera_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QMIP_CAMERA_NRT_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qmip_camera_nrt_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qmip_camera_nrt_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qmip_camera_nrt_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QMIP_CAMERA_RT_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qmip_camera_rt_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qmip_camera_rt_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qmip_camera_rt_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CAMERA_HF_AXI_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_camera_hf_axi_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 8; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved1 : 5; + u32 ignore_rpmh_clk_dis : 1; + u32 ignore_pmu_clk_dis : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_camera_hf_axi_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_camera_hf_axi_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CAMERA_HF_AXI_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_camera_hf_axi_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 4; + u32 pwr_fsm_clk_sel : 1; + u32 reserved1 : 3; + u32 sreg_pscbc_spare_ctrl_out : 4; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_camera_hf_axi_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_camera_hf_axi_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CAMERA_HF_AXI_CFG_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_camera_hf_axi_cfg_sregr_s +{ + u32 wakeup_timer : 8; + u32 sleep_timer : 8; + u32 mem_cph_timer : 6; + u32 mem_core_on_status : 1; + u32 mem_periph_on_status : 1; + u32 mem_core_on_ack_status : 1; + u32 mem_periph_on_ack_status : 1; + u32 mem_core_off_timer : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_camera_hf_axi_cfg_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_camera_hf_axi_cfg_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CAMERA_SF_AXI_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_camera_sf_axi_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 8; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved1 : 5; + u32 ignore_rpmh_clk_dis : 1; + u32 ignore_pmu_clk_dis : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_camera_sf_axi_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_camera_sf_axi_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CAMERA_SF_AXI_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_camera_sf_axi_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 4; + u32 pwr_fsm_clk_sel : 1; + u32 reserved1 : 3; + u32 sreg_pscbc_spare_ctrl_out : 4; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_camera_sf_axi_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_camera_sf_axi_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CAMERA_SF_AXI_CFG_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_camera_sf_axi_cfg_sregr_s +{ + u32 wakeup_timer : 8; + u32 sleep_timer : 8; + u32 mem_cph_timer : 6; + u32 mem_core_on_status : 1; + u32 mem_periph_on_status : 1; + u32 mem_core_on_ack_status : 1; + u32 mem_periph_on_ack_status : 1; + u32 mem_core_off_timer : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_camera_sf_axi_cfg_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_camera_sf_axi_cfg_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CAMERA_XO_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_camera_xo_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_camera_xo_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_camera_xo_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DISPLAY_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_display_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_display_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_display_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DISP_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_disp_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_disp_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_disp_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QMIP_DISP_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qmip_disp_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qmip_disp_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qmip_disp_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DISP_HF_AXI_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_disp_hf_axi_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 8; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved1 : 5; + u32 ignore_rpmh_clk_dis : 1; + u32 ignore_pmu_clk_dis : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_disp_hf_axi_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_disp_hf_axi_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DISP_HF_AXI_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_disp_hf_axi_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 4; + u32 pwr_fsm_clk_sel : 1; + u32 reserved1 : 3; + u32 sreg_pscbc_spare_ctrl_out : 4; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_disp_hf_axi_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_disp_hf_axi_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DISP_HF_AXI_CFG_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_disp_hf_axi_cfg_sregr_s +{ + u32 wakeup_timer : 8; + u32 sleep_timer : 8; + u32 mem_cph_timer : 6; + u32 mem_core_on_status : 1; + u32 mem_periph_on_status : 1; + u32 mem_core_on_ack_status : 1; + u32 mem_periph_on_ack_status : 1; + u32 mem_core_off_timer : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_disp_hf_axi_cfg_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_disp_hf_axi_cfg_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DISP_XO_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_disp_xo_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_disp_xo_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_disp_xo_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_VIDEO_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_video_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_video_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_video_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_VIDEO_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_video_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_video_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_video_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QMIP_VIDEO_CVP_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qmip_video_cvp_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qmip_video_cvp_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qmip_video_cvp_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QMIP_VIDEO_VCODEC_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qmip_video_vcodec_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qmip_video_vcodec_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qmip_video_vcodec_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QMIP_VIDEO_V_CPU_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qmip_video_v_cpu_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qmip_video_v_cpu_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qmip_video_v_cpu_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QMIP_VIDEO_CV_CPU_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qmip_video_cv_cpu_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qmip_video_cv_cpu_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qmip_video_cv_cpu_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_VIDEO_AXI0_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_video_axi0_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 8; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved1 : 5; + u32 ignore_rpmh_clk_dis : 1; + u32 ignore_pmu_clk_dis : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_video_axi0_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_video_axi0_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_VIDEO_AXI0_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_video_axi0_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 4; + u32 pwr_fsm_clk_sel : 1; + u32 reserved1 : 3; + u32 sreg_pscbc_spare_ctrl_out : 4; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_video_axi0_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_video_axi0_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_VIDEO_AXI0_CFG_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_video_axi0_cfg_sregr_s +{ + u32 wakeup_timer : 8; + u32 sleep_timer : 8; + u32 mem_cph_timer : 6; + u32 mem_core_on_status : 1; + u32 mem_periph_on_status : 1; + u32 mem_core_on_ack_status : 1; + u32 mem_periph_on_ack_status : 1; + u32 mem_core_off_timer : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_video_axi0_cfg_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_video_axi0_cfg_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_VIDEO_AXI1_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_video_axi1_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 8; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved1 : 5; + u32 ignore_rpmh_clk_dis : 1; + u32 ignore_pmu_clk_dis : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_video_axi1_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_video_axi1_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_VIDEO_AXI1_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_video_axi1_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 4; + u32 pwr_fsm_clk_sel : 1; + u32 reserved1 : 3; + u32 sreg_pscbc_spare_ctrl_out : 4; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_video_axi1_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_video_axi1_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_VIDEO_AXI1_CFG_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_video_axi1_cfg_sregr_s +{ + u32 wakeup_timer : 8; + u32 sleep_timer : 8; + u32 mem_cph_timer : 6; + u32 mem_core_on_status : 1; + u32 mem_periph_on_status : 1; + u32 mem_core_on_ack_status : 1; + u32 mem_periph_on_ack_status : 1; + u32 mem_core_off_timer : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_video_axi1_cfg_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_video_axi1_cfg_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_VIDEO_XO_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_video_xo_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_video_xo_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_video_xo_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QDSS_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qdss_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qdss_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_qdss_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QDSS_DAP_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qdss_dap_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qdss_dap_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qdss_dap_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QDSS_CFG_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qdss_cfg_ahb_cbcr_s +{ + u32 reserved0 : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved1 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qdss_cfg_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qdss_cfg_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QDSS_CENTER_AT_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qdss_center_at_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 8; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved1 : 5; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qdss_center_at_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qdss_center_at_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QDSS_CENTER_AT_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qdss_center_at_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 4; + u32 pwr_fsm_clk_sel : 1; + u32 reserved1 : 3; + u32 sreg_pscbc_spare_ctrl_out : 4; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qdss_center_at_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_qdss_center_at_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QDSS_CENTER_AT_CFG_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qdss_center_at_cfg_sregr_s +{ + u32 wakeup_timer : 8; + u32 sleep_timer : 8; + u32 mem_cph_timer : 6; + u32 mem_core_on_status : 1; + u32 mem_periph_on_status : 1; + u32 mem_core_on_ack_status : 1; + u32 mem_periph_on_ack_status : 1; + u32 mem_core_off_timer : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qdss_center_at_cfg_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_qdss_center_at_cfg_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SOUTH_AT_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_south_at_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_south_at_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_south_at_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_WEST_AT_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_west_at_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_west_at_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_west_at_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_NORTH_AT_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_north_at_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_north_at_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_north_at_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PHY_AT_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_phy_at_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_phy_at_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_phy_at_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QDSS_ETR_USB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qdss_etr_usb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qdss_etr_usb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qdss_etr_usb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QDSS_ETR_DDR_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qdss_etr_ddr_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qdss_etr_ddr_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qdss_etr_ddr_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QDSS_STM_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qdss_stm_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qdss_stm_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qdss_stm_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QDSS_TRACECLKIN_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qdss_traceclkin_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qdss_traceclkin_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qdss_traceclkin_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QDSS_TSCTR_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qdss_tsctr_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qdss_tsctr_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qdss_tsctr_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QDSS_TRIG_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qdss_trig_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qdss_trig_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qdss_trig_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QDSS_DAP_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qdss_dap_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qdss_dap_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qdss_dap_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CENTER_APB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_center_apb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_center_apb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_center_apb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_NORTH_APB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_north_apb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_north_apb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_north_apb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SOUTH_APB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_south_apb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_south_apb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_south_apb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_WEST_APB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_west_apb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_west_apb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_west_apb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_EAST_APB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_east_apb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_east_apb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_east_apb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MMNOC_APB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mmnoc_apb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mmnoc_apb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_mmnoc_apb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QDSS_XO_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qdss_xo_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qdss_xo_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qdss_xo_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QDSS_USB_PRIM_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qdss_usb_prim_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qdss_usb_prim_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qdss_usb_prim_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_a_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_a_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_a_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_a_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_a_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_a_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_a_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_a_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_a_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_a_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_a_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_a_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_a_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_a_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_a_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_a_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_a_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_a_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_a_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_a_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_a_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_a_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_a_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_a_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_a_perf8_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_a_perf8_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_a_perf8_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_a_perf9_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_a_perf9_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_a_perf9_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_a_perf10_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_a_perf10_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_a_perf10_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_a_perf11_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_a_perf11_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_a_perf11_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_a_perf12_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_a_perf12_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_a_perf12_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_a_perf13_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_a_perf13_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_a_perf13_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_a_perf14_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_a_perf14_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_a_perf14_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_a_perf15_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_a_perf15_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_a_perf15_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QDSS_ATB_A_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qdss_atb_a_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qdss_atb_a_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qdss_atb_a_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QDSS_ATB_A_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qdss_atb_a_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qdss_atb_a_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qdss_atb_a_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_b_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_b_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_b_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_b_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_b_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_b_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_b_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_b_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_b_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_b_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_b_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_b_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_b_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_b_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_b_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_b_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_b_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_b_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_b_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_b_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_b_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_b_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_b_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_b_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_b_perf8_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_b_perf8_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_b_perf8_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_b_perf9_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_b_perf9_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_b_perf9_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_b_perf10_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_b_perf10_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_b_perf10_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_b_perf11_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_b_perf11_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_b_perf11_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_b_perf12_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_b_perf12_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_b_perf12_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_b_perf13_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_b_perf13_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_b_perf13_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_b_perf14_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_b_perf14_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_b_perf14_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_b_perf15_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_b_perf15_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_b_perf15_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QDSS_ATB_B_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qdss_atb_b_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qdss_atb_b_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qdss_atb_b_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QDSS_ATB_B_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qdss_atb_b_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qdss_atb_b_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qdss_atb_b_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_c_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_c_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_c_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_c_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_c_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_c_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_c_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_c_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_c_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_c_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_c_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_c_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_c_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_c_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_c_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_c_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_c_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_c_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_c_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_c_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_c_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_c_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_c_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_c_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_c_perf8_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_c_perf8_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_c_perf8_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_c_perf9_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_c_perf9_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_c_perf9_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_c_perf10_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_c_perf10_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_c_perf10_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_c_perf11_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_c_perf11_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_c_perf11_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_c_perf12_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_c_perf12_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_c_perf12_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_c_perf13_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_c_perf13_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_c_perf13_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_c_perf14_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_c_perf14_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_c_perf14_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_c_perf15_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_c_perf15_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_atb_c_perf15_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QDSS_ATB_C_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qdss_atb_c_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qdss_atb_c_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qdss_atb_c_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QDSS_ATB_C_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qdss_atb_c_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qdss_atb_c_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qdss_atb_c_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf8_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf8_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf8_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf9_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf9_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf9_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf10_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf10_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf10_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf11_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf11_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf11_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf12_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf12_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf12_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf13_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf13_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf13_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf14_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf14_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf14_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf15_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf15_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_stm_perf15_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QDSS_STM_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qdss_stm_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qdss_stm_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qdss_stm_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QDSS_STM_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qdss_stm_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qdss_stm_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qdss_stm_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf8_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf8_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf8_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf9_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf9_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf9_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf10_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf10_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf10_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf11_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf11_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf11_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf12_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf12_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf12_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf13_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf13_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf13_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf14_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf14_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf14_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf15_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf15_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_qdss_traceclkin_perf15_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QDSS_TRACECLKIN_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qdss_traceclkin_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qdss_traceclkin_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qdss_traceclkin_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QDSS_TRACECLKIN_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qdss_traceclkin_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qdss_traceclkin_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qdss_traceclkin_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QDSS_APB_TSCTR_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qdss_apb_tsctr_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qdss_apb_tsctr_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qdss_apb_tsctr_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QDSS_APB_TSCTR_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qdss_apb_tsctr_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qdss_apb_tsctr_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qdss_apb_tsctr_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf8_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf8_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf8_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf9_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf9_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf9_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf10_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf10_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf10_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf11_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf11_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf11_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf12_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf12_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf12_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf13_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf13_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf13_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf14_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf14_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf14_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf15_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf15_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_qdss_trig_perf15_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QDSS_TRIG_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qdss_trig_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qdss_trig_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qdss_trig_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QDSS_TRIG_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qdss_trig_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qdss_trig_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qdss_trig_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB30_PRIM_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb30_prim_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb30_prim_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_usb30_prim_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB30_PRIM_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb30_prim_gdscr_s +{ + u32 sw_collapse : 1; + u32 hw_control : 1; + u32 sw_override : 1; + u32 pd_ares : 1; + u32 clk_disable : 1; + u32 clamp_io : 1; + u32 en_few : 1; + u32 en_rest : 1; + u32 retain : 1; + u32 save : 1; + u32 restore : 1; + u32 retain_ff_enable : 1; + u32 clk_dis_wait : 4; + u32 en_few_wait : 4; + u32 en_rest_wait : 4; + u32 reserved0 : 3; + u32 gdsc_state : 4; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb30_prim_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_usb30_prim_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB30_PRIM_CFG_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb30_prim_cfg_gdscr_s +{ + u32 disable_clk_software_override : 1; + u32 clamp_io_software_override : 1; + u32 save_restore_software_override : 1; + u32 unclamp_io_software_override : 1; + u32 gdsc_pscbc_pwr_dwn_sw : 1; + u32 gdsc_phase_reset_delay_count_sw : 2; + u32 gdsc_phase_reset_en_sw : 1; + u32 gdsc_mem_core_force_in_sw : 1; + u32 gdsc_mem_peri_force_in_sw : 1; + u32 gdsc_handshake_dis : 1; + u32 software_control_override : 4; + u32 gdsc_power_down_complete : 1; + u32 gdsc_power_up_complete : 1; + u32 gdsc_enf_ack_status : 1; + u32 gdsc_enr_ack_status : 1; + u32 gdsc_mem_pwr_ack_status : 1; + u32 gdsc_cfg_fsm_state_status : 4; + u32 gdsc_pwr_up_start : 1; + u32 gdsc_pwr_dwn_start : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 5; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb30_prim_cfg_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_usb30_prim_cfg_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB30_PRIM_CFG2_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb30_prim_cfg2_gdscr_s +{ + u32 mem_pwr_dwn_timeout : 4; + u32 dly_assert_clamp_mem : 4; + u32 dly_deassert_clamp_mem : 4; + u32 dly_mem_pwr_up : 4; + u32 gdsc_clamp_mem_sw : 1; + u32 gdsc_pwrdwn_enable_ack_override : 1; + u32 gdsc_mem_pwrup_ack_override : 1; + u32 reserved0 : 13; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb30_prim_cfg2_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_usb30_prim_cfg2_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB30_PRIM_CFG3_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb30_prim_cfg3_gdscr_s +{ + u32 gdsc_spare_ctrl_out : 8; + u32 gdsc_spare_ctrl_in : 8; + u32 gdsc_accu_red_sw_override : 1; + u32 gdsc_accu_red_shifter_start_sw : 1; + u32 gdsc_accu_red_shifter_clk_en_sw : 1; + u32 gdsc_accu_red_shifter_done_override : 1; + u32 gdsc_accu_red_timer_en_sw : 1; + u32 dly_accu_red_shifter_done : 4; + u32 gdsc_accu_red_enable : 1; + u32 gdsc_accu_red_shifter_done_status : 1; + u32 reserved0 : 5; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb30_prim_cfg3_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_usb30_prim_cfg3_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB30_PRIM_CFG4_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb30_prim_cfg4_gdscr_s +{ + u32 dly_retainff : 4; + u32 dly_clampio : 4; + u32 dly_deassertares : 4; + u32 dly_noretainff : 4; + u32 dly_restoreff : 4; + u32 dly_unclampio : 4; + u32 reserved0 : 8; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb30_prim_cfg4_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_usb30_prim_cfg4_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB30_PRIM_MASTER_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb30_prim_master_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 9; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved2 : 7; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb30_prim_master_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_usb30_prim_master_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB30_PRIM_MASTER_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb30_prim_master_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 4; + u32 pwr_fsm_clk_sel : 1; + u32 reserved1 : 3; + u32 sreg_pscbc_spare_ctrl_out : 4; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb30_prim_master_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_usb30_prim_master_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB30_PRIM_MASTER_CFG_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb30_prim_master_cfg_sregr_s +{ + u32 wakeup_timer : 8; + u32 sleep_timer : 8; + u32 mem_cph_timer : 6; + u32 mem_core_on_status : 1; + u32 mem_periph_on_status : 1; + u32 mem_core_on_ack_status : 1; + u32 mem_periph_on_ack_status : 1; + u32 mem_core_off_timer : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb30_prim_master_cfg_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_usb30_prim_master_cfg_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB30_PRIM_SLEEP_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb30_prim_sleep_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb30_prim_sleep_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_usb30_prim_sleep_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB30_PRIM_MOCK_UTMI_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb30_prim_mock_utmi_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb30_prim_mock_utmi_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_usb30_prim_mock_utmi_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB30_PRIM_MASTER_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb30_prim_master_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 dirty_m : 1; + u32 dirty_n : 1; + u32 dirty_d : 1; + u32 reserved1 : 23; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb30_prim_master_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_usb30_prim_master_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB30_PRIM_MASTER_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb30_prim_master_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 6; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb30_prim_master_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_usb30_prim_master_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB30_PRIM_MASTER_M +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb30_prim_master_m_s +{ + u32 m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb30_prim_master_m_u +{ + struct ipa_gcc_hwio_def_gcc_usb30_prim_master_m_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB30_PRIM_MASTER_N +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb30_prim_master_n_s +{ + u32 not_n_minus_m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb30_prim_master_n_u +{ + struct ipa_gcc_hwio_def_gcc_usb30_prim_master_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB30_PRIM_MASTER_D +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb30_prim_master_d_s +{ + u32 not_2d : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb30_prim_master_d_u +{ + struct ipa_gcc_hwio_def_gcc_usb30_prim_master_d_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb30_prim_mock_utmi_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb30_prim_mock_utmi_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_usb30_prim_mock_utmi_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb30_prim_mock_utmi_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb30_prim_mock_utmi_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_usb30_prim_mock_utmi_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CDIVR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb30_prim_mock_utmi_postdiv_cdivr_s +{ + u32 clk_div : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb30_prim_mock_utmi_postdiv_cdivr_u +{ + struct ipa_gcc_hwio_def_gcc_usb30_prim_mock_utmi_postdiv_cdivr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB3_PRIM_PHY_AUX_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb3_prim_phy_aux_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb3_prim_phy_aux_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_usb3_prim_phy_aux_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB3_PRIM_PHY_COM_AUX_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb3_prim_phy_com_aux_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb3_prim_phy_com_aux_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_usb3_prim_phy_com_aux_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB3_PRIM_PHY_PIPE_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb3_prim_phy_pipe_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb3_prim_phy_pipe_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_usb3_prim_phy_pipe_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB3_PRIM_PHY_AUX_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb3_prim_phy_aux_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb3_prim_phy_aux_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_usb3_prim_phy_aux_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB3_PRIM_PHY_AUX_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb3_prim_phy_aux_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb3_prim_phy_aux_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_usb3_prim_phy_aux_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB3_PHY_PRIM_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb3_phy_prim_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb3_phy_prim_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_usb3_phy_prim_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB3PHY_PHY_PRIM_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb3phy_phy_prim_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb3phy_phy_prim_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_usb3phy_phy_prim_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB3_DP_PHY_PRIM_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb3_dp_phy_prim_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb3_dp_phy_prim_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_usb3_dp_phy_prim_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB3_PHY_SEC_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb3_phy_sec_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb3_phy_sec_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_usb3_phy_sec_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB3PHY_PHY_SEC_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb3phy_phy_sec_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb3phy_phy_sec_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_usb3phy_phy_sec_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB3_DP_PHY_SEC_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb3_dp_phy_sec_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb3_dp_phy_sec_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_usb3_dp_phy_sec_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB3_PHY_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb3_phy_gdscr_s +{ + u32 sw_collapse : 1; + u32 hw_control : 1; + u32 sw_override : 1; + u32 pd_ares : 1; + u32 clk_disable : 1; + u32 clamp_io : 1; + u32 en_few : 1; + u32 en_rest : 1; + u32 retain : 1; + u32 save : 1; + u32 restore : 1; + u32 retain_ff_enable : 1; + u32 clk_dis_wait : 4; + u32 en_few_wait : 4; + u32 en_rest_wait : 4; + u32 reserved0 : 3; + u32 gdsc_state : 4; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb3_phy_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_usb3_phy_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB3_PHY_CFG_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb3_phy_cfg_gdscr_s +{ + u32 disable_clk_software_override : 1; + u32 clamp_io_software_override : 1; + u32 save_restore_software_override : 1; + u32 unclamp_io_software_override : 1; + u32 gdsc_pscbc_pwr_dwn_sw : 1; + u32 gdsc_phase_reset_delay_count_sw : 2; + u32 gdsc_phase_reset_en_sw : 1; + u32 gdsc_mem_core_force_in_sw : 1; + u32 gdsc_mem_peri_force_in_sw : 1; + u32 gdsc_handshake_dis : 1; + u32 software_control_override : 4; + u32 gdsc_power_down_complete : 1; + u32 gdsc_power_up_complete : 1; + u32 gdsc_enf_ack_status : 1; + u32 gdsc_enr_ack_status : 1; + u32 gdsc_mem_pwr_ack_status : 1; + u32 gdsc_cfg_fsm_state_status : 4; + u32 gdsc_pwr_up_start : 1; + u32 gdsc_pwr_dwn_start : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 5; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb3_phy_cfg_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_usb3_phy_cfg_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB3_PHY_CFG2_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb3_phy_cfg2_gdscr_s +{ + u32 mem_pwr_dwn_timeout : 4; + u32 dly_assert_clamp_mem : 4; + u32 dly_deassert_clamp_mem : 4; + u32 dly_mem_pwr_up : 4; + u32 gdsc_clamp_mem_sw : 1; + u32 gdsc_pwrdwn_enable_ack_override : 1; + u32 gdsc_mem_pwrup_ack_override : 1; + u32 reserved0 : 13; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb3_phy_cfg2_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_usb3_phy_cfg2_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB3_PHY_CFG3_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb3_phy_cfg3_gdscr_s +{ + u32 gdsc_spare_ctrl_out : 8; + u32 gdsc_spare_ctrl_in : 8; + u32 gdsc_accu_red_sw_override : 1; + u32 gdsc_accu_red_shifter_start_sw : 1; + u32 gdsc_accu_red_shifter_clk_en_sw : 1; + u32 gdsc_accu_red_shifter_done_override : 1; + u32 gdsc_accu_red_timer_en_sw : 1; + u32 dly_accu_red_shifter_done : 4; + u32 gdsc_accu_red_enable : 1; + u32 gdsc_accu_red_shifter_done_status : 1; + u32 reserved0 : 5; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb3_phy_cfg3_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_usb3_phy_cfg3_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB3_PHY_CFG4_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb3_phy_cfg4_gdscr_s +{ + u32 dly_retainff : 4; + u32 dly_clampio : 4; + u32 dly_deassertares : 4; + u32 dly_noretainff : 4; + u32 dly_restoreff : 4; + u32 dly_unclampio : 4; + u32 reserved0 : 8; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb3_phy_cfg4_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_usb3_phy_cfg4_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUSB2PHY_PRIM_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qusb2phy_prim_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qusb2phy_prim_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_qusb2phy_prim_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUSB2PHY_SEC_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qusb2phy_sec_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qusb2phy_sec_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_qusb2phy_sec_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_USB_PHY_CFG_AHB2PHY_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_usb_phy_cfg_ahb2phy_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_usb_phy_cfg_ahb2phy_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_usb_phy_cfg_ahb2phy_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AHB2PHY_0_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ahb2phy_0_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ahb2phy_0_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ahb2phy_0_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SDCC2_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sdcc2_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sdcc2_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_sdcc2_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SDCC2_APPS_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sdcc2_apps_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 9; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved2 : 7; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sdcc2_apps_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_sdcc2_apps_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SDCC2_APPS_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sdcc2_apps_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 4; + u32 pwr_fsm_clk_sel : 1; + u32 reserved1 : 3; + u32 sreg_pscbc_spare_ctrl_out : 4; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sdcc2_apps_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_sdcc2_apps_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SDCC2_APPS_CFG_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sdcc2_apps_cfg_sregr_s +{ + u32 wakeup_timer : 8; + u32 sleep_timer : 8; + u32 mem_cph_timer : 6; + u32 mem_core_on_status : 1; + u32 mem_periph_on_status : 1; + u32 mem_core_on_ack_status : 1; + u32 mem_periph_on_ack_status : 1; + u32 mem_core_off_timer : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sdcc2_apps_cfg_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_sdcc2_apps_cfg_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SDCC2_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sdcc2_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sdcc2_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_sdcc2_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SDCC2_AT_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sdcc2_at_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sdcc2_at_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_sdcc2_at_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SDCC2_APPS_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sdcc2_apps_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 dirty_m : 1; + u32 dirty_n : 1; + u32 dirty_d : 1; + u32 reserved1 : 23; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sdcc2_apps_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_sdcc2_apps_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SDCC2_APPS_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sdcc2_apps_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 6; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sdcc2_apps_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_sdcc2_apps_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SDCC2_APPS_M +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sdcc2_apps_m_s +{ + u32 m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sdcc2_apps_m_u +{ + struct ipa_gcc_hwio_def_gcc_sdcc2_apps_m_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SDCC2_APPS_N +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sdcc2_apps_n_s +{ + u32 not_n_minus_m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sdcc2_apps_n_u +{ + struct ipa_gcc_hwio_def_gcc_sdcc2_apps_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SDCC2_APPS_D +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sdcc2_apps_d_s +{ + u32 not_2d : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sdcc2_apps_d_u +{ + struct ipa_gcc_hwio_def_gcc_sdcc2_apps_d_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SDCC4_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sdcc4_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sdcc4_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_sdcc4_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SDCC4_APPS_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sdcc4_apps_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 9; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved2 : 7; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sdcc4_apps_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_sdcc4_apps_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SDCC4_APPS_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sdcc4_apps_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 4; + u32 pwr_fsm_clk_sel : 1; + u32 reserved1 : 3; + u32 sreg_pscbc_spare_ctrl_out : 4; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sdcc4_apps_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_sdcc4_apps_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SDCC4_APPS_CFG_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sdcc4_apps_cfg_sregr_s +{ + u32 wakeup_timer : 8; + u32 sleep_timer : 8; + u32 mem_cph_timer : 6; + u32 mem_core_on_status : 1; + u32 mem_periph_on_status : 1; + u32 mem_core_on_ack_status : 1; + u32 mem_periph_on_ack_status : 1; + u32 mem_core_off_timer : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sdcc4_apps_cfg_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_sdcc4_apps_cfg_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SDCC4_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sdcc4_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sdcc4_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_sdcc4_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SDCC4_AT_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sdcc4_at_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sdcc4_at_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_sdcc4_at_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SDCC4_APPS_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sdcc4_apps_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 dirty_m : 1; + u32 dirty_n : 1; + u32 dirty_d : 1; + u32 reserved1 : 23; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sdcc4_apps_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_sdcc4_apps_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SDCC4_APPS_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sdcc4_apps_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 6; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sdcc4_apps_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_sdcc4_apps_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SDCC4_APPS_M +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sdcc4_apps_m_s +{ + u32 m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sdcc4_apps_m_u +{ + struct ipa_gcc_hwio_def_gcc_sdcc4_apps_m_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SDCC4_APPS_N +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sdcc4_apps_n_s +{ + u32 not_n_minus_m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sdcc4_apps_n_u +{ + struct ipa_gcc_hwio_def_gcc_sdcc4_apps_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SDCC4_APPS_D +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sdcc4_apps_d_s +{ + u32 not_2d : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sdcc4_apps_d_u +{ + struct ipa_gcc_hwio_def_gcc_sdcc4_apps_d_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAPPER_I2C_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrapper_i2c_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrapper_i2c_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrapper_i2c_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_I2C_S_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_i2c_s_ahb_cbcr_s +{ + u32 reserved0 : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved1 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_i2c_s_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_i2c_s_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_I2C_CORE_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_i2c_core_cbcr_s +{ + u32 reserved0 : 2; + u32 clk_ares : 1; + u32 reserved1 : 9; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved2 : 5; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved3 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved4 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_i2c_core_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_i2c_core_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_I2C_CORE_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_i2c_core_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 4; + u32 pwr_fsm_clk_sel : 1; + u32 reserved1 : 3; + u32 sreg_pscbc_spare_ctrl_out : 4; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_i2c_core_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_i2c_core_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_I2C_CORE_CFG_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_i2c_core_cfg_sregr_s +{ + u32 wakeup_timer : 8; + u32 sleep_timer : 8; + u32 mem_cph_timer : 6; + u32 mem_core_on_status : 1; + u32 mem_periph_on_status : 1; + u32 mem_core_on_ack_status : 1; + u32 mem_periph_on_ack_status : 1; + u32 mem_core_off_timer : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_i2c_core_cfg_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_i2c_core_cfg_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_cmd_dfsr_s +{ + u32 dfs_en : 1; + u32 curr_perf_state : 4; + u32 hw_clk_control : 1; + u32 dfs_fsm_state : 3; + u32 perf_state_update_status : 1; + u32 sw_override : 1; + u32 sw_perf_state : 4; + u32 rcg_sw_ctrl : 3; + u32 reserved0 : 14; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_cmd_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_cmd_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_i2c_core_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_i2c_core_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_i2c_core_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_i2c_core_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_i2c_core_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_i2c_core_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_i2c_core_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_i2c_core_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_i2c_core_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_i2c_core_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_i2c_core_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_i2c_core_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_i2c_core_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_i2c_core_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_i2c_core_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_i2c_core_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_i2c_core_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_i2c_core_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_i2c_core_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_i2c_core_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_i2c_core_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_i2c_core_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_i2c_core_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_i2c_core_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF8_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_i2c_core_perf8_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_i2c_core_perf8_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_i2c_core_perf8_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF9_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_i2c_core_perf9_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_i2c_core_perf9_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_i2c_core_perf9_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF10_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_i2c_core_perf10_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_i2c_core_perf10_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_i2c_core_perf10_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF11_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_i2c_core_perf11_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_i2c_core_perf11_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_i2c_core_perf11_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF12_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_i2c_core_perf12_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_i2c_core_perf12_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_i2c_core_perf12_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF13_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_i2c_core_perf13_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_i2c_core_perf13_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_i2c_core_perf13_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF14_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_i2c_core_perf14_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_i2c_core_perf14_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_i2c_core_perf14_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_QUPV3_I2C_CORE_PERF15_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_i2c_core_perf15_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_i2c_core_perf15_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_i2c_core_perf15_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_I2C_CORE_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_i2c_core_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_i2c_core_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_i2c_core_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_I2C_CORE_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_i2c_core_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_i2c_core_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_i2c_core_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_I2C_S0_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_i2c_s0_cbcr_s +{ + u32 reserved0 : 2; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_i2c_s0_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_i2c_s0_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_I2C_S0_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_i2c_s0_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_i2c_s0_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_i2c_s0_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_I2C_S0_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_i2c_s0_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_i2c_s0_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_i2c_s0_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_I2C_S1_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_i2c_s1_cbcr_s +{ + u32 reserved0 : 2; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_i2c_s1_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_i2c_s1_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_I2C_S1_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_i2c_s1_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_i2c_s1_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_i2c_s1_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_I2C_S1_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_i2c_s1_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_i2c_s1_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_i2c_s1_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_I2C_S2_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_i2c_s2_cbcr_s +{ + u32 reserved0 : 2; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_i2c_s2_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_i2c_s2_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_I2C_S2_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_i2c_s2_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_i2c_s2_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_i2c_s2_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_I2C_S2_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_i2c_s2_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_i2c_s2_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_i2c_s2_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_I2C_S3_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_i2c_s3_cbcr_s +{ + u32 reserved0 : 2; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_i2c_s3_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_i2c_s3_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_I2C_S3_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_i2c_s3_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_i2c_s3_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_i2c_s3_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_I2C_S3_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_i2c_s3_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_i2c_s3_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_i2c_s3_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_I2C_S4_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_i2c_s4_cbcr_s +{ + u32 reserved0 : 2; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_i2c_s4_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_i2c_s4_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_I2C_S4_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_i2c_s4_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_i2c_s4_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_i2c_s4_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_I2C_S4_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_i2c_s4_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_i2c_s4_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_i2c_s4_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_I2C_S5_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_i2c_s5_cbcr_s +{ + u32 reserved0 : 2; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_i2c_s5_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_i2c_s5_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_I2C_S5_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_i2c_s5_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_i2c_s5_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_i2c_s5_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_I2C_S5_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_i2c_s5_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_i2c_s5_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_i2c_s5_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_I2C_S6_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_i2c_s6_cbcr_s +{ + u32 reserved0 : 2; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_i2c_s6_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_i2c_s6_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_I2C_S6_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_i2c_s6_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_i2c_s6_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_i2c_s6_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_I2C_S6_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_i2c_s6_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_i2c_s6_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_i2c_s6_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_I2C_S7_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_i2c_s7_cbcr_s +{ + u32 reserved0 : 2; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_i2c_s7_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_i2c_s7_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_I2C_S7_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_i2c_s7_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_i2c_s7_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_i2c_s7_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_I2C_S7_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_i2c_s7_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_i2c_s7_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_i2c_s7_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_I2C_S8_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_i2c_s8_cbcr_s +{ + u32 reserved0 : 2; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_i2c_s8_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_i2c_s8_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_I2C_S8_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_i2c_s8_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_i2c_s8_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_i2c_s8_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_I2C_S8_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_i2c_s8_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_i2c_s8_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_i2c_s8_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_I2C_S9_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_i2c_s9_cbcr_s +{ + u32 reserved0 : 2; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_i2c_s9_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_i2c_s9_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_I2C_S9_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_i2c_s9_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_i2c_s9_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_i2c_s9_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_I2C_S9_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_i2c_s9_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_i2c_s9_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_i2c_s9_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAPPER_1_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrapper_1_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrapper_1_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrapper_1_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP_1_M_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap_1_m_ahb_cbcr_s +{ + u32 reserved0 : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved1 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap_1_m_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap_1_m_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP_1_S_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap_1_s_ahb_cbcr_s +{ + u32 reserved0 : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved1 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap_1_s_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap_1_s_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_CORE_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_core_cbcr_s +{ + u32 reserved0 : 2; + u32 clk_ares : 1; + u32 reserved1 : 9; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved2 : 5; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved3 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved4 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_core_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_core_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_CORE_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_core_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 4; + u32 pwr_fsm_clk_sel : 1; + u32 reserved1 : 3; + u32 sreg_pscbc_spare_ctrl_out : 4; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_core_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_core_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_CORE_CFG_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_core_cfg_sregr_s +{ + u32 wakeup_timer : 8; + u32 sleep_timer : 8; + u32 mem_cph_timer : 6; + u32 mem_core_on_status : 1; + u32 mem_periph_on_status : 1; + u32 mem_core_on_ack_status : 1; + u32 mem_periph_on_ack_status : 1; + u32 mem_core_off_timer : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_core_cfg_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_core_cfg_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_CORE_DIV_CDIVR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_core_div_cdivr_s +{ + u32 clk_div : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_core_div_cdivr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_core_div_cdivr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_CORE_2X_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_core_2x_cbcr_s +{ + u32 reserved0 : 2; + u32 clk_ares : 1; + u32 reserved1 : 9; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved2 : 5; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved3 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved4 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_core_2x_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_core_2x_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_CORE_2X_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_core_2x_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 4; + u32 pwr_fsm_clk_sel : 1; + u32 reserved1 : 3; + u32 sreg_pscbc_spare_ctrl_out : 4; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_core_2x_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_core_2x_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_CORE_2X_CFG_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_core_2x_cfg_sregr_s +{ + u32 wakeup_timer : 8; + u32 sleep_timer : 8; + u32 mem_cph_timer : 6; + u32 mem_core_on_status : 1; + u32 mem_periph_on_status : 1; + u32 mem_core_on_ack_status : 1; + u32 mem_periph_on_ack_status : 1; + u32 mem_core_off_timer : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_core_2x_cfg_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_core_2x_cfg_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap1_core_2x_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap1_core_2x_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap1_core_2x_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap1_core_2x_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap1_core_2x_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap1_core_2x_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap1_core_2x_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap1_core_2x_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap1_core_2x_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap1_core_2x_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap1_core_2x_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap1_core_2x_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap1_core_2x_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap1_core_2x_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap1_core_2x_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap1_core_2x_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap1_core_2x_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap1_core_2x_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap1_core_2x_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap1_core_2x_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap1_core_2x_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap1_core_2x_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap1_core_2x_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap1_core_2x_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap1_core_2x_perf8_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap1_core_2x_perf8_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap1_core_2x_perf8_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap1_core_2x_perf9_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap1_core_2x_perf9_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap1_core_2x_perf9_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap1_core_2x_perf10_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap1_core_2x_perf10_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap1_core_2x_perf10_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap1_core_2x_perf11_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap1_core_2x_perf11_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap1_core_2x_perf11_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap1_core_2x_perf12_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap1_core_2x_perf12_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap1_core_2x_perf12_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap1_core_2x_perf13_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap1_core_2x_perf13_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap1_core_2x_perf13_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap1_core_2x_perf14_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap1_core_2x_perf14_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap1_core_2x_perf14_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap1_core_2x_perf15_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap1_core_2x_perf15_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap1_core_2x_perf15_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_core_2x_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_core_2x_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_core_2x_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_core_2x_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_core_2x_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_core_2x_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S0_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s0_cbcr_s +{ + u32 reserved0 : 2; + u32 clk_ares : 1; + u32 reserved1 : 9; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved2 : 7; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s0_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s0_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S0_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s0_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 4; + u32 pwr_fsm_clk_sel : 1; + u32 reserved1 : 3; + u32 sreg_pscbc_spare_ctrl_out : 4; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s0_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s0_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S0_CFG_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s0_cfg_sregr_s +{ + u32 wakeup_timer : 8; + u32 sleep_timer : 8; + u32 mem_cph_timer : 6; + u32 mem_core_on_status : 1; + u32 mem_periph_on_status : 1; + u32 mem_core_on_ack_status : 1; + u32 mem_periph_on_ack_status : 1; + u32 mem_core_off_timer : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s0_cfg_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s0_cfg_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE0_CMD_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_cmd_dfsr_s +{ + u32 dfs_en : 1; + u32 curr_perf_state : 4; + u32 hw_clk_control : 1; + u32 dfs_fsm_state : 3; + u32 perf_state_update_status : 1; + u32 sw_override : 1; + u32 sw_perf_state : 4; + u32 rcg_sw_ctrl : 1; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_cmd_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_cmd_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf0_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf0_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf0_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf1_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf1_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf1_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf2_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf2_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf2_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf3_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf3_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf3_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf4_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf4_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf4_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf5_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf5_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf5_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf6_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf6_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf6_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf7_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf7_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf7_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf0_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf0_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf0_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf1_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf1_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf1_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf2_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf2_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf2_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf3_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf3_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf3_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf4_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf4_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf4_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf5_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf5_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf5_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf6_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf6_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf6_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf7_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf7_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf7_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf0_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf0_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf0_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf1_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf1_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf1_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf2_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf2_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf2_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf3_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf3_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf3_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf4_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf4_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf4_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf5_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf5_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf5_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf6_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf6_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf6_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf7_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf7_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se0_qupv3_wrap1_s0_perf7_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S0_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s0_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 dirty_m : 1; + u32 dirty_n : 1; + u32 dirty_d : 1; + u32 reserved1 : 23; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s0_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s0_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S0_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s0_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 6; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s0_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s0_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S0_M +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s0_m_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s0_m_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s0_m_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S0_N +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s0_n_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s0_n_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s0_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S0_D +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s0_d_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s0_d_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s0_d_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S1_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s1_cbcr_s +{ + u32 reserved0 : 2; + u32 clk_ares : 1; + u32 reserved1 : 9; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved2 : 7; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s1_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s1_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S1_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s1_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 4; + u32 pwr_fsm_clk_sel : 1; + u32 reserved1 : 3; + u32 sreg_pscbc_spare_ctrl_out : 4; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s1_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s1_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S1_CFG_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s1_cfg_sregr_s +{ + u32 wakeup_timer : 8; + u32 sleep_timer : 8; + u32 mem_cph_timer : 6; + u32 mem_core_on_status : 1; + u32 mem_periph_on_status : 1; + u32 mem_core_on_ack_status : 1; + u32 mem_periph_on_ack_status : 1; + u32 mem_core_off_timer : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s1_cfg_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s1_cfg_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE1_CMD_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_cmd_dfsr_s +{ + u32 dfs_en : 1; + u32 curr_perf_state : 4; + u32 hw_clk_control : 1; + u32 dfs_fsm_state : 3; + u32 perf_state_update_status : 1; + u32 sw_override : 1; + u32 sw_perf_state : 4; + u32 rcg_sw_ctrl : 1; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_cmd_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_cmd_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf0_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf0_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf0_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf1_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf1_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf1_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf2_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf2_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf2_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf3_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf3_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf3_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf4_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf4_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf4_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf5_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf5_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf5_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf6_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf6_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf6_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf7_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf7_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf7_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf0_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf0_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf0_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf1_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf1_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf1_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf2_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf2_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf2_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf3_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf3_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf3_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf4_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf4_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf4_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf5_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf5_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf5_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf6_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf6_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf6_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf7_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf7_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf7_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf0_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf0_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf0_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf1_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf1_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf1_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf2_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf2_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf2_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf3_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf3_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf3_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf4_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf4_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf4_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf5_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf5_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf5_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf6_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf6_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf6_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf7_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf7_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se1_qupv3_wrap1_s1_perf7_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S1_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s1_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 dirty_m : 1; + u32 dirty_n : 1; + u32 dirty_d : 1; + u32 reserved1 : 23; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s1_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s1_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S1_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s1_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 6; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s1_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s1_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S1_M +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s1_m_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s1_m_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s1_m_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S1_N +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s1_n_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s1_n_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s1_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S1_D +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s1_d_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s1_d_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s1_d_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S2_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s2_cbcr_s +{ + u32 reserved0 : 2; + u32 clk_ares : 1; + u32 reserved1 : 9; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved2 : 7; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s2_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s2_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S2_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s2_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 4; + u32 pwr_fsm_clk_sel : 1; + u32 reserved1 : 3; + u32 sreg_pscbc_spare_ctrl_out : 4; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s2_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s2_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S2_CFG_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s2_cfg_sregr_s +{ + u32 wakeup_timer : 8; + u32 sleep_timer : 8; + u32 mem_cph_timer : 6; + u32 mem_core_on_status : 1; + u32 mem_periph_on_status : 1; + u32 mem_core_on_ack_status : 1; + u32 mem_periph_on_ack_status : 1; + u32 mem_core_off_timer : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s2_cfg_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s2_cfg_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE2_CMD_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_cmd_dfsr_s +{ + u32 dfs_en : 1; + u32 curr_perf_state : 4; + u32 hw_clk_control : 1; + u32 dfs_fsm_state : 3; + u32 perf_state_update_status : 1; + u32 sw_override : 1; + u32 sw_perf_state : 4; + u32 rcg_sw_ctrl : 1; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_cmd_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_cmd_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf0_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf0_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf0_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf1_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf1_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf1_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf2_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf2_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf2_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf3_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf3_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf3_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf4_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf4_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf4_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf5_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf5_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf5_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf6_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf6_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf6_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf7_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf7_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf7_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf0_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf0_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf0_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf1_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf1_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf1_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf2_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf2_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf2_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf3_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf3_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf3_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf4_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf4_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf4_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf5_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf5_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf5_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf6_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf6_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf6_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf7_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf7_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf7_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf0_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf0_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf0_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf1_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf1_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf1_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf2_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf2_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf2_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf3_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf3_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf3_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf4_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf4_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf4_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf5_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf5_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf5_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf6_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf6_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf6_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf7_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf7_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se2_qupv3_wrap1_s2_perf7_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S2_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s2_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 dirty_m : 1; + u32 dirty_n : 1; + u32 dirty_d : 1; + u32 reserved1 : 23; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s2_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s2_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S2_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s2_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 6; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s2_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s2_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S2_M +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s2_m_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s2_m_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s2_m_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S2_N +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s2_n_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s2_n_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s2_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S2_D +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s2_d_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s2_d_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s2_d_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S3_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s3_cbcr_s +{ + u32 reserved0 : 2; + u32 clk_ares : 1; + u32 reserved1 : 9; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved2 : 7; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s3_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s3_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S3_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s3_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 4; + u32 pwr_fsm_clk_sel : 1; + u32 reserved1 : 3; + u32 sreg_pscbc_spare_ctrl_out : 4; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s3_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s3_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S3_CFG_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s3_cfg_sregr_s +{ + u32 wakeup_timer : 8; + u32 sleep_timer : 8; + u32 mem_cph_timer : 6; + u32 mem_core_on_status : 1; + u32 mem_periph_on_status : 1; + u32 mem_core_on_ack_status : 1; + u32 mem_periph_on_ack_status : 1; + u32 mem_core_off_timer : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s3_cfg_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s3_cfg_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE3_CMD_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_cmd_dfsr_s +{ + u32 dfs_en : 1; + u32 curr_perf_state : 4; + u32 hw_clk_control : 1; + u32 dfs_fsm_state : 3; + u32 perf_state_update_status : 1; + u32 sw_override : 1; + u32 sw_perf_state : 4; + u32 rcg_sw_ctrl : 1; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_cmd_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_cmd_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf0_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf0_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf0_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf1_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf1_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf1_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf2_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf2_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf2_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf3_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf3_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf3_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf4_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf4_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf4_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf5_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf5_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf5_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf6_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf6_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf6_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf7_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf7_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf7_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf0_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf0_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf0_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf1_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf1_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf1_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf2_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf2_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf2_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf3_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf3_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf3_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf4_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf4_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf4_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf5_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf5_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf5_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf6_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf6_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf6_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf7_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf7_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf7_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf0_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf0_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf0_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf1_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf1_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf1_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf2_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf2_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf2_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf3_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf3_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf3_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf4_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf4_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf4_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf5_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf5_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf5_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf6_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf6_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf6_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf7_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf7_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se3_qupv3_wrap1_s3_perf7_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S3_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s3_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 dirty_m : 1; + u32 dirty_n : 1; + u32 dirty_d : 1; + u32 reserved1 : 23; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s3_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s3_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S3_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s3_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 6; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s3_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s3_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S3_M +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s3_m_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s3_m_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s3_m_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S3_N +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s3_n_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s3_n_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s3_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S3_D +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s3_d_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s3_d_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s3_d_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S4_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s4_cbcr_s +{ + u32 reserved0 : 2; + u32 clk_ares : 1; + u32 reserved1 : 9; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved2 : 7; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s4_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s4_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S4_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s4_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 4; + u32 pwr_fsm_clk_sel : 1; + u32 reserved1 : 3; + u32 sreg_pscbc_spare_ctrl_out : 4; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s4_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s4_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S4_CFG_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s4_cfg_sregr_s +{ + u32 wakeup_timer : 8; + u32 sleep_timer : 8; + u32 mem_cph_timer : 6; + u32 mem_core_on_status : 1; + u32 mem_periph_on_status : 1; + u32 mem_core_on_ack_status : 1; + u32 mem_periph_on_ack_status : 1; + u32 mem_core_off_timer : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s4_cfg_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s4_cfg_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE4_CMD_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_cmd_dfsr_s +{ + u32 dfs_en : 1; + u32 curr_perf_state : 4; + u32 hw_clk_control : 1; + u32 dfs_fsm_state : 3; + u32 perf_state_update_status : 1; + u32 sw_override : 1; + u32 sw_perf_state : 4; + u32 rcg_sw_ctrl : 1; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_cmd_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_cmd_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf0_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf0_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf0_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf1_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf1_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf1_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf2_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf2_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf2_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf3_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf3_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf3_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf4_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf4_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf4_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf5_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf5_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf5_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf6_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf6_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf6_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf7_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf7_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf7_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf0_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf0_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf0_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf1_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf1_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf1_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf2_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf2_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf2_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf3_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf3_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf3_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf4_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf4_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf4_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf5_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf5_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf5_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf6_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf6_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf6_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf7_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf7_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf7_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf0_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf0_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf0_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf1_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf1_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf1_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf2_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf2_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf2_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf3_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf3_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf3_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf4_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf4_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf4_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf5_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf5_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf5_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf6_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf6_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf6_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf7_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf7_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se4_qupv3_wrap1_s4_perf7_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S4_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s4_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 dirty_m : 1; + u32 dirty_n : 1; + u32 dirty_d : 1; + u32 reserved1 : 23; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s4_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s4_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S4_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s4_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 6; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s4_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s4_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S4_M +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s4_m_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s4_m_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s4_m_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S4_N +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s4_n_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s4_n_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s4_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S4_D +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s4_d_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s4_d_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s4_d_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S5_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s5_cbcr_s +{ + u32 reserved0 : 2; + u32 clk_ares : 1; + u32 reserved1 : 9; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved2 : 7; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s5_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s5_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S5_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s5_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 4; + u32 pwr_fsm_clk_sel : 1; + u32 reserved1 : 3; + u32 sreg_pscbc_spare_ctrl_out : 4; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s5_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s5_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S5_CFG_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s5_cfg_sregr_s +{ + u32 wakeup_timer : 8; + u32 sleep_timer : 8; + u32 mem_cph_timer : 6; + u32 mem_core_on_status : 1; + u32 mem_periph_on_status : 1; + u32 mem_core_on_ack_status : 1; + u32 mem_periph_on_ack_status : 1; + u32 mem_core_off_timer : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s5_cfg_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s5_cfg_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE5_CMD_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_cmd_dfsr_s +{ + u32 dfs_en : 1; + u32 curr_perf_state : 4; + u32 hw_clk_control : 1; + u32 dfs_fsm_state : 3; + u32 perf_state_update_status : 1; + u32 sw_override : 1; + u32 sw_perf_state : 4; + u32 rcg_sw_ctrl : 1; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_cmd_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_cmd_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf0_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf0_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf0_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf1_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf1_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf1_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf2_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf2_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf2_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf3_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf3_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf3_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf4_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf4_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf4_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf5_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf5_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf5_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf6_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf6_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf6_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf7_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf7_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf7_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf0_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf0_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf0_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf1_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf1_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf1_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf2_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf2_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf2_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf3_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf3_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf3_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf4_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf4_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf4_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf5_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf5_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf5_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf6_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf6_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf6_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf7_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf7_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf7_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf0_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf0_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf0_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf1_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf1_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf1_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf2_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf2_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf2_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf3_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf3_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf3_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf4_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf4_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf4_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf5_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf5_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf5_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf6_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf6_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf6_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf7_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf7_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se5_qupv3_wrap1_s5_perf7_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S5_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s5_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 dirty_m : 1; + u32 dirty_n : 1; + u32 dirty_d : 1; + u32 reserved1 : 23; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s5_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s5_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S5_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s5_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 6; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s5_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s5_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S5_M +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s5_m_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s5_m_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s5_m_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S5_N +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s5_n_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s5_n_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s5_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S5_D +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s5_d_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s5_d_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s5_d_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S6_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s6_cbcr_s +{ + u32 reserved0 : 2; + u32 clk_ares : 1; + u32 reserved1 : 9; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved2 : 7; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s6_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s6_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S6_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s6_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 4; + u32 pwr_fsm_clk_sel : 1; + u32 reserved1 : 3; + u32 sreg_pscbc_spare_ctrl_out : 4; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s6_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s6_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S6_CFG_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s6_cfg_sregr_s +{ + u32 wakeup_timer : 8; + u32 sleep_timer : 8; + u32 mem_cph_timer : 6; + u32 mem_core_on_status : 1; + u32 mem_periph_on_status : 1; + u32 mem_core_on_ack_status : 1; + u32 mem_periph_on_ack_status : 1; + u32 mem_core_off_timer : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s6_cfg_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s6_cfg_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE6_CMD_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_cmd_dfsr_s +{ + u32 dfs_en : 1; + u32 curr_perf_state : 4; + u32 hw_clk_control : 1; + u32 dfs_fsm_state : 3; + u32 perf_state_update_status : 1; + u32 sw_override : 1; + u32 sw_perf_state : 4; + u32 rcg_sw_ctrl : 1; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_cmd_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_cmd_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf0_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf0_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf0_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf1_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf1_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf1_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf2_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf2_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf2_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf3_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf3_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf3_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf4_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf4_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf4_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf5_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf5_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf5_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf6_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf6_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf6_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf7_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf7_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf7_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf0_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf0_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf0_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf1_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf1_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf1_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf2_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf2_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf2_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf3_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf3_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf3_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf4_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf4_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf4_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf5_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf5_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf5_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf6_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf6_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf6_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf7_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf7_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf7_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF0_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf0_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf0_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf0_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF1_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf1_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf1_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf1_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF2_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf2_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf2_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf2_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF3_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf3_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf3_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf3_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF4_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf4_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf4_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf4_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF5_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf5_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf5_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf5_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF6_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf6_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf6_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf6_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE6_QUPV3_WRAP1_S6_PERF7_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf7_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf7_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se6_qupv3_wrap1_s6_perf7_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S6_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s6_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 dirty_m : 1; + u32 dirty_n : 1; + u32 dirty_d : 1; + u32 reserved1 : 23; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s6_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s6_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S6_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s6_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 6; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s6_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s6_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S6_M +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s6_m_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s6_m_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s6_m_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S6_N +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s6_n_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s6_n_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s6_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S6_D +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s6_d_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s6_d_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s6_d_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S7_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s7_cbcr_s +{ + u32 reserved0 : 2; + u32 clk_ares : 1; + u32 reserved1 : 9; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved2 : 7; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s7_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s7_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S7_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s7_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 4; + u32 pwr_fsm_clk_sel : 1; + u32 reserved1 : 3; + u32 sreg_pscbc_spare_ctrl_out : 4; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s7_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s7_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S7_CFG_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s7_cfg_sregr_s +{ + u32 wakeup_timer : 8; + u32 sleep_timer : 8; + u32 mem_cph_timer : 6; + u32 mem_core_on_status : 1; + u32 mem_periph_on_status : 1; + u32 mem_core_on_ack_status : 1; + u32 mem_periph_on_ack_status : 1; + u32 mem_core_off_timer : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s7_cfg_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s7_cfg_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE7_CMD_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_cmd_dfsr_s +{ + u32 dfs_en : 1; + u32 curr_perf_state : 4; + u32 hw_clk_control : 1; + u32 dfs_fsm_state : 3; + u32 perf_state_update_status : 1; + u32 sw_override : 1; + u32 sw_perf_state : 4; + u32 rcg_sw_ctrl : 1; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_cmd_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_cmd_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf0_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf0_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf0_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf1_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf1_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf1_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf2_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf2_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf2_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf3_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf3_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf3_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf4_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf4_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf4_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf5_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf5_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf5_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf6_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf6_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf6_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf7_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf7_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf7_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf0_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf0_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf0_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf1_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf1_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf1_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf2_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf2_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf2_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf3_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf3_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf3_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf4_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf4_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf4_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf5_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf5_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf5_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf6_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf6_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf6_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf7_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf7_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf7_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF0_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf0_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf0_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf0_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF1_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf1_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf1_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf1_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF2_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf2_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf2_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf2_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF3_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf3_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf3_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf3_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF4_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf4_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf4_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf4_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF5_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf5_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf5_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf5_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF6_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf6_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf6_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf6_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_SE7_QUPV3_WRAP1_S7_PERF7_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf7_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf7_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_se7_qupv3_wrap1_s7_perf7_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S7_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s7_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 dirty_m : 1; + u32 dirty_n : 1; + u32 dirty_d : 1; + u32 reserved1 : 23; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s7_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s7_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S7_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s7_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 6; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s7_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s7_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S7_M +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s7_m_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s7_m_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s7_m_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S7_N +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s7_n_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s7_n_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s7_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP1_S7_D +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s7_d_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap1_s7_d_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap1_s7_d_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAPPER_2_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrapper_2_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrapper_2_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrapper_2_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP_2_M_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap_2_m_ahb_cbcr_s +{ + u32 reserved0 : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved1 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap_2_m_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap_2_m_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP_2_S_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap_2_s_ahb_cbcr_s +{ + u32 reserved0 : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved1 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap_2_s_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap_2_s_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_CORE_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_core_cbcr_s +{ + u32 reserved0 : 2; + u32 clk_ares : 1; + u32 reserved1 : 9; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved2 : 5; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved3 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved4 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_core_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_core_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_CORE_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_core_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 4; + u32 pwr_fsm_clk_sel : 1; + u32 reserved1 : 3; + u32 sreg_pscbc_spare_ctrl_out : 4; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_core_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_core_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_CORE_CFG_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_core_cfg_sregr_s +{ + u32 wakeup_timer : 8; + u32 sleep_timer : 8; + u32 mem_cph_timer : 6; + u32 mem_core_on_status : 1; + u32 mem_periph_on_status : 1; + u32 mem_core_on_ack_status : 1; + u32 mem_periph_on_ack_status : 1; + u32 mem_core_off_timer : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_core_cfg_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_core_cfg_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_CORE_DIV_CDIVR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_core_div_cdivr_s +{ + u32 clk_div : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_core_div_cdivr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_core_div_cdivr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_CORE_2X_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_core_2x_cbcr_s +{ + u32 reserved0 : 2; + u32 clk_ares : 1; + u32 reserved1 : 9; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved2 : 5; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved3 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved4 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_core_2x_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_core_2x_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_CORE_2X_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_core_2x_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 4; + u32 pwr_fsm_clk_sel : 1; + u32 reserved1 : 3; + u32 sreg_pscbc_spare_ctrl_out : 4; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_core_2x_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_core_2x_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_CORE_2X_CFG_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_core_2x_cfg_sregr_s +{ + u32 wakeup_timer : 8; + u32 sleep_timer : 8; + u32 mem_cph_timer : 6; + u32 mem_core_on_status : 1; + u32 mem_periph_on_status : 1; + u32 mem_core_on_ack_status : 1; + u32 mem_periph_on_ack_status : 1; + u32 mem_core_off_timer : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_core_2x_cfg_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_core_2x_cfg_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap2_core_2x_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap2_core_2x_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap2_core_2x_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap2_core_2x_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap2_core_2x_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap2_core_2x_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap2_core_2x_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap2_core_2x_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap2_core_2x_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap2_core_2x_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap2_core_2x_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap2_core_2x_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap2_core_2x_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap2_core_2x_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap2_core_2x_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap2_core_2x_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap2_core_2x_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap2_core_2x_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap2_core_2x_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap2_core_2x_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap2_core_2x_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap2_core_2x_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap2_core_2x_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap2_core_2x_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap2_core_2x_perf8_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap2_core_2x_perf8_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap2_core_2x_perf8_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap2_core_2x_perf9_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap2_core_2x_perf9_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap2_core_2x_perf9_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap2_core_2x_perf10_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap2_core_2x_perf10_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap2_core_2x_perf10_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap2_core_2x_perf11_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap2_core_2x_perf11_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap2_core_2x_perf11_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap2_core_2x_perf12_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap2_core_2x_perf12_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap2_core_2x_perf12_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap2_core_2x_perf13_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap2_core_2x_perf13_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap2_core_2x_perf13_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap2_core_2x_perf14_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap2_core_2x_perf14_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap2_core_2x_perf14_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap2_core_2x_perf15_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap2_core_2x_perf15_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_qupv3_wrap2_core_2x_perf15_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_core_2x_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_core_2x_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_core_2x_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_core_2x_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_core_2x_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_core_2x_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S0_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s0_cbcr_s +{ + u32 reserved0 : 2; + u32 clk_ares : 1; + u32 reserved1 : 9; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved2 : 7; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s0_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s0_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S0_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s0_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 4; + u32 pwr_fsm_clk_sel : 1; + u32 reserved1 : 3; + u32 sreg_pscbc_spare_ctrl_out : 4; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s0_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s0_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S0_CFG_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s0_cfg_sregr_s +{ + u32 wakeup_timer : 8; + u32 sleep_timer : 8; + u32 mem_cph_timer : 6; + u32 mem_core_on_status : 1; + u32 mem_periph_on_status : 1; + u32 mem_core_on_ack_status : 1; + u32 mem_periph_on_ack_status : 1; + u32 mem_core_off_timer : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s0_cfg_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s0_cfg_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE0_CMD_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_cmd_dfsr_s +{ + u32 dfs_en : 1; + u32 curr_perf_state : 4; + u32 hw_clk_control : 1; + u32 dfs_fsm_state : 3; + u32 perf_state_update_status : 1; + u32 sw_override : 1; + u32 sw_perf_state : 4; + u32 rcg_sw_ctrl : 1; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_cmd_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_cmd_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf0_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf0_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf0_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf1_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf1_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf1_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf2_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf2_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf2_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf3_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf3_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf3_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf4_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf4_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf4_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf5_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf5_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf5_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf6_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf6_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf6_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf7_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf7_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf7_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf0_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf0_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf0_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf1_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf1_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf1_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf2_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf2_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf2_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf3_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf3_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf3_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf4_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf4_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf4_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf5_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf5_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf5_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf6_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf6_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf6_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf7_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf7_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf7_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf0_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf0_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf0_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf1_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf1_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf1_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf2_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf2_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf2_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf3_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf3_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf3_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf4_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf4_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf4_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf5_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf5_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf5_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf6_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf6_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf6_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf7_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf7_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se0_qupv3_wrap2_s0_perf7_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S0_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s0_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 dirty_m : 1; + u32 dirty_n : 1; + u32 dirty_d : 1; + u32 reserved1 : 23; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s0_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s0_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S0_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s0_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 6; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s0_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s0_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S0_M +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s0_m_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s0_m_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s0_m_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S0_N +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s0_n_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s0_n_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s0_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S0_D +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s0_d_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s0_d_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s0_d_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S1_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s1_cbcr_s +{ + u32 reserved0 : 2; + u32 clk_ares : 1; + u32 reserved1 : 9; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved2 : 7; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s1_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s1_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S1_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s1_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 4; + u32 pwr_fsm_clk_sel : 1; + u32 reserved1 : 3; + u32 sreg_pscbc_spare_ctrl_out : 4; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s1_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s1_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S1_CFG_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s1_cfg_sregr_s +{ + u32 wakeup_timer : 8; + u32 sleep_timer : 8; + u32 mem_cph_timer : 6; + u32 mem_core_on_status : 1; + u32 mem_periph_on_status : 1; + u32 mem_core_on_ack_status : 1; + u32 mem_periph_on_ack_status : 1; + u32 mem_core_off_timer : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s1_cfg_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s1_cfg_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE1_CMD_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_cmd_dfsr_s +{ + u32 dfs_en : 1; + u32 curr_perf_state : 4; + u32 hw_clk_control : 1; + u32 dfs_fsm_state : 3; + u32 perf_state_update_status : 1; + u32 sw_override : 1; + u32 sw_perf_state : 4; + u32 rcg_sw_ctrl : 1; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_cmd_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_cmd_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf0_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf0_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf0_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf1_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf1_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf1_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf2_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf2_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf2_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf3_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf3_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf3_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf4_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf4_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf4_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf5_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf5_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf5_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf6_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf6_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf6_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf7_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf7_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf7_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf0_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf0_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf0_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf1_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf1_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf1_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf2_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf2_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf2_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf3_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf3_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf3_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf4_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf4_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf4_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf5_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf5_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf5_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf6_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf6_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf6_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf7_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf7_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf7_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf0_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf0_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf0_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf1_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf1_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf1_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf2_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf2_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf2_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf3_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf3_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf3_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf4_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf4_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf4_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf5_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf5_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf5_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf6_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf6_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf6_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf7_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf7_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se1_qupv3_wrap2_s1_perf7_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S1_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s1_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 dirty_m : 1; + u32 dirty_n : 1; + u32 dirty_d : 1; + u32 reserved1 : 23; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s1_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s1_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S1_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s1_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 6; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s1_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s1_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S1_M +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s1_m_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s1_m_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s1_m_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S1_N +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s1_n_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s1_n_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s1_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S1_D +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s1_d_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s1_d_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s1_d_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S2_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s2_cbcr_s +{ + u32 reserved0 : 2; + u32 clk_ares : 1; + u32 reserved1 : 9; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved2 : 7; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s2_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s2_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S2_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s2_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 4; + u32 pwr_fsm_clk_sel : 1; + u32 reserved1 : 3; + u32 sreg_pscbc_spare_ctrl_out : 4; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s2_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s2_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S2_CFG_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s2_cfg_sregr_s +{ + u32 wakeup_timer : 8; + u32 sleep_timer : 8; + u32 mem_cph_timer : 6; + u32 mem_core_on_status : 1; + u32 mem_periph_on_status : 1; + u32 mem_core_on_ack_status : 1; + u32 mem_periph_on_ack_status : 1; + u32 mem_core_off_timer : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s2_cfg_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s2_cfg_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE2_CMD_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_cmd_dfsr_s +{ + u32 dfs_en : 1; + u32 curr_perf_state : 4; + u32 hw_clk_control : 1; + u32 dfs_fsm_state : 3; + u32 perf_state_update_status : 1; + u32 sw_override : 1; + u32 sw_perf_state : 4; + u32 rcg_sw_ctrl : 1; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_cmd_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_cmd_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf0_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf0_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf0_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf1_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf1_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf1_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf2_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf2_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf2_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf3_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf3_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf3_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf4_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf4_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf4_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf5_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf5_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf5_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf6_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf6_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf6_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf7_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf7_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf7_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf0_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf0_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf0_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf1_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf1_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf1_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf2_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf2_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf2_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf3_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf3_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf3_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf4_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf4_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf4_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf5_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf5_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf5_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf6_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf6_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf6_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf7_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf7_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf7_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf0_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf0_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf0_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf1_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf1_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf1_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf2_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf2_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf2_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf3_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf3_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf3_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf4_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf4_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf4_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf5_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf5_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf5_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf6_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf6_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf6_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf7_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf7_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se2_qupv3_wrap2_s2_perf7_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S2_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s2_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 dirty_m : 1; + u32 dirty_n : 1; + u32 dirty_d : 1; + u32 reserved1 : 23; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s2_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s2_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S2_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s2_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 6; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s2_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s2_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S2_M +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s2_m_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s2_m_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s2_m_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S2_N +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s2_n_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s2_n_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s2_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S2_D +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s2_d_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s2_d_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s2_d_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S3_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s3_cbcr_s +{ + u32 reserved0 : 2; + u32 clk_ares : 1; + u32 reserved1 : 9; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved2 : 7; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s3_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s3_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S3_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s3_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 4; + u32 pwr_fsm_clk_sel : 1; + u32 reserved1 : 3; + u32 sreg_pscbc_spare_ctrl_out : 4; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s3_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s3_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S3_CFG_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s3_cfg_sregr_s +{ + u32 wakeup_timer : 8; + u32 sleep_timer : 8; + u32 mem_cph_timer : 6; + u32 mem_core_on_status : 1; + u32 mem_periph_on_status : 1; + u32 mem_core_on_ack_status : 1; + u32 mem_periph_on_ack_status : 1; + u32 mem_core_off_timer : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s3_cfg_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s3_cfg_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE3_CMD_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_cmd_dfsr_s +{ + u32 dfs_en : 1; + u32 curr_perf_state : 4; + u32 hw_clk_control : 1; + u32 dfs_fsm_state : 3; + u32 perf_state_update_status : 1; + u32 sw_override : 1; + u32 sw_perf_state : 4; + u32 rcg_sw_ctrl : 1; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_cmd_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_cmd_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf0_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf0_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf0_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf1_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf1_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf1_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf2_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf2_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf2_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf3_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf3_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf3_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf4_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf4_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf4_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf5_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf5_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf5_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf6_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf6_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf6_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf7_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf7_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf7_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf0_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf0_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf0_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf1_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf1_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf1_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf2_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf2_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf2_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf3_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf3_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf3_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf4_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf4_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf4_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf5_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf5_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf5_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf6_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf6_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf6_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf7_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf7_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf7_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf0_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf0_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf0_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf1_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf1_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf1_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf2_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf2_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf2_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf3_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf3_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf3_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf4_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf4_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf4_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf5_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf5_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf5_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf6_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf6_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf6_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf7_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf7_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se3_qupv3_wrap2_s3_perf7_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S3_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s3_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 dirty_m : 1; + u32 dirty_n : 1; + u32 dirty_d : 1; + u32 reserved1 : 23; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s3_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s3_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S3_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s3_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 6; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s3_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s3_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S3_M +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s3_m_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s3_m_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s3_m_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S3_N +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s3_n_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s3_n_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s3_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S3_D +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s3_d_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s3_d_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s3_d_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S4_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s4_cbcr_s +{ + u32 reserved0 : 2; + u32 clk_ares : 1; + u32 reserved1 : 9; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved2 : 7; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s4_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s4_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S4_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s4_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 4; + u32 pwr_fsm_clk_sel : 1; + u32 reserved1 : 3; + u32 sreg_pscbc_spare_ctrl_out : 4; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s4_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s4_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S4_CFG_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s4_cfg_sregr_s +{ + u32 wakeup_timer : 8; + u32 sleep_timer : 8; + u32 mem_cph_timer : 6; + u32 mem_core_on_status : 1; + u32 mem_periph_on_status : 1; + u32 mem_core_on_ack_status : 1; + u32 mem_periph_on_ack_status : 1; + u32 mem_core_off_timer : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s4_cfg_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s4_cfg_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE4_CMD_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_cmd_dfsr_s +{ + u32 dfs_en : 1; + u32 curr_perf_state : 4; + u32 hw_clk_control : 1; + u32 dfs_fsm_state : 3; + u32 perf_state_update_status : 1; + u32 sw_override : 1; + u32 sw_perf_state : 4; + u32 rcg_sw_ctrl : 1; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_cmd_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_cmd_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf0_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf0_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf0_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf1_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf1_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf1_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf2_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf2_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf2_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf3_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf3_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf3_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf4_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf4_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf4_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf5_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf5_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf5_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf6_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf6_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf6_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf7_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf7_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf7_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf0_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf0_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf0_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf1_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf1_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf1_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf2_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf2_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf2_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf3_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf3_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf3_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf4_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf4_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf4_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf5_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf5_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf5_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf6_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf6_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf6_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf7_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf7_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf7_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf0_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf0_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf0_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf1_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf1_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf1_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf2_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf2_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf2_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf3_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf3_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf3_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf4_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf4_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf4_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf5_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf5_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf5_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf6_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf6_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf6_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf7_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf7_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se4_qupv3_wrap2_s4_perf7_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S4_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s4_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 dirty_m : 1; + u32 dirty_n : 1; + u32 dirty_d : 1; + u32 reserved1 : 23; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s4_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s4_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S4_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s4_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 6; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s4_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s4_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S4_M +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s4_m_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s4_m_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s4_m_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S4_N +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s4_n_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s4_n_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s4_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S4_D +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s4_d_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s4_d_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s4_d_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S5_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s5_cbcr_s +{ + u32 reserved0 : 2; + u32 clk_ares : 1; + u32 reserved1 : 9; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved2 : 7; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s5_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s5_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S5_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s5_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 4; + u32 pwr_fsm_clk_sel : 1; + u32 reserved1 : 3; + u32 sreg_pscbc_spare_ctrl_out : 4; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s5_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s5_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S5_CFG_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s5_cfg_sregr_s +{ + u32 wakeup_timer : 8; + u32 sleep_timer : 8; + u32 mem_cph_timer : 6; + u32 mem_core_on_status : 1; + u32 mem_periph_on_status : 1; + u32 mem_core_on_ack_status : 1; + u32 mem_periph_on_ack_status : 1; + u32 mem_core_off_timer : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s5_cfg_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s5_cfg_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE5_CMD_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_cmd_dfsr_s +{ + u32 dfs_en : 1; + u32 curr_perf_state : 4; + u32 hw_clk_control : 1; + u32 dfs_fsm_state : 3; + u32 perf_state_update_status : 1; + u32 sw_override : 1; + u32 sw_perf_state : 4; + u32 rcg_sw_ctrl : 1; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_cmd_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_cmd_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf0_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf0_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf0_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf1_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf1_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf1_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf2_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf2_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf2_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf3_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf3_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf3_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf4_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf4_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf4_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf5_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf5_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf5_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf6_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf6_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf6_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf7_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf7_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf7_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf0_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf0_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf0_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf1_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf1_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf1_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf2_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf2_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf2_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf3_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf3_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf3_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf4_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf4_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf4_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf5_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf5_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf5_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf6_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf6_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf6_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf7_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf7_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf7_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf0_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf0_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf0_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf1_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf1_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf1_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf2_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf2_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf2_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf3_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf3_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf3_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf4_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf4_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf4_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf5_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf5_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf5_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf6_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf6_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf6_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf7_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf7_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se5_qupv3_wrap2_s5_perf7_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S5_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s5_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 dirty_m : 1; + u32 dirty_n : 1; + u32 dirty_d : 1; + u32 reserved1 : 23; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s5_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s5_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S5_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s5_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 6; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s5_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s5_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S5_M +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s5_m_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s5_m_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s5_m_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S5_N +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s5_n_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s5_n_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s5_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S5_D +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s5_d_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s5_d_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s5_d_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S6_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s6_cbcr_s +{ + u32 reserved0 : 2; + u32 clk_ares : 1; + u32 reserved1 : 9; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved2 : 7; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s6_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s6_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S6_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s6_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 4; + u32 pwr_fsm_clk_sel : 1; + u32 reserved1 : 3; + u32 sreg_pscbc_spare_ctrl_out : 4; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s6_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s6_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S6_CFG_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s6_cfg_sregr_s +{ + u32 wakeup_timer : 8; + u32 sleep_timer : 8; + u32 mem_cph_timer : 6; + u32 mem_core_on_status : 1; + u32 mem_periph_on_status : 1; + u32 mem_core_on_ack_status : 1; + u32 mem_periph_on_ack_status : 1; + u32 mem_core_off_timer : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s6_cfg_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s6_cfg_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE6_CMD_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_cmd_dfsr_s +{ + u32 dfs_en : 1; + u32 curr_perf_state : 4; + u32 hw_clk_control : 1; + u32 dfs_fsm_state : 3; + u32 perf_state_update_status : 1; + u32 sw_override : 1; + u32 sw_perf_state : 4; + u32 rcg_sw_ctrl : 1; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_cmd_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_cmd_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf0_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf0_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf0_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf1_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf1_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf1_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf2_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf2_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf2_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf3_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf3_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf3_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf4_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf4_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf4_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf5_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf5_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf5_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf6_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf6_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf6_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf7_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf7_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf7_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf0_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf0_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf0_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf1_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf1_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf1_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf2_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf2_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf2_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf3_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf3_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf3_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf4_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf4_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf4_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf5_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf5_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf5_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf6_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf6_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf6_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf7_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf7_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf7_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF0_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf0_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf0_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf0_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF1_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf1_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf1_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf1_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF2_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf2_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf2_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf2_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF3_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf3_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf3_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf3_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF4_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf4_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf4_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf4_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF5_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf5_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf5_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf5_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF6_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf6_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf6_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf6_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE6_QUPV3_WRAP2_S6_PERF7_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf7_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf7_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se6_qupv3_wrap2_s6_perf7_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S6_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s6_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 dirty_m : 1; + u32 dirty_n : 1; + u32 dirty_d : 1; + u32 reserved1 : 23; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s6_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s6_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S6_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s6_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 6; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s6_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s6_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S6_M +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s6_m_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s6_m_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s6_m_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S6_N +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s6_n_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s6_n_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s6_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S6_D +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s6_d_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s6_d_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s6_d_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S7_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s7_cbcr_s +{ + u32 reserved0 : 2; + u32 clk_ares : 1; + u32 reserved1 : 9; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved2 : 7; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s7_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s7_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S7_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s7_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 4; + u32 pwr_fsm_clk_sel : 1; + u32 reserved1 : 3; + u32 sreg_pscbc_spare_ctrl_out : 4; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s7_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s7_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S7_CFG_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s7_cfg_sregr_s +{ + u32 wakeup_timer : 8; + u32 sleep_timer : 8; + u32 mem_cph_timer : 6; + u32 mem_core_on_status : 1; + u32 mem_periph_on_status : 1; + u32 mem_core_on_ack_status : 1; + u32 mem_periph_on_ack_status : 1; + u32 mem_core_off_timer : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s7_cfg_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s7_cfg_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE7_CMD_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_cmd_dfsr_s +{ + u32 dfs_en : 1; + u32 curr_perf_state : 4; + u32 hw_clk_control : 1; + u32 dfs_fsm_state : 3; + u32 perf_state_update_status : 1; + u32 sw_override : 1; + u32 sw_perf_state : 4; + u32 rcg_sw_ctrl : 1; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_cmd_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_cmd_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf0_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf0_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf0_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf1_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf1_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf1_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf2_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf2_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf2_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf3_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf3_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf3_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf4_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf4_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf4_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf5_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf5_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf5_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf6_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf6_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf6_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_M_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf7_m_dfsr_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf7_m_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf7_m_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf0_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf0_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf0_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf1_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf1_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf1_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf2_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf2_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf2_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf3_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf3_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf3_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf4_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf4_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf4_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf5_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf5_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf5_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf6_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf6_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf6_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_N_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf7_n_dfsr_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf7_n_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf7_n_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF0_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf0_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf0_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf0_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF1_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf1_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf1_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf1_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF2_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf2_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf2_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf2_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF3_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf3_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf3_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf3_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF4_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf4_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf4_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf4_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF5_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf5_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf5_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf5_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF6_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf6_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf6_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf6_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_SE7_QUPV3_WRAP2_S7_PERF7_D_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf7_d_dfsr_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf7_d_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_se7_qupv3_wrap2_s7_perf7_d_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S7_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s7_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 dirty_m : 1; + u32 dirty_n : 1; + u32 dirty_d : 1; + u32 reserved1 : 23; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s7_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s7_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S7_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s7_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 6; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s7_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s7_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S7_M +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s7_m_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s7_m_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s7_m_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S7_N +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s7_n_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s7_n_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s7_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QUPV3_WRAP2_S7_D +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s7_d_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qupv3_wrap2_s7_d_u +{ + struct ipa_gcc_hwio_def_gcc_qupv3_wrap2_s7_d_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PDM_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pdm_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pdm_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_pdm_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PDM_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pdm_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pdm_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_pdm_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PDM_XO4_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pdm_xo4_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pdm_xo4_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_pdm_xo4_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PDM2_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pdm2_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pdm2_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_pdm2_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PDM2_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pdm2_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pdm2_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_pdm2_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PDM2_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pdm2_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pdm2_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_pdm2_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PDM_XO4_DIV_CDIVR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pdm_xo4_div_cdivr_s +{ + u32 clk_div : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pdm_xo4_div_cdivr_u +{ + struct ipa_gcc_hwio_def_gcc_pdm_xo4_div_cdivr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PMU_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pmu_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pmu_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_pmu_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PMU_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pmu_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pmu_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_pmu_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PMU_CORE_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pmu_core_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pmu_core_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_pmu_core_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PMU_CMD_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pmu_cmd_dfsr_s +{ + u32 dfs_en : 1; + u32 curr_perf_state : 4; + u32 hw_clk_control : 1; + u32 dfs_fsm_state : 3; + u32 perf_state_update_status : 1; + u32 sw_override : 1; + u32 sw_perf_state : 4; + u32 rcg_sw_ctrl : 1; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pmu_cmd_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pmu_cmd_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PMU_PMU_CORE_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pmu_pmu_core_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pmu_pmu_core_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pmu_pmu_core_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PMU_PMU_CORE_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pmu_pmu_core_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pmu_pmu_core_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pmu_pmu_core_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PMU_PMU_CORE_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pmu_pmu_core_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pmu_pmu_core_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pmu_pmu_core_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PMU_PMU_CORE_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pmu_pmu_core_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pmu_pmu_core_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pmu_pmu_core_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PMU_PMU_CORE_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pmu_pmu_core_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pmu_pmu_core_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pmu_pmu_core_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PMU_PMU_CORE_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pmu_pmu_core_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pmu_pmu_core_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pmu_pmu_core_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PMU_PMU_CORE_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pmu_pmu_core_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pmu_pmu_core_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pmu_pmu_core_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PMU_PMU_CORE_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pmu_pmu_core_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pmu_pmu_core_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pmu_pmu_core_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PMU_PMU_CORE_PERF8_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pmu_pmu_core_perf8_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pmu_pmu_core_perf8_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pmu_pmu_core_perf8_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PMU_PMU_CORE_PERF9_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pmu_pmu_core_perf9_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pmu_pmu_core_perf9_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pmu_pmu_core_perf9_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PMU_PMU_CORE_PERF10_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pmu_pmu_core_perf10_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pmu_pmu_core_perf10_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pmu_pmu_core_perf10_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PMU_PMU_CORE_PERF11_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pmu_pmu_core_perf11_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pmu_pmu_core_perf11_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pmu_pmu_core_perf11_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PMU_PMU_CORE_PERF12_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pmu_pmu_core_perf12_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pmu_pmu_core_perf12_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pmu_pmu_core_perf12_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PMU_PMU_CORE_PERF13_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pmu_pmu_core_perf13_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pmu_pmu_core_perf13_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pmu_pmu_core_perf13_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PMU_PMU_CORE_PERF14_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pmu_pmu_core_perf14_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pmu_pmu_core_perf14_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pmu_pmu_core_perf14_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PMU_PMU_CORE_PERF15_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pmu_pmu_core_perf15_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pmu_pmu_core_perf15_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pmu_pmu_core_perf15_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PMU_CORE_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pmu_core_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pmu_core_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_pmu_core_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PMU_CORE_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pmu_core_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pmu_core_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_pmu_core_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PRNG_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_prng_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_prng_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_prng_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PRNG_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_prng_ahb_cbcr_s +{ + u32 reserved0 : 2; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_prng_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_prng_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TME_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tme_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tme_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_tme_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TME_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tme_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tme_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_tme_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TME_BOOT_ROM_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tme_boot_rom_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tme_boot_rom_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_tme_boot_rom_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TME_SNOC_QXM_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tme_snoc_qxm_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tme_snoc_qxm_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_tme_snoc_qxm_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TME_TRIG_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tme_trig_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tme_trig_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_tme_trig_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TME_AT_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tme_at_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tme_at_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_tme_at_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TCSR_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tcsr_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tcsr_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_tcsr_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TCSR_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tcsr_ahb_cbcr_s +{ + u32 reserved0 : 2; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tcsr_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_tcsr_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TCSR_ACC_SERIAL_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tcsr_acc_serial_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tcsr_acc_serial_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_tcsr_acc_serial_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MEMRED_P2S_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_memred_p2s_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_memred_p2s_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_memred_p2s_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MEMRED_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_memred_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_memred_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_memred_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MEMRED_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_memred_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_memred_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_memred_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BOOT_ROM_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_boot_rom_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_boot_rom_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_boot_rom_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BOOT_ROM_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_boot_rom_ahb_cbcr_s +{ + u32 reserved0 : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved1 : 8; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved2 : 5; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved3 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved4 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_boot_rom_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_boot_rom_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BOOT_ROM_AHB_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_boot_rom_ahb_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 4; + u32 pwr_fsm_clk_sel : 1; + u32 reserved1 : 3; + u32 sreg_pscbc_spare_ctrl_out : 4; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_boot_rom_ahb_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_boot_rom_ahb_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_BOOT_ROM_AHB_CFG_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_boot_rom_ahb_cfg_sregr_s +{ + u32 wakeup_timer : 8; + u32 sleep_timer : 8; + u32 mem_cph_timer : 6; + u32 mem_core_on_status : 1; + u32 mem_periph_on_status : 1; + u32 mem_core_on_ack_status : 1; + u32 mem_periph_on_ack_status : 1; + u32 mem_core_off_timer : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_boot_rom_ahb_cfg_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_boot_rom_ahb_cfg_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TLMM_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tlmm_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tlmm_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_tlmm_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TLMM_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tlmm_ahb_cbcr_s +{ + u32 reserved0 : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved1 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tlmm_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_tlmm_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TLMM_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tlmm_cbcr_s +{ + u32 reserved0 : 2; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tlmm_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_tlmm_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AOSS_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_aoss_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_aoss_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_aoss_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AOSS_CNOC_M_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_aoss_cnoc_m_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_aoss_cnoc_m_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_aoss_cnoc_m_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AOSS_CNOC_S_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_aoss_cnoc_s_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_aoss_cnoc_s_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_aoss_cnoc_s_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AOSS_AT_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_aoss_at_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_aoss_at_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_aoss_at_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPDM_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spdm_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spdm_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_spdm_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPDM_FF_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spdm_ff_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spdm_ff_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_spdm_ff_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPDM_MEMNOC_CY_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spdm_memnoc_cy_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spdm_memnoc_cy_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_spdm_memnoc_cy_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPDM_SNOC_CY_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spdm_snoc_cy_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spdm_snoc_cy_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_spdm_snoc_cy_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPDM_DEBUG_CY_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spdm_debug_cy_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spdm_debug_cy_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_spdm_debug_cy_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPDM_PNOC_CY_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spdm_pnoc_cy_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spdm_pnoc_cy_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_spdm_pnoc_cy_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPDM_MEMNOC_CY_DIV_CDIVR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spdm_memnoc_cy_div_cdivr_s +{ + u32 clk_div : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spdm_memnoc_cy_div_cdivr_u +{ + struct ipa_gcc_hwio_def_gcc_spdm_memnoc_cy_div_cdivr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPDM_SNOC_CY_DIV_CDIVR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spdm_snoc_cy_div_cdivr_s +{ + u32 clk_div : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spdm_snoc_cy_div_cdivr_u +{ + struct ipa_gcc_hwio_def_gcc_spdm_snoc_cy_div_cdivr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPDM_DEBUG_CY_DIV_CDIVR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spdm_debug_cy_div_cdivr_s +{ + u32 clk_div : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spdm_debug_cy_div_cdivr_u +{ + struct ipa_gcc_hwio_def_gcc_spdm_debug_cy_div_cdivr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CE1_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ce1_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ce1_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_ce1_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CE1_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ce1_cbcr_s +{ + u32 reserved0 : 2; + u32 clk_ares : 1; + u32 reserved1 : 9; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved2 : 5; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved3 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved4 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ce1_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ce1_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CE1_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ce1_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 4; + u32 pwr_fsm_clk_sel : 1; + u32 reserved1 : 3; + u32 sreg_pscbc_spare_ctrl_out : 4; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ce1_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_ce1_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CE1_CFG_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ce1_cfg_sregr_s +{ + u32 wakeup_timer : 8; + u32 sleep_timer : 8; + u32 mem_cph_timer : 6; + u32 mem_core_on_status : 1; + u32 mem_periph_on_status : 1; + u32 mem_core_on_ack_status : 1; + u32 mem_periph_on_ack_status : 1; + u32 mem_core_off_timer : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ce1_cfg_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_ce1_cfg_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CE1_AXI_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ce1_axi_cbcr_s +{ + u32 reserved0 : 2; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ce1_axi_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ce1_axi_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CE1_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ce1_ahb_cbcr_s +{ + u32 reserved0 : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved1 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ce1_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ce1_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_CMD_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_cmd_dfsr_s +{ + u32 dfs_en : 1; + u32 curr_perf_state : 4; + u32 hw_clk_control : 1; + u32 dfs_fsm_state : 3; + u32 perf_state_update_status : 1; + u32 sw_override : 1; + u32 sw_perf_state : 4; + u32 rcg_sw_ctrl : 1; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_cmd_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_cmd_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_CE1_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_CE1_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_CE1_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_CE1_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_CE1_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_CE1_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_CE1_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_CE1_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_CE1_PERF8_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf8_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf8_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf8_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_CE1_PERF9_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf9_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf9_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf9_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_CE1_PERF10_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf10_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf10_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf10_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_CE1_PERF11_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf11_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf11_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf11_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_CE1_PERF12_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf12_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf12_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf12_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_CE1_PERF13_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf13_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf13_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf13_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_CE1_PERF14_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf14_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf14_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf14_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_CE1_PERF15_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf15_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf15_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_ce1_perf15_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CE1_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ce1_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ce1_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_ce1_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CE1_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ce1_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ce1_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_ce1_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AT_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_at_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_at_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_at_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ahb_cbcr_s +{ + u32 reserved0 : 2; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_XO_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_xo_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_xo_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_xo_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_XO_DIV4_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_xo_div4_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_xo_div4_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_xo_div4_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_XO_DIV16_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_xo_div16_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_xo_div16_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_xo_div16_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SLEEP_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sleep_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sleep_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_sleep_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_XO_DIV16_CDIVR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_xo_div16_cdivr_s +{ + u32 clk_div : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_xo_div16_cdivr_u +{ + struct ipa_gcc_hwio_def_gcc_xo_div16_cdivr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_XO_DIV4_CDIVR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_xo_div4_cdivr_s +{ + u32 clk_div : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_xo_div4_cdivr_u +{ + struct ipa_gcc_hwio_def_gcc_xo_div4_cdivr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SLEEP_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sleep_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sleep_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_sleep_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SLEEP_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sleep_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sleep_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_sleep_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_XO_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_xo_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_xo_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_xo_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_XO_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_xo_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_xo_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_xo_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DDRSS_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ddrss_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ddrss_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_ddrss_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DDRSS_MMNOC_SF_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ddrss_mmnoc_sf_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 ignore_pmu_clk_dis : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ddrss_mmnoc_sf_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ddrss_mmnoc_sf_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DDRSS_MMNOC_HF_QX_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ddrss_mmnoc_hf_qx_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 ignore_pmu_clk_dis : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ddrss_mmnoc_hf_qx_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ddrss_mmnoc_hf_qx_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DDRSS_TCU_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ddrss_tcu_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 ignore_pmu_clk_dis : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ddrss_tcu_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ddrss_tcu_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DDRSS_TURING_Q6_AXI_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ddrss_turing_q6_axi_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 ignore_pmu_clk_dis : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ddrss_turing_q6_axi_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ddrss_turing_q6_axi_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DDRSS_MSS_Q6_AXI_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ddrss_mss_q6_axi_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 ignore_pmu_clk_dis : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ddrss_mss_q6_axi_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ddrss_mss_q6_axi_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DDRSS_MODEM_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ddrss_modem_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 ignore_pmu_clk_dis : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ddrss_modem_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ddrss_modem_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DDRSS_GPU_AXI_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ddrss_gpu_axi_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 ignore_pmu_clk_dis : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ddrss_gpu_axi_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ddrss_gpu_axi_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DDRSS_PCIE_SF_QTB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ddrss_pcie_sf_qtb_cbcr_s +{ + u32 reserved0 : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved1 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 ignore_pmu_clk_dis : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ddrss_pcie_sf_qtb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ddrss_pcie_sf_qtb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DDRSS_SNOC_GC_AXI_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ddrss_snoc_gc_axi_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 ignore_pmu_clk_dis : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ddrss_snoc_gc_axi_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ddrss_snoc_gc_axi_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DDRSS_SNOC_SF_AXI_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ddrss_snoc_sf_axi_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 ignore_pmu_clk_dis : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ddrss_snoc_sf_axi_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ddrss_snoc_sf_axi_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DDRSS_CONFIG_NOC_SF_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ddrss_config_noc_sf_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ddrss_config_noc_sf_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ddrss_config_noc_sf_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DDRSS_CFG_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ddrss_cfg_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ddrss_cfg_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ddrss_cfg_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MEMNOC_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_memnoc_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_memnoc_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_memnoc_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DDRSS_LPASS_SHUB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ddrss_lpass_shub_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 ignore_pmu_clk_dis : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ddrss_lpass_shub_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ddrss_lpass_shub_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DDRSS_AT_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ddrss_at_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ddrss_at_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ddrss_at_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SHRM_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_shrm_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_shrm_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_shrm_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DDRSS_PWRCTL_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ddrss_pwrctl_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ddrss_pwrctl_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ddrss_pwrctl_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf8_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf8_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf8_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf9_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf9_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf9_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf10_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf10_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf10_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf11_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf11_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf11_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf12_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf12_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf12_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf13_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf13_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf13_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf14_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf14_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf14_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf15_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf15_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_memnoc_perf15_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MEMNOC_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_memnoc_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_memnoc_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_memnoc_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MEMNOC_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_memnoc_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_memnoc_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_memnoc_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_CMD_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_cmd_dfsr_s +{ + u32 dfs_en : 1; + u32 curr_perf_state : 4; + u32 hw_clk_control : 1; + u32 dfs_fsm_state : 3; + u32 perf_state_update_status : 1; + u32 sw_override : 1; + u32 sw_perf_state : 4; + u32 rcg_sw_ctrl : 1; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_cmd_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_cmd_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_SHRM_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_SHRM_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_SHRM_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_SHRM_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_SHRM_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_SHRM_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_SHRM_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_SHRM_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_SHRM_PERF8_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf8_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf8_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf8_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_SHRM_PERF9_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf9_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf9_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf9_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_SHRM_PERF10_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf10_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf10_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf10_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_SHRM_PERF11_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf11_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf11_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf11_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_SHRM_PERF12_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf12_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf12_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf12_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_SHRM_PERF13_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf13_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf13_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf13_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_SHRM_PERF14_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf14_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf14_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf14_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_SHRM_PERF15_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf15_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf15_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_shrm_perf15_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SHRM_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_shrm_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_shrm_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_shrm_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SHRM_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_shrm_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_shrm_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_shrm_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SHRM_DCD_CDIV_DCDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_shrm_dcd_cdiv_dcdr_s +{ + u32 dcd_enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_shrm_dcd_cdiv_dcdr_u +{ + struct ipa_gcc_hwio_def_gcc_shrm_dcd_cdiv_dcdr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MEMNOC_DCD_CDIV_DCDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_memnoc_dcd_cdiv_dcdr_s +{ + u32 dcd_enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_memnoc_dcd_cdiv_dcdr_u +{ + struct ipa_gcc_hwio_def_gcc_memnoc_dcd_cdiv_dcdr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DDRSS_GPLL0_MAIN_DIV_CDIVR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ddrss_gpll0_main_div_cdivr_s +{ + u32 clk_div : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ddrss_gpll0_main_div_cdivr_u +{ + struct ipa_gcc_hwio_def_gcc_ddrss_gpll0_main_div_cdivr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_LPASS_CFG_NOC_SWAY_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_lpass_cfg_noc_sway_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_lpass_cfg_noc_sway_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_lpass_cfg_noc_sway_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QMIP_LPASS_QTB_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qmip_lpass_qtb_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qmip_lpass_qtb_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qmip_lpass_qtb_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_LPASS_TRIG_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_lpass_trig_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_lpass_trig_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_lpass_trig_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_LPASS_AT_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_lpass_at_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_lpass_at_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_lpass_at_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_LPASS_AON_NOC_DDRSS_SHUB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_lpass_aon_noc_ddrss_shub_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 ignore_pmu_clk_dis : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_lpass_aon_noc_ddrss_shub_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_lpass_aon_noc_ddrss_shub_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_LPASS_AGGRE_NOC_MPU_CLIENT_DDRSS_SHUB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_lpass_aggre_noc_mpu_client_ddrss_shub_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 ignore_pmu_clk_dis : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_lpass_aggre_noc_mpu_client_ddrss_shub_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_lpass_aggre_noc_mpu_client_ddrss_shub_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_lpass_hw_af_noc_ddrss_shub_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 8; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved1 : 5; + u32 ignore_rpmh_clk_dis : 1; + u32 ignore_pmu_clk_dis : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_lpass_hw_af_noc_ddrss_shub_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_lpass_hw_af_noc_ddrss_shub_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_lpass_hw_af_noc_ddrss_shub_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 4; + u32 pwr_fsm_clk_sel : 1; + u32 reserved1 : 3; + u32 sreg_pscbc_spare_ctrl_out : 4; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_lpass_hw_af_noc_ddrss_shub_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_lpass_hw_af_noc_ddrss_shub_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_LPASS_HW_AF_NOC_DDRSS_SHUB_CFG_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_lpass_hw_af_noc_ddrss_shub_cfg_sregr_s +{ + u32 wakeup_timer : 8; + u32 sleep_timer : 8; + u32 mem_cph_timer : 6; + u32 mem_core_on_status : 1; + u32 mem_periph_on_status : 1; + u32 mem_core_on_ack_status : 1; + u32 mem_periph_on_ack_status : 1; + u32 mem_core_off_timer : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_lpass_hw_af_noc_ddrss_shub_cfg_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_lpass_hw_af_noc_ddrss_shub_cfg_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_LPASS_AGGRE_NOC_DDRSS_SHUB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_lpass_aggre_noc_ddrss_shub_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 ignore_pmu_clk_dis : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_lpass_aggre_noc_ddrss_shub_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_lpass_aggre_noc_ddrss_shub_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_LPASS_DCD_CDIV_DCDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_lpass_dcd_cdiv_dcdr_s +{ + u32 dcd_enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_lpass_dcd_cdiv_dcdr_u +{ + struct ipa_gcc_hwio_def_gcc_lpass_dcd_cdiv_dcdr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_lpass_ddrss_shub_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_lpass_ddrss_shub_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_lpass_ddrss_shub_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_lpass_ddrss_shub_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_lpass_ddrss_shub_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_lpass_ddrss_shub_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_lpass_ddrss_shub_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_lpass_ddrss_shub_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_lpass_ddrss_shub_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_lpass_ddrss_shub_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_lpass_ddrss_shub_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_lpass_ddrss_shub_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_lpass_ddrss_shub_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_lpass_ddrss_shub_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_lpass_ddrss_shub_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_lpass_ddrss_shub_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_lpass_ddrss_shub_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_lpass_ddrss_shub_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_lpass_ddrss_shub_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_lpass_ddrss_shub_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_lpass_ddrss_shub_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_lpass_ddrss_shub_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_lpass_ddrss_shub_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_lpass_ddrss_shub_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF8_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_lpass_ddrss_shub_perf8_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_lpass_ddrss_shub_perf8_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_lpass_ddrss_shub_perf8_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF9_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_lpass_ddrss_shub_perf9_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_lpass_ddrss_shub_perf9_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_lpass_ddrss_shub_perf9_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF10_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_lpass_ddrss_shub_perf10_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_lpass_ddrss_shub_perf10_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_lpass_ddrss_shub_perf10_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF11_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_lpass_ddrss_shub_perf11_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_lpass_ddrss_shub_perf11_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_lpass_ddrss_shub_perf11_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF12_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_lpass_ddrss_shub_perf12_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_lpass_ddrss_shub_perf12_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_lpass_ddrss_shub_perf12_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF13_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_lpass_ddrss_shub_perf13_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_lpass_ddrss_shub_perf13_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_lpass_ddrss_shub_perf13_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF14_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_lpass_ddrss_shub_perf14_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_lpass_ddrss_shub_perf14_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_lpass_ddrss_shub_perf14_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_LPASS_DDRSS_SHUB_PERF15_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_lpass_ddrss_shub_perf15_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_lpass_ddrss_shub_perf15_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_lpass_ddrss_shub_perf15_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_LPASS_DDRSS_SHUB_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_lpass_ddrss_shub_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_lpass_ddrss_shub_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_lpass_ddrss_shub_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_LPASS_DDRSS_SHUB_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_lpass_ddrss_shub_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_lpass_ddrss_shub_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_lpass_ddrss_shub_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_LPASS_QTB_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_lpass_qtb_gdscr_s +{ + u32 sw_collapse : 1; + u32 hw_control : 1; + u32 sw_override : 1; + u32 pd_ares : 1; + u32 clk_disable : 1; + u32 clamp_io : 1; + u32 en_few : 1; + u32 en_rest : 1; + u32 retain : 1; + u32 save : 1; + u32 restore : 1; + u32 retain_ff_enable : 1; + u32 clk_dis_wait : 4; + u32 en_few_wait : 4; + u32 en_rest_wait : 4; + u32 reserved0 : 3; + u32 gdsc_state : 4; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_lpass_qtb_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_lpass_qtb_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_LPASS_QTB_CFG_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_lpass_qtb_cfg_gdscr_s +{ + u32 disable_clk_software_override : 1; + u32 clamp_io_software_override : 1; + u32 save_restore_software_override : 1; + u32 unclamp_io_software_override : 1; + u32 gdsc_pscbc_pwr_dwn_sw : 1; + u32 gdsc_phase_reset_delay_count_sw : 2; + u32 gdsc_phase_reset_en_sw : 1; + u32 gdsc_mem_core_force_in_sw : 1; + u32 gdsc_mem_peri_force_in_sw : 1; + u32 gdsc_handshake_dis : 1; + u32 software_control_override : 4; + u32 gdsc_power_down_complete : 1; + u32 gdsc_power_up_complete : 1; + u32 gdsc_enf_ack_status : 1; + u32 gdsc_enr_ack_status : 1; + u32 gdsc_mem_pwr_ack_status : 1; + u32 gdsc_cfg_fsm_state_status : 4; + u32 gdsc_pwr_up_start : 1; + u32 gdsc_pwr_dwn_start : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 5; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_lpass_qtb_cfg_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_lpass_qtb_cfg_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_LPASS_QTB_CFG2_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_lpass_qtb_cfg2_gdscr_s +{ + u32 mem_pwr_dwn_timeout : 4; + u32 dly_assert_clamp_mem : 4; + u32 dly_deassert_clamp_mem : 4; + u32 dly_mem_pwr_up : 4; + u32 gdsc_clamp_mem_sw : 1; + u32 gdsc_pwrdwn_enable_ack_override : 1; + u32 gdsc_mem_pwrup_ack_override : 1; + u32 reserved0 : 13; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_lpass_qtb_cfg2_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_lpass_qtb_cfg2_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_LPASS_QTB_CFG3_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_lpass_qtb_cfg3_gdscr_s +{ + u32 gdsc_spare_ctrl_out : 8; + u32 gdsc_spare_ctrl_in : 8; + u32 gdsc_accu_red_sw_override : 1; + u32 gdsc_accu_red_shifter_start_sw : 1; + u32 gdsc_accu_red_shifter_clk_en_sw : 1; + u32 gdsc_accu_red_shifter_done_override : 1; + u32 gdsc_accu_red_timer_en_sw : 1; + u32 dly_accu_red_shifter_done : 4; + u32 gdsc_accu_red_enable : 1; + u32 gdsc_accu_red_shifter_done_status : 1; + u32 reserved0 : 5; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_lpass_qtb_cfg3_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_lpass_qtb_cfg3_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_LPASS_QTB_CFG4_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_lpass_qtb_cfg4_gdscr_s +{ + u32 dly_retainff : 4; + u32 dly_clampio : 4; + u32 dly_deassertares : 4; + u32 dly_noretainff : 4; + u32 dly_restoreff : 4; + u32 dly_unclampio : 4; + u32 reserved0 : 8; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_lpass_qtb_cfg4_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_lpass_qtb_cfg4_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_LPASS_QTB_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_lpass_qtb_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_lpass_qtb_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_lpass_qtb_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_LPASS_AUDIO_QTB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_lpass_audio_qtb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 8; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved1 : 5; + u32 ignore_rpmh_clk_dis : 1; + u32 ignore_pmu_clk_dis : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_lpass_audio_qtb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_lpass_audio_qtb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_LPASS_AUDIO_QTB_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_lpass_audio_qtb_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 4; + u32 pwr_fsm_clk_sel : 1; + u32 reserved1 : 3; + u32 sreg_pscbc_spare_ctrl_out : 4; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_lpass_audio_qtb_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_lpass_audio_qtb_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_LPASS_AUDIO_QTB_CFG_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_lpass_audio_qtb_cfg_sregr_s +{ + u32 wakeup_timer : 8; + u32 sleep_timer : 8; + u32 mem_cph_timer : 6; + u32 mem_core_on_status : 1; + u32 mem_periph_on_status : 1; + u32 mem_core_on_ack_status : 1; + u32 mem_periph_on_ack_status : 1; + u32 mem_core_off_timer : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_lpass_audio_qtb_cfg_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_lpass_audio_qtb_cfg_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_LPASS_QOSGEN_EXTREF_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_lpass_qosgen_extref_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_lpass_qosgen_extref_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_lpass_qosgen_extref_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_LPASS_QDSS_TSCTR_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_lpass_qdss_tsctr_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_lpass_qdss_tsctr_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_lpass_qdss_tsctr_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_LPASS_QTB_AT_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_lpass_qtb_at_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_lpass_qtb_at_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_lpass_qtb_at_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_LPASS_XO_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_lpass_xo_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_lpass_xo_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_lpass_xo_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_LPASS_PWRCTL_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_lpass_pwrctl_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_lpass_pwrctl_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_lpass_pwrctl_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TURING_QTB_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_turing_qtb_gdscr_s +{ + u32 sw_collapse : 1; + u32 hw_control : 1; + u32 sw_override : 1; + u32 pd_ares : 1; + u32 clk_disable : 1; + u32 clamp_io : 1; + u32 en_few : 1; + u32 en_rest : 1; + u32 retain : 1; + u32 save : 1; + u32 restore : 1; + u32 retain_ff_enable : 1; + u32 clk_dis_wait : 4; + u32 en_few_wait : 4; + u32 en_rest_wait : 4; + u32 reserved0 : 3; + u32 gdsc_state : 4; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_turing_qtb_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_turing_qtb_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TURING_QTB_CFG_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_turing_qtb_cfg_gdscr_s +{ + u32 disable_clk_software_override : 1; + u32 clamp_io_software_override : 1; + u32 save_restore_software_override : 1; + u32 unclamp_io_software_override : 1; + u32 gdsc_pscbc_pwr_dwn_sw : 1; + u32 gdsc_phase_reset_delay_count_sw : 2; + u32 gdsc_phase_reset_en_sw : 1; + u32 gdsc_mem_core_force_in_sw : 1; + u32 gdsc_mem_peri_force_in_sw : 1; + u32 gdsc_handshake_dis : 1; + u32 software_control_override : 4; + u32 gdsc_power_down_complete : 1; + u32 gdsc_power_up_complete : 1; + u32 gdsc_enf_ack_status : 1; + u32 gdsc_enr_ack_status : 1; + u32 gdsc_mem_pwr_ack_status : 1; + u32 gdsc_cfg_fsm_state_status : 4; + u32 gdsc_pwr_up_start : 1; + u32 gdsc_pwr_dwn_start : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 5; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_turing_qtb_cfg_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_turing_qtb_cfg_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TURING_QTB_CFG2_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_turing_qtb_cfg2_gdscr_s +{ + u32 mem_pwr_dwn_timeout : 4; + u32 dly_assert_clamp_mem : 4; + u32 dly_deassert_clamp_mem : 4; + u32 dly_mem_pwr_up : 4; + u32 gdsc_clamp_mem_sw : 1; + u32 gdsc_pwrdwn_enable_ack_override : 1; + u32 gdsc_mem_pwrup_ack_override : 1; + u32 reserved0 : 13; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_turing_qtb_cfg2_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_turing_qtb_cfg2_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TURING_QTB_CFG3_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_turing_qtb_cfg3_gdscr_s +{ + u32 gdsc_spare_ctrl_out : 8; + u32 gdsc_spare_ctrl_in : 8; + u32 gdsc_accu_red_sw_override : 1; + u32 gdsc_accu_red_shifter_start_sw : 1; + u32 gdsc_accu_red_shifter_clk_en_sw : 1; + u32 gdsc_accu_red_shifter_done_override : 1; + u32 gdsc_accu_red_timer_en_sw : 1; + u32 dly_accu_red_shifter_done : 4; + u32 gdsc_accu_red_enable : 1; + u32 gdsc_accu_red_shifter_done_status : 1; + u32 reserved0 : 5; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_turing_qtb_cfg3_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_turing_qtb_cfg3_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TURING_QTB_CFG4_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_turing_qtb_cfg4_gdscr_s +{ + u32 dly_retainff : 4; + u32 dly_clampio : 4; + u32 dly_deassertares : 4; + u32 dly_noretainff : 4; + u32 dly_restoreff : 4; + u32 dly_unclampio : 4; + u32 reserved0 : 8; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_turing_qtb_cfg4_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_turing_qtb_cfg4_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TURING_Q6_QTB0_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_turing_q6_qtb0_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 8; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved1 : 5; + u32 ignore_rpmh_clk_dis : 1; + u32 ignore_pmu_clk_dis : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_turing_q6_qtb0_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_turing_q6_qtb0_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TURING_Q6_QTB0_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_turing_q6_qtb0_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 4; + u32 pwr_fsm_clk_sel : 1; + u32 reserved1 : 3; + u32 sreg_pscbc_spare_ctrl_out : 4; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_turing_q6_qtb0_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_turing_q6_qtb0_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TURING_Q6_QTB0_CFG_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_turing_q6_qtb0_cfg_sregr_s +{ + u32 wakeup_timer : 8; + u32 sleep_timer : 8; + u32 mem_cph_timer : 6; + u32 mem_core_on_status : 1; + u32 mem_periph_on_status : 1; + u32 mem_core_on_ack_status : 1; + u32 mem_periph_on_ack_status : 1; + u32 mem_core_off_timer : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_turing_q6_qtb0_cfg_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_turing_q6_qtb0_cfg_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TURING_NSP_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_turing_nsp_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_turing_nsp_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_turing_nsp_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_NSP_QOSGEN_EXTREF_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_nsp_qosgen_extref_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_nsp_qosgen_extref_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_nsp_qosgen_extref_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_NSP_QDSS_TSCTR_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_nsp_qdss_tsctr_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_nsp_qdss_tsctr_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_nsp_qdss_tsctr_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TURING_QTB_AT_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_turing_qtb_at_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_turing_qtb_at_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_turing_qtb_at_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TURING_XO_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_turing_xo_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_turing_xo_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_turing_xo_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TURING_PWRCTL_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_turing_pwrctl_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_turing_pwrctl_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_turing_pwrctl_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TURING_MMNOC_SF_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_turing_mmnoc_sf_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 ignore_pmu_clk_dis : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_turing_mmnoc_sf_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_turing_mmnoc_sf_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TURING_Q6_AXI_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_turing_q6_axi_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 ignore_pmu_clk_dis : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_turing_q6_axi_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_turing_q6_axi_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TURING_CFG_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_turing_cfg_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_turing_cfg_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_turing_cfg_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TURING_AT_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_turing_at_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_turing_at_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_turing_at_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QMIP_TURING_NSP_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qmip_turing_nsp_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qmip_turing_nsp_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qmip_turing_nsp_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TURING_TRIG_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_turing_trig_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_turing_trig_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_turing_trig_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CDSP_NOC_CMD_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_cmd_dfsr_s +{ + u32 dfs_en : 1; + u32 curr_perf_state : 4; + u32 hw_clk_control : 1; + u32 dfs_fsm_state : 3; + u32 perf_state_update_status : 1; + u32 sw_override : 1; + u32 sw_perf_state : 4; + u32 rcg_sw_ctrl : 1; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_cmd_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_cmd_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_turing_q6_axi_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_turing_q6_axi_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_turing_q6_axi_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_turing_q6_axi_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_turing_q6_axi_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_turing_q6_axi_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_turing_q6_axi_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_turing_q6_axi_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_turing_q6_axi_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_turing_q6_axi_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_turing_q6_axi_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_turing_q6_axi_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_turing_q6_axi_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_turing_q6_axi_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_turing_q6_axi_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_turing_q6_axi_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_turing_q6_axi_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_turing_q6_axi_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_turing_q6_axi_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_turing_q6_axi_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_turing_q6_axi_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_turing_q6_axi_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_turing_q6_axi_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_turing_q6_axi_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_turing_q6_axi_perf8_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_turing_q6_axi_perf8_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_turing_q6_axi_perf8_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_turing_q6_axi_perf9_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_turing_q6_axi_perf9_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_turing_q6_axi_perf9_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_turing_q6_axi_perf10_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_turing_q6_axi_perf10_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_turing_q6_axi_perf10_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_turing_q6_axi_perf11_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_turing_q6_axi_perf11_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_turing_q6_axi_perf11_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_turing_q6_axi_perf12_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_turing_q6_axi_perf12_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_turing_q6_axi_perf12_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_turing_q6_axi_perf13_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_turing_q6_axi_perf13_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_turing_q6_axi_perf13_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_turing_q6_axi_perf14_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_turing_q6_axi_perf14_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_turing_q6_axi_perf14_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_turing_q6_axi_perf15_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_turing_q6_axi_perf15_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_turing_q6_axi_perf15_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TURING_Q6_AXI_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_turing_q6_axi_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_turing_q6_axi_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_turing_q6_axi_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TURING_Q6_AXI_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_turing_q6_axi_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_turing_q6_axi_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_turing_q6_axi_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TURING_Q6_AXI_DCD_CDIV_DCDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_turing_q6_axi_dcd_cdiv_dcdr_s +{ + u32 dcd_enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_turing_q6_axi_dcd_cdiv_dcdr_u +{ + struct ipa_gcc_hwio_def_gcc_turing_q6_axi_dcd_cdiv_dcdr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CPUSS_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cpuss_ahb_cbcr_s +{ + u32 reserved0 : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved1 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cpuss_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_cpuss_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CPUSS_TRIG_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cpuss_trig_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cpuss_trig_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_cpuss_trig_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CPUSS_AT_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cpuss_at_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cpuss_at_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_cpuss_at_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CPUSS_CONFIG_NOC_SF_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cpuss_config_noc_sf_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cpuss_config_noc_sf_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_cpuss_config_noc_sf_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CPUSS_AHB_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cpuss_ahb_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cpuss_ahb_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_cpuss_ahb_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CPUSS_AHB_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cpuss_ahb_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cpuss_ahb_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_cpuss_ahb_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CPUSS_AHB_POSTDIV_CDIVR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cpuss_ahb_postdiv_cdivr_s +{ + u32 clk_div : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cpuss_ahb_postdiv_cdivr_u +{ + struct ipa_gcc_hwio_def_gcc_cpuss_ahb_postdiv_cdivr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_cpuss_axi_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_cpuss_axi_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_cpuss_axi_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_cpuss_axi_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_cpuss_axi_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_cpuss_axi_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_cpuss_axi_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_cpuss_axi_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_cpuss_axi_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_cpuss_axi_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_cpuss_axi_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_cpuss_axi_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_cpuss_axi_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_cpuss_axi_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_cpuss_axi_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_cpuss_axi_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_cpuss_axi_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_cpuss_axi_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_cpuss_axi_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_cpuss_axi_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_cpuss_axi_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_cpuss_axi_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_cpuss_axi_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_cpuss_axi_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_cpuss_axi_perf8_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_cpuss_axi_perf8_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_cpuss_axi_perf8_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_cpuss_axi_perf9_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_cpuss_axi_perf9_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_cpuss_axi_perf9_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_cpuss_axi_perf10_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_cpuss_axi_perf10_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_cpuss_axi_perf10_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_cpuss_axi_perf11_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_cpuss_axi_perf11_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_cpuss_axi_perf11_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_cpuss_axi_perf12_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_cpuss_axi_perf12_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_cpuss_axi_perf12_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_cpuss_axi_perf13_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_cpuss_axi_perf13_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_cpuss_axi_perf13_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_cpuss_axi_perf14_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_cpuss_axi_perf14_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_cpuss_axi_perf14_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_cpuss_axi_perf15_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_cpuss_axi_perf15_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_cpuss_axi_perf15_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CPUSS_AXI_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cpuss_axi_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cpuss_axi_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_cpuss_axi_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CPUSS_AXI_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cpuss_axi_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cpuss_axi_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_cpuss_axi_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CPUSS_GPLL0_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cpuss_gpll0_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cpuss_gpll0_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_cpuss_gpll0_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CPUSS_GPLL0_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cpuss_gpll0_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cpuss_gpll0_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_cpuss_gpll0_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CPUSS_AXI_DCD_CDIV_DCDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cpuss_axi_dcd_cdiv_dcdr_s +{ + u32 dcd_enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cpuss_axi_dcd_cdiv_dcdr_u +{ + struct ipa_gcc_hwio_def_gcc_cpuss_axi_dcd_cdiv_dcdr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_APSS_QDSS_TSCTR_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_apss_qdss_tsctr_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_apss_qdss_tsctr_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_apss_qdss_tsctr_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_APSS_QDSS_APB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_apss_qdss_apb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_apss_qdss_apb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_apss_qdss_apb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_NOC_BUS_TIMEOUT_EXTREF_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_noc_bus_timeout_extref_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_noc_bus_timeout_extref_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_noc_bus_timeout_extref_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_noc_bus_timeout_extref_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_noc_bus_timeout_extref_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_noc_bus_timeout_extref_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_NOC_BUS_TIMEOUT_EXTREF_DIV_CDIVR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_noc_bus_timeout_extref_div_cdivr_s +{ + u32 clk_div : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_noc_bus_timeout_extref_div_cdivr_u +{ + struct ipa_gcc_hwio_def_gcc_noc_bus_timeout_extref_div_cdivr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QOSGEN_EXTREF_DIV_CDIVR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qosgen_extref_div_cdivr_s +{ + u32 clk_div : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qosgen_extref_div_cdivr_u +{ + struct ipa_gcc_hwio_def_gcc_qosgen_extref_div_cdivr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_NOC_BUS_TIMEOUT_EXTREF_DIV512_CDIVR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_noc_bus_timeout_extref_div512_cdivr_s +{ + u32 clk_div : 9; + u32 reserved0 : 23; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_noc_bus_timeout_extref_div512_cdivr_u +{ + struct ipa_gcc_hwio_def_gcc_noc_bus_timeout_extref_div512_cdivr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_APB2JTAG_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_apb2jtag_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_apb2jtag_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_apb2jtag_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RBCPR_CX_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rbcpr_cx_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rbcpr_cx_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_rbcpr_cx_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RBCPR_CX_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rbcpr_cx_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rbcpr_cx_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_rbcpr_cx_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RBCPR_CX_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rbcpr_cx_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rbcpr_cx_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_rbcpr_cx_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RBCPR_CX_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rbcpr_cx_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rbcpr_cx_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_rbcpr_cx_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RBCPR_CX_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rbcpr_cx_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rbcpr_cx_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_rbcpr_cx_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RBCPR_MXC_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rbcpr_mxc_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rbcpr_mxc_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_rbcpr_mxc_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RBCPR_MXC_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rbcpr_mxc_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rbcpr_mxc_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_rbcpr_mxc_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RBCPR_MXC_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rbcpr_mxc_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rbcpr_mxc_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_rbcpr_mxc_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RBCPR_MXC_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rbcpr_mxc_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rbcpr_mxc_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_rbcpr_mxc_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RBCPR_MXC_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rbcpr_mxc_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rbcpr_mxc_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_rbcpr_mxc_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RBCPR_MXA_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rbcpr_mxa_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rbcpr_mxa_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_rbcpr_mxa_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RBCPR_MXA_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rbcpr_mxa_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rbcpr_mxa_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_rbcpr_mxa_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RBCPR_MXA_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rbcpr_mxa_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rbcpr_mxa_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_rbcpr_mxa_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RBCPR_MXA_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rbcpr_mxa_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rbcpr_mxa_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_rbcpr_mxa_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RBCPR_MXA_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rbcpr_mxa_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rbcpr_mxa_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_rbcpr_mxa_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RBCPR_NSP_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rbcpr_nsp_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rbcpr_nsp_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_rbcpr_nsp_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RBCPR_NSP_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rbcpr_nsp_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rbcpr_nsp_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_rbcpr_nsp_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RBCPR_NSP_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rbcpr_nsp_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rbcpr_nsp_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_rbcpr_nsp_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RBCPR_NSP_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rbcpr_nsp_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rbcpr_nsp_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_rbcpr_nsp_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RBCPR_NSP_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rbcpr_nsp_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rbcpr_nsp_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_rbcpr_nsp_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DEBUG_DIV_CDIVR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_debug_div_cdivr_s +{ + u32 clk_div : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_debug_div_cdivr_u +{ + struct ipa_gcc_hwio_def_gcc_debug_div_cdivr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DEBUG_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_debug_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_debug_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_debug_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_FRQ_MEASURE_REF_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_frq_measure_ref_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_frq_measure_ref_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_frq_measure_ref_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PLL_TEST_DIV_CDIVR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pll_test_div_cdivr_s +{ + u32 clk_div : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pll_test_div_cdivr_u +{ + struct ipa_gcc_hwio_def_gcc_pll_test_div_cdivr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PLL_TEST_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pll_test_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pll_test_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_pll_test_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GP1_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gp1_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gp1_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_gp1_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GP1_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gp1_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 dirty_m : 1; + u32 dirty_n : 1; + u32 dirty_d : 1; + u32 reserved1 : 23; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gp1_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_gp1_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GP1_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gp1_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 6; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gp1_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_gp1_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GP1_M +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gp1_m_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gp1_m_u +{ + struct ipa_gcc_hwio_def_gcc_gp1_m_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GP1_N +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gp1_n_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gp1_n_u +{ + struct ipa_gcc_hwio_def_gcc_gp1_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GP1_D +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gp1_d_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gp1_d_u +{ + struct ipa_gcc_hwio_def_gcc_gp1_d_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GP2_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gp2_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gp2_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_gp2_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GP2_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gp2_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 dirty_m : 1; + u32 dirty_n : 1; + u32 dirty_d : 1; + u32 reserved1 : 23; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gp2_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_gp2_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GP2_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gp2_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 6; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gp2_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_gp2_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GP2_M +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gp2_m_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gp2_m_u +{ + struct ipa_gcc_hwio_def_gcc_gp2_m_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GP2_N +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gp2_n_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gp2_n_u +{ + struct ipa_gcc_hwio_def_gcc_gp2_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GP2_D +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gp2_d_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gp2_d_u +{ + struct ipa_gcc_hwio_def_gcc_gp2_d_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GP3_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gp3_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gp3_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_gp3_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GP3_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gp3_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 dirty_m : 1; + u32 dirty_n : 1; + u32 dirty_d : 1; + u32 reserved1 : 23; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gp3_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_gp3_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GP3_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gp3_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 6; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gp3_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_gp3_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GP3_M +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gp3_m_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gp3_m_u +{ + struct ipa_gcc_hwio_def_gcc_gp3_m_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GP3_N +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gp3_n_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gp3_n_u +{ + struct ipa_gcc_hwio_def_gcc_gp3_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GP3_D +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gp3_d_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gp3_d_u +{ + struct ipa_gcc_hwio_def_gcc_gp3_d_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_0_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_0_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_0_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_0_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_0_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_0_gdscr_s +{ + u32 sw_collapse : 1; + u32 hw_control : 1; + u32 sw_override : 1; + u32 pd_ares : 1; + u32 clk_disable : 1; + u32 clamp_io : 1; + u32 en_few : 1; + u32 en_rest : 1; + u32 retain : 1; + u32 save : 1; + u32 restore : 1; + u32 retain_ff_enable : 1; + u32 clk_dis_wait : 4; + u32 en_few_wait : 4; + u32 en_rest_wait : 4; + u32 reserved0 : 3; + u32 gdsc_state : 4; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_0_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_0_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_0_CFG_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_0_cfg_gdscr_s +{ + u32 disable_clk_software_override : 1; + u32 clamp_io_software_override : 1; + u32 save_restore_software_override : 1; + u32 unclamp_io_software_override : 1; + u32 gdsc_pscbc_pwr_dwn_sw : 1; + u32 gdsc_phase_reset_delay_count_sw : 2; + u32 gdsc_phase_reset_en_sw : 1; + u32 gdsc_mem_core_force_in_sw : 1; + u32 gdsc_mem_peri_force_in_sw : 1; + u32 gdsc_handshake_dis : 1; + u32 software_control_override : 4; + u32 gdsc_power_down_complete : 1; + u32 gdsc_power_up_complete : 1; + u32 gdsc_enf_ack_status : 1; + u32 gdsc_enr_ack_status : 1; + u32 gdsc_mem_pwr_ack_status : 1; + u32 gdsc_cfg_fsm_state_status : 4; + u32 gdsc_pwr_up_start : 1; + u32 gdsc_pwr_dwn_start : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 5; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_0_cfg_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_0_cfg_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_0_CFG2_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_0_cfg2_gdscr_s +{ + u32 mem_pwr_dwn_timeout : 4; + u32 dly_assert_clamp_mem : 4; + u32 dly_deassert_clamp_mem : 4; + u32 dly_mem_pwr_up : 4; + u32 gdsc_clamp_mem_sw : 1; + u32 gdsc_pwrdwn_enable_ack_override : 1; + u32 gdsc_mem_pwrup_ack_override : 1; + u32 reserved0 : 13; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_0_cfg2_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_0_cfg2_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_0_CFG3_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_0_cfg3_gdscr_s +{ + u32 gdsc_spare_ctrl_out : 8; + u32 gdsc_spare_ctrl_in : 8; + u32 gdsc_accu_red_sw_override : 1; + u32 gdsc_accu_red_shifter_start_sw : 1; + u32 gdsc_accu_red_shifter_clk_en_sw : 1; + u32 gdsc_accu_red_shifter_done_override : 1; + u32 gdsc_accu_red_timer_en_sw : 1; + u32 dly_accu_red_shifter_done : 4; + u32 gdsc_accu_red_enable : 1; + u32 gdsc_accu_red_shifter_done_status : 1; + u32 reserved0 : 5; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_0_cfg3_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_0_cfg3_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_0_CFG4_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_0_cfg4_gdscr_s +{ + u32 dly_retainff : 4; + u32 dly_clampio : 4; + u32 dly_deassertares : 4; + u32 dly_noretainff : 4; + u32 dly_restoreff : 4; + u32 dly_unclampio : 4; + u32 reserved0 : 8; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_0_cfg4_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_0_cfg4_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QMIP_PCIE_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qmip_pcie_ahb_cbcr_s +{ + u32 reserved0 : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved1 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qmip_pcie_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qmip_pcie_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_0_SLV_Q2A_AXI_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_0_slv_q2a_axi_cbcr_s +{ + u32 reserved0 : 2; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_0_slv_q2a_axi_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_0_slv_q2a_axi_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_0_SLV_AXI_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_0_slv_axi_cbcr_s +{ + u32 reserved0 : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved1 : 8; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved2 : 5; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved3 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved4 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_0_slv_axi_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_0_slv_axi_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_0_SLV_AXI_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_0_slv_axi_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 4; + u32 pwr_fsm_clk_sel : 1; + u32 reserved1 : 3; + u32 sreg_pscbc_spare_ctrl_out : 4; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_0_slv_axi_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_0_slv_axi_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_0_SLV_AXI_CFG_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_0_slv_axi_cfg_sregr_s +{ + u32 wakeup_timer : 8; + u32 sleep_timer : 8; + u32 mem_cph_timer : 6; + u32 mem_core_on_status : 1; + u32 mem_periph_on_status : 1; + u32 mem_core_on_ack_status : 1; + u32 mem_periph_on_ack_status : 1; + u32 mem_core_off_timer : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_0_slv_axi_cfg_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_0_slv_axi_cfg_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_0_MSTR_AXI_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_0_mstr_axi_cbcr_s +{ + u32 reserved0 : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved1 : 8; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved2 : 5; + u32 ignore_rpmh_clk_dis : 1; + u32 ignore_pmu_clk_dis : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_0_mstr_axi_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_0_mstr_axi_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_0_MSTR_AXI_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_0_mstr_axi_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 4; + u32 pwr_fsm_clk_sel : 1; + u32 reserved1 : 3; + u32 sreg_pscbc_spare_ctrl_out : 4; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_0_mstr_axi_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_0_mstr_axi_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_0_MSTR_AXI_CFG_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_0_mstr_axi_cfg_sregr_s +{ + u32 wakeup_timer : 8; + u32 sleep_timer : 8; + u32 mem_cph_timer : 6; + u32 mem_core_on_status : 1; + u32 mem_periph_on_status : 1; + u32 mem_core_on_ack_status : 1; + u32 mem_periph_on_ack_status : 1; + u32 mem_core_off_timer : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_0_mstr_axi_cfg_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_0_mstr_axi_cfg_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_0_CFG_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_0_cfg_ahb_cbcr_s +{ + u32 reserved0 : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved1 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_0_cfg_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_0_cfg_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_0_AUX_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_0_aux_cbcr_s +{ + u32 reserved0 : 2; + u32 clk_ares : 1; + u32 reserved1 : 9; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved2 : 7; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_0_aux_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_0_aux_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_0_AUX_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_0_aux_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 4; + u32 pwr_fsm_clk_sel : 1; + u32 reserved1 : 3; + u32 sreg_pscbc_spare_ctrl_out : 4; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_0_aux_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_0_aux_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_0_AUX_CFG_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_0_aux_cfg_sregr_s +{ + u32 wakeup_timer : 8; + u32 sleep_timer : 8; + u32 mem_cph_timer : 6; + u32 mem_core_on_status : 1; + u32 mem_periph_on_status : 1; + u32 mem_core_on_ack_status : 1; + u32 mem_periph_on_ack_status : 1; + u32 mem_core_off_timer : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_0_aux_cfg_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_0_aux_cfg_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_0_PIPE_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_0_pipe_cbcr_s +{ + u32 reserved0 : 2; + u32 clk_ares : 1; + u32 reserved1 : 9; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved2 : 7; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_0_pipe_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_0_pipe_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_0_PIPE_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_0_pipe_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 4; + u32 pwr_fsm_clk_sel : 1; + u32 reserved1 : 3; + u32 sreg_pscbc_spare_ctrl_out : 4; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_0_pipe_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_0_pipe_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_0_PIPE_CFG_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_0_pipe_cfg_sregr_s +{ + u32 wakeup_timer : 8; + u32 sleep_timer : 8; + u32 mem_cph_timer : 6; + u32 mem_core_on_status : 1; + u32 mem_periph_on_status : 1; + u32 mem_core_on_ack_status : 1; + u32 mem_periph_on_ack_status : 1; + u32 mem_core_off_timer : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_0_pipe_cfg_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_0_pipe_cfg_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_0_PHY_RCHNG_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_0_phy_rchng_cbcr_s +{ + u32 reserved0 : 2; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_0_phy_rchng_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_0_phy_rchng_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_0_PHY_RCHNG_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_0_phy_rchng_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_0_phy_rchng_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_0_phy_rchng_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_0_PHY_RCHNG_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_0_phy_rchng_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_0_phy_rchng_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_0_phy_rchng_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_0_AUX_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_0_aux_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 dirty_m : 1; + u32 dirty_n : 1; + u32 dirty_d : 1; + u32 reserved1 : 23; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_0_aux_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_0_aux_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_0_AUX_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_0_aux_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 6; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_0_aux_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_0_aux_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_0_AUX_M +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_0_aux_m_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_0_aux_m_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_0_aux_m_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_0_AUX_N +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_0_aux_n_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_0_aux_n_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_0_aux_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_0_AUX_D +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_0_aux_d_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_0_aux_d_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_0_aux_d_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_0_PHY_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_0_phy_gdscr_s +{ + u32 sw_collapse : 1; + u32 hw_control : 1; + u32 sw_override : 1; + u32 pd_ares : 1; + u32 clk_disable : 1; + u32 clamp_io : 1; + u32 en_few : 1; + u32 en_rest : 1; + u32 retain : 1; + u32 save : 1; + u32 restore : 1; + u32 retain_ff_enable : 1; + u32 clk_dis_wait : 4; + u32 en_few_wait : 4; + u32 en_rest_wait : 4; + u32 reserved0 : 3; + u32 gdsc_state : 4; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_0_phy_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_0_phy_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_0_PHY_CFG_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_0_phy_cfg_gdscr_s +{ + u32 disable_clk_software_override : 1; + u32 clamp_io_software_override : 1; + u32 save_restore_software_override : 1; + u32 unclamp_io_software_override : 1; + u32 gdsc_pscbc_pwr_dwn_sw : 1; + u32 gdsc_phase_reset_delay_count_sw : 2; + u32 gdsc_phase_reset_en_sw : 1; + u32 gdsc_mem_core_force_in_sw : 1; + u32 gdsc_mem_peri_force_in_sw : 1; + u32 gdsc_handshake_dis : 1; + u32 software_control_override : 4; + u32 gdsc_power_down_complete : 1; + u32 gdsc_power_up_complete : 1; + u32 gdsc_enf_ack_status : 1; + u32 gdsc_enr_ack_status : 1; + u32 gdsc_mem_pwr_ack_status : 1; + u32 gdsc_cfg_fsm_state_status : 4; + u32 gdsc_pwr_up_start : 1; + u32 gdsc_pwr_dwn_start : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 5; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_0_phy_cfg_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_0_phy_cfg_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_0_PHY_CFG2_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_0_phy_cfg2_gdscr_s +{ + u32 mem_pwr_dwn_timeout : 4; + u32 dly_assert_clamp_mem : 4; + u32 dly_deassert_clamp_mem : 4; + u32 dly_mem_pwr_up : 4; + u32 gdsc_clamp_mem_sw : 1; + u32 gdsc_pwrdwn_enable_ack_override : 1; + u32 gdsc_mem_pwrup_ack_override : 1; + u32 reserved0 : 13; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_0_phy_cfg2_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_0_phy_cfg2_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_0_PHY_CFG3_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_0_phy_cfg3_gdscr_s +{ + u32 gdsc_spare_ctrl_out : 8; + u32 gdsc_spare_ctrl_in : 8; + u32 gdsc_accu_red_sw_override : 1; + u32 gdsc_accu_red_shifter_start_sw : 1; + u32 gdsc_accu_red_shifter_clk_en_sw : 1; + u32 gdsc_accu_red_shifter_done_override : 1; + u32 gdsc_accu_red_timer_en_sw : 1; + u32 dly_accu_red_shifter_done : 4; + u32 gdsc_accu_red_enable : 1; + u32 gdsc_accu_red_shifter_done_status : 1; + u32 reserved0 : 5; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_0_phy_cfg3_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_0_phy_cfg3_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_0_PHY_CFG4_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_0_phy_cfg4_gdscr_s +{ + u32 dly_retainff : 4; + u32 dly_clampio : 4; + u32 dly_deassertares : 4; + u32 dly_noretainff : 4; + u32 dly_restoreff : 4; + u32 dly_unclampio : 4; + u32 reserved0 : 8; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_0_phy_cfg4_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_0_phy_cfg4_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_1_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_1_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_1_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_1_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_1_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_1_gdscr_s +{ + u32 sw_collapse : 1; + u32 hw_control : 1; + u32 sw_override : 1; + u32 pd_ares : 1; + u32 clk_disable : 1; + u32 clamp_io : 1; + u32 en_few : 1; + u32 en_rest : 1; + u32 retain : 1; + u32 save : 1; + u32 restore : 1; + u32 retain_ff_enable : 1; + u32 clk_dis_wait : 4; + u32 en_few_wait : 4; + u32 en_rest_wait : 4; + u32 reserved0 : 3; + u32 gdsc_state : 4; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_1_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_1_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_1_CFG_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_1_cfg_gdscr_s +{ + u32 disable_clk_software_override : 1; + u32 clamp_io_software_override : 1; + u32 save_restore_software_override : 1; + u32 unclamp_io_software_override : 1; + u32 gdsc_pscbc_pwr_dwn_sw : 1; + u32 gdsc_phase_reset_delay_count_sw : 2; + u32 gdsc_phase_reset_en_sw : 1; + u32 gdsc_mem_core_force_in_sw : 1; + u32 gdsc_mem_peri_force_in_sw : 1; + u32 gdsc_handshake_dis : 1; + u32 software_control_override : 4; + u32 gdsc_power_down_complete : 1; + u32 gdsc_power_up_complete : 1; + u32 gdsc_enf_ack_status : 1; + u32 gdsc_enr_ack_status : 1; + u32 gdsc_mem_pwr_ack_status : 1; + u32 gdsc_cfg_fsm_state_status : 4; + u32 gdsc_pwr_up_start : 1; + u32 gdsc_pwr_dwn_start : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 5; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_1_cfg_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_1_cfg_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_1_CFG2_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_1_cfg2_gdscr_s +{ + u32 mem_pwr_dwn_timeout : 4; + u32 dly_assert_clamp_mem : 4; + u32 dly_deassert_clamp_mem : 4; + u32 dly_mem_pwr_up : 4; + u32 gdsc_clamp_mem_sw : 1; + u32 gdsc_pwrdwn_enable_ack_override : 1; + u32 gdsc_mem_pwrup_ack_override : 1; + u32 reserved0 : 13; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_1_cfg2_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_1_cfg2_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_1_CFG3_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_1_cfg3_gdscr_s +{ + u32 gdsc_spare_ctrl_out : 8; + u32 gdsc_spare_ctrl_in : 8; + u32 gdsc_accu_red_sw_override : 1; + u32 gdsc_accu_red_shifter_start_sw : 1; + u32 gdsc_accu_red_shifter_clk_en_sw : 1; + u32 gdsc_accu_red_shifter_done_override : 1; + u32 gdsc_accu_red_timer_en_sw : 1; + u32 dly_accu_red_shifter_done : 4; + u32 gdsc_accu_red_enable : 1; + u32 gdsc_accu_red_shifter_done_status : 1; + u32 reserved0 : 5; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_1_cfg3_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_1_cfg3_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_1_CFG4_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_1_cfg4_gdscr_s +{ + u32 dly_retainff : 4; + u32 dly_clampio : 4; + u32 dly_deassertares : 4; + u32 dly_noretainff : 4; + u32 dly_restoreff : 4; + u32 dly_unclampio : 4; + u32 reserved0 : 8; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_1_cfg4_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_1_cfg4_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_1_SLV_Q2A_AXI_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_1_slv_q2a_axi_cbcr_s +{ + u32 reserved0 : 2; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_1_slv_q2a_axi_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_1_slv_q2a_axi_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_1_SLV_AXI_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_1_slv_axi_cbcr_s +{ + u32 reserved0 : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved1 : 8; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved2 : 5; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved3 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved4 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_1_slv_axi_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_1_slv_axi_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_1_SLV_AXI_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_1_slv_axi_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 4; + u32 pwr_fsm_clk_sel : 1; + u32 reserved1 : 3; + u32 sreg_pscbc_spare_ctrl_out : 4; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_1_slv_axi_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_1_slv_axi_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_1_SLV_AXI_CFG_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_1_slv_axi_cfg_sregr_s +{ + u32 wakeup_timer : 8; + u32 sleep_timer : 8; + u32 mem_cph_timer : 6; + u32 mem_core_on_status : 1; + u32 mem_periph_on_status : 1; + u32 mem_core_on_ack_status : 1; + u32 mem_periph_on_ack_status : 1; + u32 mem_core_off_timer : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_1_slv_axi_cfg_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_1_slv_axi_cfg_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_1_MSTR_AXI_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_1_mstr_axi_cbcr_s +{ + u32 reserved0 : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved1 : 8; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved2 : 5; + u32 ignore_rpmh_clk_dis : 1; + u32 ignore_pmu_clk_dis : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_1_mstr_axi_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_1_mstr_axi_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_1_MSTR_AXI_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_1_mstr_axi_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 4; + u32 pwr_fsm_clk_sel : 1; + u32 reserved1 : 3; + u32 sreg_pscbc_spare_ctrl_out : 4; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_1_mstr_axi_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_1_mstr_axi_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_1_MSTR_AXI_CFG_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_1_mstr_axi_cfg_sregr_s +{ + u32 wakeup_timer : 8; + u32 sleep_timer : 8; + u32 mem_cph_timer : 6; + u32 mem_core_on_status : 1; + u32 mem_periph_on_status : 1; + u32 mem_core_on_ack_status : 1; + u32 mem_periph_on_ack_status : 1; + u32 mem_core_off_timer : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_1_mstr_axi_cfg_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_1_mstr_axi_cfg_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_1_CFG_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_1_cfg_ahb_cbcr_s +{ + u32 reserved0 : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved1 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_1_cfg_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_1_cfg_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_1_AUX_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_1_aux_cbcr_s +{ + u32 reserved0 : 2; + u32 clk_ares : 1; + u32 reserved1 : 9; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved2 : 7; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_1_aux_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_1_aux_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_1_AUX_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_1_aux_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 4; + u32 pwr_fsm_clk_sel : 1; + u32 reserved1 : 3; + u32 sreg_pscbc_spare_ctrl_out : 4; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_1_aux_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_1_aux_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_1_AUX_CFG_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_1_aux_cfg_sregr_s +{ + u32 wakeup_timer : 8; + u32 sleep_timer : 8; + u32 mem_cph_timer : 6; + u32 mem_core_on_status : 1; + u32 mem_periph_on_status : 1; + u32 mem_core_on_ack_status : 1; + u32 mem_periph_on_ack_status : 1; + u32 mem_core_off_timer : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_1_aux_cfg_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_1_aux_cfg_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_1_PHY_AUX_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_1_phy_aux_cbcr_s +{ + u32 reserved0 : 2; + u32 clk_ares : 1; + u32 reserved1 : 9; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved2 : 7; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_1_phy_aux_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_1_phy_aux_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_1_PHY_AUX_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_1_phy_aux_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 4; + u32 pwr_fsm_clk_sel : 1; + u32 reserved1 : 3; + u32 sreg_pscbc_spare_ctrl_out : 4; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_1_phy_aux_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_1_phy_aux_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_1_PHY_AUX_CFG_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_1_phy_aux_cfg_sregr_s +{ + u32 wakeup_timer : 8; + u32 sleep_timer : 8; + u32 mem_cph_timer : 6; + u32 mem_core_on_status : 1; + u32 mem_periph_on_status : 1; + u32 mem_core_on_ack_status : 1; + u32 mem_periph_on_ack_status : 1; + u32 mem_core_off_timer : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_1_phy_aux_cfg_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_1_phy_aux_cfg_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_1_PIPE_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_1_pipe_cbcr_s +{ + u32 reserved0 : 2; + u32 clk_ares : 1; + u32 reserved1 : 9; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved2 : 7; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_1_pipe_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_1_pipe_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_1_PIPE_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_1_pipe_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 4; + u32 pwr_fsm_clk_sel : 1; + u32 reserved1 : 3; + u32 sreg_pscbc_spare_ctrl_out : 4; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_1_pipe_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_1_pipe_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_1_PIPE_CFG_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_1_pipe_cfg_sregr_s +{ + u32 wakeup_timer : 8; + u32 sleep_timer : 8; + u32 mem_cph_timer : 6; + u32 mem_core_on_status : 1; + u32 mem_periph_on_status : 1; + u32 mem_core_on_ack_status : 1; + u32 mem_periph_on_ack_status : 1; + u32 mem_core_off_timer : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_1_pipe_cfg_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_1_pipe_cfg_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_1_PHY_RCHNG_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_1_phy_rchng_cbcr_s +{ + u32 reserved0 : 2; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_1_phy_rchng_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_1_phy_rchng_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_1_PHY_RCHNG_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_1_phy_rchng_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_1_phy_rchng_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_1_phy_rchng_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_1_PHY_RCHNG_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_1_phy_rchng_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_1_phy_rchng_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_1_phy_rchng_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_1_AUX_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_1_aux_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 dirty_m : 1; + u32 dirty_n : 1; + u32 dirty_d : 1; + u32 reserved1 : 23; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_1_aux_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_1_aux_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_1_AUX_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_1_aux_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 6; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_1_aux_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_1_aux_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_1_AUX_M +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_1_aux_m_s +{ + u32 m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_1_aux_m_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_1_aux_m_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_1_AUX_N +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_1_aux_n_s +{ + u32 not_n_minus_m : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_1_aux_n_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_1_aux_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_1_AUX_D +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_1_aux_d_s +{ + u32 not_2d : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_1_aux_d_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_1_aux_d_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_1_PHY_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_1_phy_gdscr_s +{ + u32 sw_collapse : 1; + u32 hw_control : 1; + u32 sw_override : 1; + u32 pd_ares : 1; + u32 clk_disable : 1; + u32 clamp_io : 1; + u32 en_few : 1; + u32 en_rest : 1; + u32 retain : 1; + u32 save : 1; + u32 restore : 1; + u32 retain_ff_enable : 1; + u32 clk_dis_wait : 4; + u32 en_few_wait : 4; + u32 en_rest_wait : 4; + u32 reserved0 : 3; + u32 gdsc_state : 4; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_1_phy_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_1_phy_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_1_PHY_CFG_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_1_phy_cfg_gdscr_s +{ + u32 disable_clk_software_override : 1; + u32 clamp_io_software_override : 1; + u32 save_restore_software_override : 1; + u32 unclamp_io_software_override : 1; + u32 gdsc_pscbc_pwr_dwn_sw : 1; + u32 gdsc_phase_reset_delay_count_sw : 2; + u32 gdsc_phase_reset_en_sw : 1; + u32 gdsc_mem_core_force_in_sw : 1; + u32 gdsc_mem_peri_force_in_sw : 1; + u32 gdsc_handshake_dis : 1; + u32 software_control_override : 4; + u32 gdsc_power_down_complete : 1; + u32 gdsc_power_up_complete : 1; + u32 gdsc_enf_ack_status : 1; + u32 gdsc_enr_ack_status : 1; + u32 gdsc_mem_pwr_ack_status : 1; + u32 gdsc_cfg_fsm_state_status : 4; + u32 gdsc_pwr_up_start : 1; + u32 gdsc_pwr_dwn_start : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 5; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_1_phy_cfg_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_1_phy_cfg_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_1_PHY_CFG2_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_1_phy_cfg2_gdscr_s +{ + u32 mem_pwr_dwn_timeout : 4; + u32 dly_assert_clamp_mem : 4; + u32 dly_deassert_clamp_mem : 4; + u32 dly_mem_pwr_up : 4; + u32 gdsc_clamp_mem_sw : 1; + u32 gdsc_pwrdwn_enable_ack_override : 1; + u32 gdsc_mem_pwrup_ack_override : 1; + u32 reserved0 : 13; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_1_phy_cfg2_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_1_phy_cfg2_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_1_PHY_CFG3_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_1_phy_cfg3_gdscr_s +{ + u32 gdsc_spare_ctrl_out : 8; + u32 gdsc_spare_ctrl_in : 8; + u32 gdsc_accu_red_sw_override : 1; + u32 gdsc_accu_red_shifter_start_sw : 1; + u32 gdsc_accu_red_shifter_clk_en_sw : 1; + u32 gdsc_accu_red_shifter_done_override : 1; + u32 gdsc_accu_red_timer_en_sw : 1; + u32 dly_accu_red_shifter_done : 4; + u32 gdsc_accu_red_enable : 1; + u32 gdsc_accu_red_shifter_done_status : 1; + u32 reserved0 : 5; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_1_phy_cfg3_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_1_phy_cfg3_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_1_PHY_CFG4_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_1_phy_cfg4_gdscr_s +{ + u32 dly_retainff : 4; + u32 dly_clampio : 4; + u32 dly_deassertares : 4; + u32 dly_noretainff : 4; + u32 dly_restoreff : 4; + u32 dly_unclampio : 4; + u32 reserved0 : 8; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_1_phy_cfg4_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_1_phy_cfg4_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_PHY_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_phy_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_phy_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_phy_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_UFS_MEM_PHY_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ufs_mem_phy_gdscr_s +{ + u32 sw_collapse : 1; + u32 hw_control : 1; + u32 sw_override : 1; + u32 pd_ares : 1; + u32 clk_disable : 1; + u32 clamp_io : 1; + u32 en_few : 1; + u32 en_rest : 1; + u32 retain : 1; + u32 save : 1; + u32 restore : 1; + u32 retain_ff_enable : 1; + u32 clk_dis_wait : 4; + u32 en_few_wait : 4; + u32 en_rest_wait : 4; + u32 reserved0 : 3; + u32 gdsc_state : 4; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ufs_mem_phy_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_ufs_mem_phy_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_UFS_MEM_PHY_CFG_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ufs_mem_phy_cfg_gdscr_s +{ + u32 disable_clk_software_override : 1; + u32 clamp_io_software_override : 1; + u32 save_restore_software_override : 1; + u32 unclamp_io_software_override : 1; + u32 gdsc_pscbc_pwr_dwn_sw : 1; + u32 gdsc_phase_reset_delay_count_sw : 2; + u32 gdsc_phase_reset_en_sw : 1; + u32 gdsc_mem_core_force_in_sw : 1; + u32 gdsc_mem_peri_force_in_sw : 1; + u32 gdsc_handshake_dis : 1; + u32 software_control_override : 4; + u32 gdsc_power_down_complete : 1; + u32 gdsc_power_up_complete : 1; + u32 gdsc_enf_ack_status : 1; + u32 gdsc_enr_ack_status : 1; + u32 gdsc_mem_pwr_ack_status : 1; + u32 gdsc_cfg_fsm_state_status : 4; + u32 gdsc_pwr_up_start : 1; + u32 gdsc_pwr_dwn_start : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 5; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ufs_mem_phy_cfg_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_ufs_mem_phy_cfg_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_UFS_MEM_PHY_CFG2_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ufs_mem_phy_cfg2_gdscr_s +{ + u32 mem_pwr_dwn_timeout : 4; + u32 dly_assert_clamp_mem : 4; + u32 dly_deassert_clamp_mem : 4; + u32 dly_mem_pwr_up : 4; + u32 gdsc_clamp_mem_sw : 1; + u32 gdsc_pwrdwn_enable_ack_override : 1; + u32 gdsc_mem_pwrup_ack_override : 1; + u32 reserved0 : 13; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ufs_mem_phy_cfg2_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_ufs_mem_phy_cfg2_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_UFS_MEM_PHY_CFG3_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ufs_mem_phy_cfg3_gdscr_s +{ + u32 gdsc_spare_ctrl_out : 8; + u32 gdsc_spare_ctrl_in : 8; + u32 gdsc_accu_red_sw_override : 1; + u32 gdsc_accu_red_shifter_start_sw : 1; + u32 gdsc_accu_red_shifter_clk_en_sw : 1; + u32 gdsc_accu_red_shifter_done_override : 1; + u32 gdsc_accu_red_timer_en_sw : 1; + u32 dly_accu_red_shifter_done : 4; + u32 gdsc_accu_red_enable : 1; + u32 gdsc_accu_red_shifter_done_status : 1; + u32 reserved0 : 5; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ufs_mem_phy_cfg3_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_ufs_mem_phy_cfg3_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_UFS_MEM_PHY_CFG4_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ufs_mem_phy_cfg4_gdscr_s +{ + u32 dly_retainff : 4; + u32 dly_clampio : 4; + u32 dly_deassertares : 4; + u32 dly_noretainff : 4; + u32 dly_restoreff : 4; + u32 dly_unclampio : 4; + u32 reserved0 : 8; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ufs_mem_phy_cfg4_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_ufs_mem_phy_cfg4_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_UFS_PHY_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ufs_phy_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ufs_phy_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_ufs_phy_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_UFS_PHY_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ufs_phy_gdscr_s +{ + u32 sw_collapse : 1; + u32 hw_control : 1; + u32 sw_override : 1; + u32 pd_ares : 1; + u32 clk_disable : 1; + u32 clamp_io : 1; + u32 en_few : 1; + u32 en_rest : 1; + u32 retain : 1; + u32 save : 1; + u32 restore : 1; + u32 retain_ff_enable : 1; + u32 clk_dis_wait : 4; + u32 en_few_wait : 4; + u32 en_rest_wait : 4; + u32 reserved0 : 3; + u32 gdsc_state : 4; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ufs_phy_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_ufs_phy_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_UFS_PHY_CFG_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ufs_phy_cfg_gdscr_s +{ + u32 disable_clk_software_override : 1; + u32 clamp_io_software_override : 1; + u32 save_restore_software_override : 1; + u32 unclamp_io_software_override : 1; + u32 gdsc_pscbc_pwr_dwn_sw : 1; + u32 gdsc_phase_reset_delay_count_sw : 2; + u32 gdsc_phase_reset_en_sw : 1; + u32 gdsc_mem_core_force_in_sw : 1; + u32 gdsc_mem_peri_force_in_sw : 1; + u32 gdsc_handshake_dis : 1; + u32 software_control_override : 4; + u32 gdsc_power_down_complete : 1; + u32 gdsc_power_up_complete : 1; + u32 gdsc_enf_ack_status : 1; + u32 gdsc_enr_ack_status : 1; + u32 gdsc_mem_pwr_ack_status : 1; + u32 gdsc_cfg_fsm_state_status : 4; + u32 gdsc_pwr_up_start : 1; + u32 gdsc_pwr_dwn_start : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 5; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ufs_phy_cfg_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_ufs_phy_cfg_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_UFS_PHY_CFG2_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ufs_phy_cfg2_gdscr_s +{ + u32 mem_pwr_dwn_timeout : 4; + u32 dly_assert_clamp_mem : 4; + u32 dly_deassert_clamp_mem : 4; + u32 dly_mem_pwr_up : 4; + u32 gdsc_clamp_mem_sw : 1; + u32 gdsc_pwrdwn_enable_ack_override : 1; + u32 gdsc_mem_pwrup_ack_override : 1; + u32 reserved0 : 13; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ufs_phy_cfg2_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_ufs_phy_cfg2_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_UFS_PHY_CFG3_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ufs_phy_cfg3_gdscr_s +{ + u32 gdsc_spare_ctrl_out : 8; + u32 gdsc_spare_ctrl_in : 8; + u32 gdsc_accu_red_sw_override : 1; + u32 gdsc_accu_red_shifter_start_sw : 1; + u32 gdsc_accu_red_shifter_clk_en_sw : 1; + u32 gdsc_accu_red_shifter_done_override : 1; + u32 gdsc_accu_red_timer_en_sw : 1; + u32 dly_accu_red_shifter_done : 4; + u32 gdsc_accu_red_enable : 1; + u32 gdsc_accu_red_shifter_done_status : 1; + u32 reserved0 : 5; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ufs_phy_cfg3_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_ufs_phy_cfg3_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_UFS_PHY_CFG4_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ufs_phy_cfg4_gdscr_s +{ + u32 dly_retainff : 4; + u32 dly_clampio : 4; + u32 dly_deassertares : 4; + u32 dly_noretainff : 4; + u32 dly_restoreff : 4; + u32 dly_unclampio : 4; + u32 reserved0 : 8; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ufs_phy_cfg4_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_ufs_phy_cfg4_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_UFS_PHY_AXI_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ufs_phy_axi_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 8; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved1 : 7; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ufs_phy_axi_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ufs_phy_axi_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_UFS_PHY_AXI_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ufs_phy_axi_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 4; + u32 pwr_fsm_clk_sel : 1; + u32 reserved1 : 3; + u32 sreg_pscbc_spare_ctrl_out : 4; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ufs_phy_axi_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_ufs_phy_axi_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_UFS_PHY_AXI_CFG_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ufs_phy_axi_cfg_sregr_s +{ + u32 wakeup_timer : 8; + u32 sleep_timer : 8; + u32 mem_cph_timer : 6; + u32 mem_core_on_status : 1; + u32 mem_periph_on_status : 1; + u32 mem_core_on_ack_status : 1; + u32 mem_periph_on_ack_status : 1; + u32 mem_core_off_timer : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ufs_phy_axi_cfg_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_ufs_phy_axi_cfg_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_UFS_PHY_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ufs_phy_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ufs_phy_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ufs_phy_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_UFS_PHY_TX_SYMBOL_0_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ufs_phy_tx_symbol_0_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ufs_phy_tx_symbol_0_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ufs_phy_tx_symbol_0_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_UFS_PHY_RX_SYMBOL_0_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ufs_phy_rx_symbol_0_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ufs_phy_rx_symbol_0_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ufs_phy_rx_symbol_0_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_UFS_PHY_AXI_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ufs_phy_axi_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 dirty_m : 1; + u32 dirty_n : 1; + u32 dirty_d : 1; + u32 reserved1 : 23; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ufs_phy_axi_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_ufs_phy_axi_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_UFS_PHY_AXI_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ufs_phy_axi_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 1; + u32 mode : 2; + u32 reserved2 : 6; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ufs_phy_axi_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_ufs_phy_axi_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_UFS_PHY_AXI_M +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ufs_phy_axi_m_s +{ + u32 m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ufs_phy_axi_m_u +{ + struct ipa_gcc_hwio_def_gcc_ufs_phy_axi_m_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_UFS_PHY_AXI_N +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ufs_phy_axi_n_s +{ + u32 not_n_minus_m : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ufs_phy_axi_n_u +{ + struct ipa_gcc_hwio_def_gcc_ufs_phy_axi_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_UFS_PHY_AXI_D +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ufs_phy_axi_d_s +{ + u32 not_2d : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ufs_phy_axi_d_u +{ + struct ipa_gcc_hwio_def_gcc_ufs_phy_axi_d_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_DIV_CDIVR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpll0_ufs_phy_tx_symbol_0_div_cdivr_s +{ + u32 clk_div : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpll0_ufs_phy_tx_symbol_0_div_cdivr_u +{ + struct ipa_gcc_hwio_def_gcc_gpll0_ufs_phy_tx_symbol_0_div_cdivr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_DIV_CDIVR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpll0_ufs_phy_rx_symbol_0_div_cdivr_s +{ + u32 clk_div : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpll0_ufs_phy_rx_symbol_0_div_cdivr_u +{ + struct ipa_gcc_hwio_def_gcc_gpll0_ufs_phy_rx_symbol_0_div_cdivr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_UFS_PHY_UNIPRO_CORE_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ufs_phy_unipro_core_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 8; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved1 : 7; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ufs_phy_unipro_core_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ufs_phy_unipro_core_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_UFS_PHY_UNIPRO_CORE_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ufs_phy_unipro_core_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 4; + u32 pwr_fsm_clk_sel : 1; + u32 reserved1 : 3; + u32 sreg_pscbc_spare_ctrl_out : 4; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ufs_phy_unipro_core_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_ufs_phy_unipro_core_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_UFS_PHY_UNIPRO_CORE_CFG_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ufs_phy_unipro_core_cfg_sregr_s +{ + u32 wakeup_timer : 8; + u32 sleep_timer : 8; + u32 mem_cph_timer : 6; + u32 mem_core_on_status : 1; + u32 mem_periph_on_status : 1; + u32 mem_core_on_ack_status : 1; + u32 mem_periph_on_ack_status : 1; + u32 mem_core_off_timer : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ufs_phy_unipro_core_cfg_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_ufs_phy_unipro_core_cfg_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_UFS_PHY_ICE_CORE_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ufs_phy_ice_core_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 8; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved1 : 7; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ufs_phy_ice_core_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ufs_phy_ice_core_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_UFS_PHY_ICE_CORE_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ufs_phy_ice_core_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 4; + u32 pwr_fsm_clk_sel : 1; + u32 reserved1 : 3; + u32 sreg_pscbc_spare_ctrl_out : 4; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ufs_phy_ice_core_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_ufs_phy_ice_core_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_UFS_PHY_ICE_CORE_CFG_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ufs_phy_ice_core_cfg_sregr_s +{ + u32 wakeup_timer : 8; + u32 sleep_timer : 8; + u32 mem_cph_timer : 6; + u32 mem_core_on_status : 1; + u32 mem_periph_on_status : 1; + u32 mem_core_on_ack_status : 1; + u32 mem_periph_on_ack_status : 1; + u32 mem_core_off_timer : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ufs_phy_ice_core_cfg_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_ufs_phy_ice_core_cfg_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_UFS_PHY_ICE_CORE_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ufs_phy_ice_core_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ufs_phy_ice_core_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_ufs_phy_ice_core_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_UFS_PHY_ICE_CORE_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ufs_phy_ice_core_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ufs_phy_ice_core_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_ufs_phy_ice_core_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ufs_phy_unipro_core_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ufs_phy_unipro_core_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_ufs_phy_unipro_core_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ufs_phy_unipro_core_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ufs_phy_unipro_core_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_ufs_phy_unipro_core_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_UFS_PHY_PHY_AUX_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ufs_phy_phy_aux_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ufs_phy_phy_aux_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ufs_phy_phy_aux_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_UFS_PHY_PHY_AUX_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ufs_phy_phy_aux_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ufs_phy_phy_aux_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_ufs_phy_phy_aux_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_UFS_PHY_PHY_AUX_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ufs_phy_phy_aux_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ufs_phy_phy_aux_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_ufs_phy_phy_aux_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_UFS_PHY_RX_SYMBOL_1_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ufs_phy_rx_symbol_1_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ufs_phy_rx_symbol_1_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ufs_phy_rx_symbol_1_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_UFS_AT_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ufs_at_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ufs_at_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ufs_at_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_DIV_CDIVR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpll0_ufs_phy_rx_symbol_1_div_cdivr_s +{ + u32 clk_div : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpll0_ufs_phy_rx_symbol_1_div_cdivr_u +{ + struct ipa_gcc_hwio_def_gcc_gpll0_ufs_phy_rx_symbol_1_div_cdivr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_VS_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_vs_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_vs_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_vs_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_VDDMXC_VS_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_vddmxc_vs_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_vddmxc_vs_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_vddmxc_vs_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_VDDCX_VS_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_vddcx_vs_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_vddcx_vs_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_vddcx_vs_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_VDDMX_VS_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_vddmx_vs_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_vddmx_vs_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_vddmx_vs_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_VDDA_VS_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_vdda_vs_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_vdda_vs_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_vdda_vs_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_VS_CTRL_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_vs_ctrl_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_vs_ctrl_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_vs_ctrl_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_VS_CTRL_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_vs_ctrl_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_vs_ctrl_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_vs_ctrl_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_VSENSOR_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_vsensor_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_vsensor_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_vsensor_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_VSENSOR_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_vsensor_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_vsensor_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_vsensor_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_VS_CTRL_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_vs_ctrl_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_vs_ctrl_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_vs_ctrl_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_VS_CTRL_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_vs_ctrl_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_vs_ctrl_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_vs_ctrl_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_VS_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_vs_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_vs_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_mss_vs_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPU_VS_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpu_vs_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpu_vs_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_gpu_vs_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_APC_VS_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_apc_vs_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_apc_vs_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_apc_vs_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MDSS_VS_0_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mdss_vs_0_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mdss_vs_0_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_mdss_vs_0_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MDSS_VS_1_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mdss_vs_1_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mdss_vs_1_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_mdss_vs_1_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DCC_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_dcc_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_dcc_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_dcc_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DCC_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_dcc_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 8; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved1 : 5; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_dcc_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_dcc_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DCC_AHB_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_dcc_ahb_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 4; + u32 pwr_fsm_clk_sel : 1; + u32 reserved1 : 3; + u32 sreg_pscbc_spare_ctrl_out : 4; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_dcc_ahb_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_dcc_ahb_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DCC_AHB_CFG_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_dcc_ahb_cfg_sregr_s +{ + u32 wakeup_timer : 8; + u32 sleep_timer : 8; + u32 mem_cph_timer : 6; + u32 mem_core_on_status : 1; + u32 mem_periph_on_status : 1; + u32 mem_core_on_ack_status : 1; + u32 mem_periph_on_ack_status : 1; + u32 mem_core_off_timer : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_dcc_ahb_cfg_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_dcc_ahb_cfg_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_IPA_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ipa_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ipa_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_ipa_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_IPA_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ipa_gdscr_s +{ + u32 sw_collapse : 1; + u32 hw_control : 1; + u32 sw_override : 1; + u32 pd_ares : 1; + u32 clk_disable : 1; + u32 clamp_io : 1; + u32 en_few : 1; + u32 en_rest : 1; + u32 retain : 1; + u32 save : 1; + u32 restore : 1; + u32 retain_ff_enable : 1; + u32 clk_dis_wait : 4; + u32 en_few_wait : 4; + u32 en_rest_wait : 4; + u32 reserved0 : 3; + u32 gdsc_state : 4; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ipa_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_ipa_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_IPA_CFG_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ipa_cfg_gdscr_s +{ + u32 disable_clk_software_override : 1; + u32 clamp_io_software_override : 1; + u32 save_restore_software_override : 1; + u32 unclamp_io_software_override : 1; + u32 gdsc_pscbc_pwr_dwn_sw : 1; + u32 gdsc_phase_reset_delay_count_sw : 2; + u32 gdsc_phase_reset_en_sw : 1; + u32 gdsc_mem_core_force_in_sw : 1; + u32 gdsc_mem_peri_force_in_sw : 1; + u32 gdsc_handshake_dis : 1; + u32 software_control_override : 4; + u32 gdsc_power_down_complete : 1; + u32 gdsc_power_up_complete : 1; + u32 gdsc_enf_ack_status : 1; + u32 gdsc_enr_ack_status : 1; + u32 gdsc_mem_pwr_ack_status : 1; + u32 gdsc_cfg_fsm_state_status : 4; + u32 gdsc_pwr_up_start : 1; + u32 gdsc_pwr_dwn_start : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 5; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ipa_cfg_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_ipa_cfg_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_IPA_CFG2_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ipa_cfg2_gdscr_s +{ + u32 mem_pwr_dwn_timeout : 4; + u32 dly_assert_clamp_mem : 4; + u32 dly_deassert_clamp_mem : 4; + u32 dly_mem_pwr_up : 4; + u32 gdsc_clamp_mem_sw : 1; + u32 gdsc_pwrdwn_enable_ack_override : 1; + u32 gdsc_mem_pwrup_ack_override : 1; + u32 reserved0 : 13; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ipa_cfg2_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_ipa_cfg2_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_IPA_CFG3_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ipa_cfg3_gdscr_s +{ + u32 gdsc_spare_ctrl_out : 8; + u32 gdsc_spare_ctrl_in : 8; + u32 gdsc_accu_red_sw_override : 1; + u32 gdsc_accu_red_shifter_start_sw : 1; + u32 gdsc_accu_red_shifter_clk_en_sw : 1; + u32 gdsc_accu_red_shifter_done_override : 1; + u32 gdsc_accu_red_timer_en_sw : 1; + u32 dly_accu_red_shifter_done : 4; + u32 gdsc_accu_red_enable : 1; + u32 gdsc_accu_red_shifter_done_status : 1; + u32 reserved0 : 5; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ipa_cfg3_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_ipa_cfg3_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_IPA_CFG4_GDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ipa_cfg4_gdscr_s +{ + u32 dly_retainff : 4; + u32 dly_clampio : 4; + u32 dly_deassertares : 4; + u32 dly_noretainff : 4; + u32 dly_restoreff : 4; + u32 dly_unclampio : 4; + u32 reserved0 : 8; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ipa_cfg4_gdscr_u +{ + struct ipa_gcc_hwio_def_gcc_ipa_cfg4_gdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_IPA_2X_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ipa_2x_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 9; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved2 : 5; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved3 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved4 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ipa_2x_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ipa_2x_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_IPA_2X_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ipa_2x_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 4; + u32 pwr_fsm_clk_sel : 1; + u32 reserved1 : 3; + u32 sreg_pscbc_spare_ctrl_out : 4; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ipa_2x_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_ipa_2x_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_IPA_2X_CFG_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ipa_2x_cfg_sregr_s +{ + u32 wakeup_timer : 8; + u32 sleep_timer : 8; + u32 mem_cph_timer : 6; + u32 mem_core_on_status : 1; + u32 mem_periph_on_status : 1; + u32 mem_core_on_ack_status : 1; + u32 mem_periph_on_ack_status : 1; + u32 mem_core_off_timer : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ipa_2x_cfg_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_ipa_2x_cfg_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_IPA_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ipa_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 9; + u32 force_mem_periph_off : 1; + u32 force_mem_periph_on : 1; + u32 force_mem_core_on : 1; + u32 reserved2 : 5; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved3 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved4 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ipa_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ipa_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_IPA_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ipa_sregr_s +{ + u32 reserved0 : 1; + u32 sw_clk_en_slp_stg : 1; + u32 sw_clk_en_sel_slp_stg : 1; + u32 sw_ctrl_pwr_down : 1; + u32 sw_rst_slp_stg : 1; + u32 sw_rst_sel_slp_stg : 1; + u32 force_clk_on : 1; + u32 mem_cph_enable : 1; + u32 sw_div_ratio_slp_stg_clk : 2; + u32 mem_periph_on_ack : 1; + u32 mem_core_on_ack : 1; + u32 sw_sm_pscbc_seq_in_override : 1; + u32 mem_cph_rst_sw_override : 1; + u32 pscbc_slp_stg_mode_csr : 1; + u32 ignore_gdsc_pwr_dwn_csr : 1; + u32 sreg_pscbc_spare_ctrl_in : 4; + u32 pwr_fsm_clk_sel : 1; + u32 reserved1 : 3; + u32 sreg_pscbc_spare_ctrl_out : 4; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ipa_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_ipa_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_IPA_CFG_SREGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ipa_cfg_sregr_s +{ + u32 wakeup_timer : 8; + u32 sleep_timer : 8; + u32 mem_cph_timer : 6; + u32 mem_core_on_status : 1; + u32 mem_periph_on_status : 1; + u32 mem_core_on_ack_status : 1; + u32 mem_periph_on_ack_status : 1; + u32 mem_core_off_timer : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ipa_cfg_sregr_u +{ + struct ipa_gcc_hwio_def_gcc_ipa_cfg_sregr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_IPA_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ipa_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ipa_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ipa_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_IPA_XO_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ipa_xo_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ipa_xo_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ipa_xo_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_IPA_APB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ipa_apb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ipa_apb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ipa_apb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_IPA_AT_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ipa_at_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ipa_at_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ipa_at_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_CMD_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_cmd_dfsr_s +{ + u32 dfs_en : 1; + u32 curr_perf_state : 4; + u32 hw_clk_control : 1; + u32 dfs_fsm_state : 3; + u32 perf_state_update_status : 1; + u32 sw_override : 1; + u32 sw_perf_state : 4; + u32 rcg_sw_ctrl : 1; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_cmd_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_cmd_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF8_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf8_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf8_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf8_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF9_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf9_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf9_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf9_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF10_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf10_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf10_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf10_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF11_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf11_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf11_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf11_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF12_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf12_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf12_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf12_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF13_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf13_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf13_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf13_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF14_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf14_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf14_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf14_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_IPA_2X_PERF15_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf15_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf15_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_ipa_2x_perf15_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_IPA_2X_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ipa_2x_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ipa_2x_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_ipa_2x_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_IPA_2X_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ipa_2x_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ipa_2x_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_ipa_2x_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_IPA_2X_DCD_CDIV_DCDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ipa_2x_dcd_cdiv_dcdr_s +{ + u32 dcd_enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ipa_2x_dcd_cdiv_dcdr_u +{ + struct ipa_gcc_hwio_def_gcc_ipa_2x_dcd_cdiv_dcdr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_IPA_DIV_CDIVR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ipa_div_cdivr_s +{ + u32 clk_div : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ipa_div_cdivr_u +{ + struct ipa_gcc_hwio_def_gcc_ipa_div_cdivr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_CFG_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_cfg_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_cfg_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_mss_cfg_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QMIP_MSS_OFFLINE_CFG_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qmip_mss_offline_cfg_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qmip_mss_offline_cfg_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qmip_mss_offline_cfg_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QMIP_MSS_Q6_CFG_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qmip_mss_q6_cfg_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qmip_mss_q6_cfg_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qmip_mss_q6_cfg_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_OFFLINE_AXI_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_offline_axi_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 ignore_pmu_clk_dis : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_offline_axi_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_mss_offline_axi_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_AXIS2_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_axis2_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_axis2_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_mss_axis2_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_TRIG_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_trig_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_trig_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_mss_trig_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_AT_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_at_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_at_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_mss_at_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_SNOC_AXI_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_snoc_axi_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_snoc_axi_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_mss_snoc_axi_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_Q6_MEMNOC_AXI_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_q6_memnoc_axi_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 ignore_pmu_clk_dis : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_q6_memnoc_axi_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_mss_q6_memnoc_axi_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_PLL0_MAIN_DIV_CDIVR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_pll0_main_div_cdivr_s +{ + u32 clk_div : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_pll0_main_div_cdivr_u +{ + struct ipa_gcc_hwio_def_gcc_mss_pll0_main_div_cdivr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_OFFLINE_AXI_DCD_CDIV_DCDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_offline_axi_dcd_cdiv_dcdr_s +{ + u32 dcd_enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_offline_axi_dcd_cdiv_dcdr_u +{ + struct ipa_gcc_hwio_def_gcc_mss_offline_axi_dcd_cdiv_dcdr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_q6_memnoc_axi_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mss_q6_memnoc_axi_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_q6_memnoc_axi_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_q6_memnoc_axi_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mss_q6_memnoc_axi_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_q6_memnoc_axi_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_q6_memnoc_axi_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mss_q6_memnoc_axi_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_q6_memnoc_axi_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_q6_memnoc_axi_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mss_q6_memnoc_axi_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_q6_memnoc_axi_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_q6_memnoc_axi_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mss_q6_memnoc_axi_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_q6_memnoc_axi_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_q6_memnoc_axi_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mss_q6_memnoc_axi_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_q6_memnoc_axi_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_q6_memnoc_axi_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mss_q6_memnoc_axi_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_q6_memnoc_axi_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_q6_memnoc_axi_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mss_q6_memnoc_axi_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_q6_memnoc_axi_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_q6_memnoc_axi_perf8_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mss_q6_memnoc_axi_perf8_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_q6_memnoc_axi_perf8_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_q6_memnoc_axi_perf9_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mss_q6_memnoc_axi_perf9_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_q6_memnoc_axi_perf9_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_q6_memnoc_axi_perf10_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mss_q6_memnoc_axi_perf10_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_q6_memnoc_axi_perf10_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_q6_memnoc_axi_perf11_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mss_q6_memnoc_axi_perf11_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_q6_memnoc_axi_perf11_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_q6_memnoc_axi_perf12_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mss_q6_memnoc_axi_perf12_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_q6_memnoc_axi_perf12_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_q6_memnoc_axi_perf13_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mss_q6_memnoc_axi_perf13_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_q6_memnoc_axi_perf13_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_q6_memnoc_axi_perf14_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mss_q6_memnoc_axi_perf14_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_q6_memnoc_axi_perf14_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_q6_memnoc_axi_perf15_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mss_q6_memnoc_axi_perf15_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_q6_memnoc_axi_perf15_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_Q6_MEMNOC_AXI_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_q6_memnoc_axi_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_q6_memnoc_axi_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_mss_q6_memnoc_axi_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_q6_memnoc_axi_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_q6_memnoc_axi_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_mss_q6_memnoc_axi_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_Q6_MEMNOC_AXI_DCD_CDIV_DCDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_q6_memnoc_axi_dcd_cdiv_dcdr_s +{ + u32 dcd_enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_q6_memnoc_axi_dcd_cdiv_dcdr_u +{ + struct ipa_gcc_hwio_def_gcc_mss_q6_memnoc_axi_dcd_cdiv_dcdr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_offline_axi_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mss_offline_axi_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_offline_axi_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_offline_axi_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mss_offline_axi_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_offline_axi_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_offline_axi_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mss_offline_axi_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_offline_axi_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_offline_axi_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mss_offline_axi_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_offline_axi_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_offline_axi_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mss_offline_axi_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_offline_axi_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_offline_axi_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mss_offline_axi_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_offline_axi_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_offline_axi_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mss_offline_axi_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_offline_axi_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_offline_axi_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mss_offline_axi_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_offline_axi_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF8_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_offline_axi_perf8_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mss_offline_axi_perf8_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_offline_axi_perf8_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF9_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_offline_axi_perf9_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mss_offline_axi_perf9_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_offline_axi_perf9_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF10_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_offline_axi_perf10_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mss_offline_axi_perf10_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_offline_axi_perf10_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF11_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_offline_axi_perf11_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mss_offline_axi_perf11_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_offline_axi_perf11_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF12_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_offline_axi_perf12_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mss_offline_axi_perf12_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_offline_axi_perf12_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF13_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_offline_axi_perf13_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mss_offline_axi_perf13_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_offline_axi_perf13_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF14_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_offline_axi_perf14_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mss_offline_axi_perf14_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_offline_axi_perf14_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_MSS_OFFLINE_AXI_PERF15_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_offline_axi_perf15_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_mss_offline_axi_perf15_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_mss_offline_axi_perf15_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_OFFLINE_AXI_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_offline_axi_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_offline_axi_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_mss_offline_axi_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_OFFLINE_AXI_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_offline_axi_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_offline_axi_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_mss_offline_axi_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GLM_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_glm_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_glm_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_glm_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GLM_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_glm_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_glm_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_glm_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GLM_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_glm_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_glm_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_glm_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GLM_XO_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_glm_xo_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_glm_xo_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_glm_xo_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GLM_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_glm_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_glm_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_glm_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GLM_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_glm_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_glm_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_glm_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPU_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpu_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpu_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_gpu_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPU_CFG_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpu_cfg_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpu_cfg_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_gpu_cfg_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QMIP_GPU_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qmip_gpu_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qmip_gpu_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qmip_gpu_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPU_AT_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpu_at_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpu_at_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_gpu_at_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPU_MEMNOC_GFX_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpu_memnoc_gfx_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpu_memnoc_gfx_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_gpu_memnoc_gfx_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPU_TRIG_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpu_trig_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpu_trig_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_gpu_trig_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPU_SNOC_DVM_GFX_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpu_snoc_dvm_gfx_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpu_snoc_dvm_gfx_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_gpu_snoc_dvm_gfx_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_gpu_memnoc_gfx_perf0_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_gpu_memnoc_gfx_perf0_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_gpu_memnoc_gfx_perf0_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_gpu_memnoc_gfx_perf1_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_gpu_memnoc_gfx_perf1_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_gpu_memnoc_gfx_perf1_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_gpu_memnoc_gfx_perf2_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_gpu_memnoc_gfx_perf2_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_gpu_memnoc_gfx_perf2_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_gpu_memnoc_gfx_perf3_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_gpu_memnoc_gfx_perf3_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_gpu_memnoc_gfx_perf3_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_gpu_memnoc_gfx_perf4_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_gpu_memnoc_gfx_perf4_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_gpu_memnoc_gfx_perf4_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_gpu_memnoc_gfx_perf5_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_gpu_memnoc_gfx_perf5_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_gpu_memnoc_gfx_perf5_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_gpu_memnoc_gfx_perf6_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_gpu_memnoc_gfx_perf6_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_gpu_memnoc_gfx_perf6_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_gpu_memnoc_gfx_perf7_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_gpu_memnoc_gfx_perf7_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_gpu_memnoc_gfx_perf7_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_gpu_memnoc_gfx_perf8_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_gpu_memnoc_gfx_perf8_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_gpu_memnoc_gfx_perf8_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_gpu_memnoc_gfx_perf9_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_gpu_memnoc_gfx_perf9_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_gpu_memnoc_gfx_perf9_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_gpu_memnoc_gfx_perf10_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_gpu_memnoc_gfx_perf10_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_gpu_memnoc_gfx_perf10_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_gpu_memnoc_gfx_perf11_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_gpu_memnoc_gfx_perf11_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_gpu_memnoc_gfx_perf11_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_gpu_memnoc_gfx_perf12_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_gpu_memnoc_gfx_perf12_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_gpu_memnoc_gfx_perf12_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_gpu_memnoc_gfx_perf13_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_gpu_memnoc_gfx_perf13_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_gpu_memnoc_gfx_perf13_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_gpu_memnoc_gfx_perf14_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_gpu_memnoc_gfx_perf14_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_gpu_memnoc_gfx_perf14_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_gpu_memnoc_gfx_perf15_dfsr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_gpu_memnoc_gfx_perf15_dfsr_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_gpu_memnoc_gfx_perf15_dfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPU_MEMNOC_GFX_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpu_memnoc_gfx_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpu_memnoc_gfx_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_gpu_memnoc_gfx_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPU_MEMNOC_GFX_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpu_memnoc_gfx_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpu_memnoc_gfx_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_gpu_memnoc_gfx_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPU_MEMNOC_GFX_DCD_CDIV_DCDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpu_memnoc_gfx_dcd_cdiv_dcdr_s +{ + u32 dcd_enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpu_memnoc_gfx_dcd_cdiv_dcdr_u +{ + struct ipa_gcc_hwio_def_gcc_gpu_memnoc_gfx_dcd_cdiv_dcdr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPU_PLL0_MAIN_DIV_CDIVR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpu_pll0_main_div_cdivr_s +{ + u32 clk_div : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpu_pll0_main_div_cdivr_u +{ + struct ipa_gcc_hwio_def_gcc_gpu_pll0_main_div_cdivr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPU_TRIG_DIV_CDIVR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpu_trig_div_cdivr_s +{ + u32 clk_div : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpu_trig_div_cdivr_u +{ + struct ipa_gcc_hwio_def_gcc_gpu_trig_div_cdivr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SP_SNOC_ANOC_AXI_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sp_snoc_anoc_axi_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sp_snoc_anoc_axi_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_sp_snoc_anoc_axi_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SP_SCR_NIU_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sp_scr_niu_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sp_scr_niu_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_sp_scr_niu_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SP_CFG_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sp_cfg_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sp_cfg_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_sp_cfg_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SP_SCSR_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sp_scsr_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 17; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved2 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved3 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sp_scsr_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_sp_scsr_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SP_GPKT_XO_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sp_gpkt_xo_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sp_gpkt_xo_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_sp_gpkt_xo_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SP_TRIG_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sp_trig_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sp_trig_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_sp_trig_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SP_AT_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sp_at_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sp_at_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_sp_at_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_NAV_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_nav_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_nav_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_nav_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_NAV_AXI_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_nav_axi_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_nav_axi_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_nav_axi_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AHB2PHY_SOUTH_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ahb2phy_south_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ahb2phy_south_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_ahb2phy_south_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_AHB2PHY_1_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ahb2phy_1_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ahb2phy_1_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ahb2phy_1_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CM_PHY_REFGEN1_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cm_phy_refgen1_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cm_phy_refgen1_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_cm_phy_refgen1_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CM_PHY_REFGEN1_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cm_phy_refgen1_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cm_phy_refgen1_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_cm_phy_refgen1_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CM_PHY_REFGEN2_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cm_phy_refgen2_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cm_phy_refgen2_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_cm_phy_refgen2_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CM_PHY_REFGEN2_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cm_phy_refgen2_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cm_phy_refgen2_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_cm_phy_refgen2_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QSPI_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qspi_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qspi_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_qspi_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QSPI_CNOC_PERIPH_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qspi_cnoc_periph_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qspi_cnoc_periph_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qspi_cnoc_periph_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QSPI_CORE_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qspi_core_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qspi_core_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_qspi_core_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QSPI_CORE_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qspi_core_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qspi_core_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qspi_core_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_QSPI_CORE_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_qspi_core_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_qspi_core_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_qspi_core_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RBCPR_MMCX_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rbcpr_mmcx_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rbcpr_mmcx_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_rbcpr_mmcx_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RBCPR_MMCX_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rbcpr_mmcx_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rbcpr_mmcx_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_rbcpr_mmcx_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RBCPR_MMCX_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rbcpr_mmcx_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rbcpr_mmcx_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_rbcpr_mmcx_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RBCPR_MMCX_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rbcpr_mmcx_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rbcpr_mmcx_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_rbcpr_mmcx_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RBCPR_MMCX_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rbcpr_mmcx_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rbcpr_mmcx_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_rbcpr_mmcx_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_IPCC_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ipcc_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ipcc_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_ipcc_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_IPCC_CORE_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ipcc_core_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ipcc_core_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ipcc_core_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_IPCC_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ipcc_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ipcc_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_ipcc_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_IPCC_CORE_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ipcc_core_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ipcc_core_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_ipcc_core_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_IPCC_CORE_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ipcc_core_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ipcc_core_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_ipcc_core_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DPM_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_dpm_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_dpm_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_dpm_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DPM_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_dpm_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 18; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved1 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_dpm_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_dpm_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DPM_CX_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_dpm_cx_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_dpm_cx_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_dpm_cx_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DPM_MX_AHB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_dpm_mx_ahb_cbcr_s +{ + u32 clk_enable : 1; + u32 hw_ctl : 1; + u32 clk_ares : 1; + u32 sw_only_en : 1; + u32 reserved0 : 16; + u32 ignore_rpmh_clk_dis : 1; + u32 reserved1 : 1; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_dpm_mx_ahb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_dpm_mx_ahb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DPM_CB_CBCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_dpm_cb_cbcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 1; + u32 clk_ares : 1; + u32 reserved1 : 19; + u32 clk_dis : 1; + u32 ignore_all_clk_dis : 1; + u32 ignore_all_ares : 1; + u32 reserved2 : 6; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_dpm_cb_cbcr_u +{ + struct ipa_gcc_hwio_def_gcc_dpm_cb_cbcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DPM_CMD_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_dpm_cmd_rcgr_s +{ + u32 update : 1; + u32 root_en : 1; + u32 reserved0 : 2; + u32 dirty_cfg_rcgr : 1; + u32 reserved1 : 26; + u32 root_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_dpm_cmd_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_dpm_cmd_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DPM_CFG_RCGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_dpm_cfg_rcgr_s +{ + u32 src_div : 5; + u32 reserved0 : 3; + u32 src_sel : 3; + u32 reserved1 : 5; + u32 rcglite_disable : 1; + u32 reserved2 : 3; + u32 hw_clk_control : 1; + u32 reserved3 : 11; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_dpm_cfg_rcgr_u +{ + struct ipa_gcc_hwio_def_gcc_dpm_cfg_rcgr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp1_clkgen_acgc_acgcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp1_clkgen_acgc_acgcr_u +{ + struct ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp1_clkgen_acgc_acgcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp2_clkgen_acgc_acgcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp2_clkgen_acgc_acgcr_u +{ + struct ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp2_clkgen_acgc_acgcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp3_clkgen_acgc_acgcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp3_clkgen_acgc_acgcr_u +{ + struct ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp3_clkgen_acgc_acgcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp4_clkgen_acgc_acgcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp4_clkgen_acgc_acgcr_u +{ + struct ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp4_clkgen_acgc_acgcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp5_clkgen_acgc_acgcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp5_clkgen_acgc_acgcr_u +{ + struct ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp5_clkgen_acgc_acgcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp6_clkgen_acgc_acgcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp6_clkgen_acgc_acgcr_u +{ + struct ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp6_clkgen_acgc_acgcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp7_clkgen_acgc_acgcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp7_clkgen_acgc_acgcr_u +{ + struct ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp7_clkgen_acgc_acgcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp8_clkgen_acgc_acgcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp8_clkgen_acgc_acgcr_u +{ + struct ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp8_clkgen_acgc_acgcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp9_clkgen_acgc_acgcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp9_clkgen_acgc_acgcr_u +{ + struct ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp9_clkgen_acgc_acgcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp10_clkgen_acgc_acgcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp10_clkgen_acgc_acgcr_u +{ + struct ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp10_clkgen_acgc_acgcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp11_clkgen_acgc_acgcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp11_clkgen_acgc_acgcr_u +{ + struct ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp11_clkgen_acgc_acgcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp12_clkgen_acgc_acgcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp12_clkgen_acgc_acgcr_u +{ + struct ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp12_clkgen_acgc_acgcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPLL0_OUT_MAIN_PWRGRP13_CLKGEN_ACGC_ACGCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp13_clkgen_acgc_acgcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp13_clkgen_acgc_acgcr_u +{ + struct ipa_gcc_hwio_def_gcc_gpll0_out_main_pwrgrp13_clkgen_acgc_acgcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPLL0_OUT_EVEN_PWRGRP14_CLKGEN_ACGC_ACGCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpll0_out_even_pwrgrp14_clkgen_acgc_acgcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpll0_out_even_pwrgrp14_clkgen_acgc_acgcr_u +{ + struct ipa_gcc_hwio_def_gcc_gpll0_out_even_pwrgrp14_clkgen_acgc_acgcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpll0_out_even_pwrgrp15_clkgen_acgc_acgcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpll0_out_even_pwrgrp15_clkgen_acgc_acgcr_u +{ + struct ipa_gcc_hwio_def_gcc_gpll0_out_even_pwrgrp15_clkgen_acgc_acgcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPLL0_OUT_EVEN_PWRGRP16_CLKGEN_ACGC_ACGCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpll0_out_even_pwrgrp16_clkgen_acgc_acgcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpll0_out_even_pwrgrp16_clkgen_acgc_acgcr_u +{ + struct ipa_gcc_hwio_def_gcc_gpll0_out_even_pwrgrp16_clkgen_acgc_acgcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPLL0_OUT_EVEN_PWRGRP17_CLKGEN_ACGC_ACGCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpll0_out_even_pwrgrp17_clkgen_acgc_acgcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpll0_out_even_pwrgrp17_clkgen_acgc_acgcr_u +{ + struct ipa_gcc_hwio_def_gcc_gpll0_out_even_pwrgrp17_clkgen_acgc_acgcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPLL0_OUT_EVEN_PWRGRP18_CLKGEN_ACGC_ACGCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpll0_out_even_pwrgrp18_clkgen_acgc_acgcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpll0_out_even_pwrgrp18_clkgen_acgc_acgcr_u +{ + struct ipa_gcc_hwio_def_gcc_gpll0_out_even_pwrgrp18_clkgen_acgc_acgcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPLL0_OUT_EVEN_PWRGRP19_CLKGEN_ACGC_ACGCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpll0_out_even_pwrgrp19_clkgen_acgc_acgcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpll0_out_even_pwrgrp19_clkgen_acgc_acgcr_u +{ + struct ipa_gcc_hwio_def_gcc_gpll0_out_even_pwrgrp19_clkgen_acgc_acgcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPLL0_OUT_EVEN_PWRGRP20_CLKGEN_ACGC_ACGCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpll0_out_even_pwrgrp20_clkgen_acgc_acgcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpll0_out_even_pwrgrp20_clkgen_acgc_acgcr_u +{ + struct ipa_gcc_hwio_def_gcc_gpll0_out_even_pwrgrp20_clkgen_acgc_acgcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPLL0_OUT_EVEN_PWRGRP21_CLKGEN_ACGC_ACGCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpll0_out_even_pwrgrp21_clkgen_acgc_acgcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpll0_out_even_pwrgrp21_clkgen_acgc_acgcr_u +{ + struct ipa_gcc_hwio_def_gcc_gpll0_out_even_pwrgrp21_clkgen_acgc_acgcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPLL0_OUT_EVEN_PWRGRP22_CLKGEN_ACGC_ACGCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpll0_out_even_pwrgrp22_clkgen_acgc_acgcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpll0_out_even_pwrgrp22_clkgen_acgc_acgcr_u +{ + struct ipa_gcc_hwio_def_gcc_gpll0_out_even_pwrgrp22_clkgen_acgc_acgcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPLL0_OUT_EVEN_PWRGRP23_CLKGEN_ACGC_ACGCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpll0_out_even_pwrgrp23_clkgen_acgc_acgcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpll0_out_even_pwrgrp23_clkgen_acgc_acgcr_u +{ + struct ipa_gcc_hwio_def_gcc_gpll0_out_even_pwrgrp23_clkgen_acgc_acgcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPLL0_OUT_EVEN_PWRGRP24_CLKGEN_ACGC_ACGCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpll0_out_even_pwrgrp24_clkgen_acgc_acgcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpll0_out_even_pwrgrp24_clkgen_acgc_acgcr_u +{ + struct ipa_gcc_hwio_def_gcc_gpll0_out_even_pwrgrp24_clkgen_acgc_acgcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPLL0_OUT_EVEN_PWRGRP25_CLKGEN_ACGC_ACGCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpll0_out_even_pwrgrp25_clkgen_acgc_acgcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpll0_out_even_pwrgrp25_clkgen_acgc_acgcr_u +{ + struct ipa_gcc_hwio_def_gcc_gpll0_out_even_pwrgrp25_clkgen_acgc_acgcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPLL0_OUT_EVEN_PWRGRP26_CLKGEN_ACGC_ACGCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpll0_out_even_pwrgrp26_clkgen_acgc_acgcr_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpll0_out_even_pwrgrp26_clkgen_acgc_acgcr_u +{ + struct ipa_gcc_hwio_def_gcc_gpll0_out_even_pwrgrp26_clkgen_acgc_acgcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SP_IPA_SGDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sp_ipa_sgdscr_s +{ + u32 sw_override : 1; + u32 retain_ff_enable : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sp_ipa_sgdscr_u +{ + struct ipa_gcc_hwio_def_gcc_sp_ipa_sgdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SP_ANOC_PCIE_SGDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sp_anoc_pcie_sgdscr_s +{ + u32 sw_override : 1; + u32 retain_ff_enable : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sp_anoc_pcie_sgdscr_u +{ + struct ipa_gcc_hwio_def_gcc_sp_anoc_pcie_sgdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SP_PCIE_1_PHY_SGDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sp_pcie_1_phy_sgdscr_s +{ + u32 sw_override : 1; + u32 retain_ff_enable : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sp_pcie_1_phy_sgdscr_u +{ + struct ipa_gcc_hwio_def_gcc_sp_pcie_1_phy_sgdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SP_USB30_PRIM_SGDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sp_usb30_prim_sgdscr_s +{ + u32 sw_override : 1; + u32 retain_ff_enable : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sp_usb30_prim_sgdscr_u +{ + struct ipa_gcc_hwio_def_gcc_sp_usb30_prim_sgdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SP_UFS_PHY_SGDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sp_ufs_phy_sgdscr_s +{ + u32 sw_override : 1; + u32 retain_ff_enable : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sp_ufs_phy_sgdscr_u +{ + struct ipa_gcc_hwio_def_gcc_sp_ufs_phy_sgdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SP_USB3_PHY_SGDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sp_usb3_phy_sgdscr_s +{ + u32 sw_override : 1; + u32 retain_ff_enable : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sp_usb3_phy_sgdscr_u +{ + struct ipa_gcc_hwio_def_gcc_sp_usb3_phy_sgdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SP_MMU_SGDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sp_mmu_sgdscr_s +{ + u32 sw_override : 1; + u32 retain_ff_enable : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sp_mmu_sgdscr_u +{ + struct ipa_gcc_hwio_def_gcc_sp_mmu_sgdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SP_PCIE_1_SGDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sp_pcie_1_sgdscr_s +{ + u32 sw_override : 1; + u32 retain_ff_enable : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sp_pcie_1_sgdscr_u +{ + struct ipa_gcc_hwio_def_gcc_sp_pcie_1_sgdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SP_PCIE_0_PHY_SGDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sp_pcie_0_phy_sgdscr_s +{ + u32 sw_override : 1; + u32 retain_ff_enable : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sp_pcie_0_phy_sgdscr_u +{ + struct ipa_gcc_hwio_def_gcc_sp_pcie_0_phy_sgdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SP_TURING_QTB_SGDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sp_turing_qtb_sgdscr_s +{ + u32 sw_override : 1; + u32 retain_ff_enable : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sp_turing_qtb_sgdscr_u +{ + struct ipa_gcc_hwio_def_gcc_sp_turing_qtb_sgdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SP_UFS_MEM_PHY_SGDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sp_ufs_mem_phy_sgdscr_s +{ + u32 sw_override : 1; + u32 retain_ff_enable : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sp_ufs_mem_phy_sgdscr_u +{ + struct ipa_gcc_hwio_def_gcc_sp_ufs_mem_phy_sgdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SP_PCIE_0_SGDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sp_pcie_0_sgdscr_s +{ + u32 sw_override : 1; + u32 retain_ff_enable : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sp_pcie_0_sgdscr_u +{ + struct ipa_gcc_hwio_def_gcc_sp_pcie_0_sgdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SP_LPASS_QTB_SGDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sp_lpass_qtb_sgdscr_s +{ + u32 sw_override : 1; + u32 retain_ff_enable : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sp_lpass_qtb_sgdscr_u +{ + struct ipa_gcc_hwio_def_gcc_sp_lpass_qtb_sgdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SP_MMNOC_SGDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sp_mmnoc_sgdscr_s +{ + u32 sw_override : 1; + u32 retain_ff_enable : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sp_mmnoc_sgdscr_u +{ + struct ipa_gcc_hwio_def_gcc_sp_mmnoc_sgdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_APCS_TZ_IPA_SGDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_apcs_tz_ipa_sgdscr_s +{ + u32 sw_override : 1; + u32 retain_ff_enable : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_apcs_tz_ipa_sgdscr_u +{ + struct ipa_gcc_hwio_def_gcc_apcs_tz_ipa_sgdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_APCS_TZ_ANOC_PCIE_SGDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_apcs_tz_anoc_pcie_sgdscr_s +{ + u32 sw_override : 1; + u32 retain_ff_enable : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_apcs_tz_anoc_pcie_sgdscr_u +{ + struct ipa_gcc_hwio_def_gcc_apcs_tz_anoc_pcie_sgdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_APCS_TZ_PCIE_1_PHY_SGDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_apcs_tz_pcie_1_phy_sgdscr_s +{ + u32 sw_override : 1; + u32 retain_ff_enable : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_apcs_tz_pcie_1_phy_sgdscr_u +{ + struct ipa_gcc_hwio_def_gcc_apcs_tz_pcie_1_phy_sgdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_APCS_TZ_USB30_PRIM_SGDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_apcs_tz_usb30_prim_sgdscr_s +{ + u32 sw_override : 1; + u32 retain_ff_enable : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_apcs_tz_usb30_prim_sgdscr_u +{ + struct ipa_gcc_hwio_def_gcc_apcs_tz_usb30_prim_sgdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_APCS_TZ_UFS_PHY_SGDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_apcs_tz_ufs_phy_sgdscr_s +{ + u32 sw_override : 1; + u32 retain_ff_enable : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_apcs_tz_ufs_phy_sgdscr_u +{ + struct ipa_gcc_hwio_def_gcc_apcs_tz_ufs_phy_sgdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_APCS_TZ_USB3_PHY_SGDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_apcs_tz_usb3_phy_sgdscr_s +{ + u32 sw_override : 1; + u32 retain_ff_enable : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_apcs_tz_usb3_phy_sgdscr_u +{ + struct ipa_gcc_hwio_def_gcc_apcs_tz_usb3_phy_sgdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_APCS_TZ_MMU_SGDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_apcs_tz_mmu_sgdscr_s +{ + u32 sw_override : 1; + u32 retain_ff_enable : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_apcs_tz_mmu_sgdscr_u +{ + struct ipa_gcc_hwio_def_gcc_apcs_tz_mmu_sgdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_APCS_TZ_PCIE_1_SGDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_apcs_tz_pcie_1_sgdscr_s +{ + u32 sw_override : 1; + u32 retain_ff_enable : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_apcs_tz_pcie_1_sgdscr_u +{ + struct ipa_gcc_hwio_def_gcc_apcs_tz_pcie_1_sgdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_APCS_TZ_PCIE_0_PHY_SGDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_apcs_tz_pcie_0_phy_sgdscr_s +{ + u32 sw_override : 1; + u32 retain_ff_enable : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_apcs_tz_pcie_0_phy_sgdscr_u +{ + struct ipa_gcc_hwio_def_gcc_apcs_tz_pcie_0_phy_sgdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_APCS_TZ_TURING_QTB_SGDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_apcs_tz_turing_qtb_sgdscr_s +{ + u32 sw_override : 1; + u32 retain_ff_enable : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_apcs_tz_turing_qtb_sgdscr_u +{ + struct ipa_gcc_hwio_def_gcc_apcs_tz_turing_qtb_sgdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_APCS_TZ_UFS_MEM_PHY_SGDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_apcs_tz_ufs_mem_phy_sgdscr_s +{ + u32 sw_override : 1; + u32 retain_ff_enable : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_apcs_tz_ufs_mem_phy_sgdscr_u +{ + struct ipa_gcc_hwio_def_gcc_apcs_tz_ufs_mem_phy_sgdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_APCS_TZ_PCIE_0_SGDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_apcs_tz_pcie_0_sgdscr_s +{ + u32 sw_override : 1; + u32 retain_ff_enable : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_apcs_tz_pcie_0_sgdscr_u +{ + struct ipa_gcc_hwio_def_gcc_apcs_tz_pcie_0_sgdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_APCS_TZ_LPASS_QTB_SGDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_apcs_tz_lpass_qtb_sgdscr_s +{ + u32 sw_override : 1; + u32 retain_ff_enable : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_apcs_tz_lpass_qtb_sgdscr_u +{ + struct ipa_gcc_hwio_def_gcc_apcs_tz_lpass_qtb_sgdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_APCS_TZ_MMNOC_SGDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_apcs_tz_mmnoc_sgdscr_s +{ + u32 sw_override : 1; + u32 retain_ff_enable : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_apcs_tz_mmnoc_sgdscr_u +{ + struct ipa_gcc_hwio_def_gcc_apcs_tz_mmnoc_sgdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_Q6_IPA_SGDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_q6_ipa_sgdscr_s +{ + u32 sw_override : 1; + u32 retain_ff_enable : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_q6_ipa_sgdscr_u +{ + struct ipa_gcc_hwio_def_gcc_mss_q6_ipa_sgdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_Q6_ANOC_PCIE_SGDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_q6_anoc_pcie_sgdscr_s +{ + u32 sw_override : 1; + u32 retain_ff_enable : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_q6_anoc_pcie_sgdscr_u +{ + struct ipa_gcc_hwio_def_gcc_mss_q6_anoc_pcie_sgdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_Q6_PCIE_1_PHY_SGDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_q6_pcie_1_phy_sgdscr_s +{ + u32 sw_override : 1; + u32 retain_ff_enable : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_q6_pcie_1_phy_sgdscr_u +{ + struct ipa_gcc_hwio_def_gcc_mss_q6_pcie_1_phy_sgdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_Q6_USB30_PRIM_SGDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_q6_usb30_prim_sgdscr_s +{ + u32 sw_override : 1; + u32 retain_ff_enable : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_q6_usb30_prim_sgdscr_u +{ + struct ipa_gcc_hwio_def_gcc_mss_q6_usb30_prim_sgdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_Q6_UFS_PHY_SGDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_q6_ufs_phy_sgdscr_s +{ + u32 sw_override : 1; + u32 retain_ff_enable : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_q6_ufs_phy_sgdscr_u +{ + struct ipa_gcc_hwio_def_gcc_mss_q6_ufs_phy_sgdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_Q6_USB3_PHY_SGDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_q6_usb3_phy_sgdscr_s +{ + u32 sw_override : 1; + u32 retain_ff_enable : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_q6_usb3_phy_sgdscr_u +{ + struct ipa_gcc_hwio_def_gcc_mss_q6_usb3_phy_sgdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_Q6_MMU_SGDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_q6_mmu_sgdscr_s +{ + u32 sw_override : 1; + u32 retain_ff_enable : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_q6_mmu_sgdscr_u +{ + struct ipa_gcc_hwio_def_gcc_mss_q6_mmu_sgdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_Q6_PCIE_1_SGDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_q6_pcie_1_sgdscr_s +{ + u32 sw_override : 1; + u32 retain_ff_enable : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_q6_pcie_1_sgdscr_u +{ + struct ipa_gcc_hwio_def_gcc_mss_q6_pcie_1_sgdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_Q6_PCIE_0_PHY_SGDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_q6_pcie_0_phy_sgdscr_s +{ + u32 sw_override : 1; + u32 retain_ff_enable : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_q6_pcie_0_phy_sgdscr_u +{ + struct ipa_gcc_hwio_def_gcc_mss_q6_pcie_0_phy_sgdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_Q6_TURING_QTB_SGDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_q6_turing_qtb_sgdscr_s +{ + u32 sw_override : 1; + u32 retain_ff_enable : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_q6_turing_qtb_sgdscr_u +{ + struct ipa_gcc_hwio_def_gcc_mss_q6_turing_qtb_sgdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_Q6_UFS_MEM_PHY_SGDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_q6_ufs_mem_phy_sgdscr_s +{ + u32 sw_override : 1; + u32 retain_ff_enable : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_q6_ufs_mem_phy_sgdscr_u +{ + struct ipa_gcc_hwio_def_gcc_mss_q6_ufs_mem_phy_sgdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_Q6_PCIE_0_SGDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_q6_pcie_0_sgdscr_s +{ + u32 sw_override : 1; + u32 retain_ff_enable : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_q6_pcie_0_sgdscr_u +{ + struct ipa_gcc_hwio_def_gcc_mss_q6_pcie_0_sgdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_Q6_LPASS_QTB_SGDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_q6_lpass_qtb_sgdscr_s +{ + u32 sw_override : 1; + u32 retain_ff_enable : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_q6_lpass_qtb_sgdscr_u +{ + struct ipa_gcc_hwio_def_gcc_mss_q6_lpass_qtb_sgdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_Q6_MMNOC_SGDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_q6_mmnoc_sgdscr_s +{ + u32 sw_override : 1; + u32 retain_ff_enable : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_q6_mmnoc_sgdscr_u +{ + struct ipa_gcc_hwio_def_gcc_mss_q6_mmnoc_sgdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TME_IPA_SGDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tme_ipa_sgdscr_s +{ + u32 sw_override : 1; + u32 retain_ff_enable : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tme_ipa_sgdscr_u +{ + struct ipa_gcc_hwio_def_gcc_tme_ipa_sgdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TME_ANOC_PCIE_SGDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tme_anoc_pcie_sgdscr_s +{ + u32 sw_override : 1; + u32 retain_ff_enable : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tme_anoc_pcie_sgdscr_u +{ + struct ipa_gcc_hwio_def_gcc_tme_anoc_pcie_sgdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TME_PCIE_1_PHY_SGDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tme_pcie_1_phy_sgdscr_s +{ + u32 sw_override : 1; + u32 retain_ff_enable : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tme_pcie_1_phy_sgdscr_u +{ + struct ipa_gcc_hwio_def_gcc_tme_pcie_1_phy_sgdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TME_USB30_PRIM_SGDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tme_usb30_prim_sgdscr_s +{ + u32 sw_override : 1; + u32 retain_ff_enable : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tme_usb30_prim_sgdscr_u +{ + struct ipa_gcc_hwio_def_gcc_tme_usb30_prim_sgdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TME_UFS_PHY_SGDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tme_ufs_phy_sgdscr_s +{ + u32 sw_override : 1; + u32 retain_ff_enable : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tme_ufs_phy_sgdscr_u +{ + struct ipa_gcc_hwio_def_gcc_tme_ufs_phy_sgdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TME_USB3_PHY_SGDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tme_usb3_phy_sgdscr_s +{ + u32 sw_override : 1; + u32 retain_ff_enable : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tme_usb3_phy_sgdscr_u +{ + struct ipa_gcc_hwio_def_gcc_tme_usb3_phy_sgdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TME_MMU_SGDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tme_mmu_sgdscr_s +{ + u32 sw_override : 1; + u32 retain_ff_enable : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tme_mmu_sgdscr_u +{ + struct ipa_gcc_hwio_def_gcc_tme_mmu_sgdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TME_PCIE_1_SGDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tme_pcie_1_sgdscr_s +{ + u32 sw_override : 1; + u32 retain_ff_enable : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tme_pcie_1_sgdscr_u +{ + struct ipa_gcc_hwio_def_gcc_tme_pcie_1_sgdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TME_PCIE_0_PHY_SGDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tme_pcie_0_phy_sgdscr_s +{ + u32 sw_override : 1; + u32 retain_ff_enable : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tme_pcie_0_phy_sgdscr_u +{ + struct ipa_gcc_hwio_def_gcc_tme_pcie_0_phy_sgdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TME_TURING_QTB_SGDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tme_turing_qtb_sgdscr_s +{ + u32 sw_override : 1; + u32 retain_ff_enable : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tme_turing_qtb_sgdscr_u +{ + struct ipa_gcc_hwio_def_gcc_tme_turing_qtb_sgdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TME_UFS_MEM_PHY_SGDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tme_ufs_mem_phy_sgdscr_s +{ + u32 sw_override : 1; + u32 retain_ff_enable : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tme_ufs_mem_phy_sgdscr_u +{ + struct ipa_gcc_hwio_def_gcc_tme_ufs_mem_phy_sgdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TME_PCIE_0_SGDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tme_pcie_0_sgdscr_s +{ + u32 sw_override : 1; + u32 retain_ff_enable : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tme_pcie_0_sgdscr_u +{ + struct ipa_gcc_hwio_def_gcc_tme_pcie_0_sgdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TME_LPASS_QTB_SGDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tme_lpass_qtb_sgdscr_s +{ + u32 sw_override : 1; + u32 retain_ff_enable : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tme_lpass_qtb_sgdscr_u +{ + struct ipa_gcc_hwio_def_gcc_tme_lpass_qtb_sgdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TME_MMNOC_SGDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tme_mmnoc_sgdscr_s +{ + u32 sw_override : 1; + u32 retain_ff_enable : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tme_mmnoc_sgdscr_u +{ + struct ipa_gcc_hwio_def_gcc_tme_mmnoc_sgdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ACC_MISC +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_acc_misc_s +{ + u32 jtag_acc_src_sel_en : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_acc_misc_u +{ + struct ipa_gcc_hwio_def_gcc_acc_misc_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CPUSS_AHB_MISC +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cpuss_ahb_misc_s +{ + u32 cpuss_ahb_clk_auto_scale_dis : 1; + u32 reserved0 : 3; + u32 cpuss_ahb_clk_auto_scale_div : 4; + u32 reserved1 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cpuss_ahb_misc_u +{ + struct ipa_gcc_hwio_def_gcc_cpuss_ahb_misc_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SP_CLOCK_BRANCH_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sp_clock_branch_ena_vote_s +{ + u32 sys_noc_cpuss_ahb_clk_ena : 1; + u32 tcsr_ahb_clk_ena : 1; + u32 qdss_cfg_ahb_clk_ena : 1; + u32 ce1_ahb_clk_ena : 1; + u32 ce1_axi_clk_ena : 1; + u32 ce1_clk_ena : 1; + u32 tlmm_clk_ena : 1; + u32 reserved0 : 1; + u32 tlmm_ahb_clk_ena : 1; + u32 reserved1 : 1; + u32 boot_rom_ahb_clk_ena : 1; + u32 qmip_pcie_ahb_clk_ena : 1; + u32 aggre_noc_pcie_axi_clk_ena : 1; + u32 prng_ahb_clk_ena : 1; + u32 tme_gpll0_clk_src_ena : 1; + u32 gpu_gpll0_clk_src_ena : 1; + u32 gpu_gpll0_div_clk_src_ena : 1; + u32 mss_gpll0_div_clk_src_ena : 1; + u32 tcu_anoc_pcie_qtb_clk_ena : 1; + u32 ddrss_pcie_sf_qtb_clk_ena : 1; + u32 cfg_noc_pcie_anoc_ahb_clk_ena : 1; + u32 cpuss_ahb_clk_ena : 1; + u32 pcie_0_phy_rchng_clk_ena : 1; + u32 pcie_1_phy_rchng_clk_ena : 1; + u32 pcie_1_phy_aux_clk_ena : 1; + u32 pcie_1_slv_q2a_axi_clk_ena : 1; + u32 pcie_1_slv_axi_clk_ena : 1; + u32 pcie_1_mstr_axi_clk_ena : 1; + u32 pcie_1_cfg_ahb_clk_ena : 1; + u32 pcie_1_aux_clk_ena : 1; + u32 pcie_1_pipe_clk_ena : 1; + u32 ddrss_gpll0_main_clk_src_ena : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sp_clock_branch_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_sp_clock_branch_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SP_CLOCK_SLEEP_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sp_clock_sleep_ena_vote_s +{ + u32 sys_noc_cpuss_ahb_clk_sleep_ena : 1; + u32 tcsr_ahb_clk_sleep_ena : 1; + u32 qdss_cfg_ahb_clk_sleep_ena : 1; + u32 ce1_ahb_clk_sleep_ena : 1; + u32 ce1_axi_clk_sleep_ena : 1; + u32 ce1_clk_sleep_ena : 1; + u32 tlmm_clk_sleep_ena : 1; + u32 reserved0 : 1; + u32 tlmm_ahb_clk_sleep_ena : 1; + u32 reserved1 : 1; + u32 boot_rom_ahb_clk_sleep_ena : 1; + u32 qmip_pcie_ahb_clk_sleep_ena : 1; + u32 aggre_noc_pcie_axi_clk_sleep_ena : 1; + u32 prng_ahb_clk_sleep_ena : 1; + u32 tme_gpll0_clk_src_sleep_ena : 1; + u32 gpu_gpll0_clk_src_sleep_ena : 1; + u32 gpu_gpll0_div_clk_src_sleep_ena : 1; + u32 mss_gpll0_div_clk_src_sleep_ena : 1; + u32 tcu_anoc_pcie_qtb_clk_sleep_ena : 1; + u32 ddrss_pcie_sf_qtb_clk_sleep_ena : 1; + u32 cfg_noc_pcie_anoc_ahb_clk_sleep_ena : 1; + u32 cpuss_ahb_clk_sleep_ena : 1; + u32 pcie_0_phy_rchng_clk_sleep_ena : 1; + u32 pcie_1_phy_rchng_clk_sleep_ena : 1; + u32 pcie_1_phy_aux_clk_sleep_ena : 1; + u32 pcie_1_slv_q2a_axi_clk_sleep_ena : 1; + u32 pcie_1_slv_axi_clk_sleep_ena : 1; + u32 pcie_1_mstr_axi_clk_sleep_ena : 1; + u32 pcie_1_cfg_ahb_clk_sleep_ena : 1; + u32 pcie_1_aux_clk_sleep_ena : 1; + u32 pcie_1_pipe_clk_sleep_ena : 1; + u32 ddrss_gpll0_main_clk_src_sleep_ena : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sp_clock_sleep_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_sp_clock_sleep_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SP_CLOCK_BRANCH_ENA_VOTE_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sp_clock_branch_ena_vote_1_s +{ + u32 pcie_0_slv_axi_clk_ena : 1; + u32 pcie_0_mstr_axi_clk_ena : 1; + u32 pcie_0_cfg_ahb_clk_ena : 1; + u32 pcie_0_aux_clk_ena : 1; + u32 pcie_0_pipe_clk_ena : 1; + u32 pcie_0_slv_q2a_axi_clk_ena : 1; + u32 cnoc_pcie_sf_axi_clk_ena : 1; + u32 qupv3_i2c_s_ahb_clk_ena : 1; + u32 qupv3_i2c_core_clk_ena : 1; + u32 aggre_noc_south_axi_clk_ena : 1; + u32 qupv3_i2c_s0_clk_ena : 1; + u32 qupv3_i2c_s1_clk_ena : 1; + u32 qupv3_i2c_s2_clk_ena : 1; + u32 qupv3_i2c_s3_clk_ena : 1; + u32 qupv3_i2c_s4_clk_ena : 1; + u32 qupv3_i2c_s5_clk_ena : 1; + u32 qupv3_i2c_s6_clk_ena : 1; + u32 qupv3_i2c_s7_clk_ena : 1; + u32 qupv3_wrap1_core_2x_clk_ena : 1; + u32 qupv3_wrap1_core_clk_ena : 1; + u32 qupv3_wrap_1_m_ahb_clk_ena : 1; + u32 qupv3_wrap_1_s_ahb_clk_ena : 1; + u32 qupv3_wrap1_s0_clk_ena : 1; + u32 qupv3_wrap1_s1_clk_ena : 1; + u32 qupv3_wrap1_s2_clk_ena : 1; + u32 qupv3_wrap1_s3_clk_ena : 1; + u32 qupv3_wrap1_s4_clk_ena : 1; + u32 qupv3_wrap1_s5_clk_ena : 1; + u32 qupv3_wrap1_s6_clk_ena : 1; + u32 noc_pcie_north_dcd_xo_clk_ena : 1; + u32 qmip_aggre_noc_ahb_clk_ena : 1; + u32 anoc_pcie_pwrctl_clk_ena : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sp_clock_branch_ena_vote_1_u +{ + struct ipa_gcc_hwio_def_gcc_sp_clock_branch_ena_vote_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SP_CLOCK_SLEEP_ENA_VOTE_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sp_clock_sleep_ena_vote_1_s +{ + u32 pcie_0_slv_axi_clk_sleep_ena : 1; + u32 pcie_0_mstr_axi_clk_sleep_ena : 1; + u32 pcie_0_cfg_ahb_clk_sleep_ena : 1; + u32 pcie_0_aux_clk_sleep_ena : 1; + u32 pcie_0_pipe_clk_sleep_ena : 1; + u32 pcie_0_slv_q2a_axi_clk_sleep_ena : 1; + u32 cnoc_pcie_sf_axi_clk_sleep_ena : 1; + u32 qupv3_i2c_s_ahb_clk_sleep_ena : 1; + u32 qupv3_i2c_core_clk_sleep_ena : 1; + u32 aggre_noc_south_axi_clk_sleep_ena : 1; + u32 qupv3_i2c_s0_clk_sleep_ena : 1; + u32 qupv3_i2c_s1_clk_sleep_ena : 1; + u32 qupv3_i2c_s2_clk_sleep_ena : 1; + u32 qupv3_i2c_s3_clk_sleep_ena : 1; + u32 qupv3_i2c_s4_clk_sleep_ena : 1; + u32 qupv3_i2c_s5_clk_sleep_ena : 1; + u32 qupv3_i2c_s6_clk_sleep_ena : 1; + u32 qupv3_i2c_s7_clk_sleep_ena : 1; + u32 qupv3_wrap1_core_2x_clk_sleep_ena : 1; + u32 qupv3_wrap1_core_clk_sleep_ena : 1; + u32 qupv3_wrap_1_m_ahb_clk_sleep_ena : 1; + u32 qupv3_wrap_1_s_ahb_clk_sleep_ena : 1; + u32 qupv3_wrap1_s0_clk_sleep_ena : 1; + u32 qupv3_wrap1_s1_clk_sleep_ena : 1; + u32 qupv3_wrap1_s2_clk_sleep_ena : 1; + u32 qupv3_wrap1_s3_clk_sleep_ena : 1; + u32 qupv3_wrap1_s4_clk_sleep_ena : 1; + u32 qupv3_wrap1_s5_clk_sleep_ena : 1; + u32 qupv3_wrap1_s6_clk_sleep_ena : 1; + u32 noc_pcie_north_dcd_xo_clk_sleep_ena : 1; + u32 qmip_aggre_noc_ahb_clk_sleep_ena : 1; + u32 anoc_pcie_pwrctl_clk_sleep_ena : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sp_clock_sleep_ena_vote_1_u +{ + struct ipa_gcc_hwio_def_gcc_sp_clock_sleep_ena_vote_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SP_CLOCK_BRANCH_ENA_VOTE_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sp_clock_branch_ena_vote_2_s +{ + u32 qupv3_wrap2_core_clk_ena : 1; + u32 qupv3_wrap_2_s_ahb_clk_ena : 1; + u32 qupv3_wrap_2_m_ahb_clk_ena : 1; + u32 qupv3_wrap2_core_2x_clk_ena : 1; + u32 qupv3_wrap2_s0_clk_ena : 1; + u32 qupv3_wrap2_s1_clk_ena : 1; + u32 qupv3_wrap2_s2_clk_ena : 1; + u32 qupv3_wrap2_s3_clk_ena : 1; + u32 qupv3_wrap2_s4_clk_ena : 1; + u32 qupv3_wrap2_s5_clk_ena : 1; + u32 qupv3_wrap2_s6_clk_ena : 1; + u32 anoc_pcie_north_at_clk_ena : 1; + u32 anoc_pcie_tsctr_clk_ena : 1; + u32 anoc_pcie_qosgen_extref_clk_ena : 1; + u32 qupv3_i2c_s8_clk_ena : 1; + u32 qupv3_i2c_s9_clk_ena : 1; + u32 qupv3_wrap1_s7_clk_ena : 1; + u32 qupv3_wrap2_s7_clk_ena : 1; + u32 tme_gpll0_div2_clk_src_ena : 1; + u32 reserved0 : 13; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sp_clock_branch_ena_vote_2_u +{ + struct ipa_gcc_hwio_def_gcc_sp_clock_branch_ena_vote_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SP_CLOCK_SLEEP_ENA_VOTE_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sp_clock_sleep_ena_vote_2_s +{ + u32 qupv3_wrap2_core_clk_sleep_ena : 1; + u32 qupv3_wrap_2_s_ahb_clk_sleep_ena : 1; + u32 qupv3_wrap_2_m_ahb_clk_sleep_ena : 1; + u32 qupv3_wrap2_core_2x_clk_sleep_ena : 1; + u32 qupv3_wrap2_s0_clk_sleep_ena : 1; + u32 qupv3_wrap2_s1_clk_sleep_ena : 1; + u32 qupv3_wrap2_s2_clk_sleep_ena : 1; + u32 qupv3_wrap2_s3_clk_sleep_ena : 1; + u32 qupv3_wrap2_s4_clk_sleep_ena : 1; + u32 qupv3_wrap2_s5_clk_sleep_ena : 1; + u32 qupv3_wrap2_s6_clk_sleep_ena : 1; + u32 anoc_pcie_north_at_clk_sleep_ena : 1; + u32 anoc_pcie_tsctr_clk_sleep_ena : 1; + u32 anoc_pcie_qosgen_extref_clk_sleep_ena : 1; + u32 qupv3_i2c_s8_clk_sleep_ena : 1; + u32 qupv3_i2c_s9_clk_sleep_ena : 1; + u32 qupv3_wrap1_s7_clk_sleep_ena : 1; + u32 qupv3_wrap2_s7_clk_sleep_ena : 1; + u32 tme_gpll0_div2_clk_src_sleep_ena : 1; + u32 reserved0 : 13; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sp_clock_sleep_ena_vote_2_u +{ + struct ipa_gcc_hwio_def_gcc_sp_clock_sleep_ena_vote_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SP_PLL_BRANCH_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sp_pll_branch_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sp_pll_branch_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_sp_pll_branch_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SP_PLL_SLEEP_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sp_pll_sleep_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sp_pll_sleep_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_sp_pll_sleep_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPM_CLOCK_BRANCH_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpm_clock_branch_ena_vote_s +{ + u32 sys_noc_cpuss_ahb_clk_ena : 1; + u32 tcsr_ahb_clk_ena : 1; + u32 qdss_cfg_ahb_clk_ena : 1; + u32 ce1_ahb_clk_ena : 1; + u32 ce1_axi_clk_ena : 1; + u32 ce1_clk_ena : 1; + u32 tlmm_clk_ena : 1; + u32 reserved0 : 1; + u32 tlmm_ahb_clk_ena : 1; + u32 reserved1 : 1; + u32 boot_rom_ahb_clk_ena : 1; + u32 qmip_pcie_ahb_clk_ena : 1; + u32 aggre_noc_pcie_axi_clk_ena : 1; + u32 prng_ahb_clk_ena : 1; + u32 tme_gpll0_clk_src_ena : 1; + u32 gpu_gpll0_clk_src_ena : 1; + u32 gpu_gpll0_div_clk_src_ena : 1; + u32 mss_gpll0_div_clk_src_ena : 1; + u32 tcu_anoc_pcie_qtb_clk_ena : 1; + u32 ddrss_pcie_sf_qtb_clk_ena : 1; + u32 cfg_noc_pcie_anoc_ahb_clk_ena : 1; + u32 cpuss_ahb_clk_ena : 1; + u32 pcie_0_phy_rchng_clk_ena : 1; + u32 pcie_1_phy_rchng_clk_ena : 1; + u32 pcie_1_phy_aux_clk_ena : 1; + u32 pcie_1_slv_q2a_axi_clk_ena : 1; + u32 pcie_1_slv_axi_clk_ena : 1; + u32 pcie_1_mstr_axi_clk_ena : 1; + u32 pcie_1_cfg_ahb_clk_ena : 1; + u32 pcie_1_aux_clk_ena : 1; + u32 pcie_1_pipe_clk_ena : 1; + u32 ddrss_gpll0_main_clk_src_ena : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpm_clock_branch_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpm_clock_branch_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPM_CLOCK_SLEEP_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpm_clock_sleep_ena_vote_s +{ + u32 sys_noc_cpuss_ahb_clk_sleep_ena : 1; + u32 tcsr_ahb_clk_sleep_ena : 1; + u32 qdss_cfg_ahb_clk_sleep_ena : 1; + u32 ce1_ahb_clk_sleep_ena : 1; + u32 ce1_axi_clk_sleep_ena : 1; + u32 ce1_clk_sleep_ena : 1; + u32 tlmm_clk_sleep_ena : 1; + u32 reserved0 : 1; + u32 tlmm_ahb_clk_sleep_ena : 1; + u32 reserved1 : 1; + u32 boot_rom_ahb_clk_sleep_ena : 1; + u32 qmip_pcie_ahb_clk_sleep_ena : 1; + u32 aggre_noc_pcie_axi_clk_sleep_ena : 1; + u32 prng_ahb_clk_sleep_ena : 1; + u32 tme_gpll0_clk_src_sleep_ena : 1; + u32 gpu_gpll0_clk_src_sleep_ena : 1; + u32 gpu_gpll0_div_clk_src_sleep_ena : 1; + u32 mss_gpll0_div_clk_src_sleep_ena : 1; + u32 tcu_anoc_pcie_qtb_clk_sleep_ena : 1; + u32 ddrss_pcie_sf_qtb_clk_sleep_ena : 1; + u32 cfg_noc_pcie_anoc_ahb_clk_sleep_ena : 1; + u32 cpuss_ahb_clk_sleep_ena : 1; + u32 pcie_0_phy_rchng_clk_sleep_ena : 1; + u32 pcie_1_phy_rchng_clk_sleep_ena : 1; + u32 pcie_1_phy_aux_clk_sleep_ena : 1; + u32 pcie_1_slv_q2a_axi_clk_sleep_ena : 1; + u32 pcie_1_slv_axi_clk_sleep_ena : 1; + u32 pcie_1_mstr_axi_clk_sleep_ena : 1; + u32 pcie_1_cfg_ahb_clk_sleep_ena : 1; + u32 pcie_1_aux_clk_sleep_ena : 1; + u32 pcie_1_pipe_clk_sleep_ena : 1; + u32 ddrss_gpll0_main_clk_src_sleep_ena : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpm_clock_sleep_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpm_clock_sleep_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpm_clock_branch_ena_vote_1_s +{ + u32 pcie_0_slv_axi_clk_ena : 1; + u32 pcie_0_mstr_axi_clk_ena : 1; + u32 pcie_0_cfg_ahb_clk_ena : 1; + u32 pcie_0_aux_clk_ena : 1; + u32 pcie_0_pipe_clk_ena : 1; + u32 pcie_0_slv_q2a_axi_clk_ena : 1; + u32 cnoc_pcie_sf_axi_clk_ena : 1; + u32 qupv3_i2c_s_ahb_clk_ena : 1; + u32 qupv3_i2c_core_clk_ena : 1; + u32 aggre_noc_south_axi_clk_ena : 1; + u32 qupv3_i2c_s0_clk_ena : 1; + u32 qupv3_i2c_s1_clk_ena : 1; + u32 qupv3_i2c_s2_clk_ena : 1; + u32 qupv3_i2c_s3_clk_ena : 1; + u32 qupv3_i2c_s4_clk_ena : 1; + u32 qupv3_i2c_s5_clk_ena : 1; + u32 qupv3_i2c_s6_clk_ena : 1; + u32 qupv3_i2c_s7_clk_ena : 1; + u32 qupv3_wrap1_core_2x_clk_ena : 1; + u32 qupv3_wrap1_core_clk_ena : 1; + u32 qupv3_wrap_1_m_ahb_clk_ena : 1; + u32 qupv3_wrap_1_s_ahb_clk_ena : 1; + u32 qupv3_wrap1_s0_clk_ena : 1; + u32 qupv3_wrap1_s1_clk_ena : 1; + u32 qupv3_wrap1_s2_clk_ena : 1; + u32 qupv3_wrap1_s3_clk_ena : 1; + u32 qupv3_wrap1_s4_clk_ena : 1; + u32 qupv3_wrap1_s5_clk_ena : 1; + u32 qupv3_wrap1_s6_clk_ena : 1; + u32 noc_pcie_north_dcd_xo_clk_ena : 1; + u32 qmip_aggre_noc_ahb_clk_ena : 1; + u32 anoc_pcie_pwrctl_clk_ena : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpm_clock_branch_ena_vote_1_u +{ + struct ipa_gcc_hwio_def_gcc_rpm_clock_branch_ena_vote_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpm_clock_sleep_ena_vote_1_s +{ + u32 pcie_0_slv_axi_clk_sleep_ena : 1; + u32 pcie_0_mstr_axi_clk_sleep_ena : 1; + u32 pcie_0_cfg_ahb_clk_sleep_ena : 1; + u32 pcie_0_aux_clk_sleep_ena : 1; + u32 pcie_0_pipe_clk_sleep_ena : 1; + u32 pcie_0_slv_q2a_axi_clk_sleep_ena : 1; + u32 cnoc_pcie_sf_axi_clk_sleep_ena : 1; + u32 qupv3_i2c_s_ahb_clk_sleep_ena : 1; + u32 qupv3_i2c_core_clk_sleep_ena : 1; + u32 aggre_noc_south_axi_clk_sleep_ena : 1; + u32 qupv3_i2c_s0_clk_sleep_ena : 1; + u32 qupv3_i2c_s1_clk_sleep_ena : 1; + u32 qupv3_i2c_s2_clk_sleep_ena : 1; + u32 qupv3_i2c_s3_clk_sleep_ena : 1; + u32 qupv3_i2c_s4_clk_sleep_ena : 1; + u32 qupv3_i2c_s5_clk_sleep_ena : 1; + u32 qupv3_i2c_s6_clk_sleep_ena : 1; + u32 qupv3_i2c_s7_clk_sleep_ena : 1; + u32 qupv3_wrap1_core_2x_clk_sleep_ena : 1; + u32 qupv3_wrap1_core_clk_sleep_ena : 1; + u32 qupv3_wrap_1_m_ahb_clk_sleep_ena : 1; + u32 qupv3_wrap_1_s_ahb_clk_sleep_ena : 1; + u32 qupv3_wrap1_s0_clk_sleep_ena : 1; + u32 qupv3_wrap1_s1_clk_sleep_ena : 1; + u32 qupv3_wrap1_s2_clk_sleep_ena : 1; + u32 qupv3_wrap1_s3_clk_sleep_ena : 1; + u32 qupv3_wrap1_s4_clk_sleep_ena : 1; + u32 qupv3_wrap1_s5_clk_sleep_ena : 1; + u32 qupv3_wrap1_s6_clk_sleep_ena : 1; + u32 noc_pcie_north_dcd_xo_clk_sleep_ena : 1; + u32 qmip_aggre_noc_ahb_clk_sleep_ena : 1; + u32 anoc_pcie_pwrctl_clk_sleep_ena : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpm_clock_sleep_ena_vote_1_u +{ + struct ipa_gcc_hwio_def_gcc_rpm_clock_sleep_ena_vote_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpm_clock_branch_ena_vote_2_s +{ + u32 qupv3_wrap2_core_clk_ena : 1; + u32 qupv3_wrap_2_s_ahb_clk_ena : 1; + u32 qupv3_wrap_2_m_ahb_clk_ena : 1; + u32 qupv3_wrap2_core_2x_clk_ena : 1; + u32 qupv3_wrap2_s0_clk_ena : 1; + u32 qupv3_wrap2_s1_clk_ena : 1; + u32 qupv3_wrap2_s2_clk_ena : 1; + u32 qupv3_wrap2_s3_clk_ena : 1; + u32 qupv3_wrap2_s4_clk_ena : 1; + u32 qupv3_wrap2_s5_clk_ena : 1; + u32 qupv3_wrap2_s6_clk_ena : 1; + u32 anoc_pcie_north_at_clk_ena : 1; + u32 anoc_pcie_tsctr_clk_ena : 1; + u32 anoc_pcie_qosgen_extref_clk_ena : 1; + u32 qupv3_i2c_s8_clk_ena : 1; + u32 qupv3_i2c_s9_clk_ena : 1; + u32 qupv3_wrap1_s7_clk_ena : 1; + u32 qupv3_wrap2_s7_clk_ena : 1; + u32 tme_gpll0_div2_clk_src_ena : 1; + u32 reserved0 : 13; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpm_clock_branch_ena_vote_2_u +{ + struct ipa_gcc_hwio_def_gcc_rpm_clock_branch_ena_vote_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpm_clock_sleep_ena_vote_2_s +{ + u32 qupv3_wrap2_core_clk_sleep_ena : 1; + u32 qupv3_wrap_2_s_ahb_clk_sleep_ena : 1; + u32 qupv3_wrap_2_m_ahb_clk_sleep_ena : 1; + u32 qupv3_wrap2_core_2x_clk_sleep_ena : 1; + u32 qupv3_wrap2_s0_clk_sleep_ena : 1; + u32 qupv3_wrap2_s1_clk_sleep_ena : 1; + u32 qupv3_wrap2_s2_clk_sleep_ena : 1; + u32 qupv3_wrap2_s3_clk_sleep_ena : 1; + u32 qupv3_wrap2_s4_clk_sleep_ena : 1; + u32 qupv3_wrap2_s5_clk_sleep_ena : 1; + u32 qupv3_wrap2_s6_clk_sleep_ena : 1; + u32 anoc_pcie_north_at_clk_sleep_ena : 1; + u32 anoc_pcie_tsctr_clk_sleep_ena : 1; + u32 anoc_pcie_qosgen_extref_clk_sleep_ena : 1; + u32 qupv3_i2c_s8_clk_sleep_ena : 1; + u32 qupv3_i2c_s9_clk_sleep_ena : 1; + u32 qupv3_wrap1_s7_clk_sleep_ena : 1; + u32 qupv3_wrap2_s7_clk_sleep_ena : 1; + u32 tme_gpll0_div2_clk_src_sleep_ena : 1; + u32 reserved0 : 13; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpm_clock_sleep_ena_vote_2_u +{ + struct ipa_gcc_hwio_def_gcc_rpm_clock_sleep_ena_vote_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPM_PLL_BRANCH_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpm_pll_branch_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpm_pll_branch_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpm_pll_branch_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPM_PLL_SLEEP_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpm_pll_sleep_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpm_pll_sleep_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpm_pll_sleep_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_APCS_CLOCK_BRANCH_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_apcs_clock_branch_ena_vote_s +{ + u32 sys_noc_cpuss_ahb_clk_ena : 1; + u32 tcsr_ahb_clk_ena : 1; + u32 qdss_cfg_ahb_clk_ena : 1; + u32 ce1_ahb_clk_ena : 1; + u32 ce1_axi_clk_ena : 1; + u32 ce1_clk_ena : 1; + u32 tlmm_clk_ena : 1; + u32 reserved0 : 1; + u32 tlmm_ahb_clk_ena : 1; + u32 reserved1 : 1; + u32 boot_rom_ahb_clk_ena : 1; + u32 qmip_pcie_ahb_clk_ena : 1; + u32 aggre_noc_pcie_axi_clk_ena : 1; + u32 prng_ahb_clk_ena : 1; + u32 tme_gpll0_clk_src_ena : 1; + u32 gpu_gpll0_clk_src_ena : 1; + u32 gpu_gpll0_div_clk_src_ena : 1; + u32 mss_gpll0_div_clk_src_ena : 1; + u32 tcu_anoc_pcie_qtb_clk_ena : 1; + u32 ddrss_pcie_sf_qtb_clk_ena : 1; + u32 cfg_noc_pcie_anoc_ahb_clk_ena : 1; + u32 cpuss_ahb_clk_ena : 1; + u32 pcie_0_phy_rchng_clk_ena : 1; + u32 pcie_1_phy_rchng_clk_ena : 1; + u32 pcie_1_phy_aux_clk_ena : 1; + u32 pcie_1_slv_q2a_axi_clk_ena : 1; + u32 pcie_1_slv_axi_clk_ena : 1; + u32 pcie_1_mstr_axi_clk_ena : 1; + u32 pcie_1_cfg_ahb_clk_ena : 1; + u32 pcie_1_aux_clk_ena : 1; + u32 pcie_1_pipe_clk_ena : 1; + u32 ddrss_gpll0_main_clk_src_ena : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_apcs_clock_branch_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_apcs_clock_branch_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_APCS_CLOCK_SLEEP_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_apcs_clock_sleep_ena_vote_s +{ + u32 sys_noc_cpuss_ahb_clk_sleep_ena : 1; + u32 tcsr_ahb_clk_sleep_ena : 1; + u32 qdss_cfg_ahb_clk_sleep_ena : 1; + u32 ce1_ahb_clk_sleep_ena : 1; + u32 ce1_axi_clk_sleep_ena : 1; + u32 ce1_clk_sleep_ena : 1; + u32 tlmm_clk_sleep_ena : 1; + u32 reserved0 : 1; + u32 tlmm_ahb_clk_sleep_ena : 1; + u32 reserved1 : 1; + u32 boot_rom_ahb_clk_sleep_ena : 1; + u32 qmip_pcie_ahb_clk_sleep_ena : 1; + u32 aggre_noc_pcie_axi_clk_sleep_ena : 1; + u32 prng_ahb_clk_sleep_ena : 1; + u32 tme_gpll0_clk_src_sleep_ena : 1; + u32 gpu_gpll0_clk_src_sleep_ena : 1; + u32 gpu_gpll0_div_clk_src_sleep_ena : 1; + u32 mss_gpll0_div_clk_src_sleep_ena : 1; + u32 tcu_anoc_pcie_qtb_clk_sleep_ena : 1; + u32 ddrss_pcie_sf_qtb_clk_sleep_ena : 1; + u32 cfg_noc_pcie_anoc_ahb_clk_sleep_ena : 1; + u32 cpuss_ahb_clk_sleep_ena : 1; + u32 pcie_0_phy_rchng_clk_sleep_ena : 1; + u32 pcie_1_phy_rchng_clk_sleep_ena : 1; + u32 pcie_1_phy_aux_clk_sleep_ena : 1; + u32 pcie_1_slv_q2a_axi_clk_sleep_ena : 1; + u32 pcie_1_slv_axi_clk_sleep_ena : 1; + u32 pcie_1_mstr_axi_clk_sleep_ena : 1; + u32 pcie_1_cfg_ahb_clk_sleep_ena : 1; + u32 pcie_1_aux_clk_sleep_ena : 1; + u32 pcie_1_pipe_clk_sleep_ena : 1; + u32 ddrss_gpll0_main_clk_src_sleep_ena : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_apcs_clock_sleep_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_apcs_clock_sleep_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_apcs_clock_branch_ena_vote_1_s +{ + u32 pcie_0_slv_axi_clk_ena : 1; + u32 pcie_0_mstr_axi_clk_ena : 1; + u32 pcie_0_cfg_ahb_clk_ena : 1; + u32 pcie_0_aux_clk_ena : 1; + u32 pcie_0_pipe_clk_ena : 1; + u32 pcie_0_slv_q2a_axi_clk_ena : 1; + u32 cnoc_pcie_sf_axi_clk_ena : 1; + u32 qupv3_i2c_s_ahb_clk_ena : 1; + u32 qupv3_i2c_core_clk_ena : 1; + u32 aggre_noc_south_axi_clk_ena : 1; + u32 qupv3_i2c_s0_clk_ena : 1; + u32 qupv3_i2c_s1_clk_ena : 1; + u32 qupv3_i2c_s2_clk_ena : 1; + u32 qupv3_i2c_s3_clk_ena : 1; + u32 qupv3_i2c_s4_clk_ena : 1; + u32 qupv3_i2c_s5_clk_ena : 1; + u32 qupv3_i2c_s6_clk_ena : 1; + u32 qupv3_i2c_s7_clk_ena : 1; + u32 qupv3_wrap1_core_2x_clk_ena : 1; + u32 qupv3_wrap1_core_clk_ena : 1; + u32 qupv3_wrap_1_m_ahb_clk_ena : 1; + u32 qupv3_wrap_1_s_ahb_clk_ena : 1; + u32 qupv3_wrap1_s0_clk_ena : 1; + u32 qupv3_wrap1_s1_clk_ena : 1; + u32 qupv3_wrap1_s2_clk_ena : 1; + u32 qupv3_wrap1_s3_clk_ena : 1; + u32 qupv3_wrap1_s4_clk_ena : 1; + u32 qupv3_wrap1_s5_clk_ena : 1; + u32 qupv3_wrap1_s6_clk_ena : 1; + u32 noc_pcie_north_dcd_xo_clk_ena : 1; + u32 qmip_aggre_noc_ahb_clk_ena : 1; + u32 anoc_pcie_pwrctl_clk_ena : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_apcs_clock_branch_ena_vote_1_u +{ + struct ipa_gcc_hwio_def_gcc_apcs_clock_branch_ena_vote_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_apcs_clock_sleep_ena_vote_1_s +{ + u32 pcie_0_slv_axi_clk_sleep_ena : 1; + u32 pcie_0_mstr_axi_clk_sleep_ena : 1; + u32 pcie_0_cfg_ahb_clk_sleep_ena : 1; + u32 pcie_0_aux_clk_sleep_ena : 1; + u32 pcie_0_pipe_clk_sleep_ena : 1; + u32 pcie_0_slv_q2a_axi_clk_sleep_ena : 1; + u32 cnoc_pcie_sf_axi_clk_sleep_ena : 1; + u32 qupv3_i2c_s_ahb_clk_sleep_ena : 1; + u32 qupv3_i2c_core_clk_sleep_ena : 1; + u32 aggre_noc_south_axi_clk_sleep_ena : 1; + u32 qupv3_i2c_s0_clk_sleep_ena : 1; + u32 qupv3_i2c_s1_clk_sleep_ena : 1; + u32 qupv3_i2c_s2_clk_sleep_ena : 1; + u32 qupv3_i2c_s3_clk_sleep_ena : 1; + u32 qupv3_i2c_s4_clk_sleep_ena : 1; + u32 qupv3_i2c_s5_clk_sleep_ena : 1; + u32 qupv3_i2c_s6_clk_sleep_ena : 1; + u32 qupv3_i2c_s7_clk_sleep_ena : 1; + u32 qupv3_wrap1_core_2x_clk_sleep_ena : 1; + u32 qupv3_wrap1_core_clk_sleep_ena : 1; + u32 qupv3_wrap_1_m_ahb_clk_sleep_ena : 1; + u32 qupv3_wrap_1_s_ahb_clk_sleep_ena : 1; + u32 qupv3_wrap1_s0_clk_sleep_ena : 1; + u32 qupv3_wrap1_s1_clk_sleep_ena : 1; + u32 qupv3_wrap1_s2_clk_sleep_ena : 1; + u32 qupv3_wrap1_s3_clk_sleep_ena : 1; + u32 qupv3_wrap1_s4_clk_sleep_ena : 1; + u32 qupv3_wrap1_s5_clk_sleep_ena : 1; + u32 qupv3_wrap1_s6_clk_sleep_ena : 1; + u32 noc_pcie_north_dcd_xo_clk_sleep_ena : 1; + u32 qmip_aggre_noc_ahb_clk_sleep_ena : 1; + u32 anoc_pcie_pwrctl_clk_sleep_ena : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_apcs_clock_sleep_ena_vote_1_u +{ + struct ipa_gcc_hwio_def_gcc_apcs_clock_sleep_ena_vote_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_apcs_clock_branch_ena_vote_2_s +{ + u32 qupv3_wrap2_core_clk_ena : 1; + u32 qupv3_wrap_2_s_ahb_clk_ena : 1; + u32 qupv3_wrap_2_m_ahb_clk_ena : 1; + u32 qupv3_wrap2_core_2x_clk_ena : 1; + u32 qupv3_wrap2_s0_clk_ena : 1; + u32 qupv3_wrap2_s1_clk_ena : 1; + u32 qupv3_wrap2_s2_clk_ena : 1; + u32 qupv3_wrap2_s3_clk_ena : 1; + u32 qupv3_wrap2_s4_clk_ena : 1; + u32 qupv3_wrap2_s5_clk_ena : 1; + u32 qupv3_wrap2_s6_clk_ena : 1; + u32 anoc_pcie_north_at_clk_ena : 1; + u32 anoc_pcie_tsctr_clk_ena : 1; + u32 anoc_pcie_qosgen_extref_clk_ena : 1; + u32 qupv3_i2c_s8_clk_ena : 1; + u32 qupv3_i2c_s9_clk_ena : 1; + u32 qupv3_wrap1_s7_clk_ena : 1; + u32 qupv3_wrap2_s7_clk_ena : 1; + u32 tme_gpll0_div2_clk_src_ena : 1; + u32 reserved0 : 13; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_apcs_clock_branch_ena_vote_2_u +{ + struct ipa_gcc_hwio_def_gcc_apcs_clock_branch_ena_vote_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_apcs_clock_sleep_ena_vote_2_s +{ + u32 qupv3_wrap2_core_clk_sleep_ena : 1; + u32 qupv3_wrap_2_s_ahb_clk_sleep_ena : 1; + u32 qupv3_wrap_2_m_ahb_clk_sleep_ena : 1; + u32 qupv3_wrap2_core_2x_clk_sleep_ena : 1; + u32 qupv3_wrap2_s0_clk_sleep_ena : 1; + u32 qupv3_wrap2_s1_clk_sleep_ena : 1; + u32 qupv3_wrap2_s2_clk_sleep_ena : 1; + u32 qupv3_wrap2_s3_clk_sleep_ena : 1; + u32 qupv3_wrap2_s4_clk_sleep_ena : 1; + u32 qupv3_wrap2_s5_clk_sleep_ena : 1; + u32 qupv3_wrap2_s6_clk_sleep_ena : 1; + u32 anoc_pcie_north_at_clk_sleep_ena : 1; + u32 anoc_pcie_tsctr_clk_sleep_ena : 1; + u32 anoc_pcie_qosgen_extref_clk_sleep_ena : 1; + u32 qupv3_i2c_s8_clk_sleep_ena : 1; + u32 qupv3_i2c_s9_clk_sleep_ena : 1; + u32 qupv3_wrap1_s7_clk_sleep_ena : 1; + u32 qupv3_wrap2_s7_clk_sleep_ena : 1; + u32 tme_gpll0_div2_clk_src_sleep_ena : 1; + u32 reserved0 : 13; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_apcs_clock_sleep_ena_vote_2_u +{ + struct ipa_gcc_hwio_def_gcc_apcs_clock_sleep_ena_vote_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_APCS_PLL_BRANCH_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_apcs_pll_branch_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_apcs_pll_branch_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_apcs_pll_branch_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_APCS_PLL_SLEEP_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_apcs_pll_sleep_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_apcs_pll_sleep_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_apcs_pll_sleep_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_apcs_tz_clock_branch_ena_vote_s +{ + u32 sys_noc_cpuss_ahb_clk_ena : 1; + u32 tcsr_ahb_clk_ena : 1; + u32 qdss_cfg_ahb_clk_ena : 1; + u32 ce1_ahb_clk_ena : 1; + u32 ce1_axi_clk_ena : 1; + u32 ce1_clk_ena : 1; + u32 tlmm_clk_ena : 1; + u32 reserved0 : 1; + u32 tlmm_ahb_clk_ena : 1; + u32 reserved1 : 1; + u32 boot_rom_ahb_clk_ena : 1; + u32 qmip_pcie_ahb_clk_ena : 1; + u32 aggre_noc_pcie_axi_clk_ena : 1; + u32 prng_ahb_clk_ena : 1; + u32 tme_gpll0_clk_src_ena : 1; + u32 gpu_gpll0_clk_src_ena : 1; + u32 gpu_gpll0_div_clk_src_ena : 1; + u32 mss_gpll0_div_clk_src_ena : 1; + u32 tcu_anoc_pcie_qtb_clk_ena : 1; + u32 ddrss_pcie_sf_qtb_clk_ena : 1; + u32 cfg_noc_pcie_anoc_ahb_clk_ena : 1; + u32 cpuss_ahb_clk_ena : 1; + u32 pcie_0_phy_rchng_clk_ena : 1; + u32 pcie_1_phy_rchng_clk_ena : 1; + u32 pcie_1_phy_aux_clk_ena : 1; + u32 pcie_1_slv_q2a_axi_clk_ena : 1; + u32 pcie_1_slv_axi_clk_ena : 1; + u32 pcie_1_mstr_axi_clk_ena : 1; + u32 pcie_1_cfg_ahb_clk_ena : 1; + u32 pcie_1_aux_clk_ena : 1; + u32 pcie_1_pipe_clk_ena : 1; + u32 ddrss_gpll0_main_clk_src_ena : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_apcs_tz_clock_branch_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_apcs_tz_clock_branch_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_apcs_tz_clock_sleep_ena_vote_s +{ + u32 sys_noc_cpuss_ahb_clk_sleep_ena : 1; + u32 tcsr_ahb_clk_sleep_ena : 1; + u32 qdss_cfg_ahb_clk_sleep_ena : 1; + u32 ce1_ahb_clk_sleep_ena : 1; + u32 ce1_axi_clk_sleep_ena : 1; + u32 ce1_clk_sleep_ena : 1; + u32 tlmm_clk_sleep_ena : 1; + u32 reserved0 : 1; + u32 tlmm_ahb_clk_sleep_ena : 1; + u32 reserved1 : 1; + u32 boot_rom_ahb_clk_sleep_ena : 1; + u32 qmip_pcie_ahb_clk_sleep_ena : 1; + u32 aggre_noc_pcie_axi_clk_sleep_ena : 1; + u32 prng_ahb_clk_sleep_ena : 1; + u32 tme_gpll0_clk_src_sleep_ena : 1; + u32 gpu_gpll0_clk_src_sleep_ena : 1; + u32 gpu_gpll0_div_clk_src_sleep_ena : 1; + u32 mss_gpll0_div_clk_src_sleep_ena : 1; + u32 tcu_anoc_pcie_qtb_clk_sleep_ena : 1; + u32 ddrss_pcie_sf_qtb_clk_sleep_ena : 1; + u32 cfg_noc_pcie_anoc_ahb_clk_sleep_ena : 1; + u32 cpuss_ahb_clk_sleep_ena : 1; + u32 pcie_0_phy_rchng_clk_sleep_ena : 1; + u32 pcie_1_phy_rchng_clk_sleep_ena : 1; + u32 pcie_1_phy_aux_clk_sleep_ena : 1; + u32 pcie_1_slv_q2a_axi_clk_sleep_ena : 1; + u32 pcie_1_slv_axi_clk_sleep_ena : 1; + u32 pcie_1_mstr_axi_clk_sleep_ena : 1; + u32 pcie_1_cfg_ahb_clk_sleep_ena : 1; + u32 pcie_1_aux_clk_sleep_ena : 1; + u32 pcie_1_pipe_clk_sleep_ena : 1; + u32 ddrss_gpll0_main_clk_src_sleep_ena : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_apcs_tz_clock_sleep_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_apcs_tz_clock_sleep_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_apcs_tz_clock_branch_ena_vote_1_s +{ + u32 pcie_0_slv_axi_clk_ena : 1; + u32 pcie_0_mstr_axi_clk_ena : 1; + u32 pcie_0_cfg_ahb_clk_ena : 1; + u32 pcie_0_aux_clk_ena : 1; + u32 pcie_0_pipe_clk_ena : 1; + u32 pcie_0_slv_q2a_axi_clk_ena : 1; + u32 cnoc_pcie_sf_axi_clk_ena : 1; + u32 qupv3_i2c_s_ahb_clk_ena : 1; + u32 qupv3_i2c_core_clk_ena : 1; + u32 aggre_noc_south_axi_clk_ena : 1; + u32 qupv3_i2c_s0_clk_ena : 1; + u32 qupv3_i2c_s1_clk_ena : 1; + u32 qupv3_i2c_s2_clk_ena : 1; + u32 qupv3_i2c_s3_clk_ena : 1; + u32 qupv3_i2c_s4_clk_ena : 1; + u32 qupv3_i2c_s5_clk_ena : 1; + u32 qupv3_i2c_s6_clk_ena : 1; + u32 qupv3_i2c_s7_clk_ena : 1; + u32 qupv3_wrap1_core_2x_clk_ena : 1; + u32 qupv3_wrap1_core_clk_ena : 1; + u32 qupv3_wrap_1_m_ahb_clk_ena : 1; + u32 qupv3_wrap_1_s_ahb_clk_ena : 1; + u32 qupv3_wrap1_s0_clk_ena : 1; + u32 qupv3_wrap1_s1_clk_ena : 1; + u32 qupv3_wrap1_s2_clk_ena : 1; + u32 qupv3_wrap1_s3_clk_ena : 1; + u32 qupv3_wrap1_s4_clk_ena : 1; + u32 qupv3_wrap1_s5_clk_ena : 1; + u32 qupv3_wrap1_s6_clk_ena : 1; + u32 noc_pcie_north_dcd_xo_clk_ena : 1; + u32 qmip_aggre_noc_ahb_clk_ena : 1; + u32 anoc_pcie_pwrctl_clk_ena : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_apcs_tz_clock_branch_ena_vote_1_u +{ + struct ipa_gcc_hwio_def_gcc_apcs_tz_clock_branch_ena_vote_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_apcs_tz_clock_sleep_ena_vote_1_s +{ + u32 pcie_0_slv_axi_clk_sleep_ena : 1; + u32 pcie_0_mstr_axi_clk_sleep_ena : 1; + u32 pcie_0_cfg_ahb_clk_sleep_ena : 1; + u32 pcie_0_aux_clk_sleep_ena : 1; + u32 pcie_0_pipe_clk_sleep_ena : 1; + u32 pcie_0_slv_q2a_axi_clk_sleep_ena : 1; + u32 cnoc_pcie_sf_axi_clk_sleep_ena : 1; + u32 qupv3_i2c_s_ahb_clk_sleep_ena : 1; + u32 qupv3_i2c_core_clk_sleep_ena : 1; + u32 aggre_noc_south_axi_clk_sleep_ena : 1; + u32 qupv3_i2c_s0_clk_sleep_ena : 1; + u32 qupv3_i2c_s1_clk_sleep_ena : 1; + u32 qupv3_i2c_s2_clk_sleep_ena : 1; + u32 qupv3_i2c_s3_clk_sleep_ena : 1; + u32 qupv3_i2c_s4_clk_sleep_ena : 1; + u32 qupv3_i2c_s5_clk_sleep_ena : 1; + u32 qupv3_i2c_s6_clk_sleep_ena : 1; + u32 qupv3_i2c_s7_clk_sleep_ena : 1; + u32 qupv3_wrap1_core_2x_clk_sleep_ena : 1; + u32 qupv3_wrap1_core_clk_sleep_ena : 1; + u32 qupv3_wrap_1_m_ahb_clk_sleep_ena : 1; + u32 qupv3_wrap_1_s_ahb_clk_sleep_ena : 1; + u32 qupv3_wrap1_s0_clk_sleep_ena : 1; + u32 qupv3_wrap1_s1_clk_sleep_ena : 1; + u32 qupv3_wrap1_s2_clk_sleep_ena : 1; + u32 qupv3_wrap1_s3_clk_sleep_ena : 1; + u32 qupv3_wrap1_s4_clk_sleep_ena : 1; + u32 qupv3_wrap1_s5_clk_sleep_ena : 1; + u32 qupv3_wrap1_s6_clk_sleep_ena : 1; + u32 noc_pcie_north_dcd_xo_clk_sleep_ena : 1; + u32 qmip_aggre_noc_ahb_clk_sleep_ena : 1; + u32 anoc_pcie_pwrctl_clk_sleep_ena : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_apcs_tz_clock_sleep_ena_vote_1_u +{ + struct ipa_gcc_hwio_def_gcc_apcs_tz_clock_sleep_ena_vote_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_apcs_tz_clock_branch_ena_vote_2_s +{ + u32 qupv3_wrap2_core_clk_ena : 1; + u32 qupv3_wrap_2_s_ahb_clk_ena : 1; + u32 qupv3_wrap_2_m_ahb_clk_ena : 1; + u32 qupv3_wrap2_core_2x_clk_ena : 1; + u32 qupv3_wrap2_s0_clk_ena : 1; + u32 qupv3_wrap2_s1_clk_ena : 1; + u32 qupv3_wrap2_s2_clk_ena : 1; + u32 qupv3_wrap2_s3_clk_ena : 1; + u32 qupv3_wrap2_s4_clk_ena : 1; + u32 qupv3_wrap2_s5_clk_ena : 1; + u32 qupv3_wrap2_s6_clk_ena : 1; + u32 anoc_pcie_north_at_clk_ena : 1; + u32 anoc_pcie_tsctr_clk_ena : 1; + u32 anoc_pcie_qosgen_extref_clk_ena : 1; + u32 qupv3_i2c_s8_clk_ena : 1; + u32 qupv3_i2c_s9_clk_ena : 1; + u32 qupv3_wrap1_s7_clk_ena : 1; + u32 qupv3_wrap2_s7_clk_ena : 1; + u32 tme_gpll0_div2_clk_src_ena : 1; + u32 reserved0 : 13; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_apcs_tz_clock_branch_ena_vote_2_u +{ + struct ipa_gcc_hwio_def_gcc_apcs_tz_clock_branch_ena_vote_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_apcs_tz_clock_sleep_ena_vote_2_s +{ + u32 qupv3_wrap2_core_clk_sleep_ena : 1; + u32 qupv3_wrap_2_s_ahb_clk_sleep_ena : 1; + u32 qupv3_wrap_2_m_ahb_clk_sleep_ena : 1; + u32 qupv3_wrap2_core_2x_clk_sleep_ena : 1; + u32 qupv3_wrap2_s0_clk_sleep_ena : 1; + u32 qupv3_wrap2_s1_clk_sleep_ena : 1; + u32 qupv3_wrap2_s2_clk_sleep_ena : 1; + u32 qupv3_wrap2_s3_clk_sleep_ena : 1; + u32 qupv3_wrap2_s4_clk_sleep_ena : 1; + u32 qupv3_wrap2_s5_clk_sleep_ena : 1; + u32 qupv3_wrap2_s6_clk_sleep_ena : 1; + u32 anoc_pcie_north_at_clk_sleep_ena : 1; + u32 anoc_pcie_tsctr_clk_sleep_ena : 1; + u32 anoc_pcie_qosgen_extref_clk_sleep_ena : 1; + u32 qupv3_i2c_s8_clk_sleep_ena : 1; + u32 qupv3_i2c_s9_clk_sleep_ena : 1; + u32 qupv3_wrap1_s7_clk_sleep_ena : 1; + u32 qupv3_wrap2_s7_clk_sleep_ena : 1; + u32 tme_gpll0_div2_clk_src_sleep_ena : 1; + u32 reserved0 : 13; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_apcs_tz_clock_sleep_ena_vote_2_u +{ + struct ipa_gcc_hwio_def_gcc_apcs_tz_clock_sleep_ena_vote_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_apcs_tz_pll_branch_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_apcs_tz_pll_branch_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_apcs_tz_pll_branch_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_apcs_tz_pll_sleep_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_apcs_tz_pll_sleep_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_apcs_tz_pll_sleep_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_lpass_dsp_clock_branch_ena_vote_s +{ + u32 sys_noc_cpuss_ahb_clk_ena : 1; + u32 tcsr_ahb_clk_ena : 1; + u32 qdss_cfg_ahb_clk_ena : 1; + u32 ce1_ahb_clk_ena : 1; + u32 ce1_axi_clk_ena : 1; + u32 ce1_clk_ena : 1; + u32 tlmm_clk_ena : 1; + u32 reserved0 : 1; + u32 tlmm_ahb_clk_ena : 1; + u32 reserved1 : 1; + u32 boot_rom_ahb_clk_ena : 1; + u32 qmip_pcie_ahb_clk_ena : 1; + u32 aggre_noc_pcie_axi_clk_ena : 1; + u32 prng_ahb_clk_ena : 1; + u32 tme_gpll0_clk_src_ena : 1; + u32 gpu_gpll0_clk_src_ena : 1; + u32 gpu_gpll0_div_clk_src_ena : 1; + u32 mss_gpll0_div_clk_src_ena : 1; + u32 tcu_anoc_pcie_qtb_clk_ena : 1; + u32 ddrss_pcie_sf_qtb_clk_ena : 1; + u32 cfg_noc_pcie_anoc_ahb_clk_ena : 1; + u32 cpuss_ahb_clk_ena : 1; + u32 pcie_0_phy_rchng_clk_ena : 1; + u32 pcie_1_phy_rchng_clk_ena : 1; + u32 pcie_1_phy_aux_clk_ena : 1; + u32 pcie_1_slv_q2a_axi_clk_ena : 1; + u32 pcie_1_slv_axi_clk_ena : 1; + u32 pcie_1_mstr_axi_clk_ena : 1; + u32 pcie_1_cfg_ahb_clk_ena : 1; + u32 pcie_1_aux_clk_ena : 1; + u32 pcie_1_pipe_clk_ena : 1; + u32 ddrss_gpll0_main_clk_src_ena : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_lpass_dsp_clock_branch_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_lpass_dsp_clock_branch_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_lpass_dsp_clock_sleep_ena_vote_s +{ + u32 sys_noc_cpuss_ahb_clk_sleep_ena : 1; + u32 tcsr_ahb_clk_sleep_ena : 1; + u32 qdss_cfg_ahb_clk_sleep_ena : 1; + u32 ce1_ahb_clk_sleep_ena : 1; + u32 ce1_axi_clk_sleep_ena : 1; + u32 ce1_clk_sleep_ena : 1; + u32 tlmm_clk_sleep_ena : 1; + u32 reserved0 : 1; + u32 tlmm_ahb_clk_sleep_ena : 1; + u32 reserved1 : 1; + u32 boot_rom_ahb_clk_sleep_ena : 1; + u32 qmip_pcie_ahb_clk_sleep_ena : 1; + u32 aggre_noc_pcie_axi_clk_sleep_ena : 1; + u32 prng_ahb_clk_sleep_ena : 1; + u32 tme_gpll0_clk_src_sleep_ena : 1; + u32 gpu_gpll0_clk_src_sleep_ena : 1; + u32 gpu_gpll0_div_clk_src_sleep_ena : 1; + u32 mss_gpll0_div_clk_src_sleep_ena : 1; + u32 tcu_anoc_pcie_qtb_clk_sleep_ena : 1; + u32 ddrss_pcie_sf_qtb_clk_sleep_ena : 1; + u32 cfg_noc_pcie_anoc_ahb_clk_sleep_ena : 1; + u32 cpuss_ahb_clk_sleep_ena : 1; + u32 pcie_0_phy_rchng_clk_sleep_ena : 1; + u32 pcie_1_phy_rchng_clk_sleep_ena : 1; + u32 pcie_1_phy_aux_clk_sleep_ena : 1; + u32 pcie_1_slv_q2a_axi_clk_sleep_ena : 1; + u32 pcie_1_slv_axi_clk_sleep_ena : 1; + u32 pcie_1_mstr_axi_clk_sleep_ena : 1; + u32 pcie_1_cfg_ahb_clk_sleep_ena : 1; + u32 pcie_1_aux_clk_sleep_ena : 1; + u32 pcie_1_pipe_clk_sleep_ena : 1; + u32 ddrss_gpll0_main_clk_src_sleep_ena : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_lpass_dsp_clock_sleep_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_lpass_dsp_clock_sleep_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_lpass_dsp_clock_branch_ena_vote_1_s +{ + u32 pcie_0_slv_axi_clk_ena : 1; + u32 pcie_0_mstr_axi_clk_ena : 1; + u32 pcie_0_cfg_ahb_clk_ena : 1; + u32 pcie_0_aux_clk_ena : 1; + u32 pcie_0_pipe_clk_ena : 1; + u32 pcie_0_slv_q2a_axi_clk_ena : 1; + u32 cnoc_pcie_sf_axi_clk_ena : 1; + u32 qupv3_i2c_s_ahb_clk_ena : 1; + u32 qupv3_i2c_core_clk_ena : 1; + u32 aggre_noc_south_axi_clk_ena : 1; + u32 qupv3_i2c_s0_clk_ena : 1; + u32 qupv3_i2c_s1_clk_ena : 1; + u32 qupv3_i2c_s2_clk_ena : 1; + u32 qupv3_i2c_s3_clk_ena : 1; + u32 qupv3_i2c_s4_clk_ena : 1; + u32 qupv3_i2c_s5_clk_ena : 1; + u32 qupv3_i2c_s6_clk_ena : 1; + u32 qupv3_i2c_s7_clk_ena : 1; + u32 qupv3_wrap1_core_2x_clk_ena : 1; + u32 qupv3_wrap1_core_clk_ena : 1; + u32 qupv3_wrap_1_m_ahb_clk_ena : 1; + u32 qupv3_wrap_1_s_ahb_clk_ena : 1; + u32 qupv3_wrap1_s0_clk_ena : 1; + u32 qupv3_wrap1_s1_clk_ena : 1; + u32 qupv3_wrap1_s2_clk_ena : 1; + u32 qupv3_wrap1_s3_clk_ena : 1; + u32 qupv3_wrap1_s4_clk_ena : 1; + u32 qupv3_wrap1_s5_clk_ena : 1; + u32 qupv3_wrap1_s6_clk_ena : 1; + u32 noc_pcie_north_dcd_xo_clk_ena : 1; + u32 qmip_aggre_noc_ahb_clk_ena : 1; + u32 anoc_pcie_pwrctl_clk_ena : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_lpass_dsp_clock_branch_ena_vote_1_u +{ + struct ipa_gcc_hwio_def_gcc_lpass_dsp_clock_branch_ena_vote_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_lpass_dsp_clock_sleep_ena_vote_1_s +{ + u32 pcie_0_slv_axi_clk_sleep_ena : 1; + u32 pcie_0_mstr_axi_clk_sleep_ena : 1; + u32 pcie_0_cfg_ahb_clk_sleep_ena : 1; + u32 pcie_0_aux_clk_sleep_ena : 1; + u32 pcie_0_pipe_clk_sleep_ena : 1; + u32 pcie_0_slv_q2a_axi_clk_sleep_ena : 1; + u32 cnoc_pcie_sf_axi_clk_sleep_ena : 1; + u32 qupv3_i2c_s_ahb_clk_sleep_ena : 1; + u32 qupv3_i2c_core_clk_sleep_ena : 1; + u32 aggre_noc_south_axi_clk_sleep_ena : 1; + u32 qupv3_i2c_s0_clk_sleep_ena : 1; + u32 qupv3_i2c_s1_clk_sleep_ena : 1; + u32 qupv3_i2c_s2_clk_sleep_ena : 1; + u32 qupv3_i2c_s3_clk_sleep_ena : 1; + u32 qupv3_i2c_s4_clk_sleep_ena : 1; + u32 qupv3_i2c_s5_clk_sleep_ena : 1; + u32 qupv3_i2c_s6_clk_sleep_ena : 1; + u32 qupv3_i2c_s7_clk_sleep_ena : 1; + u32 qupv3_wrap1_core_2x_clk_sleep_ena : 1; + u32 qupv3_wrap1_core_clk_sleep_ena : 1; + u32 qupv3_wrap_1_m_ahb_clk_sleep_ena : 1; + u32 qupv3_wrap_1_s_ahb_clk_sleep_ena : 1; + u32 qupv3_wrap1_s0_clk_sleep_ena : 1; + u32 qupv3_wrap1_s1_clk_sleep_ena : 1; + u32 qupv3_wrap1_s2_clk_sleep_ena : 1; + u32 qupv3_wrap1_s3_clk_sleep_ena : 1; + u32 qupv3_wrap1_s4_clk_sleep_ena : 1; + u32 qupv3_wrap1_s5_clk_sleep_ena : 1; + u32 qupv3_wrap1_s6_clk_sleep_ena : 1; + u32 noc_pcie_north_dcd_xo_clk_sleep_ena : 1; + u32 qmip_aggre_noc_ahb_clk_sleep_ena : 1; + u32 anoc_pcie_pwrctl_clk_sleep_ena : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_lpass_dsp_clock_sleep_ena_vote_1_u +{ + struct ipa_gcc_hwio_def_gcc_lpass_dsp_clock_sleep_ena_vote_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_lpass_dsp_clock_branch_ena_vote_2_s +{ + u32 qupv3_wrap2_core_clk_ena : 1; + u32 qupv3_wrap_2_s_ahb_clk_ena : 1; + u32 qupv3_wrap_2_m_ahb_clk_ena : 1; + u32 qupv3_wrap2_core_2x_clk_ena : 1; + u32 qupv3_wrap2_s0_clk_ena : 1; + u32 qupv3_wrap2_s1_clk_ena : 1; + u32 qupv3_wrap2_s2_clk_ena : 1; + u32 qupv3_wrap2_s3_clk_ena : 1; + u32 qupv3_wrap2_s4_clk_ena : 1; + u32 qupv3_wrap2_s5_clk_ena : 1; + u32 qupv3_wrap2_s6_clk_ena : 1; + u32 anoc_pcie_north_at_clk_ena : 1; + u32 anoc_pcie_tsctr_clk_ena : 1; + u32 anoc_pcie_qosgen_extref_clk_ena : 1; + u32 qupv3_i2c_s8_clk_ena : 1; + u32 qupv3_i2c_s9_clk_ena : 1; + u32 qupv3_wrap1_s7_clk_ena : 1; + u32 qupv3_wrap2_s7_clk_ena : 1; + u32 tme_gpll0_div2_clk_src_ena : 1; + u32 reserved0 : 13; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_lpass_dsp_clock_branch_ena_vote_2_u +{ + struct ipa_gcc_hwio_def_gcc_lpass_dsp_clock_branch_ena_vote_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_lpass_dsp_clock_sleep_ena_vote_2_s +{ + u32 qupv3_wrap2_core_clk_sleep_ena : 1; + u32 qupv3_wrap_2_s_ahb_clk_sleep_ena : 1; + u32 qupv3_wrap_2_m_ahb_clk_sleep_ena : 1; + u32 qupv3_wrap2_core_2x_clk_sleep_ena : 1; + u32 qupv3_wrap2_s0_clk_sleep_ena : 1; + u32 qupv3_wrap2_s1_clk_sleep_ena : 1; + u32 qupv3_wrap2_s2_clk_sleep_ena : 1; + u32 qupv3_wrap2_s3_clk_sleep_ena : 1; + u32 qupv3_wrap2_s4_clk_sleep_ena : 1; + u32 qupv3_wrap2_s5_clk_sleep_ena : 1; + u32 qupv3_wrap2_s6_clk_sleep_ena : 1; + u32 anoc_pcie_north_at_clk_sleep_ena : 1; + u32 anoc_pcie_tsctr_clk_sleep_ena : 1; + u32 anoc_pcie_qosgen_extref_clk_sleep_ena : 1; + u32 qupv3_i2c_s8_clk_sleep_ena : 1; + u32 qupv3_i2c_s9_clk_sleep_ena : 1; + u32 qupv3_wrap1_s7_clk_sleep_ena : 1; + u32 qupv3_wrap2_s7_clk_sleep_ena : 1; + u32 tme_gpll0_div2_clk_src_sleep_ena : 1; + u32 reserved0 : 13; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_lpass_dsp_clock_sleep_ena_vote_2_u +{ + struct ipa_gcc_hwio_def_gcc_lpass_dsp_clock_sleep_ena_vote_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_lpass_dsp_pll_branch_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_lpass_dsp_pll_branch_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_lpass_dsp_pll_branch_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_lpass_dsp_pll_sleep_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_lpass_dsp_pll_sleep_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_lpass_dsp_pll_sleep_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_turing_dsp_clock_branch_ena_vote_s +{ + u32 sys_noc_cpuss_ahb_clk_ena : 1; + u32 tcsr_ahb_clk_ena : 1; + u32 qdss_cfg_ahb_clk_ena : 1; + u32 ce1_ahb_clk_ena : 1; + u32 ce1_axi_clk_ena : 1; + u32 ce1_clk_ena : 1; + u32 tlmm_clk_ena : 1; + u32 reserved0 : 1; + u32 tlmm_ahb_clk_ena : 1; + u32 reserved1 : 1; + u32 boot_rom_ahb_clk_ena : 1; + u32 qmip_pcie_ahb_clk_ena : 1; + u32 aggre_noc_pcie_axi_clk_ena : 1; + u32 prng_ahb_clk_ena : 1; + u32 tme_gpll0_clk_src_ena : 1; + u32 gpu_gpll0_clk_src_ena : 1; + u32 gpu_gpll0_div_clk_src_ena : 1; + u32 mss_gpll0_div_clk_src_ena : 1; + u32 tcu_anoc_pcie_qtb_clk_ena : 1; + u32 ddrss_pcie_sf_qtb_clk_ena : 1; + u32 cfg_noc_pcie_anoc_ahb_clk_ena : 1; + u32 cpuss_ahb_clk_ena : 1; + u32 pcie_0_phy_rchng_clk_ena : 1; + u32 pcie_1_phy_rchng_clk_ena : 1; + u32 pcie_1_phy_aux_clk_ena : 1; + u32 pcie_1_slv_q2a_axi_clk_ena : 1; + u32 pcie_1_slv_axi_clk_ena : 1; + u32 pcie_1_mstr_axi_clk_ena : 1; + u32 pcie_1_cfg_ahb_clk_ena : 1; + u32 pcie_1_aux_clk_ena : 1; + u32 pcie_1_pipe_clk_ena : 1; + u32 ddrss_gpll0_main_clk_src_ena : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_turing_dsp_clock_branch_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_turing_dsp_clock_branch_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_turing_dsp_clock_sleep_ena_vote_s +{ + u32 sys_noc_cpuss_ahb_clk_sleep_ena : 1; + u32 tcsr_ahb_clk_sleep_ena : 1; + u32 qdss_cfg_ahb_clk_sleep_ena : 1; + u32 ce1_ahb_clk_sleep_ena : 1; + u32 ce1_axi_clk_sleep_ena : 1; + u32 ce1_clk_sleep_ena : 1; + u32 tlmm_clk_sleep_ena : 1; + u32 reserved0 : 1; + u32 tlmm_ahb_clk_sleep_ena : 1; + u32 reserved1 : 1; + u32 boot_rom_ahb_clk_sleep_ena : 1; + u32 qmip_pcie_ahb_clk_sleep_ena : 1; + u32 aggre_noc_pcie_axi_clk_sleep_ena : 1; + u32 prng_ahb_clk_sleep_ena : 1; + u32 tme_gpll0_clk_src_sleep_ena : 1; + u32 gpu_gpll0_clk_src_sleep_ena : 1; + u32 gpu_gpll0_div_clk_src_sleep_ena : 1; + u32 mss_gpll0_div_clk_src_sleep_ena : 1; + u32 tcu_anoc_pcie_qtb_clk_sleep_ena : 1; + u32 ddrss_pcie_sf_qtb_clk_sleep_ena : 1; + u32 cfg_noc_pcie_anoc_ahb_clk_sleep_ena : 1; + u32 cpuss_ahb_clk_sleep_ena : 1; + u32 pcie_0_phy_rchng_clk_sleep_ena : 1; + u32 pcie_1_phy_rchng_clk_sleep_ena : 1; + u32 pcie_1_phy_aux_clk_sleep_ena : 1; + u32 pcie_1_slv_q2a_axi_clk_sleep_ena : 1; + u32 pcie_1_slv_axi_clk_sleep_ena : 1; + u32 pcie_1_mstr_axi_clk_sleep_ena : 1; + u32 pcie_1_cfg_ahb_clk_sleep_ena : 1; + u32 pcie_1_aux_clk_sleep_ena : 1; + u32 pcie_1_pipe_clk_sleep_ena : 1; + u32 ddrss_gpll0_main_clk_src_sleep_ena : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_turing_dsp_clock_sleep_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_turing_dsp_clock_sleep_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_turing_dsp_clock_branch_ena_vote_1_s +{ + u32 pcie_0_slv_axi_clk_ena : 1; + u32 pcie_0_mstr_axi_clk_ena : 1; + u32 pcie_0_cfg_ahb_clk_ena : 1; + u32 pcie_0_aux_clk_ena : 1; + u32 pcie_0_pipe_clk_ena : 1; + u32 pcie_0_slv_q2a_axi_clk_ena : 1; + u32 cnoc_pcie_sf_axi_clk_ena : 1; + u32 qupv3_i2c_s_ahb_clk_ena : 1; + u32 qupv3_i2c_core_clk_ena : 1; + u32 aggre_noc_south_axi_clk_ena : 1; + u32 qupv3_i2c_s0_clk_ena : 1; + u32 qupv3_i2c_s1_clk_ena : 1; + u32 qupv3_i2c_s2_clk_ena : 1; + u32 qupv3_i2c_s3_clk_ena : 1; + u32 qupv3_i2c_s4_clk_ena : 1; + u32 qupv3_i2c_s5_clk_ena : 1; + u32 qupv3_i2c_s6_clk_ena : 1; + u32 qupv3_i2c_s7_clk_ena : 1; + u32 qupv3_wrap1_core_2x_clk_ena : 1; + u32 qupv3_wrap1_core_clk_ena : 1; + u32 qupv3_wrap_1_m_ahb_clk_ena : 1; + u32 qupv3_wrap_1_s_ahb_clk_ena : 1; + u32 qupv3_wrap1_s0_clk_ena : 1; + u32 qupv3_wrap1_s1_clk_ena : 1; + u32 qupv3_wrap1_s2_clk_ena : 1; + u32 qupv3_wrap1_s3_clk_ena : 1; + u32 qupv3_wrap1_s4_clk_ena : 1; + u32 qupv3_wrap1_s5_clk_ena : 1; + u32 qupv3_wrap1_s6_clk_ena : 1; + u32 noc_pcie_north_dcd_xo_clk_ena : 1; + u32 qmip_aggre_noc_ahb_clk_ena : 1; + u32 anoc_pcie_pwrctl_clk_ena : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_turing_dsp_clock_branch_ena_vote_1_u +{ + struct ipa_gcc_hwio_def_gcc_turing_dsp_clock_branch_ena_vote_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_turing_dsp_clock_sleep_ena_vote_1_s +{ + u32 pcie_0_slv_axi_clk_sleep_ena : 1; + u32 pcie_0_mstr_axi_clk_sleep_ena : 1; + u32 pcie_0_cfg_ahb_clk_sleep_ena : 1; + u32 pcie_0_aux_clk_sleep_ena : 1; + u32 pcie_0_pipe_clk_sleep_ena : 1; + u32 pcie_0_slv_q2a_axi_clk_sleep_ena : 1; + u32 cnoc_pcie_sf_axi_clk_sleep_ena : 1; + u32 qupv3_i2c_s_ahb_clk_sleep_ena : 1; + u32 qupv3_i2c_core_clk_sleep_ena : 1; + u32 aggre_noc_south_axi_clk_sleep_ena : 1; + u32 qupv3_i2c_s0_clk_sleep_ena : 1; + u32 qupv3_i2c_s1_clk_sleep_ena : 1; + u32 qupv3_i2c_s2_clk_sleep_ena : 1; + u32 qupv3_i2c_s3_clk_sleep_ena : 1; + u32 qupv3_i2c_s4_clk_sleep_ena : 1; + u32 qupv3_i2c_s5_clk_sleep_ena : 1; + u32 qupv3_i2c_s6_clk_sleep_ena : 1; + u32 qupv3_i2c_s7_clk_sleep_ena : 1; + u32 qupv3_wrap1_core_2x_clk_sleep_ena : 1; + u32 qupv3_wrap1_core_clk_sleep_ena : 1; + u32 qupv3_wrap_1_m_ahb_clk_sleep_ena : 1; + u32 qupv3_wrap_1_s_ahb_clk_sleep_ena : 1; + u32 qupv3_wrap1_s0_clk_sleep_ena : 1; + u32 qupv3_wrap1_s1_clk_sleep_ena : 1; + u32 qupv3_wrap1_s2_clk_sleep_ena : 1; + u32 qupv3_wrap1_s3_clk_sleep_ena : 1; + u32 qupv3_wrap1_s4_clk_sleep_ena : 1; + u32 qupv3_wrap1_s5_clk_sleep_ena : 1; + u32 qupv3_wrap1_s6_clk_sleep_ena : 1; + u32 noc_pcie_north_dcd_xo_clk_sleep_ena : 1; + u32 qmip_aggre_noc_ahb_clk_sleep_ena : 1; + u32 anoc_pcie_pwrctl_clk_sleep_ena : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_turing_dsp_clock_sleep_ena_vote_1_u +{ + struct ipa_gcc_hwio_def_gcc_turing_dsp_clock_sleep_ena_vote_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_turing_dsp_clock_branch_ena_vote_2_s +{ + u32 qupv3_wrap2_core_clk_ena : 1; + u32 qupv3_wrap_2_s_ahb_clk_ena : 1; + u32 qupv3_wrap_2_m_ahb_clk_ena : 1; + u32 qupv3_wrap2_core_2x_clk_ena : 1; + u32 qupv3_wrap2_s0_clk_ena : 1; + u32 qupv3_wrap2_s1_clk_ena : 1; + u32 qupv3_wrap2_s2_clk_ena : 1; + u32 qupv3_wrap2_s3_clk_ena : 1; + u32 qupv3_wrap2_s4_clk_ena : 1; + u32 qupv3_wrap2_s5_clk_ena : 1; + u32 qupv3_wrap2_s6_clk_ena : 1; + u32 anoc_pcie_north_at_clk_ena : 1; + u32 anoc_pcie_tsctr_clk_ena : 1; + u32 anoc_pcie_qosgen_extref_clk_ena : 1; + u32 qupv3_i2c_s8_clk_ena : 1; + u32 qupv3_i2c_s9_clk_ena : 1; + u32 qupv3_wrap1_s7_clk_ena : 1; + u32 qupv3_wrap2_s7_clk_ena : 1; + u32 tme_gpll0_div2_clk_src_ena : 1; + u32 reserved0 : 13; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_turing_dsp_clock_branch_ena_vote_2_u +{ + struct ipa_gcc_hwio_def_gcc_turing_dsp_clock_branch_ena_vote_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_turing_dsp_clock_sleep_ena_vote_2_s +{ + u32 qupv3_wrap2_core_clk_sleep_ena : 1; + u32 qupv3_wrap_2_s_ahb_clk_sleep_ena : 1; + u32 qupv3_wrap_2_m_ahb_clk_sleep_ena : 1; + u32 qupv3_wrap2_core_2x_clk_sleep_ena : 1; + u32 qupv3_wrap2_s0_clk_sleep_ena : 1; + u32 qupv3_wrap2_s1_clk_sleep_ena : 1; + u32 qupv3_wrap2_s2_clk_sleep_ena : 1; + u32 qupv3_wrap2_s3_clk_sleep_ena : 1; + u32 qupv3_wrap2_s4_clk_sleep_ena : 1; + u32 qupv3_wrap2_s5_clk_sleep_ena : 1; + u32 qupv3_wrap2_s6_clk_sleep_ena : 1; + u32 anoc_pcie_north_at_clk_sleep_ena : 1; + u32 anoc_pcie_tsctr_clk_sleep_ena : 1; + u32 anoc_pcie_qosgen_extref_clk_sleep_ena : 1; + u32 qupv3_i2c_s8_clk_sleep_ena : 1; + u32 qupv3_i2c_s9_clk_sleep_ena : 1; + u32 qupv3_wrap1_s7_clk_sleep_ena : 1; + u32 qupv3_wrap2_s7_clk_sleep_ena : 1; + u32 tme_gpll0_div2_clk_src_sleep_ena : 1; + u32 reserved0 : 13; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_turing_dsp_clock_sleep_ena_vote_2_u +{ + struct ipa_gcc_hwio_def_gcc_turing_dsp_clock_sleep_ena_vote_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_turing_dsp_pll_branch_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_turing_dsp_pll_branch_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_turing_dsp_pll_branch_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_turing_dsp_pll_sleep_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_turing_dsp_pll_sleep_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_turing_dsp_pll_sleep_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPARE_CLOCK_BRANCH_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spare_clock_branch_ena_vote_s +{ + u32 sys_noc_cpuss_ahb_clk_ena : 1; + u32 tcsr_ahb_clk_ena : 1; + u32 qdss_cfg_ahb_clk_ena : 1; + u32 ce1_ahb_clk_ena : 1; + u32 ce1_axi_clk_ena : 1; + u32 ce1_clk_ena : 1; + u32 tlmm_clk_ena : 1; + u32 reserved0 : 1; + u32 tlmm_ahb_clk_ena : 1; + u32 reserved1 : 1; + u32 boot_rom_ahb_clk_ena : 1; + u32 qmip_pcie_ahb_clk_ena : 1; + u32 aggre_noc_pcie_axi_clk_ena : 1; + u32 prng_ahb_clk_ena : 1; + u32 tme_gpll0_clk_src_ena : 1; + u32 gpu_gpll0_clk_src_ena : 1; + u32 gpu_gpll0_div_clk_src_ena : 1; + u32 mss_gpll0_div_clk_src_ena : 1; + u32 tcu_anoc_pcie_qtb_clk_ena : 1; + u32 ddrss_pcie_sf_qtb_clk_ena : 1; + u32 cfg_noc_pcie_anoc_ahb_clk_ena : 1; + u32 cpuss_ahb_clk_ena : 1; + u32 pcie_0_phy_rchng_clk_ena : 1; + u32 pcie_1_phy_rchng_clk_ena : 1; + u32 pcie_1_phy_aux_clk_ena : 1; + u32 pcie_1_slv_q2a_axi_clk_ena : 1; + u32 pcie_1_slv_axi_clk_ena : 1; + u32 pcie_1_mstr_axi_clk_ena : 1; + u32 pcie_1_cfg_ahb_clk_ena : 1; + u32 pcie_1_aux_clk_ena : 1; + u32 pcie_1_pipe_clk_ena : 1; + u32 ddrss_gpll0_main_clk_src_ena : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spare_clock_branch_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_spare_clock_branch_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPARE_CLOCK_SLEEP_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spare_clock_sleep_ena_vote_s +{ + u32 sys_noc_cpuss_ahb_clk_sleep_ena : 1; + u32 tcsr_ahb_clk_sleep_ena : 1; + u32 qdss_cfg_ahb_clk_sleep_ena : 1; + u32 ce1_ahb_clk_sleep_ena : 1; + u32 ce1_axi_clk_sleep_ena : 1; + u32 ce1_clk_sleep_ena : 1; + u32 tlmm_clk_sleep_ena : 1; + u32 reserved0 : 1; + u32 tlmm_ahb_clk_sleep_ena : 1; + u32 reserved1 : 1; + u32 boot_rom_ahb_clk_sleep_ena : 1; + u32 qmip_pcie_ahb_clk_sleep_ena : 1; + u32 aggre_noc_pcie_axi_clk_sleep_ena : 1; + u32 prng_ahb_clk_sleep_ena : 1; + u32 tme_gpll0_clk_src_sleep_ena : 1; + u32 gpu_gpll0_clk_src_sleep_ena : 1; + u32 gpu_gpll0_div_clk_src_sleep_ena : 1; + u32 mss_gpll0_div_clk_src_sleep_ena : 1; + u32 tcu_anoc_pcie_qtb_clk_sleep_ena : 1; + u32 ddrss_pcie_sf_qtb_clk_sleep_ena : 1; + u32 cfg_noc_pcie_anoc_ahb_clk_sleep_ena : 1; + u32 cpuss_ahb_clk_sleep_ena : 1; + u32 pcie_0_phy_rchng_clk_sleep_ena : 1; + u32 pcie_1_phy_rchng_clk_sleep_ena : 1; + u32 pcie_1_phy_aux_clk_sleep_ena : 1; + u32 pcie_1_slv_q2a_axi_clk_sleep_ena : 1; + u32 pcie_1_slv_axi_clk_sleep_ena : 1; + u32 pcie_1_mstr_axi_clk_sleep_ena : 1; + u32 pcie_1_cfg_ahb_clk_sleep_ena : 1; + u32 pcie_1_aux_clk_sleep_ena : 1; + u32 pcie_1_pipe_clk_sleep_ena : 1; + u32 ddrss_gpll0_main_clk_src_sleep_ena : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spare_clock_sleep_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_spare_clock_sleep_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spare_clock_branch_ena_vote_1_s +{ + u32 pcie_0_slv_axi_clk_ena : 1; + u32 pcie_0_mstr_axi_clk_ena : 1; + u32 pcie_0_cfg_ahb_clk_ena : 1; + u32 pcie_0_aux_clk_ena : 1; + u32 pcie_0_pipe_clk_ena : 1; + u32 pcie_0_slv_q2a_axi_clk_ena : 1; + u32 cnoc_pcie_sf_axi_clk_ena : 1; + u32 qupv3_i2c_s_ahb_clk_ena : 1; + u32 qupv3_i2c_core_clk_ena : 1; + u32 aggre_noc_south_axi_clk_ena : 1; + u32 qupv3_i2c_s0_clk_ena : 1; + u32 qupv3_i2c_s1_clk_ena : 1; + u32 qupv3_i2c_s2_clk_ena : 1; + u32 qupv3_i2c_s3_clk_ena : 1; + u32 qupv3_i2c_s4_clk_ena : 1; + u32 qupv3_i2c_s5_clk_ena : 1; + u32 qupv3_i2c_s6_clk_ena : 1; + u32 qupv3_i2c_s7_clk_ena : 1; + u32 qupv3_wrap1_core_2x_clk_ena : 1; + u32 qupv3_wrap1_core_clk_ena : 1; + u32 qupv3_wrap_1_m_ahb_clk_ena : 1; + u32 qupv3_wrap_1_s_ahb_clk_ena : 1; + u32 qupv3_wrap1_s0_clk_ena : 1; + u32 qupv3_wrap1_s1_clk_ena : 1; + u32 qupv3_wrap1_s2_clk_ena : 1; + u32 qupv3_wrap1_s3_clk_ena : 1; + u32 qupv3_wrap1_s4_clk_ena : 1; + u32 qupv3_wrap1_s5_clk_ena : 1; + u32 qupv3_wrap1_s6_clk_ena : 1; + u32 noc_pcie_north_dcd_xo_clk_ena : 1; + u32 qmip_aggre_noc_ahb_clk_ena : 1; + u32 anoc_pcie_pwrctl_clk_ena : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spare_clock_branch_ena_vote_1_u +{ + struct ipa_gcc_hwio_def_gcc_spare_clock_branch_ena_vote_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spare_clock_sleep_ena_vote_1_s +{ + u32 pcie_0_slv_axi_clk_sleep_ena : 1; + u32 pcie_0_mstr_axi_clk_sleep_ena : 1; + u32 pcie_0_cfg_ahb_clk_sleep_ena : 1; + u32 pcie_0_aux_clk_sleep_ena : 1; + u32 pcie_0_pipe_clk_sleep_ena : 1; + u32 pcie_0_slv_q2a_axi_clk_sleep_ena : 1; + u32 cnoc_pcie_sf_axi_clk_sleep_ena : 1; + u32 qupv3_i2c_s_ahb_clk_sleep_ena : 1; + u32 qupv3_i2c_core_clk_sleep_ena : 1; + u32 aggre_noc_south_axi_clk_sleep_ena : 1; + u32 qupv3_i2c_s0_clk_sleep_ena : 1; + u32 qupv3_i2c_s1_clk_sleep_ena : 1; + u32 qupv3_i2c_s2_clk_sleep_ena : 1; + u32 qupv3_i2c_s3_clk_sleep_ena : 1; + u32 qupv3_i2c_s4_clk_sleep_ena : 1; + u32 qupv3_i2c_s5_clk_sleep_ena : 1; + u32 qupv3_i2c_s6_clk_sleep_ena : 1; + u32 qupv3_i2c_s7_clk_sleep_ena : 1; + u32 qupv3_wrap1_core_2x_clk_sleep_ena : 1; + u32 qupv3_wrap1_core_clk_sleep_ena : 1; + u32 qupv3_wrap_1_m_ahb_clk_sleep_ena : 1; + u32 qupv3_wrap_1_s_ahb_clk_sleep_ena : 1; + u32 qupv3_wrap1_s0_clk_sleep_ena : 1; + u32 qupv3_wrap1_s1_clk_sleep_ena : 1; + u32 qupv3_wrap1_s2_clk_sleep_ena : 1; + u32 qupv3_wrap1_s3_clk_sleep_ena : 1; + u32 qupv3_wrap1_s4_clk_sleep_ena : 1; + u32 qupv3_wrap1_s5_clk_sleep_ena : 1; + u32 qupv3_wrap1_s6_clk_sleep_ena : 1; + u32 noc_pcie_north_dcd_xo_clk_sleep_ena : 1; + u32 qmip_aggre_noc_ahb_clk_sleep_ena : 1; + u32 anoc_pcie_pwrctl_clk_sleep_ena : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spare_clock_sleep_ena_vote_1_u +{ + struct ipa_gcc_hwio_def_gcc_spare_clock_sleep_ena_vote_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spare_clock_branch_ena_vote_2_s +{ + u32 qupv3_wrap2_core_clk_ena : 1; + u32 qupv3_wrap_2_s_ahb_clk_ena : 1; + u32 qupv3_wrap_2_m_ahb_clk_ena : 1; + u32 qupv3_wrap2_core_2x_clk_ena : 1; + u32 qupv3_wrap2_s0_clk_ena : 1; + u32 qupv3_wrap2_s1_clk_ena : 1; + u32 qupv3_wrap2_s2_clk_ena : 1; + u32 qupv3_wrap2_s3_clk_ena : 1; + u32 qupv3_wrap2_s4_clk_ena : 1; + u32 qupv3_wrap2_s5_clk_ena : 1; + u32 qupv3_wrap2_s6_clk_ena : 1; + u32 anoc_pcie_north_at_clk_ena : 1; + u32 anoc_pcie_tsctr_clk_ena : 1; + u32 anoc_pcie_qosgen_extref_clk_ena : 1; + u32 qupv3_i2c_s8_clk_ena : 1; + u32 qupv3_i2c_s9_clk_ena : 1; + u32 qupv3_wrap1_s7_clk_ena : 1; + u32 qupv3_wrap2_s7_clk_ena : 1; + u32 tme_gpll0_div2_clk_src_ena : 1; + u32 reserved0 : 13; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spare_clock_branch_ena_vote_2_u +{ + struct ipa_gcc_hwio_def_gcc_spare_clock_branch_ena_vote_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spare_clock_sleep_ena_vote_2_s +{ + u32 qupv3_wrap2_core_clk_sleep_ena : 1; + u32 qupv3_wrap_2_s_ahb_clk_sleep_ena : 1; + u32 qupv3_wrap_2_m_ahb_clk_sleep_ena : 1; + u32 qupv3_wrap2_core_2x_clk_sleep_ena : 1; + u32 qupv3_wrap2_s0_clk_sleep_ena : 1; + u32 qupv3_wrap2_s1_clk_sleep_ena : 1; + u32 qupv3_wrap2_s2_clk_sleep_ena : 1; + u32 qupv3_wrap2_s3_clk_sleep_ena : 1; + u32 qupv3_wrap2_s4_clk_sleep_ena : 1; + u32 qupv3_wrap2_s5_clk_sleep_ena : 1; + u32 qupv3_wrap2_s6_clk_sleep_ena : 1; + u32 anoc_pcie_north_at_clk_sleep_ena : 1; + u32 anoc_pcie_tsctr_clk_sleep_ena : 1; + u32 anoc_pcie_qosgen_extref_clk_sleep_ena : 1; + u32 qupv3_i2c_s8_clk_sleep_ena : 1; + u32 qupv3_i2c_s9_clk_sleep_ena : 1; + u32 qupv3_wrap1_s7_clk_sleep_ena : 1; + u32 qupv3_wrap2_s7_clk_sleep_ena : 1; + u32 tme_gpll0_div2_clk_src_sleep_ena : 1; + u32 reserved0 : 13; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spare_clock_sleep_ena_vote_2_u +{ + struct ipa_gcc_hwio_def_gcc_spare_clock_sleep_ena_vote_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPARE_PLL_BRANCH_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spare_pll_branch_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spare_pll_branch_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_spare_pll_branch_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPARE_PLL_SLEEP_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spare_pll_sleep_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spare_pll_sleep_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_spare_pll_sleep_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_q6_clock_branch_ena_vote_s +{ + u32 sys_noc_cpuss_ahb_clk_ena : 1; + u32 tcsr_ahb_clk_ena : 1; + u32 qdss_cfg_ahb_clk_ena : 1; + u32 ce1_ahb_clk_ena : 1; + u32 ce1_axi_clk_ena : 1; + u32 ce1_clk_ena : 1; + u32 tlmm_clk_ena : 1; + u32 reserved0 : 1; + u32 tlmm_ahb_clk_ena : 1; + u32 reserved1 : 1; + u32 boot_rom_ahb_clk_ena : 1; + u32 qmip_pcie_ahb_clk_ena : 1; + u32 aggre_noc_pcie_axi_clk_ena : 1; + u32 prng_ahb_clk_ena : 1; + u32 tme_gpll0_clk_src_ena : 1; + u32 gpu_gpll0_clk_src_ena : 1; + u32 gpu_gpll0_div_clk_src_ena : 1; + u32 mss_gpll0_div_clk_src_ena : 1; + u32 tcu_anoc_pcie_qtb_clk_ena : 1; + u32 ddrss_pcie_sf_qtb_clk_ena : 1; + u32 cfg_noc_pcie_anoc_ahb_clk_ena : 1; + u32 cpuss_ahb_clk_ena : 1; + u32 pcie_0_phy_rchng_clk_ena : 1; + u32 pcie_1_phy_rchng_clk_ena : 1; + u32 pcie_1_phy_aux_clk_ena : 1; + u32 pcie_1_slv_q2a_axi_clk_ena : 1; + u32 pcie_1_slv_axi_clk_ena : 1; + u32 pcie_1_mstr_axi_clk_ena : 1; + u32 pcie_1_cfg_ahb_clk_ena : 1; + u32 pcie_1_aux_clk_ena : 1; + u32 pcie_1_pipe_clk_ena : 1; + u32 ddrss_gpll0_main_clk_src_ena : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_q6_clock_branch_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_mss_q6_clock_branch_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_q6_clock_sleep_ena_vote_s +{ + u32 sys_noc_cpuss_ahb_clk_sleep_ena : 1; + u32 tcsr_ahb_clk_sleep_ena : 1; + u32 qdss_cfg_ahb_clk_sleep_ena : 1; + u32 ce1_ahb_clk_sleep_ena : 1; + u32 ce1_axi_clk_sleep_ena : 1; + u32 ce1_clk_sleep_ena : 1; + u32 tlmm_clk_sleep_ena : 1; + u32 reserved0 : 1; + u32 tlmm_ahb_clk_sleep_ena : 1; + u32 reserved1 : 1; + u32 boot_rom_ahb_clk_sleep_ena : 1; + u32 qmip_pcie_ahb_clk_sleep_ena : 1; + u32 aggre_noc_pcie_axi_clk_sleep_ena : 1; + u32 prng_ahb_clk_sleep_ena : 1; + u32 tme_gpll0_clk_src_sleep_ena : 1; + u32 gpu_gpll0_clk_src_sleep_ena : 1; + u32 gpu_gpll0_div_clk_src_sleep_ena : 1; + u32 mss_gpll0_div_clk_src_sleep_ena : 1; + u32 tcu_anoc_pcie_qtb_clk_sleep_ena : 1; + u32 ddrss_pcie_sf_qtb_clk_sleep_ena : 1; + u32 cfg_noc_pcie_anoc_ahb_clk_sleep_ena : 1; + u32 cpuss_ahb_clk_sleep_ena : 1; + u32 pcie_0_phy_rchng_clk_sleep_ena : 1; + u32 pcie_1_phy_rchng_clk_sleep_ena : 1; + u32 pcie_1_phy_aux_clk_sleep_ena : 1; + u32 pcie_1_slv_q2a_axi_clk_sleep_ena : 1; + u32 pcie_1_slv_axi_clk_sleep_ena : 1; + u32 pcie_1_mstr_axi_clk_sleep_ena : 1; + u32 pcie_1_cfg_ahb_clk_sleep_ena : 1; + u32 pcie_1_aux_clk_sleep_ena : 1; + u32 pcie_1_pipe_clk_sleep_ena : 1; + u32 ddrss_gpll0_main_clk_src_sleep_ena : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_q6_clock_sleep_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_mss_q6_clock_sleep_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_q6_clock_branch_ena_vote_1_s +{ + u32 pcie_0_slv_axi_clk_ena : 1; + u32 pcie_0_mstr_axi_clk_ena : 1; + u32 pcie_0_cfg_ahb_clk_ena : 1; + u32 pcie_0_aux_clk_ena : 1; + u32 pcie_0_pipe_clk_ena : 1; + u32 pcie_0_slv_q2a_axi_clk_ena : 1; + u32 cnoc_pcie_sf_axi_clk_ena : 1; + u32 qupv3_i2c_s_ahb_clk_ena : 1; + u32 qupv3_i2c_core_clk_ena : 1; + u32 aggre_noc_south_axi_clk_ena : 1; + u32 qupv3_i2c_s0_clk_ena : 1; + u32 qupv3_i2c_s1_clk_ena : 1; + u32 qupv3_i2c_s2_clk_ena : 1; + u32 qupv3_i2c_s3_clk_ena : 1; + u32 qupv3_i2c_s4_clk_ena : 1; + u32 qupv3_i2c_s5_clk_ena : 1; + u32 qupv3_i2c_s6_clk_ena : 1; + u32 qupv3_i2c_s7_clk_ena : 1; + u32 qupv3_wrap1_core_2x_clk_ena : 1; + u32 qupv3_wrap1_core_clk_ena : 1; + u32 qupv3_wrap_1_m_ahb_clk_ena : 1; + u32 qupv3_wrap_1_s_ahb_clk_ena : 1; + u32 qupv3_wrap1_s0_clk_ena : 1; + u32 qupv3_wrap1_s1_clk_ena : 1; + u32 qupv3_wrap1_s2_clk_ena : 1; + u32 qupv3_wrap1_s3_clk_ena : 1; + u32 qupv3_wrap1_s4_clk_ena : 1; + u32 qupv3_wrap1_s5_clk_ena : 1; + u32 qupv3_wrap1_s6_clk_ena : 1; + u32 noc_pcie_north_dcd_xo_clk_ena : 1; + u32 qmip_aggre_noc_ahb_clk_ena : 1; + u32 anoc_pcie_pwrctl_clk_ena : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_q6_clock_branch_ena_vote_1_u +{ + struct ipa_gcc_hwio_def_gcc_mss_q6_clock_branch_ena_vote_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_q6_clock_sleep_ena_vote_1_s +{ + u32 pcie_0_slv_axi_clk_sleep_ena : 1; + u32 pcie_0_mstr_axi_clk_sleep_ena : 1; + u32 pcie_0_cfg_ahb_clk_sleep_ena : 1; + u32 pcie_0_aux_clk_sleep_ena : 1; + u32 pcie_0_pipe_clk_sleep_ena : 1; + u32 pcie_0_slv_q2a_axi_clk_sleep_ena : 1; + u32 cnoc_pcie_sf_axi_clk_sleep_ena : 1; + u32 qupv3_i2c_s_ahb_clk_sleep_ena : 1; + u32 qupv3_i2c_core_clk_sleep_ena : 1; + u32 aggre_noc_south_axi_clk_sleep_ena : 1; + u32 qupv3_i2c_s0_clk_sleep_ena : 1; + u32 qupv3_i2c_s1_clk_sleep_ena : 1; + u32 qupv3_i2c_s2_clk_sleep_ena : 1; + u32 qupv3_i2c_s3_clk_sleep_ena : 1; + u32 qupv3_i2c_s4_clk_sleep_ena : 1; + u32 qupv3_i2c_s5_clk_sleep_ena : 1; + u32 qupv3_i2c_s6_clk_sleep_ena : 1; + u32 qupv3_i2c_s7_clk_sleep_ena : 1; + u32 qupv3_wrap1_core_2x_clk_sleep_ena : 1; + u32 qupv3_wrap1_core_clk_sleep_ena : 1; + u32 qupv3_wrap_1_m_ahb_clk_sleep_ena : 1; + u32 qupv3_wrap_1_s_ahb_clk_sleep_ena : 1; + u32 qupv3_wrap1_s0_clk_sleep_ena : 1; + u32 qupv3_wrap1_s1_clk_sleep_ena : 1; + u32 qupv3_wrap1_s2_clk_sleep_ena : 1; + u32 qupv3_wrap1_s3_clk_sleep_ena : 1; + u32 qupv3_wrap1_s4_clk_sleep_ena : 1; + u32 qupv3_wrap1_s5_clk_sleep_ena : 1; + u32 qupv3_wrap1_s6_clk_sleep_ena : 1; + u32 noc_pcie_north_dcd_xo_clk_sleep_ena : 1; + u32 qmip_aggre_noc_ahb_clk_sleep_ena : 1; + u32 anoc_pcie_pwrctl_clk_sleep_ena : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_q6_clock_sleep_ena_vote_1_u +{ + struct ipa_gcc_hwio_def_gcc_mss_q6_clock_sleep_ena_vote_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_q6_clock_branch_ena_vote_2_s +{ + u32 qupv3_wrap2_core_clk_ena : 1; + u32 qupv3_wrap_2_s_ahb_clk_ena : 1; + u32 qupv3_wrap_2_m_ahb_clk_ena : 1; + u32 qupv3_wrap2_core_2x_clk_ena : 1; + u32 qupv3_wrap2_s0_clk_ena : 1; + u32 qupv3_wrap2_s1_clk_ena : 1; + u32 qupv3_wrap2_s2_clk_ena : 1; + u32 qupv3_wrap2_s3_clk_ena : 1; + u32 qupv3_wrap2_s4_clk_ena : 1; + u32 qupv3_wrap2_s5_clk_ena : 1; + u32 qupv3_wrap2_s6_clk_ena : 1; + u32 anoc_pcie_north_at_clk_ena : 1; + u32 anoc_pcie_tsctr_clk_ena : 1; + u32 anoc_pcie_qosgen_extref_clk_ena : 1; + u32 qupv3_i2c_s8_clk_ena : 1; + u32 qupv3_i2c_s9_clk_ena : 1; + u32 qupv3_wrap1_s7_clk_ena : 1; + u32 qupv3_wrap2_s7_clk_ena : 1; + u32 tme_gpll0_div2_clk_src_ena : 1; + u32 reserved0 : 13; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_q6_clock_branch_ena_vote_2_u +{ + struct ipa_gcc_hwio_def_gcc_mss_q6_clock_branch_ena_vote_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_q6_clock_sleep_ena_vote_2_s +{ + u32 qupv3_wrap2_core_clk_sleep_ena : 1; + u32 qupv3_wrap_2_s_ahb_clk_sleep_ena : 1; + u32 qupv3_wrap_2_m_ahb_clk_sleep_ena : 1; + u32 qupv3_wrap2_core_2x_clk_sleep_ena : 1; + u32 qupv3_wrap2_s0_clk_sleep_ena : 1; + u32 qupv3_wrap2_s1_clk_sleep_ena : 1; + u32 qupv3_wrap2_s2_clk_sleep_ena : 1; + u32 qupv3_wrap2_s3_clk_sleep_ena : 1; + u32 qupv3_wrap2_s4_clk_sleep_ena : 1; + u32 qupv3_wrap2_s5_clk_sleep_ena : 1; + u32 qupv3_wrap2_s6_clk_sleep_ena : 1; + u32 anoc_pcie_north_at_clk_sleep_ena : 1; + u32 anoc_pcie_tsctr_clk_sleep_ena : 1; + u32 anoc_pcie_qosgen_extref_clk_sleep_ena : 1; + u32 qupv3_i2c_s8_clk_sleep_ena : 1; + u32 qupv3_i2c_s9_clk_sleep_ena : 1; + u32 qupv3_wrap1_s7_clk_sleep_ena : 1; + u32 qupv3_wrap2_s7_clk_sleep_ena : 1; + u32 tme_gpll0_div2_clk_src_sleep_ena : 1; + u32 reserved0 : 13; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_q6_clock_sleep_ena_vote_2_u +{ + struct ipa_gcc_hwio_def_gcc_mss_q6_clock_sleep_ena_vote_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_q6_pll_branch_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_q6_pll_branch_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_mss_q6_pll_branch_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_q6_pll_sleep_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_q6_pll_sleep_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_mss_q6_pll_sleep_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HYP_CLOCK_BRANCH_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hyp_clock_branch_ena_vote_s +{ + u32 sys_noc_cpuss_ahb_clk_ena : 1; + u32 tcsr_ahb_clk_ena : 1; + u32 qdss_cfg_ahb_clk_ena : 1; + u32 ce1_ahb_clk_ena : 1; + u32 ce1_axi_clk_ena : 1; + u32 ce1_clk_ena : 1; + u32 tlmm_clk_ena : 1; + u32 reserved0 : 1; + u32 tlmm_ahb_clk_ena : 1; + u32 reserved1 : 1; + u32 boot_rom_ahb_clk_ena : 1; + u32 qmip_pcie_ahb_clk_ena : 1; + u32 aggre_noc_pcie_axi_clk_ena : 1; + u32 prng_ahb_clk_ena : 1; + u32 tme_gpll0_clk_src_ena : 1; + u32 gpu_gpll0_clk_src_ena : 1; + u32 gpu_gpll0_div_clk_src_ena : 1; + u32 mss_gpll0_div_clk_src_ena : 1; + u32 tcu_anoc_pcie_qtb_clk_ena : 1; + u32 ddrss_pcie_sf_qtb_clk_ena : 1; + u32 cfg_noc_pcie_anoc_ahb_clk_ena : 1; + u32 cpuss_ahb_clk_ena : 1; + u32 pcie_0_phy_rchng_clk_ena : 1; + u32 pcie_1_phy_rchng_clk_ena : 1; + u32 pcie_1_phy_aux_clk_ena : 1; + u32 pcie_1_slv_q2a_axi_clk_ena : 1; + u32 pcie_1_slv_axi_clk_ena : 1; + u32 pcie_1_mstr_axi_clk_ena : 1; + u32 pcie_1_cfg_ahb_clk_ena : 1; + u32 pcie_1_aux_clk_ena : 1; + u32 pcie_1_pipe_clk_ena : 1; + u32 ddrss_gpll0_main_clk_src_ena : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hyp_clock_branch_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_hyp_clock_branch_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HYP_CLOCK_SLEEP_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hyp_clock_sleep_ena_vote_s +{ + u32 sys_noc_cpuss_ahb_clk_sleep_ena : 1; + u32 tcsr_ahb_clk_sleep_ena : 1; + u32 qdss_cfg_ahb_clk_sleep_ena : 1; + u32 ce1_ahb_clk_sleep_ena : 1; + u32 ce1_axi_clk_sleep_ena : 1; + u32 ce1_clk_sleep_ena : 1; + u32 tlmm_clk_sleep_ena : 1; + u32 reserved0 : 1; + u32 tlmm_ahb_clk_sleep_ena : 1; + u32 reserved1 : 1; + u32 boot_rom_ahb_clk_sleep_ena : 1; + u32 qmip_pcie_ahb_clk_sleep_ena : 1; + u32 aggre_noc_pcie_axi_clk_sleep_ena : 1; + u32 prng_ahb_clk_sleep_ena : 1; + u32 tme_gpll0_clk_src_sleep_ena : 1; + u32 gpu_gpll0_clk_src_sleep_ena : 1; + u32 gpu_gpll0_div_clk_src_sleep_ena : 1; + u32 mss_gpll0_div_clk_src_sleep_ena : 1; + u32 tcu_anoc_pcie_qtb_clk_sleep_ena : 1; + u32 ddrss_pcie_sf_qtb_clk_sleep_ena : 1; + u32 cfg_noc_pcie_anoc_ahb_clk_sleep_ena : 1; + u32 cpuss_ahb_clk_sleep_ena : 1; + u32 pcie_0_phy_rchng_clk_sleep_ena : 1; + u32 pcie_1_phy_rchng_clk_sleep_ena : 1; + u32 pcie_1_phy_aux_clk_sleep_ena : 1; + u32 pcie_1_slv_q2a_axi_clk_sleep_ena : 1; + u32 pcie_1_slv_axi_clk_sleep_ena : 1; + u32 pcie_1_mstr_axi_clk_sleep_ena : 1; + u32 pcie_1_cfg_ahb_clk_sleep_ena : 1; + u32 pcie_1_aux_clk_sleep_ena : 1; + u32 pcie_1_pipe_clk_sleep_ena : 1; + u32 ddrss_gpll0_main_clk_src_sleep_ena : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hyp_clock_sleep_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_hyp_clock_sleep_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hyp_clock_branch_ena_vote_1_s +{ + u32 pcie_0_slv_axi_clk_ena : 1; + u32 pcie_0_mstr_axi_clk_ena : 1; + u32 pcie_0_cfg_ahb_clk_ena : 1; + u32 pcie_0_aux_clk_ena : 1; + u32 pcie_0_pipe_clk_ena : 1; + u32 pcie_0_slv_q2a_axi_clk_ena : 1; + u32 cnoc_pcie_sf_axi_clk_ena : 1; + u32 qupv3_i2c_s_ahb_clk_ena : 1; + u32 qupv3_i2c_core_clk_ena : 1; + u32 aggre_noc_south_axi_clk_ena : 1; + u32 qupv3_i2c_s0_clk_ena : 1; + u32 qupv3_i2c_s1_clk_ena : 1; + u32 qupv3_i2c_s2_clk_ena : 1; + u32 qupv3_i2c_s3_clk_ena : 1; + u32 qupv3_i2c_s4_clk_ena : 1; + u32 qupv3_i2c_s5_clk_ena : 1; + u32 qupv3_i2c_s6_clk_ena : 1; + u32 qupv3_i2c_s7_clk_ena : 1; + u32 qupv3_wrap1_core_2x_clk_ena : 1; + u32 qupv3_wrap1_core_clk_ena : 1; + u32 qupv3_wrap_1_m_ahb_clk_ena : 1; + u32 qupv3_wrap_1_s_ahb_clk_ena : 1; + u32 qupv3_wrap1_s0_clk_ena : 1; + u32 qupv3_wrap1_s1_clk_ena : 1; + u32 qupv3_wrap1_s2_clk_ena : 1; + u32 qupv3_wrap1_s3_clk_ena : 1; + u32 qupv3_wrap1_s4_clk_ena : 1; + u32 qupv3_wrap1_s5_clk_ena : 1; + u32 qupv3_wrap1_s6_clk_ena : 1; + u32 noc_pcie_north_dcd_xo_clk_ena : 1; + u32 qmip_aggre_noc_ahb_clk_ena : 1; + u32 anoc_pcie_pwrctl_clk_ena : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hyp_clock_branch_ena_vote_1_u +{ + struct ipa_gcc_hwio_def_gcc_hyp_clock_branch_ena_vote_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hyp_clock_sleep_ena_vote_1_s +{ + u32 pcie_0_slv_axi_clk_sleep_ena : 1; + u32 pcie_0_mstr_axi_clk_sleep_ena : 1; + u32 pcie_0_cfg_ahb_clk_sleep_ena : 1; + u32 pcie_0_aux_clk_sleep_ena : 1; + u32 pcie_0_pipe_clk_sleep_ena : 1; + u32 pcie_0_slv_q2a_axi_clk_sleep_ena : 1; + u32 cnoc_pcie_sf_axi_clk_sleep_ena : 1; + u32 qupv3_i2c_s_ahb_clk_sleep_ena : 1; + u32 qupv3_i2c_core_clk_sleep_ena : 1; + u32 aggre_noc_south_axi_clk_sleep_ena : 1; + u32 qupv3_i2c_s0_clk_sleep_ena : 1; + u32 qupv3_i2c_s1_clk_sleep_ena : 1; + u32 qupv3_i2c_s2_clk_sleep_ena : 1; + u32 qupv3_i2c_s3_clk_sleep_ena : 1; + u32 qupv3_i2c_s4_clk_sleep_ena : 1; + u32 qupv3_i2c_s5_clk_sleep_ena : 1; + u32 qupv3_i2c_s6_clk_sleep_ena : 1; + u32 qupv3_i2c_s7_clk_sleep_ena : 1; + u32 qupv3_wrap1_core_2x_clk_sleep_ena : 1; + u32 qupv3_wrap1_core_clk_sleep_ena : 1; + u32 qupv3_wrap_1_m_ahb_clk_sleep_ena : 1; + u32 qupv3_wrap_1_s_ahb_clk_sleep_ena : 1; + u32 qupv3_wrap1_s0_clk_sleep_ena : 1; + u32 qupv3_wrap1_s1_clk_sleep_ena : 1; + u32 qupv3_wrap1_s2_clk_sleep_ena : 1; + u32 qupv3_wrap1_s3_clk_sleep_ena : 1; + u32 qupv3_wrap1_s4_clk_sleep_ena : 1; + u32 qupv3_wrap1_s5_clk_sleep_ena : 1; + u32 qupv3_wrap1_s6_clk_sleep_ena : 1; + u32 noc_pcie_north_dcd_xo_clk_sleep_ena : 1; + u32 qmip_aggre_noc_ahb_clk_sleep_ena : 1; + u32 anoc_pcie_pwrctl_clk_sleep_ena : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hyp_clock_sleep_ena_vote_1_u +{ + struct ipa_gcc_hwio_def_gcc_hyp_clock_sleep_ena_vote_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hyp_clock_branch_ena_vote_2_s +{ + u32 qupv3_wrap2_core_clk_ena : 1; + u32 qupv3_wrap_2_s_ahb_clk_ena : 1; + u32 qupv3_wrap_2_m_ahb_clk_ena : 1; + u32 qupv3_wrap2_core_2x_clk_ena : 1; + u32 qupv3_wrap2_s0_clk_ena : 1; + u32 qupv3_wrap2_s1_clk_ena : 1; + u32 qupv3_wrap2_s2_clk_ena : 1; + u32 qupv3_wrap2_s3_clk_ena : 1; + u32 qupv3_wrap2_s4_clk_ena : 1; + u32 qupv3_wrap2_s5_clk_ena : 1; + u32 qupv3_wrap2_s6_clk_ena : 1; + u32 anoc_pcie_north_at_clk_ena : 1; + u32 anoc_pcie_tsctr_clk_ena : 1; + u32 anoc_pcie_qosgen_extref_clk_ena : 1; + u32 qupv3_i2c_s8_clk_ena : 1; + u32 qupv3_i2c_s9_clk_ena : 1; + u32 qupv3_wrap1_s7_clk_ena : 1; + u32 qupv3_wrap2_s7_clk_ena : 1; + u32 tme_gpll0_div2_clk_src_ena : 1; + u32 reserved0 : 13; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hyp_clock_branch_ena_vote_2_u +{ + struct ipa_gcc_hwio_def_gcc_hyp_clock_branch_ena_vote_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hyp_clock_sleep_ena_vote_2_s +{ + u32 qupv3_wrap2_core_clk_sleep_ena : 1; + u32 qupv3_wrap_2_s_ahb_clk_sleep_ena : 1; + u32 qupv3_wrap_2_m_ahb_clk_sleep_ena : 1; + u32 qupv3_wrap2_core_2x_clk_sleep_ena : 1; + u32 qupv3_wrap2_s0_clk_sleep_ena : 1; + u32 qupv3_wrap2_s1_clk_sleep_ena : 1; + u32 qupv3_wrap2_s2_clk_sleep_ena : 1; + u32 qupv3_wrap2_s3_clk_sleep_ena : 1; + u32 qupv3_wrap2_s4_clk_sleep_ena : 1; + u32 qupv3_wrap2_s5_clk_sleep_ena : 1; + u32 qupv3_wrap2_s6_clk_sleep_ena : 1; + u32 anoc_pcie_north_at_clk_sleep_ena : 1; + u32 anoc_pcie_tsctr_clk_sleep_ena : 1; + u32 anoc_pcie_qosgen_extref_clk_sleep_ena : 1; + u32 qupv3_i2c_s8_clk_sleep_ena : 1; + u32 qupv3_i2c_s9_clk_sleep_ena : 1; + u32 qupv3_wrap1_s7_clk_sleep_ena : 1; + u32 qupv3_wrap2_s7_clk_sleep_ena : 1; + u32 tme_gpll0_div2_clk_src_sleep_ena : 1; + u32 reserved0 : 13; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hyp_clock_sleep_ena_vote_2_u +{ + struct ipa_gcc_hwio_def_gcc_hyp_clock_sleep_ena_vote_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HYP_PLL_BRANCH_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hyp_pll_branch_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hyp_pll_branch_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_hyp_pll_branch_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HYP_PLL_SLEEP_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hyp_pll_sleep_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hyp_pll_sleep_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_hyp_pll_sleep_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spare1_clock_branch_ena_vote_s +{ + u32 sys_noc_cpuss_ahb_clk_ena : 1; + u32 tcsr_ahb_clk_ena : 1; + u32 qdss_cfg_ahb_clk_ena : 1; + u32 ce1_ahb_clk_ena : 1; + u32 ce1_axi_clk_ena : 1; + u32 ce1_clk_ena : 1; + u32 tlmm_clk_ena : 1; + u32 reserved0 : 1; + u32 tlmm_ahb_clk_ena : 1; + u32 reserved1 : 1; + u32 boot_rom_ahb_clk_ena : 1; + u32 qmip_pcie_ahb_clk_ena : 1; + u32 aggre_noc_pcie_axi_clk_ena : 1; + u32 prng_ahb_clk_ena : 1; + u32 tme_gpll0_clk_src_ena : 1; + u32 gpu_gpll0_clk_src_ena : 1; + u32 gpu_gpll0_div_clk_src_ena : 1; + u32 mss_gpll0_div_clk_src_ena : 1; + u32 tcu_anoc_pcie_qtb_clk_ena : 1; + u32 ddrss_pcie_sf_qtb_clk_ena : 1; + u32 cfg_noc_pcie_anoc_ahb_clk_ena : 1; + u32 cpuss_ahb_clk_ena : 1; + u32 pcie_0_phy_rchng_clk_ena : 1; + u32 pcie_1_phy_rchng_clk_ena : 1; + u32 pcie_1_phy_aux_clk_ena : 1; + u32 pcie_1_slv_q2a_axi_clk_ena : 1; + u32 pcie_1_slv_axi_clk_ena : 1; + u32 pcie_1_mstr_axi_clk_ena : 1; + u32 pcie_1_cfg_ahb_clk_ena : 1; + u32 pcie_1_aux_clk_ena : 1; + u32 pcie_1_pipe_clk_ena : 1; + u32 ddrss_gpll0_main_clk_src_ena : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spare1_clock_branch_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_spare1_clock_branch_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spare1_clock_sleep_ena_vote_s +{ + u32 sys_noc_cpuss_ahb_clk_sleep_ena : 1; + u32 tcsr_ahb_clk_sleep_ena : 1; + u32 qdss_cfg_ahb_clk_sleep_ena : 1; + u32 ce1_ahb_clk_sleep_ena : 1; + u32 ce1_axi_clk_sleep_ena : 1; + u32 ce1_clk_sleep_ena : 1; + u32 tlmm_clk_sleep_ena : 1; + u32 reserved0 : 1; + u32 tlmm_ahb_clk_sleep_ena : 1; + u32 reserved1 : 1; + u32 boot_rom_ahb_clk_sleep_ena : 1; + u32 qmip_pcie_ahb_clk_sleep_ena : 1; + u32 aggre_noc_pcie_axi_clk_sleep_ena : 1; + u32 prng_ahb_clk_sleep_ena : 1; + u32 tme_gpll0_clk_src_sleep_ena : 1; + u32 gpu_gpll0_clk_src_sleep_ena : 1; + u32 gpu_gpll0_div_clk_src_sleep_ena : 1; + u32 mss_gpll0_div_clk_src_sleep_ena : 1; + u32 tcu_anoc_pcie_qtb_clk_sleep_ena : 1; + u32 ddrss_pcie_sf_qtb_clk_sleep_ena : 1; + u32 cfg_noc_pcie_anoc_ahb_clk_sleep_ena : 1; + u32 cpuss_ahb_clk_sleep_ena : 1; + u32 pcie_0_phy_rchng_clk_sleep_ena : 1; + u32 pcie_1_phy_rchng_clk_sleep_ena : 1; + u32 pcie_1_phy_aux_clk_sleep_ena : 1; + u32 pcie_1_slv_q2a_axi_clk_sleep_ena : 1; + u32 pcie_1_slv_axi_clk_sleep_ena : 1; + u32 pcie_1_mstr_axi_clk_sleep_ena : 1; + u32 pcie_1_cfg_ahb_clk_sleep_ena : 1; + u32 pcie_1_aux_clk_sleep_ena : 1; + u32 pcie_1_pipe_clk_sleep_ena : 1; + u32 ddrss_gpll0_main_clk_src_sleep_ena : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spare1_clock_sleep_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_spare1_clock_sleep_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spare1_clock_branch_ena_vote_1_s +{ + u32 pcie_0_slv_axi_clk_ena : 1; + u32 pcie_0_mstr_axi_clk_ena : 1; + u32 pcie_0_cfg_ahb_clk_ena : 1; + u32 pcie_0_aux_clk_ena : 1; + u32 pcie_0_pipe_clk_ena : 1; + u32 pcie_0_slv_q2a_axi_clk_ena : 1; + u32 cnoc_pcie_sf_axi_clk_ena : 1; + u32 qupv3_i2c_s_ahb_clk_ena : 1; + u32 qupv3_i2c_core_clk_ena : 1; + u32 aggre_noc_south_axi_clk_ena : 1; + u32 qupv3_i2c_s0_clk_ena : 1; + u32 qupv3_i2c_s1_clk_ena : 1; + u32 qupv3_i2c_s2_clk_ena : 1; + u32 qupv3_i2c_s3_clk_ena : 1; + u32 qupv3_i2c_s4_clk_ena : 1; + u32 qupv3_i2c_s5_clk_ena : 1; + u32 qupv3_i2c_s6_clk_ena : 1; + u32 qupv3_i2c_s7_clk_ena : 1; + u32 qupv3_wrap1_core_2x_clk_ena : 1; + u32 qupv3_wrap1_core_clk_ena : 1; + u32 qupv3_wrap_1_m_ahb_clk_ena : 1; + u32 qupv3_wrap_1_s_ahb_clk_ena : 1; + u32 qupv3_wrap1_s0_clk_ena : 1; + u32 qupv3_wrap1_s1_clk_ena : 1; + u32 qupv3_wrap1_s2_clk_ena : 1; + u32 qupv3_wrap1_s3_clk_ena : 1; + u32 qupv3_wrap1_s4_clk_ena : 1; + u32 qupv3_wrap1_s5_clk_ena : 1; + u32 qupv3_wrap1_s6_clk_ena : 1; + u32 noc_pcie_north_dcd_xo_clk_ena : 1; + u32 qmip_aggre_noc_ahb_clk_ena : 1; + u32 anoc_pcie_pwrctl_clk_ena : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spare1_clock_branch_ena_vote_1_u +{ + struct ipa_gcc_hwio_def_gcc_spare1_clock_branch_ena_vote_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spare1_clock_sleep_ena_vote_1_s +{ + u32 pcie_0_slv_axi_clk_sleep_ena : 1; + u32 pcie_0_mstr_axi_clk_sleep_ena : 1; + u32 pcie_0_cfg_ahb_clk_sleep_ena : 1; + u32 pcie_0_aux_clk_sleep_ena : 1; + u32 pcie_0_pipe_clk_sleep_ena : 1; + u32 pcie_0_slv_q2a_axi_clk_sleep_ena : 1; + u32 cnoc_pcie_sf_axi_clk_sleep_ena : 1; + u32 qupv3_i2c_s_ahb_clk_sleep_ena : 1; + u32 qupv3_i2c_core_clk_sleep_ena : 1; + u32 aggre_noc_south_axi_clk_sleep_ena : 1; + u32 qupv3_i2c_s0_clk_sleep_ena : 1; + u32 qupv3_i2c_s1_clk_sleep_ena : 1; + u32 qupv3_i2c_s2_clk_sleep_ena : 1; + u32 qupv3_i2c_s3_clk_sleep_ena : 1; + u32 qupv3_i2c_s4_clk_sleep_ena : 1; + u32 qupv3_i2c_s5_clk_sleep_ena : 1; + u32 qupv3_i2c_s6_clk_sleep_ena : 1; + u32 qupv3_i2c_s7_clk_sleep_ena : 1; + u32 qupv3_wrap1_core_2x_clk_sleep_ena : 1; + u32 qupv3_wrap1_core_clk_sleep_ena : 1; + u32 qupv3_wrap_1_m_ahb_clk_sleep_ena : 1; + u32 qupv3_wrap_1_s_ahb_clk_sleep_ena : 1; + u32 qupv3_wrap1_s0_clk_sleep_ena : 1; + u32 qupv3_wrap1_s1_clk_sleep_ena : 1; + u32 qupv3_wrap1_s2_clk_sleep_ena : 1; + u32 qupv3_wrap1_s3_clk_sleep_ena : 1; + u32 qupv3_wrap1_s4_clk_sleep_ena : 1; + u32 qupv3_wrap1_s5_clk_sleep_ena : 1; + u32 qupv3_wrap1_s6_clk_sleep_ena : 1; + u32 noc_pcie_north_dcd_xo_clk_sleep_ena : 1; + u32 qmip_aggre_noc_ahb_clk_sleep_ena : 1; + u32 anoc_pcie_pwrctl_clk_sleep_ena : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spare1_clock_sleep_ena_vote_1_u +{ + struct ipa_gcc_hwio_def_gcc_spare1_clock_sleep_ena_vote_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spare1_clock_branch_ena_vote_2_s +{ + u32 qupv3_wrap2_core_clk_ena : 1; + u32 qupv3_wrap_2_s_ahb_clk_ena : 1; + u32 qupv3_wrap_2_m_ahb_clk_ena : 1; + u32 qupv3_wrap2_core_2x_clk_ena : 1; + u32 qupv3_wrap2_s0_clk_ena : 1; + u32 qupv3_wrap2_s1_clk_ena : 1; + u32 qupv3_wrap2_s2_clk_ena : 1; + u32 qupv3_wrap2_s3_clk_ena : 1; + u32 qupv3_wrap2_s4_clk_ena : 1; + u32 qupv3_wrap2_s5_clk_ena : 1; + u32 qupv3_wrap2_s6_clk_ena : 1; + u32 anoc_pcie_north_at_clk_ena : 1; + u32 anoc_pcie_tsctr_clk_ena : 1; + u32 anoc_pcie_qosgen_extref_clk_ena : 1; + u32 qupv3_i2c_s8_clk_ena : 1; + u32 qupv3_i2c_s9_clk_ena : 1; + u32 qupv3_wrap1_s7_clk_ena : 1; + u32 qupv3_wrap2_s7_clk_ena : 1; + u32 tme_gpll0_div2_clk_src_ena : 1; + u32 reserved0 : 13; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spare1_clock_branch_ena_vote_2_u +{ + struct ipa_gcc_hwio_def_gcc_spare1_clock_branch_ena_vote_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spare1_clock_sleep_ena_vote_2_s +{ + u32 qupv3_wrap2_core_clk_sleep_ena : 1; + u32 qupv3_wrap_2_s_ahb_clk_sleep_ena : 1; + u32 qupv3_wrap_2_m_ahb_clk_sleep_ena : 1; + u32 qupv3_wrap2_core_2x_clk_sleep_ena : 1; + u32 qupv3_wrap2_s0_clk_sleep_ena : 1; + u32 qupv3_wrap2_s1_clk_sleep_ena : 1; + u32 qupv3_wrap2_s2_clk_sleep_ena : 1; + u32 qupv3_wrap2_s3_clk_sleep_ena : 1; + u32 qupv3_wrap2_s4_clk_sleep_ena : 1; + u32 qupv3_wrap2_s5_clk_sleep_ena : 1; + u32 qupv3_wrap2_s6_clk_sleep_ena : 1; + u32 anoc_pcie_north_at_clk_sleep_ena : 1; + u32 anoc_pcie_tsctr_clk_sleep_ena : 1; + u32 anoc_pcie_qosgen_extref_clk_sleep_ena : 1; + u32 qupv3_i2c_s8_clk_sleep_ena : 1; + u32 qupv3_i2c_s9_clk_sleep_ena : 1; + u32 qupv3_wrap1_s7_clk_sleep_ena : 1; + u32 qupv3_wrap2_s7_clk_sleep_ena : 1; + u32 tme_gpll0_div2_clk_src_sleep_ena : 1; + u32 reserved0 : 13; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spare1_clock_sleep_ena_vote_2_u +{ + struct ipa_gcc_hwio_def_gcc_spare1_clock_sleep_ena_vote_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPARE1_PLL_BRANCH_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spare1_pll_branch_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spare1_pll_branch_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_spare1_pll_branch_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPARE1_PLL_SLEEP_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spare1_pll_sleep_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spare1_pll_sleep_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_spare1_pll_sleep_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TME_CLOCK_BRANCH_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tme_clock_branch_ena_vote_s +{ + u32 sys_noc_cpuss_ahb_clk_ena : 1; + u32 tcsr_ahb_clk_ena : 1; + u32 qdss_cfg_ahb_clk_ena : 1; + u32 ce1_ahb_clk_ena : 1; + u32 ce1_axi_clk_ena : 1; + u32 ce1_clk_ena : 1; + u32 tlmm_clk_ena : 1; + u32 reserved0 : 1; + u32 tlmm_ahb_clk_ena : 1; + u32 reserved1 : 1; + u32 boot_rom_ahb_clk_ena : 1; + u32 qmip_pcie_ahb_clk_ena : 1; + u32 aggre_noc_pcie_axi_clk_ena : 1; + u32 prng_ahb_clk_ena : 1; + u32 tme_gpll0_clk_src_ena : 1; + u32 gpu_gpll0_clk_src_ena : 1; + u32 gpu_gpll0_div_clk_src_ena : 1; + u32 mss_gpll0_div_clk_src_ena : 1; + u32 tcu_anoc_pcie_qtb_clk_ena : 1; + u32 ddrss_pcie_sf_qtb_clk_ena : 1; + u32 cfg_noc_pcie_anoc_ahb_clk_ena : 1; + u32 cpuss_ahb_clk_ena : 1; + u32 pcie_0_phy_rchng_clk_ena : 1; + u32 pcie_1_phy_rchng_clk_ena : 1; + u32 pcie_1_phy_aux_clk_ena : 1; + u32 pcie_1_slv_q2a_axi_clk_ena : 1; + u32 pcie_1_slv_axi_clk_ena : 1; + u32 pcie_1_mstr_axi_clk_ena : 1; + u32 pcie_1_cfg_ahb_clk_ena : 1; + u32 pcie_1_aux_clk_ena : 1; + u32 pcie_1_pipe_clk_ena : 1; + u32 ddrss_gpll0_main_clk_src_ena : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tme_clock_branch_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_tme_clock_branch_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TME_CLOCK_SLEEP_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tme_clock_sleep_ena_vote_s +{ + u32 sys_noc_cpuss_ahb_clk_sleep_ena : 1; + u32 tcsr_ahb_clk_sleep_ena : 1; + u32 qdss_cfg_ahb_clk_sleep_ena : 1; + u32 ce1_ahb_clk_sleep_ena : 1; + u32 ce1_axi_clk_sleep_ena : 1; + u32 ce1_clk_sleep_ena : 1; + u32 tlmm_clk_sleep_ena : 1; + u32 reserved0 : 1; + u32 tlmm_ahb_clk_sleep_ena : 1; + u32 reserved1 : 1; + u32 boot_rom_ahb_clk_sleep_ena : 1; + u32 qmip_pcie_ahb_clk_sleep_ena : 1; + u32 aggre_noc_pcie_axi_clk_sleep_ena : 1; + u32 prng_ahb_clk_sleep_ena : 1; + u32 tme_gpll0_clk_src_sleep_ena : 1; + u32 gpu_gpll0_clk_src_sleep_ena : 1; + u32 gpu_gpll0_div_clk_src_sleep_ena : 1; + u32 mss_gpll0_div_clk_src_sleep_ena : 1; + u32 tcu_anoc_pcie_qtb_clk_sleep_ena : 1; + u32 ddrss_pcie_sf_qtb_clk_sleep_ena : 1; + u32 cfg_noc_pcie_anoc_ahb_clk_sleep_ena : 1; + u32 cpuss_ahb_clk_sleep_ena : 1; + u32 pcie_0_phy_rchng_clk_sleep_ena : 1; + u32 pcie_1_phy_rchng_clk_sleep_ena : 1; + u32 pcie_1_phy_aux_clk_sleep_ena : 1; + u32 pcie_1_slv_q2a_axi_clk_sleep_ena : 1; + u32 pcie_1_slv_axi_clk_sleep_ena : 1; + u32 pcie_1_mstr_axi_clk_sleep_ena : 1; + u32 pcie_1_cfg_ahb_clk_sleep_ena : 1; + u32 pcie_1_aux_clk_sleep_ena : 1; + u32 pcie_1_pipe_clk_sleep_ena : 1; + u32 ddrss_gpll0_main_clk_src_sleep_ena : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tme_clock_sleep_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_tme_clock_sleep_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TME_CLOCK_BRANCH_ENA_VOTE_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tme_clock_branch_ena_vote_1_s +{ + u32 pcie_0_slv_axi_clk_ena : 1; + u32 pcie_0_mstr_axi_clk_ena : 1; + u32 pcie_0_cfg_ahb_clk_ena : 1; + u32 pcie_0_aux_clk_ena : 1; + u32 pcie_0_pipe_clk_ena : 1; + u32 pcie_0_slv_q2a_axi_clk_ena : 1; + u32 cnoc_pcie_sf_axi_clk_ena : 1; + u32 qupv3_i2c_s_ahb_clk_ena : 1; + u32 qupv3_i2c_core_clk_ena : 1; + u32 aggre_noc_south_axi_clk_ena : 1; + u32 qupv3_i2c_s0_clk_ena : 1; + u32 qupv3_i2c_s1_clk_ena : 1; + u32 qupv3_i2c_s2_clk_ena : 1; + u32 qupv3_i2c_s3_clk_ena : 1; + u32 qupv3_i2c_s4_clk_ena : 1; + u32 qupv3_i2c_s5_clk_ena : 1; + u32 qupv3_i2c_s6_clk_ena : 1; + u32 qupv3_i2c_s7_clk_ena : 1; + u32 qupv3_wrap1_core_2x_clk_ena : 1; + u32 qupv3_wrap1_core_clk_ena : 1; + u32 qupv3_wrap_1_m_ahb_clk_ena : 1; + u32 qupv3_wrap_1_s_ahb_clk_ena : 1; + u32 qupv3_wrap1_s0_clk_ena : 1; + u32 qupv3_wrap1_s1_clk_ena : 1; + u32 qupv3_wrap1_s2_clk_ena : 1; + u32 qupv3_wrap1_s3_clk_ena : 1; + u32 qupv3_wrap1_s4_clk_ena : 1; + u32 qupv3_wrap1_s5_clk_ena : 1; + u32 qupv3_wrap1_s6_clk_ena : 1; + u32 noc_pcie_north_dcd_xo_clk_ena : 1; + u32 qmip_aggre_noc_ahb_clk_ena : 1; + u32 anoc_pcie_pwrctl_clk_ena : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tme_clock_branch_ena_vote_1_u +{ + struct ipa_gcc_hwio_def_gcc_tme_clock_branch_ena_vote_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TME_CLOCK_SLEEP_ENA_VOTE_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tme_clock_sleep_ena_vote_1_s +{ + u32 pcie_0_slv_axi_clk_sleep_ena : 1; + u32 pcie_0_mstr_axi_clk_sleep_ena : 1; + u32 pcie_0_cfg_ahb_clk_sleep_ena : 1; + u32 pcie_0_aux_clk_sleep_ena : 1; + u32 pcie_0_pipe_clk_sleep_ena : 1; + u32 pcie_0_slv_q2a_axi_clk_sleep_ena : 1; + u32 cnoc_pcie_sf_axi_clk_sleep_ena : 1; + u32 qupv3_i2c_s_ahb_clk_sleep_ena : 1; + u32 qupv3_i2c_core_clk_sleep_ena : 1; + u32 aggre_noc_south_axi_clk_sleep_ena : 1; + u32 qupv3_i2c_s0_clk_sleep_ena : 1; + u32 qupv3_i2c_s1_clk_sleep_ena : 1; + u32 qupv3_i2c_s2_clk_sleep_ena : 1; + u32 qupv3_i2c_s3_clk_sleep_ena : 1; + u32 qupv3_i2c_s4_clk_sleep_ena : 1; + u32 qupv3_i2c_s5_clk_sleep_ena : 1; + u32 qupv3_i2c_s6_clk_sleep_ena : 1; + u32 qupv3_i2c_s7_clk_sleep_ena : 1; + u32 qupv3_wrap1_core_2x_clk_sleep_ena : 1; + u32 qupv3_wrap1_core_clk_sleep_ena : 1; + u32 qupv3_wrap_1_m_ahb_clk_sleep_ena : 1; + u32 qupv3_wrap_1_s_ahb_clk_sleep_ena : 1; + u32 qupv3_wrap1_s0_clk_sleep_ena : 1; + u32 qupv3_wrap1_s1_clk_sleep_ena : 1; + u32 qupv3_wrap1_s2_clk_sleep_ena : 1; + u32 qupv3_wrap1_s3_clk_sleep_ena : 1; + u32 qupv3_wrap1_s4_clk_sleep_ena : 1; + u32 qupv3_wrap1_s5_clk_sleep_ena : 1; + u32 qupv3_wrap1_s6_clk_sleep_ena : 1; + u32 noc_pcie_north_dcd_xo_clk_sleep_ena : 1; + u32 qmip_aggre_noc_ahb_clk_sleep_ena : 1; + u32 anoc_pcie_pwrctl_clk_sleep_ena : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tme_clock_sleep_ena_vote_1_u +{ + struct ipa_gcc_hwio_def_gcc_tme_clock_sleep_ena_vote_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TME_CLOCK_BRANCH_ENA_VOTE_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tme_clock_branch_ena_vote_2_s +{ + u32 qupv3_wrap2_core_clk_ena : 1; + u32 qupv3_wrap_2_s_ahb_clk_ena : 1; + u32 qupv3_wrap_2_m_ahb_clk_ena : 1; + u32 qupv3_wrap2_core_2x_clk_ena : 1; + u32 qupv3_wrap2_s0_clk_ena : 1; + u32 qupv3_wrap2_s1_clk_ena : 1; + u32 qupv3_wrap2_s2_clk_ena : 1; + u32 qupv3_wrap2_s3_clk_ena : 1; + u32 qupv3_wrap2_s4_clk_ena : 1; + u32 qupv3_wrap2_s5_clk_ena : 1; + u32 qupv3_wrap2_s6_clk_ena : 1; + u32 anoc_pcie_north_at_clk_ena : 1; + u32 anoc_pcie_tsctr_clk_ena : 1; + u32 anoc_pcie_qosgen_extref_clk_ena : 1; + u32 qupv3_i2c_s8_clk_ena : 1; + u32 qupv3_i2c_s9_clk_ena : 1; + u32 qupv3_wrap1_s7_clk_ena : 1; + u32 qupv3_wrap2_s7_clk_ena : 1; + u32 tme_gpll0_div2_clk_src_ena : 1; + u32 reserved0 : 13; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tme_clock_branch_ena_vote_2_u +{ + struct ipa_gcc_hwio_def_gcc_tme_clock_branch_ena_vote_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TME_CLOCK_SLEEP_ENA_VOTE_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tme_clock_sleep_ena_vote_2_s +{ + u32 qupv3_wrap2_core_clk_sleep_ena : 1; + u32 qupv3_wrap_2_s_ahb_clk_sleep_ena : 1; + u32 qupv3_wrap_2_m_ahb_clk_sleep_ena : 1; + u32 qupv3_wrap2_core_2x_clk_sleep_ena : 1; + u32 qupv3_wrap2_s0_clk_sleep_ena : 1; + u32 qupv3_wrap2_s1_clk_sleep_ena : 1; + u32 qupv3_wrap2_s2_clk_sleep_ena : 1; + u32 qupv3_wrap2_s3_clk_sleep_ena : 1; + u32 qupv3_wrap2_s4_clk_sleep_ena : 1; + u32 qupv3_wrap2_s5_clk_sleep_ena : 1; + u32 qupv3_wrap2_s6_clk_sleep_ena : 1; + u32 anoc_pcie_north_at_clk_sleep_ena : 1; + u32 anoc_pcie_tsctr_clk_sleep_ena : 1; + u32 anoc_pcie_qosgen_extref_clk_sleep_ena : 1; + u32 qupv3_i2c_s8_clk_sleep_ena : 1; + u32 qupv3_i2c_s9_clk_sleep_ena : 1; + u32 qupv3_wrap1_s7_clk_sleep_ena : 1; + u32 qupv3_wrap2_s7_clk_sleep_ena : 1; + u32 tme_gpll0_div2_clk_src_sleep_ena : 1; + u32 reserved0 : 13; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tme_clock_sleep_ena_vote_2_u +{ + struct ipa_gcc_hwio_def_gcc_tme_clock_sleep_ena_vote_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TME_PLL_BRANCH_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tme_pll_branch_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tme_pll_branch_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_tme_pll_branch_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TME_PLL_SLEEP_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tme_pll_sleep_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tme_pll_sleep_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_tme_pll_sleep_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_0_LINK_DOWN_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_0_link_down_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_0_link_down_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_0_link_down_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_0_MISC_RESET +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_0_misc_reset_s +{ + u32 pcie_0_slv_axi_bcr_blk_ares : 1; + u32 pcie_0_mstr_axi_bcr_blk_ares : 1; + u32 pcie_0_cfg_ahb_bcr_blk_ares : 1; + u32 pcie_0_aux_bcr_blk_ares : 1; + u32 pcie_0_pipe_bcr_blk_ares : 1; + u32 pcie_0_mstr_axi_sticky_bcr_blk_ares : 1; + u32 pcie_0_core_sticky_bcr_blk_ares : 1; + u32 pcie_0_slv_axi_sticky_bcr_blk_ares : 1; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_0_misc_reset_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_0_misc_reset_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_0_PHY_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_0_phy_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_0_phy_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_0_phy_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_0_NOCSR_COM_PHY_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_0_nocsr_com_phy_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_0_nocsr_com_phy_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_0_nocsr_com_phy_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_0_phy_nocsr_com_phy_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_0_phy_nocsr_com_phy_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_0_phy_nocsr_com_phy_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_PHY_CFG_AHB_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_phy_cfg_ahb_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_phy_cfg_ahb_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_phy_cfg_ahb_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_PHY_COM_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_phy_com_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_phy_com_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_phy_com_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_1_LINK_DOWN_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_1_link_down_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_1_link_down_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_1_link_down_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_1_MISC_RESET +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_1_misc_reset_s +{ + u32 pcie_1_slv_axi_bcr_blk_ares : 1; + u32 pcie_1_mstr_axi_bcr_blk_ares : 1; + u32 pcie_1_cfg_ahb_bcr_blk_ares : 1; + u32 pcie_1_aux_bcr_blk_ares : 1; + u32 pcie_1_pipe_bcr_blk_ares : 1; + u32 pcie_1_mstr_axi_sticky_bcr_blk_ares : 1; + u32 pcie_1_core_sticky_bcr_blk_ares : 1; + u32 pcie_1_slv_axi_sticky_bcr_blk_ares : 1; + u32 pcie_1_phy_aux_bcr_blk_ares : 1; + u32 reserved0 : 23; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_1_misc_reset_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_1_misc_reset_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_1_PHY_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_1_phy_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_1_phy_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_1_phy_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_1_NOCSR_COM_PHY_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_1_nocsr_com_phy_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_1_nocsr_com_phy_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_1_nocsr_com_phy_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_1_phy_nocsr_com_phy_bcr_s +{ + u32 blk_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_1_phy_nocsr_com_phy_bcr_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_1_phy_nocsr_com_phy_bcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_LPASS_RESET +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_lpass_reset_s +{ + u32 lpass_ares : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_lpass_reset_u +{ + struct ipa_gcc_hwio_def_gcc_lpass_reset_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DEBUG_MUX_MUXR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_debug_mux_muxr_s +{ + u32 mux_sel : 10; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_debug_mux_muxr_u +{ + struct ipa_gcc_hwio_def_gcc_debug_mux_muxr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PLL_TEST_MUX_MUXR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pll_test_mux_muxr_s +{ + u32 out_sel : 6; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pll_test_mux_muxr_u +{ + struct ipa_gcc_hwio_def_gcc_pll_test_mux_muxr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PLL_STATUS_MUXR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pll_status_muxr_s +{ + u32 debug_bus_sel : 6; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pll_status_muxr_u +{ + struct ipa_gcc_hwio_def_gcc_pll_status_muxr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DEBUG_OR_PLL_TEST_MUX_MUXR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_debug_or_pll_test_mux_muxr_s +{ + u32 plltest_de_sel : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_debug_or_pll_test_mux_muxr_u +{ + struct ipa_gcc_hwio_def_gcc_debug_or_pll_test_mux_muxr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PLLTEST_PAD_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_plltest_pad_cfg_s +{ + u32 reserve_bits5_0 : 6; + u32 reserve_bits10_6 : 5; + u32 hdrive : 3; + u32 reserve_bit14 : 1; + u32 core_ie : 1; + u32 reserve_bit16 : 1; + u32 core_oe : 1; + u32 reserve_bit18 : 1; + u32 core_pll_en : 1; + u32 reserve_bits23_20 : 4; + u32 core_pll_b : 2; + u32 reserved0 : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_plltest_pad_cfg_u +{ + struct ipa_gcc_hwio_def_gcc_plltest_pad_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CLOCK_FRQ_MEASURE_CTL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_clock_frq_measure_ctl_s +{ + u32 xo_div4_term_cnt : 20; + u32 cnt_en : 1; + u32 clr_cnt : 1; + u32 reserved0 : 10; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_clock_frq_measure_ctl_u +{ + struct ipa_gcc_hwio_def_gcc_clock_frq_measure_ctl_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CLOCK_FRQ_MEASURE_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_clock_frq_measure_status_s +{ + u32 measure_cnt : 25; + u32 xo_div4_cnt_done : 1; + u32 reserved0 : 6; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_clock_frq_measure_status_u +{ + struct ipa_gcc_hwio_def_gcc_clock_frq_measure_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GDS_HW_CTRL_SW_OVRD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gds_hw_ctrl_sw_ovrd_s +{ + u32 sw_override : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gds_hw_ctrl_sw_ovrd_u +{ + struct ipa_gcc_hwio_def_gcc_gds_hw_ctrl_sw_ovrd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_VTT_EN_TIMER +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_vtt_en_timer_s +{ + u32 pvc_load_value : 20; + u32 reserved0 : 12; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_vtt_en_timer_u +{ + struct ipa_gcc_hwio_def_gcc_vtt_en_timer_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_VREF_EN_TIMER +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_vref_en_timer_s +{ + u32 pvc_load_value : 20; + u32 max_index : 2; + u32 reserved0 : 10; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_vref_en_timer_u +{ + struct ipa_gcc_hwio_def_gcc_vref_en_timer_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PLL_IS_ACTIVE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pll_is_active_s +{ + u32 gpll0_sel : 1; + u32 gpll1_sel : 1; + u32 reserved0 : 2; + u32 gpll4_sel : 1; + u32 gpll5_sel : 1; + u32 reserved1 : 26; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pll_is_active_u +{ + struct ipa_gcc_hwio_def_gcc_pll_is_active_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GDS_HW_CTRL_SPARE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gds_hw_ctrl_spare_s +{ + u32 spare : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gds_hw_ctrl_spare_u +{ + struct ipa_gcc_hwio_def_gcc_gds_hw_ctrl_spare_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_WCSS_PD_CLK_DIS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_wcss_pd_clk_dis_s +{ + u32 sw_override : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_wcss_pd_clk_dis_u +{ + struct ipa_gcc_hwio_def_gcc_wcss_pd_clk_dis_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPARE0_REG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spare0_reg_s +{ + u32 spare_bits : 32; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spare0_reg_u +{ + struct ipa_gcc_hwio_def_gcc_spare0_reg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPARE1_REG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spare1_reg_s +{ + u32 spare_bits : 32; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spare1_reg_u +{ + struct ipa_gcc_hwio_def_gcc_spare1_reg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPARE2_REG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spare2_reg_s +{ + u32 spare_bits : 32; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spare2_reg_u +{ + struct ipa_gcc_hwio_def_gcc_spare2_reg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPARE3_REG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spare3_reg_s +{ + u32 spare_bits : 32; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spare3_reg_u +{ + struct ipa_gcc_hwio_def_gcc_spare3_reg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPARE4_REG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spare4_reg_s +{ + u32 spare_bits : 32; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spare4_reg_u +{ + struct ipa_gcc_hwio_def_gcc_spare4_reg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPARE5_REG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spare5_reg_s +{ + u32 spare_bits : 32; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spare5_reg_u +{ + struct ipa_gcc_hwio_def_gcc_spare5_reg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPU_MISC +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpu_misc_s +{ + u32 gpll0_div_src_disable : 1; + u32 gpll0_src_disable : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpu_misc_u +{ + struct ipa_gcc_hwio_def_gcc_gpu_misc_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TME_MISC +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tme_misc_s +{ + u32 reserved0 : 1; + u32 gpll0_src_disable : 1; + u32 reserved1 : 30; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tme_misc_u +{ + struct ipa_gcc_hwio_def_gcc_tme_misc_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DDRSS_MISC +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ddrss_misc_s +{ + u32 reserved0 : 1; + u32 gpll0_src_disable : 1; + u32 reserved1 : 30; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ddrss_misc_u +{ + struct ipa_gcc_hwio_def_gcc_ddrss_misc_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DDRSS_MC_MISC_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_ddrss_mc_misc_status_s +{ + u32 reserved0 : 1; + u32 stall_req : 1; + u32 unstall : 1; + u32 stall_complete : 1; + u32 reserved1 : 28; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_ddrss_mc_misc_status_u +{ + struct ipa_gcc_hwio_def_gcc_ddrss_mc_misc_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TZ_VOTE_GPU_SMMU_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tz_vote_gpu_smmu_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tz_vote_gpu_smmu_clk_u +{ + struct ipa_gcc_hwio_def_gcc_tz_vote_gpu_smmu_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TZ_VOTE_LPASS_QTB_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tz_vote_lpass_qtb_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tz_vote_lpass_qtb_clk_u +{ + struct ipa_gcc_hwio_def_gcc_tz_vote_lpass_qtb_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB1_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tz_vote_aggre_noc_mmu_qtb1_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tz_vote_aggre_noc_mmu_qtb1_clk_u +{ + struct ipa_gcc_hwio_def_gcc_tz_vote_aggre_noc_mmu_qtb1_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB2_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tz_vote_aggre_noc_mmu_qtb2_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tz_vote_aggre_noc_mmu_qtb2_clk_u +{ + struct ipa_gcc_hwio_def_gcc_tz_vote_aggre_noc_mmu_qtb2_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tz_vote_aggre_noc_mmu_pcie_qtb_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tz_vote_aggre_noc_mmu_pcie_qtb_clk_u +{ + struct ipa_gcc_hwio_def_gcc_tz_vote_aggre_noc_mmu_pcie_qtb_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TZ_VOTE_MMNOC_MMU_QTB_SF_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tz_vote_mmnoc_mmu_qtb_sf_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tz_vote_mmnoc_mmu_qtb_sf_clk_u +{ + struct ipa_gcc_hwio_def_gcc_tz_vote_mmnoc_mmu_qtb_sf_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TZ_VOTE_MMNOC_MMU_QTB_HF01_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tz_vote_mmnoc_mmu_qtb_hf01_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tz_vote_mmnoc_mmu_qtb_hf01_clk_u +{ + struct ipa_gcc_hwio_def_gcc_tz_vote_mmnoc_mmu_qtb_hf01_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TZ_VOTE_TURING_MMU_QTB0_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tz_vote_turing_mmu_qtb0_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tz_vote_turing_mmu_qtb0_clk_u +{ + struct ipa_gcc_hwio_def_gcc_tz_vote_turing_mmu_qtb0_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TZ_VOTE_ALL_SMMU_MMU_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tz_vote_all_smmu_mmu_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tz_vote_all_smmu_mmu_clk_u +{ + struct ipa_gcc_hwio_def_gcc_tz_vote_all_smmu_mmu_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TZ_VOTE_MMU_TCU_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tz_vote_mmu_tcu_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tz_vote_mmu_tcu_clk_u +{ + struct ipa_gcc_hwio_def_gcc_tz_vote_mmu_tcu_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TZ_VOTE_GPU_SMMU_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tz_vote_gpu_smmu_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tz_vote_gpu_smmu_gds_u +{ + struct ipa_gcc_hwio_def_gcc_tz_vote_gpu_smmu_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TZ_VOTE_LPASS_QTB_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tz_vote_lpass_qtb_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tz_vote_lpass_qtb_gds_u +{ + struct ipa_gcc_hwio_def_gcc_tz_vote_lpass_qtb_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB1_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tz_vote_aggre_noc_mmu_qtb1_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tz_vote_aggre_noc_mmu_qtb1_gds_u +{ + struct ipa_gcc_hwio_def_gcc_tz_vote_aggre_noc_mmu_qtb1_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TZ_VOTE_AGGRE_NOC_MMU_QTB2_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tz_vote_aggre_noc_mmu_qtb2_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tz_vote_aggre_noc_mmu_qtb2_gds_u +{ + struct ipa_gcc_hwio_def_gcc_tz_vote_aggre_noc_mmu_qtb2_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tz_vote_aggre_noc_mmu_pcie_qtb_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tz_vote_aggre_noc_mmu_pcie_qtb_gds_u +{ + struct ipa_gcc_hwio_def_gcc_tz_vote_aggre_noc_mmu_pcie_qtb_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TZ_VOTE_MMNOC_MMU_QTB_HF01_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tz_vote_mmnoc_mmu_qtb_hf01_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tz_vote_mmnoc_mmu_qtb_hf01_gds_u +{ + struct ipa_gcc_hwio_def_gcc_tz_vote_mmnoc_mmu_qtb_hf01_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TZ_VOTE_MMNOC_MMU_QTB_SF_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tz_vote_mmnoc_mmu_qtb_sf_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tz_vote_mmnoc_mmu_qtb_sf_gds_u +{ + struct ipa_gcc_hwio_def_gcc_tz_vote_mmnoc_mmu_qtb_sf_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TZ_VOTE_TURING_MMU_QTB0_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tz_vote_turing_mmu_qtb0_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tz_vote_turing_mmu_qtb0_gds_u +{ + struct ipa_gcc_hwio_def_gcc_tz_vote_turing_mmu_qtb0_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TZ_VOTE_ALL_SMMU_MMU_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tz_vote_all_smmu_mmu_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tz_vote_all_smmu_mmu_gds_u +{ + struct ipa_gcc_hwio_def_gcc_tz_vote_all_smmu_mmu_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TZ_VOTE_MMU_TCU_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tz_vote_mmu_tcu_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tz_vote_mmu_tcu_gds_u +{ + struct ipa_gcc_hwio_def_gcc_tz_vote_mmu_tcu_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TZ_VOTE_MMNOC_MMU_QTB_HF23_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tz_vote_mmnoc_mmu_qtb_hf23_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tz_vote_mmnoc_mmu_qtb_hf23_clk_u +{ + struct ipa_gcc_hwio_def_gcc_tz_vote_mmnoc_mmu_qtb_hf23_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TZ_VOTE_MMNOC_MMU_QTB_HF23_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tz_vote_mmnoc_mmu_qtb_hf23_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tz_vote_mmnoc_mmu_qtb_hf23_gds_u +{ + struct ipa_gcc_hwio_def_gcc_tz_vote_mmnoc_mmu_qtb_hf23_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HYP_VOTE_GPU_SMMU_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hyp_vote_gpu_smmu_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hyp_vote_gpu_smmu_clk_u +{ + struct ipa_gcc_hwio_def_gcc_hyp_vote_gpu_smmu_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HYP_VOTE_LPASS_QTB_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hyp_vote_lpass_qtb_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hyp_vote_lpass_qtb_clk_u +{ + struct ipa_gcc_hwio_def_gcc_hyp_vote_lpass_qtb_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB1_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hyp_vote_aggre_noc_mmu_qtb1_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hyp_vote_aggre_noc_mmu_qtb1_clk_u +{ + struct ipa_gcc_hwio_def_gcc_hyp_vote_aggre_noc_mmu_qtb1_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB2_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hyp_vote_aggre_noc_mmu_qtb2_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hyp_vote_aggre_noc_mmu_qtb2_clk_u +{ + struct ipa_gcc_hwio_def_gcc_hyp_vote_aggre_noc_mmu_qtb2_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hyp_vote_aggre_noc_mmu_pcie_qtb_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hyp_vote_aggre_noc_mmu_pcie_qtb_clk_u +{ + struct ipa_gcc_hwio_def_gcc_hyp_vote_aggre_noc_mmu_pcie_qtb_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HYP_VOTE_MMNOC_MMU_QTB_SF_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hyp_vote_mmnoc_mmu_qtb_sf_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hyp_vote_mmnoc_mmu_qtb_sf_clk_u +{ + struct ipa_gcc_hwio_def_gcc_hyp_vote_mmnoc_mmu_qtb_sf_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HYP_VOTE_MMNOC_MMU_QTB_HF01_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hyp_vote_mmnoc_mmu_qtb_hf01_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hyp_vote_mmnoc_mmu_qtb_hf01_clk_u +{ + struct ipa_gcc_hwio_def_gcc_hyp_vote_mmnoc_mmu_qtb_hf01_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HYP_VOTE_TURING_MMU_QTB0_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hyp_vote_turing_mmu_qtb0_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hyp_vote_turing_mmu_qtb0_clk_u +{ + struct ipa_gcc_hwio_def_gcc_hyp_vote_turing_mmu_qtb0_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HYP_VOTE_ALL_SMMU_MMU_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hyp_vote_all_smmu_mmu_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hyp_vote_all_smmu_mmu_clk_u +{ + struct ipa_gcc_hwio_def_gcc_hyp_vote_all_smmu_mmu_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HYP_VOTE_MMU_TCU_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hyp_vote_mmu_tcu_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hyp_vote_mmu_tcu_clk_u +{ + struct ipa_gcc_hwio_def_gcc_hyp_vote_mmu_tcu_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HYP_VOTE_GPU_SMMU_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hyp_vote_gpu_smmu_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hyp_vote_gpu_smmu_gds_u +{ + struct ipa_gcc_hwio_def_gcc_hyp_vote_gpu_smmu_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HYP_VOTE_LPASS_QTB_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hyp_vote_lpass_qtb_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hyp_vote_lpass_qtb_gds_u +{ + struct ipa_gcc_hwio_def_gcc_hyp_vote_lpass_qtb_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB1_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hyp_vote_aggre_noc_mmu_qtb1_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hyp_vote_aggre_noc_mmu_qtb1_gds_u +{ + struct ipa_gcc_hwio_def_gcc_hyp_vote_aggre_noc_mmu_qtb1_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HYP_VOTE_AGGRE_NOC_MMU_QTB2_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hyp_vote_aggre_noc_mmu_qtb2_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hyp_vote_aggre_noc_mmu_qtb2_gds_u +{ + struct ipa_gcc_hwio_def_gcc_hyp_vote_aggre_noc_mmu_qtb2_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hyp_vote_aggre_noc_mmu_pcie_qtb_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hyp_vote_aggre_noc_mmu_pcie_qtb_gds_u +{ + struct ipa_gcc_hwio_def_gcc_hyp_vote_aggre_noc_mmu_pcie_qtb_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HYP_VOTE_MMNOC_MMU_QTB_HF01_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hyp_vote_mmnoc_mmu_qtb_hf01_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hyp_vote_mmnoc_mmu_qtb_hf01_gds_u +{ + struct ipa_gcc_hwio_def_gcc_hyp_vote_mmnoc_mmu_qtb_hf01_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HYP_VOTE_MMNOC_MMU_QTB_SF_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hyp_vote_mmnoc_mmu_qtb_sf_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hyp_vote_mmnoc_mmu_qtb_sf_gds_u +{ + struct ipa_gcc_hwio_def_gcc_hyp_vote_mmnoc_mmu_qtb_sf_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HYP_VOTE_TURING_MMU_QTB0_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hyp_vote_turing_mmu_qtb0_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hyp_vote_turing_mmu_qtb0_gds_u +{ + struct ipa_gcc_hwio_def_gcc_hyp_vote_turing_mmu_qtb0_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HYP_VOTE_ALL_SMMU_MMU_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hyp_vote_all_smmu_mmu_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hyp_vote_all_smmu_mmu_gds_u +{ + struct ipa_gcc_hwio_def_gcc_hyp_vote_all_smmu_mmu_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HYP_VOTE_MMU_TCU_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hyp_vote_mmu_tcu_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hyp_vote_mmu_tcu_gds_u +{ + struct ipa_gcc_hwio_def_gcc_hyp_vote_mmu_tcu_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HYP_VOTE_MMNOC_MMU_QTB_HF23_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hyp_vote_mmnoc_mmu_qtb_hf23_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hyp_vote_mmnoc_mmu_qtb_hf23_clk_u +{ + struct ipa_gcc_hwio_def_gcc_hyp_vote_mmnoc_mmu_qtb_hf23_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HYP_VOTE_MMNOC_MMU_QTB_HF23_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hyp_vote_mmnoc_mmu_qtb_hf23_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hyp_vote_mmnoc_mmu_qtb_hf23_gds_u +{ + struct ipa_gcc_hwio_def_gcc_hyp_vote_mmnoc_mmu_qtb_hf23_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HLOS1_VOTE_GPU_SMMU_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hlos1_vote_gpu_smmu_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hlos1_vote_gpu_smmu_clk_u +{ + struct ipa_gcc_hwio_def_gcc_hlos1_vote_gpu_smmu_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HLOS1_VOTE_LPASS_QTB_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hlos1_vote_lpass_qtb_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hlos1_vote_lpass_qtb_clk_u +{ + struct ipa_gcc_hwio_def_gcc_hlos1_vote_lpass_qtb_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB1_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hlos1_vote_aggre_noc_mmu_qtb1_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hlos1_vote_aggre_noc_mmu_qtb1_clk_u +{ + struct ipa_gcc_hwio_def_gcc_hlos1_vote_aggre_noc_mmu_qtb1_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB2_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hlos1_vote_aggre_noc_mmu_qtb2_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hlos1_vote_aggre_noc_mmu_qtb2_clk_u +{ + struct ipa_gcc_hwio_def_gcc_hlos1_vote_aggre_noc_mmu_qtb2_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hlos1_vote_aggre_noc_mmu_pcie_qtb_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hlos1_vote_aggre_noc_mmu_pcie_qtb_clk_u +{ + struct ipa_gcc_hwio_def_gcc_hlos1_vote_aggre_noc_mmu_pcie_qtb_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HLOS1_VOTE_MMNOC_MMU_QTB_SF_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hlos1_vote_mmnoc_mmu_qtb_sf_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hlos1_vote_mmnoc_mmu_qtb_sf_clk_u +{ + struct ipa_gcc_hwio_def_gcc_hlos1_vote_mmnoc_mmu_qtb_sf_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF01_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hlos1_vote_mmnoc_mmu_qtb_hf01_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hlos1_vote_mmnoc_mmu_qtb_hf01_clk_u +{ + struct ipa_gcc_hwio_def_gcc_hlos1_vote_mmnoc_mmu_qtb_hf01_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HLOS1_VOTE_TURING_MMU_QTB0_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hlos1_vote_turing_mmu_qtb0_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hlos1_vote_turing_mmu_qtb0_clk_u +{ + struct ipa_gcc_hwio_def_gcc_hlos1_vote_turing_mmu_qtb0_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hlos1_vote_all_smmu_mmu_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hlos1_vote_all_smmu_mmu_clk_u +{ + struct ipa_gcc_hwio_def_gcc_hlos1_vote_all_smmu_mmu_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HLOS1_VOTE_MMU_TCU_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hlos1_vote_mmu_tcu_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hlos1_vote_mmu_tcu_clk_u +{ + struct ipa_gcc_hwio_def_gcc_hlos1_vote_mmu_tcu_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HLOS1_VOTE_GPU_SMMU_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hlos1_vote_gpu_smmu_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hlos1_vote_gpu_smmu_gds_u +{ + struct ipa_gcc_hwio_def_gcc_hlos1_vote_gpu_smmu_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HLOS1_VOTE_LPASS_QTB_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hlos1_vote_lpass_qtb_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hlos1_vote_lpass_qtb_gds_u +{ + struct ipa_gcc_hwio_def_gcc_hlos1_vote_lpass_qtb_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB1_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hlos1_vote_aggre_noc_mmu_qtb1_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hlos1_vote_aggre_noc_mmu_qtb1_gds_u +{ + struct ipa_gcc_hwio_def_gcc_hlos1_vote_aggre_noc_mmu_qtb1_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HLOS1_VOTE_AGGRE_NOC_MMU_QTB2_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hlos1_vote_aggre_noc_mmu_qtb2_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hlos1_vote_aggre_noc_mmu_qtb2_gds_u +{ + struct ipa_gcc_hwio_def_gcc_hlos1_vote_aggre_noc_mmu_qtb2_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hlos1_vote_aggre_noc_mmu_pcie_qtb_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hlos1_vote_aggre_noc_mmu_pcie_qtb_gds_u +{ + struct ipa_gcc_hwio_def_gcc_hlos1_vote_aggre_noc_mmu_pcie_qtb_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF01_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hlos1_vote_mmnoc_mmu_qtb_hf01_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hlos1_vote_mmnoc_mmu_qtb_hf01_gds_u +{ + struct ipa_gcc_hwio_def_gcc_hlos1_vote_mmnoc_mmu_qtb_hf01_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HLOS1_VOTE_MMNOC_MMU_QTB_SF_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hlos1_vote_mmnoc_mmu_qtb_sf_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hlos1_vote_mmnoc_mmu_qtb_sf_gds_u +{ + struct ipa_gcc_hwio_def_gcc_hlos1_vote_mmnoc_mmu_qtb_sf_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HLOS1_VOTE_TURING_MMU_QTB0_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hlos1_vote_turing_mmu_qtb0_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hlos1_vote_turing_mmu_qtb0_gds_u +{ + struct ipa_gcc_hwio_def_gcc_hlos1_vote_turing_mmu_qtb0_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HLOS1_VOTE_ALL_SMMU_MMU_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hlos1_vote_all_smmu_mmu_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hlos1_vote_all_smmu_mmu_gds_u +{ + struct ipa_gcc_hwio_def_gcc_hlos1_vote_all_smmu_mmu_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HLOS1_VOTE_MMU_TCU_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hlos1_vote_mmu_tcu_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hlos1_vote_mmu_tcu_gds_u +{ + struct ipa_gcc_hwio_def_gcc_hlos1_vote_mmu_tcu_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF23_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hlos1_vote_mmnoc_mmu_qtb_hf23_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hlos1_vote_mmnoc_mmu_qtb_hf23_clk_u +{ + struct ipa_gcc_hwio_def_gcc_hlos1_vote_mmnoc_mmu_qtb_hf23_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HLOS1_VOTE_MMNOC_MMU_QTB_HF23_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hlos1_vote_mmnoc_mmu_qtb_hf23_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hlos1_vote_mmnoc_mmu_qtb_hf23_gds_u +{ + struct ipa_gcc_hwio_def_gcc_hlos1_vote_mmnoc_mmu_qtb_hf23_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HLOS2_VOTE_GPU_SMMU_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hlos2_vote_gpu_smmu_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hlos2_vote_gpu_smmu_clk_u +{ + struct ipa_gcc_hwio_def_gcc_hlos2_vote_gpu_smmu_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HLOS2_VOTE_LPASS_QTB_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hlos2_vote_lpass_qtb_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hlos2_vote_lpass_qtb_clk_u +{ + struct ipa_gcc_hwio_def_gcc_hlos2_vote_lpass_qtb_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB1_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hlos2_vote_aggre_noc_mmu_qtb1_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hlos2_vote_aggre_noc_mmu_qtb1_clk_u +{ + struct ipa_gcc_hwio_def_gcc_hlos2_vote_aggre_noc_mmu_qtb1_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB2_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hlos2_vote_aggre_noc_mmu_qtb2_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hlos2_vote_aggre_noc_mmu_qtb2_clk_u +{ + struct ipa_gcc_hwio_def_gcc_hlos2_vote_aggre_noc_mmu_qtb2_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hlos2_vote_aggre_noc_mmu_pcie_qtb_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hlos2_vote_aggre_noc_mmu_pcie_qtb_clk_u +{ + struct ipa_gcc_hwio_def_gcc_hlos2_vote_aggre_noc_mmu_pcie_qtb_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HLOS2_VOTE_MMNOC_MMU_QTB_SF_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hlos2_vote_mmnoc_mmu_qtb_sf_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hlos2_vote_mmnoc_mmu_qtb_sf_clk_u +{ + struct ipa_gcc_hwio_def_gcc_hlos2_vote_mmnoc_mmu_qtb_sf_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF01_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hlos2_vote_mmnoc_mmu_qtb_hf01_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hlos2_vote_mmnoc_mmu_qtb_hf01_clk_u +{ + struct ipa_gcc_hwio_def_gcc_hlos2_vote_mmnoc_mmu_qtb_hf01_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HLOS2_VOTE_TURING_MMU_QTB0_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hlos2_vote_turing_mmu_qtb0_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hlos2_vote_turing_mmu_qtb0_clk_u +{ + struct ipa_gcc_hwio_def_gcc_hlos2_vote_turing_mmu_qtb0_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hlos2_vote_all_smmu_mmu_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hlos2_vote_all_smmu_mmu_clk_u +{ + struct ipa_gcc_hwio_def_gcc_hlos2_vote_all_smmu_mmu_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HLOS2_VOTE_MMU_TCU_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hlos2_vote_mmu_tcu_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hlos2_vote_mmu_tcu_clk_u +{ + struct ipa_gcc_hwio_def_gcc_hlos2_vote_mmu_tcu_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HLOS2_VOTE_GPU_SMMU_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hlos2_vote_gpu_smmu_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hlos2_vote_gpu_smmu_gds_u +{ + struct ipa_gcc_hwio_def_gcc_hlos2_vote_gpu_smmu_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HLOS2_VOTE_LPASS_QTB_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hlos2_vote_lpass_qtb_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hlos2_vote_lpass_qtb_gds_u +{ + struct ipa_gcc_hwio_def_gcc_hlos2_vote_lpass_qtb_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB1_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hlos2_vote_aggre_noc_mmu_qtb1_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hlos2_vote_aggre_noc_mmu_qtb1_gds_u +{ + struct ipa_gcc_hwio_def_gcc_hlos2_vote_aggre_noc_mmu_qtb1_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HLOS2_VOTE_AGGRE_NOC_MMU_QTB2_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hlos2_vote_aggre_noc_mmu_qtb2_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hlos2_vote_aggre_noc_mmu_qtb2_gds_u +{ + struct ipa_gcc_hwio_def_gcc_hlos2_vote_aggre_noc_mmu_qtb2_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hlos2_vote_aggre_noc_mmu_pcie_qtb_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hlos2_vote_aggre_noc_mmu_pcie_qtb_gds_u +{ + struct ipa_gcc_hwio_def_gcc_hlos2_vote_aggre_noc_mmu_pcie_qtb_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF01_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hlos2_vote_mmnoc_mmu_qtb_hf01_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hlos2_vote_mmnoc_mmu_qtb_hf01_gds_u +{ + struct ipa_gcc_hwio_def_gcc_hlos2_vote_mmnoc_mmu_qtb_hf01_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HLOS2_VOTE_MMNOC_MMU_QTB_SF_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hlos2_vote_mmnoc_mmu_qtb_sf_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hlos2_vote_mmnoc_mmu_qtb_sf_gds_u +{ + struct ipa_gcc_hwio_def_gcc_hlos2_vote_mmnoc_mmu_qtb_sf_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HLOS2_VOTE_TURING_MMU_QTB0_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hlos2_vote_turing_mmu_qtb0_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hlos2_vote_turing_mmu_qtb0_gds_u +{ + struct ipa_gcc_hwio_def_gcc_hlos2_vote_turing_mmu_qtb0_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HLOS2_VOTE_ALL_SMMU_MMU_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hlos2_vote_all_smmu_mmu_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hlos2_vote_all_smmu_mmu_gds_u +{ + struct ipa_gcc_hwio_def_gcc_hlos2_vote_all_smmu_mmu_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HLOS2_VOTE_MMU_TCU_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hlos2_vote_mmu_tcu_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hlos2_vote_mmu_tcu_gds_u +{ + struct ipa_gcc_hwio_def_gcc_hlos2_vote_mmu_tcu_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF23_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hlos2_vote_mmnoc_mmu_qtb_hf23_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hlos2_vote_mmnoc_mmu_qtb_hf23_clk_u +{ + struct ipa_gcc_hwio_def_gcc_hlos2_vote_mmnoc_mmu_qtb_hf23_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HLOS2_VOTE_MMNOC_MMU_QTB_HF23_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hlos2_vote_mmnoc_mmu_qtb_hf23_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hlos2_vote_mmnoc_mmu_qtb_hf23_gds_u +{ + struct ipa_gcc_hwio_def_gcc_hlos2_vote_mmnoc_mmu_qtb_hf23_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MMNOC_GDS_HW_CTRL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mmnoc_gds_hw_ctrl_s +{ + u32 sw_override : 1; + u32 gds_hw_state : 5; + u32 halt_ack_timeout : 8; + u32 reserved0 : 1; + u32 collapse_out : 1; + u32 deny_enable : 1; + u32 max_retry : 4; + u32 hys_timer : 8; + u32 reserve_30_29 : 2; + u32 pwr_on_status : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mmnoc_gds_hw_ctrl_u +{ + struct ipa_gcc_hwio_def_gcc_mmnoc_gds_hw_ctrl_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MMNOC_GDS_HW_CTRL_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mmnoc_gds_hw_ctrl_status_s +{ + u32 halt1_pwr_up_ack_status : 2; + u32 halt1_pwr_down_deny_status : 2; + u32 dvm_halt1_pwr_down_deny_status : 2; + u32 halt1_pwr_down_ack_status : 2; + u32 halt2_pwr_up_ack_status : 1; + u32 halt2_pwr_down_ack_status : 1; + u32 dvm_halt1_pwr_up_ack_status : 2; + u32 dvm_halt1_pwr_down_ack_status : 2; + u32 halt2_pwr_down_deny_status : 1; + u32 dvm_halt1_req_status : 2; + u32 halt2_req_status : 1; + u32 halt1_req_status : 2; + u32 reserved0 : 12; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mmnoc_gds_hw_ctrl_status_u +{ + struct ipa_gcc_hwio_def_gcc_mmnoc_gds_hw_ctrl_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MMNOC_HALT_REQ_GDS_HW_CTRL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mmnoc_halt_req_gds_hw_ctrl_s +{ + u32 noc_halt_req : 1; + u32 mmu_qtb_halt_req : 2; + u32 dvm_halt_req : 2; + u32 reserve_4_15 : 12; + u32 reserved0 : 15; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mmnoc_halt_req_gds_hw_ctrl_u +{ + struct ipa_gcc_hwio_def_gcc_mmnoc_halt_req_gds_hw_ctrl_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MMNOC_GDS_HW_CTRL_IRQ_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mmnoc_gds_hw_ctrl_irq_status_s +{ + u32 status : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mmnoc_gds_hw_ctrl_irq_status_u +{ + struct ipa_gcc_hwio_def_gcc_mmnoc_gds_hw_ctrl_irq_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MMNOC_GDS_HW_CTRL_IRQ_MASK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mmnoc_gds_hw_ctrl_irq_mask_s +{ + u32 mask : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mmnoc_gds_hw_ctrl_irq_mask_u +{ + struct ipa_gcc_hwio_def_gcc_mmnoc_gds_hw_ctrl_irq_mask_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MMNOC_GDS_HW_CTRL_IRQ_CLEAR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mmnoc_gds_hw_ctrl_irq_clear_s +{ + u32 clear : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mmnoc_gds_hw_ctrl_irq_clear_u +{ + struct ipa_gcc_hwio_def_gcc_mmnoc_gds_hw_ctrl_irq_clear_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MMNOC_GDS_HW_CTRL_SPARE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mmnoc_gds_hw_ctrl_spare_s +{ + u32 spare : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mmnoc_gds_hw_ctrl_spare_u +{ + struct ipa_gcc_hwio_def_gcc_mmnoc_gds_hw_ctrl_spare_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ANOC_PCIE_GDS_HW_CTRL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_anoc_pcie_gds_hw_ctrl_s +{ + u32 sw_override : 1; + u32 gds_hw_state : 5; + u32 halt_ack_timeout : 8; + u32 reserved0 : 1; + u32 collapse_out : 1; + u32 deny_enable : 1; + u32 max_retry : 4; + u32 hys_timer : 8; + u32 reserve_30_29 : 2; + u32 pwr_on_status : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_anoc_pcie_gds_hw_ctrl_u +{ + struct ipa_gcc_hwio_def_gcc_anoc_pcie_gds_hw_ctrl_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ANOC_PCIE_GDS_HW_CTRL_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_anoc_pcie_gds_hw_ctrl_status_s +{ + u32 halt1_pwr_up_ack_status : 1; + u32 halt1_pwr_down_deny_status : 1; + u32 dvm_halt1_pwr_down_deny_status : 1; + u32 halt1_pwr_down_ack_status : 1; + u32 halt2_pwr_up_ack_status : 1; + u32 halt2_pwr_down_deny_status : 1; + u32 reserve_6_11 : 6; + u32 halt2_pwr_down_ack_status : 1; + u32 reserve_13_17 : 5; + u32 dvm_halt1_pwr_up_ack_status : 1; + u32 reserve_19 : 1; + u32 dvm_halt1_pwr_down_ack_status : 1; + u32 dvm_halt1_req_status : 1; + u32 halt2_req_status : 1; + u32 halt1_req_status : 1; + u32 reserve_24_31 : 8; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_anoc_pcie_gds_hw_ctrl_status_u +{ + struct ipa_gcc_hwio_def_gcc_anoc_pcie_gds_hw_ctrl_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ANOC_PCIE_HALT_REQ_GDS_HW_CTRL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_anoc_pcie_halt_req_gds_hw_ctrl_s +{ + u32 noc_halt_req : 1; + u32 mmu_qtb_halt_req : 1; + u32 dvm_halt_req : 1; + u32 reserve_3_15 : 13; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_anoc_pcie_halt_req_gds_hw_ctrl_u +{ + struct ipa_gcc_hwio_def_gcc_anoc_pcie_halt_req_gds_hw_ctrl_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ANOC_PCIE_GDS_HW_CTRL_IRQ_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_anoc_pcie_gds_hw_ctrl_irq_status_s +{ + u32 status : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_anoc_pcie_gds_hw_ctrl_irq_status_u +{ + struct ipa_gcc_hwio_def_gcc_anoc_pcie_gds_hw_ctrl_irq_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ANOC_PCIE_GDS_HW_CTRL_IRQ_MASK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_anoc_pcie_gds_hw_ctrl_irq_mask_s +{ + u32 mask : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_anoc_pcie_gds_hw_ctrl_irq_mask_u +{ + struct ipa_gcc_hwio_def_gcc_anoc_pcie_gds_hw_ctrl_irq_mask_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ANOC_PCIE_GDS_HW_CTRL_IRQ_CLEAR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_anoc_pcie_gds_hw_ctrl_irq_clear_s +{ + u32 clear : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_anoc_pcie_gds_hw_ctrl_irq_clear_u +{ + struct ipa_gcc_hwio_def_gcc_anoc_pcie_gds_hw_ctrl_irq_clear_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ANOC_PCIE_GDS_HW_CTRL_SPARE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_anoc_pcie_gds_hw_ctrl_spare_s +{ + u32 spare : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_anoc_pcie_gds_hw_ctrl_spare_u +{ + struct ipa_gcc_hwio_def_gcc_anoc_pcie_gds_hw_ctrl_spare_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TURING_QTB_GDS_HW_CTRL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_turing_qtb_gds_hw_ctrl_s +{ + u32 sw_override : 1; + u32 gds_hw_state : 5; + u32 halt_ack_timeout : 8; + u32 reserved0 : 1; + u32 collapse_out : 1; + u32 deny_enable : 1; + u32 max_retry : 4; + u32 hys_timer : 8; + u32 reserve_30_29 : 2; + u32 pwr_on_status : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_turing_qtb_gds_hw_ctrl_u +{ + struct ipa_gcc_hwio_def_gcc_turing_qtb_gds_hw_ctrl_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TURING_QTB_GDS_HW_CTRL_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_turing_qtb_gds_hw_ctrl_status_s +{ + u32 halt1_pwr_up_ack_status : 1; + u32 halt1_pwr_down_deny_status : 1; + u32 reserved0 : 1; + u32 dvm_halt1_pwr_down_deny_status : 1; + u32 halt1_pwr_down_ack_status : 1; + u32 halt2_pwr_up_ack_status : 1; + u32 halt2_pwr_down_deny_status : 1; + u32 halt2_pwr_down_ack_status : 1; + u32 reserve_8_17 : 10; + u32 dvm_halt1_pwr_up_ack_status : 1; + u32 reserve_19 : 1; + u32 dvm_halt1_pwr_down_ack_status : 1; + u32 dvm_halt1_req_status : 1; + u32 halt2_req_status : 1; + u32 halt1_req_status : 1; + u32 reserve_24_31 : 8; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_turing_qtb_gds_hw_ctrl_status_u +{ + struct ipa_gcc_hwio_def_gcc_turing_qtb_gds_hw_ctrl_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TURING_QTB_HALT_REQ_GDS_HW_CTRL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_turing_qtb_halt_req_gds_hw_ctrl_s +{ + u32 noc_halt_req : 1; + u32 mmu_qtb_halt_req : 1; + u32 dvm_halt_req : 1; + u32 reserve_3_15 : 13; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_turing_qtb_halt_req_gds_hw_ctrl_u +{ + struct ipa_gcc_hwio_def_gcc_turing_qtb_halt_req_gds_hw_ctrl_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TURING_QTB_GDS_HW_CTRL_IRQ_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_turing_qtb_gds_hw_ctrl_irq_status_s +{ + u32 status : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_turing_qtb_gds_hw_ctrl_irq_status_u +{ + struct ipa_gcc_hwio_def_gcc_turing_qtb_gds_hw_ctrl_irq_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TURING_QTB_GDS_HW_CTRL_IRQ_MASK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_turing_qtb_gds_hw_ctrl_irq_mask_s +{ + u32 mask : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_turing_qtb_gds_hw_ctrl_irq_mask_u +{ + struct ipa_gcc_hwio_def_gcc_turing_qtb_gds_hw_ctrl_irq_mask_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TURING_QTB_GDS_HW_CTRL_IRQ_CLEAR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_turing_qtb_gds_hw_ctrl_irq_clear_s +{ + u32 clear : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_turing_qtb_gds_hw_ctrl_irq_clear_u +{ + struct ipa_gcc_hwio_def_gcc_turing_qtb_gds_hw_ctrl_irq_clear_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TURING_QTB_GDS_HW_CTRL_SPARE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_turing_qtb_gds_hw_ctrl_spare_s +{ + u32 spare : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_turing_qtb_gds_hw_ctrl_spare_u +{ + struct ipa_gcc_hwio_def_gcc_turing_qtb_gds_hw_ctrl_spare_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_LPASS_QTB_GDS_HW_CTRL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_lpass_qtb_gds_hw_ctrl_s +{ + u32 sw_override : 1; + u32 gds_hw_state : 5; + u32 halt_ack_timeout : 8; + u32 reserved0 : 1; + u32 collapse_out : 1; + u32 deny_enable : 1; + u32 max_retry : 4; + u32 hys_timer : 8; + u32 reserve_30_29 : 2; + u32 pwr_on_status : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_lpass_qtb_gds_hw_ctrl_u +{ + struct ipa_gcc_hwio_def_gcc_lpass_qtb_gds_hw_ctrl_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_LPASS_QTB_GDS_HW_CTRL_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_lpass_qtb_gds_hw_ctrl_status_s +{ + u32 halt1_pwr_up_ack_status : 1; + u32 halt1_pwr_down_deny_status : 1; + u32 reserved0 : 1; + u32 dvm_halt1_pwr_down_deny_status : 1; + u32 halt1_pwr_down_ack_status : 1; + u32 halt2_pwr_up_ack_status : 1; + u32 halt2_pwr_down_deny_status : 1; + u32 halt2_pwr_down_ack_status : 1; + u32 reserve_8_17 : 10; + u32 dvm_halt1_pwr_up_ack_status : 1; + u32 reserve_19 : 1; + u32 dvm_halt1_pwr_down_ack_status : 1; + u32 dvm_halt1_req_status : 1; + u32 halt2_req_status : 1; + u32 halt1_req_status : 1; + u32 reserve_24_31 : 8; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_lpass_qtb_gds_hw_ctrl_status_u +{ + struct ipa_gcc_hwio_def_gcc_lpass_qtb_gds_hw_ctrl_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_LPASS_QTB_HALT_REQ_GDS_HW_CTRL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_lpass_qtb_halt_req_gds_hw_ctrl_s +{ + u32 noc_halt_req : 1; + u32 mmu_qtb_halt_req : 1; + u32 dvm_halt_req : 1; + u32 reserve_3_15 : 13; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_lpass_qtb_halt_req_gds_hw_ctrl_u +{ + struct ipa_gcc_hwio_def_gcc_lpass_qtb_halt_req_gds_hw_ctrl_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_LPASS_QTB_GDS_HW_CTRL_IRQ_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_lpass_qtb_gds_hw_ctrl_irq_status_s +{ + u32 status : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_lpass_qtb_gds_hw_ctrl_irq_status_u +{ + struct ipa_gcc_hwio_def_gcc_lpass_qtb_gds_hw_ctrl_irq_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_LPASS_QTB_GDS_HW_CTRL_IRQ_MASK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_lpass_qtb_gds_hw_ctrl_irq_mask_s +{ + u32 mask : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_lpass_qtb_gds_hw_ctrl_irq_mask_u +{ + struct ipa_gcc_hwio_def_gcc_lpass_qtb_gds_hw_ctrl_irq_mask_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_LPASS_QTB_GDS_HW_CTRL_IRQ_CLEAR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_lpass_qtb_gds_hw_ctrl_irq_clear_s +{ + u32 clear : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_lpass_qtb_gds_hw_ctrl_irq_clear_u +{ + struct ipa_gcc_hwio_def_gcc_lpass_qtb_gds_hw_ctrl_irq_clear_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_LPASS_QTB_GDS_HW_CTRL_SPARE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_lpass_qtb_gds_hw_ctrl_spare_s +{ + u32 spare : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_lpass_qtb_gds_hw_ctrl_spare_u +{ + struct ipa_gcc_hwio_def_gcc_lpass_qtb_gds_hw_ctrl_spare_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ANOC_QTB_GDS_HW_CTRL_SPARE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_anoc_qtb_gds_hw_ctrl_spare_s +{ + u32 spare : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_anoc_qtb_gds_hw_ctrl_spare_u +{ + struct ipa_gcc_hwio_def_gcc_anoc_qtb_gds_hw_ctrl_spare_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ANOC_QTB_RESET_CNTR_VALUE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_anoc_qtb_reset_cntr_value_s +{ + u32 count : 10; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_anoc_qtb_reset_cntr_value_u +{ + struct ipa_gcc_hwio_def_gcc_anoc_qtb_reset_cntr_value_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ANOC_QTB_PWR_QCHANNEL_HANDSHAKE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_anoc_qtb_pwr_qchannel_handshake_s +{ + u32 fsm_state : 5; + u32 reset_allowed : 1; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_anoc_qtb_pwr_qchannel_handshake_u +{ + struct ipa_gcc_hwio_def_gcc_anoc_qtb_pwr_qchannel_handshake_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ANOC_QTB_SREG_MISC +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_anoc_qtb_sreg_misc_s +{ + u32 qtb_1_micro_force_mem_core_on : 1; + u32 qtb_2_micro_force_mem_core_on : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_anoc_qtb_sreg_misc_u +{ + struct ipa_gcc_hwio_def_gcc_anoc_qtb_sreg_misc_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_LPASS_SREG_MISC +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_lpass_sreg_misc_s +{ + u32 audio_qtb_micro_force_mem_core_on : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_lpass_sreg_misc_u +{ + struct ipa_gcc_hwio_def_gcc_lpass_sreg_misc_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MMNOC_SREG_MISC +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mmnoc_sreg_misc_s +{ + u32 sf_micro_force_mem_core_on : 1; + u32 hf_micro_force_mem_core_on : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mmnoc_sreg_misc_u +{ + struct ipa_gcc_hwio_def_gcc_mmnoc_sreg_misc_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ANOC_PCIE_SREG_MISC +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_anoc_pcie_sreg_misc_s +{ + u32 aggre_noc_pcie_axi_micro_force_mem_core_on : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_anoc_pcie_sreg_misc_u +{ + struct ipa_gcc_hwio_def_gcc_anoc_pcie_sreg_misc_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TURING_QTB_SREG_MISC +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_turing_qtb_sreg_misc_s +{ + u32 qtb_0_micro_force_mem_core_on : 1; + u32 qtb_1_micro_force_mem_core_on : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_turing_qtb_sreg_misc_u +{ + struct ipa_gcc_hwio_def_gcc_turing_qtb_sreg_misc_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MMU_TCU_SREG_MISC +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mmu_tcu_sreg_misc_s +{ + u32 mmu_tcu_micro_force_mem_core_on : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mmu_tcu_sreg_misc_u +{ + struct ipa_gcc_hwio_def_gcc_mmu_tcu_sreg_misc_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CAMERA_SREG_MISC +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_camera_sreg_misc_s +{ + u32 sf_axi_micro_force_mem_core_on : 1; + u32 hf_axi_micro_force_mem_core_on : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_camera_sreg_misc_u +{ + struct ipa_gcc_hwio_def_gcc_camera_sreg_misc_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DISP_SREG_MISC +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_disp_sreg_misc_s +{ + u32 sf_axi_micro_force_mem_core_on : 1; + u32 hf_axi_micro_force_mem_core_on : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_disp_sreg_misc_u +{ + struct ipa_gcc_hwio_def_gcc_disp_sreg_misc_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_VIDEO_SREG_MISC +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_video_sreg_misc_s +{ + u32 axi_0_micro_force_mem_core_on : 1; + u32 axi_1_micro_force_mem_core_on : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_video_sreg_misc_u +{ + struct ipa_gcc_hwio_def_gcc_video_sreg_misc_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_0_SREG_MISC +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_0_sreg_misc_s +{ + u32 mstr_axi_micro_force_mem_core_on : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_0_sreg_misc_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_0_sreg_misc_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PCIE_1_SREG_MISC +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pcie_1_sreg_misc_s +{ + u32 mstr_axi_micro_force_mem_core_on : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pcie_1_sreg_misc_u +{ + struct ipa_gcc_hwio_def_gcc_pcie_1_sreg_misc_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SP_VOTE_GPU_SMMU_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sp_vote_gpu_smmu_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sp_vote_gpu_smmu_clk_u +{ + struct ipa_gcc_hwio_def_gcc_sp_vote_gpu_smmu_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SP_VOTE_LPASS_QTB_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sp_vote_lpass_qtb_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sp_vote_lpass_qtb_clk_u +{ + struct ipa_gcc_hwio_def_gcc_sp_vote_lpass_qtb_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SP_VOTE_AGGRE_NOC_MMU_QTB1_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sp_vote_aggre_noc_mmu_qtb1_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sp_vote_aggre_noc_mmu_qtb1_clk_u +{ + struct ipa_gcc_hwio_def_gcc_sp_vote_aggre_noc_mmu_qtb1_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SP_VOTE_AGGRE_NOC_MMU_QTB2_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sp_vote_aggre_noc_mmu_qtb2_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sp_vote_aggre_noc_mmu_qtb2_clk_u +{ + struct ipa_gcc_hwio_def_gcc_sp_vote_aggre_noc_mmu_qtb2_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sp_vote_aggre_noc_mmu_pcie_qtb_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sp_vote_aggre_noc_mmu_pcie_qtb_clk_u +{ + struct ipa_gcc_hwio_def_gcc_sp_vote_aggre_noc_mmu_pcie_qtb_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SP_VOTE_MMNOC_MMU_QTB_SF_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sp_vote_mmnoc_mmu_qtb_sf_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sp_vote_mmnoc_mmu_qtb_sf_clk_u +{ + struct ipa_gcc_hwio_def_gcc_sp_vote_mmnoc_mmu_qtb_sf_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SP_VOTE_MMNOC_MMU_QTB_HF01_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sp_vote_mmnoc_mmu_qtb_hf01_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sp_vote_mmnoc_mmu_qtb_hf01_clk_u +{ + struct ipa_gcc_hwio_def_gcc_sp_vote_mmnoc_mmu_qtb_hf01_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SP_VOTE_TURING_MMU_QTB0_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sp_vote_turing_mmu_qtb0_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sp_vote_turing_mmu_qtb0_clk_u +{ + struct ipa_gcc_hwio_def_gcc_sp_vote_turing_mmu_qtb0_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SP_VOTE_ALL_SMMU_MMU_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sp_vote_all_smmu_mmu_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sp_vote_all_smmu_mmu_clk_u +{ + struct ipa_gcc_hwio_def_gcc_sp_vote_all_smmu_mmu_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SP_VOTE_MMU_TCU_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sp_vote_mmu_tcu_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sp_vote_mmu_tcu_clk_u +{ + struct ipa_gcc_hwio_def_gcc_sp_vote_mmu_tcu_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SP_VOTE_GPU_SMMU_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sp_vote_gpu_smmu_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sp_vote_gpu_smmu_gds_u +{ + struct ipa_gcc_hwio_def_gcc_sp_vote_gpu_smmu_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SP_VOTE_LPASS_QTB_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sp_vote_lpass_qtb_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sp_vote_lpass_qtb_gds_u +{ + struct ipa_gcc_hwio_def_gcc_sp_vote_lpass_qtb_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SP_VOTE_AGGRE_NOC_MMU_QTB1_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sp_vote_aggre_noc_mmu_qtb1_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sp_vote_aggre_noc_mmu_qtb1_gds_u +{ + struct ipa_gcc_hwio_def_gcc_sp_vote_aggre_noc_mmu_qtb1_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SP_VOTE_AGGRE_NOC_MMU_QTB2_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sp_vote_aggre_noc_mmu_qtb2_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sp_vote_aggre_noc_mmu_qtb2_gds_u +{ + struct ipa_gcc_hwio_def_gcc_sp_vote_aggre_noc_mmu_qtb2_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sp_vote_aggre_noc_mmu_pcie_qtb_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sp_vote_aggre_noc_mmu_pcie_qtb_gds_u +{ + struct ipa_gcc_hwio_def_gcc_sp_vote_aggre_noc_mmu_pcie_qtb_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SP_VOTE_MMNOC_MMU_QTB_HF01_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sp_vote_mmnoc_mmu_qtb_hf01_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sp_vote_mmnoc_mmu_qtb_hf01_gds_u +{ + struct ipa_gcc_hwio_def_gcc_sp_vote_mmnoc_mmu_qtb_hf01_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SP_VOTE_MMNOC_MMU_QTB_SF_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sp_vote_mmnoc_mmu_qtb_sf_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sp_vote_mmnoc_mmu_qtb_sf_gds_u +{ + struct ipa_gcc_hwio_def_gcc_sp_vote_mmnoc_mmu_qtb_sf_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SP_VOTE_TURING_MMU_QTB0_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sp_vote_turing_mmu_qtb0_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sp_vote_turing_mmu_qtb0_gds_u +{ + struct ipa_gcc_hwio_def_gcc_sp_vote_turing_mmu_qtb0_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SP_VOTE_ALL_SMMU_MMU_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sp_vote_all_smmu_mmu_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sp_vote_all_smmu_mmu_gds_u +{ + struct ipa_gcc_hwio_def_gcc_sp_vote_all_smmu_mmu_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SP_VOTE_MMU_TCU_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sp_vote_mmu_tcu_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sp_vote_mmu_tcu_gds_u +{ + struct ipa_gcc_hwio_def_gcc_sp_vote_mmu_tcu_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SP_VOTE_MMNOC_MMU_QTB_HF23_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sp_vote_mmnoc_mmu_qtb_hf23_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sp_vote_mmnoc_mmu_qtb_hf23_clk_u +{ + struct ipa_gcc_hwio_def_gcc_sp_vote_mmnoc_mmu_qtb_hf23_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SP_VOTE_MMNOC_MMU_QTB_HF23_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sp_vote_mmnoc_mmu_qtb_hf23_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sp_vote_mmnoc_mmu_qtb_hf23_gds_u +{ + struct ipa_gcc_hwio_def_gcc_sp_vote_mmnoc_mmu_qtb_hf23_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_VOTE_GPU_SMMU_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_vote_gpu_smmu_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_vote_gpu_smmu_clk_u +{ + struct ipa_gcc_hwio_def_gcc_mss_vote_gpu_smmu_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_VOTE_LPASS_QTB_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_vote_lpass_qtb_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_vote_lpass_qtb_clk_u +{ + struct ipa_gcc_hwio_def_gcc_mss_vote_lpass_qtb_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB1_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_vote_aggre_noc_mmu_qtb1_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_vote_aggre_noc_mmu_qtb1_clk_u +{ + struct ipa_gcc_hwio_def_gcc_mss_vote_aggre_noc_mmu_qtb1_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB2_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_vote_aggre_noc_mmu_qtb2_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_vote_aggre_noc_mmu_qtb2_clk_u +{ + struct ipa_gcc_hwio_def_gcc_mss_vote_aggre_noc_mmu_qtb2_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_vote_aggre_noc_mmu_pcie_qtb_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_vote_aggre_noc_mmu_pcie_qtb_clk_u +{ + struct ipa_gcc_hwio_def_gcc_mss_vote_aggre_noc_mmu_pcie_qtb_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_VOTE_MMNOC_MMU_QTB_SF_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_vote_mmnoc_mmu_qtb_sf_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_vote_mmnoc_mmu_qtb_sf_clk_u +{ + struct ipa_gcc_hwio_def_gcc_mss_vote_mmnoc_mmu_qtb_sf_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_VOTE_MMNOC_MMU_QTB_HF01_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_vote_mmnoc_mmu_qtb_hf01_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_vote_mmnoc_mmu_qtb_hf01_clk_u +{ + struct ipa_gcc_hwio_def_gcc_mss_vote_mmnoc_mmu_qtb_hf01_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_VOTE_TURING_MMU_QTB0_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_vote_turing_mmu_qtb0_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_vote_turing_mmu_qtb0_clk_u +{ + struct ipa_gcc_hwio_def_gcc_mss_vote_turing_mmu_qtb0_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_VOTE_ALL_SMMU_MMU_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_vote_all_smmu_mmu_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_vote_all_smmu_mmu_clk_u +{ + struct ipa_gcc_hwio_def_gcc_mss_vote_all_smmu_mmu_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_VOTE_MMU_TCU_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_vote_mmu_tcu_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_vote_mmu_tcu_clk_u +{ + struct ipa_gcc_hwio_def_gcc_mss_vote_mmu_tcu_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_VOTE_GPU_SMMU_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_vote_gpu_smmu_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_vote_gpu_smmu_gds_u +{ + struct ipa_gcc_hwio_def_gcc_mss_vote_gpu_smmu_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_VOTE_LPASS_QTB_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_vote_lpass_qtb_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_vote_lpass_qtb_gds_u +{ + struct ipa_gcc_hwio_def_gcc_mss_vote_lpass_qtb_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB1_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_vote_aggre_noc_mmu_qtb1_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_vote_aggre_noc_mmu_qtb1_gds_u +{ + struct ipa_gcc_hwio_def_gcc_mss_vote_aggre_noc_mmu_qtb1_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_VOTE_AGGRE_NOC_MMU_QTB2_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_vote_aggre_noc_mmu_qtb2_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_vote_aggre_noc_mmu_qtb2_gds_u +{ + struct ipa_gcc_hwio_def_gcc_mss_vote_aggre_noc_mmu_qtb2_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_vote_aggre_noc_mmu_pcie_qtb_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_vote_aggre_noc_mmu_pcie_qtb_gds_u +{ + struct ipa_gcc_hwio_def_gcc_mss_vote_aggre_noc_mmu_pcie_qtb_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_VOTE_MMNOC_MMU_QTB_HF01_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_vote_mmnoc_mmu_qtb_hf01_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_vote_mmnoc_mmu_qtb_hf01_gds_u +{ + struct ipa_gcc_hwio_def_gcc_mss_vote_mmnoc_mmu_qtb_hf01_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_VOTE_MMNOC_MMU_QTB_SF_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_vote_mmnoc_mmu_qtb_sf_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_vote_mmnoc_mmu_qtb_sf_gds_u +{ + struct ipa_gcc_hwio_def_gcc_mss_vote_mmnoc_mmu_qtb_sf_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_VOTE_TURING_MMU_QTB0_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_vote_turing_mmu_qtb0_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_vote_turing_mmu_qtb0_gds_u +{ + struct ipa_gcc_hwio_def_gcc_mss_vote_turing_mmu_qtb0_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_VOTE_ALL_SMMU_MMU_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_vote_all_smmu_mmu_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_vote_all_smmu_mmu_gds_u +{ + struct ipa_gcc_hwio_def_gcc_mss_vote_all_smmu_mmu_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_VOTE_MMU_TCU_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_vote_mmu_tcu_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_vote_mmu_tcu_gds_u +{ + struct ipa_gcc_hwio_def_gcc_mss_vote_mmu_tcu_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_VOTE_MMNOC_MMU_QTB_HF23_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_vote_mmnoc_mmu_qtb_hf23_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_vote_mmnoc_mmu_qtb_hf23_clk_u +{ + struct ipa_gcc_hwio_def_gcc_mss_vote_mmnoc_mmu_qtb_hf23_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_VOTE_MMNOC_MMU_QTB_HF23_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_vote_mmnoc_mmu_qtb_hf23_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_vote_mmnoc_mmu_qtb_hf23_gds_u +{ + struct ipa_gcc_hwio_def_gcc_mss_vote_mmnoc_mmu_qtb_hf23_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TURING_DSP_VOTE_GPU_SMMU_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_turing_dsp_vote_gpu_smmu_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_turing_dsp_vote_gpu_smmu_clk_u +{ + struct ipa_gcc_hwio_def_gcc_turing_dsp_vote_gpu_smmu_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TURING_DSP_VOTE_LPASS_QTB_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_turing_dsp_vote_lpass_qtb_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_turing_dsp_vote_lpass_qtb_clk_u +{ + struct ipa_gcc_hwio_def_gcc_turing_dsp_vote_lpass_qtb_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB1_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_turing_dsp_vote_aggre_noc_mmu_qtb1_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_turing_dsp_vote_aggre_noc_mmu_qtb1_clk_u +{ + struct ipa_gcc_hwio_def_gcc_turing_dsp_vote_aggre_noc_mmu_qtb1_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB2_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_turing_dsp_vote_aggre_noc_mmu_qtb2_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_turing_dsp_vote_aggre_noc_mmu_qtb2_clk_u +{ + struct ipa_gcc_hwio_def_gcc_turing_dsp_vote_aggre_noc_mmu_qtb2_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_turing_dsp_vote_aggre_noc_mmu_pcie_qtb_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_turing_dsp_vote_aggre_noc_mmu_pcie_qtb_clk_u +{ + struct ipa_gcc_hwio_def_gcc_turing_dsp_vote_aggre_noc_mmu_pcie_qtb_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_SF_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_turing_dsp_vote_mmnoc_mmu_qtb_sf_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_turing_dsp_vote_mmnoc_mmu_qtb_sf_clk_u +{ + struct ipa_gcc_hwio_def_gcc_turing_dsp_vote_mmnoc_mmu_qtb_sf_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF01_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_turing_dsp_vote_mmnoc_mmu_qtb_hf01_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_turing_dsp_vote_mmnoc_mmu_qtb_hf01_clk_u +{ + struct ipa_gcc_hwio_def_gcc_turing_dsp_vote_mmnoc_mmu_qtb_hf01_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TURING_DSP_VOTE_TURING_MMU_QTB0_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_turing_dsp_vote_turing_mmu_qtb0_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_turing_dsp_vote_turing_mmu_qtb0_clk_u +{ + struct ipa_gcc_hwio_def_gcc_turing_dsp_vote_turing_mmu_qtb0_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_turing_dsp_vote_all_smmu_mmu_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_turing_dsp_vote_all_smmu_mmu_clk_u +{ + struct ipa_gcc_hwio_def_gcc_turing_dsp_vote_all_smmu_mmu_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TURING_DSP_VOTE_MMU_TCU_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_turing_dsp_vote_mmu_tcu_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_turing_dsp_vote_mmu_tcu_clk_u +{ + struct ipa_gcc_hwio_def_gcc_turing_dsp_vote_mmu_tcu_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TURING_DSP_VOTE_GPU_SMMU_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_turing_dsp_vote_gpu_smmu_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_turing_dsp_vote_gpu_smmu_gds_u +{ + struct ipa_gcc_hwio_def_gcc_turing_dsp_vote_gpu_smmu_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TURING_DSP_VOTE_LPASS_QTB_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_turing_dsp_vote_lpass_qtb_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_turing_dsp_vote_lpass_qtb_gds_u +{ + struct ipa_gcc_hwio_def_gcc_turing_dsp_vote_lpass_qtb_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB1_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_turing_dsp_vote_aggre_noc_mmu_qtb1_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_turing_dsp_vote_aggre_noc_mmu_qtb1_gds_u +{ + struct ipa_gcc_hwio_def_gcc_turing_dsp_vote_aggre_noc_mmu_qtb1_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_QTB2_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_turing_dsp_vote_aggre_noc_mmu_qtb2_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_turing_dsp_vote_aggre_noc_mmu_qtb2_gds_u +{ + struct ipa_gcc_hwio_def_gcc_turing_dsp_vote_aggre_noc_mmu_qtb2_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_QTB_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_turing_dsp_vote_aggre_noc_mmu_pcie_qtb_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_turing_dsp_vote_aggre_noc_mmu_pcie_qtb_gds_u +{ + struct ipa_gcc_hwio_def_gcc_turing_dsp_vote_aggre_noc_mmu_pcie_qtb_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF01_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_turing_dsp_vote_mmnoc_mmu_qtb_hf01_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_turing_dsp_vote_mmnoc_mmu_qtb_hf01_gds_u +{ + struct ipa_gcc_hwio_def_gcc_turing_dsp_vote_mmnoc_mmu_qtb_hf01_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_SF_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_turing_dsp_vote_mmnoc_mmu_qtb_sf_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_turing_dsp_vote_mmnoc_mmu_qtb_sf_gds_u +{ + struct ipa_gcc_hwio_def_gcc_turing_dsp_vote_mmnoc_mmu_qtb_sf_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TURING_DSP_VOTE_TURING_MMU_QTB0_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_turing_dsp_vote_turing_mmu_qtb0_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_turing_dsp_vote_turing_mmu_qtb0_gds_u +{ + struct ipa_gcc_hwio_def_gcc_turing_dsp_vote_turing_mmu_qtb0_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_turing_dsp_vote_all_smmu_mmu_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_turing_dsp_vote_all_smmu_mmu_gds_u +{ + struct ipa_gcc_hwio_def_gcc_turing_dsp_vote_all_smmu_mmu_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TURING_DSP_VOTE_MMU_TCU_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_turing_dsp_vote_mmu_tcu_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_turing_dsp_vote_mmu_tcu_gds_u +{ + struct ipa_gcc_hwio_def_gcc_turing_dsp_vote_mmu_tcu_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF23_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_turing_dsp_vote_mmnoc_mmu_qtb_hf23_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_turing_dsp_vote_mmnoc_mmu_qtb_hf23_clk_u +{ + struct ipa_gcc_hwio_def_gcc_turing_dsp_vote_mmnoc_mmu_qtb_hf23_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TURING_DSP_VOTE_MMNOC_MMU_QTB_HF23_GDS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_turing_dsp_vote_mmnoc_mmu_qtb_hf23_gds_s +{ + u32 sw_collapse : 1; + u32 reserved0 : 30; + u32 pwr_on : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_turing_dsp_vote_mmnoc_mmu_qtb_hf23_gds_u +{ + struct ipa_gcc_hwio_def_gcc_turing_dsp_vote_mmnoc_mmu_qtb_hf23_gds_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TURING_DSP_VOTE_QDSS_APB_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_turing_dsp_vote_qdss_apb_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_turing_dsp_vote_qdss_apb_clk_u +{ + struct ipa_gcc_hwio_def_gcc_turing_dsp_vote_qdss_apb_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPM_VOTE_QDSS_APB_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpm_vote_qdss_apb_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpm_vote_qdss_apb_clk_u +{ + struct ipa_gcc_hwio_def_gcc_rpm_vote_qdss_apb_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_Q6_VOTE_QDSS_APB_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_q6_vote_qdss_apb_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_q6_vote_qdss_apb_clk_u +{ + struct ipa_gcc_hwio_def_gcc_mss_q6_vote_qdss_apb_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_APCS_VOTE_QDSS_APB_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_apcs_vote_qdss_apb_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_apcs_vote_qdss_apb_clk_u +{ + struct ipa_gcc_hwio_def_gcc_apcs_vote_qdss_apb_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_APCS_TZ_VOTE_QDSS_APB_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_apcs_tz_vote_qdss_apb_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_apcs_tz_vote_qdss_apb_clk_u +{ + struct ipa_gcc_hwio_def_gcc_apcs_tz_vote_qdss_apb_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_LPASS_DSP_VOTE_QDSS_APB_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_lpass_dsp_vote_qdss_apb_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_lpass_dsp_vote_qdss_apb_clk_u +{ + struct ipa_gcc_hwio_def_gcc_lpass_dsp_vote_qdss_apb_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HYP_VOTE_QDSS_APB_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hyp_vote_qdss_apb_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hyp_vote_qdss_apb_clk_u +{ + struct ipa_gcc_hwio_def_gcc_hyp_vote_qdss_apb_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPARE1_VOTE_QDSS_APB_CLK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spare1_vote_qdss_apb_clk_s +{ + u32 clk_enable : 1; + u32 reserved0 : 30; + u32 clk_off : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spare1_vote_qdss_apb_clk_u +{ + struct ipa_gcc_hwio_def_gcc_spare1_vote_qdss_apb_clk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_JBIST_MODE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_jbist_mode_s +{ + u32 sleep_n : 1; + u32 reset_n : 1; + u32 jbist_test : 1; + u32 start_meas : 1; + u32 pll_lock_det : 1; + u32 dll_clk_ext1_mux_sel : 2; + u32 dll_clk_ext2_mux_sel : 2; + u32 jbist_enable : 1; + u32 jbist_pass : 1; + u32 reserve_bits31_9 : 21; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_jbist_mode_u +{ + struct ipa_gcc_hwio_def_gcc_jbist_mode_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_JBIST_MEAS_DONE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_jbist_meas_done_s +{ + u32 jbist_data_stream_rdy : 1; + u32 reserve_bits31_1 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_jbist_meas_done_u +{ + struct ipa_gcc_hwio_def_gcc_jbist_meas_done_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GLOBAL_EN +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_global_en_s +{ + u32 east_enable : 1; + u32 west_enable : 1; + u32 north_enable : 1; + u32 south_enable : 1; + u32 center_enable : 1; + u32 peripherals_enable : 1; + u32 rest_enable : 1; + u32 mem_enable_0 : 1; + u32 mem_enable_1 : 1; + u32 mem_enable_2 : 1; + u32 mem_enable_3 : 1; + u32 mem_enable_4 : 1; + u32 mem_enable_5 : 1; + u32 mem_enable_6 : 1; + u32 mem_enable_7 : 1; + u32 spare_enable : 17; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_global_en_u +{ + struct ipa_gcc_hwio_def_gcc_global_en_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_DEBUG_EN +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_debug_en_s +{ + u32 cdbgpwrupreq : 1; + u32 spare_enable : 30; + u32 cdbgpwrupack : 1; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_debug_en_u +{ + struct ipa_gcc_hwio_def_gcc_debug_en_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_CAM_CC_SGDSCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_cam_cc_sgdscr_s +{ + u32 sw_override : 1; + u32 retain_ff_enable : 1; + u32 pre_pwrup_retain_ff_enable : 1; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_cam_cc_sgdscr_u +{ + struct ipa_gcc_hwio_def_gcc_cam_cc_sgdscr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf0_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf0_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf0_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf1_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf1_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf1_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf2_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf2_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf2_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf3_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf3_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf3_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf4_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf4_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf4_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf5_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf5_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf5_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf6_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf6_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf6_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf7_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf7_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf7_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf8_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf8_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf8_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf9_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf9_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf9_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf10_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf10_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf10_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf11_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf11_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf11_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf12_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf12_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf12_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf13_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf13_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf13_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf14_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf14_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf14_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf15_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf15_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_perf15_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_PERF0_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf0_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf0_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf0_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_PERF1_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf1_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf1_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf1_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_PERF2_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf2_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf2_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf2_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_PERF3_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf3_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf3_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf3_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_PERF4_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf4_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf4_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf4_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_PERF5_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf5_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf5_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf5_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_PERF6_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf6_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf6_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf6_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_PERF7_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf7_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf7_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf7_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_PERF8_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf8_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf8_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf8_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_PERF9_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf9_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf9_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf9_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_PERF10_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf10_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf10_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf10_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_PERF11_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf11_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf11_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf11_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_PERF12_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf12_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf12_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf12_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_PERF13_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf13_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf13_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf13_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_PERF14_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf14_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf14_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf14_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_PERF15_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf15_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf15_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_perf15_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_PERF0_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf0_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_perf0_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf0_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_PERF1_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf1_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_perf1_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf1_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_PERF2_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf2_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_perf2_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf2_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_PERF3_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf3_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_perf3_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf3_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_PERF4_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf4_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_perf4_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf4_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_PERF5_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf5_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_perf5_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf5_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_PERF6_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf6_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_perf6_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf6_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_PERF7_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf7_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_perf7_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf7_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_PERF8_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf8_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_perf8_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf8_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_PERF9_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf9_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_perf9_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf9_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_PERF10_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf10_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_perf10_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf10_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_PERF11_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf11_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_perf11_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf11_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_PERF12_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf12_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_perf12_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf12_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_PERF13_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf13_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_perf13_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf13_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_PERF14_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf14_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_perf14_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf14_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_PERF15_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf15_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_perf15_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_perf15_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_MMNOC_PERF0_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_perf0_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_mmnoc_perf0_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_perf0_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_MMNOC_PERF1_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_perf1_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_mmnoc_perf1_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_perf1_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_MMNOC_PERF2_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_perf2_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_mmnoc_perf2_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_perf2_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_MMNOC_PERF3_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_perf3_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_mmnoc_perf3_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_perf3_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_MMNOC_PERF4_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_perf4_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_mmnoc_perf4_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_perf4_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_MMNOC_PERF5_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_perf5_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_mmnoc_perf5_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_perf5_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_MMNOC_PERF6_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_perf6_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_mmnoc_perf6_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_perf6_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_MMNOC_PERF7_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_perf7_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_mmnoc_perf7_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_perf7_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_MMNOC_PERF8_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_perf8_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_mmnoc_perf8_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_perf8_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_MMNOC_PERF9_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_perf9_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_mmnoc_perf9_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_perf9_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_MMNOC_PERF10_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_perf10_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_mmnoc_perf10_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_perf10_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_MMNOC_PERF11_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_perf11_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_mmnoc_perf11_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_perf11_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_MMNOC_PERF12_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_perf12_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_mmnoc_perf12_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_perf12_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_MMNOC_PERF13_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_perf13_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_mmnoc_perf13_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_perf13_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_MMNOC_PERF14_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_perf14_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_mmnoc_perf14_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_perf14_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_MMNOC_PERF15_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_perf15_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_mmnoc_perf15_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_perf15_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_perf0_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_perf0_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_perf0_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_perf1_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_perf1_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_perf1_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_perf2_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_perf2_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_perf2_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_perf3_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_perf3_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_perf3_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_perf4_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_perf4_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_perf4_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_perf5_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_perf5_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_perf5_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_perf6_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_perf6_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_perf6_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_perf7_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_perf7_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_perf7_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_perf8_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_perf8_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_perf8_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_perf9_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_perf9_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_perf9_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_perf10_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_perf10_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_perf10_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_perf11_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_perf11_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_perf11_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_perf12_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_perf12_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_perf12_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_perf13_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_perf13_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_perf13_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_perf14_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_perf14_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_perf14_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_perf15_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_perf15_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_perf15_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PMU_PERF0_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pmu_perf0_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pmu_perf0_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pmu_perf0_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PMU_PERF1_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pmu_perf1_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pmu_perf1_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pmu_perf1_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PMU_PERF2_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pmu_perf2_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pmu_perf2_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pmu_perf2_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PMU_PERF3_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pmu_perf3_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pmu_perf3_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pmu_perf3_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PMU_PERF4_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pmu_perf4_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pmu_perf4_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pmu_perf4_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PMU_PERF5_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pmu_perf5_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pmu_perf5_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pmu_perf5_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PMU_PERF6_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pmu_perf6_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pmu_perf6_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pmu_perf6_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PMU_PERF7_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pmu_perf7_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pmu_perf7_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pmu_perf7_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PMU_PERF8_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pmu_perf8_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pmu_perf8_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pmu_perf8_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PMU_PERF9_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pmu_perf9_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pmu_perf9_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pmu_perf9_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PMU_PERF10_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pmu_perf10_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pmu_perf10_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pmu_perf10_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PMU_PERF11_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pmu_perf11_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pmu_perf11_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pmu_perf11_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PMU_PERF12_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pmu_perf12_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pmu_perf12_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pmu_perf12_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PMU_PERF13_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pmu_perf13_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pmu_perf13_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pmu_perf13_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PMU_PERF14_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pmu_perf14_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pmu_perf14_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pmu_perf14_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PMU_PERF15_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pmu_perf15_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pmu_perf15_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pmu_perf15_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_PERF0_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf0_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_perf0_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf0_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_PERF1_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf1_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_perf1_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf1_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_PERF2_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf2_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_perf2_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf2_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_PERF3_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf3_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_perf3_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf3_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_PERF4_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf4_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_perf4_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf4_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_PERF5_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf5_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_perf5_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf5_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_PERF6_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf6_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_perf6_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf6_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_PERF7_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf7_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_perf7_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf7_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_PERF8_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf8_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_perf8_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf8_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_PERF9_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf9_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_perf9_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf9_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_PERF10_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf10_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_perf10_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf10_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_PERF11_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf11_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_perf11_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf11_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_PERF12_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf12_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_perf12_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf12_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_PERF13_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf13_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_perf13_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf13_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_PERF14_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf14_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_perf14_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf14_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_PERF15_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf15_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_perf15_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_perf15_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_PERF0_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf0_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_perf0_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf0_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_PERF1_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf1_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_perf1_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf1_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_PERF2_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf2_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_perf2_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf2_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_PERF3_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf3_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_perf3_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf3_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_PERF4_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf4_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_perf4_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf4_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_PERF5_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf5_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_perf5_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf5_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_PERF6_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf6_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_perf6_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf6_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_PERF7_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf7_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_perf7_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf7_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_PERF8_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf8_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_perf8_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf8_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_PERF9_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf9_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_perf9_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf9_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_PERF10_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf10_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_perf10_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf10_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_PERF11_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf11_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_perf11_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf11_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_PERF12_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf12_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_perf12_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf12_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_PERF13_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf13_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_perf13_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf13_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_PERF14_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf14_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_perf14_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf14_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_PERF15_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf15_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_perf15_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_perf15_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_perf0_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_perf0_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_perf0_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_perf1_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_perf1_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_perf1_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_perf2_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_perf2_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_perf2_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_perf3_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_perf3_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_perf3_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_perf4_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_perf4_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_perf4_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_perf5_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_perf5_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_perf5_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_perf6_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_perf6_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_perf6_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_perf7_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_perf7_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_perf7_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_perf8_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_perf8_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_perf8_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_perf9_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_perf9_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_perf9_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_perf10_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_perf10_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_perf10_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_perf11_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_perf11_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_perf11_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_perf12_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_perf12_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_perf12_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_perf13_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_perf13_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_perf13_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_perf14_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_perf14_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_perf14_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_perf15_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_perf15_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_perf15_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_PERF0_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf0_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_perf0_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf0_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_PERF1_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf1_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_perf1_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf1_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_PERF2_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf2_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_perf2_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf2_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_PERF3_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf3_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_perf3_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf3_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_PERF4_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf4_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_perf4_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf4_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_PERF5_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf5_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_perf5_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf5_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_PERF6_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf6_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_perf6_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf6_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_PERF7_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf7_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_perf7_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf7_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_PERF8_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf8_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_perf8_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf8_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_PERF9_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf9_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_perf9_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf9_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_PERF10_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf10_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_perf10_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf10_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_PERF11_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf11_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_perf11_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf11_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_PERF12_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf12_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_perf12_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf12_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_PERF13_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf13_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_perf13_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf13_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_PERF14_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf14_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_perf14_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf14_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_PERF15_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf15_ena_vote_s +{ + u32 gcc_gpll0 : 1; + u32 gcc_gpll1 : 1; + u32 gcc_gpll2 : 1; + u32 gcc_gpll3 : 1; + u32 gcc_gpll4 : 1; + u32 gcc_gpll5 : 1; + u32 gcc_gpll6 : 1; + u32 gcc_gpll7 : 1; + u32 gcc_gpll8 : 1; + u32 gcc_gpll9 : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_perf15_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_perf15_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SYS_NOC_INTERFACE_FSM +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_interface_fsm_s +{ + u32 fsm_state : 5; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_sys_noc_interface_fsm_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_sys_noc_interface_fsm_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CNOC_INTERFACE_FSM +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_interface_fsm_s +{ + u32 fsm_state : 5; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cnoc_interface_fsm_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cnoc_interface_fsm_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_IPA_INTERFACE_FSM +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ipa_interface_fsm_s +{ + u32 fsm_state : 5; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ipa_interface_fsm_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ipa_interface_fsm_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_QUPV3_CORE_2X_INTERFACE_FSM +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_interface_fsm_s +{ + u32 fsm_state : 5; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_interface_fsm_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_qupv3_core_2x_interface_fsm_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CE_INTERFACE_FSM +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_ce_interface_fsm_s +{ + u32 fsm_state : 5; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_ce_interface_fsm_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_ce_interface_fsm_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_CDSP_NOC_INTERFACE_FSM +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_interface_fsm_s +{ + u32 fsm_state : 5; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_interface_fsm_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_cdsp_noc_interface_fsm_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_MMNOC_INTERFACE_FSM +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_interface_fsm_s +{ + u32 fsm_state : 5; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_mmnoc_interface_fsm_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_mmnoc_interface_fsm_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHUB_INTERFACE_FSM +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shub_interface_fsm_s +{ + u32 fsm_state : 5; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shub_interface_fsm_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shub_interface_fsm_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_SHRM_INTERFACE_FSM +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_shrm_interface_fsm_s +{ + u32 fsm_state : 5; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_shrm_interface_fsm_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_shrm_interface_fsm_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_PMU_INTERFACE_FSM +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_pmu_interface_fsm_s +{ + u32 fsm_state : 5; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_pmu_interface_fsm_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_pmu_interface_fsm_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GPU_MEMNOC_GFX_CLK_EN +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gpu_memnoc_gfx_clk_en_s +{ + u32 mux_select : 2; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gpu_memnoc_gfx_clk_en_u +{ + struct ipa_gcc_hwio_def_gcc_gpu_memnoc_gfx_clk_en_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MMU_MEMNOC_TCU_CLK_EN +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mmu_memnoc_tcu_clk_en_s +{ + u32 mux_select : 2; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mmu_memnoc_tcu_clk_en_u +{ + struct ipa_gcc_hwio_def_gcc_mmu_memnoc_tcu_clk_en_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MMU_GDSC_MISC +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mmu_gdsc_misc_s +{ + u32 ignore_pmu_pwr_collapse_req : 1; + u32 wait_for_lpass_qtb_pwr_collapse : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mmu_gdsc_misc_u +{ + struct ipa_gcc_hwio_def_gcc_mmu_gdsc_misc_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MEMNOC_TURING_CLK_EN +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_memnoc_turing_clk_en_s +{ + u32 mux_select : 2; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_memnoc_turing_clk_en_u +{ + struct ipa_gcc_hwio_def_gcc_memnoc_turing_clk_en_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MEMNOC_MSS_Q6_CLK_EN +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_memnoc_mss_q6_clk_en_s +{ + u32 mux_select : 2; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_memnoc_mss_q6_clk_en_u +{ + struct ipa_gcc_hwio_def_gcc_memnoc_mss_q6_clk_en_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MEMNOC_MSS_OFFLINE_CLK_EN +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_memnoc_mss_offline_clk_en_s +{ + u32 mux_select : 2; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_memnoc_mss_offline_clk_en_u +{ + struct ipa_gcc_hwio_def_gcc_memnoc_mss_offline_clk_en_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_LPASS_Q6SS_BOOT_GPLL0_MUXR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_lpass_q6ss_boot_gpll0_muxr_s +{ + u32 mux_sel : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_lpass_q6ss_boot_gpll0_muxr_u +{ + struct ipa_gcc_hwio_def_gcc_lpass_q6ss_boot_gpll0_muxr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_Q6SS_BOOT_GPLL0_MUXR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_q6ss_boot_gpll0_muxr_s +{ + u32 mux_sel : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_q6ss_boot_gpll0_muxr_u +{ + struct ipa_gcc_hwio_def_gcc_mss_q6ss_boot_gpll0_muxr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_ACA_FAL10_VETO_ENABLE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_aca_fal10_veto_enable_s +{ + u32 clk_on_veto_enable : 32; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_aca_fal10_veto_enable_u +{ + struct ipa_gcc_hwio_def_gcc_aca_fal10_veto_enable_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PLL_MISC +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pll_misc_s +{ + u32 hw_triggered_pll_stby_dis : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pll_misc_u +{ + struct ipa_gcc_hwio_def_gcc_pll_misc_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPMH_ALL_CLK_OFF +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpmh_all_clk_off_s +{ + u32 mux_sel : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpmh_all_clk_off_u +{ + struct ipa_gcc_hwio_def_gcc_rpmh_all_clk_off_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_GDSC_ALL_CLK_OFF +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_gdsc_all_clk_off_s +{ + u32 ufs_phy_gdscr_sw_power_down_complete : 1; + u32 ufs_mem_phy_gdscr_sw_power_down_complete : 1; + u32 pcie_1_phy_gdscr_sw_power_down_complete : 1; + u32 pcie_1_gdscr_sw_power_down_complete : 1; + u32 pcie_0_phy_gdscr_sw_power_down_complete : 1; + u32 pcie_0_gdscr_sw_power_down_complete : 1; + u32 turing_qtb_gdscr_sw_power_down_complete : 1; + u32 lpass_qtb_gdscr_sw_power_down_complete : 1; + u32 usb3_phy_gdscr_sw_power_down_complete : 1; + u32 usb30_prim_gdscr_sw_power_down_complete : 1; + u32 mmnoc_gdscr_sw_power_down_complete : 1; + u32 mmu_gdscr_sw_power_down_complete : 1; + u32 anoc_pcie_gdscr_sw_power_down_complete : 1; + u32 ipa_gdscr_sw_power_down_complete : 1; + u32 reserved0 : 18; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_gdsc_all_clk_off_u +{ + struct ipa_gcc_hwio_def_gcc_gdsc_all_clk_off_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_PLL_ALL_CLK_OFF +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_pll_all_clk_off_s +{ + u32 mux_sel : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_pll_all_clk_off_u +{ + struct ipa_gcc_hwio_def_gcc_pll_all_clk_off_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SP_GDSC_BRANCH_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sp_gdsc_branch_ena_vote_s +{ + u32 gcc_pcie_0_gdsc_sw_collapse : 1; + u32 gcc_pcie_1_gdsc_sw_collapse : 1; + u32 gcc_anoc_pcie_gdsc_sw_collapse : 1; + u32 gcc_pcie_0_phy_gdsc_sw_collapse : 1; + u32 gcc_pcie_1_phy_gdsc_sw_collapse : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sp_gdsc_branch_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_sp_gdsc_branch_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SP_GDSC_SLEEP_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_sp_gdsc_sleep_ena_vote_s +{ + u32 gcc_pcie_0_gdsc_sw_collapse : 1; + u32 gcc_pcie_1_gdsc_sw_collapse : 1; + u32 gcc_anoc_pcie_gdsc_sw_collapse : 1; + u32 gcc_pcie_0_phy_gdsc_sw_collapse : 1; + u32 gcc_pcie_1_phy_gdsc_sw_collapse : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_sp_gdsc_sleep_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_sp_gdsc_sleep_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPM_GDSC_BRANCH_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpm_gdsc_branch_ena_vote_s +{ + u32 gcc_pcie_0_gdsc_sw_collapse : 1; + u32 gcc_pcie_1_gdsc_sw_collapse : 1; + u32 gcc_anoc_pcie_gdsc_sw_collapse : 1; + u32 gcc_pcie_0_phy_gdsc_sw_collapse : 1; + u32 gcc_pcie_1_phy_gdsc_sw_collapse : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpm_gdsc_branch_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpm_gdsc_branch_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_RPM_GDSC_SLEEP_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_rpm_gdsc_sleep_ena_vote_s +{ + u32 gcc_pcie_0_gdsc_sw_collapse : 1; + u32 gcc_pcie_1_gdsc_sw_collapse : 1; + u32 gcc_anoc_pcie_gdsc_sw_collapse : 1; + u32 gcc_pcie_0_phy_gdsc_sw_collapse : 1; + u32 gcc_pcie_1_phy_gdsc_sw_collapse : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_rpm_gdsc_sleep_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_rpm_gdsc_sleep_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_APCS_GDSC_BRANCH_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_apcs_gdsc_branch_ena_vote_s +{ + u32 gcc_pcie_0_gdsc_sw_collapse : 1; + u32 gcc_pcie_1_gdsc_sw_collapse : 1; + u32 gcc_anoc_pcie_gdsc_sw_collapse : 1; + u32 gcc_pcie_0_phy_gdsc_sw_collapse : 1; + u32 gcc_pcie_1_phy_gdsc_sw_collapse : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_apcs_gdsc_branch_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_apcs_gdsc_branch_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_APCS_GDSC_SLEEP_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_apcs_gdsc_sleep_ena_vote_s +{ + u32 gcc_pcie_0_gdsc_sw_collapse : 1; + u32 gcc_pcie_1_gdsc_sw_collapse : 1; + u32 gcc_anoc_pcie_gdsc_sw_collapse : 1; + u32 gcc_pcie_0_phy_gdsc_sw_collapse : 1; + u32 gcc_pcie_1_phy_gdsc_sw_collapse : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_apcs_gdsc_sleep_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_apcs_gdsc_sleep_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_APCS_TZ_GDSC_BRANCH_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_apcs_tz_gdsc_branch_ena_vote_s +{ + u32 gcc_pcie_0_gdsc_sw_collapse : 1; + u32 gcc_pcie_1_gdsc_sw_collapse : 1; + u32 gcc_anoc_pcie_gdsc_sw_collapse : 1; + u32 gcc_pcie_0_phy_gdsc_sw_collapse : 1; + u32 gcc_pcie_1_phy_gdsc_sw_collapse : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_apcs_tz_gdsc_branch_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_apcs_tz_gdsc_branch_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_APCS_TZ_GDSC_SLEEP_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_apcs_tz_gdsc_sleep_ena_vote_s +{ + u32 gcc_pcie_0_gdsc_sw_collapse : 1; + u32 gcc_pcie_1_gdsc_sw_collapse : 1; + u32 gcc_anoc_pcie_gdsc_sw_collapse : 1; + u32 gcc_pcie_0_phy_gdsc_sw_collapse : 1; + u32 gcc_pcie_1_phy_gdsc_sw_collapse : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_apcs_tz_gdsc_sleep_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_apcs_tz_gdsc_sleep_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_LPASS_DSP_GDSC_BRANCH_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_lpass_dsp_gdsc_branch_ena_vote_s +{ + u32 gcc_pcie_0_gdsc_sw_collapse : 1; + u32 gcc_pcie_1_gdsc_sw_collapse : 1; + u32 gcc_anoc_pcie_gdsc_sw_collapse : 1; + u32 gcc_pcie_0_phy_gdsc_sw_collapse : 1; + u32 gcc_pcie_1_phy_gdsc_sw_collapse : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_lpass_dsp_gdsc_branch_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_lpass_dsp_gdsc_branch_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_LPASS_DSP_GDSC_SLEEP_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_lpass_dsp_gdsc_sleep_ena_vote_s +{ + u32 gcc_pcie_0_gdsc_sw_collapse : 1; + u32 gcc_pcie_1_gdsc_sw_collapse : 1; + u32 gcc_anoc_pcie_gdsc_sw_collapse : 1; + u32 gcc_pcie_0_phy_gdsc_sw_collapse : 1; + u32 gcc_pcie_1_phy_gdsc_sw_collapse : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_lpass_dsp_gdsc_sleep_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_lpass_dsp_gdsc_sleep_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TURING_DSP_GDSC_BRANCH_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_turing_dsp_gdsc_branch_ena_vote_s +{ + u32 gcc_pcie_0_gdsc_sw_collapse : 1; + u32 gcc_pcie_1_gdsc_sw_collapse : 1; + u32 gcc_anoc_pcie_gdsc_sw_collapse : 1; + u32 gcc_pcie_0_phy_gdsc_sw_collapse : 1; + u32 gcc_pcie_1_phy_gdsc_sw_collapse : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_turing_dsp_gdsc_branch_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_turing_dsp_gdsc_branch_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TURING_DSP_GDSC_SLEEP_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_turing_dsp_gdsc_sleep_ena_vote_s +{ + u32 gcc_pcie_0_gdsc_sw_collapse : 1; + u32 gcc_pcie_1_gdsc_sw_collapse : 1; + u32 gcc_anoc_pcie_gdsc_sw_collapse : 1; + u32 gcc_pcie_0_phy_gdsc_sw_collapse : 1; + u32 gcc_pcie_1_phy_gdsc_sw_collapse : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_turing_dsp_gdsc_sleep_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_turing_dsp_gdsc_sleep_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPARE_GDSC_BRANCH_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spare_gdsc_branch_ena_vote_s +{ + u32 gcc_pcie_0_gdsc_sw_collapse : 1; + u32 gcc_pcie_1_gdsc_sw_collapse : 1; + u32 gcc_anoc_pcie_gdsc_sw_collapse : 1; + u32 gcc_pcie_0_phy_gdsc_sw_collapse : 1; + u32 gcc_pcie_1_phy_gdsc_sw_collapse : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spare_gdsc_branch_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_spare_gdsc_branch_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPARE_GDSC_SLEEP_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spare_gdsc_sleep_ena_vote_s +{ + u32 gcc_pcie_0_gdsc_sw_collapse : 1; + u32 gcc_pcie_1_gdsc_sw_collapse : 1; + u32 gcc_anoc_pcie_gdsc_sw_collapse : 1; + u32 gcc_pcie_0_phy_gdsc_sw_collapse : 1; + u32 gcc_pcie_1_phy_gdsc_sw_collapse : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spare_gdsc_sleep_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_spare_gdsc_sleep_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_Q6_GDSC_BRANCH_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_q6_gdsc_branch_ena_vote_s +{ + u32 gcc_pcie_0_gdsc_sw_collapse : 1; + u32 gcc_pcie_1_gdsc_sw_collapse : 1; + u32 gcc_anoc_pcie_gdsc_sw_collapse : 1; + u32 gcc_pcie_0_phy_gdsc_sw_collapse : 1; + u32 gcc_pcie_1_phy_gdsc_sw_collapse : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_q6_gdsc_branch_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_mss_q6_gdsc_branch_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_MSS_Q6_GDSC_SLEEP_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_mss_q6_gdsc_sleep_ena_vote_s +{ + u32 gcc_pcie_0_gdsc_sw_collapse : 1; + u32 gcc_pcie_1_gdsc_sw_collapse : 1; + u32 gcc_anoc_pcie_gdsc_sw_collapse : 1; + u32 gcc_pcie_0_phy_gdsc_sw_collapse : 1; + u32 gcc_pcie_1_phy_gdsc_sw_collapse : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_mss_q6_gdsc_sleep_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_mss_q6_gdsc_sleep_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HYP_GDSC_BRANCH_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hyp_gdsc_branch_ena_vote_s +{ + u32 gcc_pcie_0_gdsc_sw_collapse : 1; + u32 gcc_pcie_1_gdsc_sw_collapse : 1; + u32 gcc_anoc_pcie_gdsc_sw_collapse : 1; + u32 gcc_pcie_0_phy_gdsc_sw_collapse : 1; + u32 gcc_pcie_1_phy_gdsc_sw_collapse : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hyp_gdsc_branch_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_hyp_gdsc_branch_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_HYP_GDSC_SLEEP_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_hyp_gdsc_sleep_ena_vote_s +{ + u32 gcc_pcie_0_gdsc_sw_collapse : 1; + u32 gcc_pcie_1_gdsc_sw_collapse : 1; + u32 gcc_anoc_pcie_gdsc_sw_collapse : 1; + u32 gcc_pcie_0_phy_gdsc_sw_collapse : 1; + u32 gcc_pcie_1_phy_gdsc_sw_collapse : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_hyp_gdsc_sleep_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_hyp_gdsc_sleep_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPARE1_GDSC_BRANCH_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spare1_gdsc_branch_ena_vote_s +{ + u32 gcc_pcie_0_gdsc_sw_collapse : 1; + u32 gcc_pcie_1_gdsc_sw_collapse : 1; + u32 gcc_anoc_pcie_gdsc_sw_collapse : 1; + u32 gcc_pcie_0_phy_gdsc_sw_collapse : 1; + u32 gcc_pcie_1_phy_gdsc_sw_collapse : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spare1_gdsc_branch_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_spare1_gdsc_branch_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_SPARE1_GDSC_SLEEP_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_spare1_gdsc_sleep_ena_vote_s +{ + u32 gcc_pcie_0_gdsc_sw_collapse : 1; + u32 gcc_pcie_1_gdsc_sw_collapse : 1; + u32 gcc_anoc_pcie_gdsc_sw_collapse : 1; + u32 gcc_pcie_0_phy_gdsc_sw_collapse : 1; + u32 gcc_pcie_1_phy_gdsc_sw_collapse : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_spare1_gdsc_sleep_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_spare1_gdsc_sleep_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TME_GDSC_BRANCH_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tme_gdsc_branch_ena_vote_s +{ + u32 gcc_pcie_0_gdsc_sw_collapse : 1; + u32 gcc_pcie_1_gdsc_sw_collapse : 1; + u32 gcc_anoc_pcie_gdsc_sw_collapse : 1; + u32 gcc_pcie_0_phy_gdsc_sw_collapse : 1; + u32 gcc_pcie_1_phy_gdsc_sw_collapse : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tme_gdsc_branch_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_tme_gdsc_branch_ena_vote_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: GCC_TME_GDSC_SLEEP_ENA_VOTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_gcc_hwio_def_gcc_tme_gdsc_sleep_ena_vote_s +{ + u32 gcc_pcie_0_gdsc_sw_collapse : 1; + u32 gcc_pcie_1_gdsc_sw_collapse : 1; + u32 gcc_anoc_pcie_gdsc_sw_collapse : 1; + u32 gcc_pcie_0_phy_gdsc_sw_collapse : 1; + u32 gcc_pcie_1_phy_gdsc_sw_collapse : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_gcc_hwio_def_gcc_tme_gdsc_sleep_ena_vote_u +{ + struct ipa_gcc_hwio_def_gcc_tme_gdsc_sleep_ena_vote_s def; + u32 value; +}; + + +#endif /* __IPA_GCC_HWIO_DEF_H__ */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.5/ipa_hw_common_ex.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.5/ipa_hw_common_ex.h new file mode 100644 index 0000000000..896bbf5e63 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.5/ipa_hw_common_ex.h @@ -0,0 +1,653 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ +#if !defined(_IPA_HW_COMMON_EX_H_) +#define _IPA_HW_COMMON_EX_H_ + +/* VLVL defs are available for 854 */ +#define FEATURE_VLVL_DEFS true + +/* Important Platform Specific Values : IRQ_NUM, IRQ_CNT, BCR */ +#define IPA_HW_BAM_IRQ_NUM 639 + +/* Q6 IRQ number for IPA. */ +#define IPA_HW_IRQ_NUM 640 + +/* Total number of different interrupts that can be enabled */ +#define IPA_HW_IRQ_CNT_TOTAL 23 + +/* IPAv4 spare reg value */ +#define IPA_HW_SPARE_1_REG_VAL 0xC0000005 + +/* Whether to allow setting step mode on IPA when we crash or not */ +#define IPA_CFG_HW_IS_STEP_MODE_ALLOWED (false) + +/* GSI MHI related definitions */ +#define IPA_HW_GSI_MHI_CONSUMER_CHANNEL_NUM 0x0 +#define IPA_HW_GSI_MHI_PRODUCER_CHANNEL_NUM 0x1 + +#define IPA_HW_GSI_MHI_CONSUMER_EP_NUM 0x1 +#define IPA_HW_GSI_MHI_PRODUCER_EP_NUM 0x11 + +/* IPA ZIP WA related Macros */ +#define IPA_HW_DCMP_SRC_PIPE 0x8 +#define IPA_HW_DCMP_DEST_PIPE 0x4 +#define IPA_HW_ACK_MNGR_MASK 0x1D +#define IPA_HW_DCMP_SRC_GRP 0x5 + +/* IPA Clock resource name */ +#define IPA_CLK_RESOURCE_NAME "/clk/pcnoc" + +/* IPA Clock Bus Client name */ +#define IPA_CLK_BUS_CLIENT_NAME "IPA_PCNOC_BUS_CLIENT" + +/* HPS Sequences */ +#define IPA_HW_PKT_PROCESS_HPS_DMA 0x0 +#define IPA_HW_PKT_PROCESS_HPS_DMA_DECIPH_CIPHE 0x1 +#define IPA_HW_PKT_PROCESS_HPS_PKT_PRS_NO_DECIPH_UCP 0x2 +#define IPA_HW_PKT_PROCESS_HPS_PKT_PRS_DECIPH_UCP 0x3 +#define IPA_HW_PKT_PROCESS_HPS_2_PKT_PRS_NO_DECIPH 0x4 +#define IPA_HW_PKT_PROCESS_HPS_2_PKT_PRS_DECIPH 0x5 +#define IPA_HW_PKT_PROCESS_HPS_PKT_PRS_NO_DECIPH_NO_UCP 0x6 +#define IPA_HW_PKT_PROCESS_HPS_PKT_PRS_DECIPH_NO_UCP 0x7 +#define IPA_HW_PKT_PROCESS_HPS_DMA_PARSER 0x8 +#define IPA_HW_PKT_PROCESS_HPS_DMA_DECIPH_PARSER 0x9 +#define IPA_HW_PKT_PROCESS_HPS_2_PKT_PRS_UCP_TWICE_NO_DECIPH 0xA +#define IPA_HW_PKT_PROCESS_HPS_2_PKT_PRS_UCP_TWICE_DECIPH 0xB +#define IPA_HW_PKT_PROCESS_HPS_3_PKT_PRS_UCP_TWICE_NO_DECIPH 0xC +#define IPA_HW_PKT_PROCESS_HPS_3_PKT_PRS_UCP_TWICE_DECIPH 0xD + +/* DPS Sequences */ +#define IPA_HW_PKT_PROCESS_DPS_DMA 0x0 +#define IPA_HW_PKT_PROCESS_DPS_DMA_WITH_DECIPH 0x1 +#define IPA_HW_PKT_PROCESS_DPS_DMA_WITH_DECOMP 0x2 +#define IPA_HW_PKT_PROCESS_DPS_DMA_WITH_CIPH 0x3 + +/* Src RSRC GRP config */ +#define IPA_HW_SRC_RSRC_GRP_01_RSRC_TYPE_0 0x0B040803 +#define IPA_HW_SRC_RSRC_GRP_01_RSRC_TYPE_1 0x0C0C0909 +#define IPA_HW_SRC_RSRC_GRP_01_RSRC_TYPE_2 0x0E0E0909 +#define IPA_HW_SRC_RSRC_GRP_01_RSRC_TYPE_3 0x3F003F00 +#define IPA_HW_SRC_RSRC_GRP_01_RSRC_TYPE_4 0x10101616 + +#define IPA_HW_SRC_RSRC_GRP_23_RSRC_TYPE_0 0x01010101 +#define IPA_HW_SRC_RSRC_GRP_23_RSRC_TYPE_1 0x02020202 +#define IPA_HW_SRC_RSRC_GRP_23_RSRC_TYPE_2 0x04040404 +#define IPA_HW_SRC_RSRC_GRP_23_RSRC_TYPE_3 0x3F003F00 +#define IPA_HW_SRC_RSRC_GRP_23_RSRC_TYPE_4 0x02020606 + +#define IPA_HW_SRC_RSRC_GRP_45_RSRC_TYPE_0 0x00000000 +#define IPA_HW_SRC_RSRC_GRP_45_RSRC_TYPE_1 0x00000000 +#define IPA_HW_SRC_RSRC_GRP_45_RSRC_TYPE_2 0x00000000 +#define IPA_HW_SRC_RSRC_GRP_45_RSRC_TYPE_3 0x00003F00 +#define IPA_HW_SRC_RSRC_GRP_45_RSRC_TYPE_4 0x00000000 + +/* Dest RSRC GRP config */ +#define IPA_HW_DST_RSRC_GRP_01_RSRC_TYPE_0 0x05051010 +#define IPA_HW_DST_RSRC_GRP_01_RSRC_TYPE_1 0x3F013F02 + +#define IPA_HW_DST_RSRC_GRP_23_RSRC_TYPE_0 0x02020202 +#define IPA_HW_DST_RSRC_GRP_23_RSRC_TYPE_1 0x02010201 + +#define IPA_HW_DST_RSRC_GRP_45_RSRC_TYPE_0 0x00000000 +#define IPA_HW_DST_RSRC_GRP_45_RSRC_TYPE_1 0x00000200 + +#define IPA_HW_RX_HPS_CLIENTS_MIN_DEPTH_0 0x03030303 +#define IPA_HW_RX_HPS_CLIENTS_MAX_DEPTH_0 0x03030303 + +#define IPA_HW_RSRP_GRP_0 0x0 +#define IPA_HW_RSRP_GRP_1 0x1 +#define IPA_HW_RSRP_GRP_2 0x2 +#define IPA_HW_RSRP_GRP_3 0x3 + +#define IPA_HW_PCIE_SRC_RSRP_GRP IPA_HW_RSRP_GRP_0 +#define IPA_HW_PCIE_DEST_RSRP_GRP IPA_HW_RSRP_GRP_0 + +#define IPA_HW_DDR_SRC_RSRP_GRP IPA_HW_RSRP_GRP_1 +#define IPA_HW_DDR_DEST_RSRP_GRP IPA_HW_RSRP_GRP_1 + +#define IPA_HW_DMA_SRC_RSRP_GRP IPA_HW_RSRP_GRP_2 +#define IPA_HW_DMA_DEST_RSRP_GRP IPA_HW_RSRP_GRP_2 + +#define IPA_HW_SRC_RSRP_TYPE_MAX 0x05 +#define IPA_HW_DST_RSRP_TYPE_MAX 0x03 + +#define GSI_HW_QSB_LOG_MISC_MAX 0x4 + +/* IPA Clock Bus Client name */ +#define IPA_CLK_BUS_CLIENT_NAME "IPA_PCNOC_BUS_CLIENT" + +/* Is IPA decompression feature enabled */ +#define IPA_HW_IS_DECOMPRESSION_ENABLED (1) + +/* Whether to allow setting step mode on IPA when we crash or not */ +#define IPA_HW_IS_STEP_MODE_ALLOWED (true) + +/* Max number of virtual pipes for UL QBAP provided by HW */ +#define IPA_HW_MAX_VP_NUM (32) + +/* + * HW specific clock vote freq values in KHz + * (BIMC/SNOC/PCNOC/IPA/Q6 CPU) + */ +enum ipa_hw_clk_freq_e { + /* BIMC */ + IPA_HW_CLK_FREQ_BIMC_PEAK = 518400, + IPA_HW_CLK_FREQ_BIMC_NOM_PLUS = 404200, + IPA_HW_CLK_FREQ_BIMC_NOM = 404200, + IPA_HW_CLK_FREQ_BIMC_SVS = 100000, + + /* PCNOC */ + IPA_HW_CLK_FREQ_PCNOC_PEAK = 133330, + IPA_HW_CLK_FREQ_PCNOC_NOM_PLUS = 100000, + IPA_HW_CLK_FREQ_PCNOC_NOM = 100000, + IPA_HW_CLK_FREQ_PCNOC_SVS = 50000, + + /*IPA_HW_CLK_SNOC*/ + IPA_HW_CLK_FREQ_SNOC_PEAK = 200000, + IPA_HW_CLK_FREQ_SNOC_NOM_PLUS = 150000, + IPA_HW_CLK_FREQ_SNOC_NOM = 150000, + IPA_HW_CLK_FREQ_SNOC_SVS = 85000, + IPA_HW_CLK_FREQ_SNOC_SVS_2 = 50000, + + /* IPA */ + IPA_HW_CLK_FREQ_IPA_PEAK = 600000, + IPA_HW_CLK_FREQ_IPA_NOM_PLUS = 500000, + IPA_HW_CLK_FREQ_IPA_NOM = 500000, + IPA_HW_CLK_FREQ_IPA_SVS = 250000, + IPA_HW_CLK_FREQ_IPA_SVS_2 = 150000, + + /* Q6 CPU */ + IPA_HW_CLK_FREQ_Q6_PEAK = 729600, + IPA_HW_CLK_FREQ_Q6_NOM_PLUS = 729600, + IPA_HW_CLK_FREQ_Q6_NOM = 729600, + IPA_HW_CLK_FREQ_Q6_SVS = 729600, +}; + +enum ipa_hw_qtimer_gran_e { + IPA_HW_QTIMER_GRAN_0 = 0, /* granularity 0 is 10us */ + IPA_HW_QTIMER_GRAN_1 = 1, /* granularity 1 is 100us */ + IPA_HW_QTIMER_GRAN_MAX, +}; + +/* Pipe ID of all the IPA pipes */ +enum ipa_hw_pipe_id_e { + IPA_HW_PIPE_ID_0, + IPA_HW_PIPE_ID_1, + IPA_HW_PIPE_ID_2, + IPA_HW_PIPE_ID_3, + IPA_HW_PIPE_ID_4, + IPA_HW_PIPE_ID_5, + IPA_HW_PIPE_ID_6, + IPA_HW_PIPE_ID_7, + IPA_HW_PIPE_ID_8, + IPA_HW_PIPE_ID_9, + IPA_HW_PIPE_ID_10, + IPA_HW_PIPE_ID_11, + IPA_HW_PIPE_ID_12, + IPA_HW_PIPE_ID_13, + IPA_HW_PIPE_ID_14, + IPA_HW_PIPE_ID_15, + IPA_HW_PIPE_ID_16, + IPA_HW_PIPE_ID_17, + IPA_HW_PIPE_ID_18, + IPA_HW_PIPE_ID_19, + IPA_HW_PIPE_ID_20, + IPA_HW_PIPE_ID_21, + IPA_HW_PIPE_ID_22, + IPA_HW_PIPE_ID_23, + IPA_HW_PIPE_ID_24, + IPA_HW_PIPE_ID_25, + IPA_HW_PIPE_ID_26, + IPA_HW_PIPE_ID_27, + IPA_HW_PIPE_ID_28, + IPA_HW_PIPE_ID_29, + IPA_HW_PIPE_ID_30, + IPA_HW_PIPE_ID_31, + IPA_HW_PIPE_ID_32, + IPA_HW_PIPE_ID_33, + IPA_HW_PIPE_ID_34, + IPA_HW_PIPE_ID_35, + IPA_HW_PIPE_ID_MAX +}; + +/* Pipe ID's of System Bam Endpoints between Q6 & IPA */ +enum ipa_hw_q6_pipe_id_e { + /* Pipes used by IPA Q6 driver */ + IPA_HW_Q6_DL_CONSUMER_PIPE_ID = IPA_HW_PIPE_ID_5, + IPA_HW_Q6_CTL_CONSUMER_PIPE_ID = IPA_HW_PIPE_ID_6, + IPA_HW_Q6_DL_NLO_CONSUMER_PIPE_ID = IPA_HW_PIPE_ID_8, + + IPA_HW_Q6_UL_ACC_ACK_PRODUCER_PIPE_ID = IPA_HW_PIPE_ID_20, + IPA_HW_Q6_UL_PRODUCER_PIPE_ID = IPA_HW_PIPE_ID_21, + IPA_HW_Q6_DL_PRODUCER_PIPE_ID = IPA_HW_PIPE_ID_17, + IPA_HW_Q6_QBAP_STATUS_PRODUCER_PIPE_ID = IPA_HW_PIPE_ID_18, + IPA_HW_Q6_UL_ACC_DATA_PRODUCER_PIPE_ID = IPA_HW_PIPE_ID_19, + + IPA_HW_Q6_UL_ACK_PRODUCER_PIPE_ID = + IPA_HW_Q6_UL_ACC_ACK_PRODUCER_PIPE_ID, + IPA_HW_Q6_UL_DATA_PRODUCER_PIPE_ID = + IPA_HW_Q6_UL_ACC_DATA_PRODUCER_PIPE_ID, + + IPA_HW_Q6_DMA_ASYNC_CONSUMER_PIPE_ID = IPA_HW_PIPE_ID_4, + IPA_HW_Q6_DMA_ASYNC_PRODUCER_PIPE_ID = IPA_HW_PIPE_ID_29, + + /* Test Simulator Pipes */ + IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_0_ID = IPA_HW_PIPE_ID_0, + IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_1_ID = IPA_HW_PIPE_ID_1, + + /* GSI UT channel SW->IPA */ + IPA_HW_Q6_GSI_UT_CONSUMER_PIPE_1_ID = IPA_HW_PIPE_ID_3, + /* GSI UT channel SW->IPA */ + IPA_HW_Q6_GSI_UT_CONSUMER_PIPE_2_ID = IPA_HW_PIPE_ID_10, + + IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_2_ID = IPA_HW_PIPE_ID_7, + + /* GSI UT channel IPA->SW */ + IPA_HW_Q6_DIAG_CONSUMER_PIPE_ID = IPA_HW_PIPE_ID_9, + + IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_0_ID = IPA_HW_PIPE_ID_23, + IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_1_ID = IPA_HW_PIPE_ID_24, + + IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_2_ID = IPA_HW_PIPE_ID_25, + + /* GSI UT channel IPA->SW */ + IPA_HW_Q6_GSI_UT_PRODUCER_PIPE_1_ID = IPA_HW_PIPE_ID_26, + + /* GSI UT channel IPA->SW */ + IPA_HW_Q6_GSI_UT_PRODUCER_PIPE_2_ID = IPA_HW_PIPE_ID_27, + IPA_HW_Q6_PIPE_ID_MAX = IPA_HW_PIPE_ID_MAX, +}; + +enum ipa_hw_q6_pipe_ch_id_e { + /* Channels used by IPA Q6 driver */ + IPA_HW_Q6_DL_CONSUMER_PIPE_CH_ID = 0, + IPA_HW_Q6_CTL_CONSUMER_PIPE_CH_ID = 1, + IPA_HW_Q6_DL_NLO_CONSUMER_PIPE_CH_ID = 2, + IPA_HW_Q6_UL_ACC_PATH_ACK_PRODUCER_PIPE_CH_ID = 6, + IPA_HW_Q6_UL_PRODUCER_PIPE_CH_ID = 7, + IPA_HW_Q6_DL_PRODUCER_PIPE_CH_ID = 3, + IPA_HW_Q6_UL_ACC_PATH_DATA_PRODUCER_PIPE_CH_ID = 5, + IPA_HW_Q6_QBAP_STATUS_PRODUCER_PIPE_CH_ID = 4, + + IPA_HW_Q6_DMA_ASYNC_CONSUMER_PIPE_CH_ID = 8, + IPA_HW_Q6_DMA_ASYNC_PRODUCER_PIPE_CH_ID = 9, + /* CH_ID 8 and 9 are Q6 SPARE CONSUMERs */ + + /* Test Simulator Channels */ + IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_0_CH_ID = 10, + IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_0_CH_ID = 11, + IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_1_CH_ID = 12, + IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_1_CH_ID = 13, + IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_2_CH_ID = 14, + IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_2_CH_ID = 15, + /* GSI UT channel SW->IPA */ + IPA_HW_Q6_GSI_UT_CONSUMER_PIPE_1_CH_ID = 16, + /* GSI UT channel IPA->SW */ + IPA_HW_Q6_GSI_UT_PRODUCER_PIPE_1_CH_ID = 17, + /* GSI UT channel SW->IPA */ + IPA_HW_Q6_GSI_UT_CONSUMER_PIPE_2_CH_ID = 18, + /* GSI UT channel IPA->SW */ + IPA_HW_Q6_GSI_UT_PRODUCER_PIPE_2_CH_ID = 19, +}; + +/* System Bam Endpoints between Q6 & IPA */ +enum ipa_hw_q6_pipe_e { + /* DL Pipe IPA->Q6 */ + IPA_HW_Q6_DL_PRODUCER_PIPE = 0, + /* UL Pipe IPA->Q6 */ + IPA_HW_Q6_UL_PRODUCER_PIPE = 1, + /* DL Pipe Q6->IPA */ + IPA_HW_Q6_DL_CONSUMER_PIPE = 2, + /* CTL Pipe Q6->IPA */ + IPA_HW_Q6_CTL_CONSUMER_PIPE = 3, + /* Q6 -> IPA, DL NLO */ + IPA_HW_Q6_DL_NLO_CONSUMER_PIPE = 4, + /* DMA ASYNC CONSUMER */ + IPA_HW_Q6_DMA_ASYNC_CONSUMER_PIPE = 5, + /* DMA ASYNC PRODUCER */ + IPA_HW_Q6_DMA_ASYNC_PRODUCER_PIPE = 6, + /* UL Acc Path Data Pipe IPA->Q6 */ + IPA_HW_Q6_UL_ACC_DATA_PRODUCER_PIPE = 7, + /* UL Acc Path ACK Pipe IPA->Q6 */ + IPA_HW_Q6_UL_ACC_ACK_PRODUCER_PIPE = 8, + /* UL Acc Path QBAP status Pipe IPA->Q6 */ + IPA_HW_Q6_QBAP_STATUS_PRODUCER_PIPE = 9, + /* Diag status pipe IPA->Q6 */ + /* Used only when FEATURE_IPA_TEST_PER_SIM is ON */ + /* SIM Pipe IPA->Sim */ + IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_0 = 10, + /* SIM Pipe Sim->IPA */ + IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_1 = 11, + /* SIM Pipe Sim->IPA */ + IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_2 = 12, + /* SIM Pipe Sim->IPA */ + IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_0 = 13, + /* SIM B2B PROD Pipe */ + IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_1 = 14, + /* SIM Pipe IPA->Sim */ + IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_2 = 15, + /* End FEATURE_IPA_TEST_PER_SIM */ + /* GSI UT channel SW->IPA */ + IPA_HW_Q6_GSI_UT_CONSUMER_PIPE_1 = 16, + /* GSI UT channel IPA->SW */ + IPA_HW_Q6_GSI_UT_PRODUCER_PIPE_1 = 17, + /* GSI UT channel SW->IPA */ + IPA_HW_Q6_GSI_UT_CONSUMER_PIPE_2 = 18, + /* GSI UT channel IPA->SW */ + IPA_HW_Q6_GSI_UT_PRODUCER_PIPE_2 = 19, + + IPA_HW_Q6_PIPE_TOTAL +}; + +/* System Bam Endpoints between Q6 & IPA */ +enum ipa_hw_q6_gsi_ev_e { /* In Sdx24 0..11 */ + /* DL Pipe IPA->Q6 */ + IPA_HW_Q6_DL_PRODUCER_PIPE_GSI_EV = 0, + /* UL Pipe IPA->Q6 */ + IPA_HW_Q6_UL_PRODUCER_PIPE_GSI_EV = 1, + /* DL Pipe Q6->IPA */ + //IPA_HW_Q6_DL_CONSUMER_PIPE_GSI_EV = 2, + /* CTL Pipe Q6->IPA */ + //IPA_HW_Q6_CTL_CONSUMER_PIPE_GSI_EV = 3, + /* Q6 -> IPA, LTE DL Optimized path */ + //IPA_HW_Q6_LTE_DL_CONSUMER_PIPE_GSI_EV = 4, + /* LWA DL(Wifi to Q6) */ + //IPA_HW_Q6_LWA_DL_PRODUCER_PIPE_GSI_EV = 5, + /* Diag status pipe IPA->Q6 */ + //IPA_HW_Q6_DIAG_STATUS_PRODUCER_PIPE_GSI_EV = 6, + /* Used only when FEATURE_IPA_TEST_PER_SIM is ON */ + /* SIM Pipe IPA->Sim */ + IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_0_GSI_EV = 2, + /* SIM Pipe Sim->IPA */ + IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_1_GSI_EV = 3, + /* SIM Pipe Sim->IPA */ + IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_2_GSI_EV = 4, + /* SIM Pipe Sim->IPA */ + IPA_HW_Q6_SIM_1_GSI_EV = 5, + IPA_HW_Q6_SIM_2_GSI_EV = 6, + IPA_HW_Q6_SIM_3_GSI_EV = 7, + IPA_HW_Q6_SIM_4_GSI_EV = 8, + + IPA_HW_Q6_PIPE_GSI_EV_TOTAL +}; + +/* + * All the IRQ's supported by the IPA HW. Use this enum to set IRQ_EN + * register and read IRQ_STTS register + */ +enum ipa_hw_irq_e { + IPA_HW_IRQ_GSI_HWP = (1 << 25), + IPA_HW_IRQ_GSI_IPA_IF_TLV_RCVD = (1 << 24), + IPA_HW_IRQ_GSI_EE_IRQ = (1 << 23), + IPA_HW_IRQ_DCMP_ERR = (1 << 22), + IPA_HW_IRQ_HWP_ERR = (1 << 21), + IPA_HW_IRQ_RED_MARKER_ABOVE = (1 << 20), + IPA_HW_IRQ_YELLOW_MARKER_ABOVE = (1 << 19), + IPA_HW_IRQ_RED_MARKER_BELOW = (1 << 18), + IPA_HW_IRQ_YELLOW_MARKER_BELOW = (1 << 17), + IPA_HW_IRQ_BAM_IDLE_IRQ = (1 << 16), + IPA_HW_IRQ_TX_HOLB_DROP = (1 << 15), + IPA_HW_IRQ_TX_SUSPEND = (1 << 14), + IPA_HW_IRQ_PROC_ERR = (1 << 13), + IPA_HW_IRQ_STEP_MODE = (1 << 12), + IPA_HW_IRQ_TX_ERR = (1 << 11), + IPA_HW_IRQ_DEAGGR_ERR = (1 << 10), + IPA_HW_IRQ_RX_ERR = (1 << 9), + IPA_HW_IRQ_PROC_TO_HW_ACK_Q_NOT_EMPTY = (1 << 8), + IPA_HW_IRQ_HWP_RX_CMD_Q_NOT_FULL = (1 << 7), + IPA_HW_IRQ_HWP_IN_Q_NOT_EMPTY = (1 << 6), + IPA_HW_IRQ_HWP_IRQ_3 = (1 << 5), + IPA_HW_IRQ_HWP_IRQ_2 = (1 << 4), + IPA_HW_IRQ_HWP_IRQ_1 = (1 << 3), + IPA_HW_IRQ_HWP_IRQ_0 = (1 << 2), + IPA_HW_IRQ_EOT_COAL = (1 << 1), + IPA_HW_IRQ_BAD_SNOC_ACCESS = (1 << 0), + IPA_HW_IRQ_NONE = 0, + IPA_HW_IRQ_ALL = 0xFFFFFFFF +}; + +/* + * All the IRQ sources supported by the IPA HW. Use this enum to set + * IRQ_SRCS register + */ +enum ipa_hw_irq_srcs_e { + IPA_HW_IRQ_SRCS_PIPE_0 = (1 << IPA_HW_PIPE_ID_0), + IPA_HW_IRQ_SRCS_PIPE_1 = (1 << IPA_HW_PIPE_ID_1), + IPA_HW_IRQ_SRCS_PIPE_2 = (1 << IPA_HW_PIPE_ID_2), + IPA_HW_IRQ_SRCS_PIPE_3 = (1 << IPA_HW_PIPE_ID_3), + IPA_HW_IRQ_SRCS_PIPE_4 = (1 << IPA_HW_PIPE_ID_4), + IPA_HW_IRQ_SRCS_PIPE_5 = (1 << IPA_HW_PIPE_ID_5), + IPA_HW_IRQ_SRCS_PIPE_6 = (1 << IPA_HW_PIPE_ID_6), + IPA_HW_IRQ_SRCS_PIPE_7 = (1 << IPA_HW_PIPE_ID_7), + IPA_HW_IRQ_SRCS_PIPE_8 = (1 << IPA_HW_PIPE_ID_8), + IPA_HW_IRQ_SRCS_PIPE_9 = (1 << IPA_HW_PIPE_ID_9), + IPA_HW_IRQ_SRCS_PIPE_10 = (1 << IPA_HW_PIPE_ID_10), + IPA_HW_IRQ_SRCS_PIPE_11 = (1 << IPA_HW_PIPE_ID_11), + IPA_HW_IRQ_SRCS_PIPE_12 = (1 << IPA_HW_PIPE_ID_12), + IPA_HW_IRQ_SRCS_PIPE_13 = (1 << IPA_HW_PIPE_ID_13), + IPA_HW_IRQ_SRCS_PIPE_14 = (1 << IPA_HW_PIPE_ID_14), + IPA_HW_IRQ_SRCS_PIPE_15 = (1 << IPA_HW_PIPE_ID_15), + IPA_HW_IRQ_SRCS_PIPE_16 = (1 << IPA_HW_PIPE_ID_16), + IPA_HW_IRQ_SRCS_PIPE_17 = (1 << IPA_HW_PIPE_ID_17), + IPA_HW_IRQ_SRCS_PIPE_18 = (1 << IPA_HW_PIPE_ID_18), + IPA_HW_IRQ_SRCS_PIPE_19 = (1 << IPA_HW_PIPE_ID_19), + IPA_HW_IRQ_SRCS_PIPE_20 = (1 << IPA_HW_PIPE_ID_20), + IPA_HW_IRQ_SRCS_PIPE_21 = (1 << IPA_HW_PIPE_ID_21), + IPA_HW_IRQ_SRCS_PIPE_22 = (1 << IPA_HW_PIPE_ID_22), + IPA_HW_IRQ_SRCS_NONE = 0, + IPA_HW_IRQ_SRCS_ALL = 0xFFFFFFFF, +}; + +/* + * Total number of channel contexts that need to be saved for APPS + */ +#define IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_A7 30 + +/* + * Total number of channel contexts that need to be saved for UC + */ +#define IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_UC 7 + + /* + * Total number of channel contexts that need to be saved for Q6 + */ +#define IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_Q6 11 + +/* + * Total number of event ring contexts that need to be saved for APPS + */ +#define IPA_HW_REG_SAVE_GSI_NUM_EVT_CNTXT_A7 30 + +/* + * Total number of event ring contexts that need to be saved for UC + */ +#define IPA_HW_REG_SAVE_GSI_NUM_EVT_CNTXT_UC 7 + +/* + * Total number of event ring contexts that need to be saved for Q6 + */ +#define IPA_HW_REG_SAVE_GSI_NUM_EVT_CNTXT_Q6 11 + +/* + * Total number of endpoints for which ipa_reg_save.pipes[endp_number] + * are not saved by default (only if ipa_cfg.gen.full_reg_trace = + * true) There is no extra endpoints in Stingray + */ +#define IPA_HW_REG_SAVE_NUM_ENDP_EXTRA 0 + +/* + * Total number of endpoints for which ipa_reg_save.pipes[endp_number] + * are always saved + */ +#define IPA_HW_REG_SAVE_NUM_ACTIVE_PIPES IPA_HW_PIPE_ID_MAX + +/* + * SHRAM Bytes per ch + */ +#define IPA_REG_SAVE_BYTES_PER_CHNL_SHRAM 20 + +/* + * Total number of rx splt cmdq's see: + * ipa_rx_splt_cmdq_n_cmd[IPA_RX_SPLT_CMDQ_MAX] + */ +#define IPA_RX_SPLT_CMDQ_MAX 4 + +/* + * Although not necessary for the numbers below, the use of round_up + * is so that future developers know that these particular constants + * have to be a multiple of four bytes, because the IPA memory reads + * that they drive are always 32 bits... + */ +#define IPA_IU_ADDR 0x001A0000 +#define IPA_IU_SIZE round_up(40704, sizeof(u32)) + +#define IPA_SRAM_ADDR 0x00150000 +#define IPA_SRAM_SIZE round_up(19232, sizeof(u32)) + +#define IPA_MBOX_ADDR 0x001C2000 +#define IPA_MBOX_SIZE round_up(256, sizeof(u32)) + +#define IPA_HRAM_ADDR 0x00160000 +#define IPA_HRAM_SIZE round_up(47536, sizeof(u32)) + +#define IPA_SEQ_ADDR 0x00181000 +#define IPA_SEQ_SIZE round_up(768, sizeof(u32)) + +#define IPA_GSI_ADDR 0x00006000 +#define IPA_GSI_SIZE round_up(5376, sizeof(u32)) + +/* + * Macro to define a particular register cfg entry for all pipe + * indexed register + */ +#define IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(reg_name, var_name) \ + { GEN_1xVECTOR_REG_OFST(reg_name, 0), \ + (u32 *)&ipa_reg_save.ipa.pipes[0].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 1), \ + (u32 *)&ipa_reg_save.ipa.pipes[1].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 2), \ + (u32 *)&ipa_reg_save.ipa.pipes[2].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 3), \ + (u32 *)&ipa_reg_save.ipa.pipes[3].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 4), \ + (u32 *)&ipa_reg_save.ipa.pipes[4].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 5), \ + (u32 *)&ipa_reg_save.ipa.pipes[5].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 6), \ + (u32 *)&ipa_reg_save.ipa.pipes[6].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 7), \ + (u32 *)&ipa_reg_save.ipa.pipes[7].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 8), \ + (u32 *)&ipa_reg_save.ipa.pipes[8].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 9), \ + (u32 *)&ipa_reg_save.ipa.pipes[9].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 10), \ + (u32 *)&ipa_reg_save.ipa.pipes[10].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 11), \ + (u32 *)&ipa_reg_save.ipa.pipes[11].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 12), \ + (u32 *)&ipa_reg_save.ipa.pipes[12].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 13), \ + (u32 *)&ipa_reg_save.ipa.pipes[13].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 14), \ + (u32 *)&ipa_reg_save.ipa.pipes[14].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 15), \ + (u32 *)&ipa_reg_save.ipa.pipes[15].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 16), \ + (u32 *)&ipa_reg_save.ipa.pipes[16].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 17), \ + (u32 *)&ipa_reg_save.ipa.pipes[17].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 18), \ + (u32 *)&ipa_reg_save.ipa.pipes[18].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 19), \ + (u32 *)&ipa_reg_save.ipa.pipes[19].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 20), \ + (u32 *)&ipa_reg_save.ipa.pipes[20].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 21), \ + (u32 *)&ipa_reg_save.ipa.pipes[21].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 22), \ + (u32 *)&ipa_reg_save.ipa.pipes[22].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 23), \ + (u32 *)&ipa_reg_save.ipa.pipes[23].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 24), \ + (u32 *)&ipa_reg_save.ipa.pipes[24].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 25), \ + (u32 *)&ipa_reg_save.ipa.pipes[25].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 26), \ + (u32 *)&ipa_reg_save.ipa.pipes[26].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 27), \ + (u32 *)&ipa_reg_save.ipa.pipes[27].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 28), \ + (u32 *)&ipa_reg_save.ipa.pipes[28].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 29), \ + (u32 *)&ipa_reg_save.ipa.pipes[29].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 30), \ + (u32 *)&ipa_reg_save.ipa.pipes[30].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 31), \ + (u32 *)&ipa_reg_save.ipa.pipes[31].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 32), \ + (u32 *)&ipa_reg_save.ipa.pipes[32].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 33), \ + (u32 *)&ipa_reg_save.ipa.pipes[33].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 34), \ + (u32 *)&ipa_reg_save.ipa.pipes[34].endp.var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 35), \ + (u32 *)&ipa_reg_save.ipa.pipes[35].endp.var_name, \ + GEN_REG_ATTR(reg_name) } + +/* + * Macro to define a particular register cfg entry for the remaining + * pipe indexed register. In Stingray case we don't have extra + * endpoints so it is intentially empty + */ +#define IPA_HW_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(REG_NAME, VAR_NAME) \ + { 0, 0 } + +/* + * Macro to set the active flag for all active pipe indexed register + * In Stingray case we don't have extra endpoints so it is intentially + * empty + */ +#define IPA_HW_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA_ACTIVE() \ + do { \ + } while (0) + +#endif /* #if !defined(_IPA_HW_COMMON_EX_H_) */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.5/ipa_hwio.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.5/ipa_hwio.h new file mode 100644 index 0000000000..8ee5952e7a --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.5/ipa_hwio.h @@ -0,0 +1,15373 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef __IPA_HWIO_H__ +#define __IPA_HWIO_H__ +/** + @file ipa_hwio.h + @brief Auto-generated HWIO interface include file. + + This file contains HWIO register definitions for the following modules: + IPA.* + + 'Include' filters applied: + 'Exclude' filters applied: RESERVED DUMMY + + Attribute definitions for the HWIO_*_ATTR macros are as follows: + 0x0: Command register + 0x1: Read-Only + 0x2: Write-Only + 0x3: Read/Write +*/ + +/*---------------------------------------------------------------------------- + * MODULE: IPA_UC_IPA_UC + *--------------------------------------------------------------------------*/ + +#define IPA_UC_IPA_UC_REG_BASE (IPA_0_IPA_WRAPPER_BASE + 0x001a0000) +#define IPA_UC_IPA_UC_REG_BASE_PHYS (IPA_0_IPA_WRAPPER_BASE_PHYS + 0x001a0000) +#define IPA_UC_IPA_UC_REG_BASE_OFFS 0x001a0000 + +/*---------------------------------------------------------------------------- + * MODULE: IPA_UC_IPA_UC_RAM + *--------------------------------------------------------------------------*/ + +#define IPA_UC_IPA_UC_RAM_REG_BASE (IPA_0_IPA_WRAPPER_BASE + 0x001a0000) +#define IPA_UC_IPA_UC_RAM_REG_BASE_PHYS (IPA_0_IPA_WRAPPER_BASE_PHYS + 0x001a0000) +#define IPA_UC_IPA_UC_RAM_REG_BASE_OFFS 0x001a0000 + +#define HWIO_IPA_UC_IRAM_START_ADDR (IPA_UC_IPA_UC_RAM_REG_BASE + 0x00000000) +#define HWIO_IPA_UC_IRAM_START_PHYS (IPA_UC_IPA_UC_RAM_REG_BASE_PHYS + 0x00000000) +#define HWIO_IPA_UC_IRAM_START_OFFS (IPA_UC_IPA_UC_RAM_REG_BASE_OFFS + 0x00000000) +#define HWIO_IPA_UC_IRAM_START_RMSK 0xffffffff +#define HWIO_IPA_UC_IRAM_START_ATTR 0x3 +#define HWIO_IPA_UC_IRAM_START_IN \ + in_dword_masked(HWIO_IPA_UC_IRAM_START_ADDR, HWIO_IPA_UC_IRAM_START_RMSK) +#define HWIO_IPA_UC_IRAM_START_INM(m) \ + in_dword_masked(HWIO_IPA_UC_IRAM_START_ADDR, m) +#define HWIO_IPA_UC_IRAM_START_OUT(v) \ + out_dword(HWIO_IPA_UC_IRAM_START_ADDR,v) +#define HWIO_IPA_UC_IRAM_START_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_IRAM_START_ADDR,m,v,HWIO_IPA_UC_IRAM_START_IN) +#define HWIO_IPA_UC_IRAM_START_DATA_BMSK 0xffffffff +#define HWIO_IPA_UC_IRAM_START_DATA_SHFT 0x0 + +#define HWIO_IPA_UC_DRAM_START_ADDR (IPA_UC_IPA_UC_RAM_REG_BASE + 0x0000a000) +#define HWIO_IPA_UC_DRAM_START_PHYS (IPA_UC_IPA_UC_RAM_REG_BASE_PHYS + 0x0000a000) +#define HWIO_IPA_UC_DRAM_START_OFFS (IPA_UC_IPA_UC_RAM_REG_BASE_OFFS + 0x0000a000) +#define HWIO_IPA_UC_DRAM_START_RMSK 0xffffffff +#define HWIO_IPA_UC_DRAM_START_ATTR 0x3 +#define HWIO_IPA_UC_DRAM_START_IN \ + in_dword_masked(HWIO_IPA_UC_DRAM_START_ADDR, HWIO_IPA_UC_DRAM_START_RMSK) +#define HWIO_IPA_UC_DRAM_START_INM(m) \ + in_dword_masked(HWIO_IPA_UC_DRAM_START_ADDR, m) +#define HWIO_IPA_UC_DRAM_START_OUT(v) \ + out_dword(HWIO_IPA_UC_DRAM_START_ADDR,v) +#define HWIO_IPA_UC_DRAM_START_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_DRAM_START_ADDR,m,v,HWIO_IPA_UC_DRAM_START_IN) +#define HWIO_IPA_UC_DRAM_START_DATA_BMSK 0xffffffff +#define HWIO_IPA_UC_DRAM_START_DATA_SHFT 0x0 + +/*---------------------------------------------------------------------------- + * MODULE: IPA_UC_IPA_UC_PER + *--------------------------------------------------------------------------*/ + +#define IPA_UC_IPA_UC_PER_REG_BASE (IPA_0_IPA_WRAPPER_BASE + 0x001c0000) +#define IPA_UC_IPA_UC_PER_REG_BASE_PHYS (IPA_0_IPA_WRAPPER_BASE_PHYS + 0x001c0000) +#define IPA_UC_IPA_UC_PER_REG_BASE_OFFS 0x001c0000 + +#define HWIO_IPA_UC_STATUS_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000000) +#define HWIO_IPA_UC_STATUS_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000000) +#define HWIO_IPA_UC_STATUS_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000000) +#define HWIO_IPA_UC_STATUS_RMSK 0xf +#define HWIO_IPA_UC_STATUS_ATTR 0x1 +#define HWIO_IPA_UC_STATUS_IN \ + in_dword_masked(HWIO_IPA_UC_STATUS_ADDR, HWIO_IPA_UC_STATUS_RMSK) +#define HWIO_IPA_UC_STATUS_INM(m) \ + in_dword_masked(HWIO_IPA_UC_STATUS_ADDR, m) +#define HWIO_IPA_UC_STATUS_UC_ENABLE_BMSK 0x8 +#define HWIO_IPA_UC_STATUS_UC_ENABLE_SHFT 0x3 +#define HWIO_IPA_UC_STATUS_LOCKUP_BMSK 0x4 +#define HWIO_IPA_UC_STATUS_LOCKUP_SHFT 0x2 +#define HWIO_IPA_UC_STATUS_SLEEP_BMSK 0x2 +#define HWIO_IPA_UC_STATUS_SLEEP_SHFT 0x1 +#define HWIO_IPA_UC_STATUS_SLEEPDEEP_BMSK 0x1 +#define HWIO_IPA_UC_STATUS_SLEEPDEEP_SHFT 0x0 + +#define HWIO_IPA_UC_CONTROL_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000004) +#define HWIO_IPA_UC_CONTROL_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000004) +#define HWIO_IPA_UC_CONTROL_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000004) +#define HWIO_IPA_UC_CONTROL_RMSK 0x9000ffe +#define HWIO_IPA_UC_CONTROL_ATTR 0x3 +#define HWIO_IPA_UC_CONTROL_IN \ + in_dword_masked(HWIO_IPA_UC_CONTROL_ADDR, HWIO_IPA_UC_CONTROL_RMSK) +#define HWIO_IPA_UC_CONTROL_INM(m) \ + in_dword_masked(HWIO_IPA_UC_CONTROL_ADDR, m) +#define HWIO_IPA_UC_CONTROL_OUT(v) \ + out_dword(HWIO_IPA_UC_CONTROL_ADDR,v) +#define HWIO_IPA_UC_CONTROL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_CONTROL_ADDR,m,v,HWIO_IPA_UC_CONTROL_IN) +#define HWIO_IPA_UC_CONTROL_UC_RAM_RD_CLI_CACHE_DIS_BMSK 0x8000000 +#define HWIO_IPA_UC_CONTROL_UC_RAM_RD_CLI_CACHE_DIS_SHFT 0x1b +#define HWIO_IPA_UC_CONTROL_WARMBOOT_DIS_BMSK 0x1000000 +#define HWIO_IPA_UC_CONTROL_WARMBOOT_DIS_SHFT 0x18 +#define HWIO_IPA_UC_CONTROL_MBOX_DIS_BMSK 0xff0 +#define HWIO_IPA_UC_CONTROL_MBOX_DIS_SHFT 0x4 +#define HWIO_IPA_UC_CONTROL_UC_CLOCK_GATING_DIS_BMSK 0x8 +#define HWIO_IPA_UC_CONTROL_UC_CLOCK_GATING_DIS_SHFT 0x3 +#define HWIO_IPA_UC_CONTROL_QMB_SNOC_BYPASS_DIS_BMSK 0x4 +#define HWIO_IPA_UC_CONTROL_QMB_SNOC_BYPASS_DIS_SHFT 0x2 +#define HWIO_IPA_UC_CONTROL_UC_DSMODE_BMSK 0x2 +#define HWIO_IPA_UC_CONTROL_UC_DSMODE_SHFT 0x1 + +#define HWIO_IPA_UC_SYS_BUS_ATTRIB_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000010) +#define HWIO_IPA_UC_SYS_BUS_ATTRIB_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000010) +#define HWIO_IPA_UC_SYS_BUS_ATTRIB_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000010) +#define HWIO_IPA_UC_SYS_BUS_ATTRIB_RMSK 0x1117 +#define HWIO_IPA_UC_SYS_BUS_ATTRIB_ATTR 0x3 +#define HWIO_IPA_UC_SYS_BUS_ATTRIB_IN \ + in_dword_masked(HWIO_IPA_UC_SYS_BUS_ATTRIB_ADDR, HWIO_IPA_UC_SYS_BUS_ATTRIB_RMSK) +#define HWIO_IPA_UC_SYS_BUS_ATTRIB_INM(m) \ + in_dword_masked(HWIO_IPA_UC_SYS_BUS_ATTRIB_ADDR, m) +#define HWIO_IPA_UC_SYS_BUS_ATTRIB_OUT(v) \ + out_dword(HWIO_IPA_UC_SYS_BUS_ATTRIB_ADDR,v) +#define HWIO_IPA_UC_SYS_BUS_ATTRIB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_SYS_BUS_ATTRIB_ADDR,m,v,HWIO_IPA_UC_SYS_BUS_ATTRIB_IN) +#define HWIO_IPA_UC_SYS_BUS_ATTRIB_SHARED_BMSK 0x1000 +#define HWIO_IPA_UC_SYS_BUS_ATTRIB_SHARED_SHFT 0xc +#define HWIO_IPA_UC_SYS_BUS_ATTRIB_INNERSHARED_BMSK 0x100 +#define HWIO_IPA_UC_SYS_BUS_ATTRIB_INNERSHARED_SHFT 0x8 +#define HWIO_IPA_UC_SYS_BUS_ATTRIB_NOALLOCATE_BMSK 0x10 +#define HWIO_IPA_UC_SYS_BUS_ATTRIB_NOALLOCATE_SHFT 0x4 +#define HWIO_IPA_UC_SYS_BUS_ATTRIB_MEMTYPE_BMSK 0x7 +#define HWIO_IPA_UC_SYS_BUS_ATTRIB_MEMTYPE_SHFT 0x0 +#define HWIO_IPA_UC_SYS_BUS_ATTRIB_MEMTYPE_STRONGLY_ORDERED_FVAL 0x0 +#define HWIO_IPA_UC_SYS_BUS_ATTRIB_MEMTYPE_DEVICE_FVAL 0x1 +#define HWIO_IPA_UC_SYS_BUS_ATTRIB_MEMTYPE_NON_CACHEABLE_FVAL 0x2 +#define HWIO_IPA_UC_SYS_BUS_ATTRIB_MEMTYPE_COPYBACK_WRITEALLOCATE_FVAL 0x3 +#define HWIO_IPA_UC_SYS_BUS_ATTRIB_MEMTYPE_WRITETHROUGH_NOALLOCATE_FVAL 0x6 +#define HWIO_IPA_UC_SYS_BUS_ATTRIB_MEMTYPE_COPYBACK_NOALLOCATE_FVAL 0x7 + +#define HWIO_IPA_UC_PEND_IRQ_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000014) +#define HWIO_IPA_UC_PEND_IRQ_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000014) +#define HWIO_IPA_UC_PEND_IRQ_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000014) +#define HWIO_IPA_UC_PEND_IRQ_RMSK 0xffffffff +#define HWIO_IPA_UC_PEND_IRQ_ATTR 0x1 +#define HWIO_IPA_UC_PEND_IRQ_IN \ + in_dword_masked(HWIO_IPA_UC_PEND_IRQ_ADDR, HWIO_IPA_UC_PEND_IRQ_RMSK) +#define HWIO_IPA_UC_PEND_IRQ_INM(m) \ + in_dword_masked(HWIO_IPA_UC_PEND_IRQ_ADDR, m) +#define HWIO_IPA_UC_PEND_IRQ_PEND_IRQ_BMSK 0xffffffff +#define HWIO_IPA_UC_PEND_IRQ_PEND_IRQ_SHFT 0x0 + +#define HWIO_IPA_UC_TRACE_BUFFER_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000018) +#define HWIO_IPA_UC_TRACE_BUFFER_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000018) +#define HWIO_IPA_UC_TRACE_BUFFER_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000018) +#define HWIO_IPA_UC_TRACE_BUFFER_RMSK 0xffffffff +#define HWIO_IPA_UC_TRACE_BUFFER_ATTR 0x1 +#define HWIO_IPA_UC_TRACE_BUFFER_IN \ + in_dword_masked(HWIO_IPA_UC_TRACE_BUFFER_ADDR, HWIO_IPA_UC_TRACE_BUFFER_RMSK) +#define HWIO_IPA_UC_TRACE_BUFFER_INM(m) \ + in_dword_masked(HWIO_IPA_UC_TRACE_BUFFER_ADDR, m) +#define HWIO_IPA_UC_TRACE_BUFFER_TRACE_BUFFER_BMSK 0xffffffff +#define HWIO_IPA_UC_TRACE_BUFFER_TRACE_BUFFER_SHFT 0x0 + +#define HWIO_IPA_UC_PC_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x0000001c) +#define HWIO_IPA_UC_PC_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x0000001c) +#define HWIO_IPA_UC_PC_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x0000001c) +#define HWIO_IPA_UC_PC_RMSK 0xffffffff +#define HWIO_IPA_UC_PC_ATTR 0x1 +#define HWIO_IPA_UC_PC_IN \ + in_dword_masked(HWIO_IPA_UC_PC_ADDR, HWIO_IPA_UC_PC_RMSK) +#define HWIO_IPA_UC_PC_INM(m) \ + in_dword_masked(HWIO_IPA_UC_PC_ADDR, m) +#define HWIO_IPA_UC_PC_PC_BMSK 0xffffffff +#define HWIO_IPA_UC_PC_PC_SHFT 0x0 + +#define HWIO_IPA_UC_VUIC_INT_ADDRESS_LSB_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000024) +#define HWIO_IPA_UC_VUIC_INT_ADDRESS_LSB_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000024) +#define HWIO_IPA_UC_VUIC_INT_ADDRESS_LSB_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000024) +#define HWIO_IPA_UC_VUIC_INT_ADDRESS_LSB_RMSK 0xffffffff +#define HWIO_IPA_UC_VUIC_INT_ADDRESS_LSB_ATTR 0x1 +#define HWIO_IPA_UC_VUIC_INT_ADDRESS_LSB_IN \ + in_dword_masked(HWIO_IPA_UC_VUIC_INT_ADDRESS_LSB_ADDR, HWIO_IPA_UC_VUIC_INT_ADDRESS_LSB_RMSK) +#define HWIO_IPA_UC_VUIC_INT_ADDRESS_LSB_INM(m) \ + in_dword_masked(HWIO_IPA_UC_VUIC_INT_ADDRESS_LSB_ADDR, m) +#define HWIO_IPA_UC_VUIC_INT_ADDRESS_LSB_ADDRRESS_BMSK 0xffffffff +#define HWIO_IPA_UC_VUIC_INT_ADDRESS_LSB_ADDRRESS_SHFT 0x0 + +#define HWIO_IPA_UC_VUIC_INT_ADDRESS_MSB_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000028) +#define HWIO_IPA_UC_VUIC_INT_ADDRESS_MSB_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000028) +#define HWIO_IPA_UC_VUIC_INT_ADDRESS_MSB_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000028) +#define HWIO_IPA_UC_VUIC_INT_ADDRESS_MSB_RMSK 0x1ff +#define HWIO_IPA_UC_VUIC_INT_ADDRESS_MSB_ATTR 0x1 +#define HWIO_IPA_UC_VUIC_INT_ADDRESS_MSB_IN \ + in_dword_masked(HWIO_IPA_UC_VUIC_INT_ADDRESS_MSB_ADDR, HWIO_IPA_UC_VUIC_INT_ADDRESS_MSB_RMSK) +#define HWIO_IPA_UC_VUIC_INT_ADDRESS_MSB_INM(m) \ + in_dword_masked(HWIO_IPA_UC_VUIC_INT_ADDRESS_MSB_ADDR, m) +#define HWIO_IPA_UC_VUIC_INT_ADDRESS_MSB_ADDRRESS_BMSK 0x1ff +#define HWIO_IPA_UC_VUIC_INT_ADDRESS_MSB_ADDRRESS_SHFT 0x0 + +#define HWIO_IPA_UC_QMB_SYS_ADDR_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000100) +#define HWIO_IPA_UC_QMB_SYS_ADDR_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000100) +#define HWIO_IPA_UC_QMB_SYS_ADDR_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000100) +#define HWIO_IPA_UC_QMB_SYS_ADDR_RMSK 0xffffffff +#define HWIO_IPA_UC_QMB_SYS_ADDR_ATTR 0x3 +#define HWIO_IPA_UC_QMB_SYS_ADDR_IN \ + in_dword_masked(HWIO_IPA_UC_QMB_SYS_ADDR_ADDR, HWIO_IPA_UC_QMB_SYS_ADDR_RMSK) +#define HWIO_IPA_UC_QMB_SYS_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_UC_QMB_SYS_ADDR_ADDR, m) +#define HWIO_IPA_UC_QMB_SYS_ADDR_OUT(v) \ + out_dword(HWIO_IPA_UC_QMB_SYS_ADDR_ADDR,v) +#define HWIO_IPA_UC_QMB_SYS_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_QMB_SYS_ADDR_ADDR,m,v,HWIO_IPA_UC_QMB_SYS_ADDR_IN) +#define HWIO_IPA_UC_QMB_SYS_ADDR_ADDR_BMSK 0xffffffff +#define HWIO_IPA_UC_QMB_SYS_ADDR_ADDR_SHFT 0x0 + +#define HWIO_IPA_UC_QMB_SYS_ADDR_MSB_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000104) +#define HWIO_IPA_UC_QMB_SYS_ADDR_MSB_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000104) +#define HWIO_IPA_UC_QMB_SYS_ADDR_MSB_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000104) +#define HWIO_IPA_UC_QMB_SYS_ADDR_MSB_RMSK 0xffffffff +#define HWIO_IPA_UC_QMB_SYS_ADDR_MSB_ATTR 0x3 +#define HWIO_IPA_UC_QMB_SYS_ADDR_MSB_IN \ + in_dword_masked(HWIO_IPA_UC_QMB_SYS_ADDR_MSB_ADDR, HWIO_IPA_UC_QMB_SYS_ADDR_MSB_RMSK) +#define HWIO_IPA_UC_QMB_SYS_ADDR_MSB_INM(m) \ + in_dword_masked(HWIO_IPA_UC_QMB_SYS_ADDR_MSB_ADDR, m) +#define HWIO_IPA_UC_QMB_SYS_ADDR_MSB_OUT(v) \ + out_dword(HWIO_IPA_UC_QMB_SYS_ADDR_MSB_ADDR,v) +#define HWIO_IPA_UC_QMB_SYS_ADDR_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_QMB_SYS_ADDR_MSB_ADDR,m,v,HWIO_IPA_UC_QMB_SYS_ADDR_MSB_IN) +#define HWIO_IPA_UC_QMB_SYS_ADDR_MSB_ADDR_MSB_BMSK 0xffffffff +#define HWIO_IPA_UC_QMB_SYS_ADDR_MSB_ADDR_MSB_SHFT 0x0 + +#define HWIO_IPA_UC_QMB_LOCAL_ADDR_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000108) +#define HWIO_IPA_UC_QMB_LOCAL_ADDR_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000108) +#define HWIO_IPA_UC_QMB_LOCAL_ADDR_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000108) +#define HWIO_IPA_UC_QMB_LOCAL_ADDR_RMSK 0x3ffff +#define HWIO_IPA_UC_QMB_LOCAL_ADDR_ATTR 0x3 +#define HWIO_IPA_UC_QMB_LOCAL_ADDR_IN \ + in_dword_masked(HWIO_IPA_UC_QMB_LOCAL_ADDR_ADDR, HWIO_IPA_UC_QMB_LOCAL_ADDR_RMSK) +#define HWIO_IPA_UC_QMB_LOCAL_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_UC_QMB_LOCAL_ADDR_ADDR, m) +#define HWIO_IPA_UC_QMB_LOCAL_ADDR_OUT(v) \ + out_dword(HWIO_IPA_UC_QMB_LOCAL_ADDR_ADDR,v) +#define HWIO_IPA_UC_QMB_LOCAL_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_QMB_LOCAL_ADDR_ADDR,m,v,HWIO_IPA_UC_QMB_LOCAL_ADDR_IN) +#define HWIO_IPA_UC_QMB_LOCAL_ADDR_ADDR_BMSK 0x3ffff +#define HWIO_IPA_UC_QMB_LOCAL_ADDR_ADDR_SHFT 0x0 + +#define HWIO_IPA_UC_QMB_LENGTH_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x0000010c) +#define HWIO_IPA_UC_QMB_LENGTH_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x0000010c) +#define HWIO_IPA_UC_QMB_LENGTH_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x0000010c) +#define HWIO_IPA_UC_QMB_LENGTH_RMSK 0xffff +#define HWIO_IPA_UC_QMB_LENGTH_ATTR 0x3 +#define HWIO_IPA_UC_QMB_LENGTH_IN \ + in_dword_masked(HWIO_IPA_UC_QMB_LENGTH_ADDR, HWIO_IPA_UC_QMB_LENGTH_RMSK) +#define HWIO_IPA_UC_QMB_LENGTH_INM(m) \ + in_dword_masked(HWIO_IPA_UC_QMB_LENGTH_ADDR, m) +#define HWIO_IPA_UC_QMB_LENGTH_OUT(v) \ + out_dword(HWIO_IPA_UC_QMB_LENGTH_ADDR,v) +#define HWIO_IPA_UC_QMB_LENGTH_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_QMB_LENGTH_ADDR,m,v,HWIO_IPA_UC_QMB_LENGTH_IN) +#define HWIO_IPA_UC_QMB_LENGTH_LENGTH_BMSK 0xffff +#define HWIO_IPA_UC_QMB_LENGTH_LENGTH_SHFT 0x0 + +#define HWIO_IPA_UC_QMB_TRIGGER_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000110) +#define HWIO_IPA_UC_QMB_TRIGGER_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000110) +#define HWIO_IPA_UC_QMB_TRIGGER_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000110) +#define HWIO_IPA_UC_QMB_TRIGGER_RMSK 0xffffffff +#define HWIO_IPA_UC_QMB_TRIGGER_ATTR 0x2 +#define HWIO_IPA_UC_QMB_TRIGGER_OUT(v) \ + out_dword(HWIO_IPA_UC_QMB_TRIGGER_ADDR,v) +#define HWIO_IPA_UC_QMB_TRIGGER_RSV_BMSK 0xffffffff +#define HWIO_IPA_UC_QMB_TRIGGER_RSV_SHFT 0x0 + +#define HWIO_IPA_UC_QMB_COMMAND_ATTR_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000114) +#define HWIO_IPA_UC_QMB_COMMAND_ATTR_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000114) +#define HWIO_IPA_UC_QMB_COMMAND_ATTR_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000114) +#define HWIO_IPA_UC_QMB_COMMAND_ATTR_RMSK 0x7ff003f +#define HWIO_IPA_UC_QMB_COMMAND_ATTR_ATTR 0x3 +#define HWIO_IPA_UC_QMB_COMMAND_ATTR_IN \ + in_dword_masked(HWIO_IPA_UC_QMB_COMMAND_ATTR_ADDR, HWIO_IPA_UC_QMB_COMMAND_ATTR_RMSK) +#define HWIO_IPA_UC_QMB_COMMAND_ATTR_INM(m) \ + in_dword_masked(HWIO_IPA_UC_QMB_COMMAND_ATTR_ADDR, m) +#define HWIO_IPA_UC_QMB_COMMAND_ATTR_OUT(v) \ + out_dword(HWIO_IPA_UC_QMB_COMMAND_ATTR_ADDR,v) +#define HWIO_IPA_UC_QMB_COMMAND_ATTR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_QMB_COMMAND_ATTR_ADDR,m,v,HWIO_IPA_UC_QMB_COMMAND_ATTR_IN) +#define HWIO_IPA_UC_QMB_COMMAND_ATTR_USER_BMSK 0x7ff0000 +#define HWIO_IPA_UC_QMB_COMMAND_ATTR_USER_SHFT 0x10 +#define HWIO_IPA_UC_QMB_COMMAND_ATTR_QUEUE_NUMBER_BMSK 0x20 +#define HWIO_IPA_UC_QMB_COMMAND_ATTR_QUEUE_NUMBER_SHFT 0x5 +#define HWIO_IPA_UC_QMB_COMMAND_ATTR_INTERRUPT_ON_COMPLETION_BMSK 0x10 +#define HWIO_IPA_UC_QMB_COMMAND_ATTR_INTERRUPT_ON_COMPLETION_SHFT 0x4 +#define HWIO_IPA_UC_QMB_COMMAND_ATTR_SYNC_BMSK 0x8 +#define HWIO_IPA_UC_QMB_COMMAND_ATTR_SYNC_SHFT 0x3 +#define HWIO_IPA_UC_QMB_COMMAND_ATTR_WAIT_FOR_RESPONSE_MODE_BMSK 0x4 +#define HWIO_IPA_UC_QMB_COMMAND_ATTR_WAIT_FOR_RESPONSE_MODE_SHFT 0x2 +#define HWIO_IPA_UC_QMB_COMMAND_ATTR_INORDER_BMSK 0x2 +#define HWIO_IPA_UC_QMB_COMMAND_ATTR_INORDER_SHFT 0x1 +#define HWIO_IPA_UC_QMB_COMMAND_ATTR_DIRECTION_BMSK 0x1 +#define HWIO_IPA_UC_QMB_COMMAND_ATTR_DIRECTION_SHFT 0x0 + +#define HWIO_IPA_UC_QMB_COMMAND_UCTAG_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000118) +#define HWIO_IPA_UC_QMB_COMMAND_UCTAG_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000118) +#define HWIO_IPA_UC_QMB_COMMAND_UCTAG_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000118) +#define HWIO_IPA_UC_QMB_COMMAND_UCTAG_RMSK 0x3ffff +#define HWIO_IPA_UC_QMB_COMMAND_UCTAG_ATTR 0x3 +#define HWIO_IPA_UC_QMB_COMMAND_UCTAG_IN \ + in_dword_masked(HWIO_IPA_UC_QMB_COMMAND_UCTAG_ADDR, HWIO_IPA_UC_QMB_COMMAND_UCTAG_RMSK) +#define HWIO_IPA_UC_QMB_COMMAND_UCTAG_INM(m) \ + in_dword_masked(HWIO_IPA_UC_QMB_COMMAND_UCTAG_ADDR, m) +#define HWIO_IPA_UC_QMB_COMMAND_UCTAG_OUT(v) \ + out_dword(HWIO_IPA_UC_QMB_COMMAND_UCTAG_ADDR,v) +#define HWIO_IPA_UC_QMB_COMMAND_UCTAG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_QMB_COMMAND_UCTAG_ADDR,m,v,HWIO_IPA_UC_QMB_COMMAND_UCTAG_IN) +#define HWIO_IPA_UC_QMB_COMMAND_UCTAG_UCTAG_BMSK 0x3ffff +#define HWIO_IPA_UC_QMB_COMMAND_UCTAG_UCTAG_SHFT 0x0 + +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_n_ADDR(n) (IPA_UC_IPA_UC_PER_REG_BASE + 0x0000011c + 0x4 * (n)) +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_n_PHYS(n) (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x0000011c + 0x4 * (n)) +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_n_OFFS(n) (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x0000011c + 0x4 * (n)) +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_n_RMSK 0xc7ffffff +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_n_MAXn 1 +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_n_ATTR 0x1 +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_n_INI(n) \ + in_dword_masked(HWIO_IPA_UC_QMB_COMPLETED_FIFO_n_ADDR(n), HWIO_IPA_UC_QMB_COMPLETED_FIFO_n_RMSK) +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_UC_QMB_COMPLETED_FIFO_n_ADDR(n), mask) +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_n_FULL_BMSK 0x80000000 +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_n_FULL_SHFT 0x1f +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_n_EMPTY_BMSK 0x40000000 +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_n_EMPTY_SHFT 0x1e +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_n_ERROR_BMSK 0x4000000 +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_n_ERROR_SHFT 0x1a +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_n_FIFO_CNT_BMSK 0x3c00000 +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_n_FIFO_CNT_SHFT 0x16 +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_n_FIFO_SIZE_BMSK 0x3c0000 +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_n_FIFO_SIZE_SHFT 0x12 +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_n_UCTAG_BMSK 0x3ffff +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_n_UCTAG_SHFT 0x0 + +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_PEEK_n_ADDR(n) (IPA_UC_IPA_UC_PER_REG_BASE + 0x0000012c + 0x4 * (n)) +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_PEEK_n_PHYS(n) (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x0000012c + 0x4 * (n)) +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_PEEK_n_OFFS(n) (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x0000012c + 0x4 * (n)) +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_PEEK_n_RMSK 0xc7ffffff +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_PEEK_n_MAXn 1 +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_PEEK_n_ATTR 0x1 +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_PEEK_n_INI(n) \ + in_dword_masked(HWIO_IPA_UC_QMB_COMPLETED_FIFO_PEEK_n_ADDR(n), HWIO_IPA_UC_QMB_COMPLETED_FIFO_PEEK_n_RMSK) +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_PEEK_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_UC_QMB_COMPLETED_FIFO_PEEK_n_ADDR(n), mask) +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_PEEK_n_FULL_BMSK 0x80000000 +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_PEEK_n_FULL_SHFT 0x1f +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_PEEK_n_EMPTY_BMSK 0x40000000 +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_PEEK_n_EMPTY_SHFT 0x1e +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_PEEK_n_ERROR_BMSK 0x4000000 +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_PEEK_n_ERROR_SHFT 0x1a +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_PEEK_n_FIFO_CNT_BMSK 0x3c00000 +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_PEEK_n_FIFO_CNT_SHFT 0x16 +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_PEEK_n_FIFO_SIZE_BMSK 0x3c0000 +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_PEEK_n_FIFO_SIZE_SHFT 0x12 +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_PEEK_n_UCTAG_BMSK 0x3ffff +#define HWIO_IPA_UC_QMB_COMPLETED_FIFO_PEEK_n_UCTAG_SHFT 0x0 + +#define HWIO_IPA_UC_QMB_CMD_FIFO_STATUS_n_ADDR(n) (IPA_UC_IPA_UC_PER_REG_BASE + 0x0000013c + 0x4 * (n)) +#define HWIO_IPA_UC_QMB_CMD_FIFO_STATUS_n_PHYS(n) (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x0000013c + 0x4 * (n)) +#define HWIO_IPA_UC_QMB_CMD_FIFO_STATUS_n_OFFS(n) (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x0000013c + 0x4 * (n)) +#define HWIO_IPA_UC_QMB_CMD_FIFO_STATUS_n_RMSK 0x300ff +#define HWIO_IPA_UC_QMB_CMD_FIFO_STATUS_n_MAXn 1 +#define HWIO_IPA_UC_QMB_CMD_FIFO_STATUS_n_ATTR 0x1 +#define HWIO_IPA_UC_QMB_CMD_FIFO_STATUS_n_INI(n) \ + in_dword_masked(HWIO_IPA_UC_QMB_CMD_FIFO_STATUS_n_ADDR(n), HWIO_IPA_UC_QMB_CMD_FIFO_STATUS_n_RMSK) +#define HWIO_IPA_UC_QMB_CMD_FIFO_STATUS_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_UC_QMB_CMD_FIFO_STATUS_n_ADDR(n), mask) +#define HWIO_IPA_UC_QMB_CMD_FIFO_STATUS_n_FULL_BMSK 0x20000 +#define HWIO_IPA_UC_QMB_CMD_FIFO_STATUS_n_FULL_SHFT 0x11 +#define HWIO_IPA_UC_QMB_CMD_FIFO_STATUS_n_EMPTY_BMSK 0x10000 +#define HWIO_IPA_UC_QMB_CMD_FIFO_STATUS_n_EMPTY_SHFT 0x10 +#define HWIO_IPA_UC_QMB_CMD_FIFO_STATUS_n_FIFO_CNT_BMSK 0xf0 +#define HWIO_IPA_UC_QMB_CMD_FIFO_STATUS_n_FIFO_CNT_SHFT 0x4 +#define HWIO_IPA_UC_QMB_CMD_FIFO_STATUS_n_FIFO_SIZE_BMSK 0xf +#define HWIO_IPA_UC_QMB_CMD_FIFO_STATUS_n_FIFO_SIZE_SHFT 0x0 + +#define HWIO_IPA_UC_QMB_SYNC_STATUS_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000150) +#define HWIO_IPA_UC_QMB_SYNC_STATUS_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000150) +#define HWIO_IPA_UC_QMB_SYNC_STATUS_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000150) +#define HWIO_IPA_UC_QMB_SYNC_STATUS_RMSK 0x10001 +#define HWIO_IPA_UC_QMB_SYNC_STATUS_ATTR 0x1 +#define HWIO_IPA_UC_QMB_SYNC_STATUS_IN \ + in_dword_masked(HWIO_IPA_UC_QMB_SYNC_STATUS_ADDR, HWIO_IPA_UC_QMB_SYNC_STATUS_RMSK) +#define HWIO_IPA_UC_QMB_SYNC_STATUS_INM(m) \ + in_dword_masked(HWIO_IPA_UC_QMB_SYNC_STATUS_ADDR, m) +#define HWIO_IPA_UC_QMB_SYNC_STATUS_ERROR_QUEUE_1_BMSK 0x10000 +#define HWIO_IPA_UC_QMB_SYNC_STATUS_ERROR_QUEUE_1_SHFT 0x10 +#define HWIO_IPA_UC_QMB_SYNC_STATUS_ERROR_QUEUE_0_BMSK 0x1 +#define HWIO_IPA_UC_QMB_SYNC_STATUS_ERROR_QUEUE_0_SHFT 0x0 + +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000154) +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000154) +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000154) +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_RMSK 0x1117 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_ATTR 0x3 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_IN \ + in_dword_masked(HWIO_IPA_UC_QMB_BUS_ATTRIB_ADDR, HWIO_IPA_UC_QMB_BUS_ATTRIB_RMSK) +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_INM(m) \ + in_dword_masked(HWIO_IPA_UC_QMB_BUS_ATTRIB_ADDR, m) +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_OUT(v) \ + out_dword(HWIO_IPA_UC_QMB_BUS_ATTRIB_ADDR,v) +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_QMB_BUS_ATTRIB_ADDR,m,v,HWIO_IPA_UC_QMB_BUS_ATTRIB_IN) +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_SHARED_BMSK 0x1000 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_SHARED_SHFT 0xc +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_INNERSHARED_BMSK 0x100 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_INNERSHARED_SHFT 0x8 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_NOALLOCATE_BMSK 0x10 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_NOALLOCATE_SHFT 0x4 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_MEMTYPE_BMSK 0x7 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_MEMTYPE_SHFT 0x0 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_MEMTYPE_STRONGLY_ORDERED_FVAL 0x0 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_MEMTYPE_DEVICE_FVAL 0x1 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_MEMTYPE_NON_CACHEABLE_FVAL 0x2 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_MEMTYPE_COPYBACK_WRITEALLOCATE_FVAL 0x3 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_MEMTYPE_WRITETHROUGH_NOALLOCATE_FVAL 0x6 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_MEMTYPE_COPYBACK_NOALLOCATE_FVAL 0x7 + +#define HWIO_IPA_UC_QMB_OUTSTANDING_CFG_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000158) +#define HWIO_IPA_UC_QMB_OUTSTANDING_CFG_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000158) +#define HWIO_IPA_UC_QMB_OUTSTANDING_CFG_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000158) +#define HWIO_IPA_UC_QMB_OUTSTANDING_CFG_RMSK 0xffffff +#define HWIO_IPA_UC_QMB_OUTSTANDING_CFG_ATTR 0x3 +#define HWIO_IPA_UC_QMB_OUTSTANDING_CFG_IN \ + in_dword_masked(HWIO_IPA_UC_QMB_OUTSTANDING_CFG_ADDR, HWIO_IPA_UC_QMB_OUTSTANDING_CFG_RMSK) +#define HWIO_IPA_UC_QMB_OUTSTANDING_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_UC_QMB_OUTSTANDING_CFG_ADDR, m) +#define HWIO_IPA_UC_QMB_OUTSTANDING_CFG_OUT(v) \ + out_dword(HWIO_IPA_UC_QMB_OUTSTANDING_CFG_ADDR,v) +#define HWIO_IPA_UC_QMB_OUTSTANDING_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_QMB_OUTSTANDING_CFG_ADDR,m,v,HWIO_IPA_UC_QMB_OUTSTANDING_CFG_IN) +#define HWIO_IPA_UC_QMB_OUTSTANDING_CFG_MAX_OT_WR_BMSK 0xff0000 +#define HWIO_IPA_UC_QMB_OUTSTANDING_CFG_MAX_OT_WR_SHFT 0x10 +#define HWIO_IPA_UC_QMB_OUTSTANDING_CFG_MAX_OT_RD_BMSK 0xff00 +#define HWIO_IPA_UC_QMB_OUTSTANDING_CFG_MAX_OT_RD_SHFT 0x8 +#define HWIO_IPA_UC_QMB_OUTSTANDING_CFG_MAX_OT_OVERALL_BMSK 0xff +#define HWIO_IPA_UC_QMB_OUTSTANDING_CFG_MAX_OT_OVERALL_SHFT 0x0 + +#define HWIO_IPA_UC_QMB_OUTSTANDING_STATUS_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x0000015c) +#define HWIO_IPA_UC_QMB_OUTSTANDING_STATUS_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x0000015c) +#define HWIO_IPA_UC_QMB_OUTSTANDING_STATUS_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x0000015c) +#define HWIO_IPA_UC_QMB_OUTSTANDING_STATUS_RMSK 0xffffff +#define HWIO_IPA_UC_QMB_OUTSTANDING_STATUS_ATTR 0x1 +#define HWIO_IPA_UC_QMB_OUTSTANDING_STATUS_IN \ + in_dword_masked(HWIO_IPA_UC_QMB_OUTSTANDING_STATUS_ADDR, HWIO_IPA_UC_QMB_OUTSTANDING_STATUS_RMSK) +#define HWIO_IPA_UC_QMB_OUTSTANDING_STATUS_INM(m) \ + in_dword_masked(HWIO_IPA_UC_QMB_OUTSTANDING_STATUS_ADDR, m) +#define HWIO_IPA_UC_QMB_OUTSTANDING_STATUS_CURRENT_OT_WR_BMSK 0xff0000 +#define HWIO_IPA_UC_QMB_OUTSTANDING_STATUS_CURRENT_OT_WR_SHFT 0x10 +#define HWIO_IPA_UC_QMB_OUTSTANDING_STATUS_CURRENT_OT_RD_BMSK 0xff00 +#define HWIO_IPA_UC_QMB_OUTSTANDING_STATUS_CURRENT_OT_RD_SHFT 0x8 +#define HWIO_IPA_UC_QMB_OUTSTANDING_STATUS_CURRENT_OT_OVERALL_BMSK 0xff +#define HWIO_IPA_UC_QMB_OUTSTANDING_STATUS_CURRENT_OT_OVERALL_SHFT 0x0 + +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_EN_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000160) +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_EN_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000160) +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_EN_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000160) +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_EN_RMSK 0x70007 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_EN_ATTR 0x3 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_EN_IN \ + in_dword_masked(HWIO_IPA_UC_QMB_COMP_FIFO_INT_EN_ADDR, HWIO_IPA_UC_QMB_COMP_FIFO_INT_EN_RMSK) +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_EN_INM(m) \ + in_dword_masked(HWIO_IPA_UC_QMB_COMP_FIFO_INT_EN_ADDR, m) +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_EN_OUT(v) \ + out_dword(HWIO_IPA_UC_QMB_COMP_FIFO_INT_EN_ADDR,v) +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_EN_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_QMB_COMP_FIFO_INT_EN_ADDR,m,v,HWIO_IPA_UC_QMB_COMP_FIFO_INT_EN_IN) +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_EN_COMP_FIFO_1_IOC_CMD_BMSK 0x40000 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_EN_COMP_FIFO_1_IOC_CMD_SHFT 0x12 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_EN_COMP_FIFO_1_FULL_BMSK 0x20000 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_EN_COMP_FIFO_1_FULL_SHFT 0x11 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_EN_COMP_FIFO_1_NOT_EMPTY_BMSK 0x10000 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_EN_COMP_FIFO_1_NOT_EMPTY_SHFT 0x10 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_EN_COMP_FIFO_0_IOC_CMD_BMSK 0x4 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_EN_COMP_FIFO_0_IOC_CMD_SHFT 0x2 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_EN_COMP_FIFO_0_FULL_BMSK 0x2 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_EN_COMP_FIFO_0_FULL_SHFT 0x1 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_EN_COMP_FIFO_0_NOT_EMPTY_BMSK 0x1 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_EN_COMP_FIFO_0_NOT_EMPTY_SHFT 0x0 + +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_CLR_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000164) +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_CLR_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000164) +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_CLR_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000164) +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_CLR_RMSK 0x70007 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_CLR_ATTR 0x2 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_CLR_OUT(v) \ + out_dword(HWIO_IPA_UC_QMB_COMP_FIFO_INT_CLR_ADDR,v) +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_CLR_COMP_FIFO_1_IOC_CMD_BMSK 0x40000 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_CLR_COMP_FIFO_1_IOC_CMD_SHFT 0x12 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_CLR_COMP_FIFO_1_FULL_BMSK 0x20000 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_CLR_COMP_FIFO_1_FULL_SHFT 0x11 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_CLR_COMP_FIFO_1_NOT_EMPTY_BMSK 0x10000 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_CLR_COMP_FIFO_1_NOT_EMPTY_SHFT 0x10 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_CLR_COMP_FIFO_0_IOC_CMD_BMSK 0x4 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_CLR_COMP_FIFO_0_IOC_CMD_SHFT 0x2 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_CLR_COMP_FIFO_0_FULL_BMSK 0x2 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_CLR_COMP_FIFO_0_FULL_SHFT 0x1 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_CLR_COMP_FIFO_0_NOT_EMPTY_BMSK 0x1 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_CLR_COMP_FIFO_0_NOT_EMPTY_SHFT 0x0 + +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_STTS_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000168) +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_STTS_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000168) +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_STTS_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000168) +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_STTS_RMSK 0x70007 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_STTS_ATTR 0x1 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_STTS_IN \ + in_dword_masked(HWIO_IPA_UC_QMB_COMP_FIFO_INT_STTS_ADDR, HWIO_IPA_UC_QMB_COMP_FIFO_INT_STTS_RMSK) +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_STTS_INM(m) \ + in_dword_masked(HWIO_IPA_UC_QMB_COMP_FIFO_INT_STTS_ADDR, m) +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_STTS_COMP_FIFO_1_IOC_CMD_BMSK 0x40000 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_STTS_COMP_FIFO_1_IOC_CMD_SHFT 0x12 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_STTS_COMP_FIFO_1_FULL_BMSK 0x20000 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_STTS_COMP_FIFO_1_FULL_SHFT 0x11 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_STTS_COMP_FIFO_1_NOT_EMPTY_BMSK 0x10000 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_STTS_COMP_FIFO_1_NOT_EMPTY_SHFT 0x10 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_STTS_COMP_FIFO_0_IOC_CMD_BMSK 0x4 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_STTS_COMP_FIFO_0_IOC_CMD_SHFT 0x2 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_STTS_COMP_FIFO_0_FULL_BMSK 0x2 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_STTS_COMP_FIFO_0_FULL_SHFT 0x1 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_STTS_COMP_FIFO_0_NOT_EMPTY_BMSK 0x1 +#define HWIO_IPA_UC_QMB_COMP_FIFO_INT_STTS_COMP_FIFO_0_NOT_EMPTY_SHFT 0x0 + +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_EN_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x0000016c) +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_EN_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x0000016c) +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_EN_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x0000016c) +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_EN_RMSK 0x3 +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_EN_ATTR 0x3 +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_EN_IN \ + in_dword_masked(HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_EN_ADDR, HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_EN_RMSK) +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_EN_INM(m) \ + in_dword_masked(HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_EN_ADDR, m) +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_EN_OUT(v) \ + out_dword(HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_EN_ADDR,v) +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_EN_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_EN_ADDR,m,v,HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_EN_IN) +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_EN_SYNC_COMPLETED_1_BMSK 0x2 +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_EN_SYNC_COMPLETED_1_SHFT 0x1 +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_EN_SYNC_COMPLETED_0_BMSK 0x1 +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_EN_SYNC_COMPLETED_0_SHFT 0x0 + +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_CLR_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000170) +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_CLR_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000170) +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_CLR_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000170) +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_CLR_RMSK 0x3 +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_CLR_ATTR 0x2 +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_CLR_OUT(v) \ + out_dword(HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_CLR_ADDR,v) +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_CLR_SYNC_COMPLETED_1_BMSK 0x2 +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_CLR_SYNC_COMPLETED_1_SHFT 0x1 +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_CLR_SYNC_COMPLETED_0_BMSK 0x1 +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_CLR_SYNC_COMPLETED_0_SHFT 0x0 + +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_STTS_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000174) +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_STTS_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000174) +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_STTS_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000174) +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_STTS_RMSK 0x3 +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_STTS_ATTR 0x1 +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_STTS_IN \ + in_dword_masked(HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_STTS_ADDR, HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_STTS_RMSK) +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_STTS_INM(m) \ + in_dword_masked(HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_STTS_ADDR, m) +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_STTS_SYNC_COMPLETED_1_BMSK 0x2 +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_STTS_SYNC_COMPLETED_1_SHFT 0x1 +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_STTS_SYNC_COMPLETED_0_BMSK 0x1 +#define HWIO_IPA_UC_QMB_SYNC_COMPLETE_INT_STTS_SYNC_COMPLETED_0_SHFT 0x0 + +#define HWIO_IPA_UC_MBOX_INT_STTS_n_ADDR(n) (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000200 + 0x10 * (n)) +#define HWIO_IPA_UC_MBOX_INT_STTS_n_PHYS(n) (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000200 + 0x10 * (n)) +#define HWIO_IPA_UC_MBOX_INT_STTS_n_OFFS(n) (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000200 + 0x10 * (n)) +#define HWIO_IPA_UC_MBOX_INT_STTS_n_RMSK 0xffff +#define HWIO_IPA_UC_MBOX_INT_STTS_n_MAXn 7 +#define HWIO_IPA_UC_MBOX_INT_STTS_n_ATTR 0x1 +#define HWIO_IPA_UC_MBOX_INT_STTS_n_INI(n) \ + in_dword_masked(HWIO_IPA_UC_MBOX_INT_STTS_n_ADDR(n), HWIO_IPA_UC_MBOX_INT_STTS_n_RMSK) +#define HWIO_IPA_UC_MBOX_INT_STTS_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_UC_MBOX_INT_STTS_n_ADDR(n), mask) +#define HWIO_IPA_UC_MBOX_INT_STTS_n_IRQ_STATUS_BMSK 0xffff +#define HWIO_IPA_UC_MBOX_INT_STTS_n_IRQ_STATUS_SHFT 0x0 + +#define HWIO_IPA_UC_MBOX_INT_EN_n_ADDR(n) (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000204 + 0x10 * (n)) +#define HWIO_IPA_UC_MBOX_INT_EN_n_PHYS(n) (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000204 + 0x10 * (n)) +#define HWIO_IPA_UC_MBOX_INT_EN_n_OFFS(n) (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000204 + 0x10 * (n)) +#define HWIO_IPA_UC_MBOX_INT_EN_n_RMSK 0xffff +#define HWIO_IPA_UC_MBOX_INT_EN_n_MAXn 7 +#define HWIO_IPA_UC_MBOX_INT_EN_n_ATTR 0x3 +#define HWIO_IPA_UC_MBOX_INT_EN_n_INI(n) \ + in_dword_masked(HWIO_IPA_UC_MBOX_INT_EN_n_ADDR(n), HWIO_IPA_UC_MBOX_INT_EN_n_RMSK) +#define HWIO_IPA_UC_MBOX_INT_EN_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_UC_MBOX_INT_EN_n_ADDR(n), mask) +#define HWIO_IPA_UC_MBOX_INT_EN_n_OUTI(n,val) \ + out_dword(HWIO_IPA_UC_MBOX_INT_EN_n_ADDR(n),val) +#define HWIO_IPA_UC_MBOX_INT_EN_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_UC_MBOX_INT_EN_n_ADDR(n),mask,val,HWIO_IPA_UC_MBOX_INT_EN_n_INI(n)) +#define HWIO_IPA_UC_MBOX_INT_EN_n_IRQ_EN_BMSK 0xffff +#define HWIO_IPA_UC_MBOX_INT_EN_n_IRQ_EN_SHFT 0x0 + +#define HWIO_IPA_UC_MBOX_INT_CLR_n_ADDR(n) (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000208 + 0x10 * (n)) +#define HWIO_IPA_UC_MBOX_INT_CLR_n_PHYS(n) (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000208 + 0x10 * (n)) +#define HWIO_IPA_UC_MBOX_INT_CLR_n_OFFS(n) (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000208 + 0x10 * (n)) +#define HWIO_IPA_UC_MBOX_INT_CLR_n_RMSK 0xffff +#define HWIO_IPA_UC_MBOX_INT_CLR_n_MAXn 7 +#define HWIO_IPA_UC_MBOX_INT_CLR_n_ATTR 0x0 +#define HWIO_IPA_UC_MBOX_INT_CLR_n_OUTI(n,val) \ + out_dword(HWIO_IPA_UC_MBOX_INT_CLR_n_ADDR(n),val) +#define HWIO_IPA_UC_MBOX_INT_CLR_n_IRQ_CLR_BMSK 0xffff +#define HWIO_IPA_UC_MBOX_INT_CLR_n_IRQ_CLR_SHFT 0x0 + +#define HWIO_IPA_UC_IPA_INT_STTS_n_ADDR(n) (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000300 + 0x10 * (n)) +#define HWIO_IPA_UC_IPA_INT_STTS_n_PHYS(n) (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000300 + 0x10 * (n)) +#define HWIO_IPA_UC_IPA_INT_STTS_n_OFFS(n) (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000300 + 0x10 * (n)) +#define HWIO_IPA_UC_IPA_INT_STTS_n_RMSK 0xf +#define HWIO_IPA_UC_IPA_INT_STTS_n_MAXn 3 +#define HWIO_IPA_UC_IPA_INT_STTS_n_ATTR 0x1 +#define HWIO_IPA_UC_IPA_INT_STTS_n_INI(n) \ + in_dword_masked(HWIO_IPA_UC_IPA_INT_STTS_n_ADDR(n), HWIO_IPA_UC_IPA_INT_STTS_n_RMSK) +#define HWIO_IPA_UC_IPA_INT_STTS_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_UC_IPA_INT_STTS_n_ADDR(n), mask) +#define HWIO_IPA_UC_IPA_INT_STTS_n_IRQ_STATUS_BMSK 0xf +#define HWIO_IPA_UC_IPA_INT_STTS_n_IRQ_STATUS_SHFT 0x0 + +#define HWIO_IPA_UC_IPA_INT_EN_n_ADDR(n) (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000304 + 0x10 * (n)) +#define HWIO_IPA_UC_IPA_INT_EN_n_PHYS(n) (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000304 + 0x10 * (n)) +#define HWIO_IPA_UC_IPA_INT_EN_n_OFFS(n) (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000304 + 0x10 * (n)) +#define HWIO_IPA_UC_IPA_INT_EN_n_RMSK 0xf +#define HWIO_IPA_UC_IPA_INT_EN_n_MAXn 3 +#define HWIO_IPA_UC_IPA_INT_EN_n_ATTR 0x3 +#define HWIO_IPA_UC_IPA_INT_EN_n_INI(n) \ + in_dword_masked(HWIO_IPA_UC_IPA_INT_EN_n_ADDR(n), HWIO_IPA_UC_IPA_INT_EN_n_RMSK) +#define HWIO_IPA_UC_IPA_INT_EN_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_UC_IPA_INT_EN_n_ADDR(n), mask) +#define HWIO_IPA_UC_IPA_INT_EN_n_OUTI(n,val) \ + out_dword(HWIO_IPA_UC_IPA_INT_EN_n_ADDR(n),val) +#define HWIO_IPA_UC_IPA_INT_EN_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_UC_IPA_INT_EN_n_ADDR(n),mask,val,HWIO_IPA_UC_IPA_INT_EN_n_INI(n)) +#define HWIO_IPA_UC_IPA_INT_EN_n_IRQ_EN_BMSK 0xf +#define HWIO_IPA_UC_IPA_INT_EN_n_IRQ_EN_SHFT 0x0 + +#define HWIO_IPA_UC_IPA_INT_CLR_n_ADDR(n) (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000308 + 0x10 * (n)) +#define HWIO_IPA_UC_IPA_INT_CLR_n_PHYS(n) (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000308 + 0x10 * (n)) +#define HWIO_IPA_UC_IPA_INT_CLR_n_OFFS(n) (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000308 + 0x10 * (n)) +#define HWIO_IPA_UC_IPA_INT_CLR_n_RMSK 0xf +#define HWIO_IPA_UC_IPA_INT_CLR_n_MAXn 3 +#define HWIO_IPA_UC_IPA_INT_CLR_n_ATTR 0x0 +#define HWIO_IPA_UC_IPA_INT_CLR_n_OUTI(n,val) \ + out_dword(HWIO_IPA_UC_IPA_INT_CLR_n_ADDR(n),val) +#define HWIO_IPA_UC_IPA_INT_CLR_n_IRQ_CLR_BMSK 0xf +#define HWIO_IPA_UC_IPA_INT_CLR_n_IRQ_CLR_SHFT 0x0 + +#define HWIO_IPA_UC_HWEV_INT_STTS_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000400) +#define HWIO_IPA_UC_HWEV_INT_STTS_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000400) +#define HWIO_IPA_UC_HWEV_INT_STTS_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000400) +#define HWIO_IPA_UC_HWEV_INT_STTS_RMSK 0xffffffff +#define HWIO_IPA_UC_HWEV_INT_STTS_ATTR 0x1 +#define HWIO_IPA_UC_HWEV_INT_STTS_IN \ + in_dword_masked(HWIO_IPA_UC_HWEV_INT_STTS_ADDR, HWIO_IPA_UC_HWEV_INT_STTS_RMSK) +#define HWIO_IPA_UC_HWEV_INT_STTS_INM(m) \ + in_dword_masked(HWIO_IPA_UC_HWEV_INT_STTS_ADDR, m) +#define HWIO_IPA_UC_HWEV_INT_STTS_IRQ_STATUS_BMSK 0xffffffff +#define HWIO_IPA_UC_HWEV_INT_STTS_IRQ_STATUS_SHFT 0x0 + +#define HWIO_IPA_UC_HWEV_INT_EN_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000404) +#define HWIO_IPA_UC_HWEV_INT_EN_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000404) +#define HWIO_IPA_UC_HWEV_INT_EN_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000404) +#define HWIO_IPA_UC_HWEV_INT_EN_RMSK 0xffffffff +#define HWIO_IPA_UC_HWEV_INT_EN_ATTR 0x3 +#define HWIO_IPA_UC_HWEV_INT_EN_IN \ + in_dword_masked(HWIO_IPA_UC_HWEV_INT_EN_ADDR, HWIO_IPA_UC_HWEV_INT_EN_RMSK) +#define HWIO_IPA_UC_HWEV_INT_EN_INM(m) \ + in_dword_masked(HWIO_IPA_UC_HWEV_INT_EN_ADDR, m) +#define HWIO_IPA_UC_HWEV_INT_EN_OUT(v) \ + out_dword(HWIO_IPA_UC_HWEV_INT_EN_ADDR,v) +#define HWIO_IPA_UC_HWEV_INT_EN_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_HWEV_INT_EN_ADDR,m,v,HWIO_IPA_UC_HWEV_INT_EN_IN) +#define HWIO_IPA_UC_HWEV_INT_EN_IRQ_EN_BMSK 0xffffffff +#define HWIO_IPA_UC_HWEV_INT_EN_IRQ_EN_SHFT 0x0 + +#define HWIO_IPA_UC_HWEV_INT_CLR_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000408) +#define HWIO_IPA_UC_HWEV_INT_CLR_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000408) +#define HWIO_IPA_UC_HWEV_INT_CLR_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000408) +#define HWIO_IPA_UC_HWEV_INT_CLR_RMSK 0xffffffff +#define HWIO_IPA_UC_HWEV_INT_CLR_ATTR 0x0 +#define HWIO_IPA_UC_HWEV_INT_CLR_OUT(v) \ + out_dword(HWIO_IPA_UC_HWEV_INT_CLR_ADDR,v) +#define HWIO_IPA_UC_HWEV_INT_CLR_IRQ_CLR_BMSK 0xffffffff +#define HWIO_IPA_UC_HWEV_INT_CLR_IRQ_CLR_SHFT 0x0 + +#define HWIO_IPA_UC_SWEV_INT_STTS_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000410) +#define HWIO_IPA_UC_SWEV_INT_STTS_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000410) +#define HWIO_IPA_UC_SWEV_INT_STTS_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000410) +#define HWIO_IPA_UC_SWEV_INT_STTS_RMSK 0xffffffff +#define HWIO_IPA_UC_SWEV_INT_STTS_ATTR 0x1 +#define HWIO_IPA_UC_SWEV_INT_STTS_IN \ + in_dword_masked(HWIO_IPA_UC_SWEV_INT_STTS_ADDR, HWIO_IPA_UC_SWEV_INT_STTS_RMSK) +#define HWIO_IPA_UC_SWEV_INT_STTS_INM(m) \ + in_dword_masked(HWIO_IPA_UC_SWEV_INT_STTS_ADDR, m) +#define HWIO_IPA_UC_SWEV_INT_STTS_IRQ_STATUS_BMSK 0xffffffff +#define HWIO_IPA_UC_SWEV_INT_STTS_IRQ_STATUS_SHFT 0x0 + +#define HWIO_IPA_UC_SWEV_INT_EN_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000414) +#define HWIO_IPA_UC_SWEV_INT_EN_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000414) +#define HWIO_IPA_UC_SWEV_INT_EN_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000414) +#define HWIO_IPA_UC_SWEV_INT_EN_RMSK 0xffffffff +#define HWIO_IPA_UC_SWEV_INT_EN_ATTR 0x3 +#define HWIO_IPA_UC_SWEV_INT_EN_IN \ + in_dword_masked(HWIO_IPA_UC_SWEV_INT_EN_ADDR, HWIO_IPA_UC_SWEV_INT_EN_RMSK) +#define HWIO_IPA_UC_SWEV_INT_EN_INM(m) \ + in_dword_masked(HWIO_IPA_UC_SWEV_INT_EN_ADDR, m) +#define HWIO_IPA_UC_SWEV_INT_EN_OUT(v) \ + out_dword(HWIO_IPA_UC_SWEV_INT_EN_ADDR,v) +#define HWIO_IPA_UC_SWEV_INT_EN_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_SWEV_INT_EN_ADDR,m,v,HWIO_IPA_UC_SWEV_INT_EN_IN) +#define HWIO_IPA_UC_SWEV_INT_EN_IRQ_EN_BMSK 0xffffffff +#define HWIO_IPA_UC_SWEV_INT_EN_IRQ_EN_SHFT 0x0 + +#define HWIO_IPA_UC_SWEV_INT_CLR_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000418) +#define HWIO_IPA_UC_SWEV_INT_CLR_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000418) +#define HWIO_IPA_UC_SWEV_INT_CLR_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000418) +#define HWIO_IPA_UC_SWEV_INT_CLR_RMSK 0xffffffff +#define HWIO_IPA_UC_SWEV_INT_CLR_ATTR 0x0 +#define HWIO_IPA_UC_SWEV_INT_CLR_OUT(v) \ + out_dword(HWIO_IPA_UC_SWEV_INT_CLR_ADDR,v) +#define HWIO_IPA_UC_SWEV_INT_CLR_IRQ_CLR_BMSK 0xffffffff +#define HWIO_IPA_UC_SWEV_INT_CLR_IRQ_CLR_SHFT 0x0 + +#define HWIO_IPA_UC_VUIC_INT_STTS_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x0000041c) +#define HWIO_IPA_UC_VUIC_INT_STTS_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x0000041c) +#define HWIO_IPA_UC_VUIC_INT_STTS_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x0000041c) +#define HWIO_IPA_UC_VUIC_INT_STTS_RMSK 0x1 +#define HWIO_IPA_UC_VUIC_INT_STTS_ATTR 0x1 +#define HWIO_IPA_UC_VUIC_INT_STTS_IN \ + in_dword_masked(HWIO_IPA_UC_VUIC_INT_STTS_ADDR, HWIO_IPA_UC_VUIC_INT_STTS_RMSK) +#define HWIO_IPA_UC_VUIC_INT_STTS_INM(m) \ + in_dword_masked(HWIO_IPA_UC_VUIC_INT_STTS_ADDR, m) +#define HWIO_IPA_UC_VUIC_INT_STTS_IRQ_STATUS_BMSK 0x1 +#define HWIO_IPA_UC_VUIC_INT_STTS_IRQ_STATUS_SHFT 0x0 + +#define HWIO_IPA_UC_VUIC_INT_CLR_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000420) +#define HWIO_IPA_UC_VUIC_INT_CLR_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000420) +#define HWIO_IPA_UC_VUIC_INT_CLR_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000420) +#define HWIO_IPA_UC_VUIC_INT_CLR_RMSK 0x1 +#define HWIO_IPA_UC_VUIC_INT_CLR_ATTR 0x0 +#define HWIO_IPA_UC_VUIC_INT_CLR_OUT(v) \ + out_dword(HWIO_IPA_UC_VUIC_INT_CLR_ADDR,v) +#define HWIO_IPA_UC_VUIC_INT_CLR_IRQ_CLR_BMSK 0x1 +#define HWIO_IPA_UC_VUIC_INT_CLR_IRQ_CLR_SHFT 0x0 + +#define HWIO_IPA_UC_TIMER_CTRL_n_ADDR(n) (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000500 + 0x10 * (n)) +#define HWIO_IPA_UC_TIMER_CTRL_n_PHYS(n) (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000500 + 0x10 * (n)) +#define HWIO_IPA_UC_TIMER_CTRL_n_OFFS(n) (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000500 + 0x10 * (n)) +#define HWIO_IPA_UC_TIMER_CTRL_n_RMSK 0xc17fffff +#define HWIO_IPA_UC_TIMER_CTRL_n_MAXn 3 +#define HWIO_IPA_UC_TIMER_CTRL_n_ATTR 0x3 +#define HWIO_IPA_UC_TIMER_CTRL_n_INI(n) \ + in_dword_masked(HWIO_IPA_UC_TIMER_CTRL_n_ADDR(n), HWIO_IPA_UC_TIMER_CTRL_n_RMSK) +#define HWIO_IPA_UC_TIMER_CTRL_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_UC_TIMER_CTRL_n_ADDR(n), mask) +#define HWIO_IPA_UC_TIMER_CTRL_n_OUTI(n,val) \ + out_dword(HWIO_IPA_UC_TIMER_CTRL_n_ADDR(n),val) +#define HWIO_IPA_UC_TIMER_CTRL_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_UC_TIMER_CTRL_n_ADDR(n),mask,val,HWIO_IPA_UC_TIMER_CTRL_n_INI(n)) +#define HWIO_IPA_UC_TIMER_CTRL_n_GRAN_SEL_BMSK 0xc0000000 +#define HWIO_IPA_UC_TIMER_CTRL_n_GRAN_SEL_SHFT 0x1e +#define HWIO_IPA_UC_TIMER_CTRL_n_RETRIG_BMSK 0x1000000 +#define HWIO_IPA_UC_TIMER_CTRL_n_RETRIG_SHFT 0x18 +#define HWIO_IPA_UC_TIMER_CTRL_n_RETRIG_ONE_SHOT_FVAL 0x0 +#define HWIO_IPA_UC_TIMER_CTRL_n_RETRIG_RETRIG_FVAL 0x1 +#define HWIO_IPA_UC_TIMER_CTRL_n_EVENT_SEL_BMSK 0x7f0000 +#define HWIO_IPA_UC_TIMER_CTRL_n_EVENT_SEL_SHFT 0x10 +#define HWIO_IPA_UC_TIMER_CTRL_n_COUNT_BMSK 0xffff +#define HWIO_IPA_UC_TIMER_CTRL_n_COUNT_SHFT 0x0 + +#define HWIO_IPA_UC_TIMER_STATUS_n_ADDR(n) (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000508 + 0x10 * (n)) +#define HWIO_IPA_UC_TIMER_STATUS_n_PHYS(n) (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000508 + 0x10 * (n)) +#define HWIO_IPA_UC_TIMER_STATUS_n_OFFS(n) (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000508 + 0x10 * (n)) +#define HWIO_IPA_UC_TIMER_STATUS_n_RMSK 0x100ffff +#define HWIO_IPA_UC_TIMER_STATUS_n_MAXn 3 +#define HWIO_IPA_UC_TIMER_STATUS_n_ATTR 0x1 +#define HWIO_IPA_UC_TIMER_STATUS_n_INI(n) \ + in_dword_masked(HWIO_IPA_UC_TIMER_STATUS_n_ADDR(n), HWIO_IPA_UC_TIMER_STATUS_n_RMSK) +#define HWIO_IPA_UC_TIMER_STATUS_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_UC_TIMER_STATUS_n_ADDR(n), mask) +#define HWIO_IPA_UC_TIMER_STATUS_n_ACTIVE_BMSK 0x1000000 +#define HWIO_IPA_UC_TIMER_STATUS_n_ACTIVE_SHFT 0x18 +#define HWIO_IPA_UC_TIMER_STATUS_n_COUNT_BMSK 0xffff +#define HWIO_IPA_UC_TIMER_STATUS_n_COUNT_SHFT 0x0 + +#define HWIO_IPA_UC_EVENTS_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000600) +#define HWIO_IPA_UC_EVENTS_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000600) +#define HWIO_IPA_UC_EVENTS_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000600) +#define HWIO_IPA_UC_EVENTS_RMSK 0xffffffff +#define HWIO_IPA_UC_EVENTS_ATTR 0x2 +#define HWIO_IPA_UC_EVENTS_OUT(v) \ + out_dword(HWIO_IPA_UC_EVENTS_ADDR,v) +#define HWIO_IPA_UC_EVENTS_EVENTS_BMSK 0xffffffff +#define HWIO_IPA_UC_EVENTS_EVENTS_SHFT 0x0 + +#define HWIO_IPA_UC_VUIC_BUS_ADDR_TRANSLATE_EN_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000710) +#define HWIO_IPA_UC_VUIC_BUS_ADDR_TRANSLATE_EN_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000710) +#define HWIO_IPA_UC_VUIC_BUS_ADDR_TRANSLATE_EN_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000710) +#define HWIO_IPA_UC_VUIC_BUS_ADDR_TRANSLATE_EN_RMSK 0x3 +#define HWIO_IPA_UC_VUIC_BUS_ADDR_TRANSLATE_EN_ATTR 0x3 +#define HWIO_IPA_UC_VUIC_BUS_ADDR_TRANSLATE_EN_IN \ + in_dword_masked(HWIO_IPA_UC_VUIC_BUS_ADDR_TRANSLATE_EN_ADDR, HWIO_IPA_UC_VUIC_BUS_ADDR_TRANSLATE_EN_RMSK) +#define HWIO_IPA_UC_VUIC_BUS_ADDR_TRANSLATE_EN_INM(m) \ + in_dword_masked(HWIO_IPA_UC_VUIC_BUS_ADDR_TRANSLATE_EN_ADDR, m) +#define HWIO_IPA_UC_VUIC_BUS_ADDR_TRANSLATE_EN_OUT(v) \ + out_dword(HWIO_IPA_UC_VUIC_BUS_ADDR_TRANSLATE_EN_ADDR,v) +#define HWIO_IPA_UC_VUIC_BUS_ADDR_TRANSLATE_EN_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_VUIC_BUS_ADDR_TRANSLATE_EN_ADDR,m,v,HWIO_IPA_UC_VUIC_BUS_ADDR_TRANSLATE_EN_IN) +#define HWIO_IPA_UC_VUIC_BUS_ADDR_TRANSLATE_EN_DIRECT_ADDR_TRANSLATE_BMSK 0x2 +#define HWIO_IPA_UC_VUIC_BUS_ADDR_TRANSLATE_EN_DIRECT_ADDR_TRANSLATE_SHFT 0x1 +#define HWIO_IPA_UC_VUIC_BUS_ADDR_TRANSLATE_EN_QMB_ADDR_TRANSLATE_BMSK 0x1 +#define HWIO_IPA_UC_VUIC_BUS_ADDR_TRANSLATE_EN_QMB_ADDR_TRANSLATE_SHFT 0x0 + +#define HWIO_IPA_UC_SYS_ADDR_MSB_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000714) +#define HWIO_IPA_UC_SYS_ADDR_MSB_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000714) +#define HWIO_IPA_UC_SYS_ADDR_MSB_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000714) +#define HWIO_IPA_UC_SYS_ADDR_MSB_RMSK 0xffffffff +#define HWIO_IPA_UC_SYS_ADDR_MSB_ATTR 0x3 +#define HWIO_IPA_UC_SYS_ADDR_MSB_IN \ + in_dword_masked(HWIO_IPA_UC_SYS_ADDR_MSB_ADDR, HWIO_IPA_UC_SYS_ADDR_MSB_RMSK) +#define HWIO_IPA_UC_SYS_ADDR_MSB_INM(m) \ + in_dword_masked(HWIO_IPA_UC_SYS_ADDR_MSB_ADDR, m) +#define HWIO_IPA_UC_SYS_ADDR_MSB_OUT(v) \ + out_dword(HWIO_IPA_UC_SYS_ADDR_MSB_ADDR,v) +#define HWIO_IPA_UC_SYS_ADDR_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_SYS_ADDR_MSB_ADDR,m,v,HWIO_IPA_UC_SYS_ADDR_MSB_IN) +#define HWIO_IPA_UC_SYS_ADDR_MSB_SYS_ADDR_MSB_BMSK 0xffffffff +#define HWIO_IPA_UC_SYS_ADDR_MSB_SYS_ADDR_MSB_SHFT 0x0 + +#define HWIO_IPA_UC_PC_RESTORE_WR_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000718) +#define HWIO_IPA_UC_PC_RESTORE_WR_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000718) +#define HWIO_IPA_UC_PC_RESTORE_WR_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000718) +#define HWIO_IPA_UC_PC_RESTORE_WR_RMSK 0xf +#define HWIO_IPA_UC_PC_RESTORE_WR_ATTR 0x2 +#define HWIO_IPA_UC_PC_RESTORE_WR_OUT(v) \ + out_dword(HWIO_IPA_UC_PC_RESTORE_WR_ADDR,v) +#define HWIO_IPA_UC_PC_RESTORE_WR_CLEAR_IPA_RESTORE_ACK_BMSK 0x8 +#define HWIO_IPA_UC_PC_RESTORE_WR_CLEAR_IPA_RESTORE_ACK_SHFT 0x3 +#define HWIO_IPA_UC_PC_RESTORE_WR_SET_IPA_RESTORE_ACK_BMSK 0x4 +#define HWIO_IPA_UC_PC_RESTORE_WR_SET_IPA_RESTORE_ACK_SHFT 0x2 +#define HWIO_IPA_UC_PC_RESTORE_WR_CLEAR_IPA_PC_ACK_BMSK 0x2 +#define HWIO_IPA_UC_PC_RESTORE_WR_CLEAR_IPA_PC_ACK_SHFT 0x1 +#define HWIO_IPA_UC_PC_RESTORE_WR_SET_IPA_PC_ACK_BMSK 0x1 +#define HWIO_IPA_UC_PC_RESTORE_WR_SET_IPA_PC_ACK_SHFT 0x0 + +#define HWIO_IPA_UC_PC_RESTORE_RD_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x0000071c) +#define HWIO_IPA_UC_PC_RESTORE_RD_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x0000071c) +#define HWIO_IPA_UC_PC_RESTORE_RD_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x0000071c) +#define HWIO_IPA_UC_PC_RESTORE_RD_RMSK 0xf +#define HWIO_IPA_UC_PC_RESTORE_RD_ATTR 0x1 +#define HWIO_IPA_UC_PC_RESTORE_RD_IN \ + in_dword_masked(HWIO_IPA_UC_PC_RESTORE_RD_ADDR, HWIO_IPA_UC_PC_RESTORE_RD_RMSK) +#define HWIO_IPA_UC_PC_RESTORE_RD_INM(m) \ + in_dword_masked(HWIO_IPA_UC_PC_RESTORE_RD_ADDR, m) +#define HWIO_IPA_UC_PC_RESTORE_RD_IPA_RESTORE_ACK_BMSK 0x8 +#define HWIO_IPA_UC_PC_RESTORE_RD_IPA_RESTORE_ACK_SHFT 0x3 +#define HWIO_IPA_UC_PC_RESTORE_RD_IPA_RESTORE_REQ_BMSK 0x4 +#define HWIO_IPA_UC_PC_RESTORE_RD_IPA_RESTORE_REQ_SHFT 0x2 +#define HWIO_IPA_UC_PC_RESTORE_RD_IPA_PC_ACK_BMSK 0x2 +#define HWIO_IPA_UC_PC_RESTORE_RD_IPA_PC_ACK_SHFT 0x1 +#define HWIO_IPA_UC_PC_RESTORE_RD_IPA_PC_REQ_BMSK 0x1 +#define HWIO_IPA_UC_PC_RESTORE_RD_IPA_PC_REQ_SHFT 0x0 + +#define HWIO_IPA_UC_CNT_GLOBAL_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000800) +#define HWIO_IPA_UC_CNT_GLOBAL_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000800) +#define HWIO_IPA_UC_CNT_GLOBAL_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000800) +#define HWIO_IPA_UC_CNT_GLOBAL_RMSK 0x80000003 +#define HWIO_IPA_UC_CNT_GLOBAL_ATTR 0x0 +#define HWIO_IPA_UC_CNT_GLOBAL_IN \ + in_dword_masked(HWIO_IPA_UC_CNT_GLOBAL_ADDR, HWIO_IPA_UC_CNT_GLOBAL_RMSK) +#define HWIO_IPA_UC_CNT_GLOBAL_INM(m) \ + in_dword_masked(HWIO_IPA_UC_CNT_GLOBAL_ADDR, m) +#define HWIO_IPA_UC_CNT_GLOBAL_OUT(v) \ + out_dword(HWIO_IPA_UC_CNT_GLOBAL_ADDR,v) +#define HWIO_IPA_UC_CNT_GLOBAL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_CNT_GLOBAL_ADDR,m,v,HWIO_IPA_UC_CNT_GLOBAL_IN) +#define HWIO_IPA_UC_CNT_GLOBAL_CLEAR_ALL_BMSK 0x80000000 +#define HWIO_IPA_UC_CNT_GLOBAL_CLEAR_ALL_SHFT 0x1f +#define HWIO_IPA_UC_CNT_GLOBAL_COUNT_CGC_OPEN_BMSK 0x2 +#define HWIO_IPA_UC_CNT_GLOBAL_COUNT_CGC_OPEN_SHFT 0x1 +#define HWIO_IPA_UC_CNT_GLOBAL_COUNT_EN_BMSK 0x1 +#define HWIO_IPA_UC_CNT_GLOBAL_COUNT_EN_SHFT 0x0 + +#define HWIO_IPA_UC_CNT_CTL_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000804) +#define HWIO_IPA_UC_CNT_CTL_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000804) +#define HWIO_IPA_UC_CNT_CTL_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000804) +#define HWIO_IPA_UC_CNT_CTL_RMSK 0xff755 +#define HWIO_IPA_UC_CNT_CTL_ATTR 0x0 +#define HWIO_IPA_UC_CNT_CTL_IN \ + in_dword_masked(HWIO_IPA_UC_CNT_CTL_ADDR, HWIO_IPA_UC_CNT_CTL_RMSK) +#define HWIO_IPA_UC_CNT_CTL_INM(m) \ + in_dword_masked(HWIO_IPA_UC_CNT_CTL_ADDR, m) +#define HWIO_IPA_UC_CNT_CTL_OUT(v) \ + out_dword(HWIO_IPA_UC_CNT_CTL_ADDR,v) +#define HWIO_IPA_UC_CNT_CTL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_CNT_CTL_ADDR,m,v,HWIO_IPA_UC_CNT_CTL_IN) +#define HWIO_IPA_UC_CNT_CTL_DRAM_CNT_CLR_BMSK 0x80000 +#define HWIO_IPA_UC_CNT_CTL_DRAM_CNT_CLR_SHFT 0x13 +#define HWIO_IPA_UC_CNT_CTL_DRAM_CLR_AFTER_RD_BMSK 0x40000 +#define HWIO_IPA_UC_CNT_CTL_DRAM_CLR_AFTER_RD_SHFT 0x12 +#define HWIO_IPA_UC_CNT_CTL_DRAM_WR_CNT_EN_BMSK 0x20000 +#define HWIO_IPA_UC_CNT_CTL_DRAM_WR_CNT_EN_SHFT 0x11 +#define HWIO_IPA_UC_CNT_CTL_DRAM_RD_CNT_EN_BMSK 0x10000 +#define HWIO_IPA_UC_CNT_CTL_DRAM_RD_CNT_EN_SHFT 0x10 +#define HWIO_IPA_UC_CNT_CTL_VUIC_CNT_CLR_BMSK 0x8000 +#define HWIO_IPA_UC_CNT_CTL_VUIC_CNT_CLR_SHFT 0xf +#define HWIO_IPA_UC_CNT_CTL_VUIC_CLR_AFTER_RD_BMSK 0x4000 +#define HWIO_IPA_UC_CNT_CTL_VUIC_CLR_AFTER_RD_SHFT 0xe +#define HWIO_IPA_UC_CNT_CTL_VUIC_WR_CNT_EN_BMSK 0x2000 +#define HWIO_IPA_UC_CNT_CTL_VUIC_WR_CNT_EN_SHFT 0xd +#define HWIO_IPA_UC_CNT_CTL_VUIC_RD_CNT_EN_BMSK 0x1000 +#define HWIO_IPA_UC_CNT_CTL_VUIC_RD_CNT_EN_SHFT 0xc +#define HWIO_IPA_UC_CNT_CTL_INST_CNT_CLR_BMSK 0x400 +#define HWIO_IPA_UC_CNT_CTL_INST_CNT_CLR_SHFT 0xa +#define HWIO_IPA_UC_CNT_CTL_INST_CLR_AFTER_RD_BMSK 0x200 +#define HWIO_IPA_UC_CNT_CTL_INST_CLR_AFTER_RD_SHFT 0x9 +#define HWIO_IPA_UC_CNT_CTL_INST_CNT_EN_BMSK 0x100 +#define HWIO_IPA_UC_CNT_CTL_INST_CNT_EN_SHFT 0x8 +#define HWIO_IPA_UC_CNT_CTL_IDLE_CNT_CLR_BMSK 0x40 +#define HWIO_IPA_UC_CNT_CTL_IDLE_CNT_CLR_SHFT 0x6 +#define HWIO_IPA_UC_CNT_CTL_IDLE_CNT_EN_BMSK 0x10 +#define HWIO_IPA_UC_CNT_CTL_IDLE_CNT_EN_SHFT 0x4 +#define HWIO_IPA_UC_CNT_CTL_CYCLE_CNT_CLR_BMSK 0x4 +#define HWIO_IPA_UC_CNT_CTL_CYCLE_CNT_CLR_SHFT 0x2 +#define HWIO_IPA_UC_CNT_CTL_CYCLE_CNT_EN_BMSK 0x1 +#define HWIO_IPA_UC_CNT_CTL_CYCLE_CNT_EN_SHFT 0x0 + +#define HWIO_IPA_UC_CNT_CLK_CYCLE_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000808) +#define HWIO_IPA_UC_CNT_CLK_CYCLE_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000808) +#define HWIO_IPA_UC_CNT_CLK_CYCLE_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000808) +#define HWIO_IPA_UC_CNT_CLK_CYCLE_RMSK 0xffffffff +#define HWIO_IPA_UC_CNT_CLK_CYCLE_ATTR 0x1 +#define HWIO_IPA_UC_CNT_CLK_CYCLE_IN \ + in_dword_masked(HWIO_IPA_UC_CNT_CLK_CYCLE_ADDR, HWIO_IPA_UC_CNT_CLK_CYCLE_RMSK) +#define HWIO_IPA_UC_CNT_CLK_CYCLE_INM(m) \ + in_dword_masked(HWIO_IPA_UC_CNT_CLK_CYCLE_ADDR, m) +#define HWIO_IPA_UC_CNT_CLK_CYCLE_COUNTER_BMSK 0xffffffff +#define HWIO_IPA_UC_CNT_CLK_CYCLE_COUNTER_SHFT 0x0 + +#define HWIO_IPA_UC_CNT_CLK_CYCLE_MSB_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x0000080c) +#define HWIO_IPA_UC_CNT_CLK_CYCLE_MSB_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x0000080c) +#define HWIO_IPA_UC_CNT_CLK_CYCLE_MSB_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x0000080c) +#define HWIO_IPA_UC_CNT_CLK_CYCLE_MSB_RMSK 0xff +#define HWIO_IPA_UC_CNT_CLK_CYCLE_MSB_ATTR 0x1 +#define HWIO_IPA_UC_CNT_CLK_CYCLE_MSB_IN \ + in_dword_masked(HWIO_IPA_UC_CNT_CLK_CYCLE_MSB_ADDR, HWIO_IPA_UC_CNT_CLK_CYCLE_MSB_RMSK) +#define HWIO_IPA_UC_CNT_CLK_CYCLE_MSB_INM(m) \ + in_dword_masked(HWIO_IPA_UC_CNT_CLK_CYCLE_MSB_ADDR, m) +#define HWIO_IPA_UC_CNT_CLK_CYCLE_MSB_COUNTER_BMSK 0xff +#define HWIO_IPA_UC_CNT_CLK_CYCLE_MSB_COUNTER_SHFT 0x0 + +#define HWIO_IPA_UC_CNT_IDLE_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000810) +#define HWIO_IPA_UC_CNT_IDLE_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000810) +#define HWIO_IPA_UC_CNT_IDLE_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000810) +#define HWIO_IPA_UC_CNT_IDLE_RMSK 0xffffffff +#define HWIO_IPA_UC_CNT_IDLE_ATTR 0x1 +#define HWIO_IPA_UC_CNT_IDLE_IN \ + in_dword_masked(HWIO_IPA_UC_CNT_IDLE_ADDR, HWIO_IPA_UC_CNT_IDLE_RMSK) +#define HWIO_IPA_UC_CNT_IDLE_INM(m) \ + in_dword_masked(HWIO_IPA_UC_CNT_IDLE_ADDR, m) +#define HWIO_IPA_UC_CNT_IDLE_COUNTER_BMSK 0xffffffff +#define HWIO_IPA_UC_CNT_IDLE_COUNTER_SHFT 0x0 + +#define HWIO_IPA_UC_CNT_IDLE_MSB_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000814) +#define HWIO_IPA_UC_CNT_IDLE_MSB_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000814) +#define HWIO_IPA_UC_CNT_IDLE_MSB_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000814) +#define HWIO_IPA_UC_CNT_IDLE_MSB_RMSK 0xff +#define HWIO_IPA_UC_CNT_IDLE_MSB_ATTR 0x1 +#define HWIO_IPA_UC_CNT_IDLE_MSB_IN \ + in_dword_masked(HWIO_IPA_UC_CNT_IDLE_MSB_ADDR, HWIO_IPA_UC_CNT_IDLE_MSB_RMSK) +#define HWIO_IPA_UC_CNT_IDLE_MSB_INM(m) \ + in_dword_masked(HWIO_IPA_UC_CNT_IDLE_MSB_ADDR, m) +#define HWIO_IPA_UC_CNT_IDLE_MSB_COUNTER_BMSK 0xff +#define HWIO_IPA_UC_CNT_IDLE_MSB_COUNTER_SHFT 0x0 + +#define HWIO_IPA_UC_CNT_INST_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000818) +#define HWIO_IPA_UC_CNT_INST_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000818) +#define HWIO_IPA_UC_CNT_INST_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000818) +#define HWIO_IPA_UC_CNT_INST_RMSK 0xffffffff +#define HWIO_IPA_UC_CNT_INST_ATTR 0x1 +#define HWIO_IPA_UC_CNT_INST_IN \ + in_dword_masked(HWIO_IPA_UC_CNT_INST_ADDR, HWIO_IPA_UC_CNT_INST_RMSK) +#define HWIO_IPA_UC_CNT_INST_INM(m) \ + in_dword_masked(HWIO_IPA_UC_CNT_INST_ADDR, m) +#define HWIO_IPA_UC_CNT_INST_COUNTER_BMSK 0xffffffff +#define HWIO_IPA_UC_CNT_INST_COUNTER_SHFT 0x0 + +#define HWIO_IPA_UC_CNT_DRAM_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x0000081c) +#define HWIO_IPA_UC_CNT_DRAM_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x0000081c) +#define HWIO_IPA_UC_CNT_DRAM_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x0000081c) +#define HWIO_IPA_UC_CNT_DRAM_RMSK 0xffffffff +#define HWIO_IPA_UC_CNT_DRAM_ATTR 0x1 +#define HWIO_IPA_UC_CNT_DRAM_IN \ + in_dword_masked(HWIO_IPA_UC_CNT_DRAM_ADDR, HWIO_IPA_UC_CNT_DRAM_RMSK) +#define HWIO_IPA_UC_CNT_DRAM_INM(m) \ + in_dword_masked(HWIO_IPA_UC_CNT_DRAM_ADDR, m) +#define HWIO_IPA_UC_CNT_DRAM_COUNTER_BMSK 0xffffffff +#define HWIO_IPA_UC_CNT_DRAM_COUNTER_SHFT 0x0 + +#define HWIO_IPA_UC_CNT_VUIC_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000820) +#define HWIO_IPA_UC_CNT_VUIC_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000820) +#define HWIO_IPA_UC_CNT_VUIC_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000820) +#define HWIO_IPA_UC_CNT_VUIC_RMSK 0xffffffff +#define HWIO_IPA_UC_CNT_VUIC_ATTR 0x1 +#define HWIO_IPA_UC_CNT_VUIC_IN \ + in_dword_masked(HWIO_IPA_UC_CNT_VUIC_ADDR, HWIO_IPA_UC_CNT_VUIC_RMSK) +#define HWIO_IPA_UC_CNT_VUIC_INM(m) \ + in_dword_masked(HWIO_IPA_UC_CNT_VUIC_ADDR, m) +#define HWIO_IPA_UC_CNT_VUIC_COUNTER_BMSK 0xffffffff +#define HWIO_IPA_UC_CNT_VUIC_COUNTER_SHFT 0x0 + +#define HWIO_IPA_UC_SPARE_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00001ffc) +#define HWIO_IPA_UC_SPARE_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00001ffc) +#define HWIO_IPA_UC_SPARE_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00001ffc) +#define HWIO_IPA_UC_SPARE_RMSK 0xffffffff +#define HWIO_IPA_UC_SPARE_ATTR 0x3 +#define HWIO_IPA_UC_SPARE_IN \ + in_dword_masked(HWIO_IPA_UC_SPARE_ADDR, HWIO_IPA_UC_SPARE_RMSK) +#define HWIO_IPA_UC_SPARE_INM(m) \ + in_dword_masked(HWIO_IPA_UC_SPARE_ADDR, m) +#define HWIO_IPA_UC_SPARE_OUT(v) \ + out_dword(HWIO_IPA_UC_SPARE_ADDR,v) +#define HWIO_IPA_UC_SPARE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_SPARE_ADDR,m,v,HWIO_IPA_UC_SPARE_IN) +#define HWIO_IPA_UC_SPARE_SPARE_BMSK 0xffffffff +#define HWIO_IPA_UC_SPARE_SPARE_SHFT 0x0 + +/*---------------------------------------------------------------------------- + * MODULE: IPA_UC_IPA_UC_MBOX + *--------------------------------------------------------------------------*/ + +#define IPA_UC_IPA_UC_MBOX_REG_BASE (IPA_0_IPA_WRAPPER_BASE + 0x001c2000) +#define IPA_UC_IPA_UC_MBOX_REG_BASE_PHYS (IPA_0_IPA_WRAPPER_BASE_PHYS + 0x001c2000) +#define IPA_UC_IPA_UC_MBOX_REG_BASE_OFFS 0x001c2000 + +#define HWIO_IPA_UC_MAILBOX_m_n_ADDR(m,n) (IPA_UC_IPA_UC_MBOX_REG_BASE + 0x00000000 + 0x80 * (m) + 0x4 * (n)) +#define HWIO_IPA_UC_MAILBOX_m_n_PHYS(m,n) (IPA_UC_IPA_UC_MBOX_REG_BASE_PHYS + 0x00000000 + 0x80 * (m) + 0x4 * (n)) +#define HWIO_IPA_UC_MAILBOX_m_n_OFFS(m,n) (IPA_UC_IPA_UC_MBOX_REG_BASE_OFFS + 0x00000000 + 0x80 * (m) + 0x4 * (n)) +#define HWIO_IPA_UC_MAILBOX_m_n_RMSK 0xffffffff +#define HWIO_IPA_UC_MAILBOX_m_n_MAXm 3 +#define HWIO_IPA_UC_MAILBOX_m_n_MAXn 31 +#define HWIO_IPA_UC_MAILBOX_m_n_ATTR 0x3 +#define HWIO_IPA_UC_MAILBOX_m_n_INI2(m,n) \ + in_dword_masked(HWIO_IPA_UC_MAILBOX_m_n_ADDR(m,n), HWIO_IPA_UC_MAILBOX_m_n_RMSK) +#define HWIO_IPA_UC_MAILBOX_m_n_INMI2(m,n,mask) \ + in_dword_masked(HWIO_IPA_UC_MAILBOX_m_n_ADDR(m,n), mask) +#define HWIO_IPA_UC_MAILBOX_m_n_OUTI2(m,n,val) \ + out_dword(HWIO_IPA_UC_MAILBOX_m_n_ADDR(m,n),val) +#define HWIO_IPA_UC_MAILBOX_m_n_OUTMI2(m,n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_UC_MAILBOX_m_n_ADDR(m,n),mask,val,HWIO_IPA_UC_MAILBOX_m_n_INI2(m,n)) +#define HWIO_IPA_UC_MAILBOX_m_n_DATA_BMSK 0xffffffff +#define HWIO_IPA_UC_MAILBOX_m_n_DATA_SHFT 0x0 + +/*---------------------------------------------------------------------------- + * MODULE: IPA_RAM + *--------------------------------------------------------------------------*/ + +#define IPA_RAM_REG_BASE (IPA_0_IPA_WRAPPER_BASE + 0x00150000) +#define IPA_RAM_REG_BASE_PHYS (IPA_0_IPA_WRAPPER_BASE_PHYS + 0x00150000) +#define IPA_RAM_REG_BASE_OFFS 0x00150000 + +#define HWIO_IPA_SW_AREA_RAM_DIRECT_ACCESS_n_ADDR(n) (IPA_RAM_REG_BASE + 0x00000000 + 0x4 * (n)) +#define HWIO_IPA_SW_AREA_RAM_DIRECT_ACCESS_n_PHYS(n) (IPA_RAM_REG_BASE_PHYS + 0x00000000 + 0x4 * (n)) +#define HWIO_IPA_SW_AREA_RAM_DIRECT_ACCESS_n_OFFS(n) (IPA_RAM_REG_BASE_OFFS + 0x00000000 + 0x4 * (n)) +#define HWIO_IPA_SW_AREA_RAM_DIRECT_ACCESS_n_RMSK 0xffffffff +#define HWIO_IPA_SW_AREA_RAM_DIRECT_ACCESS_n_MAXn 5119 +#define HWIO_IPA_SW_AREA_RAM_DIRECT_ACCESS_n_ATTR 0x3 +#define HWIO_IPA_SW_AREA_RAM_DIRECT_ACCESS_n_INI(n) \ + in_dword_masked(HWIO_IPA_SW_AREA_RAM_DIRECT_ACCESS_n_ADDR(n), HWIO_IPA_SW_AREA_RAM_DIRECT_ACCESS_n_RMSK) +#define HWIO_IPA_SW_AREA_RAM_DIRECT_ACCESS_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_SW_AREA_RAM_DIRECT_ACCESS_n_ADDR(n), mask) +#define HWIO_IPA_SW_AREA_RAM_DIRECT_ACCESS_n_OUTI(n,val) \ + out_dword(HWIO_IPA_SW_AREA_RAM_DIRECT_ACCESS_n_ADDR(n),val) +#define HWIO_IPA_SW_AREA_RAM_DIRECT_ACCESS_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_SW_AREA_RAM_DIRECT_ACCESS_n_ADDR(n),mask,val,HWIO_IPA_SW_AREA_RAM_DIRECT_ACCESS_n_INI(n)) +#define HWIO_IPA_SW_AREA_RAM_DIRECT_ACCESS_n_DATA_WORD_BMSK 0xffffffff +#define HWIO_IPA_SW_AREA_RAM_DIRECT_ACCESS_n_DATA_WORD_SHFT 0x0 + +#define HWIO_IPA_HW_AREA_RAM_DIRECT_ACCESS_n_ADDR(n) (IPA_RAM_REG_BASE + 0x00010000 + 0x4 * (n)) +#define HWIO_IPA_HW_AREA_RAM_DIRECT_ACCESS_n_PHYS(n) (IPA_RAM_REG_BASE_PHYS + 0x00010000 + 0x4 * (n)) +#define HWIO_IPA_HW_AREA_RAM_DIRECT_ACCESS_n_OFFS(n) (IPA_RAM_REG_BASE_OFFS + 0x00010000 + 0x4 * (n)) +#define HWIO_IPA_HW_AREA_RAM_DIRECT_ACCESS_n_RMSK 0xffffffff +#define HWIO_IPA_HW_AREA_RAM_DIRECT_ACCESS_n_MAXn 10307 +#define HWIO_IPA_HW_AREA_RAM_DIRECT_ACCESS_n_ATTR 0x3 +#define HWIO_IPA_HW_AREA_RAM_DIRECT_ACCESS_n_INI(n) \ + in_dword_masked(HWIO_IPA_HW_AREA_RAM_DIRECT_ACCESS_n_ADDR(n), HWIO_IPA_HW_AREA_RAM_DIRECT_ACCESS_n_RMSK) +#define HWIO_IPA_HW_AREA_RAM_DIRECT_ACCESS_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_HW_AREA_RAM_DIRECT_ACCESS_n_ADDR(n), mask) +#define HWIO_IPA_HW_AREA_RAM_DIRECT_ACCESS_n_OUTI(n,val) \ + out_dword(HWIO_IPA_HW_AREA_RAM_DIRECT_ACCESS_n_ADDR(n),val) +#define HWIO_IPA_HW_AREA_RAM_DIRECT_ACCESS_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_HW_AREA_RAM_DIRECT_ACCESS_n_ADDR(n),mask,val,HWIO_IPA_HW_AREA_RAM_DIRECT_ACCESS_n_INI(n)) +#define HWIO_IPA_HW_AREA_RAM_DIRECT_ACCESS_n_DATA_WORD_BMSK 0xffffffff +#define HWIO_IPA_HW_AREA_RAM_DIRECT_ACCESS_n_DATA_WORD_SHFT 0x0 + +/*---------------------------------------------------------------------------- + * MODULE: IPA_EE + *--------------------------------------------------------------------------*/ + +#define IPA_EE_REG_BASE (IPA_0_IPA_WRAPPER_BASE + 0x0014c000) +#define IPA_EE_REG_BASE_PHYS (IPA_0_IPA_WRAPPER_BASE_PHYS + 0x0014c000) +#define IPA_EE_REG_BASE_OFFS 0x0014c000 + +#define HWIO_IPA_IRQ_STTS_EE_n_ADDR(n) (IPA_EE_REG_BASE + 0x00000008 + 0x1000 * (n)) +#define HWIO_IPA_IRQ_STTS_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + 0x00000008 + 0x1000 * (n)) +#define HWIO_IPA_IRQ_STTS_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + 0x00000008 + 0x1000 * (n)) +#define HWIO_IPA_IRQ_STTS_EE_n_RMSK 0xc3bfc1fc +#define HWIO_IPA_IRQ_STTS_EE_n_MAXn 3 +#define HWIO_IPA_IRQ_STTS_EE_n_ATTR 0x1 +#define HWIO_IPA_IRQ_STTS_EE_n_INI(n) \ + in_dword_masked(HWIO_IPA_IRQ_STTS_EE_n_ADDR(n), HWIO_IPA_IRQ_STTS_EE_n_RMSK) +#define HWIO_IPA_IRQ_STTS_EE_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_IRQ_STTS_EE_n_ADDR(n), mask) +#define HWIO_IPA_IRQ_STTS_EE_n_IPA_ERROR_FATAL_IRQ_BMSK 0x80000000 +#define HWIO_IPA_IRQ_STTS_EE_n_IPA_ERROR_FATAL_IRQ_SHFT 0x1f +#define HWIO_IPA_IRQ_STTS_EE_n_IPA_ERROR_NON_FATAL_IRQ_BMSK 0x40000000 +#define HWIO_IPA_IRQ_STTS_EE_n_IPA_ERROR_NON_FATAL_IRQ_SHFT 0x1e +#define HWIO_IPA_IRQ_STTS_EE_n_GSI_UC_IRQ_BMSK 0x2000000 +#define HWIO_IPA_IRQ_STTS_EE_n_GSI_UC_IRQ_SHFT 0x19 +#define HWIO_IPA_IRQ_STTS_EE_n_GSI_IPA_IF_TLV_RCVD_IRQ_BMSK 0x1000000 +#define HWIO_IPA_IRQ_STTS_EE_n_GSI_IPA_IF_TLV_RCVD_IRQ_SHFT 0x18 +#define HWIO_IPA_IRQ_STTS_EE_n_GSI_EE_IRQ_BMSK 0x800000 +#define HWIO_IPA_IRQ_STTS_EE_n_GSI_EE_IRQ_SHFT 0x17 +#define HWIO_IPA_IRQ_STTS_EE_n_UCP_IRQ_BMSK 0x200000 +#define HWIO_IPA_IRQ_STTS_EE_n_UCP_IRQ_SHFT 0x15 +#define HWIO_IPA_IRQ_STTS_EE_n_PIPE_RED_MARKER_ABOVE_IRQ_BMSK 0x100000 +#define HWIO_IPA_IRQ_STTS_EE_n_PIPE_RED_MARKER_ABOVE_IRQ_SHFT 0x14 +#define HWIO_IPA_IRQ_STTS_EE_n_PIPE_YELLOW_MARKER_ABOVE_IRQ_BMSK 0x80000 +#define HWIO_IPA_IRQ_STTS_EE_n_PIPE_YELLOW_MARKER_ABOVE_IRQ_SHFT 0x13 +#define HWIO_IPA_IRQ_STTS_EE_n_PIPE_RED_MARKER_BELOW_IRQ_BMSK 0x40000 +#define HWIO_IPA_IRQ_STTS_EE_n_PIPE_RED_MARKER_BELOW_IRQ_SHFT 0x12 +#define HWIO_IPA_IRQ_STTS_EE_n_PIPE_YELLOW_MARKER_BELOW_IRQ_BMSK 0x20000 +#define HWIO_IPA_IRQ_STTS_EE_n_PIPE_YELLOW_MARKER_BELOW_IRQ_SHFT 0x11 +#define HWIO_IPA_IRQ_STTS_EE_n_GSI_IDLE_IRQ_BMSK 0x10000 +#define HWIO_IPA_IRQ_STTS_EE_n_GSI_IDLE_IRQ_SHFT 0x10 +#define HWIO_IPA_IRQ_STTS_EE_n_TX_HOLB_DROP_IRQ_BMSK 0x8000 +#define HWIO_IPA_IRQ_STTS_EE_n_TX_HOLB_DROP_IRQ_SHFT 0xf +#define HWIO_IPA_IRQ_STTS_EE_n_TX_SUSPEND_IRQ_BMSK 0x4000 +#define HWIO_IPA_IRQ_STTS_EE_n_TX_SUSPEND_IRQ_SHFT 0xe +#define HWIO_IPA_IRQ_STTS_EE_n_PROC_TO_UC_ACK_Q_NOT_EMPTY_IRQ_BMSK 0x100 +#define HWIO_IPA_IRQ_STTS_EE_n_PROC_TO_UC_ACK_Q_NOT_EMPTY_IRQ_SHFT 0x8 +#define HWIO_IPA_IRQ_STTS_EE_n_UC_RX_CMD_Q_NOT_FULL_IRQ_BMSK 0x80 +#define HWIO_IPA_IRQ_STTS_EE_n_UC_RX_CMD_Q_NOT_FULL_IRQ_SHFT 0x7 +#define HWIO_IPA_IRQ_STTS_EE_n_UC_IN_Q_NOT_EMPTY_IRQ_BMSK 0x40 +#define HWIO_IPA_IRQ_STTS_EE_n_UC_IN_Q_NOT_EMPTY_IRQ_SHFT 0x6 +#define HWIO_IPA_IRQ_STTS_EE_n_UC_IRQ_3_BMSK 0x20 +#define HWIO_IPA_IRQ_STTS_EE_n_UC_IRQ_3_SHFT 0x5 +#define HWIO_IPA_IRQ_STTS_EE_n_UC_IRQ_2_BMSK 0x10 +#define HWIO_IPA_IRQ_STTS_EE_n_UC_IRQ_2_SHFT 0x4 +#define HWIO_IPA_IRQ_STTS_EE_n_UC_IRQ_1_BMSK 0x8 +#define HWIO_IPA_IRQ_STTS_EE_n_UC_IRQ_1_SHFT 0x3 +#define HWIO_IPA_IRQ_STTS_EE_n_UC_IRQ_0_BMSK 0x4 +#define HWIO_IPA_IRQ_STTS_EE_n_UC_IRQ_0_SHFT 0x2 + +#define HWIO_IPA_IRQ_EN_EE_n_ADDR(n) (IPA_EE_REG_BASE + 0x0000000c + 0x1000 * (n)) +#define HWIO_IPA_IRQ_EN_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + 0x0000000c + 0x1000 * (n)) +#define HWIO_IPA_IRQ_EN_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + 0x0000000c + 0x1000 * (n)) +#define HWIO_IPA_IRQ_EN_EE_n_RMSK 0xc3bfc1fc +#define HWIO_IPA_IRQ_EN_EE_n_MAXn 3 +#define HWIO_IPA_IRQ_EN_EE_n_ATTR 0x3 +#define HWIO_IPA_IRQ_EN_EE_n_INI(n) \ + in_dword_masked(HWIO_IPA_IRQ_EN_EE_n_ADDR(n), HWIO_IPA_IRQ_EN_EE_n_RMSK) +#define HWIO_IPA_IRQ_EN_EE_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_IRQ_EN_EE_n_ADDR(n), mask) +#define HWIO_IPA_IRQ_EN_EE_n_OUTI(n,val) \ + out_dword(HWIO_IPA_IRQ_EN_EE_n_ADDR(n),val) +#define HWIO_IPA_IRQ_EN_EE_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_IRQ_EN_EE_n_ADDR(n),mask,val,HWIO_IPA_IRQ_EN_EE_n_INI(n)) +#define HWIO_IPA_IRQ_EN_EE_n_IPA_ERROR_FATAL_IRQ_EN_BMSK 0x80000000 +#define HWIO_IPA_IRQ_EN_EE_n_IPA_ERROR_FATAL_IRQ_EN_SHFT 0x1f +#define HWIO_IPA_IRQ_EN_EE_n_IPA_ERROR_NON_FATAL_IRQ_EN_BMSK 0x40000000 +#define HWIO_IPA_IRQ_EN_EE_n_IPA_ERROR_NON_FATAL_IRQ_EN_SHFT 0x1e +#define HWIO_IPA_IRQ_EN_EE_n_GSI_UC_IRQ_EN_BMSK 0x2000000 +#define HWIO_IPA_IRQ_EN_EE_n_GSI_UC_IRQ_EN_SHFT 0x19 +#define HWIO_IPA_IRQ_EN_EE_n_GSI_IPA_IF_TLV_RCVD_IRQ_EN_BMSK 0x1000000 +#define HWIO_IPA_IRQ_EN_EE_n_GSI_IPA_IF_TLV_RCVD_IRQ_EN_SHFT 0x18 +#define HWIO_IPA_IRQ_EN_EE_n_GSI_EE_IRQ_EN_BMSK 0x800000 +#define HWIO_IPA_IRQ_EN_EE_n_GSI_EE_IRQ_EN_SHFT 0x17 +#define HWIO_IPA_IRQ_EN_EE_n_UCP_IRQ_EN_BMSK 0x200000 +#define HWIO_IPA_IRQ_EN_EE_n_UCP_IRQ_EN_SHFT 0x15 +#define HWIO_IPA_IRQ_EN_EE_n_PIPE_RED_MARKER_ABOVE_IRQ_EN_BMSK 0x100000 +#define HWIO_IPA_IRQ_EN_EE_n_PIPE_RED_MARKER_ABOVE_IRQ_EN_SHFT 0x14 +#define HWIO_IPA_IRQ_EN_EE_n_PIPE_YELLOW_MARKER_ABOVE_IRQ_EN_BMSK 0x80000 +#define HWIO_IPA_IRQ_EN_EE_n_PIPE_YELLOW_MARKER_ABOVE_IRQ_EN_SHFT 0x13 +#define HWIO_IPA_IRQ_EN_EE_n_PIPE_RED_MARKER_BELOW_IRQ_EN_BMSK 0x40000 +#define HWIO_IPA_IRQ_EN_EE_n_PIPE_RED_MARKER_BELOW_IRQ_EN_SHFT 0x12 +#define HWIO_IPA_IRQ_EN_EE_n_PIPE_YELLOW_MARKER_BELOW_IRQ_EN_BMSK 0x20000 +#define HWIO_IPA_IRQ_EN_EE_n_PIPE_YELLOW_MARKER_BELOW_IRQ_EN_SHFT 0x11 +#define HWIO_IPA_IRQ_EN_EE_n_GSI_IDLE_IRQ_EN_BMSK 0x10000 +#define HWIO_IPA_IRQ_EN_EE_n_GSI_IDLE_IRQ_EN_SHFT 0x10 +#define HWIO_IPA_IRQ_EN_EE_n_TX_HOLB_DROP_IRQ_EN_BMSK 0x8000 +#define HWIO_IPA_IRQ_EN_EE_n_TX_HOLB_DROP_IRQ_EN_SHFT 0xf +#define HWIO_IPA_IRQ_EN_EE_n_TX_SUSPEND_IRQ_EN_BMSK 0x4000 +#define HWIO_IPA_IRQ_EN_EE_n_TX_SUSPEND_IRQ_EN_SHFT 0xe +#define HWIO_IPA_IRQ_EN_EE_n_PROC_TO_UC_ACK_Q_NOT_EMPTY_IRQ_EN_BMSK 0x100 +#define HWIO_IPA_IRQ_EN_EE_n_PROC_TO_UC_ACK_Q_NOT_EMPTY_IRQ_EN_SHFT 0x8 +#define HWIO_IPA_IRQ_EN_EE_n_UC_RX_CMD_Q_NOT_FULL_IRQ_EN_BMSK 0x80 +#define HWIO_IPA_IRQ_EN_EE_n_UC_RX_CMD_Q_NOT_FULL_IRQ_EN_SHFT 0x7 +#define HWIO_IPA_IRQ_EN_EE_n_UC_IN_Q_NOT_EMPTY_IRQ_EN_BMSK 0x40 +#define HWIO_IPA_IRQ_EN_EE_n_UC_IN_Q_NOT_EMPTY_IRQ_EN_SHFT 0x6 +#define HWIO_IPA_IRQ_EN_EE_n_UC_IRQ_3_IRQ_EN_BMSK 0x20 +#define HWIO_IPA_IRQ_EN_EE_n_UC_IRQ_3_IRQ_EN_SHFT 0x5 +#define HWIO_IPA_IRQ_EN_EE_n_UC_IRQ_2_IRQ_EN_BMSK 0x10 +#define HWIO_IPA_IRQ_EN_EE_n_UC_IRQ_2_IRQ_EN_SHFT 0x4 +#define HWIO_IPA_IRQ_EN_EE_n_UC_IRQ_1_IRQ_EN_BMSK 0x8 +#define HWIO_IPA_IRQ_EN_EE_n_UC_IRQ_1_IRQ_EN_SHFT 0x3 +#define HWIO_IPA_IRQ_EN_EE_n_UC_IRQ_0_IRQ_EN_BMSK 0x4 +#define HWIO_IPA_IRQ_EN_EE_n_UC_IRQ_0_IRQ_EN_SHFT 0x2 + +#define HWIO_IPA_IRQ_CLR_EE_n_ADDR(n) (IPA_EE_REG_BASE + 0x00000010 + 0x1000 * (n)) +#define HWIO_IPA_IRQ_CLR_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + 0x00000010 + 0x1000 * (n)) +#define HWIO_IPA_IRQ_CLR_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + 0x00000010 + 0x1000 * (n)) +#define HWIO_IPA_IRQ_CLR_EE_n_RMSK 0xc3bfc1fc +#define HWIO_IPA_IRQ_CLR_EE_n_MAXn 3 +#define HWIO_IPA_IRQ_CLR_EE_n_ATTR 0x2 +#define HWIO_IPA_IRQ_CLR_EE_n_OUTI(n,val) \ + out_dword(HWIO_IPA_IRQ_CLR_EE_n_ADDR(n),val) +#define HWIO_IPA_IRQ_CLR_EE_n_IPA_ERROR_FATAL_CLR_BMSK 0x80000000 +#define HWIO_IPA_IRQ_CLR_EE_n_IPA_ERROR_FATAL_CLR_SHFT 0x1f +#define HWIO_IPA_IRQ_CLR_EE_n_IPA_ERROR_NON_FATAL_CLR_BMSK 0x40000000 +#define HWIO_IPA_IRQ_CLR_EE_n_IPA_ERROR_NON_FATAL_CLR_SHFT 0x1e +#define HWIO_IPA_IRQ_CLR_EE_n_GSI_UC_IRQ_CLR_BMSK 0x2000000 +#define HWIO_IPA_IRQ_CLR_EE_n_GSI_UC_IRQ_CLR_SHFT 0x19 +#define HWIO_IPA_IRQ_CLR_EE_n_GSI_IPA_IF_TLV_RCVD_IRQ_CLR_BMSK 0x1000000 +#define HWIO_IPA_IRQ_CLR_EE_n_GSI_IPA_IF_TLV_RCVD_IRQ_CLR_SHFT 0x18 +#define HWIO_IPA_IRQ_CLR_EE_n_GSI_EE_IRQ_CLR_BMSK 0x800000 +#define HWIO_IPA_IRQ_CLR_EE_n_GSI_EE_IRQ_CLR_SHFT 0x17 +#define HWIO_IPA_IRQ_CLR_EE_n_UCP_IRQ_CLR_BMSK 0x200000 +#define HWIO_IPA_IRQ_CLR_EE_n_UCP_IRQ_CLR_SHFT 0x15 +#define HWIO_IPA_IRQ_CLR_EE_n_PIPE_RED_MARKER_ABOVE_IRQ_CLR_BMSK 0x100000 +#define HWIO_IPA_IRQ_CLR_EE_n_PIPE_RED_MARKER_ABOVE_IRQ_CLR_SHFT 0x14 +#define HWIO_IPA_IRQ_CLR_EE_n_PIPE_YELLOW_MARKER_ABOVE_IRQ_CLR_BMSK 0x80000 +#define HWIO_IPA_IRQ_CLR_EE_n_PIPE_YELLOW_MARKER_ABOVE_IRQ_CLR_SHFT 0x13 +#define HWIO_IPA_IRQ_CLR_EE_n_PIPE_RED_MARKER_BELOW_IRQ_CLR_BMSK 0x40000 +#define HWIO_IPA_IRQ_CLR_EE_n_PIPE_RED_MARKER_BELOW_IRQ_CLR_SHFT 0x12 +#define HWIO_IPA_IRQ_CLR_EE_n_PIPE_YELLOW_MARKER_BELOW_IRQ_CLR_BMSK 0x20000 +#define HWIO_IPA_IRQ_CLR_EE_n_PIPE_YELLOW_MARKER_BELOW_IRQ_CLR_SHFT 0x11 +#define HWIO_IPA_IRQ_CLR_EE_n_GSI_IDLE_IRQ_CLR_BMSK 0x10000 +#define HWIO_IPA_IRQ_CLR_EE_n_GSI_IDLE_IRQ_CLR_SHFT 0x10 +#define HWIO_IPA_IRQ_CLR_EE_n_TX_HOLB_DROP_IRQ_CLR_BMSK 0x8000 +#define HWIO_IPA_IRQ_CLR_EE_n_TX_HOLB_DROP_IRQ_CLR_SHFT 0xf +#define HWIO_IPA_IRQ_CLR_EE_n_TX_SUSPEND_IRQ_CLR_BMSK 0x4000 +#define HWIO_IPA_IRQ_CLR_EE_n_TX_SUSPEND_IRQ_CLR_SHFT 0xe +#define HWIO_IPA_IRQ_CLR_EE_n_PROC_TO_UC_ACK_Q_NOT_EMPTY_IRQ_CLR_BMSK 0x100 +#define HWIO_IPA_IRQ_CLR_EE_n_PROC_TO_UC_ACK_Q_NOT_EMPTY_IRQ_CLR_SHFT 0x8 +#define HWIO_IPA_IRQ_CLR_EE_n_UC_RX_CMD_Q_NOT_FULL_IRQ_CLR_BMSK 0x80 +#define HWIO_IPA_IRQ_CLR_EE_n_UC_RX_CMD_Q_NOT_FULL_IRQ_CLR_SHFT 0x7 +#define HWIO_IPA_IRQ_CLR_EE_n_UC_IN_Q_NOT_EMPTY_IRQ_CLR_BMSK 0x40 +#define HWIO_IPA_IRQ_CLR_EE_n_UC_IN_Q_NOT_EMPTY_IRQ_CLR_SHFT 0x6 +#define HWIO_IPA_IRQ_CLR_EE_n_UC_IRQ_3_CLR_BMSK 0x20 +#define HWIO_IPA_IRQ_CLR_EE_n_UC_IRQ_3_CLR_SHFT 0x5 +#define HWIO_IPA_IRQ_CLR_EE_n_UC_IRQ_2_CLR_BMSK 0x10 +#define HWIO_IPA_IRQ_CLR_EE_n_UC_IRQ_2_CLR_SHFT 0x4 +#define HWIO_IPA_IRQ_CLR_EE_n_UC_IRQ_1_CLR_BMSK 0x8 +#define HWIO_IPA_IRQ_CLR_EE_n_UC_IRQ_1_CLR_SHFT 0x3 +#define HWIO_IPA_IRQ_CLR_EE_n_UC_IRQ_0_CLR_BMSK 0x4 +#define HWIO_IPA_IRQ_CLR_EE_n_UC_IRQ_0_CLR_SHFT 0x2 + +#define HWIO_IPA_SNOC_FEC_EE_n_ADDR(n) (IPA_EE_REG_BASE + 0x00000018 + 0x1000 * (n)) +#define HWIO_IPA_SNOC_FEC_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + 0x00000018 + 0x1000 * (n)) +#define HWIO_IPA_SNOC_FEC_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + 0x00000018 + 0x1000 * (n)) +#define HWIO_IPA_SNOC_FEC_EE_n_RMSK 0xb001ffff +#define HWIO_IPA_SNOC_FEC_EE_n_MAXn 3 +#define HWIO_IPA_SNOC_FEC_EE_n_ATTR 0x3 +#define HWIO_IPA_SNOC_FEC_EE_n_INI(n) \ + in_dword_masked(HWIO_IPA_SNOC_FEC_EE_n_ADDR(n), HWIO_IPA_SNOC_FEC_EE_n_RMSK) +#define HWIO_IPA_SNOC_FEC_EE_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_SNOC_FEC_EE_n_ADDR(n), mask) +#define HWIO_IPA_SNOC_FEC_EE_n_OUTI(n,val) \ + out_dword(HWIO_IPA_SNOC_FEC_EE_n_ADDR(n),val) +#define HWIO_IPA_SNOC_FEC_EE_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_SNOC_FEC_EE_n_ADDR(n),mask,val,HWIO_IPA_SNOC_FEC_EE_n_INI(n)) +#define HWIO_IPA_SNOC_FEC_EE_n_DIRECTION_BMSK 0x80000000 +#define HWIO_IPA_SNOC_FEC_EE_n_DIRECTION_SHFT 0x1f +#define HWIO_IPA_SNOC_FEC_EE_n_CLEAR_BMSK 0x20000000 +#define HWIO_IPA_SNOC_FEC_EE_n_CLEAR_SHFT 0x1d +#define HWIO_IPA_SNOC_FEC_EE_n_VALID_BMSK 0x10000000 +#define HWIO_IPA_SNOC_FEC_EE_n_VALID_SHFT 0x1c +#define HWIO_IPA_SNOC_FEC_EE_n_TID_BMSK 0x1f000 +#define HWIO_IPA_SNOC_FEC_EE_n_TID_SHFT 0xc +#define HWIO_IPA_SNOC_FEC_EE_n_NOC_MASTER_BMSK 0xe00 +#define HWIO_IPA_SNOC_FEC_EE_n_NOC_MASTER_SHFT 0x9 +#define HWIO_IPA_SNOC_FEC_EE_n_NOC_PORT_BMSK 0x100 +#define HWIO_IPA_SNOC_FEC_EE_n_NOC_PORT_SHFT 0x8 +#define HWIO_IPA_SNOC_FEC_EE_n_CLIENT_BMSK 0xff +#define HWIO_IPA_SNOC_FEC_EE_n_CLIENT_SHFT 0x0 + +#define HWIO_IPA_IRQ_EE_UC_n_ADDR(n) (IPA_EE_REG_BASE + 0x0000001c + 0x1000 * (n)) +#define HWIO_IPA_IRQ_EE_UC_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + 0x0000001c + 0x1000 * (n)) +#define HWIO_IPA_IRQ_EE_UC_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + 0x0000001c + 0x1000 * (n)) +#define HWIO_IPA_IRQ_EE_UC_n_RMSK 0x1 +#define HWIO_IPA_IRQ_EE_UC_n_MAXn 3 +#define HWIO_IPA_IRQ_EE_UC_n_ATTR 0x2 +#define HWIO_IPA_IRQ_EE_UC_n_OUTI(n,val) \ + out_dword(HWIO_IPA_IRQ_EE_UC_n_ADDR(n),val) +#define HWIO_IPA_IRQ_EE_UC_n_INTR_BMSK 0x1 +#define HWIO_IPA_IRQ_EE_UC_n_INTR_SHFT 0x0 + +#define HWIO_IPA_FEC_FATAL_ADDR_EE_n_ADDR(n) (IPA_EE_REG_BASE + 0x00000020 + 0x1000 * (n)) +#define HWIO_IPA_FEC_FATAL_ADDR_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + 0x00000020 + 0x1000 * (n)) +#define HWIO_IPA_FEC_FATAL_ADDR_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + 0x00000020 + 0x1000 * (n)) +#define HWIO_IPA_FEC_FATAL_ADDR_EE_n_RMSK 0xffffffff +#define HWIO_IPA_FEC_FATAL_ADDR_EE_n_MAXn 3 +#define HWIO_IPA_FEC_FATAL_ADDR_EE_n_ATTR 0x1 +#define HWIO_IPA_FEC_FATAL_ADDR_EE_n_INI(n) \ + in_dword_masked(HWIO_IPA_FEC_FATAL_ADDR_EE_n_ADDR(n), HWIO_IPA_FEC_FATAL_ADDR_EE_n_RMSK) +#define HWIO_IPA_FEC_FATAL_ADDR_EE_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_FEC_FATAL_ADDR_EE_n_ADDR(n), mask) +#define HWIO_IPA_FEC_FATAL_ADDR_EE_n_ADDR_BMSK 0xffffffff +#define HWIO_IPA_FEC_FATAL_ADDR_EE_n_ADDR_SHFT 0x0 + +#define HWIO_IPA_FEC_FATAL_ADDR_MSB_EE_n_ADDR(n) (IPA_EE_REG_BASE + 0x00000024 + 0x1000 * (n)) +#define HWIO_IPA_FEC_FATAL_ADDR_MSB_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + 0x00000024 + 0x1000 * (n)) +#define HWIO_IPA_FEC_FATAL_ADDR_MSB_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + 0x00000024 + 0x1000 * (n)) +#define HWIO_IPA_FEC_FATAL_ADDR_MSB_EE_n_RMSK 0xffffffff +#define HWIO_IPA_FEC_FATAL_ADDR_MSB_EE_n_MAXn 3 +#define HWIO_IPA_FEC_FATAL_ADDR_MSB_EE_n_ATTR 0x1 +#define HWIO_IPA_FEC_FATAL_ADDR_MSB_EE_n_INI(n) \ + in_dword_masked(HWIO_IPA_FEC_FATAL_ADDR_MSB_EE_n_ADDR(n), HWIO_IPA_FEC_FATAL_ADDR_MSB_EE_n_RMSK) +#define HWIO_IPA_FEC_FATAL_ADDR_MSB_EE_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_FEC_FATAL_ADDR_MSB_EE_n_ADDR(n), mask) +#define HWIO_IPA_FEC_FATAL_ADDR_MSB_EE_n_ADDR_BMSK 0xffffffff +#define HWIO_IPA_FEC_FATAL_ADDR_MSB_EE_n_ADDR_SHFT 0x0 + +#define HWIO_IPA_FEC_FATAL_ATTR_EE_n_ADDR(n) (IPA_EE_REG_BASE + 0x00000028 + 0x1000 * (n)) +#define HWIO_IPA_FEC_FATAL_ATTR_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + 0x00000028 + 0x1000 * (n)) +#define HWIO_IPA_FEC_FATAL_ATTR_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + 0x00000028 + 0x1000 * (n)) +#define HWIO_IPA_FEC_FATAL_ATTR_EE_n_RMSK 0xffffffff +#define HWIO_IPA_FEC_FATAL_ATTR_EE_n_MAXn 3 +#define HWIO_IPA_FEC_FATAL_ATTR_EE_n_ATTR 0x1 +#define HWIO_IPA_FEC_FATAL_ATTR_EE_n_INI(n) \ + in_dword_masked(HWIO_IPA_FEC_FATAL_ATTR_EE_n_ADDR(n), HWIO_IPA_FEC_FATAL_ATTR_EE_n_RMSK) +#define HWIO_IPA_FEC_FATAL_ATTR_EE_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_FEC_FATAL_ATTR_EE_n_ADDR(n), mask) +#define HWIO_IPA_FEC_FATAL_ATTR_EE_n_ERROR_INFO_BMSK 0xffffffc0 +#define HWIO_IPA_FEC_FATAL_ATTR_EE_n_ERROR_INFO_SHFT 0x6 +#define HWIO_IPA_FEC_FATAL_ATTR_EE_n_OPCODE_BMSK 0x3f +#define HWIO_IPA_FEC_FATAL_ATTR_EE_n_OPCODE_SHFT 0x0 + +#define HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_REG_k_ADDR(n,k) (IPA_EE_REG_BASE + 0x00000030 + 0x1000 * (n) + 0x4 * (k)) +#define HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_REG_k_PHYS(n,k) (IPA_EE_REG_BASE_PHYS + 0x00000030 + 0x1000 * (n) + 0x4 * (k)) +#define HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_REG_k_OFFS(n,k) (IPA_EE_REG_BASE_OFFS + 0x00000030 + 0x1000 * (n) + 0x4 * (k)) +#define HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_REG_k_RMSK 0xffffffff +#define HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_REG_k_MAXn 3 +#define HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_REG_k_MAXk 1 +#define HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_REG_k_ATTR 0x1 +#define HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_REG_k_INI2(n,k) \ + in_dword_masked(HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_REG_k_ADDR(n,k), HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_REG_k_RMSK) +#define HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_REG_k_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_REG_k_ADDR(n,k), mask) +#define HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_REG_k_ENDPOINTS_BMSK 0xffffffff +#define HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_REG_k_ENDPOINTS_SHFT 0x0 + +#define HWIO_IPA_SUSPEND_IRQ_EN_EE_n_REG_k_ADDR(n,k) (IPA_EE_REG_BASE + 0x00000050 + 0x1000 * (n) + 0x4 * (k)) +#define HWIO_IPA_SUSPEND_IRQ_EN_EE_n_REG_k_PHYS(n,k) (IPA_EE_REG_BASE_PHYS + 0x00000050 + 0x1000 * (n) + 0x4 * (k)) +#define HWIO_IPA_SUSPEND_IRQ_EN_EE_n_REG_k_OFFS(n,k) (IPA_EE_REG_BASE_OFFS + 0x00000050 + 0x1000 * (n) + 0x4 * (k)) +#define HWIO_IPA_SUSPEND_IRQ_EN_EE_n_REG_k_RMSK 0xffffffff +#define HWIO_IPA_SUSPEND_IRQ_EN_EE_n_REG_k_MAXn 3 +#define HWIO_IPA_SUSPEND_IRQ_EN_EE_n_REG_k_MAXk 1 +#define HWIO_IPA_SUSPEND_IRQ_EN_EE_n_REG_k_ATTR 0x3 +#define HWIO_IPA_SUSPEND_IRQ_EN_EE_n_REG_k_INI2(n,k) \ + in_dword_masked(HWIO_IPA_SUSPEND_IRQ_EN_EE_n_REG_k_ADDR(n,k), HWIO_IPA_SUSPEND_IRQ_EN_EE_n_REG_k_RMSK) +#define HWIO_IPA_SUSPEND_IRQ_EN_EE_n_REG_k_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_SUSPEND_IRQ_EN_EE_n_REG_k_ADDR(n,k), mask) +#define HWIO_IPA_SUSPEND_IRQ_EN_EE_n_REG_k_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_SUSPEND_IRQ_EN_EE_n_REG_k_ADDR(n,k),val) +#define HWIO_IPA_SUSPEND_IRQ_EN_EE_n_REG_k_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_SUSPEND_IRQ_EN_EE_n_REG_k_ADDR(n,k),mask,val,HWIO_IPA_SUSPEND_IRQ_EN_EE_n_REG_k_INI2(n,k)) +#define HWIO_IPA_SUSPEND_IRQ_EN_EE_n_REG_k_ENDPOINTS_BMSK 0xffffffff +#define HWIO_IPA_SUSPEND_IRQ_EN_EE_n_REG_k_ENDPOINTS_SHFT 0x0 + +#define HWIO_IPA_DRBIP_FEC_INFO_EE_n_ADDR(n) (IPA_EE_REG_BASE + 0x00000060 + 0x1000 * (n)) +#define HWIO_IPA_DRBIP_FEC_INFO_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + 0x00000060 + 0x1000 * (n)) +#define HWIO_IPA_DRBIP_FEC_INFO_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + 0x00000060 + 0x1000 * (n)) +#define HWIO_IPA_DRBIP_FEC_INFO_EE_n_RMSK 0xffffffff +#define HWIO_IPA_DRBIP_FEC_INFO_EE_n_MAXn 3 +#define HWIO_IPA_DRBIP_FEC_INFO_EE_n_ATTR 0x1 +#define HWIO_IPA_DRBIP_FEC_INFO_EE_n_INI(n) \ + in_dword_masked(HWIO_IPA_DRBIP_FEC_INFO_EE_n_ADDR(n), HWIO_IPA_DRBIP_FEC_INFO_EE_n_RMSK) +#define HWIO_IPA_DRBIP_FEC_INFO_EE_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_DRBIP_FEC_INFO_EE_n_ADDR(n), mask) +#define HWIO_IPA_DRBIP_FEC_INFO_EE_n_AVAIL_DATA_SECTORS_BMSK 0xff000000 +#define HWIO_IPA_DRBIP_FEC_INFO_EE_n_AVAIL_DATA_SECTORS_SHFT 0x18 +#define HWIO_IPA_DRBIP_FEC_INFO_EE_n_REQUIRED_DATA_SECTORS_BMSK 0xff0000 +#define HWIO_IPA_DRBIP_FEC_INFO_EE_n_REQUIRED_DATA_SECTORS_SHFT 0x10 +#define HWIO_IPA_DRBIP_FEC_INFO_EE_n_SRC_PIPE_BMSK 0xff00 +#define HWIO_IPA_DRBIP_FEC_INFO_EE_n_SRC_PIPE_SHFT 0x8 +#define HWIO_IPA_DRBIP_FEC_INFO_EE_n_SRC_GRP_BMSK 0xf0 +#define HWIO_IPA_DRBIP_FEC_INFO_EE_n_SRC_GRP_SHFT 0x4 +#define HWIO_IPA_DRBIP_FEC_INFO_EE_n_ERROR_CODE_BMSK 0xf +#define HWIO_IPA_DRBIP_FEC_INFO_EE_n_ERROR_CODE_SHFT 0x0 + +#define HWIO_IPA_DRBIP_FEC_INFO_EXT_EE_n_ADDR(n) (IPA_EE_REG_BASE + 0x00000064 + 0x1000 * (n)) +#define HWIO_IPA_DRBIP_FEC_INFO_EXT_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + 0x00000064 + 0x1000 * (n)) +#define HWIO_IPA_DRBIP_FEC_INFO_EXT_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + 0x00000064 + 0x1000 * (n)) +#define HWIO_IPA_DRBIP_FEC_INFO_EXT_EE_n_RMSK 0xffffff +#define HWIO_IPA_DRBIP_FEC_INFO_EXT_EE_n_MAXn 3 +#define HWIO_IPA_DRBIP_FEC_INFO_EXT_EE_n_ATTR 0x1 +#define HWIO_IPA_DRBIP_FEC_INFO_EXT_EE_n_INI(n) \ + in_dword_masked(HWIO_IPA_DRBIP_FEC_INFO_EXT_EE_n_ADDR(n), HWIO_IPA_DRBIP_FEC_INFO_EXT_EE_n_RMSK) +#define HWIO_IPA_DRBIP_FEC_INFO_EXT_EE_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_DRBIP_FEC_INFO_EXT_EE_n_ADDR(n), mask) +#define HWIO_IPA_DRBIP_FEC_INFO_EXT_EE_n_OPCODE_BMSK 0xff0000 +#define HWIO_IPA_DRBIP_FEC_INFO_EXT_EE_n_OPCODE_SHFT 0x10 +#define HWIO_IPA_DRBIP_FEC_INFO_EXT_EE_n_SIZE_BMSK 0xffff +#define HWIO_IPA_DRBIP_FEC_INFO_EXT_EE_n_SIZE_SHFT 0x0 + +#define HWIO_IPA_SUSPEND_IRQ_CLR_EE_n_REG_k_ADDR(n,k) (IPA_EE_REG_BASE + 0x00000070 + 0x1000 * (n) + 0x4 * (k)) +#define HWIO_IPA_SUSPEND_IRQ_CLR_EE_n_REG_k_PHYS(n,k) (IPA_EE_REG_BASE_PHYS + 0x00000070 + 0x1000 * (n) + 0x4 * (k)) +#define HWIO_IPA_SUSPEND_IRQ_CLR_EE_n_REG_k_OFFS(n,k) (IPA_EE_REG_BASE_OFFS + 0x00000070 + 0x1000 * (n) + 0x4 * (k)) +#define HWIO_IPA_SUSPEND_IRQ_CLR_EE_n_REG_k_RMSK 0xffffffff +#define HWIO_IPA_SUSPEND_IRQ_CLR_EE_n_REG_k_MAXn 3 +#define HWIO_IPA_SUSPEND_IRQ_CLR_EE_n_REG_k_MAXk 1 +#define HWIO_IPA_SUSPEND_IRQ_CLR_EE_n_REG_k_ATTR 0x2 +#define HWIO_IPA_SUSPEND_IRQ_CLR_EE_n_REG_k_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_SUSPEND_IRQ_CLR_EE_n_REG_k_ADDR(n,k),val) +#define HWIO_IPA_SUSPEND_IRQ_CLR_EE_n_REG_k_ENDPOINTS_BMSK 0xffffffff +#define HWIO_IPA_SUSPEND_IRQ_CLR_EE_n_REG_k_ENDPOINTS_SHFT 0x0 + +#define HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_REG_k_ADDR(n,k) (IPA_EE_REG_BASE + 0x00000090 + 0x1000 * (n) + 0x4 * (k)) +#define HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_REG_k_PHYS(n,k) (IPA_EE_REG_BASE_PHYS + 0x00000090 + 0x1000 * (n) + 0x4 * (k)) +#define HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_REG_k_OFFS(n,k) (IPA_EE_REG_BASE_OFFS + 0x00000090 + 0x1000 * (n) + 0x4 * (k)) +#define HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_REG_k_RMSK 0xffffffff +#define HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_REG_k_MAXn 3 +#define HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_REG_k_MAXk 1 +#define HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_REG_k_ATTR 0x1 +#define HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_REG_k_INI2(n,k) \ + in_dword_masked(HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_REG_k_ADDR(n,k), HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_REG_k_RMSK) +#define HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_REG_k_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_REG_k_ADDR(n,k), mask) +#define HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_REG_k_ENDPOINTS_BMSK 0xffffffff +#define HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_REG_k_ENDPOINTS_SHFT 0x0 + +#define HWIO_IPA_HOLB_DROP_IRQ_EN_EE_n_REG_k_ADDR(n,k) (IPA_EE_REG_BASE + 0x000000b0 + 0x1000 * (n) + 0x4 * (k)) +#define HWIO_IPA_HOLB_DROP_IRQ_EN_EE_n_REG_k_PHYS(n,k) (IPA_EE_REG_BASE_PHYS + 0x000000b0 + 0x1000 * (n) + 0x4 * (k)) +#define HWIO_IPA_HOLB_DROP_IRQ_EN_EE_n_REG_k_OFFS(n,k) (IPA_EE_REG_BASE_OFFS + 0x000000b0 + 0x1000 * (n) + 0x4 * (k)) +#define HWIO_IPA_HOLB_DROP_IRQ_EN_EE_n_REG_k_RMSK 0xffffffff +#define HWIO_IPA_HOLB_DROP_IRQ_EN_EE_n_REG_k_MAXn 3 +#define HWIO_IPA_HOLB_DROP_IRQ_EN_EE_n_REG_k_MAXk 1 +#define HWIO_IPA_HOLB_DROP_IRQ_EN_EE_n_REG_k_ATTR 0x3 +#define HWIO_IPA_HOLB_DROP_IRQ_EN_EE_n_REG_k_INI2(n,k) \ + in_dword_masked(HWIO_IPA_HOLB_DROP_IRQ_EN_EE_n_REG_k_ADDR(n,k), HWIO_IPA_HOLB_DROP_IRQ_EN_EE_n_REG_k_RMSK) +#define HWIO_IPA_HOLB_DROP_IRQ_EN_EE_n_REG_k_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_HOLB_DROP_IRQ_EN_EE_n_REG_k_ADDR(n,k), mask) +#define HWIO_IPA_HOLB_DROP_IRQ_EN_EE_n_REG_k_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_HOLB_DROP_IRQ_EN_EE_n_REG_k_ADDR(n,k),val) +#define HWIO_IPA_HOLB_DROP_IRQ_EN_EE_n_REG_k_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_HOLB_DROP_IRQ_EN_EE_n_REG_k_ADDR(n,k),mask,val,HWIO_IPA_HOLB_DROP_IRQ_EN_EE_n_REG_k_INI2(n,k)) +#define HWIO_IPA_HOLB_DROP_IRQ_EN_EE_n_REG_k_ENDPOINTS_BMSK 0xffffffff +#define HWIO_IPA_HOLB_DROP_IRQ_EN_EE_n_REG_k_ENDPOINTS_SHFT 0x0 + +#define HWIO_IPA_HOLB_DROP_IRQ_CLR_EE_n_REG_k_ADDR(n,k) (IPA_EE_REG_BASE + 0x000000c0 + 0x1000 * (n) + 0x4 * (k)) +#define HWIO_IPA_HOLB_DROP_IRQ_CLR_EE_n_REG_k_PHYS(n,k) (IPA_EE_REG_BASE_PHYS + 0x000000c0 + 0x1000 * (n) + 0x4 * (k)) +#define HWIO_IPA_HOLB_DROP_IRQ_CLR_EE_n_REG_k_OFFS(n,k) (IPA_EE_REG_BASE_OFFS + 0x000000c0 + 0x1000 * (n) + 0x4 * (k)) +#define HWIO_IPA_HOLB_DROP_IRQ_CLR_EE_n_REG_k_RMSK 0xffffffff +#define HWIO_IPA_HOLB_DROP_IRQ_CLR_EE_n_REG_k_MAXn 3 +#define HWIO_IPA_HOLB_DROP_IRQ_CLR_EE_n_REG_k_MAXk 1 +#define HWIO_IPA_HOLB_DROP_IRQ_CLR_EE_n_REG_k_ATTR 0x2 +#define HWIO_IPA_HOLB_DROP_IRQ_CLR_EE_n_REG_k_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_HOLB_DROP_IRQ_CLR_EE_n_REG_k_ADDR(n,k),val) +#define HWIO_IPA_HOLB_DROP_IRQ_CLR_EE_n_REG_k_ENDPOINTS_BMSK 0xffffffff +#define HWIO_IPA_HOLB_DROP_IRQ_CLR_EE_n_REG_k_ENDPOINTS_SHFT 0x0 + +#define HWIO_IPA_IRQ_STTS_EE_ERROR_FATAL_n_ADDR(n) (IPA_EE_REG_BASE + 0x00000144 + 0x1000 * (n)) +#define HWIO_IPA_IRQ_STTS_EE_ERROR_FATAL_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + 0x00000144 + 0x1000 * (n)) +#define HWIO_IPA_IRQ_STTS_EE_ERROR_FATAL_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + 0x00000144 + 0x1000 * (n)) +#define HWIO_IPA_IRQ_STTS_EE_ERROR_FATAL_n_RMSK 0x7f +#define HWIO_IPA_IRQ_STTS_EE_ERROR_FATAL_n_MAXn 3 +#define HWIO_IPA_IRQ_STTS_EE_ERROR_FATAL_n_ATTR 0x1 +#define HWIO_IPA_IRQ_STTS_EE_ERROR_FATAL_n_INI(n) \ + in_dword_masked(HWIO_IPA_IRQ_STTS_EE_ERROR_FATAL_n_ADDR(n), HWIO_IPA_IRQ_STTS_EE_ERROR_FATAL_n_RMSK) +#define HWIO_IPA_IRQ_STTS_EE_ERROR_FATAL_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_IRQ_STTS_EE_ERROR_FATAL_n_ADDR(n), mask) +#define HWIO_IPA_IRQ_STTS_EE_ERROR_FATAL_n_DRBIP_IMM_CMD_NO_FLSH_HZRD_IRQ_BMSK 0x40 +#define HWIO_IPA_IRQ_STTS_EE_ERROR_FATAL_n_DRBIP_IMM_CMD_NO_FLSH_HZRD_IRQ_SHFT 0x6 +#define HWIO_IPA_IRQ_STTS_EE_ERROR_FATAL_n_DRBIP_DATA_SCTR_CFG_ERROR_IRQ_BMSK 0x20 +#define HWIO_IPA_IRQ_STTS_EE_ERROR_FATAL_n_DRBIP_DATA_SCTR_CFG_ERROR_IRQ_SHFT 0x5 +#define HWIO_IPA_IRQ_STTS_EE_ERROR_FATAL_n_DRBIP_PKT_EXCEED_MAX_SIZE_IRQ_BMSK 0x10 +#define HWIO_IPA_IRQ_STTS_EE_ERROR_FATAL_n_DRBIP_PKT_EXCEED_MAX_SIZE_IRQ_SHFT 0x4 +#define HWIO_IPA_IRQ_STTS_EE_ERROR_FATAL_n_TLV_LEN_MIN_DSM_IRQ_BMSK 0x8 +#define HWIO_IPA_IRQ_STTS_EE_ERROR_FATAL_n_TLV_LEN_MIN_DSM_IRQ_SHFT 0x3 +#define HWIO_IPA_IRQ_STTS_EE_ERROR_FATAL_n_RX_ERR_IRQ_BMSK 0x4 +#define HWIO_IPA_IRQ_STTS_EE_ERROR_FATAL_n_RX_ERR_IRQ_SHFT 0x2 +#define HWIO_IPA_IRQ_STTS_EE_ERROR_FATAL_n_PROC_ERR_IRQ_BMSK 0x2 +#define HWIO_IPA_IRQ_STTS_EE_ERROR_FATAL_n_PROC_ERR_IRQ_SHFT 0x1 +#define HWIO_IPA_IRQ_STTS_EE_ERROR_FATAL_n_BAD_SNOC_ACCESS_IRQ_BMSK 0x1 +#define HWIO_IPA_IRQ_STTS_EE_ERROR_FATAL_n_BAD_SNOC_ACCESS_IRQ_SHFT 0x0 + +#define HWIO_IPA_IRQ_EN_EE_ERROR_FATAL_n_ADDR(n) (IPA_EE_REG_BASE + 0x00000148 + 0x1000 * (n)) +#define HWIO_IPA_IRQ_EN_EE_ERROR_FATAL_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + 0x00000148 + 0x1000 * (n)) +#define HWIO_IPA_IRQ_EN_EE_ERROR_FATAL_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + 0x00000148 + 0x1000 * (n)) +#define HWIO_IPA_IRQ_EN_EE_ERROR_FATAL_n_RMSK 0x7f +#define HWIO_IPA_IRQ_EN_EE_ERROR_FATAL_n_MAXn 3 +#define HWIO_IPA_IRQ_EN_EE_ERROR_FATAL_n_ATTR 0x3 +#define HWIO_IPA_IRQ_EN_EE_ERROR_FATAL_n_INI(n) \ + in_dword_masked(HWIO_IPA_IRQ_EN_EE_ERROR_FATAL_n_ADDR(n), HWIO_IPA_IRQ_EN_EE_ERROR_FATAL_n_RMSK) +#define HWIO_IPA_IRQ_EN_EE_ERROR_FATAL_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_IRQ_EN_EE_ERROR_FATAL_n_ADDR(n), mask) +#define HWIO_IPA_IRQ_EN_EE_ERROR_FATAL_n_OUTI(n,val) \ + out_dword(HWIO_IPA_IRQ_EN_EE_ERROR_FATAL_n_ADDR(n),val) +#define HWIO_IPA_IRQ_EN_EE_ERROR_FATAL_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_IRQ_EN_EE_ERROR_FATAL_n_ADDR(n),mask,val,HWIO_IPA_IRQ_EN_EE_ERROR_FATAL_n_INI(n)) +#define HWIO_IPA_IRQ_EN_EE_ERROR_FATAL_n_DRBIP_IMM_CMD_NO_FLSH_HZRD_IRQ_EN_BMSK 0x40 +#define HWIO_IPA_IRQ_EN_EE_ERROR_FATAL_n_DRBIP_IMM_CMD_NO_FLSH_HZRD_IRQ_EN_SHFT 0x6 +#define HWIO_IPA_IRQ_EN_EE_ERROR_FATAL_n_DRBIP_DATA_SCTR_CFG_ERROR_IRQ_EN_BMSK 0x20 +#define HWIO_IPA_IRQ_EN_EE_ERROR_FATAL_n_DRBIP_DATA_SCTR_CFG_ERROR_IRQ_EN_SHFT 0x5 +#define HWIO_IPA_IRQ_EN_EE_ERROR_FATAL_n_DRBIP_PKT_EXCEED_MAX_SIZE_IRQ_EN_BMSK 0x10 +#define HWIO_IPA_IRQ_EN_EE_ERROR_FATAL_n_DRBIP_PKT_EXCEED_MAX_SIZE_IRQ_EN_SHFT 0x4 +#define HWIO_IPA_IRQ_EN_EE_ERROR_FATAL_n_TLV_LEN_MIN_DSM_IRQ_EN_BMSK 0x8 +#define HWIO_IPA_IRQ_EN_EE_ERROR_FATAL_n_TLV_LEN_MIN_DSM_IRQ_EN_SHFT 0x3 +#define HWIO_IPA_IRQ_EN_EE_ERROR_FATAL_n_RX_ERR_IRQ_EN_BMSK 0x4 +#define HWIO_IPA_IRQ_EN_EE_ERROR_FATAL_n_RX_ERR_IRQ_EN_SHFT 0x2 +#define HWIO_IPA_IRQ_EN_EE_ERROR_FATAL_n_PROC_ERR_IRQ_EN_BMSK 0x2 +#define HWIO_IPA_IRQ_EN_EE_ERROR_FATAL_n_PROC_ERR_IRQ_EN_SHFT 0x1 +#define HWIO_IPA_IRQ_EN_EE_ERROR_FATAL_n_BAD_SNOC_ACCESS_IRQ_EN_BMSK 0x1 +#define HWIO_IPA_IRQ_EN_EE_ERROR_FATAL_n_BAD_SNOC_ACCESS_IRQ_EN_SHFT 0x0 + +#define HWIO_IPA_IRQ_CLR_EE_ERROR_FATAL_n_ADDR(n) (IPA_EE_REG_BASE + 0x0000014c + 0x1000 * (n)) +#define HWIO_IPA_IRQ_CLR_EE_ERROR_FATAL_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + 0x0000014c + 0x1000 * (n)) +#define HWIO_IPA_IRQ_CLR_EE_ERROR_FATAL_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + 0x0000014c + 0x1000 * (n)) +#define HWIO_IPA_IRQ_CLR_EE_ERROR_FATAL_n_RMSK 0x7f +#define HWIO_IPA_IRQ_CLR_EE_ERROR_FATAL_n_MAXn 3 +#define HWIO_IPA_IRQ_CLR_EE_ERROR_FATAL_n_ATTR 0x2 +#define HWIO_IPA_IRQ_CLR_EE_ERROR_FATAL_n_OUTI(n,val) \ + out_dword(HWIO_IPA_IRQ_CLR_EE_ERROR_FATAL_n_ADDR(n),val) +#define HWIO_IPA_IRQ_CLR_EE_ERROR_FATAL_n_DRBIP_IMM_CMD_NO_FLSH_HZRD_IRQ_CLR_BMSK 0x40 +#define HWIO_IPA_IRQ_CLR_EE_ERROR_FATAL_n_DRBIP_IMM_CMD_NO_FLSH_HZRD_IRQ_CLR_SHFT 0x6 +#define HWIO_IPA_IRQ_CLR_EE_ERROR_FATAL_n_DRBIP_DATA_SCTR_CFG_ERROR_IRQ_CLR_BMSK 0x20 +#define HWIO_IPA_IRQ_CLR_EE_ERROR_FATAL_n_DRBIP_DATA_SCTR_CFG_ERROR_IRQ_CLR_SHFT 0x5 +#define HWIO_IPA_IRQ_CLR_EE_ERROR_FATAL_n_DRBIP_PKT_EXCEED_MAX_SIZE_IRQ_CLR_BMSK 0x10 +#define HWIO_IPA_IRQ_CLR_EE_ERROR_FATAL_n_DRBIP_PKT_EXCEED_MAX_SIZE_IRQ_CLR_SHFT 0x4 +#define HWIO_IPA_IRQ_CLR_EE_ERROR_FATAL_n_TLV_LEN_MIN_DSM_IRQ_CLR_BMSK 0x8 +#define HWIO_IPA_IRQ_CLR_EE_ERROR_FATAL_n_TLV_LEN_MIN_DSM_IRQ_CLR_SHFT 0x3 +#define HWIO_IPA_IRQ_CLR_EE_ERROR_FATAL_n_RX_ERR_IRQ_CLR_BMSK 0x4 +#define HWIO_IPA_IRQ_CLR_EE_ERROR_FATAL_n_RX_ERR_IRQ_CLR_SHFT 0x2 +#define HWIO_IPA_IRQ_CLR_EE_ERROR_FATAL_n_PROC_ERR_IRQ_CLR_BMSK 0x2 +#define HWIO_IPA_IRQ_CLR_EE_ERROR_FATAL_n_PROC_ERR_IRQ_CLR_SHFT 0x1 +#define HWIO_IPA_IRQ_CLR_EE_ERROR_FATAL_n_BAD_SNOC_ACCESS_IRQ_CLR_BMSK 0x1 +#define HWIO_IPA_IRQ_CLR_EE_ERROR_FATAL_n_BAD_SNOC_ACCESS_IRQ_CLR_SHFT 0x0 + +#define HWIO_IPA_IRQ_STTS_EE_ERROR_NON_FATAL_n_ADDR(n) (IPA_EE_REG_BASE + 0x00000150 + 0x1000 * (n)) +#define HWIO_IPA_IRQ_STTS_EE_ERROR_NON_FATAL_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + 0x00000150 + 0x1000 * (n)) +#define HWIO_IPA_IRQ_STTS_EE_ERROR_NON_FATAL_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + 0x00000150 + 0x1000 * (n)) +#define HWIO_IPA_IRQ_STTS_EE_ERROR_NON_FATAL_n_RMSK 0x3 +#define HWIO_IPA_IRQ_STTS_EE_ERROR_NON_FATAL_n_MAXn 3 +#define HWIO_IPA_IRQ_STTS_EE_ERROR_NON_FATAL_n_ATTR 0x1 +#define HWIO_IPA_IRQ_STTS_EE_ERROR_NON_FATAL_n_INI(n) \ + in_dword_masked(HWIO_IPA_IRQ_STTS_EE_ERROR_NON_FATAL_n_ADDR(n), HWIO_IPA_IRQ_STTS_EE_ERROR_NON_FATAL_n_RMSK) +#define HWIO_IPA_IRQ_STTS_EE_ERROR_NON_FATAL_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_IRQ_STTS_EE_ERROR_NON_FATAL_n_ADDR(n), mask) +#define HWIO_IPA_IRQ_STTS_EE_ERROR_NON_FATAL_n_PROC_ERR_IRQ_BMSK 0x2 +#define HWIO_IPA_IRQ_STTS_EE_ERROR_NON_FATAL_n_PROC_ERR_IRQ_SHFT 0x1 +#define HWIO_IPA_IRQ_STTS_EE_ERROR_NON_FATAL_n_DEAGGR_ERR_IRQ_BMSK 0x1 +#define HWIO_IPA_IRQ_STTS_EE_ERROR_NON_FATAL_n_DEAGGR_ERR_IRQ_SHFT 0x0 + +#define HWIO_IPA_IRQ_EN_EE_ERROR_NON_FATAL_n_ADDR(n) (IPA_EE_REG_BASE + 0x00000154 + 0x1000 * (n)) +#define HWIO_IPA_IRQ_EN_EE_ERROR_NON_FATAL_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + 0x00000154 + 0x1000 * (n)) +#define HWIO_IPA_IRQ_EN_EE_ERROR_NON_FATAL_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + 0x00000154 + 0x1000 * (n)) +#define HWIO_IPA_IRQ_EN_EE_ERROR_NON_FATAL_n_RMSK 0x3 +#define HWIO_IPA_IRQ_EN_EE_ERROR_NON_FATAL_n_MAXn 3 +#define HWIO_IPA_IRQ_EN_EE_ERROR_NON_FATAL_n_ATTR 0x3 +#define HWIO_IPA_IRQ_EN_EE_ERROR_NON_FATAL_n_INI(n) \ + in_dword_masked(HWIO_IPA_IRQ_EN_EE_ERROR_NON_FATAL_n_ADDR(n), HWIO_IPA_IRQ_EN_EE_ERROR_NON_FATAL_n_RMSK) +#define HWIO_IPA_IRQ_EN_EE_ERROR_NON_FATAL_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_IRQ_EN_EE_ERROR_NON_FATAL_n_ADDR(n), mask) +#define HWIO_IPA_IRQ_EN_EE_ERROR_NON_FATAL_n_OUTI(n,val) \ + out_dword(HWIO_IPA_IRQ_EN_EE_ERROR_NON_FATAL_n_ADDR(n),val) +#define HWIO_IPA_IRQ_EN_EE_ERROR_NON_FATAL_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_IRQ_EN_EE_ERROR_NON_FATAL_n_ADDR(n),mask,val,HWIO_IPA_IRQ_EN_EE_ERROR_NON_FATAL_n_INI(n)) +#define HWIO_IPA_IRQ_EN_EE_ERROR_NON_FATAL_n_PROC_ERR_IRQ_EN_BMSK 0x2 +#define HWIO_IPA_IRQ_EN_EE_ERROR_NON_FATAL_n_PROC_ERR_IRQ_EN_SHFT 0x1 +#define HWIO_IPA_IRQ_EN_EE_ERROR_NON_FATAL_n_DEAGGR_ERR_IRQ_EN_BMSK 0x1 +#define HWIO_IPA_IRQ_EN_EE_ERROR_NON_FATAL_n_DEAGGR_ERR_IRQ_EN_SHFT 0x0 + +#define HWIO_IPA_IRQ_CLR_EE_ERROR_NON_FATAL_n_ADDR(n) (IPA_EE_REG_BASE + 0x00000158 + 0x1000 * (n)) +#define HWIO_IPA_IRQ_CLR_EE_ERROR_NON_FATAL_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + 0x00000158 + 0x1000 * (n)) +#define HWIO_IPA_IRQ_CLR_EE_ERROR_NON_FATAL_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + 0x00000158 + 0x1000 * (n)) +#define HWIO_IPA_IRQ_CLR_EE_ERROR_NON_FATAL_n_RMSK 0x3 +#define HWIO_IPA_IRQ_CLR_EE_ERROR_NON_FATAL_n_MAXn 3 +#define HWIO_IPA_IRQ_CLR_EE_ERROR_NON_FATAL_n_ATTR 0x1 +#define HWIO_IPA_IRQ_CLR_EE_ERROR_NON_FATAL_n_INI(n) \ + in_dword_masked(HWIO_IPA_IRQ_CLR_EE_ERROR_NON_FATAL_n_ADDR(n), HWIO_IPA_IRQ_CLR_EE_ERROR_NON_FATAL_n_RMSK) +#define HWIO_IPA_IRQ_CLR_EE_ERROR_NON_FATAL_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_IRQ_CLR_EE_ERROR_NON_FATAL_n_ADDR(n), mask) +#define HWIO_IPA_IRQ_CLR_EE_ERROR_NON_FATAL_n_PROC_ERR_IRQ_CLR_BMSK 0x2 +#define HWIO_IPA_IRQ_CLR_EE_ERROR_NON_FATAL_n_PROC_ERR_IRQ_CLR_SHFT 0x1 +#define HWIO_IPA_IRQ_CLR_EE_ERROR_NON_FATAL_n_DEAGGR_ERR_IRQ_CLR_BMSK 0x1 +#define HWIO_IPA_IRQ_CLR_EE_ERROR_NON_FATAL_n_DEAGGR_ERR_IRQ_CLR_SHFT 0x0 + +#define HWIO_IPA_FEC_NON_FATAL_ADDR_EE_n_ADDR(n) (IPA_EE_REG_BASE + 0x0000015c + 0x1000 * (n)) +#define HWIO_IPA_FEC_NON_FATAL_ADDR_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + 0x0000015c + 0x1000 * (n)) +#define HWIO_IPA_FEC_NON_FATAL_ADDR_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + 0x0000015c + 0x1000 * (n)) +#define HWIO_IPA_FEC_NON_FATAL_ADDR_EE_n_RMSK 0xffffffff +#define HWIO_IPA_FEC_NON_FATAL_ADDR_EE_n_MAXn 3 +#define HWIO_IPA_FEC_NON_FATAL_ADDR_EE_n_ATTR 0x1 +#define HWIO_IPA_FEC_NON_FATAL_ADDR_EE_n_INI(n) \ + in_dword_masked(HWIO_IPA_FEC_NON_FATAL_ADDR_EE_n_ADDR(n), HWIO_IPA_FEC_NON_FATAL_ADDR_EE_n_RMSK) +#define HWIO_IPA_FEC_NON_FATAL_ADDR_EE_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_FEC_NON_FATAL_ADDR_EE_n_ADDR(n), mask) +#define HWIO_IPA_FEC_NON_FATAL_ADDR_EE_n_ADDR_BMSK 0xffffffff +#define HWIO_IPA_FEC_NON_FATAL_ADDR_EE_n_ADDR_SHFT 0x0 + +#define HWIO_IPA_FEC_NON_FATAL_ADDR_MSB_EE_n_ADDR(n) (IPA_EE_REG_BASE + 0x00000160 + 0x1000 * (n)) +#define HWIO_IPA_FEC_NON_FATAL_ADDR_MSB_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + 0x00000160 + 0x1000 * (n)) +#define HWIO_IPA_FEC_NON_FATAL_ADDR_MSB_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + 0x00000160 + 0x1000 * (n)) +#define HWIO_IPA_FEC_NON_FATAL_ADDR_MSB_EE_n_RMSK 0xffffffff +#define HWIO_IPA_FEC_NON_FATAL_ADDR_MSB_EE_n_MAXn 3 +#define HWIO_IPA_FEC_NON_FATAL_ADDR_MSB_EE_n_ATTR 0x1 +#define HWIO_IPA_FEC_NON_FATAL_ADDR_MSB_EE_n_INI(n) \ + in_dword_masked(HWIO_IPA_FEC_NON_FATAL_ADDR_MSB_EE_n_ADDR(n), HWIO_IPA_FEC_NON_FATAL_ADDR_MSB_EE_n_RMSK) +#define HWIO_IPA_FEC_NON_FATAL_ADDR_MSB_EE_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_FEC_NON_FATAL_ADDR_MSB_EE_n_ADDR(n), mask) +#define HWIO_IPA_FEC_NON_FATAL_ADDR_MSB_EE_n_ADDR_BMSK 0xffffffff +#define HWIO_IPA_FEC_NON_FATAL_ADDR_MSB_EE_n_ADDR_SHFT 0x0 + +#define HWIO_IPA_FEC_NON_FATAL_ATTR_EE_n_ADDR(n) (IPA_EE_REG_BASE + 0x00000164 + 0x1000 * (n)) +#define HWIO_IPA_FEC_NON_FATAL_ATTR_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + 0x00000164 + 0x1000 * (n)) +#define HWIO_IPA_FEC_NON_FATAL_ATTR_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + 0x00000164 + 0x1000 * (n)) +#define HWIO_IPA_FEC_NON_FATAL_ATTR_EE_n_RMSK 0xffffffff +#define HWIO_IPA_FEC_NON_FATAL_ATTR_EE_n_MAXn 3 +#define HWIO_IPA_FEC_NON_FATAL_ATTR_EE_n_ATTR 0x1 +#define HWIO_IPA_FEC_NON_FATAL_ATTR_EE_n_INI(n) \ + in_dword_masked(HWIO_IPA_FEC_NON_FATAL_ATTR_EE_n_ADDR(n), HWIO_IPA_FEC_NON_FATAL_ATTR_EE_n_RMSK) +#define HWIO_IPA_FEC_NON_FATAL_ATTR_EE_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_FEC_NON_FATAL_ATTR_EE_n_ADDR(n), mask) +#define HWIO_IPA_FEC_NON_FATAL_ATTR_EE_n_ERROR_INFO_BMSK 0xffffffc0 +#define HWIO_IPA_FEC_NON_FATAL_ATTR_EE_n_ERROR_INFO_SHFT 0x6 +#define HWIO_IPA_FEC_NON_FATAL_ATTR_EE_n_OPCODE_BMSK 0x3f +#define HWIO_IPA_FEC_NON_FATAL_ATTR_EE_n_OPCODE_SHFT 0x0 + +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_0_ADDR (IPA_EE_REG_BASE + 0x00001100) +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_0_PHYS (IPA_EE_REG_BASE_PHYS + 0x00001100) +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_0_OFFS (IPA_EE_REG_BASE_OFFS + 0x00001100) +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_0_RMSK 0xff1ff7ff +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_0_ATTR 0x1 +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_0_IN \ + in_dword_masked(HWIO_IPA_MODEM_BEARER_INIT_VALUES_0_ADDR, HWIO_IPA_MODEM_BEARER_INIT_VALUES_0_RMSK) +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_0_INM(m) \ + in_dword_masked(HWIO_IPA_MODEM_BEARER_INIT_VALUES_0_ADDR, m) +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_0_MODEM_BEARER_INIT_BEARER_BMSK 0xff000000 +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_0_MODEM_BEARER_INIT_BEARER_SHFT 0x18 +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_0_MODEM_BEARER_INIT_CPHR_KEY_INDX_BMSK 0x1f0000 +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_0_MODEM_BEARER_INIT_CPHR_KEY_INDX_SHFT 0x10 +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_0_MODEM_BEARER_INIT_CPHR_ALGORITHM_BMSK 0xf000 +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_0_MODEM_BEARER_INIT_CPHR_ALGORITHM_SHFT 0xc +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_0_MODEM_BEARER_INIT_RDI_ENABLE_BMSK 0x400 +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_0_MODEM_BEARER_INIT_RDI_ENABLE_SHFT 0xa +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_0_MODEM_BEARER_INIT_RQI_ENABLE_BMSK 0x200 +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_0_MODEM_BEARER_INIT_RQI_ENABLE_SHFT 0x9 +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_0_MODEM_BEARER_INIT_SDAP_ENABLE_BMSK 0x100 +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_0_MODEM_BEARER_INIT_SDAP_ENABLE_SHFT 0x8 +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_0_MODEM_BEARER_INIT_L2_HDR_SIZE_BMSK 0xff +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_0_MODEM_BEARER_INIT_L2_HDR_SIZE_SHFT 0x0 + +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_1_ADDR (IPA_EE_REG_BASE + 0x00001104) +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_1_PHYS (IPA_EE_REG_BASE_PHYS + 0x00001104) +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_1_OFFS (IPA_EE_REG_BASE_OFFS + 0x00001104) +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_1_RMSK 0xffffffff +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_1_ATTR 0x1 +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_1_IN \ + in_dword_masked(HWIO_IPA_MODEM_BEARER_INIT_VALUES_1_ADDR, HWIO_IPA_MODEM_BEARER_INIT_VALUES_1_RMSK) +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_1_INM(m) \ + in_dword_masked(HWIO_IPA_MODEM_BEARER_INIT_VALUES_1_ADDR, m) +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_1_MODEM_BEARER_INIT_BEARER_SEL_BMSK 0x80000000 +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_1_MODEM_BEARER_INIT_BEARER_SEL_SHFT 0x1f +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_1_MODEM_BEARER_INIT_DIRECTION_BMSK 0x40000000 +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_1_MODEM_BEARER_INIT_DIRECTION_SHFT 0x1e +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_1_MODEM_BEARER_INIT_CPHR_OFST_START_BMSK 0x3fff0000 +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_1_MODEM_BEARER_INIT_CPHR_OFST_START_SHFT 0x10 +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_1_MODEM_BEARER_INIT_CPHR_OFST_KEYSTRM_BMSK 0xffff +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_1_MODEM_BEARER_INIT_CPHR_OFST_KEYSTRM_SHFT 0x0 + +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_2_ADDR (IPA_EE_REG_BASE + 0x00001108) +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_2_PHYS (IPA_EE_REG_BASE_PHYS + 0x00001108) +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_2_OFFS (IPA_EE_REG_BASE_OFFS + 0x00001108) +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_2_RMSK 0xff31ff +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_2_ATTR 0x1 +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_2_IN \ + in_dword_masked(HWIO_IPA_MODEM_BEARER_INIT_VALUES_2_ADDR, HWIO_IPA_MODEM_BEARER_INIT_VALUES_2_RMSK) +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_2_INM(m) \ + in_dword_masked(HWIO_IPA_MODEM_BEARER_INIT_VALUES_2_ADDR, m) +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_2_MODEM_BEARER_INIT_PDN_ID_BMSK 0xff0000 +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_2_MODEM_BEARER_INIT_PDN_ID_SHFT 0x10 +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_2_MODEM_BEARER_INIT_IP_MACI_SIZE_BMSK 0x3000 +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_2_MODEM_BEARER_INIT_IP_MACI_SIZE_SHFT 0xc +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_2_MODEM_BEARER_INIT_IP_KEY_INDX_BMSK 0x1f0 +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_2_MODEM_BEARER_INIT_IP_KEY_INDX_SHFT 0x4 +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_2_MODEM_BEARER_INIT_IP_ALGORITHM_BMSK 0xf +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_2_MODEM_BEARER_INIT_IP_ALGORITHM_SHFT 0x0 + +#define HWIO_IPA_MODEM_BEARER_CONFIG_VALUES_0_ADDR (IPA_EE_REG_BASE + 0x0000110c) +#define HWIO_IPA_MODEM_BEARER_CONFIG_VALUES_0_PHYS (IPA_EE_REG_BASE_PHYS + 0x0000110c) +#define HWIO_IPA_MODEM_BEARER_CONFIG_VALUES_0_OFFS (IPA_EE_REG_BASE_OFFS + 0x0000110c) +#define HWIO_IPA_MODEM_BEARER_CONFIG_VALUES_0_RMSK 0xffffffff +#define HWIO_IPA_MODEM_BEARER_CONFIG_VALUES_0_ATTR 0x1 +#define HWIO_IPA_MODEM_BEARER_CONFIG_VALUES_0_IN \ + in_dword_masked(HWIO_IPA_MODEM_BEARER_CONFIG_VALUES_0_ADDR, HWIO_IPA_MODEM_BEARER_CONFIG_VALUES_0_RMSK) +#define HWIO_IPA_MODEM_BEARER_CONFIG_VALUES_0_INM(m) \ + in_dword_masked(HWIO_IPA_MODEM_BEARER_CONFIG_VALUES_0_ADDR, m) +#define HWIO_IPA_MODEM_BEARER_CONFIG_VALUES_0_MODEM_BEARER_CONFIG_COUNT_F_BMSK 0xffffffff +#define HWIO_IPA_MODEM_BEARER_CONFIG_VALUES_0_MODEM_BEARER_CONFIG_COUNT_F_SHFT 0x0 + +#define HWIO_IPA_MODEM_BEARER_CONFIG_VALUES_1_ADDR (IPA_EE_REG_BASE + 0x00001110) +#define HWIO_IPA_MODEM_BEARER_CONFIG_VALUES_1_PHYS (IPA_EE_REG_BASE_PHYS + 0x00001110) +#define HWIO_IPA_MODEM_BEARER_CONFIG_VALUES_1_OFFS (IPA_EE_REG_BASE_OFFS + 0x00001110) +#define HWIO_IPA_MODEM_BEARER_CONFIG_VALUES_1_RMSK 0xffff +#define HWIO_IPA_MODEM_BEARER_CONFIG_VALUES_1_ATTR 0x1 +#define HWIO_IPA_MODEM_BEARER_CONFIG_VALUES_1_IN \ + in_dword_masked(HWIO_IPA_MODEM_BEARER_CONFIG_VALUES_1_ADDR, HWIO_IPA_MODEM_BEARER_CONFIG_VALUES_1_RMSK) +#define HWIO_IPA_MODEM_BEARER_CONFIG_VALUES_1_INM(m) \ + in_dword_masked(HWIO_IPA_MODEM_BEARER_CONFIG_VALUES_1_ADDR, m) +#define HWIO_IPA_MODEM_BEARER_CONFIG_VALUES_1_MODEM_BEARER_CONFIG_SIZE_F_BMSK 0xffff +#define HWIO_IPA_MODEM_BEARER_CONFIG_VALUES_1_MODEM_BEARER_CONFIG_SIZE_F_SHFT 0x0 + +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_3_ADDR (IPA_EE_REG_BASE + 0x00001114) +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_3_PHYS (IPA_EE_REG_BASE_PHYS + 0x00001114) +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_3_OFFS (IPA_EE_REG_BASE_OFFS + 0x00001114) +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_3_RMSK 0xffffffff +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_3_ATTR 0x1 +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_3_IN \ + in_dword_masked(HWIO_IPA_MODEM_BEARER_INIT_VALUES_3_ADDR, HWIO_IPA_MODEM_BEARER_INIT_VALUES_3_RMSK) +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_3_INM(m) \ + in_dword_masked(HWIO_IPA_MODEM_BEARER_INIT_VALUES_3_ADDR, m) +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_3_MODEM_BEARER_INIT_METADATA_BMSK 0xffffffff +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_3_MODEM_BEARER_INIT_METADATA_SHFT 0x0 + +#define HWIO_IPA_SECURED_PIPES_n_ADDR(n) (IPA_EE_REG_BASE + 0x00001120 + 0x4 * (n)) +#define HWIO_IPA_SECURED_PIPES_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + 0x00001120 + 0x4 * (n)) +#define HWIO_IPA_SECURED_PIPES_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + 0x00001120 + 0x4 * (n)) +#define HWIO_IPA_SECURED_PIPES_n_RMSK 0xffffffff +#define HWIO_IPA_SECURED_PIPES_n_MAXn 1 +#define HWIO_IPA_SECURED_PIPES_n_ATTR 0x3 +#define HWIO_IPA_SECURED_PIPES_n_INI(n) \ + in_dword_masked(HWIO_IPA_SECURED_PIPES_n_ADDR(n), HWIO_IPA_SECURED_PIPES_n_RMSK) +#define HWIO_IPA_SECURED_PIPES_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_SECURED_PIPES_n_ADDR(n), mask) +#define HWIO_IPA_SECURED_PIPES_n_OUTI(n,val) \ + out_dword(HWIO_IPA_SECURED_PIPES_n_ADDR(n),val) +#define HWIO_IPA_SECURED_PIPES_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_SECURED_PIPES_n_ADDR(n),mask,val,HWIO_IPA_SECURED_PIPES_n_INI(n)) +#define HWIO_IPA_SECURED_PIPES_n_ENDPOINTS_BMSK 0xffffffff +#define HWIO_IPA_SECURED_PIPES_n_ENDPOINTS_SHFT 0x0 + +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_CFG_ADDR (IPA_EE_REG_BASE + 0x00001140) +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_CFG_PHYS (IPA_EE_REG_BASE_PHYS + 0x00001140) +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_CFG_OFFS (IPA_EE_REG_BASE_OFFS + 0x00001140) +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_CFG_RMSK 0x3 +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_CFG_ATTR 0x3 +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_CFG_IN \ + in_dword_masked(HWIO_IPA_MODEM_BEARER_INIT_VALUES_CFG_ADDR, HWIO_IPA_MODEM_BEARER_INIT_VALUES_CFG_RMSK) +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_MODEM_BEARER_INIT_VALUES_CFG_ADDR, m) +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_CFG_OUT(v) \ + out_dword(HWIO_IPA_MODEM_BEARER_INIT_VALUES_CFG_ADDR,v) +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_MODEM_BEARER_INIT_VALUES_CFG_ADDR,m,v,HWIO_IPA_MODEM_BEARER_INIT_VALUES_CFG_IN) +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_CFG_BEARER_CONTEXT_INDEX_SEL_BMSK 0x3 +#define HWIO_IPA_MODEM_BEARER_INIT_VALUES_CFG_BEARER_CONTEXT_INDEX_SEL_SHFT 0x0 + +#define HWIO_IPA_UC_REGS_INSIDE_IPA__CONTROL_ADDR (IPA_EE_REG_BASE + 0x00001200) +#define HWIO_IPA_UC_REGS_INSIDE_IPA__CONTROL_PHYS (IPA_EE_REG_BASE_PHYS + 0x00001200) +#define HWIO_IPA_UC_REGS_INSIDE_IPA__CONTROL_OFFS (IPA_EE_REG_BASE_OFFS + 0x00001200) +#define HWIO_IPA_UC_REGS_INSIDE_IPA__CONTROL_RMSK 0x1 +#define HWIO_IPA_UC_REGS_INSIDE_IPA__CONTROL_ATTR 0x3 +#define HWIO_IPA_UC_REGS_INSIDE_IPA__CONTROL_IN \ + in_dword_masked(HWIO_IPA_UC_REGS_INSIDE_IPA__CONTROL_ADDR, HWIO_IPA_UC_REGS_INSIDE_IPA__CONTROL_RMSK) +#define HWIO_IPA_UC_REGS_INSIDE_IPA__CONTROL_INM(m) \ + in_dword_masked(HWIO_IPA_UC_REGS_INSIDE_IPA__CONTROL_ADDR, m) +#define HWIO_IPA_UC_REGS_INSIDE_IPA__CONTROL_OUT(v) \ + out_dword(HWIO_IPA_UC_REGS_INSIDE_IPA__CONTROL_ADDR,v) +#define HWIO_IPA_UC_REGS_INSIDE_IPA__CONTROL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_REGS_INSIDE_IPA__CONTROL_ADDR,m,v,HWIO_IPA_UC_REGS_INSIDE_IPA__CONTROL_IN) +#define HWIO_IPA_UC_REGS_INSIDE_IPA__CONTROL_UC_ENABLE_BMSK 0x1 +#define HWIO_IPA_UC_REGS_INSIDE_IPA__CONTROL_UC_ENABLE_SHFT 0x0 + +#define HWIO_IPA_UC_REGS_INSIDE_IPA__NMI_ADDR (IPA_EE_REG_BASE + 0x00001204) +#define HWIO_IPA_UC_REGS_INSIDE_IPA__NMI_PHYS (IPA_EE_REG_BASE_PHYS + 0x00001204) +#define HWIO_IPA_UC_REGS_INSIDE_IPA__NMI_OFFS (IPA_EE_REG_BASE_OFFS + 0x00001204) +#define HWIO_IPA_UC_REGS_INSIDE_IPA__NMI_RMSK 0x1 +#define HWIO_IPA_UC_REGS_INSIDE_IPA__NMI_ATTR 0x2 +#define HWIO_IPA_UC_REGS_INSIDE_IPA__NMI_OUT(v) \ + out_dword(HWIO_IPA_UC_REGS_INSIDE_IPA__NMI_ADDR,v) +#define HWIO_IPA_UC_REGS_INSIDE_IPA__NMI_PULSE_BMSK 0x1 +#define HWIO_IPA_UC_REGS_INSIDE_IPA__NMI_PULSE_SHFT 0x0 + +#define HWIO_IPA_DRBIP_CFG_ADDR (IPA_EE_REG_BASE + 0x00001400) +#define HWIO_IPA_DRBIP_CFG_PHYS (IPA_EE_REG_BASE_PHYS + 0x00001400) +#define HWIO_IPA_DRBIP_CFG_OFFS (IPA_EE_REG_BASE_OFFS + 0x00001400) +#define HWIO_IPA_DRBIP_CFG_RMSK 0x1 +#define HWIO_IPA_DRBIP_CFG_ATTR 0x3 +#define HWIO_IPA_DRBIP_CFG_IN \ + in_dword_masked(HWIO_IPA_DRBIP_CFG_ADDR, HWIO_IPA_DRBIP_CFG_RMSK) +#define HWIO_IPA_DRBIP_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_DRBIP_CFG_ADDR, m) +#define HWIO_IPA_DRBIP_CFG_OUT(v) \ + out_dword(HWIO_IPA_DRBIP_CFG_ADDR,v) +#define HWIO_IPA_DRBIP_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_DRBIP_CFG_ADDR,m,v,HWIO_IPA_DRBIP_CFG_IN) +#define HWIO_IPA_DRBIP_CFG_OPERATION_MODE_BMSK 0x1 +#define HWIO_IPA_DRBIP_CFG_OPERATION_MODE_SHFT 0x0 + +#define HWIO_IPA_RQOS_CFG_ADDR (IPA_EE_REG_BASE + 0x00001404) +#define HWIO_IPA_RQOS_CFG_PHYS (IPA_EE_REG_BASE_PHYS + 0x00001404) +#define HWIO_IPA_RQOS_CFG_OFFS (IPA_EE_REG_BASE_OFFS + 0x00001404) +#define HWIO_IPA_RQOS_CFG_RMSK 0x7ffffff +#define HWIO_IPA_RQOS_CFG_ATTR 0x3 +#define HWIO_IPA_RQOS_CFG_IN \ + in_dword_masked(HWIO_IPA_RQOS_CFG_ADDR, HWIO_IPA_RQOS_CFG_RMSK) +#define HWIO_IPA_RQOS_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_RQOS_CFG_ADDR, m) +#define HWIO_IPA_RQOS_CFG_OUT(v) \ + out_dword(HWIO_IPA_RQOS_CFG_ADDR,v) +#define HWIO_IPA_RQOS_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_RQOS_CFG_ADDR,m,v,HWIO_IPA_RQOS_CFG_IN) +#define HWIO_IPA_RQOS_CFG_RQOS_NAS_UNKNOWN_PROTOCOL_PKT_CNT_RESET_BMSK 0x4000000 +#define HWIO_IPA_RQOS_CFG_RQOS_NAS_UNKNOWN_PROTOCOL_PKT_CNT_RESET_SHFT 0x1a +#define HWIO_IPA_RQOS_CFG_RQOS_NAS_REDUCE_LEVEL_EN_BMSK 0x2000000 +#define HWIO_IPA_RQOS_CFG_RQOS_NAS_REDUCE_LEVEL_EN_SHFT 0x19 +#define HWIO_IPA_RQOS_CFG_RQOS_AS_REDUCE_LEVEL_EN_BMSK 0x1000000 +#define HWIO_IPA_RQOS_CFG_RQOS_AS_REDUCE_LEVEL_EN_SHFT 0x18 +#define HWIO_IPA_RQOS_CFG_RQOS_NAS_REDUCE_LEVEL_BMSK 0xff0000 +#define HWIO_IPA_RQOS_CFG_RQOS_NAS_REDUCE_LEVEL_SHFT 0x10 +#define HWIO_IPA_RQOS_CFG_RQOS_AS_REDUCE_LEVEL_BMSK 0xff00 +#define HWIO_IPA_RQOS_CFG_RQOS_AS_REDUCE_LEVEL_SHFT 0x8 +#define HWIO_IPA_RQOS_CFG_RQOS_NOTIFICATION_PIPE_BMSK 0xff +#define HWIO_IPA_RQOS_CFG_RQOS_NOTIFICATION_PIPE_SHFT 0x0 + +#define HWIO_IPA_RQOS_NAS_UNKNOWN_PROTOCOL_PKT_CNT_ADDR (IPA_EE_REG_BASE + 0x00001408) +#define HWIO_IPA_RQOS_NAS_UNKNOWN_PROTOCOL_PKT_CNT_PHYS (IPA_EE_REG_BASE_PHYS + 0x00001408) +#define HWIO_IPA_RQOS_NAS_UNKNOWN_PROTOCOL_PKT_CNT_OFFS (IPA_EE_REG_BASE_OFFS + 0x00001408) +#define HWIO_IPA_RQOS_NAS_UNKNOWN_PROTOCOL_PKT_CNT_RMSK 0xffffffff +#define HWIO_IPA_RQOS_NAS_UNKNOWN_PROTOCOL_PKT_CNT_ATTR 0x1 +#define HWIO_IPA_RQOS_NAS_UNKNOWN_PROTOCOL_PKT_CNT_IN \ + in_dword_masked(HWIO_IPA_RQOS_NAS_UNKNOWN_PROTOCOL_PKT_CNT_ADDR, HWIO_IPA_RQOS_NAS_UNKNOWN_PROTOCOL_PKT_CNT_RMSK) +#define HWIO_IPA_RQOS_NAS_UNKNOWN_PROTOCOL_PKT_CNT_INM(m) \ + in_dword_masked(HWIO_IPA_RQOS_NAS_UNKNOWN_PROTOCOL_PKT_CNT_ADDR, m) +#define HWIO_IPA_RQOS_NAS_UNKNOWN_PROTOCOL_PKT_CNT_COUNT_BMSK 0xffffffff +#define HWIO_IPA_RQOS_NAS_UNKNOWN_PROTOCOL_PKT_CNT_COUNT_SHFT 0x0 + +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_0_ADDR (IPA_EE_REG_BASE + 0x0000140c) +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_0_PHYS (IPA_EE_REG_BASE_PHYS + 0x0000140c) +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_0_OFFS (IPA_EE_REG_BASE_OFFS + 0x0000140c) +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_0_RMSK 0xffffffff +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_0_ATTR 0x3 +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_0_IN \ + in_dword_masked(HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_0_ADDR, HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_0_RMSK) +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_0_INM(m) \ + in_dword_masked(HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_0_ADDR, m) +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_0_OUT(v) \ + out_dword(HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_0_ADDR,v) +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_0_ADDR,m,v,HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_0_IN) +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_0_PROTOCOL_3_BMSK 0xff000000 +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_0_PROTOCOL_3_SHFT 0x18 +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_0_PROTOCOL_2_BMSK 0xff0000 +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_0_PROTOCOL_2_SHFT 0x10 +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_0_PROTOCOL_1_BMSK 0xff00 +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_0_PROTOCOL_1_SHFT 0x8 +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_0_PROTOCOL_0_BMSK 0xff +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_0_PROTOCOL_0_SHFT 0x0 + +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_1_ADDR (IPA_EE_REG_BASE + 0x00001410) +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_1_PHYS (IPA_EE_REG_BASE_PHYS + 0x00001410) +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_1_OFFS (IPA_EE_REG_BASE_OFFS + 0x00001410) +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_1_RMSK 0xffffffff +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_1_ATTR 0x3 +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_1_IN \ + in_dword_masked(HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_1_ADDR, HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_1_RMSK) +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_1_INM(m) \ + in_dword_masked(HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_1_ADDR, m) +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_1_OUT(v) \ + out_dword(HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_1_ADDR,v) +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_1_ADDR,m,v,HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_1_IN) +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_1_PROTOCOL_3_BMSK 0xff000000 +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_1_PROTOCOL_3_SHFT 0x18 +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_1_PROTOCOL_2_BMSK 0xff0000 +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_1_PROTOCOL_2_SHFT 0x10 +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_1_PROTOCOL_1_BMSK 0xff00 +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_1_PROTOCOL_1_SHFT 0x8 +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_1_PROTOCOL_0_BMSK 0xff +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_1_PROTOCOL_0_SHFT 0x0 + +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_2_ADDR (IPA_EE_REG_BASE + 0x00001414) +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_2_PHYS (IPA_EE_REG_BASE_PHYS + 0x00001414) +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_2_OFFS (IPA_EE_REG_BASE_OFFS + 0x00001414) +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_2_RMSK 0xffffffff +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_2_ATTR 0x3 +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_2_IN \ + in_dword_masked(HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_2_ADDR, HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_2_RMSK) +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_2_INM(m) \ + in_dword_masked(HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_2_ADDR, m) +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_2_OUT(v) \ + out_dword(HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_2_ADDR,v) +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_2_ADDR,m,v,HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_2_IN) +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_2_PROTOCOL_3_BMSK 0xff000000 +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_2_PROTOCOL_3_SHFT 0x18 +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_2_PROTOCOL_2_BMSK 0xff0000 +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_2_PROTOCOL_2_SHFT 0x10 +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_2_PROTOCOL_1_BMSK 0xff00 +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_2_PROTOCOL_1_SHFT 0x8 +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_2_PROTOCOL_0_BMSK 0xff +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_2_PROTOCOL_0_SHFT 0x0 + +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_3_ADDR (IPA_EE_REG_BASE + 0x00001418) +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_3_PHYS (IPA_EE_REG_BASE_PHYS + 0x00001418) +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_3_OFFS (IPA_EE_REG_BASE_OFFS + 0x00001418) +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_3_RMSK 0xffffffff +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_3_ATTR 0x3 +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_3_IN \ + in_dword_masked(HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_3_ADDR, HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_3_RMSK) +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_3_INM(m) \ + in_dword_masked(HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_3_ADDR, m) +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_3_OUT(v) \ + out_dword(HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_3_ADDR,v) +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_3_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_3_ADDR,m,v,HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_3_IN) +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_3_PROTOCOL_3_BMSK 0xff000000 +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_3_PROTOCOL_3_SHFT 0x18 +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_3_PROTOCOL_2_BMSK 0xff0000 +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_3_PROTOCOL_2_SHFT 0x10 +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_3_PROTOCOL_1_BMSK 0xff00 +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_3_PROTOCOL_1_SHFT 0x8 +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_3_PROTOCOL_0_BMSK 0xff +#define HWIO_IPA_RQOS_ILLEGAL_PROTOCOL_3_PROTOCOL_0_SHFT 0x0 + +#define HWIO_IPA_RQOS_THRESHOLD_CFG_ADDR (IPA_EE_REG_BASE + 0x0000141c) +#define HWIO_IPA_RQOS_THRESHOLD_CFG_PHYS (IPA_EE_REG_BASE_PHYS + 0x0000141c) +#define HWIO_IPA_RQOS_THRESHOLD_CFG_OFFS (IPA_EE_REG_BASE_OFFS + 0x0000141c) +#define HWIO_IPA_RQOS_THRESHOLD_CFG_RMSK 0xf10fff +#define HWIO_IPA_RQOS_THRESHOLD_CFG_ATTR 0x3 +#define HWIO_IPA_RQOS_THRESHOLD_CFG_IN \ + in_dword_masked(HWIO_IPA_RQOS_THRESHOLD_CFG_ADDR, HWIO_IPA_RQOS_THRESHOLD_CFG_RMSK) +#define HWIO_IPA_RQOS_THRESHOLD_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_RQOS_THRESHOLD_CFG_ADDR, m) +#define HWIO_IPA_RQOS_THRESHOLD_CFG_OUT(v) \ + out_dword(HWIO_IPA_RQOS_THRESHOLD_CFG_ADDR,v) +#define HWIO_IPA_RQOS_THRESHOLD_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_RQOS_THRESHOLD_CFG_ADDR,m,v,HWIO_IPA_RQOS_THRESHOLD_CFG_IN) +#define HWIO_IPA_RQOS_THRESHOLD_CFG_THRESHOLD_TIMER_GRAN_SEL_BMSK 0xf00000 +#define HWIO_IPA_RQOS_THRESHOLD_CFG_THRESHOLD_TIMER_GRAN_SEL_SHFT 0x14 +#define HWIO_IPA_RQOS_THRESHOLD_CFG_THRESHOLD_EN_BMSK 0x10000 +#define HWIO_IPA_RQOS_THRESHOLD_CFG_THRESHOLD_EN_SHFT 0x10 +#define HWIO_IPA_RQOS_THRESHOLD_CFG_THRESHOLD_BMSK 0xfff +#define HWIO_IPA_RQOS_THRESHOLD_CFG_THRESHOLD_SHFT 0x0 + +#define HWIO_IPA_SET_UC_IRQ_EE_n_ADDR(n) (IPA_EE_REG_BASE + 0x000020e0 + 0x4 * (n)) +#define HWIO_IPA_SET_UC_IRQ_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + 0x000020e0 + 0x4 * (n)) +#define HWIO_IPA_SET_UC_IRQ_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + 0x000020e0 + 0x4 * (n)) +#define HWIO_IPA_SET_UC_IRQ_EE_n_RMSK 0xf +#define HWIO_IPA_SET_UC_IRQ_EE_n_MAXn 3 +#define HWIO_IPA_SET_UC_IRQ_EE_n_ATTR 0x2 +#define HWIO_IPA_SET_UC_IRQ_EE_n_OUTI(n,val) \ + out_dword(HWIO_IPA_SET_UC_IRQ_EE_n_ADDR(n),val) +#define HWIO_IPA_SET_UC_IRQ_EE_n_SET_UC_IRQ_3_BMSK 0x8 +#define HWIO_IPA_SET_UC_IRQ_EE_n_SET_UC_IRQ_3_SHFT 0x3 +#define HWIO_IPA_SET_UC_IRQ_EE_n_SET_UC_IRQ_2_BMSK 0x4 +#define HWIO_IPA_SET_UC_IRQ_EE_n_SET_UC_IRQ_2_SHFT 0x2 +#define HWIO_IPA_SET_UC_IRQ_EE_n_SET_UC_IRQ_1_BMSK 0x2 +#define HWIO_IPA_SET_UC_IRQ_EE_n_SET_UC_IRQ_1_SHFT 0x1 +#define HWIO_IPA_SET_UC_IRQ_EE_n_SET_UC_IRQ_0_BMSK 0x1 +#define HWIO_IPA_SET_UC_IRQ_EE_n_SET_UC_IRQ_0_SHFT 0x0 + +#define HWIO_IPA_SET_UC_IRQ_ALL_EES_ADDR (IPA_EE_REG_BASE + 0x000020f0) +#define HWIO_IPA_SET_UC_IRQ_ALL_EES_PHYS (IPA_EE_REG_BASE_PHYS + 0x000020f0) +#define HWIO_IPA_SET_UC_IRQ_ALL_EES_OFFS (IPA_EE_REG_BASE_OFFS + 0x000020f0) +#define HWIO_IPA_SET_UC_IRQ_ALL_EES_RMSK 0xf +#define HWIO_IPA_SET_UC_IRQ_ALL_EES_ATTR 0x2 +#define HWIO_IPA_SET_UC_IRQ_ALL_EES_OUT(v) \ + out_dword(HWIO_IPA_SET_UC_IRQ_ALL_EES_ADDR,v) +#define HWIO_IPA_SET_UC_IRQ_ALL_EES_SET_UC_IRQ_3_BMSK 0x8 +#define HWIO_IPA_SET_UC_IRQ_ALL_EES_SET_UC_IRQ_3_SHFT 0x3 +#define HWIO_IPA_SET_UC_IRQ_ALL_EES_SET_UC_IRQ_2_BMSK 0x4 +#define HWIO_IPA_SET_UC_IRQ_ALL_EES_SET_UC_IRQ_2_SHFT 0x2 +#define HWIO_IPA_SET_UC_IRQ_ALL_EES_SET_UC_IRQ_1_BMSK 0x2 +#define HWIO_IPA_SET_UC_IRQ_ALL_EES_SET_UC_IRQ_1_SHFT 0x1 +#define HWIO_IPA_SET_UC_IRQ_ALL_EES_SET_UC_IRQ_0_BMSK 0x1 +#define HWIO_IPA_SET_UC_IRQ_ALL_EES_SET_UC_IRQ_0_SHFT 0x0 + +#define HWIO_IPA_UCP_RESUME_ADDR (IPA_EE_REG_BASE + 0x000030e0) +#define HWIO_IPA_UCP_RESUME_PHYS (IPA_EE_REG_BASE_PHYS + 0x000030e0) +#define HWIO_IPA_UCP_RESUME_OFFS (IPA_EE_REG_BASE_OFFS + 0x000030e0) +#define HWIO_IPA_UCP_RESUME_RMSK 0x1f19ff36 +#define HWIO_IPA_UCP_RESUME_ATTR 0x2 +#define HWIO_IPA_UCP_RESUME_OUT(v) \ + out_dword(HWIO_IPA_UCP_RESUME_ADDR,v) +#define HWIO_IPA_UCP_RESUME_IPA_UCP_RESUME_POST_UC_HW_PROCESSING_DIS_BMSK 0x10000000 +#define HWIO_IPA_UCP_RESUME_IPA_UCP_RESUME_POST_UC_HW_PROCESSING_DIS_SHFT 0x1c +#define HWIO_IPA_UCP_RESUME_IPA_UCP_RESUME_REFTECH_CONTEXT_BMSK 0x8000000 +#define HWIO_IPA_UCP_RESUME_IPA_UCP_RESUME_REFTECH_CONTEXT_SHFT 0x1b +#define HWIO_IPA_UCP_RESUME_IPA_UCP_RESUME_COPY_HDR_EN_BMSK 0x4000000 +#define HWIO_IPA_UCP_RESUME_IPA_UCP_RESUME_COPY_HDR_EN_SHFT 0x1a +#define HWIO_IPA_UCP_RESUME_IPA_UCP_RESUME_TTL_EXCEPTION_BMSK 0x2000000 +#define HWIO_IPA_UCP_RESUME_IPA_UCP_RESUME_TTL_EXCEPTION_SHFT 0x19 +#define HWIO_IPA_UCP_RESUME_IPA_UCP_RESUME_TTL_UPDATED_BMSK 0x1000000 +#define HWIO_IPA_UCP_RESUME_IPA_UCP_RESUME_TTL_UPDATED_SHFT 0x18 +#define HWIO_IPA_UCP_RESUME_IPA_UCP_RESUME_METADATA_OVERRIDE_BMSK 0x100000 +#define HWIO_IPA_UCP_RESUME_IPA_UCP_RESUME_METADATA_OVERRIDE_SHFT 0x14 +#define HWIO_IPA_UCP_RESUME_IPA_UCP_RESUME_NEXT_PKT_PARSER_DIS_BMSK 0x80000 +#define HWIO_IPA_UCP_RESUME_IPA_UCP_RESUME_NEXT_PKT_PARSER_DIS_SHFT 0x13 +#define HWIO_IPA_UCP_RESUME_IPA_UCP_RESUME_EXCEPTION_BMSK 0x10000 +#define HWIO_IPA_UCP_RESUME_IPA_UCP_RESUME_EXCEPTION_SHFT 0x10 +#define HWIO_IPA_UCP_RESUME_IPA_UCP_RESUME_DEST_PIPE_VALUE_BMSK 0xff00 +#define HWIO_IPA_UCP_RESUME_IPA_UCP_RESUME_DEST_PIPE_VALUE_SHFT 0x8 +#define HWIO_IPA_UCP_RESUME_IPA_UCP_RESUME_TPORT_CHECKSUM_FIX_EN_BMSK 0x20 +#define HWIO_IPA_UCP_RESUME_IPA_UCP_RESUME_TPORT_CHECKSUM_FIX_EN_SHFT 0x5 +#define HWIO_IPA_UCP_RESUME_IPA_UCP_RESUME_IP_CHECKSUM_FIX_EN_BMSK 0x10 +#define HWIO_IPA_UCP_RESUME_IPA_UCP_RESUME_IP_CHECKSUM_FIX_EN_SHFT 0x4 +#define HWIO_IPA_UCP_RESUME_IPA_UCP_RESUME_DEST_PIPE_OVERRIDE_BMSK 0x4 +#define HWIO_IPA_UCP_RESUME_IPA_UCP_RESUME_DEST_PIPE_OVERRIDE_SHFT 0x2 +#define HWIO_IPA_UCP_RESUME_IPA_UCP_RESUME_NEXT_ROUND_EN_BMSK 0x2 +#define HWIO_IPA_UCP_RESUME_IPA_UCP_RESUME_NEXT_ROUND_EN_SHFT 0x1 + +#define HWIO_IPA_UCP_RESUME_METADATA_ADDR (IPA_EE_REG_BASE + 0x000030e4) +#define HWIO_IPA_UCP_RESUME_METADATA_PHYS (IPA_EE_REG_BASE_PHYS + 0x000030e4) +#define HWIO_IPA_UCP_RESUME_METADATA_OFFS (IPA_EE_REG_BASE_OFFS + 0x000030e4) +#define HWIO_IPA_UCP_RESUME_METADATA_RMSK 0xffffffff +#define HWIO_IPA_UCP_RESUME_METADATA_ATTR 0x3 +#define HWIO_IPA_UCP_RESUME_METADATA_IN \ + in_dword_masked(HWIO_IPA_UCP_RESUME_METADATA_ADDR, HWIO_IPA_UCP_RESUME_METADATA_RMSK) +#define HWIO_IPA_UCP_RESUME_METADATA_INM(m) \ + in_dword_masked(HWIO_IPA_UCP_RESUME_METADATA_ADDR, m) +#define HWIO_IPA_UCP_RESUME_METADATA_OUT(v) \ + out_dword(HWIO_IPA_UCP_RESUME_METADATA_ADDR,v) +#define HWIO_IPA_UCP_RESUME_METADATA_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UCP_RESUME_METADATA_ADDR,m,v,HWIO_IPA_UCP_RESUME_METADATA_IN) +#define HWIO_IPA_UCP_RESUME_METADATA_METADATA_BMSK 0xffffffff +#define HWIO_IPA_UCP_RESUME_METADATA_METADATA_SHFT 0x0 + +#define HWIO_IPA_PROC_UCP_CFG_ADDR (IPA_EE_REG_BASE + 0x000030e8) +#define HWIO_IPA_PROC_UCP_CFG_PHYS (IPA_EE_REG_BASE_PHYS + 0x000030e8) +#define HWIO_IPA_PROC_UCP_CFG_OFFS (IPA_EE_REG_BASE_OFFS + 0x000030e8) +#define HWIO_IPA_PROC_UCP_CFG_RMSK 0x1 +#define HWIO_IPA_PROC_UCP_CFG_ATTR 0x3 +#define HWIO_IPA_PROC_UCP_CFG_IN \ + in_dword_masked(HWIO_IPA_PROC_UCP_CFG_ADDR, HWIO_IPA_PROC_UCP_CFG_RMSK) +#define HWIO_IPA_PROC_UCP_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_PROC_UCP_CFG_ADDR, m) +#define HWIO_IPA_PROC_UCP_CFG_OUT(v) \ + out_dword(HWIO_IPA_PROC_UCP_CFG_ADDR,v) +#define HWIO_IPA_PROC_UCP_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_PROC_UCP_CFG_ADDR,m,v,HWIO_IPA_PROC_UCP_CFG_IN) +#define HWIO_IPA_PROC_UCP_CFG_IPA_UCP_IRQ_SW_EVENTS_UC_MUX_EN_BMSK 0x1 +#define HWIO_IPA_PROC_UCP_CFG_IPA_UCP_IRQ_SW_EVENTS_UC_MUX_EN_SHFT 0x0 + +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_0_ADDR (IPA_EE_REG_BASE + 0x000030ec) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_0_PHYS (IPA_EE_REG_BASE_PHYS + 0x000030ec) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_0_OFFS (IPA_EE_REG_BASE_OFFS + 0x000030ec) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_0_RMSK 0x3ffff +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_0_ATTR 0x3 +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_0_IN \ + in_dword_masked(HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_0_ADDR, HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_0_RMSK) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_0_INM(m) \ + in_dword_masked(HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_0_ADDR, m) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_0_OUT(v) \ + out_dword(HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_0_ADDR,v) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_0_ADDR,m,v,HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_0_IN) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_0_IPA_UC_PKT_PROCESS_CONTEXT_BASE_BMSK 0x3ffff +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_0_IPA_UC_PKT_PROCESS_CONTEXT_BASE_SHFT 0x0 + +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_1_ADDR (IPA_EE_REG_BASE + 0x000030f0) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_1_PHYS (IPA_EE_REG_BASE_PHYS + 0x000030f0) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_1_OFFS (IPA_EE_REG_BASE_OFFS + 0x000030f0) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_1_RMSK 0x3ffff +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_1_ATTR 0x3 +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_1_IN \ + in_dword_masked(HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_1_ADDR, HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_1_RMSK) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_1_INM(m) \ + in_dword_masked(HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_1_ADDR, m) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_1_OUT(v) \ + out_dword(HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_1_ADDR,v) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_1_ADDR,m,v,HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_1_IN) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_1_IPA_UC_PKT_PROCESS_PKT_BASE_BMSK 0x3ffff +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_1_IPA_UC_PKT_PROCESS_PKT_BASE_SHFT 0x0 + +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_2_ADDR (IPA_EE_REG_BASE + 0x000030f4) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_2_PHYS (IPA_EE_REG_BASE_PHYS + 0x000030f4) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_2_OFFS (IPA_EE_REG_BASE_OFFS + 0x000030f4) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_2_RMSK 0x3ffff +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_2_ATTR 0x3 +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_2_IN \ + in_dword_masked(HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_2_ADDR, HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_2_RMSK) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_2_INM(m) \ + in_dword_masked(HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_2_ADDR, m) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_2_OUT(v) \ + out_dword(HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_2_ADDR,v) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_2_ADDR,m,v,HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_2_IN) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_2_IPA_UC_PKT_PROCESS_HDR_BASE_BMSK 0x3ffff +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_2_IPA_UC_PKT_PROCESS_HDR_BASE_SHFT 0x0 + +/*---------------------------------------------------------------------------- + * MODULE: IPA_DEBUG + *--------------------------------------------------------------------------*/ + +#define IPA_DEBUG_REG_BASE (IPA_0_IPA_WRAPPER_BASE + 0x00148000) +#define IPA_DEBUG_REG_BASE_PHYS (IPA_0_IPA_WRAPPER_BASE_PHYS + 0x00148000) +#define IPA_DEBUG_REG_BASE_OFFS 0x00148000 + +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_ADDR (IPA_DEBUG_REG_BASE + 0x00000000) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000000) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000000) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_RMSK 0xf3f3f77 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_ATTR 0x3 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_IN \ + in_dword_masked(HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_ADDR, HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_RMSK) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_ADDR, m) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_OUT(v) \ + out_dword(HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_ADDR,v) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_ADDR,m,v,HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_IN) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_ALLOC_LIST_TYPE_BMSK 0xc000000 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_ALLOC_LIST_TYPE_SHFT 0x1a +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_ALLOC_HOLD_BMSK 0x1000000 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_ALLOC_HOLD_SHFT 0x18 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_ALLOC_LIST_ID_BMSK 0x3f0000 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_ALLOC_LIST_ID_SHFT 0x10 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_ALLOC_RSRC_ID_CURR_BMSK 0x3f00 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_ALLOC_RSRC_ID_CURR_SHFT 0x8 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_ALLOC_RSRC_GRP_BMSK 0x70 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_ALLOC_RSRC_GRP_SHFT 0x4 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_ALLOC_RSRC_TYPE_BMSK 0x7 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_ALLOC_RSRC_TYPE_SHFT 0x0 + +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_SRCH_CFG_ADDR (IPA_DEBUG_REG_BASE + 0x00000004) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_SRCH_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000004) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_SRCH_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000004) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_SRCH_CFG_RMSK 0xff7f7 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_SRCH_CFG_ATTR 0x3 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_SRCH_CFG_IN \ + in_dword_masked(HWIO_IPA_RSRC_MNGR_SW_ACCESS_SRCH_CFG_ADDR, HWIO_IPA_RSRC_MNGR_SW_ACCESS_SRCH_CFG_RMSK) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_SRCH_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_RSRC_MNGR_SW_ACCESS_SRCH_CFG_ADDR, m) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_SRCH_CFG_OUT(v) \ + out_dword(HWIO_IPA_RSRC_MNGR_SW_ACCESS_SRCH_CFG_ADDR,v) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_SRCH_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_RSRC_MNGR_SW_ACCESS_SRCH_CFG_ADDR,m,v,HWIO_IPA_RSRC_MNGR_SW_ACCESS_SRCH_CFG_IN) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_SRCH_CFG_SRCH_LIST_TYPE_BMSK 0xc0000 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_SRCH_CFG_SRCH_LIST_TYPE_SHFT 0x12 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_SRCH_CFG_SRCH_LIST_ID_BMSK 0x3f000 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_SRCH_CFG_SRCH_LIST_ID_SHFT 0xc +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_SRCH_CFG_SRCH_RSRC_CNT_BMSK 0x7f0 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_SRCH_CFG_SRCH_RSRC_CNT_SHFT 0x4 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_SRCH_CFG_SRCH_RSRC_TYPE_BMSK 0x7 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_SRCH_CFG_SRCH_RSRC_TYPE_SHFT 0x0 + +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_REL_CFG_ADDR (IPA_DEBUG_REG_BASE + 0x00000008) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_REL_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000008) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_REL_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000008) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_REL_CFG_RMSK 0xff3f77 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_REL_CFG_ATTR 0x3 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_REL_CFG_IN \ + in_dword_masked(HWIO_IPA_RSRC_MNGR_SW_ACCESS_REL_CFG_ADDR, HWIO_IPA_RSRC_MNGR_SW_ACCESS_REL_CFG_RMSK) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_REL_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_RSRC_MNGR_SW_ACCESS_REL_CFG_ADDR, m) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_REL_CFG_OUT(v) \ + out_dword(HWIO_IPA_RSRC_MNGR_SW_ACCESS_REL_CFG_ADDR,v) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_REL_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_RSRC_MNGR_SW_ACCESS_REL_CFG_ADDR,m,v,HWIO_IPA_RSRC_MNGR_SW_ACCESS_REL_CFG_IN) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_REL_CFG_REL_LIST_TYPE_BMSK 0xc00000 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_REL_CFG_REL_LIST_TYPE_SHFT 0x16 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_REL_CFG_REL_LIST_ID_BMSK 0x3f0000 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_REL_CFG_REL_LIST_ID_SHFT 0x10 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_REL_CFG_REL_RSRC_ID_BMSK 0x3f00 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_REL_CFG_REL_RSRC_ID_SHFT 0x8 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_REL_CFG_REL_RSRC_GRP_BMSK 0x70 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_REL_CFG_REL_RSRC_GRP_SHFT 0x4 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_REL_CFG_REL_RSRC_TYPE_BMSK 0x7 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_REL_CFG_REL_RSRC_TYPE_SHFT 0x0 + +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_RSRV_CFG_ADDR (IPA_DEBUG_REG_BASE + 0x0000000c) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_RSRV_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000000c) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_RSRV_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000000c) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_RSRV_CFG_RMSK 0x3f77 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_RSRV_CFG_ATTR 0x3 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_RSRV_CFG_IN \ + in_dword_masked(HWIO_IPA_RSRC_MNGR_SW_ACCESS_RSRV_CFG_ADDR, HWIO_IPA_RSRC_MNGR_SW_ACCESS_RSRV_CFG_RMSK) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_RSRV_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_RSRC_MNGR_SW_ACCESS_RSRV_CFG_ADDR, m) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_RSRV_CFG_OUT(v) \ + out_dword(HWIO_IPA_RSRC_MNGR_SW_ACCESS_RSRV_CFG_ADDR,v) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_RSRV_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_RSRC_MNGR_SW_ACCESS_RSRV_CFG_ADDR,m,v,HWIO_IPA_RSRC_MNGR_SW_ACCESS_RSRV_CFG_IN) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_RSRV_CFG_RSRV_RSRC_AMOUNT_BMSK 0x3f00 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_RSRV_CFG_RSRV_RSRC_AMOUNT_SHFT 0x8 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_RSRV_CFG_RSRV_RSRC_GRP_BMSK 0x70 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_RSRV_CFG_RSRV_RSRC_GRP_SHFT 0x4 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_RSRV_CFG_RSRV_RSRC_TYPE_BMSK 0x7 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_RSRV_CFG_RSRV_RSRC_TYPE_SHFT 0x0 + +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x00000010) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000010) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000010) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_CMD_RMSK 0xf +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_CMD_ATTR 0x2 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_CMD_OUT(v) \ + out_dword(HWIO_IPA_RSRC_MNGR_SW_ACCESS_CMD_ADDR,v) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_CMD_RSRV_VALID_BMSK 0x8 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_CMD_RSRV_VALID_SHFT 0x3 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_CMD_REL_VALID_BMSK 0x4 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_CMD_REL_VALID_SHFT 0x2 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_CMD_SRCH_VALID_BMSK 0x2 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_CMD_SRCH_VALID_SHFT 0x1 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_CMD_ALLOC_VALID_BMSK 0x1 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_CMD_ALLOC_VALID_SHFT 0x0 + +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x00000014) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000014) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000014) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_STATUS_RMSK 0x3f3ff +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_STATUS_ATTR 0x1 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_STATUS_IN \ + in_dword_masked(HWIO_IPA_RSRC_MNGR_SW_ACCESS_STATUS_ADDR, HWIO_IPA_RSRC_MNGR_SW_ACCESS_STATUS_RMSK) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_STATUS_INM(m) \ + in_dword_masked(HWIO_IPA_RSRC_MNGR_SW_ACCESS_STATUS_ADDR, m) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_STATUS_SRCH_RSRC_ID_NEXT_BMSK 0x3f000 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_STATUS_SRCH_RSRC_ID_NEXT_SHFT 0xc +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_STATUS_ALLOC_RSRC_ID_NEXT_BMSK 0x3f0 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_STATUS_ALLOC_RSRC_ID_NEXT_SHFT 0x4 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_STATUS_RSRV_READY_BMSK 0x8 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_STATUS_RSRV_READY_SHFT 0x3 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_STATUS_REL_READY_BMSK 0x4 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_STATUS_REL_READY_SHFT 0x2 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_STATUS_SRCH_READY_BMSK 0x2 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_STATUS_SRCH_READY_SHFT 0x1 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_STATUS_ALLOC_READY_BMSK 0x1 +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_STATUS_ALLOC_READY_SHFT 0x0 + +#define HWIO_IPA_RSRC_MNGR_DB_CFG_ADDR (IPA_DEBUG_REG_BASE + 0x00000018) +#define HWIO_IPA_RSRC_MNGR_DB_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000018) +#define HWIO_IPA_RSRC_MNGR_DB_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000018) +#define HWIO_IPA_RSRC_MNGR_DB_CFG_RMSK 0x3f77 +#define HWIO_IPA_RSRC_MNGR_DB_CFG_ATTR 0x3 +#define HWIO_IPA_RSRC_MNGR_DB_CFG_IN \ + in_dword_masked(HWIO_IPA_RSRC_MNGR_DB_CFG_ADDR, HWIO_IPA_RSRC_MNGR_DB_CFG_RMSK, HWIO_IPA_RSRC_MNGR_DB_CFG_ATTR) +#define HWIO_IPA_RSRC_MNGR_DB_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_RSRC_MNGR_DB_CFG_ADDR, m, HWIO_IPA_RSRC_MNGR_DB_CFG_ATTR) +#define HWIO_IPA_RSRC_MNGR_DB_CFG_OUT(v) \ + out_dword(HWIO_IPA_RSRC_MNGR_DB_CFG_ADDR,v, HWIO_IPA_RSRC_MNGR_DB_CFG_ATTR) +#define HWIO_IPA_RSRC_MNGR_DB_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_RSRC_MNGR_DB_CFG_ADDR,m,v,HWIO_IPA_RSRC_MNGR_DB_CFG_IN) +#define HWIO_IPA_RSRC_MNGR_DB_CFG_RSRC_ID_SEL_BMSK 0x3f00 +#define HWIO_IPA_RSRC_MNGR_DB_CFG_RSRC_ID_SEL_SHFT 0x8 +#define HWIO_IPA_RSRC_MNGR_DB_CFG_RSRC_TYPE_SEL_BMSK 0x70 +#define HWIO_IPA_RSRC_MNGR_DB_CFG_RSRC_TYPE_SEL_SHFT 0x4 +#define HWIO_IPA_RSRC_MNGR_DB_CFG_RSRC_GRP_SEL_BMSK 0x7 +#define HWIO_IPA_RSRC_MNGR_DB_CFG_RSRC_GRP_SEL_SHFT 0x0 + +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_ADDR (IPA_DEBUG_REG_BASE + 0x0000001c) +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000001c) +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000001c) +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_RMSK 0x3f3 +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_ATTR 0x1 +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_IN \ + in_dword_masked(HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_ADDR, HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_RMSK, HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_ATTR) +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_INM(m) \ + in_dword_masked(HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_ADDR, m, HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_ATTR) +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_RSRC_NEXT_INDEX_BMSK 0x3f0 +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_RSRC_NEXT_INDEX_SHFT 0x4 +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_RSRC_NEXT_VALID_BMSK 0x2 +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_RSRC_NEXT_VALID_SHFT 0x1 +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_RSRC_OCCUPIED_BMSK 0x1 +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_RSRC_OCCUPIED_SHFT 0x0 + +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_ADDR (IPA_DEBUG_REG_BASE + 0x00000020) +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000020) +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000020) +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_RMSK 0x7f7f3f3 +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_ATTR 0x1 +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_IN \ + in_dword_masked(HWIO_IPA_RSRC_MNGR_DB_LIST_READ_ADDR, HWIO_IPA_RSRC_MNGR_DB_LIST_READ_RMSK, HWIO_IPA_RSRC_MNGR_DB_LIST_READ_ATTR) +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_INM(m) \ + in_dword_masked(HWIO_IPA_RSRC_MNGR_DB_LIST_READ_ADDR, m, HWIO_IPA_RSRC_MNGR_DB_LIST_READ_ATTR) +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_RSRC_LIST_ENTRY_CNT_BMSK 0x7f00000 +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_RSRC_LIST_ENTRY_CNT_SHFT 0x14 +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_RSRC_LIST_HEAD_CNT_BMSK 0x7f000 +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_RSRC_LIST_HEAD_CNT_SHFT 0xc +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_RSRC_LIST_HEAD_RSRC_BMSK 0x3f0 +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_RSRC_LIST_HEAD_RSRC_SHFT 0x4 +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_RSRC_LIST_HOLD_BMSK 0x2 +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_RSRC_LIST_HOLD_SHFT 0x1 +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_RSRC_LIST_VALID_BMSK 0x1 +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_RSRC_LIST_VALID_SHFT 0x0 + +#define HWIO_IPA_RSRC_MNGR_CONTEXTS_ADDR (IPA_DEBUG_REG_BASE + 0x00000024) +#define HWIO_IPA_RSRC_MNGR_CONTEXTS_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000024) +#define HWIO_IPA_RSRC_MNGR_CONTEXTS_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000024) +#define HWIO_IPA_RSRC_MNGR_CONTEXTS_RMSK 0xffff +#define HWIO_IPA_RSRC_MNGR_CONTEXTS_ATTR 0x1 +#define HWIO_IPA_RSRC_MNGR_CONTEXTS_IN \ + in_dword_masked(HWIO_IPA_RSRC_MNGR_CONTEXTS_ADDR, HWIO_IPA_RSRC_MNGR_CONTEXTS_RMSK) +#define HWIO_IPA_RSRC_MNGR_CONTEXTS_INM(m) \ + in_dword_masked(HWIO_IPA_RSRC_MNGR_CONTEXTS_ADDR, m) +#define HWIO_IPA_RSRC_MNGR_CONTEXTS_RSRC_OCCUPIED_CONTEXTS_BITMAP_BMSK 0xffff +#define HWIO_IPA_RSRC_MNGR_CONTEXTS_RSRC_OCCUPIED_CONTEXTS_BITMAP_SHFT 0x0 + +#define HWIO_IPA_BRESP_DB_CFG_ADDR (IPA_DEBUG_REG_BASE + 0x00000028) +#define HWIO_IPA_BRESP_DB_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000028) +#define HWIO_IPA_BRESP_DB_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000028) +#define HWIO_IPA_BRESP_DB_CFG_RMSK 0xf +#define HWIO_IPA_BRESP_DB_CFG_ATTR 0x3 +#define HWIO_IPA_BRESP_DB_CFG_IN \ + in_dword_masked(HWIO_IPA_BRESP_DB_CFG_ADDR, HWIO_IPA_BRESP_DB_CFG_RMSK) +#define HWIO_IPA_BRESP_DB_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_BRESP_DB_CFG_ADDR, m) +#define HWIO_IPA_BRESP_DB_CFG_OUT(v) \ + out_dword(HWIO_IPA_BRESP_DB_CFG_ADDR,v) +#define HWIO_IPA_BRESP_DB_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_BRESP_DB_CFG_ADDR,m,v,HWIO_IPA_BRESP_DB_CFG_IN) +#define HWIO_IPA_BRESP_DB_CFG_SEL_ENTRY_BMSK 0xf +#define HWIO_IPA_BRESP_DB_CFG_SEL_ENTRY_SHFT 0x0 + +#define HWIO_IPA_BRESP_DB_DATA_ADDR (IPA_DEBUG_REG_BASE + 0x0000002c) +#define HWIO_IPA_BRESP_DB_DATA_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000002c) +#define HWIO_IPA_BRESP_DB_DATA_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000002c) +#define HWIO_IPA_BRESP_DB_DATA_RMSK 0xffffffff +#define HWIO_IPA_BRESP_DB_DATA_ATTR 0x1 +#define HWIO_IPA_BRESP_DB_DATA_IN \ + in_dword_masked(HWIO_IPA_BRESP_DB_DATA_ADDR, HWIO_IPA_BRESP_DB_DATA_RMSK) +#define HWIO_IPA_BRESP_DB_DATA_INM(m) \ + in_dword_masked(HWIO_IPA_BRESP_DB_DATA_ADDR, m) +#define HWIO_IPA_BRESP_DB_DATA_DATA_BMSK 0xffffffff +#define HWIO_IPA_BRESP_DB_DATA_DATA_SHFT 0x0 + +#define HWIO_IPA_SNOC_MONITORING_CFG_ADDR (IPA_DEBUG_REG_BASE + 0x00000030) +#define HWIO_IPA_SNOC_MONITORING_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000030) +#define HWIO_IPA_SNOC_MONITORING_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000030) +#define HWIO_IPA_SNOC_MONITORING_CFG_RMSK 0x1 +#define HWIO_IPA_SNOC_MONITORING_CFG_ATTR 0x3 +#define HWIO_IPA_SNOC_MONITORING_CFG_IN \ + in_dword_masked(HWIO_IPA_SNOC_MONITORING_CFG_ADDR, HWIO_IPA_SNOC_MONITORING_CFG_RMSK) +#define HWIO_IPA_SNOC_MONITORING_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_SNOC_MONITORING_CFG_ADDR, m) +#define HWIO_IPA_SNOC_MONITORING_CFG_OUT(v) \ + out_dword(HWIO_IPA_SNOC_MONITORING_CFG_ADDR,v) +#define HWIO_IPA_SNOC_MONITORING_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_SNOC_MONITORING_CFG_ADDR,m,v,HWIO_IPA_SNOC_MONITORING_CFG_IN) +#define HWIO_IPA_SNOC_MONITORING_CFG_ENABLE_BMSK 0x1 +#define HWIO_IPA_SNOC_MONITORING_CFG_ENABLE_SHFT 0x0 + +#define HWIO_IPA_PCIE_SNOC_MONITOR_CNT_ADDR (IPA_DEBUG_REG_BASE + 0x00000034) +#define HWIO_IPA_PCIE_SNOC_MONITOR_CNT_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000034) +#define HWIO_IPA_PCIE_SNOC_MONITOR_CNT_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000034) +#define HWIO_IPA_PCIE_SNOC_MONITOR_CNT_RMSK 0x1f7df7df +#define HWIO_IPA_PCIE_SNOC_MONITOR_CNT_ATTR 0x1 +#define HWIO_IPA_PCIE_SNOC_MONITOR_CNT_IN \ + in_dword_masked(HWIO_IPA_PCIE_SNOC_MONITOR_CNT_ADDR, HWIO_IPA_PCIE_SNOC_MONITOR_CNT_RMSK) +#define HWIO_IPA_PCIE_SNOC_MONITOR_CNT_INM(m) \ + in_dword_masked(HWIO_IPA_PCIE_SNOC_MONITOR_CNT_ADDR, m) +#define HWIO_IPA_PCIE_SNOC_MONITOR_CNT_B_VALUE_BMSK 0x1f000000 +#define HWIO_IPA_PCIE_SNOC_MONITOR_CNT_B_VALUE_SHFT 0x18 +#define HWIO_IPA_PCIE_SNOC_MONITOR_CNT_W_VALUE_BMSK 0x7c0000 +#define HWIO_IPA_PCIE_SNOC_MONITOR_CNT_W_VALUE_SHFT 0x12 +#define HWIO_IPA_PCIE_SNOC_MONITOR_CNT_R_VALUE_BMSK 0x1f000 +#define HWIO_IPA_PCIE_SNOC_MONITOR_CNT_R_VALUE_SHFT 0xc +#define HWIO_IPA_PCIE_SNOC_MONITOR_CNT_AW_VALUE_BMSK 0x7c0 +#define HWIO_IPA_PCIE_SNOC_MONITOR_CNT_AW_VALUE_SHFT 0x6 +#define HWIO_IPA_PCIE_SNOC_MONITOR_CNT_AR_VALUE_BMSK 0x1f +#define HWIO_IPA_PCIE_SNOC_MONITOR_CNT_AR_VALUE_SHFT 0x0 + +#define HWIO_IPA_DDR_SNOC_MONITOR_CNT_ADDR (IPA_DEBUG_REG_BASE + 0x00000038) +#define HWIO_IPA_DDR_SNOC_MONITOR_CNT_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000038) +#define HWIO_IPA_DDR_SNOC_MONITOR_CNT_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000038) +#define HWIO_IPA_DDR_SNOC_MONITOR_CNT_RMSK 0x1f7df7df +#define HWIO_IPA_DDR_SNOC_MONITOR_CNT_ATTR 0x1 +#define HWIO_IPA_DDR_SNOC_MONITOR_CNT_IN \ + in_dword_masked(HWIO_IPA_DDR_SNOC_MONITOR_CNT_ADDR, HWIO_IPA_DDR_SNOC_MONITOR_CNT_RMSK) +#define HWIO_IPA_DDR_SNOC_MONITOR_CNT_INM(m) \ + in_dword_masked(HWIO_IPA_DDR_SNOC_MONITOR_CNT_ADDR, m) +#define HWIO_IPA_DDR_SNOC_MONITOR_CNT_B_VALUE_BMSK 0x1f000000 +#define HWIO_IPA_DDR_SNOC_MONITOR_CNT_B_VALUE_SHFT 0x18 +#define HWIO_IPA_DDR_SNOC_MONITOR_CNT_W_VALUE_BMSK 0x7c0000 +#define HWIO_IPA_DDR_SNOC_MONITOR_CNT_W_VALUE_SHFT 0x12 +#define HWIO_IPA_DDR_SNOC_MONITOR_CNT_R_VALUE_BMSK 0x1f000 +#define HWIO_IPA_DDR_SNOC_MONITOR_CNT_R_VALUE_SHFT 0xc +#define HWIO_IPA_DDR_SNOC_MONITOR_CNT_AW_VALUE_BMSK 0x7c0 +#define HWIO_IPA_DDR_SNOC_MONITOR_CNT_AW_VALUE_SHFT 0x6 +#define HWIO_IPA_DDR_SNOC_MONITOR_CNT_AR_VALUE_BMSK 0x1f +#define HWIO_IPA_DDR_SNOC_MONITOR_CNT_AR_VALUE_SHFT 0x0 + +#define HWIO_IPA_GSI_SNOC_MONITOR_CNT_ADDR (IPA_DEBUG_REG_BASE + 0x0000003c) +#define HWIO_IPA_GSI_SNOC_MONITOR_CNT_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000003c) +#define HWIO_IPA_GSI_SNOC_MONITOR_CNT_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000003c) +#define HWIO_IPA_GSI_SNOC_MONITOR_CNT_RMSK 0x1f7df7df +#define HWIO_IPA_GSI_SNOC_MONITOR_CNT_ATTR 0x1 +#define HWIO_IPA_GSI_SNOC_MONITOR_CNT_IN \ + in_dword_masked(HWIO_IPA_GSI_SNOC_MONITOR_CNT_ADDR, HWIO_IPA_GSI_SNOC_MONITOR_CNT_RMSK) +#define HWIO_IPA_GSI_SNOC_MONITOR_CNT_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_SNOC_MONITOR_CNT_ADDR, m) +#define HWIO_IPA_GSI_SNOC_MONITOR_CNT_B_VALUE_BMSK 0x1f000000 +#define HWIO_IPA_GSI_SNOC_MONITOR_CNT_B_VALUE_SHFT 0x18 +#define HWIO_IPA_GSI_SNOC_MONITOR_CNT_W_VALUE_BMSK 0x7c0000 +#define HWIO_IPA_GSI_SNOC_MONITOR_CNT_W_VALUE_SHFT 0x12 +#define HWIO_IPA_GSI_SNOC_MONITOR_CNT_R_VALUE_BMSK 0x1f000 +#define HWIO_IPA_GSI_SNOC_MONITOR_CNT_R_VALUE_SHFT 0xc +#define HWIO_IPA_GSI_SNOC_MONITOR_CNT_AW_VALUE_BMSK 0x7c0 +#define HWIO_IPA_GSI_SNOC_MONITOR_CNT_AW_VALUE_SHFT 0x6 +#define HWIO_IPA_GSI_SNOC_MONITOR_CNT_AR_VALUE_BMSK 0x1f +#define HWIO_IPA_GSI_SNOC_MONITOR_CNT_AR_VALUE_SHFT 0x0 + +#define HWIO_IPA_DEBUG_DATA_ADDR (IPA_DEBUG_REG_BASE + 0x00000040) +#define HWIO_IPA_DEBUG_DATA_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000040) +#define HWIO_IPA_DEBUG_DATA_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000040) +#define HWIO_IPA_DEBUG_DATA_RMSK 0xffffffff +#define HWIO_IPA_DEBUG_DATA_ATTR 0x1 +#define HWIO_IPA_DEBUG_DATA_IN \ + in_dword_masked(HWIO_IPA_DEBUG_DATA_ADDR, HWIO_IPA_DEBUG_DATA_RMSK, HWIO_IPA_DEBUG_DATA_ATTR) +#define HWIO_IPA_DEBUG_DATA_INM(m) \ + in_dword_masked(HWIO_IPA_DEBUG_DATA_ADDR, m, HWIO_IPA_DEBUG_DATA_ATTR) +#define HWIO_IPA_DEBUG_DATA_DEBUG_DATA_BMSK 0xffffffff +#define HWIO_IPA_DEBUG_DATA_DEBUG_DATA_SHFT 0x0 + +#define HWIO_IPA_TESTBUS_SEL_ADDR (IPA_DEBUG_REG_BASE + 0x0000004c) +#define HWIO_IPA_TESTBUS_SEL_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000004c) +#define HWIO_IPA_TESTBUS_SEL_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000004c) +#define HWIO_IPA_TESTBUS_SEL_RMSK 0xffff1 +#define HWIO_IPA_TESTBUS_SEL_ATTR 0x3 +#define HWIO_IPA_TESTBUS_SEL_IN \ + in_dword_masked(HWIO_IPA_TESTBUS_SEL_ADDR, HWIO_IPA_TESTBUS_SEL_RMSK, HWIO_IPA_TESTBUS_SEL_ATTR) +#define HWIO_IPA_TESTBUS_SEL_INM(m) \ + in_dword_masked(HWIO_IPA_TESTBUS_SEL_ADDR, m, HWIO_IPA_TESTBUS_SEL_ATTR) +#define HWIO_IPA_TESTBUS_SEL_OUT(v) \ + out_dword(HWIO_IPA_TESTBUS_SEL_ADDR,v, HWIO_IPA_TESTBUS_SEL_ATTR) +#define HWIO_IPA_TESTBUS_SEL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_TESTBUS_SEL_ADDR,m,v,HWIO_IPA_TESTBUS_SEL_IN) +#define HWIO_IPA_TESTBUS_SEL_INTERNAL_BLOCK_SELECT_BMSK 0xff000 +#define HWIO_IPA_TESTBUS_SEL_INTERNAL_BLOCK_SELECT_SHFT 0xc +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_BMSK 0xff0 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_SHFT 0x4 +#define HWIO_IPA_TESTBUS_SEL_TESTBUS_EN_BMSK 0x1 +#define HWIO_IPA_TESTBUS_SEL_TESTBUS_EN_SHFT 0x0 + +#define HWIO_IPA_HW_EVENTS_CFG_ADDR (IPA_DEBUG_REG_BASE + 0x0000005c) +#define HWIO_IPA_HW_EVENTS_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000005c) +#define HWIO_IPA_HW_EVENTS_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000005c) +#define HWIO_IPA_HW_EVENTS_CFG_RMSK 0xfff +#define HWIO_IPA_HW_EVENTS_CFG_ATTR 0x3 +#define HWIO_IPA_HW_EVENTS_CFG_IN \ + in_dword_masked(HWIO_IPA_HW_EVENTS_CFG_ADDR, HWIO_IPA_HW_EVENTS_CFG_RMSK) +#define HWIO_IPA_HW_EVENTS_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_HW_EVENTS_CFG_ADDR, m) +#define HWIO_IPA_HW_EVENTS_CFG_OUT(v) \ + out_dword(HWIO_IPA_HW_EVENTS_CFG_ADDR,v) +#define HWIO_IPA_HW_EVENTS_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_HW_EVENTS_CFG_ADDR,m,v,HWIO_IPA_HW_EVENTS_CFG_IN) +#define HWIO_IPA_HW_EVENTS_CFG_RX_EVENTS_PIPE_SELECT_BMSK 0xff0 +#define HWIO_IPA_HW_EVENTS_CFG_RX_EVENTS_PIPE_SELECT_SHFT 0x4 +#define HWIO_IPA_HW_EVENTS_CFG_HW_EVENTS_SELECT_BMSK 0xf +#define HWIO_IPA_HW_EVENTS_CFG_HW_EVENTS_SELECT_SHFT 0x0 + +#define HWIO_IPA_CONS_LOG_ADDR (IPA_DEBUG_REG_BASE + 0x00000060) +#define HWIO_IPA_CONS_LOG_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000060) +#define HWIO_IPA_CONS_LOG_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000060) +#define HWIO_IPA_CONS_LOG_RMSK 0x3ffff2 +#define HWIO_IPA_CONS_LOG_ATTR 0x3 +#define HWIO_IPA_CONS_LOG_IN \ + in_dword_masked(HWIO_IPA_CONS_LOG_ADDR, HWIO_IPA_CONS_LOG_RMSK) +#define HWIO_IPA_CONS_LOG_INM(m) \ + in_dword_masked(HWIO_IPA_CONS_LOG_ADDR, m) +#define HWIO_IPA_CONS_LOG_OUT(v) \ + out_dword(HWIO_IPA_CONS_LOG_ADDR,v) +#define HWIO_IPA_CONS_LOG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_CONS_LOG_ADDR,m,v,HWIO_IPA_CONS_LOG_IN) +#define HWIO_IPA_CONS_LOG_LOG_DPL_L2_REMOVE_EN_BMSK 0x200000 +#define HWIO_IPA_CONS_LOG_LOG_DPL_L2_REMOVE_EN_SHFT 0x15 +#define HWIO_IPA_CONS_LOG_LOG_REDUCTION_EN_BMSK 0x100000 +#define HWIO_IPA_CONS_LOG_LOG_REDUCTION_EN_SHFT 0x14 +#define HWIO_IPA_CONS_LOG_LOG_LENGTH_BMSK 0xff000 +#define HWIO_IPA_CONS_LOG_LOG_LENGTH_SHFT 0xc +#define HWIO_IPA_CONS_LOG_LOG_PIPE_BMSK 0xff0 +#define HWIO_IPA_CONS_LOG_LOG_PIPE_SHFT 0x4 +#define HWIO_IPA_CONS_LOG_LOG_EN_BMSK 0x2 +#define HWIO_IPA_CONS_LOG_LOG_EN_SHFT 0x1 + +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_ADDR (IPA_DEBUG_REG_BASE + 0x00000064) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000064) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000064) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_IN \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_CMD_ADDR_ADDR, HWIO_IPA_LOG_BUF_HW_CMD_ADDR_RMSK) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_CMD_ADDR_ADDR, m) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_OUT(v) \ + out_dword(HWIO_IPA_LOG_BUF_HW_CMD_ADDR_ADDR,v) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_LOG_BUF_HW_CMD_ADDR_ADDR,m,v,HWIO_IPA_LOG_BUF_HW_CMD_ADDR_IN) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_START_ADDR_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_START_ADDR_SHFT 0x0 + +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_ADDR (IPA_DEBUG_REG_BASE + 0x00000068) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000068) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000068) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_IN \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_ADDR, HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_RMSK) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_INM(m) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_ADDR, m) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_OUT(v) \ + out_dword(HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_ADDR,v) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_ADDR,m,v,HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_IN) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_START_ADDR_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_START_ADDR_SHFT 0x0 + +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_ADDR (IPA_DEBUG_REG_BASE + 0x0000006c) +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000006c) +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000006c) +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_ATTR 0x1 +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_IN \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_ADDR, HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_RMSK) +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_INM(m) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_ADDR, m) +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_WRITR_ADDR_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_WRITR_ADDR_SHFT 0x0 + +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_MSB_ADDR (IPA_DEBUG_REG_BASE + 0x00000070) +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_MSB_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000070) +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_MSB_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000070) +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_MSB_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_MSB_ATTR 0x1 +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_MSB_IN \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_MSB_ADDR, HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_MSB_RMSK) +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_MSB_INM(m) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_MSB_ADDR, m) +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_MSB_WRITR_ADDR_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_MSB_WRITR_ADDR_SHFT 0x0 + +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_ADDR (IPA_DEBUG_REG_BASE + 0x00000074) +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000074) +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000074) +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_RMSK 0xfffff +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_IN \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_CMD_CFG_ADDR, HWIO_IPA_LOG_BUF_HW_CMD_CFG_RMSK) +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_CMD_CFG_ADDR, m) +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_OUT(v) \ + out_dword(HWIO_IPA_LOG_BUF_HW_CMD_CFG_ADDR,v) +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_LOG_BUF_HW_CMD_CFG_ADDR,m,v,HWIO_IPA_LOG_BUF_HW_CMD_CFG_IN) +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_TPDM_TS_EN_BMSK 0x80000 +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_TPDM_TS_EN_SHFT 0x13 +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_TPDM_ENABLE_BMSK 0x40000 +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_TPDM_ENABLE_SHFT 0x12 +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_SKIP_DDR_DMA_BMSK 0x20000 +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_SKIP_DDR_DMA_SHFT 0x11 +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_ENABLE_BMSK 0x10000 +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_ENABLE_SHFT 0x10 +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_SIZE_BMSK 0xffff +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_SIZE_SHFT 0x0 + +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_ADDR (IPA_DEBUG_REG_BASE + 0x00000078) +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000078) +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000078) +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_RMSK 0xffff3fff +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_ATTR 0x1 +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_IN \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_ADDR, HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_RMSK) +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_INM(m) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_ADDR, m) +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_SKIP_DDR_WRAP_HAPPENED_BMSK 0x80000000 +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_SKIP_DDR_WRAP_HAPPENED_SHFT 0x1f +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_FULL_BMSK 0x40000000 +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_FULL_SHFT 0x1e +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_WRITE_PTR_BMSK 0x3fff0000 +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_WRITE_PTR_SHFT 0x10 +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_READ_PTR_BMSK 0x3fff +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_READ_PTR_SHFT 0x0 + +#define HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_ADDR (IPA_DEBUG_REG_BASE + 0x00000080) +#define HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000080) +#define HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000080) +#define HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_RMSK 0x3ff +#define HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_IN \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_ADDR, HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_RMSK) +#define HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_INM(m) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_ADDR, m) +#define HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_OUT(v) \ + out_dword(HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_ADDR,v) +#define HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_ADDR,m,v,HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_IN) +#define HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_UC_RESP_EN_BMSK 0x200 +#define HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_UC_RESP_EN_SHFT 0x9 +#define HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_GSI_RESP_EN_BMSK 0x100 +#define HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_GSI_RESP_EN_SHFT 0x8 +#define HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_QMB_RESP_EN_BMSK 0x80 +#define HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_QMB_RESP_EN_SHFT 0x7 +#define HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_UC_WR_EN_BMSK 0x40 +#define HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_UC_WR_EN_SHFT 0x6 +#define HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_UC_RD_EN_BMSK 0x20 +#define HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_UC_RD_EN_SHFT 0x5 +#define HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_GSI_WR_EN_BMSK 0x10 +#define HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_GSI_WR_EN_SHFT 0x4 +#define HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_GSI_RD_EN_BMSK 0x8 +#define HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_GSI_RD_EN_SHFT 0x3 +#define HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_QMB_WR_EN_BMSK 0x4 +#define HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_QMB_WR_EN_SHFT 0x2 +#define HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_QMB_RD_EN_BMSK 0x2 +#define HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_QMB_RD_EN_SHFT 0x1 +#define HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_NOC_PORT_SEL_BMSK 0x1 +#define HWIO_IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL_NOC_PORT_SEL_SHFT 0x0 + +#define HWIO_IPA_BRESP_DB_DATA_1_ADDR (IPA_DEBUG_REG_BASE + 0x00000084) +#define HWIO_IPA_BRESP_DB_DATA_1_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000084) +#define HWIO_IPA_BRESP_DB_DATA_1_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000084) +#define HWIO_IPA_BRESP_DB_DATA_1_RMSK 0xffffffff +#define HWIO_IPA_BRESP_DB_DATA_1_ATTR 0x1 +#define HWIO_IPA_BRESP_DB_DATA_1_IN \ + in_dword_masked(HWIO_IPA_BRESP_DB_DATA_1_ADDR, HWIO_IPA_BRESP_DB_DATA_1_RMSK) +#define HWIO_IPA_BRESP_DB_DATA_1_INM(m) \ + in_dword_masked(HWIO_IPA_BRESP_DB_DATA_1_ADDR, m) +#define HWIO_IPA_BRESP_DB_DATA_1_DATA_BMSK 0xffffffff +#define HWIO_IPA_BRESP_DB_DATA_1_DATA_SHFT 0x0 + +#define HWIO_IPA_BUS_MASTER_LEGACY_BURSTS_ADDR (IPA_DEBUG_REG_BASE + 0x00000090) +#define HWIO_IPA_BUS_MASTER_LEGACY_BURSTS_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000090) +#define HWIO_IPA_BUS_MASTER_LEGACY_BURSTS_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000090) +#define HWIO_IPA_BUS_MASTER_LEGACY_BURSTS_RMSK 0x7f +#define HWIO_IPA_BUS_MASTER_LEGACY_BURSTS_ATTR 0x3 +#define HWIO_IPA_BUS_MASTER_LEGACY_BURSTS_IN \ + in_dword_masked(HWIO_IPA_BUS_MASTER_LEGACY_BURSTS_ADDR, HWIO_IPA_BUS_MASTER_LEGACY_BURSTS_RMSK) +#define HWIO_IPA_BUS_MASTER_LEGACY_BURSTS_INM(m) \ + in_dword_masked(HWIO_IPA_BUS_MASTER_LEGACY_BURSTS_ADDR, m) +#define HWIO_IPA_BUS_MASTER_LEGACY_BURSTS_OUT(v) \ + out_dword(HWIO_IPA_BUS_MASTER_LEGACY_BURSTS_ADDR,v) +#define HWIO_IPA_BUS_MASTER_LEGACY_BURSTS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_BUS_MASTER_LEGACY_BURSTS_ADDR,m,v,HWIO_IPA_BUS_MASTER_LEGACY_BURSTS_IN) +#define HWIO_IPA_BUS_MASTER_LEGACY_BURSTS_CROSS_128B_UC_QMB_BMSK 0x40 +#define HWIO_IPA_BUS_MASTER_LEGACY_BURSTS_CROSS_128B_UC_QMB_SHFT 0x6 +#define HWIO_IPA_BUS_MASTER_LEGACY_BURSTS_CROSS_128B_RQOS_BMSK 0x20 +#define HWIO_IPA_BUS_MASTER_LEGACY_BURSTS_CROSS_128B_RQOS_SHFT 0x5 +#define HWIO_IPA_BUS_MASTER_LEGACY_BURSTS_CROSS_128B_HDRI_BMSK 0x10 +#define HWIO_IPA_BUS_MASTER_LEGACY_BURSTS_CROSS_128B_HDRI_SHFT 0x4 +#define HWIO_IPA_BUS_MASTER_LEGACY_BURSTS_CROSS_128B_DRBIP_DDMAR_BMSK 0x8 +#define HWIO_IPA_BUS_MASTER_LEGACY_BURSTS_CROSS_128B_DRBIP_DDMAR_SHFT 0x3 +#define HWIO_IPA_BUS_MASTER_LEGACY_BURSTS_CROSS_128B_DFETCHER_DDMAR_BMSK 0x4 +#define HWIO_IPA_BUS_MASTER_LEGACY_BURSTS_CROSS_128B_DFETCHER_DDMAR_SHFT 0x2 +#define HWIO_IPA_BUS_MASTER_LEGACY_BURSTS_CROSS_128B_FETCHER_DMAR_BMSK 0x2 +#define HWIO_IPA_BUS_MASTER_LEGACY_BURSTS_CROSS_128B_FETCHER_DMAR_SHFT 0x1 +#define HWIO_IPA_BUS_MASTER_LEGACY_BURSTS_CROSS_128B_FETCHER_IMM_CMD_BMSK 0x1 +#define HWIO_IPA_BUS_MASTER_LEGACY_BURSTS_CROSS_128B_FETCHER_IMM_CMD_SHFT 0x0 + +#define HWIO_IPA_CONS_LOG_THRESHOLD_CFG_ADDR (IPA_DEBUG_REG_BASE + 0x00000120) +#define HWIO_IPA_CONS_LOG_THRESHOLD_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000120) +#define HWIO_IPA_CONS_LOG_THRESHOLD_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000120) +#define HWIO_IPA_CONS_LOG_THRESHOLD_CFG_RMSK 0xf10fff +#define HWIO_IPA_CONS_LOG_THRESHOLD_CFG_ATTR 0x3 +#define HWIO_IPA_CONS_LOG_THRESHOLD_CFG_IN \ + in_dword_masked(HWIO_IPA_CONS_LOG_THRESHOLD_CFG_ADDR, HWIO_IPA_CONS_LOG_THRESHOLD_CFG_RMSK) +#define HWIO_IPA_CONS_LOG_THRESHOLD_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_CONS_LOG_THRESHOLD_CFG_ADDR, m) +#define HWIO_IPA_CONS_LOG_THRESHOLD_CFG_OUT(v) \ + out_dword(HWIO_IPA_CONS_LOG_THRESHOLD_CFG_ADDR,v) +#define HWIO_IPA_CONS_LOG_THRESHOLD_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_CONS_LOG_THRESHOLD_CFG_ADDR,m,v,HWIO_IPA_CONS_LOG_THRESHOLD_CFG_IN) +#define HWIO_IPA_CONS_LOG_THRESHOLD_CFG_THRESHOLD_TIMER_GRAN_SEL_BMSK 0xf00000 +#define HWIO_IPA_CONS_LOG_THRESHOLD_CFG_THRESHOLD_TIMER_GRAN_SEL_SHFT 0x14 +#define HWIO_IPA_CONS_LOG_THRESHOLD_CFG_THRESHOLD_EN_BMSK 0x10000 +#define HWIO_IPA_CONS_LOG_THRESHOLD_CFG_THRESHOLD_EN_SHFT 0x10 +#define HWIO_IPA_CONS_LOG_THRESHOLD_CFG_THRESHOLD_BMSK 0xfff +#define HWIO_IPA_CONS_LOG_THRESHOLD_CFG_THRESHOLD_SHFT 0x0 + +#define HWIO_IPA_PROD_LOG_ADDR (IPA_DEBUG_REG_BASE + 0x00000124) +#define HWIO_IPA_PROD_LOG_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000124) +#define HWIO_IPA_PROD_LOG_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000124) +#define HWIO_IPA_PROD_LOG_RMSK 0x3ffff2 +#define HWIO_IPA_PROD_LOG_ATTR 0x3 +#define HWIO_IPA_PROD_LOG_IN \ + in_dword_masked(HWIO_IPA_PROD_LOG_ADDR, HWIO_IPA_PROD_LOG_RMSK) +#define HWIO_IPA_PROD_LOG_INM(m) \ + in_dword_masked(HWIO_IPA_PROD_LOG_ADDR, m) +#define HWIO_IPA_PROD_LOG_OUT(v) \ + out_dword(HWIO_IPA_PROD_LOG_ADDR,v) +#define HWIO_IPA_PROD_LOG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_PROD_LOG_ADDR,m,v,HWIO_IPA_PROD_LOG_IN) +#define HWIO_IPA_PROD_LOG_LOG_DPL_L2_REMOVE_EN_BMSK 0x200000 +#define HWIO_IPA_PROD_LOG_LOG_DPL_L2_REMOVE_EN_SHFT 0x15 +#define HWIO_IPA_PROD_LOG_LOG_REDUCTION_EN_BMSK 0x100000 +#define HWIO_IPA_PROD_LOG_LOG_REDUCTION_EN_SHFT 0x14 +#define HWIO_IPA_PROD_LOG_LOG_LENGTH_BMSK 0xff000 +#define HWIO_IPA_PROD_LOG_LOG_LENGTH_SHFT 0xc +#define HWIO_IPA_PROD_LOG_LOG_PIPE_BMSK 0xff0 +#define HWIO_IPA_PROD_LOG_LOG_PIPE_SHFT 0x4 +#define HWIO_IPA_PROD_LOG_LOG_EN_BMSK 0x2 +#define HWIO_IPA_PROD_LOG_LOG_EN_SHFT 0x1 + +#define HWIO_IPA_PROD_LOG_THRESHOLD_CFG_ADDR (IPA_DEBUG_REG_BASE + 0x00000128) +#define HWIO_IPA_PROD_LOG_THRESHOLD_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000128) +#define HWIO_IPA_PROD_LOG_THRESHOLD_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000128) +#define HWIO_IPA_PROD_LOG_THRESHOLD_CFG_RMSK 0xf10fff +#define HWIO_IPA_PROD_LOG_THRESHOLD_CFG_ATTR 0x3 +#define HWIO_IPA_PROD_LOG_THRESHOLD_CFG_IN \ + in_dword_masked(HWIO_IPA_PROD_LOG_THRESHOLD_CFG_ADDR, HWIO_IPA_PROD_LOG_THRESHOLD_CFG_RMSK) +#define HWIO_IPA_PROD_LOG_THRESHOLD_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_PROD_LOG_THRESHOLD_CFG_ADDR, m) +#define HWIO_IPA_PROD_LOG_THRESHOLD_CFG_OUT(v) \ + out_dword(HWIO_IPA_PROD_LOG_THRESHOLD_CFG_ADDR,v) +#define HWIO_IPA_PROD_LOG_THRESHOLD_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_PROD_LOG_THRESHOLD_CFG_ADDR,m,v,HWIO_IPA_PROD_LOG_THRESHOLD_CFG_IN) +#define HWIO_IPA_PROD_LOG_THRESHOLD_CFG_THRESHOLD_TIMER_GRAN_SEL_BMSK 0xf00000 +#define HWIO_IPA_PROD_LOG_THRESHOLD_CFG_THRESHOLD_TIMER_GRAN_SEL_SHFT 0x14 +#define HWIO_IPA_PROD_LOG_THRESHOLD_CFG_THRESHOLD_EN_BMSK 0x10000 +#define HWIO_IPA_PROD_LOG_THRESHOLD_CFG_THRESHOLD_EN_SHFT 0x10 +#define HWIO_IPA_PROD_LOG_THRESHOLD_CFG_THRESHOLD_BMSK 0xfff +#define HWIO_IPA_PROD_LOG_THRESHOLD_CFG_THRESHOLD_SHFT 0x0 + +#define HWIO_IPA_RX_ACKQ_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x00000158) +#define HWIO_IPA_RX_ACKQ_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000158) +#define HWIO_IPA_RX_ACKQ_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000158) +#define HWIO_IPA_RX_ACKQ_CMD_RMSK 0xf +#define HWIO_IPA_RX_ACKQ_CMD_ATTR 0x2 +#define HWIO_IPA_RX_ACKQ_CMD_OUT(v) \ + out_dword(HWIO_IPA_RX_ACKQ_CMD_ADDR,v) +#define HWIO_IPA_RX_ACKQ_CMD_RELEASE_WR_CMD_BMSK 0x8 +#define HWIO_IPA_RX_ACKQ_CMD_RELEASE_WR_CMD_SHFT 0x3 +#define HWIO_IPA_RX_ACKQ_CMD_RELEASE_RD_CMD_BMSK 0x4 +#define HWIO_IPA_RX_ACKQ_CMD_RELEASE_RD_CMD_SHFT 0x2 +#define HWIO_IPA_RX_ACKQ_CMD_POP_CMD_BMSK 0x2 +#define HWIO_IPA_RX_ACKQ_CMD_POP_CMD_SHFT 0x1 +#define HWIO_IPA_RX_ACKQ_CMD_WRITE_CMD_BMSK 0x1 +#define HWIO_IPA_RX_ACKQ_CMD_WRITE_CMD_SHFT 0x0 + +#define HWIO_IPA_RX_ACKQ_CFG_ADDR (IPA_DEBUG_REG_BASE + 0x0000015c) +#define HWIO_IPA_RX_ACKQ_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000015c) +#define HWIO_IPA_RX_ACKQ_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000015c) +#define HWIO_IPA_RX_ACKQ_CFG_RMSK 0x3 +#define HWIO_IPA_RX_ACKQ_CFG_ATTR 0x3 +#define HWIO_IPA_RX_ACKQ_CFG_IN \ + in_dword_masked(HWIO_IPA_RX_ACKQ_CFG_ADDR, HWIO_IPA_RX_ACKQ_CFG_RMSK) +#define HWIO_IPA_RX_ACKQ_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_RX_ACKQ_CFG_ADDR, m) +#define HWIO_IPA_RX_ACKQ_CFG_OUT(v) \ + out_dword(HWIO_IPA_RX_ACKQ_CFG_ADDR,v) +#define HWIO_IPA_RX_ACKQ_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_RX_ACKQ_CFG_ADDR,m,v,HWIO_IPA_RX_ACKQ_CFG_IN) +#define HWIO_IPA_RX_ACKQ_CFG_BLOCK_WR_BMSK 0x2 +#define HWIO_IPA_RX_ACKQ_CFG_BLOCK_WR_SHFT 0x1 +#define HWIO_IPA_RX_ACKQ_CFG_BLOCK_RD_REQ_BMSK 0x1 +#define HWIO_IPA_RX_ACKQ_CFG_BLOCK_RD_REQ_SHFT 0x0 + +#define HWIO_IPA_RX_ACKQ_DATA_WR_0_ADDR (IPA_DEBUG_REG_BASE + 0x00000160) +#define HWIO_IPA_RX_ACKQ_DATA_WR_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000160) +#define HWIO_IPA_RX_ACKQ_DATA_WR_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000160) +#define HWIO_IPA_RX_ACKQ_DATA_WR_0_RMSK 0x1ffffff +#define HWIO_IPA_RX_ACKQ_DATA_WR_0_ATTR 0x3 +#define HWIO_IPA_RX_ACKQ_DATA_WR_0_IN \ + in_dword_masked(HWIO_IPA_RX_ACKQ_DATA_WR_0_ADDR, HWIO_IPA_RX_ACKQ_DATA_WR_0_RMSK) +#define HWIO_IPA_RX_ACKQ_DATA_WR_0_INM(m) \ + in_dword_masked(HWIO_IPA_RX_ACKQ_DATA_WR_0_ADDR, m) +#define HWIO_IPA_RX_ACKQ_DATA_WR_0_OUT(v) \ + out_dword(HWIO_IPA_RX_ACKQ_DATA_WR_0_ADDR,v) +#define HWIO_IPA_RX_ACKQ_DATA_WR_0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_RX_ACKQ_DATA_WR_0_ADDR,m,v,HWIO_IPA_RX_ACKQ_DATA_WR_0_IN) +#define HWIO_IPA_RX_ACKQ_DATA_WR_0_ACK_VALUE1_TYPE_BMSK 0x1000000 +#define HWIO_IPA_RX_ACKQ_DATA_WR_0_ACK_VALUE1_TYPE_SHFT 0x18 +#define HWIO_IPA_RX_ACKQ_DATA_WR_0_ACK_VALUE2_BMSK 0xff0000 +#define HWIO_IPA_RX_ACKQ_DATA_WR_0_ACK_VALUE2_SHFT 0x10 +#define HWIO_IPA_RX_ACKQ_DATA_WR_0_ACK_VALUE1_BMSK 0xffff +#define HWIO_IPA_RX_ACKQ_DATA_WR_0_ACK_VALUE1_SHFT 0x0 + +#define HWIO_IPA_RX_ACKQ_DATA_RD_0_ADDR (IPA_DEBUG_REG_BASE + 0x00000164) +#define HWIO_IPA_RX_ACKQ_DATA_RD_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000164) +#define HWIO_IPA_RX_ACKQ_DATA_RD_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000164) +#define HWIO_IPA_RX_ACKQ_DATA_RD_0_RMSK 0x1ffffff +#define HWIO_IPA_RX_ACKQ_DATA_RD_0_ATTR 0x1 +#define HWIO_IPA_RX_ACKQ_DATA_RD_0_IN \ + in_dword_masked(HWIO_IPA_RX_ACKQ_DATA_RD_0_ADDR, HWIO_IPA_RX_ACKQ_DATA_RD_0_RMSK) +#define HWIO_IPA_RX_ACKQ_DATA_RD_0_INM(m) \ + in_dword_masked(HWIO_IPA_RX_ACKQ_DATA_RD_0_ADDR, m) +#define HWIO_IPA_RX_ACKQ_DATA_RD_0_ACK_VALUE1_TYPE_BMSK 0x1000000 +#define HWIO_IPA_RX_ACKQ_DATA_RD_0_ACK_VALUE1_TYPE_SHFT 0x18 +#define HWIO_IPA_RX_ACKQ_DATA_RD_0_ACK_VALUE2_BMSK 0xff0000 +#define HWIO_IPA_RX_ACKQ_DATA_RD_0_ACK_VALUE2_SHFT 0x10 +#define HWIO_IPA_RX_ACKQ_DATA_RD_0_ACK_VALUE1_BMSK 0xffff +#define HWIO_IPA_RX_ACKQ_DATA_RD_0_ACK_VALUE1_SHFT 0x0 + +#define HWIO_IPA_RX_ACKQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x00000168) +#define HWIO_IPA_RX_ACKQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000168) +#define HWIO_IPA_RX_ACKQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000168) +#define HWIO_IPA_RX_ACKQ_STATUS_RMSK 0x1ff7 +#define HWIO_IPA_RX_ACKQ_STATUS_ATTR 0x1 +#define HWIO_IPA_RX_ACKQ_STATUS_IN \ + in_dword_masked(HWIO_IPA_RX_ACKQ_STATUS_ADDR, HWIO_IPA_RX_ACKQ_STATUS_RMSK) +#define HWIO_IPA_RX_ACKQ_STATUS_INM(m) \ + in_dword_masked(HWIO_IPA_RX_ACKQ_STATUS_ADDR, m) +#define HWIO_IPA_RX_ACKQ_STATUS_BLOCK_RD_ACK_BMSK 0x1000 +#define HWIO_IPA_RX_ACKQ_STATUS_BLOCK_RD_ACK_SHFT 0xc +#define HWIO_IPA_RX_ACKQ_STATUS_ACKQ_DEPTH_BMSK 0xf00 +#define HWIO_IPA_RX_ACKQ_STATUS_ACKQ_DEPTH_SHFT 0x8 +#define HWIO_IPA_RX_ACKQ_STATUS_ACKQ_COUNT_BMSK 0xf0 +#define HWIO_IPA_RX_ACKQ_STATUS_ACKQ_COUNT_SHFT 0x4 +#define HWIO_IPA_RX_ACKQ_STATUS_ACKQ_FULL_BMSK 0x4 +#define HWIO_IPA_RX_ACKQ_STATUS_ACKQ_FULL_SHFT 0x2 +#define HWIO_IPA_RX_ACKQ_STATUS_ACKQ_EMPTY_BMSK 0x2 +#define HWIO_IPA_RX_ACKQ_STATUS_ACKQ_EMPTY_SHFT 0x1 +#define HWIO_IPA_RX_ACKQ_STATUS_STATUS_BMSK 0x1 +#define HWIO_IPA_RX_ACKQ_STATUS_STATUS_SHFT 0x0 + +#define HWIO_IPA_UC_ACKQ_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x0000016c) +#define HWIO_IPA_UC_ACKQ_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000016c) +#define HWIO_IPA_UC_ACKQ_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000016c) +#define HWIO_IPA_UC_ACKQ_CMD_RMSK 0xf +#define HWIO_IPA_UC_ACKQ_CMD_ATTR 0x2 +#define HWIO_IPA_UC_ACKQ_CMD_OUT(v) \ + out_dword(HWIO_IPA_UC_ACKQ_CMD_ADDR,v) +#define HWIO_IPA_UC_ACKQ_CMD_RELEASE_WR_CMD_BMSK 0x8 +#define HWIO_IPA_UC_ACKQ_CMD_RELEASE_WR_CMD_SHFT 0x3 +#define HWIO_IPA_UC_ACKQ_CMD_RELEASE_RD_CMD_BMSK 0x4 +#define HWIO_IPA_UC_ACKQ_CMD_RELEASE_RD_CMD_SHFT 0x2 +#define HWIO_IPA_UC_ACKQ_CMD_POP_CMD_BMSK 0x2 +#define HWIO_IPA_UC_ACKQ_CMD_POP_CMD_SHFT 0x1 +#define HWIO_IPA_UC_ACKQ_CMD_WRITE_CMD_BMSK 0x1 +#define HWIO_IPA_UC_ACKQ_CMD_WRITE_CMD_SHFT 0x0 + +#define HWIO_IPA_UC_ACKQ_CFG_ADDR (IPA_DEBUG_REG_BASE + 0x00000170) +#define HWIO_IPA_UC_ACKQ_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000170) +#define HWIO_IPA_UC_ACKQ_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000170) +#define HWIO_IPA_UC_ACKQ_CFG_RMSK 0x3 +#define HWIO_IPA_UC_ACKQ_CFG_ATTR 0x3 +#define HWIO_IPA_UC_ACKQ_CFG_IN \ + in_dword_masked(HWIO_IPA_UC_ACKQ_CFG_ADDR, HWIO_IPA_UC_ACKQ_CFG_RMSK) +#define HWIO_IPA_UC_ACKQ_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_UC_ACKQ_CFG_ADDR, m) +#define HWIO_IPA_UC_ACKQ_CFG_OUT(v) \ + out_dword(HWIO_IPA_UC_ACKQ_CFG_ADDR,v) +#define HWIO_IPA_UC_ACKQ_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_ACKQ_CFG_ADDR,m,v,HWIO_IPA_UC_ACKQ_CFG_IN) +#define HWIO_IPA_UC_ACKQ_CFG_BLOCK_WR_BMSK 0x2 +#define HWIO_IPA_UC_ACKQ_CFG_BLOCK_WR_SHFT 0x1 +#define HWIO_IPA_UC_ACKQ_CFG_BLOCK_RD_BMSK 0x1 +#define HWIO_IPA_UC_ACKQ_CFG_BLOCK_RD_SHFT 0x0 + +#define HWIO_IPA_UC_ACKQ_DATA_WR_0_ADDR (IPA_DEBUG_REG_BASE + 0x00000174) +#define HWIO_IPA_UC_ACKQ_DATA_WR_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000174) +#define HWIO_IPA_UC_ACKQ_DATA_WR_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000174) +#define HWIO_IPA_UC_ACKQ_DATA_WR_0_RMSK 0x1ffffff +#define HWIO_IPA_UC_ACKQ_DATA_WR_0_ATTR 0x3 +#define HWIO_IPA_UC_ACKQ_DATA_WR_0_IN \ + in_dword_masked(HWIO_IPA_UC_ACKQ_DATA_WR_0_ADDR, HWIO_IPA_UC_ACKQ_DATA_WR_0_RMSK) +#define HWIO_IPA_UC_ACKQ_DATA_WR_0_INM(m) \ + in_dword_masked(HWIO_IPA_UC_ACKQ_DATA_WR_0_ADDR, m) +#define HWIO_IPA_UC_ACKQ_DATA_WR_0_OUT(v) \ + out_dword(HWIO_IPA_UC_ACKQ_DATA_WR_0_ADDR,v) +#define HWIO_IPA_UC_ACKQ_DATA_WR_0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_ACKQ_DATA_WR_0_ADDR,m,v,HWIO_IPA_UC_ACKQ_DATA_WR_0_IN) +#define HWIO_IPA_UC_ACKQ_DATA_WR_0_ACK_VALUE1_TYPE_BMSK 0x1000000 +#define HWIO_IPA_UC_ACKQ_DATA_WR_0_ACK_VALUE1_TYPE_SHFT 0x18 +#define HWIO_IPA_UC_ACKQ_DATA_WR_0_ACK_VALUE2_BMSK 0xff0000 +#define HWIO_IPA_UC_ACKQ_DATA_WR_0_ACK_VALUE2_SHFT 0x10 +#define HWIO_IPA_UC_ACKQ_DATA_WR_0_ACK_VALUE1_BMSK 0xffff +#define HWIO_IPA_UC_ACKQ_DATA_WR_0_ACK_VALUE1_SHFT 0x0 + +#define HWIO_IPA_UC_ACKQ_DATA_RD_0_ADDR (IPA_DEBUG_REG_BASE + 0x00000178) +#define HWIO_IPA_UC_ACKQ_DATA_RD_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000178) +#define HWIO_IPA_UC_ACKQ_DATA_RD_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000178) +#define HWIO_IPA_UC_ACKQ_DATA_RD_0_RMSK 0x1ffffff +#define HWIO_IPA_UC_ACKQ_DATA_RD_0_ATTR 0x1 +#define HWIO_IPA_UC_ACKQ_DATA_RD_0_IN \ + in_dword_masked(HWIO_IPA_UC_ACKQ_DATA_RD_0_ADDR, HWIO_IPA_UC_ACKQ_DATA_RD_0_RMSK) +#define HWIO_IPA_UC_ACKQ_DATA_RD_0_INM(m) \ + in_dword_masked(HWIO_IPA_UC_ACKQ_DATA_RD_0_ADDR, m) +#define HWIO_IPA_UC_ACKQ_DATA_RD_0_ACK_VALUE1_TYPE_BMSK 0x1000000 +#define HWIO_IPA_UC_ACKQ_DATA_RD_0_ACK_VALUE1_TYPE_SHFT 0x18 +#define HWIO_IPA_UC_ACKQ_DATA_RD_0_ACK_VALUE2_BMSK 0xff0000 +#define HWIO_IPA_UC_ACKQ_DATA_RD_0_ACK_VALUE2_SHFT 0x10 +#define HWIO_IPA_UC_ACKQ_DATA_RD_0_ACK_VALUE1_BMSK 0xffff +#define HWIO_IPA_UC_ACKQ_DATA_RD_0_ACK_VALUE1_SHFT 0x0 + +#define HWIO_IPA_UC_ACKQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x0000017c) +#define HWIO_IPA_UC_ACKQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000017c) +#define HWIO_IPA_UC_ACKQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000017c) +#define HWIO_IPA_UC_ACKQ_STATUS_RMSK 0x1f1f7 +#define HWIO_IPA_UC_ACKQ_STATUS_ATTR 0x1 +#define HWIO_IPA_UC_ACKQ_STATUS_IN \ + in_dword_masked(HWIO_IPA_UC_ACKQ_STATUS_ADDR, HWIO_IPA_UC_ACKQ_STATUS_RMSK) +#define HWIO_IPA_UC_ACKQ_STATUS_INM(m) \ + in_dword_masked(HWIO_IPA_UC_ACKQ_STATUS_ADDR, m) +#define HWIO_IPA_UC_ACKQ_STATUS_ACKQ_DEPTH_BMSK 0x1f000 +#define HWIO_IPA_UC_ACKQ_STATUS_ACKQ_DEPTH_SHFT 0xc +#define HWIO_IPA_UC_ACKQ_STATUS_ACKQ_COUNT_BMSK 0x1f0 +#define HWIO_IPA_UC_ACKQ_STATUS_ACKQ_COUNT_SHFT 0x4 +#define HWIO_IPA_UC_ACKQ_STATUS_ACKQ_FULL_BMSK 0x4 +#define HWIO_IPA_UC_ACKQ_STATUS_ACKQ_FULL_SHFT 0x2 +#define HWIO_IPA_UC_ACKQ_STATUS_ACKQ_EMPTY_BMSK 0x2 +#define HWIO_IPA_UC_ACKQ_STATUS_ACKQ_EMPTY_SHFT 0x1 +#define HWIO_IPA_UC_ACKQ_STATUS_STATUS_BMSK 0x1 +#define HWIO_IPA_UC_ACKQ_STATUS_STATUS_SHFT 0x0 + +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x00000180 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x00000180 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x00000180 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_RMSK 0x7f +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_MAXn 4 +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_ATTR 0x2 +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_OUTI(n,val) \ + out_dword(HWIO_IPA_RX_SPLT_CMDQ_CMD_n_ADDR(n),val) +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_RELEASE_RD_PKT_ENHANCED_BMSK 0x40 +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_RELEASE_RD_PKT_ENHANCED_SHFT 0x6 +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_RELEASE_WR_PKT_BMSK 0x20 +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_RELEASE_WR_PKT_SHFT 0x5 +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_RELEASE_RD_PKT_BMSK 0x10 +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_RELEASE_RD_PKT_SHFT 0x4 +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_RELEASE_WR_CMD_BMSK 0x8 +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_RELEASE_WR_CMD_SHFT 0x3 +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_RELEASE_RD_CMD_BMSK 0x4 +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_RELEASE_RD_CMD_SHFT 0x2 +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_POP_CMD_BMSK 0x2 +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_POP_CMD_SHFT 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_WRITE_CMD_BMSK 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_WRITE_CMD_SHFT 0x0 + +#define HWIO_IPA_RX_SPLT_CMDQ_CFG_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x00000184 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_CFG_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x00000184 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_CFG_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x00000184 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_CFG_n_RMSK 0x3 +#define HWIO_IPA_RX_SPLT_CMDQ_CFG_n_MAXn 4 +#define HWIO_IPA_RX_SPLT_CMDQ_CFG_n_ATTR 0x3 +#define HWIO_IPA_RX_SPLT_CMDQ_CFG_n_INI(n) \ + in_dword_masked(HWIO_IPA_RX_SPLT_CMDQ_CFG_n_ADDR(n), HWIO_IPA_RX_SPLT_CMDQ_CFG_n_RMSK) +#define HWIO_IPA_RX_SPLT_CMDQ_CFG_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_RX_SPLT_CMDQ_CFG_n_ADDR(n), mask) +#define HWIO_IPA_RX_SPLT_CMDQ_CFG_n_OUTI(n,val) \ + out_dword(HWIO_IPA_RX_SPLT_CMDQ_CFG_n_ADDR(n),val) +#define HWIO_IPA_RX_SPLT_CMDQ_CFG_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_RX_SPLT_CMDQ_CFG_n_ADDR(n),mask,val,HWIO_IPA_RX_SPLT_CMDQ_CFG_n_INI(n)) +#define HWIO_IPA_RX_SPLT_CMDQ_CFG_n_BLOCK_WR_BMSK 0x2 +#define HWIO_IPA_RX_SPLT_CMDQ_CFG_n_BLOCK_WR_SHFT 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_CFG_n_BLOCK_RD_BMSK 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_CFG_n_BLOCK_RD_SHFT 0x0 + +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x00000188 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x00000188 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x00000188 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_RMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_MAXn 4 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_ATTR 0x3 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_INI(n) \ + in_dword_masked(HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_ADDR(n), HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_RMSK) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_ADDR(n), mask) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_OUTI(n,val) \ + out_dword(HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_ADDR(n),val) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_ADDR(n),mask,val,HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_INI(n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_CMDQ_SRC_LEN_F_BMSK 0xffff0000 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_CMDQ_SRC_LEN_F_SHFT 0x10 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_CMDQ_PACKET_LEN_F_BMSK 0xffff +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_CMDQ_PACKET_LEN_F_SHFT 0x0 + +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x0000018c + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x0000018c + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x0000018c + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_RMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_MAXn 4 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_ATTR 0x3 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_INI(n) \ + in_dword_masked(HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_ADDR(n), HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_RMSK) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_ADDR(n), mask) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_OUTI(n,val) \ + out_dword(HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_ADDR(n),val) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_ADDR(n),mask,val,HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_INI(n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_CMDQ_METADATA_F_BMSK 0xff000000 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_CMDQ_METADATA_F_SHFT 0x18 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_CMDQ_OPCODE_F_BMSK 0xff0000 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_CMDQ_OPCODE_F_SHFT 0x10 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_CMDQ_FLAGS_F_BMSK 0xfc00 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_CMDQ_FLAGS_F_SHFT 0xa +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_CMDQ_ORDER_F_BMSK 0x300 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_CMDQ_ORDER_F_SHFT 0x8 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_CMDQ_SRC_PIPE_F_BMSK 0xff +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_CMDQ_SRC_PIPE_F_SHFT 0x0 + +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x00000190 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x00000190 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x00000190 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_RMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_MAXn 4 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_ATTR 0x3 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_INI(n) \ + in_dword_masked(HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_ADDR(n), HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_RMSK) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_ADDR(n), mask) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_OUTI(n,val) \ + out_dword(HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_ADDR(n),val) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_ADDR(n),mask,val,HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_INI(n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_CMDQ_ADDR_LSB_F_BMSK 0xfffffffe +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_CMDQ_ADDR_LSB_F_SHFT 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_CMDQ_STATS_DISABLE_F_BMSK 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_CMDQ_STATS_DISABLE_F_SHFT 0x0 + +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x00000194 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x00000194 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x00000194 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_RMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_MAXn 4 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_ATTR 0x3 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_INI(n) \ + in_dword_masked(HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_ADDR(n), HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_RMSK) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_ADDR(n), mask) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_OUTI(n,val) \ + out_dword(HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_ADDR(n),val) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_ADDR(n),mask,val,HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_INI(n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_CMDQ_ADDR_MSB_F_BMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_CMDQ_ADDR_MSB_F_SHFT 0x0 + +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_0_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x00000198 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_0_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x00000198 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_0_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x00000198 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_0_n_RMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_0_n_MAXn 4 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_0_n_ATTR 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_0_n_INI(n) \ + in_dword_masked(HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_0_n_ADDR(n), HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_0_n_RMSK) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_0_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_0_n_ADDR(n), mask) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_0_n_CMDQ_SRC_LEN_F_BMSK 0xffff0000 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_0_n_CMDQ_SRC_LEN_F_SHFT 0x10 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_0_n_CMDQ_PACKET_LEN_F_BMSK 0xffff +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_0_n_CMDQ_PACKET_LEN_F_SHFT 0x0 + +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x0000019c + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x0000019c + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x0000019c + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_RMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_MAXn 4 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_ATTR 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_INI(n) \ + in_dword_masked(HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_ADDR(n), HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_RMSK) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_ADDR(n), mask) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_CMDQ_METADATA_F_BMSK 0xff000000 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_CMDQ_METADATA_F_SHFT 0x18 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_CMDQ_OPCODE_F_BMSK 0xff0000 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_CMDQ_OPCODE_F_SHFT 0x10 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_CMDQ_FLAGS_F_BMSK 0xfc00 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_CMDQ_FLAGS_F_SHFT 0xa +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_CMDQ_ORDER_F_BMSK 0x300 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_CMDQ_ORDER_F_SHFT 0x8 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_CMDQ_SRC_PIPE_F_BMSK 0xff +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_CMDQ_SRC_PIPE_F_SHFT 0x0 + +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_2_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x000001a0 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_2_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x000001a0 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_2_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x000001a0 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_2_n_RMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_2_n_MAXn 4 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_2_n_ATTR 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_2_n_INI(n) \ + in_dword_masked(HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_2_n_ADDR(n), HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_2_n_RMSK) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_2_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_2_n_ADDR(n), mask) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_2_n_CMDQ_ADDR_LSB_F_BMSK 0xfffffffe +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_2_n_CMDQ_ADDR_LSB_F_SHFT 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_2_n_CMDQ_STATS_DISABLE_F_BMSK 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_2_n_CMDQ_STATS_DISABLE_F_SHFT 0x0 + +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_3_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x000001a4 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_3_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x000001a4 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_3_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x000001a4 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_3_n_RMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_3_n_MAXn 4 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_3_n_ATTR 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_3_n_INI(n) \ + in_dword_masked(HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_3_n_ADDR(n), HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_3_n_RMSK) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_3_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_3_n_ADDR(n), mask) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_3_n_CMDQ_ADDR_MSB_F_BMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_3_n_CMDQ_ADDR_MSB_F_SHFT 0x0 + +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x000001a8 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x000001a8 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x000001a8 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_RMSK 0x7f +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_MAXn 4 +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_ATTR 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_INI(n) \ + in_dword_masked(HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_ADDR(n), HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_RMSK) +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_ADDR(n), mask) +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_CMDQ_DEPTH_BMSK 0x60 +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_CMDQ_DEPTH_SHFT 0x5 +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_CMDQ_COUNT_BMSK 0x18 +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_CMDQ_COUNT_SHFT 0x3 +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_CMDQ_FULL_BMSK 0x4 +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_CMDQ_FULL_SHFT 0x2 +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_CMDQ_EMPTY_BMSK 0x2 +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_CMDQ_EMPTY_SHFT 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_STATUS_BMSK 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_STATUS_SHFT 0x0 + +#define HWIO_IPA_RX_HPS_CMDQ_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x00000280) +#define HWIO_IPA_RX_HPS_CMDQ_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000280) +#define HWIO_IPA_RX_HPS_CMDQ_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000280) +#define HWIO_IPA_RX_HPS_CMDQ_CMD_RMSK 0x3f +#define HWIO_IPA_RX_HPS_CMDQ_CMD_ATTR 0x3 +#define HWIO_IPA_RX_HPS_CMDQ_CMD_IN \ + in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_CMD_ADDR, HWIO_IPA_RX_HPS_CMDQ_CMD_RMSK) +#define HWIO_IPA_RX_HPS_CMDQ_CMD_INM(m) \ + in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_CMD_ADDR, m) +#define HWIO_IPA_RX_HPS_CMDQ_CMD_OUT(v) \ + out_dword(HWIO_IPA_RX_HPS_CMDQ_CMD_ADDR,v) +#define HWIO_IPA_RX_HPS_CMDQ_CMD_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_RX_HPS_CMDQ_CMD_ADDR,m,v,HWIO_IPA_RX_HPS_CMDQ_CMD_IN) +#define HWIO_IPA_RX_HPS_CMDQ_CMD_RD_REQ_BMSK 0x20 +#define HWIO_IPA_RX_HPS_CMDQ_CMD_RD_REQ_SHFT 0x5 +#define HWIO_IPA_RX_HPS_CMDQ_CMD_CMD_CLIENT_BMSK 0x1c +#define HWIO_IPA_RX_HPS_CMDQ_CMD_CMD_CLIENT_SHFT 0x2 +#define HWIO_IPA_RX_HPS_CMDQ_CMD_POP_CMD_BMSK 0x2 +#define HWIO_IPA_RX_HPS_CMDQ_CMD_POP_CMD_SHFT 0x1 +#define HWIO_IPA_RX_HPS_CMDQ_CMD_WRITE_CMD_BMSK 0x1 +#define HWIO_IPA_RX_HPS_CMDQ_CMD_WRITE_CMD_SHFT 0x0 + +#define HWIO_IPA_RX_HPS_CMDQ_RELEASE_WR_ADDR (IPA_DEBUG_REG_BASE + 0x00000284) +#define HWIO_IPA_RX_HPS_CMDQ_RELEASE_WR_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000284) +#define HWIO_IPA_RX_HPS_CMDQ_RELEASE_WR_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000284) +#define HWIO_IPA_RX_HPS_CMDQ_RELEASE_WR_RMSK 0x3f +#define HWIO_IPA_RX_HPS_CMDQ_RELEASE_WR_ATTR 0x2 +#define HWIO_IPA_RX_HPS_CMDQ_RELEASE_WR_OUT(v) \ + out_dword(HWIO_IPA_RX_HPS_CMDQ_RELEASE_WR_ADDR,v) +#define HWIO_IPA_RX_HPS_CMDQ_RELEASE_WR_RELEASE_WR_CMD_BMSK 0x3f +#define HWIO_IPA_RX_HPS_CMDQ_RELEASE_WR_RELEASE_WR_CMD_SHFT 0x0 + +#define HWIO_IPA_RX_HPS_CMDQ_RELEASE_RD_ADDR (IPA_DEBUG_REG_BASE + 0x00000288) +#define HWIO_IPA_RX_HPS_CMDQ_RELEASE_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000288) +#define HWIO_IPA_RX_HPS_CMDQ_RELEASE_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000288) +#define HWIO_IPA_RX_HPS_CMDQ_RELEASE_RD_RMSK 0x3f +#define HWIO_IPA_RX_HPS_CMDQ_RELEASE_RD_ATTR 0x2 +#define HWIO_IPA_RX_HPS_CMDQ_RELEASE_RD_OUT(v) \ + out_dword(HWIO_IPA_RX_HPS_CMDQ_RELEASE_RD_ADDR,v) +#define HWIO_IPA_RX_HPS_CMDQ_RELEASE_RD_RELEASE_RD_CMD_BMSK 0x3f +#define HWIO_IPA_RX_HPS_CMDQ_RELEASE_RD_RELEASE_RD_CMD_SHFT 0x0 + +#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_ADDR (IPA_DEBUG_REG_BASE + 0x0000028c) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000028c) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000028c) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_RMSK 0x3f +#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_ATTR 0x3 +#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_IN \ + in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_CFG_WR_ADDR, HWIO_IPA_RX_HPS_CMDQ_CFG_WR_RMSK) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_INM(m) \ + in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_CFG_WR_ADDR, m) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_OUT(v) \ + out_dword(HWIO_IPA_RX_HPS_CMDQ_CFG_WR_ADDR,v) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_RX_HPS_CMDQ_CFG_WR_ADDR,m,v,HWIO_IPA_RX_HPS_CMDQ_CFG_WR_IN) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_BLOCK_WR_BMSK 0x3f +#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_BLOCK_WR_SHFT 0x0 + +#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_ADDR (IPA_DEBUG_REG_BASE + 0x00000290) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000290) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000290) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_RMSK 0x3f +#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_ATTR 0x3 +#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_IN \ + in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_CFG_RD_ADDR, HWIO_IPA_RX_HPS_CMDQ_CFG_RD_RMSK) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_INM(m) \ + in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_CFG_RD_ADDR, m) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_OUT(v) \ + out_dword(HWIO_IPA_RX_HPS_CMDQ_CFG_RD_ADDR,v) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_RX_HPS_CMDQ_CFG_RD_ADDR,m,v,HWIO_IPA_RX_HPS_CMDQ_CFG_RD_IN) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_BLOCK_RD_BMSK 0x3f +#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_BLOCK_RD_SHFT 0x0 + +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_0_ADDR (IPA_DEBUG_REG_BASE + 0x00000294) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000294) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000294) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_0_RMSK 0xffffffff +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_0_ATTR 0x3 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_0_IN \ + in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_DATA_WR_0_ADDR, HWIO_IPA_RX_HPS_CMDQ_DATA_WR_0_RMSK) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_0_INM(m) \ + in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_DATA_WR_0_ADDR, m) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_0_OUT(v) \ + out_dword(HWIO_IPA_RX_HPS_CMDQ_DATA_WR_0_ADDR,v) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_RX_HPS_CMDQ_DATA_WR_0_ADDR,m,v,HWIO_IPA_RX_HPS_CMDQ_DATA_WR_0_IN) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_0_CMDQ_DEST_LEN_F_BMSK 0xffff0000 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_0_CMDQ_DEST_LEN_F_SHFT 0x10 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_0_CMDQ_PACKET_LEN_F_BMSK 0xffff +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_0_CMDQ_PACKET_LEN_F_SHFT 0x0 + +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_1_ADDR (IPA_DEBUG_REG_BASE + 0x00000298) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_1_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000298) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_1_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000298) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_1_RMSK 0xffffffff +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_1_ATTR 0x3 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_1_IN \ + in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_DATA_WR_1_ADDR, HWIO_IPA_RX_HPS_CMDQ_DATA_WR_1_RMSK) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_1_INM(m) \ + in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_DATA_WR_1_ADDR, m) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_1_OUT(v) \ + out_dword(HWIO_IPA_RX_HPS_CMDQ_DATA_WR_1_ADDR,v) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_RX_HPS_CMDQ_DATA_WR_1_ADDR,m,v,HWIO_IPA_RX_HPS_CMDQ_DATA_WR_1_IN) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_1_CMDQ_METADATA_F_BMSK 0xff000000 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_1_CMDQ_METADATA_F_SHFT 0x18 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_1_CMDQ_OPCODE_F_BMSK 0xff0000 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_1_CMDQ_OPCODE_F_SHFT 0x10 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_1_CMDQ_FLAGS_F_BMSK 0xfc00 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_1_CMDQ_FLAGS_F_SHFT 0xa +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_1_CMDQ_ORDER_F_BMSK 0x300 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_1_CMDQ_ORDER_F_SHFT 0x8 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_1_CMDQ_SRC_PIPE_F_BMSK 0xff +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_1_CMDQ_SRC_PIPE_F_SHFT 0x0 + +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_2_ADDR (IPA_DEBUG_REG_BASE + 0x0000029c) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_2_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000029c) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_2_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000029c) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_2_RMSK 0xffffffff +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_2_ATTR 0x3 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_2_IN \ + in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_DATA_WR_2_ADDR, HWIO_IPA_RX_HPS_CMDQ_DATA_WR_2_RMSK) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_2_INM(m) \ + in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_DATA_WR_2_ADDR, m) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_2_OUT(v) \ + out_dword(HWIO_IPA_RX_HPS_CMDQ_DATA_WR_2_ADDR,v) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_RX_HPS_CMDQ_DATA_WR_2_ADDR,m,v,HWIO_IPA_RX_HPS_CMDQ_DATA_WR_2_IN) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_2_CMDQ_ADDR_LSB_F_BMSK 0xfffffffe +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_2_CMDQ_ADDR_LSB_F_SHFT 0x1 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_2_CMDQ_STATS_DISABLE_F_BMSK 0x1 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_2_CMDQ_STATS_DISABLE_F_SHFT 0x0 + +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_3_ADDR (IPA_DEBUG_REG_BASE + 0x000002a0) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_3_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000002a0) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_3_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000002a0) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_3_RMSK 0xffffffff +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_3_ATTR 0x3 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_3_IN \ + in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_DATA_WR_3_ADDR, HWIO_IPA_RX_HPS_CMDQ_DATA_WR_3_RMSK) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_3_INM(m) \ + in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_DATA_WR_3_ADDR, m) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_3_OUT(v) \ + out_dword(HWIO_IPA_RX_HPS_CMDQ_DATA_WR_3_ADDR,v) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_3_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_RX_HPS_CMDQ_DATA_WR_3_ADDR,m,v,HWIO_IPA_RX_HPS_CMDQ_DATA_WR_3_IN) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_3_CMDQ_ADDR_MSB_F_BMSK 0xffffffff +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_3_CMDQ_ADDR_MSB_F_SHFT 0x0 + +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_ADDR (IPA_DEBUG_REG_BASE + 0x000002a4) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000002a4) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000002a4) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_RMSK 0xffffffff +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_ATTR 0x1 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_IN \ + in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_ADDR, HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_RMSK, HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_ATTR) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_INM(m) \ + in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_ADDR, m, HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_ATTR) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_CMDQ_DEST_LEN_F_BMSK 0xffff0000 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_CMDQ_DEST_LEN_F_SHFT 0x10 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_CMDQ_PACKET_LEN_F_BMSK 0xffff +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_CMDQ_PACKET_LEN_F_SHFT 0x0 + +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_ADDR (IPA_DEBUG_REG_BASE + 0x000002a8) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000002a8) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000002a8) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_RMSK 0xffffffff +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_ATTR 0x1 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_IN \ + in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_ADDR, HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_RMSK, HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_ATTR) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_INM(m) \ + in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_ADDR, m, HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_ATTR) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_CMDQ_METADATA_F_BMSK 0xff000000 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_CMDQ_METADATA_F_SHFT 0x18 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_CMDQ_OPCODE_F_BMSK 0xff0000 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_CMDQ_OPCODE_F_SHFT 0x10 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_CMDQ_FLAGS_F_BMSK 0xfc00 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_CMDQ_FLAGS_F_SHFT 0xa +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_CMDQ_ORDER_F_BMSK 0x300 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_CMDQ_ORDER_F_SHFT 0x8 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_CMDQ_SRC_PIPE_F_BMSK 0xff +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_CMDQ_SRC_PIPE_F_SHFT 0x0 + +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_ADDR (IPA_DEBUG_REG_BASE + 0x000002ac) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000002ac) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000002ac) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_RMSK 0xffffffff +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_ATTR 0x1 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_IN \ + in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_ADDR, HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_RMSK, HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_ATTR) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_INM(m) \ + in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_ADDR, m, HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_ATTR) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_CMDQ_ADDR_LSB_F_BMSK 0xfffffffe +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_CMDQ_ADDR_LSB_F_SHFT 0x1 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_CMDQ_STATS_DISABLE_F_BMSK 0x1 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_CMDQ_STATS_DISABLE_F_SHFT 0x0 + +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_ADDR (IPA_DEBUG_REG_BASE + 0x000002b0) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000002b0) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000002b0) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_RMSK 0xffffffff +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_ATTR 0x1 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_IN \ + in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_ADDR, HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_RMSK, HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_ATTR) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_INM(m) \ + in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_ADDR, m, HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_ATTR) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_CMDQ_ADDR_MSB_F_BMSK 0xffffffff +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_CMDQ_ADDR_MSB_F_SHFT 0x0 + +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x000002b4) +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000002b4) +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000002b4) +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_RMSK 0x1ff +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_ATTR 0x1 +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_IN \ + in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_STATUS_ADDR, HWIO_IPA_RX_HPS_CMDQ_STATUS_RMSK, HWIO_IPA_RX_HPS_CMDQ_STATUS_ATTR) +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_INM(m) \ + in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_STATUS_ADDR, m, HWIO_IPA_RX_HPS_CMDQ_STATUS_ATTR) +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_CMDQ_DEPTH_BMSK 0x1fc +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_CMDQ_DEPTH_SHFT 0x2 +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_CMDQ_FULL_BMSK 0x2 +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_CMDQ_FULL_SHFT 0x1 +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_STATUS_BMSK 0x1 +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_STATUS_SHFT 0x0 + +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_EMPTY_ADDR (IPA_DEBUG_REG_BASE + 0x000002b8) +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_EMPTY_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000002b8) +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_EMPTY_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000002b8) +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_EMPTY_RMSK 0x3f +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_EMPTY_ATTR 0x1 +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_EMPTY_IN \ + in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_STATUS_EMPTY_ADDR, HWIO_IPA_RX_HPS_CMDQ_STATUS_EMPTY_RMSK) +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_EMPTY_INM(m) \ + in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_STATUS_EMPTY_ADDR, m) +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_EMPTY_CMDQ_EMPTY_BMSK 0x3f +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_EMPTY_CMDQ_EMPTY_SHFT 0x0 + +#define HWIO_IPA_RX_HPS_SNP_ADDR (IPA_DEBUG_REG_BASE + 0x000002bc) +#define HWIO_IPA_RX_HPS_SNP_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000002bc) +#define HWIO_IPA_RX_HPS_SNP_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000002bc) +#define HWIO_IPA_RX_HPS_SNP_RMSK 0xffff +#define HWIO_IPA_RX_HPS_SNP_ATTR 0x3 +#define HWIO_IPA_RX_HPS_SNP_IN \ + in_dword_masked(HWIO_IPA_RX_HPS_SNP_ADDR, HWIO_IPA_RX_HPS_SNP_RMSK) +#define HWIO_IPA_RX_HPS_SNP_INM(m) \ + in_dword_masked(HWIO_IPA_RX_HPS_SNP_ADDR, m) +#define HWIO_IPA_RX_HPS_SNP_OUT(v) \ + out_dword(HWIO_IPA_RX_HPS_SNP_ADDR,v) +#define HWIO_IPA_RX_HPS_SNP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_RX_HPS_SNP_ADDR,m,v,HWIO_IPA_RX_HPS_SNP_IN) +#define HWIO_IPA_RX_HPS_SNP_SNP_ADDR_BMSK 0xf000 +#define HWIO_IPA_RX_HPS_SNP_SNP_ADDR_SHFT 0xc +#define HWIO_IPA_RX_HPS_SNP_SNP_HEAD_BMSK 0xf00 +#define HWIO_IPA_RX_HPS_SNP_SNP_HEAD_SHFT 0x8 +#define HWIO_IPA_RX_HPS_SNP_SNP_NEXT_BMSK 0xf0 +#define HWIO_IPA_RX_HPS_SNP_SNP_NEXT_SHFT 0x4 +#define HWIO_IPA_RX_HPS_SNP_SNP_NEXT_IS_VALID_BMSK 0x8 +#define HWIO_IPA_RX_HPS_SNP_SNP_NEXT_IS_VALID_SHFT 0x3 +#define HWIO_IPA_RX_HPS_SNP_SNP_VALID_BMSK 0x4 +#define HWIO_IPA_RX_HPS_SNP_SNP_VALID_SHFT 0x2 +#define HWIO_IPA_RX_HPS_SNP_SNP_WRITE_BMSK 0x2 +#define HWIO_IPA_RX_HPS_SNP_SNP_WRITE_SHFT 0x1 +#define HWIO_IPA_RX_HPS_SNP_SNP_LAST_BMSK 0x1 +#define HWIO_IPA_RX_HPS_SNP_SNP_LAST_SHFT 0x0 + +#define HWIO_IPA_RX_HPS_CMDQ_COUNT_ADDR (IPA_DEBUG_REG_BASE + 0x000002c0) +#define HWIO_IPA_RX_HPS_CMDQ_COUNT_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000002c0) +#define HWIO_IPA_RX_HPS_CMDQ_COUNT_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000002c0) +#define HWIO_IPA_RX_HPS_CMDQ_COUNT_RMSK 0x7f +#define HWIO_IPA_RX_HPS_CMDQ_COUNT_ATTR 0x1 +#define HWIO_IPA_RX_HPS_CMDQ_COUNT_IN \ + in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_COUNT_ADDR, HWIO_IPA_RX_HPS_CMDQ_COUNT_RMSK, HWIO_IPA_RX_HPS_CMDQ_COUNT_ATTR) +#define HWIO_IPA_RX_HPS_CMDQ_COUNT_INM(m) \ + in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_COUNT_ADDR, m, HWIO_IPA_RX_HPS_CMDQ_COUNT_ATTR) +#define HWIO_IPA_RX_HPS_CMDQ_COUNT_FIFO_COUNT_BMSK 0x7f +#define HWIO_IPA_RX_HPS_CMDQ_COUNT_FIFO_COUNT_SHFT 0x0 + +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_ADDR (IPA_DEBUG_REG_BASE + 0x000002c4) +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000002c4) +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000002c4) +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_RMSK 0xff0f0f0f +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_ATTR 0x3 +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_IN \ + in_dword_masked(HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_ADDR, HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_RMSK) +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_INM(m) \ + in_dword_masked(HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_ADDR, m) +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_OUT(v) \ + out_dword(HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_ADDR,v) +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_ADDR,m,v,HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_IN) +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_CLIENT_4_MIN_DEPTH_BMSK 0xf0000000 +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_CLIENT_4_MIN_DEPTH_SHFT 0x1c +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_CLIENT_3_MIN_DEPTH_BMSK 0xf000000 +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_CLIENT_3_MIN_DEPTH_SHFT 0x18 +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_CLIENT_2_MIN_DEPTH_BMSK 0xf0000 +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_CLIENT_2_MIN_DEPTH_SHFT 0x10 +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_CLIENT_1_MIN_DEPTH_BMSK 0xf00 +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_CLIENT_1_MIN_DEPTH_SHFT 0x8 +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_CLIENT_0_MIN_DEPTH_BMSK 0xf +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_CLIENT_0_MIN_DEPTH_SHFT 0x0 + +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_1_ADDR (IPA_DEBUG_REG_BASE + 0x000002c8) +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_1_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000002c8) +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_1_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000002c8) +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_1_RMSK 0xff0f0f0f +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_1_ATTR 0x3 +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_1_IN \ + in_dword_masked(HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_1_ADDR, HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_1_RMSK) +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_1_INM(m) \ + in_dword_masked(HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_1_ADDR, m) +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_1_OUT(v) \ + out_dword(HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_1_ADDR,v) +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_1_ADDR,m,v,HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_1_IN) +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_1_CLIENT_9_MIN_DEPTH_BMSK 0xf0000000 +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_1_CLIENT_9_MIN_DEPTH_SHFT 0x1c +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_1_CLIENT_8_MIN_DEPTH_BMSK 0xf000000 +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_1_CLIENT_8_MIN_DEPTH_SHFT 0x18 +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_1_CLIENT_7_MIN_DEPTH_BMSK 0xf0000 +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_1_CLIENT_7_MIN_DEPTH_SHFT 0x10 +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_1_CLIENT_6_MIN_DEPTH_BMSK 0xf00 +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_1_CLIENT_6_MIN_DEPTH_SHFT 0x8 +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_1_CLIENT_5_MIN_DEPTH_BMSK 0xf +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_1_CLIENT_5_MIN_DEPTH_SHFT 0x0 + +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_ADDR (IPA_DEBUG_REG_BASE + 0x000002cc) +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000002cc) +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000002cc) +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_RMSK 0xff0f0f0f +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_ATTR 0x3 +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_IN \ + in_dword_masked(HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_ADDR, HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_RMSK) +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_INM(m) \ + in_dword_masked(HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_ADDR, m) +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_OUT(v) \ + out_dword(HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_ADDR,v) +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_ADDR,m,v,HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_IN) +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_CLIENT_4_MAX_DEPTH_BMSK 0xf0000000 +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_CLIENT_4_MAX_DEPTH_SHFT 0x1c +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_CLIENT_3_MAX_DEPTH_BMSK 0xf000000 +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_CLIENT_3_MAX_DEPTH_SHFT 0x18 +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_CLIENT_2_MAX_DEPTH_BMSK 0xf0000 +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_CLIENT_2_MAX_DEPTH_SHFT 0x10 +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_CLIENT_1_MAX_DEPTH_BMSK 0xf00 +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_CLIENT_1_MAX_DEPTH_SHFT 0x8 +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_CLIENT_0_MAX_DEPTH_BMSK 0xf +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_CLIENT_0_MAX_DEPTH_SHFT 0x0 + +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_1_ADDR (IPA_DEBUG_REG_BASE + 0x000002d0) +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_1_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000002d0) +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_1_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000002d0) +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_1_RMSK 0xff0f0f0f +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_1_ATTR 0x3 +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_1_IN \ + in_dword_masked(HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_1_ADDR, HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_1_RMSK) +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_1_INM(m) \ + in_dword_masked(HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_1_ADDR, m) +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_1_OUT(v) \ + out_dword(HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_1_ADDR,v) +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_1_ADDR,m,v,HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_1_IN) +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_1_CLIENT_9_MAX_DEPTH_BMSK 0xf0000000 +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_1_CLIENT_9_MAX_DEPTH_SHFT 0x1c +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_1_CLIENT_8_MAX_DEPTH_BMSK 0xf000000 +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_1_CLIENT_8_MAX_DEPTH_SHFT 0x18 +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_1_CLIENT_7_MAX_DEPTH_BMSK 0xf0000 +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_1_CLIENT_7_MAX_DEPTH_SHFT 0x10 +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_1_CLIENT_6_MAX_DEPTH_BMSK 0xf00 +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_1_CLIENT_6_MAX_DEPTH_SHFT 0x8 +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_1_CLIENT_5_MAX_DEPTH_BMSK 0xf +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_1_CLIENT_5_MAX_DEPTH_SHFT 0x0 + +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x000002e0) +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000002e0) +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000002e0) +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_RMSK 0xff7 +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_ATTR 0x3 +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_IN \ + in_dword_masked(HWIO_IPA_HPS_DPS_CMDQ_CMD_ADDR, HWIO_IPA_HPS_DPS_CMDQ_CMD_RMSK) +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_INM(m) \ + in_dword_masked(HWIO_IPA_HPS_DPS_CMDQ_CMD_ADDR, m) +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_OUT(v) \ + out_dword(HWIO_IPA_HPS_DPS_CMDQ_CMD_ADDR,v) +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_HPS_DPS_CMDQ_CMD_ADDR,m,v,HWIO_IPA_HPS_DPS_CMDQ_CMD_IN) +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_CMD_CLIENT_BMSK 0xff0 +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_CMD_CLIENT_SHFT 0x4 +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_RD_REQ_BMSK 0x4 +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_RD_REQ_SHFT 0x2 +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_POP_CMD_BMSK 0x2 +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_POP_CMD_SHFT 0x1 +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_WRITE_CMD_BMSK 0x1 +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_WRITE_CMD_SHFT 0x0 + +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_ADDR (IPA_DEBUG_REG_BASE + 0x000002e4) +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000002e4) +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000002e4) +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_RMSK 0xffffff +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_ATTR 0x3 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_IN \ + in_dword_masked(HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_ADDR, HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_RMSK) +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_INM(m) \ + in_dword_masked(HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_ADDR, m) +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_OUT(v) \ + out_dword(HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_ADDR,v) +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_ADDR,m,v,HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_IN) +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_CMDQ_VIRT_COD_F_BMSK 0x800000 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_CMDQ_VIRT_COD_F_SHFT 0x17 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_CMDQ_TYPE_F_BMSK 0x400000 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_CMDQ_TYPE_F_SHFT 0x16 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_CMDQ_OPCODE_F_BMSK 0x300000 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_CMDQ_OPCODE_F_SHFT 0x14 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_CMDQ_SRC_PIPE_F_BMSK 0xff000 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_CMDQ_SRC_PIPE_F_SHFT 0xc +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_CMDQ_SRC_ID_F_BMSK 0xff0 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_CMDQ_SRC_ID_F_SHFT 0x4 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_CMDQ_CTX_ID_F_BMSK 0xf +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_CMDQ_CTX_ID_F_SHFT 0x0 + +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_ADDR (IPA_DEBUG_REG_BASE + 0x000002e8) +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000002e8) +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000002e8) +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_RMSK 0xffffff +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_ATTR 0x1 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_IN \ + in_dword_masked(HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_ADDR, HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_RMSK, HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_ATTR) +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_INM(m) \ + in_dword_masked(HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_ADDR, m, HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_ATTR) +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_CMDQ_VIRT_COD_F_BMSK 0x800000 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_CMDQ_VIRT_COD_F_SHFT 0x17 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_CMDQ_TYPE_F_BMSK 0x400000 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_CMDQ_TYPE_F_SHFT 0x16 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_CMDQ_OPCODE_F_BMSK 0x300000 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_CMDQ_OPCODE_F_SHFT 0x14 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_CMDQ_SRC_PIPE_F_BMSK 0xff000 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_CMDQ_SRC_PIPE_F_SHFT 0xc +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_CMDQ_SRC_ID_F_BMSK 0xff0 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_CMDQ_SRC_ID_F_SHFT 0x4 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_CMDQ_CTX_ID_F_BMSK 0xf +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_CMDQ_CTX_ID_F_SHFT 0x0 + +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x000002ec) +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000002ec) +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000002ec) +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_RMSK 0xff3 +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_ATTR 0x1 +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_IN \ + in_dword_masked(HWIO_IPA_HPS_DPS_CMDQ_STATUS_ADDR, HWIO_IPA_HPS_DPS_CMDQ_STATUS_RMSK, HWIO_IPA_HPS_DPS_CMDQ_STATUS_ATTR) +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_INM(m) \ + in_dword_masked(HWIO_IPA_HPS_DPS_CMDQ_STATUS_ADDR, m, HWIO_IPA_HPS_DPS_CMDQ_STATUS_ATTR) +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_CMDQ_DEPTH_BMSK 0xff0 +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_CMDQ_DEPTH_SHFT 0x4 +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_CMDQ_FULL_BMSK 0x2 +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_CMDQ_FULL_SHFT 0x1 +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_STATUS_BMSK 0x1 +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_STATUS_SHFT 0x0 + +#define HWIO_IPA_HPS_DPS_SNP_ADDR (IPA_DEBUG_REG_BASE + 0x000002f0) +#define HWIO_IPA_HPS_DPS_SNP_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000002f0) +#define HWIO_IPA_HPS_DPS_SNP_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000002f0) +#define HWIO_IPA_HPS_DPS_SNP_RMSK 0xfffffff +#define HWIO_IPA_HPS_DPS_SNP_ATTR 0x3 +#define HWIO_IPA_HPS_DPS_SNP_IN \ + in_dword_masked(HWIO_IPA_HPS_DPS_SNP_ADDR, HWIO_IPA_HPS_DPS_SNP_RMSK) +#define HWIO_IPA_HPS_DPS_SNP_INM(m) \ + in_dword_masked(HWIO_IPA_HPS_DPS_SNP_ADDR, m) +#define HWIO_IPA_HPS_DPS_SNP_OUT(v) \ + out_dword(HWIO_IPA_HPS_DPS_SNP_ADDR,v) +#define HWIO_IPA_HPS_DPS_SNP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_HPS_DPS_SNP_ADDR,m,v,HWIO_IPA_HPS_DPS_SNP_IN) +#define HWIO_IPA_HPS_DPS_SNP_SNP_ADDR_BMSK 0xff00000 +#define HWIO_IPA_HPS_DPS_SNP_SNP_ADDR_SHFT 0x14 +#define HWIO_IPA_HPS_DPS_SNP_SNP_HEAD_BMSK 0xff000 +#define HWIO_IPA_HPS_DPS_SNP_SNP_HEAD_SHFT 0xc +#define HWIO_IPA_HPS_DPS_SNP_SNP_NEXT_BMSK 0xff0 +#define HWIO_IPA_HPS_DPS_SNP_SNP_NEXT_SHFT 0x4 +#define HWIO_IPA_HPS_DPS_SNP_SNP_NEXT_IS_VALID_BMSK 0x8 +#define HWIO_IPA_HPS_DPS_SNP_SNP_NEXT_IS_VALID_SHFT 0x3 +#define HWIO_IPA_HPS_DPS_SNP_SNP_VALID_BMSK 0x4 +#define HWIO_IPA_HPS_DPS_SNP_SNP_VALID_SHFT 0x2 +#define HWIO_IPA_HPS_DPS_SNP_SNP_WRITE_BMSK 0x2 +#define HWIO_IPA_HPS_DPS_SNP_SNP_WRITE_SHFT 0x1 +#define HWIO_IPA_HPS_DPS_SNP_SNP_LAST_BMSK 0x1 +#define HWIO_IPA_HPS_DPS_SNP_SNP_LAST_SHFT 0x0 + +#define HWIO_IPA_HPS_DPS_CMDQ_COUNT_ADDR (IPA_DEBUG_REG_BASE + 0x000002f4) +#define HWIO_IPA_HPS_DPS_CMDQ_COUNT_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000002f4) +#define HWIO_IPA_HPS_DPS_CMDQ_COUNT_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000002f4) +#define HWIO_IPA_HPS_DPS_CMDQ_COUNT_RMSK 0xff +#define HWIO_IPA_HPS_DPS_CMDQ_COUNT_ATTR 0x1 +#define HWIO_IPA_HPS_DPS_CMDQ_COUNT_IN \ + in_dword_masked(HWIO_IPA_HPS_DPS_CMDQ_COUNT_ADDR, HWIO_IPA_HPS_DPS_CMDQ_COUNT_RMSK, HWIO_IPA_HPS_DPS_CMDQ_COUNT_ATTR) +#define HWIO_IPA_HPS_DPS_CMDQ_COUNT_INM(m) \ + in_dword_masked(HWIO_IPA_HPS_DPS_CMDQ_COUNT_ADDR, m, HWIO_IPA_HPS_DPS_CMDQ_COUNT_ATTR) +#define HWIO_IPA_HPS_DPS_CMDQ_COUNT_FIFO_COUNT_BMSK 0xff +#define HWIO_IPA_HPS_DPS_CMDQ_COUNT_FIFO_COUNT_SHFT 0x0 + +#define HWIO_IPA_HPS_DPS_CMDQ_RELEASE_WR_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x00000300 + 0x4 * (n)) +#define HWIO_IPA_HPS_DPS_CMDQ_RELEASE_WR_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x00000300 + 0x4 * (n)) +#define HWIO_IPA_HPS_DPS_CMDQ_RELEASE_WR_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x00000300 + 0x4 * (n)) +#define HWIO_IPA_HPS_DPS_CMDQ_RELEASE_WR_n_RMSK 0xffffffff +#define HWIO_IPA_HPS_DPS_CMDQ_RELEASE_WR_n_MAXn 1 +#define HWIO_IPA_HPS_DPS_CMDQ_RELEASE_WR_n_ATTR 0x2 +#define HWIO_IPA_HPS_DPS_CMDQ_RELEASE_WR_n_OUTI(n,val) \ + out_dword(HWIO_IPA_HPS_DPS_CMDQ_RELEASE_WR_n_ADDR(n),val) +#define HWIO_IPA_HPS_DPS_CMDQ_RELEASE_WR_n_RELEASE_WR_CMD_BMSK 0xffffffff +#define HWIO_IPA_HPS_DPS_CMDQ_RELEASE_WR_n_RELEASE_WR_CMD_SHFT 0x0 + +#define HWIO_IPA_HPS_DPS_CMDQ_RELEASE_RD_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x00000320 + 0x4 * (n)) +#define HWIO_IPA_HPS_DPS_CMDQ_RELEASE_RD_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x00000320 + 0x4 * (n)) +#define HWIO_IPA_HPS_DPS_CMDQ_RELEASE_RD_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x00000320 + 0x4 * (n)) +#define HWIO_IPA_HPS_DPS_CMDQ_RELEASE_RD_n_RMSK 0xffffffff +#define HWIO_IPA_HPS_DPS_CMDQ_RELEASE_RD_n_MAXn 1 +#define HWIO_IPA_HPS_DPS_CMDQ_RELEASE_RD_n_ATTR 0x2 +#define HWIO_IPA_HPS_DPS_CMDQ_RELEASE_RD_n_OUTI(n,val) \ + out_dword(HWIO_IPA_HPS_DPS_CMDQ_RELEASE_RD_n_ADDR(n),val) +#define HWIO_IPA_HPS_DPS_CMDQ_RELEASE_RD_n_RELEASE_RD_CMD_BMSK 0xffffffff +#define HWIO_IPA_HPS_DPS_CMDQ_RELEASE_RD_n_RELEASE_RD_CMD_SHFT 0x0 + +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_WR_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x00000340 + 0x4 * (n)) +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_WR_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x00000340 + 0x4 * (n)) +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_WR_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x00000340 + 0x4 * (n)) +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_WR_n_RMSK 0xffffffff +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_WR_n_MAXn 1 +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_WR_n_ATTR 0x3 +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_WR_n_INI(n) \ + in_dword_masked(HWIO_IPA_HPS_DPS_CMDQ_CFG_WR_n_ADDR(n), HWIO_IPA_HPS_DPS_CMDQ_CFG_WR_n_RMSK) +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_WR_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_HPS_DPS_CMDQ_CFG_WR_n_ADDR(n), mask) +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_WR_n_OUTI(n,val) \ + out_dword(HWIO_IPA_HPS_DPS_CMDQ_CFG_WR_n_ADDR(n),val) +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_WR_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_HPS_DPS_CMDQ_CFG_WR_n_ADDR(n),mask,val,HWIO_IPA_HPS_DPS_CMDQ_CFG_WR_n_INI(n)) +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_WR_n_BLOCK_WR_BMSK 0xffffffff +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_WR_n_BLOCK_WR_SHFT 0x0 + +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_RD_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x00000360 + 0x4 * (n)) +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_RD_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x00000360 + 0x4 * (n)) +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_RD_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x00000360 + 0x4 * (n)) +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_RD_n_RMSK 0xffffffff +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_RD_n_MAXn 1 +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_RD_n_ATTR 0x3 +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_RD_n_INI(n) \ + in_dword_masked(HWIO_IPA_HPS_DPS_CMDQ_CFG_RD_n_ADDR(n), HWIO_IPA_HPS_DPS_CMDQ_CFG_RD_n_RMSK) +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_RD_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_HPS_DPS_CMDQ_CFG_RD_n_ADDR(n), mask) +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_RD_n_OUTI(n,val) \ + out_dword(HWIO_IPA_HPS_DPS_CMDQ_CFG_RD_n_ADDR(n),val) +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_RD_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_HPS_DPS_CMDQ_CFG_RD_n_ADDR(n),mask,val,HWIO_IPA_HPS_DPS_CMDQ_CFG_RD_n_INI(n)) +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_RD_n_BLOCK_RD_BMSK 0xffffffff +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_RD_n_BLOCK_RD_SHFT 0x0 + +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_EMPTY_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x00000380 + 0x4 * (n)) +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_EMPTY_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x00000380 + 0x4 * (n)) +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_EMPTY_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x00000380 + 0x4 * (n)) +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_EMPTY_n_RMSK 0xffffffff +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_EMPTY_n_MAXn 1 +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_EMPTY_n_ATTR 0x1 +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_EMPTY_n_INI(n) \ + in_dword_masked(HWIO_IPA_HPS_DPS_CMDQ_STATUS_EMPTY_n_ADDR(n), HWIO_IPA_HPS_DPS_CMDQ_STATUS_EMPTY_n_RMSK) +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_EMPTY_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_HPS_DPS_CMDQ_STATUS_EMPTY_n_ADDR(n), mask) +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_EMPTY_n_CMDQ_EMPTY_BMSK 0xffffffff +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_EMPTY_n_CMDQ_EMPTY_SHFT 0x0 + +#define HWIO_IPA_DPS_TX_CMDQ_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x00000400) +#define HWIO_IPA_DPS_TX_CMDQ_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000400) +#define HWIO_IPA_DPS_TX_CMDQ_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000400) +#define HWIO_IPA_DPS_TX_CMDQ_CMD_RMSK 0x7f +#define HWIO_IPA_DPS_TX_CMDQ_CMD_ATTR 0x3 +#define HWIO_IPA_DPS_TX_CMDQ_CMD_IN \ + in_dword_masked(HWIO_IPA_DPS_TX_CMDQ_CMD_ADDR, HWIO_IPA_DPS_TX_CMDQ_CMD_RMSK) +#define HWIO_IPA_DPS_TX_CMDQ_CMD_INM(m) \ + in_dword_masked(HWIO_IPA_DPS_TX_CMDQ_CMD_ADDR, m) +#define HWIO_IPA_DPS_TX_CMDQ_CMD_OUT(v) \ + out_dword(HWIO_IPA_DPS_TX_CMDQ_CMD_ADDR,v) +#define HWIO_IPA_DPS_TX_CMDQ_CMD_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_DPS_TX_CMDQ_CMD_ADDR,m,v,HWIO_IPA_DPS_TX_CMDQ_CMD_IN) +#define HWIO_IPA_DPS_TX_CMDQ_CMD_CMD_CLIENT_BMSK 0x78 +#define HWIO_IPA_DPS_TX_CMDQ_CMD_CMD_CLIENT_SHFT 0x3 +#define HWIO_IPA_DPS_TX_CMDQ_CMD_RD_REQ_BMSK 0x4 +#define HWIO_IPA_DPS_TX_CMDQ_CMD_RD_REQ_SHFT 0x2 +#define HWIO_IPA_DPS_TX_CMDQ_CMD_POP_CMD_BMSK 0x2 +#define HWIO_IPA_DPS_TX_CMDQ_CMD_POP_CMD_SHFT 0x1 +#define HWIO_IPA_DPS_TX_CMDQ_CMD_WRITE_CMD_BMSK 0x1 +#define HWIO_IPA_DPS_TX_CMDQ_CMD_WRITE_CMD_SHFT 0x0 + +#define HWIO_IPA_DPS_TX_CMDQ_RELEASE_WR_ADDR (IPA_DEBUG_REG_BASE + 0x00000404) +#define HWIO_IPA_DPS_TX_CMDQ_RELEASE_WR_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000404) +#define HWIO_IPA_DPS_TX_CMDQ_RELEASE_WR_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000404) +#define HWIO_IPA_DPS_TX_CMDQ_RELEASE_WR_RMSK 0xfff +#define HWIO_IPA_DPS_TX_CMDQ_RELEASE_WR_ATTR 0x2 +#define HWIO_IPA_DPS_TX_CMDQ_RELEASE_WR_OUT(v) \ + out_dword(HWIO_IPA_DPS_TX_CMDQ_RELEASE_WR_ADDR,v) +#define HWIO_IPA_DPS_TX_CMDQ_RELEASE_WR_RELEASE_WR_CMD_BMSK 0xfff +#define HWIO_IPA_DPS_TX_CMDQ_RELEASE_WR_RELEASE_WR_CMD_SHFT 0x0 + +#define HWIO_IPA_DPS_TX_CMDQ_RELEASE_RD_ADDR (IPA_DEBUG_REG_BASE + 0x00000408) +#define HWIO_IPA_DPS_TX_CMDQ_RELEASE_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000408) +#define HWIO_IPA_DPS_TX_CMDQ_RELEASE_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000408) +#define HWIO_IPA_DPS_TX_CMDQ_RELEASE_RD_RMSK 0xfff +#define HWIO_IPA_DPS_TX_CMDQ_RELEASE_RD_ATTR 0x2 +#define HWIO_IPA_DPS_TX_CMDQ_RELEASE_RD_OUT(v) \ + out_dword(HWIO_IPA_DPS_TX_CMDQ_RELEASE_RD_ADDR,v) +#define HWIO_IPA_DPS_TX_CMDQ_RELEASE_RD_RELEASE_RD_CMD_BMSK 0xfff +#define HWIO_IPA_DPS_TX_CMDQ_RELEASE_RD_RELEASE_RD_CMD_SHFT 0x0 + +#define HWIO_IPA_DPS_TX_CMDQ_CFG_WR_ADDR (IPA_DEBUG_REG_BASE + 0x0000040c) +#define HWIO_IPA_DPS_TX_CMDQ_CFG_WR_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000040c) +#define HWIO_IPA_DPS_TX_CMDQ_CFG_WR_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000040c) +#define HWIO_IPA_DPS_TX_CMDQ_CFG_WR_RMSK 0xfff +#define HWIO_IPA_DPS_TX_CMDQ_CFG_WR_ATTR 0x3 +#define HWIO_IPA_DPS_TX_CMDQ_CFG_WR_IN \ + in_dword_masked(HWIO_IPA_DPS_TX_CMDQ_CFG_WR_ADDR, HWIO_IPA_DPS_TX_CMDQ_CFG_WR_RMSK) +#define HWIO_IPA_DPS_TX_CMDQ_CFG_WR_INM(m) \ + in_dword_masked(HWIO_IPA_DPS_TX_CMDQ_CFG_WR_ADDR, m) +#define HWIO_IPA_DPS_TX_CMDQ_CFG_WR_OUT(v) \ + out_dword(HWIO_IPA_DPS_TX_CMDQ_CFG_WR_ADDR,v) +#define HWIO_IPA_DPS_TX_CMDQ_CFG_WR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_DPS_TX_CMDQ_CFG_WR_ADDR,m,v,HWIO_IPA_DPS_TX_CMDQ_CFG_WR_IN) +#define HWIO_IPA_DPS_TX_CMDQ_CFG_WR_BLOCK_WR_BMSK 0xfff +#define HWIO_IPA_DPS_TX_CMDQ_CFG_WR_BLOCK_WR_SHFT 0x0 + +#define HWIO_IPA_DPS_TX_CMDQ_CFG_RD_ADDR (IPA_DEBUG_REG_BASE + 0x00000410) +#define HWIO_IPA_DPS_TX_CMDQ_CFG_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000410) +#define HWIO_IPA_DPS_TX_CMDQ_CFG_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000410) +#define HWIO_IPA_DPS_TX_CMDQ_CFG_RD_RMSK 0xfff +#define HWIO_IPA_DPS_TX_CMDQ_CFG_RD_ATTR 0x3 +#define HWIO_IPA_DPS_TX_CMDQ_CFG_RD_IN \ + in_dword_masked(HWIO_IPA_DPS_TX_CMDQ_CFG_RD_ADDR, HWIO_IPA_DPS_TX_CMDQ_CFG_RD_RMSK) +#define HWIO_IPA_DPS_TX_CMDQ_CFG_RD_INM(m) \ + in_dword_masked(HWIO_IPA_DPS_TX_CMDQ_CFG_RD_ADDR, m) +#define HWIO_IPA_DPS_TX_CMDQ_CFG_RD_OUT(v) \ + out_dword(HWIO_IPA_DPS_TX_CMDQ_CFG_RD_ADDR,v) +#define HWIO_IPA_DPS_TX_CMDQ_CFG_RD_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_DPS_TX_CMDQ_CFG_RD_ADDR,m,v,HWIO_IPA_DPS_TX_CMDQ_CFG_RD_IN) +#define HWIO_IPA_DPS_TX_CMDQ_CFG_RD_BLOCK_RD_BMSK 0xfff +#define HWIO_IPA_DPS_TX_CMDQ_CFG_RD_BLOCK_RD_SHFT 0x0 + +#define HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_ADDR (IPA_DEBUG_REG_BASE + 0x00000414) +#define HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000414) +#define HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000414) +#define HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_RMSK 0x7ffffff +#define HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_ATTR 0x3 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_IN \ + in_dword_masked(HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_ADDR, HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_RMSK) +#define HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_INM(m) \ + in_dword_masked(HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_ADDR, m) +#define HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_OUT(v) \ + out_dword(HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_ADDR,v) +#define HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_ADDR,m,v,HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_IN) +#define HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_SEG_CTX_ID_F_BMSK 0x6000000 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_SEG_CTX_ID_F_SHFT 0x19 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_SEG_VALID_F_BMSK 0x1000000 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_SEG_VALID_F_SHFT 0x18 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_CMDQ_VIRT_COD_F_BMSK 0x800000 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_CMDQ_VIRT_COD_F_SHFT 0x17 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_CMDQ_TYPE_F_BMSK 0x400000 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_CMDQ_TYPE_F_SHFT 0x16 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_CMDQ_OPCODE_F_BMSK 0x300000 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_CMDQ_OPCODE_F_SHFT 0x14 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_CMDQ_SRC_PIPE_F_BMSK 0xff000 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_CMDQ_SRC_PIPE_F_SHFT 0xc +#define HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_CMDQ_SRC_ID_F_BMSK 0xff0 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_CMDQ_SRC_ID_F_SHFT 0x4 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_CMDQ_CTX_ID_F_BMSK 0xf +#define HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_CMDQ_CTX_ID_F_SHFT 0x0 + +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_ADDR (IPA_DEBUG_REG_BASE + 0x00000418) +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000418) +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000418) +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_RMSK 0x7ffffff +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_ATTR 0x1 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_IN \ + in_dword_masked(HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_ADDR, HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_RMSK, HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_ATTR) +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_INM(m) \ + in_dword_masked(HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_ADDR, m, HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_ATTR) +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_SEG_CTX_ID_F_BMSK 0x6000000 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_SEG_CTX_ID_F_SHFT 0x19 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_SEG_VALID_F_BMSK 0x1000000 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_SEG_VALID_F_SHFT 0x18 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_CMDQ_VIRT_COD_F_BMSK 0x800000 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_CMDQ_VIRT_COD_F_SHFT 0x17 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_CMDQ_TYPE_F_BMSK 0x400000 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_CMDQ_TYPE_F_SHFT 0x16 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_CMDQ_OPCODE_F_BMSK 0x300000 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_CMDQ_OPCODE_F_SHFT 0x14 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_CMDQ_SRC_PIPE_F_BMSK 0xff000 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_CMDQ_SRC_PIPE_F_SHFT 0xc +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_CMDQ_SRC_ID_F_BMSK 0xff0 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_CMDQ_SRC_ID_F_SHFT 0x4 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_CMDQ_CTX_ID_F_BMSK 0xf +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_CMDQ_CTX_ID_F_SHFT 0x0 + +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x0000041c) +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000041c) +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000041c) +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_RMSK 0xff3 +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_ATTR 0x1 +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_IN \ + in_dword_masked(HWIO_IPA_DPS_TX_CMDQ_STATUS_ADDR, HWIO_IPA_DPS_TX_CMDQ_STATUS_RMSK, HWIO_IPA_DPS_TX_CMDQ_STATUS_ATTR) +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_INM(m) \ + in_dword_masked(HWIO_IPA_DPS_TX_CMDQ_STATUS_ADDR, m, HWIO_IPA_DPS_TX_CMDQ_STATUS_ATTR) +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_CMDQ_DEPTH_BMSK 0xff0 +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_CMDQ_DEPTH_SHFT 0x4 +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_CMDQ_FULL_BMSK 0x2 +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_CMDQ_FULL_SHFT 0x1 +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_STATUS_BMSK 0x1 +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_STATUS_SHFT 0x0 + +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_EMPTY_ADDR (IPA_DEBUG_REG_BASE + 0x00000420) +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_EMPTY_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000420) +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_EMPTY_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000420) +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_EMPTY_RMSK 0xfff +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_EMPTY_ATTR 0x1 +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_EMPTY_IN \ + in_dword_masked(HWIO_IPA_DPS_TX_CMDQ_STATUS_EMPTY_ADDR, HWIO_IPA_DPS_TX_CMDQ_STATUS_EMPTY_RMSK) +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_EMPTY_INM(m) \ + in_dword_masked(HWIO_IPA_DPS_TX_CMDQ_STATUS_EMPTY_ADDR, m) +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_EMPTY_CMDQ_EMPTY_BMSK 0xfff +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_EMPTY_CMDQ_EMPTY_SHFT 0x0 + +#define HWIO_IPA_DPS_TX_SNP_ADDR (IPA_DEBUG_REG_BASE + 0x00000424) +#define HWIO_IPA_DPS_TX_SNP_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000424) +#define HWIO_IPA_DPS_TX_SNP_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000424) +#define HWIO_IPA_DPS_TX_SNP_RMSK 0xfffffff +#define HWIO_IPA_DPS_TX_SNP_ATTR 0x3 +#define HWIO_IPA_DPS_TX_SNP_IN \ + in_dword_masked(HWIO_IPA_DPS_TX_SNP_ADDR, HWIO_IPA_DPS_TX_SNP_RMSK) +#define HWIO_IPA_DPS_TX_SNP_INM(m) \ + in_dword_masked(HWIO_IPA_DPS_TX_SNP_ADDR, m) +#define HWIO_IPA_DPS_TX_SNP_OUT(v) \ + out_dword(HWIO_IPA_DPS_TX_SNP_ADDR,v) +#define HWIO_IPA_DPS_TX_SNP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_DPS_TX_SNP_ADDR,m,v,HWIO_IPA_DPS_TX_SNP_IN) +#define HWIO_IPA_DPS_TX_SNP_SNP_ADDR_BMSK 0xff00000 +#define HWIO_IPA_DPS_TX_SNP_SNP_ADDR_SHFT 0x14 +#define HWIO_IPA_DPS_TX_SNP_SNP_HEAD_BMSK 0xff000 +#define HWIO_IPA_DPS_TX_SNP_SNP_HEAD_SHFT 0xc +#define HWIO_IPA_DPS_TX_SNP_SNP_NEXT_BMSK 0xff0 +#define HWIO_IPA_DPS_TX_SNP_SNP_NEXT_SHFT 0x4 +#define HWIO_IPA_DPS_TX_SNP_SNP_NEXT_IS_VALID_BMSK 0x8 +#define HWIO_IPA_DPS_TX_SNP_SNP_NEXT_IS_VALID_SHFT 0x3 +#define HWIO_IPA_DPS_TX_SNP_SNP_VALID_BMSK 0x4 +#define HWIO_IPA_DPS_TX_SNP_SNP_VALID_SHFT 0x2 +#define HWIO_IPA_DPS_TX_SNP_SNP_WRITE_BMSK 0x2 +#define HWIO_IPA_DPS_TX_SNP_SNP_WRITE_SHFT 0x1 +#define HWIO_IPA_DPS_TX_SNP_SNP_LAST_BMSK 0x1 +#define HWIO_IPA_DPS_TX_SNP_SNP_LAST_SHFT 0x0 + +#define HWIO_IPA_DPS_TX_CMDQ_COUNT_ADDR (IPA_DEBUG_REG_BASE + 0x00000428) +#define HWIO_IPA_DPS_TX_CMDQ_COUNT_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000428) +#define HWIO_IPA_DPS_TX_CMDQ_COUNT_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000428) +#define HWIO_IPA_DPS_TX_CMDQ_COUNT_RMSK 0x7f +#define HWIO_IPA_DPS_TX_CMDQ_COUNT_ATTR 0x1 +#define HWIO_IPA_DPS_TX_CMDQ_COUNT_IN \ + in_dword_masked(HWIO_IPA_DPS_TX_CMDQ_COUNT_ADDR, HWIO_IPA_DPS_TX_CMDQ_COUNT_RMSK, HWIO_IPA_DPS_TX_CMDQ_COUNT_ATTR) +#define HWIO_IPA_DPS_TX_CMDQ_COUNT_INM(m) \ + in_dword_masked(HWIO_IPA_DPS_TX_CMDQ_COUNT_ADDR, m, HWIO_IPA_DPS_TX_CMDQ_COUNT_ATTR) +#define HWIO_IPA_DPS_TX_CMDQ_COUNT_FIFO_COUNT_BMSK 0x7f +#define HWIO_IPA_DPS_TX_CMDQ_COUNT_FIFO_COUNT_SHFT 0x0 + +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_CFG_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x0000042c + 0x4 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_CFG_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x0000042c + 0x4 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_CFG_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x0000042c + 0x4 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_CFG_n_RMSK 0x1f1 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_CFG_n_MAXn 2 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_CFG_n_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_CFG_n_INI(n) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_CFG_n_ADDR(n), HWIO_IPA_LOG_BUF_HW_SNIF_EL_CFG_n_RMSK) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_CFG_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_CFG_n_ADDR(n), mask) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_CFG_n_OUTI(n,val) \ + out_dword(HWIO_IPA_LOG_BUF_HW_SNIF_EL_CFG_n_ADDR(n),val) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_CFG_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_LOG_BUF_HW_SNIF_EL_CFG_n_ADDR(n),mask,val,HWIO_IPA_LOG_BUF_HW_SNIF_EL_CFG_n_INI(n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_CFG_n_SNIF_EL_SELECT_BMSK 0x1f0 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_CFG_n_SNIF_EL_SELECT_SHFT 0x4 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_CFG_n_SNIF_EL_ENABLE_BMSK 0x1 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_CFG_n_SNIF_EL_ENABLE_SHFT 0x0 + +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x00000438 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x00000438 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x00000438 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_MAXn 2 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_INI(n) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_ADDR(n), HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_RMSK) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_ADDR(n), mask) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_OUTI(n,val) \ + out_dword(HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_ADDR(n),val) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_ADDR(n),mask,val,HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_INI(n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_VALUE_SHFT 0x0 + +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x0000043c + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x0000043c + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x0000043c + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_MAXn 2 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_INI(n) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_ADDR(n), HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_RMSK) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_ADDR(n), mask) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_OUTI(n,val) \ + out_dword(HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_ADDR(n),val) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_ADDR(n),mask,val,HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_INI(n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_VALUE_SHFT 0x0 + +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x00000440 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x00000440 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x00000440 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_MAXn 2 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_INI(n) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_ADDR(n), HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_RMSK) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_ADDR(n), mask) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_OUTI(n,val) \ + out_dword(HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_ADDR(n),val) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_ADDR(n),mask,val,HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_INI(n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_VALUE_SHFT 0x0 + +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x00000444 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x00000444 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x00000444 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_MAXn 2 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_INI(n) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_ADDR(n), HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_RMSK) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_ADDR(n), mask) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_OUTI(n,val) \ + out_dword(HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_ADDR(n),val) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_ADDR(n),mask,val,HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_INI(n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_VALUE_SHFT 0x0 + +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x00000468 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x00000468 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x00000468 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_MAXn 2 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_INI(n) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_ADDR(n), HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_RMSK) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_ADDR(n), mask) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_OUTI(n,val) \ + out_dword(HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_ADDR(n),val) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_ADDR(n),mask,val,HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_INI(n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_VALUE_SHFT 0x0 + +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x0000046c + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x0000046c + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x0000046c + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_MAXn 2 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_INI(n) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_ADDR(n), HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_RMSK) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_ADDR(n), mask) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_OUTI(n,val) \ + out_dword(HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_ADDR(n),val) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_ADDR(n),mask,val,HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_INI(n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_VALUE_SHFT 0x0 + +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x00000470 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x00000470 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x00000470 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_MAXn 2 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_INI(n) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_ADDR(n), HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_RMSK) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_ADDR(n), mask) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_OUTI(n,val) \ + out_dword(HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_ADDR(n),val) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_ADDR(n),mask,val,HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_INI(n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_VALUE_SHFT 0x0 + +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x00000474 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x00000474 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x00000474 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_MAXn 2 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_INI(n) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_ADDR(n), HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_RMSK) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_ADDR(n), mask) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_OUTI(n,val) \ + out_dword(HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_ADDR(n),val) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_ADDR(n),mask,val,HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_INI(n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_VALUE_SHFT 0x0 + +#define HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_ADDR (IPA_DEBUG_REG_BASE + 0x00000498) +#define HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000498) +#define HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000498) +#define HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_RMSK 0x7 +#define HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_IN \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_ADDR, HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_RMSK) +#define HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_INM(m) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_ADDR, m) +#define HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_OUT(v) \ + out_dword(HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_ADDR,v) +#define HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_ADDR,m,v,HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_IN) +#define HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_SRC_GROUP_SEL_BMSK 0x7 +#define HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_SRC_GROUP_SEL_SHFT 0x0 + +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x000004a0) +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000004a0) +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000004a0) +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_RMSK 0x7ff +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_ATTR 0x3 +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_IN \ + in_dword_masked(HWIO_IPA_ACKMNGR_CMDQ_CMD_ADDR, HWIO_IPA_ACKMNGR_CMDQ_CMD_RMSK) +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_INM(m) \ + in_dword_masked(HWIO_IPA_ACKMNGR_CMDQ_CMD_ADDR, m) +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_OUT(v) \ + out_dword(HWIO_IPA_ACKMNGR_CMDQ_CMD_ADDR,v) +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_ACKMNGR_CMDQ_CMD_ADDR,m,v,HWIO_IPA_ACKMNGR_CMDQ_CMD_IN) +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_RD_REQ_BMSK 0x400 +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_RD_REQ_SHFT 0xa +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_CMD_CLIENT_BMSK 0x3fc +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_CMD_CLIENT_SHFT 0x2 +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_POP_CMD_BMSK 0x2 +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_POP_CMD_SHFT 0x1 +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_WRITE_CMD_BMSK 0x1 +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_WRITE_CMD_SHFT 0x0 + +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_ADDR (IPA_DEBUG_REG_BASE + 0x000004b8) +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000004b8) +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000004b8) +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_RMSK 0xfffffff +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_ATTR 0x1 +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_IN \ + in_dword_masked(HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_ADDR, HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_RMSK, HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_ATTR) +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_INM(m) \ + in_dword_masked(HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_ADDR, m, HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_ATTR) +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_CMDQ_ERROR_BMSK 0x8000000 +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_CMDQ_ERROR_SHFT 0x1b +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_CMDQ_SRC_ID_VALID_BMSK 0x4000000 +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_CMDQ_SRC_ID_VALID_SHFT 0x1a +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_CMDQ_SENT_BMSK 0x2000000 +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_CMDQ_SENT_SHFT 0x19 +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_CMDQ_ORIGIN_BMSK 0x1000000 +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_CMDQ_ORIGIN_SHFT 0x18 +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_CMDQ_LENGTH_BMSK 0xffff00 +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_CMDQ_LENGTH_SHFT 0x8 +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_CMDQ_SRC_ID_BMSK 0xff +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_CMDQ_SRC_ID_SHFT 0x0 + +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x000004bc) +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000004bc) +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000004bc) +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_RMSK 0x1ff +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_ATTR 0x1 +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_IN \ + in_dword_masked(HWIO_IPA_ACKMNGR_CMDQ_STATUS_ADDR, HWIO_IPA_ACKMNGR_CMDQ_STATUS_RMSK, HWIO_IPA_ACKMNGR_CMDQ_STATUS_ATTR) +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_INM(m) \ + in_dword_masked(HWIO_IPA_ACKMNGR_CMDQ_STATUS_ADDR, m, HWIO_IPA_ACKMNGR_CMDQ_STATUS_ATTR) +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_CMDQ_DEPTH_BMSK 0x1fc +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_CMDQ_DEPTH_SHFT 0x2 +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_CMDQ_FULL_BMSK 0x2 +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_CMDQ_FULL_SHFT 0x1 +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_STATUS_BMSK 0x1 +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_STATUS_SHFT 0x0 + +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_EMPTY_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x000004c0 + 0x4 * (n)) +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_EMPTY_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x000004c0 + 0x4 * (n)) +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_EMPTY_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x000004c0 + 0x4 * (n)) +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_EMPTY_n_RMSK 0xffffffff +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_EMPTY_n_MAXn 1 +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_EMPTY_n_ATTR 0x1 +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_EMPTY_n_INI(n) \ + in_dword_masked(HWIO_IPA_ACKMNGR_CMDQ_STATUS_EMPTY_n_ADDR(n), HWIO_IPA_ACKMNGR_CMDQ_STATUS_EMPTY_n_RMSK) +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_EMPTY_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ACKMNGR_CMDQ_STATUS_EMPTY_n_ADDR(n), mask) +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_EMPTY_n_CMDQ_EMPTY_BMSK 0xffffffff +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_EMPTY_n_CMDQ_EMPTY_SHFT 0x0 + +#define HWIO_IPA_ACKMNGR_CMDQ_COUNT_ADDR (IPA_DEBUG_REG_BASE + 0x000004e0) +#define HWIO_IPA_ACKMNGR_CMDQ_COUNT_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000004e0) +#define HWIO_IPA_ACKMNGR_CMDQ_COUNT_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000004e0) +#define HWIO_IPA_ACKMNGR_CMDQ_COUNT_RMSK 0x7f +#define HWIO_IPA_ACKMNGR_CMDQ_COUNT_ATTR 0x1 +#define HWIO_IPA_ACKMNGR_CMDQ_COUNT_IN \ + in_dword_masked(HWIO_IPA_ACKMNGR_CMDQ_COUNT_ADDR, HWIO_IPA_ACKMNGR_CMDQ_COUNT_RMSK, HWIO_IPA_ACKMNGR_CMDQ_COUNT_ATTR) +#define HWIO_IPA_ACKMNGR_CMDQ_COUNT_INM(m) \ + in_dword_masked(HWIO_IPA_ACKMNGR_CMDQ_COUNT_ADDR, m, HWIO_IPA_ACKMNGR_CMDQ_COUNT_ATTR) +#define HWIO_IPA_ACKMNGR_CMDQ_COUNT_FIFO_COUNT_BMSK 0x7f +#define HWIO_IPA_ACKMNGR_CMDQ_COUNT_FIFO_COUNT_SHFT 0x0 + +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_ADDR (IPA_DEBUG_REG_BASE + 0x000004e4) +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000004e4) +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000004e4) +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_RMSK 0x3f +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_ATTR 0x3 +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_IN \ + in_dword_masked(HWIO_IPA_GSI_FIFO_STATUS_CTRL_ADDR, HWIO_IPA_GSI_FIFO_STATUS_CTRL_RMSK) +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_FIFO_STATUS_CTRL_ADDR, m) +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_OUT(v) \ + out_dword(HWIO_IPA_GSI_FIFO_STATUS_CTRL_ADDR,v) +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GSI_FIFO_STATUS_CTRL_ADDR,m,v,HWIO_IPA_GSI_FIFO_STATUS_CTRL_IN) +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_IPA_GSI_FIFO_STATUS_EN_BMSK 0x20 +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_IPA_GSI_FIFO_STATUS_EN_SHFT 0x5 +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_IPA_GSI_FIFO_STATUS_PORT_SEL_BMSK 0x1f +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_IPA_GSI_FIFO_STATUS_PORT_SEL_SHFT 0x0 + +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x000004e8) +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000004e8) +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000004e8) +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_RMSK 0x7fffffff +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_ATTR 0x1 +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_IN \ + in_dword_masked(HWIO_IPA_GSI_TLV_FIFO_STATUS_ADDR, HWIO_IPA_GSI_TLV_FIFO_STATUS_RMSK, HWIO_IPA_GSI_TLV_FIFO_STATUS_ATTR) +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TLV_FIFO_STATUS_ADDR, m, HWIO_IPA_GSI_TLV_FIFO_STATUS_ATTR) +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FIFO_HEAD_IS_BUBBLE_BMSK 0x40000000 +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FIFO_HEAD_IS_BUBBLE_SHFT 0x1e +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FIFO_FULL_PUB_BMSK 0x20000000 +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FIFO_FULL_PUB_SHFT 0x1d +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FIFO_ALMOST_FULL_PUB_BMSK 0x10000000 +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FIFO_ALMOST_FULL_PUB_SHFT 0x1c +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FIFO_FULL_BMSK 0x8000000 +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FIFO_FULL_SHFT 0x1b +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FIFO_ALMOST_FULL_BMSK 0x4000000 +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FIFO_ALMOST_FULL_SHFT 0x1a +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FIFO_EMPTY_PUB_BMSK 0x2000000 +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FIFO_EMPTY_PUB_SHFT 0x19 +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FIFO_EMPTY_BMSK 0x1000000 +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FIFO_EMPTY_SHFT 0x18 +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FIFO_RD_PUB_PTR_BMSK 0xff0000 +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FIFO_RD_PUB_PTR_SHFT 0x10 +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FIFO_RD_PTR_BMSK 0xff00 +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FIFO_RD_PTR_SHFT 0x8 +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FIFO_WR_PTR_BMSK 0xff +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FIFO_WR_PTR_SHFT 0x0 + +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x000004ec) +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000004ec) +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000004ec) +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_RMSK 0x7fffffff +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_ATTR 0x1 +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_IN \ + in_dword_masked(HWIO_IPA_GSI_AOS_FIFO_STATUS_ADDR, HWIO_IPA_GSI_AOS_FIFO_STATUS_RMSK, HWIO_IPA_GSI_AOS_FIFO_STATUS_ATTR) +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_AOS_FIFO_STATUS_ADDR, m, HWIO_IPA_GSI_AOS_FIFO_STATUS_ATTR) +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FIFO_HEAD_IS_BUBBLE_BMSK 0x40000000 +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FIFO_HEAD_IS_BUBBLE_SHFT 0x1e +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FIFO_FULL_PUB_BMSK 0x20000000 +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FIFO_FULL_PUB_SHFT 0x1d +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FIFO_ALMOST_FULL_PUB_BMSK 0x10000000 +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FIFO_ALMOST_FULL_PUB_SHFT 0x1c +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FIFO_FULL_BMSK 0x8000000 +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FIFO_FULL_SHFT 0x1b +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FIFO_ALMOST_FULL_BMSK 0x4000000 +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FIFO_ALMOST_FULL_SHFT 0x1a +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FIFO_EMPTY_PUB_BMSK 0x2000000 +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FIFO_EMPTY_PUB_SHFT 0x19 +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FIFO_EMPTY_BMSK 0x1000000 +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FIFO_EMPTY_SHFT 0x18 +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FIFO_RD_PUB_PTR_BMSK 0xff0000 +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FIFO_RD_PUB_PTR_SHFT 0x10 +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FIFO_RD_PTR_BMSK 0xff00 +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FIFO_RD_PTR_SHFT 0x8 +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FIFO_WR_PTR_BMSK 0xff +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FIFO_WR_PTR_SHFT 0x0 + +#define HWIO_IPA_ENDP_GSI_CONS_BYTES_TLV_ADDR (IPA_DEBUG_REG_BASE + 0x000004f0) +#define HWIO_IPA_ENDP_GSI_CONS_BYTES_TLV_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000004f0) +#define HWIO_IPA_ENDP_GSI_CONS_BYTES_TLV_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000004f0) +#define HWIO_IPA_ENDP_GSI_CONS_BYTES_TLV_RMSK 0xffff +#define HWIO_IPA_ENDP_GSI_CONS_BYTES_TLV_ATTR 0x1 +#define HWIO_IPA_ENDP_GSI_CONS_BYTES_TLV_IN \ + in_dword_masked(HWIO_IPA_ENDP_GSI_CONS_BYTES_TLV_ADDR, HWIO_IPA_ENDP_GSI_CONS_BYTES_TLV_RMSK) +#define HWIO_IPA_ENDP_GSI_CONS_BYTES_TLV_INM(m) \ + in_dword_masked(HWIO_IPA_ENDP_GSI_CONS_BYTES_TLV_ADDR, m) +#define HWIO_IPA_ENDP_GSI_CONS_BYTES_TLV_CONS_BYTES_BMSK 0xffff +#define HWIO_IPA_ENDP_GSI_CONS_BYTES_TLV_CONS_BYTES_SHFT 0x0 + +#define HWIO_IPA_ENDP_GSI_CONS_BYTES_AOS_ADDR (IPA_DEBUG_REG_BASE + 0x000004f4) +#define HWIO_IPA_ENDP_GSI_CONS_BYTES_AOS_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000004f4) +#define HWIO_IPA_ENDP_GSI_CONS_BYTES_AOS_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000004f4) +#define HWIO_IPA_ENDP_GSI_CONS_BYTES_AOS_RMSK 0xffff +#define HWIO_IPA_ENDP_GSI_CONS_BYTES_AOS_ATTR 0x1 +#define HWIO_IPA_ENDP_GSI_CONS_BYTES_AOS_IN \ + in_dword_masked(HWIO_IPA_ENDP_GSI_CONS_BYTES_AOS_ADDR, HWIO_IPA_ENDP_GSI_CONS_BYTES_AOS_RMSK) +#define HWIO_IPA_ENDP_GSI_CONS_BYTES_AOS_INM(m) \ + in_dword_masked(HWIO_IPA_ENDP_GSI_CONS_BYTES_AOS_ADDR, m) +#define HWIO_IPA_ENDP_GSI_CONS_BYTES_AOS_CONS_BYTES_BMSK 0xffff +#define HWIO_IPA_ENDP_GSI_CONS_BYTES_AOS_CONS_BYTES_SHFT 0x0 + +#define HWIO_IPA_LOG_BUF_HW_GEN_RAM_OFFSET_ADDR (IPA_DEBUG_REG_BASE + 0x000004f8) +#define HWIO_IPA_LOG_BUF_HW_GEN_RAM_OFFSET_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000004f8) +#define HWIO_IPA_LOG_BUF_HW_GEN_RAM_OFFSET_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000004f8) +#define HWIO_IPA_LOG_BUF_HW_GEN_RAM_OFFSET_RMSK 0x80f7ffff +#define HWIO_IPA_LOG_BUF_HW_GEN_RAM_OFFSET_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_GEN_RAM_OFFSET_IN \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_GEN_RAM_OFFSET_ADDR, HWIO_IPA_LOG_BUF_HW_GEN_RAM_OFFSET_RMSK) +#define HWIO_IPA_LOG_BUF_HW_GEN_RAM_OFFSET_INM(m) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_GEN_RAM_OFFSET_ADDR, m) +#define HWIO_IPA_LOG_BUF_HW_GEN_RAM_OFFSET_OUT(v) \ + out_dword(HWIO_IPA_LOG_BUF_HW_GEN_RAM_OFFSET_ADDR,v) +#define HWIO_IPA_LOG_BUF_HW_GEN_RAM_OFFSET_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_LOG_BUF_HW_GEN_RAM_OFFSET_ADDR,m,v,HWIO_IPA_LOG_BUF_HW_GEN_RAM_OFFSET_IN) +#define HWIO_IPA_LOG_BUF_HW_GEN_RAM_OFFSET_ENABLE_BMSK 0x80000000 +#define HWIO_IPA_LOG_BUF_HW_GEN_RAM_OFFSET_ENABLE_SHFT 0x1f +#define HWIO_IPA_LOG_BUF_HW_GEN_RAM_OFFSET_RAM_REGION_SIZE_BMSK 0xf00000 +#define HWIO_IPA_LOG_BUF_HW_GEN_RAM_OFFSET_RAM_REGION_SIZE_SHFT 0x14 +#define HWIO_IPA_LOG_BUF_HW_GEN_RAM_OFFSET_RAM_REGION_BADDR_BMSK 0x7ffff +#define HWIO_IPA_LOG_BUF_HW_GEN_RAM_OFFSET_RAM_REGION_BADDR_SHFT 0x0 + +#define HWIO_IPA_UC_RX_HND_CMDQ_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x00000538) +#define HWIO_IPA_UC_RX_HND_CMDQ_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000538) +#define HWIO_IPA_UC_RX_HND_CMDQ_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000538) +#define HWIO_IPA_UC_RX_HND_CMDQ_CMD_RMSK 0x7f +#define HWIO_IPA_UC_RX_HND_CMDQ_CMD_ATTR 0x2 +#define HWIO_IPA_UC_RX_HND_CMDQ_CMD_OUT(v) \ + out_dword(HWIO_IPA_UC_RX_HND_CMDQ_CMD_ADDR,v) +#define HWIO_IPA_UC_RX_HND_CMDQ_CMD_RELEASE_RD_PKT_ENHANCED_BMSK 0x40 +#define HWIO_IPA_UC_RX_HND_CMDQ_CMD_RELEASE_RD_PKT_ENHANCED_SHFT 0x6 +#define HWIO_IPA_UC_RX_HND_CMDQ_CMD_RELEASE_WR_PKT_BMSK 0x20 +#define HWIO_IPA_UC_RX_HND_CMDQ_CMD_RELEASE_WR_PKT_SHFT 0x5 +#define HWIO_IPA_UC_RX_HND_CMDQ_CMD_RELEASE_RD_PKT_BMSK 0x10 +#define HWIO_IPA_UC_RX_HND_CMDQ_CMD_RELEASE_RD_PKT_SHFT 0x4 +#define HWIO_IPA_UC_RX_HND_CMDQ_CMD_RELEASE_WR_CMD_BMSK 0x8 +#define HWIO_IPA_UC_RX_HND_CMDQ_CMD_RELEASE_WR_CMD_SHFT 0x3 +#define HWIO_IPA_UC_RX_HND_CMDQ_CMD_RELEASE_RD_CMD_BMSK 0x4 +#define HWIO_IPA_UC_RX_HND_CMDQ_CMD_RELEASE_RD_CMD_SHFT 0x2 +#define HWIO_IPA_UC_RX_HND_CMDQ_CMD_POP_CMD_BMSK 0x2 +#define HWIO_IPA_UC_RX_HND_CMDQ_CMD_POP_CMD_SHFT 0x1 +#define HWIO_IPA_UC_RX_HND_CMDQ_CMD_WRITE_CMD_BMSK 0x1 +#define HWIO_IPA_UC_RX_HND_CMDQ_CMD_WRITE_CMD_SHFT 0x0 + +#define HWIO_IPA_UC_RX_HND_CMDQ_CFG_ADDR (IPA_DEBUG_REG_BASE + 0x0000053c) +#define HWIO_IPA_UC_RX_HND_CMDQ_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000053c) +#define HWIO_IPA_UC_RX_HND_CMDQ_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000053c) +#define HWIO_IPA_UC_RX_HND_CMDQ_CFG_RMSK 0x3 +#define HWIO_IPA_UC_RX_HND_CMDQ_CFG_ATTR 0x3 +#define HWIO_IPA_UC_RX_HND_CMDQ_CFG_IN \ + in_dword_masked(HWIO_IPA_UC_RX_HND_CMDQ_CFG_ADDR, HWIO_IPA_UC_RX_HND_CMDQ_CFG_RMSK) +#define HWIO_IPA_UC_RX_HND_CMDQ_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_UC_RX_HND_CMDQ_CFG_ADDR, m) +#define HWIO_IPA_UC_RX_HND_CMDQ_CFG_OUT(v) \ + out_dword(HWIO_IPA_UC_RX_HND_CMDQ_CFG_ADDR,v) +#define HWIO_IPA_UC_RX_HND_CMDQ_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_RX_HND_CMDQ_CFG_ADDR,m,v,HWIO_IPA_UC_RX_HND_CMDQ_CFG_IN) +#define HWIO_IPA_UC_RX_HND_CMDQ_CFG_BLOCK_WR_BMSK 0x2 +#define HWIO_IPA_UC_RX_HND_CMDQ_CFG_BLOCK_WR_SHFT 0x1 +#define HWIO_IPA_UC_RX_HND_CMDQ_CFG_BLOCK_RD_BMSK 0x1 +#define HWIO_IPA_UC_RX_HND_CMDQ_CFG_BLOCK_RD_SHFT 0x0 + +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_0_ADDR (IPA_DEBUG_REG_BASE + 0x00000540) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000540) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000540) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_0_RMSK 0xffffffff +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_0_ATTR 0x3 +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_0_IN \ + in_dword_masked(HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_0_ADDR, HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_0_RMSK) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_0_INM(m) \ + in_dword_masked(HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_0_ADDR, m) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_0_OUT(v) \ + out_dword(HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_0_ADDR,v) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_0_ADDR,m,v,HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_0_IN) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_0_CMDQ_SRC_LEN_F_BMSK 0xffff0000 +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_0_CMDQ_SRC_LEN_F_SHFT 0x10 +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_0_CMDQ_PACKET_LEN_F_BMSK 0xffff +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_0_CMDQ_PACKET_LEN_F_SHFT 0x0 + +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_1_ADDR (IPA_DEBUG_REG_BASE + 0x00000544) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_1_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000544) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_1_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000544) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_1_RMSK 0xffffffff +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_1_ATTR 0x3 +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_1_IN \ + in_dword_masked(HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_1_ADDR, HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_1_RMSK) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_1_INM(m) \ + in_dword_masked(HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_1_ADDR, m) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_1_OUT(v) \ + out_dword(HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_1_ADDR,v) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_1_ADDR,m,v,HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_1_IN) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_1_CMDQ_METADATA_F_BMSK 0xff000000 +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_1_CMDQ_METADATA_F_SHFT 0x18 +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_1_CMDQ_OPCODE_F_BMSK 0xff0000 +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_1_CMDQ_OPCODE_F_SHFT 0x10 +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_1_CMDQ_FLAGS_F_BMSK 0xfc00 +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_1_CMDQ_FLAGS_F_SHFT 0xa +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_1_CMDQ_ORDER_F_BMSK 0x300 +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_1_CMDQ_ORDER_F_SHFT 0x8 +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_1_CMDQ_SRC_PIPE_F_BMSK 0xff +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_1_CMDQ_SRC_PIPE_F_SHFT 0x0 + +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_2_ADDR (IPA_DEBUG_REG_BASE + 0x00000548) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_2_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000548) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_2_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000548) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_2_RMSK 0xffffffff +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_2_ATTR 0x3 +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_2_IN \ + in_dword_masked(HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_2_ADDR, HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_2_RMSK) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_2_INM(m) \ + in_dword_masked(HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_2_ADDR, m) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_2_OUT(v) \ + out_dword(HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_2_ADDR,v) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_2_ADDR,m,v,HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_2_IN) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_2_CMDQ_ADDR_LSB_F_BMSK 0xfffffffe +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_2_CMDQ_ADDR_LSB_F_SHFT 0x1 +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_2_CMDQ_STATS_DISABLE_F_BMSK 0x1 +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_2_CMDQ_STATS_DISABLE_F_SHFT 0x0 + +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_3_ADDR (IPA_DEBUG_REG_BASE + 0x0000054c) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_3_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000054c) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_3_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000054c) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_3_RMSK 0xffffffff +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_3_ATTR 0x3 +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_3_IN \ + in_dword_masked(HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_3_ADDR, HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_3_RMSK) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_3_INM(m) \ + in_dword_masked(HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_3_ADDR, m) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_3_OUT(v) \ + out_dword(HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_3_ADDR,v) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_3_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_3_ADDR,m,v,HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_3_IN) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_3_CMDQ_ADDR_MSB_F_BMSK 0xffffffff +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_3_CMDQ_ADDR_MSB_F_SHFT 0x0 + +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_0_ADDR (IPA_DEBUG_REG_BASE + 0x00000550) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000550) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000550) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_0_RMSK 0xffffffff +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_0_ATTR 0x1 +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_0_IN \ + in_dword_masked(HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_0_ADDR, HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_0_RMSK) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_0_INM(m) \ + in_dword_masked(HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_0_ADDR, m) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_0_CMDQ_SRC_LEN_F_BMSK 0xffff0000 +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_0_CMDQ_SRC_LEN_F_SHFT 0x10 +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_0_CMDQ_PACKET_LEN_F_BMSK 0xffff +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_0_CMDQ_PACKET_LEN_F_SHFT 0x0 + +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_1_ADDR (IPA_DEBUG_REG_BASE + 0x00000554) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_1_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000554) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_1_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000554) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_1_RMSK 0xffffffff +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_1_ATTR 0x1 +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_1_IN \ + in_dword_masked(HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_1_ADDR, HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_1_RMSK) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_1_INM(m) \ + in_dword_masked(HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_1_ADDR, m) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_1_CMDQ_METADATA_F_BMSK 0xff000000 +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_1_CMDQ_METADATA_F_SHFT 0x18 +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_1_CMDQ_OPCODE_F_BMSK 0xff0000 +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_1_CMDQ_OPCODE_F_SHFT 0x10 +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_1_CMDQ_FLAGS_F_BMSK 0xfc00 +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_1_CMDQ_FLAGS_F_SHFT 0xa +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_1_CMDQ_ORDER_F_BMSK 0x300 +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_1_CMDQ_ORDER_F_SHFT 0x8 +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_1_CMDQ_SRC_PIPE_F_BMSK 0xff +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_1_CMDQ_SRC_PIPE_F_SHFT 0x0 + +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_2_ADDR (IPA_DEBUG_REG_BASE + 0x00000558) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_2_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000558) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_2_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000558) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_2_RMSK 0xffffffff +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_2_ATTR 0x1 +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_2_IN \ + in_dword_masked(HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_2_ADDR, HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_2_RMSK) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_2_INM(m) \ + in_dword_masked(HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_2_ADDR, m) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_2_CMDQ_ADDR_LSB_F_BMSK 0xfffffffe +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_2_CMDQ_ADDR_LSB_F_SHFT 0x1 +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_2_CMDQ_STATS_DISABLE_F_BMSK 0x1 +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_2_CMDQ_STATS_DISABLE_F_SHFT 0x0 + +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_3_ADDR (IPA_DEBUG_REG_BASE + 0x0000055c) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_3_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000055c) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_3_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000055c) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_3_RMSK 0xffffffff +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_3_ATTR 0x1 +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_3_IN \ + in_dword_masked(HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_3_ADDR, HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_3_RMSK) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_3_INM(m) \ + in_dword_masked(HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_3_ADDR, m) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_3_CMDQ_ADDR_MSB_F_BMSK 0xffffffff +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_3_CMDQ_ADDR_MSB_F_SHFT 0x0 + +#define HWIO_IPA_UC_RX_HND_CMDQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x00000560) +#define HWIO_IPA_UC_RX_HND_CMDQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000560) +#define HWIO_IPA_UC_RX_HND_CMDQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000560) +#define HWIO_IPA_UC_RX_HND_CMDQ_STATUS_RMSK 0x7ff +#define HWIO_IPA_UC_RX_HND_CMDQ_STATUS_ATTR 0x1 +#define HWIO_IPA_UC_RX_HND_CMDQ_STATUS_IN \ + in_dword_masked(HWIO_IPA_UC_RX_HND_CMDQ_STATUS_ADDR, HWIO_IPA_UC_RX_HND_CMDQ_STATUS_RMSK) +#define HWIO_IPA_UC_RX_HND_CMDQ_STATUS_INM(m) \ + in_dword_masked(HWIO_IPA_UC_RX_HND_CMDQ_STATUS_ADDR, m) +#define HWIO_IPA_UC_RX_HND_CMDQ_STATUS_CMDQ_DEPTH_BMSK 0x780 +#define HWIO_IPA_UC_RX_HND_CMDQ_STATUS_CMDQ_DEPTH_SHFT 0x7 +#define HWIO_IPA_UC_RX_HND_CMDQ_STATUS_CMDQ_COUNT_BMSK 0x78 +#define HWIO_IPA_UC_RX_HND_CMDQ_STATUS_CMDQ_COUNT_SHFT 0x3 +#define HWIO_IPA_UC_RX_HND_CMDQ_STATUS_CMDQ_FULL_BMSK 0x4 +#define HWIO_IPA_UC_RX_HND_CMDQ_STATUS_CMDQ_FULL_SHFT 0x2 +#define HWIO_IPA_UC_RX_HND_CMDQ_STATUS_CMDQ_EMPTY_BMSK 0x2 +#define HWIO_IPA_UC_RX_HND_CMDQ_STATUS_CMDQ_EMPTY_SHFT 0x1 +#define HWIO_IPA_UC_RX_HND_CMDQ_STATUS_STATUS_BMSK 0x1 +#define HWIO_IPA_UC_RX_HND_CMDQ_STATUS_STATUS_SHFT 0x0 + +#define HWIO_IPA_RAM_HW_FIRST_ADDR (IPA_DEBUG_REG_BASE + 0x00000564) +#define HWIO_IPA_RAM_HW_FIRST_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000564) +#define HWIO_IPA_RAM_HW_FIRST_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000564) +#define HWIO_IPA_RAM_HW_FIRST_RMSK 0xffffffff +#define HWIO_IPA_RAM_HW_FIRST_ATTR 0x1 +#define HWIO_IPA_RAM_HW_FIRST_IN \ + in_dword_masked(HWIO_IPA_RAM_HW_FIRST_ADDR, HWIO_IPA_RAM_HW_FIRST_RMSK) +#define HWIO_IPA_RAM_HW_FIRST_INM(m) \ + in_dword_masked(HWIO_IPA_RAM_HW_FIRST_ADDR, m) +#define HWIO_IPA_RAM_HW_FIRST_ADDRESS_BMSK 0xffffffff +#define HWIO_IPA_RAM_HW_FIRST_ADDRESS_SHFT 0x0 + +#define HWIO_IPA_RAM_HW_LAST_ADDR (IPA_DEBUG_REG_BASE + 0x00000568) +#define HWIO_IPA_RAM_HW_LAST_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000568) +#define HWIO_IPA_RAM_HW_LAST_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000568) +#define HWIO_IPA_RAM_HW_LAST_RMSK 0xffffffff +#define HWIO_IPA_RAM_HW_LAST_ATTR 0x1 +#define HWIO_IPA_RAM_HW_LAST_IN \ + in_dword_masked(HWIO_IPA_RAM_HW_LAST_ADDR, HWIO_IPA_RAM_HW_LAST_RMSK) +#define HWIO_IPA_RAM_HW_LAST_INM(m) \ + in_dword_masked(HWIO_IPA_RAM_HW_LAST_ADDR, m) +#define HWIO_IPA_RAM_HW_LAST_ADDRESS_BMSK 0xffffffff +#define HWIO_IPA_RAM_HW_LAST_ADDRESS_SHFT 0x0 + +#define HWIO_IPA_RAM_FRAG_FRST_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE + 0x00000570) +#define HWIO_IPA_RAM_FRAG_FRST_BASE_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000570) +#define HWIO_IPA_RAM_FRAG_FRST_BASE_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000570) +#define HWIO_IPA_RAM_FRAG_FRST_BASE_ADDR_RMSK 0xffffffff +#define HWIO_IPA_RAM_FRAG_FRST_BASE_ADDR_ATTR 0x1 +#define HWIO_IPA_RAM_FRAG_FRST_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_RAM_FRAG_FRST_BASE_ADDR_ADDR, HWIO_IPA_RAM_FRAG_FRST_BASE_ADDR_RMSK) +#define HWIO_IPA_RAM_FRAG_FRST_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_RAM_FRAG_FRST_BASE_ADDR_ADDR, m) +#define HWIO_IPA_RAM_FRAG_FRST_BASE_ADDR_ADDRESS_BMSK 0xffffffff +#define HWIO_IPA_RAM_FRAG_FRST_BASE_ADDR_ADDRESS_SHFT 0x0 + +#define HWIO_IPA_RAM_FRAG_SCND_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE + 0x00000574) +#define HWIO_IPA_RAM_FRAG_SCND_BASE_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000574) +#define HWIO_IPA_RAM_FRAG_SCND_BASE_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000574) +#define HWIO_IPA_RAM_FRAG_SCND_BASE_ADDR_RMSK 0xffffffff +#define HWIO_IPA_RAM_FRAG_SCND_BASE_ADDR_ATTR 0x1 +#define HWIO_IPA_RAM_FRAG_SCND_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_RAM_FRAG_SCND_BASE_ADDR_ADDR, HWIO_IPA_RAM_FRAG_SCND_BASE_ADDR_RMSK) +#define HWIO_IPA_RAM_FRAG_SCND_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_RAM_FRAG_SCND_BASE_ADDR_ADDR, m) +#define HWIO_IPA_RAM_FRAG_SCND_BASE_ADDR_ADDRESS_BMSK 0xffffffff +#define HWIO_IPA_RAM_FRAG_SCND_BASE_ADDR_ADDRESS_SHFT 0x0 + +#define HWIO_IPA_RAM_GSI_TLV_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE + 0x00000578) +#define HWIO_IPA_RAM_GSI_TLV_BASE_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000578) +#define HWIO_IPA_RAM_GSI_TLV_BASE_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000578) +#define HWIO_IPA_RAM_GSI_TLV_BASE_ADDR_RMSK 0xffffffff +#define HWIO_IPA_RAM_GSI_TLV_BASE_ADDR_ATTR 0x1 +#define HWIO_IPA_RAM_GSI_TLV_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_RAM_GSI_TLV_BASE_ADDR_ADDR, HWIO_IPA_RAM_GSI_TLV_BASE_ADDR_RMSK) +#define HWIO_IPA_RAM_GSI_TLV_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_RAM_GSI_TLV_BASE_ADDR_ADDR, m) +#define HWIO_IPA_RAM_GSI_TLV_BASE_ADDR_ADDRESS_BMSK 0xffffffff +#define HWIO_IPA_RAM_GSI_TLV_BASE_ADDR_ADDRESS_SHFT 0x0 + +#define HWIO_IPA_RAM_DCPH_KEYS_FIRST_ADDR (IPA_DEBUG_REG_BASE + 0x0000057c) +#define HWIO_IPA_RAM_DCPH_KEYS_FIRST_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000057c) +#define HWIO_IPA_RAM_DCPH_KEYS_FIRST_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000057c) +#define HWIO_IPA_RAM_DCPH_KEYS_FIRST_RMSK 0xffffffff +#define HWIO_IPA_RAM_DCPH_KEYS_FIRST_ATTR 0x1 +#define HWIO_IPA_RAM_DCPH_KEYS_FIRST_IN \ + in_dword_masked(HWIO_IPA_RAM_DCPH_KEYS_FIRST_ADDR, HWIO_IPA_RAM_DCPH_KEYS_FIRST_RMSK) +#define HWIO_IPA_RAM_DCPH_KEYS_FIRST_INM(m) \ + in_dword_masked(HWIO_IPA_RAM_DCPH_KEYS_FIRST_ADDR, m) +#define HWIO_IPA_RAM_DCPH_KEYS_FIRST_ADDRESS_BMSK 0xffffffff +#define HWIO_IPA_RAM_DCPH_KEYS_FIRST_ADDRESS_SHFT 0x0 + +#define HWIO_IPA_RAM_DCPH_KEYS_LAST_ADDR (IPA_DEBUG_REG_BASE + 0x00000580) +#define HWIO_IPA_RAM_DCPH_KEYS_LAST_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000580) +#define HWIO_IPA_RAM_DCPH_KEYS_LAST_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000580) +#define HWIO_IPA_RAM_DCPH_KEYS_LAST_RMSK 0xffffffff +#define HWIO_IPA_RAM_DCPH_KEYS_LAST_ATTR 0x1 +#define HWIO_IPA_RAM_DCPH_KEYS_LAST_IN \ + in_dword_masked(HWIO_IPA_RAM_DCPH_KEYS_LAST_ADDR, HWIO_IPA_RAM_DCPH_KEYS_LAST_RMSK) +#define HWIO_IPA_RAM_DCPH_KEYS_LAST_INM(m) \ + in_dword_masked(HWIO_IPA_RAM_DCPH_KEYS_LAST_ADDR, m) +#define HWIO_IPA_RAM_DCPH_KEYS_LAST_ADDRESS_BMSK 0xffffffff +#define HWIO_IPA_RAM_DCPH_KEYS_LAST_ADDRESS_SHFT 0x0 + +#define HWIO_IPA_DPS_SEQUENCER_FIRST_ADDR (IPA_DEBUG_REG_BASE + 0x00000584) +#define HWIO_IPA_DPS_SEQUENCER_FIRST_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000584) +#define HWIO_IPA_DPS_SEQUENCER_FIRST_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000584) +#define HWIO_IPA_DPS_SEQUENCER_FIRST_RMSK 0xffffffff +#define HWIO_IPA_DPS_SEQUENCER_FIRST_ATTR 0x1 +#define HWIO_IPA_DPS_SEQUENCER_FIRST_IN \ + in_dword_masked(HWIO_IPA_DPS_SEQUENCER_FIRST_ADDR, HWIO_IPA_DPS_SEQUENCER_FIRST_RMSK) +#define HWIO_IPA_DPS_SEQUENCER_FIRST_INM(m) \ + in_dword_masked(HWIO_IPA_DPS_SEQUENCER_FIRST_ADDR, m) +#define HWIO_IPA_DPS_SEQUENCER_FIRST_ADDRESS_BMSK 0xffffffff +#define HWIO_IPA_DPS_SEQUENCER_FIRST_ADDRESS_SHFT 0x0 + +#define HWIO_IPA_DPS_SEQUENCER_LAST_ADDR (IPA_DEBUG_REG_BASE + 0x00000588) +#define HWIO_IPA_DPS_SEQUENCER_LAST_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000588) +#define HWIO_IPA_DPS_SEQUENCER_LAST_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000588) +#define HWIO_IPA_DPS_SEQUENCER_LAST_RMSK 0xffffffff +#define HWIO_IPA_DPS_SEQUENCER_LAST_ATTR 0x1 +#define HWIO_IPA_DPS_SEQUENCER_LAST_IN \ + in_dword_masked(HWIO_IPA_DPS_SEQUENCER_LAST_ADDR, HWIO_IPA_DPS_SEQUENCER_LAST_RMSK) +#define HWIO_IPA_DPS_SEQUENCER_LAST_INM(m) \ + in_dword_masked(HWIO_IPA_DPS_SEQUENCER_LAST_ADDR, m) +#define HWIO_IPA_DPS_SEQUENCER_LAST_ADDRESS_BMSK 0xffffffff +#define HWIO_IPA_DPS_SEQUENCER_LAST_ADDRESS_SHFT 0x0 + +#define HWIO_IPA_HPS_SEQUENCER_FIRST_ADDR (IPA_DEBUG_REG_BASE + 0x0000058c) +#define HWIO_IPA_HPS_SEQUENCER_FIRST_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000058c) +#define HWIO_IPA_HPS_SEQUENCER_FIRST_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000058c) +#define HWIO_IPA_HPS_SEQUENCER_FIRST_RMSK 0xffffffff +#define HWIO_IPA_HPS_SEQUENCER_FIRST_ATTR 0x1 +#define HWIO_IPA_HPS_SEQUENCER_FIRST_IN \ + in_dword_masked(HWIO_IPA_HPS_SEQUENCER_FIRST_ADDR, HWIO_IPA_HPS_SEQUENCER_FIRST_RMSK) +#define HWIO_IPA_HPS_SEQUENCER_FIRST_INM(m) \ + in_dword_masked(HWIO_IPA_HPS_SEQUENCER_FIRST_ADDR, m) +#define HWIO_IPA_HPS_SEQUENCER_FIRST_ADDRESS_BMSK 0xffffffff +#define HWIO_IPA_HPS_SEQUENCER_FIRST_ADDRESS_SHFT 0x0 + +#define HWIO_IPA_HPS_SEQUENCER_LAST_ADDR (IPA_DEBUG_REG_BASE + 0x00000590) +#define HWIO_IPA_HPS_SEQUENCER_LAST_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000590) +#define HWIO_IPA_HPS_SEQUENCER_LAST_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000590) +#define HWIO_IPA_HPS_SEQUENCER_LAST_RMSK 0xffffffff +#define HWIO_IPA_HPS_SEQUENCER_LAST_ATTR 0x1 +#define HWIO_IPA_HPS_SEQUENCER_LAST_IN \ + in_dword_masked(HWIO_IPA_HPS_SEQUENCER_LAST_ADDR, HWIO_IPA_HPS_SEQUENCER_LAST_RMSK) +#define HWIO_IPA_HPS_SEQUENCER_LAST_INM(m) \ + in_dword_masked(HWIO_IPA_HPS_SEQUENCER_LAST_ADDR, m) +#define HWIO_IPA_HPS_SEQUENCER_LAST_ADDRESS_BMSK 0xffffffff +#define HWIO_IPA_HPS_SEQUENCER_LAST_ADDRESS_SHFT 0x0 + +#define HWIO_IPA_RAM_PKT_CTX_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE + 0x00000594) +#define HWIO_IPA_RAM_PKT_CTX_BASE_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000594) +#define HWIO_IPA_RAM_PKT_CTX_BASE_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000594) +#define HWIO_IPA_RAM_PKT_CTX_BASE_ADDR_RMSK 0xffffffff +#define HWIO_IPA_RAM_PKT_CTX_BASE_ADDR_ATTR 0x1 +#define HWIO_IPA_RAM_PKT_CTX_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_RAM_PKT_CTX_BASE_ADDR_ADDR, HWIO_IPA_RAM_PKT_CTX_BASE_ADDR_RMSK) +#define HWIO_IPA_RAM_PKT_CTX_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_RAM_PKT_CTX_BASE_ADDR_ADDR, m) +#define HWIO_IPA_RAM_PKT_CTX_BASE_ADDR_ADDRESS_BMSK 0xffffffff +#define HWIO_IPA_RAM_PKT_CTX_BASE_ADDR_ADDRESS_SHFT 0x0 + +#define HWIO_IPA_RAM_SW_AREA_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE + 0x00000598) +#define HWIO_IPA_RAM_SW_AREA_BASE_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000598) +#define HWIO_IPA_RAM_SW_AREA_BASE_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000598) +#define HWIO_IPA_RAM_SW_AREA_BASE_ADDR_RMSK 0xffffffff +#define HWIO_IPA_RAM_SW_AREA_BASE_ADDR_ATTR 0x1 +#define HWIO_IPA_RAM_SW_AREA_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_RAM_SW_AREA_BASE_ADDR_ADDR, HWIO_IPA_RAM_SW_AREA_BASE_ADDR_RMSK) +#define HWIO_IPA_RAM_SW_AREA_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_RAM_SW_AREA_BASE_ADDR_ADDR, m) +#define HWIO_IPA_RAM_SW_AREA_BASE_ADDR_ADDRESS_BMSK 0xffffffff +#define HWIO_IPA_RAM_SW_AREA_BASE_ADDR_ADDRESS_SHFT 0x0 + +#define HWIO_IPA_RAM_HDRI_TYPE1_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE + 0x0000059c) +#define HWIO_IPA_RAM_HDRI_TYPE1_BASE_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000059c) +#define HWIO_IPA_RAM_HDRI_TYPE1_BASE_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000059c) +#define HWIO_IPA_RAM_HDRI_TYPE1_BASE_ADDR_RMSK 0xffffffff +#define HWIO_IPA_RAM_HDRI_TYPE1_BASE_ADDR_ATTR 0x1 +#define HWIO_IPA_RAM_HDRI_TYPE1_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_RAM_HDRI_TYPE1_BASE_ADDR_ADDR, HWIO_IPA_RAM_HDRI_TYPE1_BASE_ADDR_RMSK) +#define HWIO_IPA_RAM_HDRI_TYPE1_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_RAM_HDRI_TYPE1_BASE_ADDR_ADDR, m) +#define HWIO_IPA_RAM_HDRI_TYPE1_BASE_ADDR_ADDRESS_BMSK 0xffffffff +#define HWIO_IPA_RAM_HDRI_TYPE1_BASE_ADDR_ADDRESS_SHFT 0x0 + +#define HWIO_IPA_RAM_AGGR_NLO_COUNTERS_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE + 0x000005a0) +#define HWIO_IPA_RAM_AGGR_NLO_COUNTERS_BASE_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000005a0) +#define HWIO_IPA_RAM_AGGR_NLO_COUNTERS_BASE_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000005a0) +#define HWIO_IPA_RAM_AGGR_NLO_COUNTERS_BASE_ADDR_RMSK 0xffffffff +#define HWIO_IPA_RAM_AGGR_NLO_COUNTERS_BASE_ADDR_ATTR 0x1 +#define HWIO_IPA_RAM_AGGR_NLO_COUNTERS_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_RAM_AGGR_NLO_COUNTERS_BASE_ADDR_ADDR, HWIO_IPA_RAM_AGGR_NLO_COUNTERS_BASE_ADDR_RMSK) +#define HWIO_IPA_RAM_AGGR_NLO_COUNTERS_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_RAM_AGGR_NLO_COUNTERS_BASE_ADDR_ADDR, m) +#define HWIO_IPA_RAM_AGGR_NLO_COUNTERS_BASE_ADDR_ADDRESS_BMSK 0xffffffff +#define HWIO_IPA_RAM_AGGR_NLO_COUNTERS_BASE_ADDR_ADDRESS_SHFT 0x0 + +#define HWIO_IPA_RAM_NLO_VP_CACHE_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE + 0x000005a4) +#define HWIO_IPA_RAM_NLO_VP_CACHE_BASE_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000005a4) +#define HWIO_IPA_RAM_NLO_VP_CACHE_BASE_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000005a4) +#define HWIO_IPA_RAM_NLO_VP_CACHE_BASE_ADDR_RMSK 0xffffffff +#define HWIO_IPA_RAM_NLO_VP_CACHE_BASE_ADDR_ATTR 0x1 +#define HWIO_IPA_RAM_NLO_VP_CACHE_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_RAM_NLO_VP_CACHE_BASE_ADDR_ADDR, HWIO_IPA_RAM_NLO_VP_CACHE_BASE_ADDR_RMSK) +#define HWIO_IPA_RAM_NLO_VP_CACHE_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_RAM_NLO_VP_CACHE_BASE_ADDR_ADDR, m) +#define HWIO_IPA_RAM_NLO_VP_CACHE_BASE_ADDR_ADDRESS_BMSK 0xffffffff +#define HWIO_IPA_RAM_NLO_VP_CACHE_BASE_ADDR_ADDRESS_SHFT 0x0 + +#define HWIO_IPA_RAM_COAL_VP_CACHE_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE + 0x000005a8) +#define HWIO_IPA_RAM_COAL_VP_CACHE_BASE_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000005a8) +#define HWIO_IPA_RAM_COAL_VP_CACHE_BASE_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000005a8) +#define HWIO_IPA_RAM_COAL_VP_CACHE_BASE_ADDR_RMSK 0xffffffff +#define HWIO_IPA_RAM_COAL_VP_CACHE_BASE_ADDR_ATTR 0x1 +#define HWIO_IPA_RAM_COAL_VP_CACHE_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_RAM_COAL_VP_CACHE_BASE_ADDR_ADDR, HWIO_IPA_RAM_COAL_VP_CACHE_BASE_ADDR_RMSK) +#define HWIO_IPA_RAM_COAL_VP_CACHE_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_RAM_COAL_VP_CACHE_BASE_ADDR_ADDR, m) +#define HWIO_IPA_RAM_COAL_VP_CACHE_BASE_ADDR_ADDRESS_BMSK 0xffffffff +#define HWIO_IPA_RAM_COAL_VP_CACHE_BASE_ADDR_ADDRESS_SHFT 0x0 + +#define HWIO_IPA_RAM_COAL_VP_FIFO_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE + 0x000005ac) +#define HWIO_IPA_RAM_COAL_VP_FIFO_BASE_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000005ac) +#define HWIO_IPA_RAM_COAL_VP_FIFO_BASE_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000005ac) +#define HWIO_IPA_RAM_COAL_VP_FIFO_BASE_ADDR_RMSK 0xffffffff +#define HWIO_IPA_RAM_COAL_VP_FIFO_BASE_ADDR_ATTR 0x1 +#define HWIO_IPA_RAM_COAL_VP_FIFO_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_RAM_COAL_VP_FIFO_BASE_ADDR_ADDR, HWIO_IPA_RAM_COAL_VP_FIFO_BASE_ADDR_RMSK) +#define HWIO_IPA_RAM_COAL_VP_FIFO_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_RAM_COAL_VP_FIFO_BASE_ADDR_ADDR, m) +#define HWIO_IPA_RAM_COAL_VP_FIFO_BASE_ADDR_ADDRESS_BMSK 0xffffffff +#define HWIO_IPA_RAM_COAL_VP_FIFO_BASE_ADDR_ADDRESS_SHFT 0x0 + +#define HWIO_IPA_RAM_AGGR_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE + 0x000005b4) +#define HWIO_IPA_RAM_AGGR_BASE_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000005b4) +#define HWIO_IPA_RAM_AGGR_BASE_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000005b4) +#define HWIO_IPA_RAM_AGGR_BASE_ADDR_RMSK 0xffffffff +#define HWIO_IPA_RAM_AGGR_BASE_ADDR_ATTR 0x1 +#define HWIO_IPA_RAM_AGGR_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_RAM_AGGR_BASE_ADDR_ADDR, HWIO_IPA_RAM_AGGR_BASE_ADDR_RMSK) +#define HWIO_IPA_RAM_AGGR_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_RAM_AGGR_BASE_ADDR_ADDR, m) +#define HWIO_IPA_RAM_AGGR_BASE_ADDR_ADDRESS_BMSK 0xffffffff +#define HWIO_IPA_RAM_AGGR_BASE_ADDR_ADDRESS_SHFT 0x0 + +#define HWIO_IPA_RAM_TX_COUNTERS_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE + 0x000005b8) +#define HWIO_IPA_RAM_TX_COUNTERS_BASE_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000005b8) +#define HWIO_IPA_RAM_TX_COUNTERS_BASE_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000005b8) +#define HWIO_IPA_RAM_TX_COUNTERS_BASE_ADDR_RMSK 0xffffffff +#define HWIO_IPA_RAM_TX_COUNTERS_BASE_ADDR_ATTR 0x1 +#define HWIO_IPA_RAM_TX_COUNTERS_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_RAM_TX_COUNTERS_BASE_ADDR_ADDR, HWIO_IPA_RAM_TX_COUNTERS_BASE_ADDR_RMSK) +#define HWIO_IPA_RAM_TX_COUNTERS_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_RAM_TX_COUNTERS_BASE_ADDR_ADDR, m) +#define HWIO_IPA_RAM_TX_COUNTERS_BASE_ADDR_ADDRESS_BMSK 0xffffffff +#define HWIO_IPA_RAM_TX_COUNTERS_BASE_ADDR_ADDRESS_SHFT 0x0 + +#define HWIO_IPA_RAM_CONS_DPL_FIFO_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE + 0x000005bc) +#define HWIO_IPA_RAM_CONS_DPL_FIFO_BASE_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000005bc) +#define HWIO_IPA_RAM_CONS_DPL_FIFO_BASE_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000005bc) +#define HWIO_IPA_RAM_CONS_DPL_FIFO_BASE_ADDR_RMSK 0xffffffff +#define HWIO_IPA_RAM_CONS_DPL_FIFO_BASE_ADDR_ATTR 0x1 +#define HWIO_IPA_RAM_CONS_DPL_FIFO_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_RAM_CONS_DPL_FIFO_BASE_ADDR_ADDR, HWIO_IPA_RAM_CONS_DPL_FIFO_BASE_ADDR_RMSK) +#define HWIO_IPA_RAM_CONS_DPL_FIFO_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_RAM_CONS_DPL_FIFO_BASE_ADDR_ADDR, m) +#define HWIO_IPA_RAM_CONS_DPL_FIFO_BASE_ADDR_ADDRESS_BMSK 0xffffffff +#define HWIO_IPA_RAM_CONS_DPL_FIFO_BASE_ADDR_ADDRESS_SHFT 0x0 + +#define HWIO_IPA_RAM_COAL_MASTER_VP_CTX_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE + 0x000005c0) +#define HWIO_IPA_RAM_COAL_MASTER_VP_CTX_BASE_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000005c0) +#define HWIO_IPA_RAM_COAL_MASTER_VP_CTX_BASE_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000005c0) +#define HWIO_IPA_RAM_COAL_MASTER_VP_CTX_BASE_ADDR_RMSK 0xffffffff +#define HWIO_IPA_RAM_COAL_MASTER_VP_CTX_BASE_ADDR_ATTR 0x1 +#define HWIO_IPA_RAM_COAL_MASTER_VP_CTX_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_RAM_COAL_MASTER_VP_CTX_BASE_ADDR_ADDR, HWIO_IPA_RAM_COAL_MASTER_VP_CTX_BASE_ADDR_RMSK) +#define HWIO_IPA_RAM_COAL_MASTER_VP_CTX_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_RAM_COAL_MASTER_VP_CTX_BASE_ADDR_ADDR, m) +#define HWIO_IPA_RAM_COAL_MASTER_VP_CTX_BASE_ADDR_ADDRESS_BMSK 0xffffffff +#define HWIO_IPA_RAM_COAL_MASTER_VP_CTX_BASE_ADDR_ADDRESS_SHFT 0x0 + +#define HWIO_IPA_RAM_COAL_MASTER_VP_AGGR_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE + 0x000005c4) +#define HWIO_IPA_RAM_COAL_MASTER_VP_AGGR_BASE_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000005c4) +#define HWIO_IPA_RAM_COAL_MASTER_VP_AGGR_BASE_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000005c4) +#define HWIO_IPA_RAM_COAL_MASTER_VP_AGGR_BASE_ADDR_RMSK 0xffffffff +#define HWIO_IPA_RAM_COAL_MASTER_VP_AGGR_BASE_ADDR_ATTR 0x1 +#define HWIO_IPA_RAM_COAL_MASTER_VP_AGGR_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_RAM_COAL_MASTER_VP_AGGR_BASE_ADDR_ADDR, HWIO_IPA_RAM_COAL_MASTER_VP_AGGR_BASE_ADDR_RMSK) +#define HWIO_IPA_RAM_COAL_MASTER_VP_AGGR_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_RAM_COAL_MASTER_VP_AGGR_BASE_ADDR_ADDR, m) +#define HWIO_IPA_RAM_COAL_MASTER_VP_AGGR_BASE_ADDR_ADDRESS_BMSK 0xffffffff +#define HWIO_IPA_RAM_COAL_MASTER_VP_AGGR_BASE_ADDR_ADDRESS_SHFT 0x0 + +#define HWIO_IPA_RAM_COAL_SLAVE_VP_CTX_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE + 0x000005c8) +#define HWIO_IPA_RAM_COAL_SLAVE_VP_CTX_BASE_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000005c8) +#define HWIO_IPA_RAM_COAL_SLAVE_VP_CTX_BASE_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000005c8) +#define HWIO_IPA_RAM_COAL_SLAVE_VP_CTX_BASE_ADDR_RMSK 0xffffffff +#define HWIO_IPA_RAM_COAL_SLAVE_VP_CTX_BASE_ADDR_ATTR 0x1 +#define HWIO_IPA_RAM_COAL_SLAVE_VP_CTX_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_RAM_COAL_SLAVE_VP_CTX_BASE_ADDR_ADDR, HWIO_IPA_RAM_COAL_SLAVE_VP_CTX_BASE_ADDR_RMSK) +#define HWIO_IPA_RAM_COAL_SLAVE_VP_CTX_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_RAM_COAL_SLAVE_VP_CTX_BASE_ADDR_ADDR, m) +#define HWIO_IPA_RAM_COAL_SLAVE_VP_CTX_BASE_ADDR_ADDRESS_BMSK 0xffffffff +#define HWIO_IPA_RAM_COAL_SLAVE_VP_CTX_BASE_ADDR_ADDRESS_SHFT 0x0 + +#define HWIO_IPA_RAM_UL_NLO_AGGR_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE + 0x000005cc) +#define HWIO_IPA_RAM_UL_NLO_AGGR_BASE_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000005cc) +#define HWIO_IPA_RAM_UL_NLO_AGGR_BASE_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000005cc) +#define HWIO_IPA_RAM_UL_NLO_AGGR_BASE_ADDR_RMSK 0xffffffff +#define HWIO_IPA_RAM_UL_NLO_AGGR_BASE_ADDR_ATTR 0x1 +#define HWIO_IPA_RAM_UL_NLO_AGGR_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_RAM_UL_NLO_AGGR_BASE_ADDR_ADDR, HWIO_IPA_RAM_UL_NLO_AGGR_BASE_ADDR_RMSK) +#define HWIO_IPA_RAM_UL_NLO_AGGR_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_RAM_UL_NLO_AGGR_BASE_ADDR_ADDR, m) +#define HWIO_IPA_RAM_UL_NLO_AGGR_BASE_ADDR_ADDRESS_BMSK 0xffffffff +#define HWIO_IPA_RAM_UL_NLO_AGGR_BASE_ADDR_ADDRESS_SHFT 0x0 + +#define HWIO_IPA_RAM_UC_IRAM_ADDR_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE + 0x000005d0) +#define HWIO_IPA_RAM_UC_IRAM_ADDR_BASE_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000005d0) +#define HWIO_IPA_RAM_UC_IRAM_ADDR_BASE_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000005d0) +#define HWIO_IPA_RAM_UC_IRAM_ADDR_BASE_ADDR_RMSK 0xffffffff +#define HWIO_IPA_RAM_UC_IRAM_ADDR_BASE_ADDR_ATTR 0x1 +#define HWIO_IPA_RAM_UC_IRAM_ADDR_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_RAM_UC_IRAM_ADDR_BASE_ADDR_ADDR, HWIO_IPA_RAM_UC_IRAM_ADDR_BASE_ADDR_RMSK) +#define HWIO_IPA_RAM_UC_IRAM_ADDR_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_RAM_UC_IRAM_ADDR_BASE_ADDR_ADDR, m) +#define HWIO_IPA_RAM_UC_IRAM_ADDR_BASE_ADDR_ADDRESS_BMSK 0xffffffff +#define HWIO_IPA_RAM_UC_IRAM_ADDR_BASE_ADDR_ADDRESS_SHFT 0x0 + +#define HWIO_IPA_RAM_SNIFFER_HW_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE + 0x000005d4) +#define HWIO_IPA_RAM_SNIFFER_HW_BASE_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000005d4) +#define HWIO_IPA_RAM_SNIFFER_HW_BASE_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000005d4) +#define HWIO_IPA_RAM_SNIFFER_HW_BASE_ADDR_RMSK 0xffffffff +#define HWIO_IPA_RAM_SNIFFER_HW_BASE_ADDR_ATTR 0x1 +#define HWIO_IPA_RAM_SNIFFER_HW_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_RAM_SNIFFER_HW_BASE_ADDR_ADDR, HWIO_IPA_RAM_SNIFFER_HW_BASE_ADDR_RMSK) +#define HWIO_IPA_RAM_SNIFFER_HW_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_RAM_SNIFFER_HW_BASE_ADDR_ADDR, m) +#define HWIO_IPA_RAM_SNIFFER_HW_BASE_ADDR_ADDRESS_BMSK 0xffffffff +#define HWIO_IPA_RAM_SNIFFER_HW_BASE_ADDR_ADDRESS_SHFT 0x0 + +#define HWIO_IPA_RAM_FILTER_ROUTER_CACHE_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE + 0x000005d8) +#define HWIO_IPA_RAM_FILTER_ROUTER_CACHE_BASE_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000005d8) +#define HWIO_IPA_RAM_FILTER_ROUTER_CACHE_BASE_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000005d8) +#define HWIO_IPA_RAM_FILTER_ROUTER_CACHE_BASE_ADDR_RMSK 0xffffffff +#define HWIO_IPA_RAM_FILTER_ROUTER_CACHE_BASE_ADDR_ATTR 0x1 +#define HWIO_IPA_RAM_FILTER_ROUTER_CACHE_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_RAM_FILTER_ROUTER_CACHE_BASE_ADDR_ADDR, HWIO_IPA_RAM_FILTER_ROUTER_CACHE_BASE_ADDR_RMSK) +#define HWIO_IPA_RAM_FILTER_ROUTER_CACHE_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_RAM_FILTER_ROUTER_CACHE_BASE_ADDR_ADDR, m) +#define HWIO_IPA_RAM_FILTER_ROUTER_CACHE_BASE_ADDR_ADDRESS_BMSK 0xffffffff +#define HWIO_IPA_RAM_FILTER_ROUTER_CACHE_BASE_ADDR_ADDRESS_SHFT 0x0 + +#define HWIO_IPA_RAM_INGRESS_POLICER_DB_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE + 0x000005dc) +#define HWIO_IPA_RAM_INGRESS_POLICER_DB_BASE_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000005dc) +#define HWIO_IPA_RAM_INGRESS_POLICER_DB_BASE_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000005dc) +#define HWIO_IPA_RAM_INGRESS_POLICER_DB_BASE_ADDR_RMSK 0xffffffff +#define HWIO_IPA_RAM_INGRESS_POLICER_DB_BASE_ADDR_ATTR 0x1 +#define HWIO_IPA_RAM_INGRESS_POLICER_DB_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_RAM_INGRESS_POLICER_DB_BASE_ADDR_ADDR, HWIO_IPA_RAM_INGRESS_POLICER_DB_BASE_ADDR_RMSK) +#define HWIO_IPA_RAM_INGRESS_POLICER_DB_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_RAM_INGRESS_POLICER_DB_BASE_ADDR_ADDR, m) +#define HWIO_IPA_RAM_INGRESS_POLICER_DB_BASE_ADDR_ADDRESS_BMSK 0xffffffff +#define HWIO_IPA_RAM_INGRESS_POLICER_DB_BASE_ADDR_ADDRESS_SHFT 0x0 + +#define HWIO_IPA_RAM_EGRESS_SHAPING_PROD_DB_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE + 0x000005e0) +#define HWIO_IPA_RAM_EGRESS_SHAPING_PROD_DB_BASE_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000005e0) +#define HWIO_IPA_RAM_EGRESS_SHAPING_PROD_DB_BASE_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000005e0) +#define HWIO_IPA_RAM_EGRESS_SHAPING_PROD_DB_BASE_ADDR_RMSK 0xffffffff +#define HWIO_IPA_RAM_EGRESS_SHAPING_PROD_DB_BASE_ADDR_ATTR 0x1 +#define HWIO_IPA_RAM_EGRESS_SHAPING_PROD_DB_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_RAM_EGRESS_SHAPING_PROD_DB_BASE_ADDR_ADDR, HWIO_IPA_RAM_EGRESS_SHAPING_PROD_DB_BASE_ADDR_RMSK) +#define HWIO_IPA_RAM_EGRESS_SHAPING_PROD_DB_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_RAM_EGRESS_SHAPING_PROD_DB_BASE_ADDR_ADDR, m) +#define HWIO_IPA_RAM_EGRESS_SHAPING_PROD_DB_BASE_ADDR_ADDRESS_BMSK 0xffffffff +#define HWIO_IPA_RAM_EGRESS_SHAPING_PROD_DB_BASE_ADDR_ADDRESS_SHFT 0x0 + +#define HWIO_IPA_RAM_EGRESS_SHAPING_TC_DB_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE + 0x000005e4) +#define HWIO_IPA_RAM_EGRESS_SHAPING_TC_DB_BASE_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000005e4) +#define HWIO_IPA_RAM_EGRESS_SHAPING_TC_DB_BASE_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000005e4) +#define HWIO_IPA_RAM_EGRESS_SHAPING_TC_DB_BASE_ADDR_RMSK 0xffffffff +#define HWIO_IPA_RAM_EGRESS_SHAPING_TC_DB_BASE_ADDR_ATTR 0x1 +#define HWIO_IPA_RAM_EGRESS_SHAPING_TC_DB_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_RAM_EGRESS_SHAPING_TC_DB_BASE_ADDR_ADDR, HWIO_IPA_RAM_EGRESS_SHAPING_TC_DB_BASE_ADDR_RMSK) +#define HWIO_IPA_RAM_EGRESS_SHAPING_TC_DB_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_RAM_EGRESS_SHAPING_TC_DB_BASE_ADDR_ADDR, m) +#define HWIO_IPA_RAM_EGRESS_SHAPING_TC_DB_BASE_ADDR_ADDRESS_BMSK 0xffffffff +#define HWIO_IPA_RAM_EGRESS_SHAPING_TC_DB_BASE_ADDR_ADDRESS_SHFT 0x0 + +#define HWIO_IPA_SPARE_REG_1_ADDR (IPA_DEBUG_REG_BASE + 0x00000600) +#define HWIO_IPA_SPARE_REG_1_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000600) +#define HWIO_IPA_SPARE_REG_1_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000600) +#define HWIO_IPA_SPARE_REG_1_RMSK 0xffff +#define HWIO_IPA_SPARE_REG_1_ATTR 0x3 +#define HWIO_IPA_SPARE_REG_1_IN \ + in_dword_masked(HWIO_IPA_SPARE_REG_1_ADDR, HWIO_IPA_SPARE_REG_1_RMSK) +#define HWIO_IPA_SPARE_REG_1_INM(m) \ + in_dword_masked(HWIO_IPA_SPARE_REG_1_ADDR, m) +#define HWIO_IPA_SPARE_REG_1_OUT(v) \ + out_dword(HWIO_IPA_SPARE_REG_1_ADDR,v) +#define HWIO_IPA_SPARE_REG_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_SPARE_REG_1_ADDR,m,v,HWIO_IPA_SPARE_REG_1_IN) +#define HWIO_IPA_SPARE_REG_1_SPARE_BITS_BMSK 0xffff +#define HWIO_IPA_SPARE_REG_1_SPARE_BITS_SHFT 0x0 + +#define HWIO_IPA_HPS_UC2SEQ_PUSH_ADDR (IPA_DEBUG_REG_BASE + 0x00000604) +#define HWIO_IPA_HPS_UC2SEQ_PUSH_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000604) +#define HWIO_IPA_HPS_UC2SEQ_PUSH_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000604) +#define HWIO_IPA_HPS_UC2SEQ_PUSH_RMSK 0xc03fffff +#define HWIO_IPA_HPS_UC2SEQ_PUSH_ATTR 0x2 +#define HWIO_IPA_HPS_UC2SEQ_PUSH_OUT(v) \ + out_dword(HWIO_IPA_HPS_UC2SEQ_PUSH_ADDR,v) +#define HWIO_IPA_HPS_UC2SEQ_PUSH_TYPE_BMSK 0x80000000 +#define HWIO_IPA_HPS_UC2SEQ_PUSH_TYPE_SHFT 0x1f +#define HWIO_IPA_HPS_UC2SEQ_PUSH_VIRT_OPCODE_BMSK 0x40000000 +#define HWIO_IPA_HPS_UC2SEQ_PUSH_VIRT_OPCODE_SHFT 0x1e +#define HWIO_IPA_HPS_UC2SEQ_PUSH_CTX_ID_BMSK 0x3c0000 +#define HWIO_IPA_HPS_UC2SEQ_PUSH_CTX_ID_SHFT 0x12 +#define HWIO_IPA_HPS_UC2SEQ_PUSH_SRC_ID_BMSK 0x3fc00 +#define HWIO_IPA_HPS_UC2SEQ_PUSH_SRC_ID_SHFT 0xa +#define HWIO_IPA_HPS_UC2SEQ_PUSH_SRC_FLAGS_BMSK 0x300 +#define HWIO_IPA_HPS_UC2SEQ_PUSH_SRC_FLAGS_SHFT 0x8 +#define HWIO_IPA_HPS_UC2SEQ_PUSH_SRC_PIPE_BMSK 0xff +#define HWIO_IPA_HPS_UC2SEQ_PUSH_SRC_PIPE_SHFT 0x0 + +#define HWIO_IPA_HPS_UC2SEQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x00000608) +#define HWIO_IPA_HPS_UC2SEQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000608) +#define HWIO_IPA_HPS_UC2SEQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000608) +#define HWIO_IPA_HPS_UC2SEQ_STATUS_RMSK 0xf +#define HWIO_IPA_HPS_UC2SEQ_STATUS_ATTR 0x1 +#define HWIO_IPA_HPS_UC2SEQ_STATUS_IN \ + in_dword_masked(HWIO_IPA_HPS_UC2SEQ_STATUS_ADDR, HWIO_IPA_HPS_UC2SEQ_STATUS_RMSK) +#define HWIO_IPA_HPS_UC2SEQ_STATUS_INM(m) \ + in_dword_masked(HWIO_IPA_HPS_UC2SEQ_STATUS_ADDR, m) +#define HWIO_IPA_HPS_UC2SEQ_STATUS_FILL_LEVEL_BMSK 0xf +#define HWIO_IPA_HPS_UC2SEQ_STATUS_FILL_LEVEL_SHFT 0x0 + +#define HWIO_IPA_HPS_SEQ2UC_RD_ADDR (IPA_DEBUG_REG_BASE + 0x0000060c) +#define HWIO_IPA_HPS_SEQ2UC_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000060c) +#define HWIO_IPA_HPS_SEQ2UC_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000060c) +#define HWIO_IPA_HPS_SEQ2UC_RD_RMSK 0x803fffff +#define HWIO_IPA_HPS_SEQ2UC_RD_ATTR 0x1 +#define HWIO_IPA_HPS_SEQ2UC_RD_IN \ + in_dword_masked(HWIO_IPA_HPS_SEQ2UC_RD_ADDR, HWIO_IPA_HPS_SEQ2UC_RD_RMSK) +#define HWIO_IPA_HPS_SEQ2UC_RD_INM(m) \ + in_dword_masked(HWIO_IPA_HPS_SEQ2UC_RD_ADDR, m) +#define HWIO_IPA_HPS_SEQ2UC_RD_TYPE_BMSK 0x80000000 +#define HWIO_IPA_HPS_SEQ2UC_RD_TYPE_SHFT 0x1f +#define HWIO_IPA_HPS_SEQ2UC_RD_CTX_ID_BMSK 0x3c0000 +#define HWIO_IPA_HPS_SEQ2UC_RD_CTX_ID_SHFT 0x12 +#define HWIO_IPA_HPS_SEQ2UC_RD_SRC_ID_BMSK 0x3fc00 +#define HWIO_IPA_HPS_SEQ2UC_RD_SRC_ID_SHFT 0xa +#define HWIO_IPA_HPS_SEQ2UC_RD_SRC_FLAGS_BMSK 0x300 +#define HWIO_IPA_HPS_SEQ2UC_RD_SRC_FLAGS_SHFT 0x8 +#define HWIO_IPA_HPS_SEQ2UC_RD_SRC_PIPE_BMSK 0xff +#define HWIO_IPA_HPS_SEQ2UC_RD_SRC_PIPE_SHFT 0x0 + +#define HWIO_IPA_HPS_SEQ2UC_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x00000610) +#define HWIO_IPA_HPS_SEQ2UC_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000610) +#define HWIO_IPA_HPS_SEQ2UC_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000610) +#define HWIO_IPA_HPS_SEQ2UC_STATUS_RMSK 0xf +#define HWIO_IPA_HPS_SEQ2UC_STATUS_ATTR 0x1 +#define HWIO_IPA_HPS_SEQ2UC_STATUS_IN \ + in_dword_masked(HWIO_IPA_HPS_SEQ2UC_STATUS_ADDR, HWIO_IPA_HPS_SEQ2UC_STATUS_RMSK) +#define HWIO_IPA_HPS_SEQ2UC_STATUS_INM(m) \ + in_dword_masked(HWIO_IPA_HPS_SEQ2UC_STATUS_ADDR, m) +#define HWIO_IPA_HPS_SEQ2UC_STATUS_FILL_LEVEL_BMSK 0xf +#define HWIO_IPA_HPS_SEQ2UC_STATUS_FILL_LEVEL_SHFT 0x0 + +#define HWIO_IPA_HPS_SEQ2UC_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x00000614) +#define HWIO_IPA_HPS_SEQ2UC_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000614) +#define HWIO_IPA_HPS_SEQ2UC_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000614) +#define HWIO_IPA_HPS_SEQ2UC_CMD_RMSK 0x1 +#define HWIO_IPA_HPS_SEQ2UC_CMD_ATTR 0x2 +#define HWIO_IPA_HPS_SEQ2UC_CMD_OUT(v) \ + out_dword(HWIO_IPA_HPS_SEQ2UC_CMD_ADDR,v) +#define HWIO_IPA_HPS_SEQ2UC_CMD_POP_BMSK 0x1 +#define HWIO_IPA_HPS_SEQ2UC_CMD_POP_SHFT 0x0 + +#define HWIO_IPA_DPS_UC2SEQ_PUSH_ADDR (IPA_DEBUG_REG_BASE + 0x00000618) +#define HWIO_IPA_DPS_UC2SEQ_PUSH_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000618) +#define HWIO_IPA_DPS_UC2SEQ_PUSH_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000618) +#define HWIO_IPA_DPS_UC2SEQ_PUSH_RMSK 0xbfffffff +#define HWIO_IPA_DPS_UC2SEQ_PUSH_ATTR 0x2 +#define HWIO_IPA_DPS_UC2SEQ_PUSH_OUT(v) \ + out_dword(HWIO_IPA_DPS_UC2SEQ_PUSH_ADDR,v) +#define HWIO_IPA_DPS_UC2SEQ_PUSH_TYPE_BMSK 0x80000000 +#define HWIO_IPA_DPS_UC2SEQ_PUSH_TYPE_SHFT 0x1f +#define HWIO_IPA_DPS_UC2SEQ_PUSH_DEST_PIPE_BMSK 0x3fc00000 +#define HWIO_IPA_DPS_UC2SEQ_PUSH_DEST_PIPE_SHFT 0x16 +#define HWIO_IPA_DPS_UC2SEQ_PUSH_CTX_ID_BMSK 0x3c0000 +#define HWIO_IPA_DPS_UC2SEQ_PUSH_CTX_ID_SHFT 0x12 +#define HWIO_IPA_DPS_UC2SEQ_PUSH_SRC_ID_BMSK 0x3fc00 +#define HWIO_IPA_DPS_UC2SEQ_PUSH_SRC_ID_SHFT 0xa +#define HWIO_IPA_DPS_UC2SEQ_PUSH_SRC_FLAGS_BMSK 0x300 +#define HWIO_IPA_DPS_UC2SEQ_PUSH_SRC_FLAGS_SHFT 0x8 +#define HWIO_IPA_DPS_UC2SEQ_PUSH_SRC_PIPE_BMSK 0xff +#define HWIO_IPA_DPS_UC2SEQ_PUSH_SRC_PIPE_SHFT 0x0 + +#define HWIO_IPA_DPS_UC2SEQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x0000061c) +#define HWIO_IPA_DPS_UC2SEQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000061c) +#define HWIO_IPA_DPS_UC2SEQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000061c) +#define HWIO_IPA_DPS_UC2SEQ_STATUS_RMSK 0xf +#define HWIO_IPA_DPS_UC2SEQ_STATUS_ATTR 0x1 +#define HWIO_IPA_DPS_UC2SEQ_STATUS_IN \ + in_dword_masked(HWIO_IPA_DPS_UC2SEQ_STATUS_ADDR, HWIO_IPA_DPS_UC2SEQ_STATUS_RMSK) +#define HWIO_IPA_DPS_UC2SEQ_STATUS_INM(m) \ + in_dword_masked(HWIO_IPA_DPS_UC2SEQ_STATUS_ADDR, m) +#define HWIO_IPA_DPS_UC2SEQ_STATUS_FILL_LEVEL_BMSK 0xf +#define HWIO_IPA_DPS_UC2SEQ_STATUS_FILL_LEVEL_SHFT 0x0 + +#define HWIO_IPA_DPS_SEQ2UC_RD_ADDR (IPA_DEBUG_REG_BASE + 0x00000620) +#define HWIO_IPA_DPS_SEQ2UC_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000620) +#define HWIO_IPA_DPS_SEQ2UC_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000620) +#define HWIO_IPA_DPS_SEQ2UC_RD_RMSK 0xbfffffff +#define HWIO_IPA_DPS_SEQ2UC_RD_ATTR 0x1 +#define HWIO_IPA_DPS_SEQ2UC_RD_IN \ + in_dword_masked(HWIO_IPA_DPS_SEQ2UC_RD_ADDR, HWIO_IPA_DPS_SEQ2UC_RD_RMSK) +#define HWIO_IPA_DPS_SEQ2UC_RD_INM(m) \ + in_dword_masked(HWIO_IPA_DPS_SEQ2UC_RD_ADDR, m) +#define HWIO_IPA_DPS_SEQ2UC_RD_TYPE_BMSK 0x80000000 +#define HWIO_IPA_DPS_SEQ2UC_RD_TYPE_SHFT 0x1f +#define HWIO_IPA_DPS_SEQ2UC_RD_DEST_PIPE_BMSK 0x3fc00000 +#define HWIO_IPA_DPS_SEQ2UC_RD_DEST_PIPE_SHFT 0x16 +#define HWIO_IPA_DPS_SEQ2UC_RD_CTX_ID_BMSK 0x3c0000 +#define HWIO_IPA_DPS_SEQ2UC_RD_CTX_ID_SHFT 0x12 +#define HWIO_IPA_DPS_SEQ2UC_RD_SRC_ID_BMSK 0x3fc00 +#define HWIO_IPA_DPS_SEQ2UC_RD_SRC_ID_SHFT 0xa +#define HWIO_IPA_DPS_SEQ2UC_RD_SRC_FLAGS_BMSK 0x300 +#define HWIO_IPA_DPS_SEQ2UC_RD_SRC_FLAGS_SHFT 0x8 +#define HWIO_IPA_DPS_SEQ2UC_RD_SRC_PIPE_BMSK 0xff +#define HWIO_IPA_DPS_SEQ2UC_RD_SRC_PIPE_SHFT 0x0 + +#define HWIO_IPA_DPS_SEQ2UC_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x00000624) +#define HWIO_IPA_DPS_SEQ2UC_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000624) +#define HWIO_IPA_DPS_SEQ2UC_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000624) +#define HWIO_IPA_DPS_SEQ2UC_STATUS_RMSK 0xf +#define HWIO_IPA_DPS_SEQ2UC_STATUS_ATTR 0x1 +#define HWIO_IPA_DPS_SEQ2UC_STATUS_IN \ + in_dword_masked(HWIO_IPA_DPS_SEQ2UC_STATUS_ADDR, HWIO_IPA_DPS_SEQ2UC_STATUS_RMSK) +#define HWIO_IPA_DPS_SEQ2UC_STATUS_INM(m) \ + in_dword_masked(HWIO_IPA_DPS_SEQ2UC_STATUS_ADDR, m) +#define HWIO_IPA_DPS_SEQ2UC_STATUS_FILL_LEVEL_BMSK 0xf +#define HWIO_IPA_DPS_SEQ2UC_STATUS_FILL_LEVEL_SHFT 0x0 + +#define HWIO_IPA_DPS_SEQ2UC_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x00000628) +#define HWIO_IPA_DPS_SEQ2UC_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000628) +#define HWIO_IPA_DPS_SEQ2UC_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000628) +#define HWIO_IPA_DPS_SEQ2UC_CMD_RMSK 0x1 +#define HWIO_IPA_DPS_SEQ2UC_CMD_ATTR 0x2 +#define HWIO_IPA_DPS_SEQ2UC_CMD_OUT(v) \ + out_dword(HWIO_IPA_DPS_SEQ2UC_CMD_ADDR,v) +#define HWIO_IPA_DPS_SEQ2UC_CMD_POP_BMSK 0x1 +#define HWIO_IPA_DPS_SEQ2UC_CMD_POP_SHFT 0x0 + +#define HWIO_IPA_NTF_TX_CMDQ_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x0000062c) +#define HWIO_IPA_NTF_TX_CMDQ_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000062c) +#define HWIO_IPA_NTF_TX_CMDQ_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000062c) +#define HWIO_IPA_NTF_TX_CMDQ_CMD_RMSK 0xff7 +#define HWIO_IPA_NTF_TX_CMDQ_CMD_ATTR 0x3 +#define HWIO_IPA_NTF_TX_CMDQ_CMD_IN \ + in_dword_masked(HWIO_IPA_NTF_TX_CMDQ_CMD_ADDR, HWIO_IPA_NTF_TX_CMDQ_CMD_RMSK) +#define HWIO_IPA_NTF_TX_CMDQ_CMD_INM(m) \ + in_dword_masked(HWIO_IPA_NTF_TX_CMDQ_CMD_ADDR, m) +#define HWIO_IPA_NTF_TX_CMDQ_CMD_OUT(v) \ + out_dword(HWIO_IPA_NTF_TX_CMDQ_CMD_ADDR,v) +#define HWIO_IPA_NTF_TX_CMDQ_CMD_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_NTF_TX_CMDQ_CMD_ADDR,m,v,HWIO_IPA_NTF_TX_CMDQ_CMD_IN) +#define HWIO_IPA_NTF_TX_CMDQ_CMD_CMD_CLIENT_BMSK 0xff0 +#define HWIO_IPA_NTF_TX_CMDQ_CMD_CMD_CLIENT_SHFT 0x4 +#define HWIO_IPA_NTF_TX_CMDQ_CMD_RD_REQ_BMSK 0x4 +#define HWIO_IPA_NTF_TX_CMDQ_CMD_RD_REQ_SHFT 0x2 +#define HWIO_IPA_NTF_TX_CMDQ_CMD_POP_CMD_BMSK 0x2 +#define HWIO_IPA_NTF_TX_CMDQ_CMD_POP_CMD_SHFT 0x1 +#define HWIO_IPA_NTF_TX_CMDQ_CMD_WRITE_CMD_BMSK 0x1 +#define HWIO_IPA_NTF_TX_CMDQ_CMD_WRITE_CMD_SHFT 0x0 + +#define HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_ADDR (IPA_DEBUG_REG_BASE + 0x00000630) +#define HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000630) +#define HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000630) +#define HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_RMSK 0x7ffffff +#define HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_ATTR 0x3 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_IN \ + in_dword_masked(HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_ADDR, HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_RMSK) +#define HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_INM(m) \ + in_dword_masked(HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_ADDR, m) +#define HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_OUT(v) \ + out_dword(HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_ADDR,v) +#define HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_ADDR,m,v,HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_IN) +#define HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_SEG_CTX_ID_F_BMSK 0x6000000 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_SEG_CTX_ID_F_SHFT 0x19 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_SEG_VALID_F_BMSK 0x1000000 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_SEG_VALID_F_SHFT 0x18 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_CMDQ_VIRT_COD_F_BMSK 0x800000 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_CMDQ_VIRT_COD_F_SHFT 0x17 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_CMDQ_TYPE_F_BMSK 0x400000 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_CMDQ_TYPE_F_SHFT 0x16 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_CMDQ_OPCODE_F_BMSK 0x300000 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_CMDQ_OPCODE_F_SHFT 0x14 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_CMDQ_SRC_PIPE_F_BMSK 0xff000 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_CMDQ_SRC_PIPE_F_SHFT 0xc +#define HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_CMDQ_SRC_ID_F_BMSK 0xff0 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_CMDQ_SRC_ID_F_SHFT 0x4 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_CMDQ_CTX_ID_F_BMSK 0xf +#define HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_CMDQ_CTX_ID_F_SHFT 0x0 + +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_ADDR (IPA_DEBUG_REG_BASE + 0x00000634) +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000634) +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000634) +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_RMSK 0x7ffffff +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_ATTR 0x1 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_IN \ + in_dword_masked(HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_ADDR, HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_RMSK, HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_ATTR) +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_INM(m) \ + in_dword_masked(HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_ADDR, m, HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_ATTR) +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_SEG_CTX_ID_F_BMSK 0x6000000 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_SEG_CTX_ID_F_SHFT 0x19 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_SEG_VALID_F_BMSK 0x1000000 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_SEG_VALID_F_SHFT 0x18 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_CMDQ_VIRT_COD_F_BMSK 0x800000 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_CMDQ_VIRT_COD_F_SHFT 0x17 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_CMDQ_TYPE_F_BMSK 0x400000 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_CMDQ_TYPE_F_SHFT 0x16 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_CMDQ_OPCODE_F_BMSK 0x300000 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_CMDQ_OPCODE_F_SHFT 0x14 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_CMDQ_SRC_PIPE_F_BMSK 0xff000 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_CMDQ_SRC_PIPE_F_SHFT 0xc +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_CMDQ_SRC_ID_F_BMSK 0xff0 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_CMDQ_SRC_ID_F_SHFT 0x4 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_CMDQ_CTX_ID_F_BMSK 0xf +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_CMDQ_CTX_ID_F_SHFT 0x0 + +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x00000638) +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000638) +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000638) +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_RMSK 0x1ff +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_ATTR 0x1 +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_IN \ + in_dword_masked(HWIO_IPA_NTF_TX_CMDQ_STATUS_ADDR, HWIO_IPA_NTF_TX_CMDQ_STATUS_RMSK, HWIO_IPA_NTF_TX_CMDQ_STATUS_ATTR) +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_INM(m) \ + in_dword_masked(HWIO_IPA_NTF_TX_CMDQ_STATUS_ADDR, m, HWIO_IPA_NTF_TX_CMDQ_STATUS_ATTR) +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_CMDQ_DEPTH_BMSK 0x1fc +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_CMDQ_DEPTH_SHFT 0x2 +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_CMDQ_FULL_BMSK 0x2 +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_CMDQ_FULL_SHFT 0x1 +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_STATUS_BMSK 0x1 +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_STATUS_SHFT 0x0 + +#define HWIO_IPA_NTF_TX_SNP_ADDR (IPA_DEBUG_REG_BASE + 0x0000063c) +#define HWIO_IPA_NTF_TX_SNP_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000063c) +#define HWIO_IPA_NTF_TX_SNP_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000063c) +#define HWIO_IPA_NTF_TX_SNP_RMSK 0xfffffff +#define HWIO_IPA_NTF_TX_SNP_ATTR 0x3 +#define HWIO_IPA_NTF_TX_SNP_IN \ + in_dword_masked(HWIO_IPA_NTF_TX_SNP_ADDR, HWIO_IPA_NTF_TX_SNP_RMSK) +#define HWIO_IPA_NTF_TX_SNP_INM(m) \ + in_dword_masked(HWIO_IPA_NTF_TX_SNP_ADDR, m) +#define HWIO_IPA_NTF_TX_SNP_OUT(v) \ + out_dword(HWIO_IPA_NTF_TX_SNP_ADDR,v) +#define HWIO_IPA_NTF_TX_SNP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_NTF_TX_SNP_ADDR,m,v,HWIO_IPA_NTF_TX_SNP_IN) +#define HWIO_IPA_NTF_TX_SNP_SNP_ADDR_BMSK 0xff00000 +#define HWIO_IPA_NTF_TX_SNP_SNP_ADDR_SHFT 0x14 +#define HWIO_IPA_NTF_TX_SNP_SNP_HEAD_BMSK 0xff000 +#define HWIO_IPA_NTF_TX_SNP_SNP_HEAD_SHFT 0xc +#define HWIO_IPA_NTF_TX_SNP_SNP_NEXT_BMSK 0xff0 +#define HWIO_IPA_NTF_TX_SNP_SNP_NEXT_SHFT 0x4 +#define HWIO_IPA_NTF_TX_SNP_SNP_NEXT_IS_VALID_BMSK 0x8 +#define HWIO_IPA_NTF_TX_SNP_SNP_NEXT_IS_VALID_SHFT 0x3 +#define HWIO_IPA_NTF_TX_SNP_SNP_VALID_BMSK 0x4 +#define HWIO_IPA_NTF_TX_SNP_SNP_VALID_SHFT 0x2 +#define HWIO_IPA_NTF_TX_SNP_SNP_WRITE_BMSK 0x2 +#define HWIO_IPA_NTF_TX_SNP_SNP_WRITE_SHFT 0x1 +#define HWIO_IPA_NTF_TX_SNP_SNP_LAST_BMSK 0x1 +#define HWIO_IPA_NTF_TX_SNP_SNP_LAST_SHFT 0x0 + +#define HWIO_IPA_NTF_TX_CMDQ_COUNT_ADDR (IPA_DEBUG_REG_BASE + 0x00000640) +#define HWIO_IPA_NTF_TX_CMDQ_COUNT_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000640) +#define HWIO_IPA_NTF_TX_CMDQ_COUNT_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000640) +#define HWIO_IPA_NTF_TX_CMDQ_COUNT_RMSK 0x7f +#define HWIO_IPA_NTF_TX_CMDQ_COUNT_ATTR 0x1 +#define HWIO_IPA_NTF_TX_CMDQ_COUNT_IN \ + in_dword_masked(HWIO_IPA_NTF_TX_CMDQ_COUNT_ADDR, HWIO_IPA_NTF_TX_CMDQ_COUNT_RMSK, HWIO_IPA_NTF_TX_CMDQ_COUNT_ATTR) +#define HWIO_IPA_NTF_TX_CMDQ_COUNT_INM(m) \ + in_dword_masked(HWIO_IPA_NTF_TX_CMDQ_COUNT_ADDR, m, HWIO_IPA_NTF_TX_CMDQ_COUNT_ATTR) +#define HWIO_IPA_NTF_TX_CMDQ_COUNT_FIFO_COUNT_BMSK 0x7f +#define HWIO_IPA_NTF_TX_CMDQ_COUNT_FIFO_COUNT_SHFT 0x0 + +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x00000644) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000644) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000644) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_RMSK 0x7ff +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_ATTR 0x3 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_IN \ + in_dword_masked(HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_ADDR, HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_RMSK) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_INM(m) \ + in_dword_masked(HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_ADDR, m) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_OUT(v) \ + out_dword(HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_ADDR,v) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_ADDR,m,v,HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_IN) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_RD_REQ_BMSK 0x400 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_RD_REQ_SHFT 0xa +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_CMD_CLIENT_BMSK 0x3fc +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_CMD_CLIENT_SHFT 0x2 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_POP_CMD_BMSK 0x2 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_POP_CMD_SHFT 0x1 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_WRITE_CMD_BMSK 0x1 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_WRITE_CMD_SHFT 0x0 + +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_ADDR (IPA_DEBUG_REG_BASE + 0x00000648) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000648) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000648) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_RMSK 0xffffffff +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_ATTR 0x3 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_IN \ + in_dword_masked(HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_ADDR, HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_RMSK, HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_ATTR) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_INM(m) \ + in_dword_masked(HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_ADDR, m, HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_ATTR) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_OUT(v) \ + out_dword(HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_ADDR,v) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_ADDR,m,v,HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_IN) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_CMDQ_USERDATA_BMSK 0xf8000000 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_CMDQ_USERDATA_SHFT 0x1b +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_CMDQ_SRC_ID_VALID_BMSK 0x4000000 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_CMDQ_SRC_ID_VALID_SHFT 0x1a +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_CMDQ_SENT_BMSK 0x2000000 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_CMDQ_SENT_SHFT 0x19 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_CMDQ_ORIGIN_BMSK 0x1000000 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_CMDQ_ORIGIN_SHFT 0x18 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_CMDQ_LENGTH_BMSK 0xffff00 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_CMDQ_LENGTH_SHFT 0x8 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_CMDQ_SRC_ID_BMSK 0xff +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_CMDQ_SRC_ID_SHFT 0x0 + +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_1_ADDR (IPA_DEBUG_REG_BASE + 0x0000064c) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_1_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000064c) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_1_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000064c) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_1_RMSK 0x7f +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_1_ATTR 0x1 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_1_IN \ + in_dword_masked(HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_1_ADDR, HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_1_RMSK) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_1_INM(m) \ + in_dword_masked(HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_1_ADDR, m) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_1_CMDQ_EGRESS_BMSK 0x7e +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_1_CMDQ_EGRESS_SHFT 0x1 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_1_CMDQ_FNR_AGGR_FC_BMSK 0x1 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_1_CMDQ_FNR_AGGR_FC_SHFT 0x0 + +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x00000650 + 0x4 * (n)) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x00000650 + 0x4 * (n)) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x00000650 + 0x4 * (n)) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_n_RMSK 0xffffffff +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_n_MAXn 1 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_n_ATTR 0x1 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_n_INI(n) \ + in_dword_masked(HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_n_ADDR(n), HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_n_RMSK) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_n_ADDR(n), mask) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_n_CMDQ_EMPTY_BMSK 0xffffffff +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_n_CMDQ_EMPTY_SHFT 0x0 + +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x00000670) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000670) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000670) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_RMSK 0x1ff +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_ATTR 0x1 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_IN \ + in_dword_masked(HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_ADDR, HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_RMSK, HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_ATTR) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_INM(m) \ + in_dword_masked(HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_ADDR, m, HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_ATTR) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_CMDQ_DEPTH_BMSK 0x1fc +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_CMDQ_DEPTH_SHFT 0x2 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_CMDQ_FULL_BMSK 0x2 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_CMDQ_FULL_SHFT 0x1 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_STATUS_BMSK 0x1 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_STATUS_SHFT 0x0 + +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_ADDR (IPA_DEBUG_REG_BASE + 0x00000674) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000674) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000674) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_RMSK 0x7f +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_ATTR 0x1 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_IN \ + in_dword_masked(HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_ADDR, HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_RMSK, HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_ATTR) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_INM(m) \ + in_dword_masked(HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_ADDR, m, HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_ATTR) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_FIFO_COUNT_BMSK 0x7f +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_FIFO_COUNT_SHFT 0x0 + +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ADDR (IPA_DEBUG_REG_BASE + 0x00000678) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000678) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000678) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_CFG_RMSK 0xffffffe0 +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ATTR 0x3 +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_CFG_IN \ + in_dword_masked(HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ADDR, HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_CFG_RMSK) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ADDR, m) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_CFG_OUT(v) \ + out_dword(HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ADDR,v) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ADDR,m,v,HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_CFG_IN) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ACKINJ_LENGTH_BMSK 0xffff0000 +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ACKINJ_LENGTH_SHFT 0x10 +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ACKINJ_SRC_ID_BMSK 0xff00 +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ACKINJ_SRC_ID_SHFT 0x8 +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ACKINJ_SENT_BMSK 0x80 +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ACKINJ_SENT_SHFT 0x7 +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ACKINJ_ORIGIN_BMSK 0x40 +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ACKINJ_ORIGIN_SHFT 0x6 +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ACKINJ_SRC_ID_VALID_BMSK 0x20 +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ACKINJ_SRC_ID_VALID_SHFT 0x5 + +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_PIPE_ADDR (IPA_DEBUG_REG_BASE + 0x0000067c) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_PIPE_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000067c) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_PIPE_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000067c) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_PIPE_RMSK 0xffff +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_PIPE_ATTR 0x3 +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_PIPE_IN \ + in_dword_masked(HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_PIPE_ADDR, HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_PIPE_RMSK) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_PIPE_INM(m) \ + in_dword_masked(HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_PIPE_ADDR, m) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_PIPE_OUT(v) \ + out_dword(HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_PIPE_ADDR,v) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_PIPE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_PIPE_ADDR,m,v,HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_PIPE_IN) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_PIPE_PROD_ACKINJ_SRC_PIPE_BMSK 0xff00 +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_PIPE_PROD_ACKINJ_SRC_PIPE_SHFT 0x8 +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_PIPE_CONS_ACKINJ_SRC_PIPE_BMSK 0xff +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_PIPE_CONS_ACKINJ_SRC_PIPE_SHFT 0x0 + +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKUPD_CFG_ADDR (IPA_DEBUG_REG_BASE + 0x00000680) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKUPD_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000680) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKUPD_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000680) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKUPD_CFG_RMSK 0x1ffff +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKUPD_CFG_ATTR 0x3 +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKUPD_CFG_IN \ + in_dword_masked(HWIO_IPA_ACKMNGR_SW_ACCESS_ACKUPD_CFG_ADDR, HWIO_IPA_ACKMNGR_SW_ACCESS_ACKUPD_CFG_RMSK) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKUPD_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_ACKMNGR_SW_ACCESS_ACKUPD_CFG_ADDR, m) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKUPD_CFG_OUT(v) \ + out_dword(HWIO_IPA_ACKMNGR_SW_ACCESS_ACKUPD_CFG_ADDR,v) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKUPD_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_ACKMNGR_SW_ACCESS_ACKUPD_CFG_ADDR,m,v,HWIO_IPA_ACKMNGR_SW_ACCESS_ACKUPD_CFG_IN) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKUPD_CFG_ACKUPD_ERROR_BMSK 0x10000 +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKUPD_CFG_ACKUPD_ERROR_SHFT 0x10 +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKUPD_CFG_ACKUPD_SRC_ID_BMSK 0xff00 +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKUPD_CFG_ACKUPD_SRC_ID_SHFT 0x8 +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKUPD_CFG_ACKUPD_SRC_PIPE_BMSK 0xff +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKUPD_CFG_ACKUPD_SRC_PIPE_SHFT 0x0 + +#define HWIO_IPA_ACKMNGR_SW_ACCESS_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x00000684) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000684) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000684) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_CMD_RMSK 0x3 +#define HWIO_IPA_ACKMNGR_SW_ACCESS_CMD_ATTR 0x2 +#define HWIO_IPA_ACKMNGR_SW_ACCESS_CMD_OUT(v) \ + out_dword(HWIO_IPA_ACKMNGR_SW_ACCESS_CMD_ADDR,v) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_CMD_ACKUPD_VALID_BMSK 0x2 +#define HWIO_IPA_ACKMNGR_SW_ACCESS_CMD_ACKUPD_VALID_SHFT 0x1 +#define HWIO_IPA_ACKMNGR_SW_ACCESS_CMD_ACKINJ_VALID_BMSK 0x1 +#define HWIO_IPA_ACKMNGR_SW_ACCESS_CMD_ACKINJ_VALID_SHFT 0x0 + +#define HWIO_IPA_ACKMNGR_SW_ACCESS_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x00000688) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000688) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000688) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_STATUS_RMSK 0x3 +#define HWIO_IPA_ACKMNGR_SW_ACCESS_STATUS_ATTR 0x1 +#define HWIO_IPA_ACKMNGR_SW_ACCESS_STATUS_IN \ + in_dword_masked(HWIO_IPA_ACKMNGR_SW_ACCESS_STATUS_ADDR, HWIO_IPA_ACKMNGR_SW_ACCESS_STATUS_RMSK) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_STATUS_INM(m) \ + in_dword_masked(HWIO_IPA_ACKMNGR_SW_ACCESS_STATUS_ADDR, m) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_STATUS_ACKUPD_READY_BMSK 0x2 +#define HWIO_IPA_ACKMNGR_SW_ACCESS_STATUS_ACKUPD_READY_SHFT 0x1 +#define HWIO_IPA_ACKMNGR_SW_ACCESS_STATUS_ACKINJ_READY_BMSK 0x1 +#define HWIO_IPA_ACKMNGR_SW_ACCESS_STATUS_ACKINJ_READY_SHFT 0x0 + +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ADDR (IPA_DEBUG_REG_BASE + 0x0000068c) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000068c) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000068c) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG_RMSK 0xffffffe0 +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ATTR 0x3 +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG_IN \ + in_dword_masked(HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ADDR, HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG_RMSK) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ADDR, m) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG_OUT(v) \ + out_dword(HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ADDR,v) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ADDR,m,v,HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG_IN) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ACKINJ_LENGTH_BMSK 0xffff0000 +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ACKINJ_LENGTH_SHFT 0x10 +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ACKINJ_SRC_ID_BMSK 0xff00 +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ACKINJ_SRC_ID_SHFT 0x8 +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ACKINJ_SENT_BMSK 0x80 +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ACKINJ_SENT_SHFT 0x7 +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ACKINJ_ORIGIN_BMSK 0x40 +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ACKINJ_ORIGIN_SHFT 0x6 +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ACKINJ_SRC_ID_VALID_BMSK 0x20 +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ACKINJ_SRC_ID_VALID_SHFT 0x5 + +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKUPD_CFG_ADDR (IPA_DEBUG_REG_BASE + 0x00000690) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKUPD_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000690) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKUPD_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000690) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKUPD_CFG_RMSK 0xffff +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKUPD_CFG_ATTR 0x3 +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKUPD_CFG_IN \ + in_dword_masked(HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKUPD_CFG_ADDR, HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKUPD_CFG_RMSK) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKUPD_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKUPD_CFG_ADDR, m) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKUPD_CFG_OUT(v) \ + out_dword(HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKUPD_CFG_ADDR,v) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKUPD_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKUPD_CFG_ADDR,m,v,HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKUPD_CFG_IN) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKUPD_CFG_ACKUPD_SRC_ID_BMSK 0xff00 +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKUPD_CFG_ACKUPD_SRC_ID_SHFT 0x8 +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKUPD_CFG_ACKUPD_SRC_PIPE_BMSK 0xff +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKUPD_CFG_ACKUPD_SRC_PIPE_SHFT 0x0 + +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x00000694) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000694) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000694) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_CMD_RMSK 0x3 +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_CMD_ATTR 0x2 +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_CMD_OUT(v) \ + out_dword(HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_CMD_ADDR,v) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_CMD_ACKUPD_VALID_BMSK 0x2 +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_CMD_ACKUPD_VALID_SHFT 0x1 +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_CMD_ACKINJ_VALID_BMSK 0x1 +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_CMD_ACKINJ_VALID_SHFT 0x0 + +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x00000698) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000698) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000698) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_STATUS_RMSK 0x3 +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_STATUS_ATTR 0x1 +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_STATUS_IN \ + in_dword_masked(HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_STATUS_ADDR, HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_STATUS_RMSK) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_STATUS_INM(m) \ + in_dword_masked(HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_STATUS_ADDR, m) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_STATUS_ACKUPD_READY_BMSK 0x2 +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_STATUS_ACKUPD_READY_SHFT 0x1 +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_STATUS_ACKINJ_READY_BMSK 0x1 +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_STATUS_ACKINJ_READY_SHFT 0x0 + +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG1_ADDR (IPA_DEBUG_REG_BASE + 0x0000069c) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG1_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000069c) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG1_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000069c) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG1_RMSK 0x3f +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG1_ATTR 0x3 +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG1_IN \ + in_dword_masked(HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG1_ADDR, HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG1_RMSK) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG1_INM(m) \ + in_dword_masked(HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG1_ADDR, m) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG1_OUT(v) \ + out_dword(HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG1_ADDR,v) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG1_ADDR,m,v,HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG1_IN) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG1_ACKINJ_USERDATA_BMSK 0x3f +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG1_ACKINJ_USERDATA_SHFT 0x0 + +#define HWIO_IPA_NTF_TX_CMDQ_RELEASE_WR_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x000006a0 + 0x4 * (n)) +#define HWIO_IPA_NTF_TX_CMDQ_RELEASE_WR_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x000006a0 + 0x4 * (n)) +#define HWIO_IPA_NTF_TX_CMDQ_RELEASE_WR_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x000006a0 + 0x4 * (n)) +#define HWIO_IPA_NTF_TX_CMDQ_RELEASE_WR_n_RMSK 0xffffffff +#define HWIO_IPA_NTF_TX_CMDQ_RELEASE_WR_n_MAXn 1 +#define HWIO_IPA_NTF_TX_CMDQ_RELEASE_WR_n_ATTR 0x2 +#define HWIO_IPA_NTF_TX_CMDQ_RELEASE_WR_n_OUTI(n,val) \ + out_dword(HWIO_IPA_NTF_TX_CMDQ_RELEASE_WR_n_ADDR(n),val) +#define HWIO_IPA_NTF_TX_CMDQ_RELEASE_WR_n_RELEASE_WR_CMD_BMSK 0xffffffff +#define HWIO_IPA_NTF_TX_CMDQ_RELEASE_WR_n_RELEASE_WR_CMD_SHFT 0x0 + +#define HWIO_IPA_NTF_TX_CMDQ_RELEASE_RD_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x000006c0 + 0x4 * (n)) +#define HWIO_IPA_NTF_TX_CMDQ_RELEASE_RD_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x000006c0 + 0x4 * (n)) +#define HWIO_IPA_NTF_TX_CMDQ_RELEASE_RD_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x000006c0 + 0x4 * (n)) +#define HWIO_IPA_NTF_TX_CMDQ_RELEASE_RD_n_RMSK 0xffffffff +#define HWIO_IPA_NTF_TX_CMDQ_RELEASE_RD_n_MAXn 1 +#define HWIO_IPA_NTF_TX_CMDQ_RELEASE_RD_n_ATTR 0x2 +#define HWIO_IPA_NTF_TX_CMDQ_RELEASE_RD_n_OUTI(n,val) \ + out_dword(HWIO_IPA_NTF_TX_CMDQ_RELEASE_RD_n_ADDR(n),val) +#define HWIO_IPA_NTF_TX_CMDQ_RELEASE_RD_n_RELEASE_RD_CMD_BMSK 0xffffffff +#define HWIO_IPA_NTF_TX_CMDQ_RELEASE_RD_n_RELEASE_RD_CMD_SHFT 0x0 + +#define HWIO_IPA_NTF_TX_CMDQ_CFG_WR_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x000006e0 + 0x4 * (n)) +#define HWIO_IPA_NTF_TX_CMDQ_CFG_WR_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x000006e0 + 0x4 * (n)) +#define HWIO_IPA_NTF_TX_CMDQ_CFG_WR_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x000006e0 + 0x4 * (n)) +#define HWIO_IPA_NTF_TX_CMDQ_CFG_WR_n_RMSK 0xffffffff +#define HWIO_IPA_NTF_TX_CMDQ_CFG_WR_n_MAXn 1 +#define HWIO_IPA_NTF_TX_CMDQ_CFG_WR_n_ATTR 0x3 +#define HWIO_IPA_NTF_TX_CMDQ_CFG_WR_n_INI(n) \ + in_dword_masked(HWIO_IPA_NTF_TX_CMDQ_CFG_WR_n_ADDR(n), HWIO_IPA_NTF_TX_CMDQ_CFG_WR_n_RMSK) +#define HWIO_IPA_NTF_TX_CMDQ_CFG_WR_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_NTF_TX_CMDQ_CFG_WR_n_ADDR(n), mask) +#define HWIO_IPA_NTF_TX_CMDQ_CFG_WR_n_OUTI(n,val) \ + out_dword(HWIO_IPA_NTF_TX_CMDQ_CFG_WR_n_ADDR(n),val) +#define HWIO_IPA_NTF_TX_CMDQ_CFG_WR_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_NTF_TX_CMDQ_CFG_WR_n_ADDR(n),mask,val,HWIO_IPA_NTF_TX_CMDQ_CFG_WR_n_INI(n)) +#define HWIO_IPA_NTF_TX_CMDQ_CFG_WR_n_BLOCK_WR_BMSK 0xffffffff +#define HWIO_IPA_NTF_TX_CMDQ_CFG_WR_n_BLOCK_WR_SHFT 0x0 + +#define HWIO_IPA_NTF_TX_CMDQ_CFG_RD_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x00000710 + 0x4 * (n)) +#define HWIO_IPA_NTF_TX_CMDQ_CFG_RD_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x00000710 + 0x4 * (n)) +#define HWIO_IPA_NTF_TX_CMDQ_CFG_RD_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x00000710 + 0x4 * (n)) +#define HWIO_IPA_NTF_TX_CMDQ_CFG_RD_n_RMSK 0xffffffff +#define HWIO_IPA_NTF_TX_CMDQ_CFG_RD_n_MAXn 1 +#define HWIO_IPA_NTF_TX_CMDQ_CFG_RD_n_ATTR 0x3 +#define HWIO_IPA_NTF_TX_CMDQ_CFG_RD_n_INI(n) \ + in_dword_masked(HWIO_IPA_NTF_TX_CMDQ_CFG_RD_n_ADDR(n), HWIO_IPA_NTF_TX_CMDQ_CFG_RD_n_RMSK) +#define HWIO_IPA_NTF_TX_CMDQ_CFG_RD_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_NTF_TX_CMDQ_CFG_RD_n_ADDR(n), mask) +#define HWIO_IPA_NTF_TX_CMDQ_CFG_RD_n_OUTI(n,val) \ + out_dword(HWIO_IPA_NTF_TX_CMDQ_CFG_RD_n_ADDR(n),val) +#define HWIO_IPA_NTF_TX_CMDQ_CFG_RD_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_NTF_TX_CMDQ_CFG_RD_n_ADDR(n),mask,val,HWIO_IPA_NTF_TX_CMDQ_CFG_RD_n_INI(n)) +#define HWIO_IPA_NTF_TX_CMDQ_CFG_RD_n_BLOCK_RD_BMSK 0xffffffff +#define HWIO_IPA_NTF_TX_CMDQ_CFG_RD_n_BLOCK_RD_SHFT 0x0 + +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_EMPTY_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x00000730 + 0x4 * (n)) +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_EMPTY_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x00000730 + 0x4 * (n)) +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_EMPTY_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x00000730 + 0x4 * (n)) +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_EMPTY_n_RMSK 0xffffffff +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_EMPTY_n_MAXn 1 +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_EMPTY_n_ATTR 0x1 +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_EMPTY_n_INI(n) \ + in_dword_masked(HWIO_IPA_NTF_TX_CMDQ_STATUS_EMPTY_n_ADDR(n), HWIO_IPA_NTF_TX_CMDQ_STATUS_EMPTY_n_RMSK) +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_EMPTY_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_NTF_TX_CMDQ_STATUS_EMPTY_n_ADDR(n), mask) +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_EMPTY_n_CMDQ_EMPTY_BMSK 0xffffffff +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_EMPTY_n_CMDQ_EMPTY_SHFT 0x0 + +#define HWIO_IPA_BASE_ADDR_ADDR (IPA_DEBUG_REG_BASE + 0x00000740) +#define HWIO_IPA_BASE_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000740) +#define HWIO_IPA_BASE_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000740) +#define HWIO_IPA_BASE_ADDR_RMSK 0xffffffff +#define HWIO_IPA_BASE_ADDR_ATTR 0x3 +#define HWIO_IPA_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_BASE_ADDR_ADDR, HWIO_IPA_BASE_ADDR_RMSK) +#define HWIO_IPA_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_BASE_ADDR_ADDR, m) +#define HWIO_IPA_BASE_ADDR_OUT(v) \ + out_dword(HWIO_IPA_BASE_ADDR_ADDR,v) +#define HWIO_IPA_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_BASE_ADDR_ADDR,m,v,HWIO_IPA_BASE_ADDR_IN) +#define HWIO_IPA_BASE_ADDR_BASE_BMSK 0xffe00000 +#define HWIO_IPA_BASE_ADDR_BASE_SHFT 0x15 +#define HWIO_IPA_BASE_ADDR_ZERO_BMSK 0x1fffff +#define HWIO_IPA_BASE_ADDR_ZERO_SHFT 0x0 + +#define HWIO_IPA_BASE_ADDR_MSB_ADDR (IPA_DEBUG_REG_BASE + 0x00000744) +#define HWIO_IPA_BASE_ADDR_MSB_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000744) +#define HWIO_IPA_BASE_ADDR_MSB_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000744) +#define HWIO_IPA_BASE_ADDR_MSB_RMSK 0xffffffff +#define HWIO_IPA_BASE_ADDR_MSB_ATTR 0x3 +#define HWIO_IPA_BASE_ADDR_MSB_IN \ + in_dword_masked(HWIO_IPA_BASE_ADDR_MSB_ADDR, HWIO_IPA_BASE_ADDR_MSB_RMSK) +#define HWIO_IPA_BASE_ADDR_MSB_INM(m) \ + in_dword_masked(HWIO_IPA_BASE_ADDR_MSB_ADDR, m) +#define HWIO_IPA_BASE_ADDR_MSB_OUT(v) \ + out_dword(HWIO_IPA_BASE_ADDR_MSB_ADDR,v) +#define HWIO_IPA_BASE_ADDR_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_BASE_ADDR_MSB_ADDR,m,v,HWIO_IPA_BASE_ADDR_MSB_IN) +#define HWIO_IPA_BASE_ADDR_MSB_BASE_MSB_BMSK 0xffffffff +#define HWIO_IPA_BASE_ADDR_MSB_BASE_MSB_SHFT 0x0 + +#define HWIO_IPA_ENDP_GSI_CFG1_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x00000800 + 0x4 * (n)) +#define HWIO_IPA_ENDP_GSI_CFG1_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x00000800 + 0x4 * (n)) +#define HWIO_IPA_ENDP_GSI_CFG1_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x00000800 + 0x4 * (n)) +#define HWIO_IPA_ENDP_GSI_CFG1_n_RMSK 0x80010000 +#define HWIO_IPA_ENDP_GSI_CFG1_n_MAXn 35 +#define HWIO_IPA_ENDP_GSI_CFG1_n_ATTR 0x3 +#define HWIO_IPA_ENDP_GSI_CFG1_n_INI(n) \ + in_dword_masked(HWIO_IPA_ENDP_GSI_CFG1_n_ADDR(n), HWIO_IPA_ENDP_GSI_CFG1_n_RMSK) +#define HWIO_IPA_ENDP_GSI_CFG1_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ENDP_GSI_CFG1_n_ADDR(n), mask) +#define HWIO_IPA_ENDP_GSI_CFG1_n_OUTI(n,val) \ + out_dword(HWIO_IPA_ENDP_GSI_CFG1_n_ADDR(n),val) +#define HWIO_IPA_ENDP_GSI_CFG1_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_ENDP_GSI_CFG1_n_ADDR(n),mask,val,HWIO_IPA_ENDP_GSI_CFG1_n_INI(n)) +#define HWIO_IPA_ENDP_GSI_CFG1_n_INIT_ENDP_BMSK 0x80000000 +#define HWIO_IPA_ENDP_GSI_CFG1_n_INIT_ENDP_SHFT 0x1f +#define HWIO_IPA_ENDP_GSI_CFG1_n_ENDP_EN_BMSK 0x10000 +#define HWIO_IPA_ENDP_GSI_CFG1_n_ENDP_EN_SHFT 0x10 + +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x00001000 + 0x4 * (n)) +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x00001000 + 0x4 * (n)) +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x00001000 + 0x4 * (n)) +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_RMSK 0xffffff +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_MAXn 35 +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_ATTR 0x3 +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_INI(n) \ + in_dword_masked(HWIO_IPA_ENDP_GSI_CFG_TLV_n_ADDR(n), HWIO_IPA_ENDP_GSI_CFG_TLV_n_RMSK) +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ENDP_GSI_CFG_TLV_n_ADDR(n), mask) +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_OUTI(n,val) \ + out_dword(HWIO_IPA_ENDP_GSI_CFG_TLV_n_ADDR(n),val) +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_ENDP_GSI_CFG_TLV_n_ADDR(n),mask,val,HWIO_IPA_ENDP_GSI_CFG_TLV_n_INI(n)) +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_FIFO_SIZE_BMSK 0xff0000 +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_FIFO_SIZE_SHFT 0x10 +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_FIFO_BASE_ADDR_BMSK 0xffff +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_FIFO_BASE_ADDR_SHFT 0x0 + +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x00001400 + 0x4 * (n)) +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x00001400 + 0x4 * (n)) +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x00001400 + 0x4 * (n)) +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_RMSK 0xffffff +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_MAXn 35 +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_ATTR 0x3 +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_INI(n) \ + in_dword_masked(HWIO_IPA_ENDP_GSI_CFG_AOS_n_ADDR(n), HWIO_IPA_ENDP_GSI_CFG_AOS_n_RMSK) +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ENDP_GSI_CFG_AOS_n_ADDR(n), mask) +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_OUTI(n,val) \ + out_dword(HWIO_IPA_ENDP_GSI_CFG_AOS_n_ADDR(n),val) +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_ENDP_GSI_CFG_AOS_n_ADDR(n),mask,val,HWIO_IPA_ENDP_GSI_CFG_AOS_n_INI(n)) +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_FIFO_SIZE_BMSK 0xff0000 +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_FIFO_SIZE_SHFT 0x10 +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_FIFO_BASE_ADDR_BMSK 0xffff +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_FIFO_BASE_ADDR_SHFT 0x0 + +#define HWIO_IPA_COAL_VP_AOS_FIFO_n_ADDR(n) (IPA_DEBUG_REG_BASE + 0x00001800 + 0x4 * (n)) +#define HWIO_IPA_COAL_VP_AOS_FIFO_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + 0x00001800 + 0x4 * (n)) +#define HWIO_IPA_COAL_VP_AOS_FIFO_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + 0x00001800 + 0x4 * (n)) +#define HWIO_IPA_COAL_VP_AOS_FIFO_n_RMSK 0xffffff +#define HWIO_IPA_COAL_VP_AOS_FIFO_n_MAXn 31 +#define HWIO_IPA_COAL_VP_AOS_FIFO_n_ATTR 0x3 +#define HWIO_IPA_COAL_VP_AOS_FIFO_n_INI(n) \ + in_dword_masked(HWIO_IPA_COAL_VP_AOS_FIFO_n_ADDR(n), HWIO_IPA_COAL_VP_AOS_FIFO_n_RMSK) +#define HWIO_IPA_COAL_VP_AOS_FIFO_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_COAL_VP_AOS_FIFO_n_ADDR(n), mask) +#define HWIO_IPA_COAL_VP_AOS_FIFO_n_OUTI(n,val) \ + out_dword(HWIO_IPA_COAL_VP_AOS_FIFO_n_ADDR(n),val) +#define HWIO_IPA_COAL_VP_AOS_FIFO_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_COAL_VP_AOS_FIFO_n_ADDR(n),mask,val,HWIO_IPA_COAL_VP_AOS_FIFO_n_INI(n)) +#define HWIO_IPA_COAL_VP_AOS_FIFO_n_FIFO_SIZE_BMSK 0xff0000 +#define HWIO_IPA_COAL_VP_AOS_FIFO_n_FIFO_SIZE_SHFT 0x10 +#define HWIO_IPA_COAL_VP_AOS_FIFO_n_FIFO_BASE_ADDR_BMSK 0xffff +#define HWIO_IPA_COAL_VP_AOS_FIFO_n_FIFO_BASE_ADDR_SHFT 0x0 + +#define HWIO_IPA_QMB_DEBUG_CTRL_ADDR (IPA_DEBUG_REG_BASE + 0x00001d40) +#define HWIO_IPA_QMB_DEBUG_CTRL_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00001d40) +#define HWIO_IPA_QMB_DEBUG_CTRL_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00001d40) +#define HWIO_IPA_QMB_DEBUG_CTRL_RMSK 0x1 +#define HWIO_IPA_QMB_DEBUG_CTRL_ATTR 0x3 +#define HWIO_IPA_QMB_DEBUG_CTRL_IN \ + in_dword_masked(HWIO_IPA_QMB_DEBUG_CTRL_ADDR, HWIO_IPA_QMB_DEBUG_CTRL_RMSK) +#define HWIO_IPA_QMB_DEBUG_CTRL_INM(m) \ + in_dword_masked(HWIO_IPA_QMB_DEBUG_CTRL_ADDR, m) +#define HWIO_IPA_QMB_DEBUG_CTRL_OUT(v) \ + out_dword(HWIO_IPA_QMB_DEBUG_CTRL_ADDR,v) +#define HWIO_IPA_QMB_DEBUG_CTRL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_QMB_DEBUG_CTRL_ADDR,m,v,HWIO_IPA_QMB_DEBUG_CTRL_IN) +#define HWIO_IPA_QMB_DEBUG_CTRL_RAM_SLAVEWAY_ACCESS_PROTECTION_DISABLE_BMSK 0x1 +#define HWIO_IPA_QMB_DEBUG_CTRL_RAM_SLAVEWAY_ACCESS_PROTECTION_DISABLE_SHFT 0x0 + +#define HWIO_IPA_CTXH_CTRL_ADDR (IPA_DEBUG_REG_BASE + 0x00001e50) +#define HWIO_IPA_CTXH_CTRL_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00001e50) +#define HWIO_IPA_CTXH_CTRL_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00001e50) +#define HWIO_IPA_CTXH_CTRL_RMSK 0xe000000f +#define HWIO_IPA_CTXH_CTRL_ATTR 0x3 +#define HWIO_IPA_CTXH_CTRL_IN \ + in_dword_masked(HWIO_IPA_CTXH_CTRL_ADDR, HWIO_IPA_CTXH_CTRL_RMSK) +#define HWIO_IPA_CTXH_CTRL_INM(m) \ + in_dword_masked(HWIO_IPA_CTXH_CTRL_ADDR, m) +#define HWIO_IPA_CTXH_CTRL_OUT(v) \ + out_dword(HWIO_IPA_CTXH_CTRL_ADDR,v) +#define HWIO_IPA_CTXH_CTRL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_CTXH_CTRL_ADDR,m,v,HWIO_IPA_CTXH_CTRL_IN) +#define HWIO_IPA_CTXH_CTRL_CTXH_LOCK_BMSK 0x80000000 +#define HWIO_IPA_CTXH_CTRL_CTXH_LOCK_SHFT 0x1f +#define HWIO_IPA_CTXH_CTRL_CTXH_LOCK_ACTIVE_BMSK 0x40000000 +#define HWIO_IPA_CTXH_CTRL_CTXH_LOCK_ACTIVE_SHFT 0x1e +#define HWIO_IPA_CTXH_CTRL_CTXH_WR_BLOCK_ON_NOC_ERR_BMSK 0x20000000 +#define HWIO_IPA_CTXH_CTRL_CTXH_WR_BLOCK_ON_NOC_ERR_SHFT 0x1d +#define HWIO_IPA_CTXH_CTRL_CTXH_LOCK_ID_BMSK 0xf +#define HWIO_IPA_CTXH_CTRL_CTXH_LOCK_ID_SHFT 0x0 + +#define HWIO_IPA_CTX_ID_m_CTX_NUM_n_ADDR(m,n) (IPA_DEBUG_REG_BASE + 0x00002000 + 0x100 * (m) + 0x4 * (n)) +#define HWIO_IPA_CTX_ID_m_CTX_NUM_n_PHYS(m,n) (IPA_DEBUG_REG_BASE_PHYS + 0x00002000 + 0x100 * (m) + 0x4 * (n)) +#define HWIO_IPA_CTX_ID_m_CTX_NUM_n_OFFS(m,n) (IPA_DEBUG_REG_BASE_OFFS + 0x00002000 + 0x100 * (m) + 0x4 * (n)) +#define HWIO_IPA_CTX_ID_m_CTX_NUM_n_RMSK 0xffffffff +#define HWIO_IPA_CTX_ID_m_CTX_NUM_n_MAXm 15 +#define HWIO_IPA_CTX_ID_m_CTX_NUM_n_MAXn 63 +#define HWIO_IPA_CTX_ID_m_CTX_NUM_n_ATTR 0x3 +#define HWIO_IPA_CTX_ID_m_CTX_NUM_n_INI2(m,n) \ + in_dword_masked(HWIO_IPA_CTX_ID_m_CTX_NUM_n_ADDR(m,n), HWIO_IPA_CTX_ID_m_CTX_NUM_n_RMSK) +#define HWIO_IPA_CTX_ID_m_CTX_NUM_n_INMI2(m,n,mask) \ + in_dword_masked(HWIO_IPA_CTX_ID_m_CTX_NUM_n_ADDR(m,n), mask) +#define HWIO_IPA_CTX_ID_m_CTX_NUM_n_OUTI2(m,n,val) \ + out_dword(HWIO_IPA_CTX_ID_m_CTX_NUM_n_ADDR(m,n),val) +#define HWIO_IPA_CTX_ID_m_CTX_NUM_n_OUTMI2(m,n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_CTX_ID_m_CTX_NUM_n_ADDR(m,n),mask,val,HWIO_IPA_CTX_ID_m_CTX_NUM_n_INI2(m,n)) +#define HWIO_IPA_CTX_ID_m_CTX_NUM_n_IPA_CTXH_DATA_BMSK 0xffffffff +#define HWIO_IPA_CTX_ID_m_CTX_NUM_n_IPA_CTXH_DATA_SHFT 0x0 + +#define HWIO_IPA_SEG_CTX_ID_m_0_ADDR(m) (IPA_DEBUG_REG_BASE + 0x00003504 + 0x1C * (m)) +#define HWIO_IPA_SEG_CTX_ID_m_0_PHYS(m) (IPA_DEBUG_REG_BASE_PHYS + 0x00003504 + 0x1C * (m)) +#define HWIO_IPA_SEG_CTX_ID_m_0_OFFS(m) (IPA_DEBUG_REG_BASE_OFFS + 0x00003504 + 0x1C * (m)) +#define HWIO_IPA_SEG_CTX_ID_m_0_RMSK 0xffffff1f +#define HWIO_IPA_SEG_CTX_ID_m_0_MAXm 3 +#define HWIO_IPA_SEG_CTX_ID_m_0_ATTR 0x1 +#define HWIO_IPA_SEG_CTX_ID_m_0_INI(m) \ + in_dword_masked(HWIO_IPA_SEG_CTX_ID_m_0_ADDR(m), HWIO_IPA_SEG_CTX_ID_m_0_RMSK) +#define HWIO_IPA_SEG_CTX_ID_m_0_INMI(m,mask) \ + in_dword_masked(HWIO_IPA_SEG_CTX_ID_m_0_ADDR(m), mask) +#define HWIO_IPA_SEG_CTX_ID_m_0_DATA_SECTOR_VALID_LENGTH_BMSK 0xffff0000 +#define HWIO_IPA_SEG_CTX_ID_m_0_DATA_SECTOR_VALID_LENGTH_SHFT 0x10 +#define HWIO_IPA_SEG_CTX_ID_m_0_TRNSEQ_LEN_EXT_BMSK 0xff00 +#define HWIO_IPA_SEG_CTX_ID_m_0_TRNSEQ_LEN_EXT_SHFT 0x8 +#define HWIO_IPA_SEG_CTX_ID_m_0_OPEN_FRAME_BMSK 0x10 +#define HWIO_IPA_SEG_CTX_ID_m_0_OPEN_FRAME_SHFT 0x4 +#define HWIO_IPA_SEG_CTX_ID_m_0_ROUTER_AGGR_FORCE_CLOSE_BMSK 0x8 +#define HWIO_IPA_SEG_CTX_ID_m_0_ROUTER_AGGR_FORCE_CLOSE_SHFT 0x3 +#define HWIO_IPA_SEG_CTX_ID_m_0_LAST_BMSK 0x4 +#define HWIO_IPA_SEG_CTX_ID_m_0_LAST_SHFT 0x2 +#define HWIO_IPA_SEG_CTX_ID_m_0_FILTER_AGGR_FORCE_CLOSE_BMSK 0x2 +#define HWIO_IPA_SEG_CTX_ID_m_0_FILTER_AGGR_FORCE_CLOSE_SHFT 0x1 +#define HWIO_IPA_SEG_CTX_ID_m_0_DMA_TASK_EOF_BMSK 0x1 +#define HWIO_IPA_SEG_CTX_ID_m_0_DMA_TASK_EOF_SHFT 0x0 + +#define HWIO_IPA_SEG_CTX_ID_m_1_ADDR(m) (IPA_DEBUG_REG_BASE + 0x00003508 + 0x1C * (m)) +#define HWIO_IPA_SEG_CTX_ID_m_1_PHYS(m) (IPA_DEBUG_REG_BASE_PHYS + 0x00003508 + 0x1C * (m)) +#define HWIO_IPA_SEG_CTX_ID_m_1_OFFS(m) (IPA_DEBUG_REG_BASE_OFFS + 0x00003508 + 0x1C * (m)) +#define HWIO_IPA_SEG_CTX_ID_m_1_RMSK 0xffffffff +#define HWIO_IPA_SEG_CTX_ID_m_1_MAXm 3 +#define HWIO_IPA_SEG_CTX_ID_m_1_ATTR 0x1 +#define HWIO_IPA_SEG_CTX_ID_m_1_INI(m) \ + in_dword_masked(HWIO_IPA_SEG_CTX_ID_m_1_ADDR(m), HWIO_IPA_SEG_CTX_ID_m_1_RMSK) +#define HWIO_IPA_SEG_CTX_ID_m_1_INMI(m,mask) \ + in_dword_masked(HWIO_IPA_SEG_CTX_ID_m_1_ADDR(m), mask) +#define HWIO_IPA_SEG_CTX_ID_m_1_REVISED_PACKET_LENGTH_BMSK 0xffff0000 +#define HWIO_IPA_SEG_CTX_ID_m_1_REVISED_PACKET_LENGTH_SHFT 0x10 +#define HWIO_IPA_SEG_CTX_ID_m_1_L4_PSEUDO_HDR_CHECKSUM_BMSK 0xffff +#define HWIO_IPA_SEG_CTX_ID_m_1_L4_PSEUDO_HDR_CHECKSUM_SHFT 0x0 + +#define HWIO_IPA_SEG_CTX_ID_m_2_ADDR(m) (IPA_DEBUG_REG_BASE + 0x0000350c + 0x1C * (m)) +#define HWIO_IPA_SEG_CTX_ID_m_2_PHYS(m) (IPA_DEBUG_REG_BASE_PHYS + 0x0000350c + 0x1C * (m)) +#define HWIO_IPA_SEG_CTX_ID_m_2_OFFS(m) (IPA_DEBUG_REG_BASE_OFFS + 0x0000350c + 0x1C * (m)) +#define HWIO_IPA_SEG_CTX_ID_m_2_RMSK 0x7fffff +#define HWIO_IPA_SEG_CTX_ID_m_2_MAXm 3 +#define HWIO_IPA_SEG_CTX_ID_m_2_ATTR 0x1 +#define HWIO_IPA_SEG_CTX_ID_m_2_INI(m) \ + in_dword_masked(HWIO_IPA_SEG_CTX_ID_m_2_ADDR(m), HWIO_IPA_SEG_CTX_ID_m_2_RMSK) +#define HWIO_IPA_SEG_CTX_ID_m_2_INMI(m,mask) \ + in_dword_masked(HWIO_IPA_SEG_CTX_ID_m_2_ADDR(m), mask) +#define HWIO_IPA_SEG_CTX_ID_m_2_TRNSEQ_0_OFFSET_BMSK 0x7fe000 +#define HWIO_IPA_SEG_CTX_ID_m_2_TRNSEQ_0_OFFSET_SHFT 0xd +#define HWIO_IPA_SEG_CTX_ID_m_2_TRNSEQ_0_LENGTH_BMSK 0x1ff8 +#define HWIO_IPA_SEG_CTX_ID_m_2_TRNSEQ_0_LENGTH_SHFT 0x3 +#define HWIO_IPA_SEG_CTX_ID_m_2_TRNSEQ_0_OPCODE_BMSK 0x7 +#define HWIO_IPA_SEG_CTX_ID_m_2_TRNSEQ_0_OPCODE_SHFT 0x0 + +#define HWIO_IPA_SEG_CTX_ID_m_3_ADDR(m) (IPA_DEBUG_REG_BASE + 0x00003510 + 0x1C * (m)) +#define HWIO_IPA_SEG_CTX_ID_m_3_PHYS(m) (IPA_DEBUG_REG_BASE_PHYS + 0x00003510 + 0x1C * (m)) +#define HWIO_IPA_SEG_CTX_ID_m_3_OFFS(m) (IPA_DEBUG_REG_BASE_OFFS + 0x00003510 + 0x1C * (m)) +#define HWIO_IPA_SEG_CTX_ID_m_3_RMSK 0x7fffff +#define HWIO_IPA_SEG_CTX_ID_m_3_MAXm 3 +#define HWIO_IPA_SEG_CTX_ID_m_3_ATTR 0x1 +#define HWIO_IPA_SEG_CTX_ID_m_3_INI(m) \ + in_dword_masked(HWIO_IPA_SEG_CTX_ID_m_3_ADDR(m), HWIO_IPA_SEG_CTX_ID_m_3_RMSK) +#define HWIO_IPA_SEG_CTX_ID_m_3_INMI(m,mask) \ + in_dword_masked(HWIO_IPA_SEG_CTX_ID_m_3_ADDR(m), mask) +#define HWIO_IPA_SEG_CTX_ID_m_3_TRNSEQ_1_OFFSET_BMSK 0x7fe000 +#define HWIO_IPA_SEG_CTX_ID_m_3_TRNSEQ_1_OFFSET_SHFT 0xd +#define HWIO_IPA_SEG_CTX_ID_m_3_TRNSEQ_1_LENGTH_BMSK 0x1ff8 +#define HWIO_IPA_SEG_CTX_ID_m_3_TRNSEQ_1_LENGTH_SHFT 0x3 +#define HWIO_IPA_SEG_CTX_ID_m_3_TRNSEQ_1_OPCODE_BMSK 0x7 +#define HWIO_IPA_SEG_CTX_ID_m_3_TRNSEQ_1_OPCODE_SHFT 0x0 + +#define HWIO_IPA_SEG_CTX_ID_m_4_ADDR(m) (IPA_DEBUG_REG_BASE + 0x00003514 + 0x1C * (m)) +#define HWIO_IPA_SEG_CTX_ID_m_4_PHYS(m) (IPA_DEBUG_REG_BASE_PHYS + 0x00003514 + 0x1C * (m)) +#define HWIO_IPA_SEG_CTX_ID_m_4_OFFS(m) (IPA_DEBUG_REG_BASE_OFFS + 0x00003514 + 0x1C * (m)) +#define HWIO_IPA_SEG_CTX_ID_m_4_RMSK 0x7fffff +#define HWIO_IPA_SEG_CTX_ID_m_4_MAXm 3 +#define HWIO_IPA_SEG_CTX_ID_m_4_ATTR 0x1 +#define HWIO_IPA_SEG_CTX_ID_m_4_INI(m) \ + in_dword_masked(HWIO_IPA_SEG_CTX_ID_m_4_ADDR(m), HWIO_IPA_SEG_CTX_ID_m_4_RMSK) +#define HWIO_IPA_SEG_CTX_ID_m_4_INMI(m,mask) \ + in_dword_masked(HWIO_IPA_SEG_CTX_ID_m_4_ADDR(m), mask) +#define HWIO_IPA_SEG_CTX_ID_m_4_TRNSEQ_2_OFFSET_BMSK 0x7fe000 +#define HWIO_IPA_SEG_CTX_ID_m_4_TRNSEQ_2_OFFSET_SHFT 0xd +#define HWIO_IPA_SEG_CTX_ID_m_4_TRNSEQ_2_LENGTH_BMSK 0x1ff8 +#define HWIO_IPA_SEG_CTX_ID_m_4_TRNSEQ_2_LENGTH_SHFT 0x3 +#define HWIO_IPA_SEG_CTX_ID_m_4_TRNSEQ_2_OPCODE_BMSK 0x7 +#define HWIO_IPA_SEG_CTX_ID_m_4_TRNSEQ_2_OPCODE_SHFT 0x0 + +#define HWIO_IPA_SEG_CTX_ID_m_5_ADDR(m) (IPA_DEBUG_REG_BASE + 0x00003518 + 0x1C * (m)) +#define HWIO_IPA_SEG_CTX_ID_m_5_PHYS(m) (IPA_DEBUG_REG_BASE_PHYS + 0x00003518 + 0x1C * (m)) +#define HWIO_IPA_SEG_CTX_ID_m_5_OFFS(m) (IPA_DEBUG_REG_BASE_OFFS + 0x00003518 + 0x1C * (m)) +#define HWIO_IPA_SEG_CTX_ID_m_5_RMSK 0x7fffff +#define HWIO_IPA_SEG_CTX_ID_m_5_MAXm 3 +#define HWIO_IPA_SEG_CTX_ID_m_5_ATTR 0x1 +#define HWIO_IPA_SEG_CTX_ID_m_5_INI(m) \ + in_dword_masked(HWIO_IPA_SEG_CTX_ID_m_5_ADDR(m), HWIO_IPA_SEG_CTX_ID_m_5_RMSK) +#define HWIO_IPA_SEG_CTX_ID_m_5_INMI(m,mask) \ + in_dword_masked(HWIO_IPA_SEG_CTX_ID_m_5_ADDR(m), mask) +#define HWIO_IPA_SEG_CTX_ID_m_5_TRNSEQ_3_OFFSET_BMSK 0x7fe000 +#define HWIO_IPA_SEG_CTX_ID_m_5_TRNSEQ_3_OFFSET_SHFT 0xd +#define HWIO_IPA_SEG_CTX_ID_m_5_TRNSEQ_3_LENGTH_BMSK 0x1ff8 +#define HWIO_IPA_SEG_CTX_ID_m_5_TRNSEQ_3_LENGTH_SHFT 0x3 +#define HWIO_IPA_SEG_CTX_ID_m_5_TRNSEQ_3_OPCODE_BMSK 0x7 +#define HWIO_IPA_SEG_CTX_ID_m_5_TRNSEQ_3_OPCODE_SHFT 0x0 + +#define HWIO_IPA_SEG_CTX_ID_m_6_ADDR(m) (IPA_DEBUG_REG_BASE + 0x0000351c + 0x1C * (m)) +#define HWIO_IPA_SEG_CTX_ID_m_6_PHYS(m) (IPA_DEBUG_REG_BASE_PHYS + 0x0000351c + 0x1C * (m)) +#define HWIO_IPA_SEG_CTX_ID_m_6_OFFS(m) (IPA_DEBUG_REG_BASE_OFFS + 0x0000351c + 0x1C * (m)) +#define HWIO_IPA_SEG_CTX_ID_m_6_RMSK 0x7fffff +#define HWIO_IPA_SEG_CTX_ID_m_6_MAXm 3 +#define HWIO_IPA_SEG_CTX_ID_m_6_ATTR 0x1 +#define HWIO_IPA_SEG_CTX_ID_m_6_INI(m) \ + in_dword_masked(HWIO_IPA_SEG_CTX_ID_m_6_ADDR(m), HWIO_IPA_SEG_CTX_ID_m_6_RMSK) +#define HWIO_IPA_SEG_CTX_ID_m_6_INMI(m,mask) \ + in_dword_masked(HWIO_IPA_SEG_CTX_ID_m_6_ADDR(m), mask) +#define HWIO_IPA_SEG_CTX_ID_m_6_TRNSEQ_4_OFFSET_BMSK 0x7fe000 +#define HWIO_IPA_SEG_CTX_ID_m_6_TRNSEQ_4_OFFSET_SHFT 0xd +#define HWIO_IPA_SEG_CTX_ID_m_6_TRNSEQ_4_LENGTH_BMSK 0x1ff8 +#define HWIO_IPA_SEG_CTX_ID_m_6_TRNSEQ_4_LENGTH_SHFT 0x3 +#define HWIO_IPA_SEG_CTX_ID_m_6_TRNSEQ_4_OPCODE_BMSK 0x7 +#define HWIO_IPA_SEG_CTX_ID_m_6_TRNSEQ_4_OPCODE_SHFT 0x0 + +/*---------------------------------------------------------------------------- + * MODULE: IPA_CFG + *--------------------------------------------------------------------------*/ + +#define IPA_CFG_REG_BASE (IPA_0_IPA_WRAPPER_BASE + 0x00140000) +#define IPA_CFG_REG_BASE_PHYS (IPA_0_IPA_WRAPPER_BASE_PHYS + 0x00140000) +#define IPA_CFG_REG_BASE_OFFS 0x00140000 + +#define HWIO_IPA_FLAVOR_0_ADDR (IPA_CFG_REG_BASE + 0x00000000) +#define HWIO_IPA_FLAVOR_0_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000000) +#define HWIO_IPA_FLAVOR_0_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000000) +#define HWIO_IPA_FLAVOR_0_RMSK 0xffffffff +#define HWIO_IPA_FLAVOR_0_ATTR 0x1 +#define HWIO_IPA_FLAVOR_0_IN \ + in_dword_masked(HWIO_IPA_FLAVOR_0_ADDR, HWIO_IPA_FLAVOR_0_RMSK) +#define HWIO_IPA_FLAVOR_0_INM(m) \ + in_dword_masked(HWIO_IPA_FLAVOR_0_ADDR, m) +#define HWIO_IPA_FLAVOR_0_IPA_PROD_LOWEST_BMSK 0xff000000 +#define HWIO_IPA_FLAVOR_0_IPA_PROD_LOWEST_SHFT 0x18 +#define HWIO_IPA_FLAVOR_0_IPA_PROD_PIPES_BMSK 0xff0000 +#define HWIO_IPA_FLAVOR_0_IPA_PROD_PIPES_SHFT 0x10 +#define HWIO_IPA_FLAVOR_0_IPA_CONS_PIPES_BMSK 0xff00 +#define HWIO_IPA_FLAVOR_0_IPA_CONS_PIPES_SHFT 0x8 +#define HWIO_IPA_FLAVOR_0_IPA_PIPES_BMSK 0xff +#define HWIO_IPA_FLAVOR_0_IPA_PIPES_SHFT 0x0 + +#define HWIO_IPA_FLAVOR_1_ADDR (IPA_CFG_REG_BASE + 0x00000004) +#define HWIO_IPA_FLAVOR_1_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000004) +#define HWIO_IPA_FLAVOR_1_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000004) +#define HWIO_IPA_FLAVOR_1_RMSK 0x1fffdf3f +#define HWIO_IPA_FLAVOR_1_ATTR 0x1 +#define HWIO_IPA_FLAVOR_1_IN \ + in_dword_masked(HWIO_IPA_FLAVOR_1_ADDR, HWIO_IPA_FLAVOR_1_RMSK) +#define HWIO_IPA_FLAVOR_1_INM(m) \ + in_dword_masked(HWIO_IPA_FLAVOR_1_ADDR, m) +#define HWIO_IPA_FLAVOR_1_D_DCPH_ENGINE_NUM_BMSK 0x18000000 +#define HWIO_IPA_FLAVOR_1_D_DCPH_ENGINE_NUM_SHFT 0x1b +#define HWIO_IPA_FLAVOR_1_PCIE_PATH_EN_BMSK 0x4000000 +#define HWIO_IPA_FLAVOR_1_PCIE_PATH_EN_SHFT 0x1a +#define HWIO_IPA_FLAVOR_1_GSI_SLAVEWAY_EN_BMSK 0x2000000 +#define HWIO_IPA_FLAVOR_1_GSI_SLAVEWAY_EN_SHFT 0x19 +#define HWIO_IPA_FLAVOR_1_RX_UC_HANDLER_EN_BMSK 0x1000000 +#define HWIO_IPA_FLAVOR_1_RX_UC_HANDLER_EN_SHFT 0x18 +#define HWIO_IPA_FLAVOR_1_DUAL_TX_EN_BMSK 0x800000 +#define HWIO_IPA_FLAVOR_1_DUAL_TX_EN_SHFT 0x17 +#define HWIO_IPA_FLAVOR_1_QMB1_EN_BMSK 0x400000 +#define HWIO_IPA_FLAVOR_1_QMB1_EN_SHFT 0x16 +#define HWIO_IPA_FLAVOR_1_QMB1_SLAVEWAY_EN_BMSK 0x200000 +#define HWIO_IPA_FLAVOR_1_QMB1_SLAVEWAY_EN_SHFT 0x15 +#define HWIO_IPA_FLAVOR_1_QMB0_SLAVEWAY_EN_BMSK 0x100000 +#define HWIO_IPA_FLAVOR_1_QMB0_SLAVEWAY_EN_SHFT 0x14 +#define HWIO_IPA_FLAVOR_1_CONS_DPL_EN_BMSK 0x80000 +#define HWIO_IPA_FLAVOR_1_CONS_DPL_EN_SHFT 0x13 +#define HWIO_IPA_FLAVOR_1_CPR_EN_BMSK 0x40000 +#define HWIO_IPA_FLAVOR_1_CPR_EN_SHFT 0x12 +#define HWIO_IPA_FLAVOR_1_UC_EN_BMSK 0x20000 +#define HWIO_IPA_FLAVOR_1_UC_EN_SHFT 0x11 +#define HWIO_IPA_FLAVOR_1_VMIDMT_EN_BMSK 0x10000 +#define HWIO_IPA_FLAVOR_1_VMIDMT_EN_SHFT 0x10 +#define HWIO_IPA_FLAVOR_1_NAT_ACL_EN_BMSK 0x8000 +#define HWIO_IPA_FLAVOR_1_NAT_ACL_EN_SHFT 0xf +#define HWIO_IPA_FLAVOR_1_FILTER_ROUTER_CACHE_GEN_BMSK 0x4000 +#define HWIO_IPA_FLAVOR_1_FILTER_ROUTER_CACHE_GEN_SHFT 0xe +#define HWIO_IPA_FLAVOR_1_H_DCPH_EN_BMSK 0x1000 +#define HWIO_IPA_FLAVOR_1_H_DCPH_EN_SHFT 0xc +#define HWIO_IPA_FLAVOR_1_D_DCPH_EN_BMSK 0x800 +#define HWIO_IPA_FLAVOR_1_D_DCPH_EN_SHFT 0xb +#define HWIO_IPA_FLAVOR_1_D_DCPH_2_EN_BMSK 0x400 +#define HWIO_IPA_FLAVOR_1_D_DCPH_2_EN_SHFT 0xa +#define HWIO_IPA_FLAVOR_1_UCP_EN_BMSK 0x200 +#define HWIO_IPA_FLAVOR_1_UCP_EN_SHFT 0x9 +#define HWIO_IPA_FLAVOR_1_MBIM_DEAGG_EN_BMSK 0x100 +#define HWIO_IPA_FLAVOR_1_MBIM_DEAGG_EN_SHFT 0x8 +#define HWIO_IPA_FLAVOR_1_CTX_N_BMSK 0x3f +#define HWIO_IPA_FLAVOR_1_CTX_N_SHFT 0x0 + +#define HWIO_IPA_FLAVOR_2_ADDR (IPA_CFG_REG_BASE + 0x00000008) +#define HWIO_IPA_FLAVOR_2_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000008) +#define HWIO_IPA_FLAVOR_2_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000008) +#define HWIO_IPA_FLAVOR_2_RMSK 0x3f3f3f3f +#define HWIO_IPA_FLAVOR_2_ATTR 0x1 +#define HWIO_IPA_FLAVOR_2_IN \ + in_dword_masked(HWIO_IPA_FLAVOR_2_ADDR, HWIO_IPA_FLAVOR_2_RMSK) +#define HWIO_IPA_FLAVOR_2_INM(m) \ + in_dword_masked(HWIO_IPA_FLAVOR_2_ADDR, m) +#define HWIO_IPA_FLAVOR_2_QMB1_OUTST_RD_BMSK 0x3f000000 +#define HWIO_IPA_FLAVOR_2_QMB1_OUTST_RD_SHFT 0x18 +#define HWIO_IPA_FLAVOR_2_QMB1_OUTST_WR_BMSK 0x3f0000 +#define HWIO_IPA_FLAVOR_2_QMB1_OUTST_WR_SHFT 0x10 +#define HWIO_IPA_FLAVOR_2_QMB0_OUTST_RD_BMSK 0x3f00 +#define HWIO_IPA_FLAVOR_2_QMB0_OUTST_RD_SHFT 0x8 +#define HWIO_IPA_FLAVOR_2_QMB0_OUTST_WR_BMSK 0x3f +#define HWIO_IPA_FLAVOR_2_QMB0_OUTST_WR_SHFT 0x0 + +#define HWIO_IPA_FLAVOR_3_ADDR (IPA_CFG_REG_BASE + 0x0000000c) +#define HWIO_IPA_FLAVOR_3_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000000c) +#define HWIO_IPA_FLAVOR_3_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000000c) +#define HWIO_IPA_FLAVOR_3_RMSK 0xfffffff +#define HWIO_IPA_FLAVOR_3_ATTR 0x1 +#define HWIO_IPA_FLAVOR_3_IN \ + in_dword_masked(HWIO_IPA_FLAVOR_3_ADDR, HWIO_IPA_FLAVOR_3_RMSK) +#define HWIO_IPA_FLAVOR_3_INM(m) \ + in_dword_masked(HWIO_IPA_FLAVOR_3_ADDR, m) +#define HWIO_IPA_FLAVOR_3_RSRC_GRP_DST_NUM_DRBIP_BMSK 0xf000000 +#define HWIO_IPA_FLAVOR_3_RSRC_GRP_DST_NUM_DRBIP_SHFT 0x18 +#define HWIO_IPA_FLAVOR_3_PKT_CTX_SIZE_BMSK 0xff0000 +#define HWIO_IPA_FLAVOR_3_PKT_CTX_SIZE_SHFT 0x10 +#define HWIO_IPA_FLAVOR_3_RSRC_GRP_DST_NUM_UC_BMSK 0xf000 +#define HWIO_IPA_FLAVOR_3_RSRC_GRP_DST_NUM_UC_SHFT 0xc +#define HWIO_IPA_FLAVOR_3_RSRC_GRP_DST_NUM_WO_UC_N_DRBIP_BMSK 0xf00 +#define HWIO_IPA_FLAVOR_3_RSRC_GRP_DST_NUM_WO_UC_N_DRBIP_SHFT 0x8 +#define HWIO_IPA_FLAVOR_3_RSRC_GRP_SRC_NUM_UC_BMSK 0xf0 +#define HWIO_IPA_FLAVOR_3_RSRC_GRP_SRC_NUM_UC_SHFT 0x4 +#define HWIO_IPA_FLAVOR_3_RSRC_GRP_SRC_NUM_WOUT_UC_BMSK 0xf +#define HWIO_IPA_FLAVOR_3_RSRC_GRP_SRC_NUM_WOUT_UC_SHFT 0x0 + +#define HWIO_IPA_FLAVOR_4_ADDR (IPA_CFG_REG_BASE + 0x00000010) +#define HWIO_IPA_FLAVOR_4_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000010) +#define HWIO_IPA_FLAVOR_4_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000010) +#define HWIO_IPA_FLAVOR_4_RMSK 0x30ffffff +#define HWIO_IPA_FLAVOR_4_ATTR 0x1 +#define HWIO_IPA_FLAVOR_4_IN \ + in_dword_masked(HWIO_IPA_FLAVOR_4_ADDR, HWIO_IPA_FLAVOR_4_RMSK) +#define HWIO_IPA_FLAVOR_4_INM(m) \ + in_dword_masked(HWIO_IPA_FLAVOR_4_ADDR, m) +#define HWIO_IPA_FLAVOR_4_FRAG_TABLES_NUM_BMSK 0x30000000 +#define HWIO_IPA_FLAVOR_4_FRAG_TABLES_NUM_SHFT 0x1c +#define HWIO_IPA_FLAVOR_4_MBIM_AGG_PIPES_BMSK 0xf00000 +#define HWIO_IPA_FLAVOR_4_MBIM_AGG_PIPES_SHFT 0x14 +#define HWIO_IPA_FLAVOR_4_BEARER_INIT_CTX_NUM_BMSK 0xf0000 +#define HWIO_IPA_FLAVOR_4_BEARER_INIT_CTX_NUM_SHFT 0x10 +#define HWIO_IPA_FLAVOR_4_GENERIC_DEAGG_PIPES_BMSK 0xff00 +#define HWIO_IPA_FLAVOR_4_GENERIC_DEAGG_PIPES_SHFT 0x8 +#define HWIO_IPA_FLAVOR_4_GENERIC_AGG_PIPES_BMSK 0xff +#define HWIO_IPA_FLAVOR_4_GENERIC_AGG_PIPES_SHFT 0x0 + +#define HWIO_IPA_FLAVOR_5_ADDR (IPA_CFG_REG_BASE + 0x00000014) +#define HWIO_IPA_FLAVOR_5_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000014) +#define HWIO_IPA_FLAVOR_5_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000014) +#define HWIO_IPA_FLAVOR_5_RMSK 0x3fff3f3f +#define HWIO_IPA_FLAVOR_5_ATTR 0x1 +#define HWIO_IPA_FLAVOR_5_IN \ + in_dword_masked(HWIO_IPA_FLAVOR_5_ADDR, HWIO_IPA_FLAVOR_5_RMSK) +#define HWIO_IPA_FLAVOR_5_INM(m) \ + in_dword_masked(HWIO_IPA_FLAVOR_5_ADDR, m) +#define HWIO_IPA_FLAVOR_5_RX_HPS_CMDQ_Q_DEPTH_BMSK 0x3f000000 +#define HWIO_IPA_FLAVOR_5_RX_HPS_CMDQ_Q_DEPTH_SHFT 0x18 +#define HWIO_IPA_FLAVOR_5_GSI_NUM_EES_BMSK 0xf00000 +#define HWIO_IPA_FLAVOR_5_GSI_NUM_EES_SHFT 0x14 +#define HWIO_IPA_FLAVOR_5_IPA_NUM_EES_BMSK 0xf0000 +#define HWIO_IPA_FLAVOR_5_IPA_NUM_EES_SHFT 0x10 +#define HWIO_IPA_FLAVOR_5_PRODUCER_ACK_MNGR_DB_DEPTH_BMSK 0x3f00 +#define HWIO_IPA_FLAVOR_5_PRODUCER_ACK_MNGR_DB_DEPTH_SHFT 0x8 +#define HWIO_IPA_FLAVOR_5_CONSUMER_ACK_MNGR_DB_DEPTH_BMSK 0x3f +#define HWIO_IPA_FLAVOR_5_CONSUMER_ACK_MNGR_DB_DEPTH_SHFT 0x0 + +#define HWIO_IPA_FLAVOR_6_ADDR (IPA_CFG_REG_BASE + 0x00000018) +#define HWIO_IPA_FLAVOR_6_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000018) +#define HWIO_IPA_FLAVOR_6_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000018) +#define HWIO_IPA_FLAVOR_6_RMSK 0x3fff3fff +#define HWIO_IPA_FLAVOR_6_ATTR 0x1 +#define HWIO_IPA_FLAVOR_6_IN \ + in_dword_masked(HWIO_IPA_FLAVOR_6_ADDR, HWIO_IPA_FLAVOR_6_RMSK) +#define HWIO_IPA_FLAVOR_6_INM(m) \ + in_dword_masked(HWIO_IPA_FLAVOR_6_ADDR, m) +#define HWIO_IPA_FLAVOR_6_DATA_SECTORS_BMSK 0x3f000000 +#define HWIO_IPA_FLAVOR_6_DATA_SECTORS_SHFT 0x18 +#define HWIO_IPA_FLAVOR_6_DATA_DESCRIPTOR_BUFFERS_BMSK 0xff0000 +#define HWIO_IPA_FLAVOR_6_DATA_DESCRIPTOR_BUFFERS_SHFT 0x10 +#define HWIO_IPA_FLAVOR_6_DATA_DESCRIPTOR_LISTS_BMSK 0x3f00 +#define HWIO_IPA_FLAVOR_6_DATA_DESCRIPTOR_LISTS_SHFT 0x8 +#define HWIO_IPA_FLAVOR_6_DPS_DMAR_NUM_BMSK 0xf0 +#define HWIO_IPA_FLAVOR_6_DPS_DMAR_NUM_SHFT 0x4 +#define HWIO_IPA_FLAVOR_6_HPS_DMAR_NUM_BMSK 0xf +#define HWIO_IPA_FLAVOR_6_HPS_DMAR_NUM_SHFT 0x0 + +#define HWIO_IPA_FLAVOR_7_ADDR (IPA_CFG_REG_BASE + 0x0000001c) +#define HWIO_IPA_FLAVOR_7_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000001c) +#define HWIO_IPA_FLAVOR_7_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000001c) +#define HWIO_IPA_FLAVOR_7_RMSK 0x7fff03ff +#define HWIO_IPA_FLAVOR_7_ATTR 0x1 +#define HWIO_IPA_FLAVOR_7_IN \ + in_dword_masked(HWIO_IPA_FLAVOR_7_ADDR, HWIO_IPA_FLAVOR_7_RMSK) +#define HWIO_IPA_FLAVOR_7_INM(m) \ + in_dword_masked(HWIO_IPA_FLAVOR_7_ADDR, m) +#define HWIO_IPA_FLAVOR_7_COAL_VP_NUM_BMSK 0x7c000000 +#define HWIO_IPA_FLAVOR_7_COAL_VP_NUM_SHFT 0x1a +#define HWIO_IPA_FLAVOR_7_AOS_ENTRY_NUM_BMSK 0x3ff0000 +#define HWIO_IPA_FLAVOR_7_AOS_ENTRY_NUM_SHFT 0x10 +#define HWIO_IPA_FLAVOR_7_TLV_ENTRY_NUM_BMSK 0x3ff +#define HWIO_IPA_FLAVOR_7_TLV_ENTRY_NUM_SHFT 0x0 + +#define HWIO_IPA_FLAVOR_8_ADDR (IPA_CFG_REG_BASE + 0x00000020) +#define HWIO_IPA_FLAVOR_8_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000020) +#define HWIO_IPA_FLAVOR_8_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000020) +#define HWIO_IPA_FLAVOR_8_RMSK 0xff +#define HWIO_IPA_FLAVOR_8_ATTR 0x1 +#define HWIO_IPA_FLAVOR_8_IN \ + in_dword_masked(HWIO_IPA_FLAVOR_8_ADDR, HWIO_IPA_FLAVOR_8_RMSK) +#define HWIO_IPA_FLAVOR_8_INM(m) \ + in_dword_masked(HWIO_IPA_FLAVOR_8_ADDR, m) +#define HWIO_IPA_FLAVOR_8_MULTI_DRBIP_DCPH_ENGINE_NUM_BMSK 0xf0 +#define HWIO_IPA_FLAVOR_8_MULTI_DRBIP_DCPH_ENGINE_NUM_SHFT 0x4 +#define HWIO_IPA_FLAVOR_8_MULTI_DRBIP_DMAR_ENGINE_NUM_BMSK 0xf +#define HWIO_IPA_FLAVOR_8_MULTI_DRBIP_DMAR_ENGINE_NUM_SHFT 0x0 + +#define HWIO_IPA_FLAVOR_9_ADDR (IPA_CFG_REG_BASE + 0x00000024) +#define HWIO_IPA_FLAVOR_9_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000024) +#define HWIO_IPA_FLAVOR_9_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000024) +#define HWIO_IPA_FLAVOR_9_RMSK 0xffffff +#define HWIO_IPA_FLAVOR_9_ATTR 0x1 +#define HWIO_IPA_FLAVOR_9_IN \ + in_dword_masked(HWIO_IPA_FLAVOR_9_ADDR, HWIO_IPA_FLAVOR_9_RMSK) +#define HWIO_IPA_FLAVOR_9_INM(m) \ + in_dword_masked(HWIO_IPA_FLAVOR_9_ADDR, m) +#define HWIO_IPA_FLAVOR_9_IPA_MAX_SUPPORTED_TSP_PRODUCERS_BMSK 0xff0000 +#define HWIO_IPA_FLAVOR_9_IPA_MAX_SUPPORTED_TSP_PRODUCERS_SHFT 0x10 +#define HWIO_IPA_FLAVOR_9_IPA_MAX_SUPPORTED_TSP_EGRESS_TCS_BMSK 0xff00 +#define HWIO_IPA_FLAVOR_9_IPA_MAX_SUPPORTED_TSP_EGRESS_TCS_SHFT 0x8 +#define HWIO_IPA_FLAVOR_9_IPA_MAX_SUPPORTED_TSP_INGRESS_TCS_BMSK 0xff +#define HWIO_IPA_FLAVOR_9_IPA_MAX_SUPPORTED_TSP_INGRESS_TCS_SHFT 0x0 + +#define HWIO_IPA_FLAVOR_10_ADDR (IPA_CFG_REG_BASE + 0x00000028) +#define HWIO_IPA_FLAVOR_10_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000028) +#define HWIO_IPA_FLAVOR_10_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000028) +#define HWIO_IPA_FLAVOR_10_RMSK 0xffff +#define HWIO_IPA_FLAVOR_10_ATTR 0x1 +#define HWIO_IPA_FLAVOR_10_IN \ + in_dword_masked(HWIO_IPA_FLAVOR_10_ADDR, HWIO_IPA_FLAVOR_10_RMSK) +#define HWIO_IPA_FLAVOR_10_INM(m) \ + in_dword_masked(HWIO_IPA_FLAVOR_10_ADDR, m) +#define HWIO_IPA_FLAVOR_10_IPA_MAX_SUPPORTED_QMNGR_BLOCKS_BMSK 0xffff +#define HWIO_IPA_FLAVOR_10_IPA_MAX_SUPPORTED_QMNGR_BLOCKS_SHFT 0x0 + +#define HWIO_IPA_COMP_HW_VERSION_ADDR (IPA_CFG_REG_BASE + 0x00000040) +#define HWIO_IPA_COMP_HW_VERSION_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000040) +#define HWIO_IPA_COMP_HW_VERSION_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000040) +#define HWIO_IPA_COMP_HW_VERSION_RMSK 0xffffffff +#define HWIO_IPA_COMP_HW_VERSION_ATTR 0x1 +#define HWIO_IPA_COMP_HW_VERSION_IN \ + in_dword_masked(HWIO_IPA_COMP_HW_VERSION_ADDR, HWIO_IPA_COMP_HW_VERSION_RMSK) +#define HWIO_IPA_COMP_HW_VERSION_INM(m) \ + in_dword_masked(HWIO_IPA_COMP_HW_VERSION_ADDR, m) +#define HWIO_IPA_COMP_HW_VERSION_MAJOR_BMSK 0xf0000000 +#define HWIO_IPA_COMP_HW_VERSION_MAJOR_SHFT 0x1c +#define HWIO_IPA_COMP_HW_VERSION_MINOR_BMSK 0xfff0000 +#define HWIO_IPA_COMP_HW_VERSION_MINOR_SHFT 0x10 +#define HWIO_IPA_COMP_HW_VERSION_STEP_BMSK 0xffff +#define HWIO_IPA_COMP_HW_VERSION_STEP_SHFT 0x0 + +#define HWIO_IPA_VERSION_ADDR (IPA_CFG_REG_BASE + 0x00000044) +#define HWIO_IPA_VERSION_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000044) +#define HWIO_IPA_VERSION_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000044) +#define HWIO_IPA_VERSION_RMSK 0xffffffff +#define HWIO_IPA_VERSION_ATTR 0x1 +#define HWIO_IPA_VERSION_IN \ + in_dword_masked(HWIO_IPA_VERSION_ADDR, HWIO_IPA_VERSION_RMSK) +#define HWIO_IPA_VERSION_INM(m) \ + in_dword_masked(HWIO_IPA_VERSION_ADDR, m) +#define HWIO_IPA_VERSION_IPA_R_REV_BMSK 0xffffffff +#define HWIO_IPA_VERSION_IPA_R_REV_SHFT 0x0 + +#define HWIO_IPA_COMP_CFG_ADDR (IPA_CFG_REG_BASE + 0x00000048) +#define HWIO_IPA_COMP_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000048) +#define HWIO_IPA_COMP_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000048) +#define HWIO_IPA_COMP_CFG_RMSK 0xcff9ffef +#define HWIO_IPA_COMP_CFG_ATTR 0x3 +#define HWIO_IPA_COMP_CFG_IN \ + in_dword_masked(HWIO_IPA_COMP_CFG_ADDR, HWIO_IPA_COMP_CFG_RMSK) +#define HWIO_IPA_COMP_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_COMP_CFG_ADDR, m) +#define HWIO_IPA_COMP_CFG_OUT(v) \ + out_dword(HWIO_IPA_COMP_CFG_ADDR,v) +#define HWIO_IPA_COMP_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_COMP_CFG_ADDR,m,v,HWIO_IPA_COMP_CFG_IN) +#define HWIO_IPA_COMP_CFG_GEN_QMB_0_DYNAMIC_ASIZE_BMSK 0x80000000 +#define HWIO_IPA_COMP_CFG_GEN_QMB_0_DYNAMIC_ASIZE_SHFT 0x1f +#define HWIO_IPA_COMP_CFG_GEN_QMB_1_DYNAMIC_ASIZE_BMSK 0x40000000 +#define HWIO_IPA_COMP_CFG_GEN_QMB_1_DYNAMIC_ASIZE_SHFT 0x1e +#define HWIO_IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_BMSK 0xfc00000 +#define HWIO_IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_SHFT 0x16 +#define HWIO_IPA_COMP_CFG_GSI_IF_OUT_OF_BUF_STOP_RESET_MASK_ENABLE_BMSK 0x200000 +#define HWIO_IPA_COMP_CFG_GSI_IF_OUT_OF_BUF_STOP_RESET_MASK_ENABLE_SHFT 0x15 +#define HWIO_IPA_COMP_CFG_GENQMB_AOOOWR_BMSK 0x100000 +#define HWIO_IPA_COMP_CFG_GENQMB_AOOOWR_SHFT 0x14 +#define HWIO_IPA_COMP_CFG_QMB_RAM_RD_CACHE_DISABLE_BMSK 0x80000 +#define HWIO_IPA_COMP_CFG_QMB_RAM_RD_CACHE_DISABLE_SHFT 0x13 +#define HWIO_IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_GLOBAL_EN_BMSK 0x10000 +#define HWIO_IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_GLOBAL_EN_SHFT 0x10 +#define HWIO_IPA_COMP_CFG_GSI_MULTI_AXI_MASTERS_DIS_BMSK 0x8000 +#define HWIO_IPA_COMP_CFG_GSI_MULTI_AXI_MASTERS_DIS_SHFT 0xf +#define HWIO_IPA_COMP_CFG_GSI_SNOC_CNOC_LOOP_PROTECTION_DISABLE_BMSK 0x4000 +#define HWIO_IPA_COMP_CFG_GSI_SNOC_CNOC_LOOP_PROTECTION_DISABLE_SHFT 0xe +#define HWIO_IPA_COMP_CFG_GEN_QMB_0_SNOC_CNOC_LOOP_PROTECTION_DISABLE_BMSK 0x2000 +#define HWIO_IPA_COMP_CFG_GEN_QMB_0_SNOC_CNOC_LOOP_PROTECTION_DISABLE_SHFT 0xd +#define HWIO_IPA_COMP_CFG_GEN_QMB_1_MULTI_INORDER_WR_DIS_BMSK 0x1000 +#define HWIO_IPA_COMP_CFG_GEN_QMB_1_MULTI_INORDER_WR_DIS_SHFT 0xc +#define HWIO_IPA_COMP_CFG_GEN_QMB_0_MULTI_INORDER_WR_DIS_BMSK 0x800 +#define HWIO_IPA_COMP_CFG_GEN_QMB_0_MULTI_INORDER_WR_DIS_SHFT 0xb +#define HWIO_IPA_COMP_CFG_GEN_QMB_1_MULTI_INORDER_RD_DIS_BMSK 0x400 +#define HWIO_IPA_COMP_CFG_GEN_QMB_1_MULTI_INORDER_RD_DIS_SHFT 0xa +#define HWIO_IPA_COMP_CFG_GEN_QMB_0_MULTI_INORDER_RD_DIS_BMSK 0x200 +#define HWIO_IPA_COMP_CFG_GEN_QMB_0_MULTI_INORDER_RD_DIS_SHFT 0x9 +#define HWIO_IPA_COMP_CFG_GSI_MULTI_INORDER_WR_DIS_BMSK 0x100 +#define HWIO_IPA_COMP_CFG_GSI_MULTI_INORDER_WR_DIS_SHFT 0x8 +#define HWIO_IPA_COMP_CFG_GSI_MULTI_INORDER_RD_DIS_BMSK 0x80 +#define HWIO_IPA_COMP_CFG_GSI_MULTI_INORDER_RD_DIS_SHFT 0x7 +#define HWIO_IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_PROD_EN_BMSK 0x40 +#define HWIO_IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_PROD_EN_SHFT 0x6 +#define HWIO_IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_CONS_EN_BMSK 0x20 +#define HWIO_IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_CONS_EN_SHFT 0x5 +#define HWIO_IPA_COMP_CFG_GEN_QMB_1_SNOC_BYPASS_DIS_BMSK 0x8 +#define HWIO_IPA_COMP_CFG_GEN_QMB_1_SNOC_BYPASS_DIS_SHFT 0x3 +#define HWIO_IPA_COMP_CFG_GEN_QMB_0_SNOC_BYPASS_DIS_BMSK 0x4 +#define HWIO_IPA_COMP_CFG_GEN_QMB_0_SNOC_BYPASS_DIS_SHFT 0x2 +#define HWIO_IPA_COMP_CFG_GSI_SNOC_BYPASS_DIS_BMSK 0x2 +#define HWIO_IPA_COMP_CFG_GSI_SNOC_BYPASS_DIS_SHFT 0x1 +#define HWIO_IPA_COMP_CFG_RAM_ARB_PRIORITY_CLIENT_SAMP_FIX_DISABLE_BMSK 0x1 +#define HWIO_IPA_COMP_CFG_RAM_ARB_PRIORITY_CLIENT_SAMP_FIX_DISABLE_SHFT 0x0 + +#define HWIO_IPA_CLKON_CFG_SPECIAL_ADDR (IPA_CFG_REG_BASE + 0x000004f4) +#define HWIO_IPA_CLKON_CFG_SPECIAL_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000004f4) +#define HWIO_IPA_CLKON_CFG_SPECIAL_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000004f4) +#define HWIO_IPA_CLKON_CFG_SPECIAL_RMSK 0x1 +#define HWIO_IPA_CLKON_CFG_SPECIAL_ATTR 0x3 +#define HWIO_IPA_CLKON_CFG_SPECIAL_IN \ + in_dword_masked(HWIO_IPA_CLKON_CFG_SPECIAL_ADDR, HWIO_IPA_CLKON_CFG_SPECIAL_RMSK) +#define HWIO_IPA_CLKON_CFG_SPECIAL_INM(m) \ + in_dword_masked(HWIO_IPA_CLKON_CFG_SPECIAL_ADDR, m) +#define HWIO_IPA_CLKON_CFG_SPECIAL_OUT(v) \ + out_dword(HWIO_IPA_CLKON_CFG_SPECIAL_ADDR,v) +#define HWIO_IPA_CLKON_CFG_SPECIAL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_CLKON_CFG_SPECIAL_ADDR,m,v,HWIO_IPA_CLKON_CFG_SPECIAL_IN) +#define HWIO_IPA_CLKON_CFG_SPECIAL_CGC_OPEN_TPDM_CMB_BMSK 0x1 +#define HWIO_IPA_CLKON_CFG_SPECIAL_CGC_OPEN_TPDM_CMB_SHFT 0x0 + +#define HWIO_IPA_CLKON_CFG_1_ADDR (IPA_CFG_REG_BASE + 0x0000004c) +#define HWIO_IPA_CLKON_CFG_1_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000004c) +#define HWIO_IPA_CLKON_CFG_1_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000004c) +#define HWIO_IPA_CLKON_CFG_1_RMSK 0xf +#define HWIO_IPA_CLKON_CFG_1_ATTR 0x3 +#define HWIO_IPA_CLKON_CFG_1_IN \ + in_dword_masked(HWIO_IPA_CLKON_CFG_1_ADDR, HWIO_IPA_CLKON_CFG_1_RMSK) +#define HWIO_IPA_CLKON_CFG_1_INM(m) \ + in_dword_masked(HWIO_IPA_CLKON_CFG_1_ADDR, m) +#define HWIO_IPA_CLKON_CFG_1_OUT(v) \ + out_dword(HWIO_IPA_CLKON_CFG_1_ADDR,v) +#define HWIO_IPA_CLKON_CFG_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_CLKON_CFG_1_ADDR,m,v,HWIO_IPA_CLKON_CFG_1_IN) +#define HWIO_IPA_CLKON_CFG_1_CGC_OPEN_PROD_DPL_FIFO_BMSK 0x8 +#define HWIO_IPA_CLKON_CFG_1_CGC_OPEN_PROD_DPL_FIFO_SHFT 0x3 +#define HWIO_IPA_CLKON_CFG_1_CGC_OPEN_IPA_TSP_BMSK 0x4 +#define HWIO_IPA_CLKON_CFG_1_CGC_OPEN_IPA_TSP_SHFT 0x2 +#define HWIO_IPA_CLKON_CFG_1_CGC_OPEN_IPA_XPU_WRAPPER_BMSK 0x2 +#define HWIO_IPA_CLKON_CFG_1_CGC_OPEN_IPA_XPU_WRAPPER_SHFT 0x1 +#define HWIO_IPA_CLKON_CFG_1_CGC_OPEN_IPA_CORE_CLK_PHASE_BMSK 0x1 +#define HWIO_IPA_CLKON_CFG_1_CGC_OPEN_IPA_CORE_CLK_PHASE_SHFT 0x0 + +#define HWIO_IPA_CLKON_CFG_ADDR (IPA_CFG_REG_BASE + 0x00000050) +#define HWIO_IPA_CLKON_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000050) +#define HWIO_IPA_CLKON_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000050) +#define HWIO_IPA_CLKON_CFG_RMSK 0xfffdffff +#define HWIO_IPA_CLKON_CFG_ATTR 0x3 +#define HWIO_IPA_CLKON_CFG_IN \ + in_dword_masked(HWIO_IPA_CLKON_CFG_ADDR, HWIO_IPA_CLKON_CFG_RMSK) +#define HWIO_IPA_CLKON_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_CLKON_CFG_ADDR, m) +#define HWIO_IPA_CLKON_CFG_OUT(v) \ + out_dword(HWIO_IPA_CLKON_CFG_ADDR,v) +#define HWIO_IPA_CLKON_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_CLKON_CFG_ADDR,m,v,HWIO_IPA_CLKON_CFG_IN) +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_DRBIP_BMSK 0x80000000 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_DRBIP_SHFT 0x1f +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_CONS_DPL_FIFO_BMSK 0x40000000 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_CONS_DPL_FIFO_SHFT 0x1e +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_GLOBAL_2X_CLK_BMSK 0x20000000 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_GLOBAL_2X_CLK_SHFT 0x1d +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_GLOBAL_BMSK 0x10000000 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_GLOBAL_SHFT 0x1c +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_GSI_IF_BMSK 0x8000000 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_GSI_IF_SHFT 0x1b +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_WEIGHT_ARB_BMSK 0x4000000 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_WEIGHT_ARB_SHFT 0x1a +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_QMB_BMSK 0x2000000 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_QMB_SHFT 0x19 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_RAM_SLAVEWAY_BMSK 0x1000000 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_RAM_SLAVEWAY_SHFT 0x18 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_AGGR_WRAPPER_BMSK 0x800000 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_AGGR_WRAPPER_SHFT 0x17 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_QSB2AXI_CMDQ_L_BMSK 0x400000 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_QSB2AXI_CMDQ_L_SHFT 0x16 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_FNR_BMSK 0x200000 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_FNR_SHFT 0x15 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_TX_1_BMSK 0x100000 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_TX_1_SHFT 0x14 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_TX_0_BMSK 0x80000 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_TX_0_SHFT 0x13 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_NTF_TX_CMDQS_BMSK 0x40000 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_NTF_TX_CMDQS_SHFT 0x12 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_H_DCPH_BMSK 0x10000 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_H_DCPH_SHFT 0x10 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_D_DCPH_BMSK 0x8000 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_D_DCPH_SHFT 0xf +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_ACK_MNGR_BMSK 0x4000 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_ACK_MNGR_SHFT 0xe +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_CTX_HANDLER_BMSK 0x2000 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_CTX_HANDLER_SHFT 0xd +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_RSRC_MNGR_BMSK 0x1000 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_RSRC_MNGR_SHFT 0xc +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_DPS_TX_CMDQS_BMSK 0x800 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_DPS_TX_CMDQS_SHFT 0xb +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_HPS_DPS_CMDQS_BMSK 0x400 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_HPS_DPS_CMDQS_SHFT 0xa +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_RX_HPS_CMDQS_BMSK 0x200 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_RX_HPS_CMDQS_SHFT 0x9 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_DPS_BMSK 0x100 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_DPS_SHFT 0x8 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_HPS_BMSK 0x80 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_HPS_SHFT 0x7 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_FTCH_DPS_BMSK 0x40 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_FTCH_DPS_SHFT 0x6 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_FTCH_HPS_BMSK 0x20 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_FTCH_HPS_SHFT 0x5 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_RAM_ARB_BMSK 0x10 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_RAM_ARB_SHFT 0x4 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_MISC_BMSK 0x8 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_MISC_SHFT 0x3 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_TX_WRAPPER_BMSK 0x4 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_TX_WRAPPER_SHFT 0x2 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_PROC_BMSK 0x2 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_PROC_SHFT 0x1 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_RX_BMSK 0x1 +#define HWIO_IPA_CLKON_CFG_CGC_OPEN_RX_SHFT 0x0 + +#define HWIO_IPA_ROUTE_ADDR (IPA_CFG_REG_BASE + 0x00000054) +#define HWIO_IPA_ROUTE_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000054) +#define HWIO_IPA_ROUTE_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000054) +#define HWIO_IPA_ROUTE_RMSK 0x1fffffff +#define HWIO_IPA_ROUTE_ATTR 0x3 +#define HWIO_IPA_ROUTE_IN \ + in_dword_masked(HWIO_IPA_ROUTE_ADDR, HWIO_IPA_ROUTE_RMSK) +#define HWIO_IPA_ROUTE_INM(m) \ + in_dword_masked(HWIO_IPA_ROUTE_ADDR, m) +#define HWIO_IPA_ROUTE_OUT(v) \ + out_dword(HWIO_IPA_ROUTE_ADDR,v) +#define HWIO_IPA_ROUTE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_ROUTE_ADDR,m,v,HWIO_IPA_ROUTE_IN) +#define HWIO_IPA_ROUTE_ROUTE_DIS_BMSK 0x10000000 +#define HWIO_IPA_ROUTE_ROUTE_DIS_SHFT 0x1c +#define HWIO_IPA_ROUTE_ROUTE_DEF_RETAIN_HDR_BMSK 0x8000000 +#define HWIO_IPA_ROUTE_ROUTE_DEF_RETAIN_HDR_SHFT 0x1b +#define HWIO_IPA_ROUTE_ROUTE_DEF_HDR_TABLE_BMSK 0x4000000 +#define HWIO_IPA_ROUTE_ROUTE_DEF_HDR_TABLE_SHFT 0x1a +#define HWIO_IPA_ROUTE_ROUTE_DEF_HDR_OFST_BMSK 0x3ff0000 +#define HWIO_IPA_ROUTE_ROUTE_DEF_HDR_OFST_SHFT 0x10 +#define HWIO_IPA_ROUTE_ROUTE_FRAG_DEF_PIPE_BMSK 0xff00 +#define HWIO_IPA_ROUTE_ROUTE_FRAG_DEF_PIPE_SHFT 0x8 +#define HWIO_IPA_ROUTE_ROUTE_DEF_PIPE_BMSK 0xff +#define HWIO_IPA_ROUTE_ROUTE_DEF_PIPE_SHFT 0x0 + +#define HWIO_IPA_MASTER_PRIORITY_ADDR (IPA_CFG_REG_BASE + 0x00000058) +#define HWIO_IPA_MASTER_PRIORITY_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000058) +#define HWIO_IPA_MASTER_PRIORITY_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000058) +#define HWIO_IPA_MASTER_PRIORITY_RMSK 0xf +#define HWIO_IPA_MASTER_PRIORITY_ATTR 0x3 +#define HWIO_IPA_MASTER_PRIORITY_IN \ + in_dword_masked(HWIO_IPA_MASTER_PRIORITY_ADDR, HWIO_IPA_MASTER_PRIORITY_RMSK) +#define HWIO_IPA_MASTER_PRIORITY_INM(m) \ + in_dword_masked(HWIO_IPA_MASTER_PRIORITY_ADDR, m) +#define HWIO_IPA_MASTER_PRIORITY_OUT(v) \ + out_dword(HWIO_IPA_MASTER_PRIORITY_ADDR,v) +#define HWIO_IPA_MASTER_PRIORITY_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_MASTER_PRIORITY_ADDR,m,v,HWIO_IPA_MASTER_PRIORITY_IN) +#define HWIO_IPA_MASTER_PRIORITY_QMB_1_RD_BMSK 0xc +#define HWIO_IPA_MASTER_PRIORITY_QMB_1_RD_SHFT 0x2 +#define HWIO_IPA_MASTER_PRIORITY_QMB_0_RD_BMSK 0x3 +#define HWIO_IPA_MASTER_PRIORITY_QMB_0_RD_SHFT 0x0 + +#define HWIO_IPA_SHARED_MEM_SIZE_ADDR (IPA_CFG_REG_BASE + 0x0000005c) +#define HWIO_IPA_SHARED_MEM_SIZE_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000005c) +#define HWIO_IPA_SHARED_MEM_SIZE_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000005c) +#define HWIO_IPA_SHARED_MEM_SIZE_RMSK 0xffffffff +#define HWIO_IPA_SHARED_MEM_SIZE_ATTR 0x1 +#define HWIO_IPA_SHARED_MEM_SIZE_IN \ + in_dword_masked(HWIO_IPA_SHARED_MEM_SIZE_ADDR, HWIO_IPA_SHARED_MEM_SIZE_RMSK) +#define HWIO_IPA_SHARED_MEM_SIZE_INM(m) \ + in_dword_masked(HWIO_IPA_SHARED_MEM_SIZE_ADDR, m) +#define HWIO_IPA_SHARED_MEM_SIZE_SHARED_MEM_BADDR_BMSK 0xffff0000 +#define HWIO_IPA_SHARED_MEM_SIZE_SHARED_MEM_BADDR_SHFT 0x10 +#define HWIO_IPA_SHARED_MEM_SIZE_SHARED_MEM_SIZE_BMSK 0xffff +#define HWIO_IPA_SHARED_MEM_SIZE_SHARED_MEM_SIZE_SHFT 0x0 + +#define HWIO_IPA_NAT_TIMER_ADDR (IPA_CFG_REG_BASE + 0x00000060) +#define HWIO_IPA_NAT_TIMER_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000060) +#define HWIO_IPA_NAT_TIMER_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000060) +#define HWIO_IPA_NAT_TIMER_RMSK 0xffffff +#define HWIO_IPA_NAT_TIMER_ATTR 0x1 +#define HWIO_IPA_NAT_TIMER_IN \ + in_dword_masked(HWIO_IPA_NAT_TIMER_ADDR, HWIO_IPA_NAT_TIMER_RMSK) +#define HWIO_IPA_NAT_TIMER_INM(m) \ + in_dword_masked(HWIO_IPA_NAT_TIMER_ADDR, m) +#define HWIO_IPA_NAT_TIMER_NAT_TIMER_BMSK 0xffffff +#define HWIO_IPA_NAT_TIMER_NAT_TIMER_SHFT 0x0 + +#define HWIO_IPA_TAG_TIMER_ADDR (IPA_CFG_REG_BASE + 0x00000064) +#define HWIO_IPA_TAG_TIMER_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000064) +#define HWIO_IPA_TAG_TIMER_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000064) +#define HWIO_IPA_TAG_TIMER_RMSK 0xffffff +#define HWIO_IPA_TAG_TIMER_ATTR 0x1 +#define HWIO_IPA_TAG_TIMER_IN \ + in_dword_masked(HWIO_IPA_TAG_TIMER_ADDR, HWIO_IPA_TAG_TIMER_RMSK) +#define HWIO_IPA_TAG_TIMER_INM(m) \ + in_dword_masked(HWIO_IPA_TAG_TIMER_ADDR, m) +#define HWIO_IPA_TAG_TIMER_TAG_TIMER_BMSK 0xffffff +#define HWIO_IPA_TAG_TIMER_TAG_TIMER_SHFT 0x0 + +#define HWIO_IPA_FRAG_RULES_CLR_ADDR (IPA_CFG_REG_BASE + 0x00000068) +#define HWIO_IPA_FRAG_RULES_CLR_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000068) +#define HWIO_IPA_FRAG_RULES_CLR_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000068) +#define HWIO_IPA_FRAG_RULES_CLR_RMSK 0x1 +#define HWIO_IPA_FRAG_RULES_CLR_ATTR 0x2 +#define HWIO_IPA_FRAG_RULES_CLR_OUT(v) \ + out_dword(HWIO_IPA_FRAG_RULES_CLR_ADDR,v) +#define HWIO_IPA_FRAG_RULES_CLR_CLR_BMSK 0x1 +#define HWIO_IPA_FRAG_RULES_CLR_CLR_SHFT 0x0 + +#define HWIO_IPA_PROC_IPH_CFG_ADDR (IPA_CFG_REG_BASE + 0x0000006c) +#define HWIO_IPA_PROC_IPH_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000006c) +#define HWIO_IPA_PROC_IPH_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000006c) +#define HWIO_IPA_PROC_IPH_CFG_RMSK 0x1ff0f00 +#define HWIO_IPA_PROC_IPH_CFG_ATTR 0x3 +#define HWIO_IPA_PROC_IPH_CFG_IN \ + in_dword_masked(HWIO_IPA_PROC_IPH_CFG_ADDR, HWIO_IPA_PROC_IPH_CFG_RMSK) +#define HWIO_IPA_PROC_IPH_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_PROC_IPH_CFG_ADDR, m) +#define HWIO_IPA_PROC_IPH_CFG_OUT(v) \ + out_dword(HWIO_IPA_PROC_IPH_CFG_ADDR,v) +#define HWIO_IPA_PROC_IPH_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_PROC_IPH_CFG_ADDR,m,v,HWIO_IPA_PROC_IPH_CFG_IN) +#define HWIO_IPA_PROC_IPH_CFG_D_DCPH_MULTI_ENGINE_DISABLE_BMSK 0x1000000 +#define HWIO_IPA_PROC_IPH_CFG_D_DCPH_MULTI_ENGINE_DISABLE_SHFT 0x18 +#define HWIO_IPA_PROC_IPH_CFG_IPH_PKT_PARSER_PROTOCOL_STOP_VALUE_BMSK 0xff0000 +#define HWIO_IPA_PROC_IPH_CFG_IPH_PKT_PARSER_PROTOCOL_STOP_VALUE_SHFT 0x10 +#define HWIO_IPA_PROC_IPH_CFG_IPH_PKT_PARSER_IHL_TO_2ND_FRAG_EN_BMSK 0x800 +#define HWIO_IPA_PROC_IPH_CFG_IPH_PKT_PARSER_IHL_TO_2ND_FRAG_EN_SHFT 0xb +#define HWIO_IPA_PROC_IPH_CFG_IPH_PKT_PARSER_PROTOCOL_STOP_DEST_BMSK 0x400 +#define HWIO_IPA_PROC_IPH_CFG_IPH_PKT_PARSER_PROTOCOL_STOP_DEST_SHFT 0xa +#define HWIO_IPA_PROC_IPH_CFG_IPH_PKT_PARSER_PROTOCOL_STOP_HOP_BMSK 0x200 +#define HWIO_IPA_PROC_IPH_CFG_IPH_PKT_PARSER_PROTOCOL_STOP_HOP_SHFT 0x9 +#define HWIO_IPA_PROC_IPH_CFG_IPH_PKT_PARSER_PROTOCOL_STOP_ENABLE_BMSK 0x100 +#define HWIO_IPA_PROC_IPH_CFG_IPH_PKT_PARSER_PROTOCOL_STOP_ENABLE_SHFT 0x8 + +#define HWIO_IPA_QSB_MAX_WRITES_ADDR (IPA_CFG_REG_BASE + 0x00000070) +#define HWIO_IPA_QSB_MAX_WRITES_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000070) +#define HWIO_IPA_QSB_MAX_WRITES_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000070) +#define HWIO_IPA_QSB_MAX_WRITES_RMSK 0xff +#define HWIO_IPA_QSB_MAX_WRITES_ATTR 0x3 +#define HWIO_IPA_QSB_MAX_WRITES_IN \ + in_dword_masked(HWIO_IPA_QSB_MAX_WRITES_ADDR, HWIO_IPA_QSB_MAX_WRITES_RMSK) +#define HWIO_IPA_QSB_MAX_WRITES_INM(m) \ + in_dword_masked(HWIO_IPA_QSB_MAX_WRITES_ADDR, m) +#define HWIO_IPA_QSB_MAX_WRITES_OUT(v) \ + out_dword(HWIO_IPA_QSB_MAX_WRITES_ADDR,v) +#define HWIO_IPA_QSB_MAX_WRITES_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_QSB_MAX_WRITES_ADDR,m,v,HWIO_IPA_QSB_MAX_WRITES_IN) +#define HWIO_IPA_QSB_MAX_WRITES_GEN_QMB_1_MAX_WRITES_BMSK 0xf0 +#define HWIO_IPA_QSB_MAX_WRITES_GEN_QMB_1_MAX_WRITES_SHFT 0x4 +#define HWIO_IPA_QSB_MAX_WRITES_GEN_QMB_0_MAX_WRITES_BMSK 0xf +#define HWIO_IPA_QSB_MAX_WRITES_GEN_QMB_0_MAX_WRITES_SHFT 0x0 + +#define HWIO_IPA_QSB_MAX_READS_ADDR (IPA_CFG_REG_BASE + 0x00000074) +#define HWIO_IPA_QSB_MAX_READS_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000074) +#define HWIO_IPA_QSB_MAX_READS_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000074) +#define HWIO_IPA_QSB_MAX_READS_RMSK 0xffff00ff +#define HWIO_IPA_QSB_MAX_READS_ATTR 0x3 +#define HWIO_IPA_QSB_MAX_READS_IN \ + in_dword_masked(HWIO_IPA_QSB_MAX_READS_ADDR, HWIO_IPA_QSB_MAX_READS_RMSK) +#define HWIO_IPA_QSB_MAX_READS_INM(m) \ + in_dword_masked(HWIO_IPA_QSB_MAX_READS_ADDR, m) +#define HWIO_IPA_QSB_MAX_READS_OUT(v) \ + out_dword(HWIO_IPA_QSB_MAX_READS_ADDR,v) +#define HWIO_IPA_QSB_MAX_READS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_QSB_MAX_READS_ADDR,m,v,HWIO_IPA_QSB_MAX_READS_IN) +#define HWIO_IPA_QSB_MAX_READS_GEN_QMB_1_MAX_READ_BEATS_BMSK 0xff000000 +#define HWIO_IPA_QSB_MAX_READS_GEN_QMB_1_MAX_READ_BEATS_SHFT 0x18 +#define HWIO_IPA_QSB_MAX_READS_GEN_QMB_0_MAX_READ_BEATS_BMSK 0xff0000 +#define HWIO_IPA_QSB_MAX_READS_GEN_QMB_0_MAX_READ_BEATS_SHFT 0x10 +#define HWIO_IPA_QSB_MAX_READS_GEN_QMB_1_MAX_READS_BMSK 0xf0 +#define HWIO_IPA_QSB_MAX_READS_GEN_QMB_1_MAX_READS_SHFT 0x4 +#define HWIO_IPA_QSB_MAX_READS_GEN_QMB_0_MAX_READS_BMSK 0xf +#define HWIO_IPA_QSB_MAX_READS_GEN_QMB_0_MAX_READS_SHFT 0x0 + +#define HWIO_IPA_QSB_OUTSTANDING_COUNTER_ADDR (IPA_CFG_REG_BASE + 0x00000078) +#define HWIO_IPA_QSB_OUTSTANDING_COUNTER_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000078) +#define HWIO_IPA_QSB_OUTSTANDING_COUNTER_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000078) +#define HWIO_IPA_QSB_OUTSTANDING_COUNTER_RMSK 0x1f1f1f1f +#define HWIO_IPA_QSB_OUTSTANDING_COUNTER_ATTR 0x1 +#define HWIO_IPA_QSB_OUTSTANDING_COUNTER_IN \ + in_dword_masked(HWIO_IPA_QSB_OUTSTANDING_COUNTER_ADDR, HWIO_IPA_QSB_OUTSTANDING_COUNTER_RMSK) +#define HWIO_IPA_QSB_OUTSTANDING_COUNTER_INM(m) \ + in_dword_masked(HWIO_IPA_QSB_OUTSTANDING_COUNTER_ADDR, m) +#define HWIO_IPA_QSB_OUTSTANDING_COUNTER_GEN_QMB_1_WRITES_CNT_BMSK 0x1f000000 +#define HWIO_IPA_QSB_OUTSTANDING_COUNTER_GEN_QMB_1_WRITES_CNT_SHFT 0x18 +#define HWIO_IPA_QSB_OUTSTANDING_COUNTER_GEN_QMB_0_WRITES_CNT_BMSK 0x1f0000 +#define HWIO_IPA_QSB_OUTSTANDING_COUNTER_GEN_QMB_0_WRITES_CNT_SHFT 0x10 +#define HWIO_IPA_QSB_OUTSTANDING_COUNTER_GEN_QMB_1_READS_CNT_BMSK 0x1f00 +#define HWIO_IPA_QSB_OUTSTANDING_COUNTER_GEN_QMB_1_READS_CNT_SHFT 0x8 +#define HWIO_IPA_QSB_OUTSTANDING_COUNTER_GEN_QMB_0_READS_CNT_BMSK 0x1f +#define HWIO_IPA_QSB_OUTSTANDING_COUNTER_GEN_QMB_0_READS_CNT_SHFT 0x0 + +#define HWIO_IPA_QSB_OUTSTANDING_BEATS_COUNTER_ADDR (IPA_CFG_REG_BASE + 0x0000007c) +#define HWIO_IPA_QSB_OUTSTANDING_BEATS_COUNTER_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000007c) +#define HWIO_IPA_QSB_OUTSTANDING_BEATS_COUNTER_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000007c) +#define HWIO_IPA_QSB_OUTSTANDING_BEATS_COUNTER_RMSK 0xffff +#define HWIO_IPA_QSB_OUTSTANDING_BEATS_COUNTER_ATTR 0x1 +#define HWIO_IPA_QSB_OUTSTANDING_BEATS_COUNTER_IN \ + in_dword_masked(HWIO_IPA_QSB_OUTSTANDING_BEATS_COUNTER_ADDR, HWIO_IPA_QSB_OUTSTANDING_BEATS_COUNTER_RMSK) +#define HWIO_IPA_QSB_OUTSTANDING_BEATS_COUNTER_INM(m) \ + in_dword_masked(HWIO_IPA_QSB_OUTSTANDING_BEATS_COUNTER_ADDR, m) +#define HWIO_IPA_QSB_OUTSTANDING_BEATS_COUNTER_GEN_QMB_1_READ_BEATS_CNT_BMSK 0xff00 +#define HWIO_IPA_QSB_OUTSTANDING_BEATS_COUNTER_GEN_QMB_1_READ_BEATS_CNT_SHFT 0x8 +#define HWIO_IPA_QSB_OUTSTANDING_BEATS_COUNTER_GEN_QMB_0_READ_BEATS_CNT_BMSK 0xff +#define HWIO_IPA_QSB_OUTSTANDING_BEATS_COUNTER_GEN_QMB_0_READ_BEATS_CNT_SHFT 0x0 + +#define HWIO_IPA_DPL_TIMER_LSB_ADDR (IPA_CFG_REG_BASE + 0x00000080) +#define HWIO_IPA_DPL_TIMER_LSB_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000080) +#define HWIO_IPA_DPL_TIMER_LSB_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000080) +#define HWIO_IPA_DPL_TIMER_LSB_RMSK 0xffffffff +#define HWIO_IPA_DPL_TIMER_LSB_ATTR 0x3 +#define HWIO_IPA_DPL_TIMER_LSB_IN \ + in_dword_masked(HWIO_IPA_DPL_TIMER_LSB_ADDR, HWIO_IPA_DPL_TIMER_LSB_RMSK) +#define HWIO_IPA_DPL_TIMER_LSB_INM(m) \ + in_dword_masked(HWIO_IPA_DPL_TIMER_LSB_ADDR, m) +#define HWIO_IPA_DPL_TIMER_LSB_OUT(v) \ + out_dword(HWIO_IPA_DPL_TIMER_LSB_ADDR,v) +#define HWIO_IPA_DPL_TIMER_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_DPL_TIMER_LSB_ADDR,m,v,HWIO_IPA_DPL_TIMER_LSB_IN) +#define HWIO_IPA_DPL_TIMER_LSB_TOD_LSB_BMSK 0xffffffff +#define HWIO_IPA_DPL_TIMER_LSB_TOD_LSB_SHFT 0x0 + +#define HWIO_IPA_DPL_TIMER_MSB_ADDR (IPA_CFG_REG_BASE + 0x00000084) +#define HWIO_IPA_DPL_TIMER_MSB_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000084) +#define HWIO_IPA_DPL_TIMER_MSB_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000084) +#define HWIO_IPA_DPL_TIMER_MSB_RMSK 0xf80fffff +#define HWIO_IPA_DPL_TIMER_MSB_ATTR 0x3 +#define HWIO_IPA_DPL_TIMER_MSB_IN \ + in_dword_masked(HWIO_IPA_DPL_TIMER_MSB_ADDR, HWIO_IPA_DPL_TIMER_MSB_RMSK) +#define HWIO_IPA_DPL_TIMER_MSB_INM(m) \ + in_dword_masked(HWIO_IPA_DPL_TIMER_MSB_ADDR, m) +#define HWIO_IPA_DPL_TIMER_MSB_OUT(v) \ + out_dword(HWIO_IPA_DPL_TIMER_MSB_ADDR,v) +#define HWIO_IPA_DPL_TIMER_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_DPL_TIMER_MSB_ADDR,m,v,HWIO_IPA_DPL_TIMER_MSB_IN) +#define HWIO_IPA_DPL_TIMER_MSB_TIMER_EN_BMSK 0x80000000 +#define HWIO_IPA_DPL_TIMER_MSB_TIMER_EN_SHFT 0x1f +#define HWIO_IPA_DPL_TIMER_MSB_GRAN_SEL_BMSK 0x78000000 +#define HWIO_IPA_DPL_TIMER_MSB_GRAN_SEL_SHFT 0x1b +#define HWIO_IPA_DPL_TIMER_MSB_TOD_MSB_BMSK 0xfffff +#define HWIO_IPA_DPL_TIMER_MSB_TOD_MSB_SHFT 0x0 + +#define HWIO_IPA_DPL_TIMER_CTL_STS_ADDR (IPA_CFG_REG_BASE + 0x00000088) +#define HWIO_IPA_DPL_TIMER_CTL_STS_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000088) +#define HWIO_IPA_DPL_TIMER_CTL_STS_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000088) +#define HWIO_IPA_DPL_TIMER_CTL_STS_RMSK 0x11 +#define HWIO_IPA_DPL_TIMER_CTL_STS_ATTR 0x3 +#define HWIO_IPA_DPL_TIMER_CTL_STS_IN \ + in_dword_masked(HWIO_IPA_DPL_TIMER_CTL_STS_ADDR, HWIO_IPA_DPL_TIMER_CTL_STS_RMSK) +#define HWIO_IPA_DPL_TIMER_CTL_STS_INM(m) \ + in_dword_masked(HWIO_IPA_DPL_TIMER_CTL_STS_ADDR, m) +#define HWIO_IPA_DPL_TIMER_CTL_STS_OUT(v) \ + out_dword(HWIO_IPA_DPL_TIMER_CTL_STS_ADDR,v) +#define HWIO_IPA_DPL_TIMER_CTL_STS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_DPL_TIMER_CTL_STS_ADDR,m,v,HWIO_IPA_DPL_TIMER_CTL_STS_IN) +#define HWIO_IPA_DPL_TIMER_CTL_STS_TOD_VALID_BMSK 0x10 +#define HWIO_IPA_DPL_TIMER_CTL_STS_TOD_VALID_SHFT 0x4 +#define HWIO_IPA_DPL_TIMER_CTL_STS_LEGACY_TIMER_BMSK 0x1 +#define HWIO_IPA_DPL_TIMER_CTL_STS_LEGACY_TIMER_SHFT 0x0 + +#define HWIO_IPA_STATE_RX_ACTIVE_n_ADDR(n) (IPA_CFG_REG_BASE + 0x000000a0 + 0x4 * (n)) +#define HWIO_IPA_STATE_RX_ACTIVE_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x000000a0 + 0x4 * (n)) +#define HWIO_IPA_STATE_RX_ACTIVE_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x000000a0 + 0x4 * (n)) +#define HWIO_IPA_STATE_RX_ACTIVE_n_RMSK 0xffffffff +#define HWIO_IPA_STATE_RX_ACTIVE_n_MAXn 0 +#define HWIO_IPA_STATE_RX_ACTIVE_n_ATTR 0x1 +#define HWIO_IPA_STATE_RX_ACTIVE_n_INI(n) \ + in_dword_masked(HWIO_IPA_STATE_RX_ACTIVE_n_ADDR(n), HWIO_IPA_STATE_RX_ACTIVE_n_RMSK) +#define HWIO_IPA_STATE_RX_ACTIVE_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_STATE_RX_ACTIVE_n_ADDR(n), mask) +#define HWIO_IPA_STATE_RX_ACTIVE_n_ENDPOINTS_BMSK 0xffffffff +#define HWIO_IPA_STATE_RX_ACTIVE_n_ENDPOINTS_SHFT 0x0 + +#define HWIO_IPA_STATE_TX_WRAPPER_ADDR (IPA_CFG_REG_BASE + 0x000000b0) +#define HWIO_IPA_STATE_TX_WRAPPER_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000b0) +#define HWIO_IPA_STATE_TX_WRAPPER_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000b0) +#define HWIO_IPA_STATE_TX_WRAPPER_RMSK 0x3c3dd +#define HWIO_IPA_STATE_TX_WRAPPER_ATTR 0x1 +#define HWIO_IPA_STATE_TX_WRAPPER_IN \ + in_dword_masked(HWIO_IPA_STATE_TX_WRAPPER_ADDR, HWIO_IPA_STATE_TX_WRAPPER_RMSK) +#define HWIO_IPA_STATE_TX_WRAPPER_INM(m) \ + in_dword_masked(HWIO_IPA_STATE_TX_WRAPPER_ADDR, m) +#define HWIO_IPA_STATE_TX_WRAPPER_COAL_DIRECT_DMA_BMSK 0x30000 +#define HWIO_IPA_STATE_TX_WRAPPER_COAL_DIRECT_DMA_SHFT 0x10 +#define HWIO_IPA_STATE_TX_WRAPPER_NLO_DIRECT_DMA_BMSK 0xc000 +#define HWIO_IPA_STATE_TX_WRAPPER_NLO_DIRECT_DMA_SHFT 0xe +#define HWIO_IPA_STATE_TX_WRAPPER_MBIM_DIRECT_DMA_BMSK 0x300 +#define HWIO_IPA_STATE_TX_WRAPPER_MBIM_DIRECT_DMA_SHFT 0x8 +#define HWIO_IPA_STATE_TX_WRAPPER_IPA_MBIM_PKT_FSM_IDLE_BMSK 0xc0 +#define HWIO_IPA_STATE_TX_WRAPPER_IPA_MBIM_PKT_FSM_IDLE_SHFT 0x6 +#define HWIO_IPA_STATE_TX_WRAPPER_IPA_PROD_BRESP_EMPTY_BMSK 0x10 +#define HWIO_IPA_STATE_TX_WRAPPER_IPA_PROD_BRESP_EMPTY_SHFT 0x4 +#define HWIO_IPA_STATE_TX_WRAPPER_IPA_PROD_ACKMNGR_STATE_IDLE_BMSK 0x8 +#define HWIO_IPA_STATE_TX_WRAPPER_IPA_PROD_ACKMNGR_STATE_IDLE_SHFT 0x3 +#define HWIO_IPA_STATE_TX_WRAPPER_IPA_PROD_ACKMNGR_DB_EMPTY_BMSK 0x4 +#define HWIO_IPA_STATE_TX_WRAPPER_IPA_PROD_ACKMNGR_DB_EMPTY_SHFT 0x2 +#define HWIO_IPA_STATE_TX_WRAPPER_TX_IDLE_BMSK 0x1 +#define HWIO_IPA_STATE_TX_WRAPPER_TX_IDLE_SHFT 0x0 + +#define HWIO_IPA_STATE_TX_ADDR (IPA_CFG_REG_BASE + 0x000000b4) +#define HWIO_IPA_STATE_TX_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000b4) +#define HWIO_IPA_STATE_TX_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000b4) +#define HWIO_IPA_STATE_TX_RMSK 0xffffffff +#define HWIO_IPA_STATE_TX_ATTR 0x1 +#define HWIO_IPA_STATE_TX_IN \ + in_dword_masked(HWIO_IPA_STATE_TX_ADDR, HWIO_IPA_STATE_TX_RMSK) +#define HWIO_IPA_STATE_TX_INM(m) \ + in_dword_masked(HWIO_IPA_STATE_TX_ADDR, m) +#define HWIO_IPA_STATE_TX_STAGE_ARB_DMA_TYPE_BMSK 0xf0000000 +#define HWIO_IPA_STATE_TX_STAGE_ARB_DMA_TYPE_SHFT 0x1c +#define HWIO_IPA_STATE_TX_STAGE_ARB_CTX_ID_BMSK 0xf000000 +#define HWIO_IPA_STATE_TX_STAGE_ARB_CTX_ID_SHFT 0x18 +#define HWIO_IPA_STATE_TX_STAGE_ARB_DEST_PIPE_BMSK 0xff0000 +#define HWIO_IPA_STATE_TX_STAGE_ARB_DEST_PIPE_SHFT 0x10 +#define HWIO_IPA_STATE_TX_DMAW_1_BUSY_BMSK 0x8000 +#define HWIO_IPA_STATE_TX_DMAW_1_BUSY_SHFT 0xf +#define HWIO_IPA_STATE_TX_DMAW_0_BUSY_BMSK 0x4000 +#define HWIO_IPA_STATE_TX_DMAW_0_BUSY_SHFT 0xe +#define HWIO_IPA_STATE_TX_HOLB_MASK_VALID_BMSK 0x2000 +#define HWIO_IPA_STATE_TX_HOLB_MASK_VALID_SHFT 0xd +#define HWIO_IPA_STATE_TX_PACKET_RELEASE_HANDLER_BUSY_BMSK 0x1000 +#define HWIO_IPA_STATE_TX_PACKET_RELEASE_HANDLER_BUSY_SHFT 0xc +#define HWIO_IPA_STATE_TX_DROP_HANDLER_BUSY_BMSK 0x800 +#define HWIO_IPA_STATE_TX_DROP_HANDLER_BUSY_SHFT 0xb +#define HWIO_IPA_STATE_TX_SUSPEND_HANDLER_BUSY_BMSK 0x400 +#define HWIO_IPA_STATE_TX_SUSPEND_HANDLER_BUSY_SHFT 0xa +#define HWIO_IPA_STATE_TX_PACKET_DROP_COUNTER_BUSY_BMSK 0x200 +#define HWIO_IPA_STATE_TX_PACKET_DROP_COUNTER_BUSY_SHFT 0x9 +#define HWIO_IPA_STATE_TX_STAGE_CHECKSUM_HANDLER_1_BUSY_BMSK 0x100 +#define HWIO_IPA_STATE_TX_STAGE_CHECKSUM_HANDLER_1_BUSY_SHFT 0x8 +#define HWIO_IPA_STATE_TX_STAGE_CHECKSUM_HANDLER_0_BUSY_BMSK 0x80 +#define HWIO_IPA_STATE_TX_STAGE_CHECKSUM_HANDLER_0_BUSY_SHFT 0x7 +#define HWIO_IPA_STATE_TX_STAGE_TRANSMISSION_1_BUSY_BMSK 0x40 +#define HWIO_IPA_STATE_TX_STAGE_TRANSMISSION_1_BUSY_SHFT 0x6 +#define HWIO_IPA_STATE_TX_STAGE_TRANSMISSION_0_BUSY_BMSK 0x20 +#define HWIO_IPA_STATE_TX_STAGE_TRANSMISSION_0_BUSY_SHFT 0x5 +#define HWIO_IPA_STATE_TX_STAGE_PACKET_CONSTRUCTOR_1_BUSY_BMSK 0x10 +#define HWIO_IPA_STATE_TX_STAGE_PACKET_CONSTRUCTOR_1_BUSY_SHFT 0x4 +#define HWIO_IPA_STATE_TX_STAGE_PACKET_CONSTRUCTOR_0_BUSY_BMSK 0x8 +#define HWIO_IPA_STATE_TX_STAGE_PACKET_CONSTRUCTOR_0_BUSY_SHFT 0x3 +#define HWIO_IPA_STATE_TX_STAGE_ADDRESS_RESOLUTION_BUSY_BMSK 0x4 +#define HWIO_IPA_STATE_TX_STAGE_ADDRESS_RESOLUTION_BUSY_SHFT 0x2 +#define HWIO_IPA_STATE_TX_STAGE_PACKET_PROCESSSOR_BUSY_BMSK 0x2 +#define HWIO_IPA_STATE_TX_STAGE_PACKET_PROCESSSOR_BUSY_SHFT 0x1 +#define HWIO_IPA_STATE_TX_STAGE_ARB_BUSY_BMSK 0x1 +#define HWIO_IPA_STATE_TX_STAGE_ARB_BUSY_SHFT 0x0 + +#define HWIO_IPA_STATE_TX_HOLB_MASK_DPS_TX_0_ADDR (IPA_CFG_REG_BASE + 0x000000b8) +#define HWIO_IPA_STATE_TX_HOLB_MASK_DPS_TX_0_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000b8) +#define HWIO_IPA_STATE_TX_HOLB_MASK_DPS_TX_0_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000b8) +#define HWIO_IPA_STATE_TX_HOLB_MASK_DPS_TX_0_RMSK 0xffffffff +#define HWIO_IPA_STATE_TX_HOLB_MASK_DPS_TX_0_ATTR 0x1 +#define HWIO_IPA_STATE_TX_HOLB_MASK_DPS_TX_0_IN \ + in_dword_masked(HWIO_IPA_STATE_TX_HOLB_MASK_DPS_TX_0_ADDR, HWIO_IPA_STATE_TX_HOLB_MASK_DPS_TX_0_RMSK) +#define HWIO_IPA_STATE_TX_HOLB_MASK_DPS_TX_0_INM(m) \ + in_dword_masked(HWIO_IPA_STATE_TX_HOLB_MASK_DPS_TX_0_ADDR, m) +#define HWIO_IPA_STATE_TX_HOLB_MASK_DPS_TX_0_PRODUCER_MASK_0_31_BMSK 0xffffffff +#define HWIO_IPA_STATE_TX_HOLB_MASK_DPS_TX_0_PRODUCER_MASK_0_31_SHFT 0x0 + +#define HWIO_IPA_STATE_TX_HOLB_MASK_NTF_TX_0_ADDR (IPA_CFG_REG_BASE + 0x000000bc) +#define HWIO_IPA_STATE_TX_HOLB_MASK_NTF_TX_0_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000bc) +#define HWIO_IPA_STATE_TX_HOLB_MASK_NTF_TX_0_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000bc) +#define HWIO_IPA_STATE_TX_HOLB_MASK_NTF_TX_0_RMSK 0xffffffff +#define HWIO_IPA_STATE_TX_HOLB_MASK_NTF_TX_0_ATTR 0x1 +#define HWIO_IPA_STATE_TX_HOLB_MASK_NTF_TX_0_IN \ + in_dword_masked(HWIO_IPA_STATE_TX_HOLB_MASK_NTF_TX_0_ADDR, HWIO_IPA_STATE_TX_HOLB_MASK_NTF_TX_0_RMSK) +#define HWIO_IPA_STATE_TX_HOLB_MASK_NTF_TX_0_INM(m) \ + in_dword_masked(HWIO_IPA_STATE_TX_HOLB_MASK_NTF_TX_0_ADDR, m) +#define HWIO_IPA_STATE_TX_HOLB_MASK_NTF_TX_0_PRODUCER_MASK_0_31_BMSK 0xffffffff +#define HWIO_IPA_STATE_TX_HOLB_MASK_NTF_TX_0_PRODUCER_MASK_0_31_SHFT 0x0 + +#define HWIO_IPA_STATE_TX_HOLB_MASK_NTF_TX_1_ADDR (IPA_CFG_REG_BASE + 0x000000c0) +#define HWIO_IPA_STATE_TX_HOLB_MASK_NTF_TX_1_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000c0) +#define HWIO_IPA_STATE_TX_HOLB_MASK_NTF_TX_1_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000c0) +#define HWIO_IPA_STATE_TX_HOLB_MASK_NTF_TX_1_RMSK 0xffffffff +#define HWIO_IPA_STATE_TX_HOLB_MASK_NTF_TX_1_ATTR 0x1 +#define HWIO_IPA_STATE_TX_HOLB_MASK_NTF_TX_1_IN \ + in_dword_masked(HWIO_IPA_STATE_TX_HOLB_MASK_NTF_TX_1_ADDR, HWIO_IPA_STATE_TX_HOLB_MASK_NTF_TX_1_RMSK) +#define HWIO_IPA_STATE_TX_HOLB_MASK_NTF_TX_1_INM(m) \ + in_dword_masked(HWIO_IPA_STATE_TX_HOLB_MASK_NTF_TX_1_ADDR, m) +#define HWIO_IPA_STATE_TX_HOLB_MASK_NTF_TX_1_PRODUCER_MASK_32_64_BMSK 0xffffffff +#define HWIO_IPA_STATE_TX_HOLB_MASK_NTF_TX_1_PRODUCER_MASK_32_64_SHFT 0x0 + +#define HWIO_IPA_STATE_FETCHER_ADDR (IPA_CFG_REG_BASE + 0x000000c4) +#define HWIO_IPA_STATE_FETCHER_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000c4) +#define HWIO_IPA_STATE_FETCHER_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000c4) +#define HWIO_IPA_STATE_FETCHER_RMSK 0xfffff +#define HWIO_IPA_STATE_FETCHER_ATTR 0x1 +#define HWIO_IPA_STATE_FETCHER_IN \ + in_dword_masked(HWIO_IPA_STATE_FETCHER_ADDR, HWIO_IPA_STATE_FETCHER_RMSK) +#define HWIO_IPA_STATE_FETCHER_INM(m) \ + in_dword_masked(HWIO_IPA_STATE_FETCHER_ADDR, m) +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_IMM_CMD_EXEC_STATE_IDLE_BMSK 0x80000 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_IMM_CMD_EXEC_STATE_IDLE_SHFT 0x13 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_DMAR_SLOT_STATE_IDLE_BMSK 0x7f000 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_DMAR_SLOT_STATE_IDLE_SHFT 0xc +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_DMAR_STATE_IDLE_BMSK 0xfe0 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_DMAR_STATE_IDLE_SHFT 0x5 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_FTCH_CMPLT_STATE_IDLE_BMSK 0x10 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_FTCH_CMPLT_STATE_IDLE_SHFT 0x4 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_FTCH_IMM_STATE_IDLE_BMSK 0x8 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_FTCH_IMM_STATE_IDLE_SHFT 0x3 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_FTCH_PKT_STATE_IDLE_BMSK 0x4 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_FTCH_PKT_STATE_IDLE_SHFT 0x2 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_FTCH_ALLOC_STATE_IDLE_BMSK 0x2 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_FTCH_ALLOC_STATE_IDLE_SHFT 0x1 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_FTCH_STATE_IDLE_BMSK 0x1 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_FTCH_STATE_IDLE_SHFT 0x0 + +#define HWIO_IPA_STATE_FETCHER_MASK_0_ADDR (IPA_CFG_REG_BASE + 0x000000c8) +#define HWIO_IPA_STATE_FETCHER_MASK_0_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000c8) +#define HWIO_IPA_STATE_FETCHER_MASK_0_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000c8) +#define HWIO_IPA_STATE_FETCHER_MASK_0_RMSK 0xffffffff +#define HWIO_IPA_STATE_FETCHER_MASK_0_ATTR 0x1 +#define HWIO_IPA_STATE_FETCHER_MASK_0_IN \ + in_dword_masked(HWIO_IPA_STATE_FETCHER_MASK_0_ADDR, HWIO_IPA_STATE_FETCHER_MASK_0_RMSK) +#define HWIO_IPA_STATE_FETCHER_MASK_0_INM(m) \ + in_dword_masked(HWIO_IPA_STATE_FETCHER_MASK_0_ADDR, m) +#define HWIO_IPA_STATE_FETCHER_MASK_0_MASK_QUEUE_NO_RESOURCES_HPS_DMAR_BMSK 0xff000000 +#define HWIO_IPA_STATE_FETCHER_MASK_0_MASK_QUEUE_NO_RESOURCES_HPS_DMAR_SHFT 0x18 +#define HWIO_IPA_STATE_FETCHER_MASK_0_MASK_QUEUE_NO_RESOURCES_CONTEXT_BMSK 0xff0000 +#define HWIO_IPA_STATE_FETCHER_MASK_0_MASK_QUEUE_NO_RESOURCES_CONTEXT_SHFT 0x10 +#define HWIO_IPA_STATE_FETCHER_MASK_0_MASK_QUEUE_IMM_EXEC_BMSK 0xff00 +#define HWIO_IPA_STATE_FETCHER_MASK_0_MASK_QUEUE_IMM_EXEC_SHFT 0x8 +#define HWIO_IPA_STATE_FETCHER_MASK_0_MASK_QUEUE_DMAR_USES_QUEUE_BMSK 0xff +#define HWIO_IPA_STATE_FETCHER_MASK_0_MASK_QUEUE_DMAR_USES_QUEUE_SHFT 0x0 + +#define HWIO_IPA_STATE_DFETCHER_ADDR (IPA_CFG_REG_BASE + 0x000000cc) +#define HWIO_IPA_STATE_DFETCHER_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000cc) +#define HWIO_IPA_STATE_DFETCHER_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000cc) +#define HWIO_IPA_STATE_DFETCHER_RMSK 0x7f07f3 +#define HWIO_IPA_STATE_DFETCHER_ATTR 0x1 +#define HWIO_IPA_STATE_DFETCHER_IN \ + in_dword_masked(HWIO_IPA_STATE_DFETCHER_ADDR, HWIO_IPA_STATE_DFETCHER_RMSK) +#define HWIO_IPA_STATE_DFETCHER_INM(m) \ + in_dword_masked(HWIO_IPA_STATE_DFETCHER_ADDR, m) +#define HWIO_IPA_STATE_DFETCHER_IPA_DPS_DMAR_SLOT_STATE_IDLE_BMSK 0x7f0000 +#define HWIO_IPA_STATE_DFETCHER_IPA_DPS_DMAR_SLOT_STATE_IDLE_SHFT 0x10 +#define HWIO_IPA_STATE_DFETCHER_IPA_DPS_DMAR_STATE_IDLE_BMSK 0x7f0 +#define HWIO_IPA_STATE_DFETCHER_IPA_DPS_DMAR_STATE_IDLE_SHFT 0x4 +#define HWIO_IPA_STATE_DFETCHER_IPA_DPS_FTCH_CMPLT_STATE_IDLE_BMSK 0x2 +#define HWIO_IPA_STATE_DFETCHER_IPA_DPS_FTCH_CMPLT_STATE_IDLE_SHFT 0x1 +#define HWIO_IPA_STATE_DFETCHER_IPA_DPS_FTCH_PKT_STATE_IDLE_BMSK 0x1 +#define HWIO_IPA_STATE_DFETCHER_IPA_DPS_FTCH_PKT_STATE_IDLE_SHFT 0x0 + +#define HWIO_IPA_STATE_ACL_ADDR (IPA_CFG_REG_BASE + 0x000000d0) +#define HWIO_IPA_STATE_ACL_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000d0) +#define HWIO_IPA_STATE_ACL_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000d0) +#define HWIO_IPA_STATE_ACL_RMSK 0x7ffcffff +#define HWIO_IPA_STATE_ACL_ATTR 0x1 +#define HWIO_IPA_STATE_ACL_IN \ + in_dword_masked(HWIO_IPA_STATE_ACL_ADDR, HWIO_IPA_STATE_ACL_RMSK) +#define HWIO_IPA_STATE_ACL_INM(m) \ + in_dword_masked(HWIO_IPA_STATE_ACL_ADDR, m) +#define HWIO_IPA_STATE_ACL_IPA_HPS_EMPTY_BMSK 0x40000000 +#define HWIO_IPA_STATE_ACL_IPA_HPS_EMPTY_SHFT 0x1e +#define HWIO_IPA_STATE_ACL_IPA_HPS_MULTI_DRBIP_ACTIVE_BMSK 0x20000000 +#define HWIO_IPA_STATE_ACL_IPA_HPS_MULTI_DRBIP_ACTIVE_SHFT 0x1d +#define HWIO_IPA_STATE_ACL_IPA_HPS_MULTI_DRBIP_EMPTY_BMSK 0x10000000 +#define HWIO_IPA_STATE_ACL_IPA_HPS_MULTI_DRBIP_EMPTY_SHFT 0x1c +#define HWIO_IPA_STATE_ACL_IPA_HPS_COAL_MASTER_ACTIVE_BMSK 0x8000000 +#define HWIO_IPA_STATE_ACL_IPA_HPS_COAL_MASTER_ACTIVE_SHFT 0x1b +#define HWIO_IPA_STATE_ACL_IPA_HPS_COAL_MASTER_EMPTY_BMSK 0x4000000 +#define HWIO_IPA_STATE_ACL_IPA_HPS_COAL_MASTER_EMPTY_SHFT 0x1a +#define HWIO_IPA_STATE_ACL_IPA_DPS_D_DCPH_2ND_ACTIVE_BMSK 0x2000000 +#define HWIO_IPA_STATE_ACL_IPA_DPS_D_DCPH_2ND_ACTIVE_SHFT 0x19 +#define HWIO_IPA_STATE_ACL_IPA_DPS_D_DCPH_2ND_EMPTY_BMSK 0x1000000 +#define HWIO_IPA_STATE_ACL_IPA_DPS_D_DCPH_2ND_EMPTY_SHFT 0x18 +#define HWIO_IPA_STATE_ACL_IPA_DPS_SEQUENCER_IDLE_BMSK 0x800000 +#define HWIO_IPA_STATE_ACL_IPA_DPS_SEQUENCER_IDLE_SHFT 0x17 +#define HWIO_IPA_STATE_ACL_IPA_HPS_SEQUENCER_IDLE_BMSK 0x400000 +#define HWIO_IPA_STATE_ACL_IPA_HPS_SEQUENCER_IDLE_SHFT 0x16 +#define HWIO_IPA_STATE_ACL_IPA_DPS_D_DCPH_2_ACTIVE_BMSK 0x200000 +#define HWIO_IPA_STATE_ACL_IPA_DPS_D_DCPH_2_ACTIVE_SHFT 0x15 +#define HWIO_IPA_STATE_ACL_IPA_DPS_D_DCPH_2_EMPTY_BMSK 0x100000 +#define HWIO_IPA_STATE_ACL_IPA_DPS_D_DCPH_2_EMPTY_SHFT 0x14 +#define HWIO_IPA_STATE_ACL_IPA_DPS_DISPATCHER_ACTIVE_BMSK 0x80000 +#define HWIO_IPA_STATE_ACL_IPA_DPS_DISPATCHER_ACTIVE_SHFT 0x13 +#define HWIO_IPA_STATE_ACL_IPA_DPS_DISPATCHER_EMPTY_BMSK 0x40000 +#define HWIO_IPA_STATE_ACL_IPA_DPS_DISPATCHER_EMPTY_SHFT 0x12 +#define HWIO_IPA_STATE_ACL_IPA_DPS_D_DCPH_ACTIVE_BMSK 0x8000 +#define HWIO_IPA_STATE_ACL_IPA_DPS_D_DCPH_ACTIVE_SHFT 0xf +#define HWIO_IPA_STATE_ACL_IPA_DPS_D_DCPH_EMPTY_BMSK 0x4000 +#define HWIO_IPA_STATE_ACL_IPA_DPS_D_DCPH_EMPTY_SHFT 0xe +#define HWIO_IPA_STATE_ACL_IPA_HPS_ENQUEUER_ACTIVE_BMSK 0x2000 +#define HWIO_IPA_STATE_ACL_IPA_HPS_ENQUEUER_ACTIVE_SHFT 0xd +#define HWIO_IPA_STATE_ACL_IPA_HPS_ENQUEUER_EMPTY_BMSK 0x1000 +#define HWIO_IPA_STATE_ACL_IPA_HPS_ENQUEUER_EMPTY_SHFT 0xc +#define HWIO_IPA_STATE_ACL_IPA_HPS_UCP_ACTIVE_BMSK 0x800 +#define HWIO_IPA_STATE_ACL_IPA_HPS_UCP_ACTIVE_SHFT 0xb +#define HWIO_IPA_STATE_ACL_IPA_HPS_UCP_EMPTY_BMSK 0x400 +#define HWIO_IPA_STATE_ACL_IPA_HPS_UCP_EMPTY_SHFT 0xa +#define HWIO_IPA_STATE_ACL_IPA_HPS_HDRI_ACTIVE_BMSK 0x200 +#define HWIO_IPA_STATE_ACL_IPA_HPS_HDRI_ACTIVE_SHFT 0x9 +#define HWIO_IPA_STATE_ACL_IPA_HPS_HDRI_EMPTY_BMSK 0x100 +#define HWIO_IPA_STATE_ACL_IPA_HPS_HDRI_EMPTY_SHFT 0x8 +#define HWIO_IPA_STATE_ACL_IPA_HPS_ROUTER_ACTIVE_BMSK 0x80 +#define HWIO_IPA_STATE_ACL_IPA_HPS_ROUTER_ACTIVE_SHFT 0x7 +#define HWIO_IPA_STATE_ACL_IPA_HPS_ROUTER_EMPTY_BMSK 0x40 +#define HWIO_IPA_STATE_ACL_IPA_HPS_ROUTER_EMPTY_SHFT 0x6 +#define HWIO_IPA_STATE_ACL_IPA_HPS_FILTER_NAT_ACTIVE_BMSK 0x20 +#define HWIO_IPA_STATE_ACL_IPA_HPS_FILTER_NAT_ACTIVE_SHFT 0x5 +#define HWIO_IPA_STATE_ACL_IPA_HPS_FILTER_NAT_EMPTY_BMSK 0x10 +#define HWIO_IPA_STATE_ACL_IPA_HPS_FILTER_NAT_EMPTY_SHFT 0x4 +#define HWIO_IPA_STATE_ACL_IPA_HPS_PKT_PARSER_ACTIVE_BMSK 0x8 +#define HWIO_IPA_STATE_ACL_IPA_HPS_PKT_PARSER_ACTIVE_SHFT 0x3 +#define HWIO_IPA_STATE_ACL_IPA_HPS_PKT_PARSER_EMPTY_BMSK 0x4 +#define HWIO_IPA_STATE_ACL_IPA_HPS_PKT_PARSER_EMPTY_SHFT 0x2 +#define HWIO_IPA_STATE_ACL_IPA_HPS_H_DCPH_ACTIVE_BMSK 0x2 +#define HWIO_IPA_STATE_ACL_IPA_HPS_H_DCPH_ACTIVE_SHFT 0x1 +#define HWIO_IPA_STATE_ACL_IPA_HPS_H_DCPH_EMPTY_BMSK 0x1 +#define HWIO_IPA_STATE_ACL_IPA_HPS_H_DCPH_EMPTY_SHFT 0x0 + +#define HWIO_IPA_STATE_ADDR (IPA_CFG_REG_BASE + 0x000000d4) +#define HWIO_IPA_STATE_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000d4) +#define HWIO_IPA_STATE_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000d4) +#define HWIO_IPA_STATE_RMSK 0xffffffff +#define HWIO_IPA_STATE_ATTR 0x1 +#define HWIO_IPA_STATE_IN \ + in_dword_masked(HWIO_IPA_STATE_ADDR, HWIO_IPA_STATE_RMSK) +#define HWIO_IPA_STATE_INM(m) \ + in_dword_masked(HWIO_IPA_STATE_ADDR, m) +#define HWIO_IPA_STATE_IPA_UC_RX_HND_CMDQ_EMPTY_BMSK 0x80000000 +#define HWIO_IPA_STATE_IPA_UC_RX_HND_CMDQ_EMPTY_SHFT 0x1f +#define HWIO_IPA_STATE_IPA_DPS_TX_EMPTY_BMSK 0x40000000 +#define HWIO_IPA_STATE_IPA_DPS_TX_EMPTY_SHFT 0x1e +#define HWIO_IPA_STATE_IPA_HPS_DPS_EMPTY_BMSK 0x20000000 +#define HWIO_IPA_STATE_IPA_HPS_DPS_EMPTY_SHFT 0x1d +#define HWIO_IPA_STATE_IPA_RX_HPS_EMPTY_BMSK 0x10000000 +#define HWIO_IPA_STATE_IPA_RX_HPS_EMPTY_SHFT 0x1c +#define HWIO_IPA_STATE_IPA_RX_SPLT_CMDQ_EMPTY_BMSK 0xf800000 +#define HWIO_IPA_STATE_IPA_RX_SPLT_CMDQ_EMPTY_SHFT 0x17 +#define HWIO_IPA_STATE_IPA_TX_COMMANDER_CMDQ_EMPTY_BMSK 0x400000 +#define HWIO_IPA_STATE_IPA_TX_COMMANDER_CMDQ_EMPTY_SHFT 0x16 +#define HWIO_IPA_STATE_IPA_RX_ACKQ_EMPTY_BMSK 0x200000 +#define HWIO_IPA_STATE_IPA_RX_ACKQ_EMPTY_SHFT 0x15 +#define HWIO_IPA_STATE_IPA_UC_ACKQ_EMPTY_BMSK 0x100000 +#define HWIO_IPA_STATE_IPA_UC_ACKQ_EMPTY_SHFT 0x14 +#define HWIO_IPA_STATE_IPA_PROD_DPL_FIFO_IDLE_BMSK 0x80000 +#define HWIO_IPA_STATE_IPA_PROD_DPL_FIFO_IDLE_SHFT 0x13 +#define HWIO_IPA_STATE_IPA_NTF_TX_EMPTY_BMSK 0x40000 +#define HWIO_IPA_STATE_IPA_NTF_TX_EMPTY_SHFT 0x12 +#define HWIO_IPA_STATE_IPA_FULL_IDLE_BMSK 0x20000 +#define HWIO_IPA_STATE_IPA_FULL_IDLE_SHFT 0x11 +#define HWIO_IPA_STATE_IPA_PROD_BRESP_IDLE_BMSK 0x10000 +#define HWIO_IPA_STATE_IPA_PROD_BRESP_IDLE_SHFT 0x10 +#define HWIO_IPA_STATE_IPA_PROD_ACKMNGR_STATE_IDLE_BMSK 0x8000 +#define HWIO_IPA_STATE_IPA_PROD_ACKMNGR_STATE_IDLE_SHFT 0xf +#define HWIO_IPA_STATE_IPA_PROD_ACKMNGR_DB_EMPTY_BMSK 0x4000 +#define HWIO_IPA_STATE_IPA_PROD_ACKMNGR_DB_EMPTY_SHFT 0xe +#define HWIO_IPA_STATE_IPA_TX_ACKQ_FULL_BMSK 0x2000 +#define HWIO_IPA_STATE_IPA_TX_ACKQ_FULL_SHFT 0xd +#define HWIO_IPA_STATE_IPA_ACKMNGR_STATE_IDLE_BMSK 0x1000 +#define HWIO_IPA_STATE_IPA_ACKMNGR_STATE_IDLE_SHFT 0xc +#define HWIO_IPA_STATE_IPA_ACKMNGR_DB_EMPTY_BMSK 0x800 +#define HWIO_IPA_STATE_IPA_ACKMNGR_DB_EMPTY_SHFT 0xb +#define HWIO_IPA_STATE_IPA_RSRC_STATE_IDLE_BMSK 0x400 +#define HWIO_IPA_STATE_IPA_RSRC_STATE_IDLE_SHFT 0xa +#define HWIO_IPA_STATE_IPA_RSRC_MNGR_DB_EMPTY_BMSK 0x200 +#define HWIO_IPA_STATE_IPA_RSRC_MNGR_DB_EMPTY_SHFT 0x9 +#define HWIO_IPA_STATE_MBIM_AGGR_IDLE_BMSK 0x100 +#define HWIO_IPA_STATE_MBIM_AGGR_IDLE_SHFT 0x8 +#define HWIO_IPA_STATE_AGGR_IDLE_BMSK 0x80 +#define HWIO_IPA_STATE_AGGR_IDLE_SHFT 0x7 +#define HWIO_IPA_STATE_IPA_NOC_IDLE_BMSK 0x40 +#define HWIO_IPA_STATE_IPA_NOC_IDLE_SHFT 0x6 +#define HWIO_IPA_STATE_IPA_HW_SNIFFER_IDLE_BMSK 0x20 +#define HWIO_IPA_STATE_IPA_HW_SNIFFER_IDLE_SHFT 0x5 +#define HWIO_IPA_STATE_GSI_IDLE_BMSK 0x10 +#define HWIO_IPA_STATE_GSI_IDLE_SHFT 0x4 +#define HWIO_IPA_STATE_IPA_CONS_DPL_FIFO_IDLE_BMSK 0x8 +#define HWIO_IPA_STATE_IPA_CONS_DPL_FIFO_IDLE_SHFT 0x3 +#define HWIO_IPA_STATE_TX_IDLE_BMSK 0x4 +#define HWIO_IPA_STATE_TX_IDLE_SHFT 0x2 +#define HWIO_IPA_STATE_RX_IDLE_BMSK 0x2 +#define HWIO_IPA_STATE_RX_IDLE_SHFT 0x1 +#define HWIO_IPA_STATE_RX_WAIT_BMSK 0x1 +#define HWIO_IPA_STATE_RX_WAIT_SHFT 0x0 + +#define HWIO_IPA_STATE_GSI_AOS_ADDR (IPA_CFG_REG_BASE + 0x000000d8) +#define HWIO_IPA_STATE_GSI_AOS_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000d8) +#define HWIO_IPA_STATE_GSI_AOS_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000d8) +#define HWIO_IPA_STATE_GSI_AOS_RMSK 0x3 +#define HWIO_IPA_STATE_GSI_AOS_ATTR 0x1 +#define HWIO_IPA_STATE_GSI_AOS_IN \ + in_dword_masked(HWIO_IPA_STATE_GSI_AOS_ADDR, HWIO_IPA_STATE_GSI_AOS_RMSK) +#define HWIO_IPA_STATE_GSI_AOS_INM(m) \ + in_dword_masked(HWIO_IPA_STATE_GSI_AOS_ADDR, m) +#define HWIO_IPA_STATE_GSI_AOS_IPA_GSI_AOS_NLO_FSM_IDLE_BMSK 0x2 +#define HWIO_IPA_STATE_GSI_AOS_IPA_GSI_AOS_NLO_FSM_IDLE_SHFT 0x1 +#define HWIO_IPA_STATE_GSI_AOS_IPA_GSI_AOS_FSM_IDLE_BMSK 0x1 +#define HWIO_IPA_STATE_GSI_AOS_IPA_GSI_AOS_FSM_IDLE_SHFT 0x0 + +#define HWIO_IPA_STATE_COAL_SLAVE_ADDR (IPA_CFG_REG_BASE + 0x000000dc) +#define HWIO_IPA_STATE_COAL_SLAVE_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000dc) +#define HWIO_IPA_STATE_COAL_SLAVE_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000dc) +#define HWIO_IPA_STATE_COAL_SLAVE_RMSK 0xffff +#define HWIO_IPA_STATE_COAL_SLAVE_ATTR 0x1 +#define HWIO_IPA_STATE_COAL_SLAVE_IN \ + in_dword_masked(HWIO_IPA_STATE_COAL_SLAVE_ADDR, HWIO_IPA_STATE_COAL_SLAVE_RMSK) +#define HWIO_IPA_STATE_COAL_SLAVE_INM(m) \ + in_dword_masked(HWIO_IPA_STATE_COAL_SLAVE_ADDR, m) +#define HWIO_IPA_STATE_COAL_SLAVE_COAL_SLAVE_OPEN_FRAME_BMSK 0xffff +#define HWIO_IPA_STATE_COAL_SLAVE_COAL_SLAVE_OPEN_FRAME_SHFT 0x0 + +#define HWIO_IPA_STATE_GSI_IF_ADDR (IPA_CFG_REG_BASE + 0x000000e0) +#define HWIO_IPA_STATE_GSI_IF_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000e0) +#define HWIO_IPA_STATE_GSI_IF_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000e0) +#define HWIO_IPA_STATE_GSI_IF_RMSK 0x301ff +#define HWIO_IPA_STATE_GSI_IF_ATTR 0x1 +#define HWIO_IPA_STATE_GSI_IF_IN \ + in_dword_masked(HWIO_IPA_STATE_GSI_IF_ADDR, HWIO_IPA_STATE_GSI_IF_RMSK) +#define HWIO_IPA_STATE_GSI_IF_INM(m) \ + in_dword_masked(HWIO_IPA_STATE_GSI_IF_ADDR, m) +#define HWIO_IPA_STATE_GSI_IF_IPA_GSI_SKIP_FSM_BMSK 0x30000 +#define HWIO_IPA_STATE_GSI_IF_IPA_GSI_SKIP_FSM_SHFT 0x10 +#define HWIO_IPA_STATE_GSI_IF_IPA_GSI_TOGGLE_FSM_IDLE_BMSK 0x100 +#define HWIO_IPA_STATE_GSI_IF_IPA_GSI_TOGGLE_FSM_IDLE_SHFT 0x8 +#define HWIO_IPA_STATE_GSI_IF_IPA_GSI_PROD_FSM_TX_1_BMSK 0xf0 +#define HWIO_IPA_STATE_GSI_IF_IPA_GSI_PROD_FSM_TX_1_SHFT 0x4 +#define HWIO_IPA_STATE_GSI_IF_IPA_GSI_PROD_FSM_TX_0_BMSK 0xf +#define HWIO_IPA_STATE_GSI_IF_IPA_GSI_PROD_FSM_TX_0_SHFT 0x0 + +#define HWIO_IPA_STATE_RQOS_ADDR (IPA_CFG_REG_BASE + 0x000000e4) +#define HWIO_IPA_STATE_RQOS_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000e4) +#define HWIO_IPA_STATE_RQOS_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000e4) +#define HWIO_IPA_STATE_RQOS_RMSK 0x1f +#define HWIO_IPA_STATE_RQOS_ATTR 0x1 +#define HWIO_IPA_STATE_RQOS_IN \ + in_dword_masked(HWIO_IPA_STATE_RQOS_ADDR, HWIO_IPA_STATE_RQOS_RMSK) +#define HWIO_IPA_STATE_RQOS_INM(m) \ + in_dword_masked(HWIO_IPA_STATE_RQOS_ADDR, m) +#define HWIO_IPA_STATE_RQOS_IPA_RQOS_FIFO_POP_IDLE_BMSK 0x10 +#define HWIO_IPA_STATE_RQOS_IPA_RQOS_FIFO_POP_IDLE_SHFT 0x4 +#define HWIO_IPA_STATE_RQOS_IPA_RQOS_FIFO_EMPTY_BMSK 0x8 +#define HWIO_IPA_STATE_RQOS_IPA_RQOS_FIFO_EMPTY_SHFT 0x3 +#define HWIO_IPA_STATE_RQOS_IPA_RQOS_SW_IDLE_BMSK 0x4 +#define HWIO_IPA_STATE_RQOS_IPA_RQOS_SW_IDLE_SHFT 0x2 +#define HWIO_IPA_STATE_RQOS_IPA_RQOS_AS_IDLE_BMSK 0x2 +#define HWIO_IPA_STATE_RQOS_IPA_RQOS_AS_IDLE_SHFT 0x1 +#define HWIO_IPA_STATE_RQOS_IPA_RQOS_NAS_IDLE_BMSK 0x1 +#define HWIO_IPA_STATE_RQOS_IPA_RQOS_NAS_IDLE_SHFT 0x0 + +#define HWIO_IPA_STATE_GSI_IF_CONS_ADDR (IPA_CFG_REG_BASE + 0x000000e8) +#define HWIO_IPA_STATE_GSI_IF_CONS_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000e8) +#define HWIO_IPA_STATE_GSI_IF_CONS_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000e8) +#define HWIO_IPA_STATE_GSI_IF_CONS_RMSK 0xff +#define HWIO_IPA_STATE_GSI_IF_CONS_ATTR 0x1 +#define HWIO_IPA_STATE_GSI_IF_CONS_IN \ + in_dword_masked(HWIO_IPA_STATE_GSI_IF_CONS_ADDR, HWIO_IPA_STATE_GSI_IF_CONS_RMSK) +#define HWIO_IPA_STATE_GSI_IF_CONS_INM(m) \ + in_dword_masked(HWIO_IPA_STATE_GSI_IF_CONS_ADDR, m) +#define HWIO_IPA_STATE_GSI_IF_CONS_IPA_STATE_GSI_IF_CONS_CACHE_VLD_BMSK 0xfe +#define HWIO_IPA_STATE_GSI_IF_CONS_IPA_STATE_GSI_IF_CONS_CACHE_VLD_SHFT 0x1 +#define HWIO_IPA_STATE_GSI_IF_CONS_IPA_STATE_GSI_IF_CONS_STATE_IDLE_BMSK 0x1 +#define HWIO_IPA_STATE_GSI_IF_CONS_IPA_STATE_GSI_IF_CONS_STATE_IDLE_SHFT 0x0 + +#define HWIO_IPA_STATE_FETCHER_MASK_1_ADDR (IPA_CFG_REG_BASE + 0x000000ec) +#define HWIO_IPA_STATE_FETCHER_MASK_1_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000ec) +#define HWIO_IPA_STATE_FETCHER_MASK_1_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000ec) +#define HWIO_IPA_STATE_FETCHER_MASK_1_RMSK 0xffffffff +#define HWIO_IPA_STATE_FETCHER_MASK_1_ATTR 0x1 +#define HWIO_IPA_STATE_FETCHER_MASK_1_IN \ + in_dword_masked(HWIO_IPA_STATE_FETCHER_MASK_1_ADDR, HWIO_IPA_STATE_FETCHER_MASK_1_RMSK) +#define HWIO_IPA_STATE_FETCHER_MASK_1_INM(m) \ + in_dword_masked(HWIO_IPA_STATE_FETCHER_MASK_1_ADDR, m) +#define HWIO_IPA_STATE_FETCHER_MASK_1_MASK_QUEUE_NO_SPACE_DPL_FIFO_BMSK 0xff000000 +#define HWIO_IPA_STATE_FETCHER_MASK_1_MASK_QUEUE_NO_SPACE_DPL_FIFO_SHFT 0x18 +#define HWIO_IPA_STATE_FETCHER_MASK_1_MASK_QUEUE_STEP_MODE_BMSK 0xff0000 +#define HWIO_IPA_STATE_FETCHER_MASK_1_MASK_QUEUE_STEP_MODE_SHFT 0x10 +#define HWIO_IPA_STATE_FETCHER_MASK_1_MASK_QUEUE_ARB_LOCK_BMSK 0xff00 +#define HWIO_IPA_STATE_FETCHER_MASK_1_MASK_QUEUE_ARB_LOCK_SHFT 0x8 +#define HWIO_IPA_STATE_FETCHER_MASK_1_MASK_QUEUE_NO_RESOURCES_ACK_ENTRY_BMSK 0xff +#define HWIO_IPA_STATE_FETCHER_MASK_1_MASK_QUEUE_NO_RESOURCES_ACK_ENTRY_SHFT 0x0 + +#define HWIO_IPA_STATE_FETCHER_MASK_2_ADDR (IPA_CFG_REG_BASE + 0x000000f0) +#define HWIO_IPA_STATE_FETCHER_MASK_2_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000f0) +#define HWIO_IPA_STATE_FETCHER_MASK_2_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000f0) +#define HWIO_IPA_STATE_FETCHER_MASK_2_RMSK 0xffffff +#define HWIO_IPA_STATE_FETCHER_MASK_2_ATTR 0x1 +#define HWIO_IPA_STATE_FETCHER_MASK_2_IN \ + in_dword_masked(HWIO_IPA_STATE_FETCHER_MASK_2_ADDR, HWIO_IPA_STATE_FETCHER_MASK_2_RMSK) +#define HWIO_IPA_STATE_FETCHER_MASK_2_INM(m) \ + in_dword_masked(HWIO_IPA_STATE_FETCHER_MASK_2_ADDR, m) +#define HWIO_IPA_STATE_FETCHER_MASK_2_MASK_QUEUE_NO_SPACE_RQOS_FIFO_BMSK 0xff0000 +#define HWIO_IPA_STATE_FETCHER_MASK_2_MASK_QUEUE_NO_SPACE_RQOS_FIFO_SHFT 0x10 +#define HWIO_IPA_STATE_FETCHER_MASK_2_MASK_QUEUE_DRBIP_PKT_EXCEED_MAX_SIZE_BMSK 0xff00 +#define HWIO_IPA_STATE_FETCHER_MASK_2_MASK_QUEUE_DRBIP_PKT_EXCEED_MAX_SIZE_SHFT 0x8 +#define HWIO_IPA_STATE_FETCHER_MASK_2_MASK_QUEUE_DRBIP_NO_DATA_SECTORS_BMSK 0xff +#define HWIO_IPA_STATE_FETCHER_MASK_2_MASK_QUEUE_DRBIP_NO_DATA_SECTORS_SHFT 0x0 + +#define HWIO_IPA_STATE_CONS_DPL_FIFO_ADDR (IPA_CFG_REG_BASE + 0x000000f4) +#define HWIO_IPA_STATE_CONS_DPL_FIFO_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000f4) +#define HWIO_IPA_STATE_CONS_DPL_FIFO_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000f4) +#define HWIO_IPA_STATE_CONS_DPL_FIFO_RMSK 0x7 +#define HWIO_IPA_STATE_CONS_DPL_FIFO_ATTR 0x1 +#define HWIO_IPA_STATE_CONS_DPL_FIFO_IN \ + in_dword_masked(HWIO_IPA_STATE_CONS_DPL_FIFO_ADDR, HWIO_IPA_STATE_CONS_DPL_FIFO_RMSK) +#define HWIO_IPA_STATE_CONS_DPL_FIFO_INM(m) \ + in_dword_masked(HWIO_IPA_STATE_CONS_DPL_FIFO_ADDR, m) +#define HWIO_IPA_STATE_CONS_DPL_FIFO_POP_FSM_STATE_BMSK 0x7 +#define HWIO_IPA_STATE_CONS_DPL_FIFO_POP_FSM_STATE_SHFT 0x0 + +#define HWIO_IPA_STATE_COAL_MASTER_ADDR (IPA_CFG_REG_BASE + 0x000000f8) +#define HWIO_IPA_STATE_COAL_MASTER_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000f8) +#define HWIO_IPA_STATE_COAL_MASTER_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000f8) +#define HWIO_IPA_STATE_COAL_MASTER_RMSK 0x3ffffff +#define HWIO_IPA_STATE_COAL_MASTER_ATTR 0x1 +#define HWIO_IPA_STATE_COAL_MASTER_IN \ + in_dword_masked(HWIO_IPA_STATE_COAL_MASTER_ADDR, HWIO_IPA_STATE_COAL_MASTER_RMSK) +#define HWIO_IPA_STATE_COAL_MASTER_INM(m) \ + in_dword_masked(HWIO_IPA_STATE_COAL_MASTER_ADDR, m) +#define HWIO_IPA_STATE_COAL_MASTER_LRU_VP_BMSK 0x3f00000 +#define HWIO_IPA_STATE_COAL_MASTER_LRU_VP_SHFT 0x14 +#define HWIO_IPA_STATE_COAL_MASTER_INIT_VP_FSM_STATE_BMSK 0xf0000 +#define HWIO_IPA_STATE_COAL_MASTER_INIT_VP_FSM_STATE_SHFT 0x10 +#define HWIO_IPA_STATE_COAL_MASTER_CHECK_FIT_FSM_STATE_BMSK 0xf000 +#define HWIO_IPA_STATE_COAL_MASTER_CHECK_FIT_FSM_STATE_SHFT 0xc +#define HWIO_IPA_STATE_COAL_MASTER_HASH_CALC_FSM_STATE_BMSK 0xf00 +#define HWIO_IPA_STATE_COAL_MASTER_HASH_CALC_FSM_STATE_SHFT 0x8 +#define HWIO_IPA_STATE_COAL_MASTER_FIND_OPEN_FSM_STATE_BMSK 0xf0 +#define HWIO_IPA_STATE_COAL_MASTER_FIND_OPEN_FSM_STATE_SHFT 0x4 +#define HWIO_IPA_STATE_COAL_MASTER_MAIN_FSM_STATE_BMSK 0xf +#define HWIO_IPA_STATE_COAL_MASTER_MAIN_FSM_STATE_SHFT 0x0 + +#define HWIO_IPA_STATE_COAL_MASTER_1_ADDR (IPA_CFG_REG_BASE + 0x000000fc) +#define HWIO_IPA_STATE_COAL_MASTER_1_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000fc) +#define HWIO_IPA_STATE_COAL_MASTER_1_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000fc) +#define HWIO_IPA_STATE_COAL_MASTER_1_RMSK 0x3fffffff +#define HWIO_IPA_STATE_COAL_MASTER_1_ATTR 0x1 +#define HWIO_IPA_STATE_COAL_MASTER_1_IN \ + in_dword_masked(HWIO_IPA_STATE_COAL_MASTER_1_ADDR, HWIO_IPA_STATE_COAL_MASTER_1_RMSK) +#define HWIO_IPA_STATE_COAL_MASTER_1_INM(m) \ + in_dword_masked(HWIO_IPA_STATE_COAL_MASTER_1_ADDR, m) +#define HWIO_IPA_STATE_COAL_MASTER_1_ARBITER_STATE_BMSK 0x3c000000 +#define HWIO_IPA_STATE_COAL_MASTER_1_ARBITER_STATE_SHFT 0x1a +#define HWIO_IPA_STATE_COAL_MASTER_1_CHECK_FIT_FSM_STATE_BMSK 0x3c00000 +#define HWIO_IPA_STATE_COAL_MASTER_1_CHECK_FIT_FSM_STATE_SHFT 0x16 +#define HWIO_IPA_STATE_COAL_MASTER_1_CHECK_FIT_RD_CTX_LINE_BMSK 0x3f0000 +#define HWIO_IPA_STATE_COAL_MASTER_1_CHECK_FIT_RD_CTX_LINE_SHFT 0x10 +#define HWIO_IPA_STATE_COAL_MASTER_1_INIT_VP_FSM_STATE_BMSK 0xf000 +#define HWIO_IPA_STATE_COAL_MASTER_1_INIT_VP_FSM_STATE_SHFT 0xc +#define HWIO_IPA_STATE_COAL_MASTER_1_INIT_VP_RD_PKT_LINE_BMSK 0xfc0 +#define HWIO_IPA_STATE_COAL_MASTER_1_INIT_VP_RD_PKT_LINE_SHFT 0x6 +#define HWIO_IPA_STATE_COAL_MASTER_1_INIT_VP_WR_CTX_LINE_BMSK 0x3f +#define HWIO_IPA_STATE_COAL_MASTER_1_INIT_VP_WR_CTX_LINE_SHFT 0x0 + +#define HWIO_IPA_STATE_NLO_AGGR_ADDR (IPA_CFG_REG_BASE + 0x00000100) +#define HWIO_IPA_STATE_NLO_AGGR_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000100) +#define HWIO_IPA_STATE_NLO_AGGR_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000100) +#define HWIO_IPA_STATE_NLO_AGGR_RMSK 0xffffffff +#define HWIO_IPA_STATE_NLO_AGGR_ATTR 0x1 +#define HWIO_IPA_STATE_NLO_AGGR_IN \ + in_dword_masked(HWIO_IPA_STATE_NLO_AGGR_ADDR, HWIO_IPA_STATE_NLO_AGGR_RMSK) +#define HWIO_IPA_STATE_NLO_AGGR_INM(m) \ + in_dword_masked(HWIO_IPA_STATE_NLO_AGGR_ADDR, m) +#define HWIO_IPA_STATE_NLO_AGGR_NLO_AGGR_STATE_BMSK 0xffffffff +#define HWIO_IPA_STATE_NLO_AGGR_NLO_AGGR_STATE_SHFT 0x0 + +#define HWIO_IPA_STATE_CTXH_ADDR (IPA_CFG_REG_BASE + 0x00000104) +#define HWIO_IPA_STATE_CTXH_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000104) +#define HWIO_IPA_STATE_CTXH_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000104) +#define HWIO_IPA_STATE_CTXH_RMSK 0x3 +#define HWIO_IPA_STATE_CTXH_ATTR 0x1 +#define HWIO_IPA_STATE_CTXH_IN \ + in_dword_masked(HWIO_IPA_STATE_CTXH_ADDR, HWIO_IPA_STATE_CTXH_RMSK) +#define HWIO_IPA_STATE_CTXH_INM(m) \ + in_dword_masked(HWIO_IPA_STATE_CTXH_ADDR, m) +#define HWIO_IPA_STATE_CTXH_IPA_CTXH_WR_IDLE_BMSK 0x2 +#define HWIO_IPA_STATE_CTXH_IPA_CTXH_WR_IDLE_SHFT 0x1 +#define HWIO_IPA_STATE_CTXH_IPA_CTXH_RD_IDLE_BMSK 0x1 +#define HWIO_IPA_STATE_CTXH_IPA_CTXH_RD_IDLE_SHFT 0x0 + +#define HWIO_IPA_STATE_UC_QMB_ADDR (IPA_CFG_REG_BASE + 0x00000108) +#define HWIO_IPA_STATE_UC_QMB_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000108) +#define HWIO_IPA_STATE_UC_QMB_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000108) +#define HWIO_IPA_STATE_UC_QMB_RMSK 0x1ff01ff +#define HWIO_IPA_STATE_UC_QMB_ATTR 0x1 +#define HWIO_IPA_STATE_UC_QMB_IN \ + in_dword_masked(HWIO_IPA_STATE_UC_QMB_ADDR, HWIO_IPA_STATE_UC_QMB_RMSK) +#define HWIO_IPA_STATE_UC_QMB_INM(m) \ + in_dword_masked(HWIO_IPA_STATE_UC_QMB_ADDR, m) +#define HWIO_IPA_STATE_UC_QMB_QUEUE_1_IDLE_BMSK 0x1000000 +#define HWIO_IPA_STATE_UC_QMB_QUEUE_1_IDLE_SHFT 0x18 +#define HWIO_IPA_STATE_UC_QMB_CMD_FIFO_FULL_QUEUE_1_BMSK 0x800000 +#define HWIO_IPA_STATE_UC_QMB_CMD_FIFO_FULL_QUEUE_1_SHFT 0x17 +#define HWIO_IPA_STATE_UC_QMB_CMD_FIFO_EMPTY_QUEUE_1_BMSK 0x400000 +#define HWIO_IPA_STATE_UC_QMB_CMD_FIFO_EMPTY_QUEUE_1_SHFT 0x16 +#define HWIO_IPA_STATE_UC_QMB_COMP_FIFO_FULL_QUEUE_1_BMSK 0x200000 +#define HWIO_IPA_STATE_UC_QMB_COMP_FIFO_FULL_QUEUE_1_SHFT 0x15 +#define HWIO_IPA_STATE_UC_QMB_COMP_FIFO_EMPTY_QUEUE_1_BMSK 0x100000 +#define HWIO_IPA_STATE_UC_QMB_COMP_FIFO_EMPTY_QUEUE_1_SHFT 0x14 +#define HWIO_IPA_STATE_UC_QMB_OT_TABLE_FULL_QUEUE_1_BMSK 0x80000 +#define HWIO_IPA_STATE_UC_QMB_OT_TABLE_FULL_QUEUE_1_SHFT 0x13 +#define HWIO_IPA_STATE_UC_QMB_OT_TABLE_EMPTY_QUEUE_1_BMSK 0x40000 +#define HWIO_IPA_STATE_UC_QMB_OT_TABLE_EMPTY_QUEUE_1_SHFT 0x12 +#define HWIO_IPA_STATE_UC_QMB_CTRL_FSM_STATE_QUEUE_1_BMSK 0x30000 +#define HWIO_IPA_STATE_UC_QMB_CTRL_FSM_STATE_QUEUE_1_SHFT 0x10 +#define HWIO_IPA_STATE_UC_QMB_QUEUE_0_IDLE_BMSK 0x100 +#define HWIO_IPA_STATE_UC_QMB_QUEUE_0_IDLE_SHFT 0x8 +#define HWIO_IPA_STATE_UC_QMB_CMD_FIFO_FULL_QUEUE_0_BMSK 0x80 +#define HWIO_IPA_STATE_UC_QMB_CMD_FIFO_FULL_QUEUE_0_SHFT 0x7 +#define HWIO_IPA_STATE_UC_QMB_CMD_FIFO_EMPTY_QUEUE_0_BMSK 0x40 +#define HWIO_IPA_STATE_UC_QMB_CMD_FIFO_EMPTY_QUEUE_0_SHFT 0x6 +#define HWIO_IPA_STATE_UC_QMB_COMP_FIFO_FULL_QUEUE_0_BMSK 0x20 +#define HWIO_IPA_STATE_UC_QMB_COMP_FIFO_FULL_QUEUE_0_SHFT 0x5 +#define HWIO_IPA_STATE_UC_QMB_COMP_FIFO_EMPTY_QUEUE_0_BMSK 0x10 +#define HWIO_IPA_STATE_UC_QMB_COMP_FIFO_EMPTY_QUEUE_0_SHFT 0x4 +#define HWIO_IPA_STATE_UC_QMB_OT_TABLE_FULL_QUEUE_0_BMSK 0x8 +#define HWIO_IPA_STATE_UC_QMB_OT_TABLE_FULL_QUEUE_0_SHFT 0x3 +#define HWIO_IPA_STATE_UC_QMB_OT_TABLE_EMPTY_QUEUE_0_BMSK 0x4 +#define HWIO_IPA_STATE_UC_QMB_OT_TABLE_EMPTY_QUEUE_0_SHFT 0x2 +#define HWIO_IPA_STATE_UC_QMB_CTRL_FSM_STATE_QUEUE_0_BMSK 0x3 +#define HWIO_IPA_STATE_UC_QMB_CTRL_FSM_STATE_QUEUE_0_SHFT 0x0 + +#define HWIO_IPA_STATE_DRBIP_ADDR (IPA_CFG_REG_BASE + 0x0000010c) +#define HWIO_IPA_STATE_DRBIP_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000010c) +#define HWIO_IPA_STATE_DRBIP_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000010c) +#define HWIO_IPA_STATE_DRBIP_RMSK 0xf0107 +#define HWIO_IPA_STATE_DRBIP_ATTR 0x1 +#define HWIO_IPA_STATE_DRBIP_IN \ + in_dword_masked(HWIO_IPA_STATE_DRBIP_ADDR, HWIO_IPA_STATE_DRBIP_RMSK) +#define HWIO_IPA_STATE_DRBIP_INM(m) \ + in_dword_masked(HWIO_IPA_STATE_DRBIP_ADDR, m) +#define HWIO_IPA_STATE_DRBIP_DRBIP_PKT_IDLE_BMSK 0xf0000 +#define HWIO_IPA_STATE_DRBIP_DRBIP_PKT_IDLE_SHFT 0x10 +#define HWIO_IPA_STATE_DRBIP_DRBIP_DCPH_IDLE_BMSK 0x100 +#define HWIO_IPA_STATE_DRBIP_DRBIP_DCPH_IDLE_SHFT 0x8 +#define HWIO_IPA_STATE_DRBIP_DRBIP_DMAR_IDLE_BMSK 0x7 +#define HWIO_IPA_STATE_DRBIP_DRBIP_DMAR_IDLE_SHFT 0x0 + +#define HWIO_IPA_STATE_TX_HOLB_MASK_DPS_TX_1_ADDR (IPA_CFG_REG_BASE + 0x00000110) +#define HWIO_IPA_STATE_TX_HOLB_MASK_DPS_TX_1_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000110) +#define HWIO_IPA_STATE_TX_HOLB_MASK_DPS_TX_1_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000110) +#define HWIO_IPA_STATE_TX_HOLB_MASK_DPS_TX_1_RMSK 0xffffffff +#define HWIO_IPA_STATE_TX_HOLB_MASK_DPS_TX_1_ATTR 0x1 +#define HWIO_IPA_STATE_TX_HOLB_MASK_DPS_TX_1_IN \ + in_dword_masked(HWIO_IPA_STATE_TX_HOLB_MASK_DPS_TX_1_ADDR, HWIO_IPA_STATE_TX_HOLB_MASK_DPS_TX_1_RMSK) +#define HWIO_IPA_STATE_TX_HOLB_MASK_DPS_TX_1_INM(m) \ + in_dword_masked(HWIO_IPA_STATE_TX_HOLB_MASK_DPS_TX_1_ADDR, m) +#define HWIO_IPA_STATE_TX_HOLB_MASK_DPS_TX_1_PRODUCER_MASK_32_64_BMSK 0xffffffff +#define HWIO_IPA_STATE_TX_HOLB_MASK_DPS_TX_1_PRODUCER_MASK_32_64_SHFT 0x0 + +#define HWIO_IPA_STATE_COAL_MASTER_2_ADDR (IPA_CFG_REG_BASE + 0x00000114) +#define HWIO_IPA_STATE_COAL_MASTER_2_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000114) +#define HWIO_IPA_STATE_COAL_MASTER_2_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000114) +#define HWIO_IPA_STATE_COAL_MASTER_2_RMSK 0xffff +#define HWIO_IPA_STATE_COAL_MASTER_2_ATTR 0x1 +#define HWIO_IPA_STATE_COAL_MASTER_2_IN \ + in_dword_masked(HWIO_IPA_STATE_COAL_MASTER_2_ADDR, HWIO_IPA_STATE_COAL_MASTER_2_RMSK) +#define HWIO_IPA_STATE_COAL_MASTER_2_INM(m) \ + in_dword_masked(HWIO_IPA_STATE_COAL_MASTER_2_ADDR, m) +#define HWIO_IPA_STATE_COAL_MASTER_2_VP_TIMER_EXPIRED_BMSK 0xffff +#define HWIO_IPA_STATE_COAL_MASTER_2_VP_TIMER_EXPIRED_SHFT 0x0 + +#define HWIO_IPA_STATE_COAL_MASTER_3_ADDR (IPA_CFG_REG_BASE + 0x00000118) +#define HWIO_IPA_STATE_COAL_MASTER_3_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000118) +#define HWIO_IPA_STATE_COAL_MASTER_3_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000118) +#define HWIO_IPA_STATE_COAL_MASTER_3_RMSK 0xffff +#define HWIO_IPA_STATE_COAL_MASTER_3_ATTR 0x1 +#define HWIO_IPA_STATE_COAL_MASTER_3_IN \ + in_dword_masked(HWIO_IPA_STATE_COAL_MASTER_3_ADDR, HWIO_IPA_STATE_COAL_MASTER_3_RMSK) +#define HWIO_IPA_STATE_COAL_MASTER_3_INM(m) \ + in_dword_masked(HWIO_IPA_STATE_COAL_MASTER_3_ADDR, m) +#define HWIO_IPA_STATE_COAL_MASTER_3_VP_VLD_BMSK 0xffff +#define HWIO_IPA_STATE_COAL_MASTER_3_VP_VLD_SHFT 0x0 + +#define HWIO_IPA_STATE_TSP_ADDR (IPA_CFG_REG_BASE + 0x0000011c) +#define HWIO_IPA_STATE_TSP_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000011c) +#define HWIO_IPA_STATE_TSP_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000011c) +#define HWIO_IPA_STATE_TSP_RMSK 0x7f +#define HWIO_IPA_STATE_TSP_ATTR 0x1 +#define HWIO_IPA_STATE_TSP_IN \ + in_dword_masked(HWIO_IPA_STATE_TSP_ADDR, HWIO_IPA_STATE_TSP_RMSK) +#define HWIO_IPA_STATE_TSP_INM(m) \ + in_dword_masked(HWIO_IPA_STATE_TSP_ADDR, m) +#define HWIO_IPA_STATE_TSP_QUEUE_MNGR_BLOCK_CTRL_IDLE_BMSK 0x40 +#define HWIO_IPA_STATE_TSP_QUEUE_MNGR_BLOCK_CTRL_IDLE_SHFT 0x6 +#define HWIO_IPA_STATE_TSP_QUEUE_MNGR_TAIL_IDLE_BMSK 0x20 +#define HWIO_IPA_STATE_TSP_QUEUE_MNGR_TAIL_IDLE_SHFT 0x5 +#define HWIO_IPA_STATE_TSP_QUEUE_MNGR_SHARED_IDLE_BMSK 0x10 +#define HWIO_IPA_STATE_TSP_QUEUE_MNGR_SHARED_IDLE_SHFT 0x4 +#define HWIO_IPA_STATE_TSP_QUEUE_MNGR_HEAD_IDLE_BMSK 0x8 +#define HWIO_IPA_STATE_TSP_QUEUE_MNGR_HEAD_IDLE_SHFT 0x3 +#define HWIO_IPA_STATE_TSP_QUEUE_MNGR_IDLE_BMSK 0x4 +#define HWIO_IPA_STATE_TSP_QUEUE_MNGR_IDLE_SHFT 0x2 +#define HWIO_IPA_STATE_TSP_TRAFFIC_SHAPER_FIFO_EMPTY_BMSK 0x2 +#define HWIO_IPA_STATE_TSP_TRAFFIC_SHAPER_FIFO_EMPTY_SHFT 0x1 +#define HWIO_IPA_STATE_TSP_TRAFFIC_SHAPER_IDLE_BMSK 0x1 +#define HWIO_IPA_STATE_TSP_TRAFFIC_SHAPER_IDLE_SHFT 0x0 + +#define HWIO_IPA_STATE_AGGR_ACTIVE_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000120 + 0x4 * (n)) +#define HWIO_IPA_STATE_AGGR_ACTIVE_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000120 + 0x4 * (n)) +#define HWIO_IPA_STATE_AGGR_ACTIVE_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000120 + 0x4 * (n)) +#define HWIO_IPA_STATE_AGGR_ACTIVE_n_RMSK 0xffffffff +#define HWIO_IPA_STATE_AGGR_ACTIVE_n_MAXn 1 +#define HWIO_IPA_STATE_AGGR_ACTIVE_n_ATTR 0x1 +#define HWIO_IPA_STATE_AGGR_ACTIVE_n_INI(n) \ + in_dword_masked(HWIO_IPA_STATE_AGGR_ACTIVE_n_ADDR(n), HWIO_IPA_STATE_AGGR_ACTIVE_n_RMSK) +#define HWIO_IPA_STATE_AGGR_ACTIVE_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_STATE_AGGR_ACTIVE_n_ADDR(n), mask) +#define HWIO_IPA_STATE_AGGR_ACTIVE_n_ENDPOINTS_BMSK 0xffffffff +#define HWIO_IPA_STATE_AGGR_ACTIVE_n_ENDPOINTS_SHFT 0x0 + +#define HWIO_IPA_STATE_GSI_TLV_FIFO_EMPTY_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000140 + 0x4 * (n)) +#define HWIO_IPA_STATE_GSI_TLV_FIFO_EMPTY_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000140 + 0x4 * (n)) +#define HWIO_IPA_STATE_GSI_TLV_FIFO_EMPTY_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000140 + 0x4 * (n)) +#define HWIO_IPA_STATE_GSI_TLV_FIFO_EMPTY_n_RMSK 0xffffffff +#define HWIO_IPA_STATE_GSI_TLV_FIFO_EMPTY_n_MAXn 1 +#define HWIO_IPA_STATE_GSI_TLV_FIFO_EMPTY_n_ATTR 0x1 +#define HWIO_IPA_STATE_GSI_TLV_FIFO_EMPTY_n_INI(n) \ + in_dword_masked(HWIO_IPA_STATE_GSI_TLV_FIFO_EMPTY_n_ADDR(n), HWIO_IPA_STATE_GSI_TLV_FIFO_EMPTY_n_RMSK) +#define HWIO_IPA_STATE_GSI_TLV_FIFO_EMPTY_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_STATE_GSI_TLV_FIFO_EMPTY_n_ADDR(n), mask) +#define HWIO_IPA_STATE_GSI_TLV_FIFO_EMPTY_n_PIPE_FIFO_EMPTY_BMSK 0xffffffff +#define HWIO_IPA_STATE_GSI_TLV_FIFO_EMPTY_n_PIPE_FIFO_EMPTY_SHFT 0x0 + +#define HWIO_IPA_STATE_GSI_AOS_FIFO_EMPTY_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000160 + 0x4 * (n)) +#define HWIO_IPA_STATE_GSI_AOS_FIFO_EMPTY_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000160 + 0x4 * (n)) +#define HWIO_IPA_STATE_GSI_AOS_FIFO_EMPTY_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000160 + 0x4 * (n)) +#define HWIO_IPA_STATE_GSI_AOS_FIFO_EMPTY_n_RMSK 0xffffffff +#define HWIO_IPA_STATE_GSI_AOS_FIFO_EMPTY_n_MAXn 1 +#define HWIO_IPA_STATE_GSI_AOS_FIFO_EMPTY_n_ATTR 0x1 +#define HWIO_IPA_STATE_GSI_AOS_FIFO_EMPTY_n_INI(n) \ + in_dword_masked(HWIO_IPA_STATE_GSI_AOS_FIFO_EMPTY_n_ADDR(n), HWIO_IPA_STATE_GSI_AOS_FIFO_EMPTY_n_RMSK) +#define HWIO_IPA_STATE_GSI_AOS_FIFO_EMPTY_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_STATE_GSI_AOS_FIFO_EMPTY_n_ADDR(n), mask) +#define HWIO_IPA_STATE_GSI_AOS_FIFO_EMPTY_n_PIPE_FIFO_EMPTY_BMSK 0xffffffff +#define HWIO_IPA_STATE_GSI_AOS_FIFO_EMPTY_n_PIPE_FIFO_EMPTY_SHFT 0x0 + +#define HWIO_IPA_STATE_DRBIP_DROP_STATE_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000180 + 0x4 * (n)) +#define HWIO_IPA_STATE_DRBIP_DROP_STATE_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000180 + 0x4 * (n)) +#define HWIO_IPA_STATE_DRBIP_DROP_STATE_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000180 + 0x4 * (n)) +#define HWIO_IPA_STATE_DRBIP_DROP_STATE_n_RMSK 0xffffffff +#define HWIO_IPA_STATE_DRBIP_DROP_STATE_n_MAXn 1 +#define HWIO_IPA_STATE_DRBIP_DROP_STATE_n_ATTR 0x1 +#define HWIO_IPA_STATE_DRBIP_DROP_STATE_n_INI(n) \ + in_dword_masked(HWIO_IPA_STATE_DRBIP_DROP_STATE_n_ADDR(n), HWIO_IPA_STATE_DRBIP_DROP_STATE_n_RMSK) +#define HWIO_IPA_STATE_DRBIP_DROP_STATE_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_STATE_DRBIP_DROP_STATE_n_ADDR(n), mask) +#define HWIO_IPA_STATE_DRBIP_DROP_STATE_n_CONSUMER_PIPE_DROP_STATE_BMSK 0xffffffff +#define HWIO_IPA_STATE_DRBIP_DROP_STATE_n_CONSUMER_PIPE_DROP_STATE_SHFT 0x0 + +#define HWIO_IPA_STATE_DFETCHER_MASK_0_n_ADDR(n) (IPA_CFG_REG_BASE + 0x000001a0 + 0x4 * (n)) +#define HWIO_IPA_STATE_DFETCHER_MASK_0_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x000001a0 + 0x4 * (n)) +#define HWIO_IPA_STATE_DFETCHER_MASK_0_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x000001a0 + 0x4 * (n)) +#define HWIO_IPA_STATE_DFETCHER_MASK_0_n_RMSK 0xffffffff +#define HWIO_IPA_STATE_DFETCHER_MASK_0_n_MAXn 1 +#define HWIO_IPA_STATE_DFETCHER_MASK_0_n_ATTR 0x1 +#define HWIO_IPA_STATE_DFETCHER_MASK_0_n_INI(n) \ + in_dword_masked(HWIO_IPA_STATE_DFETCHER_MASK_0_n_ADDR(n), HWIO_IPA_STATE_DFETCHER_MASK_0_n_RMSK) +#define HWIO_IPA_STATE_DFETCHER_MASK_0_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_STATE_DFETCHER_MASK_0_n_ADDR(n), mask) +#define HWIO_IPA_STATE_DFETCHER_MASK_0_n_MASK_QUEUE_DST_GRP_DMAR_OUTSTANDING_BMSK 0xffffffff +#define HWIO_IPA_STATE_DFETCHER_MASK_0_n_MASK_QUEUE_DST_GRP_DMAR_OUTSTANDING_SHFT 0x0 + +#define HWIO_IPA_STATE_DFETCHER_MASK_1_n_ADDR(n) (IPA_CFG_REG_BASE + 0x000001c0 + 0x4 * (n)) +#define HWIO_IPA_STATE_DFETCHER_MASK_1_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x000001c0 + 0x4 * (n)) +#define HWIO_IPA_STATE_DFETCHER_MASK_1_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x000001c0 + 0x4 * (n)) +#define HWIO_IPA_STATE_DFETCHER_MASK_1_n_RMSK 0xffffffff +#define HWIO_IPA_STATE_DFETCHER_MASK_1_n_MAXn 1 +#define HWIO_IPA_STATE_DFETCHER_MASK_1_n_ATTR 0x1 +#define HWIO_IPA_STATE_DFETCHER_MASK_1_n_INI(n) \ + in_dword_masked(HWIO_IPA_STATE_DFETCHER_MASK_1_n_ADDR(n), HWIO_IPA_STATE_DFETCHER_MASK_1_n_RMSK) +#define HWIO_IPA_STATE_DFETCHER_MASK_1_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_STATE_DFETCHER_MASK_1_n_ADDR(n), mask) +#define HWIO_IPA_STATE_DFETCHER_MASK_1_n_MASK_QUEUE_NO_RESOURCES_DATA_SECTORS_BMSK 0xffffffff +#define HWIO_IPA_STATE_DFETCHER_MASK_1_n_MASK_QUEUE_NO_RESOURCES_DATA_SECTORS_SHFT 0x0 + +#define HWIO_IPA_STATE_DFETCHER_MASK_2_n_ADDR(n) (IPA_CFG_REG_BASE + 0x000001e0 + 0x4 * (n)) +#define HWIO_IPA_STATE_DFETCHER_MASK_2_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x000001e0 + 0x4 * (n)) +#define HWIO_IPA_STATE_DFETCHER_MASK_2_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x000001e0 + 0x4 * (n)) +#define HWIO_IPA_STATE_DFETCHER_MASK_2_n_RMSK 0xffffffff +#define HWIO_IPA_STATE_DFETCHER_MASK_2_n_MAXn 1 +#define HWIO_IPA_STATE_DFETCHER_MASK_2_n_ATTR 0x1 +#define HWIO_IPA_STATE_DFETCHER_MASK_2_n_INI(n) \ + in_dword_masked(HWIO_IPA_STATE_DFETCHER_MASK_2_n_ADDR(n), HWIO_IPA_STATE_DFETCHER_MASK_2_n_RMSK) +#define HWIO_IPA_STATE_DFETCHER_MASK_2_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_STATE_DFETCHER_MASK_2_n_ADDR(n), mask) +#define HWIO_IPA_STATE_DFETCHER_MASK_2_n_MASK_QUEUE_NO_RESOURCES_DPS_DMAR_BMSK 0xffffffff +#define HWIO_IPA_STATE_DFETCHER_MASK_2_n_MASK_QUEUE_NO_RESOURCES_DPS_DMAR_SHFT 0x0 + +#define HWIO_IPA_STATE_DFETCHER_MASK_3_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000200 + 0x4 * (n)) +#define HWIO_IPA_STATE_DFETCHER_MASK_3_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000200 + 0x4 * (n)) +#define HWIO_IPA_STATE_DFETCHER_MASK_3_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000200 + 0x4 * (n)) +#define HWIO_IPA_STATE_DFETCHER_MASK_3_n_RMSK 0xffffffff +#define HWIO_IPA_STATE_DFETCHER_MASK_3_n_MAXn 1 +#define HWIO_IPA_STATE_DFETCHER_MASK_3_n_ATTR 0x1 +#define HWIO_IPA_STATE_DFETCHER_MASK_3_n_INI(n) \ + in_dword_masked(HWIO_IPA_STATE_DFETCHER_MASK_3_n_ADDR(n), HWIO_IPA_STATE_DFETCHER_MASK_3_n_RMSK) +#define HWIO_IPA_STATE_DFETCHER_MASK_3_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_STATE_DFETCHER_MASK_3_n_ADDR(n), mask) +#define HWIO_IPA_STATE_DFETCHER_MASK_3_n_MASK_QUEUE_NO_RESOURCES_SEG_CTX_BMSK 0xffffffff +#define HWIO_IPA_STATE_DFETCHER_MASK_3_n_MASK_QUEUE_NO_RESOURCES_SEG_CTX_SHFT 0x0 + +#define HWIO_IPA_ACTIVE_PIPES_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000220 + 0x4 * (n)) +#define HWIO_IPA_ACTIVE_PIPES_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000220 + 0x4 * (n)) +#define HWIO_IPA_ACTIVE_PIPES_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000220 + 0x4 * (n)) +#define HWIO_IPA_ACTIVE_PIPES_n_RMSK 0xffffffff +#define HWIO_IPA_ACTIVE_PIPES_n_MAXn 1 +#define HWIO_IPA_ACTIVE_PIPES_n_ATTR 0x1 +#define HWIO_IPA_ACTIVE_PIPES_n_INI(n) \ + in_dword_masked(HWIO_IPA_ACTIVE_PIPES_n_ADDR(n), HWIO_IPA_ACTIVE_PIPES_n_RMSK) +#define HWIO_IPA_ACTIVE_PIPES_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ACTIVE_PIPES_n_ADDR(n), mask) +#define HWIO_IPA_ACTIVE_PIPES_n_ENDPOINTS_BMSK 0xffffffff +#define HWIO_IPA_ACTIVE_PIPES_n_ENDPOINTS_SHFT 0x0 + +#define HWIO_IPA_YELLOW_MARKER_BELOW_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000240 + 0x4 * (n)) +#define HWIO_IPA_YELLOW_MARKER_BELOW_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000240 + 0x4 * (n)) +#define HWIO_IPA_YELLOW_MARKER_BELOW_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000240 + 0x4 * (n)) +#define HWIO_IPA_YELLOW_MARKER_BELOW_n_RMSK 0xffffffff +#define HWIO_IPA_YELLOW_MARKER_BELOW_n_MAXn 1 +#define HWIO_IPA_YELLOW_MARKER_BELOW_n_ATTR 0x1 +#define HWIO_IPA_YELLOW_MARKER_BELOW_n_INI(n) \ + in_dword_masked(HWIO_IPA_YELLOW_MARKER_BELOW_n_ADDR(n), HWIO_IPA_YELLOW_MARKER_BELOW_n_RMSK) +#define HWIO_IPA_YELLOW_MARKER_BELOW_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_YELLOW_MARKER_BELOW_n_ADDR(n), mask) +#define HWIO_IPA_YELLOW_MARKER_BELOW_n_ENDPOINTS_BMSK 0xffffffff +#define HWIO_IPA_YELLOW_MARKER_BELOW_n_ENDPOINTS_SHFT 0x0 + +#define HWIO_IPA_YELLOW_MARKER_BELOW_EN_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000260 + 0x4 * (n)) +#define HWIO_IPA_YELLOW_MARKER_BELOW_EN_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000260 + 0x4 * (n)) +#define HWIO_IPA_YELLOW_MARKER_BELOW_EN_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000260 + 0x4 * (n)) +#define HWIO_IPA_YELLOW_MARKER_BELOW_EN_n_RMSK 0xffffffff +#define HWIO_IPA_YELLOW_MARKER_BELOW_EN_n_MAXn 1 +#define HWIO_IPA_YELLOW_MARKER_BELOW_EN_n_ATTR 0x3 +#define HWIO_IPA_YELLOW_MARKER_BELOW_EN_n_INI(n) \ + in_dword_masked(HWIO_IPA_YELLOW_MARKER_BELOW_EN_n_ADDR(n), HWIO_IPA_YELLOW_MARKER_BELOW_EN_n_RMSK) +#define HWIO_IPA_YELLOW_MARKER_BELOW_EN_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_YELLOW_MARKER_BELOW_EN_n_ADDR(n), mask) +#define HWIO_IPA_YELLOW_MARKER_BELOW_EN_n_OUTI(n,val) \ + out_dword(HWIO_IPA_YELLOW_MARKER_BELOW_EN_n_ADDR(n),val) +#define HWIO_IPA_YELLOW_MARKER_BELOW_EN_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_YELLOW_MARKER_BELOW_EN_n_ADDR(n),mask,val,HWIO_IPA_YELLOW_MARKER_BELOW_EN_n_INI(n)) +#define HWIO_IPA_YELLOW_MARKER_BELOW_EN_n_ENDPOINTS_BMSK 0xffffffff +#define HWIO_IPA_YELLOW_MARKER_BELOW_EN_n_ENDPOINTS_SHFT 0x0 + +#define HWIO_IPA_YELLOW_MARKER_BELOW_CLR_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000280 + 0x4 * (n)) +#define HWIO_IPA_YELLOW_MARKER_BELOW_CLR_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000280 + 0x4 * (n)) +#define HWIO_IPA_YELLOW_MARKER_BELOW_CLR_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000280 + 0x4 * (n)) +#define HWIO_IPA_YELLOW_MARKER_BELOW_CLR_n_RMSK 0xffffffff +#define HWIO_IPA_YELLOW_MARKER_BELOW_CLR_n_MAXn 1 +#define HWIO_IPA_YELLOW_MARKER_BELOW_CLR_n_ATTR 0x2 +#define HWIO_IPA_YELLOW_MARKER_BELOW_CLR_n_OUTI(n,val) \ + out_dword(HWIO_IPA_YELLOW_MARKER_BELOW_CLR_n_ADDR(n),val) +#define HWIO_IPA_YELLOW_MARKER_BELOW_CLR_n_ENDPOINTS_BMSK 0xffffffff +#define HWIO_IPA_YELLOW_MARKER_BELOW_CLR_n_ENDPOINTS_SHFT 0x0 + +#define HWIO_IPA_RED_MARKER_BELOW_n_ADDR(n) (IPA_CFG_REG_BASE + 0x000002a0 + 0x4 * (n)) +#define HWIO_IPA_RED_MARKER_BELOW_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x000002a0 + 0x4 * (n)) +#define HWIO_IPA_RED_MARKER_BELOW_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x000002a0 + 0x4 * (n)) +#define HWIO_IPA_RED_MARKER_BELOW_n_RMSK 0xffffffff +#define HWIO_IPA_RED_MARKER_BELOW_n_MAXn 1 +#define HWIO_IPA_RED_MARKER_BELOW_n_ATTR 0x1 +#define HWIO_IPA_RED_MARKER_BELOW_n_INI(n) \ + in_dword_masked(HWIO_IPA_RED_MARKER_BELOW_n_ADDR(n), HWIO_IPA_RED_MARKER_BELOW_n_RMSK) +#define HWIO_IPA_RED_MARKER_BELOW_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_RED_MARKER_BELOW_n_ADDR(n), mask) +#define HWIO_IPA_RED_MARKER_BELOW_n_ENDPOINTS_BMSK 0xffffffff +#define HWIO_IPA_RED_MARKER_BELOW_n_ENDPOINTS_SHFT 0x0 + +#define HWIO_IPA_RED_MARKER_BELOW_EN_n_ADDR(n) (IPA_CFG_REG_BASE + 0x000002c0 + 0x4 * (n)) +#define HWIO_IPA_RED_MARKER_BELOW_EN_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x000002c0 + 0x4 * (n)) +#define HWIO_IPA_RED_MARKER_BELOW_EN_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x000002c0 + 0x4 * (n)) +#define HWIO_IPA_RED_MARKER_BELOW_EN_n_RMSK 0xffffffff +#define HWIO_IPA_RED_MARKER_BELOW_EN_n_MAXn 1 +#define HWIO_IPA_RED_MARKER_BELOW_EN_n_ATTR 0x3 +#define HWIO_IPA_RED_MARKER_BELOW_EN_n_INI(n) \ + in_dword_masked(HWIO_IPA_RED_MARKER_BELOW_EN_n_ADDR(n), HWIO_IPA_RED_MARKER_BELOW_EN_n_RMSK) +#define HWIO_IPA_RED_MARKER_BELOW_EN_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_RED_MARKER_BELOW_EN_n_ADDR(n), mask) +#define HWIO_IPA_RED_MARKER_BELOW_EN_n_OUTI(n,val) \ + out_dword(HWIO_IPA_RED_MARKER_BELOW_EN_n_ADDR(n),val) +#define HWIO_IPA_RED_MARKER_BELOW_EN_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_RED_MARKER_BELOW_EN_n_ADDR(n),mask,val,HWIO_IPA_RED_MARKER_BELOW_EN_n_INI(n)) +#define HWIO_IPA_RED_MARKER_BELOW_EN_n_ENDPOINTS_BMSK 0xffffffff +#define HWIO_IPA_RED_MARKER_BELOW_EN_n_ENDPOINTS_SHFT 0x0 + +#define HWIO_IPA_RED_MARKER_BELOW_CLR_n_ADDR(n) (IPA_CFG_REG_BASE + 0x000002e0 + 0x4 * (n)) +#define HWIO_IPA_RED_MARKER_BELOW_CLR_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x000002e0 + 0x4 * (n)) +#define HWIO_IPA_RED_MARKER_BELOW_CLR_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x000002e0 + 0x4 * (n)) +#define HWIO_IPA_RED_MARKER_BELOW_CLR_n_RMSK 0xffffffff +#define HWIO_IPA_RED_MARKER_BELOW_CLR_n_MAXn 1 +#define HWIO_IPA_RED_MARKER_BELOW_CLR_n_ATTR 0x2 +#define HWIO_IPA_RED_MARKER_BELOW_CLR_n_OUTI(n,val) \ + out_dword(HWIO_IPA_RED_MARKER_BELOW_CLR_n_ADDR(n),val) +#define HWIO_IPA_RED_MARKER_BELOW_CLR_n_ENDPOINTS_BMSK 0xffffffff +#define HWIO_IPA_RED_MARKER_BELOW_CLR_n_ENDPOINTS_SHFT 0x0 + +#define HWIO_IPA_YELLOW_MARKER_SHADOW_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000300 + 0x4 * (n)) +#define HWIO_IPA_YELLOW_MARKER_SHADOW_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000300 + 0x4 * (n)) +#define HWIO_IPA_YELLOW_MARKER_SHADOW_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000300 + 0x4 * (n)) +#define HWIO_IPA_YELLOW_MARKER_SHADOW_n_RMSK 0xffffffff +#define HWIO_IPA_YELLOW_MARKER_SHADOW_n_MAXn 1 +#define HWIO_IPA_YELLOW_MARKER_SHADOW_n_ATTR 0x1 +#define HWIO_IPA_YELLOW_MARKER_SHADOW_n_INI(n) \ + in_dword_masked(HWIO_IPA_YELLOW_MARKER_SHADOW_n_ADDR(n), HWIO_IPA_YELLOW_MARKER_SHADOW_n_RMSK) +#define HWIO_IPA_YELLOW_MARKER_SHADOW_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_YELLOW_MARKER_SHADOW_n_ADDR(n), mask) +#define HWIO_IPA_YELLOW_MARKER_SHADOW_n_ENDPOINTS_BMSK 0xffffffff +#define HWIO_IPA_YELLOW_MARKER_SHADOW_n_ENDPOINTS_SHFT 0x0 + +#define HWIO_IPA_RED_MARKER_SHADOW_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000320 + 0x4 * (n)) +#define HWIO_IPA_RED_MARKER_SHADOW_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000320 + 0x4 * (n)) +#define HWIO_IPA_RED_MARKER_SHADOW_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000320 + 0x4 * (n)) +#define HWIO_IPA_RED_MARKER_SHADOW_n_RMSK 0xffffffff +#define HWIO_IPA_RED_MARKER_SHADOW_n_MAXn 1 +#define HWIO_IPA_RED_MARKER_SHADOW_n_ATTR 0x1 +#define HWIO_IPA_RED_MARKER_SHADOW_n_INI(n) \ + in_dword_masked(HWIO_IPA_RED_MARKER_SHADOW_n_ADDR(n), HWIO_IPA_RED_MARKER_SHADOW_n_RMSK) +#define HWIO_IPA_RED_MARKER_SHADOW_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_RED_MARKER_SHADOW_n_ADDR(n), mask) +#define HWIO_IPA_RED_MARKER_SHADOW_n_ENDPOINTS_BMSK 0xffffffff +#define HWIO_IPA_RED_MARKER_SHADOW_n_ENDPOINTS_SHFT 0x0 + +#define HWIO_IPA_YELLOW_MARKER_ABOVE_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000340 + 0x4 * (n)) +#define HWIO_IPA_YELLOW_MARKER_ABOVE_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000340 + 0x4 * (n)) +#define HWIO_IPA_YELLOW_MARKER_ABOVE_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000340 + 0x4 * (n)) +#define HWIO_IPA_YELLOW_MARKER_ABOVE_n_RMSK 0xffffffff +#define HWIO_IPA_YELLOW_MARKER_ABOVE_n_MAXn 1 +#define HWIO_IPA_YELLOW_MARKER_ABOVE_n_ATTR 0x1 +#define HWIO_IPA_YELLOW_MARKER_ABOVE_n_INI(n) \ + in_dword_masked(HWIO_IPA_YELLOW_MARKER_ABOVE_n_ADDR(n), HWIO_IPA_YELLOW_MARKER_ABOVE_n_RMSK) +#define HWIO_IPA_YELLOW_MARKER_ABOVE_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_YELLOW_MARKER_ABOVE_n_ADDR(n), mask) +#define HWIO_IPA_YELLOW_MARKER_ABOVE_n_ENDPOINTS_BMSK 0xffffffff +#define HWIO_IPA_YELLOW_MARKER_ABOVE_n_ENDPOINTS_SHFT 0x0 + +#define HWIO_IPA_YELLOW_MARKER_ABOVE_EN_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000360 + 0x4 * (n)) +#define HWIO_IPA_YELLOW_MARKER_ABOVE_EN_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000360 + 0x4 * (n)) +#define HWIO_IPA_YELLOW_MARKER_ABOVE_EN_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000360 + 0x4 * (n)) +#define HWIO_IPA_YELLOW_MARKER_ABOVE_EN_n_RMSK 0xffffffff +#define HWIO_IPA_YELLOW_MARKER_ABOVE_EN_n_MAXn 1 +#define HWIO_IPA_YELLOW_MARKER_ABOVE_EN_n_ATTR 0x3 +#define HWIO_IPA_YELLOW_MARKER_ABOVE_EN_n_INI(n) \ + in_dword_masked(HWIO_IPA_YELLOW_MARKER_ABOVE_EN_n_ADDR(n), HWIO_IPA_YELLOW_MARKER_ABOVE_EN_n_RMSK) +#define HWIO_IPA_YELLOW_MARKER_ABOVE_EN_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_YELLOW_MARKER_ABOVE_EN_n_ADDR(n), mask) +#define HWIO_IPA_YELLOW_MARKER_ABOVE_EN_n_OUTI(n,val) \ + out_dword(HWIO_IPA_YELLOW_MARKER_ABOVE_EN_n_ADDR(n),val) +#define HWIO_IPA_YELLOW_MARKER_ABOVE_EN_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_YELLOW_MARKER_ABOVE_EN_n_ADDR(n),mask,val,HWIO_IPA_YELLOW_MARKER_ABOVE_EN_n_INI(n)) +#define HWIO_IPA_YELLOW_MARKER_ABOVE_EN_n_ENDPOINTS_BMSK 0xffffffff +#define HWIO_IPA_YELLOW_MARKER_ABOVE_EN_n_ENDPOINTS_SHFT 0x0 + +#define HWIO_IPA_YELLOW_MARKER_ABOVE_CLR_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000380 + 0x4 * (n)) +#define HWIO_IPA_YELLOW_MARKER_ABOVE_CLR_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000380 + 0x4 * (n)) +#define HWIO_IPA_YELLOW_MARKER_ABOVE_CLR_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000380 + 0x4 * (n)) +#define HWIO_IPA_YELLOW_MARKER_ABOVE_CLR_n_RMSK 0xffffffff +#define HWIO_IPA_YELLOW_MARKER_ABOVE_CLR_n_MAXn 1 +#define HWIO_IPA_YELLOW_MARKER_ABOVE_CLR_n_ATTR 0x2 +#define HWIO_IPA_YELLOW_MARKER_ABOVE_CLR_n_OUTI(n,val) \ + out_dword(HWIO_IPA_YELLOW_MARKER_ABOVE_CLR_n_ADDR(n),val) +#define HWIO_IPA_YELLOW_MARKER_ABOVE_CLR_n_ENDPOINTS_BMSK 0xffffffff +#define HWIO_IPA_YELLOW_MARKER_ABOVE_CLR_n_ENDPOINTS_SHFT 0x0 + +#define HWIO_IPA_RED_MARKER_ABOVE_n_ADDR(n) (IPA_CFG_REG_BASE + 0x000003a0 + 0x4 * (n)) +#define HWIO_IPA_RED_MARKER_ABOVE_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x000003a0 + 0x4 * (n)) +#define HWIO_IPA_RED_MARKER_ABOVE_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x000003a0 + 0x4 * (n)) +#define HWIO_IPA_RED_MARKER_ABOVE_n_RMSK 0xffffffff +#define HWIO_IPA_RED_MARKER_ABOVE_n_MAXn 1 +#define HWIO_IPA_RED_MARKER_ABOVE_n_ATTR 0x1 +#define HWIO_IPA_RED_MARKER_ABOVE_n_INI(n) \ + in_dword_masked(HWIO_IPA_RED_MARKER_ABOVE_n_ADDR(n), HWIO_IPA_RED_MARKER_ABOVE_n_RMSK) +#define HWIO_IPA_RED_MARKER_ABOVE_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_RED_MARKER_ABOVE_n_ADDR(n), mask) +#define HWIO_IPA_RED_MARKER_ABOVE_n_ENDPOINTS_BMSK 0xffffffff +#define HWIO_IPA_RED_MARKER_ABOVE_n_ENDPOINTS_SHFT 0x0 + +#define HWIO_IPA_RED_MARKER_ABOVE_EN_n_ADDR(n) (IPA_CFG_REG_BASE + 0x000003c0 + 0x4 * (n)) +#define HWIO_IPA_RED_MARKER_ABOVE_EN_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x000003c0 + 0x4 * (n)) +#define HWIO_IPA_RED_MARKER_ABOVE_EN_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x000003c0 + 0x4 * (n)) +#define HWIO_IPA_RED_MARKER_ABOVE_EN_n_RMSK 0xffffffff +#define HWIO_IPA_RED_MARKER_ABOVE_EN_n_MAXn 1 +#define HWIO_IPA_RED_MARKER_ABOVE_EN_n_ATTR 0x3 +#define HWIO_IPA_RED_MARKER_ABOVE_EN_n_INI(n) \ + in_dword_masked(HWIO_IPA_RED_MARKER_ABOVE_EN_n_ADDR(n), HWIO_IPA_RED_MARKER_ABOVE_EN_n_RMSK) +#define HWIO_IPA_RED_MARKER_ABOVE_EN_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_RED_MARKER_ABOVE_EN_n_ADDR(n), mask) +#define HWIO_IPA_RED_MARKER_ABOVE_EN_n_OUTI(n,val) \ + out_dword(HWIO_IPA_RED_MARKER_ABOVE_EN_n_ADDR(n),val) +#define HWIO_IPA_RED_MARKER_ABOVE_EN_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_RED_MARKER_ABOVE_EN_n_ADDR(n),mask,val,HWIO_IPA_RED_MARKER_ABOVE_EN_n_INI(n)) +#define HWIO_IPA_RED_MARKER_ABOVE_EN_n_ENDPOINTS_BMSK 0xffffffff +#define HWIO_IPA_RED_MARKER_ABOVE_EN_n_ENDPOINTS_SHFT 0x0 + +#define HWIO_IPA_RED_MARKER_ABOVE_CLR_n_ADDR(n) (IPA_CFG_REG_BASE + 0x000003e0 + 0x4 * (n)) +#define HWIO_IPA_RED_MARKER_ABOVE_CLR_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x000003e0 + 0x4 * (n)) +#define HWIO_IPA_RED_MARKER_ABOVE_CLR_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x000003e0 + 0x4 * (n)) +#define HWIO_IPA_RED_MARKER_ABOVE_CLR_n_RMSK 0xffffffff +#define HWIO_IPA_RED_MARKER_ABOVE_CLR_n_MAXn 1 +#define HWIO_IPA_RED_MARKER_ABOVE_CLR_n_ATTR 0x2 +#define HWIO_IPA_RED_MARKER_ABOVE_CLR_n_OUTI(n,val) \ + out_dword(HWIO_IPA_RED_MARKER_ABOVE_CLR_n_ADDR(n),val) +#define HWIO_IPA_RED_MARKER_ABOVE_CLR_n_ENDPOINTS_BMSK 0xffffffff +#define HWIO_IPA_RED_MARKER_ABOVE_CLR_n_ENDPOINTS_SHFT 0x0 + +#define HWIO_IPA_FILT_ROUT_CACHE_CFG_ADDR (IPA_CFG_REG_BASE + 0x00000400) +#define HWIO_IPA_FILT_ROUT_CACHE_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000400) +#define HWIO_IPA_FILT_ROUT_CACHE_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000400) +#define HWIO_IPA_FILT_ROUT_CACHE_CFG_RMSK 0xffff0111 +#define HWIO_IPA_FILT_ROUT_CACHE_CFG_ATTR 0x3 +#define HWIO_IPA_FILT_ROUT_CACHE_CFG_IN \ + in_dword_masked(HWIO_IPA_FILT_ROUT_CACHE_CFG_ADDR, HWIO_IPA_FILT_ROUT_CACHE_CFG_RMSK) +#define HWIO_IPA_FILT_ROUT_CACHE_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_FILT_ROUT_CACHE_CFG_ADDR, m) +#define HWIO_IPA_FILT_ROUT_CACHE_CFG_OUT(v) \ + out_dword(HWIO_IPA_FILT_ROUT_CACHE_CFG_ADDR,v) +#define HWIO_IPA_FILT_ROUT_CACHE_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_FILT_ROUT_CACHE_CFG_ADDR,m,v,HWIO_IPA_FILT_ROUT_CACHE_CFG_IN) +#define HWIO_IPA_FILT_ROUT_CACHE_CFG_CACHE_LRU_EVICTION_THRESHOLD_BMSK 0xffff0000 +#define HWIO_IPA_FILT_ROUT_CACHE_CFG_CACHE_LRU_EVICTION_THRESHOLD_SHFT 0x10 +#define HWIO_IPA_FILT_ROUT_CACHE_CFG_CACHE_LOW_PRIORITY_HASHABLE_HIT_DISABLE_BMSK 0x100 +#define HWIO_IPA_FILT_ROUT_CACHE_CFG_CACHE_LOW_PRIORITY_HASHABLE_HIT_DISABLE_SHFT 0x8 +#define HWIO_IPA_FILT_ROUT_CACHE_CFG_IPA_FILTER_CACHE_EN_BMSK 0x10 +#define HWIO_IPA_FILT_ROUT_CACHE_CFG_IPA_FILTER_CACHE_EN_SHFT 0x4 +#define HWIO_IPA_FILT_ROUT_CACHE_CFG_IPA_ROUTER_CACHE_EN_BMSK 0x1 +#define HWIO_IPA_FILT_ROUT_CACHE_CFG_IPA_ROUTER_CACHE_EN_SHFT 0x0 + +#define HWIO_IPA_FILT_ROUT_CACHE_REDUCE_CFG_ADDR (IPA_CFG_REG_BASE + 0x000004e0) +#define HWIO_IPA_FILT_ROUT_CACHE_REDUCE_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000004e0) +#define HWIO_IPA_FILT_ROUT_CACHE_REDUCE_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000004e0) +#define HWIO_IPA_FILT_ROUT_CACHE_REDUCE_CFG_RMSK 0xffff11 +#define HWIO_IPA_FILT_ROUT_CACHE_REDUCE_CFG_ATTR 0x3 +#define HWIO_IPA_FILT_ROUT_CACHE_REDUCE_CFG_IN \ + in_dword_masked(HWIO_IPA_FILT_ROUT_CACHE_REDUCE_CFG_ADDR, HWIO_IPA_FILT_ROUT_CACHE_REDUCE_CFG_RMSK) +#define HWIO_IPA_FILT_ROUT_CACHE_REDUCE_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_FILT_ROUT_CACHE_REDUCE_CFG_ADDR, m) +#define HWIO_IPA_FILT_ROUT_CACHE_REDUCE_CFG_OUT(v) \ + out_dword(HWIO_IPA_FILT_ROUT_CACHE_REDUCE_CFG_ADDR,v) +#define HWIO_IPA_FILT_ROUT_CACHE_REDUCE_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_FILT_ROUT_CACHE_REDUCE_CFG_ADDR,m,v,HWIO_IPA_FILT_ROUT_CACHE_REDUCE_CFG_IN) +#define HWIO_IPA_FILT_ROUT_CACHE_REDUCE_CFG_IPA_FILTER_CACHE_REDUCE_LEVEL_BMSK 0xff0000 +#define HWIO_IPA_FILT_ROUT_CACHE_REDUCE_CFG_IPA_FILTER_CACHE_REDUCE_LEVEL_SHFT 0x10 +#define HWIO_IPA_FILT_ROUT_CACHE_REDUCE_CFG_IPA_ROUTER_CACHE_REDUCE_LEVEL_BMSK 0xff00 +#define HWIO_IPA_FILT_ROUT_CACHE_REDUCE_CFG_IPA_ROUTER_CACHE_REDUCE_LEVEL_SHFT 0x8 +#define HWIO_IPA_FILT_ROUT_CACHE_REDUCE_CFG_IPA_FILTER_CACHE_REDUCE_EN_BMSK 0x10 +#define HWIO_IPA_FILT_ROUT_CACHE_REDUCE_CFG_IPA_FILTER_CACHE_REDUCE_EN_SHFT 0x4 +#define HWIO_IPA_FILT_ROUT_CACHE_REDUCE_CFG_IPA_ROUTER_CACHE_REDUCE_EN_BMSK 0x1 +#define HWIO_IPA_FILT_ROUT_CACHE_REDUCE_CFG_IPA_ROUTER_CACHE_REDUCE_EN_SHFT 0x0 + +#define HWIO_IPA_FILT_ROUT_CACHE_FLUSH_ADDR (IPA_CFG_REG_BASE + 0x00000404) +#define HWIO_IPA_FILT_ROUT_CACHE_FLUSH_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000404) +#define HWIO_IPA_FILT_ROUT_CACHE_FLUSH_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000404) +#define HWIO_IPA_FILT_ROUT_CACHE_FLUSH_RMSK 0x11 +#define HWIO_IPA_FILT_ROUT_CACHE_FLUSH_ATTR 0x2 +#define HWIO_IPA_FILT_ROUT_CACHE_FLUSH_OUT(v) \ + out_dword(HWIO_IPA_FILT_ROUT_CACHE_FLUSH_ADDR,v) +#define HWIO_IPA_FILT_ROUT_CACHE_FLUSH_IPA_FILTER_CACHE_FLUSH_BMSK 0x10 +#define HWIO_IPA_FILT_ROUT_CACHE_FLUSH_IPA_FILTER_CACHE_FLUSH_SHFT 0x4 +#define HWIO_IPA_FILT_ROUT_CACHE_FLUSH_IPA_ROUTER_CACHE_FLUSH_BMSK 0x1 +#define HWIO_IPA_FILT_ROUT_CACHE_FLUSH_IPA_ROUTER_CACHE_FLUSH_SHFT 0x0 + +#define HWIO_IPA_FILT_ROUT_CFG_ADDR (IPA_CFG_REG_BASE + 0x00000408) +#define HWIO_IPA_FILT_ROUT_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000408) +#define HWIO_IPA_FILT_ROUT_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000408) +#define HWIO_IPA_FILT_ROUT_CFG_RMSK 0x111 +#define HWIO_IPA_FILT_ROUT_CFG_ATTR 0x3 +#define HWIO_IPA_FILT_ROUT_CFG_IN \ + in_dword_masked(HWIO_IPA_FILT_ROUT_CFG_ADDR, HWIO_IPA_FILT_ROUT_CFG_RMSK) +#define HWIO_IPA_FILT_ROUT_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_FILT_ROUT_CFG_ADDR, m) +#define HWIO_IPA_FILT_ROUT_CFG_OUT(v) \ + out_dword(HWIO_IPA_FILT_ROUT_CFG_ADDR,v) +#define HWIO_IPA_FILT_ROUT_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_FILT_ROUT_CFG_ADDR,m,v,HWIO_IPA_FILT_ROUT_CFG_IN) +#define HWIO_IPA_FILT_ROUT_CFG_FILT_ROUT_DATA_CACHE_EN_BMSK 0x100 +#define HWIO_IPA_FILT_ROUT_CFG_FILT_ROUT_DATA_CACHE_EN_SHFT 0x8 +#define HWIO_IPA_FILT_ROUT_CFG_FILTER_PREFETCH_EN_BMSK 0x10 +#define HWIO_IPA_FILT_ROUT_CFG_FILTER_PREFETCH_EN_SHFT 0x4 +#define HWIO_IPA_FILT_ROUT_CFG_ROUTER_PREFETCH_EN_BMSK 0x1 +#define HWIO_IPA_FILT_ROUT_CFG_ROUTER_PREFETCH_EN_SHFT 0x0 + +#define HWIO_IPA_IPV4_NAT_EXC_SUPPRESS_ROUT_TABLE_INDX_ADDR (IPA_CFG_REG_BASE + 0x000004e4) +#define HWIO_IPA_IPV4_NAT_EXC_SUPPRESS_ROUT_TABLE_INDX_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000004e4) +#define HWIO_IPA_IPV4_NAT_EXC_SUPPRESS_ROUT_TABLE_INDX_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000004e4) +#define HWIO_IPA_IPV4_NAT_EXC_SUPPRESS_ROUT_TABLE_INDX_RMSK 0xff +#define HWIO_IPA_IPV4_NAT_EXC_SUPPRESS_ROUT_TABLE_INDX_ATTR 0x3 +#define HWIO_IPA_IPV4_NAT_EXC_SUPPRESS_ROUT_TABLE_INDX_IN \ + in_dword_masked(HWIO_IPA_IPV4_NAT_EXC_SUPPRESS_ROUT_TABLE_INDX_ADDR, HWIO_IPA_IPV4_NAT_EXC_SUPPRESS_ROUT_TABLE_INDX_RMSK) +#define HWIO_IPA_IPV4_NAT_EXC_SUPPRESS_ROUT_TABLE_INDX_INM(m) \ + in_dword_masked(HWIO_IPA_IPV4_NAT_EXC_SUPPRESS_ROUT_TABLE_INDX_ADDR, m) +#define HWIO_IPA_IPV4_NAT_EXC_SUPPRESS_ROUT_TABLE_INDX_OUT(v) \ + out_dword(HWIO_IPA_IPV4_NAT_EXC_SUPPRESS_ROUT_TABLE_INDX_ADDR,v) +#define HWIO_IPA_IPV4_NAT_EXC_SUPPRESS_ROUT_TABLE_INDX_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_IPV4_NAT_EXC_SUPPRESS_ROUT_TABLE_INDX_ADDR,m,v,HWIO_IPA_IPV4_NAT_EXC_SUPPRESS_ROUT_TABLE_INDX_IN) +#define HWIO_IPA_IPV4_NAT_EXC_SUPPRESS_ROUT_TABLE_INDX_IP_V4_NAT_EXC_SUPPRESS_ROUT_TABLE_INDX_BMSK 0xff +#define HWIO_IPA_IPV4_NAT_EXC_SUPPRESS_ROUT_TABLE_INDX_IP_V4_NAT_EXC_SUPPRESS_ROUT_TABLE_INDX_SHFT 0x0 + +#define HWIO_IPA_IPV6_CONN_TRACK_EXC_SUPPRESS_ROUT_TABLE_INDX_ADDR (IPA_CFG_REG_BASE + 0x000004e8) +#define HWIO_IPA_IPV6_CONN_TRACK_EXC_SUPPRESS_ROUT_TABLE_INDX_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000004e8) +#define HWIO_IPA_IPV6_CONN_TRACK_EXC_SUPPRESS_ROUT_TABLE_INDX_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000004e8) +#define HWIO_IPA_IPV6_CONN_TRACK_EXC_SUPPRESS_ROUT_TABLE_INDX_RMSK 0xff +#define HWIO_IPA_IPV6_CONN_TRACK_EXC_SUPPRESS_ROUT_TABLE_INDX_ATTR 0x3 +#define HWIO_IPA_IPV6_CONN_TRACK_EXC_SUPPRESS_ROUT_TABLE_INDX_IN \ + in_dword_masked(HWIO_IPA_IPV6_CONN_TRACK_EXC_SUPPRESS_ROUT_TABLE_INDX_ADDR, HWIO_IPA_IPV6_CONN_TRACK_EXC_SUPPRESS_ROUT_TABLE_INDX_RMSK) +#define HWIO_IPA_IPV6_CONN_TRACK_EXC_SUPPRESS_ROUT_TABLE_INDX_INM(m) \ + in_dword_masked(HWIO_IPA_IPV6_CONN_TRACK_EXC_SUPPRESS_ROUT_TABLE_INDX_ADDR, m) +#define HWIO_IPA_IPV6_CONN_TRACK_EXC_SUPPRESS_ROUT_TABLE_INDX_OUT(v) \ + out_dword(HWIO_IPA_IPV6_CONN_TRACK_EXC_SUPPRESS_ROUT_TABLE_INDX_ADDR,v) +#define HWIO_IPA_IPV6_CONN_TRACK_EXC_SUPPRESS_ROUT_TABLE_INDX_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_IPV6_CONN_TRACK_EXC_SUPPRESS_ROUT_TABLE_INDX_ADDR,m,v,HWIO_IPA_IPV6_CONN_TRACK_EXC_SUPPRESS_ROUT_TABLE_INDX_IN) +#define HWIO_IPA_IPV6_CONN_TRACK_EXC_SUPPRESS_ROUT_TABLE_INDX_IP_V6_CONN_TRACK_EXC_SUPPRESS_ROUT_TABLE_INDX_BMSK 0xff +#define HWIO_IPA_IPV6_CONN_TRACK_EXC_SUPPRESS_ROUT_TABLE_INDX_IP_V6_CONN_TRACK_EXC_SUPPRESS_ROUT_TABLE_INDX_SHFT 0x0 + +#define HWIO_IPA_IPV4_FILTER_INIT_VALUES_ADDR (IPA_CFG_REG_BASE + 0x0000040c) +#define HWIO_IPA_IPV4_FILTER_INIT_VALUES_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000040c) +#define HWIO_IPA_IPV4_FILTER_INIT_VALUES_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000040c) +#define HWIO_IPA_IPV4_FILTER_INIT_VALUES_RMSK 0xffffffff +#define HWIO_IPA_IPV4_FILTER_INIT_VALUES_ATTR 0x1 +#define HWIO_IPA_IPV4_FILTER_INIT_VALUES_IN \ + in_dword_masked(HWIO_IPA_IPV4_FILTER_INIT_VALUES_ADDR, HWIO_IPA_IPV4_FILTER_INIT_VALUES_RMSK) +#define HWIO_IPA_IPV4_FILTER_INIT_VALUES_INM(m) \ + in_dword_masked(HWIO_IPA_IPV4_FILTER_INIT_VALUES_ADDR, m) +#define HWIO_IPA_IPV4_FILTER_INIT_VALUES_IP_V4_FILTER_INIT_NON_HASHED_ADDR_BMSK 0xffff0000 +#define HWIO_IPA_IPV4_FILTER_INIT_VALUES_IP_V4_FILTER_INIT_NON_HASHED_ADDR_SHFT 0x10 +#define HWIO_IPA_IPV4_FILTER_INIT_VALUES_IP_V4_FILTER_INIT_HASHED_ADDR_BMSK 0xffff +#define HWIO_IPA_IPV4_FILTER_INIT_VALUES_IP_V4_FILTER_INIT_HASHED_ADDR_SHFT 0x0 + +#define HWIO_IPA_IPV6_FILTER_INIT_VALUES_ADDR (IPA_CFG_REG_BASE + 0x00000410) +#define HWIO_IPA_IPV6_FILTER_INIT_VALUES_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000410) +#define HWIO_IPA_IPV6_FILTER_INIT_VALUES_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000410) +#define HWIO_IPA_IPV6_FILTER_INIT_VALUES_RMSK 0xffffffff +#define HWIO_IPA_IPV6_FILTER_INIT_VALUES_ATTR 0x1 +#define HWIO_IPA_IPV6_FILTER_INIT_VALUES_IN \ + in_dword_masked(HWIO_IPA_IPV6_FILTER_INIT_VALUES_ADDR, HWIO_IPA_IPV6_FILTER_INIT_VALUES_RMSK) +#define HWIO_IPA_IPV6_FILTER_INIT_VALUES_INM(m) \ + in_dword_masked(HWIO_IPA_IPV6_FILTER_INIT_VALUES_ADDR, m) +#define HWIO_IPA_IPV6_FILTER_INIT_VALUES_IP_V6_FILTER_INIT_NON_HASHED_ADDR_BMSK 0xffff0000 +#define HWIO_IPA_IPV6_FILTER_INIT_VALUES_IP_V6_FILTER_INIT_NON_HASHED_ADDR_SHFT 0x10 +#define HWIO_IPA_IPV6_FILTER_INIT_VALUES_IP_V6_FILTER_INIT_HASHED_ADDR_BMSK 0xffff +#define HWIO_IPA_IPV6_FILTER_INIT_VALUES_IP_V6_FILTER_INIT_HASHED_ADDR_SHFT 0x0 + +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_0_ADDR (IPA_CFG_REG_BASE + 0x00000414) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_0_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000414) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_0_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000414) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_0_RMSK 0xffffffff +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_0_ATTR 0x1 +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_0_IN \ + in_dword_masked(HWIO_IPA_IPV4_NAT_INIT_VALUES_0_ADDR, HWIO_IPA_IPV4_NAT_INIT_VALUES_0_RMSK) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_0_INM(m) \ + in_dword_masked(HWIO_IPA_IPV4_NAT_INIT_VALUES_0_ADDR, m) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_0_IP_V4_NAT_INIT_RULES_ADDR_BMSK 0xffffffff +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_0_IP_V4_NAT_INIT_RULES_ADDR_SHFT 0x0 + +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_0_MSB_ADDR (IPA_CFG_REG_BASE + 0x00000418) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_0_MSB_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000418) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_0_MSB_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000418) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_0_MSB_RMSK 0xffffffff +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_0_MSB_ATTR 0x1 +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_0_MSB_IN \ + in_dword_masked(HWIO_IPA_IPV4_NAT_INIT_VALUES_0_MSB_ADDR, HWIO_IPA_IPV4_NAT_INIT_VALUES_0_MSB_RMSK) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_0_MSB_INM(m) \ + in_dword_masked(HWIO_IPA_IPV4_NAT_INIT_VALUES_0_MSB_ADDR, m) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_0_MSB_IP_V4_NAT_INIT_RULES_ADDR_BMSK 0xffffffff +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_0_MSB_IP_V4_NAT_INIT_RULES_ADDR_SHFT 0x0 + +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_1_ADDR (IPA_CFG_REG_BASE + 0x0000041c) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_1_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000041c) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_1_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000041c) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_1_RMSK 0xffffffff +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_1_ATTR 0x1 +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_1_IN \ + in_dword_masked(HWIO_IPA_IPV4_NAT_INIT_VALUES_1_ADDR, HWIO_IPA_IPV4_NAT_INIT_VALUES_1_RMSK) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_1_INM(m) \ + in_dword_masked(HWIO_IPA_IPV4_NAT_INIT_VALUES_1_ADDR, m) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_1_IP_V4_NAT_INIT_EXP_RULES_ADDR_BMSK 0xffffffff +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_1_IP_V4_NAT_INIT_EXP_RULES_ADDR_SHFT 0x0 + +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_1_MSB_ADDR (IPA_CFG_REG_BASE + 0x00000420) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_1_MSB_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000420) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_1_MSB_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000420) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_1_MSB_RMSK 0xffffffff +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_1_MSB_ATTR 0x1 +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_1_MSB_IN \ + in_dword_masked(HWIO_IPA_IPV4_NAT_INIT_VALUES_1_MSB_ADDR, HWIO_IPA_IPV4_NAT_INIT_VALUES_1_MSB_RMSK) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_1_MSB_INM(m) \ + in_dword_masked(HWIO_IPA_IPV4_NAT_INIT_VALUES_1_MSB_ADDR, m) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_1_MSB_IP_V4_NAT_INIT_EXP_RULES_ADDR_BMSK 0xffffffff +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_1_MSB_IP_V4_NAT_INIT_EXP_RULES_ADDR_SHFT 0x0 + +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_2_ADDR (IPA_CFG_REG_BASE + 0x00000424) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_2_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000424) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_2_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000424) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_2_RMSK 0xffffffff +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_2_ATTR 0x1 +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_2_IN \ + in_dword_masked(HWIO_IPA_IPV4_NAT_INIT_VALUES_2_ADDR, HWIO_IPA_IPV4_NAT_INIT_VALUES_2_RMSK) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_2_INM(m) \ + in_dword_masked(HWIO_IPA_IPV4_NAT_INIT_VALUES_2_ADDR, m) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_2_IP_V4_NAT_INIT_INDEX_TABLE_ADDR_BMSK 0xffffffff +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_2_IP_V4_NAT_INIT_INDEX_TABLE_ADDR_SHFT 0x0 + +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_2_MSB_ADDR (IPA_CFG_REG_BASE + 0x00000428) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_2_MSB_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000428) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_2_MSB_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000428) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_2_MSB_RMSK 0xffffffff +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_2_MSB_ATTR 0x1 +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_2_MSB_IN \ + in_dword_masked(HWIO_IPA_IPV4_NAT_INIT_VALUES_2_MSB_ADDR, HWIO_IPA_IPV4_NAT_INIT_VALUES_2_MSB_RMSK) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_2_MSB_INM(m) \ + in_dword_masked(HWIO_IPA_IPV4_NAT_INIT_VALUES_2_MSB_ADDR, m) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_2_MSB_IP_V4_NAT_INIT_INDEX_TABLE_ADDR_BMSK 0xffffffff +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_2_MSB_IP_V4_NAT_INIT_INDEX_TABLE_ADDR_SHFT 0x0 + +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_3_ADDR (IPA_CFG_REG_BASE + 0x0000042c) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_3_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000042c) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_3_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000042c) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_3_RMSK 0xffffffff +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_3_ATTR 0x1 +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_3_IN \ + in_dword_masked(HWIO_IPA_IPV4_NAT_INIT_VALUES_3_ADDR, HWIO_IPA_IPV4_NAT_INIT_VALUES_3_RMSK) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_3_INM(m) \ + in_dword_masked(HWIO_IPA_IPV4_NAT_INIT_VALUES_3_ADDR, m) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_3_IP_V4_NAT_INIT_INDEX_TABLE_EXP_ADDR_BMSK 0xffffffff +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_3_IP_V4_NAT_INIT_INDEX_TABLE_EXP_ADDR_SHFT 0x0 + +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_3_MSB_ADDR (IPA_CFG_REG_BASE + 0x00000430) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_3_MSB_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000430) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_3_MSB_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000430) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_3_MSB_RMSK 0xffffffff +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_3_MSB_ATTR 0x1 +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_3_MSB_IN \ + in_dword_masked(HWIO_IPA_IPV4_NAT_INIT_VALUES_3_MSB_ADDR, HWIO_IPA_IPV4_NAT_INIT_VALUES_3_MSB_RMSK) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_3_MSB_INM(m) \ + in_dword_masked(HWIO_IPA_IPV4_NAT_INIT_VALUES_3_MSB_ADDR, m) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_3_MSB_IP_V4_NAT_INIT_INDEX_TABLE_EXP_ADDR_BMSK 0xffffffff +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_3_MSB_IP_V4_NAT_INIT_INDEX_TABLE_EXP_ADDR_SHFT 0x0 + +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_4_ADDR (IPA_CFG_REG_BASE + 0x00000434) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_4_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000434) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_4_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000434) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_4_RMSK 0x3ffffff7 +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_4_ATTR 0x1 +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_4_IN \ + in_dword_masked(HWIO_IPA_IPV4_NAT_INIT_VALUES_4_ADDR, HWIO_IPA_IPV4_NAT_INIT_VALUES_4_RMSK) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_4_INM(m) \ + in_dword_masked(HWIO_IPA_IPV4_NAT_INIT_VALUES_4_ADDR, m) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_4_IP_V4_NAT_INIT_SIZE_EXP_TABLES_BMSK 0x3ff00000 +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_4_IP_V4_NAT_INIT_SIZE_EXP_TABLES_SHFT 0x14 +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_4_IP_V4_NAT_INIT_SIZE_BASE_TABLES_BMSK 0xfff00 +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_4_IP_V4_NAT_INIT_SIZE_BASE_TABLES_SHFT 0x8 +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_4_IP_V4_NAT_INIT_INDEX_TABLE_EXP_ADDR_TYPE_BMSK 0x80 +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_4_IP_V4_NAT_INIT_INDEX_TABLE_EXP_ADDR_TYPE_SHFT 0x7 +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_4_IP_V4_NAT_INIT_INDEX_TABLE_ADDR_TYPE_BMSK 0x40 +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_4_IP_V4_NAT_INIT_INDEX_TABLE_ADDR_TYPE_SHFT 0x6 +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_4_IP_V4_NAT_INIT_EXP_RULES_ADDR_TYPE_BMSK 0x20 +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_4_IP_V4_NAT_INIT_EXP_RULES_ADDR_TYPE_SHFT 0x5 +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_4_IP_V4_NAT_INIT_RULES_ADDR_TYPE_BMSK 0x10 +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_4_IP_V4_NAT_INIT_RULES_ADDR_TYPE_SHFT 0x4 +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_4_IP_V4_NAT_INIT_TABLE_INDEX_BMSK 0x7 +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_4_IP_V4_NAT_INIT_TABLE_INDEX_SHFT 0x0 + +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_5_ADDR (IPA_CFG_REG_BASE + 0x00000438) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_5_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000438) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_5_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000438) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_5_RMSK 0xfffff +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_5_ATTR 0x1 +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_5_IN \ + in_dword_masked(HWIO_IPA_IPV4_NAT_INIT_VALUES_5_ADDR, HWIO_IPA_IPV4_NAT_INIT_VALUES_5_RMSK) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_5_INM(m) \ + in_dword_masked(HWIO_IPA_IPV4_NAT_INIT_VALUES_5_ADDR, m) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_5_IP_V4_NAT_INIT_PDN_CONFIG_TABLE_ADDR_BMSK 0xfffff +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_5_IP_V4_NAT_INIT_PDN_CONFIG_TABLE_ADDR_SHFT 0x0 + +#define HWIO_IPA_IPV4_ROUTE_INIT_VALUES_ADDR (IPA_CFG_REG_BASE + 0x0000043c) +#define HWIO_IPA_IPV4_ROUTE_INIT_VALUES_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000043c) +#define HWIO_IPA_IPV4_ROUTE_INIT_VALUES_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000043c) +#define HWIO_IPA_IPV4_ROUTE_INIT_VALUES_RMSK 0xffffffff +#define HWIO_IPA_IPV4_ROUTE_INIT_VALUES_ATTR 0x1 +#define HWIO_IPA_IPV4_ROUTE_INIT_VALUES_IN \ + in_dword_masked(HWIO_IPA_IPV4_ROUTE_INIT_VALUES_ADDR, HWIO_IPA_IPV4_ROUTE_INIT_VALUES_RMSK) +#define HWIO_IPA_IPV4_ROUTE_INIT_VALUES_INM(m) \ + in_dword_masked(HWIO_IPA_IPV4_ROUTE_INIT_VALUES_ADDR, m) +#define HWIO_IPA_IPV4_ROUTE_INIT_VALUES_IP_V4_ROUTE_INIT_NON_HASHED_ADDR_BMSK 0xffff0000 +#define HWIO_IPA_IPV4_ROUTE_INIT_VALUES_IP_V4_ROUTE_INIT_NON_HASHED_ADDR_SHFT 0x10 +#define HWIO_IPA_IPV4_ROUTE_INIT_VALUES_IP_V4_ROUTE_INIT_HASHED_ADDR_BMSK 0xffff +#define HWIO_IPA_IPV4_ROUTE_INIT_VALUES_IP_V4_ROUTE_INIT_HASHED_ADDR_SHFT 0x0 + +#define HWIO_IPA_IPV6_ROUTE_INIT_VALUES_ADDR (IPA_CFG_REG_BASE + 0x00000440) +#define HWIO_IPA_IPV6_ROUTE_INIT_VALUES_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000440) +#define HWIO_IPA_IPV6_ROUTE_INIT_VALUES_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000440) +#define HWIO_IPA_IPV6_ROUTE_INIT_VALUES_RMSK 0xffffffff +#define HWIO_IPA_IPV6_ROUTE_INIT_VALUES_ATTR 0x1 +#define HWIO_IPA_IPV6_ROUTE_INIT_VALUES_IN \ + in_dword_masked(HWIO_IPA_IPV6_ROUTE_INIT_VALUES_ADDR, HWIO_IPA_IPV6_ROUTE_INIT_VALUES_RMSK) +#define HWIO_IPA_IPV6_ROUTE_INIT_VALUES_INM(m) \ + in_dword_masked(HWIO_IPA_IPV6_ROUTE_INIT_VALUES_ADDR, m) +#define HWIO_IPA_IPV6_ROUTE_INIT_VALUES_IP_V6_ROUTE_INIT_NON_HASHED_ADDR_BMSK 0xffff0000 +#define HWIO_IPA_IPV6_ROUTE_INIT_VALUES_IP_V6_ROUTE_INIT_NON_HASHED_ADDR_SHFT 0x10 +#define HWIO_IPA_IPV6_ROUTE_INIT_VALUES_IP_V6_ROUTE_INIT_HASHED_ADDR_BMSK 0xffff +#define HWIO_IPA_IPV6_ROUTE_INIT_VALUES_IP_V6_ROUTE_INIT_HASHED_ADDR_SHFT 0x0 + +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_ADDR (IPA_CFG_REG_BASE + 0x00000444) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000444) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000444) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_RMSK 0xffffffff +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_ATTR 0x1 +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_IN \ + in_dword_masked(HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_ADDR, HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_RMSK) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_INM(m) \ + in_dword_masked(HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_ADDR, m) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_IP_V6_CONN_TRACK_INIT_TABLE_ADDR_BMSK 0xffffffff +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_IP_V6_CONN_TRACK_INIT_TABLE_ADDR_SHFT 0x0 + +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_MSB_ADDR (IPA_CFG_REG_BASE + 0x00000448) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_MSB_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000448) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_MSB_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000448) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_MSB_RMSK 0xffffffff +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_MSB_ATTR 0x1 +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_MSB_IN \ + in_dword_masked(HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_MSB_ADDR, HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_MSB_RMSK) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_MSB_INM(m) \ + in_dword_masked(HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_MSB_ADDR, m) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_MSB_IP_V6_CONN_TRACK_INIT_TABLE_ADDR_BMSK 0xffffffff +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_MSB_IP_V6_CONN_TRACK_INIT_TABLE_ADDR_SHFT 0x0 + +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_ADDR (IPA_CFG_REG_BASE + 0x0000044c) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000044c) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000044c) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_RMSK 0xffffffff +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_ATTR 0x1 +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_IN \ + in_dword_masked(HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_ADDR, HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_RMSK) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_INM(m) \ + in_dword_masked(HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_ADDR, m) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_IP_V6_CONN_TRACK_INIT_EXP_TABLE_ADDR_BMSK 0xffffffff +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_IP_V6_CONN_TRACK_INIT_EXP_TABLE_ADDR_SHFT 0x0 + +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_MSB_ADDR (IPA_CFG_REG_BASE + 0x00000450) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_MSB_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000450) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_MSB_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000450) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_MSB_RMSK 0xffffffff +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_MSB_ATTR 0x1 +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_MSB_IN \ + in_dword_masked(HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_MSB_ADDR, HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_MSB_RMSK) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_MSB_INM(m) \ + in_dword_masked(HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_MSB_ADDR, m) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_MSB_IP_V6_CONN_TRACK_INIT_EXP_TABLE_ADDR_BMSK 0xffffffff +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_MSB_IP_V6_CONN_TRACK_INIT_EXP_TABLE_ADDR_SHFT 0x0 + +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_2_ADDR (IPA_CFG_REG_BASE + 0x00000454) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_2_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000454) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_2_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000454) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_2_RMSK 0x3fffff37 +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_2_ATTR 0x1 +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_2_IN \ + in_dword_masked(HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_2_ADDR, HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_2_RMSK) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_2_INM(m) \ + in_dword_masked(HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_2_ADDR, m) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_2_IP_V6_CONN_TRACK_INIT_SIZE_EXP_TABLES_BMSK 0x3ff00000 +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_2_IP_V6_CONN_TRACK_INIT_SIZE_EXP_TABLES_SHFT 0x14 +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_2_IP_V6_CONN_TRACK_INIT_SIZE_BASE_TABLES_BMSK 0xfff00 +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_2_IP_V6_CONN_TRACK_INIT_SIZE_BASE_TABLES_SHFT 0x8 +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_2_IP_V6_CONN_TRACK_INIT_EXP_TABLE_ADDR_TYPE_BMSK 0x20 +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_2_IP_V6_CONN_TRACK_INIT_EXP_TABLE_ADDR_TYPE_SHFT 0x5 +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_2_IP_V6_CONN_TRACK_INIT_TABLE_ADDR_TYPE_BMSK 0x10 +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_2_IP_V6_CONN_TRACK_INIT_TABLE_ADDR_TYPE_SHFT 0x4 +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_2_IP_V6_CONN_TRACK_INIT_TABLE_INDEX_BMSK 0x7 +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_2_IP_V6_CONN_TRACK_INIT_TABLE_INDEX_SHFT 0x0 + +#define HWIO_IPA_HDR_INIT_LOCAL_VALUES_ADDR (IPA_CFG_REG_BASE + 0x00000458) +#define HWIO_IPA_HDR_INIT_LOCAL_VALUES_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000458) +#define HWIO_IPA_HDR_INIT_LOCAL_VALUES_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000458) +#define HWIO_IPA_HDR_INIT_LOCAL_VALUES_RMSK 0xffff000 +#define HWIO_IPA_HDR_INIT_LOCAL_VALUES_ATTR 0x1 +#define HWIO_IPA_HDR_INIT_LOCAL_VALUES_IN \ + in_dword_masked(HWIO_IPA_HDR_INIT_LOCAL_VALUES_ADDR, HWIO_IPA_HDR_INIT_LOCAL_VALUES_RMSK) +#define HWIO_IPA_HDR_INIT_LOCAL_VALUES_INM(m) \ + in_dword_masked(HWIO_IPA_HDR_INIT_LOCAL_VALUES_ADDR, m) +#define HWIO_IPA_HDR_INIT_LOCAL_VALUES_HDR_INIT_LOCAL_HDR_ADDR_BMSK 0xffff000 +#define HWIO_IPA_HDR_INIT_LOCAL_VALUES_HDR_INIT_LOCAL_HDR_ADDR_SHFT 0xc + +#define HWIO_IPA_HDR_INIT_SYSTEM_VALUES_ADDR (IPA_CFG_REG_BASE + 0x0000045c) +#define HWIO_IPA_HDR_INIT_SYSTEM_VALUES_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000045c) +#define HWIO_IPA_HDR_INIT_SYSTEM_VALUES_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000045c) +#define HWIO_IPA_HDR_INIT_SYSTEM_VALUES_RMSK 0xffffffff +#define HWIO_IPA_HDR_INIT_SYSTEM_VALUES_ATTR 0x1 +#define HWIO_IPA_HDR_INIT_SYSTEM_VALUES_IN \ + in_dword_masked(HWIO_IPA_HDR_INIT_SYSTEM_VALUES_ADDR, HWIO_IPA_HDR_INIT_SYSTEM_VALUES_RMSK) +#define HWIO_IPA_HDR_INIT_SYSTEM_VALUES_INM(m) \ + in_dword_masked(HWIO_IPA_HDR_INIT_SYSTEM_VALUES_ADDR, m) +#define HWIO_IPA_HDR_INIT_SYSTEM_VALUES_HDR_INIT_SYSTEM_HDR_TABLE_ADDR_BMSK 0xffffffff +#define HWIO_IPA_HDR_INIT_SYSTEM_VALUES_HDR_INIT_SYSTEM_HDR_TABLE_ADDR_SHFT 0x0 + +#define HWIO_IPA_HDR_INIT_SYSTEM_VALUES_MSB_ADDR (IPA_CFG_REG_BASE + 0x00000460) +#define HWIO_IPA_HDR_INIT_SYSTEM_VALUES_MSB_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000460) +#define HWIO_IPA_HDR_INIT_SYSTEM_VALUES_MSB_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000460) +#define HWIO_IPA_HDR_INIT_SYSTEM_VALUES_MSB_RMSK 0xffffffff +#define HWIO_IPA_HDR_INIT_SYSTEM_VALUES_MSB_ATTR 0x1 +#define HWIO_IPA_HDR_INIT_SYSTEM_VALUES_MSB_IN \ + in_dword_masked(HWIO_IPA_HDR_INIT_SYSTEM_VALUES_MSB_ADDR, HWIO_IPA_HDR_INIT_SYSTEM_VALUES_MSB_RMSK) +#define HWIO_IPA_HDR_INIT_SYSTEM_VALUES_MSB_INM(m) \ + in_dword_masked(HWIO_IPA_HDR_INIT_SYSTEM_VALUES_MSB_ADDR, m) +#define HWIO_IPA_HDR_INIT_SYSTEM_VALUES_MSB_HDR_INIT_SYSTEM_HDR_TABLE_ADDR_BMSK 0xffffffff +#define HWIO_IPA_HDR_INIT_SYSTEM_VALUES_MSB_HDR_INIT_SYSTEM_HDR_TABLE_ADDR_SHFT 0x0 + +#define HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_ADDR (IPA_CFG_REG_BASE + 0x00000464) +#define HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000464) +#define HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000464) +#define HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_RMSK 0xffffffff +#define HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_ATTR 0x1 +#define HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_IN \ + in_dword_masked(HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_ADDR, HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_RMSK) +#define HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_INM(m) \ + in_dword_masked(HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_ADDR, m) +#define HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_IMM_CMD_HDRI_PIPE_BMSK 0xff000000 +#define HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_IMM_CMD_HDRI_PIPE_SHFT 0x18 +#define HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_IMM_CMD_CONN_TRACK_PIPE_BMSK 0xff0000 +#define HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_IMM_CMD_CONN_TRACK_PIPE_SHFT 0x10 +#define HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_IMM_CMD_NAT_PIPE_BMSK 0xff00 +#define HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_IMM_CMD_NAT_PIPE_SHFT 0x8 +#define HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_IMM_CMD_FILTER_ROUTER_PIPE_BMSK 0xff +#define HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_IMM_CMD_FILTER_ROUTER_PIPE_SHFT 0x0 + +#define HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_1_ADDR (IPA_CFG_REG_BASE + 0x00000468) +#define HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_1_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000468) +#define HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_1_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000468) +#define HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_1_RMSK 0xff +#define HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_1_ATTR 0x1 +#define HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_1_IN \ + in_dword_masked(HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_1_ADDR, HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_1_RMSK) +#define HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_1_INM(m) \ + in_dword_masked(HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_1_ADDR, m) +#define HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_1_IMM_CMD_GEN_PIPE_BMSK 0xff +#define HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_1_IMM_CMD_GEN_PIPE_SHFT 0x0 + +#define HWIO_IPA_FRAG_VALUES_ADDR (IPA_CFG_REG_BASE + 0x0000046c) +#define HWIO_IPA_FRAG_VALUES_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000046c) +#define HWIO_IPA_FRAG_VALUES_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000046c) +#define HWIO_IPA_FRAG_VALUES_RMSK 0xf00ffff +#define HWIO_IPA_FRAG_VALUES_ATTR 0x3 +#define HWIO_IPA_FRAG_VALUES_IN \ + in_dword_masked(HWIO_IPA_FRAG_VALUES_ADDR, HWIO_IPA_FRAG_VALUES_RMSK) +#define HWIO_IPA_FRAG_VALUES_INM(m) \ + in_dword_masked(HWIO_IPA_FRAG_VALUES_ADDR, m) +#define HWIO_IPA_FRAG_VALUES_OUT(v) \ + out_dword(HWIO_IPA_FRAG_VALUES_ADDR,v) +#define HWIO_IPA_FRAG_VALUES_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_FRAG_VALUES_ADDR,m,v,HWIO_IPA_FRAG_VALUES_IN) +#define HWIO_IPA_FRAG_VALUES_IPA_FRAG_FAIRNESS_CNT_BMSK 0xf000000 +#define HWIO_IPA_FRAG_VALUES_IPA_FRAG_FAIRNESS_CNT_SHFT 0x18 +#define HWIO_IPA_FRAG_VALUES_IPA_FRAG_RAM_LAST_ADDR_BMSK 0xffff +#define HWIO_IPA_FRAG_VALUES_IPA_FRAG_RAM_LAST_ADDR_SHFT 0x0 + +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_ADDR (IPA_CFG_REG_BASE + 0x00000470) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000470) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000470) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_RMSK 0xffffffff +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_ATTR 0x3 +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_IN \ + in_dword_masked(HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_ADDR, HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_RMSK) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_INM(m) \ + in_dword_masked(HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_ADDR, m) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_OUT(v) \ + out_dword(HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_ADDR,v) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_ADDR,m,v,HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_IN) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_ADDR_BMSK 0xfffffff8 +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_ADDR_SHFT 0x3 +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_ZERO_BMSK 0x7 +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_ZERO_SHFT 0x0 + +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_ADDR (IPA_CFG_REG_BASE + 0x00000474) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000474) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000474) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_RMSK 0xffffffff +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_ATTR 0x3 +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_IN \ + in_dword_masked(HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_ADDR, HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_RMSK) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_ADDR, m) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_OUT(v) \ + out_dword(HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_ADDR,v) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_ADDR,m,v,HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_IN) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_ADDR_BMSK 0xffffffff +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_ADDR_SHFT 0x0 + +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_ADDR (IPA_CFG_REG_BASE + 0x00000478) +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000478) +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000478) +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_RMSK 0x3ffff +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_ATTR 0x3 +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_IN \ + in_dword_masked(HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_ADDR, HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_RMSK) +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_INM(m) \ + in_dword_masked(HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_ADDR, m) +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_OUT(v) \ + out_dword(HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_ADDR,v) +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_ADDR,m,v,HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_IN) +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_ADDR_BMSK 0x3fff8 +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_ADDR_SHFT 0x3 +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_ZERO_BMSK 0x7 +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_ZERO_SHFT 0x0 + +#define HWIO_IPA_SCND_FRAG_VALUES_ADDR (IPA_CFG_REG_BASE + 0x00000480) +#define HWIO_IPA_SCND_FRAG_VALUES_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000480) +#define HWIO_IPA_SCND_FRAG_VALUES_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000480) +#define HWIO_IPA_SCND_FRAG_VALUES_RMSK 0xf00ffff +#define HWIO_IPA_SCND_FRAG_VALUES_ATTR 0x3 +#define HWIO_IPA_SCND_FRAG_VALUES_IN \ + in_dword_masked(HWIO_IPA_SCND_FRAG_VALUES_ADDR, HWIO_IPA_SCND_FRAG_VALUES_RMSK) +#define HWIO_IPA_SCND_FRAG_VALUES_INM(m) \ + in_dword_masked(HWIO_IPA_SCND_FRAG_VALUES_ADDR, m) +#define HWIO_IPA_SCND_FRAG_VALUES_OUT(v) \ + out_dword(HWIO_IPA_SCND_FRAG_VALUES_ADDR,v) +#define HWIO_IPA_SCND_FRAG_VALUES_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_SCND_FRAG_VALUES_ADDR,m,v,HWIO_IPA_SCND_FRAG_VALUES_IN) +#define HWIO_IPA_SCND_FRAG_VALUES_IPA_SCND_FRAG_FAIRNESS_CNT_BMSK 0xf000000 +#define HWIO_IPA_SCND_FRAG_VALUES_IPA_SCND_FRAG_FAIRNESS_CNT_SHFT 0x18 +#define HWIO_IPA_SCND_FRAG_VALUES_IPA_SCND_FRAG_RAM_LAST_ADDR_BMSK 0xffff +#define HWIO_IPA_SCND_FRAG_VALUES_IPA_SCND_FRAG_RAM_LAST_ADDR_SHFT 0x0 + +#define HWIO_IPA_AOS_CFG_ADDR (IPA_CFG_REG_BASE + 0x00000484) +#define HWIO_IPA_AOS_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000484) +#define HWIO_IPA_AOS_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000484) +#define HWIO_IPA_AOS_CFG_RMSK 0x1 +#define HWIO_IPA_AOS_CFG_ATTR 0x3 +#define HWIO_IPA_AOS_CFG_IN \ + in_dword_masked(HWIO_IPA_AOS_CFG_ADDR, HWIO_IPA_AOS_CFG_RMSK) +#define HWIO_IPA_AOS_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_AOS_CFG_ADDR, m) +#define HWIO_IPA_AOS_CFG_OUT(v) \ + out_dword(HWIO_IPA_AOS_CFG_ADDR,v) +#define HWIO_IPA_AOS_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_AOS_CFG_ADDR,m,v,HWIO_IPA_AOS_CFG_IN) +#define HWIO_IPA_AOS_CFG_IPA_AOS_TX_RX_PRIORITY_BMSK 0x1 +#define HWIO_IPA_AOS_CFG_IPA_AOS_TX_RX_PRIORITY_SHFT 0x0 + +#define HWIO_IPA_TX_CFG_ADDR (IPA_CFG_REG_BASE + 0x00000488) +#define HWIO_IPA_TX_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000488) +#define HWIO_IPA_TX_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000488) +#define HWIO_IPA_TX_CFG_RMSK 0x17fffc +#define HWIO_IPA_TX_CFG_ATTR 0x3 +#define HWIO_IPA_TX_CFG_IN \ + in_dword_masked(HWIO_IPA_TX_CFG_ADDR, HWIO_IPA_TX_CFG_RMSK) +#define HWIO_IPA_TX_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_TX_CFG_ADDR, m) +#define HWIO_IPA_TX_CFG_OUT(v) \ + out_dword(HWIO_IPA_TX_CFG_ADDR,v) +#define HWIO_IPA_TX_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_TX_CFG_ADDR,m,v,HWIO_IPA_TX_CFG_IN) +#define HWIO_IPA_TX_CFG_HOLB_STICKY_DROP_EN_BMSK 0x100000 +#define HWIO_IPA_TX_CFG_HOLB_STICKY_DROP_EN_SHFT 0x14 +#define HWIO_IPA_TX_CFG_SSPND_PA_NO_START_STATE_BMSK 0x40000 +#define HWIO_IPA_TX_CFG_SSPND_PA_NO_START_STATE_SHFT 0x12 +#define HWIO_IPA_TX_CFG_DUAL_TX_ENABLE_BMSK 0x20000 +#define HWIO_IPA_TX_CFG_DUAL_TX_ENABLE_SHFT 0x11 +#define HWIO_IPA_TX_CFG_PREFETCH_ALMOST_EMPTY_SIZE_TX1_BMSK 0x1e000 +#define HWIO_IPA_TX_CFG_PREFETCH_ALMOST_EMPTY_SIZE_TX1_SHFT 0xd +#define HWIO_IPA_TX_CFG_PA_MASK_EN_BMSK 0x1000 +#define HWIO_IPA_TX_CFG_PA_MASK_EN_SHFT 0xc +#define HWIO_IPA_TX_CFG_DMAW_MAX_BEATS_256_DIS_BMSK 0x800 +#define HWIO_IPA_TX_CFG_DMAW_MAX_BEATS_256_DIS_SHFT 0xb +#define HWIO_IPA_TX_CFG_DMAW_SCND_OUTSD_PRED_EN_BMSK 0x400 +#define HWIO_IPA_TX_CFG_DMAW_SCND_OUTSD_PRED_EN_SHFT 0xa +#define HWIO_IPA_TX_CFG_DMAW_SCND_OUTSD_PRED_THRESHOLD_BMSK 0x3c0 +#define HWIO_IPA_TX_CFG_DMAW_SCND_OUTSD_PRED_THRESHOLD_SHFT 0x6 +#define HWIO_IPA_TX_CFG_PREFETCH_ALMOST_EMPTY_SIZE_TX0_BMSK 0x3c +#define HWIO_IPA_TX_CFG_PREFETCH_ALMOST_EMPTY_SIZE_TX0_SHFT 0x2 + +#define HWIO_IPA_NAT_UC_EXTERNAL_CFG_ADDR (IPA_CFG_REG_BASE + 0x0000048c) +#define HWIO_IPA_NAT_UC_EXTERNAL_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000048c) +#define HWIO_IPA_NAT_UC_EXTERNAL_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000048c) +#define HWIO_IPA_NAT_UC_EXTERNAL_CFG_RMSK 0xffffffff +#define HWIO_IPA_NAT_UC_EXTERNAL_CFG_ATTR 0x3 +#define HWIO_IPA_NAT_UC_EXTERNAL_CFG_IN \ + in_dword_masked(HWIO_IPA_NAT_UC_EXTERNAL_CFG_ADDR, HWIO_IPA_NAT_UC_EXTERNAL_CFG_RMSK) +#define HWIO_IPA_NAT_UC_EXTERNAL_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_NAT_UC_EXTERNAL_CFG_ADDR, m) +#define HWIO_IPA_NAT_UC_EXTERNAL_CFG_OUT(v) \ + out_dword(HWIO_IPA_NAT_UC_EXTERNAL_CFG_ADDR,v) +#define HWIO_IPA_NAT_UC_EXTERNAL_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_NAT_UC_EXTERNAL_CFG_ADDR,m,v,HWIO_IPA_NAT_UC_EXTERNAL_CFG_IN) +#define HWIO_IPA_NAT_UC_EXTERNAL_CFG_IPA_NAT_UC_EXTERNAL_TABLE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_IPA_NAT_UC_EXTERNAL_CFG_IPA_NAT_UC_EXTERNAL_TABLE_ADDR_LSB_SHFT 0x0 + +#define HWIO_IPA_NAT_UC_LOCAL_CFG_ADDR (IPA_CFG_REG_BASE + 0x00000490) +#define HWIO_IPA_NAT_UC_LOCAL_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000490) +#define HWIO_IPA_NAT_UC_LOCAL_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000490) +#define HWIO_IPA_NAT_UC_LOCAL_CFG_RMSK 0xffffffff +#define HWIO_IPA_NAT_UC_LOCAL_CFG_ATTR 0x3 +#define HWIO_IPA_NAT_UC_LOCAL_CFG_IN \ + in_dword_masked(HWIO_IPA_NAT_UC_LOCAL_CFG_ADDR, HWIO_IPA_NAT_UC_LOCAL_CFG_RMSK) +#define HWIO_IPA_NAT_UC_LOCAL_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_NAT_UC_LOCAL_CFG_ADDR, m) +#define HWIO_IPA_NAT_UC_LOCAL_CFG_OUT(v) \ + out_dword(HWIO_IPA_NAT_UC_LOCAL_CFG_ADDR,v) +#define HWIO_IPA_NAT_UC_LOCAL_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_NAT_UC_LOCAL_CFG_ADDR,m,v,HWIO_IPA_NAT_UC_LOCAL_CFG_IN) +#define HWIO_IPA_NAT_UC_LOCAL_CFG_IPA_NAT_UC_LOCAL_TABLE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_IPA_NAT_UC_LOCAL_CFG_IPA_NAT_UC_LOCAL_TABLE_ADDR_LSB_SHFT 0x0 + +#define HWIO_IPA_NAT_UC_SHARED_CFG_ADDR (IPA_CFG_REG_BASE + 0x00000494) +#define HWIO_IPA_NAT_UC_SHARED_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000494) +#define HWIO_IPA_NAT_UC_SHARED_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000494) +#define HWIO_IPA_NAT_UC_SHARED_CFG_RMSK 0xffffffff +#define HWIO_IPA_NAT_UC_SHARED_CFG_ATTR 0x3 +#define HWIO_IPA_NAT_UC_SHARED_CFG_IN \ + in_dword_masked(HWIO_IPA_NAT_UC_SHARED_CFG_ADDR, HWIO_IPA_NAT_UC_SHARED_CFG_RMSK) +#define HWIO_IPA_NAT_UC_SHARED_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_NAT_UC_SHARED_CFG_ADDR, m) +#define HWIO_IPA_NAT_UC_SHARED_CFG_OUT(v) \ + out_dword(HWIO_IPA_NAT_UC_SHARED_CFG_ADDR,v) +#define HWIO_IPA_NAT_UC_SHARED_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_NAT_UC_SHARED_CFG_ADDR,m,v,HWIO_IPA_NAT_UC_SHARED_CFG_IN) +#define HWIO_IPA_NAT_UC_SHARED_CFG_IPA_NAT_UC_LOCAL_TABLE_ADDR_MSB_BMSK 0xffff0000 +#define HWIO_IPA_NAT_UC_SHARED_CFG_IPA_NAT_UC_LOCAL_TABLE_ADDR_MSB_SHFT 0x10 +#define HWIO_IPA_NAT_UC_SHARED_CFG_IPA_NAT_UC_EXTERNAL_TABLE_ADDR_MSB_BMSK 0xffff +#define HWIO_IPA_NAT_UC_SHARED_CFG_IPA_NAT_UC_EXTERNAL_TABLE_ADDR_MSB_SHFT 0x0 + +#define HWIO_IPA_RAM_INTLV_CFG_ADDR (IPA_CFG_REG_BASE + 0x00000498) +#define HWIO_IPA_RAM_INTLV_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000498) +#define HWIO_IPA_RAM_INTLV_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000498) +#define HWIO_IPA_RAM_INTLV_CFG_RMSK 0xfffff +#define HWIO_IPA_RAM_INTLV_CFG_ATTR 0x3 +#define HWIO_IPA_RAM_INTLV_CFG_IN \ + in_dword_masked(HWIO_IPA_RAM_INTLV_CFG_ADDR, HWIO_IPA_RAM_INTLV_CFG_RMSK) +#define HWIO_IPA_RAM_INTLV_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_RAM_INTLV_CFG_ADDR, m) +#define HWIO_IPA_RAM_INTLV_CFG_OUT(v) \ + out_dword(HWIO_IPA_RAM_INTLV_CFG_ADDR,v) +#define HWIO_IPA_RAM_INTLV_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_RAM_INTLV_CFG_ADDR,m,v,HWIO_IPA_RAM_INTLV_CFG_IN) +#define HWIO_IPA_RAM_INTLV_CFG_IPA_RAM_INTLV_CFG_BMSK 0xfffff +#define HWIO_IPA_RAM_INTLV_CFG_IPA_RAM_INTLV_CFG_SHFT 0x0 + +#define HWIO_IPA_CONN_TRACK_UC_EXTERNAL_CFG_ADDR (IPA_CFG_REG_BASE + 0x0000049c) +#define HWIO_IPA_CONN_TRACK_UC_EXTERNAL_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000049c) +#define HWIO_IPA_CONN_TRACK_UC_EXTERNAL_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000049c) +#define HWIO_IPA_CONN_TRACK_UC_EXTERNAL_CFG_RMSK 0xffffffff +#define HWIO_IPA_CONN_TRACK_UC_EXTERNAL_CFG_ATTR 0x3 +#define HWIO_IPA_CONN_TRACK_UC_EXTERNAL_CFG_IN \ + in_dword_masked(HWIO_IPA_CONN_TRACK_UC_EXTERNAL_CFG_ADDR, HWIO_IPA_CONN_TRACK_UC_EXTERNAL_CFG_RMSK) +#define HWIO_IPA_CONN_TRACK_UC_EXTERNAL_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_CONN_TRACK_UC_EXTERNAL_CFG_ADDR, m) +#define HWIO_IPA_CONN_TRACK_UC_EXTERNAL_CFG_OUT(v) \ + out_dword(HWIO_IPA_CONN_TRACK_UC_EXTERNAL_CFG_ADDR,v) +#define HWIO_IPA_CONN_TRACK_UC_EXTERNAL_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_CONN_TRACK_UC_EXTERNAL_CFG_ADDR,m,v,HWIO_IPA_CONN_TRACK_UC_EXTERNAL_CFG_IN) +#define HWIO_IPA_CONN_TRACK_UC_EXTERNAL_CFG_IPA_CONN_TRACK_UC_EXTERNAL_TABLE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_IPA_CONN_TRACK_UC_EXTERNAL_CFG_IPA_CONN_TRACK_UC_EXTERNAL_TABLE_ADDR_LSB_SHFT 0x0 + +#define HWIO_IPA_CONN_TRACK_UC_LOCAL_CFG_ADDR (IPA_CFG_REG_BASE + 0x000004a0) +#define HWIO_IPA_CONN_TRACK_UC_LOCAL_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000004a0) +#define HWIO_IPA_CONN_TRACK_UC_LOCAL_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000004a0) +#define HWIO_IPA_CONN_TRACK_UC_LOCAL_CFG_RMSK 0xffffffff +#define HWIO_IPA_CONN_TRACK_UC_LOCAL_CFG_ATTR 0x3 +#define HWIO_IPA_CONN_TRACK_UC_LOCAL_CFG_IN \ + in_dword_masked(HWIO_IPA_CONN_TRACK_UC_LOCAL_CFG_ADDR, HWIO_IPA_CONN_TRACK_UC_LOCAL_CFG_RMSK) +#define HWIO_IPA_CONN_TRACK_UC_LOCAL_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_CONN_TRACK_UC_LOCAL_CFG_ADDR, m) +#define HWIO_IPA_CONN_TRACK_UC_LOCAL_CFG_OUT(v) \ + out_dword(HWIO_IPA_CONN_TRACK_UC_LOCAL_CFG_ADDR,v) +#define HWIO_IPA_CONN_TRACK_UC_LOCAL_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_CONN_TRACK_UC_LOCAL_CFG_ADDR,m,v,HWIO_IPA_CONN_TRACK_UC_LOCAL_CFG_IN) +#define HWIO_IPA_CONN_TRACK_UC_LOCAL_CFG_IPA_CONN_TRACK_UC_LOCAL_TABLE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_IPA_CONN_TRACK_UC_LOCAL_CFG_IPA_CONN_TRACK_UC_LOCAL_TABLE_ADDR_LSB_SHFT 0x0 + +#define HWIO_IPA_CONN_TRACK_UC_SHARED_CFG_ADDR (IPA_CFG_REG_BASE + 0x000004a4) +#define HWIO_IPA_CONN_TRACK_UC_SHARED_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000004a4) +#define HWIO_IPA_CONN_TRACK_UC_SHARED_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000004a4) +#define HWIO_IPA_CONN_TRACK_UC_SHARED_CFG_RMSK 0xffffffff +#define HWIO_IPA_CONN_TRACK_UC_SHARED_CFG_ATTR 0x3 +#define HWIO_IPA_CONN_TRACK_UC_SHARED_CFG_IN \ + in_dword_masked(HWIO_IPA_CONN_TRACK_UC_SHARED_CFG_ADDR, HWIO_IPA_CONN_TRACK_UC_SHARED_CFG_RMSK) +#define HWIO_IPA_CONN_TRACK_UC_SHARED_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_CONN_TRACK_UC_SHARED_CFG_ADDR, m) +#define HWIO_IPA_CONN_TRACK_UC_SHARED_CFG_OUT(v) \ + out_dword(HWIO_IPA_CONN_TRACK_UC_SHARED_CFG_ADDR,v) +#define HWIO_IPA_CONN_TRACK_UC_SHARED_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_CONN_TRACK_UC_SHARED_CFG_ADDR,m,v,HWIO_IPA_CONN_TRACK_UC_SHARED_CFG_IN) +#define HWIO_IPA_CONN_TRACK_UC_SHARED_CFG_IPA_CONN_TRACK_UC_LOCAL_TABLE_ADDR_MSB_BMSK 0xffff0000 +#define HWIO_IPA_CONN_TRACK_UC_SHARED_CFG_IPA_CONN_TRACK_UC_LOCAL_TABLE_ADDR_MSB_SHFT 0x10 +#define HWIO_IPA_CONN_TRACK_UC_SHARED_CFG_IPA_CONN_TRACK_UC_EXTERNAL_TABLE_ADDR_MSB_BMSK 0xffff +#define HWIO_IPA_CONN_TRACK_UC_SHARED_CFG_IPA_CONN_TRACK_UC_EXTERNAL_TABLE_ADDR_MSB_SHFT 0x0 + +#define HWIO_IPA_IDLE_INDICATION_CFG_ADDR (IPA_CFG_REG_BASE + 0x000004a8) +#define HWIO_IPA_IDLE_INDICATION_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000004a8) +#define HWIO_IPA_IDLE_INDICATION_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000004a8) +#define HWIO_IPA_IDLE_INDICATION_CFG_RMSK 0x1ffff +#define HWIO_IPA_IDLE_INDICATION_CFG_ATTR 0x3 +#define HWIO_IPA_IDLE_INDICATION_CFG_IN \ + in_dword_masked(HWIO_IPA_IDLE_INDICATION_CFG_ADDR, HWIO_IPA_IDLE_INDICATION_CFG_RMSK) +#define HWIO_IPA_IDLE_INDICATION_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_IDLE_INDICATION_CFG_ADDR, m) +#define HWIO_IPA_IDLE_INDICATION_CFG_OUT(v) \ + out_dword(HWIO_IPA_IDLE_INDICATION_CFG_ADDR,v) +#define HWIO_IPA_IDLE_INDICATION_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_IDLE_INDICATION_CFG_ADDR,m,v,HWIO_IPA_IDLE_INDICATION_CFG_IN) +#define HWIO_IPA_IDLE_INDICATION_CFG_IDLE_INDICATION_ENABLE_BMSK 0x10000 +#define HWIO_IPA_IDLE_INDICATION_CFG_IDLE_INDICATION_ENABLE_SHFT 0x10 +#define HWIO_IPA_IDLE_INDICATION_CFG_ENTER_IDLE_DEBOUNCE_THRESH_BMSK 0xffff +#define HWIO_IPA_IDLE_INDICATION_CFG_ENTER_IDLE_DEBOUNCE_THRESH_SHFT 0x0 + +#define HWIO_IPA_QTIME_TIMESTAMP_CFG_ADDR (IPA_CFG_REG_BASE + 0x000004ac) +#define HWIO_IPA_QTIME_TIMESTAMP_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000004ac) +#define HWIO_IPA_QTIME_TIMESTAMP_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000004ac) +#define HWIO_IPA_QTIME_TIMESTAMP_CFG_RMSK 0x1f1f00 +#define HWIO_IPA_QTIME_TIMESTAMP_CFG_ATTR 0x3 +#define HWIO_IPA_QTIME_TIMESTAMP_CFG_IN \ + in_dword_masked(HWIO_IPA_QTIME_TIMESTAMP_CFG_ADDR, HWIO_IPA_QTIME_TIMESTAMP_CFG_RMSK) +#define HWIO_IPA_QTIME_TIMESTAMP_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_QTIME_TIMESTAMP_CFG_ADDR, m) +#define HWIO_IPA_QTIME_TIMESTAMP_CFG_OUT(v) \ + out_dword(HWIO_IPA_QTIME_TIMESTAMP_CFG_ADDR,v) +#define HWIO_IPA_QTIME_TIMESTAMP_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_QTIME_TIMESTAMP_CFG_ADDR,m,v,HWIO_IPA_QTIME_TIMESTAMP_CFG_IN) +#define HWIO_IPA_QTIME_TIMESTAMP_CFG_NAT_TIMESTAMP_LSB_BMSK 0x1f0000 +#define HWIO_IPA_QTIME_TIMESTAMP_CFG_NAT_TIMESTAMP_LSB_SHFT 0x10 +#define HWIO_IPA_QTIME_TIMESTAMP_CFG_TAG_TIMESTAMP_LSB_BMSK 0x1f00 +#define HWIO_IPA_QTIME_TIMESTAMP_CFG_TAG_TIMESTAMP_LSB_SHFT 0x8 + +#define HWIO_IPA_TIMERS_XO_CLK_DIV_CFG_ADDR (IPA_CFG_REG_BASE + 0x000004b0) +#define HWIO_IPA_TIMERS_XO_CLK_DIV_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000004b0) +#define HWIO_IPA_TIMERS_XO_CLK_DIV_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000004b0) +#define HWIO_IPA_TIMERS_XO_CLK_DIV_CFG_RMSK 0x800001ff +#define HWIO_IPA_TIMERS_XO_CLK_DIV_CFG_ATTR 0x3 +#define HWIO_IPA_TIMERS_XO_CLK_DIV_CFG_IN \ + in_dword_masked(HWIO_IPA_TIMERS_XO_CLK_DIV_CFG_ADDR, HWIO_IPA_TIMERS_XO_CLK_DIV_CFG_RMSK) +#define HWIO_IPA_TIMERS_XO_CLK_DIV_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_TIMERS_XO_CLK_DIV_CFG_ADDR, m) +#define HWIO_IPA_TIMERS_XO_CLK_DIV_CFG_OUT(v) \ + out_dword(HWIO_IPA_TIMERS_XO_CLK_DIV_CFG_ADDR,v) +#define HWIO_IPA_TIMERS_XO_CLK_DIV_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_TIMERS_XO_CLK_DIV_CFG_ADDR,m,v,HWIO_IPA_TIMERS_XO_CLK_DIV_CFG_IN) +#define HWIO_IPA_TIMERS_XO_CLK_DIV_CFG_ENABLE_BMSK 0x80000000 +#define HWIO_IPA_TIMERS_XO_CLK_DIV_CFG_ENABLE_SHFT 0x1f +#define HWIO_IPA_TIMERS_XO_CLK_DIV_CFG_VALUE_BMSK 0x1ff +#define HWIO_IPA_TIMERS_XO_CLK_DIV_CFG_VALUE_SHFT 0x0 + +#define HWIO_IPA_TIMERS_PULSE_GRAN_CFG_ADDR (IPA_CFG_REG_BASE + 0x000004b4) +#define HWIO_IPA_TIMERS_PULSE_GRAN_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000004b4) +#define HWIO_IPA_TIMERS_PULSE_GRAN_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000004b4) +#define HWIO_IPA_TIMERS_PULSE_GRAN_CFG_RMSK 0xfff +#define HWIO_IPA_TIMERS_PULSE_GRAN_CFG_ATTR 0x3 +#define HWIO_IPA_TIMERS_PULSE_GRAN_CFG_IN \ + in_dword_masked(HWIO_IPA_TIMERS_PULSE_GRAN_CFG_ADDR, HWIO_IPA_TIMERS_PULSE_GRAN_CFG_RMSK) +#define HWIO_IPA_TIMERS_PULSE_GRAN_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_TIMERS_PULSE_GRAN_CFG_ADDR, m) +#define HWIO_IPA_TIMERS_PULSE_GRAN_CFG_OUT(v) \ + out_dword(HWIO_IPA_TIMERS_PULSE_GRAN_CFG_ADDR,v) +#define HWIO_IPA_TIMERS_PULSE_GRAN_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_TIMERS_PULSE_GRAN_CFG_ADDR,m,v,HWIO_IPA_TIMERS_PULSE_GRAN_CFG_IN) +#define HWIO_IPA_TIMERS_PULSE_GRAN_CFG_GRAN_3_BMSK 0xe00 +#define HWIO_IPA_TIMERS_PULSE_GRAN_CFG_GRAN_3_SHFT 0x9 +#define HWIO_IPA_TIMERS_PULSE_GRAN_CFG_GRAN_2_BMSK 0x1c0 +#define HWIO_IPA_TIMERS_PULSE_GRAN_CFG_GRAN_2_SHFT 0x6 +#define HWIO_IPA_TIMERS_PULSE_GRAN_CFG_GRAN_1_BMSK 0x38 +#define HWIO_IPA_TIMERS_PULSE_GRAN_CFG_GRAN_1_SHFT 0x3 +#define HWIO_IPA_TIMERS_PULSE_GRAN_CFG_GRAN_0_BMSK 0x7 +#define HWIO_IPA_TIMERS_PULSE_GRAN_CFG_GRAN_0_SHFT 0x0 + +#define HWIO_IPA_QTIME_LSB_ADDR (IPA_CFG_REG_BASE + 0x000004bc) +#define HWIO_IPA_QTIME_LSB_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000004bc) +#define HWIO_IPA_QTIME_LSB_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000004bc) +#define HWIO_IPA_QTIME_LSB_RMSK 0xffffffff +#define HWIO_IPA_QTIME_LSB_ATTR 0x1 +#define HWIO_IPA_QTIME_LSB_IN \ + in_dword_masked(HWIO_IPA_QTIME_LSB_ADDR, HWIO_IPA_QTIME_LSB_RMSK) +#define HWIO_IPA_QTIME_LSB_INM(m) \ + in_dword_masked(HWIO_IPA_QTIME_LSB_ADDR, m) +#define HWIO_IPA_QTIME_LSB_VALUE_BMSK 0xffffffff +#define HWIO_IPA_QTIME_LSB_VALUE_SHFT 0x0 + +#define HWIO_IPA_QTIME_MSB_ADDR (IPA_CFG_REG_BASE + 0x000004c0) +#define HWIO_IPA_QTIME_MSB_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000004c0) +#define HWIO_IPA_QTIME_MSB_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000004c0) +#define HWIO_IPA_QTIME_MSB_RMSK 0xffffffff +#define HWIO_IPA_QTIME_MSB_ATTR 0x1 +#define HWIO_IPA_QTIME_MSB_IN \ + in_dword_masked(HWIO_IPA_QTIME_MSB_ADDR, HWIO_IPA_QTIME_MSB_RMSK) +#define HWIO_IPA_QTIME_MSB_INM(m) \ + in_dword_masked(HWIO_IPA_QTIME_MSB_ADDR, m) +#define HWIO_IPA_QTIME_MSB_VALUE_BMSK 0xffffffff +#define HWIO_IPA_QTIME_MSB_VALUE_SHFT 0x0 + +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_EN_ADDR (IPA_CFG_REG_BASE + 0x000004c4) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_EN_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000004c4) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_EN_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000004c4) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_EN_RMSK 0xff +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_EN_ATTR 0x3 +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_EN_IN \ + in_dword_masked(HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_EN_ADDR, HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_EN_RMSK) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_EN_INM(m) \ + in_dword_masked(HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_EN_ADDR, m) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_EN_OUT(v) \ + out_dword(HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_EN_ADDR,v) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_EN_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_EN_ADDR,m,v,HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_EN_IN) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_EN_IPA_SRC_RSRC_AMOUNT_REDUCE_EN_BMSK 0xff +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_EN_IPA_SRC_RSRC_AMOUNT_REDUCE_EN_SHFT 0x0 + +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_0_ADDR (IPA_CFG_REG_BASE + 0x000004c8) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_0_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000004c8) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_0_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000004c8) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_0_RMSK 0x3f3f3f3f +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_0_ATTR 0x3 +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_0_IN \ + in_dword_masked(HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_0_ADDR, HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_0_RMSK) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_0_INM(m) \ + in_dword_masked(HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_0_ADDR, m) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_0_OUT(v) \ + out_dword(HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_0_ADDR,v) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_0_ADDR,m,v,HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_0_IN) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_0_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUE_RSRC_TYPE_3_BMSK 0x3f000000 +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_0_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUE_RSRC_TYPE_3_SHFT 0x18 +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_0_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUE_RSRC_TYPE_2_BMSK 0x3f0000 +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_0_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUE_RSRC_TYPE_2_SHFT 0x10 +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_0_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUE_RSRC_TYPE_1_BMSK 0x3f00 +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_0_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUE_RSRC_TYPE_1_SHFT 0x8 +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_0_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUE_RSRC_TYPE_0_BMSK 0x3f +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_0_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUE_RSRC_TYPE_0_SHFT 0x0 + +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_1_ADDR (IPA_CFG_REG_BASE + 0x000004cc) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_1_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000004cc) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_1_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000004cc) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_1_RMSK 0x3f +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_1_ATTR 0x3 +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_1_IN \ + in_dword_masked(HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_1_ADDR, HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_1_RMSK) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_1_INM(m) \ + in_dword_masked(HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_1_ADDR, m) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_1_OUT(v) \ + out_dword(HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_1_ADDR,v) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_1_ADDR,m,v,HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_1_IN) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_1_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUE_RSRC_TYPE_4_BMSK 0x3f +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_1_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUE_RSRC_TYPE_4_SHFT 0x0 + +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_EN_ADDR (IPA_CFG_REG_BASE + 0x000004d0) +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_EN_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000004d0) +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_EN_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000004d0) +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_EN_RMSK 0xf +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_EN_ATTR 0x3 +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_EN_IN \ + in_dword_masked(HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_EN_ADDR, HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_EN_RMSK) +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_EN_INM(m) \ + in_dword_masked(HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_EN_ADDR, m) +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_EN_OUT(v) \ + out_dword(HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_EN_ADDR,v) +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_EN_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_EN_ADDR,m,v,HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_EN_IN) +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_EN_IPA_DST_RSRC_AMOUNT_REDUCE_EN_BMSK 0xf +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_EN_IPA_DST_RSRC_AMOUNT_REDUCE_EN_SHFT 0x0 + +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_VALUES_0_ADDR (IPA_CFG_REG_BASE + 0x000004d4) +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_VALUES_0_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000004d4) +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_VALUES_0_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000004d4) +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_VALUES_0_RMSK 0x3f3f +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_VALUES_0_ATTR 0x3 +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_VALUES_0_IN \ + in_dword_masked(HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_VALUES_0_ADDR, HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_VALUES_0_RMSK) +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_VALUES_0_INM(m) \ + in_dword_masked(HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_VALUES_0_ADDR, m) +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_VALUES_0_OUT(v) \ + out_dword(HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_VALUES_0_ADDR,v) +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_VALUES_0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_VALUES_0_ADDR,m,v,HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_VALUES_0_IN) +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_VALUES_0_IPA_DST_RSRC_AMOUNT_REDUCE_VALUE_RSRC_TYPE_1_BMSK 0x3f00 +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_VALUES_0_IPA_DST_RSRC_AMOUNT_REDUCE_VALUE_RSRC_TYPE_1_SHFT 0x8 +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_VALUES_0_IPA_DST_RSRC_AMOUNT_REDUCE_VALUE_RSRC_TYPE_0_BMSK 0x3f +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_VALUES_0_IPA_DST_RSRC_AMOUNT_REDUCE_VALUE_RSRC_TYPE_0_SHFT 0x0 + +#define HWIO_IPA_ATOMIC_LOCK_CFG_ADDR (IPA_CFG_REG_BASE + 0x000004d8) +#define HWIO_IPA_ATOMIC_LOCK_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000004d8) +#define HWIO_IPA_ATOMIC_LOCK_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000004d8) +#define HWIO_IPA_ATOMIC_LOCK_CFG_RMSK 0x3f +#define HWIO_IPA_ATOMIC_LOCK_CFG_ATTR 0x3 +#define HWIO_IPA_ATOMIC_LOCK_CFG_IN \ + in_dword_masked(HWIO_IPA_ATOMIC_LOCK_CFG_ADDR, HWIO_IPA_ATOMIC_LOCK_CFG_RMSK) +#define HWIO_IPA_ATOMIC_LOCK_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_ATOMIC_LOCK_CFG_ADDR, m) +#define HWIO_IPA_ATOMIC_LOCK_CFG_OUT(v) \ + out_dword(HWIO_IPA_ATOMIC_LOCK_CFG_ADDR,v) +#define HWIO_IPA_ATOMIC_LOCK_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_ATOMIC_LOCK_CFG_ADDR,m,v,HWIO_IPA_ATOMIC_LOCK_CFG_IN) +#define HWIO_IPA_ATOMIC_LOCK_CFG_GROUPS_TO_MASK_BMSK 0x3f +#define HWIO_IPA_ATOMIC_LOCK_CFG_GROUPS_TO_MASK_SHFT 0x0 + +#define HWIO_IPA_GENERIC_RAM_ARBITER_PRIORITY_ADDR (IPA_CFG_REG_BASE + 0x000004dc) +#define HWIO_IPA_GENERIC_RAM_ARBITER_PRIORITY_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000004dc) +#define HWIO_IPA_GENERIC_RAM_ARBITER_PRIORITY_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000004dc) +#define HWIO_IPA_GENERIC_RAM_ARBITER_PRIORITY_RMSK 0xffff3 +#define HWIO_IPA_GENERIC_RAM_ARBITER_PRIORITY_ATTR 0x3 +#define HWIO_IPA_GENERIC_RAM_ARBITER_PRIORITY_IN \ + in_dword_masked(HWIO_IPA_GENERIC_RAM_ARBITER_PRIORITY_ADDR, HWIO_IPA_GENERIC_RAM_ARBITER_PRIORITY_RMSK) +#define HWIO_IPA_GENERIC_RAM_ARBITER_PRIORITY_INM(m) \ + in_dword_masked(HWIO_IPA_GENERIC_RAM_ARBITER_PRIORITY_ADDR, m) +#define HWIO_IPA_GENERIC_RAM_ARBITER_PRIORITY_OUT(v) \ + out_dword(HWIO_IPA_GENERIC_RAM_ARBITER_PRIORITY_ADDR,v) +#define HWIO_IPA_GENERIC_RAM_ARBITER_PRIORITY_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_GENERIC_RAM_ARBITER_PRIORITY_ADDR,m,v,HWIO_IPA_GENERIC_RAM_ARBITER_PRIORITY_IN) +#define HWIO_IPA_GENERIC_RAM_ARBITER_PRIORITY_WR_PRIORITY_INDEX_BMSK 0xff000 +#define HWIO_IPA_GENERIC_RAM_ARBITER_PRIORITY_WR_PRIORITY_INDEX_SHFT 0xc +#define HWIO_IPA_GENERIC_RAM_ARBITER_PRIORITY_RD_PRIORITY_INDEX_BMSK 0xff0 +#define HWIO_IPA_GENERIC_RAM_ARBITER_PRIORITY_RD_PRIORITY_INDEX_SHFT 0x4 +#define HWIO_IPA_GENERIC_RAM_ARBITER_PRIORITY_WR_PRIORITY_VALID_BMSK 0x2 +#define HWIO_IPA_GENERIC_RAM_ARBITER_PRIORITY_WR_PRIORITY_VALID_SHFT 0x1 +#define HWIO_IPA_GENERIC_RAM_ARBITER_PRIORITY_RD_PRIORITY_VALID_BMSK 0x1 +#define HWIO_IPA_GENERIC_RAM_ARBITER_PRIORITY_RD_PRIORITY_VALID_SHFT 0x0 + +#define HWIO_IPA_DPL_TIMER_SW_ADJ_LSB_ADDR (IPA_CFG_REG_BASE + 0x000004ec) +#define HWIO_IPA_DPL_TIMER_SW_ADJ_LSB_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000004ec) +#define HWIO_IPA_DPL_TIMER_SW_ADJ_LSB_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000004ec) +#define HWIO_IPA_DPL_TIMER_SW_ADJ_LSB_RMSK 0xffffffff +#define HWIO_IPA_DPL_TIMER_SW_ADJ_LSB_ATTR 0x3 +#define HWIO_IPA_DPL_TIMER_SW_ADJ_LSB_IN \ + in_dword_masked(HWIO_IPA_DPL_TIMER_SW_ADJ_LSB_ADDR, HWIO_IPA_DPL_TIMER_SW_ADJ_LSB_RMSK) +#define HWIO_IPA_DPL_TIMER_SW_ADJ_LSB_INM(m) \ + in_dword_masked(HWIO_IPA_DPL_TIMER_SW_ADJ_LSB_ADDR, m) +#define HWIO_IPA_DPL_TIMER_SW_ADJ_LSB_OUT(v) \ + out_dword(HWIO_IPA_DPL_TIMER_SW_ADJ_LSB_ADDR,v) +#define HWIO_IPA_DPL_TIMER_SW_ADJ_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_DPL_TIMER_SW_ADJ_LSB_ADDR,m,v,HWIO_IPA_DPL_TIMER_SW_ADJ_LSB_IN) +#define HWIO_IPA_DPL_TIMER_SW_ADJ_LSB_TOD_OFFSET_LSB_BMSK 0xffffffff +#define HWIO_IPA_DPL_TIMER_SW_ADJ_LSB_TOD_OFFSET_LSB_SHFT 0x0 + +#define HWIO_IPA_DPL_TIMER_SW_ADJ_MSB_ADDR (IPA_CFG_REG_BASE + 0x000004f0) +#define HWIO_IPA_DPL_TIMER_SW_ADJ_MSB_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000004f0) +#define HWIO_IPA_DPL_TIMER_SW_ADJ_MSB_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000004f0) +#define HWIO_IPA_DPL_TIMER_SW_ADJ_MSB_RMSK 0xfffff +#define HWIO_IPA_DPL_TIMER_SW_ADJ_MSB_ATTR 0x3 +#define HWIO_IPA_DPL_TIMER_SW_ADJ_MSB_IN \ + in_dword_masked(HWIO_IPA_DPL_TIMER_SW_ADJ_MSB_ADDR, HWIO_IPA_DPL_TIMER_SW_ADJ_MSB_RMSK) +#define HWIO_IPA_DPL_TIMER_SW_ADJ_MSB_INM(m) \ + in_dword_masked(HWIO_IPA_DPL_TIMER_SW_ADJ_MSB_ADDR, m) +#define HWIO_IPA_DPL_TIMER_SW_ADJ_MSB_OUT(v) \ + out_dword(HWIO_IPA_DPL_TIMER_SW_ADJ_MSB_ADDR,v) +#define HWIO_IPA_DPL_TIMER_SW_ADJ_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_DPL_TIMER_SW_ADJ_MSB_ADDR,m,v,HWIO_IPA_DPL_TIMER_SW_ADJ_MSB_IN) +#define HWIO_IPA_DPL_TIMER_SW_ADJ_MSB_TOD_OFFSET_MSB_BMSK 0xfffff +#define HWIO_IPA_DPL_TIMER_SW_ADJ_MSB_TOD_OFFSET_MSB_SHFT 0x0 + +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000500 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000500 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000500 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_RMSK 0x3f3f3f3f +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_MAXn 4 +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_ATTR 0x3 +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_INI(n) \ + in_dword_masked(HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_ADDR(n), HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_RMSK) +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_ADDR(n), mask) +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_OUTI(n,val) \ + out_dword(HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_ADDR(n),val) +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_ADDR(n),mask,val,HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_INI(n)) +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_SRC_RSRC_GRP_1_MAX_LIMIT_BMSK 0x3f000000 +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_SRC_RSRC_GRP_1_MAX_LIMIT_SHFT 0x18 +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_SRC_RSRC_GRP_1_MIN_LIMIT_BMSK 0x3f0000 +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_SRC_RSRC_GRP_1_MIN_LIMIT_SHFT 0x10 +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_SRC_RSRC_GRP_0_MAX_LIMIT_BMSK 0x3f00 +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_SRC_RSRC_GRP_0_MAX_LIMIT_SHFT 0x8 +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_SRC_RSRC_GRP_0_MIN_LIMIT_BMSK 0x3f +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_SRC_RSRC_GRP_0_MIN_LIMIT_SHFT 0x0 + +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000504 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000504 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000504 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_RMSK 0x3f3f3f3f +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_MAXn 4 +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_ATTR 0x3 +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_INI(n) \ + in_dword_masked(HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_ADDR(n), HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_RMSK) +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_ADDR(n), mask) +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_OUTI(n,val) \ + out_dword(HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_ADDR(n),val) +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_ADDR(n),mask,val,HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_INI(n)) +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_SRC_RSRC_GRP_3_MAX_LIMIT_BMSK 0x3f000000 +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_SRC_RSRC_GRP_3_MAX_LIMIT_SHFT 0x18 +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_SRC_RSRC_GRP_3_MIN_LIMIT_BMSK 0x3f0000 +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_SRC_RSRC_GRP_3_MIN_LIMIT_SHFT 0x10 +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_SRC_RSRC_GRP_2_MAX_LIMIT_BMSK 0x3f00 +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_SRC_RSRC_GRP_2_MAX_LIMIT_SHFT 0x8 +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_SRC_RSRC_GRP_2_MIN_LIMIT_BMSK 0x3f +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_SRC_RSRC_GRP_2_MIN_LIMIT_SHFT 0x0 + +#define HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000508 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000508 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000508 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_RMSK 0x3f3f3f3f +#define HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_MAXn 4 +#define HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_ATTR 0x3 +#define HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_INI(n) \ + in_dword_masked(HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_ADDR(n), HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_RMSK) +#define HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_ADDR(n), mask) +#define HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_OUTI(n,val) \ + out_dword(HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_ADDR(n),val) +#define HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_ADDR(n),mask,val,HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_INI(n)) +#define HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_SRC_RSRC_GRP_5_MAX_LIMIT_BMSK 0x3f000000 +#define HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_SRC_RSRC_GRP_5_MAX_LIMIT_SHFT 0x18 +#define HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_SRC_RSRC_GRP_5_MIN_LIMIT_BMSK 0x3f0000 +#define HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_SRC_RSRC_GRP_5_MIN_LIMIT_SHFT 0x10 +#define HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_SRC_RSRC_GRP_4_MAX_LIMIT_BMSK 0x3f00 +#define HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_SRC_RSRC_GRP_4_MAX_LIMIT_SHFT 0x8 +#define HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_SRC_RSRC_GRP_4_MIN_LIMIT_BMSK 0x3f +#define HWIO_IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n_SRC_RSRC_GRP_4_MIN_LIMIT_SHFT 0x0 + +#define HWIO_IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n_ADDR(n) (IPA_CFG_REG_BASE + 0x0000050c + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x0000050c + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x0000050c + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n_RMSK 0x3f3f3f3f +#define HWIO_IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n_MAXn 4 +#define HWIO_IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n_ATTR 0x3 +#define HWIO_IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n_INI(n) \ + in_dword_masked(HWIO_IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n_ADDR(n), HWIO_IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n_RMSK) +#define HWIO_IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n_ADDR(n), mask) +#define HWIO_IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n_OUTI(n,val) \ + out_dword(HWIO_IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n_ADDR(n),val) +#define HWIO_IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n_ADDR(n),mask,val,HWIO_IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n_INI(n)) +#define HWIO_IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n_SRC_RSRC_GRP_7_MAX_LIMIT_BMSK 0x3f000000 +#define HWIO_IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n_SRC_RSRC_GRP_7_MAX_LIMIT_SHFT 0x18 +#define HWIO_IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n_SRC_RSRC_GRP_7_MIN_LIMIT_BMSK 0x3f0000 +#define HWIO_IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n_SRC_RSRC_GRP_7_MIN_LIMIT_SHFT 0x10 +#define HWIO_IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n_SRC_RSRC_GRP_6_MAX_LIMIT_BMSK 0x3f00 +#define HWIO_IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n_SRC_RSRC_GRP_6_MAX_LIMIT_SHFT 0x8 +#define HWIO_IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n_SRC_RSRC_GRP_6_MIN_LIMIT_BMSK 0x3f +#define HWIO_IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n_SRC_RSRC_GRP_6_MIN_LIMIT_SHFT 0x0 + +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000510 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000510 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000510 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_RMSK 0x3f3f3f3f +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_MAXn 4 +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_ATTR 0x1 +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_INI(n) \ + in_dword_masked(HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_ADDR(n), HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_RMSK, HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_ATTR) +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_ADDR(n), mask, HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_ATTR) +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_SRC_RSRC_GRP_3_CNT_BMSK 0x3f000000 +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_SRC_RSRC_GRP_3_CNT_SHFT 0x18 +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_SRC_RSRC_GRP_2_CNT_BMSK 0x3f0000 +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_SRC_RSRC_GRP_2_CNT_SHFT 0x10 +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_SRC_RSRC_GRP_1_CNT_BMSK 0x3f00 +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_SRC_RSRC_GRP_1_CNT_SHFT 0x8 +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_SRC_RSRC_GRP_0_CNT_BMSK 0x3f +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_SRC_RSRC_GRP_0_CNT_SHFT 0x0 + +#define HWIO_IPA_SRC_RSRC_GRP_4567_RSRC_TYPE_CNT_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000514 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_GRP_4567_RSRC_TYPE_CNT_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000514 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_GRP_4567_RSRC_TYPE_CNT_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000514 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_GRP_4567_RSRC_TYPE_CNT_n_RMSK 0x3f3f +#define HWIO_IPA_SRC_RSRC_GRP_4567_RSRC_TYPE_CNT_n_MAXn 4 +#define HWIO_IPA_SRC_RSRC_GRP_4567_RSRC_TYPE_CNT_n_ATTR 0x1 +#define HWIO_IPA_SRC_RSRC_GRP_4567_RSRC_TYPE_CNT_n_INI(n) \ + in_dword_masked(HWIO_IPA_SRC_RSRC_GRP_4567_RSRC_TYPE_CNT_n_ADDR(n), HWIO_IPA_SRC_RSRC_GRP_4567_RSRC_TYPE_CNT_n_RMSK) +#define HWIO_IPA_SRC_RSRC_GRP_4567_RSRC_TYPE_CNT_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_SRC_RSRC_GRP_4567_RSRC_TYPE_CNT_n_ADDR(n), mask) +#define HWIO_IPA_SRC_RSRC_GRP_4567_RSRC_TYPE_CNT_n_SRC_RSRC_GRP_5_CNT_BMSK 0x3f00 +#define HWIO_IPA_SRC_RSRC_GRP_4567_RSRC_TYPE_CNT_n_SRC_RSRC_GRP_5_CNT_SHFT 0x8 +#define HWIO_IPA_SRC_RSRC_GRP_4567_RSRC_TYPE_CNT_n_SRC_RSRC_GRP_4_CNT_BMSK 0x3f +#define HWIO_IPA_SRC_RSRC_GRP_4567_RSRC_TYPE_CNT_n_SRC_RSRC_GRP_4_CNT_SHFT 0x0 + +#define HWIO_IPA_SRC_RSRC_TYPE_AMOUNT_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000518 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_TYPE_AMOUNT_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000518 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_TYPE_AMOUNT_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000518 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_TYPE_AMOUNT_n_RMSK 0x3f +#define HWIO_IPA_SRC_RSRC_TYPE_AMOUNT_n_MAXn 4 +#define HWIO_IPA_SRC_RSRC_TYPE_AMOUNT_n_ATTR 0x1 +#define HWIO_IPA_SRC_RSRC_TYPE_AMOUNT_n_INI(n) \ + in_dword_masked(HWIO_IPA_SRC_RSRC_TYPE_AMOUNT_n_ADDR(n), HWIO_IPA_SRC_RSRC_TYPE_AMOUNT_n_RMSK) +#define HWIO_IPA_SRC_RSRC_TYPE_AMOUNT_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_SRC_RSRC_TYPE_AMOUNT_n_ADDR(n), mask) +#define HWIO_IPA_SRC_RSRC_TYPE_AMOUNT_n_SRC_RSRC_TYPE_AMOUNT_BMSK 0x3f +#define HWIO_IPA_SRC_RSRC_TYPE_AMOUNT_n_SRC_RSRC_TYPE_AMOUNT_SHFT 0x0 + +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000600 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000600 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000600 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_RMSK 0x3f3f3f3f +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_MAXn 2 +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_ATTR 0x3 +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_INI(n) \ + in_dword_masked(HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_ADDR(n), HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_RMSK) +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_ADDR(n), mask) +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_OUTI(n,val) \ + out_dword(HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_ADDR(n),val) +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_ADDR(n),mask,val,HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_INI(n)) +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_DST_RSRC_GRP_1_MAX_LIMIT_BMSK 0x3f000000 +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_DST_RSRC_GRP_1_MAX_LIMIT_SHFT 0x18 +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_DST_RSRC_GRP_1_MIN_LIMIT_BMSK 0x3f0000 +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_DST_RSRC_GRP_1_MIN_LIMIT_SHFT 0x10 +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_DST_RSRC_GRP_0_MAX_LIMIT_BMSK 0x3f00 +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_DST_RSRC_GRP_0_MAX_LIMIT_SHFT 0x8 +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_DST_RSRC_GRP_0_MIN_LIMIT_BMSK 0x3f +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_DST_RSRC_GRP_0_MIN_LIMIT_SHFT 0x0 + +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000604 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000604 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000604 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_RMSK 0x3f3f3f3f +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_MAXn 2 +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_ATTR 0x3 +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_INI(n) \ + in_dword_masked(HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_ADDR(n), HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_RMSK) +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_ADDR(n), mask) +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_OUTI(n,val) \ + out_dword(HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_ADDR(n),val) +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_ADDR(n),mask,val,HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_INI(n)) +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_DST_RSRC_GRP_3_MAX_LIMIT_BMSK 0x3f000000 +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_DST_RSRC_GRP_3_MAX_LIMIT_SHFT 0x18 +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_DST_RSRC_GRP_3_MIN_LIMIT_BMSK 0x3f0000 +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_DST_RSRC_GRP_3_MIN_LIMIT_SHFT 0x10 +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_DST_RSRC_GRP_2_MAX_LIMIT_BMSK 0x3f00 +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_DST_RSRC_GRP_2_MAX_LIMIT_SHFT 0x8 +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_DST_RSRC_GRP_2_MIN_LIMIT_BMSK 0x3f +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_DST_RSRC_GRP_2_MIN_LIMIT_SHFT 0x0 + +#define HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000608 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000608 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000608 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_RMSK 0x3f3f3f3f +#define HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_MAXn 2 +#define HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_ATTR 0x3 +#define HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_INI(n) \ + in_dword_masked(HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_ADDR(n), HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_RMSK) +#define HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_ADDR(n), mask) +#define HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_OUTI(n,val) \ + out_dword(HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_ADDR(n),val) +#define HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_ADDR(n),mask,val,HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_INI(n)) +#define HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_DST_RSRC_GRP_5_MAX_LIMIT_BMSK 0x3f000000 +#define HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_DST_RSRC_GRP_5_MAX_LIMIT_SHFT 0x18 +#define HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_DST_RSRC_GRP_5_MIN_LIMIT_BMSK 0x3f0000 +#define HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_DST_RSRC_GRP_5_MIN_LIMIT_SHFT 0x10 +#define HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_DST_RSRC_GRP_4_MAX_LIMIT_BMSK 0x3f00 +#define HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_DST_RSRC_GRP_4_MAX_LIMIT_SHFT 0x8 +#define HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_DST_RSRC_GRP_4_MIN_LIMIT_BMSK 0x3f +#define HWIO_IPA_DST_RSRC_GRP_45_RSRC_TYPE_n_DST_RSRC_GRP_4_MIN_LIMIT_SHFT 0x0 + +#define HWIO_IPA_DST_RSRC_GRP_67_RSRC_TYPE_n_ADDR(n) (IPA_CFG_REG_BASE + 0x0000060c + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_67_RSRC_TYPE_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x0000060c + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_67_RSRC_TYPE_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x0000060c + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_67_RSRC_TYPE_n_RMSK 0x3f3f +#define HWIO_IPA_DST_RSRC_GRP_67_RSRC_TYPE_n_MAXn 2 +#define HWIO_IPA_DST_RSRC_GRP_67_RSRC_TYPE_n_ATTR 0x3 +#define HWIO_IPA_DST_RSRC_GRP_67_RSRC_TYPE_n_INI(n) \ + in_dword_masked(HWIO_IPA_DST_RSRC_GRP_67_RSRC_TYPE_n_ADDR(n), HWIO_IPA_DST_RSRC_GRP_67_RSRC_TYPE_n_RMSK) +#define HWIO_IPA_DST_RSRC_GRP_67_RSRC_TYPE_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_DST_RSRC_GRP_67_RSRC_TYPE_n_ADDR(n), mask) +#define HWIO_IPA_DST_RSRC_GRP_67_RSRC_TYPE_n_OUTI(n,val) \ + out_dword(HWIO_IPA_DST_RSRC_GRP_67_RSRC_TYPE_n_ADDR(n),val) +#define HWIO_IPA_DST_RSRC_GRP_67_RSRC_TYPE_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_DST_RSRC_GRP_67_RSRC_TYPE_n_ADDR(n),mask,val,HWIO_IPA_DST_RSRC_GRP_67_RSRC_TYPE_n_INI(n)) +#define HWIO_IPA_DST_RSRC_GRP_67_RSRC_TYPE_n_DST_RSRC_GRP_6_MAX_LIMIT_BMSK 0x3f00 +#define HWIO_IPA_DST_RSRC_GRP_67_RSRC_TYPE_n_DST_RSRC_GRP_6_MAX_LIMIT_SHFT 0x8 +#define HWIO_IPA_DST_RSRC_GRP_67_RSRC_TYPE_n_DST_RSRC_GRP_6_MIN_LIMIT_BMSK 0x3f +#define HWIO_IPA_DST_RSRC_GRP_67_RSRC_TYPE_n_DST_RSRC_GRP_6_MIN_LIMIT_SHFT 0x0 + +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000610 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000610 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000610 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_RMSK 0x3f3f3f3f +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_MAXn 2 +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_ATTR 0x1 +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_INI(n) \ + in_dword_masked(HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_ADDR(n), HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_RMSK, HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_ATTR) +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_ADDR(n), mask, HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_ATTR) +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_DST_RSRC_GRP_3_CNT_BMSK 0x3f000000 +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_DST_RSRC_GRP_3_CNT_SHFT 0x18 +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_DST_RSRC_GRP_2_CNT_BMSK 0x3f0000 +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_DST_RSRC_GRP_2_CNT_SHFT 0x10 +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_DST_RSRC_GRP_1_CNT_BMSK 0x3f00 +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_DST_RSRC_GRP_1_CNT_SHFT 0x8 +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_DST_RSRC_GRP_0_CNT_BMSK 0x3f +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_DST_RSRC_GRP_0_CNT_SHFT 0x0 + +#define HWIO_IPA_DST_RSRC_GRP_4567_RSRC_TYPE_CNT_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000614 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_4567_RSRC_TYPE_CNT_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000614 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_4567_RSRC_TYPE_CNT_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000614 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_4567_RSRC_TYPE_CNT_n_RMSK 0xffffff +#define HWIO_IPA_DST_RSRC_GRP_4567_RSRC_TYPE_CNT_n_MAXn 2 +#define HWIO_IPA_DST_RSRC_GRP_4567_RSRC_TYPE_CNT_n_ATTR 0x1 +#define HWIO_IPA_DST_RSRC_GRP_4567_RSRC_TYPE_CNT_n_INI(n) \ + in_dword_masked(HWIO_IPA_DST_RSRC_GRP_4567_RSRC_TYPE_CNT_n_ADDR(n), HWIO_IPA_DST_RSRC_GRP_4567_RSRC_TYPE_CNT_n_RMSK) +#define HWIO_IPA_DST_RSRC_GRP_4567_RSRC_TYPE_CNT_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_DST_RSRC_GRP_4567_RSRC_TYPE_CNT_n_ADDR(n), mask) +#define HWIO_IPA_DST_RSRC_GRP_4567_RSRC_TYPE_CNT_n_DST_RSRC_GRP_6_CNT_BMSK 0xff0000 +#define HWIO_IPA_DST_RSRC_GRP_4567_RSRC_TYPE_CNT_n_DST_RSRC_GRP_6_CNT_SHFT 0x10 +#define HWIO_IPA_DST_RSRC_GRP_4567_RSRC_TYPE_CNT_n_DST_RSRC_GRP_5_CNT_BMSK 0xff00 +#define HWIO_IPA_DST_RSRC_GRP_4567_RSRC_TYPE_CNT_n_DST_RSRC_GRP_5_CNT_SHFT 0x8 +#define HWIO_IPA_DST_RSRC_GRP_4567_RSRC_TYPE_CNT_n_DST_RSRC_GRP_4_CNT_BMSK 0xff +#define HWIO_IPA_DST_RSRC_GRP_4567_RSRC_TYPE_CNT_n_DST_RSRC_GRP_4_CNT_SHFT 0x0 + +#define HWIO_IPA_DST_RSRC_TYPE_AMOUNT_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000618 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_TYPE_AMOUNT_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000618 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_TYPE_AMOUNT_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000618 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_TYPE_AMOUNT_n_RMSK 0x3f +#define HWIO_IPA_DST_RSRC_TYPE_AMOUNT_n_MAXn 2 +#define HWIO_IPA_DST_RSRC_TYPE_AMOUNT_n_ATTR 0x1 +#define HWIO_IPA_DST_RSRC_TYPE_AMOUNT_n_INI(n) \ + in_dword_masked(HWIO_IPA_DST_RSRC_TYPE_AMOUNT_n_ADDR(n), HWIO_IPA_DST_RSRC_TYPE_AMOUNT_n_RMSK) +#define HWIO_IPA_DST_RSRC_TYPE_AMOUNT_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_DST_RSRC_TYPE_AMOUNT_n_ADDR(n), mask) +#define HWIO_IPA_DST_RSRC_TYPE_AMOUNT_n_DST_RSRC_TYPE_AMOUNT_BMSK 0x3f +#define HWIO_IPA_DST_RSRC_TYPE_AMOUNT_n_DST_RSRC_TYPE_AMOUNT_SHFT 0x0 + +#define HWIO_IPA_RX_CFG_ADDR (IPA_CFG_REG_BASE + 0x00000698) +#define HWIO_IPA_RX_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000698) +#define HWIO_IPA_RX_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000698) +#define HWIO_IPA_RX_CFG_RMSK 0x3 +#define HWIO_IPA_RX_CFG_ATTR 0x3 +#define HWIO_IPA_RX_CFG_IN \ + in_dword_masked(HWIO_IPA_RX_CFG_ADDR, HWIO_IPA_RX_CFG_RMSK) +#define HWIO_IPA_RX_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_RX_CFG_ADDR, m) +#define HWIO_IPA_RX_CFG_OUT(v) \ + out_dword(HWIO_IPA_RX_CFG_ADDR,v) +#define HWIO_IPA_RX_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_RX_CFG_ADDR,m,v,HWIO_IPA_RX_CFG_IN) +#define HWIO_IPA_RX_CFG_RX_CMDQ_SPLITTER_CMDQ_PENDING_MUX_DISABLE_BMSK 0x2 +#define HWIO_IPA_RX_CFG_RX_CMDQ_SPLITTER_CMDQ_PENDING_MUX_DISABLE_SHFT 0x1 +#define HWIO_IPA_RX_CFG_CMDQ_SPLIT_NOT_WAIT_DATA_DESC_PRIOR_HDR_PUSH_BMSK 0x1 +#define HWIO_IPA_RX_CFG_CMDQ_SPLIT_NOT_WAIT_DATA_DESC_PRIOR_HDR_PUSH_SHFT 0x0 + +#define HWIO_IPA_RSRC_GRP_CFG_ADDR (IPA_CFG_REG_BASE + 0x000006a0) +#define HWIO_IPA_RSRC_GRP_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000006a0) +#define HWIO_IPA_RSRC_GRP_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000006a0) +#define HWIO_IPA_RSRC_GRP_CFG_RMSK 0x3f1ff171 +#define HWIO_IPA_RSRC_GRP_CFG_ATTR 0x3 +#define HWIO_IPA_RSRC_GRP_CFG_IN \ + in_dword_masked(HWIO_IPA_RSRC_GRP_CFG_ADDR, HWIO_IPA_RSRC_GRP_CFG_RMSK) +#define HWIO_IPA_RSRC_GRP_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_RSRC_GRP_CFG_ADDR, m) +#define HWIO_IPA_RSRC_GRP_CFG_OUT(v) \ + out_dword(HWIO_IPA_RSRC_GRP_CFG_ADDR,v) +#define HWIO_IPA_RSRC_GRP_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_RSRC_GRP_CFG_ADDR,m,v,HWIO_IPA_RSRC_GRP_CFG_IN) +#define HWIO_IPA_RSRC_GRP_CFG_DST_GRP_SPECIAL_INDEX_BMSK 0x3f000000 +#define HWIO_IPA_RSRC_GRP_CFG_DST_GRP_SPECIAL_INDEX_SHFT 0x18 +#define HWIO_IPA_RSRC_GRP_CFG_DST_GRP_SPECIAL_VALID_BMSK 0x100000 +#define HWIO_IPA_RSRC_GRP_CFG_DST_GRP_SPECIAL_VALID_SHFT 0x14 +#define HWIO_IPA_RSRC_GRP_CFG_DST_PIPE_SPECIAL_INDEX_BMSK 0xff000 +#define HWIO_IPA_RSRC_GRP_CFG_DST_PIPE_SPECIAL_INDEX_SHFT 0xc +#define HWIO_IPA_RSRC_GRP_CFG_DST_PIPE_SPECIAL_VALID_BMSK 0x100 +#define HWIO_IPA_RSRC_GRP_CFG_DST_PIPE_SPECIAL_VALID_SHFT 0x8 +#define HWIO_IPA_RSRC_GRP_CFG_SRC_GRP_SPECIAL_INDEX_BMSK 0x70 +#define HWIO_IPA_RSRC_GRP_CFG_SRC_GRP_SPECIAL_INDEX_SHFT 0x4 +#define HWIO_IPA_RSRC_GRP_CFG_SRC_GRP_SPECIAL_VALID_BMSK 0x1 +#define HWIO_IPA_RSRC_GRP_CFG_SRC_GRP_SPECIAL_VALID_SHFT 0x0 + +#define HWIO_IPA_RSRC_GRP_CFG_EXT_ADDR (IPA_CFG_REG_BASE + 0x000006a4) +#define HWIO_IPA_RSRC_GRP_CFG_EXT_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000006a4) +#define HWIO_IPA_RSRC_GRP_CFG_EXT_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000006a4) +#define HWIO_IPA_RSRC_GRP_CFG_EXT_RMSK 0x71 +#define HWIO_IPA_RSRC_GRP_CFG_EXT_ATTR 0x3 +#define HWIO_IPA_RSRC_GRP_CFG_EXT_IN \ + in_dword_masked(HWIO_IPA_RSRC_GRP_CFG_EXT_ADDR, HWIO_IPA_RSRC_GRP_CFG_EXT_RMSK) +#define HWIO_IPA_RSRC_GRP_CFG_EXT_INM(m) \ + in_dword_masked(HWIO_IPA_RSRC_GRP_CFG_EXT_ADDR, m) +#define HWIO_IPA_RSRC_GRP_CFG_EXT_OUT(v) \ + out_dword(HWIO_IPA_RSRC_GRP_CFG_EXT_ADDR,v) +#define HWIO_IPA_RSRC_GRP_CFG_EXT_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_RSRC_GRP_CFG_EXT_ADDR,m,v,HWIO_IPA_RSRC_GRP_CFG_EXT_IN) +#define HWIO_IPA_RSRC_GRP_CFG_EXT_SRC_GRP_2ND_PRIORITY_SPECIAL_INDEX_BMSK 0x70 +#define HWIO_IPA_RSRC_GRP_CFG_EXT_SRC_GRP_2ND_PRIORITY_SPECIAL_INDEX_SHFT 0x4 +#define HWIO_IPA_RSRC_GRP_CFG_EXT_SRC_GRP_2ND_PRIORITY_SPECIAL_VALID_BMSK 0x1 +#define HWIO_IPA_RSRC_GRP_CFG_EXT_SRC_GRP_2ND_PRIORITY_SPECIAL_VALID_SHFT 0x0 + +#define HWIO_IPA_AXI_CFG_ADDR (IPA_CFG_REG_BASE + 0x000006ac) +#define HWIO_IPA_AXI_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000006ac) +#define HWIO_IPA_AXI_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000006ac) +#define HWIO_IPA_AXI_CFG_RMSK 0xf +#define HWIO_IPA_AXI_CFG_ATTR 0x3 +#define HWIO_IPA_AXI_CFG_IN \ + in_dword_masked(HWIO_IPA_AXI_CFG_ADDR, HWIO_IPA_AXI_CFG_RMSK) +#define HWIO_IPA_AXI_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_AXI_CFG_ADDR, m) +#define HWIO_IPA_AXI_CFG_OUT(v) \ + out_dword(HWIO_IPA_AXI_CFG_ADDR,v) +#define HWIO_IPA_AXI_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_AXI_CFG_ADDR,m,v,HWIO_IPA_AXI_CFG_IN) +#define HWIO_IPA_AXI_CFG_RELAXED_ORDERING_IPA_WR_BMSK 0x8 +#define HWIO_IPA_AXI_CFG_RELAXED_ORDERING_IPA_WR_SHFT 0x3 +#define HWIO_IPA_AXI_CFG_RELAXED_ORDERING_IPA_RD_BMSK 0x4 +#define HWIO_IPA_AXI_CFG_RELAXED_ORDERING_IPA_RD_SHFT 0x2 +#define HWIO_IPA_AXI_CFG_RELAXED_ORDERING_GSI_WR_BMSK 0x2 +#define HWIO_IPA_AXI_CFG_RELAXED_ORDERING_GSI_WR_SHFT 0x1 +#define HWIO_IPA_AXI_CFG_RELAXED_ORDERING_GSI_RD_BMSK 0x1 +#define HWIO_IPA_AXI_CFG_RELAXED_ORDERING_GSI_RD_SHFT 0x0 + +#define HWIO_IPA_AGGR_FORCE_CLOSE_n_ADDR(n) (IPA_CFG_REG_BASE + 0x000006b0 + 0x4 * (n)) +#define HWIO_IPA_AGGR_FORCE_CLOSE_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x000006b0 + 0x4 * (n)) +#define HWIO_IPA_AGGR_FORCE_CLOSE_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x000006b0 + 0x4 * (n)) +#define HWIO_IPA_AGGR_FORCE_CLOSE_n_RMSK 0xffffffff +#define HWIO_IPA_AGGR_FORCE_CLOSE_n_MAXn 1 +#define HWIO_IPA_AGGR_FORCE_CLOSE_n_ATTR 0x2 +#define HWIO_IPA_AGGR_FORCE_CLOSE_n_OUTI(n,val) \ + out_dword(HWIO_IPA_AGGR_FORCE_CLOSE_n_ADDR(n),val) +#define HWIO_IPA_AGGR_FORCE_CLOSE_n_AGGR_FORCE_CLOSE_PIPE_BITMAP_BMSK 0xffffffff +#define HWIO_IPA_AGGR_FORCE_CLOSE_n_AGGR_FORCE_CLOSE_PIPE_BITMAP_SHFT 0x0 + +#define HWIO_IPA_STAT_QUOTA_BASE_n_ADDR(n) (IPA_CFG_REG_BASE + 0x000006d0 + 0x4 * (n)) +#define HWIO_IPA_STAT_QUOTA_BASE_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x000006d0 + 0x4 * (n)) +#define HWIO_IPA_STAT_QUOTA_BASE_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x000006d0 + 0x4 * (n)) +#define HWIO_IPA_STAT_QUOTA_BASE_n_RMSK 0x7ffff +#define HWIO_IPA_STAT_QUOTA_BASE_n_MAXn 1 +#define HWIO_IPA_STAT_QUOTA_BASE_n_ATTR 0x3 +#define HWIO_IPA_STAT_QUOTA_BASE_n_INI(n) \ + in_dword_masked(HWIO_IPA_STAT_QUOTA_BASE_n_ADDR(n), HWIO_IPA_STAT_QUOTA_BASE_n_RMSK) +#define HWIO_IPA_STAT_QUOTA_BASE_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_STAT_QUOTA_BASE_n_ADDR(n), mask) +#define HWIO_IPA_STAT_QUOTA_BASE_n_OUTI(n,val) \ + out_dword(HWIO_IPA_STAT_QUOTA_BASE_n_ADDR(n),val) +#define HWIO_IPA_STAT_QUOTA_BASE_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_STAT_QUOTA_BASE_n_ADDR(n),mask,val,HWIO_IPA_STAT_QUOTA_BASE_n_INI(n)) +#define HWIO_IPA_STAT_QUOTA_BASE_n_BASE_ADDR_BMSK 0x7fff8 +#define HWIO_IPA_STAT_QUOTA_BASE_n_BASE_ADDR_SHFT 0x3 +#define HWIO_IPA_STAT_QUOTA_BASE_n_BASE_ADDR_OFFSET_BMSK 0x7 +#define HWIO_IPA_STAT_QUOTA_BASE_n_BASE_ADDR_OFFSET_SHFT 0x0 + +#define HWIO_IPA_STAT_TETHERING_BASE_n_ADDR(n) (IPA_CFG_REG_BASE + 0x000006e0 + 0x4 * (n)) +#define HWIO_IPA_STAT_TETHERING_BASE_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x000006e0 + 0x4 * (n)) +#define HWIO_IPA_STAT_TETHERING_BASE_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x000006e0 + 0x4 * (n)) +#define HWIO_IPA_STAT_TETHERING_BASE_n_RMSK 0x7ffff +#define HWIO_IPA_STAT_TETHERING_BASE_n_MAXn 1 +#define HWIO_IPA_STAT_TETHERING_BASE_n_ATTR 0x3 +#define HWIO_IPA_STAT_TETHERING_BASE_n_INI(n) \ + in_dword_masked(HWIO_IPA_STAT_TETHERING_BASE_n_ADDR(n), HWIO_IPA_STAT_TETHERING_BASE_n_RMSK) +#define HWIO_IPA_STAT_TETHERING_BASE_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_STAT_TETHERING_BASE_n_ADDR(n), mask) +#define HWIO_IPA_STAT_TETHERING_BASE_n_OUTI(n,val) \ + out_dword(HWIO_IPA_STAT_TETHERING_BASE_n_ADDR(n),val) +#define HWIO_IPA_STAT_TETHERING_BASE_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_STAT_TETHERING_BASE_n_ADDR(n),mask,val,HWIO_IPA_STAT_TETHERING_BASE_n_INI(n)) +#define HWIO_IPA_STAT_TETHERING_BASE_n_BASE_ADDR_BMSK 0x7fff8 +#define HWIO_IPA_STAT_TETHERING_BASE_n_BASE_ADDR_SHFT 0x3 +#define HWIO_IPA_STAT_TETHERING_BASE_n_BASE_ADDR_OFFSET_BMSK 0x7 +#define HWIO_IPA_STAT_TETHERING_BASE_n_BASE_ADDR_OFFSET_SHFT 0x0 + +#define HWIO_IPA_STAT_DROP_CNT_BASE_n_ADDR(n) (IPA_CFG_REG_BASE + 0x000006f0 + 0x4 * (n)) +#define HWIO_IPA_STAT_DROP_CNT_BASE_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x000006f0 + 0x4 * (n)) +#define HWIO_IPA_STAT_DROP_CNT_BASE_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x000006f0 + 0x4 * (n)) +#define HWIO_IPA_STAT_DROP_CNT_BASE_n_RMSK 0x7ffff +#define HWIO_IPA_STAT_DROP_CNT_BASE_n_MAXn 1 +#define HWIO_IPA_STAT_DROP_CNT_BASE_n_ATTR 0x3 +#define HWIO_IPA_STAT_DROP_CNT_BASE_n_INI(n) \ + in_dword_masked(HWIO_IPA_STAT_DROP_CNT_BASE_n_ADDR(n), HWIO_IPA_STAT_DROP_CNT_BASE_n_RMSK) +#define HWIO_IPA_STAT_DROP_CNT_BASE_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_STAT_DROP_CNT_BASE_n_ADDR(n), mask) +#define HWIO_IPA_STAT_DROP_CNT_BASE_n_OUTI(n,val) \ + out_dword(HWIO_IPA_STAT_DROP_CNT_BASE_n_ADDR(n),val) +#define HWIO_IPA_STAT_DROP_CNT_BASE_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_STAT_DROP_CNT_BASE_n_ADDR(n),mask,val,HWIO_IPA_STAT_DROP_CNT_BASE_n_INI(n)) +#define HWIO_IPA_STAT_DROP_CNT_BASE_n_BASE_ADDR_BMSK 0x7fff8 +#define HWIO_IPA_STAT_DROP_CNT_BASE_n_BASE_ADDR_SHFT 0x3 +#define HWIO_IPA_STAT_DROP_CNT_BASE_n_BASE_ADDR_OFFSET_BMSK 0x7 +#define HWIO_IPA_STAT_DROP_CNT_BASE_n_BASE_ADDR_OFFSET_SHFT 0x0 + +#define HWIO_IPA_STAT_FILTER_IPV4_BASE_ADDR (IPA_CFG_REG_BASE + 0x00000700) +#define HWIO_IPA_STAT_FILTER_IPV4_BASE_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000700) +#define HWIO_IPA_STAT_FILTER_IPV4_BASE_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000700) +#define HWIO_IPA_STAT_FILTER_IPV4_BASE_RMSK 0x7ffff +#define HWIO_IPA_STAT_FILTER_IPV4_BASE_ATTR 0x3 +#define HWIO_IPA_STAT_FILTER_IPV4_BASE_IN \ + in_dword_masked(HWIO_IPA_STAT_FILTER_IPV4_BASE_ADDR, HWIO_IPA_STAT_FILTER_IPV4_BASE_RMSK) +#define HWIO_IPA_STAT_FILTER_IPV4_BASE_INM(m) \ + in_dword_masked(HWIO_IPA_STAT_FILTER_IPV4_BASE_ADDR, m) +#define HWIO_IPA_STAT_FILTER_IPV4_BASE_OUT(v) \ + out_dword(HWIO_IPA_STAT_FILTER_IPV4_BASE_ADDR,v) +#define HWIO_IPA_STAT_FILTER_IPV4_BASE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_STAT_FILTER_IPV4_BASE_ADDR,m,v,HWIO_IPA_STAT_FILTER_IPV4_BASE_IN) +#define HWIO_IPA_STAT_FILTER_IPV4_BASE_BASE_ADDR_BMSK 0x7fff8 +#define HWIO_IPA_STAT_FILTER_IPV4_BASE_BASE_ADDR_SHFT 0x3 +#define HWIO_IPA_STAT_FILTER_IPV4_BASE_BASE_ADDR_OFFSET_BMSK 0x7 +#define HWIO_IPA_STAT_FILTER_IPV4_BASE_BASE_ADDR_OFFSET_SHFT 0x0 + +#define HWIO_IPA_STAT_FILTER_IPV6_BASE_ADDR (IPA_CFG_REG_BASE + 0x00000704) +#define HWIO_IPA_STAT_FILTER_IPV6_BASE_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000704) +#define HWIO_IPA_STAT_FILTER_IPV6_BASE_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000704) +#define HWIO_IPA_STAT_FILTER_IPV6_BASE_RMSK 0x7ffff +#define HWIO_IPA_STAT_FILTER_IPV6_BASE_ATTR 0x3 +#define HWIO_IPA_STAT_FILTER_IPV6_BASE_IN \ + in_dword_masked(HWIO_IPA_STAT_FILTER_IPV6_BASE_ADDR, HWIO_IPA_STAT_FILTER_IPV6_BASE_RMSK) +#define HWIO_IPA_STAT_FILTER_IPV6_BASE_INM(m) \ + in_dword_masked(HWIO_IPA_STAT_FILTER_IPV6_BASE_ADDR, m) +#define HWIO_IPA_STAT_FILTER_IPV6_BASE_OUT(v) \ + out_dword(HWIO_IPA_STAT_FILTER_IPV6_BASE_ADDR,v) +#define HWIO_IPA_STAT_FILTER_IPV6_BASE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_STAT_FILTER_IPV6_BASE_ADDR,m,v,HWIO_IPA_STAT_FILTER_IPV6_BASE_IN) +#define HWIO_IPA_STAT_FILTER_IPV6_BASE_BASE_ADDR_BMSK 0x7fff8 +#define HWIO_IPA_STAT_FILTER_IPV6_BASE_BASE_ADDR_SHFT 0x3 +#define HWIO_IPA_STAT_FILTER_IPV6_BASE_BASE_ADDR_OFFSET_BMSK 0x7 +#define HWIO_IPA_STAT_FILTER_IPV6_BASE_BASE_ADDR_OFFSET_SHFT 0x0 + +#define HWIO_IPA_STAT_ROUTER_IPV4_BASE_ADDR (IPA_CFG_REG_BASE + 0x00000708) +#define HWIO_IPA_STAT_ROUTER_IPV4_BASE_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000708) +#define HWIO_IPA_STAT_ROUTER_IPV4_BASE_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000708) +#define HWIO_IPA_STAT_ROUTER_IPV4_BASE_RMSK 0x7ffff +#define HWIO_IPA_STAT_ROUTER_IPV4_BASE_ATTR 0x3 +#define HWIO_IPA_STAT_ROUTER_IPV4_BASE_IN \ + in_dword_masked(HWIO_IPA_STAT_ROUTER_IPV4_BASE_ADDR, HWIO_IPA_STAT_ROUTER_IPV4_BASE_RMSK) +#define HWIO_IPA_STAT_ROUTER_IPV4_BASE_INM(m) \ + in_dword_masked(HWIO_IPA_STAT_ROUTER_IPV4_BASE_ADDR, m) +#define HWIO_IPA_STAT_ROUTER_IPV4_BASE_OUT(v) \ + out_dword(HWIO_IPA_STAT_ROUTER_IPV4_BASE_ADDR,v) +#define HWIO_IPA_STAT_ROUTER_IPV4_BASE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_STAT_ROUTER_IPV4_BASE_ADDR,m,v,HWIO_IPA_STAT_ROUTER_IPV4_BASE_IN) +#define HWIO_IPA_STAT_ROUTER_IPV4_BASE_BASE_ADDR_BMSK 0x7fff8 +#define HWIO_IPA_STAT_ROUTER_IPV4_BASE_BASE_ADDR_SHFT 0x3 +#define HWIO_IPA_STAT_ROUTER_IPV4_BASE_BASE_ADDR_OFFSET_BMSK 0x7 +#define HWIO_IPA_STAT_ROUTER_IPV4_BASE_BASE_ADDR_OFFSET_SHFT 0x0 + +#define HWIO_IPA_STAT_ROUTER_IPV6_BASE_ADDR (IPA_CFG_REG_BASE + 0x0000070c) +#define HWIO_IPA_STAT_ROUTER_IPV6_BASE_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000070c) +#define HWIO_IPA_STAT_ROUTER_IPV6_BASE_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000070c) +#define HWIO_IPA_STAT_ROUTER_IPV6_BASE_RMSK 0x7ffff +#define HWIO_IPA_STAT_ROUTER_IPV6_BASE_ATTR 0x3 +#define HWIO_IPA_STAT_ROUTER_IPV6_BASE_IN \ + in_dword_masked(HWIO_IPA_STAT_ROUTER_IPV6_BASE_ADDR, HWIO_IPA_STAT_ROUTER_IPV6_BASE_RMSK) +#define HWIO_IPA_STAT_ROUTER_IPV6_BASE_INM(m) \ + in_dword_masked(HWIO_IPA_STAT_ROUTER_IPV6_BASE_ADDR, m) +#define HWIO_IPA_STAT_ROUTER_IPV6_BASE_OUT(v) \ + out_dword(HWIO_IPA_STAT_ROUTER_IPV6_BASE_ADDR,v) +#define HWIO_IPA_STAT_ROUTER_IPV6_BASE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_STAT_ROUTER_IPV6_BASE_ADDR,m,v,HWIO_IPA_STAT_ROUTER_IPV6_BASE_IN) +#define HWIO_IPA_STAT_ROUTER_IPV6_BASE_BASE_ADDR_BMSK 0x7fff8 +#define HWIO_IPA_STAT_ROUTER_IPV6_BASE_BASE_ADDR_SHFT 0x3 +#define HWIO_IPA_STAT_ROUTER_IPV6_BASE_BASE_ADDR_OFFSET_BMSK 0x7 +#define HWIO_IPA_STAT_ROUTER_IPV6_BASE_BASE_ADDR_OFFSET_SHFT 0x0 + +#define HWIO_IPA_STAT_QUOTA_MASK_EE_n_REG_k_ADDR(n,k) (IPA_CFG_REG_BASE + 0x00000710 + 0x4 * (n) + 0x8 * (k)) +#define HWIO_IPA_STAT_QUOTA_MASK_EE_n_REG_k_PHYS(n,k) (IPA_CFG_REG_BASE_PHYS + 0x00000710 + 0x4 * (n) + 0x8 * (k)) +#define HWIO_IPA_STAT_QUOTA_MASK_EE_n_REG_k_OFFS(n,k) (IPA_CFG_REG_BASE_OFFS + 0x00000710 + 0x4 * (n) + 0x8 * (k)) +#define HWIO_IPA_STAT_QUOTA_MASK_EE_n_REG_k_RMSK 0xffffffff +#define HWIO_IPA_STAT_QUOTA_MASK_EE_n_REG_k_MAXn 1 +#define HWIO_IPA_STAT_QUOTA_MASK_EE_n_REG_k_MAXk 1 +#define HWIO_IPA_STAT_QUOTA_MASK_EE_n_REG_k_ATTR 0x3 +#define HWIO_IPA_STAT_QUOTA_MASK_EE_n_REG_k_INI2(n,k) \ + in_dword_masked(HWIO_IPA_STAT_QUOTA_MASK_EE_n_REG_k_ADDR(n,k), HWIO_IPA_STAT_QUOTA_MASK_EE_n_REG_k_RMSK) +#define HWIO_IPA_STAT_QUOTA_MASK_EE_n_REG_k_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_STAT_QUOTA_MASK_EE_n_REG_k_ADDR(n,k), mask) +#define HWIO_IPA_STAT_QUOTA_MASK_EE_n_REG_k_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_STAT_QUOTA_MASK_EE_n_REG_k_ADDR(n,k),val) +#define HWIO_IPA_STAT_QUOTA_MASK_EE_n_REG_k_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_STAT_QUOTA_MASK_EE_n_REG_k_ADDR(n,k),mask,val,HWIO_IPA_STAT_QUOTA_MASK_EE_n_REG_k_INI2(n,k)) +#define HWIO_IPA_STAT_QUOTA_MASK_EE_n_REG_k_PIPE_MASK_BMSK 0xffffffff +#define HWIO_IPA_STAT_QUOTA_MASK_EE_n_REG_k_PIPE_MASK_SHFT 0x0 + +#define HWIO_IPA_STAT_TETHERING_MASK_EE_n_REG_k_ADDR(n,k) (IPA_CFG_REG_BASE + 0x00000750 + 0x4 * (n) + 0x8 * (k)) +#define HWIO_IPA_STAT_TETHERING_MASK_EE_n_REG_k_PHYS(n,k) (IPA_CFG_REG_BASE_PHYS + 0x00000750 + 0x4 * (n) + 0x8 * (k)) +#define HWIO_IPA_STAT_TETHERING_MASK_EE_n_REG_k_OFFS(n,k) (IPA_CFG_REG_BASE_OFFS + 0x00000750 + 0x4 * (n) + 0x8 * (k)) +#define HWIO_IPA_STAT_TETHERING_MASK_EE_n_REG_k_RMSK 0xffffffff +#define HWIO_IPA_STAT_TETHERING_MASK_EE_n_REG_k_MAXn 1 +#define HWIO_IPA_STAT_TETHERING_MASK_EE_n_REG_k_MAXk 1 +#define HWIO_IPA_STAT_TETHERING_MASK_EE_n_REG_k_ATTR 0x3 +#define HWIO_IPA_STAT_TETHERING_MASK_EE_n_REG_k_INI2(n,k) \ + in_dword_masked(HWIO_IPA_STAT_TETHERING_MASK_EE_n_REG_k_ADDR(n,k), HWIO_IPA_STAT_TETHERING_MASK_EE_n_REG_k_RMSK) +#define HWIO_IPA_STAT_TETHERING_MASK_EE_n_REG_k_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_STAT_TETHERING_MASK_EE_n_REG_k_ADDR(n,k), mask) +#define HWIO_IPA_STAT_TETHERING_MASK_EE_n_REG_k_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_STAT_TETHERING_MASK_EE_n_REG_k_ADDR(n,k),val) +#define HWIO_IPA_STAT_TETHERING_MASK_EE_n_REG_k_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_STAT_TETHERING_MASK_EE_n_REG_k_ADDR(n,k),mask,val,HWIO_IPA_STAT_TETHERING_MASK_EE_n_REG_k_INI2(n,k)) +#define HWIO_IPA_STAT_TETHERING_MASK_EE_n_REG_k_PIPE_MASK_BMSK 0xffffffff +#define HWIO_IPA_STAT_TETHERING_MASK_EE_n_REG_k_PIPE_MASK_SHFT 0x0 + +#define HWIO_IPA_STAT_DROP_CNT_MASK_EE_n_REG_k_ADDR(n,k) (IPA_CFG_REG_BASE + 0x00000790 + 0x4 * (n) + 0x8 * (k)) +#define HWIO_IPA_STAT_DROP_CNT_MASK_EE_n_REG_k_PHYS(n,k) (IPA_CFG_REG_BASE_PHYS + 0x00000790 + 0x4 * (n) + 0x8 * (k)) +#define HWIO_IPA_STAT_DROP_CNT_MASK_EE_n_REG_k_OFFS(n,k) (IPA_CFG_REG_BASE_OFFS + 0x00000790 + 0x4 * (n) + 0x8 * (k)) +#define HWIO_IPA_STAT_DROP_CNT_MASK_EE_n_REG_k_RMSK 0xffffffff +#define HWIO_IPA_STAT_DROP_CNT_MASK_EE_n_REG_k_MAXn 1 +#define HWIO_IPA_STAT_DROP_CNT_MASK_EE_n_REG_k_MAXk 1 +#define HWIO_IPA_STAT_DROP_CNT_MASK_EE_n_REG_k_ATTR 0x3 +#define HWIO_IPA_STAT_DROP_CNT_MASK_EE_n_REG_k_INI2(n,k) \ + in_dword_masked(HWIO_IPA_STAT_DROP_CNT_MASK_EE_n_REG_k_ADDR(n,k), HWIO_IPA_STAT_DROP_CNT_MASK_EE_n_REG_k_RMSK) +#define HWIO_IPA_STAT_DROP_CNT_MASK_EE_n_REG_k_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_STAT_DROP_CNT_MASK_EE_n_REG_k_ADDR(n,k), mask) +#define HWIO_IPA_STAT_DROP_CNT_MASK_EE_n_REG_k_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_STAT_DROP_CNT_MASK_EE_n_REG_k_ADDR(n,k),val) +#define HWIO_IPA_STAT_DROP_CNT_MASK_EE_n_REG_k_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_STAT_DROP_CNT_MASK_EE_n_REG_k_ADDR(n,k),mask,val,HWIO_IPA_STAT_DROP_CNT_MASK_EE_n_REG_k_INI2(n,k)) +#define HWIO_IPA_STAT_DROP_CNT_MASK_EE_n_REG_k_PIPE_MASK_BMSK 0xffffffff +#define HWIO_IPA_STAT_DROP_CNT_MASK_EE_n_REG_k_PIPE_MASK_SHFT 0x0 + +#define HWIO_IPA_NLO_PP_CFG1_ADDR (IPA_CFG_REG_BASE + 0x000007d0) +#define HWIO_IPA_NLO_PP_CFG1_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000007d0) +#define HWIO_IPA_NLO_PP_CFG1_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000007d0) +#define HWIO_IPA_NLO_PP_CFG1_RMSK 0xffffffff +#define HWIO_IPA_NLO_PP_CFG1_ATTR 0x3 +#define HWIO_IPA_NLO_PP_CFG1_IN \ + in_dword_masked(HWIO_IPA_NLO_PP_CFG1_ADDR, HWIO_IPA_NLO_PP_CFG1_RMSK) +#define HWIO_IPA_NLO_PP_CFG1_INM(m) \ + in_dword_masked(HWIO_IPA_NLO_PP_CFG1_ADDR, m) +#define HWIO_IPA_NLO_PP_CFG1_OUT(v) \ + out_dword(HWIO_IPA_NLO_PP_CFG1_ADDR,v) +#define HWIO_IPA_NLO_PP_CFG1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_NLO_PP_CFG1_ADDR,m,v,HWIO_IPA_NLO_PP_CFG1_IN) +#define HWIO_IPA_NLO_PP_CFG1_NLO_ACK_MAX_VP_BMSK 0xff000000 +#define HWIO_IPA_NLO_PP_CFG1_NLO_ACK_MAX_VP_SHFT 0x18 +#define HWIO_IPA_NLO_PP_CFG1_NLO_STATUS_PP_BMSK 0xff0000 +#define HWIO_IPA_NLO_PP_CFG1_NLO_STATUS_PP_SHFT 0x10 +#define HWIO_IPA_NLO_PP_CFG1_NLO_DATA_PP_BMSK 0xff00 +#define HWIO_IPA_NLO_PP_CFG1_NLO_DATA_PP_SHFT 0x8 +#define HWIO_IPA_NLO_PP_CFG1_NLO_ACK_PP_BMSK 0xff +#define HWIO_IPA_NLO_PP_CFG1_NLO_ACK_PP_SHFT 0x0 + +#define HWIO_IPA_NLO_PP_CFG2_ADDR (IPA_CFG_REG_BASE + 0x000007d4) +#define HWIO_IPA_NLO_PP_CFG2_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000007d4) +#define HWIO_IPA_NLO_PP_CFG2_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000007d4) +#define HWIO_IPA_NLO_PP_CFG2_RMSK 0x7ffff +#define HWIO_IPA_NLO_PP_CFG2_ATTR 0x3 +#define HWIO_IPA_NLO_PP_CFG2_IN \ + in_dword_masked(HWIO_IPA_NLO_PP_CFG2_ADDR, HWIO_IPA_NLO_PP_CFG2_RMSK) +#define HWIO_IPA_NLO_PP_CFG2_INM(m) \ + in_dword_masked(HWIO_IPA_NLO_PP_CFG2_ADDR, m) +#define HWIO_IPA_NLO_PP_CFG2_OUT(v) \ + out_dword(HWIO_IPA_NLO_PP_CFG2_ADDR,v) +#define HWIO_IPA_NLO_PP_CFG2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_NLO_PP_CFG2_ADDR,m,v,HWIO_IPA_NLO_PP_CFG2_IN) +#define HWIO_IPA_NLO_PP_CFG2_NLO_STATUS_BUFFER_MODE_BMSK 0x40000 +#define HWIO_IPA_NLO_PP_CFG2_NLO_STATUS_BUFFER_MODE_SHFT 0x12 +#define HWIO_IPA_NLO_PP_CFG2_NLO_DATA_BUFFER_MODE_BMSK 0x20000 +#define HWIO_IPA_NLO_PP_CFG2_NLO_DATA_BUFFER_MODE_SHFT 0x11 +#define HWIO_IPA_NLO_PP_CFG2_NLO_ACK_BUFFER_MODE_BMSK 0x10000 +#define HWIO_IPA_NLO_PP_CFG2_NLO_ACK_BUFFER_MODE_SHFT 0x10 +#define HWIO_IPA_NLO_PP_CFG2_NLO_DATA_CLOSE_PADD_BMSK 0xff00 +#define HWIO_IPA_NLO_PP_CFG2_NLO_DATA_CLOSE_PADD_SHFT 0x8 +#define HWIO_IPA_NLO_PP_CFG2_NLO_ACK_CLOSE_PADD_BMSK 0xff +#define HWIO_IPA_NLO_PP_CFG2_NLO_ACK_CLOSE_PADD_SHFT 0x0 + +#define HWIO_IPA_NLO_MIN_DSM_CFG_ADDR (IPA_CFG_REG_BASE + 0x000007d8) +#define HWIO_IPA_NLO_MIN_DSM_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000007d8) +#define HWIO_IPA_NLO_MIN_DSM_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000007d8) +#define HWIO_IPA_NLO_MIN_DSM_CFG_RMSK 0xffffffff +#define HWIO_IPA_NLO_MIN_DSM_CFG_ATTR 0x3 +#define HWIO_IPA_NLO_MIN_DSM_CFG_IN \ + in_dword_masked(HWIO_IPA_NLO_MIN_DSM_CFG_ADDR, HWIO_IPA_NLO_MIN_DSM_CFG_RMSK) +#define HWIO_IPA_NLO_MIN_DSM_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_NLO_MIN_DSM_CFG_ADDR, m) +#define HWIO_IPA_NLO_MIN_DSM_CFG_OUT(v) \ + out_dword(HWIO_IPA_NLO_MIN_DSM_CFG_ADDR,v) +#define HWIO_IPA_NLO_MIN_DSM_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_NLO_MIN_DSM_CFG_ADDR,m,v,HWIO_IPA_NLO_MIN_DSM_CFG_IN) +#define HWIO_IPA_NLO_MIN_DSM_CFG_NLO_DATA_MIN_DSM_LEN_BMSK 0xffff0000 +#define HWIO_IPA_NLO_MIN_DSM_CFG_NLO_DATA_MIN_DSM_LEN_SHFT 0x10 +#define HWIO_IPA_NLO_MIN_DSM_CFG_NLO_ACK_MIN_DSM_LEN_BMSK 0xffff +#define HWIO_IPA_NLO_MIN_DSM_CFG_NLO_ACK_MIN_DSM_LEN_SHFT 0x0 + +#define HWIO_IPA_NLO_VP_AGGR_CFG_LSB_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000800 + 0x8 * (n)) +#define HWIO_IPA_NLO_VP_AGGR_CFG_LSB_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000800 + 0x8 * (n)) +#define HWIO_IPA_NLO_VP_AGGR_CFG_LSB_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000800 + 0x8 * (n)) +#define HWIO_IPA_NLO_VP_AGGR_CFG_LSB_n_RMSK 0x7ffff +#define HWIO_IPA_NLO_VP_AGGR_CFG_LSB_n_MAXn 31 +#define HWIO_IPA_NLO_VP_AGGR_CFG_LSB_n_ATTR 0x3 +#define HWIO_IPA_NLO_VP_AGGR_CFG_LSB_n_INI(n) \ + in_dword_masked(HWIO_IPA_NLO_VP_AGGR_CFG_LSB_n_ADDR(n), HWIO_IPA_NLO_VP_AGGR_CFG_LSB_n_RMSK) +#define HWIO_IPA_NLO_VP_AGGR_CFG_LSB_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_NLO_VP_AGGR_CFG_LSB_n_ADDR(n), mask) +#define HWIO_IPA_NLO_VP_AGGR_CFG_LSB_n_OUTI(n,val) \ + out_dword(HWIO_IPA_NLO_VP_AGGR_CFG_LSB_n_ADDR(n),val) +#define HWIO_IPA_NLO_VP_AGGR_CFG_LSB_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_NLO_VP_AGGR_CFG_LSB_n_ADDR(n),mask,val,HWIO_IPA_NLO_VP_AGGR_CFG_LSB_n_INI(n)) +#define HWIO_IPA_NLO_VP_AGGR_CFG_LSB_n_VP_AGGR_GRAN_SEL_BMSK 0x40000 +#define HWIO_IPA_NLO_VP_AGGR_CFG_LSB_n_VP_AGGR_GRAN_SEL_SHFT 0x12 +#define HWIO_IPA_NLO_VP_AGGR_CFG_LSB_n_VP_HARD_BYTE_LIMIT_EN_BMSK 0x20000 +#define HWIO_IPA_NLO_VP_AGGR_CFG_LSB_n_VP_HARD_BYTE_LIMIT_EN_SHFT 0x11 +#define HWIO_IPA_NLO_VP_AGGR_CFG_LSB_n_VP_BYTE_LIMIT_BMSK 0x1f800 +#define HWIO_IPA_NLO_VP_AGGR_CFG_LSB_n_VP_BYTE_LIMIT_SHFT 0xb +#define HWIO_IPA_NLO_VP_AGGR_CFG_LSB_n_VP_TIME_LIMIT_BMSK 0x7c0 +#define HWIO_IPA_NLO_VP_AGGR_CFG_LSB_n_VP_TIME_LIMIT_SHFT 0x6 +#define HWIO_IPA_NLO_VP_AGGR_CFG_LSB_n_VP_PKT_LIMIT_BMSK 0x3f +#define HWIO_IPA_NLO_VP_AGGR_CFG_LSB_n_VP_PKT_LIMIT_SHFT 0x0 + +#define HWIO_IPA_NLO_VP_LIMIT_CFG_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000804 + 0x8 * (n)) +#define HWIO_IPA_NLO_VP_LIMIT_CFG_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000804 + 0x8 * (n)) +#define HWIO_IPA_NLO_VP_LIMIT_CFG_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000804 + 0x8 * (n)) +#define HWIO_IPA_NLO_VP_LIMIT_CFG_n_RMSK 0xffffffff +#define HWIO_IPA_NLO_VP_LIMIT_CFG_n_MAXn 31 +#define HWIO_IPA_NLO_VP_LIMIT_CFG_n_ATTR 0x3 +#define HWIO_IPA_NLO_VP_LIMIT_CFG_n_INI(n) \ + in_dword_masked(HWIO_IPA_NLO_VP_LIMIT_CFG_n_ADDR(n), HWIO_IPA_NLO_VP_LIMIT_CFG_n_RMSK) +#define HWIO_IPA_NLO_VP_LIMIT_CFG_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_NLO_VP_LIMIT_CFG_n_ADDR(n), mask) +#define HWIO_IPA_NLO_VP_LIMIT_CFG_n_OUTI(n,val) \ + out_dword(HWIO_IPA_NLO_VP_LIMIT_CFG_n_ADDR(n),val) +#define HWIO_IPA_NLO_VP_LIMIT_CFG_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_NLO_VP_LIMIT_CFG_n_ADDR(n),mask,val,HWIO_IPA_NLO_VP_LIMIT_CFG_n_INI(n)) +#define HWIO_IPA_NLO_VP_LIMIT_CFG_n_UPPER_SIZE_BMSK 0xffff0000 +#define HWIO_IPA_NLO_VP_LIMIT_CFG_n_UPPER_SIZE_SHFT 0x10 +#define HWIO_IPA_NLO_VP_LIMIT_CFG_n_LOWER_SIZE_BMSK 0xffff +#define HWIO_IPA_NLO_VP_LIMIT_CFG_n_LOWER_SIZE_SHFT 0x0 + +#define HWIO_IPA_NLO_VP_FLUSH_REQ_ADDR (IPA_CFG_REG_BASE + 0x00000900) +#define HWIO_IPA_NLO_VP_FLUSH_REQ_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000900) +#define HWIO_IPA_NLO_VP_FLUSH_REQ_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000900) +#define HWIO_IPA_NLO_VP_FLUSH_REQ_RMSK 0x80ff00ff +#define HWIO_IPA_NLO_VP_FLUSH_REQ_ATTR 0x3 +#define HWIO_IPA_NLO_VP_FLUSH_REQ_IN \ + in_dword_masked(HWIO_IPA_NLO_VP_FLUSH_REQ_ADDR, HWIO_IPA_NLO_VP_FLUSH_REQ_RMSK) +#define HWIO_IPA_NLO_VP_FLUSH_REQ_INM(m) \ + in_dword_masked(HWIO_IPA_NLO_VP_FLUSH_REQ_ADDR, m) +#define HWIO_IPA_NLO_VP_FLUSH_REQ_OUT(v) \ + out_dword(HWIO_IPA_NLO_VP_FLUSH_REQ_ADDR,v) +#define HWIO_IPA_NLO_VP_FLUSH_REQ_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_NLO_VP_FLUSH_REQ_ADDR,m,v,HWIO_IPA_NLO_VP_FLUSH_REQ_IN) +#define HWIO_IPA_NLO_VP_FLUSH_REQ_VP_FLUSH_REQ_BMSK 0x80000000 +#define HWIO_IPA_NLO_VP_FLUSH_REQ_VP_FLUSH_REQ_SHFT 0x1f +#define HWIO_IPA_NLO_VP_FLUSH_REQ_VP_FLUSH_VP_INDX_BMSK 0xff0000 +#define HWIO_IPA_NLO_VP_FLUSH_REQ_VP_FLUSH_VP_INDX_SHFT 0x10 +#define HWIO_IPA_NLO_VP_FLUSH_REQ_VP_FLUSH_PP_INDX_BMSK 0xff +#define HWIO_IPA_NLO_VP_FLUSH_REQ_VP_FLUSH_PP_INDX_SHFT 0x0 + +#define HWIO_IPA_NLO_VP_FLUSH_COOKIE_ADDR (IPA_CFG_REG_BASE + 0x00000904) +#define HWIO_IPA_NLO_VP_FLUSH_COOKIE_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000904) +#define HWIO_IPA_NLO_VP_FLUSH_COOKIE_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000904) +#define HWIO_IPA_NLO_VP_FLUSH_COOKIE_RMSK 0xffffffff +#define HWIO_IPA_NLO_VP_FLUSH_COOKIE_ATTR 0x1 +#define HWIO_IPA_NLO_VP_FLUSH_COOKIE_IN \ + in_dword_masked(HWIO_IPA_NLO_VP_FLUSH_COOKIE_ADDR, HWIO_IPA_NLO_VP_FLUSH_COOKIE_RMSK) +#define HWIO_IPA_NLO_VP_FLUSH_COOKIE_INM(m) \ + in_dword_masked(HWIO_IPA_NLO_VP_FLUSH_COOKIE_ADDR, m) +#define HWIO_IPA_NLO_VP_FLUSH_COOKIE_VP_FLUSH_COOKIE_BMSK 0xffffffff +#define HWIO_IPA_NLO_VP_FLUSH_COOKIE_VP_FLUSH_COOKIE_SHFT 0x0 + +#define HWIO_IPA_NLO_VP_FLUSH_ACK_ADDR (IPA_CFG_REG_BASE + 0x00000908) +#define HWIO_IPA_NLO_VP_FLUSH_ACK_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000908) +#define HWIO_IPA_NLO_VP_FLUSH_ACK_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000908) +#define HWIO_IPA_NLO_VP_FLUSH_ACK_RMSK 0x1 +#define HWIO_IPA_NLO_VP_FLUSH_ACK_ATTR 0x1 +#define HWIO_IPA_NLO_VP_FLUSH_ACK_IN \ + in_dword_masked(HWIO_IPA_NLO_VP_FLUSH_ACK_ADDR, HWIO_IPA_NLO_VP_FLUSH_ACK_RMSK) +#define HWIO_IPA_NLO_VP_FLUSH_ACK_INM(m) \ + in_dword_masked(HWIO_IPA_NLO_VP_FLUSH_ACK_ADDR, m) +#define HWIO_IPA_NLO_VP_FLUSH_ACK_VP_FLUSH_ACK_BMSK 0x1 +#define HWIO_IPA_NLO_VP_FLUSH_ACK_VP_FLUSH_ACK_SHFT 0x0 + +#define HWIO_IPA_NLO_VP_DSM_OPEN_ADDR (IPA_CFG_REG_BASE + 0x0000090c) +#define HWIO_IPA_NLO_VP_DSM_OPEN_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000090c) +#define HWIO_IPA_NLO_VP_DSM_OPEN_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000090c) +#define HWIO_IPA_NLO_VP_DSM_OPEN_RMSK 0xffffffff +#define HWIO_IPA_NLO_VP_DSM_OPEN_ATTR 0x1 +#define HWIO_IPA_NLO_VP_DSM_OPEN_IN \ + in_dword_masked(HWIO_IPA_NLO_VP_DSM_OPEN_ADDR, HWIO_IPA_NLO_VP_DSM_OPEN_RMSK) +#define HWIO_IPA_NLO_VP_DSM_OPEN_INM(m) \ + in_dword_masked(HWIO_IPA_NLO_VP_DSM_OPEN_ADDR, m) +#define HWIO_IPA_NLO_VP_DSM_OPEN_VP_DSM_OPEN_BMSK 0xffffffff +#define HWIO_IPA_NLO_VP_DSM_OPEN_VP_DSM_OPEN_SHFT 0x0 + +#define HWIO_IPA_NLO_VP_QBAP_OPEN_ADDR (IPA_CFG_REG_BASE + 0x00000910) +#define HWIO_IPA_NLO_VP_QBAP_OPEN_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000910) +#define HWIO_IPA_NLO_VP_QBAP_OPEN_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000910) +#define HWIO_IPA_NLO_VP_QBAP_OPEN_RMSK 0xffffffff +#define HWIO_IPA_NLO_VP_QBAP_OPEN_ATTR 0x1 +#define HWIO_IPA_NLO_VP_QBAP_OPEN_IN \ + in_dword_masked(HWIO_IPA_NLO_VP_QBAP_OPEN_ADDR, HWIO_IPA_NLO_VP_QBAP_OPEN_RMSK) +#define HWIO_IPA_NLO_VP_QBAP_OPEN_INM(m) \ + in_dword_masked(HWIO_IPA_NLO_VP_QBAP_OPEN_ADDR, m) +#define HWIO_IPA_NLO_VP_QBAP_OPEN_VP_QBAP_OPEN_BMSK 0xffffffff +#define HWIO_IPA_NLO_VP_QBAP_OPEN_VP_QBAP_OPEN_SHFT 0x0 + +#define HWIO_IPA_COAL_MASTER_CFG_ADDR (IPA_CFG_REG_BASE + 0x00000914) +#define HWIO_IPA_COAL_MASTER_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000914) +#define HWIO_IPA_COAL_MASTER_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000914) +#define HWIO_IPA_COAL_MASTER_CFG_RMSK 0x7 +#define HWIO_IPA_COAL_MASTER_CFG_ATTR 0x3 +#define HWIO_IPA_COAL_MASTER_CFG_IN \ + in_dword_masked(HWIO_IPA_COAL_MASTER_CFG_ADDR, HWIO_IPA_COAL_MASTER_CFG_RMSK) +#define HWIO_IPA_COAL_MASTER_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_COAL_MASTER_CFG_ADDR, m) +#define HWIO_IPA_COAL_MASTER_CFG_OUT(v) \ + out_dword(HWIO_IPA_COAL_MASTER_CFG_ADDR,v) +#define HWIO_IPA_COAL_MASTER_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_COAL_MASTER_CFG_ADDR,m,v,HWIO_IPA_COAL_MASTER_CFG_IN) +#define HWIO_IPA_COAL_MASTER_CFG_COAL_IPV4_ID_IGNORE_BMSK 0x4 +#define HWIO_IPA_COAL_MASTER_CFG_COAL_IPV4_ID_IGNORE_SHFT 0x2 +#define HWIO_IPA_COAL_MASTER_CFG_COAL_ENHANCED_IPV4_ID_EN_BMSK 0x2 +#define HWIO_IPA_COAL_MASTER_CFG_COAL_ENHANCED_IPV4_ID_EN_SHFT 0x1 +#define HWIO_IPA_COAL_MASTER_CFG_COAL_FORCE_TO_DEFAULT_BMSK 0x1 +#define HWIO_IPA_COAL_MASTER_CFG_COAL_FORCE_TO_DEFAULT_SHFT 0x0 + +#define HWIO_IPA_COAL_EVICT_LRU_ADDR (IPA_CFG_REG_BASE + 0x00000918) +#define HWIO_IPA_COAL_EVICT_LRU_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000918) +#define HWIO_IPA_COAL_EVICT_LRU_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000918) +#define HWIO_IPA_COAL_EVICT_LRU_RMSK 0xfffff +#define HWIO_IPA_COAL_EVICT_LRU_ATTR 0x3 +#define HWIO_IPA_COAL_EVICT_LRU_IN \ + in_dword_masked(HWIO_IPA_COAL_EVICT_LRU_ADDR, HWIO_IPA_COAL_EVICT_LRU_RMSK) +#define HWIO_IPA_COAL_EVICT_LRU_INM(m) \ + in_dword_masked(HWIO_IPA_COAL_EVICT_LRU_ADDR, m) +#define HWIO_IPA_COAL_EVICT_LRU_OUT(v) \ + out_dword(HWIO_IPA_COAL_EVICT_LRU_ADDR,v) +#define HWIO_IPA_COAL_EVICT_LRU_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_COAL_EVICT_LRU_ADDR,m,v,HWIO_IPA_COAL_EVICT_LRU_IN) +#define HWIO_IPA_COAL_EVICT_LRU_COAL_VP_LRU_TCP_NUM_BMSK 0xf8000 +#define HWIO_IPA_COAL_EVICT_LRU_COAL_VP_LRU_TCP_NUM_SHFT 0xf +#define HWIO_IPA_COAL_EVICT_LRU_COAL_VP_LRU_TCP_THRSHLD_EN_BMSK 0x4000 +#define HWIO_IPA_COAL_EVICT_LRU_COAL_VP_LRU_TCP_THRSHLD_EN_SHFT 0xe +#define HWIO_IPA_COAL_EVICT_LRU_COAL_VP_LRU_UDP_THRSHLD_EN_BMSK 0x2000 +#define HWIO_IPA_COAL_EVICT_LRU_COAL_VP_LRU_UDP_THRSHLD_EN_SHFT 0xd +#define HWIO_IPA_COAL_EVICT_LRU_COAL_VP_LRU_TCP_THRSHLD_BMSK 0x1f00 +#define HWIO_IPA_COAL_EVICT_LRU_COAL_VP_LRU_TCP_THRSHLD_SHFT 0x8 +#define HWIO_IPA_COAL_EVICT_LRU_COAL_VP_LRU_UDP_THRSHLD_BMSK 0xf8 +#define HWIO_IPA_COAL_EVICT_LRU_COAL_VP_LRU_UDP_THRSHLD_SHFT 0x3 +#define HWIO_IPA_COAL_EVICT_LRU_COAL_VP_LRU_GRAN_SEL_BMSK 0x6 +#define HWIO_IPA_COAL_EVICT_LRU_COAL_VP_LRU_GRAN_SEL_SHFT 0x1 +#define HWIO_IPA_COAL_EVICT_LRU_COAL_EVICTION_EN_BMSK 0x1 +#define HWIO_IPA_COAL_EVICT_LRU_COAL_EVICTION_EN_SHFT 0x0 + +#define HWIO_IPA_COAL_QMAP_CFG_ADDR (IPA_CFG_REG_BASE + 0x0000091c) +#define HWIO_IPA_COAL_QMAP_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000091c) +#define HWIO_IPA_COAL_QMAP_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000091c) +#define HWIO_IPA_COAL_QMAP_CFG_RMSK 0x3 +#define HWIO_IPA_COAL_QMAP_CFG_ATTR 0x3 +#define HWIO_IPA_COAL_QMAP_CFG_IN \ + in_dword_masked(HWIO_IPA_COAL_QMAP_CFG_ADDR, HWIO_IPA_COAL_QMAP_CFG_RMSK) +#define HWIO_IPA_COAL_QMAP_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_COAL_QMAP_CFG_ADDR, m) +#define HWIO_IPA_COAL_QMAP_CFG_OUT(v) \ + out_dword(HWIO_IPA_COAL_QMAP_CFG_ADDR,v) +#define HWIO_IPA_COAL_QMAP_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_COAL_QMAP_CFG_ADDR,m,v,HWIO_IPA_COAL_QMAP_CFG_IN) +#define HWIO_IPA_COAL_QMAP_CFG_MUX_ID_BYTE_SEL_BMSK 0x3 +#define HWIO_IPA_COAL_QMAP_CFG_MUX_ID_BYTE_SEL_SHFT 0x0 + +#define HWIO_IPA_SNIFFER_QMB_SEL_ADDR (IPA_CFG_REG_BASE + 0x00000920) +#define HWIO_IPA_SNIFFER_QMB_SEL_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000920) +#define HWIO_IPA_SNIFFER_QMB_SEL_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000920) +#define HWIO_IPA_SNIFFER_QMB_SEL_RMSK 0x1 +#define HWIO_IPA_SNIFFER_QMB_SEL_ATTR 0x3 +#define HWIO_IPA_SNIFFER_QMB_SEL_IN \ + in_dword_masked(HWIO_IPA_SNIFFER_QMB_SEL_ADDR, HWIO_IPA_SNIFFER_QMB_SEL_RMSK) +#define HWIO_IPA_SNIFFER_QMB_SEL_INM(m) \ + in_dword_masked(HWIO_IPA_SNIFFER_QMB_SEL_ADDR, m) +#define HWIO_IPA_SNIFFER_QMB_SEL_OUT(v) \ + out_dword(HWIO_IPA_SNIFFER_QMB_SEL_ADDR,v) +#define HWIO_IPA_SNIFFER_QMB_SEL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_SNIFFER_QMB_SEL_ADDR,m,v,HWIO_IPA_SNIFFER_QMB_SEL_IN) +#define HWIO_IPA_SNIFFER_QMB_SEL_SNIF_QMB_SEL_BMSK 0x1 +#define HWIO_IPA_SNIFFER_QMB_SEL_SNIF_QMB_SEL_SHFT 0x0 + +#define HWIO_IPA_ULSO_CFG_IP_ID_MAX_VALUE_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000924 + 0x4 * (n)) +#define HWIO_IPA_ULSO_CFG_IP_ID_MAX_VALUE_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000924 + 0x4 * (n)) +#define HWIO_IPA_ULSO_CFG_IP_ID_MAX_VALUE_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000924 + 0x4 * (n)) +#define HWIO_IPA_ULSO_CFG_IP_ID_MAX_VALUE_n_RMSK 0xffff +#define HWIO_IPA_ULSO_CFG_IP_ID_MAX_VALUE_n_MAXn 2 +#define HWIO_IPA_ULSO_CFG_IP_ID_MAX_VALUE_n_ATTR 0x3 +#define HWIO_IPA_ULSO_CFG_IP_ID_MAX_VALUE_n_INI(n) \ + in_dword_masked(HWIO_IPA_ULSO_CFG_IP_ID_MAX_VALUE_n_ADDR(n), HWIO_IPA_ULSO_CFG_IP_ID_MAX_VALUE_n_RMSK) +#define HWIO_IPA_ULSO_CFG_IP_ID_MAX_VALUE_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ULSO_CFG_IP_ID_MAX_VALUE_n_ADDR(n), mask) +#define HWIO_IPA_ULSO_CFG_IP_ID_MAX_VALUE_n_OUTI(n,val) \ + out_dword(HWIO_IPA_ULSO_CFG_IP_ID_MAX_VALUE_n_ADDR(n),val) +#define HWIO_IPA_ULSO_CFG_IP_ID_MAX_VALUE_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_ULSO_CFG_IP_ID_MAX_VALUE_n_ADDR(n),mask,val,HWIO_IPA_ULSO_CFG_IP_ID_MAX_VALUE_n_INI(n)) +#define HWIO_IPA_ULSO_CFG_IP_ID_MAX_VALUE_n_IP_ID_MAX_VALUE_BMSK 0xffff +#define HWIO_IPA_ULSO_CFG_IP_ID_MAX_VALUE_n_IP_ID_MAX_VALUE_SHFT 0x0 + +#define HWIO_IPA_ULSO_CFG_IP_ID_MIN_VALUE_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000934 + 0x4 * (n)) +#define HWIO_IPA_ULSO_CFG_IP_ID_MIN_VALUE_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000934 + 0x4 * (n)) +#define HWIO_IPA_ULSO_CFG_IP_ID_MIN_VALUE_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000934 + 0x4 * (n)) +#define HWIO_IPA_ULSO_CFG_IP_ID_MIN_VALUE_n_RMSK 0xffff +#define HWIO_IPA_ULSO_CFG_IP_ID_MIN_VALUE_n_MAXn 2 +#define HWIO_IPA_ULSO_CFG_IP_ID_MIN_VALUE_n_ATTR 0x3 +#define HWIO_IPA_ULSO_CFG_IP_ID_MIN_VALUE_n_INI(n) \ + in_dword_masked(HWIO_IPA_ULSO_CFG_IP_ID_MIN_VALUE_n_ADDR(n), HWIO_IPA_ULSO_CFG_IP_ID_MIN_VALUE_n_RMSK) +#define HWIO_IPA_ULSO_CFG_IP_ID_MIN_VALUE_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ULSO_CFG_IP_ID_MIN_VALUE_n_ADDR(n), mask) +#define HWIO_IPA_ULSO_CFG_IP_ID_MIN_VALUE_n_OUTI(n,val) \ + out_dword(HWIO_IPA_ULSO_CFG_IP_ID_MIN_VALUE_n_ADDR(n),val) +#define HWIO_IPA_ULSO_CFG_IP_ID_MIN_VALUE_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_ULSO_CFG_IP_ID_MIN_VALUE_n_ADDR(n),mask,val,HWIO_IPA_ULSO_CFG_IP_ID_MIN_VALUE_n_INI(n)) +#define HWIO_IPA_ULSO_CFG_IP_ID_MIN_VALUE_n_IP_ID_MIN_VALUE_BMSK 0xffff +#define HWIO_IPA_ULSO_CFG_IP_ID_MIN_VALUE_n_IP_ID_MIN_VALUE_SHFT 0x0 + +#define HWIO_IPA_STATE_DFETCHER_MASK_4_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000944 + 0x4 * (n)) +#define HWIO_IPA_STATE_DFETCHER_MASK_4_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00000944 + 0x4 * (n)) +#define HWIO_IPA_STATE_DFETCHER_MASK_4_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00000944 + 0x4 * (n)) +#define HWIO_IPA_STATE_DFETCHER_MASK_4_n_RMSK 0xffffffff +#define HWIO_IPA_STATE_DFETCHER_MASK_4_n_MAXn 1 +#define HWIO_IPA_STATE_DFETCHER_MASK_4_n_ATTR 0x1 +#define HWIO_IPA_STATE_DFETCHER_MASK_4_n_INI(n) \ + in_dword_masked(HWIO_IPA_STATE_DFETCHER_MASK_4_n_ADDR(n), HWIO_IPA_STATE_DFETCHER_MASK_4_n_RMSK) +#define HWIO_IPA_STATE_DFETCHER_MASK_4_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_STATE_DFETCHER_MASK_4_n_ADDR(n), mask) +#define HWIO_IPA_STATE_DFETCHER_MASK_4_n_MASK_QUEUE_PROD_DPL_FIFO_FULL_BMSK 0xffffffff +#define HWIO_IPA_STATE_DFETCHER_MASK_4_n_MASK_QUEUE_PROD_DPL_FIFO_FULL_SHFT 0x0 + +#define HWIO_IPA_TSP_QM_EXTERNAL_BADDR_LSB_ADDR (IPA_CFG_REG_BASE + 0x00000a00) +#define HWIO_IPA_TSP_QM_EXTERNAL_BADDR_LSB_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000a00) +#define HWIO_IPA_TSP_QM_EXTERNAL_BADDR_LSB_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000a00) +#define HWIO_IPA_TSP_QM_EXTERNAL_BADDR_LSB_RMSK 0xffffffff +#define HWIO_IPA_TSP_QM_EXTERNAL_BADDR_LSB_ATTR 0x3 +#define HWIO_IPA_TSP_QM_EXTERNAL_BADDR_LSB_IN \ + in_dword_masked(HWIO_IPA_TSP_QM_EXTERNAL_BADDR_LSB_ADDR, HWIO_IPA_TSP_QM_EXTERNAL_BADDR_LSB_RMSK) +#define HWIO_IPA_TSP_QM_EXTERNAL_BADDR_LSB_INM(m) \ + in_dword_masked(HWIO_IPA_TSP_QM_EXTERNAL_BADDR_LSB_ADDR, m) +#define HWIO_IPA_TSP_QM_EXTERNAL_BADDR_LSB_OUT(v) \ + out_dword(HWIO_IPA_TSP_QM_EXTERNAL_BADDR_LSB_ADDR,v) +#define HWIO_IPA_TSP_QM_EXTERNAL_BADDR_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_TSP_QM_EXTERNAL_BADDR_LSB_ADDR,m,v,HWIO_IPA_TSP_QM_EXTERNAL_BADDR_LSB_IN) +#define HWIO_IPA_TSP_QM_EXTERNAL_BADDR_LSB_BADDR_LSBS_BMSK 0xffffffff +#define HWIO_IPA_TSP_QM_EXTERNAL_BADDR_LSB_BADDR_LSBS_SHFT 0x0 + +#define HWIO_IPA_TSP_QM_EXTERNAL_BADDR_MSB_ADDR (IPA_CFG_REG_BASE + 0x00000a04) +#define HWIO_IPA_TSP_QM_EXTERNAL_BADDR_MSB_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000a04) +#define HWIO_IPA_TSP_QM_EXTERNAL_BADDR_MSB_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000a04) +#define HWIO_IPA_TSP_QM_EXTERNAL_BADDR_MSB_RMSK 0xffffffff +#define HWIO_IPA_TSP_QM_EXTERNAL_BADDR_MSB_ATTR 0x3 +#define HWIO_IPA_TSP_QM_EXTERNAL_BADDR_MSB_IN \ + in_dword_masked(HWIO_IPA_TSP_QM_EXTERNAL_BADDR_MSB_ADDR, HWIO_IPA_TSP_QM_EXTERNAL_BADDR_MSB_RMSK) +#define HWIO_IPA_TSP_QM_EXTERNAL_BADDR_MSB_INM(m) \ + in_dword_masked(HWIO_IPA_TSP_QM_EXTERNAL_BADDR_MSB_ADDR, m) +#define HWIO_IPA_TSP_QM_EXTERNAL_BADDR_MSB_OUT(v) \ + out_dword(HWIO_IPA_TSP_QM_EXTERNAL_BADDR_MSB_ADDR,v) +#define HWIO_IPA_TSP_QM_EXTERNAL_BADDR_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_TSP_QM_EXTERNAL_BADDR_MSB_ADDR,m,v,HWIO_IPA_TSP_QM_EXTERNAL_BADDR_MSB_IN) +#define HWIO_IPA_TSP_QM_EXTERNAL_BADDR_MSB_BADDR_MSBS_BMSK 0xffffffff +#define HWIO_IPA_TSP_QM_EXTERNAL_BADDR_MSB_BADDR_MSBS_SHFT 0x0 + +#define HWIO_IPA_TSP_QM_EXTERNAL_SIZE_ADDR (IPA_CFG_REG_BASE + 0x00000a08) +#define HWIO_IPA_TSP_QM_EXTERNAL_SIZE_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000a08) +#define HWIO_IPA_TSP_QM_EXTERNAL_SIZE_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000a08) +#define HWIO_IPA_TSP_QM_EXTERNAL_SIZE_RMSK 0xfff +#define HWIO_IPA_TSP_QM_EXTERNAL_SIZE_ATTR 0x3 +#define HWIO_IPA_TSP_QM_EXTERNAL_SIZE_IN \ + in_dword_masked(HWIO_IPA_TSP_QM_EXTERNAL_SIZE_ADDR, HWIO_IPA_TSP_QM_EXTERNAL_SIZE_RMSK) +#define HWIO_IPA_TSP_QM_EXTERNAL_SIZE_INM(m) \ + in_dword_masked(HWIO_IPA_TSP_QM_EXTERNAL_SIZE_ADDR, m) +#define HWIO_IPA_TSP_QM_EXTERNAL_SIZE_OUT(v) \ + out_dword(HWIO_IPA_TSP_QM_EXTERNAL_SIZE_ADDR,v) +#define HWIO_IPA_TSP_QM_EXTERNAL_SIZE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_TSP_QM_EXTERNAL_SIZE_ADDR,m,v,HWIO_IPA_TSP_QM_EXTERNAL_SIZE_IN) +#define HWIO_IPA_TSP_QM_EXTERNAL_SIZE_SIZE_IN_4KB_RESOLUTION_BMSK 0xfff +#define HWIO_IPA_TSP_QM_EXTERNAL_SIZE_SIZE_IN_4KB_RESOLUTION_SHFT 0x0 + +#define HWIO_IPA_TSP_INGRESS_POLICING_CFG_ADDR (IPA_CFG_REG_BASE + 0x00000a0c) +#define HWIO_IPA_TSP_INGRESS_POLICING_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000a0c) +#define HWIO_IPA_TSP_INGRESS_POLICING_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000a0c) +#define HWIO_IPA_TSP_INGRESS_POLICING_CFG_RMSK 0xffffffff +#define HWIO_IPA_TSP_INGRESS_POLICING_CFG_ATTR 0x3 +#define HWIO_IPA_TSP_INGRESS_POLICING_CFG_IN \ + in_dword_masked(HWIO_IPA_TSP_INGRESS_POLICING_CFG_ADDR, HWIO_IPA_TSP_INGRESS_POLICING_CFG_RMSK) +#define HWIO_IPA_TSP_INGRESS_POLICING_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_TSP_INGRESS_POLICING_CFG_ADDR, m) +#define HWIO_IPA_TSP_INGRESS_POLICING_CFG_OUT(v) \ + out_dword(HWIO_IPA_TSP_INGRESS_POLICING_CFG_ADDR,v) +#define HWIO_IPA_TSP_INGRESS_POLICING_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_TSP_INGRESS_POLICING_CFG_ADDR,m,v,HWIO_IPA_TSP_INGRESS_POLICING_CFG_IN) +#define HWIO_IPA_TSP_INGRESS_POLICING_CFG_INCLUDE_L2_LEN_PER_TRAFFIC_CLASS_BITMAP_BMSK 0xffffffff +#define HWIO_IPA_TSP_INGRESS_POLICING_CFG_INCLUDE_L2_LEN_PER_TRAFFIC_CLASS_BITMAP_SHFT 0x0 + +#define HWIO_IPA_TSP_EGRESS_POLICING_CFG_ADDR (IPA_CFG_REG_BASE + 0x00000a10) +#define HWIO_IPA_TSP_EGRESS_POLICING_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000a10) +#define HWIO_IPA_TSP_EGRESS_POLICING_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000a10) +#define HWIO_IPA_TSP_EGRESS_POLICING_CFG_RMSK 0xffffffff +#define HWIO_IPA_TSP_EGRESS_POLICING_CFG_ATTR 0x3 +#define HWIO_IPA_TSP_EGRESS_POLICING_CFG_IN \ + in_dword_masked(HWIO_IPA_TSP_EGRESS_POLICING_CFG_ADDR, HWIO_IPA_TSP_EGRESS_POLICING_CFG_RMSK) +#define HWIO_IPA_TSP_EGRESS_POLICING_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_TSP_EGRESS_POLICING_CFG_ADDR, m) +#define HWIO_IPA_TSP_EGRESS_POLICING_CFG_OUT(v) \ + out_dword(HWIO_IPA_TSP_EGRESS_POLICING_CFG_ADDR,v) +#define HWIO_IPA_TSP_EGRESS_POLICING_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_TSP_EGRESS_POLICING_CFG_ADDR,m,v,HWIO_IPA_TSP_EGRESS_POLICING_CFG_IN) +#define HWIO_IPA_TSP_EGRESS_POLICING_CFG_DISABLE_GUARANTEED_RATE_PER_TRAFFIC_CLASS_BITMAP_BMSK 0xffffffff +#define HWIO_IPA_TSP_EGRESS_POLICING_CFG_DISABLE_GUARANTEED_RATE_PER_TRAFFIC_CLASS_BITMAP_SHFT 0x0 + +#define HWIO_IPA_STAT_TSP_DROP_BASE_ADDR (IPA_CFG_REG_BASE + 0x00000a14) +#define HWIO_IPA_STAT_TSP_DROP_BASE_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000a14) +#define HWIO_IPA_STAT_TSP_DROP_BASE_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000a14) +#define HWIO_IPA_STAT_TSP_DROP_BASE_RMSK 0x7ffff +#define HWIO_IPA_STAT_TSP_DROP_BASE_ATTR 0x3 +#define HWIO_IPA_STAT_TSP_DROP_BASE_IN \ + in_dword_masked(HWIO_IPA_STAT_TSP_DROP_BASE_ADDR, HWIO_IPA_STAT_TSP_DROP_BASE_RMSK) +#define HWIO_IPA_STAT_TSP_DROP_BASE_INM(m) \ + in_dword_masked(HWIO_IPA_STAT_TSP_DROP_BASE_ADDR, m) +#define HWIO_IPA_STAT_TSP_DROP_BASE_OUT(v) \ + out_dword(HWIO_IPA_STAT_TSP_DROP_BASE_ADDR,v) +#define HWIO_IPA_STAT_TSP_DROP_BASE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_STAT_TSP_DROP_BASE_ADDR,m,v,HWIO_IPA_STAT_TSP_DROP_BASE_IN) +#define HWIO_IPA_STAT_TSP_DROP_BASE_BASE_ADDR_BMSK 0x7fff8 +#define HWIO_IPA_STAT_TSP_DROP_BASE_BASE_ADDR_SHFT 0x3 +#define HWIO_IPA_STAT_TSP_DROP_BASE_BASE_ADDR_OFFSET_BMSK 0x7 +#define HWIO_IPA_STAT_TSP_DROP_BASE_BASE_ADDR_OFFSET_SHFT 0x0 + +#define HWIO_IPA_STATE_QMNGR_QUEUE_NONEMPTY_ADDR (IPA_CFG_REG_BASE + 0x00000a18) +#define HWIO_IPA_STATE_QMNGR_QUEUE_NONEMPTY_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000a18) +#define HWIO_IPA_STATE_QMNGR_QUEUE_NONEMPTY_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000a18) +#define HWIO_IPA_STATE_QMNGR_QUEUE_NONEMPTY_RMSK 0xffffffff +#define HWIO_IPA_STATE_QMNGR_QUEUE_NONEMPTY_ATTR 0x1 +#define HWIO_IPA_STATE_QMNGR_QUEUE_NONEMPTY_IN \ + in_dword_masked(HWIO_IPA_STATE_QMNGR_QUEUE_NONEMPTY_ADDR, HWIO_IPA_STATE_QMNGR_QUEUE_NONEMPTY_RMSK) +#define HWIO_IPA_STATE_QMNGR_QUEUE_NONEMPTY_INM(m) \ + in_dword_masked(HWIO_IPA_STATE_QMNGR_QUEUE_NONEMPTY_ADDR, m) +#define HWIO_IPA_STATE_QMNGR_QUEUE_NONEMPTY_QUEUE_NONEMPTY_BITMAP_BMSK 0xffffffff +#define HWIO_IPA_STATE_QMNGR_QUEUE_NONEMPTY_QUEUE_NONEMPTY_BITMAP_SHFT 0x0 + +#define HWIO_IPA_STATE_PROD_DPL_FIFO_ADDR (IPA_CFG_REG_BASE + 0x00000a1c) +#define HWIO_IPA_STATE_PROD_DPL_FIFO_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000a1c) +#define HWIO_IPA_STATE_PROD_DPL_FIFO_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000a1c) +#define HWIO_IPA_STATE_PROD_DPL_FIFO_RMSK 0x7 +#define HWIO_IPA_STATE_PROD_DPL_FIFO_ATTR 0x1 +#define HWIO_IPA_STATE_PROD_DPL_FIFO_IN \ + in_dword_masked(HWIO_IPA_STATE_PROD_DPL_FIFO_ADDR, HWIO_IPA_STATE_PROD_DPL_FIFO_RMSK) +#define HWIO_IPA_STATE_PROD_DPL_FIFO_INM(m) \ + in_dword_masked(HWIO_IPA_STATE_PROD_DPL_FIFO_ADDR, m) +#define HWIO_IPA_STATE_PROD_DPL_FIFO_POP_FSM_STATE_BMSK 0x7 +#define HWIO_IPA_STATE_PROD_DPL_FIFO_POP_FSM_STATE_SHFT 0x0 + +#define HWIO_IPA_ENDP_INIT_CTRL_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00001000 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_CTRL_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00001000 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_CTRL_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00001000 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_CTRL_n_RMSK 0x2 +#define HWIO_IPA_ENDP_INIT_CTRL_n_MAXn 35 +#define HWIO_IPA_ENDP_INIT_CTRL_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_CTRL_n_INI(n) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_CTRL_n_ADDR(n), HWIO_IPA_ENDP_INIT_CTRL_n_RMSK) +#define HWIO_IPA_ENDP_INIT_CTRL_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_CTRL_n_ADDR(n), mask) +#define HWIO_IPA_ENDP_INIT_CTRL_n_OUTI(n,val) \ + out_dword(HWIO_IPA_ENDP_INIT_CTRL_n_ADDR(n),val) +#define HWIO_IPA_ENDP_INIT_CTRL_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_ENDP_INIT_CTRL_n_ADDR(n),mask,val,HWIO_IPA_ENDP_INIT_CTRL_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_CTRL_n_ENDP_DELAY_BMSK 0x2 +#define HWIO_IPA_ENDP_INIT_CTRL_n_ENDP_DELAY_SHFT 0x1 + +#define HWIO_IPA_ENDP_INIT_CTRL_SCND_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00001004 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_CTRL_SCND_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00001004 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_CTRL_SCND_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00001004 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_CTRL_SCND_n_RMSK 0x2 +#define HWIO_IPA_ENDP_INIT_CTRL_SCND_n_MAXn 35 +#define HWIO_IPA_ENDP_INIT_CTRL_SCND_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_CTRL_SCND_n_INI(n) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_CTRL_SCND_n_ADDR(n), HWIO_IPA_ENDP_INIT_CTRL_SCND_n_RMSK) +#define HWIO_IPA_ENDP_INIT_CTRL_SCND_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_CTRL_SCND_n_ADDR(n), mask) +#define HWIO_IPA_ENDP_INIT_CTRL_SCND_n_OUTI(n,val) \ + out_dword(HWIO_IPA_ENDP_INIT_CTRL_SCND_n_ADDR(n),val) +#define HWIO_IPA_ENDP_INIT_CTRL_SCND_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_ENDP_INIT_CTRL_SCND_n_ADDR(n),mask,val,HWIO_IPA_ENDP_INIT_CTRL_SCND_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_CTRL_SCND_n_ENDP_DELAY_BMSK 0x2 +#define HWIO_IPA_ENDP_INIT_CTRL_SCND_n_ENDP_DELAY_SHFT 0x1 + +#define HWIO_IPA_ENDP_INIT_CFG_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00001008 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_CFG_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00001008 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_CFG_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00001008 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_CFG_n_RMSK 0x37f +#define HWIO_IPA_ENDP_INIT_CFG_n_MAXn 35 +#define HWIO_IPA_ENDP_INIT_CFG_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_CFG_n_INI(n) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_CFG_n_ADDR(n), HWIO_IPA_ENDP_INIT_CFG_n_RMSK) +#define HWIO_IPA_ENDP_INIT_CFG_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_CFG_n_ADDR(n), mask) +#define HWIO_IPA_ENDP_INIT_CFG_n_OUTI(n,val) \ + out_dword(HWIO_IPA_ENDP_INIT_CFG_n_ADDR(n),val) +#define HWIO_IPA_ENDP_INIT_CFG_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_ENDP_INIT_CFG_n_ADDR(n),mask,val,HWIO_IPA_ENDP_INIT_CFG_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_CFG_n_PIPE_REPLICATE_EN_BMSK 0x200 +#define HWIO_IPA_ENDP_INIT_CFG_n_PIPE_REPLICATE_EN_SHFT 0x9 +#define HWIO_IPA_ENDP_INIT_CFG_n_GEN_QMB_MASTER_SEL_BMSK 0x100 +#define HWIO_IPA_ENDP_INIT_CFG_n_GEN_QMB_MASTER_SEL_SHFT 0x8 +#define HWIO_IPA_ENDP_INIT_CFG_n_CS_METADATA_HDR_OFFSET_BMSK 0x78 +#define HWIO_IPA_ENDP_INIT_CFG_n_CS_METADATA_HDR_OFFSET_SHFT 0x3 +#define HWIO_IPA_ENDP_INIT_CFG_n_CS_OFFLOAD_EN_BMSK 0x6 +#define HWIO_IPA_ENDP_INIT_CFG_n_CS_OFFLOAD_EN_SHFT 0x1 +#define HWIO_IPA_ENDP_INIT_CFG_n_FRAG_OFFLOAD_EN_BMSK 0x1 +#define HWIO_IPA_ENDP_INIT_CFG_n_FRAG_OFFLOAD_EN_SHFT 0x0 + +#define HWIO_IPA_ENDP_INIT_NAT_n_ADDR(n) (IPA_CFG_REG_BASE + 0x0000100c + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_NAT_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x0000100c + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_NAT_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x0000100c + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_NAT_n_RMSK 0x3 +#define HWIO_IPA_ENDP_INIT_NAT_n_MAXn 15 +#define HWIO_IPA_ENDP_INIT_NAT_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_NAT_n_INI(n) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_NAT_n_ADDR(n), HWIO_IPA_ENDP_INIT_NAT_n_RMSK) +#define HWIO_IPA_ENDP_INIT_NAT_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_NAT_n_ADDR(n), mask) +#define HWIO_IPA_ENDP_INIT_NAT_n_OUTI(n,val) \ + out_dword(HWIO_IPA_ENDP_INIT_NAT_n_ADDR(n),val) +#define HWIO_IPA_ENDP_INIT_NAT_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_ENDP_INIT_NAT_n_ADDR(n),mask,val,HWIO_IPA_ENDP_INIT_NAT_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_NAT_n_NAT_EN_BMSK 0x3 +#define HWIO_IPA_ENDP_INIT_NAT_n_NAT_EN_SHFT 0x0 + +#define HWIO_IPA_ENDP_INIT_HDR_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00001010 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_HDR_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00001010 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_HDR_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00001010 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_HDR_n_RMSK 0xfbffffff +#define HWIO_IPA_ENDP_INIT_HDR_n_MAXn 35 +#define HWIO_IPA_ENDP_INIT_HDR_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_HDR_n_INI(n) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_HDR_n_ADDR(n), HWIO_IPA_ENDP_INIT_HDR_n_RMSK) +#define HWIO_IPA_ENDP_INIT_HDR_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_HDR_n_ADDR(n), mask) +#define HWIO_IPA_ENDP_INIT_HDR_n_OUTI(n,val) \ + out_dword(HWIO_IPA_ENDP_INIT_HDR_n_ADDR(n),val) +#define HWIO_IPA_ENDP_INIT_HDR_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_ENDP_INIT_HDR_n_ADDR(n),mask,val,HWIO_IPA_ENDP_INIT_HDR_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_MSB_BMSK 0xc0000000 +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_MSB_SHFT 0x1e +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_LEN_MSB_BMSK 0x30000000 +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_LEN_MSB_SHFT 0x1c +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_LEN_INC_DEAGG_HDR_BMSK 0x8000000 +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_LEN_INC_DEAGG_HDR_SHFT 0x1b +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_OFST_PKT_SIZE_BMSK 0x3f00000 +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_OFST_PKT_SIZE_SHFT 0x14 +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_OFST_PKT_SIZE_VALID_BMSK 0x80000 +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_OFST_PKT_SIZE_VALID_SHFT 0x13 +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_ADDITIONAL_CONST_LEN_BMSK 0x7e000 +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_ADDITIONAL_CONST_LEN_SHFT 0xd +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_BMSK 0x1f80 +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_SHFT 0x7 +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_VALID_BMSK 0x40 +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_VALID_SHFT 0x6 +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_LEN_BMSK 0x3f +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_LEN_SHFT 0x0 + +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00001014 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00001014 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00001014 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_RMSK 0xff7f3fff +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_MAXn 35 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_INI(n) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_HDR_EXT_n_ADDR(n), HWIO_IPA_ENDP_INIT_HDR_EXT_n_RMSK) +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_HDR_EXT_n_ADDR(n), mask) +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_OUTI(n,val) \ + out_dword(HWIO_IPA_ENDP_INIT_HDR_EXT_n_ADDR(n),val) +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_ENDP_INIT_HDR_EXT_n_ADDR(n),mask,val,HWIO_IPA_ENDP_INIT_HDR_EXT_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_BYTES_TO_REMOVE_BMSK 0xff000000 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_BYTES_TO_REMOVE_SHFT 0x18 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_BYTES_TO_REMOVE_VALID_BMSK 0x400000 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_BYTES_TO_REMOVE_VALID_SHFT 0x16 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_ADDITIONAL_CONST_LEN_MSB_BMSK 0x300000 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_ADDITIONAL_CONST_LEN_MSB_SHFT 0x14 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_OFST_PKT_SIZE_MSB_BMSK 0xc0000 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_OFST_PKT_SIZE_MSB_SHFT 0x12 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB_BMSK 0x30000 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB_SHFT 0x10 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_PAD_TO_ALIGNMENT_BMSK 0x3c00 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_PAD_TO_ALIGNMENT_SHFT 0xa +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_OFFSET_BMSK 0x3f0 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_OFFSET_SHFT 0x4 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_PAYLOAD_LEN_INC_PADDING_BMSK 0x8 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_PAYLOAD_LEN_INC_PADDING_SHFT 0x3 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_BMSK 0x4 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_SHFT 0x2 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_VALID_BMSK 0x2 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_VALID_SHFT 0x1 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_ENDIANESS_BMSK 0x1 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_ENDIANESS_SHFT 0x0 + +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00001018 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00001018 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00001018 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_RMSK 0xffffffff +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_MAXn 35 +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_INI(n) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_ADDR(n), HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_RMSK) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_ADDR(n), mask) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_OUTI(n,val) \ + out_dword(HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_ADDR(n),val) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_ADDR(n),mask,val,HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_METADATA_MASK_BMSK 0xffffffff +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_METADATA_MASK_SHFT 0x0 + +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_n_ADDR(n) (IPA_CFG_REG_BASE + 0x0000101c + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x0000101c + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x0000101c + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_n_RMSK 0xffffffff +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_n_MAXn 15 +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_n_INI(n) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_HDR_METADATA_n_ADDR(n), HWIO_IPA_ENDP_INIT_HDR_METADATA_n_RMSK) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_HDR_METADATA_n_ADDR(n), mask) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_n_OUTI(n,val) \ + out_dword(HWIO_IPA_ENDP_INIT_HDR_METADATA_n_ADDR(n),val) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_ENDP_INIT_HDR_METADATA_n_ADDR(n),mask,val,HWIO_IPA_ENDP_INIT_HDR_METADATA_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_n_METADATA_BMSK 0xffffffff +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_n_METADATA_SHFT 0x0 + +#define HWIO_IPA_ENDP_INIT_MODE_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00001020 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_MODE_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00001020 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_MODE_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00001020 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_MODE_n_RMSK 0x6fffffff +#define HWIO_IPA_ENDP_INIT_MODE_n_MAXn 15 +#define HWIO_IPA_ENDP_INIT_MODE_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_MODE_n_INI(n) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_MODE_n_ADDR(n), HWIO_IPA_ENDP_INIT_MODE_n_RMSK) +#define HWIO_IPA_ENDP_INIT_MODE_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_MODE_n_ADDR(n), mask) +#define HWIO_IPA_ENDP_INIT_MODE_n_OUTI(n,val) \ + out_dword(HWIO_IPA_ENDP_INIT_MODE_n_ADDR(n),val) +#define HWIO_IPA_ENDP_INIT_MODE_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_ENDP_INIT_MODE_n_ADDR(n),mask,val,HWIO_IPA_ENDP_INIT_MODE_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_MODE_n_DRBIP_ACL_ENABLE_BMSK 0x40000000 +#define HWIO_IPA_ENDP_INIT_MODE_n_DRBIP_ACL_ENABLE_SHFT 0x1e +#define HWIO_IPA_ENDP_INIT_MODE_n_PAD_EN_BMSK 0x20000000 +#define HWIO_IPA_ENDP_INIT_MODE_n_PAD_EN_SHFT 0x1d +#define HWIO_IPA_ENDP_INIT_MODE_n_BYTE_THRESHOLD_BMSK 0xffff000 +#define HWIO_IPA_ENDP_INIT_MODE_n_BYTE_THRESHOLD_SHFT 0xc +#define HWIO_IPA_ENDP_INIT_MODE_n_DEST_PIPE_INDEX_BMSK 0xff0 +#define HWIO_IPA_ENDP_INIT_MODE_n_DEST_PIPE_INDEX_SHFT 0x4 +#define HWIO_IPA_ENDP_INIT_MODE_n_BEARER_CNTX_ENABLE_BMSK 0x8 +#define HWIO_IPA_ENDP_INIT_MODE_n_BEARER_CNTX_ENABLE_SHFT 0x3 +#define HWIO_IPA_ENDP_INIT_MODE_n_MODE_BMSK 0x7 +#define HWIO_IPA_ENDP_INIT_MODE_n_MODE_SHFT 0x0 + +#define HWIO_IPA_ENDP_INIT_AGGR_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00001024 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_AGGR_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00001024 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_AGGR_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00001024 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_AGGR_n_RMSK 0x1dfff7ff +#define HWIO_IPA_ENDP_INIT_AGGR_n_MAXn 35 +#define HWIO_IPA_ENDP_INIT_AGGR_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_AGGR_n_INI(n) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_AGGR_n_ADDR(n), HWIO_IPA_ENDP_INIT_AGGR_n_RMSK) +#define HWIO_IPA_ENDP_INIT_AGGR_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_AGGR_n_ADDR(n), mask) +#define HWIO_IPA_ENDP_INIT_AGGR_n_OUTI(n,val) \ + out_dword(HWIO_IPA_ENDP_INIT_AGGR_n_ADDR(n),val) +#define HWIO_IPA_ENDP_INIT_AGGR_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_ENDP_INIT_AGGR_n_ADDR(n),mask,val,HWIO_IPA_ENDP_INIT_AGGR_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_COAL_L2_BMSK 0x10000000 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_COAL_L2_SHFT 0x1c +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_GRAN_SEL_BMSK 0x8000000 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_GRAN_SEL_SHFT 0x1b +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_HARD_BYTE_LIMIT_ENABLE_BMSK 0x4000000 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_HARD_BYTE_LIMIT_ENABLE_SHFT 0x1a +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_FORCE_CLOSE_BMSK 0x1000000 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_FORCE_CLOSE_SHFT 0x18 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_SW_EOF_ACTIVE_BMSK 0x800000 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_SW_EOF_ACTIVE_SHFT 0x17 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_PKT_LIMIT_BMSK 0x7e0000 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_PKT_LIMIT_SHFT 0x11 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_TIME_LIMIT_BMSK 0x1f000 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_TIME_LIMIT_SHFT 0xc +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_BYTE_LIMIT_BMSK 0x7e0 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_BYTE_LIMIT_SHFT 0x5 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_TYPE_BMSK 0x1c +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_TYPE_SHFT 0x2 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_EN_BMSK 0x3 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_EN_SHFT 0x0 + +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_ADDR(n) (IPA_CFG_REG_BASE + 0x0000102c + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x0000102c + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x0000102c + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_RMSK 0x1 +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_MAXn 35 +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_INI(n) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_ADDR(n), HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_RMSK) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_ADDR(n), mask) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_OUTI(n,val) \ + out_dword(HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_ADDR(n),val) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_ADDR(n),mask,val,HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_EN_BMSK 0x1 +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_EN_SHFT 0x0 + +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00001030 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00001030 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00001030 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_RMSK 0x31f +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_MAXn 35 +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_INI(n) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_ADDR(n), HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_RMSK) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_ADDR(n), mask) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_OUTI(n,val) \ + out_dword(HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_ADDR(n),val) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_ADDR(n),mask,val,HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_GRAN_SEL_BMSK 0x300 +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_GRAN_SEL_SHFT 0x8 +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_TIME_LIMIT_BMSK 0x1f +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_TIME_LIMIT_SHFT 0x0 + +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00001034 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00001034 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00001034 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_RMSK 0xffff7fff +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_MAXn 15 +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_INI(n) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_DEAGGR_n_ADDR(n), HWIO_IPA_ENDP_INIT_DEAGGR_n_RMSK) +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_DEAGGR_n_ADDR(n), mask) +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_OUTI(n,val) \ + out_dword(HWIO_IPA_ENDP_INIT_DEAGGR_n_ADDR(n),val) +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_ENDP_INIT_DEAGGR_n_ADDR(n),mask,val,HWIO_IPA_ENDP_INIT_DEAGGR_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_MAX_PACKET_LEN_BMSK 0xffff0000 +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_MAX_PACKET_LEN_SHFT 0x10 +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_IGNORE_MIN_PKT_ERR_BMSK 0x4000 +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_IGNORE_MIN_PKT_ERR_SHFT 0xe +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_PACKET_OFFSET_LOCATION_BMSK 0x3f00 +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_PACKET_OFFSET_LOCATION_SHFT 0x8 +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_PACKET_OFFSET_VALID_BMSK 0x80 +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_PACKET_OFFSET_VALID_SHFT 0x7 +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_SYSPIPE_ERR_DETECTION_BMSK 0x40 +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_SYSPIPE_ERR_DETECTION_SHFT 0x6 +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_DEAGGR_HDR_LEN_BMSK 0x3f +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_DEAGGR_HDR_LEN_SHFT 0x0 + +#define HWIO_IPA_ENDP_INIT_RSRC_GRP_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00001038 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_RSRC_GRP_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00001038 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_RSRC_GRP_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00001038 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_RSRC_GRP_n_RMSK 0x7 +#define HWIO_IPA_ENDP_INIT_RSRC_GRP_n_MAXn 35 +#define HWIO_IPA_ENDP_INIT_RSRC_GRP_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_RSRC_GRP_n_INI(n) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_RSRC_GRP_n_ADDR(n), HWIO_IPA_ENDP_INIT_RSRC_GRP_n_RMSK) +#define HWIO_IPA_ENDP_INIT_RSRC_GRP_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_RSRC_GRP_n_ADDR(n), mask) +#define HWIO_IPA_ENDP_INIT_RSRC_GRP_n_OUTI(n,val) \ + out_dword(HWIO_IPA_ENDP_INIT_RSRC_GRP_n_ADDR(n),val) +#define HWIO_IPA_ENDP_INIT_RSRC_GRP_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_ENDP_INIT_RSRC_GRP_n_ADDR(n),mask,val,HWIO_IPA_ENDP_INIT_RSRC_GRP_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_BMSK 0x7 +#define HWIO_IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_SHFT 0x0 + +#define HWIO_IPA_ENDP_INIT_SEQ_n_ADDR(n) (IPA_CFG_REG_BASE + 0x0000103c + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_SEQ_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x0000103c + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_SEQ_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x0000103c + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_SEQ_n_RMSK 0x1f1f +#define HWIO_IPA_ENDP_INIT_SEQ_n_MAXn 15 +#define HWIO_IPA_ENDP_INIT_SEQ_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_SEQ_n_INI(n) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_SEQ_n_ADDR(n), HWIO_IPA_ENDP_INIT_SEQ_n_RMSK) +#define HWIO_IPA_ENDP_INIT_SEQ_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_SEQ_n_ADDR(n), mask) +#define HWIO_IPA_ENDP_INIT_SEQ_n_OUTI(n,val) \ + out_dword(HWIO_IPA_ENDP_INIT_SEQ_n_ADDR(n),val) +#define HWIO_IPA_ENDP_INIT_SEQ_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_ENDP_INIT_SEQ_n_ADDR(n),mask,val,HWIO_IPA_ENDP_INIT_SEQ_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_SEQ_n_DPS_SEQ_TYPE_BMSK 0x1f00 +#define HWIO_IPA_ENDP_INIT_SEQ_n_DPS_SEQ_TYPE_SHFT 0x8 +#define HWIO_IPA_ENDP_INIT_SEQ_n_HPS_SEQ_TYPE_BMSK 0x1f +#define HWIO_IPA_ENDP_INIT_SEQ_n_HPS_SEQ_TYPE_SHFT 0x0 + +#define HWIO_IPA_ENDP_STATUS_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00001040 + 0x80 * (n)) +#define HWIO_IPA_ENDP_STATUS_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00001040 + 0x80 * (n)) +#define HWIO_IPA_ENDP_STATUS_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00001040 + 0x80 * (n)) +#define HWIO_IPA_ENDP_STATUS_n_RMSK 0x3ff +#define HWIO_IPA_ENDP_STATUS_n_MAXn 35 +#define HWIO_IPA_ENDP_STATUS_n_ATTR 0x3 +#define HWIO_IPA_ENDP_STATUS_n_INI(n) \ + in_dword_masked(HWIO_IPA_ENDP_STATUS_n_ADDR(n), HWIO_IPA_ENDP_STATUS_n_RMSK) +#define HWIO_IPA_ENDP_STATUS_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ENDP_STATUS_n_ADDR(n), mask) +#define HWIO_IPA_ENDP_STATUS_n_OUTI(n,val) \ + out_dword(HWIO_IPA_ENDP_STATUS_n_ADDR(n),val) +#define HWIO_IPA_ENDP_STATUS_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_ENDP_STATUS_n_ADDR(n),mask,val,HWIO_IPA_ENDP_STATUS_n_INI(n)) +#define HWIO_IPA_ENDP_STATUS_n_STATUS_PKT_SUPRESS_BMSK 0x200 +#define HWIO_IPA_ENDP_STATUS_n_STATUS_PKT_SUPRESS_SHFT 0x9 +#define HWIO_IPA_ENDP_STATUS_n_STATUS_ENDP_BMSK 0x1fe +#define HWIO_IPA_ENDP_STATUS_n_STATUS_ENDP_SHFT 0x1 +#define HWIO_IPA_ENDP_STATUS_n_STATUS_EN_BMSK 0x1 +#define HWIO_IPA_ENDP_STATUS_n_STATUS_EN_SHFT 0x0 + +#define HWIO_IPA_ENDP_SRC_ID_WRITE_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00001048 + 0x80 * (n)) +#define HWIO_IPA_ENDP_SRC_ID_WRITE_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00001048 + 0x80 * (n)) +#define HWIO_IPA_ENDP_SRC_ID_WRITE_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00001048 + 0x80 * (n)) +#define HWIO_IPA_ENDP_SRC_ID_WRITE_n_RMSK 0xff +#define HWIO_IPA_ENDP_SRC_ID_WRITE_n_MAXn 15 +#define HWIO_IPA_ENDP_SRC_ID_WRITE_n_ATTR 0x2 +#define HWIO_IPA_ENDP_SRC_ID_WRITE_n_OUTI(n,val) \ + out_dword(HWIO_IPA_ENDP_SRC_ID_WRITE_n_ADDR(n),val) +#define HWIO_IPA_ENDP_SRC_ID_WRITE_n_SRC_ID_WRITE_VALUE_BMSK 0xff +#define HWIO_IPA_ENDP_SRC_ID_WRITE_n_SRC_ID_WRITE_VALUE_SHFT 0x0 + +#define HWIO_IPA_ENDP_SRC_ID_READ_n_ADDR(n) (IPA_CFG_REG_BASE + 0x0000104c + 0x80 * (n)) +#define HWIO_IPA_ENDP_SRC_ID_READ_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x0000104c + 0x80 * (n)) +#define HWIO_IPA_ENDP_SRC_ID_READ_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x0000104c + 0x80 * (n)) +#define HWIO_IPA_ENDP_SRC_ID_READ_n_RMSK 0xff +#define HWIO_IPA_ENDP_SRC_ID_READ_n_MAXn 15 +#define HWIO_IPA_ENDP_SRC_ID_READ_n_ATTR 0x1 +#define HWIO_IPA_ENDP_SRC_ID_READ_n_INI(n) \ + in_dword_masked(HWIO_IPA_ENDP_SRC_ID_READ_n_ADDR(n), HWIO_IPA_ENDP_SRC_ID_READ_n_RMSK) +#define HWIO_IPA_ENDP_SRC_ID_READ_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ENDP_SRC_ID_READ_n_ADDR(n), mask) +#define HWIO_IPA_ENDP_SRC_ID_READ_n_SRC_ID_READ_VALUE_BMSK 0xff +#define HWIO_IPA_ENDP_SRC_ID_READ_n_SRC_ID_READ_VALUE_SHFT 0x0 + +#define HWIO_IPA_ENDP_INIT_CONN_TRACK_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00001050 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_CONN_TRACK_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00001050 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_CONN_TRACK_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00001050 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_CONN_TRACK_n_RMSK 0x1 +#define HWIO_IPA_ENDP_INIT_CONN_TRACK_n_MAXn 15 +#define HWIO_IPA_ENDP_INIT_CONN_TRACK_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_CONN_TRACK_n_INI(n) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_CONN_TRACK_n_ADDR(n), HWIO_IPA_ENDP_INIT_CONN_TRACK_n_RMSK) +#define HWIO_IPA_ENDP_INIT_CONN_TRACK_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_CONN_TRACK_n_ADDR(n), mask) +#define HWIO_IPA_ENDP_INIT_CONN_TRACK_n_OUTI(n,val) \ + out_dword(HWIO_IPA_ENDP_INIT_CONN_TRACK_n_ADDR(n),val) +#define HWIO_IPA_ENDP_INIT_CONN_TRACK_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_ENDP_INIT_CONN_TRACK_n_ADDR(n),mask,val,HWIO_IPA_ENDP_INIT_CONN_TRACK_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_CONN_TRACK_n_CONN_TRACK_EN_BMSK 0x1 +#define HWIO_IPA_ENDP_INIT_CONN_TRACK_n_CONN_TRACK_EN_SHFT 0x0 + +#define HWIO_IPA_ENDP_INIT_DRBIP_CFG_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00001054 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_DRBIP_CFG_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00001054 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_DRBIP_CFG_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00001054 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_DRBIP_CFG_n_RMSK 0x3f +#define HWIO_IPA_ENDP_INIT_DRBIP_CFG_n_MAXn 15 +#define HWIO_IPA_ENDP_INIT_DRBIP_CFG_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_DRBIP_CFG_n_INI(n) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_DRBIP_CFG_n_ADDR(n), HWIO_IPA_ENDP_INIT_DRBIP_CFG_n_RMSK) +#define HWIO_IPA_ENDP_INIT_DRBIP_CFG_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_DRBIP_CFG_n_ADDR(n), mask) +#define HWIO_IPA_ENDP_INIT_DRBIP_CFG_n_OUTI(n,val) \ + out_dword(HWIO_IPA_ENDP_INIT_DRBIP_CFG_n_ADDR(n),val) +#define HWIO_IPA_ENDP_INIT_DRBIP_CFG_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_ENDP_INIT_DRBIP_CFG_n_ADDR(n),mask,val,HWIO_IPA_ENDP_INIT_DRBIP_CFG_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_DRBIP_CFG_n_DATA_SECTORS_FOR_IMM_CMD_BMSK 0x3f +#define HWIO_IPA_ENDP_INIT_DRBIP_CFG_n_DATA_SECTORS_FOR_IMM_CMD_SHFT 0x0 + +#define HWIO_IPA_FILTER_CACHE_CFG_n_ADDR(n) (IPA_CFG_REG_BASE + 0x0000105c + 0x80 * (n)) +#define HWIO_IPA_FILTER_CACHE_CFG_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x0000105c + 0x80 * (n)) +#define HWIO_IPA_FILTER_CACHE_CFG_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x0000105c + 0x80 * (n)) +#define HWIO_IPA_FILTER_CACHE_CFG_n_RMSK 0x7f +#define HWIO_IPA_FILTER_CACHE_CFG_n_MAXn 15 +#define HWIO_IPA_FILTER_CACHE_CFG_n_ATTR 0x3 +#define HWIO_IPA_FILTER_CACHE_CFG_n_INI(n) \ + in_dword_masked(HWIO_IPA_FILTER_CACHE_CFG_n_ADDR(n), HWIO_IPA_FILTER_CACHE_CFG_n_RMSK) +#define HWIO_IPA_FILTER_CACHE_CFG_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_FILTER_CACHE_CFG_n_ADDR(n), mask) +#define HWIO_IPA_FILTER_CACHE_CFG_n_OUTI(n,val) \ + out_dword(HWIO_IPA_FILTER_CACHE_CFG_n_ADDR(n),val) +#define HWIO_IPA_FILTER_CACHE_CFG_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_FILTER_CACHE_CFG_n_ADDR(n),mask,val,HWIO_IPA_FILTER_CACHE_CFG_n_INI(n)) +#define HWIO_IPA_FILTER_CACHE_CFG_n_FILTER_CACHE_MSK_METADATA_BMSK 0x40 +#define HWIO_IPA_FILTER_CACHE_CFG_n_FILTER_CACHE_MSK_METADATA_SHFT 0x6 +#define HWIO_IPA_FILTER_CACHE_CFG_n_FILTER_CACHE_MSK_PROTOCOL_BMSK 0x20 +#define HWIO_IPA_FILTER_CACHE_CFG_n_FILTER_CACHE_MSK_PROTOCOL_SHFT 0x5 +#define HWIO_IPA_FILTER_CACHE_CFG_n_FILTER_CACHE_MSK_DST_PORT_BMSK 0x10 +#define HWIO_IPA_FILTER_CACHE_CFG_n_FILTER_CACHE_MSK_DST_PORT_SHFT 0x4 +#define HWIO_IPA_FILTER_CACHE_CFG_n_FILTER_CACHE_MSK_SRC_PORT_BMSK 0x8 +#define HWIO_IPA_FILTER_CACHE_CFG_n_FILTER_CACHE_MSK_SRC_PORT_SHFT 0x3 +#define HWIO_IPA_FILTER_CACHE_CFG_n_FILTER_CACHE_MSK_DST_IP_ADD_BMSK 0x4 +#define HWIO_IPA_FILTER_CACHE_CFG_n_FILTER_CACHE_MSK_DST_IP_ADD_SHFT 0x2 +#define HWIO_IPA_FILTER_CACHE_CFG_n_FILTER_CACHE_MSK_SRC_IP_ADD_BMSK 0x2 +#define HWIO_IPA_FILTER_CACHE_CFG_n_FILTER_CACHE_MSK_SRC_IP_ADD_SHFT 0x1 +#define HWIO_IPA_FILTER_CACHE_CFG_n_FILTER_CACHE_MSK_SRC_ID_BMSK 0x1 +#define HWIO_IPA_FILTER_CACHE_CFG_n_FILTER_CACHE_MSK_SRC_ID_SHFT 0x0 + +#define HWIO_IPA_ROUTER_CACHE_CFG_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00001060 + 0x80 * (n)) +#define HWIO_IPA_ROUTER_CACHE_CFG_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00001060 + 0x80 * (n)) +#define HWIO_IPA_ROUTER_CACHE_CFG_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00001060 + 0x80 * (n)) +#define HWIO_IPA_ROUTER_CACHE_CFG_n_RMSK 0x7f +#define HWIO_IPA_ROUTER_CACHE_CFG_n_MAXn 35 +#define HWIO_IPA_ROUTER_CACHE_CFG_n_ATTR 0x3 +#define HWIO_IPA_ROUTER_CACHE_CFG_n_INI(n) \ + in_dword_masked(HWIO_IPA_ROUTER_CACHE_CFG_n_ADDR(n), HWIO_IPA_ROUTER_CACHE_CFG_n_RMSK) +#define HWIO_IPA_ROUTER_CACHE_CFG_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ROUTER_CACHE_CFG_n_ADDR(n), mask) +#define HWIO_IPA_ROUTER_CACHE_CFG_n_OUTI(n,val) \ + out_dword(HWIO_IPA_ROUTER_CACHE_CFG_n_ADDR(n),val) +#define HWIO_IPA_ROUTER_CACHE_CFG_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_ROUTER_CACHE_CFG_n_ADDR(n),mask,val,HWIO_IPA_ROUTER_CACHE_CFG_n_INI(n)) +#define HWIO_IPA_ROUTER_CACHE_CFG_n_ROUTER_CACHE_MSK_METADATA_BMSK 0x40 +#define HWIO_IPA_ROUTER_CACHE_CFG_n_ROUTER_CACHE_MSK_METADATA_SHFT 0x6 +#define HWIO_IPA_ROUTER_CACHE_CFG_n_ROUTER_CACHE_MSK_PROTOCOL_BMSK 0x20 +#define HWIO_IPA_ROUTER_CACHE_CFG_n_ROUTER_CACHE_MSK_PROTOCOL_SHFT 0x5 +#define HWIO_IPA_ROUTER_CACHE_CFG_n_ROUTER_CACHE_MSK_DST_PORT_BMSK 0x10 +#define HWIO_IPA_ROUTER_CACHE_CFG_n_ROUTER_CACHE_MSK_DST_PORT_SHFT 0x4 +#define HWIO_IPA_ROUTER_CACHE_CFG_n_ROUTER_CACHE_MSK_SRC_PORT_BMSK 0x8 +#define HWIO_IPA_ROUTER_CACHE_CFG_n_ROUTER_CACHE_MSK_SRC_PORT_SHFT 0x3 +#define HWIO_IPA_ROUTER_CACHE_CFG_n_ROUTER_CACHE_MSK_DST_IP_ADD_BMSK 0x4 +#define HWIO_IPA_ROUTER_CACHE_CFG_n_ROUTER_CACHE_MSK_DST_IP_ADD_SHFT 0x2 +#define HWIO_IPA_ROUTER_CACHE_CFG_n_ROUTER_CACHE_MSK_SRC_IP_ADD_BMSK 0x2 +#define HWIO_IPA_ROUTER_CACHE_CFG_n_ROUTER_CACHE_MSK_SRC_IP_ADD_SHFT 0x1 +#define HWIO_IPA_ROUTER_CACHE_CFG_n_ROUTER_CACHE_MSK_SRC_ID_BMSK 0x1 +#define HWIO_IPA_ROUTER_CACHE_CFG_n_ROUTER_CACHE_MSK_SRC_ID_SHFT 0x0 + +#define HWIO_IPA_ENDP_YELLOW_RED_MARKER_CFG_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00001064 + 0x80 * (n)) +#define HWIO_IPA_ENDP_YELLOW_RED_MARKER_CFG_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00001064 + 0x80 * (n)) +#define HWIO_IPA_ENDP_YELLOW_RED_MARKER_CFG_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00001064 + 0x80 * (n)) +#define HWIO_IPA_ENDP_YELLOW_RED_MARKER_CFG_n_RMSK 0xfc00fc00 +#define HWIO_IPA_ENDP_YELLOW_RED_MARKER_CFG_n_MAXn 35 +#define HWIO_IPA_ENDP_YELLOW_RED_MARKER_CFG_n_ATTR 0x3 +#define HWIO_IPA_ENDP_YELLOW_RED_MARKER_CFG_n_INI(n) \ + in_dword_masked(HWIO_IPA_ENDP_YELLOW_RED_MARKER_CFG_n_ADDR(n), HWIO_IPA_ENDP_YELLOW_RED_MARKER_CFG_n_RMSK) +#define HWIO_IPA_ENDP_YELLOW_RED_MARKER_CFG_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ENDP_YELLOW_RED_MARKER_CFG_n_ADDR(n), mask) +#define HWIO_IPA_ENDP_YELLOW_RED_MARKER_CFG_n_OUTI(n,val) \ + out_dword(HWIO_IPA_ENDP_YELLOW_RED_MARKER_CFG_n_ADDR(n),val) +#define HWIO_IPA_ENDP_YELLOW_RED_MARKER_CFG_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_ENDP_YELLOW_RED_MARKER_CFG_n_ADDR(n),mask,val,HWIO_IPA_ENDP_YELLOW_RED_MARKER_CFG_n_INI(n)) +#define HWIO_IPA_ENDP_YELLOW_RED_MARKER_CFG_n_IPA_RED_MARKER_CFG_BMSK 0xfc000000 +#define HWIO_IPA_ENDP_YELLOW_RED_MARKER_CFG_n_IPA_RED_MARKER_CFG_SHFT 0x1a +#define HWIO_IPA_ENDP_YELLOW_RED_MARKER_CFG_n_IPA_YELLOW_MARKER_CFG_BMSK 0xfc00 +#define HWIO_IPA_ENDP_YELLOW_RED_MARKER_CFG_n_IPA_YELLOW_MARKER_CFG_SHFT 0xa + +#define HWIO_IPA_ENDP_INIT_CTRL_STATUS_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00001068 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_CTRL_STATUS_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00001068 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_CTRL_STATUS_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00001068 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_CTRL_STATUS_n_RMSK 0x3 +#define HWIO_IPA_ENDP_INIT_CTRL_STATUS_n_MAXn 35 +#define HWIO_IPA_ENDP_INIT_CTRL_STATUS_n_ATTR 0x1 +#define HWIO_IPA_ENDP_INIT_CTRL_STATUS_n_INI(n) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_CTRL_STATUS_n_ADDR(n), HWIO_IPA_ENDP_INIT_CTRL_STATUS_n_RMSK) +#define HWIO_IPA_ENDP_INIT_CTRL_STATUS_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_CTRL_STATUS_n_ADDR(n), mask) +#define HWIO_IPA_ENDP_INIT_CTRL_STATUS_n_ENDP_DELAY_STATUS_BMSK 0x2 +#define HWIO_IPA_ENDP_INIT_CTRL_STATUS_n_ENDP_DELAY_STATUS_SHFT 0x1 +#define HWIO_IPA_ENDP_INIT_CTRL_STATUS_n_ENDP_SUSPEND_STATUS_BMSK 0x1 +#define HWIO_IPA_ENDP_INIT_CTRL_STATUS_n_ENDP_SUSPEND_STATUS_SHFT 0x0 + +#define HWIO_IPA_ENDP_INIT_PROD_CFG_n_ADDR(n) (IPA_CFG_REG_BASE + 0x0000106c + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_PROD_CFG_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x0000106c + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_PROD_CFG_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x0000106c + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_PROD_CFG_n_RMSK 0xfffffff7 +#define HWIO_IPA_ENDP_INIT_PROD_CFG_n_MAXn 35 +#define HWIO_IPA_ENDP_INIT_PROD_CFG_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_PROD_CFG_n_INI(n) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_PROD_CFG_n_ADDR(n), HWIO_IPA_ENDP_INIT_PROD_CFG_n_RMSK) +#define HWIO_IPA_ENDP_INIT_PROD_CFG_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_PROD_CFG_n_ADDR(n), mask) +#define HWIO_IPA_ENDP_INIT_PROD_CFG_n_OUTI(n,val) \ + out_dword(HWIO_IPA_ENDP_INIT_PROD_CFG_n_ADDR(n),val) +#define HWIO_IPA_ENDP_INIT_PROD_CFG_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_ENDP_INIT_PROD_CFG_n_ADDR(n),mask,val,HWIO_IPA_ENDP_INIT_PROD_CFG_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_PROD_CFG_n_PROD_EGRESS_TC_HIGHEST_BMSK 0xff000000 +#define HWIO_IPA_ENDP_INIT_PROD_CFG_n_PROD_EGRESS_TC_HIGHEST_SHFT 0x18 +#define HWIO_IPA_ENDP_INIT_PROD_CFG_n_PROD_EGRESS_TC_LOWEST_BMSK 0xff0000 +#define HWIO_IPA_ENDP_INIT_PROD_CFG_n_PROD_EGRESS_TC_LOWEST_SHFT 0x10 +#define HWIO_IPA_ENDP_INIT_PROD_CFG_n_PROD_MAX_OUTPUT_SIZE_SIZE_BMSK 0xff00 +#define HWIO_IPA_ENDP_INIT_PROD_CFG_n_PROD_MAX_OUTPUT_SIZE_SIZE_SHFT 0x8 +#define HWIO_IPA_ENDP_INIT_PROD_CFG_n_TSP_PRODUCER_INDEX_BMSK 0xf0 +#define HWIO_IPA_ENDP_INIT_PROD_CFG_n_TSP_PRODUCER_INDEX_SHFT 0x4 +#define HWIO_IPA_ENDP_INIT_PROD_CFG_n_PROD_MAX_OUTPUT_SIZE_DROP_ENABLE_BMSK 0x4 +#define HWIO_IPA_ENDP_INIT_PROD_CFG_n_PROD_MAX_OUTPUT_SIZE_DROP_ENABLE_SHFT 0x2 +#define HWIO_IPA_ENDP_INIT_PROD_CFG_n_TSP_ENABLE_BMSK 0x2 +#define HWIO_IPA_ENDP_INIT_PROD_CFG_n_TSP_ENABLE_SHFT 0x1 +#define HWIO_IPA_ENDP_INIT_PROD_CFG_n_TX_SEL_BMSK 0x1 +#define HWIO_IPA_ENDP_INIT_PROD_CFG_n_TX_SEL_SHFT 0x0 + +#define HWIO_IPA_ENDP_INIT_ULSO_CFG_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00001070 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_ULSO_CFG_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00001070 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_ULSO_CFG_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00001070 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_ULSO_CFG_n_RMSK 0x3 +#define HWIO_IPA_ENDP_INIT_ULSO_CFG_n_MAXn 15 +#define HWIO_IPA_ENDP_INIT_ULSO_CFG_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_ULSO_CFG_n_INI(n) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_ULSO_CFG_n_ADDR(n), HWIO_IPA_ENDP_INIT_ULSO_CFG_n_RMSK) +#define HWIO_IPA_ENDP_INIT_ULSO_CFG_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_ULSO_CFG_n_ADDR(n), mask) +#define HWIO_IPA_ENDP_INIT_ULSO_CFG_n_OUTI(n,val) \ + out_dword(HWIO_IPA_ENDP_INIT_ULSO_CFG_n_ADDR(n),val) +#define HWIO_IPA_ENDP_INIT_ULSO_CFG_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_ENDP_INIT_ULSO_CFG_n_ADDR(n),mask,val,HWIO_IPA_ENDP_INIT_ULSO_CFG_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_ULSO_CFG_n_IPV4_ID_MIN_MAX_VAL_INDEX_BMSK 0x3 +#define HWIO_IPA_ENDP_INIT_ULSO_CFG_n_IPV4_ID_MIN_MAX_VAL_INDEX_SHFT 0x0 + +#define HWIO_IPA_ENDP_INIT_UCP_CFG_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00001074 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_UCP_CFG_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00001074 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_UCP_CFG_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00001074 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_UCP_CFG_n_RMSK 0x1ffff +#define HWIO_IPA_ENDP_INIT_UCP_CFG_n_MAXn 15 +#define HWIO_IPA_ENDP_INIT_UCP_CFG_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_UCP_CFG_n_INI(n) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_UCP_CFG_n_ADDR(n), HWIO_IPA_ENDP_INIT_UCP_CFG_n_RMSK) +#define HWIO_IPA_ENDP_INIT_UCP_CFG_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_UCP_CFG_n_ADDR(n), mask) +#define HWIO_IPA_ENDP_INIT_UCP_CFG_n_OUTI(n,val) \ + out_dword(HWIO_IPA_ENDP_INIT_UCP_CFG_n_ADDR(n),val) +#define HWIO_IPA_ENDP_INIT_UCP_CFG_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_ENDP_INIT_UCP_CFG_n_ADDR(n),mask,val,HWIO_IPA_ENDP_INIT_UCP_CFG_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_UCP_CFG_n_UCP_TRIGGER_EN_BMSK 0x10000 +#define HWIO_IPA_ENDP_INIT_UCP_CFG_n_UCP_TRIGGER_EN_SHFT 0x10 +#define HWIO_IPA_ENDP_INIT_UCP_CFG_n_UCP_COMMAND_ID_BMSK 0xffff +#define HWIO_IPA_ENDP_INIT_UCP_CFG_n_UCP_COMMAND_ID_SHFT 0x0 + +#define HWIO_IPA_ENDP_INIT_NAT_EXC_SUPPRESS_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00001078 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_NAT_EXC_SUPPRESS_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + 0x00001078 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_NAT_EXC_SUPPRESS_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + 0x00001078 + 0x80 * (n)) +#define HWIO_IPA_ENDP_INIT_NAT_EXC_SUPPRESS_n_RMSK 0x1 +#define HWIO_IPA_ENDP_INIT_NAT_EXC_SUPPRESS_n_MAXn 15 +#define HWIO_IPA_ENDP_INIT_NAT_EXC_SUPPRESS_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_NAT_EXC_SUPPRESS_n_INI(n) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_NAT_EXC_SUPPRESS_n_ADDR(n), HWIO_IPA_ENDP_INIT_NAT_EXC_SUPPRESS_n_RMSK) +#define HWIO_IPA_ENDP_INIT_NAT_EXC_SUPPRESS_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_ENDP_INIT_NAT_EXC_SUPPRESS_n_ADDR(n), mask) +#define HWIO_IPA_ENDP_INIT_NAT_EXC_SUPPRESS_n_OUTI(n,val) \ + out_dword(HWIO_IPA_ENDP_INIT_NAT_EXC_SUPPRESS_n_ADDR(n),val) +#define HWIO_IPA_ENDP_INIT_NAT_EXC_SUPPRESS_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_ENDP_INIT_NAT_EXC_SUPPRESS_n_ADDR(n),mask,val,HWIO_IPA_ENDP_INIT_NAT_EXC_SUPPRESS_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_NAT_EXC_SUPPRESS_n_NAT_EXC_SUPPRESS_BMSK 0x1 +#define HWIO_IPA_ENDP_INIT_NAT_EXC_SUPPRESS_n_NAT_EXC_SUPPRESS_SHFT 0x0 + +/*---------------------------------------------------------------------------- + * MODULE: IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40 + *--------------------------------------------------------------------------*/ + +#define IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE (IPA_0_IPA_WRAPPER_BASE + 0x00130000) +#define IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_PHYS (IPA_0_IPA_WRAPPER_BASE_PHYS + 0x00130000) +#define IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_OFFS 0x00130000 + +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR0_ADDR (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE + 0x00000000) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR0_PHYS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_PHYS + 0x00000000) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR0_OFFS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_OFFS + 0x00000000) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR0_RMSK 0x3ff707f5 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR0_ATTR 0x3 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR0_IN \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR0_ADDR, HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR0_RMSK) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR0_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR0_ADDR, m) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR0_OUT(v) \ + out_dword(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR0_ADDR,v) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR0_ADDR,m,v,HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR0_IN) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR0_NSCFG_BMSK 0x30000000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR0_NSCFG_SHFT 0x1c +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR0_WACFG_BMSK 0xc000000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR0_WACFG_SHFT 0x1a +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR0_RACFG_BMSK 0x3000000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR0_RACFG_SHFT 0x18 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR0_SHCFG_BMSK 0xc00000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR0_SHCFG_SHFT 0x16 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR0_SMCFCFG_BMSK 0x200000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR0_SMCFCFG_SHFT 0x15 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR0_MTCFG_BMSK 0x100000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR0_MTCFG_SHFT 0x14 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR0_MEMATTR_BMSK 0x70000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR0_MEMATTR_SHFT 0x10 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR0_USFCFG_BMSK 0x400 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR0_USFCFG_SHFT 0xa +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR0_GSE_BMSK 0x200 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR0_GSE_SHFT 0x9 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR0_STALLD_BMSK 0x100 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR0_STALLD_SHFT 0x8 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR0_TRANSIENTCFG_BMSK 0xc0 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR0_TRANSIENTCFG_SHFT 0x6 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR0_GCFGFIE_BMSK 0x20 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR0_GCFGFIE_SHFT 0x5 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR0_GCFGERE_BMSK 0x10 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR0_GCFGERE_SHFT 0x4 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR0_GFIE_BMSK 0x4 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR0_GFIE_SHFT 0x2 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR0_CLIENTPD_BMSK 0x1 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR0_CLIENTPD_SHFT 0x0 + +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR1_ADDR (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE + 0x00000004) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR1_PHYS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_PHYS + 0x00000004) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR1_OFFS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_OFFS + 0x00000004) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR1_RMSK 0x1003f00 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR1_ATTR 0x3 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR1_IN \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR1_ADDR, HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR1_RMSK) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR1_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR1_ADDR, m) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR1_OUT(v) \ + out_dword(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR1_ADDR,v) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR1_ADDR,m,v,HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR1_IN) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR1_GASRAE_BMSK 0x1000000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR1_GASRAE_SHFT 0x18 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR1_NSNUMSMRGO_BMSK 0x3f00 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR1_NSNUMSMRGO_SHFT 0x8 + +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR2_ADDR (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE + 0x00000008) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR2_PHYS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_PHYS + 0x00000008) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR2_OFFS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_OFFS + 0x00000008) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR2_RMSK 0x1f +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR2_ATTR 0x3 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR2_IN \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR2_ADDR, HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR2_RMSK) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR2_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR2_ADDR, m) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR2_OUT(v) \ + out_dword(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR2_ADDR,v) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR2_ADDR,m,v,HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR2_IN) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR2_BPVMID_BMSK 0x1f +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SCR2_BPVMID_SHFT 0x0 + +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SACR_ADDR (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE + 0x00000010) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SACR_PHYS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_PHYS + 0x00000010) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SACR_OFFS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_OFFS + 0x00000010) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SACR_RMSK 0x70000013 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SACR_ATTR 0x3 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SACR_IN \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SACR_ADDR, HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SACR_RMSK) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SACR_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SACR_ADDR, m) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SACR_OUT(v) \ + out_dword(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SACR_ADDR,v) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SACR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SACR_ADDR,m,v,HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SACR_IN) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SACR_BPRCNSH_BMSK 0x40000000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SACR_BPRCNSH_SHFT 0x1e +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SACR_BPRCISH_BMSK 0x20000000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SACR_BPRCISH_SHFT 0x1d +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SACR_BPRCOSH_BMSK 0x10000000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SACR_BPRCOSH_SHFT 0x1c +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SACR_BPREQPRIORITYCFG_BMSK 0x10 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SACR_BPREQPRIORITYCFG_SHFT 0x4 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SACR_BPREQPRIORITY_BMSK 0x3 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SACR_BPREQPRIORITY_SHFT 0x0 + +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR0_ADDR (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE + 0x00000020) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR0_PHYS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_PHYS + 0x00000020) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR0_OFFS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_OFFS + 0x00000020) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR0_RMSK 0x88001eff +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR0_ATTR 0x1 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR0_IN \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR0_ADDR, HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR0_RMSK) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR0_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR0_ADDR, m) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR0_SES_BMSK 0x80000000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR0_SES_SHFT 0x1f +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR0_SMS_BMSK 0x8000000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR0_SMS_SHFT 0x1b +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR0_NUMSIDB_BMSK 0x1e00 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR0_NUMSIDB_SHFT 0x9 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR0_NUMSMRG_BMSK 0xff +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR0_NUMSMRG_SHFT 0x0 + +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR1_ADDR (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE + 0x00000024) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR1_PHYS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_PHYS + 0x00000024) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR1_OFFS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_OFFS + 0x00000024) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR1_RMSK 0x9f00 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR1_ATTR 0x1 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR1_IN \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR1_ADDR, HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR1_RMSK) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR1_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR1_ADDR, m) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR1_SMCD_BMSK 0x8000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR1_SMCD_SHFT 0xf +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR1_SSDTP_BMSK 0x1000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR1_SSDTP_SHFT 0xc +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR1_NUMSSDNDX_BMSK 0xf00 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR1_NUMSSDNDX_SHFT 0x8 + +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR2_ADDR (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE + 0x00000028) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR2_PHYS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_PHYS + 0x00000028) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR2_OFFS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_OFFS + 0x00000028) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR2_RMSK 0xff +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR2_ATTR 0x1 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR2_IN \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR2_ADDR, HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR2_RMSK) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR2_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR2_ADDR, m) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR2_OAS_BMSK 0xf0 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR2_OAS_SHFT 0x4 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR2_IAS_BMSK 0xf +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR2_IAS_SHFT 0x0 + +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR4_ADDR (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE + 0x00000030) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR4_PHYS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_PHYS + 0x00000030) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR4_OFFS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_OFFS + 0x00000030) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR4_RMSK 0xffffffff +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR4_ATTR 0x1 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR4_IN \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR4_ADDR, HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR4_RMSK) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR4_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR4_ADDR, m) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR4_MAJOR_BMSK 0xf0000000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR4_MAJOR_SHFT 0x1c +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR4_MINOR_BMSK 0xfff0000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR4_MINOR_SHFT 0x10 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR4_STEP_BMSK 0xffff +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR4_STEP_SHFT 0x0 + +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR5_ADDR (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE + 0x00000034) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR5_PHYS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_PHYS + 0x00000034) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR5_OFFS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_OFFS + 0x00000034) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR5_RMSK 0xff03ff +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR5_ATTR 0x1 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR5_IN \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR5_ADDR, HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR5_RMSK) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR5_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR5_ADDR, m) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR5_NUMMSDRB_BMSK 0xff0000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR5_NUMMSDRB_SHFT 0x10 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR5_MSAE_BMSK 0x200 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR5_MSAE_SHFT 0x9 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR5_QRIBE_BMSK 0x100 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR5_QRIBE_SHFT 0x8 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR5_NVMID_BMSK 0xff +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR5_NVMID_SHFT 0x0 + +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR7_ADDR (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE + 0x0000003c) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR7_PHYS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_PHYS + 0x0000003c) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR7_OFFS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_OFFS + 0x0000003c) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR7_RMSK 0xff +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR7_ATTR 0x1 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR7_IN \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR7_ADDR, HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR7_RMSK) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR7_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR7_ADDR, m) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR7_MAJOR_BMSK 0xf0 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR7_MAJOR_SHFT 0x4 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR7_MINOR_BMSK 0xf +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SIDR7_MINOR_SHFT 0x0 + +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFAR0_ADDR (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE + 0x00000040) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFAR0_PHYS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_PHYS + 0x00000040) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFAR0_OFFS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_OFFS + 0x00000040) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFAR0_RMSK 0xffffffff +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFAR0_ATTR 0x1 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFAR0_IN \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFAR0_ADDR, HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFAR0_RMSK) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFAR0_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFAR0_ADDR, m) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFAR0_SGFEA0_BMSK 0xffffffff +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFAR0_SGFEA0_SHFT 0x0 + +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFAR1_ADDR (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE + 0x00000044) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFAR1_PHYS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_PHYS + 0x00000044) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFAR1_OFFS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_OFFS + 0x00000044) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFAR1_RMSK 0xff +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFAR1_ATTR 0x1 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFAR1_IN \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFAR1_ADDR, HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFAR1_RMSK) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFAR1_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFAR1_ADDR, m) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFAR1_SGFEA1_BMSK 0xff +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFAR1_SGFEA1_SHFT 0x0 + +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSR_ADDR (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE + 0x00000048) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSR_PHYS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_PHYS + 0x00000048) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSR_OFFS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_OFFS + 0x00000048) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSR_RMSK 0xc0000026 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSR_ATTR 0x3 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSR_IN \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSR_ADDR, HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSR_RMSK) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSR_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSR_ADDR, m) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSR_OUT(v) \ + out_dword(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSR_ADDR,v) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSR_ADDR,m,v,HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSR_IN) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSR_MULTI_CLIENT_BMSK 0x80000000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSR_MULTI_CLIENT_SHFT 0x1f +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSR_MULTI_CFG_BMSK 0x40000000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSR_MULTI_CFG_SHFT 0x1e +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSR_CAF_BMSK 0x20 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSR_CAF_SHFT 0x5 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSR_SMCF_BMSK 0x4 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSR_SMCF_SHFT 0x2 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSR_USF_BMSK 0x2 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSR_USF_SHFT 0x1 + +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSRRESTORE_ADDR (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE + 0x0000004c) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSRRESTORE_PHYS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_PHYS + 0x0000004c) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSRRESTORE_OFFS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_OFFS + 0x0000004c) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSRRESTORE_RMSK 0xc0000026 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSRRESTORE_ATTR 0x3 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSRRESTORE_IN \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSRRESTORE_ADDR, HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSRRESTORE_RMSK) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSRRESTORE_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSRRESTORE_ADDR, m) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSRRESTORE_OUT(v) \ + out_dword(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSRRESTORE_ADDR,v) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSRRESTORE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSRRESTORE_ADDR,m,v,HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSRRESTORE_IN) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSRRESTORE_MULTI_CLIENT_BMSK 0x80000000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSRRESTORE_MULTI_CLIENT_SHFT 0x1f +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSRRESTORE_MULTI_CFG_BMSK 0x40000000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSRRESTORE_MULTI_CFG_SHFT 0x1e +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSRRESTORE_CAF_BMSK 0x20 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSRRESTORE_CAF_SHFT 0x5 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSRRESTORE_SMCF_BMSK 0x4 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSRRESTORE_SMCF_SHFT 0x2 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSRRESTORE_USF_BMSK 0x2 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSRRESTORE_USF_SHFT 0x1 + +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSYNDR0_ADDR (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE + 0x00000050) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSYNDR0_PHYS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_PHYS + 0x00000050) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSYNDR0_OFFS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_OFFS + 0x00000050) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSYNDR0_RMSK 0x132 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSYNDR0_ATTR 0x1 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSYNDR0_IN \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSYNDR0_ADDR, HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSYNDR0_RMSK) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSYNDR0_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSYNDR0_ADDR, m) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSYNDR0_MSSSELFAUTH_BMSK 0x100 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSYNDR0_MSSSELFAUTH_SHFT 0x8 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSYNDR0_NSATTR_BMSK 0x20 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSYNDR0_NSATTR_SHFT 0x5 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSYNDR0_NSSTATE_BMSK 0x10 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSYNDR0_NSSTATE_SHFT 0x4 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSYNDR0_WNR_BMSK 0x2 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSYNDR0_WNR_SHFT 0x1 + +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSYNDR1_ADDR (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE + 0x00000054) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSYNDR1_PHYS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_PHYS + 0x00000054) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSYNDR1_OFFS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_OFFS + 0x00000054) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSYNDR1_RMSK 0x7fff00ff +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSYNDR1_ATTR 0x1 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSYNDR1_IN \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSYNDR1_ADDR, HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSYNDR1_RMSK) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSYNDR1_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSYNDR1_ADDR, m) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSYNDR1_MSDINDEX_BMSK 0x7f000000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSYNDR1_MSDINDEX_SHFT 0x18 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSYNDR1_SSDINDEX_BMSK 0xff0000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSYNDR1_SSDINDEX_SHFT 0x10 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSYNDR1_STREAMINDEX_BMSK 0xff +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSYNDR1_STREAMINDEX_SHFT 0x0 + +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSYNDR2_ADDR (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE + 0x00000058) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSYNDR2_PHYS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_PHYS + 0x00000058) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSYNDR2_OFFS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_OFFS + 0x00000058) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSYNDR2_RMSK 0x1f1fffff +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSYNDR2_ATTR 0x1 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSYNDR2_IN \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSYNDR2_ADDR, HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSYNDR2_RMSK) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSYNDR2_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSYNDR2_ADDR, m) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSYNDR2_ATID_BMSK 0x1f000000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSYNDR2_ATID_SHFT 0x18 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSYNDR2_AVMID_BMSK 0x1f0000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSYNDR2_AVMID_SHFT 0x10 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSYNDR2_ABID_BMSK 0xe000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSYNDR2_ABID_SHFT 0xd +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSYNDR2_APID_BMSK 0x1f00 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSYNDR2_APID_SHFT 0x8 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSYNDR2_AMID_BMSK 0xff +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SGFSYNDR2_AMID_SHFT 0x0 + +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_VMIDMTSCR0_ADDR (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE + 0x00000090) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_VMIDMTSCR0_PHYS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_PHYS + 0x00000090) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_VMIDMTSCR0_OFFS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_OFFS + 0x00000090) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_VMIDMTSCR0_RMSK 0x1 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_VMIDMTSCR0_ATTR 0x3 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_VMIDMTSCR0_IN \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_VMIDMTSCR0_ADDR, HWIO_IPA_0_IPA_VMIDMT_VMIDMT_VMIDMTSCR0_RMSK) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_VMIDMTSCR0_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_VMIDMTSCR0_ADDR, m) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_VMIDMTSCR0_OUT(v) \ + out_dword(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_VMIDMTSCR0_ADDR,v) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_VMIDMTSCR0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_VMIDMTSCR0_ADDR,m,v,HWIO_IPA_0_IPA_VMIDMT_VMIDMT_VMIDMTSCR0_IN) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_VMIDMTSCR0_CLKONOFFE_BMSK 0x1 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_VMIDMTSCR0_CLKONOFFE_SHFT 0x0 + +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_CR0_ADDR (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE + 0x00000000) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_CR0_PHYS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_PHYS + 0x00000000) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_CR0_OFFS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_OFFS + 0x00000000) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_CR0_RMSK 0xff70ff5 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_CR0_ATTR 0x3 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_CR0_IN \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_CR0_ADDR, HWIO_IPA_0_IPA_VMIDMT_VMIDMT_CR0_RMSK) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_CR0_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_CR0_ADDR, m) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_CR0_OUT(v) \ + out_dword(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_CR0_ADDR,v) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_CR0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_CR0_ADDR,m,v,HWIO_IPA_0_IPA_VMIDMT_VMIDMT_CR0_IN) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_CR0_WACFG_BMSK 0xc000000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_CR0_WACFG_SHFT 0x1a +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_CR0_RACFG_BMSK 0x3000000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_CR0_RACFG_SHFT 0x18 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_CR0_SHCFG_BMSK 0xc00000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_CR0_SHCFG_SHFT 0x16 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_CR0_SMCFCFG_BMSK 0x200000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_CR0_SMCFCFG_SHFT 0x15 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_CR0_MTCFG_BMSK 0x100000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_CR0_MTCFG_SHFT 0x14 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_CR0_MEMATTR_BMSK 0x70000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_CR0_MEMATTR_SHFT 0x10 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_CR0_VMIDPNE_BMSK 0x800 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_CR0_VMIDPNE_SHFT 0xb +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_CR0_USFCFG_BMSK 0x400 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_CR0_USFCFG_SHFT 0xa +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_CR0_GSE_BMSK 0x200 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_CR0_GSE_SHFT 0x9 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_CR0_STALLD_BMSK 0x100 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_CR0_STALLD_SHFT 0x8 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_CR0_TRANSIENTCFG_BMSK 0xc0 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_CR0_TRANSIENTCFG_SHFT 0x6 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_CR0_GCFGFIE_BMSK 0x20 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_CR0_GCFGFIE_SHFT 0x5 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_CR0_GCFGERE_BMSK 0x10 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_CR0_GCFGERE_SHFT 0x4 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_CR0_GFIE_BMSK 0x4 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_CR0_GFIE_SHFT 0x2 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_CR0_CLIENTPD_BMSK 0x1 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_CR0_CLIENTPD_SHFT 0x0 + +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_CR2_ADDR (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE + 0x00000008) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_CR2_PHYS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_PHYS + 0x00000008) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_CR2_OFFS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_OFFS + 0x00000008) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_CR2_RMSK 0x1f +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_CR2_ATTR 0x3 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_CR2_IN \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_CR2_ADDR, HWIO_IPA_0_IPA_VMIDMT_VMIDMT_CR2_RMSK) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_CR2_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_CR2_ADDR, m) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_CR2_OUT(v) \ + out_dword(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_CR2_ADDR,v) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_CR2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_CR2_ADDR,m,v,HWIO_IPA_0_IPA_VMIDMT_VMIDMT_CR2_IN) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_CR2_BPVMID_BMSK 0x1f +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_CR2_BPVMID_SHFT 0x0 + +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_ACR_ADDR (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE + 0x00000010) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_ACR_PHYS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_PHYS + 0x00000010) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_ACR_OFFS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_OFFS + 0x00000010) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_ACR_RMSK 0x70000013 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_ACR_ATTR 0x3 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_ACR_IN \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_ACR_ADDR, HWIO_IPA_0_IPA_VMIDMT_VMIDMT_ACR_RMSK) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_ACR_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_ACR_ADDR, m) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_ACR_OUT(v) \ + out_dword(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_ACR_ADDR,v) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_ACR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_ACR_ADDR,m,v,HWIO_IPA_0_IPA_VMIDMT_VMIDMT_ACR_IN) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_ACR_BPRCNSH_BMSK 0x40000000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_ACR_BPRCNSH_SHFT 0x1e +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_ACR_BPRCISH_BMSK 0x20000000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_ACR_BPRCISH_SHFT 0x1d +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_ACR_BPRCOSH_BMSK 0x10000000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_ACR_BPRCOSH_SHFT 0x1c +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_ACR_BPREQPRIORITYCFG_BMSK 0x10 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_ACR_BPREQPRIORITYCFG_SHFT 0x4 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_ACR_BPREQPRIORITY_BMSK 0x3 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_ACR_BPREQPRIORITY_SHFT 0x0 + +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR0_ADDR (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE + 0x00000020) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR0_PHYS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_PHYS + 0x00000020) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR0_OFFS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_OFFS + 0x00000020) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR0_RMSK 0x8001eff +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR0_ATTR 0x1 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR0_IN \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR0_ADDR, HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR0_RMSK) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR0_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR0_ADDR, m) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR0_SMS_BMSK 0x8000000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR0_SMS_SHFT 0x1b +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR0_NUMSIDB_BMSK 0x1e00 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR0_NUMSIDB_SHFT 0x9 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR0_NUMSMRG_BMSK 0xff +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR0_NUMSMRG_SHFT 0x0 + +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR1_ADDR (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE + 0x00000024) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR1_PHYS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_PHYS + 0x00000024) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR1_OFFS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_OFFS + 0x00000024) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR1_RMSK 0x9f00 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR1_ATTR 0x1 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR1_IN \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR1_ADDR, HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR1_RMSK) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR1_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR1_ADDR, m) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR1_SMCD_BMSK 0x8000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR1_SMCD_SHFT 0xf +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR1_SSDTP_BMSK 0x1000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR1_SSDTP_SHFT 0xc +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR1_NUMSSDNDX_BMSK 0xf00 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR1_NUMSSDNDX_SHFT 0x8 + +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR2_ADDR (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE + 0x00000028) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR2_PHYS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_PHYS + 0x00000028) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR2_OFFS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_OFFS + 0x00000028) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR2_RMSK 0xff +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR2_ATTR 0x1 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR2_IN \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR2_ADDR, HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR2_RMSK) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR2_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR2_ADDR, m) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR2_OAS_BMSK 0xf0 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR2_OAS_SHFT 0x4 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR2_IAS_BMSK 0xf +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR2_IAS_SHFT 0x0 + +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR4_ADDR (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE + 0x00000030) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR4_PHYS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_PHYS + 0x00000030) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR4_OFFS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_OFFS + 0x00000030) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR4_RMSK 0xffffffff +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR4_ATTR 0x1 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR4_IN \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR4_ADDR, HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR4_RMSK) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR4_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR4_ADDR, m) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR4_MAJOR_BMSK 0xf0000000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR4_MAJOR_SHFT 0x1c +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR4_MINOR_BMSK 0xfff0000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR4_MINOR_SHFT 0x10 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR4_STEP_BMSK 0xffff +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR4_STEP_SHFT 0x0 + +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR5_ADDR (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE + 0x00000034) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR5_PHYS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_PHYS + 0x00000034) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR5_OFFS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_OFFS + 0x00000034) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR5_RMSK 0xff03ff +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR5_ATTR 0x1 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR5_IN \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR5_ADDR, HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR5_RMSK) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR5_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR5_ADDR, m) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR5_NUMMSDRB_BMSK 0xff0000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR5_NUMMSDRB_SHFT 0x10 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR5_MSAE_BMSK 0x200 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR5_MSAE_SHFT 0x9 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR5_QRIBE_BMSK 0x100 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR5_QRIBE_SHFT 0x8 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR5_NVMID_BMSK 0xff +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR5_NVMID_SHFT 0x0 + +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR7_ADDR (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE + 0x0000003c) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR7_PHYS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_PHYS + 0x0000003c) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR7_OFFS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_OFFS + 0x0000003c) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR7_RMSK 0xff +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR7_ATTR 0x1 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR7_IN \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR7_ADDR, HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR7_RMSK) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR7_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR7_ADDR, m) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR7_MAJOR_BMSK 0xf0 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR7_MAJOR_SHFT 0x4 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR7_MINOR_BMSK 0xf +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_IDR7_MINOR_SHFT 0x0 + +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFAR0_ADDR (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE + 0x00000040) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFAR0_PHYS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_PHYS + 0x00000040) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFAR0_OFFS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_OFFS + 0x00000040) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFAR0_RMSK 0xffffffff +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFAR0_ATTR 0x1 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFAR0_IN \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFAR0_ADDR, HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFAR0_RMSK) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFAR0_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFAR0_ADDR, m) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFAR0_GFEA0_BMSK 0xffffffff +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFAR0_GFEA0_SHFT 0x0 + +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFAR1_ADDR (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE + 0x00000044) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFAR1_PHYS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_PHYS + 0x00000044) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFAR1_OFFS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_OFFS + 0x00000044) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFAR1_RMSK 0xff +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFAR1_ATTR 0x1 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFAR1_IN \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFAR1_ADDR, HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFAR1_RMSK) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFAR1_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFAR1_ADDR, m) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFAR1_GFEA1_BMSK 0xff +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFAR1_GFEA1_SHFT 0x0 + +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSR_ADDR (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE + 0x00000048) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSR_PHYS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_PHYS + 0x00000048) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSR_OFFS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_OFFS + 0x00000048) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSR_RMSK 0xc00000a6 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSR_ATTR 0x3 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSR_IN \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSR_ADDR, HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSR_RMSK) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSR_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSR_ADDR, m) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSR_OUT(v) \ + out_dword(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSR_ADDR,v) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSR_ADDR,m,v,HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSR_IN) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSR_MULTI_CLIENT_BMSK 0x80000000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSR_MULTI_CLIENT_SHFT 0x1f +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSR_MULTI_CFG_BMSK 0x40000000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSR_MULTI_CFG_SHFT 0x1e +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSR_PF_BMSK 0x80 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSR_PF_SHFT 0x7 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSR_CAF_BMSK 0x20 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSR_CAF_SHFT 0x5 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSR_SMCF_BMSK 0x4 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSR_SMCF_SHFT 0x2 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSR_USF_BMSK 0x2 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSR_USF_SHFT 0x1 + +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSRRESTORE_ADDR (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE + 0x0000004c) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSRRESTORE_PHYS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_PHYS + 0x0000004c) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSRRESTORE_OFFS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_OFFS + 0x0000004c) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSRRESTORE_RMSK 0xc00000a6 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSRRESTORE_ATTR 0x3 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSRRESTORE_IN \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSRRESTORE_ADDR, HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSRRESTORE_RMSK) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSRRESTORE_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSRRESTORE_ADDR, m) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSRRESTORE_OUT(v) \ + out_dword(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSRRESTORE_ADDR,v) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSRRESTORE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSRRESTORE_ADDR,m,v,HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSRRESTORE_IN) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSRRESTORE_MULTI_CLIENT_BMSK 0x80000000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSRRESTORE_MULTI_CLIENT_SHFT 0x1f +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSRRESTORE_MULTI_CFG_BMSK 0x40000000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSRRESTORE_MULTI_CFG_SHFT 0x1e +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSRRESTORE_PF_BMSK 0x80 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSRRESTORE_PF_SHFT 0x7 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSRRESTORE_CAF_BMSK 0x20 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSRRESTORE_CAF_SHFT 0x5 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSRRESTORE_SMCF_BMSK 0x4 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSRRESTORE_SMCF_SHFT 0x2 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSRRESTORE_USF_BMSK 0x2 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSRRESTORE_USF_SHFT 0x1 + +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSYNDR0_ADDR (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE + 0x00000050) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSYNDR0_PHYS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_PHYS + 0x00000050) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSYNDR0_OFFS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_OFFS + 0x00000050) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSYNDR0_RMSK 0x132 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSYNDR0_ATTR 0x1 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSYNDR0_IN \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSYNDR0_ADDR, HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSYNDR0_RMSK) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSYNDR0_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSYNDR0_ADDR, m) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSYNDR0_MSSSELFAUTH_BMSK 0x100 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSYNDR0_MSSSELFAUTH_SHFT 0x8 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSYNDR0_NSATTR_BMSK 0x20 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSYNDR0_NSATTR_SHFT 0x5 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSYNDR0_NSSTATE_BMSK 0x10 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSYNDR0_NSSTATE_SHFT 0x4 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSYNDR0_WNR_BMSK 0x2 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSYNDR0_WNR_SHFT 0x1 + +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSYNDR1_ADDR (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE + 0x00000054) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSYNDR1_PHYS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_PHYS + 0x00000054) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSYNDR1_OFFS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_OFFS + 0x00000054) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSYNDR1_RMSK 0x7fff00ff +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSYNDR1_ATTR 0x1 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSYNDR1_IN \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSYNDR1_ADDR, HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSYNDR1_RMSK) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSYNDR1_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSYNDR1_ADDR, m) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSYNDR1_MSDINDEX_BMSK 0x7f000000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSYNDR1_MSDINDEX_SHFT 0x18 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSYNDR1_SSDINDEX_BMSK 0xff0000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSYNDR1_SSDINDEX_SHFT 0x10 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSYNDR1_STREAMINDEX_BMSK 0xff +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSYNDR1_STREAMINDEX_SHFT 0x0 + +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSYNDR2_ADDR (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE + 0x00000058) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSYNDR2_PHYS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_PHYS + 0x00000058) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSYNDR2_OFFS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_OFFS + 0x00000058) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSYNDR2_RMSK 0x1f1fffff +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSYNDR2_ATTR 0x1 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSYNDR2_IN \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSYNDR2_ADDR, HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSYNDR2_RMSK) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSYNDR2_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSYNDR2_ADDR, m) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSYNDR2_ATID_BMSK 0x1f000000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSYNDR2_ATID_SHFT 0x18 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSYNDR2_AVMID_BMSK 0x1f0000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSYNDR2_AVMID_SHFT 0x10 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSYNDR2_ABID_BMSK 0xe000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSYNDR2_ABID_SHFT 0xd +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSYNDR2_APID_BMSK 0x1f00 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSYNDR2_APID_SHFT 0x8 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSYNDR2_AMID_BMSK 0xff +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_GFSYNDR2_AMID_SHFT 0x0 + +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_VMIDMTCR0_ADDR (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE + 0x00000090) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_VMIDMTCR0_PHYS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_PHYS + 0x00000090) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_VMIDMTCR0_OFFS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_OFFS + 0x00000090) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_VMIDMTCR0_RMSK 0x1 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_VMIDMTCR0_ATTR 0x3 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_VMIDMTCR0_IN \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_VMIDMTCR0_ADDR, HWIO_IPA_0_IPA_VMIDMT_VMIDMT_VMIDMTCR0_RMSK) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_VMIDMTCR0_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_VMIDMTCR0_ADDR, m) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_VMIDMTCR0_OUT(v) \ + out_dword(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_VMIDMTCR0_ADDR,v) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_VMIDMTCR0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_VMIDMTCR0_ADDR,m,v,HWIO_IPA_0_IPA_VMIDMT_VMIDMT_VMIDMTCR0_IN) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_VMIDMTCR0_CLKONOFFE_BMSK 0x1 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_VMIDMTCR0_CLKONOFFE_SHFT 0x0 + +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_VMIDMTACR_ADDR (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE + 0x0000009c) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_VMIDMTACR_PHYS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_PHYS + 0x0000009c) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_VMIDMTACR_OFFS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_OFFS + 0x0000009c) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_VMIDMTACR_RMSK 0xffffffff +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_VMIDMTACR_ATTR 0x3 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_VMIDMTACR_IN \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_VMIDMTACR_ADDR, HWIO_IPA_0_IPA_VMIDMT_VMIDMT_VMIDMTACR_RMSK) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_VMIDMTACR_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_VMIDMTACR_ADDR, m) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_VMIDMTACR_OUT(v) \ + out_dword(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_VMIDMTACR_ADDR,v) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_VMIDMTACR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_VMIDMTACR_ADDR,m,v,HWIO_IPA_0_IPA_VMIDMT_VMIDMT_VMIDMTACR_IN) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_VMIDMTACR_RWE_BMSK 0xffffffff +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_VMIDMTACR_RWE_SHFT 0x0 + +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSCR0_ADDR (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE + 0x00000400) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSCR0_PHYS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_PHYS + 0x00000400) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSCR0_OFFS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_OFFS + 0x00000400) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSCR0_RMSK 0xff70ff5 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSCR0_ATTR 0x3 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSCR0_IN \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSCR0_ADDR, HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSCR0_RMSK) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSCR0_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSCR0_ADDR, m) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSCR0_OUT(v) \ + out_dword(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSCR0_ADDR,v) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSCR0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSCR0_ADDR,m,v,HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSCR0_IN) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSCR0_WACFG_BMSK 0xc000000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSCR0_WACFG_SHFT 0x1a +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSCR0_RACFG_BMSK 0x3000000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSCR0_RACFG_SHFT 0x18 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSCR0_SHCFG_BMSK 0xc00000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSCR0_SHCFG_SHFT 0x16 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSCR0_SMCFCFG_BMSK 0x200000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSCR0_SMCFCFG_SHFT 0x15 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSCR0_MTCFG_BMSK 0x100000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSCR0_MTCFG_SHFT 0x14 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSCR0_MEMATTR_BMSK 0x70000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSCR0_MEMATTR_SHFT 0x10 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSCR0_VMIDPNE_BMSK 0x800 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSCR0_VMIDPNE_SHFT 0xb +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSCR0_USFCFG_BMSK 0x400 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSCR0_USFCFG_SHFT 0xa +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSCR0_GSE_BMSK 0x200 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSCR0_GSE_SHFT 0x9 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSCR0_STALLD_BMSK 0x100 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSCR0_STALLD_SHFT 0x8 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSCR0_TRANSIENTCFG_BMSK 0xc0 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSCR0_TRANSIENTCFG_SHFT 0x6 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSCR0_GCFGFIE_BMSK 0x20 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSCR0_GCFGFIE_SHFT 0x5 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSCR0_GCFGERE_BMSK 0x10 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSCR0_GCFGERE_SHFT 0x4 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSCR0_GFIE_BMSK 0x4 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSCR0_GFIE_SHFT 0x2 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSCR0_CLIENTPD_BMSK 0x1 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSCR0_CLIENTPD_SHFT 0x0 + +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSCR2_ADDR (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE + 0x00000408) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSCR2_PHYS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_PHYS + 0x00000408) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSCR2_OFFS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_OFFS + 0x00000408) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSCR2_RMSK 0x1f +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSCR2_ATTR 0x3 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSCR2_IN \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSCR2_ADDR, HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSCR2_RMSK) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSCR2_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSCR2_ADDR, m) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSCR2_OUT(v) \ + out_dword(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSCR2_ADDR,v) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSCR2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSCR2_ADDR,m,v,HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSCR2_IN) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSCR2_BPVMID_BMSK 0x1f +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSCR2_BPVMID_SHFT 0x0 + +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSACR_ADDR (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE + 0x00000410) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSACR_PHYS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_PHYS + 0x00000410) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSACR_OFFS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_OFFS + 0x00000410) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSACR_RMSK 0x70000013 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSACR_ATTR 0x3 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSACR_IN \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSACR_ADDR, HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSACR_RMSK) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSACR_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSACR_ADDR, m) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSACR_OUT(v) \ + out_dword(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSACR_ADDR,v) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSACR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSACR_ADDR,m,v,HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSACR_IN) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSACR_BPRCNSH_BMSK 0x40000000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSACR_BPRCNSH_SHFT 0x1e +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSACR_BPRCISH_BMSK 0x20000000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSACR_BPRCISH_SHFT 0x1d +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSACR_BPRCOSH_BMSK 0x10000000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSACR_BPRCOSH_SHFT 0x1c +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSACR_BPREQPRIORITYCFG_BMSK 0x10 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSACR_BPREQPRIORITYCFG_SHFT 0x4 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSACR_BPREQPRIORITY_BMSK 0x3 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSACR_BPREQPRIORITY_SHFT 0x0 + +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFAR0_ADDR (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE + 0x00000440) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFAR0_PHYS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_PHYS + 0x00000440) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFAR0_OFFS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_OFFS + 0x00000440) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFAR0_RMSK 0xffffffff +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFAR0_ATTR 0x1 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFAR0_IN \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFAR0_ADDR, HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFAR0_RMSK) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFAR0_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFAR0_ADDR, m) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFAR0_GFEA0_BMSK 0xffffffff +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFAR0_GFEA0_SHFT 0x0 + +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFAR1_ADDR (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE + 0x00000444) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFAR1_PHYS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_PHYS + 0x00000444) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFAR1_OFFS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_OFFS + 0x00000444) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFAR1_RMSK 0xff +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFAR1_ATTR 0x1 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFAR1_IN \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFAR1_ADDR, HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFAR1_RMSK) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFAR1_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFAR1_ADDR, m) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFAR1_GFEA1_BMSK 0xff +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFAR1_GFEA1_SHFT 0x0 + +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSR_ADDR (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE + 0x00000448) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSR_PHYS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_PHYS + 0x00000448) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSR_OFFS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_OFFS + 0x00000448) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSR_RMSK 0xc00000a6 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSR_ATTR 0x3 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSR_IN \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSR_ADDR, HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSR_RMSK) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSR_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSR_ADDR, m) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSR_OUT(v) \ + out_dword(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSR_ADDR,v) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSR_ADDR,m,v,HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSR_IN) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSR_MULTI_CLIENT_BMSK 0x80000000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSR_MULTI_CLIENT_SHFT 0x1f +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSR_MULTI_CFG_BMSK 0x40000000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSR_MULTI_CFG_SHFT 0x1e +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSR_PF_BMSK 0x80 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSR_PF_SHFT 0x7 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSR_CAF_BMSK 0x20 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSR_CAF_SHFT 0x5 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSR_SMCF_BMSK 0x4 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSR_SMCF_SHFT 0x2 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSR_USF_BMSK 0x2 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSR_USF_SHFT 0x1 + +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSRRESTORE_ADDR (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE + 0x0000044c) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSRRESTORE_PHYS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_PHYS + 0x0000044c) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSRRESTORE_OFFS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_OFFS + 0x0000044c) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSRRESTORE_RMSK 0xc00000a6 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSRRESTORE_ATTR 0x3 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSRRESTORE_IN \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSRRESTORE_ADDR, HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSRRESTORE_RMSK) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSRRESTORE_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSRRESTORE_ADDR, m) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSRRESTORE_OUT(v) \ + out_dword(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSRRESTORE_ADDR,v) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSRRESTORE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSRRESTORE_ADDR,m,v,HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSRRESTORE_IN) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSRRESTORE_MULTI_CLIENT_BMSK 0x80000000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSRRESTORE_MULTI_CLIENT_SHFT 0x1f +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSRRESTORE_MULTI_CFG_BMSK 0x40000000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSRRESTORE_MULTI_CFG_SHFT 0x1e +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSRRESTORE_PF_BMSK 0x80 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSRRESTORE_PF_SHFT 0x7 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSRRESTORE_CAF_BMSK 0x20 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSRRESTORE_CAF_SHFT 0x5 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSRRESTORE_SMCF_BMSK 0x4 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSRRESTORE_SMCF_SHFT 0x2 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSRRESTORE_USF_BMSK 0x2 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSRRESTORE_USF_SHFT 0x1 + +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSYNDR0_ADDR (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE + 0x00000450) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSYNDR0_PHYS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_PHYS + 0x00000450) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSYNDR0_OFFS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_OFFS + 0x00000450) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSYNDR0_RMSK 0x132 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSYNDR0_ATTR 0x1 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSYNDR0_IN \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSYNDR0_ADDR, HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSYNDR0_RMSK) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSYNDR0_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSYNDR0_ADDR, m) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSYNDR0_MSSSELFAUTH_BMSK 0x100 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSYNDR0_MSSSELFAUTH_SHFT 0x8 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSYNDR0_NSATTR_BMSK 0x20 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSYNDR0_NSATTR_SHFT 0x5 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSYNDR0_NSSTATE_BMSK 0x10 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSYNDR0_NSSTATE_SHFT 0x4 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSYNDR0_WNR_BMSK 0x2 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSYNDR0_WNR_SHFT 0x1 + +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSYNDR1_ADDR (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE + 0x00000454) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSYNDR1_PHYS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_PHYS + 0x00000454) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSYNDR1_OFFS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_OFFS + 0x00000454) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSYNDR1_RMSK 0x7fff00ff +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSYNDR1_ATTR 0x1 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSYNDR1_IN \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSYNDR1_ADDR, HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSYNDR1_RMSK) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSYNDR1_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSYNDR1_ADDR, m) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSYNDR1_MSDINDEX_BMSK 0x7f000000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSYNDR1_MSDINDEX_SHFT 0x18 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSYNDR1_SSDINDEX_BMSK 0xff0000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSYNDR1_SSDINDEX_SHFT 0x10 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSYNDR1_STREAMINDEX_BMSK 0xff +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSYNDR1_STREAMINDEX_SHFT 0x0 + +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSYNDR2_ADDR (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE + 0x00000458) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSYNDR2_PHYS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_PHYS + 0x00000458) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSYNDR2_OFFS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_OFFS + 0x00000458) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSYNDR2_RMSK 0x1f1fffff +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSYNDR2_ATTR 0x1 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSYNDR2_IN \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSYNDR2_ADDR, HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSYNDR2_RMSK) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSYNDR2_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSYNDR2_ADDR, m) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSYNDR2_ATID_BMSK 0x1f000000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSYNDR2_ATID_SHFT 0x18 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSYNDR2_AVMID_BMSK 0x1f0000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSYNDR2_AVMID_SHFT 0x10 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSYNDR2_ABID_BMSK 0xe000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSYNDR2_ABID_SHFT 0xd +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSYNDR2_APID_BMSK 0x1f00 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSYNDR2_APID_SHFT 0x8 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSYNDR2_AMID_BMSK 0xff +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSGFSYNDR2_AMID_SHFT 0x0 + +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSVMIDMTCR0_ADDR (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE + 0x00000490) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSVMIDMTCR0_PHYS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_PHYS + 0x00000490) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSVMIDMTCR0_OFFS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_OFFS + 0x00000490) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSVMIDMTCR0_RMSK 0x1 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSVMIDMTCR0_ATTR 0x3 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSVMIDMTCR0_IN \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSVMIDMTCR0_ADDR, HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSVMIDMTCR0_RMSK) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSVMIDMTCR0_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSVMIDMTCR0_ADDR, m) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSVMIDMTCR0_OUT(v) \ + out_dword(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSVMIDMTCR0_ADDR,v) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSVMIDMTCR0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSVMIDMTCR0_ADDR,m,v,HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSVMIDMTCR0_IN) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSVMIDMTCR0_CLKONOFFE_BMSK 0x1 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_NSVMIDMTCR0_CLKONOFFE_SHFT 0x0 + +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR0_ADDR (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE + 0x00000080) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR0_PHYS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_PHYS + 0x00000080) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR0_OFFS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_OFFS + 0x00000080) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR0_RMSK 0xffffffff +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR0_ATTR 0x3 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR0_IN \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR0_ADDR, HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR0_RMSK) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR0_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR0_ADDR, m) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR0_OUT(v) \ + out_dword(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR0_ADDR,v) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR0_ADDR,m,v,HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR0_IN) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR0_RWE_BMSK 0xffffffff +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR0_RWE_SHFT 0x0 + +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR1_ADDR (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE + 0x00000084) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR1_PHYS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_PHYS + 0x00000084) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR1_OFFS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_OFFS + 0x00000084) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR1_RMSK 0xffffffff +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR1_ATTR 0x3 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR1_IN \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR1_ADDR, HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR1_RMSK) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR1_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR1_ADDR, m) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR1_OUT(v) \ + out_dword(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR1_ADDR,v) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR1_ADDR,m,v,HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR1_IN) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR1_RWE_BMSK 0xffffffff +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR1_RWE_SHFT 0x0 + +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR2_ADDR (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE + 0x00000088) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR2_PHYS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_PHYS + 0x00000088) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR2_OFFS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_OFFS + 0x00000088) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR2_RMSK 0xffffffff +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR2_ATTR 0x3 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR2_IN \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR2_ADDR, HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR2_RMSK) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR2_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR2_ADDR, m) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR2_OUT(v) \ + out_dword(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR2_ADDR,v) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR2_ADDR,m,v,HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR2_IN) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR2_RWE_BMSK 0xffffffff +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR2_RWE_SHFT 0x0 + +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR3_ADDR (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE + 0x0000008c) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR3_PHYS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_PHYS + 0x0000008c) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR3_OFFS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_OFFS + 0x0000008c) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR3_RMSK 0xffffffff +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR3_ATTR 0x3 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR3_IN \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR3_ADDR, HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR3_RMSK) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR3_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR3_ADDR, m) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR3_OUT(v) \ + out_dword(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR3_ADDR,v) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR3_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR3_ADDR,m,v,HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR3_IN) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR3_RWE_BMSK 0xffffffff +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SSDR3_RWE_SHFT 0x0 + +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR0_ADDR (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE + 0x00000480) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR0_PHYS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_PHYS + 0x00000480) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR0_OFFS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_OFFS + 0x00000480) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR0_RMSK 0xffffffff +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR0_ATTR 0x3 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR0_IN \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR0_ADDR, HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR0_RMSK) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR0_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR0_ADDR, m) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR0_OUT(v) \ + out_dword(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR0_ADDR,v) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR0_ADDR,m,v,HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR0_IN) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR0_RWE_BMSK 0xffffffff +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR0_RWE_SHFT 0x0 + +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR1_ADDR (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE + 0x00000484) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR1_PHYS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_PHYS + 0x00000484) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR1_OFFS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_OFFS + 0x00000484) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR1_RMSK 0xffffffff +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR1_ATTR 0x3 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR1_IN \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR1_ADDR, HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR1_RMSK) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR1_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR1_ADDR, m) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR1_OUT(v) \ + out_dword(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR1_ADDR,v) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR1_ADDR,m,v,HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR1_IN) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR1_RWE_BMSK 0xffffffff +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR1_RWE_SHFT 0x0 + +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR2_ADDR (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE + 0x00000488) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR2_PHYS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_PHYS + 0x00000488) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR2_OFFS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_OFFS + 0x00000488) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR2_RMSK 0xffffffff +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR2_ATTR 0x3 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR2_IN \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR2_ADDR, HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR2_RMSK) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR2_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR2_ADDR, m) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR2_OUT(v) \ + out_dword(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR2_ADDR,v) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR2_ADDR,m,v,HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR2_IN) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR2_RWE_BMSK 0xffffffff +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR2_RWE_SHFT 0x0 + +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR3_ADDR (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE + 0x0000048c) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR3_PHYS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_PHYS + 0x0000048c) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR3_OFFS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_OFFS + 0x0000048c) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR3_RMSK 0xffffffff +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR3_ATTR 0x3 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR3_IN \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR3_ADDR, HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR3_RMSK) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR3_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR3_ADDR, m) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR3_OUT(v) \ + out_dword(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR3_ADDR,v) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR3_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR3_ADDR,m,v,HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR3_IN) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR3_RWE_BMSK 0xffffffff +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MSDR3_RWE_SHFT 0x0 + +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MCR_ADDR (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE + 0x00000494) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MCR_PHYS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_PHYS + 0x00000494) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MCR_OFFS (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_OFFS + 0x00000494) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MCR_RMSK 0x7 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MCR_ATTR 0x3 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MCR_IN \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MCR_ADDR, HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MCR_RMSK) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MCR_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MCR_ADDR, m) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MCR_OUT(v) \ + out_dword(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MCR_ADDR,v) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MCR_ADDR,m,v,HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MCR_IN) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MCR_CLKONOFFE_BMSK 0x4 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MCR_CLKONOFFE_SHFT 0x2 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MCR_BPMSACFG_BMSK 0x2 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MCR_BPMSACFG_SHFT 0x1 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MCR_BPSMSACFG_BMSK 0x1 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_MCR_BPSMSACFG_SHFT 0x0 + +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_S2VRn_ADDR(n) (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE + 0x00000c00 + 0x4 * (n)) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_S2VRn_PHYS(n) (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_PHYS + 0x00000c00 + 0x4 * (n)) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_S2VRn_OFFS(n) (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_OFFS + 0x00000c00 + 0x4 * (n)) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_S2VRn_RMSK 0x30ff7b1f +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_S2VRn_MAXn 47 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_S2VRn_ATTR 0x3 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_S2VRn_INI(n) \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_S2VRn_ADDR(n), HWIO_IPA_0_IPA_VMIDMT_VMIDMT_S2VRn_RMSK) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_S2VRn_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_S2VRn_ADDR(n), mask) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_S2VRn_OUTI(n,val) \ + out_dword(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_S2VRn_ADDR(n),val) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_S2VRn_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_S2VRn_ADDR(n),mask,val,HWIO_IPA_0_IPA_VMIDMT_VMIDMT_S2VRn_INI(n)) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_S2VRn_TRANSIENTCFG_BMSK 0x30000000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_S2VRn_TRANSIENTCFG_SHFT 0x1c +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_S2VRn_WACFG_BMSK 0xc00000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_S2VRn_WACFG_SHFT 0x16 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_S2VRn_RACFG_BMSK 0x300000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_S2VRn_RACFG_SHFT 0x14 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_S2VRn_NSCFG_BMSK 0xc0000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_S2VRn_NSCFG_SHFT 0x12 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_S2VRn_TYPE_BMSK 0x30000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_S2VRn_TYPE_SHFT 0x10 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_S2VRn_MEMATTR_BMSK 0x7000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_S2VRn_MEMATTR_SHFT 0xc +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_S2VRn_MTCFG_BMSK 0x800 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_S2VRn_MTCFG_SHFT 0xb +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_S2VRn_SHCFG_BMSK 0x300 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_S2VRn_SHCFG_SHFT 0x8 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_S2VRn_VMID_BMSK 0x1f +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_S2VRn_VMID_SHFT 0x0 + +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_AS2VRn_ADDR(n) (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE + 0x00000e00 + 0x4 * (n)) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_AS2VRn_PHYS(n) (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_PHYS + 0x00000e00 + 0x4 * (n)) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_AS2VRn_OFFS(n) (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_OFFS + 0x00000e00 + 0x4 * (n)) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_AS2VRn_RMSK 0x70000013 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_AS2VRn_MAXn 47 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_AS2VRn_ATTR 0x3 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_AS2VRn_INI(n) \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_AS2VRn_ADDR(n), HWIO_IPA_0_IPA_VMIDMT_VMIDMT_AS2VRn_RMSK) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_AS2VRn_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_AS2VRn_ADDR(n), mask) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_AS2VRn_OUTI(n,val) \ + out_dword(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_AS2VRn_ADDR(n),val) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_AS2VRn_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_AS2VRn_ADDR(n),mask,val,HWIO_IPA_0_IPA_VMIDMT_VMIDMT_AS2VRn_INI(n)) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_AS2VRn_RCNSH_BMSK 0x40000000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_AS2VRn_RCNSH_SHFT 0x1e +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_AS2VRn_RCISH_BMSK 0x20000000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_AS2VRn_RCISH_SHFT 0x1d +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_AS2VRn_RCOSH_BMSK 0x10000000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_AS2VRn_RCOSH_SHFT 0x1c +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_AS2VRn_REQPRIORITYCFG_BMSK 0x10 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_AS2VRn_REQPRIORITYCFG_SHFT 0x4 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_AS2VRn_REQPRIORITY_BMSK 0x3 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_AS2VRn_REQPRIORITY_SHFT 0x0 + +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SMRn_ADDR(n) (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE + 0x00000800 + 0x4 * (n)) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SMRn_PHYS(n) (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_PHYS + 0x00000800 + 0x4 * (n)) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SMRn_OFFS(n) (IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40_REG_BASE_OFFS + 0x00000800 + 0x4 * (n)) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SMRn_RMSK 0x80ff00ff +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SMRn_MAXn 47 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SMRn_ATTR 0x3 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SMRn_INI(n) \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SMRn_ADDR(n), HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SMRn_RMSK) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SMRn_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SMRn_ADDR(n), mask) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SMRn_OUTI(n,val) \ + out_dword(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SMRn_ADDR(n),val) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SMRn_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SMRn_ADDR(n),mask,val,HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SMRn_INI(n)) +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SMRn_VALID_BMSK 0x80000000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SMRn_VALID_SHFT 0x1f +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SMRn_MASK_BMSK 0xff0000 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SMRn_MASK_SHFT 0x10 +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SMRn_ID_BMSK 0xff +#define HWIO_IPA_0_IPA_VMIDMT_VMIDMT_SMRn_ID_SHFT 0x0 + +/*---------------------------------------------------------------------------- + * MODULE: IPA_0_IPA_ER_XPU_CFG_ER_XPU4 + *--------------------------------------------------------------------------*/ + +#define IPA_0_IPA_ER_XPU_CFG_ER_XPU4_REG_BASE (IPA_0_IPA_WRAPPER_BASE + 0x00000000) +#define IPA_0_IPA_ER_XPU_CFG_ER_XPU4_REG_BASE_PHYS (IPA_0_IPA_WRAPPER_BASE_PHYS + 0x00000000) +#define IPA_0_IPA_ER_XPU_CFG_ER_XPU4_REG_BASE_OFFS 0x00000000 + +/*---------------------------------------------------------------------------- + * MODULE: IPA_0_IPA_ER_XPU_CFG_XPU4 + *--------------------------------------------------------------------------*/ + +#define IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE (IPA_0_IPA_WRAPPER_BASE + 0x00000000) +#define IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE_PHYS (IPA_0_IPA_WRAPPER_BASE_PHYS + 0x00000000) +#define IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE_OFFS 0x00000000 + +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_IDR0_ADDR (IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE + 0x00000000) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_IDR0_PHYS (IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE_PHYS + 0x00000000) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_IDR0_OFFS (IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE_OFFS + 0x00000000) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_IDR0_RMSK 0x3ff0073 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_IDR0_ATTR 0x1 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_IDR0_IN \ + in_dword_masked(HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_IDR0_ADDR, HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_IDR0_RMSK) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_IDR0_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_IDR0_ADDR, m) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_IDR0_NRG_BMSK 0x3ff0000 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_IDR0_NRG_SHFT 0x10 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_IDR0_BLED_BMSK 0x40 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_IDR0_BLED_SHFT 0x6 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_IDR0_CLIENT_HALTREQACK_EN_BMSK 0x20 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_IDR0_CLIENT_HALTREQACK_EN_SHFT 0x5 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_IDR0_CLIENT_PIPELINE_EN_BMSK 0x10 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_IDR0_CLIENT_PIPELINE_EN_SHFT 0x4 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_IDR0_XPU_TYPE_BMSK 0x3 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_IDR0_XPU_TYPE_SHFT 0x0 + +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_IDR1_ADDR (IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE + 0x00000004) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_IDR1_PHYS (IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE_PHYS + 0x00000004) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_IDR1_OFFS (IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE_OFFS + 0x00000004) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_IDR1_RMSK 0x3f3f3f3f +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_IDR1_ATTR 0x1 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_IDR1_IN \ + in_dword_masked(HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_IDR1_ADDR, HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_IDR1_RMSK) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_IDR1_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_IDR1_ADDR, m) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_IDR1_CLIENT_ADDR_WIDTH_BMSK 0x3f000000 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_IDR1_CLIENT_ADDR_WIDTH_SHFT 0x18 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_IDR1_CONFIG_ADDR_WIDTH_BMSK 0x3f0000 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_IDR1_CONFIG_ADDR_WIDTH_SHFT 0x10 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_IDR1_ADDR_MSB_BMSK 0x3f00 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_IDR1_ADDR_MSB_SHFT 0x8 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_IDR1_ADDR_LSB_BMSK 0x3f +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_IDR1_ADDR_LSB_SHFT 0x0 + +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_IDR2_ADDR (IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE + 0x00000008) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_IDR2_PHYS (IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE_PHYS + 0x00000008) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_IDR2_OFFS (IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE_OFFS + 0x00000008) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_IDR2_RMSK 0x11f +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_IDR2_ATTR 0x1 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_IDR2_IN \ + in_dword_masked(HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_IDR2_ADDR, HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_IDR2_RMSK) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_IDR2_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_IDR2_ADDR, m) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_IDR2_USELEGACYINTF_BMSK 0x100 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_IDR2_USELEGACYINTF_SHFT 0x8 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_IDR2_NQAD_BMSK 0x1f +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_IDR2_NQAD_SHFT 0x0 + +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_REV_ADDR (IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE + 0x0000000c) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_REV_PHYS (IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE_PHYS + 0x0000000c) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_REV_OFFS (IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE_OFFS + 0x0000000c) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_REV_RMSK 0xffffffff +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_REV_ATTR 0x1 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_REV_IN \ + in_dword_masked(HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_REV_ADDR, HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_REV_RMSK) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_REV_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_REV_ADDR, m) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_REV_MAJOR_BMSK 0xf0000000 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_REV_MAJOR_SHFT 0x1c +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_REV_MINOR_BMSK 0xfff0000 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_REV_MINOR_SHFT 0x10 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_REV_STEP_BMSK 0xffff +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_REV_STEP_SHFT 0x0 + +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_GCR_ADDR (IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE + 0x00000100) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_GCR_PHYS (IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE_PHYS + 0x00000100) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_GCR_OFFS (IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE_OFFS + 0x00000100) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_GCR_RMSK 0x3 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_GCR_ATTR 0x3 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_GCR_IN \ + in_dword_masked(HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_GCR_ADDR, HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_GCR_RMSK) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_GCR_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_GCR_ADDR, m) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_GCR_OUT(v) \ + out_dword(HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_GCR_ADDR,v) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_GCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_GCR_ADDR,m,v,HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_GCR_IN) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_GCR_DYNAMIC_CLK_EN_BMSK 0x2 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_GCR_DYNAMIC_CLK_EN_SHFT 0x1 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_GCR_APNSPE_BMSK 0x1 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_GCR_APNSPE_SHFT 0x0 + +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RSR_ADDR (IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE + 0x00000104) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RSR_PHYS (IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE_PHYS + 0x00000104) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RSR_OFFS (IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE_OFFS + 0x00000104) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RSR_RMSK 0xffffffff +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RSR_ATTR 0x1 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RSR_IN \ + in_dword_masked(HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RSR_ADDR, HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RSR_RMSK) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RSR_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RSR_ADDR, m) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RSR_NXTFRG_BMSK 0xffff0000 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RSR_NXTFRG_SHFT 0x10 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RSR_NUMFRG_BMSK 0xffff +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RSR_NUMFRG_SHFT 0x0 + +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_CFGERE_ADDR (IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE + 0x00000208) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_CFGERE_PHYS (IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE_PHYS + 0x00000208) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_CFGERE_OFFS (IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE_OFFS + 0x00000208) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_CFGERE_RMSK 0xc000007f +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_CFGERE_ATTR 0x3 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_CFGERE_IN \ + in_dword_masked(HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_CFGERE_ADDR, HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_CFGERE_RMSK) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_CFGERE_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_CFGERE_ADDR, m) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_CFGERE_OUT(v) \ + out_dword(HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_CFGERE_ADDR,v) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_CFGERE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_CFGERE_ADDR,m,v,HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_CFGERE_IN) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_CFGERE_CFGERE_S_BMSK 0x80000000 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_CFGERE_CFGERE_S_SHFT 0x1f +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_CFGERE_CFGERE_NS_BMSK 0x40000000 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_CFGERE_CFGERE_NS_SHFT 0x1e +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_CFGERE_CFGERE_QAD_BMSK 0x7f +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_CFGERE_CFGERE_QAD_SHFT 0x0 + +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_CLERE_ADDR (IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE + 0x0000020c) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_CLERE_PHYS (IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE_PHYS + 0x0000020c) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_CLERE_OFFS (IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE_OFFS + 0x0000020c) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_CLERE_RMSK 0xc000007f +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_CLERE_ATTR 0x3 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_CLERE_IN \ + in_dword_masked(HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_CLERE_ADDR, HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_CLERE_RMSK) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_CLERE_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_CLERE_ADDR, m) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_CLERE_OUT(v) \ + out_dword(HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_CLERE_ADDR,v) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_CLERE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_CLERE_ADDR,m,v,HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_CLERE_IN) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_CLERE_CLERE_S_BMSK 0x80000000 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_CLERE_CLERE_S_SHFT 0x1f +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_CLERE_CLERE_NS_BMSK 0x40000000 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_CLERE_CLERE_NS_SHFT 0x1e +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_CLERE_CLERE_QAD_BMSK 0x7f +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_CLERE_CLERE_QAD_SHFT 0x0 + +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_DBGAR_ADDR (IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE + 0x00000304) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_DBGAR_PHYS (IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE_PHYS + 0x00000304) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_DBGAR_OFFS (IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE_OFFS + 0x00000304) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_DBGAR_RMSK 0xc000007f +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_DBGAR_ATTR 0x3 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_DBGAR_IN \ + in_dword_masked(HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_DBGAR_ADDR, HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_DBGAR_RMSK) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_DBGAR_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_DBGAR_ADDR, m) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_DBGAR_OUT(v) \ + out_dword(HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_DBGAR_ADDR,v) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_DBGAR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_DBGAR_ADDR,m,v,HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_DBGAR_IN) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_DBGAR_DBGA_S_BMSK 0x80000000 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_DBGAR_DBGA_S_SHFT 0x1f +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_DBGAR_DBGA_NS_BMSK 0x40000000 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_DBGAR_DBGA_NS_SHFT 0x1e +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_DBGAR_DBGA_QAD_BMSK 0x7f +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_DBGAR_DBGA_QAD_SHFT 0x0 + +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_ESR_ADDR (IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE + 0x00000500) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_ESR_PHYS (IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE_PHYS + 0x00000500) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_ESR_OFFS (IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE_OFFS + 0x00000500) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_ESR_RMSK 0xf +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_ESR_ATTR 0x3 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_ESR_IN \ + in_dword_masked(HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_ESR_ADDR, HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_ESR_RMSK) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_ESR_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_ESR_ADDR, m) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_ESR_OUT(v) \ + out_dword(HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_ESR_ADDR,v) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_ESR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_ESR_ADDR,m,v,HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_ESR_IN) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_ESR_CLMULTI_BMSK 0x8 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_ESR_CLMULTI_SHFT 0x3 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_ESR_CFGMULTI_BMSK 0x4 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_ESR_CFGMULTI_SHFT 0x2 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_ESR_CLERR_BMSK 0x2 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_ESR_CLERR_SHFT 0x1 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_ESR_CFGERR_BMSK 0x1 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_ESR_CFGERR_SHFT 0x0 + +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNAR0_ADDR (IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE + 0x00000504) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNAR0_PHYS (IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE_PHYS + 0x00000504) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNAR0_OFFS (IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE_OFFS + 0x00000504) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNAR0_RMSK 0xffffffff +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNAR0_ATTR 0x1 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNAR0_IN \ + in_dword_masked(HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNAR0_ADDR, HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNAR0_RMSK) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNAR0_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNAR0_ADDR, m) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNAR0_SYNADDR_BMSK 0xffffffff +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNAR0_SYNADDR_SHFT 0x0 + +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNAR1_ADDR (IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE + 0x00000508) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNAR1_PHYS (IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE_PHYS + 0x00000508) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNAR1_OFFS (IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE_OFFS + 0x00000508) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNAR1_RMSK 0xffffffff +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNAR1_ATTR 0x1 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNAR1_IN \ + in_dword_masked(HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNAR1_ADDR, HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNAR1_RMSK) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNAR1_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNAR1_ADDR, m) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNAR1_SYNADDR_BMSK 0xffffffff +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNAR1_SYNADDR_SHFT 0x0 + +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR0_ADDR (IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE + 0x0000050c) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR0_PHYS (IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE_PHYS + 0x0000050c) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR0_OFFS (IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE_OFFS + 0x0000050c) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR0_RMSK 0xffff9f7f +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR0_ATTR 0x1 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR0_IN \ + in_dword_masked(HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR0_ADDR, HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR0_RMSK) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR0_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR0_ADDR, m) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR0_PH_BMSK 0x80000000 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR0_PH_SHFT 0x1f +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR0_AC_CFG_BMSK 0x40000000 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR0_AC_CFG_SHFT 0x1e +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR0_AC_CL_BMSK 0x20000000 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR0_AC_CL_SHFT 0x1d +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR0_BURSTLEN_BMSK 0x10000000 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR0_BURSTLEN_SHFT 0x1c +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR0_QADERR_BMSK 0x8000000 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR0_QADERR_SHFT 0x1b +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR0_APUDECERR_BMSK 0x4000000 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR0_APUDECERR_SHFT 0x1a +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR0_SSIZE_BMSK 0x3800000 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR0_SSIZE_SHFT 0x17 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR0_LEN_BMSK 0x7f8000 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR0_LEN_SHFT 0xf +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR0_QAD_BMSK 0x1f00 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR0_QAD_SHFT 0x8 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR0_REQ_OPC_BMSK 0x78 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR0_REQ_OPC_SHFT 0x3 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR0_PRIV_BMSK 0x4 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR0_PRIV_SHFT 0x2 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR0_INST_BMSK 0x2 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR0_INST_SHFT 0x1 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR0_XPROTNS_BMSK 0x1 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR0_XPROTNS_SHFT 0x0 + +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR1_ADDR (IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE + 0x00000510) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR1_PHYS (IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE_PHYS + 0x00000510) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR1_OFFS (IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE_OFFS + 0x00000510) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR1_RMSK 0xff07ffff +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR1_ATTR 0x1 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR1_IN \ + in_dword_masked(HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR1_ADDR, HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR1_RMSK) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR1_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR1_ADDR, m) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR1_TID_BMSK 0xff000000 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR1_TID_SHFT 0x18 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR1_TRTYPE_BMSK 0x70000 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR1_TRTYPE_SHFT 0x10 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR1_BID_BMSK 0xe000 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR1_BID_SHFT 0xd +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR1_PID_BMSK 0x1f00 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR1_PID_SHFT 0x8 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR1_MID_BMSK 0xff +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR1_MID_SHFT 0x0 + +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR2_ADDR (IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE + 0x00000514) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR2_PHYS (IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE_PHYS + 0x00000514) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR2_OFFS (IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE_OFFS + 0x00000514) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR2_RMSK 0x3ffffff +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR2_ATTR 0x1 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR2_IN \ + in_dword_masked(HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR2_ADDR, HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR2_RMSK) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR2_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR2_ADDR, m) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR2_APSVIOE_BMSK 0x2000000 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR2_APSVIOE_SHFT 0x19 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR2_SLE_BMSK 0x1000000 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR2_SLE_SHFT 0x18 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR2_CFG_OWNER_BMSK 0x800000 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR2_CFG_OWNER_SHFT 0x17 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR2_APNSEE_BMSK 0x400000 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR2_APNSEE_SHFT 0x16 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR2_CESDE_BMSK 0x200000 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR2_CESDE_SHFT 0x15 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR2_OPTRW_EN_BMSK 0x100000 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR2_OPTRW_EN_SHFT 0x14 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR2_ATOPC_BMSK 0xf0000 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR2_ATOPC_SHFT 0x10 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR2_REDIRBITS_BMSK 0xf000 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR2_REDIRBITS_SHFT 0xc +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR2_INNERCACHEABLE_BMSK 0x800 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR2_INNERCACHEABLE_SHFT 0xb +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR2_MEMTYPE_BMSK 0x700 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR2_MEMTYPE_SHFT 0x8 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR2_TRANSIENT_BMSK 0x80 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR2_TRANSIENT_SHFT 0x7 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR2_NOALLOCATE_BMSK 0x40 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR2_NOALLOCATE_SHFT 0x6 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR2_WRITETHROUGH_BMSK 0x20 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR2_WRITETHROUGH_SHFT 0x5 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR2_CACHEALLOCATION_BMSK 0x1e +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR2_CACHEALLOCATION_SHFT 0x1 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR2_DIRTYINFO_BMSK 0x1 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR2_DIRTYINFO_SHFT 0x0 + +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGCR0n_ADDR(n) (IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE + 0x00001000 + 0x40 * (n)) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGCR0n_PHYS(n) (IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE_PHYS + 0x00001000 + 0x40 * (n)) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGCR0n_OFFS(n) (IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE_OFFS + 0x00001000 + 0x40 * (n)) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGCR0n_RMSK 0x1 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGCR0n_MAXn 21 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGCR0n_ATTR 0x3 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGCR0n_INI(n) \ + in_dword_masked(HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGCR0n_ADDR(n), HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGCR0n_RMSK) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGCR0n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGCR0n_ADDR(n), mask) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGCR0n_OUTI(n,val) \ + out_dword(HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGCR0n_ADDR(n),val) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGCR0n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGCR0n_ADDR(n),mask,val,HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGCR0n_INI(n)) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGCR0n_RGWOWP_BMSK 0x1 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGCR0n_RGWOWP_SHFT 0x0 + +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGCR1n_ADDR(n) (IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE + 0x00001004 + 0x40 * (n)) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGCR1n_PHYS(n) (IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE_PHYS + 0x00001004 + 0x40 * (n)) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGCR1n_OFFS(n) (IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE_OFFS + 0x00001004 + 0x40 * (n)) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGCR1n_RMSK 0x1 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGCR1n_MAXn 21 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGCR1n_ATTR 0x3 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGCR1n_INI(n) \ + in_dword_masked(HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGCR1n_ADDR(n), HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGCR1n_RMSK) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGCR1n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGCR1n_ADDR(n), mask) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGCR1n_OUTI(n,val) \ + out_dword(HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGCR1n_ADDR(n),val) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGCR1n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGCR1n_ADDR(n),mask,val,HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGCR1n_INI(n)) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGCR1n_RGE_BMSK 0x1 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGCR1n_RGE_SHFT 0x0 + +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGRDRn_ADDR(n) (IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE + 0x00001018 + 0x40 * (n)) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGRDRn_PHYS(n) (IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE_PHYS + 0x00001018 + 0x40 * (n)) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGRDRn_OFFS(n) (IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE_OFFS + 0x00001018 + 0x40 * (n)) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGRDRn_RMSK 0xc000007f +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGRDRn_MAXn 21 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGRDRn_ATTR 0x3 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGRDRn_INI(n) \ + in_dword_masked(HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGRDRn_ADDR(n), HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGRDRn_RMSK) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGRDRn_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGRDRn_ADDR(n), mask) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGRDRn_OUTI(n,val) \ + out_dword(HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGRDRn_ADDR(n),val) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGRDRn_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGRDRn_ADDR(n),mask,val,HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGRDRn_INI(n)) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGRDRn_RDA_S_BMSK 0x80000000 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGRDRn_RDA_S_SHFT 0x1f +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGRDRn_RDA_NS_BMSK 0x40000000 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGRDRn_RDA_NS_SHFT 0x1e +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGRDRn_RDA_QAD_BMSK 0x7f +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGRDRn_RDA_QAD_SHFT 0x0 + +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGWRRn_ADDR(n) (IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE + 0x0000101c + 0x40 * (n)) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGWRRn_PHYS(n) (IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE_PHYS + 0x0000101c + 0x40 * (n)) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGWRRn_OFFS(n) (IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE_OFFS + 0x0000101c + 0x40 * (n)) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGWRRn_RMSK 0xc000007f +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGWRRn_MAXn 21 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGWRRn_ATTR 0x3 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGWRRn_INI(n) \ + in_dword_masked(HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGWRRn_ADDR(n), HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGWRRn_RMSK) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGWRRn_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGWRRn_ADDR(n), mask) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGWRRn_OUTI(n,val) \ + out_dword(HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGWRRn_ADDR(n),val) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGWRRn_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGWRRn_ADDR(n),mask,val,HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGWRRn_INI(n)) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGWRRn_WRA_S_BMSK 0x80000000 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGWRRn_WRA_S_SHFT 0x1f +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGWRRn_WRA_NS_BMSK 0x40000000 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGWRRn_WRA_NS_SHFT 0x1e +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGWRRn_WRA_QAD_BMSK 0x7f +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_RGWRRn_WRA_QAD_SHFT 0x0 + +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_QADRGLn_ADDR(n) (IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE + 0x00001030 + 0x40 * (n)) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_QADRGLn_PHYS(n) (IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE_PHYS + 0x00001030 + 0x40 * (n)) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_QADRGLn_OFFS(n) (IPA_0_IPA_ER_XPU_CFG_XPU4_REG_BASE_OFFS + 0x00001030 + 0x40 * (n)) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_QADRGLn_RMSK 0xc000007f +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_QADRGLn_MAXn 21 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_QADRGLn_ATTR 0x3 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_QADRGLn_INI(n) \ + in_dword_masked(HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_QADRGLn_ADDR(n), HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_QADRGLn_RMSK) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_QADRGLn_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_QADRGLn_ADDR(n), mask) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_QADRGLn_OUTI(n,val) \ + out_dword(HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_QADRGLn_ADDR(n),val) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_QADRGLn_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_QADRGLn_ADDR(n),mask,val,HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_QADRGLn_INI(n)) +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_QADRGLn_RGL_S_BMSK 0x80000000 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_QADRGLn_RGL_S_SHFT 0x1f +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_QADRGLn_RGL_NS_BMSK 0x40000000 +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_QADRGLn_RGL_NS_SHFT 0x1e +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_QADRGLn_RGL_QAD_BMSK 0x7f +#define HWIO_IPA_0_IPA_ER_XPU_CFG_XPU4_QADRGLn_RGL_QAD_SHFT 0x0 + +/*---------------------------------------------------------------------------- + * MODULE: IPA_0_IPA_RA_XPU_CFG_RA_XPU4 + *--------------------------------------------------------------------------*/ + +#define IPA_0_IPA_RA_XPU_CFG_RA_XPU4_REG_BASE (IPA_0_IPA_WRAPPER_BASE + 0x00120000) +#define IPA_0_IPA_RA_XPU_CFG_RA_XPU4_REG_BASE_PHYS (IPA_0_IPA_WRAPPER_BASE_PHYS + 0x00120000) +#define IPA_0_IPA_RA_XPU_CFG_RA_XPU4_REG_BASE_OFFS 0x00120000 + +/*---------------------------------------------------------------------------- + * MODULE: IPA_0_IPA_RA_XPU_CFG_XPU4 + *--------------------------------------------------------------------------*/ + +#define IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE (IPA_0_IPA_WRAPPER_BASE + 0x00120000) +#define IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE_PHYS (IPA_0_IPA_WRAPPER_BASE_PHYS + 0x00120000) +#define IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE_OFFS 0x00120000 + +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_IDR0_ADDR (IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE + 0x00000000) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_IDR0_PHYS (IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE_PHYS + 0x00000000) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_IDR0_OFFS (IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE_OFFS + 0x00000000) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_IDR0_RMSK 0x3ff0073 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_IDR0_ATTR 0x1 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_IDR0_IN \ + in_dword_masked(HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_IDR0_ADDR, HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_IDR0_RMSK) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_IDR0_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_IDR0_ADDR, m) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_IDR0_NRG_BMSK 0x3ff0000 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_IDR0_NRG_SHFT 0x10 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_IDR0_BLED_BMSK 0x40 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_IDR0_BLED_SHFT 0x6 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_IDR0_CLIENT_HALTREQACK_EN_BMSK 0x20 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_IDR0_CLIENT_HALTREQACK_EN_SHFT 0x5 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_IDR0_CLIENT_PIPELINE_EN_BMSK 0x10 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_IDR0_CLIENT_PIPELINE_EN_SHFT 0x4 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_IDR0_XPU_TYPE_BMSK 0x3 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_IDR0_XPU_TYPE_SHFT 0x0 + +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_IDR1_ADDR (IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE + 0x00000004) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_IDR1_PHYS (IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE_PHYS + 0x00000004) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_IDR1_OFFS (IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE_OFFS + 0x00000004) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_IDR1_RMSK 0x3f3f3f3f +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_IDR1_ATTR 0x1 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_IDR1_IN \ + in_dword_masked(HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_IDR1_ADDR, HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_IDR1_RMSK) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_IDR1_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_IDR1_ADDR, m) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_IDR1_CLIENT_ADDR_WIDTH_BMSK 0x3f000000 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_IDR1_CLIENT_ADDR_WIDTH_SHFT 0x18 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_IDR1_CONFIG_ADDR_WIDTH_BMSK 0x3f0000 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_IDR1_CONFIG_ADDR_WIDTH_SHFT 0x10 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_IDR1_ADDR_MSB_BMSK 0x3f00 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_IDR1_ADDR_MSB_SHFT 0x8 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_IDR1_ADDR_LSB_BMSK 0x3f +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_IDR1_ADDR_LSB_SHFT 0x0 + +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_IDR2_ADDR (IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE + 0x00000008) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_IDR2_PHYS (IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE_PHYS + 0x00000008) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_IDR2_OFFS (IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE_OFFS + 0x00000008) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_IDR2_RMSK 0x11f +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_IDR2_ATTR 0x1 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_IDR2_IN \ + in_dword_masked(HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_IDR2_ADDR, HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_IDR2_RMSK) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_IDR2_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_IDR2_ADDR, m) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_IDR2_USELEGACYINTF_BMSK 0x100 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_IDR2_USELEGACYINTF_SHFT 0x8 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_IDR2_NQAD_BMSK 0x1f +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_IDR2_NQAD_SHFT 0x0 + +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_REV_ADDR (IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE + 0x0000000c) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_REV_PHYS (IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE_PHYS + 0x0000000c) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_REV_OFFS (IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE_OFFS + 0x0000000c) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_REV_RMSK 0xffffffff +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_REV_ATTR 0x1 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_REV_IN \ + in_dword_masked(HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_REV_ADDR, HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_REV_RMSK) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_REV_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_REV_ADDR, m) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_REV_MAJOR_BMSK 0xf0000000 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_REV_MAJOR_SHFT 0x1c +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_REV_MINOR_BMSK 0xfff0000 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_REV_MINOR_SHFT 0x10 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_REV_STEP_BMSK 0xffff +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_REV_STEP_SHFT 0x0 + +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_GCR_ADDR (IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE + 0x00000100) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_GCR_PHYS (IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE_PHYS + 0x00000100) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_GCR_OFFS (IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE_OFFS + 0x00000100) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_GCR_RMSK 0x3 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_GCR_ATTR 0x3 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_GCR_IN \ + in_dword_masked(HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_GCR_ADDR, HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_GCR_RMSK) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_GCR_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_GCR_ADDR, m) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_GCR_OUT(v) \ + out_dword(HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_GCR_ADDR,v) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_GCR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_GCR_ADDR,m,v,HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_GCR_IN) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_GCR_DYNAMIC_CLK_EN_BMSK 0x2 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_GCR_DYNAMIC_CLK_EN_SHFT 0x1 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_GCR_APNSPE_BMSK 0x1 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_GCR_APNSPE_SHFT 0x0 + +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RSR_ADDR (IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE + 0x00000104) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RSR_PHYS (IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE_PHYS + 0x00000104) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RSR_OFFS (IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE_OFFS + 0x00000104) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RSR_RMSK 0xffffffff +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RSR_ATTR 0x1 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RSR_IN \ + in_dword_masked(HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RSR_ADDR, HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RSR_RMSK) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RSR_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RSR_ADDR, m) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RSR_NXTFRG_BMSK 0xffff0000 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RSR_NXTFRG_SHFT 0x10 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RSR_NUMFRG_BMSK 0xffff +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RSR_NUMFRG_SHFT 0x0 + +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_CFGERE_ADDR (IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE + 0x00000208) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_CFGERE_PHYS (IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE_PHYS + 0x00000208) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_CFGERE_OFFS (IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE_OFFS + 0x00000208) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_CFGERE_RMSK 0xc000007f +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_CFGERE_ATTR 0x3 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_CFGERE_IN \ + in_dword_masked(HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_CFGERE_ADDR, HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_CFGERE_RMSK) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_CFGERE_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_CFGERE_ADDR, m) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_CFGERE_OUT(v) \ + out_dword(HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_CFGERE_ADDR,v) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_CFGERE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_CFGERE_ADDR,m,v,HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_CFGERE_IN) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_CFGERE_CFGERE_S_BMSK 0x80000000 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_CFGERE_CFGERE_S_SHFT 0x1f +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_CFGERE_CFGERE_NS_BMSK 0x40000000 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_CFGERE_CFGERE_NS_SHFT 0x1e +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_CFGERE_CFGERE_QAD_BMSK 0x7f +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_CFGERE_CFGERE_QAD_SHFT 0x0 + +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_CLERE_ADDR (IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE + 0x0000020c) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_CLERE_PHYS (IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE_PHYS + 0x0000020c) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_CLERE_OFFS (IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE_OFFS + 0x0000020c) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_CLERE_RMSK 0xc000007f +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_CLERE_ATTR 0x3 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_CLERE_IN \ + in_dword_masked(HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_CLERE_ADDR, HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_CLERE_RMSK) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_CLERE_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_CLERE_ADDR, m) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_CLERE_OUT(v) \ + out_dword(HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_CLERE_ADDR,v) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_CLERE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_CLERE_ADDR,m,v,HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_CLERE_IN) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_CLERE_CLERE_S_BMSK 0x80000000 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_CLERE_CLERE_S_SHFT 0x1f +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_CLERE_CLERE_NS_BMSK 0x40000000 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_CLERE_CLERE_NS_SHFT 0x1e +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_CLERE_CLERE_QAD_BMSK 0x7f +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_CLERE_CLERE_QAD_SHFT 0x0 + +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_DBGAR_ADDR (IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE + 0x00000304) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_DBGAR_PHYS (IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE_PHYS + 0x00000304) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_DBGAR_OFFS (IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE_OFFS + 0x00000304) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_DBGAR_RMSK 0xc000007f +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_DBGAR_ATTR 0x3 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_DBGAR_IN \ + in_dword_masked(HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_DBGAR_ADDR, HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_DBGAR_RMSK) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_DBGAR_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_DBGAR_ADDR, m) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_DBGAR_OUT(v) \ + out_dword(HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_DBGAR_ADDR,v) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_DBGAR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_DBGAR_ADDR,m,v,HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_DBGAR_IN) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_DBGAR_DBGA_S_BMSK 0x80000000 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_DBGAR_DBGA_S_SHFT 0x1f +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_DBGAR_DBGA_NS_BMSK 0x40000000 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_DBGAR_DBGA_NS_SHFT 0x1e +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_DBGAR_DBGA_QAD_BMSK 0x7f +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_DBGAR_DBGA_QAD_SHFT 0x0 + +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_ESR_ADDR (IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE + 0x00000500) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_ESR_PHYS (IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE_PHYS + 0x00000500) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_ESR_OFFS (IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE_OFFS + 0x00000500) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_ESR_RMSK 0xf +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_ESR_ATTR 0x3 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_ESR_IN \ + in_dword_masked(HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_ESR_ADDR, HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_ESR_RMSK) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_ESR_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_ESR_ADDR, m) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_ESR_OUT(v) \ + out_dword(HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_ESR_ADDR,v) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_ESR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_ESR_ADDR,m,v,HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_ESR_IN) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_ESR_CLMULTI_BMSK 0x8 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_ESR_CLMULTI_SHFT 0x3 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_ESR_CFGMULTI_BMSK 0x4 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_ESR_CFGMULTI_SHFT 0x2 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_ESR_CLERR_BMSK 0x2 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_ESR_CLERR_SHFT 0x1 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_ESR_CFGERR_BMSK 0x1 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_ESR_CFGERR_SHFT 0x0 + +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNAR0_ADDR (IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE + 0x00000504) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNAR0_PHYS (IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE_PHYS + 0x00000504) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNAR0_OFFS (IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE_OFFS + 0x00000504) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNAR0_RMSK 0xffffffff +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNAR0_ATTR 0x1 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNAR0_IN \ + in_dword_masked(HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNAR0_ADDR, HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNAR0_RMSK) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNAR0_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNAR0_ADDR, m) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNAR0_SYNADDR_BMSK 0xffffffff +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNAR0_SYNADDR_SHFT 0x0 + +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNAR1_ADDR (IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE + 0x00000508) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNAR1_PHYS (IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE_PHYS + 0x00000508) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNAR1_OFFS (IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE_OFFS + 0x00000508) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNAR1_RMSK 0xffffffff +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNAR1_ATTR 0x1 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNAR1_IN \ + in_dword_masked(HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNAR1_ADDR, HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNAR1_RMSK) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNAR1_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNAR1_ADDR, m) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNAR1_SYNADDR_BMSK 0xffffffff +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNAR1_SYNADDR_SHFT 0x0 + +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR0_ADDR (IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE + 0x0000050c) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR0_PHYS (IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE_PHYS + 0x0000050c) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR0_OFFS (IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE_OFFS + 0x0000050c) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR0_RMSK 0xffff9f7f +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR0_ATTR 0x1 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR0_IN \ + in_dword_masked(HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR0_ADDR, HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR0_RMSK) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR0_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR0_ADDR, m) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR0_PH_BMSK 0x80000000 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR0_PH_SHFT 0x1f +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR0_AC_CFG_BMSK 0x40000000 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR0_AC_CFG_SHFT 0x1e +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR0_AC_CL_BMSK 0x20000000 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR0_AC_CL_SHFT 0x1d +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR0_BURSTLEN_BMSK 0x10000000 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR0_BURSTLEN_SHFT 0x1c +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR0_QADERR_BMSK 0x8000000 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR0_QADERR_SHFT 0x1b +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR0_APUDECERR_BMSK 0x4000000 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR0_APUDECERR_SHFT 0x1a +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR0_SSIZE_BMSK 0x3800000 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR0_SSIZE_SHFT 0x17 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR0_LEN_BMSK 0x7f8000 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR0_LEN_SHFT 0xf +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR0_QAD_BMSK 0x1f00 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR0_QAD_SHFT 0x8 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR0_REQ_OPC_BMSK 0x78 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR0_REQ_OPC_SHFT 0x3 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR0_PRIV_BMSK 0x4 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR0_PRIV_SHFT 0x2 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR0_INST_BMSK 0x2 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR0_INST_SHFT 0x1 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR0_XPROTNS_BMSK 0x1 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR0_XPROTNS_SHFT 0x0 + +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR1_ADDR (IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE + 0x00000510) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR1_PHYS (IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE_PHYS + 0x00000510) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR1_OFFS (IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE_OFFS + 0x00000510) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR1_RMSK 0xff07ffff +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR1_ATTR 0x1 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR1_IN \ + in_dword_masked(HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR1_ADDR, HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR1_RMSK) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR1_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR1_ADDR, m) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR1_TID_BMSK 0xff000000 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR1_TID_SHFT 0x18 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR1_TRTYPE_BMSK 0x70000 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR1_TRTYPE_SHFT 0x10 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR1_BID_BMSK 0xe000 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR1_BID_SHFT 0xd +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR1_PID_BMSK 0x1f00 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR1_PID_SHFT 0x8 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR1_MID_BMSK 0xff +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR1_MID_SHFT 0x0 + +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR2_ADDR (IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE + 0x00000514) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR2_PHYS (IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE_PHYS + 0x00000514) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR2_OFFS (IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE_OFFS + 0x00000514) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR2_RMSK 0x3ffffff +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR2_ATTR 0x1 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR2_IN \ + in_dword_masked(HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR2_ADDR, HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR2_RMSK) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR2_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR2_ADDR, m) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR2_APSVIOE_BMSK 0x2000000 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR2_APSVIOE_SHFT 0x19 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR2_SLE_BMSK 0x1000000 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR2_SLE_SHFT 0x18 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR2_CFG_OWNER_BMSK 0x800000 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR2_CFG_OWNER_SHFT 0x17 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR2_APNSEE_BMSK 0x400000 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR2_APNSEE_SHFT 0x16 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR2_CESDE_BMSK 0x200000 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR2_CESDE_SHFT 0x15 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR2_OPTRW_EN_BMSK 0x100000 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR2_OPTRW_EN_SHFT 0x14 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR2_ATOPC_BMSK 0xf0000 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR2_ATOPC_SHFT 0x10 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR2_REDIRBITS_BMSK 0xf000 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR2_REDIRBITS_SHFT 0xc +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR2_INNERCACHEABLE_BMSK 0x800 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR2_INNERCACHEABLE_SHFT 0xb +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR2_MEMTYPE_BMSK 0x700 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR2_MEMTYPE_SHFT 0x8 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR2_TRANSIENT_BMSK 0x80 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR2_TRANSIENT_SHFT 0x7 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR2_NOALLOCATE_BMSK 0x40 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR2_NOALLOCATE_SHFT 0x6 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR2_WRITETHROUGH_BMSK 0x20 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR2_WRITETHROUGH_SHFT 0x5 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR2_CACHEALLOCATION_BMSK 0x1e +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR2_CACHEALLOCATION_SHFT 0x1 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR2_DIRTYINFO_BMSK 0x1 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR2_DIRTYINFO_SHFT 0x0 + +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGCR0n_ADDR(n) (IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE + 0x00001000 + 0x40 * (n)) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGCR0n_PHYS(n) (IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE_PHYS + 0x00001000 + 0x40 * (n)) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGCR0n_OFFS(n) (IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE_OFFS + 0x00001000 + 0x40 * (n)) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGCR0n_RMSK 0x1 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGCR0n_MAXn 21 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGCR0n_ATTR 0x3 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGCR0n_INI(n) \ + in_dword_masked(HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGCR0n_ADDR(n), HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGCR0n_RMSK) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGCR0n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGCR0n_ADDR(n), mask) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGCR0n_OUTI(n,val) \ + out_dword(HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGCR0n_ADDR(n),val) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGCR0n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGCR0n_ADDR(n),mask,val,HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGCR0n_INI(n)) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGCR0n_RGWOWP_BMSK 0x1 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGCR0n_RGWOWP_SHFT 0x0 + +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGCR1n_ADDR(n) (IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE + 0x00001004 + 0x40 * (n)) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGCR1n_PHYS(n) (IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE_PHYS + 0x00001004 + 0x40 * (n)) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGCR1n_OFFS(n) (IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE_OFFS + 0x00001004 + 0x40 * (n)) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGCR1n_RMSK 0x1 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGCR1n_MAXn 21 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGCR1n_ATTR 0x3 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGCR1n_INI(n) \ + in_dword_masked(HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGCR1n_ADDR(n), HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGCR1n_RMSK) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGCR1n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGCR1n_ADDR(n), mask) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGCR1n_OUTI(n,val) \ + out_dword(HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGCR1n_ADDR(n),val) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGCR1n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGCR1n_ADDR(n),mask,val,HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGCR1n_INI(n)) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGCR1n_RGE_BMSK 0x1 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGCR1n_RGE_SHFT 0x0 + +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGRDRn_ADDR(n) (IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE + 0x00001018 + 0x40 * (n)) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGRDRn_PHYS(n) (IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE_PHYS + 0x00001018 + 0x40 * (n)) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGRDRn_OFFS(n) (IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE_OFFS + 0x00001018 + 0x40 * (n)) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGRDRn_RMSK 0xc000007f +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGRDRn_MAXn 21 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGRDRn_ATTR 0x3 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGRDRn_INI(n) \ + in_dword_masked(HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGRDRn_ADDR(n), HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGRDRn_RMSK) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGRDRn_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGRDRn_ADDR(n), mask) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGRDRn_OUTI(n,val) \ + out_dword(HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGRDRn_ADDR(n),val) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGRDRn_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGRDRn_ADDR(n),mask,val,HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGRDRn_INI(n)) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGRDRn_RDA_S_BMSK 0x80000000 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGRDRn_RDA_S_SHFT 0x1f +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGRDRn_RDA_NS_BMSK 0x40000000 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGRDRn_RDA_NS_SHFT 0x1e +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGRDRn_RDA_QAD_BMSK 0x7f +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGRDRn_RDA_QAD_SHFT 0x0 + +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGWRRn_ADDR(n) (IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE + 0x0000101c + 0x40 * (n)) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGWRRn_PHYS(n) (IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE_PHYS + 0x0000101c + 0x40 * (n)) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGWRRn_OFFS(n) (IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE_OFFS + 0x0000101c + 0x40 * (n)) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGWRRn_RMSK 0xc000007f +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGWRRn_MAXn 21 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGWRRn_ATTR 0x3 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGWRRn_INI(n) \ + in_dword_masked(HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGWRRn_ADDR(n), HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGWRRn_RMSK) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGWRRn_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGWRRn_ADDR(n), mask) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGWRRn_OUTI(n,val) \ + out_dword(HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGWRRn_ADDR(n),val) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGWRRn_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGWRRn_ADDR(n),mask,val,HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGWRRn_INI(n)) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGWRRn_WRA_S_BMSK 0x80000000 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGWRRn_WRA_S_SHFT 0x1f +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGWRRn_WRA_NS_BMSK 0x40000000 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGWRRn_WRA_NS_SHFT 0x1e +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGWRRn_WRA_QAD_BMSK 0x7f +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_RGWRRn_WRA_QAD_SHFT 0x0 + +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_QADRGLn_ADDR(n) (IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE + 0x00001030 + 0x40 * (n)) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_QADRGLn_PHYS(n) (IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE_PHYS + 0x00001030 + 0x40 * (n)) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_QADRGLn_OFFS(n) (IPA_0_IPA_RA_XPU_CFG_XPU4_REG_BASE_OFFS + 0x00001030 + 0x40 * (n)) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_QADRGLn_RMSK 0xc000007f +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_QADRGLn_MAXn 21 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_QADRGLn_ATTR 0x3 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_QADRGLn_INI(n) \ + in_dword_masked(HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_QADRGLn_ADDR(n), HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_QADRGLn_RMSK) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_QADRGLn_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_QADRGLn_ADDR(n), mask) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_QADRGLn_OUTI(n,val) \ + out_dword(HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_QADRGLn_ADDR(n),val) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_QADRGLn_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_QADRGLn_ADDR(n),mask,val,HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_QADRGLn_INI(n)) +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_QADRGLn_RGL_S_BMSK 0x80000000 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_QADRGLn_RGL_S_SHFT 0x1f +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_QADRGLn_RGL_NS_BMSK 0x40000000 +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_QADRGLn_RGL_NS_SHFT 0x1e +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_QADRGLn_RGL_QAD_BMSK 0x7f +#define HWIO_IPA_0_IPA_RA_XPU_CFG_XPU4_QADRGLn_RGL_QAD_SHFT 0x0 + +/*---------------------------------------------------------------------------- + * MODULE: IPA_0_IPA_RA_XPU_SB_IPA_RA_XPU4_SB + *--------------------------------------------------------------------------*/ + +#define IPA_0_IPA_RA_XPU_SB_IPA_RA_XPU4_SB_REG_BASE (IPA_0_IPA_WRAPPER_BASE + 0x00124000) +#define IPA_0_IPA_RA_XPU_SB_IPA_RA_XPU4_SB_REG_BASE_PHYS (IPA_0_IPA_WRAPPER_BASE_PHYS + 0x00124000) +#define IPA_0_IPA_RA_XPU_SB_IPA_RA_XPU4_SB_REG_BASE_OFFS 0x00124000 + +#define HWIO_IPA_0_IPA_RA_XPU_SB_RA_XPU_SIDEBAND_STATIC_SLE_ADDR (IPA_0_IPA_RA_XPU_SB_IPA_RA_XPU4_SB_REG_BASE + 0x00000000) +#define HWIO_IPA_0_IPA_RA_XPU_SB_RA_XPU_SIDEBAND_STATIC_SLE_PHYS (IPA_0_IPA_RA_XPU_SB_IPA_RA_XPU4_SB_REG_BASE_PHYS + 0x00000000) +#define HWIO_IPA_0_IPA_RA_XPU_SB_RA_XPU_SIDEBAND_STATIC_SLE_OFFS (IPA_0_IPA_RA_XPU_SB_IPA_RA_XPU4_SB_REG_BASE_OFFS + 0x00000000) +#define HWIO_IPA_0_IPA_RA_XPU_SB_RA_XPU_SIDEBAND_STATIC_SLE_RMSK 0x1 +#define HWIO_IPA_0_IPA_RA_XPU_SB_RA_XPU_SIDEBAND_STATIC_SLE_ATTR 0x3 +#define HWIO_IPA_0_IPA_RA_XPU_SB_RA_XPU_SIDEBAND_STATIC_SLE_IN \ + in_dword_masked(HWIO_IPA_0_IPA_RA_XPU_SB_RA_XPU_SIDEBAND_STATIC_SLE_ADDR, HWIO_IPA_0_IPA_RA_XPU_SB_RA_XPU_SIDEBAND_STATIC_SLE_RMSK) +#define HWIO_IPA_0_IPA_RA_XPU_SB_RA_XPU_SIDEBAND_STATIC_SLE_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_RA_XPU_SB_RA_XPU_SIDEBAND_STATIC_SLE_ADDR, m) +#define HWIO_IPA_0_IPA_RA_XPU_SB_RA_XPU_SIDEBAND_STATIC_SLE_OUT(v) \ + out_dword(HWIO_IPA_0_IPA_RA_XPU_SB_RA_XPU_SIDEBAND_STATIC_SLE_ADDR,v) +#define HWIO_IPA_0_IPA_RA_XPU_SB_RA_XPU_SIDEBAND_STATIC_SLE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_IPA_RA_XPU_SB_RA_XPU_SIDEBAND_STATIC_SLE_ADDR,m,v,HWIO_IPA_0_IPA_RA_XPU_SB_RA_XPU_SIDEBAND_STATIC_SLE_IN) +#define HWIO_IPA_0_IPA_RA_XPU_SB_RA_XPU_SIDEBAND_STATIC_SLE_SET_BMSK 0x1 +#define HWIO_IPA_0_IPA_RA_XPU_SB_RA_XPU_SIDEBAND_STATIC_SLE_SET_SHFT 0x0 + +#define HWIO_IPA_0_IPA_RA_XPU_SB_RA_XPU_SIDEBAND_STATIC_ADDR (IPA_0_IPA_RA_XPU_SB_IPA_RA_XPU4_SB_REG_BASE + 0x00000004) +#define HWIO_IPA_0_IPA_RA_XPU_SB_RA_XPU_SIDEBAND_STATIC_PHYS (IPA_0_IPA_RA_XPU_SB_IPA_RA_XPU4_SB_REG_BASE_PHYS + 0x00000004) +#define HWIO_IPA_0_IPA_RA_XPU_SB_RA_XPU_SIDEBAND_STATIC_OFFS (IPA_0_IPA_RA_XPU_SB_IPA_RA_XPU4_SB_REG_BASE_OFFS + 0x00000004) +#define HWIO_IPA_0_IPA_RA_XPU_SB_RA_XPU_SIDEBAND_STATIC_RMSK 0x2f +#define HWIO_IPA_0_IPA_RA_XPU_SB_RA_XPU_SIDEBAND_STATIC_ATTR 0x3 +#define HWIO_IPA_0_IPA_RA_XPU_SB_RA_XPU_SIDEBAND_STATIC_IN \ + in_dword_masked(HWIO_IPA_0_IPA_RA_XPU_SB_RA_XPU_SIDEBAND_STATIC_ADDR, HWIO_IPA_0_IPA_RA_XPU_SB_RA_XPU_SIDEBAND_STATIC_RMSK) +#define HWIO_IPA_0_IPA_RA_XPU_SB_RA_XPU_SIDEBAND_STATIC_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_RA_XPU_SB_RA_XPU_SIDEBAND_STATIC_ADDR, m) +#define HWIO_IPA_0_IPA_RA_XPU_SB_RA_XPU_SIDEBAND_STATIC_OUT(v) \ + out_dword(HWIO_IPA_0_IPA_RA_XPU_SB_RA_XPU_SIDEBAND_STATIC_ADDR,v) +#define HWIO_IPA_0_IPA_RA_XPU_SB_RA_XPU_SIDEBAND_STATIC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_IPA_RA_XPU_SB_RA_XPU_SIDEBAND_STATIC_ADDR,m,v,HWIO_IPA_0_IPA_RA_XPU_SB_RA_XPU_SIDEBAND_STATIC_IN) +#define HWIO_IPA_0_IPA_RA_XPU_SB_RA_XPU_SIDEBAND_STATIC_APSVIOE_BMSK 0x20 +#define HWIO_IPA_0_IPA_RA_XPU_SB_RA_XPU_SIDEBAND_STATIC_APSVIOE_SHFT 0x5 +#define HWIO_IPA_0_IPA_RA_XPU_SB_RA_XPU_SIDEBAND_STATIC_CMOCESDE_BMSK 0x8 +#define HWIO_IPA_0_IPA_RA_XPU_SB_RA_XPU_SIDEBAND_STATIC_CMOCESDE_SHFT 0x3 +#define HWIO_IPA_0_IPA_RA_XPU_SB_RA_XPU_SIDEBAND_STATIC_OPTRW_EN_BMSK 0x4 +#define HWIO_IPA_0_IPA_RA_XPU_SB_RA_XPU_SIDEBAND_STATIC_OPTRW_EN_SHFT 0x2 +#define HWIO_IPA_0_IPA_RA_XPU_SB_RA_XPU_SIDEBAND_STATIC_APNSEE_BMSK 0x2 +#define HWIO_IPA_0_IPA_RA_XPU_SB_RA_XPU_SIDEBAND_STATIC_APNSEE_SHFT 0x1 +#define HWIO_IPA_0_IPA_RA_XPU_SB_RA_XPU_SIDEBAND_STATIC_CFGOWNS_BMSK 0x1 +#define HWIO_IPA_0_IPA_RA_XPU_SB_RA_XPU_SIDEBAND_STATIC_CFGOWNS_SHFT 0x0 + +#define HWIO_IPA_0_IPA_RA_XPU_SB_RA_XPU_SIDEBAND_STATIC_SLE_WAS_WRITTEN_ADDR (IPA_0_IPA_RA_XPU_SB_IPA_RA_XPU4_SB_REG_BASE + 0x00000008) +#define HWIO_IPA_0_IPA_RA_XPU_SB_RA_XPU_SIDEBAND_STATIC_SLE_WAS_WRITTEN_PHYS (IPA_0_IPA_RA_XPU_SB_IPA_RA_XPU4_SB_REG_BASE_PHYS + 0x00000008) +#define HWIO_IPA_0_IPA_RA_XPU_SB_RA_XPU_SIDEBAND_STATIC_SLE_WAS_WRITTEN_OFFS (IPA_0_IPA_RA_XPU_SB_IPA_RA_XPU4_SB_REG_BASE_OFFS + 0x00000008) +#define HWIO_IPA_0_IPA_RA_XPU_SB_RA_XPU_SIDEBAND_STATIC_SLE_WAS_WRITTEN_RMSK 0x1 +#define HWIO_IPA_0_IPA_RA_XPU_SB_RA_XPU_SIDEBAND_STATIC_SLE_WAS_WRITTEN_ATTR 0x1 +#define HWIO_IPA_0_IPA_RA_XPU_SB_RA_XPU_SIDEBAND_STATIC_SLE_WAS_WRITTEN_IN \ + in_dword_masked(HWIO_IPA_0_IPA_RA_XPU_SB_RA_XPU_SIDEBAND_STATIC_SLE_WAS_WRITTEN_ADDR, HWIO_IPA_0_IPA_RA_XPU_SB_RA_XPU_SIDEBAND_STATIC_SLE_WAS_WRITTEN_RMSK) +#define HWIO_IPA_0_IPA_RA_XPU_SB_RA_XPU_SIDEBAND_STATIC_SLE_WAS_WRITTEN_INM(m) \ + in_dword_masked(HWIO_IPA_0_IPA_RA_XPU_SB_RA_XPU_SIDEBAND_STATIC_SLE_WAS_WRITTEN_ADDR, m) +#define HWIO_IPA_0_IPA_RA_XPU_SB_RA_XPU_SIDEBAND_STATIC_SLE_WAS_WRITTEN_VAL_BMSK 0x1 +#define HWIO_IPA_0_IPA_RA_XPU_SB_RA_XPU_SIDEBAND_STATIC_SLE_WAS_WRITTEN_VAL_SHFT 0x0 + +/*---------------------------------------------------------------------------- + * MODULE: IPA_0_GSI_TOP + *--------------------------------------------------------------------------*/ + +#define IPA_0_GSI_TOP_REG_BASE (IPA_0_IPA_WRAPPER_BASE + 0x00004000) +#define IPA_0_GSI_TOP_REG_BASE_PHYS (IPA_0_IPA_WRAPPER_BASE_PHYS + 0x00004000) +#define IPA_0_GSI_TOP_REG_BASE_OFFS 0x00004000 + +/*---------------------------------------------------------------------------- + * MODULE: IPA_0_GSI_TOP_GSI + *--------------------------------------------------------------------------*/ + +#define IPA_0_GSI_TOP_GSI_REG_BASE (IPA_0_IPA_WRAPPER_BASE + 0x00004000) +#define IPA_0_GSI_TOP_GSI_REG_BASE_PHYS (IPA_0_IPA_WRAPPER_BASE_PHYS + 0x00004000) +#define IPA_0_GSI_TOP_GSI_REG_BASE_OFFS 0x00004000 + +#define HWIO_IPA_0_GSI_TOP_GSI_CFG_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00000000) +#define HWIO_IPA_0_GSI_TOP_GSI_CFG_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000000) +#define HWIO_IPA_0_GSI_TOP_GSI_CFG_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000000) +#define HWIO_IPA_0_GSI_TOP_GSI_CFG_RMSK 0xf3f +#define HWIO_IPA_0_GSI_TOP_GSI_CFG_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_CFG_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_CFG_ADDR, HWIO_IPA_0_GSI_TOP_GSI_CFG_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_CFG_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_CFG_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_CFG_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_GSI_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_GSI_CFG_ADDR,m,v,HWIO_IPA_0_GSI_TOP_GSI_CFG_IN) +#define HWIO_IPA_0_GSI_TOP_GSI_CFG_SLEEP_CLK_DIV_BMSK 0xf00 +#define HWIO_IPA_0_GSI_TOP_GSI_CFG_SLEEP_CLK_DIV_SHFT 0x8 +#define HWIO_IPA_0_GSI_TOP_GSI_CFG_BP_MTRIX_DISABLE_BMSK 0x20 +#define HWIO_IPA_0_GSI_TOP_GSI_CFG_BP_MTRIX_DISABLE_SHFT 0x5 +#define HWIO_IPA_0_GSI_TOP_GSI_CFG_GSI_PWR_CLPS_BMSK 0x10 +#define HWIO_IPA_0_GSI_TOP_GSI_CFG_GSI_PWR_CLPS_SHFT 0x4 +#define HWIO_IPA_0_GSI_TOP_GSI_CFG_UC_IS_MCS_BMSK 0x8 +#define HWIO_IPA_0_GSI_TOP_GSI_CFG_UC_IS_MCS_SHFT 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_CFG_DOUBLE_MCS_CLK_FREQ_BMSK 0x4 +#define HWIO_IPA_0_GSI_TOP_GSI_CFG_DOUBLE_MCS_CLK_FREQ_SHFT 0x2 +#define HWIO_IPA_0_GSI_TOP_GSI_CFG_MCS_ENABLE_BMSK 0x2 +#define HWIO_IPA_0_GSI_TOP_GSI_CFG_MCS_ENABLE_SHFT 0x1 +#define HWIO_IPA_0_GSI_TOP_GSI_CFG_GSI_ENABLE_BMSK 0x1 +#define HWIO_IPA_0_GSI_TOP_GSI_CFG_GSI_ENABLE_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_MANAGER_MCS_CODE_VER_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00000008) +#define HWIO_IPA_0_GSI_TOP_GSI_MANAGER_MCS_CODE_VER_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000008) +#define HWIO_IPA_0_GSI_TOP_GSI_MANAGER_MCS_CODE_VER_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000008) +#define HWIO_IPA_0_GSI_TOP_GSI_MANAGER_MCS_CODE_VER_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_GSI_MANAGER_MCS_CODE_VER_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_MANAGER_MCS_CODE_VER_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_MANAGER_MCS_CODE_VER_ADDR, HWIO_IPA_0_GSI_TOP_GSI_MANAGER_MCS_CODE_VER_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_MANAGER_MCS_CODE_VER_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_MANAGER_MCS_CODE_VER_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_MANAGER_MCS_CODE_VER_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_MANAGER_MCS_CODE_VER_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_GSI_MANAGER_MCS_CODE_VER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_GSI_MANAGER_MCS_CODE_VER_ADDR,m,v,HWIO_IPA_0_GSI_TOP_GSI_MANAGER_MCS_CODE_VER_IN) +#define HWIO_IPA_0_GSI_TOP_GSI_MANAGER_MCS_CODE_VER_VER_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_GSI_MANAGER_MCS_CODE_VER_VER_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_ZEROS_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00000010) +#define HWIO_IPA_0_GSI_TOP_GSI_ZEROS_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000010) +#define HWIO_IPA_0_GSI_TOP_GSI_ZEROS_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000010) +#define HWIO_IPA_0_GSI_TOP_GSI_ZEROS_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_GSI_ZEROS_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_GSI_ZEROS_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_ZEROS_ADDR, HWIO_IPA_0_GSI_TOP_GSI_ZEROS_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_ZEROS_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_ZEROS_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_ZEROS_ZEROS_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_GSI_ZEROS_ZEROS_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_PERIPH_BASE_ADDR_LSB_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00000018) +#define HWIO_IPA_0_GSI_TOP_GSI_PERIPH_BASE_ADDR_LSB_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000018) +#define HWIO_IPA_0_GSI_TOP_GSI_PERIPH_BASE_ADDR_LSB_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000018) +#define HWIO_IPA_0_GSI_TOP_GSI_PERIPH_BASE_ADDR_LSB_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_GSI_PERIPH_BASE_ADDR_LSB_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_PERIPH_BASE_ADDR_LSB_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_PERIPH_BASE_ADDR_LSB_ADDR, HWIO_IPA_0_GSI_TOP_GSI_PERIPH_BASE_ADDR_LSB_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_PERIPH_BASE_ADDR_LSB_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_PERIPH_BASE_ADDR_LSB_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_PERIPH_BASE_ADDR_LSB_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_PERIPH_BASE_ADDR_LSB_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_GSI_PERIPH_BASE_ADDR_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_GSI_PERIPH_BASE_ADDR_LSB_ADDR,m,v,HWIO_IPA_0_GSI_TOP_GSI_PERIPH_BASE_ADDR_LSB_IN) +#define HWIO_IPA_0_GSI_TOP_GSI_PERIPH_BASE_ADDR_LSB_BASE_ADDR_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_GSI_PERIPH_BASE_ADDR_LSB_BASE_ADDR_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_PERIPH_BASE_ADDR_MSB_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x0000001c) +#define HWIO_IPA_0_GSI_TOP_GSI_PERIPH_BASE_ADDR_MSB_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000001c) +#define HWIO_IPA_0_GSI_TOP_GSI_PERIPH_BASE_ADDR_MSB_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000001c) +#define HWIO_IPA_0_GSI_TOP_GSI_PERIPH_BASE_ADDR_MSB_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_GSI_PERIPH_BASE_ADDR_MSB_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_PERIPH_BASE_ADDR_MSB_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_PERIPH_BASE_ADDR_MSB_ADDR, HWIO_IPA_0_GSI_TOP_GSI_PERIPH_BASE_ADDR_MSB_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_PERIPH_BASE_ADDR_MSB_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_PERIPH_BASE_ADDR_MSB_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_PERIPH_BASE_ADDR_MSB_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_PERIPH_BASE_ADDR_MSB_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_GSI_PERIPH_BASE_ADDR_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_GSI_PERIPH_BASE_ADDR_MSB_ADDR,m,v,HWIO_IPA_0_GSI_TOP_GSI_PERIPH_BASE_ADDR_MSB_IN) +#define HWIO_IPA_0_GSI_TOP_GSI_PERIPH_BASE_ADDR_MSB_BASE_ADDR_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_GSI_PERIPH_BASE_ADDR_MSB_BASE_ADDR_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_CGC_CTRL_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00000020) +#define HWIO_IPA_0_GSI_TOP_GSI_CGC_CTRL_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000020) +#define HWIO_IPA_0_GSI_TOP_GSI_CGC_CTRL_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000020) +#define HWIO_IPA_0_GSI_TOP_GSI_CGC_CTRL_RMSK 0xffff +#define HWIO_IPA_0_GSI_TOP_GSI_CGC_CTRL_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_CGC_CTRL_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_CGC_CTRL_ADDR, HWIO_IPA_0_GSI_TOP_GSI_CGC_CTRL_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_CGC_CTRL_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_CGC_CTRL_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_CGC_CTRL_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_CGC_CTRL_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_GSI_CGC_CTRL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_GSI_CGC_CTRL_ADDR,m,v,HWIO_IPA_0_GSI_TOP_GSI_CGC_CTRL_IN) +#define HWIO_IPA_0_GSI_TOP_GSI_CGC_CTRL_REGION_16_HW_CGC_EN_BMSK 0x8000 +#define HWIO_IPA_0_GSI_TOP_GSI_CGC_CTRL_REGION_16_HW_CGC_EN_SHFT 0xf +#define HWIO_IPA_0_GSI_TOP_GSI_CGC_CTRL_REGION_15_HW_CGC_EN_BMSK 0x4000 +#define HWIO_IPA_0_GSI_TOP_GSI_CGC_CTRL_REGION_15_HW_CGC_EN_SHFT 0xe +#define HWIO_IPA_0_GSI_TOP_GSI_CGC_CTRL_REGION_14_HW_CGC_EN_BMSK 0x2000 +#define HWIO_IPA_0_GSI_TOP_GSI_CGC_CTRL_REGION_14_HW_CGC_EN_SHFT 0xd +#define HWIO_IPA_0_GSI_TOP_GSI_CGC_CTRL_REGION_13_HW_CGC_EN_BMSK 0x1000 +#define HWIO_IPA_0_GSI_TOP_GSI_CGC_CTRL_REGION_13_HW_CGC_EN_SHFT 0xc +#define HWIO_IPA_0_GSI_TOP_GSI_CGC_CTRL_REGION_12_HW_CGC_EN_BMSK 0x800 +#define HWIO_IPA_0_GSI_TOP_GSI_CGC_CTRL_REGION_12_HW_CGC_EN_SHFT 0xb +#define HWIO_IPA_0_GSI_TOP_GSI_CGC_CTRL_REGION_11_HW_CGC_EN_BMSK 0x400 +#define HWIO_IPA_0_GSI_TOP_GSI_CGC_CTRL_REGION_11_HW_CGC_EN_SHFT 0xa +#define HWIO_IPA_0_GSI_TOP_GSI_CGC_CTRL_REGION_10_HW_CGC_EN_BMSK 0x200 +#define HWIO_IPA_0_GSI_TOP_GSI_CGC_CTRL_REGION_10_HW_CGC_EN_SHFT 0x9 +#define HWIO_IPA_0_GSI_TOP_GSI_CGC_CTRL_REGION_9_HW_CGC_EN_BMSK 0x100 +#define HWIO_IPA_0_GSI_TOP_GSI_CGC_CTRL_REGION_9_HW_CGC_EN_SHFT 0x8 +#define HWIO_IPA_0_GSI_TOP_GSI_CGC_CTRL_REGION_8_HW_CGC_EN_BMSK 0x80 +#define HWIO_IPA_0_GSI_TOP_GSI_CGC_CTRL_REGION_8_HW_CGC_EN_SHFT 0x7 +#define HWIO_IPA_0_GSI_TOP_GSI_CGC_CTRL_REGION_7_HW_CGC_EN_BMSK 0x40 +#define HWIO_IPA_0_GSI_TOP_GSI_CGC_CTRL_REGION_7_HW_CGC_EN_SHFT 0x6 +#define HWIO_IPA_0_GSI_TOP_GSI_CGC_CTRL_REGION_6_HW_CGC_EN_BMSK 0x20 +#define HWIO_IPA_0_GSI_TOP_GSI_CGC_CTRL_REGION_6_HW_CGC_EN_SHFT 0x5 +#define HWIO_IPA_0_GSI_TOP_GSI_CGC_CTRL_REGION_5_HW_CGC_EN_BMSK 0x10 +#define HWIO_IPA_0_GSI_TOP_GSI_CGC_CTRL_REGION_5_HW_CGC_EN_SHFT 0x4 +#define HWIO_IPA_0_GSI_TOP_GSI_CGC_CTRL_REGION_4_HW_CGC_EN_BMSK 0x8 +#define HWIO_IPA_0_GSI_TOP_GSI_CGC_CTRL_REGION_4_HW_CGC_EN_SHFT 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_CGC_CTRL_REGION_3_HW_CGC_EN_BMSK 0x4 +#define HWIO_IPA_0_GSI_TOP_GSI_CGC_CTRL_REGION_3_HW_CGC_EN_SHFT 0x2 +#define HWIO_IPA_0_GSI_TOP_GSI_CGC_CTRL_REGION_2_HW_CGC_EN_BMSK 0x2 +#define HWIO_IPA_0_GSI_TOP_GSI_CGC_CTRL_REGION_2_HW_CGC_EN_SHFT 0x1 +#define HWIO_IPA_0_GSI_TOP_GSI_CGC_CTRL_REGION_1_HW_CGC_EN_BMSK 0x1 +#define HWIO_IPA_0_GSI_TOP_GSI_CGC_CTRL_REGION_1_HW_CGC_EN_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_MOQA_CFG_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00000030) +#define HWIO_IPA_0_GSI_TOP_GSI_MOQA_CFG_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000030) +#define HWIO_IPA_0_GSI_TOP_GSI_MOQA_CFG_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000030) +#define HWIO_IPA_0_GSI_TOP_GSI_MOQA_CFG_RMSK 0xffffff +#define HWIO_IPA_0_GSI_TOP_GSI_MOQA_CFG_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_MOQA_CFG_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_MOQA_CFG_ADDR, HWIO_IPA_0_GSI_TOP_GSI_MOQA_CFG_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_MOQA_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_MOQA_CFG_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_MOQA_CFG_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_MOQA_CFG_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_GSI_MOQA_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_GSI_MOQA_CFG_ADDR,m,v,HWIO_IPA_0_GSI_TOP_GSI_MOQA_CFG_IN) +#define HWIO_IPA_0_GSI_TOP_GSI_MOQA_CFG_CLIENT_OOWR_BMSK 0xff0000 +#define HWIO_IPA_0_GSI_TOP_GSI_MOQA_CFG_CLIENT_OOWR_SHFT 0x10 +#define HWIO_IPA_0_GSI_TOP_GSI_MOQA_CFG_CLIENT_OORD_BMSK 0xff00 +#define HWIO_IPA_0_GSI_TOP_GSI_MOQA_CFG_CLIENT_OORD_SHFT 0x8 +#define HWIO_IPA_0_GSI_TOP_GSI_MOQA_CFG_CLIENT_REQ_PRIO_BMSK 0xff +#define HWIO_IPA_0_GSI_TOP_GSI_MOQA_CFG_CLIENT_REQ_PRIO_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_REE_CFG_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00000038) +#define HWIO_IPA_0_GSI_TOP_GSI_REE_CFG_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000038) +#define HWIO_IPA_0_GSI_TOP_GSI_REE_CFG_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000038) +#define HWIO_IPA_0_GSI_TOP_GSI_REE_CFG_RMSK 0xff03 +#define HWIO_IPA_0_GSI_TOP_GSI_REE_CFG_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_REE_CFG_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_REE_CFG_ADDR, HWIO_IPA_0_GSI_TOP_GSI_REE_CFG_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_REE_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_REE_CFG_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_REE_CFG_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_REE_CFG_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_GSI_REE_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_GSI_REE_CFG_ADDR,m,v,HWIO_IPA_0_GSI_TOP_GSI_REE_CFG_IN) +#define HWIO_IPA_0_GSI_TOP_GSI_REE_CFG_MAX_BURST_SIZE_BMSK 0xff00 +#define HWIO_IPA_0_GSI_TOP_GSI_REE_CFG_MAX_BURST_SIZE_SHFT 0x8 +#define HWIO_IPA_0_GSI_TOP_GSI_REE_CFG_CHANNEL_EMPTY_INT_ENABLE_BMSK 0x2 +#define HWIO_IPA_0_GSI_TOP_GSI_REE_CFG_CHANNEL_EMPTY_INT_ENABLE_SHFT 0x1 +#define HWIO_IPA_0_GSI_TOP_GSI_REE_CFG_MOVE_TO_ESC_CLR_MODE_TRSH_BMSK 0x1 +#define HWIO_IPA_0_GSI_TOP_GSI_REE_CFG_MOVE_TO_ESC_CLR_MODE_TRSH_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_PERIPH_PENDING_k_ADDR(k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00000060 + 0x4 * (k)) +#define HWIO_IPA_0_GSI_TOP_GSI_PERIPH_PENDING_k_PHYS(k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000060 + 0x4 * (k)) +#define HWIO_IPA_0_GSI_TOP_GSI_PERIPH_PENDING_k_OFFS(k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000060 + 0x4 * (k)) +#define HWIO_IPA_0_GSI_TOP_GSI_PERIPH_PENDING_k_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_GSI_PERIPH_PENDING_k_MAXk 1 +#define HWIO_IPA_0_GSI_TOP_GSI_PERIPH_PENDING_k_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_GSI_PERIPH_PENDING_k_INI(k) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_PERIPH_PENDING_k_ADDR(k), HWIO_IPA_0_GSI_TOP_GSI_PERIPH_PENDING_k_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_PERIPH_PENDING_k_INMI(k,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_PERIPH_PENDING_k_ADDR(k), mask) +#define HWIO_IPA_0_GSI_TOP_GSI_PERIPH_PENDING_k_CHID_BIT_MAP_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_GSI_PERIPH_PENDING_k_CHID_BIT_MAP_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_MSI_CACHEATTR_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00000080) +#define HWIO_IPA_0_GSI_TOP_GSI_MSI_CACHEATTR_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000080) +#define HWIO_IPA_0_GSI_TOP_GSI_MSI_CACHEATTR_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000080) +#define HWIO_IPA_0_GSI_TOP_GSI_MSI_CACHEATTR_RMSK 0x3f +#define HWIO_IPA_0_GSI_TOP_GSI_MSI_CACHEATTR_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_MSI_CACHEATTR_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_MSI_CACHEATTR_ADDR, HWIO_IPA_0_GSI_TOP_GSI_MSI_CACHEATTR_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_MSI_CACHEATTR_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_MSI_CACHEATTR_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_MSI_CACHEATTR_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_MSI_CACHEATTR_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_GSI_MSI_CACHEATTR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_GSI_MSI_CACHEATTR_ADDR,m,v,HWIO_IPA_0_GSI_TOP_GSI_MSI_CACHEATTR_IN) +#define HWIO_IPA_0_GSI_TOP_GSI_MSI_CACHEATTR_AREQPRIORITY_BMSK 0x30 +#define HWIO_IPA_0_GSI_TOP_GSI_MSI_CACHEATTR_AREQPRIORITY_SHFT 0x4 +#define HWIO_IPA_0_GSI_TOP_GSI_MSI_CACHEATTR_ATRANSIENT_BMSK 0x8 +#define HWIO_IPA_0_GSI_TOP_GSI_MSI_CACHEATTR_ATRANSIENT_SHFT 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_MSI_CACHEATTR_ANOALLOCATE_BMSK 0x4 +#define HWIO_IPA_0_GSI_TOP_GSI_MSI_CACHEATTR_ANOALLOCATE_SHFT 0x2 +#define HWIO_IPA_0_GSI_TOP_GSI_MSI_CACHEATTR_AINNERSHARED_BMSK 0x2 +#define HWIO_IPA_0_GSI_TOP_GSI_MSI_CACHEATTR_AINNERSHARED_SHFT 0x1 +#define HWIO_IPA_0_GSI_TOP_GSI_MSI_CACHEATTR_ASHARED_BMSK 0x1 +#define HWIO_IPA_0_GSI_TOP_GSI_MSI_CACHEATTR_ASHARED_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_EVENT_CACHEATTR_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00000084) +#define HWIO_IPA_0_GSI_TOP_GSI_EVENT_CACHEATTR_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000084) +#define HWIO_IPA_0_GSI_TOP_GSI_EVENT_CACHEATTR_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000084) +#define HWIO_IPA_0_GSI_TOP_GSI_EVENT_CACHEATTR_RMSK 0x3f +#define HWIO_IPA_0_GSI_TOP_GSI_EVENT_CACHEATTR_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_EVENT_CACHEATTR_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_EVENT_CACHEATTR_ADDR, HWIO_IPA_0_GSI_TOP_GSI_EVENT_CACHEATTR_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_EVENT_CACHEATTR_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_EVENT_CACHEATTR_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_EVENT_CACHEATTR_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_EVENT_CACHEATTR_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_GSI_EVENT_CACHEATTR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_GSI_EVENT_CACHEATTR_ADDR,m,v,HWIO_IPA_0_GSI_TOP_GSI_EVENT_CACHEATTR_IN) +#define HWIO_IPA_0_GSI_TOP_GSI_EVENT_CACHEATTR_AREQPRIORITY_BMSK 0x30 +#define HWIO_IPA_0_GSI_TOP_GSI_EVENT_CACHEATTR_AREQPRIORITY_SHFT 0x4 +#define HWIO_IPA_0_GSI_TOP_GSI_EVENT_CACHEATTR_ATRANSIENT_BMSK 0x8 +#define HWIO_IPA_0_GSI_TOP_GSI_EVENT_CACHEATTR_ATRANSIENT_SHFT 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_EVENT_CACHEATTR_ANOALLOCATE_BMSK 0x4 +#define HWIO_IPA_0_GSI_TOP_GSI_EVENT_CACHEATTR_ANOALLOCATE_SHFT 0x2 +#define HWIO_IPA_0_GSI_TOP_GSI_EVENT_CACHEATTR_AINNERSHARED_BMSK 0x2 +#define HWIO_IPA_0_GSI_TOP_GSI_EVENT_CACHEATTR_AINNERSHARED_SHFT 0x1 +#define HWIO_IPA_0_GSI_TOP_GSI_EVENT_CACHEATTR_ASHARED_BMSK 0x1 +#define HWIO_IPA_0_GSI_TOP_GSI_EVENT_CACHEATTR_ASHARED_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_DATA_CACHEATTR_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00000088) +#define HWIO_IPA_0_GSI_TOP_GSI_DATA_CACHEATTR_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000088) +#define HWIO_IPA_0_GSI_TOP_GSI_DATA_CACHEATTR_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000088) +#define HWIO_IPA_0_GSI_TOP_GSI_DATA_CACHEATTR_RMSK 0x3f +#define HWIO_IPA_0_GSI_TOP_GSI_DATA_CACHEATTR_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_DATA_CACHEATTR_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_DATA_CACHEATTR_ADDR, HWIO_IPA_0_GSI_TOP_GSI_DATA_CACHEATTR_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_DATA_CACHEATTR_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_DATA_CACHEATTR_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_DATA_CACHEATTR_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_DATA_CACHEATTR_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_GSI_DATA_CACHEATTR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_GSI_DATA_CACHEATTR_ADDR,m,v,HWIO_IPA_0_GSI_TOP_GSI_DATA_CACHEATTR_IN) +#define HWIO_IPA_0_GSI_TOP_GSI_DATA_CACHEATTR_AREQPRIORITY_BMSK 0x30 +#define HWIO_IPA_0_GSI_TOP_GSI_DATA_CACHEATTR_AREQPRIORITY_SHFT 0x4 +#define HWIO_IPA_0_GSI_TOP_GSI_DATA_CACHEATTR_ATRANSIENT_BMSK 0x8 +#define HWIO_IPA_0_GSI_TOP_GSI_DATA_CACHEATTR_ATRANSIENT_SHFT 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_DATA_CACHEATTR_ANOALLOCATE_BMSK 0x4 +#define HWIO_IPA_0_GSI_TOP_GSI_DATA_CACHEATTR_ANOALLOCATE_SHFT 0x2 +#define HWIO_IPA_0_GSI_TOP_GSI_DATA_CACHEATTR_AINNERSHARED_BMSK 0x2 +#define HWIO_IPA_0_GSI_TOP_GSI_DATA_CACHEATTR_AINNERSHARED_SHFT 0x1 +#define HWIO_IPA_0_GSI_TOP_GSI_DATA_CACHEATTR_ASHARED_BMSK 0x1 +#define HWIO_IPA_0_GSI_TOP_GSI_DATA_CACHEATTR_ASHARED_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_TRE_CACHEATTR_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00000090) +#define HWIO_IPA_0_GSI_TOP_GSI_TRE_CACHEATTR_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000090) +#define HWIO_IPA_0_GSI_TOP_GSI_TRE_CACHEATTR_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000090) +#define HWIO_IPA_0_GSI_TOP_GSI_TRE_CACHEATTR_RMSK 0x3f +#define HWIO_IPA_0_GSI_TOP_GSI_TRE_CACHEATTR_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_TRE_CACHEATTR_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_TRE_CACHEATTR_ADDR, HWIO_IPA_0_GSI_TOP_GSI_TRE_CACHEATTR_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_TRE_CACHEATTR_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_TRE_CACHEATTR_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_TRE_CACHEATTR_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_TRE_CACHEATTR_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_GSI_TRE_CACHEATTR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_GSI_TRE_CACHEATTR_ADDR,m,v,HWIO_IPA_0_GSI_TOP_GSI_TRE_CACHEATTR_IN) +#define HWIO_IPA_0_GSI_TOP_GSI_TRE_CACHEATTR_AREQPRIORITY_BMSK 0x30 +#define HWIO_IPA_0_GSI_TOP_GSI_TRE_CACHEATTR_AREQPRIORITY_SHFT 0x4 +#define HWIO_IPA_0_GSI_TOP_GSI_TRE_CACHEATTR_ATRANSIENT_BMSK 0x8 +#define HWIO_IPA_0_GSI_TOP_GSI_TRE_CACHEATTR_ATRANSIENT_SHFT 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_TRE_CACHEATTR_ANOALLOCATE_BMSK 0x4 +#define HWIO_IPA_0_GSI_TOP_GSI_TRE_CACHEATTR_ANOALLOCATE_SHFT 0x2 +#define HWIO_IPA_0_GSI_TOP_GSI_TRE_CACHEATTR_AINNERSHARED_BMSK 0x2 +#define HWIO_IPA_0_GSI_TOP_GSI_TRE_CACHEATTR_AINNERSHARED_SHFT 0x1 +#define HWIO_IPA_0_GSI_TOP_GSI_TRE_CACHEATTR_ASHARED_BMSK 0x1 +#define HWIO_IPA_0_GSI_TOP_GSI_TRE_CACHEATTR_ASHARED_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_REE_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00000100) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_REE_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000100) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_REE_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000100) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_REE_RMSK 0xfff +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_REE_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_REE_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_REE_ADDR, HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_REE_RMSK) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_REE_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_REE_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_REE_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_REE_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_REE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_REE_ADDR,m,v,HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_REE_IN) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_REE_CH_EMPTY_INT_WEIGHT_BMSK 0xf00 +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_REE_CH_EMPTY_INT_WEIGHT_SHFT 0x8 +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_REE_NEW_RE_INT_WEIGHT_BMSK 0xf0 +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_REE_NEW_RE_INT_WEIGHT_SHFT 0x4 +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_REE_STOP_CH_COMP_INT_WEIGHT_BMSK 0xf +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_REE_STOP_CH_COMP_INT_WEIGHT_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_EVT_ENG_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00000104) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_EVT_ENG_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000104) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_EVT_ENG_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000104) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_EVT_ENG_RMSK 0xf +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_EVT_ENG_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_EVT_ENG_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_EVT_ENG_ADDR, HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_EVT_ENG_RMSK) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_EVT_ENG_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_EVT_ENG_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_EVT_ENG_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_EVT_ENG_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_EVT_ENG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_EVT_ENG_ADDR,m,v,HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_EVT_ENG_IN) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_EVT_ENG_EVNT_ENG_INT_WEIGHT_BMSK 0xf +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_EVT_ENG_EVNT_ENG_INT_WEIGHT_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_INT_ENG_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00000108) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_INT_ENG_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000108) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_INT_ENG_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000108) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_INT_ENG_RMSK 0xf +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_INT_ENG_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_INT_ENG_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_INT_ENG_ADDR, HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_INT_ENG_RMSK) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_INT_ENG_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_INT_ENG_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_INT_ENG_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_INT_ENG_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_INT_ENG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_INT_ENG_ADDR,m,v,HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_INT_ENG_IN) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_INT_ENG_INT_ENG_INT_WEIGHT_BMSK 0xf +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_INT_ENG_INT_ENG_INT_WEIGHT_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_CSR_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x0000010c) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_CSR_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000010c) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_CSR_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000010c) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_CSR_RMSK 0xff +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_CSR_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_CSR_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_CSR_ADDR, HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_CSR_RMSK) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_CSR_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_CSR_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_CSR_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_CSR_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_CSR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_CSR_ADDR,m,v,HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_CSR_IN) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_CSR_EE_GENERIC_INT_WEIGHT_BMSK 0xf0 +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_CSR_EE_GENERIC_INT_WEIGHT_SHFT 0x4 +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_CSR_CH_CMD_INT_WEIGHT_BMSK 0xf +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_CSR_CH_CMD_INT_WEIGHT_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_TLV_ENG_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00000110) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_TLV_ENG_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000110) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_TLV_ENG_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000110) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_TLV_ENG_RMSK 0xffff +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_TLV_ENG_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_TLV_ENG_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_TLV_ENG_ADDR, HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_TLV_ENG_RMSK) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_TLV_ENG_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_TLV_ENG_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_TLV_ENG_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_TLV_ENG_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_TLV_ENG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_TLV_ENG_ADDR,m,v,HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_TLV_ENG_IN) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_TLV_ENG_CH_NOT_FULL_INT_WEIGHT_BMSK 0xf000 +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_TLV_ENG_CH_NOT_FULL_INT_WEIGHT_SHFT 0xc +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_TLV_ENG_TLV_2_INT_WEIGHT_BMSK 0xf00 +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_TLV_ENG_TLV_2_INT_WEIGHT_SHFT 0x8 +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_TLV_ENG_TLV_1_INT_WEIGHT_BMSK 0xf0 +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_TLV_ENG_TLV_1_INT_WEIGHT_SHFT 0x4 +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_TLV_ENG_TLV_0_INT_WEIGHT_BMSK 0xf +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_TLV_ENG_TLV_0_INT_WEIGHT_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_TIMER_ENG_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00000114) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_TIMER_ENG_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000114) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_TIMER_ENG_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000114) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_TIMER_ENG_RMSK 0xf +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_TIMER_ENG_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_TIMER_ENG_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_TIMER_ENG_ADDR, HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_TIMER_ENG_RMSK) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_TIMER_ENG_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_TIMER_ENG_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_TIMER_ENG_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_TIMER_ENG_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_TIMER_ENG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_TIMER_ENG_ADDR,m,v,HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_TIMER_ENG_IN) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_TIMER_ENG_TIMER_INT_WEIGHT_BMSK 0xf +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_TIMER_ENG_TIMER_INT_WEIGHT_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_DB_ENG_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00000118) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_DB_ENG_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000118) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_DB_ENG_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000118) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_DB_ENG_RMSK 0xf +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_DB_ENG_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_DB_ENG_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_DB_ENG_ADDR, HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_DB_ENG_RMSK) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_DB_ENG_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_DB_ENG_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_DB_ENG_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_DB_ENG_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_DB_ENG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_DB_ENG_ADDR,m,v,HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_DB_ENG_IN) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_DB_ENG_NEW_DB_INT_WEIGHT_BMSK 0xf +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_DB_ENG_NEW_DB_INT_WEIGHT_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_RD_WR_ENG_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x0000011c) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_RD_WR_ENG_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000011c) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_RD_WR_ENG_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000011c) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_RD_WR_ENG_RMSK 0xff +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_RD_WR_ENG_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_RD_WR_ENG_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_RD_WR_ENG_ADDR, HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_RD_WR_ENG_RMSK) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_RD_WR_ENG_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_RD_WR_ENG_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_RD_WR_ENG_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_RD_WR_ENG_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_RD_WR_ENG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_RD_WR_ENG_ADDR,m,v,HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_RD_WR_ENG_IN) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_RD_WR_ENG_WRITE_INT_WEIGHT_BMSK 0xf0 +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_RD_WR_ENG_WRITE_INT_WEIGHT_SHFT 0x4 +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_RD_WR_ENG_READ_INT_WEIGHT_BMSK 0xf +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_RD_WR_ENG_READ_INT_WEIGHT_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_UCONTROLLER_ENG_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00000120) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_UCONTROLLER_ENG_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000120) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_UCONTROLLER_ENG_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000120) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_UCONTROLLER_ENG_RMSK 0xf +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_UCONTROLLER_ENG_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_UCONTROLLER_ENG_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_UCONTROLLER_ENG_ADDR, HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_UCONTROLLER_ENG_RMSK) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_UCONTROLLER_ENG_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_UCONTROLLER_ENG_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_UCONTROLLER_ENG_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_UCONTROLLER_ENG_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_UCONTROLLER_ENG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_UCONTROLLER_ENG_ADDR,m,v,HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_UCONTROLLER_ENG_IN) +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_UCONTROLLER_ENG_UCONTROLLER_GP_INT_WEIGHT_BMSK 0xf +#define HWIO_IPA_0_GSI_TOP_IC_INT_WEIGHT_UCONTROLLER_ENG_UCONTROLLER_GP_INT_WEIGHT_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_LOW_LATENCY_ARB_WEIGHT_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00000128) +#define HWIO_IPA_0_GSI_TOP_LOW_LATENCY_ARB_WEIGHT_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000128) +#define HWIO_IPA_0_GSI_TOP_LOW_LATENCY_ARB_WEIGHT_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000128) +#define HWIO_IPA_0_GSI_TOP_LOW_LATENCY_ARB_WEIGHT_RMSK 0x13f3f +#define HWIO_IPA_0_GSI_TOP_LOW_LATENCY_ARB_WEIGHT_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_LOW_LATENCY_ARB_WEIGHT_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_LOW_LATENCY_ARB_WEIGHT_ADDR, HWIO_IPA_0_GSI_TOP_LOW_LATENCY_ARB_WEIGHT_RMSK) +#define HWIO_IPA_0_GSI_TOP_LOW_LATENCY_ARB_WEIGHT_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_LOW_LATENCY_ARB_WEIGHT_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_LOW_LATENCY_ARB_WEIGHT_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_LOW_LATENCY_ARB_WEIGHT_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_LOW_LATENCY_ARB_WEIGHT_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_LOW_LATENCY_ARB_WEIGHT_ADDR,m,v,HWIO_IPA_0_GSI_TOP_LOW_LATENCY_ARB_WEIGHT_IN) +#define HWIO_IPA_0_GSI_TOP_LOW_LATENCY_ARB_WEIGHT_LL_NON_LL_FIX_PRIORITY_BMSK 0x10000 +#define HWIO_IPA_0_GSI_TOP_LOW_LATENCY_ARB_WEIGHT_LL_NON_LL_FIX_PRIORITY_SHFT 0x10 +#define HWIO_IPA_0_GSI_TOP_LOW_LATENCY_ARB_WEIGHT_NON_LL_WEIGHT_BMSK 0x3f00 +#define HWIO_IPA_0_GSI_TOP_LOW_LATENCY_ARB_WEIGHT_NON_LL_WEIGHT_SHFT 0x8 +#define HWIO_IPA_0_GSI_TOP_LOW_LATENCY_ARB_WEIGHT_LL_WEIGHT_BMSK 0x3f +#define HWIO_IPA_0_GSI_TOP_LOW_LATENCY_ARB_WEIGHT_LL_WEIGHT_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_MANAGER_EE_QOS_n_ADDR(n) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00000300 + 0x4 * (n)) +#define HWIO_IPA_0_GSI_TOP_GSI_MANAGER_EE_QOS_n_PHYS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000300 + 0x4 * (n)) +#define HWIO_IPA_0_GSI_TOP_GSI_MANAGER_EE_QOS_n_OFFS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000300 + 0x4 * (n)) +#define HWIO_IPA_0_GSI_TOP_GSI_MANAGER_EE_QOS_n_RMSK 0xffff03 +#define HWIO_IPA_0_GSI_TOP_GSI_MANAGER_EE_QOS_n_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_GSI_MANAGER_EE_QOS_n_ATTR 0x0 +#define HWIO_IPA_0_GSI_TOP_GSI_MANAGER_EE_QOS_n_INI(n) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_MANAGER_EE_QOS_n_ADDR(n), HWIO_IPA_0_GSI_TOP_GSI_MANAGER_EE_QOS_n_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_MANAGER_EE_QOS_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_MANAGER_EE_QOS_n_ADDR(n), mask) +#define HWIO_IPA_0_GSI_TOP_GSI_MANAGER_EE_QOS_n_OUTI(n,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_MANAGER_EE_QOS_n_ADDR(n),val) +#define HWIO_IPA_0_GSI_TOP_GSI_MANAGER_EE_QOS_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_GSI_MANAGER_EE_QOS_n_ADDR(n),mask,val,HWIO_IPA_0_GSI_TOP_GSI_MANAGER_EE_QOS_n_INI(n)) +#define HWIO_IPA_0_GSI_TOP_GSI_MANAGER_EE_QOS_n_MAX_EV_ALLOC_BMSK 0xff0000 +#define HWIO_IPA_0_GSI_TOP_GSI_MANAGER_EE_QOS_n_MAX_EV_ALLOC_SHFT 0x10 +#define HWIO_IPA_0_GSI_TOP_GSI_MANAGER_EE_QOS_n_MAX_CH_ALLOC_BMSK 0xff00 +#define HWIO_IPA_0_GSI_TOP_GSI_MANAGER_EE_QOS_n_MAX_CH_ALLOC_SHFT 0x8 +#define HWIO_IPA_0_GSI_TOP_GSI_MANAGER_EE_QOS_n_EE_PRIO_BMSK 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_MANAGER_EE_QOS_n_EE_PRIO_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00000200) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000200) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000200) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_RMSK 0xffff +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_ADDR, HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_ADDR,m,v,HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_IN) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00000204) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000204) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000204) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_RMSK 0xffff +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_ADDR, HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_ADDR,m,v,HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_IN) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00000208) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000208) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000208) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_RMSK 0xffff +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_ADDR, HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_ADDR,m,v,HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_IN) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x0000020c) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000020c) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000020c) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_RMSK 0xffff +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_ADDR, HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_ADDR,m,v,HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_IN) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00000240) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000240) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000240) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_RMSK 0xffff +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_ADDR, HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_ADDR,m,v,HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_IN) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00000244) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000244) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000244) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_RMSK 0xffff +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_ADDR, HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_ADDR,m,v,HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_IN) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00000210) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000210) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000210) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_RMSK 0xffff +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_ADDR, HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_ADDR,m,v,HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_IN) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00000214) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000214) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000214) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_RMSK 0xffff +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_ADDR, HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_ADDR,m,v,HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_IN) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00000218) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000218) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000218) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_RMSK 0xffff +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_ADDR, HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_ADDR,m,v,HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_IN) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x0000021c) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000021c) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000021c) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_RMSK 0xffff +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_ADDR, HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_ADDR,m,v,HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_IN) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00000254) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000254) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000254) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_RMSK 0xffff +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_ADDR, HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_ADDR,m,v,HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_IN) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00000258) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000258) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000258) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_RMSK 0xffff +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_ADDR, HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_ADDR,m,v,HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_IN) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x0000025c) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000025c) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000025c) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_RMSK 0xffff +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_ADDR, HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_ADDR,m,v,HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_IN) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00000260) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000260) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000260) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_RMSK 0xffff +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_ADDR, HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_ADDR,m,v,HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_IN) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00000264) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000264) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000264) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_RMSK 0xffff +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_ADDR, HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_ADDR,m,v,HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_IN) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00000268) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000268) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000268) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_RMSK 0xffff +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_ADDR, HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_ADDR,m,v,HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_IN) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_SHRAM_PTR_BMSK 0xffff +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR_SHRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_CMD_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00000400) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_CMD_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000400) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_CMD_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000400) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_CMD_RMSK 0xfff +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_CMD_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_CMD_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_CMD_ADDR, HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_CMD_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_CMD_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_CMD_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_CMD_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_CMD_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_CMD_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_CMD_ADDR,m,v,HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_CMD_IN) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_CMD_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_CMD_IRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00000404) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000404) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000404) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_RMSK 0xfff +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_ADDR, HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_ADDR,m,v,HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_IN) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_IRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_TLV_CH_NOT_FULL_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00000408) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_TLV_CH_NOT_FULL_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000408) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_TLV_CH_NOT_FULL_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000408) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_TLV_CH_NOT_FULL_RMSK 0xfff +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_TLV_CH_NOT_FULL_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_TLV_CH_NOT_FULL_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_TLV_CH_NOT_FULL_ADDR, HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_TLV_CH_NOT_FULL_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_TLV_CH_NOT_FULL_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_TLV_CH_NOT_FULL_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_TLV_CH_NOT_FULL_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_TLV_CH_NOT_FULL_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_TLV_CH_NOT_FULL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_TLV_CH_NOT_FULL_ADDR,m,v,HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_TLV_CH_NOT_FULL_IN) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_TLV_CH_NOT_FULL_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_TLV_CH_NOT_FULL_IRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_MSI_DB_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00000414) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_MSI_DB_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000414) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_MSI_DB_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000414) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_MSI_DB_RMSK 0xfff +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_MSI_DB_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_MSI_DB_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_MSI_DB_ADDR, HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_MSI_DB_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_MSI_DB_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_MSI_DB_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_MSI_DB_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_MSI_DB_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_MSI_DB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_MSI_DB_ADDR,m,v,HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_MSI_DB_IN) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_MSI_DB_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_MSI_DB_IRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_DB_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00000418) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_DB_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000418) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_DB_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000418) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_DB_RMSK 0xfff +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_DB_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_DB_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_DB_ADDR, HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_DB_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_DB_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_DB_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_DB_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_DB_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_DB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_DB_ADDR,m,v,HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_DB_IN) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_DB_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_DB_IRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_EV_DB_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x0000041c) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_EV_DB_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000041c) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_EV_DB_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000041c) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_EV_DB_RMSK 0xfff +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_EV_DB_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_EV_DB_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_EV_DB_ADDR, HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_EV_DB_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_EV_DB_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_EV_DB_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_EV_DB_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_EV_DB_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_EV_DB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_EV_DB_ADDR,m,v,HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_EV_DB_IN) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_EV_DB_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_EV_DB_IRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_NEW_RE_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00000420) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_NEW_RE_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000420) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_NEW_RE_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000420) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_NEW_RE_RMSK 0xfff +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_NEW_RE_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_NEW_RE_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_NEW_RE_ADDR, HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_NEW_RE_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_NEW_RE_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_NEW_RE_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_NEW_RE_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_NEW_RE_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_NEW_RE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_NEW_RE_ADDR,m,v,HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_NEW_RE_IN) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_NEW_RE_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_NEW_RE_IRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00000424) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000424) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000424) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_RMSK 0xfff +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_ADDR, HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_ADDR,m,v,HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_IN) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_IRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00000428) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000428) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000428) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_RMSK 0xfff +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_ADDR, HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_ADDR,m,v,HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_IN) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_IRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x0000042c) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000042c) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000042c) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_RMSK 0xfff +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_ADDR, HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_ADDR,m,v,HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_IN) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_IRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00000430) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000430) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000430) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_RMSK 0xfff +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_ADDR, HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_ADDR,m,v,HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_IN) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_IRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00000434) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000434) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000434) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_RMSK 0xfff +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_ADDR, HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_ADDR,m,v,HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_IN) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_IRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00000438) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000438) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000438) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_RMSK 0xfff +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_ADDR, HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_ADDR,m,v,HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_IN) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_IRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x0000043c) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000043c) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000043c) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_RMSK 0xfff +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_ADDR, HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_ADDR,m,v,HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_IN) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_IRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00000440) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000440) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000440) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_RMSK 0xfff +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_ADDR, HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_ADDR,m,v,HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_IN) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_IRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00000444) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000444) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000444) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_RMSK 0xfff +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_ADDR, HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_ADDR,m,v,HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_IN) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_IRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00000448) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000448) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000448) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_RMSK 0xfff +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_ADDR, HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_ADDR,m,v,HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_IN) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_IRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPED_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x0000044c) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPED_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000044c) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPED_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000044c) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPED_RMSK 0xfff +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPED_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPED_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPED_ADDR, HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPED_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPED_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPED_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPED_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPED_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPED_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPED_ADDR,m,v,HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPED_IN) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPED_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPED_IRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_INT_NOTIFY_MCS_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00000470) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_INT_NOTIFY_MCS_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000470) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_INT_NOTIFY_MCS_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000470) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_INT_NOTIFY_MCS_RMSK 0xfff +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_INT_NOTIFY_MCS_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_INT_NOTIFY_MCS_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_INT_NOTIFY_MCS_ADDR, HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_INT_NOTIFY_MCS_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_INT_NOTIFY_MCS_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_INT_NOTIFY_MCS_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_INT_NOTIFY_MCS_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_INT_NOTIFY_MCS_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_INT_NOTIFY_MCS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_INT_NOTIFY_MCS_ADDR,m,v,HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_INT_NOTIFY_MCS_IN) +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_INT_NOTIFY_MCS_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_0_GSI_TOP_GSI_IRAM_PTR_INT_NOTIFY_MCS_IRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_INST_RAM_n_ADDR(n) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x000a4000 + 0x4 * (n)) +#define HWIO_IPA_0_GSI_TOP_GSI_INST_RAM_n_PHYS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x000a4000 + 0x4 * (n)) +#define HWIO_IPA_0_GSI_TOP_GSI_INST_RAM_n_OFFS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x000a4000 + 0x4 * (n)) +#define HWIO_IPA_0_GSI_TOP_GSI_INST_RAM_n_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_GSI_INST_RAM_n_MAXn 8257 +#define HWIO_IPA_0_GSI_TOP_GSI_INST_RAM_n_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_INST_RAM_n_INI(n) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_INST_RAM_n_ADDR(n), HWIO_IPA_0_GSI_TOP_GSI_INST_RAM_n_RMSK, HWIO_IPA_0_GSI_TOP_GSI_INST_RAM_n_ATTR) +#define HWIO_IPA_0_GSI_TOP_GSI_INST_RAM_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_INST_RAM_n_ADDR(n), mask) +#define HWIO_IPA_0_GSI_TOP_GSI_INST_RAM_n_OUTI(n,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_INST_RAM_n_ADDR(n),val) +#define HWIO_IPA_0_GSI_TOP_GSI_INST_RAM_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_GSI_INST_RAM_n_ADDR(n),mask,val,HWIO_IPA_0_GSI_TOP_GSI_INST_RAM_n_INI(n)) +#define HWIO_IPA_0_GSI_TOP_GSI_INST_RAM_n_INST_BYTE_3_BMSK 0xff000000 +#define HWIO_IPA_0_GSI_TOP_GSI_INST_RAM_n_INST_BYTE_3_SHFT 0x18 +#define HWIO_IPA_0_GSI_TOP_GSI_INST_RAM_n_INST_BYTE_2_BMSK 0xff0000 +#define HWIO_IPA_0_GSI_TOP_GSI_INST_RAM_n_INST_BYTE_2_SHFT 0x10 +#define HWIO_IPA_0_GSI_TOP_GSI_INST_RAM_n_INST_BYTE_1_BMSK 0xff00 +#define HWIO_IPA_0_GSI_TOP_GSI_INST_RAM_n_INST_BYTE_1_SHFT 0x8 +#define HWIO_IPA_0_GSI_TOP_GSI_INST_RAM_n_INST_BYTE_0_BMSK 0xff +#define HWIO_IPA_0_GSI_TOP_GSI_INST_RAM_n_INST_BYTE_0_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_n_ADDR(n) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00002000 + 0x4 * (n)) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_n_PHYS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00002000 + 0x4 * (n)) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_n_OFFS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00002000 + 0x4 * (n)) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_n_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_n_MAXn 2037 +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_n_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_n_INI(n) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_n_ADDR(n), HWIO_IPA_0_GSI_TOP_GSI_SHRAM_n_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_n_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_n_ADDR(n), mask) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_n_OUTI(n,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_n_ADDR(n),val) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_n_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_GSI_SHRAM_n_ADDR(n),mask,val,HWIO_IPA_0_GSI_TOP_GSI_SHRAM_n_INI(n)) +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_n_SHRAM_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_GSI_SHRAM_n_SHRAM_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00009000 + 0x400 * (n) + 0x4 * (k)) +#define HWIO_IPA_0_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00009000 + 0x400 * (n) + 0x4 * (k)) +#define HWIO_IPA_0_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00009000 + 0x400 * (n) + 0x4 * (k)) +#define HWIO_IPA_0_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_RMSK 0x1ff +#define HWIO_IPA_0_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_MAXk 27 +#define HWIO_IPA_0_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_INI2(n,k) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_ADDR(n,k), HWIO_IPA_0_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_ADDR(n,k), mask) +#define HWIO_IPA_0_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_ADDR(n,k),val) +#define HWIO_IPA_0_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_ADDR(n,k),mask,val,HWIO_IPA_0_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_INI2(n,k)) +#define HWIO_IPA_0_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_VALID_BMSK 0x100 +#define HWIO_IPA_0_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_VALID_SHFT 0x8 +#define HWIO_IPA_0_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_PHY_CH_BMSK 0xff +#define HWIO_IPA_0_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_PHY_CH_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00001000) +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001000) +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001000) +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_RMSK 0xf00ff +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_ADDR, HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_ADDR,m,v,HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_IN) +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_GSI_HW_EVENTS_SEL_BMSK 0xf0000 +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_GSI_HW_EVENTS_SEL_SHFT 0x10 +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_BMSK 0xff +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_SHFT 0x0 +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_ZEROS_FVAL 0x0 +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MCS_0_FVAL 0x1 +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MCS_1_FVAL 0x2 +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MCS_2_FVAL 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MCS_3_FVAL 0x4 +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MCS_4_FVAL 0x5 +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_DB_ENG_FVAL 0x9 +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_0_FVAL 0xb +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_1_FVAL 0xc +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_2_FVAL 0xd +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_3_FVAL 0xe +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_4_FVAL 0xf +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_5_FVAL 0x10 +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_6_FVAL 0x11 +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_7_FVAL 0x12 +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_EVE_0_FVAL 0x13 +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_EVE_1_FVAL 0x14 +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_EVE_2_FVAL 0x15 +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_EVE_3_FVAL 0x16 +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_EVE_4_FVAL 0x17 +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_EVE_5_FVAL 0x18 +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IE_0_FVAL 0x1b +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IE_1_FVAL 0x1c +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IE_2_FVAL 0x1d +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IC_0_FVAL 0x1f +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IC_1_FVAL 0x20 +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IC_2_FVAL 0x21 +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IC_3_FVAL 0x22 +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IC_4_FVAL 0x23 +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MOQA_0_FVAL 0x27 +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MOQA_1_FVAL 0x28 +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MOQA_2_FVAL 0x29 +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MOQA_3_FVAL 0x2a +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_TMR_0_FVAL 0x2b +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_TMR_1_FVAL 0x2c +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_TMR_2_FVAL 0x2d +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_TMR_3_FVAL 0x2e +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_RD_WR_0_FVAL 0x33 +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_RD_WR_1_FVAL 0x34 +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_RD_WR_2_FVAL 0x35 +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_RD_WR_3_FVAL 0x36 +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_CSR_FVAL 0x3a +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_SDMA_0_FVAL 0x3c +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_SMDA_1_FVAL 0x3d +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_CSR_1_FVAL 0x3e +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_CSR_2_FVAL 0x3f +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MCS_5_FVAL 0x40 +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IC_5_FVAL 0x41 +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_CSR_3_FVAL 0x42 +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_TLV_0_FVAL 0x43 +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_8_FVAL 0x44 +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IE_NOTIFY_FVAL 0x45 +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_DB_MSI_FVAL 0x46 +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_9_FVAL 0x47 + +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_REG_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00001008) +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_REG_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001008) +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_REG_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001008) +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_REG_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_REG_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_REG_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_REG_ADDR, HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_REG_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_REG_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_REG_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_REG_GSI_TESTBUS_REG_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_GSI_TEST_BUS_REG_GSI_TESTBUS_REG_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_BUSY_REG_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00001010) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_BUSY_REG_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001010) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_BUSY_REG_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001010) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_BUSY_REG_RMSK 0x1fff +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_BUSY_REG_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_BUSY_REG_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_DEBUG_BUSY_REG_ADDR, HWIO_IPA_0_GSI_TOP_GSI_DEBUG_BUSY_REG_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_BUSY_REG_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_DEBUG_BUSY_REG_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_BUSY_REG_SDMA_BUSY_BMSK 0x1000 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_BUSY_REG_SDMA_BUSY_SHFT 0xc +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_BUSY_REG_IC_BUSY_BMSK 0x800 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_BUSY_REG_IC_BUSY_SHFT 0xb +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_BUSY_REG_UC_BUSY_BMSK 0x400 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_BUSY_REG_UC_BUSY_SHFT 0xa +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_BUSY_REG_DBG_CNT_BUSY_BMSK 0x200 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_BUSY_REG_DBG_CNT_BUSY_SHFT 0x9 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_BUSY_REG_DB_ENG_BUSY_BMSK 0x100 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_BUSY_REG_DB_ENG_BUSY_SHFT 0x8 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_BUSY_REG_REE_PWR_CLPS_BUSY_BMSK 0x80 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_BUSY_REG_REE_PWR_CLPS_BUSY_SHFT 0x7 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_BUSY_REG_INT_ENG_BUSY_BMSK 0x40 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_BUSY_REG_INT_ENG_BUSY_SHFT 0x6 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_BUSY_REG_EV_ENG_BUSY_BMSK 0x20 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_BUSY_REG_EV_ENG_BUSY_SHFT 0x5 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_BUSY_REG_RD_WR_BUSY_BMSK 0x10 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_BUSY_REG_RD_WR_BUSY_SHFT 0x4 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_BUSY_REG_TIMER_BUSY_BMSK 0x8 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_BUSY_REG_TIMER_BUSY_SHFT 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_BUSY_REG_MCS_BUSY_BMSK 0x4 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_BUSY_REG_MCS_BUSY_SHFT 0x2 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_BUSY_REG_REE_BUSY_BMSK 0x2 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_BUSY_REG_REE_BUSY_SHFT 0x1 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_BUSY_REG_CSR_BUSY_BMSK 0x1 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_BUSY_REG_CSR_BUSY_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_EVENT_PENDING_k_ADDR(k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00001a80 + 0x4 * (k)) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_EVENT_PENDING_k_PHYS(k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001a80 + 0x4 * (k)) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_EVENT_PENDING_k_OFFS(k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001a80 + 0x4 * (k)) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_EVENT_PENDING_k_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_EVENT_PENDING_k_MAXk 1 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_EVENT_PENDING_k_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_EVENT_PENDING_k_INI(k) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_DEBUG_EVENT_PENDING_k_ADDR(k), HWIO_IPA_0_GSI_TOP_GSI_DEBUG_EVENT_PENDING_k_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_EVENT_PENDING_k_INMI(k,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_DEBUG_EVENT_PENDING_k_ADDR(k), mask) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_EVENT_PENDING_k_CHID_BIT_MAP_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_EVENT_PENDING_k_CHID_BIT_MAP_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_TIMER_PENDING_k_ADDR(k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00001aa0 + 0x4 * (k)) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_TIMER_PENDING_k_PHYS(k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001aa0 + 0x4 * (k)) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_TIMER_PENDING_k_OFFS(k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001aa0 + 0x4 * (k)) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_TIMER_PENDING_k_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_TIMER_PENDING_k_MAXk 1 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_TIMER_PENDING_k_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_TIMER_PENDING_k_INI(k) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_DEBUG_TIMER_PENDING_k_ADDR(k), HWIO_IPA_0_GSI_TOP_GSI_DEBUG_TIMER_PENDING_k_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_TIMER_PENDING_k_INMI(k,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_DEBUG_TIMER_PENDING_k_ADDR(k), mask) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_TIMER_PENDING_k_CHID_BIT_MAP_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_TIMER_PENDING_k_CHID_BIT_MAP_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_k_ADDR(k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00001ac0 + 0x4 * (k)) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_k_PHYS(k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001ac0 + 0x4 * (k)) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_k_OFFS(k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001ac0 + 0x4 * (k)) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_k_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_k_MAXk 1 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_k_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_k_INI(k) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_k_ADDR(k), HWIO_IPA_0_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_k_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_k_INMI(k,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_k_ADDR(k), mask) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_k_CHID_BIT_MAP_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_k_CHID_BIT_MAP_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_SPARE_REG_1_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00001030) +#define HWIO_IPA_0_GSI_TOP_GSI_SPARE_REG_1_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001030) +#define HWIO_IPA_0_GSI_TOP_GSI_SPARE_REG_1_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001030) +#define HWIO_IPA_0_GSI_TOP_GSI_SPARE_REG_1_RMSK 0x1 +#define HWIO_IPA_0_GSI_TOP_GSI_SPARE_REG_1_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_SPARE_REG_1_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_SPARE_REG_1_ADDR, HWIO_IPA_0_GSI_TOP_GSI_SPARE_REG_1_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_SPARE_REG_1_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_SPARE_REG_1_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_SPARE_REG_1_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_SPARE_REG_1_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_GSI_SPARE_REG_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_GSI_SPARE_REG_1_ADDR,m,v,HWIO_IPA_0_GSI_TOP_GSI_SPARE_REG_1_IN) +#define HWIO_IPA_0_GSI_TOP_GSI_SPARE_REG_1_FIX_IEOB_WRONG_MSK_DISABLE_BMSK 0x1 +#define HWIO_IPA_0_GSI_TOP_GSI_SPARE_REG_1_FIX_IEOB_WRONG_MSK_DISABLE_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_PC_FROM_SW_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00001040) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_PC_FROM_SW_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001040) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_PC_FROM_SW_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001040) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_PC_FROM_SW_RMSK 0xfff +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_PC_FROM_SW_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_PC_FROM_SW_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_DEBUG_PC_FROM_SW_ADDR, HWIO_IPA_0_GSI_TOP_GSI_DEBUG_PC_FROM_SW_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_PC_FROM_SW_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_DEBUG_PC_FROM_SW_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_PC_FROM_SW_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_DEBUG_PC_FROM_SW_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_PC_FROM_SW_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_GSI_DEBUG_PC_FROM_SW_ADDR,m,v,HWIO_IPA_0_GSI_TOP_GSI_DEBUG_PC_FROM_SW_IN) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_PC_FROM_SW_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_PC_FROM_SW_IRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_STALL_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00001044) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_STALL_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001044) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_STALL_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001044) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_STALL_RMSK 0x1 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_STALL_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_STALL_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_STALL_ADDR, HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_STALL_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_STALL_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_STALL_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_STALL_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_STALL_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_STALL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_STALL_ADDR,m,v,HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_STALL_IN) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_STALL_MCS_STALL_BMSK 0x1 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_STALL_MCS_STALL_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00001048) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001048) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001048) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG_RMSK 0xfff +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG_ADDR, HWIO_IPA_0_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG_IRAM_PTR_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_SEL_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00001050) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_SEL_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001050) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_SEL_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001050) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_SEL_RMSK 0xffff01 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_SEL_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_SEL_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_SEL_ADDR, HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_SEL_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_SEL_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_SEL_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_SEL_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_SEL_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_SEL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_SEL_ADDR,m,v,HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_SEL_IN) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_SEL_SEL_MID_BMSK 0xff0000 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_SEL_SEL_MID_SHFT 0x10 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_SEL_SEL_TID_BMSK 0xff00 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_SEL_SEL_TID_SHFT 0x8 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_SEL_SEL_WRITE_BMSK 0x1 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_SEL_SEL_WRITE_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_CLR_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00001058) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_CLR_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001058) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_CLR_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001058) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_CLR_RMSK 0x1 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_CLR_ATTR 0x2 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_CLR_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_CLR_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_CLR_LOG_CLR_BMSK 0x1 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_CLR_LOG_CLR_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00001060) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001060) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001060) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_RMSK 0x1ffff01 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ADDR, HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ERR_SAVED_BMSK 0x1000000 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ERR_SAVED_SHFT 0x18 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ERR_MID_BMSK 0xff0000 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ERR_MID_SHFT 0x10 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ERR_TID_BMSK 0xff00 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ERR_TID_SHFT 0x8 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ERR_WRITE_BMSK 0x1 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ERR_WRITE_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_0_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00001064) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_0_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001064) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_0_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001064) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_0_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_0_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_0_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_0_ADDR, HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_0_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_0_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_0_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_0_ADDR_31_0_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_0_ADDR_31_0_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_1_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00001068) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_1_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001068) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_1_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001068) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_1_RMSK 0xfff7ffff +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_1_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_1_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_1_ADDR, HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_1_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_1_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_1_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_1_AREQPRIORITY_BMSK 0xf0000000 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_1_AREQPRIORITY_SHFT 0x1c +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_1_ASIZE_BMSK 0xf000000 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_1_ASIZE_SHFT 0x18 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_1_ALEN_BMSK 0xf00000 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_1_ALEN_SHFT 0x14 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_1_AOOOWR_BMSK 0x40000 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_1_AOOOWR_SHFT 0x12 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_1_AOOORD_BMSK 0x20000 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_1_AOOORD_SHFT 0x11 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_1_ATRANSIENT_BMSK 0x10000 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_1_ATRANSIENT_SHFT 0x10 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_1_ACACHEABLE_BMSK 0x8000 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_1_ACACHEABLE_SHFT 0xf +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_1_ASHARED_BMSK 0x4000 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_1_ASHARED_SHFT 0xe +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_1_ANOALLOCATE_BMSK 0x2000 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_1_ANOALLOCATE_SHFT 0xd +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_1_AINNERSHARED_BMSK 0x1000 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_1_AINNERSHARED_SHFT 0xc +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_1_ADDR_43_32_BMSK 0xfff +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_1_ADDR_43_32_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_2_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x0000106c) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_2_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000106c) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_2_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000106c) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_2_RMSK 0xffff +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_2_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_2_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_2_ADDR, HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_2_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_2_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_2_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_2_AMEMTYPE_BMSK 0xf000 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_2_AMEMTYPE_SHFT 0xc +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_2_AMMUSID_BMSK 0xfff +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_2_AMMUSID_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_ADDR(n) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00001070 + 0x4 * (n)) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_PHYS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001070 + 0x4 * (n)) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_OFFS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001070 + 0x4 * (n)) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_MAXn 3 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_INI(n) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_ADDR(n), HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_ADDR(n), mask) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_MID_BMSK 0xf8000000 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_MID_SHFT 0x1b +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_TID_BMSK 0x7c00000 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_TID_SHFT 0x16 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_WRITE_BMSK 0x200000 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_WRITE_SHFT 0x15 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_ADDR_20_0_BMSK 0x1fffff +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_ADDR_20_0_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_RF_n_WRITE_ADDR(n) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00001080 + 0x4 * (n)) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_RF_n_WRITE_PHYS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001080 + 0x4 * (n)) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_RF_n_WRITE_OFFS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001080 + 0x4 * (n)) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_RF_n_WRITE_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_RF_n_WRITE_MAXn 31 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_RF_n_WRITE_ATTR 0x2 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_RF_n_WRITE_OUTI(n,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_RF_n_WRITE_ADDR(n),val) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_RF_n_WRITE_DATA_IN_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_RF_n_WRITE_DATA_IN_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_ADDR(n) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00001100 + 0x4 * (n)) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_PHYS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001100 + 0x4 * (n)) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_OFFS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001100 + 0x4 * (n)) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_MAXn 31 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_INI(n) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_ADDR(n), HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_ADDR(n), mask) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_RF_REG_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_RF_REG_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_ADDR(n) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00001180 + 0x4 * (n)) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_PHYS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001180 + 0x4 * (n)) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_OFFS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001180 + 0x4 * (n)) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_RMSK 0x1fffff +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_MAXn 7 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_INI(n) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_ADDR(n), HWIO_IPA_0_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_ADDR(n), mask) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_OUTI(n,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_ADDR(n),val) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_ADDR(n),mask,val,HWIO_IPA_0_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_INI(n)) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_CHAIN_BMSK 0x100000 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_CHAIN_SHFT 0x14 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_VIRTUAL_CHNL_BMSK 0xff000 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_VIRTUAL_CHNL_SHFT 0xc +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_EE_BMSK 0xf00 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_EE_SHFT 0x8 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_EVNT_TYPE_BMSK 0xf8 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_EVNT_TYPE_SHFT 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_CLR_AT_READ_BMSK 0x4 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_CLR_AT_READ_SHFT 0x2 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_STOP_AT_WRAP_ARND_BMSK 0x2 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_STOP_AT_WRAP_ARND_SHFT 0x1 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_ENABLE_BMSK 0x1 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_ENABLE_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_COUNTERn_ADDR(n) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x000011a0 + 0x4 * (n)) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_COUNTERn_PHYS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x000011a0 + 0x4 * (n)) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_COUNTERn_OFFS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x000011a0 + 0x4 * (n)) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_COUNTERn_RMSK 0xffff +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_COUNTERn_MAXn 7 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_COUNTERn_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_COUNTERn_INI(n) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_DEBUG_COUNTERn_ADDR(n), HWIO_IPA_0_GSI_TOP_GSI_DEBUG_COUNTERn_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_COUNTERn_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_DEBUG_COUNTERn_ADDR(n), mask) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_COUNTERn_COUNTER_VALUE_BMSK 0xffff +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_COUNTERn_COUNTER_VALUE_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_MSK_REG_n_SEC_k_WR_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x000011c0 + 0x4 * (n) + 0x24 * (k)) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_MSK_REG_n_SEC_k_WR_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x000011c0 + 0x4 * (n) + 0x24 * (k)) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_MSK_REG_n_SEC_k_WR_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x000011c0 + 0x4 * (n) + 0x24 * (k)) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_MSK_REG_n_SEC_k_WR_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_MSK_REG_n_SEC_k_WR_MAXn 8 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_MSK_REG_n_SEC_k_WR_MAXk 1 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_MSK_REG_n_SEC_k_WR_ATTR 0x2 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_MSK_REG_n_SEC_k_WR_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_MSK_REG_n_SEC_k_WR_ADDR(n,k),val) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_MSK_REG_n_SEC_k_WR_DATA_IN_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_MSK_REG_n_SEC_k_WR_DATA_IN_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x000012e0 + 0x4 * (n) + 0x24 * (k)) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x000012e0 + 0x4 * (n) + 0x24 * (k)) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x000012e0 + 0x4 * (n) + 0x24 * (k)) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD_MAXn 8 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD_MAXk 1 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD_INI2(n,k) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD_ADDR(n,k), HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD_ADDR(n,k), mask) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD_MSK_REG_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD_MSK_REG_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00001400 + 0x80 * (n) + 0x4 * (k)) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001400 + 0x80 * (n) + 0x4 * (k)) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001400 + 0x80 * (n) + 0x4 * (k)) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_RMSK 0x1ff +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_MAXn 3 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_MAXk 27 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_INI2(n,k) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_ADDR(n,k), HWIO_IPA_0_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_ADDR(n,k), mask) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_VALID_BMSK 0x100 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_VALID_SHFT 0x8 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_PHY_CH_BMSK 0xff +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_PHY_CH_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00001600 + 0x100 * (n) + 0x4 * (k)) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001600 + 0x100 * (n) + 0x4 * (k)) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001600 + 0x100 * (n) + 0x4 * (k)) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_RMSK 0x1ff +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_MAXn 3 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_MAXk 26 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_INI2(n,k) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_ADDR(n,k), HWIO_IPA_0_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_ADDR(n,k), mask) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_VALID_BMSK 0x100 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_VALID_SHFT 0x8 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_PHY_EV_CH_BMSK 0xff +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_PHY_EV_CH_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00001a54) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001a54) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001a54) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_RMSK 0xff +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_ADDR, HWIO_IPA_0_GSI_TOP_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_ADDR,m,v,HWIO_IPA_0_GSI_TOP_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_IN) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_PREFETCH_BUF_CH_ID_BMSK 0xff +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID_PREFETCH_BUF_CH_ID_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_REE_PREFETCH_BUF_STATUS_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00001a58) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_REE_PREFETCH_BUF_STATUS_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001a58) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_REE_PREFETCH_BUF_STATUS_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001a58) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_REE_PREFETCH_BUF_STATUS_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_REE_PREFETCH_BUF_STATUS_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_REE_PREFETCH_BUF_STATUS_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_DEBUG_REE_PREFETCH_BUF_STATUS_ADDR, HWIO_IPA_0_GSI_TOP_GSI_DEBUG_REE_PREFETCH_BUF_STATUS_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_REE_PREFETCH_BUF_STATUS_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_DEBUG_REE_PREFETCH_BUF_STATUS_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_REE_PREFETCH_BUF_STATUS_PREFETCH_BUF_STATUS_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_GSI_DEBUG_REE_PREFETCH_BUF_STATUS_PREFETCH_BUF_STATUS_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_BP_CNT_LSB_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00001a5c) +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_BP_CNT_LSB_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001a5c) +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_BP_CNT_LSB_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001a5c) +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_BP_CNT_LSB_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_BP_CNT_LSB_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_BP_CNT_LSB_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_BP_CNT_LSB_ADDR, HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_BP_CNT_LSB_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_BP_CNT_LSB_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_BP_CNT_LSB_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_BP_CNT_LSB_BP_CNT_LSB_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_BP_CNT_LSB_BP_CNT_LSB_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_BP_CNT_MSB_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00001a60) +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_BP_CNT_MSB_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001a60) +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_BP_CNT_MSB_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001a60) +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_BP_CNT_MSB_RMSK 0xffff +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_BP_CNT_MSB_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_BP_CNT_MSB_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_BP_CNT_MSB_ADDR, HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_BP_CNT_MSB_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_BP_CNT_MSB_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_BP_CNT_MSB_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_BP_CNT_MSB_BP_CNT_MSB_BMSK 0xffff +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_BP_CNT_MSB_BP_CNT_MSB_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00001a64) +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001a64) +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001a64) +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB_ADDR, HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB_BP_AND_PENDING_CNT_LSB_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB_BP_AND_PENDING_CNT_LSB_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00001a68) +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001a68) +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001a68) +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB_RMSK 0xffff +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB_ADDR, HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB_BP_AND_PENDING_CNT_MSB_BMSK 0xffff +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB_BP_AND_PENDING_CNT_MSB_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00001a6c) +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001a6c) +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001a6c) +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB_ADDR, HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB_MCS_BUSY_CNT_LSB_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB_MCS_BUSY_CNT_LSB_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00001a70) +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001a70) +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001a70) +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB_RMSK 0xffff +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB_ADDR, HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB_MCS_BUSY_CNT_MSB_BMSK 0xffff +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB_MCS_BUSY_CNT_MSB_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00001a74) +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001a74) +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001a74) +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB_ADDR, HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB_MCS_IDLE_CNT_LSB_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB_MCS_IDLE_CNT_LSB_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00001a78) +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001a78) +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001a78) +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_RMSK 0xffff +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_ADDR, HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_MCS_IDLE_CNT_MSB_BMSK 0xffff +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_MCS_IDLE_CNT_MSB_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00014000 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00014000 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00014000 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_MAXk 27 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_INI2(n,k) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_ADDR(n,k), HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_ADDR(n,k), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_ADDR(n,k),val) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_ADDR(n,k),mask,val,HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_INI2(n,k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_ELEMENT_SIZE_BMSK 0xff000000 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_ELEMENT_SIZE_SHFT 0x18 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_BMSK 0xf00000 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_SHFT 0x14 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_NOT_ALLOCATED_FVAL 0x0 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_ALLOCATED_FVAL 0x1 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_STARTED_FVAL 0x2 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_STOPED_FVAL 0x3 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_STOP_IN_PROC_FVAL 0x4 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_ERROR_FVAL 0xf +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHID_BMSK 0xff000 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHID_SHFT 0xc +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_EE_BMSK 0xf00 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_EE_SHFT 0x8 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_DIR_BMSK 0x80 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_DIR_SHFT 0x7 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_DIR_INBOUND_FVAL 0x0 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_DIR_OUTBOUND_FVAL 0x1 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_BMSK 0x7f +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_SHFT 0x0 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_MHI_FVAL 0x0 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_XHCI_FVAL 0x1 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_GPI_FVAL 0x2 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_XDCI_FVAL 0x3 + +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00014004 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00014004 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00014004 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_MAXk 27 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_INI2(n,k) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_ADDR(n,k), HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_ADDR(n,k), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_ADDR(n,k),val) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_ADDR(n,k),mask,val,HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_INI2(n,k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_ERINDEX_BMSK 0xff000000 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_ERINDEX_SHFT 0x18 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_R_LENGTH_BMSK 0xffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_R_LENGTH_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00014008 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00014008 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00014008 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_MAXk 27 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_INI2(n,k) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_ADDR(n,k), HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_ADDR(n,k), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_ADDR(n,k),val) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_ADDR(n,k),mask,val,HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_INI2(n,k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_R_BASE_ADDR_LSBS_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_R_BASE_ADDR_LSBS_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x0001400c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001400c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001400c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_MAXk 27 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_INI2(n,k) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_ADDR(n,k), HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_ADDR(n,k), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_ADDR(n,k),val) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_ADDR(n,k),mask,val,HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_INI2(n,k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_R_BASE_ADDR_MSBS_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_R_BASE_ADDR_MSBS_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00014010 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00014010 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00014010 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_MAXk 27 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_INI2(n,k) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_ADDR(n,k), HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_ADDR(n,k), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_ADDR(n,k),val) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_ADDR(n,k),mask,val,HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_INI2(n,k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_READ_PTR_LSB_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_READ_PTR_LSB_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00014014 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00014014 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00014014 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_MAXk 27 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_INI2(n,k) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_ADDR(n,k), HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_ADDR(n,k), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_READ_PTR_MSB_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_READ_PTR_MSB_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00014018 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00014018 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00014018 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_MAXk 27 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_INI2(n,k) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_ADDR(n,k), HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_ADDR(n,k), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_WRITE_PTR_LSB_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_WRITE_PTR_LSB_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x0001401c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001401c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001401c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_MAXk 27 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_INI2(n,k) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_ADDR(n,k), HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_ADDR(n,k), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_WRITE_PTR_MSB_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_WRITE_PTR_MSB_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_8_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00014020 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_8_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00014020 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_8_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00014020 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_8_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_8_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_8_MAXk 27 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_8_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_8_INI2(n,k) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_8_ADDR(n,k), HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_8_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_8_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_8_ADDR(n,k), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_8_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_8_ADDR(n,k),val) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_8_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_8_ADDR(n,k),mask,val,HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_8_INI2(n,k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_8_DB_MSI_DATA_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_8_DB_MSI_DATA_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00014024 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00014024 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00014024 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_RMSK 0xf +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_MAXk 27 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_INI2(n,k) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_ADDR(n,k), HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_ADDR(n,k), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_ELEM_SIZE_SHIFT_BMSK 0xf +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_ELEM_SIZE_SHIFT_SHFT 0x0 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_ELEM_SIZE_SHIFT_TWO_FVAL 0x0 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_ELEM_SIZE_SHIFT_THREE_FVAL 0x1 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_ELEM_SIZE_SHIFT_FOUR_FVAL 0x2 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_ELEM_SIZE_SHIFT_FIVE_FVAL 0x3 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT_ELEM_SIZE_SHIFT_SIX_FVAL 0x4 + +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00014028 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00014028 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00014028 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_RMSK 0xffff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_MAXk 27 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_INI2(n,k) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_ADDR(n,k), HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_ADDR(n,k), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_ADDR(n,k),val) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_ADDR(n,k),mask,val,HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_INI2(n,k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_CH_ALMST_EMPTY_THRSHOLD_BMSK 0xffff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD_CH_ALMST_EMPTY_THRSHOLD_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00014040 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00014040 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00014040 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_RMSK 0xffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_MAXk 27 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_INI2(n,k) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_ADDR(n,k), HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_ADDR(n,k), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_ADDR(n,k),val) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_ADDR(n,k),mask,val,HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_INI2(n,k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_READ_PTR_BMSK 0xffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_READ_PTR_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00014044 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00014044 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00014044 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_RMSK 0xffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_MAXk 27 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_INI2(n,k) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_ADDR(n,k), HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_ADDR(n,k), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_ADDR(n,k),val) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_ADDR(n,k),mask,val,HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_INI2(n,k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_RE_INTR_DB_BMSK 0xffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_RE_INTR_DB_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_QOS_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00014048 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_QOS_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00014048 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_QOS_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00014048 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_QOS_RMSK 0x3ff3f0f +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_QOS_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_QOS_MAXk 27 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_QOS_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_QOS_INI2(n,k) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_QOS_ADDR(n,k), HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_QOS_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_QOS_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_QOS_ADDR(n,k), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_QOS_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_QOS_ADDR(n,k),val) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_QOS_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_QOS_ADDR(n,k),mask,val,HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_QOS_INI2(n,k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_QOS_LOW_LATENCY_EN_BMSK 0x2000000 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_QOS_LOW_LATENCY_EN_SHFT 0x19 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_QOS_DB_IN_BYTES_BMSK 0x1000000 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_QOS_DB_IN_BYTES_SHFT 0x18 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_QOS_EMPTY_LVL_THRSHOLD_BMSK 0xff0000 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_QOS_EMPTY_LVL_THRSHOLD_SHFT 0x10 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_QOS_PREFETCH_MODE_BMSK 0x3c00 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_QOS_PREFETCH_MODE_SHFT 0xa +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_QOS_PREFETCH_MODE_USE_PREFETCH_BUFS_FVAL 0x0 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_QOS_PREFETCH_MODE_ESCAPE_BUF_ONLY_FVAL 0x1 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_QOS_PREFETCH_MODE_SMART_PRE_FETCH_FVAL 0x2 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_QOS_PREFETCH_MODE_FREE_PRE_FETCH_FVAL 0x3 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_QOS_USE_DB_ENG_BMSK 0x200 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_QOS_USE_DB_ENG_SHFT 0x9 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_QOS_MAX_PREFETCH_BMSK 0x100 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_QOS_MAX_PREFETCH_SHFT 0x8 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_QOS_MAX_PREFETCH_ONE_PREFETCH_SEG_FVAL 0x0 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_QOS_MAX_PREFETCH_TWO_PREFETCH_SEG_FVAL 0x1 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_QOS_WRR_WEIGHT_BMSK 0xf +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_QOS_WRR_WEIGHT_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x0001404c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001404c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001404c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_MAXk 27 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_INI2(n,k) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_ADDR(n,k), HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_ADDR(n,k), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_ADDR(n,k),val) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_ADDR(n,k),mask,val,HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_INI2(n,k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_SCRATCH_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_SCRATCH_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00014050 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00014050 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00014050 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_MAXk 27 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_INI2(n,k) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_ADDR(n,k), HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_ADDR(n,k), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_ADDR(n,k),val) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_ADDR(n,k),mask,val,HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_INI2(n,k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_SCRATCH_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_SCRATCH_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00014054 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00014054 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00014054 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_MAXk 27 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_INI2(n,k) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_ADDR(n,k), HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_ADDR(n,k), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_ADDR(n,k),val) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_ADDR(n,k),mask,val,HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_INI2(n,k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_SCRATCH_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_SCRATCH_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00014058 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00014058 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00014058 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_MAXk 27 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_INI2(n,k) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_ADDR(n,k), HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_ADDR(n,k), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_ADDR(n,k),val) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_ADDR(n,k),mask,val,HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_INI2(n,k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_SCRATCH_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_SCRATCH_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_4_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x0001405c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_4_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001405c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_4_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001405c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_4_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_4_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_4_MAXk 27 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_4_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_4_INI2(n,k) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_4_ADDR(n,k), HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_4_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_4_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_4_ADDR(n,k), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_4_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_4_ADDR(n,k),val) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_4_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_4_ADDR(n,k),mask,val,HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_4_INI2(n,k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_4_SCRATCH_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_4_SCRATCH_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_5_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00014060 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_5_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00014060 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_5_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00014060 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_5_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_5_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_5_MAXk 27 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_5_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_5_INI2(n,k) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_5_ADDR(n,k), HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_5_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_5_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_5_ADDR(n,k), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_5_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_5_ADDR(n,k),val) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_5_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_5_ADDR(n,k),mask,val,HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_5_INI2(n,k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_5_SCRATCH_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_5_SCRATCH_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_6_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00014064 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_6_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00014064 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_6_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00014064 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_6_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_6_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_6_MAXk 27 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_6_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_6_INI2(n,k) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_6_ADDR(n,k), HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_6_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_6_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_6_ADDR(n,k), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_6_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_6_ADDR(n,k),val) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_6_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_6_ADDR(n,k),mask,val,HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_6_INI2(n,k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_6_SCRATCH_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_6_SCRATCH_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_7_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00014068 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_7_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00014068 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_7_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00014068 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_7_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_7_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_7_MAXk 27 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_7_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_7_INI2(n,k) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_7_ADDR(n,k), HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_7_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_7_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_7_ADDR(n,k), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_7_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_7_ADDR(n,k),val) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_7_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_7_ADDR(n,k),mask,val,HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_7_INI2(n,k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_7_SCRATCH_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_7_SCRATCH_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_8_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x0001406c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_8_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001406c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_8_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001406c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_8_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_8_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_8_MAXk 27 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_8_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_8_INI2(n,k) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_8_ADDR(n,k), HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_8_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_8_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_8_ADDR(n,k), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_8_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_8_ADDR(n,k),val) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_8_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_8_ADDR(n,k),mask,val,HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_8_INI2(n,k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_8_SCRATCH_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_8_SCRATCH_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_9_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00014070 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_9_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00014070 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_9_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00014070 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_9_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_9_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_9_MAXk 27 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_9_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_9_INI2(n,k) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_9_ADDR(n,k), HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_9_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_9_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_9_ADDR(n,k), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_9_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_9_ADDR(n,k),val) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_9_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_9_ADDR(n,k),mask,val,HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_9_INI2(n,k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_9_SCRATCH_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_9_SCRATCH_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00014074 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00014074 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00014074 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_RMSK 0xffff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_MAXk 27 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_INI2(n,k) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_ADDR(n,k), HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_ADDR(n,k), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_ADDR(n,k),val) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_ADDR(n,k),mask,val,HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_INI2(n,k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_LAST_DB_2_MCS_BMSK 0xffff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_LAST_DB_2_MCS_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x0001c000 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c000 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c000 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_MAXk 26 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_INI2(n,k) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_ADDR(n,k), HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_ADDR(n,k), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_ADDR(n,k),val) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_ADDR(n,k),mask,val,HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_INI2(n,k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_ELEMENT_SIZE_BMSK 0xff000000 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_ELEMENT_SIZE_SHFT 0x18 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_CHSTATE_BMSK 0xf00000 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_CHSTATE_SHFT 0x14 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_CHSTATE_NOT_ALLOCATED_FVAL 0x0 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_CHSTATE_ALLOCATED_FVAL 0x1 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_EE_BMSK 0xf0000 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_EE_SHFT 0x10 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_EVCHID_BMSK 0xff00 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_EVCHID_SHFT 0x8 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_INTYPE_BMSK 0x80 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_INTYPE_SHFT 0x7 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_INTYPE_MSI_FVAL 0x0 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_INTYPE_IRQ_FVAL 0x1 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_CHTYPE_BMSK 0x7f +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_CHTYPE_SHFT 0x0 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_CHTYPE_MHI_EV_FVAL 0x0 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_CHTYPE_XHCI_EV_FVAL 0x1 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_CHTYPE_GPI_EV_FVAL 0x2 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_CHTYPE_XDCI_FVAL 0x3 + +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x0001c004 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c004 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c004 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_RMSK 0xffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_MAXk 26 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_INI2(n,k) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_ADDR(n,k), HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_ADDR(n,k), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_ADDR(n,k),val) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_ADDR(n,k),mask,val,HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_INI2(n,k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_R_LENGTH_BMSK 0xffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_R_LENGTH_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x0001c008 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c008 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c008 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_MAXk 26 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_INI2(n,k) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_ADDR(n,k), HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_ADDR(n,k), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_ADDR(n,k),val) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_ADDR(n,k),mask,val,HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_INI2(n,k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_R_BASE_ADDR_LSBS_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_R_BASE_ADDR_LSBS_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x0001c00c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c00c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c00c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_MAXk 26 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_INI2(n,k) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_ADDR(n,k), HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_ADDR(n,k), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_ADDR(n,k),val) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_ADDR(n,k),mask,val,HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_INI2(n,k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_R_BASE_ADDR_MSBS_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_R_BASE_ADDR_MSBS_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x0001c010 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c010 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c010 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_MAXk 26 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_INI2(n,k) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_ADDR(n,k), HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_ADDR(n,k), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_ADDR(n,k),val) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_ADDR(n,k),mask,val,HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_INI2(n,k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_READ_PTR_LSB_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_READ_PTR_LSB_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x0001c014 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c014 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c014 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_MAXk 26 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_INI2(n,k) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_ADDR(n,k), HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_ADDR(n,k), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_READ_PTR_MSB_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_READ_PTR_MSB_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x0001c018 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c018 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c018 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_MAXk 26 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_INI2(n,k) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_ADDR(n,k), HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_ADDR(n,k), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_WRITE_PTR_LSB_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_WRITE_PTR_LSB_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x0001c01c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c01c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c01c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_MAXk 26 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_INI2(n,k) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_ADDR(n,k), HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_ADDR(n,k), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_WRITE_PTR_MSB_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_WRITE_PTR_MSB_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x0001c020 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c020 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c020 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_MAXk 26 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_INI2(n,k) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_ADDR(n,k), HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_ADDR(n,k), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_ADDR(n,k),val) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_ADDR(n,k),mask,val,HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_INI2(n,k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_INT_MOD_CNT_BMSK 0xff000000 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_INT_MOD_CNT_SHFT 0x18 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_INT_MODC_BMSK 0xff0000 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_INT_MODC_SHFT 0x10 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_INT_MODT_BMSK 0xffff +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_INT_MODT_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x0001c024 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c024 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c024 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_MAXk 26 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_INI2(n,k) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_ADDR(n,k), HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_ADDR(n,k), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_ADDR(n,k),val) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_ADDR(n,k),mask,val,HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_INI2(n,k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_INTVEC_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_INTVEC_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x0001c028 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c028 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c028 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_MAXk 26 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_INI2(n,k) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_ADDR(n,k), HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_ADDR(n,k), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_ADDR(n,k),val) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_ADDR(n,k),mask,val,HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_INI2(n,k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_MSI_ADDR_LSB_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_MSI_ADDR_LSB_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x0001c02c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c02c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c02c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_MAXk 26 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_INI2(n,k) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_ADDR(n,k), HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_ADDR(n,k), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_ADDR(n,k),val) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_ADDR(n,k),mask,val,HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_INI2(n,k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_MSI_ADDR_MSB_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_MSI_ADDR_MSB_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x0001c030 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c030 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c030 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_MAXk 26 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_INI2(n,k) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_ADDR(n,k), HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_ADDR(n,k), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_ADDR(n,k),val) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_ADDR(n,k),mask,val,HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_INI2(n,k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_RP_UPDATE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_RP_UPDATE_ADDR_LSB_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x0001c034 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c034 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c034 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_MAXk 26 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_INI2(n,k) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_ADDR(n,k), HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_ADDR(n,k), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_ADDR(n,k),val) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_ADDR(n,k),mask,val,HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_INI2(n,k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_RP_UPDATE_ADDR_MSB_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_RP_UPDATE_ADDR_MSB_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x0001c038 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c038 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c038 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_RMSK 0xf +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_MAXk 26 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_INI2(n,k) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_ADDR(n,k), HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_ADDR(n,k), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_ELEM_SIZE_SHIFT_BMSK 0xf +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_ELEM_SIZE_SHIFT_SHFT 0x0 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_ELEM_SIZE_SHIFT_TWO_FVAL 0x0 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_ELEM_SIZE_SHIFT_THREE_FVAL 0x1 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_ELEM_SIZE_SHIFT_FOUR_FVAL 0x2 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_ELEM_SIZE_SHIFT_FIVE_FVAL 0x3 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_ELEM_SIZE_SHIFT_ELEM_SIZE_SHIFT_SIX_FVAL 0x4 + +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x0001c048 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c048 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c048 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_MAXk 26 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_INI2(n,k) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_ADDR(n,k), HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_ADDR(n,k), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_ADDR(n,k),val) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_ADDR(n,k),mask,val,HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_INI2(n,k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_SCRATCH_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_SCRATCH_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x0001c04c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c04c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c04c + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_MAXk 26 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_INI2(n,k) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_ADDR(n,k), HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_ADDR(n,k), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_ADDR(n,k),val) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_ADDR(n,k),mask,val,HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_INI2(n,k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_SCRATCH_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_SCRATCH_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_SCRATCH_2_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x0001c050 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_SCRATCH_2_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c050 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_SCRATCH_2_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c050 + 0x12000 * (n) + 0x80 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_SCRATCH_2_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_SCRATCH_2_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_SCRATCH_2_MAXk 26 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_SCRATCH_2_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_SCRATCH_2_INI2(n,k) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_SCRATCH_2_ADDR(n,k), HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_SCRATCH_2_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_SCRATCH_2_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_SCRATCH_2_ADDR(n,k), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_SCRATCH_2_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_SCRATCH_2_ADDR(n,k),val) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_SCRATCH_2_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_SCRATCH_2_ADDR(n,k),mask,val,HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_SCRATCH_2_INI2(n,k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_SCRATCH_2_SCRATCH_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_SCRATCH_2_SCRATCH_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_0_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00024000 + 0x12000 * (n) + 0x8 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_0_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00024000 + 0x12000 * (n) + 0x8 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_0_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00024000 + 0x12000 * (n) + 0x8 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_0_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_0_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_0_MAXk 27 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_0_ATTR 0x2 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_0_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_0_ADDR(n,k),val) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_0_WRITE_PTR_LSB_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_0_WRITE_PTR_LSB_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_1_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00024004 + 0x12000 * (n) + 0x8 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_1_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00024004 + 0x12000 * (n) + 0x8 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_1_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00024004 + 0x12000 * (n) + 0x8 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_1_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_1_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_1_MAXk 27 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_1_ATTR 0x2 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_1_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_1_ADDR(n,k),val) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_1_WRITE_PTR_MSB_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_1_WRITE_PTR_MSB_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_DOORBELL_0_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00024800 + 0x12000 * (n) + 0x8 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_DOORBELL_0_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00024800 + 0x12000 * (n) + 0x8 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_DOORBELL_0_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00024800 + 0x12000 * (n) + 0x8 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_DOORBELL_0_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_DOORBELL_0_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_DOORBELL_0_MAXk 26 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_DOORBELL_0_ATTR 0x2 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_DOORBELL_0_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_DOORBELL_0_ADDR(n,k),val) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_DOORBELL_0_WRITE_PTR_LSB_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_DOORBELL_0_WRITE_PTR_LSB_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_DOORBELL_1_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00024804 + 0x12000 * (n) + 0x8 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_DOORBELL_1_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00024804 + 0x12000 * (n) + 0x8 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_DOORBELL_1_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00024804 + 0x12000 * (n) + 0x8 * (k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_DOORBELL_1_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_DOORBELL_1_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_DOORBELL_1_MAXk 26 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_DOORBELL_1_ATTR 0x2 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_DOORBELL_1_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_DOORBELL_1_ADDR(n,k),val) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_DOORBELL_1_WRITE_PTR_MSB_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_k_DOORBELL_1_WRITE_PTR_MSB_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_STATUS_ADDR(n) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00025000 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_STATUS_PHYS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00025000 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_STATUS_OFFS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00025000 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_STATUS_RMSK 0x1 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_STATUS_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_STATUS_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_STATUS_INI(n) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_STATUS_ADDR(n), HWIO_IPA_0_GSI_TOP_EE_n_GSI_STATUS_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_STATUS_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_STATUS_ADDR(n), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_STATUS_ENABLED_BMSK 0x1 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_STATUS_ENABLED_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_CMD_ADDR(n) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00025008 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_CMD_PHYS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00025008 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_CMD_OFFS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00025008 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_CMD_RMSK 0xff0000ff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_CMD_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_CMD_ATTR 0x2 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_CMD_OUTI(n,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_CMD_ADDR(n),val) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_CMD_OPCODE_BMSK 0xff000000 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_CMD_OPCODE_SHFT 0x18 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_CMD_OPCODE_ALLOCATE_FVAL 0x0 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_CMD_OPCODE_START_FVAL 0x1 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_CMD_OPCODE_STOP_FVAL 0x2 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_CMD_OPCODE_RESET_FVAL 0x9 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_CMD_OPCODE_DE_ALLOC_FVAL 0xa +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_CMD_OPCODE_DB_STOP_FVAL 0xb +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_CMD_CHID_BMSK 0xff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_CH_CMD_CHID_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_CMD_ADDR(n) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00025010 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_CMD_PHYS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00025010 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_CMD_OFFS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00025010 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_CMD_RMSK 0xff0000ff +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_CMD_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_CMD_ATTR 0x2 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_CMD_OUTI(n,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_CMD_ADDR(n),val) +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_CMD_OPCODE_BMSK 0xff000000 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_CMD_OPCODE_SHFT 0x18 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_CMD_OPCODE_ALLOCATE_FVAL 0x0 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_CMD_OPCODE_RESET_FVAL 0x9 +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_CMD_OPCODE_DE_ALLOC_FVAL 0xa +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_CMD_CHID_BMSK 0xff +#define HWIO_IPA_0_GSI_TOP_EE_n_EV_CH_CMD_CHID_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_EE_GENERIC_CMD_ADDR(n) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00025018 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_EE_GENERIC_CMD_PHYS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00025018 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_EE_GENERIC_CMD_OFFS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00025018 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_EE_GENERIC_CMD_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_EE_GENERIC_CMD_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_EE_GENERIC_CMD_ATTR 0x2 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_EE_GENERIC_CMD_OUTI(n,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_EE_n_GSI_EE_GENERIC_CMD_ADDR(n),val) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_EE_GENERIC_CMD_OPCODE_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_EE_GENERIC_CMD_OPCODE_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_0_ADDR(n) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00025038 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_0_PHYS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00025038 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_0_OFFS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00025038 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_0_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_0_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_0_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_0_INI(n) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_0_ADDR(n), HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_0_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_0_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_0_ADDR(n), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_0_USE_AXI_M_BMSK 0x80000000 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_0_USE_AXI_M_SHFT 0x1f +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_0_PERIPH_SEC_GRP_BMSK 0x7c000000 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_0_PERIPH_SEC_GRP_SHFT 0x1a +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_0_PERIPH_CONF_ADDR_BUS_W_BMSK 0x3e00000 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_0_PERIPH_CONF_ADDR_BUS_W_SHFT 0x15 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_0_NUM_EES_BMSK 0x1f0000 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_0_NUM_EES_SHFT 0x10 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_0_GSI_CH_NUM_BMSK 0xff00 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_0_GSI_CH_NUM_SHFT 0x8 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_0_GSI_EV_CH_NUM_BMSK 0xff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_0_GSI_EV_CH_NUM_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_1_ADDR(n) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x0002503c + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_1_PHYS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x0002503c + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_1_OFFS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x0002503c + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_1_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_1_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_1_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_1_INI(n) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_1_ADDR(n), HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_1_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_1_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_1_ADDR(n), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_1_GSI_BLK_INT_ACCESS_REGION_2_EN_BMSK 0x80000000 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_1_GSI_BLK_INT_ACCESS_REGION_2_EN_SHFT 0x1f +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_1_GSI_BLK_INT_ACCESS_REGION_1_EN_BMSK 0x40000000 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_1_GSI_BLK_INT_ACCESS_REGION_1_EN_SHFT 0x1e +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_1_GSI_SIMPLE_RD_WR_BMSK 0x20000000 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_1_GSI_SIMPLE_RD_WR_SHFT 0x1d +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_1_GSI_ESCAPE_BUF_ONLY_BMSK 0x10000000 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_1_GSI_ESCAPE_BUF_ONLY_SHFT 0x1c +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_1_GSI_USE_UC_IF_BMSK 0x8000000 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_1_GSI_USE_UC_IF_SHFT 0x1b +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_1_GSI_USE_DB_ENG_BMSK 0x4000000 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_1_GSI_USE_DB_ENG_SHFT 0x1a +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_1_GSI_USE_BP_MTRIX_BMSK 0x2000000 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_1_GSI_USE_BP_MTRIX_SHFT 0x19 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_1_GSI_NUM_TIMERS_BMSK 0x1f00000 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_1_GSI_NUM_TIMERS_SHFT 0x14 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_1_GSI_USE_XPU_BMSK 0x80000 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_1_GSI_USE_XPU_SHFT 0x13 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_1_GSI_QRIB_EN_BMSK 0x40000 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_1_GSI_QRIB_EN_SHFT 0x12 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_1_GSI_VMIDACR_EN_BMSK 0x20000 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_1_GSI_VMIDACR_EN_SHFT 0x11 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_1_GSI_SEC_EN_BMSK 0x10000 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_1_GSI_SEC_EN_SHFT 0x10 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_1_GSI_NONSEC_EN_BMSK 0xf000 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_1_GSI_NONSEC_EN_SHFT 0xc +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_1_GSI_NUM_QAD_BMSK 0xf00 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_1_GSI_NUM_QAD_SHFT 0x8 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_1_GSI_M_DATA_BUS_W_BMSK 0xff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_1_GSI_M_DATA_BUS_W_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_2_ADDR(n) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00025040 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_2_PHYS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00025040 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_2_OFFS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00025040 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_2_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_2_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_2_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_2_INI(n) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_2_ADDR(n), HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_2_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_2_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_2_ADDR(n), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_2_GSI_USE_INTER_EE_BMSK 0x80000000 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_2_GSI_USE_INTER_EE_SHFT 0x1f +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_2_GSI_USE_RD_WR_ENG_BMSK 0x40000000 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_2_GSI_USE_RD_WR_ENG_SHFT 0x1e +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_2_GSI_SDMA_N_IOVEC_BMSK 0x38000000 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_2_GSI_SDMA_N_IOVEC_SHFT 0x1b +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_2_GSI_SDMA_MAX_BURST_BMSK 0x7f80000 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_2_GSI_SDMA_MAX_BURST_SHFT 0x13 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_2_GSI_SDMA_N_INT_BMSK 0x70000 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_2_GSI_SDMA_N_INT_SHFT 0x10 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_2_GSI_USE_SDMA_BMSK 0x8000 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_2_GSI_USE_SDMA_SHFT 0xf +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_2_GSI_CH_FULL_LOGIC_BMSK 0x4000 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_2_GSI_CH_FULL_LOGIC_SHFT 0xe +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_2_GSI_CH_PEND_TRANSLATE_BMSK 0x2000 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_2_GSI_CH_PEND_TRANSLATE_SHFT 0xd +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_BMSK 0x1f00 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_SHFT 0x8 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_ONE_KB_FVAL 0x0 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_TWO_KB_FVAL 0x1 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_TWO_N_HALF_KB_FVAL 0x2 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_THREE_KB_FVAL 0x3 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_THREE_N_HALF_KB_FVAL 0x4 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_FOUR_KB_FVAL 0x5 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_2_GSI_NUM_CH_PER_EE_BMSK 0xff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_2_GSI_NUM_CH_PER_EE_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_MCS_CODE_VER_ADDR(n) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00025048 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_MCS_CODE_VER_PHYS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00025048 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_MCS_CODE_VER_OFFS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00025048 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_MCS_CODE_VER_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_MCS_CODE_VER_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_MCS_CODE_VER_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_MCS_CODE_VER_INI(n) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_MCS_CODE_VER_ADDR(n), HWIO_IPA_0_GSI_TOP_EE_n_GSI_MCS_CODE_VER_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_MCS_CODE_VER_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_MCS_CODE_VER_ADDR(n), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_MCS_CODE_VER_VER_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_MCS_CODE_VER_VER_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_3_ADDR(n) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x0002504c + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_3_PHYS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x0002504c + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_3_OFFS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x0002504c + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_3_RMSK 0x1fffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_3_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_3_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_3_INI(n) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_3_ADDR(n), HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_3_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_3_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_3_ADDR(n), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_3_GSI_USE_DB_MSI_MODE_BMSK 0x10000000 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_3_GSI_USE_DB_MSI_MODE_SHFT 0x1c +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_3_GSI_USE_SLEEP_CLK_DIV_BMSK 0x8000000 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_3_GSI_USE_SLEEP_CLK_DIV_SHFT 0x1b +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_3_GSI_USE_VIR_CH_IF_BMSK 0x4000000 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_3_GSI_USE_VIR_CH_IF_SHFT 0x1a +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_3_GSI_USE_IROM_BMSK 0x2000000 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_3_GSI_USE_IROM_SHFT 0x19 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_3_GSI_REE_MAX_BURST_LEN_BMSK 0x1f00000 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_3_GSI_REE_MAX_BURST_LEN_SHFT 0x14 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_3_GSI_M_ADDR_BUS_W_BMSK 0xff000 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_3_GSI_M_ADDR_BUS_W_SHFT 0xc +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_3_GSI_NUM_PREFETCH_BUFS_BMSK 0xf00 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_3_GSI_NUM_PREFETCH_BUFS_SHFT 0x8 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_3_GSI_SDMA_MAX_OS_WR_BMSK 0xf0 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_3_GSI_SDMA_MAX_OS_WR_SHFT 0x4 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_3_GSI_SDMA_MAX_OS_RD_BMSK 0xf +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_3_GSI_SDMA_MAX_OS_RD_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_4_ADDR(n) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00025050 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_4_PHYS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00025050 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_4_OFFS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00025050 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_4_RMSK 0xffff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_4_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_4_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_4_INI(n) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_4_ADDR(n), HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_4_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_4_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_4_ADDR(n), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_4_GSI_IRAM_PROTCOL_CNT_BMSK 0xff00 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_4_GSI_IRAM_PROTCOL_CNT_SHFT 0x8 +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_4_GSI_NUM_EV_PER_EE_BMSK 0xff +#define HWIO_IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_4_GSI_NUM_EV_PER_EE_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_ADDR(n) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00025080 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_PHYS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00025080 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_OFFS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00025080 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_RMSK 0x7f +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_INI(n) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_ADDR(n), HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_ADDR(n), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_GENERAL_BMSK 0x40 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_GENERAL_SHFT 0x6 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_INTER_EE_EV_CTRL_BMSK 0x20 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_INTER_EE_EV_CTRL_SHFT 0x5 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_INTER_EE_CH_CTRL_BMSK 0x10 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_INTER_EE_CH_CTRL_SHFT 0x4 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_IEOB_BMSK 0x8 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_IEOB_SHFT 0x3 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_GLOB_EE_BMSK 0x4 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_GLOB_EE_SHFT 0x2 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_EV_CTRL_BMSK 0x2 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_EV_CTRL_SHFT 0x1 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_CH_CTRL_BMSK 0x1 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_CH_CTRL_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_ADDR(n) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00025088 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_PHYS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00025088 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_OFFS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00025088 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_RMSK 0x7f +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_INI(n) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_ADDR(n), HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_ADDR(n), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_OUTI(n,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_ADDR(n),val) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_ADDR(n),mask,val,HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_INI(n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_GENERAL_BMSK 0x40 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_GENERAL_SHFT 0x6 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_INTER_EE_EV_CTRL_BMSK 0x20 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_INTER_EE_EV_CTRL_SHFT 0x5 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_INTER_EE_CH_CTRL_BMSK 0x10 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_INTER_EE_CH_CTRL_SHFT 0x4 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_IEOB_BMSK 0x8 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_IEOB_SHFT 0x3 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_GLOB_EE_BMSK 0x4 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_GLOB_EE_SHFT 0x2 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_EV_CTRL_BMSK 0x2 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_EV_CTRL_SHFT 0x1 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_CH_CTRL_BMSK 0x1 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_CH_CTRL_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_k_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00025090 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_k_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00025090 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_k_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00025090 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_k_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_k_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_k_MAXk 0 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_k_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_k_INI2(n,k) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_k_ADDR(n,k), HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_k_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_k_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_k_ADDR(n,k), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_k_GSI_CH_BIT_MAP_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_k_GSI_CH_BIT_MAP_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00025094 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00025094 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00025094 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_MAXk 0 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_INI2(n,k) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_ADDR(n,k), HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_ADDR(n,k), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_ADDR(n,k),val) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_ADDR(n,k),mask,val,HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_INI2(n,k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_GSI_CH_BIT_MAP_MSK_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k_GSI_CH_BIT_MAP_MSK_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_k_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00025098 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_k_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00025098 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_k_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00025098 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_k_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_k_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_k_MAXk 0 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_k_ATTR 0x2 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_k_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_k_ADDR(n,k),val) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_k_GSI_CH_BIT_MAP_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_k_GSI_CH_BIT_MAP_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_k_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x0002509c + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_k_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x0002509c + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_k_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x0002509c + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_k_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_k_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_k_MAXk 0 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_k_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_k_INI2(n,k) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_k_ADDR(n,k), HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_k_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_k_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_k_ADDR(n,k), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_k_EV_CH_BIT_MAP_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_k_EV_CH_BIT_MAP_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x000250a0 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x000250a0 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x000250a0 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_MAXk 0 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_INI2(n,k) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_ADDR(n,k), HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_ADDR(n,k), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_ADDR(n,k),val) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_ADDR(n,k),mask,val,HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_INI2(n,k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_EV_CH_BIT_MAP_MSK_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k_EV_CH_BIT_MAP_MSK_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_k_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x000250a4 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_k_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x000250a4 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_k_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x000250a4 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_k_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_k_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_k_MAXk 0 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_k_ATTR 0x2 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_k_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_k_ADDR(n,k),val) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_k_EV_CH_BIT_MAP_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_k_EV_CH_BIT_MAP_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_k_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x000250a8 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_k_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x000250a8 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_k_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x000250a8 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_k_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_k_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_k_MAXk 0 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_k_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_k_INI2(n,k) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_k_ADDR(n,k), HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_k_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_k_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_k_ADDR(n,k), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_k_EV_CH_BIT_MAP_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_k_EV_CH_BIT_MAP_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x000250ac + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x000250ac + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x000250ac + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_MAXk 0 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_INI2(n,k) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_ADDR(n,k), HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_ADDR(n,k), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_ADDR(n,k),val) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_ADDR(n,k),mask,val,HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_INI2(n,k)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_EV_CH_BIT_MAP_MSK_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k_EV_CH_BIT_MAP_MSK_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_k_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x000250b0 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_k_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x000250b0 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_k_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x000250b0 + 0x24 * (k) + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_k_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_k_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_k_MAXk 0 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_k_ATTR 0x2 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_k_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_k_ADDR(n,k),val) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_k_EV_CH_BIT_MAP_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_k_EV_CH_BIT_MAP_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_ADDR(n) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00025200 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_PHYS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00025200 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_OFFS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00025200 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_RMSK 0xf +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_INI(n) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_ADDR(n), HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_ADDR(n), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT3_BMSK 0x8 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT3_SHFT 0x3 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT2_BMSK 0x4 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT2_SHFT 0x2 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT1_BMSK 0x2 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT1_SHFT 0x1 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_ERROR_INT_BMSK 0x1 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_ERROR_INT_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_EN_ADDR(n) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00025204 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_EN_PHYS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00025204 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_EN_OFFS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00025204 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_EN_RMSK 0xf +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_EN_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_EN_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_EN_INI(n) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_EN_ADDR(n), HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_EN_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_EN_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_EN_ADDR(n), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_EN_OUTI(n,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_EN_ADDR(n),val) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_EN_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_EN_ADDR(n),mask,val,HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_EN_INI(n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_EN_GP_INT3_BMSK 0x8 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_EN_GP_INT3_SHFT 0x3 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_EN_GP_INT2_BMSK 0x4 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_EN_GP_INT2_SHFT 0x2 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_EN_GP_INT1_BMSK 0x2 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_EN_GP_INT1_SHFT 0x1 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_EN_ERROR_INT_BMSK 0x1 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_EN_ERROR_INT_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_CLR_ADDR(n) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00025208 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_CLR_PHYS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00025208 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_CLR_OFFS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00025208 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_CLR_RMSK 0xf +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_CLR_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_CLR_ATTR 0x2 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_CLR_OUTI(n,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_CLR_ADDR(n),val) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_CLR_GP_INT3_BMSK 0x8 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_CLR_GP_INT3_SHFT 0x3 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_CLR_GP_INT2_BMSK 0x4 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_CLR_GP_INT2_SHFT 0x2 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_CLR_GP_INT1_BMSK 0x2 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_CLR_GP_INT1_SHFT 0x1 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_CLR_ERROR_INT_BMSK 0x1 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_CLR_ERROR_INT_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_ADDR(n) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x0002520c + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_PHYS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x0002520c + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_OFFS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x0002520c + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_RMSK 0xf +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_INI(n) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_ADDR(n), HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_ADDR(n), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_GSI_MCS_STACK_OVRFLOW_BMSK 0x8 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_GSI_MCS_STACK_OVRFLOW_SHFT 0x3 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_GSI_CMD_FIFO_OVRFLOW_BMSK 0x4 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_GSI_CMD_FIFO_OVRFLOW_SHFT 0x2 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_GSI_BUS_ERROR_BMSK 0x2 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_GSI_BUS_ERROR_SHFT 0x1 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_GSI_BREAK_POINT_BMSK 0x1 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_GSI_BREAK_POINT_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GSI_IRQ_EN_ADDR(n) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00025210 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GSI_IRQ_EN_PHYS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00025210 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GSI_IRQ_EN_OFFS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00025210 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GSI_IRQ_EN_RMSK 0xf +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GSI_IRQ_EN_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GSI_IRQ_EN_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GSI_IRQ_EN_INI(n) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GSI_IRQ_EN_ADDR(n), HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GSI_IRQ_EN_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GSI_IRQ_EN_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GSI_IRQ_EN_ADDR(n), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GSI_IRQ_EN_OUTI(n,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GSI_IRQ_EN_ADDR(n),val) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GSI_IRQ_EN_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GSI_IRQ_EN_ADDR(n),mask,val,HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GSI_IRQ_EN_INI(n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GSI_IRQ_EN_GSI_MCS_STACK_OVRFLOW_BMSK 0x8 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GSI_IRQ_EN_GSI_MCS_STACK_OVRFLOW_SHFT 0x3 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GSI_IRQ_EN_GSI_CMD_FIFO_OVRFLOW_BMSK 0x4 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GSI_IRQ_EN_GSI_CMD_FIFO_OVRFLOW_SHFT 0x2 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GSI_IRQ_EN_GSI_BUS_ERROR_BMSK 0x2 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GSI_IRQ_EN_GSI_BUS_ERROR_SHFT 0x1 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GSI_IRQ_EN_GSI_BREAK_POINT_BMSK 0x1 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GSI_IRQ_EN_GSI_BREAK_POINT_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GSI_IRQ_CLR_ADDR(n) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00025214 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GSI_IRQ_CLR_PHYS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00025214 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GSI_IRQ_CLR_OFFS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00025214 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GSI_IRQ_CLR_RMSK 0xf +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GSI_IRQ_CLR_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GSI_IRQ_CLR_ATTR 0x2 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GSI_IRQ_CLR_OUTI(n,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GSI_IRQ_CLR_ADDR(n),val) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GSI_IRQ_CLR_GSI_MCS_STACK_OVRFLOW_BMSK 0x8 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GSI_IRQ_CLR_GSI_MCS_STACK_OVRFLOW_SHFT 0x3 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GSI_IRQ_CLR_GSI_CMD_FIFO_OVRFLOW_BMSK 0x4 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GSI_IRQ_CLR_GSI_CMD_FIFO_OVRFLOW_SHFT 0x2 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GSI_IRQ_CLR_GSI_BUS_ERROR_BMSK 0x2 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GSI_IRQ_CLR_GSI_BUS_ERROR_SHFT 0x1 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GSI_IRQ_CLR_GSI_BREAK_POINT_BMSK 0x1 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_GSI_IRQ_CLR_GSI_BREAK_POINT_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_INTSET_ADDR(n) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00025220 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_INTSET_PHYS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00025220 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_INTSET_OFFS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00025220 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_INTSET_RMSK 0x1 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_INTSET_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_INTSET_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_INTSET_INI(n) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_INTSET_ADDR(n), HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_INTSET_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_INTSET_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_INTSET_ADDR(n), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_INTSET_OUTI(n,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_INTSET_ADDR(n),val) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_INTSET_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_INTSET_ADDR(n),mask,val,HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_INTSET_INI(n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_INTSET_INTYPE_BMSK 0x1 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_INTSET_INTYPE_SHFT 0x0 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_INTSET_INTYPE_MSI_FVAL 0x0 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_INTSET_INTYPE_IRQ_FVAL 0x1 + +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB_ADDR(n) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00025230 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB_PHYS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00025230 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB_OFFS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00025230 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB_INI(n) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB_ADDR(n), HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB_ADDR(n), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB_OUTI(n,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB_ADDR(n),val) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB_ADDR(n),mask,val,HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB_INI(n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB_MSI_ADDR_LSB_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB_MSI_ADDR_LSB_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_MSI_BASE_MSB_ADDR(n) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00025234 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_MSI_BASE_MSB_PHYS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00025234 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_MSI_BASE_MSB_OFFS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00025234 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_MSI_BASE_MSB_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_MSI_BASE_MSB_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_MSI_BASE_MSB_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_MSI_BASE_MSB_INI(n) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_MSI_BASE_MSB_ADDR(n), HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_MSI_BASE_MSB_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_MSI_BASE_MSB_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_MSI_BASE_MSB_ADDR(n), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_MSI_BASE_MSB_OUTI(n,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_MSI_BASE_MSB_ADDR(n),val) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_MSI_BASE_MSB_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_MSI_BASE_MSB_ADDR(n),mask,val,HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_MSI_BASE_MSB_INI(n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_MSI_BASE_MSB_MSI_ADDR_MSB_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_MSI_BASE_MSB_MSI_ADDR_MSB_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_INT_VEC_ADDR(n) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00025238 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_INT_VEC_PHYS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00025238 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_INT_VEC_OFFS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00025238 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_INT_VEC_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_INT_VEC_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_INT_VEC_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_INT_VEC_INI(n) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_INT_VEC_ADDR(n), HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_INT_VEC_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_INT_VEC_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_INT_VEC_ADDR(n), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_INT_VEC_OUTI(n,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_INT_VEC_ADDR(n),val) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_INT_VEC_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_INT_VEC_ADDR(n),mask,val,HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_INT_VEC_INI(n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_INT_VEC_INT_VEC_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_INT_VEC_INT_VEC_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_ERROR_LOG_ADDR(n) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00025240 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_ERROR_LOG_PHYS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00025240 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_ERROR_LOG_OFFS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00025240 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_ERROR_LOG_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_ERROR_LOG_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_ERROR_LOG_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_EE_n_ERROR_LOG_INI(n) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_ERROR_LOG_ADDR(n), HWIO_IPA_0_GSI_TOP_EE_n_ERROR_LOG_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_ERROR_LOG_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_ERROR_LOG_ADDR(n), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_ERROR_LOG_OUTI(n,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_EE_n_ERROR_LOG_ADDR(n),val) +#define HWIO_IPA_0_GSI_TOP_EE_n_ERROR_LOG_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_EE_n_ERROR_LOG_ADDR(n),mask,val,HWIO_IPA_0_GSI_TOP_EE_n_ERROR_LOG_INI(n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_ERROR_LOG_ERROR_LOG_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_ERROR_LOG_ERROR_LOG_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_ERROR_LOG_CLR_ADDR(n) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00025244 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_ERROR_LOG_CLR_PHYS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00025244 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_ERROR_LOG_CLR_OFFS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00025244 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_ERROR_LOG_CLR_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_ERROR_LOG_CLR_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_ERROR_LOG_CLR_ATTR 0x2 +#define HWIO_IPA_0_GSI_TOP_EE_n_ERROR_LOG_CLR_OUTI(n,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_EE_n_ERROR_LOG_CLR_ADDR(n),val) +#define HWIO_IPA_0_GSI_TOP_EE_n_ERROR_LOG_CLR_ERROR_LOG_CLR_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_ERROR_LOG_CLR_ERROR_LOG_CLR_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SCRATCH_0_ADDR(n) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00025400 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SCRATCH_0_PHYS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00025400 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SCRATCH_0_OFFS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00025400 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SCRATCH_0_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SCRATCH_0_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SCRATCH_0_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SCRATCH_0_INI(n) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SCRATCH_0_ADDR(n), HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SCRATCH_0_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SCRATCH_0_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SCRATCH_0_ADDR(n), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SCRATCH_0_OUTI(n,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SCRATCH_0_ADDR(n),val) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SCRATCH_0_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SCRATCH_0_ADDR(n),mask,val,HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SCRATCH_0_INI(n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SCRATCH_0_SCRATCH_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SCRATCH_0_SCRATCH_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SCRATCH_1_ADDR(n) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x00025404 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SCRATCH_1_PHYS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x00025404 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SCRATCH_1_OFFS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x00025404 + 0x12000 * (n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SCRATCH_1_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SCRATCH_1_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SCRATCH_1_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SCRATCH_1_INI(n) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SCRATCH_1_ADDR(n), HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SCRATCH_1_RMSK) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SCRATCH_1_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SCRATCH_1_ADDR(n), mask) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SCRATCH_1_OUTI(n,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SCRATCH_1_ADDR(n),val) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SCRATCH_1_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SCRATCH_1_ADDR(n),mask,val,HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SCRATCH_1_INI(n)) +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SCRATCH_1_SCRATCH_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_EE_n_CNTXT_SCRATCH_1_SCRATCH_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_CFG_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x0000b000) +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_CFG_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000b000) +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_CFG_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000b000) +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_CFG_RMSK 0x1 +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_CFG_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_CFG_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_MCS_CFG_ADDR, HWIO_IPA_0_GSI_TOP_GSI_MCS_CFG_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_CFG_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_MCS_CFG_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_CFG_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_MCS_CFG_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_GSI_MCS_CFG_ADDR,m,v,HWIO_IPA_0_GSI_TOP_GSI_MCS_CFG_IN) +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_CFG_MCS_ENABLE_BMSK 0x1 +#define HWIO_IPA_0_GSI_TOP_GSI_MCS_CFG_MCS_ENABLE_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_TZ_FW_AUTH_LOCK_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x0000b008) +#define HWIO_IPA_0_GSI_TOP_GSI_TZ_FW_AUTH_LOCK_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000b008) +#define HWIO_IPA_0_GSI_TOP_GSI_TZ_FW_AUTH_LOCK_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000b008) +#define HWIO_IPA_0_GSI_TOP_GSI_TZ_FW_AUTH_LOCK_RMSK 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_TZ_FW_AUTH_LOCK_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_TZ_FW_AUTH_LOCK_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_TZ_FW_AUTH_LOCK_ADDR, HWIO_IPA_0_GSI_TOP_GSI_TZ_FW_AUTH_LOCK_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_TZ_FW_AUTH_LOCK_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_TZ_FW_AUTH_LOCK_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_TZ_FW_AUTH_LOCK_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_TZ_FW_AUTH_LOCK_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_GSI_TZ_FW_AUTH_LOCK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_GSI_TZ_FW_AUTH_LOCK_ADDR,m,v,HWIO_IPA_0_GSI_TOP_GSI_TZ_FW_AUTH_LOCK_IN) +#define HWIO_IPA_0_GSI_TOP_GSI_TZ_FW_AUTH_LOCK_DIS_DEBUG_SHRAM_WRITE_BMSK 0x2 +#define HWIO_IPA_0_GSI_TOP_GSI_TZ_FW_AUTH_LOCK_DIS_DEBUG_SHRAM_WRITE_SHFT 0x1 +#define HWIO_IPA_0_GSI_TOP_GSI_TZ_FW_AUTH_LOCK_DIS_IRAM_WRITE_BMSK 0x1 +#define HWIO_IPA_0_GSI_TOP_GSI_TZ_FW_AUTH_LOCK_DIS_IRAM_WRITE_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_MSA_FW_AUTH_LOCK_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x0000b010) +#define HWIO_IPA_0_GSI_TOP_GSI_MSA_FW_AUTH_LOCK_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000b010) +#define HWIO_IPA_0_GSI_TOP_GSI_MSA_FW_AUTH_LOCK_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000b010) +#define HWIO_IPA_0_GSI_TOP_GSI_MSA_FW_AUTH_LOCK_RMSK 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_MSA_FW_AUTH_LOCK_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_MSA_FW_AUTH_LOCK_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_MSA_FW_AUTH_LOCK_ADDR, HWIO_IPA_0_GSI_TOP_GSI_MSA_FW_AUTH_LOCK_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_MSA_FW_AUTH_LOCK_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_MSA_FW_AUTH_LOCK_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_MSA_FW_AUTH_LOCK_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_MSA_FW_AUTH_LOCK_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_GSI_MSA_FW_AUTH_LOCK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_GSI_MSA_FW_AUTH_LOCK_ADDR,m,v,HWIO_IPA_0_GSI_TOP_GSI_MSA_FW_AUTH_LOCK_IN) +#define HWIO_IPA_0_GSI_TOP_GSI_MSA_FW_AUTH_LOCK_DIS_DEBUG_SHRAM_WRITE_BMSK 0x2 +#define HWIO_IPA_0_GSI_TOP_GSI_MSA_FW_AUTH_LOCK_DIS_DEBUG_SHRAM_WRITE_SHFT 0x1 +#define HWIO_IPA_0_GSI_TOP_GSI_MSA_FW_AUTH_LOCK_DIS_IRAM_WRITE_BMSK 0x1 +#define HWIO_IPA_0_GSI_TOP_GSI_MSA_FW_AUTH_LOCK_DIS_IRAM_WRITE_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_GSI_SP_FW_AUTH_LOCK_ADDR (IPA_0_GSI_TOP_GSI_REG_BASE + 0x0000b018) +#define HWIO_IPA_0_GSI_TOP_GSI_SP_FW_AUTH_LOCK_PHYS (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000b018) +#define HWIO_IPA_0_GSI_TOP_GSI_SP_FW_AUTH_LOCK_OFFS (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000b018) +#define HWIO_IPA_0_GSI_TOP_GSI_SP_FW_AUTH_LOCK_RMSK 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_SP_FW_AUTH_LOCK_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_GSI_SP_FW_AUTH_LOCK_IN \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_SP_FW_AUTH_LOCK_ADDR, HWIO_IPA_0_GSI_TOP_GSI_SP_FW_AUTH_LOCK_RMSK) +#define HWIO_IPA_0_GSI_TOP_GSI_SP_FW_AUTH_LOCK_INM(m) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_GSI_SP_FW_AUTH_LOCK_ADDR, m) +#define HWIO_IPA_0_GSI_TOP_GSI_SP_FW_AUTH_LOCK_OUT(v) \ + out_dword(HWIO_IPA_0_GSI_TOP_GSI_SP_FW_AUTH_LOCK_ADDR,v) +#define HWIO_IPA_0_GSI_TOP_GSI_SP_FW_AUTH_LOCK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_GSI_SP_FW_AUTH_LOCK_ADDR,m,v,HWIO_IPA_0_GSI_TOP_GSI_SP_FW_AUTH_LOCK_IN) +#define HWIO_IPA_0_GSI_TOP_GSI_SP_FW_AUTH_LOCK_DIS_DEBUG_SHRAM_WRITE_BMSK 0x2 +#define HWIO_IPA_0_GSI_TOP_GSI_SP_FW_AUTH_LOCK_DIS_DEBUG_SHRAM_WRITE_SHFT 0x1 +#define HWIO_IPA_0_GSI_TOP_GSI_SP_FW_AUTH_LOCK_DIS_IRAM_WRITE_BMSK 0x1 +#define HWIO_IPA_0_GSI_TOP_GSI_SP_FW_AUTH_LOCK_DIS_IRAM_WRITE_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_ORIGINATOR_EE_ADDR(n) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x0000c000 + 0x1000 * (n)) +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_ORIGINATOR_EE_PHYS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000c000 + 0x1000 * (n)) +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_ORIGINATOR_EE_OFFS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000c000 + 0x1000 * (n)) +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_ORIGINATOR_EE_RMSK 0xf +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_ORIGINATOR_EE_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_ORIGINATOR_EE_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_ORIGINATOR_EE_INI(n) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_INTER_EE_n_ORIGINATOR_EE_ADDR(n), HWIO_IPA_0_GSI_TOP_INTER_EE_n_ORIGINATOR_EE_RMSK) +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_ORIGINATOR_EE_INMI(n,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_INTER_EE_n_ORIGINATOR_EE_ADDR(n), mask) +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_ORIGINATOR_EE_OUTI(n,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_INTER_EE_n_ORIGINATOR_EE_ADDR(n),val) +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_ORIGINATOR_EE_OUTMI(n,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_INTER_EE_n_ORIGINATOR_EE_ADDR(n),mask,val,HWIO_IPA_0_GSI_TOP_INTER_EE_n_ORIGINATOR_EE_INI(n)) +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_ORIGINATOR_EE_EE_NUMBER_BMSK 0xf +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_ORIGINATOR_EE_EE_NUMBER_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_GSI_CH_CMD_ADDR(n) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x0000c008 + 0x1000 * (n)) +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_GSI_CH_CMD_PHYS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000c008 + 0x1000 * (n)) +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_GSI_CH_CMD_OFFS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000c008 + 0x1000 * (n)) +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_GSI_CH_CMD_RMSK 0xff0000ff +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_GSI_CH_CMD_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_GSI_CH_CMD_ATTR 0x2 +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_GSI_CH_CMD_OUTI(n,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_INTER_EE_n_GSI_CH_CMD_ADDR(n),val) +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_GSI_CH_CMD_OPCODE_BMSK 0xff000000 +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_GSI_CH_CMD_OPCODE_SHFT 0x18 +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_GSI_CH_CMD_OPCODE_START_FVAL 0x1 +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_GSI_CH_CMD_OPCODE_STOP_FVAL 0x2 +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_GSI_CH_CMD_OPCODE_RESET_FVAL 0x9 +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_GSI_CH_CMD_OPCODE_DE_ALLOC_FVAL 0xa +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_GSI_CH_CMD_OPCODE_DB_STOP_FVAL 0xb +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_GSI_CH_CMD_CHID_BMSK 0xff +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_GSI_CH_CMD_CHID_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_EV_CH_CMD_ADDR(n) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x0000c010 + 0x1000 * (n)) +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_EV_CH_CMD_PHYS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000c010 + 0x1000 * (n)) +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_EV_CH_CMD_OFFS(n) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000c010 + 0x1000 * (n)) +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_EV_CH_CMD_RMSK 0xff0000ff +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_EV_CH_CMD_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_EV_CH_CMD_ATTR 0x2 +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_EV_CH_CMD_OUTI(n,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_INTER_EE_n_EV_CH_CMD_ADDR(n),val) +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_EV_CH_CMD_OPCODE_BMSK 0xff000000 +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_EV_CH_CMD_OPCODE_SHFT 0x18 +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_EV_CH_CMD_OPCODE_RESET_FVAL 0x9 +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_EV_CH_CMD_OPCODE_DE_ALLOC_FVAL 0xa +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_EV_CH_CMD_CHID_BMSK 0xff +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_EV_CH_CMD_CHID_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_k_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x0000c018 + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_k_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000c018 + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_k_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000c018 + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_k_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_k_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_k_MAXk 0 +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_k_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_k_INI2(n,k) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_k_ADDR(n,k), HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_k_RMSK) +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_k_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_k_ADDR(n,k), mask) +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_k_GSI_CH_BIT_MAP_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_k_GSI_CH_BIT_MAP_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x0000c01c + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000c01c + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000c01c + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_MAXk 0 +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_INI2(n,k) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_ADDR(n,k), HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_RMSK) +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_ADDR(n,k), mask) +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_ADDR(n,k),val) +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_ADDR(n,k),mask,val,HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_INI2(n,k)) +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_GSI_CH_BIT_MAP_MSK_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k_GSI_CH_BIT_MAP_MSK_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_k_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x0000c020 + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_k_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000c020 + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_k_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000c020 + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_k_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_k_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_k_MAXk 0 +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_k_ATTR 0x2 +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_k_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_k_ADDR(n,k),val) +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_k_GSI_CH_BIT_MAP_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_k_GSI_CH_BIT_MAP_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_k_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x0000c024 + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_k_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000c024 + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_k_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000c024 + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_k_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_k_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_k_MAXk 0 +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_k_ATTR 0x1 +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_k_INI2(n,k) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_k_ADDR(n,k), HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_k_RMSK) +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_k_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_k_ADDR(n,k), mask) +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_k_EV_CH_BIT_MAP_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_k_EV_CH_BIT_MAP_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x0000c028 + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000c028 + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000c028 + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_MAXk 0 +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_ATTR 0x3 +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_INI2(n,k) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_ADDR(n,k), HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_RMSK) +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_INMI2(n,k,mask) \ + in_dword_masked(HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_ADDR(n,k), mask) +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_ADDR(n,k),val) +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_OUTMI2(n,k,mask,val) \ + out_dword_masked_ns(HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_ADDR(n,k),mask,val,HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_INI2(n,k)) +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_EV_CH_BIT_MAP_MSK_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k_EV_CH_BIT_MAP_MSK_SHFT 0x0 + +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_CLR_k_ADDR(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE + 0x0000c02c + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_CLR_k_PHYS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000c02c + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_CLR_k_OFFS(n,k) (IPA_0_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000c02c + 0x18 * (k) + 0x1000 * (n)) +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_CLR_k_RMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_CLR_k_MAXn 2 +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_CLR_k_MAXk 0 +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_CLR_k_ATTR 0x2 +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_CLR_k_OUTI2(n,k,val) \ + out_dword(HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_CLR_k_ADDR(n,k),val) +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_CLR_k_EV_CH_BIT_MAP_BMSK 0xffffffff +#define HWIO_IPA_0_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_CLR_k_EV_CH_BIT_MAP_SHFT 0x0 + + +#endif /* __IPA_HWIO_H__ */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.5/ipa_hwio_def.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.5/ipa_hwio_def.h new file mode 100644 index 0000000000..4188de1780 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.5/ipa_hwio_def.h @@ -0,0 +1,17637 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef __IPA_HWIO_DEF_H__ +#define __IPA_HWIO_DEF_H__ +/** + @file ipa_hwio.h + @brief Auto-generated HWIO interface include file. + + This file contains HWIO register definitions for the following modules: + IPA.* + + 'Include' filters applied: + 'Exclude' filters applied: RESERVED DUMMY +*/ + +/*---------------------------------------------------------------------------- + * MODULE: IPA_UC_IPA_UC + *--------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------- + * MODULE: IPA_UC_IPA_UC_RAM + *--------------------------------------------------------------------------*/ + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_IRAM_START +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_iram_start_s +{ + u32 data : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_iram_start_u +{ + struct ipa_hwio_def_ipa_uc_iram_start_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_DRAM_START +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_dram_start_s +{ + u32 data : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_dram_start_u +{ + struct ipa_hwio_def_ipa_uc_dram_start_s def; + u32 value; +}; + +/*---------------------------------------------------------------------------- + * MODULE: IPA_UC_IPA_UC_PER + *--------------------------------------------------------------------------*/ + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_status_s +{ + u32 sleepdeep : 1; + u32 sleep : 1; + u32 lockup : 1; + u32 uc_enable : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_status_u +{ + struct ipa_hwio_def_ipa_uc_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_CONTROL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_control_s +{ + u32 reserved0 : 1; + u32 uc_dsmode : 1; + u32 qmb_snoc_bypass_dis : 1; + u32 uc_clock_gating_dis : 1; + u32 mbox_dis : 8; + u32 reserved1 : 12; + u32 warmboot_dis : 1; + u32 reserved2 : 2; + u32 uc_ram_rd_cli_cache_dis : 1; + u32 reserved3 : 4; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_control_u +{ + struct ipa_hwio_def_ipa_uc_control_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_SYS_BUS_ATTRIB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_sys_bus_attrib_s +{ + u32 memtype : 3; + u32 reserved0 : 1; + u32 noallocate : 1; + u32 reserved1 : 3; + u32 innershared : 1; + u32 reserved2 : 3; + u32 shared : 1; + u32 reserved3 : 19; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_sys_bus_attrib_u +{ + struct ipa_hwio_def_ipa_uc_sys_bus_attrib_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_PEND_IRQ +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_pend_irq_s +{ + u32 pend_irq : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_pend_irq_u +{ + struct ipa_hwio_def_ipa_uc_pend_irq_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_TRACE_BUFFER +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_trace_buffer_s +{ + u32 trace_buffer : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_trace_buffer_u +{ + struct ipa_hwio_def_ipa_uc_trace_buffer_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_PC +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_pc_s +{ + u32 pc : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_pc_u +{ + struct ipa_hwio_def_ipa_uc_pc_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_VUIC_INT_ADDRESS_LSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_vuic_int_address_lsb_s +{ + u32 addrress : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_vuic_int_address_lsb_u +{ + struct ipa_hwio_def_ipa_uc_vuic_int_address_lsb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_VUIC_INT_ADDRESS_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_vuic_int_address_msb_s +{ + u32 addrress : 9; + u32 reserved0 : 23; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_vuic_int_address_msb_u +{ + struct ipa_hwio_def_ipa_uc_vuic_int_address_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_QMB_SYS_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_qmb_sys_addr_s +{ + u32 addr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_qmb_sys_addr_u +{ + struct ipa_hwio_def_ipa_uc_qmb_sys_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_QMB_SYS_ADDR_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_qmb_sys_addr_msb_s +{ + u32 addr_msb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_qmb_sys_addr_msb_u +{ + struct ipa_hwio_def_ipa_uc_qmb_sys_addr_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_QMB_LOCAL_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_qmb_local_addr_s +{ + u32 addr : 18; + u32 reserved0 : 14; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_qmb_local_addr_u +{ + struct ipa_hwio_def_ipa_uc_qmb_local_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_QMB_LENGTH +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_qmb_length_s +{ + u32 length : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_qmb_length_u +{ + struct ipa_hwio_def_ipa_uc_qmb_length_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_QMB_TRIGGER +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_qmb_trigger_s +{ + u32 rsv : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_qmb_trigger_u +{ + struct ipa_hwio_def_ipa_uc_qmb_trigger_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_QMB_COMMAND_ATTR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_qmb_command_attr_s +{ + u32 direction : 1; + u32 inorder : 1; + u32 wait_for_response_mode : 1; + u32 sync : 1; + u32 interrupt_on_completion : 1; + u32 queue_number : 1; + u32 reserved0 : 10; + u32 user : 11; + u32 reserved1 : 5; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_qmb_command_attr_u +{ + struct ipa_hwio_def_ipa_uc_qmb_command_attr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_QMB_COMMAND_UCTAG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_qmb_command_uctag_s +{ + u32 uctag : 18; + u32 reserved0 : 14; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_qmb_command_uctag_u +{ + struct ipa_hwio_def_ipa_uc_qmb_command_uctag_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_QMB_COMPLETED_FIFO_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_qmb_completed_fifo_n_s +{ + u32 uctag : 18; + u32 fifo_size : 4; + u32 fifo_cnt : 4; + u32 error : 1; + u32 reserved0 : 3; + u32 empty : 1; + u32 full : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_qmb_completed_fifo_n_u +{ + struct ipa_hwio_def_ipa_uc_qmb_completed_fifo_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_QMB_COMPLETED_FIFO_PEEK_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_qmb_completed_fifo_peek_n_s +{ + u32 uctag : 18; + u32 fifo_size : 4; + u32 fifo_cnt : 4; + u32 error : 1; + u32 reserved0 : 3; + u32 empty : 1; + u32 full : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_qmb_completed_fifo_peek_n_u +{ + struct ipa_hwio_def_ipa_uc_qmb_completed_fifo_peek_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_QMB_CMD_FIFO_STATUS_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_qmb_cmd_fifo_status_n_s +{ + u32 fifo_size : 4; + u32 fifo_cnt : 4; + u32 reserved0 : 8; + u32 empty : 1; + u32 full : 1; + u32 reserved1 : 14; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_qmb_cmd_fifo_status_n_u +{ + struct ipa_hwio_def_ipa_uc_qmb_cmd_fifo_status_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_QMB_SYNC_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_qmb_sync_status_s +{ + u32 error_queue_0 : 1; + u32 reserved0 : 15; + u32 error_queue_1 : 1; + u32 reserved1 : 15; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_qmb_sync_status_u +{ + struct ipa_hwio_def_ipa_uc_qmb_sync_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_QMB_BUS_ATTRIB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_qmb_bus_attrib_s +{ + u32 memtype : 3; + u32 reserved0 : 1; + u32 noallocate : 1; + u32 reserved1 : 3; + u32 innershared : 1; + u32 reserved2 : 3; + u32 shared : 1; + u32 reserved3 : 19; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_qmb_bus_attrib_u +{ + struct ipa_hwio_def_ipa_uc_qmb_bus_attrib_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_QMB_OUTSTANDING_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_qmb_outstanding_cfg_s +{ + u32 max_ot_overall : 8; + u32 max_ot_rd : 8; + u32 max_ot_wr : 8; + u32 reserved0 : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_qmb_outstanding_cfg_u +{ + struct ipa_hwio_def_ipa_uc_qmb_outstanding_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_QMB_OUTSTANDING_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_qmb_outstanding_status_s +{ + u32 current_ot_overall : 8; + u32 current_ot_rd : 8; + u32 current_ot_wr : 8; + u32 reserved0 : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_qmb_outstanding_status_u +{ + struct ipa_hwio_def_ipa_uc_qmb_outstanding_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_QMB_COMP_FIFO_INT_EN +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_qmb_comp_fifo_int_en_s +{ + u32 comp_fifo_0_not_empty : 1; + u32 comp_fifo_0_full : 1; + u32 comp_fifo_0_ioc_cmd : 1; + u32 reserved0 : 13; + u32 comp_fifo_1_not_empty : 1; + u32 comp_fifo_1_full : 1; + u32 comp_fifo_1_ioc_cmd : 1; + u32 reserved1 : 13; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_qmb_comp_fifo_int_en_u +{ + struct ipa_hwio_def_ipa_uc_qmb_comp_fifo_int_en_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_QMB_COMP_FIFO_INT_CLR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_qmb_comp_fifo_int_clr_s +{ + u32 comp_fifo_0_not_empty : 1; + u32 comp_fifo_0_full : 1; + u32 comp_fifo_0_ioc_cmd : 1; + u32 reserved0 : 13; + u32 comp_fifo_1_not_empty : 1; + u32 comp_fifo_1_full : 1; + u32 comp_fifo_1_ioc_cmd : 1; + u32 reserved1 : 13; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_qmb_comp_fifo_int_clr_u +{ + struct ipa_hwio_def_ipa_uc_qmb_comp_fifo_int_clr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_QMB_COMP_FIFO_INT_STTS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_qmb_comp_fifo_int_stts_s +{ + u32 comp_fifo_0_not_empty : 1; + u32 comp_fifo_0_full : 1; + u32 comp_fifo_0_ioc_cmd : 1; + u32 reserved0 : 13; + u32 comp_fifo_1_not_empty : 1; + u32 comp_fifo_1_full : 1; + u32 comp_fifo_1_ioc_cmd : 1; + u32 reserved1 : 13; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_qmb_comp_fifo_int_stts_u +{ + struct ipa_hwio_def_ipa_uc_qmb_comp_fifo_int_stts_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_QMB_SYNC_COMPLETE_INT_EN +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_qmb_sync_complete_int_en_s +{ + u32 sync_completed_0 : 1; + u32 sync_completed_1 : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_qmb_sync_complete_int_en_u +{ + struct ipa_hwio_def_ipa_uc_qmb_sync_complete_int_en_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_QMB_SYNC_COMPLETE_INT_CLR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_qmb_sync_complete_int_clr_s +{ + u32 sync_completed_0 : 1; + u32 sync_completed_1 : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_qmb_sync_complete_int_clr_u +{ + struct ipa_hwio_def_ipa_uc_qmb_sync_complete_int_clr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_QMB_SYNC_COMPLETE_INT_STTS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_qmb_sync_complete_int_stts_s +{ + u32 sync_completed_0 : 1; + u32 sync_completed_1 : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_qmb_sync_complete_int_stts_u +{ + struct ipa_hwio_def_ipa_uc_qmb_sync_complete_int_stts_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_MBOX_INT_STTS_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_mbox_int_stts_n_s +{ + u32 irq_status : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_mbox_int_stts_n_u +{ + struct ipa_hwio_def_ipa_uc_mbox_int_stts_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_MBOX_INT_EN_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_mbox_int_en_n_s +{ + u32 irq_en : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_mbox_int_en_n_u +{ + struct ipa_hwio_def_ipa_uc_mbox_int_en_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_MBOX_INT_CLR_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_mbox_int_clr_n_s +{ + u32 irq_clr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_mbox_int_clr_n_u +{ + struct ipa_hwio_def_ipa_uc_mbox_int_clr_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_IPA_INT_STTS_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_ipa_int_stts_n_s +{ + u32 irq_status : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_ipa_int_stts_n_u +{ + struct ipa_hwio_def_ipa_uc_ipa_int_stts_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_IPA_INT_EN_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_ipa_int_en_n_s +{ + u32 irq_en : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_ipa_int_en_n_u +{ + struct ipa_hwio_def_ipa_uc_ipa_int_en_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_IPA_INT_CLR_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_ipa_int_clr_n_s +{ + u32 irq_clr : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_ipa_int_clr_n_u +{ + struct ipa_hwio_def_ipa_uc_ipa_int_clr_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_HWEV_INT_STTS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_hwev_int_stts_s +{ + u32 irq_status : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_hwev_int_stts_u +{ + struct ipa_hwio_def_ipa_uc_hwev_int_stts_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_HWEV_INT_EN +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_hwev_int_en_s +{ + u32 irq_en : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_hwev_int_en_u +{ + struct ipa_hwio_def_ipa_uc_hwev_int_en_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_HWEV_INT_CLR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_hwev_int_clr_s +{ + u32 irq_clr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_hwev_int_clr_u +{ + struct ipa_hwio_def_ipa_uc_hwev_int_clr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_SWEV_INT_STTS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_swev_int_stts_s +{ + u32 irq_status : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_swev_int_stts_u +{ + struct ipa_hwio_def_ipa_uc_swev_int_stts_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_SWEV_INT_EN +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_swev_int_en_s +{ + u32 irq_en : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_swev_int_en_u +{ + struct ipa_hwio_def_ipa_uc_swev_int_en_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_SWEV_INT_CLR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_swev_int_clr_s +{ + u32 irq_clr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_swev_int_clr_u +{ + struct ipa_hwio_def_ipa_uc_swev_int_clr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_VUIC_INT_STTS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_vuic_int_stts_s +{ + u32 irq_status : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_vuic_int_stts_u +{ + struct ipa_hwio_def_ipa_uc_vuic_int_stts_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_VUIC_INT_CLR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_vuic_int_clr_s +{ + u32 irq_clr : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_vuic_int_clr_u +{ + struct ipa_hwio_def_ipa_uc_vuic_int_clr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_TIMER_CTRL_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_timer_ctrl_n_s +{ + u32 count : 16; + u32 event_sel : 7; + u32 reserved0 : 1; + u32 retrig : 1; + u32 reserved1 : 5; + u32 gran_sel : 2; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_timer_ctrl_n_u +{ + struct ipa_hwio_def_ipa_uc_timer_ctrl_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_TIMER_STATUS_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_timer_status_n_s +{ + u32 count : 16; + u32 reserved0 : 8; + u32 active : 1; + u32 reserved1 : 7; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_timer_status_n_u +{ + struct ipa_hwio_def_ipa_uc_timer_status_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_EVENTS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_events_s +{ + u32 events : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_events_u +{ + struct ipa_hwio_def_ipa_uc_events_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_VUIC_BUS_ADDR_TRANSLATE_EN +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_vuic_bus_addr_translate_en_s +{ + u32 qmb_addr_translate : 1; + u32 direct_addr_translate : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_vuic_bus_addr_translate_en_u +{ + struct ipa_hwio_def_ipa_uc_vuic_bus_addr_translate_en_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_SYS_ADDR_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_sys_addr_msb_s +{ + u32 sys_addr_msb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_sys_addr_msb_u +{ + struct ipa_hwio_def_ipa_uc_sys_addr_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_PC_RESTORE_WR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_pc_restore_wr_s +{ + u32 set_ipa_pc_ack : 1; + u32 clear_ipa_pc_ack : 1; + u32 set_ipa_restore_ack : 1; + u32 clear_ipa_restore_ack : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_pc_restore_wr_u +{ + struct ipa_hwio_def_ipa_uc_pc_restore_wr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_PC_RESTORE_RD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_pc_restore_rd_s +{ + u32 ipa_pc_req : 1; + u32 ipa_pc_ack : 1; + u32 ipa_restore_req : 1; + u32 ipa_restore_ack : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_pc_restore_rd_u +{ + struct ipa_hwio_def_ipa_uc_pc_restore_rd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_CNT_GLOBAL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_cnt_global_s +{ + u32 count_en : 1; + u32 count_cgc_open : 1; + u32 reserved0 : 29; + u32 clear_all : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_cnt_global_u +{ + struct ipa_hwio_def_ipa_uc_cnt_global_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_CNT_CTL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_cnt_ctl_s +{ + u32 cycle_cnt_en : 1; + u32 reserved0 : 1; + u32 cycle_cnt_clr : 1; + u32 reserved1 : 1; + u32 idle_cnt_en : 1; + u32 reserved2 : 1; + u32 idle_cnt_clr : 1; + u32 reserved3 : 1; + u32 inst_cnt_en : 1; + u32 inst_clr_after_rd : 1; + u32 inst_cnt_clr : 1; + u32 reserved4 : 1; + u32 vuic_rd_cnt_en : 1; + u32 vuic_wr_cnt_en : 1; + u32 vuic_clr_after_rd : 1; + u32 vuic_cnt_clr : 1; + u32 dram_rd_cnt_en : 1; + u32 dram_wr_cnt_en : 1; + u32 dram_clr_after_rd : 1; + u32 dram_cnt_clr : 1; + u32 reserved5 : 12; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_cnt_ctl_u +{ + struct ipa_hwio_def_ipa_uc_cnt_ctl_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_CNT_CLK_CYCLE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_cnt_clk_cycle_s +{ + u32 counter : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_cnt_clk_cycle_u +{ + struct ipa_hwio_def_ipa_uc_cnt_clk_cycle_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_CNT_CLK_CYCLE_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_cnt_clk_cycle_msb_s +{ + u32 counter : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_cnt_clk_cycle_msb_u +{ + struct ipa_hwio_def_ipa_uc_cnt_clk_cycle_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_CNT_IDLE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_cnt_idle_s +{ + u32 counter : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_cnt_idle_u +{ + struct ipa_hwio_def_ipa_uc_cnt_idle_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_CNT_IDLE_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_cnt_idle_msb_s +{ + u32 counter : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_cnt_idle_msb_u +{ + struct ipa_hwio_def_ipa_uc_cnt_idle_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_CNT_INST +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_cnt_inst_s +{ + u32 counter : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_cnt_inst_u +{ + struct ipa_hwio_def_ipa_uc_cnt_inst_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_CNT_DRAM +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_cnt_dram_s +{ + u32 counter : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_cnt_dram_u +{ + struct ipa_hwio_def_ipa_uc_cnt_dram_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_CNT_VUIC +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_cnt_vuic_s +{ + u32 counter : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_cnt_vuic_u +{ + struct ipa_hwio_def_ipa_uc_cnt_vuic_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_SPARE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_spare_s +{ + u32 spare : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_spare_u +{ + struct ipa_hwio_def_ipa_uc_spare_s def; + u32 value; +}; + +/*---------------------------------------------------------------------------- + * MODULE: IPA_UC_IPA_UC_MBOX + *--------------------------------------------------------------------------*/ + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_MAILBOX_m_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_mailbox_m_n_s +{ + u32 data : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_mailbox_m_n_u +{ + struct ipa_hwio_def_ipa_uc_mailbox_m_n_s def; + u32 value; +}; + +/*---------------------------------------------------------------------------- + * MODULE: IPA_RAM + *--------------------------------------------------------------------------*/ + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_SW_AREA_RAM_DIRECT_ACCESS_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_sw_area_ram_direct_access_n_s +{ + u32 data_word : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_sw_area_ram_direct_access_n_u +{ + struct ipa_hwio_def_ipa_sw_area_ram_direct_access_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_HW_AREA_RAM_DIRECT_ACCESS_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_hw_area_ram_direct_access_n_s +{ + u32 data_word : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_hw_area_ram_direct_access_n_u +{ + struct ipa_hwio_def_ipa_hw_area_ram_direct_access_n_s def; + u32 value; +}; + +/*---------------------------------------------------------------------------- + * MODULE: IPA_EE + *--------------------------------------------------------------------------*/ + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_IRQ_STTS_EE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_irq_stts_ee_n_s +{ + u32 reserved0 : 2; + u32 uc_irq_0 : 1; + u32 uc_irq_1 : 1; + u32 uc_irq_2 : 1; + u32 uc_irq_3 : 1; + u32 uc_in_q_not_empty_irq : 1; + u32 uc_rx_cmd_q_not_full_irq : 1; + u32 proc_to_uc_ack_q_not_empty_irq : 1; + u32 reserved1 : 5; + u32 tx_suspend_irq : 1; + u32 tx_holb_drop_irq : 1; + u32 gsi_idle_irq : 1; + u32 pipe_yellow_marker_below_irq : 1; + u32 pipe_red_marker_below_irq : 1; + u32 pipe_yellow_marker_above_irq : 1; + u32 pipe_red_marker_above_irq : 1; + u32 ucp_irq : 1; + u32 reserved2 : 1; + u32 gsi_ee_irq : 1; + u32 gsi_ipa_if_tlv_rcvd_irq : 1; + u32 gsi_uc_irq : 1; + u32 reserved3 : 4; + u32 ipa_error_non_fatal_irq : 1; + u32 ipa_error_fatal_irq : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_irq_stts_ee_n_u +{ + struct ipa_hwio_def_ipa_irq_stts_ee_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_IRQ_EN_EE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_irq_en_ee_n_s +{ + u32 reserved0 : 2; + u32 uc_irq_0_irq_en : 1; + u32 uc_irq_1_irq_en : 1; + u32 uc_irq_2_irq_en : 1; + u32 uc_irq_3_irq_en : 1; + u32 uc_in_q_not_empty_irq_en : 1; + u32 uc_rx_cmd_q_not_full_irq_en : 1; + u32 proc_to_uc_ack_q_not_empty_irq_en : 1; + u32 reserved1 : 5; + u32 tx_suspend_irq_en : 1; + u32 tx_holb_drop_irq_en : 1; + u32 gsi_idle_irq_en : 1; + u32 pipe_yellow_marker_below_irq_en : 1; + u32 pipe_red_marker_below_irq_en : 1; + u32 pipe_yellow_marker_above_irq_en : 1; + u32 pipe_red_marker_above_irq_en : 1; + u32 ucp_irq_en : 1; + u32 reserved2 : 1; + u32 gsi_ee_irq_en : 1; + u32 gsi_ipa_if_tlv_rcvd_irq_en : 1; + u32 gsi_uc_irq_en : 1; + u32 reserved3 : 4; + u32 ipa_error_non_fatal_irq_en : 1; + u32 ipa_error_fatal_irq_en : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_irq_en_ee_n_u +{ + struct ipa_hwio_def_ipa_irq_en_ee_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_IRQ_CLR_EE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_irq_clr_ee_n_s +{ + u32 reserved0 : 2; + u32 uc_irq_0_clr : 1; + u32 uc_irq_1_clr : 1; + u32 uc_irq_2_clr : 1; + u32 uc_irq_3_clr : 1; + u32 uc_in_q_not_empty_irq_clr : 1; + u32 uc_rx_cmd_q_not_full_irq_clr : 1; + u32 proc_to_uc_ack_q_not_empty_irq_clr : 1; + u32 reserved1 : 5; + u32 tx_suspend_irq_clr : 1; + u32 tx_holb_drop_irq_clr : 1; + u32 gsi_idle_irq_clr : 1; + u32 pipe_yellow_marker_below_irq_clr : 1; + u32 pipe_red_marker_below_irq_clr : 1; + u32 pipe_yellow_marker_above_irq_clr : 1; + u32 pipe_red_marker_above_irq_clr : 1; + u32 ucp_irq_clr : 1; + u32 reserved2 : 1; + u32 gsi_ee_irq_clr : 1; + u32 gsi_ipa_if_tlv_rcvd_irq_clr : 1; + u32 gsi_uc_irq_clr : 1; + u32 reserved3 : 4; + u32 ipa_error_non_fatal_clr : 1; + u32 ipa_error_fatal_clr : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_irq_clr_ee_n_u +{ + struct ipa_hwio_def_ipa_irq_clr_ee_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_SNOC_FEC_EE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_snoc_fec_ee_n_s +{ + u32 client : 8; + u32 noc_port : 1; + u32 noc_master : 3; + u32 tid : 5; + u32 reserved0 : 11; + u32 valid : 1; + u32 clear : 1; + u32 reserved1 : 1; + u32 direction : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_snoc_fec_ee_n_u +{ + struct ipa_hwio_def_ipa_snoc_fec_ee_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_IRQ_EE_UC_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_irq_ee_uc_n_s +{ + u32 intr : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_irq_ee_uc_n_u +{ + struct ipa_hwio_def_ipa_irq_ee_uc_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_FEC_FATAL_ADDR_EE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_fec_fatal_addr_ee_n_s +{ + u32 addr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_fec_fatal_addr_ee_n_u +{ + struct ipa_hwio_def_ipa_fec_fatal_addr_ee_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_FEC_FATAL_ADDR_MSB_EE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_fec_fatal_addr_msb_ee_n_s +{ + u32 addr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_fec_fatal_addr_msb_ee_n_u +{ + struct ipa_hwio_def_ipa_fec_fatal_addr_msb_ee_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_FEC_FATAL_ATTR_EE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_fec_fatal_attr_ee_n_s +{ + u32 opcode : 6; + u32 error_info : 26; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_fec_fatal_attr_ee_n_u +{ + struct ipa_hwio_def_ipa_fec_fatal_attr_ee_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_SUSPEND_IRQ_INFO_EE_n_REG_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_suspend_irq_info_ee_n_reg_k_s +{ + u32 endpoints : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_suspend_irq_info_ee_n_reg_k_u +{ + struct ipa_hwio_def_ipa_suspend_irq_info_ee_n_reg_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_SUSPEND_IRQ_EN_EE_n_REG_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_suspend_irq_en_ee_n_reg_k_s +{ + u32 endpoints : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_suspend_irq_en_ee_n_reg_k_u +{ + struct ipa_hwio_def_ipa_suspend_irq_en_ee_n_reg_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DRBIP_FEC_INFO_EE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_drbip_fec_info_ee_n_s +{ + u32 error_code : 4; + u32 src_grp : 4; + u32 src_pipe : 8; + u32 required_data_sectors : 8; + u32 avail_data_sectors : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_drbip_fec_info_ee_n_u +{ + struct ipa_hwio_def_ipa_drbip_fec_info_ee_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DRBIP_FEC_INFO_EXT_EE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_drbip_fec_info_ext_ee_n_s +{ + u32 size : 16; + u32 opcode : 8; + u32 reserved0 : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_drbip_fec_info_ext_ee_n_u +{ + struct ipa_hwio_def_ipa_drbip_fec_info_ext_ee_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_SUSPEND_IRQ_CLR_EE_n_REG_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_suspend_irq_clr_ee_n_reg_k_s +{ + u32 endpoints : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_suspend_irq_clr_ee_n_reg_k_u +{ + struct ipa_hwio_def_ipa_suspend_irq_clr_ee_n_reg_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_HOLB_DROP_IRQ_INFO_EE_n_REG_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_holb_drop_irq_info_ee_n_reg_k_s +{ + u32 endpoints : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_holb_drop_irq_info_ee_n_reg_k_u +{ + struct ipa_hwio_def_ipa_holb_drop_irq_info_ee_n_reg_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_HOLB_DROP_IRQ_EN_EE_n_REG_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_holb_drop_irq_en_ee_n_reg_k_s +{ + u32 endpoints : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_holb_drop_irq_en_ee_n_reg_k_u +{ + struct ipa_hwio_def_ipa_holb_drop_irq_en_ee_n_reg_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_HOLB_DROP_IRQ_CLR_EE_n_REG_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_holb_drop_irq_clr_ee_n_reg_k_s +{ + u32 endpoints : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_holb_drop_irq_clr_ee_n_reg_k_u +{ + struct ipa_hwio_def_ipa_holb_drop_irq_clr_ee_n_reg_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_IRQ_STTS_EE_ERROR_FATAL_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_irq_stts_ee_error_fatal_n_s +{ + u32 bad_snoc_access_irq : 1; + u32 proc_err_irq : 1; + u32 rx_err_irq : 1; + u32 tlv_len_min_dsm_irq : 1; + u32 drbip_pkt_exceed_max_size_irq : 1; + u32 drbip_data_sctr_cfg_error_irq : 1; + u32 drbip_imm_cmd_no_flsh_hzrd_irq : 1; + u32 reserved0 : 25; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_irq_stts_ee_error_fatal_n_u +{ + struct ipa_hwio_def_ipa_irq_stts_ee_error_fatal_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_IRQ_EN_EE_ERROR_FATAL_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_irq_en_ee_error_fatal_n_s +{ + u32 bad_snoc_access_irq_en : 1; + u32 proc_err_irq_en : 1; + u32 rx_err_irq_en : 1; + u32 tlv_len_min_dsm_irq_en : 1; + u32 drbip_pkt_exceed_max_size_irq_en : 1; + u32 drbip_data_sctr_cfg_error_irq_en : 1; + u32 drbip_imm_cmd_no_flsh_hzrd_irq_en : 1; + u32 reserved0 : 25; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_irq_en_ee_error_fatal_n_u +{ + struct ipa_hwio_def_ipa_irq_en_ee_error_fatal_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_IRQ_CLR_EE_ERROR_FATAL_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_irq_clr_ee_error_fatal_n_s +{ + u32 bad_snoc_access_irq_clr : 1; + u32 proc_err_irq_clr : 1; + u32 rx_err_irq_clr : 1; + u32 tlv_len_min_dsm_irq_clr : 1; + u32 drbip_pkt_exceed_max_size_irq_clr : 1; + u32 drbip_data_sctr_cfg_error_irq_clr : 1; + u32 drbip_imm_cmd_no_flsh_hzrd_irq_clr : 1; + u32 reserved0 : 25; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_irq_clr_ee_error_fatal_n_u +{ + struct ipa_hwio_def_ipa_irq_clr_ee_error_fatal_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_IRQ_STTS_EE_ERROR_NON_FATAL_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_irq_stts_ee_error_non_fatal_n_s +{ + u32 deaggr_err_irq : 1; + u32 proc_err_irq : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_irq_stts_ee_error_non_fatal_n_u +{ + struct ipa_hwio_def_ipa_irq_stts_ee_error_non_fatal_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_IRQ_EN_EE_ERROR_NON_FATAL_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_irq_en_ee_error_non_fatal_n_s +{ + u32 deaggr_err_irq_en : 1; + u32 proc_err_irq_en : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_irq_en_ee_error_non_fatal_n_u +{ + struct ipa_hwio_def_ipa_irq_en_ee_error_non_fatal_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_IRQ_CLR_EE_ERROR_NON_FATAL_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_irq_clr_ee_error_non_fatal_n_s +{ + u32 deaggr_err_irq_clr : 1; + u32 proc_err_irq_clr : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_irq_clr_ee_error_non_fatal_n_u +{ + struct ipa_hwio_def_ipa_irq_clr_ee_error_non_fatal_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_FEC_NON_FATAL_ADDR_EE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_fec_non_fatal_addr_ee_n_s +{ + u32 addr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_fec_non_fatal_addr_ee_n_u +{ + struct ipa_hwio_def_ipa_fec_non_fatal_addr_ee_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_FEC_NON_FATAL_ADDR_MSB_EE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_fec_non_fatal_addr_msb_ee_n_s +{ + u32 addr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_fec_non_fatal_addr_msb_ee_n_u +{ + struct ipa_hwio_def_ipa_fec_non_fatal_addr_msb_ee_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_FEC_NON_FATAL_ATTR_EE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_fec_non_fatal_attr_ee_n_s +{ + u32 opcode : 6; + u32 error_info : 26; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_fec_non_fatal_attr_ee_n_u +{ + struct ipa_hwio_def_ipa_fec_non_fatal_attr_ee_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MODEM_BEARER_INIT_VALUES_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_modem_bearer_init_values_0_s +{ + u32 modem_bearer_init_l2_hdr_size : 8; + u32 modem_bearer_init_sdap_enable : 1; + u32 modem_bearer_init_rqi_enable : 1; + u32 modem_bearer_init_rdi_enable : 1; + u32 reserved0 : 1; + u32 modem_bearer_init_cphr_algorithm : 4; + u32 modem_bearer_init_cphr_key_indx : 5; + u32 reserved1 : 3; + u32 modem_bearer_init_bearer : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_modem_bearer_init_values_0_u +{ + struct ipa_hwio_def_ipa_modem_bearer_init_values_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MODEM_BEARER_INIT_VALUES_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_modem_bearer_init_values_1_s +{ + u32 modem_bearer_init_cphr_ofst_keystrm : 16; + u32 modem_bearer_init_cphr_ofst_start : 14; + u32 modem_bearer_init_direction : 1; + u32 modem_bearer_init_bearer_sel : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_modem_bearer_init_values_1_u +{ + struct ipa_hwio_def_ipa_modem_bearer_init_values_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MODEM_BEARER_INIT_VALUES_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_modem_bearer_init_values_2_s +{ + u32 modem_bearer_init_ip_algorithm : 4; + u32 modem_bearer_init_ip_key_indx : 5; + u32 reserved0 : 3; + u32 modem_bearer_init_ip_maci_size : 2; + u32 reserved1 : 2; + u32 modem_bearer_init_pdn_id : 8; + u32 reserved2 : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_modem_bearer_init_values_2_u +{ + struct ipa_hwio_def_ipa_modem_bearer_init_values_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MODEM_BEARER_CONFIG_VALUES_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_modem_bearer_config_values_0_s +{ + u32 modem_bearer_config_count_f : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_modem_bearer_config_values_0_u +{ + struct ipa_hwio_def_ipa_modem_bearer_config_values_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MODEM_BEARER_CONFIG_VALUES_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_modem_bearer_config_values_1_s +{ + u32 modem_bearer_config_size_f : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_modem_bearer_config_values_1_u +{ + struct ipa_hwio_def_ipa_modem_bearer_config_values_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MODEM_BEARER_INIT_VALUES_3 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_modem_bearer_init_values_3_s +{ + u32 modem_bearer_init_metadata : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_modem_bearer_init_values_3_u +{ + struct ipa_hwio_def_ipa_modem_bearer_init_values_3_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_SECURED_PIPES_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_secured_pipes_n_s +{ + u32 endpoints : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_secured_pipes_n_u +{ + struct ipa_hwio_def_ipa_secured_pipes_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MODEM_BEARER_INIT_VALUES_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_modem_bearer_init_values_cfg_s +{ + u32 bearer_context_index_sel : 2; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_modem_bearer_init_values_cfg_u +{ + struct ipa_hwio_def_ipa_modem_bearer_init_values_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_REGS_INSIDE_IPA__CONTROL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_regs_inside_ipa__control_s +{ + u32 uc_enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_regs_inside_ipa__control_u +{ + struct ipa_hwio_def_ipa_uc_regs_inside_ipa__control_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_REGS_INSIDE_IPA__NMI +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_regs_inside_ipa__nmi_s +{ + u32 pulse : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_regs_inside_ipa__nmi_u +{ + struct ipa_hwio_def_ipa_uc_regs_inside_ipa__nmi_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DRBIP_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_drbip_cfg_s +{ + u32 operation_mode : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_drbip_cfg_u +{ + struct ipa_hwio_def_ipa_drbip_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RQOS_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rqos_cfg_s +{ + u32 rqos_notification_pipe : 8; + u32 rqos_as_reduce_level : 8; + u32 rqos_nas_reduce_level : 8; + u32 rqos_as_reduce_level_en : 1; + u32 rqos_nas_reduce_level_en : 1; + u32 rqos_nas_unknown_protocol_pkt_cnt_reset : 1; + u32 reserved0 : 5; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rqos_cfg_u +{ + struct ipa_hwio_def_ipa_rqos_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RQOS_NAS_UNKNOWN_PROTOCOL_PKT_CNT +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rqos_nas_unknown_protocol_pkt_cnt_s +{ + u32 count : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rqos_nas_unknown_protocol_pkt_cnt_u +{ + struct ipa_hwio_def_ipa_rqos_nas_unknown_protocol_pkt_cnt_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RQOS_ILLEGAL_PROTOCOL_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rqos_illegal_protocol_0_s +{ + u32 protocol_0 : 8; + u32 protocol_1 : 8; + u32 protocol_2 : 8; + u32 protocol_3 : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rqos_illegal_protocol_0_u +{ + struct ipa_hwio_def_ipa_rqos_illegal_protocol_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RQOS_ILLEGAL_PROTOCOL_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rqos_illegal_protocol_1_s +{ + u32 protocol_0 : 8; + u32 protocol_1 : 8; + u32 protocol_2 : 8; + u32 protocol_3 : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rqos_illegal_protocol_1_u +{ + struct ipa_hwio_def_ipa_rqos_illegal_protocol_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RQOS_ILLEGAL_PROTOCOL_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rqos_illegal_protocol_2_s +{ + u32 protocol_0 : 8; + u32 protocol_1 : 8; + u32 protocol_2 : 8; + u32 protocol_3 : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rqos_illegal_protocol_2_u +{ + struct ipa_hwio_def_ipa_rqos_illegal_protocol_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RQOS_ILLEGAL_PROTOCOL_3 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rqos_illegal_protocol_3_s +{ + u32 protocol_0 : 8; + u32 protocol_1 : 8; + u32 protocol_2 : 8; + u32 protocol_3 : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rqos_illegal_protocol_3_u +{ + struct ipa_hwio_def_ipa_rqos_illegal_protocol_3_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RQOS_THRESHOLD_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rqos_threshold_cfg_s +{ + u32 threshold : 12; + u32 reserved0 : 4; + u32 threshold_en : 1; + u32 reserved1 : 3; + u32 threshold_timer_gran_sel : 4; + u32 reserved2 : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rqos_threshold_cfg_u +{ + struct ipa_hwio_def_ipa_rqos_threshold_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_SET_UC_IRQ_EE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_set_uc_irq_ee_n_s +{ + u32 set_uc_irq_0 : 1; + u32 set_uc_irq_1 : 1; + u32 set_uc_irq_2 : 1; + u32 set_uc_irq_3 : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_set_uc_irq_ee_n_u +{ + struct ipa_hwio_def_ipa_set_uc_irq_ee_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_SET_UC_IRQ_ALL_EES +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_set_uc_irq_all_ees_s +{ + u32 set_uc_irq_0 : 1; + u32 set_uc_irq_1 : 1; + u32 set_uc_irq_2 : 1; + u32 set_uc_irq_3 : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_set_uc_irq_all_ees_u +{ + struct ipa_hwio_def_ipa_set_uc_irq_all_ees_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UCP_RESUME +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ucp_resume_s +{ + u32 reserved0 : 1; + u32 next_round_en : 1; + u32 dest_pipe_override : 1; + u32 reserved1 : 1; + u32 ip_checksum_fix_en : 1; + u32 tport_checksum_fix_en : 1; + u32 reserved2 : 2; + u32 dest_pipe_value : 8; + u32 exception : 1; + u32 reserved3 : 2; + u32 next_pkt_parser_dis : 1; + u32 metadata_override : 1; + u32 reserved4 : 3; + u32 ttl_updated : 1; + u32 ttl_exception : 1; + u32 copy_hdr_en : 1; + u32 reftech_context : 1; + u32 post_uc_hw_processing_dis : 1; + u32 reserved5 : 3; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ucp_resume_u +{ + struct ipa_hwio_def_ipa_ucp_resume_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UCP_RESUME_METADATA +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ucp_resume_metadata_s +{ + u32 metadata : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ucp_resume_metadata_u +{ + struct ipa_hwio_def_ipa_ucp_resume_metadata_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_PROC_UCP_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_proc_ucp_cfg_s +{ + u32 ipa_ucp_irq_sw_events_uc_mux_en : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_proc_ucp_cfg_u +{ + struct ipa_hwio_def_ipa_proc_ucp_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_PKT_PROCESS_BASE_ADDR_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_pkt_process_base_addr_0_s +{ + u32 ipa_uc_pkt_process_context_base : 18; + u32 reserved0 : 14; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_pkt_process_base_addr_0_u +{ + struct ipa_hwio_def_ipa_uc_pkt_process_base_addr_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_PKT_PROCESS_BASE_ADDR_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_pkt_process_base_addr_1_s +{ + u32 ipa_uc_pkt_process_pkt_base : 18; + u32 reserved0 : 14; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_pkt_process_base_addr_1_u +{ + struct ipa_hwio_def_ipa_uc_pkt_process_base_addr_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_PKT_PROCESS_BASE_ADDR_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_pkt_process_base_addr_2_s +{ + u32 ipa_uc_pkt_process_hdr_base : 18; + u32 reserved0 : 14; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_pkt_process_base_addr_2_u +{ + struct ipa_hwio_def_ipa_uc_pkt_process_base_addr_2_s def; + u32 value; +}; + +/*---------------------------------------------------------------------------- + * MODULE: IPA_DEBUG + *--------------------------------------------------------------------------*/ + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rsrc_mngr_sw_access_alloc_cfg_s +{ + u32 alloc_rsrc_type : 3; + u32 reserved0 : 1; + u32 alloc_rsrc_grp : 3; + u32 reserved1 : 1; + u32 alloc_rsrc_id_curr : 6; + u32 reserved2 : 2; + u32 alloc_list_id : 6; + u32 reserved3 : 2; + u32 alloc_hold : 1; + u32 alloc_reserved : 1; + u32 alloc_list_type : 2; + u32 reserved4 : 4; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rsrc_mngr_sw_access_alloc_cfg_u +{ + struct ipa_hwio_def_ipa_rsrc_mngr_sw_access_alloc_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RSRC_MNGR_SW_ACCESS_SRCH_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rsrc_mngr_sw_access_srch_cfg_s +{ + u32 srch_rsrc_type : 3; + u32 reserved0 : 1; + u32 srch_rsrc_cnt : 7; + u32 reserved1 : 1; + u32 srch_list_id : 6; + u32 srch_list_type : 2; + u32 reserved2 : 12; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rsrc_mngr_sw_access_srch_cfg_u +{ + struct ipa_hwio_def_ipa_rsrc_mngr_sw_access_srch_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RSRC_MNGR_SW_ACCESS_REL_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rsrc_mngr_sw_access_rel_cfg_s +{ + u32 rel_rsrc_type : 3; + u32 reserved0 : 1; + u32 rel_rsrc_grp : 3; + u32 reserved1 : 1; + u32 rel_rsrc_id : 6; + u32 reserved2 : 2; + u32 rel_list_id : 6; + u32 rel_list_type : 2; + u32 reserved3 : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rsrc_mngr_sw_access_rel_cfg_u +{ + struct ipa_hwio_def_ipa_rsrc_mngr_sw_access_rel_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RSRC_MNGR_SW_ACCESS_RSRV_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rsrc_mngr_sw_access_rsrv_cfg_s +{ + u32 rsrv_rsrc_type : 3; + u32 reserved0 : 1; + u32 rsrv_rsrc_grp : 3; + u32 reserved1 : 1; + u32 rsrv_rsrc_amount : 6; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rsrc_mngr_sw_access_rsrv_cfg_u +{ + struct ipa_hwio_def_ipa_rsrc_mngr_sw_access_rsrv_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RSRC_MNGR_SW_ACCESS_CMD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rsrc_mngr_sw_access_cmd_s +{ + u32 alloc_valid : 1; + u32 srch_valid : 1; + u32 rel_valid : 1; + u32 rsrv_valid : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rsrc_mngr_sw_access_cmd_u +{ + struct ipa_hwio_def_ipa_rsrc_mngr_sw_access_cmd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RSRC_MNGR_SW_ACCESS_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rsrc_mngr_sw_access_status_s +{ + u32 alloc_ready : 1; + u32 srch_ready : 1; + u32 rel_ready : 1; + u32 rsrv_ready : 1; + u32 alloc_rsrc_id_next : 6; + u32 reserved0 : 2; + u32 srch_rsrc_id_next : 6; + u32 reserved1 : 14; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rsrc_mngr_sw_access_status_u +{ + struct ipa_hwio_def_ipa_rsrc_mngr_sw_access_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RSRC_MNGR_DB_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rsrc_mngr_db_cfg_s +{ + u32 rsrc_grp_sel : 3; + u32 reserved0 : 1; + u32 rsrc_type_sel : 3; + u32 reserved1 : 1; + u32 rsrc_id_sel : 6; + u32 reserved2 : 18; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rsrc_mngr_db_cfg_u +{ + struct ipa_hwio_def_ipa_rsrc_mngr_db_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RSRC_MNGR_DB_RSRC_READ +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rsrc_mngr_db_rsrc_read_s +{ + u32 rsrc_occupied : 1; + u32 rsrc_next_valid : 1; + u32 reserved0 : 2; + u32 rsrc_next_index : 6; + u32 reserved1 : 22; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rsrc_mngr_db_rsrc_read_u +{ + struct ipa_hwio_def_ipa_rsrc_mngr_db_rsrc_read_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RSRC_MNGR_DB_LIST_READ +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rsrc_mngr_db_list_read_s +{ + u32 rsrc_list_valid : 1; + u32 rsrc_list_hold : 1; + u32 reserved0 : 2; + u32 rsrc_list_head_rsrc : 6; + u32 reserved1 : 2; + u32 rsrc_list_head_cnt : 7; + u32 reserved2 : 1; + u32 rsrc_list_entry_cnt : 7; + u32 reserved3 : 5; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rsrc_mngr_db_list_read_u +{ + struct ipa_hwio_def_ipa_rsrc_mngr_db_list_read_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RSRC_MNGR_CONTEXTS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rsrc_mngr_contexts_s +{ + u32 rsrc_occupied_contexts_bitmap : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rsrc_mngr_contexts_u +{ + struct ipa_hwio_def_ipa_rsrc_mngr_contexts_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_BRESP_DB_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_bresp_db_cfg_s +{ + u32 sel_entry : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_bresp_db_cfg_u +{ + struct ipa_hwio_def_ipa_bresp_db_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_BRESP_DB_DATA +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_bresp_db_data_s +{ + u32 data : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_bresp_db_data_u +{ + struct ipa_hwio_def_ipa_bresp_db_data_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_SNOC_MONITORING_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_snoc_monitoring_cfg_s +{ + u32 enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_snoc_monitoring_cfg_u +{ + struct ipa_hwio_def_ipa_snoc_monitoring_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_PCIE_SNOC_MONITOR_CNT +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_pcie_snoc_monitor_cnt_s +{ + u32 ar_value : 5; + u32 reserved0 : 1; + u32 aw_value : 5; + u32 reserved1 : 1; + u32 r_value : 5; + u32 reserved2 : 1; + u32 w_value : 5; + u32 reserved3 : 1; + u32 b_value : 5; + u32 reserved4 : 3; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_pcie_snoc_monitor_cnt_u +{ + struct ipa_hwio_def_ipa_pcie_snoc_monitor_cnt_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DDR_SNOC_MONITOR_CNT +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ddr_snoc_monitor_cnt_s +{ + u32 ar_value : 5; + u32 reserved0 : 1; + u32 aw_value : 5; + u32 reserved1 : 1; + u32 r_value : 5; + u32 reserved2 : 1; + u32 w_value : 5; + u32 reserved3 : 1; + u32 b_value : 5; + u32 reserved4 : 3; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ddr_snoc_monitor_cnt_u +{ + struct ipa_hwio_def_ipa_ddr_snoc_monitor_cnt_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_SNOC_MONITOR_CNT +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_snoc_monitor_cnt_s +{ + u32 ar_value : 5; + u32 reserved0 : 1; + u32 aw_value : 5; + u32 reserved1 : 1; + u32 r_value : 5; + u32 reserved2 : 1; + u32 w_value : 5; + u32 reserved3 : 1; + u32 b_value : 5; + u32 reserved4 : 3; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_snoc_monitor_cnt_u +{ + struct ipa_hwio_def_ipa_gsi_snoc_monitor_cnt_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DEBUG_DATA +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_debug_data_s +{ + u32 debug_data : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_debug_data_u +{ + struct ipa_hwio_def_ipa_debug_data_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_TESTBUS_SEL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_testbus_sel_s +{ + u32 testbus_en : 1; + u32 reserved0 : 3; + u32 external_block_select : 8; + u32 internal_block_select : 8; + u32 reserved1 : 12; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_testbus_sel_u +{ + struct ipa_hwio_def_ipa_testbus_sel_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_HW_EVENTS_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_hw_events_cfg_s +{ + u32 hw_events_select : 4; + u32 rx_events_pipe_select : 8; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_hw_events_cfg_u +{ + struct ipa_hwio_def_ipa_hw_events_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_CONS_LOG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_cons_log_s +{ + u32 reserved0 : 1; + u32 log_en : 1; + u32 reserved1 : 2; + u32 log_pipe : 8; + u32 log_length : 8; + u32 log_reduction_en : 1; + u32 log_dpl_l2_remove_en : 1; + u32 reserved2 : 10; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_cons_log_u +{ + struct ipa_hwio_def_ipa_cons_log_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_LOG_BUF_HW_CMD_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_log_buf_hw_cmd_addr_s +{ + u32 start_addr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_log_buf_hw_cmd_addr_u +{ + struct ipa_hwio_def_ipa_log_buf_hw_cmd_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_LOG_BUF_HW_CMD_ADDR_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_log_buf_hw_cmd_addr_msb_s +{ + u32 start_addr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_log_buf_hw_cmd_addr_msb_u +{ + struct ipa_hwio_def_ipa_log_buf_hw_cmd_addr_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_LOG_BUF_HW_CMD_WRITE_PTR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_log_buf_hw_cmd_write_ptr_s +{ + u32 writr_addr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_log_buf_hw_cmd_write_ptr_u +{ + struct ipa_hwio_def_ipa_log_buf_hw_cmd_write_ptr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_LOG_BUF_HW_CMD_WRITE_PTR_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_log_buf_hw_cmd_write_ptr_msb_s +{ + u32 writr_addr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_log_buf_hw_cmd_write_ptr_msb_u +{ + struct ipa_hwio_def_ipa_log_buf_hw_cmd_write_ptr_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_LOG_BUF_HW_CMD_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_log_buf_hw_cmd_cfg_s +{ + u32 size : 16; + u32 enable : 1; + u32 skip_ddr_dma : 1; + u32 tpdm_enable : 1; + u32 tpdm_ts_en : 1; + u32 reserved0 : 12; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_log_buf_hw_cmd_cfg_u +{ + struct ipa_hwio_def_ipa_log_buf_hw_cmd_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_LOG_BUF_HW_CMD_RAM_PTR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_log_buf_hw_cmd_ram_ptr_s +{ + u32 read_ptr : 14; + u32 reserved0 : 2; + u32 write_ptr : 14; + u32 full : 1; + u32 skip_ddr_wrap_happened : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_log_buf_hw_cmd_ram_ptr_u +{ + struct ipa_hwio_def_ipa_log_buf_hw_cmd_ram_ptr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_log_buf_hw_cmd_noc_master_sel_s +{ + u32 noc_port_sel : 1; + u32 qmb_rd_en : 1; + u32 qmb_wr_en : 1; + u32 gsi_rd_en : 1; + u32 gsi_wr_en : 1; + u32 uc_rd_en : 1; + u32 uc_wr_en : 1; + u32 qmb_resp_en : 1; + u32 gsi_resp_en : 1; + u32 uc_resp_en : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_log_buf_hw_cmd_noc_master_sel_u +{ + struct ipa_hwio_def_ipa_log_buf_hw_cmd_noc_master_sel_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_BRESP_DB_DATA_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_bresp_db_data_1_s +{ + u32 data : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_bresp_db_data_1_u +{ + struct ipa_hwio_def_ipa_bresp_db_data_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_BUS_MASTER_LEGACY_BURSTS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_bus_master_legacy_bursts_s +{ + u32 cross_128b_fetcher_imm_cmd : 1; + u32 cross_128b_fetcher_dmar : 1; + u32 cross_128b_dfetcher_ddmar : 1; + u32 cross_128b_drbip_ddmar : 1; + u32 cross_128b_hdri : 1; + u32 cross_128b_rqos : 1; + u32 cross_128b_uc_qmb : 1; + u32 reserved0 : 25; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_bus_master_legacy_bursts_u +{ + struct ipa_hwio_def_ipa_bus_master_legacy_bursts_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_CONS_LOG_THRESHOLD_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_cons_log_threshold_cfg_s +{ + u32 threshold : 12; + u32 reserved0 : 4; + u32 threshold_en : 1; + u32 reserved1 : 3; + u32 threshold_timer_gran_sel : 4; + u32 reserved2 : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_cons_log_threshold_cfg_u +{ + struct ipa_hwio_def_ipa_cons_log_threshold_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_PROD_LOG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_prod_log_s +{ + u32 reserved0 : 1; + u32 log_en : 1; + u32 reserved1 : 2; + u32 log_pipe : 8; + u32 log_length : 8; + u32 log_reduction_en : 1; + u32 log_dpl_l2_remove_en : 1; + u32 reserved2 : 10; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_prod_log_u +{ + struct ipa_hwio_def_ipa_prod_log_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_PROD_LOG_THRESHOLD_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_prod_log_threshold_cfg_s +{ + u32 threshold : 12; + u32 reserved0 : 4; + u32 threshold_en : 1; + u32 reserved1 : 3; + u32 threshold_timer_gran_sel : 4; + u32 reserved2 : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_prod_log_threshold_cfg_u +{ + struct ipa_hwio_def_ipa_prod_log_threshold_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_ACKQ_CMD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_ackq_cmd_s +{ + u32 write_cmd : 1; + u32 pop_cmd : 1; + u32 release_rd_cmd : 1; + u32 release_wr_cmd : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_ackq_cmd_u +{ + struct ipa_hwio_def_ipa_rx_ackq_cmd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_ACKQ_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_ackq_cfg_s +{ + u32 block_rd_req : 1; + u32 block_wr : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_ackq_cfg_u +{ + struct ipa_hwio_def_ipa_rx_ackq_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_ACKQ_DATA_WR_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_ackq_data_wr_0_s +{ + u32 ack_value1 : 16; + u32 ack_value2 : 8; + u32 ack_value1_type : 1; + u32 reserved0 : 7; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_ackq_data_wr_0_u +{ + struct ipa_hwio_def_ipa_rx_ackq_data_wr_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_ACKQ_DATA_RD_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_ackq_data_rd_0_s +{ + u32 ack_value1 : 16; + u32 ack_value2 : 8; + u32 ack_value1_type : 1; + u32 reserved0 : 7; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_ackq_data_rd_0_u +{ + struct ipa_hwio_def_ipa_rx_ackq_data_rd_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_ACKQ_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_ackq_status_s +{ + u32 status : 1; + u32 ackq_empty : 1; + u32 ackq_full : 1; + u32 reserved0 : 1; + u32 ackq_count : 4; + u32 ackq_depth : 4; + u32 block_rd_ack : 1; + u32 reserved1 : 19; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_ackq_status_u +{ + struct ipa_hwio_def_ipa_rx_ackq_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_ACKQ_CMD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_ackq_cmd_s +{ + u32 write_cmd : 1; + u32 pop_cmd : 1; + u32 release_rd_cmd : 1; + u32 release_wr_cmd : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_ackq_cmd_u +{ + struct ipa_hwio_def_ipa_uc_ackq_cmd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_ACKQ_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_ackq_cfg_s +{ + u32 block_rd : 1; + u32 block_wr : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_ackq_cfg_u +{ + struct ipa_hwio_def_ipa_uc_ackq_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_ACKQ_DATA_WR_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_ackq_data_wr_0_s +{ + u32 ack_value1 : 16; + u32 ack_value2 : 8; + u32 ack_value1_type : 1; + u32 reserved0 : 7; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_ackq_data_wr_0_u +{ + struct ipa_hwio_def_ipa_uc_ackq_data_wr_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_ACKQ_DATA_RD_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_ackq_data_rd_0_s +{ + u32 ack_value1 : 16; + u32 ack_value2 : 8; + u32 ack_value1_type : 1; + u32 reserved0 : 7; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_ackq_data_rd_0_u +{ + struct ipa_hwio_def_ipa_uc_ackq_data_rd_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_ACKQ_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_ackq_status_s +{ + u32 status : 1; + u32 ackq_empty : 1; + u32 ackq_full : 1; + u32 reserved0 : 1; + u32 ackq_count : 5; + u32 reserved1 : 3; + u32 ackq_depth : 5; + u32 reserved2 : 15; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_ackq_status_u +{ + struct ipa_hwio_def_ipa_uc_ackq_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_SPLT_CMDQ_CMD_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_splt_cmdq_cmd_n_s +{ + u32 write_cmd : 1; + u32 pop_cmd : 1; + u32 release_rd_cmd : 1; + u32 release_wr_cmd : 1; + u32 release_rd_pkt : 1; + u32 release_wr_pkt : 1; + u32 release_rd_pkt_enhanced : 1; + u32 reserved0 : 25; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_splt_cmdq_cmd_n_u +{ + struct ipa_hwio_def_ipa_rx_splt_cmdq_cmd_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_SPLT_CMDQ_CFG_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_splt_cmdq_cfg_n_s +{ + u32 block_rd : 1; + u32 block_wr : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_splt_cmdq_cfg_n_u +{ + struct ipa_hwio_def_ipa_rx_splt_cmdq_cfg_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_SPLT_CMDQ_DATA_WR_0_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_splt_cmdq_data_wr_0_n_s +{ + u32 cmdq_packet_len_f : 16; + u32 cmdq_src_len_f : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_splt_cmdq_data_wr_0_n_u +{ + struct ipa_hwio_def_ipa_rx_splt_cmdq_data_wr_0_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_SPLT_CMDQ_DATA_WR_1_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_splt_cmdq_data_wr_1_n_s +{ + u32 cmdq_src_pipe_f : 8; + u32 cmdq_order_f : 2; + u32 cmdq_flags_f : 6; + u32 cmdq_opcode_f : 8; + u32 cmdq_metadata_f : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_splt_cmdq_data_wr_1_n_u +{ + struct ipa_hwio_def_ipa_rx_splt_cmdq_data_wr_1_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_SPLT_CMDQ_DATA_WR_2_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_splt_cmdq_data_wr_2_n_s +{ + u32 cmdq_stats_disable_f : 1; + u32 cmdq_addr_lsb_f : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_splt_cmdq_data_wr_2_n_u +{ + struct ipa_hwio_def_ipa_rx_splt_cmdq_data_wr_2_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_SPLT_CMDQ_DATA_WR_3_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_splt_cmdq_data_wr_3_n_s +{ + u32 cmdq_addr_msb_f : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_splt_cmdq_data_wr_3_n_u +{ + struct ipa_hwio_def_ipa_rx_splt_cmdq_data_wr_3_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_SPLT_CMDQ_DATA_RD_0_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_splt_cmdq_data_rd_0_n_s +{ + u32 cmdq_packet_len_f : 16; + u32 cmdq_src_len_f : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_splt_cmdq_data_rd_0_n_u +{ + struct ipa_hwio_def_ipa_rx_splt_cmdq_data_rd_0_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_SPLT_CMDQ_DATA_RD_1_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_splt_cmdq_data_rd_1_n_s +{ + u32 cmdq_src_pipe_f : 8; + u32 cmdq_order_f : 2; + u32 cmdq_flags_f : 6; + u32 cmdq_opcode_f : 8; + u32 cmdq_metadata_f : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_splt_cmdq_data_rd_1_n_u +{ + struct ipa_hwio_def_ipa_rx_splt_cmdq_data_rd_1_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_SPLT_CMDQ_DATA_RD_2_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_splt_cmdq_data_rd_2_n_s +{ + u32 cmdq_stats_disable_f : 1; + u32 cmdq_addr_lsb_f : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_splt_cmdq_data_rd_2_n_u +{ + struct ipa_hwio_def_ipa_rx_splt_cmdq_data_rd_2_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_SPLT_CMDQ_DATA_RD_3_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_splt_cmdq_data_rd_3_n_s +{ + u32 cmdq_addr_msb_f : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_splt_cmdq_data_rd_3_n_u +{ + struct ipa_hwio_def_ipa_rx_splt_cmdq_data_rd_3_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_SPLT_CMDQ_STATUS_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_splt_cmdq_status_n_s +{ + u32 status : 1; + u32 cmdq_empty : 1; + u32 cmdq_full : 1; + u32 cmdq_count : 2; + u32 cmdq_depth : 2; + u32 reserved0 : 25; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_splt_cmdq_status_n_u +{ + struct ipa_hwio_def_ipa_rx_splt_cmdq_status_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_HPS_CMDQ_CMD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_hps_cmdq_cmd_s +{ + u32 write_cmd : 1; + u32 pop_cmd : 1; + u32 cmd_client : 3; + u32 rd_req : 1; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_hps_cmdq_cmd_u +{ + struct ipa_hwio_def_ipa_rx_hps_cmdq_cmd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_HPS_CMDQ_RELEASE_WR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_hps_cmdq_release_wr_s +{ + u32 release_wr_cmd : 6; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_hps_cmdq_release_wr_u +{ + struct ipa_hwio_def_ipa_rx_hps_cmdq_release_wr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_HPS_CMDQ_RELEASE_RD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_hps_cmdq_release_rd_s +{ + u32 release_rd_cmd : 6; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_hps_cmdq_release_rd_u +{ + struct ipa_hwio_def_ipa_rx_hps_cmdq_release_rd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_HPS_CMDQ_CFG_WR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_hps_cmdq_cfg_wr_s +{ + u32 block_wr : 6; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_hps_cmdq_cfg_wr_u +{ + struct ipa_hwio_def_ipa_rx_hps_cmdq_cfg_wr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_HPS_CMDQ_CFG_RD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_hps_cmdq_cfg_rd_s +{ + u32 block_rd : 6; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_hps_cmdq_cfg_rd_u +{ + struct ipa_hwio_def_ipa_rx_hps_cmdq_cfg_rd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_HPS_CMDQ_DATA_WR_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_hps_cmdq_data_wr_0_s +{ + u32 cmdq_packet_len_f : 16; + u32 cmdq_dest_len_f : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_hps_cmdq_data_wr_0_u +{ + struct ipa_hwio_def_ipa_rx_hps_cmdq_data_wr_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_HPS_CMDQ_DATA_WR_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_hps_cmdq_data_wr_1_s +{ + u32 cmdq_src_pipe_f : 8; + u32 cmdq_order_f : 2; + u32 cmdq_flags_f : 6; + u32 cmdq_opcode_f : 8; + u32 cmdq_metadata_f : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_hps_cmdq_data_wr_1_u +{ + struct ipa_hwio_def_ipa_rx_hps_cmdq_data_wr_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_HPS_CMDQ_DATA_WR_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_hps_cmdq_data_wr_2_s +{ + u32 cmdq_stats_disable_f : 1; + u32 cmdq_addr_lsb_f : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_hps_cmdq_data_wr_2_u +{ + struct ipa_hwio_def_ipa_rx_hps_cmdq_data_wr_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_HPS_CMDQ_DATA_WR_3 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_hps_cmdq_data_wr_3_s +{ + u32 cmdq_addr_msb_f : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_hps_cmdq_data_wr_3_u +{ + struct ipa_hwio_def_ipa_rx_hps_cmdq_data_wr_3_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_HPS_CMDQ_DATA_RD_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_0_s +{ + u32 cmdq_packet_len_f : 16; + u32 cmdq_dest_len_f : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_0_u +{ + struct ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_HPS_CMDQ_DATA_RD_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_1_s +{ + u32 cmdq_src_pipe_f : 8; + u32 cmdq_order_f : 2; + u32 cmdq_flags_f : 6; + u32 cmdq_opcode_f : 8; + u32 cmdq_metadata_f : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_1_u +{ + struct ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_HPS_CMDQ_DATA_RD_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_2_s +{ + u32 cmdq_stats_disable_f : 1; + u32 cmdq_addr_lsb_f : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_2_u +{ + struct ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_HPS_CMDQ_DATA_RD_3 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_3_s +{ + u32 cmdq_addr_msb_f : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_3_u +{ + struct ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_3_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_HPS_CMDQ_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_hps_cmdq_status_s +{ + u32 status : 1; + u32 cmdq_full : 1; + u32 cmdq_depth : 7; + u32 reserved0 : 23; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_hps_cmdq_status_u +{ + struct ipa_hwio_def_ipa_rx_hps_cmdq_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_HPS_CMDQ_STATUS_EMPTY +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_hps_cmdq_status_empty_s +{ + u32 cmdq_empty : 6; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_hps_cmdq_status_empty_u +{ + struct ipa_hwio_def_ipa_rx_hps_cmdq_status_empty_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_HPS_SNP +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_hps_snp_s +{ + u32 snp_last : 1; + u32 snp_write : 1; + u32 snp_valid : 1; + u32 snp_next_is_valid : 1; + u32 snp_next : 4; + u32 snp_head : 4; + u32 snp_addr : 4; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_hps_snp_u +{ + struct ipa_hwio_def_ipa_rx_hps_snp_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_HPS_CMDQ_COUNT +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_hps_cmdq_count_s +{ + u32 fifo_count : 7; + u32 reserved0 : 25; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_hps_cmdq_count_u +{ + struct ipa_hwio_def_ipa_rx_hps_cmdq_count_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_HPS_CLIENTS_MIN_DEPTH_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_hps_clients_min_depth_0_s +{ + u32 client_0_min_depth : 4; + u32 reserved0 : 4; + u32 client_1_min_depth : 4; + u32 reserved1 : 4; + u32 client_2_min_depth : 4; + u32 reserved2 : 4; + u32 client_3_min_depth : 4; + u32 client_4_min_depth : 4; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_hps_clients_min_depth_0_u +{ + struct ipa_hwio_def_ipa_rx_hps_clients_min_depth_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_HPS_CLIENTS_MIN_DEPTH_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_hps_clients_min_depth_1_s +{ + u32 client_5_min_depth : 4; + u32 reserved0 : 4; + u32 client_6_min_depth : 4; + u32 reserved1 : 4; + u32 client_7_min_depth : 4; + u32 reserved2 : 4; + u32 client_8_min_depth : 4; + u32 client_9_min_depth : 4; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_hps_clients_min_depth_1_u +{ + struct ipa_hwio_def_ipa_rx_hps_clients_min_depth_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_HPS_CLIENTS_MAX_DEPTH_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_hps_clients_max_depth_0_s +{ + u32 client_0_max_depth : 4; + u32 reserved0 : 4; + u32 client_1_max_depth : 4; + u32 reserved1 : 4; + u32 client_2_max_depth : 4; + u32 reserved2 : 4; + u32 client_3_max_depth : 4; + u32 client_4_max_depth : 4; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_hps_clients_max_depth_0_u +{ + struct ipa_hwio_def_ipa_rx_hps_clients_max_depth_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_HPS_CLIENTS_MAX_DEPTH_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_hps_clients_max_depth_1_s +{ + u32 client_5_max_depth : 4; + u32 reserved0 : 4; + u32 client_6_max_depth : 4; + u32 reserved1 : 4; + u32 client_7_max_depth : 4; + u32 reserved2 : 4; + u32 client_8_max_depth : 4; + u32 client_9_max_depth : 4; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_hps_clients_max_depth_1_u +{ + struct ipa_hwio_def_ipa_rx_hps_clients_max_depth_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_HPS_DPS_CMDQ_CMD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_hps_dps_cmdq_cmd_s +{ + u32 write_cmd : 1; + u32 pop_cmd : 1; + u32 rd_req : 1; + u32 reserved0 : 1; + u32 cmd_client : 8; + u32 reserved1 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_hps_dps_cmdq_cmd_u +{ + struct ipa_hwio_def_ipa_hps_dps_cmdq_cmd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_HPS_DPS_CMDQ_DATA_WR_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_hps_dps_cmdq_data_wr_0_s +{ + u32 cmdq_ctx_id_f : 4; + u32 cmdq_src_id_f : 8; + u32 cmdq_src_pipe_f : 8; + u32 cmdq_opcode_f : 2; + u32 cmdq_type_f : 1; + u32 cmdq_virt_cod_f : 1; + u32 reserved0 : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_hps_dps_cmdq_data_wr_0_u +{ + struct ipa_hwio_def_ipa_hps_dps_cmdq_data_wr_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_HPS_DPS_CMDQ_DATA_RD_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_hps_dps_cmdq_data_rd_0_s +{ + u32 cmdq_ctx_id_f : 4; + u32 cmdq_src_id_f : 8; + u32 cmdq_src_pipe_f : 8; + u32 cmdq_opcode_f : 2; + u32 cmdq_type_f : 1; + u32 cmdq_virt_cod_f : 1; + u32 reserved0 : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_hps_dps_cmdq_data_rd_0_u +{ + struct ipa_hwio_def_ipa_hps_dps_cmdq_data_rd_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_HPS_DPS_CMDQ_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_hps_dps_cmdq_status_s +{ + u32 status : 1; + u32 cmdq_full : 1; + u32 reserved0 : 2; + u32 cmdq_depth : 8; + u32 reserved1 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_hps_dps_cmdq_status_u +{ + struct ipa_hwio_def_ipa_hps_dps_cmdq_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_HPS_DPS_SNP +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_hps_dps_snp_s +{ + u32 snp_last : 1; + u32 snp_write : 1; + u32 snp_valid : 1; + u32 snp_next_is_valid : 1; + u32 snp_next : 8; + u32 snp_head : 8; + u32 snp_addr : 8; + u32 reserved0 : 4; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_hps_dps_snp_u +{ + struct ipa_hwio_def_ipa_hps_dps_snp_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_HPS_DPS_CMDQ_COUNT +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_hps_dps_cmdq_count_s +{ + u32 fifo_count : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_hps_dps_cmdq_count_u +{ + struct ipa_hwio_def_ipa_hps_dps_cmdq_count_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_HPS_DPS_CMDQ_RELEASE_WR_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_hps_dps_cmdq_release_wr_n_s +{ + u32 release_wr_cmd : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_hps_dps_cmdq_release_wr_n_u +{ + struct ipa_hwio_def_ipa_hps_dps_cmdq_release_wr_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_HPS_DPS_CMDQ_RELEASE_RD_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_hps_dps_cmdq_release_rd_n_s +{ + u32 release_rd_cmd : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_hps_dps_cmdq_release_rd_n_u +{ + struct ipa_hwio_def_ipa_hps_dps_cmdq_release_rd_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_HPS_DPS_CMDQ_CFG_WR_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_hps_dps_cmdq_cfg_wr_n_s +{ + u32 block_wr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_hps_dps_cmdq_cfg_wr_n_u +{ + struct ipa_hwio_def_ipa_hps_dps_cmdq_cfg_wr_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_HPS_DPS_CMDQ_CFG_RD_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_hps_dps_cmdq_cfg_rd_n_s +{ + u32 block_rd : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_hps_dps_cmdq_cfg_rd_n_u +{ + struct ipa_hwio_def_ipa_hps_dps_cmdq_cfg_rd_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_HPS_DPS_CMDQ_STATUS_EMPTY_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_hps_dps_cmdq_status_empty_n_s +{ + u32 cmdq_empty : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_hps_dps_cmdq_status_empty_n_u +{ + struct ipa_hwio_def_ipa_hps_dps_cmdq_status_empty_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DPS_TX_CMDQ_CMD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_dps_tx_cmdq_cmd_s +{ + u32 write_cmd : 1; + u32 pop_cmd : 1; + u32 rd_req : 1; + u32 cmd_client : 4; + u32 reserved0 : 25; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_dps_tx_cmdq_cmd_u +{ + struct ipa_hwio_def_ipa_dps_tx_cmdq_cmd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DPS_TX_CMDQ_RELEASE_WR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_dps_tx_cmdq_release_wr_s +{ + u32 release_wr_cmd : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_dps_tx_cmdq_release_wr_u +{ + struct ipa_hwio_def_ipa_dps_tx_cmdq_release_wr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DPS_TX_CMDQ_RELEASE_RD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_dps_tx_cmdq_release_rd_s +{ + u32 release_rd_cmd : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_dps_tx_cmdq_release_rd_u +{ + struct ipa_hwio_def_ipa_dps_tx_cmdq_release_rd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DPS_TX_CMDQ_CFG_WR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_dps_tx_cmdq_cfg_wr_s +{ + u32 block_wr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_dps_tx_cmdq_cfg_wr_u +{ + struct ipa_hwio_def_ipa_dps_tx_cmdq_cfg_wr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DPS_TX_CMDQ_CFG_RD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_dps_tx_cmdq_cfg_rd_s +{ + u32 block_rd : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_dps_tx_cmdq_cfg_rd_u +{ + struct ipa_hwio_def_ipa_dps_tx_cmdq_cfg_rd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DPS_TX_CMDQ_DATA_WR_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_dps_tx_cmdq_data_wr_0_s +{ + u32 cmdq_ctx_id_f : 4; + u32 cmdq_src_id_f : 8; + u32 cmdq_src_pipe_f : 8; + u32 cmdq_opcode_f : 2; + u32 cmdq_type_f : 1; + u32 cmdq_virt_cod_f : 1; + u32 seg_valid_f : 1; + u32 seg_ctx_id_f : 2; + u32 reserved0 : 5; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_dps_tx_cmdq_data_wr_0_u +{ + struct ipa_hwio_def_ipa_dps_tx_cmdq_data_wr_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DPS_TX_CMDQ_DATA_RD_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_dps_tx_cmdq_data_rd_0_s +{ + u32 cmdq_ctx_id_f : 4; + u32 cmdq_src_id_f : 8; + u32 cmdq_src_pipe_f : 8; + u32 cmdq_opcode_f : 2; + u32 cmdq_type_f : 1; + u32 cmdq_virt_cod_f : 1; + u32 seg_valid_f : 1; + u32 seg_ctx_id_f : 2; + u32 reserved0 : 5; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_dps_tx_cmdq_data_rd_0_u +{ + struct ipa_hwio_def_ipa_dps_tx_cmdq_data_rd_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DPS_TX_CMDQ_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_dps_tx_cmdq_status_s +{ + u32 status : 1; + u32 cmdq_full : 1; + u32 reserved0 : 2; + u32 cmdq_depth : 8; + u32 reserved1 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_dps_tx_cmdq_status_u +{ + struct ipa_hwio_def_ipa_dps_tx_cmdq_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DPS_TX_CMDQ_STATUS_EMPTY +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_dps_tx_cmdq_status_empty_s +{ + u32 cmdq_empty : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_dps_tx_cmdq_status_empty_u +{ + struct ipa_hwio_def_ipa_dps_tx_cmdq_status_empty_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DPS_TX_SNP +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_dps_tx_snp_s +{ + u32 snp_last : 1; + u32 snp_write : 1; + u32 snp_valid : 1; + u32 snp_next_is_valid : 1; + u32 snp_next : 8; + u32 snp_head : 8; + u32 snp_addr : 8; + u32 reserved0 : 4; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_dps_tx_snp_u +{ + struct ipa_hwio_def_ipa_dps_tx_snp_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DPS_TX_CMDQ_COUNT +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_dps_tx_cmdq_count_s +{ + u32 fifo_count : 7; + u32 reserved0 : 25; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_dps_tx_cmdq_count_u +{ + struct ipa_hwio_def_ipa_dps_tx_cmdq_count_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_LOG_BUF_HW_SNIF_EL_CFG_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_log_buf_hw_snif_el_cfg_n_s +{ + u32 snif_el_enable : 1; + u32 reserved0 : 3; + u32 snif_el_select : 5; + u32 reserved1 : 23; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_log_buf_hw_snif_el_cfg_n_u +{ + struct ipa_hwio_def_ipa_log_buf_hw_snif_el_cfg_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_log_buf_hw_snif_el_comp_val_0_cli_n_s +{ + u32 value : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_log_buf_hw_snif_el_comp_val_0_cli_n_u +{ + struct ipa_hwio_def_ipa_log_buf_hw_snif_el_comp_val_0_cli_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_log_buf_hw_snif_el_comp_val_1_cli_n_s +{ + u32 value : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_log_buf_hw_snif_el_comp_val_1_cli_n_u +{ + struct ipa_hwio_def_ipa_log_buf_hw_snif_el_comp_val_1_cli_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_log_buf_hw_snif_el_comp_val_2_cli_n_s +{ + u32 value : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_log_buf_hw_snif_el_comp_val_2_cli_n_u +{ + struct ipa_hwio_def_ipa_log_buf_hw_snif_el_comp_val_2_cli_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_log_buf_hw_snif_el_comp_val_3_cli_n_s +{ + u32 value : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_log_buf_hw_snif_el_comp_val_3_cli_n_u +{ + struct ipa_hwio_def_ipa_log_buf_hw_snif_el_comp_val_3_cli_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_log_buf_hw_snif_el_mask_val_0_cli_n_s +{ + u32 value : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_log_buf_hw_snif_el_mask_val_0_cli_n_u +{ + struct ipa_hwio_def_ipa_log_buf_hw_snif_el_mask_val_0_cli_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_log_buf_hw_snif_el_mask_val_1_cli_n_s +{ + u32 value : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_log_buf_hw_snif_el_mask_val_1_cli_n_u +{ + struct ipa_hwio_def_ipa_log_buf_hw_snif_el_mask_val_1_cli_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_log_buf_hw_snif_el_mask_val_2_cli_n_s +{ + u32 value : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_log_buf_hw_snif_el_mask_val_2_cli_n_u +{ + struct ipa_hwio_def_ipa_log_buf_hw_snif_el_mask_val_2_cli_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_log_buf_hw_snif_el_mask_val_3_cli_n_s +{ + u32 value : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_log_buf_hw_snif_el_mask_val_3_cli_n_u +{ + struct ipa_hwio_def_ipa_log_buf_hw_snif_el_mask_val_3_cli_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_LOG_BUF_HW_SNIF_LEGACY_RX +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_log_buf_hw_snif_legacy_rx_s +{ + u32 src_group_sel : 3; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_log_buf_hw_snif_legacy_rx_u +{ + struct ipa_hwio_def_ipa_log_buf_hw_snif_legacy_rx_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ACKMNGR_CMDQ_CMD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ackmngr_cmdq_cmd_s +{ + u32 write_cmd : 1; + u32 pop_cmd : 1; + u32 cmd_client : 8; + u32 rd_req : 1; + u32 reserved0 : 21; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ackmngr_cmdq_cmd_u +{ + struct ipa_hwio_def_ipa_ackmngr_cmdq_cmd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ACKMNGR_CMDQ_DATA_RD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ackmngr_cmdq_data_rd_s +{ + u32 cmdq_src_id : 8; + u32 cmdq_length : 16; + u32 cmdq_origin : 1; + u32 cmdq_sent : 1; + u32 cmdq_src_id_valid : 1; + u32 cmdq_error : 1; + u32 reserved0 : 4; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ackmngr_cmdq_data_rd_u +{ + struct ipa_hwio_def_ipa_ackmngr_cmdq_data_rd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ACKMNGR_CMDQ_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ackmngr_cmdq_status_s +{ + u32 status : 1; + u32 cmdq_full : 1; + u32 cmdq_depth : 7; + u32 reserved0 : 23; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ackmngr_cmdq_status_u +{ + struct ipa_hwio_def_ipa_ackmngr_cmdq_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ACKMNGR_CMDQ_STATUS_EMPTY_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ackmngr_cmdq_status_empty_n_s +{ + u32 cmdq_empty : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ackmngr_cmdq_status_empty_n_u +{ + struct ipa_hwio_def_ipa_ackmngr_cmdq_status_empty_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ACKMNGR_CMDQ_COUNT +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ackmngr_cmdq_count_s +{ + u32 fifo_count : 7; + u32 reserved0 : 25; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ackmngr_cmdq_count_u +{ + struct ipa_hwio_def_ipa_ackmngr_cmdq_count_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_FIFO_STATUS_CTRL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_fifo_status_ctrl_s +{ + u32 ipa_gsi_fifo_status_port_sel : 5; + u32 ipa_gsi_fifo_status_en : 1; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_fifo_status_ctrl_u +{ + struct ipa_hwio_def_ipa_gsi_fifo_status_ctrl_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_TLV_FIFO_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_tlv_fifo_status_s +{ + u32 fifo_wr_ptr : 8; + u32 fifo_rd_ptr : 8; + u32 fifo_rd_pub_ptr : 8; + u32 fifo_empty : 1; + u32 fifo_empty_pub : 1; + u32 fifo_almost_full : 1; + u32 fifo_full : 1; + u32 fifo_almost_full_pub : 1; + u32 fifo_full_pub : 1; + u32 fifo_head_is_bubble : 1; + u32 reserved0 : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_tlv_fifo_status_u +{ + struct ipa_hwio_def_ipa_gsi_tlv_fifo_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GSI_AOS_FIFO_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_gsi_aos_fifo_status_s +{ + u32 fifo_wr_ptr : 8; + u32 fifo_rd_ptr : 8; + u32 fifo_rd_pub_ptr : 8; + u32 fifo_empty : 1; + u32 fifo_empty_pub : 1; + u32 fifo_almost_full : 1; + u32 fifo_full : 1; + u32 fifo_almost_full_pub : 1; + u32 fifo_full_pub : 1; + u32 fifo_head_is_bubble : 1; + u32 reserved0 : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_gsi_aos_fifo_status_u +{ + struct ipa_hwio_def_ipa_gsi_aos_fifo_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ENDP_GSI_CONS_BYTES_TLV +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_endp_gsi_cons_bytes_tlv_s +{ + u32 cons_bytes : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_endp_gsi_cons_bytes_tlv_u +{ + struct ipa_hwio_def_ipa_endp_gsi_cons_bytes_tlv_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ENDP_GSI_CONS_BYTES_AOS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_endp_gsi_cons_bytes_aos_s +{ + u32 cons_bytes : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_endp_gsi_cons_bytes_aos_u +{ + struct ipa_hwio_def_ipa_endp_gsi_cons_bytes_aos_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_LOG_BUF_HW_GEN_RAM_OFFSET +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_log_buf_hw_gen_ram_offset_s +{ + u32 ram_region_baddr : 19; + u32 reserved0 : 1; + u32 ram_region_size : 4; + u32 reserved1 : 7; + u32 enable : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_log_buf_hw_gen_ram_offset_u +{ + struct ipa_hwio_def_ipa_log_buf_hw_gen_ram_offset_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_RX_HND_CMDQ_CMD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_rx_hnd_cmdq_cmd_s +{ + u32 write_cmd : 1; + u32 pop_cmd : 1; + u32 release_rd_cmd : 1; + u32 release_wr_cmd : 1; + u32 release_rd_pkt : 1; + u32 release_wr_pkt : 1; + u32 release_rd_pkt_enhanced : 1; + u32 reserved0 : 25; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_rx_hnd_cmdq_cmd_u +{ + struct ipa_hwio_def_ipa_uc_rx_hnd_cmdq_cmd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_RX_HND_CMDQ_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_rx_hnd_cmdq_cfg_s +{ + u32 block_rd : 1; + u32 block_wr : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_rx_hnd_cmdq_cfg_u +{ + struct ipa_hwio_def_ipa_uc_rx_hnd_cmdq_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_RX_HND_CMDQ_DATA_WR_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_rx_hnd_cmdq_data_wr_0_s +{ + u32 cmdq_packet_len_f : 16; + u32 cmdq_src_len_f : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_rx_hnd_cmdq_data_wr_0_u +{ + struct ipa_hwio_def_ipa_uc_rx_hnd_cmdq_data_wr_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_RX_HND_CMDQ_DATA_WR_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_rx_hnd_cmdq_data_wr_1_s +{ + u32 cmdq_src_pipe_f : 8; + u32 cmdq_order_f : 2; + u32 cmdq_flags_f : 6; + u32 cmdq_opcode_f : 8; + u32 cmdq_metadata_f : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_rx_hnd_cmdq_data_wr_1_u +{ + struct ipa_hwio_def_ipa_uc_rx_hnd_cmdq_data_wr_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_RX_HND_CMDQ_DATA_WR_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_rx_hnd_cmdq_data_wr_2_s +{ + u32 cmdq_stats_disable_f : 1; + u32 cmdq_addr_lsb_f : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_rx_hnd_cmdq_data_wr_2_u +{ + struct ipa_hwio_def_ipa_uc_rx_hnd_cmdq_data_wr_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_RX_HND_CMDQ_DATA_WR_3 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_rx_hnd_cmdq_data_wr_3_s +{ + u32 cmdq_addr_msb_f : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_rx_hnd_cmdq_data_wr_3_u +{ + struct ipa_hwio_def_ipa_uc_rx_hnd_cmdq_data_wr_3_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_RX_HND_CMDQ_DATA_RD_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_rx_hnd_cmdq_data_rd_0_s +{ + u32 cmdq_packet_len_f : 16; + u32 cmdq_src_len_f : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_rx_hnd_cmdq_data_rd_0_u +{ + struct ipa_hwio_def_ipa_uc_rx_hnd_cmdq_data_rd_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_RX_HND_CMDQ_DATA_RD_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_rx_hnd_cmdq_data_rd_1_s +{ + u32 cmdq_src_pipe_f : 8; + u32 cmdq_order_f : 2; + u32 cmdq_flags_f : 6; + u32 cmdq_opcode_f : 8; + u32 cmdq_metadata_f : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_rx_hnd_cmdq_data_rd_1_u +{ + struct ipa_hwio_def_ipa_uc_rx_hnd_cmdq_data_rd_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_RX_HND_CMDQ_DATA_RD_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_rx_hnd_cmdq_data_rd_2_s +{ + u32 cmdq_stats_disable_f : 1; + u32 cmdq_addr_lsb_f : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_rx_hnd_cmdq_data_rd_2_u +{ + struct ipa_hwio_def_ipa_uc_rx_hnd_cmdq_data_rd_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_RX_HND_CMDQ_DATA_RD_3 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_rx_hnd_cmdq_data_rd_3_s +{ + u32 cmdq_addr_msb_f : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_rx_hnd_cmdq_data_rd_3_u +{ + struct ipa_hwio_def_ipa_uc_rx_hnd_cmdq_data_rd_3_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_UC_RX_HND_CMDQ_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_uc_rx_hnd_cmdq_status_s +{ + u32 status : 1; + u32 cmdq_empty : 1; + u32 cmdq_full : 1; + u32 cmdq_count : 4; + u32 cmdq_depth : 4; + u32 reserved0 : 21; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_uc_rx_hnd_cmdq_status_u +{ + struct ipa_hwio_def_ipa_uc_rx_hnd_cmdq_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RAM_HW_FIRST +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ram_hw_first_s +{ + u32 address : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ram_hw_first_u +{ + struct ipa_hwio_def_ipa_ram_hw_first_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RAM_HW_LAST +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ram_hw_last_s +{ + u32 address : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ram_hw_last_u +{ + struct ipa_hwio_def_ipa_ram_hw_last_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RAM_FRAG_FRST_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ram_frag_frst_base_addr_s +{ + u32 address : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ram_frag_frst_base_addr_u +{ + struct ipa_hwio_def_ipa_ram_frag_frst_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RAM_FRAG_SCND_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ram_frag_scnd_base_addr_s +{ + u32 address : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ram_frag_scnd_base_addr_u +{ + struct ipa_hwio_def_ipa_ram_frag_scnd_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RAM_GSI_TLV_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ram_gsi_tlv_base_addr_s +{ + u32 address : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ram_gsi_tlv_base_addr_u +{ + struct ipa_hwio_def_ipa_ram_gsi_tlv_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RAM_DCPH_KEYS_FIRST +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ram_dcph_keys_first_s +{ + u32 address : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ram_dcph_keys_first_u +{ + struct ipa_hwio_def_ipa_ram_dcph_keys_first_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RAM_DCPH_KEYS_LAST +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ram_dcph_keys_last_s +{ + u32 address : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ram_dcph_keys_last_u +{ + struct ipa_hwio_def_ipa_ram_dcph_keys_last_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DPS_SEQUENCER_FIRST +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_dps_sequencer_first_s +{ + u32 address : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_dps_sequencer_first_u +{ + struct ipa_hwio_def_ipa_dps_sequencer_first_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DPS_SEQUENCER_LAST +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_dps_sequencer_last_s +{ + u32 address : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_dps_sequencer_last_u +{ + struct ipa_hwio_def_ipa_dps_sequencer_last_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_HPS_SEQUENCER_FIRST +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_hps_sequencer_first_s +{ + u32 address : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_hps_sequencer_first_u +{ + struct ipa_hwio_def_ipa_hps_sequencer_first_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_HPS_SEQUENCER_LAST +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_hps_sequencer_last_s +{ + u32 address : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_hps_sequencer_last_u +{ + struct ipa_hwio_def_ipa_hps_sequencer_last_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RAM_PKT_CTX_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ram_pkt_ctx_base_addr_s +{ + u32 address : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ram_pkt_ctx_base_addr_u +{ + struct ipa_hwio_def_ipa_ram_pkt_ctx_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RAM_SW_AREA_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ram_sw_area_base_addr_s +{ + u32 address : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ram_sw_area_base_addr_u +{ + struct ipa_hwio_def_ipa_ram_sw_area_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RAM_HDRI_TYPE1_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ram_hdri_type1_base_addr_s +{ + u32 address : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ram_hdri_type1_base_addr_u +{ + struct ipa_hwio_def_ipa_ram_hdri_type1_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RAM_AGGR_NLO_COUNTERS_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ram_aggr_nlo_counters_base_addr_s +{ + u32 address : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ram_aggr_nlo_counters_base_addr_u +{ + struct ipa_hwio_def_ipa_ram_aggr_nlo_counters_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RAM_NLO_VP_CACHE_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ram_nlo_vp_cache_base_addr_s +{ + u32 address : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ram_nlo_vp_cache_base_addr_u +{ + struct ipa_hwio_def_ipa_ram_nlo_vp_cache_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RAM_COAL_VP_CACHE_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ram_coal_vp_cache_base_addr_s +{ + u32 address : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ram_coal_vp_cache_base_addr_u +{ + struct ipa_hwio_def_ipa_ram_coal_vp_cache_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RAM_COAL_VP_FIFO_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ram_coal_vp_fifo_base_addr_s +{ + u32 address : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ram_coal_vp_fifo_base_addr_u +{ + struct ipa_hwio_def_ipa_ram_coal_vp_fifo_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RAM_AGGR_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ram_aggr_base_addr_s +{ + u32 address : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ram_aggr_base_addr_u +{ + struct ipa_hwio_def_ipa_ram_aggr_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RAM_TX_COUNTERS_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ram_tx_counters_base_addr_s +{ + u32 address : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ram_tx_counters_base_addr_u +{ + struct ipa_hwio_def_ipa_ram_tx_counters_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RAM_CONS_DPL_FIFO_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ram_cons_dpl_fifo_base_addr_s +{ + u32 address : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ram_cons_dpl_fifo_base_addr_u +{ + struct ipa_hwio_def_ipa_ram_cons_dpl_fifo_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RAM_COAL_MASTER_VP_CTX_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ram_coal_master_vp_ctx_base_addr_s +{ + u32 address : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ram_coal_master_vp_ctx_base_addr_u +{ + struct ipa_hwio_def_ipa_ram_coal_master_vp_ctx_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RAM_COAL_MASTER_VP_AGGR_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ram_coal_master_vp_aggr_base_addr_s +{ + u32 address : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ram_coal_master_vp_aggr_base_addr_u +{ + struct ipa_hwio_def_ipa_ram_coal_master_vp_aggr_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RAM_COAL_SLAVE_VP_CTX_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ram_coal_slave_vp_ctx_base_addr_s +{ + u32 address : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ram_coal_slave_vp_ctx_base_addr_u +{ + struct ipa_hwio_def_ipa_ram_coal_slave_vp_ctx_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RAM_UL_NLO_AGGR_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ram_ul_nlo_aggr_base_addr_s +{ + u32 address : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ram_ul_nlo_aggr_base_addr_u +{ + struct ipa_hwio_def_ipa_ram_ul_nlo_aggr_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RAM_UC_IRAM_ADDR_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ram_uc_iram_addr_base_addr_s +{ + u32 address : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ram_uc_iram_addr_base_addr_u +{ + struct ipa_hwio_def_ipa_ram_uc_iram_addr_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RAM_SNIFFER_HW_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ram_sniffer_hw_base_addr_s +{ + u32 address : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ram_sniffer_hw_base_addr_u +{ + struct ipa_hwio_def_ipa_ram_sniffer_hw_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RAM_FILTER_ROUTER_CACHE_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ram_filter_router_cache_base_addr_s +{ + u32 address : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ram_filter_router_cache_base_addr_u +{ + struct ipa_hwio_def_ipa_ram_filter_router_cache_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RAM_INGRESS_POLICER_DB_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ram_ingress_policer_db_base_addr_s +{ + u32 address : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ram_ingress_policer_db_base_addr_u +{ + struct ipa_hwio_def_ipa_ram_ingress_policer_db_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RAM_EGRESS_SHAPING_PROD_DB_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ram_egress_shaping_prod_db_base_addr_s +{ + u32 address : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ram_egress_shaping_prod_db_base_addr_u +{ + struct ipa_hwio_def_ipa_ram_egress_shaping_prod_db_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RAM_EGRESS_SHAPING_TC_DB_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ram_egress_shaping_tc_db_base_addr_s +{ + u32 address : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ram_egress_shaping_tc_db_base_addr_u +{ + struct ipa_hwio_def_ipa_ram_egress_shaping_tc_db_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_SPARE_REG_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_spare_reg_1_s +{ + u32 spare_bits : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_spare_reg_1_u +{ + struct ipa_hwio_def_ipa_spare_reg_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_HPS_UC2SEQ_PUSH +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_hps_uc2seq_push_s +{ + u32 src_pipe : 8; + u32 src_flags : 2; + u32 src_id : 8; + u32 ctx_id : 4; + u32 reserved0 : 8; + u32 virt_opcode : 1; + u32 type : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_hps_uc2seq_push_u +{ + struct ipa_hwio_def_ipa_hps_uc2seq_push_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_HPS_UC2SEQ_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_hps_uc2seq_status_s +{ + u32 fill_level : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_hps_uc2seq_status_u +{ + struct ipa_hwio_def_ipa_hps_uc2seq_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_HPS_SEQ2UC_RD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_hps_seq2uc_rd_s +{ + u32 src_pipe : 8; + u32 src_flags : 2; + u32 src_id : 8; + u32 ctx_id : 4; + u32 reserved0 : 9; + u32 type : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_hps_seq2uc_rd_u +{ + struct ipa_hwio_def_ipa_hps_seq2uc_rd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_HPS_SEQ2UC_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_hps_seq2uc_status_s +{ + u32 fill_level : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_hps_seq2uc_status_u +{ + struct ipa_hwio_def_ipa_hps_seq2uc_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_HPS_SEQ2UC_CMD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_hps_seq2uc_cmd_s +{ + u32 pop : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_hps_seq2uc_cmd_u +{ + struct ipa_hwio_def_ipa_hps_seq2uc_cmd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DPS_UC2SEQ_PUSH +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_dps_uc2seq_push_s +{ + u32 src_pipe : 8; + u32 src_flags : 2; + u32 src_id : 8; + u32 ctx_id : 4; + u32 dest_pipe : 8; + u32 reserved0 : 1; + u32 type : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_dps_uc2seq_push_u +{ + struct ipa_hwio_def_ipa_dps_uc2seq_push_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DPS_UC2SEQ_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_dps_uc2seq_status_s +{ + u32 fill_level : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_dps_uc2seq_status_u +{ + struct ipa_hwio_def_ipa_dps_uc2seq_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DPS_SEQ2UC_RD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_dps_seq2uc_rd_s +{ + u32 src_pipe : 8; + u32 src_flags : 2; + u32 src_id : 8; + u32 ctx_id : 4; + u32 dest_pipe : 8; + u32 reserved0 : 1; + u32 type : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_dps_seq2uc_rd_u +{ + struct ipa_hwio_def_ipa_dps_seq2uc_rd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DPS_SEQ2UC_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_dps_seq2uc_status_s +{ + u32 fill_level : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_dps_seq2uc_status_u +{ + struct ipa_hwio_def_ipa_dps_seq2uc_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DPS_SEQ2UC_CMD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_dps_seq2uc_cmd_s +{ + u32 pop : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_dps_seq2uc_cmd_u +{ + struct ipa_hwio_def_ipa_dps_seq2uc_cmd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_NTF_TX_CMDQ_CMD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ntf_tx_cmdq_cmd_s +{ + u32 write_cmd : 1; + u32 pop_cmd : 1; + u32 rd_req : 1; + u32 reserved0 : 1; + u32 cmd_client : 8; + u32 reserved1 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ntf_tx_cmdq_cmd_u +{ + struct ipa_hwio_def_ipa_ntf_tx_cmdq_cmd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_NTF_TX_CMDQ_DATA_WR_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ntf_tx_cmdq_data_wr_0_s +{ + u32 cmdq_ctx_id_f : 4; + u32 cmdq_src_id_f : 8; + u32 cmdq_src_pipe_f : 8; + u32 cmdq_opcode_f : 2; + u32 cmdq_type_f : 1; + u32 cmdq_virt_cod_f : 1; + u32 seg_valid_f : 1; + u32 seg_ctx_id_f : 2; + u32 reserved0 : 5; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ntf_tx_cmdq_data_wr_0_u +{ + struct ipa_hwio_def_ipa_ntf_tx_cmdq_data_wr_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_NTF_TX_CMDQ_DATA_RD_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ntf_tx_cmdq_data_rd_0_s +{ + u32 cmdq_ctx_id_f : 4; + u32 cmdq_src_id_f : 8; + u32 cmdq_src_pipe_f : 8; + u32 cmdq_opcode_f : 2; + u32 cmdq_type_f : 1; + u32 cmdq_virt_cod_f : 1; + u32 seg_valid_f : 1; + u32 seg_ctx_id_f : 2; + u32 reserved0 : 5; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ntf_tx_cmdq_data_rd_0_u +{ + struct ipa_hwio_def_ipa_ntf_tx_cmdq_data_rd_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_NTF_TX_CMDQ_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ntf_tx_cmdq_status_s +{ + u32 status : 1; + u32 cmdq_full : 1; + u32 cmdq_depth : 7; + u32 reserved0 : 23; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ntf_tx_cmdq_status_u +{ + struct ipa_hwio_def_ipa_ntf_tx_cmdq_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_NTF_TX_SNP +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ntf_tx_snp_s +{ + u32 snp_last : 1; + u32 snp_write : 1; + u32 snp_valid : 1; + u32 snp_next_is_valid : 1; + u32 snp_next : 8; + u32 snp_head : 8; + u32 snp_addr : 8; + u32 reserved0 : 4; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ntf_tx_snp_u +{ + struct ipa_hwio_def_ipa_ntf_tx_snp_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_NTF_TX_CMDQ_COUNT +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ntf_tx_cmdq_count_s +{ + u32 fifo_count : 7; + u32 reserved0 : 25; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ntf_tx_cmdq_count_u +{ + struct ipa_hwio_def_ipa_ntf_tx_cmdq_count_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_PROD_ACKMNGR_CMDQ_CMD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_cmd_s +{ + u32 write_cmd : 1; + u32 pop_cmd : 1; + u32 cmd_client : 8; + u32 rd_req : 1; + u32 reserved0 : 21; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_prod_ackmngr_cmdq_cmd_u +{ + struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_cmd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_PROD_ACKMNGR_CMDQ_DATA_RD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_data_rd_s +{ + u32 cmdq_src_id : 8; + u32 cmdq_length : 16; + u32 cmdq_origin : 1; + u32 cmdq_sent : 1; + u32 cmdq_src_id_valid : 1; + u32 cmdq_userdata : 5; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_prod_ackmngr_cmdq_data_rd_u +{ + struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_data_rd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_PROD_ACKMNGR_CMDQ_DATA_RD_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_data_rd_1_s +{ + u32 cmdq_fnr_aggr_fc : 1; + u32 cmdq_egress : 6; + u32 reserved0 : 25; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_prod_ackmngr_cmdq_data_rd_1_u +{ + struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_data_rd_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_status_empty_n_s +{ + u32 cmdq_empty : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_prod_ackmngr_cmdq_status_empty_n_u +{ + struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_status_empty_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_PROD_ACKMNGR_CMDQ_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_status_s +{ + u32 status : 1; + u32 cmdq_full : 1; + u32 cmdq_depth : 7; + u32 reserved0 : 23; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_prod_ackmngr_cmdq_status_u +{ + struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_PROD_ACKMNGR_CMDQ_COUNT +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_count_s +{ + u32 fifo_count : 7; + u32 reserved0 : 25; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_prod_ackmngr_cmdq_count_u +{ + struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_count_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ACKMNGR_SW_ACCESS_ACKINJ_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ackmngr_sw_access_ackinj_cfg_s +{ + u32 reserved0 : 5; + u32 ackinj_src_id_valid : 1; + u32 ackinj_origin : 1; + u32 ackinj_sent : 1; + u32 ackinj_src_id : 8; + u32 ackinj_length : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ackmngr_sw_access_ackinj_cfg_u +{ + struct ipa_hwio_def_ipa_ackmngr_sw_access_ackinj_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ACKMNGR_SW_ACCESS_ACKINJ_PIPE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ackmngr_sw_access_ackinj_pipe_s +{ + u32 cons_ackinj_src_pipe : 8; + u32 prod_ackinj_src_pipe : 8; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ackmngr_sw_access_ackinj_pipe_u +{ + struct ipa_hwio_def_ipa_ackmngr_sw_access_ackinj_pipe_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ACKMNGR_SW_ACCESS_ACKUPD_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ackmngr_sw_access_ackupd_cfg_s +{ + u32 ackupd_src_pipe : 8; + u32 ackupd_src_id : 8; + u32 ackupd_error : 1; + u32 reserved0 : 15; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ackmngr_sw_access_ackupd_cfg_u +{ + struct ipa_hwio_def_ipa_ackmngr_sw_access_ackupd_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ACKMNGR_SW_ACCESS_CMD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ackmngr_sw_access_cmd_s +{ + u32 ackinj_valid : 1; + u32 ackupd_valid : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ackmngr_sw_access_cmd_u +{ + struct ipa_hwio_def_ipa_ackmngr_sw_access_cmd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ACKMNGR_SW_ACCESS_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ackmngr_sw_access_status_s +{ + u32 ackinj_ready : 1; + u32 ackupd_ready : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ackmngr_sw_access_status_u +{ + struct ipa_hwio_def_ipa_ackmngr_sw_access_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_prod_ackmngr_sw_access_ackinj_cfg_s +{ + u32 reserved0 : 5; + u32 ackinj_src_id_valid : 1; + u32 ackinj_origin : 1; + u32 ackinj_sent : 1; + u32 ackinj_src_id : 8; + u32 ackinj_length : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_prod_ackmngr_sw_access_ackinj_cfg_u +{ + struct ipa_hwio_def_ipa_prod_ackmngr_sw_access_ackinj_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_PROD_ACKMNGR_SW_ACCESS_ACKUPD_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_prod_ackmngr_sw_access_ackupd_cfg_s +{ + u32 ackupd_src_pipe : 8; + u32 ackupd_src_id : 8; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_prod_ackmngr_sw_access_ackupd_cfg_u +{ + struct ipa_hwio_def_ipa_prod_ackmngr_sw_access_ackupd_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_PROD_ACKMNGR_SW_ACCESS_CMD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_prod_ackmngr_sw_access_cmd_s +{ + u32 ackinj_valid : 1; + u32 ackupd_valid : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_prod_ackmngr_sw_access_cmd_u +{ + struct ipa_hwio_def_ipa_prod_ackmngr_sw_access_cmd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_PROD_ACKMNGR_SW_ACCESS_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_prod_ackmngr_sw_access_status_s +{ + u32 ackinj_ready : 1; + u32 ackupd_ready : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_prod_ackmngr_sw_access_status_u +{ + struct ipa_hwio_def_ipa_prod_ackmngr_sw_access_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_prod_ackmngr_sw_access_ackinj_cfg1_s +{ + u32 ackinj_userdata : 6; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_prod_ackmngr_sw_access_ackinj_cfg1_u +{ + struct ipa_hwio_def_ipa_prod_ackmngr_sw_access_ackinj_cfg1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_NTF_TX_CMDQ_RELEASE_WR_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ntf_tx_cmdq_release_wr_n_s +{ + u32 release_wr_cmd : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ntf_tx_cmdq_release_wr_n_u +{ + struct ipa_hwio_def_ipa_ntf_tx_cmdq_release_wr_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_NTF_TX_CMDQ_RELEASE_RD_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ntf_tx_cmdq_release_rd_n_s +{ + u32 release_rd_cmd : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ntf_tx_cmdq_release_rd_n_u +{ + struct ipa_hwio_def_ipa_ntf_tx_cmdq_release_rd_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_NTF_TX_CMDQ_CFG_WR_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ntf_tx_cmdq_cfg_wr_n_s +{ + u32 block_wr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ntf_tx_cmdq_cfg_wr_n_u +{ + struct ipa_hwio_def_ipa_ntf_tx_cmdq_cfg_wr_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_NTF_TX_CMDQ_CFG_RD_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ntf_tx_cmdq_cfg_rd_n_s +{ + u32 block_rd : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ntf_tx_cmdq_cfg_rd_n_u +{ + struct ipa_hwio_def_ipa_ntf_tx_cmdq_cfg_rd_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_NTF_TX_CMDQ_STATUS_EMPTY_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ntf_tx_cmdq_status_empty_n_s +{ + u32 cmdq_empty : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ntf_tx_cmdq_status_empty_n_u +{ + struct ipa_hwio_def_ipa_ntf_tx_cmdq_status_empty_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_base_addr_s +{ + u32 zero : 21; + u32 base : 11; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_base_addr_u +{ + struct ipa_hwio_def_ipa_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_BASE_ADDR_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_base_addr_msb_s +{ + u32 base_msb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_base_addr_msb_u +{ + struct ipa_hwio_def_ipa_base_addr_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ENDP_GSI_CFG1_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_endp_gsi_cfg1_n_s +{ + u32 reserved0 : 16; + u32 endp_en : 1; + u32 reserved1 : 14; + u32 init_endp : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_endp_gsi_cfg1_n_u +{ + struct ipa_hwio_def_ipa_endp_gsi_cfg1_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ENDP_GSI_CFG_TLV_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_endp_gsi_cfg_tlv_n_s +{ + u32 fifo_base_addr : 16; + u32 fifo_size : 8; + u32 reserved0 : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_endp_gsi_cfg_tlv_n_u +{ + struct ipa_hwio_def_ipa_endp_gsi_cfg_tlv_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ENDP_GSI_CFG_AOS_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_endp_gsi_cfg_aos_n_s +{ + u32 fifo_base_addr : 16; + u32 fifo_size : 8; + u32 reserved0 : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_endp_gsi_cfg_aos_n_u +{ + struct ipa_hwio_def_ipa_endp_gsi_cfg_aos_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_COAL_VP_AOS_FIFO_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_coal_vp_aos_fifo_n_s +{ + u32 fifo_base_addr : 16; + u32 fifo_size : 8; + u32 reserved0 : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_coal_vp_aos_fifo_n_u +{ + struct ipa_hwio_def_ipa_coal_vp_aos_fifo_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_QMB_DEBUG_CTRL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_qmb_debug_ctrl_s +{ + u32 ram_slaveway_access_protection_disable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_qmb_debug_ctrl_u +{ + struct ipa_hwio_def_ipa_qmb_debug_ctrl_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_CTXH_CTRL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ctxh_ctrl_s +{ + u32 ctxh_lock_id : 4; + u32 reserved0 : 25; + u32 ctxh_wr_block_on_noc_err : 1; + u32 ctxh_lock_active : 1; + u32 ctxh_lock : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ctxh_ctrl_u +{ + struct ipa_hwio_def_ipa_ctxh_ctrl_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_CTX_ID_m_CTX_NUM_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ctx_id_m_ctx_num_n_s +{ + u32 ipa_ctxh_data : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ctx_id_m_ctx_num_n_u +{ + struct ipa_hwio_def_ipa_ctx_id_m_ctx_num_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_SEG_CTX_ID_m_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_seg_ctx_id_m_0_s +{ + u32 dma_task_eof : 1; + u32 filter_aggr_force_close : 1; + u32 last : 1; + u32 router_aggr_force_close : 1; + u32 open_frame : 1; + u32 reserved0 : 3; + u32 trnseq_len_ext : 8; + u32 data_sector_valid_length : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_seg_ctx_id_m_0_u +{ + struct ipa_hwio_def_ipa_seg_ctx_id_m_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_SEG_CTX_ID_m_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_seg_ctx_id_m_1_s +{ + u32 l4_pseudo_hdr_checksum : 16; + u32 revised_packet_length : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_seg_ctx_id_m_1_u +{ + struct ipa_hwio_def_ipa_seg_ctx_id_m_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_SEG_CTX_ID_m_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_seg_ctx_id_m_2_s +{ + u32 trnseq_0_opcode : 3; + u32 trnseq_0_length : 10; + u32 trnseq_0_offset : 10; + u32 reserved0 : 9; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_seg_ctx_id_m_2_u +{ + struct ipa_hwio_def_ipa_seg_ctx_id_m_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_SEG_CTX_ID_m_3 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_seg_ctx_id_m_3_s +{ + u32 trnseq_1_opcode : 3; + u32 trnseq_1_length : 10; + u32 trnseq_1_offset : 10; + u32 reserved0 : 9; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_seg_ctx_id_m_3_u +{ + struct ipa_hwio_def_ipa_seg_ctx_id_m_3_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_SEG_CTX_ID_m_4 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_seg_ctx_id_m_4_s +{ + u32 trnseq_2_opcode : 3; + u32 trnseq_2_length : 10; + u32 trnseq_2_offset : 10; + u32 reserved0 : 9; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_seg_ctx_id_m_4_u +{ + struct ipa_hwio_def_ipa_seg_ctx_id_m_4_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_SEG_CTX_ID_m_5 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_seg_ctx_id_m_5_s +{ + u32 trnseq_3_opcode : 3; + u32 trnseq_3_length : 10; + u32 trnseq_3_offset : 10; + u32 reserved0 : 9; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_seg_ctx_id_m_5_u +{ + struct ipa_hwio_def_ipa_seg_ctx_id_m_5_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_SEG_CTX_ID_m_6 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_seg_ctx_id_m_6_s +{ + u32 trnseq_4_opcode : 3; + u32 trnseq_4_length : 10; + u32 trnseq_4_offset : 10; + u32 reserved0 : 9; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_seg_ctx_id_m_6_u +{ + struct ipa_hwio_def_ipa_seg_ctx_id_m_6_s def; + u32 value; +}; + +/*---------------------------------------------------------------------------- + * MODULE: IPA_CFG + *--------------------------------------------------------------------------*/ + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_FLAVOR_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_flavor_0_s +{ + u32 ipa_pipes : 8; + u32 ipa_cons_pipes : 8; + u32 ipa_prod_pipes : 8; + u32 ipa_prod_lowest : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_flavor_0_u +{ + struct ipa_hwio_def_ipa_flavor_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_FLAVOR_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_flavor_1_s +{ + u32 ctx_n : 6; + u32 reserved0 : 2; + u32 mbim_deagg_en : 1; + u32 ucp_en : 1; + u32 d_dcph_2_en : 1; + u32 d_dcph_en : 1; + u32 h_dcph_en : 1; + u32 reserved1 : 1; + u32 filter_router_cache_gen : 1; + u32 nat_acl_en : 1; + u32 vmidmt_en : 1; + u32 uc_en : 1; + u32 cpr_en : 1; + u32 cons_dpl_en : 1; + u32 qmb0_slaveway_en : 1; + u32 qmb1_slaveway_en : 1; + u32 qmb1_en : 1; + u32 dual_tx_en : 1; + u32 rx_uc_handler_en : 1; + u32 gsi_slaveway_en : 1; + u32 pcie_path_en : 1; + u32 d_dcph_engine_num : 2; + u32 reserved2 : 3; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_flavor_1_u +{ + struct ipa_hwio_def_ipa_flavor_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_FLAVOR_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_flavor_2_s +{ + u32 qmb0_outst_wr : 6; + u32 reserved0 : 2; + u32 qmb0_outst_rd : 6; + u32 reserved1 : 2; + u32 qmb1_outst_wr : 6; + u32 reserved2 : 2; + u32 qmb1_outst_rd : 6; + u32 reserved3 : 2; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_flavor_2_u +{ + struct ipa_hwio_def_ipa_flavor_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_FLAVOR_3 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_flavor_3_s +{ + u32 rsrc_grp_src_num_wout_uc : 4; + u32 rsrc_grp_src_num_uc : 4; + u32 rsrc_grp_dst_num_wo_uc_n_drbip : 4; + u32 rsrc_grp_dst_num_uc : 4; + u32 pkt_ctx_size : 8; + u32 rsrc_grp_dst_num_drbip : 4; + u32 reserved0 : 4; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_flavor_3_u +{ + struct ipa_hwio_def_ipa_flavor_3_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_FLAVOR_4 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_flavor_4_s +{ + u32 generic_agg_pipes : 8; + u32 generic_deagg_pipes : 8; + u32 bearer_init_ctx_num : 4; + u32 mbim_agg_pipes : 4; + u32 reserved0 : 4; + u32 frag_tables_num : 2; + u32 reserved1 : 2; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_flavor_4_u +{ + struct ipa_hwio_def_ipa_flavor_4_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_FLAVOR_5 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_flavor_5_s +{ + u32 consumer_ack_mngr_db_depth : 6; + u32 reserved0 : 2; + u32 producer_ack_mngr_db_depth : 6; + u32 reserved1 : 2; + u32 ipa_num_ees : 4; + u32 gsi_num_ees : 4; + u32 rx_hps_cmdq_q_depth : 6; + u32 reserved2 : 2; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_flavor_5_u +{ + struct ipa_hwio_def_ipa_flavor_5_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_FLAVOR_6 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_flavor_6_s +{ + u32 hps_dmar_num : 4; + u32 dps_dmar_num : 4; + u32 data_descriptor_lists : 6; + u32 reserved0 : 2; + u32 data_descriptor_buffers : 8; + u32 data_sectors : 6; + u32 reserved1 : 2; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_flavor_6_u +{ + struct ipa_hwio_def_ipa_flavor_6_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_FLAVOR_7 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_flavor_7_s +{ + u32 tlv_entry_num : 10; + u32 reserved0 : 6; + u32 aos_entry_num : 10; + u32 coal_vp_num : 5; + u32 reserved1 : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_flavor_7_u +{ + struct ipa_hwio_def_ipa_flavor_7_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_FLAVOR_8 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_flavor_8_s +{ + u32 multi_drbip_dmar_engine_num : 4; + u32 multi_drbip_dcph_engine_num : 4; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_flavor_8_u +{ + struct ipa_hwio_def_ipa_flavor_8_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_FLAVOR_9 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_flavor_9_s +{ + u32 ipa_max_supported_tsp_ingress_tcs : 8; + u32 ipa_max_supported_tsp_egress_tcs : 8; + u32 ipa_max_supported_tsp_producers : 8; + u32 reserved0 : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_flavor_9_u +{ + struct ipa_hwio_def_ipa_flavor_9_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_FLAVOR_10 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_flavor_10_s +{ + u32 ipa_max_supported_qmngr_blocks : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_flavor_10_u +{ + struct ipa_hwio_def_ipa_flavor_10_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_COMP_HW_VERSION +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_comp_hw_version_s +{ + u32 step : 16; + u32 minor : 12; + u32 major : 4; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_comp_hw_version_u +{ + struct ipa_hwio_def_ipa_comp_hw_version_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_VERSION +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_version_s +{ + u32 ipa_r_rev : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_version_u +{ + struct ipa_hwio_def_ipa_version_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_COMP_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_comp_cfg_s +{ + u32 ram_arb_priority_client_samp_fix_disable : 1; + u32 gsi_snoc_bypass_dis : 1; + u32 gen_qmb_0_snoc_bypass_dis : 1; + u32 gen_qmb_1_snoc_bypass_dis : 1; + u32 reserved0 : 1; + u32 ipa_qmb_select_by_address_cons_en : 1; + u32 ipa_qmb_select_by_address_prod_en : 1; + u32 gsi_multi_inorder_rd_dis : 1; + u32 gsi_multi_inorder_wr_dis : 1; + u32 gen_qmb_0_multi_inorder_rd_dis : 1; + u32 gen_qmb_1_multi_inorder_rd_dis : 1; + u32 gen_qmb_0_multi_inorder_wr_dis : 1; + u32 gen_qmb_1_multi_inorder_wr_dis : 1; + u32 gen_qmb_0_snoc_cnoc_loop_protection_disable : 1; + u32 gsi_snoc_cnoc_loop_protection_disable : 1; + u32 gsi_multi_axi_masters_dis : 1; + u32 ipa_qmb_select_by_address_global_en : 1; + u32 reserved1 : 2; + u32 qmb_ram_rd_cache_disable : 1; + u32 genqmb_aooowr : 1; + u32 gsi_if_out_of_buf_stop_reset_mask_enable : 1; + u32 ipa_atomic_fetcher_arb_lock_dis : 6; + u32 reserved2 : 2; + u32 gen_qmb_1_dynamic_asize : 1; + u32 gen_qmb_0_dynamic_asize : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_comp_cfg_u +{ + struct ipa_hwio_def_ipa_comp_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_CLKON_CFG_SPECIAL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_clkon_cfg_special_s +{ + u32 cgc_open_tpdm_cmb : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_clkon_cfg_special_u +{ + struct ipa_hwio_def_ipa_clkon_cfg_special_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_CLKON_CFG_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_clkon_cfg_1_s +{ + u32 cgc_open_ipa_core_clk_phase : 1; + u32 cgc_open_ipa_xpu_wrapper : 1; + u32 cgc_open_ipa_tsp : 1; + u32 cgc_open_prod_dpl_fifo : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_clkon_cfg_1_u +{ + struct ipa_hwio_def_ipa_clkon_cfg_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_CLKON_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_clkon_cfg_s +{ + u32 cgc_open_rx : 1; + u32 cgc_open_proc : 1; + u32 cgc_open_tx_wrapper : 1; + u32 cgc_open_misc : 1; + u32 cgc_open_ram_arb : 1; + u32 cgc_open_ftch_hps : 1; + u32 cgc_open_ftch_dps : 1; + u32 cgc_open_hps : 1; + u32 cgc_open_dps : 1; + u32 cgc_open_rx_hps_cmdqs : 1; + u32 cgc_open_hps_dps_cmdqs : 1; + u32 cgc_open_dps_tx_cmdqs : 1; + u32 cgc_open_rsrc_mngr : 1; + u32 cgc_open_ctx_handler : 1; + u32 cgc_open_ack_mngr : 1; + u32 cgc_open_d_dcph : 1; + u32 cgc_open_h_dcph : 1; + u32 reserved0 : 1; + u32 cgc_open_ntf_tx_cmdqs : 1; + u32 cgc_open_tx_0 : 1; + u32 cgc_open_tx_1 : 1; + u32 cgc_open_fnr : 1; + u32 cgc_open_qsb2axi_cmdq_l : 1; + u32 cgc_open_aggr_wrapper : 1; + u32 cgc_open_ram_slaveway : 1; + u32 cgc_open_qmb : 1; + u32 cgc_open_weight_arb : 1; + u32 cgc_open_gsi_if : 1; + u32 cgc_open_global : 1; + u32 cgc_open_global_2x_clk : 1; + u32 cgc_open_cons_dpl_fifo : 1; + u32 cgc_open_drbip : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_clkon_cfg_u +{ + struct ipa_hwio_def_ipa_clkon_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ROUTE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_route_s +{ + u32 route_def_pipe : 8; + u32 route_frag_def_pipe : 8; + u32 route_def_hdr_ofst : 10; + u32 route_def_hdr_table : 1; + u32 route_def_retain_hdr : 1; + u32 route_dis : 1; + u32 reserved0 : 3; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_route_u +{ + struct ipa_hwio_def_ipa_route_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_MASTER_PRIORITY +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_master_priority_s +{ + u32 qmb_0_rd : 2; + u32 qmb_1_rd : 2; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_master_priority_u +{ + struct ipa_hwio_def_ipa_master_priority_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_SHARED_MEM_SIZE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_shared_mem_size_s +{ + u32 shared_mem_size : 16; + u32 shared_mem_baddr : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_shared_mem_size_u +{ + struct ipa_hwio_def_ipa_shared_mem_size_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_NAT_TIMER +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_nat_timer_s +{ + u32 nat_timer : 24; + u32 reserved0 : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_nat_timer_u +{ + struct ipa_hwio_def_ipa_nat_timer_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_TAG_TIMER +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_tag_timer_s +{ + u32 tag_timer : 24; + u32 reserved0 : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_tag_timer_u +{ + struct ipa_hwio_def_ipa_tag_timer_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_FRAG_RULES_CLR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_frag_rules_clr_s +{ + u32 clr : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_frag_rules_clr_u +{ + struct ipa_hwio_def_ipa_frag_rules_clr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_PROC_IPH_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_proc_iph_cfg_s +{ + u32 reserved0 : 8; + u32 iph_pkt_parser_protocol_stop_enable : 1; + u32 iph_pkt_parser_protocol_stop_hop : 1; + u32 iph_pkt_parser_protocol_stop_dest : 1; + u32 iph_pkt_parser_ihl_to_2nd_frag_en : 1; + u32 reserved1 : 4; + u32 iph_pkt_parser_protocol_stop_value : 8; + u32 d_dcph_multi_engine_disable : 1; + u32 reserved2 : 7; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_proc_iph_cfg_u +{ + struct ipa_hwio_def_ipa_proc_iph_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_QSB_MAX_WRITES +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_qsb_max_writes_s +{ + u32 gen_qmb_0_max_writes : 4; + u32 gen_qmb_1_max_writes : 4; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_qsb_max_writes_u +{ + struct ipa_hwio_def_ipa_qsb_max_writes_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_QSB_MAX_READS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_qsb_max_reads_s +{ + u32 gen_qmb_0_max_reads : 4; + u32 gen_qmb_1_max_reads : 4; + u32 reserved0 : 8; + u32 gen_qmb_0_max_read_beats : 8; + u32 gen_qmb_1_max_read_beats : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_qsb_max_reads_u +{ + struct ipa_hwio_def_ipa_qsb_max_reads_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_QSB_OUTSTANDING_COUNTER +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_qsb_outstanding_counter_s +{ + u32 gen_qmb_0_reads_cnt : 5; + u32 reserved0 : 3; + u32 gen_qmb_1_reads_cnt : 5; + u32 reserved1 : 3; + u32 gen_qmb_0_writes_cnt : 5; + u32 reserved2 : 3; + u32 gen_qmb_1_writes_cnt : 5; + u32 reserved3 : 3; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_qsb_outstanding_counter_u +{ + struct ipa_hwio_def_ipa_qsb_outstanding_counter_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_QSB_OUTSTANDING_BEATS_COUNTER +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_qsb_outstanding_beats_counter_s +{ + u32 gen_qmb_0_read_beats_cnt : 8; + u32 gen_qmb_1_read_beats_cnt : 8; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_qsb_outstanding_beats_counter_u +{ + struct ipa_hwio_def_ipa_qsb_outstanding_beats_counter_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DPL_TIMER_LSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_dpl_timer_lsb_s +{ + u32 tod_lsb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_dpl_timer_lsb_u +{ + struct ipa_hwio_def_ipa_dpl_timer_lsb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DPL_TIMER_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_dpl_timer_msb_s +{ + u32 tod_msb : 20; + u32 reserved0 : 7; + u32 gran_sel : 4; + u32 timer_en : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_dpl_timer_msb_u +{ + struct ipa_hwio_def_ipa_dpl_timer_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DPL_TIMER_CTL_STS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_dpl_timer_ctl_sts_s +{ + u32 legacy_timer : 1; + u32 reserved0 : 3; + u32 tod_valid : 1; + u32 reserved1 : 27; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_dpl_timer_ctl_sts_u +{ + struct ipa_hwio_def_ipa_dpl_timer_ctl_sts_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_RX_ACTIVE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_rx_active_n_s +{ + u32 endpoints : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_rx_active_n_u +{ + struct ipa_hwio_def_ipa_state_rx_active_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_TX_WRAPPER +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_tx_wrapper_s +{ + u32 tx_idle : 1; + u32 reserved0 : 1; + u32 ipa_prod_ackmngr_db_empty : 1; + u32 ipa_prod_ackmngr_state_idle : 1; + u32 ipa_prod_bresp_empty : 1; + u32 reserved1 : 1; + u32 ipa_mbim_pkt_fsm_idle : 2; + u32 mbim_direct_dma : 2; + u32 reserved2 : 4; + u32 nlo_direct_dma : 2; + u32 coal_direct_dma : 2; + u32 reserved3 : 14; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_tx_wrapper_u +{ + struct ipa_hwio_def_ipa_state_tx_wrapper_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_TX +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_tx_s +{ + u32 stage_arb_busy : 1; + u32 stage_packet_processsor_busy : 1; + u32 stage_address_resolution_busy : 1; + u32 stage_packet_constructor_0_busy : 1; + u32 stage_packet_constructor_1_busy : 1; + u32 stage_transmission_0_busy : 1; + u32 stage_transmission_1_busy : 1; + u32 stage_checksum_handler_0_busy : 1; + u32 stage_checksum_handler_1_busy : 1; + u32 packet_drop_counter_busy : 1; + u32 suspend_handler_busy : 1; + u32 drop_handler_busy : 1; + u32 packet_release_handler_busy : 1; + u32 holb_mask_valid : 1; + u32 dmaw_0_busy : 1; + u32 dmaw_1_busy : 1; + u32 stage_arb_dest_pipe : 8; + u32 stage_arb_ctx_id : 4; + u32 stage_arb_dma_type : 4; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_tx_u +{ + struct ipa_hwio_def_ipa_state_tx_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_TX_HOLB_MASK_DPS_TX_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_tx_holb_mask_dps_tx_0_s +{ + u32 producer_mask_0_31 : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_tx_holb_mask_dps_tx_0_u +{ + struct ipa_hwio_def_ipa_state_tx_holb_mask_dps_tx_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_TX_HOLB_MASK_NTF_TX_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_tx_holb_mask_ntf_tx_0_s +{ + u32 producer_mask_0_31 : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_tx_holb_mask_ntf_tx_0_u +{ + struct ipa_hwio_def_ipa_state_tx_holb_mask_ntf_tx_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_TX_HOLB_MASK_NTF_TX_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_tx_holb_mask_ntf_tx_1_s +{ + u32 producer_mask_32_64 : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_tx_holb_mask_ntf_tx_1_u +{ + struct ipa_hwio_def_ipa_state_tx_holb_mask_ntf_tx_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_FETCHER +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_fetcher_s +{ + u32 ipa_hps_ftch_state_idle : 1; + u32 ipa_hps_ftch_alloc_state_idle : 1; + u32 ipa_hps_ftch_pkt_state_idle : 1; + u32 ipa_hps_ftch_imm_state_idle : 1; + u32 ipa_hps_ftch_cmplt_state_idle : 1; + u32 ipa_hps_dmar_state_idle : 7; + u32 ipa_hps_dmar_slot_state_idle : 7; + u32 ipa_hps_imm_cmd_exec_state_idle : 1; + u32 reserved0 : 12; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_fetcher_u +{ + struct ipa_hwio_def_ipa_state_fetcher_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_FETCHER_MASK_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_fetcher_mask_0_s +{ + u32 mask_queue_dmar_uses_queue : 8; + u32 mask_queue_imm_exec : 8; + u32 mask_queue_no_resources_context : 8; + u32 mask_queue_no_resources_hps_dmar : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_fetcher_mask_0_u +{ + struct ipa_hwio_def_ipa_state_fetcher_mask_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_DFETCHER +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_dfetcher_s +{ + u32 ipa_dps_ftch_pkt_state_idle : 1; + u32 ipa_dps_ftch_cmplt_state_idle : 1; + u32 reserved0 : 2; + u32 ipa_dps_dmar_state_idle : 7; + u32 reserved1 : 5; + u32 ipa_dps_dmar_slot_state_idle : 7; + u32 reserved2 : 9; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_dfetcher_u +{ + struct ipa_hwio_def_ipa_state_dfetcher_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_ACL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_acl_s +{ + u32 ipa_hps_h_dcph_empty : 1; + u32 ipa_hps_h_dcph_active : 1; + u32 ipa_hps_pkt_parser_empty : 1; + u32 ipa_hps_pkt_parser_active : 1; + u32 ipa_hps_filter_nat_empty : 1; + u32 ipa_hps_filter_nat_active : 1; + u32 ipa_hps_router_empty : 1; + u32 ipa_hps_router_active : 1; + u32 ipa_hps_hdri_empty : 1; + u32 ipa_hps_hdri_active : 1; + u32 ipa_hps_ucp_empty : 1; + u32 ipa_hps_ucp_active : 1; + u32 ipa_hps_enqueuer_empty : 1; + u32 ipa_hps_enqueuer_active : 1; + u32 ipa_dps_d_dcph_empty : 1; + u32 ipa_dps_d_dcph_active : 1; + u32 reserved0 : 2; + u32 ipa_dps_dispatcher_empty : 1; + u32 ipa_dps_dispatcher_active : 1; + u32 ipa_dps_d_dcph_2_empty : 1; + u32 ipa_dps_d_dcph_2_active : 1; + u32 ipa_hps_sequencer_idle : 1; + u32 ipa_dps_sequencer_idle : 1; + u32 ipa_dps_d_dcph_2nd_empty : 1; + u32 ipa_dps_d_dcph_2nd_active : 1; + u32 ipa_hps_coal_master_empty : 1; + u32 ipa_hps_coal_master_active : 1; + u32 ipa_hps_multi_drbip_empty : 1; + u32 ipa_hps_multi_drbip_active : 1; + u32 ipa_hps_empty : 1; + u32 reserved1 : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_acl_u +{ + struct ipa_hwio_def_ipa_state_acl_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_s +{ + u32 rx_wait : 1; + u32 rx_idle : 1; + u32 tx_idle : 1; + u32 ipa_cons_dpl_fifo_idle : 1; + u32 gsi_idle : 1; + u32 ipa_hw_sniffer_idle : 1; + u32 ipa_noc_idle : 1; + u32 aggr_idle : 1; + u32 mbim_aggr_idle : 1; + u32 ipa_rsrc_mngr_db_empty : 1; + u32 ipa_rsrc_state_idle : 1; + u32 ipa_ackmngr_db_empty : 1; + u32 ipa_ackmngr_state_idle : 1; + u32 ipa_tx_ackq_full : 1; + u32 ipa_prod_ackmngr_db_empty : 1; + u32 ipa_prod_ackmngr_state_idle : 1; + u32 ipa_prod_bresp_idle : 1; + u32 ipa_full_idle : 1; + u32 ipa_ntf_tx_empty : 1; + u32 ipa_prod_dpl_fifo_idle : 1; + u32 ipa_uc_ackq_empty : 1; + u32 ipa_rx_ackq_empty : 1; + u32 ipa_tx_commander_cmdq_empty : 1; + u32 ipa_rx_splt_cmdq_empty : 5; + u32 ipa_rx_hps_empty : 1; + u32 ipa_hps_dps_empty : 1; + u32 ipa_dps_tx_empty : 1; + u32 ipa_uc_rx_hnd_cmdq_empty : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_u +{ + struct ipa_hwio_def_ipa_state_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_GSI_AOS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_gsi_aos_s +{ + u32 ipa_gsi_aos_fsm_idle : 1; + u32 ipa_gsi_aos_nlo_fsm_idle : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_gsi_aos_u +{ + struct ipa_hwio_def_ipa_state_gsi_aos_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_COAL_SLAVE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_coal_slave_s +{ + u32 coal_slave_open_frame : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_coal_slave_u +{ + struct ipa_hwio_def_ipa_state_coal_slave_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_GSI_IF +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_gsi_if_s +{ + u32 ipa_gsi_prod_fsm_tx_0 : 4; + u32 ipa_gsi_prod_fsm_tx_1 : 4; + u32 ipa_gsi_toggle_fsm_idle : 1; + u32 reserved0 : 7; + u32 ipa_gsi_skip_fsm : 2; + u32 reserved1 : 14; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_gsi_if_u +{ + struct ipa_hwio_def_ipa_state_gsi_if_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_RQOS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_rqos_s +{ + u32 ipa_rqos_nas_idle : 1; + u32 ipa_rqos_as_idle : 1; + u32 ipa_rqos_sw_idle : 1; + u32 ipa_rqos_fifo_empty : 1; + u32 ipa_rqos_fifo_pop_idle : 1; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_rqos_u +{ + struct ipa_hwio_def_ipa_state_rqos_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_GSI_IF_CONS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_gsi_if_cons_s +{ + u32 state_idle : 1; + u32 cache_vld : 7; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_gsi_if_cons_u +{ + struct ipa_hwio_def_ipa_state_gsi_if_cons_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_FETCHER_MASK_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_fetcher_mask_1_s +{ + u32 mask_queue_no_resources_ack_entry : 8; + u32 mask_queue_arb_lock : 8; + u32 mask_queue_step_mode : 8; + u32 mask_queue_no_space_dpl_fifo : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_fetcher_mask_1_u +{ + struct ipa_hwio_def_ipa_state_fetcher_mask_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_FETCHER_MASK_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_fetcher_mask_2_s +{ + u32 mask_queue_drbip_no_data_sectors : 8; + u32 mask_queue_drbip_pkt_exceed_max_size : 8; + u32 mask_queue_no_space_rqos_fifo : 8; + u32 reserved0 : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_fetcher_mask_2_u +{ + struct ipa_hwio_def_ipa_state_fetcher_mask_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_CONS_DPL_FIFO +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_cons_dpl_fifo_s +{ + u32 pop_fsm_state : 3; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_cons_dpl_fifo_u +{ + struct ipa_hwio_def_ipa_state_cons_dpl_fifo_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_COAL_MASTER +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_coal_master_s +{ + u32 main_fsm_state : 4; + u32 find_open_fsm_state : 4; + u32 hash_calc_fsm_state : 4; + u32 check_fit_fsm_state : 4; + u32 init_vp_fsm_state : 4; + u32 lru_vp : 6; + u32 reserved0 : 6; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_coal_master_u +{ + struct ipa_hwio_def_ipa_state_coal_master_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_COAL_MASTER_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_coal_master_1_s +{ + u32 init_vp_wr_ctx_line : 6; + u32 init_vp_rd_pkt_line : 6; + u32 init_vp_fsm_state : 4; + u32 check_fit_rd_ctx_line : 6; + u32 check_fit_fsm_state : 4; + u32 arbiter_state : 4; + u32 reserved0 : 2; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_coal_master_1_u +{ + struct ipa_hwio_def_ipa_state_coal_master_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_NLO_AGGR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_nlo_aggr_s +{ + u32 nlo_aggr_state : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_nlo_aggr_u +{ + struct ipa_hwio_def_ipa_state_nlo_aggr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_CTXH +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_ctxh_s +{ + u32 ipa_ctxh_rd_idle : 1; + u32 ipa_ctxh_wr_idle : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_ctxh_u +{ + struct ipa_hwio_def_ipa_state_ctxh_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_UC_QMB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_uc_qmb_s +{ + u32 ctrl_fsm_state_queue_0 : 2; + u32 ot_table_empty_queue_0 : 1; + u32 ot_table_full_queue_0 : 1; + u32 comp_fifo_empty_queue_0 : 1; + u32 comp_fifo_full_queue_0 : 1; + u32 cmd_fifo_empty_queue_0 : 1; + u32 cmd_fifo_full_queue_0 : 1; + u32 queue_0_idle : 1; + u32 reserved0 : 7; + u32 ctrl_fsm_state_queue_1 : 2; + u32 ot_table_empty_queue_1 : 1; + u32 ot_table_full_queue_1 : 1; + u32 comp_fifo_empty_queue_1 : 1; + u32 comp_fifo_full_queue_1 : 1; + u32 cmd_fifo_empty_queue_1 : 1; + u32 cmd_fifo_full_queue_1 : 1; + u32 queue_1_idle : 1; + u32 reserved1 : 7; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_uc_qmb_u +{ + struct ipa_hwio_def_ipa_state_uc_qmb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_DRBIP +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_drbip_s +{ + u32 drbip_dmar_idle : 3; + u32 reserved0 : 5; + u32 drbip_dcph_idle : 1; + u32 reserved1 : 7; + u32 drbip_pkt_idle : 4; + u32 reserved2 : 12; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_drbip_u +{ + struct ipa_hwio_def_ipa_state_drbip_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_TX_HOLB_MASK_DPS_TX_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_tx_holb_mask_dps_tx_1_s +{ + u32 producer_mask_32_64 : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_tx_holb_mask_dps_tx_1_u +{ + struct ipa_hwio_def_ipa_state_tx_holb_mask_dps_tx_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_COAL_MASTER_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_coal_master_2_s +{ + u32 vp_timer_expired : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_coal_master_2_u +{ + struct ipa_hwio_def_ipa_state_coal_master_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_COAL_MASTER_3 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_coal_master_3_s +{ + u32 vp_vld : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_coal_master_3_u +{ + struct ipa_hwio_def_ipa_state_coal_master_3_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_TSP +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_tsp_s +{ + u32 traffic_shaper_idle : 1; + u32 traffic_shaper_fifo_empty : 1; + u32 queue_mngr_idle : 1; + u32 queue_mngr_head_idle : 1; + u32 queue_mngr_shared_idle : 1; + u32 queue_mngr_tail_idle : 1; + u32 queue_mngr_block_ctrl_idle : 1; + u32 reserved0 : 25; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_tsp_u +{ + struct ipa_hwio_def_ipa_state_tsp_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_AGGR_ACTIVE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_aggr_active_n_s +{ + u32 endpoints : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_aggr_active_n_u +{ + struct ipa_hwio_def_ipa_state_aggr_active_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_GSI_TLV_FIFO_EMPTY_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_gsi_tlv_fifo_empty_n_s +{ + u32 pipe_fifo_empty : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_gsi_tlv_fifo_empty_n_u +{ + struct ipa_hwio_def_ipa_state_gsi_tlv_fifo_empty_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_GSI_AOS_FIFO_EMPTY_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_gsi_aos_fifo_empty_n_s +{ + u32 pipe_fifo_empty : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_gsi_aos_fifo_empty_n_u +{ + struct ipa_hwio_def_ipa_state_gsi_aos_fifo_empty_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_DRBIP_DROP_STATE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_drbip_drop_state_n_s +{ + u32 consumer_pipe_drop_state : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_drbip_drop_state_n_u +{ + struct ipa_hwio_def_ipa_state_drbip_drop_state_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_DFETCHER_MASK_0_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_dfetcher_mask_0_n_s +{ + u32 mask_queue_dst_grp_dmar_outstanding : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_dfetcher_mask_0_n_u +{ + struct ipa_hwio_def_ipa_state_dfetcher_mask_0_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_DFETCHER_MASK_1_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_dfetcher_mask_1_n_s +{ + u32 mask_queue_no_resources_data_sectors : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_dfetcher_mask_1_n_u +{ + struct ipa_hwio_def_ipa_state_dfetcher_mask_1_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_DFETCHER_MASK_2_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_dfetcher_mask_2_n_s +{ + u32 mask_queue_no_resources_dps_dmar : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_dfetcher_mask_2_n_u +{ + struct ipa_hwio_def_ipa_state_dfetcher_mask_2_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_DFETCHER_MASK_3_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_dfetcher_mask_3_n_s +{ + u32 mask_queue_no_resources_seg_ctx : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_dfetcher_mask_3_n_u +{ + struct ipa_hwio_def_ipa_state_dfetcher_mask_3_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ACTIVE_PIPES_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_active_pipes_n_s +{ + u32 endpoints : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_active_pipes_n_u +{ + struct ipa_hwio_def_ipa_active_pipes_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_YELLOW_MARKER_BELOW_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_yellow_marker_below_n_s +{ + u32 endpoints : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_yellow_marker_below_n_u +{ + struct ipa_hwio_def_ipa_yellow_marker_below_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_YELLOW_MARKER_BELOW_EN_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_yellow_marker_below_en_n_s +{ + u32 endpoints : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_yellow_marker_below_en_n_u +{ + struct ipa_hwio_def_ipa_yellow_marker_below_en_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_YELLOW_MARKER_BELOW_CLR_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_yellow_marker_below_clr_n_s +{ + u32 endpoints : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_yellow_marker_below_clr_n_u +{ + struct ipa_hwio_def_ipa_yellow_marker_below_clr_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RED_MARKER_BELOW_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_red_marker_below_n_s +{ + u32 endpoints : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_red_marker_below_n_u +{ + struct ipa_hwio_def_ipa_red_marker_below_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RED_MARKER_BELOW_EN_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_red_marker_below_en_n_s +{ + u32 endpoints : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_red_marker_below_en_n_u +{ + struct ipa_hwio_def_ipa_red_marker_below_en_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RED_MARKER_BELOW_CLR_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_red_marker_below_clr_n_s +{ + u32 endpoints : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_red_marker_below_clr_n_u +{ + struct ipa_hwio_def_ipa_red_marker_below_clr_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_YELLOW_MARKER_SHADOW_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_yellow_marker_shadow_n_s +{ + u32 endpoints : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_yellow_marker_shadow_n_u +{ + struct ipa_hwio_def_ipa_yellow_marker_shadow_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RED_MARKER_SHADOW_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_red_marker_shadow_n_s +{ + u32 endpoints : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_red_marker_shadow_n_u +{ + struct ipa_hwio_def_ipa_red_marker_shadow_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_YELLOW_MARKER_ABOVE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_yellow_marker_above_n_s +{ + u32 endpoints : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_yellow_marker_above_n_u +{ + struct ipa_hwio_def_ipa_yellow_marker_above_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_YELLOW_MARKER_ABOVE_EN_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_yellow_marker_above_en_n_s +{ + u32 endpoints : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_yellow_marker_above_en_n_u +{ + struct ipa_hwio_def_ipa_yellow_marker_above_en_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_YELLOW_MARKER_ABOVE_CLR_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_yellow_marker_above_clr_n_s +{ + u32 endpoints : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_yellow_marker_above_clr_n_u +{ + struct ipa_hwio_def_ipa_yellow_marker_above_clr_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RED_MARKER_ABOVE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_red_marker_above_n_s +{ + u32 endpoints : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_red_marker_above_n_u +{ + struct ipa_hwio_def_ipa_red_marker_above_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RED_MARKER_ABOVE_EN_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_red_marker_above_en_n_s +{ + u32 endpoints : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_red_marker_above_en_n_u +{ + struct ipa_hwio_def_ipa_red_marker_above_en_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RED_MARKER_ABOVE_CLR_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_red_marker_above_clr_n_s +{ + u32 endpoints : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_red_marker_above_clr_n_u +{ + struct ipa_hwio_def_ipa_red_marker_above_clr_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_FILT_ROUT_CACHE_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_filt_rout_cache_cfg_s +{ + u32 ipa_router_cache_en : 1; + u32 reserved0 : 3; + u32 ipa_filter_cache_en : 1; + u32 reserved1 : 3; + u32 cache_low_priority_hashable_hit_disable : 1; + u32 reserved2 : 7; + u32 cache_lru_eviction_threshold : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_filt_rout_cache_cfg_u +{ + struct ipa_hwio_def_ipa_filt_rout_cache_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_FILT_ROUT_CACHE_REDUCE_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_filt_rout_cache_reduce_cfg_s +{ + u32 ipa_router_cache_reduce_en : 1; + u32 reserved0 : 3; + u32 ipa_filter_cache_reduce_en : 1; + u32 reserved1 : 3; + u32 ipa_router_cache_reduce_level : 8; + u32 ipa_filter_cache_reduce_level : 8; + u32 reserved2 : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_filt_rout_cache_reduce_cfg_u +{ + struct ipa_hwio_def_ipa_filt_rout_cache_reduce_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_FILT_ROUT_CACHE_FLUSH +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_filt_rout_cache_flush_s +{ + u32 ipa_router_cache_flush : 1; + u32 reserved0 : 3; + u32 ipa_filter_cache_flush : 1; + u32 reserved1 : 27; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_filt_rout_cache_flush_u +{ + struct ipa_hwio_def_ipa_filt_rout_cache_flush_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_FILT_ROUT_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_filt_rout_cfg_s +{ + u32 router_prefetch_en : 1; + u32 reserved0 : 3; + u32 filter_prefetch_en : 1; + u32 reserved1 : 3; + u32 filt_rout_data_cache_en : 1; + u32 reserved2 : 23; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_filt_rout_cfg_u +{ + struct ipa_hwio_def_ipa_filt_rout_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_IPV4_NAT_EXC_SUPPRESS_ROUT_TABLE_INDX +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ipv4_nat_exc_suppress_rout_table_indx_s +{ + u32 ip_v4_nat_exc_suppress_rout_table_indx : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ipv4_nat_exc_suppress_rout_table_indx_u +{ + struct ipa_hwio_def_ipa_ipv4_nat_exc_suppress_rout_table_indx_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_IPV6_CONN_TRACK_EXC_SUPPRESS_ROUT_TABLE_INDX +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ipv6_conn_track_exc_suppress_rout_table_indx_s +{ + u32 ip_v6_conn_track_exc_suppress_rout_table_indx : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ipv6_conn_track_exc_suppress_rout_table_indx_u +{ + struct ipa_hwio_def_ipa_ipv6_conn_track_exc_suppress_rout_table_indx_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_IPV4_FILTER_INIT_VALUES +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ipv4_filter_init_values_s +{ + u32 ip_v4_filter_init_hashed_addr : 16; + u32 ip_v4_filter_init_non_hashed_addr : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ipv4_filter_init_values_u +{ + struct ipa_hwio_def_ipa_ipv4_filter_init_values_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_IPV6_FILTER_INIT_VALUES +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ipv6_filter_init_values_s +{ + u32 ip_v6_filter_init_hashed_addr : 16; + u32 ip_v6_filter_init_non_hashed_addr : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ipv6_filter_init_values_u +{ + struct ipa_hwio_def_ipa_ipv6_filter_init_values_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_IPV4_NAT_INIT_VALUES_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ipv4_nat_init_values_0_s +{ + u32 ip_v4_nat_init_rules_addr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ipv4_nat_init_values_0_u +{ + struct ipa_hwio_def_ipa_ipv4_nat_init_values_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_IPV4_NAT_INIT_VALUES_0_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ipv4_nat_init_values_0_msb_s +{ + u32 ip_v4_nat_init_rules_addr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ipv4_nat_init_values_0_msb_u +{ + struct ipa_hwio_def_ipa_ipv4_nat_init_values_0_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_IPV4_NAT_INIT_VALUES_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ipv4_nat_init_values_1_s +{ + u32 ip_v4_nat_init_exp_rules_addr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ipv4_nat_init_values_1_u +{ + struct ipa_hwio_def_ipa_ipv4_nat_init_values_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_IPV4_NAT_INIT_VALUES_1_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ipv4_nat_init_values_1_msb_s +{ + u32 ip_v4_nat_init_exp_rules_addr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ipv4_nat_init_values_1_msb_u +{ + struct ipa_hwio_def_ipa_ipv4_nat_init_values_1_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_IPV4_NAT_INIT_VALUES_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ipv4_nat_init_values_2_s +{ + u32 ip_v4_nat_init_index_table_addr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ipv4_nat_init_values_2_u +{ + struct ipa_hwio_def_ipa_ipv4_nat_init_values_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_IPV4_NAT_INIT_VALUES_2_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ipv4_nat_init_values_2_msb_s +{ + u32 ip_v4_nat_init_index_table_addr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ipv4_nat_init_values_2_msb_u +{ + struct ipa_hwio_def_ipa_ipv4_nat_init_values_2_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_IPV4_NAT_INIT_VALUES_3 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ipv4_nat_init_values_3_s +{ + u32 ip_v4_nat_init_index_table_exp_addr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ipv4_nat_init_values_3_u +{ + struct ipa_hwio_def_ipa_ipv4_nat_init_values_3_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_IPV4_NAT_INIT_VALUES_3_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ipv4_nat_init_values_3_msb_s +{ + u32 ip_v4_nat_init_index_table_exp_addr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ipv4_nat_init_values_3_msb_u +{ + struct ipa_hwio_def_ipa_ipv4_nat_init_values_3_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_IPV4_NAT_INIT_VALUES_4 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ipv4_nat_init_values_4_s +{ + u32 ip_v4_nat_init_table_index : 3; + u32 reserved0 : 1; + u32 ip_v4_nat_init_rules_addr_type : 1; + u32 ip_v4_nat_init_exp_rules_addr_type : 1; + u32 ip_v4_nat_init_index_table_addr_type : 1; + u32 ip_v4_nat_init_index_table_exp_addr_type : 1; + u32 ip_v4_nat_init_size_base_tables : 12; + u32 ip_v4_nat_init_size_exp_tables : 10; + u32 reserved1 : 2; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ipv4_nat_init_values_4_u +{ + struct ipa_hwio_def_ipa_ipv4_nat_init_values_4_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_IPV4_NAT_INIT_VALUES_5 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ipv4_nat_init_values_5_s +{ + u32 ip_v4_nat_init_pdn_config_table_addr : 20; + u32 reserved0 : 12; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ipv4_nat_init_values_5_u +{ + struct ipa_hwio_def_ipa_ipv4_nat_init_values_5_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_IPV4_ROUTE_INIT_VALUES +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ipv4_route_init_values_s +{ + u32 ip_v4_route_init_hashed_addr : 16; + u32 ip_v4_route_init_non_hashed_addr : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ipv4_route_init_values_u +{ + struct ipa_hwio_def_ipa_ipv4_route_init_values_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_IPV6_ROUTE_INIT_VALUES +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ipv6_route_init_values_s +{ + u32 ip_v6_route_init_hashed_addr : 16; + u32 ip_v6_route_init_non_hashed_addr : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ipv6_route_init_values_u +{ + struct ipa_hwio_def_ipa_ipv6_route_init_values_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_IPV6_CONN_TRACK_INIT_VALUES_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ipv6_conn_track_init_values_0_s +{ + u32 ip_v6_conn_track_init_table_addr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ipv6_conn_track_init_values_0_u +{ + struct ipa_hwio_def_ipa_ipv6_conn_track_init_values_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_IPV6_CONN_TRACK_INIT_VALUES_0_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ipv6_conn_track_init_values_0_msb_s +{ + u32 ip_v6_conn_track_init_table_addr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ipv6_conn_track_init_values_0_msb_u +{ + struct ipa_hwio_def_ipa_ipv6_conn_track_init_values_0_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_IPV6_CONN_TRACK_INIT_VALUES_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ipv6_conn_track_init_values_1_s +{ + u32 ip_v6_conn_track_init_exp_table_addr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ipv6_conn_track_init_values_1_u +{ + struct ipa_hwio_def_ipa_ipv6_conn_track_init_values_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_IPV6_CONN_TRACK_INIT_VALUES_1_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ipv6_conn_track_init_values_1_msb_s +{ + u32 ip_v6_conn_track_init_exp_table_addr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ipv6_conn_track_init_values_1_msb_u +{ + struct ipa_hwio_def_ipa_ipv6_conn_track_init_values_1_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_IPV6_CONN_TRACK_INIT_VALUES_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ipv6_conn_track_init_values_2_s +{ + u32 ip_v6_conn_track_init_table_index : 3; + u32 reserved0 : 1; + u32 ip_v6_conn_track_init_table_addr_type : 1; + u32 ip_v6_conn_track_init_exp_table_addr_type : 1; + u32 reserved1 : 2; + u32 ip_v6_conn_track_init_size_base_tables : 12; + u32 ip_v6_conn_track_init_size_exp_tables : 10; + u32 reserved2 : 2; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ipv6_conn_track_init_values_2_u +{ + struct ipa_hwio_def_ipa_ipv6_conn_track_init_values_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_HDR_INIT_LOCAL_VALUES +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_hdr_init_local_values_s +{ + u32 reserved0 : 12; + u32 hdr_init_local_hdr_addr : 16; + u32 reserved1 : 4; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_hdr_init_local_values_u +{ + struct ipa_hwio_def_ipa_hdr_init_local_values_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_HDR_INIT_SYSTEM_VALUES +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_hdr_init_system_values_s +{ + u32 hdr_init_system_hdr_table_addr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_hdr_init_system_values_u +{ + struct ipa_hwio_def_ipa_hdr_init_system_values_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_HDR_INIT_SYSTEM_VALUES_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_hdr_init_system_values_msb_s +{ + u32 hdr_init_system_hdr_table_addr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_hdr_init_system_values_msb_u +{ + struct ipa_hwio_def_ipa_hdr_init_system_values_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_IMM_CMD_ACCESS_PIPE_VALUES +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_imm_cmd_access_pipe_values_s +{ + u32 imm_cmd_filter_router_pipe : 8; + u32 imm_cmd_nat_pipe : 8; + u32 imm_cmd_conn_track_pipe : 8; + u32 imm_cmd_hdri_pipe : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_imm_cmd_access_pipe_values_u +{ + struct ipa_hwio_def_ipa_imm_cmd_access_pipe_values_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_IMM_CMD_ACCESS_PIPE_VALUES_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_imm_cmd_access_pipe_values_1_s +{ + u32 imm_cmd_gen_pipe : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_imm_cmd_access_pipe_values_1_u +{ + struct ipa_hwio_def_ipa_imm_cmd_access_pipe_values_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_FRAG_VALUES +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_frag_values_s +{ + u32 ipa_frag_ram_last_addr : 16; + u32 reserved0 : 8; + u32 ipa_frag_fairness_cnt : 4; + u32 reserved1 : 4; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_frag_values_u +{ + struct ipa_hwio_def_ipa_frag_values_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_SYS_PKT_PROC_CNTXT_BASE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_sys_pkt_proc_cntxt_base_s +{ + u32 zero : 3; + u32 addr : 29; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_sys_pkt_proc_cntxt_base_u +{ + struct ipa_hwio_def_ipa_sys_pkt_proc_cntxt_base_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_SYS_PKT_PROC_CNTXT_BASE_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_sys_pkt_proc_cntxt_base_msb_s +{ + u32 addr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_sys_pkt_proc_cntxt_base_msb_u +{ + struct ipa_hwio_def_ipa_sys_pkt_proc_cntxt_base_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_LOCAL_PKT_PROC_CNTXT_BASE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_local_pkt_proc_cntxt_base_s +{ + u32 zero : 3; + u32 addr : 15; + u32 reserved0 : 14; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_local_pkt_proc_cntxt_base_u +{ + struct ipa_hwio_def_ipa_local_pkt_proc_cntxt_base_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_SCND_FRAG_VALUES +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_scnd_frag_values_s +{ + u32 ipa_scnd_frag_ram_last_addr : 16; + u32 reserved0 : 8; + u32 ipa_scnd_frag_fairness_cnt : 4; + u32 reserved1 : 4; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_scnd_frag_values_u +{ + struct ipa_hwio_def_ipa_scnd_frag_values_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_AOS_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_aos_cfg_s +{ + u32 ipa_aos_tx_rx_priority : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_aos_cfg_u +{ + struct ipa_hwio_def_ipa_aos_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_TX_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_tx_cfg_s +{ + u32 reserved0 : 2; + u32 prefetch_almost_empty_size_tx0 : 4; + u32 dmaw_scnd_outsd_pred_threshold : 4; + u32 dmaw_scnd_outsd_pred_en : 1; + u32 dmaw_max_beats_256_dis : 1; + u32 pa_mask_en : 1; + u32 prefetch_almost_empty_size_tx1 : 4; + u32 dual_tx_enable : 1; + u32 sspnd_pa_no_start_state : 1; + u32 reserved1 : 1; + u32 holb_sticky_drop_en : 1; + u32 reserved2 : 11; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_tx_cfg_u +{ + struct ipa_hwio_def_ipa_tx_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_NAT_UC_EXTERNAL_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_nat_uc_external_cfg_s +{ + u32 ipa_nat_uc_external_table_addr_lsb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_nat_uc_external_cfg_u +{ + struct ipa_hwio_def_ipa_nat_uc_external_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_NAT_UC_LOCAL_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_nat_uc_local_cfg_s +{ + u32 ipa_nat_uc_local_table_addr_lsb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_nat_uc_local_cfg_u +{ + struct ipa_hwio_def_ipa_nat_uc_local_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_NAT_UC_SHARED_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_nat_uc_shared_cfg_s +{ + u32 ipa_nat_uc_external_table_addr_msb : 16; + u32 ipa_nat_uc_local_table_addr_msb : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_nat_uc_shared_cfg_u +{ + struct ipa_hwio_def_ipa_nat_uc_shared_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RAM_INTLV_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ram_intlv_cfg_s +{ + u32 ipa_ram_intlv_cfg : 20; + u32 reserved0 : 12; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ram_intlv_cfg_u +{ + struct ipa_hwio_def_ipa_ram_intlv_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_CONN_TRACK_UC_EXTERNAL_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_conn_track_uc_external_cfg_s +{ + u32 ipa_conn_track_uc_external_table_addr_lsb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_conn_track_uc_external_cfg_u +{ + struct ipa_hwio_def_ipa_conn_track_uc_external_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_CONN_TRACK_UC_LOCAL_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_conn_track_uc_local_cfg_s +{ + u32 ipa_conn_track_uc_local_table_addr_lsb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_conn_track_uc_local_cfg_u +{ + struct ipa_hwio_def_ipa_conn_track_uc_local_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_CONN_TRACK_UC_SHARED_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_conn_track_uc_shared_cfg_s +{ + u32 ipa_conn_track_uc_external_table_addr_msb : 16; + u32 ipa_conn_track_uc_local_table_addr_msb : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_conn_track_uc_shared_cfg_u +{ + struct ipa_hwio_def_ipa_conn_track_uc_shared_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_IDLE_INDICATION_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_idle_indication_cfg_s +{ + u32 enter_idle_debounce_thresh : 16; + u32 idle_indication_enable : 1; + u32 reserved0 : 15; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_idle_indication_cfg_u +{ + struct ipa_hwio_def_ipa_idle_indication_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_QTIME_TIMESTAMP_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_qtime_timestamp_cfg_s +{ + u32 reserved0 : 8; + u32 tag_timestamp_lsb : 5; + u32 reserved1 : 3; + u32 nat_timestamp_lsb : 5; + u32 reserved2 : 11; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_qtime_timestamp_cfg_u +{ + struct ipa_hwio_def_ipa_qtime_timestamp_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_TIMERS_XO_CLK_DIV_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_timers_xo_clk_div_cfg_s +{ + u32 value : 9; + u32 reserved0 : 22; + u32 enable : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_timers_xo_clk_div_cfg_u +{ + struct ipa_hwio_def_ipa_timers_xo_clk_div_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_TIMERS_PULSE_GRAN_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_timers_pulse_gran_cfg_s +{ + u32 gran_0 : 3; + u32 gran_1 : 3; + u32 gran_2 : 3; + u32 gran_3 : 3; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_timers_pulse_gran_cfg_u +{ + struct ipa_hwio_def_ipa_timers_pulse_gran_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_QTIME_LSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_qtime_lsb_s +{ + u32 value : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_qtime_lsb_u +{ + struct ipa_hwio_def_ipa_qtime_lsb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_QTIME_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_qtime_msb_s +{ + u32 value : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_qtime_msb_u +{ + struct ipa_hwio_def_ipa_qtime_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_SRC_RSRC_AMOUNT_REDUCE_EN +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_src_rsrc_amount_reduce_en_s +{ + u32 ipa_src_rsrc_amount_reduce_en : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_src_rsrc_amount_reduce_en_u +{ + struct ipa_hwio_def_ipa_src_rsrc_amount_reduce_en_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_src_rsrc_amount_reduce_values_0_s +{ + u32 ipa_src_rsrc_amount_reduce_value_rsrc_type_0 : 6; + u32 reserved0 : 2; + u32 ipa_src_rsrc_amount_reduce_value_rsrc_type_1 : 6; + u32 reserved1 : 2; + u32 ipa_src_rsrc_amount_reduce_value_rsrc_type_2 : 6; + u32 reserved2 : 2; + u32 ipa_src_rsrc_amount_reduce_value_rsrc_type_3 : 6; + u32 reserved3 : 2; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_src_rsrc_amount_reduce_values_0_u +{ + struct ipa_hwio_def_ipa_src_rsrc_amount_reduce_values_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_src_rsrc_amount_reduce_values_1_s +{ + u32 ipa_src_rsrc_amount_reduce_value_rsrc_type_4 : 6; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_src_rsrc_amount_reduce_values_1_u +{ + struct ipa_hwio_def_ipa_src_rsrc_amount_reduce_values_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DST_RSRC_AMOUNT_REDUCE_EN +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_dst_rsrc_amount_reduce_en_s +{ + u32 ipa_dst_rsrc_amount_reduce_en : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_dst_rsrc_amount_reduce_en_u +{ + struct ipa_hwio_def_ipa_dst_rsrc_amount_reduce_en_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DST_RSRC_AMOUNT_REDUCE_VALUES_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_dst_rsrc_amount_reduce_values_0_s +{ + u32 ipa_dst_rsrc_amount_reduce_value_rsrc_type_0 : 6; + u32 reserved0 : 2; + u32 ipa_dst_rsrc_amount_reduce_value_rsrc_type_1 : 6; + u32 reserved1 : 18; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_dst_rsrc_amount_reduce_values_0_u +{ + struct ipa_hwio_def_ipa_dst_rsrc_amount_reduce_values_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ATOMIC_LOCK_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_atomic_lock_cfg_s +{ + u32 groups_to_mask : 6; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_atomic_lock_cfg_u +{ + struct ipa_hwio_def_ipa_atomic_lock_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_GENERIC_RAM_ARBITER_PRIORITY +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_generic_ram_arbiter_priority_s +{ + u32 rd_priority_valid : 1; + u32 wr_priority_valid : 1; + u32 reserved0 : 2; + u32 rd_priority_index : 8; + u32 wr_priority_index : 8; + u32 reserved1 : 12; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_generic_ram_arbiter_priority_u +{ + struct ipa_hwio_def_ipa_generic_ram_arbiter_priority_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DPL_TIMER_SW_ADJ_LSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_dpl_timer_sw_adj_lsb_s +{ + u32 tod_offset_lsb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_dpl_timer_sw_adj_lsb_u +{ + struct ipa_hwio_def_ipa_dpl_timer_sw_adj_lsb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DPL_TIMER_SW_ADJ_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_dpl_timer_sw_adj_msb_s +{ + u32 tod_offset_msb : 20; + u32 reserved0 : 12; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_dpl_timer_sw_adj_msb_u +{ + struct ipa_hwio_def_ipa_dpl_timer_sw_adj_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_src_rsrc_grp_01_rsrc_type_n_s +{ + u32 src_rsrc_grp_0_min_limit : 6; + u32 reserved0 : 2; + u32 src_rsrc_grp_0_max_limit : 6; + u32 reserved1 : 2; + u32 src_rsrc_grp_1_min_limit : 6; + u32 reserved2 : 2; + u32 src_rsrc_grp_1_max_limit : 6; + u32 reserved3 : 2; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_src_rsrc_grp_01_rsrc_type_n_u +{ + struct ipa_hwio_def_ipa_src_rsrc_grp_01_rsrc_type_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_src_rsrc_grp_23_rsrc_type_n_s +{ + u32 src_rsrc_grp_2_min_limit : 6; + u32 reserved0 : 2; + u32 src_rsrc_grp_2_max_limit : 6; + u32 reserved1 : 2; + u32 src_rsrc_grp_3_min_limit : 6; + u32 reserved2 : 2; + u32 src_rsrc_grp_3_max_limit : 6; + u32 reserved3 : 2; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_src_rsrc_grp_23_rsrc_type_n_u +{ + struct ipa_hwio_def_ipa_src_rsrc_grp_23_rsrc_type_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_src_rsrc_grp_45_rsrc_type_n_s +{ + u32 src_rsrc_grp_4_min_limit : 6; + u32 reserved0 : 2; + u32 src_rsrc_grp_4_max_limit : 6; + u32 reserved1 : 2; + u32 src_rsrc_grp_5_min_limit : 6; + u32 reserved2 : 2; + u32 src_rsrc_grp_5_max_limit : 6; + u32 reserved3 : 2; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_src_rsrc_grp_45_rsrc_type_n_u +{ + struct ipa_hwio_def_ipa_src_rsrc_grp_45_rsrc_type_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_src_rsrc_grp_67_rsrc_type_n_s +{ + u32 src_rsrc_grp_6_min_limit : 6; + u32 reserved0 : 2; + u32 src_rsrc_grp_6_max_limit : 6; + u32 reserved1 : 2; + u32 src_rsrc_grp_7_min_limit : 6; + u32 reserved2 : 2; + u32 src_rsrc_grp_7_max_limit : 6; + u32 reserved3 : 2; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_src_rsrc_grp_67_rsrc_type_n_u +{ + struct ipa_hwio_def_ipa_src_rsrc_grp_67_rsrc_type_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_src_rsrc_grp_0123_rsrc_type_cnt_n_s +{ + u32 src_rsrc_grp_0_cnt : 6; + u32 reserved0 : 2; + u32 src_rsrc_grp_1_cnt : 6; + u32 reserved1 : 2; + u32 src_rsrc_grp_2_cnt : 6; + u32 reserved2 : 2; + u32 src_rsrc_grp_3_cnt : 6; + u32 reserved3 : 2; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_src_rsrc_grp_0123_rsrc_type_cnt_n_u +{ + struct ipa_hwio_def_ipa_src_rsrc_grp_0123_rsrc_type_cnt_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_SRC_RSRC_GRP_4567_RSRC_TYPE_CNT_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_src_rsrc_grp_4567_rsrc_type_cnt_n_s +{ + u32 src_rsrc_grp_4_cnt : 6; + u32 reserved0 : 2; + u32 src_rsrc_grp_5_cnt : 6; + u32 reserved1 : 18; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_src_rsrc_grp_4567_rsrc_type_cnt_n_u +{ + struct ipa_hwio_def_ipa_src_rsrc_grp_4567_rsrc_type_cnt_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_SRC_RSRC_TYPE_AMOUNT_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_src_rsrc_type_amount_n_s +{ + u32 src_rsrc_type_amount : 6; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_src_rsrc_type_amount_n_u +{ + struct ipa_hwio_def_ipa_src_rsrc_type_amount_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DST_RSRC_GRP_01_RSRC_TYPE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_dst_rsrc_grp_01_rsrc_type_n_s +{ + u32 dst_rsrc_grp_0_min_limit : 6; + u32 reserved0 : 2; + u32 dst_rsrc_grp_0_max_limit : 6; + u32 reserved1 : 2; + u32 dst_rsrc_grp_1_min_limit : 6; + u32 reserved2 : 2; + u32 dst_rsrc_grp_1_max_limit : 6; + u32 reserved3 : 2; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_dst_rsrc_grp_01_rsrc_type_n_u +{ + struct ipa_hwio_def_ipa_dst_rsrc_grp_01_rsrc_type_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DST_RSRC_GRP_23_RSRC_TYPE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_dst_rsrc_grp_23_rsrc_type_n_s +{ + u32 dst_rsrc_grp_2_min_limit : 6; + u32 reserved0 : 2; + u32 dst_rsrc_grp_2_max_limit : 6; + u32 reserved1 : 2; + u32 dst_rsrc_grp_3_min_limit : 6; + u32 reserved2 : 2; + u32 dst_rsrc_grp_3_max_limit : 6; + u32 reserved3 : 2; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_dst_rsrc_grp_23_rsrc_type_n_u +{ + struct ipa_hwio_def_ipa_dst_rsrc_grp_23_rsrc_type_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DST_RSRC_GRP_45_RSRC_TYPE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_dst_rsrc_grp_45_rsrc_type_n_s +{ + u32 dst_rsrc_grp_4_min_limit : 6; + u32 reserved0 : 2; + u32 dst_rsrc_grp_4_max_limit : 6; + u32 reserved1 : 2; + u32 dst_rsrc_grp_5_min_limit : 6; + u32 reserved2 : 2; + u32 dst_rsrc_grp_5_max_limit : 6; + u32 reserved3 : 2; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_dst_rsrc_grp_45_rsrc_type_n_u +{ + struct ipa_hwio_def_ipa_dst_rsrc_grp_45_rsrc_type_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DST_RSRC_GRP_67_RSRC_TYPE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_dst_rsrc_grp_67_rsrc_type_n_s +{ + u32 dst_rsrc_grp_6_min_limit : 6; + u32 reserved0 : 2; + u32 dst_rsrc_grp_6_max_limit : 6; + u32 reserved1 : 18; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_dst_rsrc_grp_67_rsrc_type_n_u +{ + struct ipa_hwio_def_ipa_dst_rsrc_grp_67_rsrc_type_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_dst_rsrc_grp_0123_rsrc_type_cnt_n_s +{ + u32 dst_rsrc_grp_0_cnt : 6; + u32 reserved0 : 2; + u32 dst_rsrc_grp_1_cnt : 6; + u32 reserved1 : 2; + u32 dst_rsrc_grp_2_cnt : 6; + u32 reserved2 : 2; + u32 dst_rsrc_grp_3_cnt : 6; + u32 reserved3 : 2; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_dst_rsrc_grp_0123_rsrc_type_cnt_n_u +{ + struct ipa_hwio_def_ipa_dst_rsrc_grp_0123_rsrc_type_cnt_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DST_RSRC_GRP_4567_RSRC_TYPE_CNT_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_dst_rsrc_grp_4567_rsrc_type_cnt_n_s +{ + u32 dst_rsrc_grp_4_cnt : 8; + u32 dst_rsrc_grp_5_cnt : 8; + u32 dst_rsrc_grp_6_cnt : 8; + u32 reserved0 : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_dst_rsrc_grp_4567_rsrc_type_cnt_n_u +{ + struct ipa_hwio_def_ipa_dst_rsrc_grp_4567_rsrc_type_cnt_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_DST_RSRC_TYPE_AMOUNT_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_dst_rsrc_type_amount_n_s +{ + u32 dst_rsrc_type_amount : 6; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_dst_rsrc_type_amount_n_u +{ + struct ipa_hwio_def_ipa_dst_rsrc_type_amount_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RX_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rx_cfg_s +{ + u32 cmdq_split_not_wait_data_desc_prior_hdr_push : 1; + u32 rx_cmdq_splitter_cmdq_pending_mux_disable : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rx_cfg_u +{ + struct ipa_hwio_def_ipa_rx_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RSRC_GRP_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rsrc_grp_cfg_s +{ + u32 src_grp_special_valid : 1; + u32 reserved0 : 3; + u32 src_grp_special_index : 3; + u32 reserved1 : 1; + u32 dst_pipe_special_valid : 1; + u32 reserved2 : 3; + u32 dst_pipe_special_index : 8; + u32 dst_grp_special_valid : 1; + u32 reserved3 : 3; + u32 dst_grp_special_index : 6; + u32 reserved4 : 2; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rsrc_grp_cfg_u +{ + struct ipa_hwio_def_ipa_rsrc_grp_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_RSRC_GRP_CFG_EXT +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_rsrc_grp_cfg_ext_s +{ + u32 src_grp_2nd_priority_special_valid : 1; + u32 reserved0 : 3; + u32 src_grp_2nd_priority_special_index : 3; + u32 reserved1 : 25; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_rsrc_grp_cfg_ext_u +{ + struct ipa_hwio_def_ipa_rsrc_grp_cfg_ext_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_AXI_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_axi_cfg_s +{ + u32 relaxed_ordering_gsi_rd : 1; + u32 relaxed_ordering_gsi_wr : 1; + u32 relaxed_ordering_ipa_rd : 1; + u32 relaxed_ordering_ipa_wr : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_axi_cfg_u +{ + struct ipa_hwio_def_ipa_axi_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_AGGR_FORCE_CLOSE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_aggr_force_close_n_s +{ + u32 aggr_force_close_pipe_bitmap : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_aggr_force_close_n_u +{ + struct ipa_hwio_def_ipa_aggr_force_close_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STAT_QUOTA_BASE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_stat_quota_base_n_s +{ + u32 base_addr_offset : 3; + u32 base_addr : 16; + u32 reserved0 : 13; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_stat_quota_base_n_u +{ + struct ipa_hwio_def_ipa_stat_quota_base_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STAT_TETHERING_BASE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_stat_tethering_base_n_s +{ + u32 base_addr_offset : 3; + u32 base_addr : 16; + u32 reserved0 : 13; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_stat_tethering_base_n_u +{ + struct ipa_hwio_def_ipa_stat_tethering_base_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STAT_DROP_CNT_BASE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_stat_drop_cnt_base_n_s +{ + u32 base_addr_offset : 3; + u32 base_addr : 16; + u32 reserved0 : 13; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_stat_drop_cnt_base_n_u +{ + struct ipa_hwio_def_ipa_stat_drop_cnt_base_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STAT_FILTER_IPV4_BASE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_stat_filter_ipv4_base_s +{ + u32 base_addr_offset : 3; + u32 base_addr : 16; + u32 reserved0 : 13; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_stat_filter_ipv4_base_u +{ + struct ipa_hwio_def_ipa_stat_filter_ipv4_base_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STAT_FILTER_IPV6_BASE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_stat_filter_ipv6_base_s +{ + u32 base_addr_offset : 3; + u32 base_addr : 16; + u32 reserved0 : 13; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_stat_filter_ipv6_base_u +{ + struct ipa_hwio_def_ipa_stat_filter_ipv6_base_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STAT_ROUTER_IPV4_BASE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_stat_router_ipv4_base_s +{ + u32 base_addr_offset : 3; + u32 base_addr : 16; + u32 reserved0 : 13; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_stat_router_ipv4_base_u +{ + struct ipa_hwio_def_ipa_stat_router_ipv4_base_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STAT_ROUTER_IPV6_BASE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_stat_router_ipv6_base_s +{ + u32 base_addr_offset : 3; + u32 base_addr : 16; + u32 reserved0 : 13; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_stat_router_ipv6_base_u +{ + struct ipa_hwio_def_ipa_stat_router_ipv6_base_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STAT_QUOTA_MASK_EE_n_REG_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_stat_quota_mask_ee_n_reg_k_s +{ + u32 pipe_mask : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_stat_quota_mask_ee_n_reg_k_u +{ + struct ipa_hwio_def_ipa_stat_quota_mask_ee_n_reg_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STAT_TETHERING_MASK_EE_n_REG_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_stat_tethering_mask_ee_n_reg_k_s +{ + u32 pipe_mask : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_stat_tethering_mask_ee_n_reg_k_u +{ + struct ipa_hwio_def_ipa_stat_tethering_mask_ee_n_reg_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STAT_DROP_CNT_MASK_EE_n_REG_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_stat_drop_cnt_mask_ee_n_reg_k_s +{ + u32 pipe_mask : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_stat_drop_cnt_mask_ee_n_reg_k_u +{ + struct ipa_hwio_def_ipa_stat_drop_cnt_mask_ee_n_reg_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_NLO_PP_CFG1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_nlo_pp_cfg1_s +{ + u32 nlo_ack_pp : 8; + u32 nlo_data_pp : 8; + u32 nlo_status_pp : 8; + u32 nlo_ack_max_vp : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_nlo_pp_cfg1_u +{ + struct ipa_hwio_def_ipa_nlo_pp_cfg1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_NLO_PP_CFG2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_nlo_pp_cfg2_s +{ + u32 nlo_ack_close_padd : 8; + u32 nlo_data_close_padd : 8; + u32 nlo_ack_buffer_mode : 1; + u32 nlo_data_buffer_mode : 1; + u32 nlo_status_buffer_mode : 1; + u32 reserved0 : 13; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_nlo_pp_cfg2_u +{ + struct ipa_hwio_def_ipa_nlo_pp_cfg2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_NLO_MIN_DSM_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_nlo_min_dsm_cfg_s +{ + u32 nlo_ack_min_dsm_len : 16; + u32 nlo_data_min_dsm_len : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_nlo_min_dsm_cfg_u +{ + struct ipa_hwio_def_ipa_nlo_min_dsm_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_NLO_VP_AGGR_CFG_LSB_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_nlo_vp_aggr_cfg_lsb_n_s +{ + u32 vp_pkt_limit : 6; + u32 vp_time_limit : 5; + u32 vp_byte_limit : 6; + u32 vp_hard_byte_limit_en : 1; + u32 vp_aggr_gran_sel : 1; + u32 reserved0 : 13; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_nlo_vp_aggr_cfg_lsb_n_u +{ + struct ipa_hwio_def_ipa_nlo_vp_aggr_cfg_lsb_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_NLO_VP_LIMIT_CFG_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_nlo_vp_limit_cfg_n_s +{ + u32 lower_size : 16; + u32 upper_size : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_nlo_vp_limit_cfg_n_u +{ + struct ipa_hwio_def_ipa_nlo_vp_limit_cfg_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_NLO_VP_FLUSH_REQ +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_nlo_vp_flush_req_s +{ + u32 vp_flush_pp_indx : 8; + u32 reserved0 : 8; + u32 vp_flush_vp_indx : 8; + u32 reserved1 : 7; + u32 vp_flush_req : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_nlo_vp_flush_req_u +{ + struct ipa_hwio_def_ipa_nlo_vp_flush_req_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_NLO_VP_FLUSH_COOKIE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_nlo_vp_flush_cookie_s +{ + u32 vp_flush_cookie : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_nlo_vp_flush_cookie_u +{ + struct ipa_hwio_def_ipa_nlo_vp_flush_cookie_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_NLO_VP_FLUSH_ACK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_nlo_vp_flush_ack_s +{ + u32 vp_flush_ack : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_nlo_vp_flush_ack_u +{ + struct ipa_hwio_def_ipa_nlo_vp_flush_ack_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_NLO_VP_DSM_OPEN +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_nlo_vp_dsm_open_s +{ + u32 vp_dsm_open : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_nlo_vp_dsm_open_u +{ + struct ipa_hwio_def_ipa_nlo_vp_dsm_open_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_NLO_VP_QBAP_OPEN +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_nlo_vp_qbap_open_s +{ + u32 vp_qbap_open : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_nlo_vp_qbap_open_u +{ + struct ipa_hwio_def_ipa_nlo_vp_qbap_open_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_COAL_MASTER_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_coal_master_cfg_s +{ + u32 coal_force_to_default : 1; + u32 coal_enhanced_ipv4_id_en : 1; + u32 coal_ipv4_id_ignore : 1; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_coal_master_cfg_u +{ + struct ipa_hwio_def_ipa_coal_master_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_COAL_EVICT_LRU +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_coal_evict_lru_s +{ + u32 coal_eviction_en : 1; + u32 coal_vp_lru_gran_sel : 2; + u32 coal_vp_lru_udp_thrshld : 5; + u32 coal_vp_lru_tcp_thrshld : 5; + u32 coal_vp_lru_udp_thrshld_en : 1; + u32 coal_vp_lru_tcp_thrshld_en : 1; + u32 coal_vp_lru_tcp_num : 5; + u32 reserved0 : 12; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_coal_evict_lru_u +{ + struct ipa_hwio_def_ipa_coal_evict_lru_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_COAL_QMAP_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_coal_qmap_cfg_s +{ + u32 mux_id_byte_sel : 2; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_coal_qmap_cfg_u +{ + struct ipa_hwio_def_ipa_coal_qmap_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_SNIFFER_QMB_SEL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_sniffer_qmb_sel_s +{ + u32 snif_qmb_sel : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_sniffer_qmb_sel_u +{ + struct ipa_hwio_def_ipa_sniffer_qmb_sel_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ULSO_CFG_IP_ID_MAX_VALUE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ulso_cfg_ip_id_max_value_n_s +{ + u32 ip_id_max_value : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ulso_cfg_ip_id_max_value_n_u +{ + struct ipa_hwio_def_ipa_ulso_cfg_ip_id_max_value_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ULSO_CFG_IP_ID_MIN_VALUE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_ulso_cfg_ip_id_min_value_n_s +{ + u32 ip_id_min_value : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_ulso_cfg_ip_id_min_value_n_u +{ + struct ipa_hwio_def_ipa_ulso_cfg_ip_id_min_value_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_DFETCHER_MASK_4_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_dfetcher_mask_4_n_s +{ + u32 mask_queue_prod_dpl_fifo_full : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_dfetcher_mask_4_n_u +{ + struct ipa_hwio_def_ipa_state_dfetcher_mask_4_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_TSP_QM_EXTERNAL_BADDR_LSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_tsp_qm_external_baddr_lsb_s +{ + u32 baddr_lsbs : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_tsp_qm_external_baddr_lsb_u +{ + struct ipa_hwio_def_ipa_tsp_qm_external_baddr_lsb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_TSP_QM_EXTERNAL_BADDR_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_tsp_qm_external_baddr_msb_s +{ + u32 baddr_msbs : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_tsp_qm_external_baddr_msb_u +{ + struct ipa_hwio_def_ipa_tsp_qm_external_baddr_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_TSP_QM_EXTERNAL_SIZE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_tsp_qm_external_size_s +{ + u32 size_in_4kb_resolution : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_tsp_qm_external_size_u +{ + struct ipa_hwio_def_ipa_tsp_qm_external_size_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_TSP_INGRESS_POLICING_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_tsp_ingress_policing_cfg_s +{ + u32 include_l2_len_per_traffic_class_bitmap : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_tsp_ingress_policing_cfg_u +{ + struct ipa_hwio_def_ipa_tsp_ingress_policing_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_TSP_EGRESS_POLICING_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_tsp_egress_policing_cfg_s +{ + u32 disable_guaranteed_rate_per_traffic_class_bitmap : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_tsp_egress_policing_cfg_u +{ + struct ipa_hwio_def_ipa_tsp_egress_policing_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STAT_TSP_DROP_BASE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_stat_tsp_drop_base_s +{ + u32 base_addr_offset : 3; + u32 base_addr : 16; + u32 reserved0 : 13; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_stat_tsp_drop_base_u +{ + struct ipa_hwio_def_ipa_stat_tsp_drop_base_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_QMNGR_QUEUE_NONEMPTY +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_qmngr_queue_nonempty_s +{ + u32 queue_nonempty_bitmap : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_qmngr_queue_nonempty_u +{ + struct ipa_hwio_def_ipa_state_qmngr_queue_nonempty_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_STATE_PROD_DPL_FIFO +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_state_prod_dpl_fifo_s +{ + u32 pop_fsm_state : 3; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_state_prod_dpl_fifo_u +{ + struct ipa_hwio_def_ipa_state_prod_dpl_fifo_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ENDP_INIT_CTRL_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_endp_init_ctrl_n_s +{ + u32 reserved0 : 1; + u32 endp_delay : 1; + u32 reserved1 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_endp_init_ctrl_n_u +{ + struct ipa_hwio_def_ipa_endp_init_ctrl_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ENDP_INIT_CTRL_SCND_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_endp_init_ctrl_scnd_n_s +{ + u32 reserved0 : 1; + u32 endp_delay : 1; + u32 reserved1 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_endp_init_ctrl_scnd_n_u +{ + struct ipa_hwio_def_ipa_endp_init_ctrl_scnd_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ENDP_INIT_CFG_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_endp_init_cfg_n_s +{ + u32 frag_offload_en : 1; + u32 cs_offload_en : 2; + u32 cs_metadata_hdr_offset : 4; + u32 reserved0 : 1; + u32 gen_qmb_master_sel : 1; + u32 pipe_replicate_en : 1; + u32 reserved1 : 22; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_endp_init_cfg_n_u +{ + struct ipa_hwio_def_ipa_endp_init_cfg_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ENDP_INIT_NAT_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_endp_init_nat_n_s +{ + u32 nat_en : 2; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_endp_init_nat_n_u +{ + struct ipa_hwio_def_ipa_endp_init_nat_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ENDP_INIT_HDR_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_endp_init_hdr_n_s +{ + u32 hdr_len : 6; + u32 hdr_ofst_metadata_valid : 1; + u32 hdr_ofst_metadata : 6; + u32 hdr_additional_const_len : 6; + u32 hdr_ofst_pkt_size_valid : 1; + u32 hdr_ofst_pkt_size : 6; + u32 reserved0 : 1; + u32 hdr_len_inc_deagg_hdr : 1; + u32 hdr_len_msb : 2; + u32 hdr_ofst_metadata_msb : 2; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_endp_init_hdr_n_u +{ + struct ipa_hwio_def_ipa_endp_init_hdr_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ENDP_INIT_HDR_EXT_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_endp_init_hdr_ext_n_s +{ + u32 hdr_endianess : 1; + u32 hdr_total_len_or_pad_valid : 1; + u32 hdr_total_len_or_pad : 1; + u32 hdr_payload_len_inc_padding : 1; + u32 hdr_total_len_or_pad_offset : 6; + u32 hdr_pad_to_alignment : 4; + u32 reserved0 : 2; + u32 hdr_total_len_or_pad_offset_msb : 2; + u32 hdr_ofst_pkt_size_msb : 2; + u32 hdr_additional_const_len_msb : 2; + u32 hdr_bytes_to_remove_valid : 1; + u32 reserved1 : 1; + u32 hdr_bytes_to_remove : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_endp_init_hdr_ext_n_u +{ + struct ipa_hwio_def_ipa_endp_init_hdr_ext_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ENDP_INIT_HDR_METADATA_MASK_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_endp_init_hdr_metadata_mask_n_s +{ + u32 metadata_mask : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_endp_init_hdr_metadata_mask_n_u +{ + struct ipa_hwio_def_ipa_endp_init_hdr_metadata_mask_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ENDP_INIT_HDR_METADATA_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_endp_init_hdr_metadata_n_s +{ + u32 metadata : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_endp_init_hdr_metadata_n_u +{ + struct ipa_hwio_def_ipa_endp_init_hdr_metadata_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ENDP_INIT_MODE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_endp_init_mode_n_s +{ + u32 mode : 3; + u32 bearer_cntx_enable : 1; + u32 dest_pipe_index : 8; + u32 byte_threshold : 16; + u32 reserved0 : 1; + u32 pad_en : 1; + u32 drbip_acl_enable : 1; + u32 reserved1 : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_endp_init_mode_n_u +{ + struct ipa_hwio_def_ipa_endp_init_mode_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ENDP_INIT_AGGR_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_endp_init_aggr_n_s +{ + u32 aggr_en : 2; + u32 aggr_type : 3; + u32 aggr_byte_limit : 6; + u32 reserved0 : 1; + u32 aggr_time_limit : 5; + u32 aggr_pkt_limit : 6; + u32 aggr_sw_eof_active : 1; + u32 aggr_force_close : 1; + u32 reserved1 : 1; + u32 aggr_hard_byte_limit_enable : 1; + u32 aggr_gran_sel : 1; + u32 aggr_coal_l2 : 1; + u32 reserved2 : 3; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_endp_init_aggr_n_u +{ + struct ipa_hwio_def_ipa_endp_init_aggr_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ENDP_INIT_HOL_BLOCK_EN_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_endp_init_hol_block_en_n_s +{ + u32 en : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_endp_init_hol_block_en_n_u +{ + struct ipa_hwio_def_ipa_endp_init_hol_block_en_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ENDP_INIT_HOL_BLOCK_TIMER_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_endp_init_hol_block_timer_n_s +{ + u32 time_limit : 5; + u32 reserved0 : 3; + u32 gran_sel : 2; + u32 reserved1 : 22; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_endp_init_hol_block_timer_n_u +{ + struct ipa_hwio_def_ipa_endp_init_hol_block_timer_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ENDP_INIT_DEAGGR_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_endp_init_deaggr_n_s +{ + u32 deaggr_hdr_len : 6; + u32 syspipe_err_detection : 1; + u32 packet_offset_valid : 1; + u32 packet_offset_location : 6; + u32 ignore_min_pkt_err : 1; + u32 reserved0 : 1; + u32 max_packet_len : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_endp_init_deaggr_n_u +{ + struct ipa_hwio_def_ipa_endp_init_deaggr_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ENDP_INIT_RSRC_GRP_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_endp_init_rsrc_grp_n_s +{ + u32 rsrc_grp : 3; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_endp_init_rsrc_grp_n_u +{ + struct ipa_hwio_def_ipa_endp_init_rsrc_grp_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ENDP_INIT_SEQ_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_endp_init_seq_n_s +{ + u32 hps_seq_type : 5; + u32 reserved0 : 3; + u32 dps_seq_type : 5; + u32 reserved1 : 19; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_endp_init_seq_n_u +{ + struct ipa_hwio_def_ipa_endp_init_seq_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ENDP_STATUS_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_endp_status_n_s +{ + u32 status_en : 1; + u32 status_endp : 8; + u32 status_pkt_supress : 1; + u32 reserved0 : 22; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_endp_status_n_u +{ + struct ipa_hwio_def_ipa_endp_status_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ENDP_SRC_ID_WRITE_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_endp_src_id_write_n_s +{ + u32 src_id_write_value : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_endp_src_id_write_n_u +{ + struct ipa_hwio_def_ipa_endp_src_id_write_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ENDP_SRC_ID_READ_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_endp_src_id_read_n_s +{ + u32 src_id_read_value : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_endp_src_id_read_n_u +{ + struct ipa_hwio_def_ipa_endp_src_id_read_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ENDP_INIT_CONN_TRACK_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_endp_init_conn_track_n_s +{ + u32 conn_track_en : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_endp_init_conn_track_n_u +{ + struct ipa_hwio_def_ipa_endp_init_conn_track_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ENDP_INIT_DRBIP_CFG_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_endp_init_drbip_cfg_n_s +{ + u32 data_sectors_for_imm_cmd : 6; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_endp_init_drbip_cfg_n_u +{ + struct ipa_hwio_def_ipa_endp_init_drbip_cfg_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_FILTER_CACHE_CFG_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_filter_cache_cfg_n_s +{ + u32 filter_cache_msk_src_id : 1; + u32 filter_cache_msk_src_ip_add : 1; + u32 filter_cache_msk_dst_ip_add : 1; + u32 filter_cache_msk_src_port : 1; + u32 filter_cache_msk_dst_port : 1; + u32 filter_cache_msk_protocol : 1; + u32 filter_cache_msk_metadata : 1; + u32 reserved0 : 25; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_filter_cache_cfg_n_u +{ + struct ipa_hwio_def_ipa_filter_cache_cfg_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ROUTER_CACHE_CFG_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_router_cache_cfg_n_s +{ + u32 router_cache_msk_src_id : 1; + u32 router_cache_msk_src_ip_add : 1; + u32 router_cache_msk_dst_ip_add : 1; + u32 router_cache_msk_src_port : 1; + u32 router_cache_msk_dst_port : 1; + u32 router_cache_msk_protocol : 1; + u32 router_cache_msk_metadata : 1; + u32 reserved0 : 25; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_router_cache_cfg_n_u +{ + struct ipa_hwio_def_ipa_router_cache_cfg_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ENDP_YELLOW_RED_MARKER_CFG_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_endp_yellow_red_marker_cfg_n_s +{ + u32 reserved0 : 10; + u32 ipa_yellow_marker_cfg : 6; + u32 reserved1 : 10; + u32 ipa_red_marker_cfg : 6; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_endp_yellow_red_marker_cfg_n_u +{ + struct ipa_hwio_def_ipa_endp_yellow_red_marker_cfg_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ENDP_INIT_CTRL_STATUS_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_endp_init_ctrl_status_n_s +{ + u32 endp_suspend_status : 1; + u32 endp_delay_status : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_endp_init_ctrl_status_n_u +{ + struct ipa_hwio_def_ipa_endp_init_ctrl_status_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ENDP_INIT_PROD_CFG_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_endp_init_prod_cfg_n_s +{ + u32 tx_sel : 1; + u32 tsp_enable : 1; + u32 prod_max_output_size_drop_enable : 1; + u32 reserved0 : 1; + u32 tsp_producer_index : 4; + u32 prod_max_output_size_size : 8; + u32 prod_egress_tc_lowest : 8; + u32 prod_egress_tc_highest : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_endp_init_prod_cfg_n_u +{ + struct ipa_hwio_def_ipa_endp_init_prod_cfg_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ENDP_INIT_ULSO_CFG_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_endp_init_ulso_cfg_n_s +{ + u32 ipv4_id_min_max_val_index : 2; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_endp_init_ulso_cfg_n_u +{ + struct ipa_hwio_def_ipa_endp_init_ulso_cfg_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ENDP_INIT_UCP_CFG_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_endp_init_ucp_cfg_n_s +{ + u32 ucp_command_id : 16; + u32 ucp_trigger_en : 1; + u32 reserved0 : 15; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_endp_init_ucp_cfg_n_u +{ + struct ipa_hwio_def_ipa_endp_init_ucp_cfg_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_ENDP_INIT_NAT_EXC_SUPPRESS_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_endp_init_nat_exc_suppress_n_s +{ + u32 nat_exc_suppress : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_endp_init_nat_exc_suppress_n_u +{ + struct ipa_hwio_def_ipa_endp_init_nat_exc_suppress_n_s def; + u32 value; +}; + +/*---------------------------------------------------------------------------- + * MODULE: IPA_0_IPA_VMIDMT_IPA_VMIDMT_VMIDMT_SMR_48_SSD8_SID8_MA128_40 + *--------------------------------------------------------------------------*/ + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_VMIDMT_VMIDMT_SCR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_scr0_s +{ + u32 clientpd : 1; + u32 reserved0 : 1; + u32 gfie : 1; + u32 reserved1 : 1; + u32 gcfgere : 1; + u32 gcfgfie : 1; + u32 transientcfg : 2; + u32 stalld : 1; + u32 gse : 1; + u32 usfcfg : 1; + u32 reserved2 : 5; + u32 memattr : 3; + u32 reserved3 : 1; + u32 mtcfg : 1; + u32 smcfcfg : 1; + u32 shcfg : 2; + u32 racfg : 2; + u32 wacfg : 2; + u32 nscfg : 2; + u32 reserved4 : 2; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_scr0_u +{ + struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_scr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_VMIDMT_VMIDMT_SCR1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_scr1_s +{ + u32 reserved0 : 8; + u32 nsnumsmrgo : 6; + u32 reserved1 : 10; + u32 gasrae : 1; + u32 reserved2 : 7; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_scr1_u +{ + struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_scr1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_VMIDMT_VMIDMT_SCR2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_scr2_s +{ + u32 bpvmid : 5; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_scr2_u +{ + struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_scr2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_VMIDMT_VMIDMT_SACR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_sacr_s +{ + u32 bpreqpriority : 2; + u32 reserved0 : 2; + u32 bpreqprioritycfg : 1; + u32 reserved1 : 23; + u32 bprcosh : 1; + u32 bprcish : 1; + u32 bprcnsh : 1; + u32 reserved2 : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_sacr_u +{ + struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_sacr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_VMIDMT_VMIDMT_SIDR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_sidr0_s +{ + u32 numsmrg : 8; + u32 reserved0 : 1; + u32 numsidb : 4; + u32 reserved1 : 14; + u32 sms : 1; + u32 reserved2 : 3; + u32 ses : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_sidr0_u +{ + struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_sidr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_VMIDMT_VMIDMT_SIDR1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_sidr1_s +{ + u32 reserved0 : 8; + u32 numssdndx : 4; + u32 ssdtp : 1; + u32 reserved1 : 2; + u32 smcd : 1; + u32 reserved2 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_sidr1_u +{ + struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_sidr1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_VMIDMT_VMIDMT_SIDR2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_sidr2_s +{ + u32 ias : 4; + u32 oas : 4; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_sidr2_u +{ + struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_sidr2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_VMIDMT_VMIDMT_SIDR4 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_sidr4_s +{ + u32 step : 16; + u32 minor : 12; + u32 major : 4; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_sidr4_u +{ + struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_sidr4_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_VMIDMT_VMIDMT_SIDR5 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_sidr5_s +{ + u32 nvmid : 8; + u32 qribe : 1; + u32 msae : 1; + u32 reserved0 : 6; + u32 nummsdrb : 8; + u32 reserved1 : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_sidr5_u +{ + struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_sidr5_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_VMIDMT_VMIDMT_SIDR7 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_sidr7_s +{ + u32 minor : 4; + u32 major : 4; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_sidr7_u +{ + struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_sidr7_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_VMIDMT_VMIDMT_SGFAR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_sgfar0_s +{ + u32 sgfea0 : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_sgfar0_u +{ + struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_sgfar0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_VMIDMT_VMIDMT_SGFAR1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_sgfar1_s +{ + u32 sgfea1 : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_sgfar1_u +{ + struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_sgfar1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_VMIDMT_VMIDMT_SGFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_sgfsr_s +{ + u32 reserved0 : 1; + u32 usf : 1; + u32 smcf : 1; + u32 reserved1 : 2; + u32 caf : 1; + u32 reserved2 : 24; + u32 multi_cfg : 1; + u32 multi_client : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_sgfsr_u +{ + struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_sgfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_VMIDMT_VMIDMT_SGFSRRESTORE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_sgfsrrestore_s +{ + u32 reserved0 : 1; + u32 usf : 1; + u32 smcf : 1; + u32 reserved1 : 2; + u32 caf : 1; + u32 reserved2 : 24; + u32 multi_cfg : 1; + u32 multi_client : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_sgfsrrestore_u +{ + struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_sgfsrrestore_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_VMIDMT_VMIDMT_SGFSYNDR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_sgfsyndr0_s +{ + u32 reserved0 : 1; + u32 wnr : 1; + u32 reserved1 : 2; + u32 nsstate : 1; + u32 nsattr : 1; + u32 reserved2 : 2; + u32 mssselfauth : 1; + u32 reserved3 : 23; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_sgfsyndr0_u +{ + struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_sgfsyndr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_VMIDMT_VMIDMT_SGFSYNDR1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_sgfsyndr1_s +{ + u32 streamindex : 8; + u32 reserved0 : 8; + u32 ssdindex : 8; + u32 msdindex : 7; + u32 reserved1 : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_sgfsyndr1_u +{ + struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_sgfsyndr1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_VMIDMT_VMIDMT_SGFSYNDR2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_sgfsyndr2_s +{ + u32 amid : 8; + u32 apid : 5; + u32 abid : 3; + u32 avmid : 5; + u32 reserved0 : 3; + u32 atid : 5; + u32 reserved1 : 3; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_sgfsyndr2_u +{ + struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_sgfsyndr2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_VMIDMT_VMIDMT_VMIDMTSCR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_vmidmtscr0_s +{ + u32 clkonoffe : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_vmidmtscr0_u +{ + struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_vmidmtscr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_VMIDMT_VMIDMT_CR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_cr0_s +{ + u32 clientpd : 1; + u32 reserved0 : 1; + u32 gfie : 1; + u32 reserved1 : 1; + u32 gcfgere : 1; + u32 gcfgfie : 1; + u32 transientcfg : 2; + u32 stalld : 1; + u32 gse : 1; + u32 usfcfg : 1; + u32 vmidpne : 1; + u32 reserved2 : 4; + u32 memattr : 3; + u32 reserved3 : 1; + u32 mtcfg : 1; + u32 smcfcfg : 1; + u32 shcfg : 2; + u32 racfg : 2; + u32 wacfg : 2; + u32 reserved4 : 4; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_cr0_u +{ + struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_cr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_VMIDMT_VMIDMT_CR2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_cr2_s +{ + u32 bpvmid : 5; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_cr2_u +{ + struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_cr2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_VMIDMT_VMIDMT_ACR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_acr_s +{ + u32 bpreqpriority : 2; + u32 reserved0 : 2; + u32 bpreqprioritycfg : 1; + u32 reserved1 : 23; + u32 bprcosh : 1; + u32 bprcish : 1; + u32 bprcnsh : 1; + u32 reserved2 : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_acr_u +{ + struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_acr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_VMIDMT_VMIDMT_IDR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_idr0_s +{ + u32 numsmrg : 8; + u32 reserved0 : 1; + u32 numsidb : 4; + u32 reserved1 : 14; + u32 sms : 1; + u32 reserved2 : 4; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_idr0_u +{ + struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_idr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_VMIDMT_VMIDMT_IDR1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_idr1_s +{ + u32 reserved0 : 8; + u32 numssdndx : 4; + u32 ssdtp : 1; + u32 reserved1 : 2; + u32 smcd : 1; + u32 reserved2 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_idr1_u +{ + struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_idr1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_VMIDMT_VMIDMT_IDR2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_idr2_s +{ + u32 ias : 4; + u32 oas : 4; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_idr2_u +{ + struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_idr2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_VMIDMT_VMIDMT_IDR4 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_idr4_s +{ + u32 step : 16; + u32 minor : 12; + u32 major : 4; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_idr4_u +{ + struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_idr4_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_VMIDMT_VMIDMT_IDR5 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_idr5_s +{ + u32 nvmid : 8; + u32 qribe : 1; + u32 msae : 1; + u32 reserved0 : 6; + u32 nummsdrb : 8; + u32 reserved1 : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_idr5_u +{ + struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_idr5_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_VMIDMT_VMIDMT_IDR7 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_idr7_s +{ + u32 minor : 4; + u32 major : 4; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_idr7_u +{ + struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_idr7_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_VMIDMT_VMIDMT_GFAR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_gfar0_s +{ + u32 gfea0 : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_gfar0_u +{ + struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_gfar0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_VMIDMT_VMIDMT_GFAR1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_gfar1_s +{ + u32 gfea1 : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_gfar1_u +{ + struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_gfar1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_VMIDMT_VMIDMT_GFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_gfsr_s +{ + u32 reserved0 : 1; + u32 usf : 1; + u32 smcf : 1; + u32 reserved1 : 2; + u32 caf : 1; + u32 reserved2 : 1; + u32 pf : 1; + u32 reserved3 : 22; + u32 multi_cfg : 1; + u32 multi_client : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_gfsr_u +{ + struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_gfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_VMIDMT_VMIDMT_GFSRRESTORE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_gfsrrestore_s +{ + u32 reserved0 : 1; + u32 usf : 1; + u32 smcf : 1; + u32 reserved1 : 2; + u32 caf : 1; + u32 reserved2 : 1; + u32 pf : 1; + u32 reserved3 : 22; + u32 multi_cfg : 1; + u32 multi_client : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_gfsrrestore_u +{ + struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_gfsrrestore_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_VMIDMT_VMIDMT_GFSYNDR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_gfsyndr0_s +{ + u32 reserved0 : 1; + u32 wnr : 1; + u32 reserved1 : 2; + u32 nsstate : 1; + u32 nsattr : 1; + u32 reserved2 : 2; + u32 mssselfauth : 1; + u32 reserved3 : 23; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_gfsyndr0_u +{ + struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_gfsyndr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_VMIDMT_VMIDMT_GFSYNDR1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_gfsyndr1_s +{ + u32 streamindex : 8; + u32 reserved0 : 8; + u32 ssdindex : 8; + u32 msdindex : 7; + u32 reserved1 : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_gfsyndr1_u +{ + struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_gfsyndr1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_VMIDMT_VMIDMT_GFSYNDR2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_gfsyndr2_s +{ + u32 amid : 8; + u32 apid : 5; + u32 abid : 3; + u32 avmid : 5; + u32 reserved0 : 3; + u32 atid : 5; + u32 reserved1 : 3; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_gfsyndr2_u +{ + struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_gfsyndr2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_VMIDMT_VMIDMT_VMIDMTCR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_vmidmtcr0_s +{ + u32 clkonoffe : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_vmidmtcr0_u +{ + struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_vmidmtcr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_VMIDMT_VMIDMT_VMIDMTACR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_vmidmtacr_s +{ + u32 rwe : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_vmidmtacr_u +{ + struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_vmidmtacr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_VMIDMT_VMIDMT_NSCR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_nscr0_s +{ + u32 clientpd : 1; + u32 reserved0 : 1; + u32 gfie : 1; + u32 reserved1 : 1; + u32 gcfgere : 1; + u32 gcfgfie : 1; + u32 transientcfg : 2; + u32 stalld : 1; + u32 gse : 1; + u32 usfcfg : 1; + u32 vmidpne : 1; + u32 reserved2 : 4; + u32 memattr : 3; + u32 reserved3 : 1; + u32 mtcfg : 1; + u32 smcfcfg : 1; + u32 shcfg : 2; + u32 racfg : 2; + u32 wacfg : 2; + u32 reserved4 : 4; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_nscr0_u +{ + struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_nscr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_VMIDMT_VMIDMT_NSCR2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_nscr2_s +{ + u32 bpvmid : 5; + u32 reserved0 : 27; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_nscr2_u +{ + struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_nscr2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_VMIDMT_VMIDMT_NSACR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_nsacr_s +{ + u32 bpreqpriority : 2; + u32 reserved0 : 2; + u32 bpreqprioritycfg : 1; + u32 reserved1 : 23; + u32 bprcosh : 1; + u32 bprcish : 1; + u32 bprcnsh : 1; + u32 reserved2 : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_nsacr_u +{ + struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_nsacr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_VMIDMT_VMIDMT_NSGFAR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_nsgfar0_s +{ + u32 gfea0 : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_nsgfar0_u +{ + struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_nsgfar0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_VMIDMT_VMIDMT_NSGFAR1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_nsgfar1_s +{ + u32 gfea1 : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_nsgfar1_u +{ + struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_nsgfar1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_VMIDMT_VMIDMT_NSGFSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_nsgfsr_s +{ + u32 reserved0 : 1; + u32 usf : 1; + u32 smcf : 1; + u32 reserved1 : 2; + u32 caf : 1; + u32 reserved2 : 1; + u32 pf : 1; + u32 reserved3 : 22; + u32 multi_cfg : 1; + u32 multi_client : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_nsgfsr_u +{ + struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_nsgfsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_VMIDMT_VMIDMT_NSGFSRRESTORE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_nsgfsrrestore_s +{ + u32 reserved0 : 1; + u32 usf : 1; + u32 smcf : 1; + u32 reserved1 : 2; + u32 caf : 1; + u32 reserved2 : 1; + u32 pf : 1; + u32 reserved3 : 22; + u32 multi_cfg : 1; + u32 multi_client : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_nsgfsrrestore_u +{ + struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_nsgfsrrestore_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_VMIDMT_VMIDMT_NSGFSYNDR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_nsgfsyndr0_s +{ + u32 reserved0 : 1; + u32 wnr : 1; + u32 reserved1 : 2; + u32 nsstate : 1; + u32 nsattr : 1; + u32 reserved2 : 2; + u32 mssselfauth : 1; + u32 reserved3 : 23; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_nsgfsyndr0_u +{ + struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_nsgfsyndr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_VMIDMT_VMIDMT_NSGFSYNDR1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_nsgfsyndr1_s +{ + u32 streamindex : 8; + u32 reserved0 : 8; + u32 ssdindex : 8; + u32 msdindex : 7; + u32 reserved1 : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_nsgfsyndr1_u +{ + struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_nsgfsyndr1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_VMIDMT_VMIDMT_NSGFSYNDR2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_nsgfsyndr2_s +{ + u32 amid : 8; + u32 apid : 5; + u32 abid : 3; + u32 avmid : 5; + u32 reserved0 : 3; + u32 atid : 5; + u32 reserved1 : 3; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_nsgfsyndr2_u +{ + struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_nsgfsyndr2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_VMIDMT_VMIDMT_NSVMIDMTCR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_nsvmidmtcr0_s +{ + u32 clkonoffe : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_nsvmidmtcr0_u +{ + struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_nsvmidmtcr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_VMIDMT_VMIDMT_SSDR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_ssdr0_s +{ + u32 rwe : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_ssdr0_u +{ + struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_ssdr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_VMIDMT_VMIDMT_SSDR1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_ssdr1_s +{ + u32 rwe : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_ssdr1_u +{ + struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_ssdr1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_VMIDMT_VMIDMT_SSDR2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_ssdr2_s +{ + u32 rwe : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_ssdr2_u +{ + struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_ssdr2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_VMIDMT_VMIDMT_SSDR3 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_ssdr3_s +{ + u32 rwe : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_ssdr3_u +{ + struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_ssdr3_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_VMIDMT_VMIDMT_MSDR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_msdr0_s +{ + u32 rwe : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_msdr0_u +{ + struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_msdr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_VMIDMT_VMIDMT_MSDR1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_msdr1_s +{ + u32 rwe : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_msdr1_u +{ + struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_msdr1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_VMIDMT_VMIDMT_MSDR2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_msdr2_s +{ + u32 rwe : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_msdr2_u +{ + struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_msdr2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_VMIDMT_VMIDMT_MSDR3 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_msdr3_s +{ + u32 rwe : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_msdr3_u +{ + struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_msdr3_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_VMIDMT_VMIDMT_MCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_mcr_s +{ + u32 bpsmsacfg : 1; + u32 bpmsacfg : 1; + u32 clkonoffe : 1; + u32 reserved0 : 29; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_mcr_u +{ + struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_mcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_VMIDMT_VMIDMT_S2VRn +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_s2vrn_s +{ + u32 vmid : 5; + u32 reserved0 : 3; + u32 shcfg : 2; + u32 reserved1 : 1; + u32 mtcfg : 1; + u32 memattr : 3; + u32 reserved2 : 1; + u32 type : 2; + u32 nscfg : 2; + u32 racfg : 2; + u32 wacfg : 2; + u32 reserved3 : 4; + u32 transientcfg : 2; + u32 reserved4 : 2; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_s2vrn_u +{ + struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_s2vrn_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_VMIDMT_VMIDMT_AS2VRn +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_as2vrn_s +{ + u32 reqpriority : 2; + u32 reserved0 : 2; + u32 reqprioritycfg : 1; + u32 reserved1 : 23; + u32 rcosh : 1; + u32 rcish : 1; + u32 rcnsh : 1; + u32 reserved2 : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_as2vrn_u +{ + struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_as2vrn_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_VMIDMT_VMIDMT_SMRn +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_smrn_s +{ + u32 id : 8; + u32 reserved0 : 8; + u32 mask : 8; + u32 reserved1 : 7; + u32 valid : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_smrn_u +{ + struct ipa_hwio_def_ipa_0_ipa_vmidmt_vmidmt_smrn_s def; + u32 value; +}; + +/*---------------------------------------------------------------------------- + * MODULE: IPA_0_IPA_ER_XPU_CFG_ER_XPU4 + *--------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------- + * MODULE: IPA_0_IPA_ER_XPU_CFG_XPU4 + *--------------------------------------------------------------------------*/ + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_ER_XPU_CFG_XPU4_IDR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_er_xpu_cfg_xpu4_idr0_s +{ + u32 xpu_type : 2; + u32 reserved0 : 2; + u32 client_pipeline_en : 1; + u32 client_haltreqack_en : 1; + u32 bled : 1; + u32 reserved1 : 9; + u32 nrg : 10; + u32 reserved2 : 6; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_er_xpu_cfg_xpu4_idr0_u +{ + struct ipa_hwio_def_ipa_0_ipa_er_xpu_cfg_xpu4_idr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_ER_XPU_CFG_XPU4_IDR1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_er_xpu_cfg_xpu4_idr1_s +{ + u32 addr_lsb : 6; + u32 reserved0 : 2; + u32 addr_msb : 6; + u32 reserved1 : 2; + u32 config_addr_width : 6; + u32 reserved2 : 2; + u32 client_addr_width : 6; + u32 reserved3 : 2; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_er_xpu_cfg_xpu4_idr1_u +{ + struct ipa_hwio_def_ipa_0_ipa_er_xpu_cfg_xpu4_idr1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_ER_XPU_CFG_XPU4_IDR2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_er_xpu_cfg_xpu4_idr2_s +{ + u32 nqad : 5; + u32 reserved0 : 3; + u32 uselegacyintf : 1; + u32 reserved1 : 23; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_er_xpu_cfg_xpu4_idr2_u +{ + struct ipa_hwio_def_ipa_0_ipa_er_xpu_cfg_xpu4_idr2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_ER_XPU_CFG_XPU4_REV +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_er_xpu_cfg_xpu4_rev_s +{ + u32 step : 16; + u32 minor : 12; + u32 major : 4; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_er_xpu_cfg_xpu4_rev_u +{ + struct ipa_hwio_def_ipa_0_ipa_er_xpu_cfg_xpu4_rev_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_ER_XPU_CFG_XPU4_GCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_er_xpu_cfg_xpu4_gcr_s +{ + u32 apnspe : 1; + u32 dynamic_clk_en : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_er_xpu_cfg_xpu4_gcr_u +{ + struct ipa_hwio_def_ipa_0_ipa_er_xpu_cfg_xpu4_gcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_ER_XPU_CFG_XPU4_RSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_er_xpu_cfg_xpu4_rsr_s +{ + u32 numfrg : 16; + u32 nxtfrg : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_er_xpu_cfg_xpu4_rsr_u +{ + struct ipa_hwio_def_ipa_0_ipa_er_xpu_cfg_xpu4_rsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_ER_XPU_CFG_XPU4_CFGERE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_er_xpu_cfg_xpu4_cfgere_s +{ + u32 cfgere_qad : 7; + u32 reserved0 : 23; + u32 cfgere_ns : 1; + u32 cfgere_s : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_er_xpu_cfg_xpu4_cfgere_u +{ + struct ipa_hwio_def_ipa_0_ipa_er_xpu_cfg_xpu4_cfgere_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_ER_XPU_CFG_XPU4_CLERE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_er_xpu_cfg_xpu4_clere_s +{ + u32 clere_qad : 7; + u32 reserved0 : 23; + u32 clere_ns : 1; + u32 clere_s : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_er_xpu_cfg_xpu4_clere_u +{ + struct ipa_hwio_def_ipa_0_ipa_er_xpu_cfg_xpu4_clere_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_ER_XPU_CFG_XPU4_DBGAR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_er_xpu_cfg_xpu4_dbgar_s +{ + u32 dbga_qad : 7; + u32 reserved0 : 23; + u32 dbga_ns : 1; + u32 dbga_s : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_er_xpu_cfg_xpu4_dbgar_u +{ + struct ipa_hwio_def_ipa_0_ipa_er_xpu_cfg_xpu4_dbgar_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_ER_XPU_CFG_XPU4_ESR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_er_xpu_cfg_xpu4_esr_s +{ + u32 cfgerr : 1; + u32 clerr : 1; + u32 cfgmulti : 1; + u32 clmulti : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_er_xpu_cfg_xpu4_esr_u +{ + struct ipa_hwio_def_ipa_0_ipa_er_xpu_cfg_xpu4_esr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_ER_XPU_CFG_XPU4_SYNAR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_er_xpu_cfg_xpu4_synar0_s +{ + u32 synaddr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_er_xpu_cfg_xpu4_synar0_u +{ + struct ipa_hwio_def_ipa_0_ipa_er_xpu_cfg_xpu4_synar0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_ER_XPU_CFG_XPU4_SYNAR1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_er_xpu_cfg_xpu4_synar1_s +{ + u32 synaddr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_er_xpu_cfg_xpu4_synar1_u +{ + struct ipa_hwio_def_ipa_0_ipa_er_xpu_cfg_xpu4_synar1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_er_xpu_cfg_xpu4_synr0_s +{ + u32 xprotns : 1; + u32 inst : 1; + u32 priv : 1; + u32 req_opc : 4; + u32 reserved0 : 1; + u32 qad : 5; + u32 reserved1 : 2; + u32 len : 8; + u32 ssize : 3; + u32 apudecerr : 1; + u32 qaderr : 1; + u32 burstlen : 1; + u32 ac_cl : 1; + u32 ac_cfg : 1; + u32 ph : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_er_xpu_cfg_xpu4_synr0_u +{ + struct ipa_hwio_def_ipa_0_ipa_er_xpu_cfg_xpu4_synr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_er_xpu_cfg_xpu4_synr1_s +{ + u32 mid : 8; + u32 pid : 5; + u32 bid : 3; + u32 trtype : 3; + u32 reserved0 : 5; + u32 tid : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_er_xpu_cfg_xpu4_synr1_u +{ + struct ipa_hwio_def_ipa_0_ipa_er_xpu_cfg_xpu4_synr1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_ER_XPU_CFG_XPU4_SYNR2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_er_xpu_cfg_xpu4_synr2_s +{ + u32 dirtyinfo : 1; + u32 cacheallocation : 4; + u32 writethrough : 1; + u32 noallocate : 1; + u32 transient : 1; + u32 memtype : 3; + u32 innercacheable : 1; + u32 redirbits : 4; + u32 atopc : 4; + u32 optrw_en : 1; + u32 cesde : 1; + u32 apnsee : 1; + u32 cfg_owner : 1; + u32 sle : 1; + u32 apsvioe : 1; + u32 reserved0 : 6; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_er_xpu_cfg_xpu4_synr2_u +{ + struct ipa_hwio_def_ipa_0_ipa_er_xpu_cfg_xpu4_synr2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_ER_XPU_CFG_XPU4_RGCR0n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_er_xpu_cfg_xpu4_rgcr0n_s +{ + u32 rgwowp : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_er_xpu_cfg_xpu4_rgcr0n_u +{ + struct ipa_hwio_def_ipa_0_ipa_er_xpu_cfg_xpu4_rgcr0n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_ER_XPU_CFG_XPU4_RGCR1n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_er_xpu_cfg_xpu4_rgcr1n_s +{ + u32 rge : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_er_xpu_cfg_xpu4_rgcr1n_u +{ + struct ipa_hwio_def_ipa_0_ipa_er_xpu_cfg_xpu4_rgcr1n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_ER_XPU_CFG_XPU4_RGRDRn +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_er_xpu_cfg_xpu4_rgrdrn_s +{ + u32 rda_qad : 7; + u32 reserved0 : 23; + u32 rda_ns : 1; + u32 rda_s : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_er_xpu_cfg_xpu4_rgrdrn_u +{ + struct ipa_hwio_def_ipa_0_ipa_er_xpu_cfg_xpu4_rgrdrn_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_ER_XPU_CFG_XPU4_RGWRRn +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_er_xpu_cfg_xpu4_rgwrrn_s +{ + u32 wra_qad : 7; + u32 reserved0 : 23; + u32 wra_ns : 1; + u32 wra_s : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_er_xpu_cfg_xpu4_rgwrrn_u +{ + struct ipa_hwio_def_ipa_0_ipa_er_xpu_cfg_xpu4_rgwrrn_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_ER_XPU_CFG_XPU4_QADRGLn +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_er_xpu_cfg_xpu4_qadrgln_s +{ + u32 rgl_qad : 7; + u32 reserved0 : 23; + u32 rgl_ns : 1; + u32 rgl_s : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_er_xpu_cfg_xpu4_qadrgln_u +{ + struct ipa_hwio_def_ipa_0_ipa_er_xpu_cfg_xpu4_qadrgln_s def; + u32 value; +}; + +/*---------------------------------------------------------------------------- + * MODULE: IPA_0_IPA_RA_XPU_CFG_RA_XPU4 + *--------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------- + * MODULE: IPA_0_IPA_RA_XPU_CFG_XPU4 + *--------------------------------------------------------------------------*/ + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_RA_XPU_CFG_XPU4_IDR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_ra_xpu_cfg_xpu4_idr0_s +{ + u32 xpu_type : 2; + u32 reserved0 : 2; + u32 client_pipeline_en : 1; + u32 client_haltreqack_en : 1; + u32 bled : 1; + u32 reserved1 : 9; + u32 nrg : 10; + u32 reserved2 : 6; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_ra_xpu_cfg_xpu4_idr0_u +{ + struct ipa_hwio_def_ipa_0_ipa_ra_xpu_cfg_xpu4_idr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_RA_XPU_CFG_XPU4_IDR1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_ra_xpu_cfg_xpu4_idr1_s +{ + u32 addr_lsb : 6; + u32 reserved0 : 2; + u32 addr_msb : 6; + u32 reserved1 : 2; + u32 config_addr_width : 6; + u32 reserved2 : 2; + u32 client_addr_width : 6; + u32 reserved3 : 2; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_ra_xpu_cfg_xpu4_idr1_u +{ + struct ipa_hwio_def_ipa_0_ipa_ra_xpu_cfg_xpu4_idr1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_RA_XPU_CFG_XPU4_IDR2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_ra_xpu_cfg_xpu4_idr2_s +{ + u32 nqad : 5; + u32 reserved0 : 3; + u32 uselegacyintf : 1; + u32 reserved1 : 23; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_ra_xpu_cfg_xpu4_idr2_u +{ + struct ipa_hwio_def_ipa_0_ipa_ra_xpu_cfg_xpu4_idr2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_RA_XPU_CFG_XPU4_REV +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_ra_xpu_cfg_xpu4_rev_s +{ + u32 step : 16; + u32 minor : 12; + u32 major : 4; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_ra_xpu_cfg_xpu4_rev_u +{ + struct ipa_hwio_def_ipa_0_ipa_ra_xpu_cfg_xpu4_rev_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_RA_XPU_CFG_XPU4_GCR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_ra_xpu_cfg_xpu4_gcr_s +{ + u32 apnspe : 1; + u32 dynamic_clk_en : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_ra_xpu_cfg_xpu4_gcr_u +{ + struct ipa_hwio_def_ipa_0_ipa_ra_xpu_cfg_xpu4_gcr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_RA_XPU_CFG_XPU4_RSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_ra_xpu_cfg_xpu4_rsr_s +{ + u32 numfrg : 16; + u32 nxtfrg : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_ra_xpu_cfg_xpu4_rsr_u +{ + struct ipa_hwio_def_ipa_0_ipa_ra_xpu_cfg_xpu4_rsr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_RA_XPU_CFG_XPU4_CFGERE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_ra_xpu_cfg_xpu4_cfgere_s +{ + u32 cfgere_qad : 7; + u32 reserved0 : 23; + u32 cfgere_ns : 1; + u32 cfgere_s : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_ra_xpu_cfg_xpu4_cfgere_u +{ + struct ipa_hwio_def_ipa_0_ipa_ra_xpu_cfg_xpu4_cfgere_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_RA_XPU_CFG_XPU4_CLERE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_ra_xpu_cfg_xpu4_clere_s +{ + u32 clere_qad : 7; + u32 reserved0 : 23; + u32 clere_ns : 1; + u32 clere_s : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_ra_xpu_cfg_xpu4_clere_u +{ + struct ipa_hwio_def_ipa_0_ipa_ra_xpu_cfg_xpu4_clere_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_RA_XPU_CFG_XPU4_DBGAR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_ra_xpu_cfg_xpu4_dbgar_s +{ + u32 dbga_qad : 7; + u32 reserved0 : 23; + u32 dbga_ns : 1; + u32 dbga_s : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_ra_xpu_cfg_xpu4_dbgar_u +{ + struct ipa_hwio_def_ipa_0_ipa_ra_xpu_cfg_xpu4_dbgar_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_RA_XPU_CFG_XPU4_ESR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_ra_xpu_cfg_xpu4_esr_s +{ + u32 cfgerr : 1; + u32 clerr : 1; + u32 cfgmulti : 1; + u32 clmulti : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_ra_xpu_cfg_xpu4_esr_u +{ + struct ipa_hwio_def_ipa_0_ipa_ra_xpu_cfg_xpu4_esr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_RA_XPU_CFG_XPU4_SYNAR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_ra_xpu_cfg_xpu4_synar0_s +{ + u32 synaddr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_ra_xpu_cfg_xpu4_synar0_u +{ + struct ipa_hwio_def_ipa_0_ipa_ra_xpu_cfg_xpu4_synar0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_RA_XPU_CFG_XPU4_SYNAR1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_ra_xpu_cfg_xpu4_synar1_s +{ + u32 synaddr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_ra_xpu_cfg_xpu4_synar1_u +{ + struct ipa_hwio_def_ipa_0_ipa_ra_xpu_cfg_xpu4_synar1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_ra_xpu_cfg_xpu4_synr0_s +{ + u32 xprotns : 1; + u32 inst : 1; + u32 priv : 1; + u32 req_opc : 4; + u32 reserved0 : 1; + u32 qad : 5; + u32 reserved1 : 2; + u32 len : 8; + u32 ssize : 3; + u32 apudecerr : 1; + u32 qaderr : 1; + u32 burstlen : 1; + u32 ac_cl : 1; + u32 ac_cfg : 1; + u32 ph : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_ra_xpu_cfg_xpu4_synr0_u +{ + struct ipa_hwio_def_ipa_0_ipa_ra_xpu_cfg_xpu4_synr0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_ra_xpu_cfg_xpu4_synr1_s +{ + u32 mid : 8; + u32 pid : 5; + u32 bid : 3; + u32 trtype : 3; + u32 reserved0 : 5; + u32 tid : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_ra_xpu_cfg_xpu4_synr1_u +{ + struct ipa_hwio_def_ipa_0_ipa_ra_xpu_cfg_xpu4_synr1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_RA_XPU_CFG_XPU4_SYNR2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_ra_xpu_cfg_xpu4_synr2_s +{ + u32 dirtyinfo : 1; + u32 cacheallocation : 4; + u32 writethrough : 1; + u32 noallocate : 1; + u32 transient : 1; + u32 memtype : 3; + u32 innercacheable : 1; + u32 redirbits : 4; + u32 atopc : 4; + u32 optrw_en : 1; + u32 cesde : 1; + u32 apnsee : 1; + u32 cfg_owner : 1; + u32 sle : 1; + u32 apsvioe : 1; + u32 reserved0 : 6; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_ra_xpu_cfg_xpu4_synr2_u +{ + struct ipa_hwio_def_ipa_0_ipa_ra_xpu_cfg_xpu4_synr2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_RA_XPU_CFG_XPU4_RGCR0n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_ra_xpu_cfg_xpu4_rgcr0n_s +{ + u32 rgwowp : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_ra_xpu_cfg_xpu4_rgcr0n_u +{ + struct ipa_hwio_def_ipa_0_ipa_ra_xpu_cfg_xpu4_rgcr0n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_RA_XPU_CFG_XPU4_RGCR1n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_ra_xpu_cfg_xpu4_rgcr1n_s +{ + u32 rge : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_ra_xpu_cfg_xpu4_rgcr1n_u +{ + struct ipa_hwio_def_ipa_0_ipa_ra_xpu_cfg_xpu4_rgcr1n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_RA_XPU_CFG_XPU4_RGRDRn +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_ra_xpu_cfg_xpu4_rgrdrn_s +{ + u32 rda_qad : 7; + u32 reserved0 : 23; + u32 rda_ns : 1; + u32 rda_s : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_ra_xpu_cfg_xpu4_rgrdrn_u +{ + struct ipa_hwio_def_ipa_0_ipa_ra_xpu_cfg_xpu4_rgrdrn_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_RA_XPU_CFG_XPU4_RGWRRn +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_ra_xpu_cfg_xpu4_rgwrrn_s +{ + u32 wra_qad : 7; + u32 reserved0 : 23; + u32 wra_ns : 1; + u32 wra_s : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_ra_xpu_cfg_xpu4_rgwrrn_u +{ + struct ipa_hwio_def_ipa_0_ipa_ra_xpu_cfg_xpu4_rgwrrn_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_RA_XPU_CFG_XPU4_QADRGLn +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_ra_xpu_cfg_xpu4_qadrgln_s +{ + u32 rgl_qad : 7; + u32 reserved0 : 23; + u32 rgl_ns : 1; + u32 rgl_s : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_ra_xpu_cfg_xpu4_qadrgln_u +{ + struct ipa_hwio_def_ipa_0_ipa_ra_xpu_cfg_xpu4_qadrgln_s def; + u32 value; +}; + +/*---------------------------------------------------------------------------- + * MODULE: IPA_0_IPA_RA_XPU_SB_IPA_RA_XPU4_SB + *--------------------------------------------------------------------------*/ + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_RA_XPU_SB_RA_XPU_SIDEBAND_STATIC_SLE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_ra_xpu_sb_ra_xpu_sideband_static_sle_s +{ + u32 set : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_ra_xpu_sb_ra_xpu_sideband_static_sle_u +{ + struct ipa_hwio_def_ipa_0_ipa_ra_xpu_sb_ra_xpu_sideband_static_sle_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_RA_XPU_SB_RA_XPU_SIDEBAND_STATIC +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_ra_xpu_sb_ra_xpu_sideband_static_s +{ + u32 cfgowns : 1; + u32 apnsee : 1; + u32 optrw_en : 1; + u32 cmocesde : 1; + u32 reserved0 : 1; + u32 apsvioe : 1; + u32 reserved1 : 26; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_ra_xpu_sb_ra_xpu_sideband_static_u +{ + struct ipa_hwio_def_ipa_0_ipa_ra_xpu_sb_ra_xpu_sideband_static_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_IPA_RA_XPU_SB_RA_XPU_SIDEBAND_STATIC_SLE_WAS_WRITTEN +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_ipa_ra_xpu_sb_ra_xpu_sideband_static_sle_was_written_s +{ + u32 val : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_ipa_ra_xpu_sb_ra_xpu_sideband_static_sle_was_written_u +{ + struct ipa_hwio_def_ipa_0_ipa_ra_xpu_sb_ra_xpu_sideband_static_sle_was_written_s def; + u32 value; +}; + +/*---------------------------------------------------------------------------- + * MODULE: IPA_0_GSI_TOP + *--------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------- + * MODULE: IPA_0_GSI_TOP_GSI + *--------------------------------------------------------------------------*/ + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_cfg_s +{ + u32 gsi_enable : 1; + u32 mcs_enable : 1; + u32 double_mcs_clk_freq : 1; + u32 uc_is_mcs : 1; + u32 gsi_pwr_clps : 1; + u32 bp_mtrix_disable : 1; + u32 reserved0 : 2; + u32 sleep_clk_div : 4; + u32 reserved1 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_cfg_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_MANAGER_MCS_CODE_VER +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_manager_mcs_code_ver_s +{ + u32 ver : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_manager_mcs_code_ver_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_manager_mcs_code_ver_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_ZEROS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_zeros_s +{ + u32 zeros : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_zeros_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_zeros_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_PERIPH_BASE_ADDR_LSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_periph_base_addr_lsb_s +{ + u32 base_addr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_periph_base_addr_lsb_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_periph_base_addr_lsb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_PERIPH_BASE_ADDR_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_periph_base_addr_msb_s +{ + u32 base_addr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_periph_base_addr_msb_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_periph_base_addr_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_CGC_CTRL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_cgc_ctrl_s +{ + u32 region_1_hw_cgc_en : 1; + u32 region_2_hw_cgc_en : 1; + u32 region_3_hw_cgc_en : 1; + u32 region_4_hw_cgc_en : 1; + u32 region_5_hw_cgc_en : 1; + u32 region_6_hw_cgc_en : 1; + u32 region_7_hw_cgc_en : 1; + u32 region_8_hw_cgc_en : 1; + u32 region_9_hw_cgc_en : 1; + u32 region_10_hw_cgc_en : 1; + u32 region_11_hw_cgc_en : 1; + u32 region_12_hw_cgc_en : 1; + u32 region_13_hw_cgc_en : 1; + u32 region_14_hw_cgc_en : 1; + u32 region_15_hw_cgc_en : 1; + u32 region_16_hw_cgc_en : 1; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_cgc_ctrl_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_cgc_ctrl_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_MOQA_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_moqa_cfg_s +{ + u32 client_req_prio : 8; + u32 client_oord : 8; + u32 client_oowr : 8; + u32 reserved0 : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_moqa_cfg_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_moqa_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_REE_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_ree_cfg_s +{ + u32 move_to_esc_clr_mode_trsh : 1; + u32 channel_empty_int_enable : 1; + u32 reserved0 : 6; + u32 max_burst_size : 8; + u32 reserved1 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_ree_cfg_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_ree_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_PERIPH_PENDING_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_periph_pending_k_s +{ + u32 chid_bit_map : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_periph_pending_k_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_periph_pending_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_MSI_CACHEATTR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_msi_cacheattr_s +{ + u32 ashared : 1; + u32 ainnershared : 1; + u32 anoallocate : 1; + u32 atransient : 1; + u32 areqpriority : 2; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_msi_cacheattr_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_msi_cacheattr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_EVENT_CACHEATTR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_event_cacheattr_s +{ + u32 ashared : 1; + u32 ainnershared : 1; + u32 anoallocate : 1; + u32 atransient : 1; + u32 areqpriority : 2; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_event_cacheattr_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_event_cacheattr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_DATA_CACHEATTR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_data_cacheattr_s +{ + u32 ashared : 1; + u32 ainnershared : 1; + u32 anoallocate : 1; + u32 atransient : 1; + u32 areqpriority : 2; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_data_cacheattr_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_data_cacheattr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_TRE_CACHEATTR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_tre_cacheattr_s +{ + u32 ashared : 1; + u32 ainnershared : 1; + u32 anoallocate : 1; + u32 atransient : 1; + u32 areqpriority : 2; + u32 reserved0 : 26; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_tre_cacheattr_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_tre_cacheattr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_IC_INT_WEIGHT_REE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ic_int_weight_ree_s +{ + u32 stop_ch_comp_int_weight : 4; + u32 new_re_int_weight : 4; + u32 ch_empty_int_weight : 4; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ic_int_weight_ree_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ic_int_weight_ree_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_IC_INT_WEIGHT_EVT_ENG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ic_int_weight_evt_eng_s +{ + u32 evnt_eng_int_weight : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ic_int_weight_evt_eng_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ic_int_weight_evt_eng_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_IC_INT_WEIGHT_INT_ENG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ic_int_weight_int_eng_s +{ + u32 int_eng_int_weight : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ic_int_weight_int_eng_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ic_int_weight_int_eng_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_IC_INT_WEIGHT_CSR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ic_int_weight_csr_s +{ + u32 ch_cmd_int_weight : 4; + u32 ee_generic_int_weight : 4; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ic_int_weight_csr_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ic_int_weight_csr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_IC_INT_WEIGHT_TLV_ENG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ic_int_weight_tlv_eng_s +{ + u32 tlv_0_int_weight : 4; + u32 tlv_1_int_weight : 4; + u32 tlv_2_int_weight : 4; + u32 ch_not_full_int_weight : 4; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ic_int_weight_tlv_eng_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ic_int_weight_tlv_eng_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_IC_INT_WEIGHT_TIMER_ENG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ic_int_weight_timer_eng_s +{ + u32 timer_int_weight : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ic_int_weight_timer_eng_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ic_int_weight_timer_eng_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_IC_INT_WEIGHT_DB_ENG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ic_int_weight_db_eng_s +{ + u32 new_db_int_weight : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ic_int_weight_db_eng_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ic_int_weight_db_eng_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_IC_INT_WEIGHT_RD_WR_ENG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ic_int_weight_rd_wr_eng_s +{ + u32 read_int_weight : 4; + u32 write_int_weight : 4; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ic_int_weight_rd_wr_eng_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ic_int_weight_rd_wr_eng_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_IC_INT_WEIGHT_UCONTROLLER_ENG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ic_int_weight_ucontroller_eng_s +{ + u32 ucontroller_gp_int_weight : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ic_int_weight_ucontroller_eng_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ic_int_weight_ucontroller_eng_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_LOW_LATENCY_ARB_WEIGHT +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_low_latency_arb_weight_s +{ + u32 ll_weight : 6; + u32 reserved0 : 2; + u32 non_ll_weight : 6; + u32 reserved1 : 2; + u32 ll_non_ll_fix_priority : 1; + u32 reserved2 : 15; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_low_latency_arb_weight_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_low_latency_arb_weight_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_MANAGER_EE_QOS_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_manager_ee_qos_n_s +{ + u32 ee_prio : 2; + u32 reserved0 : 6; + u32 max_ch_alloc : 8; + u32 max_ev_alloc : 8; + u32 reserved1 : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_manager_ee_qos_n_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_manager_ee_qos_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_shram_ptr_ch_cntxt_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_shram_ptr_ch_cntxt_base_addr_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_shram_ptr_ch_cntxt_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_shram_ptr_ev_cntxt_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_shram_ptr_ev_cntxt_base_addr_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_shram_ptr_ev_cntxt_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_shram_ptr_re_storage_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_shram_ptr_re_storage_base_addr_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_shram_ptr_re_storage_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_shram_ptr_re_esc_buf_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_shram_ptr_re_esc_buf_base_addr_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_shram_ptr_re_esc_buf_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_shram_ptr_ee_scrach_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_shram_ptr_ee_scrach_base_addr_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_shram_ptr_ee_scrach_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_shram_ptr_func_stack_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_shram_ptr_func_stack_base_addr_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_shram_ptr_func_stack_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_shram_ptr_mcs_scratch_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_shram_ptr_mcs_scratch_base_addr_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_shram_ptr_mcs_scratch_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_shram_ptr_mcs_scratch1_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_shram_ptr_mcs_scratch1_base_addr_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_shram_ptr_mcs_scratch1_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_shram_ptr_mcs_scratch2_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_shram_ptr_mcs_scratch2_base_addr_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_shram_ptr_mcs_scratch2_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH3_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_shram_ptr_mcs_scratch3_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_shram_ptr_mcs_scratch3_base_addr_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_shram_ptr_mcs_scratch3_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_SHRAM_PTR_CH_VP_TRANS_TABLE_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_shram_ptr_ch_vp_trans_table_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_shram_ptr_ch_vp_trans_table_base_addr_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_shram_ptr_ch_vp_trans_table_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_SHRAM_PTR_EV_VP_TRANS_TABLE_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_shram_ptr_ev_vp_trans_table_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_shram_ptr_ev_vp_trans_table_base_addr_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_shram_ptr_ev_vp_trans_table_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_SHRAM_PTR_USER_INFO_DATA_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_shram_ptr_user_info_data_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_shram_ptr_user_info_data_base_addr_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_shram_ptr_user_info_data_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_SHRAM_PTR_EE_CMD_FIFO_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_shram_ptr_ee_cmd_fifo_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_shram_ptr_ee_cmd_fifo_base_addr_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_shram_ptr_ee_cmd_fifo_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_SHRAM_PTR_CH_CMD_FIFO_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_shram_ptr_ch_cmd_fifo_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_shram_ptr_ch_cmd_fifo_base_addr_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_shram_ptr_ch_cmd_fifo_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_SHRAM_PTR_EVE_ED_STORAGE_BASE_ADDR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_shram_ptr_eve_ed_storage_base_addr_s +{ + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_shram_ptr_eve_ed_storage_base_addr_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_shram_ptr_eve_ed_storage_base_addr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_CMD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_ch_cmd_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_ch_cmd_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_ch_cmd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_ee_generic_cmd_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_ee_generic_cmd_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_ee_generic_cmd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_IRAM_PTR_TLV_CH_NOT_FULL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_tlv_ch_not_full_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_tlv_ch_not_full_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_tlv_ch_not_full_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_IRAM_PTR_MSI_DB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_msi_db_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_msi_db_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_msi_db_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_DB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_ch_db_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_ch_db_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_ch_db_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_IRAM_PTR_EV_DB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_ev_db_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_ev_db_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_ev_db_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_IRAM_PTR_NEW_RE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_new_re_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_new_re_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_new_re_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_ch_dis_comp_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_ch_dis_comp_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_ch_dis_comp_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_ch_empty_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_ch_empty_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_ch_empty_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_event_gen_comp_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_event_gen_comp_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_event_gen_comp_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_periph_if_tlv_in_0_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_periph_if_tlv_in_0_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_periph_if_tlv_in_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_periph_if_tlv_in_2_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_periph_if_tlv_in_2_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_periph_if_tlv_in_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_periph_if_tlv_in_1_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_periph_if_tlv_in_1_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_periph_if_tlv_in_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_timer_expired_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_timer_expired_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_timer_expired_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_write_eng_comp_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_write_eng_comp_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_write_eng_comp_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_read_eng_comp_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_read_eng_comp_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_read_eng_comp_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_uc_gp_int_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_uc_gp_int_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_uc_gp_int_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPED +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_int_mod_stoped_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_int_mod_stoped_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_int_mod_stoped_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_IRAM_PTR_INT_NOTIFY_MCS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_int_notify_mcs_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_int_notify_mcs_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_int_notify_mcs_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_INST_RAM_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_inst_ram_n_s +{ + u32 inst_byte_0 : 8; + u32 inst_byte_1 : 8; + u32 inst_byte_2 : 8; + u32 inst_byte_3 : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_inst_ram_n_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_inst_ram_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_SHRAM_n +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_shram_n_s +{ + u32 shram : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_shram_n_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_shram_n_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_map_ee_n_ch_k_vp_table_s +{ + u32 phy_ch : 8; + u32 valid : 1; + u32 reserved0 : 23; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_map_ee_n_ch_k_vp_table_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_map_ee_n_ch_k_vp_table_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_TEST_BUS_SEL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_test_bus_sel_s +{ + u32 gsi_testbus_sel : 8; + u32 reserved0 : 8; + u32 gsi_hw_events_sel : 4; + u32 reserved1 : 12; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_test_bus_sel_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_test_bus_sel_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_TEST_BUS_REG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_test_bus_reg_s +{ + u32 gsi_testbus_reg : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_test_bus_reg_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_test_bus_reg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_DEBUG_BUSY_REG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_debug_busy_reg_s +{ + u32 csr_busy : 1; + u32 ree_busy : 1; + u32 mcs_busy : 1; + u32 timer_busy : 1; + u32 rd_wr_busy : 1; + u32 ev_eng_busy : 1; + u32 int_eng_busy : 1; + u32 ree_pwr_clps_busy : 1; + u32 db_eng_busy : 1; + u32 dbg_cnt_busy : 1; + u32 uc_busy : 1; + u32 ic_busy : 1; + u32 sdma_busy : 1; + u32 reserved0 : 19; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_debug_busy_reg_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_debug_busy_reg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_DEBUG_EVENT_PENDING_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_debug_event_pending_k_s +{ + u32 chid_bit_map : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_debug_event_pending_k_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_debug_event_pending_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_DEBUG_TIMER_PENDING_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_debug_timer_pending_k_s +{ + u32 chid_bit_map : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_debug_timer_pending_k_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_debug_timer_pending_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_debug_rd_wr_pending_k_s +{ + u32 chid_bit_map : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_debug_rd_wr_pending_k_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_debug_rd_wr_pending_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_SPARE_REG_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_spare_reg_1_s +{ + u32 fix_ieob_wrong_msk_disable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_spare_reg_1_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_spare_reg_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_DEBUG_PC_FROM_SW +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_debug_pc_from_sw_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_debug_pc_from_sw_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_debug_pc_from_sw_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_DEBUG_SW_STALL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_debug_sw_stall_s +{ + u32 mcs_stall : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_debug_sw_stall_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_debug_sw_stall_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_debug_pc_for_debug_s +{ + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_debug_pc_for_debug_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_debug_pc_for_debug_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_SEL +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_debug_qsb_log_sel_s +{ + u32 sel_write : 1; + u32 reserved0 : 7; + u32 sel_tid : 8; + u32 sel_mid : 8; + u32 reserved1 : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_debug_qsb_log_sel_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_debug_qsb_log_sel_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_CLR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_debug_qsb_log_clr_s +{ + u32 log_clr : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_debug_qsb_log_clr_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_debug_qsb_log_clr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_debug_qsb_log_err_trns_id_s +{ + u32 err_write : 1; + u32 reserved0 : 7; + u32 err_tid : 8; + u32 err_mid : 8; + u32 err_saved : 1; + u32 reserved1 : 7; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_debug_qsb_log_err_trns_id_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_debug_qsb_log_err_trns_id_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_debug_qsb_log_0_s +{ + u32 addr_31_0 : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_debug_qsb_log_0_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_debug_qsb_log_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_debug_qsb_log_1_s +{ + u32 addr_43_32 : 12; + u32 ainnershared : 1; + u32 anoallocate : 1; + u32 ashared : 1; + u32 acacheable : 1; + u32 atransient : 1; + u32 aooord : 1; + u32 aooowr : 1; + u32 reserved0 : 1; + u32 alen : 4; + u32 asize : 4; + u32 areqpriority : 4; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_debug_qsb_log_1_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_debug_qsb_log_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_debug_qsb_log_2_s +{ + u32 ammusid : 12; + u32 amemtype : 4; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_debug_qsb_log_2_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_debug_qsb_log_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_debug_qsb_log_last_misc_idn_s +{ + u32 addr_20_0 : 21; + u32 write : 1; + u32 tid : 5; + u32 mid : 5; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_debug_qsb_log_last_misc_idn_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_debug_qsb_log_last_misc_idn_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_DEBUG_SW_RF_n_WRITE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_debug_sw_rf_n_write_s +{ + u32 data_in : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_debug_sw_rf_n_write_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_debug_sw_rf_n_write_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_DEBUG_SW_RF_n_READ +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_debug_sw_rf_n_read_s +{ + u32 rf_reg : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_debug_sw_rf_n_read_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_debug_sw_rf_n_read_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_DEBUG_COUNTER_CFGn +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_debug_counter_cfgn_s +{ + u32 enable : 1; + u32 stop_at_wrap_arnd : 1; + u32 clr_at_read : 1; + u32 evnt_type : 5; + u32 ee : 4; + u32 virtual_chnl : 8; + u32 chain : 1; + u32 reserved0 : 11; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_debug_counter_cfgn_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_debug_counter_cfgn_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_DEBUG_COUNTERn +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_debug_countern_s +{ + u32 counter_value : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_debug_countern_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_debug_countern_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_DEBUG_SW_MSK_REG_n_SEC_k_WR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_debug_sw_msk_reg_n_sec_k_wr_s +{ + u32 data_in : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_debug_sw_msk_reg_n_sec_k_wr_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_debug_sw_msk_reg_n_sec_k_wr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_debug_sw_msk_reg_n_sec_k_rd_s +{ + u32 msk_reg : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_debug_sw_msk_reg_n_sec_k_rd_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_debug_sw_msk_reg_n_sec_k_rd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_debug_ee_n_ch_k_vp_table_s +{ + u32 phy_ch : 8; + u32 valid : 1; + u32 reserved0 : 23; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_debug_ee_n_ch_k_vp_table_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_debug_ee_n_ch_k_vp_table_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_debug_ee_n_ev_k_vp_table_s +{ + u32 phy_ev_ch : 8; + u32 valid : 1; + u32 reserved0 : 23; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_debug_ee_n_ev_k_vp_table_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_debug_ee_n_ev_k_vp_table_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_DEBUG_REE_PREFETCH_BUF_CH_ID +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_debug_ree_prefetch_buf_ch_id_s +{ + u32 prefetch_buf_ch_id : 8; + u32 reserved0 : 24; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_debug_ree_prefetch_buf_ch_id_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_debug_ree_prefetch_buf_ch_id_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_DEBUG_REE_PREFETCH_BUF_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_debug_ree_prefetch_buf_status_s +{ + u32 prefetch_buf_status : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_debug_ree_prefetch_buf_status_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_debug_ree_prefetch_buf_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_MCS_PROFILING_BP_CNT_LSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_bp_cnt_lsb_s +{ + u32 bp_cnt_lsb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_bp_cnt_lsb_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_bp_cnt_lsb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_MCS_PROFILING_BP_CNT_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_bp_cnt_msb_s +{ + u32 bp_cnt_msb : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_bp_cnt_msb_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_bp_cnt_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_bp_and_pending_cnt_lsb_s +{ + u32 bp_and_pending_cnt_lsb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_bp_and_pending_cnt_lsb_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_bp_and_pending_cnt_lsb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_bp_and_pending_cnt_msb_s +{ + u32 bp_and_pending_cnt_msb : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_bp_and_pending_cnt_msb_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_bp_and_pending_cnt_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_mcs_busy_cnt_lsb_s +{ + u32 mcs_busy_cnt_lsb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_mcs_busy_cnt_lsb_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_mcs_busy_cnt_lsb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_mcs_busy_cnt_msb_s +{ + u32 mcs_busy_cnt_msb : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_mcs_busy_cnt_msb_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_mcs_busy_cnt_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_mcs_idle_cnt_lsb_s +{ + u32 mcs_idle_cnt_lsb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_mcs_idle_cnt_lsb_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_mcs_idle_cnt_lsb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_mcs_idle_cnt_msb_s +{ + u32 mcs_idle_cnt_msb : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_mcs_idle_cnt_msb_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_mcs_idle_cnt_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_cntxt_0_s +{ + u32 chtype_protocol : 7; + u32 chtype_dir : 1; + u32 ee : 4; + u32 chid : 8; + u32 chstate : 4; + u32 element_size : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_cntxt_0_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_cntxt_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_cntxt_1_s +{ + u32 r_length : 24; + u32 erindex : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_cntxt_1_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_cntxt_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_cntxt_2_s +{ + u32 r_base_addr_lsbs : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_cntxt_2_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_cntxt_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_cntxt_3_s +{ + u32 r_base_addr_msbs : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_cntxt_3_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_cntxt_3_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_cntxt_4_s +{ + u32 read_ptr_lsb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_cntxt_4_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_cntxt_4_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_cntxt_5_s +{ + u32 read_ptr_msb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_cntxt_5_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_cntxt_5_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_cntxt_6_s +{ + u32 write_ptr_lsb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_cntxt_6_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_cntxt_6_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_cntxt_7_s +{ + u32 write_ptr_msb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_cntxt_7_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_cntxt_7_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_GSI_CH_k_CNTXT_8 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_cntxt_8_s +{ + u32 db_msi_data : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_cntxt_8_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_cntxt_8_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_GSI_CH_k_ELEM_SIZE_SHIFT +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_elem_size_shift_s +{ + u32 elem_size_shift : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_elem_size_shift_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_elem_size_shift_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_GSI_CH_k_CH_ALMST_EMPTY_THRSHOLD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_ch_almst_empty_thrshold_s +{ + u32 ch_almst_empty_thrshold : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_ch_almst_empty_thrshold_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_ch_almst_empty_thrshold_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_re_fetch_read_ptr_s +{ + u32 read_ptr : 24; + u32 reserved0 : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_re_fetch_read_ptr_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_re_fetch_read_ptr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_re_fetch_write_ptr_s +{ + u32 re_intr_db : 24; + u32 reserved0 : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_re_fetch_write_ptr_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_re_fetch_write_ptr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_GSI_CH_k_QOS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_qos_s +{ + u32 wrr_weight : 4; + u32 reserved0 : 4; + u32 max_prefetch : 1; + u32 use_db_eng : 1; + u32 prefetch_mode : 4; + u32 reserved1 : 2; + u32 empty_lvl_thrshold : 8; + u32 db_in_bytes : 1; + u32 low_latency_en : 1; + u32 reserved2 : 6; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_qos_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_qos_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_scratch_0_s +{ + u32 scratch : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_scratch_0_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_scratch_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_scratch_1_s +{ + u32 scratch : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_scratch_1_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_scratch_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_scratch_2_s +{ + u32 scratch : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_scratch_2_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_scratch_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_scratch_3_s +{ + u32 scratch : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_scratch_3_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_scratch_3_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_4 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_scratch_4_s +{ + u32 scratch : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_scratch_4_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_scratch_4_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_5 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_scratch_5_s +{ + u32 scratch : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_scratch_5_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_scratch_5_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_6 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_scratch_6_s +{ + u32 scratch : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_scratch_6_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_scratch_6_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_7 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_scratch_7_s +{ + u32 scratch : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_scratch_7_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_scratch_7_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_8 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_scratch_8_s +{ + u32 scratch : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_scratch_8_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_scratch_8_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_9 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_scratch_9_s +{ + u32 scratch : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_scratch_9_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_scratch_9_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_db_eng_write_ptr_s +{ + u32 last_db_2_mcs : 16; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_db_eng_write_ptr_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_db_eng_write_ptr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_k_cntxt_0_s +{ + u32 chtype : 7; + u32 intype : 1; + u32 evchid : 8; + u32 ee : 4; + u32 chstate : 4; + u32 element_size : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_k_cntxt_0_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_k_cntxt_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_k_cntxt_1_s +{ + u32 r_length : 24; + u32 reserved0 : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_k_cntxt_1_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_k_cntxt_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_k_cntxt_2_s +{ + u32 r_base_addr_lsbs : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_k_cntxt_2_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_k_cntxt_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_3 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_k_cntxt_3_s +{ + u32 r_base_addr_msbs : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_k_cntxt_3_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_k_cntxt_3_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_4 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_k_cntxt_4_s +{ + u32 read_ptr_lsb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_k_cntxt_4_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_k_cntxt_4_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_5 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_k_cntxt_5_s +{ + u32 read_ptr_msb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_k_cntxt_5_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_k_cntxt_5_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_6 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_k_cntxt_6_s +{ + u32 write_ptr_lsb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_k_cntxt_6_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_k_cntxt_6_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_7 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_k_cntxt_7_s +{ + u32 write_ptr_msb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_k_cntxt_7_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_k_cntxt_7_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_8 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_k_cntxt_8_s +{ + u32 int_modt : 16; + u32 int_modc : 8; + u32 int_mod_cnt : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_k_cntxt_8_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_k_cntxt_8_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_9 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_k_cntxt_9_s +{ + u32 intvec : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_k_cntxt_9_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_k_cntxt_9_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_10 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_k_cntxt_10_s +{ + u32 msi_addr_lsb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_k_cntxt_10_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_k_cntxt_10_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_11 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_k_cntxt_11_s +{ + u32 msi_addr_msb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_k_cntxt_11_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_k_cntxt_11_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_12 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_k_cntxt_12_s +{ + u32 rp_update_addr_lsb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_k_cntxt_12_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_k_cntxt_12_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_EV_CH_k_CNTXT_13 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_k_cntxt_13_s +{ + u32 rp_update_addr_msb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_k_cntxt_13_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_k_cntxt_13_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_EV_CH_k_ELEM_SIZE_SHIFT +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_k_elem_size_shift_s +{ + u32 elem_size_shift : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_k_elem_size_shift_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_k_elem_size_shift_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_k_scratch_0_s +{ + u32 scratch : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_k_scratch_0_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_k_scratch_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_k_scratch_1_s +{ + u32 scratch : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_k_scratch_1_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_k_scratch_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_EV_CH_k_SCRATCH_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_k_scratch_2_s +{ + u32 scratch : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_k_scratch_2_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_k_scratch_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_doorbell_0_s +{ + u32 write_ptr_lsb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_doorbell_0_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_doorbell_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_doorbell_1_s +{ + u32 write_ptr_msb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_doorbell_1_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_k_doorbell_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_EV_CH_k_DOORBELL_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_k_doorbell_0_s +{ + u32 write_ptr_lsb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_k_doorbell_0_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_k_doorbell_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_EV_CH_k_DOORBELL_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_k_doorbell_1_s +{ + u32 write_ptr_msb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_k_doorbell_1_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_k_doorbell_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_GSI_STATUS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_status_s +{ + u32 enabled : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_status_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_status_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_GSI_CH_CMD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_cmd_s +{ + u32 chid : 8; + u32 reserved0 : 16; + u32 opcode : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_cmd_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ch_cmd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_EV_CH_CMD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_cmd_s +{ + u32 chid : 8; + u32 reserved0 : 16; + u32 opcode : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_cmd_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_ev_ch_cmd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_GSI_EE_GENERIC_CMD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ee_generic_cmd_s +{ + u32 opcode : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ee_generic_cmd_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_ee_generic_cmd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_hw_param_0_s +{ + u32 gsi_ev_ch_num : 8; + u32 gsi_ch_num : 8; + u32 num_ees : 5; + u32 periph_conf_addr_bus_w : 5; + u32 periph_sec_grp : 5; + u32 use_axi_m : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_hw_param_0_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_hw_param_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_hw_param_1_s +{ + u32 gsi_m_data_bus_w : 8; + u32 gsi_num_qad : 4; + u32 gsi_nonsec_en : 4; + u32 gsi_sec_en : 1; + u32 gsi_vmidacr_en : 1; + u32 gsi_qrib_en : 1; + u32 gsi_use_xpu : 1; + u32 gsi_num_timers : 5; + u32 gsi_use_bp_mtrix : 1; + u32 gsi_use_db_eng : 1; + u32 gsi_use_uc_if : 1; + u32 gsi_escape_buf_only : 1; + u32 gsi_simple_rd_wr : 1; + u32 gsi_blk_int_access_region_1_en : 1; + u32 gsi_blk_int_access_region_2_en : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_hw_param_1_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_hw_param_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_2 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_hw_param_2_s +{ + u32 gsi_num_ch_per_ee : 8; + u32 gsi_iram_size : 5; + u32 gsi_ch_pend_translate : 1; + u32 gsi_ch_full_logic : 1; + u32 gsi_use_sdma : 1; + u32 gsi_sdma_n_int : 3; + u32 gsi_sdma_max_burst : 8; + u32 gsi_sdma_n_iovec : 3; + u32 gsi_use_rd_wr_eng : 1; + u32 gsi_use_inter_ee : 1; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_hw_param_2_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_hw_param_2_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_GSI_MCS_CODE_VER +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_mcs_code_ver_s +{ + u32 ver : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_mcs_code_ver_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_mcs_code_ver_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_3 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_hw_param_3_s +{ + u32 gsi_sdma_max_os_rd : 4; + u32 gsi_sdma_max_os_wr : 4; + u32 gsi_num_prefetch_bufs : 4; + u32 gsi_m_addr_bus_w : 8; + u32 gsi_ree_max_burst_len : 5; + u32 gsi_use_irom : 1; + u32 gsi_use_vir_ch_if : 1; + u32 gsi_use_sleep_clk_div : 1; + u32 gsi_use_db_msi_mode : 1; + u32 reserved0 : 3; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_hw_param_3_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_hw_param_3_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_GSI_HW_PARAM_4 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_hw_param_4_s +{ + u32 gsi_num_ev_per_ee : 8; + u32 gsi_iram_protcol_cnt : 8; + u32 reserved0 : 16; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_hw_param_4_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_gsi_hw_param_4_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_CNTXT_TYPE_IRQ +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_type_irq_s +{ + u32 ch_ctrl : 1; + u32 ev_ctrl : 1; + u32 glob_ee : 1; + u32 ieob : 1; + u32 inter_ee_ch_ctrl : 1; + u32 inter_ee_ev_ctrl : 1; + u32 general : 1; + u32 reserved0 : 25; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_type_irq_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_type_irq_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_type_irq_msk_s +{ + u32 ch_ctrl : 1; + u32 ev_ctrl : 1; + u32 glob_ee : 1; + u32 ieob : 1; + u32 inter_ee_ch_ctrl : 1; + u32 inter_ee_ev_ctrl : 1; + u32 general : 1; + u32 reserved0 : 25; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_type_irq_msk_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_type_irq_msk_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_src_gsi_ch_irq_k_s +{ + u32 gsi_ch_bit_map : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_src_gsi_ch_irq_k_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_src_gsi_ch_irq_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_src_gsi_ch_irq_msk_k_s +{ + u32 gsi_ch_bit_map_msk : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_src_gsi_ch_irq_msk_k_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_src_gsi_ch_irq_msk_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_src_gsi_ch_irq_clr_k_s +{ + u32 gsi_ch_bit_map : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_src_gsi_ch_irq_clr_k_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_src_gsi_ch_irq_clr_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_src_ev_ch_irq_k_s +{ + u32 ev_ch_bit_map : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_src_ev_ch_irq_k_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_src_ev_ch_irq_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_src_ev_ch_irq_msk_k_s +{ + u32 ev_ch_bit_map_msk : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_src_ev_ch_irq_msk_k_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_src_ev_ch_irq_msk_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_src_ev_ch_irq_clr_k_s +{ + u32 ev_ch_bit_map : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_src_ev_ch_irq_clr_k_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_src_ev_ch_irq_clr_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_src_ieob_irq_k_s +{ + u32 ev_ch_bit_map : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_src_ieob_irq_k_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_src_ieob_irq_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_src_ieob_irq_msk_k_s +{ + u32 ev_ch_bit_map_msk : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_src_ieob_irq_msk_k_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_src_ieob_irq_msk_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_src_ieob_irq_clr_k_s +{ + u32 ev_ch_bit_map : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_src_ieob_irq_clr_k_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_src_ieob_irq_clr_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_glob_irq_stts_s +{ + u32 error_int : 1; + u32 gp_int1 : 1; + u32 gp_int2 : 1; + u32 gp_int3 : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_glob_irq_stts_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_glob_irq_stts_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_EN +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_glob_irq_en_s +{ + u32 error_int : 1; + u32 gp_int1 : 1; + u32 gp_int2 : 1; + u32 gp_int3 : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_glob_irq_en_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_glob_irq_en_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_CLR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_glob_irq_clr_s +{ + u32 error_int : 1; + u32 gp_int1 : 1; + u32 gp_int2 : 1; + u32 gp_int3 : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_glob_irq_clr_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_glob_irq_clr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_gsi_irq_stts_s +{ + u32 gsi_break_point : 1; + u32 gsi_bus_error : 1; + u32 gsi_cmd_fifo_ovrflow : 1; + u32 gsi_mcs_stack_ovrflow : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_gsi_irq_stts_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_gsi_irq_stts_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_CNTXT_GSI_IRQ_EN +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_gsi_irq_en_s +{ + u32 gsi_break_point : 1; + u32 gsi_bus_error : 1; + u32 gsi_cmd_fifo_ovrflow : 1; + u32 gsi_mcs_stack_ovrflow : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_gsi_irq_en_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_gsi_irq_en_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_CNTXT_GSI_IRQ_CLR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_gsi_irq_clr_s +{ + u32 gsi_break_point : 1; + u32 gsi_bus_error : 1; + u32 gsi_cmd_fifo_ovrflow : 1; + u32 gsi_mcs_stack_ovrflow : 1; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_gsi_irq_clr_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_gsi_irq_clr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_CNTXT_INTSET +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_intset_s +{ + u32 intype : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_intset_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_intset_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_msi_base_lsb_s +{ + u32 msi_addr_lsb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_msi_base_lsb_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_msi_base_lsb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_CNTXT_MSI_BASE_MSB +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_msi_base_msb_s +{ + u32 msi_addr_msb : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_msi_base_msb_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_msi_base_msb_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_CNTXT_INT_VEC +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_int_vec_s +{ + u32 int_vec : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_int_vec_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_int_vec_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_ERROR_LOG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_error_log_s +{ + u32 error_log : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_error_log_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_error_log_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_ERROR_LOG_CLR +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_error_log_clr_s +{ + u32 error_log_clr : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_error_log_clr_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_error_log_clr_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_CNTXT_SCRATCH_0 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_scratch_0_s +{ + u32 scratch : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_scratch_0_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_scratch_0_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_EE_n_CNTXT_SCRATCH_1 +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_scratch_1_s +{ + u32 scratch : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_scratch_1_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_ee_n_cntxt_scratch_1_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_MCS_CFG +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_mcs_cfg_s +{ + u32 mcs_enable : 1; + u32 reserved0 : 31; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_mcs_cfg_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_mcs_cfg_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_TZ_FW_AUTH_LOCK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_tz_fw_auth_lock_s +{ + u32 dis_iram_write : 1; + u32 dis_debug_shram_write : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_tz_fw_auth_lock_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_tz_fw_auth_lock_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_MSA_FW_AUTH_LOCK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_msa_fw_auth_lock_s +{ + u32 dis_iram_write : 1; + u32 dis_debug_shram_write : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_msa_fw_auth_lock_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_msa_fw_auth_lock_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_SP_FW_AUTH_LOCK +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_gsi_sp_fw_auth_lock_s +{ + u32 dis_iram_write : 1; + u32 dis_debug_shram_write : 1; + u32 reserved0 : 30; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_gsi_sp_fw_auth_lock_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_gsi_sp_fw_auth_lock_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_INTER_EE_n_ORIGINATOR_EE +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_inter_ee_n_originator_ee_s +{ + u32 ee_number : 4; + u32 reserved0 : 28; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_inter_ee_n_originator_ee_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_inter_ee_n_originator_ee_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_INTER_EE_n_GSI_CH_CMD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_inter_ee_n_gsi_ch_cmd_s +{ + u32 chid : 8; + u32 reserved0 : 16; + u32 opcode : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_inter_ee_n_gsi_ch_cmd_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_inter_ee_n_gsi_ch_cmd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_INTER_EE_n_EV_CH_CMD +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_inter_ee_n_ev_ch_cmd_s +{ + u32 chid : 8; + u32 reserved0 : 16; + u32 opcode : 8; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_inter_ee_n_ev_ch_cmd_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_inter_ee_n_ev_ch_cmd_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_inter_ee_n_src_gsi_ch_irq_k_s +{ + u32 gsi_ch_bit_map : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_inter_ee_n_src_gsi_ch_irq_k_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_inter_ee_n_src_gsi_ch_irq_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_inter_ee_n_src_gsi_ch_irq_msk_k_s +{ + u32 gsi_ch_bit_map_msk : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_inter_ee_n_src_gsi_ch_irq_msk_k_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_inter_ee_n_src_gsi_ch_irq_msk_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_inter_ee_n_src_gsi_ch_irq_clr_k_s +{ + u32 gsi_ch_bit_map : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_inter_ee_n_src_gsi_ch_irq_clr_k_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_inter_ee_n_src_gsi_ch_irq_clr_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_inter_ee_n_src_ev_ch_irq_k_s +{ + u32 ev_ch_bit_map : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_inter_ee_n_src_ev_ch_irq_k_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_inter_ee_n_src_ev_ch_irq_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_MSK_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_inter_ee_n_src_ev_ch_irq_msk_k_s +{ + u32 ev_ch_bit_map_msk : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_inter_ee_n_src_ev_ch_irq_msk_k_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_inter_ee_n_src_ev_ch_irq_msk_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of register: IPA_0_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_CLR_k +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_ipa_0_gsi_top_inter_ee_n_src_ev_ch_irq_clr_k_s +{ + u32 ev_ch_bit_map : 32; +}; + +/* Union definition of register */ +union ipa_hwio_def_ipa_0_gsi_top_inter_ee_n_src_ev_ch_irq_clr_k_u +{ + struct ipa_hwio_def_ipa_0_gsi_top_inter_ee_n_src_ev_ch_irq_clr_k_s def; + u32 value; +}; + +/*===========================================================================*/ +/*! + @brief Bit Field definition of fc_stats +*/ +/*===========================================================================*/ +/* Structure definition of register */ +struct ipa_hwio_def_fc_stats_state_s +{ + u32 reserved0 : 16; + u32 flow_control : 1; + u32 flow_control_primary : 1; + u32 flow_control_secondary : 1; + u32 pending_flow_control : 1; + u32 reserved1 : 12; +}; + +/* Union definition of register */ +union ipa_hwio_def_fc_stats_state_u +{ + struct ipa_hwio_def_fc_stats_state_s def; + u32 value; +}; + +#endif /* __IPA_HWIO_DEF_H__ */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.5/ipa_pkt_cntxt.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.5/ipa_pkt_cntxt.h new file mode 100644 index 0000000000..c11f3c0c8f --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.5/ipa_pkt_cntxt.h @@ -0,0 +1,316 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ +#if !defined(_IPA_PKT_CNTXT_H_) +#define _IPA_PKT_CNTXT_H_ + +#define IPA_HW_PKT_CTNTX_MAX 0x10 + +/* + * Packet Context States + */ +enum ipa_hw_pkt_cntxt_state_e { + IPA_HW_PKT_CNTXT_STATE_HFETCHER_INIT = 1, + IPA_HW_PKT_CNTXT_STATE_HFETCHER_DMAR = 2, + IPA_HW_PKT_CNTXT_STATE_H_DCPH = 3, + IPA_HW_PKT_CNTXT_STATE_MULTI_DRBIP = 4, + IPA_HW_PKT_CNTXT_STATE_PKT_PARSER = 5, + IPA_HW_PKT_CNTXT_STATE_FILTER_NAT = 6, + IPA_HW_PKT_CNTXT_STATE_ROUTER = 7, + IPA_HW_PKT_CNTXT_STATE_HDRI = 8, + IPA_HW_PKT_CNTXT_STATE_UCP = 9, + IPA_HW_PKT_CNTXT_STATE_COAL_MASTER = 10, + IPA_HW_PKT_CNTXT_STATE_ENQUEUER = 11, + IPA_HW_PKT_CNTXT_STATE_DFETCHER = 12, + IPA_HW_PKT_CNTXT_STATE_D_DCPH = 13, + IPA_HW_PKT_CNTXT_STATE_DISPATCHER = 14, + IPA_HW_PKT_CNTXT_STATE_TX = 15, + IPA_HW_PKT_CNTXT_STATE_TX_ZLT = 16, + IPA_HW_PKT_CNTXT_STATE_DFETCHER_DMAR = 17, + IPA_HW_PKT_CNTXT_STATE_D_DCPH_2 = 19, + IPA_HW_PKT_CNTXT_STATE_TX_RSRCREL = 20, +}; + +/* + * Packet Context fields as received from VI/Design + */ +struct ipa_pkt_ctntx_s { + u64 opcode : 8; /* Word 0 Bits 0-7 */ + u64 state : 5; /* Word 0 Bits 8-12 */ + u64 stats_disable : 1; /* Word 0 Bit 13 */ + u64 exc_ucp : 1; /* Word 0 Bit 14 */ + u64 tx_pkt_dma_done : 1; /* Word 0 Bit 15 */ + u64 exc_deagg : 1; /* Word 0 Bit 16 */ + u64 exc_pkt_version : 1; /* Word 0 Bit 17 */ + u64 exc_pkt_len : 1; /* Word 0 Bit 18 */ + u64 exc_threshold : 1; /* Word 0 Bit 19 */ + u64 exc_sw : 1; /* Word 0 Bit 20 */ + u64 exc_nat : 1; /* Word 0 Bit 21 */ + u64 exc_frag_miss : 1; /* Word 0 Bit 22 */ + u64 filter_bypass : 1; /* Word 0 Bit 23 */ + u64 router_bypass : 1; /* Word 0 Bit 24 */ + u64 nat_bypass : 1; /* Word 0 Bit 25 */ + u64 hdri_bypass : 1; /* Word 0 Bit 26 */ + u64 dcph_bypass : 1; /* Word 0 Bit 27 */ + u64 security_credentials_select : 1; /* Word 0 Bit 28 */ + u64 dcph_valid : 1; /* Word 0 Bit 29 */ + u64 round_bypass : 1; /* Word 0 Bit 30 */ + u64 bearer_valid : 1; /* Word 0 Bit 31 */ + u64 ucp_on : 1; /* Word 0 Bit 32 */ + u64 replication : 1; /* Word 0 Bit 33 */ + u64 src_status_en : 1; /* Word 0 Bit 34 */ + u64 dest_status_en : 1; /* Word 0 Bit 35 */ + u64 frag_status_en : 1; /* Word 0 Bit 36 */ + u64 eot_dest : 1; /* Word 0 Bit 37 */ + u64 eot_notif : 1; /* Word 0 Bit 38 */ + u64 prev_eot_dest : 1; /* Word 0 Bit 39 */ + u64 l2_len : 9; /* Word 0 Bits 40-48 */ + u64 dispatcher_pass : 1; /* Word 0 Bit 49 */ + u64 ucp_on_for_rts : 1; /* Word 0 Bit 50 */ + u64 exc_hdri : 1; /* Word 0 Bit 51 */ + u64 pkt_parser_bypass : 1; /* Word 0 Bit 52 */ + u64 exc_pipe : 1; /* Word 0 Bit 53 */ + u64 nat_in_hdrs : 1; /* Word 0 Bit 54 */ + u64 rx_flags : 8; /* Word 0 Bits 55-62 */ + u64 not_used_0 : 1; /* Word 0 Bit 63 */ + u64 rx_packet_length : 16; /* Word 1 Bits 0-15 */ + u64 revised_packet_length : 16; /* Word 1 Bits 16-31 */ + u64 frag_en : 1; /* Word 1 Bit 32 */ + u64 frag_bypass : 1; /* Word 1 Bit 33 */ + u64 frag_process : 1; /* Word 1 Bit 34 */ + u64 tx_pkt_transferred : 1; /* Word 1 Bit 35 */ + u64 filter_aggr_force_close : 1; /* Word 1 Bit 36 */ + u64 router_aggr_force_close : 1; /* Word 1 Bit 37 */ + u64 not_used_1 : 2; /* Word 1 Bits 38-39 */ + u64 src_id : 8; /* Word 1 Bits 40-47 */ + u64 src_pipe : 8; /* Word 1 Bits 48-55 */ + u64 dest_pipe : 8; /* Word 1 Bits 56-63 */ + u64 ihl_offset : 6; /* Word 2 Bits 0-5 */ + u64 d_dcph_pass : 1; /* Word 2 Bit 6 */ + u64 not_used_2 : 1; /* Word 2 Bit 7 */ + u64 protocol : 8; /* Word 2 Bits 8-15 */ + u64 tos : 8; /* Word 2 Bits 16-23 */ + u64 id : 16; /* Word 2 Bits 24-39 */ + u64 v6_reserved : 4; /* Word 2 Bits 40-43 */ + u64 ff : 1; /* Word 2 Bit 44 */ + u64 mf : 1; /* Word 2 Bit 45 */ + u64 pkt_is_frag : 1; /* Word 2 Bit 46 */ + u64 cs_disable_trailer_valid_bit : 1; /* Word 2 Bit 47 */ + u64 exc_checksum : 1; /* Word 2 Bit 48 */ + u64 trnseq_0 : 3; /* Word 2 Bits 49-51 */ + u64 trnseq_1 : 3; /* Word 2 Bits 52-54 */ + u64 trnseq_2 : 3; /* Word 2 Bits 55-57 */ + u64 trnseq_3 : 3; /* Word 2 Bits 58-60 */ + u64 trnseq_4 : 3; /* Word 2 Bits 61-63 */ + u64 trnseq_ex_length : 8; /* Word 3 Bits 0-7 */ + u64 trnseq_4_length : 9; /* Word 3 Bits 8-16 */ + u64 trnseq_4_offset : 8; /* Word 3 Bits 17-24 */ + u64 dps_tx_pop_cnt : 2; /* Word 3 Bits 25-26 */ + u64 dps_tx_push_cnt : 2; /* Word 3 Bits 27-28 */ + u64 vol_ic_dcph_cfg : 1; /* Word 3 Bit 29 */ + u64 vol_ic_tag_stts : 1; /* Word 3 Bit 30 */ + u64 vol_ic_pkt_init_ex : 1; /* Word 3 Bit 31 */ + u64 vol_ic_pkt_init : 1; /* Word 3 Bit 32 */ + u64 trnseq_0_preucp : 1; /* Word 3 Bit 33 */ + u64 dest_pipe_overridden_ucp : 1; /* Word 3 Bit 34 */ + u64 force_to_default : 1; /* Word 3 Bit 35 */ + u64 close_vp_before : 1; /* Word 3 Bit 36 */ + u64 vol_ic_eob_bubble : 1; /* Word 3 Bit 37 */ + u64 not_used_3 : 5; /* Word 3 Bits 38-42 */ + u64 maci_bytes_in_trnseq : 1; /* Word 3 Bit 43 */ + u64 drop_drbip : 1; /* Word 3 Bit 44 */ + u64 exc_drbip : 1; /* Word 3 Bit 45 */ + u64 drbip_valid : 1; /* Word 3 Bit 46 */ + u64 tx_pkt_suspended : 1; /* Word 3 Bit 47 */ + u64 rb : 1; /* Word 3 Bit 48 */ + u64 packet_ethernet_parsing_done : 1; /* Word 3 Bit 49 */ + u64 exc_rqos : 1; /* Word 3 Bit 50 */ + u64 not_used_4 : 13; /* Word 3 Bit 51-63 */ + u64 tcp_win_size : 16; /* Word 4 Bits 0-15 */ + u64 trnseq_0_length : 9; /* Word 4 Bits 16-24 */ + u64 trnseq_0_offset : 8; /* Word 4 Bits 25-32 */ + u64 trnseq_1_length : 9; /* Word 4 Bits 33-41 */ + u64 trnseq_1_offset : 8; /* Word 4 Bits 42-49 */ + u64 trnseq_2_length : 9; /* Word 4 Bits 50-58 */ + u64 not_used_5 : 5; /* Word 4 Bits 59-63 */ + u64 trnseq_2_offset : 8; /* Word 5 Bits 0-7 */ + u64 trnseq_3_length : 9; /* Word 5 Bits 8-16 */ + u64 trnseq_3_offset : 8; /* Word 5 Bits 17-24 */ + u64 dmar_valid_length : 16; /* Word 5 Bits 25-40 */ + u64 dcph_valid_length : 16; /* Word 5 Bits 41-56 */ + u64 not_used_6 : 7; /* Word 5 Bits 57-63 */ + u64 frag_pipe : 8; /* Word 6 Bits 0-7 */ + u64 notif_pipe : 8; /* Word 6 Bits 8-15 */ + u64 coal_vp_valid : 1; /* Word 6 Bit 16 */ + u64 coal_vp_prev_eot : 1; /* Word 6 Bit 17 */ + u64 coal_vp_open : 1; /* Word 6 Bit 18 */ + u64 coal_vp_eot : 1; /* Word 6 Bit 19 */ + u64 not_used_7 : 4; /* Word 6 Bits 20-23 */ + u64 vp_index : 8; /* Word 6 Bits 24-31 */ + u64 exc_ttl : 1; /* Word 6 Bit 32 */ + u64 tsp_drop : 1; /* Word 6 Bit 33 */ + u64 data_cmdq_ptr : 8; /* Word 6 Bits 34-41 */ + u64 not_used_8 : 22; /* Word 6 Bits 42-63 */ + u64 frag_status_opcode : 8; /* Word 7 Bits 0-7 */ + u64 frag_rule : 4; /* Word 7 Bits 8-11 */ + u64 not_used_9 : 2; /* Word 7 Bits 12-13 */ + u64 frag_exception : 1; /* Word 7 Bit 14 */ + u64 frag_table : 1; /* Word 7 Bit 15 */ + u64 not_used_10 : 16; /* Word 7 Bits 16-31 */ + u64 frag_src_ip_address : 32; /* Word 7 Bits 32-63 */ + u64 frag_dst_ip_address : 32; /* Word 8 Bits 0-31 */ + u64 frag_fr_ret : 1; /* Word 8 Bit 32 */ + u64 frag_fnr_aggr_fc : 1; /* Word 8 Bit 33 */ + u64 frag_ttl_update : 1; /* Word 8 Bit 34 */ + u64 not_used_11 : 3; /* Word 8 Bits 35-37 */ + u64 frag_nat_type : 2; /* Word 8 Bits 38-39 */ + u64 frag_protocol : 8; /* Word 8 Bits 40-47 */ + u64 frag_id : 16; /* Word 8 Bits 48-63 */ + u64 frag_nat_ip_address : 32; /* Word 9 Bits 0-31 */ + u64 frag_header_offset : 10; /* Word 9 Bits 32-41 */ + u64 frag_ingress_tc : 6; /* Word 9 Bits 42-47 */ + u64 frag_nat_ip_cs_diff : 16; /* Word 9 Bits 48-63 */ + u64 metadata_pre_nat : 32; /* Word 10 Bits 0-31 */ + u64 frag_router_stats_index : 8; /* Word 10 Bits 32-39 */ + u64 frag_filter_stats_index : 8; /* Word 10 Bits 40-47 */ + u64 frag_dest_pipe : 8; /* Word 10 Bits 48-55 */ + u64 frag_egress_tc : 6; /* Word 10 Bits 56-61 */ + u64 frag_ingress_policer_dis : 1; /* Word 10 Bit 62 */ + u64 frag_hdr_l : 1; /* Word 10 Bit 63 */ + u64 packet_status_op_code : 8; /* Word 11 Bits 0-7 */ + u64 packet_status_exception_part1_or_drop_type : 4; /* Word 11 Bits 8-11 */ + u64 packet_status_exception_part2_or_drop_reason : 4; /* Word 11 Bits 12-15 */ + u64 not_used_12 : 1; /* Word 11 Bit 16 */ + u64 filter_process : 1; /* Word 11 Bit 17 */ + u64 nat_process : 1; /* Word 11 Bit 18 */ + u64 router_process : 1; /* Word 11 Bit 19 */ + u64 not_used_13 : 4; /* Word 11 Bits 20-23 */ + u64 packet_status_checksum_process : 1; /* Word 11 Bit 24 */ + u64 packet_status_aggr_en : 1; /* Word 11 Bit 25 */ + u64 packet_status_open_frame : 1; /* Word 11 Bit 26 */ + u64 packet_status_deaggr_en : 1; /* Word 11 Bit 27 */ + u64 packet_status_deaggr_first : 1; /* Word 11 Bit 28 */ + u64 packet_status_src_eot : 1; /* Word 11 Bit 29 */ + u64 packet_status_rqos_nas_valid : 1; /* Word 11 Bit 30 */ + u64 packet_status_rqos_as_valid : 1; /* Word 11 Bit 31 */ + u64 not_used_14 : 24; /* Word 11 Bits 32-55 */ + u64 packet_status_pure_ack : 1; /* Word 11 Bit 56 */ + u64 packet_status_syn : 1; /* Word 11 Bits 57 */ + u64 packet_status_tcp_fin_rst : 1; /* Word 11 Bits 58 */ + u64 rt_l : 1; /* Word 11 Bits 59 */ + u64 rt_h : 1; /* Word 11 Bits 60 */ + u64 packet_status_protocol_encoding : 3; /* Word 11 Bits 61-63 */ + u64 metadata : 32; /* Word 12 Bit 0-31 */ + u64 fr_l : 1; /* Word 12 Bit 32 */ + u64 fl_h : 1; /* Word 12 Bit 33 */ + u64 fr_g : 1; /* Word 12 Bit 34 */ + u64 fr_ret : 1; /* Word 12 Bit 35 */ + u64 fr_rule_id : 10; /* Word 12 Bits 36-45 */ + u64 rt_table_index : 8; /* Word 12 Bits 46-53 */ + u64 rt_rule_id : 10; /* Word 12 Bits 54-63 */ + u64 nat_hit : 1; /* Word 13 Bit 0 */ + u64 nat_table_index : 13; /* Word 13 Bits 1-13 */ + u64 nat_type : 2; /* Word 13 Bits 14-15 */ + u64 tag_info_part1 : 36; /* Word 13 Bit 16-51 */ + u64 tag_info_part2_or_egress_tc : 6; /* Word 13 Bit 52-57 */ + u64 tag_info_part3_or_igress_tc : 6; /* Word 13 Bits 58-63 */ + u64 not_used_15 : 32; /* Word 14 Bits 0-31 */ + u64 hdr_l : 1; /* Word 14 Bit 32 */ + u64 header_offset : 10; /* Word 14 Bits 33-42 */ + u64 packet_status_frag_hit : 1; /* Word 14 Bit 43 */ + u64 packet_status_frag_rule : 4; /* Word 14 Bit 44-47 */ + u64 not_used_16 : 12; /* Word 14 Bits 48-59 */ + u64 nat_exc_suppress : 1; /* Word 14 Bit 60 */ + u64 tsp : 1; /* Word 14 Bit 61 */ + u64 ttl_update : 1; /* Word 14 Bit 62 */ + u64 not_used_17 : 1; /* Word 14 Bit 63 */ + u64 ucp_cmd_id : 16; /* Word 15 Bits 0-15 */ + u64 ucp_cmd_params : 32; /* Word 15 Bits 16-47 */ + u64 close_vp_after_value : 8; /* Word 15 Bits 48-55 */ + u64 close_vp_before_value : 8; /* Word 15 Bits 56-63 */ + u64 bearer_cfg_count : 32; /* Word 16 Bits 0-31 */ + u64 mbim_aggr_sid : 32; /* Word 16 Bits 32-63 */ + u64 l4_payload_checksum : 16; /* Word 17 Bits 0-15 */ + u64 l4_pseudo_hdr_checksum : 16; /* Word 17 Bits 16-31 */ + u64 ipv4_cs_without_total_len : 16; /* Word 17 Bits 32-47 */ + u64 padding_bytes_cnt : 16; /* Word 17 Bits 48-63 */ + u64 exc_handl_hdr_ram_lines_bitmap : 32; /* Word 18 Bits 0-31 */ + u64 ulso_mss : 16; /* Word 18 Bits 32-47 */ + u64 tcp_data_offset : 4; /* Word 18 Bits 48-51 */ + u64 original_hdr_size : 9; /* Word 18 Bits 52-60 */ + u64 ulso_udp_checksum_zero : 1; /* Word 18 Bit 61 */ + u64 fin : 1; /* Word 18 Bit 62 */ + u64 ipv4_vld_checksum : 1; /* Word 18 Bit 63 */ + u64 ttl : 8; /* Word 19 Bits 0-7 */ + u64 router_stats_index : 8; /* Word 19 Bits 8-15 */ + u64 filter_stats_index : 8; /* Word 19 Bits 16-23 */ + u64 filter_action_params : 5; /* Word 19 Bits 24-28 */ + u64 metadata_type : 3; /* Word 19 Bits 29-31 */ + u64 original_src_hdr_len : 8; /* Word 19 Bits 32-39 */ + u64 egress_tc : 6; /* Word 19 Bits 40-45 */ + u64 ingress_tc : 6; /* Word 19 Bits 46-51 */ + u64 frag_hdr_offset : 9; /* Word 19 Bits 52-60 */ + u64 syn : 1; /* Word 19 Bit 61 */ + u64 urg : 1; /* Word 19 Bit 62 */ + u64 cwr : 1; /* Word 19 Bit 63 */ + u64 df : 1; /* Word 20 Bit 0 */ + u64 original_ip_version : 2; /* Word 20 Bits 1-2 */ + u64 hdri_payload_length_includes_padding : 1; /* Word 20 Bit 3 */ + u64 hdri_pdding_or_total_length : 1; /* Word 20 Bit 4 */ + u64 hdri_payload_len_valid : 1; /* Word 20 Bit 5 */ + u64 hdri_padding_valid : 1; /* Word 20 Bit 6 */ + u64 hdri_endianess : 1; /* Word 20 Bit 7 */ + u64 rt_match : 1; /* Word 20 Bit 8 */ + u64 filter_result_valid : 1; /* Word 20 Bit 9 */ + u64 push : 1; /* Word 20 Bit 10 */ + u64 rst : 1; /* Word 20 Bit 11 */ + u64 pure_ack : 1; /* Word 20 Bit 12 */ + u64 ip_checksum_fix : 1; /* Word 20 Bit 13 */ + u64 tport_checksum_fix : 1; /* Word 20 Bit 14 */ + u64 ack : 1; /* Word 20 Bit 15 */ + u64 frag_hit : 1; /* Word 20 Bit 16 */ + u64 bearer_context_index : 2; /* Word 20 Bits 17-18 */ + u64 ulso_ipv4_id_mode : 2; /* Word 20 Bits 19-20 */ + u64 ulso_frame_valid : 1; /* Word 20 Bit 21 */ + u64 close_default : 1; /* Word 20 Bit 22 */ + u64 close_vp_after : 1; /* Word 20 Bit 23 */ + u64 inc_ipv4_id : 1; /* Word 20 Bit 24 */ + u64 open_vp : 1; /* Word 20 Bit 25 */ + u64 filter_ttl_update : 1; /* Word 20 Bit 26 */ + u64 router_ttl_update : 1; /* Word 20 Bit 27 */ + u64 sdap_qfi : 6; /* Word 20 Bits 28-33 */ + u64 sdap_rqi : 1; /* Word 20 Bit 34 */ + u64 sdap_rdi : 1; /* Word 20 Bit 35 */ + u64 rqos_offload_valid : 1; /* Word 20 Bit 36 */ + u64 ingress_policer_dis : 1; /* Word 20 Bit 37 */ + u64 rqos_offload_enable : 1; /* Word 20 Bit 38 */ + u64 exc_handl_copy_hdr : 1; /* Word 20 Bit 39 */ + u64 prod_dpl_dis : 1; /* Word 20 Bit 40 */ + u64 frag_hit_2nd : 1; /* Word 20 Bit 41 */ + u64 frag_filter_aggr_fc : 1; /* Word 20 Bit 42 */ + u64 frag_router_aggr_fc : 1; /* Word 20 Bit 43 */ + u64 qmap_cs_valid_bit : 1; /* Word 20 Bit 44 */ + u64 not_used_18 : 1; /* Word 20 Bit 45 */ + u64 ece : 1; /* Word 20 Bit 46 */ + u64 udp_with_zero_checksum : 1; /* Word 20 Bit 47 */ + u64 router_rule_table_hit : 1; /* Word 20 Bit 48 */ + u64 filter_rule_table_hit : 1; /* Word 20 Bit 49 */ + u64 hps_round_cnt : 2; /* Word 20 Bits 50-51 */ + u64 first_pkt_parser_done : 1; /* Word 20 Bit 52 */ + u64 filter_result : 6; /* Word 20 Bits 53-58 */ + u64 maci_size : 2; /* Word 20 Bits 59-60 */ + u64 not_used_19 : 3; /* Word 20 Bit 61-63 */ + u64 dcph_cfg_size : 16; /* Word 21 Bits 0-15 */ + u64 bearer_id : 8; /* Word 21 Bits 16-23 */ + u64 nat_result_valid : 1; /* Word 21 Bit 24 */ + u64 nat_result : 6; /* Word 21 Bits 25-30 */ + u64 hdri_offset_padding_total_length : 8; /* Word 21 Bits 31-38 */ + u64 hdri_offset_payload_len : 8; /* Word 21 Bit 39-46 */ + u64 hdri_dst_len : 8; /* Word 21 Bits 47-54 */ + u64 hdri_additional_const_length : 8; /* Word 21 Bits 55-62 */ + u64 not_used_20 : 1; /* Word 21 Bit 63 */ +} __packed; + +#endif /* #if !defined(_IPA_PKT_CNTXT_H_) */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.5/ipa_reg_dump.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.5/ipa_reg_dump.c new file mode 100644 index 0000000000..6dff39c577 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.5/ipa_reg_dump.c @@ -0,0 +1,1914 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ +#include "ipa_reg_dump.h" +#include "ipa_access_control.h" +#include + +/* Total size required for test bus */ +#define IPA_MEM_OVERLAY_SIZE 0x66000 + +#define CONFIG_IPA3_REGDUMP_NUM_EXTRA_ENDP_REGS 0 + +/* + * The following structure contains a hierarchy of structures that + * ultimately leads to a series of leafs. The leafs are structures + * containing detailed, bit level, register definitions. + */ +static struct regs_save_hierarchy_s ipa_reg_save; + +static unsigned int ipa_testbus_mem[IPA_MEM_OVERLAY_SIZE]; + +/* + * The following data structure contains a list of the registers + * (whose data are to be copied) and the locations (within + * ipa_reg_save above) into which the registers' values need to be + * copied. + */ +static struct map_src_dst_addr_s ipa_regs_to_save_array[] = { + /* + * ===================================================================== + * IPA register definitions begin here... + * ===================================================================== + */ + + /* IPA General Registers */ + GEN_SRC_DST_ADDR_MAP(IPA_STATE, + ipa.gen, + ipa_state), + GEN_SRC_DST_ADDR_MAP_ARR(IPA_STATE_RX_ACTIVE_n, + ipa.gen, + ipa_state_rx_active_n), + GEN_SRC_DST_ADDR_MAP(IPA_STATE_TX_WRAPPER, + ipa.gen, + ipa_state_tx_wrapper), + GEN_SRC_DST_ADDR_MAP(IPA_STATE_TX, + ipa.gen, + ipa_state_tx), + GEN_SRC_DST_ADDR_MAP(IPA_STATE_TX_HOLB_MASK_DPS_TX_0, + ipa.gen, + ipa_state_tx_holb_mask_dps_tx_0), + GEN_SRC_DST_ADDR_MAP(IPA_STATE_TX_HOLB_MASK_DPS_TX_1, + ipa.gen, + ipa_state_tx_holb_mask_dps_tx_1), + GEN_SRC_DST_ADDR_MAP(IPA_STATE_TX_HOLB_MASK_NTF_TX_0, + ipa.gen, + ipa_state_tx_holb_mask_ntf_tx_0), + GEN_SRC_DST_ADDR_MAP(IPA_STATE_TX_HOLB_MASK_NTF_TX_1, + ipa.gen, + ipa_state_tx_holb_mask_ntf_tx_1), + GEN_SRC_DST_ADDR_MAP_ARR(IPA_STATE_AGGR_ACTIVE_n, + ipa.gen, + ipa_state_aggr_active_n), + GEN_SRC_DST_ADDR_MAP(IPA_STATE_DFETCHER, + ipa.gen, + ipa_state_dfetcher), + GEN_SRC_DST_ADDR_MAP(IPA_STATE_FETCHER_MASK_0, + ipa.gen, + ipa_state_fetcher_mask_0), + GEN_SRC_DST_ADDR_MAP(IPA_STATE_FETCHER_MASK_1, + ipa.gen, + ipa_state_fetcher_mask_1), + GEN_SRC_DST_ADDR_MAP(IPA_STATE_FETCHER_MASK_2, + ipa.gen, + ipa_state_fetcher_mask_2), + GEN_SRC_DST_ADDR_MAP(IPA_STATE_GSI_AOS, + ipa.gen, + ipa_state_gsi_aos), + GEN_SRC_DST_ADDR_MAP(IPA_STATE_GSI_IF, + ipa.gen, + ipa_state_gsi_if), + GEN_SRC_DST_ADDR_MAP(IPA_DPL_TIMER_LSB, + ipa.gen, + ipa_dpl_timer_lsb), + GEN_SRC_DST_ADDR_MAP(IPA_DPL_TIMER_MSB, + ipa.gen, + ipa_dpl_timer_msb), + GEN_SRC_DST_ADDR_MAP(IPA_PROC_IPH_CFG, + ipa.gen, + ipa_proc_iph_cfg), + GEN_SRC_DST_ADDR_MAP(IPA_ROUTE, + ipa.gen, + ipa_route), + GEN_SRC_DST_ADDR_MAP(IPA_SPARE_REG_1, + ipa.gen, + ipa_spare_reg_1), + GEN_SRC_DST_ADDR_MAP(IPA_CONS_LOG, + ipa.gen, + ipa_cons_log), + GEN_SRC_DST_ADDR_MAP(IPA_LOG_BUF_HW_CMD_CFG, + ipa.gen, + ipa_log_buf_hw_cmd_cfg), + GEN_SRC_DST_ADDR_MAP(IPA_LOG_BUF_HW_CMD_ADDR, + ipa.gen, + ipa_log_buf_hw_cmd_addr), + GEN_SRC_DST_ADDR_MAP(IPA_LOG_BUF_HW_CMD_WRITE_PTR, + ipa.gen, + ipa_log_buf_hw_cmd_write_ptr), + GEN_SRC_DST_ADDR_MAP(IPA_LOG_BUF_HW_CMD_RAM_PTR, + ipa.gen, + ipa_log_buf_hw_cmd_ram_ptr), + GEN_SRC_DST_ADDR_MAP(IPA_COMP_HW_VERSION, + ipa.gen, + ipa_comp_hw_version), + GEN_SRC_DST_ADDR_MAP(IPA_FILT_ROUT_CACHE_CFG, + ipa.gen, + ipa_filt_rout_cache_cfg), + GEN_SRC_DST_ADDR_MAP(IPA_FILT_ROUT_CACHE_FLUSH, + ipa.gen, + ipa_filt_rout_cache_flush), + GEN_SRC_DST_ADDR_MAP(IPA_STATE_FETCHER, + ipa.gen, + ipa_state_fetcher), + GEN_SRC_DST_ADDR_MAP(IPA_IPV4_FILTER_INIT_VALUES, + ipa.gen, + ipa_ipv4_filter_init_values), + GEN_SRC_DST_ADDR_MAP(IPA_IPV6_FILTER_INIT_VALUES, + ipa.gen, + ipa_ipv6_filter_init_values), + GEN_SRC_DST_ADDR_MAP(IPA_IPV4_ROUTE_INIT_VALUES, + ipa.gen, + ipa_ipv4_route_init_values), + GEN_SRC_DST_ADDR_MAP(IPA_IPV6_ROUTE_INIT_VALUES, + ipa.gen, + ipa_ipv6_route_init_values), + GEN_SRC_DST_ADDR_MAP(IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL, + ipa.gen, + ipa_log_buf_hw_cmd_noc_master_sel), + GEN_SRC_DST_ADDR_MAP(IPA_STATE_ACL, + ipa.gen, + ipa_state_acl), + GEN_SRC_DST_ADDR_MAP(IPA_SYS_PKT_PROC_CNTXT_BASE, + ipa.gen, + ipa_sys_pkt_proc_cntxt_base), + GEN_SRC_DST_ADDR_MAP(IPA_SYS_PKT_PROC_CNTXT_BASE_MSB, + ipa.gen, + ipa_sys_pkt_proc_cntxt_base_msb), + GEN_SRC_DST_ADDR_MAP(IPA_LOCAL_PKT_PROC_CNTXT_BASE, + ipa.gen, + ipa_local_pkt_proc_cntxt_base), + GEN_SRC_DST_ADDR_MAP(IPA_RSRC_GRP_CFG, + ipa.gen, + ipa_rsrc_grp_cfg), + GEN_SRC_DST_ADDR_MAP(IPA_COMP_CFG, + ipa.gen, + ipa_comp_cfg), + GEN_SRC_DST_ADDR_MAP(IPA_STATE_NLO_AGGR, + ipa.gen, + ipa_state_nlo_aggr), + GEN_SRC_DST_ADDR_MAP(IPA_STATE_COAL_MASTER, + ipa.gen, + ipa_state_coal_master), + GEN_SRC_DST_ADDR_MAP(IPA_STATE_COAL_MASTER_1, + ipa.gen, + ipa_state_coal_master_1), + GEN_SRC_DST_ADDR_MAP(IPA_STATE_COAL_MASTER_2, + ipa.gen, + ipa_state_coal_master_2), + GEN_SRC_DST_ADDR_MAP(IPA_STATE_COAL_MASTER_3, + ipa.gen, + ipa_state_coal_master_3), + GEN_SRC_DST_ADDR_MAP(IPA_COAL_EVICT_LRU, + ipa.gen, + ipa_coal_evict_lru), + GEN_SRC_DST_ADDR_MAP(IPA_COAL_QMAP_CFG, + ipa.gen, + ipa_coal_qmap_cfg), + GEN_SRC_DST_ADDR_MAP(IPA_TAG_TIMER, + ipa.gen, + ipa_tag_timer), + GEN_SRC_DST_ADDR_MAP(IPA_NLO_PP_CFG1, + ipa.gen, + ipa_nlo_pp_cfg1), + GEN_SRC_DST_ADDR_MAP(IPA_NLO_PP_CFG2, + ipa.gen, + ipa_nlo_pp_cfg2), + GEN_SRC_DST_ADDR_MAP(IPA_NLO_MIN_DSM_CFG, + ipa.gen, + ipa_nlo_min_dsm_cfg), + GEN_SRC_DST_ADDR_MAP_ARR(IPA_NLO_VP_AGGR_CFG_LSB_n, + ipa.gen, + ipa_nlo_vp_aggr_cfg_lsb_n), + GEN_SRC_DST_ADDR_MAP_ARR(IPA_NLO_VP_LIMIT_CFG_n, + ipa.gen, + ipa_nlo_vp_limit_cfg_n), + GEN_SRC_DST_ADDR_MAP(IPA_NLO_VP_FLUSH_REQ, + ipa.gen, + ipa_nlo_vp_flush_req), + GEN_SRC_DST_ADDR_MAP(IPA_NLO_VP_FLUSH_COOKIE, + ipa.gen, + ipa_nlo_vp_flush_cookie), + GEN_SRC_DST_ADDR_MAP(IPA_NLO_VP_FLUSH_ACK, + ipa.gen, + ipa_nlo_vp_flush_ack), + GEN_SRC_DST_ADDR_MAP(IPA_NLO_VP_DSM_OPEN, + ipa.gen, + ipa_nlo_vp_dsm_open), + GEN_SRC_DST_ADDR_MAP(IPA_NLO_VP_QBAP_OPEN, + ipa.gen, + ipa_nlo_vp_qbap_open), + GEN_SRC_DST_ADDR_MAP(IPA_QSB_MAX_READS, + ipa.gen, + ipa_qsb_max_reads), + GEN_SRC_DST_ADDR_MAP(IPA_QSB_MAX_WRITES, + ipa.gen, + ipa_qsb_max_writes), + GEN_SRC_DST_ADDR_MAP(IPA_IDLE_INDICATION_CFG, + ipa.gen, + ipa_idle_indication_cfg), + GEN_SRC_DST_ADDR_MAP(IPA_CLKON_CFG, + ipa.gen, + ipa_clkon_cfg), + GEN_SRC_DST_ADDR_MAP(IPA_TIMERS_XO_CLK_DIV_CFG, + ipa.gen, + ipa_timers_xo_clk_div_cfg), + GEN_SRC_DST_ADDR_MAP(IPA_TIMERS_PULSE_GRAN_CFG, + ipa.gen, + ipa_timers_pulse_gran_cfg), + GEN_SRC_DST_ADDR_MAP(IPA_QTIME_TIMESTAMP_CFG, + ipa.gen, + ipa_qtime_timestamp_cfg), + GEN_SRC_DST_ADDR_MAP(IPA_FLAVOR_0, + ipa.gen, + ipa_flavor_0), + GEN_SRC_DST_ADDR_MAP(IPA_FLAVOR_1, + ipa.gen, + ipa_flavor_1), + GEN_SRC_DST_ADDR_MAP(IPA_FLAVOR_2, + ipa.gen, + ipa_flavor_2), + GEN_SRC_DST_ADDR_MAP(IPA_FLAVOR_3, + ipa.gen, + ipa_flavor_3), + GEN_SRC_DST_ADDR_MAP(IPA_FLAVOR_4, + ipa.gen, + ipa_flavor_4), + GEN_SRC_DST_ADDR_MAP(IPA_FLAVOR_5, + ipa.gen, + ipa_flavor_5), + GEN_SRC_DST_ADDR_MAP(IPA_FLAVOR_6, + ipa.gen, + ipa_flavor_6), + GEN_SRC_DST_ADDR_MAP(IPA_FLAVOR_7, + ipa.gen, + ipa_flavor_7), + GEN_SRC_DST_ADDR_MAP(IPA_FLAVOR_8, + ipa.gen, + ipa_flavor_8), + GEN_SRC_DST_ADDR_MAP(IPA_FLAVOR_9, + ipa.gen, + ipa_flavor_9), + GEN_SRC_DST_ADDR_MAP(IPA_FLAVOR_10, + ipa.gen, + ipa_flavor_10), + GEN_SRC_DST_ADDR_MAP(IPA_STATE_TSP, + ipa.gen, + ipa_state_tsp), + GEN_SRC_DST_ADDR_MAP(IPA_FILT_ROUT_CFG, + ipa.gen, + ipa_filt_rout_cfg), + GEN_SRC_DST_ADDR_MAP(IPA_RSRC_GRP_CFG_EXT, + ipa.gen, + ipa_rsrc_grp_cfg_ext), + GEN_SRC_DST_ADDR_MAP(IPA_BUS_MASTER_LEGACY_BURSTS, + ipa.gen, + ipa_bus_master_legacy_bursts), + GEN_SRC_DST_ADDR_MAP(IPA_CONS_LOG_THRESHOLD_CFG, + ipa.gen, + ipa_cons_log_threshold_cfg), + GEN_SRC_DST_ADDR_MAP(IPA_PROD_LOG, + ipa.gen, + ipa_prod_log), + GEN_SRC_DST_ADDR_MAP(IPA_PROD_LOG_THRESHOLD_CFG, + ipa.gen, + ipa_prod_log_threshold_cfg), + GEN_SRC_DST_ADDR_MAP(IPA_RAM_INGRESS_POLICER_DB_BASE_ADDR, + ipa.gen, + ipa_ram_ingress_policer_db_base_addr), + GEN_SRC_DST_ADDR_MAP(IPA_RAM_EGRESS_SHAPING_PROD_DB_BASE_ADDR, + ipa.gen, + ipa_ram_egress_shaping_prod_db_base_addr), + GEN_SRC_DST_ADDR_MAP(IPA_RAM_EGRESS_SHAPING_TC_DB_BASE_ADDR, + ipa.gen, + ipa_ram_egress_shaping_tc_db_base_addr), + GEN_SRC_DST_ADDR_MAP(IPA_DPL_TIMER_CTL_STS, + ipa.gen, + ipa_dpl_timer_ctl_sts), + GEN_SRC_DST_ADDR_MAP(IPA_STATE_COAL_SLAVE, + ipa.gen, + ipa_state_coal_slave), + GEN_SRC_DST_ADDR_MAP(IPA_STATE_RQOS, + ipa.gen, + ipa_state_rqos), + GEN_SRC_DST_ADDR_MAP(IPA_IPV4_NAT_EXC_SUPPRESS_ROUT_TABLE_INDX, + ipa.gen, + ipa_ipv4_nat_exc_suppress_rout_table_indx), + GEN_SRC_DST_ADDR_MAP(IPA_IPV6_CONN_TRACK_EXC_SUPPRESS_ROUT_TABLE_INDX, + ipa.gen, + ipa_ipv6_conn_track_exc_suppress_rout_table_indx), + GEN_SRC_DST_ADDR_MAP(IPA_DPL_TIMER_SW_ADJ_LSB, + ipa.gen, + ipa_dpl_timer_sw_adj_lsb), + GEN_SRC_DST_ADDR_MAP(IPA_DPL_TIMER_SW_ADJ_MSB, + ipa.gen, + ipa_dpl_timer_sw_adj_msb), + GEN_SRC_DST_ADDR_MAP(IPA_TSP_QM_EXTERNAL_BADDR_LSB, + ipa.gen, + ipa_tsp_qm_external_baddr_lsb), + GEN_SRC_DST_ADDR_MAP(IPA_TSP_QM_EXTERNAL_BADDR_MSB, + ipa.gen, + ipa_tsp_qm_external_baddr_msb), + GEN_SRC_DST_ADDR_MAP(IPA_TSP_QM_EXTERNAL_SIZE, + ipa.gen, + ipa_tsp_qm_external_size), + GEN_SRC_DST_ADDR_MAP(IPA_TSP_INGRESS_POLICING_CFG, + ipa.gen, + ipa_tsp_ingress_policing_cfg), + GEN_SRC_DST_ADDR_MAP(IPA_TSP_EGRESS_POLICING_CFG, + ipa.gen, + ipa_tsp_egress_policing_cfg), + GEN_SRC_DST_ADDR_MAP(IPA_STAT_TSP_DROP_BASE, + ipa.gen, + ipa_stat_tsp_drop_base), + GEN_SRC_DST_ADDR_MAP(IPA_STATE_QMNGR_QUEUE_NONEMPTY, + ipa.gen, + ipa_state_qmngr_queue_nonempty), + GEN_SRC_DST_ADDR_MAP(IPA_STATE_PROD_DPL_FIFO, + ipa.gen, + ipa_state_prod_dpl_fifo), + + /* Debug Registers */ + GEN_SRC_DST_ADDR_MAP(IPA_DEBUG_DATA, + ipa.dbg, + ipa_debug_data), + IPA_REG_SAVE_RX_SPLT_CMDQ( + IPA_RX_SPLT_CMDQ_CMD_n, ipa_rx_splt_cmdq_cmd_n), + IPA_REG_SAVE_RX_SPLT_CMDQ( + IPA_RX_SPLT_CMDQ_CFG_n, ipa_rx_splt_cmdq_cfg_n), + IPA_REG_SAVE_RX_SPLT_CMDQ( + IPA_RX_SPLT_CMDQ_DATA_WR_0_n, ipa_rx_splt_cmdq_data_wr_0_n), + IPA_REG_SAVE_RX_SPLT_CMDQ( + IPA_RX_SPLT_CMDQ_DATA_WR_1_n, ipa_rx_splt_cmdq_data_wr_1_n), + IPA_REG_SAVE_RX_SPLT_CMDQ( + IPA_RX_SPLT_CMDQ_DATA_WR_2_n, ipa_rx_splt_cmdq_data_wr_2_n), + IPA_REG_SAVE_RX_SPLT_CMDQ( + IPA_RX_SPLT_CMDQ_DATA_WR_3_n, ipa_rx_splt_cmdq_data_wr_3_n), + IPA_REG_SAVE_RX_SPLT_CMDQ( + IPA_RX_SPLT_CMDQ_DATA_RD_0_n, ipa_rx_splt_cmdq_data_rd_0_n), + IPA_REG_SAVE_RX_SPLT_CMDQ( + IPA_RX_SPLT_CMDQ_DATA_RD_1_n, ipa_rx_splt_cmdq_data_rd_1_n), + IPA_REG_SAVE_RX_SPLT_CMDQ( + IPA_RX_SPLT_CMDQ_DATA_RD_2_n, ipa_rx_splt_cmdq_data_rd_2_n), + IPA_REG_SAVE_RX_SPLT_CMDQ( + IPA_RX_SPLT_CMDQ_DATA_RD_3_n, ipa_rx_splt_cmdq_data_rd_3_n), + IPA_REG_SAVE_RX_SPLT_CMDQ( + IPA_RX_SPLT_CMDQ_STATUS_n, ipa_rx_splt_cmdq_status_n), + + GEN_SRC_DST_ADDR_MAP(IPA_RX_HPS_CMDQ_CFG_WR, + ipa.dbg, + ipa_rx_hps_cmdq_cfg_wr), + GEN_SRC_DST_ADDR_MAP(IPA_RX_HPS_CMDQ_CFG_RD, + ipa.dbg, + ipa_rx_hps_cmdq_cfg_rd), + GEN_SRC_DST_ADDR_MAP(IPA_RX_HPS_CMDQ_CMD, + ipa.dbg, + ipa_rx_hps_cmdq_cmd), + GEN_SRC_DST_ADDR_MAP(IPA_STAT_FILTER_IPV4_BASE, + ipa.dbg, + ipa_stat_filter_ipv4_base), + GEN_SRC_DST_ADDR_MAP(IPA_STAT_FILTER_IPV6_BASE, + ipa.dbg, + ipa_stat_filter_ipv6_base), + GEN_SRC_DST_ADDR_MAP(IPA_STAT_ROUTER_IPV4_BASE, + ipa.dbg, + ipa_stat_router_ipv4_base), + GEN_SRC_DST_ADDR_MAP(IPA_STAT_ROUTER_IPV6_BASE, + ipa.dbg, + ipa_stat_router_ipv6_base), + GEN_SRC_DST_ADDR_MAP(IPA_RSRC_MNGR_CONTEXTS, + ipa.dbg, + ipa_rsrc_mngr_contexts), + GEN_SRC_DST_ADDR_MAP(IPA_SNOC_MONITORING_CFG, + ipa.dbg, + ipa_snoc_monitoring_cfg), + GEN_SRC_DST_ADDR_MAP(IPA_PCIE_SNOC_MONITOR_CNT, + ipa.dbg, + ipa_pcie_snoc_monitor_cnt), + GEN_SRC_DST_ADDR_MAP(IPA_DDR_SNOC_MONITOR_CNT, + ipa.dbg, + ipa_ddr_snoc_monitor_cnt), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_SNOC_MONITOR_CNT, + ipa.dbg, + ipa_gsi_snoc_monitor_cnt), + + GEN_SRC_DST_ADDR_MAP(IPA_RAM_SNIFFER_HW_BASE_ADDR, + ipa.dbg, + ipa_ram_sniffer_hw_base_addr), + GEN_SRC_DST_ADDR_MAP(IPA_BRESP_DB_CFG, + ipa.dbg, + ipa_bresp_db_cfg), + GEN_SRC_DST_ADDR_MAP(IPA_BRESP_DB_DATA, + ipa.dbg, + ipa_bresp_db_data), + GEN_SRC_DST_ADDR_MAP(IPA_BRESP_DB_DATA_1, + ipa.dbg, + ipa_bresp_db_data_1), + + GEN_SRC_DST_ADDR_MAP(IPA_ENDP_GSI_CONS_BYTES_TLV, + ipa.dbg, + ipa_endp_gsi_cons_bytes_tlv), + GEN_SRC_DST_ADDR_MAP(IPA_RAM_GSI_TLV_BASE_ADDR, + ipa.dbg, + ipa_ram_gsi_tlv_base_addr), + GEN_SRC_DST_ADDR_MAP(IPA_ACKMNGR_CMDQ_CMD, + ipa.dbg, + ipa_ackmngr_cmdq_cmd), + GEN_SRC_DST_ADDR_MAP(IPA_RX_HPS_CMDQ_STATUS_EMPTY, + ipa.dbg, + ipa_rx_hps_cmdq_status_empty), + GEN_SRC_DST_ADDR_MAP(IPA_RX_HPS_CLIENTS_MIN_DEPTH_0, + ipa.dbg, + ipa_rx_hps_clients_min_depth_0), + GEN_SRC_DST_ADDR_MAP(IPA_RX_HPS_CLIENTS_MAX_DEPTH_0, + ipa.dbg, + ipa_rx_hps_clients_max_depth_0), + GEN_SRC_DST_ADDR_MAP(IPA_HPS_DPS_CMDQ_CMD, + ipa.dbg, + ipa_hps_dps_cmdq_cmd), + GEN_SRC_DST_ADDR_MAP_ARR(IPA_HPS_DPS_CMDQ_STATUS_EMPTY_n, + ipa.dbg, + ipa_hps_dps_cmdq_status_empty_n), + GEN_SRC_DST_ADDR_MAP(IPA_DPS_TX_CMDQ_CMD, + ipa.dbg, + ipa_dps_tx_cmdq_cmd), + GEN_SRC_DST_ADDR_MAP(IPA_DPS_TX_CMDQ_STATUS_EMPTY, + ipa.dbg, + ipa_dps_tx_cmdq_status_empty), + GEN_SRC_DST_ADDR_MAP(IPA_ACKMNGR_CMDQ_CMD, + ipa.dbg, + ipa_ackmngr_cmdq_cmd), + GEN_SRC_DST_ADDR_MAP_ARR(IPA_ACKMNGR_CMDQ_STATUS_EMPTY_n, + ipa.dbg, + ipa_ackmngr_cmdq_status_empty_n), + GEN_SRC_DST_ADDR_MAP_ARR(IPA_NTF_TX_CMDQ_STATUS_EMPTY_n, + ipa.dbg, + ipa_ntf_tx_cmdq_status_empty_n), + /* + * NOTE: That GEN_SRC_DST_ADDR_MAP() not used below. This is + * because the following registers are not scaler, rather + * they are register arrays... + */ + IPA_REG_SAVE_CFG_ENTRY_GEN_EE(IPA_IRQ_STTS_EE_n, + ipa_irq_stts_ee_n), + IPA_REG_SAVE_CFG_ENTRY_GEN_EE(IPA_IRQ_EN_EE_n, + ipa_irq_en_ee_n), + IPA_REG_SAVE_CFG_ENTRY_GEN_EE(IPA_FEC_FATAL_ADDR_EE_n, + ipa_fec_fatal_addr_ee_n), + IPA_REG_SAVE_CFG_ENTRY_GEN_EE(IPA_FEC_FATAL_ATTR_EE_n, + ipa_fec_fatal_attr_ee_n), + IPA_REG_SAVE_CFG_ENTRY_GEN_EE(IPA_SNOC_FEC_EE_n, + ipa_snoc_fec_ee_n), + GEN_SRC_DST_ADDR_MAP_EE_n_REG_k_ARR(IPA_HOLB_DROP_IRQ_INFO_EE_n_REG_k, + ipa.gen_ee, ipa_holb_drop_irq_info_ee_n_reg_k), + GEN_SRC_DST_ADDR_MAP_EE_n_REG_k_ARR(IPA_SUSPEND_IRQ_INFO_EE_n_REG_k, + ipa.gen_ee, ipa_suspend_irq_info_ee_n_reg_k), + GEN_SRC_DST_ADDR_MAP_EE_n_REG_k_ARR(IPA_SUSPEND_IRQ_EN_EE_n_REG_k, + ipa.gen_ee, ipa_suspend_irq_en_ee_n_reg_k), + GEN_SRC_DST_ADDR_MAP_EE_n_ARR(IPA_STAT_QUOTA_BASE_n, + ipa.stat_ee, ipa_stat_quota_base_n), + GEN_SRC_DST_ADDR_MAP_EE_n_ARR(IPA_STAT_TETHERING_BASE_n, + ipa.stat_ee, ipa_stat_tethering_base_n), + GEN_SRC_DST_ADDR_MAP_EE_n_ARR(IPA_STAT_DROP_CNT_BASE_n, + ipa.stat_ee, ipa_stat_drop_cnt_base_n), + GEN_SRC_DST_ADDR_MAP_EE_n_REG_k_ARR(IPA_STAT_QUOTA_MASK_EE_n_REG_k, + ipa.stat_ee, ipa_stat_quota_mask_ee_n_reg_k), + GEN_SRC_DST_ADDR_MAP_EE_n_REG_k_ARR(IPA_STAT_TETHERING_MASK_EE_n_REG_k, + ipa.stat_ee, ipa_stat_tethering_mask_ee_n_reg_k), + GEN_SRC_DST_ADDR_MAP_EE_n_REG_k_ARR(IPA_STAT_DROP_CNT_MASK_EE_n_REG_k, + ipa.stat_ee, ipa_stat_drop_cnt_mask_ee_n_reg_k), + + /* Pipe Endp Registers */ + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_CTRL_n, + ipa_endp_init_ctrl_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_CTRL_SCND_n, + ipa_endp_init_ctrl_scnd_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_CFG_n, + ipa_endp_init_cfg_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_NAT_n, + ipa_endp_init_nat_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_HDR_n, + ipa_endp_init_hdr_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_HDR_EXT_n, + ipa_endp_init_hdr_ext_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_HDR_METADATA_MASK_n, + ipa_endp_init_hdr_metadata_mask_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_HDR_METADATA_n, + ipa_endp_init_hdr_metadata_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_MODE_n, + ipa_endp_init_mode_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_AGGR_n, + ipa_endp_init_aggr_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_HOL_BLOCK_EN_n, + ipa_endp_init_hol_block_en_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_HOL_BLOCK_TIMER_n, + ipa_endp_init_hol_block_timer_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_DEAGGR_n, + ipa_endp_init_deaggr_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_STATUS_n, + ipa_endp_status_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_RSRC_GRP_n, + ipa_endp_init_rsrc_grp_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_SEQ_n, + ipa_endp_init_seq_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_GSI_CFG_TLV_n, + ipa_endp_gsi_cfg_tlv_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_GSI_CFG_AOS_n, + ipa_endp_gsi_cfg_aos_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_GSI_CFG1_n, + ipa_endp_gsi_cfg1_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_FILTER_CACHE_CFG_n, + ipa_filter_cache_cfg_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ROUTER_CACHE_CFG_n, + ipa_router_cache_cfg_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_NAT_EXC_SUPPRESS_n, + ipa_endp_init_nat_exc_suppress_n), + /* Source Resource Group Config Registers */ + IPA_REG_SAVE_CFG_ENTRY_SRC_RSRC_GRP(IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n, + ipa_src_rsrc_grp_01_rsrc_type_n), + IPA_REG_SAVE_CFG_ENTRY_SRC_RSRC_GRP(IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n, + ipa_src_rsrc_grp_23_rsrc_type_n), + IPA_REG_SAVE_CFG_ENTRY_SRC_RSRC_GRP(IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n, + ipa_src_rsrc_grp_45_rsrc_type_n), + IPA_REG_SAVE_CFG_ENTRY_SRC_RSRC_GRP(IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n, + ipa_src_rsrc_grp_67_rsrc_type_n), + IPA_REG_SAVE_CFG_ENTRY_SRC_RSRC_GRP(IPA_SRC_RSRC_TYPE_AMOUNT_n, + ipa_src_rsrc_type_amount), + /* Destination Resource Group Config Registers */ + IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_GRP(IPA_DST_RSRC_GRP_01_RSRC_TYPE_n, + ipa_dst_rsrc_grp_01_rsrc_type_n), + IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_GRP(IPA_DST_RSRC_GRP_23_RSRC_TYPE_n, + ipa_dst_rsrc_grp_23_rsrc_type_n), + IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_GRP(IPA_DST_RSRC_GRP_45_RSRC_TYPE_n, + ipa_dst_rsrc_grp_45_rsrc_type_n), + IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_GRP(IPA_DST_RSRC_GRP_67_RSRC_TYPE_n, + ipa_dst_rsrc_grp_67_rsrc_type_n), + IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_GRP(IPA_DST_RSRC_TYPE_AMOUNT_n, + ipa_dst_rsrc_type_amount), + /* Source Resource Group Count Registers */ + IPA_REG_SAVE_CFG_ENTRY_SRC_RSRC_CNT_GRP( + IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n, + ipa_src_rsrc_grp_0123_rsrc_type_cnt_n), + IPA_REG_SAVE_CFG_ENTRY_SRC_RSRC_CNT_GRP( + IPA_SRC_RSRC_GRP_4567_RSRC_TYPE_CNT_n, + ipa_src_rsrc_grp_4567_rsrc_type_cnt_n), + + /* Destination Resource Group Count Registers */ + IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_CNT_GRP( + IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n, + ipa_dst_rsrc_grp_0123_rsrc_type_cnt_n), + IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_CNT_GRP( + IPA_DST_RSRC_GRP_4567_RSRC_TYPE_CNT_n, + ipa_dst_rsrc_grp_4567_rsrc_type_cnt_n), + + /* + * ===================================================================== + * GSI register definitions begin here... + * ===================================================================== + */ + + /* GSI General Registers */ + GEN_SRC_DST_ADDR_MAP(GSI_CFG, + gsi.gen, + gsi_cfg), + GEN_SRC_DST_ADDR_MAP(GSI_REE_CFG, + gsi.gen, + gsi_ree_cfg), + IPA_REG_SAVE_GSI_VER( + IPA_0_GSI_TOP_GSI_INST_RAM_n, + ipa_gsi_top_gsi_inst_ram_n), + + /* GSI Debug Registers */ + GEN_SRC_DST_ADDR_MAP(IPA_0_GSI_TOP_GSI_DEBUG_BUSY_REG, + gsi.debug, + ipa_gsi_top_gsi_debug_busy_reg), + GEN_SRC_DST_ADDR_MAP(IPA_0_GSI_TOP_GSI_DEBUG_PC_FROM_SW, + gsi.debug, + ipa_gsi_top_gsi_debug_pc_from_sw), + GEN_SRC_DST_ADDR_MAP(IPA_0_GSI_TOP_GSI_DEBUG_SW_STALL, + gsi.debug, + ipa_gsi_top_gsi_debug_sw_stall), + GEN_SRC_DST_ADDR_MAP(IPA_0_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG, + gsi.debug, + ipa_gsi_top_gsi_debug_pc_for_debug), + GEN_SRC_DST_ADDR_MAP(IPA_0_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID, + gsi.debug, + ipa_gsi_top_gsi_debug_qsb_log_err_trns_id), + GEN_SRC_DST_ADDR_MAP(GSI_MCS_PROFILING_BP_CNT_LSB, + gsi.debug.gsi_mcs_prof_regs, + gsi_top_gsi_mcs_profiling_bp_cnt_lsb), + GEN_SRC_DST_ADDR_MAP(GSI_MCS_PROFILING_BP_CNT_MSB, + gsi.debug.gsi_mcs_prof_regs, + gsi_top_gsi_mcs_profiling_bp_cnt_msb), + GEN_SRC_DST_ADDR_MAP(GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB, + gsi.debug.gsi_mcs_prof_regs, + gsi_top_gsi_mcs_profiling_bp_and_pending_cnt_lsb), + GEN_SRC_DST_ADDR_MAP(GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB, + gsi.debug.gsi_mcs_prof_regs, + gsi_top_gsi_mcs_profiling_bp_and_pending_cnt_msb), + GEN_SRC_DST_ADDR_MAP(GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB, + gsi.debug.gsi_mcs_prof_regs, + gsi_top_gsi_mcs_profiling_mcs_busy_cnt_lsb), + GEN_SRC_DST_ADDR_MAP(GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB, + gsi.debug.gsi_mcs_prof_regs, + gsi_top_gsi_mcs_profiling_mcs_busy_cnt_msb), + GEN_SRC_DST_ADDR_MAP(GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB, + gsi.debug.gsi_mcs_prof_regs, + gsi_top_gsi_mcs_profiling_mcs_idle_cnt_lsb), + GEN_SRC_DST_ADDR_MAP(GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB, + gsi.debug.gsi_mcs_prof_regs, + gsi_top_gsi_mcs_profiling_mcs_idle_cnt_msb), + IPA_REG_SAVE_CFG_ENTRY_GSI_QSB_DEBUG( + GSI_DEBUG_QSB_LOG_LAST_MISC_IDn, qsb_log_last_misc), + + /* GSI IRAM pointers Registers */ + GEN_SRC_DST_ADDR_MAP(IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_CMD, + gsi.debug.gsi_iram_ptrs, + ipa_gsi_top_gsi_iram_ptr_ch_cmd), + GEN_SRC_DST_ADDR_MAP(IPA_0_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD, + gsi.debug.gsi_iram_ptrs, + ipa_gsi_top_gsi_iram_ptr_ee_generic_cmd), + GEN_SRC_DST_ADDR_MAP(IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_DB, + gsi.debug.gsi_iram_ptrs, + ipa_gsi_top_gsi_iram_ptr_ch_db), + GEN_SRC_DST_ADDR_MAP(IPA_0_GSI_TOP_GSI_IRAM_PTR_EV_DB, + gsi.debug.gsi_iram_ptrs, + ipa_gsi_top_gsi_iram_ptr_ev_db), + GEN_SRC_DST_ADDR_MAP(IPA_0_GSI_TOP_GSI_IRAM_PTR_NEW_RE, + gsi.debug.gsi_iram_ptrs, + ipa_gsi_top_gsi_iram_ptr_new_re), + GEN_SRC_DST_ADDR_MAP(IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP, + gsi.debug.gsi_iram_ptrs, + ipa_gsi_top_gsi_iram_ptr_ch_dis_comp), + GEN_SRC_DST_ADDR_MAP(IPA_0_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY, + gsi.debug.gsi_iram_ptrs, + ipa_gsi_top_gsi_iram_ptr_ch_empty), + GEN_SRC_DST_ADDR_MAP(IPA_0_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP, + gsi.debug.gsi_iram_ptrs, + ipa_gsi_top_gsi_iram_ptr_event_gen_comp), + GEN_SRC_DST_ADDR_MAP(IPA_0_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED, + gsi.debug.gsi_iram_ptrs, + ipa_gsi_top_gsi_iram_ptr_timer_expired), + GEN_SRC_DST_ADDR_MAP(IPA_0_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP, + gsi.debug.gsi_iram_ptrs, + ipa_gsi_top_gsi_iram_ptr_write_eng_comp), + GEN_SRC_DST_ADDR_MAP(IPA_0_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP, + gsi.debug.gsi_iram_ptrs, + ipa_gsi_top_gsi_iram_ptr_read_eng_comp), + GEN_SRC_DST_ADDR_MAP(IPA_0_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT, + gsi.debug.gsi_iram_ptrs, + ipa_gsi_top_gsi_iram_ptr_uc_gp_int), + GEN_SRC_DST_ADDR_MAP(IPA_0_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPED, + gsi.debug.gsi_iram_ptrs, + ipa_gsi_top_gsi_iram_ptr_int_mod_stoped), + /* GSI SHRAM pointers Registers */ + GEN_SRC_DST_ADDR_MAP(IPA_0_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR, + gsi.debug.gsi_shram_ptrs, + ipa_gsi_top_gsi_shram_ptr_ch_cntxt_base_addr), + GEN_SRC_DST_ADDR_MAP(IPA_0_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR, + gsi.debug.gsi_shram_ptrs, + ipa_gsi_top_gsi_shram_ptr_ev_cntxt_base_addr), + GEN_SRC_DST_ADDR_MAP(IPA_0_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR, + gsi.debug.gsi_shram_ptrs, + ipa_gsi_top_gsi_shram_ptr_re_storage_base_addr), + GEN_SRC_DST_ADDR_MAP(IPA_0_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR, + gsi.debug.gsi_shram_ptrs, + ipa_gsi_top_gsi_shram_ptr_re_esc_buf_base_addr), + GEN_SRC_DST_ADDR_MAP(IPA_0_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR, + gsi.debug.gsi_shram_ptrs, + ipa_gsi_top_gsi_shram_ptr_ee_scrach_base_addr), + GEN_SRC_DST_ADDR_MAP(IPA_0_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR, + gsi.debug.gsi_shram_ptrs, + ipa_gsi_top_gsi_shram_ptr_func_stack_base_addr), + + /* + * NOTE: That GEN_SRC_DST_ADDR_MAP() not used below. This is + * because the following registers are not scaler, rather + * they are register arrays... + */ + + /* GSI General EE Registers */ + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(GSI_MANAGER_EE_QOS_n, + gsi_manager_ee_qos_n), + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_GSI_STATUS, + ee_n_gsi_status), + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_CNTXT_TYPE_IRQ, + ee_n_cntxt_type_irq), + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_CNTXT_TYPE_IRQ_MSK, + ee_n_cntxt_type_irq_msk), + GEN_SRC_DST_ADDR_MAP_EE_n_REG_k_ARR(EE_n_CNTXT_SRC_GSI_CH_IRQ_k, + gsi.gen_ee, + ee_n_cntxt_src_gsi_ch_irq_k), + GEN_SRC_DST_ADDR_MAP_EE_n_REG_k_ARR(EE_n_CNTXT_SRC_EV_CH_IRQ_k, + gsi.gen_ee, + ee_n_cntxt_src_ev_ch_irq_k), + GEN_SRC_DST_ADDR_MAP_EE_n_REG_k_ARR(EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k, + gsi.gen_ee, + ee_n_cntxt_src_gsi_ch_irq_msk_k), + GEN_SRC_DST_ADDR_MAP_EE_n_REG_k_ARR(EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k, + gsi.gen_ee, + ee_n_cntxt_src_ev_ch_irq_msk_k), + GEN_SRC_DST_ADDR_MAP_EE_n_REG_k_ARR(EE_n_CNTXT_SRC_IEOB_IRQ_k, + gsi.gen_ee, + ee_n_cntxt_src_ieob_irq_k), + GEN_SRC_DST_ADDR_MAP_EE_n_REG_k_ARR(EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k, + gsi.gen_ee, + ee_n_cntxt_src_ieob_irq_msk_k), + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_CNTXT_GSI_IRQ_STTS, + ee_n_cntxt_gsi_irq_stts), + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_CNTXT_GLOB_IRQ_STTS, + ee_n_cntxt_glob_irq_stts), + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_ERROR_LOG, + ee_n_error_log), + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_CNTXT_SCRATCH_0, + ee_n_cntxt_scratch_0), + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_CNTXT_SCRATCH_1, + ee_n_cntxt_scratch_1), + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_CNTXT_INTSET, + ee_n_cntxt_intset), + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_CNTXT_MSI_BASE_LSB, + ee_n_cntxt_msi_base_lsb), + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_CNTXT_MSI_BASE_MSB, + ee_n_cntxt_msi_base_msb), + + /* GSI Channel Context Registers */ + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_CNTXT_0, + ee_n_gsi_ch_k_cntxt_0), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_CNTXT_1, + ee_n_gsi_ch_k_cntxt_1), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_CNTXT_2, + ee_n_gsi_ch_k_cntxt_2), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_CNTXT_3, + ee_n_gsi_ch_k_cntxt_3), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_CNTXT_4, + ee_n_gsi_ch_k_cntxt_4), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_CNTXT_5, + ee_n_gsi_ch_k_cntxt_5), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_CNTXT_6, + ee_n_gsi_ch_k_cntxt_6), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_CNTXT_7, + ee_n_gsi_ch_k_cntxt_7), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_RE_FETCH_READ_PTR, + ee_n_gsi_ch_k_re_fetch_read_ptr), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR, + ee_n_gsi_ch_k_re_fetch_write_ptr), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_QOS, + ee_n_gsi_ch_k_qos), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_SCRATCH_0, + ee_n_gsi_ch_k_scratch_0), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_SCRATCH_1, + ee_n_gsi_ch_k_scratch_1), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_SCRATCH_2, + ee_n_gsi_ch_k_scratch_2), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_SCRATCH_3, + ee_n_gsi_ch_k_scratch_3), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_SCRATCH_4, + ee_n_gsi_ch_k_scratch_4), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_SCRATCH_5, + ee_n_gsi_ch_k_scratch_5), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_SCRATCH_6, + ee_n_gsi_ch_k_scratch_6), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_SCRATCH_7, + ee_n_gsi_ch_k_scratch_7), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_SCRATCH_8, + ee_n_gsi_ch_k_scratch_8), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_SCRATCH_9, + ee_n_gsi_ch_k_scratch_9), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(GSI_MAP_EE_n_CH_k_VP_TABLE, + gsi_map_ee_n_ch_k_vp_table), + + /* GSI Channel Event Context Registers */ + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_CNTXT_0, + ee_n_ev_ch_k_cntxt_0), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_CNTXT_1, + ee_n_ev_ch_k_cntxt_1), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_CNTXT_2, + ee_n_ev_ch_k_cntxt_2), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_CNTXT_3, + ee_n_ev_ch_k_cntxt_3), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_CNTXT_4, + ee_n_ev_ch_k_cntxt_4), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_CNTXT_5, + ee_n_ev_ch_k_cntxt_5), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_CNTXT_6, + ee_n_ev_ch_k_cntxt_6), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_CNTXT_7, + ee_n_ev_ch_k_cntxt_7), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_CNTXT_8, + ee_n_ev_ch_k_cntxt_8), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_CNTXT_9, + ee_n_ev_ch_k_cntxt_9), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_CNTXT_10, + ee_n_ev_ch_k_cntxt_10), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_CNTXT_11, + ee_n_ev_ch_k_cntxt_11), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_CNTXT_12, + ee_n_ev_ch_k_cntxt_12), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_CNTXT_13, + ee_n_ev_ch_k_cntxt_13), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_SCRATCH_0, + ee_n_ev_ch_k_scratch_0), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_SCRATCH_1, + ee_n_ev_ch_k_scratch_1), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(GSI_DEBUG_EE_n_EV_k_VP_TABLE, + gsi_debug_ee_n_ev_k_vp_table), + +/* GSI Debug SW MSK Registers */ + IPA_REG_SAVE_GSI_DEBUG_MSK_REG_ENTRY(GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD, + regs), +#if defined(CONFIG_IPA3_REGDUMP_NUM_EXTRA_ENDP_REGS) && \ + CONFIG_IPA3_REGDUMP_NUM_EXTRA_ENDP_REGS > 0 + /* Endp Registers for remaining pipes */ + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_INIT_CTRL_n, + ipa_endp_init_ctrl_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_INIT_CTRL_SCND_n, + ipa_endp_init_ctrl_scnd_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_INIT_CFG_n, + ipa_endp_init_cfg_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_INIT_NAT_n, + ipa_endp_init_nat_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_INIT_HDR_n, + ipa_endp_init_hdr_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_INIT_HDR_EXT_n, + ipa_endp_init_hdr_ext_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA + (IPA_ENDP_INIT_HDR_METADATA_MASK_n, + ipa_endp_init_hdr_metadata_mask_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_INIT_HDR_METADATA_n, + ipa_endp_init_hdr_metadata_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_INIT_MODE_n, + ipa_endp_init_mode_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_INIT_AGGR_n, + ipa_endp_init_aggr_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_INIT_HOL_BLOCK_EN_n, + ipa_endp_init_hol_block_en_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_INIT_HOL_BLOCK_TIMER_n, + ipa_endp_init_hol_block_timer_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_INIT_DEAGGR_n, + ipa_endp_init_deaggr_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_STATUS_n, + ipa_endp_status_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_INIT_RSRC_GRP_n, + ipa_endp_init_rsrc_grp_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_INIT_SEQ_n, + ipa_endp_init_seq_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_GSI_CFG_TLV_n, + ipa_endp_gsi_cfg_tlv_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_GSI_CFG_AOS_n, + ipa_endp_gsi_cfg_aos_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_GSI_CFG1_n, + ipa_endp_gsi_cfg1_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA + (IPA_ENDP_FILTER_ROUTER_HSH_CFG_n, + ipa_endp_filter_router_hsh_cfg_n), +#endif +}; + +/* IPA uC PER registers save Cfg array */ +static struct map_src_dst_addr_s ipa_uc_regs_to_save_array[] = { + /* HWP registers */ + GEN_SRC_DST_ADDR_MAP(IPA_UC_QMB_SYS_ADDR, + ipa.hwp, + ipa_uc_qmb_sys_addr), + GEN_SRC_DST_ADDR_MAP(IPA_UC_QMB_LOCAL_ADDR, + ipa.hwp, + ipa_uc_qmb_local_addr), + GEN_SRC_DST_ADDR_MAP(IPA_UC_QMB_LENGTH, + ipa.hwp, + ipa_uc_qmb_length), + GEN_SRC_DST_ADDR_MAP(IPA_UC_QMB_TRIGGER, + ipa.hwp, + ipa_uc_qmb_trigger), + GEN_SRC_DST_ADDR_MAP(IPA_UC_QMB_BUS_ATTRIB, + ipa.hwp, + ipa_uc_qmb_bus_attrib), +}; + +static void ipa_hal_save_regs_save_ipa_testbus(void); +static void ipa_reg_save_gsi_fifo_status(void); +static void ipa_reg_save_rsrc_cnts(void); +static void ipa_hal_save_regs_ipa_cmdq(void); +static void ipa_hal_save_regs_rsrc_db(void); +static void ipa_reg_save_anomaly_check(void); + +static struct reg_access_funcs_s *get_access_funcs(u32 addr) +{ + u32 i, asub = ipa3_ctx->sd_state; + + for (i = 0; i < ARRAY_SIZE(mem_access_map); i++) { + if (addr >= mem_access_map[i].addr_range_begin && + addr < mem_access_map[i].addr_range_end) { + return mem_access_map[i].access[asub]; + } + } + + IPAERR("Unknown register offset(0x%08X). Using dflt access methods\n", + addr); + + return &io_matrix[AA_COMBO]; +} + +static u32 in_dword( + u32 addr, + u8 perm) +{ + struct reg_access_funcs_s *io = get_access_funcs(addr); + + if (perm & REG_READ_PERM) { + if (io->read == nop_read) + IPADBG_LOW("nop read action for address 0x%X\n", addr); + return io->read(ipa3_ctx->reg_collection_base + addr); + } else { + IPADBG_LOW("not permitted to read addr 0x%X\n", addr); + return nop_read(ipa3_ctx->reg_collection_base + addr); + } +} + +static u32 in_dword_masked( + u32 addr, + u32 mask, + u8 perm) +{ + struct reg_access_funcs_s *io = get_access_funcs(addr); + u32 val; + + if (perm & REG_READ_PERM) { + if (io->read == nop_read) + IPADBG_LOW("nop read action for address 0x%X\n", addr); + + val = io->read(ipa3_ctx->reg_collection_base + addr); + if (io->read == act_read) + return val & mask; + } else { + IPADBG_LOW("not permitted to read addr 0x%X\n", addr); + val = nop_read(ipa3_ctx->reg_collection_base + addr); + } + + return val; +} + +static void out_dword( + u32 addr, + u32 val, + u8 perm) +{ + struct reg_access_funcs_s *io = get_access_funcs(addr); + + if (perm & REG_WRITE_PERM) { + io->write(ipa3_ctx->reg_collection_base + addr, val); + if (io->write == nop_write) + IPADBG_LOW("nop write action for address 0x%X\n", addr); + } else { + IPADBG_LOW("not permitted to write addr 0x%X\n", addr); + return; + } +} + +/* + * FUNCTION: ipa_save_gsi_ver + * + * Saves the gsi version + * + * @return + * None + */ +void ipa_save_gsi_ver(void) +{ + u32 gsi_fw_ver; + + if (!ipa3_ctx->do_register_collection_on_crash) + return; + + /* IPA_HW_v5_5 */ + gsi_fw_ver = IPA_READ_1xVECTOR_REG(IPA_0_GSI_TOP_GSI_INST_RAM_n, 66); + + ipa_reg_save.gsi.fw_ver.raw_version = gsi_fw_ver; + ipa_reg_save.gsi.fw_ver.hw_version = (gsi_fw_ver & GSI_INST_RAM_FW_VER_HW_MASK) >> + GSI_INST_RAM_FW_VER_HW_SHIFT; + ipa_reg_save.gsi.fw_ver.flavor = (gsi_fw_ver & GSI_INST_RAM_FW_VER_FLAVOR_MASK) >> + GSI_INST_RAM_FW_VER_FLAVOR_SHIFT; + ipa_reg_save.gsi.fw_ver.fw_version = (gsi_fw_ver & GSI_INST_RAM_FW_VER_FW_MASK) >> + GSI_INST_RAM_FW_VER_FW_SHIFT; +} + +/* + * FUNCTION: ipa_save_registers + * + * Saves all the IPA register values which are configured + * + * @return + * None + */ +void ipa_save_registers(void) +{ + u32 i = 0; + u32 phys_ch_idx = 0; + u32 n = 0; + /* Fetch the number of registers configured to be saved */ + u32 num_regs = ARRAY_SIZE(ipa_regs_to_save_array); + u32 num_uc_per_regs = ARRAY_SIZE(ipa_uc_regs_to_save_array); + union ipa_hwio_def_ipa_rsrc_mngr_db_cfg_u for_cfg; + union ipa_hwio_def_ipa_rsrc_mngr_db_rsrc_read_u for_read; + + if (!ipa3_ctx->do_register_collection_on_crash) + return; + + IPAERR("Commencing\n"); + + /* + * Remove the GSI FIFO and the endp registers for extra pipes for + * now. These would be saved later + */ + num_regs -= (CONFIG_IPA3_REGDUMP_NUM_EXTRA_ENDP_REGS * + IPA_REG_SAVE_NUM_EXTRA_ENDP_REGS); + + memset(&for_cfg, 0, sizeof(for_cfg)); + memset(&for_read, 0, sizeof(for_read)); + + IPAERR("reading %d registers\n", num_regs); + /* Now save all the configured registers */ + for (i = 0; i < num_regs; i++) { + /* Copy reg value to our data struct */ + *(ipa_regs_to_save_array[i].dst_addr) = + in_dword(ipa_regs_to_save_array[i].src_addr, + ipa_regs_to_save_array[i].perm); + } + + /* + * Set the active flag for all active pipe indexed registers. + */ + for (i = 0; i < IPA_HW_PIPE_ID_MAX; i++) + ipa_reg_save.ipa.pipes[i].active = true; + + /* Now save the per endp registers for the remaining pipes */ + for (i = 0; i < (CONFIG_IPA3_REGDUMP_NUM_EXTRA_ENDP_REGS * + IPA_REG_SAVE_NUM_EXTRA_ENDP_REGS); i++) { + /* Copy reg value to our data struct */ + *(ipa_regs_to_save_array[num_regs + i].dst_addr) = + in_dword(ipa_regs_to_save_array[num_regs + i].src_addr, + ipa_regs_to_save_array[num_regs + i].perm); + } + + IPA_HW_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA_ACTIVE(); + + num_regs += (CONFIG_IPA3_REGDUMP_NUM_EXTRA_ENDP_REGS * + IPA_REG_SAVE_NUM_EXTRA_ENDP_REGS); + + /* Saving GSI FIFO Status registers */ + ipa_reg_save_gsi_fifo_status(); + + /* + * On targets that support SSR, we generally want to disable + * the following reg save functionality as it may cause stalls + * in IPA after the SSR. + * + * To override this, set do_non_tn_collection_on_crash to + * true, via dtsi, and the collection will be done. + */ + if (ipa3_ctx->do_non_tn_collection_on_crash) { + /* Save all the uC PER configured registers */ + for (i = 0; i < num_uc_per_regs; i++) { + /* Copy reg value to our data struct */ + *(ipa_uc_regs_to_save_array[i].dst_addr) = + in_dword(ipa_uc_regs_to_save_array[i].src_addr, + ipa_uc_regs_to_save_array[i].perm); + } + + /* Saving CMD Queue registers */ + ipa_hal_save_regs_ipa_cmdq(); + + /* Collecting resource DB information */ + ipa_hal_save_regs_rsrc_db(); + + /* Save IPA testbus */ + if (ipa3_ctx->do_testbus_collection_on_crash) + ipa_hal_save_regs_save_ipa_testbus(); + } + + /* GSI test bus */ + for (i = 0; + i < ARRAY_SIZE(ipa_reg_save_gsi_ch_test_bus_selector_array); + i++) { + ipa_reg_save.gsi.debug.gsi_test_bus.test_bus_selector[i] = + ipa_reg_save_gsi_ch_test_bus_selector_array[i]; + + /* Write test bus selector */ + IPA_WRITE_SCALER_REG( + GSI_TEST_BUS_SEL, + ipa_reg_save_gsi_ch_test_bus_selector_array[i]); + + ipa_reg_save.gsi.debug.gsi_test_bus.test_bus_reg[ + i].gsi_testbus_reg = + (u32) IPA_READ_SCALER_REG(GSI_TEST_BUS_REG); + } + + ipa_reg_save_rsrc_cnts(); + + for (i = 0; i < HWIO_GSI_DEBUG_SW_RF_n_READ_MAXn + 1; i++) + ipa_reg_save.gsi.debug.gsi_mcs_regs.mcs_reg[i].rf_reg = + IPA_READ_1xVECTOR_REG(GSI_DEBUG_SW_RF_n_READ, i); + + for (i = 0; i < HWIO_GSI_DEBUG_COUNTERn_MAXn + 1; i++) + ipa_reg_save.gsi.debug.gsi_cnt_regs.cnt[i].counter_value = + (u16)IPA_READ_1xVECTOR_REG(GSI_DEBUG_COUNTERn, i); + + for (i = 0; i < IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_A7; i++) { + phys_ch_idx = ipa_reg_save.gsi.ch_cntxt.a7[ + i].gsi_map_ee_n_ch_k_vp_table.phy_ch; + n = phys_ch_idx * IPA_REG_SAVE_BYTES_PER_CHNL_SHRAM; + + if (!ipa_reg_save.gsi.ch_cntxt.a7[ + i].gsi_map_ee_n_ch_k_vp_table.valid) + continue; + + ipa_reg_save.gsi.ch_cntxt.a7[ + i].mcs_channel_scratch.scratch_for_seq_low.shram = + IPA_READ_1xVECTOR_REG( + GSI_SHRAM_n, + n + IPA_GSI_OFFSET_WORDS_SCRATCH_FOR_SEQ_LOW); + + ipa_reg_save.gsi.ch_cntxt.a7[ + i].mcs_channel_scratch.scratch_for_seq_high.shram = + IPA_READ_1xVECTOR_REG( + GSI_SHRAM_n, + n + IPA_GSI_OFFSET_WORDS_SCRATCH_FOR_SEQ_HIGH); + ipa_reg_save.gsi.ch_cntxt.a7[ + i].fc_stats_state.value = IPA_READ_1xVECTOR_REG( + GSI_SHRAM_n, + n + IPA_REG_SAVE_FC_STATE_OFFSET); + } + for (i = 0; i < IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_UC; i++) { + phys_ch_idx = ipa_reg_save.gsi.ch_cntxt.uc[ + i].gsi_map_ee_n_ch_k_vp_table.phy_ch; + n = phys_ch_idx * IPA_REG_SAVE_BYTES_PER_CHNL_SHRAM; + + if (!ipa_reg_save.gsi.ch_cntxt.uc[ + i].gsi_map_ee_n_ch_k_vp_table.valid) + continue; + + ipa_reg_save.gsi.ch_cntxt.uc[ + i].mcs_channel_scratch.scratch_for_seq_low.shram = + IPA_READ_1xVECTOR_REG( + GSI_SHRAM_n, + n + IPA_GSI_OFFSET_WORDS_SCRATCH_FOR_SEQ_LOW); + + ipa_reg_save.gsi.ch_cntxt.uc[ + i].mcs_channel_scratch.scratch_for_seq_high.shram = + IPA_READ_1xVECTOR_REG( + GSI_SHRAM_n, + n + IPA_GSI_OFFSET_WORDS_SCRATCH_FOR_SEQ_HIGH); + ipa_reg_save.gsi.ch_cntxt.uc[ + i].fc_stats_state.value = IPA_READ_1xVECTOR_REG( + GSI_SHRAM_n, + n + IPA_REG_SAVE_FC_STATE_OFFSET); + } + + for (i = 0; i < IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_Q6; i++) { + phys_ch_idx = ipa_reg_save.gsi.ch_cntxt.q6[ + i].gsi_map_ee_n_ch_k_vp_table.phy_ch; + n = phys_ch_idx * IPA_REG_SAVE_BYTES_PER_CHNL_SHRAM; + + if (!ipa_reg_save.gsi.ch_cntxt.q6[ + i].gsi_map_ee_n_ch_k_vp_table.valid) + continue; + + ipa_reg_save.gsi.ch_cntxt.q6[ + i].mcs_channel_scratch.scratch_for_seq_low.shram = + IPA_READ_1xVECTOR_REG( + GSI_SHRAM_n, + n + IPA_GSI_OFFSET_WORDS_SCRATCH_FOR_SEQ_LOW); + + ipa_reg_save.gsi.ch_cntxt.q6[ + i].mcs_channel_scratch.scratch_for_seq_high.shram = + IPA_READ_1xVECTOR_REG( + GSI_SHRAM_n, + n + IPA_GSI_OFFSET_WORDS_SCRATCH_FOR_SEQ_HIGH); + ipa_reg_save.gsi.ch_cntxt.q6[ + i].fc_stats_state.value = IPA_READ_1xVECTOR_REG( + GSI_SHRAM_n, + n + IPA_REG_SAVE_FC_STATE_OFFSET); + } + /* + * On targets that support SSR, we generally want to disable + * the following reg save functionality as it may cause stalls + * in IPA after the SSR. + * + * To override this, set do_non_tn_collection_on_crash to + * true, via dtsi, and the collection will be done. + */ + if (ipa3_ctx->do_non_tn_collection_on_crash) { + u32 ofst = GEN_2xVECTOR_REG_OFST(IPA_CTX_ID_m_CTX_NUM_n, 0, 0); + struct reg_access_funcs_s *io = get_access_funcs(ofst); + /* + * If the memory is accessible, copy pkt context directly from + * IPA_CTX_ID register space + */ + if (io->read == act_read) { + for (i = 0; i < IPA_HW_PKT_CTNTX_MAX; i++) { + memcpy((void *)(&(ipa_reg_save.pkt_ctntx[i])), + (void*)(ipa3_ctx->reg_collection_base + HWIO_IPA_CTX_ID_m_CTX_NUM_n_ADDR(i, 0)), + sizeof(ipa_reg_save.pkt_ctntx[0])); + } + + for_cfg.value = + IPA_READ_SCALER_REG(IPA_RSRC_MNGR_DB_CFG); + + for_cfg.def.rsrc_type_sel = 0; + + IPA_MASKED_WRITE_SCALER_REG( + IPA_RSRC_MNGR_DB_CFG, + for_cfg.value); + + for (i = 0; i < IPA_HW_PKT_CTNTX_MAX; i++) { + for_cfg.def.rsrc_id_sel = i; + + IPA_MASKED_WRITE_SCALER_REG( + IPA_RSRC_MNGR_DB_CFG, + for_cfg.value); + + for_read.value = + IPA_READ_SCALER_REG( + IPA_RSRC_MNGR_DB_RSRC_READ); + + if (for_read.def.rsrc_occupied) { + ipa_reg_save.pkt_ctntx_active[i] = true; + ipa_reg_save.pkt_cntxt_state[i] = + (enum ipa_hw_pkt_cntxt_state_e) + ipa_reg_save.pkt_ctntx[i].state; + } + } + } else { + IPAERR("IPA_CTX_ID is not currently accessible\n"); + } + } + + if (ipa3_ctx->do_ram_collection_on_crash) { + for (i = 0; i < IPA_IU_SIZE / sizeof(u32); i++) { + ipa_reg_save.ipa.ipa_iu_ptr[i] = + in_dword(IPA_IU_ADDR + (i * sizeof(u32)), + REG_READ_PERM); + } + for (i = 0; i < IPA_SRAM_SIZE / sizeof(u32); i++) { + ipa_reg_save.ipa.ipa_sram_ptr[i] = + in_dword(IPA_SRAM_ADDR + (i * sizeof(u32)), + REG_READ_PERM); + } + for (i = 0; i < IPA_MBOX_SIZE / sizeof(u32); i++) { + ipa_reg_save.ipa.ipa_mbox_ptr[i] = + in_dword(IPA_MBOX_ADDR + (i * sizeof(u32)), + REG_READ_PERM); + } + for (i = 0; i < IPA_HRAM_SIZE / sizeof(u32); i++) { + ipa_reg_save.ipa.ipa_hram_ptr[i] = + in_dword(IPA_HRAM_ADDR + (i * sizeof(u32)), + REG_READ_PERM); + } + for (i = 0; i < IPA_SEQ_SIZE / sizeof(u32); i++) { + ipa_reg_save.ipa.ipa_seq_ptr[i] = + in_dword(IPA_SEQ_ADDR + (i * sizeof(u32)), + REG_READ_PERM); + } + for (i = 0; i < IPA_GSI_SIZE / sizeof(u32); i++) { + ipa_reg_save.ipa.ipa_gsi_ptr[i] = + in_dword(IPA_GSI_ADDR + (i * sizeof(u32)), + REG_READ_PERM); + } + IPALOG_VnP_ADDRS(ipa_reg_save.ipa.ipa_iu_ptr); + IPALOG_VnP_ADDRS(ipa_reg_save.ipa.ipa_sram_ptr); + IPALOG_VnP_ADDRS(ipa_reg_save.ipa.ipa_mbox_ptr); + IPALOG_VnP_ADDRS(ipa_reg_save.ipa.ipa_hram_ptr); + IPALOG_VnP_ADDRS(ipa_reg_save.ipa.ipa_seq_ptr); + IPALOG_VnP_ADDRS(ipa_reg_save.ipa.ipa_gsi_ptr); + } + + ipa_reg_save_anomaly_check(); + + IPAERR("Completed\n"); +} + +/* + * FUNCTION: ipa_reg_save_gsi_fifo_status + * + * This function saves the GSI FIFO Status registers for all endpoints + * + * @param + * + * @return + */ +static void ipa_reg_save_gsi_fifo_status(void) +{ + u8 i; + for (i = 0; i < IPA_HW_PIPE_ID_MAX; i++) { + memset(&ipa_reg_save.gsi_fifo_status[i].gsi_fifo_status_ctrl, + 0, sizeof(ipa_reg_save.gsi_fifo_status[i].gsi_fifo_status_ctrl)); + + ipa_reg_save.gsi_fifo_status[i].gsi_fifo_status_ctrl.def.ipa_gsi_fifo_status_en = 1; + ipa_reg_save.gsi_fifo_status[i].gsi_fifo_status_ctrl.def.ipa_gsi_fifo_status_port_sel = i; + + IPA_MASKED_WRITE_SCALER_REG(IPA_GSI_FIFO_STATUS_CTRL, + ipa_reg_save.gsi_fifo_status[i].gsi_fifo_status_ctrl.value); + + ipa_reg_save.gsi_fifo_status[i].gsi_tlv_fifo_status.value = + IPA_READ_SCALER_REG(IPA_GSI_TLV_FIFO_STATUS); + ipa_reg_save.gsi_fifo_status[i].gsi_aos_fifo_status.value = + IPA_READ_SCALER_REG(IPA_GSI_AOS_FIFO_STATUS); + } +} + +/* + * FUNCTION: ipa_reg_save_rsrc_cnts + * + * This function saves the resource counts for all PCIE and DDR + * resource groups. + * + * @param + * @return + */ +static void ipa_reg_save_rsrc_cnts(void) +{ + union ipa_hwio_def_ipa_src_rsrc_grp_0123_rsrc_type_cnt_n_u + src_0123_rsrc_cnt; + union ipa_hwio_def_ipa_dst_rsrc_grp_0123_rsrc_type_cnt_n_u + dst_0123_rsrc_cnt; + + ipa_reg_save.rsrc_cnts.pcie.resource_group = IPA_HW_PCIE_SRC_RSRP_GRP; + ipa_reg_save.rsrc_cnts.ddr.resource_group = IPA_HW_DDR_SRC_RSRP_GRP; + + src_0123_rsrc_cnt.value = + IPA_READ_1xVECTOR_REG(IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n, 0); + + ipa_reg_save.rsrc_cnts.pcie.src.pkt_cntxt = + src_0123_rsrc_cnt.def.src_rsrc_grp_0_cnt; + ipa_reg_save.rsrc_cnts.ddr.src.pkt_cntxt = + src_0123_rsrc_cnt.def.src_rsrc_grp_1_cnt; + + src_0123_rsrc_cnt.value = + IPA_READ_1xVECTOR_REG(IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n, 1); + + ipa_reg_save.rsrc_cnts.pcie.src.descriptor_list = + src_0123_rsrc_cnt.def.src_rsrc_grp_0_cnt; + ipa_reg_save.rsrc_cnts.ddr.src.descriptor_list = + src_0123_rsrc_cnt.def.src_rsrc_grp_1_cnt; + + src_0123_rsrc_cnt.value = + IPA_READ_1xVECTOR_REG(IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n, 2); + + ipa_reg_save.rsrc_cnts.pcie.src.data_descriptor_buffer = + src_0123_rsrc_cnt.def.src_rsrc_grp_0_cnt; + ipa_reg_save.rsrc_cnts.ddr.src.data_descriptor_buffer = + src_0123_rsrc_cnt.def.src_rsrc_grp_1_cnt; + + src_0123_rsrc_cnt.value = + IPA_READ_1xVECTOR_REG(IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n, 3); + + ipa_reg_save.rsrc_cnts.pcie.src.hps_dmars = + src_0123_rsrc_cnt.def.src_rsrc_grp_0_cnt; + ipa_reg_save.rsrc_cnts.ddr.src.hps_dmars = + src_0123_rsrc_cnt.def.src_rsrc_grp_1_cnt; + + src_0123_rsrc_cnt.value = + IPA_READ_1xVECTOR_REG(IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n, 4); + + ipa_reg_save.rsrc_cnts.pcie.src.reserved_acks = + src_0123_rsrc_cnt.def.src_rsrc_grp_0_cnt; + ipa_reg_save.rsrc_cnts.ddr.src.reserved_acks = + src_0123_rsrc_cnt.def.src_rsrc_grp_1_cnt; + + dst_0123_rsrc_cnt.value = + IPA_READ_1xVECTOR_REG(IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n, 0); + + ipa_reg_save.rsrc_cnts.pcie.dst.reserved_sectors = + dst_0123_rsrc_cnt.def.dst_rsrc_grp_0_cnt; + ipa_reg_save.rsrc_cnts.ddr.dst.reserved_sectors = + dst_0123_rsrc_cnt.def.dst_rsrc_grp_1_cnt; + + dst_0123_rsrc_cnt.value = + IPA_READ_1xVECTOR_REG(IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n, 1); + + ipa_reg_save.rsrc_cnts.pcie.dst.dps_dmars = + dst_0123_rsrc_cnt.def.dst_rsrc_grp_0_cnt; + ipa_reg_save.rsrc_cnts.ddr.dst.dps_dmars = + dst_0123_rsrc_cnt.def.dst_rsrc_grp_1_cnt; +} + +/* + * FUNCTION: ipa_reg_save_rsrc_cnts_test_bus + * + * This function saves the resource counts for all PCIE and DDR + * resource groups collected from test bus. + * + * @param + * + * @return + */ +void ipa_reg_save_rsrc_cnts_test_bus(void) +{ + int32_t rsrc_type = 0; + + ipa_reg_save.rsrc_cnts.pcie.resource_group = IPA_HW_PCIE_SRC_RSRP_GRP; + ipa_reg_save.rsrc_cnts.ddr.resource_group = IPA_HW_DDR_SRC_RSRP_GRP; + + rsrc_type = 0; + ipa_reg_save.rsrc_cnts.pcie.src.pkt_cntxt = + IPA_DEBUG_TESTBUS_GET_RSRC_TYPE_CNT(rsrc_type, + IPA_HW_PCIE_SRC_RSRP_GRP); + + ipa_reg_save.rsrc_cnts.ddr.src.pkt_cntxt = + IPA_DEBUG_TESTBUS_GET_RSRC_TYPE_CNT(rsrc_type, + IPA_HW_DDR_SRC_RSRP_GRP); + + rsrc_type = 1; + ipa_reg_save.rsrc_cnts.pcie.src.descriptor_list = + IPA_DEBUG_TESTBUS_GET_RSRC_TYPE_CNT(rsrc_type, + IPA_HW_PCIE_SRC_RSRP_GRP); + + ipa_reg_save.rsrc_cnts.ddr.src.descriptor_list = + IPA_DEBUG_TESTBUS_GET_RSRC_TYPE_CNT(rsrc_type, + IPA_HW_DDR_SRC_RSRP_GRP); + + rsrc_type = 2; + ipa_reg_save.rsrc_cnts.pcie.src.data_descriptor_buffer = + IPA_DEBUG_TESTBUS_GET_RSRC_TYPE_CNT(rsrc_type, + IPA_HW_PCIE_SRC_RSRP_GRP); + + ipa_reg_save.rsrc_cnts.ddr.src.data_descriptor_buffer = + IPA_DEBUG_TESTBUS_GET_RSRC_TYPE_CNT(rsrc_type, + IPA_HW_DDR_SRC_RSRP_GRP); + + rsrc_type = 3; + ipa_reg_save.rsrc_cnts.pcie.src.hps_dmars = + IPA_DEBUG_TESTBUS_GET_RSRC_TYPE_CNT(rsrc_type, + IPA_HW_PCIE_SRC_RSRP_GRP); + + ipa_reg_save.rsrc_cnts.ddr.src.hps_dmars = + IPA_DEBUG_TESTBUS_GET_RSRC_TYPE_CNT(rsrc_type, + IPA_HW_DDR_SRC_RSRP_GRP); + + rsrc_type = 4; + ipa_reg_save.rsrc_cnts.pcie.src.reserved_acks = + IPA_DEBUG_TESTBUS_GET_RSRC_TYPE_CNT(rsrc_type, + IPA_HW_PCIE_SRC_RSRP_GRP); + + ipa_reg_save.rsrc_cnts.ddr.src.reserved_acks = + IPA_DEBUG_TESTBUS_GET_RSRC_TYPE_CNT(rsrc_type, + IPA_HW_DDR_SRC_RSRP_GRP); + + rsrc_type = 5; + ipa_reg_save.rsrc_cnts.pcie.dst.reserved_sectors = + IPA_DEBUG_TESTBUS_GET_RSRC_TYPE_CNT(rsrc_type, + IPA_HW_PCIE_DEST_RSRP_GRP); + + ipa_reg_save.rsrc_cnts.ddr.dst.reserved_sectors = + IPA_DEBUG_TESTBUS_GET_RSRC_TYPE_CNT(rsrc_type, + IPA_HW_DDR_DEST_RSRP_GRP); + + rsrc_type = 6; + ipa_reg_save.rsrc_cnts.pcie.dst.dps_dmars = + IPA_DEBUG_TESTBUS_GET_RSRC_TYPE_CNT(rsrc_type, + IPA_HW_PCIE_DEST_RSRP_GRP); + + ipa_reg_save.rsrc_cnts.ddr.dst.dps_dmars = + IPA_DEBUG_TESTBUS_GET_RSRC_TYPE_CNT(rsrc_type, + IPA_HW_DDR_DEST_RSRP_GRP); +} + +/* + * FUNCTION: ipa_hal_save_regs_ipa_cmdq + * + * This function saves the various IPA CMDQ registers + * + * @param + * + * @return + */ +static void ipa_hal_save_regs_ipa_cmdq(void) +{ + int32_t i; + union ipa_hwio_def_ipa_rx_hps_cmdq_cmd_u rx_hps_cmdq_cmd = { { 0 } }; + union ipa_hwio_def_ipa_hps_dps_cmdq_cmd_u hps_dps_cmdq_cmd = { { 0 } }; + union ipa_hwio_def_ipa_dps_tx_cmdq_cmd_u dps_tx_cmdq_cmd = { { 0 } }; + union ipa_hwio_def_ipa_ackmngr_cmdq_cmd_u ackmngr_cmdq_cmd = { { 0 } }; + union ipa_hwio_def_ipa_prod_ackmngr_cmdq_cmd_u + prod_ackmngr_cmdq_cmd = { { 0 } }; + union ipa_hwio_def_ipa_ntf_tx_cmdq_cmd_u ntf_tx_cmdq_cmd = { { 0 } }; + + /* Save RX_HPS CMDQ */ + for (i = 0; i < IPA_DEBUG_CMDQ_HPS_SELECT_NUM_GROUPS; i++) { + rx_hps_cmdq_cmd.def.rd_req = 0; + rx_hps_cmdq_cmd.def.cmd_client = i; + IPA_MASKED_WRITE_SCALER_REG(IPA_RX_HPS_CMDQ_CMD, + rx_hps_cmdq_cmd.value); + ipa_reg_save.ipa.dbg.ipa_rx_hps_cmdq_count_arr[i].value = + IPA_READ_SCALER_REG(IPA_RX_HPS_CMDQ_COUNT); + ipa_reg_save.ipa.dbg.ipa_rx_hps_cmdq_status_arr[i].value = + IPA_READ_SCALER_REG(IPA_RX_HPS_CMDQ_STATUS); + rx_hps_cmdq_cmd.def.rd_req = 1; + rx_hps_cmdq_cmd.def.cmd_client = i; + IPA_MASKED_WRITE_SCALER_REG(IPA_RX_HPS_CMDQ_CMD, + rx_hps_cmdq_cmd.value); + ipa_reg_save.ipa.dbg.ipa_rx_hps_cmdq_data_rd_0_arr[i].value = + IPA_READ_SCALER_REG(IPA_RX_HPS_CMDQ_DATA_RD_0); + ipa_reg_save.ipa.dbg.ipa_rx_hps_cmdq_data_rd_1_arr[i].value = + IPA_READ_SCALER_REG(IPA_RX_HPS_CMDQ_DATA_RD_1); + ipa_reg_save.ipa.dbg.ipa_rx_hps_cmdq_data_rd_2_arr[i].value = + IPA_READ_SCALER_REG(IPA_RX_HPS_CMDQ_DATA_RD_2); + ipa_reg_save.ipa.dbg.ipa_rx_hps_cmdq_data_rd_3_arr[i].value = + IPA_READ_SCALER_REG(IPA_RX_HPS_CMDQ_DATA_RD_3); + } + + /* Save HPS_DPS CMDQ */ + for (i = 0; i < IPA_TESTBUS_SEL_EP_MAX + 1; i++) { + hps_dps_cmdq_cmd.def.rd_req = 0; + hps_dps_cmdq_cmd.def.cmd_client = i; + IPA_MASKED_WRITE_SCALER_REG(IPA_HPS_DPS_CMDQ_CMD, + hps_dps_cmdq_cmd.value); + ipa_reg_save.ipa.dbg.ipa_hps_dps_cmdq_status_arr[i].value = + IPA_READ_SCALER_REG(IPA_HPS_DPS_CMDQ_STATUS); + ipa_reg_save.ipa.dbg.ipa_hps_dps_cmdq_count_arr[i].value = + IPA_READ_SCALER_REG(IPA_HPS_DPS_CMDQ_COUNT); + + hps_dps_cmdq_cmd.def.rd_req = 1; + hps_dps_cmdq_cmd.def.cmd_client = i; + IPA_MASKED_WRITE_SCALER_REG(IPA_HPS_DPS_CMDQ_CMD, + hps_dps_cmdq_cmd.value); + ipa_reg_save.ipa.dbg.ipa_hps_dps_cmdq_data_rd_0_arr[i].value = + IPA_READ_SCALER_REG(IPA_HPS_DPS_CMDQ_DATA_RD_0); + } + + /* Save DPS_TX CMDQ */ + for (i = 0; i < IPA_DEBUG_CMDQ_DPS_SELECT_NUM_GROUPS; i++) { + dps_tx_cmdq_cmd.def.cmd_client = i; + dps_tx_cmdq_cmd.def.rd_req = 0; + IPA_MASKED_WRITE_SCALER_REG(IPA_DPS_TX_CMDQ_CMD, + dps_tx_cmdq_cmd.value); + ipa_reg_save.ipa.dbg.ipa_dps_tx_cmdq_status_arr[i].value = + IPA_READ_SCALER_REG(IPA_DPS_TX_CMDQ_STATUS); + ipa_reg_save.ipa.dbg.ipa_dps_tx_cmdq_count_arr[i].value = + IPA_READ_SCALER_REG(IPA_DPS_TX_CMDQ_COUNT); + + dps_tx_cmdq_cmd.def.cmd_client = i; + dps_tx_cmdq_cmd.def.rd_req = 1; + IPA_MASKED_WRITE_SCALER_REG(IPA_DPS_TX_CMDQ_CMD, + dps_tx_cmdq_cmd.value); + ipa_reg_save.ipa.dbg.ipa_dps_tx_cmdq_data_rd_0_arr[i].value = + IPA_READ_SCALER_REG(IPA_DPS_TX_CMDQ_DATA_RD_0); + } + + /* Save ACKMNGR CMDQ */ + for (i = 0; i < IPA_DEBUG_CMDQ_DPS_SELECT_NUM_GROUPS; i++) { + ackmngr_cmdq_cmd.def.rd_req = 0; + ackmngr_cmdq_cmd.def.cmd_client = i; + IPA_MASKED_WRITE_SCALER_REG(IPA_ACKMNGR_CMDQ_CMD, + ackmngr_cmdq_cmd.value); + ipa_reg_save.ipa.dbg.ipa_ackmngr_cmdq_status_arr[i].value = + IPA_READ_SCALER_REG(IPA_ACKMNGR_CMDQ_STATUS); + ipa_reg_save.ipa.dbg.ipa_ackmngr_cmdq_count_arr[i].value = + IPA_READ_SCALER_REG(IPA_ACKMNGR_CMDQ_COUNT); + + ackmngr_cmdq_cmd.def.rd_req = 1; + ackmngr_cmdq_cmd.def.cmd_client = i; + IPA_MASKED_WRITE_SCALER_REG(IPA_ACKMNGR_CMDQ_CMD, + ackmngr_cmdq_cmd.value); + ipa_reg_save.ipa.dbg.ipa_ackmngr_cmdq_data_rd_arr[i].value = + IPA_READ_SCALER_REG(IPA_ACKMNGR_CMDQ_DATA_RD); + } + + /* Save PROD ACKMNGR CMDQ */ + for (i = 0; i < IPA_TESTBUS_SEL_EP_MAX + 1; i++) { + prod_ackmngr_cmdq_cmd.def.rd_req = 0; + prod_ackmngr_cmdq_cmd.def.cmd_client = i; + IPA_MASKED_WRITE_SCALER_REG(IPA_PROD_ACKMNGR_CMDQ_CMD, + prod_ackmngr_cmdq_cmd.value); + ipa_reg_save.ipa.dbg.ipa_prod_ackmngr_cmdq_status_arr[i].value + = IPA_READ_SCALER_REG( + IPA_PROD_ACKMNGR_CMDQ_STATUS); + ipa_reg_save.ipa.dbg.ipa_prod_ackmngr_cmdq_count_arr[i].value = + IPA_READ_SCALER_REG(IPA_PROD_ACKMNGR_CMDQ_COUNT); + prod_ackmngr_cmdq_cmd.def.rd_req = 1; + prod_ackmngr_cmdq_cmd.def.cmd_client = i; + IPA_MASKED_WRITE_SCALER_REG(IPA_PROD_ACKMNGR_CMDQ_CMD, + prod_ackmngr_cmdq_cmd.value); + ipa_reg_save.ipa.dbg.ipa_prod_ackmngr_cmdq_data_rd_arr[ + i].value = + IPA_READ_SCALER_REG( + IPA_PROD_ACKMNGR_CMDQ_DATA_RD); + } + + /* Save NTF_TX CMDQ */ + for (i = 0; i < IPA_TESTBUS_SEL_EP_MAX + 1; i++) { + ntf_tx_cmdq_cmd.def.rd_req = 0; + ntf_tx_cmdq_cmd.def.cmd_client = i; + IPA_MASKED_WRITE_SCALER_REG(IPA_NTF_TX_CMDQ_CMD, + ntf_tx_cmdq_cmd.value); + ipa_reg_save.ipa.dbg.ipa_ntf_tx_cmdq_status_arr[i].value = + IPA_READ_SCALER_REG(IPA_NTF_TX_CMDQ_STATUS); + ipa_reg_save.ipa.dbg.ipa_ntf_tx_cmdq_count_arr[i].value = + IPA_READ_SCALER_REG(IPA_NTF_TX_CMDQ_COUNT); + ntf_tx_cmdq_cmd.def.rd_req = 1; + ntf_tx_cmdq_cmd.def.cmd_client = i; + IPA_MASKED_WRITE_SCALER_REG(IPA_NTF_TX_CMDQ_CMD, + ntf_tx_cmdq_cmd.value); + ipa_reg_save.ipa.dbg.ipa_ntf_tx_cmdq_data_rd_0_arr[i].value = + IPA_READ_SCALER_REG(IPA_NTF_TX_CMDQ_DATA_RD_0); + } +} + +/* + * FUNCTION: ipa_hal_save_regs_save_ipa_testbus + * + * This function saves the IPA testbus + * + * @param + * + * @return + */ +static void ipa_hal_save_regs_save_ipa_testbus(void) +{ + s32 sel_internal, sel_external, sel_ep; + union ipa_hwio_def_ipa_testbus_sel_u testbus_sel = { { 0 } }; + + if (ipa_reg_save.ipa.testbus == NULL) { + /* + * Test-bus structure not allocated - exit test-bus collection + */ + IPADBG("ipa_reg_save.ipa.testbus was not allocated\n"); + return; + } + + /* Enable Test-bus */ + testbus_sel.value = 0; + testbus_sel.def.testbus_en = true; + + IPA_WRITE_SCALER_REG(IPA_TESTBUS_SEL, testbus_sel.value); + + for (sel_external = 0; + sel_external <= IPA_TESTBUS_SEL_EXTERNAL_MAX; + sel_external++) { + + for (sel_internal = 0; + sel_internal <= IPA_TESTBUS_SEL_INTERNAL_MAX; + sel_internal++) { + + testbus_sel.value = 0; + testbus_sel.def.external_block_select = + sel_external; + testbus_sel.def.internal_block_select = + sel_internal; + + IPA_MASKED_WRITE_SCALER_REG( + IPA_TESTBUS_SEL, + testbus_sel.value); + + ipa_reg_save.ipa.testbus->global.global[ + sel_internal][sel_external].testbus_sel.value = + testbus_sel.value; + + ipa_reg_save.ipa.testbus->global.global[ + sel_internal][sel_external].testbus_data.value = + IPA_READ_SCALER_REG(IPA_DEBUG_DATA); + } + } + + /* Collect per EP test bus */ + for (sel_ep = 0; + sel_ep <= IPA_TESTBUS_SEL_EP_MAX; + sel_ep++) { + + for (sel_external = 0; + sel_external <= + IPA_TESTBUS_SEL_EXTERNAL_MAX; + sel_external++) { + + for (sel_internal = 0; + sel_internal <= + IPA_TESTBUS_SEL_INTERNAL_PIPE_MAX; + sel_internal++) { + + testbus_sel.value = 0; + testbus_sel.def.external_block_select = + sel_external; + testbus_sel.def.internal_block_select = + sel_internal; + + IPA_MASKED_WRITE_SCALER_REG( + IPA_TESTBUS_SEL, + testbus_sel.value); + + ipa_reg_save.ipa.testbus->ep[sel_ep].entry_ep[ + sel_internal][sel_external]. + testbus_sel.value = + testbus_sel.value; + + ipa_reg_save.ipa.testbus->ep[sel_ep].entry_ep[ + sel_internal][sel_external]. + testbus_data.value = + IPA_READ_SCALER_REG( + IPA_DEBUG_DATA); + } + } + } + + /* Disable Test-bus */ + testbus_sel.value = 0; + + IPA_WRITE_SCALER_REG( + IPA_TESTBUS_SEL, + testbus_sel.value); +} + +/* + * FUNCTION: ipa_reg_save_init + * + * This function initializes and memsets the register save struct. + * + * @param + * + * @return + */ +int ipa_reg_save_init(u32 value) +{ + u32 i, num_regs = ARRAY_SIZE(ipa_regs_to_save_array); + + if (!ipa3_ctx->do_register_collection_on_crash) + return 0; + + memset(&ipa_reg_save, value, sizeof(ipa_reg_save)); + + ipa_reg_save.ipa.testbus = NULL; + + if (ipa3_ctx->do_testbus_collection_on_crash) { + memset(ipa_testbus_mem, value, sizeof(ipa_testbus_mem)); + ipa_reg_save.ipa.testbus = + (struct ipa_reg_save_ipa_testbus_s *) ipa_testbus_mem; + } + + /* setup access for register collection/dump on crash */ + IPADBG("Mapping 0x%x bytes starting at 0x%x\n", + ipa3_ctx->entire_ipa_block_size, + ipa3_ctx->ipa_wrapper_base); + + ipa3_ctx->reg_collection_base = + ioremap(ipa3_ctx->ipa_wrapper_base, + ipa3_ctx->entire_ipa_block_size); + + if (!ipa3_ctx->reg_collection_base) { + IPAERR(":register collection ioremap err\n"); + goto alloc_fail1; + } + + num_regs -= + (CONFIG_IPA3_REGDUMP_NUM_EXTRA_ENDP_REGS * + IPA_REG_SAVE_NUM_EXTRA_ENDP_REGS); + + for (i = 0; + i < (CONFIG_IPA3_REGDUMP_NUM_EXTRA_ENDP_REGS * + IPA_REG_SAVE_NUM_EXTRA_ENDP_REGS); + i++) + *(ipa_regs_to_save_array[num_regs + i].dst_addr) = 0x0; + + ipa_reg_save.ipa.ipa_gsi_ptr = NULL; + ipa_reg_save.ipa.ipa_seq_ptr = NULL; + ipa_reg_save.ipa.ipa_hram_ptr = NULL; + ipa_reg_save.ipa.ipa_mbox_ptr = NULL; + ipa_reg_save.ipa.ipa_sram_ptr = NULL; + ipa_reg_save.ipa.ipa_iu_ptr = NULL; + + if (ipa3_ctx->do_ram_collection_on_crash) { + ipa_reg_save.ipa.ipa_iu_ptr = + alloc_and_init(IPA_IU_SIZE, value); + if (!ipa_reg_save.ipa.ipa_iu_ptr) { + IPAERR("ipa_iu_ptr memory alloc failed\n"); + goto alloc_fail2; + } + + ipa_reg_save.ipa.ipa_sram_ptr = + alloc_and_init(IPA_SRAM_SIZE, value); + if (!ipa_reg_save.ipa.ipa_sram_ptr) { + IPAERR("ipa_sram_ptr memory alloc failed\n"); + goto alloc_fail2; + } + + ipa_reg_save.ipa.ipa_mbox_ptr = + alloc_and_init(IPA_MBOX_SIZE, value); + if (!ipa_reg_save.ipa.ipa_mbox_ptr) { + IPAERR("ipa_mbox_ptr memory alloc failed\n"); + goto alloc_fail2; + } + + ipa_reg_save.ipa.ipa_hram_ptr = + alloc_and_init(IPA_HRAM_SIZE, value); + if (!ipa_reg_save.ipa.ipa_hram_ptr) { + IPAERR("ipa_hram_ptr memory alloc failed\n"); + goto alloc_fail2; + } + + ipa_reg_save.ipa.ipa_seq_ptr = + alloc_and_init(IPA_SEQ_SIZE, value); + if (!ipa_reg_save.ipa.ipa_seq_ptr) { + IPAERR("ipa_seq_ptr memory alloc failed\n"); + goto alloc_fail2; + } + + ipa_reg_save.ipa.ipa_gsi_ptr = + alloc_and_init(IPA_GSI_SIZE, value); + if (!ipa_reg_save.ipa.ipa_gsi_ptr) { + IPAERR("ipa_gsi_ptr memory alloc failed\n"); + goto alloc_fail2; + } + } + + return 0; + +alloc_fail2: + kfree(ipa_reg_save.ipa.ipa_seq_ptr); + kfree(ipa_reg_save.ipa.ipa_hram_ptr); + kfree(ipa_reg_save.ipa.ipa_mbox_ptr); + kfree(ipa_reg_save.ipa.ipa_sram_ptr); + kfree(ipa_reg_save.ipa.ipa_iu_ptr); + iounmap(ipa3_ctx->reg_collection_base); +alloc_fail1: + return -ENOMEM; +} + +/* + * FUNCTION: ipa_hal_save_regs_rsrc_db + * + * This function saves the various IPA RSRC_MNGR_DB registers + * + * @param + * + * @return + */ +static void ipa_hal_save_regs_rsrc_db(void) +{ + u32 rsrc_type = 0; + u32 rsrc_id = 0; + u32 rsrc_group = 0; + union ipa_hwio_def_ipa_rsrc_mngr_db_cfg_u + ipa_rsrc_mngr_db_cfg = { { 0 } }; + + ipa_rsrc_mngr_db_cfg.def.rsrc_grp_sel = rsrc_group; + + for (rsrc_type = 0; rsrc_type <= IPA_RSCR_MNGR_DB_RSRC_TYPE_MAX; + rsrc_type++) { + for (rsrc_id = 0; rsrc_id <= IPA_RSCR_MNGR_DB_RSRC_ID_MAX; + rsrc_id++) { + ipa_rsrc_mngr_db_cfg.def.rsrc_id_sel = rsrc_id; + ipa_rsrc_mngr_db_cfg.def.rsrc_type_sel = rsrc_type; + IPA_MASKED_WRITE_SCALER_REG(IPA_RSRC_MNGR_DB_CFG, + ipa_rsrc_mngr_db_cfg.value); + ipa_reg_save.ipa.dbg.ipa_rsrc_mngr_db_rsrc_read_arr + [rsrc_type][rsrc_id].value = + IPA_READ_SCALER_REG( + IPA_RSRC_MNGR_DB_RSRC_READ); + ipa_reg_save.ipa.dbg.ipa_rsrc_mngr_db_list_read_arr + [rsrc_type][rsrc_id].value = + IPA_READ_SCALER_REG( + IPA_RSRC_MNGR_DB_LIST_READ); + } + } +} + +/* + * FUNCTION: ipa_reg_save_anomaly_check + * + * Checks RX state and TX state upon crash dump collection and prints + * anomalies. + * + * TBD- Add more anomaly checks in the future. + * + * @return + */ +static void ipa_reg_save_anomaly_check(void) +{ + if ((ipa_reg_save.ipa.gen.ipa_state.rx_wait != 0) + || (ipa_reg_save.ipa.gen.ipa_state.rx_idle != 1)) { + int i = 0; + + for (i = 0; i < GEN_MAX_n(IPA_STATE_RX_ACTIVE_n) + 1; i++) { + IPADBG( + "RX ACTIVITY_%d, ipa_state.rx_wait = %d, ipa_state.rx_idle = %d, ipa_state_rx_active.endpoints = %d (bitmask)\n", + i, + ipa_reg_save.ipa.gen.ipa_state.rx_wait, + ipa_reg_save.ipa.gen.ipa_state.rx_idle, + ipa_reg_save.ipa.gen.ipa_state_rx_active_n[i].endpoints); + } + if (ipa_reg_save.ipa.gen.ipa_state.tx_idle != 1) { + IPADBG( + "TX ACTIVITY, ipa_state.idle = %d, ipa_state_tx_wrapper.tx_idle = %d\n", + ipa_reg_save.ipa.gen.ipa_state.tx_idle, + ipa_reg_save.ipa.gen.ipa_state_tx_wrapper.tx_idle); + } + } +} diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.5/ipa_reg_dump.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.5/ipa_reg_dump.h new file mode 100644 index 0000000000..cfa940c95d --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/dump/ipa5.5/ipa_reg_dump.h @@ -0,0 +1,2145 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ +#if !defined(_IPA_REG_DUMP_H_) +#define _IPA_REG_DUMP_H_ + +#include +#include + +#include "ipa_i.h" +#include "gsihal.h" +#include "gsihal_reg.h" + +#include "ipa_pkt_cntxt.h" +#include "ipa_hw_common_ex.h" + +#define IPA_0_IPA_WRAPPER_BASE 0 /* required by following includes */ + +#include "ipa_hwio.h" +#include "gsi_hwio.h" +#include "ipa_gcc_hwio.h" + +#include "ipa_hwio_def.h" +#include "gsi_hwio_def.h" +#include "ipa_gcc_hwio_def.h" + +#define IPA_DEBUG_CMDQ_DPS_SELECT_NUM_GROUPS 0x6 +#define IPA_DEBUG_CMDQ_HPS_SELECT_NUM_GROUPS 0x4 +#define IPA_DEBUG_TESTBUS_RSRC_NUM_EP 7 +#define IPA_DEBUG_TESTBUS_RSRC_NUM_GRP 3 +#define IPA_TESTBUS_SEL_EP_MAX 0x1F +#define IPA_TESTBUS_SEL_EXTERNAL_MAX 0x40 +#define IPA_TESTBUS_SEL_INTERNAL_MAX 0xFF +#define IPA_TESTBUS_SEL_INTERNAL_PIPE_MAX 0x40 +#define IPA_DEBUG_CMDQ_ACK_SELECT_NUM_GROUPS 0x9 +#define IPA_RSCR_MNGR_DB_RSRC_ID_MAX 0x3F +#define IPA_RSCR_MNGR_DB_RSRC_TYPE_MAX 0xA +#define IPA_REG_SAVE_FC_STATE_OFFSET 7 +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_ZEROS (0x0) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MCS_0 (0x1) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MCS_1 (0x2) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MCS_2 (0x3) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MCS_3 (0x4) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MCS_4 (0x5) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_DB_ENG (0x9) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_0 (0xB) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_1 (0xC) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_2 (0xD) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_3 (0xE) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_4 (0xF) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_5 (0x10) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_6 (0x11) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_7 (0x12) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_EVE_0 (0x13) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_EVE_1 (0x14) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_EVE_2 (0x15) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_EVE_3 (0x16) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_EVE_4 (0x17) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_EVE_5 (0x18) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IE_0 (0x1B) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IE_1 (0x1C) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IC_0 (0x1F) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IC_1 (0x20) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IC_2 (0x21) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IC_3 (0x22) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IC_4 (0x23) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MOQA_0 (0x27) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MOQA_1 (0x28) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MOQA_2 (0x29) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MOQA_3 (0x2A) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_TMR_0 (0x2B) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_TMR_1 (0x2C) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_TMR_2 (0x2D) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_TMR_3 (0x2E) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_RD_WR_0 (0x33) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_RD_WR_1 (0x34) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_RD_WR_2 (0x35) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_RD_WR_3 (0x36) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_CSR (0x3A) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_SDMA_0 (0x3C) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_SDMA_1 (0x3D) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IE_2 (0x1D) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_CSR_1 (0x3E) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_CSR_2 (0x3F) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MCS_5 (0x40) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IC_5 (0x41) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_CSR_3 (0x42) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_TLV_0 (0x43) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_8 (0x44) +#define IPA_DEBUG_TESTBUS_DEF_EXTERNAL 50 +#define IPA_DEBUG_TESTBUS_DEF_INTERNAL 6 +#define IPA_REG_SAVE_GSI_NUM_EE 3 +#define IPA_REG_SAVE_NUM_EXTRA_ENDP_REGS 22 +#define IPA_GSI_OFFSET_WORDS_SCRATCH_FOR_SEQ_LOW 18 +#define IPA_GSI_OFFSET_WORDS_SCRATCH_FOR_SEQ_HIGH 19 +#define IPA_DEBUG_TESTBUS_RSRC_TYPE_CNT_BIT_MASK 0x7E000 +#define IPA_DEBUG_TESTBUS_RSRC_TYPE_CNT_SHIFT 13 +#define IPA_REG_SAVE_HWP_GSI_EE 2 +#define GSI_HW_DEBUG_SW_MSK_REG_ARRAY_LENGTH 9 +#define GSI_HW_DEBUG_SW_MSK_REG_MAXk 2 + +/* + * A structure used to map a source address to destination address... + */ +struct map_src_dst_addr_s { + u32 src_addr; /* register offset to copy value from */ + u32 *dst_addr; /* memory address to copy register value to */ + u8 perm; /* r\w permission as parsed from hwio */ +}; + +/* a macro to generate a number of MAX n allowed in a register + * who has suffix of _n + */ +#define GEN_MAX_n(reg_name) \ + HWIO_ ## reg_name ## _MAXn + +/* a macro to generate a number of MAX k allowed in a register + * who has suffix of _k + */ +#define GEN_MAX_k(reg_name) \ + HWIO_ ## reg_name ## _MAXk + +/* + * A macro to generate the names of scaler (ie. non-vector) registers + * that reside in the *hwio.h files (said files contain the manifest + * constants for the registers' offsets in the register memory map). + */ +#define GEN_SCALER_REG_OFST(reg_name) \ + (HWIO_ ## reg_name ## _ADDR) + +/* + * A macro designed to generate the rmsk associated with reg_name + */ +#define GEN_SCALER_REG_RMSK(reg_name) \ + (HWIO_ ## reg_name ## _RMSK) + +/* + * A macro designed to generate the attr associated with reg_name + * this is actually r\w permissions, bits [1][0] ==> [W][R] + */ +#define REG_READ_PERM BIT(0) +#define REG_WRITE_PERM BIT(1) +#define GEN_REG_ATTR(reg_name) \ + (HWIO_ ## reg_name ## _ATTR) + +/* + * A macro to generate the names of vector registers that reside in + * the *hwio.h files (said files contain the manifest constants for + * the registers' offsets in the register memory map). More + * specifically, this macro will generate access to registers that are + * addressed via one dimension. + */ +#define GEN_1xVECTOR_REG_OFST(reg_name, row) \ + (HWIO_ ## reg_name ## _ADDR(row)) + +/* + * A macro to generate the names of vector registers that reside in + * the *hwio.h files (said files contain the manifest constants for + * the registers' offsets in the register memory map). More + * specifically, this macro will generate access to registers that are + * addressed via two dimensions. + */ +#define GEN_2xVECTOR_REG_OFST(reg_name, row, col) \ + (HWIO_ ## reg_name ## _ADDR(row, col)) + +/* + * A macro to generate the access to scaler registers that reside in + * the *hwio.h files (said files contain the manifest constants for + * the registers' offsets in the register memory map). More + * specifically, this macro will generate read access from a scaler + * register.. + */ +#define IPA_READ_SCALER_REG(reg_name) \ + HWIO_ ## reg_name ## _IN + +/* + * A macro to generate the access to vector registers that reside in + * the *hwio.h files (said files contain the manifest constants for + * the registers' offsets in the register memory map). More + * specifically, this macro will generate read access from a one + * dimensional vector register... + */ +#define IPA_READ_1xVECTOR_REG(reg_name, row) \ + HWIO_ ## reg_name ## _INI(row) + +/* + * A macro to generate the access to vector registers that reside in + * the *hwio.h files (said files contain the manifest constants for + * the registers' offsets in the register memory map). More + * specifically, this macro will generate read access from a two + * dimensional vector register... + */ +#define IPA_READ_2xVECTOR_REG(reg_name, row, col) \ + HWIO_ ## reg_name ## _INI2(row, col) + +/* + * A macro to generate the access to scaler registers that reside in + * the *hwio.h files (said files contain the manifest constants for + * the registers' offsets in the register memory map). More + * specifically, this macro will generate write access to a scaler + * register.. + */ +#define IPA_WRITE_SCALER_REG(reg_name, val) \ + HWIO_ ## reg_name ## _OUT(val) + +/* + * Similar to the above, but with val masked by the register's rmsk... + */ +#define IPA_MASKED_WRITE_SCALER_REG(reg_name, val) \ + out_dword(GEN_SCALER_REG_OFST(reg_name), \ + (GEN_SCALER_REG_RMSK(reg_name) & val), \ + GEN_REG_ATTR(reg_name)) + +/* + * A macro to generate the access to vector registers that reside in + * the *hwio.h files (said files contain the manifest constants for + * the registers' offsets in the register memory map). More + * specifically, this macro will generate write access to a one + * dimensional vector register... + */ +#define IPA_WRITE_1xVECTOR_REG(reg_name, row, val) \ + HWIO_ ## reg_name ## _OUTI(row, val) + +/* + * A macro to generate the access to vector registers that reside in + * the *hwio.h files (said files contain the manifest constants for + * the registers' offsets in the register memory map). More + * specifically, this macro will generate write access to a two + * dimensional vector register... + */ +#define IPA_WRITE_2xVECTOR_REG(reg_name, row, col, val) \ + HWIO_ ## reg_name ## _OUTI2(row, col, val) + + /* + * Macro that helps generate a mapping between a register's address + * and where the register's value will get stored (ie. source and + * destination address mapping) upon dump... + */ +#define GEN_SRC_DST_ADDR_MAP(reg_name, sub_struct, field_name) \ + { GEN_SCALER_REG_OFST(reg_name), \ + (u32 *)&ipa_reg_save.sub_struct.field_name , \ + GEN_REG_ATTR(reg_name) } + +/* + * Macro to get value of bits 18:13, used tp get rsrc cnts from + * IPA_DEBUG_DATA + */ +#define IPA_DEBUG_TESTBUS_DATA_GET_RSRC_CNT_BITS_FROM_DEBUG_DATA(x) \ + ((x & IPA_DEBUG_TESTBUS_RSRC_TYPE_CNT_BIT_MASK) >> \ + IPA_DEBUG_TESTBUS_RSRC_TYPE_CNT_SHIFT) + +/* + * Macro to get rsrc cnt of specific rsrc type and rsrc grp from test + * bus collected data + */ +#define IPA_DEBUG_TESTBUS_GET_RSRC_TYPE_CNT(rsrc_type, rsrc_grp) \ + IPA_DEBUG_TESTBUS_DATA_GET_RSRC_CNT_BITS_FROM_DEBUG_DATA( \ + ipa_reg_save.ipa.testbus->ep_rsrc[rsrc_type].entry_ep \ + [rsrc_grp].testbus_data.value) + +/* + * Macro to pluck the gsi version from ram. + */ +#define IPA_REG_SAVE_GSI_VER(reg_name, var_name) \ + { GEN_1xVECTOR_REG_OFST(reg_name, 0), \ + (u32 *)&ipa_reg_save.gsi.gen.var_name,\ + GEN_REG_ATTR(reg_name) } +/* + * Macro to define a particular register cfg entry for all 3 EE + * indexed register + */ +#define IPA_REG_SAVE_CFG_ENTRY_GEN_EE(reg_name, var_name) \ + { GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE), \ + (u32 *)&ipa_reg_save.ipa.gen_ee[IPA_HW_Q6_EE].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE), \ + (u32 *)&ipa_reg_save.ipa.gen_ee[IPA_HW_A7_EE].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_UC_EE), \ + (u32 *)&ipa_reg_save.ipa.gen_ee[IPA_HW_UC_EE].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_HWP_EE), \ + (u32 *)&ipa_reg_save.ipa.gen_ee[IPA_HW_HWP_EE].var_name, \ + GEN_REG_ATTR(reg_name) } + +#define IPA_REG_SAVE_CFG_ENTRY_GSI_FIFO(reg_name, var_name, index) \ + { GEN_SCALER_REG_OFST(reg_name), \ + (u32 *)&ipa_reg_save.ipa.gsi_fifo_status[index].var_name, \ + GEN_REG_ATTR(reg_name) } + +/* + * Macro to define a particular register cfg entry for all pipe + * indexed register + */ +#define IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(reg_name, var_name) \ + { 0, 0 } + +/* + * Macro to define a particular register cfg entry for all resource + * group register + */ +#define IPA_REG_SAVE_CFG_ENTRY_SRC_RSRC_GRP(reg_name, var_name) \ + { GEN_1xVECTOR_REG_OFST(reg_name, 0), \ + (u32 *)&ipa_reg_save.ipa.src_rsrc_grp[0].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 1), \ + (u32 *)&ipa_reg_save.ipa.src_rsrc_grp[1].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 2), \ + (u32 *)&ipa_reg_save.ipa.src_rsrc_grp[2].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 3), \ + (u32 *)&ipa_reg_save.ipa.src_rsrc_grp[3].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 4), \ + (u32 *)&ipa_reg_save.ipa.src_rsrc_grp[4].var_name, \ + GEN_REG_ATTR(reg_name) } + +/* + * Macro to define a particular register cfg entry for all resource + * group register + */ +#define IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_GRP(reg_name, var_name) \ + { GEN_1xVECTOR_REG_OFST(reg_name, 0), \ + (u32 *)&ipa_reg_save.ipa.dst_rsrc_grp[0].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 1), \ + (u32 *)&ipa_reg_save.ipa.dst_rsrc_grp[1].var_name, \ + GEN_REG_ATTR(reg_name) } + +/* + * Macro to define a particular register cfg entry for all source + * resource group count register + */ +#define IPA_REG_SAVE_CFG_ENTRY_SRC_RSRC_CNT_GRP(reg_name, var_name) \ + { GEN_1xVECTOR_REG_OFST(reg_name, 0), \ + (u32 *)&ipa_reg_save.ipa.src_rsrc_cnt[0].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 1), \ + (u32 *)&ipa_reg_save.ipa.src_rsrc_cnt[1].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 2), \ + (u32 *)&ipa_reg_save.ipa.src_rsrc_cnt[2].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 3), \ + (u32 *)&ipa_reg_save.ipa.src_rsrc_cnt[3].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 4), \ + (u32 *)&ipa_reg_save.ipa.src_rsrc_cnt[4].var_name, \ + GEN_REG_ATTR(reg_name) } + +/* + * Macro to define a particular register cfg entry for all dest + * resource group count register + */ +#define IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_CNT_GRP(reg_name, var_name) \ + { GEN_1xVECTOR_REG_OFST(reg_name, 0), \ + (u32 *)&ipa_reg_save.ipa.dst_rsrc_cnt[0].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 1), \ + (u32 *)&ipa_reg_save.ipa.dst_rsrc_cnt[1].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 2), \ + (u32 *)&ipa_reg_save.ipa.dst_rsrc_cnt[2].var_name, \ + GEN_REG_ATTR(reg_name) } + +#define IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(reg_name, var_name) \ + { GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE), \ + (u32 *)&ipa_reg_save.gsi.gen_ee[IPA_HW_A7_EE].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE), \ + (u32 *)&ipa_reg_save.gsi.gen_ee[IPA_HW_Q6_EE].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE), \ + (u32 *)&ipa_reg_save.gsi.gen_ee[IPA_REG_SAVE_HWP_GSI_EE].\ + var_name, \ + GEN_REG_ATTR(reg_name) } + +/* + * Macro to define a particular register cfg entry for all GSI EE + * register + */ +#define IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(reg_name, var_name) \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 0), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[0].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 1), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[1].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 2), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[2].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 3), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[3].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 4), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[4].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 5), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[5].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 6), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[6].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 7), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[7].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 8), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[8].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 9), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[9].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 10), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[10].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 11), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[11].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 12), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[12].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 13), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[13].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 14), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[14].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 15), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[15].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 16), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[16].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 17), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[17].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 18), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[18].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 19), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[19].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 20), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[20].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 21), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[21].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 22), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[22].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 23), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[23].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 24), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[24].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 25), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[25].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 26), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[26].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 27), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[27].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 28), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[28].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 29), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[29].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 30), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[30].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_UC_EE, 0), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[0].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_UC_EE, 1), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[1].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_UC_EE, 2), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[2].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_UC_EE, 3), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[3].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_UC_EE, 4), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[4].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_UC_EE, 5), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[5].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_UC_EE, 6), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[6].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_UC_EE, 7), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[7].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 0), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[0].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 1), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[1].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 2), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[2].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 3), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[3].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 4), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[4].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 5), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[5].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 6), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[6].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 7), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[7].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 8), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[8].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 9), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[9].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 10), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[10].var_name, \ + GEN_REG_ATTR(reg_name) } + +/* + * Macro to define a debug SW MSK register entry for all (n, k) + * k bound by GSI_HW_DEBUG_SW_MSK_REG_MAXk + */ +#define IPA_REG_SAVE_GSI_DEBUG_MSK_REG_ENTRY(reg_name, var_name) \ + { GEN_2xVECTOR_REG_OFST(reg_name, 0, 0), \ + (u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[0].var_name[0], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, 0, 1), \ + (u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[0].var_name[1], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, 1, 0), \ + (u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[1].var_name[0], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, 1, 1), \ + (u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[1].var_name[1], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, 2, 0), \ + (u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[2].var_name[0], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, 2, 1), \ + (u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[2].var_name[1], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, 3, 0), \ + (u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[3].var_name[0], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, 3, 1), \ + (u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[3].var_name[1], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, 4, 0), \ + (u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[4].var_name[0], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, 4, 1), \ + (u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[4].var_name[1], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, 5, 0), \ + (u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[5].var_name[0], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, 5, 1), \ + (u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[5].var_name[1], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, 6, 0), \ + (u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[6].var_name[0], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, 6, 1), \ + (u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[6].var_name[1], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, 7, 0), \ + (u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[7].var_name[0], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, 7, 1), \ + (u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[7].var_name[1], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, 8, 0), \ + (u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[8].var_name[0], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, 8, 1), \ + (u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[8].var_name[1], \ + GEN_REG_ATTR(reg_name) } + +#define IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(reg_name, var_name) \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 0), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[0].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 1), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[1].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 2), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[2].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 3), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[3].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 4), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[4].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 5), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[5].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 6), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[6].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 7), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[7].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 8), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[8].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 9), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[9].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 10), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[10].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 11), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[11].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 12), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[12].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 13), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[13].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 14), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[14].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 15), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[15].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 16), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[16].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 17), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[17].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 18), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[18].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 19), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[19].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 20), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[20].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 21), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[21].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 22), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[22].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 23), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[23].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 24), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[24].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 25), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[25].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 26), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[27].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 28), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[28].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 29), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[29].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 30), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[30].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_UC_EE, 0), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.uc[0].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_UC_EE, 1), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.uc[1].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_UC_EE, 2), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.uc[2].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_UC_EE, 3), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.uc[3].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_UC_EE, 4), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.uc[4].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_UC_EE, 5), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.uc[5].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_UC_EE, 6), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.uc[6].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_UC_EE, 7), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.uc[7].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 0), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[0].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 1), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[1].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 2), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[2].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 3), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[3].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 4), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[4].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 5), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[5].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 6), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[6].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 7), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[7].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 8), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[8].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 9), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[9].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 10), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[10].var_name, \ + GEN_REG_ATTR(reg_name) } + +/* + * Macro to define a particular register cfg entry for GSI QSB debug + * registers + */ +#define IPA_REG_SAVE_CFG_ENTRY_GSI_QSB_DEBUG(reg_name, var_name) \ + { GEN_1xVECTOR_REG_OFST(reg_name, 0), \ + (u32 *)&ipa_reg_save.gsi.debug.gsi_qsb_debug.var_name[0], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 1), \ + (u32 *)&ipa_reg_save.gsi.debug.gsi_qsb_debug.var_name[1], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 2), \ + (u32 *)&ipa_reg_save.gsi.debug.gsi_qsb_debug.var_name[2], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 3), \ + (u32 *)&ipa_reg_save.gsi.debug.gsi_qsb_debug.var_name[3], \ + GEN_REG_ATTR(reg_name) } + +#define IPA_REG_SAVE_RX_SPLT_CMDQ(reg_name, var_name) \ + { GEN_1xVECTOR_REG_OFST(reg_name, 0), \ + (u32 *)&ipa_reg_save.ipa.dbg.var_name[0], \ + GEN_REG_ATTR(reg_name)}, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 1), \ + (u32 *)&ipa_reg_save.ipa.dbg.var_name[1], \ + GEN_REG_ATTR(reg_name)}, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 2), \ + (u32 *)&ipa_reg_save.ipa.dbg.var_name[2], \ + GEN_REG_ATTR(reg_name)}, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 3), \ + (u32 *)&ipa_reg_save.ipa.dbg.var_name[3], \ + GEN_REG_ATTR(reg_name) } + +/* + * Macros to save array registers + */ + +/* + * helper macro to save array register of MAXn = 0 + */ +#define GEN_SRC_DST_ADDR_MAP_ARR_0(reg_name, sub_struct, var_name) \ + { GEN_1xVECTOR_REG_OFST(reg_name, 0), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[0], \ + GEN_REG_ATTR(reg_name) } + +/* + * helper macro to save array register of MAXn = 1 + */ +#define GEN_SRC_DST_ADDR_MAP_ARR_1(reg_name, sub_struct, var_name) \ + { GEN_1xVECTOR_REG_OFST(reg_name, 0), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[0], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 1), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[1], \ + GEN_REG_ATTR(reg_name) } + /* + * helper macro to save array register of MAXn = 31 + */ +#define GEN_SRC_DST_ADDR_MAP_ARR_31(reg_name, sub_struct, var_name) \ + { GEN_1xVECTOR_REG_OFST(reg_name, 0), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[0], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 1), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[1], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 2), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[2], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 3), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[3], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 4), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[4], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 5), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[5], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 6), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[6], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 7), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[7], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 8), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[8], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 9), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[9], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 10), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[10], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 11), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[11], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 12), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[12], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 13), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[13], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 14), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[14], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 15), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[15], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 16), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[16], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 17), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[17], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 18), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[18], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 19), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[19], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 20), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[20], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 21), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[21], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 22), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[22], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 23), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[23], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 24), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[24], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 25), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[25], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 26), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[26], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 27), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[27], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 28), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[28], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 29), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[29], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 30), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[30], \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 31), \ + (u32 *)&ipa_reg_save.sub_struct.var_name[31], \ + GEN_REG_ATTR(reg_name) } + + +#define __IPA_CONCATENATE(A, B) A ## B +#define IPA_CONCATENATE(A, B) __IPA_CONCATENATE(A, B) + +/* + * helper macro to save array register + */ +#define GEN_SRC_DST_ADDR_MAP_ARR(reg_name, sub_struct, var_name) \ + IPA_CONCATENATE(GEN_SRC_DST_ADDR_MAP_ARR_, \ + GEN_MAX_n(reg_name))(reg_name, sub_struct, var_name) + + +/* + * Macros to save multi EE array registers + */ + +/* + * helper macro to save EE array register of MAXk = 0 + */ +#define GEN_SRC_DST_ADDR_MAP_EE_n_REG_k_ARR_0(reg_name, sub_struct, var_name) \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 0), \ + (u32 *)&ipa_reg_save.sub_struct[IPA_HW_A7_EE].var_name.arr[0].value, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 0), \ + (u32 *)&ipa_reg_save.sub_struct[IPA_HW_Q6_EE].var_name.arr[0].value, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_UC_EE, 0), \ + (u32 *)&ipa_reg_save.sub_struct[IPA_HW_UC_EE].var_name.arr[0].value, \ + GEN_REG_ATTR(reg_name) } + +/* + * helper macro to save EE array register of MAXk = 1 + */ +#define GEN_SRC_DST_ADDR_MAP_EE_n_REG_k_ARR_1(reg_name, sub_struct, var_name) \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 0), \ + (u32 *)&ipa_reg_save.sub_struct[IPA_HW_A7_EE].var_name.arr[0].value, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 1), \ + (u32 *)&ipa_reg_save.sub_struct[IPA_HW_A7_EE].var_name.arr[1].value, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 0), \ + (u32 *)&ipa_reg_save.sub_struct[IPA_HW_Q6_EE].var_name.arr[0].value, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 1), \ + (u32 *)&ipa_reg_save.sub_struct[IPA_HW_Q6_EE].var_name.arr[1].value, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_UC_EE, 0), \ + (u32 *)&ipa_reg_save.sub_struct[IPA_HW_UC_EE].var_name.arr[0].value, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_UC_EE, 1), \ + (u32 *)&ipa_reg_save.sub_struct[IPA_HW_UC_EE].var_name.arr[1].value, \ + GEN_REG_ATTR(reg_name) } + +/* + * helper macro to save EE n reg k array register + */ +#define GEN_SRC_DST_ADDR_MAP_EE_n_REG_k_ARR(reg_name, sub_struct, var_name) \ + IPA_CONCATENATE(GEN_SRC_DST_ADDR_MAP_EE_n_REG_k_ARR_, \ + GEN_MAX_k(reg_name))(reg_name, sub_struct, var_name) + +/* + * helper macro to save EE n array register + */ +#define GEN_SRC_DST_ADDR_MAP_EE_n_ARR(reg_name, sub_struct, var_name) \ + { GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE), \ + (u32 *)&ipa_reg_save.sub_struct[IPA_HW_Q6_EE].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE), \ + (u32 *)&ipa_reg_save.sub_struct[IPA_HW_A7_EE].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_UC_EE), \ + (u32 *)&ipa_reg_save.sub_struct[IPA_HW_UC_EE].var_name, \ + GEN_REG_ATTR(reg_name) }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE), \ + (u32 *)&ipa_reg_save.sub_struct[IPA_REG_SAVE_HWP_GSI_EE].\ + var_name, \ + GEN_REG_ATTR(reg_name) } + +/* + * helper macro to wrap struct intended for array as regs array + * in order to create array with max_k == 1 we need to declare + * it as arr[max_k + 1] -> arr[2] + */ +#define GEN_REGS_ARRAY(struct_name, reg_name) \ + struct IPA_CONCATENATE(struct_name, _arr) { \ + union struct_name arr[GEN_MAX_k(reg_name) + 1]; \ + } + +//#define REGS_ARRAY struct struct_name regs[GEN_MAX_k(reg_name)] + +/* + * IPA HW Platform Type + */ +enum ipa_hw_ee_e { + IPA_HW_A7_EE = 0, /* A7's execution environment */ + IPA_HW_Q6_EE = 1, /* Q6's execution environment */ + IPA_HW_UC_EE = 2, /* uC's execution environment */ + IPA_HW_HWP_EE = 3, /* HWP's execution environment */ + IPA_HW_EE_MAX, /* Max EE to support */ +}; + +#define IPA_MAX_EE_TO_COLLECT IPA_HW_UC_EE + +/* + * General IPA register save data struct (ie. this is where register + * values, once read, get placed... + */ +struct ipa_gen_regs_s { + struct ipa_hwio_def_ipa_state_s + ipa_state; + struct ipa_hwio_def_ipa_state_rx_active_n_s + ipa_state_rx_active_n[GEN_MAX_n(IPA_STATE_RX_ACTIVE_n) + 1]; + struct ipa_hwio_def_ipa_state_tx_wrapper_s + ipa_state_tx_wrapper; + struct ipa_hwio_def_ipa_state_tx_s + ipa_state_tx; + struct ipa_hwio_def_ipa_state_tx_holb_mask_dps_tx_0_s + ipa_state_tx_holb_mask_dps_tx_0; + struct ipa_hwio_def_ipa_state_tx_holb_mask_dps_tx_1_s + ipa_state_tx_holb_mask_dps_tx_1; + struct ipa_hwio_def_ipa_state_tx_holb_mask_ntf_tx_0_s + ipa_state_tx_holb_mask_ntf_tx_0; + struct ipa_hwio_def_ipa_state_tx_holb_mask_ntf_tx_1_s + ipa_state_tx_holb_mask_ntf_tx_1; + struct ipa_hwio_def_ipa_state_aggr_active_n_s + ipa_state_aggr_active_n[GEN_MAX_n(IPA_STATE_AGGR_ACTIVE_n) + 1]; + struct ipa_hwio_def_ipa_state_dfetcher_s + ipa_state_dfetcher; + struct ipa_hwio_def_ipa_state_gsi_aos_s + ipa_state_gsi_aos; + struct ipa_hwio_def_ipa_state_gsi_if_s + ipa_state_gsi_if; + struct ipa_hwio_def_ipa_dpl_timer_lsb_s + ipa_dpl_timer_lsb; + struct ipa_hwio_def_ipa_dpl_timer_msb_s + ipa_dpl_timer_msb; + struct ipa_hwio_def_ipa_proc_iph_cfg_s + ipa_proc_iph_cfg; + struct ipa_hwio_def_ipa_route_s + ipa_route; + struct ipa_hwio_def_ipa_spare_reg_1_s + ipa_spare_reg_1; + struct ipa_hwio_def_ipa_cons_log_s + ipa_cons_log; + struct ipa_hwio_def_ipa_log_buf_hw_cmd_cfg_s + ipa_log_buf_hw_cmd_cfg; + struct ipa_hwio_def_ipa_log_buf_hw_cmd_addr_s + ipa_log_buf_hw_cmd_addr; + struct ipa_hwio_def_ipa_log_buf_hw_cmd_write_ptr_s + ipa_log_buf_hw_cmd_write_ptr; + struct ipa_hwio_def_ipa_log_buf_hw_cmd_ram_ptr_s + ipa_log_buf_hw_cmd_ram_ptr; + struct ipa_hwio_def_ipa_comp_hw_version_s + ipa_comp_hw_version; + struct ipa_hwio_def_ipa_filt_rout_cache_cfg_s + ipa_filt_rout_cache_cfg; + struct ipa_hwio_def_ipa_filt_rout_cache_flush_s + ipa_filt_rout_cache_flush; + struct ipa_hwio_def_ipa_state_fetcher_s + ipa_state_fetcher; + struct ipa_hwio_def_ipa_state_fetcher_mask_0_s + ipa_state_fetcher_mask_0; + struct ipa_hwio_def_ipa_state_fetcher_mask_1_s + ipa_state_fetcher_mask_1; + struct ipa_hwio_def_ipa_state_fetcher_mask_2_s + ipa_state_fetcher_mask_2; + struct ipa_hwio_def_ipa_ipv4_filter_init_values_s + ipa_ipv4_filter_init_values; + struct ipa_hwio_def_ipa_ipv6_filter_init_values_s + ipa_ipv6_filter_init_values; + struct ipa_hwio_def_ipa_ipv4_route_init_values_s + ipa_ipv4_route_init_values; + struct ipa_hwio_def_ipa_ipv6_route_init_values_s + ipa_ipv6_route_init_values; + struct ipa_hwio_def_ipa_log_buf_hw_cmd_noc_master_sel_s + ipa_log_buf_hw_cmd_noc_master_sel; + struct ipa_hwio_def_ipa_state_acl_s + ipa_state_acl; + struct ipa_hwio_def_ipa_sys_pkt_proc_cntxt_base_s + ipa_sys_pkt_proc_cntxt_base; + struct ipa_hwio_def_ipa_sys_pkt_proc_cntxt_base_msb_s + ipa_sys_pkt_proc_cntxt_base_msb; + struct ipa_hwio_def_ipa_local_pkt_proc_cntxt_base_s + ipa_local_pkt_proc_cntxt_base; + struct ipa_hwio_def_ipa_rsrc_grp_cfg_s + ipa_rsrc_grp_cfg; + struct ipa_hwio_def_ipa_rsrc_grp_cfg_ext_s + ipa_rsrc_grp_cfg_ext; + struct ipa_hwio_def_ipa_comp_cfg_s + ipa_comp_cfg; + struct ipa_hwio_def_ipa_state_prod_dpl_fifo_s + ipa_state_dpl_fifo; + struct ipa_hwio_def_ipa_state_nlo_aggr_s + ipa_state_nlo_aggr; + struct ipa_hwio_def_ipa_state_coal_master_s + ipa_state_coal_master; + struct ipa_hwio_def_ipa_state_coal_master_1_s + ipa_state_coal_master_1; + struct ipa_hwio_def_ipa_state_coal_master_1_s + ipa_state_coal_master_2; + struct ipa_hwio_def_ipa_state_coal_master_1_s + ipa_state_coal_master_3; + struct ipa_hwio_def_ipa_coal_evict_lru_s + ipa_coal_evict_lru; + struct ipa_hwio_def_ipa_coal_qmap_cfg_s + ipa_coal_qmap_cfg; + struct ipa_hwio_def_ipa_tag_timer_s + ipa_tag_timer; + struct ipa_hwio_def_ipa_nlo_pp_cfg1_s + ipa_nlo_pp_cfg1; + struct ipa_hwio_def_ipa_nlo_pp_cfg2_s + ipa_nlo_pp_cfg2; + struct ipa_hwio_def_ipa_nlo_min_dsm_cfg_s + ipa_nlo_min_dsm_cfg; + struct ipa_hwio_def_ipa_nlo_vp_aggr_cfg_lsb_n_s + ipa_nlo_vp_aggr_cfg_lsb_n[GEN_MAX_n(IPA_NLO_VP_AGGR_CFG_LSB_n) + 1]; + struct ipa_hwio_def_ipa_nlo_vp_limit_cfg_n_s + ipa_nlo_vp_limit_cfg_n[GEN_MAX_n(IPA_NLO_VP_LIMIT_CFG_n) + 1]; + struct ipa_hwio_def_ipa_nlo_vp_flush_req_s + ipa_nlo_vp_flush_req; + struct ipa_hwio_def_ipa_nlo_vp_flush_cookie_s + ipa_nlo_vp_flush_cookie; + struct ipa_hwio_def_ipa_nlo_vp_flush_ack_s + ipa_nlo_vp_flush_ack; + struct ipa_hwio_def_ipa_nlo_vp_dsm_open_s + ipa_nlo_vp_dsm_open; + struct ipa_hwio_def_ipa_nlo_vp_qbap_open_s + ipa_nlo_vp_qbap_open; + struct ipa_hwio_def_ipa_qsb_max_reads_s + ipa_qsb_max_reads; + struct ipa_hwio_def_ipa_qsb_max_writes_s + ipa_qsb_max_writes; + struct ipa_hwio_def_ipa_idle_indication_cfg_s + ipa_idle_indication_cfg; + struct ipa_hwio_def_ipa_clkon_cfg_s + ipa_clkon_cfg; + struct ipa_hwio_def_ipa_timers_xo_clk_div_cfg_s + ipa_timers_xo_clk_div_cfg; + struct ipa_hwio_def_ipa_timers_pulse_gran_cfg_s + ipa_timers_pulse_gran_cfg; + struct ipa_hwio_def_ipa_qtime_timestamp_cfg_s + ipa_qtime_timestamp_cfg; + struct ipa_hwio_def_ipa_flavor_0_s + ipa_flavor_0; + struct ipa_hwio_def_ipa_flavor_1_s + ipa_flavor_1; + struct ipa_hwio_def_ipa_flavor_2_s + ipa_flavor_2; + struct ipa_hwio_def_ipa_flavor_3_s + ipa_flavor_3; + struct ipa_hwio_def_ipa_flavor_4_s + ipa_flavor_4; + struct ipa_hwio_def_ipa_flavor_5_s + ipa_flavor_5; + struct ipa_hwio_def_ipa_flavor_6_s + ipa_flavor_6; + struct ipa_hwio_def_ipa_flavor_7_s + ipa_flavor_7; + struct ipa_hwio_def_ipa_flavor_8_s + ipa_flavor_8; + struct ipa_hwio_def_ipa_flavor_9_s + ipa_flavor_9; + struct ipa_hwio_def_ipa_flavor_10_s + ipa_flavor_10; + struct ipa_hwio_def_ipa_state_tsp_s + ipa_state_tsp; + struct ipa_hwio_def_ipa_filt_rout_cfg_s + ipa_filt_rout_cfg; + struct ipa_hwio_def_ipa_bus_master_legacy_bursts_s + ipa_bus_master_legacy_bursts; + struct ipa_hwio_def_ipa_cons_log_threshold_cfg_s + ipa_cons_log_threshold_cfg; + struct ipa_hwio_def_ipa_prod_log_s + ipa_prod_log; + struct ipa_hwio_def_ipa_prod_log_threshold_cfg_s + ipa_prod_log_threshold_cfg; + struct ipa_hwio_def_ipa_ram_ingress_policer_db_base_addr_s + ipa_ram_ingress_policer_db_base_addr; + struct ipa_hwio_def_ipa_ram_egress_shaping_prod_db_base_addr_s + ipa_ram_egress_shaping_prod_db_base_addr; + struct ipa_hwio_def_ipa_ram_egress_shaping_tc_db_base_addr_s + ipa_ram_egress_shaping_tc_db_base_addr; + struct ipa_hwio_def_ipa_dpl_timer_ctl_sts_s + ipa_dpl_timer_ctl_sts; + struct ipa_hwio_def_ipa_state_coal_slave_s + ipa_state_coal_slave; + struct ipa_hwio_def_ipa_state_rqos_s + ipa_state_rqos; + struct ipa_hwio_def_ipa_ipv4_nat_exc_suppress_rout_table_indx_s + ipa_ipv4_nat_exc_suppress_rout_table_indx; + struct ipa_hwio_def_ipa_ipv6_conn_track_exc_suppress_rout_table_indx_s + ipa_ipv6_conn_track_exc_suppress_rout_table_indx; + struct ipa_hwio_def_ipa_dpl_timer_sw_adj_lsb_s + ipa_dpl_timer_sw_adj_lsb; + struct ipa_hwio_def_ipa_dpl_timer_sw_adj_msb_s + ipa_dpl_timer_sw_adj_msb; + struct ipa_hwio_def_ipa_tsp_qm_external_baddr_lsb_s + ipa_tsp_qm_external_baddr_lsb; + struct ipa_hwio_def_ipa_tsp_qm_external_baddr_msb_s + ipa_tsp_qm_external_baddr_msb; + struct ipa_hwio_def_ipa_tsp_qm_external_size_s + ipa_tsp_qm_external_size; + struct ipa_hwio_def_ipa_tsp_ingress_policing_cfg_s + ipa_tsp_ingress_policing_cfg; + struct ipa_hwio_def_ipa_tsp_egress_policing_cfg_s + ipa_tsp_egress_policing_cfg; + struct ipa_hwio_def_ipa_stat_tsp_drop_base_s + ipa_stat_tsp_drop_base; + struct ipa_hwio_def_ipa_state_qmngr_queue_nonempty_s + ipa_state_qmngr_queue_nonempty; + struct ipa_hwio_def_ipa_state_prod_dpl_fifo_s + ipa_state_prod_dpl_fifo; +}; + +/* + * General IPA register save data struct + */ +struct ipa_reg_save_gen_ee_s { + struct ipa_hwio_def_ipa_irq_stts_ee_n_s + ipa_irq_stts_ee_n; + struct ipa_hwio_def_ipa_irq_en_ee_n_s + ipa_irq_en_ee_n; + struct ipa_hwio_def_ipa_fec_fatal_addr_ee_n_s + ipa_fec_fatal_addr_ee_n; + struct ipa_hwio_def_ipa_fec_fatal_attr_ee_n_s + ipa_fec_fatal_attr_ee_n; + struct ipa_hwio_def_ipa_snoc_fec_ee_n_s + ipa_snoc_fec_ee_n; + GEN_REGS_ARRAY(ipa_hwio_def_ipa_holb_drop_irq_info_ee_n_reg_k_u, + IPA_HOLB_DROP_IRQ_INFO_EE_n_REG_k) + ipa_holb_drop_irq_info_ee_n_reg_k; + GEN_REGS_ARRAY(ipa_hwio_def_ipa_suspend_irq_info_ee_n_reg_k_u, + IPA_SUSPEND_IRQ_INFO_EE_n_REG_k) + ipa_suspend_irq_info_ee_n_reg_k; + GEN_REGS_ARRAY(ipa_hwio_def_ipa_suspend_irq_en_ee_n_reg_k_u, + IPA_SUSPEND_IRQ_EN_EE_n_REG_k) + ipa_suspend_irq_en_ee_n_reg_k; +}; + +/* + * statistics IPA register save data struct + */ + +struct ipa_reg_save_stat_ee_s { + struct ipa_hwio_def_ipa_stat_quota_base_n_s + ipa_stat_quota_base_n; + struct ipa_hwio_def_ipa_stat_tethering_base_n_s + ipa_stat_tethering_base_n; + struct ipa_hwio_def_ipa_stat_drop_cnt_base_n_s + ipa_stat_drop_cnt_base_n; + GEN_REGS_ARRAY(ipa_hwio_def_ipa_stat_quota_mask_ee_n_reg_k_u, + IPA_STAT_QUOTA_MASK_EE_n_REG_k) + ipa_stat_quota_mask_ee_n_reg_k; + GEN_REGS_ARRAY(ipa_hwio_def_ipa_stat_tethering_mask_ee_n_reg_k_u, + IPA_STAT_TETHERING_MASK_EE_n_REG_k) + ipa_stat_tethering_mask_ee_n_reg_k; + GEN_REGS_ARRAY(ipa_hwio_def_ipa_stat_drop_cnt_mask_ee_n_reg_k_u, + IPA_STAT_DROP_CNT_MASK_EE_n_REG_k) + ipa_stat_drop_cnt_mask_ee_n_reg_k; +}; + +/* + * Pipe Endp IPA register save data struct + */ +struct ipa_reg_save_pipe_endp_s { + struct ipa_hwio_def_ipa_endp_init_ctrl_n_s + ipa_endp_init_ctrl_n; + struct ipa_hwio_def_ipa_endp_init_ctrl_scnd_n_s + ipa_endp_init_ctrl_scnd_n; + struct ipa_hwio_def_ipa_endp_init_cfg_n_s + ipa_endp_init_cfg_n; + struct ipa_hwio_def_ipa_endp_init_nat_n_s + ipa_endp_init_nat_n; + struct ipa_hwio_def_ipa_endp_init_hdr_n_s + ipa_endp_init_hdr_n; + struct ipa_hwio_def_ipa_endp_init_hdr_ext_n_s + ipa_endp_init_hdr_ext_n; + struct ipa_hwio_def_ipa_endp_init_hdr_metadata_mask_n_s + ipa_endp_init_hdr_metadata_mask_n; + struct ipa_hwio_def_ipa_endp_init_hdr_metadata_n_s + ipa_endp_init_hdr_metadata_n; + struct ipa_hwio_def_ipa_endp_init_mode_n_s + ipa_endp_init_mode_n; + struct ipa_hwio_def_ipa_endp_init_aggr_n_s + ipa_endp_init_aggr_n; + struct ipa_hwio_def_ipa_endp_init_hol_block_en_n_s + ipa_endp_init_hol_block_en_n; + struct ipa_hwio_def_ipa_endp_init_hol_block_timer_n_s + ipa_endp_init_hol_block_timer_n; + struct ipa_hwio_def_ipa_endp_init_deaggr_n_s + ipa_endp_init_deaggr_n; + struct ipa_hwio_def_ipa_endp_status_n_s + ipa_endp_status_n; + struct ipa_hwio_def_ipa_endp_init_rsrc_grp_n_s + ipa_endp_init_rsrc_grp_n; + struct ipa_hwio_def_ipa_endp_init_seq_n_s + ipa_endp_init_seq_n; + struct ipa_hwio_def_ipa_endp_gsi_cfg_tlv_n_s + ipa_endp_gsi_cfg_tlv_n; + struct ipa_hwio_def_ipa_endp_gsi_cfg_aos_n_s + ipa_endp_gsi_cfg_aos_n; + struct ipa_hwio_def_ipa_endp_gsi_cfg1_n_s + ipa_endp_gsi_cfg1_n; + struct ipa_hwio_def_ipa_filter_cache_cfg_n_s + ipa_filter_cache_cfg_n; + struct ipa_hwio_def_ipa_router_cache_cfg_n_s + ipa_router_cache_cfg_n; + struct ipa_hwio_def_ipa_endp_init_nat_exc_suppress_n_s + ipa_endp_init_nat_exc_suppress_n; +}; + +/* + * Pipe IPA register save data struct + */ +struct ipa_reg_save_pipe_s { + u8 active; + struct ipa_reg_save_pipe_endp_s endp; +}; + +/* + * HWP IPA register save data struct + */ +struct ipa_reg_save_hwp_s { + struct ipa_hwio_def_ipa_uc_qmb_sys_addr_s + ipa_uc_qmb_sys_addr; + struct ipa_hwio_def_ipa_uc_qmb_local_addr_s + ipa_uc_qmb_local_addr; + struct ipa_hwio_def_ipa_uc_qmb_length_s + ipa_uc_qmb_length; + struct ipa_hwio_def_ipa_uc_qmb_trigger_s + ipa_uc_qmb_trigger; + struct ipa_hwio_def_ipa_uc_qmb_bus_attrib_s + ipa_uc_qmb_bus_attrib; +}; + +/* + * IPA TESTBUS entry struct + */ +struct ipa_reg_save_ipa_testbus_entry_s { + union ipa_hwio_def_ipa_testbus_sel_u testbus_sel; + union ipa_hwio_def_ipa_debug_data_u testbus_data; +}; + +/* IPA TESTBUS global struct */ +struct ipa_reg_save_ipa_testbus_global_s { + struct ipa_reg_save_ipa_testbus_entry_s + global[IPA_TESTBUS_SEL_INTERNAL_MAX + 1] + [IPA_TESTBUS_SEL_EXTERNAL_MAX + 1]; +}; + +/* IPA TESTBUS per EP struct */ +struct ipa_reg_save_ipa_testbus_ep_s { + struct ipa_reg_save_ipa_testbus_entry_s + entry_ep[IPA_TESTBUS_SEL_INTERNAL_PIPE_MAX + 1] + [IPA_TESTBUS_SEL_EXTERNAL_MAX + 1]; +}; + +/* IPA TESTBUS per EP struct */ +struct ipa_reg_save_ipa_testbus_ep_rsrc_s { + struct ipa_reg_save_ipa_testbus_entry_s + entry_ep[IPA_DEBUG_TESTBUS_RSRC_NUM_GRP]; +}; + +/* IPA TESTBUS save data struct */ +struct ipa_reg_save_ipa_testbus_s { + struct ipa_reg_save_ipa_testbus_global_s global; + struct ipa_reg_save_ipa_testbus_ep_s + ep[IPA_TESTBUS_SEL_EP_MAX + 1]; + struct ipa_reg_save_ipa_testbus_ep_rsrc_s + ep_rsrc[IPA_DEBUG_TESTBUS_RSRC_NUM_EP]; +}; + +/* + * Debug IPA register save data struct + */ +struct ipa_reg_save_dbg_s { + struct ipa_hwio_def_ipa_debug_data_s + ipa_debug_data; + struct ipa_hwio_def_ipa_rx_splt_cmdq_cmd_n_s + ipa_rx_splt_cmdq_cmd_n[IPA_RX_SPLT_CMDQ_MAX]; + struct ipa_hwio_def_ipa_rx_splt_cmdq_cfg_n_s + ipa_rx_splt_cmdq_cfg_n[IPA_RX_SPLT_CMDQ_MAX]; + struct ipa_hwio_def_ipa_rx_splt_cmdq_data_wr_0_n_s + ipa_rx_splt_cmdq_data_wr_0_n[IPA_RX_SPLT_CMDQ_MAX]; + struct ipa_hwio_def_ipa_rx_splt_cmdq_data_wr_1_n_s + ipa_rx_splt_cmdq_data_wr_1_n[IPA_RX_SPLT_CMDQ_MAX]; + struct ipa_hwio_def_ipa_rx_splt_cmdq_data_wr_2_n_s + ipa_rx_splt_cmdq_data_wr_2_n[IPA_RX_SPLT_CMDQ_MAX]; + struct ipa_hwio_def_ipa_rx_splt_cmdq_data_wr_3_n_s + ipa_rx_splt_cmdq_data_wr_3_n[IPA_RX_SPLT_CMDQ_MAX]; + struct ipa_hwio_def_ipa_rx_splt_cmdq_data_rd_0_n_s + ipa_rx_splt_cmdq_data_rd_0_n[IPA_RX_SPLT_CMDQ_MAX]; + struct ipa_hwio_def_ipa_rx_splt_cmdq_data_rd_1_n_s + ipa_rx_splt_cmdq_data_rd_1_n[IPA_RX_SPLT_CMDQ_MAX]; + struct ipa_hwio_def_ipa_rx_splt_cmdq_data_rd_2_n_s + ipa_rx_splt_cmdq_data_rd_2_n[IPA_RX_SPLT_CMDQ_MAX]; + struct ipa_hwio_def_ipa_rx_splt_cmdq_data_rd_3_n_s + ipa_rx_splt_cmdq_data_rd_3_n[IPA_RX_SPLT_CMDQ_MAX]; + struct ipa_hwio_def_ipa_rx_splt_cmdq_status_n_s + ipa_rx_splt_cmdq_status_n[IPA_RX_SPLT_CMDQ_MAX]; + + union ipa_hwio_def_ipa_rx_hps_cmdq_cfg_wr_u + ipa_rx_hps_cmdq_cfg_wr; + union ipa_hwio_def_ipa_rx_hps_cmdq_cfg_rd_u + ipa_rx_hps_cmdq_cfg_rd; + + struct ipa_hwio_def_ipa_rx_hps_cmdq_cmd_s + ipa_rx_hps_cmdq_cmd; + struct ipa_hwio_def_ipa_stat_filter_ipv4_base_s + ipa_stat_filter_ipv4_base; + struct ipa_hwio_def_ipa_stat_filter_ipv6_base_s + ipa_stat_filter_ipv6_base; + struct ipa_hwio_def_ipa_stat_router_ipv4_base_s + ipa_stat_router_ipv4_base; + struct ipa_hwio_def_ipa_stat_router_ipv6_base_s + ipa_stat_router_ipv6_base; + union ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_0_u + ipa_rx_hps_cmdq_data_rd_0_arr[ + IPA_DEBUG_CMDQ_HPS_SELECT_NUM_GROUPS]; + union ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_1_u + ipa_rx_hps_cmdq_data_rd_1_arr[ + IPA_DEBUG_CMDQ_HPS_SELECT_NUM_GROUPS]; + union ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_2_u + ipa_rx_hps_cmdq_data_rd_2_arr[ + IPA_DEBUG_CMDQ_HPS_SELECT_NUM_GROUPS]; + union ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_3_u + ipa_rx_hps_cmdq_data_rd_3_arr[ + IPA_DEBUG_CMDQ_HPS_SELECT_NUM_GROUPS]; + union ipa_hwio_def_ipa_rx_hps_cmdq_count_u + ipa_rx_hps_cmdq_count_arr[IPA_DEBUG_CMDQ_HPS_SELECT_NUM_GROUPS]; + union ipa_hwio_def_ipa_rx_hps_cmdq_status_u + ipa_rx_hps_cmdq_status_arr[IPA_DEBUG_CMDQ_HPS_SELECT_NUM_GROUPS]; + struct ipa_hwio_def_ipa_rx_hps_cmdq_status_empty_s + ipa_rx_hps_cmdq_status_empty; + struct ipa_hwio_def_ipa_rsrc_mngr_contexts_s + ipa_rsrc_mngr_contexts; + struct ipa_hwio_def_ipa_snoc_monitoring_cfg_s + ipa_snoc_monitoring_cfg; + struct ipa_hwio_def_ipa_pcie_snoc_monitor_cnt_s + ipa_pcie_snoc_monitor_cnt; + struct ipa_hwio_def_ipa_ddr_snoc_monitor_cnt_s + ipa_ddr_snoc_monitor_cnt; + struct ipa_hwio_def_ipa_gsi_snoc_monitor_cnt_s + ipa_gsi_snoc_monitor_cnt; + struct ipa_hwio_def_ipa_ram_sniffer_hw_base_addr_s + ipa_ram_sniffer_hw_base_addr; + struct ipa_hwio_def_ipa_bresp_db_cfg_s + ipa_bresp_db_cfg; + struct ipa_hwio_def_ipa_bresp_db_data_s + ipa_bresp_db_data; + struct ipa_hwio_def_ipa_bresp_db_data_1_s + ipa_bresp_db_data_1; + struct ipa_hwio_def_ipa_endp_gsi_cons_bytes_tlv_s + ipa_endp_gsi_cons_bytes_tlv; + struct ipa_hwio_def_ipa_ram_gsi_tlv_base_addr_s + ipa_ram_gsi_tlv_base_addr; + struct ipa_hwio_def_ipa_rx_hps_clients_min_depth_0_s + ipa_rx_hps_clients_min_depth_0; + struct ipa_hwio_def_ipa_rx_hps_clients_max_depth_0_s + ipa_rx_hps_clients_max_depth_0; + struct ipa_hwio_def_ipa_hps_dps_cmdq_cmd_s + ipa_hps_dps_cmdq_cmd; + union ipa_hwio_def_ipa_hps_dps_cmdq_data_rd_0_u + ipa_hps_dps_cmdq_data_rd_0_arr[IPA_TESTBUS_SEL_EP_MAX + 1]; + union ipa_hwio_def_ipa_hps_dps_cmdq_count_u + ipa_hps_dps_cmdq_count_arr[IPA_TESTBUS_SEL_EP_MAX + 1]; + union ipa_hwio_def_ipa_hps_dps_cmdq_status_u + ipa_hps_dps_cmdq_status_arr[IPA_TESTBUS_SEL_EP_MAX + 1]; + struct ipa_hwio_def_ipa_hps_dps_cmdq_status_empty_n_s + ipa_hps_dps_cmdq_status_empty_n[ + GEN_MAX_n(IPA_HPS_DPS_CMDQ_STATUS_EMPTY_n) + 1]; + struct ipa_hwio_def_ipa_dps_tx_cmdq_cmd_s + ipa_dps_tx_cmdq_cmd; + union ipa_hwio_def_ipa_dps_tx_cmdq_data_rd_0_u + ipa_dps_tx_cmdq_data_rd_0_arr[ + IPA_DEBUG_CMDQ_DPS_SELECT_NUM_GROUPS]; + union ipa_hwio_def_ipa_dps_tx_cmdq_count_u + ipa_dps_tx_cmdq_count_arr[IPA_DEBUG_CMDQ_DPS_SELECT_NUM_GROUPS]; + union ipa_hwio_def_ipa_dps_tx_cmdq_status_u + ipa_dps_tx_cmdq_status_arr[IPA_DEBUG_CMDQ_DPS_SELECT_NUM_GROUPS]; + struct ipa_hwio_def_ipa_dps_tx_cmdq_status_empty_s + ipa_dps_tx_cmdq_status_empty; + + struct ipa_hwio_def_ipa_ackmngr_cmdq_cmd_s + ipa_ackmngr_cmdq_cmd; + union ipa_hwio_def_ipa_ackmngr_cmdq_data_rd_u + ipa_ackmngr_cmdq_data_rd_arr[ + IPA_DEBUG_CMDQ_ACK_SELECT_NUM_GROUPS]; + union ipa_hwio_def_ipa_ackmngr_cmdq_count_u + ipa_ackmngr_cmdq_count_arr[IPA_DEBUG_CMDQ_ACK_SELECT_NUM_GROUPS]; + union ipa_hwio_def_ipa_ackmngr_cmdq_status_u + ipa_ackmngr_cmdq_status_arr[ + IPA_DEBUG_CMDQ_ACK_SELECT_NUM_GROUPS]; + struct ipa_hwio_def_ipa_ackmngr_cmdq_status_empty_n_s + ipa_ackmngr_cmdq_status_empty_n[ + GEN_MAX_n(IPA_ACKMNGR_CMDQ_STATUS_EMPTY_n) + 1]; + struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_cmd_s + ipa_prod_ackmngr_cmdq_cmd; + union ipa_hwio_def_ipa_prod_ackmngr_cmdq_data_rd_u + ipa_prod_ackmngr_cmdq_data_rd_arr[IPA_TESTBUS_SEL_EP_MAX + 1]; + union ipa_hwio_def_ipa_prod_ackmngr_cmdq_count_u + ipa_prod_ackmngr_cmdq_count_arr[IPA_TESTBUS_SEL_EP_MAX + 1]; + union ipa_hwio_def_ipa_prod_ackmngr_cmdq_status_u + ipa_prod_ackmngr_cmdq_status_arr[IPA_TESTBUS_SEL_EP_MAX + 1]; + struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_status_empty_n_s + ipa_prod_ackmngr_cmdq_status_empty_n[GEN_MAX_n( + IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_n) + 1]; + struct ipa_hwio_def_ipa_ntf_tx_cmdq_cmd_s + ipa_ntf_tx_cmdq_cmd; + union ipa_hwio_def_ipa_ntf_tx_cmdq_data_rd_0_u + ipa_ntf_tx_cmdq_data_rd_0_arr[IPA_TESTBUS_SEL_EP_MAX + 1]; + union ipa_hwio_def_ipa_ntf_tx_cmdq_count_u + ipa_ntf_tx_cmdq_count_arr[IPA_TESTBUS_SEL_EP_MAX + 1]; + union ipa_hwio_def_ipa_ntf_tx_cmdq_status_u + ipa_ntf_tx_cmdq_status_arr[IPA_TESTBUS_SEL_EP_MAX + 1]; + struct ipa_hwio_def_ipa_ntf_tx_cmdq_status_empty_n_s + ipa_ntf_tx_cmdq_status_empty_n[GEN_MAX_n( + IPA_NTF_TX_CMDQ_STATUS_EMPTY_n) + 1]; + union ipa_hwio_def_ipa_rsrc_mngr_db_rsrc_read_u + ipa_rsrc_mngr_db_rsrc_read_arr[IPA_RSCR_MNGR_DB_RSRC_TYPE_MAX + + 1][IPA_RSCR_MNGR_DB_RSRC_ID_MAX + + 1]; + union ipa_hwio_def_ipa_rsrc_mngr_db_list_read_u + ipa_rsrc_mngr_db_list_read_arr[IPA_RSCR_MNGR_DB_RSRC_TYPE_MAX + + 1][IPA_RSCR_MNGR_DB_RSRC_ID_MAX + + 1]; +}; + +/* Source Resource Group IPA register save data struct */ +struct ipa_reg_save_src_rsrc_grp_s { + struct ipa_hwio_def_ipa_src_rsrc_grp_01_rsrc_type_n_s + ipa_src_rsrc_grp_01_rsrc_type_n; + struct ipa_hwio_def_ipa_src_rsrc_grp_23_rsrc_type_n_s + ipa_src_rsrc_grp_23_rsrc_type_n; + struct ipa_hwio_def_ipa_src_rsrc_grp_45_rsrc_type_n_s + ipa_src_rsrc_grp_45_rsrc_type_n; + struct ipa_hwio_def_ipa_src_rsrc_grp_67_rsrc_type_n_s + ipa_src_rsrc_grp_67_rsrc_type_n; + struct ipa_hwio_def_ipa_src_rsrc_type_amount_n_s + ipa_src_rsrc_type_amount; +}; + +/* Source Resource Group IPA register save data struct */ +struct ipa_reg_save_dst_rsrc_grp_s { + struct ipa_hwio_def_ipa_dst_rsrc_grp_01_rsrc_type_n_s + ipa_dst_rsrc_grp_01_rsrc_type_n; + struct ipa_hwio_def_ipa_dst_rsrc_grp_23_rsrc_type_n_s + ipa_dst_rsrc_grp_23_rsrc_type_n; + struct ipa_hwio_def_ipa_dst_rsrc_grp_45_rsrc_type_n_s + ipa_dst_rsrc_grp_45_rsrc_type_n; + struct ipa_hwio_def_ipa_dst_rsrc_grp_67_rsrc_type_n_s + ipa_dst_rsrc_grp_67_rsrc_type_n; + struct ipa_hwio_def_ipa_dst_rsrc_type_amount_n_s + ipa_dst_rsrc_type_amount; +}; + +/* Source Resource Group Count IPA register save data struct */ +struct ipa_reg_save_src_rsrc_cnt_s { + struct ipa_hwio_def_ipa_src_rsrc_grp_0123_rsrc_type_cnt_n_s + ipa_src_rsrc_grp_0123_rsrc_type_cnt_n; + struct ipa_hwio_def_ipa_src_rsrc_grp_4567_rsrc_type_cnt_n_s + ipa_src_rsrc_grp_4567_rsrc_type_cnt_n; +}; + +/* Destination Resource Group Count IPA register save data struct */ +struct ipa_reg_save_dst_rsrc_cnt_s { + struct ipa_hwio_def_ipa_dst_rsrc_grp_0123_rsrc_type_cnt_n_s + ipa_dst_rsrc_grp_0123_rsrc_type_cnt_n; + struct ipa_hwio_def_ipa_dst_rsrc_grp_4567_rsrc_type_cnt_n_s + ipa_dst_rsrc_grp_4567_rsrc_type_cnt_n; +}; + +/* GSI fw version data */ +struct ipa_reg_save_gsi_fw_version_s { + u32 raw_version; + u32 hw_version; + u32 flavor; + u32 fw_version; +}; + +/* GSI General register save data struct */ +struct ipa_reg_save_gsi_gen_s { + struct gsi_hwio_def_gsi_cfg_s + gsi_cfg; + struct gsi_hwio_def_gsi_ree_cfg_s + gsi_ree_cfg; + struct ipa_hwio_def_ipa_0_gsi_top_gsi_inst_ram_n_s + ipa_gsi_top_gsi_inst_ram_n; +}; + +/* GSI General EE register save data struct */ +struct ipa_reg_save_gsi_gen_ee_s { + struct gsi_hwio_def_gsi_manager_ee_qos_n_s + gsi_manager_ee_qos_n; + struct gsi_hwio_def_ee_n_gsi_status_s + ee_n_gsi_status; + struct gsi_hwio_def_ee_n_cntxt_type_irq_s + ee_n_cntxt_type_irq; + struct gsi_hwio_def_ee_n_cntxt_type_irq_msk_s + ee_n_cntxt_type_irq_msk; + GEN_REGS_ARRAY(gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_k_u, + EE_n_CNTXT_SRC_GSI_CH_IRQ_k) + ee_n_cntxt_src_gsi_ch_irq_k; + GEN_REGS_ARRAY(gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_k_u, + EE_n_CNTXT_SRC_EV_CH_IRQ_k) + ee_n_cntxt_src_ev_ch_irq_k; + GEN_REGS_ARRAY(gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_msk_k_u, + EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k) + ee_n_cntxt_src_gsi_ch_irq_msk_k; + GEN_REGS_ARRAY(gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_msk_k_u, + EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k) + ee_n_cntxt_src_ev_ch_irq_msk_k; + GEN_REGS_ARRAY(gsi_hwio_def_ee_n_cntxt_src_ieob_irq_k_u, + EE_n_CNTXT_SRC_IEOB_IRQ_k) + ee_n_cntxt_src_ieob_irq_k; + GEN_REGS_ARRAY(gsi_hwio_def_ee_n_cntxt_src_ieob_irq_msk_k_u, + EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k) + ee_n_cntxt_src_ieob_irq_msk_k; + struct gsi_hwio_def_ee_n_cntxt_gsi_irq_stts_s + ee_n_cntxt_gsi_irq_stts; + struct gsi_hwio_def_ee_n_cntxt_glob_irq_stts_s + ee_n_cntxt_glob_irq_stts; + struct gsi_hwio_def_ee_n_error_log_s + ee_n_error_log; + struct gsi_hwio_def_ee_n_cntxt_scratch_0_s + ee_n_cntxt_scratch_0; + struct gsi_hwio_def_ee_n_cntxt_scratch_1_s + ee_n_cntxt_scratch_1; + struct gsi_hwio_def_ee_n_cntxt_intset_s + ee_n_cntxt_intset; + struct gsi_hwio_def_ee_n_cntxt_msi_base_lsb_s + ee_n_cntxt_msi_base_lsb; + struct gsi_hwio_def_ee_n_cntxt_msi_base_msb_s + ee_n_cntxt_msi_base_msb; +}; + +/* GSI QSB debug register save data struct */ +struct ipa_reg_save_gsi_qsb_debug_s { + struct gsi_hwio_def_gsi_debug_qsb_log_last_misc_idn_s + qsb_log_last_misc[GSI_HW_QSB_LOG_MISC_MAX]; +}; + +static u32 ipa_reg_save_gsi_ch_test_bus_selector_array[] = { + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_ZEROS, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MCS_0, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MCS_1, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MCS_2, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MCS_3, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MCS_4, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_DB_ENG, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_0, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_1, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_2, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_3, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_4, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_5, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_6, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_7, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_EVE_0, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_EVE_1, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_EVE_2, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_EVE_3, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_EVE_4, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_EVE_5, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IE_0, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IE_1, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IC_0, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IC_1, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IC_2, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IC_3, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IC_4, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MOQA_0, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MOQA_1, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MOQA_2, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MOQA_3, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_TMR_0, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_TMR_1, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_TMR_2, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_TMR_3, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_RD_WR_0, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_RD_WR_1, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_RD_WR_2, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_RD_WR_3, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_CSR, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_SDMA_0, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_SDMA_1, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IE_2, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_CSR_1, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_CSR_2, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MCS_5, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IC_5, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_CSR_3, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_TLV_0, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_8, +}; + +/* + * GSI QSB debug bus register save data struct + */ +struct ipa_reg_save_gsi_test_bus_s { + u32 test_bus_selector[ + ARRAY_SIZE(ipa_reg_save_gsi_ch_test_bus_selector_array)]; + struct + gsi_hwio_def_gsi_test_bus_reg_s + test_bus_reg[ARRAY_SIZE(ipa_reg_save_gsi_ch_test_bus_selector_array)]; +}; + +/* GSI debug MCS registers save data struct */ +struct ipa_reg_save_gsi_mcs_regs_s { + struct + gsi_hwio_def_gsi_debug_sw_rf_n_read_s + mcs_reg[HWIO_GSI_DEBUG_SW_RF_n_READ_MAXn + 1]; +}; + +struct ipa_reg_save_gsi_mcs_prof_regs_s { + struct gsi_hwio_def_gsi_mcs_profiling_bp_cnt_lsb_s + gsi_top_gsi_mcs_profiling_bp_cnt_lsb; + struct gsi_hwio_def_gsi_mcs_profiling_bp_cnt_msb_s + gsi_top_gsi_mcs_profiling_bp_cnt_msb; + struct gsi_hwio_def_gsi_mcs_profiling_bp_and_pending_cnt_lsb_s + gsi_top_gsi_mcs_profiling_bp_and_pending_cnt_lsb; + struct gsi_hwio_def_gsi_mcs_profiling_bp_and_pending_cnt_msb_s + gsi_top_gsi_mcs_profiling_bp_and_pending_cnt_msb; + struct gsi_hwio_def_gsi_mcs_profiling_mcs_busy_cnt_lsb_s + gsi_top_gsi_mcs_profiling_mcs_busy_cnt_lsb; + struct gsi_hwio_def_gsi_mcs_profiling_mcs_busy_cnt_msb_s + gsi_top_gsi_mcs_profiling_mcs_busy_cnt_msb; + struct gsi_hwio_def_gsi_mcs_profiling_mcs_idle_cnt_lsb_s + gsi_top_gsi_mcs_profiling_mcs_idle_cnt_lsb; + struct gsi_hwio_def_gsi_mcs_profiling_mcs_idle_cnt_msb_s + gsi_top_gsi_mcs_profiling_mcs_idle_cnt_msb; +}; + +/* GSI debug counters save data struct */ +struct ipa_reg_save_gsi_debug_cnt_s { + struct + gsi_hwio_def_gsi_debug_countern_s + cnt[HWIO_GSI_DEBUG_COUNTERn_MAXn + 1]; +}; + +/* GSI IRAM pointers (IEP) save data struct */ +struct ipa_reg_save_gsi_iram_ptr_regs_s { + struct ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_ch_cmd_s + ipa_gsi_top_gsi_iram_ptr_ch_cmd; + struct ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_ee_generic_cmd_s + ipa_gsi_top_gsi_iram_ptr_ee_generic_cmd; + struct ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_ch_db_s + ipa_gsi_top_gsi_iram_ptr_ch_db; + struct ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_ev_db_s + ipa_gsi_top_gsi_iram_ptr_ev_db; + struct ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_new_re_s + ipa_gsi_top_gsi_iram_ptr_new_re; + struct ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_ch_dis_comp_s + ipa_gsi_top_gsi_iram_ptr_ch_dis_comp; + struct ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_ch_empty_s + ipa_gsi_top_gsi_iram_ptr_ch_empty; + struct ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_event_gen_comp_s + ipa_gsi_top_gsi_iram_ptr_event_gen_comp; + struct ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_timer_expired_s + ipa_gsi_top_gsi_iram_ptr_timer_expired; + struct ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_write_eng_comp_s + ipa_gsi_top_gsi_iram_ptr_write_eng_comp; + struct ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_read_eng_comp_s + ipa_gsi_top_gsi_iram_ptr_read_eng_comp; + struct ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_uc_gp_int_s + ipa_gsi_top_gsi_iram_ptr_uc_gp_int; + struct ipa_hwio_def_ipa_0_gsi_top_gsi_iram_ptr_int_mod_stoped_s + ipa_gsi_top_gsi_iram_ptr_int_mod_stoped; +}; + +/* GSI Debug SW registers save data struct */ +struct gsi_hwio_gsi_top_gsi_debug_sw_msk_regs_entry_rd_s{ + struct gsi_hwio_def_gsi_debug_sw_msk_reg_n_sec_k_rd_s + regs[GSI_HW_DEBUG_SW_MSK_REG_MAXk]; +}; + +struct gsi_hwio_gsi_top_gsi_debug_sw_msk_regs_rd_s{ + struct gsi_hwio_gsi_top_gsi_debug_sw_msk_regs_entry_rd_s + mask_reg[GSI_HW_DEBUG_SW_MSK_REG_ARRAY_LENGTH]; +}; + +/* GSI SHRAM pointers save data struct */ +struct ipa_reg_save_gsi_shram_ptr_regs_s { + struct ipa_hwio_def_ipa_0_gsi_top_gsi_shram_ptr_ch_cntxt_base_addr_s + ipa_gsi_top_gsi_shram_ptr_ch_cntxt_base_addr; + struct ipa_hwio_def_ipa_0_gsi_top_gsi_shram_ptr_ev_cntxt_base_addr_s + ipa_gsi_top_gsi_shram_ptr_ev_cntxt_base_addr; + struct ipa_hwio_def_ipa_0_gsi_top_gsi_shram_ptr_re_storage_base_addr_s + ipa_gsi_top_gsi_shram_ptr_re_storage_base_addr; + struct ipa_hwio_def_ipa_0_gsi_top_gsi_shram_ptr_re_esc_buf_base_addr_s + ipa_gsi_top_gsi_shram_ptr_re_esc_buf_base_addr; + struct ipa_hwio_def_ipa_0_gsi_top_gsi_shram_ptr_ee_scrach_base_addr_s + ipa_gsi_top_gsi_shram_ptr_ee_scrach_base_addr; + struct ipa_hwio_def_ipa_0_gsi_top_gsi_shram_ptr_func_stack_base_addr_s + ipa_gsi_top_gsi_shram_ptr_func_stack_base_addr; +}; + +/* GSI debug register save data struct */ +struct ipa_reg_save_gsi_debug_s { + struct ipa_hwio_def_ipa_0_gsi_top_gsi_debug_busy_reg_s + ipa_gsi_top_gsi_debug_busy_reg; + struct ipa_hwio_def_ipa_0_gsi_top_gsi_debug_pc_from_sw_s + ipa_gsi_top_gsi_debug_pc_from_sw; + struct ipa_hwio_def_ipa_0_gsi_top_gsi_debug_sw_stall_s + ipa_gsi_top_gsi_debug_sw_stall; + struct ipa_hwio_def_ipa_0_gsi_top_gsi_debug_pc_for_debug_s + ipa_gsi_top_gsi_debug_pc_for_debug; + struct ipa_hwio_def_ipa_0_gsi_top_gsi_debug_qsb_log_err_trns_id_s + ipa_gsi_top_gsi_debug_qsb_log_err_trns_id; + struct ipa_reg_save_gsi_qsb_debug_s gsi_qsb_debug; + struct ipa_reg_save_gsi_test_bus_s gsi_test_bus; + struct ipa_reg_save_gsi_mcs_regs_s gsi_mcs_regs; + struct ipa_reg_save_gsi_mcs_prof_regs_s gsi_mcs_prof_regs; + struct ipa_reg_save_gsi_debug_cnt_s gsi_cnt_regs; + struct ipa_reg_save_gsi_iram_ptr_regs_s gsi_iram_ptrs; + struct ipa_reg_save_gsi_shram_ptr_regs_s gsi_shram_ptrs; + struct gsi_hwio_gsi_top_gsi_debug_sw_msk_regs_rd_s + debug_sw_msk; +}; + +/* GSI MCS channel scratch registers save data struct */ +struct ipa_reg_save_gsi_mcs_channel_scratch_regs_s { + struct gsi_hwio_def_gsi_shram_n_s + scratch_for_seq_low; + struct gsi_hwio_def_gsi_shram_n_s + scratch_for_seq_high; +}; + +/* GSI Channel Context register save data struct */ +struct ipa_reg_save_gsi_ch_cntxt_per_ep_s { + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_0_s + ee_n_gsi_ch_k_cntxt_0; + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_1_s + ee_n_gsi_ch_k_cntxt_1; + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_2_s + ee_n_gsi_ch_k_cntxt_2; + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_3_s + ee_n_gsi_ch_k_cntxt_3; + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_4_s + ee_n_gsi_ch_k_cntxt_4; + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_5_s + ee_n_gsi_ch_k_cntxt_5; + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_6_s + ee_n_gsi_ch_k_cntxt_6; + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_7_s + ee_n_gsi_ch_k_cntxt_7; + struct gsi_hwio_def_ee_n_gsi_ch_k_re_fetch_read_ptr_s + ee_n_gsi_ch_k_re_fetch_read_ptr; + struct gsi_hwio_def_ee_n_gsi_ch_k_re_fetch_write_ptr_s + ee_n_gsi_ch_k_re_fetch_write_ptr; + struct gsi_hwio_def_ee_n_gsi_ch_k_qos_s + ee_n_gsi_ch_k_qos; + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_0_s + ee_n_gsi_ch_k_scratch_0; + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_1_s + ee_n_gsi_ch_k_scratch_1; + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_2_s + ee_n_gsi_ch_k_scratch_2; + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_3_s + ee_n_gsi_ch_k_scratch_3; + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_4_s + ee_n_gsi_ch_k_scratch_4; + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_5_s + ee_n_gsi_ch_k_scratch_5; + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_6_s + ee_n_gsi_ch_k_scratch_6; + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_7_s + ee_n_gsi_ch_k_scratch_7; + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_8_s + ee_n_gsi_ch_k_scratch_8; + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_9_s + ee_n_gsi_ch_k_scratch_9; + struct gsi_hwio_def_gsi_map_ee_n_ch_k_vp_table_s + gsi_map_ee_n_ch_k_vp_table; + struct ipa_reg_save_gsi_mcs_channel_scratch_regs_s + mcs_channel_scratch; + union ipa_hwio_def_fc_stats_state_u + fc_stats_state; +}; + +/* GSI Event Context register save data struct */ +struct ipa_reg_save_gsi_evt_cntxt_per_ep_s { + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_0_s + ee_n_ev_ch_k_cntxt_0; + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_1_s + ee_n_ev_ch_k_cntxt_1; + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_2_s + ee_n_ev_ch_k_cntxt_2; + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_3_s + ee_n_ev_ch_k_cntxt_3; + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_4_s + ee_n_ev_ch_k_cntxt_4; + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_5_s + ee_n_ev_ch_k_cntxt_5; + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_6_s + ee_n_ev_ch_k_cntxt_6; + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_7_s + ee_n_ev_ch_k_cntxt_7; + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_8_s + ee_n_ev_ch_k_cntxt_8; + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_9_s + ee_n_ev_ch_k_cntxt_9; + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_10_s + ee_n_ev_ch_k_cntxt_10; + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_11_s + ee_n_ev_ch_k_cntxt_11; + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_12_s + ee_n_ev_ch_k_cntxt_12; + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_13_s + ee_n_ev_ch_k_cntxt_13; + struct gsi_hwio_def_ee_n_ev_ch_k_scratch_0_s + ee_n_ev_ch_k_scratch_0; + struct gsi_hwio_def_ee_n_ev_ch_k_scratch_1_s + ee_n_ev_ch_k_scratch_1; + struct gsi_hwio_def_gsi_debug_ee_n_ev_k_vp_table_s + gsi_debug_ee_n_ev_k_vp_table; +}; + +/* GSI FIFO status register save data struct */ +struct ipa_reg_save_gsi_fifo_status_s { + union ipa_hwio_def_ipa_gsi_fifo_status_ctrl_u + gsi_fifo_status_ctrl; + union ipa_hwio_def_ipa_gsi_tlv_fifo_status_u + gsi_tlv_fifo_status; + union ipa_hwio_def_ipa_gsi_aos_fifo_status_u + gsi_aos_fifo_status; +}; + +/* GSI Channel Context register save top level data struct */ +struct ipa_reg_save_gsi_ch_cntxt_s { + struct ipa_reg_save_gsi_ch_cntxt_per_ep_s + a7[IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_A7]; + struct ipa_reg_save_gsi_ch_cntxt_per_ep_s + uc[IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_UC]; + struct ipa_reg_save_gsi_ch_cntxt_per_ep_s + q6[IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_Q6]; +}; + +/* GSI Event Context register save top level data struct */ +struct ipa_reg_save_gsi_evt_cntxt_s { + struct ipa_reg_save_gsi_evt_cntxt_per_ep_s + a7[IPA_HW_REG_SAVE_GSI_NUM_EVT_CNTXT_A7]; + struct ipa_reg_save_gsi_evt_cntxt_per_ep_s + uc[IPA_HW_REG_SAVE_GSI_NUM_EVT_CNTXT_UC]; + struct ipa_reg_save_gsi_evt_cntxt_per_ep_s + q6[IPA_HW_REG_SAVE_GSI_NUM_EVT_CNTXT_Q6]; +}; + +/* Top level IPA register save data struct */ +struct ipa_regs_save_hierarchy_s { + struct ipa_gen_regs_s + gen; + struct ipa_reg_save_gen_ee_s + gen_ee[IPA_HW_EE_MAX]; + struct ipa_reg_save_stat_ee_s + stat_ee[IPA_HW_EE_MAX]; + struct ipa_reg_save_hwp_s + hwp; + struct ipa_reg_save_dbg_s + dbg; + struct ipa_reg_save_ipa_testbus_s + *testbus; + struct ipa_reg_save_pipe_s + pipes[IPA_HW_PIPE_ID_MAX]; + struct ipa_reg_save_src_rsrc_grp_s + src_rsrc_grp[IPA_HW_SRC_RSRP_TYPE_MAX]; + struct ipa_reg_save_dst_rsrc_grp_s + dst_rsrc_grp[IPA_HW_DST_RSRP_TYPE_MAX]; + struct ipa_reg_save_src_rsrc_cnt_s + src_rsrc_cnt[IPA_HW_SRC_RSRP_TYPE_MAX]; + struct ipa_reg_save_dst_rsrc_cnt_s + dst_rsrc_cnt[IPA_HW_DST_RSRP_TYPE_MAX]; + u32 *ipa_iu_ptr; + u32 *ipa_sram_ptr; + u32 *ipa_mbox_ptr; + u32 *ipa_hram_ptr; + u32 *ipa_seq_ptr; + u32 *ipa_gsi_ptr; +}; + +/* Top level GSI register save data struct */ +struct gsi_regs_save_hierarchy_s { + struct ipa_reg_save_gsi_fw_version_s fw_ver; + struct ipa_reg_save_gsi_gen_s gen; + struct ipa_reg_save_gsi_gen_ee_s gen_ee[IPA_REG_SAVE_GSI_NUM_EE]; + struct ipa_reg_save_gsi_ch_cntxt_s ch_cntxt; + struct ipa_reg_save_gsi_evt_cntxt_s evt_cntxt; + struct ipa_reg_save_gsi_debug_s debug; +}; + +/* Source resources for a resource group */ +struct ipa_reg_save_src_rsrc_cnts_s { + u8 pkt_cntxt; + u8 descriptor_list; + u8 data_descriptor_buffer; + u8 hps_dmars; + u8 reserved_acks; +}; + +/* Destination resources for a resource group */ +struct ipa_reg_save_dst_rsrc_cnts_s { + u8 reserved_sectors; + u8 dps_dmars; +}; + +/* Resource count structure for a resource group */ +struct ipa_reg_save_rsrc_cnts_per_grp_s { + /* Resource group number */ + u8 resource_group; + /* Source resources for a resource group */ + struct ipa_reg_save_src_rsrc_cnts_s src; + /* Destination resources for a resource group */ + struct ipa_reg_save_dst_rsrc_cnts_s dst; +}; + +/* Top level resource count structure */ +struct ipa_reg_save_rsrc_cnts_s { + /* Resource count structure for PCIE group */ + struct ipa_reg_save_rsrc_cnts_per_grp_s pcie; + /* Resource count structure for DDR group */ + struct ipa_reg_save_rsrc_cnts_per_grp_s ddr; +}; + +/* + * Top level IPA and GSI registers save data struct + */ +struct regs_save_hierarchy_s { + struct ipa_regs_save_hierarchy_s + ipa; + struct gsi_regs_save_hierarchy_s + gsi; + bool + pkt_ctntx_active[IPA_HW_PKT_CTNTX_MAX]; + union ipa_hwio_def_ipa_ctxh_ctrl_u + pkt_ctntxt_lock; + enum ipa_hw_pkt_cntxt_state_e + pkt_cntxt_state[IPA_HW_PKT_CTNTX_MAX]; + struct ipa_pkt_ctntx_s + pkt_ctntx[IPA_HW_PKT_CTNTX_MAX]; + struct ipa_reg_save_rsrc_cnts_s + rsrc_cnts; + struct ipa_reg_save_gsi_fifo_status_s + gsi_fifo_status[IPA_HW_PIPE_ID_MAX]; +}; + +/* + * The following section deals with handling IPA registers' memory + * access relative to pre-defined memory protection schemes + * (ie. "access control"). + * + * In a nut shell, the intent of the data stuctures below is to allow + * higher level register accessors to be unaware of what really is + * going on at the lowest level (ie. real vs non-real access). This + * methodology is also designed to allow for platform specific "access + * maps." + */ + +/* + * Function for doing an actual read + */ +static inline u32 +act_read(void __iomem *addr) +{ + u32 val = ioread32(addr); + + return val; +} + +/* + * Function for doing an actual write + */ +static inline void +act_write(void __iomem *addr, u32 val) +{ + iowrite32(val, addr); +} + +/* + * Function that pretends to do a read + */ +static inline u32 +nop_read(void __iomem *addr) +{ + return IPA_MEM_INIT_VAL; +} + +/* + * Function that pretends to do a write + */ +static inline void +nop_write(void __iomem *addr, u32 val) +{ +} + +/* + * The following are used to define struct reg_access_funcs_s below... + */ +typedef u32 (*reg_read_func_t)( + void __iomem *addr); +typedef void (*reg_write_func_t)( + void __iomem *addr, + u32 val); + +/* + * The following in used to define io_matrix[] below... + */ +struct reg_access_funcs_s { + reg_read_func_t read; + reg_write_func_t write; +}; + +/* + * The following will be used to appropriately index into the + * read/write combos defined in io_matrix[] below... + */ +#define AA_COMBO 0 /* actual read, actual write */ +#define AN_COMBO 1 /* actual read, no-op write */ +#define NA_COMBO 2 /* no-op read, actual write */ +#define NN_COMBO 3 /* no-op read, no-op write */ + +/* + * The following will be used to dictate registers' access methods + * relative to the state of secure debug...whether it's enabled or + * disabled. + * + * NOTE: The table below defines all access combinations. + */ +static struct reg_access_funcs_s io_matrix[] = { + { act_read, act_write }, /* the AA_COMBO */ + { act_read, nop_write }, /* the AN_COMBO */ + { nop_read, act_write }, /* the NA_COMBO */ + { nop_read, nop_write }, /* the NN_COMBO */ +}; + +/* + * The following will be used to define and drive IPA's register + * access rules. + */ +struct reg_mem_access_map_t { + u32 addr_range_begin; + u32 addr_range_end; + struct reg_access_funcs_s *access[2]; +}; + +#endif /* #if !defined(_IPA_REG_DUMP_H_) */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa.c new file mode 100644 index 0000000000..cce9bdf971 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa.c @@ -0,0 +1,12741 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. + * + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 14, 0)) +#include +#else +#include +#endif +#include "gsi.h" +#include "ipa_stats.h" +#include + +#ifdef CONFIG_ARM64 + +/* Outer caches unsupported on ARM64 platforms */ +#define outer_flush_range(x, y) +#define __cpuc_flush_dcache_area __flush_dcache_area + +#endif + +#define DRV_NAME "ipa" +#define DELAY_BEFORE_FW_LOAD 500 +#define IPA_SUBSYSTEM_NAME "ipa_fws" +#define IPA_UC_SUBSYSTEM_NAME "ipa_uc" + +#include "ipa_i.h" +#include "ipa_rm_i.h" +#if defined(CONFIG_IPA_TSP) +#include "ipa_tsp.h" +#endif +#include "ipahal.h" +#include "ipahal_fltrt.h" + +#define CREATE_TRACE_POINTS +#include "ipa_trace.h" +#include "ipa_odl.h" + +#define IPA_SUSPEND_BUSY_TIMEOUT (msecs_to_jiffies(10)) + +#define DEFAULT_MPM_RING_SIZE_UL 6 +#define DEFAULT_MPM_RING_SIZE_DL 16 +#define DEFAULT_MPM_TETH_AGGR_SIZE 24 +#define DEFAULT_MPM_UC_THRESH_SIZE 4 + +RAW_NOTIFIER_HEAD(ipa_rmnet_notifier_list); + +/* + * The following for adding code (ie. for EMULATION) not found on x86. + */ +#if defined(CONFIG_IPA_EMULATION) +# include "ipa_emulation_stubs.h" +#endif + +#ifdef CONFIG_COMPAT +/** + * struct ipa3_ioc_nat_alloc_mem32 - nat table memory allocation + * properties + * @dev_name: input parameter, the name of table + * @size: input parameter, size of table in bytes + * @offset: output parameter, offset into page in case of system memory + */ +struct ipa3_ioc_nat_alloc_mem32 { + char dev_name[IPA_RESOURCE_NAME_MAX]; + compat_size_t size; + compat_off_t offset; +}; + +/** + * struct ipa_ioc_nat_ipv6ct_table_alloc32 - table memory allocation + * properties + * @size: input parameter, size of table in bytes + * @offset: output parameter, offset into page in case of system memory + */ +struct ipa_ioc_nat_ipv6ct_table_alloc32 { + compat_size_t size; + compat_off_t offset; +}; +#endif /* #ifdef CONFIG_COMPAT */ + +#define IPA_TZ_UNLOCK_ATTRIBUTE 0x0C0311 + +struct tz_smmu_ipa_protect_region_iovec_s { + u64 input_addr; + u64 output_addr; + u64 size; + u32 attr; +} __packed; + +struct tz_smmu_ipa_protect_region_s { + phys_addr_t iovec_buf; + u32 size_bytes; +} __packed; + +/** + * struct ipa_ready_cb_info - A list of all the registrations + * for an indication of IPA driver readiness + * + * @link: linked list link + * @ready_cb: callback + * @user_data: User data + * + */ +struct ipa_ready_cb_info { + struct list_head link; + ipa_ready_cb ready_cb; + void *user_data; +}; + +static void ipa3_start_tag_process(struct work_struct *work); +static DECLARE_WORK(ipa3_tag_work, ipa3_start_tag_process); + +static void ipa3_transport_release_resource(struct work_struct *work); +static DECLARE_DELAYED_WORK(ipa3_transport_release_resource_work, + ipa3_transport_release_resource); +static void ipa_gsi_notify_cb(struct gsi_per_notify *notify); + +static int ipa3_attach_to_smmu(void); +static int ipa3_alloc_pkt_init(void); +static int ipa_alloc_pkt_init_ex(void); +static void ipa3_free_pkt_init(void); +static void ipa3_free_pkt_init_ex(void); + +#if IS_ENABLED(CONFIG_DEEPSLEEP) || IS_ENABLED(CONFIG_HIBERNATION) +static void ipa3_deepsleep_resume(void); +static void ipa3_deepsleep_suspend(void); +#endif + +static void ipa3_load_ipa_fw(struct work_struct *work); +static DECLARE_WORK(ipa3_fw_loading_work, ipa3_load_ipa_fw); +static DECLARE_DELAYED_WORK(ipa3_fw_load_failure_handle, ipa3_load_ipa_fw); + +static void ipa_dec_clients_disable_clks_on_wq(struct work_struct *work); +static DECLARE_DELAYED_WORK(ipa_dec_clients_disable_clks_on_wq_work, + ipa_dec_clients_disable_clks_on_wq); + +static DECLARE_DELAYED_WORK(ipa_dec_clients_disable_clks_on_suspend_irq_wq_work, + ipa_dec_clients_disable_clks_on_wq); +static void ipa_inc_clients_enable_clks_on_wq(struct work_struct *work); +static DECLARE_WORK(ipa_inc_clients_enable_clks_on_wq_work, + ipa_inc_clients_enable_clks_on_wq); + +static int ipa3_ioctl_add_rt_rule_v2(unsigned long arg); +static int ipa3_ioctl_add_rt_rule_ext_v2(unsigned long arg); +static int ipa3_ioctl_add_rt_rule_after_v2(unsigned long arg); +static int ipa3_ioctl_mdfy_rt_rule_v2(unsigned long arg); +static int ipa3_ioctl_add_flt_rule_v2(unsigned long arg); +static int ipa3_ioctl_add_flt_rule_after_v2(unsigned long arg); +static int ipa3_ioctl_mdfy_flt_rule_v2(unsigned long arg); +static int ipa3_ioctl_fnr_counter_alloc(unsigned long arg); +static int ipa3_ioctl_fnr_counter_query(unsigned long arg); +static int ipa3_ioctl_fnr_counter_set(unsigned long arg); + +static struct ipa3_plat_drv_res ipa3_res = {0, }; + +static struct clk *ipa3_clk; + +struct ipa3_context *ipa3_ctx = NULL; +/* ipa_i.h is included in ipa_client modules and ipa3_ctx is + * declared as extern in ipa_i.h. So export ipa3_ctx variable + * to be visible to ipa_client module. +*/ +EXPORT_SYMBOL(ipa3_ctx); + +int ipa3_plat_drv_probe(struct platform_device *pdev_p); +int ipa3_pci_drv_probe(struct pci_dev *pci_dev, + const struct pci_device_id *ent); + +/** + * ipa_get_hw_type() - Return IPA HW version + * + * Return value: enum ipa_hw_type + */ +enum ipa_hw_type ipa_get_hw_type(void) +{ + if (ipa3_ctx == NULL) + return IPA_HW_None; + + return ipa3_ctx->ipa_hw_type; +} +EXPORT_SYMBOL(ipa_get_hw_type); + +/** + * ipa_is_test_prod_flt_in_sram_internal() - Return true if test prod FLT tbl is in SRAM + * + * Return value:bool + */ +bool ipa_is_test_prod_flt_in_sram_internal(enum ipa_ip_type ip) +{ + struct ipa3_flt_tbl *flt_tbl; + const struct ipa_gsi_ep_config *gsi_ep_info_cfg; + + if (ipa3_ctx == NULL) + return false; + + gsi_ep_info_cfg = ipa_get_gsi_ep_info(IPA_CLIENT_TEST_PROD); + if(gsi_ep_info_cfg == NULL) + return false; + + flt_tbl = &ipa3_ctx->flt_tbl[gsi_ep_info_cfg->ipa_ep_num][ip]; + + return !flt_tbl->force_sys[IPA_RULE_NON_HASHABLE] && + !flt_tbl->in_sys[IPA_RULE_NON_HASHABLE]; +} +EXPORT_SYMBOL(ipa_is_test_prod_flt_in_sram_internal); + +/** + * ipa_assert() - general function for assertion + */ +void ipa_assert(void) +{ + pr_err("IPA: unrecoverable error has occurred, asserting\n"); + BUG(); +} +EXPORT_SYMBOL(ipa_assert); + +#if defined(CONFIG_IPA_EMULATION) +static bool running_emulation = true; +#else +static bool running_emulation; +#endif + +static const struct of_device_id ipa_pci_drv_match[] = { + { .compatible = "qcom,ipa", }, + {} +}; + +#define LOCAL_VENDOR 0x17CB +#define LOCAL_DEVICE 0x00ff + +static const char ipa_pci_driver_name[] = "qcipav3"; + +static const struct pci_device_id ipa_pci_tbl[] = { + { PCI_DEVICE(LOCAL_VENDOR, LOCAL_DEVICE) }, + { 0, 0, 0, 0, 0, 0, 0 } +}; + +MODULE_DEVICE_TABLE(pci, ipa_pci_tbl); + +static void ipa_pci_remove(struct pci_dev *pci_dev) +{ +} + +static void ipa_pci_shutdown(struct pci_dev *pci_dev) +{ +} + +static pci_ers_result_t ipa_pci_io_error_detected(struct pci_dev *pci_dev, + pci_channel_state_t state) +{ + return 0; +} + +static pci_ers_result_t ipa_pci_io_slot_reset(struct pci_dev *pci_dev) +{ + return 0; +} + +static void ipa_pci_io_resume(struct pci_dev *pci_dev) +{ +} + +/* PCI Error Recovery */ +static const struct pci_error_handlers ipa_pci_err_handler = { + .error_detected = ipa_pci_io_error_detected, + .slot_reset = ipa_pci_io_slot_reset, + .resume = ipa_pci_io_resume, +}; + +static struct pci_driver ipa_pci_driver = { + .name = ipa_pci_driver_name, + .id_table = ipa_pci_tbl, + .probe = ipa3_pci_drv_probe, + .remove = ipa_pci_remove, + .shutdown = ipa_pci_shutdown, + .err_handler = &ipa_pci_err_handler +}; + +static const struct of_device_id ipa_plat_drv_match[] = { + { .compatible = "qcom,ipa", }, + { .compatible = "qcom,ipa-smmu-ap-cb", }, + { .compatible = "qcom,ipa-smmu-wlan-cb", }, + { .compatible = "qcom,ipa-smmu-rtp-cb", }, + { .compatible = "qcom,ipa-smmu-uc-cb", }, + { .compatible = "qcom,ipa-smmu-11ad-cb", }, + { .compatible = "qcom,ipa-smmu-eth-cb", }, + { .compatible = "qcom,ipa-smmu-eth1-cb", }, + { .compatible = "qcom,ipa-smmu-wlan1-cb", }, + { .compatible = "qcom,smp2p-map-ipa-1-in", }, + { .compatible = "qcom,smp2p-map-ipa-1-out", }, + {} +}; + +/** + * ipa_write_64() - convert 64 bit value to byte array + * @w: 64 bit integer + * @dest: byte array + * + * Return value: converted value + */ +u8 *ipa_write_64(u64 w, u8 *dest) +{ + if (unlikely(dest == NULL)) { + pr_err("%s: NULL address\n", __func__); + return dest; + } + *dest++ = (u8)((w) & 0xFF); + *dest++ = (u8)((w >> 8) & 0xFF); + *dest++ = (u8)((w >> 16) & 0xFF); + *dest++ = (u8)((w >> 24) & 0xFF); + *dest++ = (u8)((w >> 32) & 0xFF); + *dest++ = (u8)((w >> 40) & 0xFF); + *dest++ = (u8)((w >> 48) & 0xFF); + *dest++ = (u8)((w >> 56) & 0xFF); + + return dest; +} + +/** + * ipa_write_32() - convert 32 bit value to byte array + * @w: 32 bit integer + * @dest: byte array + * + * Return value: converted value + */ +u8 *ipa_write_32(u32 w, u8 *dest) +{ + if (unlikely(dest == NULL)) { + pr_err("%s: NULL address\n", __func__); + return dest; + } + *dest++ = (u8)((w) & 0xFF); + *dest++ = (u8)((w >> 8) & 0xFF); + *dest++ = (u8)((w >> 16) & 0xFF); + *dest++ = (u8)((w >> 24) & 0xFF); + + return dest; +} + +/** + * ipa_write_16() - convert 16 bit value to byte array + * @hw: 16 bit integer + * @dest: byte array + * + * Return value: converted value + */ +u8 *ipa_write_16(u16 hw, u8 *dest) +{ + if (unlikely(dest == NULL)) { + pr_err("%s: NULL address\n", __func__); + return dest; + } + *dest++ = (u8)((hw) & 0xFF); + *dest++ = (u8)((hw >> 8) & 0xFF); + + return dest; +} + +/** + * ipa_write_8() - convert 8 bit value to byte array + * @hw: 8 bit integer + * @dest: byte array + * + * Return value: converted value + */ +u8 *ipa_write_8(u8 b, u8 *dest) +{ + if (unlikely(dest == NULL)) { + WARN(1, "%s: NULL address\n", __func__); + return dest; + } + *dest++ = (b) & 0xFF; + + return dest; +} + +/** + * ipa_pad_to_64() - pad byte array to 64 bit value + * @dest: byte array + * + * Return value: padded value + */ +u8 *ipa_pad_to_64(u8 *dest) +{ + int i; + int j; + + if (unlikely(dest == NULL)) { + WARN(1, "%s: NULL address\n", __func__); + return dest; + } + + i = (long)dest & 0x7; + + if (i) + for (j = 0; j < (8 - i); j++) + *dest++ = 0; + + return dest; +} + +/** + * ipa_pad_to_32() - pad byte array to 32 bit value + * @dest: byte array + * + * Return value: padded value + */ +u8 *ipa_pad_to_32(u8 *dest) +{ + int i; + int j; + + if (unlikely(dest == NULL)) { + WARN(1, "%s: NULL address\n", __func__); + return dest; + } + + i = (long)dest & 0x7; + + if (i) + for (j = 0; j < (4 - i); j++) + *dest++ = 0; + + return dest; +} + +int ipa_smmu_store_sgt(struct sg_table **out_ch_ptr, + struct sg_table *in_sgt_ptr) +{ + unsigned int nents; + int i; + struct scatterlist *in_sg, *out_sg; + + if (in_sgt_ptr != NULL) { + *out_ch_ptr = kzalloc(sizeof(struct sg_table), GFP_KERNEL); + if (*out_ch_ptr == NULL) + return -ENOMEM; + + nents = in_sgt_ptr->nents; + + (*out_ch_ptr)->sgl = + kcalloc(nents, sizeof(struct scatterlist), + GFP_KERNEL); + if ((*out_ch_ptr)->sgl == NULL) { + kfree(*out_ch_ptr); + *out_ch_ptr = NULL; + return -ENOMEM; + } + + out_sg = (*out_ch_ptr)->sgl; + for_each_sg(in_sgt_ptr->sgl, in_sg, in_sgt_ptr->nents, i) { + memcpy(out_sg, in_sg, sizeof(struct scatterlist)); + out_sg++; + } + + (*out_ch_ptr)->nents = nents; + (*out_ch_ptr)->orig_nents = in_sgt_ptr->orig_nents; + } + return 0; +} +EXPORT_SYMBOL(ipa_smmu_store_sgt); + +int ipa_smmu_free_sgt(struct sg_table **out_sgt_ptr) +{ + if (*out_sgt_ptr != NULL) { + kfree((*out_sgt_ptr)->sgl); + (*out_sgt_ptr)->sgl = NULL; + kfree(*out_sgt_ptr); + *out_sgt_ptr = NULL; + } + return 0; +} +EXPORT_SYMBOL(ipa_smmu_free_sgt); + +/** + * ipa_pm_notify() - PM notify to listen suspend events + * + * This callback will be invoked by the pm framework to suspend + * operation is invoked. + * + * Returns NOTIFY_DONE to pm framework completed operation. + */ + +static int ipa_pm_notify(struct notifier_block *b, unsigned long event, void *p) +{ + IPADBG("Entry\n"); + switch (event) { + case PM_POST_SUSPEND: +#if IS_ENABLED(CONFIG_DEEPSLEEP) + if (pm_suspend_via_firmware() && ipa3_ctx->deepsleep) { + IPADBG("Enter deepsleep resume\n"); + ipa3_deepsleep_resume(); + IPADBG("Exit deepsleep resume\n"); + } +#endif + break; + case PM_POST_HIBERNATION: +#if IS_ENABLED(CONFIG_HIBERNATION) + /*Using the same deepsleep flag to check if freeze happened or not.*/ + if (ipa3_ctx->deepsleep) { + IPADBG("Enter hibernate restore\n"); + ipa3_deepsleep_resume(); + IPADBG("Exit hibernate restore\n"); + } +#endif + break; + } + IPADBG("Exit\n"); + return NOTIFY_DONE; +} + + +static struct notifier_block ipa_pm_notifier = { + .notifier_call = ipa_pm_notify, +}; + +static const struct dev_pm_ops ipa_pm_ops = { + .suspend_late = ipa3_ap_suspend, +#if IS_ENABLED(CONFIG_HIBERNATION) + .freeze_late = ipa3_ap_freeze, +#endif + .resume_early = ipa3_ap_resume, + .restore_early = ipa3_ap_resume, +}; + +static struct platform_driver ipa_plat_drv = { + .probe = ipa3_plat_drv_probe, + .driver = { + .name = DRV_NAME, + .pm = &ipa_pm_ops, + .of_match_table = ipa_plat_drv_match, + }, +}; + +static struct { + bool present[IPA_SMMU_CB_MAX]; + bool arm_smmu; + bool use_64_bit_dma_mask; + u32 ipa_base; + u32 ipa_size; +} smmu_info; + +static char *active_clients_table_buf; + +void ipa3_get_default_evict_values( + struct ipahal_reg_coal_evict_lru *evict_lru ) +{ + if (evict_lru) { + + struct device *dev = &ipa3_ctx->master_pdev->dev; + + u32 val; + int result; + + memset(evict_lru, 0, sizeof(*evict_lru)); + + /* + * Get coal_vp_lru_thrshld + */ + result = + of_property_read_u32( + dev->of_node, + "qcom,coal-vp-lru-thrshld", + &val); + if ( result == 0 ) { + evict_lru->coal_vp_lru_thrshld = val; + } else { + IPADBG( + "Error reading qcom,coal-vp-lru-thrshld...will use default\n"); + evict_lru->coal_vp_lru_thrshld = IPA_COAL_VP_LRU_THRSHLD; + } + IPADBG(": coal_vp_lru_thrshld = %u", evict_lru->coal_vp_lru_thrshld); + + /* + * Get coal_eviction_en + */ + evict_lru->coal_eviction_en = + of_property_read_bool( + dev->of_node, + "qcom,coal-eviction-en"); + if ( evict_lru->coal_eviction_en == false ) { + evict_lru->coal_eviction_en = IPA_COAL_EVICTION_EN; + } + IPADBG(": coal_eviction_en = %s", + (evict_lru->coal_eviction_en) ? "true" : "false"); + + /* + * Get coal_vp_lru_gran_sel + */ + result = + of_property_read_u32( + dev->of_node, + "qcom,coal_vp_lru_gran_sel", + &val); + if ( result == 0 ) { + evict_lru->coal_vp_lru_gran_sel = val; + } else { + IPADBG( + "Error reading qcom,coal_vp_lru_gran_sel...will use default\n"); + evict_lru->coal_vp_lru_gran_sel = IPA_COAL_VP_LRU_GRAN_SEL; + } + IPADBG(": coal_vp_lru_gran_sel = %u\n", + evict_lru->coal_vp_lru_gran_sel); + + /* + * Get coal_vp_lru_udp_thrshld + */ + result = + of_property_read_u32( + dev->of_node, + "qcom,coal-vp-lru-udp-thrshld", + &val); + if ( result == 0 ) { + evict_lru->coal_vp_lru_udp_thrshld = val; + } else { + IPADBG( + "Error reading qcom,coal-vp-lru-udp-thrshld...will use default\n"); + evict_lru->coal_vp_lru_udp_thrshld = IPA_COAL_VP_LRU_UDP_THRSHLD; + } + IPADBG(": coal_vp_lru_udp_thrshld = %u", evict_lru->coal_vp_lru_udp_thrshld); + + /* + * Get coal_vp_lru_tcp_thrshld + */ + result = + of_property_read_u32( + dev->of_node, + "qcom,coal-vp-lru-tcp-thrshld", + &val); + if ( result == 0 ) { + evict_lru->coal_vp_lru_tcp_thrshld = val; + } else { + IPADBG( + "Error reading qcom,coal-vp-lru-tcp-thrshld...will use default\n"); + evict_lru->coal_vp_lru_tcp_thrshld = IPA_COAL_VP_LRU_TCP_THRSHLD; + } + IPADBG(": coal_vp_lru_tcp_thrshld = %u", evict_lru->coal_vp_lru_tcp_thrshld); + + /* + * Get coal_vp_lru_udp_thrshld_en + */ + result = + of_property_read_u32( + dev->of_node, + "qcom,coal-vp-lru-udp-thrshld-en", + &val); + if ( result == 0 ) { + evict_lru->coal_vp_lru_udp_thrshld_en = val; + } else { + IPADBG( + "Error reading qcom,coal-vp-lru-udp-thrshld-en...will use default\n"); + evict_lru->coal_vp_lru_udp_thrshld_en = IPA_COAL_VP_LRU_UDP_THRSHLD_EN; + } + IPADBG(": coal_vp_lru_udp_thrshld_en = %u", + evict_lru->coal_vp_lru_udp_thrshld_en); + + /* + * Get coal_vp_lru_tcp_thrshld_en + */ + result = + of_property_read_u32( + dev->of_node, + "qcom,coal-vp-lru-tcp-thrshld-en", + &val); + if ( result == 0 ) { + evict_lru->coal_vp_lru_tcp_thrshld_en = val; + } else { + IPADBG( + "Error reading qcom,coal-vp-lru-tcp-thrshld-en...will use default\n"); + evict_lru->coal_vp_lru_tcp_thrshld_en = IPA_COAL_VP_LRU_TCP_THRSHLD_EN; + } + IPADBG(": coal_vp_lru_tcp_thrshld_en = %u", + evict_lru->coal_vp_lru_tcp_thrshld_en); + + /* + * Get coal_vp_lru_tcp_num + */ + result = + of_property_read_u32( + dev->of_node, + "qcom,coal-vp-lru-tcp-num", + &val); + if ( result == 0 ) { + evict_lru->coal_vp_lru_tcp_num = val; + } else { + IPADBG( + "Error reading qcom,coal-vp-lru-tcp-num...will use default\n"); + evict_lru->coal_vp_lru_tcp_num = IPA_COAL_VP_LRU_TCP_NUM; + } + IPADBG(": coal_vp_lru_tcp_num = %u", evict_lru->coal_vp_lru_tcp_num); + } +} + +int ipa3_active_clients_log_print_buffer(char *buf, int size) +{ + int i; + int nbytes; + int cnt = 0; + int start_idx; + int end_idx; + unsigned long flags; + + spin_lock_irqsave(&ipa3_ctx->ipa3_active_clients_logging.lock, flags); + start_idx = (ipa3_ctx->ipa3_active_clients_logging.log_tail + 1) % + IPA3_ACTIVE_CLIENTS_LOG_BUFFER_SIZE_LINES; + end_idx = ipa3_ctx->ipa3_active_clients_logging.log_head; + for (i = start_idx; i != end_idx; + i = (i + 1) % IPA3_ACTIVE_CLIENTS_LOG_BUFFER_SIZE_LINES) { + nbytes = scnprintf(buf + cnt, size - cnt, "%s\n", + ipa3_ctx->ipa3_active_clients_logging + .log_buffer[i]); + cnt += nbytes; + } + spin_unlock_irqrestore(&ipa3_ctx->ipa3_active_clients_logging.lock, + flags); + + return cnt; +} + +int ipa3_active_clients_log_print_table(char *buf, int size) +{ + int i; + struct ipa3_active_client_htable_entry *iterator; + int cnt = 0; + unsigned long flags; + + spin_lock_irqsave(&ipa3_ctx->ipa3_active_clients_logging.lock, flags); + cnt = scnprintf(buf, size, "\n---- Active Clients Table ----\n"); + hash_for_each(ipa3_ctx->ipa3_active_clients_logging.htable, i, + iterator, list) { + switch (iterator->type) { + case IPA3_ACTIVE_CLIENT_LOG_TYPE_EP: + cnt += scnprintf(buf + cnt, size - cnt, + "%-40s %-3d ENDPOINT\n", + iterator->id_string, iterator->count); + break; + case IPA3_ACTIVE_CLIENT_LOG_TYPE_SIMPLE: + cnt += scnprintf(buf + cnt, size - cnt, + "%-40s %-3d SIMPLE\n", + iterator->id_string, iterator->count); + break; + case IPA3_ACTIVE_CLIENT_LOG_TYPE_RESOURCE: + cnt += scnprintf(buf + cnt, size - cnt, + "%-40s %-3d RESOURCE\n", + iterator->id_string, iterator->count); + break; + case IPA3_ACTIVE_CLIENT_LOG_TYPE_SPECIAL: + cnt += scnprintf(buf + cnt, size - cnt, + "%-40s %-3d SPECIAL\n", + iterator->id_string, iterator->count); + break; + default: + IPAERR("Trying to print illegal active_clients type"); + break; + } + } + cnt += scnprintf(buf + cnt, size - cnt, + "\nTotal active clients count: %d\n", + atomic_read(&ipa3_ctx->ipa3_active_clients.cnt)); + + if (ipa3_is_mhip_offload_enabled()) + cnt += ipa_mpm_panic_handler(buf + cnt, size - cnt); + + spin_unlock_irqrestore(&ipa3_ctx->ipa3_active_clients_logging.lock, + flags); + + return cnt; +} + +static int ipa3_clean_modem_rule(void) +{ + struct ipa_install_fltr_rule_req_ex_msg_v01 *req_ex; + int val = 0; + + req_ex = kzalloc( + sizeof(struct ipa_install_fltr_rule_req_ex_msg_v01), + GFP_KERNEL); + if (!req_ex) { + IPAERR("mem allocated failed!\n"); + return -ENOMEM; + } + req_ex->filter_spec_ex_list_valid = false; + req_ex->filter_spec_ex_list_len = 0; + req_ex->source_pipe_index_valid = 0; + val = ipa3_qmi_filter_request_ex_send(req_ex); + kfree(req_ex); + return val; +} + +static int ipa3_clean_mhip_dl_rule(void) +{ + struct ipa_remove_offload_connection_req_msg_v01 req; + + memset(&req, 0, sizeof(struct + ipa_remove_offload_connection_req_msg_v01)); + + req.clean_all_rules_valid = true; + req.clean_all_rules = true; + + if (ipa3_qmi_rmv_offload_request_send(&req)) { + IPAWANDBG("clean dl rule cache failed\n"); + return -EFAULT; + } + + return 0; +} + +#ifdef CONFIG_IPA_DEBUG +static int ipa3_active_clients_log_insert(const char *string) +{ + int head; + int tail; + + if (!ipa3_ctx->ipa3_active_clients_logging.log_rdy) + return -EPERM; + + head = ipa3_ctx->ipa3_active_clients_logging.log_head; + tail = ipa3_ctx->ipa3_active_clients_logging.log_tail; + + memset(ipa3_ctx->ipa3_active_clients_logging.log_buffer[head], '_', + IPA3_ACTIVE_CLIENTS_LOG_LINE_LEN); + strlcpy(ipa3_ctx->ipa3_active_clients_logging.log_buffer[head], string, + (size_t)IPA3_ACTIVE_CLIENTS_LOG_LINE_LEN); + head = (head + 1) % IPA3_ACTIVE_CLIENTS_LOG_BUFFER_SIZE_LINES; + if (tail == head) + tail = (tail + 1) % IPA3_ACTIVE_CLIENTS_LOG_BUFFER_SIZE_LINES; + + ipa3_ctx->ipa3_active_clients_logging.log_tail = tail; + ipa3_ctx->ipa3_active_clients_logging.log_head = head; + + return 0; +} +#endif + +static int ipa3_active_clients_log_init(void) +{ + int i; + + spin_lock_init(&ipa3_ctx->ipa3_active_clients_logging.lock); + ipa3_ctx->ipa3_active_clients_logging.log_buffer[0] = kcalloc( + IPA3_ACTIVE_CLIENTS_LOG_BUFFER_SIZE_LINES, + sizeof(char[IPA3_ACTIVE_CLIENTS_LOG_LINE_LEN]), + GFP_KERNEL); + active_clients_table_buf = kzalloc(sizeof( + char[IPA3_ACTIVE_CLIENTS_TABLE_BUF_SIZE]), GFP_KERNEL); + if (ipa3_ctx->ipa3_active_clients_logging.log_buffer[0] == NULL) { + pr_err("Active Clients Logging memory allocation failed\n"); + goto bail; + } + for (i = 0; i < IPA3_ACTIVE_CLIENTS_LOG_BUFFER_SIZE_LINES; i++) { + ipa3_ctx->ipa3_active_clients_logging.log_buffer[i] = + ipa3_ctx->ipa3_active_clients_logging.log_buffer[0] + + (IPA3_ACTIVE_CLIENTS_LOG_LINE_LEN * i); + } + ipa3_ctx->ipa3_active_clients_logging.log_head = 0; + ipa3_ctx->ipa3_active_clients_logging.log_tail = + IPA3_ACTIVE_CLIENTS_LOG_BUFFER_SIZE_LINES - 1; + hash_init(ipa3_ctx->ipa3_active_clients_logging.htable); + ipa3_ctx->ipa3_active_clients_logging.log_rdy = true; + + return 0; + +bail: + return -ENOMEM; +} + +void ipa3_active_clients_log_clear(void) +{ + unsigned long flags; + + spin_lock_irqsave(&ipa3_ctx->ipa3_active_clients_logging.lock, flags); + ipa3_ctx->ipa3_active_clients_logging.log_head = 0; + ipa3_ctx->ipa3_active_clients_logging.log_tail = + IPA3_ACTIVE_CLIENTS_LOG_BUFFER_SIZE_LINES - 1; + spin_unlock_irqrestore(&ipa3_ctx->ipa3_active_clients_logging.lock, + flags); +} + +static void ipa3_active_clients_log_destroy(void) +{ + unsigned long flags; + + spin_lock_irqsave(&ipa3_ctx->ipa3_active_clients_logging.lock, flags); + ipa3_ctx->ipa3_active_clients_logging.log_rdy = false; + kfree(active_clients_table_buf); + active_clients_table_buf = NULL; + kfree(ipa3_ctx->ipa3_active_clients_logging.log_buffer[0]); + ipa3_ctx->ipa3_active_clients_logging.log_buffer[0] = NULL; + ipa3_ctx->ipa3_active_clients_logging.log_head = 0; + ipa3_ctx->ipa3_active_clients_logging.log_tail = + IPA3_ACTIVE_CLIENTS_LOG_BUFFER_SIZE_LINES - 1; + spin_unlock_irqrestore(&ipa3_ctx->ipa3_active_clients_logging.lock, + flags); +} + +static struct ipa_smmu_cb_ctx smmu_cb[IPA_SMMU_CB_MAX]; + +struct iommu_domain *ipa3_get_smmu_domain_by_type(enum ipa_smmu_cb_type cb_type) +{ + if (VALID_IPA_SMMU_CB_TYPE(cb_type) && smmu_cb[cb_type].valid) + return smmu_cb[cb_type].iommu_domain; + + IPAERR("cb_type(%d) not valid\n", cb_type); + + return NULL; +} + +struct iommu_domain *ipa3_get_smmu_domain(void) +{ + return ipa3_get_smmu_domain_by_type(IPA_SMMU_CB_AP); +} + +struct iommu_domain *ipa3_get_uc_smmu_domain(void) +{ + return ipa3_get_smmu_domain_by_type(IPA_SMMU_CB_UC); +} + +struct iommu_domain *ipa3_get_wlan_smmu_domain(void) +{ + return ipa3_get_smmu_domain_by_type(IPA_SMMU_CB_WLAN); +} + +struct iommu_domain *ipa3_get_rtp_smmu_domain(void) +{ + return ipa3_get_smmu_domain_by_type(IPA_SMMU_CB_RTP); +} + +struct iommu_domain *ipa3_get_wlan1_smmu_domain(void) +{ + return ipa3_get_smmu_domain_by_type(IPA_SMMU_CB_WLAN1); +} + +struct iommu_domain *ipa3_get_eth_smmu_domain(void) +{ + return ipa3_get_smmu_domain_by_type(IPA_SMMU_CB_ETH); +} + +struct iommu_domain *ipa3_get_eth1_smmu_domain(void) +{ + return ipa3_get_smmu_domain_by_type(IPA_SMMU_CB_ETH1); +} + + +struct iommu_domain *ipa3_get_11ad_smmu_domain(void) +{ + return ipa3_get_smmu_domain_by_type(IPA_SMMU_CB_11AD); +} + +struct device *ipa3_get_dma_dev(void) +{ + return ipa3_ctx->pdev; +} +EXPORT_SYMBOL(ipa3_get_dma_dev); + +/** + * ipa3_get_smmu_ctx()- Return smmu context for the given cb_type + * + * Return value: pointer to smmu context address + */ +struct ipa_smmu_cb_ctx *ipa3_get_smmu_ctx(enum ipa_smmu_cb_type cb_type) +{ + return &smmu_cb[cb_type]; +} + +static int ipa3_open(struct inode *inode, struct file *filp) +{ + IPADBG_LOW("ENTER\n"); + filp->private_data = ipa3_ctx; + + return 0; +} + +static void ipa3_wan_msg_free_cb(void *buff, u32 len, u32 type) +{ + if (!buff) { + IPAERR("Null buffer\n"); + return; + } + + if (type != WAN_UPSTREAM_ROUTE_ADD && + type != WAN_UPSTREAM_ROUTE_DEL && + type != WAN_EMBMS_CONNECT) { + IPAERR("Wrong type given. buff %pK type %d\n", buff, type); + return; + } + + kfree(buff); +} + +static int ipa3_send_wan_msg(unsigned long usr_param, + uint8_t msg_type, bool is_cache) +{ + int retval; + struct ipa_wan_msg *wan_msg; + struct ipa_msg_meta msg_meta; + struct ipa_wan_msg cache_wan_msg; + + wan_msg = kzalloc(sizeof(*wan_msg), GFP_KERNEL); + if (!wan_msg) + return -ENOMEM; + + if (copy_from_user(wan_msg, (const void __user *)usr_param, + sizeof(struct ipa_wan_msg))) { + kfree(wan_msg); + return -EFAULT; + } + + memcpy(&cache_wan_msg, wan_msg, sizeof(cache_wan_msg)); + + memset(&msg_meta, 0, sizeof(struct ipa_msg_meta)); + msg_meta.msg_type = msg_type; + msg_meta.msg_len = sizeof(struct ipa_wan_msg); + retval = ipa_send_msg(&msg_meta, wan_msg, ipa3_wan_msg_free_cb); + if (retval) { + IPAERR_RL("ipa_send_msg failed: %d\n", retval); + kfree(wan_msg); + return retval; + } + + if (is_cache) { + mutex_lock(&ipa3_ctx->ipa_cne_evt_lock); + + /* cache the cne event */ + memcpy(&ipa3_ctx->ipa_cne_evt_req_cache[ + ipa3_ctx->num_ipa_cne_evt_req].wan_msg, + &cache_wan_msg, + sizeof(cache_wan_msg)); + + memcpy(&ipa3_ctx->ipa_cne_evt_req_cache[ + ipa3_ctx->num_ipa_cne_evt_req].msg_meta, + &msg_meta, + sizeof(struct ipa_msg_meta)); + + ipa3_ctx->num_ipa_cne_evt_req++; + ipa3_ctx->num_ipa_cne_evt_req %= IPA_MAX_NUM_REQ_CACHE; + mutex_unlock(&ipa3_ctx->ipa_cne_evt_lock); + } + + return 0; +} + +static void ipa3_vlan_l2tp_msg_free_cb(void *buff, u32 len, u32 type) +{ + if (!buff) { + IPAERR("Null buffer\n"); + return; + } + + switch (type) { + case ADD_VLAN_IFACE: + case DEL_VLAN_IFACE: + case ADD_L2TP_VLAN_MAPPING: + case DEL_L2TP_VLAN_MAPPING: + case ADD_BRIDGE_VLAN_MAPPING: + case DEL_BRIDGE_VLAN_MAPPING: + break; + default: + IPAERR("Wrong type given. buff %pK type %d\n", buff, type); + return; + } + + kfree(buff); +} + +static void ipa3_pdn_config_msg_free_cb(void *buff, u32 len, u32 type) +{ + if (!buff) { + IPAERR("Null buffer\n"); + return; + } + + kfree(buff); +} + +static int ipa3_send_pdn_config_msg(unsigned long usr_param) +{ + int retval; + struct ipa_ioc_pdn_config *pdn_info; + struct ipa_msg_meta msg_meta; + void *buff; + + memset(&msg_meta, 0, sizeof(msg_meta)); + + pdn_info = kzalloc(sizeof(struct ipa_ioc_pdn_config), + GFP_KERNEL); + if (!pdn_info) + return -ENOMEM; + + if (copy_from_user((u8 *)pdn_info, (void __user *)usr_param, + sizeof(struct ipa_ioc_pdn_config))) { + kfree(pdn_info); + return -EFAULT; + } + + msg_meta.msg_len = sizeof(struct ipa_ioc_pdn_config); + buff = pdn_info; + + msg_meta.msg_type = pdn_info->pdn_cfg_type; + /* null terminate the string */ + pdn_info->dev_name[IPA_RESOURCE_NAME_MAX - 1] = '\0'; + if ((pdn_info->pdn_cfg_type < IPA_PDN_DEFAULT_MODE_CONFIG) || + (pdn_info->pdn_cfg_type >= IPA_PDN_CONFIG_EVENT_MAX)) { + IPAERR_RL("invalid pdn_cfg_type =%d", pdn_info->pdn_cfg_type); + kfree(pdn_info); + return -EINVAL; + } + + IPADBG("type %d, interface name: %s, enable:%d\n", msg_meta.msg_type, + pdn_info->dev_name, pdn_info->enable); + + if (pdn_info->pdn_cfg_type == IPA_PDN_IP_PASSTHROUGH_MODE_CONFIG) { + IPADBG("Client MAC %02x:%02x:%02x:%02x:%02x:%02x\n", + pdn_info->u.passthrough_cfg.client_mac_addr[0], + pdn_info->u.passthrough_cfg.client_mac_addr[1], + pdn_info->u.passthrough_cfg.client_mac_addr[2], + pdn_info->u.passthrough_cfg.client_mac_addr[3], + pdn_info->u.passthrough_cfg.client_mac_addr[4], + pdn_info->u.passthrough_cfg.client_mac_addr[5]); + } + + retval = ipa_send_msg(&msg_meta, buff, + ipa3_pdn_config_msg_free_cb); + if (retval) { + IPAERR("ipa_send_msg failed: %d, msg_type %d\n", + retval, + msg_meta.msg_type); + kfree(buff); + return retval; + } + IPADBG("exit\n"); + + return 0; +} + +static int ipa3_send_vlan_l2tp_msg(unsigned long usr_param, uint8_t msg_type) +{ + int retval; + struct ipa_ioc_vlan_iface_info *vlan_info; + struct ipa_ioc_l2tp_vlan_mapping_info *mapping_info; + struct ipa_ioc_bridge_vlan_mapping_info *bridge_vlan_info; + struct ipa_msg_meta msg_meta; + void *buff; + + IPADBG("type %d\n", msg_type); + + memset(&msg_meta, 0, sizeof(msg_meta)); + msg_meta.msg_type = msg_type; + + if ((msg_type == ADD_VLAN_IFACE) || + (msg_type == DEL_VLAN_IFACE)) { + vlan_info = kzalloc(sizeof(struct ipa_ioc_vlan_iface_info), + GFP_KERNEL); + if (!vlan_info) + return -ENOMEM; + + if (copy_from_user((u8 *)vlan_info, (void __user *)usr_param, + sizeof(struct ipa_ioc_vlan_iface_info))) { + kfree(vlan_info); + return -EFAULT; + } + + msg_meta.msg_len = sizeof(struct ipa_ioc_vlan_iface_info); + buff = vlan_info; + } else if ((msg_type == ADD_L2TP_VLAN_MAPPING) || + (msg_type == DEL_L2TP_VLAN_MAPPING)) { + mapping_info = kzalloc(sizeof(struct + ipa_ioc_l2tp_vlan_mapping_info), GFP_KERNEL); + if (!mapping_info) + return -ENOMEM; + + if (copy_from_user((u8 *)mapping_info, + (void __user *)usr_param, + sizeof(struct ipa_ioc_l2tp_vlan_mapping_info))) { + kfree(mapping_info); + return -EFAULT; + } + + msg_meta.msg_len = sizeof(struct + ipa_ioc_l2tp_vlan_mapping_info); + buff = mapping_info; + } else if ((msg_type == ADD_BRIDGE_VLAN_MAPPING) || + (msg_type == DEL_BRIDGE_VLAN_MAPPING)) { + bridge_vlan_info = kzalloc( + sizeof(struct ipa_ioc_bridge_vlan_mapping_info), + GFP_KERNEL); + if (!bridge_vlan_info) + return -ENOMEM; + + if (copy_from_user((u8 *)bridge_vlan_info, + (void __user *)usr_param, + sizeof(struct ipa_ioc_bridge_vlan_mapping_info))) { + kfree(bridge_vlan_info); + IPAERR("copy from user failed\n"); + return -EFAULT; + } + + msg_meta.msg_len = sizeof(struct + ipa_ioc_bridge_vlan_mapping_info); + buff = bridge_vlan_info; + } else { + IPAERR("Unexpected event\n"); + return -EFAULT; + } + + retval = ipa_send_msg(&msg_meta, buff, + ipa3_vlan_l2tp_msg_free_cb); + if (retval) { + IPAERR("ipa_send_msg failed: %d, msg_type %d\n", + retval, + msg_type); + kfree(buff); + return retval; + } + IPADBG("exit\n"); + + return 0; +} + +static void ipa3_gsb_msg_free_cb(void *buff, u32 len, u32 type) +{ + if (!buff) { + IPAERR("Null buffer\n"); + return; + } + + switch (type) { + case IPA_GSB_CONNECT: + case IPA_GSB_DISCONNECT: + break; + default: + IPAERR("Wrong type given. buff %pK type %d\n", buff, type); + return; + } + + kfree(buff); +} + +static void ipa3_get_usb_ep_info( + struct ipa_ioc_get_ep_info *ep_info, + struct ipa_ep_pair_info *pair_info + ) +{ + int ep_index = -1, i; + + ep_info->num_ep_pairs = 0; + for (i = 0; i < ep_info->max_ep_pairs; i++) { + pair_info[i].consumer_pipe_num = -1; + pair_info[i].producer_pipe_num = -1; + pair_info[i].ep_id = -1; + } + + ep_index = ipa_get_ep_mapping(IPA_CLIENT_USB2_PROD); + + if ((ep_index != -1) && ipa3_ctx->ep[ep_index].valid) { + pair_info[ep_info->num_ep_pairs].consumer_pipe_num = ep_index; + ep_index = ipa_get_ep_mapping(IPA_CLIENT_USB2_CONS); + if ((ep_index != -1) && (ipa3_ctx->ep[ep_index].valid)) { + pair_info[ep_info->num_ep_pairs].producer_pipe_num = + ep_index; + pair_info[ep_info->num_ep_pairs].ep_id = + IPA_v4_USB1_EP_ID; + + IPADBG("ep_pair_info consumer_pipe_num %d", + pair_info[ep_info->num_ep_pairs].consumer_pipe_num); + IPADBG(" producer_pipe_num %d ep_id %d\n", + pair_info[ep_info->num_ep_pairs].producer_pipe_num, + pair_info[ep_info->num_ep_pairs].ep_id); + ep_info->num_ep_pairs++; + } else { + pair_info[ep_info->num_ep_pairs].consumer_pipe_num = -1; + IPADBG("ep_pair_info consumer_pipe_num %d", + pair_info[ep_info->num_ep_pairs].consumer_pipe_num); + IPADBG(" producer_pipe_num %d ep_id %d\n", + pair_info[ep_info->num_ep_pairs].producer_pipe_num, + pair_info[ep_info->num_ep_pairs].ep_id); + } + } + + ep_index = ipa_get_ep_mapping(IPA_CLIENT_USB_PROD); + + if ((ep_index != -1) && ipa3_ctx->ep[ep_index].valid) { + pair_info[ep_info->num_ep_pairs].consumer_pipe_num = ep_index; + ep_index = ipa_get_ep_mapping(IPA_CLIENT_USB_CONS); + if ((ep_index != -1) && (ipa3_ctx->ep[ep_index].valid)) { + pair_info[ep_info->num_ep_pairs].producer_pipe_num = + ep_index; + pair_info[ep_info->num_ep_pairs].ep_id = + IPA_v4_USB0_EP_ID; + + IPADBG("ep_pair_info consumer_pipe_num %d", + pair_info[ep_info->num_ep_pairs].consumer_pipe_num); + IPADBG(" producer_pipe_num %d ep_id %d\n", + pair_info[ep_info->num_ep_pairs].producer_pipe_num, + pair_info[ep_info->num_ep_pairs].ep_id); + ep_info->num_ep_pairs++; + } else { + pair_info[ep_info->num_ep_pairs].consumer_pipe_num = -1; + IPADBG("ep_pair_info consumer_pipe_num %d", + pair_info[ep_info->num_ep_pairs].consumer_pipe_num); + IPADBG(" producer_pipe_num %d ep_id %d\n", + pair_info[ep_info->num_ep_pairs].producer_pipe_num, + pair_info[ep_info->num_ep_pairs].ep_id); + } + } +} + +static void ipa3_get_pcie_ep_info( + struct ipa_ioc_get_ep_info *ep_info, + struct ipa_ep_pair_info *pair_info + ) +{ + int ep_index = -1, i; + + ep_info->num_ep_pairs = 0; + for (i = 0; i < ep_info->max_ep_pairs; i++) { + pair_info[i].consumer_pipe_num = -1; + pair_info[i].producer_pipe_num = -1; + pair_info[i].ep_id = -1; + } + + /* + * Legacy codes for ipa4.X version + */ + if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0) { + ep_index = ipa_get_ep_mapping(IPA_CLIENT_MHI2_PROD); + + if ((ep_index != -1) && ipa3_ctx->ep[ep_index].valid) { + pair_info[ep_info->num_ep_pairs].consumer_pipe_num = ep_index; + ep_index = ipa_get_ep_mapping(IPA_CLIENT_MHI2_CONS); + if ((ep_index != -1) && (ipa3_ctx->ep[ep_index].valid)) { + pair_info[ep_info->num_ep_pairs].producer_pipe_num = + ep_index; + pair_info[ep_info->num_ep_pairs].ep_id = + IPA_v4_PCIE1_EP_ID; + + IPADBG("ep_pair_info consumer_pipe_num %d", + pair_info[ep_info->num_ep_pairs].consumer_pipe_num); + IPADBG(" producer_pipe_num %d ep_id %d\n", + pair_info[ep_info->num_ep_pairs].producer_pipe_num, + pair_info[ep_info->num_ep_pairs].ep_id); + ep_info->num_ep_pairs++; + } else { + pair_info[ep_info->num_ep_pairs].consumer_pipe_num = -1; + IPADBG("ep_pair_info consumer_pipe_num %d", + pair_info[ep_info->num_ep_pairs].consumer_pipe_num); + IPADBG(" producer_pipe_num %d ep_id %d\n", + pair_info[ep_info->num_ep_pairs].producer_pipe_num, + pair_info[ep_info->num_ep_pairs].ep_id); + } + } + } + + ep_index = ipa_get_ep_mapping(IPA_CLIENT_MHI_PROD); + + if ((ep_index != -1) && ipa3_ctx->ep[ep_index].valid) { + pair_info[ep_info->num_ep_pairs].consumer_pipe_num = ep_index; + ep_index = ipa_get_ep_mapping(IPA_CLIENT_MHI_CONS); + if ((ep_index != -1) && (ipa3_ctx->ep[ep_index].valid)) { + pair_info[ep_info->num_ep_pairs].producer_pipe_num = + ep_index; + if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0) + pair_info[ep_info->num_ep_pairs].ep_id = + IPA_v4_PCIE0_EP_ID; + else + pair_info[ep_info->num_ep_pairs].ep_id = + IPA_v5_PCIE0_EP_ID; + + IPADBG("ep_pair_info consumer_pipe_num %d", + pair_info[ep_info->num_ep_pairs].consumer_pipe_num); + IPADBG(" producer_pipe_num %d ep_id %d\n", + pair_info[ep_info->num_ep_pairs].producer_pipe_num, + pair_info[ep_info->num_ep_pairs].ep_id); + ep_info->num_ep_pairs++; + } else { + pair_info[ep_info->num_ep_pairs].consumer_pipe_num = -1; + IPADBG("ep_pair_info consumer_pipe_num %d", + pair_info[ep_info->num_ep_pairs].consumer_pipe_num); + IPADBG(" producer_pipe_num %d ep_id %d\n", + pair_info[ep_info->num_ep_pairs].producer_pipe_num, + pair_info[ep_info->num_ep_pairs].ep_id); + } + } +} + +static void ipa3_get_eth_ep_info( + struct ipa_ioc_get_ep_info *ep_info, + struct ipa_ep_pair_info *pair_info + ) +{ + int ep_index = -1, i; + + ep_info->num_ep_pairs = 0; + for (i = 0; i < ep_info->max_ep_pairs; i++) { + pair_info[i].consumer_pipe_num = -1; + pair_info[i].producer_pipe_num = -1; + pair_info[i].ep_id = -1; + } + + ep_index = ipa_get_ep_mapping(IPA_CLIENT_ETHERNET2_PROD); + + if ((ep_index != -1) && ipa3_ctx->ep[ep_index].valid) { + pair_info[ep_info->num_ep_pairs].consumer_pipe_num = ep_index; + ep_index = ipa_get_ep_mapping(IPA_CLIENT_ETHERNET2_CONS); + if ((ep_index != -1) && (ipa3_ctx->ep[ep_index].valid)) { + pair_info[ep_info->num_ep_pairs].producer_pipe_num = + ep_index; + pair_info[ep_info->num_ep_pairs].ep_id = + IPA_ETH1_EP_ID; + IPADBG("ep_pair_info consumer_pipe_num %d", + pair_info[ep_info->num_ep_pairs].consumer_pipe_num); + IPADBG(" producer_pipe_num %d ep_id %d\n", + pair_info[ep_info->num_ep_pairs].producer_pipe_num, + pair_info[ep_info->num_ep_pairs].ep_id); + ep_info->num_ep_pairs++; + } else { + pair_info[ep_info->num_ep_pairs].consumer_pipe_num = -1; + IPADBG("ep_pair_info consumer_pipe_num %d", + pair_info[ep_info->num_ep_pairs].consumer_pipe_num); + IPADBG(" producer_pipe_num %d ep_id %d\n", + pair_info[ep_info->num_ep_pairs].producer_pipe_num, + pair_info[ep_info->num_ep_pairs].ep_id); + } + } + + ep_index = ipa_get_ep_mapping(IPA_CLIENT_ETHERNET_PROD); + + if ((ep_index != -1) && ipa3_ctx->ep[ep_index].valid) { + pair_info[ep_info->num_ep_pairs].consumer_pipe_num = ep_index; + ep_index = ipa_get_ep_mapping(IPA_CLIENT_ETHERNET_CONS); + if ((ep_index != -1) && (ipa3_ctx->ep[ep_index].valid)) { + pair_info[ep_info->num_ep_pairs].producer_pipe_num = + ep_index; + pair_info[ep_info->num_ep_pairs].ep_id = + IPA_ETH0_EP_ID; + + IPADBG("ep_pair_info consumer_pipe_num %d", + pair_info[ep_info->num_ep_pairs].consumer_pipe_num); + IPADBG(" producer_pipe_num %d ep_id %d\n", + pair_info[ep_info->num_ep_pairs].producer_pipe_num, + pair_info[ep_info->num_ep_pairs].ep_id); + ep_info->num_ep_pairs++; + } else { + pair_info[ep_info->num_ep_pairs].consumer_pipe_num = -1; + IPADBG("ep_pair_info consumer_pipe_num %d", + pair_info[ep_info->num_ep_pairs].consumer_pipe_num); + IPADBG(" producer_pipe_num %d ep_id %d\n", + pair_info[ep_info->num_ep_pairs].producer_pipe_num, + pair_info[ep_info->num_ep_pairs].ep_id); + } + } +} + +static int ipa3_get_ep_info(struct ipa_ioc_get_ep_info *ep_info, + u8 *param) +{ + int ret = 0; + struct ipa_ep_pair_info *pair_info = (struct ipa_ep_pair_info *)param; + + switch (ep_info->ep_type) { + case IPA_DATA_EP_TYP_HSUSB: + ipa3_get_usb_ep_info(ep_info, pair_info); + break; + + case IPA_DATA_EP_TYP_PCIE: + ipa3_get_pcie_ep_info(ep_info, pair_info); + break; + + case IPA_DATA_EP_TYP_ETH: + ipa3_get_eth_ep_info(ep_info, pair_info); + break; + + default: + IPAERR_RL("Undefined ep_type %d\n", ep_info->ep_type); + ret = -EFAULT; + break; + } + + return ret; +} + +static int ipa3_send_gsb_msg(unsigned long usr_param, uint8_t msg_type) +{ + int retval; + struct ipa_ioc_gsb_info *gsb_info; + struct ipa_msg_meta msg_meta; + void *buff; + + IPADBG("type %d\n", msg_type); + + memset(&msg_meta, 0, sizeof(msg_meta)); + msg_meta.msg_type = msg_type; + + if ((msg_type == IPA_GSB_CONNECT) || + (msg_type == IPA_GSB_DISCONNECT)) { + gsb_info = kzalloc(sizeof(struct ipa_ioc_gsb_info), + GFP_KERNEL); + if (!gsb_info) { + IPAERR("no memory\n"); + return -ENOMEM; + } + + if (copy_from_user((u8 *)gsb_info, (void __user *)usr_param, + sizeof(struct ipa_ioc_gsb_info))) { + kfree(gsb_info); + return -EFAULT; + } + + msg_meta.msg_len = sizeof(struct ipa_ioc_gsb_info); + buff = gsb_info; + } else { + IPAERR("Unexpected event\n"); + return -EFAULT; + } + + retval = ipa_send_msg(&msg_meta, buff, + ipa3_gsb_msg_free_cb); + if (retval) { + IPAERR("ipa_send_msg failed: %d, msg_type %d\n", + retval, + msg_type); + kfree(buff); + return retval; + } + IPADBG("exit\n"); + + return 0; +} + +static int ipa3_ioctl_add_rt_rule_v2(unsigned long arg) +{ + int retval = 0; + int i; + u8 header[128] = { 0 }; + int pre_entry; + u32 usr_pyld_sz; + u32 pyld_sz; + u64 uptr = 0; + u8 *param = NULL; + u8 *param2 = NULL; + u8 *kptr = NULL; + + if (copy_from_user(header, (const void __user *)arg, + sizeof(struct ipa_ioc_add_rt_rule_v2))) { + IPAERR_RL("copy_from_user fails\n"); + retval = -EFAULT; + goto free_param_kptr; + } + pre_entry = + ((struct ipa_ioc_add_rt_rule_v2 *)header)->num_rules; + if (unlikely(((struct ipa_ioc_add_rt_rule_v2 *) + header)->rule_add_size > + sizeof(struct ipa_rt_rule_add_i))) { + IPAERR_RL("unexpected rule_add_size %d\n", + ((struct ipa_ioc_add_rt_rule_v2 *) + header)->rule_add_size); + retval = -EPERM; + goto free_param_kptr; + } + /* user payload size */ + usr_pyld_sz = ((struct ipa_ioc_add_rt_rule_v2 *) + header)->rule_add_size * pre_entry; + /* actual payload structure size in kernel */ + pyld_sz = sizeof(struct ipa_rt_rule_add_i) * pre_entry; + uptr = ((struct ipa_ioc_add_rt_rule_v2 *) + header)->rules; + if (unlikely(!uptr)) { + IPAERR_RL("unexpected NULL rules\n"); + retval = -EPERM; + goto free_param_kptr; + } + /* alloc param with same payload size as user payload */ + param = memdup_user((const void __user *)uptr, + usr_pyld_sz); + if (IS_ERR(param)) { + retval = -EFAULT; + goto free_param_kptr; + } + + param2 = memdup_user((const void __user *)arg, + sizeof(struct ipa_ioc_add_rt_rule_v2)); + if (IS_ERR(param2)) { + retval = -EFAULT; + goto free_param_kptr; + } + + + /* add check in case user-space module compromised */ + if (unlikely(((struct ipa_ioc_add_rt_rule_v2 *)param2)->num_rules + != pre_entry)) { + IPAERR_RL("current %d pre %d\n", + ((struct ipa_ioc_add_rt_rule_v2 *)param2)-> + num_rules, pre_entry); + retval = -EFAULT; + goto free_param_kptr; + } + /* alloc kernel pointer with actual payload size */ + kptr = kzalloc(pyld_sz, GFP_KERNEL); + if (!kptr) { + retval = -ENOMEM; + goto free_param_kptr; + } + for (i = 0; i < pre_entry; i++) + memcpy(kptr + i * sizeof(struct ipa_rt_rule_add_i), + (void *)param + i * + ((struct ipa_ioc_add_rt_rule_v2 *) + header)->rule_add_size, + ((struct ipa_ioc_add_rt_rule_v2 *) + header)->rule_add_size); + /* modify the rule pointer to the kernel pointer */ + ((struct ipa_ioc_add_rt_rule_v2 *)header)->rules = + (u64)kptr; + if (ipa3_add_rt_rule_usr_v2( + (struct ipa_ioc_add_rt_rule_v2 *)header, true)) { + IPAERR_RL("ipa3_add_rt_rule_usr_v2 fails\n"); + retval = -EPERM; + goto free_param_kptr; + } + for (i = 0; i < pre_entry; i++) + memcpy((void *)param + i * + ((struct ipa_ioc_add_rt_rule_v2 *) + header)->rule_add_size, + kptr + i * sizeof(struct ipa_rt_rule_add_i), + ((struct ipa_ioc_add_rt_rule_v2 *) + header)->rule_add_size); + if (copy_to_user((void __user *)uptr, param, + usr_pyld_sz)) { + IPAERR_RL("copy_to_user fails\n"); + retval = -EFAULT; + goto free_param_kptr; + } + +free_param_kptr: + if (!IS_ERR(param)) + kfree(param); + if (!IS_ERR(param2)) + kfree(param2); + kfree(kptr); + + return retval; +} + +static int ipa3_ioctl_add_rt_rule_ext_v2(unsigned long arg) +{ + int retval = 0; + int i; + u8 header[128] = { 0 }; + int pre_entry; + u32 usr_pyld_sz; + u32 pyld_sz; + u64 uptr = 0; + u8 *param = NULL; + u8 *param2 = NULL; + u8 *kptr = NULL; + + if (copy_from_user(header, + (const void __user *)arg, + sizeof(struct ipa_ioc_add_rt_rule_ext_v2))) { + IPAERR_RL("copy_from_user fails\n"); + retval = -EFAULT; + goto free_param_kptr; + } + pre_entry = + ((struct ipa_ioc_add_rt_rule_ext_v2 *) + header)->num_rules; + if (unlikely(((struct ipa_ioc_add_rt_rule_ext_v2 *) + header)->rule_add_ext_size > + sizeof(struct ipa_rt_rule_add_ext_i))) { + IPAERR_RL("unexpected rule_add_size %d\n", + ((struct ipa_ioc_add_rt_rule_ext_v2 *) + header)->rule_add_ext_size); + retval = -EPERM; + goto free_param_kptr; + } + /* user payload size */ + usr_pyld_sz = ((struct ipa_ioc_add_rt_rule_ext_v2 *) + header)->rule_add_ext_size * pre_entry; + /* actual payload structure size in kernel */ + pyld_sz = sizeof(struct ipa_rt_rule_add_ext_i) + * pre_entry; + uptr = ((struct ipa_ioc_add_rt_rule_ext_v2 *) + header)->rules; + if (unlikely(!uptr)) { + IPAERR_RL("unexpected NULL rules\n"); + retval = -EPERM; + goto free_param_kptr; + } + /* alloc param with same payload size as user payload */ + param = memdup_user((const void __user *)uptr, + usr_pyld_sz); + if (IS_ERR(param)) { + retval = -EFAULT; + goto free_param_kptr; + } + + param2 = memdup_user((const void __user *)arg, + sizeof(struct ipa_ioc_add_rt_rule_ext_v2)); + if (IS_ERR(param2)) { + retval = -EFAULT; + goto free_param_kptr; + } + + + /* add check in case user-space module compromised */ + if (unlikely(((struct ipa_ioc_add_rt_rule_ext_v2 *)param2)->num_rules + != pre_entry)) { + IPAERR_RL("current %d pre %d\n", + ((struct ipa_ioc_add_rt_rule_ext_v2 *)param2)-> + num_rules, pre_entry); + retval = -EFAULT; + goto free_param_kptr; + } + /* alloc kernel pointer with actual payload size */ + kptr = kzalloc(pyld_sz, GFP_KERNEL); + if (!kptr) { + retval = -ENOMEM; + goto free_param_kptr; + } + for (i = 0; i < pre_entry; i++) + memcpy(kptr + i * + sizeof(struct ipa_rt_rule_add_ext_i), + (void *)param + i * + ((struct ipa_ioc_add_rt_rule_ext_v2 *) + header)->rule_add_ext_size, + ((struct ipa_ioc_add_rt_rule_ext_v2 *) + header)->rule_add_ext_size); + /* modify the rule pointer to the kernel pointer */ + ((struct ipa_ioc_add_rt_rule_ext_v2 *)header)->rules = + (u64)kptr; + if (ipa3_add_rt_rule_ext_v2( + (struct ipa_ioc_add_rt_rule_ext_v2 *)header, true)) { + IPAERR_RL("ipa3_add_rt_rule_ext_v2 fails\n"); + retval = -EPERM; + goto free_param_kptr; + } + for (i = 0; i < pre_entry; i++) + memcpy((void *)param + i * + ((struct ipa_ioc_add_rt_rule_ext_v2 *) + header)->rule_add_ext_size, + kptr + i * + sizeof(struct ipa_rt_rule_add_ext_i), + ((struct ipa_ioc_add_rt_rule_ext_v2 *) + header)->rule_add_ext_size); + if (copy_to_user((void __user *)uptr, param, + usr_pyld_sz)) { + IPAERR_RL("copy_to_user fails\n"); + retval = -EFAULT; + goto free_param_kptr; + } + +free_param_kptr: + if (!IS_ERR(param)) + kfree(param); + if (!IS_ERR(param2)) + kfree(param2); + kfree(kptr); + + return retval; +} + +static int ipa3_ioctl_add_rt_rule_after_v2(unsigned long arg) +{ + int retval = 0; + int i; + u8 header[128] = { 0 }; + int pre_entry; + u32 usr_pyld_sz; + u32 pyld_sz; + u64 uptr = 0; + u8 *param = NULL; + u8 *param2 = NULL; + u8 *kptr = NULL; + + if (copy_from_user(header, (const void __user *)arg, + sizeof(struct ipa_ioc_add_rt_rule_after_v2))) { + IPAERR_RL("copy_from_user fails\n"); + retval = -EFAULT; + goto free_param_kptr; + } + pre_entry = + ((struct ipa_ioc_add_rt_rule_after_v2 *) + header)->num_rules; + if (unlikely(((struct ipa_ioc_add_rt_rule_after_v2 *) + header)->rule_add_size > + sizeof(struct ipa_rt_rule_add_i))) { + IPAERR_RL("unexpected rule_add_size %d\n", + ((struct ipa_ioc_add_rt_rule_after_v2 *) + header)->rule_add_size); + retval = -EPERM; + goto free_param_kptr; + } + /* user payload size */ + usr_pyld_sz = ((struct ipa_ioc_add_rt_rule_after_v2 *) + header)->rule_add_size * pre_entry; + /* actual payload structure size in kernel */ + pyld_sz = sizeof(struct ipa_rt_rule_add_i) + * pre_entry; + uptr = ((struct ipa_ioc_add_rt_rule_after_v2 *) + header)->rules; + if (unlikely(!uptr)) { + IPAERR_RL("unexpected NULL rules\n"); + retval = -EPERM; + goto free_param_kptr; + } + /* alloc param with same payload size as user payload */ + param = memdup_user((const void __user *)uptr, + usr_pyld_sz); + if (IS_ERR(param)) { + retval = -EFAULT; + goto free_param_kptr; + } + + param2 = memdup_user((const void __user *)arg, + sizeof(struct ipa_ioc_add_rt_rule_after_v2)); + if (IS_ERR(param2)) { + retval = -EFAULT; + goto free_param_kptr; + } + + /* add check in case user-space module compromised */ + if (unlikely(((struct ipa_ioc_add_rt_rule_after_v2 *)param2)->num_rules + != pre_entry)) { + IPAERR_RL("current %d pre %d\n", + ((struct ipa_ioc_add_rt_rule_after_v2 *)param2)-> + num_rules, pre_entry); + retval = -EFAULT; + goto free_param_kptr; + } + /* alloc kernel pointer with actual payload size */ + kptr = kzalloc(pyld_sz, GFP_KERNEL); + if (!kptr) { + retval = -ENOMEM; + goto free_param_kptr; + } + for (i = 0; i < pre_entry; i++) + memcpy(kptr + i * sizeof(struct ipa_rt_rule_add_i), + (void *)param + i * + ((struct ipa_ioc_add_rt_rule_after_v2 *) + header)->rule_add_size, + ((struct ipa_ioc_add_rt_rule_after_v2 *) + header)->rule_add_size); + /* modify the rule pointer to the kernel pointer */ + ((struct ipa_ioc_add_rt_rule_after_v2 *)header)->rules = + (u64)kptr; + if (ipa3_add_rt_rule_after_v2( + (struct ipa_ioc_add_rt_rule_after_v2 *)header)) { + IPAERR_RL("ipa3_add_rt_rule_after_v2 fails\n"); + retval = -EPERM; + goto free_param_kptr; + } + for (i = 0; i < pre_entry; i++) + memcpy((void *)param + i * + ((struct ipa_ioc_add_rt_rule_after_v2 *) + header)->rule_add_size, + kptr + i * sizeof(struct ipa_rt_rule_add_i), + ((struct ipa_ioc_add_rt_rule_after_v2 *) + header)->rule_add_size); + if (copy_to_user((void __user *)uptr, param, + usr_pyld_sz)) { + IPAERR_RL("copy_to_user fails\n"); + retval = -EFAULT; + goto free_param_kptr; + } + +free_param_kptr: + if (!IS_ERR(param)) + kfree(param); + if (!IS_ERR(param2)) + kfree(param2); + kfree(kptr); + + return retval; +} + +static int ipa3_ioctl_mdfy_rt_rule_v2(unsigned long arg) +{ + int retval = 0; + int i; + u8 header[128] = { 0 }; + int pre_entry; + u32 usr_pyld_sz; + u32 pyld_sz; + u64 uptr = 0; + u8 *param = NULL; + u8 *param2 = NULL; + u8 *kptr = NULL; + + if (copy_from_user(header, (const void __user *)arg, + sizeof(struct ipa_ioc_mdfy_rt_rule_v2))) { + IPAERR_RL("copy_from_user fails\n"); + retval = -EFAULT; + goto free_param_kptr; + } + pre_entry = + ((struct ipa_ioc_mdfy_rt_rule_v2 *) + header)->num_rules; + if (unlikely(((struct ipa_ioc_mdfy_rt_rule_v2 *) + header)->rule_mdfy_size > + sizeof(struct ipa_rt_rule_mdfy_i))) { + IPAERR_RL("unexpected rule_add_size %d\n", + ((struct ipa_ioc_mdfy_rt_rule_v2 *) + header)->rule_mdfy_size); + retval = -EPERM; + goto free_param_kptr; + } + /* user payload size */ + usr_pyld_sz = ((struct ipa_ioc_mdfy_rt_rule_v2 *) + header)->rule_mdfy_size * pre_entry; + /* actual payload structure size in kernel */ + pyld_sz = sizeof(struct ipa_rt_rule_mdfy_i) + * pre_entry; + uptr = ((struct ipa_ioc_mdfy_rt_rule_v2 *) + header)->rules; + if (unlikely(!uptr)) { + IPAERR_RL("unexpected NULL rules\n"); + retval = -EPERM; + goto free_param_kptr; + } + /* alloc param with same payload size as user payload */ + param = memdup_user((const void __user *)uptr, + usr_pyld_sz); + if (IS_ERR(param)) { + retval = -EFAULT; + goto free_param_kptr; + } + + param2 = memdup_user((const void __user *)arg, + sizeof(struct ipa_ioc_mdfy_rt_rule_v2)); + if (IS_ERR(param2)) { + retval = -EFAULT; + goto free_param_kptr; + } + + /* add check in case user-space module compromised */ + if (unlikely(((struct ipa_ioc_mdfy_rt_rule_v2 *)param2)->num_rules + != pre_entry)) { + IPAERR_RL("current %d pre %d\n", + ((struct ipa_ioc_mdfy_rt_rule_v2 *)param2)-> + num_rules, pre_entry); + retval = -EFAULT; + goto free_param_kptr; + } + /* alloc kernel pointer with actual payload size */ + kptr = kzalloc(pyld_sz, GFP_KERNEL); + if (!kptr) { + retval = -ENOMEM; + goto free_param_kptr; + } + for (i = 0; i < pre_entry; i++) + memcpy(kptr + i * sizeof(struct ipa_rt_rule_mdfy_i), + (void *)param + i * + ((struct ipa_ioc_mdfy_rt_rule_v2 *) + header)->rule_mdfy_size, + ((struct ipa_ioc_mdfy_rt_rule_v2 *) + header)->rule_mdfy_size); + /* modify the rule pointer to the kernel pointer */ + ((struct ipa_ioc_mdfy_rt_rule_v2 *)header)->rules = + (u64)kptr; + if (ipa3_mdfy_rt_rule_v2((struct ipa_ioc_mdfy_rt_rule_v2 *) + header)) { + IPAERR_RL("ipa3_mdfy_rt_rule_v2 fails\n"); + retval = -EPERM; + goto free_param_kptr; + } + for (i = 0; i < pre_entry; i++) + memcpy((void *)param + i * + ((struct ipa_ioc_mdfy_rt_rule_v2 *) + header)->rule_mdfy_size, + kptr + i * sizeof(struct ipa_rt_rule_mdfy_i), + ((struct ipa_ioc_mdfy_rt_rule_v2 *) + header)->rule_mdfy_size); + if (copy_to_user((void __user *)uptr, param, + usr_pyld_sz)) { + IPAERR_RL("copy_to_user fails\n"); + retval = -EFAULT; + goto free_param_kptr; + } + +free_param_kptr: + if (!IS_ERR(param)) + kfree(param); + if (!IS_ERR(param2)) + kfree(param2); + kfree(kptr); + + return retval; +} + +static int ipa3_ioctl_add_flt_rule_v2(unsigned long arg) +{ + int retval = 0; + int i; + u8 header[128] = { 0 }; + int pre_entry; + u32 usr_pyld_sz; + u32 pyld_sz; + u64 uptr = 0; + u8 *param = NULL; + u8 *param2 = NULL; + u8 *kptr = NULL; + + if (copy_from_user(header, (const void __user *)arg, + sizeof(struct ipa_ioc_add_flt_rule_v2))) { + IPAERR_RL("copy_from_user fails\n"); + retval = -EFAULT; + goto free_param_kptr; + } + pre_entry = + ((struct ipa_ioc_add_flt_rule_v2 *)header)->num_rules; + if (unlikely(((struct ipa_ioc_add_flt_rule_v2 *) + header)->flt_rule_size > + sizeof(struct ipa_flt_rule_add_i))) { + IPAERR_RL("unexpected rule_add_size %d\n", + ((struct ipa_ioc_add_flt_rule_v2 *) + header)->flt_rule_size); + retval = -EPERM; + goto free_param_kptr; + } + /* user payload size */ + usr_pyld_sz = ((struct ipa_ioc_add_flt_rule_v2 *) + header)->flt_rule_size * pre_entry; + /* actual payload structure size in kernel */ + pyld_sz = sizeof(struct ipa_flt_rule_add_i) + * pre_entry; + uptr = ((struct ipa_ioc_add_flt_rule_v2 *) + header)->rules; + if (unlikely(!uptr)) { + IPAERR_RL("unexpected NULL rules\n"); + retval = -EPERM; + goto free_param_kptr; + } + /* alloc param with same payload size as user payload */ + param = memdup_user((const void __user *)uptr, + usr_pyld_sz); + if (IS_ERR(param)) { + retval = -EFAULT; + goto free_param_kptr; + } + + param2 = memdup_user((const void __user *)arg, + sizeof(struct ipa_ioc_add_flt_rule_v2)); + if (IS_ERR(param2)) { + retval = -EFAULT; + goto free_param_kptr; + } + + /* add check in case user-space module compromised */ + if (unlikely(((struct ipa_ioc_add_flt_rule_v2 *)param2)->num_rules + != pre_entry)) { + IPAERR_RL("current %d pre %d\n", + ((struct ipa_ioc_add_flt_rule_v2 *)param2)-> + num_rules, pre_entry); + retval = -EFAULT; + goto free_param_kptr; + } + /* alloc kernel pointer with actual payload size */ + kptr = kzalloc(pyld_sz, GFP_KERNEL); + if (!kptr) { + retval = -ENOMEM; + goto free_param_kptr; + } + for (i = 0; i < pre_entry; i++) + memcpy(kptr + i * sizeof(struct ipa_flt_rule_add_i), + (void *)param + i * + ((struct ipa_ioc_add_flt_rule_v2 *) + header)->flt_rule_size, + ((struct ipa_ioc_add_flt_rule_v2 *) + header)->flt_rule_size); + /* modify the rule pointer to the kernel pointer */ + ((struct ipa_ioc_add_flt_rule_v2 *)header)->rules = + (u64)kptr; + if (ipa3_add_flt_rule_usr_v2((struct ipa_ioc_add_flt_rule_v2 *) + header, true)) { + IPAERR_RL("ipa3_add_flt_rule_usr_v2 fails\n"); + retval = -EPERM; + goto free_param_kptr; + } + for (i = 0; i < pre_entry; i++) + memcpy((void *)param + i * + ((struct ipa_ioc_add_flt_rule_v2 *) + header)->flt_rule_size, + kptr + i * sizeof(struct ipa_flt_rule_add_i), + ((struct ipa_ioc_add_flt_rule_v2 *) + header)->flt_rule_size); + if (copy_to_user((void __user *)uptr, param, + usr_pyld_sz)) { + IPAERR_RL("copy_to_user fails\n"); + retval = -EFAULT; + goto free_param_kptr; + } +free_param_kptr: + if (!IS_ERR(param)) + kfree(param); + if (!IS_ERR(param2)) + kfree(param2); + kfree(kptr); + + return retval; +} + +static int ipa3_ioctl_add_flt_rule_after_v2(unsigned long arg) +{ + int retval = 0; + int i; + u8 header[128] = { 0 }; + int pre_entry; + u32 usr_pyld_sz; + u32 pyld_sz; + u64 uptr = 0; + u8 *param = NULL; + u8 *param2 = NULL; + u8 *kptr = NULL; + + if (copy_from_user(header, (const void __user *)arg, + sizeof(struct ipa_ioc_add_flt_rule_after_v2))) { + IPAERR_RL("copy_from_user fails\n"); + retval = -EFAULT; + goto free_param_kptr; + } + pre_entry = + ((struct ipa_ioc_add_flt_rule_after_v2 *) + header)->num_rules; + if (unlikely(((struct ipa_ioc_add_flt_rule_after_v2 *) + header)->flt_rule_size > + sizeof(struct ipa_flt_rule_add_i))) { + IPAERR_RL("unexpected rule_add_size %d\n", + ((struct ipa_ioc_add_flt_rule_after_v2 *) + header)->flt_rule_size); + retval = -EPERM; + goto free_param_kptr; + } + /* user payload size */ + usr_pyld_sz = ((struct ipa_ioc_add_flt_rule_after_v2 *) + header)->flt_rule_size * pre_entry; + /* actual payload structure size in kernel */ + pyld_sz = sizeof(struct ipa_flt_rule_add_i) + * pre_entry; + uptr = ((struct ipa_ioc_add_flt_rule_after_v2 *) + header)->rules; + if (unlikely(!uptr)) { + IPAERR_RL("unexpected NULL rules\n"); + retval = -EPERM; + goto free_param_kptr; + } + /* alloc param with same payload size as user payload */ + param = memdup_user((const void __user *)uptr, + usr_pyld_sz); + if (IS_ERR(param)) { + retval = -EFAULT; + goto free_param_kptr; + } + + param2 = memdup_user((const void __user *)arg, + sizeof(struct ipa_ioc_add_flt_rule_after_v2)); + if (IS_ERR(param2)) { + retval = -EFAULT; + goto free_param_kptr; + } + + /* add check in case user-space module compromised */ + if (unlikely(((struct ipa_ioc_add_flt_rule_after_v2 *)param2)->num_rules + != pre_entry)) { + IPAERR_RL("current %d pre %d\n", + ((struct ipa_ioc_add_flt_rule_after_v2 *)param2)-> + num_rules, pre_entry); + retval = -EFAULT; + goto free_param_kptr; + } + /* alloc kernel pointer with actual payload size */ + kptr = kzalloc(pyld_sz, GFP_KERNEL); + if (!kptr) { + retval = -ENOMEM; + goto free_param_kptr; + } + for (i = 0; i < pre_entry; i++) + memcpy(kptr + i * sizeof(struct ipa_flt_rule_add_i), + (void *)param + i * + ((struct ipa_ioc_add_flt_rule_after_v2 *) + header)->flt_rule_size, + ((struct ipa_ioc_add_flt_rule_after_v2 *) + header)->flt_rule_size); + /* modify the rule pointer to the kernel pointer */ + ((struct ipa_ioc_add_flt_rule_after_v2 *)header)->rules = + (u64)kptr; + if (ipa3_add_flt_rule_after_v2( + (struct ipa_ioc_add_flt_rule_after_v2 *)header)) { + IPAERR_RL("ipa3_add_flt_rule_after_v2 fails\n"); + retval = -EPERM; + goto free_param_kptr; + } + for (i = 0; i < pre_entry; i++) + memcpy((void *)param + i * + ((struct ipa_ioc_add_flt_rule_after_v2 *) + header)->flt_rule_size, + kptr + i * sizeof(struct ipa_flt_rule_add_i), + ((struct ipa_ioc_add_flt_rule_after_v2 *) + header)->flt_rule_size); + if (copy_to_user((void __user *)uptr, param, + usr_pyld_sz)) { + IPAERR_RL("copy_to_user fails\n"); + retval = -EFAULT; + goto free_param_kptr; + } + +free_param_kptr: + if (!IS_ERR(param)) + kfree(param); + if (!IS_ERR(param2)) + kfree(param2); + kfree(kptr); + + return retval; +} + +static int ipa3_ioctl_mdfy_flt_rule_v2(unsigned long arg) +{ + int retval = 0; + int i; + u8 header[128] = { 0 }; + int pre_entry; + u32 usr_pyld_sz; + u32 pyld_sz; + u64 uptr = 0; + u8 *param = NULL; + u8 *param2 = NULL; + u8 *kptr = NULL; + + if (copy_from_user(header, (const void __user *)arg, + sizeof(struct ipa_ioc_mdfy_flt_rule_v2))) { + IPAERR_RL("copy_from_user fails\n"); + retval = -EFAULT; + goto free_param_kptr; + } + pre_entry = + ((struct ipa_ioc_mdfy_flt_rule_v2 *) + header)->num_rules; + if (unlikely(((struct ipa_ioc_mdfy_flt_rule_v2 *) + header)->rule_mdfy_size > + sizeof(struct ipa_flt_rule_mdfy_i))) { + IPAERR_RL("unexpected rule_add_size %d\n", + ((struct ipa_ioc_mdfy_flt_rule_v2 *) + header)->rule_mdfy_size); + retval = -EPERM; + goto free_param_kptr; + } + /* user payload size */ + usr_pyld_sz = ((struct ipa_ioc_mdfy_flt_rule_v2 *) + header)->rule_mdfy_size * pre_entry; + /* actual payload structure size in kernel */ + pyld_sz = sizeof(struct ipa_flt_rule_mdfy_i) + * pre_entry; + uptr = ((struct ipa_ioc_mdfy_flt_rule_v2 *) + header)->rules; + if (unlikely(!uptr)) { + IPAERR_RL("unexpected NULL rules\n"); + retval = -EPERM; + goto free_param_kptr; + } + /* alloc param with same payload size as user payload */ + param = memdup_user((const void __user *)uptr, + usr_pyld_sz); + if (IS_ERR(param)) { + retval = -EFAULT; + goto free_param_kptr; + } + + param2 = memdup_user((const void __user *)arg, + sizeof(struct ipa_ioc_mdfy_flt_rule_v2)); + if (IS_ERR(param2)) { + retval = -EFAULT; + goto free_param_kptr; + } + + /* add check in case user-space module compromised */ + if (unlikely(((struct ipa_ioc_mdfy_flt_rule_v2 *)param2)->num_rules + != pre_entry)) { + IPAERR_RL("current %d pre %d\n", + ((struct ipa_ioc_mdfy_flt_rule_v2 *)param2)-> + num_rules, pre_entry); + retval = -EFAULT; + goto free_param_kptr; + } + /* alloc kernel pointer with actual payload size */ + kptr = kzalloc(pyld_sz, GFP_KERNEL); + if (!kptr) { + retval = -ENOMEM; + goto free_param_kptr; + } + for (i = 0; i < pre_entry; i++) + memcpy(kptr + i * sizeof(struct ipa_flt_rule_mdfy_i), + (void *)param + i * + ((struct ipa_ioc_mdfy_flt_rule_v2 *) + header)->rule_mdfy_size, + ((struct ipa_ioc_mdfy_flt_rule_v2 *) + header)->rule_mdfy_size); + /* modify the rule pointer to the kernel pointer */ + ((struct ipa_ioc_mdfy_flt_rule_v2 *)header)->rules = + (u64)kptr; + if (ipa3_mdfy_flt_rule_v2 + ((struct ipa_ioc_mdfy_flt_rule_v2 *)header)) { + IPAERR_RL("ipa3_mdfy_flt_rule_v2 fails\n"); + retval = -EPERM; + goto free_param_kptr; + } + for (i = 0; i < pre_entry; i++) + memcpy((void *)param + i * + ((struct ipa_ioc_mdfy_flt_rule_v2 *) + header)->rule_mdfy_size, + kptr + i * sizeof(struct ipa_flt_rule_mdfy_i), + ((struct ipa_ioc_mdfy_flt_rule_v2 *) + header)->rule_mdfy_size); + if (copy_to_user((void __user *)uptr, param, + usr_pyld_sz)) { + IPAERR_RL("copy_to_user fails\n"); + retval = -EFAULT; + goto free_param_kptr; + } + +free_param_kptr: + if (!IS_ERR(param)) + kfree(param); + if (!IS_ERR(param2)) + kfree(param2); + kfree(kptr); + + return retval; +} + +static int ipa3_ioctl_fnr_counter_alloc(unsigned long arg) +{ + int retval = 0; + u8 header[128] = { 0 }; + + if (copy_from_user(header, (const void __user *)arg, + sizeof(struct ipa_ioc_flt_rt_counter_alloc))) { + IPAERR_RL("copy_from_user fails\n"); + return -EFAULT; + } + if (((struct ipa_ioc_flt_rt_counter_alloc *) + header)->hw_counter.num_counters > + IPA_FLT_RT_HW_COUNTER || + ((struct ipa_ioc_flt_rt_counter_alloc *) + header)->sw_counter.num_counters > + IPA_FLT_RT_SW_COUNTER) { + IPAERR_RL("failed: wrong sw/hw num_counters\n"); + return -EPERM; + } + if (((struct ipa_ioc_flt_rt_counter_alloc *) + header)->hw_counter.num_counters == 0 && + ((struct ipa_ioc_flt_rt_counter_alloc *) + header)->sw_counter.num_counters == 0) { + IPAERR_RL("failed: both sw/hw num_counters 0\n"); + return -EPERM; + } + retval = ipa3_alloc_counter_id + ((struct ipa_ioc_flt_rt_counter_alloc *)header); + if (retval < 0) { + IPAERR_RL("ipa3_alloc_counter_id failed\n"); + return retval; + } + if (copy_to_user((void __user *)arg, header, + sizeof(struct ipa_ioc_flt_rt_counter_alloc))) { + IPAERR_RL("copy_to_user fails\n"); + ipa3_counter_remove_hdl( + ((struct ipa_ioc_flt_rt_counter_alloc *) + header)->hdl); + return -EFAULT; + } + return 0; +} + +static int ipa3_ioctl_fnr_counter_query(unsigned long arg) +{ + int retval = 0; + int i; + u8 header[128] = { 0 }; + int pre_entry; + u32 usr_pyld_sz; + u32 pyld_sz; + u64 uptr = 0; + u8 *param = NULL; + u8 *kptr = NULL; + + if (copy_from_user(header, (const void __user *)arg, + sizeof(struct ipa_ioc_flt_rt_query))) { + IPAERR_RL("copy_from_user fails\n"); + retval = -EFAULT; + goto free_param_kptr; + } + pre_entry = + ((struct ipa_ioc_flt_rt_query *) + header)->end_id - ((struct ipa_ioc_flt_rt_query *) + header)->start_id + 1; + if (pre_entry <= 0 || pre_entry > IPA_MAX_FLT_RT_CNT_INDEX) { + IPAERR("IPA_IOC_FNR_COUNTER_QUERY failed: num %d\n", + pre_entry); + retval = -EPERM; + goto free_param_kptr; + } + if (((struct ipa_ioc_flt_rt_query *)header)->stats_size + > sizeof(struct ipa_flt_rt_stats)) { + IPAERR_RL("unexpected stats_size %d\n", + ((struct ipa_ioc_flt_rt_query *)header)->stats_size); + retval = -EPERM; + goto free_param_kptr; + } + /* user payload size */ + usr_pyld_sz = ((struct ipa_ioc_flt_rt_query *) + header)->stats_size * pre_entry; + /* actual payload structure size in kernel */ + pyld_sz = sizeof(struct ipa_flt_rt_stats) * pre_entry; + uptr = ((struct ipa_ioc_flt_rt_query *) + header)->stats; + if (unlikely(!uptr)) { + IPAERR_RL("unexpected NULL rules\n"); + retval = -EPERM; + goto free_param_kptr; + } + /* alloc param with same payload size as user payload */ + param = memdup_user((const void __user *)uptr, + usr_pyld_sz); + if (IS_ERR(param)) { + retval = -EFAULT; + goto free_param_kptr; + } + /* alloc kernel pointer with actual payload size */ + kptr = kzalloc(pyld_sz, GFP_KERNEL); + if (!kptr) { + retval = -ENOMEM; + goto free_param_kptr; + } + for (i = 0; i < pre_entry; i++) + memcpy(kptr + i * sizeof(struct ipa_flt_rt_stats), + (void *)param + i * + ((struct ipa_ioc_flt_rt_query *) + header)->stats_size, + ((struct ipa_ioc_flt_rt_query *) + header)->stats_size); + /* modify the rule pointer to the kernel pointer */ + ((struct ipa_ioc_flt_rt_query *) + header)->stats = (u64)kptr; + retval = ipa_get_flt_rt_stats + ((struct ipa_ioc_flt_rt_query *)header); + if (retval < 0) { + IPAERR("ipa_get_flt_rt_stats failed\n"); + retval = -EPERM; + goto free_param_kptr; + } + for (i = 0; i < pre_entry; i++) + memcpy((void *)param + i * + ((struct ipa_ioc_flt_rt_query *) + header)->stats_size, + kptr + i * sizeof(struct ipa_flt_rt_stats), + ((struct ipa_ioc_flt_rt_query *) + header)->stats_size); + if (copy_to_user((void __user *)uptr, param, + usr_pyld_sz)) { + IPAERR_RL("copy_to_user fails\n"); + retval = -EFAULT; + goto free_param_kptr; + } + +free_param_kptr: + if (!IS_ERR(param)) + kfree(param); + kfree(kptr); + + return retval; +} + +static int ipa3_ioctl_fnr_counter_set(unsigned long arg) +{ + u8 header[128] = { 0 }; + uint8_t value; + + if (copy_from_user(header, (const void __user *)arg, + sizeof(struct ipa_ioc_fnr_index_info))) { + IPAERR_RL("copy_from_user fails\n"); + return -EFAULT; + } + + value = ((struct ipa_ioc_fnr_index_info *) + header)->hw_counter_offset; + if (value <= 0 || value > IPA_MAX_FLT_RT_CNT_INDEX) { + IPAERR("hw_counter_offset failed: num %d\n", + value); + return -EPERM; + } + + ipa3_ctx->fnr_info.hw_counter_offset = value; + + value = ((struct ipa_ioc_fnr_index_info *) + header)->sw_counter_offset; + if (value <= 0 || value > IPA_MAX_FLT_RT_CNT_INDEX) { + IPAERR("sw_counter_offset failed: num %d\n", + value); + return -EPERM; + } + ipa3_ctx->fnr_info.sw_counter_offset = value; + /* reset when ipacm-cleanup */ + ipa3_ctx->fnr_info.valid = true; + IPADBG("fnr_info hw=%d, hw=%d\n", + ipa3_ctx->fnr_info.hw_counter_offset, + ipa3_ctx->fnr_info.sw_counter_offset); + return 0; +} + +static int proc_sram_info_rqst( + unsigned long arg) +{ + struct ipa_nat_in_sram_info sram_info = { 0 }; + + if (ipa3_nat_get_sram_info(&sram_info)) + return -EFAULT; + + if (copy_to_user( + (void __user *) arg, + &sram_info, + sizeof(struct ipa_nat_in_sram_info))) + return -EFAULT; + + return 0; +} + +static void ipa3_general_free_cb(void *buff, u32 len, u32 type) +{ + if (!buff) { + IPAERR("Null buffer\n"); + return; + } + kfree(buff); +} + +static int ipa3_send_mac_flt_list(unsigned long usr_param) +{ + int retval; + struct ipa_msg_meta msg_meta; + void *buff; + + buff = kzalloc(sizeof(struct ipa_ioc_mac_client_list_type), + GFP_KERNEL); + if (!buff) + return -ENOMEM; + + if (copy_from_user(buff, (const void __user *)usr_param, + sizeof(struct ipa_ioc_mac_client_list_type))) { + kfree(buff); + return -EFAULT; + } + memset(&msg_meta, 0, sizeof(struct ipa_msg_meta)); + msg_meta.msg_type = IPA_MAC_FLT_EVENT; + msg_meta.msg_len = sizeof(struct ipa_ioc_mac_client_list_type); + + IPADBG("No of clients: %d, flt state: %d\n", + ((struct ipa_ioc_mac_client_list_type *)buff)->num_of_clients, + ((struct ipa_ioc_mac_client_list_type *)buff)->flt_state); + + retval = ipa_send_msg(&msg_meta, buff, + ipa3_general_free_cb); + if (retval) { + IPAERR("ipa_send_msg failed: %d, msg_type %d\n", + retval, + msg_meta.msg_type); + kfree(buff); + return retval; + } + return 0; +} + +static int ipa3_send_pkt_threshold(unsigned long usr_param) +{ + int retval; + struct ipa_msg_meta msg_meta; + void *buff1, *buff2; + + buff1 = kzalloc(sizeof(struct ipa_ioc_set_pkt_threshold), + GFP_KERNEL); + if (!buff1) + return -ENOMEM; + + if (copy_from_user(buff1, (const void __user *)usr_param, + sizeof(struct ipa_ioc_set_pkt_threshold))) { + kfree(buff1); + return -EFAULT; + } + + if (((struct ipa_ioc_set_pkt_threshold *)buff1)->ioctl_data_size != + sizeof(struct ipa_set_pkt_threshold)) { + IPAERR("IPA_IOC_SET_PKT_THRESHOLD size not match(%d,%d)!\n", + ((struct ipa_ioc_set_pkt_threshold *)buff1)->ioctl_data_size, + sizeof(struct ipa_set_pkt_threshold)); + kfree(buff1); + return -EFAULT; + } + + buff2 = kzalloc(sizeof(struct ipa_set_pkt_threshold), + GFP_KERNEL); + if (!buff2) { + IPAERR("ipa_set_pkt_threshold buff2 allocate failure\n"); + kfree(buff1); + return -ENOMEM; + } + + if (copy_from_user(buff2, u64_to_user_ptr( + ((struct ipa_ioc_set_pkt_threshold *)buff1)->ioctl_ptr), + sizeof(struct ipa_set_pkt_threshold))) { + IPAERR("Failed to copy ipa_set_pkt_threshold\n"); + kfree(buff1); + kfree(buff2); + return -EFAULT; + } + + + memset(&msg_meta, 0, sizeof(struct ipa_msg_meta)); + msg_meta.msg_type = IPA_PKT_THRESHOLD_EVENT; + msg_meta.msg_len = sizeof(struct ipa_set_pkt_threshold); + + IPADBG("pkt thr enable: %d, pkt_threshold: %d\n", + ((struct ipa_set_pkt_threshold *)buff2)->pkt_threshold_enable, + ((struct ipa_set_pkt_threshold *)buff2)->pkt_threshold); + + retval = ipa_send_msg(&msg_meta, buff2, + ipa3_general_free_cb); + if (retval) { + IPAERR("ipa_send_msg failed: %d, msg_type %d\n", + retval, + msg_meta.msg_type); + kfree(buff1); + kfree(buff2); + return retval; + } + return 0; +} + +static int ipa3_send_sw_flt_list(unsigned long usr_param) +{ + int retval; + struct ipa_msg_meta msg_meta; + struct ipa_ioc_sw_flt_list_type sw_flt_list; + void *buff; + + if (copy_from_user(&sw_flt_list, (const void __user *)usr_param, + sizeof(struct ipa_ioc_sw_flt_list_type))) { + IPAERR("Copy ipa_ioc_sw_flt_list_type failure\n"); + return -EFAULT; + } + + if (sw_flt_list.ioctl_data_size != + sizeof(struct ipa_sw_flt_list_type)) { + IPAERR("IPA_IOC_SET_SW_FLT size not match(%d,%d)!\n", + sw_flt_list.ioctl_data_size, + sizeof(struct ipa_sw_flt_list_type)); + return -EFAULT; + } + + buff = kzalloc(sizeof(struct ipa_sw_flt_list_type), + GFP_KERNEL); + if (!buff) { + IPAERR("ipa_sw_flt_list_type mem-allocate failure\n"); + return -ENOMEM; + } + + if (copy_from_user(buff, u64_to_user_ptr(sw_flt_list.ioctl_ptr), + sizeof(struct ipa_sw_flt_list_type))) { + IPAERR("Failed to copy ipa_sw_flt_list_type\n"); + kfree(buff); + return -EFAULT; + } + memset(&msg_meta, 0, sizeof(struct ipa_msg_meta)); + msg_meta.msg_type = IPA_SW_FLT_EVENT; + msg_meta.msg_len = sizeof(struct ipa_sw_flt_list_type); + + IPADBG("No of clients: %d, mac-flt enable: %d\n", + ((struct ipa_sw_flt_list_type *)buff)->num_of_mac, + ((struct ipa_sw_flt_list_type *)buff)->mac_enable); + + IPADBG("No of segs: %d, ipv4-seg-flt enable: %d v6-offload %d\n", + ((struct ipa_sw_flt_list_type *)buff)->num_of_ipv4_segs, + ((struct ipa_sw_flt_list_type *)buff)->ipv4_segs_enable, + ((struct ipa_sw_flt_list_type *)buff)->ipv4_segs_ipv6_offload); + + IPADBG("No of ifaces: %d, iface-flt enable: %d\n", + ((struct ipa_sw_flt_list_type *)buff)->num_of_iface, + ((struct ipa_sw_flt_list_type *)buff)->iface_enable); + + retval = ipa_send_msg(&msg_meta, buff, + ipa3_general_free_cb); + if (retval) { + IPAERR("ipa_send_msg failed: %d, msg_type %d\n", + retval, + msg_meta.msg_type); + kfree(buff); + return retval; + } + return 0; +} + +static int ipa3_send_ippt_sw_flt_list(unsigned long usr_param) +{ + int retval; + struct ipa_msg_meta msg_meta; + struct ipa_ioc_sw_flt_list_type sw_flt_list; + void *buff; + + if (copy_from_user(&sw_flt_list, (const void __user *)usr_param, + sizeof(struct ipa_ioc_sw_flt_list_type))) { + IPAERR("Copy ipa_ioc_sw_flt_list_type failure\n"); + return -EFAULT; + } + + /* Expect ipa_ippt_sw_flt_list_type struct*/ + if (sw_flt_list.ioctl_data_size != + sizeof(struct ipa_ippt_sw_flt_list_type)) { + IPAERR("IPA_IOC_SET_IPPT_SW_FLT size not match(%d,%d)!\n", + sw_flt_list.ioctl_data_size, + sizeof(struct ipa_ippt_sw_flt_list_type)); + return -EFAULT; + } + + buff = kzalloc(sizeof(struct ipa_ippt_sw_flt_list_type), + GFP_KERNEL); + if (!buff) { + IPAERR("ipa_ippt_sw_flt_list_type mem-allocate failure\n"); + return -ENOMEM; + } + + if (copy_from_user(buff, u64_to_user_ptr(sw_flt_list.ioctl_ptr), + sizeof(struct ipa_ippt_sw_flt_list_type))) { + IPAERR("Failed to copy ipa_ippt_sw_flt_list_type\n"); + kfree(buff); + return -EFAULT; + } + memset(&msg_meta, 0, sizeof(struct ipa_msg_meta)); + msg_meta.msg_type = IPA_IPPT_SW_FLT_EVENT; + msg_meta.msg_len = sizeof(struct ipa_ippt_sw_flt_list_type); + + IPADBG("Num of ipv4: %d, ipv4 enable: %d \n", + ((struct ipa_ippt_sw_flt_list_type *)buff)->num_of_ipv4, + ((struct ipa_ippt_sw_flt_list_type *)buff)->ipv4_enable); + + IPADBG("Num of ports: %d, port enable: %d\n", + ((struct ipa_ippt_sw_flt_list_type *)buff)->num_of_port, + ((struct ipa_ippt_sw_flt_list_type *)buff)->port_enable); + + retval = ipa_send_msg(&msg_meta, buff, + ipa3_general_free_cb); + if (retval) { + IPAERR("ipa_send_msg failed: %d, msg_type %d\n", + retval, + msg_meta.msg_type); + kfree(buff); + return retval; + } + return 0; +} + +/** + * ipa3_send_macsec_info() - Pass macsec mapping to the IPACM + * @event_type: Type of the event - UP or DOWN + * @map: pointer to macsec to eth mapping structure + * + * Returns: 0 on success, negative on failure + */ +int ipa3_send_macsec_info(enum ipa_macsec_event event_type, struct ipa_macsec_map *map) +{ + struct ipa_msg_meta msg_meta; + int res = 0; + + if (!map) { + IPAERR("Bad arg: info is NULL\n"); + res = -EIO; + goto done; + } + + /* + * Prep and send msg to ipacm + */ + memset(&msg_meta, 0, sizeof(struct ipa_msg_meta)); + msg_meta.msg_type = event_type; + msg_meta.msg_len = sizeof(struct ipa_macsec_map); + + /* + * Post event to ipacm + */ + res = ipa_send_msg(&msg_meta, map, ipa3_general_free_cb); + + if (res) { + IPAERR_RL("ipa_send_msg failed: %d\n", res); + kfree(map); + goto done; + } + +done: + return res; +} + +static long ipa3_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) +{ + int retval = 0; + u32 pyld_sz; + u8 header[512] = { 0 }; + u8 *param = NULL; + bool is_vlan_mode; + struct ipa_ioc_coal_evict_policy evict_pol; + struct ipa_ioc_nat_alloc_mem nat_mem; + struct ipa_ioc_nat_ipv6ct_table_alloc table_alloc; + struct ipa_ioc_v4_nat_init nat_init; + struct ipa_ioc_ipv6ct_init ipv6ct_init; + struct ipa_ioc_v4_nat_del nat_del; + struct ipa_ioc_nat_ipv6ct_table_del table_del; + struct ipa_ioc_nat_pdn_entry mdfy_pdn; + struct ipa_ioc_nat_dma_cmd *table_dma_cmd; + struct ipa_ioc_get_vlan_mode vlan_mode; + struct ipa_ioc_wigig_fst_switch fst_switch; + struct ipa_ioc_eogre_info eogre_info; + struct ipa_ioc_macsec_info macsec_info; + struct ipa_macsec_map *macsec_map; +#if defined(CONFIG_IPA_TSP) + struct ipa_ioc_tsp_ingress_class_get ingr_tc_get; + struct ipa_ioc_tsp_egress_class_get egr_tc_get; + struct ipa_ioc_tsp_egress_prod_get egr_ep_get; + struct ipa_ioc_tsp_ingress_class_set ingr_tc_set; + struct ipa_ioc_tsp_egress_class_set egr_tc_set; + struct ipa_ioc_tsp_egress_prod_set egr_ep_set; + u32 u32temp; +#endif + bool send2uC, send2ipacm; + size_t sz; + int pre_entry; + int hdl; + unsigned long uptr = 0; + struct ipa_ioc_get_ep_info ep_info; + + IPADBG("cmd=%x nr=%d\n", cmd, _IOC_NR(cmd)); + + if (_IOC_TYPE(cmd) != IPA_IOC_MAGIC) + return -ENOTTY; + + if (!ipa_is_ready()) { + IPAERR("IPA not ready, waiting for init completion\n"); + wait_for_completion(&ipa3_ctx->init_completion_obj); + } + + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + + switch (cmd) { + case IPA_IOC_COAL_EVICT_POLICY: + if (copy_from_user( + &evict_pol, + (const void __user *) arg, + sizeof(struct ipa_ioc_coal_evict_policy))) { + IPAERR_RL("copy_from_user fails\n"); + retval = -EFAULT; + break; + } + retval = ipa3_set_evict_policy(&evict_pol); + break; + case IPA_IOC_ALLOC_NAT_MEM: + if (copy_from_user(&nat_mem, (const void __user *)arg, + sizeof(struct ipa_ioc_nat_alloc_mem))) { + retval = -EFAULT; + break; + } + /* null terminate the string */ + nat_mem.dev_name[IPA_RESOURCE_NAME_MAX - 1] = '\0'; + + if (ipa3_allocate_nat_device(&nat_mem)) { + retval = -EFAULT; + break; + } + if (copy_to_user((void __user *)arg, &nat_mem, + sizeof(struct ipa_ioc_nat_alloc_mem))) { + retval = -EFAULT; + break; + } + break; + case IPA_IOC_ALLOC_NAT_TABLE: + if (copy_from_user(&table_alloc, (const void __user *)arg, + sizeof(struct ipa_ioc_nat_ipv6ct_table_alloc))) { + retval = -EFAULT; + break; + } + + if (ipa3_allocate_nat_table(&table_alloc)) { + retval = -EFAULT; + break; + } + if (table_alloc.offset && + copy_to_user((void __user *)arg, &table_alloc, sizeof( + struct ipa_ioc_nat_ipv6ct_table_alloc))) { + retval = -EFAULT; + break; + } + break; + + case IPA_IOC_ALLOC_IPV6CT_TABLE: + if (copy_from_user(&table_alloc, (const void __user *)arg, + sizeof(struct ipa_ioc_nat_ipv6ct_table_alloc))) { + retval = -EFAULT; + break; + } + + if (ipa3_allocate_ipv6ct_table(&table_alloc)) { + retval = -EFAULT; + break; + } + if (table_alloc.offset && + copy_to_user((void __user *)arg, &table_alloc, sizeof( + struct ipa_ioc_nat_ipv6ct_table_alloc))) { + retval = -EFAULT; + break; + } + break; + + case IPA_IOC_V4_INIT_NAT: + if (copy_from_user(&nat_init, (const void __user *)arg, + sizeof(struct ipa_ioc_v4_nat_init))) { + retval = -EFAULT; + break; + } + + if (ipa3_nat_init_cmd(&nat_init)) { + retval = -EFAULT; + break; + } + break; + + case IPA_IOC_INIT_IPV6CT_TABLE: + if (copy_from_user(&ipv6ct_init, (const void __user *)arg, + sizeof(struct ipa_ioc_ipv6ct_init))) { + retval = -EFAULT; + break; + } + if (ipa3_ipv6ct_init_cmd(&ipv6ct_init)) { + retval = -EFAULT; + break; + } + break; + + case IPA_IOC_TABLE_DMA_CMD: + table_dma_cmd = (struct ipa_ioc_nat_dma_cmd *)header; + if (copy_from_user(header, (const void __user *)arg, + sizeof(struct ipa_ioc_nat_dma_cmd))) { + retval = -EFAULT; + break; + } + pre_entry = table_dma_cmd->entries; + pyld_sz = sizeof(struct ipa_ioc_nat_dma_cmd) + + pre_entry * sizeof(struct ipa_ioc_nat_dma_one); + param = memdup_user((const void __user *)arg, pyld_sz); + if (IS_ERR(param)) { + retval = PTR_ERR(param); + break; + } + table_dma_cmd = (struct ipa_ioc_nat_dma_cmd *)param; + /* add check in case user-space module compromised */ + if (unlikely(table_dma_cmd->entries != pre_entry)) { + IPAERR_RL("current %d pre %d\n", + table_dma_cmd->entries, pre_entry); + retval = -EFAULT; + break; + } + if (ipa3_table_dma_cmd(table_dma_cmd)) { + retval = -EFAULT; + break; + } + break; + + case IPA_IOC_V4_DEL_NAT: + if (copy_from_user(&nat_del, (const void __user *)arg, + sizeof(struct ipa_ioc_v4_nat_del))) { + retval = -EFAULT; + break; + } + if (ipa3_nat_del_cmd(&nat_del)) { + retval = -EFAULT; + break; + } + break; + + case IPA_IOC_DEL_NAT_TABLE: + if (copy_from_user(&table_del, (const void __user *)arg, + sizeof(struct ipa_ioc_nat_ipv6ct_table_del))) { + retval = -EFAULT; + break; + } + + if (ipa3_del_nat_table(&table_del)) { + retval = -EFAULT; + break; + } + break; + + case IPA_IOC_DEL_IPV6CT_TABLE: + if (copy_from_user(&table_del, (const void __user *)arg, + sizeof(struct ipa_ioc_nat_ipv6ct_table_del))) { + retval = -EFAULT; + break; + } + + if (ipa3_del_ipv6ct_table(&table_del)) { + retval = -EFAULT; + break; + } + break; + + case IPA_IOC_NAT_MODIFY_PDN: + if (copy_from_user(&mdfy_pdn, (const void __user *)arg, + sizeof(struct ipa_ioc_nat_pdn_entry))) { + retval = -EFAULT; + break; + } + if (ipa3_nat_mdfy_pdn(&mdfy_pdn)) { + retval = -EFAULT; + break; + } + break; + + case IPA_IOC_ADD_HDR: + if (copy_from_user(header, (const void __user *)arg, + sizeof(struct ipa_ioc_add_hdr))) { + retval = -EFAULT; + break; + } + pre_entry = + ((struct ipa_ioc_add_hdr *)header)->num_hdrs; + pyld_sz = + sizeof(struct ipa_ioc_add_hdr) + + pre_entry * sizeof(struct ipa_hdr_add); + param = memdup_user((const void __user *)arg, pyld_sz); + if (IS_ERR(param)) { + retval = PTR_ERR(param); + break; + } + /* add check in case user-space module compromised */ + if (unlikely(((struct ipa_ioc_add_hdr *)param)->num_hdrs + != pre_entry)) { + IPAERR_RL("current %d pre %d\n", + ((struct ipa_ioc_add_hdr *)param)->num_hdrs, + pre_entry); + retval = -EFAULT; + break; + } + if (ipa3_add_hdr_usr((struct ipa_ioc_add_hdr *)param, + true)) { + retval = -EFAULT; + break; + } + if (copy_to_user((void __user *)arg, param, pyld_sz)) { + retval = -EFAULT; + break; + } + break; + + case IPA_IOC_DEL_HDR: + if (copy_from_user(header, (const void __user *)arg, + sizeof(struct ipa_ioc_del_hdr))) { + retval = -EFAULT; + break; + } + pre_entry = + ((struct ipa_ioc_del_hdr *)header)->num_hdls; + pyld_sz = + sizeof(struct ipa_ioc_del_hdr) + + pre_entry * sizeof(struct ipa_hdr_del); + param = memdup_user((const void __user *)arg, pyld_sz); + if (IS_ERR(param)) { + retval = PTR_ERR(param); + break; + } + /* add check in case user-space module compromised */ + if (unlikely(((struct ipa_ioc_del_hdr *)param)->num_hdls + != pre_entry)) { + IPAERR_RL("current %d pre %d\n", + ((struct ipa_ioc_del_hdr *)param)->num_hdls, + pre_entry); + retval = -EFAULT; + break; + } + if (ipa3_del_hdr_by_user((struct ipa_ioc_del_hdr *)param, + true)) { + retval = -EFAULT; + break; + } + if (copy_to_user((void __user *)arg, param, pyld_sz)) { + retval = -EFAULT; + break; + } + break; + + case IPA_IOC_ADD_RT_RULE: + if (copy_from_user(header, (const void __user *)arg, + sizeof(struct ipa_ioc_add_rt_rule))) { + retval = -EFAULT; + break; + } + pre_entry = + ((struct ipa_ioc_add_rt_rule *)header)->num_rules; + pyld_sz = + sizeof(struct ipa_ioc_add_rt_rule) + + pre_entry * sizeof(struct ipa_rt_rule_add); + param = memdup_user((const void __user *)arg, pyld_sz); + if (IS_ERR(param)) { + retval = PTR_ERR(param); + break; + } + /* add check in case user-space module compromised */ + if (unlikely(((struct ipa_ioc_add_rt_rule *)param)->num_rules + != pre_entry)) { + IPAERR_RL("current %d pre %d\n", + ((struct ipa_ioc_add_rt_rule *)param)-> + num_rules, + pre_entry); + retval = -EFAULT; + break; + } + if (ipa3_add_rt_rule_usr((struct ipa_ioc_add_rt_rule *)param, + true)) { + retval = -EFAULT; + break; + } + if (copy_to_user((void __user *)arg, param, pyld_sz)) { + retval = -EFAULT; + break; + } + break; + + case IPA_IOC_ADD_RT_RULE_EXT: + if (copy_from_user(header, + (const void __user *)arg, + sizeof(struct ipa_ioc_add_rt_rule_ext))) { + retval = -EFAULT; + break; + } + pre_entry = + ((struct ipa_ioc_add_rt_rule_ext *)header)->num_rules; + pyld_sz = + sizeof(struct ipa_ioc_add_rt_rule_ext) + + pre_entry * sizeof(struct ipa_rt_rule_add_ext); + param = memdup_user((const void __user *)arg, pyld_sz); + if (IS_ERR(param)) { + retval = PTR_ERR(param); + break; + } + /* add check in case user-space module compromised */ + if (unlikely( + ((struct ipa_ioc_add_rt_rule_ext *)param)->num_rules + != pre_entry)) { + IPAERR(" prevent memory corruption(%d not match %d)\n", + ((struct ipa_ioc_add_rt_rule_ext *)param)-> + num_rules, + pre_entry); + retval = -EINVAL; + break; + } + if (ipa3_add_rt_rule_ext( + (struct ipa_ioc_add_rt_rule_ext *)param)) { + retval = -EFAULT; + break; + } + if (copy_to_user((void __user *)arg, param, pyld_sz)) { + retval = -EFAULT; + break; + } + break; + + case IPA_IOC_ADD_RT_RULE_AFTER: + if (copy_from_user(header, (const void __user *)arg, + sizeof(struct ipa_ioc_add_rt_rule_after))) { + + retval = -EFAULT; + break; + } + pre_entry = + ((struct ipa_ioc_add_rt_rule_after *)header)->num_rules; + pyld_sz = + sizeof(struct ipa_ioc_add_rt_rule_after) + + pre_entry * sizeof(struct ipa_rt_rule_add); + param = memdup_user((const void __user *)arg, pyld_sz); + if (IS_ERR(param)) { + retval = PTR_ERR(param); + break; + } + /* add check in case user-space module compromised */ + if (unlikely(((struct ipa_ioc_add_rt_rule_after *)param)-> + num_rules != pre_entry)) { + IPAERR_RL("current %d pre %d\n", + ((struct ipa_ioc_add_rt_rule_after *)param)-> + num_rules, + pre_entry); + retval = -EFAULT; + break; + } + if (ipa3_add_rt_rule_after( + (struct ipa_ioc_add_rt_rule_after *)param)) { + + retval = -EFAULT; + break; + } + if (copy_to_user((void __user *)arg, param, pyld_sz)) { + retval = -EFAULT; + break; + } + break; + + case IPA_IOC_MDFY_RT_RULE: + if (copy_from_user(header, (const void __user *)arg, + sizeof(struct ipa_ioc_mdfy_rt_rule))) { + retval = -EFAULT; + break; + } + pre_entry = + ((struct ipa_ioc_mdfy_rt_rule *)header)->num_rules; + pyld_sz = + sizeof(struct ipa_ioc_mdfy_rt_rule) + + pre_entry * sizeof(struct ipa_rt_rule_mdfy); + param = memdup_user((const void __user *)arg, pyld_sz); + if (IS_ERR(param)) { + retval = PTR_ERR(param); + break; + } + /* add check in case user-space module compromised */ + if (unlikely(((struct ipa_ioc_mdfy_rt_rule *)param)->num_rules + != pre_entry)) { + IPAERR_RL("current %d pre %d\n", + ((struct ipa_ioc_mdfy_rt_rule *)param)-> + num_rules, + pre_entry); + retval = -EFAULT; + break; + } + if (ipa3_mdfy_rt_rule((struct ipa_ioc_mdfy_rt_rule *)param)) { + retval = -EFAULT; + break; + } + if (copy_to_user((void __user *)arg, param, pyld_sz)) { + retval = -EFAULT; + break; + } + break; + + case IPA_IOC_DEL_RT_RULE: + if (copy_from_user(header, (const void __user *)arg, + sizeof(struct ipa_ioc_del_rt_rule))) { + retval = -EFAULT; + break; + } + pre_entry = + ((struct ipa_ioc_del_rt_rule *)header)->num_hdls; + pyld_sz = + sizeof(struct ipa_ioc_del_rt_rule) + + pre_entry * sizeof(struct ipa_rt_rule_del); + param = memdup_user((const void __user *)arg, pyld_sz); + if (IS_ERR(param)) { + retval = PTR_ERR(param); + break; + } + /* add check in case user-space module compromised */ + if (unlikely(((struct ipa_ioc_del_rt_rule *)param)->num_hdls + != pre_entry)) { + IPAERR_RL("current %d pre %d\n", + ((struct ipa_ioc_del_rt_rule *)param)->num_hdls, + pre_entry); + retval = -EFAULT; + break; + } + if (ipa3_del_rt_rule((struct ipa_ioc_del_rt_rule *)param)) { + retval = -EFAULT; + break; + } + if (copy_to_user((void __user *)arg, param, pyld_sz)) { + retval = -EFAULT; + break; + } + break; + + case IPA_IOC_ADD_FLT_RULE: + if (copy_from_user(header, (const void __user *)arg, + sizeof(struct ipa_ioc_add_flt_rule))) { + retval = -EFAULT; + break; + } + pre_entry = + ((struct ipa_ioc_add_flt_rule *)header)->num_rules; + pyld_sz = + sizeof(struct ipa_ioc_add_flt_rule) + + pre_entry * sizeof(struct ipa_flt_rule_add); + param = memdup_user((const void __user *)arg, pyld_sz); + if (IS_ERR(param)) { + retval = PTR_ERR(param); + break; + } + /* add check in case user-space module compromised */ + if (unlikely(((struct ipa_ioc_add_flt_rule *)param)->num_rules + != pre_entry)) { + IPAERR_RL("current %d pre %d\n", + ((struct ipa_ioc_add_flt_rule *)param)-> + num_rules, + pre_entry); + retval = -EFAULT; + break; + } + if (ipa3_add_flt_rule_usr((struct ipa_ioc_add_flt_rule *)param, + true)) { + retval = -EFAULT; + break; + } + if (copy_to_user((void __user *)arg, param, pyld_sz)) { + retval = -EFAULT; + break; + } + break; + + case IPA_IOC_ADD_FLT_RULE_AFTER: + if (copy_from_user(header, (const void __user *)arg, + sizeof(struct ipa_ioc_add_flt_rule_after))) { + + retval = -EFAULT; + break; + } + pre_entry = + ((struct ipa_ioc_add_flt_rule_after *)header)-> + num_rules; + pyld_sz = + sizeof(struct ipa_ioc_add_flt_rule_after) + + pre_entry * sizeof(struct ipa_flt_rule_add); + param = memdup_user((const void __user *)arg, pyld_sz); + if (IS_ERR(param)) { + retval = PTR_ERR(param); + break; + } + /* add check in case user-space module compromised */ + if (unlikely(((struct ipa_ioc_add_flt_rule_after *)param)-> + num_rules != pre_entry)) { + IPAERR_RL("current %d pre %d\n", + ((struct ipa_ioc_add_flt_rule_after *)param)-> + num_rules, + pre_entry); + retval = -EFAULT; + break; + } + if (ipa3_add_flt_rule_after( + (struct ipa_ioc_add_flt_rule_after *)param)) { + retval = -EFAULT; + break; + } + if (copy_to_user((void __user *)arg, param, pyld_sz)) { + retval = -EFAULT; + break; + } + break; + + case IPA_IOC_DEL_FLT_RULE: + if (copy_from_user(header, (const void __user *)arg, + sizeof(struct ipa_ioc_del_flt_rule))) { + retval = -EFAULT; + break; + } + pre_entry = + ((struct ipa_ioc_del_flt_rule *)header)->num_hdls; + pyld_sz = + sizeof(struct ipa_ioc_del_flt_rule) + + pre_entry * sizeof(struct ipa_flt_rule_del); + param = memdup_user((const void __user *)arg, pyld_sz); + if (IS_ERR(param)) { + retval = PTR_ERR(param); + break; + } + /* add check in case user-space module compromised */ + if (unlikely(((struct ipa_ioc_del_flt_rule *)param)->num_hdls + != pre_entry)) { + IPAERR_RL("current %d pre %d\n", + ((struct ipa_ioc_del_flt_rule *)param)-> + num_hdls, + pre_entry); + retval = -EFAULT; + break; + } + if (ipa3_del_flt_rule((struct ipa_ioc_del_flt_rule *)param)) { + retval = -EFAULT; + break; + } + if (copy_to_user((void __user *)arg, param, pyld_sz)) { + retval = -EFAULT; + break; + } + break; + + case IPA_IOC_MDFY_FLT_RULE: + if (copy_from_user(header, (const void __user *)arg, + sizeof(struct ipa_ioc_mdfy_flt_rule))) { + retval = -EFAULT; + break; + } + pre_entry = + ((struct ipa_ioc_mdfy_flt_rule *)header)->num_rules; + pyld_sz = + sizeof(struct ipa_ioc_mdfy_flt_rule) + + pre_entry * sizeof(struct ipa_flt_rule_mdfy); + param = memdup_user((const void __user *)arg, pyld_sz); + if (IS_ERR(param)) { + retval = PTR_ERR(param); + break; + } + /* add check in case user-space module compromised */ + if (unlikely(((struct ipa_ioc_mdfy_flt_rule *)param)->num_rules + != pre_entry)) { + IPAERR_RL("current %d pre %d\n", + ((struct ipa_ioc_mdfy_flt_rule *)param)-> + num_rules, + pre_entry); + retval = -EFAULT; + break; + } + if (ipa3_mdfy_flt_rule((struct ipa_ioc_mdfy_flt_rule *)param)) { + retval = -EFAULT; + break; + } + if (copy_to_user((void __user *)arg, param, pyld_sz)) { + retval = -EFAULT; + break; + } + break; + + case IPA_IOC_COMMIT_HDR: + retval = ipa3_commit_hdr(); + break; + case IPA_IOC_RESET_HDR: + retval = ipa3_reset_hdr(false); + break; + case IPA_IOC_COMMIT_RT: + retval = ipa3_commit_rt(arg); + break; + case IPA_IOC_RESET_RT: + retval = ipa3_reset_rt(arg, false); + break; + case IPA_IOC_COMMIT_FLT: + retval = ipa3_commit_flt(arg); + break; + case IPA_IOC_RESET_FLT: + retval = ipa3_reset_flt(arg, false); + break; + case IPA_IOC_GET_RT_TBL: + if (copy_from_user(header, (const void __user *)arg, + sizeof(struct ipa_ioc_get_rt_tbl))) { + retval = -EFAULT; + break; + } + if (ipa3_get_rt_tbl((struct ipa_ioc_get_rt_tbl *)header)) { + retval = -EFAULT; + break; + } + if (copy_to_user((void __user *)arg, header, + sizeof(struct ipa_ioc_get_rt_tbl))) { + retval = -EFAULT; + break; + } + break; + case IPA_IOC_PUT_RT_TBL: + retval = ipa_put_rt_tbl(arg); + break; + case IPA_IOC_GET_HDR: + if (copy_from_user(header, (const void __user *)arg, + sizeof(struct ipa_ioc_get_hdr))) { + retval = -EFAULT; + break; + } + if (ipa_get_hdr((struct ipa_ioc_get_hdr *)header)) { + retval = -EFAULT; + break; + } + if (copy_to_user((void __user *)arg, header, + sizeof(struct ipa_ioc_get_hdr))) { + retval = -EFAULT; + break; + } + break; + case IPA_IOC_PUT_HDR: + retval = ipa3_put_hdr(arg); + break; + case IPA_IOC_SET_FLT: + retval = ipa3_cfg_filter(arg); + break; + case IPA_IOC_COPY_HDR: + if (copy_from_user(header, (const void __user *)arg, + sizeof(struct ipa_ioc_copy_hdr))) { + retval = -EFAULT; + break; + } + if (ipa3_copy_hdr((struct ipa_ioc_copy_hdr *)header)) { + retval = -EFAULT; + break; + } + if (copy_to_user((void __user *)arg, header, + sizeof(struct ipa_ioc_copy_hdr))) { + retval = -EFAULT; + break; + } + break; + case IPA_IOC_QUERY_INTF: + if (copy_from_user(header, (const void __user *)arg, + sizeof(struct ipa_ioc_query_intf))) { + retval = -EFAULT; + break; + } + if (ipa3_query_intf((struct ipa_ioc_query_intf *)header)) { + retval = -1; + break; + } + if (copy_to_user((void __user *)arg, header, + sizeof(struct ipa_ioc_query_intf))) { + retval = -EFAULT; + break; + } + break; + case IPA_IOC_QUERY_INTF_TX_PROPS: + sz = sizeof(struct ipa_ioc_query_intf_tx_props); + if (copy_from_user(header, (const void __user *)arg, sz)) { + retval = -EFAULT; + break; + } + + if (((struct ipa_ioc_query_intf_tx_props *)header)->num_tx_props + > IPA_NUM_PROPS_MAX) { + retval = -EFAULT; + break; + } + pre_entry = + ((struct ipa_ioc_query_intf_tx_props *) + header)->num_tx_props; + pyld_sz = sz + pre_entry * + sizeof(struct ipa_ioc_tx_intf_prop); + param = memdup_user((const void __user *)arg, pyld_sz); + if (IS_ERR(param)) { + retval = PTR_ERR(param); + break; + } + /* add check in case user-space module compromised */ + if (unlikely(((struct ipa_ioc_query_intf_tx_props *) + param)->num_tx_props + != pre_entry)) { + IPAERR_RL("current %d pre %d\n", + ((struct ipa_ioc_query_intf_tx_props *) + param)->num_tx_props, pre_entry); + retval = -EFAULT; + break; + } + if (ipa3_query_intf_tx_props( + (struct ipa_ioc_query_intf_tx_props *)param)) { + retval = -1; + break; + } + if (copy_to_user((void __user *)arg, param, pyld_sz)) { + retval = -EFAULT; + break; + } + break; + case IPA_IOC_QUERY_INTF_RX_PROPS: + sz = sizeof(struct ipa_ioc_query_intf_rx_props); + if (copy_from_user(header, (const void __user *)arg, sz)) { + retval = -EFAULT; + break; + } + + if (((struct ipa_ioc_query_intf_rx_props *)header)->num_rx_props + > IPA_NUM_PROPS_MAX) { + retval = -EFAULT; + break; + } + pre_entry = + ((struct ipa_ioc_query_intf_rx_props *) + header)->num_rx_props; + pyld_sz = sz + pre_entry * + sizeof(struct ipa_ioc_rx_intf_prop); + param = memdup_user((const void __user *)arg, pyld_sz); + if (IS_ERR(param)) { + retval = PTR_ERR(param); + break; + } + /* add check in case user-space module compromised */ + if (unlikely(((struct ipa_ioc_query_intf_rx_props *) + param)->num_rx_props != pre_entry)) { + IPAERR_RL("current %d pre %d\n", + ((struct ipa_ioc_query_intf_rx_props *) + param)->num_rx_props, pre_entry); + retval = -EFAULT; + break; + } + if (ipa3_query_intf_rx_props( + (struct ipa_ioc_query_intf_rx_props *)param)) { + retval = -1; + break; + } + if (copy_to_user((void __user *)arg, param, pyld_sz)) { + retval = -EFAULT; + break; + } + break; + case IPA_IOC_QUERY_INTF_EXT_PROPS: + sz = sizeof(struct ipa_ioc_query_intf_ext_props); + if (copy_from_user(header, (const void __user *)arg, sz)) { + retval = -EFAULT; + break; + } + + if (((struct ipa_ioc_query_intf_ext_props *) + header)->num_ext_props > IPA_NUM_PROPS_MAX) { + retval = -EFAULT; + break; + } + pre_entry = + ((struct ipa_ioc_query_intf_ext_props *) + header)->num_ext_props; + pyld_sz = sz + pre_entry * + sizeof(struct ipa_ioc_ext_intf_prop); + param = memdup_user((const void __user *)arg, pyld_sz); + if (IS_ERR(param)) { + retval = PTR_ERR(param); + break; + } + /* add check in case user-space module compromised */ + if (unlikely(((struct ipa_ioc_query_intf_ext_props *) + param)->num_ext_props != pre_entry)) { + IPAERR_RL("current %d pre %d\n", + ((struct ipa_ioc_query_intf_ext_props *) + param)->num_ext_props, pre_entry); + retval = -EFAULT; + break; + } + if (ipa3_query_intf_ext_props( + (struct ipa_ioc_query_intf_ext_props *)param)) { + retval = -1; + break; + } + if (copy_to_user((void __user *)arg, param, pyld_sz)) { + retval = -EFAULT; + break; + } + break; + case IPA_IOC_PULL_MSG: + if (copy_from_user(header, (const void __user *)arg, + sizeof(struct ipa_msg_meta))) { + retval = -EFAULT; + break; + } + pre_entry = + ((struct ipa_msg_meta *)header)->msg_len; + pyld_sz = sizeof(struct ipa_msg_meta) + + pre_entry; + param = memdup_user((const void __user *)arg, pyld_sz); + if (IS_ERR(param)) { + retval = PTR_ERR(param); + break; + } + /* add check in case user-space module compromised */ + if (unlikely(((struct ipa_msg_meta *)param)->msg_len + != pre_entry)) { + IPAERR_RL("current %d pre %d\n", + ((struct ipa_msg_meta *)param)->msg_len, + pre_entry); + retval = -EFAULT; + break; + } + if (ipa3_pull_msg((struct ipa_msg_meta *)param, + (char *)param + sizeof(struct ipa_msg_meta), + ((struct ipa_msg_meta *)param)->msg_len) != + ((struct ipa_msg_meta *)param)->msg_len) { + retval = -1; + break; + } + if (copy_to_user((void __user *)arg, param, pyld_sz)) { + retval = -EFAULT; + break; + } + break; + case IPA_IOC_RM_ADD_DEPENDENCY: + /* IPA RM is deprecate because IPA PM is used */ + IPAERR("using obselete command: IPA_IOC_RM_ADD_DEPENDENCY"); + retval = -EINVAL; + break; + + case IPA_IOC_RM_DEL_DEPENDENCY: + /* IPA RM is deprecate because IPA PM is used */ + IPAERR("using obselete command: IPA_IOC_RM_DEL_DEPENDENCY"); + retval = -EINVAL; + break; + + case IPA_IOC_GENERATE_FLT_EQ: + { + struct ipa_ioc_generate_flt_eq flt_eq; + + if (copy_from_user(&flt_eq, (const void __user *)arg, + sizeof(struct ipa_ioc_generate_flt_eq))) { + retval = -EFAULT; + break; + } + if (ipahal_flt_generate_equation(flt_eq.ip, + &flt_eq.attrib, &flt_eq.eq_attrib)) { + retval = -EFAULT; + break; + } + if (copy_to_user((void __user *)arg, &flt_eq, + sizeof(struct ipa_ioc_generate_flt_eq))) { + retval = -EFAULT; + break; + } + break; + } + case IPA_IOC_QUERY_EP_MAPPING: + { + retval = ipa_get_ep_mapping(arg); + break; + } + case IPA_IOC_QUERY_RT_TBL_INDEX: + if (copy_from_user(header, (const void __user *)arg, + sizeof(struct ipa_ioc_get_rt_tbl_indx))) { + retval = -EFAULT; + break; + } + if (ipa3_query_rt_index( + (struct ipa_ioc_get_rt_tbl_indx *)header)) { + retval = -EFAULT; + break; + } + if (copy_to_user((void __user *)arg, header, + sizeof(struct ipa_ioc_get_rt_tbl_indx))) { + retval = -EFAULT; + break; + } + break; + case IPA_IOC_WRITE_QMAPID: + if (copy_from_user(header, (const void __user *)arg, + sizeof(struct ipa_ioc_write_qmapid))) { + retval = -EFAULT; + break; + } + if (ipa3_write_qmap_id((struct ipa_ioc_write_qmapid *)header)) { + retval = -EFAULT; + break; + } + if (copy_to_user((void __user *)arg, header, + sizeof(struct ipa_ioc_write_qmapid))) { + retval = -EFAULT; + break; + } + break; + case IPA_IOC_NOTIFY_WAN_UPSTREAM_ROUTE_ADD: + retval = ipa3_send_wan_msg(arg, WAN_UPSTREAM_ROUTE_ADD, true); + if (retval) { + IPAERR("ipa3_send_wan_msg failed: %d\n", retval); + break; + } + break; + case IPA_IOC_NOTIFY_WAN_UPSTREAM_ROUTE_DEL: + retval = ipa3_send_wan_msg(arg, WAN_UPSTREAM_ROUTE_DEL, true); + if (retval) { + IPAERR("ipa3_send_wan_msg failed: %d\n", retval); + break; + } + break; + case IPA_IOC_NOTIFY_WAN_EMBMS_CONNECTED: + retval = ipa3_send_wan_msg(arg, WAN_EMBMS_CONNECT, false); + if (retval) { + IPAERR("ipa3_send_wan_msg failed: %d\n", retval); + break; + } + break; + case IPA_IOC_ADD_HDR_PROC_CTX: + if (copy_from_user(header, (const void __user *)arg, + sizeof(struct ipa_ioc_add_hdr_proc_ctx))) { + retval = -EFAULT; + break; + } + pre_entry = + ((struct ipa_ioc_add_hdr_proc_ctx *) + header)->num_proc_ctxs; + pyld_sz = + sizeof(struct ipa_ioc_add_hdr_proc_ctx) + + pre_entry * sizeof(struct ipa_hdr_proc_ctx_add); + param = memdup_user((const void __user *)arg, pyld_sz); + if (IS_ERR(param)) { + retval = PTR_ERR(param); + break; + } + /* add check in case user-space module compromised */ + if (unlikely(((struct ipa_ioc_add_hdr_proc_ctx *) + param)->num_proc_ctxs != pre_entry)) { + IPAERR_RL("current %d pre %d\n", + ((struct ipa_ioc_add_hdr_proc_ctx *) + param)->num_proc_ctxs, pre_entry); + retval = -EFAULT; + break; + } + if (ipa3_add_hdr_proc_ctx( + (struct ipa_ioc_add_hdr_proc_ctx *)param, true)) { + retval = -EFAULT; + break; + } + if (copy_to_user((void __user *)arg, param, pyld_sz)) { + retval = -EFAULT; + break; + } + break; + case IPA_IOC_DEL_HDR_PROC_CTX: + if (copy_from_user(header, (const void __user *)arg, + sizeof(struct ipa_ioc_del_hdr_proc_ctx))) { + retval = -EFAULT; + break; + } + pre_entry = + ((struct ipa_ioc_del_hdr_proc_ctx *)header)->num_hdls; + pyld_sz = + sizeof(struct ipa_ioc_del_hdr_proc_ctx) + + pre_entry * sizeof(struct ipa_hdr_proc_ctx_del); + param = memdup_user((const void __user *)arg, pyld_sz); + if (IS_ERR(param)) { + retval = PTR_ERR(param); + break; + } + /* add check in case user-space module compromised */ + if (unlikely(((struct ipa_ioc_del_hdr_proc_ctx *) + param)->num_hdls != pre_entry)) { + IPAERR_RL("current %d pre %d\n", + ((struct ipa_ioc_del_hdr_proc_ctx *)param)-> + num_hdls, + pre_entry); + retval = -EFAULT; + break; + } + if (ipa3_del_hdr_proc_ctx_by_user( + (struct ipa_ioc_del_hdr_proc_ctx *)param, true)) { + retval = -EFAULT; + break; + } + if (copy_to_user((void __user *)arg, param, pyld_sz)) { + retval = -EFAULT; + break; + } + break; + + case IPA_IOC_GET_HW_VERSION: + pyld_sz = sizeof(enum ipa_hw_type); + param = kmemdup(&ipa3_ctx->ipa_hw_type, pyld_sz, GFP_KERNEL); + if (!param) { + retval = -ENOMEM; + break; + } + if (copy_to_user((void __user *)arg, param, pyld_sz)) { + retval = -EFAULT; + break; + } + break; + + case IPA_IOC_GET_VLAN_MODE: + if (copy_from_user(&vlan_mode, (const void __user *)arg, + sizeof(struct ipa_ioc_get_vlan_mode))) { + retval = -EFAULT; + break; + } + retval = ipa_is_vlan_mode( + vlan_mode.iface, + &is_vlan_mode); + if (retval) + break; + + vlan_mode.is_vlan_mode = is_vlan_mode; + + if (copy_to_user((void __user *)arg, + &vlan_mode, + sizeof(struct ipa_ioc_get_vlan_mode))) { + retval = -EFAULT; + break; + } + break; + + case IPA_IOC_ADD_VLAN_IFACE: + if (ipa3_send_vlan_l2tp_msg(arg, ADD_VLAN_IFACE)) { + retval = -EFAULT; + break; + } + break; + + case IPA_IOC_DEL_VLAN_IFACE: + if (ipa3_send_vlan_l2tp_msg(arg, DEL_VLAN_IFACE)) { + retval = -EFAULT; + break; + } + break; + case IPA_IOC_ADD_BRIDGE_VLAN_MAPPING: + if (ipa3_send_vlan_l2tp_msg(arg, ADD_BRIDGE_VLAN_MAPPING)) { + retval = -EFAULT; + break; + } + break; + case IPA_IOC_DEL_BRIDGE_VLAN_MAPPING: + if (ipa3_send_vlan_l2tp_msg(arg, DEL_BRIDGE_VLAN_MAPPING)) { + retval = -EFAULT; + break; + } + break; + case IPA_IOC_ADD_L2TP_VLAN_MAPPING: + if (ipa3_send_vlan_l2tp_msg(arg, ADD_L2TP_VLAN_MAPPING)) { + retval = -EFAULT; + break; + } + break; + + case IPA_IOC_DEL_L2TP_VLAN_MAPPING: + if (ipa3_send_vlan_l2tp_msg(arg, DEL_L2TP_VLAN_MAPPING)) { + retval = -EFAULT; + break; + } + break; + + case IPA_IOC_CLEANUP: + /*Route and filter rules will also be clean*/ + IPADBG("Got IPA_IOC_CLEANUP\n"); + retval = ipa3_reset_hdr(true); + memset(&nat_del, 0, sizeof(nat_del)); + nat_del.table_index = 0; + retval = ipa3_nat_del_cmd(&nat_del); + if (ipa3_ctx->platform_type == IPA_PLAT_TYPE_APQ) + retval = ipa3_clean_mhip_dl_rule(); + else + retval = ipa3_clean_modem_rule(); + ipa3_counter_id_remove_all(); + break; + + case IPA_IOC_QUERY_WLAN_CLIENT: + IPADBG("Got IPA_IOC_QUERY_WLAN_CLIENT\n"); + retval = ipa3_resend_wlan_msg(); + break; + + case IPA_IOC_GSB_CONNECT: + IPADBG("Got IPA_IOC_GSB_CONNECT\n"); + if (ipa3_send_gsb_msg(arg, IPA_GSB_CONNECT)) { + retval = -EFAULT; + break; + } + break; + + case IPA_IOC_GSB_DISCONNECT: + IPADBG("Got IPA_IOC_GSB_DISCONNECT\n"); + if (ipa3_send_gsb_msg(arg, IPA_GSB_DISCONNECT)) { + retval = -EFAULT; + break; + } + break; + + case IPA_IOC_ADD_RT_RULE_V2: + retval = ipa3_ioctl_add_rt_rule_v2(arg); + break; + + case IPA_IOC_ADD_RT_RULE_EXT_V2: + retval = ipa3_ioctl_add_rt_rule_ext_v2(arg); + break; + + case IPA_IOC_ADD_RT_RULE_AFTER_V2: + retval = ipa3_ioctl_add_rt_rule_after_v2(arg); + break; + + case IPA_IOC_MDFY_RT_RULE_V2: + retval = ipa3_ioctl_mdfy_rt_rule_v2(arg); + break; + + case IPA_IOC_ADD_FLT_RULE_V2: + retval = ipa3_ioctl_add_flt_rule_v2(arg); + break; + + case IPA_IOC_ADD_FLT_RULE_AFTER_V2: + retval = ipa3_ioctl_add_flt_rule_after_v2(arg); + break; + + case IPA_IOC_MDFY_FLT_RULE_V2: + retval = ipa3_ioctl_mdfy_flt_rule_v2(arg); + break; + + case IPA_IOC_FNR_COUNTER_ALLOC: + if (ipa3_ctx->ipa_hw_type < IPA_HW_v4_5) { + IPAERR("FNR stats not supported on IPA ver %d", + ipa3_ctx->ipa_hw_type); + retval = -EFAULT; + break; + } + retval = ipa3_ioctl_fnr_counter_alloc(arg); + break; + + case IPA_IOC_FNR_COUNTER_DEALLOC: + if (ipa3_ctx->ipa_hw_type < IPA_HW_v4_5) { + IPAERR("FNR stats not supported on IPA ver %d", + ipa3_ctx->ipa_hw_type); + retval = -EFAULT; + break; + } + hdl = (int)arg; + if (hdl < 0) { + IPAERR("IPA_FNR_COUNTER_DEALLOC failed: hdl %d\n", + hdl); + retval = -EPERM; + break; + } + ipa3_counter_remove_hdl(hdl); + break; + + case IPA_IOC_FNR_COUNTER_QUERY: + if (ipa3_ctx->ipa_hw_type < IPA_HW_v4_5) { + IPAERR("FNR stats not supported on IPA ver %d", + ipa3_ctx->ipa_hw_type); + retval = -EFAULT; + break; + } + retval = ipa3_ioctl_fnr_counter_query(arg); + break; + + case IPA_IOC_SET_FNR_COUNTER_INFO: + if (ipa3_ctx->ipa_hw_type < IPA_HW_v4_5) { + IPAERR("FNR stats not supported on IPA ver %d", + ipa3_ctx->ipa_hw_type); + retval = -EFAULT; + break; + } + retval = ipa3_ioctl_fnr_counter_set(arg); + break; + + case IPA_IOC_WIGIG_FST_SWITCH: + IPADBG("Got IPA_IOCTL_WIGIG_FST_SWITCH\n"); + if (copy_from_user(&fst_switch, (const void __user *)arg, + sizeof(struct ipa_ioc_wigig_fst_switch))) { + retval = -EFAULT; + break; + } + + /* null terminate the string */ + fst_switch.netdev_name[IPA_RESOURCE_NAME_MAX - 1] = '\0'; + + retval = ipa_wigig_send_msg(WIGIG_FST_SWITCH, + fst_switch.netdev_name, + fst_switch.client_mac_addr, + IPA_CLIENT_MAX, + fst_switch.to_wigig); + break; + + case IPA_IOC_GET_NAT_IN_SRAM_INFO: + retval = proc_sram_info_rqst(arg); + break; + + case IPA_IOC_APP_CLOCK_VOTE: + retval = ipa3_app_clk_vote( + (enum ipa_app_clock_vote_type) arg); + break; + + case IPA_IOC_PDN_CONFIG: + if (ipa3_send_pdn_config_msg(arg)) { + retval = -EFAULT; + break; + } + break; + + case IPA_IOC_SET_MAC_FLT: + IPADBG("Got IPA_IOC_SET_MAC_FLT\n"); + if (ipa3_send_mac_flt_list(arg)) { + retval = -EFAULT; + break; + } + break; + + case IPA_IOC_SET_SW_FLT: + IPADBG("Got IPA_IOC_SET_SW_FLT\n"); + if (ipa3_send_sw_flt_list(arg)) { + retval = -EFAULT; + break; + } + break; + + case IPA_IOC_SET_IPPT_SW_FLT: + IPADBG("Got IPA_IOC_SET_IPPT_SW_FLT\n"); + if (ipa3_send_ippt_sw_flt_list(arg)) { + retval = -EFAULT; + break; + } + break; + + case IPA_IOC_GET_PHERIPHERAL_EP_INFO: + IPADBG("Got IPA_IOC_GET_EP_INFO\n"); + /* used in IPA4.X AUTO and IPA5.0 MDM onwards */ + if (copy_from_user(&ep_info, (const void __user *)arg, + sizeof(struct ipa_ioc_get_ep_info))) { + IPAERR_RL("copy_from_user fails\n"); + retval = -EFAULT; + break; + } + + if (ep_info.max_ep_pairs != QUERY_MAX_EP_PAIRS) { + IPAERR_RL("unexpected max_ep_pairs %d\n", + ep_info.max_ep_pairs); + retval = -EFAULT; + break; + } + + if (ep_info.ep_pair_size != + (QUERY_MAX_EP_PAIRS * sizeof(struct ipa_ep_pair_info))) { + IPAERR_RL("unexpected ep_pair_size %d\n", + ep_info.max_ep_pairs); + retval = -EFAULT; + break; + } + + uptr = ep_info.info; + if (unlikely(!uptr)) { + IPAERR_RL("unexpected NULL info\n"); + retval = -EFAULT; + break; + } + + param = kzalloc(ep_info.ep_pair_size, GFP_KERNEL); + if (!param) { + IPAERR_RL("kzalloc fails\n"); + retval = -ENOMEM; + break; + } + + retval = ipa3_get_ep_info(&ep_info, param); + if (retval < 0) { + IPAERR("ipa3_get_ep_info failed\n"); + retval = -EFAULT; + break; + } + + if (copy_to_user((void __user *)uptr, param, + ep_info.ep_pair_size)) { + IPAERR_RL("copy_to_user fails\n"); + retval = -EFAULT; + break; + } + + if (copy_to_user((void __user *)arg, &ep_info, + sizeof(struct ipa_ioc_get_ep_info))) { + IPAERR_RL("copy_to_user fails\n"); + retval = -EFAULT; + break; + } + break; + + case IPA_IOC_SET_PKT_THRESHOLD: + IPADBG("Got IPA_IOC_SET_PKT_THRESHOLD\n"); + if (ipa3_send_pkt_threshold(arg)) + retval = -EFAULT; + break; + + case IPA_IOC_ADD_EoGRE_MAPPING: + IPADBG("Got IPA_IOC_ADD_EoGRE_MAPPING\n"); + if (copy_from_user( + &eogre_info, + (const void __user *) arg, + sizeof(struct ipa_ioc_eogre_info))) { + IPAERR_RL("copy_from_user fails\n"); + retval = -EFAULT; + break; + } + + retval = ipa3_check_eogre(&eogre_info, &send2uC, &send2ipacm); + + ipa3_ctx->eogre_enabled = (retval == 0); + + if (retval == 0 && send2uC == true) { + /* + * Send map to uC... + */ + retval = ipa3_add_dscp_vlan_pcp_map( + &eogre_info.map_info); + } + + if (retval == 0 && send2ipacm == true) { + /* + * Send ip addrs to ipacm... + */ + retval = ipa3_send_eogre_info(IPA_EoGRE_UP_EVENT, &eogre_info); + } + + if (retval != 0) { + ipa3_ctx->eogre_enabled = false; + } + + break; + + case IPA_IOC_DEL_EoGRE_MAPPING: + IPADBG("Got IPA_IOC_DEL_EoGRE_MAPPING\n"); + + memset(&eogre_info, 0, sizeof(eogre_info)); + + retval = ipa3_check_eogre(&eogre_info, &send2uC, &send2ipacm); + + if (retval == 0 && send2uC == true) { + /* + * Send map clear to uC... + */ + retval = ipa3_add_dscp_vlan_pcp_map( + &eogre_info.map_info); + } + + if (retval == 0 && send2ipacm == true) { + /* + * Send null ip addrs to ipacm... + */ + retval = ipa3_send_eogre_info(IPA_EoGRE_DOWN_EVENT, &eogre_info); + } + + if (retval == 0) { + ipa3_ctx->eogre_enabled = false; + } + + break; +#ifdef IPA_IOC_FLT_MEM_PERIPHERAL_SET_PRIO_HIGH + case IPA_IOC_FLT_MEM_PERIPHERAL_SET_PRIO_HIGH: + retval = ipa_flt_sram_set_client_prio_high((enum ipa_client_type) arg); + if (retval) + IPAERR("ipa_flt_sram_set_client_prio_high failed! retval=%d\n", retval); + break; +#endif + + case IPA_IOC_ADD_MACSEC_MAPPING: + case IPA_IOC_DEL_MACSEC_MAPPING: + IPADBG("Got %s\n", cmd == IPA_IOC_ADD_MACSEC_MAPPING ? + "IPA_IOC_ADD_MACSEC_MAPPING" : "IPA_IOC_DEL_MACSEC_MAPPING"); + if (copy_from_user(&macsec_info, (const void __user *) arg, + sizeof(struct ipa_ioc_macsec_info))) { + IPAERR_RL("copy_from_user for ipa_ioc_macsec_info fails\n"); + retval = -EFAULT; + break; + } + + /* Validate the input */ + if (macsec_info.ioctl_data_size != sizeof(struct ipa_macsec_map)) { + IPAERR_RL("data size missmatch\n"); + retval = -EFAULT; + break; + } + + macsec_map = kzalloc(sizeof(struct ipa_macsec_map), GFP_KERNEL); + if (!macsec_map) { + IPAERR("macsec_map memory allocation failed !\n"); + retval = -ENOMEM; + break; + } + + if (copy_from_user(macsec_map, (const void __user *)(macsec_info.ioctl_ptr), + sizeof(struct ipa_macsec_map))) { + IPAERR_RL("copy_from_user for ipa_macsec_map fails\n"); + retval = -EFAULT; + kfree(macsec_map); + break; + } + + /* Send message to the IPACM */ + ipa3_send_macsec_info( + (cmd == IPA_IOC_ADD_MACSEC_MAPPING) ? + IPA_MACSEC_ADD_EVENT : IPA_MACSEC_DEL_EVENT, + macsec_map); + break; + + case IPA_IOC_SET_NAT_EXC_RT_TBL_IDX: + retval = ipa3_set_nat_conn_track_exc_rt_tbl(arg, IPA_IP_v4); + break; + + case IPA_IOC_SET_CONN_TRACK_EXC_RT_TBL_IDX: + retval = ipa3_set_nat_conn_track_exc_rt_tbl(arg, IPA_IP_v6); + break; +#if defined(CONFIG_IPA_TSP) + case IPA_IOC_TSP_GET_INGR_TC_NUM: + u32temp = (u32)ipa3_ctx->tsp.ingr_tc_max; + goto send; + case IPA_IOC_TSP_GET_EGR_EP_NUM: + u32temp = (u32)ipa3_ctx->tsp.egr_ep_max; + goto send; + case IPA_IOC_TSP_GET_EGR_TC_NUM: + u32temp = (u32)ipa3_ctx->tsp.egr_tc_max; +send: + if (copy_to_user((void __user *)arg, &u32temp, sizeof(u32temp))) { + retval = -EFAULT; + break; + } + break; + + case IPA_IOC_TSP_GET_INGR_TC: + if (copy_from_user(&ingr_tc_get, (const void __user *)arg, + sizeof(struct ipa_ioc_tsp_ingress_class_get))) { + retval = -EFAULT; + break; + } + + if (ingr_tc_get.index == 0 || ingr_tc_get.index > (u32)ipa3_ctx->tsp.ingr_tc_max) { + retval = -EINVAL; + break; + } + + retval = ipa_tsp_get_ingr_tc(ingr_tc_get.index, &(ingr_tc_get.params)); + if (retval != 0) + break; + + if (copy_to_user((void __user *)arg, &ingr_tc_get, + sizeof(struct ipa_ioc_tsp_ingress_class_get))) { + retval = -EFAULT; + break; + } + break; + + case IPA_IOC_TSP_GET_EGR_EP: + if (copy_from_user(&egr_ep_get, (const void __user *)arg, + sizeof(struct ipa_ioc_tsp_egress_prod_get))) { + retval = -EFAULT; + break; + } + + if (egr_ep_get.index >= (u32)ipa3_ctx->tsp.egr_ep_max) { + retval = -EINVAL; + break; + } + + retval = ipa_tsp_get_egr_ep(egr_ep_get.index, &(egr_ep_get.params)); + if (retval != 0) + break; + + if (copy_to_user((void __user *)arg, &egr_ep_get, + sizeof(struct ipa_ioc_tsp_egress_prod_get))) { + retval = -EFAULT; + break; + } + break; + + case IPA_IOC_TSP_GET_EGR_TC: + if (copy_from_user(&egr_tc_get, (const void __user *)arg, + sizeof(struct ipa_ioc_tsp_egress_class_get))) { + retval = -EFAULT; + break; + } + + if (egr_tc_get.index == 0 || egr_tc_get.index > (u32)ipa3_ctx->tsp.egr_tc_max) { + retval = -EINVAL; + break; + } + + retval = ipa_tsp_get_egr_tc(egr_tc_get.index, &(egr_tc_get.params)); + if (retval != 0) + break; + + if (copy_to_user((void __user *)arg, &egr_tc_get, + sizeof(struct ipa_ioc_tsp_egress_class_get))) { + retval = -EFAULT; + break; + } + break; + + case IPA_IOC_TSP_SET_INGR_TC: + if (copy_from_user(&ingr_tc_set, (const void __user *)arg, + sizeof(struct ipa_ioc_tsp_ingress_class_set))) { + retval = -EFAULT; + break; + } + + if (ingr_tc_set.index == 0 || ingr_tc_set.index > (u32)ipa3_ctx->tsp.ingr_tc_max) { + retval = -EINVAL; + break; + } + + retval = ipa_tsp_set_ingr_tc(ingr_tc_set.index, &(ingr_tc_set.params)); + if (retval != 0) + break; + + if (ingr_tc_set.commit) + retval = ipa_tsp_commit(); + + break; + + case IPA_IOC_TSP_SET_EGR_EP: + if (copy_from_user(&egr_ep_set, (const void __user *)arg, + sizeof(struct ipa_ioc_tsp_egress_prod_set))) { + retval = -EFAULT; + break; + } + + if (egr_ep_set.index >= (u32)ipa3_ctx->tsp.egr_ep_max) { + retval = -EINVAL; + break; + } + + retval = ipa_tsp_set_egr_ep(egr_ep_set.index, &(egr_ep_set.params)); + if (retval != 0) + break; + + if (egr_ep_set.commit) + retval = ipa_tsp_commit(); + break; + + case IPA_IOC_TSP_SET_EGR_TC: + if (copy_from_user(&egr_tc_set, (const void __user *)arg, + sizeof(struct ipa_ioc_tsp_egress_class_set))) { + retval = -EFAULT; + break; + } + + if (egr_tc_set.index == 0 || egr_tc_set.index > (u32)ipa3_ctx->tsp.egr_tc_max) { + retval = -EINVAL; + break; + } + + retval = ipa_tsp_set_egr_tc(egr_tc_set.index, &(egr_tc_set.params)); + if (retval != 0) + break; + + if (egr_tc_set.commit) + retval = ipa_tsp_commit(); + + break; + + case IPA_IOC_TSP_COMMIT: + retval = ipa_tsp_commit(); + break; + + case IPA_IOC_TSP_RESET: + retval = ipa_tsp_reset(); + break; +#endif + + default: + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + return -ENOTTY; + } + if (!IS_ERR(param)) + kfree(param); + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + + return retval; +} + +/** + * ipa3_setup_dflt_rt_tables() - Setup default routing tables + * + * Return codes: + * 0: success + * -ENOMEM: failed to allocate memory + * -EPERM: failed to add the tables + */ +int ipa3_setup_dflt_rt_tables(void) +{ + struct ipa_ioc_add_rt_rule *rt_rule; + struct ipa_rt_rule_add *rt_rule_entry; + + rt_rule = + kzalloc(sizeof(struct ipa_ioc_add_rt_rule) + 1 * + sizeof(struct ipa_rt_rule_add), GFP_KERNEL); + if (!rt_rule) + return -ENOMEM; + + /* setup a default v4 route to point to Apps */ + rt_rule->num_rules = 1; + rt_rule->commit = 1; + rt_rule->ip = IPA_IP_v4; + strlcpy(rt_rule->rt_tbl_name, IPA_DFLT_RT_TBL_NAME, + IPA_RESOURCE_NAME_MAX); + + rt_rule_entry = &rt_rule->rules[0]; + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = IPA_CLIENT_APPS_LAN_CONS; + rt_rule_entry->rule.hdr_hdl = ipa3_ctx->excp_hdr_hdl; + rt_rule_entry->rule.retain_hdr = 1; + + if (ipa_add_rt_rule(rt_rule)) { + IPAERR("fail to add dflt v4 rule\n"); + kfree(rt_rule); + return -EPERM; + } + IPADBG("dflt v4 rt rule hdl=%x\n", rt_rule_entry->rt_rule_hdl); + ipa3_ctx->dflt_v4_rt_rule_hdl = rt_rule_entry->rt_rule_hdl; + + /* setup a default v6 route to point to A5 */ + rt_rule->ip = IPA_IP_v6; + if (ipa_add_rt_rule(rt_rule)) { + IPAERR("fail to add dflt v6 rule\n"); + kfree(rt_rule); + return -EPERM; + } + IPADBG("dflt v6 rt rule hdl=%x\n", rt_rule_entry->rt_rule_hdl); + ipa3_ctx->dflt_v6_rt_rule_hdl = rt_rule_entry->rt_rule_hdl; + + /* + * because these tables are the very first to be added, they will both + * have the same index (0) which is essential for programming the + * "route" end-point config + */ + + kfree(rt_rule); + + return 0; +} + +static int ipa3_setup_exception_path(void) +{ + struct ipa_ioc_add_hdr *hdr = NULL; + int ret = 0; + + if ( ! lan_coal_enabled() ) { + + struct ipa_hdr_add *hdr_entry; + struct ipahal_reg_route route = { 0 }; + struct ipa3_hdr_entry *hdr_entry_internal; + + /* install the basic exception header */ + hdr = kzalloc(sizeof(struct ipa_ioc_add_hdr) + 1 * + sizeof(struct ipa_hdr_add), GFP_KERNEL); + if (!hdr) + return -ENOMEM; + + hdr->num_hdrs = 1; + hdr->commit = 1; + hdr_entry = &hdr->hdr[0]; + + strlcpy(hdr_entry->name, IPA_LAN_RX_HDR_NAME, IPA_RESOURCE_NAME_MAX); + hdr_entry->hdr_len = IPA_LAN_RX_HEADER_LENGTH; + + if (ipa_add_hdr(hdr)) { + IPAERR("fail to add exception hdr\n"); + ret = -EPERM; + goto bail; + } + + if (hdr_entry->status) { + IPAERR("fail to add exception hdr\n"); + ret = -EPERM; + goto bail; + } + + hdr_entry_internal = ipa3_id_find(hdr_entry->hdr_hdl); + if (unlikely(!hdr_entry_internal)) { + IPAERR("fail to find internal hdr structure\n"); + ret = -EPERM; + goto bail; + } + + ipa3_ctx->excp_hdr_hdl = hdr_entry->hdr_hdl; + + /* set the route register to pass exception packets to Apps */ + route.route_def_pipe = ipa_get_ep_mapping(IPA_CLIENT_APPS_LAN_CONS); + route.route_frag_def_pipe = ipa_get_ep_mapping( + IPA_CLIENT_APPS_LAN_CONS); + route.route_def_hdr_table = !hdr_entry_internal->is_lcl; + route.route_def_retain_hdr = 1; + + if (ipa3_cfg_route(&route)) { + IPAERR("fail to add exception hdr\n"); + ret = -EPERM; + goto bail; + } + } + +bail: + if ( hdr ) kfree(hdr); + return ret; +} + +static int ipa3_init_smem_region(int memory_region_size, + int memory_region_offset) +{ + struct ipahal_imm_cmd_dma_shared_mem cmd; + struct ipahal_imm_cmd_pyld *cmd_pyld; + struct ipa3_desc desc; + struct ipa_mem_buffer mem; + int rc; + + if (memory_region_size == 0) + return 0; + + memset(&desc, 0, sizeof(desc)); + memset(&cmd, 0, sizeof(cmd)); + memset(&mem, 0, sizeof(mem)); + + mem.size = memory_region_size; + mem.base = dma_alloc_coherent(ipa3_ctx->pdev, mem.size, + &mem.phys_base, GFP_KERNEL); + if (!mem.base) { + IPAERR("failed to alloc DMA buff of size %d\n", mem.size); + return -ENOMEM; + } + + cmd.is_read = false; + cmd.skip_pipeline_clear = false; + cmd.pipeline_clear_options = IPAHAL_HPS_CLEAR; + cmd.size = mem.size; + cmd.system_addr = mem.phys_base; + cmd.local_addr = ipa3_ctx->smem_restricted_bytes + + memory_region_offset; + cmd_pyld = ipahal_construct_imm_cmd( + IPA_IMM_CMD_DMA_SHARED_MEM, &cmd, false); + if (!cmd_pyld) { + IPAERR("failed to construct dma_shared_mem imm cmd\n"); + return -ENOMEM; + } + ipa3_init_imm_cmd_desc(&desc, cmd_pyld); + + rc = ipa3_send_cmd(1, &desc); + if (rc) { + IPAERR("failed to send immediate command (error %d)\n", rc); + rc = -EFAULT; + } + + ipahal_destroy_imm_cmd(cmd_pyld); + dma_free_coherent(ipa3_ctx->pdev, mem.size, mem.base, + mem.phys_base); + + return rc; +} + +/** + * ipa3_init_q6_smem() - Initialize Q6 general memory and + * header memory regions in IPA. + * + * Return codes: + * 0: success + * -ENOMEM: failed to allocate dma memory + * -EFAULT: failed to send IPA command to initialize the memory + */ +int ipa3_init_q6_smem(void) +{ + int rc; + + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + + rc = ipa3_init_smem_region(IPA_MEM_PART(modem_size), + IPA_MEM_PART(modem_ofst)); + if (rc) { + IPAERR("failed to initialize Modem RAM memory\n"); + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + return rc; + } + + rc = ipa3_init_smem_region(IPA_MEM_PART(modem_hdr_size), + IPA_MEM_PART(modem_hdr_ofst)); + if (rc) { + IPAERR("failed to initialize Modem HDRs RAM memory\n"); + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + return rc; + } + + rc = ipa3_init_smem_region(IPA_MEM_PART(modem_hdr_proc_ctx_size), + IPA_MEM_PART(modem_hdr_proc_ctx_ofst)); + if (rc) { + IPAERR("failed to initialize Modem proc ctx RAM memory\n"); + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + return rc; + } + + rc = ipa3_init_smem_region(IPA_MEM_PART(modem_comp_decomp_size), + IPA_MEM_PART(modem_comp_decomp_ofst)); + if (rc) { + IPAERR("failed to initialize Modem Comp/Decomp RAM memory\n"); + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + return rc; + } + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + + return rc; +} + +static void ipa3_destroy_imm(void *user1, int user2) +{ + ipahal_destroy_imm_cmd(user1); +} + +static void ipa3_q6_pipe_flow_control(bool delay) +{ + int ep_idx; + int client_idx; + int code = 0, result; + const struct ipa_gsi_ep_config *gsi_ep_cfg; + + for (client_idx = 0; client_idx < IPA_CLIENT_MAX; client_idx++) { + if (IPA_CLIENT_IS_Q6_PROD(client_idx)) { + ep_idx = ipa_get_ep_mapping(client_idx); + if (ep_idx == -1) + continue; + gsi_ep_cfg = ipa_get_gsi_ep_info(client_idx); + if (!gsi_ep_cfg) { + IPAERR("failed to get GSI config\n"); + ipa_assert(); + return; + } + IPADBG("pipe setting V2 flow control\n"); + /* Configurig primary flow control on Q6 pipes*/ + result = gsi_flow_control_ee( + gsi_ep_cfg->ipa_gsi_chan_num, ep_idx, + gsi_ep_cfg->ee, delay, false, &code); + if (result == GSI_STATUS_SUCCESS) { + IPADBG("sussess gsi ch %d with code %d\n", + gsi_ep_cfg->ipa_gsi_chan_num, code); + } else { + IPADBG("failed gsi ch %d code %d\n", + gsi_ep_cfg->ipa_gsi_chan_num, code); + } + } + } +} + +static void ipa3_q6_pipe_delay(bool delay) +{ + int client_idx; + int ep_idx; + struct ipa_ep_cfg_ctrl ep_ctrl; + + memset(&ep_ctrl, 0, sizeof(struct ipa_ep_cfg_ctrl)); + ep_ctrl.ipa_ep_delay = delay; + + for (client_idx = 0; client_idx < IPA_CLIENT_MAX; client_idx++) { + if (IPA_CLIENT_IS_Q6_PROD(client_idx)) { + ep_idx = ipa_get_ep_mapping(client_idx); + if (ep_idx == -1) + continue; + + ipahal_write_reg_n_fields(IPA_ENDP_INIT_CTRL_n, + ep_idx, &ep_ctrl); + } + } +} + +static void ipa3_q6_avoid_holb(void) +{ + int ep_idx; + int client_idx; + struct ipa_ep_cfg_ctrl ep_suspend; + struct ipa_ep_cfg_holb ep_holb; + + memset(&ep_suspend, 0, sizeof(ep_suspend)); + memset(&ep_holb, 0, sizeof(ep_holb)); + + ep_suspend.ipa_ep_suspend = true; + ep_holb.tmr_val = 0; + ep_holb.en = 1; + + if (ipa3_ctx->ipa_hw_type == IPA_HW_v4_2) + ipa3_cal_ep_holb_scale_base_val(ep_holb.tmr_val, &ep_holb); + + for (client_idx = 0; client_idx < IPA_CLIENT_MAX; client_idx++) { + if (IPA_CLIENT_IS_Q6_CONS(client_idx)) { + ep_idx = ipa_get_ep_mapping(client_idx); + if (ep_idx == -1) + continue; + + /* from IPA 4.0 pipe suspend is not supported */ + if (ipa3_ctx->ipa_hw_type < IPA_HW_v4_0) + ipahal_write_reg_n_fields( + IPA_ENDP_INIT_CTRL_n, + ep_idx, &ep_suspend); + + /* + * ipa3_cfg_ep_holb is not used here because we are + * setting HOLB on Q6 pipes, and from APPS perspective + * they are not valid, therefore, the above function + * will fail. + * Also don't reset the HOLB timer to 0 for Q6 pipes. + */ + + + + ipahal_write_reg_n_fields( + IPA_ENDP_INIT_HOL_BLOCK_EN_n, + ep_idx, &ep_holb); + + /* For targets > IPA_4.0 issue requires HOLB_EN to + * be written twice. + */ + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_0) + ipahal_write_reg_n_fields( + IPA_ENDP_INIT_HOL_BLOCK_EN_n, + ep_idx, &ep_holb); + } + } +} + +static void ipa3_halt_q6_gsi_channels(bool prod) +{ + int ep_idx; + int client_idx; + const struct ipa_gsi_ep_config *gsi_ep_cfg; + int i; + int ret; + int code = 0; + + /* if prod flag is true, then we halt the producer channels also */ + for (client_idx = 0; client_idx < IPA_CLIENT_MAX; client_idx++) { + if (IPA_CLIENT_IS_Q6_CONS(client_idx) + || (IPA_CLIENT_IS_Q6_PROD(client_idx) && prod)) { + ep_idx = ipa_get_ep_mapping(client_idx); + if (ep_idx == -1) + continue; + + gsi_ep_cfg = ipa_get_gsi_ep_info(client_idx); + if (!gsi_ep_cfg) { + IPAERR("failed to get GSI config\n"); + ipa_assert(); + return; + } + + ret = gsi_halt_channel_ee( + gsi_ep_cfg->ipa_gsi_chan_num, gsi_ep_cfg->ee, + &code); + for (i = 0; i < IPA_GSI_CHANNEL_STOP_MAX_RETRY && + ret == -GSI_STATUS_AGAIN; i++) { + IPADBG( + "ch %d ee %d with code %d\n is busy try again", + gsi_ep_cfg->ipa_gsi_chan_num, + gsi_ep_cfg->ee, + code); + usleep_range(IPA_GSI_CHANNEL_HALT_MIN_SLEEP, + IPA_GSI_CHANNEL_HALT_MAX_SLEEP); + ret = gsi_halt_channel_ee( + gsi_ep_cfg->ipa_gsi_chan_num, + gsi_ep_cfg->ee, &code); + } + if (ret == GSI_STATUS_SUCCESS) + IPADBG("halted gsi ch %d ee %d with code %d\n", + gsi_ep_cfg->ipa_gsi_chan_num, + gsi_ep_cfg->ee, + code); + else + IPAERR("failed to halt ch %d ee %d code %d\n", + gsi_ep_cfg->ipa_gsi_chan_num, + gsi_ep_cfg->ee, + code); + } + } +} + +static int ipa3_q6_clean_q6_flt_tbls(enum ipa_ip_type ip, + enum ipa_rule_type rlt) +{ + struct ipa3_desc *desc; + struct ipahal_imm_cmd_dma_shared_mem cmd = {0}; + struct ipahal_imm_cmd_pyld **cmd_pyld; + int retval = 0; + int pipe_idx; + int flt_idx = 0; + int num_cmds = 0, count = 0; + int index; + u32 lcl_addr_mem_part; + u32 lcl_hdr_sz; + struct ipa_mem_buffer mem; + struct ipahal_reg_valmask valmask; + struct ipahal_imm_cmd_register_write reg_write_coal_close; + int coal_ep = IPA_EP_NOT_ALLOCATED; + + IPADBG("Entry\n"); + + if ((ip >= IPA_IP_MAX) || (rlt >= IPA_RULE_TYPE_MAX)) { + IPAERR("Input Err: ip=%d ; rlt=%d\n", ip, rlt); + return -EINVAL; + } + + /* + * SRAM memory not allocated to hash tables. Cleaning the of hash table + * operation not supported. + */ + if (rlt == IPA_RULE_HASHABLE && ipa3_ctx->ipa_fltrt_not_hashable) { + IPADBG("Clean hashable rules not supported\n"); + return retval; + } + + /* Up to filtering pipes we have filtering tables + 1 for coal close */ + desc = kcalloc(ipa3_ctx->ep_flt_num + 1, sizeof(struct ipa3_desc), + GFP_KERNEL); + if (!desc) + return -ENOMEM; + + cmd_pyld = kcalloc(ipa3_ctx->ep_flt_num + 1, + sizeof(struct ipahal_imm_cmd_pyld *), GFP_KERNEL); + if (!cmd_pyld) { + retval = -ENOMEM; + goto free_desc; + } + + if (ip == IPA_IP_v4) { + if (rlt == IPA_RULE_HASHABLE) { + lcl_addr_mem_part = IPA_MEM_PART(v4_flt_hash_ofst); + lcl_hdr_sz = IPA_MEM_PART(v4_flt_hash_size); + } else { + lcl_addr_mem_part = IPA_MEM_PART(v4_flt_nhash_ofst); + lcl_hdr_sz = IPA_MEM_PART(v4_flt_nhash_size); + } + } else { + if (rlt == IPA_RULE_HASHABLE) { + lcl_addr_mem_part = IPA_MEM_PART(v6_flt_hash_ofst); + lcl_hdr_sz = IPA_MEM_PART(v6_flt_hash_size); + } else { + lcl_addr_mem_part = IPA_MEM_PART(v6_flt_nhash_ofst); + lcl_hdr_sz = IPA_MEM_PART(v6_flt_nhash_size); + } + } + + retval = ipahal_flt_generate_empty_img(1, lcl_hdr_sz, lcl_hdr_sz, + 0, &mem, true); + if (retval) { + IPAERR("failed to generate flt single tbl empty img\n"); + goto free_cmd_pyld; + } + + coal_ep = ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS); + /* IC to close the coal frame before HPS Clear if coal is enabled */ + if (coal_ep != IPA_EP_NOT_ALLOCATED && !ipa3_ctx->ulso_wa) { + u32 offset = 0; + + reg_write_coal_close.skip_pipeline_clear = false; + reg_write_coal_close.pipeline_clear_options = IPAHAL_HPS_CLEAR; + if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0) + offset = ipahal_get_reg_ofst( + IPA_AGGR_FORCE_CLOSE); + else + offset = ipahal_get_ep_reg_offset( + IPA_AGGR_FORCE_CLOSE_n, coal_ep); + reg_write_coal_close.offset = offset; + ipahal_get_aggr_force_close_valmask(coal_ep, &valmask); + reg_write_coal_close.value = valmask.val; + reg_write_coal_close.value_mask = valmask.mask; + cmd_pyld[num_cmds] = ipahal_construct_imm_cmd( + IPA_IMM_CMD_REGISTER_WRITE, + ®_write_coal_close, false); + if (!cmd_pyld[num_cmds]) { + IPAERR("failed to construct coal close IC\n"); + retval = -ENOMEM; + goto free_empty_img; + } + ipa3_init_imm_cmd_desc(&desc[num_cmds], cmd_pyld[num_cmds]); + ++num_cmds; + } + + for (pipe_idx = 0; pipe_idx < ipa3_ctx->ipa_num_pipes; pipe_idx++) { + if (!ipa_is_ep_support_flt(pipe_idx)) + continue; + + /* + * Iterating over all the filtering pipes which are either + * invalid but connected or connected but not configured by AP. + */ + if (!ipa3_ctx->ep[pipe_idx].valid || + ipa3_ctx->ep[pipe_idx].skip_ep_cfg) { + + /* + * When coal pipe is valid send close coalescing frame + * command and increment the ep_flt_num accordingly. + */ + count = (coal_ep != IPA_EP_NOT_ALLOCATED) ? 1 : 0; + if (num_cmds >= (ipa3_ctx->ep_flt_num + count)) { + IPAERR("number of commands is out of range\n"); + retval = -ENOBUFS; + goto free_empty_img; + } + + cmd.is_read = false; + cmd.skip_pipeline_clear = false; + cmd.pipeline_clear_options = IPAHAL_HPS_CLEAR; + cmd.size = mem.size; + cmd.system_addr = mem.phys_base; + cmd.local_addr = + ipa3_ctx->smem_restricted_bytes + + lcl_addr_mem_part + + ipahal_get_hw_tbl_hdr_width() + + flt_idx * ipahal_get_hw_tbl_hdr_width(); + cmd_pyld[num_cmds] = ipahal_construct_imm_cmd( + IPA_IMM_CMD_DMA_SHARED_MEM, &cmd, false); + if (!cmd_pyld[num_cmds]) { + IPAERR("fail construct dma_shared_mem cmd\n"); + retval = -ENOMEM; + goto free_empty_img; + } + ipa3_init_imm_cmd_desc(&desc[num_cmds], + cmd_pyld[num_cmds]); + ++num_cmds; + } + + ++flt_idx; + } + + IPADBG("Sending %d descriptors for flt tbl clearing\n", num_cmds); + retval = ipa3_send_cmd(num_cmds, desc); + if (retval) { + IPAERR("failed to send immediate command (err %d)\n", retval); + retval = -EFAULT; + } + +free_empty_img: + ipahal_free_dma_mem(&mem); +free_cmd_pyld: + for (index = 0; index < num_cmds; index++) + ipahal_destroy_imm_cmd(cmd_pyld[index]); + kfree(cmd_pyld); +free_desc: + kfree(desc); + return retval; +} + +static int ipa3_q6_clean_q6_rt_tbls(enum ipa_ip_type ip, + enum ipa_rule_type rlt) +{ + struct ipa3_desc *desc; + struct ipahal_imm_cmd_dma_shared_mem cmd = {0}; + struct ipahal_imm_cmd_pyld **cmd_pyld; + int retval = 0; + int num_cmds = 0; + u32 modem_rt_index_lo; + u32 modem_rt_index_hi; + u32 lcl_addr_mem_part; + u32 lcl_hdr_sz; + struct ipa_mem_buffer mem; + struct ipahal_reg_valmask valmask; + struct ipahal_imm_cmd_register_write reg_write_coal_close; + int i; + + IPADBG("Entry\n"); + + if ((ip >= IPA_IP_MAX) || (rlt >= IPA_RULE_TYPE_MAX)) { + IPAERR("Input Err: ip=%d ; rlt=%d\n", ip, rlt); + return -EINVAL; + } + + /* + * SRAM memory not allocated to hash tables. Cleaning the of hash table + * operation not supported. + */ + if (rlt == IPA_RULE_HASHABLE && ipa3_ctx->ipa_fltrt_not_hashable) { + IPADBG("Clean hashable rules not supported\n"); + return retval; + } + + if (ip == IPA_IP_v4) { + modem_rt_index_lo = IPA_MEM_PART(v4_modem_rt_index_lo); + modem_rt_index_hi = IPA_MEM_PART(v4_modem_rt_index_hi); + if (rlt == IPA_RULE_HASHABLE) { + lcl_addr_mem_part = IPA_MEM_PART(v4_rt_hash_ofst); + lcl_hdr_sz = IPA_MEM_PART(v4_flt_hash_size); + } else { + lcl_addr_mem_part = IPA_MEM_PART(v4_rt_nhash_ofst); + lcl_hdr_sz = IPA_MEM_PART(v4_flt_nhash_size); + } + } else { + modem_rt_index_lo = IPA_MEM_PART(v6_modem_rt_index_lo); + modem_rt_index_hi = IPA_MEM_PART(v6_modem_rt_index_hi); + if (rlt == IPA_RULE_HASHABLE) { + lcl_addr_mem_part = IPA_MEM_PART(v6_rt_hash_ofst); + lcl_hdr_sz = IPA_MEM_PART(v6_flt_hash_size); + } else { + lcl_addr_mem_part = IPA_MEM_PART(v6_rt_nhash_ofst); + lcl_hdr_sz = IPA_MEM_PART(v6_flt_nhash_size); + } + } + + retval = ipahal_rt_generate_empty_img( + modem_rt_index_hi - modem_rt_index_lo + 1, + lcl_hdr_sz, lcl_hdr_sz, &mem, true); + if (retval) { + IPAERR("fail generate empty rt img\n"); + return -ENOMEM; + } + + desc = kcalloc(2, sizeof(struct ipa3_desc), GFP_KERNEL); + if (!desc) { + retval = -ENOMEM; + goto free_empty_img; + } + + cmd_pyld = kcalloc(2, sizeof(struct ipahal_imm_cmd_pyld *), GFP_KERNEL); + if (!cmd_pyld) { + retval = -ENOMEM; + goto free_desc; + } + + /* IC to close the coal frame before HPS Clear if coal is enabled */ + if (ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS) != -1 + && !ipa3_ctx->ulso_wa) { + u32 offset = 0; + + i = ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS); + reg_write_coal_close.skip_pipeline_clear = false; + reg_write_coal_close.pipeline_clear_options = IPAHAL_HPS_CLEAR; + if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0) + offset = ipahal_get_reg_ofst( + IPA_AGGR_FORCE_CLOSE); + else + offset = ipahal_get_ep_reg_offset( + IPA_AGGR_FORCE_CLOSE_n, i); + reg_write_coal_close.offset = offset; + ipahal_get_aggr_force_close_valmask(i, &valmask); + reg_write_coal_close.value = valmask.val; + reg_write_coal_close.value_mask = valmask.mask; + cmd_pyld[num_cmds] = ipahal_construct_imm_cmd( + IPA_IMM_CMD_REGISTER_WRITE, + ®_write_coal_close, false); + if (!cmd_pyld[num_cmds]) { + IPAERR("failed to construct coal close IC\n"); + retval = -ENOMEM; + goto free_cmd_pyld; + } + ipa3_init_imm_cmd_desc(&desc[num_cmds], cmd_pyld[num_cmds]); + ++num_cmds; + } + + cmd.is_read = false; + cmd.skip_pipeline_clear = false; + cmd.pipeline_clear_options = IPAHAL_HPS_CLEAR; + cmd.size = mem.size; + cmd.system_addr = mem.phys_base; + cmd.local_addr = ipa3_ctx->smem_restricted_bytes + + lcl_addr_mem_part + + modem_rt_index_lo * ipahal_get_hw_tbl_hdr_width(); + cmd_pyld[num_cmds] = ipahal_construct_imm_cmd( + IPA_IMM_CMD_DMA_SHARED_MEM, &cmd, false); + if (!cmd_pyld[num_cmds]) { + IPAERR("failed to construct dma_shared_mem imm cmd\n"); + retval = -ENOMEM; + goto free_cmd_pyld; + } + ipa3_init_imm_cmd_desc(&desc[num_cmds], cmd_pyld[num_cmds]); + ++num_cmds; + + IPADBG("Sending 1 descriptor for rt tbl clearing\n"); + retval = ipa3_send_cmd(num_cmds, desc); + if (retval) { + IPAERR("failed to send immediate command (err %d)\n", retval); + retval = -EFAULT; + } + +free_cmd_pyld: + for (i = 0; i < num_cmds; i++) + ipahal_destroy_imm_cmd(cmd_pyld[i]); + kfree(cmd_pyld); +free_desc: + kfree(desc); +free_empty_img: + ipahal_free_dma_mem(&mem); + return retval; +} + +static int ipa3_q6_clean_q6_tables(void) +{ + struct ipa3_desc *desc; + struct ipahal_imm_cmd_pyld **cmd_pyld; + struct ipahal_imm_cmd_register_write reg_write_cmd = {0}; + int retval = 0; + int num_cmds = 0; + struct ipahal_reg_valmask valmask; + struct ipahal_imm_cmd_register_write reg_write_coal_close; + int i; + + IPADBG("Entry\n"); + + + if (ipa3_q6_clean_q6_flt_tbls(IPA_IP_v4, IPA_RULE_HASHABLE)) { + IPAERR("failed to clean q6 flt tbls (v4/hashable)\n"); + return -EFAULT; + } + if (ipa3_q6_clean_q6_flt_tbls(IPA_IP_v6, IPA_RULE_HASHABLE)) { + IPAERR("failed to clean q6 flt tbls (v6/hashable)\n"); + return -EFAULT; + } + if (ipa3_q6_clean_q6_flt_tbls(IPA_IP_v4, IPA_RULE_NON_HASHABLE)) { + IPAERR("failed to clean q6 flt tbls (v4/non-hashable)\n"); + return -EFAULT; + } + if (ipa3_q6_clean_q6_flt_tbls(IPA_IP_v6, IPA_RULE_NON_HASHABLE)) { + IPAERR("failed to clean q6 flt tbls (v6/non-hashable)\n"); + return -EFAULT; + } + + if (ipa3_q6_clean_q6_rt_tbls(IPA_IP_v4, IPA_RULE_HASHABLE)) { + IPAERR("failed to clean q6 rt tbls (v4/hashable)\n"); + return -EFAULT; + } + if (ipa3_q6_clean_q6_rt_tbls(IPA_IP_v6, IPA_RULE_HASHABLE)) { + IPAERR("failed to clean q6 rt tbls (v6/hashable)\n"); + return -EFAULT; + } + if (ipa3_q6_clean_q6_rt_tbls(IPA_IP_v4, IPA_RULE_NON_HASHABLE)) { + IPAERR("failed to clean q6 rt tbls (v4/non-hashable)\n"); + return -EFAULT; + } + if (ipa3_q6_clean_q6_rt_tbls(IPA_IP_v6, IPA_RULE_NON_HASHABLE)) { + IPAERR("failed to clean q6 rt tbls (v6/non-hashable)\n"); + return -EFAULT; + } + + /* + * SRAM memory not allocated to hash tables. Cleaning the of hash table + * operation not supported. + */ + if (ipa3_ctx->ipa_fltrt_not_hashable) + return retval; + /* Flush rules cache */ + desc = kcalloc(2, sizeof(struct ipa3_desc), GFP_KERNEL); + if (!desc) + return -ENOMEM; + + cmd_pyld = kcalloc(2, sizeof(struct ipahal_imm_cmd_pyld *), GFP_KERNEL); + if (!cmd_pyld) { + retval = -ENOMEM; + goto bail_desc; + } + + /* IC to close the coal frame before HPS Clear if coal is enabled */ + if (ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS) != -1 + && !ipa3_ctx->ulso_wa) { + u32 offset = 0; + + i = ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS); + reg_write_coal_close.skip_pipeline_clear = false; + reg_write_coal_close.pipeline_clear_options = IPAHAL_HPS_CLEAR; + if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0) + offset = ipahal_get_reg_ofst( + IPA_AGGR_FORCE_CLOSE); + else + offset = ipahal_get_ep_reg_offset( + IPA_AGGR_FORCE_CLOSE_n, i); + reg_write_coal_close.offset = offset; + ipahal_get_aggr_force_close_valmask(i, &valmask); + reg_write_coal_close.value = valmask.val; + reg_write_coal_close.value_mask = valmask.mask; + cmd_pyld[num_cmds] = ipahal_construct_imm_cmd( + IPA_IMM_CMD_REGISTER_WRITE, + ®_write_coal_close, false); + if (!cmd_pyld[num_cmds]) { + IPAERR("failed to construct coal close IC\n"); + retval = -ENOMEM; + goto free_cmd_pyld; + } + ipa3_init_imm_cmd_desc(&desc[num_cmds], cmd_pyld[num_cmds]); + ++num_cmds; + } + + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0) { + struct ipahal_reg_fltrt_cache_flush flush_cache; + + memset(&flush_cache, 0, sizeof(flush_cache)); + flush_cache.flt = true; + flush_cache.rt = true; + ipahal_get_fltrt_cache_flush_valmask( + &flush_cache, &valmask); + reg_write_cmd.offset = ipahal_get_reg_ofst( + IPA_FILT_ROUT_CACHE_FLUSH); + } else { + struct ipahal_reg_fltrt_hash_flush flush_hash; + + flush_hash.v4_flt = true; + flush_hash.v4_rt = true; + flush_hash.v6_flt = true; + flush_hash.v6_rt = true; + ipahal_get_fltrt_hash_flush_valmask(&flush_hash, &valmask); + reg_write_cmd.offset = ipahal_get_reg_ofst( + IPA_FILT_ROUT_HASH_FLUSH); + } + reg_write_cmd.skip_pipeline_clear = false; + reg_write_cmd.pipeline_clear_options = IPAHAL_HPS_CLEAR; + reg_write_cmd.value = valmask.val; + reg_write_cmd.value_mask = valmask.mask; + cmd_pyld[num_cmds] = ipahal_construct_imm_cmd( + IPA_IMM_CMD_REGISTER_WRITE, ®_write_cmd, false); + if (!cmd_pyld[num_cmds]) { + IPAERR("fail construct register_write imm cmd\n"); + retval = -EFAULT; + goto free_cmd_pyld; + } + ipa3_init_imm_cmd_desc(&desc[num_cmds], cmd_pyld[num_cmds]); + ++num_cmds; + + IPADBG("Sending 1 descriptor for tbls flush\n"); + retval = ipa3_send_cmd(num_cmds, desc); + if (retval) { + IPAERR("failed to send immediate command (err %d)\n", retval); + retval = -EFAULT; + } + +free_cmd_pyld: + for (i = 0; i < num_cmds; i++) + ipahal_destroy_imm_cmd(cmd_pyld[i]); + kfree(cmd_pyld); +bail_desc: + kfree(desc); + IPADBG("Done - retval = %d\n", retval); + return retval; +} + +static int ipa3_q6_set_ex_path_to_apps(void) +{ + int ep_idx; + int client_idx; + struct ipa3_desc *desc; + int num_descs = 0; + int index; + struct ipahal_imm_cmd_register_write reg_write; + struct ipahal_imm_cmd_pyld *cmd_pyld; + int retval; + struct ipahal_reg_valmask valmask; + struct ipahal_imm_cmd_register_write reg_write_coal_close; + int i; + + desc = kcalloc(ipa3_ctx->ipa_num_pipes + 1, sizeof(struct ipa3_desc), + GFP_KERNEL); + if (!desc) + return -ENOMEM; + + /* IC to close the coal frame before HPS Clear if coal is enabled */ + if (ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS) != -1 + && !ipa3_ctx->ulso_wa) { + u32 offset = 0; + + i = ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS); + reg_write_coal_close.skip_pipeline_clear = false; + reg_write_coal_close.pipeline_clear_options = IPAHAL_HPS_CLEAR; + if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0) + offset = ipahal_get_reg_ofst( + IPA_AGGR_FORCE_CLOSE); + else + offset = ipahal_get_ep_reg_offset( + IPA_AGGR_FORCE_CLOSE_n, i); + reg_write_coal_close.offset = offset; + ipahal_get_aggr_force_close_valmask(i, &valmask); + reg_write_coal_close.value = valmask.val; + reg_write_coal_close.value_mask = valmask.mask; + cmd_pyld = ipahal_construct_imm_cmd( + IPA_IMM_CMD_REGISTER_WRITE, + ®_write_coal_close, false); + if (!cmd_pyld) { + IPAERR("failed to construct coal close IC\n"); + ipa_assert(); + return -ENOMEM; + } + ipa3_init_imm_cmd_desc(&desc[num_descs], cmd_pyld); + desc[num_descs].callback = ipa3_destroy_imm; + desc[num_descs].user1 = cmd_pyld; + ++num_descs; + } + + /* Set the exception path to AP */ + for (client_idx = 0; client_idx < IPA_CLIENT_MAX; client_idx++) { + ep_idx = ipa_get_ep_mapping(client_idx); + if (ep_idx == -1 || (ep_idx >= ipa3_get_max_num_pipes())) + continue; + + /* disable statuses for all modem controlled prod pipes */ + if (!IPA_CLIENT_IS_TEST(client_idx) && + (IPA_CLIENT_IS_Q6_PROD(client_idx) || + (IPA_CLIENT_IS_PROD(client_idx) && + ipa3_ctx->ep[ep_idx].valid && + ipa3_ctx->ep[ep_idx].skip_ep_cfg) || + (ipa3_ctx->ep[ep_idx].client == IPA_CLIENT_APPS_WAN_PROD + && ipa3_ctx->modem_cfg_emb_pipe_flt))) { + ipa_assert_on(num_descs >= ipa3_ctx->ipa_num_pipes); + + ipa3_ctx->ep[ep_idx].status.status_en = false; + reg_write.skip_pipeline_clear = false; + reg_write.pipeline_clear_options = + IPAHAL_HPS_CLEAR; + reg_write.offset = + ipahal_get_reg_n_ofst(IPA_ENDP_STATUS_n, + ep_idx); + reg_write.value = 0; + reg_write.value_mask = ~0; + cmd_pyld = ipahal_construct_imm_cmd( + IPA_IMM_CMD_REGISTER_WRITE, ®_write, false); + if (!cmd_pyld) { + IPAERR("fail construct register_write cmd\n"); + ipa_assert(); + return -ENOMEM; + } + + ipa3_init_imm_cmd_desc(&desc[num_descs], cmd_pyld); + desc[num_descs].callback = ipa3_destroy_imm; + desc[num_descs].user1 = cmd_pyld; + ++num_descs; + } + } + + /* Will wait 500msecs for IPA tag process completion */ + retval = ipa3_tag_process(desc, num_descs, CLEANUP_TAG_PROCESS_TIMEOUT); + if (retval) { + IPAERR("TAG process failed! (error %d)\n", retval); + /* For timeout error ipa3_destroy_imm cb will destroy user1 */ + if (retval != -ETIME) { + for (index = 0; index < num_descs; index++) + if (desc[index].callback) + desc[index].callback(desc[index].user1, + desc[index].user2); + retval = -EINVAL; + } + } + + kfree(desc); + + return retval; +} + +/* + * ipa3_update_ssr_state() - updating current SSR state + * @is_ssr: [in] Current SSR state + */ + +void ipa3_update_ssr_state(bool is_ssr) +{ + if (is_ssr) + atomic_set(&ipa3_ctx->is_ssr, 1); + else + atomic_set(&ipa3_ctx->is_ssr, 0); +} + +/** + * ipa3_q6_pre_shutdown_cleanup() - A cleanup for all Q6 related configuration + * in IPA HW. This is performed in case of SSR. + * + * This is a mandatory procedure, in case one of the steps fails, the + * AP needs to restart. + */ +void ipa3_q6_pre_shutdown_cleanup(void) +{ + IPADBG_LOW("ENTER\n"); + + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + + ipa3_update_ssr_state(true); + + if (ipa3_ctx->ipa_endp_delay_wa_v2) + ipa3_q6_pipe_flow_control(true); + else if (!ipa3_ctx->ipa_endp_delay_wa) + ipa3_q6_pipe_delay(true); + + ipa3_q6_avoid_holb(); + if (ipa3_ctx->ipa_config_is_mhi) { + ipa3_set_reset_client_cons_pipe_sus_holb(true, + IPA_CLIENT_MHI_CONS); + if (ipa3_ctx->ipa_config_is_auto) + ipa3_set_reset_client_cons_pipe_sus_holb(true, + IPA_CLIENT_MHI2_CONS); + } + if (ipa3_ctx->ipa_wdi_opt_dpath){ + + struct ipa_wlan_opt_dp_remove_all_filter_req_msg_v01 req; + struct ipa_wlan_opt_dp_remove_all_filter_resp_msg_v01 resp; + + memset(&req, 0, sizeof(struct ipa_wlan_opt_dp_remove_all_filter_req_msg_v01)); + + ipa_wdi_opt_dpath_remove_all_filter_req(&req, &resp); + } + + if (ipa3_q6_clean_q6_tables()) { + IPAERR("Failed to clean Q6 tables\n"); + /* + * Indicates IPA hardware is stalled, unexpected + * hardware state. + */ + ipa_assert(); + } + if (ipa3_q6_set_ex_path_to_apps()) { + IPAERR("Failed to redirect exceptions to APPS\n"); + /* + * Indicates IPA hardware is stalled, unexpected + * hardware state. + */ + ipa_assert(); + } + /* Remove delay from Q6 PRODs to avoid pending descriptors + * on pipe reset procedure + */ + + if (ipa3_ctx->ipa_endp_delay_wa_v2) { + ipa3_q6_pipe_flow_control(false); + ipa3_set_reset_client_prod_pipe_delay(true, + IPA_CLIENT_USB_PROD); + } else if (!ipa3_ctx->ipa_endp_delay_wa) { + ipa3_q6_pipe_delay(false); + ipa3_set_reset_client_prod_pipe_delay(true, + IPA_CLIENT_USB_PROD); + if (ipa3_ctx->ipa_config_is_auto) + ipa3_set_reset_client_prod_pipe_delay(true, + IPA_CLIENT_USB2_PROD); + } else { + ipa3_start_stop_client_prod_gsi_chnl(IPA_CLIENT_USB_PROD, + false); + if (ipa3_ctx->ipa_config_is_auto) + ipa3_start_stop_client_prod_gsi_chnl( + IPA_CLIENT_USB2_PROD, false); + } + + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + IPADBG_LOW("Exit with success\n"); +} + +/* + * ipa3_q6_post_shutdown_cleanup() - As part of this cleanup + * check if GSI channel related to Q6 producer client is empty. + * + * Q6 GSI channel emptiness is needed to garantee no descriptors with invalid + * info are injected into IPA RX from IPA_IF, while modem is restarting. + */ +void ipa3_q6_post_shutdown_cleanup(void) +{ + int client_idx; + int ep_idx; + bool prod = false; + + IPADBG_LOW("ENTER\n"); + + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + + /* Handle the issue where SUSPEND was removed for some reason */ + ipa3_q6_avoid_holb(); + + /* halt both prod and cons channels starting at IPAv4 */ + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_0) { + prod = true; + ipa3_halt_q6_gsi_channels(prod); + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + IPADBG("Exit without consumer check\n"); + return; + } + + ipa3_halt_q6_gsi_channels(prod); + + if (!ipa3_ctx->uc_ctx.uc_loaded) { + IPAERR("uC is not loaded. Skipping\n"); + return; + } + + for (client_idx = 0; client_idx < IPA_CLIENT_MAX; client_idx++) + if (IPA_CLIENT_IS_Q6_PROD(client_idx)) { + ep_idx = ipa_get_ep_mapping(client_idx); + if (ep_idx == -1) + continue; + + if (ipa3_uc_is_gsi_channel_empty(client_idx)) { + IPAERR("fail to validate Q6 ch emptiness %d\n", + client_idx); + /* + * Indicates GSI hardware is stalled, unexpected + * hardware state. + * Remove bug for adb reboot issue. + */ + } + } + + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + IPADBG_LOW("Exit with success\n"); +} + +/** + * ipa3_q6_pre_powerup_cleanup() - A cleanup routine for pheripheral + * configuration in IPA HW. This is performed in case of SSR. + * + * This is a mandatory procedure, in case one of the steps fails, the + * AP needs to restart. + */ +void ipa3_q6_pre_powerup_cleanup(void) +{ + IPADBG_LOW("ENTER\n"); + + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + + if (ipa3_ctx->ipa_config_is_mhi) { + if (!ipa3_ctx->ipa_endp_delay_wa) { + ipa3_set_reset_client_prod_pipe_delay(true, + IPA_CLIENT_MHI_PROD); + if (ipa3_ctx->ipa_config_is_auto) + ipa3_set_reset_client_prod_pipe_delay(true, + IPA_CLIENT_MHI2_PROD); + } + } + + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + IPADBG_LOW("Exit with success\n"); +} + +/* + * ipa3_client_prod_post_shutdown_cleanup () - As part of this function + * set end point delay client producer pipes and starting corresponding + * gsi channels + */ + +void ipa3_client_prod_post_shutdown_cleanup(void) +{ + IPADBG_LOW("ENTER\n"); + + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + + ipa3_set_reset_client_prod_pipe_delay(true, + IPA_CLIENT_USB_PROD); + ipa3_start_stop_client_prod_gsi_chnl(IPA_CLIENT_USB_PROD, true); + + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + IPADBG_LOW("Exit with success\n"); +} + +static inline void ipa3_sram_set_canary(u32 *sram_mmio, int offset) +{ + /* Set 4 bytes of CANARY before the offset */ + sram_mmio[(offset - 4) / 4] = IPA_MEM_CANARY_VAL; +} + +/** + * _ipa_init_sram_v3() - Initialize IPA local SRAM. + * + * Return codes: 0 for success, negative value for failure + */ +int _ipa_init_sram_v3(void) +{ + u32 *ipa_sram_mmio; + unsigned long phys_addr; + + IPADBG( + "ipa_wrapper_base(0x%08X) ipa_reg_base_ofst(0x%08X) IPA_SW_AREA_RAM_DIRECT_ACCESS_n(0x%08X) smem_restricted_bytes(0x%08X) smem_sz(0x%08X)\n", + ipa3_ctx->ipa_wrapper_base, + ipa3_ctx->ctrl->ipa_reg_base_ofst, + ipahal_get_reg_n_ofst( + IPA_SW_AREA_RAM_DIRECT_ACCESS_n, + ipa3_ctx->smem_restricted_bytes / 4), + ipa3_ctx->smem_restricted_bytes, + ipa3_ctx->smem_sz); + + phys_addr = ipa3_ctx->ipa_wrapper_base + + ipa3_ctx->ctrl->ipa_reg_base_ofst + + ipahal_get_reg_n_ofst(IPA_SW_AREA_RAM_DIRECT_ACCESS_n, + ipa3_ctx->smem_restricted_bytes / 4); + + ipa_sram_mmio = ioremap(phys_addr, ipa3_ctx->smem_sz); + if (!ipa_sram_mmio) { + IPAERR("fail to ioremap IPA SRAM\n"); + return -ENOMEM; + } + + /* Consult with ipa_i.h on the location of the CANARY values */ + ipa3_sram_set_canary(ipa_sram_mmio, IPA_MEM_PART(v4_flt_hash_ofst) - 4); + ipa3_sram_set_canary(ipa_sram_mmio, IPA_MEM_PART(v4_flt_hash_ofst)); + ipa3_sram_set_canary(ipa_sram_mmio, + IPA_MEM_PART(v4_flt_nhash_ofst) - 4); + ipa3_sram_set_canary(ipa_sram_mmio, IPA_MEM_PART(v4_flt_nhash_ofst)); + ipa3_sram_set_canary(ipa_sram_mmio, IPA_MEM_PART(v6_flt_hash_ofst) - 4); + ipa3_sram_set_canary(ipa_sram_mmio, IPA_MEM_PART(v6_flt_hash_ofst)); + ipa3_sram_set_canary(ipa_sram_mmio, + IPA_MEM_PART(v6_flt_nhash_ofst) - 4); + ipa3_sram_set_canary(ipa_sram_mmio, IPA_MEM_PART(v6_flt_nhash_ofst)); + ipa3_sram_set_canary(ipa_sram_mmio, IPA_MEM_PART(v4_rt_hash_ofst) - 4); + ipa3_sram_set_canary(ipa_sram_mmio, IPA_MEM_PART(v4_rt_hash_ofst)); + ipa3_sram_set_canary(ipa_sram_mmio, IPA_MEM_PART(v4_rt_nhash_ofst) - 4); + ipa3_sram_set_canary(ipa_sram_mmio, IPA_MEM_PART(v4_rt_nhash_ofst)); + ipa3_sram_set_canary(ipa_sram_mmio, IPA_MEM_PART(v6_rt_hash_ofst) - 4); + ipa3_sram_set_canary(ipa_sram_mmio, IPA_MEM_PART(v6_rt_hash_ofst)); + ipa3_sram_set_canary(ipa_sram_mmio, IPA_MEM_PART(v6_rt_nhash_ofst) - 4); + ipa3_sram_set_canary(ipa_sram_mmio, IPA_MEM_PART(v6_rt_nhash_ofst)); + ipa3_sram_set_canary(ipa_sram_mmio, IPA_MEM_PART(modem_hdr_ofst) - 4); + ipa3_sram_set_canary(ipa_sram_mmio, IPA_MEM_PART(modem_hdr_ofst)); + ipa3_sram_set_canary(ipa_sram_mmio, + IPA_MEM_PART(modem_hdr_proc_ctx_ofst) - 4); + ipa3_sram_set_canary(ipa_sram_mmio, + IPA_MEM_PART(modem_hdr_proc_ctx_ofst)); + if (ipa_get_hw_type() >= IPA_HW_v4_5 + && ipa_get_hw_type() < IPA_HW_v5_0) { + /* 4.5, 4.7, 4.9, 4.11 */ + ipa3_sram_set_canary(ipa_sram_mmio, + IPA_MEM_PART(nat_tbl_ofst) - 12); + } + + if (ipa_get_hw_type() >= IPA_HW_v4_0) { + if (ipa_get_hw_type() < IPA_HW_v4_5) { + /* 4.0, 4.1, 4.2 */ + ipa3_sram_set_canary(ipa_sram_mmio, + IPA_MEM_PART(pdn_config_ofst) - 4); + ipa3_sram_set_canary(ipa_sram_mmio, + IPA_MEM_PART(pdn_config_ofst)); + ipa3_sram_set_canary(ipa_sram_mmio, + IPA_MEM_PART(stats_quota_q6_ofst) - 4); + ipa3_sram_set_canary(ipa_sram_mmio, + IPA_MEM_PART(stats_quota_q6_ofst)); + } else if (ipa_get_hw_type() < IPA_HW_v5_0) { + /* 4.5, 4.7, 4.11 */ + ipa3_sram_set_canary(ipa_sram_mmio, + IPA_MEM_PART(stats_quota_q6_ofst) - 12); + } else { + /* 5.0 and above */ + ipa3_sram_set_canary(ipa_sram_mmio, + IPA_MEM_PART(stats_quota_q6_ofst) - 4); + ipa3_sram_set_canary(ipa_sram_mmio, + IPA_MEM_PART(stats_quota_q6_ofst)); + } + } + + /* all excluding 3.5.1, 4.0, 4.1, 4.2 */ + if (ipa_get_hw_type() <= IPA_HW_v3_5 || + ipa_get_hw_type() >= IPA_HW_v4_5) { + ipa3_sram_set_canary(ipa_sram_mmio, + IPA_MEM_PART(modem_ofst) - 4); + ipa3_sram_set_canary(ipa_sram_mmio, IPA_MEM_PART(modem_ofst)); + } + + if (ipa_get_hw_type() == IPA_HW_v5_0) { + ipa3_sram_set_canary(ipa_sram_mmio, + IPA_MEM_PART(apps_v4_flt_nhash_ofst) - 4); + ipa3_sram_set_canary(ipa_sram_mmio, + IPA_MEM_PART(apps_v4_flt_nhash_ofst)); + ipa3_sram_set_canary(ipa_sram_mmio, + IPA_MEM_PART(stats_fnr_ofst) - 4); + ipa3_sram_set_canary(ipa_sram_mmio, + IPA_MEM_PART(stats_fnr_ofst)); + } + + if (ipa_get_hw_type() >= IPA_HW_v5_0) { + ipa3_sram_set_canary(ipa_sram_mmio, + IPA_MEM_PART(pdn_config_ofst - 4)); + ipa3_sram_set_canary(ipa_sram_mmio, + IPA_MEM_PART(pdn_config_ofst)); + } else { + ipa3_sram_set_canary(ipa_sram_mmio, + (ipa_get_hw_type() >= IPA_HW_v3_5) ? + IPA_MEM_PART(uc_descriptor_ram_ofst) : + IPA_MEM_PART(end_ofst)); + } + + iounmap(ipa_sram_mmio); + + return 0; +} + +/** + * _ipa_init_hdr_v3_0() - Initialize IPA header block. + * + * Return codes: 0 for success, negative value for failure + */ +int _ipa_init_hdr_v3_0(void) +{ + struct ipa3_desc hdr_init_desc; + struct ipa3_desc dma_cmd_desc[2]; + struct ipa_mem_buffer mem; + struct ipahal_imm_cmd_hdr_init_local cmd = {0}; + struct ipahal_imm_cmd_pyld *hdr_init_cmd_payload; + struct ipahal_imm_cmd_pyld *cmd_pyld[2]; + struct ipahal_imm_cmd_dma_shared_mem dma_cmd = { 0 }; + struct ipahal_reg_valmask valmask; + struct ipahal_imm_cmd_register_write reg_write_coal_close; + int num_cmds = 0; + int i; + + mem.size = IPA_MEM_PART(modem_hdr_size) + IPA_MEM_PART(apps_hdr_size); + mem.base = dma_alloc_coherent(ipa3_ctx->pdev, mem.size, &mem.phys_base, + GFP_KERNEL); + if (!mem.base) { + IPAERR("fail to alloc DMA buff of size %d\n", mem.size); + return -ENOMEM; + } + + cmd.hdr_table_addr = mem.phys_base; + cmd.size_hdr_table = mem.size; + cmd.hdr_addr = ipa3_ctx->smem_restricted_bytes + + IPA_MEM_PART(modem_hdr_ofst); + hdr_init_cmd_payload = ipahal_construct_imm_cmd( + IPA_IMM_CMD_HDR_INIT_LOCAL, &cmd, false); + if (!hdr_init_cmd_payload) { + IPAERR("fail to construct hdr_init_local imm cmd\n"); + dma_free_coherent(ipa3_ctx->pdev, + mem.size, mem.base, + mem.phys_base); + return -EFAULT; + } + ipa3_init_imm_cmd_desc(&hdr_init_desc, hdr_init_cmd_payload); + IPA_DUMP_BUFF(mem.base, mem.phys_base, mem.size); + + if (ipa3_send_cmd(1, &hdr_init_desc)) { + IPAERR("fail to send immediate command\n"); + ipahal_destroy_imm_cmd(hdr_init_cmd_payload); + dma_free_coherent(ipa3_ctx->pdev, + mem.size, mem.base, + mem.phys_base); + return -EFAULT; + } + + ipahal_destroy_imm_cmd(hdr_init_cmd_payload); + dma_free_coherent(ipa3_ctx->pdev, mem.size, mem.base, mem.phys_base); + + /* IC to close the coal frame before HPS Clear if coal is enabled */ + if (ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS) != -1 + && !ipa3_ctx->ulso_wa) { + u32 offset = 0; + + i = ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS); + reg_write_coal_close.skip_pipeline_clear = false; + reg_write_coal_close.pipeline_clear_options = IPAHAL_HPS_CLEAR; + if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0) + offset = ipahal_get_reg_ofst( + IPA_AGGR_FORCE_CLOSE); + else + offset = ipahal_get_ep_reg_offset( + IPA_AGGR_FORCE_CLOSE_n, i); + reg_write_coal_close.offset = offset; + ipahal_get_aggr_force_close_valmask(i, &valmask); + reg_write_coal_close.value = valmask.val; + reg_write_coal_close.value_mask = valmask.mask; + cmd_pyld[num_cmds] = ipahal_construct_imm_cmd( + IPA_IMM_CMD_REGISTER_WRITE, + ®_write_coal_close, false); + if (!cmd_pyld[num_cmds]) { + IPAERR("failed to construct coal close IC\n"); + return -ENOMEM; + } + ipa3_init_imm_cmd_desc(&dma_cmd_desc[num_cmds], + cmd_pyld[num_cmds]); + ++num_cmds; + } + + mem.size = IPA_MEM_PART(modem_hdr_proc_ctx_size) + + IPA_MEM_PART(apps_hdr_proc_ctx_size); + mem.base = dma_alloc_coherent(ipa3_ctx->pdev, mem.size, &mem.phys_base, + GFP_KERNEL); + if (!mem.base) { + IPAERR("fail to alloc DMA buff of size %d\n", mem.size); + return -ENOMEM; + } + + dma_cmd.is_read = false; + dma_cmd.skip_pipeline_clear = false; + dma_cmd.pipeline_clear_options = IPAHAL_HPS_CLEAR; + dma_cmd.system_addr = mem.phys_base; + dma_cmd.local_addr = ipa3_ctx->smem_restricted_bytes + + IPA_MEM_PART(modem_hdr_proc_ctx_ofst); + dma_cmd.size = mem.size; + cmd_pyld[num_cmds] = ipahal_construct_imm_cmd( + IPA_IMM_CMD_DMA_SHARED_MEM, &dma_cmd, false); + if (!cmd_pyld[num_cmds]) { + IPAERR("fail to construct dma_shared_mem imm\n"); + dma_free_coherent(ipa3_ctx->pdev, + mem.size, mem.base, + mem.phys_base); + return -ENOMEM; + } + ipa3_init_imm_cmd_desc(&dma_cmd_desc[num_cmds], cmd_pyld[num_cmds]); + ++num_cmds; + IPA_DUMP_BUFF(mem.base, mem.phys_base, mem.size); + + if (ipa3_send_cmd(num_cmds, dma_cmd_desc)) { + IPAERR("fail to send immediate command\n"); + for (i = 0; i < num_cmds; i++) + ipahal_destroy_imm_cmd(cmd_pyld[i]); + dma_free_coherent(ipa3_ctx->pdev, + mem.size, + mem.base, + mem.phys_base); + return -EBUSY; + } + for (i = 0; i < num_cmds; i++) + ipahal_destroy_imm_cmd(cmd_pyld[i]); + + ipahal_write_reg(IPA_LOCAL_PKT_PROC_CNTXT_BASE, dma_cmd.local_addr); + + dma_free_coherent(ipa3_ctx->pdev, mem.size, mem.base, mem.phys_base); + + return 0; +} + +/** + * _ipa_init_rt4_v3() - Initialize IPA routing block for IPv4. + * + * Return codes: 0 for success, negative value for failure + */ +int _ipa_init_rt4_v3(void) +{ + struct ipa3_desc desc; + struct ipa_mem_buffer mem; + struct ipahal_imm_cmd_ip_v4_routing_init v4_cmd; + struct ipahal_imm_cmd_pyld *cmd_pyld; + int i; + int rc = 0; + + for (i = IPA_MEM_PART(v4_modem_rt_index_lo); + i <= IPA_MEM_PART(v4_modem_rt_index_hi); + i++) + ipa3_ctx->rt_idx_bitmap[IPA_IP_v4] |= (1 << i); + IPADBG("v4 rt bitmap 0x%lx\n", ipa3_ctx->rt_idx_bitmap[IPA_IP_v4]); + + rc = ipahal_rt_generate_empty_img(IPA_MEM_PART(v4_rt_num_index), + IPA_MEM_PART(v4_rt_hash_size), IPA_MEM_PART(v4_rt_nhash_size), + &mem, false); + if (rc) { + IPAERR("fail generate empty v4 rt img\n"); + return rc; + } + + /* + * SRAM memory not allocated to hash tables. Initializing/Sending + * command to hash tables(filer/routing) operation not supported. + */ + if (ipa3_ctx->ipa_fltrt_not_hashable) { + v4_cmd.hash_rules_addr = 0; + v4_cmd.hash_rules_size = 0; + v4_cmd.hash_local_addr = 0; + } else { + v4_cmd.hash_rules_addr = mem.phys_base; + v4_cmd.hash_rules_size = mem.size; + v4_cmd.hash_local_addr = ipa3_ctx->smem_restricted_bytes + + IPA_MEM_PART(v4_rt_hash_ofst); + } + + v4_cmd.nhash_rules_addr = mem.phys_base; + v4_cmd.nhash_rules_size = mem.size; + v4_cmd.nhash_local_addr = ipa3_ctx->smem_restricted_bytes + + IPA_MEM_PART(v4_rt_nhash_ofst); + IPADBG("putting hashable routing IPv4 rules to phys 0x%x\n", + v4_cmd.hash_local_addr); + IPADBG("putting non-hashable routing IPv4 rules to phys 0x%x\n", + v4_cmd.nhash_local_addr); + cmd_pyld = ipahal_construct_imm_cmd( + IPA_IMM_CMD_IP_V4_ROUTING_INIT, &v4_cmd, false); + if (!cmd_pyld) { + IPAERR("fail construct ip_v4_rt_init imm cmd\n"); + rc = -EPERM; + goto free_mem; + } + + ipa3_init_imm_cmd_desc(&desc, cmd_pyld); + IPA_DUMP_BUFF(mem.base, mem.phys_base, mem.size); + + if (ipa3_send_cmd(1, &desc)) { + IPAERR("fail to send immediate command\n"); + rc = -EFAULT; + } + + ipahal_destroy_imm_cmd(cmd_pyld); + +free_mem: + ipahal_free_dma_mem(&mem); + return rc; +} + +/** + * _ipa_init_rt6_v3() - Initialize IPA routing block for IPv6. + * + * Return codes: 0 for success, negative value for failure + */ +int _ipa_init_rt6_v3(void) +{ + struct ipa3_desc desc; + struct ipa_mem_buffer mem; + struct ipahal_imm_cmd_ip_v6_routing_init v6_cmd; + struct ipahal_imm_cmd_pyld *cmd_pyld; + int i; + int rc = 0; + + for (i = IPA_MEM_PART(v6_modem_rt_index_lo); + i <= IPA_MEM_PART(v6_modem_rt_index_hi); + i++) + ipa3_ctx->rt_idx_bitmap[IPA_IP_v6] |= (1 << i); + IPADBG("v6 rt bitmap 0x%lx\n", ipa3_ctx->rt_idx_bitmap[IPA_IP_v6]); + + rc = ipahal_rt_generate_empty_img(IPA_MEM_PART(v6_rt_num_index), + IPA_MEM_PART(v6_rt_hash_size), IPA_MEM_PART(v6_rt_nhash_size), + &mem, false); + if (rc) { + IPAERR("fail generate empty v6 rt img\n"); + return rc; + } + + /* + * SRAM memory not allocated to hash tables. Initializing/Sending + * command to hash tables(filer/routing) operation not supported. + */ + if (ipa3_ctx->ipa_fltrt_not_hashable) { + v6_cmd.hash_rules_addr = 0; + v6_cmd.hash_rules_size = 0; + v6_cmd.hash_local_addr = 0; + } else { + v6_cmd.hash_rules_addr = mem.phys_base; + v6_cmd.hash_rules_size = mem.size; + v6_cmd.hash_local_addr = ipa3_ctx->smem_restricted_bytes + + IPA_MEM_PART(v6_rt_hash_ofst); + } + + v6_cmd.nhash_rules_addr = mem.phys_base; + v6_cmd.nhash_rules_size = mem.size; + v6_cmd.nhash_local_addr = ipa3_ctx->smem_restricted_bytes + + IPA_MEM_PART(v6_rt_nhash_ofst); + IPADBG("putting hashable routing IPv6 rules to phys 0x%x\n", + v6_cmd.hash_local_addr); + IPADBG("putting non-hashable routing IPv6 rules to phys 0x%x\n", + v6_cmd.nhash_local_addr); + cmd_pyld = ipahal_construct_imm_cmd( + IPA_IMM_CMD_IP_V6_ROUTING_INIT, &v6_cmd, false); + if (!cmd_pyld) { + IPAERR("fail construct ip_v6_rt_init imm cmd\n"); + rc = -EPERM; + goto free_mem; + } + + ipa3_init_imm_cmd_desc(&desc, cmd_pyld); + IPA_DUMP_BUFF(mem.base, mem.phys_base, mem.size); + + if (ipa3_send_cmd(1, &desc)) { + IPAERR("fail to send immediate command\n"); + rc = -EFAULT; + } + + ipahal_destroy_imm_cmd(cmd_pyld); + +free_mem: + ipahal_free_dma_mem(&mem); + return rc; +} + +/** + * _ipa_init_flt4_v3() - Initialize IPA filtering block for IPv4. + * + * Return codes: 0 for success, negative value for failure + */ +int _ipa_init_flt4_v3(void) +{ + struct ipa3_desc desc; + struct ipa_mem_buffer mem; + struct ipahal_imm_cmd_ip_v4_filter_init v4_cmd; + struct ipahal_imm_cmd_pyld *cmd_pyld; + int rc; + + rc = ipahal_flt_generate_empty_img(ipa3_ctx->ep_flt_num, + IPA_MEM_PART(v4_flt_hash_size), + IPA_MEM_PART(v4_flt_nhash_size), ipa3_ctx->ep_flt_bitmap, + &mem, false); + if (rc) { + IPAERR("fail generate empty v4 flt img\n"); + return rc; + } + + /* + * SRAM memory not allocated to hash tables. Initializing/Sending + * command to hash tables(filer/routing) operation not supported. + */ + if (ipa3_ctx->ipa_fltrt_not_hashable) { + v4_cmd.hash_rules_addr = 0; + v4_cmd.hash_rules_size = 0; + v4_cmd.hash_local_addr = 0; + } else { + v4_cmd.hash_rules_addr = mem.phys_base; + v4_cmd.hash_rules_size = mem.size; + v4_cmd.hash_local_addr = ipa3_ctx->smem_restricted_bytes + + IPA_MEM_PART(v4_flt_hash_ofst); + } + + v4_cmd.nhash_rules_addr = mem.phys_base; + v4_cmd.nhash_rules_size = mem.size; + v4_cmd.nhash_local_addr = ipa3_ctx->smem_restricted_bytes + + IPA_MEM_PART(v4_flt_nhash_ofst); + IPADBG("putting hashable filtering IPv4 rules to phys 0x%x\n", + v4_cmd.hash_local_addr); + IPADBG("putting non-hashable filtering IPv4 rules to phys 0x%x\n", + v4_cmd.nhash_local_addr); + cmd_pyld = ipahal_construct_imm_cmd( + IPA_IMM_CMD_IP_V4_FILTER_INIT, &v4_cmd, false); + if (!cmd_pyld) { + IPAERR("fail construct ip_v4_flt_init imm cmd\n"); + rc = -EPERM; + goto free_mem; + } + + ipa3_init_imm_cmd_desc(&desc, cmd_pyld); + IPA_DUMP_BUFF(mem.base, mem.phys_base, mem.size); + + if (ipa3_send_cmd(1, &desc)) { + IPAERR("fail to send immediate command\n"); + rc = -EFAULT; + } + + ipahal_destroy_imm_cmd(cmd_pyld); + +free_mem: + ipahal_free_dma_mem(&mem); + return rc; +} + +/** + * _ipa_init_flt6_v3() - Initialize IPA filtering block for IPv6. + * + * Return codes: 0 for success, negative value for failure + */ +int _ipa_init_flt6_v3(void) +{ + struct ipa3_desc desc; + struct ipa_mem_buffer mem; + struct ipahal_imm_cmd_ip_v6_filter_init v6_cmd; + struct ipahal_imm_cmd_pyld *cmd_pyld; + int rc; + + rc = ipahal_flt_generate_empty_img(ipa3_ctx->ep_flt_num, + IPA_MEM_PART(v6_flt_hash_size), + IPA_MEM_PART(v6_flt_nhash_size), ipa3_ctx->ep_flt_bitmap, + &mem, false); + if (rc) { + IPAERR("fail generate empty v6 flt img\n"); + return rc; + } + + /* + * SRAM memory not allocated to hash tables. Initializing/Sending + * command to hash tables(filer/routing) operation not supported. + */ + if (ipa3_ctx->ipa_fltrt_not_hashable) { + v6_cmd.hash_rules_addr = 0; + v6_cmd.hash_rules_size = 0; + v6_cmd.hash_local_addr = 0; + } else { + v6_cmd.hash_rules_addr = mem.phys_base; + v6_cmd.hash_rules_size = mem.size; + v6_cmd.hash_local_addr = ipa3_ctx->smem_restricted_bytes + + IPA_MEM_PART(v6_flt_hash_ofst); + } + + v6_cmd.nhash_rules_addr = mem.phys_base; + v6_cmd.nhash_rules_size = mem.size; + v6_cmd.nhash_local_addr = ipa3_ctx->smem_restricted_bytes + + IPA_MEM_PART(v6_flt_nhash_ofst); + IPADBG("putting hashable filtering IPv6 rules to phys 0x%x\n", + v6_cmd.hash_local_addr); + IPADBG("putting non-hashable filtering IPv6 rules to phys 0x%x\n", + v6_cmd.nhash_local_addr); + + cmd_pyld = ipahal_construct_imm_cmd( + IPA_IMM_CMD_IP_V6_FILTER_INIT, &v6_cmd, false); + if (!cmd_pyld) { + IPAERR("fail construct ip_v6_flt_init imm cmd\n"); + rc = -EPERM; + goto free_mem; + } + + ipa3_init_imm_cmd_desc(&desc, cmd_pyld); + IPA_DUMP_BUFF(mem.base, mem.phys_base, mem.size); + + if (ipa3_send_cmd(1, &desc)) { + IPAERR("fail to send immediate command\n"); + rc = -EFAULT; + } + + ipahal_destroy_imm_cmd(cmd_pyld); + +free_mem: + ipahal_free_dma_mem(&mem); + return rc; +} + +static int ipa3_setup_flt_hash_tuple(void) +{ + int pipe_idx; + struct ipahal_reg_hash_tuple tuple; + + memset(&tuple, 0, sizeof(struct ipahal_reg_hash_tuple)); + + for (pipe_idx = 0; pipe_idx < ipa3_ctx->ipa_num_pipes ; pipe_idx++) { + if (!ipa_is_ep_support_flt(pipe_idx)) + continue; + + if (ipa_is_modem_pipe(pipe_idx)) + continue; + + if (ipa3_set_flt_tuple_mask(pipe_idx, &tuple)) { + IPAERR("failed to setup pipe %d flt tuple\n", pipe_idx); + return -EFAULT; + } + } + + return 0; +} + +static int ipa3_setup_rt_hash_tuple(void) +{ + int tbl_idx; + struct ipahal_reg_hash_tuple tuple; + + memset(&tuple, 0, sizeof(struct ipahal_reg_hash_tuple)); + + for (tbl_idx = 0; + tbl_idx < max(IPA_MEM_PART(v6_rt_num_index), + IPA_MEM_PART(v4_rt_num_index)); + tbl_idx++) { + + if (tbl_idx >= IPA_MEM_PART(v4_modem_rt_index_lo) && + tbl_idx <= IPA_MEM_PART(v4_modem_rt_index_hi)) + continue; + + if (tbl_idx >= IPA_MEM_PART(v6_modem_rt_index_lo) && + tbl_idx <= IPA_MEM_PART(v6_modem_rt_index_hi)) + continue; + + if (ipa3_set_rt_tuple_mask(tbl_idx, &tuple)) { + IPAERR("failed to setup tbl %d rt tuple\n", tbl_idx); + return -EFAULT; + } + } + + return 0; +} + +static int ipa3_setup_apps_pipes(void) +{ + struct ipa_sys_connect_params sys_in; + int result = 0; + + if (ipa3_ctx->gsi_ch20_wa) { + IPADBG("Allocating GSI physical channel 20\n"); + result = ipa_gsi_ch20_wa(); + if (result) { + IPAERR("ipa_gsi_ch20_wa failed %d\n", result); + goto fail_ch20_wa; + } + } + + /* allocate the common PROD event ring */ + if (ipa3_alloc_common_event_ring()) { + IPAERR("ipa3_alloc_common_event_ring failed.\n"); + result = -EPERM; + goto fail_ch20_wa; + } + + /* CMD OUT (AP->IPA) */ + memset(&sys_in, 0, sizeof(struct ipa_sys_connect_params)); + sys_in.client = IPA_CLIENT_APPS_CMD_PROD; + sys_in.desc_fifo_sz = IPA_SYS_DESC_FIFO_SZ; + sys_in.ipa_ep_cfg.mode.mode = IPA_DMA; + sys_in.ipa_ep_cfg.mode.dst = IPA_CLIENT_APPS_LAN_CONS; + if (ipa_setup_sys_pipe(&sys_in, &ipa3_ctx->clnt_hdl_cmd)) { + IPAERR(":setup sys pipe (APPS_CMD_PROD) failed.\n"); + result = -EPERM; + goto fail_ch20_wa; + } + IPADBG("Apps to IPA cmd pipe is connected\n"); + + IPADBG("Will initialize SRAM\n"); + ipa3_ctx->ctrl->ipa_init_sram(); + IPADBG("SRAM initialized\n"); + + IPADBG("Will initialize HDR\n"); + ipa3_ctx->ctrl->ipa_init_hdr(); + IPADBG("HDR initialized\n"); + + IPADBG("Will initialize V4 RT\n"); + ipa3_ctx->ctrl->ipa_init_rt4(); + IPADBG("V4 RT initialized\n"); + + IPADBG("Will initialize V6 RT\n"); + ipa3_ctx->ctrl->ipa_init_rt6(); + IPADBG("V6 RT initialized\n"); + + IPADBG("Will initialize V4 FLT\n"); + ipa3_ctx->ctrl->ipa_init_flt4(); + IPADBG("V4 FLT initialized\n"); + + IPADBG("Will initialize V6 FLT\n"); + ipa3_ctx->ctrl->ipa_init_flt6(); + IPADBG("V6 FLT initialized\n"); + + if (!ipa3_ctx->ipa_fltrt_not_hashable) { + if (ipa3_setup_flt_hash_tuple()) { + IPAERR(":fail to configure flt hash tuple\n"); + result = -EPERM; + goto fail_flt_hash_tuple; + } + IPADBG("flt hash tuple is configured\n"); + + if (ipa3_setup_rt_hash_tuple()) { + IPAERR(":fail to configure rt hash tuple\n"); + result = -EPERM; + goto fail_flt_hash_tuple; + } + IPADBG("rt hash tuple is configured\n"); + } + if (ipa3_setup_exception_path()) { + IPAERR(":fail to setup excp path\n"); + result = -EPERM; + goto fail_flt_hash_tuple; + } + IPADBG("Exception path was successfully set"); + + if (ipa3_setup_dflt_rt_tables()) { + IPAERR(":fail to setup dflt routes\n"); + result = -EPERM; + goto fail_flt_hash_tuple; + } + IPADBG("default routing was set\n"); + + ipa3_ctx->clnt_hdl_data_in = 0; + + if ( ipa3_ctx->ipa_hw_type >= IPA_HW_v5_5 && ipa3_ctx->lan_coal_enable) { + /* + * LAN_COAL IN (IPA->AP) + */ + memset(&sys_in, 0, sizeof(struct ipa_sys_connect_params)); + sys_in.client = IPA_CLIENT_APPS_LAN_COAL_CONS; + sys_in.desc_fifo_sz = IPA_SYS_DESC_FIFO_SZ; + sys_in.notify = ipa3_lan_coal_rx_cb; + sys_in.priv = NULL; + if (ipa3_ctx->lan_rx_napi_enable) + sys_in.napi_obj = &ipa3_ctx->napi_lan_rx; + sys_in.ipa_ep_cfg.hdr_ext.hdr_little_endian = false; + sys_in.ipa_ep_cfg.hdr_ext.hdr_total_len_or_pad_valid = true; + sys_in.ipa_ep_cfg.hdr_ext.hdr_total_len_or_pad = IPA_HDR_PAD; + sys_in.ipa_ep_cfg.hdr_ext.hdr_payload_len_inc_padding = false; + sys_in.ipa_ep_cfg.hdr_ext.hdr_total_len_or_pad_offset = 0; + sys_in.ipa_ep_cfg.hdr_ext.hdr_pad_to_alignment = 2; + sys_in.ipa_ep_cfg.cfg.cs_offload_en = IPA_DISABLE_CS_OFFLOAD; + + /** + * ipa3_lan_coal_rx_cb() intended to notify the source EP about + * packet being received on the LAN_COAL_CONS via calling the + * source EP call-back. There could be a race condition with + * calling this call-back. Other thread may nullify it - e.g. on + * EP disconnect. This lock intended to protect the access to the + * source EP call-back + */ + spin_lock_init(&ipa3_ctx->disconnect_lock); + if (ipa_setup_sys_pipe(&sys_in, &ipa3_ctx->clnt_hdl_data_in)) { + IPAERR(":setup sys pipe (LAN_COAL_CONS) failed.\n"); + result = -EPERM; + goto fail_flt_hash_tuple; + } + + } else { /* ipa3_ctx->ipa_hw_type < IPA_HW_v5_5 */ + /* + * LAN IN (IPA->AP) + */ + memset(&sys_in, 0, sizeof(struct ipa_sys_connect_params)); + sys_in.client = IPA_CLIENT_APPS_LAN_CONS; + sys_in.desc_fifo_sz = IPA_SYS_DESC_FIFO_SZ; + sys_in.notify = ipa3_lan_rx_cb; + sys_in.priv = NULL; + if (ipa3_ctx->lan_rx_napi_enable) + sys_in.napi_obj = &ipa3_ctx->napi_lan_rx; + sys_in.ipa_ep_cfg.hdr.hdr_len = IPA_LAN_RX_HEADER_LENGTH; + sys_in.ipa_ep_cfg.hdr_ext.hdr_little_endian = false; + sys_in.ipa_ep_cfg.hdr_ext.hdr_total_len_or_pad_valid = true; + sys_in.ipa_ep_cfg.hdr_ext.hdr_total_len_or_pad = IPA_HDR_PAD; + sys_in.ipa_ep_cfg.hdr_ext.hdr_payload_len_inc_padding = false; + sys_in.ipa_ep_cfg.hdr_ext.hdr_total_len_or_pad_offset = 0; + sys_in.ipa_ep_cfg.hdr_ext.hdr_pad_to_alignment = 2; + sys_in.ipa_ep_cfg.cfg.cs_offload_en = IPA_DISABLE_CS_OFFLOAD; + + /** + * ipa_lan_rx_cb() intended to notify the source EP about packet + * being received on the LAN_CONS via calling the source EP call-back. + * There could be a race condition with calling this call-back. Other + * thread may nullify it - e.g. on EP disconnect. + * This lock intended to protect the access to the source EP call-back + */ + spin_lock_init(&ipa3_ctx->disconnect_lock); + if (ipa_setup_sys_pipe(&sys_in, &ipa3_ctx->clnt_hdl_data_in)) { + IPAERR(":setup sys pipe (LAN_CONS) failed.\n"); + result = -EPERM; + goto fail_flt_hash_tuple; + } + } + + /* LAN OUT (AP->IPA) */ + if (!ipa3_ctx->ipa_config_is_mhi) { + memset(&sys_in, 0, sizeof(struct ipa_sys_connect_params)); + sys_in.client = IPA_CLIENT_APPS_LAN_PROD; + sys_in.desc_fifo_sz = IPA_SYS_TX_DATA_DESC_FIFO_SZ; + sys_in.ipa_ep_cfg.mode.mode = IPA_BASIC; + if (ipa3_ctx->ulso_supported) { + sys_in.ipa_ep_cfg.ulso.ipid_min_max_idx = + ENDP_INIT_ULSO_CFG_IP_ID_MIN_MAX_VAL_IDX_LINUX; + sys_in.ipa_ep_cfg.ulso.is_ulso_pipe = true; + sys_in.ipa_ep_cfg.cfg.cs_offload_en = IPA_ENABLE_CS_OFFLOAD_UL; + sys_in.ipa_ep_cfg.hdr.hdr_len = QMAP_HDR_LEN + ETH_HLEN; + sys_in.ipa_ep_cfg.hdr_ext.hdr_bytes_to_remove_valid = true; + sys_in.ipa_ep_cfg.hdr_ext.hdr_bytes_to_remove = QMAP_HDR_LEN; + } + if (ipa_setup_sys_pipe(&sys_in, + &ipa3_ctx->clnt_hdl_data_out)) { + IPAERR(":setup sys pipe (LAN_PROD) failed.\n"); + result = -EPERM; + goto fail_lan_data_out; + } + } + + return 0; + +fail_lan_data_out: + if ( ipa3_ctx->clnt_hdl_data_in ) + ipa_teardown_sys_pipe(ipa3_ctx->clnt_hdl_data_in); +fail_flt_hash_tuple: + if (ipa3_ctx->dflt_v6_rt_rule_hdl) + __ipa3_del_rt_rule(ipa3_ctx->dflt_v6_rt_rule_hdl); + if (ipa3_ctx->dflt_v4_rt_rule_hdl) + __ipa3_del_rt_rule(ipa3_ctx->dflt_v4_rt_rule_hdl); + if (ipa3_ctx->excp_hdr_hdl) + __ipa3_del_hdr(ipa3_ctx->excp_hdr_hdl, false); + ipa_teardown_sys_pipe(ipa3_ctx->clnt_hdl_cmd); +fail_ch20_wa: + return result; +} + +static void ipa3_teardown_apps_pipes(void) +{ + if (!ipa3_ctx->ipa_config_is_mhi) + ipa_teardown_sys_pipe(ipa3_ctx->clnt_hdl_data_out); + if ( ipa3_ctx->clnt_hdl_data_in ) + ipa_teardown_sys_pipe(ipa3_ctx->clnt_hdl_data_in); + __ipa3_del_rt_rule(ipa3_ctx->dflt_v6_rt_rule_hdl); + __ipa3_del_rt_rule(ipa3_ctx->dflt_v4_rt_rule_hdl); + __ipa3_del_hdr(ipa3_ctx->excp_hdr_hdl, false); + ipa_teardown_sys_pipe(ipa3_ctx->clnt_hdl_cmd); + ipa3_dealloc_common_event_ring(); +} + +#ifdef CONFIG_COMPAT + +static long compat_ipa3_nat_ipv6ct_alloc_table(unsigned long arg, + int (alloc_func)(struct ipa_ioc_nat_ipv6ct_table_alloc *)) +{ + long retval; + struct ipa_ioc_nat_ipv6ct_table_alloc32 table_alloc32; + struct ipa_ioc_nat_ipv6ct_table_alloc table_alloc; + + retval = copy_from_user(&table_alloc32, (const void __user *)arg, + sizeof(struct ipa_ioc_nat_ipv6ct_table_alloc32)); + if (retval) + return retval; + + table_alloc.size = (size_t)table_alloc32.size; + table_alloc.offset = (off_t)table_alloc32.offset; + + retval = alloc_func(&table_alloc); + if (retval) + return retval; + + if (table_alloc.offset) { + table_alloc32.offset = (compat_off_t)table_alloc.offset; + retval = copy_to_user((void __user *)arg, &table_alloc32, + sizeof(struct ipa_ioc_nat_ipv6ct_table_alloc32)); + } + + return retval; +} + +long compat_ipa3_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + long retval = 0; + struct ipa3_ioc_nat_alloc_mem32 nat_mem32; + struct ipa_ioc_nat_alloc_mem nat_mem; + + switch (cmd) { + case IPA_IOC_ADD_HDR32: + cmd = IPA_IOC_ADD_HDR; + break; + case IPA_IOC_DEL_HDR32: + cmd = IPA_IOC_DEL_HDR; + break; + case IPA_IOC_ADD_RT_RULE32: + cmd = IPA_IOC_ADD_RT_RULE; + break; + case IPA_IOC_DEL_RT_RULE32: + cmd = IPA_IOC_DEL_RT_RULE; + break; + case IPA_IOC_ADD_FLT_RULE32: + cmd = IPA_IOC_ADD_FLT_RULE; + break; + case IPA_IOC_DEL_FLT_RULE32: + cmd = IPA_IOC_DEL_FLT_RULE; + break; + case IPA_IOC_GET_RT_TBL32: + cmd = IPA_IOC_GET_RT_TBL; + break; + case IPA_IOC_COPY_HDR32: + cmd = IPA_IOC_COPY_HDR; + break; + case IPA_IOC_QUERY_INTF32: + cmd = IPA_IOC_QUERY_INTF; + break; + case IPA_IOC_QUERY_INTF_TX_PROPS32: + cmd = IPA_IOC_QUERY_INTF_TX_PROPS; + break; + case IPA_IOC_QUERY_INTF_RX_PROPS32: + cmd = IPA_IOC_QUERY_INTF_RX_PROPS; + break; + case IPA_IOC_QUERY_INTF_EXT_PROPS32: + cmd = IPA_IOC_QUERY_INTF_EXT_PROPS; + break; + case IPA_IOC_GET_HDR32: + cmd = IPA_IOC_GET_HDR; + break; + case IPA_IOC_ALLOC_NAT_MEM32: + retval = copy_from_user(&nat_mem32, (const void __user *)arg, + sizeof(struct ipa3_ioc_nat_alloc_mem32)); + if (retval) + return retval; + memcpy(nat_mem.dev_name, nat_mem32.dev_name, + IPA_RESOURCE_NAME_MAX); + nat_mem.size = (size_t)nat_mem32.size; + nat_mem.offset = (off_t)nat_mem32.offset; + + /* null terminate the string */ + nat_mem.dev_name[IPA_RESOURCE_NAME_MAX - 1] = '\0'; + + retval = ipa3_allocate_nat_device(&nat_mem); + if (retval) + return retval; + nat_mem32.offset = (compat_off_t)nat_mem.offset; + retval = copy_to_user((void __user *)arg, &nat_mem32, + sizeof(struct ipa3_ioc_nat_alloc_mem32)); + return retval; + case IPA_IOC_ALLOC_NAT_TABLE32: + return compat_ipa3_nat_ipv6ct_alloc_table(arg, + ipa3_allocate_nat_table); + case IPA_IOC_ALLOC_IPV6CT_TABLE32: + return compat_ipa3_nat_ipv6ct_alloc_table(arg, + ipa3_allocate_ipv6ct_table); + case IPA_IOC_V4_INIT_NAT32: + cmd = IPA_IOC_V4_INIT_NAT; + break; + case IPA_IOC_INIT_IPV6CT_TABLE32: + cmd = IPA_IOC_INIT_IPV6CT_TABLE; + break; + case IPA_IOC_TABLE_DMA_CMD32: + cmd = IPA_IOC_TABLE_DMA_CMD; + break; + case IPA_IOC_V4_DEL_NAT32: + cmd = IPA_IOC_V4_DEL_NAT; + break; + case IPA_IOC_DEL_NAT_TABLE32: + cmd = IPA_IOC_DEL_NAT_TABLE; + break; + case IPA_IOC_DEL_IPV6CT_TABLE32: + cmd = IPA_IOC_DEL_IPV6CT_TABLE; + break; + case IPA_IOC_NAT_MODIFY_PDN32: + cmd = IPA_IOC_NAT_MODIFY_PDN; + break; + case IPA_IOC_GET_NAT_OFFSET32: + cmd = IPA_IOC_GET_NAT_OFFSET; + break; + case IPA_IOC_PULL_MSG32: + cmd = IPA_IOC_PULL_MSG; + break; + case IPA_IOC_RM_ADD_DEPENDENCY32: + cmd = IPA_IOC_RM_ADD_DEPENDENCY; + break; + case IPA_IOC_RM_DEL_DEPENDENCY32: + cmd = IPA_IOC_RM_DEL_DEPENDENCY; + break; + case IPA_IOC_GENERATE_FLT_EQ32: + cmd = IPA_IOC_GENERATE_FLT_EQ; + break; + case IPA_IOC_QUERY_RT_TBL_INDEX32: + cmd = IPA_IOC_QUERY_RT_TBL_INDEX; + break; + case IPA_IOC_WRITE_QMAPID32: + cmd = IPA_IOC_WRITE_QMAPID; + break; + case IPA_IOC_MDFY_FLT_RULE32: + cmd = IPA_IOC_MDFY_FLT_RULE; + break; + case IPA_IOC_NOTIFY_WAN_UPSTREAM_ROUTE_ADD32: + cmd = IPA_IOC_NOTIFY_WAN_UPSTREAM_ROUTE_ADD; + break; + case IPA_IOC_NOTIFY_WAN_UPSTREAM_ROUTE_DEL32: + cmd = IPA_IOC_NOTIFY_WAN_UPSTREAM_ROUTE_DEL; + break; + case IPA_IOC_NOTIFY_WAN_EMBMS_CONNECTED32: + cmd = IPA_IOC_NOTIFY_WAN_EMBMS_CONNECTED; + break; + case IPA_IOC_MDFY_RT_RULE32: + cmd = IPA_IOC_MDFY_RT_RULE; + break; + case IPA_IOC_GET_NAT_IN_SRAM_INFO32: + cmd = IPA_IOC_GET_NAT_IN_SRAM_INFO; + break; + case IPA_IOC_APP_CLOCK_VOTE32: + cmd = IPA_IOC_APP_CLOCK_VOTE; + break; + case IPA_IOC_ADD_EoGRE_MAPPING32: + cmd = IPA_IOC_ADD_EoGRE_MAPPING; + break; + case IPA_IOC_DEL_EoGRE_MAPPING32: + cmd = IPA_IOC_DEL_EoGRE_MAPPING; + break; + case IPA_IOC_SET_NAT_EXC_RT_TBL_IDX32: + cmd = IPA_IOC_SET_NAT_EXC_RT_TBL_IDX; + break; + case IPA_IOC_SET_CONN_TRACK_EXC_RT_TBL_IDX32: + cmd = IPA_IOC_SET_CONN_TRACK_EXC_RT_TBL_IDX; + break; + case IPA_IOC_COMMIT_HDR: + case IPA_IOC_RESET_HDR: + case IPA_IOC_COMMIT_RT: + case IPA_IOC_RESET_RT: + case IPA_IOC_COMMIT_FLT: + case IPA_IOC_RESET_FLT: + case IPA_IOC_DUMP: + case IPA_IOC_PUT_RT_TBL: + case IPA_IOC_PUT_HDR: + case IPA_IOC_SET_FLT: + case IPA_IOC_QUERY_EP_MAPPING: + break; + default: + return -ENOIOCTLCMD; + } + return ipa3_ioctl(file, cmd, (unsigned long) compat_ptr(arg)); +} +#endif + +static ssize_t ipa3_write(struct file *file, const char __user *buf, + size_t count, loff_t *ppos); + +static const struct file_operations ipa3_drv_fops = { + .owner = THIS_MODULE, + .open = ipa3_open, + .read = ipa3_read, + .write = ipa3_write, + .unlocked_ioctl = ipa3_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl = compat_ipa3_ioctl, +#endif +}; + +static int ipa3_get_clks(struct device *dev) +{ + if (!IPA_IS_REGULAR_CLK_MODE(ipa3_ctx->ipa3_hw_mode)) { + IPADBG("not supported in this HW mode\n"); + ipa3_clk = NULL; + return 0; + } + + if (ipa3_res.use_bw_vote) { + IPADBG("Vote IPA clock by bw voting via bus scaling driver\n"); + ipa3_clk = NULL; + return 0; + } + + ipa3_clk = clk_get(dev, "core_clk"); + if (IS_ERR(ipa3_clk)) { + if (ipa3_clk != ERR_PTR(-EPROBE_DEFER)) + IPAERR("fail to get ipa clk\n"); + return PTR_ERR(ipa3_clk); + } + return 0; +} + +/** + * _ipa_enable_clks_v3_0() - Enable IPA clocks. + */ +void _ipa_enable_clks_v3_0(void) +{ + IPADBG_LOW("curr_ipa_clk_rate=%d", ipa3_ctx->curr_ipa_clk_rate); + if (ipa3_clk) { + IPADBG_LOW("enabling gcc_ipa_clk\n"); + clk_prepare(ipa3_clk); + clk_enable(ipa3_clk); + clk_set_rate(ipa3_clk, ipa3_ctx->curr_ipa_clk_rate); + } + + ipa3_uc_notify_clk_state(true); +} + +static unsigned int ipa3_get_bus_vote(void) +{ + unsigned int idx = 1; + + if (ipa3_ctx->curr_ipa_clk_rate == ipa3_ctx->ctrl->ipa_clk_rate_svs2) { + idx = 1; + } else if (ipa3_ctx->curr_ipa_clk_rate == + ipa3_ctx->ctrl->ipa_clk_rate_svs) { + idx = 2; + } else if (ipa3_ctx->curr_ipa_clk_rate == + ipa3_ctx->ctrl->ipa_clk_rate_nominal) { + idx = 3; + } else if (ipa3_ctx->curr_ipa_clk_rate == + ipa3_ctx->ctrl->ipa_clk_rate_turbo) { + idx = 4; + } else { + WARN(1, "unexpected clock rate"); + } + IPADBG_LOW("curr %d idx %d\n", ipa3_ctx->curr_ipa_clk_rate, idx); + + return idx; +} + +/** + * ipa3_enable_clks() - Turn on IPA clocks + * + * Return codes: + * None + */ +void ipa3_enable_clks(void) +{ + int idx; + int i; + + if (!IPA_IS_REGULAR_CLK_MODE(ipa3_ctx->ipa3_hw_mode)) { + IPAERR("not supported in this mode\n"); + return; + } + + IPADBG("enabling IPA clocks and bus voting\n"); + + idx = ipa3_get_bus_vote(); + + IPADBG_CLK("IPA ICC Voting for BW Started\n"); + for (i = 0; i < ipa3_ctx->icc_num_paths; i++) { + if (ipa3_ctx->ctrl->icc_path[i] && + icc_set_bw( + ipa3_ctx->ctrl->icc_path[i], + ipa3_ctx->icc_clk[idx][i][IPA_ICC_AB], + ipa3_ctx->icc_clk[idx][i][IPA_ICC_IB])) + WARN(1, "path %d bus scaling failed", i); + IPADBG_CLK("IPA ICC Voting for BW %d Path Completed\n", i); + } + IPADBG_CLK("IPA ICC Voting for BW Finished\n"); + + IPADBG_CLK("Enabling IPA Clocks Started\n"); + ipa3_ctx->ctrl->ipa3_enable_clks(); + IPADBG_CLK("Enabling IPA Clocks Finished\n"); + atomic_set(&ipa3_ctx->ipa_clk_vote, 1); +} + + +/** + * _ipa_disable_clks_v3_0() - Disable IPA clocks. + */ +void _ipa_disable_clks_v3_0(void) +{ + ipa3_uc_notify_clk_state(false); + if (ipa3_clk) { + IPADBG_LOW("disabling gcc_ipa_clk\n"); + clk_disable_unprepare(ipa3_clk); + } +} + +/** + * ipa3_disable_clks() - Turn off IPA clocks + * + * Return codes: + * None + */ +void ipa3_disable_clks(void) +{ + int i; + int type; + + if (!IPA_IS_REGULAR_CLK_MODE(ipa3_ctx->ipa3_hw_mode)) { + IPAERR("not supported in this mode\n"); + return; + } + + IPADBG("disabling IPA clocks and bus voting\n"); + + /* + * We see a NoC error on GSI on this flag sequence. + * Need to set this flag first before clock off. + */ + atomic_set(&ipa3_ctx->ipa_clk_vote, 0); + + /* + * If there is still pending gsi irq, this indicate + * issue on GSI FW side. We need to capture before + * turn off the ipa clock. + */ + if (!ipa3_ctx->ipa_config_is_mhi || (ipa3_ctx->platform_type != IPA_PLAT_TYPE_XR)) { + type = gsi_pending_irq_type(); + if (type != -EPERM && type) { + IPAERR("unexpected gsi irq type: %d\n", type); + /* increase ipa3_active_clients for smp2p response */ + atomic_inc(&ipa3_ctx->ipa3_active_clients.cnt); + atomic_set(&ipa3_ctx->ipa_clk_vote, 1); + ipa_assert(); + } + } + + IPADBG_CLK("Disabling IPA Clocks Started\n"); + ipa3_ctx->ctrl->ipa3_disable_clks(); + IPADBG_CLK("Disabling IPA Clocks Finished\n"); + + ipa_pm_set_clock_index(0); + + IPADBG_CLK("IPA ICC Voting for BW Started\n"); + for (i = 0; i < ipa3_ctx->icc_num_paths; i++) { + if (ipa3_ctx->ctrl->icc_path[i] && + icc_set_bw( + ipa3_ctx->ctrl->icc_path[i], + ipa3_ctx->icc_clk[IPA_ICC_NONE][i][IPA_ICC_AB], + ipa3_ctx->icc_clk[IPA_ICC_NONE][i][IPA_ICC_IB])) + WARN(1, "path %d bus off failed", i); + IPADBG_CLK("IPA ICC Voting for BW %d Path Completed\n", i); + } + IPADBG_CLK("IPA ICC Voting for BW Finished\n"); + atomic_set(&ipa3_ctx->ipa_clk_vote, 0); +} + +/** + * ipa3_start_tag_process() - Send TAG packet and wait for it to come back + * + * This function is called prior to clock gating when active client counter + * is 1. TAG process ensures that there are no packets inside IPA HW that + * were not submitted to the IPA client via the transport. During TAG process + * all aggregation frames are (force) closed. + * + * Return codes: + * None + */ +static void ipa3_start_tag_process(struct work_struct *work) +{ + int res; + + IPADBG("starting TAG process\n"); + /* close aggregation frames on all pipes */ + res = ipa3_tag_aggr_force_close(-1); + if (res) + IPAERR("ipa3_tag_aggr_force_close failed %d\n", res); + IPA_ACTIVE_CLIENTS_DEC_SPECIAL("TAG_PROCESS"); + + IPADBG("TAG process done\n"); +} + +/** + * ipa3_active_clients_log_mod() - Log a modification in the active clients + * reference count + * + * This method logs any modification in the active clients reference count: + * It logs the modification in the circular history buffer + * It logs the modification in the hash table - looking for an entry, + * creating one if needed and deleting one if needed. + * + * @id: ipa3_active client logging info struct to hold the log information + * @inc: a boolean variable to indicate whether the modification is an increase + * or decrease + * @int_ctx: a boolean variable to indicate whether this call is being made from + * an interrupt context and therefore should allocate GFP_ATOMIC memory + * + * Method process: + * - Hash the unique identifier string + * - Find the hash in the table + * 1)If found, increase or decrease the reference count + * 2)If not found, allocate a new hash table entry struct and initialize it + * - Remove and deallocate unneeded data structure + * - Log the call in the circular history buffer (unless it is a simple call) + */ +#ifdef CONFIG_IPA_DEBUG +static void ipa3_active_clients_log_mod( + struct ipa_active_client_logging_info *id, + bool inc, bool int_ctx) +{ + char temp_str[IPA3_ACTIVE_CLIENTS_LOG_LINE_LEN]; + unsigned long long t; + unsigned long nanosec_rem; + struct ipa3_active_client_htable_entry *hentry; + struct ipa3_active_client_htable_entry *hfound; + u32 hkey; + char str_to_hash[IPA3_ACTIVE_CLIENTS_LOG_NAME_LEN]; + unsigned long flags; + + spin_lock_irqsave(&ipa3_ctx->ipa3_active_clients_logging.lock, flags); + int_ctx = true; + hfound = NULL; + memset(str_to_hash, 0, IPA3_ACTIVE_CLIENTS_LOG_NAME_LEN); + strlcpy(str_to_hash, id->id_string, IPA3_ACTIVE_CLIENTS_LOG_NAME_LEN); + hkey = jhash(str_to_hash, IPA3_ACTIVE_CLIENTS_LOG_NAME_LEN, + 0); + hash_for_each_possible(ipa3_ctx->ipa3_active_clients_logging.htable, + hentry, list, hkey) { + if (!strcmp(hentry->id_string, id->id_string)) { + hentry->count = hentry->count + (inc ? 1 : -1); + hfound = hentry; + } + } + if (hfound == NULL) { + hentry = NULL; + hentry = kzalloc(sizeof( + struct ipa3_active_client_htable_entry), + int_ctx ? GFP_ATOMIC : GFP_KERNEL); + if (hentry == NULL) { + spin_unlock_irqrestore( + &ipa3_ctx->ipa3_active_clients_logging.lock, + flags); + return; + } + hentry->type = id->type; + strlcpy(hentry->id_string, id->id_string, + IPA3_ACTIVE_CLIENTS_LOG_NAME_LEN); + INIT_HLIST_NODE(&hentry->list); + hentry->count = inc ? 1 : -1; + hash_add(ipa3_ctx->ipa3_active_clients_logging.htable, + &hentry->list, hkey); + } else if (hfound->count == 0) { + hash_del(&hfound->list); + kfree(hfound); + } + + if (id->type != SIMPLE) { + t = local_clock(); + nanosec_rem = do_div(t, 1000000000) / 1000; + snprintf(temp_str, IPA3_ACTIVE_CLIENTS_LOG_LINE_LEN, + inc ? "[%5lu.%06lu] ^ %s, %s: %d" : + "[%5lu.%06lu] v %s, %s: %d", + (unsigned long)t, nanosec_rem, + id->id_string, id->file, id->line); + ipa3_active_clients_log_insert(temp_str); + } + spin_unlock_irqrestore(&ipa3_ctx->ipa3_active_clients_logging.lock, + flags); +} +#else +static void ipa3_active_clients_log_mod( + struct ipa_active_client_logging_info *id, + bool inc, bool int_ctx) +{ +} +#endif + +void ipa3_active_clients_log_dec(struct ipa_active_client_logging_info *id, + bool int_ctx) +{ + ipa3_active_clients_log_mod(id, false, int_ctx); +} + +void ipa3_active_clients_log_inc(struct ipa_active_client_logging_info *id, + bool int_ctx) +{ + ipa3_active_clients_log_mod(id, true, int_ctx); +} + +/** + * ipa3_inc_client_enable_clks_no_log() - Increase active clients counter, and + * enable ipa clocks if necessary + * + * Return codes: + * None + */ +static void ipa3_inc_client_enable_clks_no_log(void) +{ + int ret; + + ret = atomic_inc_not_zero(&ipa3_ctx->ipa3_active_clients.cnt); + if (ret) { + IPADBG_LOW("active clients = %d\n", + atomic_read(&ipa3_ctx->ipa3_active_clients.cnt)); + return; + } + + mutex_lock(&ipa3_ctx->ipa3_active_clients.mutex); + + /* somebody might voted to clocks meanwhile */ + ret = atomic_inc_not_zero(&ipa3_ctx->ipa3_active_clients.cnt); + if (ret) { + mutex_unlock(&ipa3_ctx->ipa3_active_clients.mutex); + IPADBG_LOW("active clients = %d\n", + atomic_read(&ipa3_ctx->ipa3_active_clients.cnt)); + return; + } + + ipa3_enable_clks(); + ipa3_suspend_apps_pipes(false); + atomic_inc(&ipa3_ctx->ipa3_active_clients.cnt); + IPADBG_LOW("active clients = %d\n", + atomic_read(&ipa3_ctx->ipa3_active_clients.cnt)); + mutex_unlock(&ipa3_ctx->ipa3_active_clients.mutex); +} + +/** + * ipa3_inc_client_enable_clks() - Increase active clients counter and + * enable ipa clocks if necessary, log the caller + * + * Return codes: + * None + */ +void ipa3_inc_client_enable_clks(struct ipa_active_client_logging_info *id) +{ + ipa3_active_clients_log_inc(id, false); + ipa3_inc_client_enable_clks_no_log(); +} +EXPORT_SYMBOL(ipa3_inc_client_enable_clks); + +static void ipa3_handle_gsi_differ_irq(void) +{ + queue_work(ipa3_ctx->power_mgmt_wq, + &ipa_inc_clients_enable_clks_on_wq_work); +} + +/** + * ipa3_active_clks_status() - update the current msm bus clock vote + * status + */ +int ipa3_active_clks_status(void) +{ + return atomic_read(&ipa3_ctx->ipa_clk_vote); +} + +/** + * ipa3_inc_client_enable_clks_no_block() - Only increment the number of active + * clients if no asynchronous actions should be done. Asynchronous actions are + * locking a mutex and waking up IPA HW. + * + * Return codes: 0 for success + * -EPERM if an asynchronous action should have been done + */ +int ipa3_inc_client_enable_clks_no_block(struct ipa_active_client_logging_info + *id) +{ + int ret; + + ret = atomic_inc_not_zero(&ipa3_ctx->ipa3_active_clients.cnt); + if (ret) { + ipa3_active_clients_log_inc(id, true); + IPADBG_LOW("active clients = %d\n", + atomic_read(&ipa3_ctx->ipa3_active_clients.cnt)); + return 0; + } + + return -EPERM; +} +EXPORT_SYMBOL(ipa3_inc_client_enable_clks_no_block); + +static void __ipa3_dec_client_disable_clks(void) +{ + int ret; + + if (!atomic_read(&ipa3_ctx->ipa3_active_clients.cnt)) { + IPAERR("trying to disable clocks with refcnt is 0\n"); + ipa_assert(); + return; + } + + ret = atomic_add_unless(&ipa3_ctx->ipa3_active_clients.cnt, -1, 1); + if (ret) + goto bail; + + /* Send force close coalsecing frame command in LPM mode before taking + * mutex lock and otherwise observing race condition. + */ + if (atomic_read(&ipa3_ctx->ipa3_active_clients.cnt) == 1 && + !ipa3_ctx->tag_process_before_gating) { + ipa3_force_close_coal(true, true); + /* While sending force close command setting + * tag process as true to make configure to + * original state + */ + ipa3_ctx->tag_process_before_gating = false; + } + /* seems like this is the only client holding the clocks */ + mutex_lock(&ipa3_ctx->ipa3_active_clients.mutex); + if (atomic_read(&ipa3_ctx->ipa3_active_clients.cnt) == 1 && + ipa3_ctx->tag_process_before_gating) { + ipa3_ctx->tag_process_before_gating = false; + /* + * When TAG process ends, active clients will be + * decreased + */ + queue_work(ipa3_ctx->power_mgmt_wq, &ipa3_tag_work); + goto unlock_mutex; + } + + /* a different context might increase the clock reference meanwhile */ + ret = atomic_sub_return(1, &ipa3_ctx->ipa3_active_clients.cnt); + if (ret > 0) + goto unlock_mutex; + ret = ipa3_suspend_apps_pipes(true); + if (ret) { + /* HW is busy, retry after some time */ + atomic_inc(&ipa3_ctx->ipa3_active_clients.cnt); + queue_delayed_work(ipa3_ctx->power_mgmt_wq, + &ipa_dec_clients_disable_clks_on_wq_work, + IPA_SUSPEND_BUSY_TIMEOUT); + } else { + ipa3_disable_clks(); + } + +unlock_mutex: + mutex_unlock(&ipa3_ctx->ipa3_active_clients.mutex); +bail: + IPADBG_LOW("active clients = %d\n", + atomic_read(&ipa3_ctx->ipa3_active_clients.cnt)); +} + +/** + * ipa3_dec_client_disable_clks_no_log() - Decrease active clients counter + * + * In case that there are no active clients this function also starts + * TAG process. When TAG progress ends ipa clocks will be gated. + * start_tag_process_again flag is set during this function to signal TAG + * process to start again as there was another client that may send data to ipa + * + * Return codes: + * None + */ +static void ipa3_dec_client_disable_clks_no_log(void) +{ + __ipa3_dec_client_disable_clks(); +} + +/** + * ipa3_dec_client_disable_clks() - Decrease active clients counter and log caller + * + * In case that there are no active clients this function also starts + * TAG process. When TAG progress ends ipa clocks will be gated. + * start_tag_process_again flag is set during this function to signal TAG + * process to start again as there was another client that may send data to ipa + * + * Return codes: + * None + */ +void ipa3_dec_client_disable_clks(struct ipa_active_client_logging_info *id) +{ + ipa3_active_clients_log_dec(id, false); + __ipa3_dec_client_disable_clks(); +} +EXPORT_SYMBOL(ipa3_dec_client_disable_clks); + +static void ipa_dec_clients_disable_clks_on_wq(struct work_struct *work) +{ + __ipa3_dec_client_disable_clks(); +} + +static void ipa_inc_clients_enable_clks_on_wq(struct work_struct *work) +{ + ipa3_enable_clks(); + IPAERR("unexpected clk access, clock on IPA to save reg"); + ipa_assert(); +} + +/** + * ipa3_dec_client_disable_clks_no_block() - Decrease active clients counter + * if possible without blocking. If this is the last client then the desrease + * will happen from work queue context. + * + * Return codes: + * None + */ +void ipa3_dec_client_disable_clks_no_block( + struct ipa_active_client_logging_info *id) +{ + int ret; + + ipa3_active_clients_log_dec(id, true); + ret = atomic_add_unless(&ipa3_ctx->ipa3_active_clients.cnt, -1, 1); + if (ret) { + IPADBG_LOW("active clients = %d\n", + atomic_read(&ipa3_ctx->ipa3_active_clients.cnt)); + return; + } + + /* seems like this is the only client holding the clocks */ + queue_delayed_work(ipa3_ctx->power_mgmt_wq, + &ipa_dec_clients_disable_clks_on_wq_work, 0); +} + +/** + * ipa3_dec_client_disable_clks_delay_wq() - Decrease active clients counter + * in delayed workqueue. + * + * Return codes: + * None + */ +void ipa3_dec_client_disable_clks_delay_wq( + struct ipa_active_client_logging_info *id, unsigned long delay) +{ + ipa3_active_clients_log_dec(id, true); + + if (!queue_delayed_work(ipa3_ctx->power_mgmt_wq, + &ipa_dec_clients_disable_clks_on_suspend_irq_wq_work, delay)) { + IPAERR("Scheduling delayed work failed, disable clk\n"); + __ipa3_dec_client_disable_clks(); + } +} +/** + * ipa3_inc_acquire_wakelock() - Increase active clients counter, and + * acquire wakelock if necessary + * + * Return codes: + * None + */ +void ipa3_inc_acquire_wakelock(void) +{ + unsigned long flags; + + spin_lock_irqsave(&ipa3_ctx->wakelock_ref_cnt.spinlock, flags); + ipa3_ctx->wakelock_ref_cnt.cnt++; + if (ipa3_ctx->wakelock_ref_cnt.cnt == 1) + __pm_stay_awake(ipa3_ctx->w_lock); + IPADBG_LOW("active wakelock ref cnt = %d\n", + ipa3_ctx->wakelock_ref_cnt.cnt); + spin_unlock_irqrestore(&ipa3_ctx->wakelock_ref_cnt.spinlock, flags); +} + +/** + * ipa3_dec_release_wakelock() - Decrease active clients counter + * + * In case if the ref count is 0, release the wakelock. + * + * Return codes: + * None + */ +void ipa3_dec_release_wakelock(void) +{ + unsigned long flags; + + spin_lock_irqsave(&ipa3_ctx->wakelock_ref_cnt.spinlock, flags); + ipa3_ctx->wakelock_ref_cnt.cnt--; + IPADBG_LOW("active wakelock ref cnt = %d\n", + ipa3_ctx->wakelock_ref_cnt.cnt); + if (ipa3_ctx->wakelock_ref_cnt.cnt == 0) + __pm_relax(ipa3_ctx->w_lock); + spin_unlock_irqrestore(&ipa3_ctx->wakelock_ref_cnt.spinlock, flags); +} + +int ipa3_set_clock_plan_from_pm(int idx) +{ + u32 clk_rate; + int i; + + IPADBG_LOW("idx = %d\n", idx); + + if (!ipa3_ctx->enable_clock_scaling) { + ipa3_ctx->ipa3_active_clients.bus_vote_idx = idx; + return 0; + } + + if (!IPA_IS_REGULAR_CLK_MODE(ipa3_ctx->ipa3_hw_mode)) { + IPAERR("not supported in this mode\n"); + return 0; + } + + if (idx <= 0 || idx >= 5) { + IPAERR("bad voltage\n"); + return -EINVAL; + } + + if (idx == 1) + clk_rate = ipa3_ctx->ctrl->ipa_clk_rate_svs2; + else if (idx == 2) + clk_rate = ipa3_ctx->ctrl->ipa_clk_rate_svs; + else if (idx == 3) + clk_rate = ipa3_ctx->ctrl->ipa_clk_rate_nominal; + else if (idx == 4) + clk_rate = ipa3_ctx->ctrl->ipa_clk_rate_turbo; + else { + IPAERR("bad voltage\n"); + WARN_ON(1); + return -EFAULT; + } + + if (clk_rate == ipa3_ctx->curr_ipa_clk_rate) { + IPADBG_LOW("Same voltage\n"); + return 0; + } + + mutex_lock(&ipa3_ctx->ipa3_active_clients.mutex); + ipa3_ctx->curr_ipa_clk_rate = clk_rate; + ipa3_ctx->ipa3_active_clients.bus_vote_idx = idx; + IPADBG_LOW("setting clock rate to %u\n", ipa3_ctx->curr_ipa_clk_rate); + if (atomic_read(&ipa3_ctx->ipa3_active_clients.cnt) > 0) { + if (ipa3_clk) + clk_set_rate(ipa3_clk, ipa3_ctx->curr_ipa_clk_rate); + idx = ipa3_get_bus_vote(); + for (i = 0; i < ipa3_ctx->icc_num_paths; i++) { + if (ipa3_ctx->ctrl->icc_path[i] && + icc_set_bw( + ipa3_ctx->ctrl->icc_path[i], + ipa3_ctx->icc_clk[idx][i][IPA_ICC_AB], + ipa3_ctx->icc_clk[idx][i][IPA_ICC_IB])) { + WARN(1, "path %d bus scaling failed", + i); + } + } + } else { + IPADBG_LOW("clocks are gated, not setting rate\n"); + } + mutex_unlock(&ipa3_ctx->ipa3_active_clients.mutex); + IPADBG_LOW("Done\n"); + + return 0; +} + +int ipa3_set_required_perf_profile(enum ipa_voltage_level floor_voltage, + u32 bandwidth_mbps) +{ + enum ipa_voltage_level needed_voltage; + u32 clk_rate; + int i; + int idx; + + if (!IPA_IS_REGULAR_CLK_MODE(ipa3_ctx->ipa3_hw_mode)) { + IPAERR("not supported in this mode\n"); + return 0; + } + + IPADBG_LOW("floor_voltage=%d, bandwidth_mbps=%u", + floor_voltage, bandwidth_mbps); + + if (floor_voltage < IPA_VOLTAGE_UNSPECIFIED || + floor_voltage >= IPA_VOLTAGE_MAX) { + IPAERR("bad voltage\n"); + return -EINVAL; + } + + if (ipa3_ctx->enable_clock_scaling) { + IPADBG_LOW("Clock scaling is enabled\n"); + if (bandwidth_mbps >= + ipa3_ctx->ctrl->clock_scaling_bw_threshold_turbo) + needed_voltage = IPA_VOLTAGE_TURBO; + else if (bandwidth_mbps >= + ipa3_ctx->ctrl->clock_scaling_bw_threshold_nominal) + needed_voltage = IPA_VOLTAGE_NOMINAL; + else if (bandwidth_mbps >= + ipa3_ctx->ctrl->clock_scaling_bw_threshold_svs) + needed_voltage = IPA_VOLTAGE_SVS; + else + needed_voltage = IPA_VOLTAGE_SVS2; + } else { + IPADBG_LOW("Clock scaling is disabled\n"); + needed_voltage = IPA_VOLTAGE_NOMINAL; + } + + needed_voltage = max(needed_voltage, floor_voltage); + switch (needed_voltage) { + case IPA_VOLTAGE_SVS2: + clk_rate = ipa3_ctx->ctrl->ipa_clk_rate_svs2; + break; + case IPA_VOLTAGE_SVS: + clk_rate = ipa3_ctx->ctrl->ipa_clk_rate_svs; + break; + case IPA_VOLTAGE_NOMINAL: + clk_rate = ipa3_ctx->ctrl->ipa_clk_rate_nominal; + break; + case IPA_VOLTAGE_TURBO: + clk_rate = ipa3_ctx->ctrl->ipa_clk_rate_turbo; + break; + default: + IPAERR("bad voltage\n"); + WARN_ON(1); + return -EFAULT; + } + + if (clk_rate == ipa3_ctx->curr_ipa_clk_rate) { + IPADBG_LOW("Same voltage\n"); + return 0; + } + + /* Hold the mutex to avoid race conditions with ipa3_enable_clocks() */ + mutex_lock(&ipa3_ctx->ipa3_active_clients.mutex); + ipa3_ctx->curr_ipa_clk_rate = clk_rate; + IPADBG_LOW("setting clock rate to %u\n", ipa3_ctx->curr_ipa_clk_rate); + if (atomic_read(&ipa3_ctx->ipa3_active_clients.cnt) > 0) { + if (ipa3_clk) + clk_set_rate(ipa3_clk, ipa3_ctx->curr_ipa_clk_rate); + idx = ipa3_get_bus_vote(); + for (i = 0; i < ipa3_ctx->icc_num_paths; i++) { + if (ipa3_ctx->ctrl->icc_path[i] && + icc_set_bw( + ipa3_ctx->ctrl->icc_path[i], + ipa3_ctx->icc_clk[idx][i][IPA_ICC_AB], + ipa3_ctx->icc_clk[idx][i][IPA_ICC_IB])) + WARN(1, "path %d bus scaling failed", i); + } + } else { + IPADBG_LOW("clocks are gated, not setting rate\n"); + } + mutex_unlock(&ipa3_ctx->ipa3_active_clients.mutex); + IPADBG_LOW("Done\n"); + + return 0; +} +EXPORT_SYMBOL(ipa3_set_required_perf_profile); + +static void ipa3_process_irq_schedule_rel(void) +{ + queue_delayed_work(ipa3_ctx->transport_power_mgmt_wq, + &ipa3_transport_release_resource_work, + msecs_to_jiffies(IPA_TRANSPORT_PROD_TIMEOUT_MSEC)); +} + +/** + * ipa3_suspend_handler() - Handles the suspend interrupt: + * wakes up the suspended peripheral by requesting its consumer + * @interrupt: Interrupt type + * @private_data: The client's private data + * @interrupt_data: Interrupt specific information data + */ +void ipa3_suspend_handler(enum ipa_irq_type interrupt, + void *private_data, + void *interrupt_data) +{ + u32 *suspend_data = + ((struct ipa_tx_suspend_irq_data *)interrupt_data)->endpoints; + u32 bmsk = 1; + u32 i = 0, j = 0, ep_arr_size, ep_per_reg; + int res; + u32 pipe_bitmask = 0; + + IPADBG("interrupt=%d\n", interrupt); + + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0) { + ep_arr_size = IPA_EP_ARR_SIZE; + ep_per_reg = IPA_EP_PER_REG; + } else { + ep_arr_size = 1; + ep_per_reg = ipa3_ctx->ipa_num_pipes; + } + + j = 0; + for (i = 0; i < ipa3_ctx->ipa_num_pipes && j < ep_arr_size; i++) { + if ((suspend_data[j] & bmsk) && (ipa3_ctx->ep[i].valid)) + pipe_bitmask |= bmsk; + bmsk = bmsk << 1; + + if ((i % IPA_EP_PER_REG) == (ep_per_reg - 1) + || (i == ipa3_ctx->ipa_num_pipes - 1)) { + IPADBG("interrupt data: %u\n", suspend_data[j]); + res = ipa_pm_handle_suspend(pipe_bitmask, j); + if (res) { + IPAERR( + "ipa_pm_handle_suspend failed %d\n", res); + return; + } + pipe_bitmask = 0; + bmsk = 1; + j++; + } + } +} + +/** + * ipa_restore_suspend_handler() - restores the original suspend IRQ handler + * as it was registered in the IPA init sequence. + * Return codes: + * 0: success + * -EPERM: failed to remove current handler or failed to add original handler + */ +int ipa_restore_suspend_handler(void) +{ + int result = 0; + + result = ipa3_remove_interrupt_handler(IPA_TX_SUSPEND_IRQ); + if (result) { + IPAERR("remove handler for suspend interrupt failed\n"); + return -EPERM; + } + + result = ipa_add_interrupt_handler(IPA_TX_SUSPEND_IRQ, + ipa3_suspend_handler, false, NULL); + if (result) { + IPAERR("register handler for suspend interrupt failed\n"); + result = -EPERM; + } + + IPADBG("suspend handler successfully restored\n"); + + return result; +} +EXPORT_SYMBOL(ipa_restore_suspend_handler); + +static void ipa3_transport_release_resource(struct work_struct *work) +{ + mutex_lock(&ipa3_ctx->transport_pm.transport_pm_mutex); + /* check whether still need to decrease client usage */ + if (atomic_read(&ipa3_ctx->transport_pm.dec_clients)) { + if (atomic_read(&ipa3_ctx->transport_pm.eot_activity)) { + IPADBG("EOT pending Re-scheduling\n"); + ipa3_process_irq_schedule_rel(); + } else { + atomic_set(&ipa3_ctx->transport_pm.dec_clients, 0); + ipa3_dec_release_wakelock(); + IPA_ACTIVE_CLIENTS_DEC_SPECIAL("TRANSPORT_RESOURCE"); + } + } + atomic_set(&ipa3_ctx->transport_pm.eot_activity, 0); + mutex_unlock(&ipa3_ctx->transport_pm.transport_pm_mutex); +} + +/** + * ipa3_init_interrupts() - Register to IPA IRQs + * + * Return codes: 0 in success, negative in failure + * + */ +int ipa3_init_interrupts(void) +{ + int result; + + /*register IPA IRQ handler*/ + result = ipa3_interrupts_init(ipa3_res.ipa_irq, 0, + &ipa3_ctx->master_pdev->dev); + if (result) { + IPAERR("ipa interrupts initialization failed\n"); + return -ENODEV; + } + + /*add handler for suspend interrupt*/ + result = ipa_add_interrupt_handler(IPA_TX_SUSPEND_IRQ, + ipa3_suspend_handler, false, NULL); + if (result) { + IPAERR("register handler for suspend interrupt failed\n"); + result = -ENODEV; + goto fail_add_interrupt_handler; + } + + return 0; + +fail_add_interrupt_handler: + ipa3_interrupts_destroy(ipa3_res.ipa_irq, &ipa3_ctx->master_pdev->dev); + return result; +} + +/** + * ipa3_destroy_flt_tbl_idrs() - destroy the idr structure for flt tables + * The idr strcuture per filtering table is intended for rule id generation + * per filtering rule. + */ +static void ipa3_destroy_flt_tbl_idrs(void) +{ + int i; + struct ipa3_flt_tbl *flt_tbl; + + idr_destroy(&ipa3_ctx->flt_rule_ids[IPA_IP_v4]); + idr_destroy(&ipa3_ctx->flt_rule_ids[IPA_IP_v6]); + + for (i = 0; i < ipa3_ctx->ipa_num_pipes; i++) { + if (!ipa_is_ep_support_flt(i)) + continue; + + flt_tbl = &ipa3_ctx->flt_tbl[i][IPA_IP_v4]; + flt_tbl->rule_ids = NULL; + flt_tbl = &ipa3_ctx->flt_tbl[i][IPA_IP_v6]; + flt_tbl->rule_ids = NULL; + } +} + +static void ipa3_freeze_clock_vote_and_notify_modem(void) +{ + int res; + struct ipa_active_client_logging_info log_info; + + if (ipa3_ctx->platform_type == IPA_PLAT_TYPE_APQ || + ipa3_ctx->platform_type == IPA_PLAT_TYPE_XR) { + IPADBG("Ignore smp2p on APQ platform\n"); + return; + } + + if (ipa3_ctx->smp2p_info.res_sent) + return; + + if (IS_ERR(ipa3_ctx->smp2p_info.smem_state)) { + IPAERR("fail to get smp2p clk resp bit %ld\n", + PTR_ERR(ipa3_ctx->smp2p_info.smem_state)); + return; + } + + IPA_ACTIVE_CLIENTS_PREP_SPECIAL(log_info, "FREEZE_VOTE"); + res = ipa3_inc_client_enable_clks_no_block(&log_info); + if (res) + ipa3_ctx->smp2p_info.ipa_clk_on = false; + else + ipa3_ctx->smp2p_info.ipa_clk_on = true; + + qcom_smem_state_update_bits(ipa3_ctx->smp2p_info.smem_state, + IPA_SMP2P_SMEM_STATE_MASK, + ((ipa3_ctx->smp2p_info.ipa_clk_on << + IPA_SMP2P_OUT_CLK_VOTE_IDX) | + (1 << IPA_SMP2P_OUT_CLK_RSP_CMPLT_IDX))); + + ipa3_ctx->smp2p_info.res_sent = true; + IPADBG("IPA clocks are %s\n", + ipa3_ctx->smp2p_info.ipa_clk_on ? "ON" : "OFF"); +} + +void ipa3_reset_freeze_vote(void) +{ + if (!ipa3_ctx->smp2p_info.res_sent) + return; + + if (ipa3_ctx->smp2p_info.ipa_clk_on) + IPA_ACTIVE_CLIENTS_DEC_SPECIAL("FREEZE_VOTE"); + + qcom_smem_state_update_bits(ipa3_ctx->smp2p_info.smem_state, + IPA_SMP2P_SMEM_STATE_MASK, + ((0 << + IPA_SMP2P_OUT_CLK_VOTE_IDX) | + (0 << IPA_SMP2P_OUT_CLK_RSP_CMPLT_IDX))); + + ipa3_ctx->smp2p_info.res_sent = false; + ipa3_ctx->smp2p_info.ipa_clk_on = false; +} + +static int ipa3_panic_notifier(struct notifier_block *this, + unsigned long event, void *ptr) +{ + int res; + struct ipa_active_client_logging_info log_info; + + if (ipa3_ctx != NULL) + { + if (ipa3_ctx->is_device_crashed) + return NOTIFY_DONE; + ipa3_ctx->is_device_crashed = true; + } + + ipa3_freeze_clock_vote_and_notify_modem(); + + IPADBG("Calling uC panic handler\n"); + res = ipa3_uc_panic_notifier(this, event, ptr); + if (res) + IPAERR("uC panic handler failed %d\n", res); + + /* Make sure IPA clock voted when collecting the reg dump */ + IPA_ACTIVE_CLIENTS_PREP_SPECIAL(log_info, "PANIC_VOTE"); + res = ipa3_inc_client_enable_clks_no_block(&log_info); + if (!ipa3_active_clks_status()) { + IPAERR("IPA clk off not saving the IPA registers\n"); + } else { + /*make sure clock won't disable in middle of save reg*/ + if (res) { + IPADBG("IPA resume in progress increment clinet cnt\n"); + atomic_inc(&ipa3_ctx->ipa3_active_clients.cnt); + } + ipa_save_registers(); + ipahal_print_all_regs(false); + ipa_wigig_save_regs(); + if (res) { + IPADBG("IPA resume in progress decrement clinet cnt\n"); + atomic_dec(&ipa3_ctx->ipa3_active_clients.cnt); + } + } + + ipa3_active_clients_log_print_table(active_clients_table_buf, + IPA3_ACTIVE_CLIENTS_TABLE_BUF_SIZE); + IPAERR("%s\n", active_clients_table_buf); + + return NOTIFY_DONE; +} + +static struct notifier_block ipa3_panic_blk = { + .notifier_call = ipa3_panic_notifier, + /* IPA panic handler needs to run before modem shuts down */ + .priority = INT_MAX, +}; + +static void ipa3_register_panic_hdlr(void) +{ + atomic_notifier_chain_register(&panic_notifier_list, + &ipa3_panic_blk); +} + +static void ipa3_uc_is_loaded(void) +{ + IPADBG("\n"); + complete_all(&ipa3_ctx->uc_loaded_completion_obj); +} + +static enum gsi_ver ipa3_get_gsi_ver(enum ipa_hw_type ipa_hw_type) +{ + enum gsi_ver gsi_ver; + + switch (ipa_hw_type) { + case IPA_HW_v3_0: + case IPA_HW_v3_1: + gsi_ver = GSI_VER_1_0; + break; + case IPA_HW_v3_5: + gsi_ver = GSI_VER_1_2; + break; + case IPA_HW_v3_5_1: + gsi_ver = GSI_VER_1_3; + break; + case IPA_HW_v4_0: + case IPA_HW_v4_1: + gsi_ver = GSI_VER_2_0; + break; + case IPA_HW_v4_2: + gsi_ver = GSI_VER_2_2; + break; + case IPA_HW_v4_5: + gsi_ver = GSI_VER_2_5; + break; + case IPA_HW_v4_7: + gsi_ver = GSI_VER_2_7; + break; + case IPA_HW_v4_9: + gsi_ver = GSI_VER_2_9; + break; + case IPA_HW_v4_11: + gsi_ver = GSI_VER_2_11; + break; + case IPA_HW_v5_0: + case IPA_HW_v5_1: + gsi_ver = GSI_VER_3_0; + break; + case IPA_HW_v5_2: + gsi_ver = GSI_VER_5_2; + break; + case IPA_HW_v5_5: + gsi_ver = GSI_VER_5_5; + break; + default: + IPAERR("No GSI version for ipa type %d\n", ipa_hw_type); + WARN_ON(1); + gsi_ver = GSI_VER_ERR; + } + + IPADBG("GSI version %d\n", gsi_ver); + + return gsi_ver; +} + +static int ipa3_gsi_pre_fw_load_init(void) +{ + int result; + + result = gsi_configure_regs( + ipa3_res.ipa_mem_base, + ipa3_ctx->gsi_ver); + + if (result) { + IPAERR("Failed to configure GSI registers\n"); + return -EINVAL; + } + + return 0; +} + +static int ipa3_alloc_gsi_channel(void) +{ + const struct ipa_gsi_ep_config *gsi_ep_cfg; + enum ipa_client_type type; + int code = 0; + int ret = 0; + int i; + + for (i = 0; i < ipa3_ctx->ipa_num_pipes; i++) { + type = ipa3_get_client_by_pipe(i); + gsi_ep_cfg = ipa_get_gsi_ep_info(type); + IPADBG("for ep %d client is %d\n", i, type); + if (!gsi_ep_cfg) + continue; + + ret = gsi_alloc_channel_ee(gsi_ep_cfg->ipa_gsi_chan_num, + gsi_ep_cfg->ee, &code); + if (ret == GSI_STATUS_SUCCESS) { + IPADBG("alloc gsi ch %d ee %d with code %d\n", + gsi_ep_cfg->ipa_gsi_chan_num, + gsi_ep_cfg->ee, + code); + } else { + IPAERR("failed to alloc ch %d ee %d code %d\n", + gsi_ep_cfg->ipa_gsi_chan_num, + gsi_ep_cfg->ee, + code); + return ret; + } + } + return ret; +} + +static inline void ipa3_enable_napi_lan_rx(void) +{ + if (ipa3_ctx->lan_rx_napi_enable) + napi_enable(&ipa3_ctx->napi_lan_rx); +} + +static inline void ipa3_disable_napi_lan_rx(void) +{ + if (ipa3_ctx->lan_rx_napi_enable) + napi_disable(&ipa3_ctx->napi_lan_rx); +} + +static inline void ipa_trigger_ipa_ready_cbs(void) +{ + struct ipa_ready_cb_info *info; + struct ipa_ready_cb_info *next; + + /* Call all the CBs */ + list_for_each_entry_safe(info, next, + &ipa3_ctx->ipa_ready_cb_list, link) { + if (info->ready_cb) + info->ready_cb(info->user_data); + + list_del(&info->link); + kfree(info); + } +} + +int ipa_register_ipa_ready_cb(void(*ipa_ready_cb)(void *user_data), + void *user_data) +{ + struct ipa_ready_cb_info *cb_info = NULL; + + if (!ipa3_ctx) { + IPAERR("ipa framework hasn't been initialized yet\n"); + return -EPERM; + } + + mutex_lock(&ipa3_ctx->lock); + if (ipa3_ctx->ipa_initialization_complete) { + IPADBG("IPA driver finished initialization already\n"); + mutex_unlock(&ipa3_ctx->lock); + return -EEXIST; + } + + cb_info = kmalloc(sizeof(struct ipa_ready_cb_info), GFP_KERNEL); + if (!cb_info) { + mutex_unlock(&ipa3_ctx->lock); + return -ENOMEM; + } + + cb_info->ready_cb = ipa_ready_cb; + cb_info->user_data = user_data; + + list_add_tail(&cb_info->link, &ipa3_ctx->ipa_ready_cb_list); + mutex_unlock(&ipa3_ctx->lock); + + return 0; +} +EXPORT_SYMBOL(ipa_register_ipa_ready_cb); + +void ipa3_notify_clients_registered(void) +{ + mutex_lock(&ipa3_ctx->lock); + ipa3_ctx->clients_registered = true; + mutex_unlock(&ipa3_ctx->lock); +} +EXPORT_SYMBOL(ipa3_notify_clients_registered); + +static void ipa_gsi_map_unmap_gsi_msi_addr(bool map) +{ + struct ipa_smmu_cb_ctx *cb; + u64 rounddown_addr; + int res; + int prot = IOMMU_READ | IOMMU_WRITE | IOMMU_MMIO; + + cb = ipa3_get_smmu_ctx(IPA_SMMU_CB_AP); + rounddown_addr = rounddown(ipa3_ctx->gsi_msi_addr, PAGE_SIZE); + if (map) { + res = ipa3_iommu_map(cb->iommu_domain, + rounddown_addr, rounddown_addr, PAGE_SIZE, prot); + if (res) { + IPAERR("iommu mapping failed for gsi_msi_addr\n"); + ipa_assert(); + } + } else { + res = iommu_unmap(cb->iommu_domain, rounddown_addr, PAGE_SIZE); + if (res) + IPAERR("smmu unmap for gsi_msi_addr failed %d\n", res); + } +} + + +/** + * ipa3_post_init() - Initialize the IPA Driver (Part II). + * This part contains all initialization which requires interaction with + * IPA HW (via GSI). + * + * @resource_p: contain platform specific values from DST file + * @pdev: The platform device structure representing the IPA driver + * + * Function initialization process: + * - Initialize endpoints bitmaps + * - Initialize resource groups min and max values + * - Initialize filtering lists heads and idr + * - Initialize interrupts + * - Register GSI + * - Setup APPS pipes + * - Initialize tethering bridge + * - Initialize IPA debugfs + * - Initialize IPA uC interface + * - Initialize WDI interface + * - Initialize USB interface + * - Register for panic handler + * - Trigger IPA ready callbacks (to all subscribers) + * - Trigger IPA completion object (to all who wait on it) + */ +static int ipa3_post_init(const struct ipa3_plat_drv_res *resource_p, + struct device *ipa_dev) +{ + int result; + struct gsi_per_props gsi_props; + struct ipa3_uc_hdlrs uc_hdlrs = { 0 }; + struct ipa3_flt_tbl *flt_tbl; + struct ipa3_flt_tbl_nhash_lcl *lcl_tbl; + int i; + struct idr *idr; + enum ipa_ip_type ip; +#if IS_ENABLED(CONFIG_QCOM_VA_MINIDUMP) + struct ipa_minidump_data *mini_dump; +#endif + + if (ipa3_ctx == NULL) { + IPADBG("IPA driver haven't initialized\n"); + return -ENXIO; + } + + /* Prevent consequent calls from trying to load the FW again. */ + if (ipa3_ctx->ipa_initialization_complete) + return 0; + + IPADBG("active clients = %d\n", + atomic_read(&ipa3_ctx->ipa3_active_clients.cnt)); + /* move proxy vote for modem on ipa3_post_init */ + if (ipa3_ctx->ipa_hw_type != IPA_HW_v4_0) + ipa3_proxy_clk_vote(false); + + /* The following will retrieve and save the gsi fw version */ + ipa_save_gsi_ver(); + + /* + * IPA version 3.0 IPAHAL initialized at pre_init as there is no SMMU. + * In normal mode need to wait until SMMU is attached and + * thus initialization done here + */ + if (ipa3_ctx->ipa_hw_type != IPA_HW_v3_0) { + if (ipahal_init(ipa3_ctx->ipa_hw_type, ipa3_ctx->mmio, + ipa3_ctx->ipa_cfg_offset, ipa3_ctx->pdev)) { + IPAERR("fail to init ipahal\n"); + result = -EFAULT; + goto fail_ipahal; + } + } + + result = ipa3_init_hw(); + if (result) { + IPAERR(":error initializing HW\n"); + result = -ENODEV; + goto fail_init_hw; + } + IPADBG("IPA HW initialization sequence completed"); + + ipa3_ctx->ipa_num_pipes = ipa3_get_num_pipes(); + IPADBG("IPA Pipes num %u\n", ipa3_ctx->ipa_num_pipes); + if (ipa3_ctx->ipa_num_pipes > IPA5_MAX_NUM_PIPES) { + IPAERR("IPA has more pipes then supported has %d, max %d\n", + ipa3_ctx->ipa_num_pipes, IPA5_MAX_NUM_PIPES); + result = -ENODEV; + goto fail_init_hw; + } + + ipa3_ctx->ctrl->ipa_sram_read_settings(); + IPADBG("SRAM, size: 0x%x, restricted bytes: 0x%x\n", + ipa3_ctx->smem_sz, ipa3_ctx->smem_restricted_bytes); + + IPADBG("ip4_rt_hash=%u ip4_rt_nonhash=%u\n", + ipa3_ctx->rt_tbl_hash_lcl[IPA_IP_v4], ipa3_ctx->rt_tbl_nhash_lcl[IPA_IP_v4]); + + IPADBG("ip6_rt_hash=%u ip6_rt_nonhash=%u\n", + ipa3_ctx->rt_tbl_hash_lcl[IPA_IP_v6], ipa3_ctx->rt_tbl_nhash_lcl[IPA_IP_v6]); + + IPADBG("ip4_flt_hash=%u ip4_flt_nonhash=%u\n", + ipa3_ctx->flt_tbl_hash_lcl[IPA_IP_v4], + ipa3_ctx->flt_tbl_nhash_lcl[IPA_IP_v4]); + + IPADBG("ip6_flt_hash=%u ip6_flt_nonhash=%u\n", + ipa3_ctx->flt_tbl_hash_lcl[IPA_IP_v6], + ipa3_ctx->flt_tbl_nhash_lcl[IPA_IP_v6]); + + if (ipa3_ctx->smem_reqd_sz > ipa3_ctx->smem_sz) { + IPAERR("SW expect more core memory, needed %d, avail %d\n", + ipa3_ctx->smem_reqd_sz, ipa3_ctx->smem_sz); + result = -ENOMEM; + goto fail_init_hw; + } + + result = ipa3_allocate_dma_task_for_gsi(); + if (result) { + IPAERR("failed to allocate dma task\n"); + goto fail_dma_task; + } + + result = ipa3_allocate_coal_close_frame(); + if (result) { + IPAERR("failed to allocate coal frame cmd\n"); + goto fail_coal_frame; + } + + if (ipa3_nat_ipv6ct_init_devices()) { + IPAERR("unable to init NAT and IPv6CT devices\n"); + result = -ENODEV; + goto fail_nat_ipv6ct_init_dev; + } + + result = ipa3_alloc_pkt_init(); + if (result) { + IPAERR("Failed to alloc pkt_init payload\n"); + result = -ENODEV; + goto fail_alloc_pkt_init; + } + + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0) { + result = ipa_alloc_pkt_init_ex(); + if (result) { + IPAERR("Failed to alloc pkt_init_ex payload\n"); + result = -ENODEV; + goto fail_alloc_pkt_init_ex; + } + } + + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v3_5) + ipa3_enable_dcd(); + + /* + * indication whether working in MHI config or non MHI config is given + * in ipa3_write which is launched before ipa3_post_init. i.e. from + * this point it is safe to use ipa3_ep_mapping array and the correct + * entry will be returned from ipa3_get_hw_type_index() + */ + ipa_init_ep_flt_bitmap(); + IPADBG("EP with flt support bitmap 0x%llx (%u pipes)\n", + ipa3_ctx->ep_flt_bitmap, ipa3_ctx->ep_flt_num); + + /* Assign resource limitation to each group */ + ipa3_set_resorce_groups_min_max_limits(); + + /* Initialize general resource group parameters */ + ipa3_set_resorce_groups_config(); + + idr = &(ipa3_ctx->flt_rule_ids[IPA_IP_v4]); + idr_init(idr); + idr = &(ipa3_ctx->flt_rule_ids[IPA_IP_v6]); + idr_init(idr); + + INIT_LIST_HEAD(&ipa3_ctx->flt_tbl_nhash_lcl_list[IPA_IP_v4]); + INIT_LIST_HEAD(&ipa3_ctx->flt_tbl_nhash_lcl_list[IPA_IP_v6]); + + for (i = 0; i < ipa3_ctx->ipa_num_pipes; i++) { + if (!ipa_is_ep_support_flt(i)) + continue; + + for (ip = IPA_IP_v4; ip < IPA_IP_MAX; ip++) { + flt_tbl = &ipa3_ctx->flt_tbl[i][ip]; + INIT_LIST_HEAD(&flt_tbl->head_flt_rule_list); + flt_tbl->in_sys[IPA_RULE_HASHABLE] = !ipa3_ctx->flt_tbl_hash_lcl[ip]; + + /* For ETH client place Non-Hash FLT table in SRAM if allowed, for + all other EPs always place the table in DDR */ + if (ipa3_ctx->flt_tbl_nhash_lcl[ip] && + (IPA_CLIENT_IS_ETH_PROD(i) || + ((ipa3_ctx->ipa3_hw_mode == IPA_HW_MODE_TEST) && + (i == ipa_get_ep_mapping(IPA_CLIENT_TEST_PROD))))) { + flt_tbl->in_sys[IPA_RULE_NON_HASHABLE] = false; + lcl_tbl = kcalloc(1, sizeof(struct ipa3_flt_tbl_nhash_lcl), + GFP_KERNEL); + WARN_ON(lcl_tbl); + if (likely(lcl_tbl)) { + lcl_tbl->tbl = flt_tbl; + /* Add to the head of the list, to be pulled first */ + list_add(&lcl_tbl->link, + &ipa3_ctx->flt_tbl_nhash_lcl_list[ip]); + } + } else + flt_tbl->in_sys[IPA_RULE_NON_HASHABLE] = true; + + /* Init force sys to false */ + flt_tbl->force_sys[IPA_RULE_HASHABLE] = false; + flt_tbl->force_sys[IPA_RULE_NON_HASHABLE] = false; + + flt_tbl->rule_ids = &ipa3_ctx->flt_rule_ids[ip]; + } + } + + if (!ipa3_ctx->apply_rg10_wa) { + result = ipa3_init_interrupts(); + if (result) { + IPAERR("ipa initialization of interrupts failed\n"); + result = -ENODEV; + goto fail_init_interrupts; + } + } else { + IPADBG("Initialization of ipa interrupts skipped\n"); + } + + /* + * Disable prefetch for USB or MHI at IPAv3.5/IPA.3.5.1 + * This is to allow MBIM to work. + */ + if ((ipa3_ctx->ipa_hw_type >= IPA_HW_v3_5 + && ipa3_ctx->ipa_hw_type < IPA_HW_v4_0) && + (!ipa3_ctx->ipa_config_is_mhi)) + ipa3_disable_prefetch(IPA_CLIENT_USB_CONS); + + if ((ipa3_ctx->ipa_hw_type >= IPA_HW_v3_5 + && ipa3_ctx->ipa_hw_type < IPA_HW_v4_0) && + (ipa3_ctx->ipa_config_is_mhi)) + ipa3_disable_prefetch(IPA_CLIENT_MHI_CONS); + + memset(&gsi_props, 0, sizeof(gsi_props)); + gsi_props.ver = ipa3_ctx->gsi_ver; + gsi_props.ee = resource_p->ee; + gsi_props.intr = GSI_INTR_IRQ; + gsi_props.phys_addr = resource_p->transport_mem_base; + gsi_props.size = resource_p->transport_mem_size; + if (ipa3_ctx->ipa3_hw_mode == IPA_HW_MODE_EMULATION) { + gsi_props.irq = resource_p->emulator_irq; + gsi_props.emulator_intcntrlr_client_isr = ipa3_get_isr(); + gsi_props.emulator_intcntrlr_addr = + resource_p->emulator_intcntrlr_mem_base; + gsi_props.emulator_intcntrlr_size = + resource_p->emulator_intcntrlr_mem_size; + } else { + gsi_props.irq = resource_p->transport_irq; + } + gsi_props.notify_cb = ipa_gsi_notify_cb; + gsi_props.req_clk_cb = NULL; + gsi_props.rel_clk_cb = NULL; + gsi_props.clk_status_cb = ipa3_active_clks_status; + gsi_props.enable_clk_bug_on = ipa3_handle_gsi_differ_irq; + gsi_props.vote_clk_cb = ipa3_inc_client_enable_clks_no_log; + gsi_props.unvote_clk_cb = ipa3_dec_client_disable_clks_no_log; + + if (ipa3_ctx->ipa_config_is_mhi) { + gsi_props.mhi_er_id_limits_valid = true; + gsi_props.mhi_er_id_limits[0] = resource_p->mhi_evid_limits[0]; + gsi_props.mhi_er_id_limits[1] = resource_p->mhi_evid_limits[1]; + } + gsi_props.skip_ieob_mask_wa = resource_p->skip_ieob_mask_wa; + gsi_props.tx_poll = resource_p->tx_poll; + + result = gsi_register_device(&gsi_props, + &ipa3_ctx->gsi_dev_hdl); + if (result != GSI_STATUS_SUCCESS) { + IPAERR(":gsi register error - %d\n", result); + result = -ENODEV; + goto fail_register_device; + } + IPADBG("IPA gsi is registered\n"); + /* GSI 2.2 requires to allocate all EE GSI channel + * during device bootup. + */ + if (gsi_props.ver == GSI_VER_2_2) { + result = ipa3_alloc_gsi_channel(); + if (result) { + IPAERR("Failed to alloc the GSI channels\n"); + result = -ENODEV; + goto fail_alloc_gsi_channel; + } + } + + ipa3_enable_napi_lan_rx(); + /* setup the AP-IPA pipes */ + if (ipa3_setup_apps_pipes()) { + IPAERR(":failed to setup IPA-Apps pipes\n"); + result = -ENODEV; + goto fail_setup_apps_pipes; + } + IPADBG("IPA GPI pipes were connected\n"); + + if (ipa3_ctx->use_ipa_teth_bridge) { + /* Initialize the tethering bridge driver */ + result = ipa3_teth_bridge_driver_init(); + if (result) { + IPAERR(":teth_bridge init failed (%d)\n", -result); + result = -ENODEV; + goto fail_teth_bridge_driver_init; + } + IPADBG("teth_bridge initialized"); + } + + result = ipa3_uc_interface_init(); + if (result) + IPAERR(":ipa Uc interface init failed (%d)\n", -result); + else + IPADBG(":ipa Uc interface init ok\n"); + uc_hdlrs.ipa_uc_loaded_hdlr = ipa3_uc_is_loaded; + uc_hdlrs.ipa_uc_holb_enabled_hdlr = ipa3_uc_holb_client_handler; + ipa3_uc_register_handlers(IPA_HW_FEATURE_COMMON, &uc_hdlrs); + + if (ipa3_ctx->use_tput_est_ep) { + result = ipa3_setup_tput_pipe(); + if (result) + IPAERR(":Failed configuring throughput moniter ep\n"); + else + IPADBG(":Throughput moniter ep configured\n"); + } + + result = ipa3_wdi_init(); + if (result) + IPAERR(":wdi init failed (%d)\n", -result); + else + IPADBG(":wdi init ok\n"); + + result = ipa3_wigig_init_i(); + if (result) + IPAERR(":wigig init failed (%d)\n", -result); + else + IPADBG(":wigig init ok\n"); + + result = ipa3_ntn_init(); + if (result) + IPAERR(":ntn init failed (%d)\n", -result); + else + IPADBG(":ntn init ok\n"); +#if defined(CONFIG_IPA_TSP) + result = ipa_tsp_init(); + if (result) + IPAERR(":TSP init failed (%d)\n", -result); + else + IPADBG(":TSP init ok\n"); +#endif + + result = ipa_hw_stats_init(); + if (result) + IPAERR("fail to init stats %d\n", result); + else + IPADBG(":stats init ok\n"); + + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_5) { + result = ipa_init_flt_rt_stats(); + if (result) + IPAERR("fail to init FnR stats %d\n", result); + else + IPADBG(":FnR stats init ok\n"); + } + + result = ipa_drop_stats_init(); + if (result) + IPAERR("fail to init stats %d\n", result); + else + IPADBG(":stats init ok\n"); + + /* 1st ipa3_panic_notifier*/ + ipa3_register_panic_hdlr(); + + ipa3_debugfs_init(); + + result = ipa_mpm_init(); + if (result) + IPAERR("fail to init mpm %d\n", result); + else + IPADBG(":mpm init init ok\n"); + + ipa3_usb_init(); + + mutex_lock(&ipa3_ctx->lock); + ipa3_ctx->ipa_initialization_complete = true; + mutex_unlock(&ipa3_ctx->lock); + /* init uc-activation tbl*/ + ipa3_setup_uc_act_tbl(); + ipa_trigger_ipa_ready_cbs(); + + complete_all(&ipa3_ctx->init_completion_obj); + + ipa_ut_module_init(); + + /* Query MSI address. */ + gsi_query_device_msi_addr(&ipa3_ctx->gsi_msi_addr); + /* Map the MSI addresses for the GSI to access, for LL and QMAP FC pipe */ + if (ipa3_ctx->gsi_msi_addr) + ipa_gsi_map_unmap_gsi_msi_addr(true); + + if(!ipa_tlpd_stats_init()) + IPADBG("Fail to init tlpd ipa lnx module"); + +#ifdef CONFIG_IPA_RTP + if (ipa3_ctx->platform_type == IPA_PLAT_TYPE_XR) { + /* uC is getting loaded through XBL here */ + ipa3_ctx->uc_ctx.uc_inited = true; + ipa3_ctx->uc_ctx.uc_loaded = true; + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + result = ipa3_alloc_temp_buffs_to_uc(TEMP_BUFF_SIZE, NO_OF_BUFFS); + if (result) { + IPAERR("Temp buffer allocations for uC failed %d\n", result); + result = -ENODEV; + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + goto fail_teth_bridge_driver_init; + } + + result = ipa3_allocate_uc_pipes_er_tr_send_to_uc(); + if (result) { + IPAERR("ER and TR allocations for uC pipes failed %d\n", result); + ipa3_free_uc_temp_buffs(NO_OF_BUFFS); + result = -ENODEV; + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + goto fail_teth_bridge_driver_init; + } + + /* + * Here, synx_init API calls will be success only + * when hw-fence is enabled by default in builds. + */ + result = ipa3_create_hfi_send_uc(); + if (result) { + IPAERR("HFI Creation failed %d\n", result); + ipa3_free_uc_temp_buffs(NO_OF_BUFFS); + ipa3_free_uc_pipes_er_tr(); + result = -ENODEV; + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + goto fail_teth_bridge_driver_init; + } + + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + } +#endif + + pr_info("IPA driver initialization was successful.\n"); +#if IS_ENABLED(CONFIG_QCOM_VA_MINIDUMP) + /*Adding ipa3_ctx pointer to minidump list*/ + mini_dump = (struct ipa_minidump_data *)kzalloc(sizeof(struct ipa_minidump_data), GFP_KERNEL); + if (mini_dump != NULL) { + strlcpy(mini_dump->data.owner, "ipa3_ctx", sizeof(mini_dump->data.owner)); + mini_dump->data.vaddr = (unsigned long)(ipa3_ctx); + mini_dump->data.size = sizeof(struct ipa3_context); + list_add(&mini_dump->entry, &ipa3_ctx->minidump_list_head); + } +#endif + return 0; + +fail_teth_bridge_driver_init: + ipa3_teardown_apps_pipes(); +fail_alloc_gsi_channel: +fail_setup_apps_pipes: + gsi_deregister_device(ipa3_ctx->gsi_dev_hdl, false); +fail_register_device: + ipa3_destroy_flt_tbl_idrs(); +fail_init_interrupts: + ipa3_remove_interrupt_handler(IPA_TX_SUSPEND_IRQ); + ipa3_interrupts_destroy(ipa3_res.ipa_irq, &ipa3_ctx->master_pdev->dev); + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0) + ipa3_free_pkt_init_ex(); +fail_alloc_pkt_init_ex: + ipa3_free_pkt_init(); +fail_alloc_pkt_init: + ipa3_nat_ipv6ct_destroy_devices(); +fail_nat_ipv6ct_init_dev: + ipa3_free_coal_close_frame(); +fail_coal_frame: + ipa3_free_dma_task_for_gsi(); +fail_dma_task: +fail_init_hw: + ipahal_destroy(); +fail_ipahal: + ipa3_proxy_clk_unvote(); + + return result; +} + +static int ipa3_manual_load_ipa_fws(void) +{ + int result; + const struct firmware *fw; + const char *path = IPA_FWS_PATH; + enum gsi_ver gsi_ver = ipa3_ctx->gsi_ver; + + if (ipa3_ctx->ipa3_hw_mode == IPA_HW_MODE_EMULATION) { + switch (ipa3_get_emulation_type()) { + case IPA_HW_v3_5_1: + path = IPA_FWS_PATH_3_5_1; + break; + case IPA_HW_v4_0: + path = IPA_FWS_PATH_4_0; + break; + case IPA_HW_v4_5: + path = IPA_FWS_PATH_4_5; + break; + default: + break; + } + } + + IPADBG("Manual FW loading (%s) process initiated\n", path); + + result = request_firmware(&fw, path, ipa3_ctx->cdev.dev); + if (result < 0) { + IPAERR("request_firmware failed, error %d\n", result); + return result; + } + + IPADBG("FWs are available for loading\n"); + + if (ipa3_ctx->ipa3_hw_mode == IPA_HW_MODE_EMULATION) { + result = emulator_load_fws(fw, + ipa3_res.transport_mem_base, + ipa3_res.transport_mem_size, + gsi_ver); + } else { + result = ipa3_load_fws(fw, ipa3_res.transport_mem_base, + gsi_ver); + } + + if (result) { + IPAERR("Manual IPA FWs loading has failed\n"); + release_firmware(fw); + return result; + } + + result = gsi_enable_fw(ipa3_res.transport_mem_base, + ipa3_res.transport_mem_size, + gsi_ver); + if (result) { + IPAERR("Failed to enable GSI FW\n"); + release_firmware(fw); + return result; + } + + release_firmware(fw); + + IPADBG("Manual FW loading process is complete\n"); + + return 0; +} + +#if IS_ENABLED(CONFIG_QCOM_MDT_LOADER) +static int ipa_firmware_load(const char *sub_sys) +{ + const struct firmware *fw; + char fw_name[32]; + struct device_node *node; + struct resource res; + phys_addr_t phys; + ssize_t size; + void *virt; + int ret, index, pas_id; + struct device *dev = &ipa3_ctx->master_pdev->dev; + + index = of_property_match_string(dev->of_node, "firmware-names", + sub_sys); + if (index < 0) { + pr_err("#####Not able to match firmware names prorperty\n"); + return -EINVAL; + } + + node = of_parse_phandle(dev->of_node, "memory-regions", index); + if (!node) { + dev_err(dev, "DT error getting \"memory-region\" property\n"); + return -EINVAL; + } + + ret = of_address_to_resource(node, 0, &res); + if (ret) { + dev_err(dev, "error %d getting \"memory-region\" resource\n", + ret); + return ret; + } + + scnprintf(fw_name, ARRAY_SIZE(fw_name), "%s.mdt", sub_sys); + ret = of_property_read_u32_index(dev->of_node, "pas-ids", index, + &pas_id); + if(ret) { + dev_err(dev, "error %d getting \"pass-ids\" property\n", + ret); + return ret; + } + + ret = request_firmware(&fw, fw_name, dev); + if (ret) { + dev_err(dev, "error %d requesting \"%s\"\n", ret, fw_name); + return ret; + } + + phys = res.start; + size = (size_t)resource_size(&res); + virt = memremap(phys, size, MEMREMAP_WC); + if (!virt) { + dev_err(dev, "unable to remap firmware memory\n"); + ret = -ENOMEM; + goto out_release_firmware; + } + + ret = qcom_mdt_load(dev, fw, fw_name, pas_id, virt, phys, size, NULL); + if (ret) + dev_err(dev, "error %d loading \"%s\"\n", ret, fw_name); + else if ((ret = qcom_scm_pas_auth_and_reset(pas_id))) + dev_err(dev, "error %d authenticating \"%s\"\n", ret, fw_name); + + memunmap(virt); + +out_release_firmware: + release_firmware(fw); + + return ret; +} + +static int ipa3_mdt_load_ipa_fws(const char *sub_sys) +{ + int ret; + + IPADBG("MDT FW loading process initiated sub_sys=%s\n", + sub_sys); + + ret = ipa_firmware_load(sub_sys); + if (ret < 0) { + IPAERR("Unable to MDT load FW for sub_sys=%s\n", sub_sys); + return -EINVAL; + } + + IPADBG("MDT FW loading process is complete sub_sys=%s\n", sub_sys); + return 0; +} +#else /* IS_ENABLED(CONFIG_QCOM_MDT_LOADER) */ + +static int ipa3_pil_load_ipa_fws(const char *sub_sys) +{ + + IPADBG("PIL FW loading process initiated sub_sys=%s\n", + sub_sys); +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 14, 0)) + ipa3_ctx->subsystem_get_retval = subsystem_get(sub_sys); + if (IS_ERR_OR_NULL(ipa3_ctx->subsystem_get_retval)) { + IPAERR("Unable to PIL load FW for sub_sys=%s\n", sub_sys); + return -EINVAL; + } +#endif + IPADBG("PIL FW loading process is complete sub_sys=%s\n", sub_sys); + return 0; +} +#endif /* IS_ENABLED(CONFIG_QCOM_MDT_LOADER) */ + +#if IS_ENABLED(CONFIG_DEEPSLEEP) || IS_ENABLED(CONFIG_HIBERNATION) +static int ipa3_pil_unload_ipa_fws(void) +{ +#if !IS_ENABLED(CONFIG_QCOM_MDT_LOADER) + IPADBG("PIL FW unloading process initiated sub_sys\n"); + + if (ipa3_ctx->subsystem_get_retval) + subsystem_put(ipa3_ctx->subsystem_get_retval); + + IPADBG("PIL FW unloading process is complete sub_sys\n"); +#endif + return 0; +} +#endif + +static void ipa3_load_ipa_fw(struct work_struct *work) +{ + int result; + + IPADBG("Entry\n"); + + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + + result = ipa3_attach_to_smmu(); + if (result) { + IPAERR("IPA attach to smmu failed %d\n", result); + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + queue_delayed_work(ipa3_ctx->transport_power_mgmt_wq, + &ipa3_fw_load_failure_handle, + msecs_to_jiffies(DELAY_BEFORE_FW_LOAD)); + return; + } + + if (ipa3_ctx->ipa3_hw_mode != IPA_HW_MODE_EMULATION && + ((ipa3_ctx->platform_type != IPA_PLAT_TYPE_MDM) || + (ipa3_ctx->ipa_hw_type >= IPA_HW_v3_5))) { + /* some targets sharing same lunch option but + * using different signing images, adding support to + * load specific FW image to based on dt entry. + */ +#if IS_ENABLED(CONFIG_QCOM_MDT_LOADER) + if (ipa3_ctx->gsi_fw_file_name) + result = ipa3_mdt_load_ipa_fws( + ipa3_ctx->gsi_fw_file_name); + else + result = ipa3_mdt_load_ipa_fws(IPA_SUBSYSTEM_NAME); +#else /* IS_ENABLED(CONFIG_QCOM_MDT_LOADER) */ + if (ipa3_ctx->gsi_fw_file_name) + result = ipa3_pil_load_ipa_fws( + ipa3_ctx->gsi_fw_file_name); + else + result = ipa3_pil_load_ipa_fws(IPA_SUBSYSTEM_NAME); +#endif /* IS_ENABLED(CONFIG_QCOM_MDT_LOADER) */ + } else { + result = ipa3_manual_load_ipa_fws(); + } + + + if (result) { + + ipa3_ctx->ipa_pil_load++; + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + IPADBG("IPA firmware loading deffered to a work queue\n"); + queue_delayed_work(ipa3_ctx->transport_power_mgmt_wq, + &ipa3_fw_load_failure_handle, + msecs_to_jiffies(DELAY_BEFORE_FW_LOAD)); + return; + } + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + mutex_lock(&ipa3_ctx->fw_load_data.lock); + ipa3_ctx->fw_load_data.state = IPA_FW_LOAD_STATE_LOADED; + mutex_unlock(&ipa3_ctx->fw_load_data.lock); + pr_info("IPA FW loaded successfully\n"); + + result = ipa3_post_init(&ipa3_res, ipa3_ctx->cdev.dev); + if (result) { + IPAERR("IPA post init failed %d\n", result); + return; + } + + if (ipa3_ctx->platform_type == IPA_PLAT_TYPE_APQ && + ipa3_ctx->ipa3_hw_mode != IPA_HW_MODE_VIRTUAL && + ipa3_ctx->ipa3_hw_mode != IPA_HW_MODE_EMULATION) { + + IPADBG("Loading IPA uC via PIL\n"); + + /* Unvoting will happen when uC loaded event received. */ + ipa3_proxy_clk_vote(false); + +#if IS_ENABLED(CONFIG_QCOM_MDT_LOADER) + if (ipa3_ctx->uc_fw_file_name) + result = ipa3_mdt_load_ipa_fws( + ipa3_ctx->uc_fw_file_name); + else + result = ipa3_mdt_load_ipa_fws(IPA_UC_SUBSYSTEM_NAME); +#else /* IS_ENABLED(CONFIG_QCOM_MDT_LOADER) */ + if (ipa3_ctx->uc_fw_file_name) + result = ipa3_pil_load_ipa_fws( + ipa3_ctx->uc_fw_file_name); + else + result = ipa3_pil_load_ipa_fws(IPA_UC_SUBSYSTEM_NAME); +#endif /* IS_ENABLED(CONFIG_QCOM_MDT_LOADER) */ + if (result) { + IPAERR("IPA uC loading process has failed result=%d\n", + result); + ipa3_proxy_clk_unvote(); + return; + } + IPADBG("IPA uC loading succeeded\n"); + } +} + +static void ipa_fw_load_sm_handle_event(enum ipa_fw_load_event ev) +{ + mutex_lock(&ipa3_ctx->fw_load_data.lock); + + IPADBG("state=%d event=%d\n", ipa3_ctx->fw_load_data.state, ev); + + if (ev == IPA_FW_LOAD_EVNT_FWFILE_READY) { + if (ipa3_ctx->fw_load_data.state == IPA_FW_LOAD_STATE_INIT) { + ipa3_ctx->fw_load_data.state = + IPA_FW_LOAD_STATE_FWFILE_READY; + goto out; + } + if (ipa3_ctx->fw_load_data.state == + IPA_FW_LOAD_STATE_SMMU_DONE) { + ipa3_ctx->fw_load_data.state = + IPA_FW_LOAD_STATE_LOAD_READY; + goto sched_fw_load; + } + IPAERR("ignore multiple requests to load FW\n"); + goto out; + } + if (ev == IPA_FW_LOAD_EVNT_SMMU_DONE) { + if (ipa3_ctx->fw_load_data.state == IPA_FW_LOAD_STATE_INIT) { + ipa3_ctx->fw_load_data.state = + IPA_FW_LOAD_STATE_SMMU_DONE; + goto sched_fw_load; + } + if (ipa3_ctx->fw_load_data.state == + IPA_FW_LOAD_STATE_FWFILE_READY) { + ipa3_ctx->fw_load_data.state = + IPA_FW_LOAD_STATE_LOAD_READY; + goto sched_fw_load; + } + IPAERR("ignore multiple smmu done events\n"); + goto out; + } + IPAERR("invalid event ev=%d\n", ev); + mutex_unlock(&ipa3_ctx->fw_load_data.lock); + ipa_assert(); + return; + +out: + mutex_unlock(&ipa3_ctx->fw_load_data.lock); + return; + +sched_fw_load: + IPADBG("Scheduled a work to load IPA FW\n"); + mutex_unlock(&ipa3_ctx->fw_load_data.lock); + queue_work(ipa3_ctx->transport_power_mgmt_wq, + &ipa3_fw_loading_work); +} + +static ssize_t ipa3_write(struct file *file, const char __user *buf, + size_t count, loff_t *ppos) +{ + unsigned long missing; + + char dbg_buff[32] = { 0 }; + int i = 0; + + if (count >= sizeof(dbg_buff)) + return -EFAULT; + + missing = copy_from_user(dbg_buff, buf, count); + + if (missing) { + IPAERR("Unable to copy data from user\n"); + return -EFAULT; + } + + if (count > 0) + dbg_buff[count] = '\0'; + + IPADBG("user input string %s\n", dbg_buff); + + /*Ignore empty ipa_config file*/ + for (i = 0 ; i < count ; ++i) { + if (!isspace(dbg_buff[i])) + break; + } + + if (i == count) { + IPADBG("Empty ipa_config file\n"); + return count; + } + + /* Check MHI configuration on MDM devices */ + if (ipa3_ctx->platform_type == IPA_PLAT_TYPE_MDM) { + + if (strnstr(dbg_buff, "vlan", strlen(dbg_buff))) { + if (strnstr(dbg_buff, STR_ETH_IFACE, strlen(dbg_buff))) + ipa3_ctx->vlan_mode_iface[IPA_VLAN_IF_EMAC] = + true; +#if IPA_ETH_API_VER >= 2 + /* In Dual NIC mode we get "vlan: eth [eth0|eth1] [eth0|eth1]?" while device name is + "eth0" in legacy so, we set it to false to diffrentiate Dual NIC from legacy */ + if (strnstr(dbg_buff, STR_ETH0_IFACE, strlen(dbg_buff))) { + ipa3_ctx->vlan_mode_iface[IPA_VLAN_IF_ETH0] = true; + ipa3_ctx->vlan_mode_iface[IPA_VLAN_IF_EMAC] = false; + } + if (strnstr(dbg_buff, STR_ETH1_IFACE, strlen(dbg_buff))){ + ipa3_ctx->vlan_mode_iface[IPA_VLAN_IF_ETH1] = true; + ipa3_ctx->vlan_mode_iface[IPA_VLAN_IF_EMAC] = false; + } +#endif + if (strnstr(dbg_buff, STR_RNDIS_IFACE, strlen(dbg_buff))) + ipa3_ctx->vlan_mode_iface[IPA_VLAN_IF_RNDIS] = + true; + if (strnstr(dbg_buff, STR_ECM_IFACE, strlen(dbg_buff))) + ipa3_ctx->vlan_mode_iface[IPA_VLAN_IF_ECM] = + true; + + /* + * when vlan mode is passed to our dev we expect + * another write + */ + return count; + } + + /* trim ending newline character if any */ + if (count && (dbg_buff[count - 1] == '\n')) + dbg_buff[count - 1] = '\0'; + + /* + * This logic enforeces MHI mode based on userspace input. + * Note that MHI mode could be already determined due + * to previous logic. + */ + if (!strcasecmp(dbg_buff, "MHI")) { + ipa3_ctx->ipa_config_is_mhi = true; + } else if(!strcmp(dbg_buff, "DBS")) { + ipa3_ctx->is_wdi3_tx1_needed = true; + } else if (strcmp(dbg_buff, "1")) { + IPAERR("got invalid string %s not loading FW\n", + dbg_buff); + return count; + } + pr_info("IPA is loading with %sMHI configuration\n", + ipa3_ctx->ipa_config_is_mhi ? "" : "non "); + } + + /* Prevent consequent calls from trying to load the FW again. */ + if (ipa_is_ready()) + return count; + + ipa_fw_load_sm_handle_event(IPA_FW_LOAD_EVNT_FWFILE_READY); + + return count; +} + +/** + * ipa3_tz_unlock_reg - Unlocks memory regions so that they become accessible + * from AP. + * @reg_info - Pointer to array of memory regions to unlock + * @num_regs - Number of elements in the array + * + * Converts the input array of regions to a struct that TZ understands and + * issues an SCM call. + * Also flushes the memory cache to DDR in order to make sure that TZ sees the + * correct data structure. + * + * Returns: 0 on success, negative on failure + */ +int ipa3_tz_unlock_reg(struct ipa_tz_unlock_reg_info *reg_info, u16 num_regs) +{ + int i, ret; + compat_size_t size; + struct tz_smmu_ipa_protect_region_iovec_s *ipa_tz_unlock_vec; + struct tz_smmu_ipa_protect_region_s cmd_buf; + + if (reg_info == NULL || num_regs == 0) { + IPAERR("Bad parameters\n"); + return -EFAULT; + } + + size = num_regs * sizeof(struct tz_smmu_ipa_protect_region_iovec_s); + ipa_tz_unlock_vec = kzalloc(PAGE_ALIGN(size), GFP_KERNEL); + if (ipa_tz_unlock_vec == NULL) + return -ENOMEM; + + for (i = 0; i < num_regs; i++) { + ipa_tz_unlock_vec[i].input_addr = reg_info[i].reg_addr ^ + (reg_info[i].reg_addr & 0xFFF); + ipa_tz_unlock_vec[i].output_addr = reg_info[i].reg_addr ^ + (reg_info[i].reg_addr & 0xFFF); + ipa_tz_unlock_vec[i].size = reg_info[i].size; + ipa_tz_unlock_vec[i].attr = IPA_TZ_UNLOCK_ATTRIBUTE; + } + + /* pass physical address of command buffer */ + cmd_buf.iovec_buf = virt_to_phys((void *)ipa_tz_unlock_vec); + cmd_buf.size_bytes = size; + + ret = qcom_scm_mem_protect_region_id( + virt_to_phys((void *)ipa_tz_unlock_vec), + size); + + if (ret) { + IPAERR("scm call SCM_SVC_MP failed: %d\n", ret); + kfree(ipa_tz_unlock_vec); + return -EFAULT; + } + kfree(ipa_tz_unlock_vec); + return 0; +} + +static int ipa3_alloc_pkt_init(void) +{ + struct ipa_mem_buffer *mem = &ipa3_ctx->pkt_init_mem; + struct ipahal_imm_cmd_pyld *cmd_pyld; + struct ipahal_imm_cmd_ip_packet_init cmd = {0}; + int i; + + cmd_pyld = ipahal_construct_imm_cmd(IPA_IMM_CMD_IP_PACKET_INIT, + &cmd, false); + if (!cmd_pyld) { + IPAERR("failed to construct IMM cmd\n"); + return -ENOMEM; + } + ipa3_ctx->pkt_init_imm_opcode = cmd_pyld->opcode; + + mem->size = cmd_pyld->len * ipa3_ctx->ipa_num_pipes; + ipahal_destroy_imm_cmd(cmd_pyld); + mem->base = dma_alloc_coherent(ipa3_ctx->pdev, mem->size, + &mem->phys_base, GFP_KERNEL); + if (!mem->base) { + IPAERR("failed to alloc DMA buff of size %d\n", mem->size); + return -ENOMEM; + } + + memset(mem->base, 0, mem->size); + for (i = 0; i < ipa3_ctx->ipa_num_pipes; i++) { + cmd.destination_pipe_index = i; + cmd_pyld = ipahal_construct_imm_cmd(IPA_IMM_CMD_IP_PACKET_INIT, + &cmd, false); + if (!cmd_pyld) { + IPAERR("failed to construct IMM cmd\n"); + dma_free_coherent(ipa3_ctx->pdev, + mem->size, + mem->base, + mem->phys_base); + return -ENOMEM; + } + memcpy(mem->base + i * cmd_pyld->len, cmd_pyld->data, + cmd_pyld->len); + ipa3_ctx->pkt_init_imm[i] = mem->phys_base + i * cmd_pyld->len; + ipahal_destroy_imm_cmd(cmd_pyld); + } + + return 0; +} + +static void ipa3_free_pkt_init(void) +{ + dma_free_coherent(ipa3_ctx->pdev, ipa3_ctx->pkt_init_mem.size, + ipa3_ctx->pkt_init_mem.base, + ipa3_ctx->pkt_init_mem.phys_base); +} + +static void ipa3_free_pkt_init_ex(void) +{ + dma_free_coherent(ipa3_ctx->pdev, ipa3_ctx->pkt_init_ex_mem.size, + ipa3_ctx->pkt_init_ex_mem.base, + ipa3_ctx->pkt_init_ex_mem.phys_base); +} + +static int ipa_alloc_pkt_init_ex(void) +{ + struct ipa_mem_buffer *mem = &ipa3_ctx->pkt_init_ex_mem; + struct ipahal_imm_cmd_pyld *cmd_pyld; + struct ipahal_imm_cmd_ip_packet_init_ex cmd = {0}; + struct ipahal_imm_cmd_ip_packet_init_ex cmd_mask = {0}; + int result = 0; + + cmd_pyld = ipahal_construct_imm_cmd(IPA_IMM_CMD_IP_PACKET_INIT_EX, + &cmd, false); + if (!cmd_pyld) { + IPAERR("failed to construct IMM cmd\n"); + return -ENOMEM; + } + ipa3_ctx->pkt_init_ex_imm_opcode = cmd_pyld->opcode; + + /* one cmd for each pipe for ULSO + one common for ICMP */ + mem->size = cmd_pyld->len * (ipa3_ctx->ipa_num_pipes + 1); + mem->base = dma_alloc_coherent(ipa3_ctx->pdev, mem->size, + &mem->phys_base, GFP_KERNEL); + if (!mem->base) { + IPAERR("failed to alloc DMA buff of size %d\n", mem->size); + result = -ENOMEM; + goto free_imm; + } + + memset(mem->base, 0, mem->size); + cmd.frag_disable = true; + cmd_mask.frag_disable = true; + cmd.nat_disable = true; + cmd_mask.nat_disable = true; + cmd.filter_disable = true; + cmd_mask.filter_disable = true; + cmd.route_disable = true; + cmd_mask.route_disable = true; + cmd.hdr_removal_insertion_disable = false; + cmd_mask.hdr_removal_insertion_disable = true; + cmd.cs_disable = false; + cmd_mask.cs_disable = true; + cmd.flt_retain_hdr = true; + cmd_mask.flt_retain_hdr = true; + cmd.rt_retain_hdr = true; + cmd_mask.rt_retain_hdr = true; + cmd_mask.rt_pipe_dest_idx = true; + for (cmd.rt_pipe_dest_idx = 0; + cmd.rt_pipe_dest_idx < ipa3_ctx->ipa_num_pipes; + cmd.rt_pipe_dest_idx++) { + result = ipahal_modify_imm_cmd(IPA_IMM_CMD_IP_PACKET_INIT_EX, + cmd_pyld->data, &cmd, &cmd_mask); + if (unlikely(result != 0)) { + IPAERR("failed to modify IMM cmd\n"); + goto free_dma; + } + memcpy(mem->base + cmd.rt_pipe_dest_idx * cmd_pyld->len, + cmd_pyld->data, cmd_pyld->len); + ipa3_ctx->pkt_init_ex_imm[cmd.rt_pipe_dest_idx].phys_base = + mem->phys_base + cmd.rt_pipe_dest_idx * cmd_pyld->len; + ipa3_ctx->pkt_init_ex_imm[cmd.rt_pipe_dest_idx].base = + mem->base + cmd.rt_pipe_dest_idx * cmd_pyld->len; + ipa3_ctx->pkt_init_ex_imm[cmd.rt_pipe_dest_idx].size = + cmd_pyld->len; + } + + cmd.hdr_removal_insertion_disable = true; + cmd.cs_disable = true; + cmd.flt_retain_hdr = false; + cmd.rt_retain_hdr = false; + cmd.flt_close_aggr_irq_mod = true; + cmd_mask.flt_close_aggr_irq_mod = true; + cmd.rt_close_aggr_irq_mod = true; + cmd_mask.rt_close_aggr_irq_mod = true; + /* Just a placeholder. Will be assigned in the DP, before sending. */ + cmd.rt_pipe_dest_idx = ipa3_ctx->ipa_num_pipes; + result = ipahal_modify_imm_cmd(IPA_IMM_CMD_IP_PACKET_INIT_EX, + cmd_pyld->data, &cmd, &cmd_mask); + if (unlikely(result != 0)) { + IPAERR("failed to modify IMM cmd\n"); + goto free_dma; + } + memcpy(mem->base + ipa3_ctx->ipa_num_pipes * cmd_pyld->len, + cmd_pyld->data, + cmd_pyld->len); + ipa3_ctx->pkt_init_ex_imm[ipa3_ctx->ipa_num_pipes].phys_base = + mem->phys_base + ipa3_ctx->ipa_num_pipes * cmd_pyld->len; + ipa3_ctx->pkt_init_ex_imm[ipa3_ctx->ipa_num_pipes].base = + mem->base + ipa3_ctx->ipa_num_pipes * cmd_pyld->len; + ipa3_ctx->pkt_init_ex_imm[ipa3_ctx->ipa_num_pipes].size = cmd_pyld->len; + + goto free_imm; + +free_dma: + dma_free_coherent(ipa3_ctx->pdev, + mem->size, + mem->base, + mem->phys_base); +free_imm: + ipahal_destroy_imm_cmd(cmd_pyld); + return result; +} + +/** + * ipa_set_pkt_init_ex_hdr_ofst() - Set pkt_init_ex header offset for the ep + * @lookup: header and ep identifying parameters + * + * Returns 0 on success + */ +int ipa_set_pkt_init_ex_hdr_ofst(struct ipa_pkt_init_ex_hdr_ofst_set + *lookup, bool proc_ctx) +{ + struct ipahal_imm_cmd_pyld *cmd_pyld; + struct ipahal_imm_cmd_ip_packet_init_ex cmd = {0}; + u32 offset; + int res = 0; + int dst_ep_idx; + + if (!lookup) + return -EINVAL; + + dst_ep_idx = ipa_get_ep_mapping(lookup->ep); + IPADBG("dst_ep_idx=%d\n", dst_ep_idx); + if (-1 == dst_ep_idx) { + IPAERR("Client %u is not mapped\n", lookup->ep); + return -EINVAL; + } + if (proc_ctx) { + res = ipa3_get_hdr_proc_ctx_offset(lookup->name, &offset); + } else { + res = ipa3_get_hdr_offset(lookup->name ,&offset); + } + if (res != 0) + return res; + + cmd.rt_hdr_offset = offset; + IPADBG("cmd.rt_hdr_offset=%d\n", cmd.rt_hdr_offset); + cmd.frag_disable = true; + cmd.nat_disable = true; + cmd.filter_disable = true; + cmd.route_disable = true; + cmd.hdr_removal_insertion_disable = false; + cmd.cs_disable = false; + cmd.flt_retain_hdr = true; + cmd.rt_retain_hdr = true; + cmd.rt_pipe_dest_idx = dst_ep_idx; + cmd.rt_proc_ctx = proc_ctx; + cmd_pyld = ipahal_construct_imm_cmd(IPA_IMM_CMD_IP_PACKET_INIT_EX, + &cmd, false); + if (!cmd_pyld) { + IPAERR("failed to construct IMM cmd\n"); + return -ENOMEM; + } + memcpy(ipa3_ctx->pkt_init_ex_mem.base + dst_ep_idx * cmd_pyld->len, + cmd_pyld->data, cmd_pyld->len); + ipahal_destroy_imm_cmd(cmd_pyld); + return 0; +} +EXPORT_SYMBOL(ipa_set_pkt_init_ex_hdr_ofst); + +/* + * SCM call to check if secure dump is allowed. + * + * Returns true in secure dump allowed. + * Return false when secure dump not allowed. + */ +static bool ipa_is_mem_dump_allowed(void) +{ + int ret; + u32 dump_state; + + ret = qcom_scm_get_sec_dump_state(&dump_state); + + if (ret) { + IPAERR("SCM DUMP_STATE call failed\n"); + return false; + } + + return (dump_state == 1); +} + +static int ipa3_lan_poll(struct napi_struct *napi, int budget) +{ + int rcvd_pkts = 0; + + rcvd_pkts = ipa3_lan_rx_poll(ipa3_ctx->clnt_hdl_data_in, + NAPI_WEIGHT); + return rcvd_pkts; +} + +static inline void ipa3_enable_napi_netdev(void) +{ + if (ipa3_ctx->lan_rx_napi_enable || ipa3_ctx->tx_napi_enable) { + init_dummy_netdev(&ipa3_ctx->generic_ndev); + if(ipa3_ctx->lan_rx_napi_enable) { +#if (LINUX_VERSION_CODE > KERNEL_VERSION(6, 0, 14)) + netif_napi_add( + &ipa3_ctx->generic_ndev, + &ipa3_ctx->napi_lan_rx, + ipa3_lan_poll); +#else + netif_napi_add( + &ipa3_ctx->generic_ndev, + &ipa3_ctx->napi_lan_rx, + ipa3_lan_poll, + NAPI_WEIGHT); +#endif + } + } +} + +static inline void ipa3_disable_napi_netdev(void) +{ + if (ipa3_ctx->lan_rx_napi_enable) + netif_napi_del(&ipa3_ctx->napi_lan_rx); +} + +static u32 get_tx_wrapper_cache_size(u32 cache_size) +{ + if (cache_size <= IPA_TX_WRAPPER_CACHE_MAX_THRESHOLD) + return cache_size; + return IPA_TX_WRAPPER_CACHE_MAX_THRESHOLD; +} + +#if IS_ENABLED(CONFIG_QCOM_VA_MINIDUMP) +static int qcom_va_md_ipa_notif_handler(struct notifier_block *this, + unsigned long event, void *ptr) +{ + struct ipa_minidump_data *testptr; + struct ipa_minidump_data *ptr_next; + + list_for_each_entry_safe(testptr, ptr_next, &ipa3_ctx->minidump_list_head, entry) { + qcom_va_md_add_region(&testptr->data); + } + + return NOTIFY_OK; +} + +static struct notifier_block qcom_va_md_ipa_notif_blk = { + .notifier_call = qcom_va_md_ipa_notif_handler, + .priority = INT_MAX, +}; +#endif + +static u32 get_ipa_gen_rx_cmn_page_pool_size(u32 rx_cmn_page_pool_size) +{ + if (!rx_cmn_page_pool_size) + return IPA_GENERIC_RX_CMN_PAGE_POOL_SZ_FACTOR; + return rx_cmn_page_pool_size; +} + + +static u32 get_ipa_gen_rx_cmn_temp_pool_size(u32 rx_cmn_temp_pool_size) +{ + if (!rx_cmn_temp_pool_size) + return IPA_GENERIC_RX_CMN_TEMP_POOL_SZ_FACTOR; + return rx_cmn_temp_pool_size; +} + +static u32 get_ipa_gen_rx_ll_pool_size(u32 rx_ll_pool_sz_factor) +{ + if (!rx_ll_pool_sz_factor) + return IPA_GENERIC_RX_PAGE_POOL_SZ_FACTOR; + if (rx_ll_pool_sz_factor <= IPA_GENERIC_RX_PAGE_POOL_SZ_FACTOR) + return rx_ll_pool_sz_factor; + return IPA_GENERIC_RX_PAGE_POOL_SZ_FACTOR; +} + +/** + * ipa3_pre_init() - Initialize the IPA Driver. + * This part contains all initialization which doesn't require IPA HW, such + * as structure allocations and initializations, register writes, etc. + * + * @resource_p: contain platform specific values from DST file + * @pdev: The platform device structure representing the IPA driver + * + * Function initialization process: + * Allocate memory for the driver context data struct + * Initializing the ipa3_ctx with : + * 1)parsed values from the dts file + * 2)parameters passed to the module initialization + * 3)read HW values(such as core memory size) + * Map IPA core registers to CPU memory + * Restart IPA core(HW reset) + * Initialize the look-aside caches(kmem_cache/slab) for filter, + * routing and IPA-tree + * Create memory pool with 4 objects for DMA operations(each object + * is 512Bytes long), this object will be use for tx(A5->IPA) + * Initialize lists head(routing, hdr, system pipes) + * Initialize mutexes (for ipa_ctx and NAT memory mutexes) + * Initialize spinlocks (for list related to A5<->IPA pipes) + * Initialize 2 single-threaded work-queue named "ipa rx wq" and "ipa tx wq" + * Initialize Red-Black-Tree(s) for handles of header,routing rule, + * routing table ,filtering rule + * Initialize the filter block by committing IPV4 and IPV6 default rules + * Create empty routing table in system memory(no committing) + * Create a char-device for IPA + * Initialize IPA PM (power manager) + * Configure GSI registers (in GSI case) + */ +static int ipa3_pre_init(const struct ipa3_plat_drv_res *resource_p, + struct platform_device *ipa_pdev) +{ + int result = 0; + int i, j; + struct ipa3_rt_tbl_set *rset; + struct ipa_active_client_logging_info log_info; + struct cdev *cdev; + enum hdr_tbl_storage hdr_tbl; + + IPADBG("IPA Driver initialization started\n"); + + if (!ipa3_ctx) { + result = -ENOMEM; + goto fail_mem_ctx; + } + /* If SMMU not support fw load state will be updated + * in probe function. Avoid overwriting in pre-init function */ + if (ipa3_ctx->fw_load_data.state != IPA_FW_LOAD_STATE_SMMU_DONE) + ipa3_ctx->fw_load_data.state = IPA_FW_LOAD_STATE_INIT; + mutex_init(&ipa3_ctx->fw_load_data.lock); + + ipa3_ctx->logbuf = ipc_log_context_create(IPA_IPC_LOG_PAGES, "ipa", MINIDUMP_MASK); + if (ipa3_ctx->logbuf == NULL) + IPADBG("failed to create IPC log, continue...\n"); + + ipa3_ctx->logbuf_clk = ipc_log_context_create(IPA_IPC_LOG_PAGES, "ipa_clk", MINIDUMP_MASK); + if (ipa3_ctx->logbuf_clk == NULL) + IPADBG("failed to create IPC ipa_clk log, continue...\n"); + + /* ipa3_ctx->pdev and ipa3_ctx->uc_pdev will be set in the smmu probes*/ + ipa3_ctx->master_pdev = ipa_pdev; + for (i = 0; i < IPA_SMMU_CB_MAX; i++) + ipa3_ctx->s1_bypass_arr[i] = true; + + /* initialize the gsi protocol info for uC debug stats */ + for (i = 0; i < IPA_HW_PROTOCOL_MAX; i++) { + ipa3_ctx->gsi_info[i].protocol = i; + /* initialize all to be not started */ + for (j = 0; j < IPA_MAX_CH_STATS_SUPPORTED; j++) + ipa3_ctx->gsi_info[i].ch_id_info[j].ch_id = + 0xFF; + } + + ipa3_ctx->ipa_wrapper_base = resource_p->ipa_mem_base; + ipa3_ctx->ipa_wrapper_size = resource_p->ipa_mem_size; + ipa3_ctx->ipa_cfg_offset = resource_p->ipa_cfg_offset; + ipa3_ctx->ipa_hw_type = resource_p->ipa_hw_type; + ipa3_ctx->ipa_config_is_mhi = resource_p->ipa_mhi_dynamic_config; + ipa3_ctx->ipa3_hw_mode = resource_p->ipa3_hw_mode; + ipa3_ctx->platform_type = resource_p->platform_type; + ipa3_ctx->use_ipa_teth_bridge = resource_p->use_ipa_teth_bridge; + ipa3_ctx->modem_cfg_emb_pipe_flt = resource_p->modem_cfg_emb_pipe_flt; + ipa3_ctx->ipa_wdi2 = resource_p->ipa_wdi2; + ipa3_ctx->ipa_wdi2_over_gsi = resource_p->ipa_wdi2_over_gsi; + ipa3_ctx->ipa_wdi3_over_gsi = resource_p->ipa_wdi3_over_gsi; + ipa3_ctx->ipa_fltrt_not_hashable = resource_p->ipa_fltrt_not_hashable; + ipa3_ctx->use_xbl_boot = resource_p->use_xbl_boot; + ipa3_ctx->use_64_bit_dma_mask = resource_p->use_64_bit_dma_mask; + ipa3_ctx->wan_rx_ring_size = resource_p->wan_rx_ring_size; + ipa3_ctx->lan_rx_ring_size = resource_p->lan_rx_ring_size; + ipa3_ctx->ipa_wan_skb_page = resource_p->ipa_wan_skb_page; + ipa3_ctx->uc_ctx.ipa_use_uc_holb_monitor = + resource_p->ipa_use_uc_holb_monitor; + ipa3_ctx->uc_ctx.holb_monitor.poll_period = + resource_p->ipa_holb_monitor_poll_period; + ipa3_ctx->uc_ctx.holb_monitor.max_cnt_wlan = + resource_p->ipa_holb_monitor_max_cnt_wlan; + ipa3_ctx->uc_ctx.holb_monitor.max_cnt_usb = + resource_p->ipa_holb_monitor_max_cnt_usb; + ipa3_ctx->uc_ctx.holb_monitor.max_cnt_11ad = + resource_p->ipa_holb_monitor_max_cnt_11ad; + ipa3_ctx->ipa_wan_aggr_pkt_cnt = resource_p->ipa_wan_aggr_pkt_cnt; + memset( + ipa3_ctx->stats.page_recycle_stats, + 0, + sizeof(ipa3_ctx->stats.page_recycle_stats)); + memset( + ipa3_ctx->stats.cache_recycle_stats, + 0, + sizeof(ipa3_ctx->stats.cache_recycle_stats)); + memset( + &ipa3_ctx->stats.coal, + 0, + sizeof(ipa3_ctx->stats.coal)); + memset(ipa3_ctx->stats.page_recycle_cnt, 0, + sizeof(ipa3_ctx->stats.page_recycle_cnt)); + ipa3_ctx->stats.num_sort_tasklet_sched[0] = 0; + ipa3_ctx->stats.num_sort_tasklet_sched[1] = 0; + ipa3_ctx->stats.num_sort_tasklet_sched[2] = 0; + ipa3_ctx->stats.num_of_times_wq_reschd = 0; + ipa3_ctx->stats.page_recycle_cnt_in_tasklet = 0; + ipa3_ctx->skip_uc_pipe_reset = resource_p->skip_uc_pipe_reset; + ipa3_ctx->tethered_flow_control = resource_p->tethered_flow_control; + ipa3_ctx->ee = resource_p->ee; + ipa3_ctx->apply_rg10_wa = resource_p->apply_rg10_wa; + ipa3_ctx->gsi_ch20_wa = resource_p->gsi_ch20_wa; + ipa3_ctx->wdi_over_pcie = resource_p->wdi_over_pcie; + ipa3_ctx->ipa3_active_clients_logging.log_rdy = false; + ipa3_ctx->is_device_crashed = false; + ipa3_ctx->mhi_evid_limits[0] = resource_p->mhi_evid_limits[0]; + ipa3_ctx->mhi_evid_limits[1] = resource_p->mhi_evid_limits[1]; + ipa3_ctx->entire_ipa_block_size = resource_p->entire_ipa_block_size; + ipa3_ctx->do_register_collection_on_crash = + resource_p->do_register_collection_on_crash; + ipa3_ctx->do_testbus_collection_on_crash = + resource_p->do_testbus_collection_on_crash; + ipa3_ctx->do_non_tn_collection_on_crash = + resource_p->do_non_tn_collection_on_crash; + ipa3_ctx->secure_debug_check_action = + resource_p->secure_debug_check_action; + ipa3_ctx->do_ram_collection_on_crash = + resource_p->do_ram_collection_on_crash; + ipa3_ctx->lan_rx_napi_enable = resource_p->lan_rx_napi_enable; + ipa3_ctx->tx_napi_enable = resource_p->tx_napi_enable; + ipa3_ctx->tx_poll = resource_p->tx_poll; + ipa3_ctx->ipa_gpi_event_rp_ddr = resource_p->ipa_gpi_event_rp_ddr; + ipa3_ctx->rmnet_ctl_enable = resource_p->rmnet_ctl_enable; + ipa3_ctx->lan_coal_enable = resource_p->lan_coal_enable; + ipa3_ctx->rmnet_ll_enable = resource_p->rmnet_ll_enable; + ipa3_ctx->tx_wrapper_cache_max_size = get_tx_wrapper_cache_size( + resource_p->tx_wrapper_cache_max_size); + ipa3_ctx->ipa_gen_rx_cmn_page_pool_sz_factor = get_ipa_gen_rx_cmn_page_pool_size( + resource_p->ipa_gen_rx_cmn_page_pool_sz_factor); + ipa3_ctx->ipa_gen_rx_cmn_temp_pool_sz_factor = get_ipa_gen_rx_cmn_temp_pool_size( + resource_p->ipa_gen_rx_cmn_temp_pool_sz_factor); + ipa3_ctx->ipa_gen_rx_ll_pool_sz_factor = get_ipa_gen_rx_ll_pool_size( + resource_p->ipa_gen_rx_ll_pool_sz_factor); + ipa3_ctx->ipa_config_is_auto = resource_p->ipa_config_is_auto; + ipa3_ctx->ipa_mhi_proxy = resource_p->ipa_mhi_proxy; + ipa3_ctx->max_num_smmu_cb = resource_p->max_num_smmu_cb; + ipa3_ctx->hw_type_index = ipa3_get_hw_type_index(); + ipa3_ctx->ipa_wdi3_2g_holb_timeout = + resource_p->ipa_wdi3_2g_holb_timeout; + ipa3_ctx->ipa_wdi3_5g_holb_timeout = + resource_p->ipa_wdi3_5g_holb_timeout; + ipa3_ctx->is_wdi3_tx1_needed = false; + ipa3_ctx->ulso_supported = resource_p->ulso_supported; + ipa3_ctx->ulso_ip_id_min = resource_p->ulso_ip_id_min; + ipa3_ctx->ulso_ip_id_max = resource_p->ulso_ip_id_max; + ipa3_ctx->use_pm_wrapper = resource_p->use_pm_wrapper; + ipa3_ctx->use_tput_est_ep = resource_p->use_tput_est_ep; + ipa3_ctx->mpm_ring_size_ul_cache = DEFAULT_MPM_RING_SIZE_UL; + ipa3_ctx->mpm_ring_size_ul = DEFAULT_MPM_RING_SIZE_UL; + ipa3_ctx->mpm_ring_size_dl_cache = DEFAULT_MPM_RING_SIZE_DL; + ipa3_ctx->mpm_ring_size_dl = DEFAULT_MPM_RING_SIZE_DL; + ipa3_ctx->mpm_teth_aggr_size = DEFAULT_MPM_TETH_AGGR_SIZE; + ipa3_ctx->mpm_uc_thresh = DEFAULT_MPM_UC_THRESH_SIZE; + ipa3_ctx->uc_act_tbl_valid = false; + ipa3_ctx->uc_act_tbl_total = 0; + ipa3_ctx->uc_act_tbl_next_index = 0; + ipa3_ctx->ipa_wdi_opt_dpath = resource_p->ipa_wdi_opt_dpath; + + if (resource_p->gsi_fw_file_name) { + ipa3_ctx->gsi_fw_file_name = + kzalloc(((strlen(resource_p->gsi_fw_file_name)+1) * + sizeof(const char)), GFP_KERNEL); + if (ipa3_ctx->gsi_fw_file_name == NULL) { + IPAERR_RL("Failed to alloc GSI FW file name\n"); + result = -ENOMEM; + goto fail_gsi_file_alloc; + } + memcpy(ipa3_ctx->gsi_fw_file_name, + (void const *)resource_p->gsi_fw_file_name, + strlen(resource_p->gsi_fw_file_name)); + } + + if (resource_p->uc_fw_file_name) { + ipa3_ctx->uc_fw_file_name = + kzalloc(((strlen(resource_p->uc_fw_file_name)+1) * + sizeof(const char)), GFP_KERNEL); + if (ipa3_ctx->uc_fw_file_name == NULL) { + IPAERR_RL("Failed to alloc uC FW file name\n"); + result = -ENOMEM; + goto fail_uc_file_alloc; + } + memcpy(ipa3_ctx->uc_fw_file_name, + (void const *)resource_p->uc_fw_file_name, + strlen(resource_p->uc_fw_file_name)); + } + + if (IPA_IS_REGULAR_CLK_MODE(ipa3_ctx->ipa3_hw_mode) && + ipa3_ctx->secure_debug_check_action == USE_SCM) { + if (ipa_is_mem_dump_allowed()) + ipa3_ctx->sd_state = SD_ENABLED; + else + ipa3_ctx->sd_state = SD_DISABLED; + } else { + if (ipa3_ctx->secure_debug_check_action == OVERRIDE_SCM_TRUE) + ipa3_ctx->sd_state = SD_ENABLED; + else + /* secure_debug_check_action == OVERRIDE_SCM_FALSE */ + ipa3_ctx->sd_state = SD_DISABLED; + } + + if (ipa3_ctx->sd_state == SD_ENABLED) { + /* secure debug is enabled. */ + IPADBG("secure debug enabled\n"); + } else { + /* secure debug is disabled. */ + IPADBG("secure debug disabled\n"); + ipa3_ctx->do_testbus_collection_on_crash = false; + } + ipa3_ctx->ipa_endp_delay_wa = resource_p->ipa_endp_delay_wa; + ipa3_ctx->ipa_endp_delay_wa_v2 = resource_p->ipa_endp_delay_wa_v2; + ipa3_ctx->ulso_wa = resource_p->ulso_wa; + ipa3_ctx->coal_ipv4_id_ignore = resource_p->coal_ipv4_id_ignore; + + WARN(!IPA_IS_REGULAR_CLK_MODE(ipa3_ctx->ipa3_hw_mode), + "Non NORMAL IPA HW mode, is this emulation platform ?"); + + if (resource_p->ipa_tz_unlock_reg) { + ipa3_ctx->ipa_tz_unlock_reg_num = + resource_p->ipa_tz_unlock_reg_num; + ipa3_ctx->ipa_tz_unlock_reg = kcalloc( + ipa3_ctx->ipa_tz_unlock_reg_num, + sizeof(*ipa3_ctx->ipa_tz_unlock_reg), + GFP_KERNEL); + if (ipa3_ctx->ipa_tz_unlock_reg == NULL) { + result = -ENOMEM; + goto fail_tz_unlock_reg; + } + for (i = 0; i < ipa3_ctx->ipa_tz_unlock_reg_num; i++) { + ipa3_ctx->ipa_tz_unlock_reg[i].reg_addr = + resource_p->ipa_tz_unlock_reg[i].reg_addr; + ipa3_ctx->ipa_tz_unlock_reg[i].size = + resource_p->ipa_tz_unlock_reg[i].size; + } + + /* unlock registers for uc */ + result = ipa3_tz_unlock_reg(ipa3_ctx->ipa_tz_unlock_reg, + ipa3_ctx->ipa_tz_unlock_reg_num); + if (result) + IPAERR("Failed to unlock memory region using TZ\n"); + } + + /* default aggregation parameters */ + ipa3_ctx->aggregation_type = IPA_MBIM_16; + ipa3_ctx->aggregation_byte_limit = 1; + ipa3_ctx->aggregation_time_limit = 0; + + /* configure interconnect parameters */ + ipa3_ctx->icc_num_cases = resource_p->icc_num_cases; + ipa3_ctx->icc_num_paths = resource_p->icc_num_paths; + for (i = 0; i < ipa3_ctx->icc_num_cases; i++) { + for (j = 0; j < ipa3_ctx->icc_num_paths; j++) { + ipa3_ctx->icc_clk[i][j][IPA_ICC_AB] = + resource_p->icc_clk_val[i][j*IPA_ICC_TYPE_MAX]; + ipa3_ctx->icc_clk[i][j][IPA_ICC_IB] = + resource_p->icc_clk_val[i][j*IPA_ICC_TYPE_MAX+1]; + } + } + + ipa3_ctx->ctrl = kzalloc(sizeof(*ipa3_ctx->ctrl), GFP_KERNEL); + if (!ipa3_ctx->ctrl) { + result = -ENOMEM; + goto fail_mem_ctrl; + } + result = ipa3_controller_static_bind(ipa3_ctx->ctrl, + ipa3_ctx->ipa_hw_type, ipa3_ctx->ipa_cfg_offset); + if (result) { + IPAERR("fail to static bind IPA ctrl\n"); + result = -EFAULT; + goto fail_bind; + } + + result = ipa3_init_mem_partition(ipa3_ctx->ipa_hw_type); + if (result) { + IPAERR(":ipa3_init_mem_partition failed\n"); + result = -ENODEV; + goto fail_init_mem_partition; + } + + if (ipa3_ctx->ipa3_hw_mode != IPA_HW_MODE_VIRTUAL && + ipa3_ctx->ipa3_hw_mode != IPA_HW_MODE_EMULATION) { + /* get BUS handle */ + for (i = 0; i < ipa3_ctx->icc_num_paths; i++) { + ipa3_ctx->ctrl->icc_path[i] = of_icc_get( + &ipa3_ctx->master_pdev->dev, + resource_p->icc_path_name[i]); + if (IS_ERR(ipa3_ctx->ctrl->icc_path[i])) { + IPAERR("fail to register with bus mgr!\n"); + result = PTR_ERR(ipa3_ctx->ctrl->icc_path[i]); + if (result != -EPROBE_DEFER) { + IPAERR("Failed to get path %s\n", + ipa3_ctx->master_pdev->name); + } + goto fail_bus_reg; + } + } + } + + /* get IPA clocks */ + result = ipa3_get_clks(&ipa3_ctx->master_pdev->dev); + if (result) + goto fail_bus_reg; + + /* init active_clients_log after getting ipa-clk */ + result = ipa3_active_clients_log_init(); + if (result) + goto fail_init_active_client; + + /* Enable ipa3_ctx->enable_clock_scaling */ + ipa3_ctx->enable_clock_scaling = 1; + /* vote for svs2 on bootup */ + ipa3_ctx->curr_ipa_clk_rate = ipa3_ctx->ctrl->ipa_clk_rate_svs2; + + /* Enable ipa3_ctx->enable_napi_chain */ + ipa3_ctx->enable_napi_chain = 1; + + /* Initialize Page poll threshold. */ + ipa3_ctx->page_poll_threshold = IPA_PAGE_POLL_DEFAULT_THRESHOLD; + + /*Initialize number napi without prealloc buff*/ + ipa3_ctx->ipa_max_napi_sort_page_thrshld = IPA_MAX_NAPI_SORT_PAGE_THRSHLD; + ipa3_ctx->page_wq_reschd_time = IPA_MAX_PAGE_WQ_RESCHED_TIME; + + /* Use common page pool for Def/Coal pipe. */ + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_1) + ipa3_ctx->wan_common_page_pool = true; + + /* assume clock is on in virtual/emulation mode */ + if (ipa3_ctx->ipa3_hw_mode == IPA_HW_MODE_VIRTUAL || + ipa3_ctx->ipa3_hw_mode == IPA_HW_MODE_EMULATION) + atomic_set(&ipa3_ctx->ipa_clk_vote, 1); + + /* enable IPA clocks explicitly to allow the initialization */ + ipa3_enable_clks(); + + /* setup IPA register access */ + IPADBG("Mapping 0x%x\n", resource_p->ipa_mem_base + + ipa3_ctx->ctrl->ipa_reg_base_ofst); + ipa3_ctx->mmio = ioremap(resource_p->ipa_mem_base + + ipa3_ctx->ctrl->ipa_reg_base_ofst, + resource_p->ipa_mem_size); + if (!ipa3_ctx->mmio) { + IPAERR(":ipa-base ioremap err\n"); + result = -EFAULT; + goto fail_remap; + } + + IPADBG( + "base(0x%x)+offset(0x%x)=(0x%x) mapped to (0x%x) with len (0x%x)\n", + resource_p->ipa_mem_base, + ipa3_ctx->ctrl->ipa_reg_base_ofst, + resource_p->ipa_mem_base + ipa3_ctx->ctrl->ipa_reg_base_ofst, + ipa3_ctx->mmio, + resource_p->ipa_mem_size); + + /* IPA version 3.0 IPAHAL used to load the firmwares and + * there is no SMMU so IPAHAL is initialized here.*/ + if (ipa3_ctx->ipa_hw_type == IPA_HW_v3_0) { + if (ipahal_init(ipa3_ctx->ipa_hw_type, ipa3_ctx->mmio, + ipa3_ctx->ipa_cfg_offset, &ipa3_ctx->master_pdev->dev)) { + IPAERR("fail to init ipahal\n"); + result = -EFAULT; + goto fail_remap; + } + } + + INIT_LIST_HEAD(&ipa3_ctx->minidump_list_head); + + /* + * Setup access for register collection/dump on crash + */ + if (ipa_reg_save_init(IPA_MEM_INIT_VAL) != 0) { + result = -EFAULT; + goto fail_gsi_map; + } + + mutex_init(&ipa3_ctx->ipa3_active_clients.mutex); + + IPA_ACTIVE_CLIENTS_PREP_SPECIAL(log_info, "PROXY_CLK_VOTE"); + ipa3_active_clients_log_inc(&log_info, false); + ipa3_ctx->q6_proxy_clk_vote_valid = true; + ipa3_ctx->q6_proxy_clk_vote_cnt = 1; + + /*Updating the proxy vote cnt 1 */ + atomic_set(&ipa3_ctx->ipa3_active_clients.cnt, 1); + + /* Create workqueues for power management */ + ipa3_ctx->power_mgmt_wq = alloc_workqueue("ipa_power_mgmt", + WQ_MEM_RECLAIM | WQ_UNBOUND | WQ_SYSFS | WQ_HIGHPRI, 1); + if (!ipa3_ctx->power_mgmt_wq) { + IPAERR("failed to create power mgmt wq\n"); + result = -ENOMEM; + goto fail_gsi_map; + } + mutex_init(&ipa3_ctx->recycle_stats_collection_lock); + memset(&ipa3_ctx->recycle_stats, 0, sizeof(struct ipa_lnx_pipe_page_recycling_stats)); + memset(&ipa3_ctx->prev_coal_recycle_stats, 0, sizeof(struct ipa3_page_recycle_stats)); + memset(&ipa3_ctx->prev_default_recycle_stats, 0, sizeof(struct ipa3_page_recycle_stats)); + memset(&ipa3_ctx->prev_low_lat_data_recycle_stats, 0, sizeof(struct ipa3_page_recycle_stats)); + + ipa3_ctx->transport_power_mgmt_wq = + create_singlethread_workqueue("transport_power_mgmt"); + if (!ipa3_ctx->transport_power_mgmt_wq) { + IPAERR("failed to create transport power mgmt wq\n"); + result = -ENOMEM; + goto fail_create_transport_wq; + } + + /* Create workqueue for recycle stats collection */ + ipa3_ctx->collect_recycle_stats_wq = + create_singlethread_workqueue("page_recycle_stats_collection"); + if (!ipa3_ctx->collect_recycle_stats_wq) { + IPAERR("failed to create page recycling stats collection wq\n"); + result = -ENOMEM; + goto fail_create_recycle_stats_wq; + } + memset(&ipa3_ctx->recycle_stats, 0, + sizeof(ipa3_ctx->recycle_stats)); + + mutex_init(&ipa3_ctx->transport_pm.transport_pm_mutex); + + /* init the lookaside cache */ + ipa3_ctx->flt_rule_cache = kmem_cache_create("IPA_FLT", + sizeof(struct ipa3_flt_entry), 0, 0, NULL); + if (!ipa3_ctx->flt_rule_cache) { + IPAERR(":ipa flt cache create failed\n"); + result = -ENOMEM; + goto fail_flt_rule_cache; + } + ipa3_ctx->rt_rule_cache = kmem_cache_create("IPA_RT", + sizeof(struct ipa3_rt_entry), 0, 0, NULL); + if (!ipa3_ctx->rt_rule_cache) { + IPAERR(":ipa rt cache create failed\n"); + result = -ENOMEM; + goto fail_rt_rule_cache; + } + ipa3_ctx->hdr_cache = kmem_cache_create("IPA_HDR", + sizeof(struct ipa3_hdr_entry), 0, 0, NULL); + if (!ipa3_ctx->hdr_cache) { + IPAERR(":ipa hdr cache create failed\n"); + result = -ENOMEM; + goto fail_hdr_cache; + } + ipa3_ctx->hdr_offset_cache = + kmem_cache_create("IPA_HDR_OFFSET", + sizeof(struct ipa_hdr_offset_entry), 0, 0, NULL); + if (!ipa3_ctx->hdr_offset_cache) { + IPAERR(":ipa hdr off cache create failed\n"); + result = -ENOMEM; + goto fail_hdr_offset_cache; + } + ipa3_ctx->fnr_stats_cache = kmem_cache_create("IPA_FNR_STATS", + sizeof(struct ipa_ioc_flt_rt_counter_alloc), 0, 0, NULL); + if (!ipa3_ctx->fnr_stats_cache) { + IPAERR(":ipa fnr stats cache create failed\n"); + result = -ENOMEM; + goto fail_fnr_stats_cache; + } + ipa3_ctx->hdr_proc_ctx_cache = kmem_cache_create("IPA_HDR_PROC_CTX", + sizeof(struct ipa3_hdr_proc_ctx_entry), 0, 0, NULL); + if (!ipa3_ctx->hdr_proc_ctx_cache) { + IPAERR(":ipa hdr proc ctx cache create failed\n"); + result = -ENOMEM; + goto fail_hdr_proc_ctx_cache; + } + ipa3_ctx->hdr_proc_ctx_offset_cache = + kmem_cache_create("IPA_HDR_PROC_CTX_OFFSET", + sizeof(struct ipa3_hdr_proc_ctx_offset_entry), 0, 0, NULL); + if (!ipa3_ctx->hdr_proc_ctx_offset_cache) { + IPAERR(":ipa hdr proc ctx off cache create failed\n"); + result = -ENOMEM; + goto fail_hdr_proc_ctx_offset_cache; + } + ipa3_ctx->rt_tbl_cache = kmem_cache_create("IPA_RT_TBL", + sizeof(struct ipa3_rt_tbl), 0, 0, NULL); + if (!ipa3_ctx->rt_tbl_cache) { + IPAERR(":ipa rt tbl cache create failed\n"); + result = -ENOMEM; + goto fail_rt_tbl_cache; + } + ipa3_ctx->tx_pkt_wrapper_cache = + kmem_cache_create("IPA_TX_PKT_WRAPPER", + sizeof(struct ipa3_tx_pkt_wrapper), 0, 0, NULL); + if (!ipa3_ctx->tx_pkt_wrapper_cache) { + IPAERR(":ipa tx pkt wrapper cache create failed\n"); + result = -ENOMEM; + goto fail_tx_pkt_wrapper_cache; + } + ipa3_ctx->rx_pkt_wrapper_cache = + kmem_cache_create("IPA_RX_PKT_WRAPPER", + sizeof(struct ipa3_rx_pkt_wrapper), 0, 0, NULL); + if (!ipa3_ctx->rx_pkt_wrapper_cache) { + IPAERR(":ipa rx pkt wrapper cache create failed\n"); + result = -ENOMEM; + goto fail_rx_pkt_wrapper_cache; + } + + /* Init the various list heads for both SRAM/DDR */ + for (hdr_tbl = HDR_TBL_LCL; hdr_tbl < HDR_TBLS_TOTAL; hdr_tbl++) { + INIT_LIST_HEAD(&ipa3_ctx->hdr_tbl[hdr_tbl].head_hdr_entry_list); + for (i = 0; i < IPA_HDR_BIN_MAX; i++) { + INIT_LIST_HEAD(&ipa3_ctx->hdr_tbl[hdr_tbl].head_offset_list[i]); + INIT_LIST_HEAD(&ipa3_ctx->hdr_tbl[hdr_tbl].head_free_offset_list[i]); + } + } + INIT_LIST_HEAD(&ipa3_ctx->hdr_proc_ctx_tbl.head_proc_ctx_entry_list); + for (i = 0; i < IPA_HDR_PROC_CTX_BIN_MAX; i++) { + INIT_LIST_HEAD( + &ipa3_ctx->hdr_proc_ctx_tbl.head_offset_list[i]); + INIT_LIST_HEAD( + &ipa3_ctx->hdr_proc_ctx_tbl.head_free_offset_list[i]); + } + INIT_LIST_HEAD(&ipa3_ctx->rt_tbl_set[IPA_IP_v4].head_rt_tbl_list); + idr_init(&ipa3_ctx->rt_tbl_set[IPA_IP_v4].rule_ids); + INIT_LIST_HEAD(&ipa3_ctx->rt_tbl_set[IPA_IP_v6].head_rt_tbl_list); + idr_init(&ipa3_ctx->rt_tbl_set[IPA_IP_v6].rule_ids); + + rset = &ipa3_ctx->reap_rt_tbl_set[IPA_IP_v4]; + INIT_LIST_HEAD(&rset->head_rt_tbl_list); + idr_init(&rset->rule_ids); + rset = &ipa3_ctx->reap_rt_tbl_set[IPA_IP_v6]; + INIT_LIST_HEAD(&rset->head_rt_tbl_list); + idr_init(&rset->rule_ids); + idr_init(&ipa3_ctx->flt_rt_counters.hdl); + spin_lock_init(&ipa3_ctx->flt_rt_counters.hdl_lock); + memset(&ipa3_ctx->flt_rt_counters.used_hw, 0, + sizeof(ipa3_ctx->flt_rt_counters.used_hw)); + memset(&ipa3_ctx->flt_rt_counters.used_sw, 0, + sizeof(ipa3_ctx->flt_rt_counters.used_sw)); + + INIT_LIST_HEAD(&ipa3_ctx->intf_list); + INIT_LIST_HEAD(&ipa3_ctx->msg_list); + INIT_LIST_HEAD(&ipa3_ctx->pull_msg_list); + init_waitqueue_head(&ipa3_ctx->msg_waitq); + mutex_init(&ipa3_ctx->msg_lock); + + /* store wlan client-connect-msg-list */ + INIT_LIST_HEAD(&ipa3_ctx->msg_wlan_client_list); + mutex_init(&ipa3_ctx->msg_wlan_client_lock); + + mutex_init(&ipa3_ctx->q6_proxy_clk_vote_mutex); + mutex_init(&ipa3_ctx->ipa_cne_evt_lock); + mutex_init(&ipa3_ctx->act_tbl_lock); + + idr_init(&ipa3_ctx->ipa_idr); + spin_lock_init(&ipa3_ctx->idr_lock); + + /* wlan related member */ + memset(&ipa3_ctx->wc_memb, 0, sizeof(ipa3_ctx->wc_memb)); + spin_lock_init(&ipa3_ctx->wc_memb.wlan_spinlock); + spin_lock_init(&ipa3_ctx->wc_memb.ipa_tx_mul_spinlock); + INIT_LIST_HEAD(&ipa3_ctx->wc_memb.wlan_comm_desc_list); + + ipa3_ctx->cdev.class = class_create(THIS_MODULE, DRV_NAME); + + result = alloc_chrdev_region(&ipa3_ctx->cdev.dev_num, 0, 1, DRV_NAME); + if (result) { + IPAERR("alloc_chrdev_region err\n"); + result = -ENODEV; + goto fail_alloc_chrdev_region; + } + + ipa3_ctx->cdev.dev = device_create(ipa3_ctx->cdev.class, NULL, + ipa3_ctx->cdev.dev_num, ipa3_ctx, DRV_NAME); + if (IS_ERR(ipa3_ctx->cdev.dev)) { + IPAERR(":device_create err.\n"); + result = -ENODEV; + goto fail_device_create; + } + + /* Register a wakeup source. */ + ipa3_ctx->w_lock = + wakeup_source_register(&ipa_pdev->dev, "IPA_WS"); + if (!ipa3_ctx->w_lock) { + IPAERR("IPA wakeup source register failed\n"); + result = -ENOMEM; + goto fail_w_source_register; + } + spin_lock_init(&ipa3_ctx->wakelock_ref_cnt.spinlock); + + /* Initialize Power Management framework */ + result = ipa_pm_init(&ipa3_res.pm_init); + if (result) { + IPAERR("IPA PM initialization failed (%d)\n", -result); + result = -ENODEV; + goto fail_ipa_pm_init; + } + IPADBG("IPA power manager initialized\n"); + + init_completion(&ipa3_ctx->init_completion_obj); + init_completion(&ipa3_ctx->uc_loaded_completion_obj); + + result = ipa3_dma_setup(); + if (result) { + IPAERR("Failed to setup IPA DMA\n"); + result = -ENODEV; + goto fail_ipa_dma_setup; + } + + /* + * We can't register the GSI driver yet, as it expects + * the GSI FW to be up and running before the registration. + * + * For IPA3.0 and the emulation system, the GSI configuration + * is done by the GSI driver. + * + * For IPA3.1 (and on), the GSI configuration is done by TZ. + */ + if (ipa3_ctx->ipa_hw_type == IPA_HW_v3_0 || + ipa3_ctx->ipa3_hw_mode == IPA_HW_MODE_EMULATION) { + result = ipa3_gsi_pre_fw_load_init(); + if (result) { + IPAERR("gsi pre FW loading config failed\n"); + result = -ENODEV; + goto fail_gsi_pre_fw_load_init; + } + } + + cdev = &ipa3_ctx->cdev.cdev; + cdev_init(cdev, &ipa3_drv_fops); + cdev->owner = THIS_MODULE; + cdev->ops = &ipa3_drv_fops; /* from LDD3 */ + + result = cdev_add(cdev, ipa3_ctx->cdev.dev_num, 1); + if (result) { + IPAERR(":cdev_add err=%d\n", -result); + result = -ENODEV; + goto fail_cdev_add; + } + IPADBG("ipa cdev added successful. major:%d minor:%d\n", + MAJOR(ipa3_ctx->cdev.dev_num), + MINOR(ipa3_ctx->cdev.dev_num)); + + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_1) { + result = ipa_odl_init(); + if (result) { + IPADBG("Error: ODL init fialed\n"); + result = -ENODEV; + goto fail_odl_init; + } + } + + /* + * for IPA 4.0 offline charge is not needed and we need to prevent + * power collapse until IPA uC is loaded. + */ + + /* proxy vote for modem is added in ipa3_post_init() phase */ + if (ipa3_ctx->ipa_hw_type != IPA_HW_v4_0) + ipa3_proxy_clk_unvote(); + + /* Create the dummy netdev for LAN RX NAPI*/ + ipa3_enable_napi_netdev(); + + result = ipa3_wwan_init(); + if (result) { + IPAERR(":ipa3_wwan_init err=%d\n", -result); + result = -ENODEV; + goto fail_wwan_init; + } + + if (ipa3_ctx->rmnet_ctl_enable) { + result = ipa3_rmnet_ctl_init(); + if (result) { + IPAERR(":ipa3_rmnet_ctl_init err=%d\n", -result); + result = -ENODEV; + goto fail_rmnet_ctl_init; + } + } + + if (ipa3_ctx->rmnet_ll_enable) { + result = ipa3_rmnet_ll_init(); + if (result) { + IPAERR(":ipa3_rmnet_ll_init err=%d\n", -result); + result = -ENODEV; + goto fail_rmnet_ll_init; + } + } + ipa3_ctx->ipa_rmnet_notifier_list_internal = &ipa_rmnet_notifier_list; + spin_lock_init(&ipa3_ctx->notifier_lock); + ipa3_ctx->buff_above_thresh_for_def_pipe_notified = false; + ipa3_ctx->buff_above_thresh_for_coal_pipe_notified = false; + ipa3_ctx->buff_below_thresh_for_def_pipe_notified = false; + ipa3_ctx->buff_below_thresh_for_coal_pipe_notified = false; + ipa3_ctx->buff_above_thresh_for_ll_pipe_notified = false; + ipa3_ctx->buff_below_thresh_for_ll_pipe_notified = false; + ipa3_ctx->free_page_task_scheduled = false; + + mutex_init(&ipa3_ctx->app_clock_vote.mutex); + mutex_init(&ipa3_ctx->ssr_lock); + ipa3_ctx->is_modem_up = false; + ipa3_ctx->mhi_ctrl_state = IPA_MHI_CTRL_NOT_SETUP; + +#if IS_ENABLED(CONFIG_QCOM_VA_MINIDUMP) + result = qcom_va_md_register("ipa_mini", &qcom_va_md_ipa_notif_blk); + + if(result) + IPAERR("ipa mini qcom_va_md_register failed = %d\n", result); + else + IPADBG("ipa mini qcom_va_md_register success\n"); +#endif + return 0; + +fail_rmnet_ll_init: +fail_rmnet_ctl_init: + ipa3_wwan_cleanup(); +fail_wwan_init: + ipa3_disable_napi_netdev(); + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_1) + ipa_odl_cleanup(); +fail_odl_init: + cdev_del(cdev); +fail_cdev_add: +fail_gsi_pre_fw_load_init: + ipa3_dma_shutdown(); +fail_ipa_dma_setup: + ipa_pm_destroy(); +fail_w_source_register: + device_destroy(ipa3_ctx->cdev.class, ipa3_ctx->cdev.dev_num); +fail_ipa_pm_init: + wakeup_source_unregister(ipa3_ctx->w_lock); + ipa3_ctx->w_lock = NULL; +fail_device_create: + unregister_chrdev_region(ipa3_ctx->cdev.dev_num, 1); +fail_alloc_chrdev_region: + idr_destroy(&ipa3_ctx->ipa_idr); + rset = &ipa3_ctx->reap_rt_tbl_set[IPA_IP_v6]; + idr_destroy(&rset->rule_ids); + rset = &ipa3_ctx->reap_rt_tbl_set[IPA_IP_v4]; + idr_destroy(&rset->rule_ids); + idr_destroy(&ipa3_ctx->rt_tbl_set[IPA_IP_v6].rule_ids); + idr_destroy(&ipa3_ctx->rt_tbl_set[IPA_IP_v4].rule_ids); + kmem_cache_destroy(ipa3_ctx->rx_pkt_wrapper_cache); +fail_rx_pkt_wrapper_cache: + kmem_cache_destroy(ipa3_ctx->tx_pkt_wrapper_cache); +fail_tx_pkt_wrapper_cache: + kmem_cache_destroy(ipa3_ctx->rt_tbl_cache); +fail_rt_tbl_cache: + kmem_cache_destroy(ipa3_ctx->hdr_proc_ctx_offset_cache); +fail_hdr_proc_ctx_offset_cache: + kmem_cache_destroy(ipa3_ctx->hdr_proc_ctx_cache); +fail_hdr_proc_ctx_cache: + kmem_cache_destroy(ipa3_ctx->fnr_stats_cache); +fail_fnr_stats_cache: + kmem_cache_destroy(ipa3_ctx->hdr_offset_cache); +fail_hdr_offset_cache: + kmem_cache_destroy(ipa3_ctx->hdr_cache); +fail_hdr_cache: + kmem_cache_destroy(ipa3_ctx->rt_rule_cache); +fail_rt_rule_cache: + kmem_cache_destroy(ipa3_ctx->flt_rule_cache); +fail_flt_rule_cache: + destroy_workqueue(ipa3_ctx->collect_recycle_stats_wq); +fail_create_recycle_stats_wq: + destroy_workqueue(ipa3_ctx->transport_power_mgmt_wq); +fail_create_transport_wq: + destroy_workqueue(ipa3_ctx->power_mgmt_wq); +fail_gsi_map: + if (ipa3_ctx->reg_collection_base) + iounmap(ipa3_ctx->reg_collection_base); + iounmap(ipa3_ctx->mmio); +fail_remap: + ipa3_disable_clks(); + ipa3_active_clients_log_destroy(); + gsi_unmap_base(); +fail_init_active_client: + if (ipa3_clk) + clk_put(ipa3_clk); + ipa3_clk = NULL; +fail_bus_reg: + for (i = 0; i < ipa3_ctx->icc_num_paths; i++) + if (IS_ERR_OR_NULL(ipa3_ctx->ctrl->icc_path[i])) { + ipa3_ctx->ctrl->icc_path[i] = NULL; + break; + } else { + icc_put(ipa3_ctx->ctrl->icc_path[i]); + ipa3_ctx->ctrl->icc_path[i] = NULL; + } +fail_init_mem_partition: +fail_bind: + kfree(ipa3_ctx->ctrl); + ipa3_ctx->ctrl = NULL; +fail_mem_ctrl: + kfree(ipa3_ctx->ipa_tz_unlock_reg); + ipa3_ctx->ipa_tz_unlock_reg = NULL; +fail_tz_unlock_reg: + if (ipa3_ctx->logbuf) { + ipc_log_context_destroy(ipa3_ctx->logbuf); + ipa3_ctx->logbuf = NULL; + } +fail_uc_file_alloc: + kfree(ipa3_ctx->gsi_fw_file_name); + ipa3_ctx->gsi_fw_file_name = NULL; +fail_gsi_file_alloc: +fail_mem_ctx: + return result; +} + +static int get_ipa_dts_pm_info(struct platform_device *pdev, + struct ipa3_plat_drv_res *ipa_drv_res) +{ + int result; + int i, j; + + /* this interconnects entry must be presented */ + if (!of_find_property(pdev->dev.of_node, + "interconnects", NULL)) { + IPAERR("No interconnect info\n"); + return -EFAULT; + } + + result = of_property_read_u32(pdev->dev.of_node, + "qcom,interconnect,num-cases", + &ipa_drv_res->icc_num_cases); + /* No vote is ignored */ + ipa_drv_res->pm_init.threshold_size = + ipa_drv_res->icc_num_cases - 2; + if (result || ipa_drv_res->pm_init.threshold_size > + IPA_PM_THRESHOLD_MAX) { + IPAERR("invalid qcom,interconnect,num-cases %d\n", + ipa_drv_res->pm_init.threshold_size); + return -EFAULT; + } + + result = of_property_read_u32(pdev->dev.of_node, + "qcom,interconnect,num-paths", + &ipa_drv_res->icc_num_paths); + if (result || ipa_drv_res->icc_num_paths > + IPA_ICC_PATH_MAX) { + IPAERR("invalid qcom,interconnect,num-paths %d\n", + ipa_drv_res->icc_num_paths); + return -EFAULT; + } + + for (i = 0; i < ipa_drv_res->icc_num_paths; i++) { + result = of_property_read_string_index(pdev->dev.of_node, + "interconnect-names", + i, + &ipa_drv_res->icc_path_name[i]); + if (result) { + IPAERR("invalid interconnect-names %d\n", i); + return -EFAULT; + } + } + /* read no-vote AB IB value */ + result = of_property_read_u32_array(pdev->dev.of_node, + "qcom,no-vote", + ipa_drv_res->icc_clk_val[IPA_ICC_NONE], + ipa_drv_res->icc_num_paths * + IPA_ICC_TYPE_MAX); + if (result) { + IPAERR("invalid property qcom,no-vote\n"); + return -EFAULT; + } + + /* read svs2 AB IB value */ + result = of_property_read_u32_array(pdev->dev.of_node, + "qcom,svs2", + ipa_drv_res->icc_clk_val[IPA_ICC_SVS2], + ipa_drv_res->icc_num_paths * + IPA_ICC_TYPE_MAX); + if (result) { + IPAERR("invalid property qcom,svs2\n"); + return -EFAULT; + } + + /* read svs AB IB value */ + result = of_property_read_u32_array(pdev->dev.of_node, + "qcom,svs", + ipa_drv_res->icc_clk_val[IPA_ICC_SVS], + ipa_drv_res->icc_num_paths * + IPA_ICC_TYPE_MAX); + if (result) { + IPAERR("invalid property qcom,svs\n"); + return -EFAULT; + } + + /* read nominal AB IB value */ + result = of_property_read_u32_array(pdev->dev.of_node, + "qcom,nominal", + ipa_drv_res->icc_clk_val[IPA_ICC_NOMINAL], + ipa_drv_res->icc_num_paths * + IPA_ICC_TYPE_MAX); + if (result) { + IPAERR("invalid property qcom,nominal\n"); + return -EFAULT; + } + + /* read turbo AB IB value */ + result = of_property_read_u32_array(pdev->dev.of_node, + "qcom,turbo", + ipa_drv_res->icc_clk_val[IPA_ICC_TURBO], + ipa_drv_res->icc_num_paths * + IPA_ICC_TYPE_MAX); + if (result) { + IPAERR("invalid property qcom,turbo\n"); + return -EFAULT; + } + + result = of_property_read_u32_array(pdev->dev.of_node, + "qcom,throughput-threshold", + ipa_drv_res->pm_init.default_threshold, + ipa_drv_res->pm_init.threshold_size); + if (result) { + IPAERR("failed to read qcom,throughput-thresholds\n"); + return -EFAULT; + } + + result = of_property_count_strings(pdev->dev.of_node, + "qcom,scaling-exceptions"); + if (result < 0) { + IPADBG("no exception list for ipa pm\n"); + result = 0; + } + + if (result % (ipa_drv_res->pm_init.threshold_size + 1)) { + IPAERR("failed to read qcom,scaling-exceptions\n"); + return -EFAULT; + } + + ipa_drv_res->pm_init.exception_size = result / + (ipa_drv_res->pm_init.threshold_size + 1); + if (ipa_drv_res->pm_init.exception_size >= + IPA_PM_EXCEPTION_MAX) { + IPAERR("exception list larger then max %d\n", + ipa_drv_res->pm_init.exception_size); + return -EFAULT; + } + + for (i = 0; i < ipa_drv_res->pm_init.exception_size; i++) { + struct ipa_pm_exception *ex = ipa_drv_res->pm_init.exceptions; + + result = of_property_read_string_index(pdev->dev.of_node, + "qcom,scaling-exceptions", + i * (ipa_drv_res->pm_init.threshold_size + 1), + &ex[i].usecase); + if (result) { + IPAERR("failed to read qcom,scaling-exceptions"); + return -EFAULT; + } + + for (j = 0; j < ipa_drv_res->pm_init.threshold_size; j++) { + const char *str; + + result = of_property_read_string_index( + pdev->dev.of_node, + "qcom,scaling-exceptions", + i * (ipa_drv_res->pm_init.threshold_size + 1) + + j + 1, + &str); + if (result) { + IPAERR("failed to read qcom,scaling-exceptions" + ); + return -EFAULT; + } + + if (kstrtou32(str, 0, &ex[i].threshold[j])) { + IPAERR("error str=%s\n", str); + return -EFAULT; + } + } + } + + return 0; +} + +static void get_dts_tx_wrapper_cache_size(struct platform_device *pdev, + struct ipa3_plat_drv_res *ipa_drv_res) +{ + int result; + + result = of_property_read_u32 ( + pdev->dev.of_node, + "qcom,tx-wrapper-cache-max-size", + &ipa_drv_res->tx_wrapper_cache_max_size); + if (result) + ipa_drv_res->tx_wrapper_cache_max_size = 0; + + IPADBG("tx_wrapper_cache_max_size is set to %d", + ipa_drv_res->tx_wrapper_cache_max_size); +} + +static void get_dts_ipa_gen_rx_cmn_page_pool_sz_factor(struct platform_device *pdev, + struct ipa3_plat_drv_res *ipa_drv_res) +{ + int result; + + result = of_property_read_u32 ( + pdev->dev.of_node, + "qcom,ipa-gen-rx-cmn-page-pool-sz-factor", + &ipa_drv_res->ipa_gen_rx_cmn_page_pool_sz_factor); + if (result) + ipa_drv_res->ipa_gen_rx_cmn_page_pool_sz_factor = 0; + + IPADBG("ipa_gen_rx_cmn_page_pool_sz_factor is set to %d", + ipa_drv_res->ipa_gen_rx_cmn_page_pool_sz_factor); +} + +static void get_dts_ipa_gen_rx_cmn_temp_pool_sz_factor(struct platform_device *pdev, + struct ipa3_plat_drv_res *ipa_drv_res) +{ + int result; + + result = of_property_read_u32 ( + pdev->dev.of_node, + "qcom,ipa-gen-rx-cmn-temp-pool-sz-factor", + &ipa_drv_res->ipa_gen_rx_cmn_temp_pool_sz_factor); + if (result) + ipa_drv_res->ipa_gen_rx_cmn_temp_pool_sz_factor = 0; + + IPADBG("ipa_gen_rx_cmn_temp_pool_sz_factor is set to %d", + ipa_drv_res->ipa_gen_rx_cmn_temp_pool_sz_factor); +} + +static void get_dts_ipa_gen_rx_ll_page_pool_sz_factor(struct platform_device *pdev, + struct ipa3_plat_drv_res *ipa_drv_res) +{ + int result; + + result = of_property_read_u32 ( + pdev->dev.of_node, + "qcom,ipa-gen-rx-ll-pool-sz-factor", + &ipa_drv_res->ipa_gen_rx_ll_pool_sz_factor); + if (result) + ipa_drv_res->ipa_gen_rx_ll_pool_sz_factor = 0; + + IPADBG("ipa_gen_rx_ll_pool_sz_factor is set to %d", + ipa_drv_res->ipa_gen_rx_ll_pool_sz_factor); +} + +static void ipa_dts_get_ulso_data(struct platform_device *pdev, + struct ipa3_plat_drv_res *ipa_drv_res) +{ + int result; + u32 tmp; + + ipa_drv_res->ulso_supported = of_property_read_bool(pdev->dev.of_node, + "qcom,ulso-supported"); + IPADBG(": ulso_supported = %d", ipa_drv_res->ulso_supported); + if (!ipa_drv_res->ulso_supported) + return; + + result = of_property_read_u32( + pdev->dev.of_node, + "qcom,ulso-ip-id-min-linux-val", + &tmp); + if (result) { + ipa_drv_res->ulso_ip_id_min = 0; + } else { + ipa_drv_res->ulso_ip_id_min = tmp; + } + IPADBG("ulso_ip_id_min is set to %d", + ipa_drv_res->ulso_ip_id_min); + + result = of_property_read_u32( + pdev->dev.of_node, + "qcom,ulso-ip-id-max-linux-val", + &tmp); + if (result) { + ipa_drv_res->ulso_ip_id_max = 0xffff; + } else { + ipa_drv_res->ulso_ip_id_max = tmp; + } + IPADBG("ulso_ip_id_max is set to %d", + ipa_drv_res->ulso_ip_id_max); +} + +static int get_ipa_dts_configuration(struct platform_device *pdev, + struct ipa3_plat_drv_res *ipa_drv_res) +{ + int i, result, pos, irq = 0; + struct resource *resource; + u32 *ipa_tz_unlock_reg; + int elem_num; + u32 mhi_evid_limits[2]; + u32 ipa_holb_monitor_poll_period; + u32 ipa_holb_monitor_max_cnt_wlan; + u32 ipa_holb_monitor_max_cnt_usb; + u32 ipa_holb_monitor_max_cnt_11ad; + u32 ipa_wan_aggr_pkt_cnt; + + /* initialize ipa3_res */ + ipa_drv_res->ipa_wdi3_2g_holb_timeout = 0; + ipa_drv_res->ipa_wdi3_5g_holb_timeout = 0; + ipa_drv_res->ipa_pipe_mem_start_ofst = IPA_PIPE_MEM_START_OFST; + ipa_drv_res->ipa_pipe_mem_size = IPA_PIPE_MEM_SIZE; + ipa_drv_res->ipa_hw_type = 0; + ipa_drv_res->ipa3_hw_mode = 0; + ipa_drv_res->platform_type = 0; + ipa_drv_res->modem_cfg_emb_pipe_flt = false; + ipa_drv_res->ipa_wdi2 = false; + ipa_drv_res->ipa_wan_skb_page = false; + ipa_drv_res->ipa_use_uc_holb_monitor = false; + ipa_drv_res->ipa_wdi2_over_gsi = false; + ipa_drv_res->ipa_wdi3_over_gsi = false; + ipa_drv_res->use_xbl_boot = false; + ipa_drv_res->ipa_mhi_dynamic_config = false; + ipa_drv_res->use_64_bit_dma_mask = false; + ipa_drv_res->use_bw_vote = false; + ipa_drv_res->wan_rx_ring_size = IPA_GENERIC_RX_POOL_SZ_WAN; + ipa_drv_res->lan_rx_ring_size = IPA_GENERIC_RX_POOL_SZ; + ipa_drv_res->apply_rg10_wa = false; + ipa_drv_res->gsi_ch20_wa = false; + ipa_drv_res->ipa_tz_unlock_reg_num = 0; + ipa_drv_res->ipa_tz_unlock_reg = NULL; + ipa_drv_res->mhi_evid_limits[0] = IPA_MHI_GSI_EVENT_RING_ID_START; + ipa_drv_res->mhi_evid_limits[1] = IPA_MHI_GSI_EVENT_RING_ID_END; + ipa_drv_res->ipa_fltrt_not_hashable = false; + ipa_drv_res->ipa_endp_delay_wa = false; + ipa_drv_res->skip_ieob_mask_wa = false; + ipa_drv_res->ipa_gpi_event_rp_ddr = false; + ipa_drv_res->ipa_config_is_auto = false; + ipa_drv_res->max_num_smmu_cb = IPA_SMMU_CB_MAX; + ipa_drv_res->ipa_endp_delay_wa_v2 = false; + ipa_drv_res->use_tput_est_ep = false; + ipa_drv_res->rmnet_ctl_enable = 0; + ipa_drv_res->rmnet_ll_enable = 0; + ipa_drv_res->ulso_wa = false; + ipa_drv_res->coal_ipv4_id_ignore = true; + + /* Get IPA HW Version */ + result = of_property_read_u32(pdev->dev.of_node, "qcom,ipa-hw-ver", + &ipa_drv_res->ipa_hw_type); + if ((result) || (ipa_drv_res->ipa_hw_type == IPA_HW_None)) { + IPAERR(":get resource failed for ipa-hw-ver\n"); + return -ENODEV; + } + IPADBG(": ipa_hw_type = %d", ipa_drv_res->ipa_hw_type); + + if (ipa_drv_res->ipa_hw_type < IPA_HW_v3_0) { + IPAERR(":IPA version below 3.0 not supported\n"); + return -ENODEV; + } + + if (ipa_drv_res->ipa_hw_type >= IPA_HW_MAX) { + IPAERR(":IPA version is greater than the MAX\n"); + return -ENODEV; + } + + /* Get IPA HW mode */ + result = of_property_read_u32(pdev->dev.of_node, "qcom,ipa-hw-mode", + &ipa_drv_res->ipa3_hw_mode); + if (result) + IPADBG("using default (IPA_MODE_NORMAL) for ipa-hw-mode\n"); + else + IPADBG(": found ipa_drv_res->ipa3_hw_mode = %d", + ipa_drv_res->ipa3_hw_mode); + + /* Get Platform Type */ + result = of_property_read_u32(pdev->dev.of_node, "qcom,platform-type", + &ipa_drv_res->platform_type); + if (result) + IPADBG("using default (IPA_PLAT_TYPE_MDM) for platform-type\n"); + else + IPADBG(": found ipa_drv_res->platform_type = %d", + ipa_drv_res->platform_type); + + /* Get IPA WAN / LAN RX pool size */ + result = of_property_read_u32(pdev->dev.of_node, + "qcom,wan-rx-ring-size", + &ipa_drv_res->wan_rx_ring_size); + if (result) + IPADBG("using default for wan-rx-ring-size = %u\n", + ipa_drv_res->wan_rx_ring_size); + else + IPADBG(": found ipa_drv_res->wan-rx-ring-size = %u", + ipa_drv_res->wan_rx_ring_size); + + result = of_property_read_u32(pdev->dev.of_node, + "qcom,lan-rx-ring-size", + &ipa_drv_res->lan_rx_ring_size); + if (result) + IPADBG("using default for lan-rx-ring-size = %u\n", + ipa_drv_res->lan_rx_ring_size); + else + IPADBG(": found ipa_drv_res->lan-rx-ring-size = %u", + ipa_drv_res->lan_rx_ring_size); + + ipa_drv_res->use_ipa_teth_bridge = + of_property_read_bool(pdev->dev.of_node, + "qcom,use-ipa-tethering-bridge"); + IPADBG(": using ipa teth bridge = %s", + ipa_drv_res->use_ipa_teth_bridge + ? "True" : "False"); + + ipa_drv_res->ipa_mhi_dynamic_config = + of_property_read_bool(pdev->dev.of_node, + "qcom,use-ipa-in-mhi-mode"); + IPADBG(": ipa_mhi_dynamic_config (%s)\n", + ipa_drv_res->ipa_mhi_dynamic_config + ? "True" : "False"); + + ipa_drv_res->modem_cfg_emb_pipe_flt = + of_property_read_bool(pdev->dev.of_node, + "qcom,modem-cfg-emb-pipe-flt"); + IPADBG(": modem configure embedded pipe filtering = %s\n", + ipa_drv_res->modem_cfg_emb_pipe_flt + ? "True" : "False"); + ipa_drv_res->ipa_wdi2_over_gsi = + of_property_read_bool(pdev->dev.of_node, + "qcom,ipa-wdi2_over_gsi"); + IPADBG(": WDI-2.0 over gsi= %s\n", + ipa_drv_res->ipa_wdi2_over_gsi + ? "True" : "False"); + + ipa_drv_res->ipa_endp_delay_wa = + of_property_read_bool(pdev->dev.of_node, + "qcom,ipa-endp-delay-wa"); + IPADBG(": endppoint delay wa = %s\n", + ipa_drv_res->ipa_endp_delay_wa + ? "True" : "False"); + + ipa_drv_res->ipa_endp_delay_wa_v2 = + of_property_read_bool(pdev->dev.of_node, + "qcom,ipa-endp-delay-wa-v2"); + IPADBG(": endppoint delay wa v2 = %s\n", + ipa_drv_res->ipa_endp_delay_wa_v2 + ? "True" : "False"); + + /** + * Overwrite end point delay workaround for + * APQ target as device tree is same + * for MSM and APQ + */ + if (ipa_drv_res->platform_type == IPA_PLAT_TYPE_APQ) { + ipa_drv_res->ipa_endp_delay_wa = true; + ipa_drv_res->ipa_endp_delay_wa_v2 = false; + } + + + ipa_drv_res->ulso_wa = of_property_read_bool(pdev->dev.of_node, + "qcom,ipa-ulso-wa"); + IPADBG(": ipa-ulso wa = %s\n", + ipa_drv_res->ulso_wa + ? "True" : "False"); + + ipa_drv_res->ipa_wdi3_over_gsi = + of_property_read_bool(pdev->dev.of_node, + "qcom,ipa-wdi3-over-gsi"); + IPADBG(": WDI-3.0 over gsi= %s\n", + ipa_drv_res->ipa_wdi3_over_gsi + ? "True" : "False"); + + ipa_drv_res->ipa_wdi2 = + of_property_read_bool(pdev->dev.of_node, + "qcom,ipa-wdi2"); + IPADBG(": WDI-2.0 = %s\n", + ipa_drv_res->ipa_wdi2 + ? "True" : "False"); + + ipa_drv_res->ipa_config_is_auto = + of_property_read_bool(pdev->dev.of_node, + "qcom,ipa-config-is-auto"); + IPADBG(": ipa-config-is-auto = %s\n", + ipa_drv_res->ipa_config_is_auto + ? "True" : "False"); + + ipa_drv_res->ipa_wan_skb_page = + of_property_read_bool(pdev->dev.of_node, + "qcom,wan-use-skb-page"); + IPADBG(": Use skb page = %s\n", + ipa_drv_res->ipa_wan_skb_page + ? "True" : "False"); + + ipa_drv_res->ipa_use_uc_holb_monitor = + of_property_read_bool(pdev->dev.of_node, + "qcom,ipa-uc-holb-monitor"); + IPADBG(": uC HOLB monitor = %s\n", + ipa_drv_res->ipa_use_uc_holb_monitor + ? "True" : "False"); + + /* Get HOLB Monitor Polling Period */ + result = of_property_read_u32(pdev->dev.of_node, + "qcom,ipa-holb-monitor-poll-period", + &ipa_holb_monitor_poll_period); + if (result) { + IPADBG("ipa holb monitor poll period = %u\n", + IPA_HOLB_POLLING_PERIOD_MS); + ipa_holb_monitor_poll_period = IPA_HOLB_POLLING_PERIOD_MS; + } else + IPADBG("ipa holb monitor poll period = %u\n", + ipa_holb_monitor_poll_period); + + ipa_drv_res->ipa_holb_monitor_poll_period = + ipa_holb_monitor_poll_period; + + /* Get HOLB Monitor Max Stuck Cnt Values */ + result = of_property_read_u32(pdev->dev.of_node, + "qcom,ipa-holb-monitor-max-cnt-wlan", + &ipa_holb_monitor_max_cnt_wlan); + if (result) { + IPADBG("ipa holb monitor max count wlan = %u\n", + IPA_HOLB_MONITOR_MAX_STUCK_COUNT); + ipa_holb_monitor_max_cnt_wlan = + IPA_HOLB_MONITOR_MAX_STUCK_COUNT; + } else + IPADBG("ipa holb monitor max count wlan = %u\n", + ipa_holb_monitor_max_cnt_wlan); + + ipa_drv_res->ipa_holb_monitor_max_cnt_wlan = + ipa_holb_monitor_max_cnt_wlan; + + result = of_property_read_u32(pdev->dev.of_node, + "qcom,ipa-holb-monitor-max-cnt-usb", + &ipa_holb_monitor_max_cnt_usb); + if (result) { + IPADBG("ipa holb monitor max count usb = %u\n", + IPA_HOLB_MONITOR_MAX_STUCK_COUNT); + ipa_holb_monitor_max_cnt_usb = + IPA_HOLB_MONITOR_MAX_STUCK_COUNT; + } else + IPADBG("ipa holb monitor max count usb = %u\n", + ipa_holb_monitor_max_cnt_usb); + + ipa_drv_res->ipa_holb_monitor_max_cnt_usb = + ipa_holb_monitor_max_cnt_usb; + + result = of_property_read_u32(pdev->dev.of_node, + "qcom,ipa-holb-monitor-max-cnt-11ad", + &ipa_holb_monitor_max_cnt_11ad); + if (result) { + IPADBG("ipa holb monitor max count 11ad = %u\n", + IPA_HOLB_MONITOR_MAX_STUCK_COUNT); + ipa_holb_monitor_max_cnt_11ad = + IPA_HOLB_MONITOR_MAX_STUCK_COUNT; + } else + IPADBG("ipa holb monitor max count 11ad = %u\n", + ipa_holb_monitor_max_cnt_11ad); + + ipa_drv_res->ipa_holb_monitor_max_cnt_11ad = + ipa_holb_monitor_max_cnt_11ad; + + ipa_drv_res->ipa_fltrt_not_hashable = + of_property_read_bool(pdev->dev.of_node, + "qcom,ipa-fltrt-not-hashable"); + IPADBG(": IPA filter/route rule hashable = %s\n", + ipa_drv_res->ipa_fltrt_not_hashable + ? "True" : "False"); + + ipa_drv_res->use_xbl_boot = + of_property_read_bool(pdev->dev.of_node, + "qcom,use-xbl-boot"); + IPADBG("Is xbl loading used ? (%s)\n", + ipa_drv_res->use_xbl_boot + ? "Yes":"No"); + + ipa_drv_res->use_64_bit_dma_mask = + of_property_read_bool(pdev->dev.of_node, + "qcom,use-64-bit-dma-mask"); + IPADBG(": use_64_bit_dma_mask = %s\n", + ipa_drv_res->use_64_bit_dma_mask + ? "True" : "False"); + + ipa_drv_res->use_bw_vote = + of_property_read_bool(pdev->dev.of_node, + "qcom,bandwidth-vote-for-ipa"); + IPADBG(": use_bw_vote = %s\n", + ipa_drv_res->use_bw_vote + ? "True" : "False"); + ipa_drv_res->skip_ieob_mask_wa = + of_property_read_bool(pdev->dev.of_node, + "qcom,skip-ieob-mask-wa"); + IPADBG(": skip ieob mask wa = %s\n", + ipa_drv_res->skip_ieob_mask_wa + ? "True" : "False"); + + ipa_drv_res->skip_uc_pipe_reset = + of_property_read_bool(pdev->dev.of_node, + "qcom,skip-uc-pipe-reset"); + IPADBG(": skip uC pipe reset = %s\n", + ipa_drv_res->skip_uc_pipe_reset + ? "True" : "False"); + + ipa_drv_res->tethered_flow_control = + of_property_read_bool(pdev->dev.of_node, + "qcom,tethered-flow-control"); + IPADBG(": Use apps based flow control = %s\n", + ipa_drv_res->tethered_flow_control + ? "True" : "False"); + + ipa_drv_res->lan_rx_napi_enable = + of_property_read_bool(pdev->dev.of_node, + "qcom,lan-rx-napi"); + IPADBG(": Enable LAN rx NAPI = %s\n", + ipa_drv_res->lan_rx_napi_enable + ? "True" : "False"); + + ipa_drv_res->ipa_gpi_event_rp_ddr = + of_property_read_bool(pdev->dev.of_node, + "qcom,ipa-gpi-event-rp-ddr"); + IPADBG(": Read GPI or GCI Event RP from DDR = %s\n", + ipa_drv_res->ipa_gpi_event_rp_ddr ? "True" : "False"); + + ipa_drv_res->tx_napi_enable = + of_property_read_bool(pdev->dev.of_node, + "qcom,tx-napi"); + IPADBG(": Enable tx NAPI = %s\n", + ipa_drv_res->tx_napi_enable + ? "True" : "False"); + + ipa_drv_res->tx_poll = of_property_read_bool(pdev->dev.of_node, + "qcom,tx-poll"); + IPADBG(": Enable tx polling = %s\n", ipa_drv_res->tx_poll + ? "True" : "False"); + + if (ipa_drv_res->platform_type != IPA_PLAT_TYPE_APQ) { + ipa_drv_res->rmnet_ctl_enable = + of_property_read_bool(pdev->dev.of_node, + "qcom,rmnet-ctl-enable"); + IPADBG(": Enable rmnet ctl = %s\n", + ipa_drv_res->rmnet_ctl_enable + ? "True" : "False"); + + ipa_drv_res->rmnet_ll_enable = + of_property_read_bool(pdev->dev.of_node, + "qcom,rmnet-ll-enable"); + IPADBG(": Enable rmnet ll = %s\n", + ipa_drv_res->rmnet_ll_enable + ? "True" : "False"); + } + ipa_drv_res->lan_coal_enable = + of_property_read_bool(pdev->dev.of_node, + "qcom,lan-coal-enable"); + IPADBG(": Enable lan coal = %s\n", + ipa_drv_res->lan_coal_enable + ? "True" : "False"); + + + + result = of_property_read_string(pdev->dev.of_node, + "qcom,use-gsi-ipa-fw", &ipa_drv_res->gsi_fw_file_name); + if (!result) + IPADBG("GSI IPA FW name %s\n", ipa_drv_res->gsi_fw_file_name); + else + IPADBG("GSI IPA FW file not defined. Using default one\n"); + result = of_property_read_string(pdev->dev.of_node, + "qcom,use-uc-ipa-fw", &ipa_drv_res->uc_fw_file_name); + if (!result) + IPADBG("uC IPA FW name = %s\n", ipa_drv_res->uc_fw_file_name); + else + IPADBG("uC IPA FW file not defined. Using default one\n"); + + ipa_drv_res->ipa_mhi_proxy = + of_property_read_bool(pdev->dev.of_node, + "qcom,ipa-mhi-proxy"); + IPADBG(": Use mhi proxy = %s\n", + ipa_drv_res->ipa_mhi_proxy + ? "True" : "False"); + + ipa_drv_res->ipa_wdi_opt_dpath = + of_property_read_bool(pdev->dev.of_node, + "qcom,ipa-wdi-opt-dpath"); + IPADBG(": Use optimized datapath = %s\n", + ipa_drv_res->ipa_wdi_opt_dpath + ? "True" : "False"); + + /* Get IPA wrapper address */ + result = of_property_read_u32(pdev->dev.of_node, "qcom,ipa-cfg-offset", + &ipa_drv_res->ipa_cfg_offset); + if (!result) { + IPADBG(": Read offset of IPA_CFG from IPA_WRAPPER_BASE = 0x%x\n", + ipa_drv_res->ipa_cfg_offset); + } else { + ipa_drv_res->ipa_cfg_offset = 0; + IPADBG("IPA_CFG_OFFSET not defined. Using default one\n"); + } + + resource = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "ipa-base"); + if (!resource) { + IPAERR(":get resource failed for ipa-base!\n"); + return -ENODEV; + } + ipa_drv_res->ipa_mem_base = resource->start; + ipa_drv_res->ipa_mem_size = resource_size(resource); + IPADBG(": ipa-base = 0x%x, size = 0x%x\n", + ipa_drv_res->ipa_mem_base, + ipa_drv_res->ipa_mem_size); + + smmu_info.ipa_base = ipa_drv_res->ipa_mem_base; + smmu_info.ipa_size = ipa_drv_res->ipa_mem_size; + + /* Get IPA GSI address */ + resource = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "gsi-base"); + if (!resource) { + IPAERR(":get resource failed for gsi-base\n"); + return -ENODEV; + } + ipa_drv_res->transport_mem_base = resource->start; + ipa_drv_res->transport_mem_size = resource_size(resource); + IPADBG(": gsi-base = 0x%x, size = 0x%x\n", + ipa_drv_res->transport_mem_base, + ipa_drv_res->transport_mem_size); + + /* Get IPA GSI IRQ number */ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 18, 0)) + irq = 0; + resource = platform_get_resource_byname(pdev, IORESOURCE_IRQ, + "gsi-irq"); + if (!resource) { + IPAERR(":get resource failed for gsi-irq\n"); + return -ENODEV; + } + ipa_drv_res->transport_irq = resource->start; +#else + irq = platform_get_irq_byname(pdev, "gsi-irq"); + if (irq < 0) { + IPAERR(":get resource failed for gsi-irq\n"); + return -ENODEV; + } + ipa_drv_res->transport_irq = irq; +#endif + IPADBG(": gsi-irq = %d\n", ipa_drv_res->transport_irq); + + /* Get IPA pipe mem start ofst */ + resource = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "ipa-pipe-mem"); + if (!resource) { + IPADBG(":not using pipe memory - resource nonexisting\n"); + } else { + ipa_drv_res->ipa_pipe_mem_start_ofst = resource->start; + ipa_drv_res->ipa_pipe_mem_size = resource_size(resource); + IPADBG(":using pipe memory - at 0x%x of size 0x%x\n", + ipa_drv_res->ipa_pipe_mem_start_ofst, + ipa_drv_res->ipa_pipe_mem_size); + } + + /* Get IPA IRQ number */ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 18, 0)) + resource = platform_get_resource_byname(pdev, IORESOURCE_IRQ, + "ipa-irq"); + if (!resource) { + IPAERR(":get resource failed for ipa-irq\n"); + return -ENODEV; + } + ipa_drv_res->ipa_irq = resource->start; +#else + irq = platform_get_irq_byname(pdev, "ipa-irq"); + if (irq < 0) { + IPAERR(":get resource failed for ipa-irq\n"); + return -ENODEV; + } + ipa_drv_res->ipa_irq = irq; +#endif + IPADBG(":ipa-irq = %d\n", ipa_drv_res->ipa_irq); + + result = of_property_read_u32(pdev->dev.of_node, "qcom,ee", + &ipa_drv_res->ee); + if (result) + ipa_drv_res->ee = 0; + IPADBG(":ee = %u\n", ipa_drv_res->ee); + + ipa_drv_res->apply_rg10_wa = + of_property_read_bool(pdev->dev.of_node, + "qcom,use-rg10-limitation-mitigation"); + IPADBG(": Use Register Group 10 limitation mitigation = %s\n", + ipa_drv_res->apply_rg10_wa + ? "True" : "False"); + + ipa_drv_res->gsi_ch20_wa = + of_property_read_bool(pdev->dev.of_node, + "qcom,do-not-use-ch-gsi-20"); + IPADBG(": GSI CH 20 WA is = %s\n", + ipa_drv_res->gsi_ch20_wa + ? "Needed" : "Not needed"); + + ipa_drv_res->use_pm_wrapper = false; + ipa_drv_res->use_pm_wrapper = + of_property_read_bool(pdev->dev.of_node, + "qcom,use-wrapper-pm-support"); + IPADBG(": Use PM wrapper Support = %s\n", + ipa_drv_res->use_pm_wrapper + ? "Needed" : "Not needed"); + + ipa_drv_res->use_tput_est_ep = + of_property_read_bool(pdev->dev.of_node, + "qcom,use-tput-estmation-pipe"); + IPADBG(": Use Tput estimation ep = %s\n", + ipa_drv_res->use_tput_est_ep + ? "Needed" : "Not needed"); + + elem_num = of_property_count_elems_of_size(pdev->dev.of_node, + "qcom,mhi-event-ring-id-limits", sizeof(u32)); + + if (elem_num == 2) { + if (of_property_read_u32_array(pdev->dev.of_node, + "qcom,mhi-event-ring-id-limits", mhi_evid_limits, 2)) { + IPAERR("failed to read mhi event ring id limits\n"); + return -EFAULT; + } + if (mhi_evid_limits[0] > mhi_evid_limits[1]) { + IPAERR("mhi event ring id low limit > high limit\n"); + return -EFAULT; + } + ipa_drv_res->mhi_evid_limits[0] = mhi_evid_limits[0]; + ipa_drv_res->mhi_evid_limits[1] = mhi_evid_limits[1]; + IPADBG(": mhi-event-ring-id-limits start=%u end=%u\n", + mhi_evid_limits[0], mhi_evid_limits[1]); + } else { + if (elem_num > 0) { + IPAERR("Invalid mhi event ring id limits number %d\n", + elem_num); + return -EINVAL; + } + IPADBG("use default mhi evt ring id limits start=%u end=%u\n", + ipa_drv_res->mhi_evid_limits[0], + ipa_drv_res->mhi_evid_limits[1]); + } + + elem_num = of_property_count_elems_of_size(pdev->dev.of_node, + "qcom,ipa-tz-unlock-reg", sizeof(u32)); + + if (elem_num > 0 && elem_num % 2 == 0) { + ipa_drv_res->ipa_tz_unlock_reg_num = elem_num / 2; + + ipa_tz_unlock_reg = kcalloc(elem_num, sizeof(u32), GFP_KERNEL); + if (ipa_tz_unlock_reg == NULL) + return -ENOMEM; + + ipa_drv_res->ipa_tz_unlock_reg = kcalloc( + ipa_drv_res->ipa_tz_unlock_reg_num, + sizeof(*ipa_drv_res->ipa_tz_unlock_reg), + GFP_KERNEL); + if (ipa_drv_res->ipa_tz_unlock_reg == NULL) { + kfree(ipa_tz_unlock_reg); + return -ENOMEM; + } + + if (of_property_read_u32_array(pdev->dev.of_node, + "qcom,ipa-tz-unlock-reg", ipa_tz_unlock_reg, + elem_num)) { + IPAERR("failed to read register addresses\n"); + kfree(ipa_tz_unlock_reg); + kfree(ipa_drv_res->ipa_tz_unlock_reg); + ipa_drv_res->ipa_tz_unlock_reg = NULL; + return -EFAULT; + } + + pos = 0; + for (i = 0; i < ipa_drv_res->ipa_tz_unlock_reg_num; i++) { + ipa_drv_res->ipa_tz_unlock_reg[i].reg_addr = + ipa_tz_unlock_reg[pos++]; + ipa_drv_res->ipa_tz_unlock_reg[i].size = + ipa_tz_unlock_reg[pos++]; + IPADBG("tz unlock reg %d: addr 0x%pa size %llu\n", i, + &ipa_drv_res->ipa_tz_unlock_reg[i].reg_addr, + ipa_drv_res->ipa_tz_unlock_reg[i].size); + } + kfree(ipa_tz_unlock_reg); + } + + /* get HOLB_TO numbers for wdi3 tx pipe */ + result = of_property_read_u32(pdev->dev.of_node, + "qcom,ipa-wdi3-holb-2g", + &ipa_drv_res->ipa_wdi3_2g_holb_timeout); + if (result) + IPADBG("Not able to get the holb for 2g pipe = %u\n", + ipa_drv_res->ipa_wdi3_2g_holb_timeout); + else + IPADBG(": found ipa_drv_res->ipa_wdi3_2g_holb_timeout = %u", + ipa_drv_res->ipa_wdi3_2g_holb_timeout); + + /* get HOLB_TO numbers for wdi3 tx1 pipe */ + result = of_property_read_u32(pdev->dev.of_node, + "qcom,ipa-wdi3-holb-5g", + &ipa_drv_res->ipa_wdi3_5g_holb_timeout); + if (result) + IPADBG("Not able to get the holb for 5g pipe = %u\n", + ipa_drv_res->ipa_wdi3_5g_holb_timeout); + else + IPADBG(": found ipa_drv_res->ipa_wdi3_2g_holb_timeout = %u", + ipa_drv_res->ipa_wdi3_2g_holb_timeout); + + /* get IPA PM related information */ + result = get_ipa_dts_pm_info(pdev, ipa_drv_res); + if (result) { + IPAERR("failed to get pm info from dts %d\n", result); + return result; + } + + ipa_drv_res->wdi_over_pcie = + of_property_read_bool(pdev->dev.of_node, + "qcom,wlan-ce-db-over-pcie"); + IPADBG("Is wdi_over_pcie ? (%s)\n", + ipa_drv_res->wdi_over_pcie ? "Yes":"No"); + + /* + * If we're on emulator, get its interrupt controller's mem + * start and size + */ + if (ipa_drv_res->ipa3_hw_mode == IPA_HW_MODE_EMULATION) { + resource = platform_get_resource_byname( + pdev, IORESOURCE_MEM, "intctrl-base"); + if (!resource) { + IPAERR(":Can't find intctrl-base resource\n"); + return -ENODEV; + } + ipa_drv_res->emulator_intcntrlr_mem_base = + resource->start; + ipa_drv_res->emulator_intcntrlr_mem_size = + resource_size(resource); + IPADBG(":using intctrl-base at 0x%x of size 0x%x\n", + ipa_drv_res->emulator_intcntrlr_mem_base, + ipa_drv_res->emulator_intcntrlr_mem_size); + } + + ipa_drv_res->entire_ipa_block_size = 0x100000; + result = of_property_read_u32(pdev->dev.of_node, + "qcom,entire-ipa-block-size", + &ipa_drv_res->entire_ipa_block_size); + IPADBG(": entire_ipa_block_size = %d\n", + ipa_drv_res->entire_ipa_block_size); + + /* + * We'll read register-collection-on-crash here, but log it + * later below because its value may change based on other + * subsequent dtsi reads...... + */ + ipa_drv_res->do_register_collection_on_crash = + of_property_read_bool(pdev->dev.of_node, + "qcom,register-collection-on-crash"); + /* + * We'll read testbus-collection-on-crash here... + */ + ipa_drv_res->do_testbus_collection_on_crash = + of_property_read_bool(pdev->dev.of_node, + "qcom,testbus-collection-on-crash"); + IPADBG(": doing testbus collection on crash = %u\n", + ipa_drv_res->do_testbus_collection_on_crash); + + /* + * We'll read non-tn-collection-on-crash here... + */ + ipa_drv_res->do_non_tn_collection_on_crash = + of_property_read_bool(pdev->dev.of_node, + "qcom,non-tn-collection-on-crash"); + IPADBG(": doing non-tn collection on crash = %u\n", + ipa_drv_res->do_non_tn_collection_on_crash); + + /* + * We'll read ram-collection-on-crash here... + */ + ipa_drv_res->do_ram_collection_on_crash = + of_property_read_bool( + pdev->dev.of_node, + "qcom,ram-collection-on-crash"); + IPADBG(": doing ram collection on crash = %u\n", + ipa_drv_res->do_ram_collection_on_crash); + + if (ipa_drv_res->do_testbus_collection_on_crash || + ipa_drv_res->do_non_tn_collection_on_crash || + ipa_drv_res->do_ram_collection_on_crash) + ipa_drv_res->do_register_collection_on_crash = true; + + IPADBG(": doing register collection on crash = %u\n", + ipa_drv_res->do_register_collection_on_crash); + + result = of_property_read_u32( + pdev->dev.of_node, + "qcom,secure-debug-check-action", + &ipa_drv_res->secure_debug_check_action); + if (result || + (ipa_drv_res->secure_debug_check_action != 0 && + ipa_drv_res->secure_debug_check_action != 1 && + ipa_drv_res->secure_debug_check_action != 2)) + ipa_drv_res->secure_debug_check_action = USE_SCM; + + IPADBG(": secure-debug-check-action = %d\n", + ipa_drv_res->secure_debug_check_action); + + + result = of_property_read_u32( + pdev->dev.of_node, + "qcom,ipa-wan-aggr-pkt-cnt", + &ipa_wan_aggr_pkt_cnt); + if (result) { + ipa_wan_aggr_pkt_cnt = IPA_WAN_AGGR_PKT_CNT; + IPADBG("ipa wan aggr pkt cnt = %u\n", ipa_wan_aggr_pkt_cnt); + } else + IPADBG("ipa wan aggr pkt cnt = %u\n", ipa_wan_aggr_pkt_cnt); + + ipa_drv_res->ipa_wan_aggr_pkt_cnt = ipa_wan_aggr_pkt_cnt; + + get_dts_tx_wrapper_cache_size(pdev, ipa_drv_res); + + get_dts_ipa_gen_rx_cmn_page_pool_sz_factor(pdev, ipa_drv_res); + + get_dts_ipa_gen_rx_cmn_temp_pool_sz_factor(pdev, ipa_drv_res); + + get_dts_ipa_gen_rx_ll_page_pool_sz_factor(pdev, ipa_drv_res); + + ipa_dts_get_ulso_data(pdev, ipa_drv_res); + + result = of_property_read_u32(pdev->dev.of_node, + "qcom,max_num_smmu_cb", + &ipa_drv_res->max_num_smmu_cb); + if (result) + IPADBG(": using default max number of cb = %d\n", + ipa_drv_res->max_num_smmu_cb); + else + IPADBG(": found ipa_drv_res->max_num_smmu_cb = %d\n", + ipa_drv_res->max_num_smmu_cb); + + result = of_property_read_u8(pdev->dev.of_node, + "qcom,coal-ipv4-id-ignore", + &ipa_drv_res->coal_ipv4_id_ignore); + if (result || ipa_drv_res->coal_ipv4_id_ignore > 1) { + IPADBG(":Resource not present for coal-ipv4-id-ignore, use def\n"); + ipa_drv_res->coal_ipv4_id_ignore = true; + } + IPADBG(": coal-ipv4-id-ignore = %s\n", + ipa_drv_res->coal_ipv4_id_ignore + ? "True" : "False"); + + return 0; +} + +static int ipa_smmu_perph_cb_probe(struct device *dev, + enum ipa_smmu_cb_type cb_type) +{ + struct ipa_smmu_cb_ctx *cb = ipa3_get_smmu_ctx(cb_type); + int fast = 0; + int bypass = 0; + u32 add_map_size; + const u32 *add_map; + int i; + u32 iova; + u32 pa; + u32 size; + unsigned long iova_p; + phys_addr_t pa_p; + u32 size_p; + u32 iova_ap_mapping[2]; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 13, 0)) + int mapping_config; +#endif + + IPADBG("CB %d PROBE dev=%pK\n", cb_type, dev); + + if (!smmu_info.present[cb_type]) { + IPAERR("cb %d is disabled\n", cb_type); + return 0; + } + + IPADBG("CB %d PROBE dev=%pK retrieving IOMMU mapping\n", cb_type, dev); + + cb->iommu_domain = iommu_get_domain_for_dev(dev); + if (IS_ERR_OR_NULL(cb->iommu_domain)) { + IPAERR("could not get iommu domain\n"); + return -EINVAL; + } + + IPADBG("CB %d PROBE mapping retrieved\n", cb_type); + cb->is_cache_coherent = of_property_read_bool(dev->of_node, + "dma-coherent"); + cb->dev = dev; + cb->valid = true; + + cb->va_start = cb->va_end = cb->va_size = 0; + if (of_property_read_u32_array( + dev->of_node, "qcom,iommu-dma-addr-pool", + iova_ap_mapping, 2) == 0) { + cb->va_start = iova_ap_mapping[0]; + cb->va_size = iova_ap_mapping[1]; + cb->va_end = cb->va_start + cb->va_size; + } + + IPADBG("CB %d PROBE dev=%pK va_start=0x%x va_size=0x%x\n", + cb_type, dev, cb->va_start, cb->va_size); + + /* + * Prior to these calls to iommu_domain_get_attr(), these + * attributes were set in this function relative to dtsi values + * defined for this driver. In other words, if corresponding ipa + * driver owned values were found in the dtsi, they were read and + * set here. + * + * In this new world, the developer will use iommu owned dtsi + * settings to set them there. This new logic below, simply + * checks to see if they've been set in dtsi. If so, the logic + * further below acts accordingly... + */ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 13, 0)) + + mapping_config = qcom_iommu_get_mappings_configuration(cb->iommu_domain); + + if (mapping_config < 0) { + IPAERR("No Mapping configuration found for CB %d\n", cb_type); + } else { + bypass = (mapping_config & QCOM_IOMMU_MAPPING_CONF_S1_BYPASS) ? 1 : 0; + fast = (mapping_config & QCOM_IOMMU_MAPPING_CONF_FAST) ? 1 : 0; + } +#else + iommu_domain_get_attr(cb->iommu_domain, DOMAIN_ATTR_S1_BYPASS, &bypass); + iommu_domain_get_attr(cb->iommu_domain, DOMAIN_ATTR_FAST, &fast); +#endif + IPADBG( + "CB %d PROBE dev=%pK DOMAIN ATTRS bypass=%d fast=%d\n", + cb_type, dev, bypass, fast); + + ipa3_ctx->s1_bypass_arr[cb_type] = (bypass != 0); + + if (of_property_read_bool(dev->of_node, "qcom,shared-cb")) { + IPADBG("CB %d using shared CB\n", cb_type); + cb->shared = true; + } + + /* MAP ipa-uc ram */ + add_map = of_get_property(dev->of_node, + "qcom,additional-mapping", &add_map_size); + if (add_map) { + /* mapping size is an array of 3-tuple of u32 */ + if (add_map_size % (3 * sizeof(u32))) { + IPAERR("wrong additional mapping format\n"); + cb->valid = false; + return -EFAULT; + } + + /* iterate of each entry of the additional mapping array */ + for (i = 0; i < add_map_size / sizeof(u32); i += 3) { + iova = be32_to_cpu(add_map[i]); + pa = be32_to_cpu(add_map[i + 1]); + size = be32_to_cpu(add_map[i + 2]); + + IPA_SMMU_ROUND_TO_PAGE(iova, pa, size, + iova_p, pa_p, size_p); + IPADBG_LOW("mapping 0x%lx to 0x%pa size %d\n", + iova_p, &pa_p, size_p); + ipa3_iommu_map(cb->iommu_domain, + iova_p, pa_p, size_p, + IOMMU_READ | IOMMU_WRITE | IOMMU_MMIO); + } + } + + cb->done = true; + return 0; +} + +static int ipa_smmu_uc_cb_probe(struct device *dev) +{ + struct ipa_smmu_cb_ctx *cb = ipa3_get_smmu_ctx(IPA_SMMU_CB_UC); + int bypass = 0; + int fast = 0; + u32 iova_ap_mapping[2]; + u32 iova = 0; + u32 pa = 0; + u32 size = 0; + unsigned long iova_p; + phys_addr_t pa_p; + u32 size_p; + u32 add_map_size; + const u32 *add_map; + int i = 0; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 13, 0)) + int mapping_config; +#endif + + IPADBG("UC CB PROBE dev=%pK\n", dev); + + if (!smmu_info.present[IPA_SMMU_CB_UC]) { + IPAERR("UC SMMU is disabled\n"); + return 0; + } + + if (smmu_info.use_64_bit_dma_mask) { + if (dma_set_mask(dev, DMA_BIT_MASK(64)) || + dma_set_coherent_mask(dev, DMA_BIT_MASK(64))) { + IPAERR("DMA set 64bit mask failed\n"); + return -EOPNOTSUPP; + } + } else { + if (dma_set_mask(dev, DMA_BIT_MASK(32)) || + dma_set_coherent_mask(dev, DMA_BIT_MASK(32))) { + IPAERR("DMA set 32bit mask failed\n"); + return -EOPNOTSUPP; + } + } + + IPADBG("UC CB PROBE dev=%pK retrieving IOMMU mapping\n", dev); + + cb->iommu_domain = iommu_get_domain_for_dev(dev); + if (IS_ERR_OR_NULL(cb->iommu_domain)) { + IPAERR("could not get iommu domain\n"); + return -EINVAL; + } + + IPADBG("UC CB PROBE mapping retrieved\n"); + + cb->is_cache_coherent = of_property_read_bool(dev->of_node, + "dma-coherent"); + cb->dev = dev; + cb->valid = true; + + cb->va_start = cb->va_end = cb->va_size = 0; + if (of_property_read_u32_array( + dev->of_node, "qcom,iommu-dma-addr-pool", + iova_ap_mapping, 2) == 0) { + cb->va_start = iova_ap_mapping[0]; + cb->va_size = iova_ap_mapping[1]; + cb->va_end = cb->va_start + cb->va_size; + } + + IPADBG("UC CB PROBE dev=%pK va_start=0x%x va_size=0x%x\n", + dev, cb->va_start, cb->va_size); + + /* + * Prior to these calls to iommu_domain_get_attr(), these + * attributes were set in this function relative to dtsi values + * defined for this driver. In other words, if corresponding ipa + * driver owned values were found in the dtsi, they were read and + * set here. + * + * In this new world, the developer will use iommu owned dtsi + * settings to set them there. This new logic below, simply + * checks to see if they've been set in dtsi. If so, the logic + * further below acts accordingly... + */ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 13, 0)) + + mapping_config = qcom_iommu_get_mappings_configuration(cb->iommu_domain); + + if (mapping_config < 0) { + IPAERR("No Mapping configuration found for UC CB\n"); + } else { + bypass = (mapping_config & QCOM_IOMMU_MAPPING_CONF_S1_BYPASS) ? 1 : 0; + fast = (mapping_config & QCOM_IOMMU_MAPPING_CONF_FAST) ? 1 : 0; + } +#else + iommu_domain_get_attr(cb->iommu_domain, DOMAIN_ATTR_S1_BYPASS, &bypass); + iommu_domain_get_attr(cb->iommu_domain, DOMAIN_ATTR_FAST, &fast); +#endif + IPADBG("UC CB PROBE dev=%pK DOMAIN ATTRS bypass=%d fast=%d\n", + dev, bypass, fast); + + ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_UC] = (bypass != 0); + + ipa3_ctx->uc_pdev = dev; + + add_map = of_get_property(dev->of_node, + "qcom,ipcc-mapping", &add_map_size); + if (add_map) { + /* mapping size is an array of 3-tuple of u32 */ + if (add_map_size % (3 * sizeof(u32))) { + IPAERR("wrong ipcc mapping format\n"); + cb->valid = false; + return -EFAULT; + } + + /* iterate of each entry of the ipcc mapping array */ + for (i = 0; i < add_map_size / sizeof(u32); i += 3) { + iova = be32_to_cpu(add_map[i]); + pa = be32_to_cpu(add_map[i + 1]); + size = be32_to_cpu(add_map[i + 2]); + + IPA_SMMU_ROUND_TO_PAGE(iova, pa, size, + iova_p, pa_p, size_p); + IPADBG_LOW("mapping 0x%lx to 0x%pa size %d\n", + iova_p, &pa_p, size_p); + ipa3_iommu_map(cb->iommu_domain, + iova_p, pa_p, size_p, + IOMMU_READ | IOMMU_WRITE | IOMMU_MMIO); + } + } + + cb->done = true; + return 0; +} + +static void ipa3_ap_iommu_unmap(struct ipa_smmu_cb_ctx *cb, const u32 *add_map, u32 add_map_size) { + + int i, res; + + /* iterate of each entry of the additional mapping array */ + for (i = 0; i < add_map_size / sizeof(u32); i += 3) { + u32 iova = be32_to_cpu(add_map[i]); + u32 pa = be32_to_cpu(add_map[i + 1]); + u32 size = be32_to_cpu(add_map[i + 2]); + unsigned long iova_p; + phys_addr_t pa_p; + u32 size_p; + + IPA_SMMU_ROUND_TO_PAGE(iova, pa, size, + iova_p, pa_p, size_p); + IPADBG_LOW("unmapping 0x%lx to 0x%pa size %d\n", + iova_p, &pa_p, size_p); + + res = iommu_unmap(cb->iommu_domain,iova_p, size_p); + if(res != size_p) { + pr_err("iommu unmap failed for AP cb\n"); + ipa_assert(); + } + } +} +static int ipa_smmu_ap_cb_probe(struct device *dev) +{ + struct ipa_smmu_cb_ctx *cb = ipa3_get_smmu_ctx(IPA_SMMU_CB_AP); + int fast = 0; + int bypass = 0; + u32 add_map_size; + const u32 *add_map; + void *smem_addr; + size_t smem_size; + u32 ipa_smem_size = 0; + int ret; + int i; + u32 iova; + u32 pa; + u32 size; + unsigned long iova_p; + phys_addr_t pa_p; + u32 size_p; + u32 iova_ap_mapping[2]; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 13, 0)) + int mapping_config; +#endif + u32 geometry_ap_mapping[2]; + + IPADBG("AP CB PROBE dev=%pK\n", dev); + + if (!smmu_info.present[IPA_SMMU_CB_AP]) { + IPAERR("AP SMMU is disabled"); + return 0; + } + + if (smmu_info.use_64_bit_dma_mask) { + if (dma_set_mask(dev, DMA_BIT_MASK(64)) || + dma_set_coherent_mask(dev, DMA_BIT_MASK(64))) { + IPAERR("DMA set 64bit mask failed\n"); + return -EOPNOTSUPP; + } + } else { + if (dma_set_mask(dev, DMA_BIT_MASK(32)) || + dma_set_coherent_mask(dev, DMA_BIT_MASK(32))) { + IPAERR("DMA set 32bit mask failed\n"); + return -EOPNOTSUPP; + } + } + + IPADBG("AP CB PROBE dev=%pK retrieving IOMMU mapping\n", dev); + + cb->iommu_domain = iommu_get_domain_for_dev(dev); + if (IS_ERR_OR_NULL(cb->iommu_domain)) { + IPAERR("could not get iommu domain\n"); + return -EINVAL; + } + + IPADBG("AP CB PROBE mapping retrieved\n"); + + cb->is_cache_coherent = of_property_read_bool(dev->of_node, + "dma-coherent"); + cb->dev = dev; + cb->valid = true; + + cb->va_start = cb->va_end = cb->va_size = 0; + if (of_property_read_u32_array( + dev->of_node, "qcom,iommu-dma-addr-pool", + iova_ap_mapping, 2) == 0) { + cb->va_start = iova_ap_mapping[0]; + cb->va_size = iova_ap_mapping[1]; + cb->va_end = cb->va_start + cb->va_size; + } + + IPADBG("AP CB PROBE dev=%pK va_start=0x%x va_size=0x%x\n", + dev, cb->va_start, cb->va_size); + if (of_property_read_u32_array( + dev->of_node, "qcom,iommu-geometry", + geometry_ap_mapping, 2) == 0) { + cb->geometry_start = geometry_ap_mapping[0]; + cb->geometry_end = geometry_ap_mapping[1]; + } else { + IPADBG("AP CB PROBE Geometry not defined using max!\n"); + cb->geometry_start = 0; + cb->geometry_end = 0xF0000000; + } + + IPADBG("AP CB PROBE dev=%pK geometry_start=0x%x geometry_end=0x%x\n", + dev, cb->geometry_start, cb->geometry_end); + + /* + * Prior to these calls to iommu_domain_get_attr(), these + * attributes were set in this function relative to dtsi values + * defined for this driver. In other words, if corresponding ipa + * driver owned values were found in the dtsi, they were read and + * set here. + * + * In this new world, the developer will use iommu owned dtsi + * settings to set them there. This new logic below, simply + * checks to see if they've been set in dtsi. If so, the logic + * further below acts accordingly... + */ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 13, 0)) + + mapping_config = qcom_iommu_get_mappings_configuration(cb->iommu_domain); + + if (mapping_config < 0) { + IPAERR("No Mapping configuration found for AP CB\n"); + } else { + bypass = (mapping_config & QCOM_IOMMU_MAPPING_CONF_S1_BYPASS) ? 1 : 0; + fast = (mapping_config & QCOM_IOMMU_MAPPING_CONF_FAST) ? 1 : 0; + } +#else + iommu_domain_get_attr(cb->iommu_domain, DOMAIN_ATTR_S1_BYPASS, &bypass); + iommu_domain_get_attr(cb->iommu_domain, DOMAIN_ATTR_FAST, &fast); +#endif + IPADBG("AP CB PROBE dev=%pK DOMAIN ATTRS bypass=%d fast=%d\n", + dev, bypass, fast); + + ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_AP] = (bypass != 0); + + add_map = of_get_property(dev->of_node, + "qcom,additional-mapping", &add_map_size); + if (add_map) { + /* mapping size is an array of 3-tuple of u32 */ + if (add_map_size % (3 * sizeof(u32))) { + IPAERR("wrong additional mapping format\n"); + cb->valid = false; + return -EFAULT; + } + + /* iterate of each entry of the additional mapping array */ + for (i = 0; i < add_map_size / sizeof(u32); i += 3) { + iova = be32_to_cpu(add_map[i]); + pa = be32_to_cpu(add_map[i + 1]); + size = be32_to_cpu(add_map[i + 2]); + + IPA_SMMU_ROUND_TO_PAGE(iova, pa, size, + iova_p, pa_p, size_p); + IPADBG_LOW("mapping 0x%lx to 0x%pa size %d\n", + iova_p, &pa_p, size_p); + ipa3_iommu_map(cb->iommu_domain, + iova_p, pa_p, size_p, + IOMMU_READ | IOMMU_WRITE | IOMMU_MMIO); + } + } + + ret = of_property_read_u32(dev->of_node, "qcom,ipa-q6-smem-size", + &ipa_smem_size); + if (ret) { + IPADBG("ipa q6 smem size (default) = %u\n", IPA_SMEM_SIZE); + ipa_smem_size = IPA_SMEM_SIZE; + } else { + IPADBG("ipa q6 smem size = %u\n", ipa_smem_size); + } + + ipa3_ctx->ipa_smem_size = ipa_smem_size; + if (ipa3_ctx->platform_type != IPA_PLAT_TYPE_APQ) { + /* map SMEM memory for IPA table accesses */ + ret = qcom_smem_alloc(SMEM_MODEM, + SMEM_IPA_FILTER_TABLE, + ipa_smem_size); + + if (ret < 0 && ret != -EEXIST) { + IPAERR("unable to allocate smem MODEM entry\n"); + cb->valid = false; + if(add_map) + ipa3_ap_iommu_unmap(cb, add_map, add_map_size); + return -EFAULT; + } + smem_addr = qcom_smem_get(SMEM_MODEM, + SMEM_IPA_FILTER_TABLE, + &smem_size); + if (IS_ERR(smem_addr)) { + IPAERR("unable to acquire smem MODEM entry\n"); + cb->valid = false; + if(add_map) + ipa3_ap_iommu_unmap(cb, add_map, add_map_size); + return -EFAULT; + } + if (smem_size != ipa_smem_size) + IPAERR("unexpected read q6 smem size %zu %u\n", + smem_size, ipa_smem_size); + + iova = qcom_smem_virt_to_phys(smem_addr); + pa = iova; + + IPA_SMMU_ROUND_TO_PAGE(iova, pa, ipa_smem_size, + iova_p, pa_p, size_p); + IPADBG("mapping 0x%lx to 0x%pa size %d\n", + iova_p, &pa_p, size_p); + ipa3_iommu_map(cb->iommu_domain, + iova_p, pa_p, size_p, + IOMMU_READ | IOMMU_WRITE); + + ipa3_ctx->per_stats_smem_pa = iova; + ipa3_ctx->per_stats_smem_va = smem_addr; + + /** + * Force type casting to perpheral stats structure. + * First 2kB of the FILTER_TABLE SMEM is allocated for + * Peripheral stats design. If there is a need to + * use rest of FILTER_TABLE_SMEM it should be used from + * smem_addr + 2KB offset + */ + ret = ipa3_peripheral_stats_init((union ipa_peripheral_stats *) smem_addr); + if(ret) IPAERR("IPA Peripheral stats init failure = %d ", ret); + } + + smmu_info.present[IPA_SMMU_CB_AP] = true; + + cb->done = true; + ipa3_ctx->pdev = dev; + cb->next_addr = cb->va_end; + + return 0; +} + + +static int ipa_smmu_rtp_cb_probe(struct device *dev) +{ + struct ipa_smmu_cb_ctx *cb = ipa3_get_smmu_ctx(IPA_SMMU_CB_RTP); + int fast = 0; + int bypass = 0; + u32 add_map_size; + const u32 *add_map; + int i; + u32 iova; + u32 pa; + u32 size; + unsigned long iova_p; + phys_addr_t pa_p; + u32 size_p; + u32 iova_ap_mapping[2]; +#if (KERNEL_VERSION(5, 13, 0) <= LINUX_VERSION_CODE) + int mapping_config; +#endif + u32 geometry_ap_mapping[2]; + + IPADBG("RTP CB PROBE dev=%pK\n", dev); + + if (!smmu_info.present[IPA_SMMU_CB_RTP]) { + IPAERR("RTP SMMU is disabled\n"); + return 0; + } + + if (smmu_info.use_64_bit_dma_mask) { + if (dma_set_mask(dev, DMA_BIT_MASK(64)) || + dma_set_coherent_mask(dev, DMA_BIT_MASK(64))) { + IPAERR("DMA set 64bit mask failed\n"); + return -EOPNOTSUPP; + } + } else { + if (dma_set_mask(dev, DMA_BIT_MASK(32)) || + dma_set_coherent_mask(dev, DMA_BIT_MASK(32))) { + IPAERR("DMA set 32bit mask failed\n"); + return -EOPNOTSUPP; + } + } + + IPADBG("RTP CB PROBE dev=%pK retrieving IOMMU mapping\n", dev); + + cb->iommu_domain = iommu_get_domain_for_dev(dev); + if (IS_ERR_OR_NULL(cb->iommu_domain)) { + IPAERR("could not get iommu domain\n"); + return -EINVAL; + } + + IPADBG("RTP CB PROBE mapping retrieved\n"); + + cb->is_cache_coherent = of_property_read_bool(dev->of_node, + "dma-coherent"); + cb->dev = dev; + cb->valid = true; + + cb->va_start = cb->va_end = cb->va_size = 0; + if (of_property_read_u32_array( + dev->of_node, "qcom,iommu-dma-addr-pool", + iova_ap_mapping, 2) == 0) { + cb->va_start = iova_ap_mapping[0]; + cb->va_size = iova_ap_mapping[1]; + cb->va_end = cb->va_start + cb->va_size; + } + + IPADBG("RTP CB PROBE dev=%pK va_start=0x%x va_size=0x%x\n", + dev, cb->va_start, cb->va_size); + if (of_property_read_u32_array( + dev->of_node, "qcom,iommu-geometry", + geometry_ap_mapping, 2) == 0) { + cb->geometry_start = geometry_ap_mapping[0]; + cb->geometry_end = geometry_ap_mapping[1]; + } else { + IPADBG("RTP CB PROBE Geometry not defined using max!\n"); + cb->geometry_start = 0; + cb->geometry_end = 0xF0000000; + } + + IPADBG("RTP CB PROBE dev=%pK geometry_start=0x%x geometry_end=0x%x\n", + dev, cb->geometry_start, cb->geometry_end); + + /* + * Prior to these calls to iommu_domain_get_attr(), these + * attributes were set in this function relative to dtsi values + * defined for this driver. In other words, if corresponding ipa + * driver owned values were found in the dtsi, they were read and + * set here. + * + * In this new world, the developer will use iommu owned dtsi + * settings to set them there. This new logic below, simply + * checks to see if they've been set in dtsi. If so, the logic + * further below acts accordingly... + */ +#if (KERNEL_VERSION(5, 13, 0) <= LINUX_VERSION_CODE) + + mapping_config = qcom_iommu_get_mappings_configuration(cb->iommu_domain); + + if (mapping_config < 0) { + IPAERR("No Mapping configuration found for RTP CB\n"); + } else { + bypass = (mapping_config & QCOM_IOMMU_MAPPING_CONF_S1_BYPASS) ? 1 : 0; + fast = (mapping_config & QCOM_IOMMU_MAPPING_CONF_FAST) ? 1 : 0; + } +#else + iommu_domain_get_attr(cb->iommu_domain, DOMAIN_ATTR_S1_BYPASS, &bypass); + iommu_domain_get_attr(cb->iommu_domain, DOMAIN_ATTR_FAST, &fast); +#endif + IPADBG("RTP CB PROBE dev=%pK DOMAIN ATTRS bypass=%d fast=%d\n", + dev, bypass, fast); + + ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_RTP] = (bypass != 0); + + add_map = of_get_property(dev->of_node, + "qcom,additional-mapping", &add_map_size); + if (add_map) { + /* mapping size is an array of 3-tuple of u32 */ + if (add_map_size % (3 * sizeof(u32))) { + IPAERR("wrong additional mapping format\n"); + cb->valid = false; + return -EFAULT; + } + + /* iterate of each entry of the additional mapping array */ + for (i = 0; i < add_map_size / sizeof(u32); i += 3) { + iova = be32_to_cpu(add_map[i]); + pa = be32_to_cpu(add_map[i + 1]); + size = be32_to_cpu(add_map[i + 2]); + + IPA_SMMU_ROUND_TO_PAGE(iova, pa, size, + iova_p, pa_p, size_p); + IPADBG_LOW("mapping 0x%lx to 0x%pa size %d\n", + iova_p, &pa_p, size_p); + ipa3_iommu_map(cb->iommu_domain, + iova_p, pa_p, size_p, + IOMMU_READ | IOMMU_WRITE | IOMMU_MMIO); + } + } + + smmu_info.present[IPA_SMMU_CB_RTP] = true; + + cb->done = true; + ipa3_ctx->rtp_pdev = dev; + cb->next_addr = cb->va_end; + + return 0; +} + +static int ipa_smmu_11ad_cb_probe(struct device *dev) +{ + int bypass = 0; + struct ipa_smmu_cb_ctx *cb = ipa3_get_smmu_ctx(IPA_SMMU_CB_11AD); + u32 iova_ap_mapping[2]; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 13, 0)) + int mapping_config; +#endif + + IPADBG("11AD CB probe: dev=%pK\n", dev); + + if (!smmu_info.present[IPA_SMMU_CB_11AD]) { + IPAERR("11AD SMMU is disabled"); + return 0; + } + + cb->iommu_domain = iommu_get_domain_for_dev(dev); + if (IS_ERR_OR_NULL(cb->iommu_domain)) { + IPAERR("could not get iommu domain\n"); + return -EINVAL; + } + cb->is_cache_coherent = of_property_read_bool(dev->of_node, + "dma-coherent"); + cb->dev = dev; + cb->valid = true; + + cb->va_start = cb->va_end = cb->va_size = 0; + if (of_property_read_u32_array( + dev->of_node, "qcom,iommu-dma-addr-pool", + iova_ap_mapping, 2) == 0) { + cb->va_start = iova_ap_mapping[0]; + cb->va_size = iova_ap_mapping[1]; + cb->va_end = cb->va_start + cb->va_size; + } + + IPADBG("11AD CB PROBE dev=%pK va_start=0x%x va_size=0x%x\n", + dev, cb->va_start, cb->va_size); +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 13, 0)) + + mapping_config = qcom_iommu_get_mappings_configuration(cb->iommu_domain); + + if (mapping_config < 0) { + IPAERR("No Mapping configuration found for 11AD CB\n"); + } else { + bypass = (mapping_config & QCOM_IOMMU_MAPPING_CONF_S1_BYPASS) ? 1 : 0; + } +#else + iommu_domain_get_attr(cb->iommu_domain, DOMAIN_ATTR_S1_BYPASS, &bypass); +#endif + IPADBG("11AD CB PROBE dev=%pK DOMAIN ATTRS bypass=%d\n", + dev, bypass); + + ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_11AD] = (bypass != 0); + + if (of_property_read_bool(dev->of_node, "qcom,shared-cb")) { + IPADBG("11AD using shared CB\n"); + cb->shared = true; + } + cb->done = true; + return 0; +} + +static int ipa_smmu_cb_probe(struct device *dev, enum ipa_smmu_cb_type cb_type) +{ + struct ipa_smmu_cb_ctx *cb = ipa3_get_smmu_ctx(cb_type); + + if((cb != NULL) && (cb->done == true)) { + IPADBG("SMMU CB type %d already initialized\n", cb_type); + return 0; + } + switch (cb_type) { + case IPA_SMMU_CB_AP: + ipa3_ctx->pdev = &ipa3_ctx->master_pdev->dev; + return ipa_smmu_ap_cb_probe(dev); + case IPA_SMMU_CB_WLAN: + case IPA_SMMU_CB_WLAN1: + case IPA_SMMU_CB_ETH: + case IPA_SMMU_CB_ETH1: + return ipa_smmu_perph_cb_probe(dev, cb_type); + case IPA_SMMU_CB_UC: + ipa3_ctx->uc_pdev = &ipa3_ctx->master_pdev->dev; + return ipa_smmu_uc_cb_probe(dev); + case IPA_SMMU_CB_RTP: + ipa3_ctx->rtp_pdev = &ipa3_ctx->master_pdev->dev; + return ipa_smmu_rtp_cb_probe(dev); + case IPA_SMMU_CB_11AD: + return ipa_smmu_11ad_cb_probe(dev); + case IPA_SMMU_CB_MAX: + IPAERR("Invalid cb_type\n"); + } + return 0; +} + +static int ipa3_attach_to_smmu(void) +{ + struct ipa_smmu_cb_ctx *cb; + int i, result; + + if (smmu_info.arm_smmu) { + IPADBG("smmu is enabled\n"); + for (i = 0; i < IPA_SMMU_CB_MAX; i++) { + cb = ipa3_get_smmu_ctx(i); + result = ipa_smmu_cb_probe(cb->dev, i); + if (result) { + IPAERR("probe failed for cb %d\n", i); + return result; + } + } + } else { + ipa3_ctx->pdev = &ipa3_ctx->master_pdev->dev; + ipa3_ctx->uc_pdev = &ipa3_ctx->master_pdev->dev; + IPADBG("smmu is disabled\n"); + } + return 0; +} + +static irqreturn_t ipa3_smp2p_modem_clk_query_isr(int irq, void *ctxt) +{ + ipa3_freeze_clock_vote_and_notify_modem(); + + return IRQ_HANDLED; +} + +static int ipa3_smp2p_probe(struct device *dev) +{ + struct device_node *node = dev->of_node; + int res; + int irq = 0; + + if (ipa3_ctx == NULL) { + IPAERR("ipa3_ctx was not initialized\n"); + return -EPROBE_DEFER; + } + IPADBG("node->name=%s\n", node->name); + if (ipa3_ctx->platform_type == IPA_PLAT_TYPE_APQ) { + IPADBG("Ignore smp2p on APQ platform\n"); + return 0; + } + + if (strcmp("qcom,smp2p_map_ipa_1_out", node->name) == 0) { + if (of_find_property(node, "qcom,smem-states", NULL)) { + ipa3_ctx->smp2p_info.smem_state = + qcom_smem_state_get(dev, "ipa-smp2p-out", + &ipa3_ctx->smp2p_info.smem_bit); + if (IS_ERR(ipa3_ctx->smp2p_info.smem_state)) { + IPAERR("fail to get smp2p clk resp bit %ld\n", + PTR_ERR(ipa3_ctx->smp2p_info.smem_state)); + return PTR_ERR(ipa3_ctx->smp2p_info.smem_state); + } + IPADBG("smem_bit=%d\n", ipa3_ctx->smp2p_info.smem_bit); + } + } else if (strcmp("qcom,smp2p_map_ipa_1_in", node->name) == 0) { + res = irq = of_irq_get_byname(node, "ipa-smp2p-in"); + if (res < 0) { + IPADBG("of_irq_get_byname returned %d\n", irq); + return res; + } + + ipa3_ctx->smp2p_info.in_base_id = irq; + IPADBG("smp2p irq#=%d\n", irq); + res = devm_request_threaded_irq(dev, irq, NULL, + (irq_handler_t)ipa3_smp2p_modem_clk_query_isr, + IRQF_TRIGGER_RISING | IRQF_ONESHOT, + "ipa_smp2p_clk_vote", dev); + if (res) { + IPAERR("fail to register smp2p irq=%d\n", irq); + return -ENODEV; + } + } + return 0; +} + +static int ipa_smmu_update_fw_loader(void) +{ + int i, result; + int cnt = 0; + + if (smmu_info.arm_smmu) { + IPADBG("smmu is enabled\n"); + for (i = 0; i < IPA_SMMU_CB_MAX; i++) { + if (!smmu_info.present[i]) { + IPADBG("CB %d not probed yet\n", i); + } else { + cnt++; + IPADBG("CB %d probed\n", i); + } + } + if (cnt == IPA_SMMU_CB_MAX || + ipa3_ctx->num_smmu_cb_probed == + ipa3_ctx->max_num_smmu_cb) { + IPADBG("All %d CBs probed\n", IPA_SMMU_CB_MAX); + + if (ipa3_ctx->use_xbl_boot) { + IPAERR("Using XBL boot load for IPA FW\n"); + mutex_lock(&ipa3_ctx->fw_load_data.lock); + ipa3_ctx->fw_load_data.state = IPA_FW_LOAD_STATE_LOADED; + mutex_unlock(&ipa3_ctx->fw_load_data.lock); + + result = ipa3_attach_to_smmu(); + if (result) { + IPAERR("IPA attach to smmu failed %d\n", + result); + return result; + } + + result = ipa3_post_init(&ipa3_res, ipa3_ctx->cdev.dev); + if (result) { + IPAERR("IPA post init failed %d\n", result); + return result; + } + } else { + + ipa_fw_load_sm_handle_event(IPA_FW_LOAD_EVNT_SMMU_DONE); + } + } + } else { + IPADBG("smmu is disabled\n"); + } + + return 0; +} + +int ipa3_plat_drv_probe(struct platform_device *pdev_p) +{ + int result; + struct device *dev = &pdev_p->dev; + struct ipa_smmu_cb_ctx *cb; + + /* + * IPA probe function can be called for multiple times as the same probe + * function handles multiple compatibilities + */ + pr_debug("ipa: IPA driver probing started for %s\n", + pdev_p->dev.of_node->name); + + if (ipa3_ctx == NULL) { + IPAERR("ipa3_ctx was not initialized\n"); + return -EPROBE_DEFER; + } + + if (ipa3_ctx->ipa_hw_type == 0) { + + /* Get IPA HW Version */ + result = of_property_read_u32(pdev_p->dev.of_node, + "qcom,ipa-hw-ver", &ipa3_ctx->ipa_hw_type); + if ((result) || (ipa3_ctx->ipa_hw_type == IPA_HW_None)) { + pr_err("ipa: get resource failed for ipa-hw-ver!\n"); + return -ENODEV; + } + pr_debug("ipa: ipa_hw_type = %d\n", ipa3_ctx->ipa_hw_type); + } + + if (ipa3_ctx->ipa_hw_type < IPA_HW_v3_0) { + pr_err(":IPA version below 3.0 not supported\n"); + return -ENODEV; + } + + if (ipa3_ctx->ipa_hw_type >= IPA_HW_MAX) { + pr_err(":IPA version is greater than the MAX\n"); + return -ENODEV; + } + + IPADBG("IPA driver probing started\n"); + IPADBG("dev->of_node->name = %s\n", dev->of_node->name); + + if (of_device_is_compatible(dev->of_node, "qcom,ipa-smmu-ap-cb")) { + cb = ipa3_get_smmu_ctx(IPA_SMMU_CB_AP); + cb->dev = dev; + smmu_info.present[IPA_SMMU_CB_AP] = true; + ipa3_ctx->num_smmu_cb_probed++; + return ipa_smmu_update_fw_loader(); + } + + if (of_device_is_compatible(dev->of_node, "qcom,ipa-smmu-wlan-cb")) { + cb = ipa3_get_smmu_ctx(IPA_SMMU_CB_WLAN); + cb->dev = dev; + smmu_info.present[IPA_SMMU_CB_WLAN] = true; + ipa3_ctx->num_smmu_cb_probed++; + return ipa_smmu_update_fw_loader(); + } + + if (of_device_is_compatible(dev->of_node, "qcom,ipa-smmu-wlan1-cb")) { + cb = ipa3_get_smmu_ctx(IPA_SMMU_CB_WLAN1); + cb->dev = dev; + smmu_info.present[IPA_SMMU_CB_WLAN1] = true; + ipa3_ctx->num_smmu_cb_probed++; + return ipa_smmu_update_fw_loader(); + } + + if (of_device_is_compatible(dev->of_node, "qcom,ipa-smmu-eth-cb")) { + cb = ipa3_get_smmu_ctx(IPA_SMMU_CB_ETH); + cb->dev = dev; + smmu_info.present[IPA_SMMU_CB_ETH] = true; + ipa3_ctx->num_smmu_cb_probed++; + return ipa_smmu_update_fw_loader(); + } + + if (of_device_is_compatible(dev->of_node, "qcom,ipa-smmu-eth1-cb")) { + cb = ipa3_get_smmu_ctx(IPA_SMMU_CB_ETH1); + cb->dev = dev; + smmu_info.present[IPA_SMMU_CB_ETH1] = true; + ipa3_ctx->num_smmu_cb_probed++; + return ipa_smmu_update_fw_loader(); + } + + if (of_device_is_compatible(dev->of_node, "qcom,ipa-smmu-uc-cb")) { + cb = ipa3_get_smmu_ctx(IPA_SMMU_CB_UC); + cb->dev = dev; + smmu_info.present[IPA_SMMU_CB_UC] = true; + ipa3_ctx->num_smmu_cb_probed++; + return ipa_smmu_update_fw_loader(); + } + + if (of_device_is_compatible(dev->of_node, "qcom,ipa-smmu-11ad-cb")) { + cb = ipa3_get_smmu_ctx(IPA_SMMU_CB_11AD); + cb->dev = dev; + smmu_info.present[IPA_SMMU_CB_11AD] = true; + ipa3_ctx->num_smmu_cb_probed++; + return ipa_smmu_update_fw_loader(); + } + + if (of_device_is_compatible(dev->of_node, "qcom,ipa-smmu-rtp-cb")) { + cb = ipa3_get_smmu_ctx(IPA_SMMU_CB_RTP); + cb->dev = dev; + smmu_info.present[IPA_SMMU_CB_RTP] = true; + ipa3_ctx->num_smmu_cb_probed++; + return ipa_smmu_update_fw_loader(); + } + + if (of_device_is_compatible(dev->of_node, + "qcom,smp2p-map-ipa-1-out")) + return ipa3_smp2p_probe(dev); + if (of_device_is_compatible(dev->of_node, + "qcom,smp2p-map-ipa-1-in")) + return ipa3_smp2p_probe(dev); + + result = get_ipa_dts_configuration(pdev_p, &ipa3_res); + if (result) { + IPAERR("IPA dts parsing failed\n"); + return result; + } + + /* + * Since we now know where the transport's registers live, + * let's set up access to them. This is done since subsequent + * functions, that deal with the transport, require the + * access. + */ + if (gsi_map_base( + ipa3_res.transport_mem_base, + ipa3_res.transport_mem_size, + ipa3_get_gsi_ver(ipa3_res.ipa_hw_type)) != 0) { + IPAERR("Allocation of gsi base failed\n"); + return -EFAULT; + } + + /* Get GSI version */ + ipa3_ctx->gsi_ver = ipa3_get_gsi_ver(ipa3_res.ipa_hw_type); + + if (of_property_read_bool(pdev_p->dev.of_node, "qcom,arm-smmu")) { + if (of_property_read_bool(pdev_p->dev.of_node, + "qcom,use-64-bit-dma-mask")) { + smmu_info.use_64_bit_dma_mask = true; + if (dma_set_mask_and_coherent(&pdev_p->dev, DMA_BIT_MASK(64))) { + IPAERR("DMA set 64bit mask failed\n"); + return -EOPNOTSUPP; + } + } + smmu_info.arm_smmu = true; + } else { + if (of_property_read_bool(pdev_p->dev.of_node, + "qcom,use-64-bit-dma-mask")) { + if (dma_set_mask_and_coherent(&pdev_p->dev, DMA_BIT_MASK(64))) { + IPAERR("DMA set 64bit mask failed\n"); + return -EOPNOTSUPP; + } + } else { + if (dma_set_mask_and_coherent(&pdev_p->dev, DMA_BIT_MASK(32))) { + IPAERR("DMA set 32bit mask failed\n"); + return -EOPNOTSUPP; + } + } + /* Below update of pre init for non smmu device, As + * existing flow initialzies only for smmu + * enabled node.*/ + + result = ipa3_pre_init(&ipa3_res, pdev_p); + if (result) { + IPAERR("ipa3_init failed\n"); + return result; + } + ipa_fw_load_sm_handle_event(IPA_FW_LOAD_EVNT_SMMU_DONE); + goto skip_repeat_pre_init; + } + + /* Proceed to real initialization */ + result = ipa3_pre_init(&ipa3_res, pdev_p); + if (result) { + IPAERR("ipa3_init failed\n"); + return result; + } + +skip_repeat_pre_init: + result = of_platform_populate(pdev_p->dev.of_node, + ipa_plat_drv_match, NULL, &pdev_p->dev); + if (result) { + IPAERR("failed to populate platform\n"); + return result; + } + + if (result && result != -EPROBE_DEFER) + IPAERR("ipa: ipa_plat_drv_probe failed\n"); + + return result; +} + +/** + * ipa3_ap_suspend() - suspend callback for runtime_pm + * @dev: pointer to device + * + * This callback will be invoked by the runtime_pm framework when an AP suspend + * operation is invoked, usually by pressing a suspend button. + * + * Returns -EAGAIN to runtime_pm framework in case IPA is in use by AP. + * This will postpone the suspend operation until IPA is no longer used by AP. + */ +int ipa3_ap_suspend(struct device *dev) +{ + int i; + + IPADBG("Enter...\n"); + if (!of_device_is_compatible(dev->of_node,"qcom,ipa")) + return 0; + /* In case there is a tx/rx handler in polling mode fail to suspend */ + for (i = 0; i < ipa3_ctx->ipa_num_pipes; i++) { + if (ipa3_ctx->ep[i].sys && + atomic_read(&ipa3_ctx->ep[i].sys->curr_polling_state)) { + IPAERR("EP %d is in polling state, do not suspend\n", + i); + return -EAGAIN; + } + } + + +#if IS_ENABLED(CONFIG_DEEPSLEEP) + if (pm_suspend_via_firmware()) { + IPADBG("Enter deepsleep suspend\n"); + ipa3_deepsleep_suspend(); + IPADBG("Exit deepsleep suspend\n"); + } +#endif + ipa_pm_deactivate_all_deferred(); + + IPADBG("Exit\n"); + + return 0; +} + +#if IS_ENABLED(CONFIG_HIBERNATION) +/** + * ipa3_ap_freeze() - hibernate freeze callback for runtime_pm + * @dev: pointer to device + * + * This callback will be invoked by the runtime_pm framework when an AP + * hibernate freeze operation is invoked, usually by pressing a hibernate button. + * + * Returns -EAGAIN to runtime_pm framework in case IPA is in use by AP. + * This will postpone the suspend/freeze operation until IPA is no longer used by AP. + */ +int ipa3_ap_freeze(struct device *dev) +{ + int i; + + IPADBG("Enter\n"); + + if (!of_device_is_compatible(dev->of_node, "qcom,ipa")) + return 0; + /* In case there is a tx/rx handler in polling mode fail to suspend */ + for (i = 0; i < ipa3_ctx->ipa_num_pipes; i++) { + if (ipa3_ctx->ep[i].sys && + atomic_read(&ipa3_ctx->ep[i].sys->curr_polling_state)) { + IPAERR("EP %d is in polling state, do not suspend\n", + i); + return -EAGAIN; + } + } + + IPADBG("Enter hibernate freeze\n"); + ipa3_deepsleep_suspend(); + IPADBG("Exit hibernate freeze\n"); + + ipa_pm_deactivate_all_deferred(); + + IPADBG("Exit\n"); + return 0; +} +#endif + +/** + * ipa3_ap_resume() - resume callback for runtime_pm + * @dev: pointer to device + * + * This callback will be invoked by the runtime_pm framework when an AP resume + * operation is invoked. + * + * Always returns 0 since resume should always succeed. + */ +int ipa3_ap_resume(struct device *dev) +{ + return 0; +} + +struct ipa3_context *ipa3_get_ctx(void) +{ + return ipa3_ctx; +} +EXPORT_SYMBOL(ipa3_get_ctx); + +bool ipa_get_lan_rx_napi(void) +{ + return ipa3_ctx->lan_rx_napi_enable; +} +EXPORT_SYMBOL(ipa_get_lan_rx_napi); + + +#if IS_ENABLED(CONFIG_DEEPSLEEP) || IS_ENABLED(CONFIG_HIBERNATION) +static void ipa3_deepsleep_suspend(void) +{ + IPADBG("Entry\n"); + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + + /* To allow default routing table delection using this flag */ + ipa3_ctx->deepsleep = true; + ipa3_usb_exit(); + /*Disabling the LAN NAPI*/ + ipa3_disable_napi_lan_rx(); + /*NOt allow uC related operations until uC load again*/ + ipa3_ctx->uc_ctx.uc_loaded = false; + /*Disconnecting LAN PROD/LAN CONS/CMD PROD apps pipes*/ + ipa3_teardown_apps_pipes(); + /*Deregistering the GSI driver*/ + gsi_deregister_device(ipa3_ctx->gsi_dev_hdl, false); + /*Destroying filter table ids*/ + ipa3_destroy_flt_tbl_idrs(); + /*Disabling IPA interrupt*/ + ipa3_remove_interrupt_handler(IPA_TX_SUSPEND_IRQ); + ipa3_interrupts_destroy(ipa3_res.ipa_irq, &ipa3_ctx->master_pdev->dev); + ipa3_uc_interface_destroy(); + /*Destroy the NAT device*/ + ipa3_nat_ipv6ct_destroy_devices(); + /*Freeing memory allocated for coalesing and dma task*/ + ipa3_free_coal_close_frame(); + ipa3_free_dma_task_for_gsi(); + /*Destroying ipa hal module*/ + ipahal_destroy(); + ipa3_ctx->ipa_initialization_complete = false; + ipa3_debugfs_remove(); + /*Unloading IPA FW to allow FW load in resume*/ + ipa3_pil_unload_ipa_fws(); + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + IPADBG("Exit\n"); +} + +static void ipa3_deepsleep_resume(void) +{ + + IPADBG("Entry\n"); + /*After deeplseep exit we shouldn't allow delete the default routing table*/ + ipa3_ctx->deepsleep = false; + /*Scheduling WQ to load IPA FW*/ + queue_work(ipa3_ctx->transport_power_mgmt_wq, + &ipa3_fw_loading_work); + IPADBG("Exit\n"); +} +#endif + +static void ipa_gsi_notify_cb(struct gsi_per_notify *notify) +{ + /* + * These values are reported by hardware. Any error indicates + * hardware unexpected state. + */ + switch (notify->evt_id) { + case GSI_PER_EVT_GLOB_ERROR: + IPAERR("Got GSI_PER_EVT_GLOB_ERROR\n"); + IPAERR("Err_desc = 0x%04x\n", notify->data.err_desc); + break; + case GSI_PER_EVT_GLOB_GP1: + IPAERR("Got GSI_PER_EVT_GLOB_GP1\n"); + ipa_assert(); + break; + case GSI_PER_EVT_GLOB_GP2: + IPAERR("Got GSI_PER_EVT_GLOB_GP2\n"); + ipa_assert(); + break; + case GSI_PER_EVT_GLOB_GP3: + IPAERR("Got GSI_PER_EVT_GLOB_GP3\n"); + ipa_assert(); + break; + case GSI_PER_EVT_GENERAL_BREAK_POINT: + IPAERR("Got GSI_PER_EVT_GENERAL_BREAK_POINT\n"); + break; + case GSI_PER_EVT_GENERAL_BUS_ERROR: + IPAERR("Got GSI_PER_EVT_GENERAL_BUS_ERROR\n"); + ipa_assert(); + break; + case GSI_PER_EVT_GENERAL_CMD_FIFO_OVERFLOW: + IPAERR("Got GSI_PER_EVT_GENERAL_CMD_FIFO_OVERFLOW\n"); + ipa_assert(); + break; + case GSI_PER_EVT_GENERAL_MCS_STACK_OVERFLOW: + IPAERR("Got GSI_PER_EVT_GENERAL_MCS_STACK_OVERFLOW\n"); + ipa_assert(); + break; + default: + IPAERR("Received unexpected evt: %d\n", + notify->evt_id); + ipa_assert(); + } +} + +int ipa3_iommu_map(struct iommu_domain *domain, + unsigned long iova, phys_addr_t paddr, size_t size, int prot) +{ + struct ipa_smmu_cb_ctx *cb = NULL; + + IPADBG_LOW("domain =0x%pK iova 0x%lx\n", domain, iova); + IPADBG_LOW("paddr =0x%pa size 0x%x\n", &paddr, (u32)size); + + /* make sure no overlapping */ + if (domain == ipa3_get_smmu_domain()) { + cb = ipa3_get_smmu_ctx(IPA_SMMU_CB_AP); + if (iova >= cb->va_start && iova < cb->va_end) { + IPAERR("iommu AP overlap addr 0x%lx\n", iova); + ipa_assert(); + return -EFAULT; + } + } else if (domain == ipa3_get_wlan_smmu_domain()) { + /* wlan is one time map */ + cb = ipa3_get_smmu_ctx(IPA_SMMU_CB_WLAN); + } else if (domain == ipa3_get_wlan1_smmu_domain()) { + /* wlan1 is one time map */ + cb = ipa3_get_smmu_ctx(IPA_SMMU_CB_WLAN1); + } else if (domain == ipa3_get_eth_smmu_domain()) { + /* eth is one time map */ + cb = ipa3_get_smmu_ctx(IPA_SMMU_CB_ETH); + } else if (domain == ipa3_get_eth1_smmu_domain()) { + /* eth1 is one time map */ + cb = ipa3_get_smmu_ctx(IPA_SMMU_CB_ETH1); + } else if (domain == ipa3_get_11ad_smmu_domain()) { + /* 11ad is one time map */ + cb = ipa3_get_smmu_ctx(IPA_SMMU_CB_11AD); + } else if (domain == ipa3_get_uc_smmu_domain()) { + cb = ipa3_get_smmu_ctx(IPA_SMMU_CB_UC); + if (iova >= cb->va_start && iova < cb->va_end) { + IPAERR("iommu uC overlap addr 0x%lx\n", iova); + ipa_assert(); + return -EFAULT; + } + } else if (domain == ipa3_get_rtp_smmu_domain()) { + cb = ipa3_get_smmu_ctx(IPA_SMMU_CB_RTP); + if (iova >= cb->va_start && iova < cb->va_end) { + IPAERR("iommu rtp overlap addr 0x%lx\n", iova); + ipa_assert(); + return -EFAULT; + } + } else { + IPAERR("Unexpected domain 0x%pK\n", domain); + ipa_assert(); + return -EFAULT; + } + + if (cb == NULL) { + IPAERR("Unexpected cb turning NULL for domain 0x%pK\n", domain); + ipa_assert(); + } + + /* + * IOMMU_CACHE is needed to make the entries cachable + * if cache coherency is enabled in dtsi. + */ + if (cb->is_cache_coherent) + prot |= IOMMU_CACHE; + + return iommu_map_atomic(domain, iova, paddr, size, prot); +} + +/** + * ipa_get_smmu_params()- Return the ipa3 smmu related params. + */ +int ipa_get_smmu_params(struct ipa_smmu_in_params *in, + struct ipa_smmu_out_params *out) +{ + bool is_smmu_enable = false; + + if (out == NULL || in == NULL) { + IPAERR("bad parms for Client SMMU out params\n"); + return -EINVAL; + } + + if (!ipa3_ctx) { + IPAERR("IPA not yet initialized\n"); + return -EINVAL; + } + + out->shared_cb = false; + + switch (in->smmu_client) { + case IPA_SMMU_WLAN_CLIENT: + if (ipa_get_wdi_version() >= IPA_WDI_3 || + IPA_WDI2_OVER_GSI()) + is_smmu_enable = + !(ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_AP] || + ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_WLAN]); + else + is_smmu_enable = + !(ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_UC] || + ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_WLAN]); + break; + case IPA_SMMU_WLAN1_CLIENT: + is_smmu_enable = + !(ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_AP] || + ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_WLAN1]); + break; + case IPA_SMMU_ETH_CLIENT: + is_smmu_enable = + !(ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_AP] || + ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_ETH]); + break; + case IPA_SMMU_ETH1_CLIENT: + is_smmu_enable = + !(ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_AP] || + ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_ETH1]); + break; + case IPA_SMMU_WIGIG_CLIENT: + is_smmu_enable = !(ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_UC] || + ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_11AD] || + ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_AP]); + if (is_smmu_enable) { + if (ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_UC] || + ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_11AD] || + ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_AP]) { + IPAERR("11AD SMMU Discrepancy (%d %d %d)\n", + ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_UC], + ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_AP], + ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_11AD]); + WARN_ON(1); + return -EINVAL; + } + } else { + if (!ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_UC] || + !ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_11AD] || + !ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_AP]) { + IPAERR("11AD SMMU Discrepancy (%d %d %d)\n", + ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_UC], + ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_AP], + ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_11AD]); + WARN_ON(1); + return -EINVAL; + } + } + out->shared_cb = (ipa3_get_smmu_ctx(IPA_SMMU_CB_11AD))->shared; + break; + case IPA_SMMU_AP_CLIENT: + is_smmu_enable = + !(ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_AP]); + break; + default: + is_smmu_enable = false; + IPAERR("Trying to get illegal clients SMMU status"); + return -EINVAL; + } + + out->smmu_enable = is_smmu_enable; + + return 0; +} +EXPORT_SYMBOL(ipa_get_smmu_params); + +#define MAX_LEN 96 + +void ipa_pc_qmp_enable(void) +{ + char buf[MAX_LEN] = "{class: bcm, res: ipa_pc, val: 1}"; + struct qmp_pkt pkt; + int ret = 0; + struct ipa3_pc_mbox_data *mbox_data = &ipa3_ctx->pc_mbox; + + IPADBG("Enter\n"); + + /* prepare the mailbox struct */ + mbox_data->mbox_client.dev = &ipa3_ctx->master_pdev->dev; + mbox_data->mbox_client.tx_block = true; + mbox_data->mbox_client.tx_tout = MBOX_TOUT_MS; + mbox_data->mbox_client.knows_txdone = false; + + mbox_data->mbox = mbox_request_channel(&mbox_data->mbox_client, 0); + if (IS_ERR(mbox_data->mbox)) { + ret = PTR_ERR(mbox_data->mbox); + if (ret != -EPROBE_DEFER) + IPAERR("mailbox channel request failed, ret=%d\n", ret); + + return; + } + + /* prepare the QMP packet to send */ + pkt.size = MAX_LEN; + pkt.data = buf; + + /* send the QMP packet to AOP */ + ret = mbox_send_message(mbox_data->mbox, &pkt); + if (ret < 0) + IPAERR("qmp message send failed, ret=%d\n", ret); + + if (mbox_data->mbox) { + mbox_free_channel(mbox_data->mbox); + mbox_data->mbox = NULL; + } +} + +/************************************************************** + * PCIe Version + *************************************************************/ + +int ipa3_pci_drv_probe(struct pci_dev *pci_dev, const struct pci_device_id *ent) +{ + int result; + struct ipa3_plat_drv_res *ipa_drv_res; + u32 bar0_offset; + u32 mem_start; + u32 mem_end; + uint32_t bits; + uint32_t ipa_start, gsi_start, intctrl_start; + struct device *dev; + static struct platform_device platform_dev; + + if (!pci_dev || !ent) { + pr_err( + "Bad arg: pci_dev (%pK) and/or ent (%pK)\n", + pci_dev, ent); + return -EOPNOTSUPP; + } + + if (ipa3_ctx == NULL) { + IPAERR("ipa3_ctx was not initialized\n"); + return -EPROBE_DEFER; + } + + if (ipa3_ctx->ipa_hw_type == 0) { + /* Get IPA HW Version */ + result = of_property_read_u32(NULL, + "qcom,ipa-hw-ver", &ipa3_ctx->ipa_hw_type); + if (result || ipa3_ctx->ipa_hw_type == IPA_HW_None) { + pr_err("ipa: get resource failed for ipa-hw-ver!\n"); + return -ENODEV; + } + pr_debug("ipa: ipa_hw_type = %d\n", ipa3_ctx->ipa_hw_type); + } + + dev = &(pci_dev->dev); + + IPADBG("IPA PCI driver probing started\n"); + + /* + * Follow PCI driver flow here. + * pci_enable_device: Enables device and assigns resources + * pci_request_region: Makes BAR0 address region usable + */ + result = pci_enable_device(pci_dev); + if (result < 0) { + IPAERR("pci_enable_device() failed\n"); + return -EOPNOTSUPP; + } + + result = pci_request_region(pci_dev, 0, "IPA Memory"); + if (result < 0) { + IPAERR("pci_request_region() failed\n"); + pci_disable_device(pci_dev); + return -EOPNOTSUPP; + } + + /* + * When in the PCI/emulation environment, &platform_dev is + * passed to get_ipa_dts_configuration(), but is unused, since + * all usages of it in the function are replaced by CPP + * relative to definitions in ipa_emulation_stubs.h. Passing + * &platform_dev makes code validity tools happy. + */ + if (get_ipa_dts_configuration(&platform_dev, &ipa3_res) != 0) { + IPAERR("get_ipa_dts_configuration() failed\n"); + pci_release_region(pci_dev, 0); + pci_disable_device(pci_dev); + return -EOPNOTSUPP; + } + + ipa_drv_res = &ipa3_res; + + result = + of_property_read_u32(NULL, "emulator-bar0-offset", + &bar0_offset); + if (result) { + IPAERR(":get resource failed for emulator-bar0-offset!\n"); + pci_release_region(pci_dev, 0); + pci_disable_device(pci_dev); + return -ENODEV; + } + IPADBG(":using emulator-bar0-offset 0x%08X\n", bar0_offset); + + ipa_start = ipa_drv_res->ipa_mem_base; + gsi_start = ipa_drv_res->transport_mem_base; + intctrl_start = ipa_drv_res->emulator_intcntrlr_mem_base; + + /* + * Where will we be inerrupted at? + */ + ipa_drv_res->emulator_irq = pci_dev->irq; + IPADBG( + "EMULATION PCI_INTERRUPT_PIN(%u)\n", + ipa_drv_res->emulator_irq); + + /* + * Set the ipa_mem_base to the PCI base address of BAR0 + */ + mem_start = pci_resource_start(pci_dev, 0); + mem_end = pci_resource_end(pci_dev, 0); + + IPADBG("PCI START = 0x%x\n", mem_start); + IPADBG("PCI END = 0x%x\n", mem_end); + + ipa_drv_res->ipa_mem_base = mem_start + bar0_offset; + + smmu_info.ipa_base = ipa_drv_res->ipa_mem_base; + smmu_info.ipa_size = ipa_drv_res->ipa_mem_size; + + ipa_drv_res->transport_mem_base = + ipa_drv_res->ipa_mem_base + (gsi_start - ipa_start); + + ipa_drv_res->emulator_intcntrlr_mem_base = + ipa_drv_res->ipa_mem_base + (intctrl_start - ipa_start); + + IPADBG("ipa_mem_base = 0x%x\n", + ipa_drv_res->ipa_mem_base); + IPADBG("ipa_mem_size = 0x%x\n", + ipa_drv_res->ipa_mem_size); + + IPADBG("transport_mem_base = 0x%x\n", + ipa_drv_res->transport_mem_base); + IPADBG("transport_mem_size = 0x%x\n", + ipa_drv_res->transport_mem_size); + + IPADBG("emulator_intcntrlr_mem_base = 0x%x\n", + ipa_drv_res->emulator_intcntrlr_mem_base); + IPADBG("emulator_intcntrlr_mem_size = 0x%x\n", + ipa_drv_res->emulator_intcntrlr_mem_size); + + bits = (ipa_drv_res->use_64_bit_dma_mask) ? 64 : 32; + + if (dma_set_mask(dev, DMA_BIT_MASK(bits)) != 0) { + IPAERR("dma_set_mask(%pK, %u) failed\n", dev, bits); + pci_release_region(pci_dev, 0); + pci_disable_device(pci_dev); + return -EOPNOTSUPP; + } + + if (dma_set_coherent_mask(dev, DMA_BIT_MASK(bits)) != 0) { + IPAERR("dma_set_coherent_mask(%pK, %u) failed\n", dev, bits); + pci_release_region(pci_dev, 0); + pci_disable_device(pci_dev); + return -EOPNOTSUPP; + } + + pci_set_master(pci_dev); + + memset(&platform_dev, 0, sizeof(platform_dev)); + platform_dev.dev = *dev; + + /* Proceed to real initialization */ + result = ipa3_pre_init(&ipa3_res, &platform_dev); + if (result) { + IPAERR("ipa3_init failed\n"); + pci_clear_master(pci_dev); + pci_release_region(pci_dev, 0); + pci_disable_device(pci_dev); + return result; + } + + return result; +} + +/* + * The following returns transport register memory location and + * size... + */ +int ipa3_get_transport_info( + phys_addr_t *phys_addr_ptr, + unsigned long *size_ptr) +{ + if (!phys_addr_ptr || !size_ptr) { + IPAERR("Bad arg: phys_addr_ptr(%pK) and/or size_ptr(%pK)\n", + phys_addr_ptr, size_ptr); + return -EINVAL; + } + + *phys_addr_ptr = ipa3_res.transport_mem_base; + *size_ptr = ipa3_res.transport_mem_size; + + return 0; +} +EXPORT_SYMBOL(ipa3_get_transport_info); + +static uint emulation_type = IPA_HW_v4_0; + +/* + * The following returns emulation type... + */ +uint ipa3_get_emulation_type(void) +{ + return emulation_type; +} + +static int __init ipa_module_init(void) +{ + pr_debug("IPA module init\n"); + + ipa3_ctx = kzalloc(sizeof(*ipa3_ctx), GFP_KERNEL); + if (!ipa3_ctx) { + return -ENOMEM; + } + mutex_init(&ipa3_ctx->lock); + INIT_LIST_HEAD(&ipa3_ctx->ipa_ready_cb_list); + + if (running_emulation) { + /* Register as a PCI device driver */ + return pci_register_driver(&ipa_pci_driver); + } +#ifdef CONFIG_IPA_RTP + ipa_rtp_genl_init(); +#endif + + register_pm_notifier(&ipa_pm_notifier); + /* Register as a platform device driver */ + return platform_driver_register(&ipa_plat_drv); +} +subsys_initcall(ipa_module_init); + +static void __exit ipa_module_exit(void) +{ + if (running_emulation) + pci_unregister_driver(&ipa_pci_driver); + platform_driver_unregister(&ipa_plat_drv); + if(ipa3_ctx->hw_stats) { + kfree(ipa3_ctx->hw_stats); + ipa3_ctx->hw_stats = NULL; + } +#ifdef CONFIG_IPA_RTP + ipa_rtp_genl_deinit(); +#endif + unregister_pm_notifier(&ipa_pm_notifier); + kfree(ipa3_ctx); + ipa3_ctx = NULL; +} +module_exit(ipa_module_exit); + +MODULE_SOFTDEP("pre: subsys-pil-tz"); +MODULE_SOFTDEP("pre: qcom-arm-smmu-mod"); +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("IPA HW device driver"); + +/* + * Module parameter. Invoke as follows: + * insmod ipat.ko emulation_type=[13|14|17|...|N] + * Examples: + * insmod ipat.ko emulation_type=13 # for IPA 3.5.1 + * insmod ipat.ko emulation_type=14 # for IPA 4.0 + * insmod ipat.ko emulation_type=17 # for IPA 4.5 + * + * NOTE: The emulation_type values need to come from: enum ipa_hw_type + * + */ + +module_param(emulation_type, uint, 0000); +MODULE_PARM_DESC( + emulation_type, + "emulation_type=N N can be 13 for IPA 3.5.1, 14 for IPA 4.0, 17 for IPA 4.5"); diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_client.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_client.c new file mode 100644 index 0000000000..90ec936293 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_client.c @@ -0,0 +1,2172 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include "ipa_i.h" +#include "ipahal.h" +#include +#include "gsi.h" + +/* + * These values were determined empirically and shows good E2E bi- + * directional throughputs + */ +#define IPA_POLL_AGGR_STATE_RETRIES_NUM 3 +#define IPA_POLL_AGGR_STATE_SLEEP_USEC_MIN 1010 +#define IPA_POLL_AGGR_STATE_SLEEP_USEC_MAX 1050 + +#define IPA_PKT_FLUSH_TO_US 100 + +#define IPA_POLL_FOR_EMPTINESS_NUM 50 +#define IPA_POLL_FOR_EMPTINESS_SLEEP_USEC 20 +#define IPA_CHANNEL_STOP_IN_PROC_TO_MSEC 5 +#define IPA_CHANNEL_STOP_IN_PROC_SLEEP_USEC 200 + +/* xfer_rsc_idx should be 7 bits */ +#define IPA_XFER_RSC_IDX_MAX 127 + +static int ipa3_is_xdci_channel_empty(struct ipa3_ep_context *ep, + bool *is_empty); +static void ipa3_start_gsi_debug_monitor(u32 clnt_hdl); + +int ipa3_enable_data_path(u32 clnt_hdl) +{ + struct ipa3_ep_context *ep = &ipa3_ctx->ep[clnt_hdl]; + struct ipa_ep_cfg_holb holb_cfg; + struct ipa_ep_cfg_ctrl ep_cfg_ctrl; + int res = 0; + struct ipahal_reg_endp_init_rsrc_grp rsrc_grp; + + /* Assign the resource group for pipe */ + memset(&rsrc_grp, 0, sizeof(rsrc_grp)); + rsrc_grp.rsrc_grp = ipa_get_ep_group(ep->client); + if (rsrc_grp.rsrc_grp == -1) { + IPAERR("invalid group for client %d\n", ep->client); + WARN_ON(1); + return -EFAULT; + } + + IPADBG("Setting group %d for pipe %d\n", + rsrc_grp.rsrc_grp, clnt_hdl); + ipahal_write_reg_n_fields(IPA_ENDP_INIT_RSRC_GRP_n, clnt_hdl, + &rsrc_grp); + + IPADBG("Enabling data path\n"); + if (IPA_CLIENT_IS_CONS(ep->client)) { + memset(&holb_cfg, 0, sizeof(holb_cfg)); + /* + * Set HOLB on USB DPL CONS to avoid IPA stall + * if DPL client is not pulling the data + * on other end from IPA hw. + */ + if ((ep->client == IPA_CLIENT_USB_DPL_CONS) || + (ep->client == IPA_CLIENT_TPUT_CONS) || + (ep->client == IPA_CLIENT_MHI_DPL_CONS) || + (ep->client == IPA_CLIENT_MHI_QDSS_CONS)) { + holb_cfg.en = IPA_HOLB_TMR_EN; + holb_cfg.tmr_val = 0; + } else if (ipa3_ctx->ipa_hw_type == IPA_HW_v4_11 && + (ep->client == IPA_CLIENT_WLAN1_CONS || + ep->client == IPA_CLIENT_WLAN2_CONS || + ep->client == IPA_CLIENT_USB_CONS)) { + holb_cfg.en = IPA_HOLB_TMR_EN; + holb_cfg.tmr_val = IPA_HOLB_TMR_VAL_4_5; + } else if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_1 && + ipa3_ctx->platform_type == IPA_PLAT_TYPE_APQ && + ep->client == IPA_CLIENT_USB_CONS) { + holb_cfg.en = IPA_HOLB_TMR_EN; + holb_cfg.tmr_val = IPA_HOLB_TMR_VAL_4_5; + } else if ((ipa3_ctx->ipa_hw_type == IPA_HW_v4_5) && + (ep->client == IPA_CLIENT_USB_CONS)) { + holb_cfg.tmr_val = IPA_HOLB_TMR_VAL_4_5; + holb_cfg.en = IPA_HOLB_TMR_EN; + } else if ((ipa3_ctx->ipa_hw_type >= IPA_HW_v5_2) && + (ep->client == IPA_CLIENT_USB_CONS || + ep->client == IPA_CLIENT_APPS_WAN_CONS)) { + holb_cfg.tmr_val = IPA_HOLB_TMR_VAL_4_5; + holb_cfg.en = IPA_HOLB_TMR_EN; + } else if ((ipa3_ctx->ipa_hw_type >= IPA_HW_v5_5) && + ep->client == IPA_CLIENT_APPS_WAN_COAL_CONS) { + holb_cfg.tmr_val = IPA_HOLB_TMR_VAL_4_5; + holb_cfg.en = IPA_HOLB_TMR_EN; + } else { + holb_cfg.en = IPA_HOLB_TMR_DIS; + holb_cfg.tmr_val = 0; + } + res = ipa3_cfg_ep_holb(clnt_hdl, &holb_cfg); + } + + /* Enable the pipe */ + if (ipa3_ctx->ipa_hw_type < IPA_HW_v4_0) { + if (IPA_CLIENT_IS_CONS(ep->client) && + (ep->keep_ipa_awake || + ipa3_ctx->resume_on_connect[ep->client] || + !ipa3_should_pipe_be_suspended(ep->client))) { + memset(&ep_cfg_ctrl, 0, sizeof(ep_cfg_ctrl)); + ep_cfg_ctrl.ipa_ep_suspend = false; + res = ipa_cfg_ep_ctrl(clnt_hdl, &ep_cfg_ctrl); + } + } + + return res; +} + +int ipa3_disable_data_path(u32 clnt_hdl) +{ + struct ipa3_ep_context *ep = &ipa3_ctx->ep[clnt_hdl]; + struct ipa_ep_cfg_holb holb_cfg; + struct ipa_ep_cfg_ctrl ep_cfg_ctrl; + struct ipa_ep_cfg_aggr ep_aggr; + int res = 0; + + IPADBG("Disabling data path\n"); + if (IPA_CLIENT_IS_CONS(ep->client)) { + /* + * for RG10 workaround uC needs to be loaded before + * pipe can be suspended in this case. + */ + if (ipa3_ctx->apply_rg10_wa && ipa3_uc_state_check()) { + IPADBG("uC is not loaded yet, waiting...\n"); + res = wait_for_completion_timeout( + &ipa3_ctx->uc_loaded_completion_obj, + 60 * HZ); + if (res == 0) + IPADBG("timeout waiting for uC load\n"); + } + + memset(&holb_cfg, 0, sizeof(holb_cfg)); + holb_cfg.en = IPA_HOLB_TMR_EN; + holb_cfg.tmr_val = 0; + res = ipa3_cfg_ep_holb(clnt_hdl, &holb_cfg); + } + + /* + * for IPA 4.0 and above aggregation frame is closed together with + * channel STOP + */ + if (ipa3_ctx->ipa_hw_type < IPA_HW_v4_0) { + /* Suspend the pipe */ + if (IPA_CLIENT_IS_CONS(ep->client)) { + memset(&ep_cfg_ctrl, 0, sizeof(struct ipa_ep_cfg_ctrl)); + ep_cfg_ctrl.ipa_ep_suspend = true; + res = ipa_cfg_ep_ctrl(clnt_hdl, &ep_cfg_ctrl); + } + + udelay(IPA_PKT_FLUSH_TO_US); + ipahal_read_reg_n_fields(IPA_ENDP_INIT_AGGR_n, clnt_hdl, + &ep_aggr); + if (ep_aggr.aggr_en) { + res = ipa3_tag_aggr_force_close(clnt_hdl); + if (res) { + IPAERR("tag process timeout client:%d err:%d\n", + clnt_hdl, res); + ipa_assert(); + } + } + } + + return res; +} + +int ipa3_reset_gsi_channel(u32 clnt_hdl) +{ + struct ipa3_ep_context *ep; + int result = -EFAULT; + enum gsi_status gsi_res; + bool undo_aggr_value = false; + struct ipahal_reg_clkon_cfg fields; + + IPADBG("entry\n"); + if (clnt_hdl >= ipa3_ctx->ipa_num_pipes || + ipa3_ctx->ep[clnt_hdl].valid == 0) { + IPAERR("Bad parameter\n"); + return -EINVAL; + } + + ep = &ipa3_ctx->ep[clnt_hdl]; + + if (!ep->keep_ipa_awake) + IPA_ACTIVE_CLIENTS_INC_EP(ipa3_get_client_mapping(clnt_hdl)); + + /* + * IPAv4.0 HW has a limitation where WSEQ in MBIM NTH header is not + * reset to 0 when MBIM pipe is reset. Workaround is to disable + * HW clock gating for AGGR block using IPA_CLKON_CFG reg. undo flag to + * disable the bit after reset is finished + */ + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_0) { + if (ep->cfg.aggr.aggr == IPA_MBIM_16 && + ep->cfg.aggr.aggr_en != IPA_BYPASS_AGGR) { + ipahal_read_reg_fields(IPA_CLKON_CFG, &fields); + if (fields.open_aggr_wrapper) { + undo_aggr_value = true; + fields.open_aggr_wrapper = false; + ipahal_write_reg_fields(IPA_CLKON_CFG, &fields); + } + } + } + + /* + * Reset channel + * If the reset called after stop, need to wait for about 1010us to 1050us + */ + usleep_range(IPA_POLL_AGGR_STATE_SLEEP_USEC_MIN, + IPA_POLL_AGGR_STATE_SLEEP_USEC_MAX); + gsi_res = gsi_reset_channel(ep->gsi_chan_hdl); + if (gsi_res != GSI_STATUS_SUCCESS) { + IPAERR("Error resetting channel: %d\n", gsi_res); + result = -EFAULT; + goto reset_chan_fail; + } + + /* undo the aggr value if flag was set above*/ + if (undo_aggr_value) { + fields.open_aggr_wrapper = false; + ipahal_write_reg_fields(IPA_CLKON_CFG, &fields); + } + + if (!ep->keep_ipa_awake) + IPA_ACTIVE_CLIENTS_DEC_EP(ipa3_get_client_mapping(clnt_hdl)); + + IPADBG("exit\n"); + return 0; + +reset_chan_fail: + /* undo the aggr value if flag was set above*/ + if (undo_aggr_value) { + fields.open_aggr_wrapper = false; + ipahal_write_reg_fields(IPA_CLKON_CFG, &fields); + } + + if (!ep->keep_ipa_awake) + IPA_ACTIVE_CLIENTS_DEC_EP(ipa3_get_client_mapping(clnt_hdl)); + return result; +} +EXPORT_SYMBOL(ipa3_reset_gsi_channel); + +int ipa3_reset_gsi_event_ring(u32 clnt_hdl) +{ + struct ipa3_ep_context *ep; + int result = -EFAULT; + enum gsi_status gsi_res; + + IPADBG("entry\n"); + if (clnt_hdl >= ipa3_ctx->ipa_num_pipes || + ipa3_ctx->ep[clnt_hdl].valid == 0) { + IPAERR("Bad parameter.\n"); + return -EINVAL; + } + + ep = &ipa3_ctx->ep[clnt_hdl]; + + if (!ep->keep_ipa_awake) + IPA_ACTIVE_CLIENTS_INC_EP(ipa3_get_client_mapping(clnt_hdl)); + /* Reset event ring */ + gsi_res = gsi_reset_evt_ring(ep->gsi_evt_ring_hdl); + if (gsi_res != GSI_STATUS_SUCCESS) { + IPAERR("Error resetting event: %d\n", gsi_res); + result = -EFAULT; + goto reset_evt_fail; + } + + if (!ep->keep_ipa_awake) + IPA_ACTIVE_CLIENTS_DEC_EP(ipa3_get_client_mapping(clnt_hdl)); + + IPADBG("exit\n"); + return 0; + +reset_evt_fail: + if (!ep->keep_ipa_awake) + IPA_ACTIVE_CLIENTS_DEC_EP(ipa3_get_client_mapping(clnt_hdl)); + return result; +} +EXPORT_SYMBOL(ipa3_reset_gsi_event_ring); + +static bool ipa3_is_legal_params(struct ipa_request_gsi_channel_params *params) +{ + if (params->client >= IPA_CLIENT_MAX) + return false; + else + return true; +} + +static void ipa3_start_gsi_debug_monitor(u32 clnt_hdl) +{ + struct IpaHwOffloadStatsAllocCmdData_t *gsi_info; + struct ipa3_ep_context *ep; + enum ipa_client_type client_type; + + IPADBG("entry\n"); + if (clnt_hdl >= ipa3_ctx->ipa_num_pipes || + ipa3_ctx->ep[clnt_hdl].valid == 0) { + IPAERR("Bad parameters.\n"); + return; + } + + ep = &ipa3_ctx->ep[clnt_hdl]; + client_type = ipa3_get_client_mapping(clnt_hdl); + + /* start uC gsi dbg stats monitor */ + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_5 && + ipa3_ctx->ipa_hw_type != IPA_HW_v4_7 && + ipa3_ctx->ipa_hw_type != IPA_HW_v4_11 && + ipa3_ctx->ipa_hw_type != IPA_HW_v5_2) { + switch (client_type) { + case IPA_CLIENT_MHI_PRIME_TETH_PROD: + gsi_info = &ipa3_ctx->gsi_info[IPA_HW_PROTOCOL_MHIP]; + gsi_info->ch_id_info[0].ch_id = ep->gsi_chan_hdl; + gsi_info->ch_id_info[0].dir = DIR_PRODUCER; + ipa3_uc_debug_stats_alloc(*gsi_info); + break; + case IPA_CLIENT_MHI_PRIME_TETH_CONS: + gsi_info = &ipa3_ctx->gsi_info[IPA_HW_PROTOCOL_MHIP]; + gsi_info->ch_id_info[1].ch_id = ep->gsi_chan_hdl; + gsi_info->ch_id_info[1].dir = DIR_CONSUMER; + ipa3_uc_debug_stats_alloc(*gsi_info); + break; + case IPA_CLIENT_MHI_PRIME_RMNET_PROD: + gsi_info = &ipa3_ctx->gsi_info[IPA_HW_PROTOCOL_MHIP]; + gsi_info->ch_id_info[2].ch_id = ep->gsi_chan_hdl; + gsi_info->ch_id_info[2].dir = DIR_PRODUCER; + ipa3_uc_debug_stats_alloc(*gsi_info); + break; + case IPA_CLIENT_MHI_PRIME_RMNET_CONS: + gsi_info = &ipa3_ctx->gsi_info[IPA_HW_PROTOCOL_MHIP]; + gsi_info->ch_id_info[3].ch_id = ep->gsi_chan_hdl; + gsi_info->ch_id_info[3].dir = DIR_CONSUMER; + ipa3_uc_debug_stats_alloc(*gsi_info); + break; + case IPA_CLIENT_USB_PROD: + gsi_info = &ipa3_ctx->gsi_info[IPA_HW_PROTOCOL_USB]; + gsi_info->ch_id_info[0].ch_id = ep->gsi_chan_hdl; + gsi_info->ch_id_info[0].dir = DIR_PRODUCER; + ipa3_uc_debug_stats_alloc(*gsi_info); + break; + case IPA_CLIENT_USB_CONS: + gsi_info = &ipa3_ctx->gsi_info[IPA_HW_PROTOCOL_USB]; + gsi_info->ch_id_info[1].ch_id = ep->gsi_chan_hdl; + gsi_info->ch_id_info[1].dir = DIR_CONSUMER; + ipa3_uc_debug_stats_alloc(*gsi_info); + break; + default: + IPADBG("client_type %d not supported\n", + client_type); + } + } +} + +int ipa3_smmu_map_peer_reg(phys_addr_t phys_addr, bool map, + enum ipa_smmu_cb_type cb_type) +{ + struct iommu_domain *smmu_domain; + int res; + + if (!VALID_IPA_SMMU_CB_TYPE(cb_type)) { + IPAERR("invalid cb_type\n"); + return -EINVAL; + } + + if (ipa3_ctx->s1_bypass_arr[cb_type]) { + IPADBG("CB# %d is set to s1 bypass\n", cb_type); + return 0; + } + + smmu_domain = ipa3_get_smmu_domain_by_type(cb_type); + if (!smmu_domain) { + IPAERR("invalid smmu domain\n"); + return -EINVAL; + } + + if (map) { + res = ipa3_iommu_map(smmu_domain, phys_addr, phys_addr, + PAGE_SIZE, IOMMU_READ | IOMMU_WRITE | IOMMU_MMIO); + } else { + res = iommu_unmap(smmu_domain, phys_addr, PAGE_SIZE); + res = (res != PAGE_SIZE); + } + if (res) { + IPAERR("Fail to %s reg 0x%pa\n", map ? "map" : "unmap", + &phys_addr); + return -EINVAL; + } + + IPADBG("Peer reg 0x%pa %s\n", &phys_addr, map ? "map" : "unmap"); + + return 0; +} +EXPORT_SYMBOL(ipa3_smmu_map_peer_reg); + +int ipa3_smmu_map_peer_buff(u64 iova, u32 size, bool map, struct sg_table *sgt, + enum ipa_smmu_cb_type cb_type) +{ + struct iommu_domain *smmu_domain; + int res, ret = 0; + phys_addr_t phys; + unsigned long va; + struct scatterlist *sg; + int count = 0; + size_t len; + int i; + struct page *page; + + if (!VALID_IPA_SMMU_CB_TYPE(cb_type)) { + IPAERR("invalid cb_type\n"); + return -EINVAL; + } + + if (ipa3_ctx->s1_bypass_arr[cb_type]) { + IPADBG("CB# %d is set to s1 bypass\n", cb_type); + return 0; + } + + smmu_domain = ipa3_get_smmu_domain_by_type(cb_type); + if (!smmu_domain) { + IPAERR("invalid smmu domain\n"); + return -EINVAL; + } + + /* + * USB GSI driver would update sgt irrespective of USB S1 + * is enable or bypass. + * If USB S1 is enabled using IOMMU, iova != pa. + * If USB S1 is bypass, iova == pa. + */ + if (map) { + if (sgt != NULL) { + va = rounddown(iova, PAGE_SIZE); + for_each_sg(sgt->sgl, sg, sgt->nents, i) { + page = sg_page(sg); + phys = page_to_phys(page); + len = PAGE_ALIGN(sg->offset + sg->length); + res = ipa3_iommu_map(smmu_domain, va, phys, + len, IOMMU_READ | IOMMU_WRITE); + if (res) { + IPAERR("Fail to map pa=%pa, va 0x%X\n", + &phys, va); + return -EINVAL; + } + va += len; + count++; + } + } else { + res = ipa3_iommu_map(smmu_domain, + rounddown(iova, PAGE_SIZE), + rounddown(iova, PAGE_SIZE), + roundup(size + iova - + rounddown(iova, PAGE_SIZE), + PAGE_SIZE), + IOMMU_READ | IOMMU_WRITE); + if (res) { + IPAERR("Fail to map 0x%llx\n", iova); + return -EINVAL; + } + } + } else { + if (sgt != NULL) { + va = rounddown(iova, PAGE_SIZE); + for_each_sg(sgt->sgl, sg, sgt->nents, i) + { + page = sg_page(sg); + phys = page_to_phys(page); + len = PAGE_ALIGN(sg->offset + sg->length); + res = iommu_unmap(smmu_domain, va, len); + if (res != len) { + IPAERR( + "Fail to unmap pa=%pa, va 0x%X, res %d\n" + , &phys, va, res); + ret = -EINVAL; + } + va += len; + count++; + } + } else { + res = iommu_unmap(smmu_domain, + rounddown(iova, PAGE_SIZE), + roundup( + size + iova - rounddown(iova, PAGE_SIZE), + PAGE_SIZE)); + if (res != roundup( + size + iova - rounddown(iova, PAGE_SIZE), + PAGE_SIZE)) { + IPAERR("Fail to unmap 0x%llx\n", iova); + return -EINVAL; + } + } + } + IPADBG("Peer buff %s 0x%llx\n", map ? "map" : "unmap", iova); + return ret; +} +EXPORT_SYMBOL(ipa3_smmu_map_peer_buff); + +static enum ipa_client_cb_type ipa_get_client_cb_type( + enum ipa_client_type client_type) +{ + enum ipa_client_cb_type client_cb; + + if (client_type == IPA_CLIENT_USB_PROD || + client_type == IPA_CLIENT_USB_CONS) { + IPADBG("USB Client registered\n"); + client_cb = IPA_USB_CLNT; + } else if (client_type == IPA_CLIENT_MHI_PROD || + client_type == IPA_CLIENT_MHI_CONS) { + IPADBG("MHI Client registered\n"); + client_cb = IPA_MHI_CLNT; + } else { + IPAERR("Invalid IPA client\n"); + client_cb = IPA_MAX_CLNT; + } + + return client_cb; +} +void ipa3_register_client_callback(int (*client_cb)(bool is_lock), + bool (*teth_port_state)(void), + enum ipa_client_type client_type) +{ + enum ipa_client_cb_type client; + + IPADBG("entry\n"); + + client = ipa_get_client_cb_type(client_type); + if (client == IPA_MAX_CLNT) + return; + + if (client_cb == NULL) { + IPAERR("Bad Param"); + return; + } + + if (!ipa3_ctx->client_lock_unlock[client]) + ipa3_ctx->client_lock_unlock[client] = client_cb; + if (!ipa3_ctx->get_teth_port_state[client]) + ipa3_ctx->get_teth_port_state[client] = teth_port_state; + IPADBG("exit\n"); +} +EXPORT_SYMBOL(ipa3_register_client_callback); + +void ipa3_deregister_client_callback(enum ipa_client_type client_type) +{ + enum ipa_client_cb_type client_cb; + + IPADBG("entry\n"); + + client_cb = ipa_get_client_cb_type(client_type); + if (client_cb == IPA_MAX_CLNT) + return; + + if (ipa3_ctx->client_lock_unlock[client_cb] == NULL && + ipa3_ctx->get_teth_port_state[client_cb] == NULL) { + IPAERR("client_lock_unlock is already NULL"); + return; + } + + ipa3_ctx->client_lock_unlock[client_cb] = NULL; + ipa3_ctx->get_teth_port_state[client_cb] = NULL; + IPADBG("exit\n"); +} +EXPORT_SYMBOL(ipa3_deregister_client_callback); + +static void client_lock_unlock_cb(enum ipa_client_type client, bool is_lock) +{ + enum ipa_client_cb_type client_cb; + + IPADBG("entry\n"); + + client_cb = ipa_get_client_cb_type(client); + if (client_cb == IPA_MAX_CLNT) + return; + + if (ipa3_ctx->client_lock_unlock[client_cb]) + ipa3_ctx->client_lock_unlock[client_cb](is_lock); + + IPADBG("exit\n"); +} + +int ipa3_request_gsi_channel(struct ipa_request_gsi_channel_params *params, + struct ipa_req_chan_out_params *out_params) +{ + int ipa_ep_idx; + int result = -EFAULT; + struct ipa3_ep_context *ep; + struct ipahal_reg_ep_cfg_status ep_status; + unsigned long gsi_dev_hdl; + enum gsi_status gsi_res; + const struct ipa_gsi_ep_config *gsi_ep_cfg_ptr; + + IPADBG("entry\n"); + if (params == NULL || out_params == NULL || + !ipa3_is_legal_params(params)) { + IPAERR("bad parameters\n"); + return -EINVAL; + } + + ipa_ep_idx = ipa_get_ep_mapping(params->client); + if (ipa_ep_idx == -1) { + IPAERR("fail to alloc EP.\n"); + goto fail; + } + + ep = &ipa3_ctx->ep[ipa_ep_idx]; + + if (ep->valid) { + IPAERR("EP already allocated.\n"); + goto fail; + } + + memset(&ipa3_ctx->ep[ipa_ep_idx], 0, sizeof(struct ipa3_ep_context)); + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + + ep->skip_ep_cfg = params->skip_ep_cfg; + ep->valid = 1; + ep->client = params->client; + ep->client_notify = params->notify; + ep->priv = params->priv; + ep->keep_ipa_awake = params->keep_ipa_awake; + + + /* Config QMB for USB_CONS ep */ + if (!IPA_CLIENT_IS_PROD(ep->client)) { + IPADBG("Configuring QMB on USB CONS pipe\n"); + if (ipa_ep_idx >= ipa3_ctx->ipa_num_pipes || + ipa3_ctx->ep[ipa_ep_idx].valid == 0) { + IPAERR("bad parm.\n"); + return -EINVAL; + } + result = ipa3_cfg_ep_cfg(ipa_ep_idx, ¶ms->ipa_ep_cfg.cfg); + if (result) { + IPAERR("fail to configure QMB.\n"); + return result; + } + } + + if (!ep->skip_ep_cfg) { + if (ipa3_cfg_ep(ipa_ep_idx, ¶ms->ipa_ep_cfg)) { + IPAERR("fail to configure EP.\n"); + goto ipa_cfg_ep_fail; + } + /* Setting EP status 0 */ + memset(&ep_status, 0, sizeof(ep_status)); + if (ipa3_cfg_ep_status(ipa_ep_idx, &ep_status)) { + IPAERR("fail to configure status of EP.\n"); + goto ipa_cfg_ep_fail; + } + IPADBG("ep configuration successful\n"); + } else { + IPADBG("Skipping endpoint configuration.\n"); + if (IPA_CLIENT_IS_PROD(ipa3_ctx->ep[ipa_ep_idx].client) && + ipa3_ctx->ep[ipa_ep_idx].client == IPA_CLIENT_USB_PROD + && !ipa3_is_mhip_offload_enabled()) { + if (ipa3_cfg_ep_seq(ipa_ep_idx, + ¶ms->ipa_ep_cfg.seq)) { + IPAERR("fail to configure USB pipe seq\n"); + goto ipa_cfg_ep_fail; + } + } + } + + out_params->clnt_hdl = ipa_ep_idx; + + result = ipa3_enable_data_path(out_params->clnt_hdl); + if (result) { + IPAERR("enable data path failed res=%d clnt=%d.\n", result, + out_params->clnt_hdl); + goto ipa_cfg_ep_fail; + } + + gsi_dev_hdl = ipa3_ctx->gsi_dev_hdl; + gsi_res = gsi_alloc_evt_ring(¶ms->evt_ring_params, gsi_dev_hdl, + &ep->gsi_evt_ring_hdl); + if (gsi_res != GSI_STATUS_SUCCESS) { + IPAERR("Error allocating event ring: %d\n", gsi_res); + result = -EFAULT; + goto ipa_cfg_ep_fail; + } + + gsi_res = gsi_write_evt_ring_scratch(ep->gsi_evt_ring_hdl, + params->evt_scratch); + if (gsi_res != GSI_STATUS_SUCCESS) { + IPAERR("Error writing event ring scratch: %d\n", gsi_res); + result = -EFAULT; + goto write_evt_scratch_fail; + } + + gsi_ep_cfg_ptr = ipa_get_gsi_ep_info(ep->client); + if (gsi_ep_cfg_ptr == NULL) { + IPAERR("Error ipa_get_gsi_ep_info ret NULL\n"); + result = -EFAULT; + goto write_evt_scratch_fail; + } + + params->chan_params.evt_ring_hdl = ep->gsi_evt_ring_hdl; + params->chan_params.ch_id = gsi_ep_cfg_ptr->ipa_gsi_chan_num; + params->chan_params.prefetch_mode = gsi_ep_cfg_ptr->prefetch_mode; + params->chan_params.empty_lvl_threshold = + gsi_ep_cfg_ptr->prefetch_threshold; + gsi_res = gsi_alloc_channel(¶ms->chan_params, gsi_dev_hdl, + &ep->gsi_chan_hdl); + if (gsi_res != GSI_STATUS_SUCCESS) { + IPAERR("Error allocating channel: %d, chan_id: %d\n", gsi_res, + params->chan_params.ch_id); + result = -EFAULT; + goto write_evt_scratch_fail; + } + + memcpy(&ep->chan_scratch, ¶ms->chan_scratch, + sizeof(union __packed gsi_channel_scratch)); + + /* + * Update scratch for MCS smart prefetch: + * Starting IPA4.5, smart prefetch implemented by H/W. + * At IPA 4.0/4.1/4.2, we do not use MCS smart prefetch + * so keep the fields zero. + */ + if (ipa3_ctx->ipa_hw_type < IPA_HW_v4_0) { + ep->chan_scratch.xdci.max_outstanding_tre = + params->chan_params.re_size * gsi_ep_cfg_ptr->ipa_if_tlv; + } + + gsi_res = gsi_write_channel_scratch(ep->gsi_chan_hdl, + params->chan_scratch); + if (gsi_res != GSI_STATUS_SUCCESS) { + IPAERR("Error writing channel scratch: %d\n", gsi_res); + result = -EFAULT; + goto write_chan_scratch_fail; + } + + gsi_res = gsi_query_channel_db_addr(ep->gsi_chan_hdl, + &out_params->db_reg_phs_addr_lsb, + &out_params->db_reg_phs_addr_msb); + if (gsi_res != GSI_STATUS_SUCCESS) { + IPAERR("Error querying channel DB registers addresses: %d\n", + gsi_res); + result = -EFAULT; + goto write_chan_scratch_fail; + } + + ep->gsi_mem_info.evt_ring_len = params->evt_ring_params.ring_len; + ep->gsi_mem_info.evt_ring_base_addr = + params->evt_ring_params.ring_base_addr; + ep->gsi_mem_info.evt_ring_base_vaddr = + params->evt_ring_params.ring_base_vaddr; + ep->gsi_mem_info.chan_ring_len = params->chan_params.ring_len; + ep->gsi_mem_info.chan_ring_base_addr = + params->chan_params.ring_base_addr; + ep->gsi_mem_info.chan_ring_base_vaddr = + params->chan_params.ring_base_vaddr; + + ipa3_ctx->skip_ep_cfg_shadow[ipa_ep_idx] = ep->skip_ep_cfg; + if (!ep->skip_ep_cfg && IPA_CLIENT_IS_PROD(params->client)) + ipa3_install_dflt_flt_rules(ipa_ep_idx); + + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + + IPADBG("client %d (ep: %d) connected\n", params->client, ipa_ep_idx); + IPADBG("exit\n"); + + return 0; + +write_chan_scratch_fail: + gsi_dealloc_channel(ep->gsi_chan_hdl); +write_evt_scratch_fail: + gsi_dealloc_evt_ring(ep->gsi_evt_ring_hdl); +ipa_cfg_ep_fail: + memset(&ipa3_ctx->ep[ipa_ep_idx], 0, sizeof(struct ipa3_ep_context)); + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); +fail: + return result; +} +EXPORT_SYMBOL(ipa3_request_gsi_channel); + +int ipa3_set_usb_max_packet_size( + enum ipa_usb_max_usb_packet_size usb_max_packet_size) +{ + struct gsi_device_scratch dev_scratch; + enum gsi_status gsi_res; + + IPADBG("entry\n"); + + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + + memset(&dev_scratch, 0, sizeof(struct gsi_device_scratch)); + dev_scratch.mhi_base_chan_idx_valid = false; + dev_scratch.max_usb_pkt_size_valid = true; + dev_scratch.max_usb_pkt_size = usb_max_packet_size; + + gsi_res = gsi_write_device_scratch(ipa3_ctx->gsi_dev_hdl, + &dev_scratch); + if (gsi_res != GSI_STATUS_SUCCESS) { + IPAERR("Error writing device scratch: %d\n", gsi_res); + return -EFAULT; + } + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + + IPADBG("exit\n"); + return 0; +} +EXPORT_SYMBOL(ipa3_set_usb_max_packet_size); + +/** + * ipa3_get_usb_gsi_stats() - Query USB gsi stats from uc + * @stats: [inout] stats blob from client populated by driver + * + * Returns: 0 on success, negative on failure + * + * @note Cannot be called from atomic context + * + */ +int ipa3_get_usb_gsi_stats(struct ipa_uc_dbg_ring_stats *stats) +{ + int i; + + if (!ipa3_ctx->usb_ctx.dbg_stats.uc_dbg_stats_mmio) + return -EINVAL; + + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + for (i = 0; i < MAX_USB_CHANNELS; i++) { + stats->u.ring[i].ringFull = ioread32( + ipa3_ctx->usb_ctx.dbg_stats.uc_dbg_stats_mmio + + i * IPA3_UC_DEBUG_STATS_OFF + + IPA3_UC_DEBUG_STATS_RINGFULL_OFF); + stats->u.ring[i].ringEmpty = ioread32( + ipa3_ctx->usb_ctx.dbg_stats.uc_dbg_stats_mmio + + i * IPA3_UC_DEBUG_STATS_OFF + + IPA3_UC_DEBUG_STATS_RINGEMPTY_OFF); + stats->u.ring[i].ringUsageHigh = ioread32( + ipa3_ctx->usb_ctx.dbg_stats.uc_dbg_stats_mmio + + i * IPA3_UC_DEBUG_STATS_OFF + + IPA3_UC_DEBUG_STATS_RINGUSAGEHIGH_OFF); + stats->u.ring[i].ringUsageLow = ioread32( + ipa3_ctx->usb_ctx.dbg_stats.uc_dbg_stats_mmio + + i * IPA3_UC_DEBUG_STATS_OFF + + IPA3_UC_DEBUG_STATS_RINGUSAGELOW_OFF); + stats->u.ring[i].RingUtilCount = ioread32( + ipa3_ctx->usb_ctx.dbg_stats.uc_dbg_stats_mmio + + i * IPA3_UC_DEBUG_STATS_OFF + + IPA3_UC_DEBUG_STATS_RINGUTILCOUNT_OFF); + } + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + + + return 0; +} + +/* This function called as part of usb pipe resume */ +int ipa3_xdci_connect(u32 clnt_hdl) +{ + int result; + struct ipa3_ep_context *ep; + + IPADBG("entry\n"); + + if (clnt_hdl >= ipa3_ctx->ipa_num_pipes || + ipa3_ctx->ep[clnt_hdl].valid == 0) { + IPAERR("Bad parameter.\n"); + return -EINVAL; + } + + ep = &ipa3_ctx->ep[clnt_hdl]; + IPA_ACTIVE_CLIENTS_INC_EP(ipa3_get_client_mapping(clnt_hdl)); + + result = ipa3_start_gsi_channel(clnt_hdl); + if (result) { + IPAERR("failed to start gsi channel clnt_hdl=%u\n", clnt_hdl); + goto exit; + } + + result = ipa3_enable_data_path(clnt_hdl); + if (result) { + IPAERR("enable data path failed res=%d clnt_hdl=%d.\n", result, + clnt_hdl); + goto stop_ch; + } + + IPADBG("exit\n"); + goto exit; + +stop_ch: + (void)ipa_stop_gsi_channel(clnt_hdl); +exit: + IPA_ACTIVE_CLIENTS_DEC_EP(ipa3_get_client_mapping(clnt_hdl)); + return result; +} +EXPORT_SYMBOL(ipa3_xdci_connect); + +/* This function called as part of usb pipe connect */ +int ipa3_xdci_start(u32 clnt_hdl, u8 xferrscidx, bool xferrscidx_valid) +{ + struct ipa3_ep_context *ep; + int result = -EFAULT; + enum gsi_status gsi_res; + struct ipa_ep_cfg_ctrl ep_cfg_ctrl; + u32 holb_max_cnt = ipa3_ctx->uc_ctx.holb_monitor.max_cnt_usb; + int code = 0; + + IPADBG("entry\n"); + if (clnt_hdl >= ipa3_ctx->ipa_num_pipes || + ipa3_ctx->ep[clnt_hdl].valid == 0 || + xferrscidx > IPA_XFER_RSC_IDX_MAX) { + IPAERR("Bad parameters.\n"); + return -EINVAL; + } + + ep = &ipa3_ctx->ep[clnt_hdl]; + IPA_ACTIVE_CLIENTS_INC_EP(ipa3_get_client_mapping(clnt_hdl)); + + if (xferrscidx_valid) { + ep->chan_scratch.xdci.xferrscidx = xferrscidx; + gsi_res = gsi_write_channel_scratch(ep->gsi_chan_hdl, + ep->chan_scratch); + if (gsi_res != GSI_STATUS_SUCCESS) { + IPAERR("Error writing channel scratch: %d\n", gsi_res); + goto write_chan_scratch_fail; + } + } + + if (IPA_CLIENT_IS_PROD(ep->client) && ep->skip_ep_cfg) { + memset(&ep_cfg_ctrl, 0, sizeof(struct ipa_ep_cfg_ctrl)); + ep_cfg_ctrl.ipa_ep_delay = true; + ep->ep_delay_set = true; + + result = ipa_cfg_ep_ctrl(clnt_hdl, &ep_cfg_ctrl); + if (result) + IPAERR("client (ep: %d) failed result=%d\n", + clnt_hdl, result); + else + IPADBG("client (ep: %d) success\n", clnt_hdl); + } else { + ep->ep_delay_set = false; + } + + gsi_res = gsi_start_channel(ep->gsi_chan_hdl); + if (gsi_res != GSI_STATUS_SUCCESS) { + IPAERR("Error starting channel: %d\n", gsi_res); + goto write_chan_scratch_fail; + } + + if (IPA_CLIENT_IS_HOLB_CONS(ep->client)) { + result = ipa3_uc_client_add_holb_monitor(ep->gsi_chan_hdl, + HOLB_MONITOR_MASK, + holb_max_cnt, IPA_EE_AP); + if (result) + IPAERR("Add HOLB monitor failed for gsi ch %d\n", + ep->gsi_chan_hdl); + } + + if (IPA_CLIENT_IS_PROD(ep->client) && ep->skip_ep_cfg && + ipa3_ctx->ipa_endp_delay_wa && + !ipa3_is_mhip_offload_enabled()) { + gsi_res = gsi_enable_flow_control_ee(ep->gsi_chan_hdl, 0, + &code); + if (gsi_res == GSI_STATUS_SUCCESS) { + IPADBG("flow control sussess gsi ch %d with code %d\n", + ep->gsi_chan_hdl, code); + } else { + IPADBG("failed to flow control gsi ch %d code %d\n", + ep->gsi_chan_hdl, code); + } + } + ipa3_start_gsi_debug_monitor(clnt_hdl); + if (!ep->keep_ipa_awake) + IPA_ACTIVE_CLIENTS_DEC_EP(ipa3_get_client_mapping(clnt_hdl)); + + IPADBG("exit\n"); + return 0; + +write_chan_scratch_fail: + IPA_ACTIVE_CLIENTS_DEC_EP(ipa3_get_client_mapping(clnt_hdl)); + return result; +} +EXPORT_SYMBOL(ipa3_xdci_start); + +int ipa3_get_gsi_chan_info(struct gsi_chan_info *gsi_chan_info, + unsigned long chan_hdl) +{ + enum gsi_status gsi_res; + + memset(gsi_chan_info, 0, sizeof(struct gsi_chan_info)); + gsi_res = gsi_query_channel_info(chan_hdl, gsi_chan_info); + if (gsi_res != GSI_STATUS_SUCCESS) { + IPAERR("Error querying channel info: %d\n", gsi_res); + return -EFAULT; + } + if (!gsi_chan_info->evt_valid) { + IPAERR("Event info invalid\n"); + return -EFAULT; + } + + return 0; +} + +static bool ipa3_is_xdci_channel_with_given_info_empty( + struct ipa3_ep_context *ep, struct gsi_chan_info *chan_info) +{ + bool is_empty = false; + + if (!IPA_CLIENT_IS_CONS(ep->client)) { + /* For UL channel: chan.RP == chan.WP */ + is_empty = (chan_info->rp == chan_info->wp); + } else { + /* For DL channel: */ + if (chan_info->wp != + (ep->gsi_mem_info.chan_ring_base_addr + + ep->gsi_mem_info.chan_ring_len - + GSI_CHAN_RE_SIZE_16B)) { + /* if chan.WP != LINK TRB: chan.WP == evt.RP */ + is_empty = (chan_info->wp == chan_info->evt_rp); + } else { + /* + * if chan.WP == LINK TRB: chan.base_xfer_ring_addr + * == evt.RP + */ + is_empty = (ep->gsi_mem_info.chan_ring_base_addr == + chan_info->evt_rp); + } + } + + return is_empty; +} + +static int ipa3_is_xdci_channel_empty(struct ipa3_ep_context *ep, + bool *is_empty) +{ + struct gsi_chan_info chan_info; + int res; + + if (!ep || !is_empty || !ep->valid) { + IPAERR("Input Error\n"); + return -EFAULT; + } + + res = ipa3_get_gsi_chan_info(&chan_info, ep->gsi_chan_hdl); + if (res) { + IPAERR("Failed to get GSI channel info\n"); + return -EFAULT; + } + + *is_empty = ipa3_is_xdci_channel_with_given_info_empty(ep, &chan_info); + + return 0; +} + +int ipa3_enable_force_clear(u32 request_id, bool throttle_source, + u32 source_pipe_bitmask, u32 source_pipe_reg_idx) +{ + struct ipa_enable_force_clear_datapath_req_msg_v01 req; + int result; + + if (ipa3_ctx->platform_type == IPA_PLAT_TYPE_APQ) { + IPADBG("APQ platform - ignore force clear\n"); + return 0; + } + + memset(&req, 0, sizeof(req)); + req.request_id = request_id; + if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0) { + WARN_ON(source_pipe_reg_idx); + req.source_pipe_bitmask = source_pipe_bitmask; + } else { + req.source_pipe_bitmask_ext_valid = 1; + req.source_pipe_bitmask_ext[source_pipe_reg_idx] = + source_pipe_bitmask; + } + if (throttle_source) { + req.throttle_source_valid = 1; + req.throttle_source = 1; + } + result = ipa3_qmi_enable_force_clear_datapath_send(&req); + if (result) { + IPAERR("ipa3_qmi_enable_force_clear_datapath_send failed %d\n", + result); + return result; + } + + return 0; +} + +int ipa3_disable_force_clear(u32 request_id) +{ + struct ipa_disable_force_clear_datapath_req_msg_v01 req; + int result; + + if (ipa3_ctx->platform_type == IPA_PLAT_TYPE_APQ) { + IPADBG("APQ platform - ignore force clear\n"); + return 0; + } + + memset(&req, 0, sizeof(req)); + req.request_id = request_id; + result = ipa3_qmi_disable_force_clear_datapath_send(&req); + if (result) { + IPAERR("ipa3_qmi_disable_force_clear_datapath_send failed %d\n", + result); + return result; + } + + return 0; +} + +/* Clocks should be voted before invoking this function */ +static int ipa3_xdci_stop_gsi_channel(u32 clnt_hdl, bool *stop_in_proc) +{ + int res; + + IPADBG("entry\n"); + if (clnt_hdl >= ipa3_ctx->ipa_num_pipes || + ipa3_ctx->ep[clnt_hdl].valid == 0 || + !stop_in_proc) { + IPAERR("Bad parameter.\n"); + return -EINVAL; + } + + res = ipa_stop_gsi_channel(clnt_hdl); + if (res != 0 && res != -GSI_STATUS_AGAIN && + res != -GSI_STATUS_TIMED_OUT) { + IPAERR("xDCI stop channel failed res=%d\n", res); + return -EFAULT; + } + + if (res) + *stop_in_proc = true; + else + *stop_in_proc = false; + + IPADBG("xDCI channel is %s (result=%d)\n", + res ? "STOP_IN_PROC/TimeOut" : "STOP", res); + + IPADBG("exit\n"); + return 0; +} + +/* Clocks should be voted before invoking this function */ +static int ipa3_xdci_stop_gsi_ch_brute_force(u32 clnt_hdl, + bool *stop_in_proc) +{ + unsigned long jiffies_start; + unsigned long jiffies_timeout = + msecs_to_jiffies(IPA_CHANNEL_STOP_IN_PROC_TO_MSEC); + int res; + + IPADBG("entry\n"); + if (clnt_hdl >= ipa3_ctx->ipa_num_pipes || + ipa3_ctx->ep[clnt_hdl].valid == 0 || + !stop_in_proc) { + IPAERR("Bad parameter.\n"); + return -EINVAL; + } + + jiffies_start = jiffies; + while (1) { + res = ipa3_xdci_stop_gsi_channel(clnt_hdl, + stop_in_proc); + if (res) { + IPAERR("failed to stop xDCI channel hdl=%d\n", + clnt_hdl); + return res; + } + + if (!*stop_in_proc) { + IPADBG("xDCI channel STOP hdl=%d\n", clnt_hdl); + return res; + } + + /* + * Give chance to the previous stop request to be accomplished + * before the retry + */ + udelay(IPA_CHANNEL_STOP_IN_PROC_SLEEP_USEC); + + if (time_after(jiffies, jiffies_start + jiffies_timeout)) { + IPADBG("timeout waiting for xDCI channel emptiness\n"); + return res; + } + } +} + +int ipa3_remove_secondary_flow_ctrl(int gsi_chan_hdl) +{ + int code = 0; + int result; + + result = gsi_query_flow_control_state_ee(gsi_chan_hdl, 0, 1, &code); + if (result == GSI_STATUS_SUCCESS) { + code = 0; + result = gsi_flow_control_ee(gsi_chan_hdl, + ipa_get_ep_mapping_from_gsi(gsi_chan_hdl), 0, false, true, &code); + if (result == GSI_STATUS_SUCCESS) { + IPADBG("flow control sussess ch %d code %d\n", + gsi_chan_hdl, code); + } else { + IPADBG("failed to flow control ch %d code %d\n", + gsi_chan_hdl, code); + } + } else { + IPADBG("failed to query flow control mode ch %d code %d\n", + gsi_chan_hdl, code); + } + return result; +} +/* Clocks should be voted for before invoking this function */ +static int ipa3_stop_ul_chan_with_data_drain(u32 qmi_req_id, + u32 source_pipe_bitmask, u32 source_pipe_reg_idx, + bool should_force_clear, u32 clnt_hdl, bool remove_delay) +{ + int result; + bool is_empty = false; + int i; + bool stop_in_proc; + struct ipa3_ep_context *ep; + struct ipa_ep_cfg_ctrl ep_cfg_ctrl; + + IPADBG("entry\n"); + + if (clnt_hdl >= ipa3_ctx->ipa_num_pipes || + ipa3_ctx->ep[clnt_hdl].valid == 0) { + IPAERR("Bad parameter.\n"); + return -EINVAL; + } + + ep = &ipa3_ctx->ep[clnt_hdl]; + + /* first try to stop the channel */ + result = ipa3_xdci_stop_gsi_ch_brute_force(clnt_hdl, + &stop_in_proc); + if (result) { + IPAERR("fail to stop UL channel - hdl=%d clnt=%d\n", + clnt_hdl, ep->client); + goto exit; + } + if (!stop_in_proc) + goto exit; + + /* Remove delay only if stop channel success*/ + if (remove_delay && ep->ep_delay_set == true && !stop_in_proc) { + memset(&ep_cfg_ctrl, 0, sizeof(struct ipa_ep_cfg_ctrl)); + ep_cfg_ctrl.ipa_ep_delay = false; + result = ipa_cfg_ep_ctrl(clnt_hdl, + &ep_cfg_ctrl); + if (result) { + IPAERR + ("client (ep: %d) failed to remove delay result=%d\n", + clnt_hdl, result); + } else { + IPADBG("client (ep: %d) delay removed\n", + clnt_hdl); + ep->ep_delay_set = false; + } + } + + /* if stop_in_proc, lets wait for emptiness */ + for (i = 0; i < IPA_POLL_FOR_EMPTINESS_NUM; i++) { + result = ipa3_is_xdci_channel_empty(ep, &is_empty); + if (result) + goto exit; + if (is_empty) + break; + udelay(IPA_POLL_FOR_EMPTINESS_SLEEP_USEC); + } + /* In case of empty, lets try to stop the channel again */ + if (is_empty) { + result = ipa3_xdci_stop_gsi_ch_brute_force(clnt_hdl, + &stop_in_proc); + if (result) { + IPAERR("fail to stop UL channel - hdl=%d clnt=%d\n", + clnt_hdl, ep->client); + goto exit; + } + if (!stop_in_proc) + goto exit; + } + /* if still stop_in_proc or not empty, activate force clear */ + if (should_force_clear && IPA_CLIENT_IS_PROD(ep->client)) { + result = ipa3_enable_force_clear(qmi_req_id, false, + source_pipe_bitmask, source_pipe_reg_idx); + if (result) { + struct ipahal_ep_cfg_ctrl_scnd ep_ctrl_scnd = { 0 }; + + /* + * assuming here modem SSR\shutdown, AP can remove + * the delay in this case + */ + IPAERR( + "failed to force clear %d, remove delay from SCND reg\n" + , result); + if (ipa3_ctx->ipa_endp_delay_wa_v2) { + ipa3_remove_secondary_flow_ctrl( + ep->gsi_chan_hdl); + } else { + ep_ctrl_scnd.endp_delay = false; + ipahal_write_reg_n_fields( + IPA_ENDP_INIT_CTRL_SCND_n, clnt_hdl, + &ep_ctrl_scnd); + } + } + } + /* with force clear, wait for emptiness */ + for (i = 0; i < IPA_POLL_FOR_EMPTINESS_NUM; i++) { + result = ipa3_is_xdci_channel_empty(ep, &is_empty); + if (result) + goto disable_force_clear_and_exit; + if (is_empty) + break; + + udelay(IPA_POLL_FOR_EMPTINESS_SLEEP_USEC); + } + /* try to stop for the last time */ + result = ipa3_xdci_stop_gsi_ch_brute_force(clnt_hdl, + &stop_in_proc); + if (result) { + IPAERR("fail to stop UL channel - hdl=%d clnt=%d\n", + clnt_hdl, ep->client); + ipa_assert(); + goto disable_force_clear_and_exit; + } + result = stop_in_proc ? -EFAULT : 0; + +disable_force_clear_and_exit: + if (should_force_clear) + ipa3_disable_force_clear(qmi_req_id); +exit: + if (remove_delay && ep->ep_delay_set == true && !stop_in_proc) { + memset(&ep_cfg_ctrl, 0, sizeof(struct ipa_ep_cfg_ctrl)); + ep_cfg_ctrl.ipa_ep_delay = false; + result = ipa_cfg_ep_ctrl(clnt_hdl, + &ep_cfg_ctrl); + if (result) { + IPAERR + ("client (ep: %d) failed to remove delay result=%d\n", + clnt_hdl, result); + } else { + IPADBG("client (ep: %d) delay removed\n", + clnt_hdl); + ep->ep_delay_set = false; + } + } + IPADBG("exit\n"); + return result; +} + +/* + * Set reset ep_delay for CLIENT PROD pipe + * Clocks, should be voted before calling this API + * locks should be taken before calling this API + */ + +int ipa3_set_reset_client_prod_pipe_delay(bool set_reset, + enum ipa_client_type client) +{ + int result = 0; + int pipe_idx; + struct ipa3_ep_context *ep; + struct ipa_ep_cfg_ctrl ep_ctrl; + + memset(&ep_ctrl, 0, sizeof(struct ipa_ep_cfg_ctrl)); + ep_ctrl.ipa_ep_delay = set_reset; + + if (IPA_CLIENT_IS_CONS(client)) { + IPAERR("client (%d) not PROD\n", client); + return -EINVAL; + } + + pipe_idx = ipa_get_ep_mapping(client); + + if (pipe_idx == IPA_EP_NOT_ALLOCATED) { + IPAERR("client (%d) not valid\n", client); + return -EINVAL; + } + + ep = &ipa3_ctx->ep[pipe_idx]; + + /* Setting delay on USB_PROD with skip_ep_cfg */ + client_lock_unlock_cb(client, true); + if (ep->valid && ep->skip_ep_cfg) { + ep->ep_delay_set = ep_ctrl.ipa_ep_delay; + result = ipa_cfg_ep_ctrl(pipe_idx, &ep_ctrl); + if (result) + IPAERR("client (ep: %d) failed result=%d\n", + pipe_idx, result); + else + IPADBG("client (ep: %d) success\n", pipe_idx); + } + client_lock_unlock_cb(client, false); + return result; +} + +static bool ipa3_get_teth_port_status(enum ipa_client_type client) +{ + enum ipa_client_cb_type client_cb; + + client_cb = ipa_get_client_cb_type(client); + if (client_cb == IPA_MAX_CLNT) + return false; + if (ipa3_ctx->get_teth_port_state[client_cb]) + return ipa3_ctx->get_teth_port_state[client_cb](); + return false; +} + +/* + * Start/stop the CLIENT PROD pipes in SSR scenarios + */ + +int ipa3_start_stop_client_prod_gsi_chnl(enum ipa_client_type client, + bool start_chnl) +{ + int result = 0; + int pipe_idx; + struct ipa3_ep_context *ep; + int code = 0; + + if (IPA_CLIENT_IS_CONS(client)) { + IPAERR("client (%d) not PROD\n", client); + return -EINVAL; + } + + pipe_idx = ipa_get_ep_mapping(client); + + if (pipe_idx == IPA_EP_NOT_ALLOCATED) { + IPAERR("client (%d) not valid\n", client); + return -EINVAL; + } + + client_lock_unlock_cb(client, true); + ep = &ipa3_ctx->ep[pipe_idx]; + if (ep->valid && ep->skip_ep_cfg && ipa3_get_teth_port_status(client) + && !ipa3_is_mhip_offload_enabled()) { + if (start_chnl) { + result = ipa3_start_gsi_channel(pipe_idx); + result = gsi_enable_flow_control_ee(ep->gsi_chan_hdl, + 0, &code); + if (result == GSI_STATUS_SUCCESS) { + IPADBG("flow control sussess ch %d code %d\n", + ep->gsi_chan_hdl, code); + } else { + IPADBG("failed to flow control ch %d code %d\n", + ep->gsi_chan_hdl, code); + } + } else + result = ipa_stop_gsi_channel(pipe_idx); + } + client_lock_unlock_cb(client, false); + return result; +} +int ipa3_set_reset_client_cons_pipe_sus_holb(bool set_reset, + enum ipa_client_type client) +{ + int pipe_idx; + struct ipa3_ep_context *ep; + struct ipa_ep_cfg_ctrl ep_suspend; + struct ipa_ep_cfg_holb ep_holb; + + memset(&ep_suspend, 0, sizeof(ep_suspend)); + memset(&ep_holb, 0, sizeof(ep_holb)); + + ep_suspend.ipa_ep_suspend = set_reset; + ep_holb.tmr_val = 0; + ep_holb.en = set_reset; + + if (IPA_CLIENT_IS_PROD(client)) { + IPAERR("client (%d) not CONS\n", client); + return -EINVAL; + } + + pipe_idx = ipa_get_ep_mapping(client); + + if (pipe_idx == IPA_EP_NOT_ALLOCATED) { + IPAERR("client (%d) not valid\n", client); + return -EINVAL; + } + + ep = &ipa3_ctx->ep[pipe_idx]; + /* Setting sus/holb on MHI_CONS with skip_ep_cfg */ + client_lock_unlock_cb(client, true); + if (ep->valid && ep->skip_ep_cfg) { + if (ipa3_ctx->ipa_hw_type < IPA_HW_v4_0) + ipahal_write_reg_n_fields( + IPA_ENDP_INIT_CTRL_n, + pipe_idx, &ep_suspend); + /* + * ipa3_cfg_ep_holb is not used here because we are + * setting HOLB on Q6 pipes, and from APPS perspective + * they are not valid, therefore, the above function + * will fail. + */ + ipahal_write_reg_n_fields( + IPA_ENDP_INIT_HOL_BLOCK_TIMER_n, + pipe_idx, &ep_holb); + ipahal_write_reg_n_fields( + IPA_ENDP_INIT_HOL_BLOCK_EN_n, + pipe_idx, &ep_holb); + + /* For targets > IPA_4.0 issue requires HOLB_EN to be + * written twice. + */ + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_0) + ipahal_write_reg_n_fields( + IPA_ENDP_INIT_HOL_BLOCK_EN_n, + pipe_idx, &ep_holb); + } + client_lock_unlock_cb(client, false); + return 0; +} + +void ipa3_xdci_ep_delay_rm(u32 clnt_hdl) +{ + struct ipa3_ep_context *ep; + struct ipa_ep_cfg_ctrl ep_cfg_ctrl; + int result; + + if (clnt_hdl >= ipa3_ctx->ipa_num_pipes || + ipa3_ctx->ep[clnt_hdl].valid == 0) { + IPAERR("bad parm.\n"); + return; + } + + ep = &ipa3_ctx->ep[clnt_hdl]; + + if (ep->ep_delay_set) { + + memset(&ep_cfg_ctrl, 0, sizeof(struct ipa_ep_cfg_ctrl)); + ep_cfg_ctrl.ipa_ep_delay = false; + + if (!ep->keep_ipa_awake) + IPA_ACTIVE_CLIENTS_INC_EP + (ipa3_get_client_mapping(clnt_hdl)); + + result = ipa_cfg_ep_ctrl(clnt_hdl, + &ep_cfg_ctrl); + + if (!ep->keep_ipa_awake) + IPA_ACTIVE_CLIENTS_DEC_EP + (ipa3_get_client_mapping(clnt_hdl)); + + if (result) { + IPAERR + ("client (ep: %d) failed to remove delay result=%d\n", + clnt_hdl, result); + } else { + IPADBG("client (ep: %d) delay removed\n", + clnt_hdl); + ep->ep_delay_set = false; + } + } +} +EXPORT_SYMBOL(ipa3_xdci_ep_delay_rm); + +int ipa3_xdci_disconnect(u32 clnt_hdl, bool should_force_clear, u32 qmi_req_id) +{ + struct ipa3_ep_context *ep; + struct ipa_ep_cfg_ctrl ep_cfg_ctrl; + int result; + u32 source_pipe_bitmask = 0; + u32 source_pipe_reg_idx = 0; + + IPADBG("entry\n"); + if (clnt_hdl >= ipa3_ctx->ipa_num_pipes || + ipa3_ctx->ep[clnt_hdl].valid == 0) { + IPAERR("Bad parameter.\n"); + return -EINVAL; + } + + ep = &ipa3_ctx->ep[clnt_hdl]; + + if (!ep->keep_ipa_awake) + IPA_ACTIVE_CLIENTS_INC_EP(ipa3_get_client_mapping(clnt_hdl)); + + ipa3_disable_data_path(clnt_hdl); + + if (!IPA_CLIENT_IS_CONS(ep->client)) { + IPADBG("Stopping PROD channel - hdl=%d clnt=%d\n", + clnt_hdl, ep->client); + source_pipe_bitmask = ipahal_get_ep_bit(clnt_hdl); + source_pipe_reg_idx = ipahal_get_ep_reg_idx(clnt_hdl); + result = ipa3_stop_ul_chan_with_data_drain(qmi_req_id, + source_pipe_bitmask, source_pipe_reg_idx, + should_force_clear, clnt_hdl, true); + if (result) { + IPAERR("Fail to stop UL channel with data drain\n"); + WARN_ON(1); + goto stop_chan_fail; + } + } else { + IPADBG("Stopping CONS channel - hdl=%d clnt=%d\n", + clnt_hdl, ep->client); + result = ipa_stop_gsi_channel(clnt_hdl); + if (result) { + IPAERR("Error stopping channel (CONS client): %d\n", + result); + goto stop_chan_fail; + } + if (ipa3_ctx->ipa_hw_type < IPA_HW_v4_0) { + /* Unsuspend the pipe */ + memset(&ep_cfg_ctrl, 0, sizeof(struct ipa_ep_cfg_ctrl)); + ep_cfg_ctrl.ipa_ep_suspend = false; + ipa_cfg_ep_ctrl(clnt_hdl, &ep_cfg_ctrl); + } + } + IPA_ACTIVE_CLIENTS_DEC_EP(ipa3_get_client_mapping(clnt_hdl)); + + IPADBG("exit\n"); + return 0; + +stop_chan_fail: + if (!ep->keep_ipa_awake) + IPA_ACTIVE_CLIENTS_DEC_EP(ipa3_get_client_mapping(clnt_hdl)); + return result; +} +EXPORT_SYMBOL(ipa3_xdci_disconnect); + +int ipa3_release_gsi_channel(u32 clnt_hdl) +{ + struct ipa3_ep_context *ep; + int result = -EFAULT; + enum gsi_status gsi_res; + + IPADBG("entry\n"); + if (clnt_hdl >= ipa3_ctx->ipa_num_pipes || + ipa3_ctx->ep[clnt_hdl].valid == 0) { + IPAERR("Bad parameter.\n"); + return -EINVAL; + } + + ep = &ipa3_ctx->ep[clnt_hdl]; + + if (!ep->keep_ipa_awake) + IPA_ACTIVE_CLIENTS_INC_EP(ipa3_get_client_mapping(clnt_hdl)); + + /* Set the disconnect in progress flag to avoid calling cb.*/ + spin_lock(&ipa3_ctx->disconnect_lock); + atomic_set(&ep->disconnect_in_progress, 1); + spin_unlock(&ipa3_ctx->disconnect_lock); + + + gsi_res = gsi_dealloc_channel(ep->gsi_chan_hdl); + if (gsi_res != GSI_STATUS_SUCCESS) { + IPAERR("Error deallocating channel: %d\n", gsi_res); + goto dealloc_chan_fail; + } + + gsi_res = gsi_dealloc_evt_ring(ep->gsi_evt_ring_hdl); + if (gsi_res != GSI_STATUS_SUCCESS) { + IPAERR("Error deallocating event: %d\n", gsi_res); + goto dealloc_chan_fail; + } + + if (!ep->skip_ep_cfg && IPA_CLIENT_IS_PROD(ep->client)) + ipa3_delete_dflt_flt_rules(clnt_hdl); + + if (!ep->keep_ipa_awake) + IPA_ACTIVE_CLIENTS_DEC_EP(ipa3_get_client_mapping(clnt_hdl)); + + spin_lock(&ipa3_ctx->disconnect_lock); + memset(&ipa3_ctx->ep[clnt_hdl], 0, sizeof(struct ipa3_ep_context)); + spin_unlock(&ipa3_ctx->disconnect_lock); + + IPADBG("exit\n"); + return 0; + +dealloc_chan_fail: + if (!ep->keep_ipa_awake) + IPA_ACTIVE_CLIENTS_DEC_EP(ipa3_get_client_mapping(clnt_hdl)); + return result; +} +EXPORT_SYMBOL(ipa3_release_gsi_channel); + +int ipa3_xdci_suspend(u32 ul_clnt_hdl, u32 dl_clnt_hdl, + bool should_force_clear, u32 qmi_req_id, bool is_dpl) +{ + struct ipa3_ep_context *ul_ep = NULL; + struct ipa3_ep_context *dl_ep; + int result = -EFAULT; + u32 source_pipe_bitmask = 0; + u32 source_pipe_reg_idx = 0; + bool dl_data_pending = true; + bool ul_data_pending = true; + int i; + bool is_empty = false; + struct gsi_chan_info ul_gsi_chan_info, dl_gsi_chan_info; + int aggr_active_bitmap = 0; + struct ipa_ep_cfg_ctrl ep_cfg_ctrl; + u32 holb_max_cnt = ipa3_ctx->uc_ctx.holb_monitor.max_cnt_usb; + int res = 0; + struct ipa_ep_cfg_holb holb_cfg; + + /* In case of DPL, dl is the DPL channel/client */ + + IPADBG("entry\n"); + if (dl_clnt_hdl >= ipa3_ctx->ipa_num_pipes || + ipa3_ctx->ep[dl_clnt_hdl].valid == 0 || + (!is_dpl && (ul_clnt_hdl >= ipa3_ctx->ipa_num_pipes || + ipa3_ctx->ep[ul_clnt_hdl].valid == 0))) { + IPAERR("Bad parameter.\n"); + return -EINVAL; + } + + dl_ep = &ipa3_ctx->ep[dl_clnt_hdl]; + if (!is_dpl) + ul_ep = &ipa3_ctx->ep[ul_clnt_hdl]; + IPA_ACTIVE_CLIENTS_INC_EP(ipa3_get_client_mapping(dl_clnt_hdl)); + + result = ipa3_get_gsi_chan_info(&dl_gsi_chan_info, + dl_ep->gsi_chan_hdl); + if (result) + goto disable_clk_and_exit; + + if (!is_dpl) { + result = ipa3_get_gsi_chan_info(&ul_gsi_chan_info, + ul_ep->gsi_chan_hdl); + if (result) + goto disable_clk_and_exit; + } + + for (i = 0; i < IPA_POLL_FOR_EMPTINESS_NUM; i++) { + if (!dl_data_pending && !ul_data_pending) + break; + result = ipa3_is_xdci_channel_empty(dl_ep, &is_empty); + if (result) + goto disable_clk_and_exit; + if (!is_empty) { + dl_data_pending = true; + break; + } + dl_data_pending = false; + if (!is_dpl) { + result = ipa3_is_xdci_channel_empty(ul_ep, &is_empty); + if (result) + goto disable_clk_and_exit; + ul_data_pending = !is_empty; + } else { + ul_data_pending = false; + } + + udelay(IPA_POLL_FOR_EMPTINESS_SLEEP_USEC); + } + + if (!dl_data_pending) { + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0) { + aggr_active_bitmap = + ipahal_read_ep_reg(IPA_STATE_AGGR_ACTIVE_n, + dl_clnt_hdl); + } else { + aggr_active_bitmap = + ipahal_read_reg(IPA_STATE_AGGR_ACTIVE); + } + if (ipahal_test_ep_bit(aggr_active_bitmap, dl_clnt_hdl)) { + IPADBG( + "DL/DPL data pending due to open aggr. frame\n" + ); + dl_data_pending = true; + } + } + if (dl_data_pending) { + IPAERR("DL/DPL data pending, can't suspend\n"); + result = -EFAULT; + goto disable_clk_and_exit; + } + + if (ipa3_ctx->ipa_hw_type < IPA_HW_v4_0) { + /* Suspend the DL/DPL EP */ + memset(&ep_cfg_ctrl, 0, sizeof(struct ipa_ep_cfg_ctrl)); + ep_cfg_ctrl.ipa_ep_suspend = true; + ipa_cfg_ep_ctrl(dl_clnt_hdl, &ep_cfg_ctrl); + } + + /* + * Check if DL/DPL channel is empty again, data could enter the channel + * before its IPA EP was suspended + */ + result = ipa3_is_xdci_channel_empty(dl_ep, &is_empty); + if (result) + goto unsuspend_dl_and_exit; + if (!is_empty) { + IPAERR("DL/DPL data pending, can't suspend\n"); + result = -EFAULT; + goto unsuspend_dl_and_exit; + } + + /*enable holb to discard the packets*/ + if (IPA_CLIENT_IS_CONS(dl_ep->client) && !is_dpl) { + memset(&holb_cfg, 0, sizeof(holb_cfg)); + holb_cfg.en = IPA_HOLB_TMR_EN; + holb_cfg.tmr_val = IPA_HOLB_TMR_VAL_4_5; + result = ipa3_cfg_ep_holb(dl_clnt_hdl, &holb_cfg); + } + + /* Stop DL channel */ + result = ipa_stop_gsi_channel(dl_clnt_hdl); + if (result) { + IPAERR("Error stopping DL/DPL channel: %d\n", result); + result = -EFAULT; + goto unsuspend_dl_and_exit; + } + + /* STOP UL channel */ + if (!is_dpl) { + source_pipe_bitmask = ipahal_get_ep_bit(ul_clnt_hdl); + source_pipe_reg_idx = ipahal_get_ep_reg_idx(ul_clnt_hdl); + result = ipa3_stop_ul_chan_with_data_drain(qmi_req_id, + source_pipe_bitmask, source_pipe_reg_idx, + should_force_clear, ul_clnt_hdl, false); + if (result) { + IPAERR("Error stopping UL channel: result = %d\n", + result); + goto start_dl_and_exit; + } + } + + IPA_ACTIVE_CLIENTS_DEC_EP(ipa3_get_client_mapping(dl_clnt_hdl)); + + IPADBG("exit\n"); + return 0; + +start_dl_and_exit: + gsi_start_channel(dl_ep->gsi_chan_hdl); + if (IPA_CLIENT_IS_HOLB_CONS(dl_ep->client)) { + res = ipa3_uc_client_add_holb_monitor(dl_ep->gsi_chan_hdl, + HOLB_MONITOR_MASK, holb_max_cnt, + IPA_EE_AP); + if (res) + IPAERR("Add HOLB monitor failed for gsi ch %d\n", + dl_ep->gsi_chan_hdl); + } + ipa3_start_gsi_debug_monitor(dl_clnt_hdl); + /*disable holb to allow packets*/ + if (IPA_CLIENT_IS_CONS(dl_ep->client) && !is_dpl) { + memset(&holb_cfg, 0, sizeof(holb_cfg)); + holb_cfg.en = IPA_HOLB_TMR_DIS; + holb_cfg.tmr_val = 0; + ipa3_cfg_ep_holb(dl_clnt_hdl, &holb_cfg); + } +unsuspend_dl_and_exit: + if (ipa3_ctx->ipa_hw_type < IPA_HW_v4_0) { + /* Unsuspend the DL EP */ + memset(&ep_cfg_ctrl, 0, sizeof(struct ipa_ep_cfg_ctrl)); + ep_cfg_ctrl.ipa_ep_suspend = false; + ipa_cfg_ep_ctrl(dl_clnt_hdl, &ep_cfg_ctrl); + } +disable_clk_and_exit: + IPA_ACTIVE_CLIENTS_DEC_EP(ipa3_get_client_mapping(dl_clnt_hdl)); + return result; +} +EXPORT_SYMBOL(ipa3_xdci_suspend); + +int ipa3_start_gsi_channel(u32 clnt_hdl) +{ + struct ipa3_ep_context *ep; + int result = -EFAULT; + enum gsi_status gsi_res; + enum ipa_client_type client_type; + int res = 0; + u32 holb_max_cnt = ipa3_ctx->uc_ctx.holb_monitor.max_cnt_usb; + + IPADBG("entry\n"); + if (clnt_hdl >= ipa3_ctx->ipa_num_pipes || + ipa3_ctx->ep[clnt_hdl].valid == 0) { + IPAERR("Bad parameters.\n"); + return -EINVAL; + } + + ep = &ipa3_ctx->ep[clnt_hdl]; + client_type = ipa3_get_client_mapping(clnt_hdl); + if (!ep->keep_ipa_awake) + IPA_ACTIVE_CLIENTS_INC_EP(client_type); + + gsi_res = gsi_start_channel(ep->gsi_chan_hdl); + if (gsi_res != GSI_STATUS_SUCCESS) { + IPAERR("Error starting channel: %d\n", gsi_res); + goto start_chan_fail; + } + if (IPA_CLIENT_IS_HOLB_CONS(ep->client)) { + res = ipa3_uc_client_add_holb_monitor(ep->gsi_chan_hdl, + HOLB_MONITOR_MASK, + holb_max_cnt, IPA_EE_AP); + if (res) + IPAERR("Add HOLB monitor failed for gsi ch %d\n", + ep->gsi_chan_hdl); + } + ipa3_start_gsi_debug_monitor(clnt_hdl); + + if (!ep->keep_ipa_awake) + IPA_ACTIVE_CLIENTS_DEC_EP(client_type); + + IPADBG("exit\n"); + return 0; + +start_chan_fail: + if (!ep->keep_ipa_awake) + IPA_ACTIVE_CLIENTS_DEC_EP(ipa3_get_client_mapping(clnt_hdl)); + return result; +} +EXPORT_SYMBOL(ipa3_start_gsi_channel); + +int ipa3_xdci_resume(u32 ul_clnt_hdl, u32 dl_clnt_hdl, bool is_dpl) +{ + struct ipa3_ep_context *ul_ep = NULL; + struct ipa3_ep_context *dl_ep = NULL; + enum gsi_status gsi_res; + struct ipa_ep_cfg_ctrl ep_cfg_ctrl; + int result; + u32 holb_max_cnt = ipa3_ctx->uc_ctx.holb_monitor.max_cnt_usb; + struct ipa_ep_cfg_holb holb_cfg; + + /* In case of DPL, dl is the DPL channel/client */ + + IPADBG("entry\n"); + if (dl_clnt_hdl >= ipa3_ctx->ipa_num_pipes || + ipa3_ctx->ep[dl_clnt_hdl].valid == 0 || + (!is_dpl && (ul_clnt_hdl >= ipa3_ctx->ipa_num_pipes || + ipa3_ctx->ep[ul_clnt_hdl].valid == 0))) { + IPAERR("Bad parameter.\n"); + return -EINVAL; + } + + dl_ep = &ipa3_ctx->ep[dl_clnt_hdl]; + if (!is_dpl) + ul_ep = &ipa3_ctx->ep[ul_clnt_hdl]; + IPA_ACTIVE_CLIENTS_INC_EP(ipa3_get_client_mapping(dl_clnt_hdl)); + + if (ipa3_ctx->ipa_hw_type < IPA_HW_v4_0) { + /* Unsuspend the DL/DPL EP */ + memset(&ep_cfg_ctrl, 0, sizeof(struct ipa_ep_cfg_ctrl)); + ep_cfg_ctrl.ipa_ep_suspend = false; + ipa_cfg_ep_ctrl(dl_clnt_hdl, &ep_cfg_ctrl); + } + + /* Start DL channel */ + gsi_res = gsi_start_channel(dl_ep->gsi_chan_hdl); + if (gsi_res != GSI_STATUS_SUCCESS) + IPAERR("Error starting DL channel: %d\n", gsi_res); + /*disable holb to allow packets*/ + if (IPA_CLIENT_IS_CONS(dl_ep->client) && !is_dpl) { + memset(&holb_cfg, 0, sizeof(holb_cfg)); + holb_cfg.en = IPA_HOLB_TMR_DIS; + holb_cfg.tmr_val = 0; + ipa3_cfg_ep_holb(dl_clnt_hdl, &holb_cfg); + } + if (!is_dpl) { + result = ipa3_uc_client_add_holb_monitor(dl_ep->gsi_chan_hdl, + HOLB_MONITOR_MASK, + holb_max_cnt, IPA_EE_AP); + if (result) + IPAERR("Add HOLB monitor failed for gsi ch %d\n", + dl_ep->gsi_chan_hdl); + } + ipa3_start_gsi_debug_monitor(dl_clnt_hdl); + + /* Start UL channel */ + if (!is_dpl) { + gsi_res = gsi_start_channel(ul_ep->gsi_chan_hdl); + if (gsi_res != GSI_STATUS_SUCCESS) + IPAERR("Error starting UL channel: %d\n", gsi_res); + ipa3_start_gsi_debug_monitor(ul_clnt_hdl); + } + + IPA_ACTIVE_CLIENTS_DEC_EP(ipa3_get_client_mapping(dl_clnt_hdl)); + + IPADBG("exit\n"); + return 0; +} +EXPORT_SYMBOL(ipa3_xdci_resume); + +/** + * ipa3_clear_endpoint_delay() - Remove ep delay set on the IPA pipe before + * client disconnect. + * @clnt_hdl: [in] opaque client handle assigned by IPA to client + * + * Should be called by the driver of the peripheral that wants to remove + * ep delay on IPA consumer ipe before disconnect in non GPI mode. this api + * expects caller to take responsibility to free any needed headers, routing + * and filtering tables and rules as needed. + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_clear_endpoint_delay(u32 clnt_hdl) +{ + struct ipa3_ep_context *ep; + struct ipa_ep_cfg_ctrl ep_ctrl = {0}; + struct ipa_enable_force_clear_datapath_req_msg_v01 req = {0}; + int res; + + if (unlikely(!ipa3_ctx)) { + IPAERR("IPA driver was not initialized\n"); + return -EINVAL; + } + + if (clnt_hdl >= ipa3_ctx->ipa_num_pipes || + ipa3_ctx->ep[clnt_hdl].valid == 0) { + IPAERR("bad parm.\n"); + return -EINVAL; + } + + ep = &ipa3_ctx->ep[clnt_hdl]; + + if (!ipa3_ctx->tethered_flow_control) { + u32 source_pipe_bitmask = ipahal_get_ep_bit(clnt_hdl); + int source_pipe_reg_idx = ipahal_get_ep_reg_idx(clnt_hdl); + IPADBG("APPS flow control is not enabled\n"); + /* Send a message to modem to disable flow control honoring. */ + req.request_id = clnt_hdl; + if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0) { + WARN_ON(source_pipe_reg_idx); + req.source_pipe_bitmask = source_pipe_bitmask; + } else { + req.source_pipe_bitmask_ext_valid = 1; + req.source_pipe_bitmask_ext[source_pipe_reg_idx] = + source_pipe_bitmask; + } + res = ipa3_qmi_enable_force_clear_datapath_send(&req); + if (res) { + IPADBG("enable_force_clear_datapath failed %d\n", + res); + } + ep->qmi_request_sent = true; + } + + IPA_ACTIVE_CLIENTS_INC_EP(ipa3_get_client_mapping(clnt_hdl)); + /* Set disconnect in progress flag so further flow control events are + * not honored. + */ + atomic_set(&ep->disconnect_in_progress, 1); + + /* If flow is disabled at this point, restore the ep state.*/ + ep_ctrl.ipa_ep_delay = false; + ep_ctrl.ipa_ep_suspend = false; + ipa_cfg_ep_ctrl(clnt_hdl, &ep_ctrl); + + IPA_ACTIVE_CLIENTS_DEC_EP(ipa3_get_client_mapping(clnt_hdl)); + + IPADBG("client (ep: %d) removed ep delay\n", clnt_hdl); + + return 0; +} + +static void ipa3_get_gsi_ring_stats(struct IpaHwRingStats_t *ring, + struct ipa3_uc_dbg_stats *ctx_stats, int idx) +{ + ring->ringFull = ioread32( + ctx_stats->uc_dbg_stats_mmio + + idx * IPA3_UC_DEBUG_STATS_OFF + + IPA3_UC_DEBUG_STATS_RINGFULL_OFF); + + ring->ringEmpty = ioread32( + ctx_stats->uc_dbg_stats_mmio + + idx * IPA3_UC_DEBUG_STATS_OFF + + IPA3_UC_DEBUG_STATS_RINGEMPTY_OFF); + ring->ringUsageHigh = ioread32( + ctx_stats->uc_dbg_stats_mmio + + idx * IPA3_UC_DEBUG_STATS_OFF + + IPA3_UC_DEBUG_STATS_RINGUSAGEHIGH_OFF); + ring->ringUsageLow = ioread32( + ctx_stats->uc_dbg_stats_mmio + + idx * IPA3_UC_DEBUG_STATS_OFF + + IPA3_UC_DEBUG_STATS_RINGUSAGELOW_OFF); + ring->RingUtilCount = ioread32( + ctx_stats->uc_dbg_stats_mmio + + idx * IPA3_UC_DEBUG_STATS_OFF + + IPA3_UC_DEBUG_STATS_RINGUTILCOUNT_OFF); +} + +/** + * ipa3_get_aqc_gsi_stats() - Query AQC gsi stats from uc + * @stats: [inout] stats blob from client populated by driver + * + * Returns: 0 on success, negative on failure + * + * @note Cannot be called from atomic context + * + */ +int ipa3_get_aqc_gsi_stats(struct ipa_uc_dbg_ring_stats *stats) +{ + int i; + + if (!ipa3_ctx->aqc_ctx.dbg_stats.uc_dbg_stats_mmio) + return -EINVAL; + + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + for (i = 0; i < MAX_AQC_CHANNELS; i++) { + ipa3_get_gsi_ring_stats(stats->u.ring + i, + &ipa3_ctx->aqc_ctx.dbg_stats, i); + } + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + + + return 0; +} + +/** +* ipa3_get_ntn_gsi_stats() - Query NTN gsi stats from uc +* @stats: [inout] stats blob from client populated by driver +* +* Returns: 0 on success, negative on failure +* +* @note Cannot be called from atomic context +* +*/ +int ipa3_get_ntn_gsi_stats(struct ipa_uc_dbg_ring_stats *stats) +{ + int i; + + if (!ipa3_ctx->ntn_ctx.dbg_stats.uc_dbg_stats_mmio) + return -EINVAL; + + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + for (i = 0; i < MAX_NTN_CHANNELS; i++) { + ipa3_get_gsi_ring_stats(stats->u.ring + i, + &ipa3_ctx->ntn_ctx.dbg_stats, i); + } + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + + + return 0; +} + +/** + * ipa3_get_rtk_gsi_stats() - Query RTK gsi stats from uc + * @stats: [inout] stats blob from client populated by driver + * + * Returns: 0 on success, negative on failure + * + * @note Cannot be called from atomic context + * + */ +int ipa3_get_rtk_gsi_stats(struct ipa_uc_dbg_ring_stats *stats) +{ + int i; + u64 low, high; + + if (!ipa3_ctx->rtk_ctx.dbg_stats.uc_dbg_stats_mmio) + return -EINVAL; + + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + for (i = 0; i < MAX_RTK_CHANNELS; i++) { + ipa3_get_gsi_ring_stats(&stats->u.rtk[i].commStats, + &ipa3_ctx->rtk_ctx.dbg_stats, i); + stats->u.rtk[i].trCount = ioread32( + ipa3_ctx->rtk_ctx.dbg_stats.uc_dbg_stats_mmio + + i * IPA3_UC_DEBUG_STATS_RTK_OFF + + IPA3_UC_DEBUG_STATS_TRCOUNT_OFF); + stats->u.rtk[i].erCount = ioread32( + ipa3_ctx->rtk_ctx.dbg_stats.uc_dbg_stats_mmio + + i * IPA3_UC_DEBUG_STATS_RTK_OFF + + IPA3_UC_DEBUG_STATS_ERCOUNT_OFF); + stats->u.rtk[i].totalAosCount = ioread32( + ipa3_ctx->rtk_ctx.dbg_stats.uc_dbg_stats_mmio + + i * IPA3_UC_DEBUG_STATS_RTK_OFF + + IPA3_UC_DEBUG_STATS_AOSCOUNT_OFF); + low = ioread32(ipa3_ctx->rtk_ctx.dbg_stats.uc_dbg_stats_mmio + + i * IPA3_UC_DEBUG_STATS_RTK_OFF + + IPA3_UC_DEBUG_STATS_BUSYTIME_OFF); + high = ioread32(ipa3_ctx->rtk_ctx.dbg_stats.uc_dbg_stats_mmio + + i * IPA3_UC_DEBUG_STATS_RTK_OFF + + IPA3_UC_DEBUG_STATS_BUSYTIME_OFF + sizeof(u32)); + stats->u.rtk[i].busyTime = low | (high << 32); + } + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + + + return 0; +} diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_debugfs.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_debugfs.c new file mode 100644 index 0000000000..fd58864851 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_debugfs.c @@ -0,0 +1,4816 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. + * + * Copyright (c) 2022, 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifdef CONFIG_DEBUG_FS + +#include +#include +#include +#include "ipa_i.h" +#include "ipa_rm_i.h" +#include "ipahal_reg.h" +#include "ipahal_nat.h" +#include "ipa_odl.h" +#include "ipa_qmi_service.h" +#if defined(CONFIG_IPA_TSP) +/* The following line should be removed once TSP feature is POR */ +#include "ipa_test_module_tsp.h" +#include "ipahal_tsp.h" +#endif +#define IPA_MAX_ENTRY_STRING_LEN 500 +#define IPA_MAX_MSG_LEN 4096 +#define IPA_DBG_MAX_RULE_IN_TBL 128 +#define IPA_DBG_ACTIVE_CLIENT_BUF_SIZE ((IPA3_ACTIVE_CLIENTS_LOG_LINE_LEN \ + * IPA3_ACTIVE_CLIENTS_LOG_BUFFER_SIZE_LINES) + IPA_MAX_MSG_LEN) +#define MAX_UC_BUFF_SIZE (1 * 1024UL * 1024UL) + +#define IPA_DUMP_STATUS_FIELD(f) \ + pr_err(#f "=0x%x\n", status->f) + +#define IPA_READ_ONLY_MODE 0444 +#define IPA_READ_WRITE_MODE 0664 +#define IPA_WRITE_ONLY_MODE 0220 + +struct ipa3_debugfs_file { + const char *name; + umode_t mode; + void *data; + const struct file_operations fops; +}; + +static const char * const ipa_eth_clients_strings[] = { + __stringify(AQC107), + __stringify(AQC113), + __stringify(RTK8111K), + __stringify(RTK8125B), + __stringify(NTN), + __stringify(NTN3), + __stringify(EMAC), +}; + +const char *ipa3_event_name[IPA_EVENT_MAX_NUM] = { + __stringify(WLAN_CLIENT_CONNECT), + __stringify(WLAN_CLIENT_DISCONNECT), + __stringify(WLAN_CLIENT_POWER_SAVE_MODE), + __stringify(WLAN_CLIENT_NORMAL_MODE), + __stringify(SW_ROUTING_ENABLE), + __stringify(SW_ROUTING_DISABLE), + __stringify(WLAN_AP_CONNECT), + __stringify(WLAN_AP_DISCONNECT), + __stringify(WLAN_STA_CONNECT), + __stringify(WLAN_STA_DISCONNECT), + __stringify(WLAN_CLIENT_CONNECT_EX), + __stringify(WLAN_SWITCH_TO_SCC), + __stringify(WLAN_SWITCH_TO_MCC), + __stringify(WLAN_WDI_ENABLE), + __stringify(WLAN_WDI_DISABLE), + __stringify(WAN_UPSTREAM_ROUTE_ADD), + __stringify(WAN_UPSTREAM_ROUTE_DEL), + __stringify(WAN_EMBMS_CONNECT), + __stringify(WAN_XLAT_CONNECT), + __stringify(ECM_CONNECT), + __stringify(ECM_DISCONNECT), + __stringify(IPA_TETHERING_STATS_UPDATE_STATS), + __stringify(IPA_TETHERING_STATS_UPDATE_NETWORK_STATS), + __stringify(IPA_QUOTA_REACH), + __stringify(IPA_SSR_BEFORE_SHUTDOWN), + __stringify(IPA_SSR_AFTER_POWERUP), + __stringify(ADD_VLAN_IFACE), + __stringify(DEL_VLAN_IFACE), + __stringify(ADD_L2TP_VLAN_MAPPING), + __stringify(DEL_L2TP_VLAN_MAPPING), + __stringify(IPA_PER_CLIENT_STATS_CONNECT_EVENT), + __stringify(IPA_PER_CLIENT_STATS_DISCONNECT_EVENT), + __stringify(ADD_BRIDGE_VLAN_MAPPING), + __stringify(DEL_BRIDGE_VLAN_MAPPING), + __stringify(WLAN_FWR_SSR_BEFORE_SHUTDOWN), + __stringify(IPA_GSB_CONNECT), + __stringify(IPA_GSB_DISCONNECT), + __stringify(IPA_COALESCE_ENABLE), + __stringify(IPA_COALESCE_DISABLE), + __stringify(IPA_SET_MTU), + __stringify_1(WIGIG_CLIENT_CONNECT), + __stringify_1(WIGIG_FST_SWITCH), + __stringify(IPA_PDN_DEFAULT_MODE_CONFIG), + __stringify(IPA_PDN_IP_COLLISION_MODE_CONFIG), + __stringify(IPA_PDN_IP_PASSTHROUGH_MODE_CONFIG), + __stringify(IPA_MAC_FLT_EVENT), + __stringify(IPA_SOCKV5_ADD), + __stringify(IPA_SOCKV5_DEL), + __stringify(IPA_SW_FLT_EVENT), + __stringify(IPA_PKT_THRESHOLD_EVENT), + __stringify(IPA_MOVE_NAT_TABLE), + __stringify(IPA_EoGRE_UP_EVENT), + __stringify(IPA_EoGRE_DOWN_EVENT), + __stringify(IPA_IPPT_SW_FLT_EVENT), + __stringify(IPA_MACSEC_ADD_EVENT), + __stringify(IPA_MACSEC_DEL_EVENT), +}; + +const char *ipa3_hdr_l2_type_name[] = { + __stringify(IPA_HDR_L2_NONE), + __stringify(IPA_HDR_L2_ETHERNET_II), + __stringify(IPA_HDR_L2_802_3), + __stringify(IPA_HDR_L2_802_1Q), +}; + +const char *ipa3_hdr_proc_type_name[] = { + __stringify(IPA_HDR_PROC_NONE), + __stringify(IPA_HDR_PROC_ETHII_TO_ETHII), + __stringify(IPA_HDR_PROC_ETHII_TO_802_3), + __stringify(IPA_HDR_PROC_802_3_TO_ETHII), + __stringify(IPA_HDR_PROC_802_3_TO_802_3), + __stringify(IPA_HDR_PROC_L2TP_HEADER_ADD), + __stringify(IPA_HDR_PROC_L2TP_HEADER_REMOVE), + __stringify(IPA_HDR_PROC_ETHII_TO_ETHII_EX), + __stringify(IPA_HDR_PROC_L2TP_UDP_HEADER_ADD), + __stringify(IPA_HDR_PROC_L2TP_UDP_HEADER_REMOVE), + __stringify(IPA_HDR_PROC_SET_DSCP), + __stringify(IPA_HDR_PROC_EoGRE_HEADER_ADD), + __stringify(IPA_HDR_PROC_EoGRE_HEADER_REMOVE), + __stringify(IPA_HDR_PROC_RTP_METADATA_STREAM0), + __stringify(IPA_HDR_PROC_RTP_METADATA_STREAM1), + __stringify(IPA_HDR_PROC_RTP_METADATA_STREAM2), + __stringify(IPA_HDR_PROC_RTP_METADATA_STREAM3), +}; + +static struct dentry *dent; +static struct dentry *dent_eth; +static char dbg_buff[IPA_MAX_MSG_LEN + 1]; +static char *active_clients_buf; + +static s8 ep_reg_idx; +static void *ipa_ipc_low_buff; +static u8 active_streams[MAX_STREAMS]; +static u8 active_flt_cnt; + + +static ssize_t ipa3_read_gen_reg(struct file *file, char __user *ubuf, + size_t count, loff_t *ppos) +{ + int nbytes; + struct ipahal_reg_shared_mem_size smem_sz; + + memset(&smem_sz, 0, sizeof(smem_sz)); + + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + + ipahal_read_reg_fields(IPA_SHARED_MEM_SIZE, &smem_sz); + nbytes = scnprintf(dbg_buff, IPA_MAX_MSG_LEN, + "IPA_VERSION=0x%x\n" + "IPA_COMP_HW_VERSION=0x%x\n" + "IPA_ROUTE=0x%x\n" + "IPA_SHARED_MEM_RESTRICTED=0x%x\n" + "IPA_SHARED_MEM_SIZE=0x%x\n" + "IPA_QTIME_TIMESTAMP_CFG=0x%x\n" + "IPA_TIMERS_PULSE_GRAN_CFG=0x%x\n" + "IPA_TIMERS_XO_CLK_DIV_CFG=0x%x\n", + ipahal_read_reg(IPA_VERSION), + ipahal_read_reg(IPA_COMP_HW_VERSION), + ipahal_read_reg(IPA_ROUTE), + smem_sz.shared_mem_baddr, + smem_sz.shared_mem_sz, + ipahal_read_reg(IPA_QTIME_TIMESTAMP_CFG), + ipahal_read_reg(IPA_TIMERS_PULSE_GRAN_CFG), + ipahal_read_reg(IPA_TIMERS_XO_CLK_DIV_CFG)); + + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + + return simple_read_from_buffer(ubuf, count, ppos, dbg_buff, nbytes); +} + +static ssize_t ipa3_write_ep_holb(struct file *file, + const char __user *buf, size_t count, loff_t *ppos) +{ + struct ipa_ep_cfg_holb holb; + u32 en; + u32 tmr_val; + u32 ep_idx; + unsigned long missing; + char *sptr, *token; + + if (count >= sizeof(dbg_buff)) + return -EFAULT; + + missing = copy_from_user(dbg_buff, buf, count); + if (missing) + return -EFAULT; + + dbg_buff[count] = '\0'; + + sptr = dbg_buff; + + token = strsep(&sptr, " "); + if (!token) + return -EINVAL; + if (kstrtou32(token, 0, &ep_idx)) + return -EINVAL; + + token = strsep(&sptr, " "); + if (!token) + return -EINVAL; + if (kstrtou32(token, 0, &en)) + return -EINVAL; + + token = strsep(&sptr, " "); + if (!token) + return -EINVAL; + if (kstrtou32(token, 0, &tmr_val)) + return -EINVAL; + + holb.en = en; + holb.tmr_val = tmr_val; + + ipa3_cfg_ep_holb(ep_idx, &holb); + + return count; +} + +static ssize_t ipa3_write_holb_monitor_client(struct file *file, + const char __user *buf, size_t count, loff_t *ppos) +{ + struct ipa_uc_holb_client_info holb_client; + u32 max_stuck_cnt; + u16 gsi_ch; + u8 set_client; + unsigned long missing; + char *sptr, *token; + + if (count >= sizeof(dbg_buff)) + return -EFAULT; + + missing = copy_from_user(dbg_buff, buf, count); + if (missing) + return -EFAULT; + + dbg_buff[count] = '\0'; + + sptr = dbg_buff; + + token = strsep(&sptr, " "); + if (!token) + return -EINVAL; + if (kstrtou16(token, 0, &gsi_ch)) + return -EINVAL; + + token = strsep(&sptr, " "); + if (!token) + return -EINVAL; + if (kstrtou32(token, 0, &max_stuck_cnt)) + return -EINVAL; + + token = strsep(&sptr, " "); + if (!token) + return -EINVAL; + if (kstrtou8(token, 0, &set_client)) + return -EINVAL; + + holb_client.gsi_chan_hdl = gsi_ch; + holb_client.debugfs_param = set_client; + holb_client.max_stuck_cnt = max_stuck_cnt; + holb_client.action_mask = HOLB_MONITOR_MASK; + holb_client.ee = IPA_EE_AP; + + + ipa3_set_holb_client_by_ch(holb_client); + + return count; +} + +static ssize_t ipa3_write_holb_monitor_client_add_del(struct file *file, + const char __user *buf, size_t count, loff_t *ppos) +{ + u32 max_stuck_cnt, action_mask; + u16 gsi_ch; + u8 ee, add_client; + + unsigned long missing; + char *sptr, *token; + + if (count >= sizeof(dbg_buff)) + return -EFAULT; + + missing = copy_from_user(dbg_buff, buf, count); + if (missing) + return -EFAULT; + + dbg_buff[count] = '\0'; + + sptr = dbg_buff; + + token = strsep(&sptr, " "); + if (!token) + return -EINVAL; + if (kstrtou16(token, 0, &gsi_ch)) + return -EINVAL; + + token = strsep(&sptr, " "); + if (!token) + return -EINVAL; + if (kstrtou32(token, 0, &action_mask)) + return -EINVAL; + + token = strsep(&sptr, " "); + if (!token) + return -EINVAL; + if (kstrtou32(token, 0, &max_stuck_cnt)) + return -EINVAL; + + token = strsep(&sptr, " "); + if (!token) + return -EINVAL; + if (kstrtou8(token, 0, &ee)) + return -EINVAL; + + + token = strsep(&sptr, " "); + if (!token) + return -EINVAL; + if (kstrtou8(token, 0, &add_client)) + return -EINVAL; + + if (add_client) + ipa3_uc_client_add_holb_monitor(gsi_ch, action_mask, + max_stuck_cnt, ee); + else + ipa3_uc_client_del_holb_monitor(gsi_ch, ee); + + return count; +} +static ssize_t ipa3_write_ep_reg(struct file *file, const char __user *buf, + size_t count, loff_t *ppos) +{ + s8 option; + int ret; + + ret = kstrtos8_from_user(buf, count, 0, &option); + if (ret) + return ret; + + if (option >= ipa3_ctx->ipa_num_pipes) { + IPAERR("bad pipe specified %u\n", option); + return count; + } + + ep_reg_idx = option; + + return count; +} + +/** + * _ipa_read_ep_reg_v3_0() - Reads and prints endpoint configuration registers + * + * Returns the number of characters printed + */ +int _ipa_read_ep_reg_v3_0(char *buf, int max_len, int pipe) +{ + return scnprintf( + dbg_buff, IPA_MAX_MSG_LEN, + "IPA_ENDP_INIT_NAT_%u=0x%x\n" + "IPA_ENDP_INIT_HDR_%u=0x%x\n" + "IPA_ENDP_INIT_HDR_EXT_%u=0x%x\n" + "IPA_ENDP_INIT_MODE_%u=0x%x\n" + "IPA_ENDP_INIT_AGGR_%u=0x%x\n" + "IPA_ENDP_INIT_ROUTE_%u=0x%x\n" + "IPA_ENDP_INIT_CTRL_%u=0x%x\n" + "IPA_ENDP_INIT_HOL_EN_%u=0x%x\n" + "IPA_ENDP_INIT_HOL_TIMER_%u=0x%x\n" + "IPA_ENDP_INIT_DEAGGR_%u=0x%x\n" + "IPA_ENDP_INIT_CFG_%u=0x%x\n" + "IPA_ENDP_INIT_PROD_CFG_%u=0x%x\n", + pipe, ipahal_read_reg_n(IPA_ENDP_INIT_NAT_n, pipe), + pipe, ipahal_read_reg_n(IPA_ENDP_INIT_HDR_n, pipe), + pipe, ipahal_read_reg_n(IPA_ENDP_INIT_HDR_EXT_n, pipe), + pipe, ipahal_read_reg_n(IPA_ENDP_INIT_MODE_n, pipe), + pipe, ipahal_read_reg_n(IPA_ENDP_INIT_AGGR_n, pipe), + pipe, ipahal_read_reg_n(IPA_ENDP_INIT_ROUTE_n, pipe), + pipe, ipahal_read_reg_n(IPA_ENDP_INIT_CTRL_n, pipe), + pipe, ipahal_read_reg_n(IPA_ENDP_INIT_HOL_BLOCK_EN_n, pipe), + pipe, ipahal_read_reg_n(IPA_ENDP_INIT_HOL_BLOCK_TIMER_n, pipe), + pipe, ipahal_read_reg_n(IPA_ENDP_INIT_DEAGGR_n, pipe), + pipe, ipahal_read_reg_n(IPA_ENDP_INIT_CFG_n, pipe), + pipe, ipahal_read_reg_n(IPA_ENDP_INIT_PROD_CFG_n, pipe)); +} + +/** + * _ipa_read_ep_reg_v4_0() - Reads and prints endpoint configuration registers + * + * Returns the number of characters printed + * Removed IPA_ENDP_INIT_ROUTE_n from v3 + */ +int _ipa_read_ep_reg_v4_0(char *buf, int max_len, int pipe) +{ + return scnprintf( + dbg_buff, IPA_MAX_MSG_LEN, + "IPA_ENDP_INIT_NAT_%u=0x%x\n" + "IPA_ENDP_INIT_CONN_TRACK_n%u=0x%x\n" + "IPA_ENDP_INIT_HDR_%u=0x%x\n" + "IPA_ENDP_INIT_HDR_EXT_%u=0x%x\n" + "IPA_ENDP_INIT_MODE_%u=0x%x\n" + "IPA_ENDP_INIT_AGGR_%u=0x%x\n" + "IPA_ENDP_INIT_CTRL_%u=0x%x\n" + "IPA_ENDP_INIT_HOL_EN_%u=0x%x\n" + "IPA_ENDP_INIT_HOL_TIMER_%u=0x%x\n" + "IPA_ENDP_INIT_DEAGGR_%u=0x%x\n" + "IPA_ENDP_INIT_CFG_%u=0x%x\n", + pipe, ipahal_read_reg_n(IPA_ENDP_INIT_NAT_n, pipe), + pipe, ipahal_read_reg_n(IPA_ENDP_INIT_CONN_TRACK_n, pipe), + pipe, ipahal_read_reg_n(IPA_ENDP_INIT_HDR_n, pipe), + pipe, ipahal_read_reg_n(IPA_ENDP_INIT_HDR_EXT_n, pipe), + pipe, ipahal_read_reg_n(IPA_ENDP_INIT_MODE_n, pipe), + pipe, ipahal_read_reg_n(IPA_ENDP_INIT_AGGR_n, pipe), + pipe, ipahal_read_reg_n(IPA_ENDP_INIT_CTRL_n, pipe), + pipe, ipahal_read_reg_n(IPA_ENDP_INIT_HOL_BLOCK_EN_n, pipe), + pipe, ipahal_read_reg_n(IPA_ENDP_INIT_HOL_BLOCK_TIMER_n, pipe), + pipe, ipahal_read_reg_n(IPA_ENDP_INIT_DEAGGR_n, pipe), + pipe, ipahal_read_reg_n(IPA_ENDP_INIT_CFG_n, pipe)); +} + +static ssize_t ipa3_read_ep_reg(struct file *file, char __user *ubuf, + size_t count, loff_t *ppos) +{ + int nbytes; + int i; + int start_idx; + int end_idx; + int size = 0; + int ret; + loff_t pos; + + /* negative ep_reg_idx means all registers */ + if (ep_reg_idx < 0) { + start_idx = 0; + end_idx = ipa3_ctx->ipa_num_pipes; + } else { + start_idx = ep_reg_idx; + end_idx = start_idx + 1; + } + pos = *ppos; + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + for (i = start_idx; i < end_idx; i++) { + + nbytes = ipa3_ctx->ctrl->ipa3_read_ep_reg(dbg_buff, + IPA_MAX_MSG_LEN, i); + + *ppos = pos; + ret = simple_read_from_buffer(ubuf, count, ppos, dbg_buff, + nbytes); + if (ret < 0) { + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + return ret; + } + + size += ret; + ubuf += nbytes; + count -= nbytes; + } + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + + *ppos = pos + size; + return size; +} + +static ssize_t ipa3_set_clk_index(struct file *file, const char __user *buf, + size_t count, loff_t *ppos) +{ + s8 option = 0; + int ret; + uint32_t bw_idx = 0; + + ret = kstrtos8_from_user(buf, count, 0, &option); + if (ret) + return ret; + + switch (option) { + case 0: + bw_idx = 0; + break; + case 1: + bw_idx = 1; + break; + case 2: + bw_idx = 2; + break; + case 3: + bw_idx = 3; + break; + case 4: + bw_idx = 4; + break; + default: + pr_err("Not support this vote (%d)\n", option); + return -EFAULT; + } + pr_info("Make sure some client connected before scaling the BW\n"); + ipa3_ctx->enable_clock_scaling = 1; + if (ipa3_set_clock_plan_from_pm(bw_idx)) { + IPAERR("Failed to vote for bus BW (%u)\n", bw_idx); + return -EFAULT; + } + ipa3_ctx->enable_clock_scaling = 0; + IPAERR("Clock scaling is done sucessful\n"); + + return count; +} + +static ssize_t ipa3_write_keep_awake(struct file *file, const char __user *buf, + size_t count, loff_t *ppos) +{ + s8 option = 0; + int ret; + + ret = kstrtos8_from_user(buf, count, 0, &option); + if (ret) + return ret; + + if (option == 0) { + if (ipa_pm_remove_dummy_clients()) { + pr_err("Failed to remove dummy clients\n"); + return -EFAULT; + } + } else { + if (ipa_pm_add_dummy_clients(option - 1)) { + pr_err("Failed to add dummy clients\n"); + return -EFAULT; + } + } + + return count; +} + +static ssize_t ipa3_read_keep_awake(struct file *file, char __user *ubuf, + size_t count, loff_t *ppos) +{ + int nbytes; + + mutex_lock(&ipa3_ctx->ipa3_active_clients.mutex); + if (atomic_read(&ipa3_ctx->ipa3_active_clients.cnt)) + nbytes = scnprintf(dbg_buff, IPA_MAX_MSG_LEN, + "IPA APPS power state is ON\n"); + else + nbytes = scnprintf(dbg_buff, IPA_MAX_MSG_LEN, + "IPA APPS power state is OFF\n"); + mutex_unlock(&ipa3_ctx->ipa3_active_clients.mutex); + + return simple_read_from_buffer(ubuf, count, ppos, dbg_buff, nbytes); +} + +static ssize_t ipa3_read_mpm_ring_size_dl(struct file *file, char __user *ubuf, + size_t count, loff_t *ppos) +{ + int nbytes; + + nbytes = scnprintf(dbg_buff, IPA_MAX_MSG_LEN, + "IPA_MPM_RING_SIZE_DL = %d\n", + ipa3_ctx->mpm_ring_size_dl); + + return simple_read_from_buffer(ubuf, count, ppos, dbg_buff, nbytes); +} + +static ssize_t ipa3_read_mpm_ring_size_ul(struct file *file, char __user *ubuf, + size_t count, loff_t *ppos) +{ + int nbytes; + + nbytes = scnprintf(dbg_buff, IPA_MAX_MSG_LEN, + "IPA_MPM_RING_SIZE_UL = %d\n", + ipa3_ctx->mpm_ring_size_ul); + + return simple_read_from_buffer(ubuf, count, ppos, dbg_buff, nbytes); +} + +static ssize_t ipa3_read_mpm_uc_thresh(struct file *file, char __user *ubuf, + size_t count, loff_t *ppos) +{ + int nbytes; + + nbytes = scnprintf(dbg_buff, IPA_MAX_MSG_LEN, + "IPA_MPM_UC_THRESH = %d\n", ipa3_ctx->mpm_uc_thresh); + + return simple_read_from_buffer(ubuf, count, ppos, dbg_buff, nbytes); +} + +static ssize_t ipa3_read_mpm_teth_aggr_size(struct file *file, + char __user *ubuf, size_t count, loff_t *ppos) +{ + int nbytes; + + nbytes = scnprintf(dbg_buff, IPA_MAX_MSG_LEN, + "IPA_MPM_TETH_AGGR_SIZE = %d\n", + ipa3_ctx->mpm_teth_aggr_size); + + return simple_read_from_buffer(ubuf, count, ppos, dbg_buff, nbytes); +} + +static ssize_t ipa3_write_mpm_ring_size_dl(struct file *file, + const char __user *buf, + size_t count, loff_t *ppos) +{ + s8 option = 0; + int ret; + + ret = kstrtos8_from_user(buf, count, 0, &option); + if (ret) + return ret; + /* as option is type s8, max it can take is 127 */ + if ((option > 0) && (option <= IPA_MPM_MAX_RING_LEN)) + ipa3_ctx->mpm_ring_size_dl = option; + else + IPAERR("Invalid dl ring size =%d: range is 1 to %d\n", + option, IPA_MPM_MAX_RING_LEN); + return count; +} + +static ssize_t ipa3_write_mpm_ring_size_ul(struct file *file, + const char __user *buf, + size_t count, loff_t *ppos) +{ + s8 option = 0; + int ret; + + ret = kstrtos8_from_user(buf, count, 0, &option); + if (ret) + return ret; + /* as option is type s8, max it can take is 127 */ + if ((option > 0) && (option <= IPA_MPM_MAX_RING_LEN)) + ipa3_ctx->mpm_ring_size_ul = option; + else + IPAERR("Invalid ul ring size =%d: range is 1 to %d\n", + option, IPA_MPM_MAX_RING_LEN); + return count; +} + +static ssize_t ipa3_write_mpm_uc_thresh(struct file *file, + const char __user *buf, + size_t count, loff_t *ppos) +{ + s8 option = 0; + int ret; + + ret = kstrtos8_from_user(buf, count, 0, &option); + if (ret) + return ret; + /* as option is type s8, max it can take is 127 */ + if ((option > 0) && (option <= IPA_MPM_MAX_UC_THRESH)) + ipa3_ctx->mpm_uc_thresh = option; + else + IPAERR("Invalid uc thresh =%d: range is 1 to %d\n", + option, IPA_MPM_MAX_UC_THRESH); + return count; +} + +static ssize_t ipa3_write_mpm_teth_aggr_size(struct file *file, + const char __user *buf, + size_t count, loff_t *ppos) +{ + s8 option = 0; + int ret; + + ret = kstrtos8_from_user(buf, count, 0, &option); + if (ret) + return ret; + /* as option is type s8, max it can take is 127 */ + if ((option > 0) && (option <= IPA_MAX_TETH_AGGR_BYTE_LIMIT)) + ipa3_ctx->mpm_teth_aggr_size = option; + else + IPAERR("Invalid agg byte limit =%d: range is 1 to %d\n", + option, IPA_MAX_TETH_AGGR_BYTE_LIMIT); + return count; +} + +static ssize_t ipa3_read_holb_events(struct file *file, char __user *ubuf, size_t count, + loff_t *ppos) +{ + int nbytes = 0; + int client_idx; + int event_id; + bool enable; + int num_clients = ipa3_ctx->uc_ctx.holb_monitor.num_holb_clients; + struct ipa_uc_holb_client_info *holb_client; + uint32_t qtimer_lsb; + uint32_t qtimer_msb; + + mutex_lock(&ipa3_ctx->lock); + for (client_idx = 0; client_idx < num_clients; client_idx++) { + holb_client = + &(ipa3_ctx->uc_ctx.holb_monitor.client[client_idx]); + event_id = holb_client->current_idx; + nbytes += scnprintf( + dbg_buff + nbytes, + IPA_MAX_MSG_LEN - nbytes, + "========================\n"); + nbytes += scnprintf( + dbg_buff + nbytes, + IPA_MAX_MSG_LEN - nbytes, + "GSI ch %d cur event_id %d ", + holb_client->gsi_chan_hdl, holb_client->current_idx); + nbytes += scnprintf( + dbg_buff + nbytes, + IPA_MAX_MSG_LEN - nbytes, + "enable cnt %d disable cnt %d\n", + holb_client->enable_cnt, holb_client->disable_cnt); + for (event_id = 0; event_id < IPA_HOLB_EVENT_LOG_MAX; event_id++) { + enable = holb_client->events[event_id].enable; + qtimer_lsb = holb_client->events[event_id].qTimerLSB; + qtimer_msb = holb_client->events[event_id].qTimerMSB; + nbytes += scnprintf( + dbg_buff + nbytes, + IPA_MAX_MSG_LEN - nbytes, + "event id %d: %s QTimer %u %u\n", + event_id, + enable ? "Bad Periph event" : "Recovered Periph event", + qtimer_lsb, + qtimer_msb); + } + nbytes += scnprintf( + dbg_buff + nbytes, + IPA_MAX_MSG_LEN - nbytes, + "===============\n"); + } + + mutex_unlock(&ipa3_ctx->lock); + + return simple_read_from_buffer(ubuf, count, ppos, dbg_buff, nbytes); +} + +static ssize_t ipa3_read_hdr(struct file *file, char __user *ubuf, size_t count, + loff_t *ppos) +{ + int nbytes = 0; + int i = 0; + struct ipa3_hdr_entry *entry; + enum hdr_tbl_storage hdr_tbl; + struct ipa_hdr_offset_entry *offset_entry; + unsigned int offset_count; + + mutex_lock(&ipa3_ctx->lock); + + for (hdr_tbl = HDR_TBL_LCL; hdr_tbl < HDR_TBLS_TOTAL; hdr_tbl++) { + if (hdr_tbl == HDR_TBL_LCL) + pr_err("Table on local memory:\n"); + else + pr_err("Table on system (ddr) memory:\n"); + + nbytes = scnprintf(dbg_buff, IPA_MAX_MSG_LEN, "Used offsets: "); + for (i = 0; i < IPA_HDR_BIN_MAX; i++){ + offset_count = 0; + list_for_each_entry(offset_entry, + &ipa3_ctx->hdr_tbl[hdr_tbl].head_offset_list[i], + link) + offset_count++; + if (offset_count) + nbytes += scnprintf(dbg_buff + nbytes, + IPA_MAX_MSG_LEN - nbytes, + "%u * %u bytes, ", + offset_count, + ipa3_get_hdr_bin_size(i)); + } + pr_err("%s", dbg_buff); + + nbytes = scnprintf(dbg_buff, IPA_MAX_MSG_LEN, "Free offsets: "); + for (i = 0; i < IPA_HDR_BIN_MAX; i++){ + offset_count = 0; + list_for_each_entry(offset_entry, + &ipa3_ctx->hdr_tbl[hdr_tbl].head_free_offset_list[i], + link) + offset_count++; + if (offset_count) + nbytes += scnprintf(dbg_buff + nbytes, + IPA_MAX_MSG_LEN - nbytes, + "%u * %u bytes, ", + offset_count, + ipa3_get_hdr_bin_size(i)); + } + pr_err("%s", dbg_buff); + + list_for_each_entry(entry, &ipa3_ctx->hdr_tbl[hdr_tbl].head_hdr_entry_list, + link) { + if (entry->cookie != IPA_HDR_COOKIE) + continue; + nbytes = scnprintf( + dbg_buff, + IPA_MAX_MSG_LEN, + "name:%s len=%d ref=%d partial=%d type=%s ofst=%u ", + entry->name, + entry->hdr_len, + entry->ref_cnt, + entry->is_partial, + ipa3_hdr_l2_type_name[entry->type], + entry->offset_entry->offset >> 2); + + for (i = 0; i < entry->hdr_len; i++) { + scnprintf(dbg_buff + nbytes + i * 2, + IPA_MAX_MSG_LEN - nbytes - i * 2, + "%02x", entry->hdr[i]); + } + scnprintf(dbg_buff + nbytes + entry->hdr_len * 2, + IPA_MAX_MSG_LEN - nbytes - entry->hdr_len * 2, + "\n"); + pr_err("%s", dbg_buff); + } + } + mutex_unlock(&ipa3_ctx->lock); + + return 0; +} + +static int ipa3_attrib_dump(struct ipa_rule_attrib *attrib, + enum ipa_ip_type ip) +{ + uint32_t addr[4]; + uint32_t mask[4]; + int i; + + if (attrib->attrib_mask & IPA_FLT_IS_PURE_ACK) + pr_cont("is_pure_ack "); + + if (attrib->attrib_mask & IPA_FLT_TOS) + pr_cont("tos:%d ", attrib->u.v4.tos); + + if (attrib->attrib_mask & IPA_FLT_TOS_MASKED) { + pr_cont("tos_value:%d ", attrib->tos_value); + pr_cont("tos_mask:%d ", attrib->tos_mask); + } + + if (attrib->attrib_mask & IPA_FLT_PROTOCOL) + pr_cont("protocol:%d ", attrib->u.v4.protocol); + + if (attrib->attrib_mask & IPA_FLT_SRC_ADDR) { + if (ip == IPA_IP_v4) { + addr[0] = htonl(attrib->u.v4.src_addr); + mask[0] = htonl(attrib->u.v4.src_addr_mask); + pr_cont( + "src_addr:%pI4 src_addr_mask:%pI4 ", + addr + 0, mask + 0); + } else if (ip == IPA_IP_v6) { + for (i = 0; i < 4; i++) { + addr[i] = htonl(attrib->u.v6.src_addr[i]); + mask[i] = htonl(attrib->u.v6.src_addr_mask[i]); + } + pr_cont( + "src_addr:%pI6 src_addr_mask:%pI6 ", + addr + 0, mask + 0); + } + } + if (attrib->attrib_mask & IPA_FLT_DST_ADDR) { + if (ip == IPA_IP_v4) { + addr[0] = htonl(attrib->u.v4.dst_addr); + mask[0] = htonl(attrib->u.v4.dst_addr_mask); + pr_cont( + "dst_addr:%pI4 dst_addr_mask:%pI4 ", + addr + 0, mask + 0); + } else if (ip == IPA_IP_v6) { + for (i = 0; i < 4; i++) { + addr[i] = htonl(attrib->u.v6.dst_addr[i]); + mask[i] = htonl(attrib->u.v6.dst_addr_mask[i]); + } + pr_cont( + "dst_addr:%pI6 dst_addr_mask:%pI6 ", + addr + 0, mask + 0); + } + } + if (attrib->attrib_mask & IPA_FLT_SRC_PORT_RANGE) { + pr_cont("src_port_range:%u %u ", + attrib->src_port_lo, + attrib->src_port_hi); + } + if (attrib->attrib_mask & IPA_FLT_DST_PORT_RANGE) { + pr_cont("dst_port_range:%u %u ", + attrib->dst_port_lo, + attrib->dst_port_hi); + } + if (attrib->attrib_mask & IPA_FLT_TYPE) + pr_cont("type:%d ", attrib->type); + + if (attrib->attrib_mask & IPA_FLT_CODE) + pr_cont("code:%d ", attrib->code); + + if (attrib->attrib_mask & IPA_FLT_SPI) + pr_cont("spi:%x ", attrib->spi); + + if (attrib->attrib_mask & IPA_FLT_SRC_PORT) + pr_cont("src_port:%u ", attrib->src_port); + + if (attrib->attrib_mask & IPA_FLT_DST_PORT) + pr_cont("dst_port:%u ", attrib->dst_port); + + if (attrib->attrib_mask & IPA_FLT_TC) + pr_cont("tc:%d ", attrib->u.v6.tc); + + if (attrib->attrib_mask & IPA_FLT_FLOW_LABEL) + pr_cont("flow_label:%x ", attrib->u.v6.flow_label); + + if (attrib->attrib_mask & IPA_FLT_NEXT_HDR) + pr_cont("next_hdr:%d ", attrib->u.v6.next_hdr); + + if (attrib->ext_attrib_mask & IPA_FLT_EXT_NEXT_HDR) + pr_err("next_hdr:%d ", attrib->u.v6.next_hdr); + + if (attrib->attrib_mask & IPA_FLT_META_DATA) { + pr_cont( + "metadata:%x metadata_mask:%x ", + attrib->meta_data, attrib->meta_data_mask); + } + + if (attrib->attrib_mask & IPA_FLT_FRAGMENT) + pr_cont("frg "); + + if ((attrib->attrib_mask & IPA_FLT_MAC_SRC_ADDR_ETHER_II) || + (attrib->attrib_mask & IPA_FLT_MAC_SRC_ADDR_802_3) || + (attrib->attrib_mask & IPA_FLT_MAC_SRC_ADDR_802_1Q)) { + pr_cont("src_mac_addr:%pM ", attrib->src_mac_addr); + } + + if ((attrib->attrib_mask & IPA_FLT_MAC_DST_ADDR_ETHER_II) || + (attrib->attrib_mask & IPA_FLT_MAC_DST_ADDR_802_3) || + (attrib->attrib_mask & IPA_FLT_MAC_DST_ADDR_L2TP) || + (attrib->attrib_mask & IPA_FLT_MAC_DST_ADDR_802_1Q) || + (attrib->attrib_mask & IPA_FLT_L2TP_UDP_INNER_MAC_DST_ADDR)) { + pr_cont("dst_mac_addr:%pM ", attrib->dst_mac_addr); + } + + if (attrib->ext_attrib_mask & IPA_FLT_EXT_MTU) + pr_err("Payload Length:%d ", attrib->payload_length); + + if (attrib->attrib_mask & IPA_FLT_MAC_ETHER_TYPE || + attrib->ext_attrib_mask & IPA_FLT_EXT_L2TP_UDP_INNER_ETHER_TYPE) + pr_cont("ether_type:%x ", attrib->ether_type); + + if (attrib->attrib_mask & IPA_FLT_VLAN_ID) + pr_cont("vlan_id:%x ", attrib->vlan_id); + + if (attrib->attrib_mask & IPA_FLT_TCP_SYN) + pr_cont("tcp syn "); + + if (attrib->attrib_mask & IPA_FLT_TCP_SYN_L2TP || + attrib->ext_attrib_mask & IPA_FLT_EXT_L2TP_UDP_TCP_SYN) + pr_cont("tcp syn l2tp "); + + if (attrib->attrib_mask & IPA_FLT_L2TP_INNER_IP_TYPE) + pr_cont("l2tp inner ip type: %d ", attrib->type); + + if (attrib->attrib_mask & IPA_FLT_L2TP_INNER_IPV4_DST_ADDR) { + addr[0] = htonl(attrib->u.v4.dst_addr); + mask[0] = htonl(attrib->u.v4.dst_addr_mask); + pr_cont("dst_addr:%pI4 dst_addr_mask:%pI4 ", addr, mask); + } + + pr_err("\n"); + return 0; +} + +static int ipa3_attrib_dump_eq(struct ipa_ipfltri_rule_eq *attrib) +{ + uint8_t addr[16]; + uint8_t mask[16]; + int i; + int j; + + if (attrib->tos_eq_present) { + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_5) + pr_err("pure_ack "); + else + pr_err("tos:%d ", attrib->tos_eq); + } + + if (attrib->protocol_eq_present) + pr_err("protocol:%d ", attrib->protocol_eq); + + if (attrib->tc_eq_present) + pr_err("tc:%d ", attrib->tc_eq); + + if (attrib->num_offset_meq_128 > IPA_IPFLTR_NUM_MEQ_128_EQNS) { + IPAERR_RL("num_offset_meq_128 Max %d passed value %d\n", + IPA_IPFLTR_NUM_MEQ_128_EQNS, attrib->num_offset_meq_128); + return -EPERM; + } + + for (i = 0; i < attrib->num_offset_meq_128; i++) { + for (j = 0; j < 16; j++) { + addr[j] = attrib->offset_meq_128[i].value[j]; + mask[j] = attrib->offset_meq_128[i].mask[j]; + } + pr_err( + "(ofst_meq128: ofst:%d mask:%pI6 val:%pI6) ", + attrib->offset_meq_128[i].offset, + mask, addr); + } + + if (attrib->num_offset_meq_32 > IPA_IPFLTR_NUM_MEQ_32_EQNS) { + IPAERR_RL("num_offset_meq_32 Max %d passed value %d\n", + IPA_IPFLTR_NUM_MEQ_32_EQNS, attrib->num_offset_meq_32); + return -EPERM; + } + + for (i = 0; i < attrib->num_offset_meq_32; i++) + pr_err( + "(ofst_meq32: ofst:%u mask:0x%x val:0x%x) ", + attrib->offset_meq_32[i].offset, + attrib->offset_meq_32[i].mask, + attrib->offset_meq_32[i].value); + + if (attrib->num_ihl_offset_meq_32 > IPA_IPFLTR_NUM_IHL_MEQ_32_EQNS) { + IPAERR_RL("num_ihl_offset_meq_32 Max %d passed value %d\n", + IPA_IPFLTR_NUM_IHL_MEQ_32_EQNS, attrib->num_ihl_offset_meq_32); + return -EPERM; + } + + for (i = 0; i < attrib->num_ihl_offset_meq_32; i++) + pr_err( + "(ihl_ofst_meq32: ofts:%d mask:0x%x val:0x%x) ", + attrib->ihl_offset_meq_32[i].offset, + attrib->ihl_offset_meq_32[i].mask, + attrib->ihl_offset_meq_32[i].value); + + if (attrib->metadata_meq32_present) + pr_err( + "(metadata: ofst:%u mask:0x%x val:0x%x) ", + attrib->metadata_meq32.offset, + attrib->metadata_meq32.mask, + attrib->metadata_meq32.value); + + if (attrib->num_ihl_offset_range_16 > + IPA_IPFLTR_NUM_IHL_RANGE_16_EQNS) { + IPAERR_RL("num_ihl_offset_range_16 Max %d passed value %d\n", + IPA_IPFLTR_NUM_IHL_RANGE_16_EQNS, + attrib->num_ihl_offset_range_16); + return -EPERM; + } + + for (i = 0; i < attrib->num_ihl_offset_range_16; i++) + pr_err( + "(ihl_ofst_range16: ofst:%u lo:%u hi:%u) ", + attrib->ihl_offset_range_16[i].offset, + attrib->ihl_offset_range_16[i].range_low, + attrib->ihl_offset_range_16[i].range_high); + + if (attrib->ihl_offset_eq_32_present) + pr_err( + "(ihl_ofst_eq32:%d val:0x%x) ", + attrib->ihl_offset_eq_32.offset, + attrib->ihl_offset_eq_32.value); + + if (attrib->ihl_offset_eq_16_present) + pr_err( + "(ihl_ofst_eq16:%d val:0x%x) ", + attrib->ihl_offset_eq_16.offset, + attrib->ihl_offset_eq_16.value); + + if (attrib->fl_eq_present) + pr_err("flow_label:%d ", attrib->fl_eq); + + if (attrib->ipv4_frag_eq_present) + pr_err("frag "); + + pr_err("\n"); + return 0; +} + +static int ipa3_open_dbg(struct inode *inode, struct file *file) +{ + file->private_data = inode->i_private; + return 0; +} + +static ssize_t ipa3_read_rt(struct file *file, char __user *ubuf, size_t count, + loff_t *ppos) +{ + int i = 0; + struct ipa3_rt_tbl *tbl; + struct ipa3_rt_entry *entry; + struct ipa3_rt_tbl_set *set; + enum ipa_ip_type ip = (enum ipa_ip_type)file->private_data; + u32 ofst; + u32 ofst_words; + + set = &ipa3_ctx->rt_tbl_set[ip]; + + mutex_lock(&ipa3_ctx->lock); + + pr_err("==== Routing Tables Start ====\n"); + if (ipa3_ctx->rt_tbl_hash_lcl[ip]) + pr_err("Hashable table resides on local memory\n"); + else + pr_err("Hashable table resides on system (ddr) memory\n"); + if (ipa3_ctx->rt_tbl_nhash_lcl[ip]) + pr_err("Non-Hashable table resides on local memory\n"); + else + pr_err("Non-Hashable table resides on system (ddr) memory\n"); + + list_for_each_entry(tbl, &set->head_rt_tbl_list, link) { + i = 0; + list_for_each_entry(entry, &tbl->head_rt_rule_list, link) { + pr_err("tbl_idx:%d tbl_name:%s tbl_ref:%u ", + entry->tbl->idx, entry->tbl->name, + entry->tbl->ref_cnt); + if (entry->proc_ctx && + (!ipa3_check_idr_if_freed(entry->proc_ctx))) { + ofst = entry->proc_ctx->offset_entry->offset; + ofst_words = + (ofst + + ipa3_ctx->hdr_proc_ctx_tbl.start_offset) + >> 5; + pr_err("rule_idx:%d dst:%d ep:%d S:%u ", + i, entry->rule.dst, + ipa_get_ep_mapping(entry->rule.dst), + !ipa3_ctx->hdr_proc_ctx_tbl_lcl); + pr_err("proc_ctx[32B]:%u attrib_mask:%08x ", + ofst_words, + entry->rule.attrib.attrib_mask); + } else { + if (entry->hdr) + ofst = entry->hdr->offset_entry->offset; + else + ofst = 0; + pr_err("rule_idx:%d dst:%d ep:%d S:%u ", + i, entry->rule.dst, + ipa_get_ep_mapping(entry->rule.dst), + !(entry->hdr && entry->hdr->is_lcl)); + pr_err("hdr_ofst[words]:%u attrib_mask:%08x ", + ofst >> 2, + entry->rule.attrib.attrib_mask); + } + pr_err("rule_id:%u max_prio:%u prio:%u ", + entry->rule_id, entry->rule.max_prio, + entry->prio); + pr_err("enable_stats:%u counter_id:%u ", + entry->rule.enable_stats, + entry->rule.cnt_idx); + pr_err("hashable:%u retain_hdr:%u ", + entry->rule.hashable, + entry->rule.retain_hdr); + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0) + pr_err("close_aggr_irq_mod: %u\n", + entry->rule.close_aggr_irq_mod); + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_5) + pr_err("ttl_update: %u\n", entry->rule.ttl_update); + + ipa3_attrib_dump(&entry->rule.attrib, ip); + i++; + } + } + pr_err("==== Routing Tables End ====\n"); + mutex_unlock(&ipa3_ctx->lock); + + return 0; +} + +static ssize_t ipa3_read_rt_hw(struct file *file, char __user *ubuf, + size_t count, loff_t *ppos) +{ + enum ipa_ip_type ip = (enum ipa_ip_type)file->private_data; + int tbls_num; + int rules_num; + int tbl; + int rl; + int res = 0; + struct ipahal_rt_rule_entry *rules = NULL; + + switch (ip) { + case IPA_IP_v4: + tbls_num = IPA_MEM_PART(v4_rt_num_index); + break; + case IPA_IP_v6: + tbls_num = IPA_MEM_PART(v6_rt_num_index); + break; + default: + IPAERR("ip type error %d\n", ip); + return -EINVAL; + } + + IPADBG("Tring to parse %d H/W routing tables - IP=%d\n", tbls_num, ip); + + rules = kzalloc(sizeof(*rules) * IPA_DBG_MAX_RULE_IN_TBL, GFP_KERNEL); + if (!rules) { + IPAERR("failed to allocate mem for tbl rules\n"); + return -ENOMEM; + } + + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + mutex_lock(&ipa3_ctx->lock); + + for (tbl = 0 ; tbl < tbls_num ; tbl++) { + pr_err("=== Routing Table %d = Hashable Rules ===\n", tbl); + rules_num = IPA_DBG_MAX_RULE_IN_TBL; + res = ipa3_rt_read_tbl_from_hw(tbl, ip, true, rules, + &rules_num); + if (res) { + pr_err("ERROR - Check the logs\n"); + IPAERR("failed reading tbl from hw\n"); + goto bail; + } + if (!rules_num) + pr_err("-->No rules. Empty tbl or modem system table\n"); + + for (rl = 0 ; rl < rules_num ; rl++) { + pr_err("rule_idx:%d dst ep:%d L:%u ", + rl, rules[rl].dst_pipe_idx, rules[rl].hdr_lcl); + + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0) + pr_err("close_aggr_irq_mod: %u ", + rules[rl].close_aggr_irq_mod); + + if (rules[rl].hdr_type == IPAHAL_RT_RULE_HDR_PROC_CTX) + pr_err("proc_ctx:%u attrib_mask:%08x ", + rules[rl].hdr_ofst, + rules[rl].eq_attrib.rule_eq_bitmap); + else + pr_err("hdr_ofst:%u attrib_mask:%08x ", + rules[rl].hdr_ofst, + rules[rl].eq_attrib.rule_eq_bitmap); + + pr_err("rule_id:%u cnt_id:%hhu prio:%u retain_hdr:%u\n", + rules[rl].id, rules[rl].cnt_idx, + rules[rl].priority, rules[rl].retain_hdr); + res = ipa3_attrib_dump_eq(&rules[rl].eq_attrib); + if (res) { + IPAERR_RL("failed read attrib eq\n"); + goto bail; + } + } + + pr_err("=== Routing Table %d = Non-Hashable Rules ===\n", tbl); + rules_num = IPA_DBG_MAX_RULE_IN_TBL; + res = ipa3_rt_read_tbl_from_hw(tbl, ip, false, rules, + &rules_num); + if (res) { + pr_err("ERROR - Check the logs\n"); + IPAERR("failed reading tbl from hw\n"); + goto bail; + } + if (!rules_num) + pr_err("-->No rules. Empty tbl or modem system table\n"); + + for (rl = 0 ; rl < rules_num ; rl++) { + pr_err("rule_idx:%d dst ep:%d L:%u ", + rl, rules[rl].dst_pipe_idx, rules[rl].hdr_lcl); + + if (rules[rl].hdr_type == IPAHAL_RT_RULE_HDR_PROC_CTX) + pr_err("proc_ctx:%u attrib_mask:%08x ", + rules[rl].hdr_ofst, + rules[rl].eq_attrib.rule_eq_bitmap); + else + pr_err("hdr_ofst:%u attrib_mask:%08x ", + rules[rl].hdr_ofst, + rules[rl].eq_attrib.rule_eq_bitmap); + + pr_err("rule_id:%u cnt_id:%hhu prio:%u retain_hdr:%u\n", + rules[rl].id, rules[rl].cnt_idx, + rules[rl].priority, rules[rl].retain_hdr); + res = ipa3_attrib_dump_eq(&rules[rl].eq_attrib); + if (res) { + IPAERR_RL("failed read attrib eq\n"); + goto bail; + } + } + pr_err("\n"); + } + +bail: + mutex_unlock(&ipa3_ctx->lock); + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + kfree(rules); + return res; +} + +static ssize_t ipa3_read_proc_ctx(struct file *file, char __user *ubuf, + size_t count, loff_t *ppos) +{ + int nbytes = 0; + struct ipa3_hdr_proc_ctx_tbl *tbl; + struct ipa3_hdr_proc_ctx_entry *entry; + u32 ofst_words; + + tbl = &ipa3_ctx->hdr_proc_ctx_tbl; + + mutex_lock(&ipa3_ctx->lock); + + if (ipa3_ctx->hdr_proc_ctx_tbl_lcl) + pr_info("Table resides on local memory\n"); + else + pr_info("Table resides on system(ddr) memory\n"); + + list_for_each_entry(entry, &tbl->head_proc_ctx_entry_list, link) { + ofst_words = (entry->offset_entry->offset + + ipa3_ctx->hdr_proc_ctx_tbl.start_offset) + >> 5; + nbytes += scnprintf(dbg_buff + nbytes, + IPA_MAX_MSG_LEN - nbytes, + "id:%u hdr_proc_type:%s proc_ctx[32B]:%u ", + entry->id, + ipa3_hdr_proc_type_name[entry->type], + ofst_words); + nbytes += scnprintf(dbg_buff + nbytes, + IPA_MAX_MSG_LEN - nbytes, + "hdr[words]:%u\n", + entry->hdr->offset_entry->offset >> 2); + } + mutex_unlock(&ipa3_ctx->lock); + + return simple_read_from_buffer(ubuf, count, ppos, dbg_buff, nbytes); +} + +static ssize_t ipa3_read_flt(struct file *file, char __user *ubuf, size_t count, + loff_t *ppos) +{ + int i; + int j; + struct ipa3_flt_tbl *tbl; + struct ipa3_flt_entry *entry; + enum ipa_ip_type ip = (enum ipa_ip_type)file->private_data; + struct ipa3_rt_tbl *rt_tbl; + u32 rt_tbl_idx; + u32 bitmap; + bool eq; + int res = 0; + + mutex_lock(&ipa3_ctx->lock); + + pr_err("==== Filtering Tables Start ====\n"); + if (ipa3_ctx->flt_tbl_hash_lcl[ip]) + pr_err("Hashable table resides on local memory\n"); + else + pr_err("Hashable table resides on system (ddr) memory\n"); + if (ipa3_ctx->flt_tbl_nhash_lcl[ip]) + pr_err("Non-Hashable table resides on local memory\n"); + else + pr_err("Non-Hashable table resides on system (ddr) memory\n"); + + for (j = 0; j < ipa3_ctx->ipa_num_pipes; j++) { + if (!ipa_is_ep_support_flt(j)) + continue; + tbl = &ipa3_ctx->flt_tbl[j][ip]; + i = 0; + list_for_each_entry(entry, &tbl->head_flt_rule_list, link) { + if (entry->cookie != IPA_FLT_COOKIE) + continue; + if (entry->rule.eq_attrib_type) { + rt_tbl_idx = entry->rule.rt_tbl_idx; + bitmap = entry->rule.eq_attrib.rule_eq_bitmap; + eq = true; + } else { + rt_tbl = ipa3_id_find(entry->rule.rt_tbl_hdl); + if (rt_tbl == NULL || + rt_tbl->cookie != IPA_RT_TBL_COOKIE) + rt_tbl_idx = ~0; + else + rt_tbl_idx = rt_tbl->idx; + bitmap = entry->rule.attrib.attrib_mask; + eq = false; + } + pr_err("ep_idx:%d rule_idx:%d act:%d rt_tbl_idx:%d ", + j, i, entry->rule.action, rt_tbl_idx); + pr_err("attrib_mask:%08x retain_hdr:%d eq:%d ", + bitmap, entry->rule.retain_hdr, eq); + pr_err("hashable:%u rule_id:%u max_prio:%u prio:%u ", + entry->rule.hashable, entry->rule_id, + entry->rule.max_prio, entry->prio); + if (entry->rule.hashable) + pr_err("hash in_sys_preffer:%d, force: %d ", + tbl->in_sys[IPA_RULE_HASHABLE], + tbl->force_sys[IPA_RULE_HASHABLE]); + else + pr_err("non-hash in_sys_preffer:%d, force: %d ", + tbl->in_sys[IPA_RULE_NON_HASHABLE], + tbl->force_sys[IPA_RULE_NON_HASHABLE]); + pr_err("enable_stats:%u counter_id:%u\n", + entry->rule.enable_stats, + entry->rule.cnt_idx); + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_0) + pr_err("pdn index %d, set metadata %d ", + entry->rule.pdn_idx, + entry->rule.set_metadata); + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0) + pr_err("close_aggr_irq_mod %u ", + entry->rule.close_aggr_irq_mod); + if (eq) { + res = ipa3_attrib_dump_eq( + &entry->rule.eq_attrib); + if (res) { + IPAERR_RL("failed read attrib eq\n"); + goto bail; + } + } else + ipa3_attrib_dump( + &entry->rule.attrib, ip); + i++; + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_5) + pr_err("ttl_update %u ", entry->rule.ttl_update); + } + } +bail: + pr_err("==== Filtering Tables End ====\n"); + mutex_unlock(&ipa3_ctx->lock); + + return res; +} + +static ssize_t ipa3_read_flt_hw(struct file *file, char __user *ubuf, + size_t count, loff_t *ppos) +{ + int pipe; + int rl; + int rules_num; + struct ipahal_flt_rule_entry *rules; + enum ipa_ip_type ip = (enum ipa_ip_type)file->private_data; + u32 rt_tbl_idx; + u32 bitmap; + int res = 0; + + IPADBG("Tring to parse %d H/W filtering tables - IP=%d\n", + ipa3_ctx->ep_flt_num, ip); + + rules = kzalloc(sizeof(*rules) * IPA_DBG_MAX_RULE_IN_TBL, GFP_KERNEL); + if (!rules) + return -ENOMEM; + + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + mutex_lock(&ipa3_ctx->lock); + + if (ipa3_ctx->flt_tbl_hash_lcl[ip]) + pr_err("Hashable table resides on local memory\n"); + else + pr_err("Hashable table resides on system (ddr) memory\n"); + if (ipa3_ctx->flt_tbl_nhash_lcl[ip]) + pr_err("Non-Hashable table resides on local memory\n"); + else + pr_err("Non-Hashable table resides on system (ddr) memory\n"); + + for (pipe = 0; pipe < ipa3_ctx->ipa_num_pipes; pipe++) { + if (!ipa_is_ep_support_flt(pipe)) + continue; + pr_err("=== Filtering Table ep:%d = Hashable Rules ===\n", + pipe); + rules_num = IPA_DBG_MAX_RULE_IN_TBL; + res = ipa3_flt_read_tbl_from_hw(pipe, ip, true, rules, + &rules_num); + if (res) { + pr_err("ERROR - Check the logs\n"); + IPAERR("failed reading tbl from hw\n"); + goto bail; + } + if (!rules_num) + pr_err("-->No rules. Empty tbl or modem sys table\n"); + + for (rl = 0; rl < rules_num; rl++) { + rt_tbl_idx = rules[rl].rule.rt_tbl_idx; + bitmap = rules[rl].rule.eq_attrib.rule_eq_bitmap; + pr_err("ep_idx:%d rule_idx:%d act:%d rt_tbl_idx:%d ", + pipe, rl, rules[rl].rule.action, rt_tbl_idx); + pr_err("attrib_mask:%08x retain_hdr:%d ", + bitmap, rules[rl].rule.retain_hdr); + pr_err("rule_id:%u cnt_id:%hhu prio:%u\n", + rules[rl].id, rules[rl].cnt_idx, + rules[rl].priority); + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0) + pr_err("close_aggr_irq_mod %u\n", + rules[rl].rule.close_aggr_irq_mod); + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_0) + pr_err("pdn: %u, set_metadata: %u ", + rules[rl].rule.pdn_idx, + rules[rl].rule.set_metadata); + res = ipa3_attrib_dump_eq(&rules[rl].rule.eq_attrib); + if (res) { + IPAERR_RL("failed read attrib eq\n"); + goto bail; + } + } + + pr_err("=== Filtering Table ep:%d = Non-Hashable Rules ===\n", + pipe); + rules_num = IPA_DBG_MAX_RULE_IN_TBL; + res = ipa3_flt_read_tbl_from_hw(pipe, ip, false, rules, + &rules_num); + if (res) { + IPAERR("failed reading tbl from hw\n"); + goto bail; + } + if (!rules_num) + pr_err("-->No rules. Empty tbl or modem sys table\n"); + for (rl = 0; rl < rules_num; rl++) { + rt_tbl_idx = rules[rl].rule.rt_tbl_idx; + bitmap = rules[rl].rule.eq_attrib.rule_eq_bitmap; + pr_err("ep_idx:%d rule_idx:%d act:%d rt_tbl_idx:%d ", + pipe, rl, rules[rl].rule.action, rt_tbl_idx); + pr_err("attrib_mask:%08x retain_hdr:%d ", + bitmap, rules[rl].rule.retain_hdr); + pr_err("rule_id:%u cnt_id:%hhu prio:%u\n", + rules[rl].id, rules[rl].cnt_idx, + rules[rl].priority); + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0) + pr_err("close_aggr_irq_mod %u\n", + rules[rl].rule.close_aggr_irq_mod); + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_0) + pr_err("pdn: %u, set_metadata: %u ", + rules[rl].rule.pdn_idx, + rules[rl].rule.set_metadata); + res = ipa3_attrib_dump_eq(&rules[rl].rule.eq_attrib); + if (res) { + IPAERR_RL("failed read attrib eq\n"); + goto bail; + } + } + pr_err("\n"); + } + +bail: + mutex_unlock(&ipa3_ctx->lock); + kfree(rules); + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + return res; +} + +static ssize_t ipa3_read_stats(struct file *file, char __user *ubuf, + size_t count, loff_t *ppos) +{ + int nbytes; + int i; + int cnt = 0; + uint connect = 0; + + for (i = 0; i < ipa3_ctx->ipa_num_pipes; i++) + connect |= (ipa3_ctx->ep[i].valid << i); + + nbytes = scnprintf(dbg_buff, IPA_MAX_MSG_LEN, + "sw_tx=%u\n" + "hw_tx=%u\n" + "tx_non_linear=%u\n" + "tx_compl=%u\n" + "wan_rx=%u\n" + "stat_compl=%u\n" + "lan_aggr_close=%u\n" + "wan_aggr_close=%u\n" + "act_clnt=%u\n" + "con_clnt_bmap=0x%x\n" + "wan_rx_empty=%u\n" + "wan_rx_empty_coal=%u\n" + "wan_repl_rx_empty=%u\n" + "rmnet_ll_rx_empty=%u\n" + "rmnet_ll_repl_rx_empty=%u\n" + "lan_rx_empty=%u\n" + "lan_repl_rx_empty=%u\n" + "flow_enable=%u\n" + "flow_disable=%u\n" + "rx_page_drop_cnt=%u\n" + "lower_order=%u\n" + "rmnet_notifier_enabled=%u\n" + "num_buff_above_thresh_for_def_pipe_notified=%u\n" + "num_buff_below_thresh_for_def_pipe_notified=%u\n" + "num_buff_above_thresh_for_coal_pipe_notified=%u\n" + "num_buff_below_thresh_for_coal_pipe_notified=%u\n" + "num_buff_above_thresh_for_ll_pipe_notified=%u\n" + "num_buff_below_thresh_for_ll_pipe_notified=%u\n" + "num_free_page_task_scheduled=%u\n" + "pipe_setup_fail_cnt=%u\n" + "ttl_count=%u\n", + ipa3_ctx->stats.tx_sw_pkts, + ipa3_ctx->stats.tx_hw_pkts, + ipa3_ctx->stats.tx_non_linear, + ipa3_ctx->stats.tx_pkts_compl, + ipa3_ctx->stats.rx_pkts, + ipa3_ctx->stats.stat_compl, + ipa3_ctx->stats.aggr_close, + ipa3_ctx->stats.wan_aggr_close, + atomic_read(&ipa3_ctx->ipa3_active_clients.cnt), + connect, + ipa3_ctx->stats.wan_rx_empty, + ipa3_ctx->stats.wan_rx_empty_coal, + ipa3_ctx->stats.wan_repl_rx_empty, + ipa3_ctx->stats.rmnet_ll_rx_empty, + ipa3_ctx->stats.rmnet_ll_repl_rx_empty, + ipa3_ctx->stats.lan_rx_empty, + ipa3_ctx->stats.lan_repl_rx_empty, + ipa3_ctx->stats.flow_enable, + ipa3_ctx->stats.flow_disable, + ipa3_ctx->stats.rx_page_drop_cnt, + ipa3_ctx->stats.lower_order, + ipa3_ctx->ipa_rmnet_notifier_enabled, + atomic_read(&ipa3_ctx->stats.num_buff_above_thresh_for_def_pipe_notified), + atomic_read(&ipa3_ctx->stats.num_buff_below_thresh_for_def_pipe_notified), + atomic_read(&ipa3_ctx->stats.num_buff_above_thresh_for_coal_pipe_notified), + atomic_read(&ipa3_ctx->stats.num_buff_below_thresh_for_coal_pipe_notified), + atomic_read(&ipa3_ctx->stats.num_buff_above_thresh_for_ll_pipe_notified), + atomic_read(&ipa3_ctx->stats.num_buff_below_thresh_for_ll_pipe_notified), + atomic_read(&ipa3_ctx->stats.num_free_page_task_scheduled), + ipa3_ctx->stats.pipe_setup_fail_cnt, + ipa3_ctx->stats.ttl_cnt + ); + cnt += nbytes; + + for (i = 0; i < IPAHAL_PKT_STATUS_EXCEPTION_MAX; i++) { + nbytes = scnprintf(dbg_buff + cnt, + IPA_MAX_MSG_LEN - cnt, + "lan_rx_excp[%u:%20s]=%u\n", i, + ipahal_pkt_status_exception_str(i), + ipa3_ctx->stats.rx_excp_pkts[i]); + cnt += nbytes; + } + + return simple_read_from_buffer(ubuf, count, ppos, dbg_buff, cnt); +} + +static ssize_t ipa3_read_odlstats(struct file *file, char __user *ubuf, + size_t count, loff_t *ppos) +{ + int nbytes; + int cnt = 0; + + nbytes = scnprintf(dbg_buff, IPA_MAX_MSG_LEN, + "ODL received pkt =%u\n" + "ODL processed pkt to DIAG=%u\n" + "ODL dropped pkt =%u\n" + "ODL packet in queue =%u\n", + ipa3_odl_ctx->stats.odl_rx_pkt, + ipa3_odl_ctx->stats.odl_tx_diag_pkt, + ipa3_odl_ctx->stats.odl_drop_pkt, + atomic_read(&ipa3_odl_ctx->stats.numer_in_queue)); + + cnt += nbytes; + + return simple_read_from_buffer(ubuf, count, ppos, dbg_buff, cnt); +} + + +static ssize_t ipa3_read_page_recycle_stats(struct file *file, + char __user *ubuf, size_t count, loff_t *ppos) +{ + int nbytes; + int cnt = 0, i = 0, k = 0; + + nbytes = scnprintf( + dbg_buff, IPA_MAX_MSG_LEN, + "COAL : Total number of packets replenished =%llu\n" + "COAL : Number of page recycled packets =%llu\n" + "COAL : Number of tmp alloc packets =%llu\n" + "COAL : Number of times tasklet scheduled =%llu\n" + + "DEF : Total number of packets replenished =%llu\n" + "DEF : Number of page recycled packets =%llu\n" + "DEF : Number of tmp alloc packets =%llu\n" + "DEF : Number of times tasklet scheduled =%llu\n" + + "COMMON : Number of page recycled in tasklet =%llu\n" + "COMMON : Number of times free pages not found in tasklet =%llu\n", + + ipa3_ctx->stats.page_recycle_stats[0].total_replenished, + ipa3_ctx->stats.page_recycle_stats[0].page_recycled, + ipa3_ctx->stats.page_recycle_stats[0].tmp_alloc, + ipa3_ctx->stats.num_sort_tasklet_sched[0], + + ipa3_ctx->stats.page_recycle_stats[1].total_replenished, + ipa3_ctx->stats.page_recycle_stats[1].page_recycled, + ipa3_ctx->stats.page_recycle_stats[1].tmp_alloc, + ipa3_ctx->stats.num_sort_tasklet_sched[1], + + ipa3_ctx->stats.page_recycle_cnt_in_tasklet, + ipa3_ctx->stats.num_of_times_wq_reschd); + + cnt += nbytes; + + for (k = 0; k < 2; k++) { + for (i = 0; i < ipa3_ctx->page_poll_threshold; i++) { + nbytes = scnprintf( + dbg_buff + cnt, IPA_MAX_MSG_LEN, + "COMMON : Page replenish efficiency[%d][%d] =%llu\n", + k, i, ipa3_ctx->stats.page_recycle_cnt[k][i]); + cnt += nbytes; + } + } + + return simple_read_from_buffer(ubuf, count, ppos, dbg_buff, cnt); +} + +static ssize_t ipa3_read_lan_coal_stats( + struct file *file, + char __user *ubuf, + size_t count, + loff_t *ppos) +{ + int nbytes=0, cnt=0; + u32 i; + char buf[1024]; + + *buf = '\0'; + + for ( i = 0; + i < sizeof(ipa3_ctx->stats.coal.coal_veid) / + sizeof(ipa3_ctx->stats.coal.coal_veid[0]); + i++ ) { + + nbytes += scnprintf( + buf + nbytes, + sizeof(buf) - nbytes, + "(%u/%llu) ", + i, + ipa3_ctx->stats.coal.coal_veid[i]); + } + + nbytes = scnprintf( + dbg_buff, IPA_MAX_MSG_LEN, + "LAN COAL rx = %llu\n" + "LAN COAL pkts = %llu\n" + "LAN COAL left as is = %llu\n" + "LAN COAL reconstructed = %llu\n" + "LAN COAL hdr qmap err = %llu\n" + "LAN COAL hdr nlo err = %llu\n" + "LAN COAL hdr pkt err = %llu\n" + "LAN COAL csum err = %llu\n" + + "LAN COAL ip invalid = %llu\n" + "LAN COAL trans invalid = %llu\n" + "LAN COAL tcp = %llu\n" + "LAN COAL tcp bytes = %llu\n" + "LAN COAL udp = %llu\n" + "LAN COAL udp bytes = %llu\n" + "LAN COAL (veid/cnt)...(veid/cnt) = %s\n", + + ipa3_ctx->stats.coal.coal_rx, + ipa3_ctx->stats.coal.coal_pkts, + ipa3_ctx->stats.coal.coal_left_as_is, + ipa3_ctx->stats.coal.coal_reconstructed, + ipa3_ctx->stats.coal.coal_hdr_qmap_err, + ipa3_ctx->stats.coal.coal_hdr_nlo_err, + ipa3_ctx->stats.coal.coal_hdr_pkt_err, + ipa3_ctx->stats.coal.coal_csum_err, + ipa3_ctx->stats.coal.coal_ip_invalid, + ipa3_ctx->stats.coal.coal_trans_invalid, + ipa3_ctx->stats.coal.coal_tcp, + ipa3_ctx->stats.coal.coal_tcp_bytes, + ipa3_ctx->stats.coal.coal_udp, + ipa3_ctx->stats.coal.coal_udp_bytes, + buf); + + cnt += nbytes; + + return simple_read_from_buffer(ubuf, count, ppos, dbg_buff, cnt); +} + +static ssize_t ipa3_read_cache_recycle_stats( + struct file *file, + char __user *ubuf, + size_t count, + loff_t *ppos) +{ + int nbytes; + int cnt = 0; + + nbytes = scnprintf(dbg_buff, IPA_MAX_MSG_LEN, + "COAL (cache) : Total number of pkts replenished =%llu\n" + "COAL (cache) : Number of pkts alloced =%llu\n" + "COAL (cache) : Number of pkts not alloced =%llu\n" + + "DEF (cache) : Total number of pkts replenished =%llu\n" + "DEF (cache) : Number of pkts alloced =%llu\n" + "DEF (cache) : Number of pkts not alloced =%llu\n" + + "OTHER (cache) : Total number of packets replenished =%llu\n" + "OTHER (cache) : Number of pkts alloced =%llu\n" + "OTHER (cache) : Number of pkts not alloced =%llu\n", + + ipa3_ctx->stats.cache_recycle_stats[0].tot_pkt_replenished, + ipa3_ctx->stats.cache_recycle_stats[0].pkt_allocd, + ipa3_ctx->stats.cache_recycle_stats[0].pkt_found, + + ipa3_ctx->stats.cache_recycle_stats[1].tot_pkt_replenished, + ipa3_ctx->stats.cache_recycle_stats[1].pkt_allocd, + ipa3_ctx->stats.cache_recycle_stats[1].pkt_found, + + ipa3_ctx->stats.cache_recycle_stats[2].tot_pkt_replenished, + ipa3_ctx->stats.cache_recycle_stats[2].pkt_allocd, + ipa3_ctx->stats.cache_recycle_stats[2].pkt_found); + + cnt += nbytes; + + return simple_read_from_buffer(ubuf, count, ppos, dbg_buff, cnt); +} + +static ssize_t ipa3_read_wstats(struct file *file, char __user *ubuf, + size_t count, loff_t *ppos) +{ + +#define HEAD_FRMT_STR "%25s\n" +#define FRMT_STR "%25s %10u\n" +#define FRMT_STR1 "%25s %10u\n\n" + + int cnt = 0; + int nbytes; + int ipa_ep_idx; + enum ipa_client_type client = IPA_CLIENT_WLAN1_PROD; + struct ipa3_ep_context *ep; + + do { + nbytes = scnprintf(dbg_buff + cnt, IPA_MAX_MSG_LEN - cnt, + HEAD_FRMT_STR, "Client IPA_CLIENT_WLAN1_PROD Stats:"); + cnt += nbytes; + + ipa_ep_idx = ipa_get_ep_mapping(client); + if (ipa_ep_idx == -1) { + nbytes = scnprintf(dbg_buff + cnt, + IPA_MAX_MSG_LEN - cnt, HEAD_FRMT_STR, "Not up"); + cnt += nbytes; + break; + } + + ep = &ipa3_ctx->ep[ipa_ep_idx]; + if (ep->valid != 1) { + nbytes = scnprintf(dbg_buff + cnt, + IPA_MAX_MSG_LEN - cnt, HEAD_FRMT_STR, "Not up"); + cnt += nbytes; + break; + } + + nbytes = scnprintf(dbg_buff + cnt, IPA_MAX_MSG_LEN - cnt, + FRMT_STR, "Avail Fifo Desc:", + atomic_read(&ep->avail_fifo_desc)); + cnt += nbytes; + + nbytes = scnprintf(dbg_buff + cnt, IPA_MAX_MSG_LEN - cnt, + FRMT_STR, "Rx Pkts Rcvd:", ep->wstats.rx_pkts_rcvd); + cnt += nbytes; + + nbytes = scnprintf(dbg_buff + cnt, IPA_MAX_MSG_LEN - cnt, + FRMT_STR, "Rx Pkts Status Rcvd:", + ep->wstats.rx_pkts_status_rcvd); + cnt += nbytes; + + nbytes = scnprintf(dbg_buff + cnt, IPA_MAX_MSG_LEN - cnt, + FRMT_STR, "Rx DH Rcvd:", ep->wstats.rx_hd_rcvd); + cnt += nbytes; + + nbytes = scnprintf(dbg_buff + cnt, IPA_MAX_MSG_LEN - cnt, + FRMT_STR, "Rx DH Processed:", + ep->wstats.rx_hd_processed); + cnt += nbytes; + + nbytes = scnprintf(dbg_buff + cnt, IPA_MAX_MSG_LEN - cnt, + FRMT_STR, "Rx DH Sent Back:", ep->wstats.rx_hd_reply); + cnt += nbytes; + + nbytes = scnprintf(dbg_buff + cnt, IPA_MAX_MSG_LEN - cnt, + FRMT_STR, "Rx Pkt Leak:", ep->wstats.rx_pkt_leak); + cnt += nbytes; + + nbytes = scnprintf(dbg_buff + cnt, IPA_MAX_MSG_LEN - cnt, + FRMT_STR1, "Rx DP Fail:", ep->wstats.rx_dp_fail); + cnt += nbytes; + + } while (0); + + client = IPA_CLIENT_WLAN1_CONS; + nbytes = scnprintf(dbg_buff + cnt, IPA_MAX_MSG_LEN - cnt, HEAD_FRMT_STR, + "Client IPA_CLIENT_WLAN1_CONS Stats:"); + cnt += nbytes; + while (1) { + ipa_ep_idx = ipa_get_ep_mapping(client); + if (ipa_ep_idx == -1) { + nbytes = scnprintf(dbg_buff + cnt, + IPA_MAX_MSG_LEN - cnt, HEAD_FRMT_STR, "Not up"); + cnt += nbytes; + goto nxt_clnt_cons; + } + + ep = &ipa3_ctx->ep[ipa_ep_idx]; + if (ep->valid != 1) { + nbytes = scnprintf(dbg_buff + cnt, + IPA_MAX_MSG_LEN - cnt, HEAD_FRMT_STR, "Not up"); + cnt += nbytes; + goto nxt_clnt_cons; + } + + nbytes = scnprintf(dbg_buff + cnt, IPA_MAX_MSG_LEN - cnt, + FRMT_STR, "Tx Pkts Received:", ep->wstats.tx_pkts_rcvd); + cnt += nbytes; + + nbytes = scnprintf(dbg_buff + cnt, IPA_MAX_MSG_LEN - cnt, + FRMT_STR, "Tx Pkts Sent:", ep->wstats.tx_pkts_sent); + cnt += nbytes; + + nbytes = scnprintf(dbg_buff + cnt, IPA_MAX_MSG_LEN - cnt, + FRMT_STR1, "Tx Pkts Dropped:", + ep->wstats.tx_pkts_dropped); + cnt += nbytes; + if (ep->sys) { + nbytes = scnprintf(dbg_buff + cnt, IPA_MAX_MSG_LEN - cnt, + FRMT_STR1, "sys len:", + ep->sys->len); + cnt += nbytes; + nbytes = scnprintf(dbg_buff + cnt, IPA_MAX_MSG_LEN - cnt, + FRMT_STR1, "rx_pool_sz:", + ep->sys->rx_pool_sz); + cnt += nbytes; + } + +nxt_clnt_cons: + switch (client) { + case IPA_CLIENT_WLAN1_CONS: + client = IPA_CLIENT_WLAN2_CONS; + nbytes = scnprintf(dbg_buff + cnt, + IPA_MAX_MSG_LEN - cnt, HEAD_FRMT_STR, + "Client IPA_CLIENT_WLAN2_CONS Stats:"); + cnt += nbytes; + continue; + case IPA_CLIENT_WLAN2_CONS: + client = IPA_CLIENT_WLAN2_CONS1; + nbytes = scnprintf(dbg_buff + cnt, + IPA_MAX_MSG_LEN - cnt, HEAD_FRMT_STR, + "Client IPA_CLIENT_WLAN2_CONS1 Stats:"); + cnt += nbytes; + continue; + case IPA_CLIENT_WLAN2_CONS1: + client = IPA_CLIENT_WLAN3_CONS; + nbytes = scnprintf(dbg_buff + cnt, + IPA_MAX_MSG_LEN - cnt, HEAD_FRMT_STR, + "Client IPA_CLIENT_WLAN3_CONS Stats:"); + cnt += nbytes; + continue; + case IPA_CLIENT_WLAN3_CONS: + client = IPA_CLIENT_WLAN4_CONS; + nbytes = scnprintf(dbg_buff + cnt, + IPA_MAX_MSG_LEN - cnt, HEAD_FRMT_STR, + "Client IPA_CLIENT_WLAN4_CONS Stats:"); + cnt += nbytes; + continue; + case IPA_CLIENT_WLAN4_CONS: + default: + break; + } + break; + } + + nbytes = scnprintf(dbg_buff + cnt, IPA_MAX_MSG_LEN - cnt, + "\n"HEAD_FRMT_STR, "All Wlan Consumer pipes stats:"); + cnt += nbytes; + + nbytes = scnprintf(dbg_buff + cnt, IPA_MAX_MSG_LEN - cnt, FRMT_STR, + "Tx Comm Buff Allocated:", + ipa3_ctx->wc_memb.wlan_comm_total_cnt); + cnt += nbytes; + + nbytes = scnprintf(dbg_buff + cnt, IPA_MAX_MSG_LEN - cnt, FRMT_STR, + "Tx Comm Buff Avail:", ipa3_ctx->wc_memb.wlan_comm_free_cnt); + cnt += nbytes; + + nbytes = scnprintf(dbg_buff + cnt, IPA_MAX_MSG_LEN - cnt, FRMT_STR1, + "Total Tx Pkts Freed:", ipa3_ctx->wc_memb.total_tx_pkts_freed); + cnt += nbytes; + + return simple_read_from_buffer(ubuf, count, ppos, dbg_buff, cnt); +} + +static ssize_t ipa3_read_ntn(struct file *file, char __user *ubuf, + size_t count, loff_t *ppos) +{ +#define TX_STATS(x, y) \ + stats.tx_ch_stats[x].y +#define RX_STATS(x, y) \ + stats.rx_ch_stats[x].y + + struct Ipa3HwStatsNTNInfoData_t stats; + int nbytes; + int cnt = 0, i = 0; + + if (!ipa3_get_ntn_stats(&stats)) { + for (i = 0; i < IPA_UC_MAX_NTN_TX_CHANNELS; i++) { + nbytes = scnprintf(dbg_buff + cnt, + IPA_MAX_MSG_LEN - cnt, + "TX%d num_pkts_psr=%u\n" + "TX%d ringFull=%u\n" + "TX%d ringEmpty=%u\n" + "TX%d ringUsageHigh=%u\n" + "TX%d ringUsageLow=%u\n" + "TX%d RingUtilCount=%u\n" + "TX%d bamFifoFull=%u\n" + "TX%d bamFifoEmpty=%u\n" + "TX%d bamFifoUsageHigh=%u\n" + "TX%d bamFifoUsageLow=%u\n" + "TX%d bamUtilCount=%u\n" + "TX%d num_db=%u\n" + "TX%d num_qmb_int_handled=%u\n" + "TX%d ipa_pipe_number=%u\n", + i, TX_STATS(i, num_pkts_processed), + i, TX_STATS(i, ring_stats.ringFull), + i, TX_STATS(i, ring_stats.ringEmpty), + i, TX_STATS(i, ring_stats.ringUsageHigh), + i, TX_STATS(i, ring_stats.ringUsageLow), + i, TX_STATS(i, ring_stats.RingUtilCount), + i, TX_STATS(i, gsi_stats.bamFifoFull), + i, TX_STATS(i, gsi_stats.bamFifoEmpty), + i, TX_STATS(i, gsi_stats.bamFifoUsageHigh), + i, TX_STATS(i, gsi_stats.bamFifoUsageLow), + i, TX_STATS(i, gsi_stats.bamUtilCount), + i, TX_STATS(i, num_db), + i, TX_STATS(i, num_qmb_int_handled), + i, TX_STATS(i, ipa_pipe_number)); + cnt += nbytes; + } + + for (i = 0; i < IPA_UC_MAX_NTN_RX_CHANNELS; i++) { + nbytes = scnprintf(dbg_buff + cnt, + IPA_MAX_MSG_LEN - cnt, + "RX%d num_pkts_psr=%u\n" + "RX%d ringFull=%u\n" + "RX%d ringEmpty=%u\n" + "RX%d ringUsageHigh=%u\n" + "RX%d ringUsageLow=%u\n" + "RX%d RingUtilCount=%u\n" + "RX%d bamFifoFull=%u\n" + "RX%d bamFifoEmpty=%u\n" + "RX%d bamFifoUsageHigh=%u\n" + "RX%d bamFifoUsageLow=%u\n" + "RX%d bamUtilCount=%u\n" + "RX%d num_db=%u\n" + "RX%d num_qmb_int_handled=%u\n" + "RX%d ipa_pipe_number=%u\n", + i, RX_STATS(i, num_pkts_processed), + i, RX_STATS(i, ring_stats.ringFull), + i, RX_STATS(i, ring_stats.ringEmpty), + i, RX_STATS(i, ring_stats.ringUsageHigh), + i, RX_STATS(i, ring_stats.ringUsageLow), + i, RX_STATS(i, ring_stats.RingUtilCount), + i, RX_STATS(i, gsi_stats.bamFifoFull), + i, RX_STATS(i, gsi_stats.bamFifoEmpty), + i, RX_STATS(i, gsi_stats.bamFifoUsageHigh), + i, RX_STATS(i, gsi_stats.bamFifoUsageLow), + i, RX_STATS(i, gsi_stats.bamUtilCount), + i, RX_STATS(i, num_db), + i, RX_STATS(i, num_qmb_int_handled), + i, RX_STATS(i, ipa_pipe_number)); + cnt += nbytes; + } + } else { + nbytes = scnprintf(dbg_buff, IPA_MAX_MSG_LEN, + "Fail to read NTN stats\n"); + cnt += nbytes; + } + + return simple_read_from_buffer(ubuf, count, ppos, dbg_buff, cnt); +} + +static ssize_t ipa3_read_wdi(struct file *file, char __user *ubuf, + size_t count, loff_t *ppos) +{ + struct IpaHwStatsWDIInfoData_t stats; + int nbytes; + int cnt = 0; + struct IpaHwStatsWDITxInfoData_t *tx_ch_ptr; + + if (!ipa_get_wdi_stats(&stats)) { + tx_ch_ptr = &stats.tx_ch_stats; + nbytes = scnprintf(dbg_buff, IPA_MAX_MSG_LEN, + "TX num_pkts_processed=%u\n" + "TX copy_engine_doorbell_value=%u\n" + "TX num_db_fired=%u\n" + "TX ringFull=%u\n" + "TX ringEmpty=%u\n" + "TX ringUsageHigh=%u\n" + "TX ringUsageLow=%u\n" + "TX RingUtilCount=%u\n" + "TX bamFifoFull=%u\n" + "TX bamFifoEmpty=%u\n" + "TX bamFifoUsageHigh=%u\n" + "TX bamFifoUsageLow=%u\n" + "TX bamUtilCount=%u\n" + "TX num_db=%u\n" + "TX num_unexpected_db=%u\n" + "TX num_bam_int_handled=%u\n" + "TX num_bam_int_in_non_running_state=%u\n" + "TX num_qmb_int_handled=%u\n" + "TX num_bam_int_handled_while_wait_for_bam=%u\n", + tx_ch_ptr->num_pkts_processed, + tx_ch_ptr->copy_engine_doorbell_value, + tx_ch_ptr->num_db_fired, + tx_ch_ptr->tx_comp_ring_stats.ringFull, + tx_ch_ptr->tx_comp_ring_stats.ringEmpty, + tx_ch_ptr->tx_comp_ring_stats.ringUsageHigh, + tx_ch_ptr->tx_comp_ring_stats.ringUsageLow, + tx_ch_ptr->tx_comp_ring_stats.RingUtilCount, + tx_ch_ptr->bam_stats.bamFifoFull, + tx_ch_ptr->bam_stats.bamFifoEmpty, + tx_ch_ptr->bam_stats.bamFifoUsageHigh, + tx_ch_ptr->bam_stats.bamFifoUsageLow, + tx_ch_ptr->bam_stats.bamUtilCount, + tx_ch_ptr->num_db, + tx_ch_ptr->num_unexpected_db, + tx_ch_ptr->num_bam_int_handled, + tx_ch_ptr->num_bam_int_in_non_running_state, + tx_ch_ptr->num_qmb_int_handled, + tx_ch_ptr->num_bam_int_handled_while_wait_for_bam); + cnt += nbytes; + nbytes = scnprintf(dbg_buff + cnt, IPA_MAX_MSG_LEN - cnt, + "RX max_outstanding_pkts=%u\n" + "RX num_pkts_processed=%u\n" + "RX rx_ring_rp_value=%u\n" + "RX ringFull=%u\n" + "RX ringEmpty=%u\n" + "RX ringUsageHigh=%u\n" + "RX ringUsageLow=%u\n" + "RX RingUtilCount=%u\n" + "RX bamFifoFull=%u\n" + "RX bamFifoEmpty=%u\n" + "RX bamFifoUsageHigh=%u\n" + "RX bamFifoUsageLow=%u\n" + "RX bamUtilCount=%u\n" + "RX num_bam_int_handled=%u\n" + "RX num_db=%u\n" + "RX num_unexpected_db=%u\n" + "RX num_pkts_in_dis_uninit_state=%u\n" + "RX num_ic_inj_vdev_change=%u\n" + "RX num_ic_inj_fw_desc_change=%u\n" + "RX num_qmb_int_handled=%u\n" + "RX reserved1=%u\n" + "RX reserved2=%u\n", + stats.rx_ch_stats.max_outstanding_pkts, + stats.rx_ch_stats.num_pkts_processed, + stats.rx_ch_stats.rx_ring_rp_value, + stats.rx_ch_stats.rx_ind_ring_stats.ringFull, + stats.rx_ch_stats.rx_ind_ring_stats.ringEmpty, + stats.rx_ch_stats.rx_ind_ring_stats.ringUsageHigh, + stats.rx_ch_stats.rx_ind_ring_stats.ringUsageLow, + stats.rx_ch_stats.rx_ind_ring_stats.RingUtilCount, + stats.rx_ch_stats.bam_stats.bamFifoFull, + stats.rx_ch_stats.bam_stats.bamFifoEmpty, + stats.rx_ch_stats.bam_stats.bamFifoUsageHigh, + stats.rx_ch_stats.bam_stats.bamFifoUsageLow, + stats.rx_ch_stats.bam_stats.bamUtilCount, + stats.rx_ch_stats.num_bam_int_handled, + stats.rx_ch_stats.num_db, + stats.rx_ch_stats.num_unexpected_db, + stats.rx_ch_stats.num_pkts_in_dis_uninit_state, + stats.rx_ch_stats.num_ic_inj_vdev_change, + stats.rx_ch_stats.num_ic_inj_fw_desc_change, + stats.rx_ch_stats.num_qmb_int_handled, + stats.rx_ch_stats.reserved1, + stats.rx_ch_stats.reserved2); + cnt += nbytes; + } else { + nbytes = scnprintf(dbg_buff, IPA_MAX_MSG_LEN, + "Fail to read WDI stats\n"); + cnt += nbytes; + } + + return simple_read_from_buffer(ubuf, count, ppos, dbg_buff, cnt); +} + +static ssize_t ipa3_write_dbg_cnt(struct file *file, const char __user *buf, + size_t count, loff_t *ppos) +{ + u32 option = 0; + struct ipahal_reg_debug_cnt_ctrl dbg_cnt_ctrl; + int ret; + + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_0) { + IPAERR("IPA_DEBUG_CNT_CTRL is not supported in IPA 4.0\n"); + return -EPERM; + } + + ret = kstrtou32_from_user(buf, count, 0, &option); + if (ret) + return ret; + + memset(&dbg_cnt_ctrl, 0, sizeof(dbg_cnt_ctrl)); + dbg_cnt_ctrl.type = DBG_CNT_TYPE_GENERAL; + dbg_cnt_ctrl.product = true; + dbg_cnt_ctrl.src_pipe = 0xff; + dbg_cnt_ctrl.rule_idx_pipe_rule = false; + dbg_cnt_ctrl.rule_idx = 0; + if (option == 1) + dbg_cnt_ctrl.en = true; + else + dbg_cnt_ctrl.en = false; + + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + ipahal_write_reg_n_fields(IPA_DEBUG_CNT_CTRL_n, 0, &dbg_cnt_ctrl); + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + + return count; +} + +static ssize_t ipa3_read_dbg_cnt(struct file *file, char __user *ubuf, + size_t count, loff_t *ppos) +{ + int nbytes; + u32 regval; + + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_0) { + IPAERR("IPA_DEBUG_CNT_REG is not supported in IPA 4.0\n"); + return -EPERM; + } + + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + regval = + ipahal_read_reg_n(IPA_DEBUG_CNT_REG_n, 0); + nbytes = scnprintf(dbg_buff, IPA_MAX_MSG_LEN, + "IPA_DEBUG_CNT_REG_0=0x%x\n", regval); + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + + return simple_read_from_buffer(ubuf, count, ppos, dbg_buff, nbytes); +} + +static ssize_t ipa3_read_msg(struct file *file, char __user *ubuf, + size_t count, loff_t *ppos) +{ + int nbytes; + int cnt = 0; + int i; + + for (i = 0; i < ARRAY_SIZE(ipa3_event_name); i++) { + nbytes = scnprintf(dbg_buff + cnt, IPA_MAX_MSG_LEN - cnt, + "msg[%u:%27s] W:%u R:%u\n", i, + ipa3_event_name[i], + ipa3_ctx->stats.msg_w[i], + ipa3_ctx->stats.msg_r[i]); + cnt += nbytes; + } + + return simple_read_from_buffer(ubuf, count, ppos, dbg_buff, cnt); +} + +static void ipa3_read_table( + char *table_addr, + u32 table_size, + u32 *total_num_entries, + u32 *rule_id, + enum ipahal_nat_type nat_type) +{ + int result; + char *entry; + size_t entry_size; + bool entry_zeroed; + bool entry_valid; + u32 i, num_entries = 0, id = *rule_id; + char *buff; + size_t buff_size = 2 * IPA_MAX_ENTRY_STRING_LEN; + + IPADBG("In\n"); + + if (table_addr == NULL) { + pr_err("NULL NAT table\n"); + goto bail; + } + + result = ipahal_nat_entry_size(nat_type, &entry_size); + + if (result) { + IPAERR("Failed to retrieve size of %s entry\n", + ipahal_nat_type_str(nat_type)); + goto bail; + } + + buff = kzalloc(buff_size, GFP_KERNEL); + + if (!buff) { + IPAERR("Out of memory\n"); + goto bail; + } + + for (i = 0, entry = table_addr; + i < table_size; + ++i, ++id, entry += entry_size) { + + result = ipahal_nat_is_entry_zeroed(nat_type, entry, + &entry_zeroed); + + if (result) { + IPAERR("Undefined if %s entry is zero\n", + ipahal_nat_type_str(nat_type)); + goto free_buf; + } + + if (entry_zeroed) + continue; + + result = ipahal_nat_is_entry_valid(nat_type, entry, + &entry_valid); + + if (result) { + IPAERR("Undefined if %s entry is valid\n", + ipahal_nat_type_str(nat_type)); + goto free_buf; + } + + if (entry_valid) { + ++num_entries; + pr_err("\tEntry_Index=%d\n", id); + } else + pr_err("\tEntry_Index=%d - Invalid Entry\n", id); + + ipahal_nat_stringify_entry(nat_type, entry, + buff, buff_size); + + pr_err("%s\n", buff); + + memset(buff, 0, buff_size); + } + + if (num_entries) + pr_err("\n"); + else + pr_err("\tEmpty\n\n"); + +free_buf: + kfree(buff); + *rule_id = id; + *total_num_entries += num_entries; + +bail: + IPADBG("Out\n"); +} + +static void ipa3_start_read_memory_device( + struct ipa3_nat_ipv6ct_common_mem *dev, + enum ipahal_nat_type nat_type, + u32 *num_ddr_ent_ptr, + u32 *num_sram_ent_ptr) +{ + u32 rule_id = 0; + + if (dev->is_ipv6ct_mem) { + + IPADBG("In: v6\n"); + + pr_err("%s_Table_Size=%d\n", + dev->name, dev->table_entries + 1); + + pr_err("%s_Expansion_Table_Size=%d\n", + dev->name, dev->expn_table_entries); + + pr_err("\n%s Base Table:\n", dev->name); + + if (dev->base_table_addr) + ipa3_read_table( + dev->base_table_addr, + dev->table_entries + 1, + num_ddr_ent_ptr, + &rule_id, + nat_type); + + pr_err("%s Expansion Table:\n", dev->name); + + if (dev->expansion_table_addr) + ipa3_read_table( + dev->expansion_table_addr, + dev->expn_table_entries, + num_ddr_ent_ptr, + &rule_id, + nat_type); + } + + if (dev->is_nat_mem) { + struct ipa3_nat_mem *nm_ptr = (struct ipa3_nat_mem *) dev; + struct ipa3_nat_mem_loc_data *mld_ptr = NULL; + u32 *num_ent_ptr; + const char *type_ptr; + + IPADBG("In: v4\n"); + + if (nm_ptr->active_table == IPA_NAT_MEM_IN_DDR && + nm_ptr->ddr_in_use) { + + mld_ptr = &nm_ptr->mem_loc[IPA_NAT_MEM_IN_DDR]; + num_ent_ptr = num_ddr_ent_ptr; + type_ptr = "DDR based table"; + } + + if (nm_ptr->active_table == IPA_NAT_MEM_IN_SRAM && + nm_ptr->sram_in_use) { + + mld_ptr = &nm_ptr->mem_loc[IPA_NAT_MEM_IN_SRAM]; + num_ent_ptr = num_sram_ent_ptr; + type_ptr = "SRAM based table"; + } + + if (mld_ptr) { + pr_err("(%s) %s_Table_Size=%d\n", + type_ptr, + dev->name, + mld_ptr->table_entries + 1); + + pr_err("(%s) %s_Expansion_Table_Size=%d\n", + type_ptr, + dev->name, + mld_ptr->expn_table_entries); + + pr_err("\n(%s) %s_Base Table:\n", + type_ptr, + dev->name); + + if (mld_ptr->base_table_addr) + ipa3_read_table( + mld_ptr->base_table_addr, + mld_ptr->table_entries + 1, + num_ent_ptr, + &rule_id, + nat_type); + + pr_err("(%s) %s_Expansion Table:\n", + type_ptr, + dev->name); + + if (mld_ptr->expansion_table_addr) + ipa3_read_table( + mld_ptr->expansion_table_addr, + mld_ptr->expn_table_entries, + num_ent_ptr, + &rule_id, + nat_type); + } + } + + IPADBG("Out\n"); +} + +static void ipa3_finish_read_memory_device( + struct ipa3_nat_ipv6ct_common_mem *dev, + u32 num_ddr_entries, + u32 num_sram_entries) +{ + IPADBG("In\n"); + + if (dev->is_ipv6ct_mem) { + pr_err("Overall number %s entries: %u\n\n", + dev->name, + num_ddr_entries); + } else { + struct ipa3_nat_mem *nm_ptr = (struct ipa3_nat_mem *) dev; + + if (num_ddr_entries) + pr_err("%s: Overall number of DDR entries: %u\n\n", + dev->name, + num_ddr_entries); + + if (num_sram_entries) + pr_err("%s: Overall number of SRAM entries: %u\n\n", + dev->name, + num_sram_entries); + + pr_err("%s: Driver focus changes to DDR(%u) to SRAM(%u)\n", + dev->name, + nm_ptr->switch2ddr_cnt, + nm_ptr->switch2sram_cnt); + } + + IPADBG("Out\n"); +} + +static void ipa3_read_pdn_table(void) +{ + int i, result; + char *pdn_entry; + size_t pdn_entry_size; + bool entry_zeroed; + bool entry_valid; + char *buff; + size_t buff_size = 128; + + IPADBG("In\n"); + + if (ipa3_ctx->nat_mem.pdn_mem.base) { + + result = ipahal_nat_entry_size( + IPAHAL_NAT_IPV4_PDN, &pdn_entry_size); + + if (result) { + IPAERR("Failed to retrieve size of PDN entry"); + goto bail; + } + + buff = kzalloc(buff_size, GFP_KERNEL); + if (!buff) { + IPAERR("Out of memory\n"); + goto bail; + } + + for (i = 0, pdn_entry = ipa3_ctx->nat_mem.pdn_mem.base; + i < ipa3_get_max_pdn(); + ++i, pdn_entry += pdn_entry_size) { + + result = ipahal_nat_is_entry_zeroed( + IPAHAL_NAT_IPV4_PDN, + pdn_entry, &entry_zeroed); + + if (result) { + IPAERR("ipahal_nat_is_entry_zeroed() fail\n"); + goto free; + } + + if (entry_zeroed) + continue; + + result = ipahal_nat_is_entry_valid( + IPAHAL_NAT_IPV4_PDN, + pdn_entry, &entry_valid); + + if (result) { + IPAERR( + "Failed to determine whether the PDN entry is valid\n"); + goto free; + } + + ipahal_nat_stringify_entry( + IPAHAL_NAT_IPV4_PDN, + pdn_entry, buff, buff_size); + + if (entry_valid) + pr_err("PDN %d: %s\n", i, buff); + else + pr_err("PDN %d - Invalid: %s\n", i, buff); + + memset(buff, 0, buff_size); + } + pr_err("\n"); +free: + kfree(buff); + } +bail: + IPADBG("Out\n"); +} + +static ssize_t ipa3_read_nat4( + struct file *file, + char __user *ubuf, + size_t count, + loff_t *ppos) +{ + struct ipa3_nat_ipv6ct_common_mem *dev = &ipa3_ctx->nat_mem.dev; + struct ipa3_nat_mem *nm_ptr = (struct ipa3_nat_mem *) dev; + struct ipa3_nat_mem_loc_data *mld_ptr = NULL; + + u32 rule_id = 0; + + u32 *num_ents_ptr; + u32 num_ddr_ents = 0; + u32 num_sram_ents = 0; + + u32 *num_index_ents_ptr; + u32 num_ddr_index_ents = 0; + u32 num_sram_index_ents = 0; + + const char *type_ptr; + + bool any_table_active = (nm_ptr->ddr_in_use || nm_ptr->sram_in_use); + + pr_err("==== NAT Tables Start ====\n"); + + if (!dev->is_dev_init) { + pr_err("NAT hasn't been initialized or not supported\n"); + goto ret; + } + + mutex_lock(&dev->lock); + + if (!dev->is_hw_init || !any_table_active) { + pr_err("NAT H/W and/or S/W not initialized\n"); + goto bail; + } + + if (nm_ptr->sram_in_use) { + IPADBG("SRAM based table with client 0, enable clk\n"); + IPA_ACTIVE_CLIENTS_INC_SPECIAL("SRAM"); + } + + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_0) { + ipa3_read_pdn_table(); + } else { + pr_err("NAT Table IP Address=%pI4h\n\n", + &ipa3_ctx->nat_mem.public_ip_addr); + } + + ipa3_start_read_memory_device( + dev, + IPAHAL_NAT_IPV4, + &num_ddr_ents, + &num_sram_ents); + + if (nm_ptr->active_table == IPA_NAT_MEM_IN_DDR && + nm_ptr->ddr_in_use) { + + mld_ptr = &nm_ptr->mem_loc[IPA_NAT_MEM_IN_DDR]; + num_ents_ptr = &num_ddr_ents; + num_index_ents_ptr = &num_ddr_index_ents; + type_ptr = "DDR based table"; + } + + if (nm_ptr->active_table == IPA_NAT_MEM_IN_SRAM && + nm_ptr->sram_in_use) { + + mld_ptr = &nm_ptr->mem_loc[IPA_NAT_MEM_IN_SRAM]; + num_ents_ptr = &num_sram_ents; + num_index_ents_ptr = &num_sram_index_ents; + type_ptr = "SRAM based table"; + } + + if (mld_ptr) { + /* Print Index tables */ + pr_err("(%s) ipaNatTable Index Table:\n", type_ptr); + + ipa3_read_table( + mld_ptr->index_table_addr, + mld_ptr->table_entries + 1, + num_index_ents_ptr, + &rule_id, + IPAHAL_NAT_IPV4_INDEX); + + pr_err("(%s) ipaNatTable Expansion Index Table:\n", type_ptr); + + ipa3_read_table( + mld_ptr->index_table_expansion_addr, + mld_ptr->expn_table_entries, + num_index_ents_ptr, + &rule_id, + IPAHAL_NAT_IPV4_INDEX); + + if (*num_ents_ptr != *num_index_ents_ptr) + IPAERR( + "(%s) Base Table vs Index Table entry count differs (%u vs %u)\n", + type_ptr, *num_ents_ptr, *num_index_ents_ptr); + } + + ipa3_finish_read_memory_device( + dev, + num_ddr_ents, + num_sram_ents); + + if (nm_ptr->sram_in_use) { + IPADBG("SRAM based table with client 0, disable clk\n"); + IPA_ACTIVE_CLIENTS_DEC_SPECIAL("SRAM"); + } + +bail: + pr_err("==== NAT Tables End ====\n"); + mutex_unlock(&dev->lock); + +ret: + IPADBG("Out\n"); + + return 0; +} + +static ssize_t ipa3_read_ipv6ct( + struct file *file, + char __user *ubuf, + size_t count, + loff_t *ppos) +{ + struct ipa3_nat_ipv6ct_common_mem *dev = &ipa3_ctx->ipv6ct_mem.dev; + + u32 num_ddr_ents, num_sram_ents; + + num_ddr_ents = num_sram_ents = 0; + + IPADBG("In\n"); + + pr_err("\n"); + + if (!dev->is_dev_init) { + pr_err("IPv6 Conntrack not initialized or not supported\n"); + goto bail; + } + + if (!dev->is_hw_init) { + pr_err("IPv6 connection tracking H/W hasn't been initialized\n"); + goto bail; + } + + mutex_lock(&dev->lock); + + ipa3_start_read_memory_device( + dev, + IPAHAL_NAT_IPV6CT, + &num_ddr_ents, + &num_sram_ents); + + ipa3_finish_read_memory_device( + dev, + num_ddr_ents, + num_sram_ents); + + mutex_unlock(&dev->lock); + +bail: + IPADBG("Out\n"); + + return 0; +} + +static ssize_t ipa3_pm_read_stats(struct file *file, char __user *ubuf, + size_t count, loff_t *ppos) +{ + int result, cnt = 0; + + result = ipa_pm_stat(dbg_buff, IPA_MAX_MSG_LEN); + if (result < 0) { + cnt += scnprintf(dbg_buff + cnt, IPA_MAX_MSG_LEN - cnt, + "Error in printing PM stat %d\n", result); + goto ret; + } + cnt += result; +ret: + return simple_read_from_buffer(ubuf, count, ppos, dbg_buff, cnt); +} + +static ssize_t ipa3_pm_ex_read_stats(struct file *file, char __user *ubuf, + size_t count, loff_t *ppos) +{ + int result, cnt = 0; + + result = ipa_pm_exceptions_stat(dbg_buff, IPA_MAX_MSG_LEN); + if (result < 0) { + cnt += scnprintf(dbg_buff + cnt, IPA_MAX_MSG_LEN - cnt, + "Error in printing PM stat %d\n", result); + goto ret; + } + cnt += result; +ret: + return simple_read_from_buffer(ubuf, count, ppos, dbg_buff, cnt); +} + +static ssize_t ipa3_read_ipahal_regs(struct file *file, char __user *ubuf, + size_t count, loff_t *ppos) +{ + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + ipahal_print_all_regs(true); + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + + return 0; +} + +static ssize_t ipa3_read_wdi_gsi_stats(struct file *file, + char __user *ubuf, size_t count, loff_t *ppos) +{ + struct ipa_uc_dbg_ring_stats stats; + int nbytes; + int cnt = 0; + + if (ipa3_ctx->ipa_hw_type < IPA_HW_v4_5) { + nbytes = scnprintf(dbg_buff, IPA_MAX_MSG_LEN, + "This feature only support on IPA4.5+\n"); + cnt += nbytes; + goto done; + } + + if (!ipa3_get_wdi_gsi_stats(&stats)) { + nbytes = scnprintf(dbg_buff, IPA_MAX_MSG_LEN, + "TX ringFull=%u\n" + "TX ringEmpty=%u\n" + "TX ringUsageHigh=%u\n" + "TX ringUsageLow=%u\n" + "TX RingUtilCount=%u\n", + stats.u.ring[1].ringFull, + stats.u.ring[1].ringEmpty, + stats.u.ring[1].ringUsageHigh, + stats.u.ring[1].ringUsageLow, + stats.u.ring[1].RingUtilCount); + cnt += nbytes; + nbytes = scnprintf(dbg_buff + cnt, IPA_MAX_MSG_LEN - cnt, + "RX ringFull=%u\n" + "RX ringEmpty=%u\n" + "RX ringUsageHigh=%u\n" + "RX ringUsageLow=%u\n" + "RX RingUtilCount=%u\n", + stats.u.ring[0].ringFull, + stats.u.ring[0].ringEmpty, + stats.u.ring[0].ringUsageHigh, + stats.u.ring[0].ringUsageLow, + stats.u.ring[0].RingUtilCount); + cnt += nbytes; + } else { + nbytes = scnprintf(dbg_buff, IPA_MAX_MSG_LEN, + "Fail to read WDI GSI stats\n"); + cnt += nbytes; + } +done: + return simple_read_from_buffer(ubuf, count, ppos, dbg_buff, cnt); +} + +static ssize_t ipa3_read_wdi3_gsi_stats(struct file *file, + char __user *ubuf, size_t count, loff_t *ppos) +{ + struct ipa_uc_dbg_ring_stats stats; + int nbytes; + int cnt = 0; + + if (ipa3_ctx->ipa_hw_type < IPA_HW_v4_5) { + nbytes = scnprintf(dbg_buff, IPA_MAX_MSG_LEN, + "This feature only support on IPA4.5+\n"); + cnt += nbytes; + goto done; + } + if (!ipa3_get_wdi3_gsi_stats(&stats)) { + nbytes = scnprintf(dbg_buff, IPA_MAX_MSG_LEN, + "TX ringFull=%u\n" + "TX ringEmpty=%u\n" + "TX ringUsageHigh=%u\n" + "TX ringUsageLow=%u\n" + "TX RingUtilCount=%u\n", + stats.u.ring[1].ringFull, + stats.u.ring[1].ringEmpty, + stats.u.ring[1].ringUsageHigh, + stats.u.ring[1].ringUsageLow, + stats.u.ring[1].RingUtilCount); + cnt += nbytes; + nbytes = scnprintf(dbg_buff + cnt, IPA_MAX_MSG_LEN - cnt, + "TX1 ringFull=%u\n" + "TX1 ringEmpty=%u\n" + "TX1 ringUsageHigh=%u\n" + "TX1 ringUsageLow=%u\n" + "TX1 RingUtilCount=%u\n", + stats.u.ring[2].ringFull, + stats.u.ring[2].ringEmpty, + stats.u.ring[2].ringUsageHigh, + stats.u.ring[2].ringUsageLow, + stats.u.ring[2].RingUtilCount); + cnt += nbytes; + nbytes = scnprintf(dbg_buff + cnt, IPA_MAX_MSG_LEN - cnt, + "RX ringFull=%u\n" + "RX ringEmpty=%u\n" + "RX ringUsageHigh=%u\n" + "RX ringUsageLow=%u\n" + "RX RingUtilCount=%u\n", + stats.u.ring[0].ringFull, + stats.u.ring[0].ringEmpty, + stats.u.ring[0].ringUsageHigh, + stats.u.ring[0].ringUsageLow, + stats.u.ring[0].RingUtilCount); + cnt += nbytes; + } else { + nbytes = scnprintf(dbg_buff, IPA_MAX_MSG_LEN, + "Fail to read WDI GSI stats\n"); + cnt += nbytes; + } + +done: + return simple_read_from_buffer(ubuf, count, ppos, dbg_buff, cnt); +} + +static ssize_t ipa3_read_11ad_gsi_stats(struct file *file, + char __user *ubuf, size_t count, loff_t *ppos) +{ + int nbytes; + int cnt = 0; + + if (ipa3_ctx->ipa_hw_type < IPA_HW_v4_5) { + nbytes = scnprintf(dbg_buff, IPA_MAX_MSG_LEN, + "This feature only support on IPA4.5+\n"); + cnt += nbytes; + goto done; + } + return 0; +done: + return simple_read_from_buffer(ubuf, count, ppos, dbg_buff, cnt); +} + +static ssize_t ipa3_read_aqc_gsi_stats(struct file *file, + char __user *ubuf, size_t count, loff_t *ppos) +{ + struct ipa_uc_dbg_ring_stats stats; + int nbytes; + int cnt = 0; + + if (ipa3_ctx->ipa_hw_type < IPA_HW_v4_5) { + nbytes = scnprintf(dbg_buff, IPA_MAX_MSG_LEN, + "This feature only support on IPA4.5+\n"); + cnt += nbytes; + goto done; + } + if (!ipa3_get_aqc_gsi_stats(&stats)) { + nbytes = scnprintf(dbg_buff, IPA_MAX_MSG_LEN, + "TX ringFull=%u\n" + "TX ringEmpty=%u\n" + "TX ringUsageHigh=%u\n" + "TX ringUsageLow=%u\n" + "TX RingUtilCount=%u\n", + stats.u.ring[1].ringFull, + stats.u.ring[1].ringEmpty, + stats.u.ring[1].ringUsageHigh, + stats.u.ring[1].ringUsageLow, + stats.u.ring[1].RingUtilCount); + cnt += nbytes; + nbytes = scnprintf(dbg_buff + cnt, IPA_MAX_MSG_LEN - cnt, + "RX ringFull=%u\n" + "RX ringEmpty=%u\n" + "RX ringUsageHigh=%u\n" + "RX ringUsageLow=%u\n" + "RX RingUtilCount=%u\n", + stats.u.ring[0].ringFull, + stats.u.ring[0].ringEmpty, + stats.u.ring[0].ringUsageHigh, + stats.u.ring[0].ringUsageLow, + stats.u.ring[0].RingUtilCount); + cnt += nbytes; + } else { + nbytes = scnprintf(dbg_buff, IPA_MAX_MSG_LEN, + "Fail to read AQC GSI stats\n"); + cnt += nbytes; + } +done: + return simple_read_from_buffer(ubuf, count, ppos, dbg_buff, cnt); +} + +static ssize_t ipa3_read_mhip_gsi_stats(struct file *file, + char __user *ubuf, size_t count, loff_t *ppos) +{ + struct ipa_uc_dbg_ring_stats stats; + int nbytes; + int cnt = 0; + + if (ipa3_ctx->ipa_hw_type < IPA_HW_v4_5) { + nbytes = scnprintf(dbg_buff, IPA_MAX_MSG_LEN, + "This feature only support on IPA4.5+\n"); + cnt += nbytes; + goto done; + } + if (!ipa3_get_mhip_gsi_stats(&stats)) { + nbytes = scnprintf(dbg_buff, IPA_MAX_MSG_LEN, + "IPA_CLIENT_MHI_PRIME_TETH_CONS ringFull=%u\n" + "IPA_CLIENT_MHI_PRIME_TETH_CONS ringEmpty=%u\n" + "IPA_CLIENT_MHI_PRIME_TETH_CONS ringUsageHigh=%u\n" + "IPA_CLIENT_MHI_PRIME_TETH_CONS ringUsageLow=%u\n" + "IPA_CLIENT_MHI_PRIME_TETH_CONS RingUtilCount=%u\n", + stats.u.ring[1].ringFull, + stats.u.ring[1].ringEmpty, + stats.u.ring[1].ringUsageHigh, + stats.u.ring[1].ringUsageLow, + stats.u.ring[1].RingUtilCount); + cnt += nbytes; + nbytes = scnprintf(dbg_buff + cnt, IPA_MAX_MSG_LEN - cnt, + "IPA_CLIENT_MHI_PRIME_TETH_PROD ringFull=%u\n" + "IPA_CLIENT_MHI_PRIME_TETH_PROD ringEmpty=%u\n" + "IPA_CLIENT_MHI_PRIME_TETH_PROD ringUsageHigh=%u\n" + "IPA_CLIENT_MHI_PRIME_TETH_PROD ringUsageLow=%u\n" + "IPA_CLIENT_MHI_PRIME_TETH_PROD RingUtilCount=%u\n", + stats.u.ring[0].ringFull, + stats.u.ring[0].ringEmpty, + stats.u.ring[0].ringUsageHigh, + stats.u.ring[0].ringUsageLow, + stats.u.ring[0].RingUtilCount); + cnt += nbytes; + nbytes = scnprintf(dbg_buff + cnt, IPA_MAX_MSG_LEN - cnt, + "IPA_CLIENT_MHI_PRIME_RMNET_CONS ringFull=%u\n" + "IPA_CLIENT_MHI_PRIME_RMNET_CONS ringEmpty=%u\n" + "IPA_CLIENT_MHI_PRIME_RMNET_CONS ringUsageHigh=%u\n" + "IPA_CLIENT_MHI_PRIME_RMNET_CONS ringUsageLow=%u\n" + "IPA_CLIENT_MHI_PRIME_RMNET_CONS RingUtilCount=%u\n", + stats.u.ring[3].ringFull, + stats.u.ring[3].ringEmpty, + stats.u.ring[3].ringUsageHigh, + stats.u.ring[3].ringUsageLow, + stats.u.ring[3].RingUtilCount); + cnt += nbytes; + nbytes = scnprintf(dbg_buff + cnt, IPA_MAX_MSG_LEN - cnt, + "IPA_CLIENT_MHI_PRIME_RMNET_PROD ringFull=%u\n" + "IPA_CLIENT_MHI_PRIME_RMNET_PROD ringEmpty=%u\n" + "IPA_CLIENT_MHI_PRIME_RMNET_PROD ringUsageHigh=%u\n" + "IPA_CLIENT_MHI_PRIME_RMNET_PROD ringUsageLow=%u\n" + "IPA_CLIENT_MHI_PRIME_RMNET_PROD RingUtilCount=%u\n", + stats.u.ring[2].ringFull, + stats.u.ring[2].ringEmpty, + stats.u.ring[2].ringUsageHigh, + stats.u.ring[2].ringUsageLow, + stats.u.ring[2].RingUtilCount); + cnt += nbytes; + } else { + nbytes = scnprintf(dbg_buff, IPA_MAX_MSG_LEN, + "Fail to read WDI GSI stats\n"); + cnt += nbytes; + } + +done: + return simple_read_from_buffer(ubuf, count, ppos, dbg_buff, cnt); +} + +static ssize_t ipa3_read_usb_gsi_stats(struct file *file, + char __user *ubuf, size_t count, loff_t *ppos) +{ + struct ipa_uc_dbg_ring_stats stats; + int nbytes; + int cnt = 0; + + if (ipa3_ctx->ipa_hw_type < IPA_HW_v4_5) { + nbytes = scnprintf(dbg_buff, IPA_MAX_MSG_LEN, + "This feature only support on IPA4.5+\n"); + cnt += nbytes; + goto done; + } + if (!ipa3_get_usb_gsi_stats(&stats)) { + nbytes = scnprintf(dbg_buff, IPA_MAX_MSG_LEN, + "TX ringFull=%u\n" + "TX ringEmpty=%u\n" + "TX ringUsageHigh=%u\n" + "TX ringUsageLow=%u\n" + "TX RingUtilCount=%u\n", + stats.u.ring[1].ringFull, + stats.u.ring[1].ringEmpty, + stats.u.ring[1].ringUsageHigh, + stats.u.ring[1].ringUsageLow, + stats.u.ring[1].RingUtilCount); + cnt += nbytes; + nbytes = scnprintf(dbg_buff + cnt, IPA_MAX_MSG_LEN - cnt, + "RX ringFull=%u\n" + "RX ringEmpty=%u\n" + "RX ringUsageHigh=%u\n" + "RX ringUsageLow=%u\n" + "RX RingUtilCount=%u\n", + stats.u.ring[0].ringFull, + stats.u.ring[0].ringEmpty, + stats.u.ring[0].ringUsageHigh, + stats.u.ring[0].ringUsageLow, + stats.u.ring[0].RingUtilCount); + cnt += nbytes; + } else { + nbytes = scnprintf(dbg_buff, IPA_MAX_MSG_LEN, + "Fail to read WDI GSI stats\n"); + cnt += nbytes; + } + +done: + return simple_read_from_buffer(ubuf, count, ppos, dbg_buff, cnt); +} + +static ssize_t ipa3_read_app_clk_vote( + struct file *file, + char __user *ubuf, + size_t count, + loff_t *ppos) +{ + int cnt = + scnprintf( + dbg_buff, + IPA_MAX_MSG_LEN, + "%u\n", + ipa3_ctx->app_clock_vote.cnt); + + return simple_read_from_buffer(ubuf, count, ppos, dbg_buff, cnt); +} + +static void ipa_dump_status(struct ipahal_pkt_status *status) +{ + IPA_DUMP_STATUS_FIELD(status_opcode); + IPA_DUMP_STATUS_FIELD(exception); + IPA_DUMP_STATUS_FIELD(status_mask); + IPA_DUMP_STATUS_FIELD(pkt_len); + IPA_DUMP_STATUS_FIELD(endp_src_idx); + IPA_DUMP_STATUS_FIELD(endp_dest_idx); + IPA_DUMP_STATUS_FIELD(metadata); + IPA_DUMP_STATUS_FIELD(flt_local); + IPA_DUMP_STATUS_FIELD(flt_hash); + IPA_DUMP_STATUS_FIELD(flt_global); + IPA_DUMP_STATUS_FIELD(flt_ret_hdr); + IPA_DUMP_STATUS_FIELD(flt_miss); + IPA_DUMP_STATUS_FIELD(flt_rule_id); + IPA_DUMP_STATUS_FIELD(rt_local); + IPA_DUMP_STATUS_FIELD(rt_hash); + IPA_DUMP_STATUS_FIELD(ucp); + IPA_DUMP_STATUS_FIELD(rt_tbl_idx); + IPA_DUMP_STATUS_FIELD(rt_miss); + IPA_DUMP_STATUS_FIELD(rt_rule_id); + IPA_DUMP_STATUS_FIELD(nat_hit); + IPA_DUMP_STATUS_FIELD(nat_entry_idx); + IPA_DUMP_STATUS_FIELD(nat_type); + pr_err("tag = 0x%llx\n", (u64)status->tag_info & 0xFFFFFFFFFFFF); + IPA_DUMP_STATUS_FIELD(seq_num); + IPA_DUMP_STATUS_FIELD(time_of_day_ctr); + IPA_DUMP_STATUS_FIELD(hdr_local); + IPA_DUMP_STATUS_FIELD(hdr_offset); + IPA_DUMP_STATUS_FIELD(frag_hit); + IPA_DUMP_STATUS_FIELD(frag_rule); + IPA_DUMP_STATUS_FIELD(ttl_dec); +} + +static ssize_t ipa_status_stats_read(struct file *file, char __user *ubuf, + size_t count, loff_t *ppos) +{ + struct ipa3_status_stats *stats; + int i, j; + + stats = kzalloc(sizeof(*stats), GFP_KERNEL); + if (!stats) + return -EFAULT; + + for (i = 0; i < ipa3_ctx->ipa_num_pipes; i++) { + if (!ipa3_ctx->ep[i].sys || !ipa3_ctx->ep[i].sys->status_stat) + continue; + + memcpy(stats, ipa3_ctx->ep[i].sys->status_stat, sizeof(*stats)); + pr_err("Statuses for pipe %d\n", i); + for (j = 0; j < IPA_MAX_STATUS_STAT_NUM; j++) { + pr_err("curr=%d\n", stats->curr); + ipa_dump_status(&stats->status[stats->curr]); + pr_err("\n\n\n"); + stats->curr = (stats->curr + 1) % + IPA_MAX_STATUS_STAT_NUM; + } + } + + kfree(stats); + return 0; +} + +static ssize_t ipa3_print_active_clients_log(struct file *file, + char __user *ubuf, size_t count, loff_t *ppos) +{ + int cnt; + int table_size; + + if (active_clients_buf == NULL) { + IPAERR("Active Clients buffer is not allocated"); + return 0; + } + memset(active_clients_buf, 0, IPA_DBG_ACTIVE_CLIENT_BUF_SIZE); + mutex_lock(&ipa3_ctx->ipa3_active_clients.mutex); + cnt = ipa3_active_clients_log_print_buffer(active_clients_buf, + IPA_DBG_ACTIVE_CLIENT_BUF_SIZE - IPA_MAX_MSG_LEN); + table_size = ipa3_active_clients_log_print_table(active_clients_buf + + cnt, IPA_MAX_MSG_LEN); + mutex_unlock(&ipa3_ctx->ipa3_active_clients.mutex); + + return simple_read_from_buffer(ubuf, count, ppos, + active_clients_buf, cnt + table_size); +} + +static ssize_t ipa3_clear_active_clients_log(struct file *file, + const char __user *ubuf, size_t count, loff_t *ppos) +{ + ipa3_active_clients_log_clear(); + + return count; +} + +static ssize_t ipa3_enable_ipc_low(struct file *file, + const char __user *ubuf, size_t count, loff_t *ppos) +{ + s8 option = 0; + int ret; + + ret = kstrtos8_from_user(ubuf, count, 0, &option); + if (ret) + return ret; + + mutex_lock(&ipa3_ctx->lock); + if (option) { + if (!ipa_ipc_low_buff) { + ipa_ipc_low_buff = + ipc_log_context_create(IPA_IPC_LOG_PAGES, + "ipa_low", MINIDUMP_MASK); + } + if (ipa_ipc_low_buff == NULL) + IPADBG("failed to get logbuf_low\n"); + ipa3_ctx->logbuf_low = ipa_ipc_low_buff; + } else { + ipa3_ctx->logbuf_low = NULL; + } + mutex_unlock(&ipa3_ctx->lock); + + return count; +} + +static ssize_t ipa3_read_ipa_max_napi_sort_page_thrshld(struct file *file, + char __user *buf, size_t count, loff_t *ppos) { + + int nbytes; + nbytes = scnprintf(dbg_buff, IPA_MAX_MSG_LEN, + "page max napi without free page = %d\n", + ipa3_ctx->ipa_max_napi_sort_page_thrshld); + return simple_read_from_buffer(buf, count, ppos, dbg_buff, nbytes); + +} + +static ssize_t ipa3_write_ipa_max_napi_sort_page_thrshld(struct file *file, + const char __user *buf, size_t count, loff_t *ppos) { + + int ret; + u8 ipa_max_napi_sort_page_thrshld = 0; + + if (count >= sizeof(dbg_buff)) + return -EFAULT; + + ret = kstrtou8_from_user(buf, count, 0, &ipa_max_napi_sort_page_thrshld); + if(ret) + return ret; + + ipa3_ctx->ipa_max_napi_sort_page_thrshld = ipa_max_napi_sort_page_thrshld; + + IPADBG("napi cnt without prealloc pages = %d", ipa3_ctx->ipa_max_napi_sort_page_thrshld); + + return count; +} + +static ssize_t ipa3_read_page_wq_reschd_time(struct file *file, + char __user *buf, size_t count, loff_t *ppos) { + + int nbytes; + nbytes = scnprintf(dbg_buff, IPA_MAX_MSG_LEN, + "Page WQ reschduule time = %d\n", + ipa3_ctx->page_wq_reschd_time); + return simple_read_from_buffer(buf, count, ppos, dbg_buff, nbytes); + +} + +static ssize_t ipa3_write_page_wq_reschd_time(struct file *file, + const char __user *buf, size_t count, loff_t *ppos) { + + int ret; + u8 page_wq_reschd_time = 0; + + if (count >= sizeof(dbg_buff)) + return -EFAULT; + + ret = kstrtou8_from_user(buf, count, 0, &page_wq_reschd_time); + if(ret) + return ret; + + ipa3_ctx->page_wq_reschd_time = page_wq_reschd_time; + + IPADBG("Updated page WQ reschedule time = %d", ipa3_ctx->page_wq_reschd_time); + + return count; +} + +static ssize_t ipa3_read_page_poll_threshold(struct file *file, + char __user *buf, size_t count, loff_t *ppos) { + + int nbytes; + nbytes = scnprintf(dbg_buff, IPA_MAX_MSG_LEN, + "Page Poll Threshold = %d\n", + ipa3_ctx->page_poll_threshold); + return simple_read_from_buffer(buf, count, ppos, dbg_buff, nbytes); + +} +static ssize_t ipa3_write_page_poll_threshold(struct file *file, + const char __user *buf, size_t count, loff_t *ppos) { + + int ret; + u8 page_poll_threshold =0; + + if (count >= sizeof(dbg_buff)) + return -EFAULT; + + ret = kstrtou8_from_user(buf, count, 0, &page_poll_threshold); + if(ret) + return ret; + + if(page_poll_threshold != 0 && + page_poll_threshold <= IPA_PAGE_POLL_THRESHOLD_MAX) + ipa3_ctx->page_poll_threshold = page_poll_threshold; + else + IPAERR("Invalid value \n"); + + IPADBG("Updated page poll threshold = %d", ipa3_ctx->page_poll_threshold); + + return count; +} + +static void ipa3_nat_move_free_cb(void *buff, u32 len, u32 type) +{ + kfree(buff); +} + +static ssize_t ipa3_write_nat_table_move(struct file *file, + const char __user *buf, size_t count, loff_t *ppos) +{ + u32 direction; + unsigned long missing; + char *sptr, *token; + struct ipa_move_nat_req_msg_v01 *req_data; + struct ipa_msg_meta msg_meta; + + if (count >= sizeof(dbg_buff)) + return -EFAULT; + + missing = copy_from_user(dbg_buff, buf, count); + if (missing) + return -EFAULT; + + dbg_buff[count] = '\0'; + + sptr = dbg_buff; + + token = strsep(&sptr, " "); + if (!token) + return -EINVAL; + if (kstrtou32(token, 0, &direction)) + return -EINVAL; + + if (direction) { + pr_err("moving to DDR\n"); + direction = QMI_IPA_MOVE_NAT_TO_DDR_V01; + } else { + pr_err("moving to SRAM\n"); + direction = QMI_IPA_MOVE_NAT_TO_SRAM_V01; + } + + req_data = kzalloc(sizeof(struct ipa_move_nat_req_msg_v01), + GFP_KERNEL); + if (!req_data) { + pr_err("allocation failed\n"); + return EFAULT; + } + + memset(&msg_meta, 0, sizeof(struct ipa_msg_meta)); + msg_meta.msg_type = IPA_MOVE_NAT_TABLE; + msg_meta.msg_len = sizeof(struct ipa_move_nat_req_msg_v01); + + req_data->nat_move_direction = direction; + + ipa3_disable_move_nat_resp(); + pr_err("disabled QMI\n"); + /* make sure QMI is disabled before message sent to IPACM */ + wmb(); + if (ipa_send_msg(&msg_meta, req_data, ipa3_nat_move_free_cb)) { + pr_err("ipa_send_msg failed\nn"); + } + pr_err("message sent\n"); + + return count; +} +#if defined(CONFIG_IPA_TSP) +static ssize_t ipa3_read_tsp(struct file *file, char __user *buf, size_t count, loff_t *ppos) +{ + int i, nbytes = 0; + struct ipahal_ipa_state_tsp state_tsp; + u32 qm_non_empty; + struct ipa_ioc_tsp_ingress_class_params ingr_tc; + struct ipa_ioc_tsp_egress_prod_params egr_ep; + struct ipa_ioc_tsp_egress_class_params egr_tc; + + /* Print the global TSP state flags */ + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + ipahal_read_reg_fields(IPA_STATE_TSP, &state_tsp); + ipahal_read_reg_fields(IPA_STATE_QMNGR_QUEUE_NONEMPTY, &qm_non_empty); + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + + if (state_tsp.traffic_shaper_idle) + nbytes += scnprintf(dbg_buff + nbytes, IPA_MAX_MSG_LEN - nbytes, + "Traffic-Sahper module IDLE\n"); + if (state_tsp.traffic_shaper_fifo_empty) + nbytes += scnprintf(dbg_buff + nbytes, IPA_MAX_MSG_LEN - nbytes, + "Traffic-Sahper FIFO empty\n"); + if (state_tsp.queue_mngr_idle) + nbytes += scnprintf(dbg_buff + nbytes, IPA_MAX_MSG_LEN - nbytes, + "QMNGR overall IDLE\n"); + if (state_tsp.queue_mngr_head_idle) + nbytes += scnprintf(dbg_buff + nbytes, IPA_MAX_MSG_LEN - nbytes, + "QMNGR head module IDLE\n"); + if (state_tsp.queue_mngr_shared_idle) + nbytes += scnprintf(dbg_buff + nbytes, IPA_MAX_MSG_LEN - nbytes, + "QMNGR shared module IDLE\n"); + if (state_tsp.queue_mngr_tail_idle) + nbytes += scnprintf(dbg_buff + nbytes, IPA_MAX_MSG_LEN - nbytes, + "QMNGR tail module IDLE\n"); + if (state_tsp.queue_mngr_block_ctrl_idle) + nbytes += scnprintf(dbg_buff + nbytes, IPA_MAX_MSG_LEN - nbytes, + "Block control module IDLE\n"); + + nbytes += scnprintf(dbg_buff + nbytes, IPA_MAX_MSG_LEN - nbytes, + "QM non-empty bitmask: 0x%08X\n", qm_non_empty); + + /* Dump Ingress Class, Egress Producer and Egress Class tables */ + nbytes += scnprintf(dbg_buff + nbytes, IPA_MAX_MSG_LEN - nbytes, + "Ingress Trafic Class Table:\n"); + nbytes += scnprintf(dbg_buff + nbytes, IPA_MAX_MSG_LEN - nbytes, + "TC Index\tMax Rate\tMax Burst\tInclude L2\n"); + for (i = 1; i <= ipa3_ctx->tsp.ingr_tc_max; i++) { + ipahal_tsp_parse_hw_ingr_tc(ipa3_ctx->tsp.ingr_tc_tbl.base, i, &ingr_tc); + nbytes += scnprintf(dbg_buff + nbytes, IPA_MAX_MSG_LEN - nbytes, + "%02d:\t\t%u\t\t%u\t\t%u\n", + i, ingr_tc.max_rate, ingr_tc.max_burst, ingr_tc.include_l2_len); + } + + nbytes += scnprintf(dbg_buff + nbytes, IPA_MAX_MSG_LEN - nbytes, + "Egress Producer Table:\n"); + nbytes += scnprintf(dbg_buff + nbytes, IPA_MAX_MSG_LEN - nbytes, + "EP Index\tClient\tMax Rate\tMax Burst\n"); + for (i = 0; i < ipa3_ctx->tsp.egr_ep_max; i++) { + ipahal_tsp_parse_hw_egr_ep(ipa3_ctx->tsp.egr_ep_tbl.base, i, &egr_ep); + nbytes += scnprintf(dbg_buff + nbytes, IPA_MAX_MSG_LEN - nbytes, + "%d:\t\t%d\t%u\t\t%u\n", + i, ipa3_ctx->tsp.egr_ep_config[i], egr_ep.max_rate, egr_ep.max_burst); + } + + nbytes += scnprintf(dbg_buff + nbytes, IPA_MAX_MSG_LEN - nbytes, + "Egress Trafic Class Table:\n"); + nbytes += scnprintf(dbg_buff + nbytes, IPA_MAX_MSG_LEN - nbytes, + "TC Index\tMax Rate\tMax Burst\tG. Rate\tG. Burst\n"); + for (i = 1; i <= ipa3_ctx->tsp.egr_tc_max; i++) { + ipahal_tsp_parse_hw_egr_tc(ipa3_ctx->tsp.egr_tc_tbl.base, i, &egr_tc); + nbytes += scnprintf(dbg_buff + nbytes, IPA_MAX_MSG_LEN - nbytes, + "%02d:\t\t%u\t\t%u\t\t%u\t%u\n", + i, egr_tc.max_rate, egr_tc.max_burst, + egr_tc.guaranteed_rate, egr_tc.guaranteed_burst); + } + + return simple_read_from_buffer(buf, count, ppos, dbg_buff, nbytes); +} + +static ssize_t ipa3_write_tsp(struct file *file, const char __user *buf, + size_t count, loff_t *ppos) { + int ret; + u8 option = 0; + + if (count >= sizeof(dbg_buff)) + return -EFAULT; + + ret = kstrtou8_from_user(buf, count, 0, &option); + if(ret) + return ret; + + pr_err("TSP write is not implemented.\n"); + + return count; +} +#endif + +static ssize_t ipa3_perform_loopback(struct file *file, char __user *ubuf, + size_t count, loff_t *ppos) +{ + struct ipa_ioc_add_rt_rule *rt_rule; + struct ipa_ioc_add_flt_rule *flt_rule; + struct ipa_ioc_get_rt_tbl rt_lookup; + int idx; + u32 rt4_wan_cons; + u32 rt6_wan_cons; + struct ipahal_reg_ep_cfg_status ep_status = { 0 }; + + IPAERR("Adding rules to perform loopback on IPA\n"); + + /* set this flag to false so flt rule dont get skipped for WAN_PROD */ + ipa3_ctx->modem_cfg_emb_pipe_flt = false; + + idx = ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_PROD); + if (idx == IPA_EP_NOT_ALLOCATED) { + IPAERR("failed to get idx"); + return idx; + } + + ipa3_ctx->ep[idx].cfg.hdr.hdr_ofst_metadata = 1; + ipa3_cfg_ep_hdr(idx, &ipa3_ctx->ep[idx].cfg.hdr); + + ipa3_cfg_ep_status(idx, &ep_status); + + rt_rule = kzalloc(sizeof(*rt_rule) + 1 * sizeof(struct ipa_rt_rule_add), + GFP_KERNEL); + if (!rt_rule) { + IPAERR("no mem\n"); + return 0; + } + + flt_rule = kzalloc(sizeof(*flt_rule) + + 1 * sizeof(struct ipa_flt_rule_add), GFP_KERNEL); + if (!flt_rule) { + IPAERR("no mem\n"); + goto free_rt; + } + + rt_rule->commit = 1; + rt_rule->ip = IPA_IP_v4; + rt_lookup.ip = rt_rule->ip; + strlcpy(rt_rule->rt_tbl_name, "V4_RT_TO_APPS_WAN_CONS", + IPA_RESOURCE_NAME_MAX); + strlcpy(rt_lookup.name, rt_rule->rt_tbl_name, IPA_RESOURCE_NAME_MAX); + rt_rule->num_rules = 1; + rt_rule->rules[0].rule.dst = IPA_CLIENT_APPS_WAN_CONS; + rt_rule->rules[0].rule.hashable = true; + #ifdef IPA_RT_SUPPORT_COAL + rt_rule->rules[0].rule.coalesce = true; + #endif + if (ipa_add_rt_rule(rt_rule) || rt_rule->rules[0].status) { + IPAERR("failed to install V4 rules\n"); + goto free_flt; + } + if (ipa3_get_rt_tbl(&rt_lookup)) { + IPAERR("failed to query V4 rules\n"); + goto free_flt; + } + rt4_wan_cons = rt_lookup.hdl; + + memset(rt_rule, 0, sizeof(*rt_rule)); + rt_rule->commit = 1; + rt_rule->ip = IPA_IP_v6; + rt_lookup.ip = rt_rule->ip; + strlcpy(rt_rule->rt_tbl_name, "V6_RT_TO_APPS_WAN_CONS", + IPA_RESOURCE_NAME_MAX); + strlcpy(rt_lookup.name, rt_rule->rt_tbl_name, IPA_RESOURCE_NAME_MAX); + rt_rule->num_rules = 1; + rt_rule->rules[0].rule.dst = IPA_CLIENT_APPS_WAN_CONS; + rt_rule->rules[0].rule.hashable = true; + #ifdef IPA_RT_SUPPORT_COAL + rt_rule->rules[0].rule.coalesce = true; + #endif + if (ipa_add_rt_rule(rt_rule) || rt_rule->rules[0].status) { + IPAERR("failed to install V6 rules\n"); + goto free_flt; + } + if (ipa3_get_rt_tbl(&rt_lookup)) { + IPAERR("failed to query V6 rules\n"); + goto free_flt; + } + rt6_wan_cons = rt_lookup.hdl; + + memset(flt_rule, 0, sizeof(*flt_rule)); + flt_rule->commit = 1; + flt_rule->ip = IPA_IP_v4; + flt_rule->ep = IPA_CLIENT_APPS_WAN_PROD; + flt_rule->num_rules = 1; + flt_rule->rules[0].at_rear = 1; + flt_rule->rules[0].rule.action = IPA_PASS_TO_ROUTING; + flt_rule->rules[0].rule.rt_tbl_hdl = rt4_wan_cons; + flt_rule->rules[0].rule.hashable = 1; + if (ipa3_add_flt_rule(flt_rule) || flt_rule->rules[0].status) { + IPAERR("failed to install V4 rules\n"); + goto free_flt; + } + + memset(flt_rule, 0, sizeof(*flt_rule)); + flt_rule->commit = 1; + flt_rule->ip = IPA_IP_v6; + flt_rule->ep = IPA_CLIENT_APPS_WAN_PROD; + flt_rule->num_rules = 1; + flt_rule->rules[0].at_rear = 1; + flt_rule->rules[0].rule.action = IPA_PASS_TO_ROUTING; + flt_rule->rules[0].rule.rt_tbl_hdl = rt6_wan_cons; + flt_rule->rules[0].rule.hashable = 1; + if (ipa3_add_flt_rule(flt_rule) || flt_rule->rules[0].status) { + IPAERR("failed to install V6 rules\n"); + goto free_flt; + } + + +free_flt: + kfree(flt_rule); +free_rt: + kfree(rt_rule); + return 0; +} + +static inline u32 ip_to_int(u8 a, u8 b, u8 c, u8 d) +{ + // IP to int is first octet * 256^3 + second octet * 256^2 + third octet * 256 + fourth oct + // Bit shifting is quicker than multiplication + // 2^24 = 256^3, 2^16 = 256^2, 256 = 2^8 + return (a << 24) + (b << 16) + (c << 8) + d; +} + +static u32 string_ip_to_integer_ip(char *str_ip) +{ + u8 a = 0, b = 0, c = 0, d = 0; + char *found = NULL; + u32 ip = 0; + + if (!str_ip) + return ip; + + found = strsep(&str_ip, "."); + if (!found || kstrtou8(found, 0, &a)) + goto err; + + found = strsep(&str_ip, "."); + if (!found || kstrtou8(found, 0, &b)) + goto err; + + found = strsep(&str_ip, "."); + if (!found || kstrtou8(found, 0, &c)) + goto err; + + found = strsep(&str_ip, "."); + if (!found || kstrtou8(found, 0, &d)) + goto err; + + pr_info("IP ADDR -> %d.%d.%d.%d\n", a, b, c, d); + ip = ip_to_int(a, b, c, d); + +err: + return ip; +} + +static ssize_t ipa_xr_add_flt_to_wlan(struct file *file, + const char __user *buf, size_t count, loff_t *ppos) +{ + u32 src_ip[MAX_STREAMS] = {0}; + u32 dst_ip[MAX_STREAMS] = {0}; + u16 src_port[MAX_STREAMS] = {0}; + u16 dst_port[MAX_STREAMS] = {0}; + u8 prot[MAX_STREAMS] = {0}; + u8 num_filters = 0; + ssize_t missing = 0; + char *sptr = NULL; + char *token = NULL; + struct ipa_wdi_opt_dpath_flt_add_cb_params flt_add_req; + int result = 0; + u8 i = 0, j = 0, stream_id = 0; + + if (count >= sizeof(dbg_buff)) + return -EFAULT; + + memset(dbg_buff, 0, sizeof(dbg_buff)); + missing = copy_from_user(dbg_buff, buf, count); + if (missing) + return -EFAULT; + + dbg_buff[count] = '\0'; + sptr = dbg_buff; + + /* Getting the number of filters configured by user */ + token = strsep(&sptr, " "); + if (!token) + return -EINVAL; + if (kstrtou8(token, 0, &num_filters)) + return -EINVAL; + + IPADBG("Number of filters %d\n", num_filters); + + if (num_filters > MAX_STREAMS || num_filters == 0) { + IPAERR("Number of filters is zero or more than max_streams, so it is invalid\n"); + return -EINVAL; + } + + if (!atomic_read(&ipa3_ctx->ipa_xr_wdi_flt_rsv_status)) { + memset(active_streams, 0, sizeof(active_streams)); + active_flt_cnt = 0; + } + + if (active_flt_cnt + num_filters > MAX_STREAMS) { + IPAERR("Active filter count of %u exceeded maximum streams of %u\n", + active_flt_cnt, MAX_STREAMS); + return -EFAULT; + } + + for (i = 0; i < num_filters; i++) { + token = strsep(&sptr, " "); + if (!token) + return -EINVAL; + src_ip[i] = string_ip_to_integer_ip(token); + if (!src_ip[i]) + return -EINVAL; + + token = strsep(&sptr, " "); + if (!token) + return -EINVAL; + dst_ip[i] = string_ip_to_integer_ip(token); + if (!dst_ip[i]) + return -EINVAL; + + token = strsep(&sptr, " "); + if (!token) + return -EINVAL; + /* Range detection will be done by this API */ + if (kstrtou16(token, 0, &src_port[i]) || src_port[i] == 0) + return -EINVAL; + + token = strsep(&sptr, " "); + if (!token) + return -EINVAL; + /* Range detection will be done by this API */ + if (kstrtou16(token, 0, &dst_port[i]) || dst_port[i] == 0) + return -EINVAL; + + token = strsep(&sptr, " "); + if (!token) + return -EINVAL; + if (kstrtou8(token, 0, &prot[i]) || + !(prot[i] == IPPROTO_UDP || prot[i] == IPPROTO_TCP)) + return -EINVAL; + } + + if (!atomic_read(&ipa3_ctx->ipa_xr_wdi_flt_rsv_status)) { + result = ipa_xr_wdi_opt_dpath_rsrv_filter_req(); + if (result) { + IPAERR("Filter reservation failed at WLAN %d\n", result); + return result; + } + } + + for (i = 0; i < num_filters; i++) { + for (j = 0; j < MAX_STREAMS; j++) { + if (active_streams[j] == 0) { + stream_id = j; + break; + } + } + + IPADBG("Available stream id %u\n", stream_id); + memset(&flt_add_req, 0, sizeof(struct ipa_wdi_opt_dpath_flt_add_cb_params)); + flt_add_req.num_tuples = 1; + flt_add_req.flt_info[0].version = 0; + flt_add_req.flt_info[0].ipv4_addr.ipv4_saddr = src_ip[i]; + flt_add_req.flt_info[0].ipv4_addr.ipv4_daddr = dst_ip[i]; + flt_add_req.flt_info[0].sport = src_port[i]; + flt_add_req.flt_info[0].dport = dst_port[i]; + flt_add_req.flt_info[0].protocol = prot[i]; + + IPADBG("IPv4 saddr:%lu, daddr:%lu IPv4 sport:%u, dport:%u protocol:%u\n", + flt_add_req.flt_info[0].ipv4_addr.ipv4_saddr, + flt_add_req.flt_info[0].ipv4_addr.ipv4_daddr, + flt_add_req.flt_info[0].sport, + flt_add_req.flt_info[0].dport, + flt_add_req.flt_info[0].protocol); + + result = ipa_xr_wdi_opt_dpath_add_filter_req(&flt_add_req, stream_id); + if (result) { + IPAERR("Failed to add filters at wlan\n"); + return -EPERM; + } + active_streams[stream_id] = 1; + active_flt_cnt++; + } + + return count; +} + +static ssize_t ipa_xr_remove_flt_to_wlan(struct file *file, + const char __user *buf, size_t count, loff_t *ppos) +{ + char *sptr = NULL, *token = NULL; + u8 flt_opt = 0; + int result = 0; + ssize_t missing = 0; + + if (active_flt_cnt == 0) { + IPAERR("No active filters to delete\n"); + return -EFAULT; + } + + if (count >= sizeof(dbg_buff)) + return -EFAULT; + + memset(dbg_buff, 0, sizeof(dbg_buff)); + missing = copy_from_user(dbg_buff, buf, count); + if (missing) + return -EFAULT; + + dbg_buff[count] = '\0'; + sptr = dbg_buff; + + token = strsep(&sptr, " "); + if (!token) + return -EINVAL; + if (kstrtou8(token, 0, &flt_opt)) + return -EINVAL; + + if (flt_opt > MAX_STREAMS) { + IPAERR("Flt_opt is more than max_streams, so it is invalid\n"); + return -EINVAL; + } + + if (!atomic_read(&ipa3_ctx->ipa_xr_wdi_flt_rsv_status)) { + IPAERR("No existing filters at wlan\n"); + memset(active_streams, 0, sizeof(active_streams)); + active_flt_cnt = 0; + return -EPERM; + } + + /* flt_opt == 0, will remove all streams filters from wlan */ + if (!flt_opt) { + result = ipa_xr_wdi_opt_dpath_remove_all_filter_req(); + if (result) { + IPAERR("Failed to remove all streams filters from wlan\n"); + return -EPERM; + } + active_flt_cnt = 0; + memset(active_streams, 0, sizeof(active_streams)); + IPADBG("Removed all streams existing filters\n"); + return count; + } + + if (active_streams[flt_opt-1] == 0) { + IPADBG("Stream_ID: %d filter is already deleted at WLAN\n", flt_opt); + return -EPERM; + } + + /* Based on stream ID removing filters from wlan */ + result = ipa_xr_wdi_opt_dpath_remove_filter_req(flt_opt - 1); + if (result) { + IPAERR("Failed to remove stream-id: %d filter from wlan\n", flt_opt); + return -EPERM; + } + IPADBG("Removed stream-id: %d filter from wlan\n", flt_opt); + active_flt_cnt--; + active_streams[flt_opt - 1] = 0; + return count; +} + +#ifdef CONFIG_IPA_RTP +static ssize_t ipa_xr_add_flt_to_ipa_wlan(struct file *file, + const char __user *buf, size_t count, loff_t *ppos) +{ + struct traffic_tuple_info tuple_info; + u32 src_ip = 0; + u32 dst_ip = 0; + u16 src_port = 0; + u16 dst_port = 0; + u8 prot = 0; + ssize_t missing = 0; + char *sptr = NULL, *token = NULL; + int result = 0; + u32 bs_buff_size = 0; + u8 stream_id = 0; + + struct bitstream_buffers_to_uc data; + dma_addr_t bs_phys_base[MAX_BUFF], mb_phys_base[MAX_BUFF]; + void *bs_va[MAX_BUFF] = {NULL}, *mb_va[MAX_BUFF] = {NULL}; + int i = 0, j = 0; + + if (!atomic_read(&ipa3_ctx->ipa_xr_wdi_flt_rsv_status)) { + memset(active_streams, 0, sizeof(active_streams)); + active_flt_cnt = 0; + } + + if (active_flt_cnt >= MAX_STREAMS) { + IPAERR("Maximum filters already installed: %u\n", active_flt_cnt); + return -EFAULT; + } + + if (count >= sizeof(dbg_buff)) + return -EFAULT; + + memset(dbg_buff, 0, sizeof(dbg_buff)); + missing = copy_from_user(dbg_buff, buf, count); + if (missing) + return -EFAULT; + + dbg_buff[count] = '\0'; + sptr = dbg_buff; + + token = strsep(&sptr, " "); + if (!token) + return -EINVAL; + src_ip = string_ip_to_integer_ip(token); + if (!src_ip) + return -EINVAL; + + token = strsep(&sptr, " "); + if (!token) + return -EINVAL; + dst_ip = string_ip_to_integer_ip(token); + if (!dst_ip) + return -EINVAL; + + token = strsep(&sptr, " "); + if (!token) + return -EINVAL; + if (kstrtou16(token, 0, &src_port) || src_port == 0) + return -EINVAL; + + token = strsep(&sptr, " "); + if (!token) + return -EINVAL; + if (kstrtou16(token, 0, &dst_port) || dst_port == 0) + return -EINVAL; + + token = strsep(&sptr, " "); + if (!token) + return -EINVAL; + if (kstrtou8(token, 0, &prot) || prot != IPPROTO_UDP) + return -EINVAL; + + token = strsep(&sptr, " "); + if (!token) + return -EINVAL; + if (kstrtou32(token, 0, &bs_buff_size) || bs_buff_size > MAX_UC_BUFF_SIZE) + return -EINVAL; + + for (j = 0; j < MAX_STREAMS; j++) { + if (active_streams[j] == 0) { + stream_id = j; + break; + } + } + + IPADBG("Available stream id %u\n", stream_id); + IPADBG("Framing bitstream & Metadata buffer of size :%lu\n", bs_buff_size); + + data.buff_cnt = MAX_BUFF; + data.cookie = 0x1234; + for (i = 0; i < data.buff_cnt; i++) { + data.bs_info[i].stream_id = stream_id; + data.bs_info[i].fence_id = i; + bs_va[i] = dma_alloc_coherent(ipa3_ctx->rtp_pdev, bs_buff_size, + &bs_phys_base[i], GFP_KERNEL); + if (!bs_va[i]) { + IPADBG("Failed to allocate bitstream buffers of size: %u\n", + bs_buff_size); + goto free_bs_mb_buff; + } + + IPADBG("Bit stream buffer va is 0x%x\n", bs_va[i]); + IPADBG("Bit stream buffer iova is 0x%x\n", bs_phys_base[i]); + data.bs_info[i].buff_addr = bs_phys_base[i]; + data.bs_info[i].buff_fd = 0; + data.bs_info[i].buff_size = bs_buff_size; + mb_va[i] = dma_alloc_coherent(ipa3_ctx->rtp_pdev, IPA_MAX_MSG_LEN, + &mb_phys_base[i], GFP_KERNEL); + if (!mb_va[i]) { + IPADBG("Failed to allocate metadata buffers of size: %u\n", + IPA_MAX_MSG_LEN); + dma_free_coherent(ipa3_ctx->rtp_pdev, bs_buff_size, + bs_va[i], bs_phys_base[i]); + goto free_bs_mb_buff; + } + + IPADBG("Metadata buffer va is 0x%x\n", mb_va[i]); + IPADBG("Metadata buffer iova is 0x%x\n", mb_phys_base[i]); + data.bs_info[i].meta_buff_addr = mb_phys_base[i]; + data.bs_info[i].meta_buff_fd = 0; + data.bs_info[i].meta_buff_size = IPA_MAX_MSG_LEN; + } + + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + + result = ipa3_uc_send_add_bitstream_buffers_cmd(&data); + if (result) { + IPAERR("Failed to send bitstream buffers to uC\n"); + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + goto free_bs_mb_buff; + } + + tuple_info.ts_info.no_of_openframe = 3; + tuple_info.ts_info.max_pkt_frame = 256; + tuple_info.ts_info.stream_type = 0; + tuple_info.ts_info.reorder_timeout = 100; + tuple_info.ts_info.num_slices_per_frame = 0; + + tuple_info.ip_type = 0; + tuple_info.ip_info.ipv4.src_port_number = src_port; + tuple_info.ip_info.ipv4.dst_port_number = dst_port; + tuple_info.ip_info.ipv4.src_ip = src_ip; + tuple_info.ip_info.ipv4.dst_ip = dst_ip; + tuple_info.ip_info.ipv4.protocol = prot; + + IPADBG("IPv4 saddr:0x%x, daddr:0x%x\n", + tuple_info.ip_info.ipv4.src_ip, + tuple_info.ip_info.ipv4.dst_ip); + IPADBG("IPv4 sport:%u, dport:%u\n", + tuple_info.ip_info.ipv4.src_port_number, + tuple_info.ip_info.ipv4.dst_port_number); + + if (ipa3_install_rtp_hdr_proc_rt_flt_rules(&tuple_info, stream_id) || + ipa3_tuple_info_cmd_to_wlan_uc(&tuple_info, stream_id)) { + IPAERR("Failed to install rtp hdr proc and flt rules or filters at WLAN\n"); + ipa3_delete_rtp_hdr_proc_rt_flt_rules(stream_id); + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + goto free_bs_mb_buff; + } + active_flt_cnt++; + active_streams[stream_id] = 1; + IPADBG("Sent bitstream and metadata buffer, filter info to uC or WLAN\n"); + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + + return count; + +free_bs_mb_buff: + /* ith bs_buff is already freed above */ + for (j = i-1; j >= 0; j--) { + if (bs_va[j]) + dma_free_coherent(ipa3_ctx->rtp_pdev, bs_buff_size, + bs_va[j], bs_phys_base[j]); + if (mb_va[j]) + dma_free_coherent(ipa3_ctx->rtp_pdev, IPA_MAX_MSG_LEN, + mb_va[j], mb_phys_base[j]); + } + return -ENOMEM; +} + +static ssize_t ipa_xr_remove_flt_to_ipa_wlan(struct file *file, + const char __user *buf, size_t count, loff_t *ppos) +{ + char *sptr = NULL, *token = NULL; + u8 stream_id = 0; + ssize_t missing = 0; + struct remove_bitstream_buffers rmv_sid_req; + + if (active_flt_cnt == 0) { + IPAERR("No active filters to delete\n"); + return -EFAULT; + } + + if (!atomic_read(&ipa3_ctx->ipa_xr_wdi_flt_rsv_status)) { + IPAERR("No existing filters at wlan\n"); + memset(active_streams, 0, sizeof(active_streams)); + active_flt_cnt = 0; + return -EPERM; + } + + if (count >= sizeof(dbg_buff)) + return -EFAULT; + + memset(dbg_buff, 0, sizeof(dbg_buff)); + missing = copy_from_user(dbg_buff, buf, count); + if (missing) + return -EFAULT; + + dbg_buff[count] = '\0'; + sptr = dbg_buff; + token = strsep(&sptr, " "); + if (!token) + return -EINVAL; + if (kstrtou8(token, 0, &stream_id)) + return -EINVAL; + + if (stream_id > MAX_STREAMS || stream_id == 0) { + IPAERR("Stream_id is zero or more than %u. Exit\n", MAX_STREAMS); + return -EINVAL; + } + + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + + rmv_sid_req.stream_id = stream_id; + if (ipa3_uc_send_remove_stream_cmd(&rmv_sid_req) || + ipa3_delete_rtp_hdr_proc_rt_flt_rules(stream_id - 1)) { + IPADBG("Failed to remove stream id: %d filters from IPA and WLAN\n", stream_id); + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + return -EPERM; + } + + active_streams[stream_id - 1] = 0; + active_flt_cnt--; + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + IPADBG("Removed stream id: %d filters from IPA and WLAN\n", stream_id); + return count; +} +#endif + +static const struct ipa3_debugfs_file debugfs_files[] = { + { + "gen_reg", IPA_READ_ONLY_MODE, NULL, { + .read = ipa3_read_gen_reg + } + }, { + "active_clients", IPA_READ_WRITE_MODE, NULL, { + .read = ipa3_print_active_clients_log, + .write = ipa3_clear_active_clients_log + } + }, { + "ep_reg", IPA_READ_WRITE_MODE, NULL, { + .read = ipa3_read_ep_reg, + .write = ipa3_write_ep_reg, + } + }, { + "keep_awake", IPA_READ_WRITE_MODE, NULL, { + .read = ipa3_read_keep_awake, + .write = ipa3_write_keep_awake, + } + }, { + "mpm_ring_size_dl", IPA_READ_WRITE_MODE, NULL, { + .read = ipa3_read_mpm_ring_size_dl, + .write = ipa3_write_mpm_ring_size_dl, + } + }, { + "mpm_ring_size_ul", IPA_READ_WRITE_MODE, NULL, { + .read = ipa3_read_mpm_ring_size_ul, + .write = ipa3_write_mpm_ring_size_ul, + } + }, { + "mpm_uc_thresh", IPA_READ_WRITE_MODE, NULL, { + .read = ipa3_read_mpm_uc_thresh, + .write = ipa3_write_mpm_uc_thresh, + } + }, { + "mpm_teth_aggr_size", IPA_READ_WRITE_MODE, NULL, { + .read = ipa3_read_mpm_teth_aggr_size, + .write = ipa3_write_mpm_teth_aggr_size, + } + }, { + "set_clk_idx", IPA_READ_WRITE_MODE, NULL, { + .write = ipa3_set_clk_index, + } + }, { + "holb", IPA_WRITE_ONLY_MODE, NULL, { + .write = ipa3_write_ep_holb, + } + }, { + "holb_monitor_client_param", IPA_WRITE_ONLY_MODE, NULL, { + .write = ipa3_write_holb_monitor_client, + } + }, { + "holb_monitor_client_add_del", IPA_WRITE_ONLY_MODE, NULL, { + .write = ipa3_write_holb_monitor_client_add_del, + } + }, { + "holb_events", IPA_READ_ONLY_MODE, NULL, { + .read = ipa3_read_holb_events, + } + }, { + "hdr", IPA_READ_ONLY_MODE, NULL, { + .read = ipa3_read_hdr, + } + }, { + "proc_ctx", IPA_READ_ONLY_MODE, NULL, { + .read = ipa3_read_proc_ctx, + } + }, { + "ip4_rt", IPA_READ_ONLY_MODE, (void *)IPA_IP_v4, { + .read = ipa3_read_rt, + .open = ipa3_open_dbg, + } + }, { + "ip4_rt_hw", IPA_READ_ONLY_MODE, (void *)IPA_IP_v4, { + .read = ipa3_read_rt_hw, + .open = ipa3_open_dbg, + } + }, { + "ip6_rt", IPA_READ_ONLY_MODE, (void *)IPA_IP_v6, { + .read = ipa3_read_rt, + .open = ipa3_open_dbg, + } + }, { + "ip6_rt_hw", IPA_READ_ONLY_MODE, (void *)IPA_IP_v6, { + .read = ipa3_read_rt_hw, + .open = ipa3_open_dbg, + } + }, { + "ip4_flt", IPA_READ_ONLY_MODE, (void *)IPA_IP_v4, { + .read = ipa3_read_flt, + .open = ipa3_open_dbg, + } + }, { + "ip4_flt_hw", IPA_READ_ONLY_MODE, (void *)IPA_IP_v4, { + .read = ipa3_read_flt_hw, + .open = ipa3_open_dbg, + } + }, { + "ip6_flt", IPA_READ_ONLY_MODE, (void *)IPA_IP_v6, { + .read = ipa3_read_flt, + .open = ipa3_open_dbg, + } + }, { + "ip6_flt_hw", IPA_READ_ONLY_MODE, (void *)IPA_IP_v6, { + .read = ipa3_read_flt_hw, + .open = ipa3_open_dbg, + } + }, { + "stats", IPA_READ_ONLY_MODE, NULL, { + .read = ipa3_read_stats, + } + }, { + "wstats", IPA_READ_ONLY_MODE, NULL, { + .read = ipa3_read_wstats, + } + }, { + "odlstats", IPA_READ_ONLY_MODE, NULL, { + .read = ipa3_read_odlstats, + } + }, { + "page_recycle_stats", IPA_READ_ONLY_MODE, NULL, { + .read = ipa3_read_page_recycle_stats, + } + }, { + "lan_coal_stats", IPA_READ_ONLY_MODE, NULL, { + .read = ipa3_read_lan_coal_stats, + } + }, { + "cache_recycle_stats", IPA_READ_ONLY_MODE, NULL, { + .read = ipa3_read_cache_recycle_stats, + } + }, { + "wdi", IPA_READ_ONLY_MODE, NULL, { + .read = ipa3_read_wdi, + } + }, { + "ntn", IPA_READ_ONLY_MODE, NULL, { + .read = ipa3_read_ntn, + } + }, { + "dbg_cnt", IPA_READ_WRITE_MODE, NULL, { + .read = ipa3_read_dbg_cnt, + .write = ipa3_write_dbg_cnt, + } + }, { + "msg", IPA_READ_ONLY_MODE, NULL, { + .read = ipa3_read_msg, + } + }, { + "ip4_nat", IPA_READ_ONLY_MODE, NULL, { + .read = ipa3_read_nat4, + } + }, { + "ipv6ct", IPA_READ_ONLY_MODE, NULL, { + .read = ipa3_read_ipv6ct, + } + }, { + "pm_stats", IPA_READ_ONLY_MODE, NULL, { + .read = ipa3_pm_read_stats, + } + }, { + "pm_ex_stats", IPA_READ_ONLY_MODE, NULL, { + .read = ipa3_pm_ex_read_stats, + } + }, { + "status_stats", IPA_READ_ONLY_MODE, NULL, { + .read = ipa_status_stats_read, + } + }, { + "enable_low_prio_print", IPA_WRITE_ONLY_MODE, NULL, { + .write = ipa3_enable_ipc_low, + } + }, { + "ipa_dump_regs", IPA_READ_ONLY_MODE, NULL, { + .read = ipa3_read_ipahal_regs, + } + }, { + "wdi_gsi_stats", IPA_READ_ONLY_MODE, NULL, { + .read = ipa3_read_wdi_gsi_stats, + } + }, { + "wdi3_gsi_stats", IPA_READ_ONLY_MODE, NULL, { + .read = ipa3_read_wdi3_gsi_stats, + } + }, { + "11ad_gsi_stats", IPA_READ_ONLY_MODE, NULL, { + .read = ipa3_read_11ad_gsi_stats, + } + }, { + "aqc_gsi_stats", IPA_READ_ONLY_MODE, NULL, { + .read = ipa3_read_aqc_gsi_stats, + } + }, { + "mhip_gsi_stats", IPA_READ_ONLY_MODE, NULL, { + .read = ipa3_read_mhip_gsi_stats, + } + }, { + "usb_gsi_stats", IPA_READ_ONLY_MODE, NULL, { + .read = ipa3_read_usb_gsi_stats, + } + }, { + "app_clk_vote_cnt", IPA_READ_ONLY_MODE, NULL, { + .read = ipa3_read_app_clk_vote, + } + }, { + "page_poll_threshold", IPA_READ_WRITE_MODE, NULL, { + .read = ipa3_read_page_poll_threshold, + .write = ipa3_write_page_poll_threshold, + } + }, { + "move_nat_table_to_ddr", IPA_WRITE_ONLY_MODE, NULL,{ + .write = ipa3_write_nat_table_move, + } + }, { + "page_wq_reschd_time", IPA_READ_WRITE_MODE, NULL, { + .read = ipa3_read_page_wq_reschd_time, + .write = ipa3_write_page_wq_reschd_time, + } + }, { + "ipa_max_napi_sort_page_thrshld", IPA_READ_WRITE_MODE, NULL, { + .read = ipa3_read_ipa_max_napi_sort_page_thrshld, + .write = ipa3_write_ipa_max_napi_sort_page_thrshld, + } +#if defined(CONFIG_IPA_TSP) + }, { + "tsp", IPA_READ_WRITE_MODE, NULL, { + .read = ipa3_read_tsp, + .write = ipa3_write_tsp, + } +#endif + }, { + "ipa_loopback_on_ipa", IPA_READ_ONLY_MODE, NULL, { + .read = ipa3_perform_loopback, + } + }, { + "xr_wlan_add_flt", IPA_WRITE_ONLY_MODE, NULL, { + .write = ipa_xr_add_flt_to_wlan + } + }, { + "xr_wlan_rmv_flt", IPA_WRITE_ONLY_MODE, NULL, { + .write = ipa_xr_remove_flt_to_wlan, + } +#if defined(CONFIG_IPA_RTP) + }, { + "xr_ipa_wlan_add_flt", IPA_WRITE_ONLY_MODE, NULL, { + .write = ipa_xr_add_flt_to_ipa_wlan, + } + }, { + "xr_ipa_wlan_rmv_flt", IPA_WRITE_ONLY_MODE, NULL, { + .write = ipa_xr_remove_flt_to_ipa_wlan, + } +#endif + } +}; + +void ipa3_debugfs_init(void) +{ + const size_t debugfs_files_num = + sizeof(debugfs_files) / sizeof(struct ipa3_debugfs_file); + size_t i; + struct dentry *file; + + dent = debugfs_create_dir("ipa", NULL); + if (IS_ERR(dent)) { + IPAERR("fail to create folder in debug_fs.\n"); + return; + } + + debugfs_create_u32("hw_type", IPA_READ_ONLY_MODE, + dent, &ipa3_ctx->ipa_hw_type); + + for (i = 0; i < debugfs_files_num; ++i) { + const struct ipa3_debugfs_file *curr = &debugfs_files[i]; + + file = debugfs_create_file(curr->name, curr->mode, dent, + curr->data, &curr->fops); + if (!file || IS_ERR(file)) { + IPAERR("fail to create file for debug_fs %s\n", + curr->name); + goto fail; + } + } + + active_clients_buf = NULL; + active_clients_buf = kzalloc(IPA_DBG_ACTIVE_CLIENT_BUF_SIZE, + GFP_KERNEL); + if (active_clients_buf == NULL) + goto fail; + + debugfs_create_u32("enable_clock_scaling", IPA_READ_WRITE_MODE, + dent, &ipa3_ctx->enable_clock_scaling); + + debugfs_create_u32("tx_wrapper_cache_max_size", + IPA_READ_WRITE_MODE, + dent, &ipa3_ctx->tx_wrapper_cache_max_size); + + debugfs_create_u32("enable_napi_chain", IPA_READ_WRITE_MODE, + dent, &ipa3_ctx->enable_napi_chain); + + debugfs_create_u32("clock_scaling_bw_threshold_nominal_mbps", + IPA_READ_WRITE_MODE, dent, + &ipa3_ctx->ctrl->clock_scaling_bw_threshold_nominal); + + debugfs_create_u32("clock_scaling_bw_threshold_turbo_mbps", + IPA_READ_WRITE_MODE, dent, + &ipa3_ctx->ctrl->clock_scaling_bw_threshold_turbo); + + debugfs_create_u32("clk_rate", IPA_READ_ONLY_MODE, + dent, &ipa3_ctx->curr_ipa_clk_rate); + + ipa_debugfs_init_stats(dent); + + ipa3_wigig_init_debugfs_i(dent); + + return; + +fail: + debugfs_remove_recursive(dent); +} + +void ipa3_debugfs_remove(void) +{ + if (IS_ERR(dent)) { + IPAERR("Debugfs:folder was not created.\n"); + return; + } + if (active_clients_buf != NULL) { + kfree(active_clients_buf); + active_clients_buf = NULL; + } + debugfs_remove_recursive(dent); +} + +struct dentry *ipa_debugfs_get_root(void) +{ + return dent; +} +EXPORT_SYMBOL(ipa_debugfs_get_root); + +static ssize_t ipa3_eth_read_status(struct file *file, + char __user *ubuf, size_t count, loff_t *ppos) +{ + int nbytes; + int cnt = 0; + int i, j, k, type; + struct ipa3_eth_info eth_info; + + if (ipa3_ctx->ipa_hw_type < IPA_HW_v4_5) { + nbytes = scnprintf(dbg_buff, IPA_MAX_MSG_LEN, + "This feature only support on IPA4.5+\n"); + cnt += nbytes; + goto done; + } + + nbytes = scnprintf(dbg_buff, IPA_MAX_MSG_LEN, + "%15s|%10s|%10s|%30s|%10s|%10s\n", "protocol", + "instance", "pipe_hdl", "pipe_enum", + "pipe_id", "ch_id"); + cnt += nbytes; + for (i = 0; i < IPA_ETH_CLIENT_MAX; i++) { + for (j = 0; j < IPA_ETH_INST_ID_MAX; j++) { + eth_info = ipa3_ctx->eth_info[i][j]; + for (k = 0; k < eth_info.num_ch; k++) { + if (eth_info.map[j].valid) { + type = eth_info.map[k].type; + nbytes = scnprintf(dbg_buff + cnt, + IPA_MAX_MSG_LEN - cnt, + "%15s|%10d|%10d|%30s|%10d|%10d\n", + ipa_eth_clients_strings[i], + j, + eth_info.map[k].pipe_hdl, + ipa_clients_strings[type], + eth_info.map[k].pipe_id, + eth_info.map[k].ch_id); + cnt += nbytes; + } + } + } + } +done: + return simple_read_from_buffer(ubuf, count, ppos, dbg_buff, cnt); +} + +static const struct file_operations fops_ipa_eth_status = { + .read = ipa3_eth_read_status, +}; + +void ipa3_eth_debugfs_init(void) +{ + struct dentry *file; + + if (IS_ERR_OR_NULL(dent)) { + IPAERR("debugs root not created\n"); + return; + } + dent_eth = debugfs_create_dir("eth", dent); + if (IS_ERR(dent)) { + IPAERR("fail to create folder in debug_fs.\n"); + return; + } + file = debugfs_create_file("status", IPA_READ_ONLY_MODE, + dent_eth, NULL, &fops_ipa_eth_status); + if (!file) { + IPAERR("could not create status\n"); + goto fail; + } + return; + +fail: + debugfs_remove_recursive(dent_eth); +} +EXPORT_SYMBOL(ipa3_eth_debugfs_init); + +static ssize_t ipa3_eth_read_perf_status(struct file *file, + char __user *ubuf, size_t count, loff_t *ppos) +{ + int nbytes; + int cnt = 0; + struct ipa_eth_client *client; + struct ipa_uc_dbg_ring_stats stats; + int tx_ep, rx_ep; + int ret; + + if (ipa3_ctx->ipa_hw_type < IPA_HW_v4_5 + && (ipa3_ctx->ipa_hw_type != IPA_HW_v4_1 + || ipa3_ctx->platform_type != IPA_PLAT_TYPE_APQ)) { + nbytes = scnprintf(dbg_buff, IPA_MAX_MSG_LEN, + "This feature only support on IPA4.5+\n"); + cnt += nbytes; + goto done; + } + client = (struct ipa_eth_client *)file->private_data; + switch (client->client_type) { + case IPA_ETH_CLIENT_AQC107: + case IPA_ETH_CLIENT_AQC113: + case IPA_ETH_CLIENT_NTN: + if (client->client_type == IPA_ETH_CLIENT_NTN) { + ret = ipa3_get_ntn_gsi_stats(&stats); + tx_ep = IPA_CLIENT_ETHERNET_CONS; + rx_ep = IPA_CLIENT_ETHERNET_PROD; + } else { + ret = ipa3_get_aqc_gsi_stats(&stats); + tx_ep = IPA_CLIENT_AQC_ETHERNET_CONS; + rx_ep = IPA_CLIENT_AQC_ETHERNET_PROD; + } + if (!ret) { + nbytes = scnprintf(dbg_buff, IPA_MAX_MSG_LEN, + "%s_ringFull=%u\n" + "%s_ringEmpty=%u\n" + "%s_ringUsageHigh=%u\n" + "%s_ringUsageLow=%u\n" + "%s_RingUtilCount=%u\n", + ipa_clients_strings[tx_ep], + stats.u.ring[1].ringFull, + ipa_clients_strings[tx_ep], + stats.u.ring[1].ringEmpty, + ipa_clients_strings[tx_ep], + stats.u.ring[1].ringUsageHigh, + ipa_clients_strings[tx_ep], + stats.u.ring[1].ringUsageLow, + ipa_clients_strings[tx_ep], + stats.u.ring[1].RingUtilCount); + cnt += nbytes; + nbytes = scnprintf(dbg_buff + cnt, + IPA_MAX_MSG_LEN - cnt, + "%s_ringFull=%u\n" + "%s_ringEmpty=%u\n" + "%s_ringUsageHigh=%u\n" + "%s_ringUsageLow=%u\n" + "%s_RingUtilCount=%u\n", + ipa_clients_strings[rx_ep], + stats.u.ring[0].ringFull, + ipa_clients_strings[rx_ep], + stats.u.ring[0].ringEmpty, + ipa_clients_strings[rx_ep], + stats.u.ring[0].ringUsageHigh, + ipa_clients_strings[rx_ep], + stats.u.ring[0].ringUsageLow, + ipa_clients_strings[rx_ep], + stats.u.ring[0].RingUtilCount); + cnt += nbytes; + } else { + nbytes = scnprintf(dbg_buff, + IPA_MAX_MSG_LEN, + "Fail to read [%s][%s] GSI stats\n", + ipa_clients_strings[rx_ep], + ipa_clients_strings[tx_ep]); + cnt += nbytes; + } + break; + case IPA_ETH_CLIENT_RTK8111K: + case IPA_ETH_CLIENT_RTK8125B: + ret = ipa3_get_rtk_gsi_stats(&stats); + tx_ep = IPA_CLIENT_RTK_ETHERNET_CONS; + rx_ep = IPA_CLIENT_RTK_ETHERNET_PROD; + if (!ret) { + nbytes = scnprintf(dbg_buff, IPA_MAX_MSG_LEN, + "%s_ringFull=%u\n" + "%s_ringEmpty=%u\n" + "%s_ringUsageHigh=%u\n" + "%s_ringUsageLow=%u\n" + "%s_RingUtilCount=%u\n" + "%s_trCount=%u\n" + "%s_erCound=%u\n" + "%s_totalAoSCount=%u\n" + "%s_busytime=%llu\n", + ipa_clients_strings[tx_ep], + stats.u.rtk[1].commStats.ringFull, + ipa_clients_strings[tx_ep], + stats.u.rtk[1].commStats.ringEmpty, + ipa_clients_strings[tx_ep], + stats.u.rtk[1].commStats.ringUsageHigh, + ipa_clients_strings[tx_ep], + stats.u.rtk[1].commStats.ringUsageLow, + ipa_clients_strings[tx_ep], + stats.u.rtk[1].commStats.RingUtilCount, + ipa_clients_strings[tx_ep], + stats.u.rtk[1].trCount, + ipa_clients_strings[tx_ep], + stats.u.rtk[1].erCount, + ipa_clients_strings[tx_ep], + stats.u.rtk[1].totalAosCount, + ipa_clients_strings[tx_ep], + stats.u.rtk[1].busyTime); + cnt += nbytes; + nbytes = scnprintf(dbg_buff + cnt, + IPA_MAX_MSG_LEN - cnt, + "%s_ringFull=%u\n" + "%s_ringEmpty=%u\n" + "%s_ringUsageHigh=%u\n" + "%s_ringUsageLow=%u\n" + "%s_RingUtilCount=%u\n" + "%s_trCount=%u\n" + "%s_erCount=%u\n" + "%s_totalAoSCount=%u\n" + "%s_busytime=%llu\n", + ipa_clients_strings[rx_ep], + stats.u.rtk[0].commStats.ringFull, + ipa_clients_strings[rx_ep], + stats.u.rtk[0].commStats.ringEmpty, + ipa_clients_strings[rx_ep], + stats.u.rtk[0].commStats.ringUsageHigh, + ipa_clients_strings[rx_ep], + stats.u.rtk[0].commStats.ringUsageLow, + ipa_clients_strings[rx_ep], + stats.u.rtk[0].commStats.RingUtilCount, + ipa_clients_strings[rx_ep], + stats.u.rtk[0].trCount, + ipa_clients_strings[rx_ep], + stats.u.rtk[0].erCount, + ipa_clients_strings[rx_ep], + stats.u.rtk[0].totalAosCount, + ipa_clients_strings[rx_ep], + stats.u.rtk[0].busyTime); + cnt += nbytes; + } else { + nbytes = scnprintf(dbg_buff, IPA_MAX_MSG_LEN, + "Fail to read RTK GSI stats\n"); + cnt += nbytes; + } + break; + default: + ret = -EFAULT; + } + +done: + return simple_read_from_buffer(ubuf, count, ppos, dbg_buff, cnt); +} + +#if IPA_ETH_API_VER >= 2 +static void __ipa_ntn3_client_stats_read(int *cnt, struct ipa_ntn3_client_stats *s, + const char *str_client_tx, const char *str_client_rx) +{ + int nbytes; + + nbytes = scnprintf(dbg_buff + *cnt, IPA_MAX_MSG_LEN - *cnt, + "%s_RP=0x%x\n" + "%s_WP=0x%x\n" + "%s_ntn_pending_db_after_rollback:%u\n" + "%s_msi_db_idx_val:%u\n" + "%s_tx_derr_counter:%u\n" + "%s_ntn_tx_oob_counter:%u\n" + "%s_ntn_accumulated_tres_handled:%u\n" + "%s_ntn_rollbacks_counter:%u\n" + "%s_ntn_msi_db_count:%u\n", + str_client_tx, s->tx_stats.rp, + str_client_tx, s->tx_stats.wp, + str_client_tx, s->tx_stats.pending_db_after_rollback, + str_client_tx, s->tx_stats.msi_db_idx, + str_client_tx, s->tx_stats.derr_cnt, + str_client_tx, s->tx_stats.oob_cnt, + str_client_tx, s->tx_stats.tres_handled, + str_client_tx, s->tx_stats.rollbacks_cnt, + str_client_tx, s->tx_stats.msi_db_cnt); + *cnt += nbytes; + nbytes = scnprintf(dbg_buff + *cnt, IPA_MAX_MSG_LEN - *cnt, + "%s_RP=0x%x\n" + "%s_WP=0x%x\n" + "%s_ntn_pending_db_after_rollback:%u\n" + "%s_msi_db_idx_val:%u\n" + "%s_ntn_rx_chain_counter:%u\n" + "%s_ntn_rx_err_counter:%u\n" + "%s_ntn_accumulated_tres_handled:%u\n" + "%s_ntn_rollbacks_counter:%u\n" + "%s_ntn_msi_db_count:%u\n", + str_client_rx, s->rx_stats.rp, + str_client_rx, s->rx_stats.wp, + str_client_rx, s->rx_stats.pending_db_after_rollback, + str_client_rx, s->rx_stats.msi_db_idx, + str_client_rx, s->rx_stats.chain_cnt, + str_client_rx, s->rx_stats.err_cnt, + str_client_rx, s->rx_stats.tres_handled, + str_client_rx, s->rx_stats.rollbacks_cnt, + str_client_rx, s->rx_stats.msi_db_cnt); + *cnt += nbytes; +} +#endif + +static ssize_t ipa3_eth_read_err_status(struct file *file, + char __user *ubuf, size_t count, loff_t *ppos) +{ + int nbytes; + int cnt = 0; + struct ipa_eth_client *client; + int tx_ep, rx_ep; + struct ipa3_eth_error_stats tx_stats; + struct ipa3_eth_error_stats rx_stats; + int scratch_num; +#if IPA_ETH_API_VER >= 2 + struct ipa_ntn3_client_stats ntn3_stats; + const char *str_client_tx, *str_client_rx; +#endif + + memset(&tx_stats, 0, sizeof(struct ipa3_eth_error_stats)); + memset(&rx_stats, 0, sizeof(struct ipa3_eth_error_stats)); + + if (ipa3_ctx->ipa_hw_type < IPA_HW_v4_5 + && (ipa3_ctx->ipa_hw_type != IPA_HW_v4_1 + || ipa3_ctx->platform_type != IPA_PLAT_TYPE_APQ)) { + nbytes = scnprintf(dbg_buff, IPA_MAX_MSG_LEN, + "This feature only support on IPA4.5+\n"); + cnt += nbytes; + goto done; + } + client = (struct ipa_eth_client *)file->private_data; + + switch (client->client_type) { + case IPA_ETH_CLIENT_AQC107: + fallthrough; + case IPA_ETH_CLIENT_AQC113: + tx_ep = IPA_CLIENT_AQC_ETHERNET_CONS; + rx_ep = IPA_CLIENT_AQC_ETHERNET_PROD; + scratch_num = 7; + fallthrough; + case IPA_ETH_CLIENT_RTK8111K: + fallthrough; + case IPA_ETH_CLIENT_RTK8125B: + tx_ep = IPA_CLIENT_RTK_ETHERNET_CONS; + rx_ep = IPA_CLIENT_RTK_ETHERNET_PROD; + scratch_num = 5; + break; + case IPA_ETH_CLIENT_NTN: + tx_ep = IPA_CLIENT_ETHERNET_CONS; + rx_ep = IPA_CLIENT_ETHERNET_PROD; + scratch_num = 6; +#if IPA_ETH_API_VER >= 2 + case IPA_ETH_CLIENT_NTN3: + + memset(&ntn3_stats, 0, sizeof(ntn3_stats)); + if (strstr(file->f_path.dentry->d_name.name, "0_status")) { + ipa_eth_ntn3_get_status(&ntn3_stats, 0); + str_client_tx = ipa_clients_strings[IPA_CLIENT_ETHERNET_CONS]; + str_client_rx = ipa_clients_strings[IPA_CLIENT_ETHERNET_PROD]; + } else { + ipa_eth_ntn3_get_status(&ntn3_stats, 1); + str_client_tx = ipa_clients_strings[IPA_CLIENT_ETHERNET2_CONS]; + str_client_rx = ipa_clients_strings[IPA_CLIENT_ETHERNET2_PROD]; + } + __ipa_ntn3_client_stats_read(&cnt, &ntn3_stats, str_client_tx, str_client_rx); + goto done; +#endif + fallthrough; + default: + IPAERR("Not supported\n"); + return 0; + } + ipa3_eth_get_status(tx_ep, scratch_num, &tx_stats); + ipa3_eth_get_status(rx_ep, scratch_num, &rx_stats); + + nbytes = scnprintf(dbg_buff, IPA_MAX_MSG_LEN, + "%s_RP=0x%x\n" + "%s_WP=0x%x\n" + "%s_err:%u (scratch %d)\n", + ipa_clients_strings[tx_ep], + tx_stats.rp, + ipa_clients_strings[tx_ep], + tx_stats.wp, + ipa_clients_strings[tx_ep], + tx_stats.err, scratch_num); + cnt += nbytes; + nbytes = scnprintf(dbg_buff + cnt, IPA_MAX_MSG_LEN - cnt, + "%s_RP=0x%x\n" + "%s_WP=0x%x\n" + "%s_err:%u (scratch %d)\n", + ipa_clients_strings[rx_ep], + rx_stats.rp, + ipa_clients_strings[rx_ep], + rx_stats.wp, + ipa_clients_strings[rx_ep], + rx_stats.err, scratch_num); + cnt += nbytes; +done: + return simple_read_from_buffer(ubuf, count, ppos, dbg_buff, cnt); +} + +static const struct file_operations fops_ipa_eth_stats = { + .read = ipa3_eth_read_perf_status, + .open = ipa3_open_dbg, +}; +static const struct file_operations fops_ipa_eth_client_status = { + .read = ipa3_eth_read_err_status, + .open = ipa3_open_dbg, +}; +void ipa3_eth_debugfs_add_node(struct ipa_eth_client *client) +{ + struct dentry *file = NULL; + int type, inst_id; + char name[IPA_RESOURCE_NAME_MAX]; + + if (IS_ERR_OR_NULL(dent_eth)) { + IPAERR("debugs eth root not created\n"); + return; + } + + if (client == NULL) { + IPAERR_RL("invalid input\n"); + return; + } + + type = client->client_type; + inst_id = client->inst_id; + if (type < IPA_ETH_CLIENT_MAX) { + snprintf(name, IPA_RESOURCE_NAME_MAX, + "%s_%d_stats", ipa_eth_clients_strings[type], inst_id); + file = debugfs_create_file(name, IPA_READ_ONLY_MODE, + dent_eth, (void *)client, &fops_ipa_eth_stats); + } + if (!file) { + IPAERR("could not create hw_type file\n"); + return; + } + if (type < IPA_ETH_CLIENT_MAX) { + snprintf(name, IPA_RESOURCE_NAME_MAX, + "%s_%d_status", ipa_eth_clients_strings[type], inst_id); + file = debugfs_create_file(name, IPA_READ_ONLY_MODE, + dent_eth, (void *)client, &fops_ipa_eth_client_status); + } + if (!file) { + IPAERR("could not create hw_type file\n"); + goto fail; + } + return; +fail: + debugfs_remove_recursive(dent_eth); +} +EXPORT_SYMBOL(ipa3_eth_debugfs_add_node); + +#else /* !CONFIG_DEBUG_FS */ +#define INVALID_NO_OF_CHAR (-1) +void ipa3_debugfs_init(void) {} +void ipa3_debugfs_remove(void) {} +int _ipa_read_ep_reg_v3_0(char *buf, int max_len, int pipe) +{ + return INVALID_NO_OF_CHAR; +} +int _ipa_read_ep_reg_v4_0(char *buf, int max_len, int pipe) +{ + return INVALID_NO_OF_CHAR; +} +void ipa3_eth_debugfs_init(void) {} +void ipa3_eth_debugfs_add(struct ipa_eth_client *client) {} +#endif diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_defs.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_defs.h new file mode 100644 index 0000000000..364123f503 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_defs.h @@ -0,0 +1,110 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _IPA_DEFS_H_ +#define _IPA_DEFS_H_ +#include "ipa.h" + +/** + * struct ipa_rt_rule_i - attributes of a routing rule + * @dst: dst "client" + * @hdr_hdl: handle to the dynamic header + it is not an index or an offset + * @hdr_proc_ctx_hdl: handle to header processing context. if it is provided + hdr_hdl shall be 0 + * @attrib: attributes of the rule + * @max_prio: bool switch. is this rule with Max priority? meaning on rule hit, + * IPA will use the rule and will not look for other rules that may have + * higher priority + * @hashable: bool switch. is this rule hashable or not? + * ipa uses hashable rules to cache their hit results to be used in + * consecutive packets + * @retain_hdr: bool switch to instruct IPA core to add back to the packet + * the header removed as part of header removal + * @coalesce: bool to decide whether packets should be coalesced or not + * @enable_stats: is true when we want to enable stats for this + * rt rule. + * @cnt_idx: if enable_stats is 1 and cnt_idx is 0, then cnt_idx + * will be assigned by ipa driver. + * @close_aggr_irq_mod: close aggregation/coalescing and close GSI + * interrupt moderation + * @ttl_update: bool to indicate whether TTL update is needed or not. + * @qos_class: QOS classification value. + * @skip_ingress: bool to skip ingress policing. + */ +struct ipa_rt_rule_i { + enum ipa_client_type dst; + u32 hdr_hdl; + u32 hdr_proc_ctx_hdl; + struct ipa_rule_attrib attrib; + u8 max_prio; + u8 hashable; + u8 retain_hdr; + u8 coalesce; + u8 enable_stats; + u8 cnt_idx; + u8 close_aggr_irq_mod; + u8 ttl_update; + u8 qos_class; + u8 skip_ingress; +}; + +/** + * struct ipa_flt_rule_i - attributes of a filtering rule + * @retain_hdr: bool switch to instruct IPA core to add back to the packet + * the header removed as part of header removal + * @to_uc: bool switch to pass packet to micro-controller + * @action: action field + * @rt_tbl_hdl: handle of table from "get" + * @attrib: attributes of the rule + * @eq_attrib: attributes of the rule in equation form (valid when + * eq_attrib_type is true) + * @rt_tbl_idx: index of RT table referred to by filter rule (valid when + * eq_attrib_type is true and non-exception action) + * @eq_attrib_type: true if equation level form used to specify attributes + * @max_prio: bool switch. is this rule with Max priority? meaning on rule hit, + * IPA will use the rule and will not look for other rules that may have + * higher priority + * @hashable: bool switch. is this rule hashable or not? + * ipa uses hashable rules to cache their hit results to be used in + * consecutive packets + * @rule_id: rule_id to be assigned to the filter rule. In case client specifies + * rule_id as 0 the driver will assign a new rule_id + * @set_metadata: bool switch. should metadata replacement at the NAT block + * take place? + * @pdn_idx: if action is "pass to source\destination NAT" then a comparison + * against the PDN index in the matching PDN entry will take place as an + * additional condition for NAT hit. + * @enable_stats: is true when we want to enable stats for this + * flt rule. + * @cnt_idx: if 0 means disable, otherwise use for index. + * will be assigned by ipa driver. + * @close_aggr_irq_mod: close aggregation/coalescing and close GSI + * interrupt moderation + * @ttl_update: bool to indicate whether TTL update is needed or not. + * @qos_class: QOS classification value. + */ +struct ipa_flt_rule_i { + u8 retain_hdr; + u8 to_uc; + enum ipa_flt_action action; + u32 rt_tbl_hdl; + struct ipa_rule_attrib attrib; + struct ipa_ipfltri_rule_eq eq_attrib; + u32 rt_tbl_idx; + u8 eq_attrib_type; + u8 max_prio; + u8 hashable; + u16 rule_id; + u8 set_metadata; + u8 pdn_idx; + u8 enable_stats; + u8 cnt_idx; + u8 close_aggr_irq_mod; + u8 ttl_update; + u8 qos_class; +}; + +#endif /* _IPA_DEFS_H_ */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_dma.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_dma.c new file mode 100644 index 0000000000..ccc38130b1 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_dma.c @@ -0,0 +1,1250 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved. + */ + + +#include +#include +#include +#include +#include +#include +#include "ipa.h" +#include +#include +#include "ipa_i.h" +#include "gsi.h" + +#define IPA_DMA_POLLING_MIN_SLEEP_RX 1010 +#define IPA_DMA_POLLING_MAX_SLEEP_RX 1050 +#define IPA_DMA_SYS_DESC_MAX_FIFO_SZ 0x7FF8 +#define IPA_DMA_MAX_PKT_SZ 0xFFFF +#define IPA_DMA_DUMMY_BUFF_SZ 8 +#define IPA_DMA_PREFETCH_WA_THRESHOLD 9 + +#define IPADMA_DRV_NAME "ipa_dma" + +#define IPADMA_DBG(fmt, args...) \ + do { \ + pr_debug(IPADMA_DRV_NAME " %s:%d " fmt, \ + __func__, __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf(), \ + IPADMA_DRV_NAME " %s:%d " fmt, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf_low(), \ + IPADMA_DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) + +#define IPADMA_DBG_LOW(fmt, args...) \ + do { \ + pr_debug(IPADMA_DRV_NAME " %s:%d " fmt, \ + __func__, __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf_low(), \ + IPADMA_DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) + +#define IPADMA_ERR(fmt, args...) \ + do { \ + pr_err(IPADMA_DRV_NAME " %s:%d " fmt, \ + __func__, __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf(), \ + IPADMA_DRV_NAME " %s:%d " fmt, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf_low(), \ + IPADMA_DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) + +#define IPADMA_FUNC_ENTRY() \ + IPADMA_DBG_LOW("ENTRY\n") + +#define IPADMA_FUNC_EXIT() \ + IPADMA_DBG_LOW("EXIT\n") + +#ifdef CONFIG_DEBUG_FS +#define IPADMA_MAX_MSG_LEN 1024 +static char dbg_buff[IPADMA_MAX_MSG_LEN]; +static void ipa3_dma_debugfs_init(void); +static void ipa3_dma_debugfs_destroy(void); +#else +static void ipa3_dma_debugfs_init(void) {} +static void ipa3_dma_debugfs_destroy(void) {} +#endif + +/** + * struct ipa3_dma_ctx -IPADMA driver context information + * @enable_ref_cnt: ipa dma enable reference count + * @destroy_pending: destroy ipa_dma after handling all pending memcpy + * @ipa_dma_xfer_wrapper_cache: cache of ipa3_dma_xfer_wrapper structs + * @sync_lock: lock for synchronisation in sync_memcpy + * @async_lock: lock for synchronisation in async_memcpy + * @enable_lock: lock for is_enabled + * @pending_lock: lock for synchronize is_enable and pending_cnt + * @done: no pending works-ipadma can be destroyed + * @ipa_dma_sync_prod_hdl: handle of sync memcpy producer + * @ipa_dma_async_prod_hdl:handle of async memcpy producer + * @ipa_dma_sync_cons_hdl: handle of sync memcpy consumer + * @sync_memcpy_pending_cnt: number of pending sync memcopy operations + * @async_memcpy_pending_cnt: number of pending async memcopy operations + * @uc_memcpy_pending_cnt: number of pending uc memcopy operations + * @total_sync_memcpy: total number of sync memcpy (statistics) + * @total_async_memcpy: total number of async memcpy (statistics) + * @total_uc_memcpy: total number of uc memcpy (statistics) + */ +struct ipa3_dma_ctx { + unsigned int enable_ref_cnt; + bool destroy_pending; + struct kmem_cache *ipa_dma_xfer_wrapper_cache; + struct mutex sync_lock; + spinlock_t async_lock; + struct mutex enable_lock; + spinlock_t pending_lock; + struct completion done; + u32 ipa_dma_sync_prod_hdl; + u32 ipa_dma_async_prod_hdl; + u32 ipa_dma_sync_cons_hdl; + u32 ipa_dma_async_cons_hdl; + atomic_t sync_memcpy_pending_cnt; + atomic_t async_memcpy_pending_cnt; + atomic_t uc_memcpy_pending_cnt; + atomic_t total_sync_memcpy; + atomic_t total_async_memcpy; + atomic_t total_uc_memcpy; + struct ipa_mem_buffer ipa_dma_dummy_src_sync; + struct ipa_mem_buffer ipa_dma_dummy_dst_sync; + struct ipa_mem_buffer ipa_dma_dummy_src_async; + struct ipa_mem_buffer ipa_dma_dummy_dst_async; +}; +static struct ipa3_dma_ctx *ipa3_dma_ctx; + +/** + * struct ipa_dma_init_refcnt_ctrl -IPADMA driver init control information + * @ref_cnt: reference count for initialization operations + * @lock: lock for the reference count + */ +struct ipa_dma_init_refcnt_ctrl { + unsigned int ref_cnt; + struct mutex lock; +}; +static struct ipa_dma_init_refcnt_ctrl *ipa_dma_init_refcnt_ctrl; + +/** + * ipa3_dma_setup() - One time setup for IPA DMA + * + * This function should be called once to setup ipa dma + * by creating the init reference count controller + * + * Return codes: 0: success + * Negative value: failure + */ +int ipa3_dma_setup(void) +{ + IPADMA_FUNC_ENTRY(); + + if (ipa_dma_init_refcnt_ctrl) { + IPADMA_ERR("Setup already done\n"); + return -EFAULT; + } + + ipa_dma_init_refcnt_ctrl = + kzalloc(sizeof(*(ipa_dma_init_refcnt_ctrl)), GFP_KERNEL); + + if (!ipa_dma_init_refcnt_ctrl) { + IPADMA_ERR("kzalloc error.\n"); + return -ENOMEM; + } + + mutex_init(&ipa_dma_init_refcnt_ctrl->lock); + + IPADMA_FUNC_EXIT(); + return 0; +} + +/** + * ipa3_dma_shutdown() - Clear setup operations. + * + * Cleanup for the setup function. + * Should be called during IPA driver unloading. + * It assumes all ipa_dma operations are done and ipa_dma is destroyed. + * + * Return codes: None. + */ +void ipa3_dma_shutdown(void) +{ + IPADMA_FUNC_ENTRY(); + + if (!ipa_dma_init_refcnt_ctrl) + return; + + kfree(ipa_dma_init_refcnt_ctrl); + ipa_dma_init_refcnt_ctrl = NULL; + + IPADMA_FUNC_EXIT(); +} + +/** + * ipa_dma_init() -Initialize IPADMA. + * + * This function initialize all IPADMA internal data and connect in dma: + * MEMCPY_DMA_SYNC_PROD ->MEMCPY_DMA_SYNC_CONS + * MEMCPY_DMA_ASYNC_PROD->MEMCPY_DMA_SYNC_CONS + * + * Can be executed several times (re-entrant) + * + * Return codes: 0: success + * -EFAULT: Mismatch between context existence and init ref_cnt + * -EINVAL: IPA driver is not initialized + * -ENOMEM: allocating memory error + * -EPERM: pipe connection failed + */ +int ipa_dma_init(void) +{ + struct ipa3_dma_ctx *ipa_dma_ctx_t; + struct ipa_sys_connect_params sys_in; + int res = 0; + int sync_sz; + int async_sz; + + IPADMA_FUNC_ENTRY(); + + if (!ipa_dma_init_refcnt_ctrl) { + IPADMA_ERR("Setup isn't done yet!\n"); + return -EINVAL; + } + + mutex_lock(&ipa_dma_init_refcnt_ctrl->lock); + if (ipa_dma_init_refcnt_ctrl->ref_cnt > 0) { + IPADMA_DBG("Already initialized refcnt=%d\n", + ipa_dma_init_refcnt_ctrl->ref_cnt); + if (!ipa3_dma_ctx) { + IPADMA_ERR("Context missing. refcnt=%d\n", + ipa_dma_init_refcnt_ctrl->ref_cnt); + res = -EFAULT; + } else { + ipa_dma_init_refcnt_ctrl->ref_cnt++; + } + goto init_unlock; + } + + if (ipa3_dma_ctx) { + IPADMA_ERR("Context already exist\n"); + res = -EFAULT; + goto init_unlock; + } + + if (!ipa_is_ready()) { + IPADMA_ERR("IPA is not ready yet\n"); + res = -EINVAL; + goto init_unlock; + } + + ipa_dma_ctx_t = kzalloc(sizeof(*(ipa3_dma_ctx)), GFP_KERNEL); + + if (!ipa_dma_ctx_t) { + res = -ENOMEM; + goto init_unlock; + } + + ipa_dma_ctx_t->ipa_dma_xfer_wrapper_cache = + kmem_cache_create("IPA DMA XFER WRAPPER", + sizeof(struct ipa3_dma_xfer_wrapper), 0, 0, NULL); + if (!ipa_dma_ctx_t->ipa_dma_xfer_wrapper_cache) { + IPAERR(":failed to create ipa dma xfer wrapper cache.\n"); + res = -ENOMEM; + goto fail_mem_ctrl; + } + + mutex_init(&ipa_dma_ctx_t->enable_lock); + spin_lock_init(&ipa_dma_ctx_t->async_lock); + mutex_init(&ipa_dma_ctx_t->sync_lock); + spin_lock_init(&ipa_dma_ctx_t->pending_lock); + init_completion(&ipa_dma_ctx_t->done); + ipa_dma_ctx_t->enable_ref_cnt = 0; + ipa_dma_ctx_t->destroy_pending = false; + atomic_set(&ipa_dma_ctx_t->async_memcpy_pending_cnt, 0); + atomic_set(&ipa_dma_ctx_t->sync_memcpy_pending_cnt, 0); + atomic_set(&ipa_dma_ctx_t->uc_memcpy_pending_cnt, 0); + atomic_set(&ipa_dma_ctx_t->total_async_memcpy, 0); + atomic_set(&ipa_dma_ctx_t->total_sync_memcpy, 0); + atomic_set(&ipa_dma_ctx_t->total_uc_memcpy, 0); + + sync_sz = IPA_SYS_DESC_FIFO_SZ; + async_sz = IPA_DMA_SYS_DESC_MAX_FIFO_SZ; + /* + * for ipav3.5 we need to double the rings and allocate dummy buffers + * in order to apply the prefetch WA + */ + if (ipa_get_hw_type() == IPA_HW_v3_5) { + sync_sz *= 2; + async_sz *= 2; + + ipa_dma_ctx_t->ipa_dma_dummy_src_sync.base = + dma_alloc_coherent(ipa3_ctx->pdev, + IPA_DMA_DUMMY_BUFF_SZ * 4, + &ipa_dma_ctx_t->ipa_dma_dummy_src_sync.phys_base, + GFP_KERNEL); + + if (!ipa_dma_ctx_t->ipa_dma_dummy_src_sync.base) { + IPAERR("DMA alloc fail %d bytes for prefetch WA\n", + IPA_DMA_DUMMY_BUFF_SZ); + res = -ENOMEM; + goto fail_alloc_dummy; + } + + ipa_dma_ctx_t->ipa_dma_dummy_dst_sync.base = + ipa_dma_ctx_t->ipa_dma_dummy_src_sync.base + + IPA_DMA_DUMMY_BUFF_SZ; + ipa_dma_ctx_t->ipa_dma_dummy_dst_sync.phys_base = + ipa_dma_ctx_t->ipa_dma_dummy_src_sync.phys_base + + IPA_DMA_DUMMY_BUFF_SZ; + ipa_dma_ctx_t->ipa_dma_dummy_src_async.base = + ipa_dma_ctx_t->ipa_dma_dummy_dst_sync.base + + IPA_DMA_DUMMY_BUFF_SZ; + ipa_dma_ctx_t->ipa_dma_dummy_src_async.phys_base = + ipa_dma_ctx_t->ipa_dma_dummy_dst_sync.phys_base + + IPA_DMA_DUMMY_BUFF_SZ; + ipa_dma_ctx_t->ipa_dma_dummy_dst_async.base = + ipa_dma_ctx_t->ipa_dma_dummy_src_async.base + + IPA_DMA_DUMMY_BUFF_SZ; + ipa_dma_ctx_t->ipa_dma_dummy_dst_async.phys_base = + ipa_dma_ctx_t->ipa_dma_dummy_src_async.phys_base + + IPA_DMA_DUMMY_BUFF_SZ; + } + + /* IPADMA SYNC PROD-source for sync memcpy */ + memset(&sys_in, 0, sizeof(struct ipa_sys_connect_params)); + sys_in.client = IPA_CLIENT_MEMCPY_DMA_SYNC_PROD; + sys_in.desc_fifo_sz = sync_sz; + sys_in.ipa_ep_cfg.mode.mode = IPA_DMA; + sys_in.ipa_ep_cfg.mode.dst = IPA_CLIENT_MEMCPY_DMA_SYNC_CONS; + sys_in.skip_ep_cfg = false; + if (ipa_setup_sys_pipe(&sys_in, + &ipa_dma_ctx_t->ipa_dma_sync_prod_hdl)) { + IPADMA_ERR(":setup sync prod pipe failed\n"); + res = -EPERM; + goto fail_sync_prod; + } + + /* IPADMA SYNC CONS-destination for sync memcpy */ + memset(&sys_in, 0, sizeof(struct ipa_sys_connect_params)); + sys_in.client = IPA_CLIENT_MEMCPY_DMA_SYNC_CONS; + sys_in.desc_fifo_sz = sync_sz; + sys_in.skip_ep_cfg = false; + sys_in.ipa_ep_cfg.mode.mode = IPA_BASIC; + sys_in.notify = NULL; + sys_in.priv = NULL; + if (ipa_setup_sys_pipe(&sys_in, + &ipa_dma_ctx_t->ipa_dma_sync_cons_hdl)) { + IPADMA_ERR(":setup sync cons pipe failed.\n"); + res = -EPERM; + goto fail_sync_cons; + } + + IPADMA_DBG("SYNC MEMCPY pipes are connected\n"); + + /* IPADMA ASYNC PROD-source for sync memcpy */ + memset(&sys_in, 0, sizeof(struct ipa_sys_connect_params)); + sys_in.client = IPA_CLIENT_MEMCPY_DMA_ASYNC_PROD; + sys_in.desc_fifo_sz = async_sz; + sys_in.ipa_ep_cfg.mode.mode = IPA_DMA; + sys_in.ipa_ep_cfg.mode.dst = IPA_CLIENT_MEMCPY_DMA_ASYNC_CONS; + sys_in.skip_ep_cfg = false; + sys_in.notify = NULL; + if (ipa_setup_sys_pipe(&sys_in, + &ipa_dma_ctx_t->ipa_dma_async_prod_hdl)) { + IPADMA_ERR(":setup async prod pipe failed.\n"); + res = -EPERM; + goto fail_async_prod; + } + + /* IPADMA ASYNC CONS-destination for sync memcpy */ + memset(&sys_in, 0, sizeof(struct ipa_sys_connect_params)); + sys_in.client = IPA_CLIENT_MEMCPY_DMA_ASYNC_CONS; + sys_in.desc_fifo_sz = async_sz; + sys_in.skip_ep_cfg = false; + sys_in.ipa_ep_cfg.mode.mode = IPA_BASIC; + sys_in.notify = ipa3_dma_async_memcpy_notify_cb; + sys_in.priv = NULL; + if (ipa_setup_sys_pipe(&sys_in, + &ipa_dma_ctx_t->ipa_dma_async_cons_hdl)) { + IPADMA_ERR(":setup async cons pipe failed.\n"); + res = -EPERM; + goto fail_async_cons; + } + ipa3_dma_debugfs_init(); + ipa3_dma_ctx = ipa_dma_ctx_t; + ipa_dma_init_refcnt_ctrl->ref_cnt = 1; + IPADMA_DBG("ASYNC MEMCPY pipes are connected\n"); + + IPADMA_FUNC_EXIT(); + goto init_unlock; + +fail_async_cons: + ipa_teardown_sys_pipe(ipa_dma_ctx_t->ipa_dma_async_prod_hdl); +fail_async_prod: + ipa_teardown_sys_pipe(ipa_dma_ctx_t->ipa_dma_sync_cons_hdl); +fail_sync_cons: + ipa_teardown_sys_pipe(ipa_dma_ctx_t->ipa_dma_sync_prod_hdl); +fail_sync_prod: + dma_free_coherent(ipa3_ctx->pdev, IPA_DMA_DUMMY_BUFF_SZ * 4, + ipa_dma_ctx_t->ipa_dma_dummy_src_sync.base, + ipa_dma_ctx_t->ipa_dma_dummy_src_sync.phys_base); +fail_alloc_dummy: + kmem_cache_destroy(ipa_dma_ctx_t->ipa_dma_xfer_wrapper_cache); +fail_mem_ctrl: + kfree(ipa_dma_ctx_t); + ipa3_dma_ctx = NULL; +init_unlock: + mutex_unlock(&ipa_dma_init_refcnt_ctrl->lock); + return res; + +} +EXPORT_SYMBOL(ipa_dma_init); + +/** + * ipa_dma_enable() -Vote for IPA clocks. + * + * Can be executed several times (re-entrant) + * + *Return codes: 0: success + * -EINVAL: IPADMA is not initialized + */ +int ipa_dma_enable(void) +{ + IPADMA_FUNC_ENTRY(); + if ((ipa3_dma_ctx == NULL) || + (ipa_dma_init_refcnt_ctrl->ref_cnt < 1)) { + IPADMA_ERR("IPADMA isn't initialized, can't enable\n"); + return -EINVAL; + } + mutex_lock(&ipa3_dma_ctx->enable_lock); + if (ipa3_dma_ctx->enable_ref_cnt > 0) { + IPADMA_ERR("Already enabled refcnt=%d\n", + ipa3_dma_ctx->enable_ref_cnt); + ipa3_dma_ctx->enable_ref_cnt++; + mutex_unlock(&ipa3_dma_ctx->enable_lock); + return 0; + } + IPA_ACTIVE_CLIENTS_INC_SPECIAL("DMA"); + ipa3_dma_ctx->enable_ref_cnt = 1; + mutex_unlock(&ipa3_dma_ctx->enable_lock); + + IPADMA_FUNC_EXIT(); + return 0; +} +EXPORT_SYMBOL(ipa_dma_enable); + +static bool ipa3_dma_work_pending(void) +{ + if (atomic_read(&ipa3_dma_ctx->sync_memcpy_pending_cnt)) { + IPADMA_DBG("pending sync\n"); + return true; + } + if (atomic_read(&ipa3_dma_ctx->async_memcpy_pending_cnt)) { + IPADMA_DBG("pending async\n"); + return true; + } + if (atomic_read(&ipa3_dma_ctx->uc_memcpy_pending_cnt)) { + IPADMA_DBG("pending uc\n"); + return true; + } + IPADMA_DBG_LOW("no pending work\n"); + return false; +} + +/** + * ipa_dma_disable()- Unvote for IPA clocks. + * + * enter to power save mode. + * + * Return codes: 0: success + * -EINVAL: IPADMA is not initialized + * -EPERM: Operation not permitted as ipa_dma is already + * diabled + * -EFAULT: can not disable ipa_dma as there are pending + * memcopy works + */ +int ipa_dma_disable(void) +{ + unsigned long flags; + int res = 0; + bool dec_clks = false; + + IPADMA_FUNC_ENTRY(); + if ((ipa3_dma_ctx == NULL) || + (ipa_dma_init_refcnt_ctrl->ref_cnt < 1)) { + IPADMA_ERR("IPADMA isn't initialized, can't disable\n"); + return -EINVAL; + } + mutex_lock(&ipa3_dma_ctx->enable_lock); + spin_lock_irqsave(&ipa3_dma_ctx->pending_lock, flags); + if (ipa3_dma_ctx->enable_ref_cnt > 1) { + IPADMA_DBG("Multiple enablement done. refcnt=%d\n", + ipa3_dma_ctx->enable_ref_cnt); + ipa3_dma_ctx->enable_ref_cnt--; + goto completed; + } + + if (ipa3_dma_ctx->enable_ref_cnt == 0) { + IPADMA_ERR("Already disabled\n"); + res = -EPERM; + goto completed; + } + + if (ipa3_dma_work_pending()) { + IPADMA_ERR("There is pending work, can't disable.\n"); + res = -EFAULT; + goto completed; + } + ipa3_dma_ctx->enable_ref_cnt = 0; + dec_clks = true; + IPADMA_FUNC_EXIT(); + +completed: + spin_unlock_irqrestore(&ipa3_dma_ctx->pending_lock, flags); + if (dec_clks) + IPA_ACTIVE_CLIENTS_DEC_SPECIAL("DMA"); + mutex_unlock(&ipa3_dma_ctx->enable_lock); + return res; +} +EXPORT_SYMBOL(ipa_dma_disable); + +/** + * ipa_dma_sync_memcpy()- Perform synchronous memcpy using IPA. + * + * @dest: physical address to store the copied data. + * @src: physical address of the source data to copy. + * @len: number of bytes to copy. + * + * Return codes: 0: success + * -EINVAL: invalid params + * -EPERM: operation not permitted as ipa_dma isn't enable or + * initialized + * -gsi_status : on GSI failures + * -EFAULT: other + */ +int ipa_dma_sync_memcpy(u64 dest, u64 src, int len) +{ + int ep_idx; + int res; + int i = 0; + struct ipa3_sys_context *cons_sys; + struct ipa3_sys_context *prod_sys; + struct ipa3_dma_xfer_wrapper *xfer_descr = NULL; + struct ipa3_dma_xfer_wrapper *head_descr = NULL; + struct gsi_xfer_elem prod_xfer_elem; + struct gsi_xfer_elem cons_xfer_elem; + struct gsi_chan_xfer_notify gsi_notify; + unsigned long flags; + bool stop_polling = false; + bool prefetch_wa = false; + + IPADMA_FUNC_ENTRY(); + IPADMA_DBG_LOW("dest = 0x%llx, src = 0x%llx, len = %d\n", + dest, src, len); + if (ipa3_dma_ctx == NULL) { + IPADMA_ERR("IPADMA isn't initialized, can't memcpy\n"); + return -EPERM; + } + if ((max(src, dest) - min(src, dest)) < len) { + IPADMA_ERR("invalid addresses - overlapping buffers\n"); + return -EINVAL; + } + if (len > IPA_DMA_MAX_PKT_SZ || len <= 0) { + IPADMA_ERR("invalid len, %d\n", len); + return -EINVAL; + } + spin_lock_irqsave(&ipa3_dma_ctx->pending_lock, flags); + if (!ipa3_dma_ctx->enable_ref_cnt) { + IPADMA_ERR("can't memcpy, IPADMA isn't enabled\n"); + spin_unlock_irqrestore(&ipa3_dma_ctx->pending_lock, flags); + return -EPERM; + } + atomic_inc(&ipa3_dma_ctx->sync_memcpy_pending_cnt); + spin_unlock_irqrestore(&ipa3_dma_ctx->pending_lock, flags); + + ep_idx = ipa_get_ep_mapping(IPA_CLIENT_MEMCPY_DMA_SYNC_CONS); + if (-1 == ep_idx) { + IPADMA_ERR("Client %u is not mapped\n", + IPA_CLIENT_MEMCPY_DMA_SYNC_CONS); + return -EFAULT; + } + cons_sys = ipa3_ctx->ep[ep_idx].sys; + + ep_idx = ipa_get_ep_mapping(IPA_CLIENT_MEMCPY_DMA_SYNC_PROD); + if (-1 == ep_idx) { + IPADMA_ERR("Client %u is not mapped\n", + IPA_CLIENT_MEMCPY_DMA_SYNC_PROD); + return -EFAULT; + } + prod_sys = ipa3_ctx->ep[ep_idx].sys; + + xfer_descr = kmem_cache_zalloc(ipa3_dma_ctx->ipa_dma_xfer_wrapper_cache, + GFP_KERNEL); + if (!xfer_descr) { + IPADMA_ERR("failed to alloc xfer descr wrapper\n"); + res = -ENOMEM; + goto fail_mem_alloc; + } + xfer_descr->phys_addr_dest = dest; + xfer_descr->phys_addr_src = src; + xfer_descr->len = len; + init_completion(&xfer_descr->xfer_done); + + mutex_lock(&ipa3_dma_ctx->sync_lock); + list_add_tail(&xfer_descr->link, &cons_sys->head_desc_list); + cons_sys->len++; + cons_xfer_elem.addr = dest; + cons_xfer_elem.len = len; + cons_xfer_elem.type = GSI_XFER_ELEM_DATA; + cons_xfer_elem.flags = GSI_XFER_FLAG_EOT; + + prod_xfer_elem.addr = src; + prod_xfer_elem.len = len; + prod_xfer_elem.type = GSI_XFER_ELEM_DATA; + prod_xfer_elem.xfer_user_data = NULL; + + /* + * when copy is less than 9B we need to chain another dummy + * copy so the total size will be larger (for ipav3.5) + * for the consumer we have to prepare an additional credit + */ + prefetch_wa = ((ipa_get_hw_type() == IPA_HW_v3_5) && + len < IPA_DMA_PREFETCH_WA_THRESHOLD); + if (prefetch_wa) { + cons_xfer_elem.xfer_user_data = NULL; + res = gsi_queue_xfer(cons_sys->ep->gsi_chan_hdl, 1, + &cons_xfer_elem, false); + if (res) { + IPADMA_ERR( + "Failed: gsi_queue_xfer dest descr res:%d\n", + res); + goto fail_send; + } + cons_xfer_elem.addr = + ipa3_dma_ctx->ipa_dma_dummy_dst_sync.phys_base; + cons_xfer_elem.len = IPA_DMA_DUMMY_BUFF_SZ; + cons_xfer_elem.type = GSI_XFER_ELEM_DATA; + cons_xfer_elem.flags = GSI_XFER_FLAG_EOT; + cons_xfer_elem.xfer_user_data = xfer_descr; + res = gsi_queue_xfer(cons_sys->ep->gsi_chan_hdl, 1, + &cons_xfer_elem, true); + if (res) { + IPADMA_ERR( + "Failed: gsi_queue_xfer dummy dest descr res:%d\n", + res); + goto fail_send; + } + prod_xfer_elem.flags = GSI_XFER_FLAG_CHAIN; + res = gsi_queue_xfer(prod_sys->ep->gsi_chan_hdl, 1, + &prod_xfer_elem, false); + if (res) { + IPADMA_ERR( + "Failed: gsi_queue_xfer src descr res:%d\n", + res); + ipa_assert(); + goto fail_send; + } + prod_xfer_elem.addr = + ipa3_dma_ctx->ipa_dma_dummy_src_sync.phys_base; + prod_xfer_elem.len = IPA_DMA_DUMMY_BUFF_SZ; + prod_xfer_elem.type = GSI_XFER_ELEM_DATA; + prod_xfer_elem.flags = GSI_XFER_FLAG_EOT; + prod_xfer_elem.xfer_user_data = NULL; + res = gsi_queue_xfer(prod_sys->ep->gsi_chan_hdl, 1, + &prod_xfer_elem, true); + if (res) { + IPADMA_ERR( + "Failed: gsi_queue_xfer dummy src descr res:%d\n", + res); + ipa_assert(); + goto fail_send; + } + } else { + cons_xfer_elem.xfer_user_data = xfer_descr; + res = gsi_queue_xfer(cons_sys->ep->gsi_chan_hdl, 1, + &cons_xfer_elem, true); + if (res) { + IPADMA_ERR( + "Failed: gsi_queue_xfer dest descr res:%d\n", + res); + goto fail_send; + } + prod_xfer_elem.flags = GSI_XFER_FLAG_EOT; + res = gsi_queue_xfer(prod_sys->ep->gsi_chan_hdl, 1, + &prod_xfer_elem, true); + if (res) { + IPADMA_ERR( + "Failed: gsi_queue_xfer src descr res:%d\n", + res); + ipa_assert(); + goto fail_send; + } + } + head_descr = list_first_entry(&cons_sys->head_desc_list, + struct ipa3_dma_xfer_wrapper, link); + + /* in case we are not the head of the list, wait for head to wake us */ + if (xfer_descr != head_descr) { + mutex_unlock(&ipa3_dma_ctx->sync_lock); + wait_for_completion(&xfer_descr->xfer_done); + mutex_lock(&ipa3_dma_ctx->sync_lock); + head_descr = list_first_entry(&cons_sys->head_desc_list, + struct ipa3_dma_xfer_wrapper, link); + /* Unexpected transfer sent from HW */ + ipa_assert_on(xfer_descr != head_descr); + } + mutex_unlock(&ipa3_dma_ctx->sync_lock); + + do { + /* wait for transfer to complete */ + res = gsi_poll_channel(cons_sys->ep->gsi_chan_hdl, + &gsi_notify); + if (res == GSI_STATUS_SUCCESS) + stop_polling = true; + else if (res != GSI_STATUS_POLL_EMPTY) + IPADMA_ERR( + "Failed: gsi_poll_chanel, returned %d loop#:%d\n", + res, i); + usleep_range(IPA_DMA_POLLING_MIN_SLEEP_RX, + IPA_DMA_POLLING_MAX_SLEEP_RX); + i++; + } while (!stop_polling); + + /* for prefetch WA we will receive the length of the dummy + * transfer in the event (because it is the second element) + */ + if (prefetch_wa) + ipa_assert_on(gsi_notify.bytes_xfered != + IPA_DMA_DUMMY_BUFF_SZ); + else + ipa_assert_on(len != gsi_notify.bytes_xfered); + + ipa_assert_on(dest != ((struct ipa3_dma_xfer_wrapper *) + (gsi_notify.xfer_user_data))->phys_addr_dest); + + mutex_lock(&ipa3_dma_ctx->sync_lock); + list_del(&head_descr->link); + cons_sys->len--; + kmem_cache_free(ipa3_dma_ctx->ipa_dma_xfer_wrapper_cache, xfer_descr); + /* wake the head of the list */ + if (!list_empty(&cons_sys->head_desc_list)) { + head_descr = list_first_entry(&cons_sys->head_desc_list, + struct ipa3_dma_xfer_wrapper, link); + complete(&head_descr->xfer_done); + } + mutex_unlock(&ipa3_dma_ctx->sync_lock); + + atomic_inc(&ipa3_dma_ctx->total_sync_memcpy); + atomic_dec(&ipa3_dma_ctx->sync_memcpy_pending_cnt); + if (ipa3_dma_ctx->destroy_pending && !ipa3_dma_work_pending()) + complete(&ipa3_dma_ctx->done); + + IPADMA_FUNC_EXIT(); + return res; + +fail_send: + list_del(&xfer_descr->link); + cons_sys->len--; + mutex_unlock(&ipa3_dma_ctx->sync_lock); + kmem_cache_free(ipa3_dma_ctx->ipa_dma_xfer_wrapper_cache, xfer_descr); +fail_mem_alloc: + atomic_dec(&ipa3_dma_ctx->sync_memcpy_pending_cnt); + if (ipa3_dma_ctx->destroy_pending && !ipa3_dma_work_pending()) + complete(&ipa3_dma_ctx->done); + return res; +} +EXPORT_SYMBOL(ipa_dma_sync_memcpy); + +/** + * ipa_dma_async_memcpy()- Perform asynchronous memcpy using IPA. + * + * @dest: physical address to store the copied data. + * @src: physical address of the source data to copy. + * @len: number of bytes to copy. + * @user_cb: callback function to notify the client when the copy was done. + * @user_param: cookie for user_cb. + * + * Return codes: 0: success + * -EINVAL: invalid params + * -EPERM: operation not permitted as ipa_dma isn't enable or + * initialized + * -gsi_status : on GSI failures + * -EFAULT: descr fifo is full. + */ +int ipa_dma_async_memcpy(u64 dest, u64 src, int len, + void (*user_cb)(void *user1), void *user_param) +{ + int ep_idx; + int res = 0; + struct ipa3_dma_xfer_wrapper *xfer_descr = NULL; + struct ipa3_sys_context *prod_sys; + struct ipa3_sys_context *cons_sys; + struct gsi_xfer_elem xfer_elem_cons, xfer_elem_prod; + unsigned long flags; + + IPADMA_FUNC_ENTRY(); + IPADMA_DBG_LOW("dest = 0x%llx, src = 0x%llx, len = %d\n", + dest, src, len); + if (ipa3_dma_ctx == NULL) { + IPADMA_ERR("IPADMA isn't initialized, can't memcpy\n"); + return -EPERM; + } + if ((max(src, dest) - min(src, dest)) < len) { + IPADMA_ERR("invalid addresses - overlapping buffers\n"); + return -EINVAL; + } + if (len > IPA_DMA_MAX_PKT_SZ || len <= 0) { + IPADMA_ERR("invalid len, %d\n", len); + return -EINVAL; + } + if (!user_cb) { + IPADMA_ERR("null pointer: user_cb\n"); + return -EINVAL; + } + spin_lock_irqsave(&ipa3_dma_ctx->pending_lock, flags); + if (!ipa3_dma_ctx->enable_ref_cnt) { + IPADMA_ERR("can't memcpy, IPA_DMA isn't enabled\n"); + spin_unlock_irqrestore(&ipa3_dma_ctx->pending_lock, flags); + return -EPERM; + } + atomic_inc(&ipa3_dma_ctx->async_memcpy_pending_cnt); + spin_unlock_irqrestore(&ipa3_dma_ctx->pending_lock, flags); + + ep_idx = ipa_get_ep_mapping(IPA_CLIENT_MEMCPY_DMA_ASYNC_CONS); + if (-1 == ep_idx) { + IPADMA_ERR("Client %u is not mapped\n", + IPA_CLIENT_MEMCPY_DMA_ASYNC_CONS); + return -EFAULT; + } + cons_sys = ipa3_ctx->ep[ep_idx].sys; + + ep_idx = ipa_get_ep_mapping(IPA_CLIENT_MEMCPY_DMA_ASYNC_PROD); + if (-1 == ep_idx) { + IPADMA_ERR("Client %u is not mapped\n", + IPA_CLIENT_MEMCPY_DMA_ASYNC_PROD); + return -EFAULT; + } + prod_sys = ipa3_ctx->ep[ep_idx].sys; + + xfer_descr = kmem_cache_zalloc(ipa3_dma_ctx->ipa_dma_xfer_wrapper_cache, + GFP_KERNEL); + if (!xfer_descr) { + res = -ENOMEM; + goto fail_mem_alloc; + } + xfer_descr->phys_addr_dest = dest; + xfer_descr->phys_addr_src = src; + xfer_descr->len = len; + xfer_descr->callback = user_cb; + xfer_descr->user1 = user_param; + + spin_lock_irqsave(&ipa3_dma_ctx->async_lock, flags); + list_add_tail(&xfer_descr->link, &cons_sys->head_desc_list); + cons_sys->len++; + /* + * when copy is less than 9B we need to chain another dummy + * copy so the total size will be larger (for ipav3.5) + */ + if ((ipa_get_hw_type() == IPA_HW_v3_5) && len < + IPA_DMA_PREFETCH_WA_THRESHOLD) { + xfer_elem_cons.addr = dest; + xfer_elem_cons.len = len; + xfer_elem_cons.type = GSI_XFER_ELEM_DATA; + xfer_elem_cons.flags = GSI_XFER_FLAG_EOT; + xfer_elem_cons.xfer_user_data = NULL; + res = gsi_queue_xfer(cons_sys->ep->gsi_chan_hdl, 1, + &xfer_elem_cons, false); + if (res) { + IPADMA_ERR( + "Failed: gsi_queue_xfer on dest descr res: %d\n", + res); + goto fail_send; + } + xfer_elem_cons.addr = + ipa3_dma_ctx->ipa_dma_dummy_dst_async.phys_base; + xfer_elem_cons.len = IPA_DMA_DUMMY_BUFF_SZ; + xfer_elem_cons.type = GSI_XFER_ELEM_DATA; + xfer_elem_cons.flags = GSI_XFER_FLAG_EOT; + xfer_elem_cons.xfer_user_data = xfer_descr; + res = gsi_queue_xfer(cons_sys->ep->gsi_chan_hdl, 1, + &xfer_elem_cons, true); + if (res) { + IPADMA_ERR( + "Failed: gsi_queue_xfer on dummy dest descr res: %d\n", + res); + goto fail_send; + } + + xfer_elem_prod.addr = src; + xfer_elem_prod.len = len; + xfer_elem_prod.type = GSI_XFER_ELEM_DATA; + xfer_elem_prod.flags = GSI_XFER_FLAG_CHAIN; + xfer_elem_prod.xfer_user_data = NULL; + res = gsi_queue_xfer(prod_sys->ep->gsi_chan_hdl, 1, + &xfer_elem_prod, false); + if (res) { + IPADMA_ERR( + "Failed: gsi_queue_xfer on src descr res: %d\n", + res); + ipa_assert(); + goto fail_send; + } + xfer_elem_prod.addr = + ipa3_dma_ctx->ipa_dma_dummy_src_async.phys_base; + xfer_elem_prod.len = IPA_DMA_DUMMY_BUFF_SZ; + xfer_elem_prod.type = GSI_XFER_ELEM_DATA; + xfer_elem_prod.flags = GSI_XFER_FLAG_EOT; + xfer_elem_prod.xfer_user_data = NULL; + res = gsi_queue_xfer(prod_sys->ep->gsi_chan_hdl, 1, + &xfer_elem_prod, true); + if (res) { + IPADMA_ERR( + "Failed: gsi_queue_xfer on dummy src descr res: %d\n", + res); + ipa_assert(); + goto fail_send; + } + } else { + + xfer_elem_cons.addr = dest; + xfer_elem_cons.len = len; + xfer_elem_cons.type = GSI_XFER_ELEM_DATA; + xfer_elem_cons.flags = GSI_XFER_FLAG_EOT; + xfer_elem_cons.xfer_user_data = xfer_descr; + res = gsi_queue_xfer(cons_sys->ep->gsi_chan_hdl, 1, + &xfer_elem_cons, true); + if (res) { + IPADMA_ERR( + "Failed: gsi_queue_xfer on dummy dest descr res: %d\n", + res); + ipa_assert(); + goto fail_send; + } + xfer_elem_prod.addr = src; + xfer_elem_prod.len = len; + xfer_elem_prod.type = GSI_XFER_ELEM_DATA; + xfer_elem_prod.flags = GSI_XFER_FLAG_EOT; + xfer_elem_prod.xfer_user_data = NULL; + res = gsi_queue_xfer(prod_sys->ep->gsi_chan_hdl, 1, + &xfer_elem_prod, true); + if (res) { + IPADMA_ERR( + "Failed: gsi_queue_xfer on dummy src descr res: %d\n", + res); + ipa_assert(); + goto fail_send; + } + + } + spin_unlock_irqrestore(&ipa3_dma_ctx->async_lock, flags); + IPADMA_FUNC_EXIT(); + return res; + +fail_send: + list_del(&xfer_descr->link); + spin_unlock_irqrestore(&ipa3_dma_ctx->async_lock, flags); + kmem_cache_free(ipa3_dma_ctx->ipa_dma_xfer_wrapper_cache, xfer_descr); +fail_mem_alloc: + atomic_dec(&ipa3_dma_ctx->async_memcpy_pending_cnt); + if (ipa3_dma_ctx->destroy_pending && !ipa3_dma_work_pending()) + complete(&ipa3_dma_ctx->done); + return res; +} +EXPORT_SYMBOL(ipa_dma_async_memcpy); + +/** + * ipa3_dma_uc_memcpy() - Perform a memcpy action using IPA uC + * @dest: physical address to store the copied data. + * @src: physical address of the source data to copy. + * @len: number of bytes to copy. + * + * Return codes: 0: success + * -EINVAL: invalid params + * -EPERM: operation not permitted as ipa_dma isn't enable or + * initialized + * -EBADF: IPA uC is not loaded + */ +int ipa3_dma_uc_memcpy(phys_addr_t dest, phys_addr_t src, int len) +{ + int res; + unsigned long flags; + + IPADMA_FUNC_ENTRY(); + if (ipa3_dma_ctx == NULL) { + IPADMA_ERR("IPADMA isn't initialized, can't memcpy\n"); + return -EPERM; + } + if ((max(src, dest) - min(src, dest)) < len) { + IPADMA_ERR("invalid addresses - overlapping buffers\n"); + return -EINVAL; + } + if (len > IPA_DMA_MAX_PKT_SZ || len <= 0) { + IPADMA_ERR("invalid len, %d\n", len); + return -EINVAL; + } + + spin_lock_irqsave(&ipa3_dma_ctx->pending_lock, flags); + if (!ipa3_dma_ctx->enable_ref_cnt) { + IPADMA_ERR("can't memcpy, IPADMA isn't enabled\n"); + spin_unlock_irqrestore(&ipa3_dma_ctx->pending_lock, flags); + return -EPERM; + } + atomic_inc(&ipa3_dma_ctx->uc_memcpy_pending_cnt); + spin_unlock_irqrestore(&ipa3_dma_ctx->pending_lock, flags); + + res = ipa3_uc_memcpy(dest, src, len); + if (res) { + IPADMA_ERR("ipa3_uc_memcpy failed %d\n", res); + goto dec_and_exit; + } + + atomic_inc(&ipa3_dma_ctx->total_uc_memcpy); + res = 0; +dec_and_exit: + atomic_dec(&ipa3_dma_ctx->uc_memcpy_pending_cnt); + if (ipa3_dma_ctx->destroy_pending && !ipa3_dma_work_pending()) + complete(&ipa3_dma_ctx->done); + IPADMA_FUNC_EXIT(); + return res; +} + +/** + * ipa_dma_destroy() -teardown IPADMA pipes and release ipadma. + * + * this is a blocking function, returns just after destroying IPADMA. + */ +void ipa_dma_destroy(void) +{ + int res = 0; + + IPADMA_FUNC_ENTRY(); + + if (!ipa_dma_init_refcnt_ctrl) { + IPADMA_ERR("Setup isn't done\n"); + return; + } + + mutex_lock(&ipa_dma_init_refcnt_ctrl->lock); + if (ipa_dma_init_refcnt_ctrl->ref_cnt > 1) { + IPADMA_DBG("Multiple initialization done. refcnt=%d\n", + ipa_dma_init_refcnt_ctrl->ref_cnt); + ipa_dma_init_refcnt_ctrl->ref_cnt--; + goto completed; + } + + if ((!ipa3_dma_ctx) || (ipa_dma_init_refcnt_ctrl->ref_cnt == 0)) { + IPADMA_ERR("IPADMA isn't initialized ctx=%pK\n", ipa3_dma_ctx); + goto completed; + } + + if (ipa3_dma_work_pending()) { + ipa3_dma_ctx->destroy_pending = true; + IPADMA_DBG("There are pending memcpy, wait for completion\n"); + wait_for_completion(&ipa3_dma_ctx->done); + } + + if (ipa3_dma_ctx->enable_ref_cnt > 0) { + IPADMA_ERR("IPADMA still enabled\n"); + goto completed; + } + + res = ipa_teardown_sys_pipe(ipa3_dma_ctx->ipa_dma_async_cons_hdl); + if (res) + IPADMA_ERR("teardown IPADMA ASYNC CONS failed\n"); + ipa3_dma_ctx->ipa_dma_async_cons_hdl = 0; + res = ipa_teardown_sys_pipe(ipa3_dma_ctx->ipa_dma_sync_cons_hdl); + if (res) + IPADMA_ERR("teardown IPADMA SYNC CONS failed\n"); + ipa3_dma_ctx->ipa_dma_sync_cons_hdl = 0; + res = ipa_teardown_sys_pipe(ipa3_dma_ctx->ipa_dma_async_prod_hdl); + if (res) + IPADMA_ERR("teardown IPADMA ASYNC PROD failed\n"); + ipa3_dma_ctx->ipa_dma_async_prod_hdl = 0; + res = ipa_teardown_sys_pipe(ipa3_dma_ctx->ipa_dma_sync_prod_hdl); + if (res) + IPADMA_ERR("teardown IPADMA SYNC PROD failed\n"); + ipa3_dma_ctx->ipa_dma_sync_prod_hdl = 0; + + ipa3_dma_debugfs_destroy(); + kmem_cache_destroy(ipa3_dma_ctx->ipa_dma_xfer_wrapper_cache); + dma_free_coherent(ipa3_ctx->pdev, IPA_DMA_DUMMY_BUFF_SZ * 4, + ipa3_dma_ctx->ipa_dma_dummy_src_sync.base, + ipa3_dma_ctx->ipa_dma_dummy_src_sync.phys_base); + kfree(ipa3_dma_ctx); + ipa3_dma_ctx = NULL; + + ipa_dma_init_refcnt_ctrl->ref_cnt = 0; + IPADMA_FUNC_EXIT(); + +completed: + mutex_unlock(&ipa_dma_init_refcnt_ctrl->lock); +} +EXPORT_SYMBOL(ipa_dma_destroy); + +/** + * ipa3_dma_async_memcpy_notify_cb() - Callback function which will be called + * by IPA driver after getting notify on Rx operation is completed (data was + * written to dest descriptor on async_cons ep). + * + * @priv -not in use. + * @evt - event name - IPA_RECIVE. + * @data -the ipa_mem_buffer. + */ +void ipa3_dma_async_memcpy_notify_cb(void *priv + , enum ipa_dp_evt_type evt, unsigned long data) +{ + int ep_idx = 0; + struct ipa3_dma_xfer_wrapper *xfer_descr_expected; + struct ipa3_sys_context *sys; + unsigned long flags; + + IPADMA_FUNC_ENTRY(); + + ep_idx = ipa_get_ep_mapping(IPA_CLIENT_MEMCPY_DMA_ASYNC_CONS); + if (ep_idx < 0) { + IPADMA_ERR("IPA Client mapping failed\n"); + return; + } + sys = ipa3_ctx->ep[ep_idx].sys; + + spin_lock_irqsave(&ipa3_dma_ctx->async_lock, flags); + xfer_descr_expected = list_first_entry(&sys->head_desc_list, + struct ipa3_dma_xfer_wrapper, link); + list_del(&xfer_descr_expected->link); + sys->len--; + spin_unlock_irqrestore(&ipa3_dma_ctx->async_lock, flags); + atomic_inc(&ipa3_dma_ctx->total_async_memcpy); + atomic_dec(&ipa3_dma_ctx->async_memcpy_pending_cnt); + xfer_descr_expected->callback(xfer_descr_expected->user1); + + kmem_cache_free(ipa3_dma_ctx->ipa_dma_xfer_wrapper_cache, + xfer_descr_expected); + + if (ipa3_dma_ctx->destroy_pending && !ipa3_dma_work_pending()) + complete(&ipa3_dma_ctx->done); + + IPADMA_FUNC_EXIT(); +} + +#ifdef CONFIG_DEBUG_FS +static struct dentry *dent; +static struct dentry *dfile_info; + +static ssize_t ipa3_dma_debugfs_read(struct file *file, char __user *ubuf, + size_t count, loff_t *ppos) +{ + int nbytes = 0; + + if (!ipa_dma_init_refcnt_ctrl) { + nbytes += scnprintf(&dbg_buff[nbytes], + IPADMA_MAX_MSG_LEN - nbytes, + "Setup was not done\n"); + goto completed; + + } + + if (!ipa3_dma_ctx) { + nbytes += scnprintf(&dbg_buff[nbytes], + IPADMA_MAX_MSG_LEN - nbytes, + "Status:\n Not initialized (ref_cnt=%d)\n", + ipa_dma_init_refcnt_ctrl->ref_cnt); + } else { + nbytes += scnprintf(&dbg_buff[nbytes], + IPADMA_MAX_MSG_LEN - nbytes, + "Status:\n Initialized (ref_cnt=%d)\n", + ipa_dma_init_refcnt_ctrl->ref_cnt); + nbytes += scnprintf(&dbg_buff[nbytes], + IPADMA_MAX_MSG_LEN - nbytes, + " %s (ref_cnt=%d)\n", + (ipa3_dma_ctx->enable_ref_cnt > 0) ? + "Enabled" : "Disabled", + ipa3_dma_ctx->enable_ref_cnt); + nbytes += scnprintf(&dbg_buff[nbytes], + IPADMA_MAX_MSG_LEN - nbytes, + "Statistics:\n total sync memcpy: %d\n ", + atomic_read(&ipa3_dma_ctx->total_sync_memcpy)); + nbytes += scnprintf(&dbg_buff[nbytes], + IPADMA_MAX_MSG_LEN - nbytes, + "total async memcpy: %d\n ", + atomic_read(&ipa3_dma_ctx->total_async_memcpy)); + nbytes += scnprintf(&dbg_buff[nbytes], + IPADMA_MAX_MSG_LEN - nbytes, + "total uc memcpy: %d\n ", + atomic_read(&ipa3_dma_ctx->total_uc_memcpy)); + nbytes += scnprintf(&dbg_buff[nbytes], + IPADMA_MAX_MSG_LEN - nbytes, + "pending sync memcpy jobs: %d\n ", + atomic_read(&ipa3_dma_ctx->sync_memcpy_pending_cnt)); + nbytes += scnprintf(&dbg_buff[nbytes], + IPADMA_MAX_MSG_LEN - nbytes, + "pending async memcpy jobs: %d\n ", + atomic_read(&ipa3_dma_ctx->async_memcpy_pending_cnt)); + nbytes += scnprintf(&dbg_buff[nbytes], + IPADMA_MAX_MSG_LEN - nbytes, + "pending uc memcpy jobs: %d\n", + atomic_read(&ipa3_dma_ctx->uc_memcpy_pending_cnt)); + } + +completed: + return simple_read_from_buffer(ubuf, count, ppos, dbg_buff, nbytes); +} + +static ssize_t ipa3_dma_debugfs_reset_statistics(struct file *file, + const char __user *ubuf, + size_t count, + loff_t *ppos) +{ + s8 in_num = 0; + int ret; + + ret = kstrtos8_from_user(ubuf, count, 0, &in_num); + if (ret) + return ret; + + switch (in_num) { + case 0: + if (ipa3_dma_work_pending()) + IPADMA_ERR("Note, there are pending memcpy\n"); + + atomic_set(&ipa3_dma_ctx->total_async_memcpy, 0); + atomic_set(&ipa3_dma_ctx->total_sync_memcpy, 0); + break; + default: + IPADMA_ERR("invalid argument: To reset statistics echo 0\n"); + break; + } + return count; +} + +const struct file_operations ipa3_ipadma_stats_ops = { + .read = ipa3_dma_debugfs_read, + .write = ipa3_dma_debugfs_reset_statistics, +}; + +static void ipa3_dma_debugfs_init(void) +{ + const mode_t read_write_mode = 0666; + + dent = debugfs_create_dir("ipa_dma", 0); + if (IS_ERR(dent)) { + IPADMA_ERR("fail to create folder ipa_dma\n"); + return; + } + + dfile_info = + debugfs_create_file("info", read_write_mode, dent, + 0, &ipa3_ipadma_stats_ops); + if (!dfile_info || IS_ERR(dfile_info)) { + IPADMA_ERR("fail to create file stats\n"); + goto fail; + } + return; +fail: + debugfs_remove_recursive(dent); +} + +static void ipa3_dma_debugfs_destroy(void) +{ + debugfs_remove_recursive(dent); +} + +#endif /* !CONFIG_DEBUG_FS */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_dp.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_dp.c new file mode 100644 index 0000000000..347a558787 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_dp.c @@ -0,0 +1,7532 @@ + +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. + * + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "gsi.h" +#include "ipa_i.h" +#include "ipa_trace.h" +#include "ipahal.h" +#include "ipahal_fltrt.h" +#include "ipa_stats.h" +#ifdef CONFIG_IPA_RMNET_MEM +#include +#endif + +#define IPA_GSI_EVENT_RP_SIZE 8 +#define IPA_WAN_NAPI_MAX_FRAMES (NAPI_WEIGHT / IPA_WAN_AGGR_PKT_CNT) +#define IPA_WAN_PAGE_ORDER 3 +#define IPA_LAN_AGGR_PKT_CNT 1 +#define IPA_LAN_NAPI_MAX_FRAMES (NAPI_WEIGHT / IPA_LAN_AGGR_PKT_CNT) +#define IPA_LAST_DESC_CNT 0xFFFF +#define POLLING_INACTIVITY_RX 40 +#define POLLING_MIN_SLEEP_RX 1010 +#define POLLING_MAX_SLEEP_RX 1050 +#define POLLING_INACTIVITY_TX 40 +#define POLLING_MIN_SLEEP_TX 400 +#define POLLING_MAX_SLEEP_TX 500 +#define SUSPEND_MIN_SLEEP_RX 1000 +#define SUSPEND_MAX_SLEEP_RX 1005 +/* 8K less 1 nominal MTU (1500 bytes) rounded to units of KB */ +#define IPA_MTU 1500 +#define IPA_GENERIC_AGGR_BYTE_LIMIT 6 +#define IPA_GENERIC_AGGR_TIME_LIMIT 500 /* 0.5msec */ +#define IPA_GENERIC_AGGR_PKT_LIMIT 0 + +#define IPA_GSB_AGGR_BYTE_LIMIT 14 +#define IPA_GSB_RX_BUFF_BASE_SZ 16384 +#define IPA_QMAP_RX_BUFF_BASE_SZ 576 +#define IPA_GENERIC_RX_BUFF_BASE_SZ 8192 +#define IPA_REAL_GENERIC_RX_BUFF_SZ(X) (SKB_DATA_ALIGN(\ + (X) + NET_SKB_PAD) +\ + SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) +#define IPA_GENERIC_RX_BUFF_SZ(X) ((X) -\ + (IPA_REAL_GENERIC_RX_BUFF_SZ(X) - (X))) +#define IPA_GENERIC_RX_BUFF_LIMIT (\ + IPA_REAL_GENERIC_RX_BUFF_SZ(\ + IPA_GENERIC_RX_BUFF_BASE_SZ) -\ + IPA_GENERIC_RX_BUFF_BASE_SZ) + +/* less 1 nominal MTU (1500 bytes) rounded to units of KB */ +#define IPA_ADJUST_AGGR_BYTE_LIMIT(X) (((X) - IPA_MTU)/1000) + +#define IPA_RX_BUFF_CLIENT_HEADROOM 256 + +#define IPA_WLAN_RX_POOL_SZ 100 +#define IPA_WLAN_RX_POOL_SZ_LOW_WM 5 +#define IPA_WLAN_RX_BUFF_SZ 2048 +#define IPA_WLAN_COMM_RX_POOL_LOW 100 +#define IPA_WLAN_COMM_RX_POOL_HIGH 900 + +#define IPA_ODU_RX_BUFF_SZ 2048 +#define IPA_ODU_RX_POOL_SZ 64 + +#define IPA_ODL_RX_BUFF_SZ (16 * 1024) + +#define IPA_GSI_MAX_CH_LOW_WEIGHT 15 +#define IPA_GSI_EVT_RING_INT_MODT (16) /* 0.5ms under 32KHz clock */ +#define IPA_GSI_EVT_RING_INT_MODC (20) + +#define IPA_GSI_CH_20_WA_NUM_CH_TO_ALLOC 10 +/* The below virtual channel cannot be used by any entity */ +#define IPA_GSI_CH_20_WA_VIRT_CHAN 29 + +#define IPA_DEFAULT_SYS_YELLOW_WM 32 +/* High threshold is set for 50% of the buffer */ +#define IPA_BUFF_THRESHOLD_HIGH 112 +#define IPA_REPL_XFER_THRESH 20 +#define IPA_REPL_XFER_MAX 36 + +#define IPA_TX_SEND_COMPL_NOP_DELAY_NS (2 * 1000 * 1000) + +#define IPA_APPS_BW_FOR_PM 700 + +#define IPA_SEND_MAX_DESC (20) + +#define IPA_EOT_THRESH 32 + +#define IPA_QMAP_ID_BYTE 0 + +#define IPA_MEM_ALLOC_RETRY 5 + +static int ipa3_tx_switch_to_intr_mode(struct ipa3_sys_context *sys); +static int ipa3_rx_switch_to_intr_mode(struct ipa3_sys_context *sys); +static struct sk_buff *ipa3_get_skb_ipa_rx(unsigned int len, gfp_t flags); +static void ipa3_replenish_wlan_rx_cache(struct ipa3_sys_context *sys); +static void ipa3_replenish_rx_cache(struct ipa3_sys_context *sys); +static void ipa3_first_replenish_rx_cache(struct ipa3_sys_context *sys); +static void ipa3_replenish_rx_work_func(struct work_struct *work); +static void ipa3_fast_replenish_rx_cache(struct ipa3_sys_context *sys); +static void ipa3_replenish_rx_page_cache(struct ipa3_sys_context *sys); +static void ipa3_wq_page_repl(struct work_struct *work); +static void ipa3_replenish_rx_page_recycle(struct ipa3_sys_context *sys); +static struct ipa3_rx_pkt_wrapper *ipa3_alloc_rx_pkt_page(gfp_t flag, + bool is_tmp_alloc, struct ipa3_sys_context *sys); +static void ipa3_wq_handle_rx(struct work_struct *work); +static void ipa3_wq_rx_common(struct ipa3_sys_context *sys, + struct gsi_chan_xfer_notify *notify); +static void ipa3_rx_napi_chain(struct ipa3_sys_context *sys, + struct gsi_chan_xfer_notify *notify, uint32_t num); +static void ipa3_wlan_wq_rx_common(struct ipa3_sys_context *sys, + struct gsi_chan_xfer_notify *notify); +static int ipa3_assign_policy(struct ipa_sys_connect_params *in, + struct ipa3_sys_context *sys); +static void ipa3_cleanup_rx(struct ipa3_sys_context *sys); +static void ipa3_wq_rx_avail(struct work_struct *work); +static void ipa3_alloc_wlan_rx_common_cache(u32 size); +static void ipa3_cleanup_wlan_rx_common_cache(void); +static void ipa3_wq_repl_rx(struct work_struct *work); +static void ipa3_dma_memcpy_notify(struct ipa3_sys_context *sys); +static int ipa_gsi_setup_coal_def_channel(struct ipa_sys_connect_params *in, + struct ipa3_ep_context *ep, struct ipa3_ep_context *coal_ep); +static int ipa_gsi_setup_channel(struct ipa_sys_connect_params *in, + struct ipa3_ep_context *ep); +static int ipa_gsi_setup_event_ring(struct ipa3_ep_context *ep, + u32 ring_size, gfp_t mem_flag); +static int ipa_gsi_setup_transfer_ring(struct ipa3_ep_context *ep, + u32 ring_size, struct ipa3_sys_context *user_data, gfp_t mem_flag); +static int ipa3_teardown_pipe(u32 clnt_hdl); +static int ipa_populate_tag_field(struct ipa3_desc *desc, + struct ipa3_tx_pkt_wrapper *tx_pkt, + struct ipahal_imm_cmd_pyld **tag_pyld_ret); +static int ipa_poll_gsi_pkt(struct ipa3_sys_context *sys, + struct gsi_chan_xfer_notify *notify); +static int ipa_poll_gsi_n_pkt(struct ipa3_sys_context *sys, + struct gsi_chan_xfer_notify *notify, int expected_num, + int *actual_num); +static unsigned long tag_to_pointer_wa(uint64_t tag); +static uint64_t pointer_to_tag_wa(struct ipa3_tx_pkt_wrapper *tx_pkt); +static void ipa3_tasklet_rx_notify(unsigned long data); +static void ipa3_tasklet_find_freepage(unsigned long data); +static u32 ipa_adjust_ra_buff_base_sz(u32 aggr_byte_limit); +static int ipa3_rmnet_ll_rx_poll(struct napi_struct *napi_rx, int budget); + +struct gsi_chan_xfer_notify g_lan_rx_notify[IPA_LAN_NAPI_MAX_FRAMES]; + +static void ipa3_collect_default_coal_recycle_stats_wq(struct work_struct *work); +static DECLARE_DELAYED_WORK(ipa3_collect_default_coal_recycle_stats_wq_work, + ipa3_collect_default_coal_recycle_stats_wq); + +static void ipa3_collect_low_lat_data_recycle_stats_wq(struct work_struct *work); +static DECLARE_DELAYED_WORK(ipa3_collect_low_lat_data_recycle_stats_wq_work, + ipa3_collect_low_lat_data_recycle_stats_wq); + +static void ipa3_collect_default_coal_recycle_stats_wq(struct work_struct *work) +{ + struct ipa3_sys_context *sys; + int stat_interval_index; + int ep_idx = -1; + + /* For targets which don't require coalescing pipe */ + ep_idx = ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS); + if (ep_idx == -1) + ep_idx = ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_CONS); + + if (ep_idx == -1) + sys = NULL; + else + sys = ipa3_ctx->ep[ep_idx].sys; + + mutex_lock(&ipa3_ctx->recycle_stats_collection_lock); + stat_interval_index = ipa3_ctx->recycle_stats.default_coal_stats_index; + ipa3_ctx->recycle_stats.interval_time_in_ms = IPA_LNX_PIPE_PAGE_RECYCLING_INTERVAL_TIME; + + /* Coalescing pipe page recycling stats */ + ipa3_ctx->recycle_stats.rx_channel[RX_WAN_COALESCING][stat_interval_index].total_cumulative + = ipa3_ctx->stats.page_recycle_stats[0].total_replenished; + ipa3_ctx->recycle_stats.rx_channel[RX_WAN_COALESCING][stat_interval_index].recycle_cumulative + = ipa3_ctx->stats.page_recycle_stats[0].page_recycled; + ipa3_ctx->recycle_stats.rx_channel[RX_WAN_COALESCING][stat_interval_index].temp_cumulative + = ipa3_ctx->stats.page_recycle_stats[0].tmp_alloc; + + ipa3_ctx->recycle_stats.rx_channel[RX_WAN_COALESCING][stat_interval_index].total_diff + = ipa3_ctx->recycle_stats.rx_channel[RX_WAN_COALESCING][stat_interval_index].total_cumulative + - ipa3_ctx->prev_coal_recycle_stats.total_replenished; + ipa3_ctx->recycle_stats.rx_channel[RX_WAN_COALESCING][stat_interval_index].recycle_diff + = ipa3_ctx->recycle_stats.rx_channel[RX_WAN_COALESCING][stat_interval_index].recycle_cumulative + - ipa3_ctx->prev_coal_recycle_stats.page_recycled; + ipa3_ctx->recycle_stats.rx_channel[RX_WAN_COALESCING][stat_interval_index].temp_diff + = ipa3_ctx->recycle_stats.rx_channel[RX_WAN_COALESCING][stat_interval_index].temp_cumulative + - ipa3_ctx->prev_coal_recycle_stats.tmp_alloc; + + ipa3_ctx->prev_coal_recycle_stats.total_replenished + = ipa3_ctx->recycle_stats.rx_channel[RX_WAN_COALESCING][stat_interval_index].total_cumulative; + ipa3_ctx->prev_coal_recycle_stats.page_recycled + = ipa3_ctx->recycle_stats.rx_channel[RX_WAN_COALESCING][stat_interval_index].recycle_cumulative; + ipa3_ctx->prev_coal_recycle_stats.tmp_alloc + = ipa3_ctx->recycle_stats.rx_channel[RX_WAN_COALESCING][stat_interval_index].temp_cumulative; + + /* Default pipe page recycling stats */ + ipa3_ctx->recycle_stats.rx_channel[RX_WAN_DEFAULT][stat_interval_index].total_cumulative + = ipa3_ctx->stats.page_recycle_stats[1].total_replenished; + ipa3_ctx->recycle_stats.rx_channel[RX_WAN_DEFAULT][stat_interval_index].recycle_cumulative + = ipa3_ctx->stats.page_recycle_stats[1].page_recycled; + ipa3_ctx->recycle_stats.rx_channel[RX_WAN_DEFAULT][stat_interval_index].temp_cumulative + = ipa3_ctx->stats.page_recycle_stats[1].tmp_alloc; + + ipa3_ctx->recycle_stats.rx_channel[RX_WAN_DEFAULT][stat_interval_index].total_diff + = ipa3_ctx->recycle_stats.rx_channel[RX_WAN_DEFAULT][stat_interval_index].total_cumulative + - ipa3_ctx->prev_default_recycle_stats.total_replenished; + ipa3_ctx->recycle_stats.rx_channel[RX_WAN_DEFAULT][stat_interval_index].recycle_diff + = ipa3_ctx->recycle_stats.rx_channel[RX_WAN_DEFAULT][stat_interval_index].recycle_cumulative + - ipa3_ctx->prev_default_recycle_stats.page_recycled; + ipa3_ctx->recycle_stats.rx_channel[RX_WAN_DEFAULT][stat_interval_index].temp_diff + = ipa3_ctx->recycle_stats.rx_channel[RX_WAN_DEFAULT][stat_interval_index].temp_cumulative + - ipa3_ctx->prev_default_recycle_stats.tmp_alloc; + + ipa3_ctx->prev_default_recycle_stats.total_replenished + = ipa3_ctx->recycle_stats.rx_channel[RX_WAN_DEFAULT][stat_interval_index].total_cumulative; + ipa3_ctx->prev_default_recycle_stats.page_recycled + = ipa3_ctx->recycle_stats.rx_channel[RX_WAN_DEFAULT][stat_interval_index].recycle_cumulative; + ipa3_ctx->prev_default_recycle_stats.tmp_alloc + = ipa3_ctx->recycle_stats.rx_channel[RX_WAN_DEFAULT][stat_interval_index].temp_cumulative; + + ipa3_ctx->recycle_stats.rx_channel[RX_WAN_COALESCING][stat_interval_index].valid = 1; + ipa3_ctx->recycle_stats.rx_channel[RX_WAN_DEFAULT][stat_interval_index].valid = 1; + + /* Single Indexing for coalescing and default pipe */ + ipa3_ctx->recycle_stats.default_coal_stats_index = + (ipa3_ctx->recycle_stats.default_coal_stats_index + 1) % IPA_LNX_PIPE_PAGE_RECYCLING_INTERVAL_COUNT; + + if (sys && atomic_read(&sys->curr_polling_state)) + queue_delayed_work(ipa3_ctx->collect_recycle_stats_wq, + &ipa3_collect_default_coal_recycle_stats_wq_work, msecs_to_jiffies(10)); + + mutex_unlock(&ipa3_ctx->recycle_stats_collection_lock); + + return; + +} + +static void ipa3_collect_low_lat_data_recycle_stats_wq(struct work_struct *work) +{ + struct ipa3_sys_context *sys; + int stat_interval_index; + int ep_idx; + + ep_idx = ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_CONS); + if (ep_idx == -1) + sys = NULL; + else + sys = ipa3_ctx->ep[ep_idx].sys; + + mutex_lock(&ipa3_ctx->recycle_stats_collection_lock); + stat_interval_index = ipa3_ctx->recycle_stats.low_lat_stats_index; + + /* Low latency data pipe page recycling stats */ + ipa3_ctx->recycle_stats.rx_channel[RX_WAN_LOW_LAT_DATA][stat_interval_index].total_cumulative + = ipa3_ctx->stats.page_recycle_stats[2].total_replenished; + ipa3_ctx->recycle_stats.rx_channel[RX_WAN_LOW_LAT_DATA][stat_interval_index].recycle_cumulative + = ipa3_ctx->stats.page_recycle_stats[2].page_recycled; + ipa3_ctx->recycle_stats.rx_channel[RX_WAN_LOW_LAT_DATA][stat_interval_index].temp_cumulative + = ipa3_ctx->stats.page_recycle_stats[2].tmp_alloc; + + ipa3_ctx->recycle_stats.rx_channel[RX_WAN_LOW_LAT_DATA][stat_interval_index].total_diff + = ipa3_ctx->recycle_stats.rx_channel[RX_WAN_LOW_LAT_DATA][stat_interval_index].total_cumulative + - ipa3_ctx->prev_low_lat_data_recycle_stats.total_replenished; + ipa3_ctx->recycle_stats.rx_channel[RX_WAN_LOW_LAT_DATA][stat_interval_index].recycle_diff + = ipa3_ctx->recycle_stats.rx_channel[RX_WAN_LOW_LAT_DATA][stat_interval_index].recycle_cumulative + - ipa3_ctx->prev_low_lat_data_recycle_stats.page_recycled; + ipa3_ctx->recycle_stats.rx_channel[RX_WAN_LOW_LAT_DATA][stat_interval_index].temp_diff + = ipa3_ctx->recycle_stats.rx_channel[RX_WAN_LOW_LAT_DATA][stat_interval_index].temp_cumulative + - ipa3_ctx->prev_low_lat_data_recycle_stats.tmp_alloc; + + ipa3_ctx->prev_low_lat_data_recycle_stats.total_replenished + = ipa3_ctx->recycle_stats.rx_channel[RX_WAN_LOW_LAT_DATA][stat_interval_index].total_cumulative; + ipa3_ctx->prev_low_lat_data_recycle_stats.page_recycled + = ipa3_ctx->recycle_stats.rx_channel[RX_WAN_LOW_LAT_DATA][stat_interval_index].recycle_cumulative; + ipa3_ctx->prev_low_lat_data_recycle_stats.tmp_alloc + = ipa3_ctx->recycle_stats.rx_channel[RX_WAN_LOW_LAT_DATA][stat_interval_index].temp_cumulative; + + ipa3_ctx->recycle_stats.rx_channel[RX_WAN_LOW_LAT_DATA][stat_interval_index].valid = 1; + + /* Indexing for low lat data stats pipe */ + ipa3_ctx->recycle_stats.low_lat_stats_index = + (ipa3_ctx->recycle_stats.low_lat_stats_index + 1) % IPA_LNX_PIPE_PAGE_RECYCLING_INTERVAL_COUNT; + + if (sys && atomic_read(&sys->curr_polling_state)) + queue_delayed_work(ipa3_ctx->collect_recycle_stats_wq, + &ipa3_collect_low_lat_data_recycle_stats_wq_work, msecs_to_jiffies(10)); + + mutex_unlock(&ipa3_ctx->recycle_stats_collection_lock); + + return; +} + +/** + * ipa3_write_done_common() - this function is responsible on freeing + * all tx_pkt_wrappers related to a skb + * @tx_pkt: the first tx_pkt_warpper related to a certain skb + * @sys:points to the ipa3_sys_context the EOT was received on + * returns the number of tx_pkt_wrappers that were freed + */ +static int ipa3_write_done_common(struct ipa3_sys_context *sys, + struct ipa3_tx_pkt_wrapper *tx_pkt) +{ + struct ipa3_tx_pkt_wrapper *next_pkt; + int i, cnt; + void *user1; + int user2; + void (*callback)(void *user1, int user2); + + if (unlikely(tx_pkt == NULL)) { + IPAERR("tx_pkt is NULL\n"); + return 0; + } + + cnt = tx_pkt->cnt; + for (i = 0; i < cnt; i++) { + spin_lock_bh(&sys->spinlock); + if (unlikely(list_empty(&sys->head_desc_list))) { + spin_unlock_bh(&sys->spinlock); + IPAERR_RL("list is empty missing descriptors"); + return i; + } + next_pkt = list_next_entry(tx_pkt, link); + list_del(&tx_pkt->link); + sys->len--; + if (!tx_pkt->no_unmap_dma) { + if (tx_pkt->type != IPA_DATA_DESC_SKB_PAGED) { + dma_unmap_single(ipa3_ctx->pdev, + tx_pkt->mem.phys_base, + tx_pkt->mem.size, + DMA_TO_DEVICE); + } else { + dma_unmap_page(ipa3_ctx->pdev, + tx_pkt->mem.phys_base, + tx_pkt->mem.size, + DMA_TO_DEVICE); + } + } + callback = tx_pkt->callback; + user1 = tx_pkt->user1; + user2 = tx_pkt->user2; + if (sys->avail_tx_wrapper >= + ipa3_ctx->tx_wrapper_cache_max_size || + sys->ep->client == IPA_CLIENT_APPS_CMD_PROD) { + kmem_cache_free(ipa3_ctx->tx_pkt_wrapper_cache, + tx_pkt); + } else { + list_add_tail(&tx_pkt->link, + &sys->avail_tx_wrapper_list); + sys->avail_tx_wrapper++; + } + spin_unlock_bh(&sys->spinlock); + if (callback) + (*callback)(user1, user2); + tx_pkt = next_pkt; + } + return i; +} + +static void ipa3_wq_write_done_status(int src_pipe, + struct ipa3_tx_pkt_wrapper *tx_pkt) +{ + struct ipa3_sys_context *sys; + + WARN_ON(src_pipe >= ipa3_ctx->ipa_num_pipes); + + if (!ipa3_ctx->ep[src_pipe].status.status_en) + return; + + sys = ipa3_ctx->ep[src_pipe].sys; + if (!sys) + return; + + ipa3_write_done_common(sys, tx_pkt); +} + +/** + * ipa_write_done() - this function will be (eventually) called when a Tx + * operation is complete + * @data: user pointer point to the ipa3_sys_context + * + * Will be called in deferred context. + * - invoke the callback supplied by the client who sent this command + * - iterate over all packets and validate that + * the order for sent packet is the same as expected + * - delete all the tx packet descriptors from the system + * pipe context (not needed anymore) + */ +static void ipa3_tasklet_write_done(unsigned long data) +{ + struct ipa3_sys_context *sys; + struct ipa3_tx_pkt_wrapper *this_pkt; + bool xmit_done = false; + + sys = (struct ipa3_sys_context *)data; + spin_lock_bh(&sys->spinlock); + while (atomic_add_unless(&sys->xmit_eot_cnt, -1, 0)) { + while (!list_empty(&sys->head_desc_list)) { + this_pkt = list_first_entry(&sys->head_desc_list, + struct ipa3_tx_pkt_wrapper, link); + xmit_done = this_pkt->xmit_done; + spin_unlock_bh(&sys->spinlock); + ipa3_write_done_common(sys, this_pkt); + spin_lock_bh(&sys->spinlock); + if (xmit_done) + break; + } + } + spin_unlock_bh(&sys->spinlock); +} + +static int ipa3_napi_poll_tx_complete(struct ipa3_sys_context *sys, int budget) +{ + struct ipa3_tx_pkt_wrapper *this_pkt = NULL; + int entry_budget = budget; + int poll_status = 0; + int num_of_desc = 0; + int i = 0; + struct gsi_chan_xfer_notify notify[NAPI_TX_WEIGHT]; + + do { + poll_status = + ipa_poll_gsi_n_pkt(sys, notify, budget, &num_of_desc); + for(i = 0; i < num_of_desc; i++) { + this_pkt = notify[i].xfer_user_data; + /* For shared event ring sys context might change */ + sys = this_pkt->sys; + ipa3_write_done_common(sys, this_pkt); + budget--; + } + IPADBG_LOW("Number of desc polled %d", num_of_desc); + } while(budget > 0 && !poll_status); + return entry_budget - budget; +} + +static int ipa3_aux_napi_poll_tx_complete(struct napi_struct *napi_tx, + int budget) +{ + struct ipa3_sys_context *sys = container_of(napi_tx, + struct ipa3_sys_context, napi_tx); + bool napi_rescheduled = false; + int tx_done = 0; + int ret = 0; + + tx_done += ipa3_napi_poll_tx_complete(sys, budget - tx_done); + + /* Doorbell needed here for continuous polling */ + gsi_ring_evt_doorbell_polling_mode(sys->ep->gsi_chan_hdl); + + if (tx_done < budget) { + napi_complete(napi_tx); + ret = ipa3_tx_switch_to_intr_mode(sys); + + /* if we got an EOT while we marked NAPI as complete */ + if (ret == -GSI_STATUS_PENDING_IRQ && napi_reschedule(napi_tx)) { + /* rescheduale will perform poll again, don't dec vote twice*/ + napi_rescheduled = true; + } + + if(!napi_rescheduled) + IPA_ACTIVE_CLIENTS_DEC_EP_NO_BLOCK(sys->ep->client); + } + IPADBG_LOW("the number of tx completions is: %d", tx_done); + return min(tx_done, budget); +} + +static int ipa3_napi_tx_complete(struct ipa3_sys_context *sys, int budget) +{ + struct ipa3_tx_pkt_wrapper *this_pkt = NULL; + bool xmit_done = false; + int entry_budget = budget; + + spin_lock_bh(&sys->spinlock); + while (budget > 0 && atomic_read(&sys->xmit_eot_cnt) > 0) { + if (unlikely(list_empty(&sys->head_desc_list))) { + IPADBG_LOW("list is empty"); + break; + } + this_pkt = list_first_entry(&sys->head_desc_list, + struct ipa3_tx_pkt_wrapper, link); + xmit_done = this_pkt->xmit_done; + spin_unlock_bh(&sys->spinlock); + budget -= ipa3_write_done_common(sys, this_pkt); + spin_lock_bh(&sys->spinlock); + if (xmit_done) + atomic_add_unless(&sys->xmit_eot_cnt, -1, 0); + } + spin_unlock_bh(&sys->spinlock); + return entry_budget - budget; +} + +static int ipa3_aux_napi_tx_complete(struct napi_struct *napi_tx, int budget) +{ + struct ipa3_sys_context *sys = container_of(napi_tx, + struct ipa3_sys_context, napi_tx); + int tx_done = 0; + +poll_tx: + tx_done += ipa3_napi_tx_complete(sys, budget - tx_done); + if (tx_done < budget) { + napi_complete(napi_tx); + atomic_set(&sys->in_napi_context, 0); + + /*if we got an EOT while we marked NAPI as complete*/ + if (atomic_read(&sys->xmit_eot_cnt) > 0 && + !atomic_cmpxchg(&sys->in_napi_context, 0, 1) + && napi_reschedule(napi_tx)) { + goto poll_tx; + } + } + IPADBG_LOW("the number of tx completions is: %d", tx_done); + return min(tx_done, budget); +} + +static void ipa3_send_nop_desc(struct work_struct *work) +{ + struct ipa3_sys_context *sys = container_of(work, + struct ipa3_sys_context, work); + struct gsi_xfer_elem nop_xfer; + struct ipa3_tx_pkt_wrapper *tx_pkt; + + IPADBG_LOW("gsi send NOP for ch: %lu\n", sys->ep->gsi_chan_hdl); + if (atomic_read(&sys->workqueue_flushed)) + return; + + spin_lock_bh(&sys->spinlock); + if (!list_empty(&sys->avail_tx_wrapper_list)) { + tx_pkt = list_first_entry(&sys->avail_tx_wrapper_list, + struct ipa3_tx_pkt_wrapper, link); + list_del(&tx_pkt->link); + sys->avail_tx_wrapper--; + memset(tx_pkt, 0, sizeof(struct ipa3_tx_pkt_wrapper)); + } else { + spin_unlock_bh(&sys->spinlock); + tx_pkt = kmem_cache_zalloc(ipa3_ctx->tx_pkt_wrapper_cache, + GFP_KERNEL); + spin_lock_bh(&sys->spinlock); + } + if (!tx_pkt) { + spin_unlock_bh(&sys->spinlock); + queue_work(sys->wq, &sys->work); + return; + } + + INIT_LIST_HEAD(&tx_pkt->link); + tx_pkt->cnt = 1; + tx_pkt->no_unmap_dma = true; + tx_pkt->sys = sys; + if (unlikely(!sys->nop_pending)) { + spin_unlock_bh(&sys->spinlock); + kmem_cache_free(ipa3_ctx->tx_pkt_wrapper_cache, tx_pkt); + return; + } + list_add_tail(&tx_pkt->link, &sys->head_desc_list); + + memset(&nop_xfer, 0, sizeof(nop_xfer)); + nop_xfer.type = GSI_XFER_ELEM_NOP; + nop_xfer.flags = GSI_XFER_FLAG_EOT; + nop_xfer.xfer_user_data = tx_pkt; + if (gsi_queue_xfer(sys->ep->gsi_chan_hdl, 1, &nop_xfer, true)) { + list_del(&tx_pkt->link); + kmem_cache_free(ipa3_ctx->tx_pkt_wrapper_cache, tx_pkt); + spin_unlock_bh(&sys->spinlock); + IPAERR("gsi_queue_xfer for ch:%lu failed\n", + sys->ep->gsi_chan_hdl); + queue_work(sys->wq, &sys->work); + return; + } + sys->len++; + sys->nop_pending = false; + spin_unlock_bh(&sys->spinlock); + + /* make sure TAG process is sent before clocks are gated */ + ipa3_ctx->tag_process_before_gating = true; +} + + +/** + * ipa3_send() - Send multiple descriptors in one HW transaction + * @sys: system pipe context + * @num_desc: number of packets + * @desc: packets to send (may be immediate command or data) + * @in_atomic: whether caller is in atomic context + * + * This function is used for GPI connection. + * - ipa3_tx_pkt_wrapper will be used for each ipa + * descriptor (allocated from wrappers cache) + * - The wrapper struct will be configured for each ipa-desc payload and will + * contain information which will be later used by the user callbacks + * - Each packet (command or data) that will be sent will also be saved in + * ipa3_sys_context for later check that all data was sent + * + * Return codes: 0: success, -EFAULT: failure + */ +int ipa3_send(struct ipa3_sys_context *sys, + u32 num_desc, + struct ipa3_desc *desc, + bool in_atomic) +{ + struct ipa3_tx_pkt_wrapper *tx_pkt, *tx_pkt_first = NULL; + struct ipahal_imm_cmd_pyld *tag_pyld_ret = NULL; + struct ipa3_tx_pkt_wrapper *next_pkt; + struct gsi_xfer_elem gsi_xfer[IPA_SEND_MAX_DESC]; + int i = 0; + int j; + int result; + u32 mem_flag = GFP_ATOMIC; + const struct ipa_gsi_ep_config *gsi_ep_cfg; + bool send_nop = false; + unsigned int max_desc; + + if (unlikely(!in_atomic)) + mem_flag = GFP_KERNEL; + + gsi_ep_cfg = ipa_get_gsi_ep_info(sys->ep->client); + if (unlikely(!gsi_ep_cfg)) { + IPAERR("failed to get gsi EP config for client=%d\n", + sys->ep->client); + return -EFAULT; + } + if (unlikely(num_desc > IPA_SEND_MAX_DESC)) { + IPAERR("max descriptors reached need=%d max=%d\n", + num_desc, IPA_SEND_MAX_DESC); + WARN_ON(1); + return -EPERM; + } + + max_desc = gsi_ep_cfg->ipa_if_tlv; + if (gsi_ep_cfg->prefetch_mode == GSI_SMART_PRE_FETCH || + gsi_ep_cfg->prefetch_mode == GSI_FREE_PRE_FETCH) + max_desc -= gsi_ep_cfg->prefetch_threshold; + + if (unlikely(num_desc > max_desc)) { + IPAERR("Too many chained descriptors need=%d max=%d\n", + num_desc, max_desc); + WARN_ON(1); + return -EPERM; + } + + /* initialize only the xfers we use */ + memset(gsi_xfer, 0, sizeof(gsi_xfer[0]) * num_desc); + + spin_lock_bh(&sys->spinlock); + + if (unlikely(atomic_read(&sys->ep->disconnect_in_progress))) { + IPAERR("Pipe disconnect in progress dropping the packet\n"); + spin_unlock_bh(&sys->spinlock); + return -EFAULT; + } + + for (i = 0; i < num_desc; i++) { + if (!list_empty(&sys->avail_tx_wrapper_list)) { + tx_pkt = list_first_entry(&sys->avail_tx_wrapper_list, + struct ipa3_tx_pkt_wrapper, link); + list_del(&tx_pkt->link); + sys->avail_tx_wrapper--; + + memset(tx_pkt, 0, sizeof(struct ipa3_tx_pkt_wrapper)); + } else { + tx_pkt = kmem_cache_zalloc( + ipa3_ctx->tx_pkt_wrapper_cache, + GFP_ATOMIC); + } + if (!tx_pkt) { + IPAERR("failed to alloc tx wrapper\n"); + result = -ENOMEM; + goto failure; + } + INIT_LIST_HEAD(&tx_pkt->link); + + if (i == 0) { + tx_pkt_first = tx_pkt; + tx_pkt->cnt = num_desc; + } + + /* populate tag field */ + if (desc[i].is_tag_status) { + if (ipa_populate_tag_field(&desc[i], tx_pkt, + &tag_pyld_ret)) { + IPAERR("Failed to populate tag field\n"); + result = -EFAULT; + goto failure_dma_map; + } + } + + tx_pkt->type = desc[i].type; + + if (desc[i].type != IPA_DATA_DESC_SKB_PAGED) { + tx_pkt->mem.base = desc[i].pyld; + tx_pkt->mem.size = desc[i].len; + + if (!desc[i].dma_address_valid) { + tx_pkt->mem.phys_base = + dma_map_single(ipa3_ctx->pdev, + tx_pkt->mem.base, + tx_pkt->mem.size, + DMA_TO_DEVICE); + } else { + tx_pkt->mem.phys_base = + desc[i].dma_address; + tx_pkt->no_unmap_dma = true; + } + } else { + tx_pkt->mem.base = desc[i].frag; + tx_pkt->mem.size = desc[i].len; + + if (!desc[i].dma_address_valid) { + tx_pkt->mem.phys_base = + skb_frag_dma_map(ipa3_ctx->pdev, + desc[i].frag, + 0, tx_pkt->mem.size, + DMA_TO_DEVICE); + } else { + tx_pkt->mem.phys_base = + desc[i].dma_address; + tx_pkt->no_unmap_dma = true; + } + } + if (dma_mapping_error(ipa3_ctx->pdev, tx_pkt->mem.phys_base)) { + IPAERR("failed to do dma map.\n"); + result = -EFAULT; + goto failure_dma_map; + } + + tx_pkt->sys = sys; + tx_pkt->callback = desc[i].callback; + tx_pkt->user1 = desc[i].user1; + tx_pkt->user2 = desc[i].user2; + tx_pkt->xmit_done = false; + + list_add_tail(&tx_pkt->link, &sys->head_desc_list); + sys->len++; + gsi_xfer[i].addr = tx_pkt->mem.phys_base; + + /* + * Special treatment for immediate commands, where + * the structure of the descriptor is different + */ + if (desc[i].type == IPA_IMM_CMD_DESC) { + gsi_xfer[i].len = desc[i].opcode; + gsi_xfer[i].type = + GSI_XFER_ELEM_IMME_CMD; + } else { + gsi_xfer[i].len = desc[i].len; + gsi_xfer[i].type = + GSI_XFER_ELEM_DATA; + } + + if (i == (num_desc - 1)) { + if (ipa3_ctx->tx_poll || + !sys->use_comm_evt_ring || + (sys->pkt_sent % IPA_EOT_THRESH == 0)) { + gsi_xfer[i].flags |= + GSI_XFER_FLAG_EOT; + gsi_xfer[i].flags |= + GSI_XFER_FLAG_BEI; + hrtimer_try_to_cancel(&sys->db_timer); + sys->nop_pending = false; + } else { + send_nop = true; + } + gsi_xfer[i].xfer_user_data = + tx_pkt_first; + } else { + gsi_xfer[i].flags |= + GSI_XFER_FLAG_CHAIN; + } + } + + IPADBG_LOW("ch:%lu queue xfer\n", sys->ep->gsi_chan_hdl); + result = gsi_queue_xfer(sys->ep->gsi_chan_hdl, num_desc, + gsi_xfer, true); + if (result != GSI_STATUS_SUCCESS) { + IPAERR_RL("GSI xfer failed.\n"); + result = -EFAULT; + goto failure; + } + + if (send_nop && !sys->nop_pending) + sys->nop_pending = true; + else + send_nop = false; + + sys->pkt_sent++; + spin_unlock_bh(&sys->spinlock); + + /* set the timer for sending the NOP descriptor */ + if (send_nop) { + ktime_t time = ktime_set(0, IPA_TX_SEND_COMPL_NOP_DELAY_NS); + + IPADBG_LOW("scheduling timer for ch %lu\n", + sys->ep->gsi_chan_hdl); + hrtimer_start(&sys->db_timer, time, HRTIMER_MODE_REL); + } + + /* make sure TAG process is sent before clocks are gated */ + ipa3_ctx->tag_process_before_gating = true; + + return 0; + +failure_dma_map: + kmem_cache_free(ipa3_ctx->tx_pkt_wrapper_cache, tx_pkt); + +failure: + ipahal_destroy_imm_cmd(tag_pyld_ret); + tx_pkt = tx_pkt_first; + for (j = 0; j < i; j++) { + next_pkt = list_next_entry(tx_pkt, link); + list_del(&tx_pkt->link); + sys->len--; + + if (!tx_pkt->no_unmap_dma) { + if (desc[j].type != IPA_DATA_DESC_SKB_PAGED) { + dma_unmap_single(ipa3_ctx->pdev, + tx_pkt->mem.phys_base, + tx_pkt->mem.size, DMA_TO_DEVICE); + } else { + dma_unmap_page(ipa3_ctx->pdev, + tx_pkt->mem.phys_base, + tx_pkt->mem.size, + DMA_TO_DEVICE); + } + } + kmem_cache_free(ipa3_ctx->tx_pkt_wrapper_cache, tx_pkt); + tx_pkt = next_pkt; + } + + spin_unlock_bh(&sys->spinlock); + return result; +} + +/** + * ipa3_send_one() - Send a single descriptor + * @sys: system pipe context + * @desc: descriptor to send + * @in_atomic: whether caller is in atomic context + * + * - Allocate tx_packet wrapper + * - transfer data to the IPA + * - after the transfer was done the SPS will + * notify the sending user via ipa_sps_irq_comp_tx() + * + * Return codes: 0: success, -EFAULT: failure + */ +int ipa3_send_one(struct ipa3_sys_context *sys, struct ipa3_desc *desc, + bool in_atomic) +{ + return ipa3_send(sys, 1, desc, in_atomic); +} + +/** + * ipa3_transport_irq_cmd_ack - callback function which will be called by + * the transport driver after an immediate command is complete. + * @user1: pointer to the descriptor of the transfer + * @user2: + * + * Complete the immediate commands completion object, this will release the + * thread which waits on this completion object (ipa3_send_cmd()) + */ +static void ipa3_transport_irq_cmd_ack(void *user1, int user2) +{ + struct ipa3_desc *desc = (struct ipa3_desc *)user1; + + if (WARN(!desc, "desc is NULL")) + return; + + IPADBG_LOW("got ack for cmd=%d\n", desc->opcode); + complete(&desc->xfer_done); +} + +/** + * ipa3_transport_irq_cmd_ack_free - callback function which will be + * called by the transport driver after an immediate command is complete. + * This function will also free the completion object once it is done. + * @tag_comp: pointer to the completion object + * @ignored: parameter not used + * + * Complete the immediate commands completion object, this will release the + * thread which waits on this completion object (ipa3_send_cmd()) + */ +static void ipa3_transport_irq_cmd_ack_free(void *tag_comp, int ignored) +{ + struct ipa3_tag_completion *comp = tag_comp; + + if (!comp) { + IPAERR("comp is NULL\n"); + return; + } + + complete(&comp->comp); + if (atomic_dec_return(&comp->cnt) == 0) + kfree(comp); +} + +/** + * ipa3_send_cmd - send immediate commands + * @num_desc: number of descriptors within the desc struct + * @descr: descriptor structure + * + * Function will block till command gets ACK from IPA HW, caller needs + * to free any resources it allocated after function returns + * The callback in ipa3_desc should not be set by the caller + * for this function. + */ +int ipa3_send_cmd(u16 num_desc, struct ipa3_desc *descr) +{ + struct ipa3_desc *desc; + int i, result = 0; + struct ipa3_sys_context *sys; + int ep_idx; + + for (i = 0; i < num_desc; i++) + IPADBG("sending imm cmd %d\n", descr[i].opcode); + + ep_idx = ipa_get_ep_mapping(IPA_CLIENT_APPS_CMD_PROD); + if (-1 == ep_idx) { + IPAERR("Client %u is not mapped\n", + IPA_CLIENT_APPS_CMD_PROD); + return -EFAULT; + } + + sys = ipa3_ctx->ep[ep_idx].sys; + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + + if (num_desc == 1) { + init_completion(&descr->xfer_done); + + if (descr->callback || descr->user1) + WARN_ON(1); + + descr->callback = ipa3_transport_irq_cmd_ack; + descr->user1 = descr; + if (ipa3_send_one(sys, descr, true)) { + IPAERR("fail to send immediate command\n"); + result = -EFAULT; + goto bail; + } + wait_for_completion(&descr->xfer_done); + } else { + desc = &descr[num_desc - 1]; + init_completion(&desc->xfer_done); + + if (desc->callback || desc->user1) + WARN_ON(1); + + desc->callback = ipa3_transport_irq_cmd_ack; + desc->user1 = desc; + if (ipa3_send(sys, num_desc, descr, true)) { + IPAERR("fail to send multiple immediate command set\n"); + result = -EFAULT; + goto bail; + } + wait_for_completion(&desc->xfer_done); + } + +bail: + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + return result; +} + +/** + * ipa3_send_cmd_timeout - send immediate commands with limited time + * waiting for ACK from IPA HW + * @num_desc: number of descriptors within the desc struct + * @descr: descriptor structure + * @timeout: millisecond to wait till get ACK from IPA HW + * + * Function will block till command gets ACK from IPA HW or timeout. + * Caller needs to free any resources it allocated after function returns + * The callback in ipa3_desc should not be set by the caller + * for this function. + */ +int ipa3_send_cmd_timeout(u16 num_desc, struct ipa3_desc *descr, u32 timeout) +{ + struct ipa3_desc *desc; + int i, result = 0; + struct ipa3_sys_context *sys; + int ep_idx; + int completed; + struct ipa3_tag_completion *comp; + + for (i = 0; i < num_desc; i++) + IPADBG("sending imm cmd %d\n", descr[i].opcode); + + ep_idx = ipa_get_ep_mapping(IPA_CLIENT_APPS_CMD_PROD); + if (-1 == ep_idx) { + IPAERR("Client %u is not mapped\n", + IPA_CLIENT_APPS_CMD_PROD); + return -EFAULT; + } + + comp = kzalloc(sizeof(*comp), GFP_ATOMIC); + if (!comp) + return -ENOMEM; + + init_completion(&comp->comp); + + /* completion needs to be released from both here and in ack callback */ + atomic_set(&comp->cnt, 2); + + sys = ipa3_ctx->ep[ep_idx].sys; + + if (num_desc == 1) { + if (descr->callback || descr->user1) + WARN_ON(1); + + descr->callback = ipa3_transport_irq_cmd_ack_free; + descr->user1 = comp; + if (ipa3_send_one(sys, descr, true)) { + IPAERR("fail to send immediate command\n"); + kfree(comp); + result = -EFAULT; + goto bail; + } + } else { + desc = &descr[num_desc - 1]; + + if (desc->callback || desc->user1) + WARN_ON(1); + + desc->callback = ipa3_transport_irq_cmd_ack_free; + desc->user1 = comp; + if (ipa3_send(sys, num_desc, descr, true)) { + IPAERR("fail to send multiple immediate command set\n"); + kfree(comp); + result = -EFAULT; + goto bail; + } + } + + completed = wait_for_completion_timeout( + &comp->comp, msecs_to_jiffies(timeout)); + if (!completed) { + IPADBG("timeout waiting for imm-cmd ACK\n"); + result = -EBUSY; + } + + if (atomic_dec_return(&comp->cnt) == 0) + kfree(comp); + +bail: + return result; +} + +/** + * ipa3_handle_rx_core() - The core functionality of packet reception. This + * function is read from multiple code paths. + * + * All the packets on the Rx data path are received on the IPA_A5_LAN_WAN_IN + * endpoint. The function runs as long as there are packets in the pipe. + * For each packet: + * - Disconnect the packet from the system pipe linked list + * - Unmap the packets skb, make it non DMAable + * - Free the packet from the cache + * - Prepare a proper skb + * - Call the endpoints notify function, passing the skb in the parameters + * - Replenish the rx cache + */ +static int ipa3_handle_rx_core(struct ipa3_sys_context *sys, bool process_all, + bool in_poll_state) +{ + int ret; + int cnt = 0; + struct gsi_chan_xfer_notify notify = { 0 }; + + while ((in_poll_state ? atomic_read(&sys->curr_polling_state) : + !atomic_read(&sys->curr_polling_state))) { + if (cnt && !process_all) + break; + + ret = ipa_poll_gsi_pkt(sys, ¬ify); + if (ret) + break; + + if (IPA_CLIENT_IS_MEMCPY_DMA_CONS(sys->ep->client)) + ipa3_dma_memcpy_notify(sys); + else if (IPA_CLIENT_IS_WLAN_CONS(sys->ep->client)) + ipa3_wlan_wq_rx_common(sys, ¬ify); + else + ipa3_wq_rx_common(sys, ¬ify); + + ++cnt; + } + return cnt; +} + +/** + * __ipa3_update_curr_poll_state -> update current polling for default wan and + * coalescing pipe. + * In RSC/RSB enabled cases using common event ring, so both the pipe + * polling state should be in sync. + */ +void __ipa3_update_curr_poll_state(enum ipa_client_type client, int state) +{ + int ep_idx = IPA_EP_NOT_ALLOCATED; + + switch (client) { + case IPA_CLIENT_APPS_WAN_COAL_CONS: + ep_idx = ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_CONS); + break; + case IPA_CLIENT_APPS_WAN_CONS: + ep_idx = ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS); + break; + case IPA_CLIENT_APPS_LAN_COAL_CONS: + ep_idx = ipa_get_ep_mapping(IPA_CLIENT_APPS_LAN_CONS); + break; + case IPA_CLIENT_APPS_LAN_CONS: + ep_idx = ipa_get_ep_mapping(IPA_CLIENT_APPS_LAN_COAL_CONS); + break; + default: + break; + } + + if (ep_idx != IPA_EP_NOT_ALLOCATED && ipa3_ctx->ep[ep_idx].sys) + atomic_set(&ipa3_ctx->ep[ep_idx].sys->curr_polling_state, + state); +} + +static int ipa3_tx_switch_to_intr_mode(struct ipa3_sys_context *sys) { + int ret; + + atomic_set(&sys->curr_polling_state, 0); + __ipa3_update_curr_poll_state(sys->ep->client, 0); + ret = gsi_config_channel_mode(sys->ep->gsi_chan_hdl, + GSI_CHAN_MODE_CALLBACK); + if ((ret != GSI_STATUS_SUCCESS) && + !atomic_read(&sys->curr_polling_state)) { + if (ret == -GSI_STATUS_PENDING_IRQ) { + atomic_set(&sys->curr_polling_state, 1); + __ipa3_update_curr_poll_state(sys->ep->client, 1); + } else { + IPAERR("Failed to switch to intr mode %d ch_id %d\n", + sys->curr_polling_state, sys->ep->gsi_chan_hdl); + } + } + return ret; +} + +/** + * ipa3_rx_switch_to_intr_mode() - Operate the Rx data path in interrupt mode + */ +static int ipa3_rx_switch_to_intr_mode(struct ipa3_sys_context *sys) +{ + int ret; + + atomic_set(&sys->curr_polling_state, 0); + __ipa3_update_curr_poll_state(sys->ep->client, 0); + ipa_pm_deferred_deactivate(sys->pm_hdl); + ipa3_dec_release_wakelock(); + ret = gsi_config_channel_mode(sys->ep->gsi_chan_hdl, + GSI_CHAN_MODE_CALLBACK); + if ((ret != GSI_STATUS_SUCCESS) && + !atomic_read(&sys->curr_polling_state)) { + if (ret == -GSI_STATUS_PENDING_IRQ) { + ipa3_inc_acquire_wakelock(); + atomic_set(&sys->curr_polling_state, 1); + __ipa3_update_curr_poll_state(sys->ep->client, 1); + } else { + IPAERR("Failed to switch to intr mode %d ch_id %d\n", + sys->curr_polling_state, sys->ep->gsi_chan_hdl); + } + } + + return ret; +} + +/** + * ipa3_handle_rx() - handle packet reception. This function is executed in the + * context of a work queue. + * @work: work struct needed by the work queue + * + * ipa3_handle_rx_core() is run in polling mode. After all packets has been + * received, the driver switches back to interrupt mode. + */ +static void ipa3_handle_rx(struct ipa3_sys_context *sys) +{ + enum ipa_client_type client_type; + int inactive_cycles; + int cnt; + int ret; + +start_poll: + ipa_pm_activate_sync(sys->pm_hdl); + inactive_cycles = 0; + do { + cnt = ipa3_handle_rx_core(sys, true, true); + if (cnt == 0) + inactive_cycles++; + else + inactive_cycles = 0; + + trace_idle_sleep_enter3(sys->ep->client); + usleep_range(POLLING_MIN_SLEEP_RX, POLLING_MAX_SLEEP_RX); + trace_idle_sleep_exit3(sys->ep->client); + + /* + * if pipe is out of buffers there is no point polling for + * completed descs; release the worker so delayed work can + * run in a timely manner + */ + if (sys->len == 0) + break; + + } while (inactive_cycles <= POLLING_INACTIVITY_RX); + + trace_poll_to_intr3(sys->ep->client); + ret = ipa3_rx_switch_to_intr_mode(sys); + if (ret == -GSI_STATUS_PENDING_IRQ) + goto start_poll; + + if (IPA_CLIENT_IS_WAN_CONS(sys->ep->client)) + client_type = IPA_CLIENT_APPS_WAN_COAL_CONS; + else if (IPA_CLIENT_IS_LAN_CONS(sys->ep->client)) + client_type = IPA_CLIENT_APPS_LAN_COAL_CONS; + else + client_type = sys->ep->client; + + IPA_ACTIVE_CLIENTS_DEC_EP(client_type); +} + +static void ipa3_switch_to_intr_rx_work_func(struct work_struct *work) +{ + struct delayed_work *dwork; + struct ipa3_sys_context *sys; + + dwork = container_of(work, struct delayed_work, work); + sys = container_of(dwork, struct ipa3_sys_context, switch_to_intr_work); + + if (sys->napi_obj || IPA_CLIENT_IS_LOW_LAT_CONS(sys->ep->client)) { + /* interrupt mode is done in ipa3_rx_poll context */ + ipa_assert(); + } else + ipa3_handle_rx(sys); +} + +enum hrtimer_restart ipa3_ring_doorbell_timer_fn(struct hrtimer *param) +{ + struct ipa3_sys_context *sys = container_of(param, + struct ipa3_sys_context, db_timer); + + queue_work(sys->wq, &sys->work); + return HRTIMER_NORESTART; +} + +static void ipa_pm_sys_pipe_cb(void *p, enum ipa_pm_cb_event event) +{ + struct ipa3_sys_context *sys = (struct ipa3_sys_context *)p; + + switch (event) { + case IPA_PM_CLIENT_ACTIVATED: + /* + * this event is ignored as the sync version of activation + * will be used. + */ + break; + case IPA_PM_REQUEST_WAKEUP: + /* + * pipe will be unsuspended as part of + * enabling IPA clocks + */ + IPADBG("calling wakeup for client %d\n", sys->ep->client); + if (sys->ep->client == IPA_CLIENT_APPS_WAN_CONS) { + IPA_ACTIVE_CLIENTS_INC_SPECIAL("PIPE_SUSPEND_WAN"); + usleep_range(SUSPEND_MIN_SLEEP_RX, + SUSPEND_MAX_SLEEP_RX); + IPA_ACTIVE_CLIENTS_DEC_SPECIAL("PIPE_SUSPEND_WAN"); + } else if (sys->ep->client == IPA_CLIENT_APPS_LAN_CONS) { + IPA_ACTIVE_CLIENTS_INC_SPECIAL("PIPE_SUSPEND_LAN"); + usleep_range(SUSPEND_MIN_SLEEP_RX, + SUSPEND_MAX_SLEEP_RX); + IPA_ACTIVE_CLIENTS_DEC_SPECIAL("PIPE_SUSPEND_LAN"); + } else if (sys->ep->client == IPA_CLIENT_ODL_DPL_CONS) { + IPA_ACTIVE_CLIENTS_INC_SPECIAL("PIPE_SUSPEND_ODL"); + usleep_range(SUSPEND_MIN_SLEEP_RX, + SUSPEND_MAX_SLEEP_RX); + IPA_ACTIVE_CLIENTS_DEC_SPECIAL("PIPE_SUSPEND_ODL"); + } else if (sys->ep->client == IPA_CLIENT_APPS_WAN_COAL_CONS) { + IPA_ACTIVE_CLIENTS_INC_SPECIAL("PIPE_SUSPEND_COAL"); + usleep_range(SUSPEND_MIN_SLEEP_RX, + SUSPEND_MAX_SLEEP_RX); + IPA_ACTIVE_CLIENTS_DEC_SPECIAL("PIPE_SUSPEND_COAL"); + } else if (sys->ep->client == IPA_CLIENT_APPS_LAN_COAL_CONS) { + IPA_ACTIVE_CLIENTS_INC_SPECIAL("PIPE_SUSPEND_LAN_COAL"); + usleep_range(SUSPEND_MIN_SLEEP_RX, + SUSPEND_MAX_SLEEP_RX); + IPA_ACTIVE_CLIENTS_DEC_SPECIAL("PIPE_SUSPEND_LAN_COAL"); + } else if (sys->ep->client == IPA_CLIENT_APPS_WAN_LOW_LAT_CONS) { + IPA_ACTIVE_CLIENTS_INC_SPECIAL("PIPE_SUSPEND_LOW_LAT"); + usleep_range(SUSPEND_MIN_SLEEP_RX, + SUSPEND_MAX_SLEEP_RX); + IPA_ACTIVE_CLIENTS_DEC_SPECIAL("PIPE_SUSPEND_LOW_LAT"); + } else if (sys->ep->client == IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_CONS) { + IPA_ACTIVE_CLIENTS_INC_SPECIAL("PIPE_SUSPEND_LOW_LAT_DATA"); + usleep_range(SUSPEND_MIN_SLEEP_RX, + SUSPEND_MAX_SLEEP_RX); + IPA_ACTIVE_CLIENTS_DEC_SPECIAL("PIPE_SUSPEND_LOW_LAT_DATA"); + } else + IPAERR("Unexpected event %d\n for client %d\n", + event, sys->ep->client); + break; + default: + IPAERR("Unexpected event %d\n for client %d\n", + event, sys->ep->client); + WARN_ON(1); + return; + } +} + +int ipa3_setup_tput_pipe(void) +{ + struct ipa3_ep_context *ep; + int ipa_ep_idx, result; + struct ipa_sys_connect_params sys_in; + + memset(&sys_in, 0, sizeof(struct ipa_sys_connect_params)); + sys_in.client = IPA_CLIENT_TPUT_CONS; + sys_in.desc_fifo_sz = IPA_SYS_TPUT_EP_DESC_FIFO_SZ; + + ipa_ep_idx = ipa_get_ep_mapping(sys_in.client); + if (ipa_ep_idx == IPA_EP_NOT_ALLOCATED) { + IPAERR("Invalid client.\n"); + return -EFAULT; + } + ep = &ipa3_ctx->ep[ipa_ep_idx]; + if (ep->valid == 1) { + IPAERR("EP %d already allocated.\n", ipa_ep_idx); + return -EFAULT; + } + IPA_ACTIVE_CLIENTS_INC_EP(sys_in.client); + memset(ep, 0, offsetof(struct ipa3_ep_context, sys)); + ep->valid = 1; + ep->client = sys_in.client; + + result = ipa_gsi_setup_channel(&sys_in, ep); + if (result) { + IPAERR("Failed to setup GSI channel\n"); + goto fail_setup; + } + + result = ipa3_enable_data_path(ipa_ep_idx); + if (result) { + IPAERR("enable data path failed res=%d ep=%d.\n", result, + ipa_ep_idx); + goto fail_setup; + } + IPA_ACTIVE_CLIENTS_DEC_EP(sys_in.client); + return 0; + +fail_setup: + memset(&ipa3_ctx->ep[ipa_ep_idx], 0, sizeof(struct ipa3_ep_context)); + IPA_ACTIVE_CLIENTS_DEC_EP(sys_in.client); + return result; +} + +static void ipa3_schd_freepage_work(struct work_struct *work) +{ + struct delayed_work *dwork; + struct ipa3_sys_context *sys; + + dwork = container_of(work, struct delayed_work, work); + sys = container_of(dwork, struct ipa3_sys_context, freepage_work); + + IPADBG_LOW("WQ scheduled, reschedule sort tasklet\n"); + + tasklet_schedule(&sys->tasklet_find_freepage); +} + +static void ipa3_tasklet_find_freepage(unsigned long data) +{ + struct ipa3_sys_context *sys; + struct ipa3_rx_pkt_wrapper *rx_pkt = NULL; + struct ipa3_rx_pkt_wrapper *tmp = NULL; + struct page *cur_page; + int found_free_page = 0; + struct list_head temp_head; + + sys = (struct ipa3_sys_context *)data; + + if(sys->page_recycle_repl == NULL) + return; + INIT_LIST_HEAD(&temp_head); + spin_lock_bh(&sys->common_sys->spinlock); + list_for_each_entry_safe(rx_pkt, tmp, + &sys->page_recycle_repl->page_repl_head, link) { + cur_page = rx_pkt->page_data.page; + if (page_ref_count(cur_page) == 1) { + /* Found a free page. */ + list_del_init(&rx_pkt->link); + list_add(&rx_pkt->link, &temp_head); + found_free_page++; + } + } + if (!found_free_page) { + /*Not found free page rescheduling tasklet after 2msec*/ + IPADBG_LOW("Scheduling WQ not found free pages\n"); + ++ipa3_ctx->stats.num_of_times_wq_reschd; + queue_delayed_work(sys->freepage_wq, + &sys->freepage_work, + msecs_to_jiffies(ipa3_ctx->page_wq_reschd_time)); + } else { + /*Allow to use pre-allocated buffers*/ + list_splice(&temp_head, &sys->page_recycle_repl->page_repl_head); + ipa3_ctx->stats.page_recycle_cnt_in_tasklet += found_free_page; + IPADBG_LOW("found free pages count = %d\n", found_free_page); + ipa3_ctx->free_page_task_scheduled = false; + atomic_set(&sys->common_sys->page_avilable, 1); + } + spin_unlock_bh(&sys->common_sys->spinlock); + +} + +/** + * ipa_setup_sys_pipe() - Setup an IPA GPI pipe and perform + * IPA EP configuration + * @sys_in: [in] input needed to setup the pipe and configure EP + * @clnt_hdl: [out] client handle + * + * - configure the end-point registers with the supplied + * parameters from the user. + * - Creates a GPI connection with IPA. + * - allocate descriptor FIFO + * + * Returns: 0 on success, negative on failure + */ +int ipa_setup_sys_pipe(struct ipa_sys_connect_params *sys_in, u32 *clnt_hdl) +{ + struct ipa3_ep_context *ep; + int i, ipa_ep_idx; + int wan_handle, lan_handle; + int wan_coal_ep_id, lan_coal_ep_id; + int result = -EINVAL; + struct ipahal_reg_coal_qmap_cfg qmap_cfg; + char buff[IPA_RESOURCE_NAME_MAX]; + struct ipa_ep_cfg ep_cfg_copy; + int (*tx_completion_func)(struct napi_struct *, int); + + if (sys_in == NULL || clnt_hdl == NULL) { + IPAERR( + "NULL args: sys_in(%p) and/or clnt_hdl(%u)\n", + sys_in, clnt_hdl); + goto fail_gen; + } + + if (sys_in->client >= IPA_CLIENT_MAX || sys_in->desc_fifo_sz == 0) { + IPAERR("bad parm client:%d fifo_sz:%d\n", + sys_in->client, sys_in->desc_fifo_sz); + goto fail_gen; + } + + if ( ! IPA_CLIENT_IS_MAPPED(sys_in->client, ipa_ep_idx) ) { + IPAERR("Invalid client.\n"); + goto fail_gen; + } + + ep = &ipa3_ctx->ep[ipa_ep_idx]; + if (ep->valid == 1) { + IPAERR("EP %d already allocated.\n", ipa_ep_idx); + goto fail_gen; + } + + *clnt_hdl = 0; + wan_coal_ep_id = ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS); + lan_coal_ep_id = ipa_get_ep_mapping(IPA_CLIENT_APPS_LAN_COAL_CONS); + + /* save the input config parameters */ + if (IPA_CLIENT_IS_APPS_COAL_CONS(sys_in->client)) + ep_cfg_copy = sys_in->ipa_ep_cfg; + + IPA_ACTIVE_CLIENTS_INC_EP(sys_in->client); + memset(ep, 0, offsetof(struct ipa3_ep_context, sys)); + + if (!ep->sys) { + struct ipa_pm_register_params pm_reg; + + memset(&pm_reg, 0, sizeof(pm_reg)); + ep->sys = kzalloc(sizeof(struct ipa3_sys_context), GFP_KERNEL); + if (!ep->sys) { + IPAERR("failed to sys ctx for client %d\n", + sys_in->client); + result = -ENOMEM; + goto fail_and_disable_clocks; + } + + ep->sys->ep = ep; + snprintf(buff, IPA_RESOURCE_NAME_MAX, "ipawq%d", + sys_in->client); + ep->sys->wq = alloc_workqueue(buff, + WQ_MEM_RECLAIM | WQ_UNBOUND | WQ_SYSFS, 1); + + if (!ep->sys->wq) { + IPAERR("failed to create wq for client %d\n", + sys_in->client); + result = -EFAULT; + goto fail_wq; + } + + snprintf(buff, IPA_RESOURCE_NAME_MAX, "iparepwq%d", + sys_in->client); + ep->sys->repl_wq = alloc_workqueue(buff, + WQ_MEM_RECLAIM | WQ_UNBOUND | WQ_SYSFS | WQ_HIGHPRI, + 1); + if (!ep->sys->repl_wq) { + IPAERR("failed to create rep wq for client %d\n", + sys_in->client); + result = -EFAULT; + goto fail_wq2; + } + + snprintf(buff, IPA_RESOURCE_NAME_MAX, "ipafreepagewq%d", + sys_in->client); + + INIT_LIST_HEAD(&ep->sys->head_desc_list); + INIT_LIST_HEAD(&ep->sys->rcycl_list); + INIT_LIST_HEAD(&ep->sys->avail_tx_wrapper_list); + ep->sys->avail_tx_wrapper = 0; + spin_lock_init(&ep->sys->spinlock); + hrtimer_init(&ep->sys->db_timer, CLOCK_MONOTONIC, + HRTIMER_MODE_REL); + ep->sys->db_timer.function = ipa3_ring_doorbell_timer_fn; + + /* create IPA PM resources for handling polling mode */ + if (sys_in->client == IPA_CLIENT_APPS_WAN_CONS && + wan_coal_ep_id != IPA_EP_NOT_ALLOCATED && + ipa3_ctx->ep[wan_coal_ep_id].valid == 1) { + /* Use coalescing pipe PM handle for default pipe also*/ + ep->sys->pm_hdl = ipa3_ctx->ep[wan_coal_ep_id].sys->pm_hdl; + } else if (sys_in->client == IPA_CLIENT_APPS_LAN_CONS && + lan_coal_ep_id != IPA_EP_NOT_ALLOCATED && + ipa3_ctx->ep[lan_coal_ep_id].valid == 1) { + /* Use coalescing pipe PM handle for default pipe also*/ + ep->sys->pm_hdl = ipa3_ctx->ep[lan_coal_ep_id].sys->pm_hdl; + } else if (IPA_CLIENT_IS_CONS(sys_in->client)) { + ep->sys->freepage_wq = alloc_workqueue(buff, + WQ_MEM_RECLAIM | WQ_UNBOUND | WQ_SYSFS | + WQ_HIGHPRI, 1); + if (!ep->sys->freepage_wq) { + IPAERR("failed to create freepage wq for client %d\n", + sys_in->client); + result = -EFAULT; + goto fail_wq3; + } + + pm_reg.name = ipa_clients_strings[sys_in->client]; + pm_reg.callback = ipa_pm_sys_pipe_cb; + pm_reg.user_data = ep->sys; + pm_reg.group = IPA_PM_GROUP_APPS; + result = ipa_pm_register(&pm_reg, &ep->sys->pm_hdl); + if (result) { + IPAERR("failed to create IPA PM client %d\n", + result); + goto fail_pm; + } + + if (IPA_CLIENT_IS_APPS_CONS(sys_in->client)) { + result = ipa_pm_associate_ipa_cons_to_client( + ep->sys->pm_hdl, sys_in->client); + if (result) { + IPAERR("failed to associate\n"); + goto fail_gen2; + } + } + + result = ipa_pm_set_throughput(ep->sys->pm_hdl, + IPA_APPS_BW_FOR_PM); + if (result) { + IPAERR("failed to set profile IPA PM client\n"); + goto fail_gen2; + } + } + } else { + memset(ep->sys, 0, offsetof(struct ipa3_sys_context, ep)); + } + + if(ipa3_ctx->tx_poll) + tx_completion_func = &ipa3_aux_napi_poll_tx_complete; + else + tx_completion_func = &ipa3_aux_napi_tx_complete; + + atomic_set(&ep->sys->xmit_eot_cnt, 0); + if (IPA_CLIENT_IS_PROD(sys_in->client)) + tasklet_init(&ep->sys->tasklet, ipa3_tasklet_write_done, + (unsigned long) ep->sys); + if (sys_in->client == IPA_CLIENT_APPS_WAN_LOW_LAT_CONS) + tasklet_init(&ep->sys->tasklet, ipa3_tasklet_rx_notify, + (unsigned long) ep->sys); + + if (IPA_CLIENT_IS_PROD(sys_in->client) && + ipa3_ctx->tx_napi_enable) { + if (sys_in->client == IPA_CLIENT_APPS_LAN_PROD) { +#if (LINUX_VERSION_CODE > KERNEL_VERSION(6, 0, 14)) + netif_napi_add_tx_weight(&ipa3_ctx->generic_ndev, + &ep->sys->napi_tx, tx_completion_func, + NAPI_TX_WEIGHT); +#else + netif_tx_napi_add(&ipa3_ctx->generic_ndev, + &ep->sys->napi_tx, tx_completion_func, + NAPI_TX_WEIGHT); + +#endif + ep->sys->napi_tx_enable = ipa3_ctx->tx_napi_enable; + ep->sys->tx_poll = ipa3_ctx->tx_poll; + } else if(sys_in->client == IPA_CLIENT_APPS_WAN_PROD || + sys_in->client == IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_PROD) { +#if (LINUX_VERSION_CODE > KERNEL_VERSION(6, 0, 14)) + netif_napi_add_tx_weight((struct net_device *)sys_in->priv, + &ep->sys->napi_tx, tx_completion_func, + NAPI_TX_WEIGHT); +#else + netif_tx_napi_add((struct net_device *)sys_in->priv, + &ep->sys->napi_tx, tx_completion_func, + NAPI_TX_WEIGHT); +#endif + ep->sys->napi_tx_enable = ipa3_ctx->tx_napi_enable; + ep->sys->tx_poll = ipa3_ctx->tx_poll; + } else { + /*CMD pipe*/ + ep->sys->tx_poll = false; + ep->sys->napi_tx_enable = false; + } + if(ep->sys->napi_tx_enable) { + napi_enable(&ep->sys->napi_tx); + IPADBG("napi_enable on producer client %d completed", + sys_in->client); + } + } + + if (sys_in->client == IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_CONS) { +#if (LINUX_VERSION_CODE > KERNEL_VERSION(6, 0, 14)) + netif_napi_add((struct net_device *)sys_in->priv, + &ep->sys->napi_rx, ipa3_rmnet_ll_rx_poll); +#else + netif_napi_add((struct net_device *)sys_in->priv, + &ep->sys->napi_rx, ipa3_rmnet_ll_rx_poll, NAPI_WEIGHT); +#endif + napi_enable(&ep->sys->napi_rx); + } + + ep->client = sys_in->client; + ep->sys->ext_ioctl_v2 = sys_in->ext_ioctl_v2; + ep->sys->int_modt = sys_in->int_modt; + ep->sys->int_modc = sys_in->int_modc; + ep->sys->buff_size = sys_in->buff_size; + ep->sys->page_order = (sys_in->ext_ioctl_v2) ? + get_order(sys_in->buff_size) : IPA_WAN_PAGE_ORDER; + ep->skip_ep_cfg = sys_in->skip_ep_cfg; + if (ipa3_assign_policy(sys_in, ep->sys)) { + IPAERR("failed to sys ctx for client %d\n", sys_in->client); + result = -ENOMEM; + goto fail_napi; + } + + ep->valid = 1; + ep->client_notify = sys_in->notify; + ep->sys->napi_obj = sys_in->napi_obj; + ep->priv = sys_in->priv; + ep->keep_ipa_awake = sys_in->keep_ipa_awake; + atomic_set(&ep->avail_fifo_desc, + ((sys_in->desc_fifo_sz / IPA_FIFO_ELEMENT_SIZE) - 1)); + + if (ep->status.status_en && IPA_CLIENT_IS_CONS(ep->client) && + ep->sys->status_stat == NULL) { + ep->sys->status_stat = + kzalloc(sizeof(struct ipa3_status_stats), GFP_KERNEL); + if (!ep->sys->status_stat) + goto fail_napi; + } + + if (!ep->skip_ep_cfg) { + if (ipa3_cfg_ep(ipa_ep_idx, &sys_in->ipa_ep_cfg)) { + IPAERR("fail to configure EP.\n"); + goto fail_napi; + } + if (ipa3_cfg_ep_status(ipa_ep_idx, &ep->status)) { + IPAERR("fail to configure status of EP.\n"); + goto fail_napi; + } + IPADBG("ep %d configuration successful\n", ipa_ep_idx); + } else { + IPADBG("skipping ep %d configuration\n", ipa_ep_idx); + } + + result = ipa_gsi_setup_channel(sys_in, ep); + if (result) { + IPAERR("Failed to setup GSI channel\n"); + goto fail_napi; + } + + *clnt_hdl = ipa_ep_idx; + ep->sys->common_sys = ipa3_ctx->ep[ipa_ep_idx].sys; + + if (ep->sys->repl_hdlr == ipa3_fast_replenish_rx_cache) { + ep->sys->repl = kzalloc(sizeof(*ep->sys->repl), GFP_KERNEL); + if (!ep->sys->repl) { + IPAERR("failed to alloc repl for client %d\n", + sys_in->client); + result = -ENOMEM; + goto fail_napi; + } + atomic_set(&ep->sys->repl->pending, 0); + ep->sys->repl->capacity = ep->sys->rx_pool_sz + 1; + + ep->sys->repl->cache = kcalloc(ep->sys->repl->capacity, + sizeof(void *), GFP_KERNEL); + if (!ep->sys->repl->cache) { + IPAERR("ep=%d fail to alloc repl cache\n", ipa_ep_idx); + ep->sys->repl_hdlr = ipa3_replenish_rx_cache; + ep->sys->repl->capacity = 0; + } else { + atomic_set(&ep->sys->repl->head_idx, 0); + atomic_set(&ep->sys->repl->tail_idx, 0); + ipa3_wq_repl_rx(&ep->sys->repl_work); + } + } + + /* Use common page pool for Coal and defalt pipe if applicable. */ + if (ep->sys->repl_hdlr == ipa3_replenish_rx_page_recycle) { + if (!(ipa3_ctx->wan_common_page_pool && + sys_in->client == IPA_CLIENT_APPS_WAN_CONS && + wan_coal_ep_id != IPA_EP_NOT_ALLOCATED && + ipa3_ctx->ep[wan_coal_ep_id].valid == 1)) { + /* Allocate page recycling pool only once. */ + if (!ep->sys->page_recycle_repl) { + ep->sys->page_recycle_repl = kzalloc( + sizeof(*ep->sys->page_recycle_repl), GFP_KERNEL); + if (!ep->sys->page_recycle_repl) { + IPAERR("failed to alloc repl for client %d\n", + sys_in->client); + result = -ENOMEM; + goto fail_napi; + } + atomic_set(&ep->sys->page_recycle_repl->pending, 0); + /* For common page pool double the pool size. */ + if (ipa3_ctx->wan_common_page_pool && + sys_in->client == IPA_CLIENT_APPS_WAN_COAL_CONS) + ep->sys->page_recycle_repl->capacity = + (ep->sys->rx_pool_sz + 1) * + ipa3_ctx->ipa_gen_rx_cmn_page_pool_sz_factor; + else if (sys_in->client == IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_CONS) + ep->sys->page_recycle_repl->capacity = + (ep->sys->rx_pool_sz + 1) * + ipa3_ctx->ipa_gen_rx_ll_pool_sz_factor; + else + ep->sys->page_recycle_repl->capacity = + (ep->sys->rx_pool_sz + 1) * + IPA_GENERIC_RX_PAGE_POOL_SZ_FACTOR; + IPADBG("Page repl capacity for client:%d, value:%d\n", + sys_in->client, ep->sys->page_recycle_repl->capacity); + INIT_LIST_HEAD(&ep->sys->page_recycle_repl->page_repl_head); + INIT_DELAYED_WORK(&ep->sys->freepage_work, ipa3_schd_freepage_work); + tasklet_init(&ep->sys->tasklet_find_freepage, + ipa3_tasklet_find_freepage, (unsigned long) ep->sys); + ipa3_replenish_rx_page_cache(ep->sys); + } else { + ep->sys->napi_sort_page_thrshld_cnt = 0; + /* Sort the pages once. */ + ipa3_tasklet_find_freepage((unsigned long) ep->sys); + } + + ep->sys->repl = kzalloc(sizeof(*ep->sys->repl), GFP_KERNEL); + if (!ep->sys->repl) { + IPAERR("failed to alloc repl for client %d\n", + sys_in->client); + result = -ENOMEM; + goto fail_page_recycle_repl; + } + /* For common page pool triple the pool size. */ + if (ipa3_ctx->wan_common_page_pool && + sys_in->client == IPA_CLIENT_APPS_WAN_COAL_CONS) + ep->sys->repl->capacity = (ep->sys->rx_pool_sz + 1) * + ipa3_ctx->ipa_gen_rx_cmn_temp_pool_sz_factor; + else + ep->sys->repl->capacity = (ep->sys->rx_pool_sz + 1); + IPADBG("Repl capacity for client:%d, value:%d\n", + sys_in->client, ep->sys->repl->capacity); + atomic_set(&ep->sys->repl->pending, 0); + ep->sys->repl->cache = kcalloc(ep->sys->repl->capacity, + sizeof(void *), GFP_KERNEL); + atomic_set(&ep->sys->repl->head_idx, 0); + atomic_set(&ep->sys->repl->tail_idx, 0); + + ipa3_wq_page_repl(&ep->sys->repl_work); + } else { + /* Use pool same as coal pipe when common page pool is used. */ + ep->sys->common_buff_pool = true; + ep->sys->common_sys = ipa3_ctx->ep[wan_coal_ep_id].sys; + ep->sys->repl = ipa3_ctx->ep[wan_coal_ep_id].sys->repl; + ep->sys->page_recycle_repl = + ipa3_ctx->ep[wan_coal_ep_id].sys->page_recycle_repl; + } + } + + if (IPA_CLIENT_IS_CONS(sys_in->client)) { + if ((IPA_CLIENT_IS_WAN_CONS(sys_in->client) || + sys_in->client == + IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_CONS) && + ipa3_ctx->ipa_wan_skb_page) { + ipa3_replenish_rx_page_recycle(ep->sys); + } else + ipa3_first_replenish_rx_cache(ep->sys); + for (i = 0; i < GSI_VEID_MAX; i++) + INIT_LIST_HEAD(&ep->sys->pending_pkts[i]); + } + + if (IPA_CLIENT_IS_WLAN_CONS(sys_in->client)) { + ipa3_alloc_wlan_rx_common_cache(IPA_WLAN_COMM_RX_POOL_LOW); + atomic_inc(&ipa3_ctx->wc_memb.active_clnt_cnt); + } + + ipa3_ctx->skip_ep_cfg_shadow[ipa_ep_idx] = ep->skip_ep_cfg; + if (!ep->skip_ep_cfg && IPA_CLIENT_IS_PROD(sys_in->client)) { + if (ipa3_ctx->modem_cfg_emb_pipe_flt && + (sys_in->client == IPA_CLIENT_APPS_WAN_PROD || + sys_in->client == + IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_PROD)) + IPADBG("modem cfg emb pipe flt\n"); + else + ipa3_install_dflt_flt_rules(ipa_ep_idx); + } + + result = ipa3_enable_data_path(ipa_ep_idx); + if (result) { + IPAERR("enable data path failed res=%d ep=%d.\n", result, + ipa_ep_idx); + goto fail_repl; + } + + result = gsi_start_channel(ep->gsi_chan_hdl); + if (result != GSI_STATUS_SUCCESS) { + IPAERR("gsi_start_channel failed res=%d ep=%d.\n", result, + ipa_ep_idx); + goto fail_gen3; + } + + IPADBG("client %d (ep: %d) connected sys=%pK\n", sys_in->client, + ipa_ep_idx, ep->sys); + + /* + * Configure the registers and setup the default pipe + */ + if (IPA_CLIENT_IS_APPS_COAL_CONS(sys_in->client)) { + + const char* str = ""; + + if (sys_in->client == IPA_CLIENT_APPS_WAN_COAL_CONS) { + + str = "wan"; + + qmap_cfg.mux_id_byte_sel = IPA_QMAP_ID_BYTE; + + ipahal_write_reg_fields(IPA_COAL_QMAP_CFG, &qmap_cfg); + + if (!sys_in->ext_ioctl_v2) { + sys_in->client = IPA_CLIENT_APPS_WAN_CONS; + sys_in->ipa_ep_cfg = ep_cfg_copy; + result = ipa_setup_sys_pipe(sys_in, &wan_handle); + } + + } else { /* (sys_in->client == IPA_CLIENT_APPS_LAN_COAL_CONS) */ + + str = "lan"; + + if (!sys_in->ext_ioctl_v2) { + sys_in->client = IPA_CLIENT_APPS_LAN_CONS; + sys_in->ipa_ep_cfg = ep_cfg_copy; + sys_in->notify = ipa3_lan_rx_cb; + result = ipa_setup_sys_pipe(sys_in, &lan_handle); + } + } + + if (result) { + IPAERR( + "Failed to setup default %s coalescing pipe\n", + str); + goto fail_repl; + } + + ipa3_default_evict_register(); + } + + if (!ep->keep_ipa_awake) + IPA_ACTIVE_CLIENTS_DEC_EP(ep->client); + + return 0; + +fail_gen3: + ipa3_disable_data_path(ipa_ep_idx); +fail_repl: + if (IPA_CLIENT_IS_CONS(ep->client) && !ep->sys->common_buff_pool) + ipa3_cleanup_rx(ep->sys); + + ep->sys->repl_hdlr = ipa3_replenish_rx_cache; + if (ep->sys->repl && !ep->sys->common_buff_pool) { + kfree(ep->sys->repl); + ep->sys->repl = NULL; + } +fail_page_recycle_repl: + if (ep->sys->page_recycle_repl && !ep->sys->common_buff_pool) { + kfree(ep->sys->page_recycle_repl); + ep->sys->page_recycle_repl = NULL; + } +fail_napi: + if (sys_in->client == IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_CONS) { + napi_disable(&ep->sys->napi_rx); + netif_napi_del(&ep->sys->napi_rx); + } + /* Delete NAPI TX object. */ + if (ipa3_ctx->tx_napi_enable && + (IPA_CLIENT_IS_PROD(sys_in->client))) + netif_napi_del(&ep->sys->napi_tx); +fail_gen2: + ipa_pm_deregister(ep->sys->pm_hdl); +fail_pm: + if (ep->sys->freepage_wq) + destroy_workqueue(ep->sys->freepage_wq); +fail_wq3: + destroy_workqueue(ep->sys->repl_wq); +fail_wq2: + destroy_workqueue(ep->sys->wq); +fail_wq: + kfree(ep->sys); + memset(&ipa3_ctx->ep[ipa_ep_idx], 0, sizeof(struct ipa3_ep_context)); +fail_and_disable_clocks: + IPA_ACTIVE_CLIENTS_DEC_EP(sys_in->client); + *clnt_hdl = -1; +fail_gen: + IPA_STATS_INC_CNT(ipa3_ctx->stats.pipe_setup_fail_cnt); + return result; +} +EXPORT_SYMBOL(ipa_setup_sys_pipe); + +static void delete_avail_tx_wrapper_list(struct ipa3_ep_context *ep) +{ + struct ipa3_tx_pkt_wrapper *tx_pkt_iterator = NULL; + struct ipa3_tx_pkt_wrapper *tx_pkt_temp = NULL; + + spin_lock_bh(&ep->sys->spinlock); + list_for_each_entry_safe(tx_pkt_iterator, tx_pkt_temp, + &ep->sys->avail_tx_wrapper_list, link) { + list_del(&tx_pkt_iterator->link); + kmem_cache_free(ipa3_ctx->tx_pkt_wrapper_cache, tx_pkt_iterator); + ep->sys->avail_tx_wrapper--; + } + ep->sys->avail_tx_wrapper = 0; + spin_unlock_bh(&ep->sys->spinlock); +} + +/** + * ipa_teardown_sys_pipe() - Teardown the GPI pipe and cleanup IPA EP + * @clnt_hdl: [in] the handle obtained from ipa_setup_sys_pipe + * + * Returns: 0 on success, negative on failure + */ +int ipa_teardown_sys_pipe(u32 clnt_hdl) +{ + struct ipa3_ep_context *ep; + int empty; + int result; + int i; + + if (clnt_hdl >= ipa3_ctx->ipa_num_pipes || + ipa3_ctx->ep[clnt_hdl].valid == 0) { + IPAERR("bad parm.\n"); + return -EINVAL; + } + + ep = &ipa3_ctx->ep[clnt_hdl]; + + if (!ep->keep_ipa_awake) + IPA_ACTIVE_CLIENTS_INC_EP(ipa3_get_client_mapping(clnt_hdl)); + + ipa3_disable_data_path(clnt_hdl); + + if (IPA_CLIENT_IS_PROD(ep->client)) { + do { + spin_lock_bh(&ep->sys->spinlock); + atomic_set(&ep->disconnect_in_progress, 1); + empty = list_empty(&ep->sys->head_desc_list); + spin_unlock_bh(&ep->sys->spinlock); + if (!empty) + usleep_range(95, 105); + else + break; + } while (1); + + delete_avail_tx_wrapper_list(ep); + /* Delete NAPI TX object. For WAN_PROD, it is deleted + * in rmnet_ipa driver. + */ + if (ipa3_ctx->tx_napi_enable && + (ep->client != IPA_CLIENT_APPS_WAN_PROD)) + netif_napi_del(&ep->sys->napi_tx); + } + + if(ep->client == IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_CONS) { + napi_disable(&ep->sys->napi_rx); + netif_napi_del(&ep->sys->napi_rx); + } + + if ( ep->client == IPA_CLIENT_APPS_WAN_COAL_CONS ) { + stop_coalescing(); + ipa3_force_close_coal(false, true); + } + + /* channel stop might fail on timeout if IPA is busy */ + for (i = 0; i < IPA_GSI_CHANNEL_STOP_MAX_RETRY; i++) { + result = ipa_stop_gsi_channel(clnt_hdl); + if (result == GSI_STATUS_SUCCESS) + break; + + if (result != -GSI_STATUS_AGAIN && + result != -GSI_STATUS_TIMED_OUT) + break; + } + + if ( ep->client == IPA_CLIENT_APPS_WAN_COAL_CONS ) { + start_coalescing(); + } + + if (result != GSI_STATUS_SUCCESS) { + IPAERR("GSI stop chan err: %d.\n", result); + ipa_assert(); + return result; + } + + /* Wait untill end point moving to interrupt mode before teardown */ + do { + usleep_range(95, 105); + } while (atomic_read(&ep->sys->curr_polling_state)); + + if (IPA_CLIENT_IS_CONS(ep->client)) + cancel_delayed_work_sync(&ep->sys->replenish_rx_work); + flush_workqueue(ep->sys->wq); + if (IPA_CLIENT_IS_PROD(ep->client)) + atomic_set(&ep->sys->workqueue_flushed, 1); + + /* + * Tear down the default pipe before we reset the channel + */ + if (ep->client == IPA_CLIENT_APPS_WAN_COAL_CONS) { + + if ( ! IPA_CLIENT_IS_MAPPED(IPA_CLIENT_APPS_WAN_CONS, i) ) { + IPAERR("Failed to get idx for IPA_CLIENT_APPS_WAN_CONS"); + return i; + } + + /* If the default channel is already torn down, + * resetting only coalescing channel. + */ + if (ipa3_ctx->ep[i].valid) { + result = ipa3_teardown_pipe(i); + if (result) { + IPAERR("failed to teardown default coal pipe\n"); + return result; + } + } else { + napi_disable(ep->sys->napi_obj); + netif_napi_del(ep->sys->napi_obj); + } + } + + /* + * Tear down the default pipe before we reset the channel + */ + if (ep->client == IPA_CLIENT_APPS_LAN_COAL_CONS) { + + if ( ! IPA_CLIENT_IS_MAPPED(IPA_CLIENT_APPS_LAN_CONS, i) ) { + IPAERR("Failed to get idx for IPA_CLIENT_APPS_LAN_CONS,"); + return i; + } + + /* If the default channel is already torn down, + * resetting only coalescing channel. + */ + if (ipa3_ctx->ep[i].valid) { + result = ipa3_teardown_pipe(i); + if (result) { + IPAERR("failed to teardown default coal pipe\n"); + return result; + } + } + } + + result = ipa3_reset_gsi_channel(clnt_hdl); + if (result != GSI_STATUS_SUCCESS) { + IPAERR("Failed to reset chan: %d.\n", result); + ipa_assert(); + return result; + } + dma_free_coherent(ipa3_ctx->pdev, + ep->gsi_mem_info.chan_ring_len, + ep->gsi_mem_info.chan_ring_base_vaddr, + ep->gsi_mem_info.chan_ring_base_addr); + result = gsi_dealloc_channel(ep->gsi_chan_hdl); + if (result != GSI_STATUS_SUCCESS) { + IPAERR("Failed to dealloc chan: %d.\n", result); + ipa_assert(); + return result; + } + + /* free event ring only when it is present */ + if (ep->sys->use_comm_evt_ring) { + ipa3_ctx->gsi_evt_comm_ring_rem += + ep->gsi_mem_info.chan_ring_len; + } else if (ep->gsi_evt_ring_hdl != ~0) { + result = gsi_reset_evt_ring(ep->gsi_evt_ring_hdl); + if (WARN(result != GSI_STATUS_SUCCESS, "reset evt %d", result)) + return result; + + dma_free_coherent(ipa3_ctx->pdev, + ep->gsi_mem_info.evt_ring_len, + ep->gsi_mem_info.evt_ring_base_vaddr, + ep->gsi_mem_info.evt_ring_base_addr); + + if (ep->gsi_mem_info.evt_ring_rp_vaddr) { + dma_free_coherent(ipa3_ctx->pdev, + IPA_GSI_EVENT_RP_SIZE, + ep->gsi_mem_info.evt_ring_rp_vaddr, + ep->gsi_mem_info.evt_ring_rp_addr); + ep->gsi_mem_info.evt_ring_rp_addr = 0; + ep->gsi_mem_info.evt_ring_rp_vaddr = 0; + } + + result = gsi_dealloc_evt_ring(ep->gsi_evt_ring_hdl); + if (WARN(result != GSI_STATUS_SUCCESS, "deall evt %d", result)) + return result; + } + if (ep->sys->repl_wq) + flush_workqueue(ep->sys->repl_wq); + + if (ep->sys->repl_hdlr == ipa3_replenish_rx_page_recycle) { + cancel_delayed_work_sync(&ep->sys->common_sys->freepage_work); + + if (ep->sys->freepage_wq) + flush_workqueue(ep->sys->freepage_wq); + + tasklet_kill(&ep->sys->common_sys->tasklet_find_freepage); + } + + if (IPA_CLIENT_IS_CONS(ep->client) && !ep->sys->common_buff_pool) + ipa3_cleanup_rx(ep->sys); + + if (!ep->skip_ep_cfg && IPA_CLIENT_IS_PROD(ep->client)) { + if (ipa3_ctx->modem_cfg_emb_pipe_flt && + (ep->client == IPA_CLIENT_APPS_WAN_PROD || + ep->client == IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_PROD)) + IPADBG("modem cfg emb pipe flt\n"); + else + ipa3_delete_dflt_flt_rules(clnt_hdl); + } + + if (IPA_CLIENT_IS_WLAN_CONS(ep->client)) + atomic_dec(&ipa3_ctx->wc_memb.active_clnt_cnt); + + memset(&ep->wstats, 0, sizeof(struct ipa3_wlan_stats)); + + if (!atomic_read(&ipa3_ctx->wc_memb.active_clnt_cnt)) + ipa3_cleanup_wlan_rx_common_cache(); + + ep->valid = 0; + + IPA_ACTIVE_CLIENTS_DEC_EP(ipa3_get_client_mapping(clnt_hdl)); + + IPADBG("client (ep: %d) disconnected\n", clnt_hdl); + + return 0; +} +EXPORT_SYMBOL(ipa_teardown_sys_pipe); + +/** + * ipa3_teardown_pipe() + * + * Teardown and cleanup of the physical connection (i.e. data + * structures, buffers, GSI channel, work queues, etc) associated + * with the passed client handle and the endpoint context that the + * handle represents. + * + * @clnt_hdl: [in] A handle obtained from ipa_setup_sys_pipe + * + * Returns: 0 on success, negative on failure + */ +static int ipa3_teardown_pipe(u32 clnt_hdl) +{ + struct ipa3_ep_context *ep; + int result; + int i; + + ep = &ipa3_ctx->ep[clnt_hdl]; + + ipa3_disable_data_path(clnt_hdl); + + /* channel stop might fail on timeout if IPA is busy */ + for (i = 0; i < IPA_GSI_CHANNEL_STOP_MAX_RETRY; i++) { + result = ipa_stop_gsi_channel(clnt_hdl); + if (result == GSI_STATUS_SUCCESS) + break; + + if (result != -GSI_STATUS_AGAIN && + result != -GSI_STATUS_TIMED_OUT) + break; + } + + if (result != GSI_STATUS_SUCCESS) { + IPAERR("GSI stop chan err: %d.\n", result); + ipa_assert(); + return result; + } + + if (IPA_CLIENT_IS_WAN_CONS(ep->client)) { + /* Wait for any pending irqs */ + usleep_range(POLLING_MIN_SLEEP_RX, POLLING_MAX_SLEEP_RX); + /* Wait until end point moving to interrupt mode before teardown */ + do { + usleep_range(95, 105); + } while (atomic_read(&ep->sys->curr_polling_state)); + + napi_disable(ep->sys->napi_obj); + netif_napi_del(ep->sys->napi_obj); + } + + result = ipa3_reset_gsi_channel(clnt_hdl); + if (result != GSI_STATUS_SUCCESS) { + IPAERR("Failed to reset chan: %d.\n", result); + ipa_assert(); + return result; + } + dma_free_coherent(ipa3_ctx->pdev, + ep->gsi_mem_info.chan_ring_len, + ep->gsi_mem_info.chan_ring_base_vaddr, + ep->gsi_mem_info.chan_ring_base_addr); + result = gsi_dealloc_channel(ep->gsi_chan_hdl); + if (result != GSI_STATUS_SUCCESS) { + IPAERR("Failed to dealloc chan: %d.\n", result); + ipa_assert(); + return result; + } + + if (IPA_CLIENT_IS_CONS(ep->client)) + cancel_delayed_work_sync(&ep->sys->replenish_rx_work); + + flush_workqueue(ep->sys->wq); + + if (ep->sys->repl_wq) + flush_workqueue(ep->sys->repl_wq); + if (IPA_CLIENT_IS_CONS(ep->client) && !ep->sys->common_buff_pool) + ipa3_cleanup_rx(ep->sys); + + ep->valid = 0; + + IPADBG("client (ep: %d) disconnected\n", clnt_hdl); + + return 0; +} + +/** + * ipa3_tx_comp_usr_notify_release() - Callback function which will call the + * user supplied callback function to release the skb, or release it on + * its own if no callback function was supplied. + * @user1 + * @user2 + * + * This notified callback is for the destination client. + */ +static void ipa3_tx_comp_usr_notify_release(void *user1, int user2) +{ + struct sk_buff *skb = (struct sk_buff *)user1; + int ep_idx = user2; + + IPADBG_LOW("skb=%pK ep=%d\n", skb, ep_idx); + + IPA_STATS_INC_CNT(ipa3_ctx->stats.tx_pkts_compl); + + if (ipa3_ctx->ep[ep_idx].client_notify) + ipa3_ctx->ep[ep_idx].client_notify(ipa3_ctx->ep[ep_idx].priv, + IPA_WRITE_DONE, (unsigned long)skb); + else + dev_kfree_skb_any(skb); +} + +void ipa3_tx_cmd_comp(void *user1, int user2) +{ + ipahal_destroy_imm_cmd(user1); +} + +/** + * ipa_tx_dp() - Data-path tx handler + * @dst: [in] which IPA destination to route tx packets to + * @skb: [in] the packet to send + * @metadata: [in] TX packet meta-data + * + * Data-path tx handler, this is used for both SW data-path which by-passes most + * IPA HW blocks AND the regular HW data-path for WLAN AMPDU traffic only. If + * dst is a "valid" CONS type, then SW data-path is used. If dst is the + * WLAN_AMPDU PROD type, then HW data-path for WLAN AMPDU is used. Anything else + * is an error. For errors, client needs to free the skb as needed. For success, + * IPA driver will later invoke client callback if one was supplied. That + * callback should free the skb. If no callback supplied, IPA driver will free + * the skb internally + * + * The function will use two descriptors for this send command + * (for A5_WLAN_AMPDU_PROD only one desciprtor will be sent), + * the first descriptor will be used to inform the IPA hardware that + * apps need to push data into the IPA (IP_PACKET_INIT immediate command). + * Once this send was done from transport point-of-view the IPA driver will + * get notified by the supplied callback. + * + * Returns: 0 on success, negative on failure + */ +int ipa_tx_dp(enum ipa_client_type dst, struct sk_buff *skb, + struct ipa_tx_meta *meta) +{ + struct ipa3_desc *desc; + struct ipa3_desc _desc[3]; + int dst_ep_idx; + struct ipa3_sys_context *sys; + int src_ep_idx; + int num_frags, f; + const struct ipa_gsi_ep_config *gsi_ep; + int data_idx; + unsigned int max_desc; + + if (unlikely(!ipa3_ctx)) { + IPAERR("IPA3 driver was not initialized\n"); + return -EINVAL; + } + + if (skb->len == 0) { + IPAERR("packet size is 0\n"); + return -EINVAL; + } + + /* + * USB_CONS: PKT_INIT ep_idx = dst pipe + * Q6_CONS: PKT_INIT ep_idx = sender pipe + * A5_LAN_WAN_PROD: HW path ep_idx = sender pipe + * + * LAN TX: all PKT_INIT + * WAN TX: PKT_INIT (cmd) + HW (data) + * + */ + if (IPA_CLIENT_IS_CONS(dst)) { + src_ep_idx = ipa_get_ep_mapping(IPA_CLIENT_APPS_LAN_PROD); + if (-1 == src_ep_idx) { + IPAERR("Client %u is not mapped\n", + IPA_CLIENT_APPS_LAN_PROD); + goto fail_gen; + } + dst_ep_idx = ipa_get_ep_mapping(dst); + } else { + src_ep_idx = ipa_get_ep_mapping(dst); + if (-1 == src_ep_idx) { + IPAERR("Client %u is not mapped\n", dst); + goto fail_gen; + } + if (meta && meta->pkt_init_dst_ep_valid) + dst_ep_idx = meta->pkt_init_dst_ep; + else + dst_ep_idx = -1; + } + + sys = ipa3_ctx->ep[src_ep_idx].sys; + + if (!sys || !sys->ep->valid) { + IPAERR_RL("pipe %d not valid\n", src_ep_idx); + goto fail_pipe_not_valid; + } + + trace_ipa_tx_dp(skb,sys->ep->client); + num_frags = skb_shinfo(skb)->nr_frags; + /* + * make sure TLV FIFO supports the needed frags. + * 2 descriptors are needed for IP_PACKET_INIT and TAG_STATUS. + * 1 descriptor needed for the linear portion of skb. + */ + gsi_ep = ipa_get_gsi_ep_info(ipa3_ctx->ep[src_ep_idx].client); + if (unlikely(gsi_ep == NULL)) { + IPAERR("failed to get EP %d GSI info\n", src_ep_idx); + goto fail_gen; + } + max_desc = gsi_ep->ipa_if_tlv; + if (gsi_ep->prefetch_mode == GSI_SMART_PRE_FETCH || + gsi_ep->prefetch_mode == GSI_FREE_PRE_FETCH) + max_desc -= gsi_ep->prefetch_threshold; + if (num_frags + 3 > max_desc) { + if (skb_linearize(skb)) { + IPAERR("Failed to linear skb with %d frags\n", + num_frags); + goto fail_gen; + } + num_frags = 0; + } + if (num_frags) { + /* 1 desc for tag to resolve status out-of-order issue; + * 1 desc is needed for the linear portion of skb; + * 1 desc may be needed for the PACKET_INIT; + * 1 desc for each frag + */ + desc = kzalloc(sizeof(*desc) * (num_frags + 3), GFP_ATOMIC); + if (!desc) { + IPAERR("failed to alloc desc array\n"); + goto fail_gen; + } + } else { + memset(_desc, 0, 3 * sizeof(struct ipa3_desc)); + desc = &_desc[0]; + } + + if (dst_ep_idx != -1) { + /* SW data path */ + int skb_idx; + struct iphdr *network_header; + + network_header = (struct iphdr *)(skb_network_header(skb)); + + data_idx = 0; + + if (sys->policy == IPA_POLICY_NOINTR_MODE) { + /* + * For non-interrupt mode channel (where there is no + * event ring) TAG STATUS are used for completion + * notification. IPA will generate a status packet with + * tag info as a result of the TAG STATUS command. + */ + desc[data_idx].is_tag_status = true; + data_idx++; + } + + if ((ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0) && + ((network_header->version == 4 && + network_header->protocol == IPPROTO_ICMP) || + (((struct ipv6hdr *)network_header)->version == 6 && + ((struct ipv6hdr *)network_header)->nexthdr == NEXTHDR_ICMP))) { + ipa_imm_cmd_modify_ip_packet_init_ex_dest_pipe( + ipa3_ctx->pkt_init_ex_imm[ipa3_ctx->ipa_num_pipes].base, + dst_ep_idx); + desc[data_idx].opcode = ipa3_ctx->pkt_init_ex_imm_opcode; + desc[data_idx].dma_address = + ipa3_ctx->pkt_init_ex_imm[ipa3_ctx->ipa_num_pipes].phys_base; + } else if (ipa3_ctx->ep[dst_ep_idx].cfg.ulso.is_ulso_pipe && + skb_is_gso(skb)) { + desc[data_idx].opcode = ipa3_ctx->pkt_init_ex_imm_opcode; + desc[data_idx].dma_address = + ipa3_ctx->pkt_init_ex_imm[dst_ep_idx].phys_base; + } else { + desc[data_idx].opcode = ipa3_ctx->pkt_init_imm_opcode; + desc[data_idx].dma_address = ipa3_ctx->pkt_init_imm[dst_ep_idx]; + } + desc[data_idx].dma_address_valid = true; + desc[data_idx].type = IPA_IMM_CMD_DESC; + desc[data_idx].callback = NULL; + data_idx++; + desc[data_idx].pyld = skb->data; + desc[data_idx].len = skb_headlen(skb); + desc[data_idx].type = IPA_DATA_DESC_SKB; + desc[data_idx].callback = ipa3_tx_comp_usr_notify_release; + desc[data_idx].user1 = skb; + desc[data_idx].user2 = (meta && meta->pkt_init_dst_ep_valid && + meta->pkt_init_dst_ep_remote) ? + src_ep_idx : + dst_ep_idx; + if (meta && meta->dma_address_valid) { + desc[data_idx].dma_address_valid = true; + desc[data_idx].dma_address = meta->dma_address; + } + + skb_idx = data_idx; + data_idx++; + + for (f = 0; f < num_frags; f++) { + desc[data_idx + f].frag = &skb_shinfo(skb)->frags[f]; + desc[data_idx + f].type = IPA_DATA_DESC_SKB_PAGED; + desc[data_idx + f].len = + skb_frag_size(desc[data_idx + f].frag); + } + /* don't free skb till frag mappings are released */ + if (num_frags) { + desc[data_idx + f - 1].callback = + desc[skb_idx].callback; + desc[data_idx + f - 1].user1 = desc[skb_idx].user1; + desc[data_idx + f - 1].user2 = desc[skb_idx].user2; + desc[skb_idx].callback = NULL; + } + + if (ipa3_send(sys, num_frags + data_idx, desc, true)) { + IPAERR_RL("fail to send skb %pK num_frags %u SWP\n", + skb, num_frags); + goto fail_send; + } + IPA_STATS_INC_CNT(ipa3_ctx->stats.tx_sw_pkts); + } else { + /* HW data path */ + data_idx = 0; + if (sys->policy == IPA_POLICY_NOINTR_MODE) { + /* + * For non-interrupt mode channel (where there is no + * event ring) TAG STATUS are used for completion + * notification. IPA will generate a status packet with + * tag info as a result of the TAG STATUS command. + */ + desc[data_idx].is_tag_status = true; + data_idx++; + } + desc[data_idx].pyld = skb->data; + desc[data_idx].len = skb_headlen(skb); + desc[data_idx].type = IPA_DATA_DESC_SKB; + desc[data_idx].callback = ipa3_tx_comp_usr_notify_release; + desc[data_idx].user1 = skb; + desc[data_idx].user2 = src_ep_idx; + + if (meta && meta->dma_address_valid) { + desc[data_idx].dma_address_valid = true; + desc[data_idx].dma_address = meta->dma_address; + } + if (num_frags == 0) { + if (ipa3_send(sys, data_idx + 1, desc, true)) { + IPAERR_RL("fail to send skb %pK HWP\n", skb); + goto fail_mem; + } + } else { + for (f = 0; f < num_frags; f++) { + desc[data_idx+f+1].frag = + &skb_shinfo(skb)->frags[f]; + desc[data_idx+f+1].type = + IPA_DATA_DESC_SKB_PAGED; + desc[data_idx+f+1].len = + skb_frag_size(desc[data_idx+f+1].frag); + } + /* don't free skb till frag mappings are released */ + desc[data_idx+f].callback = desc[data_idx].callback; + desc[data_idx+f].user1 = desc[data_idx].user1; + desc[data_idx+f].user2 = desc[data_idx].user2; + desc[data_idx].callback = NULL; + + if (ipa3_send(sys, num_frags + data_idx + 1, + desc, true)) { + IPAERR_RL("fail to send skb %pK num_frags %u\n", + skb, num_frags); + goto fail_mem; + } + } + IPA_STATS_INC_CNT(ipa3_ctx->stats.tx_hw_pkts); + } + + trace_ipa3_tx_done(sys->ep->client); + if (num_frags) { + kfree(desc); + IPA_STATS_INC_CNT(ipa3_ctx->stats.tx_non_linear); + } + return 0; + +fail_send: +fail_mem: + if (num_frags) + kfree(desc); +fail_gen: + return -EFAULT; +fail_pipe_not_valid: + return -EPIPE; +} +EXPORT_SYMBOL(ipa_tx_dp); + +static void ipa3_wq_handle_rx(struct work_struct *work) +{ + struct ipa3_sys_context *sys; + enum ipa_client_type client_type; + + sys = container_of(work, struct ipa3_sys_context, work); + /* + * Mark client as WAN_COAL_CONS only as + * NAPI only use sys of WAN_COAL_CONS. + */ + if (IPA_CLIENT_IS_WAN_CONS(sys->ep->client)) + client_type = IPA_CLIENT_APPS_WAN_COAL_CONS; + else if (IPA_CLIENT_IS_LAN_CONS(sys->ep->client)) + client_type = IPA_CLIENT_APPS_LAN_COAL_CONS; + else + client_type = sys->ep->client; + + IPA_ACTIVE_CLIENTS_INC_EP(client_type); + if (ipa_net_initialized && sys->napi_obj) { + napi_schedule(sys->napi_obj); + } else if (ipa_net_initialized && + sys->ep->client == IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_CONS) { + napi_schedule(&sys->napi_rx); + } else if (IPA_CLIENT_IS_LOW_LAT_CONS(sys->ep->client)) { + tasklet_schedule(&sys->tasklet); + } else + ipa3_handle_rx(sys); +} + +static void ipa3_wq_repl_rx(struct work_struct *work) +{ + struct ipa3_sys_context *sys; + void *ptr; + struct ipa3_rx_pkt_wrapper *rx_pkt; + gfp_t flag = GFP_KERNEL; + u32 next; + u32 curr; + + sys = container_of(work, struct ipa3_sys_context, repl_work); + atomic_set(&sys->repl->pending, 0); + curr = atomic_read(&sys->repl->tail_idx); + +begin: + while (1) { + next = (curr + 1) % sys->repl->capacity; + if (next == atomic_read(&sys->repl->head_idx)) + goto fail_kmem_cache_alloc; + + rx_pkt = kmem_cache_zalloc(ipa3_ctx->rx_pkt_wrapper_cache, + flag); + if (!rx_pkt) + goto fail_kmem_cache_alloc; + + INIT_WORK(&rx_pkt->work, ipa3_wq_rx_avail); + rx_pkt->sys = sys; + + rx_pkt->data.skb = sys->get_skb(sys->rx_buff_sz, flag); + if (rx_pkt->data.skb == NULL) + goto fail_skb_alloc; + + ptr = skb_put(rx_pkt->data.skb, sys->rx_buff_sz); + rx_pkt->data.dma_addr = dma_map_single(ipa3_ctx->pdev, ptr, + sys->rx_buff_sz, + DMA_FROM_DEVICE); + if (dma_mapping_error(ipa3_ctx->pdev, rx_pkt->data.dma_addr)) { + pr_err_ratelimited("%s dma map fail %pK for %pK sys=%pK\n", + __func__, (void *)rx_pkt->data.dma_addr, + ptr, sys); + goto fail_dma_mapping; + } + + sys->repl->cache[curr] = rx_pkt; + curr = next; + /* ensure write is done before setting tail index */ + mb(); + atomic_set(&sys->repl->tail_idx, next); + } + + return; + +fail_dma_mapping: + sys->free_skb(rx_pkt->data.skb); +fail_skb_alloc: + kmem_cache_free(ipa3_ctx->rx_pkt_wrapper_cache, rx_pkt); +fail_kmem_cache_alloc: + if (atomic_read(&sys->repl->tail_idx) == + atomic_read(&sys->repl->head_idx)) { + if (IPA_CLIENT_IS_WAN_CONS(sys->ep->client)) + IPA_STATS_INC_CNT(ipa3_ctx->stats.wan_repl_rx_empty); + else if (IPA_CLIENT_IS_LAN_CONS(sys->ep->client)) + IPA_STATS_INC_CNT(ipa3_ctx->stats.lan_repl_rx_empty); + else if (sys->ep->client == IPA_CLIENT_APPS_WAN_LOW_LAT_CONS) + IPA_STATS_INC_CNT(ipa3_ctx->stats.low_lat_repl_rx_empty); + else if (sys->ep->client == IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_CONS) + IPA_STATS_INC_CNT(ipa3_ctx->stats.rmnet_ll_repl_rx_empty); + pr_err_ratelimited("%s sys=%pK repl ring empty\n", + __func__, sys); + goto begin; + } +} + +static struct page *ipa3_alloc_page( + gfp_t flag, u32 *page_order, bool try_lower) +{ + struct page *page = NULL; + u32 p_order = *page_order; + + page = __dev_alloc_pages(flag, p_order); + /* We will only try 1 page order lower. */ + if (unlikely(!page)) { + if (try_lower && p_order > 0) { + p_order = p_order - 1; + page = __dev_alloc_pages(flag, p_order); + if (likely(page)) + ipa3_ctx->stats.lower_order++; + } + } + *page_order = p_order; + return page; +} + +#ifdef CONFIG_IPA_RMNET_MEM +static struct page *ipa3_rmnet_alloc_page( + gfp_t flag, u32 *page_order, bool try_lower) +{ + struct page *page = NULL; + u32 p_order = *page_order; + int rc, porder; + + while (true) { + page = rmnet_mem_get_pages_entry( + flag, p_order, &rc, &porder, IPA_ID); + + if (unlikely(!page)) { + if (p_order > 0) { + p_order = p_order - 1; + continue; + } + break; + } + + ipa3_ctx->stats.lower_order++; + break; + } + + if (unlikely(!page)) + IPAERR("rmnet page alloc fails\n"); + + *page_order = p_order; + return page; +} +#endif + +static struct ipa3_rx_pkt_wrapper *ipa3_alloc_rx_pkt_page( + gfp_t flag, bool is_tmp_alloc, struct ipa3_sys_context *sys) +{ + struct ipa3_rx_pkt_wrapper *rx_pkt; + + flag |= __GFP_NOMEMALLOC; + rx_pkt = kmem_cache_zalloc(ipa3_ctx->rx_pkt_wrapper_cache, + flag); + if (unlikely(!rx_pkt)) + return NULL; + + rx_pkt->page_data.page_order = sys->page_order; + /* For temporary allocations, avoid triggering OOM Killer. */ + if (is_tmp_alloc) { + flag |= __GFP_RETRY_MAYFAIL | __GFP_NOWARN; +#ifdef CONFIG_IPA_RMNET_MEM + rx_pkt->page_data.page = ipa3_rmnet_alloc_page( + flag, &rx_pkt->page_data.page_order, true); +#else + rx_pkt->page_data.page = ipa3_alloc_page(flag, + &rx_pkt->page_data.page_order, + (is_tmp_alloc && rx_pkt->page_data.page_order == 3)); +#endif + } else { + /* Try a lower order page for order 3 pages in case allocation fails. */ + rx_pkt->page_data.page = ipa3_alloc_page(flag, + &rx_pkt->page_data.page_order, + (is_tmp_alloc && rx_pkt->page_data.page_order == 3)); + } + + if (unlikely(!rx_pkt->page_data.page)) + goto fail_page_alloc; + + rx_pkt->len = PAGE_SIZE << rx_pkt->page_data.page_order; + + rx_pkt->page_data.dma_addr = dma_map_page(ipa3_ctx->pdev, + rx_pkt->page_data.page, 0, + rx_pkt->len, DMA_FROM_DEVICE); + if (dma_mapping_error(ipa3_ctx->pdev, + rx_pkt->page_data.dma_addr)) { + pr_err_ratelimited("%s dma map fail %pK for %pK\n", + __func__, (void *)rx_pkt->page_data.dma_addr, + rx_pkt->page_data.page); + goto fail_dma_mapping; + } + if (is_tmp_alloc) + rx_pkt->page_data.is_tmp_alloc = true; + else + rx_pkt->page_data.is_tmp_alloc = false; + return rx_pkt; + +fail_dma_mapping: + __free_pages(rx_pkt->page_data.page, rx_pkt->page_data.page_order); +fail_page_alloc: + kmem_cache_free(ipa3_ctx->rx_pkt_wrapper_cache, rx_pkt); + return NULL; +} + +static void ipa3_replenish_rx_page_cache(struct ipa3_sys_context *sys) +{ + struct ipa3_rx_pkt_wrapper *rx_pkt; + u32 curr; + + for (curr = 0; curr < sys->page_recycle_repl->capacity; curr++) { + rx_pkt = ipa3_alloc_rx_pkt_page(GFP_KERNEL, false, sys); + if (!rx_pkt) { + IPAERR("ipa3_alloc_rx_pkt_page fails\n"); + ipa_assert(); + break; + } + INIT_LIST_HEAD(&rx_pkt->link); + rx_pkt->sys = sys; + list_add_tail(&rx_pkt->link, + &sys->page_recycle_repl->page_repl_head); + } + atomic_set(&sys->common_sys->page_avilable, 1); + + return; + +} + +static void ipa3_wq_page_repl(struct work_struct *work) +{ + struct ipa3_sys_context *sys; + struct ipa3_rx_pkt_wrapper *rx_pkt; + u32 next; + u32 curr; + + sys = container_of(work, struct ipa3_sys_context, repl_work); + atomic_set(&sys->repl->pending, 0); + curr = atomic_read(&sys->repl->tail_idx); + +begin: + while (1) { + next = (curr + 1) % sys->repl->capacity; + if (unlikely(next == atomic_read(&sys->repl->head_idx))) + goto fail_kmem_cache_alloc; + rx_pkt = ipa3_alloc_rx_pkt_page(GFP_KERNEL, true, sys); + if (unlikely(!rx_pkt)) { + IPAERR("ipa3_alloc_rx_pkt_page fails\n"); + break; + } + rx_pkt->sys = sys; + sys->repl->cache[curr] = rx_pkt; + curr = next; + /* ensure write is done before setting tail index */ + mb(); + atomic_set(&sys->repl->tail_idx, next); + } + + return; + +fail_kmem_cache_alloc: + if (atomic_read(&sys->repl->tail_idx) == + atomic_read(&sys->repl->head_idx)) { + if (sys->ep->client == IPA_CLIENT_APPS_WAN_CONS || + sys->ep->client == IPA_CLIENT_APPS_WAN_COAL_CONS) + IPA_STATS_INC_CNT(ipa3_ctx->stats.wan_repl_rx_empty); + if (sys->ep->client == IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_CONS) + IPA_STATS_INC_CNT(ipa3_ctx->stats.rmnet_ll_repl_rx_empty); + pr_err_ratelimited("%s sys=%pK wq_repl ring empty\n", + __func__, sys); + goto begin; + } + +} + +static inline void __trigger_repl_work(struct ipa3_sys_context *sys) +{ + int tail, head, avail; + + if (atomic_read(&sys->repl->pending)) + return; + + tail = atomic_read(&sys->repl->tail_idx); + head = atomic_read(&sys->repl->head_idx); + avail = (tail - head) % sys->repl->capacity; + + if (avail < sys->repl->capacity / 2) { + atomic_set(&sys->repl->pending, 1); + queue_work(sys->repl_wq, &sys->repl_work); + } +} + +static struct ipa3_rx_pkt_wrapper * ipa3_get_free_page +( + struct ipa3_sys_context *sys, + u32 stats_i +) +{ + struct ipa3_rx_pkt_wrapper *rx_pkt = NULL; + struct ipa3_rx_pkt_wrapper *tmp = NULL; + struct page *cur_page; + int i = 0; + u8 LOOP_THRESHOLD = ipa3_ctx->page_poll_threshold; + + spin_lock_bh(&sys->common_sys->spinlock); + list_for_each_entry_safe(rx_pkt, tmp, + &sys->page_recycle_repl->page_repl_head, link) { + if (i == LOOP_THRESHOLD) + break; + cur_page = rx_pkt->page_data.page; + if (page_ref_count(cur_page) == 1) { + /* Found a free page. */ + page_ref_inc(cur_page); + list_del_init(&rx_pkt->link); + ++ipa3_ctx->stats.page_recycle_cnt[stats_i][i]; + sys->common_sys->napi_sort_page_thrshld_cnt = 0; + spin_unlock_bh(&sys->common_sys->spinlock); + return rx_pkt; + } + i++; + } + spin_unlock_bh(&sys->common_sys->spinlock); + IPADBG_LOW("napi_sort_page_thrshld_cnt = %d ipa_max_napi_sort_page_thrshld = %d\n", + sys->common_sys->napi_sort_page_thrshld_cnt, + ipa3_ctx->ipa_max_napi_sort_page_thrshld); + /*Scheduling tasklet to find the free page*/ + if (sys->common_sys->napi_sort_page_thrshld_cnt >= + ipa3_ctx->ipa_max_napi_sort_page_thrshld) { + atomic_set(&sys->common_sys->page_avilable, 0); + tasklet_schedule(&sys->common_sys->tasklet_find_freepage); + ++ipa3_ctx->stats.num_sort_tasklet_sched[stats_i]; + spin_lock(&ipa3_ctx->notifier_lock); + if(ipa3_ctx->ipa_rmnet_notifier_enabled && + !ipa3_ctx->free_page_task_scheduled) { + atomic_inc(&ipa3_ctx->stats.num_free_page_task_scheduled); + if (stats_i ==2) { + raw_notifier_call_chain(ipa3_ctx->ipa_rmnet_notifier_list_internal, + FREE_PAGE_TASK_SCHEDULED_LL, &sys->common_sys->napi_sort_page_thrshld_cnt); + } + else { + raw_notifier_call_chain(ipa3_ctx->ipa_rmnet_notifier_list_internal, + FREE_PAGE_TASK_SCHEDULED, &sys->common_sys->napi_sort_page_thrshld_cnt); + } + ipa3_ctx->free_page_task_scheduled = true; + } + spin_unlock(&ipa3_ctx->notifier_lock); + } + return NULL; +} + +int ipa_register_notifier(void *fn_ptr) +{ + struct ipa_notifier_block_data *ipa_notifier_block; + if (fn_ptr == NULL) + return -EFAULT; + spin_lock(&ipa3_ctx->notifier_lock); + ipa_notifier_block = (struct ipa_notifier_block_data *)kzalloc(sizeof(struct ipa_notifier_block_data), GFP_KERNEL); + if (ipa_notifier_block == NULL) { + IPAWANERR("Buffer threshold notifier failure\n"); + spin_unlock(&ipa3_ctx->notifier_lock); + return -EFAULT; + } + ipa_notifier_block->ipa_rmnet_notifier.notifier_call = fn_ptr; + list_add(&ipa_notifier_block->entry, &ipa3_ctx->notifier_block_list_head); + raw_notifier_chain_register(ipa3_ctx->ipa_rmnet_notifier_list_internal, + &ipa_notifier_block->ipa_rmnet_notifier); + IPAWANERR("Registered noifier for buffer threshold\n"); + + ipa3_ctx->ipa_rmnet_notifier_enabled = true; + spin_unlock(&ipa3_ctx->notifier_lock); + return 0; +} +EXPORT_SYMBOL(ipa_register_notifier); + +int ipa_unregister_notifier(void *fn_ptr) +{ + struct ipa_notifier_block_data *ipa_notifier_block, *temp; + if (fn_ptr == NULL) + return -EFAULT; + spin_lock(&ipa3_ctx->notifier_lock); + /* Find the client pointer, unregister and remove from the list */ + list_for_each_entry_safe(ipa_notifier_block, temp, &ipa3_ctx->notifier_block_list_head, entry) { + if (ipa_notifier_block->ipa_rmnet_notifier.notifier_call == fn_ptr) { + raw_notifier_chain_unregister(ipa3_ctx->ipa_rmnet_notifier_list_internal, + &ipa_notifier_block->ipa_rmnet_notifier); + list_del(&ipa_notifier_block->entry); + kfree(ipa_notifier_block); + IPAWANERR("Client removed from list and unregistered succesfully\n"); + spin_unlock(&ipa3_ctx->notifier_lock); + return 0; + } + } + spin_unlock(&ipa3_ctx->notifier_lock); + IPAWANERR("Unable to find the client in the list\n"); + return 0; +} +EXPORT_SYMBOL(ipa_unregister_notifier); + + static void ipa3_replenish_rx_page_recycle(struct ipa3_sys_context *sys) +{ + struct ipa3_rx_pkt_wrapper *rx_pkt; + int ret; + int rx_len_cached = 0; + struct gsi_xfer_elem gsi_xfer_elem_array[IPA_REPL_XFER_MAX]; + u32 curr_wq; + int idx = 0; + u32 stats_i = 0; + + /* start replenish only when buffers go lower than the threshold */ + if (sys->rx_pool_sz - sys->len < IPA_REPL_XFER_THRESH) + return; + switch (sys->ep->client) { + case IPA_CLIENT_APPS_WAN_COAL_CONS: + stats_i = 0; + break; + case IPA_CLIENT_APPS_WAN_CONS: + stats_i = 1; + break; + case IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_CONS: + stats_i = 2; + break; + default: + IPAERR_RL("Unexpected client%d\n", sys->ep->client); + } + + rx_len_cached = sys->len; + curr_wq = atomic_read(&sys->repl->head_idx); + + while (rx_len_cached < sys->rx_pool_sz) { + /* check for an idle page that can be used */ + if (atomic_read(&sys->common_sys->page_avilable) && + ((rx_pkt = ipa3_get_free_page(sys,stats_i)) != NULL)) { + ipa3_ctx->stats.page_recycle_stats[stats_i].page_recycled++; + + } else { + /* + * Could not find idle page at curr index. + * Allocate a new one. + */ + if (curr_wq == atomic_read(&sys->repl->tail_idx)) + break; + ipa3_ctx->stats.page_recycle_stats[stats_i].tmp_alloc++; + rx_pkt = sys->repl->cache[curr_wq]; + curr_wq = (++curr_wq == sys->repl->capacity) ? + 0 : curr_wq; + } + rx_pkt->sys = sys; + + trace_ipa3_replenish_rx_page_recycle( + stats_i, + rx_pkt->page_data.page, + rx_pkt->page_data.is_tmp_alloc); + + dma_sync_single_for_device(ipa3_ctx->pdev, + rx_pkt->page_data.dma_addr, + rx_pkt->len, DMA_FROM_DEVICE); + gsi_xfer_elem_array[idx].addr = rx_pkt->page_data.dma_addr; + gsi_xfer_elem_array[idx].len = rx_pkt->len; + gsi_xfer_elem_array[idx].flags = GSI_XFER_FLAG_EOT; + gsi_xfer_elem_array[idx].flags |= GSI_XFER_FLAG_EOB; + gsi_xfer_elem_array[idx].flags |= GSI_XFER_FLAG_BEI; + gsi_xfer_elem_array[idx].type = GSI_XFER_ELEM_DATA; + gsi_xfer_elem_array[idx].xfer_user_data = rx_pkt; + rx_len_cached++; + idx++; + ipa3_ctx->stats.page_recycle_stats[stats_i].total_replenished++; + /* + * gsi_xfer_elem_buffer has a size of IPA_REPL_XFER_THRESH. + * If this size is reached we need to queue the xfers. + */ + if (idx == IPA_REPL_XFER_MAX) { + ret = gsi_queue_xfer(sys->ep->gsi_chan_hdl, idx, + gsi_xfer_elem_array, false); + if (ret != GSI_STATUS_SUCCESS) { + /* we don't expect this will happen */ + IPAERR("failed to provide buffer: %d\n", ret); + ipa_assert(); + break; + } + idx = 0; + } + } + /* only ring doorbell once here */ + ret = gsi_queue_xfer(sys->ep->gsi_chan_hdl, idx, + gsi_xfer_elem_array, true); + if (ret == GSI_STATUS_SUCCESS) { + /* ensure write is done before setting head index */ + mb(); + atomic_set(&sys->repl->head_idx, curr_wq); + sys->len = rx_len_cached; + } else { + /* we don't expect this will happen */ + IPAERR("failed to provide buffer: %d\n", ret); + ipa_assert(); + } + + if (sys->common_buff_pool) + __trigger_repl_work(sys->common_sys); + else + __trigger_repl_work(sys); + + if (rx_len_cached <= IPA_DEFAULT_SYS_YELLOW_WM) { + if (sys->ep->client == IPA_CLIENT_APPS_WAN_CONS) { + IPA_STATS_INC_CNT(ipa3_ctx->stats.wan_rx_empty); + spin_lock(&ipa3_ctx->notifier_lock); + if (ipa3_ctx->ipa_rmnet_notifier_enabled + && !ipa3_ctx->buff_below_thresh_for_def_pipe_notified) { + atomic_inc(&ipa3_ctx->stats.num_buff_below_thresh_for_def_pipe_notified); + raw_notifier_call_chain(ipa3_ctx->ipa_rmnet_notifier_list_internal, + BUFF_BELOW_LOW_THRESHOLD_FOR_DEFAULT_PIPE, &rx_len_cached); + ipa3_ctx->buff_above_thresh_for_def_pipe_notified = false; + ipa3_ctx->buff_below_thresh_for_def_pipe_notified = true; + } + spin_unlock(&ipa3_ctx->notifier_lock); + } + else if (sys->ep->client == IPA_CLIENT_APPS_WAN_COAL_CONS) { + IPA_STATS_INC_CNT(ipa3_ctx->stats.wan_rx_empty_coal); + spin_lock(&ipa3_ctx->notifier_lock); + if (ipa3_ctx->ipa_rmnet_notifier_enabled + && !ipa3_ctx->buff_below_thresh_for_coal_pipe_notified) { + atomic_inc(&ipa3_ctx->stats.num_buff_below_thresh_for_coal_pipe_notified); + raw_notifier_call_chain(ipa3_ctx->ipa_rmnet_notifier_list_internal, + BUFF_BELOW_LOW_THRESHOLD_FOR_COAL_PIPE, &rx_len_cached); + ipa3_ctx->buff_above_thresh_for_coal_pipe_notified = false; + ipa3_ctx->buff_below_thresh_for_coal_pipe_notified = true; + } + spin_unlock(&ipa3_ctx->notifier_lock); + } + else if (sys->ep->client == IPA_CLIENT_APPS_LAN_CONS) + IPA_STATS_INC_CNT(ipa3_ctx->stats.lan_rx_empty); + else if (sys->ep->client == IPA_CLIENT_APPS_LAN_COAL_CONS) + IPA_STATS_INC_CNT(ipa3_ctx->stats.lan_rx_empty_coal); + else if (sys->ep->client == IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_CONS) { + IPA_STATS_INC_CNT(ipa3_ctx->stats.rmnet_ll_rx_empty); + spin_lock(&ipa3_ctx->notifier_lock); + if (ipa3_ctx->ipa_rmnet_notifier_enabled + && !ipa3_ctx->buff_below_thresh_for_ll_pipe_notified) { + atomic_inc(&ipa3_ctx->stats.num_buff_below_thresh_for_ll_pipe_notified); + raw_notifier_call_chain(ipa3_ctx->ipa_rmnet_notifier_list_internal, + BUFF_BELOW_LOW_THRESHOLD_FOR_LL_PIPE, &rx_len_cached); + ipa3_ctx->buff_above_thresh_for_ll_pipe_notified = false; + ipa3_ctx->buff_below_thresh_for_ll_pipe_notified = true; + } + spin_unlock(&ipa3_ctx->notifier_lock); + } + else + WARN_ON(1); + } + + if (rx_len_cached >= IPA_BUFF_THRESHOLD_HIGH) { + if (sys->ep->client == IPA_CLIENT_APPS_WAN_CONS) { + spin_lock(&ipa3_ctx->notifier_lock); + if(ipa3_ctx->ipa_rmnet_notifier_enabled && + !ipa3_ctx->buff_above_thresh_for_def_pipe_notified) { + atomic_inc(&ipa3_ctx->stats.num_buff_above_thresh_for_def_pipe_notified); + raw_notifier_call_chain(ipa3_ctx->ipa_rmnet_notifier_list_internal, + BUFF_ABOVE_HIGH_THRESHOLD_FOR_DEFAULT_PIPE, &rx_len_cached); + ipa3_ctx->buff_above_thresh_for_def_pipe_notified = true; + ipa3_ctx->buff_below_thresh_for_def_pipe_notified = false; + } + spin_unlock(&ipa3_ctx->notifier_lock); + } else if (sys->ep->client == IPA_CLIENT_APPS_WAN_COAL_CONS) { + spin_lock(&ipa3_ctx->notifier_lock); + if(ipa3_ctx->ipa_rmnet_notifier_enabled && + !ipa3_ctx->buff_above_thresh_for_coal_pipe_notified) { + atomic_inc(&ipa3_ctx->stats.num_buff_above_thresh_for_coal_pipe_notified); + raw_notifier_call_chain(ipa3_ctx->ipa_rmnet_notifier_list_internal, + BUFF_ABOVE_HIGH_THRESHOLD_FOR_COAL_PIPE, &rx_len_cached); + ipa3_ctx->buff_above_thresh_for_coal_pipe_notified = true; + ipa3_ctx->buff_below_thresh_for_coal_pipe_notified = false; + } + spin_unlock(&ipa3_ctx->notifier_lock); + } else if (sys->ep->client == IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_CONS) { + spin_lock(&ipa3_ctx->notifier_lock); + if(ipa3_ctx->ipa_rmnet_notifier_enabled && + !ipa3_ctx->buff_above_thresh_for_ll_pipe_notified) { + atomic_inc(&ipa3_ctx->stats.num_buff_above_thresh_for_ll_pipe_notified); + raw_notifier_call_chain(ipa3_ctx->ipa_rmnet_notifier_list_internal, + BUFF_ABOVE_HIGH_THRESHOLD_FOR_LL_PIPE, &rx_len_cached); + ipa3_ctx->buff_above_thresh_for_ll_pipe_notified = true; + ipa3_ctx->buff_below_thresh_for_ll_pipe_notified = false; + } + spin_unlock(&ipa3_ctx->notifier_lock); + } + } + + return; +} + +static void ipa3_replenish_wlan_rx_cache(struct ipa3_sys_context *sys) +{ + struct ipa3_rx_pkt_wrapper *rx_pkt = NULL; + struct ipa3_rx_pkt_wrapper *tmp; + int ret; + struct gsi_xfer_elem gsi_xfer_elem_one; + u32 rx_len_cached = 0; + + IPADBG_LOW("\n"); + + spin_lock_bh(&ipa3_ctx->wc_memb.wlan_spinlock); + rx_len_cached = sys->len; + + if (rx_len_cached < sys->rx_pool_sz) { + list_for_each_entry_safe(rx_pkt, tmp, + &ipa3_ctx->wc_memb.wlan_comm_desc_list, link) { + list_del(&rx_pkt->link); + + if (ipa3_ctx->wc_memb.wlan_comm_free_cnt > 0) + ipa3_ctx->wc_memb.wlan_comm_free_cnt--; + + rx_pkt->len = 0; + rx_pkt->sys = sys; + + memset(&gsi_xfer_elem_one, 0, + sizeof(gsi_xfer_elem_one)); + gsi_xfer_elem_one.addr = rx_pkt->data.dma_addr; + gsi_xfer_elem_one.len = IPA_WLAN_RX_BUFF_SZ; + gsi_xfer_elem_one.flags |= GSI_XFER_FLAG_EOT; + gsi_xfer_elem_one.flags |= GSI_XFER_FLAG_EOB; + gsi_xfer_elem_one.type = GSI_XFER_ELEM_DATA; + gsi_xfer_elem_one.xfer_user_data = rx_pkt; + + ret = gsi_queue_xfer(sys->ep->gsi_chan_hdl, 1, + &gsi_xfer_elem_one, true); + + if (ret) { + IPAERR("failed to provide buffer: %d\n", ret); + goto fail_provide_rx_buffer; + } + + rx_len_cached = ++sys->len; + + if (rx_len_cached >= sys->rx_pool_sz) { + spin_unlock_bh( + &ipa3_ctx->wc_memb.wlan_spinlock); + return; + } + } + } + spin_unlock_bh(&ipa3_ctx->wc_memb.wlan_spinlock); + + if (rx_len_cached < sys->rx_pool_sz && + ipa3_ctx->wc_memb.wlan_comm_total_cnt < + IPA_WLAN_COMM_RX_POOL_HIGH) { + ipa3_replenish_rx_cache(sys); + ipa3_ctx->wc_memb.wlan_comm_total_cnt += + (sys->len - rx_len_cached); + } + + return; + +fail_provide_rx_buffer: + list_del(&rx_pkt->link); + spin_unlock_bh(&ipa3_ctx->wc_memb.wlan_spinlock); +} + +static void ipa3_cleanup_wlan_rx_common_cache(void) +{ + struct ipa3_rx_pkt_wrapper *rx_pkt; + struct ipa3_rx_pkt_wrapper *tmp; + + spin_lock_bh(&ipa3_ctx->wc_memb.wlan_spinlock); + + list_for_each_entry_safe(rx_pkt, tmp, + &ipa3_ctx->wc_memb.wlan_comm_desc_list, link) { + list_del(&rx_pkt->link); + dma_unmap_single(ipa3_ctx->pdev, rx_pkt->data.dma_addr, + IPA_WLAN_RX_BUFF_SZ, DMA_FROM_DEVICE); + dev_kfree_skb_any(rx_pkt->data.skb); + kmem_cache_free(ipa3_ctx->rx_pkt_wrapper_cache, rx_pkt); + ipa3_ctx->wc_memb.wlan_comm_free_cnt--; + ipa3_ctx->wc_memb.wlan_comm_total_cnt--; + } + ipa3_ctx->wc_memb.total_tx_pkts_freed = 0; + + if (ipa3_ctx->wc_memb.wlan_comm_free_cnt != 0) + IPAERR("wlan comm buff free cnt: %d\n", + ipa3_ctx->wc_memb.wlan_comm_free_cnt); + + if (ipa3_ctx->wc_memb.wlan_comm_total_cnt != 0) + IPAERR("wlan comm buff total cnt: %d\n", + ipa3_ctx->wc_memb.wlan_comm_total_cnt); + + spin_unlock_bh(&ipa3_ctx->wc_memb.wlan_spinlock); + +} + +static void ipa3_alloc_wlan_rx_common_cache(u32 size) +{ + void *ptr; + struct ipa3_rx_pkt_wrapper *rx_pkt; + int rx_len_cached = 0; + gfp_t flag = GFP_NOWAIT | __GFP_NOWARN; + + rx_len_cached = ipa3_ctx->wc_memb.wlan_comm_total_cnt; + while (rx_len_cached < size) { + rx_pkt = kmem_cache_zalloc(ipa3_ctx->rx_pkt_wrapper_cache, + flag); + if (!rx_pkt) + goto fail_kmem_cache_alloc; + + INIT_LIST_HEAD(&rx_pkt->link); + INIT_WORK(&rx_pkt->work, ipa3_wq_rx_avail); + + rx_pkt->data.skb = + ipa3_get_skb_ipa_rx(IPA_WLAN_RX_BUFF_SZ, + flag); + if (rx_pkt->data.skb == NULL) { + IPAERR("failed to alloc skb\n"); + goto fail_skb_alloc; + } + ptr = skb_put(rx_pkt->data.skb, IPA_WLAN_RX_BUFF_SZ); + rx_pkt->data.dma_addr = dma_map_single(ipa3_ctx->pdev, ptr, + IPA_WLAN_RX_BUFF_SZ, DMA_FROM_DEVICE); + if (dma_mapping_error(ipa3_ctx->pdev, rx_pkt->data.dma_addr)) { + IPAERR("dma_map_single failure %pK for %pK\n", + (void *)rx_pkt->data.dma_addr, ptr); + goto fail_dma_mapping; + } + + spin_lock_bh(&ipa3_ctx->wc_memb.wlan_spinlock); + list_add_tail(&rx_pkt->link, + &ipa3_ctx->wc_memb.wlan_comm_desc_list); + rx_len_cached = ++ipa3_ctx->wc_memb.wlan_comm_total_cnt; + + ipa3_ctx->wc_memb.wlan_comm_free_cnt++; + spin_unlock_bh(&ipa3_ctx->wc_memb.wlan_spinlock); + + } + + return; + +fail_dma_mapping: + dev_kfree_skb_any(rx_pkt->data.skb); +fail_skb_alloc: + kmem_cache_free(ipa3_ctx->rx_pkt_wrapper_cache, rx_pkt); +fail_kmem_cache_alloc: + return; +} + +/** + * ipa3_first_replenish_rx_cache() - Replenish the Rx packets cache for the first time. + * + * The function allocates buffers in the rx_pkt_wrapper_cache cache until there + * are IPA_RX_POOL_CEIL buffers in the cache. + * - Allocate a buffer in the cache + * - Initialized the packets link + * - Initialize the packets work struct + * - Allocate the packets socket buffer (skb) + * - Fill the packets skb with data + * - Make the packet DMAable + * - Add the packet to the system pipe linked list + */ +static void ipa3_first_replenish_rx_cache(struct ipa3_sys_context *sys) +{ + void *ptr; + struct ipa3_rx_pkt_wrapper *rx_pkt; + int ret; + int idx = 0; + int rx_len_cached = 0; + struct gsi_xfer_elem gsi_xfer_elem_array[IPA_REPL_XFER_MAX]; + gfp_t flag = GFP_NOWAIT | __GFP_NOWARN; + + rx_len_cached = sys->len; + + /* start replenish only when buffers go lower than the threshold */ + if (sys->rx_pool_sz - sys->len < IPA_REPL_XFER_THRESH) + return; + + while (rx_len_cached < sys->rx_pool_sz) { + rx_pkt = kmem_cache_zalloc(ipa3_ctx->rx_pkt_wrapper_cache, + flag); + if (!rx_pkt) { + IPAERR("failed to alloc cache\n"); + goto fail_kmem_cache_alloc; + } + + INIT_WORK(&rx_pkt->work, ipa3_wq_rx_avail); + rx_pkt->sys = sys; + + rx_pkt->data.skb = sys->get_skb(sys->rx_buff_sz, flag); + if (rx_pkt->data.skb == NULL) { + IPAERR("failed to alloc skb\n"); + goto fail_skb_alloc; + } + ptr = skb_put(rx_pkt->data.skb, sys->rx_buff_sz); + rx_pkt->data.dma_addr = dma_map_single(ipa3_ctx->pdev, ptr, + sys->rx_buff_sz, + DMA_FROM_DEVICE); + if (dma_mapping_error(ipa3_ctx->pdev, rx_pkt->data.dma_addr)) { + IPAERR("dma_map_single failure %pK for %pK\n", + (void *)rx_pkt->data.dma_addr, ptr); + goto fail_dma_mapping; + } + + gsi_xfer_elem_array[idx].addr = rx_pkt->data.dma_addr; + gsi_xfer_elem_array[idx].len = sys->rx_buff_sz; + gsi_xfer_elem_array[idx].flags = GSI_XFER_FLAG_EOT; + gsi_xfer_elem_array[idx].flags |= GSI_XFER_FLAG_EOB; + gsi_xfer_elem_array[idx].flags |= GSI_XFER_FLAG_BEI; + gsi_xfer_elem_array[idx].type = GSI_XFER_ELEM_DATA; + gsi_xfer_elem_array[idx].xfer_user_data = rx_pkt; + idx++; + rx_len_cached++; + /* + * gsi_xfer_elem_buffer has a size of IPA_REPL_XFER_MAX. + * If this size is reached we need to queue the xfers. + */ + if (idx == IPA_REPL_XFER_MAX) { + ret = gsi_queue_xfer(sys->ep->gsi_chan_hdl, idx, + gsi_xfer_elem_array, false); + if (ret != GSI_STATUS_SUCCESS) { + /* we don't expect this will happen */ + IPAERR("failed to provide buffer: %d\n", ret); + WARN_ON(1); + break; + } + idx = 0; + } + } + goto done; + +fail_dma_mapping: + sys->free_skb(rx_pkt->data.skb); +fail_skb_alloc: + kmem_cache_free(ipa3_ctx->rx_pkt_wrapper_cache, rx_pkt); +fail_kmem_cache_alloc: + /* Ensuring minimum buffers are submitted to HW */ + if (rx_len_cached < IPA_REPL_XFER_THRESH) { + queue_delayed_work(sys->wq, &sys->replenish_rx_work, + msecs_to_jiffies(1)); + return; + } +done: + /* only ring doorbell once here */ + ret = gsi_queue_xfer(sys->ep->gsi_chan_hdl, idx, + gsi_xfer_elem_array, true); + if (ret == GSI_STATUS_SUCCESS) { + sys->len = rx_len_cached; + } else { + /* we don't expect this will happen */ + IPAERR("failed to provide buffer: %d\n", ret); + WARN_ON(1); + } +} + +/** + * ipa3_replenish_rx_cache() - Replenish the Rx packets cache. + * + * The function allocates buffers in the rx_pkt_wrapper_cache cache until there + * are IPA_RX_POOL_CEIL buffers in the cache. + * - Allocate a buffer in the cache + * - Initialized the packets link + * - Initialize the packets work struct + * - Allocate the packets socket buffer (skb) + * - Fill the packets skb with data + * - Make the packet DMAable + * - Add the packet to the system pipe linked list + */ +static void ipa3_replenish_rx_cache(struct ipa3_sys_context *sys) +{ + void *ptr; + struct ipa3_rx_pkt_wrapper *rx_pkt; + int ret; + int idx = 0; + int rx_len_cached = 0; + struct gsi_xfer_elem gsi_xfer_elem_array[IPA_REPL_XFER_MAX]; + gfp_t flag = GFP_NOWAIT | __GFP_NOWARN; + + rx_len_cached = sys->len; + + /* start replenish only when buffers go lower than the threshold */ + if (sys->rx_pool_sz - sys->len < IPA_REPL_XFER_THRESH) + return; + + + while (rx_len_cached < sys->rx_pool_sz) { + rx_pkt = kmem_cache_zalloc(ipa3_ctx->rx_pkt_wrapper_cache, + flag); + if (!rx_pkt) + goto fail_kmem_cache_alloc; + + INIT_WORK(&rx_pkt->work, ipa3_wq_rx_avail); + rx_pkt->sys = sys; + + rx_pkt->data.skb = sys->get_skb(sys->rx_buff_sz, flag); + if (rx_pkt->data.skb == NULL) { + IPAERR("failed to alloc skb\n"); + goto fail_skb_alloc; + } + ptr = skb_put(rx_pkt->data.skb, sys->rx_buff_sz); + rx_pkt->data.dma_addr = dma_map_single(ipa3_ctx->pdev, ptr, + sys->rx_buff_sz, + DMA_FROM_DEVICE); + if (dma_mapping_error(ipa3_ctx->pdev, rx_pkt->data.dma_addr)) { + IPAERR("dma_map_single failure %pK for %pK\n", + (void *)rx_pkt->data.dma_addr, ptr); + goto fail_dma_mapping; + } + + gsi_xfer_elem_array[idx].addr = rx_pkt->data.dma_addr; + gsi_xfer_elem_array[idx].len = sys->rx_buff_sz; + gsi_xfer_elem_array[idx].flags = GSI_XFER_FLAG_EOT; + gsi_xfer_elem_array[idx].flags |= GSI_XFER_FLAG_EOB; + gsi_xfer_elem_array[idx].flags |= GSI_XFER_FLAG_BEI; + gsi_xfer_elem_array[idx].type = GSI_XFER_ELEM_DATA; + gsi_xfer_elem_array[idx].xfer_user_data = rx_pkt; + idx++; + rx_len_cached++; + /* + * gsi_xfer_elem_buffer has a size of IPA_REPL_XFER_MAX. + * If this size is reached we need to queue the xfers. + */ + if (idx == IPA_REPL_XFER_MAX) { + ret = gsi_queue_xfer(sys->ep->gsi_chan_hdl, idx, + gsi_xfer_elem_array, false); + if (ret != GSI_STATUS_SUCCESS) { + /* we don't expect this will happen */ + IPAERR("failed to provide buffer: %d\n", ret); + WARN_ON(1); + break; + } + idx = 0; + } + } + goto done; + +fail_dma_mapping: + sys->free_skb(rx_pkt->data.skb); +fail_skb_alloc: + kmem_cache_free(ipa3_ctx->rx_pkt_wrapper_cache, rx_pkt); +fail_kmem_cache_alloc: + if (rx_len_cached == 0) { + queue_delayed_work(sys->wq, &sys->replenish_rx_work, + msecs_to_jiffies(1)); + return; + } +done: + /* only ring doorbell once here */ + ret = gsi_queue_xfer(sys->ep->gsi_chan_hdl, idx, + gsi_xfer_elem_array, true); + if (ret == GSI_STATUS_SUCCESS) { + sys->len = rx_len_cached; + } else { + /* we don't expect this will happen */ + IPAERR("failed to provide buffer: %d\n", ret); + WARN_ON(1); + } +} + +static void ipa3_replenish_rx_cache_recycle(struct ipa3_sys_context *sys) +{ + void *ptr; + struct ipa3_rx_pkt_wrapper *rx_pkt; + int ret; + int idx = 0; + int rx_len_cached = 0; + struct gsi_xfer_elem gsi_xfer_elem_array[IPA_REPL_XFER_MAX]; + gfp_t flag = GFP_NOWAIT | __GFP_NOWARN; + u32 stats_i = + (sys->ep->client == IPA_CLIENT_APPS_LAN_COAL_CONS) ? 0 : + (sys->ep->client == IPA_CLIENT_APPS_LAN_CONS) ? 1 : 2; + + /* start replenish only when buffers go lower than the threshold */ + if (sys->rx_pool_sz - sys->len < IPA_REPL_XFER_THRESH) + return; + + rx_len_cached = sys->len; + + while (rx_len_cached < sys->rx_pool_sz) { + if (list_empty(&sys->rcycl_list)) { + rx_pkt = kmem_cache_zalloc( + ipa3_ctx->rx_pkt_wrapper_cache, flag); + if (!rx_pkt) + goto fail_kmem_cache_alloc; + + INIT_WORK(&rx_pkt->work, ipa3_wq_rx_avail); + rx_pkt->sys = sys; + + rx_pkt->data.skb = sys->get_skb(sys->rx_buff_sz, flag); + if (rx_pkt->data.skb == NULL) { + IPAERR("failed to alloc skb\n"); + kmem_cache_free(ipa3_ctx->rx_pkt_wrapper_cache, + rx_pkt); + goto fail_kmem_cache_alloc; + } + ipa3_ctx->stats.cache_recycle_stats[stats_i].pkt_allocd++; + } else { + spin_lock_bh(&sys->spinlock); + rx_pkt = list_first_entry( + &sys->rcycl_list, + struct ipa3_rx_pkt_wrapper, link); + list_del_init(&rx_pkt->link); + spin_unlock_bh(&sys->spinlock); + ipa3_ctx->stats.cache_recycle_stats[stats_i].pkt_found++; + } + + ptr = skb_put(rx_pkt->data.skb, sys->rx_buff_sz); + + rx_pkt->data.dma_addr = dma_map_single( + ipa3_ctx->pdev, ptr, sys->rx_buff_sz, DMA_FROM_DEVICE); + + if (dma_mapping_error( ipa3_ctx->pdev, rx_pkt->data.dma_addr)) { + IPAERR("dma_map_single failure %pK for %pK\n", + (void *)rx_pkt->data.dma_addr, ptr); + goto fail_dma_mapping; + } + + gsi_xfer_elem_array[idx].addr = rx_pkt->data.dma_addr; + gsi_xfer_elem_array[idx].len = sys->rx_buff_sz; + gsi_xfer_elem_array[idx].flags = GSI_XFER_FLAG_EOT; + gsi_xfer_elem_array[idx].flags |= GSI_XFER_FLAG_EOB; + gsi_xfer_elem_array[idx].flags |= GSI_XFER_FLAG_BEI; + gsi_xfer_elem_array[idx].type = GSI_XFER_ELEM_DATA; + gsi_xfer_elem_array[idx].xfer_user_data = rx_pkt; + idx++; + rx_len_cached++; + ipa3_ctx->stats.cache_recycle_stats[stats_i].tot_pkt_replenished++; + /* + * gsi_xfer_elem_buffer has a size of IPA_REPL_XFER_MAX. + * If this size is reached we need to queue the xfers. + */ + if (idx == IPA_REPL_XFER_MAX) { + ret = gsi_queue_xfer(sys->ep->gsi_chan_hdl, idx, + gsi_xfer_elem_array, false); + if (ret != GSI_STATUS_SUCCESS) { + /* we don't expect this will happen */ + IPAERR("failed to provide buffer: %d\n", ret); + WARN_ON(1); + break; + } + idx = 0; + } + } + goto done; +fail_dma_mapping: + spin_lock_bh(&sys->spinlock); + ipa3_skb_recycle(rx_pkt->data.skb); + list_add_tail(&rx_pkt->link, &sys->rcycl_list); + spin_unlock_bh(&sys->spinlock); +fail_kmem_cache_alloc: + if (rx_len_cached == 0) { + queue_delayed_work(sys->wq, &sys->replenish_rx_work, + msecs_to_jiffies(1)); + return; + } + +done: + /* only ring doorbell once here */ + ret = gsi_queue_xfer(sys->ep->gsi_chan_hdl, idx, + gsi_xfer_elem_array, true); + if (ret == GSI_STATUS_SUCCESS) { + sys->len = rx_len_cached; + } else { + /* we don't expect this will happen */ + IPAERR("failed to provide buffer: %d\n", ret); + WARN_ON(1); + } +} + +static void ipa3_fast_replenish_rx_cache(struct ipa3_sys_context *sys) +{ + struct ipa3_rx_pkt_wrapper *rx_pkt; + int ret; + int rx_len_cached = 0; + struct gsi_xfer_elem gsi_xfer_elem_array[IPA_REPL_XFER_MAX]; + u32 curr; + int idx = 0; + + /* start replenish only when buffers go lower than the threshold */ + if (sys->rx_pool_sz - sys->len < IPA_REPL_XFER_THRESH) + return; + + spin_lock_bh(&sys->spinlock); + rx_len_cached = sys->len; + curr = atomic_read(&sys->repl->head_idx); + + while (rx_len_cached < sys->rx_pool_sz) { + if (curr == atomic_read(&sys->repl->tail_idx)) + break; + rx_pkt = sys->repl->cache[curr]; + gsi_xfer_elem_array[idx].addr = rx_pkt->data.dma_addr; + gsi_xfer_elem_array[idx].len = sys->rx_buff_sz; + gsi_xfer_elem_array[idx].flags = GSI_XFER_FLAG_EOT; + gsi_xfer_elem_array[idx].flags |= GSI_XFER_FLAG_EOB; + gsi_xfer_elem_array[idx].flags |= GSI_XFER_FLAG_BEI; + gsi_xfer_elem_array[idx].type = GSI_XFER_ELEM_DATA; + gsi_xfer_elem_array[idx].xfer_user_data = rx_pkt; + rx_len_cached++; + curr = (++curr == sys->repl->capacity) ? 0 : curr; + idx++; + /* + * gsi_xfer_elem_buffer has a size of IPA_REPL_XFER_THRESH. + * If this size is reached we need to queue the xfers. + */ + if (idx == IPA_REPL_XFER_MAX) { + ret = gsi_queue_xfer(sys->ep->gsi_chan_hdl, idx, + gsi_xfer_elem_array, false); + if (ret != GSI_STATUS_SUCCESS) { + /* we don't expect this will happen */ + IPAERR("failed to provide buffer: %d\n", ret); + WARN_ON(1); + break; + } + idx = 0; + } + } + /* only ring doorbell once here */ + ret = gsi_queue_xfer(sys->ep->gsi_chan_hdl, idx, + gsi_xfer_elem_array, true); + if (ret == GSI_STATUS_SUCCESS) { + /* ensure write is done before setting head index */ + mb(); + atomic_set(&sys->repl->head_idx, curr); + sys->len = rx_len_cached; + } else { + /* we don't expect this will happen */ + IPAERR("failed to provide buffer: %d\n", ret); + WARN_ON(1); + } + + spin_unlock_bh(&sys->spinlock); + + __trigger_repl_work(sys); + + if (rx_len_cached <= IPA_DEFAULT_SYS_YELLOW_WM) { + if (IPA_CLIENT_IS_WAN_CONS(sys->ep->client)) + IPA_STATS_INC_CNT(ipa3_ctx->stats.wan_rx_empty); + else if (IPA_CLIENT_IS_LAN_CONS(sys->ep->client)) + IPA_STATS_INC_CNT(ipa3_ctx->stats.lan_rx_empty); + else if (sys->ep->client == IPA_CLIENT_APPS_WAN_LOW_LAT_CONS) + IPA_STATS_INC_CNT(ipa3_ctx->stats.low_lat_rx_empty); + else if (sys->ep->client == IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_CONS) + IPA_STATS_INC_CNT(ipa3_ctx->stats.rmnet_ll_rx_empty); + else + WARN_ON_RATELIMIT_IPA(1); + queue_delayed_work(sys->wq, &sys->replenish_rx_work, + msecs_to_jiffies(1)); + } +} + +static void ipa3_replenish_rx_work_func(struct work_struct *work) +{ + struct delayed_work *dwork; + struct ipa3_sys_context *sys; + + dwork = container_of(work, struct delayed_work, work); + sys = container_of(dwork, struct ipa3_sys_context, replenish_rx_work); + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + sys->repl_hdlr(sys); + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); +} + +/** + * free_rx_pkt() - function to free the skb and rx_pkt_wrapper + * + * @chan_user_data: ipa_sys_context used for skb size and skb_free func + * @xfer_uder_data: rx_pkt wrapper to be freed + * + */ +static void free_rx_pkt(void *chan_user_data, void *xfer_user_data) +{ + + struct ipa3_rx_pkt_wrapper *rx_pkt = (struct ipa3_rx_pkt_wrapper *) + xfer_user_data; + struct ipa3_sys_context *sys = (struct ipa3_sys_context *) + chan_user_data; + + dma_unmap_single(ipa3_ctx->pdev, rx_pkt->data.dma_addr, + sys->rx_buff_sz, DMA_FROM_DEVICE); + sys->free_skb(rx_pkt->data.skb); + kmem_cache_free(ipa3_ctx->rx_pkt_wrapper_cache, rx_pkt); +} + +/** + * free_rx_page() - function to free the page and rx_pkt_wrapper + * + * @chan_user_data: ipa_sys_context used for skb size and skb_free func + * @xfer_uder_data: rx_pkt wrapper to be freed + * + */ +static void free_rx_page(void *chan_user_data, void *xfer_user_data) +{ + struct ipa3_rx_pkt_wrapper *rx_pkt = (struct ipa3_rx_pkt_wrapper *) + xfer_user_data; + + if (!rx_pkt->page_data.is_tmp_alloc) { + list_del_init(&rx_pkt->link); + page_ref_dec(rx_pkt->page_data.page); + spin_lock_bh(&rx_pkt->sys->common_sys->spinlock); + /* Add the element to head. */ + list_add(&rx_pkt->link, + &rx_pkt->sys->page_recycle_repl->page_repl_head); + spin_unlock_bh(&rx_pkt->sys->common_sys->spinlock); + } else { + dma_unmap_page(ipa3_ctx->pdev, rx_pkt->page_data.dma_addr, + rx_pkt->len, DMA_FROM_DEVICE); + __free_pages(rx_pkt->page_data.page, rx_pkt->page_data.page_order); + kmem_cache_free(ipa3_ctx->rx_pkt_wrapper_cache, rx_pkt); + } +} + +/** + * ipa3_cleanup_rx() - release RX queue resources + * + */ +static void ipa3_cleanup_rx(struct ipa3_sys_context *sys) +{ + struct ipa3_rx_pkt_wrapper *rx_pkt; + struct ipa3_rx_pkt_wrapper *r; + u32 head; + u32 tail; + + /* + * buffers not consumed by gsi are cleaned up using cleanup callback + * provided to gsi + */ + + spin_lock_bh(&sys->spinlock); + list_for_each_entry_safe(rx_pkt, r, + &sys->rcycl_list, link) { + list_del(&rx_pkt->link); + if (rx_pkt->data.dma_addr) + dma_unmap_single(ipa3_ctx->pdev, rx_pkt->data.dma_addr, + sys->rx_buff_sz, DMA_FROM_DEVICE); + else + IPADBG("DMA address already freed\n"); + sys->free_skb(rx_pkt->data.skb); + kmem_cache_free(ipa3_ctx->rx_pkt_wrapper_cache, rx_pkt); + } + spin_unlock_bh(&sys->spinlock); + + if (sys->repl) { + head = atomic_read(&sys->repl->head_idx); + tail = atomic_read(&sys->repl->tail_idx); + while (head != tail) { + rx_pkt = sys->repl->cache[head]; + if (sys->repl_hdlr != ipa3_replenish_rx_page_recycle) { + dma_unmap_single(ipa3_ctx->pdev, + rx_pkt->data.dma_addr, + sys->rx_buff_sz, + DMA_FROM_DEVICE); + sys->free_skb(rx_pkt->data.skb); + } else { + dma_unmap_page(ipa3_ctx->pdev, + rx_pkt->page_data.dma_addr, + rx_pkt->len, + DMA_FROM_DEVICE); + __free_pages(rx_pkt->page_data.page, rx_pkt->page_data.page_order); + } + kmem_cache_free(ipa3_ctx->rx_pkt_wrapper_cache, + rx_pkt); + head = (head + 1) % sys->repl->capacity; + } + + kfree(sys->repl->cache); + kfree(sys->repl); + sys->repl = NULL; + } +} + +static struct sk_buff *ipa3_skb_copy_for_client(struct sk_buff *skb, int len) +{ + struct sk_buff *skb2 = NULL; + + if (!ipa3_ctx->lan_rx_napi_enable) + skb2 = __dev_alloc_skb(len + IPA_RX_BUFF_CLIENT_HEADROOM, + GFP_KERNEL); + else + skb2 = __dev_alloc_skb(len + IPA_RX_BUFF_CLIENT_HEADROOM, + GFP_ATOMIC); + + if (likely(skb2)) { + /* Set the data pointer */ + skb_reserve(skb2, IPA_RX_BUFF_CLIENT_HEADROOM); + memcpy(skb2->data, skb->data, len); + skb2->len = len; + skb_set_tail_pointer(skb2, len); + } + + return skb2; +} + +static int ipa3_lan_rx_pyld_hdlr(struct sk_buff *skb, + struct ipa3_sys_context *sys) +{ + struct ipahal_pkt_status status; + u32 pkt_status_sz; + struct sk_buff *skb2; + int pad_len_byte = 0; + int len; + unsigned char *buf; + int src_pipe; + unsigned int used = *(unsigned int *)skb->cb; + unsigned int used_align = ALIGN(used, 32); + unsigned long unused = IPA_GENERIC_RX_BUFF_BASE_SZ - used; + struct ipa3_tx_pkt_wrapper *tx_pkt = NULL; + unsigned long ptr; + + IPA_DUMP_BUFF(skb->data, 0, skb->len); + + if (skb->len == 0) { + IPAERR("ZLT packet arrived to AP\n"); + goto out; + } + + if (sys->len_partial) { + IPADBG_LOW("len_partial %d\n", sys->len_partial); + buf = skb_push(skb, sys->len_partial); + memcpy(buf, sys->prev_skb->data, sys->len_partial); + sys->len_partial = 0; + sys->free_skb(sys->prev_skb); + sys->prev_skb = NULL; + goto begin; + } + + /* this pipe has TX comp (status only) + mux-ed LAN RX data + * (status+data) + */ + if (sys->len_rem) { + IPADBG_LOW("rem %d skb %d pad %d\n", sys->len_rem, skb->len, + sys->len_pad); + if (sys->len_rem <= skb->len) { + if (sys->prev_skb) { + if (!ipa3_ctx->lan_rx_napi_enable) + skb2 = skb_copy_expand(sys->prev_skb, + 0, sys->len_rem, GFP_KERNEL); + else + skb2 = skb_copy_expand(sys->prev_skb, + 0, sys->len_rem, GFP_ATOMIC); + if (likely(skb2)) { + memcpy(skb_put(skb2, sys->len_rem), + skb->data, sys->len_rem); + skb_trim(skb2, + skb2->len - sys->len_pad); + skb2->truesize = skb2->len + + sizeof(struct sk_buff); + if (sys->drop_packet) + dev_kfree_skb_any(skb2); + else + sys->ep->client_notify( + sys->ep->priv, + IPA_RECEIVE, + (unsigned long)(skb2)); + } else { + IPAERR("copy expand failed\n"); + } + dev_kfree_skb_any(sys->prev_skb); + } + skb_pull(skb, sys->len_rem); + sys->prev_skb = NULL; + sys->len_rem = 0; + sys->len_pad = 0; + } else { + if (sys->prev_skb) { + if (!ipa3_ctx->lan_rx_napi_enable) + skb2 = skb_copy_expand(sys->prev_skb, 0, + skb->len, GFP_KERNEL); + else + skb2 = skb_copy_expand(sys->prev_skb, 0, + skb->len, GFP_ATOMIC); + if (likely(skb2)) { + memcpy(skb_put(skb2, skb->len), + skb->data, skb->len); + } else { + IPAERR("copy expand failed\n"); + } + dev_kfree_skb_any(sys->prev_skb); + sys->prev_skb = skb2; + } + sys->len_rem -= skb->len; + goto out; + } + } + +begin: + pkt_status_sz = ipahal_pkt_status_get_size(); + while (skb->len) { + sys->drop_packet = false; + IPADBG_LOW("LEN_REM %d\n", skb->len); + + if (skb->len < pkt_status_sz) { + WARN_ON(sys->prev_skb != NULL); + IPADBG_LOW("status straddles buffer\n"); + if (!ipa3_ctx->lan_rx_napi_enable) + sys->prev_skb = skb_copy(skb, GFP_KERNEL); + else + sys->prev_skb = skb_copy(skb, GFP_ATOMIC); + sys->len_partial = skb->len; + goto out; + } + + ipahal_pkt_status_parse(skb->data, &status); + IPADBG_LOW("STATUS opcode=%d src=%d dst=%d len=%d\n", + status.status_opcode, status.endp_src_idx, + status.endp_dest_idx, status.pkt_len); + if (sys->status_stat) { + sys->status_stat->status[sys->status_stat->curr] = + status; + sys->status_stat->curr++; + if (sys->status_stat->curr == IPA_MAX_STATUS_STAT_NUM) + sys->status_stat->curr = 0; + } + + switch (status.status_opcode) { + case IPAHAL_PKT_STATUS_OPCODE_DROPPED_PACKET: + case IPAHAL_PKT_STATUS_OPCODE_PACKET: + case IPAHAL_PKT_STATUS_OPCODE_SUSPENDED_PACKET: + case IPAHAL_PKT_STATUS_OPCODE_PACKET_2ND_PASS: + break; + case IPAHAL_PKT_STATUS_OPCODE_NEW_FRAG_RULE: + IPAERR_RL("Frag packets received on lan consumer\n"); + IPAERR_RL("STATUS opcode=%d src=%d dst=%d src ip=%x\n", + status.status_opcode, status.endp_src_idx, + status.endp_dest_idx, status.src_ip_addr); + skb_pull(skb, pkt_status_sz); + continue; + default: + IPAERR_RL("unsupported opcode(%d)\n", + status.status_opcode); + skb_pull(skb, pkt_status_sz); + continue; + } + + IPA_STATS_EXCP_CNT(status.exception, + ipa3_ctx->stats.rx_excp_pkts); + if (status.endp_dest_idx >= ipa3_ctx->ipa_num_pipes || + status.endp_src_idx >= ipa3_ctx->ipa_num_pipes) { + IPAERR_RL("status fields invalid\n"); + IPAERR_RL("STATUS opcode=%d src=%d dst=%d len=%d\n", + status.status_opcode, status.endp_src_idx, + status.endp_dest_idx, status.pkt_len); + WARN_ON(1); + /* HW gave an unexpected status */ + ipa_assert(); + } + if (IPAHAL_PKT_STATUS_MASK_FLAG_VAL( + IPAHAL_PKT_STATUS_MASK_TAG_VALID_SHFT, &status)) { + struct ipa3_tag_completion *comp; + + IPADBG_LOW("TAG packet arrived\n"); + if (status.tag_info == IPA_COOKIE) { + skb_pull(skb, pkt_status_sz); + if (skb->len < sizeof(comp)) { + IPAERR("TAG arrived without packet\n"); + goto out; + } + memcpy(&comp, skb->data, sizeof(comp)); + skb_pull(skb, sizeof(comp)); + complete(&comp->comp); + if (atomic_dec_return(&comp->cnt) == 0) + kfree(comp); + continue; + } else { + ptr = tag_to_pointer_wa(status.tag_info); + tx_pkt = (struct ipa3_tx_pkt_wrapper *)ptr; + IPADBG_LOW("tx_pkt recv = %pK\n", tx_pkt); + } + } + if (status.pkt_len == 0) { + IPADBG_LOW("Skip aggr close status\n"); + skb_pull(skb, pkt_status_sz); + IPA_STATS_INC_CNT(ipa3_ctx->stats.aggr_close); + IPA_STATS_DEC_CNT(ipa3_ctx->stats.rx_excp_pkts + [IPAHAL_PKT_STATUS_EXCEPTION_NONE]); + continue; + } + + if (status.endp_dest_idx == (sys->ep - ipa3_ctx->ep)) { + /* RX data */ + src_pipe = status.endp_src_idx; + + /* + * A packet which is received back to the AP after + * there was no route match. + */ + if (status.exception == + IPAHAL_PKT_STATUS_EXCEPTION_NONE && + ipahal_is_rule_miss_id(status.rt_rule_id)) + sys->drop_packet = true; + + if (skb->len == pkt_status_sz && + status.exception == + IPAHAL_PKT_STATUS_EXCEPTION_NONE) { + WARN_ON(sys->prev_skb != NULL); + IPADBG_LOW("Ins header in next buffer\n"); + if (!ipa3_ctx->lan_rx_napi_enable) + sys->prev_skb = skb_copy(skb, + GFP_KERNEL); + else + sys->prev_skb = skb_copy(skb, + GFP_ATOMIC); + sys->len_partial = skb->len; + goto out; + } + + /* + * Padding not needed for LAN coalescing pipe, hence we + * only pad when not LAN coalescing pipe. + */ + if (sys->ep->client != IPA_CLIENT_APPS_LAN_COAL_CONS) + pad_len_byte = ((status.pkt_len + 3) & ~3) - + status.pkt_len; + len = status.pkt_len + pad_len_byte; + IPADBG_LOW("pad %d pkt_len %d len %d\n", pad_len_byte, + status.pkt_len, len); + + if (status.exception == + IPAHAL_PKT_STATUS_EXCEPTION_DEAGGR) { + IPADBG_LOW( + "Dropping packet on DeAggr Exception\n"); + sys->drop_packet = true; + } + + skb2 = ipa3_skb_copy_for_client(skb, + min(status.pkt_len + pkt_status_sz, skb->len)); + if (likely(skb2)) { + if (skb->len < len + pkt_status_sz) { + IPADBG_LOW("SPL skb len %d len %d\n", + skb->len, len); + sys->prev_skb = skb2; + sys->len_rem = len - skb->len + + pkt_status_sz; + sys->len_pad = pad_len_byte; + skb_pull(skb, skb->len); + } else { + skb_trim(skb2, status.pkt_len + + pkt_status_sz); + IPADBG_LOW("rx avail for %d\n", + status.endp_dest_idx); + if (sys->drop_packet) { + dev_kfree_skb_any(skb2); + } else if (status.pkt_len > + IPA_GENERIC_AGGR_BYTE_LIMIT * + 1024) { + IPAERR("packet size invalid\n"); + IPAERR("STATUS opcode=%d\n", + status.status_opcode); + IPAERR("src=%d dst=%d len=%d\n", + status.endp_src_idx, + status.endp_dest_idx, + status.pkt_len); + sys->drop_packet = true; + dev_kfree_skb_any(skb2); + } else { + skb2->truesize = skb2->len + + sizeof(struct sk_buff) + + (ALIGN(len + + pkt_status_sz, 32) * + unused / used_align); + sys->ep->client_notify( + sys->ep->priv, + IPA_RECEIVE, + (unsigned long)(skb2)); + } + skb_pull(skb, len + pkt_status_sz); + } + } else { + IPAERR("fail to alloc skb\n"); + if (skb->len < len) { + sys->prev_skb = NULL; + sys->len_rem = len - skb->len + + pkt_status_sz; + sys->len_pad = pad_len_byte; + skb_pull(skb, skb->len); + } else { + skb_pull(skb, len + pkt_status_sz); + } + } + /* TX comp */ + ipa3_wq_write_done_status(src_pipe, tx_pkt); + IPADBG_LOW("tx comp imp for %d\n", src_pipe); + } else { + /* TX comp */ + ipa3_wq_write_done_status(status.endp_src_idx, tx_pkt); + IPADBG_LOW("tx comp exp for %d\n", + status.endp_src_idx); + skb_pull(skb, pkt_status_sz); + IPA_STATS_INC_CNT(ipa3_ctx->stats.stat_compl); + IPA_STATS_DEC_CNT(ipa3_ctx->stats.rx_excp_pkts + [IPAHAL_PKT_STATUS_EXCEPTION_NONE]); + } + tx_pkt = NULL; + } + +out: + ipa3_skb_recycle(skb); + return 0; +} + +static struct sk_buff *ipa3_join_prev_skb(struct sk_buff *prev_skb, + struct sk_buff *skb, unsigned int len) +{ + struct sk_buff *skb2; + + skb2 = skb_copy_expand(prev_skb, 0, + len, GFP_KERNEL); + if (likely(skb2)) { + memcpy(skb_put(skb2, len), + skb->data, len); + } else { + IPAERR("copy expand failed\n"); + skb2 = NULL; + } + dev_kfree_skb_any(prev_skb); + + return skb2; +} + +static void ipa3_wan_rx_handle_splt_pyld(struct sk_buff *skb, + struct ipa3_sys_context *sys) +{ + struct sk_buff *skb2; + + IPADBG_LOW("rem %d skb %d\n", sys->len_rem, skb->len); + if (sys->len_rem <= skb->len) { + if (sys->prev_skb) { + skb2 = ipa3_join_prev_skb(sys->prev_skb, skb, + sys->len_rem); + if (likely(skb2)) { + IPADBG_LOW( + "removing Status element from skb and sending to WAN client"); + skb_pull(skb2, ipahal_pkt_status_get_size()); + skb2->truesize = skb2->len + + sizeof(struct sk_buff); + sys->ep->client_notify(sys->ep->priv, + IPA_RECEIVE, + (unsigned long)(skb2)); + } + } + skb_pull(skb, sys->len_rem); + sys->prev_skb = NULL; + sys->len_rem = 0; + } else { + if (sys->prev_skb) { + skb2 = ipa3_join_prev_skb(sys->prev_skb, skb, + skb->len); + sys->prev_skb = skb2; + } + sys->len_rem -= skb->len; + skb_pull(skb, skb->len); + } +} + +static int ipa3_low_lat_rx_pyld_hdlr(struct sk_buff *skb, + struct ipa3_sys_context *sys) +{ + if (skb->len == 0) { + IPAERR("ZLT\n"); + goto bail; + } + + IPA_DUMP_BUFF(skb->data, 0, skb->len); + if (!sys->ep->client_notify) { + IPAERR("client_notify is NULL"); + goto bail; + } + sys->ep->client_notify(sys->ep->priv, + IPA_RECEIVE, (unsigned long)(skb)); + return 0; + +bail: + sys->free_skb(skb); + return 0; +} + +static int ipa3_wan_rx_pyld_hdlr(struct sk_buff *skb, + struct ipa3_sys_context *sys) +{ + struct ipahal_pkt_status status; + unsigned char *skb_data; + u32 pkt_status_sz; + struct sk_buff *skb2; + u16 pkt_len_with_pad; + u32 qmap_hdr; + int checksum_trailer_exists; + int frame_len; + int ep_idx; + unsigned int used = *(unsigned int *)skb->cb; + unsigned int used_align = ALIGN(used, 32); + unsigned long unused = IPA_GENERIC_RX_BUFF_BASE_SZ - used; + + IPA_DUMP_BUFF(skb->data, 0, skb->len); + if (skb->len == 0) { + IPAERR("ZLT\n"); + goto bail; + } + + if (ipa3_ctx->ipa_client_apps_wan_cons_agg_gro) { + sys->ep->client_notify(sys->ep->priv, + IPA_RECEIVE, (unsigned long)(skb)); + return 0; + } + if (sys->repl_hdlr == ipa3_replenish_rx_cache_recycle) { + IPAERR("Recycle should enable only with GRO Aggr\n"); + ipa_assert(); + } + + /* + * payload splits across 2 buff or more, + * take the start of the payload from prev_skb + */ + if (sys->len_rem) + ipa3_wan_rx_handle_splt_pyld(skb, sys); + + pkt_status_sz = ipahal_pkt_status_get_size(); + while (skb->len) { + IPADBG_LOW("LEN_REM %d\n", skb->len); + if (skb->len < pkt_status_sz) { + IPAERR("status straddles buffer\n"); + WARN_ON(1); + goto bail; + } + ipahal_pkt_status_parse(skb->data, &status); + skb_data = skb->data; + IPADBG_LOW("STATUS opcode=%d src=%d dst=%d len=%d ttl_dec=%d\n", + status.status_opcode, status.endp_src_idx, status.endp_dest_idx, + status.pkt_len, status.ttl_dec); + + if (sys->status_stat) { + sys->status_stat->status[sys->status_stat->curr] = + status; + sys->status_stat->curr++; + if (sys->status_stat->curr == IPA_MAX_STATUS_STAT_NUM) + sys->status_stat->curr = 0; + } + + if ((status.status_opcode != + IPAHAL_PKT_STATUS_OPCODE_DROPPED_PACKET) && + (status.status_opcode != + IPAHAL_PKT_STATUS_OPCODE_PACKET) && + (status.status_opcode != + IPAHAL_PKT_STATUS_OPCODE_PACKET_2ND_PASS)) { + IPAERR("unsupported opcode(%d)\n", + status.status_opcode); + skb_pull(skb, pkt_status_sz); + continue; + } + + IPA_STATS_INC_CNT(ipa3_ctx->stats.rx_pkts); + if (status.ttl_dec) + IPA_STATS_INC_CNT(ipa3_ctx->stats.ttl_cnt); + if (status.endp_dest_idx >= ipa3_ctx->ipa_num_pipes || + status.endp_src_idx >= ipa3_ctx->ipa_num_pipes) { + IPAERR("status fields invalid\n"); + WARN_ON(1); + goto bail; + } + if (status.pkt_len == 0) { + IPADBG_LOW("Skip aggr close status\n"); + skb_pull(skb, pkt_status_sz); + IPA_STATS_DEC_CNT(ipa3_ctx->stats.rx_pkts); + IPA_STATS_INC_CNT(ipa3_ctx->stats.wan_aggr_close); + continue; + } + ep_idx = ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_CONS); + if (status.endp_dest_idx != ep_idx) { + IPAERR("expected endp_dest_idx %d received %d\n", + ep_idx, status.endp_dest_idx); + WARN_ON(1); + goto bail; + } + /* RX data */ + if (skb->len == pkt_status_sz) { + IPAERR("Ins header in next buffer\n"); + WARN_ON(1); + goto bail; + } + qmap_hdr = *(u32 *)(skb_data + pkt_status_sz); + /* + * Take the pkt_len_with_pad from the last 2 bytes of the QMAP + * header + */ + + /*QMAP is BE: convert the pkt_len field from BE to LE*/ + pkt_len_with_pad = ntohs((qmap_hdr>>16) & 0xffff); + IPADBG_LOW("pkt_len with pad %d\n", pkt_len_with_pad); + /*get the CHECKSUM_PROCESS bit*/ + checksum_trailer_exists = IPAHAL_PKT_STATUS_MASK_FLAG_VAL( + IPAHAL_PKT_STATUS_MASK_CKSUM_PROCESS_SHFT, &status); + IPADBG_LOW("checksum_trailer_exists %d\n", + checksum_trailer_exists); + + frame_len = pkt_status_sz + IPA_QMAP_HEADER_LENGTH + + pkt_len_with_pad; + if (checksum_trailer_exists) + frame_len += IPA_DL_CHECKSUM_LENGTH; + IPADBG_LOW("frame_len %d\n", frame_len); + + skb2 = skb_clone(skb, GFP_KERNEL); + if (likely(skb2)) { + /* + * the len of actual data is smaller than expected + * payload split across 2 buff + */ + if (skb->len < frame_len) { + IPADBG_LOW("SPL skb len %d len %d\n", + skb->len, frame_len); + sys->prev_skb = skb2; + sys->len_rem = frame_len - skb->len; + skb_pull(skb, skb->len); + } else { + skb_trim(skb2, frame_len); + IPADBG_LOW("rx avail for %d\n", + status.endp_dest_idx); + IPADBG_LOW( + "removing Status element from skb and sending to WAN client"); + skb_pull(skb2, pkt_status_sz); + skb2->truesize = skb2->len + + sizeof(struct sk_buff) + + (ALIGN(frame_len, 32) * + unused / used_align); + sys->ep->client_notify(sys->ep->priv, + IPA_RECEIVE, (unsigned long)(skb2)); + skb_pull(skb, frame_len); + } + } else { + IPAERR("fail to clone\n"); + if (skb->len < frame_len) { + sys->prev_skb = NULL; + sys->len_rem = frame_len - skb->len; + skb_pull(skb, skb->len); + } else { + skb_pull(skb, frame_len); + } + } + } +bail: + sys->free_skb(skb); + return 0; +} + +static struct sk_buff *ipa3_get_skb_ipa_rx(unsigned int len, gfp_t flags) +{ + return __dev_alloc_skb(len, flags); +} + +static void ipa_free_skb_rx(struct sk_buff *skb) +{ + dev_kfree_skb_any(skb); +} + +void ipa3_lan_rx_cb(void *priv, enum ipa_dp_evt_type evt, unsigned long data) +{ + struct sk_buff *rx_skb = (struct sk_buff *)data; + struct ipahal_pkt_status_thin status; + struct ipa3_ep_context *ep; + unsigned int src_pipe; + u32 metadata; + u8 ucp; + void (*client_notify)(void *client_priv, enum ipa_dp_evt_type evt, + unsigned long data); + void *client_priv; + + ipahal_pkt_status_parse_thin(rx_skb->data, &status); + src_pipe = status.endp_src_idx; + metadata = status.metadata; + ucp = status.ucp; + ep = &ipa3_ctx->ep[src_pipe]; + if (unlikely(src_pipe >= ipa3_ctx->ipa_num_pipes) || + unlikely(atomic_read(&ep->disconnect_in_progress))) { + IPAERR("drop pipe=%d\n", src_pipe); + dev_kfree_skb_any(rx_skb); + return; + } + if (status.exception == IPAHAL_PKT_STATUS_EXCEPTION_NONE) { + u32 extra = ( lan_coal_enabled() ) ? 0 : IPA_LAN_RX_HEADER_LENGTH; + skb_pull(rx_skb, ipahal_pkt_status_get_size() + extra); + } + else + skb_pull(rx_skb, ipahal_pkt_status_get_size()); + + /* Metadata Info + * ------------------------------------------ + * | 3 | 2 | 1 | 0 | + * | fw_desc | vdev_id | qmap mux id | Resv | + * ------------------------------------------ + */ + *(u16 *)rx_skb->cb = ((metadata >> 16) & 0xFFFF); + *(u8 *)(rx_skb->cb + 4) = ucp; + IPADBG_LOW("meta_data: 0x%x cb: 0x%x\n", + metadata, *(u32 *)rx_skb->cb); + IPADBG_LOW("ucp: %d\n", *(u8 *)(rx_skb->cb + 4)); + + spin_lock(&ipa3_ctx->disconnect_lock); + if (likely((!atomic_read(&ep->disconnect_in_progress)) && + ep->valid && ep->client_notify)) { + client_notify = ep->client_notify; + client_priv = ep->priv; + spin_unlock(&ipa3_ctx->disconnect_lock); + client_notify(client_priv, IPA_RECEIVE, + (unsigned long)(rx_skb)); + } else { + spin_unlock(&ipa3_ctx->disconnect_lock); + dev_kfree_skb_any(rx_skb); + } + +} + +/* + * The following will help us deduce the real size of an ipv6 header + * that may or may not have extensions... + */ +static int _skip_ipv6_exthdr( + u8 *hdr_ptr, + int start, + u8 *nexthdrp, + __be16 *fragp ) +{ + u8 nexthdr = *nexthdrp; + + *fragp = 0; + + while ( ipv6_ext_hdr(nexthdr) ) { + + struct ipv6_opt_hdr *hp; + + int hdrlen; + + if (nexthdr == NEXTHDR_NONE) + return -EINVAL; + + hp = (struct ipv6_opt_hdr*) (hdr_ptr + (u32) start); + + if (nexthdr == NEXTHDR_FRAGMENT) { + + u32 off = offsetof(struct frag_hdr, frag_off); + + __be16 *fp = (__be16*) (hdr_ptr + (u32)start + off); + + *fragp = *fp; + + if (ntohs(*fragp) & ~0x7) + break; + + hdrlen = 8; + + } else if (nexthdr == NEXTHDR_AUTH) { + + hdrlen = ipv6_authlen(hp); + + } else { + + hdrlen = ipv6_optlen(hp); + } + + nexthdr = hp->nexthdr; + + start += hdrlen; + } + + *nexthdrp = nexthdr; + + return start; +} + +/* + * The following defines and structure used for calculating Ethernet + * frame type and size... + */ +#define IPA_ETH_VLAN_2TAG 0x88A8 +#define IPA_ETH_VLAN_TAG 0x8100 +#define IPA_ETH_TAG_SZ sizeof(u32) + +/* + * The following structure used for containing packet payload + * information. + */ +typedef struct ipa_pkt_data_s { + void* pkt; + u32 pkt_len; +} ipa_pkt_data_t; + +/* + * The following structure used for consolidating all header + * information. + */ +typedef struct ipa_header_data_s { + struct ethhdr* eth_hdr; + u32 eth_hdr_size; + u8 ip_vers; + void* ip_hdr; + u32 ip_hdr_size; + u8 ip_proto; + void* proto_hdr; + u32 proto_hdr_size; + u32 aggr_hdr_len; + u32 curr_seq; +} ipa_header_data_t; + +static int +_calc_partial_csum( + struct sk_buff* skb, + ipa_header_data_t* hdr_data, + u32 aggr_payload_size ) +{ + u32 ip_hdr_size; + u32 proto_hdr_size; + u8 ip_vers; + u8 ip_proto; + u8* new_ip_hdr; + u8* new_proto_hdr; + u32 len_for_calc; + __sum16 pseudo; + + if ( !skb || !hdr_data ) { + + IPAERR( + "NULL args: skb(%p) and/or hdr_data(%p)\n", + skb, hdr_data); + + return -1; + + } else { + + ip_hdr_size = hdr_data->ip_hdr_size; + proto_hdr_size = hdr_data->proto_hdr_size; + ip_vers = hdr_data->ip_vers; + ip_proto = hdr_data->ip_proto; + + new_ip_hdr = (u8*) skb->data + hdr_data->eth_hdr_size; + + new_proto_hdr = new_ip_hdr + ip_hdr_size; + + len_for_calc = proto_hdr_size + aggr_payload_size; + + skb->ip_summed = CHECKSUM_PARTIAL; + + if ( ip_vers == 4 ) { + + struct iphdr* iph = (struct iphdr*) new_ip_hdr; + + iph->check = 0; + iph->check = ip_fast_csum(iph, iph->ihl); + + pseudo = ~csum_tcpudp_magic( + iph->saddr, + iph->daddr, + len_for_calc, + ip_proto, + 0); + + } else { /* ( ip_vers == 6 ) */ + + struct ipv6hdr* iph = (struct ipv6hdr*) new_ip_hdr; + + pseudo = ~csum_ipv6_magic( + &iph->saddr, + &iph->daddr, + len_for_calc, + ip_proto, + 0); + } + + if ( ip_proto == IPPROTO_TCP ) { + + struct tcphdr* hdr = (struct tcphdr*) new_proto_hdr; + + hdr->check = pseudo; + + skb->csum_offset = offsetof(struct tcphdr, check); + + } else { + + struct udphdr* hdr = (struct udphdr*) new_proto_hdr; + + hdr->check = pseudo; + + skb->csum_offset = offsetof(struct udphdr, check); + } + } + + return 0; +} + +/* + * The following function takes the constituent parts of an Ethernet + * and IP packet and creates an skb from them... + */ +static int +_prep_and_send_skb( + struct sk_buff* rx_skb, + struct ipa3_ep_context* ep, + u32 metadata, + u8 ucp, + ipa_header_data_t* hdr_data, + ipa_pkt_data_t* pkts, + u32 num_pkts, + u32 aggr_payload_size, + u8 pkt_id, + bool recalc_cksum ) +{ + struct ethhdr* eth_hdr; + u32 eth_hdr_size; + u8 ip_vers; + void* ip_hdr; + u32 ip_hdr_size; + u8 ip_proto; + void* proto_hdr; + u32 proto_hdr_size; + u32 aggr_hdr_len; + u32 i; + + void *new_proto_hdr, *new_ip_hdr, *new_eth_hdr; + + struct skb_shared_info *shinfo; + + struct sk_buff *head_skb; + + void *client_priv; + void (*client_notify)( + void *client_priv, + enum ipa_dp_evt_type evt, + unsigned long data); + + client_notify = 0; + + spin_lock(&ipa3_ctx->disconnect_lock); + if (ep->valid && ep->client_notify && + likely((!atomic_read(&ep->disconnect_in_progress)))) { + + client_notify = ep->client_notify; + client_priv = ep->priv; + } + spin_unlock(&ipa3_ctx->disconnect_lock); + + if ( client_notify ) { + + eth_hdr = hdr_data->eth_hdr; + eth_hdr_size = hdr_data->eth_hdr_size; + ip_vers = hdr_data->ip_vers; + ip_hdr = hdr_data->ip_hdr; + ip_hdr_size = hdr_data->ip_hdr_size; + ip_proto = hdr_data->ip_proto; + proto_hdr = hdr_data->proto_hdr; + proto_hdr_size = hdr_data->proto_hdr_size; + aggr_hdr_len = hdr_data->aggr_hdr_len; + + if ( rx_skb ) { + + head_skb = rx_skb; + + ipa3_ctx->stats.coal.coal_left_as_is++; + + } else { + + head_skb = alloc_skb(aggr_hdr_len + aggr_payload_size, GFP_ATOMIC); + + if ( unlikely(!head_skb) ) { + IPAERR("skb alloc failure\n"); + return -1; + } + + ipa3_ctx->stats.coal.coal_reconstructed++; + + head_skb->protocol = ip_proto; + + /* + * Copy MAC header into the skb... + */ + new_eth_hdr = skb_put_data(head_skb, eth_hdr, eth_hdr_size); + + skb_reset_mac_header(head_skb); + + /* + * Copy, and update, IP[4|6] header into the skb... + */ + new_ip_hdr = skb_put_data(head_skb, ip_hdr, ip_hdr_size); + + if ( ip_vers == 4 ) { + + struct iphdr* ip4h = new_ip_hdr; + + ip4h->id = htons(ntohs(ip4h->id) + pkt_id); + + ip4h->tot_len = + htons(ip_hdr_size + proto_hdr_size + aggr_payload_size); + + } else { + + struct ipv6hdr* ip6h = new_ip_hdr; + + ip6h->payload_len = + htons(proto_hdr_size + aggr_payload_size); + } + + skb_reset_network_header(head_skb); + + /* + * Copy, and update, [TCP|UDP] header into the skb... + */ + new_proto_hdr = skb_put_data(head_skb, proto_hdr, proto_hdr_size); + + if ( ip_proto == IPPROTO_TCP ) { + + struct tcphdr* hdr = new_proto_hdr; + + hdr_data->curr_seq += (aggr_payload_size) ? aggr_payload_size : 1; + + hdr->seq = htonl(hdr_data->curr_seq); + + } else { + + struct udphdr* hdr = new_proto_hdr; + + u16 len = sizeof(struct udphdr) + aggr_payload_size; + + hdr->len = htons(len); + } + + skb_reset_transport_header(head_skb); + + /* + * Now aggregate all the individual physical payloads into + * th eskb. + */ + for ( i = 0; i < num_pkts; i++ ) { + skb_put_data(head_skb, pkts[i].pkt, pkts[i].pkt_len); + } + } + + /* + * Is a recalc of the various checksums in order? + */ + if ( recalc_cksum ) { + _calc_partial_csum(head_skb, hdr_data, aggr_payload_size); + } + + /* + * Let's add some resegmentation info into the head skb. The + * data will allow the stack to resegment the data...should it + * need to relative to MTU... + */ + shinfo = skb_shinfo(head_skb); + + shinfo->gso_segs = num_pkts; + shinfo->gso_size = pkts[0].pkt_len; + + if (ip_proto == IPPROTO_TCP) { + shinfo->gso_type = (ip_vers == 4) ? SKB_GSO_TCPV4 : SKB_GSO_TCPV6; + ipa3_ctx->stats.coal.coal_tcp++; + ipa3_ctx->stats.coal.coal_tcp_bytes += aggr_payload_size; + } else { + shinfo->gso_type = SKB_GSO_UDP_L4; + ipa3_ctx->stats.coal.coal_udp++; + ipa3_ctx->stats.coal.coal_udp_bytes += aggr_payload_size; + } + + /* + * Send this new skb to the client... + */ + *(u16 *)head_skb->cb = ((metadata >> 16) & 0xFFFF); + *(u8 *)(head_skb->cb + 4) = ucp; + + IPADBG_LOW("meta_data: 0x%x cb: 0x%x\n", + metadata, *(u32 *)head_skb->cb); + IPADBG_LOW("ucp: %d\n", *(u8 *)(head_skb->cb + 4)); + + client_notify(client_priv, IPA_RECEIVE, (unsigned long)(head_skb)); + } + + return 0; +} + +/* + * The following will process a coalesced LAN packet from the IPA... + */ +void ipa3_lan_coal_rx_cb( + void *priv, + enum ipa_dp_evt_type evt, + unsigned long data) +{ + struct sk_buff *rx_skb = (struct sk_buff *) data; + + unsigned int src_pipe; + u8 ucp; + u32 metadata; + + struct ipahal_pkt_status_thin status; + struct ipa3_ep_context *ep; + + u8* qmap_hdr_data_ptr; + struct qmap_hdr_data qmap_hdr; + + struct coal_packet_status_info *cpsi, *cpsi_orig; + u8* stat_info_ptr; + + u32 pkt_status_sz = ipahal_pkt_status_get_size(); + + u32 eth_hdr_size; + u32 ip_hdr_size; + u8 ip_vers, ip_proto; + u32 proto_hdr_size; + u32 cpsi_hdrs_size; + u32 aggr_payload_size; + + u32 pkt_len; + + struct ethhdr* eth_hdr; + void* ip_hdr; + struct iphdr* ip4h; + struct ipv6hdr* ip6h; + void* proto_hdr; + u8* pkt_data; + bool gro = true; + bool cksum_is_zero; + ipa_header_data_t hdr_data; + + ipa_pkt_data_t in_pkts[MAX_COAL_PACKETS]; + u32 in_pkts_sub; + + u8 tot_pkts; + + u32 i, j; + + u64 cksum_mask = 0; + + int ret; + + IPA_DUMP_BUFF(skb->data, 0, skb->len); + + ipa3_ctx->stats.coal.coal_rx++; + + ipahal_pkt_status_parse_thin(rx_skb->data, &status); + src_pipe = status.endp_src_idx; + metadata = status.metadata; + ucp = status.ucp; + ep = &ipa3_ctx->ep[src_pipe]; + if (unlikely(src_pipe >= ipa3_ctx->ipa_num_pipes) || + unlikely(atomic_read(&ep->disconnect_in_progress))) { + IPAERR("drop pipe=%d\n", src_pipe); + goto process_done; + } + + memset(&hdr_data, 0, sizeof(hdr_data)); + memset(&qmap_hdr, 0, sizeof(qmap_hdr)); + + /* + * Let's get to, then parse, the qmap header... + */ + qmap_hdr_data_ptr = rx_skb->data + pkt_status_sz; + + ret = ipahal_qmap_parse(qmap_hdr_data_ptr, &qmap_hdr); + + if ( unlikely(ret) ) { + IPAERR("ipahal_qmap_parse fail\n"); + ipa3_ctx->stats.coal.coal_hdr_qmap_err++; + goto process_done; + } + + if ( ! VALID_NLS(qmap_hdr.num_nlos) ) { + IPAERR("Bad num_nlos(%u) value\n", qmap_hdr.num_nlos); + ipa3_ctx->stats.coal.coal_hdr_nlo_err++; + goto process_done; + } + + stat_info_ptr = qmap_hdr_data_ptr + sizeof(union qmap_hdr_u); + + cpsi = cpsi_orig = (struct coal_packet_status_info*) stat_info_ptr; + + /* + * Reconstruct the 48 bits of checksum info. And count total + * packets as well... + */ + for (i = tot_pkts = 0; + i < MAX_COAL_PACKET_STATUS_INFO; + ++i, ++cpsi) { + + cpsi->pkt_len = ntohs(cpsi->pkt_len); + + cksum_mask |= ((u64) cpsi->pkt_cksum_errs) << (8 * i); + + if ( i < qmap_hdr.num_nlos ) { + tot_pkts += cpsi->num_pkts; + } + } + + /* + * A bounds check. + * + * Technically, the hardware shouldn't give us a bad count, but + * just to be safe... + */ + if ( tot_pkts > MAX_COAL_PACKETS ) { + IPAERR("tot_pkts(%u) > MAX_COAL_PACKETS(%u)\n", + tot_pkts, MAX_COAL_PACKETS); + ipa3_ctx->stats.coal.coal_hdr_pkt_err++; + goto process_done; + } + + ipa3_ctx->stats.coal.coal_pkts += tot_pkts; + + /* + * Move along past the coal headers... + */ + cpsi_hdrs_size = MAX_COAL_PACKET_STATUS_INFO * sizeof(u32); + + pkt_data = stat_info_ptr + cpsi_hdrs_size; + + /* + * Let's processes the Ethernet header... + */ + eth_hdr = (struct ethhdr*) pkt_data; + + switch ( ntohs(eth_hdr->h_proto) ) + { + case IPA_ETH_VLAN_2TAG: + eth_hdr_size = sizeof(struct ethhdr) + (IPA_ETH_TAG_SZ * 2); + break; + case IPA_ETH_VLAN_TAG: + eth_hdr_size = sizeof(struct ethhdr) + IPA_ETH_TAG_SZ; + break; + default: + eth_hdr_size = sizeof(struct ethhdr); + break; + } + + /* + * Get to and process the ip header... + */ + ip_hdr = (u8*) eth_hdr + eth_hdr_size; + + /* + * Is it a IPv[4|6] header? + */ + if (((struct iphdr*) ip_hdr)->version == 4) { + /* + * Eth frame is carrying ip v4 payload. + */ + ip_vers = 4; + ip4h = (struct iphdr*) ip_hdr; + ip_hdr_size = ip4h->ihl * sizeof(u32); + ip_proto = ip4h->protocol; + + /* + * Don't allow grouping of any packets with IP options + * (i.e. don't allow when ihl != 5)... + */ + gro = (ip4h->ihl == 5); + + } else if (((struct ipv6hdr*) ip_hdr)->version == 6) { + /* + * Eth frame is carrying ip v6 payload. + */ + int hdr_size; + __be16 frag_off; + + ip_vers = 6; + ip6h = (struct ipv6hdr*) ip_hdr; + ip_proto = ip6h->nexthdr; + + /* + * If extension headers exist, we need to analyze/skip them, + * hence... + */ + hdr_size = _skip_ipv6_exthdr( + (u8*) ip_hdr, + sizeof(*ip6h), + &ip_proto, + &frag_off); + + /* + * If we run into a problem, or this has a fragmented header + * (which technically should not be possible if the HW works + * as intended), bail. + */ + if (hdr_size < 0 || frag_off) { + IPAERR( + "_skip_ipv6_exthdr() failed. Errored with hdr_size(%d) " + "and/or frag_off(%d)\n", + hdr_size, + ntohs(frag_off)); + ipa3_ctx->stats.coal.coal_ip_invalid++; + goto process_done; + } + + ip_hdr_size = hdr_size; + + /* + * Don't allow grouping of any packets with IPv6 extension + * headers (i.e. don't allow when ip_hdr_size != basic v6 + * header size). + */ + gro = (ip_hdr_size == sizeof(*ip6h)); + + } else { + + IPAERR("Not a v4 or v6 header...can't process\n"); + ipa3_ctx->stats.coal.coal_ip_invalid++; + goto process_done; + } + + /* + * Get to and process the protocol header... + */ + proto_hdr = (u8*) ip_hdr + ip_hdr_size; + + if (ip_proto == IPPROTO_TCP) { + + struct tcphdr* hdr = (struct tcphdr*) proto_hdr; + + hdr_data.curr_seq = ntohl(hdr->seq); + + proto_hdr_size = hdr->doff * sizeof(u32); + + cksum_is_zero = false; + + } else if (ip_proto == IPPROTO_UDP) { + + proto_hdr_size = sizeof(struct udphdr); + + cksum_is_zero = (ip_vers == 4 && ((struct udphdr*) proto_hdr)->check == 0); + + } else { + + IPAERR("Not a TCP or UDP heqder...can't process\n"); + ipa3_ctx->stats.coal.coal_trans_invalid++; + goto process_done; + + } + + /* + * The following will adjust the skb internals (ie. skb->data and + * skb->len), such that they're positioned, and reflect, the data + * starting at the ETH header... + */ + skb_pull( + rx_skb, + pkt_status_sz + + sizeof(union qmap_hdr_u) + + cpsi_hdrs_size); + + /* + * Consolidate all header, header type, and header size info... + */ + hdr_data.eth_hdr = eth_hdr; + hdr_data.eth_hdr_size = eth_hdr_size; + hdr_data.ip_vers = ip_vers; + hdr_data.ip_hdr = ip_hdr; + hdr_data.ip_hdr_size = ip_hdr_size; + hdr_data.ip_proto = ip_proto; + hdr_data.proto_hdr = proto_hdr; + hdr_data.proto_hdr_size = proto_hdr_size; + hdr_data.aggr_hdr_len = eth_hdr_size + ip_hdr_size + proto_hdr_size; + + if ( qmap_hdr.vcid < GSI_VEID_MAX ) { + ipa3_ctx->stats.coal.coal_veid[qmap_hdr.vcid] += 1; + } + + /* + * Quick check to see if we really need to go any further... + */ + if ( gro && qmap_hdr.num_nlos == 1 && qmap_hdr.chksum_valid ) { + + cpsi = cpsi_orig; + + in_pkts[0].pkt = rx_skb->data + hdr_data.aggr_hdr_len; + in_pkts[0].pkt_len = cpsi->pkt_len - (ip_hdr_size + proto_hdr_size); + + in_pkts_sub = 1; + + aggr_payload_size = rx_skb->len - hdr_data.aggr_hdr_len; + + _prep_and_send_skb( + rx_skb, + ep, metadata, ucp, + &hdr_data, + in_pkts, + in_pkts_sub, + aggr_payload_size, + tot_pkts, + false); + + return; + } + + /* + * Time to process packet payloads... + */ + pkt_data = (u8*) proto_hdr + proto_hdr_size; + + for ( i = tot_pkts = 0, cpsi = cpsi_orig; + i < qmap_hdr.num_nlos; + ++i, ++cpsi ) { + + aggr_payload_size = in_pkts_sub = 0; + + for ( j = 0; + j < cpsi->num_pkts; + j++, tot_pkts++, cksum_mask >>= 1 ) { + + bool csum_err = cksum_mask & 1; + + pkt_len = cpsi->pkt_len - (ip_hdr_size + proto_hdr_size); + + if ( csum_err || ! gro ) { + + if ( csum_err ) { + ipa3_ctx->stats.coal.coal_csum_err++; + } + + /* + * If there are previously queued packets, send them + * now... + */ + if ( in_pkts_sub ) { + + _prep_and_send_skb( + NULL, + ep, metadata, ucp, + &hdr_data, + in_pkts, + in_pkts_sub, + aggr_payload_size, + tot_pkts, + !cksum_is_zero); + + in_pkts_sub = aggr_payload_size = 0; + } + + /* + * Now send the singleton... + */ + in_pkts[in_pkts_sub].pkt = pkt_data; + in_pkts[in_pkts_sub].pkt_len = pkt_len; + + aggr_payload_size += in_pkts[in_pkts_sub].pkt_len; + pkt_data += in_pkts[in_pkts_sub].pkt_len; + + in_pkts_sub++; + + _prep_and_send_skb( + NULL, + ep, metadata, ucp, + &hdr_data, + in_pkts, + in_pkts_sub, + aggr_payload_size, + tot_pkts, + (csum_err) ? false : !cksum_is_zero); + + in_pkts_sub = aggr_payload_size = 0; + + continue; + } + + in_pkts[in_pkts_sub].pkt = pkt_data; + in_pkts[in_pkts_sub].pkt_len = pkt_len; + + aggr_payload_size += in_pkts[in_pkts_sub].pkt_len; + pkt_data += in_pkts[in_pkts_sub].pkt_len; + + in_pkts_sub++; + } + + if ( in_pkts_sub ) { + + _prep_and_send_skb( + NULL, + ep, metadata, ucp, + &hdr_data, + in_pkts, + in_pkts_sub, + aggr_payload_size, + tot_pkts, + !cksum_is_zero); + } + } + +process_done: + /* + * One way or the other, we no longer need the skb, hence... + */ + dev_kfree_skb_any(rx_skb); +} + +static void ipa3_recycle_rx_wrapper(struct ipa3_rx_pkt_wrapper *rx_pkt) +{ + rx_pkt->data.dma_addr = 0; + /* skb recycle was moved to pyld_hdlr */ + INIT_LIST_HEAD(&rx_pkt->link); + spin_lock_bh(&rx_pkt->sys->spinlock); + list_add_tail(&rx_pkt->link, &rx_pkt->sys->rcycl_list); + spin_unlock_bh(&rx_pkt->sys->spinlock); +} + +static void ipa3_recycle_rx_page_wrapper(struct ipa3_rx_pkt_wrapper *rx_pkt) +{ + struct ipa_rx_page_data rx_page; + + rx_page = rx_pkt->page_data; + + /* Free rx_wrapper only for tmp alloc pages*/ + if (rx_page.is_tmp_alloc) + kmem_cache_free(ipa3_ctx->rx_pkt_wrapper_cache, rx_pkt); +} + +/** + * handle_skb_completion()- Handle event completion EOB or EOT and prep the skb + * + * if eob: Set skb values, put rx_pkt at the end of the list and return NULL + * + * if eot: Set skb values, put skb at the end of the list. Then update the + * length and chain the skbs together while also freeing and unmapping the + * corresponding rx pkt. Once finished return the head_skb to be sent up the + * network stack. + */ +static struct sk_buff *handle_skb_completion( + struct gsi_chan_xfer_notify *notify, + bool update_truesize, + struct ipa3_rx_pkt_wrapper **rx_pkt_ptr ) +{ + struct ipa3_rx_pkt_wrapper *rx_pkt, *tmp; + struct sk_buff *rx_skb, *next_skb = NULL; + struct list_head *head; + struct ipa3_sys_context *sys; + + sys = (struct ipa3_sys_context *) notify->chan_user_data; + rx_pkt = (struct ipa3_rx_pkt_wrapper *) notify->xfer_user_data; + + if ( rx_pkt_ptr ) { + *rx_pkt_ptr = rx_pkt; + } + + spin_lock_bh(&rx_pkt->sys->spinlock); + rx_pkt->sys->len--; + spin_unlock_bh(&rx_pkt->sys->spinlock); + + if (notify->bytes_xfered) + rx_pkt->len = notify->bytes_xfered; + + /*Drop packets when WAN consumer channel receive EOB event*/ + if ((notify->evt_id == GSI_CHAN_EVT_EOB || + sys->skip_eot) && + sys->ep->client == IPA_CLIENT_APPS_WAN_CONS) { + dma_unmap_single(ipa3_ctx->pdev, rx_pkt->data.dma_addr, + sys->rx_buff_sz, DMA_FROM_DEVICE); + sys->free_skb(rx_pkt->data.skb); + sys->free_rx_wrapper(rx_pkt); + sys->eob_drop_cnt++; + if (notify->evt_id == GSI_CHAN_EVT_EOB) { + IPADBG("EOB event on WAN consumer channel, drop\n"); + sys->skip_eot = true; + } else { + IPADBG("Reset skip eot flag.\n"); + sys->skip_eot = false; + } + return NULL; + } + + rx_skb = rx_pkt->data.skb; + skb_set_tail_pointer(rx_skb, rx_pkt->len); + rx_skb->len = rx_pkt->len; + + if (update_truesize) { + *(unsigned int *)rx_skb->cb = rx_skb->len; + rx_skb->truesize = rx_pkt->len + sizeof(struct sk_buff); + } + + if (notify->veid >= GSI_VEID_MAX) { + WARN_ON(1); + return NULL; + } + + head = &rx_pkt->sys->pending_pkts[notify->veid]; + + INIT_LIST_HEAD(&rx_pkt->link); + list_add_tail(&rx_pkt->link, head); + + /* Check added for handling LAN consumer packet without EOT flag */ + if (notify->evt_id == GSI_CHAN_EVT_EOT || + sys->ep->client == IPA_CLIENT_APPS_LAN_CONS || + sys->ep->client == IPA_CLIENT_APPS_LAN_COAL_CONS) { + /* go over the list backward to save computations on updating length */ + list_for_each_entry_safe_reverse(rx_pkt, tmp, head, link) { + rx_skb = rx_pkt->data.skb; + + list_del(&rx_pkt->link); + dma_unmap_single(ipa3_ctx->pdev, rx_pkt->data.dma_addr, + sys->rx_buff_sz, DMA_FROM_DEVICE); + sys->free_rx_wrapper(rx_pkt); + + if (next_skb) { + skb_shinfo(rx_skb)->frag_list = next_skb; + rx_skb->len += next_skb->len; + rx_skb->data_len += next_skb->len; + } + next_skb = rx_skb; + } + } else { + return NULL; + } + return rx_skb; +} + +/** + * handle_page_completion()- Handle event completion EOB or EOT + * and prep the skb + * + * if eob: Set skb values, put rx_pkt at the end of the list and return NULL + * + * if eot: Set skb values, put skb at the end of the list. Then update the + * length and put the page together to the frags while also + * freeing and unmapping the corresponding rx pkt. Once finished + * return the head_skb to be sent up the network stack. + */ +static struct sk_buff *handle_page_completion(struct gsi_chan_xfer_notify + *notify, bool update_truesize) +{ + struct ipa3_rx_pkt_wrapper *rx_pkt, *tmp; + struct sk_buff *rx_skb; + struct list_head *head; + struct ipa3_sys_context *sys; + struct ipa_rx_page_data rx_page; + int size; + + sys = (struct ipa3_sys_context *) notify->chan_user_data; + rx_pkt = (struct ipa3_rx_pkt_wrapper *) notify->xfer_user_data; + rx_page = rx_pkt->page_data; + + spin_lock_bh(&rx_pkt->sys->spinlock); + rx_pkt->sys->len--; + spin_unlock_bh(&rx_pkt->sys->spinlock); + + if (likely(notify->bytes_xfered)) + rx_pkt->data_len = notify->bytes_xfered; + else { + IPAERR_RL("unexpected 0 byte_xfered\n"); + rx_pkt->data_len = rx_pkt->len; + } + + if (notify->veid >= GSI_VEID_MAX) { + IPAERR("notify->veid > GSI_VEID_MAX\n"); + if (!rx_page.is_tmp_alloc) { + init_page_count(rx_page.page); + spin_lock_bh(&rx_pkt->sys->common_sys->spinlock); + /* Add the element to head. */ + list_add(&rx_pkt->link, + &rx_pkt->sys->page_recycle_repl->page_repl_head); + spin_unlock_bh(&rx_pkt->sys->common_sys->spinlock); + } else { + dma_unmap_page(ipa3_ctx->pdev, rx_page.dma_addr, + rx_pkt->len, DMA_FROM_DEVICE); + __free_pages(rx_pkt->page_data.page, rx_pkt->page_data.page_order); + } + rx_pkt->sys->free_rx_wrapper(rx_pkt); + IPA_STATS_INC_CNT(ipa3_ctx->stats.rx_page_drop_cnt); + return NULL; + } + + head = &rx_pkt->sys->pending_pkts[notify->veid]; + + INIT_LIST_HEAD(&rx_pkt->link); + list_add_tail(&rx_pkt->link, head); + + /* Check added for handling LAN consumer packet without EOT flag */ + if (notify->evt_id == GSI_CHAN_EVT_EOT || + sys->ep->client == IPA_CLIENT_APPS_LAN_CONS) { + rx_skb = alloc_skb(0, GFP_ATOMIC); + if (unlikely(!rx_skb)) { + IPAERR("skb alloc failure, free all pending pages\n"); + list_for_each_entry_safe(rx_pkt, tmp, head, link) { + rx_page = rx_pkt->page_data; + size = rx_pkt->data_len; + list_del_init(&rx_pkt->link); + if (!rx_page.is_tmp_alloc) { + init_page_count(rx_page.page); + spin_lock_bh(&rx_pkt->sys->common_sys->spinlock); + /* Add the element to head. */ + list_add(&rx_pkt->link, + &rx_pkt->sys->page_recycle_repl->page_repl_head); + spin_unlock_bh(&rx_pkt->sys->common_sys->spinlock); + } else { + dma_unmap_page(ipa3_ctx->pdev, rx_page.dma_addr, + rx_pkt->len, DMA_FROM_DEVICE); + __free_pages(rx_pkt->page_data.page, rx_pkt->page_data.page_order); + } + rx_pkt->sys->free_rx_wrapper(rx_pkt); + } + IPA_STATS_INC_CNT(ipa3_ctx->stats.rx_page_drop_cnt); + return NULL; + } + list_for_each_entry_safe(rx_pkt, tmp, head, link) { + rx_page = rx_pkt->page_data; + size = rx_pkt->data_len; + + list_del_init(&rx_pkt->link); + if (rx_page.is_tmp_alloc) { + dma_unmap_page(ipa3_ctx->pdev, rx_page.dma_addr, + rx_pkt->len, DMA_FROM_DEVICE); + } else { + spin_lock_bh(&rx_pkt->sys->common_sys->spinlock); + /* Add the element back to tail. */ + list_add_tail(&rx_pkt->link, + &rx_pkt->sys->page_recycle_repl->page_repl_head); + spin_unlock_bh(&rx_pkt->sys->common_sys->spinlock); + dma_sync_single_for_cpu(ipa3_ctx->pdev, + rx_page.dma_addr, + rx_pkt->len, DMA_FROM_DEVICE); + } + rx_pkt->sys->free_rx_wrapper(rx_pkt); + + skb_add_rx_frag(rx_skb, + skb_shinfo(rx_skb)->nr_frags, + rx_page.page, 0, + size, + PAGE_SIZE << rx_page.page_order); + + trace_handle_page_completion(rx_page.page, + rx_skb, notify->bytes_xfered, + rx_page.is_tmp_alloc, sys->ep->client); + } + } else { + return NULL; + } + return rx_skb; +} + +static void ipa3_wq_rx_common( + struct ipa3_sys_context *sys, + struct gsi_chan_xfer_notify *notify) +{ + struct ipa3_rx_pkt_wrapper *rx_pkt; + struct sk_buff *rx_skb; + + if (!notify) { + IPAERR_RL("gsi_chan_xfer_notify is null\n"); + return; + } + + rx_skb = handle_skb_completion(notify, true, &rx_pkt); + + if (rx_skb) { + rx_pkt->sys->pyld_hdlr(rx_skb, rx_pkt->sys); + rx_pkt->sys->repl_hdlr(rx_pkt->sys); + } +} + +static void ipa3_rx_napi_chain(struct ipa3_sys_context *sys, + struct gsi_chan_xfer_notify *notify, uint32_t num) +{ + struct ipa3_sys_context *wan_def_sys; + int i, ipa_ep_idx; + struct sk_buff *rx_skb, *first_skb = NULL, *prev_skb = NULL, + *second_skb = NULL; + + /* non-coalescing case (SKB chaining enabled) */ + /* Chain is created as follows: first_skb->frag_list = second_skb + * After that the next skb's are added to second_skb->next .i.e + * first_skb->frag_list->next->next->next etc..*/ + if (sys->ep->client != IPA_CLIENT_APPS_WAN_COAL_CONS) { + for (i = 0; i < num; i++) { + if (!ipa3_ctx->ipa_wan_skb_page) + rx_skb = handle_skb_completion( + ¬ify[i], false, NULL); + else + rx_skb = handle_page_completion( + ¬ify[i], false); + + /* this is always true for EOTs */ + if (rx_skb) { + if (!first_skb) { + first_skb = rx_skb; + } else if (!second_skb) { + second_skb = rx_skb; + skb_shinfo(first_skb)->frag_list = + second_skb; + } else if (prev_skb) { + prev_skb->next = rx_skb; + } + prev_skb = rx_skb; + trace_ipa3_rx_napi_chain(first_skb, + prev_skb, + rx_skb); + } + } + if (prev_skb) { + skb_shinfo(prev_skb)->frag_list = NULL; + sys->pyld_hdlr(first_skb, sys); + } + } else { + if (!ipa3_ctx->ipa_wan_skb_page) { + /* TODO: add chaining for coal case */ + for (i = 0; i < num; i++) { + rx_skb = handle_skb_completion( + ¬ify[i], false, NULL); + if (rx_skb) { + sys->pyld_hdlr(rx_skb, sys); + /* + * For coalescing, we have 2 transfer + * rings to replenish + */ + ipa_ep_idx = ipa_get_ep_mapping( + IPA_CLIENT_APPS_WAN_CONS); + if (ipa_ep_idx == + IPA_EP_NOT_ALLOCATED) { + IPAERR("Invalid client.\n"); + return; + } + wan_def_sys = + ipa3_ctx->ep[ipa_ep_idx].sys; + wan_def_sys->repl_hdlr(wan_def_sys); + sys->repl_hdlr(sys); + } + } + } else { + for (i = 0; i < num; i++) { + rx_skb = handle_page_completion( + ¬ify[i], false); + + /* this is always true for EOTs */ + if (rx_skb) { + if (!first_skb) { + first_skb = rx_skb; + } else if (!second_skb) { + second_skb = rx_skb; + skb_shinfo(first_skb)->frag_list = + second_skb; + } else if (prev_skb) { + prev_skb->next = rx_skb; + } + prev_skb = rx_skb; + trace_ipa3_rx_napi_chain(first_skb, + prev_skb, + rx_skb); + } + } + if (prev_skb) { + skb_shinfo(prev_skb)->frag_list = NULL; + sys->pyld_hdlr(first_skb, sys); + } + } + } +} + +static void ipa3_wlan_wq_rx_common(struct ipa3_sys_context *sys, + struct gsi_chan_xfer_notify *notify) +{ + struct ipa3_rx_pkt_wrapper *rx_pkt_expected; + struct sk_buff *rx_skb; + + rx_pkt_expected = (struct ipa3_rx_pkt_wrapper *) notify->xfer_user_data; + + sys->len--; + + if (notify->bytes_xfered) + rx_pkt_expected->len = notify->bytes_xfered; + + rx_skb = rx_pkt_expected->data.skb; + skb_set_tail_pointer(rx_skb, rx_pkt_expected->len); + rx_skb->len = rx_pkt_expected->len; + rx_skb->truesize = rx_pkt_expected->len + sizeof(struct sk_buff); + sys->ep->wstats.tx_pkts_rcvd++; + if (sys->len <= IPA_WLAN_RX_POOL_SZ_LOW_WM) { + ipa_free_skb(&rx_pkt_expected->data); + sys->ep->wstats.tx_pkts_dropped++; + } else { + sys->ep->wstats.tx_pkts_sent++; + sys->ep->client_notify(sys->ep->priv, IPA_RECEIVE, + (unsigned long)(&rx_pkt_expected->data)); + } + ipa3_replenish_wlan_rx_cache(sys); +} + +static void ipa3_dma_memcpy_notify(struct ipa3_sys_context *sys) +{ + IPADBG_LOW("ENTER.\n"); + if (unlikely(list_empty(&sys->head_desc_list))) { + IPAERR("descriptor list is empty!\n"); + WARN_ON(1); + return; + } + sys->ep->client_notify(sys->ep->priv, IPA_RECEIVE, 0); + IPADBG_LOW("EXIT\n"); +} + +static void ipa3_wq_rx_avail(struct work_struct *work) +{ + struct ipa3_rx_pkt_wrapper *rx_pkt; + struct ipa3_sys_context *sys; + + rx_pkt = container_of(work, struct ipa3_rx_pkt_wrapper, work); + WARN(unlikely(rx_pkt == NULL), "rx pkt is null"); + sys = rx_pkt->sys; + ipa3_wq_rx_common(sys, 0); +} + +static int ipa3_odu_rx_pyld_hdlr(struct sk_buff *rx_skb, + struct ipa3_sys_context *sys) +{ + if (sys->ep->client_notify) { + sys->ep->client_notify(sys->ep->priv, IPA_RECEIVE, + (unsigned long)(rx_skb)); + } else { + dev_kfree_skb_any(rx_skb); + WARN(1, "client notify is null"); + } + + return 0; +} + +static int ipa3_odl_dpl_rx_pyld_hdlr(struct sk_buff *rx_skb, + struct ipa3_sys_context *sys) +{ + if (WARN(!sys->ep->client_notify, "sys->ep->client_notify is NULL\n")) { + dev_kfree_skb_any(rx_skb); + } else { + sys->ep->client_notify(sys->ep->priv, IPA_RECEIVE, + (unsigned long)(rx_skb)); + /*Recycle the SKB before reusing it*/ + ipa3_skb_recycle(rx_skb); + } + + return 0; +} +static void ipa3_free_rx_wrapper(struct ipa3_rx_pkt_wrapper *rk_pkt) +{ + kmem_cache_free(ipa3_ctx->rx_pkt_wrapper_cache, rk_pkt); +} + +static void ipa3_set_aggr_limit(struct ipa_sys_connect_params *in, + struct ipa3_sys_context *sys) +{ + u32 *aggr_byte_limit = &in->ipa_ep_cfg.aggr.aggr_byte_limit; + u32 adjusted_sz; + + if (ipa3_ctx->ipa_wan_skb_page) { + IPAERR("set rx_buff_sz config from netmngr %lu\n", (unsigned long) + sys->buff_size); + sys->rx_buff_sz = IPA_GENERIC_RX_BUFF_SZ(sys->buff_size); + *aggr_byte_limit = IPA_ADJUST_AGGR_BYTE_LIMIT(*aggr_byte_limit); + } else { + adjusted_sz = ipa_adjust_ra_buff_base_sz(*aggr_byte_limit); + IPAERR("get close-by %u\n", adjusted_sz); + IPAERR("set default rx_buff_sz %lu\n", (unsigned long) + IPA_GENERIC_RX_BUFF_SZ(adjusted_sz)); + sys->rx_buff_sz = IPA_GENERIC_RX_BUFF_SZ(adjusted_sz); + *aggr_byte_limit = sys->rx_buff_sz < *aggr_byte_limit ? + IPA_ADJUST_AGGR_BYTE_LIMIT(sys->rx_buff_sz) : + IPA_ADJUST_AGGR_BYTE_LIMIT(*aggr_byte_limit); + } + + /* disable ipa_status */ + sys->ep->status.status_en = false; + + if (in->client == IPA_CLIENT_APPS_WAN_COAL_CONS || + (in->client == IPA_CLIENT_APPS_WAN_CONS && + ipa3_ctx->ipa_hw_type <= IPA_HW_v4_2)) + in->ipa_ep_cfg.aggr.aggr_hard_byte_limit_en = 1; + + IPADBG("set aggr_limit %lu\n", (unsigned long) *aggr_byte_limit); +} + +static int ipa3_assign_policy(struct ipa_sys_connect_params *in, + struct ipa3_sys_context *sys) +{ + bool apps_wan_cons_agg_gro_flag; + unsigned long aggr_byte_limit; + + if (in->client == IPA_CLIENT_APPS_CMD_PROD || + in->client == IPA_CLIENT_APPS_WAN_LOW_LAT_PROD) { + sys->policy = IPA_POLICY_INTR_MODE; + sys->use_comm_evt_ring = false; + return 0; + } + + if (in->client == IPA_CLIENT_APPS_WAN_PROD || + in->client == IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_PROD) { + sys->policy = IPA_POLICY_INTR_MODE; + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0) + sys->use_comm_evt_ring = false; + else + sys->use_comm_evt_ring = true; + INIT_WORK(&sys->work, ipa3_send_nop_desc); + atomic_set(&sys->workqueue_flushed, 0); + + /* + * enable source notification status for exception packets + * (i.e. QMAP commands) to be routed to modem. + */ + sys->ep->status.status_en = true; + sys->ep->status.status_ep = + ipa_get_ep_mapping(IPA_CLIENT_Q6_WAN_CONS); + /* Enable status supression to disable sending status for + * every packet. + */ + sys->ep->status.status_pkt_suppress = true; + return 0; + } + + if (IPA_CLIENT_IS_MEMCPY_DMA_PROD(in->client)) { + sys->policy = IPA_POLICY_NOINTR_MODE; + return 0; + } + + apps_wan_cons_agg_gro_flag = + ipa3_ctx->ipa_client_apps_wan_cons_agg_gro; + aggr_byte_limit = in->ipa_ep_cfg.aggr.aggr_byte_limit; + + if (IPA_CLIENT_IS_PROD(in->client)) { + if (sys->ep->skip_ep_cfg) { + sys->policy = IPA_POLICY_INTR_POLL_MODE; + sys->use_comm_evt_ring = true; + atomic_set(&sys->curr_polling_state, 0); + } else { + sys->policy = IPA_POLICY_INTR_MODE; + sys->use_comm_evt_ring = true; + INIT_WORK(&sys->work, ipa3_send_nop_desc); + atomic_set(&sys->workqueue_flushed, 0); + } + } else { + if (IPA_CLIENT_IS_LAN_CONS(in->client) || + IPA_CLIENT_IS_WAN_CONS(in->client) || + in->client == IPA_CLIENT_APPS_WAN_LOW_LAT_CONS || + in->client == IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_CONS) { + sys->ep->status.status_en = true; + sys->policy = IPA_POLICY_INTR_POLL_MODE; + INIT_WORK(&sys->work, ipa3_wq_handle_rx); + INIT_DELAYED_WORK(&sys->switch_to_intr_work, + ipa3_switch_to_intr_rx_work_func); + INIT_DELAYED_WORK(&sys->replenish_rx_work, + ipa3_replenish_rx_work_func); + atomic_set(&sys->curr_polling_state, 0); + sys->rx_buff_sz = IPA_GENERIC_RX_BUFF_SZ( + IPA_GENERIC_RX_BUFF_BASE_SZ); + sys->get_skb = ipa3_get_skb_ipa_rx; + sys->free_skb = ipa_free_skb_rx; + if (IPA_CLIENT_IS_APPS_COAL_CONS(in->client)) + in->ipa_ep_cfg.aggr.aggr = IPA_COALESCE; + else + in->ipa_ep_cfg.aggr.aggr = IPA_GENERIC; + if (IPA_CLIENT_IS_LAN_CONS(in->client)) { + INIT_WORK(&sys->repl_work, ipa3_wq_repl_rx); + sys->pyld_hdlr = ipa3_lan_rx_pyld_hdlr; + sys->repl_hdlr = + ipa3_replenish_rx_cache_recycle; + sys->free_rx_wrapper = + ipa3_recycle_rx_wrapper; + sys->rx_pool_sz = + ipa3_ctx->lan_rx_ring_size; + in->ipa_ep_cfg.aggr.aggr_en = IPA_ENABLE_AGGR; + in->ipa_ep_cfg.aggr.aggr_byte_limit = + IPA_GENERIC_AGGR_BYTE_LIMIT; + in->ipa_ep_cfg.aggr.aggr_pkt_limit = + IPA_GENERIC_AGGR_PKT_LIMIT; + in->ipa_ep_cfg.aggr.aggr_time_limit = + IPA_GENERIC_AGGR_TIME_LIMIT; + if (in->client == IPA_CLIENT_APPS_LAN_COAL_CONS) { + in->ipa_ep_cfg.aggr.aggr_coal_l2 = true; + in->ipa_ep_cfg.aggr.aggr_hard_byte_limit_en = 1; + } + } else if (IPA_CLIENT_IS_WAN_CONS(in->client) || + in->client == IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_CONS) { + in->ipa_ep_cfg.aggr.aggr_en = IPA_ENABLE_AGGR; + if (!in->ext_ioctl_v2) + in->ipa_ep_cfg.aggr.aggr_time_limit = + IPA_GENERIC_AGGR_TIME_LIMIT; + if ((ipa3_ctx->ipa_wan_skb_page + && in->napi_obj) || + in->client == IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_CONS) { + INIT_WORK(&sys->repl_work, + ipa3_wq_page_repl); + sys->pyld_hdlr = ipa3_wan_rx_pyld_hdlr; + sys->free_rx_wrapper = + ipa3_recycle_rx_page_wrapper; + sys->repl_hdlr = + ipa3_replenish_rx_page_recycle; + sys->rx_pool_sz = + ipa3_ctx->wan_rx_ring_size; + } else { + INIT_WORK(&sys->repl_work, + ipa3_wq_repl_rx); + sys->pyld_hdlr = ipa3_wan_rx_pyld_hdlr; + sys->free_rx_wrapper = + ipa3_free_rx_wrapper; + sys->rx_pool_sz = + ipa3_ctx->wan_rx_ring_size; + if (nr_cpu_ids > 1) { + sys->repl_hdlr = + ipa3_fast_replenish_rx_cache; + } else { + sys->repl_hdlr = + ipa3_replenish_rx_cache; + } + if (in->napi_obj && in->recycle_enabled) + sys->repl_hdlr = + ipa3_replenish_rx_cache_recycle; + } + in->ipa_ep_cfg.aggr.aggr_sw_eof_active + = true; + if (apps_wan_cons_agg_gro_flag) + ipa3_set_aggr_limit(in, sys); + else { + in->ipa_ep_cfg.aggr.aggr_byte_limit + = IPA_GENERIC_AGGR_BYTE_LIMIT; + in->ipa_ep_cfg.aggr.aggr_pkt_limit + = IPA_GENERIC_AGGR_PKT_LIMIT; + } + } else if (in->client == + IPA_CLIENT_APPS_WAN_LOW_LAT_CONS) { + INIT_WORK(&sys->repl_work, ipa3_wq_repl_rx); + sys->ep->status.status_en = false; + sys->rx_buff_sz = IPA_GENERIC_RX_BUFF_SZ( + IPA_QMAP_RX_BUFF_BASE_SZ); + sys->pyld_hdlr = ipa3_low_lat_rx_pyld_hdlr; + sys->repl_hdlr = + ipa3_fast_replenish_rx_cache; + sys->free_rx_wrapper = + ipa3_free_rx_wrapper; + sys->rx_pool_sz = + ipa3_ctx->wan_rx_ring_size; + } + } else if (IPA_CLIENT_IS_WLAN_CONS(in->client)) { + IPADBG("assigning policy to client:%d", + in->client); + + sys->policy = IPA_POLICY_INTR_POLL_MODE; + INIT_WORK(&sys->work, ipa3_wq_handle_rx); + INIT_DELAYED_WORK(&sys->switch_to_intr_work, + ipa3_switch_to_intr_rx_work_func); + INIT_DELAYED_WORK(&sys->replenish_rx_work, + ipa3_replenish_rx_work_func); + atomic_set(&sys->curr_polling_state, 0); + sys->rx_buff_sz = IPA_WLAN_RX_BUFF_SZ; + sys->rx_pool_sz = in->desc_fifo_sz / + IPA_FIFO_ELEMENT_SIZE - 1; + if (sys->rx_pool_sz > IPA_WLAN_RX_POOL_SZ) + sys->rx_pool_sz = IPA_WLAN_RX_POOL_SZ; + sys->pyld_hdlr = NULL; + sys->repl_hdlr = ipa3_replenish_wlan_rx_cache; + sys->get_skb = ipa3_get_skb_ipa_rx; + sys->free_skb = ipa_free_skb_rx; + sys->free_rx_wrapper = ipa3_free_rx_wrapper; + in->ipa_ep_cfg.aggr.aggr_en = IPA_BYPASS_AGGR; + } else if (IPA_CLIENT_IS_ODU_CONS(in->client)) { + IPADBG("assigning policy to client:%d", + in->client); + + sys->policy = IPA_POLICY_INTR_POLL_MODE; + INIT_WORK(&sys->work, ipa3_wq_handle_rx); + INIT_DELAYED_WORK(&sys->switch_to_intr_work, + ipa3_switch_to_intr_rx_work_func); + INIT_DELAYED_WORK(&sys->replenish_rx_work, + ipa3_replenish_rx_work_func); + atomic_set(&sys->curr_polling_state, 0); + sys->rx_pool_sz = in->desc_fifo_sz / + IPA_FIFO_ELEMENT_SIZE - 1; + if (sys->rx_pool_sz > IPA_ODU_RX_POOL_SZ) + sys->rx_pool_sz = IPA_ODU_RX_POOL_SZ; + sys->pyld_hdlr = ipa3_odu_rx_pyld_hdlr; + sys->get_skb = ipa3_get_skb_ipa_rx; + sys->free_skb = ipa_free_skb_rx; + /* recycle skb for GSB use case */ + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_0) { + sys->free_rx_wrapper = + ipa3_free_rx_wrapper; + sys->repl_hdlr = + ipa3_replenish_rx_cache; + /* Overwrite buffer size & aggr limit for GSB */ + sys->rx_buff_sz = IPA_GENERIC_RX_BUFF_SZ( + IPA_GSB_RX_BUFF_BASE_SZ); + in->ipa_ep_cfg.aggr.aggr_byte_limit = + IPA_GSB_AGGR_BYTE_LIMIT; + } else { + sys->free_rx_wrapper = + ipa3_free_rx_wrapper; + sys->repl_hdlr = ipa3_replenish_rx_cache; + sys->rx_buff_sz = IPA_ODU_RX_BUFF_SZ; + } + } else if (in->client == + IPA_CLIENT_MEMCPY_DMA_ASYNC_CONS) { + IPADBG("assigning policy to client:%d", + in->client); + + sys->policy = IPA_POLICY_INTR_POLL_MODE; + INIT_WORK(&sys->work, ipa3_wq_handle_rx); + INIT_DELAYED_WORK(&sys->switch_to_intr_work, + ipa3_switch_to_intr_rx_work_func); + } else if (in->client == + IPA_CLIENT_MEMCPY_DMA_SYNC_CONS) { + IPADBG("assigning policy to client:%d", + in->client); + + sys->policy = IPA_POLICY_NOINTR_MODE; + } else if (in->client == IPA_CLIENT_ODL_DPL_CONS) { + IPADBG("assigning policy to ODL client:%d\n", + in->client); + /* Status enabling is needed for DPLv2 with + * IPA versions < 4.5. + * Dont enable ipa_status for APQ, since MDM IPA + * has IPA >= 4.5 with DPLv3. + */ + if ((ipa3_ctx->platform_type == IPA_PLAT_TYPE_APQ && + ipa3_is_mhip_offload_enabled()) || + (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_5)) + sys->ep->status.status_en = false; + else + sys->ep->status.status_en = true; + sys->policy = IPA_POLICY_INTR_POLL_MODE; + INIT_WORK(&sys->work, ipa3_wq_handle_rx); + INIT_DELAYED_WORK(&sys->switch_to_intr_work, + ipa3_switch_to_intr_rx_work_func); + INIT_DELAYED_WORK(&sys->replenish_rx_work, + ipa3_replenish_rx_work_func); + atomic_set(&sys->curr_polling_state, 0); + sys->rx_buff_sz = + IPA_GENERIC_RX_BUFF_SZ(IPA_ODL_RX_BUFF_SZ); + sys->pyld_hdlr = ipa3_odl_dpl_rx_pyld_hdlr; + sys->get_skb = ipa3_get_skb_ipa_rx; + sys->free_skb = ipa_free_skb_rx; + sys->free_rx_wrapper = ipa3_recycle_rx_wrapper; + sys->repl_hdlr = ipa3_replenish_rx_cache_recycle; + sys->rx_pool_sz = in->desc_fifo_sz / + IPA_FIFO_ELEMENT_SIZE - 1; + } else { + WARN(1, "Need to install a RX pipe hdlr\n"); + return -EINVAL; + } + } + + return 0; +} + +/** + * ipa3_tx_client_rx_notify_release() - Callback function + * which will call the user supplied callback function to + * release the skb, or release it on its own if no callback + * function was supplied + * + * @user1: [in] - Data Descriptor + * @user2: [in] - endpoint idx + * + * This notified callback is for the destination client + * This function is supplied in ipa3_tx_dp_mul + */ +static void ipa3_tx_client_rx_notify_release(void *user1, int user2) +{ + struct ipa_tx_data_desc *dd = (struct ipa_tx_data_desc *)user1; + int ep_idx = user2; + + IPADBG_LOW("Received data desc anchor:%pK\n", dd); + + atomic_inc(&ipa3_ctx->ep[ep_idx].avail_fifo_desc); + ipa3_ctx->ep[ep_idx].wstats.rx_pkts_status_rcvd++; + + /* wlan host driver waits till tx complete before unload */ + IPADBG_LOW("ep=%d fifo_desc_free_count=%d\n", + ep_idx, atomic_read(&ipa3_ctx->ep[ep_idx].avail_fifo_desc)); + IPADBG_LOW("calling client notify callback with priv:%pK\n", + ipa3_ctx->ep[ep_idx].priv); + + if (ipa3_ctx->ep[ep_idx].client_notify) { + ipa3_ctx->ep[ep_idx].client_notify(ipa3_ctx->ep[ep_idx].priv, + IPA_WRITE_DONE, (unsigned long)user1); + ipa3_ctx->ep[ep_idx].wstats.rx_hd_reply++; + } +} +/** + * ipa3_tx_client_rx_pkt_status() - Callback function + * which will call the user supplied callback function to + * increase the available fifo descriptor + * + * @user1: [in] - Data Descriptor + * @user2: [in] - endpoint idx + * + * This notified callback is for the destination client + * This function is supplied in ipa3_tx_dp_mul + */ +static void ipa3_tx_client_rx_pkt_status(void *user1, int user2) +{ + int ep_idx = user2; + + atomic_inc(&ipa3_ctx->ep[ep_idx].avail_fifo_desc); + ipa3_ctx->ep[ep_idx].wstats.rx_pkts_status_rcvd++; +} + + +/** + * ipa3_tx_dp_mul() - Data-path tx handler for multiple packets + * @src: [in] - Client that is sending data + * @ipa_tx_data_desc: [in] data descriptors from wlan + * + * this is used for to transfer data descriptors that received + * from WLAN1_PROD pipe to IPA HW + * + * The function will send data descriptors from WLAN1_PROD (one + * at a time). Will set EOT flag for last descriptor Once this send was done + * from transport point-of-view the IPA driver will get notified by the + * supplied callback - ipa_gsi_irq_tx_notify_cb() + * + * ipa_gsi_irq_tx_notify_cb will call to the user supplied callback + * + * Returns: 0 on success, negative on failure + */ +int ipa3_tx_dp_mul(enum ipa_client_type src, + struct ipa_tx_data_desc *data_desc) +{ + /* The second byte in wlan header holds qmap id */ +#define IPA_WLAN_HDR_QMAP_ID_OFFSET 1 + struct ipa_tx_data_desc *entry; + struct ipa3_sys_context *sys; + struct ipa3_desc desc[2]; + u32 num_desc, cnt; + int ep_idx; + + IPADBG_LOW("Received data desc anchor:%pK\n", data_desc); + + spin_lock_bh(&ipa3_ctx->wc_memb.ipa_tx_mul_spinlock); + + ep_idx = ipa_get_ep_mapping(src); + if (unlikely(ep_idx == -1)) { + IPAERR("dest EP does not exist.\n"); + goto fail_send; + } + IPADBG_LOW("ep idx:%d\n", ep_idx); + sys = ipa3_ctx->ep[ep_idx].sys; + + if (unlikely(ipa3_ctx->ep[ep_idx].valid == 0)) { + IPAERR("dest EP not valid.\n"); + goto fail_send; + } + sys->ep->wstats.rx_hd_rcvd++; + + /* Calculate the number of descriptors */ + num_desc = 0; + list_for_each_entry(entry, &data_desc->link, link) { + num_desc++; + } + IPADBG_LOW("Number of Data Descriptors:%d", num_desc); + + if (atomic_read(&sys->ep->avail_fifo_desc) < num_desc) { + IPAERR("Insufficient data descriptors available\n"); + goto fail_send; + } + + /* Assign callback only for last data descriptor */ + cnt = 0; + list_for_each_entry(entry, &data_desc->link, link) { + memset(desc, 0, 2 * sizeof(struct ipa3_desc)); + + IPADBG_LOW("Parsing data desc :%d\n", cnt); + cnt++; + ((u8 *)entry->pyld_buffer)[IPA_WLAN_HDR_QMAP_ID_OFFSET] = + (u8)sys->ep->cfg.meta.qmap_id; + + /* the tag field will be populated in ipa3_send() function */ + desc[0].is_tag_status = true; + desc[1].pyld = entry->pyld_buffer; + desc[1].len = entry->pyld_len; + desc[1].type = IPA_DATA_DESC_SKB; + desc[1].user1 = data_desc; + desc[1].user2 = ep_idx; + IPADBG_LOW("priv:%pK pyld_buf:0x%pK pyld_len:%d\n", + entry->priv, desc[1].pyld, desc[1].len); + + /* In case of last descriptor populate callback */ + if (cnt == num_desc) { + IPADBG_LOW("data desc:%pK\n", data_desc); + desc[1].callback = ipa3_tx_client_rx_notify_release; + } else { + desc[1].callback = ipa3_tx_client_rx_pkt_status; + } + + IPADBG_LOW("calling ipa3_send()\n"); + if (ipa3_send(sys, 2, desc, true)) { + IPAERR_RL("fail to send skb\n"); + sys->ep->wstats.rx_pkt_leak += (cnt-1); + sys->ep->wstats.rx_dp_fail++; + goto fail_send; + } + + if (atomic_read(&sys->ep->avail_fifo_desc) >= 0) + atomic_dec(&sys->ep->avail_fifo_desc); + + sys->ep->wstats.rx_pkts_rcvd++; + IPADBG_LOW("ep=%d fifo desc=%d\n", + ep_idx, atomic_read(&sys->ep->avail_fifo_desc)); + } + + sys->ep->wstats.rx_hd_processed++; + spin_unlock_bh(&ipa3_ctx->wc_memb.ipa_tx_mul_spinlock); + return 0; + +fail_send: + spin_unlock_bh(&ipa3_ctx->wc_memb.ipa_tx_mul_spinlock); + return -EFAULT; + +} + +void ipa_free_skb(struct ipa_rx_data *data) +{ + struct ipa3_rx_pkt_wrapper *rx_pkt; + + spin_lock_bh(&ipa3_ctx->wc_memb.wlan_spinlock); + + ipa3_ctx->wc_memb.total_tx_pkts_freed++; + rx_pkt = container_of(data, struct ipa3_rx_pkt_wrapper, data); + + ipa3_skb_recycle(rx_pkt->data.skb); + (void)skb_put(rx_pkt->data.skb, IPA_WLAN_RX_BUFF_SZ); + + list_add_tail(&rx_pkt->link, + &ipa3_ctx->wc_memb.wlan_comm_desc_list); + ipa3_ctx->wc_memb.wlan_comm_free_cnt++; + + spin_unlock_bh(&ipa3_ctx->wc_memb.wlan_spinlock); +} +EXPORT_SYMBOL(ipa_free_skb); + +/* Functions added to support kernel tests */ + +int ipa3_sys_setup(struct ipa_sys_connect_params *sys_in, + unsigned long *ipa_transport_hdl, + u32 *ipa_pipe_num, u32 *clnt_hdl, bool en_status) +{ + struct ipa3_ep_context *ep; + int ipa_ep_idx; + int result = -EINVAL; + + if (sys_in == NULL || clnt_hdl == NULL) { + IPAERR("NULL args\n"); + goto fail_gen; + } + + if (ipa_transport_hdl == NULL || ipa_pipe_num == NULL) { + IPAERR("NULL args\n"); + goto fail_gen; + } + if (sys_in->client >= IPA_CLIENT_MAX) { + IPAERR("bad parm client:%d\n", sys_in->client); + goto fail_gen; + } + + ipa_ep_idx = ipa_get_ep_mapping(sys_in->client); + if (ipa_ep_idx == -1) { + IPAERR("Invalid client :%d\n", sys_in->client); + goto fail_gen; + } + + ep = &ipa3_ctx->ep[ipa_ep_idx]; + IPA_ACTIVE_CLIENTS_INC_EP(sys_in->client); + + if (ep->valid == 1) { + if (sys_in->client != IPA_CLIENT_APPS_WAN_PROD) { + IPAERR("EP %d already allocated\n", ipa_ep_idx); + goto fail_and_disable_clocks; + } else { + if (ipa3_cfg_ep_hdr(ipa_ep_idx, + &sys_in->ipa_ep_cfg.hdr)) { + IPAERR("fail to configure hdr prop of EP %d\n", + ipa_ep_idx); + result = -EFAULT; + goto fail_and_disable_clocks; + } + if (ipa3_cfg_ep_hdr_ext(ipa_ep_idx, + &sys_in->ipa_ep_cfg.hdr_ext)) { + IPAERR("fail config hdr_ext prop of EP %d\n", + ipa_ep_idx); + result = -EFAULT; + goto fail_and_disable_clocks; + } + if (ipa3_cfg_ep_cfg(ipa_ep_idx, + &sys_in->ipa_ep_cfg.cfg)) { + IPAERR("fail to configure cfg prop of EP %d\n", + ipa_ep_idx); + result = -EFAULT; + goto fail_and_disable_clocks; + } + IPAERR("client %d (ep: %d) overlay ok sys=%pK\n", + sys_in->client, ipa_ep_idx, ep->sys); + ep->client_notify = sys_in->notify; + ep->priv = sys_in->priv; + *clnt_hdl = ipa_ep_idx; + if (!ep->keep_ipa_awake) + IPA_ACTIVE_CLIENTS_DEC_EP(sys_in->client); + + return 0; + } + } + + memset(ep, 0, offsetof(struct ipa3_ep_context, sys)); + + ep->valid = 1; + ep->client = sys_in->client; + ep->client_notify = sys_in->notify; + ep->priv = sys_in->priv; + ep->keep_ipa_awake = true; + if (en_status) { + ep->status.status_en = true; + ep->status.status_ep = ipa_ep_idx; + } + + result = ipa3_enable_data_path(ipa_ep_idx); + if (result) { + IPAERR("enable data path failed res=%d clnt=%d.\n", + result, ipa_ep_idx); + goto fail_gen2; + } + + if (!ep->skip_ep_cfg) { + if (ipa3_cfg_ep(ipa_ep_idx, &sys_in->ipa_ep_cfg)) { + IPAERR("fail to configure EP.\n"); + goto fail_gen2; + } + if (ipa3_cfg_ep_status(ipa_ep_idx, &ep->status)) { + IPAERR("fail to configure status of EP.\n"); + goto fail_gen2; + } + IPADBG("ep configuration successful\n"); + } else { + IPADBG("skipping ep configuration\n"); + } + + *clnt_hdl = ipa_ep_idx; + + *ipa_pipe_num = ipa_ep_idx; + *ipa_transport_hdl = ipa3_ctx->gsi_dev_hdl; + + if (!ep->keep_ipa_awake) + IPA_ACTIVE_CLIENTS_DEC_EP(sys_in->client); + + ipa3_ctx->skip_ep_cfg_shadow[ipa_ep_idx] = ep->skip_ep_cfg; + IPADBG("client %d (ep: %d) connected sys=%pK\n", sys_in->client, + ipa_ep_idx, ep->sys); + + return 0; + +fail_gen2: +fail_and_disable_clocks: + IPA_ACTIVE_CLIENTS_DEC_EP(sys_in->client); +fail_gen: + return result; +} +EXPORT_SYMBOL(ipa3_sys_setup); + +int ipa3_sys_teardown(u32 clnt_hdl) +{ + struct ipa3_ep_context *ep; + + if (clnt_hdl >= ipa3_ctx->ipa_num_pipes || + ipa3_ctx->ep[clnt_hdl].valid == 0) { + IPAERR("bad parm(Either endpoint or client hdl invalid)\n"); + return -EINVAL; + } + + ep = &ipa3_ctx->ep[clnt_hdl]; + + if (!ep->keep_ipa_awake) + IPA_ACTIVE_CLIENTS_INC_EP(ipa3_get_client_mapping(clnt_hdl)); + + ipa3_disable_data_path(clnt_hdl); + ep->valid = 0; + + IPA_ACTIVE_CLIENTS_DEC_EP(ipa3_get_client_mapping(clnt_hdl)); + + IPADBG("client (ep: %d) disconnected\n", clnt_hdl); + + return 0; +} +EXPORT_SYMBOL(ipa3_sys_teardown); + +int ipa3_sys_update_gsi_hdls(u32 clnt_hdl, unsigned long gsi_ch_hdl, + unsigned long gsi_ev_hdl) +{ + struct ipa3_ep_context *ep; + + if (clnt_hdl >= ipa3_ctx->ipa_num_pipes || + ipa3_ctx->ep[clnt_hdl].valid == 0) { + IPAERR("bad parm(Either endpoint or client hdl invalid)\n"); + return -EINVAL; + } + + ep = &ipa3_ctx->ep[clnt_hdl]; + + ep->gsi_chan_hdl = gsi_ch_hdl; + ep->gsi_evt_ring_hdl = gsi_ev_hdl; + + return 0; +} +EXPORT_SYMBOL(ipa3_sys_update_gsi_hdls); + +static void ipa_gsi_evt_ring_err_cb(struct gsi_evt_err_notify *notify) +{ + switch (notify->evt_id) { + case GSI_EVT_OUT_OF_BUFFERS_ERR: + IPAERR("Got GSI_EVT_OUT_OF_BUFFERS_ERR\n"); + break; + case GSI_EVT_OUT_OF_RESOURCES_ERR: + IPAERR("Got GSI_EVT_OUT_OF_RESOURCES_ERR\n"); + break; + case GSI_EVT_UNSUPPORTED_INTER_EE_OP_ERR: + IPAERR("Got GSI_EVT_UNSUPPORTED_INTER_EE_OP_ERR\n"); + break; + case GSI_EVT_EVT_RING_EMPTY_ERR: + IPAERR("Got GSI_EVT_EVT_RING_EMPTY_ERR\n"); + break; + default: + IPAERR("Unexpected err evt: %d\n", notify->evt_id); + } +} + +static void ipa_gsi_chan_err_cb(struct gsi_chan_err_notify *notify) +{ + switch (notify->evt_id) { + case GSI_CHAN_INVALID_TRE_ERR: + IPAERR("Got GSI_CHAN_INVALID_TRE_ERR\n"); + break; + case GSI_CHAN_NON_ALLOCATED_EVT_ACCESS_ERR: + IPAERR("Got GSI_CHAN_NON_ALLOCATED_EVT_ACCESS_ERR\n"); + break; + case GSI_CHAN_OUT_OF_BUFFERS_ERR: + IPAERR("Got GSI_CHAN_OUT_OF_BUFFERS_ERR\n"); + break; + case GSI_CHAN_OUT_OF_RESOURCES_ERR: + IPAERR("Got GSI_CHAN_OUT_OF_RESOURCES_ERR\n"); + break; + case GSI_CHAN_UNSUPPORTED_INTER_EE_OP_ERR: + IPAERR("Got GSI_CHAN_UNSUPPORTED_INTER_EE_OP_ERR\n"); + break; + case GSI_CHAN_HWO_1_ERR: + IPAERR("Got GSI_CHAN_HWO_1_ERR\n"); + break; + default: + IPAERR("Unexpected err evt: %d\n", notify->evt_id); + } +} + +static void ipa_gsi_irq_tx_notify_cb(struct gsi_chan_xfer_notify *notify) +{ + struct ipa3_tx_pkt_wrapper *tx_pkt; + struct ipa3_sys_context *sys; + + IPADBG_LOW("event %d notified\n", notify->evt_id); + + switch (notify->evt_id) { + case GSI_CHAN_EVT_EOT: + atomic_set(&ipa3_ctx->transport_pm.eot_activity, 1); + tx_pkt = notify->xfer_user_data; + tx_pkt->xmit_done = true; + sys = tx_pkt->sys; + if (sys->tx_poll) { + if (!atomic_read(&sys->curr_polling_state)) { + /* dummy vote to prevent NoC error */ + if(IPA_ACTIVE_CLIENTS_INC_EP_NO_BLOCK( + sys->ep->client)) { + IPAERR_RL("clk off, event likely handled in NAPI contxt"); + return; + } + /* put the producer event ring into polling mode */ + gsi_config_channel_mode(sys->ep->gsi_chan_hdl, + GSI_CHAN_MODE_POLL); + atomic_set(&sys->curr_polling_state, 1); + __ipa3_update_curr_poll_state(sys->ep->client, 1); + napi_schedule(&tx_pkt->sys->napi_tx); + } + } else if (ipa_net_initialized && sys->napi_tx_enable) { + if(!atomic_cmpxchg(&tx_pkt->sys->in_napi_context, 0, 1)) + napi_schedule(&tx_pkt->sys->napi_tx); + } else { + atomic_inc(&tx_pkt->sys->xmit_eot_cnt); + tasklet_schedule(&tx_pkt->sys->tasklet); + } + break; + default: + IPAERR("received unexpected event id %d\n", notify->evt_id); + } +} + +void __ipa_gsi_irq_rx_scedule_poll(struct ipa3_sys_context *sys) +{ + bool clk_off = true; + enum ipa_client_type client_type; + + atomic_set(&sys->curr_polling_state, 1); + __ipa3_update_curr_poll_state(sys->ep->client, 1); + + ipa3_inc_acquire_wakelock(); + /* + * Mark client as WAN_COAL_CONS only as + * NAPI only use sys of WAN_COAL_CONS. + */ + if (IPA_CLIENT_IS_WAN_CONS(sys->ep->client)) + client_type = IPA_CLIENT_APPS_WAN_COAL_CONS; + else if (IPA_CLIENT_IS_LAN_CONS(sys->ep->client)) + client_type = IPA_CLIENT_APPS_LAN_COAL_CONS; + else + client_type = sys->ep->client; + /* + * Have race condition to use PM on poll to isr + * switch. Use the active no block instead + * where we would have ref counts. + */ + if ((ipa_net_initialized && sys->napi_obj) || + IPA_CLIENT_IS_LOW_LAT_CONS(sys->ep->client) || + (sys->ep->client == IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_CONS)) + clk_off = IPA_ACTIVE_CLIENTS_INC_EP_NO_BLOCK(client_type); + if (!clk_off && ipa_net_initialized && sys->napi_obj) { + trace_ipa3_napi_schedule(sys->ep->client); + napi_schedule(sys->napi_obj); + } else if (!clk_off && + (sys->ep->client == IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_CONS)) { + trace_ipa3_napi_schedule(sys->ep->client); + napi_schedule(&sys->napi_rx); + } else if (!clk_off && + IPA_CLIENT_IS_LOW_LAT_CONS(sys->ep->client)) { + tasklet_schedule(&sys->tasklet); + } else + queue_work(sys->wq, &sys->work); +} + +static void ipa_gsi_irq_rx_notify_cb(struct gsi_chan_xfer_notify *notify) +{ + struct ipa3_sys_context *sys; + + if (!notify) { + IPAERR("gsi notify is NULL.\n"); + return; + } + IPADBG_LOW("event %d notified\n", notify->evt_id); + + sys = (struct ipa3_sys_context *)notify->chan_user_data; + + /* + * In suspend just before stopping the channel possible to receive + * the IEOB interrupt and xfer pointer will not be processed in this + * mode and moving channel poll mode. In resume after starting the + * channel will receive the IEOB interrupt and xfer pointer will be + * overwritten. To avoid this process all data in polling context. + */ + sys->ep->xfer_notify_valid = false; + sys->ep->xfer_notify = *notify; + + switch (notify->evt_id) { + case GSI_CHAN_EVT_EOT: + case GSI_CHAN_EVT_EOB: + atomic_set(&ipa3_ctx->transport_pm.eot_activity, 1); + if (!atomic_read(&sys->curr_polling_state)) { + /* put the gsi channel into polling mode */ + gsi_config_channel_mode(sys->ep->gsi_chan_hdl, + GSI_CHAN_MODE_POLL); + __ipa_gsi_irq_rx_scedule_poll(sys); + } + break; + default: + IPAERR("received unexpected event id %d\n", notify->evt_id); + } +} + +static void ipa_dma_gsi_irq_rx_notify_cb(struct gsi_chan_xfer_notify *notify) +{ + struct ipa3_sys_context *sys; + + if (!notify) { + IPAERR("gsi notify is NULL.\n"); + return; + } + IPADBG_LOW("event %d notified\n", notify->evt_id); + + sys = (struct ipa3_sys_context *)notify->chan_user_data; + if (sys->ep->client == IPA_CLIENT_MEMCPY_DMA_SYNC_CONS) { + IPAERR("IRQ_RX Callback was called for DMA_SYNC_CONS.\n"); + return; + } + + sys->ep->xfer_notify_valid = false; + sys->ep->xfer_notify = *notify; + + switch (notify->evt_id) { + case GSI_CHAN_EVT_EOT: + if (!atomic_read(&sys->curr_polling_state)) { + /* put the gsi channel into polling mode */ + gsi_config_channel_mode(sys->ep->gsi_chan_hdl, + GSI_CHAN_MODE_POLL); + ipa3_inc_acquire_wakelock(); + atomic_set(&sys->curr_polling_state, 1); + queue_work(sys->wq, &sys->work); + } + break; + default: + IPAERR("received unexpected event id %d\n", notify->evt_id); + } +} + +void ipa3_dealloc_common_event_ring(void) +{ + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + gsi_dealloc_evt_ring(ipa3_ctx->gsi_evt_comm_hdl); + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); +} + +int ipa3_alloc_common_event_ring(void) +{ + struct gsi_evt_ring_props gsi_evt_ring_props; + dma_addr_t evt_dma_addr = 0; + dma_addr_t evt_rp_dma_addr = 0; + int result; + + memset(&gsi_evt_ring_props, 0, sizeof(gsi_evt_ring_props)); + gsi_evt_ring_props.intf = GSI_EVT_CHTYPE_GPI_EV; + gsi_evt_ring_props.intr = GSI_INTR_IRQ; + gsi_evt_ring_props.re_size = GSI_EVT_RING_RE_SIZE_16B; + + gsi_evt_ring_props.ring_len = IPA_COMMON_EVENT_RING_SIZE; + + gsi_evt_ring_props.ring_base_vaddr = + dma_alloc_coherent(ipa3_ctx->pdev, + gsi_evt_ring_props.ring_len, &evt_dma_addr, GFP_KERNEL); + if (!gsi_evt_ring_props.ring_base_vaddr) { + IPAERR("fail to dma alloc %u bytes\n", + gsi_evt_ring_props.ring_len); + return -ENOMEM; + } + gsi_evt_ring_props.ring_base_addr = evt_dma_addr; + gsi_evt_ring_props.int_modt = 0; + gsi_evt_ring_props.int_modc = 1; /* moderation comes from channel*/ + + if (ipa3_ctx->ipa_gpi_event_rp_ddr) { + gsi_evt_ring_props.rp_update_vaddr = + dma_alloc_coherent(ipa3_ctx->pdev, + IPA_GSI_EVENT_RP_SIZE, + &evt_rp_dma_addr, GFP_KERNEL); + if (!gsi_evt_ring_props.rp_update_vaddr) { + IPAERR("fail to dma alloc %u bytes\n", + IPA_GSI_EVENT_RP_SIZE); + result = -ENOMEM; + goto fail_alloc_rp; + } + gsi_evt_ring_props.rp_update_addr = evt_rp_dma_addr; + } else { + gsi_evt_ring_props.rp_update_addr = 0; + } + + gsi_evt_ring_props.exclusive = false; + gsi_evt_ring_props.err_cb = ipa_gsi_evt_ring_err_cb; + gsi_evt_ring_props.user_data = NULL; + + result = gsi_alloc_evt_ring(&gsi_evt_ring_props, + ipa3_ctx->gsi_dev_hdl, &ipa3_ctx->gsi_evt_comm_hdl); + if (result) { + IPAERR("gsi_alloc_evt_ring failed %d\n", result); + goto fail_alloc_evt_ring; + } + ipa3_ctx->gsi_evt_comm_ring_rem = IPA_COMMON_EVENT_RING_SIZE; + + return 0; +fail_alloc_evt_ring: + if (gsi_evt_ring_props.rp_update_vaddr) { + dma_free_coherent(ipa3_ctx->pdev, IPA_GSI_EVENT_RP_SIZE, + gsi_evt_ring_props.rp_update_vaddr, + evt_rp_dma_addr); + } +fail_alloc_rp: + dma_free_coherent(ipa3_ctx->pdev, gsi_evt_ring_props.ring_len, + gsi_evt_ring_props.ring_base_vaddr, + evt_dma_addr); + return result; +} + +static int ipa_gsi_setup_channel(struct ipa_sys_connect_params *in, + struct ipa3_ep_context *ep) +{ + u32 ring_size; + int result; + gfp_t mem_flag = GFP_KERNEL; + u32 wan_coal_ep_id, lan_coal_ep_id; + + if (IPA_CLIENT_IS_WAN_CONS(in->client) || + IPA_CLIENT_IS_LAN_CONS(in->client) || + in->client == IPA_CLIENT_APPS_WAN_LOW_LAT_CONS || + in->client == IPA_CLIENT_APPS_WAN_LOW_LAT_PROD || + in->client == IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_CONS || + in->client == IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_PROD || + in->client == IPA_CLIENT_APPS_WAN_PROD) + mem_flag = GFP_ATOMIC; + + if (!ep) { + IPAERR("EP context is empty\n"); + return -EINVAL; + } + + /* + * GSI ring length is calculated based on the desc_fifo_sz + * which was meant to define the BAM desc fifo. GSI descriptors + * are 16B as opposed to 8B for BAM. + */ + ring_size = 2 * in->desc_fifo_sz; + ep->gsi_evt_ring_hdl = ~0; + if (ep->sys && ep->sys->use_comm_evt_ring) { + if (ipa3_ctx->gsi_evt_comm_ring_rem < ring_size) { + IPAERR("not enough space in common event ring\n"); + IPAERR("available: %d needed: %d\n", + ipa3_ctx->gsi_evt_comm_ring_rem, + ring_size); + WARN_ON(1); + return -EFAULT; + } + ipa3_ctx->gsi_evt_comm_ring_rem -= (ring_size); + ep->gsi_evt_ring_hdl = ipa3_ctx->gsi_evt_comm_hdl; + } else if (in->client == IPA_CLIENT_APPS_WAN_COAL_CONS) { + result = ipa_gsi_setup_event_ring(ep, + IPA_COMMON_EVENT_RING_SIZE, mem_flag); + if (result) + goto fail_setup_event_ring; + + } else if (in->client == IPA_CLIENT_APPS_WAN_CONS && + IPA_CLIENT_IS_MAPPED_VALID(IPA_CLIENT_APPS_WAN_COAL_CONS, wan_coal_ep_id)) { + IPADBG("Wan consumer pipe configured\n"); + result = ipa_gsi_setup_coal_def_channel(in, ep, + &ipa3_ctx->ep[wan_coal_ep_id]); + if (result) { + IPAERR("Failed to setup default coal GSI channel\n"); + goto fail_setup_event_ring; + } + return result; + } else if (in->client == IPA_CLIENT_APPS_LAN_COAL_CONS) { + result = ipa_gsi_setup_event_ring(ep, + IPA_COMMON_EVENT_RING_SIZE, mem_flag); + if (result) + goto fail_setup_event_ring; + } else if (in->client == IPA_CLIENT_APPS_LAN_CONS && + IPA_CLIENT_IS_MAPPED_VALID(IPA_CLIENT_APPS_LAN_COAL_CONS, lan_coal_ep_id)) { + IPADBG("Lan consumer pipe configured\n"); + result = ipa_gsi_setup_coal_def_channel(in, ep, + &ipa3_ctx->ep[lan_coal_ep_id]); + if (result) { + IPAERR("Failed to setup default coal GSI channel\n"); + goto fail_setup_event_ring; + } + return result; + } else if ((ep->sys && ep->sys->policy != IPA_POLICY_NOINTR_MODE) || + IPA_CLIENT_IS_CONS(ep->client)) { + result = ipa_gsi_setup_event_ring(ep, ring_size, mem_flag); + if (result) + goto fail_setup_event_ring; + } + result = ipa_gsi_setup_transfer_ring(ep, ring_size, + ep->sys, mem_flag); + if (result) + goto fail_setup_transfer_ring; + + if (ep->client == IPA_CLIENT_MEMCPY_DMA_SYNC_CONS) + gsi_config_channel_mode(ep->gsi_chan_hdl, + GSI_CHAN_MODE_POLL); + return 0; + +fail_setup_transfer_ring: + if (ep->gsi_mem_info.evt_ring_base_vaddr) + dma_free_coherent(ipa3_ctx->pdev, ep->gsi_mem_info.evt_ring_len, + ep->gsi_mem_info.evt_ring_base_vaddr, + ep->gsi_mem_info.evt_ring_base_addr); +fail_setup_event_ring: + IPAERR("Return with err: %d\n", result); + return result; +} + +static void *ipa3_ring_alloc(struct device *dev, size_t size, + dma_addr_t *dma_handle, gfp_t gfp) +{ + void *va_addr; + int retry_cnt = 0; + +alloc: + va_addr = dma_alloc_coherent(dev, size, dma_handle, gfp); + if (!va_addr) { + if (retry_cnt < IPA_MEM_ALLOC_RETRY) { + IPADBG("Fail to dma alloc retry cnt = %d\n", + retry_cnt); + retry_cnt++; + goto alloc; + } + + if (gfp == GFP_ATOMIC) { + gfp = GFP_KERNEL; + goto alloc; + } + IPAERR("fail to dma alloc %u bytes\n", size); + ipa_assert(); + } + + return va_addr; +} + +static int ipa_gsi_setup_event_ring(struct ipa3_ep_context *ep, + u32 ring_size, gfp_t mem_flag) +{ + struct gsi_evt_ring_props gsi_evt_ring_props; + dma_addr_t evt_dma_addr; + dma_addr_t evt_rp_dma_addr; + int result; + + evt_dma_addr = 0; + evt_rp_dma_addr = 0; + memset(&gsi_evt_ring_props, 0, sizeof(gsi_evt_ring_props)); + gsi_evt_ring_props.intf = GSI_EVT_CHTYPE_GPI_EV; + if ((ipa3_ctx->gsi_msi_addr) && + (ep->client == IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_CONS || + ep->client == IPA_CLIENT_APPS_WAN_LOW_LAT_CONS)) + gsi_evt_ring_props.intr = GSI_INTR_MSI; // intvec chosen dynamically. + else gsi_evt_ring_props.intr = GSI_INTR_IRQ; + gsi_evt_ring_props.re_size = GSI_EVT_RING_RE_SIZE_16B; + gsi_evt_ring_props.ring_len = ring_size; + gsi_evt_ring_props.ring_base_vaddr = + ipa3_ring_alloc(ipa3_ctx->pdev, gsi_evt_ring_props.ring_len, + &evt_dma_addr, mem_flag); + gsi_evt_ring_props.ring_base_addr = evt_dma_addr; + + /* copy mem info */ + ep->gsi_mem_info.evt_ring_len = gsi_evt_ring_props.ring_len; + ep->gsi_mem_info.evt_ring_base_addr = + gsi_evt_ring_props.ring_base_addr; + ep->gsi_mem_info.evt_ring_base_vaddr = + gsi_evt_ring_props.ring_base_vaddr; + + if (ep->sys && ep->sys->napi_obj) { + gsi_evt_ring_props.int_modt = IPA_GSI_EVT_RING_INT_MODT; + gsi_evt_ring_props.int_modc = IPA_GSI_EVT_RING_INT_MODC; + } else { + gsi_evt_ring_props.int_modt = IPA_GSI_EVT_RING_INT_MODT; + gsi_evt_ring_props.int_modc = 1; + } + + if ((ep->sys && ep->sys->ext_ioctl_v2) && + ((ep->client == IPA_CLIENT_APPS_WAN_PROD) || + (ep->client == IPA_CLIENT_APPS_WAN_CONS) || + (ep->client == IPA_CLIENT_APPS_WAN_COAL_CONS) || + (ep->client == IPA_CLIENT_APPS_WAN_LOW_LAT_PROD) || + (ep->client == IPA_CLIENT_APPS_WAN_LOW_LAT_CONS) || + (ep->client == IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_PROD) || + (ep->client == IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_CONS))) { + gsi_evt_ring_props.int_modt = ep->sys->int_modt; + gsi_evt_ring_props.int_modc = ep->sys->int_modc; + } + + IPADBG("client=%d moderation threshold cycles=%u cnt=%u\n", + ep->client, + gsi_evt_ring_props.int_modt, + gsi_evt_ring_props.int_modc); + if (ipa3_ctx->ipa_gpi_event_rp_ddr) { + gsi_evt_ring_props.rp_update_vaddr = + dma_alloc_coherent(ipa3_ctx->pdev, + IPA_GSI_EVENT_RP_SIZE, + &evt_rp_dma_addr, GFP_KERNEL); + if (!gsi_evt_ring_props.rp_update_vaddr) { + IPAERR("fail to dma alloc %u bytes\n", + IPA_GSI_EVENT_RP_SIZE); + result = -ENOMEM; + goto fail_alloc_rp; + } + gsi_evt_ring_props.rp_update_addr = evt_rp_dma_addr; + } else { + gsi_evt_ring_props.rp_update_addr = 0; + } + + /* copy mem info */ + ep->gsi_mem_info.evt_ring_rp_addr = + gsi_evt_ring_props.rp_update_addr; + ep->gsi_mem_info.evt_ring_rp_vaddr = + gsi_evt_ring_props.rp_update_vaddr; + + gsi_evt_ring_props.exclusive = true; + gsi_evt_ring_props.err_cb = ipa_gsi_evt_ring_err_cb; + gsi_evt_ring_props.user_data = NULL; + + result = gsi_alloc_evt_ring(&gsi_evt_ring_props, + ipa3_ctx->gsi_dev_hdl, &ep->gsi_evt_ring_hdl); + if (result != GSI_STATUS_SUCCESS) + goto fail_alloc_evt_ring; + + return 0; + +fail_alloc_evt_ring: + if (gsi_evt_ring_props.rp_update_vaddr) { + dma_free_coherent(ipa3_ctx->pdev, IPA_GSI_EVENT_RP_SIZE, + gsi_evt_ring_props.rp_update_vaddr, + evt_rp_dma_addr); + ep->gsi_mem_info.evt_ring_rp_addr = 0; + ep->gsi_mem_info.evt_ring_rp_vaddr = 0; + } +fail_alloc_rp: + if (ep->gsi_mem_info.evt_ring_base_vaddr) + dma_free_coherent(ipa3_ctx->pdev, ep->gsi_mem_info.evt_ring_len, + ep->gsi_mem_info.evt_ring_base_vaddr, + ep->gsi_mem_info.evt_ring_base_addr); + IPAERR("Return with err: %d\n", result); + return result; +} + +static int ipa_gsi_setup_transfer_ring(struct ipa3_ep_context *ep, + u32 ring_size, struct ipa3_sys_context *user_data, gfp_t mem_flag) +{ + dma_addr_t dma_addr; + union __packed gsi_channel_scratch ch_scratch; + struct gsi_chan_props gsi_channel_props; + const struct ipa_gsi_ep_config *gsi_ep_info; + int result; + + memset(&gsi_channel_props, 0, sizeof(gsi_channel_props)); + if (IPA_CLIENT_IS_APPS_COAL_CONS(ep->client)) + gsi_channel_props.prot = GSI_CHAN_PROT_GCI; + else + gsi_channel_props.prot = GSI_CHAN_PROT_GPI; + if (IPA_CLIENT_IS_PROD(ep->client)) { + gsi_channel_props.dir = GSI_CHAN_DIR_TO_GSI; + if(ep->client == IPA_CLIENT_APPS_WAN_PROD || + ep->client == IPA_CLIENT_APPS_LAN_PROD || + ep->client == IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_PROD) + gsi_channel_props.tx_poll = ipa3_ctx->tx_poll; + else + gsi_channel_props.tx_poll = false; + } else { + gsi_channel_props.dir = GSI_CHAN_DIR_FROM_GSI; + if (ep->sys) + gsi_channel_props.max_re_expected = ep->sys->rx_pool_sz; + } + + gsi_ep_info = ipa_get_gsi_ep_info(ep->client); + if (!gsi_ep_info) { + IPAERR("Failed getting GSI EP info for client=%d\n", + ep->client); + result = -EINVAL; + goto fail_get_gsi_ep_info; + } else { + gsi_channel_props.ch_id = gsi_ep_info->ipa_gsi_chan_num; + } + + gsi_channel_props.evt_ring_hdl = ep->gsi_evt_ring_hdl; + gsi_channel_props.re_size = GSI_CHAN_RE_SIZE_16B; + gsi_channel_props.ring_len = ring_size; + + gsi_channel_props.ring_base_vaddr = + ipa3_ring_alloc(ipa3_ctx->pdev, gsi_channel_props.ring_len, + &dma_addr, mem_flag); + gsi_channel_props.ring_base_addr = dma_addr; + + /* copy mem info */ + ep->gsi_mem_info.chan_ring_len = gsi_channel_props.ring_len; + ep->gsi_mem_info.chan_ring_base_addr = + gsi_channel_props.ring_base_addr; + ep->gsi_mem_info.chan_ring_base_vaddr = + gsi_channel_props.ring_base_vaddr; + + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_0) + gsi_channel_props.use_db_eng = GSI_CHAN_DIRECT_MODE; + else + gsi_channel_props.use_db_eng = GSI_CHAN_DB_MODE; + gsi_channel_props.max_prefetch = GSI_ONE_PREFETCH_SEG; + if (ep->client == IPA_CLIENT_APPS_CMD_PROD) + gsi_channel_props.low_weight = IPA_GSI_MAX_CH_LOW_WEIGHT; + else + gsi_channel_props.low_weight = 1; + gsi_channel_props.db_in_bytes = 1; + /* Configure Low Latency Mode. */ + if (ep->client == IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_PROD || + ep->client == IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_CONS) + gsi_channel_props.low_latency_en = 1; + gsi_channel_props.prefetch_mode = gsi_ep_info->prefetch_mode; + gsi_channel_props.empty_lvl_threshold = gsi_ep_info->prefetch_threshold; + gsi_channel_props.chan_user_data = user_data; + gsi_channel_props.err_cb = ipa_gsi_chan_err_cb; + if (IPA_CLIENT_IS_PROD(ep->client)) + gsi_channel_props.xfer_cb = ipa_gsi_irq_tx_notify_cb; + else + gsi_channel_props.xfer_cb = ipa_gsi_irq_rx_notify_cb; + if (IPA_CLIENT_IS_MEMCPY_DMA_CONS(ep->client)) + gsi_channel_props.xfer_cb = ipa_dma_gsi_irq_rx_notify_cb; + + if (IPA_CLIENT_IS_CONS(ep->client)) + gsi_channel_props.cleanup_cb = free_rx_pkt; + + /* overwrite the cleanup_cb for page recycling */ + if (ipa3_ctx->ipa_wan_skb_page && + (IPA_CLIENT_IS_WAN_CONS(ep->client) || + (ep->client == IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_CONS))) + gsi_channel_props.cleanup_cb = free_rx_page; + + result = gsi_alloc_channel(&gsi_channel_props, ipa3_ctx->gsi_dev_hdl, + &ep->gsi_chan_hdl); + if (result != GSI_STATUS_SUCCESS) { + IPAERR("Failed to alloc GSI chan.\n"); + goto fail_alloc_channel; + } + + memset(&ch_scratch, 0, sizeof(ch_scratch)); + /* + * Update scratch for MCS smart prefetch: + * Starting IPA4.5, smart prefetch implemented by H/W. + * At IPA 4.0/4.1/4.2, we do not use MCS smart prefetch + * so keep the fields zero. + */ + if (ipa3_ctx->ipa_hw_type < IPA_HW_v4_0) { + ch_scratch.gpi.max_outstanding_tre = + gsi_ep_info->ipa_if_tlv * GSI_CHAN_RE_SIZE_16B; + ch_scratch.gpi.outstanding_threshold = + 2 * GSI_CHAN_RE_SIZE_16B; + } + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_5) + ch_scratch.gpi.dl_nlo_channel = 0; + result = gsi_write_channel_scratch(ep->gsi_chan_hdl, ch_scratch); + if (result != GSI_STATUS_SUCCESS) { + IPAERR("failed to write scratch %d\n", result); + goto fail_write_channel_scratch; + } + return 0; + +fail_write_channel_scratch: + if (gsi_dealloc_channel(ep->gsi_chan_hdl) + != GSI_STATUS_SUCCESS) { + IPAERR("Failed to dealloc GSI chan.\n"); + WARN_ON(1); + } +fail_alloc_channel: + dma_free_coherent(ipa3_ctx->pdev, ep->gsi_mem_info.chan_ring_len, + ep->gsi_mem_info.chan_ring_base_vaddr, + ep->gsi_mem_info.chan_ring_base_addr); +fail_get_gsi_ep_info: + if (ep->gsi_evt_ring_hdl != ~0) { + gsi_dealloc_evt_ring(ep->gsi_evt_ring_hdl); + ep->gsi_evt_ring_hdl = ~0; + } + return result; +} + +static int ipa_gsi_setup_coal_def_channel(struct ipa_sys_connect_params *in, + struct ipa3_ep_context *ep, struct ipa3_ep_context *coal_ep) +{ + u32 ring_size; + int result; + + ring_size = 2 * in->desc_fifo_sz; + + /* copy event ring handle */ + ep->gsi_evt_ring_hdl = coal_ep->gsi_evt_ring_hdl; + + result = ipa_gsi_setup_transfer_ring(ep, ring_size, + coal_ep->sys, GFP_ATOMIC); + if (result) { + if (ep->gsi_mem_info.evt_ring_base_vaddr) + dma_free_coherent(ipa3_ctx->pdev, + ep->gsi_mem_info.chan_ring_len, + ep->gsi_mem_info.chan_ring_base_vaddr, + ep->gsi_mem_info.chan_ring_base_addr); + IPAERR("Destroying WAN_COAL_CONS evt_ring"); + if (ep->gsi_evt_ring_hdl != ~0) { + gsi_dealloc_evt_ring(ep->gsi_evt_ring_hdl); + ep->gsi_evt_ring_hdl = ~0; + } + IPAERR("Return with err: %d\n", result); + return result; + } + return 0; +} + +static int ipa_populate_tag_field(struct ipa3_desc *desc, + struct ipa3_tx_pkt_wrapper *tx_pkt, + struct ipahal_imm_cmd_pyld **tag_pyld_ret) +{ + struct ipahal_imm_cmd_pyld *tag_pyld; + struct ipahal_imm_cmd_ip_packet_tag_status tag_cmd = {0}; + + /* populate tag field only if it is NULL */ + if (desc->pyld == NULL) { + tag_cmd.tag = pointer_to_tag_wa(tx_pkt); + tag_pyld = ipahal_construct_imm_cmd( + IPA_IMM_CMD_IP_PACKET_TAG_STATUS, &tag_cmd, true); + if (unlikely(!tag_pyld)) { + IPAERR("Failed to construct ip_packet_tag_status\n"); + return -EFAULT; + } + /* + * This is for 32-bit pointer, will need special + * handling if 64-bit pointer is used + */ + IPADBG_LOW("tx_pkt sent in tag: 0x%pK\n", tx_pkt); + desc->pyld = tag_pyld->data; + desc->opcode = tag_pyld->opcode; + desc->len = tag_pyld->len; + desc->user1 = tag_pyld; + desc->type = IPA_IMM_CMD_DESC; + desc->callback = ipa3_tag_destroy_imm; + + *tag_pyld_ret = tag_pyld; + } + return 0; +} + +static int ipa_poll_gsi_pkt(struct ipa3_sys_context *sys, + struct gsi_chan_xfer_notify *notify) +{ + int unused_var; + + return ipa_poll_gsi_n_pkt(sys, notify, 1, &unused_var); +} + + +static int ipa_poll_gsi_n_pkt(struct ipa3_sys_context *sys, + struct gsi_chan_xfer_notify *notify, + int expected_num, int *actual_num) +{ + int ret; + int idx = 0; + int poll_num = 0; + + /* Parameters validity isn't checked as this is a static function */ + + if (sys->ep->xfer_notify_valid) { + *notify = sys->ep->xfer_notify; + sys->ep->xfer_notify_valid = false; + idx++; + } + if (expected_num == idx) { + *actual_num = idx; + return GSI_STATUS_SUCCESS; + } + + ret = gsi_poll_n_channel(sys->ep->gsi_chan_hdl, + ¬ify[idx], expected_num - idx, &poll_num); + if (ret == GSI_STATUS_POLL_EMPTY) { + if (idx) { + *actual_num = idx; + return GSI_STATUS_SUCCESS; + } + *actual_num = 0; + return ret; + } else if (ret != GSI_STATUS_SUCCESS) { + if (idx) { + *actual_num = idx; + return GSI_STATUS_SUCCESS; + } + *actual_num = 0; + IPAERR("Poll channel err: %d\n", ret); + return ret; + } + + *actual_num = idx + poll_num; + return ret; +} + +/** + * ipa3_lan_rx_poll() - Poll the LAN rx packets from IPA HW. + * This function is executed in the softirq context + * + * if input budget is zero, the driver switches back to + * interrupt mode. + * + * return number of polled packets, on error 0(zero) + */ +int ipa3_lan_rx_poll(u32 clnt_hdl, int weight) +{ + struct ipa3_ep_context *ep; + int ret; + int cnt = 0; + int num = 0; + int i; + int remain_aggr_weight; + + if (unlikely(clnt_hdl >= ipa3_ctx->ipa_num_pipes || + ipa3_ctx->ep[clnt_hdl].valid == 0)) { + IPAERR("bad param 0x%x\n", clnt_hdl); + return cnt; + } + remain_aggr_weight = weight / IPA_LAN_AGGR_PKT_CNT; + if (unlikely(remain_aggr_weight > IPA_LAN_NAPI_MAX_FRAMES)) { + IPAERR("NAPI weight is higher than expected\n"); + IPAERR("expected %d got %d\n", + IPA_LAN_NAPI_MAX_FRAMES, remain_aggr_weight); + return cnt; + } + ep = &ipa3_ctx->ep[clnt_hdl]; + +start_poll: + /* + * it is guaranteed we already have clock here. + * This is mainly for clock scaling. + */ + ipa_pm_activate(ep->sys->pm_hdl); + while (remain_aggr_weight > 0 && + atomic_read(&ep->sys->curr_polling_state)) { + atomic_set(&ipa3_ctx->transport_pm.eot_activity, 1); + ret = ipa_poll_gsi_n_pkt(ep->sys, g_lan_rx_notify, + remain_aggr_weight, &num); + if (ret) + break; + + for (i = 0; i < num; i++) { + if (IPA_CLIENT_IS_MEMCPY_DMA_CONS(ep->client)) + ipa3_dma_memcpy_notify(ep->sys); + else if (IPA_CLIENT_IS_WLAN_CONS(ep->client)) + ipa3_wlan_wq_rx_common(ep->sys, g_lan_rx_notify + i); + else + ipa3_wq_rx_common(ep->sys, g_lan_rx_notify + i); + } + + remain_aggr_weight -= num; + if (ep->sys->len == 0) { + if (remain_aggr_weight == 0) + cnt--; + break; + } + } + cnt += weight - remain_aggr_weight * IPA_LAN_AGGR_PKT_CNT; + if (cnt < weight) { + napi_complete(ep->sys->napi_obj); + ret = ipa3_rx_switch_to_intr_mode(ep->sys); + if (ret == -GSI_STATUS_PENDING_IRQ && + napi_reschedule(ep->sys->napi_obj)) + goto start_poll; + + IPA_ACTIVE_CLIENTS_DEC_EP_NO_BLOCK(ep->client); + } + + return cnt; +} + +/** + * ipa3_rx_poll() - Poll the WAN rx packets from IPA HW. This + * function is exectued in the softirq context + * + * if input budget is zero, the driver switches back to + * interrupt mode. + * + * return number of polled packets, on error 0(zero) + */ +int ipa3_rx_poll(u32 clnt_hdl, int weight) +{ + struct ipa3_ep_context *ep; + struct ipa3_sys_context *wan_def_sys; + int ret; + int cnt = 0; + int num = 0; + int remain_aggr_weight; + int ipa_ep_idx; + struct ipa_active_client_logging_info log; + static struct gsi_chan_xfer_notify notify[IPA_WAN_NAPI_MAX_FRAMES]; + + IPA_ACTIVE_CLIENTS_PREP_SPECIAL(log, "NAPI"); + + if (clnt_hdl >= ipa3_ctx->ipa_num_pipes || + ipa3_ctx->ep[clnt_hdl].valid == 0) { + IPAERR("bad parm 0x%x\n", clnt_hdl); + return cnt; + } + + ipa_ep_idx = ipa_get_ep_mapping( + IPA_CLIENT_APPS_WAN_CONS); + if (ipa_ep_idx == + IPA_EP_NOT_ALLOCATED) { + IPAERR("Invalid client.\n"); + return cnt; + } + ep = &ipa3_ctx->ep[clnt_hdl]; + + trace_ipa3_napi_poll_entry(ep->client); + + wan_def_sys = ipa3_ctx->ep[ipa_ep_idx].sys; + remain_aggr_weight = weight / ipa3_ctx->ipa_wan_aggr_pkt_cnt; + if (remain_aggr_weight > IPA_WAN_NAPI_MAX_FRAMES) { + IPAERR("NAPI weight is higher than expected\n"); + IPAERR("expected %d got %d\n", + IPA_WAN_NAPI_MAX_FRAMES, remain_aggr_weight); + return -EINVAL; + } + + ep->sys->common_sys->napi_sort_page_thrshld_cnt++; +start_poll: + /* + * it is guaranteed we already have clock here. + * This is mainly for clock scaling. + */ + ipa_pm_activate(ep->sys->pm_hdl); + while (remain_aggr_weight > 0 && + atomic_read(&ep->sys->curr_polling_state)) { + atomic_set(&ipa3_ctx->transport_pm.eot_activity, 1); + if (ipa3_ctx->enable_napi_chain) { + ret = ipa_poll_gsi_n_pkt(ep->sys, notify, + remain_aggr_weight, &num); + } else { + ret = ipa_poll_gsi_n_pkt(ep->sys, notify, + 1, &num); + } + if (ret) + break; + + trace_ipa3_napi_rx_poll_num(ep->client, num); + ipa3_rx_napi_chain(ep->sys, notify, num); + remain_aggr_weight -= num; + + trace_ipa3_napi_rx_poll_cnt(ep->client, ep->sys->len); + if (ep->sys->len == 0) { + if (remain_aggr_weight == 0) + cnt--; + break; + } + } + cnt += weight - remain_aggr_weight * ipa3_ctx->ipa_wan_aggr_pkt_cnt; + /* call repl_hdlr before napi_reschedule / napi_complete */ + ep->sys->repl_hdlr(ep->sys); + wan_def_sys->repl_hdlr(wan_def_sys); + /* Scheduling WAN and COAL collect stats work wueue */ + queue_delayed_work(ipa3_ctx->collect_recycle_stats_wq, + &ipa3_collect_default_coal_recycle_stats_wq_work, msecs_to_jiffies(10)); + /* When not able to replenish enough descriptors, keep in polling + * mode, wait for napi-poll and replenish again. + */ + if (cnt < weight && ep->sys->len > IPA_DEFAULT_SYS_YELLOW_WM && + wan_def_sys->len > IPA_DEFAULT_SYS_YELLOW_WM) { + napi_complete(ep->sys->napi_obj); + ret = ipa3_rx_switch_to_intr_mode(ep->sys); + if (ret == -GSI_STATUS_PENDING_IRQ && + napi_reschedule(ep->sys->napi_obj)) + goto start_poll; + IPA_ACTIVE_CLIENTS_DEC_EP_NO_BLOCK(ep->client); + } else { + cnt = weight; + IPADBG_LOW("Client = %d not replenished free descripotrs\n", + ep->client); + } + trace_ipa3_napi_poll_exit(ep->client); + return cnt; +} + +static unsigned long tag_to_pointer_wa(uint64_t tag) +{ + return 0xFFFF000000000000 | (unsigned long) tag; +} + +static uint64_t pointer_to_tag_wa(struct ipa3_tx_pkt_wrapper *tx_pkt) +{ + u16 temp; + /* Add the check but it might have throughput issue */ + if (BITS_PER_LONG == 64) { + temp = (u16) (~((unsigned long) tx_pkt & + 0xFFFF000000000000) >> 48); + if (temp) { + IPAERR("The 16 prefix is not all 1s (%pK)\n", + tx_pkt); + /* + * We need all addresses starting at 0xFFFF to + * pass it to HW. + */ + ipa_assert(); + } + } + return (unsigned long)tx_pkt & 0x0000FFFFFFFFFFFF; +} + +/** + * ipa_gsi_ch20_wa() - software workaround for IPA GSI channel 20 + * + * A hardware limitation requires to avoid using GSI physical channel 20. + * This function allocates GSI physical channel 20 and holds it to prevent + * others to use it. + * + * Return codes: 0 on success, negative on failure + */ +int ipa_gsi_ch20_wa(void) +{ + struct gsi_chan_props gsi_channel_props; + dma_addr_t dma_addr; + int result; + int i; + unsigned long chan_hdl[IPA_GSI_CH_20_WA_NUM_CH_TO_ALLOC]; + unsigned long chan_hdl_to_keep; + + + memset(&gsi_channel_props, 0, sizeof(gsi_channel_props)); + gsi_channel_props.prot = GSI_CHAN_PROT_GPI; + gsi_channel_props.dir = GSI_CHAN_DIR_TO_GSI; + gsi_channel_props.evt_ring_hdl = ~0; + gsi_channel_props.re_size = GSI_CHAN_RE_SIZE_16B; + gsi_channel_props.ring_len = 4 * gsi_channel_props.re_size; + gsi_channel_props.ring_base_vaddr = + dma_alloc_coherent(ipa3_ctx->pdev, gsi_channel_props.ring_len, + &dma_addr, 0); + gsi_channel_props.ring_base_addr = dma_addr; + + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_0) + gsi_channel_props.use_db_eng = GSI_CHAN_DIRECT_MODE; + else + gsi_channel_props.use_db_eng = GSI_CHAN_DB_MODE; + + gsi_channel_props.db_in_bytes = 1; + gsi_channel_props.max_prefetch = GSI_ONE_PREFETCH_SEG; + gsi_channel_props.low_weight = 1; + gsi_channel_props.err_cb = ipa_gsi_chan_err_cb; + gsi_channel_props.xfer_cb = ipa_gsi_irq_tx_notify_cb; + + /* first allocate channels up to channel 20 */ + for (i = 0; i < IPA_GSI_CH_20_WA_NUM_CH_TO_ALLOC; i++) { + gsi_channel_props.ch_id = i; + result = gsi_alloc_channel(&gsi_channel_props, + ipa3_ctx->gsi_dev_hdl, + &chan_hdl[i]); + if (result != GSI_STATUS_SUCCESS) { + IPAERR("failed to alloc channel %d err %d\n", + i, result); + return result; + } + } + + /* allocate channel 20 */ + gsi_channel_props.ch_id = IPA_GSI_CH_20_WA_VIRT_CHAN; + result = gsi_alloc_channel(&gsi_channel_props, ipa3_ctx->gsi_dev_hdl, + &chan_hdl_to_keep); + if (result != GSI_STATUS_SUCCESS) { + IPAERR("failed to alloc channel %d err %d\n", + i, result); + return result; + } + + /* release all other channels */ + for (i = 0; i < IPA_GSI_CH_20_WA_NUM_CH_TO_ALLOC; i++) { + result = gsi_dealloc_channel(chan_hdl[i]); + if (result != GSI_STATUS_SUCCESS) { + IPAERR("failed to dealloc channel %d err %d\n", + i, result); + return result; + } + } + + /* DMA memory shall not be freed as it is used by channel 20 */ + return 0; +} + +/** + * ipa_adjust_ra_buff_base_sz() + * + * Return value: the largest power of two which is smaller + * than the input value + */ +static u32 ipa_adjust_ra_buff_base_sz(u32 aggr_byte_limit) +{ + aggr_byte_limit += IPA_MTU; + aggr_byte_limit += IPA_GENERIC_RX_BUFF_LIMIT; + aggr_byte_limit--; + aggr_byte_limit |= aggr_byte_limit >> 1; + aggr_byte_limit |= aggr_byte_limit >> 2; + aggr_byte_limit |= aggr_byte_limit >> 4; + aggr_byte_limit |= aggr_byte_limit >> 8; + aggr_byte_limit |= aggr_byte_limit >> 16; + aggr_byte_limit++; + return aggr_byte_limit >> 1; +} + +static void ipa3_tasklet_rx_notify(unsigned long data) +{ + struct ipa3_sys_context *sys; + struct sk_buff *rx_skb; + struct gsi_chan_xfer_notify notify; + int ret; + + sys = (struct ipa3_sys_context *)data; + atomic_set(&ipa3_ctx->transport_pm.eot_activity, 1); +start_poll: + /* + * it is guaranteed we already have clock here. + * This is mainly for clock scaling. + */ + ipa_pm_activate(sys->pm_hdl); + while (1) { + ret = ipa_poll_gsi_pkt(sys, ¬ify); + if (ret) + break; + rx_skb = handle_skb_completion(¬ify, true, NULL); + if (rx_skb) { + sys->pyld_hdlr(rx_skb, sys); + sys->repl_hdlr(sys); + } + } + + ret = ipa3_rx_switch_to_intr_mode(sys); + if (ret == -GSI_STATUS_PENDING_IRQ) + goto start_poll; + IPA_ACTIVE_CLIENTS_DEC_EP_NO_BLOCK(sys->ep->client); +} + +static int ipa3_rmnet_ll_rx_poll(struct napi_struct *napi_rx, int budget) +{ + struct ipa3_sys_context *sys = container_of(napi_rx, + struct ipa3_sys_context, napi_rx); + int remain_aggr_weight; + int ret; + int cnt = 0; + int num = 0; + struct ipa_active_client_logging_info log; + static struct gsi_chan_xfer_notify notify[IPA_WAN_NAPI_MAX_FRAMES]; + + IPA_ACTIVE_CLIENTS_PREP_SPECIAL(log, "NAPI_LL"); + + remain_aggr_weight = budget / ipa3_ctx->ipa_wan_aggr_pkt_cnt; + if (remain_aggr_weight > IPA_WAN_NAPI_MAX_FRAMES) { + IPAERR("NAPI weight is higher than expected\n"); + IPAERR("expected %d got %d\n", + IPA_WAN_NAPI_MAX_FRAMES, remain_aggr_weight); + return -EINVAL; + } + + sys->napi_sort_page_thrshld_cnt++; + + trace_ipa3_napi_poll_entry(sys->ep->client); +start_poll: + /* + * it is guaranteed we already have clock here. + * This is mainly for clock scaling. + */ + ipa_pm_activate(sys->pm_hdl); + while (remain_aggr_weight > 0 && + atomic_read(&sys->curr_polling_state)) { + atomic_set(&ipa3_ctx->transport_pm.eot_activity, 1); + ret = ipa_poll_gsi_n_pkt(sys, notify, + remain_aggr_weight, &num); + if (ret) + break; + + trace_ipa3_napi_rx_poll_num(sys->ep->client, num); + ipa3_rx_napi_chain(sys, notify, num); + remain_aggr_weight -= num; + + trace_ipa3_napi_rx_poll_cnt(sys->ep->client, sys->len); + if (sys->len == 0) { + if (remain_aggr_weight == 0) + cnt--; + break; + } + } + cnt += budget - remain_aggr_weight * ipa3_ctx->ipa_wan_aggr_pkt_cnt; + /* call repl_hdlr before napi_reschedule / napi_complete */ + sys->repl_hdlr(sys); + /* Scheduling RMNET LOW LAT DATA collect stats work queue */ + queue_delayed_work(ipa3_ctx->collect_recycle_stats_wq, + &ipa3_collect_low_lat_data_recycle_stats_wq_work, msecs_to_jiffies(10)); + /* When not able to replenish enough descriptors, keep in polling + * mode, wait for napi-poll and replenish again. + */ + if (cnt < budget && (sys->len > IPA_DEFAULT_SYS_YELLOW_WM)) { + napi_complete(napi_rx); + ret = ipa3_rx_switch_to_intr_mode(sys); + if (ret == -GSI_STATUS_PENDING_IRQ && + napi_reschedule(napi_rx)) + goto start_poll; + IPA_ACTIVE_CLIENTS_DEC_EP_NO_BLOCK(sys->ep->client); + } else { + cnt = budget; + IPADBG_LOW("Client = %d not replenished free descripotrs\n", + sys->ep->client); + } + return cnt; +} diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_dt_replacement.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_dt_replacement.c new file mode 100644 index 0000000000..d54df6409b --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_dt_replacement.c @@ -0,0 +1,874 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include "ipa_i.h" +#include "ipa_emulation_stubs.h" + +# undef strsame +# define strsame(x, y) \ + (!strcmp((x), (y))) + +/* + * The following enum values used to index tables below. + */ +enum dtsi_index_e { + DTSI_INDEX_3_5_1 = 0, + DTSI_INDEX_4_0 = 1, + DTSI_INDEX_4_5 = 2, +}; + +struct dtsi_replacement_u32 { + char *key; + u32 value; +}; + +struct dtsi_replacement_u32_table { + struct dtsi_replacement_u32 *p_table; + u32 num_entries; +}; + +struct dtsi_replacement_bool { + char *key; + bool value; +}; + +struct dtsi_replacement_bool_table { + struct dtsi_replacement_bool *p_table; + u32 num_entries; +}; + +struct dtsi_replacement_u32_array { + char *key; + u32 *p_value; + u32 num_elements; +}; + +struct dtsi_replacement_u32_array_table { + struct dtsi_replacement_u32_array *p_table; + u32 num_entries; +}; + +struct dtsi_replacement_resource_table { + struct resource *p_table; + u32 num_entries; +}; + +/* + * Any of the data below with _4_5 in the name represent data taken + * from the 4.5 dtsi file. + * + * Any of the data below with _4_0 in the name represent data taken + * from the 4.0 dtsi file. + * + * Any of the data below with _3_5_1 in the name represent data taken + * from the 3.5.1 dtsi file. + */ +static struct dtsi_replacement_bool ipa3_plat_drv_bool_4_5[] = { + {"qcom,use-ipa-tethering-bridge", true}, + {"qcom,modem-cfg-emb-pipe-flt", true}, + {"qcom,ipa-wdi2", false}, + {"qcom,use-64-bit-dma-mask", false}, + {"qcom,bandwidth-vote-for-ipa", true}, + {"qcom,skip-uc-pipe-reset", false}, + {"qcom,tethered-flow-control", false}, + {"qcom,use-rg10-limitation-mitigation", false}, + {"qcom,do-not-use-ch-gsi-20", false}, + {"qcom,use-ipa-pm", true}, + {"qcom,register-collection-on-crash", true}, + {"qcom,testbus-collection-on-crash", true}, + {"qcom,non-tn-collection-on-crash", true}, +}; + +static struct dtsi_replacement_bool ipa3_plat_drv_bool_4_0[] = { + {"qcom,use-ipa-tethering-bridge", true}, + {"qcom,modem-cfg-emb-pipe-flt", true}, + {"qcom,ipa-wdi2", true}, + {"qcom,use-64-bit-dma-mask", false}, + {"qcom,bandwidth-vote-for-ipa", false}, + {"qcom,skip-uc-pipe-reset", false}, + {"qcom,tethered-flow-control", true}, + {"qcom,use-rg10-limitation-mitigation", false}, + {"qcom,do-not-use-ch-gsi-20", false}, + {"qcom,use-ipa-pm", false}, + {"qcom,register-collection-on-crash", true}, + {"qcom,testbus-collection-on-crash", true}, + {"qcom,non-tn-collection-on-crash", true}, +}; + +static struct dtsi_replacement_bool ipa3_plat_drv_bool_3_5_1[] = { + {"qcom,use-ipa-tethering-bridge", true}, + {"qcom,modem-cfg-emb-pipe-flt", true}, + {"qcom,ipa-wdi2", true}, + {"qcom,use-64-bit-dma-mask", false}, + {"qcom,bandwidth-vote-for-ipa", true}, + {"qcom,skip-uc-pipe-reset", false}, + {"qcom,tethered-flow-control", false}, + {"qcom,use-rg10-limitation-mitigation", false}, + {"qcom,do-not-use-ch-gsi-20", false}, + {"qcom,use-ipa-pm", false}, + {"qcom,register-collection-on-crash", true}, + {"qcom,testbus-collection-on-crash", true}, + {"qcom,non-tn-collection-on-crash", true}, +}; + +static struct dtsi_replacement_bool_table +ipa3_plat_drv_bool_table[] = { + { ipa3_plat_drv_bool_3_5_1, + ARRAY_SIZE(ipa3_plat_drv_bool_3_5_1) }, + { ipa3_plat_drv_bool_4_0, + ARRAY_SIZE(ipa3_plat_drv_bool_4_0) }, + { ipa3_plat_drv_bool_4_5, + ARRAY_SIZE(ipa3_plat_drv_bool_4_5) }, +}; + +static struct dtsi_replacement_u32 ipa3_plat_drv_u32_4_5[] = { + {"qcom,ipa-hw-ver", IPA_HW_v4_5}, + {"qcom,ipa-hw-mode", 3}, + {"qcom,wan-rx-ring-size", 192}, + {"qcom,lan-rx-ring-size", 192}, + {"qcom,ee", 0}, + {"qcom,msm-bus,num-cases", 5}, + {"emulator-bar0-offset", 0x01C00000}, + {"qcom,entire-ipa-block-size", 0x00100000}, +}; + +static struct dtsi_replacement_u32 ipa3_plat_drv_u32_4_0[] = { + {"qcom,ipa-hw-ver", IPA_HW_v4_0}, + {"qcom,ipa-hw-mode", 3}, + {"qcom,wan-rx-ring-size", 192}, + {"qcom,lan-rx-ring-size", 192}, + {"qcom,ee", 0}, + {"emulator-bar0-offset", 0x01C00000}, + {"qcom,entire-ipa-block-size", 0x00100000}, +}; + +static struct dtsi_replacement_u32 ipa3_plat_drv_u32_3_5_1[] = { + {"qcom,ipa-hw-ver", IPA_HW_v3_5_1}, + {"qcom,ipa-hw-mode", 3}, + {"qcom,wan-rx-ring-size", 192}, + {"qcom,lan-rx-ring-size", 192}, + {"qcom,ee", 0}, + {"emulator-bar0-offset", 0x01C00000}, + {"qcom,entire-ipa-block-size", 0x00100000}, +}; + +static struct dtsi_replacement_u32_table ipa3_plat_drv_u32_table[] = { + { ipa3_plat_drv_u32_3_5_1, + ARRAY_SIZE(ipa3_plat_drv_u32_3_5_1) }, + { ipa3_plat_drv_u32_4_0, + ARRAY_SIZE(ipa3_plat_drv_u32_4_0) }, + { ipa3_plat_drv_u32_4_5, + ARRAY_SIZE(ipa3_plat_drv_u32_4_5) }, +}; + +static u32 mhi_event_ring_id_limits_array_4_5[] = { + 9, 10 +}; + +static u32 mhi_event_ring_id_limits_array_4_0[] = { + 9, 10 +}; + +static u32 mhi_event_ring_id_limits_array_3_5_1[] = { + IPA_MHI_GSI_EVENT_RING_ID_START, IPA_MHI_GSI_EVENT_RING_ID_END +}; + +static u32 ipa_tz_unlock_reg_array_4_5[] = { + 0x04043583c, 0x00001000 +}; + +static u32 ipa_throughput_thresh_array_4_5[] = { + 310, 600, 1000 +}; + +static u32 ipa_tz_unlock_reg_array_4_0[] = { + 0x04043583c, 0x00001000 +}; + +static u32 ipa_tz_unlock_reg_array_3_5_1[] = { + 0x04043583c, 0x00001000 +}; + +struct dtsi_replacement_u32_array ipa3_plat_drv_u32_array_4_5[] = { + {"qcom,mhi-event-ring-id-limits", + mhi_event_ring_id_limits_array_4_5, + ARRAY_SIZE(mhi_event_ring_id_limits_array_4_5) }, + {"qcom,ipa-tz-unlock-reg", + ipa_tz_unlock_reg_array_4_5, + ARRAY_SIZE(ipa_tz_unlock_reg_array_4_5) }, + {"qcom,throughput-threshold", + ipa_throughput_thresh_array_4_5, + ARRAY_SIZE(ipa_throughput_thresh_array_4_5) }, +}; + +struct dtsi_replacement_u32_array ipa3_plat_drv_u32_array_4_0[] = { + {"qcom,mhi-event-ring-id-limits", + mhi_event_ring_id_limits_array_4_0, + ARRAY_SIZE(mhi_event_ring_id_limits_array_4_0) }, + {"qcom,ipa-tz-unlock-reg", + ipa_tz_unlock_reg_array_4_0, + ARRAY_SIZE(ipa_tz_unlock_reg_array_4_0) }, +}; + +struct dtsi_replacement_u32_array ipa3_plat_drv_u32_array_3_5_1[] = { + {"qcom,mhi-event-ring-id-limits", + mhi_event_ring_id_limits_array_3_5_1, + ARRAY_SIZE(mhi_event_ring_id_limits_array_3_5_1) }, + {"qcom,ipa-tz-unlock-reg", + ipa_tz_unlock_reg_array_3_5_1, + ARRAY_SIZE(ipa_tz_unlock_reg_array_3_5_1) }, +}; + +struct dtsi_replacement_u32_array_table +ipa3_plat_drv_u32_array_table[] = { + { ipa3_plat_drv_u32_array_3_5_1, + ARRAY_SIZE(ipa3_plat_drv_u32_array_3_5_1) }, + { ipa3_plat_drv_u32_array_4_0, + ARRAY_SIZE(ipa3_plat_drv_u32_array_4_0) }, + { ipa3_plat_drv_u32_array_4_5, + ARRAY_SIZE(ipa3_plat_drv_u32_array_4_5) }, +}; + +#define INTCTRL_OFFSET 0x083C0000 +#define INTCTRL_SIZE 0x00000110 + +#define IPA_BASE_OFFSET_4_5 0x01e00000 +#define IPA_BASE_SIZE_4_5 0x000c0000 +#define GSI_BASE_OFFSET_4_5 0x01e04000 +#define GSI_BASE_SIZE_4_5 0x00023000 + +struct resource ipa3_plat_drv_resource_4_5[] = { + /* + * PLEASE NOTE: The following offset values below ("ipa-base", + * "gsi-base", and "intctrl-base") are used to calculate + * offsets relative to the PCI BAR0 address provided by the + * PCI probe. After their use to calculate the offsets, they + * are not used again, since PCI ultimately dictates where + * things live. + */ + { + IPA_BASE_OFFSET_4_5, + (IPA_BASE_OFFSET_4_5 + IPA_BASE_SIZE_4_5), + "ipa-base", + IORESOURCE_MEM, + 0, + NULL, + NULL, + NULL + }, + + { + GSI_BASE_OFFSET_4_5, + (GSI_BASE_OFFSET_4_5 + GSI_BASE_SIZE_4_5), + "gsi-base", + IORESOURCE_MEM, + 0, + NULL, + NULL, + NULL + }, + + /* + * The following entry is germane only to the emulator + * environment. It is needed to locate the emulator's PCI + * interrupt controller... + */ + { + INTCTRL_OFFSET, + (INTCTRL_OFFSET + INTCTRL_SIZE), + "intctrl-base", + IORESOURCE_MEM, + 0, + NULL, + NULL, + NULL + }, + + { + IPA_PIPE_MEM_START_OFST, + (IPA_PIPE_MEM_START_OFST + IPA_PIPE_MEM_SIZE), + "ipa-pipe-mem", + IORESOURCE_MEM, + 0, + NULL, + NULL, + NULL + }, + + { + 0, + 0, + "gsi-irq", + IORESOURCE_IRQ, + 0, + NULL, + NULL, + NULL + }, + + { + 0, + 0, + "ipa-irq", + IORESOURCE_IRQ, + 0, + NULL, + NULL, + NULL + }, +}; + +#define IPA_BASE_OFFSET_4_0 0x01e00000 +#define IPA_BASE_SIZE_4_0 0x00034000 +#define GSI_BASE_OFFSET_4_0 0x01e04000 +#define GSI_BASE_SIZE_4_0 0x00028000 + +struct resource ipa3_plat_drv_resource_4_0[] = { + /* + * PLEASE NOTE: The following offset values below ("ipa-base", + * "gsi-base", and "intctrl-base") are used to calculate + * offsets relative to the PCI BAR0 address provided by the + * PCI probe. After their use to calculate the offsets, they + * are not used again, since PCI ultimately dictates where + * things live. + */ + { + IPA_BASE_OFFSET_4_0, + (IPA_BASE_OFFSET_4_0 + IPA_BASE_SIZE_4_0), + "ipa-base", + IORESOURCE_MEM, + 0, + NULL, + NULL, + NULL + }, + + { + GSI_BASE_OFFSET_4_0, + (GSI_BASE_OFFSET_4_0 + GSI_BASE_SIZE_4_0), + "gsi-base", + IORESOURCE_MEM, + 0, + NULL, + NULL, + NULL + }, + + /* + * The following entry is germane only to the emulator + * environment. It is needed to locate the emulator's PCI + * interrupt controller... + */ + { + INTCTRL_OFFSET, + (INTCTRL_OFFSET + INTCTRL_SIZE), + "intctrl-base", + IORESOURCE_MEM, + 0, + NULL, + NULL, + NULL + }, + + { + IPA_PIPE_MEM_START_OFST, + (IPA_PIPE_MEM_START_OFST + IPA_PIPE_MEM_SIZE), + "ipa-pipe-mem", + IORESOURCE_MEM, + 0, + NULL, + NULL, + NULL + }, + + { + 0, + 0, + "gsi-irq", + IORESOURCE_IRQ, + 0, + NULL, + NULL, + NULL + }, + + { + 0, + 0, + "ipa-irq", + IORESOURCE_IRQ, + 0, + NULL, + NULL, + NULL + }, +}; + +#define IPA_BASE_OFFSET_3_5_1 0x01e00000 +#define IPA_BASE_SIZE_3_5_1 0x00034000 +#define GSI_BASE_OFFSET_3_5_1 0x01e04000 +#define GSI_BASE_SIZE_3_5_1 0x0002c000 + +struct resource ipa3_plat_drv_resource_3_5_1[] = { + /* + * PLEASE NOTE: The following offset values below ("ipa-base", + * "gsi-base", and "intctrl-base") are used to calculate + * offsets relative to the PCI BAR0 address provided by the + * PCI probe. After their use to calculate the offsets, they + * are not used again, since PCI ultimately dictates where + * things live. + */ + { + IPA_BASE_OFFSET_3_5_1, + (IPA_BASE_OFFSET_3_5_1 + IPA_BASE_SIZE_3_5_1), + "ipa-base", + IORESOURCE_MEM, + 0, + NULL, + NULL, + NULL + }, + + { + GSI_BASE_OFFSET_3_5_1, + (GSI_BASE_OFFSET_3_5_1 + GSI_BASE_SIZE_3_5_1), + "gsi-base", + IORESOURCE_MEM, + 0, + NULL, + NULL, + NULL + }, + + /* + * The following entry is germane only to the emulator + * environment. It is needed to locate the emulator's PCI + * interrupt controller... + */ + { + INTCTRL_OFFSET, + (INTCTRL_OFFSET + INTCTRL_SIZE), + "intctrl-base", + IORESOURCE_MEM, + 0, + NULL, + NULL, + NULL + }, + + { + IPA_PIPE_MEM_START_OFST, + (IPA_PIPE_MEM_START_OFST + IPA_PIPE_MEM_SIZE), + "ipa-pipe-mem", + IORESOURCE_MEM, + 0, + NULL, + NULL, + NULL + }, + + { + 0, + 0, + "gsi-irq", + IORESOURCE_IRQ, + 0, + NULL, + NULL, + NULL + }, + + { + 0, + 0, + "ipa-irq", + IORESOURCE_IRQ, + 0, + NULL, + NULL, + NULL + }, +}; + +struct dtsi_replacement_resource_table +ipa3_plat_drv_resource_table[] = { + { ipa3_plat_drv_resource_3_5_1, + ARRAY_SIZE(ipa3_plat_drv_resource_3_5_1) }, + { ipa3_plat_drv_resource_4_0, + ARRAY_SIZE(ipa3_plat_drv_resource_4_0) }, + { ipa3_plat_drv_resource_4_5, + ARRAY_SIZE(ipa3_plat_drv_resource_4_5) }, +}; + +/* + * The following code uses the data above... + */ +static u32 emulator_type_to_index(void) +{ + /* + * Use the input parameter to the IPA driver loadable module, + * which specifies the type of hardware the driver is running + * on. + */ + u32 index = DTSI_INDEX_4_0; + uint emulation_type = ipa3_get_emulation_type(); + + switch (emulation_type) { + case IPA_HW_v3_5_1: + index = DTSI_INDEX_3_5_1; + break; + case IPA_HW_v4_0: + index = DTSI_INDEX_4_0; + break; + case IPA_HW_v4_5: + index = DTSI_INDEX_4_5; + break; + default: + break; + } + + IPADBG("emulation_type(%u) emulation_index(%u)\n", + emulation_type, index); + + return index; +} + +/* From include/linux/of.h */ +/** + * emulator_of_property_read_bool - Find from a property + * @np: device node from which the property value is to be read. + * @propname: name of the property to be searched. + * + * Search for a property in a device node. + * Returns true if the property exists false otherwise. + */ +bool emulator_of_property_read_bool( + const struct device_node *np, + const char *propname) +{ + u16 i; + u32 index; + struct dtsi_replacement_bool *ipa3_plat_drv_boolP; + + /* + * Get the index for the type of hardware we're running on. + * This is used as a table index. + */ + index = emulator_type_to_index(); + if (index >= ARRAY_SIZE(ipa3_plat_drv_bool_table)) { + IPADBG( + "Did not find ipa3_plat_drv_bool_table for index %u\n", + index); + return false; + } + + ipa3_plat_drv_boolP = + ipa3_plat_drv_bool_table[index].p_table; + + for (i = 0; + i < ipa3_plat_drv_bool_table[index].num_entries; + i++) { + if (strsame(ipa3_plat_drv_boolP[i].key, propname)) { + IPADBG( + "Found value %u for propname %s index %u\n", + ipa3_plat_drv_boolP[i].value, + propname, + index); + return ipa3_plat_drv_boolP[i].value; + } + } + + IPADBG("Did not find match for propname %s index %u\n", + propname, + index); + + return false; +} + +/* From include/linux/of.h */ +int emulator_of_property_read_u32( + const struct device_node *np, + const char *propname, + u32 *out_value) +{ + u16 i; + u32 index; + struct dtsi_replacement_u32 *ipa3_plat_drv_u32P; + + /* + * Get the index for the type of hardware we're running on. + * This is used as a table index. + */ + index = emulator_type_to_index(); + if (index >= ARRAY_SIZE(ipa3_plat_drv_u32_table)) { + IPADBG( + "Did not find ipa3_plat_drv_u32_table for index %u\n", + index); + return false; + } + + ipa3_plat_drv_u32P = + ipa3_plat_drv_u32_table[index].p_table; + + for (i = 0; + i < ipa3_plat_drv_u32_table[index].num_entries; + i++) { + if (strsame(ipa3_plat_drv_u32P[i].key, propname)) { + *out_value = ipa3_plat_drv_u32P[i].value; + IPADBG( + "Found value %u for propname %s index %u\n", + ipa3_plat_drv_u32P[i].value, + propname, + index); + return 0; + } + } + + IPADBG("Did not find match for propname %s index %u\n", + propname, + index); + + return -EINVAL; +} + +/* From include/linux/of.h */ +/** + * emulator_of_property_read_u32_array - Find and read an array of 32 + * bit integers from a property. + * + * @np: device node from which the property value is to be read. + * @propname: name of the property to be searched. + * @out_values: pointer to return value, modified only if return value is 0. + * @sz: number of array elements to read + * + * Search for a property in a device node and read 32-bit value(s) from + * it. Returns 0 on success, -EINVAL if the property does not exist, + * -ENODATA if property does not have a value, and -EOVERFLOW if the + * property data isn't large enough. + * + * The out_values is modified only if a valid u32 value can be decoded. + */ +int emulator_of_property_read_u32_array( + const struct device_node *np, + const char *propname, + u32 *out_values, + size_t sz) +{ + u16 i; + u32 index; + struct dtsi_replacement_u32_array *u32_arrayP; + + /* + * Get the index for the type of hardware we're running on. + * This is used as a table index. + */ + index = emulator_type_to_index(); + if (index >= ARRAY_SIZE(ipa3_plat_drv_u32_array_table)) { + IPADBG( + "Did not find ipa3_plat_drv_u32_array_table for index %u\n", + index); + return false; + } + + u32_arrayP = + ipa3_plat_drv_u32_array_table[index].p_table; + for (i = 0; + i < ipa3_plat_drv_u32_array_table[index].num_entries; + i++) { + if (strsame( + u32_arrayP[i].key, propname)) { + u32 num_elements = + u32_arrayP[i].num_elements; + u32 *p_element = + &u32_arrayP[i].p_value[0]; + size_t j = 0; + + if (num_elements > sz) { + IPAERR( + "Found array of %u values for propname %s; only room for %u elements in copy buffer\n", + num_elements, + propname, + (unsigned int) sz); + return -EOVERFLOW; + } + + while (j++ < num_elements) + *out_values++ = *p_element++; + + IPADBG( + "Found array of values starting with %u for propname %s index %u\n", + u32_arrayP[i].p_value[0], + propname, + index); + + return 0; + } + } + + IPADBG("Did not find match for propname %s index %u\n", + propname, + index); + + return -EINVAL; +} + +/* From drivers/base/platform.c */ +/** + * emulator_platform_get_resource_byname - get a resource for a device by name + * @dev: platform device + * @type: resource type + * @name: resource name + */ +struct resource *emulator_platform_get_resource_byname( + struct platform_device *dev, + unsigned int type, + const char *name) +{ + u16 i; + u32 index; + struct resource *ipa3_plat_drv_resourceP; + + /* + * Get the index for the type of hardware we're running on. + * This is used as a table index. + */ + index = emulator_type_to_index(); + if (index >= ARRAY_SIZE(ipa3_plat_drv_resource_table)) { + IPADBG( + "Did not find ipa3_plat_drv_resource_table for index %u\n", + index); + return false; + } + + ipa3_plat_drv_resourceP = + ipa3_plat_drv_resource_table[index].p_table; + for (i = 0; + i < ipa3_plat_drv_resource_table[index].num_entries; + i++) { + struct resource *r = &ipa3_plat_drv_resourceP[i]; + + if (type == resource_type(r) && strsame(r->name, name)) { + IPADBG( + "Found start 0x%x size %u for name %s index %u\n", + (unsigned int) (r->start), + (unsigned int) (resource_size(r)), + name, + index); + return r; + } + } + + IPADBG("Did not find match for name %s index %u\n", + name, + index); + + return NULL; +} + +/* From drivers/of/base.c */ +/** + * emulator_of_property_count_elems_of_size - Count the number of + * elements in a property + * + * @np: device node from which the property value is to + * be read. Not used. + * @propname: name of the property to be searched. + * @elem_size: size of the individual element + * + * Search for a property and count the number of elements of size + * elem_size in it. Returns number of elements on success, -EINVAL if + * the property does not exist or its length does not match a multiple + * of elem_size and -ENODATA if the property does not have a value. + */ +int emulator_of_property_count_elems_of_size( + const struct device_node *np, + const char *propname, + int elem_size) +{ + u32 index; + + /* + * Get the index for the type of hardware we're running on. + * This is used as a table index. + */ + index = emulator_type_to_index(); + + /* + * Use elem_size to determine which table to search for the + * specified property name + */ + if (elem_size == sizeof(u32)) { + u16 i; + struct dtsi_replacement_u32_array *u32_arrayP; + + if (index >= ARRAY_SIZE(ipa3_plat_drv_u32_array_table)) { + IPADBG( + "Did not find ipa3_plat_drv_u32_array_table for index %u\n", + index); + return false; + } + + u32_arrayP = + ipa3_plat_drv_u32_array_table[index].p_table; + + for (i = 0; + i < ipa3_plat_drv_u32_array_table[index].num_entries; + i++) { + if (strsame(u32_arrayP[i].key, propname)) { + if (u32_arrayP[i].p_value == NULL) { + IPADBG( + "Found no elements for propname %s index %u\n", + propname, + index); + return -ENODATA; + } + + IPADBG( + "Found %u elements for propname %s index %u\n", + u32_arrayP[i].num_elements, + propname, + index); + + return u32_arrayP[i].num_elements; + } + } + + IPADBG( + "Found no match in table with elem_size %d for propname %s index %u\n", + elem_size, + propname, + index); + + return -EINVAL; + } + + IPAERR( + "Found no tables with element size %u to search for propname %s index %u\n", + elem_size, + propname, + index); + + return -EINVAL; +} + +int emulator_of_property_read_variable_u32_array( + const struct device_node *np, + const char *propname, + u32 *out_values, + size_t sz_min, + size_t sz_max) +{ + return emulator_of_property_read_u32_array( + np, propname, out_values, sz_max); +} + +resource_size_t emulator_resource_size(const struct resource *res) +{ + return resource_size(res); +} diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_emulation_stubs.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_emulation_stubs.h new file mode 100644 index 0000000000..98cc4c60fd --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_emulation_stubs.h @@ -0,0 +1,121 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + */ + +#if !defined(_IPA_EMULATION_STUBS_H_) +# define _IPA_EMULATION_STUBS_H_ + +# define outer_flush_range(x, y) +# define __flush_dcache_area(x, y) +# define __cpuc_flush_dcache_area(x, y) __flush_dcache_area(x, y) + +/* Point several API calls to these new EMULATION functions */ +# define of_property_read_bool(np, propname) \ + emulator_of_property_read_bool(NULL, propname) +# define of_property_read_u32(np, propname, out_value) \ + emulator_of_property_read_u32(NULL, propname, out_value) +# define of_property_read_u32_array(np, propname, out_values, sz) \ + emulator_of_property_read_u32_array(NULL, propname, out_values, sz) +# define platform_get_resource_byname(dev, type, name) \ + emulator_platform_get_resource_byname(NULL, type, name) +# define of_property_count_elems_of_size(np, propname, elem_size) \ + emulator_of_property_count_elems_of_size(NULL, propname, elem_size) +# define of_property_read_variable_u32_array( \ + np, propname, out_values, sz_min, sz_max) \ + emulator_of_property_read_variable_u32_array( \ + NULL, propname, out_values, sz_min, sz_max) +# define resource_size(res) \ + emulator_resource_size(res) + +/** + * emulator_of_property_read_bool - Findfrom a property + * @np: device node used to find the property value. (not used) + * @propname: name of the property to be searched. + * + * Search for a property in a device node. + * Returns true if the property exists false otherwise. + */ +bool emulator_of_property_read_bool( + const struct device_node *np, + const char *propname); + +int emulator_of_property_read_u32( + const struct device_node *np, + const char *propname, + u32 *out_value); + +/** + * emulator_of_property_read_u32_array - Find and read an array of 32 + * bit integers from a property. + * + * @np: device node used to find the property value. (not used) + * @propname: name of the property to be searched. + * @out_values: pointer to return value, modified only if return value is 0. + * @sz: number of array elements to read + * + * Search for a property in a device node and read 32-bit value(s) from + * it. Returns 0 on success, -EINVAL if the property does not exist, + * -ENODATA if property does not have a value, and -EOVERFLOW if the + * property data isn't large enough. + * + * The out_values is modified only if a valid u32 value can be decoded. + */ +int emulator_of_property_read_u32_array( + const struct device_node *np, + const char *propname, + u32 *out_values, + size_t sz); + +/** + * emulator_platform_get_resource_byname - get a resource for a device + * by name + * + * @dev: platform device + * @type: resource type + * @name: resource name + */ +struct resource *emulator_platform_get_resource_byname( + struct platform_device *dev, + unsigned int type, + const char *name); + +/** + * emulator_of_property_count_elems_of_size - Count the number of + * elements in a property + * + * @np: device node used to find the property value. (not used) + * @propname: name of the property to be searched. + * @elem_size: size of the individual element + * + * Search for a property and count the number of elements of size + * elem_size in it. Returns number of elements on success, -EINVAL if + * the property does not exist or its length does not match a multiple + * of elem_size and -ENODATA if the property does not have a value. + */ +int emulator_of_property_count_elems_of_size( + const struct device_node *np, + const char *propname, + int elem_size); + +int emulator_of_property_read_variable_u32_array( + const struct device_node *np, + const char *propname, + u32 *out_values, + size_t sz_min, + size_t sz_max); + +resource_size_t emulator_resource_size( + const struct resource *res); + +static inline bool is_device_dma_coherent(struct device *dev) +{ + return false; +} + +static inline phys_addr_t qcom_smem_virt_to_phys(void *addr) +{ + return 0; +} + +#endif /* #if !defined(_IPA_EMULATION_STUBS_H_) */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_eth_i.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_eth_i.c new file mode 100644 index 0000000000..8ef5fdb07b --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_eth_i.c @@ -0,0 +1,1412 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. + */ +#include "ipa_i.h" +#include +#include "ipa_eth.h" +#include + +#define IPA_ETH_RTK_MODT (32) +#define IPA_ETH_RTK_MODC (128) + +#define IPA_ETH_AQC_MODT (32) +/* + * MODC factors are the number of percents from ring len (i.e 10 is 10% of len) + */ +#define IPA_ETH_AQC_MODC_FACTOR (10) +#define AQC_WRB_MODC_FACTOR (10) + +#define IPA_ETH_NTN_MODT (32) +#define IPA_ETH_NTN_MODC (128) + +#define NTN_BUFFER_SIZE 2048 /* 2K */ + +#define IPA_ETH_AGGR_PKT_LIMIT 1 +#define IPA_ETH_AGGR_BYTE_LIMIT 2 /* 2 Kbytes Agger hard byte limit */ + +#define IPA_ETH_MBOX_M (1) + +#define IPA_AQC_RX_MBOX_N (0) +#define IPA_RTK_RX_MBOX_N (20) +#define IPA_RTK_TX_MBOX_N (21) + +#define IPA_AQC_RX_MBOX_VAL (0x636f6d6d) +#define IPA_RTK_RX_MBOX_VAL (1) +#define IPA_RTK_TX_MBOX_VAL (2) + +#define IPA_ETH_MSI_DB_VAL (0xFDB) + +#define IPA_ETH_PCIE_MASK BIT_ULL(40) +#define IPA_ETH_PCIE_SET(val) (val | IPA_ETH_PCIE_MASK) + +#define IPA_CLIENT_IS_SMMU_ETH_INSTANCE(client) \ + ((client) == IPA_CLIENT_AQC_ETHERNET_PROD || \ + (client) == IPA_CLIENT_AQC_ETHERNET_CONS || \ + (client) == IPA_CLIENT_RTK_ETHERNET_PROD || \ + (client) == IPA_CLIENT_RTK_ETHERNET_CONS || \ + (client) == IPA_CLIENT_ETHERNET_PROD || \ + (client) == IPA_CLIENT_ETHERNET_CONS) + +#define IPA_CLIENT_IS_SMMU_ETH1_INSTANCE(client) \ + ((client) == IPA_CLIENT_ETHERNET2_PROD || \ + (client) == IPA_CLIENT_ETHERNET2_CONS) + +enum ipa_eth_dir { + IPA_ETH_RX = 0, + IPA_ETH_TX = 1, +}; + +static void ipa3_eth_save_client_mapping( + struct ipa_eth_client_pipe_info *pipe, + enum ipa_client_type type, int id, + int pipe_id, int ch_id) +{ + struct ipa_eth_client *client_info; + enum ipa_eth_client_type client_type; + u8 inst_id, pipe_hdl; + struct ipa3_eth_info *eth_info; + + client_info = pipe->client_info; + client_type = client_info->client_type; + inst_id = client_info->inst_id; + pipe_hdl = pipe->pipe_hdl; + eth_info = &ipa3_ctx->eth_info[client_type][inst_id]; + if (!eth_info->map[id].valid) { + eth_info->num_ch++; + eth_info->map[id].type = type; + eth_info->map[id].pipe_id = pipe_id; + eth_info->map[id].ch_id = ch_id; + eth_info->map[id].valid = true; + eth_info->map[id].pipe_hdl = pipe_hdl; + } +} + +static void ipa3_eth_release_client_mapping( + struct ipa_eth_client_pipe_info *pipe, + int id) +{ + struct ipa_eth_client *client_info; + enum ipa_eth_client_type client_type; + u8 inst_id, pipe_hdl; + struct ipa3_eth_info *eth_info; + + client_info = pipe->client_info; + client_type = client_info->client_type; + inst_id = client_info->inst_id; + pipe_hdl = pipe->pipe_hdl; + eth_info = &ipa3_ctx->eth_info[client_type][inst_id]; + if (eth_info->map[id].valid) { + eth_info->num_ch--; + eth_info->map[id].type = 0; + eth_info->map[id].pipe_id = 0; + eth_info->map[id].ch_id = 0; + eth_info->map[id].valid = false; + eth_info->map[id].pipe_hdl = 0; + } +} + +static int ipa3_eth_uc_init_peripheral(bool init, + u8 protocol, u64 per_base) +{ + struct ipa_mem_buffer cmd; + enum ipa_cpu_2_hw_offload_commands command; + int result; + + if (init) { + struct IpaHwPeripheralInitCmdData_t *cmd_data; + + cmd.size = sizeof(*cmd_data); + cmd.base = dma_alloc_coherent(ipa3_ctx->uc_pdev, cmd.size, + &cmd.phys_base, GFP_KERNEL); + if (cmd.base == NULL) { + IPAERR("fail to get DMA memory.\n"); + return -ENOMEM; + } + cmd_data = + (struct IpaHwPeripheralInitCmdData_t *)cmd.base; + cmd_data->protocol = protocol; + if (protocol == IPA_HW_PROTOCOL_AQC) { + cmd_data->Init_params.AqcInit_params.periph_baddr_lsb = + lower_32_bits(per_base); + cmd_data->Init_params.AqcInit_params.periph_baddr_msb = + upper_32_bits(per_base); + } + command = IPA_CPU_2_HW_CMD_PERIPHERAL_INIT; + } else { + struct IpaHwPeripheralDeinitCmdData_t *cmd_data; + + cmd.size = sizeof(*cmd_data); + cmd.base = dma_alloc_coherent(ipa3_ctx->uc_pdev, cmd.size, + &cmd.phys_base, GFP_KERNEL); + if (cmd.base == NULL) { + IPAERR("fail to get DMA memory.\n"); + return -ENOMEM; + } + cmd_data = + (struct IpaHwPeripheralDeinitCmdData_t *)cmd.base; + cmd_data->protocol = protocol; + if (protocol == IPA_HW_PROTOCOL_AQC) { + cmd_data->PeripheralDeinit_params.AqcDeinit_params.reserved = + 0; + } + command = IPA_CPU_2_HW_CMD_PERIPHERAL_DEINIT; + } + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + + result = ipa3_uc_send_cmd((u32)(cmd.phys_base), + command, + IPA_HW_2_CPU_OFFLOAD_CMD_STATUS_SUCCESS, + false, 10 * HZ); + if (result) { + IPAERR("fail to %s uc\n", + init ? "init" : "deinit"); + } + + dma_free_coherent(ipa3_ctx->uc_pdev, + cmd.size, cmd.base, cmd.phys_base); + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + + IPADBG("exit\n"); + return result; +} + +static int ipa3_eth_config_uc(bool init, + u8 protocol, + u8 dir, + u8 gsi_ch, + u8 peripheral_ch) +{ + struct ipa_mem_buffer cmd; + enum ipa_cpu_2_hw_offload_commands command; + int result; + + IPADBG("config uc %s\n", init ? "init" : "Deinit"); + if (init) { + struct IpaHwOffloadSetUpCmdData_t_v4_0 *cmd_data; + + cmd.size = sizeof(*cmd_data); + cmd.base = dma_alloc_coherent(ipa3_ctx->uc_pdev, cmd.size, + &cmd.phys_base, GFP_KERNEL); + if (cmd.base == NULL) { + IPAERR("dma_alloc_coherent failed\n"); + return -ENOMEM; + } + cmd_data = (struct IpaHwOffloadSetUpCmdData_t_v4_0 *)cmd.base; + cmd_data->protocol = protocol; + switch (protocol) { + case IPA_HW_PROTOCOL_AQC: + cmd_data->SetupCh_params.aqc_params.dir = dir; + cmd_data->SetupCh_params.aqc_params.gsi_ch = gsi_ch; + cmd_data->SetupCh_params.aqc_params.aqc_ch = peripheral_ch; + break; + case IPA_HW_PROTOCOL_RTK: + cmd_data->SetupCh_params.rtk_params.dir = dir; + cmd_data->SetupCh_params.rtk_params.gsi_ch = gsi_ch; + break; + default: + IPAERR("Unsupported protocol%d\n", protocol); + } + command = IPA_CPU_2_HW_CMD_OFFLOAD_CHANNEL_SET_UP; + + } else { + struct IpaHwOffloadCommonChCmdData_t_v4_0 *cmd_data; + + cmd.size = sizeof(*cmd_data); + cmd.base = dma_alloc_coherent(ipa3_ctx->uc_pdev, cmd.size, + &cmd.phys_base, GFP_KERNEL); + if (cmd.base == NULL) { + IPAERR("dma_alloc_coherent failed\n"); + return -ENOMEM; + } + + cmd_data = (struct IpaHwOffloadCommonChCmdData_t_v4_0 *)cmd.base; + + cmd_data->protocol = protocol; + switch (protocol) { + case IPA_HW_PROTOCOL_AQC: + cmd_data->CommonCh_params.aqc_params.gsi_ch = gsi_ch; + break; + case IPA_HW_PROTOCOL_RTK: + cmd_data->CommonCh_params.rtk_params.gsi_ch = gsi_ch; + break; + default: + IPAERR("Unsupported protocol%d\n", protocol); + } + cmd_data->CommonCh_params.rtk_params.gsi_ch = gsi_ch; + command = IPA_CPU_2_HW_CMD_OFFLOAD_CHANNEL_TEAR_DOWN; + } + + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + + result = ipa3_uc_send_cmd((u32)(cmd.phys_base), command, + IPA_HW_2_CPU_OFFLOAD_CMD_STATUS_SUCCESS, false, 10 * HZ); + if (result) + IPAERR("fail to %s uc for %s gsi channel %d\n", + init ? "init" : "deinit", dir == IPA_ETH_RX ? "Rx" : "Tx", gsi_ch); + + dma_free_coherent(ipa3_ctx->uc_pdev, cmd.size, cmd.base, cmd.phys_base); + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + + IPADBG("exit\n"); + return result; +} + + +static void ipa_eth_gsi_evt_ring_err_cb(struct gsi_evt_err_notify *notify) +{ + switch (notify->evt_id) { + case GSI_EVT_OUT_OF_BUFFERS_ERR: + IPAERR("Got GSI_EVT_OUT_OF_BUFFERS_ERR\n"); + break; + case GSI_EVT_OUT_OF_RESOURCES_ERR: + IPAERR("Got GSI_EVT_OUT_OF_RESOURCES_ERR\n"); + break; + case GSI_EVT_UNSUPPORTED_INTER_EE_OP_ERR: + IPAERR("Got GSI_EVT_UNSUPPORTED_INTER_EE_OP_ERR\n"); + break; + case GSI_EVT_EVT_RING_EMPTY_ERR: + IPAERR("Got GSI_EVT_EVT_RING_EMPTY_ERR\n"); + break; + default: + IPAERR("Unexpected err evt: %d\n", notify->evt_id); + } + ipa_assert(); +} + +static void ipa_eth_gsi_chan_err_cb(struct gsi_chan_err_notify *notify) +{ + switch (notify->evt_id) { + case GSI_CHAN_INVALID_TRE_ERR: + IPAERR("Got GSI_CHAN_INVALID_TRE_ERR\n"); + break; + case GSI_CHAN_NON_ALLOCATED_EVT_ACCESS_ERR: + IPAERR("Got GSI_CHAN_NON_ALLOCATED_EVT_ACCESS_ERR\n"); + break; + case GSI_CHAN_OUT_OF_BUFFERS_ERR: + IPAERR("Got GSI_CHAN_OUT_OF_BUFFERS_ERR\n"); + break; + case GSI_CHAN_OUT_OF_RESOURCES_ERR: + IPAERR("Got GSI_CHAN_OUT_OF_RESOURCES_ERR\n"); + break; + case GSI_CHAN_UNSUPPORTED_INTER_EE_OP_ERR: + IPAERR("Got GSI_CHAN_UNSUPPORTED_INTER_EE_OP_ERR\n"); + break; + case GSI_CHAN_HWO_1_ERR: + IPAERR("Got GSI_CHAN_HWO_1_ERR\n"); + break; + default: + IPAERR("Unexpected err evt: %d\n", notify->evt_id); + } + ipa_assert(); +} + + +static int ipa_eth_setup_rtk_gsi_channel( + struct ipa_eth_client_pipe_info *pipe, + struct ipa3_ep_context *ep) +{ + struct gsi_evt_ring_props gsi_evt_ring_props; + struct gsi_chan_props gsi_channel_props; + union __packed gsi_channel_scratch ch_scratch; + union __packed gsi_evt_scratch evt_scratch; + const struct ipa_gsi_ep_config *gsi_ep_info; + int result, len; + int queue_number; + u64 bar_addr; + + if (unlikely(!pipe->info.is_transfer_ring_valid)) { + IPAERR("RTK transfer ring invalid\n"); + ipa_assert(); + return -EFAULT; + } + + /* setup event ring */ + bar_addr = + IPA_ETH_PCIE_SET(pipe->info.client_info.rtk.bar_addr); + memset(&gsi_evt_ring_props, 0, sizeof(gsi_evt_ring_props)); + gsi_evt_ring_props.intf = GSI_EVT_CHTYPE_RTK_EV; + gsi_evt_ring_props.intr = GSI_INTR_MSI; + gsi_evt_ring_props.re_size = GSI_EVT_RING_RE_SIZE_32B; + if (pipe->dir == IPA_ETH_PIPE_DIR_TX) { + gsi_evt_ring_props.int_modt = IPA_ETH_RTK_MODT; + gsi_evt_ring_props.int_modc = IPA_ETH_RTK_MODC; + } + gsi_evt_ring_props.exclusive = true; + gsi_evt_ring_props.err_cb = ipa_eth_gsi_evt_ring_err_cb; + gsi_evt_ring_props.user_data = NULL; + gsi_evt_ring_props.msi_addr = + bar_addr + + pipe->info.client_info.rtk.dest_tail_ptr_offs; + len = pipe->info.transfer_ring_size; + gsi_evt_ring_props.ring_len = len; + gsi_evt_ring_props.ring_base_addr = + (u64)pipe->info.transfer_ring_base; + result = gsi_alloc_evt_ring(&gsi_evt_ring_props, + ipa3_ctx->gsi_dev_hdl, + &ep->gsi_evt_ring_hdl); + if (result != GSI_STATUS_SUCCESS) { + IPAERR("fail to alloc RX event ring\n"); + return -EFAULT; + } + ep->gsi_mem_info.evt_ring_len = + gsi_evt_ring_props.ring_len; + ep->gsi_mem_info.evt_ring_base_addr = + gsi_evt_ring_props.ring_base_addr; + + /* setup channel ring */ + memset(&gsi_channel_props, 0, sizeof(gsi_channel_props)); + gsi_channel_props.prot = GSI_CHAN_PROT_RTK; + if (pipe->dir == IPA_ETH_PIPE_DIR_TX) + gsi_channel_props.dir = GSI_CHAN_DIR_FROM_GSI; + else + gsi_channel_props.dir = GSI_CHAN_DIR_TO_GSI; + gsi_ep_info = ipa_get_gsi_ep_info(ep->client); + if (!gsi_ep_info) { + IPAERR("Failed getting GSI EP info for client=%d\n", + ep->client); + result = -EINVAL; + goto fail_get_gsi_ep_info; + } else + gsi_channel_props.ch_id = gsi_ep_info->ipa_gsi_chan_num; + gsi_channel_props.evt_ring_hdl = ep->gsi_evt_ring_hdl; + gsi_channel_props.re_size = GSI_CHAN_RE_SIZE_32B; + gsi_channel_props.use_db_eng = GSI_CHAN_DB_MODE; + gsi_channel_props.db_in_bytes = 1; + gsi_channel_props.max_prefetch = GSI_ONE_PREFETCH_SEG; + gsi_channel_props.prefetch_mode = + gsi_ep_info->prefetch_mode; + gsi_channel_props.empty_lvl_threshold = + gsi_ep_info->prefetch_threshold; + gsi_channel_props.low_weight = 1; + gsi_channel_props.err_cb = ipa_eth_gsi_chan_err_cb; + gsi_channel_props.ring_len = len; + gsi_channel_props.ring_base_addr = + (u64)pipe->info.transfer_ring_base; + result = gsi_alloc_channel(&gsi_channel_props, ipa3_ctx->gsi_dev_hdl, + &ep->gsi_chan_hdl); + if (result != GSI_STATUS_SUCCESS) + goto fail_get_gsi_ep_info; + ep->gsi_mem_info.chan_ring_len = gsi_channel_props.ring_len; + ep->gsi_mem_info.chan_ring_base_addr = + gsi_channel_props.ring_base_addr; + + /* write event scratch */ + memset(&evt_scratch, 0, sizeof(evt_scratch)); + /* nothing is needed for RTK event scratch */ + + /* write ch scratch */ + queue_number = pipe->info.client_info.rtk.queue_number; + memset(&ch_scratch, 0, sizeof(ch_scratch)); + ch_scratch.rtk.rtk_bar_low = + (u32)bar_addr; + ch_scratch.rtk.rtk_bar_high = + (u32)((u64)(bar_addr) >> 32); + /* + * RX: Queue Number will be as is received from RTK + * (Range 0 - 15). + * TX: Queue Number will be configured to be + * either 16 or 18. + * (For TX Queue 0: Configure 16) + * (For TX Queue 1: Configure 18) + */ + ch_scratch.rtk.queue_number = + (pipe->dir == IPA_ETH_PIPE_DIR_RX) ? + pipe->info.client_info.rtk.queue_number : + (queue_number == 0) ? 16 : 18; + ch_scratch.rtk.fix_buff_size = + ilog2(pipe->info.fix_buffer_size); + ch_scratch.rtk.rtk_buff_addr_low = + (u32)pipe->info.data_buff_list[0].iova; + ch_scratch.rtk.rtk_buff_addr_high = + (u32)((u64)(pipe->info.data_buff_list[0].iova) >> 32); + result = gsi_write_channel_scratch(ep->gsi_chan_hdl, ch_scratch); + if (result != GSI_STATUS_SUCCESS) { + IPAERR("failed to write evt ring scratch\n"); + goto fail_write_scratch; + } + return 0; +fail_write_scratch: + gsi_dealloc_channel(ep->gsi_chan_hdl); + ep->gsi_chan_hdl = ~0; +fail_get_gsi_ep_info: + gsi_dealloc_evt_ring(ep->gsi_evt_ring_hdl); + ep->gsi_evt_ring_hdl = ~0; + return result; +} + +static struct iommu_domain *ipa_eth_get_smmu_domain( + enum ipa_client_type client_type) +{ + if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0) + return ipa3_get_smmu_domain(); + if (IPA_CLIENT_IS_SMMU_ETH_INSTANCE(client_type)) + return ipa3_get_eth_smmu_domain(); + if (IPA_CLIENT_IS_SMMU_ETH1_INSTANCE(client_type)) + return ipa3_get_eth1_smmu_domain(); + + return NULL; +} + +static bool ipa_eth_is_smmu_buff_cb_bypass( + enum ipa_client_type client_type) +{ + if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0) + return ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_AP]; + if (IPA_CLIENT_IS_SMMU_ETH_INSTANCE(client_type)) + return ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_ETH]; + if (IPA_CLIENT_IS_SMMU_ETH1_INSTANCE(client_type)) + return ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_ETH1]; + return false; +} + +static enum ipa_smmu_cb_type ipa_eth_get_cb_type( + enum ipa_client_type client_type) +{ + if (IPA_CLIENT_IS_SMMU_ETH_INSTANCE(client_type)) + return IPA_SMMU_CB_ETH; + if (IPA_CLIENT_IS_SMMU_ETH1_INSTANCE(client_type)) + return IPA_SMMU_CB_ETH1; + + return IPA_SMMU_CB_MAX; +} + +static int ipa3_smmu_map_eth_pipes(struct ipa_eth_client_pipe_info *pipe, + enum ipa_client_type client_type, bool map) +{ + struct iommu_domain *smmu_domain; + int result = -EINVAL; + int i; + u64 iova; + phys_addr_t pa; + u64 iova_p; + u64 prev_iova_p; + phys_addr_t pa_p; + u32 size_p; + enum ipa_smmu_cb_type cb_type; + + if (pipe->info.fix_buffer_size > PAGE_SIZE) { + IPAERR("%s: invalid data buff size %d\n", + pipe->dir == IPA_ETH_PIPE_DIR_TX ? "TX" : "RX", + pipe->info.fix_buffer_size); + return -EINVAL; + } + + if (ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_AP]) { + IPADBG("AP SMMU is set to s1 bypass\n"); + goto map_buffer; + } + + result = ipa3_smmu_map_peer_buff( + (u64)pipe->info.transfer_ring_base, + pipe->info.transfer_ring_size, + map, + pipe->info.transfer_ring_sgt, + IPA_SMMU_CB_AP); + if (result) { + IPAERR("failed to %s ring %d\n", + map ? "map" : "unmap", result); + return -EINVAL; + } + +map_buffer: + if (ipa_eth_is_smmu_buff_cb_bypass(client_type)) { + IPADBG("SMMU cb for buffer is set to s1 bypass\n"); + return 0; + } + + cb_type = ipa_eth_get_cb_type(client_type); + if (cb_type >= IPA_SMMU_CB_MAX) { + IPAERR("invalid CB type %d\n", cb_type); + goto fail_map_buffer_smmu_enabled; + } + + if ((ipa3_get_smmu_ctx(cb_type))->shared) { + IPADBG("SMMU cb %d is shared, no need to map buffers\n", cb_type); + return 0; + } else { + IPADBG( + "SMMU cb %d is not shared, continue to map buffers\n", cb_type); + } + + if (pipe->info.is_buffer_pool_valid) { + IPADBG("buffer pool valid\n"); + result = ipa3_smmu_map_peer_buff( + (u64)pipe->info.buffer_pool_base_addr, + pipe->info.fix_buffer_size, + map, + pipe->info.buffer_pool_base_sgt, + cb_type); + if (result) { + IPAERR("failed to %s buffer %d cb_type %d\n", + map ? "map" : "unmap", result, cb_type); + goto fail_map_buffer_smmu_enabled; + } + } else { + IPADBG("buffer pool not valid\n"); + smmu_domain = ipa_eth_get_smmu_domain(client_type); + if (!smmu_domain) { + IPAERR("invalid smmu domain\n"); + result = -EINVAL; + goto fail_map_buffer_smmu_enabled; + } + + prev_iova_p = 0; + for (i = 0; i < pipe->info.data_buff_list_size; i++) { + iova = (u64)pipe->info.data_buff_list[i].iova; + pa = (phys_addr_t)pipe->info.data_buff_list[i].pa; + IPA_SMMU_ROUND_TO_PAGE(iova, pa, pipe->info.fix_buffer_size, + iova_p, pa_p, size_p); + /* Add check on every 2nd buffer for AQC smmu-dup issue */ + if (prev_iova_p == iova_p) { + IPADBG_LOW( + "current buffer and previous are on the same page, skip page mapping\n" + ); + continue; + } + prev_iova_p = iova_p; + IPADBG_LOW("%s 0x%llx to 0x%pa size %d\n", map ? "mapping" : + "unmapping", iova_p, &pa_p, size_p); + if (map) { + result = ipa3_iommu_map(smmu_domain, iova_p, pa_p, + size_p, IOMMU_READ | IOMMU_WRITE); + if (result) + IPAERR("Fail to map 0x%llx\n", iova); + } else { + result = iommu_unmap(smmu_domain, iova_p, size_p); + if (result != size_p) { + IPAERR("Fail to unmap 0x%llx\n", iova); + } + } + } + } + + return 0; + +fail_map_buffer_smmu_enabled: + ipa3_smmu_map_peer_buff( + (u64)pipe->info.transfer_ring_base, + pipe->info.transfer_ring_size, + !map, + pipe->info.transfer_ring_sgt, + IPA_SMMU_CB_AP); + return result; +} + +static int ipa_eth_setup_aqc_gsi_channel( + struct ipa_eth_client_pipe_info *pipe, + struct ipa3_ep_context *ep) +{ + struct gsi_evt_ring_props gsi_evt_ring_props; + struct gsi_chan_props gsi_channel_props; + union __packed gsi_channel_scratch ch_scratch; + union __packed gsi_evt_scratch evt_scratch; + const struct ipa_gsi_ep_config *gsi_ep_info; + int result, len; + u64 bar_addr; + u64 head_ptr; + + if (unlikely(!pipe->info.is_transfer_ring_valid)) { + IPAERR("RTK transfer ring invalid\n"); + ipa_assert(); + return -EFAULT; + } + /* setup event ring */ + bar_addr = + IPA_ETH_PCIE_SET(pipe->info.client_info.aqc.bar_addr); + memset(&gsi_evt_ring_props, 0, sizeof(gsi_evt_ring_props)); + gsi_evt_ring_props.intf = GSI_EVT_CHTYPE_AQC_EV; + gsi_evt_ring_props.intr = GSI_INTR_MSI; + gsi_evt_ring_props.re_size = GSI_EVT_RING_RE_SIZE_16B; + gsi_evt_ring_props.int_modt = IPA_ETH_AQC_MODT; + len = pipe->info.transfer_ring_size; + /* len / RE_SIZE == len in counts (convert from bytes) */ + gsi_evt_ring_props.int_modc = len * IPA_ETH_AQC_MODC_FACTOR / + (100 * GSI_EVT_RING_RE_SIZE_16B); + gsi_evt_ring_props.exclusive = true; + gsi_evt_ring_props.err_cb = ipa_eth_gsi_evt_ring_err_cb; + gsi_evt_ring_props.user_data = NULL; + gsi_evt_ring_props.msi_addr = + bar_addr + + pipe->info.client_info.aqc.dest_tail_ptr_offs; + gsi_evt_ring_props.ring_len = len; + gsi_evt_ring_props.ring_base_addr = + (u64)pipe->info.transfer_ring_base; + result = gsi_alloc_evt_ring(&gsi_evt_ring_props, + ipa3_ctx->gsi_dev_hdl, + &ep->gsi_evt_ring_hdl); + if (result != GSI_STATUS_SUCCESS) { + IPAERR("fail to alloc RX event ring\n"); + result = -EFAULT; + } + ep->gsi_mem_info.evt_ring_len = + gsi_evt_ring_props.ring_len; + ep->gsi_mem_info.evt_ring_base_addr = + gsi_evt_ring_props.ring_base_addr; + + /* setup channel ring */ + memset(&gsi_channel_props, 0, sizeof(gsi_channel_props)); + gsi_channel_props.prot = GSI_CHAN_PROT_AQC; + if (pipe->dir == IPA_ETH_PIPE_DIR_TX) + gsi_channel_props.dir = GSI_CHAN_DIR_FROM_GSI; + else + gsi_channel_props.dir = GSI_CHAN_DIR_TO_GSI; + gsi_ep_info = ipa_get_gsi_ep_info(ep->client); + if (!gsi_ep_info) { + IPAERR("Failed getting GSI EP info for client=%d\n", + ep->client); + result = -EINVAL; + goto fail_get_gsi_ep_info; + } else + gsi_channel_props.ch_id = gsi_ep_info->ipa_gsi_chan_num; + gsi_channel_props.evt_ring_hdl = ep->gsi_evt_ring_hdl; + gsi_channel_props.re_size = GSI_CHAN_RE_SIZE_16B; + gsi_channel_props.use_db_eng = GSI_CHAN_DB_MODE; + gsi_channel_props.db_in_bytes = 0; + gsi_channel_props.max_prefetch = GSI_ONE_PREFETCH_SEG; + gsi_channel_props.prefetch_mode = + gsi_ep_info->prefetch_mode; + gsi_channel_props.empty_lvl_threshold = + gsi_ep_info->prefetch_threshold; + gsi_channel_props.low_weight = 1; + gsi_channel_props.err_cb = ipa_eth_gsi_chan_err_cb; + gsi_channel_props.ring_len = len; + gsi_channel_props.ring_base_addr = + (u64)pipe->info.transfer_ring_base; + result = gsi_alloc_channel(&gsi_channel_props, + ipa3_ctx->gsi_dev_hdl, + &ep->gsi_chan_hdl); + if (result != GSI_STATUS_SUCCESS) + goto fail_get_gsi_ep_info; + ep->gsi_mem_info.chan_ring_len = gsi_channel_props.ring_len; + ep->gsi_mem_info.chan_ring_base_addr = + gsi_channel_props.ring_base_addr; + + /* write event scratch */ + memset(&evt_scratch, 0, sizeof(evt_scratch)); + if (pipe->dir == IPA_ETH_PIPE_DIR_TX) + /* len / RE_SIZE == len in counts (convert from bytes) */ + evt_scratch.aqc.head_ptr_wrb_mod_threshold = + len * AQC_WRB_MODC_FACTOR / (100 * GSI_EVT_RING_RE_SIZE_16B); + + /* write ch scratch */ + memset(&ch_scratch, 0, sizeof(ch_scratch)); + ch_scratch.aqc.fix_buff_size = + ilog2(pipe->info.fix_buffer_size); + head_ptr = pipe->info.client_info.aqc.head_ptr_offs; + if (pipe->dir == IPA_ETH_PIPE_DIR_RX) { + ch_scratch.aqc.buff_addr_lsb = + (u32)pipe->info.data_buff_list[0].iova; + ch_scratch.aqc.buff_addr_msb = + (u32)((u64)(pipe->info.data_buff_list[0].iova) >> 32); + ch_scratch.aqc.head_ptr_lsb = (u32)(bar_addr + head_ptr); + ch_scratch.aqc.head_ptr_msb = (u32)((bar_addr + + head_ptr) >> 32); + } + + result = gsi_write_channel_scratch(ep->gsi_chan_hdl, ch_scratch); + if (result != GSI_STATUS_SUCCESS) { + IPAERR("failed to write evt ring scratch\n"); + goto fail_write_scratch; + } + return 0; +fail_write_scratch: + gsi_dealloc_channel(ep->gsi_chan_hdl); + ep->gsi_chan_hdl = ~0; +fail_get_gsi_ep_info: + gsi_dealloc_evt_ring(ep->gsi_evt_ring_hdl); + ep->gsi_evt_ring_hdl = ~0; + return result; +} + +static int ipa_eth_setup_ntn_gsi_channel( + struct ipa_eth_client_pipe_info *pipe, + struct ipa3_ep_context *ep) +{ + struct gsi_evt_ring_props gsi_evt_ring_props; + struct gsi_chan_props gsi_channel_props; + union __packed gsi_channel_scratch ch_scratch; + union __packed gsi_evt_scratch evt_scratch; + const struct ipa_gsi_ep_config *gsi_ep_info; + int result, len; + u64 bar_addr; + + if (unlikely(!pipe->info.is_transfer_ring_valid)) { + IPAERR("NTN transfer ring invalid\n"); + ipa_assert(); + return -EFAULT; + } + + /* don't assert bit 40 in test mode as we emulate regs on DDR not + * on PICE address space */ + bar_addr = pipe->client_info->test ? + pipe->info.client_info.ntn.bar_addr : + IPA_ETH_PCIE_SET(pipe->info.client_info.ntn.bar_addr); + + /* setup event ring */ + memset(&gsi_evt_ring_props, 0, sizeof(gsi_evt_ring_props)); + gsi_evt_ring_props.intf = GSI_EVT_CHTYPE_NTN_EV; + gsi_evt_ring_props.re_size = GSI_EVT_RING_RE_SIZE_16B; + gsi_evt_ring_props.intr = GSI_INTR_MSI; + gsi_evt_ring_props.int_modt = IPA_ETH_NTN_MODT; + /* len / RE_SIZE == len in counts (convert from bytes) */ + len = pipe->info.transfer_ring_size; + gsi_evt_ring_props.int_modc = len * IPA_ETH_AQC_MODC_FACTOR / + (100 * GSI_EVT_RING_RE_SIZE_16B); + gsi_evt_ring_props.exclusive = true; + gsi_evt_ring_props.err_cb = ipa_eth_gsi_evt_ring_err_cb; + gsi_evt_ring_props.user_data = NULL; + gsi_evt_ring_props.msi_addr = + bar_addr + + pipe->info.client_info.ntn.tail_ptr_offs; + gsi_evt_ring_props.ring_len = len; + gsi_evt_ring_props.ring_base_addr = + (u64)pipe->info.transfer_ring_base; + result = gsi_alloc_evt_ring(&gsi_evt_ring_props, + ipa3_ctx->gsi_dev_hdl, + &ep->gsi_evt_ring_hdl); + if (result != GSI_STATUS_SUCCESS) { + IPAERR("fail to alloc RX event ring\n"); + result = -EFAULT; + } + + ep->gsi_mem_info.evt_ring_len = + gsi_evt_ring_props.ring_len; + ep->gsi_mem_info.evt_ring_base_addr = + gsi_evt_ring_props.ring_base_addr; + + /* setup channel ring */ + memset(&gsi_channel_props, 0, sizeof(gsi_channel_props)); + gsi_channel_props.prot = GSI_CHAN_PROT_NTN; + if (pipe->dir == IPA_ETH_PIPE_DIR_TX) + gsi_channel_props.dir = GSI_CHAN_DIR_FROM_GSI; + else + gsi_channel_props.dir = GSI_CHAN_DIR_TO_GSI; + gsi_ep_info = ipa_get_gsi_ep_info(ep->client); + if (!gsi_ep_info) { + IPAERR("Failed getting GSI EP info for client=%d\n", + ep->client); + result = -EINVAL; + goto fail_get_gsi_ep_info; + } else + gsi_channel_props.ch_id = gsi_ep_info->ipa_gsi_chan_num; + gsi_channel_props.evt_ring_hdl = ep->gsi_evt_ring_hdl; + gsi_channel_props.re_size = GSI_CHAN_RE_SIZE_16B; + gsi_channel_props.use_db_eng = GSI_CHAN_DB_MODE; + gsi_channel_props.db_in_bytes = 1; + gsi_channel_props.max_prefetch = GSI_ONE_PREFETCH_SEG; + gsi_channel_props.prefetch_mode = + gsi_ep_info->prefetch_mode; + gsi_channel_props.empty_lvl_threshold = + gsi_ep_info->prefetch_threshold; + gsi_channel_props.low_weight = 1; + gsi_channel_props.err_cb = ipa_eth_gsi_chan_err_cb; + gsi_channel_props.ring_len = len; + gsi_channel_props.ring_base_addr = + (u64)pipe->info.transfer_ring_base; + result = gsi_alloc_channel(&gsi_channel_props, ipa3_ctx->gsi_dev_hdl, + &ep->gsi_chan_hdl); + if (result != GSI_STATUS_SUCCESS) + goto fail_get_gsi_ep_info; + ep->gsi_mem_info.chan_ring_len = gsi_channel_props.ring_len; + ep->gsi_mem_info.chan_ring_base_addr = + gsi_channel_props.ring_base_addr; + + /* write event scratch */ + memset(&evt_scratch, 0, sizeof(evt_scratch)); + /* nothing is needed for NTN event scratch */ + + /* write ch scratch */ + memset(&ch_scratch, 0, sizeof(ch_scratch)); + ch_scratch.ntn.fix_buff_size = + ilog2(pipe->info.fix_buffer_size); + if (pipe->info.is_buffer_pool_valid) { + ch_scratch.ntn.buff_addr_lsb = + (u32)pipe->info.buffer_pool_base_addr; + ch_scratch.ntn.buff_addr_msb = + (u32)((u64)(pipe->info.buffer_pool_base_addr) >> 32); + } + else { + ch_scratch.ntn.buff_addr_lsb = + (u32)pipe->info.data_buff_list[0].iova; + ch_scratch.ntn.buff_addr_msb = + (u32)((u64)(pipe->info.data_buff_list[0].iova) >> 32); + } + + if (pipe->dir == IPA_ETH_PIPE_DIR_TX) { + if (pipe->info.client_info.ntn.ioc_mod_threshold && + pipe->info.client_info.ntn.ioc_mod_threshold < len / GSI_EVT_RING_RE_SIZE_16B) { + ch_scratch.ntn.ioc_mod_threshold = + pipe->info.client_info.ntn.ioc_mod_threshold; + } else { + ch_scratch.ntn.ioc_mod_threshold = IPA_ETH_NTN_MODT; + } + } + + result = gsi_write_channel_scratch(ep->gsi_chan_hdl, ch_scratch); + if (result != GSI_STATUS_SUCCESS) { + IPAERR("failed to write evt ring scratch\n"); + goto fail_write_scratch; + } + return 0; +fail_write_scratch: + gsi_dealloc_channel(ep->gsi_chan_hdl); + ep->gsi_chan_hdl = ~0; +fail_get_gsi_ep_info: + gsi_dealloc_evt_ring(ep->gsi_evt_ring_hdl); + ep->gsi_evt_ring_hdl = ~0; + return result; +} + +static int ipa3_eth_get_prot(struct ipa_eth_client_pipe_info *pipe, + enum ipa4_hw_protocol *prot) +{ + int ret = 0; + + switch (pipe->client_info->client_type) { + case IPA_ETH_CLIENT_AQC107: + case IPA_ETH_CLIENT_AQC113: + *prot = IPA_HW_PROTOCOL_AQC; + break; + case IPA_ETH_CLIENT_RTK8111K: + case IPA_ETH_CLIENT_RTK8125B: + *prot = IPA_HW_PROTOCOL_RTK; + break; + case IPA_ETH_CLIENT_NTN: +#if IPA_ETH_API_VER >= 2 + case IPA_ETH_CLIENT_NTN3: +#endif + *prot = IPA_HW_PROTOCOL_NTN3; + break; + case IPA_ETH_CLIENT_EMAC: + *prot = IPA_HW_PROTOCOL_ETH; + break; + default: + IPAERR("invalid client type%d\n", + pipe->client_info->client_type); + *prot = IPA_HW_PROTOCOL_MAX; + ret = -EFAULT; + } + + return ret; +} + +int ipa3_eth_connect( + struct ipa_eth_client_pipe_info *pipe, + enum ipa_client_type client_type) +{ + struct ipa3_ep_context *ep; + int ep_idx; + bool vlan_mode; + int result = 0; + u32 gsi_db_addr_low, gsi_db_addr_high; + void __iomem *db_addr; + u32 evt_ring_db_addr_low, evt_ring_db_addr_high, db_val = 0; + int id; + int ch; + u64 bar_addr; + enum ipa4_hw_protocol prot; +#if IPA_ETH_API_VER >= 2 + struct net_device *net_dev; +#endif + + ep_idx = ipa_get_ep_mapping(client_type); + if (ep_idx == -1 || ep_idx >= IPA3_MAX_NUM_PIPES) { + IPAERR("undefined client_type\n"); + return -EFAULT; + } + + /* currently all protocols require valid transfer ring */ + if (!pipe->info.is_transfer_ring_valid) { + IPAERR("transfer ring not valid!\n"); + return -EINVAL; + } + + if (pipe->client_info->client_type == IPA_ETH_CLIENT_NTN) { + if (pipe->info.fix_buffer_size != NTN_BUFFER_SIZE) { + IPAERR("fix buffer size %u not valid for NTN, use 2K\n" + , pipe->info.fix_buffer_size); + return -EINVAL; + } + } + +#if IPA_ETH_API_VER >= 2 + net_dev = pipe->client_info->net_dev; + + /* multiple attach support */ + if (strnstr(net_dev->name, STR_ETH0_IFACE, strlen(net_dev->name))) { + result = ipa_is_vlan_mode(IPA_VLAN_IF_ETH0, &vlan_mode); + if (result) { + IPAERR("Could not determine IPA VLAN mode\n"); + return result; + } + } else if (strnstr(net_dev->name, STR_ETH1_IFACE, strlen(net_dev->name))) { + result = ipa_is_vlan_mode(IPA_VLAN_IF_ETH1, &vlan_mode); + if (result) { + IPAERR("Could not determine IPA VLAN mode\n"); + return result; + } + } else { + result = ipa_is_vlan_mode(IPA_VLAN_IF_ETH, &vlan_mode); + if (result) { + IPAERR("Could not determine IPA VLAN mode\n"); + return result; + } + } +#else + result = ipa_is_vlan_mode(IPA_VLAN_IF_ETH, &vlan_mode); + if (result) { + IPAERR("Could not determine IPA VLAN mode\n"); + return result; + } +#endif + + result = ipa3_eth_get_prot(pipe, &prot); + if (result) { + IPAERR("Could not determine protocol\n"); + return result; + } + + result = ipa3_smmu_map_eth_pipes(pipe, client_type, true); + if (result) { + IPAERR("failed to map SMMU %d\n", result); + return result; + } + + ep = &ipa3_ctx->ep[ep_idx]; + memset(ep, 0, offsetof(struct ipa3_ep_context, sys)); + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + ep->valid = 1; + ep->client = client_type; + result = ipa3_disable_data_path(ep_idx); + if (result) { + IPAERR("disable data path failed res=%d clnt=%d.\n", result, + ep_idx); + goto disable_data_path_fail; + } + + ep->cfg.nat.nat_en = IPA_CLIENT_IS_PROD(client_type) ? + IPA_SRC_NAT : IPA_BYPASS_NAT; + ep->cfg.hdr.hdr_len = vlan_mode ? VLAN_ETH_HLEN : ETH_HLEN; + ep->cfg.mode.mode = IPA_BASIC; + if (IPA_CLIENT_IS_CONS(client_type)) { + ep->cfg.aggr.aggr_en = IPA_ENABLE_AGGR; + ep->cfg.aggr.aggr = IPA_GENERIC; + ep->cfg.aggr.aggr_byte_limit = IPA_ETH_AGGR_BYTE_LIMIT; + ep->cfg.aggr.aggr_pkt_limit = IPA_ETH_AGGR_PKT_LIMIT; + ep->cfg.aggr.aggr_hard_byte_limit_en = IPA_ENABLE_AGGR; + } else { + ep->client_notify = pipe->info.notify; + ep->priv = pipe->info.priv; + /* xlat config in vlan mode */ + if (vlan_mode) { + ep->cfg.hdr.hdr_ofst_metadata_valid = 1; + ep->cfg.hdr.hdr_ofst_metadata = ETH_HLEN; + ep->cfg.hdr.hdr_metadata_reg_valid = false; + } + } + if (ipa3_cfg_ep(ep_idx, &ep->cfg)) { + IPAERR("fail to setup rx pipe cfg\n"); + goto cfg_ep_fail; + } + if (IPA_CLIENT_IS_PROD(client_type)) + ipa3_install_dflt_flt_rules(ep_idx); + IPADBG("client %d (ep: %d) connected\n", client_type, + ep_idx); + + switch (prot) { + case IPA_HW_PROTOCOL_RTK: + result = ipa_eth_setup_rtk_gsi_channel(pipe, ep); + break; + case IPA_HW_PROTOCOL_AQC: + result = ipa_eth_setup_aqc_gsi_channel(pipe, ep); + break; + case IPA_HW_PROTOCOL_NTN3: + result = ipa_eth_setup_ntn_gsi_channel(pipe, ep); + break; + default: + IPAERR("unknown protocol %d\n", prot); + result = -EINVAL; + } + if (result) { + IPAERR("fail to setup eth gsi rx channel\n"); + result = -EFAULT; + goto setup_gsi_ch_fail; + } + + if (gsi_query_channel_db_addr(ep->gsi_chan_hdl, + &gsi_db_addr_low, &gsi_db_addr_high)) { + IPAERR("failed to query gsi rx db addr\n"); + result = -EFAULT; + goto query_ch_db_fail; + } + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0) { + switch (prot) { + case IPA_HW_PROTOCOL_AQC: + if (IPA_CLIENT_IS_PROD(client_type)) { + if (gsi_query_msi_addr(ep->gsi_chan_hdl, + &pipe->info.db_pa)) { + result = -EFAULT; + goto query_msi_fail; + } + /* we don't need to ring the MSI doorbell in RX case */ + } else { + pipe->info.db_pa = gsi_db_addr_low; + pipe->info.db_val = 0; + /* only 32 bit lsb is used */ + db_addr = ioremap((phys_addr_t)(gsi_db_addr_low), 4); + if (!db_addr) { + IPAERR("ioremap failed\n"); + result = -EFAULT; + goto ioremap_fail; + } + /* TX: Initialize to end of ring */ + db_val = (u32)ep->gsi_mem_info.chan_ring_base_addr; + db_val += (u32)ep->gsi_mem_info.chan_ring_len; + iowrite32(db_val, db_addr); + iounmap(db_addr); + } + break; + case IPA_HW_PROTOCOL_RTK: + if (gsi_query_msi_addr(ep->gsi_chan_hdl, + &pipe->info.db_pa)) { + result = -EFAULT; + goto query_msi_fail; + } + if (IPA_CLIENT_IS_CONS(client_type)) { + /* only 32 bit lsb is used */ + db_addr = ioremap((phys_addr_t)(pipe->info.db_pa), 4); + if (!db_addr) { + IPAERR("ioremap failed\n"); + result = -EFAULT; + goto ioremap_fail; + } + /* TX: ring MSI doorbell */ + db_val = IPA_ETH_MSI_DB_VAL; + iowrite32(db_val, db_addr); + iounmap(db_addr); + } + break; + case IPA_HW_PROTOCOL_NTN3: + if (gsi_query_msi_addr(ep->gsi_chan_hdl, &pipe->info.db_pa)) { + result = -EFAULT; + goto query_msi_fail; + } + pipe->info.db_val = 0; + + if (IPA_CLIENT_IS_CONS(client_type)) { + db_addr = ioremap((phys_addr_t)(pipe->info.db_pa), 4); + if (!db_addr) { + IPAERR("ioremap failed\n"); + result = -EFAULT; + goto ioremap_fail; + } + /* Any value is good to write here, so writing as is */ + iowrite32(db_val, db_addr); + iounmap(db_addr); + } + break; + default: + /* we can't really get here as we checked prot before */ + IPAERR("unknown protocol %d\n", prot); + } + } else { + if (IPA_CLIENT_IS_PROD(client_type)) { + /* RX mailbox */ + if (prot == IPA_HW_PROTOCOL_RTK) { + pipe->info.db_pa = ipa3_ctx->ipa_wrapper_base + + ipahal_get_reg_base() + + ipahal_get_reg_mn_ofst(IPA_UC_MAILBOX_m_n, + IPA_ETH_MBOX_M, + IPA_RTK_RX_MBOX_N); + pipe->info.db_val = IPA_RTK_RX_MBOX_VAL; + } else if (prot == IPA_HW_PROTOCOL_AQC) { + pipe->info.db_pa = ipa3_ctx->ipa_wrapper_base + + ipahal_get_reg_base() + + ipahal_get_reg_mn_ofst(IPA_UC_MAILBOX_m_n, + IPA_ETH_MBOX_M, + IPA_AQC_RX_MBOX_N); + pipe->info.db_val = IPA_AQC_RX_MBOX_VAL; + } + /* only 32 bit lsb is used */ + db_addr = ioremap((phys_addr_t)(gsi_db_addr_low), 4); + if (!db_addr) { + IPAERR("ioremap failed\n"); + result = -EFAULT; + goto ioremap_fail; + } + /* Rx: Initialize to ring base (i.e point 6) */ + db_val = (u32)ep->gsi_mem_info.chan_ring_base_addr; + iowrite32(db_val, db_addr); + iounmap(db_addr); + } else { + /* TX mailbox */ + if (prot == IPA_HW_PROTOCOL_RTK) { + pipe->info.db_pa = ipa3_ctx->ipa_wrapper_base + + ipahal_get_reg_base() + + ipahal_get_reg_mn_ofst(IPA_UC_MAILBOX_m_n, + IPA_ETH_MBOX_M, + IPA_RTK_TX_MBOX_N); + pipe->info.db_val = IPA_RTK_TX_MBOX_VAL; + } else if (prot == IPA_HW_PROTOCOL_AQC) { + pipe->info.db_pa = gsi_db_addr_low; + pipe->info.db_val = 0; + } + /* only 32 bit lsb is used */ + db_addr = ioremap((phys_addr_t)(gsi_db_addr_low), 4); + if (!db_addr) { + IPAERR("ioremap failed\n"); + result = -EFAULT; + goto ioremap_fail; + } + /* TX: Initialize to end of ring */ + db_val = (u32)ep->gsi_mem_info.chan_ring_base_addr; + db_val += (u32)ep->gsi_mem_info.chan_ring_len; + iowrite32(db_val, db_addr); + iounmap(db_addr); + } + } + gsi_query_evt_ring_db_addr(ep->gsi_evt_ring_hdl, + &evt_ring_db_addr_low, &evt_ring_db_addr_high); + IPADBG("evt_ring_hdl %lu, db_addr_low %u db_addr_high %u\n", + ep->gsi_evt_ring_hdl, evt_ring_db_addr_low, + evt_ring_db_addr_high); + /* only 32 bit lsb is used */ + db_addr = ioremap((phys_addr_t)(evt_ring_db_addr_low), 4); + if (!db_addr) { + IPAERR("ioremap failed\n"); + result = -EFAULT; + goto ioremap_fail; + } + /* + * IPA/GSI driver should ring the event DB once after + * initialization of the event, with a value that is + * outside of the ring range. Eg: ring base = 0x1000, + * ring size = 0x100 => AP can write value > 0x1100 + * into the doorbell address. Eg: 0x 1110. + * Use event ring base addr + event ring size + 1 element size. + */ + db_val = (u32)ep->gsi_mem_info.evt_ring_base_addr; + db_val += (u32)ep->gsi_mem_info.evt_ring_len; + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0 && + prot == IPA_HW_PROTOCOL_RTK) { + db_val += GSI_EVT_RING_RE_SIZE_32B; + } else { + db_val += GSI_EVT_RING_RE_SIZE_16B; + } + iowrite32(db_val, db_addr); + iounmap(db_addr); + + /* enable data path */ + result = ipa3_enable_data_path(ep_idx); + if (result) { + IPAERR("enable data path failed res=%d clnt=%d\n", result, + ep_idx); + goto enable_data_path_fail; + } + + /* start gsi channel */ + result = gsi_start_channel(ep->gsi_chan_hdl); + if (result) { + IPAERR("failed to start gsi tx channel\n"); + goto start_channel_fail; + } + + id = (pipe->dir == IPA_ETH_PIPE_DIR_TX) ? 1 : 0; + + /* start uC gsi dbg stats monitor */ + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_5 && ipa3_ctx->ipa_hw_type != IPA_HW_v5_2) { + ipa3_ctx->gsi_info[prot].ch_id_info[id].ch_id + = ep->gsi_chan_hdl; + ipa3_ctx->gsi_info[prot].ch_id_info[id].dir + = pipe->dir; + ipa3_uc_debug_stats_alloc( + ipa3_ctx->gsi_info[prot]); + } + + ch = 0; + if ((ipa3_ctx->ipa_hw_type == IPA_HW_v4_5) && + (prot == IPA_HW_PROTOCOL_AQC)) { + enum ipa_eth_client_type type; + u8 inst_id; + struct ipa3_eth_info *eth_info; + + type = pipe->client_info->client_type; + inst_id = pipe->client_info->inst_id; + eth_info = &ipa3_ctx->eth_info[type][inst_id]; + if (!eth_info->num_ch) { + bar_addr = + IPA_ETH_PCIE_SET(pipe->info.client_info.aqc.bar_addr); + result = ipa3_eth_uc_init_peripheral(true, + IPA_HW_PROTOCOL_AQC, bar_addr); + if (result) { + IPAERR("failed to init peripheral from uc\n"); + goto uc_init_peripheral_fail; + } + } + ch = pipe->info.client_info.aqc.aqc_ch; + } + + ipa3_eth_save_client_mapping(pipe, client_type, + id, ep_idx, ep->gsi_chan_hdl); + if ((ipa3_ctx->ipa_hw_type == IPA_HW_v4_5) || + (prot == IPA_HW_PROTOCOL_RTK)) { + result = ipa3_eth_config_uc(true, + prot, + (pipe->dir == IPA_ETH_PIPE_DIR_TX) + ? IPA_ETH_TX : IPA_ETH_RX, + ep->gsi_chan_hdl, ch); + if (result) { + IPAERR("failed to config uc\n"); + goto config_uc_fail; + } + } + + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + return 0; + +config_uc_fail: + /* stop uC gsi dbg stats monitor */ + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_5 && ipa3_ctx->ipa_hw_type != IPA_HW_v5_2) { + ipa3_ctx->gsi_info[prot].ch_id_info[id].ch_id + = 0xff; + ipa3_ctx->gsi_info[prot].ch_id_info[id].dir + = pipe->dir; + ipa3_uc_debug_stats_alloc( + ipa3_ctx->gsi_info[prot]); + } +uc_init_peripheral_fail: + ipa_stop_gsi_channel(ep->gsi_chan_hdl); +start_channel_fail: + ipa3_disable_data_path(ep_idx); +enable_data_path_fail: +ioremap_fail: +query_msi_fail: +query_ch_db_fail: +setup_gsi_ch_fail: +cfg_ep_fail: +disable_data_path_fail: + ipa3_smmu_map_eth_pipes(pipe, client_type, false); + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + return result; +} +EXPORT_SYMBOL(ipa3_eth_connect); + +int ipa3_eth_disconnect( + struct ipa_eth_client_pipe_info *pipe, + enum ipa_client_type client_type) +{ + int result = 0; + struct ipa3_ep_context *ep; + int ep_idx; + int id; + enum ipa4_hw_protocol prot; + + result = ipa3_eth_get_prot(pipe, &prot); + if (result) { + IPAERR("Could not determine protocol\n"); + return result; + } + + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + ep_idx = ipa_get_ep_mapping(client_type); + if (ep_idx == -1 || ep_idx >= IPA3_MAX_NUM_PIPES) { + IPAERR("undefined client_type\n"); + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + return -EFAULT; + } + ep = &ipa3_ctx->ep[ep_idx]; + /* disable data path */ + result = ipa3_disable_data_path(ep_idx); + if (result) { + IPAERR("enable data path failed res=%d clnt=%d.\n", result, + ep_idx); + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + return -EFAULT; + } + + id = (pipe->dir == IPA_ETH_PIPE_DIR_TX) ? 1 : 0; + /* stop uC gsi dbg stats monitor */ + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_5 && ipa3_ctx->ipa_hw_type != IPA_HW_v5_2) { + ipa3_ctx->gsi_info[prot].ch_id_info[id].ch_id + = 0xff; + ipa3_ctx->gsi_info[prot].ch_id_info[id].dir + = pipe->dir; + ipa3_uc_debug_stats_alloc( + ipa3_ctx->gsi_info[prot]); + } + /* stop gsi channel */ + result = ipa_stop_gsi_channel(ep_idx); + if (result) { + IPAERR("failed to stop gsi channel %d\n", ep_idx); + result = -EFAULT; + ipa_assert(); + goto fail; + } + + if ((ipa3_ctx->ipa_hw_type == IPA_HW_v4_5) || + (prot == IPA_HW_PROTOCOL_RTK)) { + result = ipa3_eth_config_uc(false, + prot, + (pipe->dir == IPA_ETH_PIPE_DIR_TX) + ? IPA_ETH_TX : IPA_ETH_RX, + ep->gsi_chan_hdl, 0); + if (result) + IPAERR("failed to config uc\n"); + } + + /* tear down pipe */ + result = ipa3_reset_gsi_channel(ep_idx); + if (result != GSI_STATUS_SUCCESS) { + IPAERR("failed to reset gsi channel: %d.\n", result); + ipa_assert(); + goto fail; + } + result = gsi_reset_evt_ring(ep->gsi_evt_ring_hdl); + if (result != GSI_STATUS_SUCCESS) { + IPAERR("failed to reset evt ring: %d.\n", result); + ipa_assert(); + goto fail; + } + result = ipa3_release_gsi_channel(ep_idx); + if (result) { + IPAERR("failed to release gsi channel: %d\n", result); + ipa_assert(); + goto fail; + } + memset(ep, 0, sizeof(struct ipa3_ep_context)); + IPADBG("client (ep: %d) disconnected\n", ep_idx); + + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_5 && ipa3_ctx->ipa_hw_type != IPA_HW_v5_2) + ipa3_uc_debug_stats_dealloc(prot); + if (IPA_CLIENT_IS_PROD(client_type)) + ipa3_delete_dflt_flt_rules(ep_idx); + /* unmap th pipe */ + result = ipa3_smmu_map_eth_pipes(pipe, client_type, false); + if (result) + IPAERR("failed to unmap SMMU %d\n", result); + ipa3_eth_release_client_mapping(pipe, id); + + if ((ipa3_ctx->ipa_hw_type == IPA_HW_v4_5) && + (prot == IPA_HW_PROTOCOL_AQC)) { + enum ipa_eth_client_type type; + u8 inst_id; + struct ipa3_eth_info *eth_info; + + type = pipe->client_info->client_type; + inst_id = pipe->client_info->inst_id; + eth_info = &ipa3_ctx->eth_info[type][inst_id]; + if (!eth_info->num_ch) { + result = ipa3_eth_uc_init_peripheral(false, + IPA_HW_PROTOCOL_AQC, 0); + if (result) { + IPAERR("failed to de-init peripheral %d\n", result); + goto fail; + } + } + } +fail: + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + return result; +} +EXPORT_SYMBOL(ipa3_eth_disconnect); diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_flt.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_flt.c new file mode 100644 index 0000000000..601cfc8158 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_flt.c @@ -0,0 +1,2329 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. + * + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ipa_i.h" +#include "ipahal.h" +#include "ipahal_fltrt.h" + +#define IPA_FLT_STATUS_OF_ADD_FAILED (-1) +#define IPA_FLT_STATUS_OF_DEL_FAILED (-1) +#define IPA_FLT_STATUS_OF_MDFY_FAILED (-1) +#define IPA_FLT_MAX_IMM_CMD_CHAIN_LENGTH (10) + +#define IPA_FLT_GET_RULE_TYPE(__entry) \ + ( \ + ((__entry)->rule.hashable) ? \ + (IPA_RULE_HASHABLE):(IPA_RULE_NON_HASHABLE) \ + ) + +/** + * ipa3_generate_flt_hw_rule() - generates the filtering hardware rule + * @ip: the ip address family type + * @entry: filtering entry + * @buf: output buffer, buf == NULL means + * caller wants to know the size of the rule as seen + * by HW so they did not pass a valid buffer, we will use a + * scratch buffer instead. + * With this scheme we are going to + * generate the rule twice, once to know size using scratch + * buffer and second to write the rule to the actual caller + * supplied buffer which is of required size + * + * Returns: 0 on success, negative on failure + * + * caller needs to hold any needed locks to ensure integrity + * + */ +static int ipa3_generate_flt_hw_rule(enum ipa_ip_type ip, + struct ipa3_flt_entry *entry, u8 *buf) +{ + struct ipahal_flt_rule_gen_params gen_params; + int res = 0; + + memset(&gen_params, 0, sizeof(gen_params)); + + if (entry->rule.hashable) { + if (entry->rule.attrib.attrib_mask & IPA_FLT_IS_PURE_ACK + && !entry->rule.eq_attrib_type) { + IPAERR_RL("PURE_ACK rule atrb used with hash rule\n"); + WARN_ON_RATELIMIT_IPA(1); + return -EPERM; + } + /* + * tos_eq_present field has two meanings: + * tos equation for IPA ver < 4.5 (as the field name reveals) + * pure_ack equation for IPA ver >= 4.5 + */ + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_5 && + entry->rule.eq_attrib_type && + entry->rule.eq_attrib.tos_eq_present) { + IPAERR_RL("PURE_ACK rule eq used with hash rule\n"); + return -EPERM; + } + } + + gen_params.ipt = ip; + if (entry->rt_tbl && (!ipa3_check_idr_if_freed(entry->rt_tbl))) + gen_params.rt_tbl_idx = entry->rt_tbl->idx; + else + gen_params.rt_tbl_idx = entry->rule.rt_tbl_idx; + + gen_params.priority = entry->prio; + gen_params.id = entry->rule_id; + gen_params.rule = (const struct ipa_flt_rule_i *)&entry->rule; + gen_params.cnt_idx = entry->cnt_idx; + + res = ipahal_flt_generate_hw_rule(&gen_params, &entry->hw_len, buf); + if (res) { + IPAERR_RL("failed to generate flt h/w rule\n"); + return res; + } + + return 0; +} + +static void __ipa_reap_sys_flt_tbls(enum ipa_ip_type ip, enum ipa_rule_type rlt) +{ + struct ipa3_flt_tbl *tbl; + int i; + + IPADBG_LOW("reaping sys flt tbls ip=%d rlt=%d\n", ip, rlt); + + for (i = 0; i < ipa3_ctx->ipa_num_pipes; i++) { + if (!ipa_is_ep_support_flt(i)) + continue; + + tbl = &ipa3_ctx->flt_tbl[i][ip]; + if (tbl->prev_mem[rlt].phys_base) { + IPADBG_LOW("reaping flt tbl (prev) pipe=%d\n", i); + ipahal_free_dma_mem(&tbl->prev_mem[rlt]); + } + + if (list_empty(&tbl->head_flt_rule_list)) { + if (tbl->curr_mem[rlt].phys_base) { + IPADBG_LOW("reaping flt tbl (curr) pipe=%d\n", + i); + ipahal_free_dma_mem(&tbl->curr_mem[rlt]); + } + } + } +} + +/** + * ipa_prep_flt_tbl_for_cmt() - preparing the flt table for commit + * assign priorities to the rules, calculate their sizes and calculate + * the overall table size + * @ip: the ip address family type + * @tbl: the flt tbl to be prepared + * @pipe_idx: the ep pipe appropriate for the given tbl + * + * Return: 0 on success, negative on failure + */ +static int ipa_prep_flt_tbl_for_cmt(enum ipa_ip_type ip, + struct ipa3_flt_tbl *tbl, int pipe_idx) +{ + struct ipa3_flt_entry *entry; + int prio_i; + int max_prio; + u32 hdr_width; + + tbl->sz[IPA_RULE_HASHABLE] = 0; + tbl->sz[IPA_RULE_NON_HASHABLE] = 0; + + max_prio = ipahal_get_rule_max_priority(); + + prio_i = max_prio; + list_for_each_entry(entry, &tbl->head_flt_rule_list, link) { + + if (entry->rule.max_prio) { + entry->prio = max_prio; + } else { + if (ipahal_rule_decrease_priority(&prio_i)) { + IPAERR("cannot decrease rule priority - %d\n", + prio_i); + return -EPERM; + } + entry->prio = prio_i; + } + + if (ipa3_generate_flt_hw_rule(ip, entry, NULL)) { + IPAERR("failed to calculate HW FLT rule size\n"); + return -EPERM; + } + IPADBG_LOW("pipe %d rule_id(handle) %u hw_len %d priority %u\n", + pipe_idx, entry->rule_id, entry->hw_len, entry->prio); + + if (entry->rule.hashable) + tbl->sz[IPA_RULE_HASHABLE] += entry->hw_len; + else + tbl->sz[IPA_RULE_NON_HASHABLE] += entry->hw_len; + } + + if ((tbl->sz[IPA_RULE_HASHABLE] + + tbl->sz[IPA_RULE_NON_HASHABLE]) == 0) { + IPADBG_LOW("flt tbl pipe %d is with zero total size\n", + pipe_idx); + return 0; + } + + hdr_width = ipahal_get_hw_tbl_hdr_width(); + + /* for the header word */ + if (tbl->sz[IPA_RULE_HASHABLE]) + tbl->sz[IPA_RULE_HASHABLE] += hdr_width; + if (tbl->sz[IPA_RULE_NON_HASHABLE]) + tbl->sz[IPA_RULE_NON_HASHABLE] += hdr_width; + + IPADBG_LOW("FLT tbl pipe idx %d hash sz %u non-hash sz %u\n", pipe_idx, + tbl->sz[IPA_RULE_HASHABLE], tbl->sz[IPA_RULE_NON_HASHABLE]); + + return 0; +} + +/** + * ipa_translate_flt_tbl_to_hw_fmt() - translate the flt driver structures + * (rules and tables) to HW format and fill it in the given buffers + * @ip: the ip address family type + * @rlt: the type of the rules to translate (hashable or non-hashable) + * @base: the rules body buffer to be filled + * @hdr: the rules header (addresses/offsets) buffer to be filled + * @body_ofst: the offset of the rules body from the rules header at + * ipa sram + * + * Returns: 0 on success, negative on failure + * + * caller needs to hold any needed locks to ensure integrity + * + */ +static int ipa_translate_flt_tbl_to_hw_fmt(enum ipa_ip_type ip, + enum ipa_rule_type rlt, u8 *base, u8 *hdr, u32 body_ofst) +{ + u64 offset; + u8 *body_i; + int res; + struct ipa3_flt_entry *entry; + u8 *tbl_mem_buf; + struct ipa_mem_buffer tbl_mem; + struct ipa3_flt_tbl *tbl; + int i; + int hdr_idx = 0; + + body_i = base; + for (i = 0; i < ipa3_ctx->ipa_num_pipes; i++) { + if (!ipa_is_ep_support_flt(i)) + continue; + tbl = &ipa3_ctx->flt_tbl[i][ip]; + if (tbl->sz[rlt] == 0) { + hdr_idx++; + continue; + } + if (tbl->in_sys[rlt] || tbl->force_sys[rlt]) { + /* only body (no header) */ + tbl_mem.size = tbl->sz[rlt] - + ipahal_get_hw_tbl_hdr_width(); + /* Add prefetech buf size. */ + tbl_mem.size += + ipahal_get_hw_prefetch_buf_size(); + if (ipahal_fltrt_allocate_hw_sys_tbl(&tbl_mem)) { + IPAERR("fail to alloc sys tbl of size %d\n", + tbl_mem.size); + goto err; + } + + if (ipahal_fltrt_write_addr_to_hdr(tbl_mem.phys_base, + hdr, hdr_idx, true)) { + IPAERR("fail to wrt sys tbl addr to hdr\n"); + goto hdr_update_fail; + } + + tbl_mem_buf = tbl_mem.base; + + /* generate the rule-set */ + list_for_each_entry(entry, &tbl->head_flt_rule_list, + link) { + if (IPA_FLT_GET_RULE_TYPE(entry) != rlt) + continue; + res = ipa3_generate_flt_hw_rule( + ip, entry, tbl_mem_buf); + if (res) { + IPAERR("failed to gen HW FLT rule\n"); + goto hdr_update_fail; + } + tbl_mem_buf += entry->hw_len; + } + + if (tbl->curr_mem[rlt].phys_base) { + WARN_ON(tbl->prev_mem[rlt].phys_base); + tbl->prev_mem[rlt] = tbl->curr_mem[rlt]; + } + tbl->curr_mem[rlt] = tbl_mem; + } else { + offset = body_i - base + body_ofst; + + /* update the hdr at the right index */ + if (ipahal_fltrt_write_addr_to_hdr(offset, hdr, + hdr_idx, false)) { + IPAERR("fail to wrt lcl tbl ofst to hdr\n"); + goto hdr_update_fail; + } + + /* generate the rule-set */ + list_for_each_entry(entry, &tbl->head_flt_rule_list, + link) { + if (IPA_FLT_GET_RULE_TYPE(entry) != rlt) + continue; + res = ipa3_generate_flt_hw_rule( + ip, entry, body_i); + if (res) { + IPAERR("failed to gen HW FLT rule\n"); + goto err; + } + body_i += entry->hw_len; + } + + /** + * advance body_i to next table alignment as local + * tables are order back-to-back + */ + body_i += ipahal_get_lcl_tbl_addr_alignment(); + body_i = (u8 *)((long)body_i & + ~ipahal_get_lcl_tbl_addr_alignment()); + } + hdr_idx++; + } + + return 0; + +hdr_update_fail: + ipahal_free_dma_mem(&tbl_mem); +err: + return -EPERM; +} + +/** + * ipa_generate_flt_hw_tbl_img() - generates the flt hw tbls. + * headers and bodies are being created into buffers that will be filled into + * the local memory (sram) + * @ip: the ip address family type + * @alloc_params: In and Out parameters for the allocations of the buffers + * 4 buffers: hdr and bdy, each hashable and non-hashable + * + * Return: 0 on success, negative on failure + */ +static int ipa_generate_flt_hw_tbl_img(enum ipa_ip_type ip, + struct ipahal_fltrt_alloc_imgs_params *alloc_params) +{ + u32 hash_bdy_start_ofst, nhash_bdy_start_ofst; + int rc = 0; + + if (ip == IPA_IP_v4) { + nhash_bdy_start_ofst = IPA_MEM_PART(apps_v4_flt_nhash_ofst) - + IPA_MEM_PART(v4_flt_nhash_ofst); + hash_bdy_start_ofst = IPA_MEM_PART(apps_v4_flt_hash_ofst) - + IPA_MEM_PART(v4_flt_hash_ofst); + } else { + nhash_bdy_start_ofst = IPA_MEM_PART(apps_v6_flt_nhash_ofst) - + IPA_MEM_PART(v6_flt_nhash_ofst); + hash_bdy_start_ofst = IPA_MEM_PART(apps_v6_flt_hash_ofst) - + IPA_MEM_PART(v6_flt_hash_ofst); + } + + if (ipahal_fltrt_allocate_hw_tbl_imgs(alloc_params)) { + IPAERR_RL("fail to allocate FLT HW TBL images. IP %d\n", ip); + rc = -ENOMEM; + goto allocate_failed; + } + + if (ipa_translate_flt_tbl_to_hw_fmt(ip, IPA_RULE_HASHABLE, + alloc_params->hash_bdy.base, alloc_params->hash_hdr.base, + hash_bdy_start_ofst)) { + IPAERR_RL("fail to translate hashable flt tbls to hw format\n"); + rc = -EPERM; + goto translate_fail; + } + if (ipa_translate_flt_tbl_to_hw_fmt(ip, IPA_RULE_NON_HASHABLE, + alloc_params->nhash_bdy.base, alloc_params->nhash_hdr.base, + nhash_bdy_start_ofst)) { + IPAERR_RL("fail to translate non-hash flt tbls to hw format\n"); + rc = -EPERM; + goto translate_fail; + } + + return rc; + +translate_fail: + if (alloc_params->hash_hdr.size) + ipahal_free_dma_mem(&alloc_params->hash_hdr); + ipahal_free_dma_mem(&alloc_params->nhash_hdr); + if (alloc_params->hash_bdy.size) + ipahal_free_dma_mem(&alloc_params->hash_bdy); + if (alloc_params->nhash_bdy.size) + ipahal_free_dma_mem(&alloc_params->nhash_bdy); +allocate_failed: + return rc; +} + +/** + * ipa_flt_valid_lcl_tbl_size() - validate if the space allocated for flt + * tbl bodies at the sram is enough for the commit + * @ipt: the ip address family type + * @rlt: the rule type (hashable or non-hashable) + * @aligned_sz_lcl_tbls: calculated required aligned size + * + * Return: true if enough space available or false in other cases + */ +static bool ipa_flt_valid_lcl_tbl_size(enum ipa_ip_type ipt, + enum ipa_rule_type rlt, u32 aligned_sz_lcl_tbls) +{ + u16 avail; + + if (ipt == IPA_IP_v4) + avail = (rlt == IPA_RULE_HASHABLE) ? + IPA_MEM_PART(apps_v4_flt_hash_size) : + IPA_MEM_PART(apps_v4_flt_nhash_size); + else + avail = (rlt == IPA_RULE_HASHABLE) ? + IPA_MEM_PART(apps_v6_flt_hash_size) : + IPA_MEM_PART(apps_v6_flt_nhash_size); + + if (aligned_sz_lcl_tbls <= avail) + return true; + + IPADBG("tbl too big, needed %d avail %d ipt %d rlt %d\n", + aligned_sz_lcl_tbls, avail, ipt, rlt); + return false; +} + +/** + * ipa_flt_alloc_cmd_buffers() - alloc descriptors and imm cmds + * payload pointers buffers for headers and bodies of flt structure + * as well as place for flush imm. + * @ipt: the ip address family type + * @entries: the number of entries + * @desc: [OUT] descriptor buffer + * @cmd: [OUT] imm commands payload pointers buffer + * + * Return: 0 on success, negative on failure + */ +static int ipa_flt_alloc_cmd_buffers(enum ipa_ip_type ip, u16 entries, + struct ipa3_desc **desc, struct ipahal_imm_cmd_pyld ***cmd_pyld) +{ + *desc = kcalloc(entries, sizeof(**desc), GFP_ATOMIC); + if (*desc == NULL) { + IPAERR("fail to alloc desc blob ip %d\n", ip); + goto fail_desc_alloc; + } + + *cmd_pyld = kcalloc(entries, sizeof(**cmd_pyld), GFP_ATOMIC); + if (*cmd_pyld == NULL) { + IPAERR("fail to alloc cmd pyld blob ip %d\n", ip); + goto fail_cmd_alloc; + } + + return 0; + +fail_cmd_alloc: + kfree(*desc); +fail_desc_alloc: + return -ENOMEM; +} + +/** + * ipa_flt_skip_pipe_config() - skip ep flt configuration or not? + * will skip according to pre-configuration or modem pipes + * @pipe: the EP pipe index + * + * Return: true if to skip, false otherwize + */ +static bool ipa_flt_skip_pipe_config(int pipe) +{ + struct ipa3_ep_context *ep; + + if (ipa_is_modem_pipe(pipe)) { + IPADBG_LOW("skip %d - modem owned pipe\n", pipe); + return true; + } + + if (ipa3_ctx->skip_ep_cfg_shadow[pipe]) { + IPADBG_LOW("skip %d\n", pipe); + return true; + } + + ep = &ipa3_ctx->ep[pipe]; + + if ((ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_PROD) == pipe + && ipa3_ctx->modem_cfg_emb_pipe_flt) + && ep->client == IPA_CLIENT_APPS_WAN_PROD) { + IPADBG_LOW("skip %d\n", pipe); + return true; + } + + if ((ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_PROD) == pipe + && ipa3_ctx->modem_cfg_emb_pipe_flt) + && ep->client == IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_PROD) { + IPADBG_LOW("skip %d\n", pipe); + return true; + } + + return false; +} + +/** + * __ipa_commit_flt_v3() - commit flt tables to the hw + * commit the headers and the bodies if are local with internal cache flushing. + * The headers (and local bodies) will first be created into dma buffers and + * then written via IC to the SRAM + * @ipt: the ip address family type + * + * Return: 0 on success, negative on failure + */ +int __ipa_commit_flt_v3(enum ipa_ip_type ip) +{ + struct ipahal_fltrt_alloc_imgs_params alloc_params; + int rc = 0; + struct ipa3_desc *desc, *desc_to_send; + struct ipahal_imm_cmd_register_write reg_write_cmd = {0}; + struct ipahal_imm_cmd_dma_shared_mem mem_cmd = {0}; + struct ipahal_imm_cmd_pyld **cmd_pyld; + int num_cmd = 0, remaining_num_cmd = 0, num_cmd_to_send = 0; + int i; + int hdr_idx; + u32 lcl_hash_hdr, lcl_nhash_hdr; + u32 lcl_hash_bdy, lcl_nhash_bdy; + bool lcl_hash, lcl_nhash; + struct ipahal_reg_valmask valmask; + u32 tbl_hdr_width; + struct ipa3_flt_tbl *tbl; + struct ipa3_flt_tbl_nhash_lcl *lcl_tbl; + u16 entries; + struct ipahal_imm_cmd_register_write reg_write_coal_close; + + tbl_hdr_width = ipahal_get_hw_tbl_hdr_width(); + memset(&alloc_params, 0, sizeof(alloc_params)); + alloc_params.ipt = ip; + alloc_params.tbls_num = ipa3_ctx->ep_flt_num; + + if (ip == IPA_IP_v4) { + lcl_hash_hdr = ipa3_ctx->smem_restricted_bytes + + IPA_MEM_PART(v4_flt_hash_ofst) + + tbl_hdr_width; /* to skip the bitmap */ + lcl_nhash_hdr = ipa3_ctx->smem_restricted_bytes + + IPA_MEM_PART(v4_flt_nhash_ofst) + + tbl_hdr_width; /* to skip the bitmap */ + lcl_hash_bdy = ipa3_ctx->smem_restricted_bytes + + IPA_MEM_PART(apps_v4_flt_hash_ofst); + lcl_nhash_bdy = ipa3_ctx->smem_restricted_bytes + + IPA_MEM_PART(apps_v4_flt_nhash_ofst); + lcl_hash = ipa3_ctx->flt_tbl_hash_lcl[IPA_IP_v4]; + lcl_nhash = ipa3_ctx->flt_tbl_nhash_lcl[IPA_IP_v4]; + } else { + lcl_hash_hdr = ipa3_ctx->smem_restricted_bytes + + IPA_MEM_PART(v6_flt_hash_ofst) + + tbl_hdr_width; /* to skip the bitmap */ + lcl_nhash_hdr = ipa3_ctx->smem_restricted_bytes + + IPA_MEM_PART(v6_flt_nhash_ofst) + + tbl_hdr_width; /* to skip the bitmap */ + lcl_hash_bdy = ipa3_ctx->smem_restricted_bytes + + IPA_MEM_PART(apps_v6_flt_hash_ofst); + lcl_nhash_bdy = ipa3_ctx->smem_restricted_bytes + + IPA_MEM_PART(apps_v6_flt_nhash_ofst); + lcl_hash = ipa3_ctx->flt_tbl_hash_lcl[IPA_IP_v6]; + lcl_nhash = ipa3_ctx->flt_tbl_nhash_lcl[IPA_IP_v6]; + } + + for (i = 0; i < ipa3_ctx->ipa_num_pipes; i++) { + if (!ipa_is_ep_support_flt(i)) + continue; + tbl = &ipa3_ctx->flt_tbl[i][ip]; + if (ipa_prep_flt_tbl_for_cmt(ip, tbl, i)) { + rc = -EPERM; + goto prep_failed; + } + + /* First try fitting tables in lcl memory if allowed */ + tbl->force_sys[IPA_RULE_NON_HASHABLE] = false; + + if (!tbl->in_sys[IPA_RULE_HASHABLE] && + tbl->sz[IPA_RULE_HASHABLE]) { + alloc_params.num_lcl_hash_tbls++; + alloc_params.total_sz_lcl_hash_tbls += + tbl->sz[IPA_RULE_HASHABLE]; + alloc_params.total_sz_lcl_hash_tbls -= tbl_hdr_width; + + } + if (!tbl->in_sys[IPA_RULE_NON_HASHABLE] && + tbl->sz[IPA_RULE_NON_HASHABLE]) { + alloc_params.num_lcl_nhash_tbls++; + alloc_params.total_sz_lcl_nhash_tbls += + tbl->sz[IPA_RULE_NON_HASHABLE]; + alloc_params.total_sz_lcl_nhash_tbls -= tbl_hdr_width; + } + } + + if (!ipa_flt_valid_lcl_tbl_size(ip, IPA_RULE_HASHABLE, + ipa_fltrt_get_aligned_lcl_bdy_size(alloc_params.num_lcl_hash_tbls, + alloc_params.total_sz_lcl_hash_tbls))) { + IPAERR_RL("Hash filter table for IP:%d too big to fit in lcl memory\n", + ip); + rc = -EFAULT; + goto fail_size_valid; + } + + /* Check Non-Hash filter tables fits in SRAM, if it is not - move some tables to DDR */ + list_for_each_entry(lcl_tbl, &ipa3_ctx->flt_tbl_nhash_lcl_list[ip], link) { + if (ipa_flt_valid_lcl_tbl_size(ip, IPA_RULE_NON_HASHABLE, + ipa_fltrt_get_aligned_lcl_bdy_size(alloc_params.num_lcl_nhash_tbls, + alloc_params.total_sz_lcl_nhash_tbls)) || + alloc_params.num_lcl_nhash_tbls == 0) + break; + + IPADBG("SRAM partition is too small, move one non-hash table in DDR. " + "IP:%d alloc_params.total_sz_lcl_nhash_tbls = %u\n", + ip, alloc_params.total_sz_lcl_nhash_tbls); + + /* Move lowest priority Eth client to DDR */ + lcl_tbl->tbl->force_sys[IPA_RULE_NON_HASHABLE] = true; + + alloc_params.num_lcl_nhash_tbls--; + alloc_params.total_sz_lcl_nhash_tbls -= lcl_tbl->tbl->sz[IPA_RULE_NON_HASHABLE]; + alloc_params.total_sz_lcl_nhash_tbls += tbl_hdr_width; + } + + if (ipa_generate_flt_hw_tbl_img(ip, &alloc_params)) { + IPAERR_RL("fail to generate FLT HW TBL image. IP %d\n", ip); + rc = -EFAULT; + goto prep_failed; + } + + /* +4: 2 for bodies (hashable and non-hashable), 1 for flushing and 1 + * for closing the colaescing frame + */ + entries = (ipa3_ctx->ep_flt_num) * 2 + 4; + + if (ipa_flt_alloc_cmd_buffers(ip, entries, &desc, &cmd_pyld)) { + rc = -ENOMEM; + goto fail_size_valid; + } + + /* IC to close the coal frame before HPS Clear if coal is enabled */ + if (ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS) != -1 + && !ipa3_ctx->ulso_wa) { + u32 offset = 0; + + i = ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS); + reg_write_coal_close.skip_pipeline_clear = false; + reg_write_coal_close.pipeline_clear_options = IPAHAL_HPS_CLEAR; + if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0) + offset = ipahal_get_reg_ofst( + IPA_AGGR_FORCE_CLOSE); + else + offset = ipahal_get_ep_reg_offset( + IPA_AGGR_FORCE_CLOSE_n, i); + reg_write_coal_close.offset = offset; + ipahal_get_aggr_force_close_valmask(i, &valmask); + reg_write_coal_close.value = valmask.val; + reg_write_coal_close.value_mask = valmask.mask; + cmd_pyld[num_cmd] = ipahal_construct_imm_cmd( + IPA_IMM_CMD_REGISTER_WRITE, + ®_write_coal_close, false); + if (!cmd_pyld[num_cmd]) { + IPAERR("failed to construct coal close IC\n"); + rc = -ENOMEM; + goto fail_reg_write_construct; + } + ipa3_init_imm_cmd_desc(&desc[num_cmd], cmd_pyld[num_cmd]); + ++num_cmd; + } + + /* + * SRAM memory not allocated to hash tables. Sending + * command to hash tables(filer/routing) operation not supported. + */ + if (!ipa3_ctx->ipa_fltrt_not_hashable) { + /* flushing ipa internal hashable flt rules cache */ + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0) { + struct ipahal_reg_fltrt_cache_flush flush_cache; + + memset(&flush_cache, 0, sizeof(flush_cache)); + flush_cache.flt = true; + ipahal_get_fltrt_cache_flush_valmask( + &flush_cache, &valmask); + reg_write_cmd.offset = ipahal_get_reg_ofst( + IPA_FILT_ROUT_CACHE_FLUSH); + } else { + struct ipahal_reg_fltrt_hash_flush flush_hash; + + memset(&flush_hash, 0, sizeof(flush_hash)); + if (ip == IPA_IP_v4) + flush_hash.v4_flt = true; + else + flush_hash.v6_flt = true; + ipahal_get_fltrt_hash_flush_valmask( + &flush_hash, &valmask); + reg_write_cmd.offset = ipahal_get_reg_ofst( + IPA_FILT_ROUT_HASH_FLUSH); + } + reg_write_cmd.skip_pipeline_clear = false; + reg_write_cmd.pipeline_clear_options = IPAHAL_HPS_CLEAR; + reg_write_cmd.value = valmask.val; + reg_write_cmd.value_mask = valmask.mask; + cmd_pyld[num_cmd] = ipahal_construct_imm_cmd( + IPA_IMM_CMD_REGISTER_WRITE, ®_write_cmd, + false); + if (!cmd_pyld[num_cmd]) { + IPAERR( + "fail construct register_write imm cmd: IP %d\n", ip); + rc = -EFAULT; + goto fail_imm_cmd_construct; + } + ipa3_init_imm_cmd_desc(&desc[num_cmd], cmd_pyld[num_cmd]); + ++num_cmd; + } + + hdr_idx = 0; + for (i = 0; i < ipa3_ctx->ipa_num_pipes; i++) { + if (!ipa_is_ep_support_flt(i)) { + IPADBG_LOW("skip %d - not filtering pipe\n", i); + continue; + } + + if (ipa_flt_skip_pipe_config(i)) { + hdr_idx++; + continue; + } + + if (num_cmd + 1 >= entries) { + IPAERR("number of commands is out of range: IP = %d\n", + ip); + rc = -ENOBUFS; + goto fail_imm_cmd_construct; + } + + IPADBG_LOW("Prepare imm cmd for hdr at index %d for pipe %d\n", + hdr_idx, i); + + mem_cmd.is_read = false; + mem_cmd.skip_pipeline_clear = false; + mem_cmd.pipeline_clear_options = IPAHAL_HPS_CLEAR; + mem_cmd.size = tbl_hdr_width; + mem_cmd.system_addr = alloc_params.nhash_hdr.phys_base + + hdr_idx * tbl_hdr_width; + mem_cmd.local_addr = lcl_nhash_hdr + + hdr_idx * tbl_hdr_width; + cmd_pyld[num_cmd] = ipahal_construct_imm_cmd( + IPA_IMM_CMD_DMA_SHARED_MEM, &mem_cmd, false); + if (!cmd_pyld[num_cmd]) { + IPAERR("fail construct dma_shared_mem cmd: IP = %d\n", + ip); + rc = -ENOMEM; + goto fail_imm_cmd_construct; + } + ipa3_init_imm_cmd_desc(&desc[num_cmd], cmd_pyld[num_cmd]); + ++num_cmd; + + /* + * SRAM memory not allocated to hash tables. Sending command + * to hash tables(filer/routing) operation not supported. + */ + if (!ipa3_ctx->ipa_fltrt_not_hashable) { + mem_cmd.is_read = false; + mem_cmd.skip_pipeline_clear = false; + mem_cmd.pipeline_clear_options = IPAHAL_HPS_CLEAR; + mem_cmd.size = tbl_hdr_width; + mem_cmd.system_addr = alloc_params.hash_hdr.phys_base + + hdr_idx * tbl_hdr_width; + mem_cmd.local_addr = lcl_hash_hdr + + hdr_idx * tbl_hdr_width; + cmd_pyld[num_cmd] = ipahal_construct_imm_cmd( + IPA_IMM_CMD_DMA_SHARED_MEM, + &mem_cmd, false); + if (!cmd_pyld[num_cmd]) { + IPAERR( + "fail construct dma_shared_mem cmd: IP = %d\n", + ip); + rc = -ENOMEM; + goto fail_imm_cmd_construct; + } + ipa3_init_imm_cmd_desc(&desc[num_cmd], + cmd_pyld[num_cmd]); + ++num_cmd; + } + ++hdr_idx; + } + + if (lcl_nhash && alloc_params.num_lcl_nhash_tbls > 0) { + if (num_cmd >= entries) { + IPAERR("number of commands is out of range: IP = %d\n", + ip); + rc = -ENOBUFS; + goto fail_imm_cmd_construct; + } + + mem_cmd.is_read = false; + mem_cmd.skip_pipeline_clear = false; + mem_cmd.pipeline_clear_options = IPAHAL_HPS_CLEAR; + mem_cmd.size = alloc_params.nhash_bdy.size; + mem_cmd.system_addr = alloc_params.nhash_bdy.phys_base; + mem_cmd.local_addr = lcl_nhash_bdy; + cmd_pyld[num_cmd] = ipahal_construct_imm_cmd( + IPA_IMM_CMD_DMA_SHARED_MEM, &mem_cmd, false); + if (!cmd_pyld[num_cmd]) { + IPAERR("fail construct dma_shared_mem cmd: IP = %d\n", + ip); + rc = -ENOMEM; + goto fail_imm_cmd_construct; + } + ipa3_init_imm_cmd_desc(&desc[num_cmd], cmd_pyld[num_cmd]); + ++num_cmd; + } + if (lcl_hash) { + if (num_cmd >= entries) { + IPAERR("number of commands is out of range: IP = %d\n", + ip); + rc = -ENOBUFS; + goto fail_imm_cmd_construct; + } + + mem_cmd.is_read = false; + mem_cmd.skip_pipeline_clear = false; + mem_cmd.pipeline_clear_options = IPAHAL_HPS_CLEAR; + mem_cmd.size = alloc_params.hash_bdy.size; + mem_cmd.system_addr = alloc_params.hash_bdy.phys_base; + mem_cmd.local_addr = lcl_hash_bdy; + cmd_pyld[num_cmd] = ipahal_construct_imm_cmd( + IPA_IMM_CMD_DMA_SHARED_MEM, &mem_cmd, false); + if (!cmd_pyld[num_cmd]) { + IPAERR("fail construct dma_shared_mem cmd: IP = %d\n", + ip); + rc = -ENOMEM; + goto fail_imm_cmd_construct; + } + ipa3_init_imm_cmd_desc(&desc[num_cmd], cmd_pyld[num_cmd]); + ++num_cmd; + } + + remaining_num_cmd = num_cmd; + desc_to_send = desc; + + /* + * Avoid sending longs chain that may surpass number of TLVs available + * for the system pipe. + */ + while (remaining_num_cmd > 0) { + num_cmd_to_send = + remaining_num_cmd > IPA_FLT_MAX_IMM_CMD_CHAIN_LENGTH ? + IPA_FLT_MAX_IMM_CMD_CHAIN_LENGTH : remaining_num_cmd; + remaining_num_cmd -= num_cmd_to_send; + + if (ipa3_send_cmd(num_cmd_to_send, desc_to_send)) { + IPAERR("fail to send immediate command batch\n"); + rc = -EFAULT; + goto fail_imm_cmd_construct; + } + desc_to_send += num_cmd_to_send; + } + + IPADBG_LOW("Hashable HEAD\n"); + IPA_DUMP_BUFF(alloc_params.hash_hdr.base, + alloc_params.hash_hdr.phys_base, alloc_params.hash_hdr.size); + + IPADBG_LOW("Non-Hashable HEAD\n"); + IPA_DUMP_BUFF(alloc_params.nhash_hdr.base, + alloc_params.nhash_hdr.phys_base, alloc_params.nhash_hdr.size); + + if (alloc_params.hash_bdy.size) { + IPADBG_LOW("Hashable BODY\n"); + IPA_DUMP_BUFF(alloc_params.hash_bdy.base, + alloc_params.hash_bdy.phys_base, + alloc_params.hash_bdy.size); + } + + if (alloc_params.nhash_bdy.size) { + IPADBG_LOW("Non-Hashable BODY\n"); + IPA_DUMP_BUFF(alloc_params.nhash_bdy.base, + alloc_params.nhash_bdy.phys_base, + alloc_params.nhash_bdy.size); + } + + __ipa_reap_sys_flt_tbls(ip, IPA_RULE_HASHABLE); + __ipa_reap_sys_flt_tbls(ip, IPA_RULE_NON_HASHABLE); + +fail_imm_cmd_construct: + for (i = 0 ; i < num_cmd ; i++) + ipahal_destroy_imm_cmd(cmd_pyld[i]); +fail_reg_write_construct: + kfree(desc); + kfree(cmd_pyld); +fail_size_valid: + if (alloc_params.hash_hdr.size) + ipahal_free_dma_mem(&alloc_params.hash_hdr); + ipahal_free_dma_mem(&alloc_params.nhash_hdr); + if (alloc_params.hash_bdy.size) + ipahal_free_dma_mem(&alloc_params.hash_bdy); + if (alloc_params.nhash_bdy.size) + ipahal_free_dma_mem(&alloc_params.nhash_bdy); +prep_failed: + return rc; +} + +static int __ipa_validate_flt_rule(const struct ipa_flt_rule_i *rule, + struct ipa3_rt_tbl **rt_tbl, enum ipa_ip_type ip) +{ + int index; + + if (rule->action != IPA_PASS_TO_EXCEPTION) { + if (!rule->eq_attrib_type) { + if (!rule->rt_tbl_hdl) { + IPAERR_RL("invalid RT tbl\n"); + goto error; + } + + *rt_tbl = ipa3_id_find(rule->rt_tbl_hdl); + if (*rt_tbl == NULL) { + IPAERR_RL("RT tbl not found\n"); + goto error; + } + + if ((*rt_tbl)->cookie != IPA_RT_TBL_COOKIE) { + IPAERR_RL("RT table cookie is invalid\n"); + goto error; + } + } else { + if (rule->rt_tbl_idx > ((ip == IPA_IP_v4) ? + IPA_MEM_PART(v4_modem_rt_index_hi) : + IPA_MEM_PART(v6_modem_rt_index_hi))) { + IPAERR_RL("invalid RT tbl\n"); + goto error; + } + } + } else { + if (rule->rt_tbl_idx > 0) { + IPAERR_RL("invalid RT tbl\n"); + goto error; + } + } + + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_0) { + if (rule->pdn_idx) { + if (rule->action == IPA_PASS_TO_EXCEPTION || + rule->action == IPA_PASS_TO_ROUTING) { + IPAERR_RL( + "PDN index should be 0 when action is not pass to NAT\n"); + goto error; + } else { + if (rule->pdn_idx >= ipa3_get_max_pdn()) { + IPAERR_RL("PDN index %d is too large\n", + rule->pdn_idx); + goto error; + } + } + } + } + + if (rule->rule_id) { + if ((rule->rule_id < ipahal_get_rule_id_hi_bit()) || + (rule->rule_id >= ((ipahal_get_rule_id_hi_bit()<<1)-1))) { + IPAERR_RL("invalid rule_id provided 0x%x\n" + "rule_id with bit 0x%x are auto generated\n", + rule->rule_id, ipahal_get_rule_id_hi_bit()); + goto error; + } + } + + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_5) { + if (rule->enable_stats && rule->cnt_idx) { + if (!ipahal_is_rule_cnt_id_valid(rule->cnt_idx)) { + IPAERR_RL( + "invalid cnt_idx %hhu out of range\n", + rule->cnt_idx); + goto error; + } + index = rule->cnt_idx - 1; + if (!ipa3_ctx->flt_rt_counters.used_hw[index]) { + IPAERR_RL( + "invalid cnt_idx %hhu not alloc by driver\n", + rule->cnt_idx); + goto error; + } + } + } else { + if (rule->enable_stats) { + IPAERR_RL( + "enable_stats won't support on ipa_hw_type %d\n", + ipa3_ctx->ipa_hw_type); + goto error; + } + } + return 0; + +error: + return -EPERM; +} + +static int __ipa_create_flt_entry(struct ipa3_flt_entry **entry, + const struct ipa_flt_rule_i *rule, struct ipa3_rt_tbl *rt_tbl, + struct ipa3_flt_tbl *tbl, bool user) +{ + int id; + + *entry = kmem_cache_zalloc(ipa3_ctx->flt_rule_cache, GFP_KERNEL); + if (!*entry) + goto error; + INIT_LIST_HEAD(&((*entry)->link)); + (*entry)->rule = *rule; + (*entry)->cookie = IPA_FLT_COOKIE; + (*entry)->rt_tbl = rt_tbl; + (*entry)->tbl = tbl; + if (rule->rule_id) { + id = rule->rule_id; + } else { + id = ipa3_alloc_rule_id(tbl->rule_ids); + if (id < 0) { + IPAERR_RL("failed to allocate rule id\n"); + WARN_ON_RATELIMIT_IPA(1); + goto rule_id_fail; + } + } + (*entry)->rule_id = id; + (*entry)->ipacm_installed = user; + if (rule->enable_stats) + (*entry)->cnt_idx = rule->cnt_idx; + else + (*entry)->cnt_idx = 0; + return 0; + +rule_id_fail: + kmem_cache_free(ipa3_ctx->flt_rule_cache, *entry); +error: + return -EPERM; +} + +static int __ipa_finish_flt_rule_add(struct ipa3_flt_tbl *tbl, + struct ipa3_flt_entry *entry, u32 *rule_hdl) +{ + int id; + + if (tbl->rule_cnt < IPA_RULE_CNT_MAX) + tbl->rule_cnt++; + else + return -EINVAL; + if (entry->rt_tbl) + entry->rt_tbl->ref_cnt++; + id = ipa3_id_alloc(entry); + if (id < 0) { + IPAERR_RL("failed to add to tree\n"); + WARN_ON_RATELIMIT_IPA(1); + goto ipa_insert_failed; + } + *rule_hdl = id; + entry->id = id; + IPADBG_LOW("add flt rule rule_cnt=%d\n", tbl->rule_cnt); + + return 0; +ipa_insert_failed: + if (entry->rt_tbl) + entry->rt_tbl->ref_cnt--; + tbl->rule_cnt--; + return -EPERM; +} + +static int __ipa_add_flt_rule(struct ipa3_flt_tbl *tbl, enum ipa_ip_type ip, + const struct ipa_flt_rule_i *rule, u8 add_rear, + u32 *rule_hdl, bool user) +{ + struct ipa3_flt_entry *entry; + struct ipa3_rt_tbl *rt_tbl = NULL; + + if (__ipa_validate_flt_rule(rule, &rt_tbl, ip)) + goto error; + + if (__ipa_create_flt_entry(&entry, rule, rt_tbl, tbl, user)) + goto error; + + if (add_rear) { + if (tbl->sticky_rear) + list_add_tail(&entry->link, + tbl->head_flt_rule_list.prev); + else + list_add_tail(&entry->link, &tbl->head_flt_rule_list); + } else { + list_add(&entry->link, &tbl->head_flt_rule_list); + } + + if (__ipa_finish_flt_rule_add(tbl, entry, rule_hdl)) + goto ipa_insert_failed; + + return 0; +ipa_insert_failed: + list_del(&entry->link); + /* if rule id was allocated from idr, remove it */ + if ((entry->rule_id < ipahal_get_rule_id_hi_bit()) && + (entry->rule_id >= ipahal_get_low_rule_id())) + idr_remove(entry->tbl->rule_ids, entry->rule_id); + kmem_cache_free(ipa3_ctx->flt_rule_cache, entry); + +error: + return -EPERM; +} + +static int __ipa_add_flt_rule_after(struct ipa3_flt_tbl *tbl, + const struct ipa_flt_rule_i *rule, + u32 *rule_hdl, + enum ipa_ip_type ip, + struct ipa3_flt_entry **add_after_entry) +{ + struct ipa3_flt_entry *entry; + struct ipa3_rt_tbl *rt_tbl = NULL; + + if (!*add_after_entry) + goto error; + + if (rule == NULL || rule_hdl == NULL) { + IPAERR_RL("bad parms rule=%pK rule_hdl=%pK\n", rule, + rule_hdl); + goto error; + } + + if (__ipa_validate_flt_rule(rule, &rt_tbl, ip)) + goto error; + + if (__ipa_create_flt_entry(&entry, rule, rt_tbl, tbl, true)) + goto error; + + list_add(&entry->link, &((*add_after_entry)->link)); + + if (__ipa_finish_flt_rule_add(tbl, entry, rule_hdl)) + goto ipa_insert_failed; + + /* + * prepare for next insertion + */ + *add_after_entry = entry; + + return 0; + +ipa_insert_failed: + list_del(&entry->link); + /* if rule id was allocated from idr, remove it */ + if ((entry->rule_id < ipahal_get_rule_id_hi_bit()) && + (entry->rule_id >= ipahal_get_low_rule_id())) + idr_remove(entry->tbl->rule_ids, entry->rule_id); + kmem_cache_free(ipa3_ctx->flt_rule_cache, entry); + +error: + *add_after_entry = NULL; + return -EPERM; +} + +static int __ipa_del_flt_rule(u32 rule_hdl) +{ + struct ipa3_flt_entry *entry; + int id; + + entry = ipa3_id_find(rule_hdl); + if (entry == NULL) { + IPAERR_RL("lookup failed\n"); + return -EINVAL; + } + + if (entry->cookie != IPA_FLT_COOKIE) { + IPAERR_RL("bad params\n"); + return -EINVAL; + } + id = entry->id; + + list_del(&entry->link); + entry->tbl->rule_cnt--; + if (entry->rt_tbl && !ipa3_check_idr_if_freed(entry->rt_tbl)) + entry->rt_tbl->ref_cnt--; + IPADBG("del flt rule rule_cnt=%d rule_id=%d\n", + entry->tbl->rule_cnt, entry->rule_id); + entry->cookie = 0; + /* if rule id was allocated from idr, remove it */ + if ((entry->rule_id < ipahal_get_rule_id_hi_bit()) && + (entry->rule_id >= ipahal_get_low_rule_id())) + idr_remove(entry->tbl->rule_ids, entry->rule_id); + + kmem_cache_free(ipa3_ctx->flt_rule_cache, entry); + + /* remove the handle from the database */ + ipa3_id_remove(id); + + return 0; +} + +static int __ipa_mdfy_flt_rule(struct ipa_flt_rule_mdfy_i *frule, + enum ipa_ip_type ip) +{ + struct ipa3_flt_entry *entry; + struct ipa3_rt_tbl *rt_tbl = NULL; + + entry = ipa3_id_find(frule->rule_hdl); + if (entry == NULL) { + IPAERR_RL("lookup failed\n"); + goto error; + } + + if (entry->cookie != IPA_FLT_COOKIE) { + IPAERR_RL("bad params\n"); + goto error; + } + + if (__ipa_validate_flt_rule(&frule->rule, &rt_tbl, ip)) + goto error; + + if (entry->rt_tbl) + entry->rt_tbl->ref_cnt--; + + entry->rule = frule->rule; + entry->rt_tbl = rt_tbl; + if (entry->rt_tbl) + entry->rt_tbl->ref_cnt++; + entry->hw_len = 0; + entry->prio = 0; + if (frule->rule.enable_stats) + entry->cnt_idx = frule->rule.cnt_idx; + else + entry->cnt_idx = 0; + + return 0; + +error: + return -EPERM; +} + +static int __ipa_add_flt_get_ep_idx(enum ipa_client_type ep, int *ipa_ep_idx) +{ + *ipa_ep_idx = ipa_get_ep_mapping(ep); + if (*ipa_ep_idx < 0 || *ipa_ep_idx >= ipa3_get_max_num_pipes()) { + IPAERR_RL("ep not valid ep=%d\n", ep); + return -EINVAL; + } + if (ipa3_ctx->ep[*ipa_ep_idx].valid == 0) + IPAERR_RL("ep not connected ep_idx=%d\n", *ipa_ep_idx); + + if (!ipa_is_ep_support_flt(*ipa_ep_idx)) { + IPAERR_RL("ep do not support filtering ep=%d\n", ep); + return -EINVAL; + } + + return 0; +} + +static int __ipa_add_ep_flt_rule(enum ipa_ip_type ip, enum ipa_client_type ep, + const struct ipa_flt_rule_i *rule, u8 add_rear, + u32 *rule_hdl, bool user) +{ + struct ipa3_flt_tbl *tbl; + int ipa_ep_idx; + + if (rule == NULL || rule_hdl == NULL || ep >= IPA_CLIENT_MAX) { + IPAERR_RL("bad parms rule=%pK rule_hdl=%pK ep=%d\n", rule, + rule_hdl, ep); + return -EINVAL; + } + + if (__ipa_add_flt_get_ep_idx(ep, &ipa_ep_idx)) + return -EINVAL; + + if (ipa_ep_idx >= ipa3_get_max_num_pipes()) { + IPAERR_RL("invalid ipa_ep_idx=%d\n", ipa_ep_idx); + return -EINVAL; + } + + tbl = &ipa3_ctx->flt_tbl[ipa_ep_idx][ip]; + IPADBG_LOW("add ep flt rule ip=%d ep=%d\n", ip, ep); + + return __ipa_add_flt_rule(tbl, ip, rule, add_rear, rule_hdl, user); +} + +static void __ipa_convert_flt_rule_in(struct ipa_flt_rule rule_in, + struct ipa_flt_rule_i *rule_out) +{ + if (unlikely(sizeof(struct ipa_flt_rule) > + sizeof(struct ipa_flt_rule_i))) { + IPAERR_RL("invalid size in:%d size out:%d\n", + sizeof(struct ipa_flt_rule_i), + sizeof(struct ipa_flt_rule)); + return; + } + memset(rule_out, 0, sizeof(struct ipa_flt_rule_i)); + memcpy(rule_out, &rule_in, sizeof(struct ipa_flt_rule)); +} + +static void __ipa_convert_flt_rule_out(struct ipa_flt_rule_i rule_in, + struct ipa_flt_rule *rule_out) +{ + if (unlikely(sizeof(struct ipa_flt_rule) > + sizeof(struct ipa_flt_rule_i))) { + IPAERR_RL("invalid size in:%d size out:%d\n", + sizeof(struct ipa_flt_rule_i), + sizeof(struct ipa_flt_rule)); + return; + } + memset(rule_out, 0, sizeof(struct ipa_flt_rule)); + memcpy(rule_out, &rule_in, sizeof(struct ipa_flt_rule)); +} + +static void __ipa_convert_flt_mdfy_in(struct ipa_flt_rule_mdfy rule_in, + struct ipa_flt_rule_mdfy_i *rule_out) +{ + if (unlikely(sizeof(struct ipa_flt_rule_mdfy) > + sizeof(struct ipa_flt_rule_mdfy_i))) { + IPAERR_RL("invalid size in:%d size out:%d\n", + sizeof(struct ipa_flt_rule_mdfy), + sizeof(struct ipa_flt_rule_mdfy_i)); + return; + } + memset(rule_out, 0, sizeof(struct ipa_flt_rule_mdfy_i)); + memcpy(&rule_out->rule, &rule_in.rule, + sizeof(struct ipa_flt_rule)); + rule_out->rule_hdl = rule_in.rule_hdl; + rule_out->status = rule_in.status; +} + +static void __ipa_convert_flt_mdfy_out(struct ipa_flt_rule_mdfy_i rule_in, + struct ipa_flt_rule_mdfy *rule_out) +{ + if (unlikely(sizeof(struct ipa_flt_rule_mdfy) > + sizeof(struct ipa_flt_rule_mdfy_i))) { + IPAERR_RL("invalid size in:%d size out:%d\n", + sizeof(struct ipa_flt_rule_mdfy), + sizeof(struct ipa_flt_rule_mdfy_i)); + return; + } + memset(rule_out, 0, sizeof(struct ipa_flt_rule_mdfy)); + memcpy(&rule_out->rule, &rule_in.rule, + sizeof(struct ipa_flt_rule)); + rule_out->rule_hdl = rule_in.rule_hdl; + rule_out->status = rule_in.status; +} + +/** + * ipa3_add_flt_rule() - Add the specified filtering rules to SW and optionally + * commit to IPA HW + * @rules: [inout] set of filtering rules to add + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_add_flt_rule(struct ipa_ioc_add_flt_rule *rules) +{ + return ipa3_add_flt_rule_usr(rules, false); +} + +/** + * ipa3_add_flt_rule_v2() - Add the specified filtering rules to + * SW and optionally commit to IPA HW + * @rules: [inout] set of filtering rules to add + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_add_flt_rule_v2(struct ipa_ioc_add_flt_rule_v2 *rules) +{ + return ipa3_add_flt_rule_usr_v2(rules, false); +} + + +/** + * ipa3_add_flt_rule_usr() - Add the specified filtering rules to + * SW and optionally commit to IPA HW + * @rules: [inout] set of filtering rules to add + * @user_only: [in] indicate rules installed by userspace + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_add_flt_rule_usr(struct ipa_ioc_add_flt_rule *rules, bool user_only) +{ + int i; + int result; + struct ipa_flt_rule_i rule; + + if (rules == NULL || rules->num_rules == 0 || + rules->ip >= IPA_IP_MAX) { + IPAERR_RL("bad parm\n"); + return -EINVAL; + } + + mutex_lock(&ipa3_ctx->lock); + for (i = 0; i < rules->num_rules; i++) { + if (!rules->global) { + /* if hashing not supported, all table entry + * are non-hash tables + */ + if (ipa3_ctx->ipa_fltrt_not_hashable) + rules->rules[i].rule.hashable = false; + __ipa_convert_flt_rule_in( + rules->rules[i].rule, &rule); + result = __ipa_add_ep_flt_rule(rules->ip, + rules->ep, + &rule, + rules->rules[i].at_rear, + &rules->rules[i].flt_rule_hdl, + user_only); + __ipa_convert_flt_rule_out(rule, + &rules->rules[i].rule); + } else + result = -1; + if (result) { + IPAERR_RL("failed to add flt rule %d\n", i); + rules->rules[i].status = IPA_FLT_STATUS_OF_ADD_FAILED; + } else { + rules->rules[i].status = 0; + } + } + + if (rules->global) { + IPAERR_RL("no support for global filter rules\n"); + result = -EPERM; + goto bail; + } + + if (rules->commit) + if (ipa3_ctx->ctrl->ipa3_commit_flt(rules->ip)) { + result = -EPERM; + goto bail; + } + result = 0; +bail: + mutex_unlock(&ipa3_ctx->lock); + + return result; +} + +/** + * ipa3_add_flt_rule_usr_v2() - Add the specified filtering + * rules to SW and optionally commit to IPA HW + * @rules: [inout] set of filtering rules to add + * @user_only: [in] indicate rules installed by userspace + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_add_flt_rule_usr_v2(struct ipa_ioc_add_flt_rule_v2 + *rules, bool user_only) +{ + int i; + int result; + + if (rules == NULL || rules->num_rules == 0 || + rules->ip >= IPA_IP_MAX) { + IPAERR_RL("bad parm\n"); + return -EINVAL; + } + + mutex_lock(&ipa3_ctx->lock); + for (i = 0; i < rules->num_rules; i++) { + if (!rules->global) { + /* if hashing not supported, all table entry + * are non-hash tables + */ + if (ipa3_ctx->ipa_fltrt_not_hashable) + ((struct ipa_flt_rule_add_i *) + rules->rules)[i].rule.hashable = false; + result = __ipa_add_ep_flt_rule(rules->ip, + rules->ep, + &(((struct ipa_flt_rule_add_i *) + rules->rules)[i].rule), + ((struct ipa_flt_rule_add_i *) + rules->rules)[i].at_rear, + &(((struct ipa_flt_rule_add_i *) + rules->rules)[i].flt_rule_hdl), + user_only); + } else + result = -1; + + if (result) { + IPAERR_RL("failed to add flt rule %d\n", i); + ((struct ipa_flt_rule_add_i *) + rules->rules)[i].status = IPA_FLT_STATUS_OF_ADD_FAILED; + } else { + ((struct ipa_flt_rule_add_i *) + rules->rules)[i].status = 0; + } + } + + if (rules->global) { + IPAERR_RL("no support for global filter rules\n"); + result = -EPERM; + goto bail; + } + + if (rules->commit) + if (ipa3_ctx->ctrl->ipa3_commit_flt(rules->ip)) { + result = -EPERM; + goto bail; + } + result = 0; +bail: + mutex_unlock(&ipa3_ctx->lock); + + return result; +} + +/** + * ipa3_add_flt_rule_after() - Add the specified filtering rules to SW after + * the rule which its handle is given and optionally commit to IPA HW + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_add_flt_rule_after(struct ipa_ioc_add_flt_rule_after *rules) +{ + int i; + int result; + struct ipa3_flt_tbl *tbl; + int ipa_ep_idx; + struct ipa3_flt_entry *entry; + struct ipa_flt_rule_i rule; + + if (rules == NULL || rules->num_rules == 0 || + rules->ip >= IPA_IP_MAX) { + IPAERR_RL("bad parm\n"); + return -EINVAL; + } + + if (rules->ep >= IPA_CLIENT_MAX) { + IPAERR_RL("bad parms ep=%d\n", rules->ep); + return -EINVAL; + } + + mutex_lock(&ipa3_ctx->lock); + + if (__ipa_add_flt_get_ep_idx(rules->ep, &ipa_ep_idx)) { + result = -EINVAL; + goto bail; + } + + if (ipa_ep_idx >= ipa3_get_max_num_pipes() || ipa_ep_idx < 0) { + IPAERR_RL("invalid ipa_ep_idx=%u\n", ipa_ep_idx); + result = -EINVAL; + goto bail; + } + + tbl = &ipa3_ctx->flt_tbl[ipa_ep_idx][rules->ip]; + + entry = ipa3_id_find(rules->add_after_hdl); + if (entry == NULL) { + IPAERR_RL("lookup failed\n"); + result = -EINVAL; + goto bail; + } + + if (entry->cookie != IPA_FLT_COOKIE) { + IPAERR_RL("Invalid cookie value = %u flt hdl id = %d\n", + entry->cookie, rules->add_after_hdl); + result = -EINVAL; + goto bail; + } + + if (entry->tbl != tbl) { + IPAERR_RL("given entry does not match the table\n"); + result = -EINVAL; + goto bail; + } + + if (tbl->sticky_rear) + if (&entry->link == tbl->head_flt_rule_list.prev) { + IPAERR_RL("cannot add rule at end of a sticky table"); + result = -EINVAL; + goto bail; + } + + IPADBG("add ep flt rule ip=%d ep=%d after hdl %d\n", + rules->ip, rules->ep, rules->add_after_hdl); + + /* + * we add all rules one after the other, if one insertion fails, it cuts + * the chain (all following will receive fail status) following calls to + * __ipa_add_flt_rule_after will fail (entry == NULL) + */ + + for (i = 0; i < rules->num_rules; i++) { + /* if hashing not supported, all tables are non-hash tables*/ + if (ipa3_ctx->ipa_fltrt_not_hashable) + rules->rules[i].rule.hashable = false; + + __ipa_convert_flt_rule_in( + rules->rules[i].rule, &rule); + + result = __ipa_add_flt_rule_after(tbl, + &rule, + &rules->rules[i].flt_rule_hdl, + rules->ip, + &entry); + + __ipa_convert_flt_rule_out(rule, + &rules->rules[i].rule); + + if (result) { + IPAERR_RL("failed to add flt rule %d\n", i); + rules->rules[i].status = IPA_FLT_STATUS_OF_ADD_FAILED; + } else { + rules->rules[i].status = 0; + } + } + + if (rules->commit) + if (ipa3_ctx->ctrl->ipa3_commit_flt(rules->ip)) { + IPAERR("failed to commit flt rules\n"); + result = -EPERM; + goto bail; + } + result = 0; +bail: + mutex_unlock(&ipa3_ctx->lock); + + return result; +} + +/** + * ipa3_add_flt_rule_after_v2() - Add the specified filtering + * rules to SW after the rule which its handle is given and + * optionally commit to IPA HW + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_add_flt_rule_after_v2(struct ipa_ioc_add_flt_rule_after_v2 + *rules) +{ + int i; + int result; + struct ipa3_flt_tbl *tbl; + int ipa_ep_idx; + struct ipa3_flt_entry *entry; + + if (rules == NULL || rules->num_rules == 0 || + rules->ip >= IPA_IP_MAX) { + IPAERR_RL("bad parm\n"); + return -EINVAL; + } + + if (rules->ep >= IPA_CLIENT_MAX) { + IPAERR_RL("bad parms ep=%d\n", rules->ep); + return -EINVAL; + } + + mutex_lock(&ipa3_ctx->lock); + + if (__ipa_add_flt_get_ep_idx(rules->ep, &ipa_ep_idx)) { + result = -EINVAL; + goto bail; + } + + if (ipa_ep_idx >= ipa3_get_max_num_pipes() || + ipa_ep_idx < 0) { + IPAERR_RL("invalid ipa_ep_idx=%u\n", ipa_ep_idx); + result = -EINVAL; + goto bail; + } + + tbl = &ipa3_ctx->flt_tbl[ipa_ep_idx][rules->ip]; + + entry = ipa3_id_find(rules->add_after_hdl); + if (entry == NULL) { + IPAERR_RL("lookup failed\n"); + result = -EINVAL; + goto bail; + } + + if (entry->cookie != IPA_FLT_COOKIE) { + IPAERR_RL("Invalid cookie value = %u flt hdl id = %d\n", + entry->cookie, rules->add_after_hdl); + result = -EINVAL; + goto bail; + } + + if (entry->tbl != tbl) { + IPAERR_RL("given entry does not match the table\n"); + result = -EINVAL; + goto bail; + } + + if (tbl->sticky_rear) + if (&entry->link == tbl->head_flt_rule_list.prev) { + IPAERR_RL("cannot add rule at end of a sticky table"); + result = -EINVAL; + goto bail; + } + + IPADBG("add ep flt rule ip=%d ep=%d after hdl %d\n", + rules->ip, rules->ep, rules->add_after_hdl); + + /* + * we add all rules one after the other, if one insertion fails, it cuts + * the chain (all following will receive fail status) following calls to + * __ipa_add_flt_rule_after will fail (entry == NULL) + */ + + for (i = 0; i < rules->num_rules; i++) { + /* if hashing not supported, all tables are non-hash tables*/ + if (ipa3_ctx->ipa_fltrt_not_hashable) + ((struct ipa_flt_rule_add_i *) + rules->rules)[i].rule.hashable = false; + result = __ipa_add_flt_rule_after(tbl, + &(((struct ipa_flt_rule_add_i *) + rules->rules)[i].rule), + &(((struct ipa_flt_rule_add_i *) + rules->rules)[i].flt_rule_hdl), + rules->ip, + &entry); + if (result) { + IPAERR_RL("failed to add flt rule %d\n", i); + ((struct ipa_flt_rule_add_i *) + rules->rules)[i].status = IPA_FLT_STATUS_OF_ADD_FAILED; + } else { + ((struct ipa_flt_rule_add_i *) + rules->rules)[i].status = 0; + } + } + + if (rules->commit) + if (ipa3_ctx->ctrl->ipa3_commit_flt(rules->ip)) { + IPAERR("failed to commit flt rules\n"); + result = -EPERM; + goto bail; + } + result = 0; +bail: + mutex_unlock(&ipa3_ctx->lock); + + return result; +} + +/** + * ipa3_del_flt_rule() - Remove the specified filtering rules from SW and + * optionally commit to IPA HW + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_del_flt_rule(struct ipa_ioc_del_flt_rule *hdls) +{ + int i; + int result; + + if (hdls == NULL || hdls->num_hdls == 0 || hdls->ip >= IPA_IP_MAX) { + IPAERR_RL("bad param\n"); + return -EINVAL; + } + + mutex_lock(&ipa3_ctx->lock); + for (i = 0; i < hdls->num_hdls; i++) { + if (__ipa_del_flt_rule(hdls->hdl[i].hdl)) { + IPAERR_RL("failed to del flt rule %i\n", i); + hdls->hdl[i].status = IPA_FLT_STATUS_OF_DEL_FAILED; + } else { + hdls->hdl[i].status = 0; + } + } + + if (hdls->commit) + if (ipa3_ctx->ctrl->ipa3_commit_flt(hdls->ip)) { + result = -EPERM; + goto bail; + } + result = 0; +bail: + mutex_unlock(&ipa3_ctx->lock); + + return result; +} + +/** + * ipa3_mdfy_flt_rule() - Modify the specified filtering rules in SW and + * optionally commit to IPA HW + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_mdfy_flt_rule(struct ipa_ioc_mdfy_flt_rule *hdls) +{ + int i; + int result; + struct ipa_flt_rule_mdfy_i rule; + + if (hdls == NULL || hdls->num_rules == 0 || hdls->ip >= IPA_IP_MAX) { + IPAERR_RL("bad parm\n"); + return -EINVAL; + } + + mutex_lock(&ipa3_ctx->lock); + + for (i = 0; i < hdls->num_rules; i++) { + /* if hashing not supported, all tables are non-hash tables*/ + if (ipa3_ctx->ipa_fltrt_not_hashable) + hdls->rules[i].rule.hashable = false; + + __ipa_convert_flt_mdfy_in(hdls->rules[i], &rule); + + result = __ipa_mdfy_flt_rule(&rule, hdls->ip); + + __ipa_convert_flt_mdfy_out(rule, &hdls->rules[i]); + + if (result) { + IPAERR_RL("failed to mdfy flt rule %d\n", i); + hdls->rules[i].status = IPA_FLT_STATUS_OF_MDFY_FAILED; + } else { + hdls->rules[i].status = 0; + } + } + + if (hdls->commit) + if (ipa3_ctx->ctrl->ipa3_commit_flt(hdls->ip)) { + result = -EPERM; + goto bail; + } + result = 0; +bail: + mutex_unlock(&ipa3_ctx->lock); + + return result; +} + +/** + * ipa3_mdfy_flt_rule_v2() - Modify the specified filtering + * rules in SW and optionally commit to IPA HW + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_mdfy_flt_rule_v2(struct ipa_ioc_mdfy_flt_rule_v2 *hdls) +{ + int i; + int result; + + if (hdls == NULL || hdls->num_rules == 0 || hdls->ip >= IPA_IP_MAX) { + IPAERR_RL("bad parm\n"); + return -EINVAL; + } + + mutex_lock(&ipa3_ctx->lock); + for (i = 0; i < hdls->num_rules; i++) { + /* if hashing not supported, all tables are non-hash tables*/ + if (ipa3_ctx->ipa_fltrt_not_hashable) + ((struct ipa_flt_rule_mdfy_i *) + hdls->rules)[i].rule.hashable = false; + if (__ipa_mdfy_flt_rule(&(((struct ipa_flt_rule_mdfy_i *) + hdls->rules)[i]), hdls->ip)) { + IPAERR_RL("failed to mdfy flt rule %i\n", i); + ((struct ipa_flt_rule_mdfy_i *) + hdls->rules)[i].status = IPA_FLT_STATUS_OF_MDFY_FAILED; + } else { + ((struct ipa_flt_rule_mdfy_i *) + hdls->rules)[i].status = 0; + } + } + + if (hdls->commit) + if (ipa3_ctx->ctrl->ipa3_commit_flt(hdls->ip)) { + result = -EPERM; + goto bail; + } + result = 0; +bail: + mutex_unlock(&ipa3_ctx->lock); + + return result; +} + +/** + * ipa3_commit_flt() - Commit the current SW filtering table of specified type + * to IPA HW + * @ip: [in] the family of routing tables + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_commit_flt(enum ipa_ip_type ip) +{ + int result; + + if (ip >= IPA_IP_MAX) { + IPAERR_RL("bad param\n"); + return -EINVAL; + } + + mutex_lock(&ipa3_ctx->lock); + + if (ipa3_ctx->ctrl->ipa3_commit_flt(ip)) { + result = -EPERM; + goto bail; + } + result = 0; + +bail: + mutex_unlock(&ipa3_ctx->lock); + + return result; +} + +/** + * ipa3_reset_flt() - Reset the current SW filtering table of specified type + * (does not commit to HW) + * @ip: [in] the family of routing tables + * @user_only: [in] indicate rules deleted by userspace + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_reset_flt(enum ipa_ip_type ip, bool user_only) +{ + struct ipa3_flt_tbl *tbl; + struct ipa3_flt_entry *entry; + struct ipa3_flt_entry *next; + int i; + int id; + int rule_id; + + if (ip >= IPA_IP_MAX) { + IPAERR_RL("bad parm\n"); + return -EINVAL; + } + + mutex_lock(&ipa3_ctx->lock); + for (i = 0; i < ipa3_ctx->ipa_num_pipes; i++) { + if (!ipa_is_ep_support_flt(i)) + continue; + + tbl = &ipa3_ctx->flt_tbl[i][ip]; + list_for_each_entry_safe(entry, next, &tbl->head_flt_rule_list, + link) { + if (ipa3_id_find(entry->id) == NULL) { + WARN_ON_RATELIMIT_IPA(1); + mutex_unlock(&ipa3_ctx->lock); + return -EFAULT; + } + + if (!user_only || + entry->ipacm_installed) { + list_del(&entry->link); + entry->tbl->rule_cnt--; + if (entry->rt_tbl && + (!ipa3_check_idr_if_freed( + entry->rt_tbl))) + entry->rt_tbl->ref_cnt--; + /* if rule id was allocated from idr, remove */ + rule_id = entry->rule_id; + id = entry->id; + if ((rule_id < ipahal_get_rule_id_hi_bit()) && + (rule_id >= ipahal_get_low_rule_id())) + idr_remove(entry->tbl->rule_ids, + rule_id); + entry->cookie = 0; + kmem_cache_free(ipa3_ctx->flt_rule_cache, + entry); + + /* remove the handle from the database */ + ipa3_id_remove(id); + } + } + } + + /* commit the change to IPA-HW */ + if (ipa3_ctx->ctrl->ipa3_commit_flt(IPA_IP_v4) || + ipa3_ctx->ctrl->ipa3_commit_flt(IPA_IP_v6)) { + IPAERR("fail to commit flt-rule\n"); + WARN_ON_RATELIMIT_IPA(1); + mutex_unlock(&ipa3_ctx->lock); + return -EPERM; + } + mutex_unlock(&ipa3_ctx->lock); + return 0; +} + +void ipa3_install_dflt_flt_rules(u32 ipa_ep_idx) +{ + struct ipa3_flt_tbl *tbl; + struct ipa3_ep_context *ep; + struct ipa_flt_rule_i rule; + + if (ipa_ep_idx >= ipa3_get_max_num_pipes()) { + IPAERR("invalid ipa_ep_idx=%u\n", ipa_ep_idx); + ipa_assert(); + return; + } + + ep = &ipa3_ctx->ep[ipa_ep_idx]; + + if (!ipa_is_ep_support_flt(ipa_ep_idx)) { + IPADBG("cannot add flt rules to non filtering pipe num %d\n", + ipa_ep_idx); + return; + } + + memset(&rule, 0, sizeof(rule)); + + mutex_lock(&ipa3_ctx->lock); + tbl = &ipa3_ctx->flt_tbl[ipa_ep_idx][IPA_IP_v4]; + rule.action = IPA_PASS_TO_EXCEPTION; + __ipa_add_flt_rule(tbl, IPA_IP_v4, &rule, true, + &ep->dflt_flt4_rule_hdl, false); + ipa3_ctx->ctrl->ipa3_commit_flt(IPA_IP_v4); + tbl->sticky_rear = true; + + tbl = &ipa3_ctx->flt_tbl[ipa_ep_idx][IPA_IP_v6]; + rule.action = IPA_PASS_TO_EXCEPTION; + __ipa_add_flt_rule(tbl, IPA_IP_v6, &rule, true, + &ep->dflt_flt6_rule_hdl, false); + ipa3_ctx->ctrl->ipa3_commit_flt(IPA_IP_v6); + tbl->sticky_rear = true; + mutex_unlock(&ipa3_ctx->lock); +} + +void ipa3_delete_dflt_flt_rules(u32 ipa_ep_idx) +{ + struct ipa3_ep_context *ep = &ipa3_ctx->ep[ipa_ep_idx]; + struct ipa3_flt_tbl *tbl; + + mutex_lock(&ipa3_ctx->lock); + if (ep->dflt_flt4_rule_hdl) { + tbl = &ipa3_ctx->flt_tbl[ipa_ep_idx][IPA_IP_v4]; + __ipa_del_flt_rule(ep->dflt_flt4_rule_hdl); + ipa3_ctx->ctrl->ipa3_commit_flt(IPA_IP_v4); + /* Reset the sticky flag. */ + tbl->sticky_rear = false; + ep->dflt_flt4_rule_hdl = 0; + } + if (ep->dflt_flt6_rule_hdl) { + tbl = &ipa3_ctx->flt_tbl[ipa_ep_idx][IPA_IP_v6]; + __ipa_del_flt_rule(ep->dflt_flt6_rule_hdl); + ipa3_ctx->ctrl->ipa3_commit_flt(IPA_IP_v6); + /* Reset the sticky flag. */ + tbl->sticky_rear = false; + ep->dflt_flt6_rule_hdl = 0; + } + mutex_unlock(&ipa3_ctx->lock); +} + +void ipa3_install_dl_opt_wdi_dpath_flt_rules(u32 ipa_ep_idx, u32 rt_tbl_idx) +{ + struct ipa3_flt_tbl *tbl; + struct ipa3_ep_context *ep; + struct ipa_flt_rule_i rule; + + if (ipa_ep_idx >= ipa3_get_max_num_pipes()) { + IPAERR("invalid ipa_ep_idx=%u\n", ipa_ep_idx); + ipa_assert(); + return; + } + + ep = &ipa3_ctx->ep[ipa_ep_idx]; + + if (!ipa_is_ep_support_flt(ipa_ep_idx)) { + IPADBG("cannot add flt rules to non filtering pipe num %d\n", + ipa_ep_idx); + return; + } + + memset(&rule, 0, sizeof(rule)); + + mutex_lock(&ipa3_ctx->lock); + tbl = &ipa3_ctx->flt_tbl[ipa_ep_idx][IPA_IP_v4]; + rule.eq_attrib_type = true; + rule.eq_attrib.rule_eq_bitmap = 1 << 5; + rule.eq_attrib.num_offset_meq_32 = 1; + rule.action = IPA_PASS_TO_ROUTING; + rule.rt_tbl_idx = rt_tbl_idx; + __ipa_add_flt_rule(tbl, IPA_IP_v4, &rule, false, + &ep->dl_flt4_rule_hdl, false); + ipa3_ctx->ctrl->ipa3_commit_flt(IPA_IP_v4); + + tbl = &ipa3_ctx->flt_tbl[ipa_ep_idx][IPA_IP_v6]; + rule.eq_attrib_type = true; + rule.eq_attrib.rule_eq_bitmap = 1 << 5; + rule.eq_attrib.num_offset_meq_32 = 1; + rule.action = IPA_PASS_TO_ROUTING; + rule.rt_tbl_idx = rt_tbl_idx; + __ipa_add_flt_rule(tbl, IPA_IP_v6, &rule, false, + &ep->dl_flt6_rule_hdl, false); + ipa3_ctx->ctrl->ipa3_commit_flt(IPA_IP_v6); + mutex_unlock(&ipa3_ctx->lock); +} + +void ipa3_delete_dl_opt_wdi_dpath_flt_rules(u32 ipa_ep_idx) +{ + struct ipa3_ep_context *ep = &ipa3_ctx->ep[ipa_ep_idx]; + struct ipa3_flt_tbl *tbl; + + mutex_lock(&ipa3_ctx->lock); + if (ep->dl_flt4_rule_hdl) { + tbl = &ipa3_ctx->flt_tbl[ipa_ep_idx][IPA_IP_v4]; + __ipa_del_flt_rule(ep->dl_flt4_rule_hdl); + ipa3_ctx->ctrl->ipa3_commit_flt(IPA_IP_v4); + ep->dl_flt4_rule_hdl = 0; + } + if (ep->dl_flt6_rule_hdl) { + tbl = &ipa3_ctx->flt_tbl[ipa_ep_idx][IPA_IP_v6]; + __ipa_del_flt_rule(ep->dl_flt6_rule_hdl); + ipa3_ctx->ctrl->ipa3_commit_flt(IPA_IP_v6); + ep->dl_flt6_rule_hdl = 0; + } + mutex_unlock(&ipa3_ctx->lock); +} + +/** + * ipa3_set_flt_tuple_mask() - Sets the flt tuple masking for the given pipe + * Pipe must be for AP EP (not modem) and support filtering + * updates the the filtering masking values without changing the rt ones. + * + * @pipe_idx: filter pipe index to configure the tuple masking + * @tuple: the tuple members masking + * Returns: 0 on success, negative on failure + * + */ +int ipa3_set_flt_tuple_mask(int pipe_idx, struct ipahal_reg_hash_tuple *tuple) +{ + if (!tuple) { + IPAERR_RL("bad tuple\n"); + return -EINVAL; + } + + if (pipe_idx >= ipa3_ctx->ipa_num_pipes || pipe_idx < 0) { + IPAERR("bad pipe index!\n"); + return -EINVAL; + } + + if (!ipa_is_ep_support_flt(pipe_idx)) { + IPAERR("pipe %d not filtering pipe\n", pipe_idx); + return -EINVAL; + } + + if (ipa_is_modem_pipe(pipe_idx)) { + IPAERR("modem pipe tuple is not configured by AP\n"); + return -EINVAL; + } + + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0) { + struct ipahal_reg_fltrt_cache_tuple cache_tuple; + + ipahal_read_reg_n_fields(IPA_FILTER_CACHE_CFG_n, + pipe_idx, &cache_tuple); + cache_tuple.tuple = *tuple; + ipahal_write_reg_n_fields(IPA_FILTER_CACHE_CFG_n, + pipe_idx, &cache_tuple); + } else { + struct ipahal_reg_fltrt_hash_tuple hash_tuple; + + ipahal_read_reg_n_fields(IPA_ENDP_FILTER_ROUTER_HSH_CFG_n, + pipe_idx, &hash_tuple); + hash_tuple.flt = *tuple; + ipahal_write_reg_n_fields(IPA_ENDP_FILTER_ROUTER_HSH_CFG_n, + pipe_idx, &hash_tuple); + } + + return 0; +} + +/** + * ipa3_flt_read_tbl_from_hw() -Read filtering table from IPA HW + * @pipe_idx: IPA endpoint index + * @ip_type: IPv4 or IPv6 table + * @hashable: hashable or non-hashable table + * @entry: array to fill the table entries + * @num_entry: number of entries in entry array. set by the caller to indicate + * entry array size. Then set by this function as an output parameter to + * indicate the number of entries in the array + * + * This function reads the filtering table from IPA SRAM and prepares an array + * of entries. This function is mainly used for debugging purposes. + * + * If empty table or Modem Apps table, zero entries will be returned. + * + * Returns: 0 on success, negative on failure + */ +int ipa3_flt_read_tbl_from_hw(u32 pipe_idx, enum ipa_ip_type ip_type, + bool hashable, struct ipahal_flt_rule_entry entry[], int *num_entry) +{ + void *ipa_sram_mmio; + u64 hdr_base_ofst; + int tbl_entry_idx; + int i; + int res = 0; + u64 tbl_addr; + bool is_sys; + u8 *rule_addr; + struct ipa_mem_buffer *sys_tbl_mem; + int rule_idx; + struct ipa3_flt_tbl *flt_tbl_ptr; + + IPADBG("pipe_idx=%d ip=%d hashable=%d entry=0x%pK num_entry=0x%pK\n", + pipe_idx, ip_type, hashable, entry, num_entry); + + /* + * SRAM memory not allocated to hash tables. Reading of hash table + * rules operation not supported + */ + if (hashable && ipa3_ctx->ipa_fltrt_not_hashable) { + IPAERR_RL("Reading hashable rules not supported\n"); + *num_entry = 0; + return 0; + } + + if (pipe_idx >= ipa3_ctx->ipa_num_pipes || + pipe_idx >= ipa3_get_max_num_pipes() || ip_type >= IPA_IP_MAX || + !entry || !num_entry) { + IPAERR_RL("Invalid pipe_idx=%u\n", pipe_idx); + return -EFAULT; + } + + if (!ipa_is_ep_support_flt(pipe_idx)) { + IPAERR_RL("pipe %d does not support filtering\n", pipe_idx); + return -EINVAL; + } + + flt_tbl_ptr = &ipa3_ctx->flt_tbl[pipe_idx][ip_type]; + /* map IPA SRAM */ + ipa_sram_mmio = ioremap(ipa3_ctx->ipa_wrapper_base + + ipa3_ctx->ctrl->ipa_reg_base_ofst + + ipahal_get_reg_n_ofst(IPA_SW_AREA_RAM_DIRECT_ACCESS_n, + ipa3_ctx->smem_restricted_bytes / 4), + ipa3_ctx->smem_sz); + if (!ipa_sram_mmio) { + IPAERR("fail to ioremap IPA SRAM\n"); + return -ENOMEM; + } + + memset(entry, 0, sizeof(*entry) * (*num_entry)); + if (hashable) { + if (ip_type == IPA_IP_v4) + hdr_base_ofst = + IPA_MEM_PART(v4_flt_hash_ofst); + else + hdr_base_ofst = + IPA_MEM_PART(v6_flt_hash_ofst); + } else { + if (ip_type == IPA_IP_v4) + hdr_base_ofst = + IPA_MEM_PART(v4_flt_nhash_ofst); + else + hdr_base_ofst = + IPA_MEM_PART(v6_flt_nhash_ofst); + } + + /* calculate the index of the tbl entry */ + tbl_entry_idx = 1; /* skip the bitmap */ + for (i = 0; i < pipe_idx; i++) + if (ipa3_ctx->ep_flt_bitmap & (1 << i)) + tbl_entry_idx++; + + IPADBG("hdr_base_ofst=0x%llx tbl_entry_idx=%d\n", + hdr_base_ofst, tbl_entry_idx); + + res = ipahal_fltrt_read_addr_from_hdr(ipa_sram_mmio + hdr_base_ofst, + tbl_entry_idx, &tbl_addr, &is_sys); + if (res) { + IPAERR("failed to read table address from header structure\n"); + goto bail; + } + IPADBG("flt tbl ep=%d: tbl_addr=0x%llx is_sys=%d\n", + pipe_idx, tbl_addr, is_sys); + if (!tbl_addr) { + IPAERR("invalid flt tbl addr\n"); + res = -EFAULT; + goto bail; + } + + /* for tables resides in DDR access it from the virtual memory */ + if (is_sys) { + sys_tbl_mem = + &flt_tbl_ptr->curr_mem[hashable ? IPA_RULE_HASHABLE : + IPA_RULE_NON_HASHABLE]; + if (sys_tbl_mem->phys_base && + sys_tbl_mem->phys_base != tbl_addr) { + IPAERR("mismatch addr: parsed=%llx sw=%pad\n", + tbl_addr, &sys_tbl_mem->phys_base); + } + if (sys_tbl_mem->phys_base) + rule_addr = sys_tbl_mem->base; + else + rule_addr = NULL; + } else { + rule_addr = ipa_sram_mmio + hdr_base_ofst + tbl_addr; + } + + IPADBG("First rule addr 0x%pK\n", rule_addr); + + if (!rule_addr) { + /* Modem table in system memory or empty table */ + *num_entry = 0; + goto bail; + } + + rule_idx = 0; + while (rule_idx < *num_entry) { + res = ipahal_flt_parse_hw_rule(rule_addr, &entry[rule_idx]); + if (res) { + IPAERR("failed parsing flt rule\n"); + goto bail; + } + + IPADBG("rule_size=%d\n", entry[rule_idx].rule_size); + if (!entry[rule_idx].rule_size) + break; + + rule_addr += entry[rule_idx].rule_size; + rule_idx++; + } + *num_entry = rule_idx; +bail: + iounmap(ipa_sram_mmio); + return 0; +} + +int ipa_flt_sram_set_client_prio_high(enum ipa_client_type client) +{ + int ipa_ep_idx = IPA_EP_NOT_ALLOCATED; + enum ipa_ip_type ip; + + /* allow setting high priority only to ETH clients */ + if (!IPA_CLIENT_IS_ETH_PROD(client)) { + IPAERR("Operation not permitted for non ETH clients\n"); + return -EINVAL; + } + + ipa_ep_idx = ipa_get_ep_mapping(client); + if (ipa_ep_idx == IPA_EP_NOT_ALLOCATED) + return -EINVAL; + + if (!ipa_is_ep_support_flt(ipa_ep_idx)) + return -EINVAL; + + mutex_lock(&ipa3_ctx->lock); + for (ip = IPA_IP_v4; ip < IPA_IP_MAX; ip++) { + struct ipa3_flt_tbl_nhash_lcl *lcl_tbl, *tmp; + struct ipa3_flt_tbl *flt_tbl = &ipa3_ctx->flt_tbl[ipa_ep_idx][ip]; + /* Position filtering table last in the list so, it will have first SRAM priority */ + list_for_each_entry_safe( + lcl_tbl, tmp, &ipa3_ctx->flt_tbl_nhash_lcl_list[ip], link) { + if (lcl_tbl->tbl == flt_tbl) { + list_del(&lcl_tbl->link); + list_add_tail(&lcl_tbl->link, + &ipa3_ctx->flt_tbl_nhash_lcl_list[ip]); + break; + } + } + } + mutex_unlock(&ipa3_ctx->lock); + + return 0; +} + diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_hdr.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_hdr.c new file mode 100644 index 0000000000..fcced5e197 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_hdr.c @@ -0,0 +1,1934 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ipa_i.h" +#include "ipahal.h" + +static const u32 ipa_hdr_bin_sz[IPA_HDR_BIN_MAX] = { 8, 16, 24, 36, 64, 128}; +static const u32 ipa_hdr_proc_ctx_bin_sz[IPA_HDR_PROC_CTX_BIN_MAX] = { 32, 64}; + +#define HDR_TYPE_IS_VALID(type) \ + ((type) >= 0 && (type) < IPA_HDR_L2_MAX) + +#define HDR_PROC_TYPE_IS_VALID(type) \ + ((type) >= 0 && (type) < IPA_HDR_PROC_MAX) + +/** + * ipa3_generate_hdr_hw_tbl() - generates the headers table + * @loc: [in] storage type of the header table buffer (local or system) + * @mem: [out] buffer to put the header table + * + * Returns: 0 on success, negative on failure + */ +static int ipa3_generate_hdr_hw_tbl(enum hdr_tbl_storage loc, struct ipa_mem_buffer *mem) +{ + struct ipa3_hdr_entry *entry; + gfp_t flag = GFP_KERNEL; + + mem->size = (ipa3_ctx->hdr_tbl[loc].end) ? ipa3_ctx->hdr_tbl[loc].end : ipa_hdr_bin_sz[0]; + + if (mem->size == 0) { + IPAERR("%s hdr tbl empty\n", loc == HDR_TBL_LCL ? "SRAM" : "DDR"); + return -EPERM; + } + IPADBG_LOW("tbl_sz=%d\n", mem->size); + +alloc: + mem->base = dma_alloc_coherent(ipa3_ctx->pdev, mem->size, + &mem->phys_base, flag); + if (!mem->base) { + if (flag == GFP_KERNEL) { + flag = GFP_ATOMIC; + goto alloc; + } + IPAERR("fail to alloc DMA buff of size %d\n", mem->size); + return -ENOMEM; + } + + list_for_each_entry(entry, &ipa3_ctx->hdr_tbl[loc].head_hdr_entry_list, link) { + IPADBG_LOW("hdr of len %d ofst=%d\n", entry->hdr_len, + entry->offset_entry->offset); + ipahal_cp_hdr_to_hw_buff(mem->base, entry->offset_entry->offset, + entry->hdr, entry->hdr_len); + } + + return 0; +} + +static int ipa3_hdr_proc_ctx_to_hw_format(struct ipa_mem_buffer *mem, + u64 hdr_sys_addr) +{ + struct ipa3_hdr_proc_ctx_entry *entry; + int ret; + int ep; + struct ipa_ep_cfg *cfg_ptr; + struct ipa_l2tp_header_remove_procparams *l2p_hdr_rm_ptr; + u32 hdr_lcl_addr; + + hdr_lcl_addr = ipa3_ctx->ipa_wrapper_base + + ipa3_ctx->ctrl->ipa_reg_base_ofst + + ipahal_get_reg_n_ofst(IPA_SW_AREA_RAM_DIRECT_ACCESS_n, + ipa3_ctx->smem_restricted_bytes / 4) + + IPA_MEM_PART(apps_hdr_ofst); + + list_for_each_entry(entry, + &ipa3_ctx->hdr_proc_ctx_tbl.head_proc_ctx_entry_list, + link) { + IPADBG_LOW("processing type %d ofst=%d\n", + entry->type, entry->offset_entry->offset); + + if (entry->l2tp_params.is_dst_pipe_valid) { + ep = ipa_get_ep_mapping(entry->l2tp_params.dst_pipe); + + if (ep >= 0) { + cfg_ptr = &ipa3_ctx->ep[ep].cfg; + l2p_hdr_rm_ptr = + &entry->l2tp_params.hdr_remove_param; + l2p_hdr_rm_ptr->hdr_ofst_pkt_size_valid = + cfg_ptr->hdr.hdr_ofst_pkt_size_valid; + l2p_hdr_rm_ptr->hdr_ofst_pkt_size = + cfg_ptr->hdr.hdr_ofst_pkt_size; + l2p_hdr_rm_ptr->hdr_endianness = + cfg_ptr->hdr_ext.hdr_little_endian ? + 0 : 1; + } + } + + /* Check the pointer and header length to avoid dangerous overflow in HW */ + if (unlikely(!entry->hdr || !entry->hdr->offset_entry || + !entry->offset_entry || + entry->hdr->hdr_len > ipa_hdr_bin_sz[IPA_HDR_BIN_MAX - 1])) { + IPAERR_RL("Found invalid hdr entry\n"); + return -EINVAL; + } + + ret = ipahal_cp_proc_ctx_to_hw_buff(entry->type, mem->base, + entry->offset_entry->offset, + entry->hdr->hdr_len, + (entry->hdr->is_lcl) ? hdr_lcl_addr : hdr_sys_addr, + entry->hdr->offset_entry, + &entry->l2tp_params, + &entry->eogre_params, + &entry->generic_params, + &entry->rtp_params, + ipa3_ctx->use_64_bit_dma_mask); + if (ret) + return ret; + } + + return 0; +} + +/** + * ipa3_generate_hdr_proc_ctx_hw_tbl() - + * generates the headers processing context table. + * @mem: [out] buffer to put the processing context table + * @aligned_mem: [out] actual processing context table (with alignment). + * Processing context table needs to be 8 Bytes aligned. + * + * Returns: 0 on success, negative on failure + */ +static int ipa3_generate_hdr_proc_ctx_hw_tbl(u64 hdr_sys_addr, + struct ipa_mem_buffer *mem, struct ipa_mem_buffer *aligned_mem) +{ + gfp_t flag = GFP_KERNEL; + int ret; + + mem->size = (ipa3_ctx->hdr_proc_ctx_tbl.end) ? : 4; + + /* make sure table is aligned */ + mem->size += IPA_HDR_PROC_CTX_TABLE_ALIGNMENT_BYTE; + + IPADBG_LOW("tbl_sz=%d\n", ipa3_ctx->hdr_proc_ctx_tbl.end); + +alloc: + mem->base = dma_alloc_coherent(ipa3_ctx->pdev, mem->size, + &mem->phys_base, flag); + if (!mem->base) { + if (flag == GFP_KERNEL) { + flag = GFP_ATOMIC; + goto alloc; + } + IPAERR("fail to alloc DMA buff of size %d\n", mem->size); + return -ENOMEM; + } + + aligned_mem->phys_base = + IPA_HDR_PROC_CTX_TABLE_ALIGNMENT(mem->phys_base); + aligned_mem->base = mem->base + + (aligned_mem->phys_base - mem->phys_base); + aligned_mem->size = mem->size - IPA_HDR_PROC_CTX_TABLE_ALIGNMENT_BYTE; + memset(aligned_mem->base, 0, aligned_mem->size); + ret = ipa3_hdr_proc_ctx_to_hw_format(aligned_mem, hdr_sys_addr); + if (ret) { + dma_free_coherent(ipa3_ctx->pdev, mem->size, mem->base, mem->phys_base); + return ret; + } + return ret; +} + +/** + * __ipa_commit_hdr_v3_0() - Commits the header table from memory to HW + * + * Returns: 0 on success, negative on failure + */ +int __ipa_commit_hdr_v3_0(void) +{ + struct ipa3_desc desc[4]; + struct ipa_mem_buffer hdr_mem[HDR_TBLS_TOTAL] = {0}; + struct ipa_mem_buffer ctx_mem; + struct ipa_mem_buffer aligned_ctx_mem; + struct ipahal_imm_cmd_dma_shared_mem dma_cmd_hdr = {0}; + struct ipahal_imm_cmd_dma_shared_mem dma_cmd_ctx = {0}; + struct ipahal_imm_cmd_register_write reg_write_cmd = {0}; + struct ipahal_imm_cmd_hdr_init_system hdr_init_cmd = {0}; + struct ipahal_imm_cmd_pyld *hdr_cmd_pyld[HDR_TBLS_TOTAL] = {0}; + struct ipahal_imm_cmd_pyld *ctx_cmd_pyld = NULL; + struct ipahal_imm_cmd_pyld *coal_cmd_pyld = NULL; + int rc = -EFAULT; + int i; + int num_cmd = 0; + u32 hdr_tbl_size, proc_ctx_size; + u32 proc_ctx_ofst; + u32 proc_ctx_size_ddr; + struct ipahal_imm_cmd_register_write reg_write_coal_close; + struct ipahal_reg_valmask valmask; + enum hdr_tbl_storage loc; + + memset(desc, 0, 3 * sizeof(struct ipa3_desc)); + + /* Generate structures for both SRAM and DDR header tables */ + for (loc = HDR_TBL_LCL; loc < HDR_TBLS_TOTAL; loc++) { + hdr_tbl_size = (loc == HDR_TBL_LCL) ? + IPA_MEM_PART(apps_hdr_size) : IPA_MEM_PART(apps_hdr_size_ddr); + + if (hdr_tbl_size) { + if (ipa3_generate_hdr_hw_tbl(loc, &hdr_mem[loc])) { + IPAERR("fail to generate %s HDR HW TBL\n", + loc == HDR_TBL_LCL ? "SRAM" : "DDR"); + goto end; + } + + if (hdr_mem[loc].size > hdr_tbl_size) { + IPAERR("%s HDR tbl too big needed %d avail %d\n", + loc == HDR_TBL_LCL ? "SRAM" : "DDR", + hdr_mem[loc].size, hdr_tbl_size); + goto free_dma; + } + } + } + + /* IC to close the coal frame before HPS Clear if coal is enabled */ + if (ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS) != -1 + && !ipa3_ctx->ulso_wa) { + u32 offset = 0; + + i = ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS); + reg_write_coal_close.skip_pipeline_clear = false; + reg_write_coal_close.pipeline_clear_options = IPAHAL_HPS_CLEAR; + if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0) + offset = ipahal_get_reg_ofst( + IPA_AGGR_FORCE_CLOSE); + else + offset = ipahal_get_ep_reg_offset( + IPA_AGGR_FORCE_CLOSE_n, i); + reg_write_coal_close.offset = offset; + ipahal_get_aggr_force_close_valmask(i, &valmask); + reg_write_coal_close.value = valmask.val; + reg_write_coal_close.value_mask = valmask.mask; + coal_cmd_pyld = ipahal_construct_imm_cmd( + IPA_IMM_CMD_REGISTER_WRITE, + ®_write_coal_close, false); + if (!coal_cmd_pyld) { + IPAERR("failed to construct coal close IC\n"); + goto end; + } + ipa3_init_imm_cmd_desc(&desc[num_cmd], coal_cmd_pyld); + ++num_cmd; + } + + /* Local (SRAM) header table configuration */ + if (IPA_MEM_PART(apps_hdr_size)) { + dma_cmd_hdr.is_read = false; /* write operation */ + dma_cmd_hdr.skip_pipeline_clear = false; + dma_cmd_hdr.pipeline_clear_options = IPAHAL_HPS_CLEAR; + dma_cmd_hdr.system_addr = hdr_mem[HDR_TBL_LCL].phys_base; + dma_cmd_hdr.size = hdr_mem[HDR_TBL_LCL].size; + dma_cmd_hdr.local_addr = + ipa3_ctx->smem_restricted_bytes + + IPA_MEM_PART(apps_hdr_ofst); + hdr_cmd_pyld[HDR_TBL_LCL] = ipahal_construct_imm_cmd(IPA_IMM_CMD_DMA_SHARED_MEM, + &dma_cmd_hdr, false); + if (!hdr_cmd_pyld[HDR_TBL_LCL]) { + IPAERR("fail construct dma_shared_mem cmd\n"); + goto end; + } + + ipa3_init_imm_cmd_desc(&desc[num_cmd], hdr_cmd_pyld[HDR_TBL_LCL]); + ++num_cmd; + IPA_DUMP_BUFF(hdr_mem[HDR_TBL_LCL].base, + hdr_mem[HDR_TBL_LCL].phys_base, + hdr_mem[HDR_TBL_LCL].size); + + } + + /* System (DDR) header table configuration */ + if (IPA_MEM_PART(apps_hdr_size_ddr)) { + hdr_init_cmd.hdr_table_addr = hdr_mem[HDR_TBL_SYS].phys_base; + hdr_cmd_pyld[HDR_TBL_SYS] = ipahal_construct_imm_cmd(IPA_IMM_CMD_HDR_INIT_SYSTEM, + &hdr_init_cmd, false); + if (!hdr_cmd_pyld[HDR_TBL_SYS]) { + IPAERR("fail construct hdr_init_system cmd\n"); + goto free_dma; + } + + ipa3_init_imm_cmd_desc(&desc[num_cmd], hdr_cmd_pyld[HDR_TBL_SYS]); + ++num_cmd; + IPA_DUMP_BUFF(hdr_mem[HDR_TBL_SYS].base, + hdr_mem[HDR_TBL_SYS].phys_base, + hdr_mem[HDR_TBL_SYS].size); + } + + /* The header memory passed to the HPC here is DDR (system), + but the actual header base will be determined later for each header */ + if (ipa3_generate_hdr_proc_ctx_hw_tbl(hdr_mem[HDR_TBL_SYS].phys_base, + &ctx_mem, + &aligned_ctx_mem)) { + IPAERR("fail to generate HDR PROC CTX HW TBL\n"); + goto end; + } + + proc_ctx_size = IPA_MEM_PART(apps_hdr_proc_ctx_size); + proc_ctx_ofst = IPA_MEM_PART(apps_hdr_proc_ctx_ofst); + if (ipa3_ctx->hdr_proc_ctx_tbl_lcl) { + if (aligned_ctx_mem.size > proc_ctx_size) { + IPAERR("tbl too big needed %d avail %d\n", + aligned_ctx_mem.size, + proc_ctx_size); + goto end; + } else { + dma_cmd_ctx.is_read = false; /* Write operation */ + dma_cmd_ctx.skip_pipeline_clear = false; + dma_cmd_ctx.pipeline_clear_options = IPAHAL_HPS_CLEAR; + dma_cmd_ctx.system_addr = aligned_ctx_mem.phys_base; + dma_cmd_ctx.size = aligned_ctx_mem.size; + dma_cmd_ctx.local_addr = + ipa3_ctx->smem_restricted_bytes + + proc_ctx_ofst; + ctx_cmd_pyld = ipahal_construct_imm_cmd( + IPA_IMM_CMD_DMA_SHARED_MEM, + &dma_cmd_ctx, false); + if (!ctx_cmd_pyld) { + IPAERR("fail construct dma_shared_mem cmd\n"); + goto end; + } + } + } else { + proc_ctx_size_ddr = IPA_MEM_PART(apps_hdr_proc_ctx_size_ddr); + if (aligned_ctx_mem.size > proc_ctx_size_ddr) { + IPAERR("tbl too big, needed %d avail %d\n", + aligned_ctx_mem.size, + proc_ctx_size_ddr); + goto end; + } else { + reg_write_cmd.skip_pipeline_clear = false; + reg_write_cmd.pipeline_clear_options = + IPAHAL_HPS_CLEAR; + reg_write_cmd.offset = + ipahal_get_reg_ofst( + IPA_SYS_PKT_PROC_CNTXT_BASE); + reg_write_cmd.value = aligned_ctx_mem.phys_base; + reg_write_cmd.value_mask = + ~(IPA_HDR_PROC_CTX_TABLE_ALIGNMENT_BYTE - 1); + ctx_cmd_pyld = ipahal_construct_imm_cmd( + IPA_IMM_CMD_REGISTER_WRITE, + ®_write_cmd, false); + if (!ctx_cmd_pyld) { + IPAERR("fail construct register_write cmd\n"); + goto end; + } + } + } + ipa3_init_imm_cmd_desc(&desc[num_cmd], ctx_cmd_pyld); + ++num_cmd; + IPA_DUMP_BUFF(ctx_mem.base, ctx_mem.phys_base, ctx_mem.size); + + if (ipa3_send_cmd(num_cmd, desc)) + IPAERR("fail to send immediate command\n"); + else + rc = 0; + + if (!rc && hdr_mem[HDR_TBL_SYS].base) { + if (ipa3_ctx->hdr_sys_mem.phys_base) { + dma_free_coherent(ipa3_ctx->pdev, + ipa3_ctx->hdr_sys_mem.size, + ipa3_ctx->hdr_sys_mem.base, + ipa3_ctx->hdr_sys_mem.phys_base); + } + ipa3_ctx->hdr_sys_mem = hdr_mem[HDR_TBL_SYS]; + } + + else { + dma_free_coherent(ipa3_ctx->pdev, hdr_mem[HDR_TBL_SYS].size, + hdr_mem[HDR_TBL_SYS].base,hdr_mem[HDR_TBL_SYS].phys_base); + } + + if (ipa3_ctx->hdr_proc_ctx_tbl_lcl) { + dma_free_coherent(ipa3_ctx->pdev, ctx_mem.size, ctx_mem.base, + ctx_mem.phys_base); + } else { + if (!rc) { + if (ipa3_ctx->hdr_proc_ctx_mem.phys_base) + dma_free_coherent(ipa3_ctx->pdev, + ipa3_ctx->hdr_proc_ctx_mem.size, + ipa3_ctx->hdr_proc_ctx_mem.base, + ipa3_ctx->hdr_proc_ctx_mem.phys_base); + ipa3_ctx->hdr_proc_ctx_mem = ctx_mem; + } + else { + dma_free_coherent(ipa3_ctx->pdev, ctx_mem.size, + ctx_mem.base,ctx_mem.phys_base); + } + } + goto end; + +free_dma: + if (hdr_mem[HDR_TBL_SYS].base) { + dma_free_coherent(ipa3_ctx->pdev, + hdr_mem[HDR_TBL_SYS].size, + hdr_mem[HDR_TBL_SYS].base, + hdr_mem[HDR_TBL_SYS].phys_base); + } + +end: + if (hdr_mem[HDR_TBL_LCL].base) { + dma_free_coherent(ipa3_ctx->pdev, + hdr_mem[HDR_TBL_LCL].size, + hdr_mem[HDR_TBL_LCL].base, + hdr_mem[HDR_TBL_LCL].phys_base); + } + + if (coal_cmd_pyld) + ipahal_destroy_imm_cmd(coal_cmd_pyld); + + if (ctx_cmd_pyld) + ipahal_destroy_imm_cmd(ctx_cmd_pyld); + + if (hdr_cmd_pyld[HDR_TBL_SYS]) + ipahal_destroy_imm_cmd(hdr_cmd_pyld[HDR_TBL_SYS]); + + if (hdr_cmd_pyld[HDR_TBL_LCL]) + ipahal_destroy_imm_cmd(hdr_cmd_pyld[HDR_TBL_LCL]); + + return rc; +} + +static int __ipa_add_hdr_proc_ctx(struct ipa_hdr_proc_ctx_add *proc_ctx, + bool add_ref_hdr, bool user_only) +{ + struct ipa3_hdr_entry *hdr_entry; + struct ipa3_hdr_proc_ctx_entry *entry; + struct ipa3_hdr_proc_ctx_offset_entry *offset; + u32 bin; + struct ipa3_hdr_proc_ctx_tbl *htbl = &ipa3_ctx->hdr_proc_ctx_tbl; + int id; + int needed_len; + int mem_size; + + IPADBG_LOW("Add processing type %d hdr_hdl %d\n", + proc_ctx->type, proc_ctx->hdr_hdl); + + if (!HDR_PROC_TYPE_IS_VALID(proc_ctx->type)) { + IPAERR_RL("invalid processing type %d\n", proc_ctx->type); + return -EINVAL; + } + + hdr_entry = ipa3_id_find(proc_ctx->hdr_hdl); + if (!hdr_entry) { + IPAERR_RL("hdr_hdl is invalid\n"); + return -EINVAL; + } + if (hdr_entry->cookie != IPA_HDR_COOKIE) { + IPAERR_RL("Invalid header cookie %u\n", hdr_entry->cookie); + WARN_ON_RATELIMIT_IPA(1); + return -EINVAL; + } + IPADBG("Associated header is name=%s\n", hdr_entry->name); + + entry = kmem_cache_zalloc(ipa3_ctx->hdr_proc_ctx_cache, GFP_KERNEL); + if (!entry) { + IPAERR("failed to alloc proc_ctx object\n"); + return -ENOMEM; + } + + INIT_LIST_HEAD(&entry->link); + + entry->type = proc_ctx->type; + entry->hdr = hdr_entry; + entry->l2tp_params = proc_ctx->l2tp_params; + entry->eogre_params = proc_ctx->eogre_params; + entry->generic_params = proc_ctx->generic_params; + if (add_ref_hdr) + hdr_entry->ref_cnt++; + entry->cookie = IPA_PROC_HDR_COOKIE; + entry->ipacm_installed = user_only; + + needed_len = ipahal_get_proc_ctx_needed_len(proc_ctx->type); + if ((needed_len < 0) || + ((needed_len > ipa_hdr_proc_ctx_bin_sz[IPA_HDR_PROC_CTX_BIN0]) + && + (needed_len > + ipa_hdr_proc_ctx_bin_sz[IPA_HDR_PROC_CTX_BIN1]))) { + IPAERR_RL("unexpected needed len %d\n", needed_len); + WARN_ON_RATELIMIT_IPA(1); + goto bad_len; + } + + if (needed_len <= ipa_hdr_proc_ctx_bin_sz[IPA_HDR_PROC_CTX_BIN0]) + bin = IPA_HDR_PROC_CTX_BIN0; + else + bin = IPA_HDR_PROC_CTX_BIN1; + + mem_size = (ipa3_ctx->hdr_proc_ctx_tbl_lcl) ? + IPA_MEM_PART(apps_hdr_proc_ctx_size) : + IPA_MEM_PART(apps_hdr_proc_ctx_size_ddr); + if (list_empty(&htbl->head_free_offset_list[bin])) { + if (htbl->end + ipa_hdr_proc_ctx_bin_sz[bin] > mem_size) { + IPAERR_RL("hdr proc ctx table overflow\n"); + goto bad_len; + } + + offset = kmem_cache_zalloc(ipa3_ctx->hdr_proc_ctx_offset_cache, + GFP_KERNEL); + if (!offset) { + IPAERR("failed to alloc offset object\n"); + goto bad_len; + } + INIT_LIST_HEAD(&offset->link); + /* + * for a first item grow, set the bin and offset which are set + * in stone + */ + offset->offset = htbl->end; + offset->bin = bin; + offset->ipacm_installed = user_only; + htbl->end += ipa_hdr_proc_ctx_bin_sz[bin]; + list_add(&offset->link, + &htbl->head_offset_list[bin]); + } else { + /* get the first free slot */ + offset = + list_first_entry(&htbl->head_free_offset_list[bin], + struct ipa3_hdr_proc_ctx_offset_entry, link); + offset->ipacm_installed = user_only; + list_move(&offset->link, &htbl->head_offset_list[bin]); + } + + entry->offset_entry = offset; + list_add(&entry->link, &htbl->head_proc_ctx_entry_list); + htbl->proc_ctx_cnt++; + IPADBG("add proc ctx of sz=%d cnt=%d ofst=%d\n", needed_len, + htbl->proc_ctx_cnt, offset->offset); + + id = ipa3_id_alloc(entry); + if (id < 0) { + IPAERR_RL("failed to alloc id\n"); + WARN_ON_RATELIMIT_IPA(1); + goto ipa_insert_failed; + } + entry->id = id; + proc_ctx->proc_ctx_hdl = id; + entry->ref_cnt++; + + return 0; + +ipa_insert_failed: + list_move(&offset->link, + &htbl->head_free_offset_list[offset->bin]); + entry->offset_entry = NULL; + list_del(&entry->link); + htbl->proc_ctx_cnt--; + +bad_len: + if (add_ref_hdr) + hdr_entry->ref_cnt--; + entry->cookie = 0; + kmem_cache_free(ipa3_ctx->hdr_proc_ctx_cache, entry); + return -EPERM; +} + +static int __ipa_add_rtp_hdr_proc_ctx(struct ipa_hdr_proc_ctx_add *proc_ctx, + struct ipa_rtp_hdr_proc_ctx_params rtp_params, bool add_ref_hdr, bool user_only) +{ + struct ipa3_hdr_entry *hdr_entry; + struct ipa3_hdr_proc_ctx_entry *entry; + struct ipa3_hdr_proc_ctx_offset_entry *offset; + u32 bin; + struct ipa3_hdr_proc_ctx_tbl *htbl = &ipa3_ctx->hdr_proc_ctx_tbl; + int id; + int needed_len; + int mem_size; + + IPADBG_LOW("Add processing type %d hdr_hdl %d\n", + proc_ctx->type, proc_ctx->hdr_hdl); + + if (!HDR_PROC_TYPE_IS_VALID(proc_ctx->type)) { + IPAERR_RL("invalid processing type %d\n", proc_ctx->type); + return -EINVAL; + } + + hdr_entry = ipa3_id_find(proc_ctx->hdr_hdl); + if (!hdr_entry) { + IPAERR_RL("hdr_hdl is invalid\n"); + return -EINVAL; + } + if (hdr_entry->cookie != IPA_HDR_COOKIE) { + IPAERR_RL("Invalid header cookie %u\n", hdr_entry->cookie); + WARN_ON_RATELIMIT_IPA(1); + return -EINVAL; + } + IPADBG("Associated header is name=%s\n", hdr_entry->name); + + entry = kmem_cache_zalloc(ipa3_ctx->hdr_proc_ctx_cache, GFP_KERNEL); + if (!entry) { + IPAERR("failed to alloc proc_ctx object\n"); + return -ENOMEM; + } + + INIT_LIST_HEAD(&entry->link); + + entry->type = proc_ctx->type; + entry->hdr = hdr_entry; + entry->rtp_params = rtp_params; + if (add_ref_hdr) + hdr_entry->ref_cnt++; + entry->cookie = IPA_PROC_HDR_COOKIE; + entry->ipacm_installed = user_only; + + needed_len = ipahal_get_proc_ctx_needed_len(proc_ctx->type); + if ((needed_len < 0) || + ((needed_len > ipa_hdr_proc_ctx_bin_sz[IPA_HDR_PROC_CTX_BIN0]) + && + (needed_len > + ipa_hdr_proc_ctx_bin_sz[IPA_HDR_PROC_CTX_BIN1]))) { + IPAERR_RL("unexpected needed len %d\n", needed_len); + WARN_ON_RATELIMIT_IPA(1); + goto bad_len; + } + + if (needed_len <= ipa_hdr_proc_ctx_bin_sz[IPA_HDR_PROC_CTX_BIN0]) + bin = IPA_HDR_PROC_CTX_BIN0; + else + bin = IPA_HDR_PROC_CTX_BIN1; + + mem_size = (ipa3_ctx->hdr_proc_ctx_tbl_lcl) ? + IPA_MEM_PART(apps_hdr_proc_ctx_size) : + IPA_MEM_PART(apps_hdr_proc_ctx_size_ddr); + if (list_empty(&htbl->head_free_offset_list[bin])) { + if (htbl->end + ipa_hdr_proc_ctx_bin_sz[bin] > mem_size) { + IPAERR_RL("hdr proc ctx table overflow\n"); + goto bad_len; + } + + offset = kmem_cache_zalloc(ipa3_ctx->hdr_proc_ctx_offset_cache, + GFP_KERNEL); + if (!offset) { + IPAERR("failed to alloc offset object\n"); + goto bad_len; + } + INIT_LIST_HEAD(&offset->link); + /* + * for a first item grow, set the bin and offset which are set + * in stone + */ + offset->offset = htbl->end; + offset->bin = bin; + offset->ipacm_installed = user_only; + htbl->end += ipa_hdr_proc_ctx_bin_sz[bin]; + list_add(&offset->link, + &htbl->head_offset_list[bin]); + } else { + /* get the first free slot */ + offset = + list_first_entry(&htbl->head_free_offset_list[bin], + struct ipa3_hdr_proc_ctx_offset_entry, link); + offset->ipacm_installed = user_only; + list_move(&offset->link, &htbl->head_offset_list[bin]); + } + + entry->offset_entry = offset; + list_add(&entry->link, &htbl->head_proc_ctx_entry_list); + htbl->proc_ctx_cnt++; + IPADBG("add proc ctx of sz=%d cnt=%d ofst=%d\n", needed_len, + htbl->proc_ctx_cnt, offset->offset); + + id = ipa3_id_alloc(entry); + if (id < 0) { + IPAERR_RL("failed to alloc id\n"); + WARN_ON_RATELIMIT_IPA(1); + goto ipa_insert_failed; + } + entry->id = id; + proc_ctx->proc_ctx_hdl = id; + entry->ref_cnt++; + + return 0; + +ipa_insert_failed: + list_move(&offset->link, + &htbl->head_free_offset_list[offset->bin]); + entry->offset_entry = NULL; + list_del(&entry->link); + htbl->proc_ctx_cnt--; + +bad_len: + if (add_ref_hdr) + hdr_entry->ref_cnt--; + entry->cookie = 0; + kmem_cache_free(ipa3_ctx->hdr_proc_ctx_cache, entry); + return -EPERM; +} + +static int __ipa_add_hdr(struct ipa_hdr_add *hdr, bool user, + struct ipa3_hdr_entry **entry_out) +{ + struct ipa3_hdr_entry *entry, *entry_t, *next; + struct ipa_hdr_offset_entry *offset = NULL; + u32 bin; + struct ipa3_hdr_tbl *htbl; + int id; + int mem_size; + enum hdr_tbl_storage hdr_tbl_loc; + + if (hdr->hdr_len > IPA_HDR_MAX_SIZE) { + IPAERR_RL("bad param\n"); + goto error; + } + + if (!HDR_TYPE_IS_VALID(hdr->type)) { + IPAERR_RL("invalid hdr type %d\n", hdr->type); + goto error; + } + + entry = kmem_cache_zalloc(ipa3_ctx->hdr_cache, GFP_KERNEL); + if (!entry) + goto error; + + INIT_LIST_HEAD(&entry->link); + + memcpy(entry->hdr, hdr->hdr, hdr->hdr_len); + entry->hdr_len = hdr->hdr_len; + strscpy(entry->name, hdr->name, IPA_RESOURCE_NAME_MAX); + entry->is_partial = hdr->is_partial; + entry->type = hdr->type; + entry->is_eth2_ofst_valid = hdr->is_eth2_ofst_valid; + entry->eth2_ofst = hdr->eth2_ofst; + entry->cookie = IPA_HDR_COOKIE; + entry->ipacm_installed = user; + entry->is_lcl = ((IPA_MEM_PART(apps_hdr_size_ddr) && + (entry->is_partial || (hdr->status == IPA_HDR_TO_DDR_PATTERN))) || + !IPA_MEM_PART(apps_hdr_size)) ? false : true; + + /* check to see if adding header entry with duplicate name */ + for (hdr_tbl_loc = HDR_TBL_LCL; hdr_tbl_loc < HDR_TBLS_TOTAL; hdr_tbl_loc++) { + list_for_each_entry_safe(entry_t, next, + &ipa3_ctx->hdr_tbl[hdr_tbl_loc].head_hdr_entry_list, link) { + + /* return if adding the same name */ + if (!strcmp(entry_t->name, entry->name) && (user == true)) { + IPAERR_RL("IPACM Trying to add hdr %s len=%d, duplicate entry, return old one\n", + entry->name, entry->hdr_len); + + /* return the original entry */ + if (entry_out) + *entry_out = entry_t; + + kmem_cache_free(ipa3_ctx->hdr_cache, entry); + return 0; + } + } + } + + if (hdr->hdr_len <= ipa_hdr_bin_sz[IPA_HDR_BIN0]) + bin = IPA_HDR_BIN0; + else if (hdr->hdr_len <= ipa_hdr_bin_sz[IPA_HDR_BIN1]) + bin = IPA_HDR_BIN1; + else if (hdr->hdr_len <= ipa_hdr_bin_sz[IPA_HDR_BIN2]) + bin = IPA_HDR_BIN2; + else if (hdr->hdr_len <= ipa_hdr_bin_sz[IPA_HDR_BIN3]) + bin = IPA_HDR_BIN3; + else if (hdr->hdr_len <= ipa_hdr_bin_sz[IPA_HDR_BIN4]) + bin = IPA_HDR_BIN4; + /* Starting from IPA4.5, HW supports larger headers. */ + else if ((hdr->hdr_len <= ipa_hdr_bin_sz[IPA_HDR_BIN5]) && + (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_5)) + bin = IPA_HDR_BIN5; + else { + IPAERR_RL("unexpected hdr len %d\n", hdr->hdr_len); + goto bad_hdr_len; + } + + htbl = entry->is_lcl ? &ipa3_ctx->hdr_tbl[HDR_TBL_LCL] : &ipa3_ctx->hdr_tbl[HDR_TBL_SYS]; + mem_size = entry->is_lcl ? IPA_MEM_PART(apps_hdr_size) : IPA_MEM_PART(apps_hdr_size_ddr); + + if (list_empty(&htbl->head_free_offset_list[bin])) { + /* + * In case of a local header entry, + * first iteration will check against SRAM partition space, + * and the second iteration will check against DDR partition space. + * In case of a system header entry, the loop will iterate only once, + * and check against DDR partition space. + */ + while (htbl->end + ipa_hdr_bin_sz[bin] > mem_size) { + if (entry->is_lcl) { + /* if header does not fit to SRAM table, place it in DDR */ + IPADBG_LOW("SRAM header table was full allocting DDR header table! Requested: %d Left: %d name %s, end %d\n", + ipa_hdr_bin_sz[bin], mem_size - htbl->end, entry->name, htbl->end); + htbl = &ipa3_ctx->hdr_tbl[HDR_TBL_SYS]; + mem_size = IPA_MEM_PART(apps_hdr_size_ddr); + entry->is_lcl = false; + } + + /* check if DDR free list */ + if (list_empty(&htbl->head_free_offset_list[bin])) { + if (!entry->is_lcl && (htbl->end + ipa_hdr_bin_sz[bin] > mem_size)) { + IPAERR("No space in DDR header buffer! Requested: %d Left: %d name %s, end %d\n", + ipa_hdr_bin_sz[bin], mem_size - htbl->end, entry->name, htbl->end); + goto bad_hdr_len; + } + + IPADBG_LOW("No free offset in DDR allocating new offset Requested: %d Left: %d name %s, end %d\n", + ipa_hdr_bin_sz[bin], mem_size - htbl->end, entry->name, htbl->end); + goto create_entry; + } else { + /* get the first free slot */ + offset = list_first_entry(&htbl->head_free_offset_list[bin], + struct ipa_hdr_offset_entry, link); + list_move(&offset->link, &htbl->head_offset_list[bin]); + entry->offset_entry = offset; + offset->ipacm_installed = user; + goto free_list; + } + } +create_entry: + offset = kmem_cache_zalloc(ipa3_ctx->hdr_offset_cache, + GFP_KERNEL); + if (!offset) { + IPAERR("failed to alloc hdr offset object\n"); + goto bad_hdr_len; + } + INIT_LIST_HEAD(&offset->link); + /* + * for a first item grow, set the bin and offset which + * are set in stone + */ + offset->offset = htbl->end; + offset->bin = bin; + htbl->end += ipa_hdr_bin_sz[bin]; + list_add(&offset->link, + &htbl->head_offset_list[bin]); + entry->offset_entry = offset; + offset->ipacm_installed = user; + } else { + /* get the first free slot */ + offset = list_first_entry(&htbl->head_free_offset_list[bin], + struct ipa_hdr_offset_entry, link); + list_move(&offset->link, &htbl->head_offset_list[bin]); + entry->offset_entry = offset; + offset->ipacm_installed = user; + } + +free_list: + + list_add(&entry->link, &htbl->head_hdr_entry_list); + htbl->hdr_cnt++; + IPADBG("add hdr of sz=%d hdr_cnt=%d ofst=%d to %s table\n", + hdr->hdr_len, + htbl->hdr_cnt, + entry->offset_entry->offset, + entry->is_lcl ? "SRAM" : "DDR"); + + id = ipa3_id_alloc(entry); + if (id < 0) { + IPAERR_RL("failed to alloc id\n"); + WARN_ON_RATELIMIT_IPA(1); + goto ipa_insert_failed; + } + entry->id = id; + hdr->hdr_hdl = id; + entry->ref_cnt++; + if (entry_out) + *entry_out = entry; + + return 0; + +ipa_insert_failed: + if (offset) + list_move(&offset->link, + &htbl->head_free_offset_list[offset->bin]); + entry->offset_entry = NULL; + htbl->hdr_cnt--; + list_del(&entry->link); + +bad_hdr_len: + entry->cookie = 0; + kmem_cache_free(ipa3_ctx->hdr_cache, entry); +error: + return -EPERM; +} + +static int __ipa3_del_hdr_proc_ctx(u32 proc_ctx_hdl, + bool release_hdr, bool by_user) +{ + struct ipa3_hdr_proc_ctx_entry *entry; + struct ipa3_hdr_proc_ctx_tbl *htbl = &ipa3_ctx->hdr_proc_ctx_tbl; + + entry = ipa3_id_find(proc_ctx_hdl); + if (!entry || (entry->cookie != IPA_PROC_HDR_COOKIE)) { + IPAERR_RL("bad param\n"); + return -EINVAL; + } + + IPADBG("del proc ctx cnt=%d ofst=%d\n", + htbl->proc_ctx_cnt, entry->offset_entry->offset); + + if (by_user && entry->user_deleted) { + IPAERR_RL("proc_ctx already deleted by user\n"); + return -EINVAL; + } + + if (by_user) + entry->user_deleted = true; + + if (--entry->ref_cnt) { + IPADBG("proc_ctx_hdl %x ref_cnt %d\n", + proc_ctx_hdl, entry->ref_cnt); + return 0; + } + + if (release_hdr) + __ipa3_del_hdr(entry->hdr->id, false); + + /* move the offset entry to appropriate free list */ + list_move(&entry->offset_entry->link, + &htbl->head_free_offset_list[entry->offset_entry->bin]); + list_del(&entry->link); + htbl->proc_ctx_cnt--; + entry->cookie = 0; + kmem_cache_free(ipa3_ctx->hdr_proc_ctx_cache, entry); + + /* remove the handle from the database */ + ipa3_id_remove(proc_ctx_hdl); + + return 0; +} + +static int __ipa_add_hpc_hdr_insertion(struct ipa_hdr_add *hdr, bool user) +{ + struct ipa3_hdr_entry *entry = NULL; + struct ipa_hdr_proc_ctx_add proc_ctx; + + hdr->status = IPA_HDR_TO_DDR_PATTERN; + + if (__ipa_add_hdr(hdr, user, &entry)) + goto error; + + IPADBG("adding processing context for header %s\n", hdr->name); + proc_ctx.type = IPA_HDR_PROC_NONE; + proc_ctx.hdr_hdl = hdr->hdr_hdl; + if (__ipa_add_hdr_proc_ctx(&proc_ctx, true, user)) { + IPAERR("failed to add hdr proc ctx\n"); + goto fail_add_proc_ctx; + } + entry->proc_ctx = (struct ipa3_hdr_proc_ctx_entry *)ipa3_id_find(proc_ctx.proc_ctx_hdl); + WARN_ON_RATELIMIT_IPA(!entry->proc_ctx); + entry->proc_ctx->ref_cnt++; + + return 0; + +fail_add_proc_ctx: + __ipa3_del_hdr(hdr->hdr_hdl, user); +error: + return -EPERM; +} + +int __ipa3_del_hdr(u32 hdr_hdl, bool by_user) +{ + struct ipa3_hdr_entry *entry; + struct ipa3_hdr_tbl *htbl; + + entry = ipa3_id_find(hdr_hdl); + if (entry == NULL) { + IPAERR_RL("lookup failed\n"); + return -EINVAL; + } + + if (entry->cookie != IPA_HDR_COOKIE) { + IPAERR_RL("bad parm\n"); + return -EINVAL; + } + + htbl = entry->is_lcl ? &ipa3_ctx->hdr_tbl[HDR_TBL_LCL] : &ipa3_ctx->hdr_tbl[HDR_TBL_SYS]; + + IPADBG("del hdr of len=%d hdr_cnt=%d ofst=%d\n", entry->hdr_len, htbl->hdr_cnt, + entry->offset_entry->offset); + + if (by_user && entry->user_deleted) { + IPAERR_RL("proc_ctx already deleted by user\n"); + return -EINVAL; + } + + if (by_user) { + if (!strcmp(entry->name, IPA_LAN_RX_HDR_NAME)) { + IPADBG("Trying to delete hdr %s offset=%u\n", + entry->name, entry->offset_entry->offset); + if (!entry->offset_entry->offset) { + IPAERR_RL( + "User cannot delete default header\n"); + return -EPERM; + } + } + entry->user_deleted = true; + } + + if (--entry->ref_cnt) { + IPADBG("hdr_hdl %x ref_cnt %d\n", hdr_hdl, entry->ref_cnt); + return 0; + } + + if (entry->proc_ctx) + __ipa3_del_hdr_proc_ctx(entry->proc_ctx->id, false, false); + else + /* move the offset entry to appropriate free list */ + list_move(&entry->offset_entry->link, + &htbl->head_free_offset_list[entry->offset_entry->bin]); + list_del(&entry->link); + htbl->hdr_cnt--; + entry->cookie = 0; + kmem_cache_free(ipa3_ctx->hdr_cache, entry); + + /* remove the handle from the database */ + ipa3_id_remove(hdr_hdl); + + return 0; +} + +/** + * ipa3_add_hdr_hpc() - add the specified headers to SW and optionally commit them + * to IPA HW + * @hdrs: [inout] set of headers to add + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_add_hdr_hpc(struct ipa_ioc_add_hdr *hdrs) +{ + return ipa3_add_hdr_hpc_usr(hdrs, false); +} +EXPORT_SYMBOL(ipa3_add_hdr_hpc); + +/** + * ipa3_add_hdr_hpc_usr() - add the specified headers to SW + * and optionally commit them to IPA HW + * @hdrs: [inout] set of headers to add + * @user_only: [in] indicate installed from user + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_add_hdr_hpc_usr(struct ipa_ioc_add_hdr *hdrs, bool user_only) +{ + int i; + int result = -EFAULT; + + if (hdrs == NULL || hdrs->num_hdrs == 0) { + IPAERR_RL("bad parm\n"); + return -EINVAL; + } + + mutex_lock(&ipa3_ctx->lock); + IPADBG("adding %d headers to IPA driver internal data struct\n", + hdrs->num_hdrs); + for (i = 0; i < hdrs->num_hdrs; i++) { + if (__ipa_add_hpc_hdr_insertion(&hdrs->hdr[i], user_only)) { + IPAERR_RL("failed to add hdr hpc %d\n", i); + hdrs->hdr[i].status = -1; + } + else { + hdrs->hdr[i].status = 0; + } + } + + if (hdrs->commit) { + IPADBG("committing all headers to IPA core"); + if (ipa3_ctx->ctrl->ipa3_commit_hdr()) { + result = -EPERM; + goto bail; + } + } + result = 0; +bail: + mutex_unlock(&ipa3_ctx->lock); + return result; +} + +/** + * ipa3_del_hdr_hpc_usr() - Remove the specified headers from SW + * and optionally commit them to IPA HW + * @hdls: [inout] set of headers to delete + * @by_user: Operation requested by user? + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_del_hdr_hpc_usr(struct ipa_ioc_del_hdr *hdls, bool by_user) +{ + int i; + int result = 0; + struct ipa3_hdr_entry *entry; + struct ipa3_hdr_proc_ctx_entry *proc_ctx_entry; + + if (hdls == NULL || hdls->num_hdls == 0) { + IPAERR_RL("bad parm\n"); + return -EINVAL; + } + + mutex_lock(&ipa3_ctx->lock); + for (i = 0; i < hdls->num_hdls; i++) { + entry = (struct ipa3_hdr_entry *)ipa3_id_find(hdls->hdl[i].hdl); + if (entry) { + proc_ctx_entry = entry->proc_ctx; + /* Header API changed under the hood --> need to NULL proc_ctx in header entry to + comply and avoid outdated code reach. need to be handled better in the future + */ + entry->proc_ctx = NULL; + entry->ref_cnt--; + result = __ipa3_del_hdr(hdls->hdl[i].hdl, by_user) != 0; + if (proc_ctx_entry) { + proc_ctx_entry->ref_cnt--; + result = __ipa3_del_hdr_proc_ctx(proc_ctx_entry->id, false, false) != 0; + } + } + hdls->hdl[i].status = result; + } + + if (hdls->commit) { + if (ipa3_ctx->ctrl->ipa3_commit_hdr()) { + result = -EPERM; + goto bail; + } + } + result = 0; +bail: + mutex_unlock(&ipa3_ctx->lock); + return result; +} + +/** + * ipa3_del_hdr_hpc() - add the specified headers to SW and + * optionally commit them to IPA HW + * @hdrs: [inout] set of headers to add + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_del_hdr_hpc(struct ipa_ioc_del_hdr *hdrs) +{ + return ipa3_del_hdr_hpc_usr(hdrs, false); +} +EXPORT_SYMBOL(ipa3_del_hdr_hpc); + +/** + * ipa_add_hdr() - add the specified headers to SW and optionally commit them + * to IPA HW + * @hdrs: [inout] set of headers to add + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa_add_hdr(struct ipa_ioc_add_hdr *hdrs) +{ + return ipa3_add_hdr_usr(hdrs, false); +} +EXPORT_SYMBOL(ipa_add_hdr); + +/** + * ipa3_add_hdr_usr() - add the specified headers to SW + * and optionally commit them to IPA HW + * @hdrs: [inout] set of headers to add + * @user_only: [in] indicate installed from user + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_add_hdr_usr(struct ipa_ioc_add_hdr *hdrs, bool user_only) +{ + int i; + int result = -EFAULT; + + if (hdrs == NULL || hdrs->num_hdrs == 0) { + IPAERR_RL("bad parm\n"); + return -EINVAL; + } + + mutex_lock(&ipa3_ctx->lock); + IPADBG("adding %d headers to IPA driver internal data struct\n", + hdrs->num_hdrs); + for (i = 0; i < hdrs->num_hdrs; i++) { + if (__ipa_add_hdr(&hdrs->hdr[i], user_only, NULL)) { + IPAERR_RL("failed to add hdr %d\n", i); + hdrs->hdr[i].status = -1; + } else { + hdrs->hdr[i].status = 0; + } + } + + if (hdrs->commit) { + IPADBG("committing all headers to IPA core"); + if (ipa3_ctx->ctrl->ipa3_commit_hdr()) { + result = -EPERM; + goto bail; + } + } + result = 0; +bail: + mutex_unlock(&ipa3_ctx->lock); + return result; +} + +/** + * ipa3_del_hdr_by_user() - Remove the specified headers + * from SW and optionally commit them to IPA HW + * @hdls: [inout] set of headers to delete + * @by_user: Operation requested by user? + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_del_hdr_by_user(struct ipa_ioc_del_hdr *hdls, bool by_user) +{ + int i; + int result = -EFAULT; + + if (hdls == NULL || hdls->num_hdls == 0) { + IPAERR_RL("bad parm\n"); + return -EINVAL; + } + + mutex_lock(&ipa3_ctx->lock); + for (i = 0; i < hdls->num_hdls; i++) { + if (__ipa3_del_hdr(hdls->hdl[i].hdl, by_user)) { + IPAERR_RL("failed to del hdr %i\n", i); + hdls->hdl[i].status = -1; + } else { + hdls->hdl[i].status = 0; + } + } + + if (hdls->commit) { + if (ipa3_ctx->ctrl->ipa3_commit_hdr()) { + result = -EPERM; + goto bail; + } + } + result = 0; +bail: + mutex_unlock(&ipa3_ctx->lock); + return result; +} + +/** + * ipa_del_hdr() - Remove the specified headers from SW + * and optionally commit them to IPA HW + * @hdls: [inout] set of headers to delete + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa_del_hdr(struct ipa_ioc_del_hdr *hdls) +{ + return ipa3_del_hdr_by_user(hdls, false); +} +EXPORT_SYMBOL(ipa_del_hdr); + +/** + * ipa3_add_hdr_proc_ctx() - add the specified headers to SW + * and optionally commit them to IPA HW + * @proc_ctxs: [inout] set of processing context headers to add + * @user_only: [in] indicate installed by user-space module + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_add_hdr_proc_ctx(struct ipa_ioc_add_hdr_proc_ctx *proc_ctxs, + bool user_only) +{ + int i; + int result = -EFAULT; + + if (proc_ctxs == NULL || proc_ctxs->num_proc_ctxs == 0) { + IPAERR_RL("bad parm\n"); + return -EINVAL; + } + + mutex_lock(&ipa3_ctx->lock); + IPADBG("adding %d header processing contextes to IPA driver\n", + proc_ctxs->num_proc_ctxs); + for (i = 0; i < proc_ctxs->num_proc_ctxs; i++) { + if (__ipa_add_hdr_proc_ctx(&proc_ctxs->proc_ctx[i], + true, user_only)) { + IPAERR_RL("failed to add hdr proc ctx %d\n", i); + proc_ctxs->proc_ctx[i].status = -1; + } else { + proc_ctxs->proc_ctx[i].status = 0; + } + } + + if (proc_ctxs->commit) { + IPADBG("committing all headers to IPA core"); + if (ipa3_ctx->ctrl->ipa3_commit_hdr()) { + result = -EPERM; + goto bail; + } + } + result = 0; +bail: + mutex_unlock(&ipa3_ctx->lock); + return result; +} + +/** + * ipa3_add_rtp_hdr_proc_ctx() - add the specified headers to SW + * and optionally commit them to IPA HW + * @proc_ctxs: [inout] set of processing context headers to add + * @rtp_params: [in] set of rtp_params to be configured + * @user_only: [in] indicate installed by user-space module + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_add_rtp_hdr_proc_ctx(struct ipa_ioc_add_hdr_proc_ctx *proc_ctxs, + struct ipa_rtp_hdr_proc_ctx_params rtp_params, bool user_only) +{ + int i; + int result = -EFAULT; + + if (proc_ctxs == NULL || proc_ctxs->num_proc_ctxs == 0) { + IPAERR_RL("bad parm\n"); + return -EINVAL; + } + + mutex_lock(&ipa3_ctx->lock); + IPADBG("adding %d rtp header processing contexts to IPA driver\n", + proc_ctxs->num_proc_ctxs); + for (i = 0; i < proc_ctxs->num_proc_ctxs; i++) { + if (__ipa_add_rtp_hdr_proc_ctx(&proc_ctxs->proc_ctx[i], + rtp_params, true, user_only)) { + IPAERR_RL("failed to add hdr proc ctx %d\n", i); + proc_ctxs->proc_ctx[i].status = -1; + } else { + proc_ctxs->proc_ctx[i].status = 0; + } + } + + if (proc_ctxs->commit) { + IPADBG("committing all headers to IPA core"); + if (ipa3_ctx->ctrl->ipa3_commit_hdr()) { + result = -EPERM; + goto bail; + } + } + result = 0; +bail: + mutex_unlock(&ipa3_ctx->lock); + return result; +} + +/** + * ipa3_del_hdr_proc_ctx_by_user() - + * Remove the specified processing context headers from SW and + * optionally commit them to IPA HW. + * @hdls: [inout] set of processing context headers to delete + * @by_user: Operation requested by user? + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_del_hdr_proc_ctx_by_user(struct ipa_ioc_del_hdr_proc_ctx *hdls, + bool by_user) +{ + int i; + int result; + + if (hdls == NULL || hdls->num_hdls == 0) { + IPAERR_RL("bad parm\n"); + return -EINVAL; + } + + mutex_lock(&ipa3_ctx->lock); + for (i = 0; i < hdls->num_hdls; i++) { + if (__ipa3_del_hdr_proc_ctx(hdls->hdl[i].hdl, true, by_user)) { + IPAERR_RL("failed to del hdr %i\n", i); + hdls->hdl[i].status = -1; + } else { + hdls->hdl[i].status = 0; + } + } + + if (hdls->commit) { + if (ipa3_ctx->ctrl->ipa3_commit_hdr()) { + result = -EPERM; + goto bail; + } + } + result = 0; +bail: + mutex_unlock(&ipa3_ctx->lock); + return result; +} + +/** + * ipa3_del_hdr_proc_ctx() - + * Remove the specified processing context headers from SW and + * optionally commit them to IPA HW. + * @hdls: [inout] set of processing context headers to delete + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_del_hdr_proc_ctx(struct ipa_ioc_del_hdr_proc_ctx *hdls) +{ + return ipa3_del_hdr_proc_ctx_by_user(hdls, false); +} +EXPORT_SYMBOL(ipa3_del_hdr_proc_ctx); + +/** + * ipa3_commit_hdr() - commit to IPA HW the current header table in SW + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_commit_hdr(void) +{ + int result = -EFAULT; + + /* + * issue a commit on the routing module since routing rules point to + * header table entries + */ + if (ipa3_commit_rt(IPA_IP_v4)) + return -EPERM; + if (ipa3_commit_rt(IPA_IP_v6)) + return -EPERM; + + mutex_lock(&ipa3_ctx->lock); + if (ipa3_ctx->ctrl->ipa3_commit_hdr()) { + result = -EPERM; + goto bail; + } + result = 0; +bail: + mutex_unlock(&ipa3_ctx->lock); + return result; +} +EXPORT_SYMBOL(ipa3_commit_hdr); + +/** + * ipa3_reset_hdr() - reset the current header table in SW (does not commit to + * HW) + * + * @user_only: [in] indicate delete rules installed by userspace + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_reset_hdr(bool user_only) +{ + struct ipa3_hdr_entry *entry; + struct ipa3_hdr_entry *next; + struct ipa3_hdr_proc_ctx_entry *ctx_entry; + struct ipa3_hdr_proc_ctx_entry *ctx_next; + struct ipa_hdr_offset_entry *off_entry; + struct ipa_hdr_offset_entry *off_next; + struct ipa3_hdr_proc_ctx_offset_entry *ctx_off_entry; + struct ipa3_hdr_proc_ctx_offset_entry *ctx_off_next; + struct ipa3_hdr_proc_ctx_tbl *htbl_proc = &ipa3_ctx->hdr_proc_ctx_tbl; + enum hdr_tbl_storage hdr_tbl_loc; + int i; + + /* + * issue a reset on the routing module since routing rules point to + * header table entries + */ + if (ipa3_reset_rt(IPA_IP_v4, user_only)) + IPAERR_RL("fail to reset v4 rt\n"); + if (ipa3_reset_rt(IPA_IP_v6, user_only)) + IPAERR_RL("fail to reset v6 rt\n"); + + mutex_lock(&ipa3_ctx->lock); + IPADBG("reset hdr\n"); + for (hdr_tbl_loc = HDR_TBL_LCL; hdr_tbl_loc < HDR_TBLS_TOTAL; hdr_tbl_loc++) { + list_for_each_entry_safe(entry, next, + &ipa3_ctx->hdr_tbl[hdr_tbl_loc].head_hdr_entry_list, link) { + + /* do not remove the default header */ + if (!strcmp(entry->name, IPA_LAN_RX_HDR_NAME)) { + IPADBG("Trying to remove hdr %s offset=%u\n", + entry->name, entry->offset_entry->offset); + if (!entry->offset_entry->offset) { + IPADBG("skip default header\n"); + continue; + } + } + + if (ipa3_id_find(entry->id) == NULL) { + mutex_unlock(&ipa3_ctx->lock); + IPAERR_RL("Invalid header ID\n"); + WARN_ON_RATELIMIT_IPA(1); + return -EFAULT; + } + + if (!user_only || entry->ipacm_installed) { + if (entry->proc_ctx) { + entry->proc_ctx->hdr = NULL; + entry->proc_ctx = NULL; + } + /* move the offset entry to free list */ + entry->offset_entry->ipacm_installed = false; + list_move(&entry->offset_entry->link, + &ipa3_ctx->hdr_tbl[hdr_tbl_loc].head_free_offset_list[ + entry->offset_entry->bin]); + + /* delete the hdr entry from headers list */ + list_del(&entry->link); + ipa3_ctx->hdr_tbl[hdr_tbl_loc].hdr_cnt--; + entry->ref_cnt = 0; + entry->cookie = 0; + + /* remove the handle from the database */ + ipa3_id_remove(entry->id); + kmem_cache_free(ipa3_ctx->hdr_cache, entry); + } + } + + /* only clean up offset_list and free_offset_list on global reset */ + if (!user_only) { + for (i = 0; i < IPA_HDR_BIN_MAX; i++) { + list_for_each_entry_safe(off_entry, off_next, + &ipa3_ctx->hdr_tbl[hdr_tbl_loc].head_offset_list[i], + link) { + /** + * do not remove the default exception + * header which is at offset 0 + */ + if (off_entry->offset == 0) + continue; + list_del(&off_entry->link); + kmem_cache_free(ipa3_ctx->hdr_offset_cache, + off_entry); + } + list_for_each_entry_safe(off_entry, off_next, + &ipa3_ctx->hdr_tbl[hdr_tbl_loc].head_free_offset_list[i], + link) { + list_del(&off_entry->link); + kmem_cache_free(ipa3_ctx->hdr_offset_cache, + off_entry); + } + } + /* there is one header of size 8 */ + ipa3_ctx->hdr_tbl[hdr_tbl_loc].end = 8; + ipa3_ctx->hdr_tbl[hdr_tbl_loc].hdr_cnt = 1; + } + } + + IPADBG("reset hdr proc ctx\n"); + list_for_each_entry_safe( + ctx_entry, + ctx_next, + &(htbl_proc->head_proc_ctx_entry_list), + link) { + + if (ipa3_id_find(ctx_entry->id) == NULL) { + mutex_unlock(&ipa3_ctx->lock); + IPAERR_RL("Invalid proc header ID\n"); + WARN_ON_RATELIMIT_IPA(1); + return -EFAULT; + } + + if (!user_only || + ctx_entry->ipacm_installed) { + /* move the offset entry to appropriate free list */ + list_move(&ctx_entry->offset_entry->link, + &htbl_proc->head_free_offset_list[ + ctx_entry->offset_entry->bin]); + list_del(&ctx_entry->link); + htbl_proc->proc_ctx_cnt--; + ctx_entry->ref_cnt = 0; + ctx_entry->cookie = 0; + + /* remove the handle from the database */ + ipa3_id_remove(ctx_entry->id); + kmem_cache_free(ipa3_ctx->hdr_proc_ctx_cache, + ctx_entry); + } + } + /* only clean up offset_list and free_offset_list on global reset */ + if (!user_only) { + for (i = 0; i < IPA_HDR_PROC_CTX_BIN_MAX; i++) { + list_for_each_entry_safe(ctx_off_entry, ctx_off_next, + &(htbl_proc->head_offset_list[i]), link) { + list_del(&ctx_off_entry->link); + kmem_cache_free( + ipa3_ctx->hdr_proc_ctx_offset_cache, + ctx_off_entry); + } + list_for_each_entry_safe(ctx_off_entry, ctx_off_next, + &(htbl_proc->head_free_offset_list[i]), link) { + list_del(&ctx_off_entry->link); + kmem_cache_free( + ipa3_ctx->hdr_proc_ctx_offset_cache, + ctx_off_entry); + } + } + htbl_proc->end = 0; + htbl_proc->proc_ctx_cnt = 0; + } + + /* commit the change to IPA-HW */ + if (ipa3_ctx->ctrl->ipa3_commit_hdr()) { + IPAERR("fail to commit hdr\n"); + WARN_ON_RATELIMIT_IPA(1); + mutex_unlock(&ipa3_ctx->lock); + return -EFAULT; + } + + mutex_unlock(&ipa3_ctx->lock); + return 0; +} +EXPORT_SYMBOL(ipa3_reset_hdr); + +static struct ipa3_hdr_entry *__ipa_find_hdr(const char *name) +{ + struct ipa3_hdr_entry *entry; + enum hdr_tbl_storage hdr_tbl_loc; + + if (strnlen(name, IPA_RESOURCE_NAME_MAX) == IPA_RESOURCE_NAME_MAX) { + IPAERR_RL("Header name too long: %s\n", name); + return NULL; + } + for (hdr_tbl_loc = HDR_TBL_LCL; hdr_tbl_loc < HDR_TBLS_TOTAL; hdr_tbl_loc++) { + list_for_each_entry(entry, + &ipa3_ctx->hdr_tbl[hdr_tbl_loc].head_hdr_entry_list, + link) { + if (!strcmp(name, entry->name)) + return entry; + } + } + + return NULL; +} + +static struct ipa3_hdr_proc_ctx_entry* __ipa_find_hdr_proc_ctx(const char *name) +{ + struct ipa3_hdr_entry *entry; + + entry = __ipa_find_hdr(name); + if (entry && entry->proc_ctx) + return entry->proc_ctx; + + return NULL; +} + +/** + * ipa_get_hdr() - Lookup the specified header resource + * @lookup: [inout] header to lookup and its handle + * + * lookup the specified header resource and return handle if it exists + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + * Caller should call ipa3_put_hdr later if this function succeeds + */ +int ipa_get_hdr(struct ipa_ioc_get_hdr *lookup) +{ + struct ipa3_hdr_entry *entry; + int result = -1; + + if (lookup == NULL) { + IPAERR_RL("bad parm\n"); + return -EINVAL; + } + mutex_lock(&ipa3_ctx->lock); + lookup->name[IPA_RESOURCE_NAME_MAX-1] = '\0'; + entry = __ipa_find_hdr(lookup->name); + if (entry) { + lookup->hdl = entry->id; + result = 0; + } + mutex_unlock(&ipa3_ctx->lock); + + return result; +} +EXPORT_SYMBOL(ipa_get_hdr); + +/** + * ipa3_get_hdr_offset() - Get the the offset of the specified header resource + * @name: [in] name of header to lookup + * @offset: [out] offset of the specified header + * + * lookup the specified header resource and return its offset if exists + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_get_hdr_offset(char* name, u32* offset) +{ + struct ipa3_hdr_entry *entry; + int result = -1; + if (!name || !offset) { + IPAERR_RL("bad parm\n"); + return -EINVAL; + } + + mutex_lock(&ipa3_ctx->lock); + name[IPA_RESOURCE_NAME_MAX-1] = '\0'; + entry = __ipa_find_hdr(name); + if (entry && entry->offset_entry) { + *offset = entry->offset_entry->offset; + result = 0; + } + + mutex_unlock(&ipa3_ctx->lock); + return result; +} + +/** + * ipa3_get_hdr_proc_ctx_hdl() - Lookup the specified hpc resource + * @lookup: [inout] hpc to lookup and its handle + * + * Lookup the specified hpc resource and return handle if it exists. + * The hpc returned is identified by the hpc pointed by the hdr associated + * with lookup->name. + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_get_hdr_proc_ctx_hdl(struct ipa_ioc_get_hdr *lookup) +{ + struct ipa3_hdr_proc_ctx_entry *entry; + int result = -1; + if (lookup == NULL) { + IPAERR_RL("bad parm\n"); + return -EINVAL; + } + + mutex_lock(&ipa3_ctx->lock); + lookup->name[IPA_RESOURCE_NAME_MAX-1] = '\0'; + entry = __ipa_find_hdr_proc_ctx(lookup->name); + if (entry) { + lookup->hdl = entry->id; + result = 0; + } + + mutex_unlock(&ipa3_ctx->lock); + return result; +} + +/** + * ipa3_get_hdr_proc_ctx_offset() - Lookup the specified hpc resource + * @name: [in] hpc name to lookup + * @offset: [out] offset to of hpc to return + * + * Lookup the specified hpc resource and return offset if it exists. + * The hpc offset returned is of the hpc identified by the hpc pointed + * by the hdr associated with name. The offset returned is in 32B + * and includes the hpc table start offset. + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_get_hdr_proc_ctx_offset(char* name, u32* offset) +{ + struct ipa3_hdr_proc_ctx_entry *entry; + int result = -1; + + if (!name || !offset) { + IPAERR_RL("bad parm\n"); + return -EINVAL; + } + + mutex_lock(&ipa3_ctx->lock); + name[IPA_RESOURCE_NAME_MAX-1] = '\0'; + entry = __ipa_find_hdr_proc_ctx(name); + if (entry && entry->offset_entry) { + /* offset is in 32 Bytes chunks */ + *offset = (entry->offset_entry->offset + + ipa3_ctx->hdr_proc_ctx_tbl.start_offset) >> 5; + result = 0; + } + + mutex_unlock(&ipa3_ctx->lock); + return result; +} + +/** + * __ipa3_release_hdr() - drop reference to header and cause + * deletion if reference count permits + * @hdr_hdl: [in] handle of header to be released + * + * Returns: 0 on success, negative on failure + */ +int __ipa3_release_hdr(u32 hdr_hdl) +{ + int result = 0; + + if (__ipa3_del_hdr(hdr_hdl, false)) { + IPADBG("fail to del hdr %x\n", hdr_hdl); + result = -EFAULT; + goto bail; + } + + /* commit for put */ + if (ipa3_ctx->ctrl->ipa3_commit_hdr()) { + IPAERR("fail to commit hdr\n"); + result = -EFAULT; + goto bail; + } + +bail: + return result; +} + +/** + * __ipa3_release_hdr_proc_ctx() - drop reference to processing context + * and cause deletion if reference count permits + * @proc_ctx_hdl: [in] handle of processing context to be released + * + * Returns: 0 on success, negative on failure + */ +int __ipa3_release_hdr_proc_ctx(u32 proc_ctx_hdl) +{ + int result = 0; + + if (__ipa3_del_hdr_proc_ctx(proc_ctx_hdl, true, false)) { + IPADBG("fail to del hdr %x\n", proc_ctx_hdl); + result = -EFAULT; + goto bail; + } + + /* commit for put */ + if (ipa3_ctx->ctrl->ipa3_commit_hdr()) { + IPAERR("fail to commit hdr\n"); + result = -EFAULT; + goto bail; + } + +bail: + return result; +} + +/** + * ipa3_put_hdr() - Release the specified header handle + * @hdr_hdl: [in] the header handle to release + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_put_hdr(u32 hdr_hdl) +{ + struct ipa3_hdr_entry *entry; + int result = -EFAULT; + + mutex_lock(&ipa3_ctx->lock); + + entry = ipa3_id_find(hdr_hdl); + if (entry == NULL) { + IPAERR_RL("lookup failed\n"); + result = -EINVAL; + goto bail; + } + + if (entry->cookie != IPA_HDR_COOKIE) { + IPAERR_RL("invalid header entry\n"); + result = -EINVAL; + goto bail; + } + + result = 0; +bail: + mutex_unlock(&ipa3_ctx->lock); + return result; +} + +/** + * ipa3_copy_hdr() - Lookup the specified header resource and return a copy of + * it + * @copy: [inout] header to lookup and its copy + * + * lookup the specified header resource and return a copy of it (along with its + * attributes) if it exists, this would be called for partial headers + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_copy_hdr(struct ipa_ioc_copy_hdr *copy) +{ + struct ipa3_hdr_entry *entry; + int result = -EFAULT; + + if (copy == NULL) { + IPAERR_RL("bad parm\n"); + return -EINVAL; + } + mutex_lock(&ipa3_ctx->lock); + copy->name[IPA_RESOURCE_NAME_MAX-1] = '\0'; + entry = __ipa_find_hdr(copy->name); + if (entry) { + memcpy(copy->hdr, entry->hdr, entry->hdr_len); + copy->hdr_len = entry->hdr_len; + copy->type = entry->type; + copy->is_partial = entry->is_partial; + copy->is_eth2_ofst_valid = entry->is_eth2_ofst_valid; + copy->eth2_ofst = entry->eth2_ofst; + result = 0; + } + mutex_unlock(&ipa3_ctx->lock); + + return result; +} + +/** + * ipa3_get_hdr_bin_size() - Get header bin size from specified index + * + * @index: [in] index in the bin sizes array + * + * Returns: bin size on success, MAX_UINT32 on failure + */ +u32 ipa3_get_hdr_bin_size(int index) +{ + if (index < 0 || index >= IPA_HDR_BIN_MAX) + return U32_MAX; + return ipa_hdr_bin_sz[index]; +} diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_hw_stats.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_hw_stats.c new file mode 100644 index 0000000000..28b218e4c9 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_hw_stats.c @@ -0,0 +1,2929 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include "ipa_i.h" +#include "ipahal.h" +#include "ipahal_hw_stats.h" + +#define IPA_INIT_DROP_STATS_MAX_CMD_NUM 5 +#define IPA_INIT_TETH_STATS_MAX_CMD_NUM 5 +#define IPA_INIT_QUOTA_STATS_MAX_CMD_NUM 5 + +static inline u32 ipa_hw_stats_get_ep_bit_n_idx(enum ipa_client_type client, + u32 *reg_idx) +{ + int ep = ipa_get_ep_mapping(client); + + if (ep == IPA_EP_NOT_ALLOCATED) + return 0; + + *reg_idx = ipahal_get_ep_reg_idx(ep); + return ipahal_get_ep_bit(ep); +} + +int ipa_hw_stats_init(void) +{ + int ret = 0, ep_index; + struct ipa_teth_stats_endpoints *teth_stats_init; + u32 reg_idx; + u32 mask = 0; + + if (ipa3_ctx->ipa_hw_type < IPA_HW_v4_0) + return 0; + + ipa3_ctx->hw_stats = kzalloc(sizeof(*ipa3_ctx->hw_stats), GFP_KERNEL); + if (!ipa3_ctx->hw_stats) { + IPAERR("mem allocated failed!\n"); + return -ENOMEM; + } + + /* initialize stats here */ + ipa3_ctx->hw_stats->enabled = true; + + /* for IPA_HW_v5_0, reserved teth_stats sram for flt-tbls */ + if (ipa3_ctx->ipa_hw_type == IPA_HW_v5_0) + return 0; + + teth_stats_init = kzalloc(sizeof(*teth_stats_init), GFP_KERNEL); + if (!teth_stats_init) { + IPAERR("mem allocated failed!\n"); + return -ENOMEM; + } + /* enable prod mask */ + if (ipa3_ctx->platform_type == IPA_PLAT_TYPE_APQ) { + mask = ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_MHI_PRIME_TETH_PROD, + ®_idx); + teth_stats_init->prod_mask[reg_idx] = mask; + + mask = ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_USB_PROD, + ®_idx); + teth_stats_init->prod_mask[reg_idx] |= mask; + + if (ipa3_ctx->ipa_wdi3_over_gsi) { + mask = ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_WLAN2_PROD, + ®_idx); + teth_stats_init->prod_mask[reg_idx] |= mask; + } else { + mask = ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_WLAN1_PROD, + ®_idx); + teth_stats_init->prod_mask[reg_idx] |= mask; + } + + mask = ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_WIGIG_PROD, + ®_idx); + teth_stats_init->prod_mask[reg_idx] |= mask; + + if (ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_MHI_PRIME_TETH_PROD, + ®_idx)) { + ep_index = ipa_get_ep_mapping( + IPA_CLIENT_MHI_PRIME_TETH_PROD); + if (ep_index == -1) { + IPAERR("Invalid client.\n"); + ret = -EINVAL; + goto fail_free_stats_ctx; + } + + mask = ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_USB_CONS, + ®_idx); + teth_stats_init->dst_ep_mask[ep_index][reg_idx] = mask; + + if (ipa3_ctx->ipa_wdi3_over_gsi) { + mask = ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_WLAN2_CONS, + ®_idx); + teth_stats_init->dst_ep_mask[ep_index][reg_idx] + |= mask; + } else { + mask = ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_WLAN1_CONS, + ®_idx); + teth_stats_init->dst_ep_mask[ep_index][reg_idx] + |= mask; + } + + mask = ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_WIGIG1_CONS, + ®_idx); + teth_stats_init->dst_ep_mask[ep_index][reg_idx] |= mask; + mask = ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_WIGIG2_CONS, + ®_idx); + teth_stats_init->dst_ep_mask[ep_index][reg_idx] |= mask; + mask = ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_WIGIG3_CONS, + ®_idx); + teth_stats_init->dst_ep_mask[ep_index][reg_idx] |= mask; + mask = ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_WIGIG4_CONS, + ®_idx); + teth_stats_init->dst_ep_mask[ep_index][reg_idx] |= mask; + } + } else { + mask = ipa_hw_stats_get_ep_bit_n_idx(IPA_CLIENT_Q6_WAN_PROD, + ®_idx); + teth_stats_init->prod_mask[reg_idx] = mask; + + mask = ipa_hw_stats_get_ep_bit_n_idx(IPA_CLIENT_USB_PROD, + ®_idx); + teth_stats_init->prod_mask[reg_idx] |= mask; + + if (ipa3_ctx->ipa_wdi3_over_gsi) { + mask = ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_WLAN2_PROD, + ®_idx); + teth_stats_init->prod_mask[reg_idx] |= mask; + } else { + mask = ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_WLAN1_PROD, + ®_idx); + teth_stats_init->prod_mask[reg_idx] |= mask; + } + + mask = ipa_hw_stats_get_ep_bit_n_idx(IPA_CLIENT_WIGIG_PROD, + ®_idx); + teth_stats_init->prod_mask[reg_idx] |= mask; + + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_5) { + mask = ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_Q6_DL_NLO_DATA_PROD, + ®_idx); + teth_stats_init->prod_mask[reg_idx] |= mask; + } + + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_1) { + mask = ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_Q6_DL_NLO_LL_DATA_PROD, + ®_idx); + teth_stats_init->prod_mask[reg_idx] |= mask; + } + + if (ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_Q6_WAN_PROD, + ®_idx)) { + ep_index = ipa_get_ep_mapping(IPA_CLIENT_Q6_WAN_PROD); + if (ep_index == -1) { + IPAERR("Invalid client.\n"); + ret = -EINVAL; + goto fail_free_stats_ctx; + } + + mask = ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_USB_CONS, + ®_idx); + teth_stats_init->dst_ep_mask[ep_index][reg_idx] = mask; + + if (ipa3_ctx->ipa_wdi3_over_gsi) { + mask = ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_WLAN2_CONS, + ®_idx); + teth_stats_init->dst_ep_mask[ep_index][reg_idx] + |= mask; + } else { + mask = ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_WLAN1_CONS, + ®_idx); + teth_stats_init->dst_ep_mask[ep_index][reg_idx] + |= mask; + } + + mask = ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_WIGIG1_CONS, + ®_idx); + teth_stats_init->dst_ep_mask[ep_index][reg_idx] |= mask; + mask = ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_WIGIG2_CONS, + ®_idx); + teth_stats_init->dst_ep_mask[ep_index][reg_idx] |= mask; + mask = ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_WIGIG3_CONS, + ®_idx); + teth_stats_init->dst_ep_mask[ep_index][reg_idx] |= mask; + mask = ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_WIGIG4_CONS, + ®_idx); + teth_stats_init->dst_ep_mask[ep_index][reg_idx] |= mask; + } + + if (ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_Q6_DL_NLO_DATA_PROD, + ®_idx) && (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_5)) { + ep_index = ipa_get_ep_mapping( + IPA_CLIENT_Q6_DL_NLO_DATA_PROD); + if (ep_index == -1) { + IPAERR("Invalid client.\n"); + ret = -EINVAL; + goto fail_free_stats_ctx; + } + mask = ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_USB_CONS, + ®_idx); + teth_stats_init->dst_ep_mask[ep_index][reg_idx] = mask; + + if (ipa3_ctx->ipa_wdi3_over_gsi) { + mask = ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_WLAN2_CONS, + ®_idx); + teth_stats_init->dst_ep_mask[ep_index][reg_idx] + |= mask; + } else { + mask = ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_WLAN1_CONS, + ®_idx); + teth_stats_init->dst_ep_mask[ep_index][reg_idx] + |= mask; + } + + mask = ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_WIGIG1_CONS, + ®_idx); + teth_stats_init->dst_ep_mask[ep_index][reg_idx] |= mask; + mask = ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_WIGIG2_CONS, + ®_idx); + teth_stats_init->dst_ep_mask[ep_index][reg_idx] |= mask; + mask = ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_WIGIG3_CONS, + ®_idx); + teth_stats_init->dst_ep_mask[ep_index][reg_idx] |= mask; + mask = ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_WIGIG4_CONS, + ®_idx); + teth_stats_init->dst_ep_mask[ep_index][reg_idx] |= mask; + } + + if (ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_Q6_DL_NLO_LL_DATA_PROD, + ®_idx) && (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0)) { + ep_index = ipa_get_ep_mapping( + IPA_CLIENT_Q6_DL_NLO_LL_DATA_PROD); + if (ep_index == -1) { + IPAERR("Invalid client.\n"); + ret = -EINVAL; + goto fail_free_stats_ctx; + } + mask = ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_USB_CONS, + ®_idx); + teth_stats_init->dst_ep_mask[ep_index][reg_idx] = mask; + + if (ipa3_ctx->ipa_wdi3_over_gsi) { + mask = ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_WLAN2_CONS, + ®_idx); + teth_stats_init->dst_ep_mask[ep_index][reg_idx] + |= mask; + } else { + mask = ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_WLAN1_CONS, + ®_idx); + teth_stats_init->dst_ep_mask[ep_index][reg_idx] + |= mask; + } + + mask = ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_WIGIG1_CONS, + ®_idx); + teth_stats_init->dst_ep_mask[ep_index][reg_idx] |= mask; + mask = ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_WIGIG2_CONS, + ®_idx); + teth_stats_init->dst_ep_mask[ep_index][reg_idx] |= mask; + mask = ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_WIGIG3_CONS, + ®_idx); + teth_stats_init->dst_ep_mask[ep_index][reg_idx] |= mask; + mask = ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_WIGIG4_CONS, + ®_idx); + teth_stats_init->dst_ep_mask[ep_index][reg_idx] |= mask; + } + } + + if (ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_USB_PROD, + ®_idx)) { + ep_index = ipa_get_ep_mapping(IPA_CLIENT_USB_PROD); + if (ep_index == -1) { + IPAERR("Invalid client.\n"); + ret = -EINVAL; + goto fail_free_stats_ctx; + } + + mask = ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_Q6_WAN_CONS, + ®_idx); + teth_stats_init->dst_ep_mask[ep_index][reg_idx] = mask; + + /* enable additional pipe monitoring for pcie modem */ + if (ipa3_ctx->platform_type == IPA_PLAT_TYPE_APQ) { + mask = ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_MHI_PRIME_TETH_CONS, + ®_idx); + teth_stats_init->dst_ep_mask[ep_index][reg_idx] |= mask; + } else if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_5) { + mask = ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_Q6_UL_NLO_DATA_CONS, + ®_idx); + teth_stats_init->dst_ep_mask[ep_index][reg_idx] |= mask; + } + } + + if (ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_WLAN1_PROD, + ®_idx)) { + ep_index = ipa_get_ep_mapping(IPA_CLIENT_WLAN1_PROD); + if (ep_index == -1) { + IPAERR("Invalid client.\n"); + ret = -EINVAL; + goto fail_free_stats_ctx; + } + + mask = ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_Q6_WAN_CONS, + ®_idx); + teth_stats_init->dst_ep_mask[ep_index][reg_idx] = mask; + + /* enable additional pipe monitoring for pcie modem*/ + if (ipa3_ctx->platform_type == IPA_PLAT_TYPE_APQ) { + mask = ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_MHI_PRIME_TETH_CONS, + ®_idx); + teth_stats_init->dst_ep_mask[ep_index][reg_idx] |= mask; + } else if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_5) { + mask = ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_Q6_UL_NLO_DATA_CONS, + ®_idx); + teth_stats_init->dst_ep_mask[ep_index][reg_idx] |= mask; + } + } + + if (ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_WLAN2_PROD, + ®_idx)) { + ep_index = ipa_get_ep_mapping(IPA_CLIENT_WLAN2_PROD); + if (ep_index == -1) { + IPAERR("Invalid client.\n"); + ret = -EINVAL; + goto fail_free_stats_ctx; + } + + mask = ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_Q6_WAN_CONS, + ®_idx); + teth_stats_init->dst_ep_mask[ep_index][reg_idx] = mask; + + /* enable additional pipe monitoring for pcie modem*/ + if (ipa3_ctx->platform_type == IPA_PLAT_TYPE_APQ) { + mask = ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_MHI_PRIME_TETH_CONS, + ®_idx); + teth_stats_init->dst_ep_mask[ep_index][reg_idx] |= mask; + } else if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_5) { + mask = ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_Q6_UL_NLO_DATA_CONS, + ®_idx); + teth_stats_init->dst_ep_mask[ep_index][reg_idx] |= mask; + } + } + + if (ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_WIGIG_PROD, + ®_idx)) { + ep_index = ipa_get_ep_mapping(IPA_CLIENT_WIGIG_PROD); + if (ep_index == -1) { + IPAERR("Invalid client.\n"); + ret = -EINVAL; + goto fail_free_stats_ctx; + } + + mask = ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_Q6_WAN_CONS, + ®_idx); + teth_stats_init->dst_ep_mask[ep_index][reg_idx] = mask; + + /* enable additional pipe monitoring for pcie modem */ + if (ipa3_ctx->platform_type == IPA_PLAT_TYPE_APQ) { + mask = ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_MHI_PRIME_TETH_CONS, + ®_idx); + teth_stats_init->dst_ep_mask[ep_index][reg_idx] |= mask; + } else if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_5) { + mask = ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_Q6_UL_NLO_DATA_CONS, + ®_idx); + teth_stats_init->dst_ep_mask[ep_index][reg_idx] |= mask; + } + } + + + ret = ipa_init_teth_stats(teth_stats_init); + if (ret != 0) { + IPAERR("init teth stats fails\n"); + goto fail_free_stats_ctx; + } + + ipa3_ctx->hw_stats->teth_stats_enabled = true; + kfree(teth_stats_init); + return ret; + +fail_free_stats_ctx: + kfree(teth_stats_init); + kfree(ipa3_ctx->hw_stats); + ipa3_ctx->hw_stats = NULL; + return ret; +} + +static void ipa_close_coal_frame(struct ipahal_imm_cmd_pyld **coal_cmd_pyld) +{ + int i; + struct ipahal_reg_valmask valmask; + struct ipahal_imm_cmd_register_write reg_write_coal_close; + u32 offset = 0; + + i = ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS); + reg_write_coal_close.skip_pipeline_clear = false; + reg_write_coal_close.pipeline_clear_options = IPAHAL_HPS_CLEAR; + if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0) + offset = ipahal_get_reg_ofst( + IPA_AGGR_FORCE_CLOSE); + else + offset = ipahal_get_ep_reg_offset( + IPA_AGGR_FORCE_CLOSE_n, i); + reg_write_coal_close.offset = offset; + ipahal_get_aggr_force_close_valmask(i, &valmask); + reg_write_coal_close.value = valmask.val; + reg_write_coal_close.value_mask = valmask.mask; + *coal_cmd_pyld = ipahal_construct_imm_cmd( + IPA_IMM_CMD_REGISTER_WRITE, + ®_write_coal_close, false); +} + +static bool ipa_validate_quota_stats_sram_size(u32 needed_len) +{ + u32 sram_size; + + /* Starting IPA4.5 Quota stats is split between Q6 and AP */ + + if (ipa3_ctx->ipa_hw_type < IPA_HW_v4_5) { + IPAERR("Not supported ipa_ver=%d\n", ipa3_ctx->ipa_hw_type); + return false; + } + + sram_size = IPA_MEM_PART(stats_quota_ap_size); + if (needed_len > sram_size) { + IPAERR("SRAM partition too small: %u needed %u\n", + sram_size, needed_len); + return false; + } + + return true; +} + +int ipa_init_quota_stats(u32 *pipe_bitmask) +{ + struct ipahal_stats_init_pyld *pyld; + struct ipahal_imm_cmd_dma_shared_mem cmd = { 0 }; + struct ipahal_imm_cmd_pyld *cmd_pyld; + struct ipahal_imm_cmd_register_write quota_base = {0}; + struct ipahal_imm_cmd_pyld *quota_base_pyld; + struct ipahal_imm_cmd_register_write quota_mask = {0}; + struct ipahal_imm_cmd_pyld *quota_mask_pyld[IPA5_PIPE_REG_NUM] = {0}; + struct ipahal_imm_cmd_pyld *coal_cmd_pyld = NULL; + struct ipa3_desc desc[IPA_INIT_QUOTA_STATS_MAX_CMD_NUM] = { {0} }; + dma_addr_t dma_address; + int ret; + int num_cmd = 0; + int ipa_ep_idx = IPA_EP_NOT_ALLOCATED; + int i; + + if (!(ipa3_ctx->hw_stats && ipa3_ctx->hw_stats->enabled)) + return 0; + + if (!pipe_bitmask) + return -EPERM; + + /* reset driver's cache */ + memset(&ipa3_ctx->hw_stats->quota, 0, sizeof(ipa3_ctx->hw_stats->quota)); + for (i = 0; i < IPA5_PIPE_REG_NUM; i++) { + ipa3_ctx->hw_stats->quota.init.enabled_bitmask[i] = + pipe_bitmask[i]; + IPADBG_LOW("pipe_bitmask[%d]=0x%x\n", i, pipe_bitmask[i]); + } + + pyld = ipahal_stats_generate_init_pyld(IPAHAL_HW_STATS_QUOTA, + &ipa3_ctx->hw_stats->quota.init, false); + if (!pyld) { + IPAERR("failed to generate pyld\n"); + return -EPERM; + } + + if (!ipa_validate_quota_stats_sram_size(pyld->len)) { + ret = -EPERM; + goto destroy_init_pyld; + } + + dma_address = dma_map_single(ipa3_ctx->pdev, + pyld->data, + pyld->len, + DMA_TO_DEVICE); + if (dma_mapping_error(ipa3_ctx->pdev, dma_address)) { + IPAERR("failed to DMA map\n"); + ret = -EPERM; + goto destroy_init_pyld; + } + + /* IC to close the coal frame before HPS Clear if coal is enabled */ + ipa_ep_idx = ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS); + if (ipa_ep_idx != IPA_EP_NOT_ALLOCATED && !ipa3_ctx->ulso_wa) { + ipa_close_coal_frame(&coal_cmd_pyld); + if (!coal_cmd_pyld) { + IPAERR("failed to construct coal close IC\n"); + ret = -ENOMEM; + goto unmap; + } + ipa3_init_imm_cmd_desc(&desc[num_cmd], coal_cmd_pyld); + ++num_cmd; + } + + /* setting the registers and init the stats pyld are done atomically */ + quota_mask.skip_pipeline_clear = false; + quota_mask.pipeline_clear_options = IPAHAL_FULL_PIPELINE_CLEAR; + if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0) { + quota_mask.offset = ipahal_get_reg_n_ofst(IPA_STAT_QUOTA_MASK_n, + ipa3_ctx->ee); + quota_mask.value = pipe_bitmask[0]; + quota_mask.value_mask = ~0; + quota_mask_pyld[0] = ipahal_construct_imm_cmd( + IPA_IMM_CMD_REGISTER_WRITE, + "a_mask, false); + if (!quota_mask_pyld[0]) { + IPAERR("failed to construct register_write imm cmd\n"); + ret = -ENOMEM; + goto destroy_coal_cmd; + } + desc[num_cmd].opcode = quota_mask_pyld[0]->opcode; + desc[num_cmd].pyld = quota_mask_pyld[0]->data; + desc[num_cmd].len = quota_mask_pyld[0]->len; + desc[num_cmd].type = IPA_IMM_CMD_DESC; + num_cmd++; + } else { + for (i = 0; i < IPA5_PIPE_REG_NUM; i++) { + quota_mask.value = pipe_bitmask[i]; + quota_mask.value_mask = ~0; + quota_mask.offset = ipahal_get_reg_nk_offset( + IPA_STAT_QUOTA_MASK_EE_n_REG_k, + ipa3_ctx->ee, i); + quota_mask_pyld[i] = ipahal_construct_imm_cmd( + IPA_IMM_CMD_REGISTER_WRITE, + "a_mask, false); + if (!quota_mask_pyld[i]) { + int j; + + IPAERR( + "failed to construct register_write imm cmd\n" + ); + for (j = i - 1; j >= 0; j--) + ipahal_destroy_imm_cmd( + quota_mask_pyld[j]); + ret = -ENOMEM; + goto destroy_coal_cmd; + } + desc[num_cmd].opcode = quota_mask_pyld[i]->opcode; + desc[num_cmd].pyld = quota_mask_pyld[i]->data; + desc[num_cmd].len = quota_mask_pyld[i]->len; + desc[num_cmd].type = IPA_IMM_CMD_DESC; + num_cmd++; + } + } + + quota_base.skip_pipeline_clear = false; + quota_base.pipeline_clear_options = IPAHAL_FULL_PIPELINE_CLEAR; + quota_base.offset = ipahal_get_reg_n_ofst(IPA_STAT_QUOTA_BASE_n, + ipa3_ctx->ee); + quota_base.value = ipa3_ctx->smem_restricted_bytes + + IPA_MEM_PART(stats_quota_ap_ofst); + quota_base.value_mask = ~0; + quota_base_pyld = ipahal_construct_imm_cmd(IPA_IMM_CMD_REGISTER_WRITE, + "a_base, false); + if (!quota_base_pyld) { + IPAERR("failed to construct register_write imm cmd\n"); + ret = -ENOMEM; + goto destroy_quota_mask; + } + desc[num_cmd].opcode = quota_base_pyld->opcode; + desc[num_cmd].pyld = quota_base_pyld->data; + desc[num_cmd].len = quota_base_pyld->len; + desc[num_cmd].type = IPA_IMM_CMD_DESC; + num_cmd++; + + cmd.is_read = false; + cmd.skip_pipeline_clear = false; + cmd.pipeline_clear_options = IPAHAL_FULL_PIPELINE_CLEAR; + cmd.size = pyld->len; + cmd.system_addr = dma_address; + cmd.local_addr = ipa3_ctx->smem_restricted_bytes + + IPA_MEM_PART(stats_quota_ap_ofst); + cmd_pyld = ipahal_construct_imm_cmd( + IPA_IMM_CMD_DMA_SHARED_MEM, &cmd, false); + if (!cmd_pyld) { + IPAERR("failed to construct dma_shared_mem imm cmd\n"); + ret = -ENOMEM; + goto destroy_quota_base; + } + desc[num_cmd].opcode = cmd_pyld->opcode; + desc[num_cmd].pyld = cmd_pyld->data; + desc[num_cmd].len = cmd_pyld->len; + desc[num_cmd].type = IPA_IMM_CMD_DESC; + num_cmd++; + + ret = ipa3_send_cmd(num_cmd, desc); + if (ret) { + IPAERR("failed to send immediate command (error %d)\n", ret); + goto destroy_imm; + } + + ret = 0; + +destroy_imm: + ipahal_destroy_imm_cmd(cmd_pyld); +destroy_quota_base: + ipahal_destroy_imm_cmd(quota_base_pyld); +destroy_quota_mask: + for (i = 0; i < IPA5_PIPE_REG_NUM; i++) + if (quota_mask_pyld[i]) + ipahal_destroy_imm_cmd(quota_mask_pyld[i]); +destroy_coal_cmd: + ipahal_destroy_imm_cmd(coal_cmd_pyld); +unmap: + dma_unmap_single(ipa3_ctx->pdev, dma_address, pyld->len, DMA_TO_DEVICE); +destroy_init_pyld: + ipahal_destroy_stats_init_pyld(pyld); + return ret; +} + +int ipa_get_quota_stats(struct ipa_quota_stats_all *out) +{ + int i; + int ret; + struct ipahal_stats_get_offset_quota get_offset = { { 0 } }; + struct ipahal_stats_offset offset = { 0 }; + struct ipahal_imm_cmd_dma_shared_mem cmd = { 0 }; + struct ipahal_imm_cmd_pyld *cmd_pyld[2]; + struct ipa_mem_buffer mem; + struct ipa3_desc desc[2]; + struct ipahal_stats_quota_all *stats; + int num_cmd = 0; + + if (!(ipa3_ctx->hw_stats && ipa3_ctx->hw_stats->enabled)) + return 0; + + memset(desc, 0, sizeof(desc)); + memset(cmd_pyld, 0, sizeof(cmd_pyld)); + + get_offset.init = ipa3_ctx->hw_stats->quota.init; + ret = ipahal_stats_get_offset(IPAHAL_HW_STATS_QUOTA, &get_offset, + &offset); + if (ret) { + IPAERR("failed to get offset from hal %d\n", ret); + return ret; + } + + IPADBG_LOW("offset = %d size = %d\n", offset.offset, offset.size); + + if (offset.size == 0) + return 0; + + mem.size = offset.size; + mem.base = dma_alloc_coherent(ipa3_ctx->pdev, + mem.size, + &mem.phys_base, + GFP_KERNEL); + if (!mem.base) { + IPAERR("fail to alloc DMA memory"); + return ret; + } + + /* IC to close the coal frame before HPS Clear if coal is enabled */ + if (ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS) != + IPA_EP_NOT_ALLOCATED && !ipa3_ctx->ulso_wa) { + ipa_close_coal_frame(&cmd_pyld[num_cmd]); + if (!cmd_pyld[num_cmd]) { + IPAERR("failed to construct coal close IC\n"); + ret = -ENOMEM; + goto free_dma_mem; + } + ipa3_init_imm_cmd_desc(&desc[num_cmd], cmd_pyld[num_cmd]); + ++num_cmd; + } + + cmd.is_read = true; + cmd.clear_after_read = true; + cmd.skip_pipeline_clear = false; + cmd.pipeline_clear_options = IPAHAL_HPS_CLEAR; + cmd.size = mem.size; + cmd.system_addr = mem.phys_base; + cmd.local_addr = ipa3_ctx->smem_restricted_bytes + + IPA_MEM_PART(stats_quota_ap_ofst) + offset.offset; + cmd_pyld[num_cmd] = ipahal_construct_imm_cmd( + IPA_IMM_CMD_DMA_SHARED_MEM, &cmd, false); + if (!cmd_pyld[num_cmd]) { + IPAERR("failed to construct dma_shared_mem imm cmd\n"); + ret = -ENOMEM; + goto free_dma_mem; + } + ipa3_init_imm_cmd_desc(&desc[num_cmd], cmd_pyld[num_cmd]); + ++num_cmd; + + ret = ipa3_send_cmd(num_cmd, desc); + if (ret) { + IPAERR("failed to send immediate command (error %d)\n", ret); + goto destroy_imm; + } + + stats = kzalloc(sizeof(*stats), GFP_KERNEL); + if (!stats) { + ret = -ENOMEM; + goto destroy_imm; + } + + ret = ipahal_parse_stats(IPAHAL_HW_STATS_QUOTA, + &ipa3_ctx->hw_stats->quota.init, mem.base, stats); + if (ret) { + IPAERR("failed to parse stats (error %d)\n", ret); + goto free_stats; + } + + /* + * update driver cache. + * the stats were read from hardware with clear_after_read meaning + * hardware stats are 0 now + */ + for (i = 0; i < IPA_CLIENT_MAX; i++) { + int ep_idx = ipa_get_ep_mapping(i); + + if (ep_idx == -1 || ep_idx >= ipa3_get_max_num_pipes()) + continue; + + if (ipa3_ctx->ep[ep_idx].client != i) + continue; + + ipa3_ctx->hw_stats->quota.stats.client[ep_idx].num_ipv4_bytes += + stats->stats[ep_idx].num_ipv4_bytes; + ipa3_ctx->hw_stats->quota.stats.client[ep_idx].num_ipv4_pkts += + stats->stats[ep_idx].num_ipv4_pkts; + ipa3_ctx->hw_stats->quota.stats.client[ep_idx].num_ipv6_bytes += + stats->stats[ep_idx].num_ipv6_bytes; + ipa3_ctx->hw_stats->quota.stats.client[ep_idx].num_ipv6_pkts += + stats->stats[ep_idx].num_ipv6_pkts; + } + + /* copy results to out parameter */ + if (out) + *out = ipa3_ctx->hw_stats->quota.stats; + ret = 0; +free_stats: + kfree(stats); +destroy_imm: + for (i = 0; i < num_cmd; i++) + ipahal_destroy_imm_cmd(cmd_pyld[i]); +free_dma_mem: + dma_free_coherent(ipa3_ctx->pdev, mem.size, mem.base, mem.phys_base); + return ret; + +} + +int ipa_reset_quota_stats(enum ipa_client_type client) +{ + int ret; + struct ipa_quota_stats *stats; + int ep_idx; + + if (!(ipa3_ctx->hw_stats && ipa3_ctx->hw_stats->enabled)) + return 0; + + if (client >= IPA_CLIENT_MAX) { + IPAERR("invalid client %d\n", client); + return -EINVAL; + } + + /* reading stats will reset them in hardware */ + ret = ipa_get_quota_stats(NULL); + if (ret) { + IPAERR("ipa_get_quota_stats failed %d\n", ret); + return ret; + } + + ep_idx = ipa_get_ep_mapping(client); + if (ep_idx == IPA_EP_NOT_ALLOCATED) { + IPAERR("EP not allocated for client %d\n", client); + return EINVAL; + } + + /* reset driver's cache */ + stats = &ipa3_ctx->hw_stats->quota.stats.client[ep_idx]; + memset(stats, 0, sizeof(*stats)); + return 0; +} + +int ipa_reset_all_quota_stats(void) +{ + int ret; + struct ipa_quota_stats_all *stats; + + if (!(ipa3_ctx->hw_stats && ipa3_ctx->hw_stats->enabled)) + return 0; + + /* reading stats will reset them in hardware */ + ret = ipa_get_quota_stats(NULL); + if (ret) { + IPAERR("ipa_get_quota_stats failed %d\n", ret); + return ret; + } + + /* reset driver's cache */ + stats = &ipa3_ctx->hw_stats->quota.stats; + memset(stats, 0, sizeof(*stats)); + return 0; +} + +int ipa_init_teth_stats(struct ipa_teth_stats_endpoints *in) +{ + struct ipahal_stats_init_pyld *pyld; + struct ipahal_imm_cmd_dma_shared_mem cmd = { 0 }; + struct ipahal_imm_cmd_pyld *cmd_pyld; + struct ipahal_imm_cmd_register_write teth_base = {0}; + struct ipahal_imm_cmd_pyld *teth_base_pyld; + struct ipahal_imm_cmd_register_write teth_mask = { 0 }; + struct ipahal_imm_cmd_pyld *teth_mask_pyld[IPA5_PIPE_REG_NUM] = {0}; + struct ipahal_imm_cmd_pyld *coal_cmd_pyld = NULL; + struct ipa3_desc desc[IPA_INIT_TETH_STATS_MAX_CMD_NUM] = { {0} }; + dma_addr_t dma_address; + int ret; + int i, j; + int reg_idx; + int num_cmd = 0; + + + if (!(ipa3_ctx->hw_stats && ipa3_ctx->hw_stats->enabled)) + return 0; + + if (!in || (!in->prod_mask[0] && !in->prod_mask[1])) { + IPAERR("invalid params\n"); + return -EINVAL; + } + + reg_idx = 0; + for (i = 0; i < IPA5_PIPES_NUM; i++) { + if (i > 0 && !(i % IPA_STATS_MAX_PIPE_BIT)) { + reg_idx++; + } + if (in->prod_mask[reg_idx] & ipahal_get_ep_bit(i)) { + bool has_cons = false; + + for (j = 0; j < IPA5_PIPE_REG_NUM; j++) { + if (in->dst_ep_mask[i][j]) + has_cons = true; + } + if (!has_cons) { + IPAERR("prod %d doesn't have cons\n", i); + return -EINVAL; + } + } + } + + IPADBG("prod_mask=[0x%x][0x%x]\n", + in->prod_mask[0], in->prod_mask[1]); + + /* reset driver's cache */ + memset(&ipa3_ctx->hw_stats->teth.init, 0, + sizeof(ipa3_ctx->hw_stats->teth.init)); + for (i = 0; i < IPA5_PIPES_NUM; i++) { + memset(&ipa3_ctx->hw_stats->teth.prod_stats_sum[i], 0, + sizeof(ipa3_ctx->hw_stats->teth.prod_stats_sum[i])); + memset(&ipa3_ctx->hw_stats->teth.prod_stats[i], 0, + sizeof(ipa3_ctx->hw_stats->teth.prod_stats[i])); + } + for (i = 0; i < IPA5_PIPE_REG_NUM; i++) { + ipa3_ctx->hw_stats->teth.init.prod_bitmask[i] = in->prod_mask[i]; + } + + memcpy(ipa3_ctx->hw_stats->teth.init.cons_bitmask, in->dst_ep_mask, + sizeof(ipa3_ctx->hw_stats->teth.init.cons_bitmask)); + + pyld = ipahal_stats_generate_init_pyld(IPAHAL_HW_STATS_TETHERING, + &ipa3_ctx->hw_stats->teth.init, false); + if (!pyld) { + IPAERR("failed to generate pyld\n"); + return -EPERM; + } + + if (pyld->len > IPA_MEM_PART(stats_tethering_size)) { + IPAERR("SRAM partition too small: %d needed %d\n", + IPA_MEM_PART(stats_tethering_size), pyld->len); + ret = -EPERM; + goto destroy_init_pyld; + } + + dma_address = dma_map_single(ipa3_ctx->pdev, + pyld->data, + pyld->len, + DMA_TO_DEVICE); + if (dma_mapping_error(ipa3_ctx->pdev, dma_address)) { + IPAERR("failed to DMA map\n"); + ret = -EPERM; + goto destroy_init_pyld; + } + + /* IC to close the coal frame before HPS Clear if coal is enabled */ + if (ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS) != + IPA_EP_NOT_ALLOCATED && !ipa3_ctx->ulso_wa) { + ipa_close_coal_frame(&coal_cmd_pyld); + if (!coal_cmd_pyld) { + IPAERR("failed to construct coal close IC\n"); + ret = -ENOMEM; + goto unmap; + } + ipa3_init_imm_cmd_desc(&desc[num_cmd], coal_cmd_pyld); + ++num_cmd; + } + + /* setting the registers and init the stats pyld are done atomically */ + teth_mask.skip_pipeline_clear = false; + teth_mask.pipeline_clear_options = IPAHAL_FULL_PIPELINE_CLEAR; + teth_mask.value_mask = ~0; + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0) { + for (i = 0; i < IPA5_PIPE_REG_NUM; i++) { + teth_mask.offset = ipahal_get_reg_nk_offset( + IPA_STAT_TETHERING_MASK_EE_n_REG_k, + ipa3_ctx->ee, i); + teth_mask.value = in->prod_mask[i]; + teth_mask_pyld[i] = ipahal_construct_imm_cmd( + IPA_IMM_CMD_REGISTER_WRITE, + &teth_mask, false); + if (!teth_mask_pyld[i]) { + IPAERR( + "failed to construct register_write imm cmd\n"); + for (j = i - 1; j >= 0; j--) { + ipahal_destroy_imm_cmd( + teth_mask_pyld[j]); + teth_mask_pyld[j] = NULL; + } + ret = -ENOMEM; + goto destroy_coal_cmd; + } + desc[num_cmd].opcode = teth_mask_pyld[i]->opcode; + desc[num_cmd].pyld = teth_mask_pyld[i]->data; + desc[num_cmd].len = teth_mask_pyld[i]->len; + desc[num_cmd].type = IPA_IMM_CMD_DESC; + ++num_cmd; + } + + } else { + teth_mask.offset = ipahal_get_reg_n_ofst( + IPA_STAT_TETHERING_MASK_n, + ipa3_ctx->ee); + teth_mask.value = in->prod_mask[0]; + teth_mask_pyld[0] = ipahal_construct_imm_cmd( + IPA_IMM_CMD_REGISTER_WRITE, + &teth_mask, false); + if (!teth_mask_pyld[0]) { + IPAERR("failed to construct register_write imm cmd\n"); + ret = -ENOMEM; + goto destroy_coal_cmd; + } + desc[num_cmd].opcode = teth_mask_pyld[0]->opcode; + desc[num_cmd].pyld = teth_mask_pyld[0]->data; + desc[num_cmd].len = teth_mask_pyld[0]->len; + desc[num_cmd].type = IPA_IMM_CMD_DESC; + ++num_cmd; + } + + teth_base.skip_pipeline_clear = false; + teth_base.pipeline_clear_options = IPAHAL_FULL_PIPELINE_CLEAR; + teth_base.offset = ipahal_get_reg_n_ofst(IPA_STAT_TETHERING_BASE_n, + ipa3_ctx->ee); + teth_base.value = ipa3_ctx->smem_restricted_bytes + + IPA_MEM_PART(stats_tethering_ofst); + teth_base.value_mask = ~0; + teth_base_pyld = ipahal_construct_imm_cmd(IPA_IMM_CMD_REGISTER_WRITE, + &teth_base, false); + if (!teth_base_pyld) { + IPAERR("failed to construct register_write imm cmd\n"); + ret = -ENOMEM; + goto destroy_teth_mask; + } + desc[num_cmd].opcode = teth_base_pyld->opcode; + desc[num_cmd].pyld = teth_base_pyld->data; + desc[num_cmd].len = teth_base_pyld->len; + desc[num_cmd].type = IPA_IMM_CMD_DESC; + ++num_cmd; + + cmd.is_read = false; + cmd.skip_pipeline_clear = false; + cmd.pipeline_clear_options = IPAHAL_FULL_PIPELINE_CLEAR; + cmd.size = pyld->len; + cmd.system_addr = dma_address; + cmd.local_addr = ipa3_ctx->smem_restricted_bytes + + IPA_MEM_PART(stats_tethering_ofst); + cmd_pyld = ipahal_construct_imm_cmd( + IPA_IMM_CMD_DMA_SHARED_MEM, &cmd, false); + if (!cmd_pyld) { + IPAERR("failed to construct dma_shared_mem imm cmd\n"); + ret = -ENOMEM; + goto destroy_teth_base; + } + desc[num_cmd].opcode = cmd_pyld->opcode; + desc[num_cmd].pyld = cmd_pyld->data; + desc[num_cmd].len = cmd_pyld->len; + desc[num_cmd].type = IPA_IMM_CMD_DESC; + ++num_cmd; + + ret = ipa3_send_cmd(num_cmd, desc); + if (ret) { + IPAERR("failed to send immediate command (error %d)\n", ret); + goto destroy_imm; + } + + ret = 0; + +destroy_imm: + ipahal_destroy_imm_cmd(cmd_pyld); +destroy_teth_base: + ipahal_destroy_imm_cmd(teth_base_pyld); +destroy_teth_mask: + for (i = 0; i < IPA5_PIPE_REG_NUM; i++) { + if (teth_mask_pyld[i]) + ipahal_destroy_imm_cmd(teth_mask_pyld[i]); + } +destroy_coal_cmd: + if (coal_cmd_pyld) + ipahal_destroy_imm_cmd(coal_cmd_pyld); +unmap: + dma_unmap_single(ipa3_ctx->pdev, dma_address, pyld->len, DMA_TO_DEVICE); +destroy_init_pyld: + ipahal_destroy_stats_init_pyld(pyld); + return ret; +} + +int ipa_get_teth_stats(void) +{ + int i, j; + int prod_reg, cons_reg; + int ret; + struct ipahal_stats_get_offset_tethering get_offset; + struct ipahal_stats_offset offset = {0}; + struct ipahal_imm_cmd_dma_shared_mem cmd = { 0 }; + struct ipahal_imm_cmd_pyld *cmd_pyld[2]; + struct ipa_mem_buffer mem; + struct ipa3_desc desc[2]; + struct ipahal_stats_tethering_all *stats_all; + struct ipa_hw_stats_teth *sw_stats; + struct ipahal_stats_tethering *stats; + struct ipa_quota_stats *quota_stats; + struct ipahal_stats_init_tethering *init; + int num_cmd = 0; + + if (!(ipa3_ctx->hw_stats && ipa3_ctx->hw_stats->enabled && + ipa3_ctx->hw_stats->teth_stats_enabled)) + return 0; + + sw_stats = &ipa3_ctx->hw_stats->teth; + init = (struct ipahal_stats_init_tethering *) + &ipa3_ctx->hw_stats->teth.init; + + memset(desc, 0, sizeof(desc)); + memset(cmd_pyld, 0, sizeof(cmd_pyld)); + memset(&get_offset, 0, sizeof(get_offset)); + + get_offset.init = ipa3_ctx->hw_stats->teth.init; + ret = ipahal_stats_get_offset(IPAHAL_HW_STATS_TETHERING, &get_offset, + &offset); + if (ret) { + IPAERR("failed to get offset from hal %d\n", ret); + return ret; + } + + IPADBG_LOW("offset = %d size = %d\n", offset.offset, offset.size); + + if (offset.size == 0) + return 0; + + mem.size = offset.size; + mem.base = dma_alloc_coherent(ipa3_ctx->pdev, + mem.size, + &mem.phys_base, + GFP_KERNEL); + if (!mem.base) { + IPAERR("fail to alloc DMA memory\n"); + return ret; + } + + /* IC to close the coal frame before HPS Clear if coal is enabled */ + if (ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS) != + IPA_EP_NOT_ALLOCATED && !ipa3_ctx->ulso_wa) { + ipa_close_coal_frame(&cmd_pyld[num_cmd]); + if (!cmd_pyld[num_cmd]) { + IPAERR("failed to construct coal close IC\n"); + ret = -ENOMEM; + goto free_dma_mem; + } + ipa3_init_imm_cmd_desc(&desc[num_cmd], cmd_pyld[num_cmd]); + ++num_cmd; + } + + cmd.is_read = true; + cmd.clear_after_read = true; + cmd.skip_pipeline_clear = false; + cmd.pipeline_clear_options = IPAHAL_HPS_CLEAR; + cmd.size = mem.size; + cmd.system_addr = mem.phys_base; + cmd.local_addr = ipa3_ctx->smem_restricted_bytes + + IPA_MEM_PART(stats_tethering_ofst) + offset.offset; + cmd_pyld[num_cmd] = ipahal_construct_imm_cmd( + IPA_IMM_CMD_DMA_SHARED_MEM, &cmd, false); + if (!cmd_pyld[num_cmd]) { + IPAERR("failed to construct dma_shared_mem imm cmd\n"); + ret = -ENOMEM; + goto destroy_imm; + } + ipa3_init_imm_cmd_desc(&desc[num_cmd], cmd_pyld[num_cmd]); + ++num_cmd; + + ret = ipa3_send_cmd(num_cmd, desc); + if (ret) { + IPAERR("failed to send immediate command (error %d)\n", ret); + goto destroy_imm; + } + + stats_all = vmalloc(sizeof(*stats_all)); + if (!stats_all) { + IPADBG("failed to alloc memory\n"); + ret = -ENOMEM; + goto destroy_imm; + } + + ret = ipahal_parse_stats(IPAHAL_HW_STATS_TETHERING, + &ipa3_ctx->hw_stats->teth.init, mem.base, stats_all); + if (ret) { + IPAERR("failed to parse stats_all (error %d)\n", ret); + goto free_stats; + } + + /* reset prod_stats cache */ + for (i = 0; i < IPA5_PIPES_NUM; i++) { + memset(&ipa3_ctx->hw_stats->teth.prod_stats[i], 0, + sizeof(ipa3_ctx->hw_stats->teth.prod_stats[i])); + } + + /* + * update driver cache. + * the stats were read from hardware with clear_after_read meaning + * hardware stats are 0 now + */ + for (i = 0; i < IPA_CLIENT_MAX; i++) { + for (j = 0; j < IPA_CLIENT_MAX; j++) { + int prod_idx = ipa_get_ep_mapping(i); + int cons_idx = ipa_get_ep_mapping(j); + + if (prod_idx == -1 || + prod_idx >= ipa3_get_max_num_pipes()) + continue; + + if (cons_idx == -1 || + cons_idx >= ipa3_get_max_num_pipes()) + continue; + + prod_reg = ipahal_get_ep_reg_idx(prod_idx); + cons_reg = ipahal_get_ep_reg_idx(cons_idx); + + /* save hw-query result */ + if ((init->prod_bitmask[prod_reg] & + ipahal_get_ep_bit(prod_idx)) && + (init->cons_bitmask[prod_idx][cons_reg] + & ipahal_get_ep_bit(cons_idx))) { + IPADBG_LOW("prod %d cons %d\n", + prod_idx, cons_idx); + stats = &stats_all->stats[prod_idx][cons_idx]; + IPADBG_LOW("num_ipv4_bytes %lld\n", + stats->num_ipv4_bytes); + IPADBG_LOW("num_ipv4_pkts %lld\n", + stats->num_ipv4_pkts); + IPADBG_LOW("num_ipv6_pkts %lld\n", + stats->num_ipv6_pkts); + IPADBG_LOW("num_ipv6_bytes %lld\n", + stats->num_ipv6_bytes); + + /* update stats*/ + quota_stats = + &sw_stats->prod_stats[prod_idx].client[cons_idx]; + quota_stats->num_ipv4_bytes = + stats->num_ipv4_bytes; + quota_stats->num_ipv4_pkts = + stats->num_ipv4_pkts; + quota_stats->num_ipv6_bytes = + stats->num_ipv6_bytes; + quota_stats->num_ipv6_pkts = + stats->num_ipv6_pkts; + + /* Accumulated stats */ + quota_stats = + &sw_stats->prod_stats_sum[prod_idx].client[cons_idx]; + quota_stats->num_ipv4_bytes += + stats->num_ipv4_bytes; + quota_stats->num_ipv4_pkts += + stats->num_ipv4_pkts; + quota_stats->num_ipv6_bytes += + stats->num_ipv6_bytes; + quota_stats->num_ipv6_pkts += + stats->num_ipv6_pkts; + } + } + } + + ret = 0; +free_stats: + vfree(stats_all); + stats = NULL; +destroy_imm: + for (i = 0; i < num_cmd; i++) + ipahal_destroy_imm_cmd(cmd_pyld[i]); +free_dma_mem: + dma_free_coherent(ipa3_ctx->pdev, mem.size, mem.base, mem.phys_base); + return ret; + +} + +int ipa_query_teth_stats(enum ipa_client_type prod, + struct ipa_quota_stats_all *out, bool reset) +{ + int ipa_ep_idx; + + if (!(ipa3_ctx->hw_stats && ipa3_ctx->hw_stats->enabled && + ipa3_ctx->hw_stats->teth_stats_enabled)) + return 0; + + if (!IPA_CLIENT_IS_PROD(prod) || ipa_get_ep_mapping(prod) == -1) { + IPAERR("invalid prod %d\n", prod); + return -EINVAL; + } + + ipa_ep_idx = ipa_get_ep_mapping(prod); + if (ipa_ep_idx == IPA_EP_NOT_ALLOCATED) { + IPAERR("EP not allocated for prod %d\n", prod); + return EINVAL; + } + + /* copy results to out parameter */ + if (reset) + *out = ipa3_ctx->hw_stats->teth.prod_stats[ipa_ep_idx]; + else + *out = ipa3_ctx->hw_stats->teth.prod_stats_sum[ipa_ep_idx]; + return 0; +} + +int ipa_reset_teth_stats(enum ipa_client_type prod, enum ipa_client_type cons) +{ + int ret; + struct ipa_quota_stats *stats; + int prod_ep_idx, cons_ep_idx; + + if (!(ipa3_ctx->hw_stats && ipa3_ctx->hw_stats->enabled && + ipa3_ctx->hw_stats->teth_stats_enabled)) + return 0; + + if (!IPA_CLIENT_IS_PROD(prod) || !IPA_CLIENT_IS_CONS(cons)) { + IPAERR("invalid prod %d or cons %d\n", prod, cons); + return -EINVAL; + } + + prod_ep_idx = ipa_get_ep_mapping(prod); + if (prod_ep_idx == IPA_EP_NOT_ALLOCATED) { + IPAERR("EP not allocated for prod %d\n", prod); + return EINVAL; + } + + cons_ep_idx = ipa_get_ep_mapping(cons); + if (cons_ep_idx == IPA_EP_NOT_ALLOCATED) { + IPAERR("EP not allocated for cons %d\n", cons); + return EINVAL; + } + + /* reading stats will reset them in hardware */ + ret = ipa_get_teth_stats(); + if (ret) { + IPAERR("ipa_get_teth_stats failed %d\n", ret); + return ret; + } + + /* reset driver's cache */ + stats = &ipa3_ctx->hw_stats->teth.prod_stats_sum[prod_ep_idx].client[cons_ep_idx]; + memset(stats, 0, sizeof(*stats)); + return 0; +} + +int ipa_reset_all_cons_teth_stats(enum ipa_client_type prod) +{ + int ret; + int i; + struct ipa_quota_stats *stats; + int ipa_ep_idx; + + if (!(ipa3_ctx->hw_stats && ipa3_ctx->hw_stats->enabled && + ipa3_ctx->hw_stats->teth_stats_enabled)) + return 0; + + if (!IPA_CLIENT_IS_PROD(prod)) { + IPAERR("invalid prod %d\n", prod); + return -EINVAL; + } + + ipa_ep_idx = ipa_get_ep_mapping(prod); + if (ipa_ep_idx == IPA_EP_NOT_ALLOCATED) { + IPAERR("EP not allocated for prod %d\n", prod); + return EINVAL; + } + + /* reading stats will reset them in hardware */ + ret = ipa_get_teth_stats(); + if (ret) { + IPAERR("ipa_get_teth_stats failed %d\n", ret); + return ret; + } + + /* reset driver's cache */ + for (i = 0; i < IPA5_PIPES_NUM; i++) { + stats = &ipa3_ctx->hw_stats->teth.prod_stats_sum[ipa_ep_idx].client[i]; + memset(stats, 0, sizeof(*stats)); + } + + return 0; +} + +int ipa_reset_all_teth_stats(void) +{ + int i; + int ret; + struct ipa_quota_stats_all *stats; + + if (!(ipa3_ctx->hw_stats && ipa3_ctx->hw_stats->enabled && + ipa3_ctx->hw_stats->teth_stats_enabled)) + return 0; + + /* reading stats will reset them in hardware */ + for (i = 0; i < IPA_CLIENT_MAX; i++) { + if (IPA_CLIENT_IS_PROD(i) && ipa_get_ep_mapping(i) != -1) { + ret = ipa_get_teth_stats(); + if (ret) { + IPAERR("ipa_get_teth_stats failed %d\n", ret); + return ret; + } + /* a single iteration will reset all hardware stats */ + break; + } + } + + /* reset driver's cache */ + for (i = 0; i < IPA5_PIPES_NUM; i++) { + stats = &ipa3_ctx->hw_stats->teth.prod_stats_sum[i]; + memset(stats, 0, sizeof(*stats)); + } + + return 0; +} + +int ipa_init_flt_rt_stats(void) +{ + struct ipahal_stats_init_pyld *pyld; + int smem_ofst, smem_size; + int stats_base_flt_v4, stats_base_flt_v6; + int stats_base_rt_v4, stats_base_rt_v6; + struct ipahal_imm_cmd_dma_shared_mem cmd = { 0 }; + struct ipahal_imm_cmd_pyld *cmd_pyld; + struct ipahal_imm_cmd_register_write flt_v4_base = {0}; + struct ipahal_imm_cmd_pyld *flt_v4_base_pyld; + struct ipahal_imm_cmd_register_write flt_v6_base = {0}; + struct ipahal_imm_cmd_pyld *flt_v6_base_pyld; + struct ipahal_imm_cmd_register_write rt_v4_base = {0}; + struct ipahal_imm_cmd_pyld *rt_v4_base_pyld; + struct ipahal_imm_cmd_register_write rt_v6_base = {0}; + struct ipahal_imm_cmd_pyld *rt_v6_base_pyld; + struct ipahal_imm_cmd_pyld *coal_cmd_pyld = NULL; + struct ipa3_desc desc[6] = { {0} }; + dma_addr_t dma_address; + int ret; + int num_cmd = 0; + + if (!(ipa3_ctx->hw_stats && ipa3_ctx->hw_stats->enabled)) + return 0; + + smem_ofst = IPA_MEM_PART(stats_fnr_ofst); + smem_size = IPA_MEM_PART(stats_fnr_size); + + pyld = ipahal_stats_generate_init_pyld(IPAHAL_HW_STATS_FNR, + (void *)(uintptr_t)(IPA_MAX_FLT_RT_CNT_INDEX), false); + if (!pyld) { + IPAERR("failed to generate pyld\n"); + return -EPERM; + } + + if (pyld->len > smem_size) { + IPAERR("SRAM partition too small: %d needed %d\n", + smem_size, pyld->len); + ret = -EPERM; + goto destroy_init_pyld; + } + + dma_address = dma_map_single(ipa3_ctx->pdev, + pyld->data, + pyld->len, + DMA_TO_DEVICE); + if (dma_mapping_error(ipa3_ctx->pdev, dma_address)) { + IPAERR("failed to DMA map\n"); + ret = -EPERM; + goto destroy_init_pyld; + } + + /* IC to close the coal frame before HPS Clear if coal is enabled */ + if (ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS) != + IPA_EP_NOT_ALLOCATED && !ipa3_ctx->ulso_wa) { + ipa_close_coal_frame(&coal_cmd_pyld); + if (!coal_cmd_pyld) { + IPAERR("failed to construct coal close IC\n"); + ret = -ENOMEM; + goto unmap; + } + ipa3_init_imm_cmd_desc(&desc[num_cmd], coal_cmd_pyld); + ++num_cmd; + } + + stats_base_flt_v4 = ipahal_get_reg_ofst(IPA_STAT_FILTER_IPV4_BASE); + stats_base_flt_v6 = ipahal_get_reg_ofst(IPA_STAT_FILTER_IPV6_BASE); + stats_base_rt_v4 = ipahal_get_reg_ofst(IPA_STAT_ROUTER_IPV4_BASE); + stats_base_rt_v6 = ipahal_get_reg_ofst(IPA_STAT_ROUTER_IPV6_BASE); + + /* setting the registers and init the stats pyld are done atomically */ + /* set IPA_STAT_FILTER_IPV4_BASE */ + flt_v4_base.skip_pipeline_clear = false; + flt_v4_base.pipeline_clear_options = IPAHAL_FULL_PIPELINE_CLEAR; + flt_v4_base.offset = stats_base_flt_v4; + flt_v4_base.value = ipa3_ctx->smem_restricted_bytes + + smem_ofst; + flt_v4_base.value_mask = ~0; + flt_v4_base_pyld = ipahal_construct_imm_cmd(IPA_IMM_CMD_REGISTER_WRITE, + &flt_v4_base, false); + if (!flt_v4_base_pyld) { + IPAERR("failed to construct register_write imm cmd\n"); + ret = -ENOMEM; + goto destroy_coal_cmd; + } + desc[num_cmd].opcode = flt_v4_base_pyld->opcode; + desc[num_cmd].pyld = flt_v4_base_pyld->data; + desc[num_cmd].len = flt_v4_base_pyld->len; + desc[num_cmd].type = IPA_IMM_CMD_DESC; + ++num_cmd; + + /* set IPA_STAT_FILTER_IPV6_BASE */ + flt_v6_base.skip_pipeline_clear = false; + flt_v6_base.pipeline_clear_options = IPAHAL_FULL_PIPELINE_CLEAR; + flt_v6_base.offset = stats_base_flt_v6; + flt_v6_base.value = ipa3_ctx->smem_restricted_bytes + + smem_ofst; + flt_v6_base.value_mask = ~0; + flt_v6_base_pyld = ipahal_construct_imm_cmd(IPA_IMM_CMD_REGISTER_WRITE, + &flt_v6_base, false); + if (!flt_v6_base_pyld) { + IPAERR("failed to construct register_write imm cmd\n"); + ret = -ENOMEM; + goto destroy_flt_v4_base; + } + desc[num_cmd].opcode = flt_v6_base_pyld->opcode; + desc[num_cmd].pyld = flt_v6_base_pyld->data; + desc[num_cmd].len = flt_v6_base_pyld->len; + desc[num_cmd].type = IPA_IMM_CMD_DESC; + ++num_cmd; + + /* set IPA_STAT_ROUTER_IPV4_BASE */ + rt_v4_base.skip_pipeline_clear = false; + rt_v4_base.pipeline_clear_options = IPAHAL_FULL_PIPELINE_CLEAR; + rt_v4_base.offset = stats_base_rt_v4; + rt_v4_base.value = ipa3_ctx->smem_restricted_bytes + + smem_ofst; + rt_v4_base.value_mask = ~0; + rt_v4_base_pyld = ipahal_construct_imm_cmd(IPA_IMM_CMD_REGISTER_WRITE, + &rt_v4_base, false); + if (!rt_v4_base_pyld) { + IPAERR("failed to construct register_write imm cmd\n"); + ret = -ENOMEM; + goto destroy_flt_v6_base; + } + desc[num_cmd].opcode = rt_v4_base_pyld->opcode; + desc[num_cmd].pyld = rt_v4_base_pyld->data; + desc[num_cmd].len = rt_v4_base_pyld->len; + desc[num_cmd].type = IPA_IMM_CMD_DESC; + ++num_cmd; + + /* set IPA_STAT_ROUTER_IPV6_BASE */ + rt_v6_base.skip_pipeline_clear = false; + rt_v6_base.pipeline_clear_options = IPAHAL_FULL_PIPELINE_CLEAR; + rt_v6_base.offset = stats_base_rt_v6; + rt_v6_base.value = ipa3_ctx->smem_restricted_bytes + + smem_ofst; + rt_v6_base.value_mask = ~0; + rt_v6_base_pyld = ipahal_construct_imm_cmd(IPA_IMM_CMD_REGISTER_WRITE, + &rt_v6_base, false); + if (!rt_v6_base_pyld) { + IPAERR("failed to construct register_write imm cmd\n"); + ret = -ENOMEM; + goto destroy_rt_v4_base; + } + desc[num_cmd].opcode = rt_v6_base_pyld->opcode; + desc[num_cmd].pyld = rt_v6_base_pyld->data; + desc[num_cmd].len = rt_v6_base_pyld->len; + desc[num_cmd].type = IPA_IMM_CMD_DESC; + ++num_cmd; + + cmd.is_read = false; + cmd.skip_pipeline_clear = false; + cmd.pipeline_clear_options = IPAHAL_FULL_PIPELINE_CLEAR; + cmd.size = pyld->len; + cmd.system_addr = dma_address; + cmd.local_addr = ipa3_ctx->smem_restricted_bytes + + smem_ofst; + cmd_pyld = ipahal_construct_imm_cmd( + IPA_IMM_CMD_DMA_SHARED_MEM, &cmd, false); + if (!cmd_pyld) { + IPAERR("failed to construct dma_shared_mem imm cmd\n"); + ret = -ENOMEM; + goto destroy_rt_v6_base; + } + desc[num_cmd].opcode = cmd_pyld->opcode; + desc[num_cmd].pyld = cmd_pyld->data; + desc[num_cmd].len = cmd_pyld->len; + desc[num_cmd].type = IPA_IMM_CMD_DESC; + ++num_cmd; + + ret = ipa3_send_cmd(num_cmd, desc); + if (ret) { + IPAERR("failed to send immediate command (error %d)\n", ret); + goto destroy_imm; + } + + ret = 0; + +destroy_imm: + ipahal_destroy_imm_cmd(cmd_pyld); +destroy_rt_v6_base: + ipahal_destroy_imm_cmd(rt_v6_base_pyld); +destroy_rt_v4_base: + ipahal_destroy_imm_cmd(rt_v4_base_pyld); +destroy_flt_v6_base: + ipahal_destroy_imm_cmd(flt_v6_base_pyld); +destroy_flt_v4_base: + ipahal_destroy_imm_cmd(flt_v4_base_pyld); +destroy_coal_cmd: + if (coal_cmd_pyld) + ipahal_destroy_imm_cmd(coal_cmd_pyld); +unmap: + dma_unmap_single(ipa3_ctx->pdev, dma_address, pyld->len, DMA_TO_DEVICE); +destroy_init_pyld: + ipahal_destroy_stats_init_pyld(pyld); + return ret; +} + +static int __ipa_get_flt_rt_stats(struct ipa_ioc_flt_rt_query *query) +{ + int ret; + int smem_ofst; + bool clear = query->reset; + struct ipahal_stats_get_offset_flt_rt_v4_5 *get_offset; + struct ipahal_stats_offset offset = { 0 }; + struct ipahal_imm_cmd_dma_shared_mem cmd = { 0 }; + struct ipahal_imm_cmd_pyld *cmd_pyld[2]; + struct ipa_mem_buffer mem; + struct ipa3_desc desc[2]; + int num_cmd = 0; + int i; + + memset(desc, 0, sizeof(desc)); + memset(cmd_pyld, 0, sizeof(cmd_pyld)); + + get_offset = kzalloc(sizeof(*get_offset), GFP_KERNEL); + if (!get_offset) { + IPADBG("no mem\n"); + return -ENOMEM; + } + + smem_ofst = IPA_MEM_PART(stats_fnr_ofst); + + get_offset->start_id = query->start_id; + get_offset->end_id = query->end_id; + + ret = ipahal_stats_get_offset(IPAHAL_HW_STATS_FNR, get_offset, + &offset); + if (ret) { + IPAERR("failed to get offset from hal %d\n", ret); + goto free_offset; + } + + IPADBG("offset = %d size = %d\n", offset.offset, offset.size); + + if (offset.size == 0) { + ret = 0; + goto free_offset; + } + + mem.size = offset.size; + mem.base = dma_alloc_coherent(ipa3_ctx->pdev, + mem.size, + &mem.phys_base, + GFP_KERNEL); + if (!mem.base) { + IPAERR("fail to alloc DMA memory\n"); + goto free_offset; + } + + /* IC to close the coal frame before HPS Clear if coal is enabled */ + if (ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS) != + IPA_EP_NOT_ALLOCATED && !ipa3_ctx->ulso_wa) { + ipa_close_coal_frame(&cmd_pyld[num_cmd]); + if (!cmd_pyld[num_cmd]) { + IPAERR("failed to construct coal close IC\n"); + ret = -ENOMEM; + goto free_dma_mem; + } + ipa3_init_imm_cmd_desc(&desc[num_cmd], cmd_pyld[num_cmd]); + ++num_cmd; + } + + cmd.is_read = true; + cmd.clear_after_read = clear; + cmd.skip_pipeline_clear = false; + cmd.pipeline_clear_options = IPAHAL_HPS_CLEAR; + cmd.size = mem.size; + cmd.system_addr = mem.phys_base; + cmd.local_addr = ipa3_ctx->smem_restricted_bytes + + smem_ofst + offset.offset; + cmd_pyld[num_cmd] = ipahal_construct_imm_cmd( + IPA_IMM_CMD_DMA_SHARED_MEM, &cmd, false); + if (!cmd_pyld[num_cmd]) { + IPAERR("failed to construct dma_shared_mem imm cmd\n"); + ret = -ENOMEM; + goto destroy_imm; + } + ipa3_init_imm_cmd_desc(&desc[num_cmd], cmd_pyld[num_cmd]); + ++num_cmd; + + ret = ipa3_send_cmd(num_cmd, desc); + if (ret) { + IPAERR("failed to send immediate command (error %d)\n", ret); + goto destroy_imm; + } + + ret = ipahal_parse_stats(IPAHAL_HW_STATS_FNR, + NULL, mem.base, query); + if (ret) { + IPAERR("failed to parse stats (error %d)\n", ret); + goto destroy_imm; + } + ret = 0; + +destroy_imm: + for (i = 0; i < num_cmd; i++) + ipahal_destroy_imm_cmd(cmd_pyld[i]); +free_dma_mem: + dma_free_coherent(ipa3_ctx->pdev, mem.size, mem.base, mem.phys_base); +free_offset: + kfree(get_offset); + return ret; +} + +int ipa_get_flt_rt_stats(struct ipa_ioc_flt_rt_query *query) +{ + if (!(ipa3_ctx->hw_stats && ipa3_ctx->hw_stats->enabled)) { + IPAERR("hw_stats is not enabled\n"); + return 0; + } + + if (ipa3_ctx->ipa_hw_type < IPA_HW_v4_5) { + IPAERR("FnR stats not supported in %d hw_type\n", + ipa3_ctx->ipa_hw_type); + return 0; + } + + if (query->start_id == 0 || query->end_id == 0) { + IPAERR("Invalid start_id/end_id, must be not 0\n"); + IPAERR("start_id %d, end_id %d\n", + query->start_id, query->end_id); + return -EINVAL; + } + + if (query->start_id > IPA_MAX_FLT_RT_CNT_INDEX) { + IPAERR("start_cnt_id %d out of range\n", query->start_id); + return -EINVAL; + } + + if (query->end_id > IPA_MAX_FLT_RT_CNT_INDEX) { + IPAERR("end_cnt_id %d out of range\n", query->end_id); + return -EINVAL; + } + + if (query->end_id < query->start_id) { + IPAERR("end_id %d < start_id %d\n", + query->end_id, query->start_id); + return -EINVAL; + } + + if (query->stats_size > sizeof(struct ipa_flt_rt_stats)) { + IPAERR("stats_size %d > ipa_flt_rt_stats %d\n", + query->stats_size, sizeof(struct ipa_flt_rt_stats)); + return -EINVAL; + } + + return __ipa_get_flt_rt_stats(query); +} + + +static int __ipa_set_flt_rt_stats(int index, struct ipa_flt_rt_stats stats) +{ + int ret; + int smem_ofst; + struct ipahal_stats_get_offset_flt_rt_v4_5 *get_offset; + struct ipahal_stats_offset offset = { 0 }; + struct ipahal_imm_cmd_dma_shared_mem cmd = { 0 }; + struct ipahal_imm_cmd_pyld *cmd_pyld; + struct ipa_mem_buffer mem; + struct ipa3_desc desc = { 0 }; + + get_offset = kzalloc(sizeof(*get_offset), GFP_KERNEL); + if (!get_offset) { + IPADBG("no mem\n"); + return -ENOMEM; + } + + smem_ofst = IPA_MEM_PART(stats_fnr_ofst); + + get_offset->start_id = index; + get_offset->end_id = index; + + ret = ipahal_stats_get_offset(IPAHAL_HW_STATS_FNR, get_offset, + &offset); + if (ret) { + IPAERR("failed to get offset from hal %d\n", ret); + goto free_offset; + } + + IPADBG("offset = %d size = %d\n", offset.offset, offset.size); + + if (offset.size == 0) { + ret = 0; + goto free_offset; + } + + mem.size = offset.size; + mem.base = dma_alloc_coherent(ipa3_ctx->pdev, + mem.size, + &mem.phys_base, + GFP_KERNEL); + if (!mem.base) { + IPAERR("fail to alloc DMA memory\n"); + goto free_offset; + } + ipahal_set_flt_rt_sw_stats(mem.base, stats); + + cmd.is_read = false; + cmd.skip_pipeline_clear = false; + cmd.pipeline_clear_options = IPAHAL_HPS_CLEAR; + cmd.size = mem.size; + cmd.system_addr = mem.phys_base; + cmd.local_addr = ipa3_ctx->smem_restricted_bytes + + smem_ofst + offset.offset; + cmd_pyld = ipahal_construct_imm_cmd( + IPA_IMM_CMD_DMA_SHARED_MEM, &cmd, false); + if (!cmd_pyld) { + IPAERR("failed to construct dma_shared_mem imm cmd\n"); + ret = -ENOMEM; + goto free_dma_mem; + } + desc.opcode = cmd_pyld->opcode; + desc.pyld = cmd_pyld->data; + desc.len = cmd_pyld->len; + desc.type = IPA_IMM_CMD_DESC; + + ret = ipa3_send_cmd(1, &desc); + if (ret) { + IPAERR("failed to send immediate command (error %d)\n", ret); + goto destroy_imm; + } + + ret = 0; + +destroy_imm: + ipahal_destroy_imm_cmd(cmd_pyld); +free_dma_mem: + dma_free_coherent(ipa3_ctx->pdev, mem.size, mem.base, mem.phys_base); +free_offset: + kfree(get_offset); + return ret; +} + +int ipa_set_flt_rt_stats(int index, struct ipa_flt_rt_stats stats) +{ + if (!(ipa3_ctx->hw_stats && ipa3_ctx->hw_stats->enabled)) { + IPAERR("hw_stats is not enabled\n"); + return 0; + } + + if (ipa3_ctx->ipa_hw_type < IPA_HW_v4_5) { + IPAERR("FnR stats not supported in %d hw_type\n", + ipa3_ctx->ipa_hw_type); + return 0; + } + + if (index > IPA_MAX_FLT_RT_CNT_INDEX) { + IPAERR("index %d out of range\n", index); + return -EINVAL; + } + + if (index <= IPA_FLT_RT_HW_COUNTER) { + IPAERR("index %d invalid, only support sw counter set\n", + index); + return -EINVAL; + } + + return __ipa_set_flt_rt_stats(index, stats); +} + +int ipa_drop_stats_init(void) +{ + u32 reg_idx; + u32 mask, pipe_bitmask[IPA_EP_ARR_SIZE] = {0}; + + mask = ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_USB_CONS, + ®_idx); + pipe_bitmask[reg_idx] |= mask; + + if (ipa3_ctx->ipa_wdi3_5g_holb_timeout || ipa3_ctx->uc_ctx.ipa_use_uc_holb_monitor) { + mask = ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_WLAN2_CONS, + ®_idx); + pipe_bitmask[reg_idx] |= mask; + } + + if (ipa3_ctx->platform_type == IPA_PLAT_TYPE_MDM) { + if (ipa3_ctx->ipa_wdi3_2g_holb_timeout) { + mask = ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_WLAN2_CONS1, + ®_idx); + pipe_bitmask[reg_idx] |= mask; + } + + if (ipa3_ctx->use_tput_est_ep) { + mask = ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_TPUT_CONS, + ®_idx); + pipe_bitmask[reg_idx] |= mask; + + } + } else { + /* ADPL pipe hw stats is now taken care by IPA Q6 */ + if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0) { + mask = ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_USB_DPL_CONS, + ®_idx); + pipe_bitmask[reg_idx] |= mask; + + mask = ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_ODL_DPL_CONS, + ®_idx); + pipe_bitmask[reg_idx] |= mask; + } + + /* Add drop stats for WAN if IPA_HW >=5.2 */ + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_2) { + mask = ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_APPS_WAN_CONS, + ®_idx); + pipe_bitmask[reg_idx] |= mask; + } + + /* Add drop stats for WAN_COAL as well if IPA_HW >=5.5 */ + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_5) { + mask = ipa_hw_stats_get_ep_bit_n_idx( + IPA_CLIENT_APPS_WAN_COAL_CONS, + ®_idx); + pipe_bitmask[reg_idx] |= mask; + } + } + + /* Currently we have option to enable drop stats using debugfs. + * To enable drop stats for a different pipe, first user needs + * to query drop stats to get the current stats and enable. + * TODO: to support dynamically caching drop stats. + */ + + return ipa_init_drop_stats(pipe_bitmask); +} + +int ipa_init_drop_stats(u32 *pipe_bitmask) +{ + struct ipahal_stats_init_pyld *pyld; + struct ipahal_imm_cmd_dma_shared_mem cmd = { 0 }; + struct ipahal_imm_cmd_pyld *cmd_pyld; + struct ipahal_imm_cmd_register_write drop_base = {0}; + struct ipahal_imm_cmd_pyld *drop_base_pyld; + struct ipahal_imm_cmd_register_write drop_mask = {0}; + struct ipahal_imm_cmd_pyld *drop_mask_pyld[IPAHAL_IPA5_PIPE_REG_NUM] = + {0}; + struct ipahal_imm_cmd_pyld *coal_cmd_pyld = NULL; + struct ipa3_desc *desc = NULL; + struct ipa_hw_stats_drop tmp_drop; + dma_addr_t dma_address; + int ret, i; + int num_cmd = 0; + + if (!(ipa3_ctx->hw_stats && ipa3_ctx->hw_stats->enabled)) + return 0; + + if (!pipe_bitmask) + return -EPERM; + + desc = kzalloc(sizeof(*desc) * IPA_INIT_DROP_STATS_MAX_CMD_NUM, GFP_KERNEL); + if (!desc) { + IPAERR("failed to allocate memory\n"); + return -ENOMEM; + } + + /* check if IPA has enough space for # of pipes drop stats enabled*/ + memset(&tmp_drop, 0, sizeof(tmp_drop)); + for (i = 0; i < IPA5_PIPE_REG_NUM; i++) { + tmp_drop.init.enabled_bitmask[i] = pipe_bitmask[i]; + IPADBG_LOW("pipe_bitmask[%d]=0x%x\n", i, pipe_bitmask[i]); + } + + pyld = ipahal_stats_generate_init_pyld(IPAHAL_HW_STATS_DROP, + &tmp_drop.init, false); + if (!pyld) { + IPAERR("failed to generate pyld\n"); + ret = -EPERM; + goto fail_free_desc; + } + + if (pyld->len > IPA_MEM_PART(stats_drop_size)) { + IPAERR("SRAM partition too small: %d bytes (%d pipes)." + "Tried to add %d bytes (%d pipes)." + "Please disable some stats before adding new ones.\n", + IPA_MEM_PART(stats_drop_size), IPA_MEM_PART(stats_drop_size)/8, + pyld->len, pyld->len/8); + ret = -EPERM; + goto destroy_init_pyld; + } + + /* reset driver's cache and copy the bitmask of new drop enabled pipes */ + memset(&ipa3_ctx->hw_stats->drop, 0, sizeof(ipa3_ctx->hw_stats->drop)); + ipa3_ctx->hw_stats->drop = tmp_drop; + + dma_address = dma_map_single(ipa3_ctx->pdev, + pyld->data, + pyld->len, + DMA_TO_DEVICE); + if (dma_mapping_error(ipa3_ctx->pdev, dma_address)) { + IPAERR("failed to DMA map\n"); + ret = -EPERM; + goto destroy_init_pyld; + } + + /* IC to close the coal frame before HPS Clear if coal is enabled */ + if (ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS) != + IPA_EP_NOT_ALLOCATED && !ipa3_ctx->ulso_wa) { + ipa_close_coal_frame(&coal_cmd_pyld); + if (!coal_cmd_pyld) { + IPAERR("failed to construct coal close IC\n"); + ret = -ENOMEM; + goto unmap; + } + ipa3_init_imm_cmd_desc(&desc[num_cmd], coal_cmd_pyld); + ++num_cmd; + } + + /* setting the registers and init the stats pyld are done atomically */ + drop_mask.skip_pipeline_clear = false; + drop_mask.pipeline_clear_options = IPAHAL_FULL_PIPELINE_CLEAR; + drop_mask.value_mask = ~0; + if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0) { + drop_mask.offset = ipahal_get_reg_n_ofst( + IPA_STAT_DROP_CNT_MASK_n, + ipa3_ctx->ee); + drop_mask.value = pipe_bitmask[0]; + drop_mask_pyld[0] = ipahal_construct_imm_cmd( + IPA_IMM_CMD_REGISTER_WRITE, + &drop_mask, false); + if (!drop_mask_pyld[0]) { + IPAERR("failed to construct register_write imm cmd\n"); + ret = -ENOMEM; + goto destroy_coal_cmd; + } + desc[num_cmd].opcode = drop_mask_pyld[0]->opcode; + desc[num_cmd].pyld = drop_mask_pyld[0]->data; + desc[num_cmd].len = drop_mask_pyld[0]->len; + desc[num_cmd].type = IPA_IMM_CMD_DESC; + ++num_cmd; + } else { + for (i = 0; i < IPA5_PIPE_REG_NUM; i++) { + drop_mask.offset = ipahal_get_reg_nk_offset( + IPA_STAT_DROP_CNT_MASK_EE_n_REG_k, + ipa3_ctx->ee, i); + drop_mask.value = pipe_bitmask[i]; + drop_mask_pyld[i] = ipahal_construct_imm_cmd( + IPA_IMM_CMD_REGISTER_WRITE, + &drop_mask, false); + if (!drop_mask_pyld[i]) { + int j; + + IPAERR( + "failed to construct register_write imm cmd\n" + ); + for (j = i - 1; j >= 0; j--) + ipahal_destroy_imm_cmd( + drop_mask_pyld[j]); + ret = -ENOMEM; + goto destroy_coal_cmd; + } + desc[num_cmd].opcode = drop_mask_pyld[i]->opcode; + desc[num_cmd].pyld = drop_mask_pyld[i]->data; + desc[num_cmd].len = drop_mask_pyld[i]->len; + desc[num_cmd].type = IPA_IMM_CMD_DESC; + ++num_cmd; + } + } + + drop_base.skip_pipeline_clear = false; + drop_base.pipeline_clear_options = IPAHAL_FULL_PIPELINE_CLEAR; + drop_base.offset = ipahal_get_reg_n_ofst(IPA_STAT_DROP_CNT_BASE_n, + ipa3_ctx->ee); + drop_base.value = ipa3_ctx->smem_restricted_bytes + + IPA_MEM_PART(stats_drop_ofst); + drop_base.value_mask = ~0; + drop_base_pyld = ipahal_construct_imm_cmd(IPA_IMM_CMD_REGISTER_WRITE, + &drop_base, false); + if (!drop_base_pyld) { + IPAERR("failed to construct register_write imm cmd\n"); + ret = -ENOMEM; + goto destroy_drop_mask; + } + desc[num_cmd].opcode = drop_base_pyld->opcode; + desc[num_cmd].pyld = drop_base_pyld->data; + desc[num_cmd].len = drop_base_pyld->len; + desc[num_cmd].type = IPA_IMM_CMD_DESC; + ++num_cmd; + + cmd.is_read = false; + cmd.skip_pipeline_clear = false; + cmd.pipeline_clear_options = IPAHAL_FULL_PIPELINE_CLEAR; + cmd.size = pyld->len; + cmd.system_addr = dma_address; + cmd.local_addr = ipa3_ctx->smem_restricted_bytes + + IPA_MEM_PART(stats_drop_ofst); + cmd_pyld = ipahal_construct_imm_cmd( + IPA_IMM_CMD_DMA_SHARED_MEM, &cmd, false); + if (!cmd_pyld) { + IPAERR("failed to construct dma_shared_mem imm cmd\n"); + ret = -ENOMEM; + goto destroy_drop_base; + } + desc[num_cmd].opcode = cmd_pyld->opcode; + desc[num_cmd].pyld = cmd_pyld->data; + desc[num_cmd].len = cmd_pyld->len; + desc[num_cmd].type = IPA_IMM_CMD_DESC; + ++num_cmd; + + ret = ipa3_send_cmd(num_cmd, desc); + if (ret) { + IPAERR("failed to send immediate command (error %d)\n", ret); + goto destroy_imm; + } + + ret = 0; + +destroy_imm: + ipahal_destroy_imm_cmd(cmd_pyld); +destroy_drop_base: + ipahal_destroy_imm_cmd(drop_base_pyld); +destroy_drop_mask: + for (i = 0; i < IPA5_PIPE_REG_NUM; i++) + if (drop_mask_pyld[i]) + ipahal_destroy_imm_cmd(drop_mask_pyld[i]); +destroy_coal_cmd: + if (coal_cmd_pyld) + ipahal_destroy_imm_cmd(coal_cmd_pyld); +unmap: + dma_unmap_single(ipa3_ctx->pdev, dma_address, pyld->len, DMA_TO_DEVICE); +destroy_init_pyld: + ipahal_destroy_stats_init_pyld(pyld); +fail_free_desc: + kfree(desc); + return ret; +} + +int ipa_get_drop_stats(struct ipa_drop_stats_all *out) +{ + int i; + int ret; + struct ipahal_stats_get_offset_drop get_offset = { { 0 } }; + struct ipahal_stats_offset offset = { 0 }; + struct ipahal_imm_cmd_dma_shared_mem cmd = { 0 }; + struct ipahal_imm_cmd_pyld *cmd_pyld[2]; + struct ipa_mem_buffer mem; + struct ipa3_desc desc[2]; + struct ipahal_stats_drop_all *stats; + int num_cmd = 0; + + if (!(ipa3_ctx->hw_stats && ipa3_ctx->hw_stats->enabled)) + return 0; + + memset(desc, 0, sizeof(desc)); + memset(cmd_pyld, 0, sizeof(cmd_pyld)); + + get_offset.init = ipa3_ctx->hw_stats->drop.init; + ret = ipahal_stats_get_offset(IPAHAL_HW_STATS_DROP, &get_offset, + &offset); + if (ret) { + IPAERR("failed to get offset from hal %d\n", ret); + return ret; + } + + IPADBG_LOW("offset = %d size = %d\n", offset.offset, offset.size); + + if (offset.size == 0) + return 0; + + mem.size = offset.size; + mem.base = dma_alloc_coherent(ipa3_ctx->pdev, + mem.size, + &mem.phys_base, + GFP_KERNEL); + if (!mem.base) { + IPAERR("fail to alloc DMA memory\n"); + return ret; + } + + /* IC to close the coal frame before HPS Clear if coal is enabled */ + if (ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS) != + IPA_EP_NOT_ALLOCATED && !ipa3_ctx->ulso_wa) { + ipa_close_coal_frame(&cmd_pyld[num_cmd]); + if (!cmd_pyld[num_cmd]) { + IPAERR("failed to construct coal close IC\n"); + ret = -ENOMEM; + goto free_dma_mem; + } + ipa3_init_imm_cmd_desc(&desc[num_cmd], cmd_pyld[num_cmd]); + ++num_cmd; + } + + cmd.is_read = true; + cmd.clear_after_read = true; + cmd.skip_pipeline_clear = false; + cmd.pipeline_clear_options = IPAHAL_HPS_CLEAR; + cmd.size = mem.size; + cmd.system_addr = mem.phys_base; + cmd.local_addr = ipa3_ctx->smem_restricted_bytes + + IPA_MEM_PART(stats_drop_ofst) + offset.offset; + cmd_pyld[num_cmd] = ipahal_construct_imm_cmd( + IPA_IMM_CMD_DMA_SHARED_MEM, &cmd, false); + if (!cmd_pyld[num_cmd]) { + IPAERR("failed to construct dma_shared_mem imm cmd\n"); + ret = -ENOMEM; + goto destroy_imm; + } + ipa3_init_imm_cmd_desc(&desc[num_cmd], cmd_pyld[num_cmd]); + ++num_cmd; + + ret = ipa3_send_cmd(num_cmd, desc); + if (ret) { + IPAERR("failed to send immediate command (error %d)\n", ret); + goto destroy_imm; + } + + stats = kzalloc(sizeof(*stats), GFP_KERNEL); + if (!stats) { + ret = -ENOMEM; + goto destroy_imm; + } + + ret = ipahal_parse_stats(IPAHAL_HW_STATS_DROP, + &ipa3_ctx->hw_stats->drop.init, mem.base, stats); + if (ret) { + IPAERR("failed to parse stats (error %d)\n", ret); + goto free_stats; + } + + /* + * update driver cache. + * the stats were read from hardware with clear_after_read meaning + * hardware stats are 0 now + */ + for (i = 0; i < IPA_CLIENT_MAX; i++) { + int ep_idx = ipa_get_ep_mapping(i); + + if (ep_idx == -1 || ep_idx >= ipa3_get_max_num_pipes()) + continue; + + if (ipa3_ctx->ep[ep_idx].client != i) + continue; + + ipa3_ctx->hw_stats->drop.stats.client[i].drop_byte_cnt += + stats->stats[ep_idx].drop_byte_cnt; + ipa3_ctx->hw_stats->drop.stats.client[i].drop_packet_cnt += + stats->stats[ep_idx].drop_packet_cnt; + } + + + if (!out) { + ret = 0; + goto free_stats; + } + + /* copy results to out parameter */ + *out = ipa3_ctx->hw_stats->drop.stats; + + ret = 0; +free_stats: + kfree(stats); +destroy_imm: + for (i = 0; i < num_cmd; i++) + ipahal_destroy_imm_cmd(cmd_pyld[i]); +free_dma_mem: + dma_free_coherent(ipa3_ctx->pdev, mem.size, mem.base, mem.phys_base); + return ret; + +} + +int ipa_reset_drop_stats(enum ipa_client_type client) +{ + int ret; + struct ipa_drop_stats *stats; + + if (!(ipa3_ctx->hw_stats && ipa3_ctx->hw_stats->enabled)) + return 0; + + if (client >= IPA_CLIENT_MAX) { + IPAERR("invalid client %d\n", client); + return -EINVAL; + } + + /* reading stats will reset them in hardware */ + ret = ipa_get_drop_stats(NULL); + if (ret) { + IPAERR("ipa_get_drop_stats failed %d\n", ret); + return ret; + } + + /* reset driver's cache */ + stats = &ipa3_ctx->hw_stats->drop.stats.client[client]; + memset(stats, 0, sizeof(*stats)); + return 0; +} + +int ipa_reset_all_drop_stats(void) +{ + int ret; + struct ipa_drop_stats_all *stats; + + if (!(ipa3_ctx->hw_stats && ipa3_ctx->hw_stats->enabled)) + return 0; + + /* reading stats will reset them in hardware */ + ret = ipa_get_drop_stats(NULL); + if (ret) { + IPAERR("ipa_get_drop_stats failed %d\n", ret); + return ret; + } + + /* reset driver's cache */ + stats = &ipa3_ctx->hw_stats->drop.stats; + memset(stats, 0, sizeof(*stats)); + return 0; +} + + +#ifndef CONFIG_DEBUG_FS +int ipa_debugfs_init_stats(struct dentry *parent) { return 0; } +#else +#define IPA_MAX_MSG_LEN 4096 +static char dbg_buff[IPA_MAX_MSG_LEN]; + +static ssize_t ipa_debugfs_reset_quota_stats(struct file *file, + const char __user *ubuf, size_t count, loff_t *ppos) +{ + s8 client = 0; + int ret; + + mutex_lock(&ipa3_ctx->lock); + + ret = kstrtos8_from_user(ubuf, count, 0, &client); + if (ret) + goto bail; + + if (client == -1) + ipa_reset_all_quota_stats(); + else + ipa_reset_quota_stats(client); + + ret = count; +bail: + mutex_unlock(&ipa3_ctx->lock); + return ret; +} + +static ssize_t ipa_debugfs_print_quota_stats(struct file *file, + char __user *ubuf, size_t count, loff_t *ppos) +{ + int nbytes = 0; + struct ipa_quota_stats_all *out; + int i, reg_idx; + int res; + + out = kzalloc(sizeof(*out), GFP_KERNEL); + if (!out) + return -ENOMEM; + + if (!(ipa3_ctx->hw_stats && ipa3_ctx->hw_stats->enabled)) + return 0; + + mutex_lock(&ipa3_ctx->lock); + res = ipa_get_quota_stats(out); + if (res) { + mutex_unlock(&ipa3_ctx->lock); + kfree(out); + return res; + } + for (i = 0; i < IPA_CLIENT_MAX; i++) { + int ep_idx = ipa_get_ep_mapping(i); + + if (ep_idx == -1) + continue; + + if (IPA_CLIENT_IS_TEST(i)) + continue; + + reg_idx = ipahal_get_ep_reg_idx(ep_idx); + if (!(ipa3_ctx->hw_stats->quota.init.enabled_bitmask[reg_idx] & + ipahal_get_ep_bit(ep_idx))) + continue; + + nbytes += scnprintf(dbg_buff + nbytes, + IPA_MAX_MSG_LEN - nbytes, + "%s:\n", + ipa_clients_strings[i]); + nbytes += scnprintf(dbg_buff + nbytes, + IPA_MAX_MSG_LEN - nbytes, + "num_ipv4_bytes=%llu\n", + out->client[ep_idx].num_ipv4_bytes); + nbytes += scnprintf(dbg_buff + nbytes, + IPA_MAX_MSG_LEN - nbytes, + "num_ipv6_bytes=%llu\n", + out->client[ep_idx].num_ipv6_bytes); + nbytes += scnprintf(dbg_buff + nbytes, + IPA_MAX_MSG_LEN - nbytes, + "num_ipv4_pkts=%u\n", + out->client[ep_idx].num_ipv4_pkts); + nbytes += scnprintf(dbg_buff + nbytes, + IPA_MAX_MSG_LEN - nbytes, + "num_ipv6_pkts=%u\n", + out->client[ep_idx].num_ipv6_pkts); + nbytes += scnprintf(dbg_buff + nbytes, + IPA_MAX_MSG_LEN - nbytes, + "\n"); + + } + mutex_unlock(&ipa3_ctx->lock); + kfree(out); + + return simple_read_from_buffer(ubuf, count, ppos, dbg_buff, nbytes); +} + +static ssize_t ipa_debugfs_reset_tethering_stats(struct file *file, + const char __user *ubuf, size_t count, loff_t *ppos) +{ + s8 client = 0; + int ret; + + mutex_lock(&ipa3_ctx->lock); + + ret = kstrtos8_from_user(ubuf, count, 0, &client); + if (ret) + goto bail; + + if (client == -1) + ipa_reset_all_teth_stats(); + else + ipa_reset_all_cons_teth_stats(client); + + ret = count; +bail: + mutex_unlock(&ipa3_ctx->lock); + return ret; +} + +static ssize_t ipa_debugfs_print_tethering_stats(struct file *file, + char __user *ubuf, size_t count, loff_t *ppos) +{ + int nbytes = 0; + struct ipa_quota_stats_all *out; + int i, j, prod_reg, cons_reg; + int res; + + out = kzalloc(sizeof(*out), GFP_KERNEL); + if (!out) + return -ENOMEM; + + if (!(ipa3_ctx->hw_stats && ipa3_ctx->hw_stats->enabled && + ipa3_ctx->hw_stats->teth_stats_enabled)) + return 0; + + mutex_lock(&ipa3_ctx->lock); + + res = ipa_get_teth_stats(); + if (res) { + mutex_unlock(&ipa3_ctx->lock); + kfree(out); + return res; + } + + for (i = 0; i < IPA_CLIENT_MAX; i++) { + int ep_idx = ipa_get_ep_mapping(i); + + if (ep_idx == -1) + continue; + + if (!IPA_CLIENT_IS_PROD(i)) + continue; + + if (IPA_CLIENT_IS_TEST(i)) + continue; + + prod_reg = ipahal_get_ep_reg_idx(ep_idx); + if (!(ipa3_ctx->hw_stats->teth.init.prod_bitmask[prod_reg] & + ipahal_get_ep_bit(ep_idx))) + continue; + + res = ipa_query_teth_stats(i, out, false); + if (res) { + mutex_unlock(&ipa3_ctx->lock); + kfree(out); + return res; + } + + for (j = 0; j < IPA_CLIENT_MAX; j++) { + int cons_idx = ipa_get_ep_mapping(j); + + if (cons_idx == -1) + continue; + + if (IPA_CLIENT_IS_TEST(j)) + continue; + + cons_reg = ipahal_get_ep_reg_idx(cons_idx); + if (!(ipa3_ctx->hw_stats->teth.init. + cons_bitmask[ep_idx][cons_reg] + & ipahal_get_ep_bit(cons_idx))) + continue; + + nbytes += scnprintf(dbg_buff + nbytes, + IPA_MAX_MSG_LEN - nbytes, + "%s->%s:\n", + ipa_clients_strings[i], + ipa_clients_strings[j]); + nbytes += scnprintf(dbg_buff + nbytes, + IPA_MAX_MSG_LEN - nbytes, + "num_ipv4_bytes=%llu\n", + out->client[cons_idx].num_ipv4_bytes); + nbytes += scnprintf(dbg_buff + nbytes, + IPA_MAX_MSG_LEN - nbytes, + "num_ipv6_bytes=%llu\n", + out->client[cons_idx].num_ipv6_bytes); + nbytes += scnprintf(dbg_buff + nbytes, + IPA_MAX_MSG_LEN - nbytes, + "num_ipv4_pkts=%u\n", + out->client[cons_idx].num_ipv4_pkts); + nbytes += scnprintf(dbg_buff + nbytes, + IPA_MAX_MSG_LEN - nbytes, + "num_ipv6_pkts=%u\n", + out->client[cons_idx].num_ipv6_pkts); + nbytes += scnprintf(dbg_buff + nbytes, + IPA_MAX_MSG_LEN - nbytes, + "\n"); + } + } + mutex_unlock(&ipa3_ctx->lock); + kfree(out); + + return simple_read_from_buffer(ubuf, count, ppos, dbg_buff, nbytes); +} + +static ssize_t ipa_debugfs_control_flt_rt_stats(struct file *file, + const char __user *ubuf, size_t count, loff_t *ppos) +{ + struct ipa_ioc_flt_rt_query *query; + unsigned long missing; + int pyld_size = 0; + int ret; + + query = kzalloc(sizeof(struct ipa_ioc_flt_rt_query), + GFP_KERNEL); + if (!query) + return -ENOMEM; + query->stats_size = sizeof(struct ipa_flt_rt_stats); + pyld_size = IPA_MAX_FLT_RT_CNT_INDEX * + sizeof(struct ipa_flt_rt_stats); + query->stats = (uint64_t)kzalloc(pyld_size, GFP_KERNEL); + if (!query->stats) { + kfree(query); + return -ENOMEM; + } + + mutex_lock(&ipa3_ctx->lock); + if (count >= sizeof(dbg_buff)) { + ret = -EFAULT; + goto bail; + } + + missing = copy_from_user(dbg_buff, ubuf, count); + if (missing) { + ret = -EFAULT; + goto bail; + } + + dbg_buff[count] = '\0'; + if (strcmp(dbg_buff, "reset\n") == 0) { + query->reset = 1; + query->start_id = 1; + query->end_id = IPA_MAX_FLT_RT_CNT_INDEX; + ipa_get_flt_rt_stats(query); + } else { + IPAERR("unsupport flt_rt command\n"); + } + + ret = count; +bail: + kfree((void *)(uintptr_t)(query->stats)); + kfree(query); + mutex_unlock(&ipa3_ctx->lock); + return ret; +} + +static ssize_t ipa_debugfs_print_flt_rt_stats(struct file *file, + char __user *ubuf, size_t count, loff_t *ppos) +{ + int nbytes = 0; + int i; + int res; + int pyld_size = 0; + struct ipa_ioc_flt_rt_query *query; + + query = kzalloc(sizeof(struct ipa_ioc_flt_rt_query), + GFP_KERNEL); + if (!query) + return -ENOMEM; + query->start_id = 1; + query->end_id = IPA_MAX_FLT_RT_CNT_INDEX; + query->reset = false; + query->stats_size = sizeof(struct ipa_flt_rt_stats); + pyld_size = IPA_MAX_FLT_RT_CNT_INDEX * + sizeof(struct ipa_flt_rt_stats); + query->stats = (uint64_t)kzalloc(pyld_size, GFP_KERNEL); + if (!query->stats) { + kfree(query); + return -ENOMEM; + } + mutex_lock(&ipa3_ctx->lock); + res = ipa_get_flt_rt_stats(query); + if (res) { + mutex_unlock(&ipa3_ctx->lock); + kfree((void *)(uintptr_t)(query->stats)); + kfree(query); + return res; + } + for (i = 0; i < IPA_MAX_FLT_RT_CNT_INDEX; i++) { + nbytes += scnprintf(dbg_buff + nbytes, + IPA_MAX_MSG_LEN - nbytes, + "cnt_id: %d\n", i + 1); + nbytes += scnprintf(dbg_buff + nbytes, + IPA_MAX_MSG_LEN - nbytes, + "num_pkts: %d\n", + ((struct ipa_flt_rt_stats *) + query->stats)[i].num_pkts); + nbytes += scnprintf(dbg_buff + nbytes, + IPA_MAX_MSG_LEN - nbytes, + "num_pkts_hash: %d\n", + ((struct ipa_flt_rt_stats *) + query->stats)[i].num_pkts_hash); + nbytes += scnprintf(dbg_buff + nbytes, + IPA_MAX_MSG_LEN - nbytes, + "num_bytes: %lld\n", + ((struct ipa_flt_rt_stats *) + query->stats)[i].num_bytes); + nbytes += scnprintf(dbg_buff + nbytes, + IPA_MAX_MSG_LEN - nbytes, + "\n"); + } + mutex_unlock(&ipa3_ctx->lock); + kfree((void *)(uintptr_t)(query->stats)); + kfree(query); + return simple_read_from_buffer(ubuf, count, ppos, dbg_buff, nbytes); +} + +static ssize_t ipa_debugfs_reset_drop_stats(struct file *file, + const char __user *ubuf, size_t count, loff_t *ppos) +{ + s8 client = 0; + int ret; + + mutex_lock(&ipa3_ctx->lock); + + ret = kstrtos8_from_user(ubuf, count, 0, &client); + if (ret) + goto bail; + + if (client == -1) + ipa_reset_all_drop_stats(); + else + ipa_reset_drop_stats(client); + + ret = count; +bail: + mutex_unlock(&ipa3_ctx->lock); + return count; +} + +static ssize_t ipa_debugfs_print_drop_stats(struct file *file, + char __user *ubuf, size_t count, loff_t *ppos) +{ + int nbytes = 0; + struct ipa_drop_stats_all *out; + int i, reg_idx; + int res; + + out = kzalloc(sizeof(*out), GFP_KERNEL); + if (!out) + return -ENOMEM; + + if (!(ipa3_ctx->hw_stats && ipa3_ctx->hw_stats->enabled)) + return 0; + + mutex_lock(&ipa3_ctx->lock); + res = ipa_get_drop_stats(out); + if (res) { + mutex_unlock(&ipa3_ctx->lock); + kfree(out); + return res; + } + + for (i = 0; i < IPA_CLIENT_MAX; i++) { + int ep_idx = ipa_get_ep_mapping(i); + + if (ep_idx == -1) + continue; + + if (!IPA_CLIENT_IS_CONS(i)) + continue; + + if (IPA_CLIENT_IS_TEST(i)) + continue; + + reg_idx = ipahal_get_ep_reg_idx(ep_idx); + if (!(ipa3_ctx->hw_stats->drop.init.enabled_bitmask[reg_idx] & + ipahal_get_ep_bit(ep_idx))) + continue; + + /* Use more descriptive names for WLAN2_CONS pipes */ + if(i == IPA_CLIENT_WLAN2_CONS) { + nbytes += scnprintf(dbg_buff + nbytes, + IPA_MAX_MSG_LEN - nbytes, + "IPA_CLIENT_WLAN2_HIGHSPEED_CONS:\n"); + } else if(i == IPA_CLIENT_WLAN2_CONS1) { + nbytes += scnprintf(dbg_buff + nbytes, + IPA_MAX_MSG_LEN - nbytes, + " IPA_CLIENT_WLAN2_LOWSPEED_CONS:\n"); + } else { + nbytes += scnprintf(dbg_buff + nbytes, + IPA_MAX_MSG_LEN - nbytes, + "%s:\n", + ipa_clients_strings[i]); + } + + nbytes += scnprintf(dbg_buff + nbytes, + IPA_MAX_MSG_LEN - nbytes, + "drop_byte_cnt=%u\n", + out->client[i].drop_byte_cnt); + + nbytes += scnprintf(dbg_buff + nbytes, + IPA_MAX_MSG_LEN - nbytes, + "drop_packet_cnt=%u\n", + out->client[i].drop_packet_cnt); + nbytes += scnprintf(dbg_buff + nbytes, + IPA_MAX_MSG_LEN - nbytes, + "\n"); + } + mutex_unlock(&ipa3_ctx->lock); + kfree(out); + + return simple_read_from_buffer(ubuf, count, ppos, dbg_buff, nbytes); +} + +static ssize_t ipa_debugfs_enable_disable_drop_stats(struct file *file, + const char __user *ubuf, size_t count, loff_t *ppos) +{ + unsigned long missing; + unsigned int pipe_num = 0; + bool enable_pipe = true; + u32 pipe_bitmask[IPAHAL_IPA5_PIPE_REG_NUM] = {0}; + u32 pipe_ep_reg_idx = 0; + u32 pipe_ep_reg_bit = 0; + char seprator = ','; + int i, j; + bool is_pipe = false; + ssize_t ret; + int pipe_num_temp; + + if (ipa3_ctx->hw_stats && ipa3_ctx->hw_stats->enabled) { + for (i = 0; i < IPAHAL_IPA5_PIPE_REG_NUM; i++) { + pipe_bitmask[i] = + ipa3_ctx->hw_stats->drop.init.enabled_bitmask[i]; + } + } + + mutex_lock(&ipa3_ctx->lock); + if (count >= sizeof(dbg_buff)) { + ret = -EFAULT; + goto bail; + } + + missing = copy_from_user(dbg_buff, ubuf, count); + if (missing) { + ret = -EFAULT; + goto bail; + } + dbg_buff[count] = '\0'; + IPADBG("data is %s", dbg_buff); + + i = 0; + while (dbg_buff[i] != ' ' && i < count) + i++; + j = i; + i++; + if (i < count) { + if (dbg_buff[i] == '0') { + enable_pipe = false; + IPADBG("Drop stats will be disabled for pipes:"); + } + } + + for (i = 0; i < j; i++) { + if (dbg_buff[i] >= '0' && dbg_buff[i] <= '9') { + pipe_num = (pipe_num * 10) + (dbg_buff[i] - '0'); + pipe_ep_reg_idx = ipahal_get_ep_reg_idx(pipe_num); + pipe_ep_reg_bit = ipahal_get_ep_bit(pipe_num); + is_pipe = true; + } + pipe_num_temp = ipa3_get_client_by_pipe(pipe_num); + if (dbg_buff[i] == seprator) { + /* Removing ADPL and ODL stats as Q6 supports it from IPA_5_0 */ + if ((pipe_num_temp == IPA_CLIENT_USB_DPL_CONS || + pipe_num_temp == IPA_CLIENT_ODL_DPL_CONS) && + ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0) { + pipe_num = 0; + is_pipe = false; + continue; + } + + else if (pipe_num >= 0 && pipe_num < ipa3_ctx->ipa_num_pipes + && pipe_num_temp < IPA_CLIENT_MAX) { + IPADBG("pipe number %u\n", pipe_num); + if (enable_pipe) + pipe_bitmask[pipe_ep_reg_idx] |= + pipe_ep_reg_bit; + else + pipe_bitmask[pipe_ep_reg_idx] &= + ~pipe_ep_reg_bit; + } + pipe_num = 0; + is_pipe = false; + } + } + pipe_num_temp = ipa3_get_client_by_pipe(pipe_num); + /* Removing ADPL and ODL stats as Q6 supports it from IPA_5_0 */ + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0 && + (pipe_num_temp == IPA_CLIENT_USB_DPL_CONS || + pipe_num_temp == IPA_CLIENT_ODL_DPL_CONS)) { + IPAERR("Enable/Disable hw stats on DPL is not supported"); + } else if (is_pipe && pipe_num >= 0 && pipe_num < ipa3_ctx->ipa_num_pipes && + ipa3_get_client_by_pipe(pipe_num) < IPA_CLIENT_MAX) { + IPADBG("pipe number %u\n", pipe_num); + if (enable_pipe) + pipe_bitmask[pipe_ep_reg_idx] |= pipe_ep_reg_bit; + else + pipe_bitmask[pipe_ep_reg_idx] &= ~pipe_ep_reg_bit; + } + + ipa_init_drop_stats(pipe_bitmask); + ret = count; +bail: + mutex_unlock(&ipa3_ctx->lock); + return ret; +} + +static const struct file_operations ipa3_quota_ops = { + .read = ipa_debugfs_print_quota_stats, + .write = ipa_debugfs_reset_quota_stats, +}; + +static const struct file_operations ipa3_tethering_ops = { + .read = ipa_debugfs_print_tethering_stats, + .write = ipa_debugfs_reset_tethering_stats, +}; + +static const struct file_operations ipa3_flt_rt_ops = { + .read = ipa_debugfs_print_flt_rt_stats, + .write = ipa_debugfs_control_flt_rt_stats, +}; + +static const struct file_operations ipa3_drop_ops = { + .read = ipa_debugfs_print_drop_stats, + .write = ipa_debugfs_reset_drop_stats, +}; + +static const struct file_operations ipa3_enable_drop_ops = { + .write = ipa_debugfs_enable_disable_drop_stats, +}; + +int ipa_debugfs_init_stats(struct dentry *parent) +{ + const mode_t read_write_mode = 0664; + const mode_t write_mode = 0220; + struct dentry *file; + struct dentry *dent; + + if (!(ipa3_ctx->hw_stats && ipa3_ctx->hw_stats->enabled)) + return 0; + + dent = debugfs_create_dir("hw_stats", parent); + if (IS_ERR_OR_NULL(dent)) { + IPAERR("fail to create folder in debug_fs\n"); + return -EFAULT; + } + + file = debugfs_create_file("quota", read_write_mode, dent, NULL, + &ipa3_quota_ops); + if (IS_ERR_OR_NULL(file)) { + IPAERR("fail to create file %s\n", "quota"); + goto fail; + } + + file = debugfs_create_file("drop", read_write_mode, dent, NULL, + &ipa3_drop_ops); + if (IS_ERR_OR_NULL(file)) { + IPAERR("fail to create file %s\n", "drop"); + goto fail; + } + + file = debugfs_create_file("enable_drop_stats", write_mode, dent, NULL, + &ipa3_enable_drop_ops); + if (IS_ERR_OR_NULL(file)) { + IPAERR("fail to create file %s\n", "enable_drop_stats"); + goto fail; + } + + file = debugfs_create_file("tethering", read_write_mode, dent, NULL, + &ipa3_tethering_ops); + if (IS_ERR_OR_NULL(file)) { + IPAERR("fail to create file %s\n", "tethering"); + goto fail; + } + + file = debugfs_create_file("flt_rt", read_write_mode, dent, NULL, + &ipa3_flt_rt_ops); + if (IS_ERR_OR_NULL(file)) { + IPAERR("fail to create file flt_rt\n"); + goto fail; + } + + return 0; +fail: + debugfs_remove_recursive(dent); + return -EFAULT; +} +#endif diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_i.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_i.h new file mode 100644 index 0000000000..82cd0e99fb --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_i.h @@ -0,0 +1,3868 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. + * + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _IPA3_I_H_ +#define _IPA3_I_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ipa.h" +#include +#include "ipa_qdss.h" +#include +#include +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 9, 0)) +#include +#endif +#include +#include +#include "ipa_qmi_service.h" +#include "ipahal_reg.h" +#include "ipahal.h" +#include "ipahal_fltrt.h" +#include "ipahal_hw_stats.h" +#include "ipa_common_i.h" +#include "ipa_uc_offload_i.h" +#include "ipa_pm.h" +#include "ipa_defs.h" +#include +#include +#include +#include "ipa_uc_holb_monitor.h" +#include +#ifdef CONFIG_IPA_RTP +#include "ipa_rtp_genl.h" +#endif +#include + +#define IPA_DEV_NAME_MAX_LEN 15 +#define DRV_NAME "ipa" + +#define IPA_v4_USB0_EP_ID 11 +#define IPA_v4_USB1_EP_ID 12 + +#define IPA_v4_PCIE0_EP_ID 21 +#define IPA_v4_PCIE1_EP_ID 22 + +#define IPA_v5_PCIE0_EP_ID 4 + +#define IPA_COOKIE 0x57831603 +#define IPA_RT_RULE_COOKIE 0x57831604 +#define IPA_RT_TBL_COOKIE 0x57831605 +#define IPA_FLT_COOKIE 0x57831606 +#define IPA_HDR_COOKIE 0x57831607 +#define IPA_PROC_HDR_COOKIE 0x57831608 + +#define MTU_BYTE 1500 + +#define IPA_EP_NOT_ALLOCATED (-1) +#define IPA3_MAX_NUM_PIPES 31 +#define IPA5_PIPES_NUM 36 +#define IPA5_PIPE_REG_NUM 2 +#define IPA5_MAX_NUM_PIPES (IPA5_PIPES_NUM) +#define IPA_SYS_DESC_FIFO_SZ 0x800 +#define IPA_SYS_TX_DATA_DESC_FIFO_SZ 0x1000 +#define IPA_SYS_TX_DATA_DESC_FIFO_SZ_8K 0x2000 +#define IPA_SYS_TPUT_EP_DESC_FIFO_SZ 0x10 +#define IPA_COMMON_EVENT_RING_SIZE 0x7C00 +#define IPA_LAN_RX_HEADER_LENGTH (2) +#define IPA_QMAP_HEADER_LENGTH (4) +#define IPA_DL_CHECKSUM_LENGTH (8) +#define IPA_NUM_DESC_PER_SW_TX (3) +#define IPA_GENERIC_RX_POOL_SZ_WAN 224 +#define IPA_GENERIC_RX_POOL_SZ 192 +#define IPA_GENERIC_RX_PAGE_POOL_SZ_FACTOR 2 +#define IPA_GENERIC_RX_CMN_PAGE_POOL_SZ_FACTOR 5 +#define IPA_GENERIC_RX_CMN_TEMP_POOL_SZ_FACTOR 3 +#define IPA_UC_FINISH_MAX 6 +#define IPA_UC_WAIT_MIN_SLEEP 1000 +#define IPA_UC_WAII_MAX_SLEEP 1200 +#define IPA_HOLB_TMR_DIS 0x0 +#define IPA_HOLB_TMR_EN 0x1 +#define IPA_HOLB_TMR_VAL_4_5 31 +#define IPA_IMM_IP_PACKET_INIT_EX_CMD_NUM (IPA5_MAX_NUM_PIPES + 1) + +#define IPA_Q6_FNR_START_IDX (128) +#define IPA_Q6_FNR_IDX_CNT (52) +#define IPA_Q6_FNR_END_IDX (IPA_Q6_FNR_START_IDX+IPA_Q6_FNR_IDX_CNT-1) +#define IPA_Q6_FNR_STATS_SIZE (IPA_Q6_FNR_IDX_CNT * 16) +#define IPA_MPM_MAX_RING_LEN 64 +#define IPA_MAX_TETH_AGGR_BYTE_LIMIT 24 +#define IPA_MPM_MAX_UC_THRESH 4 + +/* ULSO Constants */ +enum { + ENDP_INIT_ULSO_CFG_IP_ID_MIN_MAX_VAL_IDX_LINUX, + ENDP_INIT_ULSO_CFG_IP_ID_MIN_MAX_VAL_IDX_FREE1, + ENDP_INIT_ULSO_CFG_IP_ID_MIN_MAX_VAL_IDX_FREE2, + ENDP_INIT_ULSO_CFG_IP_ID_MIN_MAX_VAL_IDX_MAX +}; + +#define QMAP_HDR_LEN 8 + +#define IPA_HOLB_TMR_DIS 0x0 +#define IPA_HOLB_TMR_EN 0x1 +/* + * The transport descriptor size was changed to GSI_CHAN_RE_SIZE_16B, but + * IPA users still use sps_iovec size as FIFO element size. + */ +#define IPA_FIFO_ELEMENT_SIZE 8 + +#define IPA_MAX_STATUS_STAT_NUM 30 + +#define IPA_IPC_LOG_PAGES 50 + +#define IPA_MAX_NUM_REQ_CACHE 10 + +#define NAPI_WEIGHT 64 + +#define NAPI_TX_WEIGHT 64 + +#define IPA_WAN_AGGR_PKT_CNT 1 + +#define IPA_PAGE_POLL_DEFAULT_THRESHOLD 15 +#define IPA_PAGE_POLL_THRESHOLD_MAX 30 + +#define NTN3_CLIENTS_NUM 2 + +#define IPA_MAX_NAPI_SORT_PAGE_THRSHLD 3 +#define IPA_MAX_PAGE_WQ_RESCHED_TIME 2 + +#define IPA_WDI2_OVER_GSI() (ipa3_ctx->ipa_wdi2_over_gsi \ + && (ipa_get_wdi_version() == IPA_WDI_2)) + +#define WLAN_IPA_EVENT(m) (m == WLAN_STA_CONNECT || \ + m == WLAN_AP_CONNECT || \ + m == WLAN_CLIENT_CONNECT_EX || \ + m == WLAN_CLIENT_CONNECT || \ + m == WLAN_STA_DISCONNECT || \ + m == WLAN_AP_DISCONNECT || \ + m == WLAN_CLIENT_DISCONNECT) + +#define IPADBG(fmt, args...) \ + do { \ + pr_debug(DRV_NAME " %s:%d " fmt, __func__, __LINE__, ## args);\ + if (ipa3_ctx) { \ + IPA_IPC_LOGGING(ipa3_ctx->logbuf, \ + DRV_NAME " %s:%d " fmt, ## args); \ + IPA_IPC_LOGGING(ipa3_ctx->logbuf_low, \ + DRV_NAME " %s:%d " fmt, ## args); \ + } \ + } while (0) + +#define IPADBG_LOW(fmt, args...) \ + do { \ + pr_debug(DRV_NAME " %s:%d " fmt, __func__, __LINE__, ## args);\ + if (ipa3_ctx) \ + IPA_IPC_LOGGING(ipa3_ctx->logbuf_low, \ + DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) + +#define IPADBG_CLK(fmt, args...) \ + do { \ + pr_debug(DRV_NAME " %s:%d " fmt, __func__, __LINE__, ## args);\ + if (ipa3_ctx) \ + IPA_IPC_LOGGING(ipa3_ctx->logbuf_clk, \ + DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) + +#define IPAERR(fmt, args...) \ + do { \ + pr_err(DRV_NAME " %s:%d " fmt, __func__, __LINE__, ## args);\ + if (ipa3_ctx) { \ + IPA_IPC_LOGGING(ipa3_ctx->logbuf, \ + DRV_NAME " %s:%d " fmt, ## args); \ + IPA_IPC_LOGGING(ipa3_ctx->logbuf_low, \ + DRV_NAME " %s:%d " fmt, ## args); \ + } \ + } while (0) + +#define IPAERR_RL(fmt, args...) \ + do { \ + pr_err_ratelimited_ipa(DRV_NAME " %s:%d " fmt, __func__,\ + __LINE__, ## args);\ + if (ipa3_ctx) { \ + IPA_IPC_LOGGING(ipa3_ctx->logbuf, \ + DRV_NAME " %s:%d " fmt, ## args); \ + IPA_IPC_LOGGING(ipa3_ctx->logbuf_low, \ + DRV_NAME " %s:%d " fmt, ## args); \ + } \ + } while (0) + +#define IPALOG_VnP_ADDRS(ptr) \ + do { \ + phys_addr_t b = (phys_addr_t) virt_to_phys(ptr); \ + IPAERR("%s: VIRT: %pK PHYS: %pa\n", \ + #ptr, ptr, &b); \ + } while (0) + +/* round addresses for closes page per SMMU requirements */ +#define IPA_SMMU_ROUND_TO_PAGE(iova, pa, size, iova_p, pa_p, size_p) \ + do { \ + (iova_p) = rounddown((iova), PAGE_SIZE); \ + (pa_p) = rounddown((pa), PAGE_SIZE); \ + (size_p) = roundup((size) + (pa) - (pa_p), PAGE_SIZE); \ + } while (0) + +#define WLAN_AMPDU_TX_EP 15 +#define WLAN_PROD_TX_EP 19 +#define WLAN1_CONS_RX_EP 14 +#define WLAN2_CONS_RX_EP 16 +#define WLAN3_CONS_RX_EP 17 +#define WLAN4_CONS_RX_EP 18 + +#define IPA_RAM_NAT_OFST \ + IPA_MEM_PART(nat_tbl_ofst) +#define IPA_RAM_NAT_SIZE \ + IPA_MEM_PART(nat_tbl_size) +#define IPA_RAM_IPV6CT_OFST 0 +#define IPA_RAM_IPV6CT_SIZE 0 +#define IPA_MEM_CANARY_VAL 0xdeadbeef + +#define IS_IPV6CT_MEM_DEV(d) \ + (((void *) (d) == (void *) &ipa3_ctx->ipv6ct_mem)) + +#define IS_NAT_MEM_DEV(d) \ + (((void *) (d) == (void *) &ipa3_ctx->nat_mem)) + +#define IPA_STATS + +#ifdef IPA_STATS +#define IPA_STATS_INC_CNT(val) (++val) +#define IPA_STATS_DEC_CNT(val) (--val) +#define IPA_STATS_EXCP_CNT(__excp, __base) do { \ + if (__excp < 0 || __excp >= IPAHAL_PKT_STATUS_EXCEPTION_MAX) \ + break; \ + ++__base[__excp]; \ + } while (0) +#else +#define IPA_STATS_INC_CNT(x) do { } while (0) +#define IPA_STATS_DEC_CNT(x) +#define IPA_STATS_EXCP_CNT(__excp, __base) do { } while (0) +#endif + +#define IPA_HDR_BIN0 0 +#define IPA_HDR_BIN1 1 +#define IPA_HDR_BIN2 2 +#define IPA_HDR_BIN3 3 +#define IPA_HDR_BIN4 4 +#define IPA_HDR_BIN5 5 +#define IPA_HDR_BIN_MAX 6 + +enum hdr_tbl_storage { + HDR_TBL_LCL, + HDR_TBL_SYS, + HDR_TBLS_TOTAL, +}; + +#define IPA_HDR_TO_DDR_PATTERN 0x2DDA + +#define IPA_HDR_PROC_CTX_BIN0 0 +#define IPA_HDR_PROC_CTX_BIN1 1 +#define IPA_HDR_PROC_CTX_BIN_MAX 2 + +#define IPA_RX_POOL_CEIL 32 +#define IPA_RX_SKB_SIZE 1792 + +#define IPA_A5_MUX_HDR_NAME "ipa_excp_hdr" +#define IPA_LAN_RX_HDR_NAME "ipa_lan_hdr" +#define IPA_INVALID_L4_PROTOCOL 0xFF + +#define IPA_HDR_PROC_CTX_TABLE_ALIGNMENT_BYTE 8 +#define IPA_HDR_PROC_CTX_TABLE_ALIGNMENT(start_ofst) \ + (((start_ofst) + IPA_HDR_PROC_CTX_TABLE_ALIGNMENT_BYTE - 1) & \ + ~(IPA_HDR_PROC_CTX_TABLE_ALIGNMENT_BYTE - 1)) + +#define MAX_RESOURCE_TO_CLIENTS (IPA_CLIENT_MAX) +#define IPA_MEM_PART(x_) (ipa3_ctx->ctrl->mem_partition->x_) + +#define IPA_GSI_CHANNEL_STOP_MAX_RETRY 10 +#define IPA_GSI_CHANNEL_STOP_PKT_SIZE 1 + +#define IPA_GSI_CHANNEL_EMPTY_MAX_RETRY 15 +#define IPA_GSI_CHANNEL_EMPTY_SLEEP_MIN_USEC (1000) +#define IPA_GSI_CHANNEL_EMPTY_SLEEP_MAX_USEC (2000) + +#define IPA_SLEEP_CLK_RATE_KHZ (32) + +#define IPA3_ACTIVE_CLIENTS_LOG_BUFFER_SIZE_LINES 120 +#define IPA3_ACTIVE_CLIENTS_LOG_LINE_LEN 96 +#define IPA3_ACTIVE_CLIENTS_LOG_HASHTABLE_SIZE 50 +#define IPA3_ACTIVE_CLIENTS_LOG_NAME_LEN 40 +#define SMEM_IPA_FILTER_TABLE 497 +#define IPA_TX_WRAPPER_CACHE_MAX_THRESHOLD 2000 + +enum { + SMEM_APPS, + SMEM_MODEM, + SMEM_Q6, + SMEM_DSPS, + SMEM_WCNSS, + SMEM_CDSP, + SMEM_RPM, + SMEM_TZ, + SMEM_SPSS, + SMEM_HYP, + NUM_SMEM_SUBSYSTEMS, +}; + +#define IPA_WDI_RX_RING_RES 0 +#define IPA_WDI_RX_RING_RP_RES 1 +#define IPA_WDI_RX_COMP_RING_RES 2 +#define IPA_WDI_RX_COMP_RING_WP_RES 3 +#define IPA_WDI_RX2_RING_RES 4 +#define IPA_WDI_RX2_RING_RP_RES 5 +#define IPA_WDI_RX2_COMP_RING_RES 6 +#define IPA_WDI_RX2_COMP_RING_WP_RES 7 +#define IPA_WDI_TX_RING_RES 8 +#define IPA_WDI_CE_RING_RES 9 +#define IPA_WDI_CE_DB_RES 10 +#define IPA_WDI_TX_DB_RES 11 +#define IPA_WDI_TX1_RING_RES 12 +#define IPA_WDI_CE1_RING_RES 13 +#define IPA_WDI_CE1_DB_RES 14 +#define IPA_WDI_TX1_DB_RES 15 +#define IPA_WDI_TX2_RING_RES 16 +#define IPA_WDI_CE2_RING_RES 17 +#define IPA_WDI_CE2_DB_RES 18 +#define IPA_WDI_TX2_DB_RES 19 +#define IPA_WDI_MAX_RES 20 + +#define IPA_WDI3_TX2_DIR 4 +#define IPA_WDI3_RX2_DIR 5 + +/* use QMAP header reserved bit to identify tethered traffic */ +#define IPA_QMAP_TETH_BIT (1 << 30) + +#ifdef CONFIG_ARM64 +/* Outer caches unsupported on ARM64 platforms */ +# define outer_flush_range(x, y) +# define __cpuc_flush_dcache_area __flush_dcache_area +#endif + +#define IPA_APP_VOTE_MAX 500 + +#define IPA_SMP2P_OUT_CLK_RSP_CMPLT_IDX 0 +#define IPA_SMP2P_OUT_CLK_VOTE_IDX 1 +#define IPA_SMP2P_SMEM_STATE_MASK 3 + + +#define IPA_SUMMING_THRESHOLD (0x10) +#define IPA_PIPE_MEM_START_OFST (0x0) +#define IPA_PIPE_MEM_SIZE (0x0) +#define IPA_MOBILE_AP_MODE(x) (x == IPA_MODE_MOBILE_AP_ETH || \ + x == IPA_MODE_MOBILE_AP_WAN || \ + x == IPA_MODE_MOBILE_AP_WLAN) +#define IPA_CNOC_CLK_RATE (75 * 1000 * 1000UL) +#define IPA_A5_MUX_HEADER_LENGTH (8) + +#define IPA_AGGR_MAX_STR_LENGTH (10) + +#define CLEANUP_TAG_PROCESS_TIMEOUT 1000 + +#define IPA_AGGR_STR_IN_BYTES(str) \ + (strnlen((str), IPA_AGGR_MAX_STR_LENGTH - 1) + 1) + +#define IPA_ADJUST_AGGR_BYTE_HARD_LIMIT(X) (X/1000) + +#define IPA_TRANSPORT_PROD_TIMEOUT_MSEC 100 + +#define IPA3_ACTIVE_CLIENTS_TABLE_BUF_SIZE 4096 + +#define IPA_UC_ACT_TBL_SIZE 1000 + +#define IPA3_ACTIVE_CLIENT_LOG_TYPE_EP 0 +#define IPA3_ACTIVE_CLIENT_LOG_TYPE_SIMPLE 1 +#define IPA3_ACTIVE_CLIENT_LOG_TYPE_RESOURCE 2 +#define IPA3_ACTIVE_CLIENT_LOG_TYPE_SPECIAL 3 + +#define IPA_MHI_GSI_EVENT_RING_ID_START 10 +#define IPA_MHI_GSI_EVENT_RING_ID_END 12 + +#define IPA_SMEM_SIZE (8 * 1024) + +#define IPA_GSI_CHANNEL_HALT_MIN_SLEEP 5000 +#define IPA_GSI_CHANNEL_HALT_MAX_SLEEP 10000 +#define IPA_GSI_CHANNEL_HALT_MAX_TRY 10 + +/* round addresses for closes page per SMMU requirements */ +#define IPA_SMMU_ROUND_TO_PAGE(iova, pa, size, iova_p, pa_p, size_p) \ + do { \ + (iova_p) = rounddown((iova), PAGE_SIZE); \ + (pa_p) = rounddown((pa), PAGE_SIZE); \ + (size_p) = roundup((size) + (pa) - (pa_p), PAGE_SIZE); \ + } while (0) + + +/* The relative location in /lib/firmware where the FWs will reside */ +#define IPA_FWS_PATH "ipa/ipa_fws.elf" +/* + * The following paths below are used when building the system for the + * emulation environment. + * + * As new hardware platforms are added into the emulation environment, + * please add the appropriate paths here for their firmwares. + */ +#define IPA_FWS_PATH_4_0 "ipa/4.0/ipa_fws.elf" +#define IPA_FWS_PATH_3_5_1 "ipa/3.5.1/ipa_fws.elf" +#define IPA_FWS_PATH_4_5 "ipa/4.5/ipa_fws.elf" + +/* + * The following will be used for determining/using access control + * policy. + */ +#define USE_SCM 0 /* use scm call to determine policy */ +#define OVERRIDE_SCM_TRUE 1 /* override scm call with true */ +#define OVERRIDE_SCM_FALSE 2 /* override scm call with false */ + +#define SD_ENABLED 0 /* secure debug enabled. */ +#define SD_DISABLED 1 /* secure debug disabled. */ + +#define IPA_MEM_INIT_VAL 0xFFFFFFFF + +#ifdef CONFIG_COMPAT +#define IPA_IOC_COAL_EVICT_POLICY32 _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_COAL_EVICT_POLICY, \ + compat_uptr_t) +#define IPA_IOC_ADD_HDR32 _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_ADD_HDR, \ + compat_uptr_t) +#define IPA_IOC_DEL_HDR32 _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_DEL_HDR, \ + compat_uptr_t) +#define IPA_IOC_ADD_RT_RULE32 _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_ADD_RT_RULE, \ + compat_uptr_t) +#define IPA_IOC_DEL_RT_RULE32 _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_DEL_RT_RULE, \ + compat_uptr_t) +#define IPA_IOC_ADD_FLT_RULE32 _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_ADD_FLT_RULE, \ + compat_uptr_t) +#define IPA_IOC_DEL_FLT_RULE32 _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_DEL_FLT_RULE, \ + compat_uptr_t) +#define IPA_IOC_GET_RT_TBL32 _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_GET_RT_TBL, \ + compat_uptr_t) +#define IPA_IOC_COPY_HDR32 _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_COPY_HDR, \ + compat_uptr_t) +#define IPA_IOC_QUERY_INTF32 _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_QUERY_INTF, \ + compat_uptr_t) +#define IPA_IOC_QUERY_INTF_TX_PROPS32 _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_QUERY_INTF_TX_PROPS, \ + compat_uptr_t) +#define IPA_IOC_QUERY_INTF_RX_PROPS32 _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_QUERY_INTF_RX_PROPS, \ + compat_uptr_t) +#define IPA_IOC_QUERY_INTF_EXT_PROPS32 _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_QUERY_INTF_EXT_PROPS, \ + compat_uptr_t) +#define IPA_IOC_GET_HDR32 _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_GET_HDR, \ + compat_uptr_t) +#define IPA_IOC_ALLOC_NAT_MEM32 _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_ALLOC_NAT_MEM, \ + compat_uptr_t) +#define IPA_IOC_ALLOC_NAT_TABLE32 _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_ALLOC_NAT_TABLE, \ + compat_uptr_t) +#define IPA_IOC_ALLOC_IPV6CT_TABLE32 _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_ALLOC_IPV6CT_TABLE, \ + compat_uptr_t) +#define IPA_IOC_V4_INIT_NAT32 _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_V4_INIT_NAT, \ + compat_uptr_t) +#define IPA_IOC_INIT_IPV6CT_TABLE32 _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_INIT_IPV6CT_TABLE, \ + compat_uptr_t) +#define IPA_IOC_TABLE_DMA_CMD32 _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_TABLE_DMA_CMD, \ + compat_uptr_t) +#define IPA_IOC_V4_DEL_NAT32 _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_V4_DEL_NAT, \ + compat_uptr_t) +#define IPA_IOC_DEL_NAT_TABLE32 _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_DEL_NAT_TABLE, \ + compat_uptr_t) +#define IPA_IOC_DEL_IPV6CT_TABLE32 _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_DEL_IPV6CT_TABLE, \ + compat_uptr_t) +#define IPA_IOC_NAT_MODIFY_PDN32 _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_NAT_MODIFY_PDN, \ + compat_uptr_t) +#define IPA_IOC_GET_NAT_OFFSET32 _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_GET_NAT_OFFSET, \ + compat_uptr_t) +#define IPA_IOC_PULL_MSG32 _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_PULL_MSG, \ + compat_uptr_t) +#define IPA_IOC_RM_ADD_DEPENDENCY32 _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_RM_ADD_DEPENDENCY, \ + compat_uptr_t) +#define IPA_IOC_RM_DEL_DEPENDENCY32 _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_RM_DEL_DEPENDENCY, \ + compat_uptr_t) +#define IPA_IOC_GENERATE_FLT_EQ32 _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_GENERATE_FLT_EQ, \ + compat_uptr_t) +#define IPA_IOC_QUERY_RT_TBL_INDEX32 _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_QUERY_RT_TBL_INDEX, \ + compat_uptr_t) +#define IPA_IOC_WRITE_QMAPID32 _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_WRITE_QMAPID, \ + compat_uptr_t) +#define IPA_IOC_MDFY_FLT_RULE32 _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_MDFY_FLT_RULE, \ + compat_uptr_t) +#define IPA_IOC_NOTIFY_WAN_UPSTREAM_ROUTE_ADD32 _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_NOTIFY_WAN_UPSTREAM_ROUTE_ADD, \ + compat_uptr_t) +#define IPA_IOC_NOTIFY_WAN_UPSTREAM_ROUTE_DEL32 _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_NOTIFY_WAN_UPSTREAM_ROUTE_DEL, \ + compat_uptr_t) +#define IPA_IOC_NOTIFY_WAN_EMBMS_CONNECTED32 _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_NOTIFY_WAN_EMBMS_CONNECTED, \ + compat_uptr_t) +#define IPA_IOC_ADD_HDR_PROC_CTX32 _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_ADD_HDR_PROC_CTX, \ + compat_uptr_t) +#define IPA_IOC_DEL_HDR_PROC_CTX32 _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_DEL_HDR_PROC_CTX, \ + compat_uptr_t) +#define IPA_IOC_MDFY_RT_RULE32 _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_MDFY_RT_RULE, \ + compat_uptr_t) +#define IPA_IOC_GET_NAT_IN_SRAM_INFO32 _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_GET_NAT_IN_SRAM_INFO, \ + compat_uptr_t) +#define IPA_IOC_APP_CLOCK_VOTE32 _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_APP_CLOCK_VOTE, \ + compat_uptr_t) +#define IPA_IOC_ADD_EoGRE_MAPPING32 _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_ADD_EoGRE_MAPPING, \ + compat_uptr_t) +#define IPA_IOC_DEL_EoGRE_MAPPING32 _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_DEL_EoGRE_MAPPING, \ + compat_uptr_t) +#define IPA_IOC_SET_NAT_EXC_RT_TBL_IDX32 _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_SET_NAT_EXC_RT_TBL_IDX, \ + compat_uptr_t) +#define IPA_IOC_SET_CONN_TRACK_EXC_RT_TBL_IDX32 _IOWR(IPA_IOC_MAGIC, \ + IPA_IOCTL_SET_CONN_TRACK_EXC_RT_TBL_IDX, \ + compat_uptr_t) +#endif /* #ifdef CONFIG_COMPAT */ + +#define IPA_TZ_UNLOCK_ATTRIBUTE 0x0C0311 + +#define MBOX_TOUT_MS 100 + +#define IPA_RULE_CNT_MAX 512 + +/* XR-IPA uC temp buffers sizes */ +#define TEMP_BUFF_SIZE 0x300000 +/* XR-IPA uC no. of temp buffers */ +#define NO_OF_BUFFS 0x04 +/* Max number of RTP streams supported */ +#define MAX_STREAMS 2 + +/* miscellaneous for rmnet_ipa and qmi_service */ +enum ipa_type_mode { + IPA_HW_TYPE, + PLATFORM_TYPE, + IPA3_HW_MODE, +}; + +enum ipa_flag { + IPA_ENDP_DELAY_WA_EN, + IPA_HW_STATS_EN, + IPA_MHI_EN, + IPA_FLTRT_NOT_HASHABLE_EN, +}; + +enum ipa_icc_level { + IPA_ICC_NONE, + IPA_ICC_SVS2, + IPA_ICC_SVS, + IPA_ICC_NOMINAL, + IPA_ICC_TURBO, + IPA_ICC_LVL_MAX, +}; + +enum ipa_icc_path { + IPA_ICC_IPA_TO_LLCC, + IPA_ICC_LLCC_TO_EBIL, + IPA_ICC_IPA_TO_IMEM, + IPA_ICC_APSS_TO_IPA, + IPA_ICC_PATH_MAX, +}; + +enum ipa_icc_type { + IPA_ICC_AB, + IPA_ICC_IB, + IPA_ICC_TYPE_MAX, +}; + +#define IPA_ICC_MAX (IPA_ICC_PATH_MAX*IPA_ICC_TYPE_MAX) + + +#define IPA_MHI_CTRL_NOT_SETUP (0) +#define IPA_MHI_CTRL_UL_SETUP (1 << 1) +#define IPA_MHI_CTRL_DL_SETUP (1 << 2) +#define IPA_MHI_CTRL_SETUP_ALL (IPA_MHI_CTRL_UL_SETUP | IPA_MHI_CTRL_DL_SETUP) + +/** + * struct ipa_rx_page_data - information needed + * to send to wlan driver on receiving data from ipa hw + * @page: skb page + * @dma_addr: DMA address of this Rx packet + * @is_tmp_alloc: skb page from tmp_alloc or recycle_list + * @page_order: page order associated with the page. + */ +struct ipa_rx_page_data { + struct page *page; + dma_addr_t dma_addr; + bool is_tmp_alloc; + u32 page_order; +}; + +struct ipa3_active_client_htable_entry { + struct hlist_node list; + char id_string[IPA3_ACTIVE_CLIENTS_LOG_NAME_LEN]; + int count; + enum ipa_active_client_log_type type; +}; + +struct ipa3_active_clients_log_ctx { + spinlock_t lock; + char *log_buffer[IPA3_ACTIVE_CLIENTS_LOG_BUFFER_SIZE_LINES]; + int log_head; + int log_tail; + bool log_rdy; + struct hlist_head htable[IPA3_ACTIVE_CLIENTS_LOG_HASHTABLE_SIZE]; +}; + +struct ipa3_client_names { + enum ipa_client_type names[MAX_RESOURCE_TO_CLIENTS]; + int length; +}; + +struct ipa_smmu_cb_ctx { + bool valid; + struct device *dev; + struct iommu_domain *iommu_domain; + unsigned long next_addr; + u32 va_start; + u32 va_size; + u32 va_end; + u32 geometry_start; + u32 geometry_end; + bool shared; + bool is_cache_coherent; + bool done; +}; + +/** + * struct ipa_flt_rule_add_i - filtering rule descriptor + * includes in and out parameters + * @rule: actual rule to be added + * @at_rear: add at back of filtering table? + * @flt_rule_hdl: out parameter, handle to rule, valid when status is 0 + * @status: output parameter, status of filtering rule add operation, + * 0 for success, + * -1 for failure + * + */ +struct ipa_flt_rule_add_i { + u8 at_rear; + u32 flt_rule_hdl; + int status; + struct ipa_flt_rule_i rule; +}; + +/** + * struct ipa_flt_rule_mdfy_i - filtering rule descriptor + * includes in and out parameters + * @rule: actual rule to be added + * @flt_rule_hdl: handle to rule + * @status: output parameter, status of filtering rule modify operation, + * 0 for success, + * -1 for failure + * + */ +struct ipa_flt_rule_mdfy_i { + u32 rule_hdl; + int status; + struct ipa_flt_rule_i rule; +}; + +/** + * struct ipa_rt_rule_add_i - routing rule descriptor includes + * in and out parameters + * @rule: actual rule to be added + * @at_rear: add at back of routing table, it is NOT possible to add rules at + * the rear of the "default" routing tables + * @rt_rule_hdl: output parameter, handle to rule, valid when status is 0 + * @status: output parameter, status of routing rule add operation, + * 0 for success, + * -1 for failure + */ +struct ipa_rt_rule_add_i { + u8 at_rear; + u32 rt_rule_hdl; + int status; + struct ipa_rt_rule_i rule; +}; + +/** + * struct ipa_rt_rule_mdfy_i - routing rule descriptor includes + * in and out parameters + * @rule: actual rule to be added + * @rt_rule_hdl: handle to rule which supposed to modify + * @status: output parameter, status of routing rule modify operation, + * 0 for success, + * -1 for failure + * + */ +struct ipa_rt_rule_mdfy_i { + u32 rt_rule_hdl; + int status; + struct ipa_rt_rule_i rule; +}; + +/** + * struct ipa_rt_rule_add_ext_i - routing rule descriptor + * includes in and out parameters + * @rule: actual rule to be added + * @at_rear: add at back of routing table, it is NOT possible to add rules at + * the rear of the "default" routing tables + * @rt_rule_hdl: output parameter, handle to rule, valid when status is 0 + * @status: output parameter, status of routing rule add operation, + * @rule_id: rule_id to be assigned to the routing rule. In case client + * specifies rule_id as 0 the driver will assign a new rule_id + * 0 for success, + * -1 for failure + */ +struct ipa_rt_rule_add_ext_i { + uint8_t at_rear; + uint32_t rt_rule_hdl; + int status; + uint16_t rule_id; + struct ipa_rt_rule_i rule; +}; + +/** + * struct ipa3_flt_entry - IPA filtering table entry + * @link: entry's link in global filtering enrties list + * @rule: filter rule + * @cookie: cookie used for validity check + * @tbl: filter table + * @rt_tbl: routing table + * @hw_len: entry's size + * @id: rule handle - globally unique + * @prio: rule 10bit priority which defines the order of the rule + * among other rules at the same integrated table + * @rule_id: rule 10bit ID to be returned in packet status + * @cnt_idx: stats counter index + * @ipacm_installed: indicate if installed by ipacm + */ +struct ipa3_flt_entry { + struct list_head link; + u32 cookie; + struct ipa_flt_rule_i rule; + struct ipa3_flt_tbl *tbl; + struct ipa3_rt_tbl *rt_tbl; + u32 hw_len; + int id; + u16 prio; + u16 rule_id; + u8 cnt_idx; + bool ipacm_installed; +}; + +/** + * struct ipa3_rt_tbl - IPA routing table + * @link: table's link in global routing tables list + * @head_rt_rule_list: head of routing rules list + * @name: routing table name + * @idx: routing table index + * @rule_cnt: number of rules in routing table + * @ref_cnt: reference counter of routing table + * @set: collection of routing tables + * @cookie: cookie used for validity check + * @in_sys: flag indicating if the table is located in system memory + * @sz: the size of the routing table + * @curr_mem: current routing tables block in sys memory + * @prev_mem: previous routing table block in sys memory + * @id: routing table id + * @rule_ids: common idr structure that holds the rule_id for each rule + */ +struct ipa3_rt_tbl { + struct list_head link; + u32 cookie; + struct list_head head_rt_rule_list; + char name[IPA_RESOURCE_NAME_MAX]; + u32 idx; + u32 rule_cnt; + u32 ref_cnt; + struct ipa3_rt_tbl_set *set; + bool in_sys[IPA_RULE_TYPE_MAX]; + u32 sz[IPA_RULE_TYPE_MAX]; + struct ipa_mem_buffer curr_mem[IPA_RULE_TYPE_MAX]; + struct ipa_mem_buffer prev_mem[IPA_RULE_TYPE_MAX]; + int id; + struct idr *rule_ids; +}; + +/** + * struct ipa3_hdr_entry - IPA header table entry + * @link: entry's link in global header table entries list + * @hdr: the header + * @hdr_len: header length + * @name: name of header table entry + * @type: l2 header type + * @is_partial: flag indicating if header table entry is partial + * @proc_ctx: processing context header + * @offset_entry: entry's offset + * @cookie: cookie used for validity check + * @ref_cnt: reference counter of routing table + * @id: header entry id + * @is_eth2_ofst_valid: is eth2_ofst field valid? + * @eth2_ofst: offset to start of Ethernet-II/802.3 header + * @user_deleted: is the header deleted by the user? + * @ipacm_installed: indicate if installed by ipacm + * @is_lcl: is the entry in the SRAM? + */ +struct ipa3_hdr_entry { + struct list_head link; + u32 cookie; + u8 hdr[IPA_HDR_MAX_SIZE]; + u32 hdr_len; + char name[IPA_RESOURCE_NAME_MAX]; + enum ipa_hdr_l2_type type; + u8 is_partial; + struct ipa3_hdr_proc_ctx_entry *proc_ctx; + struct ipa_hdr_offset_entry *offset_entry; + u32 ref_cnt; + int id; + u8 is_eth2_ofst_valid; + u16 eth2_ofst; + bool user_deleted; + bool ipacm_installed; + bool is_lcl; +}; + +/** + * struct ipa3_hdr_tbl - IPA header table + * @head_hdr_entry_list: header entries list + * @head_offset_list: header offset list + * @head_free_offset_list: header free offset list + * @hdr_cnt: number of headers + * @end: the last header index + */ +struct ipa3_hdr_tbl { + struct list_head head_hdr_entry_list; + struct list_head head_offset_list[IPA_HDR_BIN_MAX]; + struct list_head head_free_offset_list[IPA_HDR_BIN_MAX]; + u32 hdr_cnt; + u32 end; +}; + +/** + * struct ipa3_hdr_offset_entry - IPA header offset entry + * @link: entry's link in global processing context header offset entries list + * @offset: the offset + * @bin: bin + * @ipacm_installed: indicate if installed by ipacm + */ +struct ipa3_hdr_proc_ctx_offset_entry { + struct list_head link; + u32 offset; + u32 bin; + bool ipacm_installed; +}; + +/** + * struct ipa3_hdr_proc_ctx_entry - IPA processing context header table entry + * @link: entry's link in global header table entries list + * @type: header processing context type + * @l2tp_params: L2TP parameters + * @generic_params: generic proc_ctx params + * @rtp_params: ipa rtp proc_ctx params + * @offset_entry: entry's offset + * @hdr: the header + * @cookie: cookie used for validity check + * @ref_cnt: reference counter of routing table + * @id: processing context header entry id + * @user_deleted: is the hdr processing context deleted by the user? + * @ipacm_installed: indicate if installed by ipacm + */ +struct ipa3_hdr_proc_ctx_entry { + struct list_head link; + u32 cookie; + enum ipa_hdr_proc_type type; + struct ipa_l2tp_hdr_proc_ctx_params l2tp_params; + struct ipa_eogre_hdr_proc_ctx_params eogre_params; + struct ipa_eth_II_to_eth_II_ex_procparams generic_params; + struct ipa_rtp_hdr_proc_ctx_params rtp_params; + struct ipa3_hdr_proc_ctx_offset_entry *offset_entry; + struct ipa3_hdr_entry *hdr; + u32 ref_cnt; + int id; + bool user_deleted; + bool ipacm_installed; +}; + +/** + * struct ipa3_hdr_proc_ctx_tbl - IPA processing context header table + * @head_proc_ctx_entry_list: header entries list + * @head_offset_list: header offset list + * @head_free_offset_list: header free offset list + * @proc_ctx_cnt: number of processing context headers + * @end: the last processing context header index + * @start_offset: offset in words of processing context header table + */ +struct ipa3_hdr_proc_ctx_tbl { + struct list_head head_proc_ctx_entry_list; + struct list_head head_offset_list[IPA_HDR_PROC_CTX_BIN_MAX]; + struct list_head head_free_offset_list[IPA_HDR_PROC_CTX_BIN_MAX]; + u32 proc_ctx_cnt; + u32 end; + u32 start_offset; +}; + +/** + * struct ipa3_flt_tbl - IPA filter table + * @head_flt_rule_list: filter rules list + * @rule_cnt: number of filter rules + * @in_sys: flag indicating if filter table is located in system memory + * @sz: the size of the filter tables + * @curr_mem: current filter tables block in sys memory + * @prev_mem: previous filter table block in sys memory + * @rule_ids: common idr structure that holds the rule_id for each rule + * @force_sys: flag indicating if filter table is forced to be + located in system memory + */ +struct ipa3_flt_tbl { + struct list_head head_flt_rule_list; + u32 rule_cnt; + bool in_sys[IPA_RULE_TYPE_MAX]; + u32 sz[IPA_RULE_TYPE_MAX]; + struct ipa_mem_buffer curr_mem[IPA_RULE_TYPE_MAX]; + struct ipa_mem_buffer prev_mem[IPA_RULE_TYPE_MAX]; + bool sticky_rear; + struct idr *rule_ids; + bool force_sys[IPA_RULE_TYPE_MAX]; +}; + +struct ipa3_flt_tbl_nhash_lcl { + struct list_head link; + struct ipa3_flt_tbl *tbl; +}; + +/** + * struct ipa3_rt_entry - IPA routing table entry + * @link: entry's link in global routing table entries list + * @rule: routing rule + * @cookie: cookie used for validity check + * @tbl: routing table + * @hdr: header table + * @proc_ctx: processing context table + * @hw_len: the length of the table + * @id: rule handle - globaly unique + * @prio: rule 10bit priority which defines the order of the rule + * among other rules at the integrated same table + * @rule_id: rule 10bit ID to be returned in packet status + * @rule_id_valid: indicate if rule_id_valid valid or not? + * @cnt_idx: stats counter index + * @ipacm_installed: indicate if installed by ipacm + */ +struct ipa3_rt_entry { + struct list_head link; + u32 cookie; + struct ipa_rt_rule_i rule; + struct ipa3_rt_tbl *tbl; + struct ipa3_hdr_entry *hdr; + struct ipa3_hdr_proc_ctx_entry *proc_ctx; + u32 hw_len; + int id; + u16 prio; + u16 rule_id; + u16 rule_id_valid; + u8 cnt_idx; + bool ipacm_installed; +}; + +/** + * struct ipa3_rt_tbl_set - collection of routing tables + * @head_rt_tbl_list: collection of routing tables + * @tbl_cnt: number of routing tables + * @rule_ids: idr structure that holds the rule_id for each rule + */ +struct ipa3_rt_tbl_set { + struct list_head head_rt_tbl_list; + u32 tbl_cnt; + struct idr rule_ids; +}; + +/** + * struct ipa3_wlan_stats - Wlan stats for each wlan endpoint + * @rx_pkts_rcvd: Packets sent by wlan driver + * @rx_pkts_status_rcvd: Status packets received from ipa hw + * @rx_hd_processed: Data Descriptors processed by IPA Driver + * @rx_hd_reply: Data Descriptors recycled by wlan driver + * @rx_hd_rcvd: Data Descriptors sent by wlan driver + * @rx_pkt_leak: Packet count that are not recycled + * @rx_dp_fail: Packets failed to transfer to IPA HW + * @tx_pkts_rcvd: SKB Buffers received from ipa hw + * @tx_pkts_sent: SKB Buffers sent to wlan driver + * @tx_pkts_dropped: Dropped packets count + */ +struct ipa3_wlan_stats { + u32 rx_pkts_rcvd; + u32 rx_pkts_status_rcvd; + u32 rx_hd_processed; + u32 rx_hd_reply; + u32 rx_hd_rcvd; + u32 rx_pkt_leak; + u32 rx_dp_fail; + u32 tx_pkts_rcvd; + u32 tx_pkts_sent; + u32 tx_pkts_dropped; +}; + +/** + * struct ipa3_wlan_comm_memb - Wlan comm members + * @wlan_spinlock: protects wlan comm buff list and its size + * @ipa_tx_mul_spinlock: protects tx dp mul transfer + * @wlan_comm_total_cnt: wlan common skb buffers allocated count + * @wlan_comm_free_cnt: wlan common skb buffer free count + * @total_tx_pkts_freed: Recycled Buffer count + * @wlan_comm_desc_list: wlan common skb buffer list + */ +struct ipa3_wlan_comm_memb { + spinlock_t wlan_spinlock; + spinlock_t ipa_tx_mul_spinlock; + u32 wlan_comm_total_cnt; + u32 wlan_comm_free_cnt; + u32 total_tx_pkts_freed; + struct list_head wlan_comm_desc_list; + atomic_t active_clnt_cnt; +}; + +struct ipa_gsi_ep_mem_info { + u32 evt_ring_len; + u64 evt_ring_base_addr; + void *evt_ring_base_vaddr; + u32 chan_ring_len; + u64 chan_ring_base_addr; + void *chan_ring_base_vaddr; + u64 evt_ring_rp_addr; + void *evt_ring_rp_vaddr; +}; + +struct ipa3_status_stats { + struct ipahal_pkt_status status[IPA_MAX_STATUS_STAT_NUM]; + unsigned int curr; +}; + +/** + * struct ipa3_ep_context - IPA end point context + * @valid: flag indicating id EP context is valid + * @client: EP client type + * @gsi_chan_hdl: EP's GSI channel handle + * @gsi_evt_ring_hdl: EP's GSI channel event ring handle + * @gsi_mem_info: EP's GSI channel rings info + * @chan_scratch: EP's GSI channel scratch info + * @cfg: EP cionfiguration + * @dst_pipe_index: destination pipe index + * @rt_tbl_idx: routing table index + * @priv: user provided information which will forwarded once the user is + * notified for new data avail + * @client_notify: user provided CB for EP events notification, the event is + * data revived. + * @skip_ep_cfg: boolean field that determines if EP should be configured + * by IPA driver + * @keep_ipa_awake: when true, IPA will not be clock gated + * @disconnect_in_progress: Indicates client disconnect in progress. + * @qmi_request_sent: Indicates whether QMI request to enable clear data path + * request is sent or not. + * @client_lock_unlock: callback function to take mutex lock/unlock for USB + * clients + */ +struct ipa3_ep_context { + int valid; + enum ipa_client_type client; + unsigned long gsi_chan_hdl; + unsigned long gsi_evt_ring_hdl; + struct ipa_gsi_ep_mem_info gsi_mem_info; + union __packed gsi_channel_scratch chan_scratch; + struct gsi_chan_xfer_notify xfer_notify; + bool xfer_notify_valid; + struct ipa_ep_cfg cfg; + struct ipa_ep_cfg_holb holb; + struct ipahal_reg_ep_cfg_status status; + u32 dst_pipe_index; + u32 rt_tbl_idx; + void *priv; + void (*client_notify)(void *priv, enum ipa_dp_evt_type evt, + unsigned long data); + atomic_t avail_fifo_desc; + u32 dflt_flt4_rule_hdl; + u32 dflt_flt6_rule_hdl; + u32 dl_flt4_rule_hdl; + u32 dl_flt6_rule_hdl; + u32 rtp_flt4_rule_hdls[MAX_STREAMS]; + bool skip_ep_cfg; + bool keep_ipa_awake; + struct ipa3_wlan_stats wstats; + u32 uc_offload_state; + u32 gsi_offload_state; + atomic_t disconnect_in_progress; + u32 qmi_request_sent; + u32 eot_in_poll_err; + bool ep_delay_set; + + /* sys MUST be the last element of this struct */ + struct ipa3_sys_context *sys; +}; + +/** + * ipa_usb_xdci_chan_params - xDCI channel related properties + * + * @ipa_ep_cfg: IPA EP configuration + * @client: type of "client" + * @priv: callback cookie + * @notify: callback + * priv - callback cookie evt - type of event data - data relevant + * to event. May not be valid. See event_type enum for valid + * cases. + * @skip_ep_cfg: boolean field that determines if EP should be + * configured by IPA driver + * @keep_ipa_awake: when true, IPA will not be clock gated + * @evt_ring_params: parameters for the channel's event ring + * @evt_scratch: parameters for the channel's event ring scratch + * @chan_params: parameters for the channel + * @chan_scratch: parameters for the channel's scratch + * + */ +struct ipa_request_gsi_channel_params { + struct ipa_ep_cfg ipa_ep_cfg; + enum ipa_client_type client; + void *priv; + ipa_notify_cb notify; + bool skip_ep_cfg; + bool keep_ipa_awake; + struct gsi_evt_ring_props evt_ring_params; + union __packed gsi_evt_scratch evt_scratch; + struct gsi_chan_props chan_params; + union __packed gsi_channel_scratch chan_scratch; +}; + +enum ipa3_sys_pipe_policy { + IPA_POLICY_INTR_MODE, + IPA_POLICY_NOINTR_MODE, + IPA_POLICY_INTR_POLL_MODE, +}; + +struct ipa3_repl_ctx { + struct ipa3_rx_pkt_wrapper **cache; + atomic_t head_idx; + atomic_t tail_idx; + u32 capacity; + atomic_t pending; +}; + +struct ipa3_page_repl_ctx { + struct list_head page_repl_head; + u32 capacity; + atomic_t pending; +}; + +/** + * struct ipa3_sys_context - IPA GPI pipes context + * @head_desc_list: header descriptors list + * @len: the size of the above list + * @spinlock: protects the list and its size + * @ep: IPA EP context + * @xmit_eot_cnt: count of pending eot for tasklet to process + * @tasklet: tasklet for eot write_done handle (tx_complete) + * @napi_tx: napi for eot write done handle (tx_complete) - to replace tasklet + * @napi_rx: napi for eot write done handle (rx_complete) - to replace tasklet + * @in_napi_context: an atomic variable used for non-blocking locking, + * preventing from multiple napi_sched to be called. + * @int_modt: GSI event ring interrupt moderation timer + * @int_modc: GSI event ring interrupt moderation counter + * @buff_size: rx packet length + * @page_order: page order of the rx pipe based on the ioctl version + * @ext_ioctl_v2: specifies if it's new version of ingress/egress ioctl + * + * IPA context specific to the GPI pipes a.k.a LAN IN/OUT and WAN + */ +struct ipa3_sys_context { + u32 len; + atomic_t curr_polling_state; + atomic_t workqueue_flushed; + struct delayed_work switch_to_intr_work; + enum ipa3_sys_pipe_policy policy; + bool use_comm_evt_ring; + bool nop_pending; + int (*pyld_hdlr)(struct sk_buff *skb, struct ipa3_sys_context *sys); + struct sk_buff * (*get_skb)(unsigned int len, gfp_t flags); + void (*free_skb)(struct sk_buff *skb); + void (*free_rx_wrapper)(struct ipa3_rx_pkt_wrapper *rk_pkt); + u32 rx_buff_sz; + u32 rx_pool_sz; + struct sk_buff *prev_skb; + unsigned int len_rem; + unsigned int len_pad; + unsigned int len_partial; + bool drop_packet; + struct work_struct work; + struct delayed_work replenish_rx_work; + struct work_struct repl_work; + void (*repl_hdlr)(struct ipa3_sys_context *sys); + struct ipa3_repl_ctx *repl; + u32 pkt_sent; + struct napi_struct *napi_obj; + struct list_head pending_pkts[GSI_VEID_MAX]; + atomic_t xmit_eot_cnt; + struct tasklet_struct tasklet; + bool skip_eot; + u32 eob_drop_cnt; + struct napi_struct napi_tx; + struct napi_struct napi_rx; + bool tx_poll; + bool napi_tx_enable; + atomic_t in_napi_context; + u32 int_modt; + u32 int_modc; + u32 buff_size; + u32 page_order; + bool ext_ioctl_v2; + bool common_buff_pool; + atomic_t page_avilable; + u32 napi_sort_page_thrshld_cnt; + + /* ordering is important - mutable fields go above */ + struct ipa3_ep_context *ep; + struct list_head head_desc_list; + struct list_head rcycl_list; + struct list_head avail_tx_wrapper_list; + u32 avail_tx_wrapper; + spinlock_t spinlock; + struct hrtimer db_timer; + struct workqueue_struct *wq; + struct workqueue_struct *repl_wq; + struct ipa3_status_stats *status_stat; + u32 pm_hdl; + struct ipa3_page_repl_ctx *page_recycle_repl; + struct workqueue_struct *freepage_wq; + struct delayed_work freepage_work; + struct tasklet_struct tasklet_find_freepage; + struct ipa3_sys_context *common_sys; + /* ordering is important - other immutable fields go below */ +}; + +/** + * enum ipa3_desc_type - IPA decriptors type + * + * IPA decriptors type, IPA supports DD and ICD but no CD + */ +enum ipa3_desc_type { + IPA_DATA_DESC, + IPA_DATA_DESC_SKB, + IPA_DATA_DESC_SKB_PAGED, + IPA_IMM_CMD_DESC, +}; + +/** + * struct ipa3_tx_pkt_wrapper - IPA Tx packet wrapper + * @type: specify if this packet is for the skb or immediate command + * @mem: memory buffer used by this Tx packet + * @link: linked to the wrappers on that pipe + * @callback: IPA client provided callback + * @user1: cookie1 for above callback + * @user2: cookie2 for above callback + * @sys: corresponding IPA sys context + * @cnt: 1 for single transfers, + * >1 and <0xFFFF for first of a "multiple" transfer, + * 0xFFFF for last desc, 0 for rest of "multiple' transfer + * @bounce: va of bounce buffer + * @unmap_dma: in case this is true, the buffer will not be dma unmapped + * @xmit_done: flag to indicate the last desc got tx complete on each ieob + * + * This struct can wrap both data packet and immediate command packet. + */ +struct ipa3_tx_pkt_wrapper { + enum ipa3_desc_type type; + struct ipa_mem_buffer mem; + struct list_head link; + void (*callback)(void *user1, int user2); + void *user1; + int user2; + struct ipa3_sys_context *sys; + u32 cnt; + void *bounce; + bool no_unmap_dma; + bool xmit_done; +}; + +/** + * struct ipa3_dma_xfer_wrapper - IPADMA transfer descr wrapper + * @phys_addr_src: physical address of the source data to copy + * @phys_addr_dest: physical address to store the copied data + * @len: len in bytes to copy + * @link: linked to the wrappers list on the proper(sync/async) cons pipe + * @xfer_done: completion object for sync_memcpy completion + * @callback: IPADMA client provided completion callback + * @user1: cookie1 for above callback + * + * This struct can wrap both sync and async memcpy transfers descriptors. + */ +struct ipa3_dma_xfer_wrapper { + u64 phys_addr_src; + u64 phys_addr_dest; + u16 len; + struct list_head link; + struct completion xfer_done; + void (*callback)(void *user1); + void *user1; +}; + +/** + * struct ipa3_desc - IPA descriptor + * @type: skb or immediate command or plain old data + * @pyld: points to skb + * @frag: points to paged fragment + * or kmalloc'ed immediate command parameters/plain old data + * @dma_address: dma mapped address of pyld + * @dma_address_valid: valid field for dma_address + * @is_tag_status: flag for IP_PACKET_TAG_STATUS imd cmd + * @len: length of the pyld + * @opcode: for immediate commands + * @callback: IPA client provided completion callback + * @user1: cookie1 for above callback + * @user2: cookie2 for above callback + * @xfer_done: completion object for sync completion + * @skip_db_ring: specifies whether GSI doorbell should not be rang + */ +struct ipa3_desc { + enum ipa3_desc_type type; + void *pyld; + skb_frag_t *frag; + dma_addr_t dma_address; + bool dma_address_valid; + bool is_tag_status; + u16 len; + u16 opcode; + void (*callback)(void *user1, int user2); + void *user1; + int user2; + struct completion xfer_done; + bool skip_db_ring; +}; + +/** + * struct ipa3_rx_pkt_wrapper - IPA Rx packet wrapper + * @skb: skb + * @dma_address: DMA address of this Rx packet + * @link: linked to the Rx packets on that pipe + * @len: fixed allocated skb length (i.e. times of page size) + * @data_len: how many bytes are copied into skb's flat buffer + */ +struct ipa3_rx_pkt_wrapper { + struct list_head link; + union { + struct ipa_rx_data data; + struct ipa_rx_page_data page_data; + }; + u32 len; + u32 data_len; + struct work_struct work; + struct ipa3_sys_context *sys; +}; + +/** + * struct ipa3_nat_ipv6ct_tmp_mem - NAT/IPv6CT temporary memory + * + * In case NAT/IPv6CT table are destroyed the HW is provided with the + * temporary memory + * + * @vaddr: the address of the temporary memory + * @dma_handle: the handle of the temporary memory + */ +struct ipa3_nat_ipv6ct_tmp_mem { + void *vaddr; + dma_addr_t dma_handle; +}; + +/** + * struct ipa3_nat_ipv6ct_common_mem - IPA NAT/IPv6CT memory device + * @name: the device name + * @lock: memory mutex + * @class: pointer to the struct class + * @dev: the dev_t of the device + * @cdev: cdev of the device + * @dev_num: device number + * @is_nat_mem: is the memory for v4 nat + * @is_ipv6ct_mem: is the memory for v6 nat + * @is_dev_init: flag indicating if device is initialized + * @is_hw_init: flag indicating if the corresponding HW is initialized + * @is_mapped: flag indicating if memory is mapped + * @phys_mem_size: the physical size in the shared memory + * @phys_mem_ofst: the offset in the shared memory + * @table_alloc_size: size (bytes) of table + * @vaddr: the virtual address in the system memory + * @dma_handle: the system memory DMA handle + * @base_address: table virtual address + * @base_table_addr: base table address + * @expansion_table_addr: expansion table address + * @table_entries: num of entries in the base table + * @expn_table_entries: num of entries in the expansion table + * @tmp_mem: temporary memory used to always provide HW with a legal memory + */ +struct ipa3_nat_ipv6ct_common_mem { + char name[IPA_DEV_NAME_MAX_LEN]; + struct mutex lock; + struct class *class; + struct device *dev; + struct cdev cdev; + dev_t dev_num; + + bool is_nat_mem; + bool is_ipv6ct_mem; + + bool is_dev_init; + bool is_hw_init; + bool is_mapped; + + u32 phys_mem_size; + u32 phys_mem_ofst; + size_t table_alloc_size; + + void *vaddr; + dma_addr_t dma_handle; + void *base_address; + char *base_table_addr; + char *expansion_table_addr; + u32 table_entries; + u32 expn_table_entries; + + struct ipa3_nat_ipv6ct_tmp_mem *tmp_mem; +}; + +/** + * struct ipa3_nat_mem_loc_data - memory specific info per table memory type + * @is_mapped: has the memory been mapped? + * @io_vaddr: the virtual address in the sram memory + * @vaddr: the virtual address in the system memory + * @dma_handle: the system memory DMA handle + * @phys_addr: physical sram memory location + * @table_alloc_size: size (bytes) of table + * @table_entries: number of entries in table + * @expn_table_entries: number of entries in expansion table + * @base_address: same as vaddr above + * @base_table_addr: base table address + * @expansion_table_addr: base table's expansion table address + * @index_table_addr: index table address + * @index_table_expansion_addr: index table's expansion table address + */ +struct ipa3_nat_mem_loc_data { + bool is_mapped; + + void __iomem *io_vaddr; + + void *vaddr; + dma_addr_t dma_handle; + + unsigned long phys_addr; + + size_t table_alloc_size; + + u32 table_entries; + u32 expn_table_entries; + + void *base_address; + + char *base_table_addr; + char *expansion_table_addr; + + char *index_table_addr; + char *index_table_expansion_addr; +}; + +/** + * struct ipa3_nat_mem - IPA NAT memory description + * @dev: the memory device structure + * @public_ip_addr: ip address of nat table + * @pdn_mem: pdn config table SW cache memory structure + * @is_tmp_mem_allocated: indicate if tmp mem has been allocated + * @last_alloc_loc: last memory type allocated + * @active_table: which table memory type is currently active + * @switch2ddr_cnt: how many times we've switched focust to ddr + * @switch2sram_cnt: how many times we've switched focust to sram + * @ddr_in_use: is there table in ddr + * @sram_in_use: is there table in sram + * @mem_loc: memory specific info per table memory type + */ +struct ipa3_nat_mem { + struct ipa3_nat_ipv6ct_common_mem dev; /* this item must be first */ + + u32 public_ip_addr; + struct ipa_mem_buffer pdn_mem; + + bool is_tmp_mem_allocated; + + enum ipa3_nat_mem_in last_alloc_loc; + + enum ipa3_nat_mem_in active_table; + u32 switch2ddr_cnt; + u32 switch2sram_cnt; + + bool ddr_in_use; + bool sram_in_use; + + struct ipa3_nat_mem_loc_data mem_loc[IPA_NAT_MEM_IN_MAX]; +}; + +/** + * struct ipa3_ipv6ct_mem - IPA IPv6 connection tracking memory description + * @dev: the memory device structure + */ +struct ipa3_ipv6ct_mem { + struct ipa3_nat_ipv6ct_common_mem dev; /* this item must be first */ +}; + +/** + * enum ipa3_hw_mode - IPA hardware mode + * @IPA_HW_Normal: Regular IPA hardware + * @IPA_HW_Virtual: IPA hardware supporting virtual memory allocation + * @IPA_HW_PCIE: IPA hardware supporting memory allocation over PCIE Bridge + * @IPA_HW_Emulation: IPA emulation hardware + * @IPA_HW_Test: Regular IPA hardware in test mode (for + * kernel-tests) + */ +enum ipa3_hw_mode { + IPA_HW_MODE_NORMAL = 0, + IPA_HW_MODE_VIRTUAL = 1, + IPA_HW_MODE_PCIE = 2, + IPA_HW_MODE_EMULATION = 3, + IPA_HW_MODE_TEST = 4, +}; + +#define IPA_IS_REGULAR_CLK_MODE(hw_mode) \ + ((hw_mode == IPA_HW_MODE_NORMAL) || (hw_mode == IPA_HW_MODE_TEST)) + +/* + * enum ipa3_platform_type - Platform type + * @IPA_PLAT_TYPE_MDM: MDM platform (usually 32bit single core CPU platform) + * @IPA_PLAT_TYPE_MSM: MSM SOC platform (usually 64bit multi-core platform) + * @IPA_PLAT_TYPE_APQ: Similar to MSM but without modem + */ +enum ipa3_platform_type { + IPA_PLAT_TYPE_MDM = 0, + IPA_PLAT_TYPE_MSM = 1, + IPA_PLAT_TYPE_APQ = 2, + IPA_PLAT_TYPE_XR = 3, +}; + +enum ipa3_config_this_ep { + IPA_CONFIGURE_THIS_EP, + IPA_DO_NOT_CONFIGURE_THIS_EP, +}; + +struct ipa3_page_recycle_stats { + u64 total_replenished; + u64 page_recycled; + u64 tmp_alloc; +}; + +struct ipa3_cache_recycle_stats { + u64 pkt_allocd; + u64 pkt_found; + u64 tot_pkt_replenished; +}; + +struct lan_coal_stats { + u64 coal_rx; + u64 coal_left_as_is; + u64 coal_reconstructed; + u64 coal_pkts; + u64 coal_hdr_qmap_err; + u64 coal_hdr_nlo_err; + u64 coal_hdr_pkt_err; + u64 coal_csum_err; + u64 coal_ip_invalid; + u64 coal_trans_invalid; + u64 coal_veid[GSI_VEID_MAX]; + u64 coal_tcp; + u64 coal_tcp_bytes; + u64 coal_udp; + u64 coal_udp_bytes; +}; + +struct ipa3_stats { + u32 tx_sw_pkts; + u32 tx_hw_pkts; + u32 rx_pkts; + u32 rx_excp_pkts[IPAHAL_PKT_STATUS_EXCEPTION_MAX]; + u32 rx_repl_repost; + u32 tx_pkts_compl; + u32 rx_q_len; + u32 msg_w[IPA_EVENT_MAX_NUM]; + u32 msg_r[IPA_EVENT_MAX_NUM]; + u32 stat_compl; + u32 aggr_close; + u32 wan_aggr_close; + u32 wan_rx_empty; + u32 wan_rx_empty_coal; + u32 wan_repl_rx_empty; + u32 rmnet_ll_rx_empty; + u32 rmnet_ll_repl_rx_empty; + u32 lan_rx_empty; + u32 lan_rx_empty_coal; + u32 lan_repl_rx_empty; + u32 low_lat_rx_empty; + u32 low_lat_repl_rx_empty; + u32 flow_enable; + u32 flow_disable; + u32 tx_non_linear; + u32 rx_page_drop_cnt; + u64 lower_order; + u32 pipe_setup_fail_cnt; + struct ipa3_page_recycle_stats page_recycle_stats[3]; + struct ipa3_cache_recycle_stats cache_recycle_stats[3]; + u64 page_recycle_cnt[3][IPA_PAGE_POLL_THRESHOLD_MAX]; + atomic_t num_buff_above_thresh_for_def_pipe_notified; + atomic_t num_buff_above_thresh_for_coal_pipe_notified; + atomic_t num_buff_below_thresh_for_def_pipe_notified; + atomic_t num_buff_below_thresh_for_coal_pipe_notified; + atomic_t num_buff_above_thresh_for_ll_pipe_notified; + atomic_t num_buff_below_thresh_for_ll_pipe_notified; + atomic_t num_free_page_task_scheduled; + struct lan_coal_stats coal; + u64 num_sort_tasklet_sched[3]; + u64 num_of_times_wq_reschd; + u64 page_recycle_cnt_in_tasklet; + u32 ttl_cnt; +}; + +/* offset for each stats */ +#define IPA3_UC_DEBUG_STATS_RINGFULL_OFF (0) +#define IPA3_UC_DEBUG_STATS_RINGEMPTY_OFF (4) +#define IPA3_UC_DEBUG_STATS_RINGUSAGEHIGH_OFF (8) +#define IPA3_UC_DEBUG_STATS_RINGUSAGELOW_OFF (12) +#define IPA3_UC_DEBUG_STATS_RINGUTILCOUNT_OFF (16) +#define IPA3_UC_DEBUG_STATS_OFF (20) +#define IPA3_UC_DEBUG_STATS_TRCOUNT_OFF (20) +#define IPA3_UC_DEBUG_STATS_ERCOUNT_OFF (24) +#define IPA3_UC_DEBUG_STATS_AOSCOUNT_OFF (28) +#define IPA3_UC_DEBUG_STATS_BUSYTIME_OFF (32) +#define IPA3_UC_DEBUG_STATS_RTK_OFF (40) + + +/** + * struct ipa3_uc_dbg_stats - uC dbg stats for offloading + * protocols + * @uc_dbg_stats_ofst: offset to SRAM base + * @uc_dbg_stats_size: stats size for all channels + * @uc_dbg_stats_mmio: mmio offset + */ +struct ipa3_uc_dbg_stats { + u32 uc_dbg_stats_ofst; + u16 uc_dbg_stats_size; + void __iomem *uc_dbg_stats_mmio; +}; + +struct ipa3_active_clients { + struct mutex mutex; + atomic_t cnt; + int bus_vote_idx; +}; + +struct ipa3_wakelock_ref_cnt { + spinlock_t spinlock; + int cnt; +}; + +struct ipa3_tag_completion { + struct completion comp; + atomic_t cnt; +}; + +struct ipa3_controller; + +enum ipa_ees { + IPA_EE_AP = 0, + IPA_EE_Q6 = 1, + IPA_EE_UC = 2, +}; + +/** + * struct ipa3_uc_hdlrs - IPA uC callback functions + * @ipa_uc_loaded_hdlr: Function handler when uC is loaded + * @ipa_uc_event_hdlr: Event handler function + * @ipa3_uc_response_hdlr: Response handler function + * @ipa_uc_event_log_info_hdlr: Log event handler function + * @ipa_uc_holb_enabled_hdlr: Function handler when uC HOLB is enabled + */ +struct ipa3_uc_hdlrs { + void (*ipa_uc_loaded_hdlr)(void); + + void (*ipa_uc_event_hdlr) + (struct IpaHwSharedMemCommonMapping_t *uc_sram_mmio); + + int (*ipa3_uc_response_hdlr) + (struct IpaHwSharedMemCommonMapping_t *uc_sram_mmio, + u32 *uc_status); + + void (*ipa_uc_event_log_info_hdlr) + (struct IpaHwEventLogInfoData_t *uc_event_top_mmio); + + void (*ipa_uc_holb_enabled_hdlr)(void); +}; + +/** + * enum ipa3_hw_flags - flags which defines the behavior of HW + * + * @IPA_HW_FLAG_HALT_SYSTEM_ON_ASSERT_FAILURE: Halt system in case of assert + * failure. + * @IPA_HW_FLAG_NO_REPORT_MHI_CHANNEL_ERORR: Channel error would be reported + * in the event ring only. No event to CPU. + * @IPA_HW_FLAG_NO_REPORT_MHI_CHANNEL_WAKE_UP: No need to report event + * IPA_HW_2_CPU_EVENT_MHI_WAKE_UP_REQUEST + * @IPA_HW_FLAG_WORK_OVER_DDR: Perform all transaction to external addresses by + * QMB (avoid memcpy) + * @IPA_HW_FLAG_NO_REPORT_OOB: If set do not report that the device is OOB in + * IN Channel + * @IPA_HW_FLAG_NO_REPORT_DB_MODE: If set, do not report that the device is + * entering a mode where it expects a doorbell to be rung for OUT Channel + * @IPA_HW_FLAG_NO_START_OOB_TIMER + */ +enum ipa3_hw_flags { + IPA_HW_FLAG_HALT_SYSTEM_ON_ASSERT_FAILURE = 0x01, + IPA_HW_FLAG_NO_REPORT_MHI_CHANNEL_ERORR = 0x02, + IPA_HW_FLAG_NO_REPORT_MHI_CHANNEL_WAKE_UP = 0x04, + IPA_HW_FLAG_WORK_OVER_DDR = 0x08, + IPA_HW_FLAG_NO_REPORT_OOB = 0x10, + IPA_HW_FLAG_NO_REPORT_DB_MODE = 0x20, + IPA_HW_FLAG_NO_START_OOB_TIMER = 0x40 +}; + +/** + * struct ipa3_uc_ctx - IPA uC context + * @uc_inited: Indicates if uC interface has been initialized + * @uc_loaded: Indicates if uC has loaded + * @uc_failed: Indicates if uC has failed / returned an error + * @uc_holb_enabled: Indicates if uC HOLB enable cmd is sent. + * @uc_lock: uC interface lock to allow only one uC interaction at a time + * @uc_spinlock: same as uc_lock but for irq contexts + * @uc_completation: Completion mechanism to wait for uC commands + * @uc_sram_mmio: Pointer to uC mapped memory + * @pending_cmd: The last command sent waiting to be ACKed + * @uc_status: The last status provided by the uC + * @uc_error_type: error type from uC error event + * @uc_error_timestamp: tag timer sampled after uC crashed + * @ipa_use_uc_holb_monitor: Indicates if uC HOLB feature is enabled + * @ipa_holb_monitor: Struct with all info needed for uC HOLB feature + */ +struct ipa3_uc_ctx { + bool uc_inited; + bool uc_loaded; + bool uc_failed; + bool uc_holb_enabled; + struct mutex uc_lock; + spinlock_t uc_spinlock; + struct completion uc_completion; + struct IpaHwSharedMemCommonMapping_t *uc_sram_mmio; + struct IpaHwEventLogInfoData_t *uc_event_top_mmio; + u32 uc_event_top_ofst; + u32 pending_cmd; + u32 uc_status; + u32 uc_error_type; + u32 uc_error_timestamp; + phys_addr_t rdy_ring_base_pa; + phys_addr_t rdy_ring_rp_pa; + u32 rdy_ring_size; + phys_addr_t rdy_comp_ring_base_pa; + phys_addr_t rdy_comp_ring_wp_pa; + u32 rdy_comp_ring_size; + u32 *rdy_ring_rp_va; + u32 *rdy_comp_ring_wp_va; + bool uc_event_ring_valid; + struct ipa_mem_buffer event_ring; + u32 ering_wp_local; + u32 ering_rp_local; + u32 ering_wp; + u32 ering_rp; + bool ipa_use_uc_holb_monitor; + struct ipa_holb_monitor holb_monitor; +}; + +/** + * struct ipa3_uc_wdi_ctx + * @wdi_uc_top_ofst: + * @wdi_uc_top_mmio: + * @wdi_uc_stats_ofst: + * @wdi_uc_stats_mmio: + */ +struct ipa3_uc_wdi_ctx { + /* WDI specific fields */ + u32 wdi_uc_stats_ofst; + struct IpaHwStatsWDIInfoData_t *wdi_uc_stats_mmio; + void *priv; + ipa_uc_ready_cb uc_ready_cb; + /* for AP+STA stats update */ +#ifdef IPA_WAN_MSG_IPv6_ADDR_GW_LEN + ipa_wdi_meter_notifier_cb stats_notify; +#endif +}; + +/** + * struct ipa3_uc_wigig_ctx + * @priv: wigig driver private data + * @uc_ready_cb: wigig driver uc ready callback + * @int_notify: wigig driver misc interrupt callback + */ +struct ipa3_uc_wigig_ctx { + void *priv; + ipa_uc_ready_cb uc_ready_cb; + ipa_wigig_misc_int_cb misc_notify_cb; +}; + +/** + * struct ipa3_wdi2_ctx - IPA wdi2 context + */ +struct ipa3_wdi2_ctx { + phys_addr_t rdy_ring_base_pa; + phys_addr_t rdy_ring_rp_pa; + u32 rdy_ring_size; + phys_addr_t rdy_comp_ring_base_pa; + phys_addr_t rdy_comp_ring_wp_pa; + u32 rdy_comp_ring_size; + u32 *rdy_ring_rp_va; + u32 *rdy_comp_ring_wp_va; + struct ipa3_uc_dbg_stats dbg_stats; +}; + +/** + * struct ipa3_wdi3_ctx - IPA wdi3 context + */ +struct ipa3_wdi3_ctx { + struct ipa3_uc_dbg_stats dbg_stats; +}; + +/** + * struct ipa3_usb_ctx - IPA usb context + */ +struct ipa3_usb_ctx { + struct ipa3_uc_dbg_stats dbg_stats; +}; + +/** + * struct ipa3_mhip_ctx - IPA mhip context + */ +struct ipa3_mhip_ctx { + struct ipa3_uc_dbg_stats dbg_stats; +}; + +/** + * struct ipa3_aqc_ctx - IPA aqc context + */ +struct ipa3_aqc_ctx { + struct ipa3_uc_dbg_stats dbg_stats; +}; + +/** + * struct ipa3_rtk_ctx - IPA rtk context + */ +struct ipa3_rtk_ctx { + struct ipa3_uc_dbg_stats dbg_stats; +}; + +/** +* struct ipa3_ntn_ctx - IPA ntn context +*/ +struct ipa3_ntn_ctx { + struct ipa3_uc_dbg_stats dbg_stats; +}; + +/** + * struct ipa3_transport_pm - transport power management related members + * @transport_pm_mutex: Mutex to protect the transport_pm functionality. + */ +struct ipa3_transport_pm { + atomic_t dec_clients; + atomic_t eot_activity; + struct mutex transport_pm_mutex; +}; + +/** + * struct ipa3cm_client_info - the client-info indicated from IPACM + * @ipacm_client_enum: the enum to indicate tether-client + * @ipacm_client_uplink: the bool to indicate pipe for uplink + */ +struct ipa3cm_client_info { + enum ipacm_client_enum client_enum; + bool uplink; +}; + +/** + * struct ipacm_fnr_info - the fnr-info indicated from IPACM + * @ipacm_client_enum: the enum to indicate tether-client + * @ipacm_client_uplink: the bool to indicate pipe for uplink + */ +struct ipacm_fnr_info { + bool valid; + uint8_t hw_counter_offset; + uint8_t sw_counter_offset; +}; + +struct ipa3_smp2p_info { + u32 out_base_id; + u32 in_base_id; + bool ipa_clk_on; + bool res_sent; + unsigned int smem_bit; + struct qcom_smem_state *smem_state; +}; + +struct ipa_dma_task_info { + struct ipa_mem_buffer mem; + struct ipahal_imm_cmd_pyld *cmd_pyld; +}; + +struct ipa_quota_stats { + u64 num_ipv4_bytes; + u64 num_ipv6_bytes; + u32 num_ipv4_pkts; + u32 num_ipv6_pkts; +}; + +struct ipa_quota_stats_all { + struct ipa_quota_stats client[IPA5_PIPES_NUM]; +}; + +struct ipa_drop_stats { + u32 drop_packet_cnt; + u32 drop_byte_cnt; +}; + +struct ipa_drop_stats_all { + struct ipa_drop_stats client[IPA_CLIENT_MAX]; +}; + +struct ipa_hw_stats_quota { + struct ipahal_stats_init_quota init; + struct ipa_quota_stats_all stats; +}; + +struct ipa_hw_stats_teth { + struct ipahal_stats_init_tethering init; + struct ipa_quota_stats_all prod_stats_sum[IPA5_PIPES_NUM]; + struct ipa_quota_stats_all prod_stats[IPA5_PIPES_NUM]; +}; + +struct ipa_hw_stats_flt_rt { + struct ipahal_stats_init_flt_rt flt_v4_init; + struct ipahal_stats_init_flt_rt flt_v6_init; + struct ipahal_stats_init_flt_rt rt_v4_init; + struct ipahal_stats_init_flt_rt rt_v6_init; +}; + +struct ipa_hw_stats_drop { + struct ipahal_stats_init_drop init; + struct ipa_drop_stats_all stats; +}; + +struct ipa_hw_stats { + bool enabled; + struct ipa_hw_stats_quota quota; + struct ipa_hw_stats_teth teth; + struct ipa_hw_stats_flt_rt flt_rt; + struct ipa_hw_stats_drop drop; + bool teth_stats_enabled; +}; + +struct ipa_cne_evt { + struct ipa_wan_msg wan_msg; + struct ipa_msg_meta msg_meta; +}; + +enum ipa_smmu_cb_type { + IPA_SMMU_CB_AP, + IPA_SMMU_CB_WLAN, + IPA_SMMU_CB_WLAN1, + IPA_SMMU_CB_UC, + IPA_SMMU_CB_11AD, + IPA_SMMU_CB_ETH, + IPA_SMMU_CB_ETH1, + IPA_SMMU_CB_RTP, + IPA_SMMU_CB_MAX +}; + +#define VALID_IPA_SMMU_CB_TYPE(t) \ + ((t) >= IPA_SMMU_CB_AP && (t) < IPA_SMMU_CB_MAX) + +enum ipa_client_cb_type { + IPA_USB_CLNT, + IPA_MHI_CLNT, + IPA_MAX_CLNT +}; + +/** + * struct ipa_flt_rt_counter - IPA flt rt counters management + * @hdl: idr structure to manage hdl per request + * @used_hw: boolean array to track used hw counters + * @used_sw: boolean array to track used sw counters + * @hdl_lock: spinlock for flt_rt handle + */ +struct ipa_flt_rt_counter { + struct idr hdl; + bool used_hw[IPA_FLT_RT_HW_COUNTER]; + bool used_sw[IPA_FLT_RT_SW_COUNTER]; + spinlock_t hdl_lock; +}; + +/** + * struct ipa3_char_device_context - IPA character device + * @class: pointer to the struct class + * @dev_num: device number + * @dev: the dev_t of the device + * @cdev: cdev of the device + */ +struct ipa3_char_device_context { + struct class *class; + dev_t dev_num; + struct device *dev; + struct cdev cdev; +}; + +struct ipa3_pc_mbox_data { + struct mbox_client mbox_client; + struct mbox_chan *mbox; +}; + +enum ipa_fw_load_state { + IPA_FW_LOAD_STATE_INIT, + IPA_FW_LOAD_STATE_FWFILE_READY, + IPA_FW_LOAD_STATE_SMMU_DONE, + IPA_FW_LOAD_STATE_LOAD_READY, + IPA_FW_LOAD_STATE_LOADED, +}; + +enum ipa_fw_load_event { + IPA_FW_LOAD_EVNT_FWFILE_READY, + IPA_FW_LOAD_EVNT_SMMU_DONE, +}; + +struct ipa_fw_load_data { + enum ipa_fw_load_state state; + struct mutex lock; +}; + +struct ipa3_app_clock_vote { + struct mutex mutex; + u32 cnt; +}; + +struct ipa_eth_client_mapping { + enum ipa_client_type type; + int pipe_id; + int pipe_hdl; + int ch_id; + bool valid; +}; + +struct ipa3_eth_info { + u8 num_ch; + struct ipa_eth_client_mapping map[IPA_MAX_CH_STATS_SUPPORTED]; +}; + +struct ipa3_eth_error_stats { + int rp; + int wp; + u32 err; +}; + +struct ipa_ntn3_stats_rx { + int rp; + int wp; + bool pending_db_after_rollback; + u32 msi_db_idx; + u32 chain_cnt; + u32 err_cnt; + u32 tres_handled; + u32 rollbacks_cnt; + u32 msi_db_cnt; +}; + +struct ipa_ntn3_stats_tx { + int rp; + int wp; + bool pending_db_after_rollback; + u32 msi_db_idx; + u32 derr_cnt; + u32 oob_cnt; + u32 tres_handled; + u32 rollbacks_cnt; + u32 msi_db_cnt; +}; + +struct ipa_ntn3_client_stats { + struct ipa_ntn3_stats_rx rx_stats; + struct ipa_ntn3_stats_tx tx_stats; +}; +#if defined(CONFIG_IPA_TSP) +struct ipa3_tsp_ctx { + u8 ingr_tc_max; + u8 egr_ep_max; + u8 egr_tc_max; + enum ipa_client_type *egr_ep_config; + u32 egr_tc_range_mask; + struct ipa_mem_buffer ingr_tc_tbl; + struct ipa_mem_buffer egr_ep_tbl; + struct ipa_mem_buffer egr_tc_tbl; + struct ipa_mem_buffer qm_tlv_mem; +}; +#endif + +#if IS_ENABLED(CONFIG_QCOM_VA_MINIDUMP) +struct ipa_minidump_data { + struct list_head entry; + struct va_md_entry data; +}; +#endif + +struct ipa_notifier_block_data { + struct list_head entry; + struct notifier_block ipa_rmnet_notifier; +}; + +/* Peripheral stats for Q6, should be in the same order, defined by Q6 */ +enum ipa_per_stats_type_e { + IPA_PER_STATS_TYPE_NUM_PERS, + IPA_PER_STATS_TYPE_NUM_PERS_WWAN, + IPA_PER_STATS_TYPE_ACT_PER_TYPE, + IPA_PER_STATS_TYPE_PCIE_GEN, + IPA_PER_STATS_TYPE_PCIE_WIDTH, + IPA_PER_STATS_TYPE_PCIE_MAX_SPEED, + IPA_PER_STATS_TYPE_PCIE_NUM_LPM, + IPA_PER_STATS_TYPE_USB_TYPE, + IPA_PER_STATS_TYPE_USB_PROT, + IPA_PER_STATS_TYPE_USB_MAX_SPEED, + IPA_PER_STATS_TYPE_USB_PIPO, + IPA_PER_STATS_TYPE_WIFI_ENUM_TYPE, + IPA_PER_STATS_TYPE_WIFI_MAX_SPEED, + IPA_PER_STATS_TYPE_WIFI_DUAL_BAND_EN, + IPA_PER_STATS_TYPE_ETH_CLIENT, + IPA_PER_STATS_TYPE_ETH_MAX_SPEED, + IPA_PER_STATS_TYPE_IPA_DMA_BYTES, + IPA_PER_STATS_TYPE_WIFI_HOLB_UC, + IPA_PER_STATS_TYPE_ETH_HOLB_UC, + IPA_PER_STATS_TYPE_USB_HOLB_UC, + IPA_PER_STATS_TYPE_MAX +}; + +enum ipa_per_type_bitmask_e { + IPA_PER_TYPE_BITMASK_NONE = 0, + IPA_PER_TYPE_BITMASK_PCIE_EP = 1, + IPA_PER_TYPE_BITMASK_USB = 2, + IPA_PER_TYPE_BITMASK_WIFI = 4, + IPA_PER_TYPE_BITMASK_ETH = 8 +}; + +enum ipa_per_pcie_speed_type_e { + PCIE_LINK_SPEED_DEF = 0, /** < -- Core's default speed */ + PCIE_LINK_SPEED_GEN1 = 1, /** < -- Gen1 Speed - 2.5GT/s */ + PCIE_LINK_SPEED_GEN2 = 2, /** < -- Gen2 Speed - 5.0GT/s */ + PCIE_LINK_SPEED_GEN3 = 3, /** < -- Gen3 Speed - 8.0GT/s */ + PCIE_LINK_SPEED_GEN4 = 4 /** < -- Gen4 Speed - 16.0GT/s*/ +}; + +enum ipa_per_pcie_width_type_e { + PCIE_LINK_WIDTH_DEF = 0, /** < -- Link Width Default */ + PCIE_LINK_WIDTH_X1 = 1, /** < -- Link Width x1 */ + PCIE_LINK_WIDTH_X2 = 2, /** < -- Link Width x2 */ + PCIE_LINK_WIDTH_X4 = 4, /** < -- Link Width x4 */ + PCIE_LINK_WIDTH_X8 = 8, /** < -- Link Width x8 */ + PCIE_LINK_WIDTH_X16 = 16, /** < -- Link Width x16 */ + PCIE_LINK_WIDTH_MAX = 32 /** < -- Link Width Max */ +}; + +enum ipa_per_usb_prot_type_e { + IPA_PER_USB_PROT_TYPE_INVALID, + IPA_PER_USB_PROT_TYPE_RMNET, + IPA_PER_USB_PROT_TYPE_RNDIS, + IPA_PER_USB_PROT_TYPE_ECM, + IPA_PER_USB_PROT_TYPE_MAX +}; + +enum ipa_per_wifi_enum_type_e { + IPA_PER_WIFI_ENUM_TYPE_INVALID, + IPA_PER_WIFI_ENUM_TYPE_802_11_ABG, + IPA_PER_WIFI_ENUM_TYPE_802_11_AC, + IPA_PER_WIFI_ENUM_TYPE_802_11_AD, + IPA_PER_WIFI_ENUM_TYPE_802_11_AX, + IPA_PER_WIFI_ENUM_TYPE_MAX +}; + +enum ipa_per_usb_enum_type_e { + IPA_PER_USB_ENUM_TYPE_INVALID, + IPA_PER_USB_ENUM_TYPE_FS, + IPA_PER_USB_ENUM_TYPE_2_0_HS, + IPA_PER_USB_ENUM_TYPE_SS_GEN_1, + IPA_PER_USB_ENUM_TYPE_SS_GEN_2, + IPA_PER_USB_ENUM_TYPE_SS_GEN_2x2, + IPA_PER_USB_ENUM_TYPE_MAX +}; + +/** + * struct ipa3_context - IPA context + * @cdev: cdev context + * @ep: list of all end points + * @skip_ep_cfg_shadow: state to update filter table correctly across power-save + * @ep_flt_bitmap: End-points supporting filtering bitmap + * @ep_flt_num: End-points supporting filtering number + * @resume_on_connect: resume ep on ipa connect + * @flt_tbl: list of all IPA filter tables + * @flt_rule_ids: idr structure that holds the rule_id for each rule + * @mode: IPA operating mode + * @mmio: iomem + * @ipa_wrapper_base: IPA wrapper base address + * @ipa_wrapper_size: size of the memory pointed to by ipa_wrapper_base + * @ipa_cfg_offset: offset from IPA_WRAPPER_BASE to IPA registers + * @hdr_tbl: IPA header table + * @hdr_proc_ctx_tbl: IPA processing context table + * @rt_tbl_set: list of routing tables each of which is a list of rules + * @reap_rt_tbl_set: list of sys mem routing tables waiting to be reaped + * @flt_rule_cache: filter rule cache + * @rt_rule_cache: routing rule cache + * @hdr_cache: header cache + * @hdr_offset_cache: header offset cache + * @fnr_stats_cache: FnR stats cache + * @hdr_proc_ctx_cache: processing context cache + * @hdr_proc_ctx_offset_cache: processing context offset cache + * @rt_tbl_cache: routing table cache + * @tx_pkt_wrapper_cache: Tx packets cache + * @rx_pkt_wrapper_cache: Rx packets cache + * @rt_idx_bitmap: routing table index bitmap + * @lock: this does NOT protect the linked lists within ipa3_sys_context + * @smem_sz: shared memory size available for SW use starting + * from non-restricted bytes + * @smem_restricted_bytes: the bytes that SW should not use in the shared mem + * @nat_mem: NAT memory + * @ipv6ct_mem: IPv6CT memory + * @excp_hdr_hdl: exception header handle + * @dflt_v4_rt_rule_hdl: default v4 routing rule handle + * @dflt_v6_rt_rule_hdl: default v6 routing rule handle + * @aggregation_type: aggregation type used on USB client endpoint + * @aggregation_byte_limit: aggregation byte limit used on USB client endpoint + * @aggregation_time_limit: aggregation time limit used on USB client endpoint + * @hdr_proc_ctx_tbl_lcl: where proc_ctx tbl resides true-local, false-system + * @hdr_mem: header memory + * @hdr_proc_ctx_mem: processing context memory + * @ip4_rt_tbl_lcl: where ip4 rt tables reside 1-local; 0-system + * @ip6_rt_tbl_lcl: where ip6 rt tables reside 1-local; 0-system + * @ip4_flt_tbl_lcl: where ip4 flt tables reside 1-local; 0-system + * @ip6_flt_tbl_lcl: where ip6 flt tables reside 1-local; 0-system + * @power_mgmt_wq: workqueue for power management + * @transport_power_mgmt_wq: workqueue transport related power management + * @tag_process_before_gating: indicates whether to start tag process before + * gating IPA clocks + * @transport_pm: transport power management related information + * @disconnect_lock: protects LAN_CONS packet receive notification CB + * @ipa3_active_clients: structure for reference counting connected IPA clients + * @ipa_hw_type: type of IPA HW type (e.g. IPA 1.0, IPA 1.1 etc') + * @ipa_hw_type_index: index of IPA HW type (e.g. IPA_4_0, IPA_4_0_MHI etc') + * @ipa3_hw_mode: mode of IPA HW mode (e.g. Normal, Virtual or over PCIe) + * @gsi_ver: version of GSI + * @use_ipa_teth_bridge: use tethering bridge driver + * @modem_cfg_emb_pipe_flt: modem configure embedded pipe filtering rules + * @logbuf: ipc log buffer for high priority messages + * @logbuf_low: ipc log buffer for low priority messages + * @logbuf_clk: ipc log buffer for ipa clock messages + * @ipa_wdi2: using wdi-2.0 + * @ipa_config_is_auto: is this AUTO use case + * @ipa_fltrt_not_hashable: filter/route rules not hashable + * @use_xbl_boot: use xbl loading for IPA FW + * @use_64_bit_dma_mask: using 64bits dma mask + * @ctrl: holds the core specific operations based on + * core version (vtable like) + * @pkt_init_imm_opcode: opcode for IP_PACKET_INIT imm cmd + * @enable_clock_scaling: clock scaling is enabled ? + * @curr_ipa_clk_rate: IPA current clock rate + * @wcstats: wlan common buffer stats + * @uc_ctx: uC interface context + * @uc_wdi_ctx: WDI specific fields for uC interface + * @uc_wigig_ctx: WIGIG specific fields for uC interface + * @ipa_num_pipes: The number of pipes used by IPA HW + * @skip_uc_pipe_reset: Indicates whether pipe reset via uC needs to be avoided + * @mpm_ring_size_dl_cache: To cache the dl ring size configured previously + * @mpm_ring_size_dl: MHIP all DL pipe's ring size + * @mpm_ring_size_ul_cache: To cache the ul ring size configured previously + * @mpm_ring_size_ul: MHIP all UL pipe's ring size + * @mpm_teth_aggr_size: MHIP teth aggregation byte size + * @mpm_uc_thresh: uc threshold for enabling uc flow control + * @ipa_client_apps_wan_cons_agg_gro: RMNET_IOCTL_INGRESS_FORMAT_AGG_DATA + * @apply_rg10_wa: Indicates whether to use register group 10 workaround + * @gsi_ch20_wa: Indicates whether to apply GSI physical channel 20 workaround + * @w_lock: Indicates the wakeup source. + * @wakelock_ref_cnt: Indicates the number of times wakelock is acquired + * @ipa_initialization_complete: Indicates that IPA is fully initialized + * @ipa_ready_cb_list: A list of all the clients who require a CB when IPA + * driver is ready/initialized. + * @init_completion_obj: Completion object to be used in case IPA driver hasn't + * @mhi_evid_limits: MHI event rings start and end ids + * finished initializing. Example of use - IOCTLs to /dev/ipa + * @flt_rt_counters: the counters usage info for flt rt stats + * @wdi3_ctx: IPA wdi3 context + * @gsi_info: channel/protocol info for GSI offloading uC stats + * @app_vote: holds userspace application clock vote count + * IPA context - holds all relevant info about IPA driver and its state + * @lan_rx_napi_enable: flag if NAPI is enabled on the LAN dp + * @generic_ndev: dummy netdev for LAN rx NAPI and tx NAPI + * @napi_lan_rx: NAPI object for LAN rx + * @ipa_wan_skb_page - page recycling enabled on wwan data path + * @icc_num_cases - number of icc scaling level supported + * @icc_num_paths - number of paths icc would vote for bw + * @icc_clk - table for icc bw clock value + * @coal_cmd_pyld: holds the coslescing close frame command payload + * @ipa_gpi_event_rp_ddr: use DDR to access event RP for GPI channels + * @rmnet_ctl_enable: enable pipe support fow low latency data + * @rmnet_ll_enable: enable pipe support fow low latency data + * @gsi_fw_file_name: GSI IPA fw file name + * @uc_fw_file_name: uC IPA fw file name + * @eth_info: ethernet client mapping + * @max_num_smmu_cb: number of smmu s1 cb supported + * @non_hash_flt_lcl_sys_switch: number of times non-hash flt table moved + * mhi_ctrl_state: state of mhi ctrl pipes + * @per_stats_smem_pa: Peripheral stats physical address to be passed to Q6 + * @per_stats_smem_va: Peripheral stats virtual address to update stats from Apps + */ +struct ipa3_context { + bool coal_stopped; + struct ipa3_char_device_context cdev; + struct ipa3_ep_context ep[IPA5_MAX_NUM_PIPES]; + bool skip_ep_cfg_shadow[IPA5_MAX_NUM_PIPES]; + u64 ep_flt_bitmap; + u32 ep_flt_num; + bool resume_on_connect[IPA_CLIENT_MAX]; + struct ipa3_flt_tbl flt_tbl[IPA5_MAX_NUM_PIPES][IPA_IP_MAX]; + struct idr flt_rule_ids[IPA_IP_MAX]; + void __iomem *mmio; + u32 ipa_wrapper_base; + u32 ipa_wrapper_size; + u32 ipa_cfg_offset; + bool set_evict_reg; + struct ipa3_hdr_tbl hdr_tbl[HDR_TBLS_TOTAL]; + struct ipa3_hdr_proc_ctx_tbl hdr_proc_ctx_tbl; + struct ipa3_rt_tbl_set rt_tbl_set[IPA_IP_MAX]; + struct ipa3_rt_tbl_set reap_rt_tbl_set[IPA_IP_MAX]; + struct kmem_cache *flt_rule_cache; + struct kmem_cache *rt_rule_cache; + struct kmem_cache *hdr_cache; + struct kmem_cache *hdr_offset_cache; + struct kmem_cache *fnr_stats_cache; + struct kmem_cache *hdr_proc_ctx_cache; + struct kmem_cache *hdr_proc_ctx_offset_cache; + struct kmem_cache *rt_tbl_cache; + struct kmem_cache *tx_pkt_wrapper_cache; + struct kmem_cache *rx_pkt_wrapper_cache; + unsigned long rt_idx_bitmap[IPA_IP_MAX]; + struct mutex lock; + u16 smem_sz; + u16 smem_restricted_bytes; + u16 smem_reqd_sz; + struct ipa3_nat_mem nat_mem; + struct ipa3_ipv6ct_mem ipv6ct_mem; + u32 excp_hdr_hdl; + u32 dflt_v4_rt_rule_hdl; + u32 dflt_v6_rt_rule_hdl; + uint aggregation_type; + uint aggregation_byte_limit; + uint aggregation_time_limit; + bool hdr_proc_ctx_tbl_lcl; + struct ipa_mem_buffer hdr_sys_mem; + struct ipa_mem_buffer hdr_proc_ctx_mem; + bool rt_tbl_hash_lcl[IPA_IP_MAX]; + bool rt_tbl_nhash_lcl[IPA_IP_MAX]; + bool flt_tbl_hash_lcl[IPA_IP_MAX]; + bool flt_tbl_nhash_lcl[IPA_IP_MAX]; + struct list_head flt_tbl_nhash_lcl_list[IPA_IP_MAX]; + struct ipa3_active_clients ipa3_active_clients; + struct ipa3_active_clients_log_ctx ipa3_active_clients_logging; + struct workqueue_struct *power_mgmt_wq; + struct workqueue_struct *transport_power_mgmt_wq; + bool tag_process_before_gating; + struct ipa3_transport_pm transport_pm; + unsigned long gsi_evt_comm_hdl; + u32 gsi_evt_comm_ring_rem; + u32 clnt_hdl_cmd; + u32 clnt_hdl_data_in; + u32 clnt_hdl_data_out; + spinlock_t disconnect_lock; + u8 a5_pipe_index; + struct list_head intf_list; + struct list_head msg_list; + struct list_head pull_msg_list; + struct mutex msg_lock; + struct list_head msg_wlan_client_list; + struct mutex msg_wlan_client_lock; + wait_queue_head_t msg_waitq; + enum ipa_hw_type ipa_hw_type; + u8 hw_type_index; + enum ipa3_hw_mode ipa3_hw_mode; + enum gsi_ver gsi_ver; + enum ipa3_platform_type platform_type; + bool ipa_config_is_mhi; + bool use_ipa_teth_bridge; + bool modem_cfg_emb_pipe_flt; + bool ipa_wdi2; + bool ipa_config_is_auto; + bool ipa_wdi2_over_gsi; + bool ipa_wdi3_over_gsi; + bool ipa_wdi_opt_dpath; + atomic_t ipa_xr_wdi_flt_rsv_status; + struct completion ipa_xr_wdi_flt_rsrv_success; + u8 rtp_stream_id_cnt; + u32 rtp_proc_hdls[MAX_STREAMS]; + u32 rtp_rt4_tbl_hdls[MAX_STREAMS]; + u32 rtp_rt4_tbl_idxs[MAX_STREAMS]; + u32 rtp_rt4_rule_hdls[MAX_STREAMS]; + bool ipa_endp_delay_wa; + bool lan_coal_enable; + bool ipa_fltrt_not_hashable; + bool use_xbl_boot; + bool use_64_bit_dma_mask; + /* featurize if memory footprint becomes a concern */ + struct ipa3_stats stats; + void *smem_pipe_mem; + void *logbuf; + void *logbuf_low; + void *logbuf_clk; + struct ipa3_controller *ctrl; + struct idr ipa_idr; + struct platform_device *master_pdev; + struct device *pdev; + struct device *uc_pdev; + struct device *rtp_pdev; + spinlock_t idr_lock; + u32 enable_clock_scaling; + u32 enable_napi_chain; + u32 curr_ipa_clk_rate; + bool q6_proxy_clk_vote_valid; + struct mutex q6_proxy_clk_vote_mutex; + u32 q6_proxy_clk_vote_cnt; + u32 ipa_num_pipes; + dma_addr_t pkt_init_imm[IPA5_MAX_NUM_PIPES]; + u32 pkt_init_imm_opcode; + + struct ipa3_wlan_comm_memb wc_memb; + + struct ipa3_uc_ctx uc_ctx; + + struct ipa3_uc_wdi_ctx uc_wdi_ctx; + struct ipa3_uc_ntn_ctx uc_ntn_ctx; + struct ipa3_uc_wigig_ctx uc_wigig_ctx; + u32 wan_rx_ring_size; + u32 lan_rx_ring_size; + bool skip_uc_pipe_reset; + int mpm_ring_size_dl; + int mpm_ring_size_dl_cache; + int mpm_ring_size_ul_cache; + int mpm_ring_size_ul; + int mpm_teth_aggr_size; + int mpm_uc_thresh; + unsigned long gsi_dev_hdl; + u32 ee; + bool apply_rg10_wa; + bool gsi_ch20_wa; + bool s1_bypass_arr[IPA_SMMU_CB_MAX]; + u32 wdi_map_cnt; + struct wakeup_source *w_lock; + struct ipa3_wakelock_ref_cnt wakelock_ref_cnt; + /* RMNET_IOCTL_INGRESS_FORMAT_AGG_DATA */ + bool ipa_client_apps_wan_cons_agg_gro; + /* M-release support to know client pipes */ + struct ipa3cm_client_info ipacm_client[IPA5_MAX_NUM_PIPES]; + bool tethered_flow_control; + bool ipa_initialization_complete; + struct list_head ipa_ready_cb_list; + struct completion init_completion_obj; + struct completion uc_loaded_completion_obj; + struct ipa3_smp2p_info smp2p_info; + u32 mhi_evid_limits[2]; /* start and end values */ + u32 ipa_tz_unlock_reg_num; + struct ipa_tz_unlock_reg_info *ipa_tz_unlock_reg; + struct ipa_dma_task_info dma_task_info; + struct ipa_hw_stats *hw_stats; + struct ipa_flt_rt_counter flt_rt_counters; + struct ipa_cne_evt ipa_cne_evt_req_cache[IPA_MAX_NUM_REQ_CACHE]; + int num_ipa_cne_evt_req; + struct mutex ipa_cne_evt_lock; + bool vlan_mode_iface[IPA_VLAN_IF_MAX]; + bool wdi_over_pcie; + u32 entire_ipa_block_size; + bool do_register_collection_on_crash; + bool do_testbus_collection_on_crash; + bool do_non_tn_collection_on_crash; + bool do_ram_collection_on_crash; + u32 secure_debug_check_action; + u32 sd_state; + void __iomem *reg_collection_base; + struct ipa3_wdi2_ctx wdi2_ctx; + struct ipa3_pc_mbox_data pc_mbox; + struct ipa3_wdi3_ctx wdi3_ctx; + struct ipa3_usb_ctx usb_ctx; + struct ipa3_mhip_ctx mhip_ctx; + struct ipa3_aqc_ctx aqc_ctx; + struct ipa3_rtk_ctx rtk_ctx; + struct ipa3_ntn_ctx ntn_ctx; +#if defined(CONFIG_IPA_TSP) + struct ipa3_tsp_ctx tsp; +#endif + atomic_t ipa_clk_vote; + + int (*client_lock_unlock[IPA_MAX_CLNT])(bool is_lock); + + struct ipa_fw_load_data fw_load_data; + + bool (*get_teth_port_state[IPA_MAX_CLNT])(void); + + atomic_t is_ssr; + bool deepsleep; + void *subsystem_get_retval; + struct IpaHwOffloadStatsAllocCmdData_t + gsi_info[IPA_HW_PROTOCOL_MAX]; + bool ipa_wan_skb_page; + struct ipacm_fnr_info fnr_info; + /* dummy netdev for lan RX NAPI */ + bool lan_rx_napi_enable; + bool tx_napi_enable; + bool tx_poll; + struct net_device generic_ndev; + struct napi_struct napi_lan_rx; + u32 icc_num_cases; + u32 icc_num_paths; + u32 icc_clk[IPA_ICC_LVL_MAX][IPA_ICC_PATH_MAX][IPA_ICC_TYPE_MAX]; +#define WAN_COAL_SUB 0 +#define LAN_COAL_SUB 1 +#define ULSO_COAL_SUB 2 +#define MAX_CCP_SUB (ULSO_COAL_SUB + 1) + struct ipahal_imm_cmd_pyld *coal_cmd_pyld[MAX_CCP_SUB]; + struct ipa_mem_buffer ulso_wa_cmd; + u32 tx_wrapper_cache_max_size; + u32 ipa_gen_rx_cmn_page_pool_sz_factor; + u32 ipa_gen_rx_cmn_temp_pool_sz_factor; + u32 ipa_gen_rx_ll_pool_sz_factor; + struct ipa3_app_clock_vote app_clock_vote; + bool clients_registered; + bool ipa_gpi_event_rp_ddr; + bool rmnet_ctl_enable; + bool rmnet_ll_enable; + char *gsi_fw_file_name; + char *uc_fw_file_name; + struct ipa3_eth_info + eth_info[IPA_ETH_CLIENT_MAX][IPA_ETH_INST_ID_MAX]; + u32 ipa_wan_aggr_pkt_cnt; + bool ipa_mhi_proxy; + u32 num_smmu_cb_probed; + u32 max_num_smmu_cb; + u32 ipa_wdi3_2g_holb_timeout; + u32 ipa_wdi3_5g_holb_timeout; + bool is_wdi3_tx1_needed; + bool ipa_endp_delay_wa_v2; + u32 pkt_init_ex_imm_opcode; + struct ipa_mem_buffer pkt_init_mem; + struct ipa_mem_buffer pkt_init_ex_mem; + struct ipa_mem_buffer pkt_init_ex_imm[IPA_IMM_IP_PACKET_INIT_EX_CMD_NUM]; + bool is_modem_up; + bool ulso_supported; + u16 ulso_ip_id_min; + u16 ulso_ip_id_max; + bool use_pm_wrapper; + u8 page_poll_threshold; + bool wan_common_page_pool; + bool use_tput_est_ep; + struct ipa_ioc_eogre_info eogre_cache; + bool eogre_enabled; + bool is_device_crashed; + bool ulso_wa; + u64 gsi_msi_addr; + spinlock_t notifier_lock; + struct raw_notifier_head *ipa_rmnet_notifier_list_internal; + struct list_head notifier_block_list_head; + bool ipa_rmnet_notifier_enabled; + bool buff_above_thresh_for_def_pipe_notified; + bool buff_above_thresh_for_coal_pipe_notified; + bool buff_above_thresh_for_ll_pipe_notified; + bool buff_below_thresh_for_def_pipe_notified; + bool buff_below_thresh_for_coal_pipe_notified; + bool buff_below_thresh_for_ll_pipe_notified; + bool free_page_task_scheduled; + u8 mhi_ctrl_state; + struct ipa_mem_buffer uc_act_tbl; + bool uc_act_tbl_valid; + struct mutex act_tbl_lock; + int uc_act_tbl_total; + int uc_act_tbl_next_index; + int ipa_pil_load; + u32 ipa_max_napi_sort_page_thrshld; + u32 page_wq_reschd_time; + bool coal_ipv4_id_ignore; + struct list_head minidump_list_head; + phys_addr_t per_stats_smem_pa; + void *per_stats_smem_va; + u32 ipa_smem_size; + bool is_dual_pine_config; + struct workqueue_struct *collect_recycle_stats_wq; + struct ipa_lnx_pipe_page_recycling_stats recycle_stats; + struct ipa3_page_recycle_stats prev_coal_recycle_stats; + struct ipa3_page_recycle_stats prev_default_recycle_stats; + struct ipa3_page_recycle_stats prev_low_lat_data_recycle_stats; + struct mutex recycle_stats_collection_lock; + struct mutex ssr_lock; +}; + +struct ipa3_plat_drv_res { + bool use_ipa_teth_bridge; + u32 ipa_mem_base; + u32 ipa_mem_size; + u32 transport_mem_base; + u32 transport_mem_size; + u32 ipa_cfg_offset; + u32 emulator_intcntrlr_mem_base; + u32 emulator_intcntrlr_mem_size; + u32 emulator_irq; + u32 ipa_irq; + u32 transport_irq; + u32 ipa_pipe_mem_start_ofst; + u32 ipa_pipe_mem_size; + enum ipa_hw_type ipa_hw_type; + enum ipa3_hw_mode ipa3_hw_mode; + enum ipa3_platform_type platform_type; + u32 ee; + bool modem_cfg_emb_pipe_flt; + bool ipa_wdi2; + bool ipa_config_is_auto; + bool ipa_wdi2_over_gsi; + bool ipa_wdi3_over_gsi; + bool ipa_fltrt_not_hashable; + bool use_xbl_boot; + bool use_64_bit_dma_mask; + bool use_bw_vote; + u32 wan_rx_ring_size; + u32 lan_rx_ring_size; + bool skip_uc_pipe_reset; + bool apply_rg10_wa; + bool gsi_ch20_wa; + bool tethered_flow_control; + bool lan_rx_napi_enable; + bool tx_napi_enable; + bool tx_poll; + u32 mhi_evid_limits[2]; /* start and end values */ + bool ipa_mhi_dynamic_config; + u32 ipa_tz_unlock_reg_num; + struct ipa_tz_unlock_reg_info *ipa_tz_unlock_reg; + struct ipa_pm_init_params pm_init; + bool wdi_over_pcie; + u32 entire_ipa_block_size; + bool do_register_collection_on_crash; + bool do_testbus_collection_on_crash; + bool do_non_tn_collection_on_crash; + bool do_ram_collection_on_crash; + u32 secure_debug_check_action; + bool ipa_endp_delay_wa; + bool skip_ieob_mask_wa; + bool ipa_wan_skb_page; + u32 icc_num_cases; + u32 icc_num_paths; + const char *icc_path_name[IPA_ICC_PATH_MAX]; + u32 icc_clk_val[IPA_ICC_LVL_MAX][IPA_ICC_MAX]; + bool ipa_gpi_event_rp_ddr; + bool rmnet_ctl_enable; + bool rmnet_ll_enable; + bool lan_coal_enable; + bool ipa_use_uc_holb_monitor; + u32 ipa_holb_monitor_poll_period; + u32 ipa_holb_monitor_max_cnt_wlan; + u32 ipa_holb_monitor_max_cnt_usb; + u32 ipa_holb_monitor_max_cnt_11ad; + const char *gsi_fw_file_name; + const char *uc_fw_file_name; + u32 tx_wrapper_cache_max_size; + u32 ipa_gen_rx_cmn_page_pool_sz_factor; + u32 ipa_gen_rx_cmn_temp_pool_sz_factor; + u32 ipa_gen_rx_ll_pool_sz_factor; + u32 ipa_wan_aggr_pkt_cnt; + bool ipa_mhi_proxy; + u32 max_num_smmu_cb; + u32 ipa_wdi3_2g_holb_timeout; + u32 ipa_wdi3_5g_holb_timeout; + bool ipa_endp_delay_wa_v2; + bool ulso_supported; + u16 ulso_ip_id_min; + u16 ulso_ip_id_max; + bool use_pm_wrapper; + bool use_tput_est_ep; + bool ulso_wa; + bool ipa_wdi_opt_dpath; + u8 coal_ipv4_id_ignore; +}; + +/** + * struct ipa3_mem_partition - represents IPA RAM Map as read from DTS + * Order and type of members should not be changed without a suitable change + * to DTS file or the code that reads it. + * + * IPA SRAM memory layout: + * +-------------------------+ + * | UC MEM | + * +-------------------------+ + * | UC INFO | + * +-------------------------+ + * | CANARY | + * +-------------------------+ + * | CANARY | + * +-------------------------+ + * | V4 FLT HDR HASHABLE | + * +-------------------------+ + * | CANARY | + * +-------------------------+ + * | CANARY | + * +-------------------------+ + * | V4 FLT HDR NON-HASHABLE | + * +-------------------------+ + * | CANARY | + * +-------------------------+ + * | CANARY | + * +-------------------------+ + * | V6 FLT HDR HASHABLE | + * +-------------------------+ + * | CANARY | + * +-------------------------+ + * | CANARY | + * +-------------------------+ + * | V6 FLT HDR NON-HASHABLE | + * +-------------------------+ + * | CANARY | + * +-------------------------+ + * | CANARY | + * +-------------------------+ + * | V4 RT HDR HASHABLE | + * +-------------------------+ + * | CANARY | + * +-------------------------+ + * | CANARY | + * +-------------------------+ + * | V4 RT HDR NON-HASHABLE | + * +-------------------------+ + * | CANARY | + * +-------------------------+ + * | CANARY | + * +-------------------------+ + * | V6 RT HDR HASHABLE | + * +-------------------------+ + * | CANARY | + * +-------------------------+ + * | CANARY | + * +-------------------------+ + * | V6 RT HDR NON-HASHABLE | + * +-------------------------+ + * | CANARY | + * +-------------------------+ + * | CANARY | + * +-------------------------+ + * | MODEM HDR | + * +-------------------------+ + * | APPS HDR (IPA4.5) | + * +-------------------------+ + * | CANARY | + * +-------------------------+ + * | CANARY | + * +-------------------------+ + * | MODEM PROC CTX | + * +-------------------------+ + * | APPS PROC CTX | + * +-------------------------+ + * | CANARY | + * +-------------------------+ + * | CANARY | + * +-------------------------+ + * | CANARY (IPA4.5) | + * +-------------------------+ + * | CANARY (IPA4.5) | + * +-------------------------+ + * | NAT TABLE (IPA4.5) | + * +-------------------------+ + * | CANARY (IPA4.5) | + * +-------------------------+ + * | CANARY (IPA4.5) | + * +-------------------------+ + * | PDN CONFIG | + * +-------------------------+ + * | CANARY | + * +-------------------------+ + * | CANARY | + * +-------------------------+ + * | QUOTA STATS | + * +-------------------------+ + * | TETH STATS | + * +-------------------------+ + * | FnR STATS | + * +-------------------------+ + * | DROP STATS | + * +-------------------------+ + * | CANARY (IPA4.5) | + * +-------------------------+ + * | CANARY (IPA4.5) | + * +-------------------------+ + * | MODEM MEM | + * +-------------------------+ + * | Dummy (IPA4.5) | + * +-------------------------+ + * | CANARY (IPA4.5) | + * +-------------------------+ + * | UC DESC RAM (IPA3.5) | + * +-------------------------+ + */ +struct ipa3_mem_partition { + u32 ofst_start; + u32 v4_flt_hash_ofst; + u32 v4_flt_hash_size; + u32 v4_flt_hash_size_ddr; + u32 v4_flt_nhash_ofst; + u32 v4_flt_nhash_size; + u32 v4_flt_nhash_size_ddr; + u32 v6_flt_hash_ofst; + u32 v6_flt_hash_size; + u32 v6_flt_hash_size_ddr; + u32 v6_flt_nhash_ofst; + u32 v6_flt_nhash_size; + u32 v6_flt_nhash_size_ddr; + u32 v4_rt_num_index; + u32 v4_modem_rt_index_lo; + u32 v4_modem_rt_index_hi; + u32 v4_apps_rt_index_lo; + u32 v4_apps_rt_index_hi; + u32 v4_rt_hash_ofst; + u32 v4_rt_hash_size; + u32 v4_rt_hash_size_ddr; + u32 v4_rt_nhash_ofst; + u32 v4_rt_nhash_size; + u32 v4_rt_nhash_size_ddr; + u32 v6_rt_num_index; + u32 v6_modem_rt_index_lo; + u32 v6_modem_rt_index_hi; + u32 v6_apps_rt_index_lo; + u32 v6_apps_rt_index_hi; + u32 v6_rt_hash_ofst; + u32 v6_rt_hash_size; + u32 v6_rt_hash_size_ddr; + u32 v6_rt_nhash_ofst; + u32 v6_rt_nhash_size; + u32 v6_rt_nhash_size_ddr; + u32 modem_hdr_ofst; + u32 modem_hdr_size; + u32 apps_hdr_ofst; + u32 apps_hdr_size; + u32 apps_hdr_size_ddr; + u32 modem_hdr_proc_ctx_ofst; + u32 modem_hdr_proc_ctx_size; + u32 apps_hdr_proc_ctx_ofst; + u32 apps_hdr_proc_ctx_size; + u32 apps_hdr_proc_ctx_size_ddr; + u32 nat_tbl_ofst; + u32 nat_tbl_size; + u32 modem_comp_decomp_ofst; + u32 modem_comp_decomp_size; + u32 modem_ofst; + u32 modem_size; + u32 apps_v4_flt_hash_ofst; + u32 apps_v4_flt_hash_size; + u32 apps_v4_flt_nhash_ofst; + u32 apps_v4_flt_nhash_size; + u32 apps_v6_flt_hash_ofst; + u32 apps_v6_flt_hash_size; + u32 apps_v6_flt_nhash_ofst; + u32 apps_v6_flt_nhash_size; + u32 uc_info_ofst; + u32 uc_info_size; + u32 end_ofst; + u32 apps_v4_rt_hash_ofst; + u32 apps_v4_rt_hash_size; + u32 apps_v4_rt_nhash_ofst; + u32 apps_v4_rt_nhash_size; + u32 apps_v6_rt_hash_ofst; + u32 apps_v6_rt_hash_size; + u32 apps_v6_rt_nhash_ofst; + u32 apps_v6_rt_nhash_size; + u32 uc_descriptor_ram_ofst; + u32 uc_descriptor_ram_size; + u32 pdn_config_ofst; + u32 pdn_config_size; + u32 stats_quota_q6_ofst; + u32 stats_quota_q6_size; + u32 stats_quota_ap_ofst; + u32 stats_quota_ap_size; + u32 stats_tethering_ofst; + u32 stats_tethering_size; + u32 stats_fnr_ofst; + u32 stats_fnr_size; + u32 uc_ofst; + u32 uc_size; + + /* Irrelevant starting IPA4.5 */ + u32 stats_flt_v4_ofst; + u32 stats_flt_v4_size; + u32 stats_flt_v6_ofst; + u32 stats_flt_v6_size; + u32 stats_rt_v4_ofst; + u32 stats_rt_v4_size; + u32 stats_rt_v6_ofst; + u32 stats_rt_v6_size; + + u32 stats_drop_ofst; + u32 stats_drop_size; +}; + +struct ipa3_controller { + struct ipa3_mem_partition *mem_partition; + u32 ipa_clk_rate_turbo; + u32 ipa_clk_rate_nominal; + u32 ipa_clk_rate_svs; + u32 ipa_clk_rate_svs2; + u32 clock_scaling_bw_threshold_turbo; + u32 clock_scaling_bw_threshold_nominal; + u32 clock_scaling_bw_threshold_svs; + u32 ipa_reg_base_ofst; + u32 max_holb_tmr_val; + void (*ipa_sram_read_settings)(void); + int (*ipa_init_sram)(void); + int (*ipa_init_hdr)(void); + int (*ipa_init_rt4)(void); + int (*ipa_init_rt6)(void); + int (*ipa_init_flt4)(void); + int (*ipa_init_flt6)(void); + int (*ipa3_read_ep_reg)(char *buff, int max_len, int pipe); + int (*ipa3_commit_flt)(enum ipa_ip_type ip); + int (*ipa3_commit_rt)(enum ipa_ip_type ip); + int (*ipa3_commit_hdr)(void); + void (*ipa3_enable_clks)(void); + void (*ipa3_disable_clks)(void); + struct icc_path *icc_path[IPA_ICC_PATH_MAX]; +}; + +/* + * When data arrives on IPA_CLIENT_APPS_LAN_COAL_CONS, said data will + * contain a qmap header followed by an array of the following. The + * number of them in the array is always MAX_COAL_PACKET_STATUS_INFO + * (see below); however, only "num_nlos" (a field in the cmap heeader) + * will be valid. The rest are to be ignored. + */ +struct coal_packet_status_info { + u16 pkt_len; + u8 pkt_cksum_errs; + u8 num_pkts; +} __aligned(1); +/* + * This is the number of the struct coal_packet_status_info that + * follow the qmap header. As above, only "num_nlos" are valid. The + * rest are to be ignored. + */ +#define MAX_COAL_PACKET_STATUS_INFO (6) +#define VALID_NLS(nls) \ + ((nls) > 0 && (nls) <= MAX_COAL_PACKET_STATUS_INFO) +/* + * The following is the total number of bits in all the pkt_cksum_errs + * in each of the struct coal_packet_status_info(s) that follow the + * qmap header. Each bit is meant to tell us if a packet is good or + * bad, relative to a checksum. Given this, the max number of bits + * dictates the max number of packets that can be in a buffer from the + * IPA. + */ +#define MAX_COAL_PACKETS (48) + +extern struct ipa3_context *ipa3_ctx; +extern bool ipa_net_initialized; + +/* public APIs */ +/* Generic GSI channels functions */ +int ipa3_request_gsi_channel(struct ipa_request_gsi_channel_params *params, + struct ipa_req_chan_out_params *out_params); + +int ipa3_release_gsi_channel(u32 clnt_hdl); + +int ipa3_reset_gsi_channel(u32 clnt_hdl); + +int ipa3_reset_gsi_event_ring(u32 clnt_hdl); + +/* Specific xDCI channels functions */ +int ipa3_set_usb_max_packet_size( + enum ipa_usb_max_usb_packet_size usb_max_packet_size); + +int ipa3_xdci_start(u32 clnt_hdl, u8 xferrscidx, bool xferrscidx_valid); + +int ipa3_xdci_connect(u32 clnt_hdl); + +int ipa3_xdci_disconnect(u32 clnt_hdl, bool should_force_clear, u32 qmi_req_id); + +void ipa3_xdci_ep_delay_rm(u32 clnt_hdl); +int ipa3_set_reset_client_prod_pipe_delay(bool set_reset, + enum ipa_client_type client); +int ipa3_start_stop_client_prod_gsi_chnl(enum ipa_client_type client, + bool start_chnl); +void ipa3_client_prod_post_shutdown_cleanup(void); + +int ipa3_set_reset_client_cons_pipe_sus_holb(bool set_reset, + enum ipa_client_type client); + +int ipa3_xdci_suspend(u32 ul_clnt_hdl, u32 dl_clnt_hdl, + bool should_force_clear, u32 qmi_req_id, bool is_dpl); + +int ipa3_xdci_resume(u32 ul_clnt_hdl, u32 dl_clnt_hdl, bool is_dpl); + +/* + * Remove ep delay + */ +int ipa3_clear_endpoint_delay(u32 clnt_hdl); + +/* + * Configuration + */ +int ipa3_cfg_ep_seq(u32 clnt_hdl, const struct ipa_ep_cfg_seq *seq_cfg); + +int ipa3_cfg_ep_hdr(u32 clnt_hdl, const struct ipa_ep_cfg_hdr *ipa_ep_cfg); + +int ipa3_cfg_ep_hdr_ext(u32 clnt_hdl, + const struct ipa_ep_cfg_hdr_ext *ipa_ep_cfg); + +int ipa3_cfg_ep_mode(u32 clnt_hdl, const struct ipa_ep_cfg_mode *ipa_ep_cfg); + +int ipa3_cfg_ep_aggr(u32 clnt_hdl, const struct ipa_ep_cfg_aggr *ipa_ep_cfg); + +int ipa3_cfg_ep_deaggr(u32 clnt_hdl, + const struct ipa_ep_cfg_deaggr *ipa_ep_cfg); + +int ipa3_cfg_ep_route(u32 clnt_hdl, const struct ipa_ep_cfg_route *ipa_ep_cfg); + +int ipa3_cfg_ep_holb(u32 clnt_hdl, const struct ipa_ep_cfg_holb *ipa_ep_cfg); + +void ipa3_cal_ep_holb_scale_base_val(u32 tmr_val, + struct ipa_ep_cfg_holb *ep_holb); + +int ipa3_cfg_ep_cfg(u32 clnt_hdl, const struct ipa_ep_cfg_cfg *ipa_ep_cfg); + +int ipa3_cfg_ep_prod_cfg(u32 clnt_hdl, const struct ipa_ep_cfg_prod_cfg *prod_cfg); + +int ipa3_force_cfg_ep_holb(u32 clnt_hdl, struct ipa_ep_cfg_holb *ipa_ep_cfg); + +int ipa3_cfg_ep_metadata_mask(u32 clnt_hdl, + const struct ipa_ep_cfg_metadata_mask *ipa_ep_cfg); + +int ipa3_cfg_ep_holb_by_client(enum ipa_client_type client, + const struct ipa_ep_cfg_holb *ipa_ep_cfg); + +int ipa3_cfg_ep_ulso(u32 clnt_hdl, const struct ipa_ep_cfg_ulso *ep_ulso); + +int ipa3_setup_uc_act_tbl(void); + +/* + * Header removal / addition + */ + +int ipa3_del_hdr_by_user(struct ipa_ioc_del_hdr *hdls, bool by_user); + +int ipa3_commit_hdr(void); + +int ipa3_get_hdr_offset(char* name, u32* offset); + +int ipa3_get_hdr_proc_ctx_hdl(struct ipa_ioc_get_hdr *lookup); + +int ipa3_get_hdr_proc_ctx_offset(char* name, u32* offset); + +int ipa3_put_hdr(u32 hdr_hdl); + +int ipa3_copy_hdr(struct ipa_ioc_copy_hdr *copy); + +u32 ipa3_get_hdr_bin_size(int index); + +/* + * Header Processing Context + */ + +int ipa3_del_hdr_proc_ctx_by_user(struct ipa_ioc_del_hdr_proc_ctx *hdls, + bool by_user); + +/* + * Routing + */ +int ipa3_add_rt_rule_ext(struct ipa_ioc_add_rt_rule_ext *rules); + +int ipa3_add_rt_rule_ext_v2(struct ipa_ioc_add_rt_rule_ext_v2 *rules, + bool user); + +int ipa3_add_rt_rule_after(struct ipa_ioc_add_rt_rule_after *rules); + +int ipa3_add_rt_rule_after_v2(struct ipa_ioc_add_rt_rule_after_v2 + *rules); + +int ipa3_get_rt_tbl(struct ipa_ioc_get_rt_tbl *lookup); + +int ipa3_query_rt_index(struct ipa_ioc_get_rt_tbl_indx *in); + +int ipa3_mdfy_rt_rule(struct ipa_ioc_mdfy_rt_rule *rules); + +int ipa3_mdfy_rt_rule_v2(struct ipa_ioc_mdfy_rt_rule_v2 *rules); + +int ipa3_set_nat_conn_track_exc_rt_tbl(u32 rt_tbl_hdl, enum ipa_ip_type ip); + +/* + * Filtering + */ +int ipa3_add_flt_rule(struct ipa_ioc_add_flt_rule *rules); + +int ipa3_add_flt_rule_v2(struct ipa_ioc_add_flt_rule_v2 *rules); + +int ipa3_add_flt_rule_usr(struct ipa_ioc_add_flt_rule *rules, + bool user_only); + +int ipa3_add_flt_rule_usr_v2(struct ipa_ioc_add_flt_rule_v2 *rules, + bool user_only); + +int ipa3_add_flt_rule_after(struct ipa_ioc_add_flt_rule_after *rules); + +int ipa3_add_flt_rule_after_v2(struct ipa_ioc_add_flt_rule_after_v2 + *rules); + +int ipa3_mdfy_flt_rule(struct ipa_ioc_mdfy_flt_rule *rules); + +int ipa3_mdfy_flt_rule_v2(struct ipa_ioc_mdfy_flt_rule_v2 *rules); + +int ipa3_commit_flt(enum ipa_ip_type ip); + +int ipa3_reset_flt(enum ipa_ip_type ip, bool user_only); + +int ipa_flt_sram_set_client_prio_high(enum ipa_client_type client); + +/* + * NAT + */ +int ipa3_nat_ipv6ct_init_devices(void); +void ipa3_nat_ipv6ct_destroy_devices(void); + +int ipa3_allocate_nat_device(struct ipa_ioc_nat_alloc_mem *mem); +int ipa3_allocate_nat_table( + struct ipa_ioc_nat_ipv6ct_table_alloc *table_alloc); +int ipa3_allocate_ipv6ct_table( + struct ipa_ioc_nat_ipv6ct_table_alloc *table_alloc); +int ipa3_nat_get_sram_info(struct ipa_nat_in_sram_info *info_ptr); +int ipa3_app_clk_vote(enum ipa_app_clock_vote_type vote_type); +void ipa3_get_default_evict_values( + struct ipahal_reg_coal_evict_lru *evict_lru); +void ipa3_default_evict_register( void ); +int ipa3_set_evict_policy( + struct ipa_ioc_coal_evict_policy *evict_pol); +void start_coalescing( void ); +void stop_coalescing( void ); +bool lan_coal_enabled( void ); + +/* + * Messaging + */ +int ipa3_resend_wlan_msg(void); +int ipa3_register_pull_msg(struct ipa_msg_meta *meta, ipa_msg_pull_fn callback); +int ipa3_deregister_pull_msg(struct ipa_msg_meta *meta); + +/* + * Interface + */ +int ipa3_register_intf_ext(const char *name, const struct ipa_tx_intf *tx, + const struct ipa_rx_intf *rx, + const struct ipa_ext_intf *ext); + +/* + * To transfer multiple data packets + * While passing the data descriptor list, the anchor node + * should be of type struct ipa_tx_data_desc not list_head + */ +int ipa3_tx_dp_mul(enum ipa_client_type dst, + struct ipa_tx_data_desc *data_desc); + +/* + * System pipes + */ +int ipa3_setup_tput_pipe(void); +int ipa_pm_wrapper_wdi_set_perf_profile_internal(struct ipa_wdi_perf_profile *profile); +int ipa_pm_wrapper_connect_wdi_pipe(struct ipa_wdi_in_params *in, + struct ipa_wdi_out_params *out); +int ipa_pm_wrapper_disconnect_wdi_pipe(u32 clnt_hdl); +int ipa_pm_wrapper_enable_wdi_pipe(u32 clnt_hdl); +int ipa_pm_wrapper_disable_pipe(u32 clnt_hdl); +int ipa3_enable_gsi_wdi_pipe(u32 clnt_hdl); +int ipa3_disable_gsi_wdi_pipe(u32 clnt_hdl); +int ipa3_disconnect_gsi_wdi_pipe(u32 clnt_hdl); +int ipa3_resume_gsi_wdi_pipe(u32 clnt_hdl); +int ipa3_get_wdi_gsi_stats(struct ipa_uc_dbg_ring_stats *stats); +int ipa3_get_wdi3_gsi_stats(struct ipa_uc_dbg_ring_stats *stats); +int ipa3_get_usb_gsi_stats(struct ipa_uc_dbg_ring_stats *stats); +bool ipa_usb_is_teth_prot_connected(enum ipa_usb_teth_prot usb_teth_prot); +int ipa3_get_aqc_gsi_stats(struct ipa_uc_dbg_ring_stats *stats); +int ipa3_get_rtk_gsi_stats(struct ipa_uc_dbg_ring_stats *stats); +int ipa3_get_ntn_gsi_stats(struct ipa_uc_dbg_ring_stats *stats); +u16 ipa3_get_smem_restr_bytes(void); + +int ipa3_wigig_init_debugfs_i(struct dentry *dent); + +/* + * To register uC ready callback if uC not ready + * and also check uC readiness + * if uC not ready only, register callback + */ +int ipa3_uc_reg_rdyCB(struct ipa_wdi_uc_ready_params *param); +/* + * To de-register uC ready callback + */ +int ipa3_uc_dereg_rdyCB(void); + +int ipa_create_uc_smmu_mapping(int res_idx, bool wlan_smmu_en, + phys_addr_t pa, struct sg_table *sgt, size_t len, bool device, + unsigned long *iova); + +int ipa_create_gsi_smmu_mapping(int res_idx, bool wlan_smmu_en, + phys_addr_t pa, struct sg_table *sgt, size_t len, bool device, + unsigned long *iova); + +void ipa3_release_wdi3_gsi_smmu_mappings(u8 dir); + +/* + * Tethering bridge (Rmnet / MBIM) + */ + +int ipa3_teth_bridge_get_pm_hdl(enum ipa_client_type client); + +/* + * Tethering client info + */ + +int ipa3_get_wlan_stats(struct ipa_get_wdi_sap_stats *wdi_sap_stats); + +int ipa3_set_wlan_quota(struct ipa_set_wifi_quota *wdi_quota); + +int ipa3_inform_wlan_bw(struct ipa_inform_wlan_bw *wdi_bw); + +/* + * IPADMA + */ +int ipa3_dma_uc_memcpy(phys_addr_t dest, phys_addr_t src, int len); + +/* + * Miscellaneous + */ +int ipa_get_ep_mapping_from_gsi(int ch_id); + +int ipa3_ctx_get_type(enum ipa_type_mode type); +bool ipa3_ctx_get_flag(enum ipa_flag flag); +u32 ipa3_ctx_get_num_pipes(void); + +void ipa3_proxy_clk_vote(bool is_ssr); +void ipa3_proxy_clk_unvote(void); + +bool ipa3_is_client_handle_valid(u32 clnt_hdl); + +enum ipa_client_type ipa3_get_client_mapping(int pipe_idx); +enum ipa_client_type ipa3_get_client_by_pipe(int pipe_idx); + +void ipa_init_ep_flt_bitmap(void); + +bool ipa_is_ep_support_flt(int pipe_idx); + +bool ipa3_get_modem_cfg_emb_pipe_flt(void); + +u8 ipa3_get_qmb_master_sel(enum ipa_client_type client); + +u8 ipa3_get_tx_instance(enum ipa_client_type client); + +bool ipa3_get_qmap_pipe_enable(void); + +struct device *ipa3_get_pdev(void); +int ipa3_sys_update_gsi_hdls(u32 clnt_hdl, unsigned long gsi_ch_hdl, + unsigned long gsi_ev_hdl); +int ipa3_sys_setup(struct ipa_sys_connect_params *sys_in, + unsigned long *ipa_transport_hdl, + u32 *ipa_pipe_num, u32 *clnt_hdl, bool en_status); +int ipa3_sys_teardown(u32 clnt_hdl); + +/* internal functions */ + +u8 ipa3_get_hw_type_index(void); + +bool ipa_is_modem_pipe(int pipe_idx); + +int ipa3_send_one(struct ipa3_sys_context *sys, struct ipa3_desc *desc, + bool in_atomic); +int ipa3_send(struct ipa3_sys_context *sys, + u32 num_desc, + struct ipa3_desc *desc, + bool in_atomic); +int ipa_get_ep_mapping(enum ipa_client_type client); +int ipa_get_ep_group(enum ipa_client_type client); + +int ipa3_generate_hw_rule(enum ipa_ip_type ip, + const struct ipa_rule_attrib *attrib, + u8 **buf, + u16 *en_rule); +int ipa3_init_hw(void); +struct ipa3_rt_tbl *__ipa3_find_rt_tbl(enum ipa_ip_type ip, const char *name); +int ipa_set_single_ndp_per_mbim(bool enable); +void ipa3_debugfs_init(void); +void ipa3_debugfs_remove(void); +void ipa3_eth_debugfs_init(void); +void ipa3_eth_debugfs_add(struct ipa_eth_client *client); + +void ipa3_dump_buff_internal(void *base, dma_addr_t phy_base, u32 size); + +void ipa3_qdss_register(void); +int ipa3_conn_qdss_pipes(struct ipa_qdss_conn_in_params *in, + struct ipa_qdss_conn_out_params *out); +int ipa3_disconn_qdss_pipes(void); + +#ifdef IPA_DEBUG +#define IPA_DUMP_BUFF(base, phy_base, size) \ + ipa3_dump_buff_internal(base, phy_base, size) +#else +#define IPA_DUMP_BUFF(base, phy_base, size) +#endif +int ipa3_init_mem_partition(enum ipa_hw_type ipa_hw_type); +int ipa3_controller_static_bind(struct ipa3_controller *controller, + enum ipa_hw_type ipa_hw_type, u32 ipa_cfg_offset); +int ipa3_cfg_route(struct ipahal_reg_route *route); +int ipa3_send_cmd_timeout(u16 num_desc, struct ipa3_desc *descr, u32 timeout); +int ipa3_send_cmd(u16 num_desc, struct ipa3_desc *descr); +int ipa3_cfg_filter(u32 disable); +int ipa3_straddle_boundary(u32 start, u32 end, u32 boundary); +struct ipa3_context *ipa3_get_ctx(void); +void ipa3_enable_clks(void); +void ipa3_disable_clks(void); +int ipa3_inc_client_enable_clks_no_block(struct ipa_active_client_logging_info + *id); +void ipa3_dec_client_disable_clks_no_block( + struct ipa_active_client_logging_info *id); +void ipa3_dec_client_disable_clks_delay_wq( + struct ipa_active_client_logging_info *id, unsigned long delay); +void ipa3_active_clients_log_dec(struct ipa_active_client_logging_info *id, + bool int_ctx); +void ipa3_active_clients_log_inc(struct ipa_active_client_logging_info *id, + bool int_ctx); +int ipa3_active_clients_log_print_buffer(char *buf, int size); +int ipa3_active_clients_log_print_table(char *buf, int size); +void ipa3_active_clients_log_clear(void); +int ipa3_interrupts_init(u32 ipa_irq, u32 ee, struct device *ipa_dev); +void ipa3_interrupts_destroy(u32 ipa_irq, struct device *ipa_dev); +int __ipa3_del_rt_rule(u32 rule_hdl); +int __ipa3_del_hdr(u32 hdr_hdl, bool by_user); +int __ipa3_release_hdr(u32 hdr_hdl); +int __ipa3_release_hdr_proc_ctx(u32 proc_ctx_hdl); +int _ipa_read_ep_reg_v3_0(char *buf, int max_len, int pipe); +int _ipa_read_ep_reg_v4_0(char *buf, int max_len, int pipe); +int _ipa_read_ipahal_regs(void); +void _ipa_enable_clks_v3_0(void); +void _ipa_disable_clks_v3_0(void); +struct device *ipa3_get_dma_dev(void); +void ipa3_suspend_active_aggr_wa(u32 clnt_hdl); +void ipa3_suspend_handler(enum ipa_irq_type interrupt, + void *private_data, + void *interrupt_data); + +ssize_t ipa3_read(struct file *filp, char __user *buf, size_t count, + loff_t *f_pos); +int ipa3_pull_msg(struct ipa_msg_meta *meta, char *buff, size_t count); +int ipa3_query_intf(struct ipa_ioc_query_intf *lookup); +int ipa3_query_intf_tx_props(struct ipa_ioc_query_intf_tx_props *tx); +int ipa3_query_intf_rx_props(struct ipa_ioc_query_intf_rx_props *rx); +int ipa3_query_intf_ext_props(struct ipa_ioc_query_intf_ext_props *ext); + +int ipa3_get_max_pdn(void); + +void wwan_cleanup(void); + +int ipa3_teth_bridge_driver_init(void); +void ipa3_lan_rx_cb(void *priv, enum ipa_dp_evt_type evt, unsigned long data); +void ipa3_lan_coal_rx_cb( + void *priv, + enum ipa_dp_evt_type evt, + unsigned long data); + +int _ipa_init_sram_v3(void); +int _ipa_init_hdr_v3_0(void); +int _ipa_init_rt4_v3(void); +int _ipa_init_rt6_v3(void); +int _ipa_init_flt4_v3(void); +int _ipa_init_flt6_v3(void); + +int __ipa_commit_flt_v3(enum ipa_ip_type ip); +int __ipa_commit_rt_v3(enum ipa_ip_type ip); + +int __ipa_commit_hdr_v3_0(void); +void ipa3_skb_recycle(struct sk_buff *skb); +void ipa3_install_dflt_flt_rules(u32 ipa_ep_idx); +void ipa3_delete_dflt_flt_rules(u32 ipa_ep_idx); +void ipa3_install_dl_opt_wdi_dpath_flt_rules(u32 ipa_ep_idx, u32 rt_tbl_idx); +void ipa3_delete_dl_opt_wdi_dpath_flt_rules(u32 ipa_ep_idx); + +int ipa3_remove_secondary_flow_ctrl(int gsi_chan_hdl); +int ipa3_enable_data_path(u32 clnt_hdl); +int ipa3_disable_data_path(u32 clnt_hdl); +int ipa3_disable_gsi_data_path(u32 clnt_hdl); +int ipa3_alloc_rule_id(struct idr *rule_ids); +int ipa3_alloc_counter_id(struct ipa_ioc_flt_rt_counter_alloc *counter); +void ipa3_counter_remove_hdl(int hdl); +void ipa3_counter_id_remove_all(void); +int ipa3_id_alloc(void *ptr); +bool ipa3_check_idr_if_freed(void *ptr); +void *ipa3_id_find(u32 id); +void ipa3_id_remove(u32 id); +int ipa3_enable_force_clear(u32 request_id, bool throttle_source, + u32 source_pipe_bitmask, u32 source_pipe_reg_idx); +int ipa3_disable_force_clear(u32 request_id); + +int ipa3_cfg_ep_status(u32 clnt_hdl, + const struct ipahal_reg_ep_cfg_status *ipa_ep_cfg); + +bool ipa3_should_pipe_be_suspended(enum ipa_client_type client); +int ipa3_tag_aggr_force_close(int pipe_num); + +void ipa3_active_clients_unlock(void); +int ipa3_wdi_init(void); +int ipa_get_wdi_version(void); +bool ipa_wdi_is_tx1_used(void); +int ipa3_write_qmapid_gsi_wdi_pipe(u32 clnt_hdl, u8 qmap_id); +int ipa3_write_qmapid_wdi_pipe(u32 clnt_hdl, u8 qmap_id); +int ipa3_write_qmapid_wdi3_gsi_pipe(u32 clnt_hdl, u8 qmap_id); +int ipa3_tag_process(struct ipa3_desc *desc, int num_descs, + unsigned long timeout); + +int ipa3_usb_init(void); +void ipa3_usb_exit(void); + +void ipa3_q6_pre_shutdown_cleanup(void); +void ipa3_q6_post_shutdown_cleanup(void); +void ipa3_q6_pre_powerup_cleanup(void); +void ipa3_update_ssr_state(bool is_ssr); +int ipa3_init_q6_smem(void); + +int ipa3_mhi_handle_ipa_config_req(struct ipa_config_req_msg_v01 *config_req); + +int ipa3_uc_interface_init(void); +int ipa3_uc_is_gsi_channel_empty(enum ipa_client_type ipa_client); +int ipa3_uc_loaded_check(void); +void ipa3_uc_load_notify(void); +int ipa3_uc_holb_enabled_check(void); +int ipa3_uc_register_ready_cb(struct notifier_block *nb); +int ipa3_uc_unregister_ready_cb(struct notifier_block *nb); +int ipa3_uc_send_cmd(u32 cmd, u32 opcode, u32 expected_status, + bool polling_mode, unsigned long timeout_jiffies); +void ipa3_uc_register_handlers(enum ipa3_hw_features feature, + struct ipa3_uc_hdlrs *hdlrs); +int ipa3_uc_notify_clk_state(bool enabled); +void ipa3_uc_interface_destroy(void); +int ipa3_dma_setup(void); +void ipa3_dma_shutdown(void); +void ipa3_dma_async_memcpy_notify_cb(void *priv, + enum ipa_dp_evt_type evt, unsigned long data); + +int ipa3_uc_update_hw_flags(u32 flags); + +int ipa3_uc_mhi_init_channel(int ipa_ep_idx, int channelHandle, + int contexArrayIndex, int channelDirection); +int ipa3_uc_mhi_resume_channel(int channelHandle, bool LPTransitionRejected); +int ipa3_uc_memcpy(phys_addr_t dest, phys_addr_t src, int len); +int ipa3_uc_send_remote_ipa_info(u32 remote_addr, uint32_t mbox_n); +int ipa3_uc_quota_monitor(uint64_t quota); +int ipa3_uc_enable_holb_monitor(uint32_t polling_period); +int ipa3_uc_add_holb_monitor(uint16_t gsi_ch, uint32_t action_mask, + uint32_t max_stuck_count, uint8_t ee); +int ipa3_uc_del_holb_monitor(uint16_t gsi_ch, uint8_t ee); +int ipa3_uc_disable_holb_monitor(void); +int ipa3_uc_setup_event_ring(void); +void ipa3_tag_destroy_imm(void *user1, int user2); +void ipa3_uc_rg10_write_reg(enum ipahal_reg_name reg, u32 n, u32 val); + +int ipa3_wigig_init_i(void); + +/* Hardware stats */ + +#define IPA_STATS_MAX_PIPE_BIT 32 + +struct ipa_teth_stats_endpoints { + u32 prod_mask[IPA5_PIPE_REG_NUM]; + u32 dst_ep_mask[IPA5_PIPES_NUM][IPA5_PIPE_REG_NUM]; +}; + +int ipa_hw_stats_init(void); + +int ipa_init_flt_rt_stats(void); + +int ipa_debugfs_init_stats(struct dentry *parent); + +int ipa_init_quota_stats(u32 *pipe_bitmask); + +int ipa_get_quota_stats(struct ipa_quota_stats_all *out); + +int ipa_reset_quota_stats(enum ipa_client_type client); + +int ipa_reset_all_quota_stats(void); + +int ipa_drop_stats_init(void); + +int ipa_init_drop_stats(u32 *pipe_bitmask); + +int ipa_get_drop_stats(struct ipa_drop_stats_all *out); + +int ipa_reset_drop_stats(enum ipa_client_type client); + +int ipa_reset_all_drop_stats(void); + +int ipa_init_teth_stats(struct ipa_teth_stats_endpoints *in); + +int ipa_get_teth_stats(void); + +int ipa_query_teth_stats(enum ipa_client_type prod, + struct ipa_quota_stats_all *out, bool reset); + +int ipa_reset_teth_stats(enum ipa_client_type prod, enum ipa_client_type cons); + +int ipa_reset_all_cons_teth_stats(enum ipa_client_type prod); + +int ipa_reset_all_teth_stats(void); + +int ipa_get_flt_rt_stats(struct ipa_ioc_flt_rt_query *query); + +int ipa_set_flt_rt_stats(int index, struct ipa_flt_rt_stats stats); + +bool ipa_get_fnr_info(struct ipacm_fnr_info *fnr_info); + +u32 ipa3_get_max_num_pipes(void); +u32 ipa3_get_num_pipes(void); +struct ipa_smmu_cb_ctx *ipa3_get_smmu_ctx(enum ipa_smmu_cb_type); +struct iommu_domain *ipa3_get_smmu_domain(void); +struct iommu_domain *ipa3_get_uc_smmu_domain(void); +struct iommu_domain *ipa3_get_wlan_smmu_domain(void); +struct iommu_domain *ipa3_get_wlan1_smmu_domain(void); +struct iommu_domain *ipa3_get_eth_smmu_domain(void); +struct iommu_domain *ipa3_get_eth1_smmu_domain(void); +struct iommu_domain *ipa3_get_smmu_domain_by_type + (enum ipa_smmu_cb_type cb_type); +int ipa3_iommu_map(struct iommu_domain *domain, unsigned long iova, + phys_addr_t paddr, size_t size, int prot); +int ipa3_ap_suspend(struct device *dev); +int ipa3_ap_freeze(struct device *dev); +int ipa3_ap_resume(struct device *dev); +int ipa3_init_interrupts(void); +struct iommu_domain *ipa3_get_smmu_domain(void); +int ipa3_release_wdi_mapping(u32 num_buffers, struct ipa_wdi_buffer_info *info); +int ipa3_create_wdi_mapping(u32 num_buffers, struct ipa_wdi_buffer_info *info); +int ipa3_set_flt_tuple_mask(int pipe_idx, struct ipahal_reg_hash_tuple *tuple); +int ipa3_set_rt_tuple_mask(int tbl_idx, struct ipahal_reg_hash_tuple *tuple); +void ipa3_set_resorce_groups_min_max_limits(void); +void ipa3_set_resorce_groups_config(void); +int ipa3_suspend_apps_pipes(bool suspend); +void ipa3_force_close_coal( + bool close_wan, + bool close_lan ); +int ipa3_flt_read_tbl_from_hw(u32 pipe_idx, + enum ipa_ip_type ip_type, + bool hashable, + struct ipahal_flt_rule_entry entry[], + int *num_entry); +int ipa3_rt_read_tbl_from_hw(u32 tbl_idx, + enum ipa_ip_type ip_type, + bool hashable, + struct ipahal_rt_rule_entry entry[], + int *num_entry); +int ipa3_inject_dma_task_for_gsi(void); +int ipa3_uc_panic_notifier(struct notifier_block *this, + unsigned long event, void *ptr); +void ipa3_inc_acquire_wakelock(void); +void ipa3_dec_release_wakelock(void); +int ipa3_load_fws(const struct firmware *firmware, phys_addr_t gsi_mem_base, + enum gsi_ver); +int emulator_load_fws( + const struct firmware *firmware, + u32 transport_mem_base, + u32 transport_mem_size, + enum gsi_ver); +int ipa3_rmnet_ctl_init(void); +int ipa3_setup_apps_low_lat_prod_pipe(bool rmnet_config, + struct rmnet_egress_param *egress_param); +int ipa3_setup_apps_low_lat_cons_pipe(bool rmnet_config, + struct rmnet_ingress_param *ingress_param); +int ipa3_teardown_apps_low_lat_pipes(void); +int ipa3_rmnet_ll_init(void); +int ipa3_setup_apps_low_lat_data_prod_pipe( + struct rmnet_egress_param *egress_param, + struct net_device *dev); +int ipa3_setup_apps_low_lat_data_cons_pipe( + struct rmnet_ingress_param *ingress_param, + struct net_device *dev); +int ipa3_teardown_apps_low_lat_data_pipes(void); +const char *ipa_hw_error_str(enum ipa3_hw_errors err_type); +int ipa_gsi_ch20_wa(void); +int ipa3_lan_rx_poll(u32 clnt_hdl, int weight); +int ipa3_smmu_map_peer_reg(phys_addr_t phys_addr, bool map, + enum ipa_smmu_cb_type cb_type); +int ipa3_smmu_map_peer_buff(u64 iova, u32 size, bool map, struct sg_table *sgt, + enum ipa_smmu_cb_type cb_type); +void ipa3_reset_freeze_vote(void); +int ipa3_ntn_init(void); +int ipa3_get_ntn_stats(struct Ipa3HwStatsNTNInfoData_t *stats); +struct dentry *ipa_debugfs_get_root(void); +bool ipa3_is_msm_device(void); +void ipa3_enable_dcd(void); +void ipa3_disable_prefetch(enum ipa_client_type client); +void ipa3_dealloc_common_event_ring(void); +int ipa3_alloc_common_event_ring(void); +int ipa3_allocate_dma_task_for_gsi(void); +void ipa3_free_dma_task_for_gsi(void); +int ipa3_allocate_coal_close_frame(void); +void ipa3_free_coal_close_frame(void); +int ipa3_set_clock_plan_from_pm(int idx); +void __ipa_gsi_irq_rx_scedule_poll(struct ipa3_sys_context *sys); +void ipa3_init_imm_cmd_desc(struct ipa3_desc *desc, + struct ipahal_imm_cmd_pyld *cmd_pyld); +uint ipa3_get_emulation_type(void); +int ipa3_get_transport_info( + phys_addr_t *phys_addr_ptr, + unsigned long *size_ptr); +irq_handler_t ipa3_get_isr(void); +void ipa_pc_qmp_enable(void); +u32 ipa3_get_r_rev_version(void); +void ipa3_notify_clients_registered(void); +#if defined(CONFIG_IPA3_REGDUMP) +int ipa_reg_save_init(u32 value); +void ipa_save_registers(void); +void ipa_save_gsi_ver(void); +#else +static inline int ipa_reg_save_init(u32 value) { return 0; } +static inline void ipa_save_registers(void) {}; +static inline void ipa_save_gsi_ver(void) {}; +#endif + +#ifdef CONFIG_IPA_ETH +int ipa_eth_init(void); +void ipa_eth_exit(void); +#else +static inline int ipa_eth_init(void) { return 0; } +static inline void ipa_eth_exit(void) { } +#endif +void ipa3_eth_debugfs_add_node(struct ipa_eth_client *client); +int ipa3_eth_connect( + struct ipa_eth_client_pipe_info *pipe, + enum ipa_client_type client_type); +int ipa3_eth_disconnect( + struct ipa_eth_client_pipe_info *pipe, + enum ipa_client_type client_type); +#if IPA_ETH_API_VER < 2 +int ipa3_eth_client_conn_evt(struct ipa_ecm_msg *msg); +int ipa3_eth_client_disconn_evt(struct ipa_ecm_msg *msg); +#endif +void ipa_eth_ntn3_get_status(struct ipa_ntn3_client_stats *s, unsigned inst_id); +void ipa3_eth_get_status(u32 client, int scratch_id, + struct ipa3_eth_error_stats *stats); +int ipa3_get_gsi_chan_info(struct gsi_chan_info *gsi_chan_info, + unsigned long chan_hdl); +enum ipa_client_type ipa_eth_get_ipa_client_type_from_eth_type( + enum ipa_eth_client_type eth_client_type, enum ipa_eth_pipe_direction dir); + +bool ipa_eth_client_exist(enum ipa_eth_client_type eth_client_type, int inst_id); + +int ipa3_disable_apps_wan_cons_deaggr(uint32_t agg_size, uint32_t agg_count); + +#if IS_ENABLED(CONFIG_IPA3_MHI_PRIME_MANAGER) +int ipa_mpm_init(void); +void ipa_mpm_exit(void); +int ipa_mpm_mhip_xdci_pipe_enable(enum ipa_usb_teth_prot prot); +int ipa_mpm_mhip_xdci_pipe_disable(enum ipa_usb_teth_prot xdci_teth_prot); +int ipa_mpm_notify_wan_state(struct wan_ioctl_notify_wan_state *state); +int ipa3_is_mhip_offload_enabled(void); +int ipa_mpm_reset_dma_mode(enum ipa_client_type src_pipe, + enum ipa_client_type dst_pipe); +int ipa_mpm_panic_handler(char *buf, int size); +int ipa3_mpm_enable_adpl_over_odl(bool enable); +int ipa3_get_mhip_gsi_stats(struct ipa_uc_dbg_ring_stats *stats); +#else /* IS_ENABLED(CONFIG_IPA3_MHI_PRIME_MANAGER) */ +static inline int ipa_mpm_init(void) +{ + return 0; +} +static inline void ipa_mpm_exit(void) +{ + return; +} +static inline int ipa_mpm_mhip_xdci_pipe_enable( + enum ipa_usb_teth_prot prot) +{ + return 0; +} +static inline int ipa_mpm_mhip_xdci_pipe_disable( + enum ipa_usb_teth_prot xdci_teth_prot) +{ + return 0; +} +static inline int ipa_mpm_notify_wan_state( + struct wan_ioctl_notify_wan_state *state) +{ + return 0; +} +static inline int ipa3_is_mhip_offload_enabled(void) +{ + return 0; +} +static inline int ipa_mpm_reset_dma_mode(enum ipa_client_type src_pipe, + enum ipa_client_type dst_pipe) +{ + return 0; +} +static inline int ipa_mpm_panic_handler(char *buf, int size) +{ + return 0; +} + +static inline int ipa3_get_mhip_gsi_stats(struct ipa_uc_dbg_ring_stats *stats) +{ + return 0; +} + +static inline int ipa3_mpm_enable_adpl_over_odl(bool enable) +{ + return 0; +} +#endif /* IS_ENABLED(CONFIG_IPA3_MHI_PRIME_MANAGER) */ + +static inline void *alloc_and_init(u32 size, u32 init_val) +{ + void *ptr = kmalloc(size, GFP_KERNEL); + + if (ptr) + memset(ptr, init_val, size); + + return ptr; +} + +/** + * The following used as defaults for struct ipa_ioc_coal_evict_policy. + */ +#define IPA_COAL_VP_LRU_THRSHLD 0 +#define IPA_COAL_EVICTION_EN true +#define IPA_COAL_VP_LRU_GRAN_SEL 0 +#define IPA_COAL_VP_LRU_UDP_THRSHLD 0 +#define IPA_COAL_VP_LRU_TCP_THRSHLD 0 +#define IPA_COAL_VP_LRU_UDP_THRSHLD_EN 1 +#define IPA_COAL_VP_LRU_TCP_THRSHLD_EN 1 +#define IPA_COAL_VP_LRU_TCP_NUM 0 + +/** + * enum ipa_evict_time_gran_type - Time granularity to be used with + * eviction timers. + */ +enum ipa_evict_time_gran_type { + IPA_EVICT_TIME_GRAN_0, + IPA_EVICT_TIME_GRAN_1, + IPA_EVICT_TIME_GRAN_2, + IPA_EVICT_TIME_GRAN_3, +}; + +/* query ipa APQ mode*/ +bool ipa3_is_apq(void); +/* check if odl is connected */ +bool ipa3_is_odl_connected(void); + +int ipa3_uc_send_enable_flow_control(uint16_t gsi_chid, + uint16_t redMarkerThreshold); +int ipa3_uc_send_disable_flow_control(void); +int ipa3_uc_send_update_flow_control(uint32_t bitmask, + uint8_t add_delete); + +bool ipa_is_test_prod_flt_in_sram_internal(enum ipa_ip_type ip); +/* check if modem is up */ +bool ipa3_is_modem_up(void); +/* set modem is up */ +void ipa3_set_modem_up(bool is_up); +int ipa3_qmi_reg_dereg_for_bw(bool bw_reg_dereg); + +/* + * To check if the eogre is worthy of sending to recipients who would + * use the data. + */ +int ipa3_check_eogre( + struct ipa_ioc_eogre_info *eogre_info, + bool *send2uC, + bool *send2ipacm ); + +/* + * To send map information to uC + */ +int ipa3_add_dscp_vlan_pcp_map( + struct IpaDscpVlanPcpMap_t *map ); + +/* + * To send enable/disable information to ipacm + */ +int ipa3_send_eogre_info( + enum ipa_eogre_event etype, + struct ipa_ioc_eogre_info *info ); + +/* update mhi ctrl pipe state */ +void ipa3_update_mhi_ctrl_state(u8 state, bool set); +/* Send MHI endpoint info to modem using QMI indication message */ +int ipa_send_mhi_endp_ind_to_modem(void); + +/* + * To pass macsec mapping to the IPACM + */ +int ipa3_send_macsec_info(enum ipa_macsec_event event_type, struct ipa_macsec_map *map); + +/* Peripheral stats APIs */ +/* Non periodic/Event based stats update */ +int ipa3_update_usb_per_stats(enum ipa_per_stats_type_e stats_type, uint32_t data); +int ipa3_update_pcie_per_stats(enum ipa_per_stats_type_e stats_type, uint32_t data); +int ipa3_update_wifi_per_stats(enum ipa_per_stats_type_e stats_type, uint32_t data); +int ipa3_update_eth_per_stats(enum ipa_per_stats_type_e stats_type, uint32_t data); +int ipa3_update_apps_per_stats(enum ipa_per_stats_type_e stats_type, uint32_t data); +/* Periodic stats update */ +int ipa3_update_client_holb_per_stats(enum ipa_per_stats_type_e stats_type, uint32_t data); +int ipa3_update_dma_per_stats(enum ipa_per_stats_type_e stats_type, uint32_t data); + +/* XR-IPA API's */ +#ifdef CONFIG_IPA_RTP +int ipa3_uc_send_tuple_info_cmd(struct traffic_tuple_info *data); +int ipa3_alloc_temp_buffs_to_uc(unsigned int size, unsigned int no_of_buffs); +int ipa3_map_buff_to_device_addr(struct map_buffer *map_buffs); +int ipa3_unmap_buff_from_device_addr(struct unmap_buffer *unmap_buffs); +int ipa3_send_bitstream_buff_info(struct bitstream_buffers *data); +int ipa3_tuple_info_cmd_to_wlan_uc(struct traffic_tuple_info *req, u32 stream_id); +int ipa3_uc_send_remove_stream_cmd(struct remove_bitstream_buffers *data); +int ipa3_create_hfi_send_uc(void); +int ipa3_allocate_uc_pipes_er_tr_send_to_uc(void); +void ipa3_free_uc_temp_buffs(unsigned int no_of_buffs); +void ipa3_free_uc_pipes_er_tr(void); +int ipa3_uc_send_add_bitstream_buffers_cmd(struct bitstream_buffers_to_uc *data); +#endif +#endif /* _IPA3_I_H_ */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_interrupts.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_interrupts.c new file mode 100644 index 0000000000..d7d0f2a878 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_interrupts.c @@ -0,0 +1,744 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2014-2019, The Linux Foundation. All rights reserved. + */ + +#include +#include "ipa_i.h" + +#define INTERRUPT_WORKQUEUE_NAME "ipa_interrupt_wq" +#define DIS_SUSPEND_INTERRUPT_TIMEOUT 5 +#define IPA_IRQ_NUM_MAX 32 +#define IPA_AGG_BUSY_TIMEOUT (msecs_to_jiffies(5)) + +struct ipa3_interrupt_info { + ipa_irq_handler_t handler; + enum ipa_irq_type interrupt; + void *private_data; + bool deferred_flag; +}; + +struct ipa3_interrupt_work_wrap { + struct work_struct interrupt_work; + ipa_irq_handler_t handler; + enum ipa_irq_type interrupt; + void *private_data; + void *interrupt_data; +}; + +static struct ipa3_interrupt_info ipa_interrupt_to_cb[IPA_IRQ_NUM_MAX]; +static struct workqueue_struct *ipa_interrupt_wq; +static u32 ipa_ee; + +static void ipa3_tx_suspend_interrupt_wa(void); +static void ipa3_enable_tx_suspend_wa(struct work_struct *work); +static DECLARE_DELAYED_WORK(dwork_en_suspend_int, + ipa3_enable_tx_suspend_wa); +static spinlock_t suspend_wa_lock; +static void ipa3_process_interrupts(bool isr_context); + +static int ipa3_irq_mapping[IPA_IRQ_MAX] = { + [IPA_BAD_SNOC_ACCESS_IRQ] = 0, + [IPA_UC_IRQ_0] = 2, + [IPA_UC_IRQ_1] = 3, + [IPA_UC_IRQ_2] = 4, + [IPA_UC_IRQ_3] = 5, + [IPA_UC_IN_Q_NOT_EMPTY_IRQ] = 6, + [IPA_UC_RX_CMD_Q_NOT_FULL_IRQ] = 7, + [IPA_PROC_TO_UC_ACK_Q_NOT_EMPTY_IRQ] = 8, + [IPA_RX_ERR_IRQ] = 9, + [IPA_DEAGGR_ERR_IRQ] = 10, + [IPA_TX_ERR_IRQ] = 11, + [IPA_STEP_MODE_IRQ] = 12, + [IPA_PROC_ERR_IRQ] = 13, + [IPA_TX_SUSPEND_IRQ] = 14, + [IPA_TX_HOLB_DROP_IRQ] = 15, + [IPA_BAM_GSI_IDLE_IRQ] = 16, + [IPA_PIPE_YELLOW_MARKER_BELOW_IRQ] = 17, + [IPA_PIPE_RED_MARKER_BELOW_IRQ] = 18, + [IPA_PIPE_YELLOW_MARKER_ABOVE_IRQ] = 19, + [IPA_PIPE_RED_MARKER_ABOVE_IRQ] = 20, + [IPA_UCP_IRQ] = 21, + [IPA_DCMP_IRQ] = 22, + [IPA_GSI_EE_IRQ] = 23, + [IPA_GSI_IPA_IF_TLV_RCVD_IRQ] = 24, + [IPA_GSI_UC_IRQ] = 25, + [IPA_TLV_LEN_MIN_DSM_IRQ] = 26, + [IPA_DRBIP_PKT_EXCEED_MAX_SIZE_IRQ] = 27, + [IPA_DRBIP_DATA_SCTR_CFG_ERROR_IRQ] = 28, + [IPA_DRBIP_IMM_CMD_NO_FLSH_HZRD_IRQ] = 29, +}; + +static void ipa3_interrupt_defer(struct work_struct *work); +static DECLARE_WORK(ipa3_interrupt_defer_work, ipa3_interrupt_defer); + +static void ipa3_deferred_interrupt_work(struct work_struct *work) +{ + struct ipa3_interrupt_work_wrap *work_data = + container_of(work, + struct ipa3_interrupt_work_wrap, + interrupt_work); + IPADBG("call handler from workq for interrupt %d...\n", + work_data->interrupt); + work_data->handler(work_data->interrupt, work_data->private_data, + work_data->interrupt_data); + kfree(work_data->interrupt_data); + kfree(work_data); +} + +static bool ipa3_is_valid_ep(u32 ep_suspend_data, u8 ep_reg_idx) +{ + u32 bmsk = 1; + u32 i = 0; + u32 reg_add = ep_reg_idx << 5; + + for (i = 0; i < ipa3_ctx->ipa_num_pipes; i++) { + if ((ep_suspend_data & bmsk) && + (ipa3_ctx->ep[i + reg_add].valid)) + return true; + bmsk = bmsk << 1; + } + return false; +} + +static int ipa3_handle_interrupt(int irq_num, bool isr_context) +{ + struct ipa3_interrupt_info interrupt_info; + struct ipa3_interrupt_work_wrap *work_data; + u32 suspend_data[IPA_EP_ARR_SIZE]; + void *interrupt_data = NULL; + struct ipa_tx_suspend_irq_data *suspend_interrupt_data = NULL; + int res, i; + bool valid; + + interrupt_info = ipa_interrupt_to_cb[irq_num]; + if (interrupt_info.handler == NULL) { + IPAERR("A callback function wasn't set for interrupt num %d\n", + irq_num); + return -EINVAL; + } + + switch (interrupt_info.interrupt) { + case IPA_TX_SUSPEND_IRQ: + IPADBG_LOW("processing TX_SUSPEND interrupt\n"); + ipa3_tx_suspend_interrupt_wa(); + valid = 0; + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0) { + for (i = 0; i < IPA_EP_ARR_SIZE; i++) { + suspend_data[i] = ipahal_read_reg_nk( + IPA_SUSPEND_IRQ_INFO_EE_n_REG_k, + ipa_ee, i); + if (ipa3_is_valid_ep(suspend_data[i], i)) + valid = true; + IPADBG_LOW("get interrupt %d\n", + suspend_data[i]); + + /* Clearing L2 interrupts status */ + ipahal_write_reg_nk( + IPA_SUSPEND_IRQ_CLR_EE_n_REG_k, + ipa_ee, i, suspend_data[i]); + } + } else { + suspend_data[0] = ipahal_read_reg_n( + IPA_SUSPEND_IRQ_INFO_EE_n, + ipa_ee); + if (ipa3_is_valid_ep(suspend_data[0], 0)) + valid = true; + IPADBG_LOW("get interrupt %d\n", suspend_data[0]); + + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v3_1) { + /* Clearing L2 interrupts status */ + ipahal_write_reg_n(IPA_SUSPEND_IRQ_CLR_EE_n, + ipa_ee, suspend_data[0]); + } + } + if (!valid) + return 0; + + suspend_interrupt_data = + kzalloc(sizeof(*suspend_interrupt_data), GFP_ATOMIC); + if (!suspend_interrupt_data) { + IPAERR("failed allocating suspend_interrupt_data\n"); + return -ENOMEM; + } + + for (i = 0; i < IPA_EP_ARR_SIZE; i++) + suspend_interrupt_data->endpoints[i] = suspend_data[i]; + interrupt_data = suspend_interrupt_data; + break; + case IPA_UC_IRQ_0: + if (ipa3_ctx->apply_rg10_wa) { + /* + * Early detect of uC crash. If RG10 workaround is + * enable uC crash will not be detected as before + * processing uC event the interrupt is cleared using + * uC register write which times out as it crashed + * already. + */ + if (ipa3_ctx->uc_ctx.uc_sram_mmio->eventOp == + IPA_HW_2_CPU_EVENT_ERROR) + ipa3_ctx->uc_ctx.uc_failed = true; + } + break; + default: + break; + } + + /* Force defer processing if in ISR context. */ + if (interrupt_info.deferred_flag || isr_context) { + IPADBG_LOW("Defer handling interrupt %d\n", + interrupt_info.interrupt); + work_data = kzalloc(sizeof(struct ipa3_interrupt_work_wrap), + GFP_ATOMIC); + if (!work_data) { + IPAERR("failed allocating ipa3_interrupt_work_wrap\n"); + res = -ENOMEM; + goto fail_alloc_work; + } + INIT_WORK(&work_data->interrupt_work, + ipa3_deferred_interrupt_work); + work_data->handler = interrupt_info.handler; + work_data->interrupt = interrupt_info.interrupt; + work_data->private_data = interrupt_info.private_data; + work_data->interrupt_data = interrupt_data; + queue_work(ipa_interrupt_wq, &work_data->interrupt_work); + + } else { + IPADBG_LOW("Handle interrupt %d\n", interrupt_info.interrupt); + interrupt_info.handler(interrupt_info.interrupt, + interrupt_info.private_data, + interrupt_data); + kfree(interrupt_data); + } + + return 0; + +fail_alloc_work: + kfree(interrupt_data); + return res; +} + +static void ipa3_enable_tx_suspend_wa(struct work_struct *work) +{ + u32 en; + u32 suspend_bmask; + int irq_num; + + IPADBG_LOW("Enter\n"); + + irq_num = ipa3_irq_mapping[IPA_TX_SUSPEND_IRQ]; + + if (irq_num == -1) { + WARN_ON(1); + return; + } + + /* make sure ipa hw is clocked on*/ + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + + en = ipahal_read_reg_n(IPA_IRQ_EN_EE_n, ipa_ee); + suspend_bmask = 1 << irq_num; + /*enable TX_SUSPEND_IRQ*/ + en |= suspend_bmask; + IPADBG("enable TX_SUSPEND_IRQ, IPA_IRQ_EN_EE reg, write val = %u\n" + , en); + if (ipa3_ctx->apply_rg10_wa) + ipa3_uc_rg10_write_reg(IPA_IRQ_EN_EE_n, ipa_ee, en); + else + ipahal_write_reg_n(IPA_IRQ_EN_EE_n, ipa_ee, en); + ipa3_process_interrupts(false); + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + + IPADBG_LOW("Exit\n"); +} + +static void ipa3_tx_suspend_interrupt_wa(void) +{ + u32 val; + u32 suspend_bmask; + int irq_num; + int wa_delay; + + IPADBG_LOW("Enter\n"); + irq_num = ipa3_irq_mapping[IPA_TX_SUSPEND_IRQ]; + + if (irq_num == -1) { + WARN_ON(1); + return; + } + + /*disable TX_SUSPEND_IRQ*/ + val = ipahal_read_reg_n(IPA_IRQ_EN_EE_n, ipa_ee); + suspend_bmask = 1 << irq_num; + val &= ~suspend_bmask; + IPADBG("Disabling TX_SUSPEND_IRQ, write val: %u to IPA_IRQ_EN_EE reg\n", + val); + if (ipa3_ctx->apply_rg10_wa) + ipa3_uc_rg10_write_reg(IPA_IRQ_EN_EE_n, ipa_ee, val); + else + ipahal_write_reg_n(IPA_IRQ_EN_EE_n, ipa_ee, val); + + IPADBG_LOW(" processing suspend interrupt work-around, delayed work\n"); + + wa_delay = DIS_SUSPEND_INTERRUPT_TIMEOUT; + if (ipa3_ctx->ipa3_hw_mode == IPA_HW_MODE_VIRTUAL || + ipa3_ctx->ipa3_hw_mode == IPA_HW_MODE_EMULATION) { + wa_delay *= 400; + } + + IPADBG_LOW("Delay period %d msec\n", wa_delay); + + queue_delayed_work(ipa_interrupt_wq, &dwork_en_suspend_int, + msecs_to_jiffies(wa_delay)); + + IPADBG_LOW("Exit\n"); +} + +static inline bool is_uc_irq(int irq_num) +{ + if (ipa_interrupt_to_cb[irq_num].interrupt >= IPA_UC_IRQ_0 && + ipa_interrupt_to_cb[irq_num].interrupt <= IPA_UC_IRQ_3) + return true; + else + return false; +} + +static void ipa3_process_interrupts(bool isr_context) +{ + u32 reg; + u32 bmsk; + u32 i = 0; + u32 en; + unsigned long flags; + bool uc_irq; + + IPADBG_LOW("Enter isr_context=%d\n", isr_context); + + spin_lock_irqsave(&suspend_wa_lock, flags); + en = ipahal_read_reg_n(IPA_IRQ_EN_EE_n, ipa_ee); + reg = ipahal_read_reg_n(IPA_IRQ_STTS_EE_n, ipa_ee); + while (en & reg) { + IPADBG_LOW("en=0x%x reg=0x%x\n", en, reg); + bmsk = 1; + for (i = 0; i < IPA_IRQ_NUM_MAX; i++) { + IPADBG_LOW("Check irq number %d\n", i); + if (en & reg & bmsk) { + IPADBG_LOW("Irq number %d asserted\n", i); + uc_irq = is_uc_irq(i); + + /* + * Clear uC interrupt before processing to avoid + * clearing unhandled interrupts + */ + if (uc_irq) { + if (ipa3_ctx->apply_rg10_wa) + ipa3_uc_rg10_write_reg(IPA_IRQ_CLR_EE_n, + ipa_ee, bmsk); + else + ipahal_write_reg_n(IPA_IRQ_CLR_EE_n, + ipa_ee, bmsk); + } + + /* + * handle the interrupt with spin_lock + * unlocked to avoid calling client in atomic + * context. mutual exclusion still preserved + * as the read/clr is done with spin_lock + * locked. + */ + spin_unlock_irqrestore(&suspend_wa_lock, flags); + ipa3_handle_interrupt(i, isr_context); + spin_lock_irqsave(&suspend_wa_lock, flags); + + /* + * Clear non uC interrupt after processing + * to avoid clearing interrupt data + */ + if (!uc_irq) { + if (ipa3_ctx->apply_rg10_wa) + ipa3_uc_rg10_write_reg(IPA_IRQ_CLR_EE_n, + ipa_ee, bmsk); + else + ipahal_write_reg_n(IPA_IRQ_CLR_EE_n, + ipa_ee, bmsk); + } + } + bmsk = bmsk << 1; + } + /* + * In case uC failed interrupt cannot be cleared. + * Device will crash as part of handling uC event handler. + */ + if (ipa3_ctx->apply_rg10_wa && ipa3_ctx->uc_ctx.uc_failed) + break; + + reg = ipahal_read_reg_n(IPA_IRQ_STTS_EE_n, ipa_ee); + /* since the suspend interrupt HW bug we must + * read again the EN register, otherwise the while is endless + */ + en = ipahal_read_reg_n(IPA_IRQ_EN_EE_n, ipa_ee); + } + + spin_unlock_irqrestore(&suspend_wa_lock, flags); + IPADBG_LOW("Exit\n"); +} + +static void ipa3_interrupt_defer(struct work_struct *work) +{ + struct ipa_active_client_logging_info log_info; + + IPADBG("processing interrupts in wq\n"); + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + ipa3_process_interrupts(false); + IPA_ACTIVE_CLIENTS_PREP_SIMPLE(log_info); + /* Delay the devote process to have time to get gsi ieob irq */ + ipa3_dec_client_disable_clks_delay_wq(&log_info, IPA_AGG_BUSY_TIMEOUT); + IPADBG("Done\n"); +} + +static irqreturn_t ipa3_isr(int irq, void *ctxt) +{ + struct ipa_active_client_logging_info log_info; + + IPA_ACTIVE_CLIENTS_PREP_SIMPLE(log_info); + IPADBG_LOW("Enter\n"); + /* defer interrupt handling in case IPA is not clocked on */ + if (ipa3_inc_client_enable_clks_no_block(&log_info)) { + IPADBG("defer interrupt processing\n"); + queue_work(ipa3_ctx->power_mgmt_wq, &ipa3_interrupt_defer_work); + return IRQ_HANDLED; + } + + ipa3_process_interrupts(true); + IPADBG_LOW("Exit\n"); + + ipa3_dec_client_disable_clks_no_block(&log_info); + return IRQ_HANDLED; +} + +irq_handler_t ipa3_get_isr(void) +{ + return ipa3_isr; +} + +/** + * ipa_add_interrupt_handler() - Adds handler to an interrupt type + * @interrupt: Interrupt type + * @handler: The handler to be added + * @deferred_flag: whether the handler processing should be deferred in + * a workqueue + * @private_data: the client's private data + * + * Adds handler to an interrupt type and enable the specific bit + * in IRQ_EN register, associated interrupt in IRQ_STTS register will be enabled + */ +int ipa_add_interrupt_handler(enum ipa_irq_type interrupt, + ipa_irq_handler_t handler, + bool deferred_flag, + void *private_data) +{ + u32 val, i; + u32 pipe_bmsk[IPA_EP_ARR_SIZE] = {0, 0}; + u32 bmsk; + int irq_num; + int client_idx, ep_idx; + + IPADBG("interrupt_enum(%d)\n", interrupt); + if (interrupt < IPA_BAD_SNOC_ACCESS_IRQ || + interrupt >= IPA_IRQ_MAX) { + IPAERR("invalid interrupt number %d\n", interrupt); + return -EINVAL; + } + + irq_num = ipa3_irq_mapping[interrupt]; + if (irq_num < 0 || irq_num >= IPA_IRQ_NUM_MAX) { + IPAERR("interrupt %d not supported\n", interrupt); + WARN_ON(1); + return -EFAULT; + } + IPADBG("ipa_interrupt_to_cb irq_num(%d)\n", irq_num); + + ipa_interrupt_to_cb[irq_num].deferred_flag = deferred_flag; + ipa_interrupt_to_cb[irq_num].handler = handler; + ipa_interrupt_to_cb[irq_num].private_data = private_data; + ipa_interrupt_to_cb[irq_num].interrupt = interrupt; + + val = ipahal_read_reg_n(IPA_IRQ_EN_EE_n, ipa_ee); + IPADBG("read IPA_IRQ_EN_EE_n register. reg = %d\n", val); + bmsk = 1 << irq_num; + val |= bmsk; + if (ipa3_ctx->apply_rg10_wa) + ipa3_uc_rg10_write_reg(IPA_IRQ_EN_EE_n, ipa_ee, val); + else + ipahal_write_reg_n(IPA_IRQ_EN_EE_n, ipa_ee, val); + IPADBG("wrote IPA_IRQ_EN_EE_n register. reg = %d\n", val); + + /* register SUSPEND_IRQ_EN_EE_n_ADDR for L2 interrupt*/ + if ((interrupt == IPA_TX_SUSPEND_IRQ) && + (ipa3_ctx->ipa_hw_type >= IPA_HW_v3_1)) { + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0) { + for (client_idx = 0; + client_idx < IPA_CLIENT_MAX; + client_idx++) { + ep_idx = ipa_get_ep_mapping(client_idx); + if ((ep_idx != IPA_EP_NOT_ALLOCATED) && + !(IPA_CLIENT_IS_Q6_CONS(client_idx) || + IPA_CLIENT_IS_Q6_PROD(client_idx))) { + pipe_bmsk[ipahal_get_ep_reg_idx(ep_idx)] |= + ipahal_get_ep_bit(ep_idx); + } + } + for (i = 0; i < IPA_EP_ARR_SIZE; i++) { + ipahal_write_reg_nk( + IPA_SUSPEND_IRQ_EN_EE_n_REG_k, + ipa_ee, i, pipe_bmsk[i]); + IPADBG( + "wrote IPA_SUSPEND_IRQ_EN_EE_n_REG_k m = %u pipe_bmsk[i] = %d\n" + , i, pipe_bmsk[i]); + } + } else { + val = ~0; + for (client_idx = 0; + client_idx < IPA_CLIENT_MAX; + client_idx++) { + if (IPA_CLIENT_IS_Q6_CONS(client_idx) || + IPA_CLIENT_IS_Q6_PROD(client_idx)) { + ep_idx = ipa_get_ep_mapping(client_idx); + IPADBG( + "modem ep_idx(%d) client_idx = %d\n" + , ep_idx, client_idx); + if (ep_idx == -1) + IPADBG("Invalid IPA client\n"); + else + val &= ~(1 << ep_idx); + } + } + + ipahal_write_reg_n(IPA_SUSPEND_IRQ_EN_EE_n, ipa_ee, val); + IPADBG("wrote IPA_SUSPEND_IRQ_EN_EE_n reg = %d\n", val); + } + } + return 0; +} +EXPORT_SYMBOL(ipa_add_interrupt_handler); + +/** + * ipa3_remove_interrupt_handler() - Removes handler to an interrupt type + * @interrupt: Interrupt type + * + * Removes the handler and disable the specific bit in IRQ_EN register + */ +int ipa3_remove_interrupt_handler(enum ipa_irq_type interrupt) +{ + u32 val, i; + u32 bmsk; + int irq_num; + + if (interrupt < IPA_BAD_SNOC_ACCESS_IRQ || + interrupt >= IPA_IRQ_MAX) { + IPAERR("invalid interrupt number %d\n", interrupt); + return -EINVAL; + } + + irq_num = ipa3_irq_mapping[interrupt]; + if (irq_num < 0 || irq_num >= IPA_IRQ_NUM_MAX) { + IPAERR("interrupt %d not supported\n", interrupt); + WARN_ON(1); + return -EFAULT; + } + + /*If free ipa3_ctx pointer causing device crash during remove interrupt*/ + if(ipa_interrupt_to_cb[irq_num].private_data != ipa3_ctx) + kfree(ipa_interrupt_to_cb[irq_num].private_data); + ipa_interrupt_to_cb[irq_num].deferred_flag = false; + ipa_interrupt_to_cb[irq_num].handler = NULL; + ipa_interrupt_to_cb[irq_num].private_data = NULL; + ipa_interrupt_to_cb[irq_num].interrupt = -1; + + /* clean SUSPEND_IRQ_EN_EE_n_ADDR for L2 interrupt */ + if ((interrupt == IPA_TX_SUSPEND_IRQ) && + (ipa3_ctx->ipa_hw_type >= IPA_HW_v3_1)) { + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0) { + for (i = 0; i < IPA_EP_ARR_SIZE; i++) { + ipahal_write_reg_nk( + IPA_SUSPEND_IRQ_EN_EE_n_REG_k, + ipa_ee, i, 0); + IPADBG( + "wrote IPA_SUSPEND_IRQ_EN_EE_n_REG_k k %u val = %d\n" + , i, 0); + } + } else { + ipahal_write_reg_n(IPA_SUSPEND_IRQ_EN_EE_n, ipa_ee, 0); + IPADBG("wrote IPA_SUSPEND_IRQ_EN_EE_n reg = %d\n", 0); + } + } + + val = ipahal_read_reg_n(IPA_IRQ_EN_EE_n, ipa_ee); + bmsk = 1 << irq_num; + val &= ~bmsk; + if (ipa3_ctx->apply_rg10_wa) + ipa3_uc_rg10_write_reg(IPA_IRQ_EN_EE_n, ipa_ee, val); + else + ipahal_write_reg_n(IPA_IRQ_EN_EE_n, ipa_ee, val); + + return 0; +} + +/** + * ipa3_interrupts_init() - Initialize the IPA interrupts framework + * @ipa_irq: The interrupt number to allocate + * @ee: Execution environment + * @ipa_dev: The basic device structure representing the IPA driver + * + * - Initialize the ipa_interrupt_to_cb array + * - Clear interrupts status + * - Register the ipa interrupt handler - ipa3_isr + * - Enable apps processor wakeup by IPA interrupts + */ +int ipa3_interrupts_init(u32 ipa_irq, u32 ee, struct device *ipa_dev) +{ + int idx; + int res = 0; + + ipa_ee = ee; + for (idx = 0; idx < IPA_IRQ_NUM_MAX; idx++) { + ipa_interrupt_to_cb[idx].deferred_flag = false; + ipa_interrupt_to_cb[idx].handler = NULL; + ipa_interrupt_to_cb[idx].private_data = NULL; + ipa_interrupt_to_cb[idx].interrupt = -1; + } + + ipa_interrupt_wq = create_singlethread_workqueue( + INTERRUPT_WORKQUEUE_NAME); + if (!ipa_interrupt_wq) { + IPAERR("workqueue creation failed\n"); + return -ENOMEM; + } + + /* + * NOTE: + * + * We'll only register an isr on non-emulator (ie. real UE) + * systems. + * + * On the emulator, emulator_soft_irq_isr() will be calling + * ipa3_isr, so hence, no isr registration here, and instead, + * we'll pass the address of ipa3_isr to the gsi layer where + * emulator interrupts are handled... + */ + if (ipa3_ctx->ipa3_hw_mode != IPA_HW_MODE_EMULATION) { + res = request_irq(ipa_irq, (irq_handler_t) ipa3_isr, + IRQF_TRIGGER_RISING, "ipa", ipa_dev); + if (res) { + IPAERR( + "fail to register IPA IRQ handler irq=%d\n", + ipa_irq); + destroy_workqueue(ipa_interrupt_wq); + ipa_interrupt_wq = NULL; + return -ENODEV; + } + IPADBG("IPA IRQ handler irq=%d registered\n", ipa_irq); + + res = enable_irq_wake(ipa_irq); + if (res) + IPAERR("fail to enable IPA IRQ wakeup irq=%d res=%d\n", + ipa_irq, res); + else + IPADBG("IPA IRQ wakeup enabled irq=%d\n", ipa_irq); + } + spin_lock_init(&suspend_wa_lock); + return 0; +} + +/** + * ipa3_interrupts_destroy() - Destroy the IPA interrupts framework + * @ipa_irq: The interrupt number to allocate + * @ee: Execution environment + * @ipa_dev: The basic device structure representing the IPA driver + * + * - Disable apps processor wakeup by IPA interrupts + * - Unregister the ipa interrupt handler - ipa3_isr + * - Destroy the interrupt workqueue + */ +void ipa3_interrupts_destroy(u32 ipa_irq, struct device *ipa_dev) +{ + if (ipa3_ctx->ipa3_hw_mode != IPA_HW_MODE_EMULATION) { + disable_irq_wake(ipa_irq); + free_irq(ipa_irq, ipa_dev); + } + destroy_workqueue(ipa_interrupt_wq); + ipa_interrupt_wq = NULL; +} + +/** + * ipa3_suspend_active_aggr_wa() - Emulate suspend IRQ + * @clnt_hndl: suspended client handle, IRQ is emulated for this pipe + * + * Emulate suspend IRQ to unsuspend client which was suspended with an open + * aggregation frame in order to bypass HW bug of IRQ not generated when + * endpoint is suspended during an open aggregation. + */ +void ipa3_suspend_active_aggr_wa(u32 clnt_hdl) +{ + struct ipa3_interrupt_info interrupt_info; + struct ipa3_interrupt_work_wrap *work_data; + struct ipa_tx_suspend_irq_data *suspend_interrupt_data; + int irq_num; + int aggr_active_bitmap; + + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0) { + aggr_active_bitmap = + ipahal_read_ep_reg(IPA_STATE_AGGR_ACTIVE_n, + clnt_hdl); + } else { + aggr_active_bitmap = + ipahal_read_reg(IPA_STATE_AGGR_ACTIVE); + } + + if (ipahal_test_ep_bit(aggr_active_bitmap, clnt_hdl)) { + /* force close aggregation */ + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0) + ipahal_write_ep_reg(IPA_AGGR_FORCE_CLOSE_n, + clnt_hdl, + ipahal_get_ep_bit(clnt_hdl)); + else + ipahal_write_reg(IPA_AGGR_FORCE_CLOSE, + ipahal_get_ep_bit(clnt_hdl)); + + /* simulate suspend IRQ */ + irq_num = ipa3_irq_mapping[IPA_TX_SUSPEND_IRQ]; + interrupt_info = ipa_interrupt_to_cb[irq_num]; + if (interrupt_info.handler == NULL) { + IPAERR("no CB function for IPA_TX_SUSPEND_IRQ\n"); + return; + } + suspend_interrupt_data = kzalloc( + sizeof(*suspend_interrupt_data), + GFP_ATOMIC); + if (!suspend_interrupt_data) { + IPAERR("failed allocating suspend_interrupt_data\n"); + return; + } + suspend_interrupt_data->endpoints[ + ipahal_get_ep_reg_idx(clnt_hdl) + ] = + ipahal_get_ep_bit(clnt_hdl); + + work_data = kzalloc(sizeof(struct ipa3_interrupt_work_wrap), + GFP_ATOMIC); + if (!work_data) { + IPAERR("failed allocating ipa3_interrupt_work_wrap\n"); + goto fail_alloc_work; + } + INIT_WORK(&work_data->interrupt_work, + ipa3_deferred_interrupt_work); + work_data->handler = interrupt_info.handler; + work_data->interrupt = IPA_TX_SUSPEND_IRQ; + work_data->private_data = interrupt_info.private_data; + work_data->interrupt_data = (void *)suspend_interrupt_data; + queue_work(ipa_interrupt_wq, &work_data->interrupt_work); + return; +fail_alloc_work: + kfree(suspend_interrupt_data); + } +} diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_intf.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_intf.c new file mode 100644 index 0000000000..1d88702611 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_intf.c @@ -0,0 +1,823 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2013-2019, The Linux Foundation. All rights reserved. + * + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include "ipa_i.h" +#include + +struct ipa3_intf { + char name[IPA_RESOURCE_NAME_MAX]; + struct list_head link; + u32 num_tx_props; + u32 num_rx_props; + u32 num_ext_props; + struct ipa_ioc_tx_intf_prop *tx; + struct ipa_ioc_rx_intf_prop *rx; + struct ipa_ioc_ext_intf_prop *ext; + enum ipa_client_type excp_pipe; +}; + +struct ipa3_push_msg { + struct ipa_msg_meta meta; + ipa_msg_free_fn callback; + void *buff; + struct list_head link; +}; + +struct ipa3_pull_msg { + struct ipa_msg_meta meta; + ipa_msg_pull_fn callback; + struct list_head link; +}; + +/** + * ipa3_register_intf() - register "logical" interface + * @name: [in] interface name + * @tx: [in] TX properties of the interface + * @rx: [in] RX properties of the interface + * + * Register an interface and its tx and rx properties, this allows + * configuration of rules from user-space + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa_register_intf(const char *name, const struct ipa_tx_intf *tx, + const struct ipa_rx_intf *rx) +{ + return ipa3_register_intf_ext(name, tx, rx, NULL); +} +EXPORT_SYMBOL(ipa_register_intf); + +/** + * ipa3_register_intf_ext() - register "logical" interface which has only + * extended properties + * @name: [in] interface name + * @tx: [in] TX properties of the interface + * @rx: [in] RX properties of the interface + * @ext: [in] EXT properties of the interface + * + * Register an interface and its tx, rx and ext properties, this allows + * configuration of rules from user-space + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_register_intf_ext(const char *name, const struct ipa_tx_intf *tx, + const struct ipa_rx_intf *rx, + const struct ipa_ext_intf *ext) +{ + struct ipa3_intf *intf; + u32 len; + + if (name == NULL || (tx == NULL && rx == NULL && ext == NULL)) { + IPAERR_RL("invalid params name=%pK tx=%pK rx=%pK ext=%pK\n", + name, tx, rx, ext); + return -EINVAL; + } + + if (tx && tx->num_props > IPA_NUM_PROPS_MAX) { + IPAERR_RL("invalid tx num_props=%d max=%d\n", tx->num_props, + IPA_NUM_PROPS_MAX); + return -EINVAL; + } + + if (rx && rx->num_props > IPA_NUM_PROPS_MAX) { + IPAERR_RL("invalid rx num_props=%d max=%d\n", rx->num_props, + IPA_NUM_PROPS_MAX); + return -EINVAL; + } + + if (ext && ext->num_props > IPA_NUM_PROPS_MAX) { + IPAERR_RL("invalid ext num_props=%d max=%d\n", ext->num_props, + IPA_NUM_PROPS_MAX); + return -EINVAL; + } + + len = sizeof(struct ipa3_intf); + intf = kzalloc(len, GFP_KERNEL); + if (intf == NULL) + return -ENOMEM; + + strlcpy(intf->name, name, IPA_RESOURCE_NAME_MAX); + + if (tx) { + intf->num_tx_props = tx->num_props; + len = tx->num_props * sizeof(struct ipa_ioc_tx_intf_prop); + intf->tx = kmemdup(tx->prop, len, GFP_KERNEL); + if (intf->tx == NULL) { + kfree(intf); + return -ENOMEM; + } + } + + if (rx) { + intf->num_rx_props = rx->num_props; + len = rx->num_props * sizeof(struct ipa_ioc_rx_intf_prop); + intf->rx = kmemdup(rx->prop, len, GFP_KERNEL); + if (intf->rx == NULL) { + kfree(intf->tx); + kfree(intf); + return -ENOMEM; + } + memcpy(intf->rx, rx->prop, len); + } + + if (ext) { + intf->num_ext_props = ext->num_props; + len = ext->num_props * sizeof(struct ipa_ioc_ext_intf_prop); + intf->ext = kmemdup(ext->prop, len, GFP_KERNEL); + if (intf->ext == NULL) { + kfree(intf->rx); + kfree(intf->tx); + kfree(intf); + return -ENOMEM; + } + memcpy(intf->ext, ext->prop, len); + } + + if (ext && ext->excp_pipe_valid) + intf->excp_pipe = ext->excp_pipe; + else + intf->excp_pipe = IPA_CLIENT_APPS_LAN_CONS; + + mutex_lock(&ipa3_ctx->lock); + list_add_tail(&intf->link, &ipa3_ctx->intf_list); + mutex_unlock(&ipa3_ctx->lock); + + return 0; +} + +/** + * ipa_deregister_intf() - de-register previously registered logical interface + * @name: [in] interface name + * + * De-register a previously registered interface + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa_deregister_intf(const char *name) +{ + struct ipa3_intf *entry; + struct ipa3_intf *next; + int result = -EINVAL; + + if ((name == NULL) || + (strnlen(name, IPA_RESOURCE_NAME_MAX) == IPA_RESOURCE_NAME_MAX)) { + IPAERR_RL("invalid param name=%s\n", name); + return result; + } + + mutex_lock(&ipa3_ctx->lock); + list_for_each_entry_safe(entry, next, &ipa3_ctx->intf_list, link) { + if (!strcmp(entry->name, name)) { + list_del(&entry->link); + kfree(entry->ext); + kfree(entry->rx); + kfree(entry->tx); + kfree(entry); + result = 0; + break; + } + } + mutex_unlock(&ipa3_ctx->lock); + + return result; +} +EXPORT_SYMBOL(ipa_deregister_intf); + +/** + * ipa3_query_intf() - query logical interface properties + * @lookup: [inout] interface name and number of properties + * + * Obtain the handle and number of tx and rx properties for the named + * interface, used as part of querying the tx and rx properties for + * configuration of various rules from user-space + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_query_intf(struct ipa_ioc_query_intf *lookup) +{ + struct ipa3_intf *entry; + int result = -EINVAL; + + if (lookup == NULL) { + IPAERR_RL("invalid param lookup=%pK\n", lookup); + return result; + } + + lookup->name[IPA_RESOURCE_NAME_MAX-1] = '\0'; + if (strnlen(lookup->name, IPA_RESOURCE_NAME_MAX) == + IPA_RESOURCE_NAME_MAX) { + IPAERR_RL("Interface name too long. (%s)\n", lookup->name); + return result; + } + + mutex_lock(&ipa3_ctx->lock); + list_for_each_entry(entry, &ipa3_ctx->intf_list, link) { + if (!strcmp(entry->name, lookup->name)) { + lookup->num_tx_props = entry->num_tx_props; + lookup->num_rx_props = entry->num_rx_props; + lookup->num_ext_props = entry->num_ext_props; + lookup->excp_pipe = entry->excp_pipe; + result = 0; + break; + } + } + mutex_unlock(&ipa3_ctx->lock); + + return result; +} + +/** + * ipa3_query_intf_tx_props() - qeury TX props of an interface + * @tx: [inout] interface tx attributes + * + * Obtain the tx properties for the specified interface + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_query_intf_tx_props(struct ipa_ioc_query_intf_tx_props *tx) +{ + struct ipa3_intf *entry; + int result = -EINVAL; + + if (tx == NULL) { + IPAERR_RL("null args: tx\n"); + return result; + } + + tx->name[IPA_RESOURCE_NAME_MAX-1] = '\0'; + if (strnlen(tx->name, IPA_RESOURCE_NAME_MAX) == IPA_RESOURCE_NAME_MAX) { + IPAERR_RL("Interface name too long. (%s)\n", tx->name); + return result; + } + + mutex_lock(&ipa3_ctx->lock); + list_for_each_entry(entry, &ipa3_ctx->intf_list, link) { + if (!strcmp(entry->name, tx->name)) { + /* add the entry check */ + if (entry->num_tx_props != tx->num_tx_props) { + IPAERR("invalid entry number(%u %u)\n", + entry->num_tx_props, + tx->num_tx_props); + mutex_unlock(&ipa3_ctx->lock); + return result; + } + memcpy(tx->tx, entry->tx, entry->num_tx_props * + sizeof(struct ipa_ioc_tx_intf_prop)); + result = 0; + break; + } + } + mutex_unlock(&ipa3_ctx->lock); + + return result; +} + +/** + * ipa3_query_intf_rx_props() - qeury RX props of an interface + * @rx: [inout] interface rx attributes + * + * Obtain the rx properties for the specified interface + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_query_intf_rx_props(struct ipa_ioc_query_intf_rx_props *rx) +{ + struct ipa3_intf *entry; + int result = -EINVAL; + + if (rx == NULL) { + IPAERR_RL("null args: rx\n"); + return result; + } + + rx->name[IPA_RESOURCE_NAME_MAX-1] = '\0'; + if (strnlen(rx->name, IPA_RESOURCE_NAME_MAX) == IPA_RESOURCE_NAME_MAX) { + IPAERR_RL("Interface name too long. (%s)\n", rx->name); + return result; + } + + mutex_lock(&ipa3_ctx->lock); + list_for_each_entry(entry, &ipa3_ctx->intf_list, link) { + if (!strcmp(entry->name, rx->name)) { + /* add the entry check */ + if (entry->num_rx_props != rx->num_rx_props) { + IPAERR("invalid entry number(%u %u)\n", + entry->num_rx_props, + rx->num_rx_props); + mutex_unlock(&ipa3_ctx->lock); + return result; + } + memcpy(rx->rx, entry->rx, entry->num_rx_props * + sizeof(struct ipa_ioc_rx_intf_prop)); + result = 0; + break; + } + } + mutex_unlock(&ipa3_ctx->lock); + + return result; +} + +/** + * ipa3_query_intf_ext_props() - qeury EXT props of an interface + * @ext: [inout] interface ext attributes + * + * Obtain the ext properties for the specified interface + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_query_intf_ext_props(struct ipa_ioc_query_intf_ext_props *ext) +{ + struct ipa3_intf *entry; + int result = -EINVAL; + + if (ext == NULL) { + IPAERR_RL("invalid param ext=%pK\n", ext); + return result; + } + + mutex_lock(&ipa3_ctx->lock); + list_for_each_entry(entry, &ipa3_ctx->intf_list, link) { + if (!strcmp(entry->name, ext->name)) { + /* add the entry check */ + if (entry->num_ext_props != ext->num_ext_props) { + IPAERR("invalid entry number(%u %u)\n", + entry->num_ext_props, + ext->num_ext_props); + mutex_unlock(&ipa3_ctx->lock); + return result; + } + memcpy(ext->ext, entry->ext, entry->num_ext_props * + sizeof(struct ipa_ioc_ext_intf_prop)); + result = 0; + break; + } + } + mutex_unlock(&ipa3_ctx->lock); + return result; +} + +static void ipa_send_msg_free(void *buff, u32 len, u32 type) +{ + kfree(buff); +} + +static int wlan_msg_process(struct ipa_msg_meta *meta, void *buff) +{ + struct ipa3_push_msg *msg_dup; + struct ipa_wlan_msg_ex *event_ex_cur_con = NULL; + struct ipa_wlan_msg_ex *event_ex_list = NULL; + struct ipa_wlan_msg *event_ex_cur_discon = NULL; + void *data_dup = NULL; + struct ipa3_push_msg *entry; + struct ipa3_push_msg *next; + int cnt = 0, total = 0, max = 0; + uint8_t mac[IPA_MAC_ADDR_SIZE]; + uint8_t mac2[IPA_MAC_ADDR_SIZE]; + + if (!buff) + return -EINVAL; + if (meta->msg_type == WLAN_CLIENT_CONNECT_EX) { + /* debug print */ + event_ex_cur_con = buff; + for (cnt = 0; cnt < event_ex_cur_con->num_of_attribs; cnt++) { + if (event_ex_cur_con->attribs[cnt].attrib_type == + WLAN_HDR_ATTRIB_MAC_ADDR) { + IPADBG("%02x:%02x:%02x:%02x:%02x:%02x,(%d)\n", + event_ex_cur_con->attribs[cnt].u.mac_addr[0], + event_ex_cur_con->attribs[cnt].u.mac_addr[1], + event_ex_cur_con->attribs[cnt].u.mac_addr[2], + event_ex_cur_con->attribs[cnt].u.mac_addr[3], + event_ex_cur_con->attribs[cnt].u.mac_addr[4], + event_ex_cur_con->attribs[cnt].u.mac_addr[5], + meta->msg_type); + } + } + + mutex_lock(&ipa3_ctx->msg_wlan_client_lock); + msg_dup = kzalloc(sizeof(*msg_dup), GFP_KERNEL); + if (msg_dup == NULL) { + mutex_unlock(&ipa3_ctx->msg_wlan_client_lock); + return -ENOMEM; + } + msg_dup->meta = *meta; + if (meta->msg_len > 0 && buff) { + data_dup = kmemdup(buff, meta->msg_len, GFP_KERNEL); + if (data_dup == NULL) { + kfree(msg_dup); + mutex_unlock(&ipa3_ctx->msg_wlan_client_lock); + return -ENOMEM; + } + memcpy(data_dup, buff, meta->msg_len); + msg_dup->buff = data_dup; + msg_dup->callback = ipa_send_msg_free; + } else { + IPAERR("msg_len %d\n", meta->msg_len); + kfree(msg_dup); + mutex_unlock(&ipa3_ctx->msg_wlan_client_lock); + return -ENOMEM; + } + list_add_tail(&msg_dup->link, &ipa3_ctx->msg_wlan_client_list); + mutex_unlock(&ipa3_ctx->msg_wlan_client_lock); + } + + /* remove the cache */ + if (meta->msg_type == WLAN_CLIENT_DISCONNECT) { + /* debug print */ + event_ex_cur_discon = buff; + IPADBG("Mac %pM, msg %d\n", + event_ex_cur_discon->mac_addr, + meta->msg_type); + memcpy(mac2, + event_ex_cur_discon->mac_addr, + sizeof(mac2)); + + mutex_lock(&ipa3_ctx->msg_wlan_client_lock); + list_for_each_entry_safe(entry, next, + &ipa3_ctx->msg_wlan_client_list, + link) { + event_ex_list = entry->buff; + max = event_ex_list->num_of_attribs; + for (cnt = 0; cnt < max; cnt++) { + memcpy(mac, + event_ex_list->attribs[cnt].u.mac_addr, + sizeof(mac)); + if (event_ex_list->attribs[cnt].attrib_type == + WLAN_HDR_ATTRIB_MAC_ADDR) { + pr_debug("%pM\n", mac); + + /* compare to delete one*/ + if (memcmp(mac2, mac, + sizeof(mac)) == 0) { + IPADBG("clean %d\n", total); + list_del(&entry->link); + kfree(entry); + break; + } + } + } + total++; + } + mutex_unlock(&ipa3_ctx->msg_wlan_client_lock); + } + return 0; +} + +/** + * ipa_send_msg() - Send "message" from kernel client to IPA driver + * @meta: [in] message meta-data + * @buff: [in] the payload for message + * @callback: [in] free callback + * + * Client supplies the message meta-data and payload which IPA driver buffers + * till read by user-space. After read from user space IPA driver invokes the + * callback supplied to free the message payload. Client must not touch/free + * the message payload after calling this API. + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa_send_msg(struct ipa_msg_meta *meta, void *buff, + ipa_msg_free_fn callback) +{ + struct ipa3_push_msg *msg; + void *data = NULL; + + if (meta == NULL || (buff == NULL && callback != NULL) || + (buff != NULL && callback == NULL)) { + IPAERR_RL("invalid param meta=%pK buff=%pK, callback=%pK\n", + meta, buff, callback); + return -EINVAL; + } + + if (meta->msg_type >= IPA_EVENT_MAX_NUM) { + IPAERR_RL("unsupported message type %d\n", meta->msg_type); + return -EINVAL; + } + + if (ipa3_ctx->ipa_wdi_opt_dpath && WLAN_IPA_EVENT(meta->msg_type)) { + IPAERR_RL("Opt data path enabled, ignore message type %d\n", + meta->msg_type); + if (buff) + callback(buff, meta->msg_len, meta->msg_type); + return 0; + } + + msg = kzalloc(sizeof(struct ipa3_push_msg), GFP_KERNEL); + if (msg == NULL) + return -ENOMEM; + + msg->meta = *meta; + if (meta->msg_len > 0 && buff) { + data = kmemdup(buff, meta->msg_len, GFP_KERNEL); + if (data == NULL) { + kfree(msg); + return -ENOMEM; + } + msg->buff = data; + msg->callback = ipa_send_msg_free; + } + + mutex_lock(&ipa3_ctx->msg_lock); + list_add_tail(&msg->link, &ipa3_ctx->msg_list); + /* support for softap client event cache */ + if (wlan_msg_process(meta, buff)) + IPAERR_RL("wlan_msg_process failed\n"); + + /* unlock only after process */ + mutex_unlock(&ipa3_ctx->msg_lock); + IPA_STATS_INC_CNT(ipa3_ctx->stats.msg_w[meta->msg_type]); + + wake_up(&ipa3_ctx->msg_waitq); + if (buff) + callback(buff, meta->msg_len, meta->msg_type); + + return 0; +} +EXPORT_SYMBOL(ipa_send_msg); + +/** + * ipa3_resend_wlan_msg() - Resend cached "message" to IPACM + * + * resend wlan client connect events to user-space + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_resend_wlan_msg(void) +{ + struct ipa_wlan_msg_ex *event_ex_list = NULL; + struct ipa3_push_msg *entry; + struct ipa3_push_msg *next; + int cnt = 0, total = 0; + struct ipa3_push_msg *msg; + void *data = NULL; + + IPADBG("\n"); + + mutex_lock(&ipa3_ctx->msg_wlan_client_lock); + list_for_each_entry_safe(entry, next, &ipa3_ctx->msg_wlan_client_list, + link) { + + event_ex_list = entry->buff; + for (cnt = 0; cnt < event_ex_list->num_of_attribs; cnt++) { + if (event_ex_list->attribs[cnt].attrib_type == + WLAN_HDR_ATTRIB_MAC_ADDR) { + IPADBG("%d-Mac %pM\n", total, + event_ex_list->attribs[cnt].u.mac_addr); + } + } + + msg = kzalloc(sizeof(*msg), GFP_KERNEL); + if (msg == NULL) { + mutex_unlock(&ipa3_ctx->msg_wlan_client_lock); + return -ENOMEM; + } + msg->meta = entry->meta; + data = kmemdup(entry->buff, entry->meta.msg_len, GFP_KERNEL); + if (data == NULL) { + kfree(msg); + mutex_unlock(&ipa3_ctx->msg_wlan_client_lock); + return -ENOMEM; + } + msg->buff = data; + msg->callback = ipa_send_msg_free; + mutex_lock(&ipa3_ctx->msg_lock); + list_add_tail(&msg->link, &ipa3_ctx->msg_list); + mutex_unlock(&ipa3_ctx->msg_lock); + wake_up(&ipa3_ctx->msg_waitq); + + total++; + } + mutex_unlock(&ipa3_ctx->msg_wlan_client_lock); + return 0; +} + +/** + * ipa3_register_pull_msg() - register pull message type + * @meta: [in] message meta-data + * @callback: [in] pull callback + * + * Register message callback by kernel client with IPA driver for IPA driver to + * pull message on-demand. + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_register_pull_msg(struct ipa_msg_meta *meta, ipa_msg_pull_fn callback) +{ + struct ipa3_pull_msg *msg; + + if (meta == NULL || callback == NULL) { + IPAERR_RL("invalid param meta=%pK callback=%pK\n", + meta, callback); + return -EINVAL; + } + + msg = kzalloc(sizeof(struct ipa3_pull_msg), GFP_KERNEL); + if (msg == NULL) + return -ENOMEM; + + msg->meta = *meta; + msg->callback = callback; + + mutex_lock(&ipa3_ctx->msg_lock); + list_add_tail(&msg->link, &ipa3_ctx->pull_msg_list); + mutex_unlock(&ipa3_ctx->msg_lock); + + return 0; +} + +/** + * ipa3_deregister_pull_msg() - De-register pull message type + * @meta: [in] message meta-data + * + * De-register "message" by kernel client from IPA driver + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_deregister_pull_msg(struct ipa_msg_meta *meta) +{ + struct ipa3_pull_msg *entry; + struct ipa3_pull_msg *next; + int result = -EINVAL; + + if (meta == NULL) { + IPAERR_RL("null arg: meta\n"); + return result; + } + + mutex_lock(&ipa3_ctx->msg_lock); + list_for_each_entry_safe(entry, next, &ipa3_ctx->pull_msg_list, link) { + if (entry->meta.msg_len == meta->msg_len && + entry->meta.msg_type == meta->msg_type) { + list_del(&entry->link); + kfree(entry); + result = 0; + break; + } + } + mutex_unlock(&ipa3_ctx->msg_lock); + return result; +} + +/** + * ipa3_read() - read message from IPA device + * @filp: [in] file pointer + * @buf: [out] buffer to read into + * @count: [in] size of above buffer + * @f_pos: [inout] file position + * + * Uer-space should continually read from /dev/ipa, read wll block when there + * are no messages to read. Upon return, user-space should read the ipa_msg_meta + * from the start of the buffer to know what type of message was read and its + * length in the remainder of the buffer. Buffer supplied must be big enough to + * hold the message meta-data and the largest defined message type + * + * Returns: how many bytes copied to buffer + * + * Note: Should not be called from atomic context + */ +ssize_t ipa3_read(struct file *filp, char __user *buf, size_t count, + loff_t *f_pos) +{ + char __user *start; + struct ipa3_push_msg *msg = NULL; + int ret; + DEFINE_WAIT_FUNC(wait, woken_wake_function); + int locked; + + start = buf; + + add_wait_queue(&ipa3_ctx->msg_waitq, &wait); + while (1) { + mutex_lock(&ipa3_ctx->msg_lock); + locked = 1; + + if (!list_empty(&ipa3_ctx->msg_list)) { + msg = list_first_entry(&ipa3_ctx->msg_list, + struct ipa3_push_msg, link); + list_del(&msg->link); + } + + IPADBG_LOW("msg=%pK\n", msg); + + if (msg) { + locked = 0; + mutex_unlock(&ipa3_ctx->msg_lock); + if (copy_to_user(buf, &msg->meta, + sizeof(struct ipa_msg_meta))) { + ret = -EFAULT; + kfree(msg); + msg = NULL; + break; + } + buf += sizeof(struct ipa_msg_meta); + count -= sizeof(struct ipa_msg_meta); + if (msg->buff) { + if (copy_to_user(buf, msg->buff, + msg->meta.msg_len)) { + ret = -EFAULT; + kfree(msg); + msg = NULL; + break; + } + buf += msg->meta.msg_len; + count -= msg->meta.msg_len; + msg->callback(msg->buff, msg->meta.msg_len, + msg->meta.msg_type); + } + IPA_STATS_INC_CNT( + ipa3_ctx->stats.msg_r[msg->meta.msg_type]); + kfree(msg); + msg = NULL; + } + + ret = -EAGAIN; + if (filp->f_flags & O_NONBLOCK) + break; + + ret = -EINTR; + if (signal_pending(current)) + break; + + if (start != buf) + break; + + locked = 0; + mutex_unlock(&ipa3_ctx->msg_lock); + wait_woken(&wait, TASK_INTERRUPTIBLE, MAX_SCHEDULE_TIMEOUT); + } + + remove_wait_queue(&ipa3_ctx->msg_waitq, &wait); + if (start != buf && ret != -EFAULT) + ret = buf - start; + + if (locked) + mutex_unlock(&ipa3_ctx->msg_lock); + + return ret; +} + +/** + * ipa3_pull_msg() - pull the specified message from client + * @meta: [in] message meta-data + * @buf: [out] buffer to read into + * @count: [in] size of above buffer + * + * Populate the supplied buffer with the pull message which is fetched + * from client, the message must have previously been registered with + * the IPA driver + * + * Returns: how many bytes copied to buffer + * + * Note: Should not be called from atomic context + */ +int ipa3_pull_msg(struct ipa_msg_meta *meta, char *buff, size_t count) +{ + struct ipa3_pull_msg *entry; + int result = -EINVAL; + + if (meta == NULL || buff == NULL || !count) { + IPAERR_RL("invalid param name=%pK buff=%pK count=%zu\n", + meta, buff, count); + return result; + } + + mutex_lock(&ipa3_ctx->msg_lock); + list_for_each_entry(entry, &ipa3_ctx->pull_msg_list, link) { + if (entry->meta.msg_len == meta->msg_len && + entry->meta.msg_type == meta->msg_type) { + result = entry->callback(buff, count, meta->msg_type); + break; + } + } + mutex_unlock(&ipa3_ctx->msg_lock); + return result; +} diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_mhi.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_mhi.c new file mode 100644 index 0000000000..4293d8c0cf --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_mhi.c @@ -0,0 +1,846 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include "ipa.h" +#include +#include +#include "gsi.h" +#include "ipa_common_i.h" +#include "ipa_i.h" + +#define IPA_MHI_DRV_NAME "ipa_mhi" + + +#define IPA_MHI_DBG(fmt, args...) \ + do { \ + pr_debug(IPA_MHI_DRV_NAME " %s:%d " fmt, \ + __func__, __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf(), \ + IPA_MHI_DRV_NAME " %s:%d " fmt, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf_low(), \ + IPA_MHI_DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) + +#define IPA_MHI_DBG_LOW(fmt, args...) \ + do { \ + pr_debug(IPA_MHI_DRV_NAME " %s:%d " fmt, \ + __func__, __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf_low(), \ + IPA_MHI_DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) + + +#define IPA_MHI_ERR(fmt, args...) \ + do { \ + pr_err(IPA_MHI_DRV_NAME " %s:%d " fmt, \ + __func__, __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf(), \ + IPA_MHI_DRV_NAME " %s:%d " fmt, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf_low(), \ + IPA_MHI_DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) + + +#define IPA_MHI_FUNC_ENTRY() \ + IPA_MHI_DBG("ENTRY\n") +#define IPA_MHI_FUNC_EXIT() \ + IPA_MHI_DBG("EXIT\n") + +#define IPA_MHI_MAX_UL_CHANNELS 2 +#define IPA_MHI_MAX_DL_CHANNELS 3 + +#define IPA_CLIENT_IS_MHI_LOW_LAT(client) \ + ((client) == IPA_CLIENT_MHI_LOW_LAT_PROD || \ + (client) == IPA_CLIENT_MHI_LOW_LAT_CONS) + +/* bit #40 in address should be asserted for MHI transfers over pcie */ +#define IPA_MHI_HOST_ADDR_COND(addr) \ + ((params->assert_bit40)?(IPA_MHI_HOST_ADDR(addr)):(addr)) + +enum ipa3_mhi_polling_mode { + IPA_MHI_POLLING_MODE_DB_MODE, + IPA_MHI_POLLING_MODE_POLL_MODE, +}; + +bool ipa3_mhi_stop_gsi_channel(enum ipa_client_type client) +{ + int res; + int ipa_ep_idx; + struct ipa3_ep_context *ep; + + IPA_MHI_FUNC_ENTRY(); + ipa_ep_idx = ipa_get_ep_mapping(client); + if (ipa_ep_idx == -1) { + IPA_MHI_ERR("Invalid client.\n"); + return -EINVAL; + } + + ep = &ipa3_ctx->ep[ipa_ep_idx]; + IPA_MHI_DBG_LOW("Stopping GSI channel %ld\n", ep->gsi_chan_hdl); + res = gsi_stop_channel(ep->gsi_chan_hdl); + if (res != 0 && + res != -GSI_STATUS_AGAIN && + res != -GSI_STATUS_TIMED_OUT) { + IPA_MHI_ERR("GSI stop channel failed %d\n", + res); + WARN_ON(1); + return false; + } + + if (res == 0) { + IPA_MHI_DBG_LOW("GSI channel %ld STOP\n", + ep->gsi_chan_hdl); + return true; + } + + return false; +} +EXPORT_SYMBOL(ipa3_mhi_stop_gsi_channel); + +static int ipa3_mhi_reset_gsi_channel(enum ipa_client_type client) +{ + int res; + int clnt_hdl; + + IPA_MHI_FUNC_ENTRY(); + + clnt_hdl = ipa_get_ep_mapping(client); + if (clnt_hdl < 0) + return -EFAULT; + + res = ipa3_reset_gsi_channel(clnt_hdl); + if (res) { + IPA_MHI_ERR("ipa3_reset_gsi_channel failed %d\n", res); + return -EFAULT; + } + + IPA_MHI_FUNC_EXIT(); + return 0; +} + +int ipa3_mhi_reset_channel_internal(enum ipa_client_type client) +{ + int res; + + IPA_MHI_FUNC_ENTRY(); + + res = ipa3_mhi_reset_gsi_channel(client); + if (res) { + IPAERR("ipa3_mhi_reset_gsi_channel failed\n"); + ipa_assert(); + return res; + } + + res = ipa3_disable_data_path(ipa_get_ep_mapping(client)); + if (res) { + IPA_MHI_ERR("ipa3_disable_data_path failed %d\n", res); + return res; + } + IPA_MHI_FUNC_EXIT(); + + return 0; +} +EXPORT_SYMBOL(ipa3_mhi_reset_channel_internal); + +int ipa3_mhi_start_channel_internal(enum ipa_client_type client) +{ + int res; + int ipa_ep_idx; + + IPA_MHI_FUNC_ENTRY(); + + ipa_ep_idx = ipa_get_ep_mapping(client); + if (ipa_ep_idx < 0) { + IPA_MHI_ERR("Invalid client %d\n", client); + return -EINVAL; + } + res = ipa3_enable_data_path(ipa_ep_idx); + if (res) { + IPA_MHI_ERR("ipa3_enable_data_path failed %d\n", res); + return res; + } + IPA_MHI_FUNC_EXIT(); + + return 0; +} + +static int ipa3_mhi_get_ch_poll_cfg(enum ipa_client_type client, + struct ipa_mhi_ch_ctx *ch_ctx_host, int ring_size) +{ + switch (ch_ctx_host->pollcfg) { + case 0: + /*set default polling configuration according to MHI spec*/ + if (IPA_CLIENT_IS_PROD(client)) + return 7; + else + /* IPA5.0 use almst empty register */ + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0) + return (ring_size/2); + else + return (ring_size/2)/8; + break; + default: + return ch_ctx_host->pollcfg; + } +} + +static int ipa_mhi_start_gsi_channel(enum ipa_client_type client, + int ipa_ep_idx, struct start_gsi_channel *params, + struct ipa_ep_cfg *ipa_ep_cfg) +{ + int res = 0; + struct gsi_evt_ring_props ev_props; + struct ipa_mhi_msi_info *msi; + struct gsi_chan_props ch_props; + union __packed gsi_channel_scratch ch_scratch; + union __packed gsi_channel_scratch ch_scratch1; + struct ipa3_ep_context *ep; + const struct ipa_gsi_ep_config *ep_cfg; + struct ipa_ep_cfg_ctrl ep_cfg_ctrl; + bool burst_mode_enabled = false; + int code = 0; + + IPA_MHI_FUNC_ENTRY(); + + ep = &ipa3_ctx->ep[ipa_ep_idx]; + + msi = params->msi; + ep_cfg = ipa_get_gsi_ep_info(client); + if (!ep_cfg) { + IPA_MHI_ERR("Wrong parameter, ep_cfg is NULL\n"); + return -EPERM; + } + + /* allocate event ring only for the first time pipe is connected */ + if (params->state == IPA_HW_MHI_CHANNEL_STATE_INVALID) { + memset(&ev_props, 0, sizeof(ev_props)); + ev_props.intf = GSI_EVT_CHTYPE_MHI_EV; + ev_props.intr = GSI_INTR_MSI; + ev_props.re_size = GSI_EVT_RING_RE_SIZE_16B; + ev_props.ring_len = params->ev_ctx_host->rlen; + ev_props.ring_base_addr = IPA_MHI_HOST_ADDR_COND( + params->ev_ctx_host->rbase); + ev_props.int_modt = params->ev_ctx_host->intmodt * + IPA_SLEEP_CLK_RATE_KHZ; + ev_props.int_modc = params->ev_ctx_host->intmodc; + ev_props.intvec = ((msi->data & ~msi->mask) | + (params->ev_ctx_host->msivec & msi->mask)); + ev_props.msi_addr = IPA_MHI_HOST_ADDR_COND( + (((u64)msi->addr_hi << 32) | msi->addr_low)); + ev_props.rp_update_addr = IPA_MHI_HOST_ADDR_COND( + params->event_context_addr + + offsetof(struct ipa_mhi_ev_ctx, rp)); + ev_props.exclusive = true; + ev_props.err_cb = params->ev_err_cb; + ev_props.user_data = params->channel; + ev_props.evchid_valid = true; + ev_props.evchid = params->evchid; + IPA_MHI_DBG("allocating event ring ep:%u evchid:%u\n", + ipa_ep_idx, ev_props.evchid); + res = gsi_alloc_evt_ring(&ev_props, ipa3_ctx->gsi_dev_hdl, + &ep->gsi_evt_ring_hdl); + if (res) { + IPA_MHI_ERR("gsi_alloc_evt_ring failed %d\n", res); + goto fail_alloc_evt; + } + IPA_MHI_DBG("client %d, caching event ring hdl %lu\n", + client, + ep->gsi_evt_ring_hdl); + *params->cached_gsi_evt_ring_hdl = + ep->gsi_evt_ring_hdl; + + } else { + IPA_MHI_DBG("event ring already exists: evt_ring_hdl=%lu\n", + *params->cached_gsi_evt_ring_hdl); + ep->gsi_evt_ring_hdl = *params->cached_gsi_evt_ring_hdl; + } + + /** + * compare host evt ring wp with base ptr condition was added to check + * whether MHI driver ring db or not, but in wrap around case wp and + * base ptr can be same so removing it. + * if evt-ring has no credit, gsi will crash. + */ + + IPA_MHI_DBG("Ring event db: evt_ring_hdl=%lu host_wp=0x%llx\n", + ep->gsi_evt_ring_hdl, params->ev_ctx_host->wp); + res = gsi_ring_evt_ring_db(ep->gsi_evt_ring_hdl, + params->ev_ctx_host->wp); + if (res) { + IPA_MHI_ERR("fail to ring evt ring db %d. hdl=%lu wp=0x%llx\n", + res, ep->gsi_evt_ring_hdl, params->ev_ctx_host->wp); + goto fail_alloc_ch; + } + + memset(&ch_props, 0, sizeof(ch_props)); + ch_props.prot = GSI_CHAN_PROT_MHI; + ch_props.dir = IPA_CLIENT_IS_PROD(client) ? + GSI_CHAN_DIR_TO_GSI : GSI_CHAN_DIR_FROM_GSI; + ch_props.ch_id = ep_cfg->ipa_gsi_chan_num; + ch_props.evt_ring_hdl = *params->cached_gsi_evt_ring_hdl; + ch_props.re_size = GSI_CHAN_RE_SIZE_16B; + ch_props.ring_len = params->ch_ctx_host->rlen; + ch_props.ring_base_addr = IPA_MHI_HOST_ADDR_COND( + params->ch_ctx_host->rbase); + + /* Burst mode is not supported on DPL pipes */ + if ((client != IPA_CLIENT_MHI_DPL_CONS) && + (params->ch_ctx_host->brstmode == IPA_MHI_BURST_MODE_DEFAULT || + params->ch_ctx_host->brstmode == IPA_MHI_BURST_MODE_ENABLE)) { + burst_mode_enabled = true; + } + + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_0 && + !burst_mode_enabled) + ch_props.use_db_eng = GSI_CHAN_DIRECT_MODE; + else + ch_props.use_db_eng = GSI_CHAN_DB_MODE; + + ch_props.db_in_bytes = 1; + ch_props.low_latency_en = 0; + ch_props.max_prefetch = GSI_ONE_PREFETCH_SEG; + ch_props.low_weight = 1; + ch_props.prefetch_mode = ep_cfg->prefetch_mode; + ch_props.empty_lvl_threshold = ep_cfg->prefetch_threshold; + ch_props.err_cb = params->ch_err_cb; + ch_props.chan_user_data = params->channel; + res = gsi_alloc_channel(&ch_props, ipa3_ctx->gsi_dev_hdl, + &ep->gsi_chan_hdl); + if (res) { + IPA_MHI_ERR("gsi_alloc_channel failed %d\n", + res); + goto fail_alloc_ch; + } + + memset(&ch_scratch, 0, sizeof(ch_scratch)); + ch_scratch.mhi.mhi_host_wp_addr = IPA_MHI_HOST_ADDR_COND( + params->channel_context_addr + + offsetof(struct ipa_mhi_ch_ctx, wp)); + ch_scratch.mhi.assert_bit40 = params->assert_bit40; + + /* + * Update scratch for MCS smart prefetch: + * Starting IPA4.5, smart prefetch implemented by H/W. + * At IPA 4.0/4.1/4.2, we do not use MCS smart prefetch + * so keep the fields zero. + */ + if (ipa3_ctx->ipa_hw_type < IPA_HW_v4_0) { + ch_scratch.mhi.max_outstanding_tre = + ep_cfg->ipa_if_tlv * ch_props.re_size; + ch_scratch.mhi.outstanding_threshold = + min(ep_cfg->ipa_if_tlv / 2, 8) * ch_props.re_size; + } + ch_scratch.mhi.oob_mod_threshold = 4; + + if (burst_mode_enabled) { + ch_scratch.mhi.burst_mode_enabled = burst_mode_enabled; + ch_scratch.mhi.polling_configuration = + ipa3_mhi_get_ch_poll_cfg(client, params->ch_ctx_host, + (ch_props.ring_len / ch_props.re_size)); + ch_scratch.mhi.polling_mode = IPA_MHI_POLLING_MODE_DB_MODE; + } else { + ch_scratch.mhi.burst_mode_enabled = false; + } + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_5 && + ipa3_ctx->platform_type == IPA_PLAT_TYPE_MDM) { + memset(&ch_scratch1, 0, sizeof(ch_scratch1)); + ch_scratch1.mhi_v2.mhi_host_wp_addr_lo = + ch_scratch.mhi.mhi_host_wp_addr & 0xFFFFFFFF; + ch_scratch1.mhi_v2.mhi_host_wp_addr_hi = + (ch_scratch.mhi.mhi_host_wp_addr & 0x1FF00000000ll) >> + 32; + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0 && + client == IPA_CLIENT_MHI_CONS) { + gsi_update_almst_empty_thrshold(ep->gsi_chan_hdl, + ch_scratch.mhi.polling_configuration); + } else { + ch_scratch1.mhi_v2.polling_configuration = + ch_scratch.mhi.polling_configuration; + } + ch_scratch1.mhi_v2.assert_bit40 = ch_scratch.mhi.assert_bit40; + ch_scratch1.mhi_v2.burst_mode_enabled = + ch_scratch.mhi.burst_mode_enabled; + ch_scratch1.mhi_v2.polling_mode = ch_scratch.mhi.polling_mode; + ch_scratch1.mhi_v2.oob_mod_threshold = + ch_scratch.mhi.oob_mod_threshold; + res = gsi_write_channel_scratch(ep->gsi_chan_hdl, ch_scratch1); + } else { + res = gsi_write_channel_scratch(ep->gsi_chan_hdl, ch_scratch); + } + if (res) { + IPA_MHI_ERR("gsi_write_channel_scratch failed %d\n", + res); + goto fail_ch_scratch; + } + + *params->mhi = ch_scratch.mhi; + + res = ipa3_enable_data_path(ipa_ep_idx); + if (res) { + IPA_MHI_ERR("enable data path failed res=%d clnt=%d.\n", res, + ipa_ep_idx); + goto fail_ep_cfg; + } + + if (!ep->skip_ep_cfg) { + if (ipa3_cfg_ep(ipa_ep_idx, ipa_ep_cfg)) { + IPAERR("fail to configure EP.\n"); + goto fail_ep_cfg; + } + if (ipa3_cfg_ep_status(ipa_ep_idx, &ep->status)) { + IPAERR("fail to configure status of EP.\n"); + goto fail_ep_cfg; + } + IPA_MHI_DBG("ep configuration successful\n"); + } else { + IPA_MHI_DBG("skipping ep configuration\n"); + if (IPA_CLIENT_IS_PROD(ipa3_ctx->ep[ipa_ep_idx].client) && + ipa3_ctx->ep[ipa_ep_idx].client == IPA_CLIENT_MHI_PROD + && !ipa3_is_mhip_offload_enabled()) { + if (ipa3_cfg_ep_seq(ipa_ep_idx, + &ipa_ep_cfg->seq)) { + IPA_MHI_ERR("fail to configure USB pipe seq\n"); + goto fail_ep_cfg; + } + } + + } + + if (IPA_CLIENT_IS_PROD(ep->client) && ep->skip_ep_cfg) { + memset(&ep_cfg_ctrl, 0, sizeof(struct ipa_ep_cfg_ctrl)); + ep_cfg_ctrl.ipa_ep_delay = true; + ep->ep_delay_set = true; + res = ipa_cfg_ep_ctrl(ipa_ep_idx, &ep_cfg_ctrl); + if (res) + IPA_MHI_ERR("client (ep: %d) failed result=%d\n", + ipa_ep_idx, res); + else + IPA_MHI_DBG("client (ep: %d) success\n", ipa_ep_idx); + } else { + ep->ep_delay_set = false; + } + + if (!ep->skip_ep_cfg && IPA_CLIENT_IS_PROD(client)) + ipa3_install_dflt_flt_rules(ipa_ep_idx); + + IPA_MHI_DBG("Starting channel\n"); + res = gsi_start_channel(ep->gsi_chan_hdl); + if (res) { + IPA_MHI_ERR("gsi_start_channel failed %d\n", res); + goto fail_ch_start; + } + + if (IPA_CLIENT_IS_PROD(ep->client) && ep->skip_ep_cfg && + ipa3_ctx->ipa_endp_delay_wa && + !ipa3_is_mhip_offload_enabled() && + !(IPA_CLIENT_IS_MHI_LOW_LAT(ep->client) && + ipa3_is_modem_up())) { + res = gsi_enable_flow_control_ee(ep->gsi_chan_hdl, 0, &code); + if (res == GSI_STATUS_SUCCESS) { + IPA_MHI_DBG("flow ctrl sussess gsi ch %d code %d\n", + ep->gsi_chan_hdl, code); + } else { + IPA_MHI_DBG("failed to flow ctrll gsi ch %d code %d\n", + ep->gsi_chan_hdl, code); + } + } + + IPA_MHI_FUNC_EXIT(); + return 0; + +fail_ep_cfg: + ipa3_disable_data_path(ipa_ep_idx); +fail_ch_start: +fail_ch_scratch: + gsi_dealloc_channel(ep->gsi_chan_hdl); +fail_alloc_ch: + gsi_dealloc_evt_ring(ep->gsi_evt_ring_hdl); + ep->gsi_evt_ring_hdl = ~0; +fail_alloc_evt: + return res; +} + +int ipa3_mhi_init_engine(struct ipa_mhi_init_engine *params) +{ + int res; + struct gsi_device_scratch gsi_scratch; + const struct ipa_gsi_ep_config *gsi_ep_info; + u32 ipa_mhi_max_ul_channels, ipa_mhi_max_dl_channels; + + IPA_MHI_FUNC_ENTRY(); + + if (!params) { + IPA_MHI_ERR("null args\n"); + return -EINVAL; + } + + ipa_mhi_max_ul_channels = IPA_MHI_MAX_UL_CHANNELS; + ipa_mhi_max_dl_channels = IPA_MHI_MAX_DL_CHANNELS; + + /* In case of Auto-pcie config, MHI2_PROD and MHI2_CONS is used */ + if (ipa3_ctx->ipa_config_is_auto == true) { + ipa_mhi_max_ul_channels++; + ipa_mhi_max_dl_channels++; + } + + if ((ipa_mhi_max_ul_channels + ipa_mhi_max_dl_channels) > + ((ipa3_ctx->mhi_evid_limits[1] - + ipa3_ctx->mhi_evid_limits[0]) + 1)) { + IPAERR("Not enough event rings for MHI\n"); + ipa_assert(); + return -EINVAL; + } + + /* Initialize IPA MHI engine */ + gsi_ep_info = ipa_get_gsi_ep_info(IPA_CLIENT_MHI_PROD); + if (!gsi_ep_info) { + IPAERR("MHI PROD has no ep allocated\n"); + ipa_assert(); + } + memset(&gsi_scratch, 0, sizeof(gsi_scratch)); + gsi_scratch.mhi_base_chan_idx_valid = true; + gsi_scratch.mhi_base_chan_idx = gsi_ep_info->ipa_gsi_chan_num + + params->gsi.first_ch_idx; + res = gsi_write_device_scratch(ipa3_ctx->gsi_dev_hdl, + &gsi_scratch); + if (res) { + IPA_MHI_ERR("failed to write device scratch %d\n", res); + goto fail_init_engine; + } + + IPA_MHI_FUNC_EXIT(); + return 0; + +fail_init_engine: + return res; +} +EXPORT_SYMBOL(ipa3_mhi_init_engine); + +/** + * ipa3_connect_mhi_pipe() - Connect pipe to IPA and start corresponding + * MHI channel + * @in: connect parameters + * @clnt_hdl: [out] client handle for this pipe + * + * This function is called by IPA MHI client driver on MHI channel start. + * This function is called after MHI engine was started. + * + * Return codes: 0 : success + * negative : error + */ +int ipa3_connect_mhi_pipe(struct ipa_mhi_connect_params_internal *in, + u32 *clnt_hdl) +{ + struct ipa3_ep_context *ep; + int ipa_ep_idx; + int res; + enum ipa_client_type client; + + IPA_MHI_FUNC_ENTRY(); + + if (!in || !clnt_hdl) { + IPA_MHI_ERR("NULL args\n"); + return -EINVAL; + } + + in->start.gsi.evchid += ipa3_ctx->mhi_evid_limits[0]; + + client = in->sys->client; + ipa_ep_idx = ipa_get_ep_mapping(client); + if (ipa_ep_idx == -1) { + IPA_MHI_ERR("Invalid client.\n"); + return -EINVAL; + } + + ep = &ipa3_ctx->ep[ipa_ep_idx]; + + if (ep->valid == 1) { + IPA_MHI_ERR("EP already allocated.\n"); + return -EPERM; + } + + memset(ep, 0, offsetof(struct ipa3_ep_context, sys)); + ep->valid = 1; + ep->skip_ep_cfg = in->sys->skip_ep_cfg; + ep->client = client; + ep->client_notify = in->sys->notify; + ep->priv = in->sys->priv; + ep->keep_ipa_awake = in->sys->keep_ipa_awake; + + res = ipa_mhi_start_gsi_channel(client, + ipa_ep_idx, &in->start.gsi, + &in->sys->ipa_ep_cfg); + if (res) { + IPA_MHI_ERR("ipa_mhi_start_gsi_channel failed %d\n", + res); + goto fail_start_channel; + } + + *clnt_hdl = ipa_ep_idx; + ipa3_ctx->skip_ep_cfg_shadow[ipa_ep_idx] = ep->skip_ep_cfg; + IPA_MHI_DBG("client %d (ep: %d) connected\n", client, ipa_ep_idx); + + IPA_MHI_FUNC_EXIT(); + + return 0; + +fail_start_channel: + memset(ep, 0, offsetof(struct ipa3_ep_context, sys)); + return -EPERM; +} +EXPORT_SYMBOL(ipa3_connect_mhi_pipe); + +/** + * ipa3_disconnect_mhi_pipe() - Disconnect pipe from IPA and reset corresponding + * MHI channel + * @clnt_hdl: client handle for this pipe + * + * This function is called by IPA MHI client driver on MHI channel reset. + * This function is called after MHI channel was started. + * This function is doing the following: + * - Send command to uC/GSI to reset corresponding MHI channel + * - Configure IPA EP control + * + * Return codes: 0 : success + * negative : error + */ +int ipa3_disconnect_mhi_pipe(u32 clnt_hdl) +{ + struct ipa3_ep_context *ep; + int res; + struct ipa_ep_cfg_ctrl ep_cfg_ctrl; + + IPA_MHI_FUNC_ENTRY(); + + if (clnt_hdl >= ipa3_ctx->ipa_num_pipes) { + IPAERR("invalid handle %d\n", clnt_hdl); + return -EINVAL; + } + + if (ipa3_ctx->ep[clnt_hdl].valid == 0) { + IPAERR("pipe was not connected %d\n", clnt_hdl); + return -EINVAL; + } + + ep = &ipa3_ctx->ep[clnt_hdl]; + if (ep->ep_delay_set) { + memset(&ep_cfg_ctrl, 0, sizeof(struct ipa_ep_cfg_ctrl)); + ep_cfg_ctrl.ipa_ep_delay = false; + res = ipa_cfg_ep_ctrl(clnt_hdl, + &ep_cfg_ctrl); + if (res) { + IPAERR + ("client(ep:%d) failed to remove delay res=%d\n", + clnt_hdl, res); + } else { + IPADBG("client (ep: %d) delay removed\n", + clnt_hdl); + ep->ep_delay_set = false; + } + } + + res = gsi_dealloc_channel(ep->gsi_chan_hdl); + if (res) { + IPAERR("gsi_dealloc_channel failed %d\n", res); + goto fail_reset_channel; + } + + ep->valid = 0; + ipa3_delete_dflt_flt_rules(clnt_hdl); + + IPA_MHI_DBG("client (ep: %d) disconnected\n", clnt_hdl); + IPA_MHI_FUNC_EXIT(); + return 0; + +fail_reset_channel: + return res; +} +EXPORT_SYMBOL(ipa3_disconnect_mhi_pipe); + +int ipa3_mhi_resume_channels_internal(enum ipa_client_type client, + bool LPTransitionRejected, bool brstmode_enabled, + union __packed gsi_channel_scratch ch_scratch, u8 index, + bool is_switch_to_dbmode) +{ + int res; + int ipa_ep_idx; + struct ipa3_ep_context *ep; + union __packed gsi_channel_scratch gsi_ch_scratch; + + IPA_MHI_FUNC_ENTRY(); + + ipa_ep_idx = ipa_get_ep_mapping(client); + if (ipa_ep_idx < 0) { + IPA_MHI_ERR("Invalid client %d\n", client); + return -EINVAL; + } + ep = &ipa3_ctx->ep[ipa_ep_idx]; + + if (brstmode_enabled && !LPTransitionRejected) { + + res = gsi_read_channel_scratch(ep->gsi_chan_hdl, + &gsi_ch_scratch); + if (res) { + IPA_MHI_ERR("read ch scratch fail %d\n", res); + return res; + } + + /* + * set polling mode bit to DB mode before + * resuming the channel + * + * For MHI-->IPA pipes: + * when resuming due to transition to M0, + * set the polling mode bit to 0. + * In other cases, restore it's value form + * when you stopped the channel. + * Here, after successful resume client move to M0 state. + * So, by default setting polling mode bit to 0. + * + * For IPA-->MHI pipe: + * always restore the polling mode bit. + */ + if (IPA_CLIENT_IS_PROD(client)) { + if (is_switch_to_dbmode) + ch_scratch.mhi.polling_mode = + IPA_MHI_POLLING_MODE_DB_MODE; + else + ch_scratch.mhi.polling_mode = + gsi_ch_scratch.mhi.polling_mode; + } else { + ch_scratch.mhi.polling_mode = + gsi_ch_scratch.mhi.polling_mode; + } + + /* Use GSI update API to not affect non-SWI fields + * inside the scratch while in suspend-resume operation + */ + /* polling_mode bit remains unchanged for mhi_v2 format, + * no update needed for this effort + */ + res = gsi_update_mhi_channel_scratch( + ep->gsi_chan_hdl, ch_scratch.mhi); + if (res) { + IPA_MHI_ERR("write ch scratch fail %d\n" + , res); + return res; + } + } + + res = gsi_start_channel(ep->gsi_chan_hdl); + if (res) { + IPA_MHI_ERR("failed to resume channel error %d\n", res); + return res; + } + + IPA_MHI_FUNC_EXIT(); + return 0; +} +EXPORT_SYMBOL(ipa3_mhi_resume_channels_internal); + +int ipa3_mhi_query_ch_info(enum ipa_client_type client, + struct gsi_chan_info *ch_info) +{ + int ipa_ep_idx; + int res; + struct ipa3_ep_context *ep; + + IPA_MHI_FUNC_ENTRY(); + + ipa_ep_idx = ipa_get_ep_mapping(client); + if (ipa_ep_idx < 0) { + IPA_MHI_ERR("Invalid client %d\n", client); + return -EINVAL; + } + ep = &ipa3_ctx->ep[ipa_ep_idx]; + res = gsi_query_channel_info(ep->gsi_chan_hdl, ch_info); + if (res) { + IPA_MHI_ERR("gsi_query_channel_info failed\n"); + return res; + } + + IPA_MHI_FUNC_EXIT(); + return 0; +} +EXPORT_SYMBOL(ipa3_mhi_query_ch_info); + +bool ipa3_has_open_aggr_frame(enum ipa_client_type client) +{ + u32 aggr_state_active; + int ipa_ep_idx; + + ipa_ep_idx = ipa_get_ep_mapping(client); + if (ipa_ep_idx == -1) { + ipa_assert(); + return false; + } + + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0) { + aggr_state_active = + ipahal_read_ep_reg(IPA_STATE_AGGR_ACTIVE_n, + ipa_ep_idx); + } else { + aggr_state_active = + ipahal_read_reg(IPA_STATE_AGGR_ACTIVE); + } + + IPA_MHI_DBG_LOW("IPA_STATE_AGGR_ACTIVE_OFST 0x%x, ep_idx %d\n", + ipa_ep_idx, aggr_state_active); + + return ipahal_test_ep_bit(aggr_state_active, ipa_ep_idx); +} +EXPORT_SYMBOL(ipa3_has_open_aggr_frame); + +int ipa3_mhi_destroy_channel(enum ipa_client_type client) +{ + int res; + int ipa_ep_idx; + struct ipa3_ep_context *ep; + + ipa_ep_idx = ipa_get_ep_mapping(client); + if (ipa_ep_idx < 0) { + IPA_MHI_ERR("Invalid client %d\n", client); + return -EINVAL; + } + ep = &ipa3_ctx->ep[ipa_ep_idx]; + + IPA_ACTIVE_CLIENTS_INC_EP(client); + + IPA_MHI_DBG("reset event ring (hdl: %lu, ep: %d)\n", + ep->gsi_evt_ring_hdl, ipa_ep_idx); + + res = gsi_reset_evt_ring(ep->gsi_evt_ring_hdl); + if (res) { + IPAERR(" failed to reset evt ring %lu, err %d\n" + , ep->gsi_evt_ring_hdl, res); + goto fail; + } + + IPA_MHI_DBG("dealloc event ring (hdl: %lu, ep: %d)\n", + ep->gsi_evt_ring_hdl, ipa_ep_idx); + + res = gsi_dealloc_evt_ring( + ep->gsi_evt_ring_hdl); + if (res) { + IPAERR("dealloc evt ring %lu failed, err %d\n" + , ep->gsi_evt_ring_hdl, res); + goto fail; + } + + IPA_ACTIVE_CLIENTS_DEC_EP(client); + return 0; +fail: + IPA_ACTIVE_CLIENTS_DEC_EP(client); + return res; +} +EXPORT_SYMBOL(ipa3_mhi_destroy_channel); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("IPA MHI driver"); diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_mhi_proxy.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_mhi_proxy.c new file mode 100644 index 0000000000..992c0844f8 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_mhi_proxy.c @@ -0,0 +1,1175 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) +#include +#include +#endif +#include "ipa_qmi_service.h" +#include "ipa_common_i.h" +#include "ipa_i.h" + +#define IMP_DRV_NAME "ipa_mhi_proxy" + +#define IMP_DBG(fmt, args...) \ + do { \ + pr_debug(IMP_DRV_NAME " %s:%d " fmt, \ + __func__, __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf(), \ + IMP_DRV_NAME " %s:%d " fmt, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf_low(), \ + IMP_DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) + +#define IMP_DBG_LOW(fmt, args...) \ + do { \ + pr_debug(IMP_DRV_NAME " %s:%d " fmt, \ + __func__, __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf_low(), \ + IMP_DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) + + +#define IMP_ERR(fmt, args...) \ + do { \ + pr_err(IMP_DRV_NAME " %s:%d " fmt, \ + __func__, __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf(), \ + IMP_DRV_NAME " %s:%d " fmt, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf_low(), \ + IMP_DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) + + +#define IMP_FUNC_ENTRY() \ + IMP_DBG_LOW("ENTRY\n") +#define IMP_FUNC_EXIT() \ + IMP_DBG_LOW("EXIT\n") + +#define IMP_IPA_UC_UL_CH_n 0 +#define IMP_IPA_UC_UL_EV_n 1 +#define IMP_IPA_UC_DL_CH_n 2 +#define IMP_IPA_UC_DL_EV_n 3 +#define IMP_IPA_UC_m 1 + +/* each pair of UL/DL channels are defined below */ +static const struct mhi_device_id mhi_driver_match_table[] = { + { .chan = "IP_HW_OFFLOAD_0" }, + {}, +}; + +static int imp_mhi_probe_cb(struct mhi_device *, const struct mhi_device_id *); +static void imp_mhi_remove_cb(struct mhi_device *); +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) +static void imp_mhi_status_cb(struct mhi_device *, enum mhi_callback); +#else +static void imp_mhi_status_cb(struct mhi_device *, enum MHI_CB); +#endif + +static struct mhi_driver mhi_driver = { + .id_table = mhi_driver_match_table, + .probe = imp_mhi_probe_cb, + .remove = imp_mhi_remove_cb, + .status_cb = imp_mhi_status_cb, + .driver = { + .name = IMP_DRV_NAME, + .owner = THIS_MODULE, + }, +}; + +struct imp_channel_context_type { + u32 chstate:8; + u32 brsmode:2; + u32 pollcfg:6; + u32 reserved:16; + + u32 chtype; + + u32 erindex; + + u64 rbase; + + u64 rlen; + + u64 rpp; + + u64 wpp; +} __packed; + +struct imp_event_context_type { + u32 reserved:8; + u32 intmodc:8; + u32 intmodt:16; + + u32 ertype; + + u32 msivec; + + u64 rbase; + + u64 rlen; + + u64 rpp; + + u64 wpp; +} __packed; + +struct imp_iova_addr { + dma_addr_t base; + unsigned int size; +}; + +struct imp_dev_info { + struct platform_device *pdev; + bool smmu_enabled; + struct imp_iova_addr ctrl; + struct imp_iova_addr data; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) + phys_addr_t chdb_base; + phys_addr_t erdb_base; +#else + u32 chdb_base; + u32 erdb_base; +#endif +}; + +struct imp_event_props { + u16 id; + phys_addr_t doorbell; + u16 uc_mbox_n; + struct imp_event_context_type ev_ctx; +}; + +struct imp_event { + struct imp_event_props props; +}; + +struct imp_channel_props { + enum dma_data_direction dir; + u16 id; + phys_addr_t doorbell; + u16 uc_mbox_n; + struct imp_channel_context_type ch_ctx; + +}; + +struct imp_channel { + struct imp_channel_props props; + struct imp_event event; +}; + +enum imp_state { + IMP_INVALID = 0, + IMP_PROBED, + IMP_READY, + IMP_STARTED +}; + +struct imp_qmi_cache { + struct ipa_mhi_ready_indication_msg_v01 ready_ind; + struct ipa_mhi_alloc_channel_req_msg_v01 alloc_ch_req; + struct ipa_mhi_alloc_channel_resp_msg_v01 alloc_ch_resp; + struct ipa_mhi_clk_vote_resp_msg_v01 clk_vote_resp; +}; + +struct imp_mhi_driver { + struct mhi_device *mhi_dev; + struct imp_channel ul_chan; + struct imp_channel dl_chan; +}; + +struct imp_context { + struct imp_dev_info dev_info; + struct imp_mhi_driver md; + struct mutex mutex; + struct mutex lpm_mutex; + enum imp_state state; + bool in_lpm; + bool lpm_disabled; + struct imp_qmi_cache qmi; + +}; + +static struct imp_context *imp_ctx; + +static void _populate_smmu_info(struct ipa_mhi_ready_indication_msg_v01 *req) +{ + req->smmu_info_valid = true; + req->smmu_info.iova_ctl_base_addr = imp_ctx->dev_info.ctrl.base; + req->smmu_info.iova_ctl_size = imp_ctx->dev_info.ctrl.size; + req->smmu_info.iova_data_base_addr = imp_ctx->dev_info.data.base; + req->smmu_info.iova_data_size = imp_ctx->dev_info.data.size; +} + +static void imp_mhi_trigger_ready_ind(void) +{ + struct ipa_mhi_ready_indication_msg_v01 *req + = &imp_ctx->qmi.ready_ind; + int ret; + struct imp_channel *ch; + struct ipa_mhi_ch_init_info_type_v01 *ch_info; + + IMP_FUNC_ENTRY(); + if (imp_ctx->state != IMP_PROBED) { + IMP_ERR("invalid state %d\n", imp_ctx->state); + goto exit; + } + + if (imp_ctx->dev_info.smmu_enabled) + _populate_smmu_info(req); + + req->ch_info_arr_len = 0; + BUILD_BUG_ON(QMI_IPA_REMOTE_MHI_CHANNELS_NUM_MAX_V01 < 2); + + /* UL channel */ + ch = &imp_ctx->md.ul_chan; + ch_info = &req->ch_info_arr[req->ch_info_arr_len]; + + ch_info->ch_id = ch->props.id; + ch_info->direction_type = ch->props.dir; + ch_info->er_id = ch->event.props.id; + + /* uC is a doorbell proxy between local Q6 and remote Q6 */ + ch_info->ch_doorbell_addr = ipa3_ctx->ipa_wrapper_base + + ipahal_get_reg_base() + + ipahal_get_reg_mn_ofst(IPA_UC_MAILBOX_m_n, + IMP_IPA_UC_m, + ch->props.uc_mbox_n); + + ch_info->er_doorbell_addr = ipa3_ctx->ipa_wrapper_base + + ipahal_get_reg_base() + + ipahal_get_reg_mn_ofst(IPA_UC_MAILBOX_m_n, + IMP_IPA_UC_m, + ch->event.props.uc_mbox_n); + req->ch_info_arr_len++; + + /* DL channel */ + ch = &imp_ctx->md.dl_chan; + ch_info = &req->ch_info_arr[req->ch_info_arr_len]; + + ch_info->ch_id = ch->props.id; + ch_info->direction_type = ch->props.dir; + ch_info->er_id = ch->event.props.id; + + /* uC is a doorbell proxy between local Q6 and remote Q6 */ + ch_info->ch_doorbell_addr = ipa3_ctx->ipa_wrapper_base + + ipahal_get_reg_base() + + ipahal_get_reg_mn_ofst(IPA_UC_MAILBOX_m_n, + IMP_IPA_UC_m, + ch->props.uc_mbox_n); + + ch_info->er_doorbell_addr = ipa3_ctx->ipa_wrapper_base + + ipahal_get_reg_base() + + ipahal_get_reg_mn_ofst(IPA_UC_MAILBOX_m_n, + IMP_IPA_UC_m, + ch->event.props.uc_mbox_n); + req->ch_info_arr_len++; + + IMP_DBG("sending IND to modem\n"); + ret = ipa3_qmi_send_mhi_ready_indication(req); + if (ret) { + IMP_ERR("failed to send ready indication to modem %d\n", ret); + return; + } + + imp_ctx->state = IMP_READY; + +exit: + IMP_FUNC_EXIT(); +} + +static struct imp_channel *imp_get_ch_by_id(u16 id) +{ + if (imp_ctx->md.ul_chan.props.id == id) + return &imp_ctx->md.ul_chan; + + if (imp_ctx->md.dl_chan.props.id == id) + return &imp_ctx->md.dl_chan; + + return NULL; +} + +static struct ipa_mhi_er_info_type_v01 * + _find_ch_in_er_info_arr(struct ipa_mhi_alloc_channel_req_msg_v01 *req, + u16 id) +{ + int i; + + if (req->er_info_arr_len > QMI_IPA_REMOTE_MHI_CHANNELS_NUM_MAX_V01) + return NULL; + + for (i = 0; i < req->tr_info_arr_len; i++) + if (req->er_info_arr[i].er_id == id) + return &req->er_info_arr[i]; + return NULL; +} + +/* round addresses for closest page per SMMU requirements */ +static inline void imp_smmu_round_to_page(uint64_t iova, uint64_t pa, + uint64_t size, unsigned long *iova_p, phys_addr_t *pa_p, u32 *size_p) +{ + *iova_p = rounddown(iova, PAGE_SIZE); + *pa_p = rounddown(pa, PAGE_SIZE); + *size_p = roundup(size + pa - *pa_p, PAGE_SIZE); +} + +static void __map_smmu_info(struct device *dev, + struct imp_iova_addr *partition, int num_mapping, + struct ipa_mhi_mem_addr_info_type_v01 *map_info, + bool map) +{ + int i; + struct iommu_domain *domain; + unsigned long iova_p; + phys_addr_t pa_p; + u32 size_p; + + domain = iommu_get_domain_for_dev(dev); + if (!domain) { + IMP_ERR("domain is NULL for dev\n"); + return; + } + + for (i = 0; i < num_mapping; i++) { + int prot = IOMMU_READ | IOMMU_WRITE; + u32 ipa_base = ipa3_ctx->ipa_wrapper_base + + ipa3_ctx->ctrl->ipa_reg_base_ofst; + u32 ipa_size = ipa3_ctx->ipa_wrapper_size; + + imp_smmu_round_to_page(map_info[i].iova, map_info[i].pa, + map_info[i].size, &iova_p, &pa_p, &size_p); + + if (map) { + /* boundary check */ + WARN_ON(partition->base > iova_p || + (partition->base + partition->size) < + (iova_p + size_p)); + + /* for IPA uC MBOM we need to map with device type */ + if (pa_p - ipa_base < ipa_size) + prot |= IOMMU_MMIO; + + IMP_DBG("mapping 0x%lx to 0x%pa size %d\n", + iova_p, &pa_p, size_p); + iommu_map(domain, + iova_p, pa_p, size_p, prot); + } else { + IMP_DBG("unmapping 0x%lx to 0x%pa size %d\n", + iova_p, &pa_p, size_p); + iommu_unmap(domain, iova_p, size_p); + } + } +} + +static int __imp_configure_mhi_device( + struct ipa_mhi_alloc_channel_req_msg_v01 *req, + struct ipa_mhi_alloc_channel_resp_msg_v01 *resp) +{ + struct mhi_buf ch_config[2]; + int i; + struct ipa_mhi_er_info_type_v01 *er_info; + struct imp_channel *ch; + int ridx = 0; + int ret; + + IMP_FUNC_ENTRY(); + + /* configure MHI */ + for (i = 0; i < req->tr_info_arr_len; i++) { + ch = imp_get_ch_by_id(req->tr_info_arr[i].ch_id); + if (!ch) { + IMP_ERR("unknown channel %d\n", + req->tr_info_arr[i].ch_id); + resp->alloc_resp_arr[ridx].ch_id = + req->tr_info_arr[i].ch_id; + resp->alloc_resp_arr[ridx].is_success = 0; + ridx++; + resp->alloc_resp_arr_len = ridx; + resp->resp.result = IPA_QMI_RESULT_FAILURE_V01; + /* return INCOMPATIBLE_STATE in any case */ + resp->resp.error = + IPA_QMI_ERR_INCOMPATIBLE_STATE_V01; + return -EINVAL; + } + + /* populate CCA */ + if (req->tr_info_arr[i].brst_mode_type == + QMI_IPA_BURST_MODE_ENABLED_V01) + ch->props.ch_ctx.brsmode = 3; + else if (req->tr_info_arr[i].brst_mode_type == + QMI_IPA_BURST_MODE_DISABLED_V01) + ch->props.ch_ctx.brsmode = 2; + else + ch->props.ch_ctx.brsmode = 0; + + ch->props.ch_ctx.pollcfg = req->tr_info_arr[i].poll_cfg; + ch->props.ch_ctx.chtype = ch->props.dir; + ch->props.ch_ctx.erindex = ch->event.props.id; + ch->props.ch_ctx.rbase = req->tr_info_arr[i].ring_iova; + ch->props.ch_ctx.rlen = req->tr_info_arr[i].ring_len; + ch->props.ch_ctx.rpp = req->tr_info_arr[i].rp; + ch->props.ch_ctx.wpp = req->tr_info_arr[i].wp; + + ch_config[0].buf = &ch->props.ch_ctx; + ch_config[0].len = sizeof(ch->props.ch_ctx); + ch_config[0].name = "CCA"; + + /* populate ECA */ + er_info = _find_ch_in_er_info_arr(req, ch->event.props.id); + if (!er_info) { + IMP_ERR("no event ring for ch %d\n", + req->tr_info_arr[i].ch_id); + resp->alloc_resp_arr[ridx].ch_id = + req->tr_info_arr[i].ch_id; + resp->alloc_resp_arr[ridx].is_success = 0; + ridx++; + resp->alloc_resp_arr_len = ridx; + resp->resp.result = IPA_QMI_RESULT_FAILURE_V01; + resp->resp.error = IPA_QMI_ERR_INTERNAL_V01; + return -EINVAL; + } + + ch->event.props.ev_ctx.intmodc = er_info->intmod_count; + ch->event.props.ev_ctx.intmodt = er_info->intmod_cycles; + ch->event.props.ev_ctx.ertype = 1; + ch->event.props.ev_ctx.msivec = er_info->msi_addr; + ch->event.props.ev_ctx.rbase = er_info->ring_iova; + ch->event.props.ev_ctx.rlen = er_info->ring_len; + ch->event.props.ev_ctx.rpp = er_info->rp; + ch->event.props.ev_ctx.wpp = er_info->wp; + ch_config[1].buf = &ch->event.props.ev_ctx; + ch_config[1].len = sizeof(ch->event.props.ev_ctx); + ch_config[1].name = "ECA"; + + IMP_DBG("Configuring MHI device for ch %d\n", ch->props.id); + ret = mhi_device_configure(imp_ctx->md.mhi_dev, ch->props.dir, + ch_config, 2); + /* configure mhi-host, no need check mhi state */ + if (ret) { + IMP_ERR("mhi_device_configure failed for ch %d\n", + req->tr_info_arr[i].ch_id); + resp->alloc_resp_arr[ridx].ch_id = + req->tr_info_arr[i].ch_id; + resp->alloc_resp_arr[ridx].is_success = 0; + ridx++; + resp->alloc_resp_arr_len = ridx; + resp->resp.result = IPA_QMI_RESULT_FAILURE_V01; + resp->resp.error = IPA_QMI_ERR_INTERNAL_V01; + return -EINVAL; + } + } + + IMP_FUNC_EXIT(); + + return 0; +} + +/** + * imp_handle_allocate_channel_req() - Allocate a new MHI channel + * + * Allocates MHI channel and start them. + * + * Return: QMI return codes + */ +struct ipa_mhi_alloc_channel_resp_msg_v01 *imp_handle_allocate_channel_req( + struct ipa_mhi_alloc_channel_req_msg_v01 *req) +{ + int ret; + struct ipa_mhi_alloc_channel_resp_msg_v01 *resp = + &imp_ctx->qmi.alloc_ch_resp; + + IMP_FUNC_ENTRY(); + + mutex_lock(&imp_ctx->mutex); + + memset(resp, 0, sizeof(*resp)); + + if (imp_ctx->state != IMP_READY) { + IMP_ERR("invalid state %d\n", imp_ctx->state); + resp->resp.result = IPA_QMI_RESULT_FAILURE_V01; + resp->resp.error = IPA_QMI_ERR_INTERNAL_V01; + mutex_unlock(&imp_ctx->mutex); + return resp; + } + + /* cache the req */ + memcpy(&imp_ctx->qmi.alloc_ch_req, req, sizeof(*req)); + + if (req->tr_info_arr_len > QMI_IPA_REMOTE_MHI_CHANNELS_NUM_MAX_V01) { + IMP_ERR("invalid tr_info_arr_len %d\n", req->tr_info_arr_len); + resp->resp.result = IPA_QMI_RESULT_FAILURE_V01; + resp->resp.error = IPA_QMI_ERR_NO_MEMORY_V01; + mutex_unlock(&imp_ctx->mutex); + return resp; + } + + if ((req->ctrl_addr_map_info_len == 0 || + req->data_addr_map_info_len == 0) && + imp_ctx->dev_info.smmu_enabled) { + IMP_ERR("no mapping provided, but smmu is enabled\n"); + resp->resp.result = IPA_QMI_RESULT_FAILURE_V01; + resp->resp.error = IPA_QMI_ERR_INTERNAL_V01; + mutex_unlock(&imp_ctx->mutex); + return resp; + } + + if (imp_ctx->dev_info.smmu_enabled) { + /* map CTRL */ + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) + __map_smmu_info(imp_ctx->md.mhi_dev->dev.parent->parent, + #else + __map_smmu_info(imp_ctx->md.mhi_dev->dev.parent, + #endif + &imp_ctx->dev_info.ctrl, + req->ctrl_addr_map_info_len, + req->ctrl_addr_map_info, + true); + + /* map DATA */ + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) + __map_smmu_info(imp_ctx->md.mhi_dev->dev.parent->parent, + #else + __map_smmu_info(imp_ctx->md.mhi_dev->dev.parent, + #endif + &imp_ctx->dev_info.data, + req->data_addr_map_info_len, + req->data_addr_map_info, + true); + } + + resp->alloc_resp_arr_valid = true; + ret = __imp_configure_mhi_device(req, resp); + if (ret) + goto fail_smmu; + + IMP_DBG("Starting MHI channels %d and %d\n", + imp_ctx->md.ul_chan.props.id, + imp_ctx->md.dl_chan.props.id); + ret = mhi_prepare_for_transfer(imp_ctx->md.mhi_dev); + if (ret) { + IMP_ERR("mhi_prepare_for_transfer failed %d\n", ret); + resp->alloc_resp_arr[resp->alloc_resp_arr_len] + .ch_id = imp_ctx->md.ul_chan.props.id; + resp->alloc_resp_arr[resp->alloc_resp_arr_len] + .is_success = 0; + resp->alloc_resp_arr_len++; + resp->alloc_resp_arr[resp->alloc_resp_arr_len] + .ch_id = imp_ctx->md.dl_chan.props.id; + resp->alloc_resp_arr[resp->alloc_resp_arr_len] + .is_success = 0; + resp->alloc_resp_arr_len++; + resp->resp.result = IPA_QMI_RESULT_FAILURE_V01; + /* return INCOMPATIBLE_STATE in any case */ + resp->resp.error = IPA_QMI_ERR_INCOMPATIBLE_STATE_V01; + goto fail_smmu; + } + + resp->alloc_resp_arr[resp->alloc_resp_arr_len] + .ch_id = imp_ctx->md.ul_chan.props.id; + resp->alloc_resp_arr[resp->alloc_resp_arr_len] + .is_success = 1; + resp->alloc_resp_arr_len++; + + resp->alloc_resp_arr[resp->alloc_resp_arr_len] + .ch_id = imp_ctx->md.dl_chan.props.id; + resp->alloc_resp_arr[resp->alloc_resp_arr_len] + .is_success = 1; + resp->alloc_resp_arr_len++; + + imp_ctx->state = IMP_STARTED; + mutex_unlock(&imp_ctx->mutex); + IMP_FUNC_EXIT(); + + resp->resp.result = IPA_QMI_RESULT_SUCCESS_V01; + return resp; + +fail_smmu: + if (imp_ctx->dev_info.smmu_enabled) { + /* unmap CTRL */ + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) + __map_smmu_info(imp_ctx->md.mhi_dev->dev.parent->parent, + #else + __map_smmu_info(imp_ctx->md.mhi_dev->dev.parent, + #endif + &imp_ctx->dev_info.ctrl, + req->ctrl_addr_map_info_len, + req->ctrl_addr_map_info, + false); + + /* unmap DATA */ + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) + __map_smmu_info(imp_ctx->md.mhi_dev->dev.parent->parent, + #else + __map_smmu_info(imp_ctx->md.mhi_dev->dev.parent, + #endif + &imp_ctx->dev_info.data, + req->data_addr_map_info_len, + req->data_addr_map_info, + false); + } + mutex_unlock(&imp_ctx->mutex); + return resp; +} + +/** + * imp_handle_vote_req() - Votes for MHI / PCIe clocks + * + * Hold a vote to prevent / allow low power mode on MHI. + * + * Return: 0 on success, negative otherwise + */ +struct ipa_mhi_clk_vote_resp_msg_v01 + *imp_handle_vote_req(bool vote) +{ + int ret; + struct ipa_mhi_clk_vote_resp_msg_v01 *resp = + &imp_ctx->qmi.clk_vote_resp; + + IMP_DBG_LOW("vote %d\n", vote); + memset(resp, 0, sizeof(struct ipa_mhi_clk_vote_resp_msg_v01)); + resp->resp.result = IPA_QMI_RESULT_FAILURE_V01; + resp->resp.error = IPA_QMI_ERR_INCOMPATIBLE_STATE_V01; + + mutex_lock(&imp_ctx->mutex); + + /* + * returning success for clock unvote request - since it could + * be 5G modem SSR scenario where clocks are already OFF. + */ + if (!vote && imp_ctx->state == IMP_INVALID) { + IMP_DBG("Unvote in Invalid state, no op for clock unvote\n"); + mutex_unlock(&imp_ctx->mutex); + return resp; + } + + if (imp_ctx->state != IMP_STARTED) { + IMP_ERR("unexpected vote when in state %d\n", imp_ctx->state); + mutex_unlock(&imp_ctx->mutex); + return resp; + } + + if (vote == imp_ctx->lpm_disabled) { + IMP_ERR("already voted/devoted %d\n", vote); + mutex_unlock(&imp_ctx->mutex); + return resp; + } + mutex_unlock(&imp_ctx->mutex); + + /* + * Unlock the mutex before calling into mhi for clock vote + * to avoid deadlock on imp mutex. + * Calls into mhi are synchronous and imp callbacks are + * executed from mhi context. + */ + if (vote) { + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) + pm_runtime_get_sync(imp_ctx->md.mhi_dev->dev.parent->parent); + ret = mhi_device_get_sync(imp_ctx->md.mhi_dev); + #else + ret = mhi_device_get_sync(imp_ctx->md.mhi_dev, + MHI_VOTE_BUS | MHI_VOTE_DEVICE); + #endif + if (ret) { + IMP_ERR("mhi_sync_get failed %d\n", ret); + resp->resp.result = IPA_QMI_RESULT_FAILURE_V01; + /* return INCOMPATIBLE_STATE in any case */ + resp->resp.error = + IPA_QMI_ERR_INCOMPATIBLE_STATE_V01; + return resp; + } + } else { + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) + mhi_device_put(imp_ctx->md.mhi_dev); + pm_runtime_put(imp_ctx->md.mhi_dev->dev.parent->parent); + #else + mhi_device_put(imp_ctx->md.mhi_dev, + MHI_VOTE_BUS | MHI_VOTE_DEVICE); + #endif + } + + mutex_lock(&imp_ctx->mutex); + if (vote) + imp_ctx->lpm_disabled = true; + else + imp_ctx->lpm_disabled = false; + mutex_unlock(&imp_ctx->mutex); + + resp->resp.result = IPA_QMI_RESULT_SUCCESS_V01; + return resp; +} + +static int imp_read_iova_from_dtsi(const char *node, struct imp_iova_addr *out) +{ + u32 iova_mapping[2]; + struct device_node *of_node = imp_ctx->dev_info.pdev->dev.of_node; + + if (of_property_read_u32_array(of_node, node, iova_mapping, 2)) { + IMP_DBG("failed to read of_node %s\n", node); + return -EINVAL; + } + + out->base = iova_mapping[0]; + out->size = iova_mapping[1]; + IMP_DBG("%s: base: 0x%pad size: 0x%x\n", node, &out->base, out->size); + + return 0; +} + +static void imp_mhi_shutdown(void) +{ + struct ipa_mhi_cleanup_req_msg_v01 req = { 0 }; + + IMP_FUNC_ENTRY(); + + if (imp_ctx->state == IMP_STARTED || + imp_ctx->state == IMP_READY) { + req.cleanup_valid = true; + req.cleanup = true; + ipa3_qmi_send_mhi_cleanup_request(&req); + if (imp_ctx->dev_info.smmu_enabled) { + struct ipa_mhi_alloc_channel_req_msg_v01 *creq + = &imp_ctx->qmi.alloc_ch_req; + + /* unmap CTRL */ + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) + __map_smmu_info(imp_ctx->md.mhi_dev->dev.parent->parent, + #else + __map_smmu_info(imp_ctx->md.mhi_dev->dev.parent, + #endif + &imp_ctx->dev_info.ctrl, + creq->ctrl_addr_map_info_len, + creq->ctrl_addr_map_info, + false); + + /* unmap DATA */ + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) + __map_smmu_info(imp_ctx->md.mhi_dev->dev.parent->parent, + #else + __map_smmu_info(imp_ctx->md.mhi_dev->dev.parent, + #endif + &imp_ctx->dev_info.data, + creq->data_addr_map_info_len, + creq->data_addr_map_info, + false); + } + if (imp_ctx->lpm_disabled) { + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) + pm_runtime_put(imp_ctx->md.mhi_dev->dev.parent->parent); + #else + mhi_device_put(imp_ctx->md.mhi_dev, + MHI_VOTE_BUS); + #endif + imp_ctx->lpm_disabled = false; + } + + /* unmap MHI doorbells from IPA uC SMMU */ + if (!ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_UC]) { + struct ipa_smmu_cb_ctx *cb = + ipa3_get_smmu_ctx(IPA_SMMU_CB_UC); + unsigned long iova_p; + phys_addr_t pa_p; + u32 size_p; + + imp_smmu_round_to_page(imp_ctx->dev_info.chdb_base, + imp_ctx->dev_info.chdb_base, PAGE_SIZE, + &iova_p, &pa_p, &size_p); + + iommu_unmap(cb->iommu_domain, iova_p, size_p); + } + } + if (!imp_ctx->in_lpm && + (imp_ctx->state == IMP_READY || + imp_ctx->state == IMP_STARTED)) { + IMP_DBG("devote IMP with state= %d\n", imp_ctx->state); + IPA_ACTIVE_CLIENTS_DEC_SPECIAL("IMP"); + } + imp_ctx->in_lpm = false; + imp_ctx->state = IMP_PROBED; + + IMP_FUNC_EXIT(); +} + +static int imp_mhi_probe_cb(struct mhi_device *mhi_dev, + const struct mhi_device_id *id) +{ + struct imp_channel *ch; + struct imp_event *ev; + int ret; + + IMP_FUNC_ENTRY(); + + if (id != &mhi_driver_match_table[0]) { + IMP_ERR("only chan=%s is supported for now\n", + mhi_driver_match_table[0].chan); + return -EPERM; + } + + /* Read the MHI CH/ER DB address from MHI Driver. */ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) + ret = mhi_get_channel_db_base(mhi_dev, &imp_ctx->dev_info.chdb_base); + if (ret) { + IMP_ERR("Could not populate channel db base address\n"); + return -EINVAL; + } + + IMP_DBG("chdb-base=0x%x\n", imp_ctx->dev_info.chdb_base); + + ret = mhi_get_event_ring_db_base(mhi_dev, &imp_ctx->dev_info.erdb_base); + if (ret) { + IMP_ERR("Could not populate event ring db base address\n"); + return -EINVAL; + } + + IMP_DBG("erdb-base=0x%x\n", imp_ctx->dev_info.erdb_base); +#endif + + /* vote for IPA clock. IPA clock will be devoted when MHI enters LPM */ + IPA_ACTIVE_CLIENTS_INC_SPECIAL("IMP"); + + imp_ctx->md.mhi_dev = mhi_dev; + + mutex_lock(&imp_ctx->mutex); + /* store UL channel properties */ + ch = &imp_ctx->md.ul_chan; + ev = &imp_ctx->md.ul_chan.event; + + ch->props.id = mhi_dev->ul_chan_id; + ch->props.dir = DMA_TO_DEVICE; + ch->props.doorbell = imp_ctx->dev_info.chdb_base + ch->props.id * 8; + ch->props.uc_mbox_n = IMP_IPA_UC_UL_CH_n; + IMP_DBG("ul ch id %d doorbell 0x%pa uc_mbox_n %d\n", + ch->props.id, &ch->props.doorbell, ch->props.uc_mbox_n); + + ret = ipa3_uc_send_remote_ipa_info(ch->props.doorbell, + ch->props.uc_mbox_n); + if (ret) + goto fail; + IMP_DBG("mapped ch db 0x%pad to mbox %d\n", &ch->props.doorbell, + ch->props.uc_mbox_n); + + ev->props.id = mhi_dev->ul_event_id; + ev->props.doorbell = imp_ctx->dev_info.erdb_base + ev->props.id * 8; + ev->props.uc_mbox_n = IMP_IPA_UC_UL_EV_n; + IMP_DBG("allocated ev %d\n", ev->props.id); + + ret = ipa3_uc_send_remote_ipa_info(ev->props.doorbell, + ev->props.uc_mbox_n); + if (ret) + goto fail; + IMP_DBG("mapped ch db 0x%pad to mbox %d\n", &ev->props.doorbell, + ev->props.uc_mbox_n); + + /* store DL channel properties */ + ch = &imp_ctx->md.dl_chan; + ev = &imp_ctx->md.dl_chan.event; + + ch->props.dir = DMA_FROM_DEVICE; + ch->props.id = mhi_dev->dl_chan_id; + ch->props.doorbell = imp_ctx->dev_info.chdb_base + ch->props.id * 8; + ch->props.uc_mbox_n = IMP_IPA_UC_DL_CH_n; + IMP_DBG("dl ch id %d doorbell 0x%pa uc_mbox_n %d\n", + ch->props.id, &ch->props.doorbell, ch->props.uc_mbox_n); + + ret = ipa3_uc_send_remote_ipa_info(ch->props.doorbell, + ch->props.uc_mbox_n); + if (ret) + goto fail; + IMP_DBG("mapped ch db 0x%pad to mbox %d\n", &ch->props.doorbell, + ch->props.uc_mbox_n); + + ev->props.id = mhi_dev->dl_event_id; + ev->props.doorbell = imp_ctx->dev_info.erdb_base + ev->props.id * 8; + ev->props.uc_mbox_n = IMP_IPA_UC_DL_EV_n; + IMP_DBG("allocated ev %d\n", ev->props.id); + + ret = ipa3_uc_send_remote_ipa_info(ev->props.doorbell, + ev->props.uc_mbox_n); + if (ret) + goto fail; + IMP_DBG("mapped ch db 0x%pad to mbox %d\n", &ev->props.doorbell, + ev->props.uc_mbox_n); + + /* + * Map MHI doorbells to IPA uC SMMU. + * Both channel and event doorbells resides in a single page. + */ + if (!ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_UC]) { + struct ipa_smmu_cb_ctx *cb = + ipa3_get_smmu_ctx(IPA_SMMU_CB_UC); + unsigned long iova_p; + phys_addr_t pa_p; + u32 size_p; + + imp_smmu_round_to_page(imp_ctx->dev_info.chdb_base, + imp_ctx->dev_info.chdb_base, PAGE_SIZE, + &iova_p, &pa_p, &size_p); + + ret = ipa3_iommu_map(cb->iommu_domain, iova_p, pa_p, size_p, + IOMMU_READ | IOMMU_WRITE | IOMMU_MMIO); + if (ret) + goto fail; + } + + imp_mhi_trigger_ready_ind(); + + mutex_unlock(&imp_ctx->mutex); + + IMP_FUNC_EXIT(); + return 0; + +fail: + mutex_unlock(&imp_ctx->mutex); + IPA_ACTIVE_CLIENTS_DEC_SPECIAL("IMP"); + return ret; +} + +static void imp_mhi_remove_cb(struct mhi_device *mhi_dev) +{ + IMP_FUNC_ENTRY(); + + mutex_lock(&imp_ctx->mutex); + imp_mhi_shutdown(); + mutex_unlock(&imp_ctx->mutex); + IMP_FUNC_EXIT(); +} + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) +static void imp_mhi_status_cb(struct mhi_device *mhi_dev, enum mhi_callback mhi_cb) +#else +static void imp_mhi_status_cb(struct mhi_device *mhi_dev, enum MHI_CB mhi_cb) +#endif +{ + IMP_DBG("%d\n", mhi_cb); + + mutex_lock(&imp_ctx->lpm_mutex); + if (mhi_dev != imp_ctx->md.mhi_dev) { + IMP_DBG("ignoring secondary callbacks\n"); + mutex_unlock(&imp_ctx->lpm_mutex); + return; + } + + switch (mhi_cb) { + case MHI_CB_IDLE: + break; + case MHI_CB_LPM_ENTER: + if (imp_ctx->state == IMP_STARTED) { + if (!imp_ctx->in_lpm) { + IPA_ACTIVE_CLIENTS_DEC_SPECIAL("IMP"); + imp_ctx->in_lpm = true; + } else { + IMP_ERR("already in LPM\n"); + } + } + break; + case MHI_CB_LPM_EXIT: + if (imp_ctx->state == IMP_STARTED) { + if (imp_ctx->in_lpm) { + IPA_ACTIVE_CLIENTS_INC_SPECIAL("IMP"); + imp_ctx->in_lpm = false; + } else { + IMP_ERR("not in LPM\n"); + } + } + break; + + case MHI_CB_EE_RDDM: + case MHI_CB_PENDING_DATA: + default: + IMP_ERR("unexpected event %d\n", mhi_cb); + break; + } + mutex_unlock(&imp_ctx->lpm_mutex); +} + +static int imp_probe(struct platform_device *pdev) +{ + int ret; + + IMP_FUNC_ENTRY(); + + if (ipa3_uc_state_check()) { + IMP_DBG("uC not ready yet\n"); + return -EPROBE_DEFER; + } + + imp_ctx->dev_info.pdev = pdev; + imp_ctx->dev_info.smmu_enabled = true; + ret = imp_read_iova_from_dtsi("qcom,ctrl-iova", + &imp_ctx->dev_info.ctrl); + if (ret) + imp_ctx->dev_info.smmu_enabled = false; + + ret = imp_read_iova_from_dtsi("qcom,data-iova", + &imp_ctx->dev_info.data); + if (ret) + imp_ctx->dev_info.smmu_enabled = false; + + IMP_DBG("smmu_enabled=%d\n", imp_ctx->dev_info.smmu_enabled); + + /* Read the MHI CH/ER DB address from DT. */ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) + if (of_property_read_u32(pdev->dev.of_node, "qcom,mhi-chdb-base", + &imp_ctx->dev_info.chdb_base)) { + IMP_ERR("failed to read of_node %s\n", "qcom,mhi-chdb-base"); + return -EINVAL; + } + IMP_DBG("chdb-base=0x%x\n", imp_ctx->dev_info.chdb_base); + + if (of_property_read_u32(pdev->dev.of_node, "qcom,mhi-erdb-base", + &imp_ctx->dev_info.erdb_base)) { + IMP_ERR("failed to read of_node %s\n", "qcom,mhi-erdb-base"); + return -EINVAL; + } + IMP_DBG("erdb-base=0x%x\n", imp_ctx->dev_info.erdb_base); +#endif + + imp_ctx->state = IMP_PROBED; + ret = mhi_driver_register(&mhi_driver); + if (ret) { + IMP_ERR("mhi_driver_register failed %d\n", ret); + mutex_unlock(&imp_ctx->mutex); + return ret; + } + + IMP_FUNC_EXIT(); + return 0; +} + +static int imp_remove(struct platform_device *pdev) +{ + IMP_FUNC_ENTRY(); + mhi_driver_unregister(&mhi_driver); + mutex_lock(&imp_ctx->mutex); + if (!imp_ctx->in_lpm && (imp_ctx->state == IMP_READY || + imp_ctx->state == IMP_STARTED)) { + IMP_DBG("devote IMP with state= %d\n", imp_ctx->state); + IPA_ACTIVE_CLIENTS_DEC_SPECIAL("IMP"); + } + imp_ctx->lpm_disabled = false; + imp_ctx->state = IMP_INVALID; + mutex_unlock(&imp_ctx->mutex); + + mutex_lock(&imp_ctx->lpm_mutex); + imp_ctx->in_lpm = false; + mutex_unlock(&imp_ctx->lpm_mutex); + + return 0; +} + +static const struct of_device_id imp_dt_match[] = { + { .compatible = "qcom,ipa-mhi-proxy" }, + {}, +}; +MODULE_DEVICE_TABLE(of, imp_dt_match); + +static struct platform_driver ipa_mhi_proxy_driver = { + .driver = { + .name = "ipa_mhi_proxy", + .of_match_table = imp_dt_match, + }, + .probe = imp_probe, + .remove = imp_remove, +}; + +/** + * imp_handle_modem_ready() - Registers IMP as a platform device + * + * This function is called after modem is loaded and QMI handshake is done. + * IMP will register itself as a platform device, and on support device the + * probe function will get called. + * + * Return: None + */ +void imp_handle_modem_ready(void) +{ + + if (!imp_ctx) { + imp_ctx = kzalloc(sizeof(*imp_ctx), GFP_KERNEL); + if (!imp_ctx) + return; + + mutex_init(&imp_ctx->mutex); + mutex_init(&imp_ctx->lpm_mutex); + } + + if (imp_ctx->state != IMP_INVALID) { + IMP_ERR("unexpected state %d\n", imp_ctx->state); + return; + } + + IMP_DBG("register platform device\n"); + platform_driver_register(&ipa_mhi_proxy_driver); +} + +/** + * imp_handle_modem_shutdown() - Handles modem SSR + * + * Performs MHI cleanup when modem is going to SSR (Subsystem Restart). + * + * Return: None + */ +void imp_handle_modem_shutdown(void) +{ + IMP_FUNC_ENTRY(); + + if (!imp_ctx) + return; + + mutex_lock(&imp_ctx->mutex); + + if (imp_ctx->state == IMP_INVALID) { + mutex_unlock(&imp_ctx->mutex); + return; + } + if (imp_ctx->state == IMP_STARTED) { + mhi_unprepare_from_transfer(imp_ctx->md.mhi_dev); + imp_ctx->state = IMP_READY; + } + + if (imp_ctx->state == IMP_READY) { + if (imp_ctx->dev_info.smmu_enabled) { + struct ipa_mhi_alloc_channel_req_msg_v01 *creq + = &imp_ctx->qmi.alloc_ch_req; + + /* unmap CTRL */ + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) + __map_smmu_info(imp_ctx->md.mhi_dev->dev.parent->parent, + #else + __map_smmu_info(imp_ctx->md.mhi_dev->dev.parent, + #endif + &imp_ctx->dev_info.ctrl, + creq->ctrl_addr_map_info_len, + creq->ctrl_addr_map_info, + false); + + /* unmap DATA */ + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) + __map_smmu_info(imp_ctx->md.mhi_dev->dev.parent->parent, + #else + __map_smmu_info(imp_ctx->md.mhi_dev->dev.parent, + #endif + &imp_ctx->dev_info.data, + creq->data_addr_map_info_len, + creq->data_addr_map_info, + false); + } + } + + mutex_unlock(&imp_ctx->mutex); + + IMP_FUNC_EXIT(); + + platform_driver_unregister(&ipa_mhi_proxy_driver); +} + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("IPA MHI Proxy Driver"); diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_mhi_proxy.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_mhi_proxy.h new file mode 100644 index 0000000000..405308b770 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_mhi_proxy.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + */ + +#ifndef __IMP_H_ +#define __IMP_H_ + +#ifdef CONFIG_IPA3_MHI_PROXY + +#include "ipa_qmi_service.h" + +void imp_handle_modem_ready(void); + +struct ipa_mhi_alloc_channel_resp_msg_v01 *imp_handle_allocate_channel_req( + struct ipa_mhi_alloc_channel_req_msg_v01 *req); + +struct ipa_mhi_clk_vote_resp_msg_v01 *imp_handle_vote_req(bool vote); + +void imp_handle_modem_shutdown(void); + +#else /* CONFIG_IPA3_MHI_PROXY */ + +static inline void imp_handle_modem_ready(void) +{ + +} + +static inline struct ipa_mhi_alloc_channel_resp_msg_v01 + *imp_handle_allocate_channel_req( + struct ipa_mhi_alloc_channel_req_msg_v01 *req) +{ + return NULL; +} + +static inline struct ipa_mhi_clk_vote_resp_msg_v01 + *imp_handle_vote_req(bool vote) +{ + return NULL; +} + +static inline void imp_handle_modem_shutdown(void) +{ + +} + +#endif /* CONFIG_IPA3_MHI_PROXY */ + +#endif /* __IMP_H_ */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_mpm.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_mpm.c new file mode 100644 index 0000000000..dc3b92a62c --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_mpm.c @@ -0,0 +1,3587 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) +#include +#include +#endif +#include +#include +#include +#include +#include "gsi.h" +#include "ipa_common_i.h" +#include "ipa_i.h" +#include "ipa_qmi_service.h" + +#define IPA_MPM_DRV_NAME "ipa_mpm" + +#define IPA_MPM_DBG(fmt, args...) \ + do { \ + pr_debug(IPA_MPM_DRV_NAME " %s:%d " fmt, \ + __func__, __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf(), \ + IPA_MPM_DRV_NAME " %s:%d " fmt, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf_low(), \ + IPA_MPM_DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) + +#define IPA_MPM_DBG_LOW(fmt, args...) \ + do { \ + pr_debug(IPA_MPM_DRV_NAME " %s:%d " fmt, \ + __func__, __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf_low(), \ + IPA_MPM_DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) + + +#define IPA_MPM_ERR(fmt, args...) \ + do { \ + pr_err(IPA_MPM_DRV_NAME " %s:%d " fmt, \ + __func__, __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf(), \ + IPA_MPM_DRV_NAME " %s:%d " fmt, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf_low(), \ + IPA_MPM_DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) + + +#define IPA_MPM_FUNC_ENTRY() \ + IPA_MPM_DBG("ENTRY\n") +#define IPA_MPM_FUNC_EXIT() \ + IPA_MPM_DBG("EXIT\n") + +#define IPA_MPM_MAX_MHIP_CHAN 3 + +#define IPA_MPM_MHI_HOST_UL_CHANNEL 4 +#define IPA_MPM_MHI_HOST_DL_CHANNEL 5 +#define TETH_AGGR_TIME_LIMIT 1000 /* 1ms */ +#define TETH_AGGR_BYTE_LIMIT 24 +#define TETH_AGGR_DL_BYTE_LIMIT 16 +#define TRE_BUFF_SIZE 32768 +#define RNDIS_IPA_DFLT_RT_HDL 0 +#define IPA_POLL_FOR_EMPTINESS_NUM 50 +#define IPA_POLL_FOR_EMPTINESS_SLEEP_USEC 20 +#define IPA_CHANNEL_STOP_IN_PROC_TO_MSEC 5 +#define IPA_CHANNEL_STOP_IN_PROC_SLEEP_USEC 200 +#define IPA_MHIP_HOLB_TMO 31 /* value to match granularity on ipa HW 4.5 */ +#define IPA_MPM_FLOW_CTRL_ADD 1 +#define IPA_MPM_FLOW_CTRL_DELETE 0 +#define IPA_MPM_NUM_OF_INIT_CMD_DESC 2 + +enum mhip_re_type { + MHIP_RE_XFER = 0x2, + MHIP_RE_NOP = 0x4, +}; + +enum ipa_mpm_mhi_ch_id_type { + IPA_MPM_MHIP_CH_ID_0, + IPA_MPM_MHIP_CH_ID_1, + IPA_MPM_MHIP_CH_ID_2, + IPA_MPM_MHIP_CH_ID_MAX, +}; + +enum ipa_mpm_dma_data_direction { + DMA_HIPA_BIDIRECTIONAL = 0, + DMA_TO_HIPA = 1, + DMA_FROM_HIPA = 2, + DMA_HIPA_NONE = 3, +}; + +enum ipa_mpm_ipa_teth_client_type { + IPA_MPM_MHIP_USB, + IPA_MPM_MHIP_WIFI, +}; + +enum ipa_mpm_mhip_client_type { + IPA_MPM_MHIP_INIT, + /* USB RMNET CLIENT */ + IPA_MPM_MHIP_USB_RMNET, + /* USB RNDIS / WIFI CLIENT */ + IPA_MPM_MHIP_TETH, + /* USB DPL CLIENT */ + IPA_MPM_MHIP_USB_DPL, + IPA_MPM_MHIP_NONE, +}; + +enum ipa_mpm_clk_vote_type { + CLK_ON, + CLK_OFF, +}; + +enum mhip_status_type { + MHIP_STATUS_SUCCESS, + MHIP_STATUS_NO_OP, + MHIP_STATUS_FAIL, + MHIP_STATUS_BAD_STATE, + MHIP_STATUS_EP_NOT_FOUND, + MHIP_STATUS_EP_NOT_READY, +}; + +enum mhip_smmu_domain_type { + MHIP_SMMU_DOMAIN_IPA, + MHIP_SMMU_DOMAIN_PCIE, + MHIP_SMMU_DOMAIN_NONE, +}; + +enum ipa_mpm_start_stop_type { + MPM_MHIP_STOP, + MPM_MHIP_START, +}; +/* each pair of UL/DL channels are defined below */ +static const struct mhi_device_id mhi_driver_match_table[] = { + { .chan = "IP_HW_MHIP_0" }, /* for rndis/Wifi teth pipes */ + { .chan = "IP_HW_MHIP_1" }, /* for MHIP rmnet */ + { .chan = "IP_HW_ADPL" }, /* ADPL/ODL DL pipe */ + {}, +}; + +static const char *ipa_mpm_mhip_chan_str[IPA_MPM_MHIP_CH_ID_MAX] = { + __stringify(IPA_MPM_MHIP_TETH), + __stringify(IPA_MPM_MHIP_USB_RMNET), + __stringify(IPA_MPM_MHIP_USB_DPL), +}; +/* + * MHI PRIME GSI Descriptor format that Host IPA uses. + */ +struct __packed mhi_p_desc { + uint64_t buffer_ptr; + uint16_t buff_len; + uint16_t resvd1; + uint16_t chain : 1; + uint16_t resvd4 : 7; + uint16_t ieob : 1; + uint16_t ieot : 1; + uint16_t bei : 1; + uint16_t sct : 1; + uint16_t resvd3 : 4; + uint8_t re_type; + uint8_t resvd2; +}; + +/* + * MHI PRIME Channel Context and Event Context Array + * Information that is sent to Device IPA. + */ +struct ipa_mpm_channel_context_type { + u32 chstate : 8; + u32 reserved1 : 24; + u32 chtype; + u32 erindex; + u64 rbase; + u64 rlen; + u64 reserved2; + u64 reserved3; +} __packed; + +struct ipa_mpm_event_context_type { + u32 reserved1 : 8; + u32 update_rp_modc : 8; + u32 update_rp_intmodt : 16; + u32 ertype; + u32 update_rp_addr; + u64 rbase; + u64 rlen; + u32 buff_size : 16; + u32 reserved2 : 16; + u32 reserved3; + u64 reserved4; +} __packed; + +struct ipa_mpm_pipes_info_type { + enum ipa_client_type ipa_client; + struct ipa_ep_cfg ep_cfg; +}; + +struct ipa_mpm_channel_type { + struct ipa_mpm_pipes_info_type dl_cons; + struct ipa_mpm_pipes_info_type ul_prod; + enum ipa_mpm_mhip_client_type mhip_client; +}; + +static struct ipa_mpm_channel_type ipa_mpm_pipes[IPA_MPM_MHIP_CH_ID_MAX]; + +/* For configuring IPA_CLIENT_MHI_PRIME_TETH_CONS */ +static struct ipa_ep_cfg mhip_dl_teth_ep_cfg = { + .mode = { + .mode = IPA_BASIC, + .dst = IPA_CLIENT_MHI_PRIME_TETH_CONS, + }, + .hdr = { + .hdr_len = 4, + .hdr_ofst_metadata_valid = 1, + .hdr_ofst_metadata = 1, + .hdr_ofst_pkt_size_valid = 1, + .hdr_ofst_pkt_size = 2, + }, + .hdr_ext = { + .hdr_total_len_or_pad_valid = true, + .hdr_payload_len_inc_padding = true, + }, + .aggr = { + .aggr_en = IPA_ENABLE_DEAGGR, + .aggr = IPA_QCMAP, + .aggr_byte_limit = TETH_AGGR_DL_BYTE_LIMIT, + .aggr_time_limit = TETH_AGGR_TIME_LIMIT, + }, +}; + +static struct ipa_ep_cfg mhip_ul_teth_ep_cfg = { + .mode = { + .mode = IPA_BASIC, + .dst = IPA_CLIENT_MHI_PRIME_TETH_PROD, + }, + .hdr = { + .hdr_len = 4, + .hdr_ofst_metadata_valid = 1, + .hdr_ofst_metadata = 0, + .hdr_ofst_pkt_size_valid = 1, + .hdr_ofst_pkt_size = 2, + }, + .hdr_ext = { + .hdr_total_len_or_pad_valid = true, + .hdr_payload_len_inc_padding = true, + }, + .aggr = { + .aggr_en = IPA_ENABLE_AGGR, + .aggr = IPA_QCMAP, + .aggr_byte_limit = TETH_AGGR_BYTE_LIMIT, + .aggr_time_limit = TETH_AGGR_TIME_LIMIT, + }, + +}; + +/* WARNING!! Temporary for rndis intgration only */ + + +/* For configuring IPA_CLIENT_MHIP_RMNET_PROD */ +static struct ipa_ep_cfg mhip_dl_rmnet_ep_cfg = { + .mode = { + .mode = IPA_DMA, + .dst = IPA_CLIENT_USB_CONS, + }, +}; + +/* For configuring IPA_CLIENT_MHIP_RMNET_CONS */ +static struct ipa_ep_cfg mhip_ul_rmnet_ep_cfg = { + .mode = { + .mode = IPA_DMA, + .dst = IPA_CLIENT_USB_CONS, + }, +}; + +/* For configuring IPA_CLIENT_MHIP_DPL_PROD using USB*/ +static struct ipa_ep_cfg mhip_dl_dpl_ep_cfg = { + .mode = { + .mode = IPA_DMA, + .dst = IPA_CLIENT_USB_DPL_CONS, + }, +}; + + +struct ipa_mpm_iova_addr { + dma_addr_t base; + unsigned int size; +}; + +struct ipa_mpm_dev_info { + struct platform_device *pdev; + struct device *dev; + bool ipa_smmu_enabled; + bool pcie_smmu_enabled; + struct ipa_mpm_iova_addr ctrl; + struct ipa_mpm_iova_addr data; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) + phys_addr_t chdb_base; + phys_addr_t erdb_base; +#else + u32 chdb_base; + u32 erdb_base; +#endif + + bool is_cache_coherent; +}; + +struct ipa_mpm_event_props { + u16 id; + phys_addr_t device_db; + struct ipa_mpm_event_context_type ev_ctx; +}; + +struct ipa_mpm_channel_props { + u16 id; + phys_addr_t device_db; + struct ipa_mpm_channel_context_type ch_ctx; +}; + +enum ipa_mpm_gsi_state { + GSI_ERR, + GSI_INIT, + GSI_ALLOCATED, + GSI_STARTED, + GSI_STOPPED, +}; + +enum ipa_mpm_remote_state { + MPM_MHIP_REMOTE_STOP, + MPM_MHIP_REMOTE_START, + MPM_MHIP_REMOTE_ERR, +}; + +struct ipa_mpm_channel { + struct ipa_mpm_channel_props chan_props; + struct ipa_mpm_event_props evt_props; + enum ipa_mpm_gsi_state gsi_state; + dma_addr_t db_host_iova; + dma_addr_t db_device_iova; +}; + +enum ipa_mpm_teth_state { + IPA_MPM_TETH_INIT = 0, + IPA_MPM_TETH_INPROGRESS, + IPA_MPM_TETH_CONNECTED, +}; + +enum ipa_mpm_mhip_chan { + IPA_MPM_MHIP_CHAN_UL, + IPA_MPM_MHIP_CHAN_DL, + IPA_MPM_MHIP_CHAN_BOTH, +}; + +struct ipa_mpm_clk_cnt_type { + atomic_t pcie_clk_cnt; + atomic_t ipa_clk_cnt; +}; + +struct producer_rings { + struct mhi_p_desc *tr_va; + struct mhi_p_desc *er_va; + void *tr_buff_va[IPA_MPM_MAX_RING_LEN]; + dma_addr_t tr_pa; + dma_addr_t er_pa; + dma_addr_t tr_buff_c_iova[IPA_MPM_MAX_RING_LEN]; + /* + * The iova generated for AP CB, + * used only for dma_map_single to flush the cache. + */ + dma_addr_t ap_iova_er; + dma_addr_t ap_iova_tr; + dma_addr_t ap_iova_buff[IPA_MPM_MAX_RING_LEN]; +}; + +struct ipa_mpm_mhi_driver { + struct mhi_device *mhi_dev; + struct producer_rings ul_prod_ring; + struct producer_rings dl_prod_ring; + struct ipa_mpm_channel ul_prod; + struct ipa_mpm_channel dl_cons; + enum ipa_mpm_mhip_client_type mhip_client; + enum ipa_mpm_teth_state teth_state; + bool init_complete; + /* General MPM mutex to protect concurrent update of MPM GSI states */ + struct mutex mutex; + /* + * Mutex to protect mhi_dev update/ access, for concurrency such as + * 5G SSR and USB disconnect/connect. + */ + struct mutex mhi_mutex; + bool in_lpm; + struct ipa_mpm_clk_cnt_type clk_cnt; + enum ipa_mpm_remote_state remote_state; +}; + +struct ipa_mpm_context { + struct ipa_mpm_dev_info dev_info; + struct ipa_mpm_mhi_driver md[IPA_MPM_MAX_MHIP_CHAN]; + struct mutex mutex; + atomic_t probe_cnt; + atomic_t pcie_clk_total_cnt; + atomic_t ipa_clk_total_cnt; + atomic_t flow_ctrl_mask; + atomic_t adpl_over_usb_available; + atomic_t adpl_over_odl_available; + atomic_t active_teth_count; + atomic_t voted_before; + struct device *parent_pdev; + struct ipa_smmu_cb_ctx carved_smmu_cb; + struct device *mhi_parent_dev; +}; + +#define IPA_MPM_DESC_SIZE (sizeof(struct mhi_p_desc)) +/* WA: Make the IPA_MPM_PAGE_SIZE from 16k (next power of ring size) to + * 32k. This is to make sure IOMMU map happens for the same size + * for all TR/ER and doorbells. + */ +#define IPA_MPM_PAGE_SIZE TRE_BUFF_SIZE + + +static struct ipa_mpm_context *ipa_mpm_ctx; +static struct platform_device *m_pdev; +static int ipa_mpm_mhi_probe_cb(struct mhi_device *, + const struct mhi_device_id *); +static void ipa_mpm_mhi_remove_cb(struct mhi_device *); +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) +static void ipa_mpm_mhi_status_cb(struct mhi_device *, enum mhi_callback); +#else +static void ipa_mpm_mhi_status_cb(struct mhi_device *, enum MHI_CB); +#endif +static void ipa_mpm_change_teth_state(int probe_id, + enum ipa_mpm_teth_state ip_state); +static void ipa_mpm_change_gsi_state(int probe_id, + enum ipa_mpm_mhip_chan mhip_chan, + enum ipa_mpm_gsi_state next_state); +static int ipa_mpm_probe(struct platform_device *pdev); +static int ipa_mpm_vote_unvote_pcie_clk(enum ipa_mpm_clk_vote_type vote, + int probe_id, bool is_force, bool *is_acted); +static void ipa_mpm_vote_unvote_ipa_clk(enum ipa_mpm_clk_vote_type vote, + int probe_id); +static enum mhip_status_type ipa_mpm_start_stop_mhip_chan( + enum ipa_mpm_mhip_chan mhip_chan, + int probe_id, + enum ipa_mpm_start_stop_type start_stop); +static int ipa_mpm_start_mhip_holb_tmo(u32 clnt_hdl); + +static struct mhi_driver mhi_driver = { + .id_table = mhi_driver_match_table, + .probe = ipa_mpm_mhi_probe_cb, + .remove = ipa_mpm_mhi_remove_cb, + .status_cb = ipa_mpm_mhi_status_cb, + .driver = { + .name = IPA_MPM_DRV_NAME, + .owner = THIS_MODULE, + }, +}; + +static void ipa_mpm_ipa3_delayed_probe(struct work_struct *work) +{ + (void)ipa_mpm_probe(m_pdev); +} + +static DECLARE_WORK(ipa_mpm_ipa3_scheduled_probe, ipa_mpm_ipa3_delayed_probe); + +static void ipa_mpm_ipa3_ready_cb(void *user_data) +{ + struct platform_device *pdev = (struct platform_device *)(user_data); + + m_pdev = pdev; + + IPA_MPM_DBG("IPA ready callback has been triggered\n"); + + schedule_work(&ipa_mpm_ipa3_scheduled_probe); +} + +static void ipa_mpm_gsi_evt_ring_err_cb(struct gsi_evt_err_notify *err_data) +{ + IPA_MPM_ERR("GSI EVT RING ERROR, not expected..\n"); + ipa_assert(); +} + +static void ipa_mpm_gsi_chan_err_cb(struct gsi_chan_err_notify *err_data) +{ + IPA_MPM_ERR("GSI CHAN ERROR, not expected..\n"); + ipa_assert(); +} + +static int ipa_mpm_set_dma_mode(enum ipa_client_type src_pipe, + enum ipa_client_type dst_pipe, bool reset) +{ + struct ipahal_imm_cmd_pyld *cmd_pyld[IPA_MPM_NUM_OF_INIT_CMD_DESC]; + struct ipahal_imm_cmd_register_write reg_write_coal_close; + struct ipahal_reg_valmask valmask; + struct ipa3_desc desc[IPA_MPM_NUM_OF_INIT_CMD_DESC]; + int i, num_cmd = 0, result = 0; + struct ipa_ep_cfg ep_cfg = { { 0 } }; + + IPA_MPM_FUNC_ENTRY(); + IPA_MPM_DBG("DMA from %d to %d reset=%d\n", src_pipe, dst_pipe, reset); + + memset(desc, 0, sizeof(desc)); + memset(cmd_pyld, 0, sizeof(cmd_pyld)); + + /* First step is to clear IPA Pipeline before changing DMA mode */ + if (ipa_get_ep_mapping(src_pipe) != IPA_EP_NOT_ALLOCATED) { + u32 offset = 0; + + i = ipa_get_ep_mapping(src_pipe); + reg_write_coal_close.skip_pipeline_clear = false; + reg_write_coal_close.pipeline_clear_options = IPAHAL_HPS_CLEAR; + if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0) + offset = ipahal_get_reg_ofst( + IPA_AGGR_FORCE_CLOSE); + else + offset = ipahal_get_ep_reg_offset( + IPA_AGGR_FORCE_CLOSE_n, i); + reg_write_coal_close.offset = offset; + ipahal_get_aggr_force_close_valmask(i, &valmask); + reg_write_coal_close.value = valmask.val; + reg_write_coal_close.value_mask = valmask.mask; + cmd_pyld[num_cmd] = ipahal_construct_imm_cmd( + IPA_IMM_CMD_REGISTER_WRITE, + ®_write_coal_close, false); + + if (!cmd_pyld[num_cmd]) { + IPA_MPM_ERR("failed to construct coal close IC\n"); + result = -ENOMEM; + goto destroy_imm_cmd; + } + ipa3_init_imm_cmd_desc(&desc[num_cmd], cmd_pyld[num_cmd]); + ++num_cmd; + } + /* NO-OP IC for ensuring that IPA pipeline is empty */ + cmd_pyld[num_cmd] = + ipahal_construct_nop_imm_cmd(false, IPAHAL_HPS_CLEAR, false); + if (!cmd_pyld[num_cmd]) { + IPA_MPM_ERR("failed to construct NOP imm cmd\n"); + result = -ENOMEM; + goto destroy_imm_cmd; + } + + result = ipa3_send_cmd(num_cmd, desc); + if (result) { + IPAERR("fail to send Reset Pipeline immediate command\n"); + goto destroy_imm_cmd; + } + + /* Reset to basic if reset = 1, otherwise set to DMA */ + if (reset) + ep_cfg.mode.mode = IPA_BASIC; + else + ep_cfg.mode.mode = IPA_DMA; + ep_cfg.mode.dst = dst_pipe; + ep_cfg.seq.set_dynamic = true; + + result = ipa3_cfg_ep(ipa_get_ep_mapping(src_pipe), &ep_cfg); + IPA_MPM_FUNC_EXIT(); + +destroy_imm_cmd: + for (i = 0; i < num_cmd; ++i) + ipahal_destroy_imm_cmd(cmd_pyld[i]); + + return result; +} + +static int ipa_mpm_start_mhip_holb_tmo(u32 clnt_hdl) +{ + struct ipa_ep_cfg_holb holb_cfg; + + memset(&holb_cfg, 0, sizeof(holb_cfg)); + holb_cfg.en = IPA_HOLB_TMR_EN; + /* 31 ms timer, which is less than tag timeout */ + holb_cfg.tmr_val = IPA_MHIP_HOLB_TMO; + return ipa3_cfg_ep_holb(clnt_hdl, &holb_cfg); +} + +/** + * ipa_mpm_smmu_map() - SMMU maps ring and the buffer pointer. + * @va_addr: virtual address that needs to be mapped + * @sz: size of the address to be mapped + * @dir: ipa_mpm_dma_data_direction + * @ap_cb_iova: iova for AP context bank + * + * This function SMMU maps both ring and the buffer pointer. + * The ring pointers will be aligned to ring size and + * the buffer pointers should be aligned to buffer size. + * + * Returns: iova of the mapped address + */ +static dma_addr_t ipa_mpm_smmu_map(void *va_addr, + int sz, + int dir, + dma_addr_t *ap_cb_iova) +{ + struct iommu_domain *ipa_smmu_domain, *pcie_smmu_domain; + phys_addr_t phys_addr; + dma_addr_t iova; + int smmu_enabled; + unsigned long iova_p; + phys_addr_t pa_p; + u32 size_p; + int prot = IOMMU_READ | IOMMU_WRITE; + struct ipa_smmu_cb_ctx *cb = &ipa_mpm_ctx->carved_smmu_cb; + unsigned long carved_iova = roundup(cb->next_addr, IPA_MPM_PAGE_SIZE); + int ret = 0; + + /* check cache coherent */ + if (ipa_mpm_ctx->dev_info.is_cache_coherent) { + IPA_MPM_DBG_LOW("enable cache coherent\n"); + prot |= IOMMU_CACHE; + } + + if (carved_iova >= cb->va_end) { + IPA_MPM_ERR("running out of carved_iova %lx\n", carved_iova); + ipa_assert(); + } + /* + * Both Host IPA and PCIE SMMU should be enabled or disabled + * for proceed. + * If SMMU Enabled => iova == pa + * If SMMU Disabled => iova == iommu mapped iova + * dma_map_single ensures cache is flushed and the memory is not + * touched again until dma_unmap_single() is called + */ + smmu_enabled = (ipa_mpm_ctx->dev_info.ipa_smmu_enabled && + ipa_mpm_ctx->dev_info.pcie_smmu_enabled) ? 1 : 0; + + if (smmu_enabled) { + /* Map the phys addr to both PCIE and IPA AP CB + * from the carved out common iova range. + */ + ipa_smmu_domain = ipa3_get_smmu_domain(); + + if (!ipa_smmu_domain) { + IPA_MPM_ERR("invalid IPA smmu domain\n"); + ipa_assert(); + } + + if (!ipa_mpm_ctx->mhi_parent_dev) { + IPA_MPM_ERR("invalid PCIE SMMU domain\n"); + ipa_assert(); + } + + phys_addr = virt_to_phys((void *) va_addr); + + IPA_SMMU_ROUND_TO_PAGE(carved_iova, phys_addr, sz, + iova_p, pa_p, size_p); + + /* Flush the cache with dma_map_single for IPA AP CB */ + *ap_cb_iova = dma_map_single(ipa3_ctx->pdev, va_addr, + size_p, dir); + + if (dma_mapping_error(ipa3_ctx->pdev, *ap_cb_iova)) { + IPA_MPM_ERR("dma_map_single failure for entry\n"); + goto fail_dma_mapping; + } + + ret = ipa3_iommu_map(ipa_smmu_domain, iova_p, + pa_p, size_p, prot); + if (ret) { + IPA_MPM_ERR("IPA IOMMU returned failure, ret = %d\n", + ret); + ipa_assert(); + } + + pcie_smmu_domain = iommu_get_domain_for_dev( + ipa_mpm_ctx->mhi_parent_dev); + if (!pcie_smmu_domain) { + IPA_MPM_ERR("invalid pcie smmu domain\n"); + ipa_assert(); + } + ret = iommu_map(pcie_smmu_domain, iova_p, pa_p, size_p, prot); + + if (ret) { + IPA_MPM_ERR("PCIe IOMMU returned failure, ret = %d\n", + ret); + ipa_assert(); + } + + cb->next_addr = iova_p + size_p; + iova = iova_p; + } else { + if (dir == DMA_TO_HIPA) + iova = dma_map_single(ipa3_ctx->pdev, va_addr, + ipa3_ctx->mpm_ring_size_dl * + IPA_MPM_DESC_SIZE, dir); + else + iova = dma_map_single(ipa3_ctx->pdev, va_addr, + ipa3_ctx->mpm_ring_size_ul * + IPA_MPM_DESC_SIZE, dir); + + if (dma_mapping_error(ipa3_ctx->pdev, iova)) { + IPA_MPM_ERR("dma_map_single failure for entry\n"); + goto fail_dma_mapping; + } + + *ap_cb_iova = iova; + } + return iova; + +fail_dma_mapping: + iova = 0; + ipa_assert(); + return iova; +} + +/** + * ipa_mpm_smmu_unmap() - SMMU unmaps ring and the buffer pointer. + * @va_addr: virtual address that needs to be mapped + * @sz: size of the address to be mapped + * @dir: ipa_mpm_dma_data_direction + * @ap_cb_iova: iova for AP context bank + * + * This function SMMU unmaps both ring and the buffer pointer. + * The ring pointers will be aligned to ring size and + * the buffer pointers should be aligned to buffer size. + * + * Return: none + */ +static void ipa_mpm_smmu_unmap(dma_addr_t carved_iova, int sz, int dir, + dma_addr_t ap_cb_iova) +{ + unsigned long iova_p; + unsigned long pa_p; + u32 size_p = 0; + struct iommu_domain *ipa_smmu_domain, *pcie_smmu_domain; + struct ipa_smmu_cb_ctx *cb = &ipa_mpm_ctx->carved_smmu_cb; + int smmu_enabled = (ipa_mpm_ctx->dev_info.ipa_smmu_enabled && + ipa_mpm_ctx->dev_info.pcie_smmu_enabled) ? 1 : 0; + + if (carved_iova <= 0) { + IPA_MPM_ERR("carved_iova is zero/negative\n"); + return; + } + + if (smmu_enabled) { + ipa_smmu_domain = ipa3_get_smmu_domain(); + if (!ipa_smmu_domain) { + IPA_MPM_ERR("invalid IPA smmu domain\n"); + ipa_assert(); + } + + if (!ipa_mpm_ctx->mhi_parent_dev) { + IPA_MPM_ERR("invalid PCIE SMMU domain\n"); + ipa_assert(); + } + + IPA_SMMU_ROUND_TO_PAGE(carved_iova, carved_iova, sz, + iova_p, pa_p, size_p); + pcie_smmu_domain = iommu_get_domain_for_dev( + ipa_mpm_ctx->mhi_parent_dev); + if (pcie_smmu_domain) { + iommu_unmap(pcie_smmu_domain, iova_p, size_p); + } else { + IPA_MPM_ERR("invalid PCIE SMMU domain\n"); + ipa_assert(); + } + iommu_unmap(ipa_smmu_domain, iova_p, size_p); + + cb->next_addr -= size_p; + dma_unmap_single(ipa3_ctx->pdev, ap_cb_iova, + size_p, dir); + } else { + if (dir == DMA_TO_HIPA) + dma_unmap_single(ipa3_ctx->pdev, ap_cb_iova, + ipa3_ctx->mpm_ring_size_dl * + IPA_MPM_DESC_SIZE, dir); + else + dma_unmap_single(ipa3_ctx->pdev, ap_cb_iova, + ipa3_ctx->mpm_ring_size_ul * + IPA_MPM_DESC_SIZE, dir); + } +} + +static u32 ipa_mpm_smmu_map_doorbell(enum mhip_smmu_domain_type smmu_domain, + u32 pa_addr) +{ + /* + * Doorbells are already in PA, map these to + * PCIE/IPA doman if SMMUs are enabled. + */ + struct iommu_domain *ipa_smmu_domain, *pcie_smmu_domain; + int smmu_enabled; + unsigned long iova_p; + phys_addr_t pa_p; + u32 size_p; + int ret = 0; + int prot = IOMMU_READ | IOMMU_WRITE; + struct ipa_smmu_cb_ctx *cb = &ipa_mpm_ctx->carved_smmu_cb; + unsigned long carved_iova = roundup(cb->next_addr, IPA_MPM_PAGE_SIZE); + u32 iova = 0; + u64 offset = 0; + + /* check cache coherent */ + if (ipa_mpm_ctx->dev_info.is_cache_coherent) { + IPA_MPM_DBG(" enable cache coherent\n"); + prot |= IOMMU_CACHE; + } + + if (carved_iova >= cb->va_end) { + IPA_MPM_ERR("running out of carved_iova %lx\n", carved_iova); + ipa_assert(); + } + + smmu_enabled = (ipa_mpm_ctx->dev_info.ipa_smmu_enabled && + ipa_mpm_ctx->dev_info.pcie_smmu_enabled) ? 1 : 0; + + if (smmu_enabled) { + IPA_SMMU_ROUND_TO_PAGE(carved_iova, pa_addr, IPA_MPM_PAGE_SIZE, + iova_p, pa_p, size_p); + if (smmu_domain == MHIP_SMMU_DOMAIN_IPA) { + ipa_smmu_domain = ipa3_get_smmu_domain(); + if (!ipa_smmu_domain) { + IPA_MPM_ERR("invalid IPA smmu domain\n"); + ipa_assert(); + } + ret = ipa3_iommu_map(ipa_smmu_domain, + iova_p, pa_p, size_p, prot); + if (ret) { + IPA_MPM_ERR("IPA doorbell mapping failed\n"); + ipa_assert(); + } + offset = pa_addr - pa_p; + } else if (smmu_domain == MHIP_SMMU_DOMAIN_PCIE) { + pcie_smmu_domain = iommu_get_domain_for_dev( + ipa_mpm_ctx->mhi_parent_dev); + if (!pcie_smmu_domain) { + IPA_MPM_ERR("invalid IPA smmu domain\n"); + ipa_assert(); + } + ret = iommu_map(pcie_smmu_domain, + iova_p, pa_p, size_p, prot); + if (ret) { + IPA_MPM_ERR("PCIe doorbell mapping failed\n"); + ipa_assert(); + } + offset = pa_addr - pa_p; + } + iova = iova_p + offset; + cb->next_addr = iova_p + IPA_MPM_PAGE_SIZE; + } else { + iova = pa_addr; + } + return iova; +} + +static void ipa_mpm_smmu_unmap_doorbell(enum mhip_smmu_domain_type smmu_domain, + dma_addr_t iova) +{ + /* + * Doorbells are already in PA, map these to + * PCIE/IPA doman if SMMUs are enabled. + */ + struct iommu_domain *ipa_smmu_domain, *pcie_smmu_domain; + int smmu_enabled; + unsigned long iova_p; + phys_addr_t pa_p; + u32 size_p; + struct ipa_smmu_cb_ctx *cb = &ipa_mpm_ctx->carved_smmu_cb; + + smmu_enabled = (ipa_mpm_ctx->dev_info.ipa_smmu_enabled && + ipa_mpm_ctx->dev_info.pcie_smmu_enabled) ? 1 : 0; + + if (smmu_enabled) { + IPA_SMMU_ROUND_TO_PAGE(iova, iova, IPA_MPM_PAGE_SIZE, + iova_p, pa_p, size_p); + if (smmu_domain == MHIP_SMMU_DOMAIN_IPA) { + ipa_smmu_domain = ipa3_get_smmu_domain(); + if (ipa_smmu_domain) { + iommu_unmap(ipa_smmu_domain, iova_p, size_p); + } else { + IPA_MPM_ERR("invalid IPA smmu domain\n"); + ipa_assert(); + } + } else if (smmu_domain == MHIP_SMMU_DOMAIN_PCIE) { + pcie_smmu_domain = iommu_get_domain_for_dev( + ipa_mpm_ctx->mhi_parent_dev); + if (pcie_smmu_domain) { + iommu_unmap(pcie_smmu_domain, iova_p, size_p); + } else { + IPA_MPM_ERR("invalid PCIE smmu domain\n"); + ipa_assert(); + } + cb->next_addr -= IPA_MPM_PAGE_SIZE; + } + } +} +static int get_idx_from_id(const struct mhi_device_id *id) +{ + return (id - mhi_driver_match_table); +} + +static void get_ipa3_client(int id, + enum ipa_client_type *ul_prod, + enum ipa_client_type *dl_cons) +{ + IPA_MPM_FUNC_ENTRY(); + + if (id >= IPA_MPM_MHIP_CH_ID_MAX) { + *ul_prod = IPA_CLIENT_MAX; + *dl_cons = IPA_CLIENT_MAX; + } else { + *ul_prod = ipa_mpm_pipes[id].ul_prod.ipa_client; + *dl_cons = ipa_mpm_pipes[id].dl_cons.ipa_client; + } + IPA_MPM_FUNC_EXIT(); +} + +static int ipa_mpm_connect_mhip_gsi_pipe(enum ipa_client_type mhip_client, + int mhi_idx, struct ipa_req_chan_out_params *out_params) +{ + int ipa_ep_idx; + int res; + struct mhi_p_desc *er_ring_va, *tr_ring_va; + void *buff_va; + dma_addr_t er_carved_iova, tr_carved_iova; + dma_addr_t ap_cb_tr_iova, ap_cb_er_iova, ap_cb_buff_iova; + struct ipa_request_gsi_channel_params gsi_params; + int dir; + int i, k; + int result; + struct ipa3_ep_context *ep; + int ring_size; + + if (mhip_client == IPA_CLIENT_MAX) + goto fail_gen; + + if ((mhi_idx < IPA_MPM_MHIP_CH_ID_0) || + (mhi_idx >= IPA_MPM_MHIP_CH_ID_MAX)) + goto fail_gen; + + ipa_ep_idx = ipa_get_ep_mapping(mhip_client); + if (ipa_ep_idx == IPA_EP_NOT_ALLOCATED) { + IPA_MPM_ERR("fail to find channel EP.\n"); + goto fail_gen; + } + ep = &ipa3_ctx->ep[ipa_ep_idx]; + if (ep->valid == 1) { + IPAERR("EP %d already allocated.\n", ipa_ep_idx); + return 0; + } + + IPA_MPM_DBG("connecting client %d (ep: %d)\n", mhip_client, ipa_ep_idx); + + IPA_MPM_FUNC_ENTRY(); + + if (IPA_CLIENT_IS_PROD(mhip_client) && + (ipa3_ctx->mpm_ring_size_dl * + IPA_MPM_DESC_SIZE > PAGE_SIZE)) { + IPA_MPM_ERR("Ring Size dl / allocation mismatch\n"); + ipa_assert(); + } + + if (IPA_CLIENT_IS_PROD(mhip_client) && + (ipa3_ctx->mpm_ring_size_ul * + IPA_MPM_DESC_SIZE > PAGE_SIZE)) { + IPA_MPM_ERR("Ring Size ul / allocation mismatch\n"); + ipa_assert(); + } + /* Only ring need alignment, separate from buffer */ + er_ring_va = (struct mhi_p_desc *) get_zeroed_page(GFP_KERNEL); + + if (!er_ring_va) + goto fail_evt_alloc; + + tr_ring_va = (struct mhi_p_desc *) get_zeroed_page(GFP_KERNEL); + + if (!tr_ring_va) + goto fail_tr_alloc; + + tr_ring_va[0].re_type = MHIP_RE_NOP; + + dir = IPA_CLIENT_IS_PROD(mhip_client) ? + DMA_TO_HIPA : DMA_FROM_HIPA; + + /* allocate transfer ring elements */ + if (IPA_CLIENT_IS_PROD(mhip_client)) + ring_size = ipa3_ctx->mpm_ring_size_dl; + else + ring_size = ipa3_ctx->mpm_ring_size_ul; + for (i = 1, k = 1; i < ring_size; i++, k++) { + buff_va = kzalloc(TRE_BUFF_SIZE, GFP_KERNEL); + if (!buff_va) + goto fail_buff_alloc; + + tr_ring_va[i].buffer_ptr = + ipa_mpm_smmu_map(buff_va, TRE_BUFF_SIZE, dir, + &ap_cb_buff_iova); + + if (!tr_ring_va[i].buffer_ptr) + goto fail_smmu_map_ring; + + tr_ring_va[i].buff_len = TRE_BUFF_SIZE; + tr_ring_va[i].chain = 0; + tr_ring_va[i].ieob = 0; + tr_ring_va[i].ieot = 0; + tr_ring_va[i].bei = 0; + tr_ring_va[i].sct = 0; + tr_ring_va[i].re_type = MHIP_RE_XFER; + + if (IPA_CLIENT_IS_PROD(mhip_client)) { + ipa_mpm_ctx->md[mhi_idx].dl_prod_ring.tr_buff_va[k] = + buff_va; + ipa_mpm_ctx->md[mhi_idx].dl_prod_ring.tr_buff_c_iova[k] + = tr_ring_va[i].buffer_ptr; + ipa_mpm_ctx->md[mhi_idx].dl_prod_ring.ap_iova_buff[k] = + ap_cb_buff_iova; + } else { + ipa_mpm_ctx->md[mhi_idx].ul_prod_ring.tr_buff_va[k] = + buff_va; + ipa_mpm_ctx->md[mhi_idx].ul_prod_ring.tr_buff_c_iova[k] + = tr_ring_va[i].buffer_ptr; + ipa_mpm_ctx->md[mhi_idx].ul_prod_ring.ap_iova_buff[k] = + ap_cb_buff_iova; + } + } + + tr_carved_iova = ipa_mpm_smmu_map(tr_ring_va, PAGE_SIZE, dir, + &ap_cb_tr_iova); + if (!tr_carved_iova) + goto fail_smmu_map_ring; + + er_carved_iova = ipa_mpm_smmu_map(er_ring_va, PAGE_SIZE, dir, + &ap_cb_er_iova); + if (!er_carved_iova) + goto fail_smmu_map_ring; + + /* Store Producer channel rings */ + if (IPA_CLIENT_IS_PROD(mhip_client)) { + /* Device UL */ + ipa_mpm_ctx->md[mhi_idx].dl_prod_ring.er_va = er_ring_va; + ipa_mpm_ctx->md[mhi_idx].dl_prod_ring.tr_va = tr_ring_va; + ipa_mpm_ctx->md[mhi_idx].dl_prod_ring.er_pa = er_carved_iova; + ipa_mpm_ctx->md[mhi_idx].dl_prod_ring.tr_pa = tr_carved_iova; + ipa_mpm_ctx->md[mhi_idx].dl_prod_ring.ap_iova_tr = + ap_cb_tr_iova; + ipa_mpm_ctx->md[mhi_idx].dl_prod_ring.ap_iova_er = + ap_cb_er_iova; + } else { + /* Host UL */ + ipa_mpm_ctx->md[mhi_idx].ul_prod_ring.er_va = er_ring_va; + ipa_mpm_ctx->md[mhi_idx].ul_prod_ring.tr_va = tr_ring_va; + ipa_mpm_ctx->md[mhi_idx].ul_prod_ring.er_pa = er_carved_iova; + ipa_mpm_ctx->md[mhi_idx].ul_prod_ring.tr_pa = tr_carved_iova; + ipa_mpm_ctx->md[mhi_idx].ul_prod_ring.ap_iova_tr = + ap_cb_tr_iova; + ipa_mpm_ctx->md[mhi_idx].ul_prod_ring.ap_iova_er = + ap_cb_er_iova; + } + + memset(&gsi_params, 0, sizeof(struct ipa_request_gsi_channel_params)); + + if (IPA_CLIENT_IS_PROD(mhip_client)) + gsi_params.ipa_ep_cfg = + ipa_mpm_pipes[mhi_idx].dl_cons.ep_cfg; + else + gsi_params.ipa_ep_cfg = + ipa_mpm_pipes[mhi_idx].ul_prod.ep_cfg; + + gsi_params.client = mhip_client; + gsi_params.skip_ep_cfg = false; + + /* + * RP update address = Device channel DB address + * CLIENT_PROD -> Host DL + * CLIENT_CONS -> Host UL + */ + if (IPA_CLIENT_IS_PROD(mhip_client)) { + gsi_params.evt_ring_params.rp_update_addr = + ipa_mpm_smmu_map_doorbell( + MHIP_SMMU_DOMAIN_IPA, + ipa_mpm_ctx->md[mhi_idx].dl_cons.chan_props.device_db); + if (gsi_params.evt_ring_params.rp_update_addr == 0) + goto fail_smmu_map_db; + + ipa_mpm_ctx->md[mhi_idx].dl_cons.db_host_iova = + gsi_params.evt_ring_params.rp_update_addr; + + gsi_params.evt_ring_params.ring_base_addr = + ipa_mpm_ctx->md[mhi_idx].dl_prod_ring.tr_pa; + gsi_params.chan_params.ring_base_addr = + ipa_mpm_ctx->md[mhi_idx].dl_prod_ring.er_pa; + } else { + gsi_params.evt_ring_params.rp_update_addr = + ipa_mpm_smmu_map_doorbell( + MHIP_SMMU_DOMAIN_IPA, + ipa_mpm_ctx->md[mhi_idx].ul_prod.chan_props.device_db); + if (gsi_params.evt_ring_params.rp_update_addr == 0) + goto fail_smmu_map_db; + ipa_mpm_ctx->md[mhi_idx].ul_prod.db_host_iova = + gsi_params.evt_ring_params.rp_update_addr; + gsi_params.evt_ring_params.ring_base_addr = + ipa_mpm_ctx->md[mhi_idx].ul_prod_ring.er_pa; + gsi_params.chan_params.ring_base_addr = + ipa_mpm_ctx->md[mhi_idx].ul_prod_ring.tr_pa; + } + + /* Fill Event ring params */ + gsi_params.evt_ring_params.intf = GSI_EVT_CHTYPE_MHIP_EV; + gsi_params.evt_ring_params.intr = GSI_INTR_MSI; + gsi_params.evt_ring_params.re_size = GSI_EVT_RING_RE_SIZE_16B; + gsi_params.evt_ring_params.ring_len = + (ring_size) * GSI_EVT_RING_RE_SIZE_16B; + gsi_params.evt_ring_params.ring_base_vaddr = NULL; + gsi_params.evt_ring_params.int_modt = 0; + gsi_params.evt_ring_params.int_modc = 0; + gsi_params.evt_ring_params.intvec = 0; + gsi_params.evt_ring_params.msi_addr = 0; + gsi_params.evt_ring_params.exclusive = true; + gsi_params.evt_ring_params.err_cb = ipa_mpm_gsi_evt_ring_err_cb; + gsi_params.evt_ring_params.user_data = NULL; + + /* Evt Scratch Params */ + /* Disable the Moderation for ringing doorbells */ + gsi_params.evt_scratch.mhip.rp_mod_threshold = 1; + gsi_params.evt_scratch.mhip.rp_mod_timer = 0; + gsi_params.evt_scratch.mhip.rp_mod_counter = 0; + gsi_params.evt_scratch.mhip.rp_mod_timer_id = 0; + gsi_params.evt_scratch.mhip.rp_mod_timer_running = 0; + gsi_params.evt_scratch.mhip.fixed_buffer_sz = TRE_BUFF_SIZE; + + /* Channel Params */ + gsi_params.chan_params.prot = GSI_CHAN_PROT_MHIP; + gsi_params.chan_params.dir = IPA_CLIENT_IS_PROD(mhip_client) ? + GSI_CHAN_DIR_TO_GSI : GSI_CHAN_DIR_FROM_GSI; + /* chan_id is set in ipa3_request_gsi_channel() */ + gsi_params.chan_params.re_size = GSI_CHAN_RE_SIZE_16B; + gsi_params.chan_params.ring_len = + (ring_size) * GSI_EVT_RING_RE_SIZE_16B; + gsi_params.chan_params.ring_base_vaddr = NULL; + gsi_params.chan_params.use_db_eng = GSI_CHAN_DIRECT_MODE; + gsi_params.chan_params.max_prefetch = GSI_ONE_PREFETCH_SEG; + gsi_params.chan_params.db_in_bytes = 1; + gsi_params.chan_params.low_weight = 1; + gsi_params.chan_params.xfer_cb = NULL; + gsi_params.chan_params.err_cb = ipa_mpm_gsi_chan_err_cb; + gsi_params.chan_params.chan_user_data = NULL; + + /* Channel scratch */ + gsi_params.chan_scratch.mhip.assert_bit_40 = 0; + gsi_params.chan_scratch.mhip.host_channel = 1; + + res = ipa3_request_gsi_channel(&gsi_params, out_params); + if (res) { + IPA_MPM_ERR("failed to allocate GSI channel res=%d\n", res); + goto fail_alloc_channel; + } + + if (IPA_CLIENT_IS_CONS(mhip_client)) { + /* + * Enable HOLB timer one time after bootup/SSR. + * The HOLB timeout drops the packets on MHIP if + * there is a stall on MHIP TX pipe greater than + * configured timeout. + */ + result = ipa_mpm_start_mhip_holb_tmo(ipa_ep_idx); + if (result) { + IPA_MPM_ERR("HOLB config failed for %d, fail = %d\n", + ipa_ep_idx, result); + goto fail_alloc_channel; + } + } + + if (IPA_CLIENT_IS_PROD(mhip_client)) + ipa_mpm_change_gsi_state(mhi_idx, + IPA_MPM_MHIP_CHAN_DL, + GSI_ALLOCATED); + else + ipa_mpm_change_gsi_state(mhi_idx, + IPA_MPM_MHIP_CHAN_UL, + GSI_ALLOCATED); + result = ipa3_start_gsi_channel(ipa_ep_idx); + if (result) { + IPA_MPM_ERR("start MHIP channel %d failed\n", mhip_client); + if (IPA_CLIENT_IS_PROD(mhip_client)) + ipa_mpm_change_gsi_state(mhi_idx, + IPA_MPM_MHIP_CHAN_DL, GSI_ERR); + else + ipa_mpm_change_gsi_state(mhi_idx, + IPA_MPM_MHIP_CHAN_UL, GSI_ERR); + goto fail_start_channel; + } + if (IPA_CLIENT_IS_PROD(mhip_client)) + ipa_mpm_change_gsi_state(mhi_idx, + IPA_MPM_MHIP_CHAN_DL, GSI_STARTED); + else + ipa_mpm_change_gsi_state(mhi_idx, + IPA_MPM_MHIP_CHAN_UL, GSI_STARTED); + + /* Fill in the Device Context params */ + if (IPA_CLIENT_IS_PROD(mhip_client)) { + /* This is the DL channel :: Device -> Host */ + ipa_mpm_ctx->md[mhi_idx].dl_cons.evt_props.ev_ctx.rbase = + ipa_mpm_ctx->md[mhi_idx].dl_prod_ring.er_pa; + ipa_mpm_ctx->md[mhi_idx].dl_cons.chan_props.ch_ctx.rbase = + ipa_mpm_ctx->md[mhi_idx].dl_prod_ring.tr_pa; + } else { + ipa_mpm_ctx->md[mhi_idx].ul_prod.evt_props.ev_ctx.rbase = + ipa_mpm_ctx->md[mhi_idx].ul_prod_ring.tr_pa; + ipa_mpm_ctx->md[mhi_idx].ul_prod.chan_props.ch_ctx.rbase = + ipa_mpm_ctx->md[mhi_idx].ul_prod_ring.er_pa; + } + + IPA_MPM_FUNC_EXIT(); + + return 0; + +fail_start_channel: + ipa3_disable_data_path(ipa_ep_idx); + ipa_stop_gsi_channel(ipa_ep_idx); +fail_alloc_channel: + ipa3_release_gsi_channel(ipa_ep_idx); +fail_smmu_map_db: +fail_smmu_map_ring: +fail_tr_alloc: +fail_evt_alloc: +fail_buff_alloc: + ipa_assert(); +fail_gen: + return -EFAULT; +} + +static void ipa_mpm_clean_mhip_chan(int mhi_idx, + enum ipa_client_type mhip_client) +{ + int dir; + int i; + int ipa_ep_idx; + int result; + int ring_size; + + IPA_MPM_FUNC_ENTRY(); + + if (mhip_client == IPA_CLIENT_MAX) + return; + + if ((mhi_idx < IPA_MPM_MHIP_CH_ID_0) || + (mhi_idx >= IPA_MPM_MHIP_CH_ID_MAX)) + return; + + dir = IPA_CLIENT_IS_PROD(mhip_client) ? + DMA_TO_HIPA : DMA_FROM_HIPA; + + ipa_ep_idx = ipa_get_ep_mapping(mhip_client); + if (ipa_ep_idx == IPA_EP_NOT_ALLOCATED) { + IPA_MPM_ERR("fail to find channel EP.\n"); + return; + } + + /* For the uplink channels, enable HOLB. */ + if (IPA_CLIENT_IS_CONS(mhip_client)) + ipa3_disable_data_path(ipa_ep_idx); + + /* Release channel */ + result = ipa_stop_gsi_channel(ipa_ep_idx); + if (result) { + IPA_MPM_ERR("Stop channel for MHIP_Client = %d failed\n", + mhip_client); + goto fail_chan; + } + result = ipa3_reset_gsi_channel(ipa_ep_idx); + if (result) { + IPA_MPM_ERR("Reset channel for MHIP_Client = %d failed\n", + mhip_client); + goto fail_chan; + } + result = ipa3_reset_gsi_event_ring(ipa_ep_idx); + if (result) { + IPA_MPM_ERR("Reset ev ring for MHIP_Client = %d failed\n", + mhip_client); + goto fail_chan; + } + result = ipa3_release_gsi_channel(ipa_ep_idx); + if (result) { + IPA_MPM_ERR("Release tr ring for MHIP_Client = %d failed\n", + mhip_client); + if (IPA_CLIENT_IS_PROD(mhip_client)) + ipa_mpm_change_gsi_state(mhi_idx, + IPA_MPM_MHIP_CHAN_DL, GSI_ERR); + else + ipa_mpm_change_gsi_state(mhi_idx, + IPA_MPM_MHIP_CHAN_UL, GSI_ERR); + goto fail_chan; + } + + if (IPA_CLIENT_IS_PROD(mhip_client)) + ipa_mpm_change_gsi_state(mhi_idx, + IPA_MPM_MHIP_CHAN_DL, GSI_INIT); + else + ipa_mpm_change_gsi_state(mhi_idx, + IPA_MPM_MHIP_CHAN_UL, GSI_INIT); + + memset(&ipa3_ctx->ep[ipa_ep_idx], 0, sizeof(struct ipa3_ep_context)); + + /* Unmap Doorbells */ + if (IPA_CLIENT_IS_PROD(mhip_client)) { + ipa_mpm_smmu_unmap_doorbell(MHIP_SMMU_DOMAIN_PCIE, + ipa_mpm_ctx->md[mhi_idx].dl_cons.db_device_iova); + + ipa_mpm_smmu_unmap_doorbell(MHIP_SMMU_DOMAIN_IPA, + ipa_mpm_ctx->md[mhi_idx].dl_cons.db_host_iova); + + ipa_mpm_ctx->md[mhi_idx].dl_cons.db_host_iova = 0; + ipa_mpm_ctx->md[mhi_idx].dl_cons.db_device_iova = 0; + + } else { + ipa_mpm_smmu_unmap_doorbell(MHIP_SMMU_DOMAIN_PCIE, + ipa_mpm_ctx->md[mhi_idx].ul_prod.db_device_iova); + + ipa_mpm_smmu_unmap_doorbell(MHIP_SMMU_DOMAIN_IPA, + ipa_mpm_ctx->md[mhi_idx].ul_prod.db_host_iova); + + ipa_mpm_ctx->md[mhi_idx].ul_prod.db_host_iova = 0; + ipa_mpm_ctx->md[mhi_idx].ul_prod.db_device_iova = 0; + } + + /* deallocate/Unmap transfer ring buffers */ + if (IPA_CLIENT_IS_PROD(mhip_client)) + ring_size = ipa3_ctx->mpm_ring_size_dl_cache; + else + ring_size = ipa3_ctx->mpm_ring_size_ul_cache; + for (i = 1; i < ring_size; i++) { + if (IPA_CLIENT_IS_PROD(mhip_client)) { + ipa_mpm_smmu_unmap( + (dma_addr_t) + ipa_mpm_ctx->md[mhi_idx].dl_prod_ring.tr_buff_c_iova[i], + TRE_BUFF_SIZE, dir, + ipa_mpm_ctx->md[mhi_idx].dl_prod_ring.ap_iova_buff[i]); + ipa_mpm_ctx->md[mhi_idx].dl_prod_ring.tr_buff_c_iova[i] + = 0; + kfree( + ipa_mpm_ctx->md[mhi_idx].dl_prod_ring.tr_buff_va[i]); + ipa_mpm_ctx->md[mhi_idx].dl_prod_ring.tr_buff_va[i] + = NULL; + ipa_mpm_ctx->md[mhi_idx].dl_prod_ring.ap_iova_buff[i] + = 0; + ipa_mpm_ctx->md[mhi_idx].dl_prod_ring.tr_buff_c_iova[i] + = 0; + } else { + ipa_mpm_smmu_unmap( + (dma_addr_t) + ipa_mpm_ctx->md[mhi_idx].ul_prod_ring.tr_buff_c_iova[i], + TRE_BUFF_SIZE, dir, + ipa_mpm_ctx->md[mhi_idx].ul_prod_ring.ap_iova_buff[i] + ); + ipa_mpm_ctx->md[mhi_idx].ul_prod_ring.tr_buff_c_iova[i] + = 0; + kfree( + ipa_mpm_ctx->md[mhi_idx].ul_prod_ring.tr_buff_va[i]); + ipa_mpm_ctx->md[mhi_idx].ul_prod_ring.tr_buff_va[i] + = NULL; + ipa_mpm_ctx->md[mhi_idx].ul_prod_ring.ap_iova_buff[i] + = 0; + ipa_mpm_ctx->md[mhi_idx].ul_prod_ring.tr_buff_c_iova[i] + = 0; + } + } + + /* deallocate/Unmap rings */ + if (IPA_CLIENT_IS_PROD(mhip_client)) { + ipa_mpm_smmu_unmap( + ipa_mpm_ctx->md[mhi_idx].dl_prod_ring.er_pa, + IPA_MPM_PAGE_SIZE, dir, + ipa_mpm_ctx->md[mhi_idx].dl_prod_ring.ap_iova_er); + + ipa_mpm_smmu_unmap( + ipa_mpm_ctx->md[mhi_idx].dl_prod_ring.tr_pa, + IPA_MPM_PAGE_SIZE, dir, + ipa_mpm_ctx->md[mhi_idx].dl_prod_ring.ap_iova_tr); + + if (ipa_mpm_ctx->md[mhi_idx].dl_prod_ring.er_va) { + free_page((unsigned long) + ipa_mpm_ctx->md[mhi_idx].dl_prod_ring.er_va); + ipa_mpm_ctx->md[mhi_idx].dl_prod_ring.er_va = NULL; + } + + if (ipa_mpm_ctx->md[mhi_idx].dl_prod_ring.tr_va) { + free_page((unsigned long) + ipa_mpm_ctx->md[mhi_idx].dl_prod_ring.tr_va); + ipa_mpm_ctx->md[mhi_idx].dl_prod_ring.tr_va = NULL; + } + + ipa_mpm_ctx->md[mhi_idx].dl_prod_ring.ap_iova_er = 0; + ipa_mpm_ctx->md[mhi_idx].dl_prod_ring.ap_iova_tr = 0; + } else { + ipa_mpm_smmu_unmap( + ipa_mpm_ctx->md[mhi_idx].ul_prod_ring.tr_pa, + IPA_MPM_PAGE_SIZE, dir, + ipa_mpm_ctx->md[mhi_idx].dl_prod_ring.ap_iova_tr); + ipa_mpm_smmu_unmap( + ipa_mpm_ctx->md[mhi_idx].ul_prod_ring.er_pa, + IPA_MPM_PAGE_SIZE, dir, + ipa_mpm_ctx->md[mhi_idx].ul_prod_ring.ap_iova_er); + + ipa_mpm_ctx->md[mhi_idx].ul_prod_ring.tr_pa = 0; + ipa_mpm_ctx->md[mhi_idx].ul_prod_ring.er_pa = 0; + + if (ipa_mpm_ctx->md[mhi_idx].ul_prod_ring.er_va) { + free_page((unsigned long) + ipa_mpm_ctx->md[mhi_idx].ul_prod_ring.er_va); + ipa_mpm_ctx->md[mhi_idx].ul_prod_ring.er_va = NULL; + } + + if (ipa_mpm_ctx->md[mhi_idx].ul_prod_ring.tr_va) { + free_page((unsigned long) + ipa_mpm_ctx->md[mhi_idx].ul_prod_ring.tr_va); + ipa_mpm_ctx->md[mhi_idx].ul_prod_ring.tr_va = NULL; + } + + ipa_mpm_ctx->md[mhi_idx].ul_prod_ring.ap_iova_er = 0; + ipa_mpm_ctx->md[mhi_idx].ul_prod_ring.ap_iova_tr = 0; + } + + IPA_MPM_FUNC_EXIT(); + return; +fail_chan: + ipa_assert(); +} + +/* round addresses for closest page per SMMU requirements */ +static inline void ipa_mpm_smmu_round_to_page(uint64_t iova, uint64_t pa, + uint64_t size, unsigned long *iova_p, phys_addr_t *pa_p, u32 *size_p) +{ + *iova_p = rounddown(iova, PAGE_SIZE); + *pa_p = rounddown(pa, PAGE_SIZE); + *size_p = roundup(size + pa - *pa_p, PAGE_SIZE); +} + + +static int __ipa_mpm_configure_mhi_device(struct ipa_mpm_channel *ch, + int mhi_idx, int dir) +{ + struct mhi_buf ch_config[2]; + int ret; + + IPA_MPM_FUNC_ENTRY(); + + if (ch == NULL) { + IPA_MPM_ERR("ch config is NULL\n"); + return -EINVAL; + } + + /* Populate CCA */ + ch_config[0].buf = &ch->chan_props.ch_ctx; + ch_config[0].len = sizeof(ch->chan_props.ch_ctx); + ch_config[0].name = "CCA"; + + /* populate ECA */ + ch_config[1].buf = &ch->evt_props.ev_ctx; + ch_config[1].len = sizeof(ch->evt_props.ev_ctx); + ch_config[1].name = "ECA"; + + IPA_MPM_DBG("Configuring MHI PRIME device for mhi_idx %d\n", mhi_idx); + + ret = mhi_device_configure(ipa_mpm_ctx->md[mhi_idx].mhi_dev, dir, + ch_config, 2); + if (ret) { + IPA_MPM_ERR("mhi_device_configure failed\n"); + return -EINVAL; + } + IPA_MPM_FUNC_EXIT(); + return 0; +} + +static void ipa_mpm_mhip_shutdown(int mhip_idx) +{ + enum ipa_client_type ul_prod_chan, dl_cons_chan; + + IPA_MPM_FUNC_ENTRY(); + + get_ipa3_client(mhip_idx, &ul_prod_chan, &dl_cons_chan); + + if (mhip_idx != IPA_MPM_MHIP_CH_ID_2) + /* For DPL, stop only DL channel */ + ipa_mpm_clean_mhip_chan(mhip_idx, ul_prod_chan); + + ipa_mpm_clean_mhip_chan(mhip_idx, dl_cons_chan); + + if (!ipa_mpm_ctx->md[mhip_idx].in_lpm) { + ipa_mpm_vote_unvote_ipa_clk(CLK_OFF, mhip_idx); + /* while in modem shutdown scenarios such as SSR, no explicit + * PCIe vote is needed. + */ + ipa_mpm_ctx->md[mhip_idx].in_lpm = true; + } + mutex_lock(&ipa_mpm_ctx->md[mhip_idx].mhi_mutex); + ipa_mpm_ctx->md[mhip_idx].mhi_dev = NULL; + mutex_unlock(&ipa_mpm_ctx->md[mhip_idx].mhi_mutex); + IPA_MPM_FUNC_EXIT(); +} + +/** + * @ipa_mpm_vote_unvote_pcie_clk - Vote/Unvote PCIe Clock per probe_id + * Returns if success or failure. + * @ipa_mpm_clk_vote_type - Vote or Unvote for PCIe Clock + * @probe_id - MHI probe_id per client. + * @is_force - Forcebly casts vote - should be true only in probe. + * @is_acted - Output param - This indicates the clk is actually voted or not + * The flag output is checked only when we vote for clocks. + * Return value: PCIe clock voting is success or failure. + */ +static int ipa_mpm_vote_unvote_pcie_clk(enum ipa_mpm_clk_vote_type vote, + int probe_id, + bool is_force, + bool *is_acted) +{ + int result = 0; + + if (probe_id >= IPA_MPM_MHIP_CH_ID_MAX) { + IPA_MPM_ERR("probe_id not found\n"); + return -EINVAL; + } + + if (vote > CLK_OFF) { + IPA_MPM_ERR("Invalid vote\n"); + return -EINVAL; + } + + if (!is_acted) { + IPA_MPM_ERR("Invalid clk_vote ptr\n"); + return -EFAULT; + } + + mutex_lock(&ipa_mpm_ctx->md[probe_id].mhi_mutex); + if (ipa_mpm_ctx->md[probe_id].mhi_dev == NULL) { + IPA_MPM_ERR("MHI not initialized yet\n"); + *is_acted = false; + mutex_unlock(&ipa_mpm_ctx->md[probe_id].mhi_mutex); + return 0; + } + + if (!ipa_mpm_ctx->md[probe_id].init_complete && + !is_force) { + /* + * SSR might be in progress, dont have to vote/unvote for + * IPA clocks as it will be taken care in remove_cb/subsequent + * probe. + */ + IPA_MPM_DBG("SSR in progress, return\n"); + *is_acted = false; + mutex_unlock(&ipa_mpm_ctx->md[probe_id].mhi_mutex); + return 0; + } + mutex_unlock(&ipa_mpm_ctx->md[probe_id].mhi_mutex); + + IPA_MPM_DBG("PCIe clock vote/unvote = %d probe_id = %d clk_cnt = %d\n", + vote, probe_id, + atomic_read(&ipa_mpm_ctx->md[probe_id].clk_cnt.pcie_clk_cnt)); + + if (vote == CLK_ON) { + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) + pm_runtime_get_sync(ipa_mpm_ctx->mhi_parent_dev); + #else + result = mhi_device_get_sync( + ipa_mpm_ctx->md[probe_id].mhi_dev, + MHI_VOTE_BUS | MHI_VOTE_DEVICE); + #endif + if (result) { + IPA_MPM_ERR("mhi_sync_get failed for probe_id %d\n", + result, probe_id); + *is_acted = false; + return result; + } + + IPA_MPM_DBG("probe_id %d PCIE clock now ON\n", probe_id); + atomic_inc(&ipa_mpm_ctx->md[probe_id].clk_cnt.pcie_clk_cnt); + atomic_inc(&ipa_mpm_ctx->pcie_clk_total_cnt); + } else { + if ((atomic_read( + &ipa_mpm_ctx->md[probe_id].clk_cnt.pcie_clk_cnt) + == 0)) { + IPA_MPM_ERR("probe_id %d PCIE clock already devoted\n", + probe_id); + *is_acted = true; + return 0; + } + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) + pm_runtime_put(ipa_mpm_ctx->mhi_parent_dev); + #else + mhi_device_put(ipa_mpm_ctx->md[probe_id].mhi_dev, + MHI_VOTE_BUS | MHI_VOTE_DEVICE); + #endif + IPA_MPM_DBG("probe_id %d PCIE clock off\n", probe_id); + atomic_dec(&ipa_mpm_ctx->md[probe_id].clk_cnt.pcie_clk_cnt); + atomic_dec(&ipa_mpm_ctx->pcie_clk_total_cnt); + } + *is_acted = true; + return result; +} + +/* + * Turning on/OFF IPA Clock is done only once- for all clients + */ +static void ipa_mpm_vote_unvote_ipa_clk(enum ipa_mpm_clk_vote_type vote, + int probe_id) +{ + if (vote > CLK_OFF) + return; + + IPA_MPM_DBG("IPA clock vote/unvote = %d probe_id = %d clk_cnt = %d\n", + vote, probe_id, + atomic_read(&ipa_mpm_ctx->md[probe_id].clk_cnt.ipa_clk_cnt)); + + if (vote == CLK_ON) { + IPA_ACTIVE_CLIENTS_INC_SPECIAL(ipa_mpm_mhip_chan_str[probe_id]); + IPA_MPM_DBG("IPA clock now ON for probe_id %d\n", probe_id); + atomic_inc(&ipa_mpm_ctx->md[probe_id].clk_cnt.ipa_clk_cnt); + atomic_inc(&ipa_mpm_ctx->ipa_clk_total_cnt); + } else { + if ((atomic_read + (&ipa_mpm_ctx->md[probe_id].clk_cnt.ipa_clk_cnt) + == 0)) { + IPA_MPM_ERR("probe_id %d IPA clock count < 0\n", + probe_id); + return; + } + IPA_ACTIVE_CLIENTS_DEC_SPECIAL(ipa_mpm_mhip_chan_str[probe_id]); + IPA_MPM_DBG("probe_id %d IPA clock off\n", probe_id); + atomic_dec(&ipa_mpm_ctx->md[probe_id].clk_cnt.ipa_clk_cnt); + atomic_dec(&ipa_mpm_ctx->ipa_clk_total_cnt); + } +} + +/** + * @ipa_mpm_start_stop_remote_mhip_chan - Start/Stop Remote device side MHIP + * channels. + * @ipa_mpm_clk_vote_type - Vote or Unvote for PCIe Clock + * @probe_id - MHI probe_id per client. + * @ipa_mpm_start_stop_type - Start/Stop remote channels. + * @is_force - Forcebly casts remote channels to be started/stopped. + * should be true only in probe. + * Return value: 0 if success or error value. + */ +static int ipa_mpm_start_stop_remote_mhip_chan( + int probe_id, + enum ipa_mpm_start_stop_type start_stop, + bool is_force) +{ + int ret = 0; + struct mhi_device *mhi_dev = ipa_mpm_ctx->md[probe_id].mhi_dev; + + /* Sanity check to make sure Remote channels can be started. + * If probe in progress, mhi_prepare_for_transfer will start + * the remote channels so no need to start it from here. + */ + mutex_lock(&ipa_mpm_ctx->md[probe_id].mhi_mutex); + if (!ipa_mpm_ctx->md[probe_id].init_complete && !is_force) { + IPA_MPM_ERR("MHI not initialized yet, probe in progress\n"); + mutex_unlock(&ipa_mpm_ctx->md[probe_id].mhi_mutex); + return ret; + } + + /* For error state, expect modem SSR to recover from error */ + if (ipa_mpm_ctx->md[probe_id].remote_state == MPM_MHIP_REMOTE_ERR) { + IPA_MPM_ERR("Remote channels in err state for %d\n", probe_id); + mutex_unlock(&ipa_mpm_ctx->md[probe_id].mhi_mutex); + return -EFAULT; + } + mutex_unlock(&ipa_mpm_ctx->md[probe_id].mhi_mutex); + + if (start_stop == MPM_MHIP_START) { + if (ipa_mpm_ctx->md[probe_id].remote_state == + MPM_MHIP_REMOTE_START) { + IPA_MPM_DBG("Remote channel already started for %d\n", + probe_id); + } else { +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) + ret = mhi_start_transfer(mhi_dev); +#else + ret = mhi_resume_transfer(mhi_dev); +#endif + mutex_lock(&ipa_mpm_ctx->md[probe_id].mhi_mutex); + if (ret) + ipa_mpm_ctx->md[probe_id].remote_state = + MPM_MHIP_REMOTE_ERR; + else + ipa_mpm_ctx->md[probe_id].remote_state = + MPM_MHIP_REMOTE_START; + mutex_unlock(&ipa_mpm_ctx->md[probe_id].mhi_mutex); + } + } else { + if (ipa_mpm_ctx->md[probe_id].remote_state == + MPM_MHIP_REMOTE_STOP) { + IPA_MPM_DBG("Remote channel already stopped for %d\n", + probe_id); + } else { +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) + ret = mhi_stop_transfer(mhi_dev); +#else + ret = mhi_pause_transfer(mhi_dev); +#endif + mutex_lock(&ipa_mpm_ctx->md[probe_id].mhi_mutex); + if (ret) + ipa_mpm_ctx->md[probe_id].remote_state = + MPM_MHIP_REMOTE_ERR; + else + ipa_mpm_ctx->md[probe_id].remote_state = + MPM_MHIP_REMOTE_STOP; + mutex_unlock(&ipa_mpm_ctx->md[probe_id].mhi_mutex); + } + } + return ret; +} + +static enum mhip_status_type ipa_mpm_start_stop_mhip_chan( + enum ipa_mpm_mhip_chan mhip_chan, + int probe_id, + enum ipa_mpm_start_stop_type start_stop) +{ + int ipa_ep_idx = IPA_EP_NOT_ALLOCATED; + struct ipa3_ep_context *ep; + bool is_start; + enum ipa_client_type ul_chan, dl_chan; + enum gsi_status gsi_res = GSI_STATUS_SUCCESS; + int result; + + IPA_MPM_FUNC_ENTRY(); + + if (mhip_chan > IPA_MPM_MHIP_CHAN_BOTH) { + IPA_MPM_ERR("MHI not initialized yet\n"); + return MHIP_STATUS_FAIL; + } + + if (probe_id >= IPA_MPM_MHIP_CH_ID_MAX) { + IPA_MPM_ERR("MHI not initialized yet\n"); + return MHIP_STATUS_FAIL; + } + + get_ipa3_client(probe_id, &ul_chan, &dl_chan); + + if (mhip_chan == IPA_MPM_MHIP_CHAN_UL) { + ipa_ep_idx = ipa_get_ep_mapping(ul_chan); + } else if (mhip_chan == IPA_MPM_MHIP_CHAN_DL) { + ipa_ep_idx = ipa_get_ep_mapping(dl_chan); + } else if (mhip_chan == IPA_MPM_MHIP_CHAN_BOTH) { + ipa_ep_idx = ipa_get_ep_mapping(ul_chan); + ipa_ep_idx = ipa_get_ep_mapping(dl_chan); + } + + if (ipa_ep_idx == IPA_EP_NOT_ALLOCATED) { + IPA_MPM_ERR("fail to get EP# for idx %d\n", ipa_ep_idx); + return MHIP_STATUS_EP_NOT_FOUND; + } + + mutex_lock(&ipa_mpm_ctx->md[probe_id].mhi_mutex); + if (!ipa_mpm_ctx->md[probe_id].init_complete) { + IPA_MPM_ERR("MHIP probe %d not initialized\n", probe_id); + mutex_unlock(&ipa_mpm_ctx->md[probe_id].mhi_mutex); + return MHIP_STATUS_EP_NOT_READY; + } + mutex_unlock(&ipa_mpm_ctx->md[probe_id].mhi_mutex); + + ep = &ipa3_ctx->ep[ipa_ep_idx]; + + if (mhip_chan == IPA_MPM_MHIP_CHAN_UL) { + IPA_MPM_DBG("current GSI state = %d, action = %d\n", + ipa_mpm_ctx->md[probe_id].ul_prod.gsi_state, + start_stop); + if (ipa_mpm_ctx->md[probe_id].ul_prod.gsi_state < + GSI_ALLOCATED) { + IPA_MPM_ERR("GSI chan is not allocated yet\n"); + return MHIP_STATUS_EP_NOT_READY; + } + } else if (mhip_chan == IPA_MPM_MHIP_CHAN_DL) { + IPA_MPM_DBG("current GSI state = %d, action = %d\n", + ipa_mpm_ctx->md[probe_id].dl_cons.gsi_state, + start_stop); + if (ipa_mpm_ctx->md[probe_id].dl_cons.gsi_state < + GSI_ALLOCATED) { + IPA_MPM_ERR("GSI chan is not allocated yet\n"); + return MHIP_STATUS_EP_NOT_READY; + } + } + + is_start = (start_stop == MPM_MHIP_START) ? true : false; + + if (is_start) { + if (mhip_chan == IPA_MPM_MHIP_CHAN_UL) { + if (ipa_mpm_ctx->md[probe_id].ul_prod.gsi_state == + GSI_STARTED) { + IPA_MPM_ERR("GSI chan is already started\n"); + return MHIP_STATUS_NO_OP; + } + } + + if (mhip_chan == IPA_MPM_MHIP_CHAN_DL) { + if (ipa_mpm_ctx->md[probe_id].dl_cons.gsi_state == + GSI_STARTED) { + IPA_MPM_ERR("GSI chan is already started\n"); + return MHIP_STATUS_NO_OP; + } + } + /* Start GSI channel */ + gsi_res = ipa3_start_gsi_channel(ipa_ep_idx); + if (gsi_res != GSI_STATUS_SUCCESS) { + IPA_MPM_ERR("Error starting channel: err = %d\n", + gsi_res); + goto gsi_chan_fail; + } else { + ipa_mpm_change_gsi_state(probe_id, mhip_chan, + GSI_STARTED); + } + } else { + if (mhip_chan == IPA_MPM_MHIP_CHAN_UL) { + if (ipa_mpm_ctx->md[probe_id].ul_prod.gsi_state == + GSI_STOPPED) { + IPA_MPM_ERR("GSI chan is already stopped\n"); + return MHIP_STATUS_NO_OP; + } else if (ipa_mpm_ctx->md[probe_id].ul_prod.gsi_state + != GSI_STARTED) { + IPA_MPM_ERR("GSI chan isn't already started\n"); + return MHIP_STATUS_NO_OP; + } + } + + if (mhip_chan == IPA_MPM_MHIP_CHAN_DL) { + if (ipa_mpm_ctx->md[probe_id].dl_cons.gsi_state == + GSI_STOPPED) { + IPA_MPM_ERR("GSI chan is already stopped\n"); + return MHIP_STATUS_NO_OP; + } else if (ipa_mpm_ctx->md[probe_id].dl_cons.gsi_state + != GSI_STARTED) { + IPA_MPM_ERR("GSI chan isn't already started\n"); + return MHIP_STATUS_NO_OP; + } + } + + if (mhip_chan == IPA_MPM_MHIP_CHAN_UL) { + /* First Stop UL GSI channel before unvote PCIe clock */ + result = ipa_stop_gsi_channel(ipa_ep_idx); + + if (result) { + IPA_MPM_ERR("UL chan stop failed\n"); + goto gsi_chan_fail; + } else { + ipa_mpm_change_gsi_state(probe_id, mhip_chan, + GSI_STOPPED); + } + } + + if (mhip_chan == IPA_MPM_MHIP_CHAN_DL) { + result = ipa_stop_gsi_channel(ipa_ep_idx); + if (result) { + IPA_MPM_ERR("Fail to stop DL channel\n"); + goto gsi_chan_fail; + } else { + ipa_mpm_change_gsi_state(probe_id, mhip_chan, + GSI_STOPPED); + } + } + } + IPA_MPM_FUNC_EXIT(); + + return MHIP_STATUS_SUCCESS; +gsi_chan_fail: + ipa3_disable_data_path(ipa_ep_idx); + ipa_mpm_change_gsi_state(probe_id, mhip_chan, GSI_ERR); + ipa_assert(); + return MHIP_STATUS_FAIL; +} + +int ipa_mpm_notify_wan_state(struct wan_ioctl_notify_wan_state *state) +{ + int probe_id = IPA_MPM_MHIP_CH_ID_MAX; + int i; + static enum mhip_status_type status; + int ret = 0; + enum ipa_mpm_mhip_client_type mhip_client = IPA_MPM_MHIP_TETH; + bool is_acted = true; + const struct ipa_gsi_ep_config *ep_cfg; + uint32_t flow_ctrl_mask = 0; + + if (!state) + return -EPERM; + + if (!ipa3_is_mhip_offload_enabled()) + return -EPERM; + + for (i = 0; i < IPA_MPM_MHIP_CH_ID_MAX; i++) { + if (ipa_mpm_pipes[i].mhip_client == mhip_client) { + probe_id = i; + break; + } + } + + if (probe_id == IPA_MPM_MHIP_CH_ID_MAX) { + IPA_MPM_ERR("Unknown probe_id\n"); + return -EPERM; + } + + IPA_MPM_DBG("WAN backhaul available for probe_id = %d\n", probe_id); + + if (state->up) { + /* Start UL MHIP channel for offloading tethering connection */ + ret = ipa_mpm_vote_unvote_pcie_clk(CLK_ON, probe_id, + false, &is_acted); + if (ret) { + IPA_MPM_ERR("Err %d cloking on PCIe clk %d\n", ret); + return ret; + } + + /* + * Make sure to start Device side channels before + * starting Host side UL channels. This is to make + * sure device side access host side only after + * Host IPA gets voted. + */ + ret = ipa_mpm_start_stop_remote_mhip_chan(probe_id, + MPM_MHIP_START, + false); + if (ret) { + /* + * This can fail only when modem is in SSR state. + * Eventually there would be a remove callback, + * so return a failure. + */ + IPA_MPM_ERR("MHIP remote chan start fail = %d\n", ret); + + if (is_acted) + ipa_mpm_vote_unvote_pcie_clk(CLK_OFF, + probe_id, + false, + &is_acted); + + return ret; + } + IPA_MPM_DBG("MHIP remote channels are started\n"); + + /* + * Update flow control monitoring end point info. + * This info will be used to set delay on the end points upon + * hitting RED water mark. + */ + ep_cfg = ipa_get_gsi_ep_info(IPA_CLIENT_WLAN2_PROD); + + if (!ep_cfg) + IPA_MPM_ERR("ep = %d not allocated yet\n", + IPA_CLIENT_WLAN2_PROD); + else + flow_ctrl_mask |= 1 << (ep_cfg->ipa_gsi_chan_num); + + ep_cfg = ipa_get_gsi_ep_info(IPA_CLIENT_USB_PROD); + + if (!ep_cfg) + IPA_MPM_ERR("ep = %d not allocated yet\n", + IPA_CLIENT_USB_PROD); + else + flow_ctrl_mask |= 1 << (ep_cfg->ipa_gsi_chan_num); + + atomic_set(&ipa_mpm_ctx->flow_ctrl_mask, flow_ctrl_mask); + + ret = ipa3_uc_send_update_flow_control(flow_ctrl_mask, + IPA_MPM_FLOW_CTRL_ADD); + + if (ret) + IPA_MPM_ERR("Err = %d setting uc flow control\n", ret); + + status = ipa_mpm_start_stop_mhip_chan( + IPA_MPM_MHIP_CHAN_UL, probe_id, MPM_MHIP_START); + switch (status) { + case MHIP_STATUS_SUCCESS: + ipa_mpm_ctx->md[probe_id].teth_state = + IPA_MPM_TETH_CONNECTED; + /* Register for BW indication from Q6 */ + if (!ipa3_qmi_reg_dereg_for_bw(true)) + IPA_MPM_ERR( + "Failed rgstring for QMIBW Ind, might be SSR"); + break; + case MHIP_STATUS_EP_NOT_READY: + case MHIP_STATUS_NO_OP: + IPA_MPM_DBG("UL chan already start, status = %d\n", + status); + if (is_acted) { + return ipa_mpm_vote_unvote_pcie_clk(CLK_OFF, + probe_id, + false, + &is_acted); + } + break; + case MHIP_STATUS_FAIL: + case MHIP_STATUS_BAD_STATE: + case MHIP_STATUS_EP_NOT_FOUND: + IPA_MPM_ERR("UL chan start err =%d\n", status); + if (is_acted) + ipa_mpm_vote_unvote_pcie_clk(CLK_OFF, probe_id, + false, &is_acted); + ipa_assert(); + return -EFAULT; + default: + IPA_MPM_ERR("Err not found\n"); + if (is_acted) + ipa_mpm_vote_unvote_pcie_clk(CLK_OFF, probe_id, + false, &is_acted); + ret = -EFAULT; + break; + } + ipa_mpm_ctx->md[probe_id].mhip_client = mhip_client; + } else { + /* + * Update flow control monitoring end point info. + * This info will be used to reset delay on the end points. + */ + flow_ctrl_mask = + atomic_read(&ipa_mpm_ctx->flow_ctrl_mask); + + ret = ipa3_uc_send_update_flow_control(flow_ctrl_mask, + IPA_MPM_FLOW_CTRL_DELETE); + flow_ctrl_mask = 0; + atomic_set(&ipa_mpm_ctx->flow_ctrl_mask, 0); + + if (ret) { + IPA_MPM_ERR("Err = %d resetting uc flow control\n", + ret); + ipa_assert(); + } + + /* De-register for BW indication from Q6*/ + if (atomic_read(&ipa_mpm_ctx->active_teth_count) >= 1) { + if (!ipa3_qmi_reg_dereg_for_bw(false)) + IPA_MPM_DBG( + "Failed De-rgstrng QMI BW Indctn,might be SSR"); + } else { + IPA_MPM_ERR( + "Active teth count is %d", + atomic_read(&ipa_mpm_ctx->active_teth_count)); + } + + /* + * Make sure to stop Device side channels before + * stopping Host side UL channels. This is to make + * sure device side doesn't access host IPA after + * Host IPA gets devoted. + */ + ret = ipa_mpm_start_stop_remote_mhip_chan(probe_id, + MPM_MHIP_STOP, + false); + if (ret) { + /* + * This can fail only when modem is in SSR state. + * Eventually there would be a remove callback, + * so return a failure. + */ + IPA_MPM_ERR("MHIP remote chan stop fail = %d\n", ret); + return ret; + } + IPA_MPM_DBG("MHIP remote channels are stopped\n"); + + status = ipa_mpm_start_stop_mhip_chan( + IPA_MPM_MHIP_CHAN_UL, probe_id, + MPM_MHIP_STOP); + switch (status) { + case MHIP_STATUS_SUCCESS: + ipa_mpm_change_teth_state(probe_id, IPA_MPM_TETH_INIT); + break; + case MHIP_STATUS_NO_OP: + case MHIP_STATUS_EP_NOT_READY: + IPA_MPM_DBG("UL chan already stop, status = %d\n", + status); + break; + case MHIP_STATUS_FAIL: + case MHIP_STATUS_BAD_STATE: + case MHIP_STATUS_EP_NOT_FOUND: + IPA_MPM_ERR("UL chan cant be stopped err =%d\n", + status); + ipa_assert(); + return -EFAULT; + default: + IPA_MPM_ERR("Err not found\n"); + return -EFAULT; + } + /* Stop UL MHIP channel for offloading tethering connection */ + ret = ipa_mpm_vote_unvote_pcie_clk(CLK_OFF, probe_id, + false, &is_acted); + + if (ret) { + IPA_MPM_ERR("Error cloking off PCIe clk, err = %d\n", + ret); + return ret; + } + ipa_mpm_ctx->md[probe_id].mhip_client = IPA_MPM_MHIP_NONE; + } + return ret; +} + +static void ipa_mpm_change_gsi_state(int probe_id, + enum ipa_mpm_mhip_chan mhip_chan, + enum ipa_mpm_gsi_state next_state) +{ + + if (probe_id >= IPA_MPM_MHIP_CH_ID_MAX) + return; + + if (mhip_chan == IPA_MPM_MHIP_CHAN_UL) { + mutex_lock(&ipa_mpm_ctx->md[probe_id].mutex); + ipa_mpm_ctx->md[probe_id].ul_prod.gsi_state = next_state; + IPA_MPM_DBG("GSI next_state = %d\n", + ipa_mpm_ctx->md[probe_id].ul_prod.gsi_state); + mutex_unlock(&ipa_mpm_ctx->md[probe_id].mutex); + } + + if (mhip_chan == IPA_MPM_MHIP_CHAN_DL) { + mutex_lock(&ipa_mpm_ctx->md[probe_id].mutex); + ipa_mpm_ctx->md[probe_id].dl_cons.gsi_state = next_state; + IPA_MPM_DBG("GSI next_state = %d\n", + ipa_mpm_ctx->md[probe_id].dl_cons.gsi_state); + mutex_unlock(&ipa_mpm_ctx->md[probe_id].mutex); + } +} + +static void ipa_mpm_change_teth_state(int probe_id, + enum ipa_mpm_teth_state next_state) +{ + enum ipa_mpm_teth_state curr_state; + + if (probe_id >= IPA_MPM_MHIP_CH_ID_MAX) { + IPA_MPM_ERR("Unknown probe_id\n"); + return; + } + + curr_state = ipa_mpm_ctx->md[probe_id].teth_state; + + IPA_MPM_DBG("curr_state = %d, ip_state = %d mhip_s\n", + curr_state, next_state); + + switch (curr_state) { + case IPA_MPM_TETH_INIT: + if (next_state == IPA_MPM_TETH_CONNECTED) + next_state = IPA_MPM_TETH_INPROGRESS; + break; + case IPA_MPM_TETH_INPROGRESS: + break; + case IPA_MPM_TETH_CONNECTED: + break; + default: + IPA_MPM_ERR("No change in state\n"); + break; + } + + ipa_mpm_ctx->md[probe_id].teth_state = next_state; + IPA_MPM_DBG("next_state = %d\n", next_state); +} + +static void ipa_mpm_read_channel(enum ipa_client_type chan) +{ + struct gsi_chan_info chan_info; + int ipa_ep_idx; + struct ipa3_ep_context *ep; + int res; + + ipa_ep_idx = ipa_get_ep_mapping(chan); + + if (ipa_ep_idx == IPA_EP_NOT_ALLOCATED) { + IPAERR("failed to get idx"); + return; + } + + ep = &ipa3_ctx->ep[ipa_ep_idx]; + + IPA_MPM_DBG("Reading channel for chan %d, ep = %d, gsi_chan_hdl = %d\n", + chan, ep, ep->gsi_chan_hdl); + + res = ipa3_get_gsi_chan_info(&chan_info, ep->gsi_chan_hdl); + if (res) + IPA_MPM_ERR("Reading of channel failed for ep %d\n", ep); +} + +/* ipa_mpm_mhi_probe_cb is received for each MHI'/MHI channel + * Currently we have 4 MHI channels. + */ +static int ipa_mpm_mhi_probe_cb(struct mhi_device *mhi_dev, + const struct mhi_device_id *mhi_id) +{ + struct ipa_mpm_channel *ch; + int ret; + enum ipa_client_type ul_prod, dl_cons; + int probe_id; + struct ipa_req_chan_out_params ul_out_params, dl_out_params; + void __iomem *db_addr; + int ipa_ep_idx; + struct ipa3_ep_context *ep; + u32 evt_ring_db_addr_low, evt_ring_db_addr_high; + u32 wp_addr; + int pipe_idx; + bool is_acted = true; + uint64_t flow_ctrl_mask = 0; + bool add_delete = false; + + IPA_MPM_FUNC_ENTRY(); + + if (ipa_mpm_ctx == NULL) { + IPA_MPM_ERR("ipa_mpm_ctx is NULL not expected, returning..\n"); + return -ENOMEM; + } + + probe_id = get_idx_from_id(mhi_id); + + if (probe_id >= IPA_MPM_MHIP_CH_ID_MAX) { + IPA_MPM_ERR("chan=%pK is not supported for now\n", mhi_id); + return -EPERM; + } + + if (ipa_mpm_ctx->md[probe_id].init_complete) { + IPA_MPM_ERR("Probe initialization already done, returning\n"); + return 0; + } + + /* Read the MHI CH/ER DB address from MHI Driver. */ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) + ret = mhi_get_channel_db_base(mhi_dev, + &ipa_mpm_ctx->dev_info.chdb_base); + if (ret) { + IPA_MPM_ERR("Could not populate channel db base address\n"); + return -EINVAL; + } + + IPA_MPM_DBG("chdb-base=0x%x\n", ipa_mpm_ctx->dev_info.chdb_base); + + ret = mhi_get_event_ring_db_base(mhi_dev, + &ipa_mpm_ctx->dev_info.erdb_base); + if (ret) { + IPA_MPM_ERR("Could not populate event ring db base address\n"); + return -EINVAL; + } + + IPA_MPM_DBG("erdb-base=0x%x\n", ipa_mpm_ctx->dev_info.erdb_base); +#endif + + IPA_MPM_DBG("Received probe for id=%d\n", probe_id); + + get_ipa3_client(probe_id, &ul_prod, &dl_cons); + + /* Vote for IPA clock for first time in initialization seq. + * IPA clock will be devoted when MHI enters LPM + * PCIe clock will be voted / devoted with every channel probe + * we receive. + * ul_prod = Host -> Device + * dl_cons = Device -> Host + */ + ipa_mpm_ctx->md[probe_id].mhi_dev = mhi_dev; + ipa_mpm_ctx->mhi_parent_dev = + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) + ipa_mpm_ctx->md[probe_id].mhi_dev->dev.parent->parent; + #else + ipa_mpm_ctx->md[probe_id].mhi_dev->dev.parent; + #endif + mutex_lock(&ipa_mpm_ctx->md[probe_id].mhi_mutex); + ipa_mpm_ctx->md[probe_id].remote_state = MPM_MHIP_REMOTE_STOP; + mutex_unlock(&ipa_mpm_ctx->md[probe_id].mhi_mutex); + ret = ipa_mpm_vote_unvote_pcie_clk(CLK_ON, probe_id, true, &is_acted); + if (ret) { + IPA_MPM_ERR("Err %d voitng PCIe clocks\n", ret); + return -EPERM; + } + + ipa_mpm_vote_unvote_ipa_clk(CLK_ON, probe_id); + ipa_mpm_ctx->md[probe_id].in_lpm = false; + IPA_MPM_DBG("ul chan = %d, dl_chan = %d\n", ul_prod, dl_cons); + + /* + * Set up MHI' pipes for Device IPA filling in + * Channel Context and Event Context. + * These params will be sent to Device side. + * UL CHAN = HOST -> Device + * DL CHAN = Device -> HOST + * per channel a TRE and EV is allocated. + * for a UL channel - + * IPA HOST PROD TRE -> IPA DEVICE CONS EV + * IPA HOST PROD EV -> IPA DEVICE CONS TRE + * for a DL channel - + * IPA Device PROD TRE -> IPA HOST CONS EV + * IPA Device PROD EV -> IPA HOST CONS TRE + */ + if (ul_prod != IPA_CLIENT_MAX) { + /* store UL properties */ + ch = &ipa_mpm_ctx->md[probe_id].ul_prod; + /* Store Channel properties */ + ch->chan_props.id = mhi_dev->ul_chan_id; + ch->chan_props.device_db = + ipa_mpm_ctx->dev_info.chdb_base + + ch->chan_props.id * 8; + /* Fill Channel Conext to be sent to Device side */ + ch->chan_props.ch_ctx.chtype = + IPA_MPM_MHI_HOST_UL_CHANNEL; + ch->chan_props.ch_ctx.erindex = + mhi_dev->ul_event_id; + ch->chan_props.ch_ctx.rlen = (ipa3_ctx->mpm_ring_size_ul) * + GSI_EVT_RING_RE_SIZE_16B; + /* Store Event properties */ + ch->evt_props.ev_ctx.update_rp_modc = 1; + ch->evt_props.ev_ctx.update_rp_intmodt = 0; + ch->evt_props.ev_ctx.ertype = 1; + ch->evt_props.ev_ctx.rlen = (ipa3_ctx->mpm_ring_size_ul) * + GSI_EVT_RING_RE_SIZE_16B; + ch->evt_props.ev_ctx.buff_size = TRE_BUFF_SIZE; + ch->evt_props.device_db = + ipa_mpm_ctx->dev_info.erdb_base + + ch->chan_props.ch_ctx.erindex * 8; + + /* connect Host GSI pipes with MHI' protocol */ + ret = ipa_mpm_connect_mhip_gsi_pipe(ul_prod, + probe_id, &ul_out_params); + if (ret) { + IPA_MPM_ERR("failed connecting MPM client %d\n", + ul_prod); + goto fail_gsi_setup; + } + + ch->evt_props.ev_ctx.update_rp_addr = + ipa_mpm_smmu_map_doorbell( + MHIP_SMMU_DOMAIN_PCIE, + ul_out_params.db_reg_phs_addr_lsb); + if (ch->evt_props.ev_ctx.update_rp_addr == 0) + ipa_assert(); + + ipa_mpm_ctx->md[probe_id].ul_prod.db_device_iova = + ch->evt_props.ev_ctx.update_rp_addr; + + ret = __ipa_mpm_configure_mhi_device( + ch, probe_id, DMA_TO_HIPA); + if (ret) { + IPA_MPM_ERR("configure_mhi_dev fail %d\n", + ret); + goto fail_smmu; + } + } + + if (dl_cons != IPA_CLIENT_MAX) { + /* store DL channel properties */ + ch = &ipa_mpm_ctx->md[probe_id].dl_cons; + /* Store Channel properties */ + ch->chan_props.id = mhi_dev->dl_chan_id; + ch->chan_props.device_db = + ipa_mpm_ctx->dev_info.chdb_base + + ch->chan_props.id * 8; + /* Fill Channel Conext to be be sent to Dev side */ + ch->chan_props.ch_ctx.chstate = 1; + ch->chan_props.ch_ctx.chtype = + IPA_MPM_MHI_HOST_DL_CHANNEL; + ch->chan_props.ch_ctx.erindex = mhi_dev->dl_event_id; + ch->chan_props.ch_ctx.rlen = (ipa3_ctx->mpm_ring_size_dl) * + GSI_EVT_RING_RE_SIZE_16B; + /* Store Event properties */ + ch->evt_props.ev_ctx.update_rp_modc = 0; + ch->evt_props.ev_ctx.update_rp_intmodt = 0; + ch->evt_props.ev_ctx.ertype = 1; + ch->evt_props.ev_ctx.rlen = (ipa3_ctx->mpm_ring_size_dl) * + GSI_EVT_RING_RE_SIZE_16B; + ch->evt_props.ev_ctx.buff_size = TRE_BUFF_SIZE; + ch->evt_props.device_db = + ipa_mpm_ctx->dev_info.erdb_base + + ch->chan_props.ch_ctx.erindex * 8; + + /* connect Host GSI pipes with MHI' protocol */ + ret = ipa_mpm_connect_mhip_gsi_pipe(dl_cons, + probe_id, &dl_out_params); + if (ret) { + IPA_MPM_ERR("connecting MPM client = %d failed\n", + dl_cons); + goto fail_gsi_setup; + } + + ch->evt_props.ev_ctx.update_rp_addr = + ipa_mpm_smmu_map_doorbell( + MHIP_SMMU_DOMAIN_PCIE, + dl_out_params.db_reg_phs_addr_lsb); + + if (ch->evt_props.ev_ctx.update_rp_addr == 0) + ipa_assert(); + + ipa_mpm_ctx->md[probe_id].dl_cons.db_device_iova = + ch->evt_props.ev_ctx.update_rp_addr; + + ret = __ipa_mpm_configure_mhi_device(ch, probe_id, + DMA_FROM_HIPA); + if (ret) { + IPA_MPM_ERR("mpm_config_mhi_dev failed %d\n", ret); + goto fail_smmu; + } + } + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0)) + ret = mhi_prepare_for_transfer(ipa_mpm_ctx->md[probe_id].mhi_dev, 0); +#else + ret = mhi_prepare_for_transfer(ipa_mpm_ctx->md[probe_id].mhi_dev); +#endif + if (ret) { + IPA_MPM_ERR("mhi_prepare_for_transfer failed %d\n", ret); + /* + * WA to handle prepare_for_tx failures. + * Though prepare for transfer fails, indicate success + * to MHI driver. remove_cb will be called eventually when + * Device side comes from where pending cleanup happens. + */ + mutex_lock(&ipa_mpm_ctx->md[probe_id].mhi_mutex); + atomic_inc(&ipa_mpm_ctx->probe_cnt); + ipa_mpm_ctx->md[probe_id].init_complete = false; + mutex_unlock(&ipa_mpm_ctx->md[probe_id].mhi_mutex); + IPA_MPM_FUNC_EXIT(); + return 0; + } + + /* mhi_prepare_for_transfer translates to starting remote channels */ + mutex_lock(&ipa_mpm_ctx->md[probe_id].mhi_mutex); + ipa_mpm_ctx->md[probe_id].remote_state = MPM_MHIP_REMOTE_START; + mutex_unlock(&ipa_mpm_ctx->md[probe_id].mhi_mutex); + /* + * Ring initial channel db - Host Side UL and Device side DL channel. + * To ring doorbell, write "WP" into doorbell register. + * This WP should be set to 1 element less than ring max. + */ + + /* Ring UL PRODUCER TRANSFER RING (HOST IPA -> DEVICE IPA) Doorbell */ + if (ul_prod != IPA_CLIENT_MAX) { + IPA_MPM_DBG("Host UL TR PA DB = 0X%0x\n", + ul_out_params.db_reg_phs_addr_lsb); + + db_addr = ioremap( + (phys_addr_t)(ul_out_params.db_reg_phs_addr_lsb), 4); + + wp_addr = ipa_mpm_ctx->md[probe_id].ul_prod_ring.tr_pa + + ((ipa3_ctx->mpm_ring_size_ul - 1) * + GSI_CHAN_RE_SIZE_16B); + + iowrite32(wp_addr, db_addr); + + IPA_MPM_DBG("Host UL TR DB = 0X%pK, wp_addr = 0X%0x", + db_addr, wp_addr); + + iounmap(db_addr); + ipa_mpm_read_channel(ul_prod); + + /* Ring UL PRODUCER EVENT RING (HOST IPA -> DEVICE IPA) Doorbell + * Ring the event DB to a value outside the + * ring range such that rp and wp never meet. + */ + ipa_ep_idx = ipa_get_ep_mapping(ul_prod); + + if (ipa_ep_idx == IPA_EP_NOT_ALLOCATED) { + IPA_MPM_ERR("fail to alloc EP.\n"); + goto fail_start_channel; + } + ep = &ipa3_ctx->ep[ipa_ep_idx]; + + IPA_MPM_DBG("for ep_idx %d , gsi_evt_ring_hdl = %ld\n", + ipa_ep_idx, ep->gsi_evt_ring_hdl); + gsi_query_evt_ring_db_addr(ep->gsi_evt_ring_hdl, + &evt_ring_db_addr_low, &evt_ring_db_addr_high); + + IPA_MPM_DBG("Host UL ER PA DB = 0X%0x\n", + evt_ring_db_addr_low); + + db_addr = ioremap((phys_addr_t)(evt_ring_db_addr_low), 4); + + wp_addr = ipa_mpm_ctx->md[probe_id].ul_prod_ring.er_pa + + ((ipa3_ctx->mpm_ring_size_ul + 1) * + GSI_EVT_RING_RE_SIZE_16B); + IPA_MPM_DBG("Host UL ER DB = 0X%pK, wp_addr = 0X%0x", + db_addr, wp_addr); + + iowrite32(wp_addr, db_addr); + iounmap(db_addr); + + /* Ring DEVICE IPA DL CONSUMER Event Doorbell */ + db_addr = ioremap((phys_addr_t) + (ipa_mpm_ctx->md[probe_id].ul_prod.evt_props.device_db), + 4); + + wp_addr = ipa_mpm_ctx->md[probe_id].ul_prod_ring.tr_pa + + ((ipa3_ctx->mpm_ring_size_ul + 1) * + GSI_EVT_RING_RE_SIZE_16B); + + iowrite32(wp_addr, db_addr); + iounmap(db_addr); + } + + /* Ring DL PRODUCER (DEVICE IPA -> HOST IPA) Doorbell */ + if (dl_cons != IPA_CLIENT_MAX) { + db_addr = ioremap((phys_addr_t) + (ipa_mpm_ctx->md[probe_id].dl_cons.chan_props.device_db), + 4); + + wp_addr = ipa_mpm_ctx->md[probe_id].dl_prod_ring.tr_pa + + ((ipa3_ctx->mpm_ring_size_dl - 1) * + GSI_CHAN_RE_SIZE_16B); + + IPA_MPM_DBG("Device DL TR DB = 0X%pK, wp_addr = 0X%0x", + db_addr, wp_addr); + + iowrite32(wp_addr, db_addr); + + iounmap(db_addr); + + /* + * Ring event ring DB on Device side. + * ipa_mpm should ring the event DB to a value outside the + * ring range such that rp and wp never meet. + */ + db_addr = + ioremap( + (phys_addr_t) + (ipa_mpm_ctx->md[probe_id].dl_cons.evt_props.device_db), + 4); + + wp_addr = ipa_mpm_ctx->md[probe_id].dl_prod_ring.er_pa + + ((ipa3_ctx->mpm_ring_size_dl + 1) * + GSI_EVT_RING_RE_SIZE_16B); + + iowrite32(wp_addr, db_addr); + IPA_MPM_DBG("Device UL ER DB = 0X%pK,wp_addr = 0X%0x", + db_addr, wp_addr); + iounmap(db_addr); + + /* Ring DL EVENT RING CONSUMER (DEVICE IPA CONSUMER) Doorbell */ + ipa_ep_idx = ipa_get_ep_mapping(dl_cons); + + if (ipa_ep_idx == IPA_EP_NOT_ALLOCATED) { + IPA_MPM_ERR("fail to alloc EP.\n"); + goto fail_start_channel; + } + ep = &ipa3_ctx->ep[ipa_ep_idx]; + + gsi_query_evt_ring_db_addr(ep->gsi_evt_ring_hdl, + &evt_ring_db_addr_low, &evt_ring_db_addr_high); + IPA_MPM_DBG("Host DL ER PA DB = 0X%0x\n", + evt_ring_db_addr_low); + db_addr = ioremap((phys_addr_t)(evt_ring_db_addr_low), 4); + + wp_addr = ipa_mpm_ctx->md[probe_id].dl_prod_ring.tr_pa + + ((ipa3_ctx->mpm_ring_size_dl + 1) * + GSI_EVT_RING_RE_SIZE_16B); + iowrite32(wp_addr, db_addr); + IPA_MPM_DBG("Host DL ER DB = 0X%pK, wp_addr = 0X%0x", + db_addr, wp_addr); + iounmap(db_addr); + } + + /* Check if TETH connection is in progress. + * If teth isn't started by now, then Stop UL channel. + */ + switch (ipa_mpm_ctx->md[probe_id].teth_state) { + case IPA_MPM_TETH_INIT: + /* + * Make sure to stop Device side channels before + * stopping Host side UL channels. This is to make + * sure Device side doesn't access host side IPA if + * Host IPA gets unvoted. + */ + ret = ipa_mpm_start_stop_remote_mhip_chan(probe_id, + MPM_MHIP_STOP, true); + if (ret) { + /* + * This can fail only when modem is in SSR. + * Eventually there would be a remove callback, + * so return a failure. + */ + IPA_MPM_ERR("MHIP remote chan stop fail = %d\n", ret); + return ret; + } + if (ul_prod != IPA_CLIENT_MAX) { + /* No teth started yet, disable UL channel */ + ipa_ep_idx = ipa_get_ep_mapping(ul_prod); + if (ipa_ep_idx == IPA_EP_NOT_ALLOCATED) { + IPA_MPM_ERR("fail to alloc EP.\n"); + goto fail_stop_channel; + } + ret = ipa_stop_gsi_channel(ipa_ep_idx); + if (ret) { + IPA_MPM_ERR("MHIP Stop channel err = %d\n", + ret); + goto fail_stop_channel; + } + ipa_mpm_change_gsi_state(probe_id, + IPA_MPM_MHIP_CHAN_UL, + GSI_STOPPED); + } + if (is_acted) + ipa_mpm_vote_unvote_pcie_clk(CLK_OFF, probe_id, + true, &is_acted); + break; + case IPA_MPM_TETH_INPROGRESS: + case IPA_MPM_TETH_CONNECTED: + IPA_MPM_DBG("UL channel is already started, continue\n"); + ipa_mpm_change_teth_state(probe_id, IPA_MPM_TETH_CONNECTED); + + /* Lift the delay for rmnet USB prod pipe */ + if (probe_id == IPA_MPM_MHIP_CH_ID_1) { + pipe_idx = ipa_get_ep_mapping(IPA_CLIENT_USB_PROD); + ipa3_xdci_ep_delay_rm(pipe_idx); + /* Register for BW indication from Q6*/ + if (!ipa3_qmi_reg_dereg_for_bw(true)) + IPA_MPM_DBG( + "QMI BW reg Req failed,might be SSR"); + } + break; + default: + IPA_MPM_DBG("No op for UL channel, in teth state = %d", + ipa_mpm_ctx->md[probe_id].teth_state); + break; + } + + atomic_inc(&ipa_mpm_ctx->probe_cnt); + /* Check if ODL/USB DPL pipe is connected before probe */ + if (probe_id == IPA_MPM_MHIP_CH_ID_2) { + if (ipa3_is_odl_connected()) + ret = ipa_mpm_set_dma_mode( + IPA_CLIENT_MHI_PRIME_DPL_PROD, + IPA_CLIENT_ODL_DPL_CONS, false); + else if (atomic_read(&ipa_mpm_ctx->adpl_over_usb_available)) + ret = ipa_mpm_set_dma_mode( + IPA_CLIENT_MHI_PRIME_DPL_PROD, + IPA_CLIENT_USB_DPL_CONS, false); + if (ret) + IPA_MPM_ERR("DPL DMA to ODL/USB failed, ret = %d\n", + ret); + } + mutex_lock(&ipa_mpm_ctx->md[probe_id].mhi_mutex); + ipa_mpm_ctx->md[probe_id].init_complete = true; + mutex_unlock(&ipa_mpm_ctx->md[probe_id].mhi_mutex); + /* Update Flow control Monitoring, only for the teth UL Prod pipes */ + if (probe_id == IPA_MPM_MHIP_CH_ID_0) { + ipa_ep_idx = ipa_get_ep_mapping(ul_prod); + ep = &ipa3_ctx->ep[ipa_ep_idx]; + ret = ipa3_uc_send_enable_flow_control(ep->gsi_chan_hdl, + ipa3_ctx->mpm_uc_thresh); + IPA_MPM_DBG("Updated uc threshold to %d", + ipa3_ctx->mpm_uc_thresh); + if (ret) { + IPA_MPM_ERR("Err %d flow control enable\n", ret); + goto fail_flow_control; + } + IPA_MPM_DBG("Flow Control enabled for %d", probe_id); + flow_ctrl_mask = atomic_read(&ipa_mpm_ctx->flow_ctrl_mask); + add_delete = flow_ctrl_mask > 0 ? 1 : 0; + ret = ipa3_uc_send_update_flow_control(flow_ctrl_mask, + add_delete); + if (ret) { + IPA_MPM_ERR("Err %d flow control update\n", ret); + goto fail_flow_control; + } + IPA_MPM_DBG("Flow Control updated for %d", probe_id); + } + /* cache the current ring-size */ + ipa3_ctx->mpm_ring_size_ul_cache = ipa3_ctx->mpm_ring_size_ul; + ipa3_ctx->mpm_ring_size_dl_cache = ipa3_ctx->mpm_ring_size_dl; + IPA_MPM_DBG("Mpm ring size ul/dl %d / %d", + ipa3_ctx->mpm_ring_size_ul, ipa3_ctx->mpm_ring_size_dl); + IPA_MPM_FUNC_EXIT(); + return 0; + +fail_gsi_setup: +fail_start_channel: +fail_stop_channel: +fail_smmu: +fail_flow_control: + if (ipa_mpm_ctx->dev_info.ipa_smmu_enabled) + IPA_MPM_DBG("SMMU failed\n"); + if (is_acted) + ipa_mpm_vote_unvote_pcie_clk(CLK_OFF, probe_id, true, + &is_acted); + ipa_mpm_vote_unvote_ipa_clk(CLK_OFF, probe_id); + ipa_assert(); + return ret; +} + +static void ipa_mpm_init_mhip_channel_info(void) +{ + /* IPA_MPM_MHIP_CH_ID_0 => MHIP TETH PIPES */ + ipa_mpm_pipes[IPA_MPM_MHIP_CH_ID_0].dl_cons.ipa_client = + IPA_CLIENT_MHI_PRIME_TETH_PROD; + ipa_mpm_pipes[IPA_MPM_MHIP_CH_ID_0].dl_cons.ep_cfg = + mhip_dl_teth_ep_cfg; + ipa_mpm_pipes[IPA_MPM_MHIP_CH_ID_0].ul_prod.ipa_client = + IPA_CLIENT_MHI_PRIME_TETH_CONS; + ipa_mpm_pipes[IPA_MPM_MHIP_CH_ID_0].ul_prod.ep_cfg = + mhip_ul_teth_ep_cfg; + ipa_mpm_pipes[IPA_MPM_MHIP_CH_ID_0].ul_prod.ep_cfg.aggr.aggr_byte_limit + = ipa3_ctx->mpm_teth_aggr_size; + ipa_mpm_pipes[IPA_MPM_MHIP_CH_ID_0].mhip_client = + IPA_MPM_MHIP_TETH; + + IPA_MPM_DBG("Teth Aggregation byte limit =%d\n", + ipa3_ctx->mpm_teth_aggr_size); + + /* IPA_MPM_MHIP_CH_ID_1 => MHIP RMNET PIPES */ + ipa_mpm_pipes[IPA_MPM_MHIP_CH_ID_1].dl_cons.ipa_client = + IPA_CLIENT_MHI_PRIME_RMNET_PROD; + ipa_mpm_pipes[IPA_MPM_MHIP_CH_ID_1].dl_cons.ep_cfg = + mhip_dl_rmnet_ep_cfg; + ipa_mpm_pipes[IPA_MPM_MHIP_CH_ID_1].ul_prod.ipa_client = + IPA_CLIENT_MHI_PRIME_RMNET_CONS; + ipa_mpm_pipes[IPA_MPM_MHIP_CH_ID_1].ul_prod.ep_cfg = + mhip_ul_rmnet_ep_cfg; + ipa_mpm_pipes[IPA_MPM_MHIP_CH_ID_1].mhip_client = + IPA_MPM_MHIP_USB_RMNET; + + /* IPA_MPM_MHIP_CH_ID_2 => MHIP ADPL PIPE */ + ipa_mpm_pipes[IPA_MPM_MHIP_CH_ID_2].dl_cons.ipa_client = + IPA_CLIENT_MHI_PRIME_DPL_PROD; + ipa_mpm_pipes[IPA_MPM_MHIP_CH_ID_2].dl_cons.ep_cfg = + mhip_dl_dpl_ep_cfg; + ipa_mpm_pipes[IPA_MPM_MHIP_CH_ID_2].ul_prod.ipa_client = + IPA_CLIENT_MAX; + ipa_mpm_pipes[IPA_MPM_MHIP_CH_ID_2].mhip_client = + IPA_MPM_MHIP_USB_DPL; +} + +static void ipa_mpm_mhi_remove_cb(struct mhi_device *mhi_dev) +{ + int mhip_idx; + + IPA_MPM_FUNC_ENTRY(); + + for (mhip_idx = 0; mhip_idx < IPA_MPM_MHIP_CH_ID_MAX; mhip_idx++) { + if (mhi_dev == ipa_mpm_ctx->md[mhip_idx].mhi_dev) + break; + } + if (mhip_idx >= IPA_MPM_MHIP_CH_ID_MAX) { + IPA_MPM_DBG("remove_cb for mhip_idx = %d not probed before\n", + mhip_idx); + return; + } + + IPA_MPM_DBG("remove_cb for mhip_idx = %d", mhip_idx); + + mutex_lock(&ipa_mpm_ctx->md[mhip_idx].mhi_mutex); + ipa_mpm_ctx->md[mhip_idx].init_complete = false; + mutex_unlock(&ipa_mpm_ctx->md[mhip_idx].mhi_mutex); + + if (mhip_idx == IPA_MPM_MHIP_CH_ID_0) + ipa3_uc_send_disable_flow_control(); + + ipa_mpm_mhip_shutdown(mhip_idx); + + atomic_dec(&ipa_mpm_ctx->probe_cnt); + + if (atomic_read(&ipa_mpm_ctx->probe_cnt) == 0) { + /* Last probe done, reset Everything here */ + ipa_mpm_ctx->mhi_parent_dev = NULL; + ipa_mpm_ctx->carved_smmu_cb.next_addr = + ipa_mpm_ctx->carved_smmu_cb.va_start; + atomic_set(&ipa_mpm_ctx->pcie_clk_total_cnt, 0); + /* Force set to zero during SSR */ + atomic_set(&ipa_mpm_ctx->active_teth_count, 0); + for (mhip_idx = 0; + mhip_idx < IPA_MPM_MHIP_CH_ID_MAX; mhip_idx++) { + atomic_set( + &ipa_mpm_ctx->md[mhip_idx].clk_cnt.pcie_clk_cnt, + 0); + } + } + + IPA_MPM_FUNC_EXIT(); +} + +static void ipa_mpm_mhi_status_cb(struct mhi_device *mhi_dev, +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) + enum mhi_callback mhi_cb) +#else + enum MHI_CB mhi_cb) +#endif +{ + int mhip_idx; + enum mhip_status_type status; + + IPA_MPM_DBG("%d\n", mhi_cb); + + for (mhip_idx = 0; mhip_idx < IPA_MPM_MHIP_CH_ID_MAX; mhip_idx++) { + if (mhi_dev == ipa_mpm_ctx->md[mhip_idx].mhi_dev) + break; + } + if (mhip_idx >= IPA_MPM_MHIP_CH_ID_MAX) { + IPA_MPM_DBG("ignoring secondary callbacks\n"); + return; + } + + mutex_lock(&ipa_mpm_ctx->md[mhip_idx].mhi_mutex); + if (!ipa_mpm_ctx->md[mhip_idx].init_complete) { + /* + * SSR might be in progress, dont have to vote/unvote for + * IPA clocks as it will be taken care in remove_cb/subsequent + * probe. + */ + IPA_MPM_DBG("SSR in progress, return\n"); + mutex_unlock(&ipa_mpm_ctx->md[mhip_idx].mhi_mutex); + return; + } + mutex_unlock(&ipa_mpm_ctx->md[mhip_idx].mhi_mutex); + + switch (mhi_cb) { + case MHI_CB_IDLE: + break; + case MHI_CB_LPM_ENTER: + if (!ipa_mpm_ctx->md[mhip_idx].in_lpm) { + status = ipa_mpm_start_stop_mhip_chan( + IPA_MPM_MHIP_CHAN_DL, + mhip_idx, MPM_MHIP_STOP); + IPA_MPM_DBG("status = %d\n", status); + ipa_mpm_vote_unvote_ipa_clk(CLK_OFF, mhip_idx); + ipa_mpm_ctx->md[mhip_idx].in_lpm = true; + } else { + IPA_MPM_DBG("Already in lpm\n"); + } + break; + case MHI_CB_LPM_EXIT: + if (ipa_mpm_ctx->md[mhip_idx].in_lpm) { + ipa_mpm_vote_unvote_ipa_clk(CLK_ON, mhip_idx); + status = ipa_mpm_start_stop_mhip_chan( + IPA_MPM_MHIP_CHAN_DL, + mhip_idx, MPM_MHIP_START); + IPA_MPM_DBG("status = %d\n", status); + ipa_mpm_ctx->md[mhip_idx].in_lpm = false; + } else { + IPA_MPM_DBG("Already out of lpm\n"); + } + break; + case MHI_CB_EE_RDDM: + case MHI_CB_PENDING_DATA: + case MHI_CB_SYS_ERROR: + case MHI_CB_FATAL_ERROR: + case MHI_CB_EE_MISSION_MODE: + case MHI_CB_DTR_SIGNAL: + default: + IPA_MPM_ERR("unexpected event %d\n", mhi_cb); + break; + } +} + +static void ipa_mpm_mhip_map_prot(enum ipa_usb_teth_prot prot, + enum ipa_mpm_mhip_client_type *mhip_client) +{ + switch (prot) { + case IPA_USB_RNDIS: + *mhip_client = IPA_MPM_MHIP_TETH; + break; + case IPA_USB_RMNET: + *mhip_client = IPA_MPM_MHIP_USB_RMNET; + break; + case IPA_USB_DIAG: + *mhip_client = IPA_MPM_MHIP_USB_DPL; + break; + default: + *mhip_client = IPA_MPM_MHIP_NONE; + break; + } + IPA_MPM_DBG("Mapped xdci prot %d -> MHIP prot %d\n", prot, + *mhip_client); +} + +int ipa_mpm_mhip_xdci_pipe_enable(enum ipa_usb_teth_prot xdci_teth_prot) +{ + int probe_id = IPA_MPM_MHIP_CH_ID_MAX; + int i; + enum ipa_mpm_mhip_client_type mhip_client; + enum mhip_status_type status = MHIP_STATUS_SUCCESS; + int pipe_idx; + bool is_acted = true; + int ret = 0; + + if (ipa_mpm_ctx == NULL) { + IPA_MPM_ERR("MPM not platform probed yet, returning ..\n"); + return 0; + } + + ipa_mpm_mhip_map_prot(xdci_teth_prot, &mhip_client); + + for (i = 0; i < IPA_MPM_MHIP_CH_ID_MAX; i++) { + if (ipa_mpm_pipes[i].mhip_client == mhip_client) { + probe_id = i; + break; + } + } + + if ((probe_id < IPA_MPM_MHIP_CH_ID_0) || + (probe_id >= IPA_MPM_MHIP_CH_ID_MAX)) { + IPA_MPM_ERR("Unknown probe_id\n"); + return 0; + } + + if (probe_id == IPA_MPM_MHIP_CH_ID_0) { + /* For rndis, the MPM processing happens in WAN State IOCTL */ + IPA_MPM_DBG("MPM Xdci connect for rndis, no -op\n"); + return 0; + } + + IPA_MPM_DBG("Connect xdci prot %d -> mhip_client = %d probe_id = %d\n", + xdci_teth_prot, mhip_client, probe_id); + + ipa_mpm_ctx->md[probe_id].mhip_client = mhip_client; + + ret = ipa_mpm_vote_unvote_pcie_clk(CLK_ON, probe_id, + false, &is_acted); + if (ret) { + IPA_MPM_ERR("Error cloking on PCIe clk, err = %d\n", ret); + return ret; + } + + /* + * Make sure to start Device side channels before + * starting Host side UL channels. This is to make + * sure device side access host side IPA only when + * Host IPA gets voted. + */ + ret = ipa_mpm_start_stop_remote_mhip_chan(probe_id, + MPM_MHIP_START, false); + if (ret) { + /* + * This can fail only when modem is in SSR state. + * Eventually there would be a remove callback, + * so return a failure. Dont have to unvote PCIE here. + */ + IPA_MPM_ERR("MHIP remote chan start fail = %d\n", + ret); + return ret; + } + + IPA_MPM_DBG("MHIP remote channel start success\n"); + + switch (mhip_client) { + case IPA_MPM_MHIP_USB_RMNET: + ipa_mpm_set_dma_mode(IPA_CLIENT_USB_PROD, + IPA_CLIENT_MHI_PRIME_RMNET_CONS, false); + break; + case IPA_MPM_MHIP_USB_DPL: + IPA_MPM_DBG("connecting DPL prot %d\n", mhip_client); + ipa_mpm_change_teth_state(probe_id, IPA_MPM_TETH_CONNECTED); + atomic_set(&ipa_mpm_ctx->adpl_over_usb_available, 1); + return 0; + default: + IPA_MPM_ERR("mhip_client = %d not processed\n", mhip_client); + if (is_acted) { + ret = ipa_mpm_vote_unvote_pcie_clk(CLK_OFF, probe_id, + false, &is_acted); + if (ret) { + IPA_MPM_ERR("Err unvoting PCIe clk, err = %d\n", + ret); + return ret; + } + } + ipa_assert(); + return -EINVAL; + } + + if (mhip_client != IPA_MPM_MHIP_USB_DPL) + /* Start UL MHIP channel for offloading teth connection */ + status = ipa_mpm_start_stop_mhip_chan(IPA_MPM_MHIP_CHAN_UL, + probe_id, + MPM_MHIP_START); + switch (status) { + case MHIP_STATUS_SUCCESS: + case MHIP_STATUS_NO_OP: + ipa_mpm_change_teth_state(probe_id, IPA_MPM_TETH_CONNECTED); + /* Register for BW indication from Q6*/ + if (!ipa3_qmi_reg_dereg_for_bw(true)) + IPA_MPM_DBG("Fail regst QMI BW Indctn,might be SSR"); + + pipe_idx = ipa_get_ep_mapping(IPA_CLIENT_USB_PROD); + + /* Lift the delay for rmnet USB prod pipe */ + ipa3_xdci_ep_delay_rm(pipe_idx); + if (status == MHIP_STATUS_NO_OP && is_acted) { + /* Channels already have been started, + * we can devote for pcie clocks + */ + ipa_mpm_vote_unvote_pcie_clk(CLK_OFF, probe_id, + false, &is_acted); + } + break; + case MHIP_STATUS_EP_NOT_READY: + if (is_acted) + ipa_mpm_vote_unvote_pcie_clk(CLK_OFF, probe_id, + false, &is_acted); + ipa_mpm_change_teth_state(probe_id, IPA_MPM_TETH_INPROGRESS); + break; + case MHIP_STATUS_FAIL: + case MHIP_STATUS_BAD_STATE: + case MHIP_STATUS_EP_NOT_FOUND: + IPA_MPM_ERR("UL chan cant be started err =%d\n", status); + if (is_acted) + ipa_mpm_vote_unvote_pcie_clk(CLK_OFF, probe_id, + false, &is_acted); + ret = -EFAULT; + break; + default: + if (is_acted) + ipa_mpm_vote_unvote_pcie_clk(CLK_OFF, probe_id, + false, &is_acted); + IPA_MPM_ERR("Err not found\n"); + break; + } + return ret; +} +EXPORT_SYMBOL(ipa_mpm_mhip_xdci_pipe_enable); + +int ipa_mpm_mhip_xdci_pipe_disable(enum ipa_usb_teth_prot xdci_teth_prot) +{ + int probe_id = IPA_MPM_MHIP_CH_ID_MAX; + int i; + enum ipa_mpm_mhip_client_type mhip_client; + enum mhip_status_type status; + int ret = 0; + bool is_acted = true; + + if (ipa_mpm_ctx == NULL) { + IPA_MPM_ERR("MPM not platform probed, returning ..\n"); + return 0; + } + + ipa_mpm_mhip_map_prot(xdci_teth_prot, &mhip_client); + + for (i = 0; i < IPA_MPM_MHIP_CH_ID_MAX; i++) { + if (ipa_mpm_pipes[i].mhip_client == mhip_client) { + probe_id = i; + break; + } + } + + if ((probe_id < IPA_MPM_MHIP_CH_ID_0) || + (probe_id >= IPA_MPM_MHIP_CH_ID_MAX)) { + IPA_MPM_ERR("Unknown probe_id\n"); + return 0; + } + + if (probe_id == IPA_MPM_MHIP_CH_ID_0) { + /* For rndis, the MPM processing happens in WAN State IOCTL */ + IPA_MPM_DBG("MPM Xdci disconnect for rndis, no -op\n"); + return 0; + } + + IPA_MPM_DBG("xdci disconnect prot %d mhip_client = %d probe_id = %d\n", + xdci_teth_prot, mhip_client, probe_id); + /* + * Make sure to stop Device side channels before + * stopping Host side UL channels. This is to make + * sure device side doesn't access host side IPA if + * Host IPA gets unvoted. + */ + if ((!atomic_read(&ipa_mpm_ctx->adpl_over_odl_available)) + || (probe_id != IPA_MPM_MHIP_CH_ID_2)) { + ret = ipa_mpm_start_stop_remote_mhip_chan(probe_id, + MPM_MHIP_STOP, false); + if (ret) { + /** + * This can fail only when modem is in SSR state. + * Eventually there would be a remove callback, + * so return a failure. + */ + IPA_MPM_ERR("MHIP remote chan stop fail = %d\n", ret); + return ret; + } + IPA_MPM_DBG("MHIP remote channels are stopped(id=%d)\n", + probe_id); + } + + switch (mhip_client) { + case IPA_MPM_MHIP_USB_RMNET: + ret = ipa_mpm_set_dma_mode(IPA_CLIENT_USB_PROD, + IPA_CLIENT_APPS_LAN_CONS, true); + if (ret) { + IPA_MPM_ERR("failed to reset dma mode\n"); + return ret; + } + break; + case IPA_MPM_MHIP_TETH: + IPA_MPM_DBG("Rndis Disconnect, wait for wan_state ioctl\n"); + return 0; + case IPA_MPM_MHIP_USB_DPL: + IPA_MPM_DBG("Teth Disconnecting for DPL\n"); + + /* change teth state only if ODL is disconnected */ + if (!ipa3_is_odl_connected()) { + ipa_mpm_change_teth_state(probe_id, IPA_MPM_TETH_INIT); + ipa_mpm_ctx->md[probe_id].mhip_client = + IPA_MPM_MHIP_NONE; + } + ret = ipa_mpm_vote_unvote_pcie_clk(CLK_OFF, probe_id, + false, &is_acted); + if (ret) + IPA_MPM_ERR("Error clking off PCIe clk err%d\n", ret); + atomic_set(&ipa_mpm_ctx->adpl_over_usb_available, 0); + return ret; + default: + IPA_MPM_ERR("mhip_client = %d not supported\n", mhip_client); + return 0; + } + + status = ipa_mpm_start_stop_mhip_chan(IPA_MPM_MHIP_CHAN_UL, + probe_id, MPM_MHIP_STOP); + + switch (status) { + case MHIP_STATUS_SUCCESS: + case MHIP_STATUS_NO_OP: + case MHIP_STATUS_EP_NOT_READY: + ipa_mpm_change_teth_state(probe_id, IPA_MPM_TETH_INIT); + /* De-register for BW indication from Q6*/ + if (atomic_read(&ipa_mpm_ctx->active_teth_count) >= 1) { + if (!ipa3_qmi_reg_dereg_for_bw(false)) + IPA_MPM_DBG( + "Failed De-rgstrng QMI BW Indctn,might be SSR"); + } else { + IPA_MPM_ERR( + "Active tethe count is %d", + atomic_read(&ipa_mpm_ctx->active_teth_count)); + } + break; + case MHIP_STATUS_FAIL: + case MHIP_STATUS_BAD_STATE: + case MHIP_STATUS_EP_NOT_FOUND: + IPA_MPM_ERR("UL chan cant be started err =%d\n", status); + ipa_mpm_vote_unvote_pcie_clk(CLK_OFF, probe_id, + false, &is_acted); + return -EFAULT; + default: + IPA_MPM_ERR("Err not found\n"); + break; + } + + ret = ipa_mpm_vote_unvote_pcie_clk(CLK_OFF, probe_id, + false, &is_acted); + + if (ret) { + IPA_MPM_ERR("Error cloking off PCIe clk, err = %d\n", ret); + return ret; + } + + ipa_mpm_ctx->md[probe_id].mhip_client = IPA_MPM_MHIP_NONE; + + return ret; +} +EXPORT_SYMBOL(ipa_mpm_mhip_xdci_pipe_disable); + +static int ipa_mpm_populate_smmu_info(struct platform_device *pdev) +{ + struct ipa_smmu_in_params smmu_in; + struct ipa_smmu_out_params smmu_out; + u32 carved_iova_ap_mapping[2]; + struct ipa_smmu_cb_ctx *cb; + struct ipa_smmu_cb_ctx *ap_cb = ipa3_get_smmu_ctx(IPA_SMMU_CB_AP); + int ret = 0; + + if (ipa_mpm_ctx->carved_smmu_cb.valid) { + IPA_MPM_DBG("SMMU Context allocated, returning ..\n"); + return ret; + } + + cb = &ipa_mpm_ctx->carved_smmu_cb; + + /* get IPA SMMU enabled status */ + smmu_in.smmu_client = IPA_SMMU_AP_CLIENT; + if (ipa_get_smmu_params(&smmu_in, &smmu_out)) + ipa_mpm_ctx->dev_info.ipa_smmu_enabled = false; + else + ipa_mpm_ctx->dev_info.ipa_smmu_enabled = + smmu_out.smmu_enable; + + /* get cache_coherent enable or not */ + ipa_mpm_ctx->dev_info.is_cache_coherent = ap_cb->is_cache_coherent; + if (of_property_read_u32_array(pdev->dev.of_node, "qcom,iova-mapping", + carved_iova_ap_mapping, 2)) { + IPA_MPM_ERR("failed to read of_node %s\n", + "qcom,mpm-iova-mapping"); + return -EINVAL; + } + ipa_mpm_ctx->dev_info.pcie_smmu_enabled = true; + + if (ipa_mpm_ctx->dev_info.ipa_smmu_enabled != + ipa_mpm_ctx->dev_info.pcie_smmu_enabled) { + IPA_MPM_DBG("PCIE/IPA SMMU config mismatch\n"); + return -EINVAL; + } + + cb->va_start = carved_iova_ap_mapping[0]; + cb->va_size = carved_iova_ap_mapping[1]; + cb->va_end = cb->va_start + cb->va_size; + + if (cb->va_end >= ap_cb->va_start) { + IPA_MPM_ERR("MPM iommu and AP overlap addr 0x%lx\n", + cb->va_start); + ipa_assert(); + return -EFAULT; + } + + cb->dev = ipa_mpm_ctx->dev_info.dev; + cb->valid = true; + cb->next_addr = cb->va_start; + + if (dma_set_mask_and_coherent(ipa_mpm_ctx->dev_info.dev, + DMA_BIT_MASK(64))) { + IPA_MPM_ERR("setting DMA mask to 64 failed.\n"); + return -EINVAL; + } + + return ret; +} + +static int ipa_mpm_probe(struct platform_device *pdev) +{ + int ret = 0; + int i = 0; + int idx = 0; + + IPA_MPM_FUNC_ENTRY(); + + if (ipa_mpm_ctx) { + IPA_MPM_DBG("MPM is already probed, returning\n"); + return 0; + } + + ret = ipa_register_ipa_ready_cb(ipa_mpm_ipa3_ready_cb, (void *)pdev); + /* + * If we received -EEXIST, IPA has initialized. So we need + * to continue the probing process. + */ + if (!ret) { + IPA_MPM_DBG("IPA not ready yet, registering callback\n"); + return ret; + } + IPA_MPM_DBG("IPA is ready, continue with probe\n"); + + ipa_mpm_ctx = kzalloc(sizeof(*ipa_mpm_ctx), GFP_KERNEL); + + if (!ipa_mpm_ctx) + return -ENOMEM; + + for (i = 0; i < IPA_MPM_MHIP_CH_ID_MAX; i++) { + mutex_init(&ipa_mpm_ctx->md[i].mutex); + mutex_init(&ipa_mpm_ctx->md[i].mhi_mutex); + } + + ipa_mpm_ctx->dev_info.pdev = pdev; + ipa_mpm_ctx->dev_info.dev = &pdev->dev; + + ipa_mpm_init_mhip_channel_info(); + + /* Read the MHI CH/ER DB address from DT. */ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) + if (of_property_read_u32(pdev->dev.of_node, "qcom,mhi-chdb-base", + &ipa_mpm_ctx->dev_info.chdb_base)) { + IPA_MPM_ERR("failed to read qcom,mhi-chdb-base\n"); + goto fail_probe; + } + IPA_MPM_DBG("chdb-base=0x%x\n", ipa_mpm_ctx->dev_info.chdb_base); + + if (of_property_read_u32(pdev->dev.of_node, "qcom,mhi-erdb-base", + &ipa_mpm_ctx->dev_info.erdb_base)) { + IPA_MPM_ERR("failed to read qcom,mhi-erdb-base\n"); + goto fail_probe; + } + IPA_MPM_DBG("erdb-base=0x%x\n", ipa_mpm_ctx->dev_info.erdb_base); +#endif + + ret = ipa_mpm_populate_smmu_info(pdev); + + if (ret) { + IPA_MPM_DBG("SMMU Config failed\n"); + goto fail_probe; + } + + atomic_set(&ipa_mpm_ctx->ipa_clk_total_cnt, 0); + atomic_set(&ipa_mpm_ctx->pcie_clk_total_cnt, 0); + atomic_set(&ipa_mpm_ctx->flow_ctrl_mask, 0); + atomic_set(&ipa_mpm_ctx->active_teth_count, 0); + atomic_set(&ipa_mpm_ctx->voted_before, 1); + + for (idx = 0; idx < IPA_MPM_MHIP_CH_ID_MAX; idx++) { + ipa_mpm_ctx->md[idx].ul_prod.gsi_state = GSI_INIT; + ipa_mpm_ctx->md[idx].dl_cons.gsi_state = GSI_INIT; + atomic_set(&ipa_mpm_ctx->md[idx].clk_cnt.ipa_clk_cnt, 0); + atomic_set(&ipa_mpm_ctx->md[idx].clk_cnt.pcie_clk_cnt, 0); + } + + ret = mhi_driver_register(&mhi_driver); + if (ret) { + IPA_MPM_ERR("mhi_driver_register failed %d\n", ret); + goto fail_probe; + } + IPA_MPM_FUNC_EXIT(); + return 0; + +fail_probe: + kfree(ipa_mpm_ctx); + ipa_mpm_ctx = NULL; + return -EFAULT; +} + +static int ipa_mpm_remove(struct platform_device *pdev) +{ + IPA_MPM_FUNC_ENTRY(); + + mhi_driver_unregister(&mhi_driver); + IPA_MPM_FUNC_EXIT(); + return 0; +} + +static const struct of_device_id ipa_mpm_dt_match[] = { + { .compatible = "qcom,ipa-mpm" }, + {}, +}; +MODULE_DEVICE_TABLE(of, ipa_mpm_dt_match); + +static struct platform_driver ipa_ipa_mpm_driver = { + .driver = { + .name = "ipa_mpm", + .of_match_table = ipa_mpm_dt_match, + }, + .probe = ipa_mpm_probe, + .remove = ipa_mpm_remove, +}; + +/** + * ipa_mpm_init() - Registers ipa_mpm as a platform device for a APQ + * + * This function is called after bootup for APQ device. + * ipa_mpm will register itself as a platform device, and probe + * function will get called. + * + * Return: None + */ +int ipa_mpm_init(void) +{ + IPA_MPM_DBG("register ipa_mpm platform device\n"); + return platform_driver_register(&ipa_ipa_mpm_driver); +} + +void ipa_mpm_exit(void) +{ + IPA_MPM_DBG("unregister ipa_mpm platform device\n"); + platform_driver_unregister(&ipa_ipa_mpm_driver); +} + +/** + * ipa3_is_mhip_offload_enabled() - check if IPA MPM module was initialized + * successfully. If it is initialized, MHIP is enabled for teth + * + * Return value: 1 for yes; 0 for no + */ +int ipa3_is_mhip_offload_enabled(void) +{ + if (ipa_mpm_ctx == NULL) + return 0; + else + return 1; +} +EXPORT_SYMBOL(ipa3_is_mhip_offload_enabled); + +int ipa_mpm_panic_handler(char *buf, int size) +{ + int i; + int cnt = 0; + + cnt = scnprintf(buf, size, + "\n---- MHIP Active Clients Table ----\n"); + cnt += scnprintf(buf + cnt, size - cnt, + "Total PCIe active clients count: %d\n", + atomic_read(&ipa_mpm_ctx->pcie_clk_total_cnt)); + cnt += scnprintf(buf + cnt, size - cnt, + "Total IPA active clients count: %d\n", + atomic_read(&ipa_mpm_ctx->ipa_clk_total_cnt)); + + for (i = 0; i < IPA_MPM_MHIP_CH_ID_MAX; i++) { + cnt += scnprintf(buf + cnt, size - cnt, + "client id: %d ipa vote cnt: %d pcie vote cnt\n", i, + atomic_read(&ipa_mpm_ctx->md[i].clk_cnt.ipa_clk_cnt), + atomic_read(&ipa_mpm_ctx->md[i].clk_cnt.pcie_clk_cnt)); + } + return cnt; +} + +/** + * ipa3_get_mhip_gsi_stats() - Query MHIP gsi stats from uc + * @stats: [inout] stats blob from client populated by driver + * + * Returns: 0 on success, negative on failure + * + * @note Cannot be called from atomic context + * + */ +int ipa3_get_mhip_gsi_stats(struct ipa_uc_dbg_ring_stats *stats) +{ + int i; + + if (!ipa3_ctx->mhip_ctx.dbg_stats.uc_dbg_stats_mmio) { + IPAERR("bad parms NULL mhip_gsi_stats_mmio\n"); + return -EINVAL; + } + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + for (i = 0; i < MAX_MHIP_CHANNELS; i++) { + stats->u.ring[i].ringFull = ioread32( + ipa3_ctx->mhip_ctx.dbg_stats.uc_dbg_stats_mmio + + i * IPA3_UC_DEBUG_STATS_OFF + + IPA3_UC_DEBUG_STATS_RINGFULL_OFF); + stats->u.ring[i].ringEmpty = ioread32( + ipa3_ctx->mhip_ctx.dbg_stats.uc_dbg_stats_mmio + + i * IPA3_UC_DEBUG_STATS_OFF + + IPA3_UC_DEBUG_STATS_RINGEMPTY_OFF); + stats->u.ring[i].ringUsageHigh = ioread32( + ipa3_ctx->mhip_ctx.dbg_stats.uc_dbg_stats_mmio + + i * IPA3_UC_DEBUG_STATS_OFF + + IPA3_UC_DEBUG_STATS_RINGUSAGEHIGH_OFF); + stats->u.ring[i].ringUsageLow = ioread32( + ipa3_ctx->mhip_ctx.dbg_stats.uc_dbg_stats_mmio + + i * IPA3_UC_DEBUG_STATS_OFF + + IPA3_UC_DEBUG_STATS_RINGUSAGELOW_OFF); + stats->u.ring[i].RingUtilCount = ioread32( + ipa3_ctx->mhip_ctx.dbg_stats.uc_dbg_stats_mmio + + i * IPA3_UC_DEBUG_STATS_OFF + + IPA3_UC_DEBUG_STATS_RINGUTILCOUNT_OFF); + } + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + + + return 0; +} + +/** + * ipa3_mpm_enable_adpl_over_odl() - Enable or disable ADPL over ODL + * @enable: true for enable, false for disable + * + * Returns: 0 on success, negative on failure + * + */ +int ipa3_mpm_enable_adpl_over_odl(bool enable) +{ + int ret; + bool is_acted = true; + + IPA_MPM_FUNC_ENTRY(); + + if (!ipa3_is_mhip_offload_enabled()) { + IPA_MPM_ERR("mpm ctx is NULL\n"); + return -EPERM; + } + + if (enable) { + /* inc clk count and set DMA to ODL */ + IPA_MPM_DBG("mpm enabling ADPL over ODL\n"); + + ret = ipa_mpm_vote_unvote_pcie_clk(CLK_ON, + IPA_MPM_MHIP_CH_ID_2, false, &is_acted); + if (ret) { + IPA_MPM_ERR("Err %d cloking on PCIe clk\n", ret); + return ret; + } + + ret = ipa_mpm_set_dma_mode(IPA_CLIENT_MHI_PRIME_DPL_PROD, + IPA_CLIENT_ODL_DPL_CONS, false); + if (ret) { + IPA_MPM_ERR("MPM failed to set dma mode to ODL\n"); + if (is_acted) + ipa_mpm_vote_unvote_pcie_clk(CLK_OFF, + IPA_MPM_MHIP_CH_ID_2, + false, + &is_acted); + return ret; + } + + /*start remote mhip-dpl ch */ + ret = ipa_mpm_start_stop_remote_mhip_chan(IPA_MPM_MHIP_CH_ID_2, + MPM_MHIP_START, false); + if (ret) { + /** + * This can fail only when modem is in SSR state. + * Eventually there would be a remove callback, + * so return a failure. + */ + IPA_MPM_ERR("MHIP remote chan start fail = %d\n", + ret); + return ret; + } + IPA_MPM_DBG("MHIP remote chan started(id=%d)\n", + IPA_MPM_MHIP_CH_ID_2); + atomic_set(&ipa_mpm_ctx->adpl_over_odl_available, 1); + + ipa_mpm_change_teth_state(IPA_MPM_MHIP_CH_ID_2, + IPA_MPM_TETH_CONNECTED); + } else { + /* stop remote mhip-dpl ch if adpl not enable */ + if (!atomic_read(&ipa_mpm_ctx->adpl_over_usb_available)) { + ret = ipa_mpm_start_stop_remote_mhip_chan( + IPA_MPM_MHIP_CH_ID_2, MPM_MHIP_STOP, false); + if (ret) { + /** + * This can fail only when modem is in SSR state. + * Eventually there would be a remove callback, + * so return a failure. + */ + IPA_MPM_ERR("MHIP remote chan stop fail = %d\n", + ret); + return ret; + } + IPA_MPM_DBG("MHIP remote channels are stopped(id=%d)\n", + IPA_MPM_MHIP_CH_ID_2); + } + atomic_set(&ipa_mpm_ctx->adpl_over_odl_available, 0); + + /* dec clk count and set DMA to USB */ + IPA_MPM_DBG("mpm disabling ADPL over ODL\n"); + ret = ipa_mpm_vote_unvote_pcie_clk(CLK_OFF, + IPA_MPM_MHIP_CH_ID_2, + false, + &is_acted); + if (ret) { + IPA_MPM_ERR("Err %d cloking off PCIe clk\n", + ret); + return ret; + } + + ret = ipa_mpm_set_dma_mode(IPA_CLIENT_MHI_PRIME_DPL_PROD, + IPA_CLIENT_USB_DPL_CONS, false); + if (ret) { + IPA_MPM_ERR("MPM failed to set dma mode to USB\n"); + if (ipa_mpm_vote_unvote_pcie_clk(CLK_ON, + IPA_MPM_MHIP_CH_ID_2, + false, + &is_acted)) + IPA_MPM_ERR("Err clocking on pcie\n"); + return ret; + } + + /* If USB is not available then reset teth state */ + if (atomic_read(&ipa_mpm_ctx->adpl_over_usb_available)) { + IPA_MPM_DBG("mpm enabling ADPL over USB\n"); + } else { + ipa_mpm_change_teth_state(IPA_MPM_MHIP_CH_ID_2, + IPA_MPM_TETH_INIT); + IPA_MPM_DBG("USB disconnected. ADPL on standby\n"); + } + } + + IPA_MPM_FUNC_EXIT(); + return ret; +} + +int ipa3_qmi_reg_dereg_for_bw(bool bw_reg) +{ + int rt; + + if (bw_reg) { + atomic_inc(&ipa_mpm_ctx->active_teth_count); + if (atomic_read(&ipa_mpm_ctx->active_teth_count) == 1) { + rt = ipa3_qmi_req_ind(true); + if (rt < 0) { + IPA_MPM_ERR("QMI BW regst fail, rt = %d", rt); + atomic_dec(&ipa_mpm_ctx->active_teth_count); + /* Using voted_before for keeping track of + * request successful or not, so that we don't + * request for devote when tether turned off + */ + atomic_set(&ipa_mpm_ctx->voted_before, 0); + return false; + } + IPA_MPM_DBG("QMI BW regst success"); + } else { + IPA_MPM_DBG("bw_change to %d no-op, teth_count = %d", + bw_reg, + atomic_read(&ipa_mpm_ctx->active_teth_count)); + } + } else { + atomic_dec(&ipa_mpm_ctx->active_teth_count); + if (atomic_read(&ipa_mpm_ctx->active_teth_count) == 0) { + if (atomic_read(&ipa_mpm_ctx->voted_before) == 0) { + atomic_inc(&ipa_mpm_ctx->active_teth_count); + atomic_set(&ipa_mpm_ctx->voted_before, 1); + return false; + } + rt = ipa3_qmi_req_ind(false); + if (rt < 0) { + IPA_MPM_ERR("QMI BW de-regst fail, rt= %d", rt); + return false; + } + IPA_MPM_DBG("QMI BW De-regst success"); + } else { + IPA_MPM_DBG("bw_change to %d no-op, teth_count = %d", + bw_reg, + atomic_read(&ipa_mpm_ctx->active_teth_count)); + } + } + return true; +} + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("MHI Proxy Manager Driver"); diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_nat.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_nat.c new file mode 100644 index 0000000000..d352fbbeb4 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_nat.c @@ -0,0 +1,2548 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) +#include +#else /* Legacy */ +#include +#endif +#include "ipa_i.h" +#include "ipahal.h" +#include "ipahal_nat.h" + + +/* + * The following for adding code (ie. for EMULATION) not found on x86. + */ +#if defined(CONFIG_IPA_EMULATION) +# include "ipa_emulation_stubs.h" +#endif + +#define IPA_NAT_PHYS_MEM_OFFSET IPA_MEM_PART(nat_tbl_ofst) +#define IPA_NAT_PHYS_MEM_SIZE IPA_RAM_NAT_SIZE + +#define IPA_IPV6CT_PHYS_MEM_OFFSET 0 +#define IPA_IPV6CT_PHYS_MEM_SIZE IPA_RAM_IPV6CT_SIZE + +#define IPA_NAT_IPV6CT_TEMP_MEM_SIZE 128 + +#define IPA_NAT_MAX_NUM_OF_INIT_CMD_DESC 4 +#define IPA_IPV6CT_MAX_NUM_OF_INIT_CMD_DESC 3 +#define IPA_MAX_NUM_OF_TABLE_DMA_CMD_DESC 5 + +/* + * The base table max entries is limited by index into table 13 bits number. + * Limit the memory size required by user to prevent kernel memory starvation + */ +#define IPA_TABLE_MAX_ENTRIES 8192 +#define MAX_ALLOC_NAT_SIZE(size) (IPA_TABLE_MAX_ENTRIES * size) + +#define IPA_VALID_TBL_INDEX(ti) \ + ((ti) == 0) + +enum ipa_nat_ipv6ct_table_type { + IPA_NAT_BASE_TBL = 0, + IPA_NAT_EXPN_TBL = 1, + IPA_NAT_INDX_TBL = 2, + IPA_NAT_INDEX_EXPN_TBL = 3, + IPA_IPV6CT_BASE_TBL = 4, + IPA_IPV6CT_EXPN_TBL = 5 +}; + +static bool sram_compatible; + +static vm_fault_t ipa3_nat_ipv6ct_vma_fault_remap(struct vm_fault *vmf) +{ + vmf->page = NULL; + + IPADBG("\n"); + return VM_FAULT_SIGBUS; +} + +/* VMA related file operations functions */ +static const struct vm_operations_struct ipa3_nat_ipv6ct_remap_vm_ops = { + .fault = ipa3_nat_ipv6ct_vma_fault_remap, +}; + + +static inline const char *ipa3_nat_mem_in_as_str( + enum ipa3_nat_mem_in nmi) +{ + switch (nmi) { + case IPA_NAT_MEM_IN_DDR: + return "IPA_NAT_MEM_IN_DDR"; + case IPA_NAT_MEM_IN_SRAM: + return "IPA_NAT_MEM_IN_SRAM"; + default: + break; + } + return "INVALID_MEM_TYPE"; +} + +static inline char *ipa_ioc_v4_nat_init_as_str( + struct ipa_ioc_v4_nat_init *ptr, + char *buf, + uint32_t buf_sz) +{ + if (ptr && buf && buf_sz) { + snprintf( + buf, buf_sz, + "V4 NAT INIT: tbl_index(0x%02X) ipv4_rules_offset(0x%08X) expn_rules_offset(0x%08X) index_offset(0x%08X) index_expn_offset(0x%08X) table_entries(0x%04X) expn_table_entries(0x%04X) ip_addr(0x%08X)", + ptr->tbl_index, + ptr->ipv4_rules_offset, + ptr->expn_rules_offset, + ptr->index_offset, + ptr->index_expn_offset, + ptr->table_entries, + ptr->expn_table_entries, + ptr->ip_addr); + } + return buf; +} + +static int ipa3_nat_ipv6ct_open(struct inode *inode, struct file *filp) +{ + struct ipa3_nat_ipv6ct_common_mem *dev; + + IPADBG("\n"); + dev = container_of(inode->i_cdev, + struct ipa3_nat_ipv6ct_common_mem, cdev); + filp->private_data = dev; + IPADBG("return\n"); + + return 0; +} + +static int ipa3_nat_ipv6ct_mmap( + struct file *filp, + struct vm_area_struct *vma) +{ + struct ipa3_nat_ipv6ct_common_mem *dev = + (struct ipa3_nat_ipv6ct_common_mem *)filp->private_data; + unsigned long vsize = vma->vm_end - vma->vm_start; + struct ipa_smmu_cb_ctx *cb = ipa3_get_smmu_ctx(IPA_SMMU_CB_AP); + struct ipa3_nat_mem *nm_ptr; + struct ipa3_nat_mem_loc_data *mld_ptr; + enum ipa3_nat_mem_in nmi; + + int result = 0; + + IPADBG("In\n"); + + if (!dev->is_dev_init) { + IPAERR("Attempt to mmap %s before dev init\n", + dev->name); + result = -EPERM; + goto bail; + } + + mutex_lock(&dev->lock); + + /* + * Check if no smmu or non dma coherent + */ + if (cb && cb->dev && (!cb->valid || !dev_is_dma_coherent(cb->dev))) { + + IPADBG("Either smmu valid=%u and/or DMA coherent=%u false\n", + cb->valid, !dev_is_dma_coherent(cb->dev)); + + vma->vm_page_prot = + pgprot_noncached(vma->vm_page_prot); + } + + if (dev->is_nat_mem) { + + nm_ptr = (struct ipa3_nat_mem *) dev; + nmi = nm_ptr->last_alloc_loc; + + if (!IPA_VALID_NAT_MEM_IN(nmi)) { + IPAERR_RL("Bad ipa3_nat_mem_in type\n"); + result = -EPERM; + goto unlock; + } + + mld_ptr = &nm_ptr->mem_loc[nmi]; + + if (!mld_ptr->vaddr) { + IPAERR_RL( + "Attempt to mmap %s before the memory allocation\n", + dev->name); + result = -EPERM; + goto unlock; + } + + if (mld_ptr->is_mapped) { + IPAERR("%s already mapped, only 1 mapping supported\n", + dev->name); + result = -EINVAL; + goto unlock; + } + + if (nmi == IPA_NAT_MEM_IN_SRAM) { + if (dev->phys_mem_size == 0 || + dev->phys_mem_size > vsize) { + IPAERR_RL( + "%s err vsize(0x%X) phys_mem_size(0x%X)\n", + dev->name, vsize, dev->phys_mem_size); + result = -EINVAL; + goto unlock; + } + } + + mld_ptr->base_address = NULL; + + IPADBG("Mapping V4 NAT: %s\n", + ipa3_nat_mem_in_as_str(nmi)); + + if (nmi == IPA_NAT_MEM_IN_DDR) { + + IPADBG("map sz=0x%zx -> vma size=0x%08x\n", + mld_ptr->table_alloc_size, + vsize); + + result = + dma_mmap_coherent( + ipa3_ctx->pdev, + vma, + mld_ptr->vaddr, + mld_ptr->dma_handle, + mld_ptr->table_alloc_size); + + if (result) { + IPAERR( + "dma_mmap_coherent failed. Err:%d\n", + result); + goto unlock; + } + + mld_ptr->base_address = mld_ptr->vaddr; + + } else { /* nmi == IPA_NAT_MEM_IN_SRAM */ + + IPADBG("map phys_mem_size(0x%08X) -> vma sz(0x%08X)\n", + dev->phys_mem_size, vsize); + + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); + + result = vm_iomap_memory( + vma, mld_ptr->phys_addr, dev->phys_mem_size); + + if (result) { + IPAERR("vm_iomap_memory failed. Err:%d\n", + result); + goto unlock; + } + + mld_ptr->base_address = mld_ptr->vaddr; + } + + mld_ptr->is_mapped = true; + + } else { /* dev->is_ipv6ct_mem */ + + if (!dev->vaddr) { + IPAERR_RL( + "Attempt to mmap %s before the memory allocation\n", + dev->name); + result = -EPERM; + goto unlock; + } + + if (dev->is_mapped) { + IPAERR("%s already mapped, only 1 mapping supported\n", + dev->name); + result = -EINVAL; + goto unlock; + } + + dev->base_address = NULL; + + IPADBG("Mapping V6 CT: %s\n", + ipa3_nat_mem_in_as_str(IPA_NAT_MEM_IN_DDR)); + + IPADBG("map sz=0x%zx -> vma size=0x%08x\n", + dev->table_alloc_size, + vsize); + + result = + dma_mmap_coherent( + ipa3_ctx->pdev, + vma, + dev->vaddr, + dev->dma_handle, + dev->table_alloc_size); + + if (result) { + IPAERR("dma_mmap_coherent failed. Err:%d\n", result); + goto unlock; + } + + dev->base_address = dev->vaddr; + + dev->is_mapped = true; + } + + vma->vm_ops = &ipa3_nat_ipv6ct_remap_vm_ops; + +unlock: + mutex_unlock(&dev->lock); + +bail: + IPADBG("Out\n"); + + return result; +} + +static const struct file_operations ipa3_nat_ipv6ct_fops = { + .owner = THIS_MODULE, + .open = ipa3_nat_ipv6ct_open, + .mmap = ipa3_nat_ipv6ct_mmap +}; + +/** + * ipa3_allocate_nat_ipv6ct_tmp_memory() - Allocates the NAT\IPv6CT temp memory + */ +static struct ipa3_nat_ipv6ct_tmp_mem *ipa3_nat_ipv6ct_allocate_tmp_memory(void) +{ + struct ipa3_nat_ipv6ct_tmp_mem *tmp_mem; + gfp_t gfp_flags = GFP_KERNEL | __GFP_ZERO; + + IPADBG("\n"); + + tmp_mem = kzalloc(sizeof(*tmp_mem), GFP_KERNEL); + if (tmp_mem == NULL) + return NULL; + + tmp_mem->vaddr = + dma_alloc_coherent(ipa3_ctx->pdev, IPA_NAT_IPV6CT_TEMP_MEM_SIZE, + &tmp_mem->dma_handle, gfp_flags); + if (tmp_mem->vaddr == NULL) + goto bail_tmp_mem; + + IPADBG("IPA successfully allocated temp memory\n"); + return tmp_mem; + +bail_tmp_mem: + kfree(tmp_mem); + return NULL; +} + +static int ipa3_nat_ipv6ct_init_device( + struct ipa3_nat_ipv6ct_common_mem *dev, + const char *name, + u32 phys_mem_size, + u32 phys_mem_ofst, + struct ipa3_nat_ipv6ct_tmp_mem *tmp_mem) +{ + int result = 0; + + IPADBG("In: Init of %s\n", name); + + mutex_init(&dev->lock); + + dev->is_nat_mem = IS_NAT_MEM_DEV(dev); + dev->is_ipv6ct_mem = IS_IPV6CT_MEM_DEV(dev); + + if (strnlen(name, IPA_DEV_NAME_MAX_LEN) == IPA_DEV_NAME_MAX_LEN) { + IPAERR("device name is too long\n"); + result = -ENODEV; + goto bail; + } + + strlcpy(dev->name, name, IPA_DEV_NAME_MAX_LEN); + + dev->class = class_create(THIS_MODULE, name); + + if (IS_ERR(dev->class)) { + IPAERR("unable to create the class for %s\n", name); + result = -ENODEV; + goto bail; + } + + result = alloc_chrdev_region(&dev->dev_num, 0, 1, name); + + if (result) { + IPAERR("alloc_chrdev_region err. for %s\n", name); + result = -ENODEV; + goto alloc_chrdev_region_fail; + } + + dev->dev = device_create(dev->class, NULL, dev->dev_num, NULL, name); + + if (IS_ERR(dev->dev)) { + IPAERR("device_create err:%ld\n", PTR_ERR(dev->dev)); + result = -ENODEV; + goto device_create_fail; + } + + cdev_init(&dev->cdev, &ipa3_nat_ipv6ct_fops); + + dev->cdev.owner = THIS_MODULE; + + mutex_lock(&dev->lock); + + result = cdev_add(&dev->cdev, dev->dev_num, 1); + + if (result) { + IPAERR("cdev_add err=%d\n", -result); + goto cdev_add_fail; + } + + dev->tmp_mem = tmp_mem; + dev->phys_mem_size = phys_mem_size; + dev->phys_mem_ofst = phys_mem_ofst; + dev->is_dev_init = true; + + mutex_unlock(&dev->lock); + + IPADBG("ipa dev %s added successfully. major:%d minor:%d\n", name, + MAJOR(dev->dev_num), MINOR(dev->dev_num)); + + result = 0; + + goto bail; + +cdev_add_fail: + mutex_unlock(&dev->lock); + device_destroy(dev->class, dev->dev_num); + +device_create_fail: + unregister_chrdev_region(dev->dev_num, 1); + +alloc_chrdev_region_fail: + class_destroy(dev->class); + +bail: + IPADBG("Out\n"); + + return result; +} + +static void ipa3_nat_ipv6ct_destroy_device( + struct ipa3_nat_ipv6ct_common_mem *dev) +{ + IPADBG("In\n"); + + mutex_lock(&dev->lock); + + if (dev->tmp_mem) { + if (ipa3_ctx->nat_mem.is_tmp_mem_allocated) { + dma_free_coherent( + ipa3_ctx->pdev, + IPA_NAT_IPV6CT_TEMP_MEM_SIZE, + dev->tmp_mem->vaddr, + dev->tmp_mem->dma_handle); + kfree(dev->tmp_mem); + dev->tmp_mem = NULL; + ipa3_ctx->nat_mem.is_tmp_mem_allocated = false; + } + dev->tmp_mem = NULL; + } + + device_destroy(dev->class, dev->dev_num); + + unregister_chrdev_region(dev->dev_num, 1); + + class_destroy(dev->class); + + dev->is_dev_init = false; + + mutex_unlock(&dev->lock); + + IPADBG("Out\n"); +} + +/** + * ipa3_nat_ipv6ct_init_devices() - Initialize the NAT and IPv6CT devices + * + * Called during IPA init to create memory device + * + * Returns: 0 on success, negative on failure + */ +int ipa3_nat_ipv6ct_init_devices(void) +{ + struct ipa3_nat_ipv6ct_tmp_mem *tmp_mem; + int result; + + IPADBG("\n"); + + /* + * Allocate NAT/IPv6CT temporary memory. The memory is never deleted, + * because provided to HW once NAT or IPv6CT table is deleted. + */ + tmp_mem = ipa3_nat_ipv6ct_allocate_tmp_memory(); + + if (tmp_mem == NULL) { + IPAERR("unable to allocate tmp_mem\n"); + return -ENOMEM; + } + ipa3_ctx->nat_mem.is_tmp_mem_allocated = true; + + if (ipa3_nat_ipv6ct_init_device( + &ipa3_ctx->nat_mem.dev, + IPA_NAT_DEV_NAME, + IPA_NAT_PHYS_MEM_SIZE, + IPA_NAT_PHYS_MEM_OFFSET, + tmp_mem)) { + IPAERR("unable to create nat device\n"); + result = -ENODEV; + goto fail_init_nat_dev; + } + + if ((ipa3_ctx->ipa_hw_type >= IPA_HW_v4_0) && + ipa3_nat_ipv6ct_init_device( + &ipa3_ctx->ipv6ct_mem.dev, + IPA_IPV6CT_DEV_NAME, + IPA_IPV6CT_PHYS_MEM_SIZE, + IPA_IPV6CT_PHYS_MEM_OFFSET, + tmp_mem)) { + IPAERR("unable to create IPv6CT device\n"); + result = -ENODEV; + goto fail_init_ipv6ct_dev; + } + + return 0; + +fail_init_ipv6ct_dev: + ipa3_nat_ipv6ct_destroy_device(&ipa3_ctx->nat_mem.dev); +fail_init_nat_dev: + if (tmp_mem != NULL && ipa3_ctx->nat_mem.is_tmp_mem_allocated) { + dma_free_coherent(ipa3_ctx->pdev, IPA_NAT_IPV6CT_TEMP_MEM_SIZE, + tmp_mem->vaddr, tmp_mem->dma_handle); + kfree(tmp_mem); + ipa3_ctx->nat_mem.is_tmp_mem_allocated = false; + } + return result; +} + +/** + * ipa3_nat_ipv6ct_destroy_devices() - destroy the NAT and IPv6CT devices + * + * Called during IPA init to destroy nat device + */ +void ipa3_nat_ipv6ct_destroy_devices(void) +{ + ipa3_nat_ipv6ct_destroy_device(&ipa3_ctx->nat_mem.dev); + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_0) + ipa3_nat_ipv6ct_destroy_device(&ipa3_ctx->ipv6ct_mem.dev); +} + +static int ipa3_nat_ipv6ct_allocate_mem( + struct ipa3_nat_ipv6ct_common_mem *dev, + struct ipa_ioc_nat_ipv6ct_table_alloc *table_alloc, + enum ipahal_nat_type nat_type) +{ + gfp_t gfp_flags = GFP_KERNEL | __GFP_ZERO; + size_t nat_entry_size; + + struct ipa3_nat_mem *nm_ptr; + struct ipa3_nat_mem_loc_data *mld_ptr; + uintptr_t tmp_ptr; + + int result = 0; + + IPADBG("In: Requested alloc size %zu for %s\n", + table_alloc->size, dev->name); + + if (!table_alloc->size) { + IPAERR_RL("Invalid Parameters\n"); + result = -EPERM; + goto bail; + } + + if (!dev->is_dev_init) { + IPAERR("%s hasn't been initialized\n", dev->name); + result = -EPERM; + goto bail; + } + + if ((dev->is_nat_mem && nat_type != IPAHAL_NAT_IPV4) || + (dev->is_ipv6ct_mem && nat_type != IPAHAL_NAT_IPV6CT)) { + IPAERR("%s dev type(%s) and nat_type(%s) mismatch\n", + dev->name, + (dev->is_nat_mem) ? "V4" : "V6", + ipahal_nat_type_str(nat_type)); + result = -EPERM; + goto bail; + } + + ipahal_nat_entry_size(nat_type, &nat_entry_size); + + if (table_alloc->size > MAX_ALLOC_NAT_SIZE(nat_entry_size)) { + IPAERR("Trying allocate more size = %zu, Max allowed = %zu\n", + table_alloc->size, + MAX_ALLOC_NAT_SIZE(nat_entry_size)); + result = -EPERM; + goto bail; + } + + if (nat_type == IPAHAL_NAT_IPV4) { + + nm_ptr = (struct ipa3_nat_mem *) dev; + + if (sram_compatible && table_alloc->size <= IPA_NAT_PHYS_MEM_SIZE) { + /* + * CAN fit in SRAM, hence we'll use SRAM... + * And SRAM allowed + */ + IPADBG("V4 NAT with size 0x%08X will reside in: %s\n", + table_alloc->size, + ipa3_nat_mem_in_as_str(IPA_NAT_MEM_IN_SRAM)); + + if (nm_ptr->sram_in_use) { + IPAERR("Memory already allocated\n"); + result = -EPERM; + goto bail; + } + + mld_ptr = &nm_ptr->mem_loc[IPA_NAT_MEM_IN_SRAM]; + + mld_ptr->table_alloc_size = table_alloc->size; + + mld_ptr->phys_addr = + ipa3_ctx->ipa_wrapper_base + + ipa3_ctx->ctrl->ipa_reg_base_ofst + + ipahal_get_reg_n_ofst( + IPA_SW_AREA_RAM_DIRECT_ACCESS_n, + 0) + + IPA_NAT_PHYS_MEM_OFFSET; + + mld_ptr->io_vaddr = ioremap( + mld_ptr->phys_addr, IPA_NAT_PHYS_MEM_SIZE); + + if (mld_ptr->io_vaddr == NULL) { + IPAERR("ioremap failed\n"); + result = -ENOMEM; + goto bail; + } + + tmp_ptr = (uintptr_t) mld_ptr->io_vaddr; + + mld_ptr->vaddr = (void *) tmp_ptr; + + nm_ptr->sram_in_use = true; + nm_ptr->last_alloc_loc = IPA_NAT_MEM_IN_SRAM; + + } else { + + /* + * CAN NOT fit in SRAM OR SRAM not allowed, hence we'll allocate DDR... + */ + IPADBG("V4 NAT with size 0x%08X will reside in: %s\n", + table_alloc->size, + ipa3_nat_mem_in_as_str(IPA_NAT_MEM_IN_DDR)); + + if (nm_ptr->ddr_in_use) { + IPAERR("Memory already allocated\n"); + result = -EPERM; + goto bail; + } + + mld_ptr = &nm_ptr->mem_loc[IPA_NAT_MEM_IN_DDR]; + + mld_ptr->table_alloc_size = table_alloc->size; + + mld_ptr->vaddr = + dma_alloc_coherent( + ipa3_ctx->pdev, + mld_ptr->table_alloc_size, + &mld_ptr->dma_handle, + gfp_flags); + + if (mld_ptr->vaddr == NULL) { + IPAERR("memory alloc failed\n"); + result = -ENOMEM; + goto bail; + } + + nm_ptr->ddr_in_use = true; + nm_ptr->last_alloc_loc = IPA_NAT_MEM_IN_DDR; + } + } else { + if (nat_type == IPAHAL_NAT_IPV6CT) { + + IPADBG("V6 CT with size 0x%08X will reside in: %s\n", + table_alloc->size, + ipa3_nat_mem_in_as_str(IPA_NAT_MEM_IN_DDR)); + + dev->table_alloc_size = table_alloc->size; + + dev->vaddr = + dma_alloc_coherent( + ipa3_ctx->pdev, + dev->table_alloc_size, + &dev->dma_handle, + gfp_flags); + + if (dev->vaddr == NULL) { + IPAERR("memory alloc failed\n"); + result = -ENOMEM; + goto bail; + } + } + } + +bail: + IPADBG("Out\n"); + + return result; +} + +/** + * ipa3_allocate_nat_device() - Allocates memory for the NAT device + * @mem: [in/out] memory parameters + * + * Called by NAT client driver to allocate memory for the NAT entries. Based on + * the request size either shared or system memory will be used. + * + * Returns: 0 on success, negative on failure + */ +int ipa3_allocate_nat_device(struct ipa_ioc_nat_alloc_mem *mem) +{ + int result; + struct ipa_ioc_nat_ipv6ct_table_alloc tmp; + + tmp.size = mem->size; + tmp.offset = 0; + + result = ipa3_allocate_nat_table(&tmp); + if (result) + goto bail; + + mem->offset = tmp.offset; + +bail: + return result; +} + +/** + * ipa3_allocate_nat_table() - Allocates memory for the NAT table + * @table_alloc: [in/out] memory parameters + * + * Called by NAT client to allocate memory for the table entries. + * Based on the request size either shared or system memory will be used. + * + * Returns: 0 on success, negative on failure + */ +int ipa3_allocate_nat_table( + struct ipa_ioc_nat_ipv6ct_table_alloc *table_alloc) +{ + struct ipa3_nat_mem *nm_ptr = &(ipa3_ctx->nat_mem); + struct ipa3_nat_mem_loc_data *mld_ptr; + + int result; + + IPADBG("table size:%u offset:%u\n", + table_alloc->size, table_alloc->offset); + + mutex_lock(&nm_ptr->dev.lock); + + result = ipa3_nat_ipv6ct_allocate_mem( + &nm_ptr->dev, + table_alloc, + IPAHAL_NAT_IPV4); + + if (result) + goto bail; + + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_0 + && + nm_ptr->pdn_mem.base == NULL) { + + gfp_t gfp_flags = GFP_KERNEL | __GFP_ZERO; + size_t pdn_entry_size; + struct ipa_mem_buffer *pdn_mem_ptr = &nm_ptr->pdn_mem; + + ipahal_nat_entry_size(IPAHAL_NAT_IPV4_PDN, &pdn_entry_size); + + pdn_mem_ptr->size = pdn_entry_size * ipa3_get_max_pdn(); + + if (IPA_MEM_PART(pdn_config_size) < pdn_mem_ptr->size) { + IPAERR( + "number of PDN entries exceeds SRAM available space\n"); + result = -ENOMEM; + goto fail_alloc_pdn; + } + + pdn_mem_ptr->base = + dma_alloc_coherent( + ipa3_ctx->pdev, + pdn_mem_ptr->size, + &pdn_mem_ptr->phys_base, + gfp_flags); + + if (pdn_mem_ptr->base == NULL) { + IPAERR("fail to allocate PDN memory\n"); + result = -ENOMEM; + goto fail_alloc_pdn; + } + + IPADBG("IPA NAT dev allocated PDN memory successfully\n"); + } + + IPADBG("IPA NAT dev init successfully\n"); + + mutex_unlock(&nm_ptr->dev.lock); + + IPADBG("return\n"); + + return 0; + +fail_alloc_pdn: + mld_ptr = &nm_ptr->mem_loc[nm_ptr->last_alloc_loc]; + + if (nm_ptr->last_alloc_loc == IPA_NAT_MEM_IN_DDR) { + if (mld_ptr->vaddr) { + dma_free_coherent( + ipa3_ctx->pdev, + mld_ptr->table_alloc_size, + mld_ptr->vaddr, + mld_ptr->dma_handle); + mld_ptr->vaddr = NULL; + } + } + + if (nm_ptr->last_alloc_loc == IPA_NAT_MEM_IN_SRAM) { + if (mld_ptr->io_vaddr) { + iounmap(mld_ptr->io_vaddr); + mld_ptr->io_vaddr = NULL; + mld_ptr->vaddr = NULL; + } + } + +bail: + mutex_unlock(&nm_ptr->dev.lock); + + return result; +} + +/** + * ipa3_allocate_ipv6ct_table() - Allocates memory for the IPv6CT table + * @table_alloc: [in/out] memory parameters + * + * Called by IPv6CT client to allocate memory for the table entries. + * Based on the request size either shared or system memory will be used. + * + * Returns: 0 on success, negative on failure + */ +int ipa3_allocate_ipv6ct_table( + struct ipa_ioc_nat_ipv6ct_table_alloc *table_alloc) +{ + int result; + + IPADBG("\n"); + + if (ipa3_ctx->ipa_hw_type < IPA_HW_v4_0) { + IPAERR_RL("IPv6 connection tracking isn't supported\n"); + return -EPERM; + } + + mutex_lock(&ipa3_ctx->ipv6ct_mem.dev.lock); + + result = ipa3_nat_ipv6ct_allocate_mem( + &ipa3_ctx->ipv6ct_mem.dev, + table_alloc, + IPAHAL_NAT_IPV6CT); + + if (result) + goto bail; + + IPADBG("IPA IPv6CT dev init successfully\n"); + +bail: + mutex_unlock(&ipa3_ctx->ipv6ct_mem.dev.lock); + return result; +} + +static int ipa3_nat_ipv6ct_check_table_params( + struct ipa3_nat_ipv6ct_common_mem *dev, + enum ipa3_nat_mem_in nmi, + uint32_t offset, + uint16_t entries_num, + enum ipahal_nat_type nat_type) +{ + size_t entry_size, table_size, orig_alloc_size; + + struct ipa3_nat_mem *nm_ptr; + struct ipa3_nat_mem_loc_data *mld_ptr; + + int ret = 0; + + IPADBG("In\n"); + + IPADBG( + "v4(%u) v6(%u) nmi(%s) ofst(%u) ents(%u) nt(%s)\n", + dev->is_nat_mem, + dev->is_ipv6ct_mem, + ipa3_nat_mem_in_as_str(nmi), + offset, + entries_num, + ipahal_nat_type_str(nat_type)); + + if (dev->is_ipv6ct_mem) { + + orig_alloc_size = dev->table_alloc_size; + + if (offset > UINT_MAX - dev->dma_handle) { + IPAERR_RL("Failed due to integer overflow\n"); + IPAERR_RL("%s dma_handle: 0x%pa offset: 0x%x\n", + dev->name, &dev->dma_handle, offset); + ret = -EPERM; + goto bail; + } + + } else { /* dev->is_nat_mem */ + + nm_ptr = (struct ipa3_nat_mem *) dev; + + mld_ptr = &nm_ptr->mem_loc[nmi]; + orig_alloc_size = mld_ptr->table_alloc_size; + + if (nmi == IPA_NAT_MEM_IN_DDR) { + if (offset > UINT_MAX - mld_ptr->dma_handle) { + IPAERR_RL("Failed due to integer overflow\n"); + IPAERR_RL("%s dma_handle: 0x%pa offset: 0x%x\n", + dev->name, &mld_ptr->dma_handle, offset); + ret = -EPERM; + goto bail; + } + } + } + + ret = ipahal_nat_entry_size(nat_type, &entry_size); + + if (ret) { + IPAERR("Failed to retrieve size of entry for %s\n", + ipahal_nat_type_str(nat_type)); + goto bail; + } + + table_size = entry_size * entries_num; + + /* check for integer overflow */ + if (offset > UINT_MAX - table_size) { + IPAERR_RL("Detected overflow\n"); + ret = -EPERM; + goto bail; + } + + /* Check offset is not beyond allocated size */ + if (offset + table_size > orig_alloc_size) { + IPAERR_RL("Table offset not valid\n"); + IPAERR_RL("offset:%d entries:%d table_size:%zu mem_size:%zu\n", + offset, entries_num, table_size, orig_alloc_size); + ret = -EPERM; + goto bail; + } + +bail: + IPADBG("Out\n"); + + return ret; +} + +static inline void ipa3_nat_ipv6ct_create_init_cmd( + struct ipahal_imm_cmd_nat_ipv6ct_init_common *table_init_cmd, + bool is_shared, + dma_addr_t base_addr, + uint8_t tbl_index, + uint32_t base_table_offset, + uint32_t expn_table_offset, + uint16_t table_entries, + uint16_t expn_table_entries, + const char *table_name) +{ + table_init_cmd->base_table_addr_shared = is_shared; + table_init_cmd->expansion_table_addr_shared = is_shared; + + table_init_cmd->base_table_addr = base_addr + base_table_offset; + IPADBG("%s base table offset:0x%x\n", table_name, base_table_offset); + + table_init_cmd->expansion_table_addr = base_addr + expn_table_offset; + IPADBG("%s expn table offset:0x%x\n", table_name, expn_table_offset); + + table_init_cmd->table_index = tbl_index; + IPADBG("%s table index:0x%x\n", table_name, tbl_index); + + table_init_cmd->size_base_table = table_entries; + IPADBG("%s base table size:0x%x\n", table_name, table_entries); + + table_init_cmd->size_expansion_table = expn_table_entries; + IPADBG("%s expansion table size:0x%x\n", + table_name, expn_table_entries); +} + +static inline bool chk_sram_offset_alignment( + uintptr_t addr, + u32 mask) +{ + if (addr & (uintptr_t) mask) { + IPAERR("sram addr(%pK) is not properly aligned\n", addr); + return false; + } + return true; +} + +static inline int ipa3_nat_ipv6ct_init_device_structure( + struct ipa3_nat_ipv6ct_common_mem *dev, + enum ipa3_nat_mem_in nmi, + uint32_t base_table_offset, + uint32_t expn_table_offset, + uint16_t table_entries, + uint16_t expn_table_entries, + uint32_t index_offset, + uint32_t index_expn_offset, + uint8_t focus_change) +{ + int ret = 0; + + IPADBG("In\n"); + + IPADBG( + "v4(%u) v6(%u) nmi(%s) bto(%u) eto(%u) t_ents(%u) et_ents(%u) io(%u) ieo(%u)\n", + dev->is_nat_mem, + dev->is_ipv6ct_mem, + ipa3_nat_mem_in_as_str(nmi), + base_table_offset, + expn_table_offset, + table_entries, + expn_table_entries, + index_offset, + index_expn_offset); + + if (dev->is_ipv6ct_mem) { + + IPADBG("v6\n"); + + dev->base_table_addr = + (char *) dev->base_address + base_table_offset; + + IPADBG("%s base_table_addr: 0x%pK\n", + dev->name, dev->base_table_addr); + + dev->expansion_table_addr = + (char *) dev->base_address + expn_table_offset; + + IPADBG("%s expansion_table_addr: 0x%pK\n", + dev->name, dev->expansion_table_addr); + + IPADBG("%s table_entries: %d\n", + dev->name, table_entries); + + dev->table_entries = table_entries; + + IPADBG("%s expn_table_entries: %d\n", + dev->name, expn_table_entries); + + dev->expn_table_entries = expn_table_entries; + + } else if (dev->is_nat_mem) { + + struct ipa3_nat_mem *nm_ptr = (struct ipa3_nat_mem *) dev; + struct ipa3_nat_mem_loc_data *mld_p = + &nm_ptr->mem_loc[nmi]; + + IPADBG("v4\n"); + + nm_ptr->active_table = nmi; + + mld_p->base_table_addr = + (char *) mld_p->base_address + base_table_offset; + + IPADBG("%s base_table_addr: 0x%pK\n", + dev->name, mld_p->base_table_addr); + + mld_p->expansion_table_addr = + (char *) mld_p->base_address + expn_table_offset; + + IPADBG("%s expansion_table_addr: 0x%pK\n", + dev->name, mld_p->expansion_table_addr); + + IPADBG("%s table_entries: %d\n", + dev->name, table_entries); + + mld_p->table_entries = table_entries; + + IPADBG("%s expn_table_entries: %d\n", + dev->name, expn_table_entries); + + mld_p->expn_table_entries = expn_table_entries; + + mld_p->index_table_addr = + (char *) mld_p->base_address + index_offset; + + IPADBG("index_table_addr: 0x%pK\n", + mld_p->index_table_addr); + + mld_p->index_table_expansion_addr = + (char *) mld_p->base_address + index_expn_offset; + + IPADBG("index_table_expansion_addr: 0x%pK\n", + mld_p->index_table_expansion_addr); + + if (nmi == IPA_NAT_MEM_IN_DDR) { + if (focus_change) + nm_ptr->switch2ddr_cnt++; + } else { + /* + * The IPA wants certain SRAM addresses + * to have particular low order bits to + * be zero. We test here to ensure... + */ + if (!chk_sram_offset_alignment( + (uintptr_t) mld_p->base_table_addr, + 31) || + !chk_sram_offset_alignment( + (uintptr_t) mld_p->expansion_table_addr, + 31) || + !chk_sram_offset_alignment( + (uintptr_t) mld_p->index_table_addr, + 3) || + !chk_sram_offset_alignment( + (uintptr_t) mld_p->index_table_expansion_addr, + 3)) { + ret = -ENODEV; + goto done; + } + + if (focus_change) + nm_ptr->switch2sram_cnt++; + } + } + +done: + IPADBG("Out\n"); + + return ret; +} + +static void ipa3_nat_create_init_cmd( + struct ipa_ioc_v4_nat_init *init, + bool is_shared, + dma_addr_t base_addr, + struct ipahal_imm_cmd_ip_v4_nat_init *cmd) +{ + IPADBG("\n"); + + ipa3_nat_ipv6ct_create_init_cmd( + &cmd->table_init, + is_shared, + base_addr, + init->tbl_index, + init->ipv4_rules_offset, + init->expn_rules_offset, + init->table_entries, + init->expn_table_entries, + ipa3_ctx->nat_mem.dev.name); + + cmd->index_table_addr_shared = is_shared; + cmd->index_table_expansion_addr_shared = is_shared; + + cmd->index_table_addr = + base_addr + init->index_offset; + IPADBG("index_offset:0x%x\n", init->index_offset); + + cmd->index_table_expansion_addr = + base_addr + init->index_expn_offset; + IPADBG("index_expn_offset:0x%x\n", init->index_expn_offset); + + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_0) { + /* + * starting IPAv4.0 public ip field changed to store the + * PDN config table offset in SMEM + */ + cmd->public_addr_info = IPA_MEM_PART(pdn_config_ofst); + IPADBG("pdn config base:0x%x\n", cmd->public_addr_info); + } else { + cmd->public_addr_info = init->ip_addr; + IPADBG("Public IP address:%pI4h\n", &cmd->public_addr_info); + } + + IPADBG("return\n"); +} + +static int ipa3_nat_create_modify_pdn_cmd( + struct ipahal_imm_cmd_dma_shared_mem *mem_cmd, bool zero_mem) +{ + size_t pdn_entry_size, mem_size; + + IPADBG("\n"); + + ipahal_nat_entry_size(IPAHAL_NAT_IPV4_PDN, &pdn_entry_size); + mem_size = pdn_entry_size * ipa3_get_max_pdn(); + + /* Before providing physical base address check pointer exist or not*/ + if (!ipa3_ctx->nat_mem.pdn_mem.base) + return -EFAULT; + + if (zero_mem && ipa3_ctx->nat_mem.pdn_mem.base) + memset(ipa3_ctx->nat_mem.pdn_mem.base, 0, mem_size); + + /* Copy the PDN config table to SRAM */ + mem_cmd->is_read = false; + mem_cmd->skip_pipeline_clear = false; + mem_cmd->pipeline_clear_options = IPAHAL_HPS_CLEAR; + mem_cmd->size = mem_size; + mem_cmd->system_addr = ipa3_ctx->nat_mem.pdn_mem.phys_base; + mem_cmd->local_addr = ipa3_ctx->smem_restricted_bytes + + IPA_MEM_PART(pdn_config_ofst); + + IPADBG("return\n"); + return 0; +} + +static int ipa3_nat_send_init_cmd(struct ipahal_imm_cmd_ip_v4_nat_init *cmd, + bool zero_pdn_table) +{ + struct ipa3_desc desc[IPA_NAT_MAX_NUM_OF_INIT_CMD_DESC]; + struct ipahal_imm_cmd_pyld *cmd_pyld[IPA_NAT_MAX_NUM_OF_INIT_CMD_DESC]; + int i, num_cmd = 0, result; + struct ipahal_reg_valmask valmask; + struct ipahal_imm_cmd_register_write reg_write_coal_close; + + IPADBG("\n"); + + memset(desc, 0, sizeof(desc)); + memset(cmd_pyld, 0, sizeof(cmd_pyld)); + + /* IC to close the coal frame before HPS Clear if coal is enabled */ + if (ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS) != -1 + && !ipa3_ctx->ulso_wa) { + u32 offset = 0; + + i = ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS); + reg_write_coal_close.skip_pipeline_clear = false; + reg_write_coal_close.pipeline_clear_options = IPAHAL_HPS_CLEAR; + if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0) + offset = ipahal_get_reg_ofst( + IPA_AGGR_FORCE_CLOSE); + else + offset = ipahal_get_ep_reg_offset( + IPA_AGGR_FORCE_CLOSE_n, i); + reg_write_coal_close.offset = offset; + ipahal_get_aggr_force_close_valmask(i, &valmask); + reg_write_coal_close.value = valmask.val; + reg_write_coal_close.value_mask = valmask.mask; + cmd_pyld[num_cmd] = ipahal_construct_imm_cmd( + IPA_IMM_CMD_REGISTER_WRITE, + ®_write_coal_close, false); + if (!cmd_pyld[num_cmd]) { + IPAERR("failed to construct coal close IC\n"); + result = -ENOMEM; + goto destroy_imm_cmd; + } + ipa3_init_imm_cmd_desc(&desc[num_cmd], cmd_pyld[num_cmd]); + ++num_cmd; + } + + /* NO-OP IC for ensuring that IPA pipeline is empty */ + cmd_pyld[num_cmd] = + ipahal_construct_nop_imm_cmd(false, IPAHAL_HPS_CLEAR, false); + if (!cmd_pyld[num_cmd]) { + IPAERR("failed to construct NOP imm cmd\n"); + result = -ENOMEM; + goto destroy_imm_cmd; + } + + ipa3_init_imm_cmd_desc(&desc[num_cmd], cmd_pyld[num_cmd]); + ++num_cmd; + + cmd_pyld[num_cmd] = ipahal_construct_imm_cmd( + IPA_IMM_CMD_IP_V4_NAT_INIT, cmd, false); + if (!cmd_pyld[num_cmd]) { + IPAERR_RL("fail to construct NAT init imm cmd\n"); + result = -EPERM; + goto destroy_imm_cmd; + } + + ipa3_init_imm_cmd_desc(&desc[num_cmd], cmd_pyld[num_cmd]); + ++num_cmd; + + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_0) { + struct ipahal_imm_cmd_dma_shared_mem mem_cmd = { 0 }; + + if (num_cmd >= IPA_NAT_MAX_NUM_OF_INIT_CMD_DESC) { + IPAERR("number of commands is out of range\n"); + result = -ENOBUFS; + goto destroy_imm_cmd; + } + + /* Copy the PDN config table to SRAM */ + result = ipa3_nat_create_modify_pdn_cmd(&mem_cmd, + zero_pdn_table); + if (result) { + IPAERR(" Fail to create modify pdn command\n"); + goto destroy_imm_cmd; + } + cmd_pyld[num_cmd] = ipahal_construct_imm_cmd( + IPA_IMM_CMD_DMA_SHARED_MEM, &mem_cmd, false); + if (!cmd_pyld[num_cmd]) { + IPAERR( + "fail construct dma_shared_mem cmd: for pdn table"); + result = -ENOMEM; + goto destroy_imm_cmd; + } + ipa3_init_imm_cmd_desc(&desc[num_cmd], cmd_pyld[num_cmd]); + ++num_cmd; + IPADBG("added PDN table copy cmd\n"); + } + + result = ipa3_send_cmd(num_cmd, desc); + if (result) { + IPAERR("fail to send NAT init immediate command\n"); + goto destroy_imm_cmd; + } + + IPADBG("return\n"); + +destroy_imm_cmd: + for (i = 0; i < num_cmd; ++i) + ipahal_destroy_imm_cmd(cmd_pyld[i]); + + return result; +} + +static int ipa3_ipv6ct_send_init_cmd(struct ipahal_imm_cmd_ip_v6_ct_init *cmd) +{ + struct ipa3_desc desc[IPA_IPV6CT_MAX_NUM_OF_INIT_CMD_DESC]; + struct ipahal_imm_cmd_pyld + *cmd_pyld[IPA_IPV6CT_MAX_NUM_OF_INIT_CMD_DESC]; + int i, num_cmd = 0, result; + struct ipahal_reg_valmask valmask; + struct ipahal_imm_cmd_register_write reg_write_coal_close; + + IPADBG("\n"); + + memset(desc, 0, sizeof(desc)); + memset(cmd_pyld, 0, sizeof(cmd_pyld)); + + /* IC to close the coal frame before HPS Clear if coal is enabled */ + if (ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS) != -1 + && !ipa3_ctx->ulso_wa) { + u32 offset = 0; + i = ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS); + reg_write_coal_close.skip_pipeline_clear = false; + reg_write_coal_close.pipeline_clear_options = IPAHAL_HPS_CLEAR; + if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0) + offset = ipahal_get_reg_ofst( + IPA_AGGR_FORCE_CLOSE); + else + offset = ipahal_get_ep_reg_offset( + IPA_AGGR_FORCE_CLOSE_n, i); + reg_write_coal_close.offset = offset; + ipahal_get_aggr_force_close_valmask(i, &valmask); + reg_write_coal_close.value = valmask.val; + reg_write_coal_close.value_mask = valmask.mask; + cmd_pyld[num_cmd] = ipahal_construct_imm_cmd( + IPA_IMM_CMD_REGISTER_WRITE, + ®_write_coal_close, false); + if (!cmd_pyld[num_cmd]) { + IPAERR("failed to construct coal close IC\n"); + result = -ENOMEM; + goto destroy_imm_cmd; + } + ipa3_init_imm_cmd_desc(&desc[num_cmd], cmd_pyld[num_cmd]); + ++num_cmd; + } + + /* NO-OP IC for ensuring that IPA pipeline is empty */ + cmd_pyld[num_cmd] = + ipahal_construct_nop_imm_cmd(false, IPAHAL_HPS_CLEAR, false); + if (!cmd_pyld[num_cmd]) { + IPAERR("failed to construct NOP imm cmd\n"); + result = -ENOMEM; + goto destroy_imm_cmd; + } + + ipa3_init_imm_cmd_desc(&desc[num_cmd], cmd_pyld[num_cmd]); + ++num_cmd; + + if (num_cmd >= IPA_IPV6CT_MAX_NUM_OF_INIT_CMD_DESC) { + IPAERR("number of commands is out of range\n"); + result = -ENOBUFS; + goto destroy_imm_cmd; + } + + cmd_pyld[num_cmd] = ipahal_construct_imm_cmd( + IPA_IMM_CMD_IP_V6_CT_INIT, cmd, false); + if (!cmd_pyld[num_cmd]) { + IPAERR_RL("fail to construct IPv6CT init imm cmd\n"); + result = -EPERM; + goto destroy_imm_cmd; + } + + ipa3_init_imm_cmd_desc(&desc[num_cmd], cmd_pyld[num_cmd]); + ++num_cmd; + + result = ipa3_send_cmd(num_cmd, desc); + if (result) { + IPAERR("Fail to send IPv6CT init immediate command\n"); + goto destroy_imm_cmd; + } + + IPADBG("return\n"); + +destroy_imm_cmd: + for (i = 0; i < num_cmd; ++i) + ipahal_destroy_imm_cmd(cmd_pyld[i]); + + return result; +} + +/* IOCTL function handlers */ +/** + * ipa3_nat_init_cmd() - Post IP_V4_NAT_INIT command to IPA HW + * @init: [in] initialization command attributes + * + * Called by NAT client driver to post IP_V4_NAT_INIT command to IPA HW + * + * Returns: 0 on success, negative on failure + */ +int ipa3_nat_init_cmd( + struct ipa_ioc_v4_nat_init *init) +{ + struct ipa3_nat_ipv6ct_common_mem *dev = &ipa3_ctx->nat_mem.dev; + struct ipa3_nat_mem *nm_ptr = (struct ipa3_nat_mem *) dev; + enum ipa3_nat_mem_in nmi; + struct ipa3_nat_mem_loc_data *mld_ptr; + + struct ipahal_imm_cmd_ip_v4_nat_init cmd; + + int result; + + IPADBG("In\n"); + + if (!sram_compatible) { + init->mem_type = 0; + init->focus_change = 0; + } + + nmi = init->mem_type; + + IPADBG("tbl_index(%d) table_entries(%u)\n", + init->tbl_index, + init->table_entries); + + memset(&cmd, 0, sizeof(cmd)); + + if (!IPA_VALID_TBL_INDEX(init->tbl_index)) { + IPAERR_RL("Unsupported table index %d\n", + init->tbl_index); + result = -EPERM; + goto bail; + } + + if (init->table_entries == 0 || + init->table_entries == U16_MAX) { + IPAERR_RL("Table entries is %d\n", init->table_entries); + result = -EPERM; + goto bail; + } + + if (!IPA_VALID_NAT_MEM_IN(nmi)) { + IPAERR_RL("Bad ipa3_nat_mem_in type\n"); + result = -EPERM; + goto bail; + } + + IPADBG("nmi(%s)\n", ipa3_nat_mem_in_as_str(nmi)); + + mld_ptr = &nm_ptr->mem_loc[nmi]; + + if (!mld_ptr->is_mapped) { + IPAERR_RL("Attempt to init %s before mmap\n", dev->name); + result = -EPERM; + goto bail; + } + + result = ipa3_nat_ipv6ct_check_table_params( + dev, nmi, + init->ipv4_rules_offset, + init->table_entries + 1, + IPAHAL_NAT_IPV4); + + if (result) { + IPAERR_RL("Bad params for NAT base table\n"); + goto bail; + } + + result = ipa3_nat_ipv6ct_check_table_params( + dev, nmi, + init->expn_rules_offset, + init->expn_table_entries, + IPAHAL_NAT_IPV4); + + if (result) { + IPAERR_RL("Bad params for NAT expansion table\n"); + goto bail; + } + + result = ipa3_nat_ipv6ct_check_table_params( + dev, nmi, + init->index_offset, + init->table_entries + 1, + IPAHAL_NAT_IPV4_INDEX); + + if (result) { + IPAERR_RL("Bad params for index table\n"); + goto bail; + } + + result = ipa3_nat_ipv6ct_check_table_params( + dev, nmi, + init->index_expn_offset, + init->expn_table_entries, + IPAHAL_NAT_IPV4_INDEX); + + if (result) { + IPAERR_RL("Bad params for index expansion table\n"); + goto bail; + } + + IPADBG("Table memory becoming active: %s\n", + ipa3_nat_mem_in_as_str(nmi)); + + if (nmi == IPA_NAT_MEM_IN_DDR) { + ipa3_nat_create_init_cmd( + init, + false, + mld_ptr->dma_handle, + &cmd); + } else { + ipa3_nat_create_init_cmd( + init, + true, + IPA_RAM_NAT_OFST, + &cmd); + } + + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_0 + && + nm_ptr->pdn_mem.base + && + !init->focus_change) { + + struct ipahal_nat_pdn_entry pdn_entry; + + /* store ip in pdn entry cache array */ + pdn_entry.public_ip = init->ip_addr; + pdn_entry.src_metadata = 0; + pdn_entry.dst_metadata = 0; + + result = ipahal_nat_construct_entry( + IPAHAL_NAT_IPV4_PDN, + &pdn_entry, + nm_ptr->pdn_mem.base); + + if (result) { + IPAERR("Fail to construct NAT pdn entry\n"); + goto bail; + } + } + + IPADBG("Posting NAT init command\n"); + + result = ipa3_nat_send_init_cmd(&cmd, false); + + if (result) { + IPAERR("Fail to send NAT init immediate command\n"); + goto bail; + } + + result = ipa3_nat_ipv6ct_init_device_structure( + dev, nmi, + init->ipv4_rules_offset, + init->expn_rules_offset, + init->table_entries, + init->expn_table_entries, + init->index_offset, + init->index_expn_offset, + init->focus_change); + + if (result) { + IPAERR("Table offset initialization failure\n"); + goto bail; + } + + nm_ptr->public_ip_addr = init->ip_addr; + + IPADBG("Public IP address:%pI4h\n", &nm_ptr->public_ip_addr); + + dev->is_hw_init = true; + +bail: + IPADBG("Out\n"); + + return result; +} + +/** + * ipa3_ipv6ct_init_cmd() - Post IP_V6_CONN_TRACK_INIT command to IPA HW + * @init: [in] initialization command attributes + * + * Called by NAT client driver to post IP_V6_CONN_TRACK_INIT command to IPA HW + * + * Returns: 0 on success, negative on failure + */ +int ipa3_ipv6ct_init_cmd( + struct ipa_ioc_ipv6ct_init *init) +{ + struct ipa3_nat_ipv6ct_common_mem *dev = &ipa3_ctx->ipv6ct_mem.dev; + + struct ipahal_imm_cmd_ip_v6_ct_init cmd; + + int result; + + IPADBG("In\n"); + + memset(&cmd, 0, sizeof(cmd)); + + if (ipa3_ctx->ipa_hw_type < IPA_HW_v4_0) { + IPAERR_RL("IPv6 connection tracking isn't supported\n"); + return -EPERM; + } + + if (!IPA_VALID_TBL_INDEX(init->tbl_index)) { + IPAERR_RL("Unsupported table index %d\n", init->tbl_index); + return -EPERM; + } + + if (init->table_entries == 0) { + IPAERR_RL("Table entries is zero\n"); + return -EPERM; + } + + if (!dev->is_mapped) { + IPAERR_RL("attempt to init %s before mmap\n", + dev->name); + return -EPERM; + } + + result = ipa3_nat_ipv6ct_check_table_params( + dev, IPA_NAT_MEM_IN_DDR, + init->base_table_offset, + init->table_entries + 1, + IPAHAL_NAT_IPV6CT); + + if (result) { + IPAERR_RL("Bad params for IPv6CT base table\n"); + return result; + } + + result = ipa3_nat_ipv6ct_check_table_params( + dev, IPA_NAT_MEM_IN_DDR, + init->expn_table_offset, + init->expn_table_entries, + IPAHAL_NAT_IPV6CT); + + if (result) { + IPAERR_RL("Bad params for IPv6CT expansion table\n"); + return result; + } + + IPADBG("Will install v6 NAT in: %s\n", + ipa3_nat_mem_in_as_str(IPA_NAT_MEM_IN_DDR)); + + ipa3_nat_ipv6ct_create_init_cmd( + &cmd.table_init, + false, + dev->dma_handle, + init->tbl_index, + init->base_table_offset, + init->expn_table_offset, + init->table_entries, + init->expn_table_entries, + dev->name); + + IPADBG("posting ip_v6_ct_init imm command\n"); + + result = ipa3_ipv6ct_send_init_cmd(&cmd); + + if (result) { + IPAERR("fail to send IPv6CT init immediate command\n"); + return result; + } + + ipa3_nat_ipv6ct_init_device_structure( + dev, + IPA_NAT_MEM_IN_DDR, + init->base_table_offset, + init->expn_table_offset, + init->table_entries, + init->expn_table_entries, + 0, 0, 0); + + dev->is_hw_init = true; + + IPADBG("Out\n"); + + return 0; +} + +/** + * ipa3_nat_mdfy_pdn() - Modify a PDN entry in PDN config table in IPA SRAM + * @mdfy_pdn: [in] PDN info to be written to SRAM + * + * Called by NAT client driver to modify an entry in the PDN config table + * + * Returns: 0 on success, negative on failure + */ +int ipa3_nat_mdfy_pdn( + struct ipa_ioc_nat_pdn_entry *mdfy_pdn) +{ + struct ipa3_nat_ipv6ct_common_mem *dev = &ipa3_ctx->nat_mem.dev; + struct ipa3_nat_mem *nm_ptr = (struct ipa3_nat_mem *) dev; + struct ipa_mem_buffer *pdn_mem_ptr = &nm_ptr->pdn_mem; + + struct ipahal_imm_cmd_dma_shared_mem mem_cmd = { 0 }; + struct ipahal_nat_pdn_entry pdn_fields = { 0 }; + struct ipa3_desc desc = { 0 }; + struct ipahal_imm_cmd_pyld *cmd_pyld; + + size_t entry_size; + + int result = 0; + + IPADBG("In\n"); + + mutex_lock(&dev->lock); + + if (ipa3_ctx->ipa_hw_type < IPA_HW_v4_0) { + IPAERR_RL("IPA HW does not support multi PDN\n"); + result = -EPERM; + goto bail; + } + + if (pdn_mem_ptr->base == NULL) { + IPAERR_RL( + "Attempt to modify a PDN entry before the PDN table memory allocation\n"); + result = -EPERM; + goto bail; + } + + if (mdfy_pdn->pdn_index > (ipa3_get_max_pdn() - 1)) { + IPAERR_RL("pdn index out of range %d\n", mdfy_pdn->pdn_index); + result = -EPERM; + goto bail; + } + + /* + * Store ip in pdn entry cache array + */ + pdn_fields.public_ip = mdfy_pdn->public_ip; + pdn_fields.dst_metadata = mdfy_pdn->dst_metadata; + pdn_fields.src_metadata = mdfy_pdn->src_metadata; + + /* + * Mark tethering bit for remote modem + */ + if (ipa3_ctx->ipa_hw_type == IPA_HW_v4_1) { + pdn_fields.src_metadata |= IPA_QMAP_TETH_BIT; + } + + /* + * Get size of the entry + */ + result = ipahal_nat_entry_size( + IPAHAL_NAT_IPV4_PDN, + &entry_size); + + if (result) { + IPAERR("Failed to retrieve pdn entry size\n"); + goto bail; + } + + result = ipahal_nat_construct_entry( + IPAHAL_NAT_IPV4_PDN, + &pdn_fields, + (pdn_mem_ptr->base + (mdfy_pdn->pdn_index)*(entry_size))); + + if (result) { + IPAERR("Fail to construct NAT pdn entry\n"); + goto bail; + } + + IPADBG("Modify PDN in index: %d Public ip address:%pI4h\n", + mdfy_pdn->pdn_index, + &pdn_fields.public_ip); + + IPADBG("Modify PDN dst metadata: 0x%x src metadata: 0x%x\n", + pdn_fields.dst_metadata, + pdn_fields.src_metadata); + + /* + * Copy the PDN config table to SRAM + */ + result = ipa3_nat_create_modify_pdn_cmd(&mem_cmd, false); + + if (result) { + IPAERR(" Fail to create modify pdn command\n"); + goto bail; + } + + cmd_pyld = ipahal_construct_imm_cmd( + IPA_IMM_CMD_DMA_SHARED_MEM, &mem_cmd, false); + + if (!cmd_pyld) { + IPAERR( + "fail construct dma_shared_mem cmd: for pdn table\n"); + result = -ENOMEM; + goto bail; + } + + ipa3_init_imm_cmd_desc(&desc, cmd_pyld); + + IPADBG("sending PDN table copy cmd\n"); + + result = ipa3_send_cmd(1, &desc); + + if (result) + IPAERR("Fail to send PDN table copy immediate command\n"); + + ipahal_destroy_imm_cmd(cmd_pyld); + +bail: + mutex_unlock(&dev->lock); + + IPADBG("Out\n"); + + return result; +} + +static uint32_t ipa3_nat_ipv6ct_calculate_table_size( + enum ipa3_nat_mem_in nmi, + uint8_t base_addr) +{ + size_t entry_size; + u32 num_entries; + enum ipahal_nat_type nat_type; + struct ipa3_nat_mem_loc_data *mld_ptr = &ipa3_ctx->nat_mem.mem_loc[nmi]; + + switch (base_addr) { + case IPA_NAT_BASE_TBL: + num_entries = mld_ptr->table_entries + 1; + nat_type = IPAHAL_NAT_IPV4; + break; + case IPA_NAT_EXPN_TBL: + num_entries = mld_ptr->expn_table_entries; + nat_type = IPAHAL_NAT_IPV4; + break; + case IPA_NAT_INDX_TBL: + num_entries = mld_ptr->table_entries + 1; + nat_type = IPAHAL_NAT_IPV4_INDEX; + break; + case IPA_NAT_INDEX_EXPN_TBL: + num_entries = mld_ptr->expn_table_entries; + nat_type = IPAHAL_NAT_IPV4_INDEX; + break; + case IPA_IPV6CT_BASE_TBL: + num_entries = ipa3_ctx->ipv6ct_mem.dev.table_entries + 1; + nat_type = IPAHAL_NAT_IPV6CT; + break; + case IPA_IPV6CT_EXPN_TBL: + num_entries = ipa3_ctx->ipv6ct_mem.dev.expn_table_entries; + nat_type = IPAHAL_NAT_IPV6CT; + break; + default: + IPAERR_RL("Invalid base_addr %d for table DMA command\n", + base_addr); + return 0; + } + + ipahal_nat_entry_size(nat_type, &entry_size); + + return entry_size * num_entries; +} + +static int ipa3_table_validate_table_dma_one( + enum ipa3_nat_mem_in nmi, + struct ipa_ioc_nat_dma_one *param) +{ + uint32_t table_size; + + if (param->table_index >= 1) { + IPAERR_RL("Unsupported table index %u\n", param->table_index); + return -EPERM; + } + + switch (param->base_addr) { + case IPA_NAT_BASE_TBL: + case IPA_NAT_EXPN_TBL: + case IPA_NAT_INDX_TBL: + case IPA_NAT_INDEX_EXPN_TBL: + if (!ipa3_ctx->nat_mem.dev.is_hw_init) { + IPAERR_RL("attempt to write to %s before HW int\n", + ipa3_ctx->nat_mem.dev.name); + return -EPERM; + } + IPADBG("nmi(%s)\n", ipa3_nat_mem_in_as_str(nmi)); + break; + case IPA_IPV6CT_BASE_TBL: + case IPA_IPV6CT_EXPN_TBL: + if (ipa3_ctx->ipa_hw_type < IPA_HW_v4_0) { + IPAERR_RL("IPv6 connection tracking isn't supported\n"); + return -EPERM; + } + + if (!ipa3_ctx->ipv6ct_mem.dev.is_hw_init) { + IPAERR_RL("attempt to write to %s before HW int\n", + ipa3_ctx->ipv6ct_mem.dev.name); + return -EPERM; + } + break; + default: + IPAERR_RL("Invalid base_addr %d for table DMA command\n", + param->base_addr); + return -EPERM; + } + + table_size = ipa3_nat_ipv6ct_calculate_table_size( + nmi, + param->base_addr); + + if (!table_size) { + IPAERR_RL("Failed to calculate table size for base_addr %d\n", + param->base_addr); + return -EPERM; + } + + if (param->offset >= table_size) { + IPAERR_RL("Invalid offset %d for table DMA command\n", + param->offset); + IPAERR_RL("table_index %d base addr %d size %d\n", + param->table_index, param->base_addr, table_size); + return -EPERM; + } + + return 0; +} + + +/** + * ipa3_table_dma_cmd() - Post TABLE_DMA command to IPA HW + * @dma: [in] initialization command attributes + * + * Called by NAT/IPv6CT clients to post TABLE_DMA command to IPA HW + * + * Returns: 0 on success, negative on failure + */ +int ipa3_table_dma_cmd( + struct ipa_ioc_nat_dma_cmd *dma) +{ + struct ipa3_nat_ipv6ct_common_mem *dev = &ipa3_ctx->nat_mem.dev; + + enum ipahal_imm_cmd_name cmd_name = IPA_IMM_CMD_NAT_DMA; + + struct ipahal_imm_cmd_table_dma cmd; + struct ipahal_imm_cmd_pyld *cmd_pyld[IPA_MAX_NUM_OF_TABLE_DMA_CMD_DESC]; + struct ipa3_desc desc[IPA_MAX_NUM_OF_TABLE_DMA_CMD_DESC]; + + uint8_t cnt, num_cmd = 0; + + int result = 0; + int i; + struct ipahal_reg_valmask valmask; + struct ipahal_imm_cmd_register_write reg_write_coal_close; + int max_dma_table_cmds = IPA_MAX_NUM_OF_TABLE_DMA_CMD_DESC; + + IPADBG("In\n"); + + if (!sram_compatible) + dma->mem_type = 0; + + if (!dev->is_dev_init) { + IPAERR_RL("NAT hasn't been initialized\n"); + result = -EPERM; + goto bail; + } + + if (!IPA_VALID_NAT_MEM_IN(dma->mem_type)) { + IPAERR_RL("Invalid ipa3_nat_mem_in type (%u)\n", + dma->mem_type); + result = -EPERM; + goto bail; + } + + IPADBG("nmi(%s)\n", ipa3_nat_mem_in_as_str(dma->mem_type)); + + memset(&cmd, 0, sizeof(cmd)); + memset(cmd_pyld, 0, sizeof(cmd_pyld)); + memset(desc, 0, sizeof(desc)); + + /** + * We use a descriptor for closing coalsceing endpoint + * by immediate command. So, DMA entries should be less than + * IPA_MAX_NUM_OF_TABLE_DMA_CMD_DESC - 1 to overcome + * buffer overflow of ipa3_desc array. + */ + if (ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS) != -1) + max_dma_table_cmds -= 1; + + if (!dma->entries || dma->entries > (max_dma_table_cmds - 1)) { + IPAERR_RL("Invalid number of entries %d\n", + dma->entries); + result = -EPERM; + goto bail; + } + + for (cnt = 0; cnt < dma->entries; ++cnt) { + + result = ipa3_table_validate_table_dma_one( + dma->mem_type, &dma->dma[cnt]); + + if (result) { + IPAERR_RL("Table DMA command parameter %d is invalid\n", + cnt); + goto bail; + } + } + + /* IC to close the coal frame before HPS Clear if coal is enabled */ + if (ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS) != -1 + && !ipa3_ctx->ulso_wa) { + u32 offset = 0; + + i = ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS); + reg_write_coal_close.skip_pipeline_clear = false; + reg_write_coal_close.pipeline_clear_options = IPAHAL_HPS_CLEAR; + if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0) + offset = ipahal_get_reg_ofst( + IPA_AGGR_FORCE_CLOSE); + else + offset = ipahal_get_ep_reg_offset( + IPA_AGGR_FORCE_CLOSE_n, i); + reg_write_coal_close.offset = offset; + ipahal_get_aggr_force_close_valmask(i, &valmask); + reg_write_coal_close.value = valmask.val; + reg_write_coal_close.value_mask = valmask.mask; + cmd_pyld[num_cmd] = ipahal_construct_imm_cmd( + IPA_IMM_CMD_REGISTER_WRITE, + ®_write_coal_close, false); + if (!cmd_pyld[num_cmd]) { + IPAERR("failed to construct coal close IC\n"); + result = -ENOMEM; + goto destroy_imm_cmd; + } + ipa3_init_imm_cmd_desc(&desc[num_cmd], cmd_pyld[num_cmd]); + ++num_cmd; + } + + /* + * NO-OP IC for ensuring that IPA pipeline is empty + */ + cmd_pyld[num_cmd] = + ipahal_construct_nop_imm_cmd(false, IPAHAL_HPS_CLEAR, false); + + if (!cmd_pyld[num_cmd]) { + IPAERR("Failed to construct NOP imm cmd\n"); + result = -ENOMEM; + goto destroy_imm_cmd; + } + + ipa3_init_imm_cmd_desc(&desc[num_cmd], cmd_pyld[num_cmd]); + + ++num_cmd; + + /* + * NAT_DMA was renamed to TABLE_DMA starting from IPAv4 + */ + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_0) + cmd_name = IPA_IMM_CMD_TABLE_DMA; + + for (cnt = 0; cnt < dma->entries; ++cnt) { + + cmd.table_index = dma->dma[cnt].table_index; + cmd.base_addr = dma->dma[cnt].base_addr; + cmd.offset = dma->dma[cnt].offset; + cmd.data = dma->dma[cnt].data; + + cmd_pyld[num_cmd] = + ipahal_construct_imm_cmd(cmd_name, &cmd, false); + + if (!cmd_pyld[num_cmd]) { + IPAERR_RL("Fail to construct table_dma imm cmd\n"); + result = -ENOMEM; + goto destroy_imm_cmd; + } + + ipa3_init_imm_cmd_desc(&desc[num_cmd], cmd_pyld[num_cmd]); + + ++num_cmd; + } + + result = ipa3_send_cmd(num_cmd, desc); + + if (result) + IPAERR("Fail to send table_dma immediate command\n"); + +destroy_imm_cmd: + for (cnt = 0; cnt < num_cmd; ++cnt) + ipahal_destroy_imm_cmd(cmd_pyld[cnt]); + +bail: + IPADBG("Out\n"); + + return result; +} + +/** + * ipa3_nat_dma_cmd() - Post NAT_DMA command to IPA HW + * @dma: [in] initialization command attributes + * + * Called by NAT client driver to post NAT_DMA command to IPA HW + * + * Returns: 0 on success, negative on failure + */ +int ipa3_nat_dma_cmd(struct ipa_ioc_nat_dma_cmd *dma) +{ + return ipa3_table_dma_cmd(dma); +} + +static void ipa3_nat_ipv6ct_free_mem( + struct ipa3_nat_ipv6ct_common_mem *dev) +{ + struct ipa3_nat_mem *nm_ptr; + struct ipa3_nat_mem_loc_data *mld_ptr; + + if (dev->is_ipv6ct_mem) { + + IPADBG("In: v6\n"); + + if (dev->vaddr) { + IPADBG("Freeing dma memory for %s\n", dev->name); + + dma_free_coherent( + ipa3_ctx->pdev, + dev->table_alloc_size, + dev->vaddr, + dev->dma_handle); + } + + dev->vaddr = NULL; + dev->dma_handle = 0; + dev->table_alloc_size = 0; + dev->base_table_addr = NULL; + dev->expansion_table_addr = NULL; + dev->table_entries = 0; + dev->expn_table_entries = 0; + + dev->is_hw_init = false; + dev->is_mapped = false; + } else { + if (dev->is_nat_mem) { + + IPADBG("In: v4\n"); + + nm_ptr = (struct ipa3_nat_mem *) dev; + + if (nm_ptr->ddr_in_use) { + + nm_ptr->ddr_in_use = false; + + mld_ptr = &nm_ptr->mem_loc[IPA_NAT_MEM_IN_DDR]; + + if (mld_ptr->vaddr) { + IPADBG("Freeing dma memory for %s\n", + dev->name); + + dma_free_coherent( + ipa3_ctx->pdev, + mld_ptr->table_alloc_size, + mld_ptr->vaddr, + mld_ptr->dma_handle); + } + + mld_ptr->vaddr = NULL; + mld_ptr->dma_handle = 0; + mld_ptr->table_alloc_size = 0; + mld_ptr->table_entries = 0; + mld_ptr->expn_table_entries = 0; + mld_ptr->base_table_addr = NULL; + mld_ptr->expansion_table_addr = NULL; + mld_ptr->index_table_addr = NULL; + mld_ptr->index_table_expansion_addr = NULL; + } + + if (nm_ptr->sram_in_use) { + + nm_ptr->sram_in_use = false; + + mld_ptr = &nm_ptr->mem_loc[IPA_NAT_MEM_IN_SRAM]; + + if (mld_ptr->io_vaddr) { + IPADBG("Unmappung sram memory for %s\n", + dev->name); + iounmap(mld_ptr->io_vaddr); + } + + mld_ptr->io_vaddr = NULL; + mld_ptr->vaddr = NULL; + mld_ptr->dma_handle = 0; + mld_ptr->table_alloc_size = 0; + mld_ptr->table_entries = 0; + mld_ptr->expn_table_entries = 0; + mld_ptr->base_table_addr = NULL; + mld_ptr->expansion_table_addr = NULL; + mld_ptr->index_table_addr = NULL; + mld_ptr->index_table_expansion_addr = NULL; + } + dev->is_hw_init = false; + dev->is_mapped = false; + + memset(nm_ptr->mem_loc, 0, sizeof(nm_ptr->mem_loc)); + } + } + + IPADBG("Out\n"); +} + +static int ipa3_nat_ipv6ct_create_del_table_cmd( + uint8_t tbl_index, + u32 base_addr, + struct ipa3_nat_ipv6ct_common_mem *dev, + struct ipahal_imm_cmd_nat_ipv6ct_init_common *table_init_cmd) +{ + bool mem_type_shared = true; + + IPADBG("In: tbl_index(%u) base_addr(%u) v4(%u) v6(%u)\n", + tbl_index, + base_addr, + dev->is_nat_mem, + dev->is_ipv6ct_mem); + + if (!IPA_VALID_TBL_INDEX(tbl_index)) { + IPAERR_RL("Unsupported table index %d\n", tbl_index); + return -EPERM; + } + + if (dev->tmp_mem) { + IPADBG("using temp memory during %s del\n", dev->name); + mem_type_shared = false; + base_addr = dev->tmp_mem->dma_handle; + } + + table_init_cmd->table_index = tbl_index; + table_init_cmd->base_table_addr = base_addr; + table_init_cmd->base_table_addr_shared = mem_type_shared; + table_init_cmd->expansion_table_addr = base_addr; + table_init_cmd->expansion_table_addr_shared = mem_type_shared; + table_init_cmd->size_base_table = 0; + table_init_cmd->size_expansion_table = 0; + + IPADBG("Out\n"); + + return 0; +} + +static int ipa3_nat_send_del_table_cmd( + uint8_t tbl_index) +{ + struct ipahal_imm_cmd_ip_v4_nat_init cmd; + int result = 0; + + IPADBG("In\n"); + + result = + ipa3_nat_ipv6ct_create_del_table_cmd( + tbl_index, + IPA_NAT_PHYS_MEM_OFFSET, + &ipa3_ctx->nat_mem.dev, + &cmd.table_init); + + if (result) { + IPAERR( + "Fail to create immediate command to delete NAT table\n"); + goto bail; + } + + cmd.index_table_addr = + cmd.table_init.base_table_addr; + cmd.index_table_addr_shared = + cmd.table_init.base_table_addr_shared; + cmd.index_table_expansion_addr = + cmd.index_table_addr; + cmd.index_table_expansion_addr_shared = + cmd.index_table_addr_shared; + cmd.public_addr_info = 0; + + IPADBG("Posting NAT delete command\n"); + + result = ipa3_nat_send_init_cmd(&cmd, true); + + if (result) { + IPAERR("Fail to send NAT delete immediate command\n"); + goto bail; + } + +bail: + IPADBG("Out\n"); + + return result; +} + +static int ipa3_ipv6ct_send_del_table_cmd(uint8_t tbl_index) +{ + struct ipahal_imm_cmd_ip_v6_ct_init cmd; + int result; + + IPADBG("\n"); + + result = ipa3_nat_ipv6ct_create_del_table_cmd( + tbl_index, + IPA_IPV6CT_PHYS_MEM_OFFSET, + &ipa3_ctx->ipv6ct_mem.dev, + &cmd.table_init); + if (result) { + IPAERR( + "Fail to create immediate command to delete IPv6CT table\n"); + return result; + } + + IPADBG("posting IPv6CT delete command\n"); + result = ipa3_ipv6ct_send_init_cmd(&cmd); + if (result) { + IPAERR("Fail to send IPv6CT delete immediate command\n"); + return result; + } + + IPADBG("return\n"); + return 0; +} + +/** + * ipa3_nat_del_cmd() - Delete a NAT table + * @del: [in] delete table table table parameters + * + * Called by NAT client driver to delete the nat table + * + * Returns: 0 on success, negative on failure + */ +int ipa3_nat_del_cmd(struct ipa_ioc_v4_nat_del *del) +{ + struct ipa_ioc_nat_ipv6ct_table_del tmp; + + tmp.table_index = del->table_index; + + return ipa3_del_nat_table(&tmp); +} + +/** + * ipa3_del_nat_table() - Delete the NAT table + * @del: [in] delete table parameters + * + * Called by NAT client to delete the table + * + * Returns: 0 on success, negative on failure + */ +int ipa3_del_nat_table( + struct ipa_ioc_nat_ipv6ct_table_del *del) +{ + struct ipa3_nat_ipv6ct_common_mem *dev = &ipa3_ctx->nat_mem.dev; + struct ipa3_nat_mem *nm_ptr = (struct ipa3_nat_mem *) dev; + struct ipa3_nat_mem_loc_data *mld_ptr; + enum ipa3_nat_mem_in nmi; + + int result = 0; + + IPADBG("In\n"); + + if (!sram_compatible) + del->mem_type = 0; + + nmi = del->mem_type; + + if (!dev->is_dev_init) { + IPAERR("NAT hasn't been initialized\n"); + result = -EPERM; + goto bail; + } + + if (!IPA_VALID_TBL_INDEX(del->table_index)) { + IPAERR_RL("Unsupported table index %d\n", + del->table_index); + result = -EPERM; + goto bail; + } + + if (!IPA_VALID_NAT_MEM_IN(nmi)) { + IPAERR_RL("Bad ipa3_nat_mem_in type\n"); + result = -EPERM; + goto bail; + } + + IPADBG("nmi(%s)\n", ipa3_nat_mem_in_as_str(nmi)); + + mld_ptr = &nm_ptr->mem_loc[nmi]; + + mutex_lock(&dev->lock); + + if (dev->is_hw_init) { + + result = ipa3_nat_send_del_table_cmd(del->table_index); + + if (result) { + IPAERR( + "Fail to send immediate command to delete NAT table\n"); + goto unlock; + } + } + + nm_ptr->public_ip_addr = 0; + + mld_ptr->index_table_addr = NULL; + mld_ptr->index_table_expansion_addr = NULL; + + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_0 + && + nm_ptr->pdn_mem.base) { + + struct ipa_mem_buffer *pdn_mem_ptr = &nm_ptr->pdn_mem; + + IPADBG("Freeing the PDN memory\n"); + + dma_free_coherent( + ipa3_ctx->pdev, + pdn_mem_ptr->size, + pdn_mem_ptr->base, + pdn_mem_ptr->phys_base); + + pdn_mem_ptr->base = NULL; + } + + ipa3_nat_ipv6ct_free_mem(dev); + +unlock: + mutex_unlock(&dev->lock); + +bail: + IPADBG("Out\n"); + + return result; +} + +/** + * ipa3_del_ipv6ct_table() - Delete the IPv6CT table + * @del: [in] delete table parameters + * + * Called by IPv6CT client to delete the table + * + * Returns: 0 on success, negative on failure + */ +int ipa3_del_ipv6ct_table( + struct ipa_ioc_nat_ipv6ct_table_del *del) +{ + struct ipa3_nat_ipv6ct_common_mem *dev = &ipa3_ctx->ipv6ct_mem.dev; + + int result = 0; + + IPADBG("In\n"); + + if (!sram_compatible) + del->mem_type = 0; + + if (!dev->is_dev_init) { + IPAERR("IPv6 connection tracking hasn't been initialized\n"); + result = -EPERM; + goto bail; + } + + if (ipa3_ctx->ipa_hw_type < IPA_HW_v4_0) { + IPAERR_RL("IPv6 connection tracking isn't supported\n"); + result = -EPERM; + goto bail; + } + + mutex_lock(&dev->lock); + + if (dev->is_hw_init) { + result = ipa3_ipv6ct_send_del_table_cmd(del->table_index); + + if (result) { + IPAERR("ipa3_ipv6ct_send_del_table_cmd() fail\n"); + goto unlock; + } + } + + ipa3_nat_ipv6ct_free_mem(&ipa3_ctx->ipv6ct_mem.dev); + +unlock: + mutex_unlock(&dev->lock); + +bail: + IPADBG("Out\n"); + + return result; +} + +int ipa3_nat_get_sram_info( + struct ipa_nat_in_sram_info *info_ptr) +{ + struct ipa3_nat_ipv6ct_common_mem *dev = &ipa3_ctx->nat_mem.dev; + + int ret = 0; + + IPADBG("In\n"); + + if (!info_ptr) { + IPAERR("Bad argument passed\n"); + ret = -EINVAL; + goto bail; + } + + if (!dev->is_dev_init) { + IPAERR_RL("NAT hasn't been initialized\n"); + ret = -EPERM; + goto bail; + } + + sram_compatible = true; + + memset(info_ptr, + 0, + sizeof(struct ipa_nat_in_sram_info)); + + /* + * Size of SRAM set aside for the NAT table. + */ + info_ptr->sram_mem_available_for_nat = IPA_RAM_NAT_SIZE; + + /* + * If table's phys addr in SRAM is not page aligned, it will be + * offset into the mmap'd VM by the amount calculated below. This + * value can be used by the app, so that it can know where the + * table actually lives in the mmap'd VM... + */ + info_ptr->nat_table_offset_into_mmap = + (ipa3_ctx->ipa_wrapper_base + + ipa3_ctx->ctrl->ipa_reg_base_ofst + + ipahal_get_reg_n_ofst( + IPA_SW_AREA_RAM_DIRECT_ACCESS_n, + 0) + + IPA_RAM_NAT_OFST) & ~PAGE_MASK; + + /* + * If the offset above plus the size of the NAT table causes the + * table to extend beyond the next page boundary, the app needs to + * know it, so that it can increase the size used in the mmap + * request... + */ + info_ptr->best_nat_in_sram_size_rqst = + roundup( + info_ptr->nat_table_offset_into_mmap + + IPA_RAM_NAT_SIZE, + PAGE_SIZE); + +bail: + IPADBG("Out\n"); + + return ret; +} diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_net.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_net.c new file mode 100644 index 0000000000..a22ae57724 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_net.c @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +/* + * This module is dedicated for operations that must be performed at + * init stage later than the main IPA driver and IPA clients manager init. + * + * E.g.: + * Both net_dev driver and ipa driver are initialized during + * the subsys_initcall, and the rmnet_ipa driver probe is called + * by the ipa_pre_init or ipa_post_init or ipa_clients_manager_init, + * the register_netdev() call will cause a kernel bug. + * + */ + +#include +#include +#include +#include "ipa.h" +#include "ipa_i.h" +#include "ipa_qmi_service.h" +#include "rndis_ipa.h" + +static int __init ipa_late_init(void) +{ + int rc = 0; + + IPADBG("IPA late init\n"); + + rc = ipa3_wwan_platform_driver_register(); + if (rc) { + IPAERR("ipa3_wwan_platform_driver_register failed: %d\n", + rc); + ipa3_wwan_cleanup(); + } + + rc = rndis_ipa_init_module(); + if (rc) { + IPAERR("rndis_ipa_init_module failed: %d\n", + rc); + rndis_ipa_cleanup_module(); + } + + return rc; +} +fs_initcall(ipa_late_init); + +static void __exit ipa_late_exit(void) +{ + IPADBG("IPA late exit\n"); + ipa3_wwan_cleanup(); + rndis_ipa_cleanup_module(); +} +module_exit(ipa_late_exit); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("IPA late init module"); + diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_odl.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_odl.c new file mode 100644 index 0000000000..f6968513fb --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_odl.c @@ -0,0 +1,830 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ipa_i.h" +#include "ipa_odl.h" +#include +#include +#include + +struct ipa_odl_context *ipa3_odl_ctx; + +static DECLARE_WAIT_QUEUE_HEAD(odl_ctl_msg_wq); + +static void print_ipa_odl_state_bit_mask(void) +{ + IPADBG("ipa3_odl_ctx->odl_state.odl_init --> %d\n", + ipa3_odl_ctx->odl_state.odl_init); + IPADBG("ipa3_odl_ctx->odl_state.odl_open --> %d\n", + ipa3_odl_ctx->odl_state.odl_open); + IPADBG("ipa3_odl_ctx->odl_state.adpl_open --> %d\n", + ipa3_odl_ctx->odl_state.adpl_open); + IPADBG("ipa3_odl_ctx->odl_state.aggr_byte_limit_sent --> %d\n", + ipa3_odl_ctx->odl_state.aggr_byte_limit_sent); + IPADBG("ipa3_odl_ctx->odl_state.odl_ep_setup --> %d\n", + ipa3_odl_ctx->odl_state.odl_ep_setup); + IPADBG("ipa3_odl_ctx->odl_state.odl_setup_done_sent --> %d\n", + ipa3_odl_ctx->odl_state.odl_setup_done_sent); + IPADBG("ipa3_odl_ctx->odl_state.odl_ep_info_sent --> %d\n", + ipa3_odl_ctx->odl_state.odl_ep_info_sent); + IPADBG("ipa3_odl_ctx->odl_state.odl_connected --> %d\n", + ipa3_odl_ctx->odl_state.odl_connected); + IPADBG("ipa3_odl_ctx->odl_state.odl_disconnected --> %d\n\n", + ipa3_odl_ctx->odl_state.odl_disconnected); +} + +static int ipa_odl_ctl_fops_open(struct inode *inode, struct file *filp) +{ + int ret = 0; + + if (ipa3_odl_ctx->odl_state.odl_init) { + ipa3_odl_ctx->odl_state.odl_open = true; + } else { + IPAERR("Before odl init trying to open odl ctl pipe\n"); + print_ipa_odl_state_bit_mask(); + ret = -ENODEV; + } + + return ret; +} + +static int ipa_odl_ctl_fops_release(struct inode *inode, struct file *filp) +{ + IPADBG("QTI closed ipa_odl_ctl node\n"); + ipa3_odl_ctx->odl_state.odl_open = false; + return 0; +} + +/** + * ipa_odl_ctl_fops_read() - read message from IPA ODL device + * @filp: [in] file pointer + * @buf: [out] buffer to read into + * @count: [in] size of above buffer + * @f_pos: [inout] file position + * + * Uer-space should continuously read from /dev/ipa_odl_ctl, + * read will block when there are no messages to read. + * Upon return, user-space should read the u32 data from the + * start of the buffer. + * + * 0 --> ODL disconnected. + * 1 --> ODL connected. + * + * Buffer supplied must be big enough to + * hold the message of size u32. + * + * Returns: how many bytes copied to buffer + * + * Note: Should not be called from atomic context + */ + +static ssize_t ipa_odl_ctl_fops_read(struct file *filp, char __user *buf, + size_t count, loff_t *f_pos) +{ + char __user *start; + u8 data; + int ret = 0; + static bool old_state; + bool new_state = false; + + start = buf; + ipa3_odl_ctx->odl_ctl_msg_wq_flag = false; + + if (!ipa3_odl_ctx->odl_state.adpl_open && + !ipa3_odl_ctx->odl_state.odl_disconnected) { + IPADBG("Failed to send data odl pipe already disconnected\n"); + ret = -EFAULT; + goto send_failed; + } + + if (ipa3_odl_ctx->odl_state.odl_ep_setup) + new_state = true; + else if (ipa3_odl_ctx->odl_state.odl_disconnected) + new_state = false; + else { + IPADBG("Failed to send data odl already running\n"); + ret = -EFAULT; + goto send_failed; + } + + if (old_state != new_state) { + old_state = new_state; + + if (new_state) + data = 1; + else if (!new_state) + data = 0; + + if (copy_to_user(buf, &data, + sizeof(data))) { + IPADBG("Cpoying data to user failed\n"); + ret = -EFAULT; + goto send_failed; + } + + buf += sizeof(data); + + if (data == 1) + ipa3_odl_ctx->odl_state.odl_setup_done_sent = + true; + } + + + if (start != buf && ret != -EFAULT) + ret = buf - start; +send_failed: + return ret; +} + +static unsigned int ipa_odl_ctl_fops_poll(struct file *file, poll_table *wait) +{ + unsigned int mask = 0; + + poll_wait(file, &odl_ctl_msg_wq, wait); + + if (ipa3_odl_ctx->odl_ctl_msg_wq_flag) { + IPADBG("Sending read mask to odl control pipe\n"); + mask |= POLLIN | POLLRDNORM; + } + return mask; +} + +static long ipa_odl_ctl_fops_ioctl(struct file *filp, unsigned int cmd, + unsigned long arg) +{ + struct ipa_odl_ep_info ep_info = {0}; + struct ipa_odl_modem_config status; + int retval = 0; + + IPADBG("Calling odl ioctl cmd = %d\n", cmd); + if (!ipa3_odl_ctx->odl_state.odl_setup_done_sent) { + IPAERR("Before complete the odl setup trying calling ioctl\n"); + print_ipa_odl_state_bit_mask(); + retval = -ENODEV; + goto fail; + } + + switch (cmd) { + case IPA_IOC_ODL_QUERY_ADAPL_EP_INFO: + /* Send ep_info to user APP */ + ep_info.ep_type = ODL_EP_TYPE_HSUSB; + ep_info.peripheral_iface_id = ODL_EP_PERIPHERAL_IFACE_ID; + ep_info.cons_pipe_num = -1; + ep_info.prod_pipe_num = + ipa3_odl_ctx->odl_client_hdl; + if (copy_to_user((void __user *)arg, &ep_info, + sizeof(ep_info))) { + retval = -EFAULT; + goto fail; + } + ipa3_odl_ctx->odl_state.odl_ep_info_sent = true; + break; + case IPA_IOC_ODL_QUERY_MODEM_CONFIG: + IPADBG("Received the IPA_IOC_ODL_QUERY_MODEM_CONFIG :\n"); + if (copy_from_user(&status, (const void __user *)arg, + sizeof(status))) { + retval = -EFAULT; + break; + } + if (status.config_status == CONFIG_SUCCESS) + ipa3_odl_ctx->odl_state.odl_connected = true; + IPADBG("status.config_status = %d odl_connected = %d\n", + status.config_status, ipa3_odl_ctx->odl_state.odl_connected); + break; + default: + retval = -ENOIOCTLCMD; + break; + } + +fail: + return retval; +} + +static void delete_first_node(void) +{ + struct ipa3_push_msg_odl *msg; + + if (!list_empty(&ipa3_odl_ctx->adpl_msg_list)) { + msg = list_first_entry(&ipa3_odl_ctx->adpl_msg_list, + struct ipa3_push_msg_odl, link); + if (msg) { + list_del(&msg->link); + kfree(msg->buff); + kfree(msg); + ipa3_odl_ctx->stats.odl_drop_pkt++; + if (atomic_read(&ipa3_odl_ctx->stats.numer_in_queue)) + atomic_dec(&ipa3_odl_ctx->stats.numer_in_queue); + } + } else { + IPADBG("List Empty\n"); + } +} + +int ipa3_send_adpl_msg(unsigned long skb_data) +{ + struct ipa3_push_msg_odl *msg; + struct sk_buff *skb = (struct sk_buff *)skb_data; + void *data; + + IPADBG_LOW("Processing DPL data\n"); + msg = kzalloc(sizeof(struct ipa3_push_msg_odl), GFP_KERNEL); + if (msg == NULL) { + IPADBG("Memory allocation failed\n"); + return -ENOMEM; + } + + data = kmemdup(skb->data, skb->len, GFP_KERNEL); + if (data == NULL) { + kfree(msg); + return -ENOMEM; + } + memcpy(data, skb->data, skb->len); + msg->buff = data; + msg->len = skb->len; + mutex_lock(&ipa3_odl_ctx->adpl_msg_lock); + if (atomic_read(&ipa3_odl_ctx->stats.numer_in_queue) >= + MAX_QUEUE_TO_ODL) + delete_first_node(); + list_add_tail(&msg->link, &ipa3_odl_ctx->adpl_msg_list); + atomic_inc(&ipa3_odl_ctx->stats.numer_in_queue); + mutex_unlock(&ipa3_odl_ctx->adpl_msg_lock); + wake_up(&ipa3_odl_ctx->adpl_msg_waitq); + IPA_STATS_INC_CNT(ipa3_odl_ctx->stats.odl_rx_pkt); + + return 0; +} + +/** + * odl_ipa_packet_receive_notify() - Rx notify + * + * @priv: driver context + * @evt: event type + * @data: data provided with event + * + * IPA will pass a packet to the Linux network stack with skb->data + */ +static void odl_ipa_packet_receive_notify(void *priv, + enum ipa_dp_evt_type evt, + unsigned long data) +{ + IPADBG_LOW("Rx packet was received\n"); + if (evt == IPA_RECEIVE) + ipa3_send_adpl_msg(data); + else + IPAERR("Invalid evt %d received in wan_ipa_receive\n", evt); +} + +int ipa_setup_odl_pipe(void) +{ + struct ipa_sys_connect_params *ipa_odl_ep_cfg; + int ret; + + ipa_odl_ep_cfg = &ipa3_odl_ctx->odl_sys_param; + + IPADBG("Setting up the odl endpoint\n"); + ipa_odl_ep_cfg->ipa_ep_cfg.cfg.cs_offload_en = IPA_DISABLE_CS_OFFLOAD; + + ipa_odl_ep_cfg->ipa_ep_cfg.aggr.aggr_en = IPA_ENABLE_AGGR; + ipa_odl_ep_cfg->ipa_ep_cfg.aggr.aggr_hard_byte_limit_en = 1; + ipa_odl_ep_cfg->ipa_ep_cfg.aggr.aggr = IPA_GENERIC; + ipa_odl_ep_cfg->ipa_ep_cfg.aggr.aggr_byte_limit = + IPA_ODL_AGGR_BYTE_LIMIT; + ipa_odl_ep_cfg->ipa_ep_cfg.aggr.aggr_pkt_limit = 0; + + ipa_odl_ep_cfg->ipa_ep_cfg.hdr.hdr_len = 4; + ipa_odl_ep_cfg->ipa_ep_cfg.hdr.hdr_ofst_metadata_valid = 1; + ipa_odl_ep_cfg->ipa_ep_cfg.hdr.hdr_ofst_metadata = 1; + ipa_odl_ep_cfg->ipa_ep_cfg.hdr.hdr_ofst_pkt_size_valid = 1; + ipa_odl_ep_cfg->ipa_ep_cfg.hdr.hdr_ofst_pkt_size = 2; + + ipa_odl_ep_cfg->ipa_ep_cfg.hdr_ext.hdr_total_len_or_pad_valid = true; + ipa_odl_ep_cfg->ipa_ep_cfg.hdr_ext.hdr_total_len_or_pad = 0; + ipa_odl_ep_cfg->ipa_ep_cfg.hdr_ext.hdr_payload_len_inc_padding = true; + ipa_odl_ep_cfg->ipa_ep_cfg.hdr_ext.hdr_total_len_or_pad_offset = 0; + ipa_odl_ep_cfg->ipa_ep_cfg.hdr_ext.hdr_little_endian = 0; + ipa_odl_ep_cfg->ipa_ep_cfg.metadata_mask.metadata_mask = 0xFF000000; + + ipa_odl_ep_cfg->client = IPA_CLIENT_ODL_DPL_CONS; + ipa_odl_ep_cfg->notify = odl_ipa_packet_receive_notify; + + ipa_odl_ep_cfg->napi_obj = NULL; + ipa_odl_ep_cfg->desc_fifo_sz = IPA_ODL_RX_RING_SIZE * + IPA_FIFO_ELEMENT_SIZE; + ipa3_odl_ctx->odl_client_hdl = -1; + + /* For MHIP, ODL functionality is DMA. So bypass aggregation, checksum + * offload, hdr_len. + */ + if (ipa3_ctx->platform_type == IPA_PLAT_TYPE_APQ && + ipa3_is_mhip_offload_enabled()) { + IPADBG("MHIP enabled: bypass aggr + csum offload for ODL"); + ipa_odl_ep_cfg->ipa_ep_cfg.aggr.aggr_en = IPA_BYPASS_AGGR; + ipa_odl_ep_cfg->ipa_ep_cfg.cfg.cs_offload_en = + IPA_DISABLE_CS_OFFLOAD; + ipa_odl_ep_cfg->ipa_ep_cfg.hdr.hdr_len = 0; + } + + ret = ipa_setup_sys_pipe(ipa_odl_ep_cfg, + &ipa3_odl_ctx->odl_client_hdl); + return ret; + +} + +/** + * ipa3_odl_register_pm - Register odl client for PM + * + * This function will register 1 client with IPA PM to represent odl + * in clock scaling calculation: + * - "ODL" - this client will be activated when pipe connected + */ +static int ipa3_odl_register_pm(void) +{ + int result = 0; + struct ipa_pm_register_params pm_reg; + + memset(&pm_reg, 0, sizeof(pm_reg)); + pm_reg.name = "ODL"; + pm_reg.group = IPA_PM_GROUP_DEFAULT; + pm_reg.skip_clk_vote = true; + result = ipa_pm_register(&pm_reg, &ipa3_odl_ctx->odl_pm_hdl); + if (result) { + IPAERR("failed to create IPA PM client %d\n", result); + return result; + } + return result; +} + +int ipa3_odl_pipe_open(void) +{ + int ret = 0; + struct ipa_ep_cfg_holb holb_cfg; + + if(ipa3_ctx->ipa_hw_type < IPA_HW_v4_1) { + IPADBG("ODL not supported\n"); + return 0; + } + + if (!ipa3_odl_ctx->odl_state.adpl_open) { + IPAERR("adpl pipe not configured\n"); + return 0; + } + + if (atomic_read(&ipa3_ctx->is_ssr)) { + IPAERR("SSR in progress ODL pipe configuration not allowed\n"); + return 0; + } + + memset(&holb_cfg, 0, sizeof(holb_cfg)); + holb_cfg.tmr_val = 0; + holb_cfg.en = 1; + + ret = ipa_setup_odl_pipe(); + if (ret) { + IPAERR(" Setup endpoint config failed\n"); + ipa3_odl_ctx->odl_state.adpl_open = false; + goto fail; + } + ipa3_cfg_ep_holb_by_client(IPA_CLIENT_ODL_DPL_CONS, &holb_cfg); + ipa3_odl_ctx->odl_state.odl_ep_setup = true; + IPADBG("Setup endpoint config success\n"); + + ipa3_odl_ctx->stats.odl_drop_pkt = 0; + atomic_set(&ipa3_odl_ctx->stats.numer_in_queue, 0); + ipa3_odl_ctx->stats.odl_rx_pkt = 0; + ipa3_odl_ctx->stats.odl_tx_diag_pkt = 0; + /* + * Send signal to ipa_odl_ctl_fops_read, + * to send ODL ep open notification + */ + if (ipa3_is_mhip_offload_enabled()) { + IPADBG("MHIP is enabled, continue\n"); + ipa3_odl_ctx->odl_state.odl_open = true; + ipa3_odl_ctx->odl_state.odl_setup_done_sent = true; + ipa3_odl_ctx->odl_state.odl_ep_info_sent = true; + ipa3_odl_ctx->odl_state.odl_connected = true; + ipa3_odl_ctx->odl_state.odl_disconnected = false; + + /* Enable ADPL over ODL for MPM */ + ret = ipa3_mpm_enable_adpl_over_odl(true); + if (ret) { + IPAERR("mpm failed to enable ADPL over ODL %d\n", ret); + return ret; + } + } else { + ipa3_odl_ctx->odl_ctl_msg_wq_flag = true; + IPAERR("Wake up odl ctl\n"); + wake_up_interruptible(&odl_ctl_msg_wq); + if (ipa3_odl_ctx->odl_state.odl_disconnected) + ipa3_odl_ctx->odl_state.odl_disconnected = false; + } +fail: + return ret; + +} +static int ipa_adpl_open(struct inode *inode, struct file *filp) +{ + int ret = 0; + + IPADBG("Called the function :\n"); + mutex_lock(&ipa3_odl_ctx->pipe_lock); + if (ipa3_odl_ctx->odl_state.odl_init && + !ipa3_odl_ctx->odl_state.adpl_open) { + /* Activate ipa_pm*/ + ret = ipa_pm_activate_sync(ipa3_odl_ctx->odl_pm_hdl); + if (ret) + IPAERR("failed to activate pm\n"); + ipa3_odl_ctx->odl_state.adpl_open = true; + ret = ipa3_odl_pipe_open(); + } else { + IPAERR("Before odl init trying to open adpl pipe\n"); + print_ipa_odl_state_bit_mask(); + ret = -ENODEV; + } + mutex_unlock(&ipa3_odl_ctx->pipe_lock); + + return ret; +} + +static int ipa_adpl_release(struct inode *inode, struct file *filp) +{ + int ret = 0; + /* Deactivate ipa_pm */ + mutex_lock(&ipa3_odl_ctx->pipe_lock); + ret = ipa_pm_deactivate_sync(ipa3_odl_ctx->odl_pm_hdl); + if (ret) + IPAERR("failed to activate pm\n"); + ipa3_odl_pipe_cleanup(false); + + /* Disable ADPL over ODL for MPM */ + if (ipa3_is_mhip_offload_enabled()) { + ret = ipa3_mpm_enable_adpl_over_odl(false); + if (ret) + IPAERR("mpm failed to disable ADPL over ODL\n"); + + } + mutex_unlock(&ipa3_odl_ctx->pipe_lock); + + return ret; +} + +void ipa3_odl_pipe_open_from_ssr(void) +{ + mutex_lock(&ipa3_odl_ctx->pipe_lock); + ipa3_odl_pipe_open(); + mutex_unlock(&ipa3_odl_ctx->pipe_lock); +} + +void ipa3_odl_pipe_cleanup_from_ssr(void) +{ + mutex_lock(&ipa3_odl_ctx->pipe_lock); + ipa3_odl_pipe_cleanup(true); + mutex_unlock(&ipa3_odl_ctx->pipe_lock); +} + +void ipa3_odl_pipe_cleanup(bool is_ssr) +{ + bool ipa_odl_opened = false; + + if(ipa3_ctx->ipa_hw_type < IPA_HW_v4_1) { + IPADBG("ODL not supported\n"); + return; + } + + if (!ipa3_odl_ctx->odl_state.adpl_open) { + IPAERR("adpl pipe not configured\n"); + return; + } + + if(!ipa3_odl_ctx->odl_state.odl_ep_setup) { + IPAERR("adpl pipe setup not done\n"); + return; + } + + if (ipa3_odl_ctx->odl_state.odl_open) + ipa_odl_opened = true; + + memset(&ipa3_odl_ctx->odl_state, 0, sizeof(ipa3_odl_ctx->odl_state)); + + /*Since init will not be done again*/ + ipa3_odl_ctx->odl_state.odl_init = true; + + ipa_teardown_sys_pipe(ipa3_odl_ctx->odl_client_hdl); + ipa3_odl_ctx->odl_client_hdl = -1; + /*Assume QTI will never close this node once opened*/ + if (ipa_odl_opened) + ipa3_odl_ctx->odl_state.odl_open = true; + + /*Assume DIAG will not close this node in SSR case*/ + if (is_ssr) + ipa3_odl_ctx->odl_state.adpl_open = true; + else + ipa3_odl_ctx->odl_state.adpl_open = false; + + ipa3_odl_ctx->odl_state.odl_disconnected = true; + ipa3_odl_ctx->odl_state.odl_ep_setup = false; + ipa3_odl_ctx->odl_state.aggr_byte_limit_sent = false; + ipa3_odl_ctx->odl_state.odl_connected = false; + /* + * Send signal to ipa_odl_ctl_fops_read, + * to send ODL ep close notification + */ + ipa3_odl_ctx->odl_ctl_msg_wq_flag = true; + ipa3_odl_ctx->stats.odl_drop_pkt = 0; + atomic_set(&ipa3_odl_ctx->stats.numer_in_queue, 0); + ipa3_odl_ctx->stats.odl_rx_pkt = 0; + ipa3_odl_ctx->stats.odl_tx_diag_pkt = 0; + IPADBG("Wake up odl ctl\n"); + wake_up_interruptible(&odl_ctl_msg_wq); + +} + +/** + * ipa_adpl_read() - read message from IPA device + * @filp: [in] file pointer + * @buf: [out] buffer to read into + * @count: [in] size of above buffer + * @f_pos: [inout] file position + * + * User-space should continually read from /dev/ipa_adpl, + * read will block when there are no messages to read. + * Upon return, user-space should read + * Buffer supplied must be big enough to + * hold the data. + * + * Returns: how many bytes copied to buffer + * + * Note: Should not be called from atomic context + */ +static ssize_t ipa_adpl_read(struct file *filp, char __user *buf, size_t count, + loff_t *f_pos) +{ + int ret = 0; + char __user *start = buf; + struct ipa3_push_msg_odl *msg; + DEFINE_WAIT_FUNC(wait, woken_wake_function); + + add_wait_queue(&ipa3_odl_ctx->adpl_msg_waitq, &wait); + while (1) { + IPADBG_LOW("Writing message to adpl pipe\n"); + if (!ipa3_odl_ctx->odl_state.odl_open) + break; + + mutex_lock(&ipa3_odl_ctx->adpl_msg_lock); + msg = NULL; + if (!list_empty(&ipa3_odl_ctx->adpl_msg_list)) { + msg = list_first_entry(&ipa3_odl_ctx->adpl_msg_list, + struct ipa3_push_msg_odl, link); + list_del(&msg->link); + if (atomic_read(&ipa3_odl_ctx->stats.numer_in_queue)) + atomic_dec(&ipa3_odl_ctx->stats.numer_in_queue); + } + + mutex_unlock(&ipa3_odl_ctx->adpl_msg_lock); + + if (msg != NULL) { + if (msg->len > count) { + IPAERR("Message length greater than count\n"); + kfree(msg->buff); + kfree(msg); + msg = NULL; + ret = -EAGAIN; + break; + } + + if (msg->buff) { + if (copy_to_user(buf, msg->buff, + msg->len)) { + ret = -EFAULT; + kfree(msg->buff); + kfree(msg); + msg = NULL; + ret = -EAGAIN; + break; + } + buf += msg->len; + count -= msg->len; + kfree(msg->buff); + } + IPA_STATS_INC_CNT(ipa3_odl_ctx->stats.odl_tx_diag_pkt); + kfree(msg); + msg = NULL; + } + + ret = -EAGAIN; + if (filp->f_flags & O_NONBLOCK) + break; + + ret = -EINTR; + if (signal_pending(current)) + break; + + if (start != buf) + break; + wait_woken(&wait, TASK_INTERRUPTIBLE, MAX_SCHEDULE_TIMEOUT); + } + remove_wait_queue(&ipa3_odl_ctx->adpl_msg_waitq, &wait); + if (start != buf && ret != -EFAULT) + ret = buf - start; + + return ret; +} + +static long ipa_adpl_ioctl(struct file *filp, + unsigned int cmd, unsigned long arg) +{ + struct odl_agg_pipe_info odl_pipe_info; + int retval = 0; + + if (!ipa3_odl_ctx->odl_state.odl_connected) { + IPAERR("ODL config in progress not allowed ioctl\n"); + print_ipa_odl_state_bit_mask(); + retval = -ENODEV; + goto fail; + } + IPADBG("Calling adpl ioctl\n"); + + switch (cmd) { + case IPA_IOC_ODL_GET_AGG_BYTE_LIMIT: + odl_pipe_info.agg_byte_limit = + /*Modem expecting value in bytes. so passing 15 = 15*1024*/ + (ipa3_odl_ctx->odl_sys_param.ipa_ep_cfg.aggr.aggr_byte_limit * + 1024); + if (copy_to_user((void __user *)arg, &odl_pipe_info, + sizeof(odl_pipe_info))) { + retval = -EFAULT; + goto fail; + } + ipa3_odl_ctx->odl_state.aggr_byte_limit_sent = true; + break; + default: + retval = -ENOIOCTLCMD; + print_ipa_odl_state_bit_mask(); + break; + } + +fail: + return retval; +} + +static const struct file_operations ipa_odl_ctl_fops = { + .owner = THIS_MODULE, + .open = ipa_odl_ctl_fops_open, + .release = ipa_odl_ctl_fops_release, + .read = ipa_odl_ctl_fops_read, + .unlocked_ioctl = ipa_odl_ctl_fops_ioctl, + .poll = ipa_odl_ctl_fops_poll, +}; + +static const struct file_operations ipa_adpl_fops = { + .owner = THIS_MODULE, + .open = ipa_adpl_open, + .release = ipa_adpl_release, + .read = ipa_adpl_read, + .unlocked_ioctl = ipa_adpl_ioctl, +}; + +int ipa_odl_init(void) +{ + int result = 0; + struct cdev *cdev; + int loop = 0; + struct ipa3_odl_char_device_context *odl_cdev; + + ipa3_odl_ctx = kzalloc(sizeof(*ipa3_odl_ctx), GFP_KERNEL); + if (!ipa3_odl_ctx) { + result = -ENOMEM; + goto fail_mem_ctx; + } + + odl_cdev = ipa3_odl_ctx->odl_cdev; + INIT_LIST_HEAD(&ipa3_odl_ctx->adpl_msg_list); + init_waitqueue_head(&ipa3_odl_ctx->adpl_msg_waitq); + mutex_init(&ipa3_odl_ctx->adpl_msg_lock); + mutex_init(&ipa3_odl_ctx->pipe_lock); + + odl_cdev[loop].class = class_create(THIS_MODULE, "ipa_adpl"); + + if (IS_ERR(odl_cdev[loop].class)) { + IPAERR("Error: odl_cdev->class NULL\n"); + result = -ENODEV; + goto create_char_dev0_fail; + } + + result = alloc_chrdev_region(&odl_cdev[loop].dev_num, 0, 1, "ipa_adpl"); + if (result) { + IPAERR("alloc_chrdev_region error for ipa adpl pipe\n"); + result = -ENODEV; + goto alloc_chrdev0_region_fail; + } + + odl_cdev[loop].dev = device_create(odl_cdev[loop].class, NULL, + odl_cdev[loop].dev_num, ipa3_ctx, "ipa_adpl"); + if (IS_ERR(odl_cdev[loop].dev)) { + IPAERR("device_create err:%ld\n", PTR_ERR(odl_cdev[loop].dev)); + result = PTR_ERR(odl_cdev[loop].dev); + goto device0_create_fail; + } + + cdev = &odl_cdev[loop].cdev; + cdev_init(cdev, &ipa_adpl_fops); + cdev->owner = THIS_MODULE; + cdev->ops = &ipa_adpl_fops; + + result = cdev_add(cdev, odl_cdev[loop].dev_num, 1); + if (result) { + IPAERR("cdev_add err=%d\n", -result); + goto cdev0_add_fail; + } + + loop++; + + odl_cdev[loop].class = class_create(THIS_MODULE, "ipa_odl_ctl"); + + if (IS_ERR(odl_cdev[loop].class)) { + IPAERR("Error: odl_cdev->class NULL\n"); + result = -ENODEV; + goto create_char_dev1_fail; + } + + result = alloc_chrdev_region(&odl_cdev[loop].dev_num, 0, 1, + "ipa_odl_ctl"); + if (result) { + IPAERR("alloc_chrdev_region error for ipa odl ctl pipe\n"); + goto alloc_chrdev1_region_fail; + } + + odl_cdev[loop].dev = device_create(odl_cdev[loop].class, NULL, + odl_cdev[loop].dev_num, ipa3_ctx, "ipa_odl_ctl"); + if (IS_ERR(odl_cdev[loop].dev)) { + IPAERR("device_create err:%ld\n", PTR_ERR(odl_cdev[loop].dev)); + result = PTR_ERR(odl_cdev[loop].dev); + goto device1_create_fail; + } + + cdev = &odl_cdev[loop].cdev; + cdev_init(cdev, &ipa_odl_ctl_fops); + cdev->owner = THIS_MODULE; + cdev->ops = &ipa_odl_ctl_fops; + + result = cdev_add(cdev, odl_cdev[loop].dev_num, 1); + if (result) { + IPAERR(":cdev_add err=%d\n", -result); + goto cdev1_add_fail; + } + + ipa3_odl_ctx->odl_state.odl_init = true; + + /* register ipa_pm */ + result = ipa3_odl_register_pm(); + if (result) { + IPAWANERR("ipa3_odl_register_pm failed, ret: %d\n", + result); + } + return 0; +cdev1_add_fail: + device_destroy(odl_cdev[1].class, odl_cdev[1].dev_num); +device1_create_fail: + unregister_chrdev_region(odl_cdev[1].dev_num, 1); +alloc_chrdev1_region_fail: + class_destroy(odl_cdev[1].class); +create_char_dev1_fail: +cdev0_add_fail: + device_destroy(odl_cdev[0].class, odl_cdev[0].dev_num); +device0_create_fail: + unregister_chrdev_region(odl_cdev[0].dev_num, 1); +alloc_chrdev0_region_fail: + class_destroy(odl_cdev[0].class); +create_char_dev0_fail: + kfree(ipa3_odl_ctx); + ipa3_odl_ctx = NULL; +fail_mem_ctx: + return result; +} + +void ipa_odl_cleanup(void) +{ + struct ipa3_odl_char_device_context *odl_cdev; + + if (!ipa3_odl_ctx) + return; + + odl_cdev = ipa3_odl_ctx->odl_cdev; + + ipa_pm_deregister(ipa3_odl_ctx->odl_pm_hdl); + device_destroy(odl_cdev[1].class, odl_cdev[1].dev_num); + unregister_chrdev_region(odl_cdev[1].dev_num, 1); + class_destroy(odl_cdev[1].class); + device_destroy(odl_cdev[0].class, odl_cdev[0].dev_num); + unregister_chrdev_region(odl_cdev[0].dev_num, 1); + class_destroy(odl_cdev[0].class); + kfree(ipa3_odl_ctx); + ipa3_odl_ctx = NULL; +} + +bool ipa3_is_odl_connected(void) +{ + return ipa3_odl_ctx->odl_state.odl_connected; +} diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_odl.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_odl.h new file mode 100644 index 0000000000..3a0a361618 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_odl.h @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _IPA3_ODL_H_ +#define _IPA3_ODL_H_ + +#define IPA_ODL_AGGR_BYTE_LIMIT 15 +#define IPA_ODL_RX_RING_SIZE 192 +#define MAX_QUEUE_TO_ODL 1024 +#define CONFIG_SUCCESS 1 +#define ODL_EP_TYPE_HSUSB 2 +#define ODL_EP_PERIPHERAL_IFACE_ID 3 + +struct ipa3_odlstats { + u32 odl_rx_pkt; + u32 odl_tx_diag_pkt; + u32 odl_drop_pkt; + atomic_t numer_in_queue; +}; + +struct odl_state_bit_mask { + u32 odl_init:1; + u32 odl_open:1; + u32 adpl_open:1; + u32 aggr_byte_limit_sent:1; + u32 odl_ep_setup:1; + u32 odl_setup_done_sent:1; + u32 odl_ep_info_sent:1; + u32 odl_connected:1; + u32 odl_disconnected:1; + u32:0; +}; + +/** + * struct ipa3_odl_char_device_context - IPA ODL character device + * @class: pointer to the struct class + * @dev_num: device number + * @dev: the dev_t of the device + * @cdev: cdev of the device + */ +struct ipa3_odl_char_device_context { + struct class *class; + dev_t dev_num; + struct device *dev; + struct cdev cdev; +}; + +struct ipa_odl_context { + struct ipa3_odl_char_device_context odl_cdev[2]; + struct list_head adpl_msg_list; + struct mutex adpl_msg_lock; + struct mutex pipe_lock; + struct ipa_sys_connect_params odl_sys_param; + u32 odl_client_hdl; + struct odl_state_bit_mask odl_state; + bool odl_ctl_msg_wq_flag; + struct ipa3_odlstats stats; + u32 odl_pm_hdl; + wait_queue_head_t adpl_msg_waitq; +}; + +struct ipa3_push_msg_odl { + void *buff; + int len; + struct list_head link; +}; + +extern struct ipa_odl_context *ipa3_odl_ctx; + +int ipa_odl_init(void); +void ipa_odl_cleanup(void); +void ipa3_odl_pipe_cleanup(bool is_ssr); +int ipa3_odl_pipe_open(void); +void ipa3_odl_pipe_open_from_ssr(void); +void ipa3_odl_pipe_cleanup_from_ssr(void); +#endif /* _IPA3_ODL_H_ */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_pm.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_pm.c new file mode 100644 index 0000000000..8e3cb8b47d --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_pm.c @@ -0,0 +1,1718 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. + */ + +#include +#include "ipa_pm.h" +#include "ipa_stats.h" +#include "ipa_i.h" + + +#define IPA_PM_DRV_NAME "ipa_pm" + +#define IPA_PM_DBG(fmt, args...) \ + do { \ + pr_debug(IPA_PM_DRV_NAME " %s:%d " fmt, \ + __func__, __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf(), \ + IPA_PM_DRV_NAME " %s:%d " fmt, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf_low(), \ + IPA_PM_DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) +#define IPA_PM_DBG_LOW(fmt, args...) \ + do { \ + pr_debug(IPA_PM_DRV_NAME " %s:%d " fmt, \ + __func__, __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf_low(), \ + IPA_PM_DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) +#define IPA_PM_ERR(fmt, args...) \ + do { \ + pr_err(IPA_PM_DRV_NAME " %s:%d " fmt, \ + __func__, __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf(), \ + IPA_PM_DRV_NAME " %s:%d " fmt, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf_low(), \ + IPA_PM_DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) +#define IPA_PM_ERR_RL(fmt, args...) \ + do { \ + pr_err_ratelimited_ipa(IPA_PM_DRV_NAME " %s:%d " fmt, \ + __func__, __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf(), \ + IPA_PM_DRV_NAME " %s:%d " fmt, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf_low(), \ + IPA_PM_DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) +#define IPA_PM_DBG_STATE(hdl, name, state) \ + IPA_PM_DBG_LOW("Client[%d] %s: %s\n", hdl, name, \ + client_state_to_str[state]) + +/* + * struct ipa_pm_exception_list - holds information about an exception + * @pending: number of clients in exception that have not yet been adctivated + * @bitmask: bitmask of the clients in the exception based on handle + * @threshold: the threshold values for the exception + */ +struct ipa_pm_exception_list { + char clients[IPA_PM_MAX_EX_CL]; + int pending; + u32 bitmask[IPA5_PIPE_REG_NUM]; + int threshold[IPA_PM_THRESHOLD_MAX]; +}; + +/* + * struct clk_scaling_db - holds information about threshholds and exceptions + * @lock: lock the bitmasks and thresholds + * @exception_list: pointer to the list of exceptions + * @work: work for clock scaling algorithm + * @active_client_bitmask: the bits represent handles in the clients array that + * contain non-null client + * @threshold_size: size of the throughput threshold + * @exception_size: size of the exception list + * @cur_vote: idx of the threshold + * @default_threshold: the thresholds used if no exception passes + * @current_threshold: the current threshold of the clock plan + */ +struct clk_scaling_db { + spinlock_t lock; + struct ipa_pm_exception_list exception_list[IPA_PM_EXCEPTION_MAX]; + struct work_struct work; + u32 active_client_bitmask[IPA5_PIPE_REG_NUM]; + int threshold_size; + int exception_size; + int cur_vote; + int default_threshold[IPA_PM_THRESHOLD_MAX]; + int *current_threshold; +}; + +/* + * ipa_pm state names + * + * Timer free states: + * @IPA_PM_DEACTIVATED: client starting state when registered + * @IPA_PM_DEACTIVATE_IN_PROGRESS: deactivate was called in progress of a client + * activating + * @IPA_PM_ACTIVATE_IN_PROGRESS: client is being activated by work_queue + * @IPA_PM_ACTIVATED: client is activated without any timers + * + * Timer set states: + * @IPA_PM_ACTIVATED_PENDING_DEACTIVATION: moves to deactivate once timer pass + * @IPA_PM_ACTIVATED_TIMER_SET: client was activated while timer was set, so + * when the timer pass, client will still be activated + *@IPA_PM_ACTIVATED_PENDING_RESCHEDULE: state signifying extended timer when + * a client is deferred_deactivated when a time ris still active + */ +enum ipa_pm_state { + IPA_PM_DEACTIVATED, + IPA_PM_DEACTIVATE_IN_PROGRESS, + IPA_PM_ACTIVATE_IN_PROGRESS, + IPA_PM_ACTIVATED, + IPA_PM_ACTIVATED_PENDING_DEACTIVATION, + IPA_PM_ACTIVATED_TIMER_SET, + IPA_PM_ACTIVATED_PENDING_RESCHEDULE, + IPA_PM_STATE_MAX +}; + +#define IPA_PM_STATE_ACTIVE(state) \ + (state == IPA_PM_ACTIVATED ||\ + state == IPA_PM_ACTIVATED_PENDING_DEACTIVATION ||\ + state == IPA_PM_ACTIVATED_TIMER_SET ||\ + state == IPA_PM_ACTIVATED_PENDING_RESCHEDULE) + +#define IPA_PM_STATE_IN_PROGRESS(state) \ + (state == IPA_PM_ACTIVATE_IN_PROGRESS \ + || state == IPA_PM_DEACTIVATE_IN_PROGRESS) + +/* + * struct ipa_pm_client - holds information about a specific IPA client + * @name: string name of the client + * @callback: pointer to the client's callback function + * @callback_params: pointer to the client's callback parameters + * @state: Activation state of the client + * @skip_clk_vote: 0 if client votes for clock when activated, 1 if no vote + * @group: the ipa_pm_group the client belongs to + * @hdl: handle of the client + * @throughput: the throughput of the client for clock scaling + * @state_lock: spinlock to lock the pm_states + * @activate_work: work for activate (blocking case) + * @deactivate work: delayed work for deferred_deactivate function + * @complete: generic wait-for-completion handler + * @wlock: wake source to prevent AP suspend + */ +struct ipa_pm_client { + char name[IPA_PM_MAX_EX_CL]; + void (*callback)(void *user_data, enum ipa_pm_cb_event); + void *callback_params; + enum ipa_pm_state state; + bool skip_clk_vote; + int group; + int hdl; + int throughput; + spinlock_t state_lock; + struct work_struct activate_work; + struct delayed_work deactivate_work; + struct completion complete; + struct wakeup_source *wlock; +}; + +/* + * struct ipa_pm_ctx - global ctx that will hold the client arrays and tput info + * @clients: array to the clients with the handle as its index + * @clients_by_pipe: array to the clients with endpoint as the index + * @wq: work queue for deferred deactivate, activate, and clk_scaling work + 8 @clk_scaling: pointer to clock scaling database + * @client_mutex: global mutex to lock the client arrays + * @aggragated_tput: aggragated tput value of all valid activated clients + * @group_tput: combined throughput for the groups + */ +struct ipa_pm_ctx { + struct ipa_pm_client *clients[IPA_PM_MAX_CLIENTS]; + struct ipa_pm_client *clients_by_pipe[IPA5_PIPES_NUM]; + struct workqueue_struct *wq; + struct clk_scaling_db clk_scaling; + struct mutex client_mutex; + int aggregated_tput; + int group_tput[IPA_PM_GROUP_MAX]; +}; + +static struct ipa_pm_ctx *ipa_pm_ctx; + +static const char *client_state_to_str[IPA_PM_STATE_MAX] = { + __stringify(IPA_PM_DEACTIVATED), + __stringify(IPA_PM_DEACTIVATE_IN_PROGRESS), + __stringify(IPA_PM_ACTIVATE_IN_PROGRESS), + __stringify(IPA_PM_ACTIVATED), + __stringify(IPA_PM_ACTIVATED_PENDING_DEACTIVATION), + __stringify(IPA_PM_ACTIVATED_TIMER_SET), + __stringify(IPA_PM_ACTIVATED_PENDING_RESCHEDULE), +}; + +static const char *ipa_pm_group_to_str[IPA_PM_GROUP_MAX] = { + __stringify(IPA_PM_GROUP_DEFAULT), + __stringify(IPA_PM_GROUP_APPS), + __stringify(IPA_PM_GROUP_MODEM), +}; + +static int dummy_hdl_1, dummy_hdl_2, tput_modem, tput_apps; + +/** + * pop_max_from_array() -pop the max and move the last element to where the + * max was popped + * @arr: array to be searched for max + * @n: size of the array + * + * Returns: max value of the array + */ +static int pop_max_from_array(int *arr, int *n) +{ + int i; + int max, max_idx; + + max_idx = *n - 1; + max = 0; + + if (*n == 0) + return 0; + + for (i = 0; i < *n; i++) { + if (arr[i] > max) { + max = arr[i]; + max_idx = i; + } + } + (*n)--; + arr[max_idx] = arr[*n]; + + return max; +} + +/** + * calculate_throughput() - calculate the aggregated throughput + * based on active clients + * + * Returns: aggregated tput value + */ +static int calculate_throughput(void) +{ + int client_tput[IPA_PM_MAX_CLIENTS] = { 0 }; + bool group_voted[IPA_PM_GROUP_MAX] = { false }; + int i, n; + int max, second_max, aggregated_tput; + struct ipa_pm_client *client; + + /* Create a basic array to hold throughputs*/ + for (i = 1, n = 0; i < IPA_PM_MAX_CLIENTS; i++) { + client = ipa_pm_ctx->clients[i]; + if (client != NULL && IPA_PM_STATE_ACTIVE(client->state)) { + /* default case */ + if (client->group == IPA_PM_GROUP_DEFAULT) { + client_tput[n++] = client->throughput; + } else if (!group_voted[client->group]) { + client_tput[n++] = ipa_pm_ctx->group_tput + [client->group]; + group_voted[client->group] = true; + } + } + } + /*the array will only use n+1 spots. n will be the last index used*/ + + aggregated_tput = 0; + + /** + * throughput algorithm: + * 1) pop the max and second_max + * 2) add the 2nd max to aggregated tput + * 3) insert the value of max - 2nd max + * 4) repeat until array is of size 1 + */ + while (n > 1) { + max = pop_max_from_array(client_tput, &n); + second_max = pop_max_from_array(client_tput, &n); + client_tput[n++] = max - second_max; + aggregated_tput += second_max; + } + + IPA_PM_DBG_LOW("Aggregated throughput: %d\n", aggregated_tput); + + return aggregated_tput; +} + +/** + * deactivate_client() - turn off the bit in the active client bitmask based on + * the handle passed in + * @hdl: The index of the client to be deactivated + */ +static void deactivate_client(u32 hdl) +{ + unsigned long flags; + int idx = ipahal_get_ep_reg_idx(hdl); + + spin_lock_irqsave(&ipa_pm_ctx->clk_scaling.lock, flags); + ipa_pm_ctx->clk_scaling.active_client_bitmask[idx] &= + ~(ipahal_get_ep_bit(hdl)); + spin_unlock_irqrestore(&ipa_pm_ctx->clk_scaling.lock, flags); + IPA_PM_DBG_LOW("active bitmask (%d): %x\n", + idx, ipa_pm_ctx->clk_scaling.active_client_bitmask[idx]); +} + +/** + * activate_client() - turn on the bit in the active client bitmask based on + * the handle passed in + * @hdl: The index of the client to be activated + */ +static void activate_client(u32 hdl) +{ + unsigned long flags; + int idx = ipahal_get_ep_reg_idx(hdl); + + spin_lock_irqsave(&ipa_pm_ctx->clk_scaling.lock, flags); + ipa_pm_ctx->clk_scaling.active_client_bitmask[idx] |= + (ipahal_get_ep_bit(hdl)); + spin_unlock_irqrestore(&ipa_pm_ctx->clk_scaling.lock, flags); + IPA_PM_DBG_LOW("active bitmask (%d): %x\n", + idx, ipa_pm_ctx->clk_scaling.active_client_bitmask[idx]); +} + +/** + * deactivate_client() - get threshold + * + * Returns: threshold of the exception that passes or default if none pass + */ +static void set_current_threshold(void) +{ + int i; + struct clk_scaling_db *clk; + struct ipa_pm_exception_list *exception; + unsigned long flags; + + clk = &ipa_pm_ctx->clk_scaling; + + spin_lock_irqsave(&ipa_pm_ctx->clk_scaling.lock, flags); + for (i = 0; i < clk->exception_size; i++) { + exception = &clk->exception_list[i]; + if (exception->pending == 0 && ((exception->bitmask[0] + & ~clk->active_client_bitmask[0]) == 0) && + ((exception->bitmask[1] & + ~clk->active_client_bitmask[1]) == 0)) { + spin_unlock_irqrestore(&ipa_pm_ctx->clk_scaling.lock, + flags); + clk->current_threshold = exception->threshold; + IPA_PM_DBG("Exception %d set\n", i); + return; + } + } + clk->current_threshold = clk->default_threshold; + spin_unlock_irqrestore(&ipa_pm_ctx->clk_scaling.lock, flags); +} + +/** + * do_clk_scaling() - set the clock based on the activated clients + * + * Returns: 0 if success, negative otherwise + */ +static int do_clk_scaling(void) +{ + int i, tput; + int new_th_idx = 1; + struct clk_scaling_db *clk_scaling; + + if (atomic_read(&ipa3_ctx->ipa_clk_vote) == 0) { + IPA_PM_DBG("IPA clock is gated\n"); + return 0; + } + + clk_scaling = &ipa_pm_ctx->clk_scaling; + + mutex_lock(&ipa_pm_ctx->client_mutex); + IPA_PM_DBG_LOW("clock scaling started\n"); + tput = calculate_throughput(); + ipa_pm_ctx->aggregated_tput = tput; + set_current_threshold(); + + mutex_unlock(&ipa_pm_ctx->client_mutex); + + for (i = 0; i < clk_scaling->threshold_size; i++) { + if (tput >= clk_scaling->current_threshold[i]) + new_th_idx++; + } + + IPA_PM_DBG_LOW("old idx was at %d\n", ipa_pm_ctx->clk_scaling.cur_vote); + + + if (ipa_pm_ctx->clk_scaling.cur_vote != new_th_idx) { + ipa_pm_ctx->clk_scaling.cur_vote = new_th_idx; + ipa3_set_clock_plan_from_pm(ipa_pm_ctx->clk_scaling.cur_vote); + } + + IPA_PM_DBG_LOW("new idx is at %d\n", ipa_pm_ctx->clk_scaling.cur_vote); + + return 0; +} + +/** + * clock_scaling_func() - set the clock on a work queue + */ +static void clock_scaling_func(struct work_struct *work) +{ + do_clk_scaling(); +} + +/** + * activate_work_func - activate a client and vote for clock on a work queue + */ +static void activate_work_func(struct work_struct *work) +{ + struct ipa_pm_client *client; + bool dec_clk = false; + unsigned long flags; + + client = container_of(work, struct ipa_pm_client, activate_work); + if (!client->skip_clk_vote) { + IPA_ACTIVE_CLIENTS_INC_SPECIAL(client->name); + if (client->group == IPA_PM_GROUP_APPS) + __pm_stay_awake(client->wlock); + } + + spin_lock_irqsave(&client->state_lock, flags); + IPA_PM_DBG_STATE(client->hdl, client->name, client->state); + if (client->state == IPA_PM_ACTIVATE_IN_PROGRESS) { + client->state = IPA_PM_ACTIVATED; + } else if (client->state == IPA_PM_DEACTIVATE_IN_PROGRESS) { + client->state = IPA_PM_DEACTIVATED; + dec_clk = true; + } else { + IPA_PM_ERR("unexpected state %d\n", client->state); + WARN_ON(1); + } + spin_unlock_irqrestore(&client->state_lock, flags); + + complete_all(&client->complete); + + if (dec_clk) { + if (!client->skip_clk_vote) { + IPA_ACTIVE_CLIENTS_DEC_SPECIAL(client->name); + if (client->group == IPA_PM_GROUP_APPS) + __pm_relax(client->wlock); + } + + IPA_PM_DBG_STATE(client->hdl, client->name, client->state); + return; + } + + activate_client(client->hdl); + + mutex_lock(&ipa_pm_ctx->client_mutex); + if (client->callback) { + client->callback(client->callback_params, + IPA_PM_CLIENT_ACTIVATED); + } + mutex_unlock(&ipa_pm_ctx->client_mutex); + + IPA_PM_DBG_STATE(client->hdl, client->name, client->state); + do_clk_scaling(); +} + +/** + * delayed_deferred_deactivate_work_func - deferred deactivate on a work queue + */ +static void delayed_deferred_deactivate_work_func(struct work_struct *work) +{ + struct delayed_work *dwork; + struct ipa_pm_client *client; + unsigned long flags; + unsigned long delay; + + dwork = container_of(work, struct delayed_work, work); + client = container_of(dwork, struct ipa_pm_client, deactivate_work); + + if (unlikely(client == NULL)) { + IPA_PM_ERR("Client already deregistered\n"); + return; + } + + spin_lock_irqsave(&client->state_lock, flags); + IPA_PM_DBG_STATE(client->hdl, client->name, client->state); + switch (client->state) { + case IPA_PM_ACTIVATED_TIMER_SET: + client->state = IPA_PM_ACTIVATED; + goto bail; + case IPA_PM_ACTIVATED_PENDING_RESCHEDULE: + delay = IPA_PM_DEFERRED_TIMEOUT; + if (ipa3_ctx->ipa3_hw_mode == IPA_HW_MODE_VIRTUAL || + ipa3_ctx->ipa3_hw_mode == IPA_HW_MODE_EMULATION) + delay *= 5; + + queue_delayed_work(ipa_pm_ctx->wq, &client->deactivate_work, + msecs_to_jiffies(delay)); + client->state = IPA_PM_ACTIVATED_PENDING_DEACTIVATION; + goto bail; + case IPA_PM_ACTIVATED_PENDING_DEACTIVATION: + client->state = IPA_PM_DEACTIVATED; + IPA_PM_DBG_STATE(client->hdl, client->name, client->state); + spin_unlock_irqrestore(&client->state_lock, flags); + if (!client->skip_clk_vote) { + IPA_ACTIVE_CLIENTS_DEC_SPECIAL(client->name); + if (client->group == IPA_PM_GROUP_APPS) + __pm_relax(client->wlock); + } + + deactivate_client(client->hdl); + do_clk_scaling(); + return; + default: + IPA_PM_ERR("unexpected state %d\n", client->state); + WARN_ON(1); + goto bail; + } + +bail: + IPA_PM_DBG_STATE(client->hdl, client->name, client->state); + spin_unlock_irqrestore(&client->state_lock, flags); +} + +static int find_next_open_array_element(const char *name) +{ + int i, n; + + n = -ENOBUFS; + + /* 0 is not a valid handle */ + for (i = IPA_PM_MAX_CLIENTS - 1; i >= 1; i--) { + if (ipa_pm_ctx->clients[i] == NULL) { + n = i; + continue; + } + + if (strlen(name) == strlen(ipa_pm_ctx->clients[i]->name)) + if (!strcmp(name, ipa_pm_ctx->clients[i]->name)) + return -EEXIST; + } + return n; +} + +/** + * add_client_to_exception_list() - add client to the exception list and + * update pending if necessary + * @hdl: index of the IPA client + * + * Returns: 0 if success, negative otherwise + */ +static int add_client_to_exception_list(u32 hdl) +{ + int i, len = 0; + struct ipa_pm_exception_list *exception; + + mutex_lock(&ipa_pm_ctx->client_mutex); + len = strlen(ipa_pm_ctx->clients[hdl]->name); + for (i = 0; i < ipa_pm_ctx->clk_scaling.exception_size; i++) { + exception = &ipa_pm_ctx->clk_scaling.exception_list[i]; + if (strnstr(exception->clients, ipa_pm_ctx->clients[hdl]->name, + len) && (strlen(exception->clients) + == len)) { + exception->pending--; + IPA_PM_DBG("Pending: %d\n", + exception->pending); + + if (exception->pending < 0) { + WARN_ON(1); + exception->pending = 0; + mutex_unlock(&ipa_pm_ctx->client_mutex); + return -EPERM; + } + exception->bitmask[ipahal_get_ep_reg_idx(hdl)] |= + (ipahal_get_ep_bit(hdl)); + } + } + IPA_PM_DBG("%s added to exception list\n", + ipa_pm_ctx->clients[hdl]->name); + mutex_unlock(&ipa_pm_ctx->client_mutex); + + return 0; +} + +/** + * remove_client_to_exception_list() - remove client from the exception list and + * update pending if necessary + * @hdl: index of the IPA client + * + * Returns: 0 if success, negative otherwise + */ +static int remove_client_from_exception_list(u32 hdl) +{ + int i; + struct ipa_pm_exception_list *exception; + int idx; + u32 ep_bit; + + idx = ipahal_get_ep_reg_idx(hdl); + ep_bit = ipahal_get_ep_bit(hdl); + for (i = 0; i < ipa_pm_ctx->clk_scaling.exception_size; i++) { + exception = &ipa_pm_ctx->clk_scaling.exception_list[i]; + if (exception->bitmask[idx] & (ep_bit)) { + exception->pending++; + IPA_PM_DBG("Pending: %d\n", + exception->pending); + exception->bitmask[idx] &= ~(ep_bit); + } + } + IPA_PM_DBG("Client %d removed from exception list\n", hdl); + + return 0; +} + +/** + * ipa_pm_init() - initialize IPA PM Components + * @ipa_pm_init_params: parameters needed to fill exceptions and thresholds + * + * Returns: 0 on success, negative on failure + */ +int ipa_pm_init(struct ipa_pm_init_params *params) +{ + int i, j; + struct clk_scaling_db *clk_scaling; +#if IS_ENABLED(CONFIG_QCOM_VA_MINIDUMP) + struct ipa_minidump_data *mini_dump; +#endif + + if (params == NULL) { + IPA_PM_ERR("Invalid Params\n"); + return -EINVAL; + } + + if (params->threshold_size <= 0 + || params->threshold_size > IPA_PM_THRESHOLD_MAX) { + IPA_PM_ERR("Invalid threshold size\n"); + return -EINVAL; + } + + if (params->exception_size < 0 + || params->exception_size > IPA_PM_EXCEPTION_MAX) { + IPA_PM_ERR("Invalid exception size\n"); + return -EINVAL; + } + + IPA_PM_DBG("IPA PM initialization started\n"); + + if (ipa_pm_ctx != NULL) { + IPA_PM_ERR("Already initialized\n"); + return -EPERM; + } + + + ipa_pm_ctx = kzalloc(sizeof(*ipa_pm_ctx), GFP_KERNEL); + if (!ipa_pm_ctx) { + IPA_PM_ERR(":kzalloc err.\n"); + return -ENOMEM; + } + + ipa_pm_ctx->wq = create_singlethread_workqueue("ipa_pm_activate"); + if (!ipa_pm_ctx->wq) { + IPA_PM_ERR("create workqueue failed\n"); + kfree(ipa_pm_ctx); + ipa_pm_ctx = NULL; + return -ENOMEM; + } + + mutex_init(&ipa_pm_ctx->client_mutex); + + /* Populate and init locks in clk_scaling_db */ + clk_scaling = &ipa_pm_ctx->clk_scaling; + spin_lock_init(&clk_scaling->lock); + clk_scaling->threshold_size = params->threshold_size; + clk_scaling->exception_size = params->exception_size; + INIT_WORK(&clk_scaling->work, clock_scaling_func); + + for (i = 0; i < params->threshold_size; i++) + clk_scaling->default_threshold[i] = + params->default_threshold[i]; + + /* Populate exception list*/ + for (i = 0; i < params->exception_size; i++) { + strlcpy(clk_scaling->exception_list[i].clients, + params->exceptions[i].usecase, IPA_PM_MAX_EX_CL); + IPA_PM_DBG("Usecase: %s\n", params->exceptions[i].usecase); + + /* Parse the commas to count the size of the clients */ + for (j = 0; j < IPA_PM_MAX_EX_CL && + clk_scaling->exception_list[i].clients[j]; j++) { + if (clk_scaling->exception_list[i].clients[j] == ',') + clk_scaling->exception_list[i].pending++; + } + + /* for the first client */ + clk_scaling->exception_list[i].pending++; + IPA_PM_DBG("Pending: %d\n", + clk_scaling->exception_list[i].pending); + + /* populate the threshold */ + for (j = 0; j < params->threshold_size; j++) { + clk_scaling->exception_list[i].threshold[j] + = params->exceptions[i].threshold[j]; + } + + } + IPA_PM_DBG("initialization success"); + +#if IS_ENABLED(CONFIG_QCOM_VA_MINIDUMP) + /*Adding ipa3_ctx pointer to minidump list*/ + mini_dump = (struct ipa_minidump_data *)kzalloc(sizeof(struct ipa_minidump_data), GFP_KERNEL); + if (mini_dump != NULL) { + strlcpy(mini_dump->data.owner, "ipa_pm_ctx", sizeof(mini_dump->data.owner)); + mini_dump->data.vaddr = (unsigned long)(ipa_pm_ctx); + mini_dump->data.size = sizeof(*ipa_pm_ctx); + list_add(&mini_dump->entry, &ipa3_ctx->minidump_list_head); + } +#endif + + return 0; +} + +int ipa_pm_destroy(void) +{ + IPA_PM_DBG("IPA PM destroy started\n"); + + if (ipa_pm_ctx == NULL) { + IPA_PM_ERR("Already destroyed\n"); + return -EPERM; + } + + destroy_workqueue(ipa_pm_ctx->wq); + + kfree(ipa_pm_ctx); + ipa_pm_ctx = NULL; + + return 0; +} + +/** + * ipa_pm_register() - register an IPA PM client with the PM + * @register_params: params for a client like throughput, callback, etc. + * @hdl: int pointer that will be used as an index to access the client + * + * Returns: 0 on success, negative on failure + * + * Side effects: *hdl is replaced with the client index or -EEXIST if + * client is already registered + */ +int ipa_pm_register(struct ipa_pm_register_params *params, u32 *hdl) +{ + struct ipa_pm_client *client; + int elem; + + if (ipa_pm_ctx == NULL) { + IPA_PM_ERR("PM_ctx is null\n"); + return -EINVAL; + } + + if (params == NULL || hdl == NULL || params->name == NULL) { + IPA_PM_ERR("Invalid Params\n"); + return -EINVAL; + } + + IPA_PM_DBG("IPA PM registering client\n"); + + mutex_lock(&ipa_pm_ctx->client_mutex); + + elem = find_next_open_array_element(params->name); + *hdl = elem; + if (elem < 0 || elem > IPA_PM_MAX_CLIENTS) { + mutex_unlock(&ipa_pm_ctx->client_mutex); + IPA_PM_ERR("client already registered or full array elem=%d\n", + elem); + return elem; + } + + ipa_pm_ctx->clients[*hdl] = kzalloc(sizeof + (struct ipa_pm_client), GFP_KERNEL); + if (!ipa_pm_ctx->clients[*hdl]) { + mutex_unlock(&ipa_pm_ctx->client_mutex); + IPA_PM_ERR(":kzalloc err.\n"); + return -ENOMEM; + } + mutex_unlock(&ipa_pm_ctx->client_mutex); + + client = ipa_pm_ctx->clients[*hdl]; + + spin_lock_init(&client->state_lock); + + INIT_DELAYED_WORK(&client->deactivate_work, + delayed_deferred_deactivate_work_func); + + INIT_WORK(&client->activate_work, activate_work_func); + + /* populate fields */ + strlcpy(client->name, params->name, IPA_PM_MAX_EX_CL); + client->callback = params->callback; + client->callback_params = params->user_data; + client->group = params->group; + client->hdl = *hdl; + client->skip_clk_vote = params->skip_clk_vote; + client->wlock = wakeup_source_register(NULL, client->name); + if (!client->wlock) { + ipa_pm_deregister(*hdl); + IPA_PM_ERR("IPA wakeup source register failed %s\n", + client->name); + return -ENOMEM; + } + + init_completion(&client->complete); + + /* add client to exception list */ + if (add_client_to_exception_list(*hdl)) { + ipa_pm_deregister(*hdl); + IPA_PM_ERR("Fail to add client to exception_list\n"); + return -EPERM; + } + + IPA_PM_DBG("IPA PM client registered with handle %d\n", *hdl); + return 0; +} +EXPORT_SYMBOL(ipa_pm_register); + +/** + * ipa_pm_deregister() - deregister IPA client from the PM + * @hdl: index of the client in the array + * + * Returns: 0 on success, negative on failure + */ +int ipa_pm_deregister(u32 hdl) +{ + struct ipa_pm_client *client; + int i; + unsigned long flags; + + if (ipa_pm_ctx == NULL) { + IPA_PM_ERR("PM_ctx is null\n"); + return -EINVAL; + } + + if (hdl >= IPA_PM_MAX_CLIENTS) { + IPA_PM_ERR("Invalid Param\n"); + return -EINVAL; + } + + if (ipa_pm_ctx->clients[hdl] == NULL) { + IPA_PM_ERR("Client is Null\n"); + return -EINVAL; + } + + IPA_PM_DBG("IPA PM deregistering client\n"); + + client = ipa_pm_ctx->clients[hdl]; + spin_lock_irqsave(&client->state_lock, flags); + if (IPA_PM_STATE_IN_PROGRESS(client->state)) { + spin_unlock_irqrestore(&client->state_lock, flags); + wait_for_completion(&client->complete); + spin_lock_irqsave(&client->state_lock, flags); + } + + if (IPA_PM_STATE_ACTIVE(client->state)) { + IPA_PM_DBG("Activated clients cannot be deregistered"); + spin_unlock_irqrestore(&client->state_lock, flags); + return -EPERM; + } + spin_unlock_irqrestore(&client->state_lock, flags); + + mutex_lock(&ipa_pm_ctx->client_mutex); + + /* nullify pointers in pipe array */ + for (i = 0; i < ipa3_get_max_num_pipes(); i++) { + if (ipa_pm_ctx->clients_by_pipe[i] == ipa_pm_ctx->clients[hdl]) + ipa_pm_ctx->clients_by_pipe[i] = NULL; + } + wakeup_source_unregister(client->wlock); + kfree(client); + ipa_pm_ctx->clients[hdl] = NULL; + + remove_client_from_exception_list(hdl); + IPA_PM_DBG("IPA PM client %d deregistered\n", hdl); + mutex_unlock(&ipa_pm_ctx->client_mutex); + + return 0; +} +EXPORT_SYMBOL(ipa_pm_deregister); + +/** + * ipa_pm_associate_ipa_cons_to_client() - add mapping to pipe with ipa cllent + * @hdl: index of the client to be mapped + * @consumer: the pipe/consumer name to be pipped to the client + * + * Returns: 0 on success, negative on failure + * + * Side effects: multiple pipes are allowed to be mapped to a single client + */ +int ipa_pm_associate_ipa_cons_to_client(u32 hdl, enum ipa_client_type consumer) +{ + int idx; + + if (ipa_pm_ctx == NULL) { + IPA_PM_ERR("PM_ctx is null\n"); + return -EINVAL; + } + + if (hdl >= IPA_PM_MAX_CLIENTS || consumer < 0 || + consumer >= IPA_CLIENT_MAX) { + IPA_PM_ERR("invalid params\n"); + return -EINVAL; + } + + mutex_lock(&ipa_pm_ctx->client_mutex); + if (ipa_pm_ctx->clients[hdl] == NULL) { + mutex_unlock(&ipa_pm_ctx->client_mutex); + IPA_PM_ERR("Client is NULL\n"); + return -EPERM; + } + + idx = ipa_get_ep_mapping(consumer); + + if (idx < 0) { + mutex_unlock(&ipa_pm_ctx->client_mutex); + IPA_PM_DBG("Pipe is not used\n"); + return 0; + } + + IPA_PM_DBG("Mapping pipe %d to client %d\n", idx, hdl); + + if (ipa_pm_ctx->clients_by_pipe[idx] != NULL) { + mutex_unlock(&ipa_pm_ctx->client_mutex); + IPA_PM_ERR("Pipe is already mapped\n"); + return -EPERM; + } + ipa_pm_ctx->clients_by_pipe[idx] = ipa_pm_ctx->clients[hdl]; + mutex_unlock(&ipa_pm_ctx->client_mutex); + + IPA_PM_DBG("Pipe %d is mapped to client %d\n", idx, hdl); + + return 0; +} +EXPORT_SYMBOL(ipa_pm_associate_ipa_cons_to_client); + +static int ipa_pm_activate_helper(struct ipa_pm_client *client, bool sync) +{ + struct ipa_active_client_logging_info log_info; + int result = 0; + unsigned long flags; + + spin_lock_irqsave(&client->state_lock, flags); + IPA_PM_DBG_STATE(client->hdl, client->name, client->state); + + if (IPA_PM_STATE_IN_PROGRESS(client->state)) { + if (sync) { + spin_unlock_irqrestore(&client->state_lock, flags); + wait_for_completion(&client->complete); + spin_lock_irqsave(&client->state_lock, flags); + } else { + client->state = IPA_PM_ACTIVATE_IN_PROGRESS; + spin_unlock_irqrestore(&client->state_lock, flags); + return -EINPROGRESS; + } + } + + switch (client->state) { + case IPA_PM_ACTIVATED_PENDING_RESCHEDULE: + fallthrough; + case IPA_PM_ACTIVATED_PENDING_DEACTIVATION: + client->state = IPA_PM_ACTIVATED_TIMER_SET; + fallthrough; + case IPA_PM_ACTIVATED: + fallthrough; + case IPA_PM_ACTIVATED_TIMER_SET: + spin_unlock_irqrestore(&client->state_lock, flags); + return 0; + case IPA_PM_DEACTIVATED: + break; + default: + IPA_PM_ERR("Invalid State\n"); + spin_unlock_irqrestore(&client->state_lock, flags); + return -EPERM; + } + IPA_PM_DBG_STATE(client->hdl, client->name, client->state); + + IPA_ACTIVE_CLIENTS_PREP_SPECIAL(log_info, client->name); + if (!client->skip_clk_vote) { + if (sync) { + client->state = IPA_PM_ACTIVATE_IN_PROGRESS; + spin_unlock_irqrestore(&client->state_lock, flags); + IPA_ACTIVE_CLIENTS_INC_SPECIAL(client->name); + spin_lock_irqsave(&client->state_lock, flags); + } else + result = ipa3_inc_client_enable_clks_no_block + (&log_info); + } + + /* we got the clocks */ + if (result == 0) { + client->state = IPA_PM_ACTIVATED; + if (client->group == IPA_PM_GROUP_APPS) + __pm_stay_awake(client->wlock); + spin_unlock_irqrestore(&client->state_lock, flags); + activate_client(client->hdl); + if (sync) + do_clk_scaling(); + else + queue_work(ipa_pm_ctx->wq, + &ipa_pm_ctx->clk_scaling.work); + IPA_PM_DBG_STATE(client->hdl, client->name, client->state); + return 0; + } + + client->state = IPA_PM_ACTIVATE_IN_PROGRESS; + reinit_completion(&client->complete); + queue_work(ipa_pm_ctx->wq, &client->activate_work); + spin_unlock_irqrestore(&client->state_lock, flags); + IPA_PM_DBG_STATE(client->hdl, client->name, client->state); + return -EINPROGRESS; +} + +/** + * ipa_pm_activate(): activate ipa client to vote for clock(). Can be called + * from atomic context and returns -EINPROGRESS if cannot be done synchronously + * @hdl: index of the client in the array + * + * Returns: 0 on success, -EINPROGRESS if operation cannot be done synchronously + * and other negatives on failure + */ +int ipa_pm_activate(u32 hdl) +{ + if (ipa_pm_ctx == NULL) { + IPA_PM_ERR("PM_ctx is null\n"); + return -EINVAL; + } + + if (hdl >= IPA_PM_MAX_CLIENTS || ipa_pm_ctx->clients[hdl] == NULL) { + IPA_PM_ERR("Invalid Param\n"); + return -EINVAL; + } + + return ipa_pm_activate_helper(ipa_pm_ctx->clients[hdl], false); +} +EXPORT_SYMBOL(ipa_pm_activate); + +/** + * ipa_pm_activate(): activate ipa client to vote for clock synchronously. + * Cannot be called from an atomic contex. + * @hdl: index of the client in the array + * + * Returns: 0 on success, negative on failure + */ +int ipa_pm_activate_sync(u32 hdl) +{ + if (ipa_pm_ctx == NULL) { + IPA_PM_ERR("PM_ctx is null\n"); + return -EINVAL; + } + + if (hdl >= IPA_PM_MAX_CLIENTS || ipa_pm_ctx->clients[hdl] == NULL) { + IPA_PM_ERR("Invalid Param\n"); + return -EINVAL; + } + + return ipa_pm_activate_helper(ipa_pm_ctx->clients[hdl], true); +} +EXPORT_SYMBOL(ipa_pm_activate_sync); + +/** + * ipa_pm_deferred_deactivate(): schedule a timer to deactivate client and + * devote clock. Can be called from atomic context (asynchronously) + * @hdl: index of the client in the array + * + * Returns: 0 on success, negative on failure + */ +int ipa_pm_deferred_deactivate(u32 hdl) +{ + struct ipa_pm_client *client; + unsigned long flags; + unsigned long delay; + + if (ipa_pm_ctx == NULL) { + IPA_PM_ERR("PM_ctx is null\n"); + return -EINVAL; + } + + if (hdl >= IPA_PM_MAX_CLIENTS || ipa_pm_ctx->clients[hdl] == NULL) { + IPA_PM_ERR("Invalid Param\n"); + return -EINVAL; + } + + client = ipa_pm_ctx->clients[hdl]; + IPA_PM_DBG_STATE(hdl, client->name, client->state); + + spin_lock_irqsave(&client->state_lock, flags); + switch (client->state) { + case IPA_PM_ACTIVATE_IN_PROGRESS: + client->state = IPA_PM_DEACTIVATE_IN_PROGRESS; + fallthrough; + case IPA_PM_DEACTIVATED: + IPA_PM_DBG_STATE(hdl, client->name, client->state); + spin_unlock_irqrestore(&client->state_lock, flags); + return 0; + case IPA_PM_ACTIVATED: + delay = IPA_PM_DEFERRED_TIMEOUT; + if (ipa3_ctx->ipa3_hw_mode == IPA_HW_MODE_VIRTUAL || + ipa3_ctx->ipa3_hw_mode == IPA_HW_MODE_EMULATION) + delay *= 5; + + client->state = IPA_PM_ACTIVATED_PENDING_DEACTIVATION; + queue_delayed_work(ipa_pm_ctx->wq, &client->deactivate_work, + msecs_to_jiffies(delay)); + break; + case IPA_PM_ACTIVATED_TIMER_SET: + fallthrough; + case IPA_PM_ACTIVATED_PENDING_DEACTIVATION: + client->state = IPA_PM_ACTIVATED_PENDING_RESCHEDULE; + fallthrough; + case IPA_PM_DEACTIVATE_IN_PROGRESS: + fallthrough; + case IPA_PM_ACTIVATED_PENDING_RESCHEDULE: + break; + case IPA_PM_STATE_MAX: + fallthrough; + default: + IPA_PM_ERR("Bad State"); + spin_unlock_irqrestore(&client->state_lock, flags); + return -EINVAL; + } + IPA_PM_DBG_STATE(hdl, client->name, client->state); + spin_unlock_irqrestore(&client->state_lock, flags); + + return 0; +} +EXPORT_SYMBOL(ipa_pm_deferred_deactivate); + +/** + * ipa_pm_deactivate_all_deferred(): Cancel the deferred deactivation timer and + * immediately devotes for IPA clocks + * + * Returns: 0 on success, negative on failure + */ +int ipa_pm_deactivate_all_deferred(void) +{ + int i; + bool run_algorithm = false; + struct ipa_pm_client *client; + unsigned long flags; + + if (ipa_pm_ctx == NULL) { + IPA_PM_ERR("PM_ctx is null\n"); + return -EINVAL; + } + + for (i = 1; i < IPA_PM_MAX_CLIENTS; i++) { + client = ipa_pm_ctx->clients[i]; + + if (client == NULL) + continue; + + cancel_delayed_work_sync(&client->deactivate_work); + + if (IPA_PM_STATE_IN_PROGRESS(client->state)) { + wait_for_completion(&client->complete); + continue; + } + + spin_lock_irqsave(&client->state_lock, flags); + IPA_PM_DBG_STATE(client->hdl, client->name, client->state); + + if (client->state == IPA_PM_ACTIVATED_TIMER_SET) { + client->state = IPA_PM_ACTIVATED; + IPA_PM_DBG_STATE(client->hdl, client->name, + client->state); + spin_unlock_irqrestore(&client->state_lock, flags); + } else if (client->state == + IPA_PM_ACTIVATED_PENDING_DEACTIVATION || + client->state == + IPA_PM_ACTIVATED_PENDING_RESCHEDULE) { + run_algorithm = true; + client->state = IPA_PM_DEACTIVATED; + IPA_PM_DBG_STATE(client->hdl, client->name, + client->state); + spin_unlock_irqrestore(&client->state_lock, flags); + if (!client->skip_clk_vote) { + IPA_ACTIVE_CLIENTS_DEC_SPECIAL(client->name); + if (client->group == IPA_PM_GROUP_APPS) + __pm_relax(client->wlock); + } + deactivate_client(client->hdl); + } else /* if activated or deactivated, we do nothing */ + spin_unlock_irqrestore(&client->state_lock, flags); + } + + if (run_algorithm) + do_clk_scaling(); + + return 0; +} + +/** + * ipa_pm_deactivate_sync(): deactivate ipa client and devote clock. Cannot be + * called from atomic context. + * @hdl: index of the client in the array + * + * Returns: 0 on success, negative on failure + */ +int ipa_pm_deactivate_sync(u32 hdl) +{ + struct ipa_pm_client *client; + unsigned long flags; + + if (ipa_pm_ctx == NULL) { + IPA_PM_ERR("PM_ctx is null\n"); + return -EINVAL; + } + + if (hdl >= IPA_PM_MAX_CLIENTS || ipa_pm_ctx->clients[hdl] == NULL) { + IPA_PM_ERR("Invalid Param\n"); + return -EINVAL; + } + client = ipa_pm_ctx->clients[hdl]; + + cancel_delayed_work_sync(&client->deactivate_work); + + if (IPA_PM_STATE_IN_PROGRESS(client->state)) + wait_for_completion(&client->complete); + + spin_lock_irqsave(&client->state_lock, flags); + IPA_PM_DBG_STATE(hdl, client->name, client->state); + + if (client->state == IPA_PM_DEACTIVATED) { + spin_unlock_irqrestore(&client->state_lock, flags); + return 0; + } + + spin_unlock_irqrestore(&client->state_lock, flags); + + /* else case (Deactivates all Activated cases)*/ + if (!client->skip_clk_vote) { + IPA_ACTIVE_CLIENTS_DEC_SPECIAL(client->name); + if (client->group == IPA_PM_GROUP_APPS) + __pm_relax(client->wlock); + } + + spin_lock_irqsave(&client->state_lock, flags); + client->state = IPA_PM_DEACTIVATED; + IPA_PM_DBG_STATE(hdl, client->name, client->state); + spin_unlock_irqrestore(&client->state_lock, flags); + /*Check any delayed work queue scheduled*/ + cancel_delayed_work_sync(&client->deactivate_work); + deactivate_client(hdl); + do_clk_scaling(); + + return 0; +} +EXPORT_SYMBOL(ipa_pm_deactivate_sync); + +/** + * ipa_pm_handle_suspend(): calls the callbacks of suspended clients to wake up + * @pipe_bitmask: the bits represent the indexes of the clients to be woken up + * @pipe_arr_idx: if larger than 0 add to pipe num 32 * pipe_arr_idx + * + * Returns: 0 on success, negative on failure + */ +int ipa_pm_handle_suspend(u32 pipe_bitmask, u32 pipe_arr_idx) +{ + int i; + struct ipa_pm_client *client; + bool client_notified[IPA_PM_MAX_CLIENTS] = { false }; + u32 pipe_add; + u32 max_pipes; + + if (ipa_pm_ctx == NULL) { + IPA_PM_ERR("PM_ctx is null\n"); + return -EINVAL; + } + + IPA_PM_DBG_LOW("bitmask: %d", pipe_bitmask); + + if (pipe_bitmask == 0) + return 0; + + pipe_add = pipe_arr_idx * 32; + max_pipes = ipa3_get_max_num_pipes(); + mutex_lock(&ipa_pm_ctx->client_mutex); + for (i = 0; i < IPA_EP_PER_REG && (i + pipe_add) < max_pipes; i++) { + if (pipe_bitmask & (1 << i)) { + client = ipa_pm_ctx->clients_by_pipe[i + pipe_add]; + if (client && !client_notified[client->hdl]) { + if (client->callback) { + client->callback(client->callback_params + , IPA_PM_REQUEST_WAKEUP); + client_notified[client->hdl] = true; + } + } + } + } + mutex_unlock(&ipa_pm_ctx->client_mutex); + return 0; +} + +/** + * ipa_pm_set_throughput(): Adds/changes the throughput requirement to IPA PM + * to be used for clock scaling + * @hdl: index of the client in the array + * @throughput: the new throughput value to be set for that client + * + * Returns: 0 on success, negative on failure + */ +int ipa_pm_set_throughput(u32 hdl, int throughput) +{ + struct ipa_pm_client *client; + unsigned long flags; + + if (ipa_pm_ctx == NULL) { + IPA_PM_ERR("PM_ctx is null\n"); + return -EINVAL; + } + + mutex_lock(&ipa_pm_ctx->client_mutex); + if (hdl >= IPA_PM_MAX_CLIENTS || ipa_pm_ctx->clients[hdl] == NULL + || throughput < 0) { + IPA_PM_ERR("Invalid Params\n"); + mutex_unlock(&ipa_pm_ctx->client_mutex); + return -EINVAL; + } + client = ipa_pm_ctx->clients[hdl]; + + if (client->group == IPA_PM_GROUP_DEFAULT) + IPA_PM_DBG_LOW("Old throughput: %d\n", client->throughput); + else + IPA_PM_DBG_LOW("old Group %d throughput: %d\n", + client->group, ipa_pm_ctx->group_tput[client->group]); + + if (client->group == IPA_PM_GROUP_DEFAULT) + client->throughput = throughput; + else + ipa_pm_ctx->group_tput[client->group] = throughput; + + if (client->group == IPA_PM_GROUP_DEFAULT) + IPA_PM_DBG_LOW("New throughput: %d\n", client->throughput); + else + IPA_PM_DBG_LOW("New Group %d throughput: %d\n", + client->group, ipa_pm_ctx->group_tput[client->group]); + mutex_unlock(&ipa_pm_ctx->client_mutex); + + if (ipa_pm_ctx->clients[hdl]) { + spin_lock_irqsave(&client->state_lock, flags); + if (IPA_PM_STATE_ACTIVE(client->state) || (client->group != + IPA_PM_GROUP_DEFAULT)) { + spin_unlock_irqrestore(&client->state_lock, flags); + do_clk_scaling(); + return 0; + } + spin_unlock_irqrestore(&client->state_lock, flags); + } + + return 0; +} +EXPORT_SYMBOL(ipa_pm_set_throughput); + +void ipa_pm_set_clock_index(int index) +{ + if (ipa_pm_ctx && index >= 0) + ipa_pm_ctx->clk_scaling.cur_vote = index; + + IPA_PM_DBG("Setting pm clock vote to %d\n", index); +} + +/** + * ipa_pm_stat() - print PM stat + * @buf: [in] The user buff used to print + * @size: [in] The size of buf + * Returns: number of bytes used on success, negative on failure + * + * This function is called by ipa_debugfs in order to receive + * a picture of the clients in the PM and the throughput, threshold and cur vote + */ +int ipa_pm_stat(char *buf, int size) +{ + struct ipa_pm_client *client; + struct clk_scaling_db *clk = &ipa_pm_ctx->clk_scaling; + int i, j, tput, cnt = 0, result = 0; + unsigned long flags; + + if (!buf || size < 0) + return -EINVAL; + + mutex_lock(&ipa_pm_ctx->client_mutex); + + result = scnprintf(buf + cnt, size - cnt, "\n\nCurrent threshold: ["); + cnt += result; + + for (i = 0; i < clk->threshold_size; i++) { + result = scnprintf(buf + cnt, size - cnt, + "%d, ", clk->current_threshold[i]); + cnt += result; + } + + result = scnprintf(buf + cnt, size - cnt, "\b\b]\n"); + cnt += result; + + result = scnprintf(buf + cnt, size - cnt, + "Aggregated tput: %d, Cur vote: %d", + ipa_pm_ctx->aggregated_tput, clk->cur_vote); + cnt += result; + + result = scnprintf(buf + cnt, size - cnt, "\n\nRegistered Clients:\n"); + cnt += result; + + + for (i = 1; i < IPA_PM_MAX_CLIENTS; i++) { + client = ipa_pm_ctx->clients[i]; + + if (client == NULL) + continue; + + spin_lock_irqsave(&client->state_lock, flags); + if (client->group == IPA_PM_GROUP_DEFAULT) + tput = client->throughput; + else + tput = ipa_pm_ctx->group_tput[client->group]; + + result = scnprintf(buf + cnt, size - cnt, + "Client[%d]: %s State:%s\nGroup: %s Throughput: %d Pipes: ", + i, client->name, client_state_to_str[client->state], + ipa_pm_group_to_str[client->group], tput); + cnt += result; + + for (j = 0; j < ipa3_get_max_num_pipes(); j++) { + if (ipa_pm_ctx->clients_by_pipe[j] == client) { + result = scnprintf(buf + cnt, size - cnt, + "%d, ", j); + cnt += result; + } + } + + result = scnprintf(buf + cnt, size - cnt, "\b\b\n\n"); + cnt += result; + spin_unlock_irqrestore(&client->state_lock, flags); + } + mutex_unlock(&ipa_pm_ctx->client_mutex); + + return cnt; +} + +/** + * ipa_pm_exceptions_stat() - print PM exceptions stat + * @buf: [in] The user buff used to print + * @size: [in] The size of buf + * Returns: number of bytes used on success, negative on failure + * + * This function is called by ipa_debugfs in order to receive + * a full picture of the exceptions in the PM + */ +int ipa_pm_exceptions_stat(char *buf, int size) +{ + int i, j, cnt = 0, result = 0; + struct ipa_pm_exception_list *exception; + + if (!buf || size < 0) + return -EINVAL; + + result = scnprintf(buf + cnt, size - cnt, "\n"); + cnt += result; + + mutex_lock(&ipa_pm_ctx->client_mutex); + for (i = 0; i < ipa_pm_ctx->clk_scaling.exception_size; i++) { + exception = &ipa_pm_ctx->clk_scaling.exception_list[i]; + if (exception == NULL) { + result = scnprintf(buf + cnt, size - cnt, + "Exception %d is NULL\n\n", i); + cnt += result; + continue; + } + + result = scnprintf(buf + cnt, size - cnt, + "Exception %d: %s\nPending: %d Bitmask: %X %X Threshold: [" + , i, exception->clients, exception->pending, + exception->bitmask[0], exception->bitmask[1]); + cnt += result; + for (j = 0; j < ipa_pm_ctx->clk_scaling.threshold_size; j++) { + result = scnprintf(buf + cnt, size - cnt, + "%d, ", exception->threshold[j]); + cnt += result; + } + result = scnprintf(buf + cnt, size - cnt, "\b\b]\n\n"); + cnt += result; + } + mutex_unlock(&ipa_pm_ctx->client_mutex); + + return cnt; +} + +int ipa_pm_get_scaling_bw_levels(struct ipa_lnx_clock_stats *clock_stats) +{ + struct clk_scaling_db *clk; + + if (ipa_pm_ctx) { + clk = &ipa_pm_ctx->clk_scaling; + if (clk->threshold_size >= 3) { + clock_stats->scale_thresh_svs = clk->current_threshold[0]; + clock_stats->scale_thresh_nom = clk->current_threshold[1]; + clock_stats->scale_thresh_tur = clk->current_threshold[2]; + return 0; + } else return -EINVAL; + } else return -EINVAL; +} + +int ipa_pm_get_aggregated_throughput(void) +{ + if (ipa_pm_ctx) + return ipa_pm_ctx->aggregated_tput; + else return 0; +} + +int ipa_pm_get_current_clk_vote(void) +{ + if (ipa_pm_ctx) + return ipa_pm_ctx->clk_scaling.cur_vote; + else + return ipa3_ctx->app_clock_vote.cnt; +} + + +static int ipa_get_pm_hdl_from_name(char *client_name) +{ + int i; + struct pm_client_name_lookup *lookup; + + for (i = 0; i < NUM_PM_CLIENT_NAMES; i++) { + lookup = &client_lookup_table[i]; + if (!strcmp(lookup->name, client_name)) + return lookup->idx_hdl; + } + return NUM_PM_CLIENT_NAMES + 2; +} + +bool ipa_get_pm_client_stats_filled(struct pm_client_stats *pm_stats_ptr, + int pm_client_index) +{ + struct ipa_pm_client *client; + unsigned long flags; + int i; + + client = ipa_pm_ctx->clients[pm_client_index]; + mutex_lock(&ipa_pm_ctx->client_mutex); + if (client == NULL) { + mutex_unlock(&ipa_pm_ctx->client_mutex); + return false; + } + spin_lock_irqsave(&client->state_lock, flags); + pm_stats_ptr->pm_client_group = client->group; + pm_stats_ptr->pm_client_state = client->state; + pm_stats_ptr->pm_client_hdl = ipa_get_pm_hdl_from_name(client->name); + if (client->group == IPA_PM_GROUP_DEFAULT) + pm_stats_ptr->pm_client_bw = client->throughput; + else { + pm_stats_ptr->pm_client_bw = ipa_pm_ctx->group_tput[client->group]; + } + + pm_stats_ptr->pm_client_type = IPA_CLIENT_MAX; + for (i = 0; i < ipa3_get_max_num_pipes(); i++) { + if (ipa_pm_ctx->clients_by_pipe[i] == client) { + pm_stats_ptr->pm_client_type = ipa3_get_client_by_pipe(i); + break; + } + } + + spin_unlock_irqrestore(&client->state_lock, flags); + mutex_unlock(&ipa_pm_ctx->client_mutex); + return true; +} + +int ipa_pm_get_pm_clnt_throughput(enum ipa_client_type client_type) +{ + int idx = ipa_get_ep_mapping(client_type); + int throughput; + + mutex_lock(&ipa_pm_ctx->client_mutex); + if (ipa_pm_ctx && (idx >= 0) && ipa_pm_ctx->clients_by_pipe[idx]) { + throughput = ipa_pm_ctx->clients_by_pipe[idx]->throughput; + mutex_unlock(&ipa_pm_ctx->client_mutex); + return throughput; + } else { + mutex_unlock(&ipa_pm_ctx->client_mutex); + return 0; + } +} + +/** + * ipa_pm_add_dummy_clients() - add 2 dummy clients for modem and apps + * @power_plan: [in] The power plan for the dummy clients + * 0 = SVS (lowest plan), 1 = SVS2, ... etc + * + * Returns: 0 on success, negative on failure + */ +int ipa_pm_add_dummy_clients(s8 power_plan) +{ + int rc = 0; + int tput; + int hdl_1, hdl_2; + + struct ipa_pm_register_params dummy1_params = { + .name = "DummyModem", + .group = IPA_PM_GROUP_MODEM, + .skip_clk_vote = 0, + .callback = NULL, + .user_data = NULL + }; + + struct ipa_pm_register_params dummy2_params = { + .name = "DummyApps", + .group = IPA_PM_GROUP_APPS, + .skip_clk_vote = 0, + .callback = NULL, + .user_data = NULL + }; + + if (power_plan < 0 || + (power_plan - 1) >= ipa_pm_ctx->clk_scaling.threshold_size) { + pr_err("Invalid power plan(%d)\n", power_plan); + return -EFAULT; + } + + /* 0 is SVS case which is not part of the threshold */ + if (power_plan == 0) + tput = 0; + else + tput = ipa_pm_ctx->clk_scaling.current_threshold[power_plan-1]; + + /* + * register with local handles to prevent overwriting global handles + * in the case of a failure + */ + rc = ipa_pm_register(&dummy1_params, &hdl_1); + if (rc) { + pr_err("fail to register client 1 rc = %d\n", rc); + return -EFAULT; + } + + rc = ipa_pm_register(&dummy2_params, &hdl_2); + if (rc) { + pr_err("fail to register client 2 rc = %d\n", rc); + return -EFAULT; + } + + /* replace global handles */ + dummy_hdl_1 = hdl_1; + dummy_hdl_2 = hdl_2; + + /* save the old throughputs for removal */ + tput_modem = ipa_pm_ctx->group_tput[IPA_PM_GROUP_MODEM]; + tput_apps = ipa_pm_ctx->group_tput[IPA_PM_GROUP_APPS]; + + rc = ipa_pm_set_throughput(dummy_hdl_1, tput); + if (rc) { + IPAERR("fail to set tput for client 1 rc = %d\n", rc); + return -EFAULT; + } + + rc = ipa_pm_set_throughput(dummy_hdl_2, tput); + if (rc) { + IPAERR("fail to set tput for client 2 rc = %d\n", rc); + return -EFAULT; + } + + rc = ipa_pm_activate_sync(dummy_hdl_1); + if (rc) { + IPAERR("fail to activate sync for client 1 rc = %d\n", rc); + return -EFAULT; + } + + rc = ipa_pm_activate_sync(dummy_hdl_2); + if (rc) { + IPAERR("fail to activate sync for client 2 rc = %d\n", rc); + return -EFAULT; + } + + return rc; +} + +/** + * ipa_pm_remove_dummy_clients() - remove the 2 dummy clients for modem and apps + * + * Returns: 0 on success, negative on failure + */ +int ipa_pm_remove_dummy_clients(void) +{ + int rc = 0; + + rc = ipa_pm_deactivate_sync(dummy_hdl_1); + if (rc) { + IPAERR("fail to deactivate client 1 rc = %d\n", rc); + return -EFAULT; + } + + rc = ipa_pm_deactivate_sync(dummy_hdl_2); + if (rc) { + IPAERR("fail to deactivate client 2 rc = %d\n", rc); + return -EFAULT; + } + + /* reset the modem and apps tputs back to old values */ + rc = ipa_pm_set_throughput(dummy_hdl_1, tput_modem); + if (rc) { + IPAERR("fail to reset tput for client 1 rc = %d\n", rc); + return -EFAULT; + } + + rc = ipa_pm_set_throughput(dummy_hdl_2, tput_apps); + if (rc) { + IPAERR("fail to reset tput for client 2 rc = %d\n", rc); + return -EFAULT; + } + + rc = ipa_pm_deregister(dummy_hdl_1); + if (rc) { + IPAERR("fail to deregister client 1 rc = %d\n", rc); + return -EFAULT; + } + + rc = ipa_pm_deregister(dummy_hdl_2); + if (rc) { + IPAERR("fail to deregister client 2 rc = %d\n", rc); + return -EFAULT; + } + + return rc; +} diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_pm.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_pm.h new file mode 100644 index 0000000000..1b20b1fde0 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_pm.h @@ -0,0 +1,196 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _IPA_PM_H_ +#define _IPA_PM_H_ + +#include + +/* internal to ipa */ + +/* actual max is value -1 since we start from 1*/ +#define IPA_PM_MAX_CLIENTS IPA5_PIPES_NUM +#define IPA_PM_MAX_EX_CL 64 +#define IPA_PM_THRESHOLD_MAX 5 +#define IPA_PM_EXCEPTION_MAX 5 +#define IPA_PM_DEFERRED_TIMEOUT 100 + +/* + * ipa_pm group names + * + * Default stands for individual clients while other groups share one throughput + * Some groups also have special flags like modem which do not vote for clock + * but is accounted for in clock scaling while activated + */ +enum ipa_pm_group { + IPA_PM_GROUP_DEFAULT, + IPA_PM_GROUP_APPS, + IPA_PM_GROUP_MODEM, + IPA_PM_GROUP_MAX, +}; + +/* + * ipa_pm_cb_event + * + * specifies what kind of callback is being called. + * IPA_PM_CLIENT_ACTIVATED: the client has completed asynchronous activation + * IPA_PM_REQUEST_WAKEUP: wake up the client after it has been suspended + */ +enum ipa_pm_cb_event { + IPA_PM_CLIENT_ACTIVATED, + IPA_PM_REQUEST_WAKEUP, + IPA_PM_CB_EVENT_MAX, +}; + +/* + * struct ipa_pm_exception - clients included in exception and its threshold + * @usecase: comma separated client names + * @threshold: the threshold values for the exception + */ +struct ipa_pm_exception { + const char *usecase; + int threshold[IPA_PM_THRESHOLD_MAX]; +}; + +/* + * struct ipa_pm_init_params - parameters needed for initializng the pm + * @default_threshold: the thresholds used if no exception passes + * @threshold_size: size of the threshold + * @exceptions: list of exceptions for the pm + * @exception_size: size of the exception_list + */ +struct ipa_pm_init_params { + int default_threshold[IPA_PM_THRESHOLD_MAX]; + int threshold_size; + struct ipa_pm_exception exceptions[IPA_PM_EXCEPTION_MAX]; + int exception_size; +}; + +/* + * struct ipa_pm_register_params - parameters needed to register a client + * @name: name of the client + * @callback: pointer to the client's callback function + * @user_data: pointer to the client's callback parameters + * @group: group number of the client + * @skip_clk_vote: 0 if client votes for clock when activated, 1 if no vote + */ +struct ipa_pm_register_params { + const char *name; + void (*callback)(void *user_data, enum ipa_pm_cb_event); + void *user_data; + enum ipa_pm_group group; + bool skip_clk_vote; +}; + +#if IS_ENABLED(CONFIG_IPA3) + +int ipa_pm_register(struct ipa_pm_register_params *params, u32 *hdl); +int ipa_pm_associate_ipa_cons_to_client(u32 hdl, enum ipa_client_type consumer); +int ipa_pm_activate(u32 hdl); +int ipa_pm_activate_sync(u32 hdl); +int ipa_pm_deferred_deactivate(u32 hdl); +int ipa_pm_deactivate_sync(u32 hdl); +int ipa_pm_set_throughput(u32 hdl, int throughput); +int ipa_pm_deregister(u32 hdl); + +/* IPA Internal Functions */ +int ipa_pm_init(struct ipa_pm_init_params *params); +int ipa_pm_destroy(void); +int ipa_pm_handle_suspend(u32 pipe_bitmask, u32 pipe_arr_idx); +int ipa_pm_deactivate_all_deferred(void); +int ipa_pm_stat(char *buf, int size); +int ipa_pm_exceptions_stat(char *buf, int size); +void ipa_pm_set_clock_index(int index); +int ipa_pm_add_dummy_clients(s8 power_plan); +int ipa_pm_remove_dummy_clients(void); + +#else /* IS_ENABLED(CONFIG_IPA3) */ + +static inline int ipa_pm_register( + struct ipa_pm_register_params *params, u32 *hdl) +{ + return -EPERM; +} + +static inline int ipa_pm_associate_ipa_cons_to_client( + u32 hdl, enum ipa_client_type consumer) +{ + return -EPERM; +} + +static inline int ipa_pm_activate(u32 hdl) +{ + return -EPERM; +} + +static inline int ipa_pm_activate_sync(u32 hdl) +{ + return -EPERM; +} + +static inline int ipa_pm_deferred_deactivate(u32 hdl) +{ + return -EPERM; +} + +static inline int ipa_pm_deactivate_sync(u32 hdl) +{ + return -EPERM; +} + +static inline int ipa_pm_set_throughput(u32 hdl, int throughput) +{ + return -EPERM; +} + +static inline int ipa_pm_deregister(u32 hdl) +{ + return -EPERM; +} + +/* IPA Internal Functions */ +static inline int ipa_pm_init(struct ipa_pm_init_params *params) +{ + return -EPERM; +} + +static inline int ipa_pm_destroy(void) +{ + return -EPERM; +} + +static inline int ipa_pm_handle_suspend(u32 pipe_bitmask, u32 pipe_arr_idx) +{ + return -EPERM; +} + +static inline int ipa_pm_deactivate_all_deferred(void) +{ + return -EPERM; +} + +static inline int ipa_pm_stat(char *buf, int size) +{ + return -EPERM; +} + +static inline int ipa_pm_exceptions_stat(char *buf, int size) +{ + return -EPERM; +} + +static inline int ipa_pm_add_dummy_clients(s8 power_plan) +{ + return -EPERM; +} + +static inline int ipa_pm_remove_dummy_clients(void) +{ + return -EPERM; +} +#endif /* IS_ENABLED(CONFIG_IPA3) */ + +#endif /* _IPA_PM_H_ */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_qdss.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_qdss.c new file mode 100644 index 0000000000..873f375ef9 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_qdss.c @@ -0,0 +1,262 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include "ipa_i.h" + +#define IPA_HOLB_TMR_VALUE 0 +#define OFFLOAD_DRV_NAME "ipa_qdss" +#define IPA_QDSS_DBG(fmt, args...) \ + do { \ + pr_debug(OFFLOAD_DRV_NAME " %s:%d " fmt, \ + __func__, __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf(), \ + OFFLOAD_DRV_NAME " %s:%d " fmt, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf_low(), \ + OFFLOAD_DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) + +#define IPA_QDSS_ERR(fmt, args...) \ + do { \ + pr_err(OFFLOAD_DRV_NAME " %s:%d " fmt, \ + __func__, __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf(), \ + OFFLOAD_DRV_NAME " %s:%d " fmt, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf_low(), \ + OFFLOAD_DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) + +static void ipa3_qdss_gsi_chan_err_cb(struct gsi_chan_err_notify *notify) +{ + switch (notify->evt_id) { + case GSI_CHAN_INVALID_TRE_ERR: + IPAERR("Got GSI_CHAN_INVALID_TRE_ERR\n"); + break; + case GSI_CHAN_NON_ALLOCATED_EVT_ACCESS_ERR: + IPAERR("Got GSI_CHAN_NON_ALLOCATED_EVT_ACCESS_ERR\n"); + break; + case GSI_CHAN_OUT_OF_BUFFERS_ERR: + IPAERR("Got GSI_CHAN_OUT_OF_BUFFERS_ERR\n"); + break; + case GSI_CHAN_OUT_OF_RESOURCES_ERR: + IPAERR("Got GSI_CHAN_OUT_OF_RESOURCES_ERR\n"); + break; + case GSI_CHAN_UNSUPPORTED_INTER_EE_OP_ERR: + IPAERR("Got GSI_CHAN_UNSUPPORTED_INTER_EE_OP_ERR\n"); + break; + case GSI_CHAN_HWO_1_ERR: + IPAERR("Got GSI_CHAN_HWO_1_ERR\n"); + break; + default: + IPAERR("Unexpected err evt: %d\n", notify->evt_id); + } + ipa_assert(); +} + +int ipa_qdss_conn_pipes(struct ipa_qdss_conn_in_params *in, + struct ipa_qdss_conn_out_params *out) +{ + struct gsi_chan_props gsi_channel_props; + struct ipa3_ep_context *ep_rx; + const struct ipa_gsi_ep_config *gsi_ep_info; + union __packed gsi_channel_scratch ch_scratch; + u32 gsi_db_addr_low, gsi_db_addr_high; + struct ipa_ep_cfg ep_cfg = { { 0 } }; + int ipa_ep_idx_rx, ipa_ep_idx_tx; + int result = 0; + struct ipa_ep_cfg_holb holb_cfg; + + if (!(in && out)) { + IPA_QDSS_ERR("Empty parameters. in=%pK out=%pK\n", in, out); + return -IPA_QDSS_PIPE_CONN_FAILURE; + } + + ipa_ep_idx_tx = ipa_get_ep_mapping(IPA_CLIENT_MHI_QDSS_CONS); + if ((ipa_ep_idx_tx) < 0 || (!ipa3_ctx->ipa_config_is_mhi)) { + IPA_QDSS_ERR("getting EP map failed\n"); + return -IPA_QDSS_PIPE_CONN_FAILURE; + } + + ipa_ep_idx_rx = ipa_get_ep_mapping(IPA_CLIENT_QDSS_PROD); + if ((ipa_ep_idx_rx == -1) || + (ipa_ep_idx_rx >= IPA3_MAX_NUM_PIPES)) { + IPA_QDSS_ERR("out of range ipa_ep_idx_rx = %d\n", + ipa_ep_idx_rx); + return -IPA_QDSS_PIPE_CONN_FAILURE; + } + + ep_rx = &ipa3_ctx->ep[ipa_ep_idx_rx]; + + if (ep_rx->valid) { + IPA_QDSS_ERR("EP already allocated.\n"); + return IPA_QDSS_SUCCESS; + } + + memset(ep_rx, 0, offsetof(struct ipa3_ep_context, sys)); + + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + + ep_rx->valid = 1; + ep_rx->client = IPA_CLIENT_QDSS_PROD; + if (ipa3_cfg_ep(ipa_ep_idx_rx, &ep_rx->cfg)) { + IPAERR("fail to setup rx pipe cfg\n"); + goto fail; + } + + /* setup channel ring */ + memset(&gsi_channel_props, 0, sizeof(gsi_channel_props)); + gsi_channel_props.prot = GSI_CHAN_PROT_QDSS; + gsi_channel_props.dir = GSI_CHAN_DIR_TO_GSI; + + gsi_ep_info = ipa_get_gsi_ep_info(ep_rx->client); + if (!gsi_ep_info) { + IPA_QDSS_ERR("Failed getting GSI EP info for client=%d\n", + ep_rx->client); + goto fail; + } + + gsi_channel_props.ch_id = gsi_ep_info->ipa_gsi_chan_num; + gsi_channel_props.re_size = GSI_CHAN_RE_SIZE_8B; + gsi_channel_props.use_db_eng = GSI_CHAN_DB_MODE; + gsi_channel_props.err_cb = ipa3_qdss_gsi_chan_err_cb; + gsi_channel_props.ring_len = in->desc_fifo_size; + gsi_channel_props.ring_base_addr = + in->desc_fifo_base_addr; + gsi_channel_props.db_in_bytes = 1; + gsi_channel_props.low_latency_en = 0; + result = gsi_alloc_channel(&gsi_channel_props, ipa3_ctx->gsi_dev_hdl, + &ep_rx->gsi_chan_hdl); + if (result != GSI_STATUS_SUCCESS) { + IPA_QDSS_ERR("Failed allocating gsi_chan_hdl=%d\n", + &ep_rx->gsi_chan_hdl); + goto fail; + } + + ep_rx->gsi_mem_info.chan_ring_len = gsi_channel_props.ring_len; + ep_rx->gsi_mem_info.chan_ring_base_addr = + gsi_channel_props.ring_base_addr; + + /* write channel scratch, do we need this? */ + memset(&ch_scratch, 0, sizeof(ch_scratch)); + ch_scratch.qdss.bam_p_evt_dest_addr = in->bam_p_evt_dest_addr; + ch_scratch.qdss.data_fifo_base_addr = in->data_fifo_base_addr; + ch_scratch.qdss.data_fifo_size = in->data_fifo_size; + ch_scratch.qdss.bam_p_evt_threshold = in->bam_p_evt_threshold; + ch_scratch.qdss.override_eot = in->override_eot; + result = gsi_write_channel_scratch( + ep_rx->gsi_chan_hdl, ch_scratch); + if (result != GSI_STATUS_SUCCESS) { + IPA_QDSS_ERR("failed to write channel scratch\n"); + goto fail_write_scratch; + } + + /* query channel db address */ + if (gsi_query_channel_db_addr(ep_rx->gsi_chan_hdl, + &gsi_db_addr_low, &gsi_db_addr_high)) { + IPA_QDSS_ERR("failed to query gsi rx db addr\n"); + goto fail_write_scratch; + } + out->ipa_rx_db_pa = (phys_addr_t)(gsi_db_addr_low); + IPA_QDSS_DBG("QDSS out->ipa_rx_db_pa %llu\n", out->ipa_rx_db_pa); + + /* Configuring HOLB on MHI endpoint */ + memset(&holb_cfg, 0, sizeof(holb_cfg)); + holb_cfg.en = IPA_HOLB_TMR_EN; + holb_cfg.tmr_val = IPA_HOLB_TMR_VALUE; + result = ipa3_force_cfg_ep_holb(ipa_ep_idx_tx, &holb_cfg); + if (result) + IPA_QDSS_ERR("Configuring HOLB failed client_type =%d\n", + IPA_CLIENT_MHI_QDSS_CONS); + + /* Set DMA */ + IPA_QDSS_DBG("DMA from %d to %d", IPA_CLIENT_QDSS_PROD, + IPA_CLIENT_MHI_QDSS_CONS); + ep_cfg.mode.mode = IPA_DMA; + ep_cfg.mode.dst = IPA_CLIENT_MHI_QDSS_CONS; + ep_cfg.seq.set_dynamic = true; + if (ipa3_cfg_ep(ipa_get_ep_mapping(IPA_CLIENT_QDSS_PROD), + &ep_cfg)) { + IPA_QDSS_ERR("Setting DMA mode failed\n"); + goto fail_write_scratch; + } + + /* Start QDSS_rx gsi channel */ + result = ipa3_start_gsi_channel(ipa_ep_idx_rx); + if (result) { + IPA_QDSS_ERR("Failed starting QDSS gsi channel\n"); + goto fail_write_scratch; + } + + IPA_QDSS_DBG("QDSS connect pipe success"); + + return IPA_QDSS_SUCCESS; + +fail_write_scratch: + gsi_dealloc_channel(ep_rx->gsi_chan_hdl); + memset(ep_rx, 0, sizeof(struct ipa3_ep_context)); +fail: + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + return -IPA_QDSS_PIPE_CONN_FAILURE; +} +EXPORT_SYMBOL(ipa_qdss_conn_pipes); + +int ipa_qdss_disconn_pipes(void) +{ + int result = 0; + int ipa_ep_idx_rx; + struct ipa3_ep_context *ep_rx; + struct ipa_ep_cfg ep_cfg = { { 0 } }; + + ipa_ep_idx_rx = ipa_get_ep_mapping(IPA_CLIENT_QDSS_PROD); + if (ipa_ep_idx_rx == -1) { + IPA_QDSS_ERR("fail to get ep mapping\n"); + return -IPA_QDSS_PIPE_DISCONN_FAILURE; + } + + if (ipa_ep_idx_rx >= IPA3_MAX_NUM_PIPES) { + IPA_QDSS_ERR("ep out of range.\n"); + return -IPA_QDSS_PIPE_DISCONN_FAILURE; + } + + /* Stop QDSS_rx gsi channel / release channel */ + result = ipa_stop_gsi_channel(ipa_ep_idx_rx); + if (result) { + IPA_QDSS_ERR("Failed stopping QDSS gsi channel\n"); + goto fail; + } + + /* Resetting gsi channel */ + result = ipa3_reset_gsi_channel(ipa_ep_idx_rx); + if (result) { + IPA_QDSS_ERR("Failed resetting QDSS gsi channel\n"); + goto fail; + } + + /* Reset DMA */ + IPA_QDSS_ERR("Resetting DMA %d to %d", + IPA_CLIENT_QDSS_PROD, IPA_CLIENT_MHI_QDSS_CONS); + ep_cfg.mode.mode = IPA_BASIC; + ep_cfg.mode.dst = IPA_CLIENT_MHI_QDSS_CONS; + ep_cfg.seq.set_dynamic = true; + if (ipa3_cfg_ep(ipa_get_ep_mapping(IPA_CLIENT_QDSS_PROD), + &ep_cfg)) { + IPAERR("Resetting DMA mode failed\n"); + } + + /* Deallocating and Clearing ep config */ + ep_rx = &ipa3_ctx->ep[ipa_ep_idx_rx]; + gsi_dealloc_channel(ep_rx->gsi_chan_hdl); + memset(ep_rx, 0, sizeof(struct ipa3_ep_context)); + + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + IPA_QDSS_DBG("QDSS disconnect pipe success"); + + return IPA_QDSS_SUCCESS; +fail: + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + return -IPA_QDSS_PIPE_DISCONN_FAILURE; +} +EXPORT_SYMBOL(ipa_qdss_disconn_pipes); diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_qmi_service.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_qmi_service.c new file mode 100644 index 0000000000..976a27f648 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_qmi_service.c @@ -0,0 +1,2857 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2013-2021, The Linux Foundation. All rights reserved. + * + * Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include "ipa.h" +#include + +#include "ipa_qmi_service.h" +#include "ipa_mhi_proxy.h" +#include "ipa_i.h" + + +#define IPA_Q6_SVC_VERS 1 +#define IPA_A5_SVC_VERS 1 +#define Q6_QMI_COMPLETION_TIMEOUT (60*HZ) + +#define IPA_A5_SERVICE_SVC_ID 0x31 +#define IPA_A5_SERVICE_INS_ID 1 +#define IPA_Q6_SERVICE_SVC_ID 0x31 +#define IPA_Q6_SERVICE_INS_ID 2 + +#define IPA_PER_STATS_SMEM_SIZE (2*1024) + +#define QMI_SEND_STATS_REQ_TIMEOUT_MS 5000 +#define QMI_SEND_REQ_TIMEOUT_MS 10000 +#define QMI_MHI_SEND_REQ_TIMEOUT_MS 1000 + +#define QMI_IPA_FORCE_CLEAR_DATAPATH_TIMEOUT_MS 1000 + +static struct qmi_handle *ipa3_svc_handle; +static struct workqueue_struct *ipa_clnt_req_workqueue; +static bool ipa3_qmi_modem_init_fin, ipa3_qmi_indication_fin; +static struct work_struct ipa3_qmi_service_init_work; +static uint32_t ipa_wan_platform; +struct ipa3_qmi_context *ipa3_qmi_ctx; +static bool workqueues_stopped; +static bool ipa3_modem_init_cmplt; +static bool first_time_handshake; +static bool send_qmi_init_q6; +static bool nat_move_qmi_disabled; +struct mutex ipa3_qmi_lock; +struct ipa_msg_desc { + uint16_t msg_id; + int max_msg_len; + struct qmi_elem_info *ei_array; +}; + +static struct ipa_mhi_prime_aggr_info_req_msg_v01 aggr_req = { + .aggr_info_valid = 1, + .aggr_info_len = 5, + .aggr_info[0] = { + .ic_type = DATA_IC_TYPE_MHI_PRIME_V01, + .ep_type = DATA_EP_DESC_TYPE_DPL_PROD_V01, + .bytes_count = 16, + }, + .aggr_info[1] = { + .ic_type = DATA_IC_TYPE_MHI_PRIME_V01, + .ep_type = DATA_EP_DESC_TYPE_TETH_CONS_V01, + .bytes_count = 24, + .aggr_type = DATA_AGGR_TYPE_QMAPv5_V01, + }, + .aggr_info[2] = { + .ic_type = DATA_IC_TYPE_MHI_PRIME_V01, + .ep_type = DATA_EP_DESC_TYPE_TETH_PROD_V01, + .bytes_count = 16, + .aggr_type = DATA_AGGR_TYPE_QMAPv5_V01, + }, + .aggr_info[3] = { + .ic_type = DATA_IC_TYPE_MHI_PRIME_V01, + .ep_type = DATA_EP_DESC_TYPE_TETH_RMNET_CONS_V01, + .bytes_count = 31, + .aggr_type = DATA_AGGR_TYPE_QMAPv5_V01, + }, + .aggr_info[4] = { + .ic_type = DATA_IC_TYPE_MHI_PRIME_V01, + .ep_type = DATA_EP_DESC_TYPE_TETH_RMNET_PROD_V01, + .bytes_count = 31, + .aggr_type = DATA_AGGR_TYPE_QMAPv5_V01, + }, +}; + +/* QMI A5 service */ + +static void ipa3_handle_indication_req(struct qmi_handle *qmi_handle, + struct sockaddr_qrtr *sq, + struct qmi_txn *txn, + const void *decoded_msg) +{ + struct ipa_indication_reg_req_msg_v01 *indication_req; + struct ipa_indication_reg_resp_msg_v01 resp; + struct ipa_master_driver_init_complt_ind_msg_v01 ind; + int rc; + + indication_req = (struct ipa_indication_reg_req_msg_v01 *)decoded_msg; + IPAWANDBG("Received INDICATION Request\n"); + + /* cache the client sq */ + memcpy(&ipa3_qmi_ctx->client_sq, sq, sizeof(*sq)); + + memset(&resp, 0, sizeof(struct ipa_indication_reg_resp_msg_v01)); + resp.resp.result = IPA_QMI_RESULT_SUCCESS_V01; + + IPAWANDBG("qmi_snd_rsp: result %d, err %d\n", + resp.resp.result, resp.resp.error); + rc = qmi_send_response(qmi_handle, sq, txn, + QMI_IPA_INDICATION_REGISTER_RESP_V01, + QMI_IPA_INDICATION_REGISTER_RESP_MAX_MSG_LEN_V01, + ipa3_indication_reg_resp_msg_data_v01_ei, + &resp); + + if (rc < 0) { + IPAWANERR("send response for Indication register failed\n"); + return; + } + + ipa3_qmi_indication_fin = true; + + /* check if need sending indication to modem */ + if (ipa3_qmi_modem_init_fin) { + IPAWANDBG("send indication to modem (%d)\n", + ipa3_qmi_modem_init_fin); + memset(&ind, 0, sizeof(struct + ipa_master_driver_init_complt_ind_msg_v01)); + ind.master_driver_init_status.result = + IPA_QMI_RESULT_SUCCESS_V01; + + rc = qmi_send_indication(qmi_handle, + &(ipa3_qmi_ctx->client_sq), + QMI_IPA_MASTER_DRIVER_INIT_COMPLETE_IND_V01, + QMI_IPA_MASTER_DRIVER_INIT_COMPLETE_IND_MAX_MSG_LEN_V01, + ipa3_master_driver_init_complt_ind_msg_data_v01_ei, + &ind); + + if (rc < 0) { + IPAWANERR("send indication failed\n"); + ipa3_qmi_indication_fin = false; + } + } else { + IPAWANERR("not send indication\n"); + } +} + +static void ipa3_handle_install_filter_rule_req(struct qmi_handle *qmi_handle, + struct sockaddr_qrtr *sq, + struct qmi_txn *txn, + const void *decoded_msg) +{ + struct ipa_install_fltr_rule_req_msg_v01 *rule_req; + struct ipa_install_fltr_rule_resp_msg_v01 resp; + uint32_t rule_hdl[MAX_NUM_Q6_RULE]; + int rc = 0, i; + + rule_req = (struct ipa_install_fltr_rule_req_msg_v01 *)decoded_msg; + memset(rule_hdl, 0, sizeof(rule_hdl)); + memset(&resp, 0, sizeof(struct ipa_install_fltr_rule_resp_msg_v01)); + IPAWANDBG("Received install filter Request\n"); + + rc = ipa3_copy_ul_filter_rule_to_ipa((struct + ipa_install_fltr_rule_req_msg_v01*)decoded_msg); + + if (rc) { + IPAWANERR("copy UL rules from modem is failed\n"); + return; + } + + resp.resp.result = IPA_QMI_RESULT_SUCCESS_V01; + if (rule_req->filter_spec_ex_list_valid == true) { + resp.rule_id_valid = 1; + if (rule_req->filter_spec_ex_list_len > MAX_NUM_Q6_RULE) { + resp.rule_id_len = MAX_NUM_Q6_RULE; + IPAWANERR("installed (%d) max Q6-UL rules ", + MAX_NUM_Q6_RULE); + IPAWANERR("but modem gives total (%u)\n", + rule_req->filter_spec_ex_list_len); + } else { + resp.rule_id_len = + rule_req->filter_spec_ex_list_len; + } + } else { + resp.rule_id_valid = 0; + resp.rule_id_len = 0; + } + + /* construct UL filter rules response to Modem*/ + for (i = 0; i < resp.rule_id_len; i++) { + resp.rule_id[i] = + rule_req->filter_spec_ex_list[i].rule_id; + } + + IPAWANDBG("qmi_snd_rsp: result %d, err %d\n", + resp.resp.result, resp.resp.error); + rc = qmi_send_response(qmi_handle, sq, txn, + QMI_IPA_INSTALL_FILTER_RULE_RESP_V01, + QMI_IPA_INSTALL_FILTER_RULE_RESP_MAX_MSG_LEN_V01, + ipa3_install_fltr_rule_resp_msg_data_v01_ei, + &resp); + + if (rc < 0) + IPAWANERR("install filter rules failed\n"); + else + IPAWANDBG("Replied to install filter request\n"); +} + +static void ipa3_handle_filter_installed_notify_req( + struct qmi_handle *qmi_handle, + struct sockaddr_qrtr *sq, + struct qmi_txn *txn, + const void *decoded_msg) +{ + struct ipa_fltr_installed_notif_resp_msg_v01 resp; + int rc = 0; + + memset(&resp, 0, sizeof(struct ipa_fltr_installed_notif_resp_msg_v01)); + IPAWANDBG("Received filter_install_notify Request\n"); + resp.resp.result = IPA_QMI_RESULT_SUCCESS_V01; + + IPAWANDBG("qmi_snd_rsp: result %d, err %d\n", + resp.resp.result, resp.resp.error); + rc = qmi_send_response(qmi_handle, sq, txn, + QMI_IPA_FILTER_INSTALLED_NOTIF_RESP_V01, + QMI_IPA_FILTER_INSTALLED_NOTIF_RESP_MAX_MSG_LEN_V01, + ipa3_fltr_installed_notif_resp_msg_data_v01_ei, + &resp); + + if (rc < 0) + IPAWANERR("handle filter rules failed\n"); + else + IPAWANDBG("Responsed filter_install_notify Request\n"); +} + +static void handle_ipa_config_req(struct qmi_handle *qmi_handle, + struct sockaddr_qrtr *sq, + struct qmi_txn *txn, + const void *decoded_msg) +{ + struct ipa_config_resp_msg_v01 resp; + int rc; + + memset(&resp, 0, sizeof(struct ipa_config_resp_msg_v01)); + resp.resp.result = IPA_QMI_RESULT_SUCCESS_V01; + IPAWANDBG("Received IPA CONFIG Request\n"); + rc = ipa_mhi_handle_ipa_config_req( + (struct ipa_config_req_msg_v01 *)decoded_msg); + if (rc) { + IPAERR("ipa3_mhi_handle_ipa_config_req failed %d\n", rc); + resp.resp.result = IPA_QMI_RESULT_FAILURE_V01; + } + + IPAWANDBG("qmi_snd_rsp: result %d, err %d\n", + resp.resp.result, resp.resp.error); + rc = qmi_send_response(qmi_handle, sq, txn, + QMI_IPA_CONFIG_RESP_V01, + QMI_IPA_CONFIG_RESP_MAX_MSG_LEN_V01, + ipa3_config_resp_msg_data_v01_ei, + &resp); + + if (rc < 0) + IPAWANERR("QMI_IPA_CONFIG_RESP_V01 failed\n"); + else + IPAWANDBG("Responsed QMI_IPA_CONFIG_RESP_V01\n"); +} + +static void ipa3_handle_modem_init_cmplt_req(struct qmi_handle *qmi_handle, + struct sockaddr_qrtr *sq, + struct qmi_txn *txn, + const void *decoded_msg) +{ + struct ipa_init_modem_driver_cmplt_req_msg_v01 *cmplt_req; + struct ipa_init_modem_driver_cmplt_resp_msg_v01 resp; + int rc; + + IPAWANDBG("Received QMI_IPA_INIT_MODEM_DRIVER_CMPLT_REQ_V01\n"); + cmplt_req = (struct ipa_init_modem_driver_cmplt_req_msg_v01 *) + decoded_msg; + + if (!ipa3_modem_init_cmplt) { + ipa3_modem_init_cmplt = true; + if (ipa3_ctx->apply_rg10_wa && ipa3_qmi_modem_init_fin == true) { + IPAWANDBG("load uc related registers (%d)\n", + ipa3_qmi_modem_init_fin); + ipa3_uc_load_notify(); + } + } + + memset(&resp, 0, sizeof(resp)); + resp.resp.result = IPA_QMI_RESULT_SUCCESS_V01; + + IPAWANDBG("qmi_snd_rsp: result %d, err %d\n", + resp.resp.result, resp.resp.error); + rc = qmi_send_response(qmi_handle, sq, txn, + QMI_IPA_INIT_MODEM_DRIVER_CMPLT_RESP_V01, + QMI_IPA_INIT_MODEM_DRIVER_CMPLT_RESP_MAX_MSG_LEN_V01, + ipa3_init_modem_driver_cmplt_resp_msg_data_v01_ei, + &resp); + + + if (rc < 0) + IPAWANERR("QMI_IPA_INIT_MODEM_DRIVER_CMPLT_RESP_V01 failed\n"); + else + IPAWANDBG("Sent QMI_IPA_INIT_MODEM_DRIVER_CMPLT_RESP_V01\n"); +} + +static void ipa3_handle_mhi_alloc_channel_req(struct qmi_handle *qmi_handle, + struct sockaddr_qrtr *sq, + struct qmi_txn *txn, + const void *decoded_msg) +{ + struct ipa_mhi_alloc_channel_req_msg_v01 *ch_alloc_req; + struct ipa_mhi_alloc_channel_resp_msg_v01 *resp = NULL; + int rc; + + IPAWANDBG("Received QMI_IPA_MHI_ALLOC_CHANNEL_REQ_V01\n"); + ch_alloc_req = (struct ipa_mhi_alloc_channel_req_msg_v01 *)decoded_msg; + + resp = imp_handle_allocate_channel_req(ch_alloc_req); + if (!resp) { + IPAWANERR("imp handle allocate channel req fails\n"); + return; + } + + IPAWANDBG("qmi_snd_rsp: result %d, err %d, arr_vald: %d, arr_len %d\n", + resp->resp.result, resp->resp.error, resp->alloc_resp_arr_valid, + resp->alloc_resp_arr_len); + rc = qmi_send_response(qmi_handle, sq, txn, + QMI_IPA_MHI_ALLOC_CHANNEL_RESP_V01, + IPA_MHI_ALLOC_CHANNEL_RESP_MSG_V01_MAX_MSG_LEN, + ipa_mhi_alloc_channel_resp_msg_v01_ei, + resp); + + if (rc < 0) + IPAWANERR("QMI_IPA_MHI_ALLOC_CHANNEL_RESP_V01 failed\n"); + else + IPAWANDBG("Sent QMI_IPA_MHI_ALLOC_CHANNEL_RESP_V01\n"); +} + +static void ipa3_handle_mhi_vote_req(struct qmi_handle *qmi_handle, + struct sockaddr_qrtr *sq, + struct qmi_txn *txn, + const void *decoded_msg) +{ + struct ipa_mhi_clk_vote_req_msg_v01 *vote_req; + struct ipa_mhi_clk_vote_resp_msg_v01 *resp = NULL, resp2; + int rc; + uint32_t bw_mbps = 0; + + vote_req = (struct ipa_mhi_clk_vote_req_msg_v01 *)decoded_msg; + IPAWANDBG("Received QMI_IPA_MHI_CLK_VOTE_REQ_V01(%d)\n", + vote_req->mhi_vote); + + memset(&resp2, 0, sizeof(struct ipa_mhi_clk_vote_resp_msg_v01)); + + /* for mpm used for ipa clk voting */ + if (ipa3_is_apq()) { + IPAWANDBG("Throughput(%d:%d) clk-rate(%d:%d)\n", + vote_req->tput_value_valid, + vote_req->tput_value, + vote_req->clk_rate_valid, + vote_req->clk_rate); + if (vote_req->clk_rate_valid) { + switch (vote_req->clk_rate) { + case QMI_IPA_CLOCK_RATE_LOW_SVS_V01: + bw_mbps = 0; + break; + case QMI_IPA_CLOCK_RATE_SVS_V01: + bw_mbps = 350; + break; + case QMI_IPA_CLOCK_RATE_NOMINAL_V01: + bw_mbps = 690; + break; + case QMI_IPA_CLOCK_RATE_TURBO_V01: + bw_mbps = 1200; + break; + default: + IPAWANERR("Note supported clk_rate (%d)\n", + vote_req->clk_rate); + bw_mbps = 0; + resp2.resp.result = IPA_QMI_RESULT_FAILURE_V01; + resp2.resp.error = + IPA_QMI_ERR_NOT_SUPPORTED_V01; + break; + } + if (ipa3_vote_for_bus_bw(&bw_mbps)) { + IPAWANERR("Failed to vote BW (%u)\n", bw_mbps); + resp2.resp.result = IPA_QMI_RESULT_FAILURE_V01; + resp2.resp.error = + IPA_QMI_ERR_NOT_SUPPORTED_V01; + } + resp = &resp2; + } else { + IPAWANERR("clk_rate_valid is false\n"); + return; + } + } else { + resp = imp_handle_vote_req(vote_req->mhi_vote); + if (!resp) { + IPAWANERR("imp handle vote req fails\n"); + return; + } + IPAWANDBG("start sending QMI_IPA_MHI_CLK_VOTE_RESP_V01\n"); + } + + IPAWANDBG("qmi_snd_rsp: result %d, err %d\n", + resp->resp.result, resp->resp.error); + rc = qmi_send_response(qmi_handle, sq, txn, + QMI_IPA_MHI_CLK_VOTE_RESP_V01, + IPA_MHI_CLK_VOTE_RESP_MSG_V01_MAX_MSG_LEN, + ipa_mhi_clk_vote_resp_msg_v01_ei, + resp); + + if (rc < 0) + IPAWANERR("QMI_IPA_MHI_CLK_VOTE_RESP_V01 failed\n"); + else + IPAWANDBG("Finished senting QMI_IPA_MHI_CLK_VOTE_RESP_V01\n"); +} + +static void ipa3_qmi_msg_free_cb(void *buff, u32 len, u32 type) +{ + kfree(buff); +} + +void ipa3_disable_move_nat_resp(void) +{ + nat_move_qmi_disabled = true; +} + +static void ipa3_handle_move_nat_req(struct qmi_handle *qmi_handle, + struct sockaddr_qrtr *sq, + struct qmi_txn *txn, + const void *decoded_msg) +{ + struct ipa_move_nat_req_msg_v01 *move_req, *req_data; + struct ipa_move_nat_resp_msg_v01 resp; + struct ipa_msg_meta msg_meta; + int rc; + + move_req = (struct ipa_move_nat_req_msg_v01 *)decoded_msg; + IPAWANDBG("Received IPA_MOVE_NAT_REQ_MSG_V01(%s)\n", + move_req->nat_move_direction == QMI_IPA_MOVE_NAT_TO_DDR_V01 ? + "TO_DDR" : "TO_SRAM"); + + memset(&resp, 0, sizeof(resp)); + resp.resp.result = IPA_QMI_RESULT_SUCCESS_V01; + + req_data = kzalloc(sizeof(struct ipa_move_nat_req_msg_v01), + GFP_KERNEL); + if (!req_data) { + IPAWANERR("allocation failed\n"); + resp.resp.result = IPA_QMI_RESULT_FAILURE_V01; + resp.resp.error = IPA_QMI_ERR_NO_MEMORY_V01; + goto send_resp; + } + + memset(&msg_meta, 0, sizeof(struct ipa_msg_meta)); + msg_meta.msg_type = IPA_MOVE_NAT_TABLE; + msg_meta.msg_len = sizeof(struct ipa_move_nat_req_msg_v01); + + req_data->nat_move_direction = move_req->nat_move_direction; + + nat_move_qmi_disabled = false; + /* + * make sure QMI is enabled before message sent to IPACM. + * real QMI coming from modem takes us out of debug mode and re enables + * the QMI indication send + */ + wmb(); + + rc = ipa_send_msg(&msg_meta, req_data, ipa3_qmi_msg_free_cb); + if (rc) { + IPAWANERR("ipa_send_msg failed: %d, notify Q6\n", rc); + resp.resp.result = IPA_QMI_RESULT_FAILURE_V01; + } +send_resp: + IPAWANDBG("qmi_snd_rsp: result %d, err %d\n", + resp.resp.result, resp.resp.error); + + rc = qmi_send_response(qmi_handle, sq, txn, + QMI_IPA_MOVE_NAT_RESP_V01, + IPA_MOVE_NAT_RESP_MSG_V01_MAX_MSG_LEN, + ipa_move_nat_resp_msg_v01_ei, + &resp); + + if (rc < 0) + IPAWANERR("QMI_IPA_MOVE_NAT_RESP_V01 failed\n"); + else + IPAWANDBG( + "Finished sending QMI_IPA_MOVE_NAT_RESP_V01, res %d\n" + , resp.resp.result); +} + +static void ipa3_a5_svc_disconnect_cb(struct qmi_handle *qmi, + unsigned int node, unsigned int port) +{ + IPAWANDBG_LOW("Received QMI client disconnect\n"); +} + +/****************************************************/ +/* QMI A5 client ->Q6 */ +/****************************************************/ +static void ipa3_q6_clnt_svc_arrive(struct work_struct *work); +static DECLARE_DELAYED_WORK(ipa3_work_svc_arrive, ipa3_q6_clnt_svc_arrive); +static void ipa3_q6_clnt_svc_exit(struct work_struct *work); +static DECLARE_DELAYED_WORK(ipa3_work_svc_exit, ipa3_q6_clnt_svc_exit); +/* Test client port for IPC Router */ +static struct qmi_handle *ipa_q6_clnt; + +static int ipa3_check_qmi_response(int rc, + int req_id, + enum ipa_qmi_result_type_v01 result, + enum ipa_qmi_error_type_v01 error, + char *resp_type) +{ + if (rc < 0) { + if (rc == -ETIMEDOUT && ipa3_rmnet_ctx.ipa_rmnet_ssr) { + IPAWANERR( + "Timeout for qmi request id %d\n", req_id); + return rc; + } + if ((rc == -ENETRESET) || (rc == -ENODEV) || (rc == -ECONNRESET)) { + IPAWANERR( + "SSR while waiting for qmi request id %d\n", req_id); + return rc; + } + IPAWANERR("Error sending qmi request id %d, rc = %d\n", + req_id, rc); + return rc; + } + if (result != IPA_QMI_RESULT_SUCCESS_V01 && + ipa3_rmnet_ctx.ipa_rmnet_ssr) { + IPAWANERR( + "Got bad response %d from request id %d (error %d)\n", + req_id, result, error); + return result; + } + IPAWANDBG_LOW("Received %s successfully\n", resp_type); + return 0; +} + +static int ipa3_qmi_send_req_wait(struct qmi_handle *client_handle, + struct ipa_msg_desc *req_desc, void *req, + struct ipa_msg_desc *resp_desc, void *resp, + unsigned long timeout_ms) +{ + struct qmi_txn txn; + int ret; + + mutex_lock(&ipa3_qmi_lock); + + if (!client_handle || client_handle != ipa_q6_clnt) { + IPADBG("Q6 QMI client pointer already freed\n"); + mutex_unlock(&ipa3_qmi_lock); + return -EINVAL; + } + + ret = qmi_txn_init(client_handle, &txn, resp_desc->ei_array, resp); + + if (ret < 0) { + IPAWANERR("QMI txn init failed, ret= %d\n", ret); + mutex_unlock(&ipa3_qmi_lock); + return ret; + } + + ret = qmi_send_request(client_handle, + &ipa3_qmi_ctx->server_sq, + &txn, + req_desc->msg_id, + req_desc->max_msg_len, + req_desc->ei_array, + req); + + + + if (ret < 0) { + qmi_txn_cancel(&txn); + mutex_unlock(&ipa3_qmi_lock); + return ret; + } + + ret = qmi_txn_wait(&txn, msecs_to_jiffies(timeout_ms)); + mutex_unlock(&ipa3_qmi_lock); + return ret; +} + +static int ipa3_qmi_init_modem_send_sync_msg(void) +{ + struct ipa_init_modem_driver_req_msg_v01 req; + struct ipa_init_modem_driver_resp_msg_v01 resp; + struct ipa_msg_desc req_desc, resp_desc; + int rc; + u16 smem_restr_bytes = ipa3_get_smem_restr_bytes(); + int wan_cons_ep; + + memset(&req, 0, sizeof(struct ipa_init_modem_driver_req_msg_v01)); + memset(&resp, 0, sizeof(struct ipa_init_modem_driver_resp_msg_v01)); + + req.platform_type_valid = true; + req.platform_type = ipa_wan_platform; + + req.hdr_tbl_info_valid = (IPA_MEM_PART(modem_hdr_size) != 0); + req.hdr_tbl_info.modem_offset_start = + IPA_MEM_PART(modem_hdr_ofst) + smem_restr_bytes; + req.hdr_tbl_info.modem_offset_end = IPA_MEM_PART(modem_hdr_ofst) + + smem_restr_bytes + IPA_MEM_PART(modem_hdr_size) - 1; + + req.v4_route_tbl_info_valid = true; + req.v4_route_tbl_info.route_tbl_start_addr = + IPA_MEM_PART(v4_rt_nhash_ofst) + smem_restr_bytes; + req.v4_route_tbl_info.num_indices = + IPA_MEM_PART(v4_modem_rt_index_hi); + req.v6_route_tbl_info_valid = true; + + req.v6_route_tbl_info.route_tbl_start_addr = + IPA_MEM_PART(v6_rt_nhash_ofst) + smem_restr_bytes; + req.v6_route_tbl_info.num_indices = + IPA_MEM_PART(v6_modem_rt_index_hi); + + req.v4_filter_tbl_start_addr_valid = true; + req.v4_filter_tbl_start_addr = + IPA_MEM_PART(v4_flt_nhash_ofst) + smem_restr_bytes; + + req.v6_filter_tbl_start_addr_valid = true; + req.v6_filter_tbl_start_addr = + IPA_MEM_PART(v6_flt_nhash_ofst) + smem_restr_bytes; + + req.modem_mem_info_valid = (IPA_MEM_PART(modem_size) != 0); + req.modem_mem_info.block_start_addr = + IPA_MEM_PART(modem_ofst) + smem_restr_bytes; + req.modem_mem_info.size = IPA_MEM_PART(modem_size); + + wan_cons_ep = ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_CONS); + if (wan_cons_ep == IPA_EP_NOT_ALLOCATED) { + IPAWANDBG("APPS_WAN_CONS is not valid\n"); + req.ctrl_comm_dest_end_pt_valid = false; + req.ctrl_comm_dest_end_pt = 0; + } else { + req.ctrl_comm_dest_end_pt_valid = true; + req.ctrl_comm_dest_end_pt = + ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_CONS); + } + + req.hdr_proc_ctx_tbl_info_valid = + (IPA_MEM_PART(modem_hdr_proc_ctx_size) != 0); + req.hdr_proc_ctx_tbl_info.modem_offset_start = + IPA_MEM_PART(modem_hdr_proc_ctx_ofst) + smem_restr_bytes; + req.hdr_proc_ctx_tbl_info.modem_offset_end = + IPA_MEM_PART(modem_hdr_proc_ctx_ofst) + + IPA_MEM_PART(modem_hdr_proc_ctx_size) + smem_restr_bytes - 1; + + req.zip_tbl_info_valid = (IPA_MEM_PART(modem_comp_decomp_size) != 0); + req.zip_tbl_info.modem_offset_start = + IPA_MEM_PART(modem_comp_decomp_size) + smem_restr_bytes; + req.zip_tbl_info.modem_offset_end = + IPA_MEM_PART(modem_comp_decomp_ofst) + + IPA_MEM_PART(modem_comp_decomp_size) + smem_restr_bytes - 1; + + /* if hashing not supported, Modem filter/routing hash + * tables should not fill with valid data. + */ + if (!ipa3_ctx_get_flag(IPA_FLTRT_NOT_HASHABLE_EN)) { + req.v4_hash_route_tbl_info_valid = true; + req.v4_hash_route_tbl_info.route_tbl_start_addr = + IPA_MEM_PART(v4_rt_hash_ofst) + smem_restr_bytes; + req.v4_hash_route_tbl_info.num_indices = + IPA_MEM_PART(v4_modem_rt_index_hi); + + req.v6_hash_route_tbl_info_valid = true; + req.v6_hash_route_tbl_info.route_tbl_start_addr = + IPA_MEM_PART(v6_rt_hash_ofst) + smem_restr_bytes; + req.v6_hash_route_tbl_info.num_indices = + IPA_MEM_PART(v6_modem_rt_index_hi); + + req.v4_hash_filter_tbl_start_addr_valid = true; + req.v4_hash_filter_tbl_start_addr = + IPA_MEM_PART(v4_flt_hash_ofst) + smem_restr_bytes; + + req.v6_hash_filter_tbl_start_addr_valid = true; + req.v6_hash_filter_tbl_start_addr = + IPA_MEM_PART(v6_flt_hash_ofst) + smem_restr_bytes; + } + req.hw_stats_quota_base_addr_valid = true; + req.hw_stats_quota_base_addr = + IPA_MEM_PART(stats_quota_q6_ofst) + smem_restr_bytes; + + req.hw_stats_quota_size_valid = true; + req.hw_stats_quota_size = IPA_MEM_PART(stats_quota_q6_size); + + req.hw_drop_stats_base_addr_valid = true; + req.hw_drop_stats_base_addr = + IPA_MEM_PART(stats_drop_ofst) + smem_restr_bytes; + + req.hw_drop_stats_table_size_valid = true; + req.hw_drop_stats_table_size = IPA_MEM_PART(stats_drop_size); + + if (ipa3_ctx->platform_type != IPA_PLAT_TYPE_APQ) { + req.per_stats_smem_info_valid = true; + req.per_stats_smem_info.size = IPA_PER_STATS_SMEM_SIZE; + req.per_stats_smem_info.block_start_addr = ipa3_ctx->per_stats_smem_pa; + } + + if (!ipa3_uc_loaded_check()) { /* First time boot */ + req.is_ssr_bootup_valid = false; + req.is_ssr_bootup = 0; + } else { /* After SSR boot */ + req.is_ssr_bootup_valid = true; + req.is_ssr_bootup = 1; + } + + req.hw_fiter_stats_info_valid = true; + req.hw_filter_stats_info.hw_filter_stats_start_addr = + IPA_MEM_PART(stats_fnr_ofst); + req.hw_filter_stats_info.hw_filter_stats_size = IPA_Q6_FNR_STATS_SIZE; + req.hw_filter_stats_info.hw_filter_stats_start_index = IPA_Q6_FNR_START_IDX; + req.hw_filter_stats_info.hw_filter_stats_end_index = IPA_Q6_FNR_END_IDX; + + req.smem_info_valid = true; + req.smem_info.size = ipa3_ctx->ipa_smem_size; + + IPAWANDBG("hw_flt stats: hw_filter_start_address = %u", req.hw_filter_stats_info.hw_filter_stats_start_addr); + IPAWANDBG("hw_flt stats: hw_filter_stats_size = %u", req.hw_filter_stats_info.hw_filter_stats_size); + IPAWANDBG("hw_flt stats: hw_filter_stats_start_index = %u", req.hw_filter_stats_info.hw_filter_stats_start_index); + IPAWANDBG("platform_type %d\n", req.platform_type); + IPAWANDBG("hdr_tbl_info.modem_offset_start %d\n", + req.hdr_tbl_info.modem_offset_start); + IPAWANDBG("hdr_tbl_info.modem_offset_end %d\n", + req.hdr_tbl_info.modem_offset_end); + IPAWANDBG("v4_route_tbl_info.route_tbl_start_addr %d\n", + req.v4_route_tbl_info.route_tbl_start_addr); + IPAWANDBG("v4_route_tbl_info.num_indices %d\n", + req.v4_route_tbl_info.num_indices); + IPAWANDBG("v6_route_tbl_info.route_tbl_start_addr %d\n", + req.v6_route_tbl_info.route_tbl_start_addr); + IPAWANDBG("v6_route_tbl_info.num_indices %d\n", + req.v6_route_tbl_info.num_indices); + IPAWANDBG("v4_filter_tbl_start_addr %d\n", + req.v4_filter_tbl_start_addr); + IPAWANDBG("v6_filter_tbl_start_addr %d\n", + req.v6_filter_tbl_start_addr); + IPAWANDBG("modem_mem_info.block_start_addr %d\n", + req.modem_mem_info.block_start_addr); + IPAWANDBG("modem_mem_info.size %d\n", + req.modem_mem_info.size); + IPAWANDBG("ctrl_comm_dest_end_pt %d\n", + req.ctrl_comm_dest_end_pt); + IPAWANDBG("is_ssr_bootup %d\n", + req.is_ssr_bootup); + IPAWANDBG("v4_hash_route_tbl_info.route_tbl_start_addr %d\n", + req.v4_hash_route_tbl_info.route_tbl_start_addr); + IPAWANDBG("v4_hash_route_tbl_info.num_indices %d\n", + req.v4_hash_route_tbl_info.num_indices); + IPAWANDBG("v6_hash_route_tbl_info.route_tbl_start_addr %d\n", + req.v6_hash_route_tbl_info.route_tbl_start_addr); + IPAWANDBG("v6_hash_route_tbl_info.num_indices %d\n", + req.v6_hash_route_tbl_info.num_indices); + IPAWANDBG("v4_hash_filter_tbl_start_addr %d\n", + req.v4_hash_filter_tbl_start_addr); + IPAWANDBG("v6_hash_filter_tbl_start_addr %d\n", + req.v6_hash_filter_tbl_start_addr); + IPAWANDBG("ipa_smem_info.size %d\n", + req.smem_info.size); + + req_desc.max_msg_len = QMI_IPA_INIT_MODEM_DRIVER_REQ_MAX_MSG_LEN_V01; + req_desc.msg_id = QMI_IPA_INIT_MODEM_DRIVER_REQ_V01; + req_desc.ei_array = ipa3_init_modem_driver_req_msg_data_v01_ei; + + resp_desc.max_msg_len = QMI_IPA_INIT_MODEM_DRIVER_RESP_MAX_MSG_LEN_V01; + resp_desc.msg_id = QMI_IPA_INIT_MODEM_DRIVER_RESP_V01; + resp_desc.ei_array = ipa3_init_modem_driver_resp_msg_data_v01_ei; + + pr_info("Sending QMI_IPA_INIT_MODEM_DRIVER_REQ_V01\n"); + if (unlikely(!ipa_q6_clnt)) + return -ETIMEDOUT; + rc = ipa3_qmi_send_req_wait(ipa_q6_clnt, + &req_desc, &req, + &resp_desc, &resp, + QMI_SEND_REQ_TIMEOUT_MS); + + if (rc < 0) { + IPAWANERR("QMI send Req %d failed, rc= %d\n", + QMI_IPA_INIT_MODEM_DRIVER_REQ_V01, + rc); + return rc; + } + + pr_info("QMI_IPA_INIT_MODEM_DRIVER_REQ_V01 response received\n"); + return ipa3_check_qmi_response(rc, + QMI_IPA_INIT_MODEM_DRIVER_REQ_V01, resp.resp.result, + resp.resp.error, "ipa_init_modem_driver_resp_msg_v01"); +} + + +static int ipa3_qmi_filter_request_ex_calc_length( + struct ipa_install_fltr_rule_req_ex_msg_v01 *req) +{ + int len = 0; + + /* caller should validate and send the req */ + /* instead of sending max length,the approximate length is calculated */ + len += ((sizeof(struct ipa_install_fltr_rule_req_ex_msg_v01)) - + (QMI_IPA_MAX_FILTERS_EX_V01 * + sizeof(struct ipa_filter_spec_ex_type_v01) - + QMI_IPA_MAX_FILTERS_EX_V01 * sizeof(uint32_t)) - + (QMI_IPA_MAX_FILTERS_V01 * + sizeof(struct ipa_filter_spec_ex2_type_v01))); + + if (req->filter_spec_ex_list_valid && + req->filter_spec_ex_list_len > 0) { + len += sizeof(struct ipa_filter_spec_ex_type_v01)* + req->filter_spec_ex_list_len; + } + if (req->xlat_filter_indices_list_valid && + req->xlat_filter_indices_list_len > 0) { + len += sizeof(uint32_t)*req->xlat_filter_indices_list_len; + } + + if (req->filter_spec_ex2_list_valid && + req->filter_spec_ex2_list_len > 0) { + len += sizeof(struct ipa_filter_spec_ex2_type_v01)* + req->filter_spec_ex2_list_len; + } + + if (req->ul_firewall_indices_list_valid && + req->ul_firewall_indices_list_len > 0) { + len += sizeof(uint32_t)*req->ul_firewall_indices_list_len; + } + + return len; +} + +/* sending filter-install-request to modem*/ +int ipa3_qmi_filter_request_ex_send( + struct ipa_install_fltr_rule_req_ex_msg_v01 *req) +{ + struct ipa_install_fltr_rule_resp_ex_msg_v01 resp; + struct ipa_msg_desc req_desc, resp_desc; + int rc; + int i; + static bool cache_filter_max_flag = false; + + /* check if modem up */ + if (!ipa3_qmi_indication_fin || + !ipa3_qmi_modem_init_fin || + !ipa_q6_clnt) { + IPAWANDBG("modem QMI haven't up yet\n"); + return -EINVAL; + } + + /* check if the filter rules from IPACM is valid */ + if (req->filter_spec_ex_list_len == 0) { + IPAWANDBG("IPACM pass zero rules to Q6\n"); + } else { + IPAWANDBG( + "IPACM pass %u rule to Q6\n",req->filter_spec_ex_list_len); + } + if (req->filter_spec_ex_list_valid && req->filter_spec_ex_list_len > + QMI_IPA_MAX_FILTERS_EX_V01) { + IPAWANDBG( + "IPACM pass the number of filtering rules exceed limit\n"); + return -EINVAL; + } else if (req->source_pipe_index_valid != 0) { + IPAWANDBG( + "IPACM passes source_pipe_index_valid not zero 0 !=%d\n", + req->source_pipe_index_valid); + return -EINVAL; + } + if (req->xlat_filter_indices_list_valid && + (req->xlat_filter_indices_list_len > + QMI_IPA_MAX_FILTERS_EX_V01)) { + IPAWANDBG( + "IPACM pass the number of filtering rules exceed limit\n"); + return -EINVAL; + } + if (req->filter_spec_ex2_list_valid && + (req->filter_spec_ex2_list_len > QMI_IPA_MAX_FILTERS_V01)) { + IPAWANDBG( + "IPACM pass the number of filtering rules exceed limit\n"); + return -EINVAL; + } + if (req->ul_firewall_indices_list_valid && + (req->ul_firewall_indices_list_len > QMI_IPA_MAX_FILTERS_V01)) { + IPAWANDBG( + "IPACM pass the number of filtering rules exceed limit\n"); + return -EINVAL; + } + + for (i = 0; i < req->filter_spec_ex_list_len; i++) { + if ((req->filter_spec_ex_list[i].ip_type != + QMI_IPA_IP_TYPE_V4_V01) && + (req->filter_spec_ex_list[i].ip_type != + QMI_IPA_IP_TYPE_V6_V01)) + return -EINVAL; + if (req->filter_spec_ex_list[i].is_mux_id_valid == false) + return -EINVAL; + if ((req->filter_spec_ex_list[i].filter_action <= + QMI_IPA_FILTER_ACTION_INVALID_V01) || + (req->filter_spec_ex_list[i].filter_action > + QMI_IPA_FILTER_ACTION_EXCEPTION_V01)) + return -EINVAL; + } + mutex_lock(&ipa3_qmi_lock); + if (ipa3_qmi_ctx != NULL) { + /* cache the qmi_filter_request */ + if( cache_filter_max_flag != true ) { + ipa3_qmi_ctx->ipa_install_fltr_rule_req_ex_msg_cache_ptr + [ipa3_qmi_ctx->num_ipa_install_fltr_rule_req_ex_msg] + = vmalloc( + sizeof(struct ipa_install_fltr_rule_req_ex_msg_v01)); + } + if(ipa3_qmi_ctx->ipa_install_fltr_rule_req_ex_msg_cache_ptr + [ipa3_qmi_ctx->num_ipa_install_fltr_rule_req_ex_msg] == NULL){ + IPAWANERR(" Memory Allocation failed \n"); + } + else { + memcpy((ipa3_qmi_ctx->ipa_install_fltr_rule_req_ex_msg_cache_ptr[ + ipa3_qmi_ctx->num_ipa_install_fltr_rule_req_ex_msg]), + req, + sizeof(struct ipa_install_fltr_rule_req_ex_msg_v01)); + ipa3_qmi_ctx->num_ipa_install_fltr_rule_req_ex_msg++; + } + if ( ipa3_qmi_ctx->num_ipa_install_fltr_rule_req_ex_msg == MAX_NUM_QMI_RULE_CACHE ) + cache_filter_max_flag = true; + ipa3_qmi_ctx->num_ipa_install_fltr_rule_req_ex_msg %= 10; + } + mutex_unlock(&ipa3_qmi_lock); + + req_desc.max_msg_len = ipa3_qmi_filter_request_ex_calc_length(req); + if( req_desc.max_msg_len < 0 ){ + IPAWANDBG( + "QMI send request length = %d\n", req_desc.max_msg_len); + return -EINVAL; + } else { + IPAWANDBG("QMI send request length = %d\n", + req_desc.max_msg_len); + } + + req_desc.msg_id = QMI_IPA_INSTALL_FILTER_RULE_EX_REQ_V01; + req_desc.ei_array = ipa3_install_fltr_rule_req_ex_msg_data_v01_ei; + + memset(&resp, 0, sizeof(struct ipa_install_fltr_rule_resp_ex_msg_v01)); + resp_desc.max_msg_len = + QMI_IPA_INSTALL_FILTER_RULE_EX_RESP_MAX_MSG_LEN_V01; + resp_desc.msg_id = QMI_IPA_INSTALL_FILTER_RULE_EX_RESP_V01; + resp_desc.ei_array = ipa3_install_fltr_rule_resp_ex_msg_data_v01_ei; + + rc = ipa3_qmi_send_req_wait(ipa_q6_clnt, + &req_desc, req, + &resp_desc, &resp, + QMI_SEND_REQ_TIMEOUT_MS); + + if (rc < 0) { + IPAWANERR("QMI send Req %d failed, rc= %d\n", + QMI_IPA_INSTALL_FILTER_RULE_EX_REQ_V01, + rc); + return rc; + } + + return ipa3_check_qmi_response(rc, + QMI_IPA_INSTALL_FILTER_RULE_EX_REQ_V01, resp.resp.result, + resp.resp.error, "ipa_install_filter"); +} + +/* sending add offload-connection-request to modem*/ +int ipa3_qmi_add_offload_request_send( + struct ipa_add_offload_connection_req_msg_v01 *req) +{ + struct ipa_add_offload_connection_resp_msg_v01 resp; + struct ipa_msg_desc req_desc, resp_desc; + int rc = 0; + int i, j; + uint32_t id; + + /* check if modem up */ + if (!ipa3_qmi_modem_init_fin || + !ipa_q6_clnt) { + IPAWANDBG("modem QMI haven't up yet\n"); + return -EINVAL; + } + + /* check if the filter rules from IPACM is valid */ + if (req->filter_spec_ex2_list_len < 0) { + IPAWANERR("IPACM pass invalid num of rules\n"); + return -EINVAL; + } else if (req->filter_spec_ex2_list_len == 0) { + IPAWANDBG("IPACM pass zero rules to Q6\n"); + } else { + IPAWANDBG("IPACM pass %u rules to Q6\n", + req->filter_spec_ex2_list_len); + } + + /* currently set total max to 64 */ + if ((ipa3_qmi_ctx->num_ipa_offload_connection < 0) || + (req->filter_spec_ex2_list_len >= + (QMI_IPA_MAX_FILTERS_V01 - + ipa3_qmi_ctx->num_ipa_offload_connection))) { + IPAWANDBG( + "cur(%d), req(%d), exceed limit (%d)\n", + ipa3_qmi_ctx->num_ipa_offload_connection, + req->filter_spec_ex2_list_len, + QMI_IPA_MAX_FILTERS_V01); + return -EINVAL; + } + + for (i = 0; i < req->filter_spec_ex2_list_len; i++) { + if ((req->filter_spec_ex2_list[i].ip_type != + QMI_IPA_IP_TYPE_V4_V01) && + (req->filter_spec_ex2_list[i].ip_type != + QMI_IPA_IP_TYPE_V6_V01)) + return -EINVAL; + if (req->filter_spec_ex2_list[i].is_mux_id_valid == false) + return -EINVAL; + if ((req->filter_spec_ex2_list[i].filter_action <= + QMI_IPA_FILTER_ACTION_INVALID_V01) || + (req->filter_spec_ex2_list[i].filter_action > + QMI_IPA_FILTER_ACTION_EXCEPTION_V01)) + return -EINVAL; + } + + req_desc.max_msg_len = + IPA_ADD_OFFLOAD_CONNECTION_REQ_MSG_V01_MAX_MSG_LEN; + req_desc.msg_id = QMI_IPA_ADD_OFFLOAD_CONNECTION_REQ_V01; + req_desc.ei_array = ipa_add_offload_connection_req_msg_v01_ei; + + memset(&resp, 0, sizeof(struct + ipa_add_offload_connection_resp_msg_v01)); + resp_desc.max_msg_len = + IPA_ADD_OFFLOAD_CONNECTION_RESP_MSG_V01_MAX_MSG_LEN; + resp_desc.msg_id = QMI_IPA_ADD_OFFLOAD_CONNECTION_RESP_V01; + resp_desc.ei_array = ipa_add_offload_connection_resp_msg_v01_ei; + + rc = ipa3_qmi_send_req_wait(ipa_q6_clnt, + &req_desc, req, + &resp_desc, &resp, + QMI_SEND_REQ_TIMEOUT_MS); + + if (rc < 0) { + IPAWANERR("QMI send Req %d failed, rc= %d\n", + QMI_IPA_ADD_OFFLOAD_CONNECTION_REQ_V01, + rc); + return rc; + } + + rc = ipa3_check_qmi_response(rc, + QMI_IPA_ADD_OFFLOAD_CONNECTION_REQ_V01, resp.resp.result, + resp.resp.error, "ipa_add_offload_connection"); + + if (rc) { + IPAWANERR("QMI get Response %d failed, rc= %d\n", + QMI_IPA_ADD_OFFLOAD_CONNECTION_REQ_V01, + rc); + return rc; + } + + /* Check & copy rule-handle */ + if (!resp.filter_handle_list_valid) { + IPAWANERR("QMI resp invalid %d failed\n", + resp.filter_handle_list_valid); + return -ERANGE; + } + + if (resp.filter_handle_list_len != + req->filter_spec_ex2_list_len) { + IPAWANERR("QMI resp invalid size %d req %d\n", + resp.filter_handle_list_len, + req->filter_spec_ex2_list_len); + return -ERANGE; + } + + mutex_lock(&ipa3_qmi_lock); + for (i = 0; i < req->filter_spec_ex2_list_len; i++) { + id = resp.filter_handle_list[i].filter_spec_identifier; + /* check rule-id matched or not */ + if (req->filter_spec_ex2_list[i].rule_id != + id) { + IPAWANERR("QMI error (%d)st-(%d) rule-id (%d)\n", + i, + id, + req->filter_spec_ex2_list[i].rule_id); + mutex_unlock(&ipa3_qmi_lock); + return -EINVAL; + } + /* find free spot*/ + for (j = 0; j < QMI_IPA_MAX_FILTERS_V01; j++) { + if (!ipa3_qmi_ctx->ipa_offload_cache[j].valid) + break; + } + + if (j == QMI_IPA_MAX_FILTERS_V01) { + IPAWANERR("can't find free spot for rule-id %d\n", + id); + mutex_unlock(&ipa3_qmi_lock); + return -EINVAL; + } + + /* save rule-id handle to cache */ + ipa3_qmi_ctx->ipa_offload_cache[j].rule_id = + resp.filter_handle_list[i].filter_spec_identifier; + ipa3_qmi_ctx->ipa_offload_cache[j].rule_hdl = + resp.filter_handle_list[i].filter_handle; + ipa3_qmi_ctx->ipa_offload_cache[j].valid = true; + ipa3_qmi_ctx->ipa_offload_cache[j].ip_type = + req->filter_spec_ex2_list[i].ip_type; + ipa3_qmi_ctx->num_ipa_offload_connection++; + } + mutex_unlock(&ipa3_qmi_lock); + IPAWANDBG("Update cached conntrack entries (%d)\n", + ipa3_qmi_ctx->num_ipa_offload_connection); + return rc; +} + +/* sending rmv offload-connection-request to modem*/ +int ipa3_qmi_rmv_offload_request_send( + struct ipa_remove_offload_connection_req_msg_v01 *req) +{ + struct ipa_remove_offload_connection_resp_msg_v01 resp; + struct ipa_msg_desc req_desc, resp_desc; + int rc = 0; + int i, j; + uint32_t id; + + /* check if modem up */ + if (!ipa3_qmi_modem_init_fin || + !ipa_q6_clnt) { + IPAWANDBG("modem QMI haven't up yet\n"); + return -EINVAL; + } + + /* check if the # of handles from IPACM is valid */ + if (!req->clean_all_rules_valid && req->filter_handle_list_len == 0) { + IPAWANDBG("IPACM deleted zero rules !\n"); + return -EINVAL; + } + + IPAWANDBG("IPACM pass (%d) rules handles to Q6, cur (%d)\n", + req->filter_handle_list_len, + ipa3_qmi_ctx->num_ipa_offload_connection); + + /* max as num_ipa_offload_connection */ + if (req->filter_handle_list_len > + ipa3_qmi_ctx->num_ipa_offload_connection) { + IPAWANDBG( + "cur(%d), req_rmv(%d)\n", + ipa3_qmi_ctx->num_ipa_offload_connection, + req->filter_handle_list_len); + return -EINVAL; + } + + mutex_lock(&ipa3_qmi_lock); + for (i = 0; i < req->filter_handle_list_len; i++) { + /* check if rule-id match */ + id = + req->filter_handle_list[i].filter_spec_identifier; + for (j = 0; j < QMI_IPA_MAX_FILTERS_V01; j++) { + if ((ipa3_qmi_ctx->ipa_offload_cache[j].valid) && + (ipa3_qmi_ctx->ipa_offload_cache[j].rule_id == + id)) + break; + } + if (j == QMI_IPA_MAX_FILTERS_V01) { + IPAWANERR("can't find rule-id %d\n", + id); + mutex_unlock(&ipa3_qmi_lock); + return -EINVAL; + } + + /* fill up the filter_handle */ + req->filter_handle_list[i].filter_handle = + ipa3_qmi_ctx->ipa_offload_cache[j].rule_hdl; + ipa3_qmi_ctx->ipa_offload_cache[j].valid = false; + ipa3_qmi_ctx->num_ipa_offload_connection--; + } + mutex_unlock(&ipa3_qmi_lock); + + req_desc.max_msg_len = + IPA_REMOVE_OFFLOAD_CONNECTION_REQ_MSG_V01_MAX_MSG_LEN; + req_desc.msg_id = QMI_IPA_REMOVE_OFFLOAD_CONNECTION_REQ_V01; + req_desc.ei_array = ipa_remove_offload_connection_req_msg_v01_ei; + + /* clean the Dl rules in the cache if flag is set */ + if (req->clean_all_rules) { + for (i = 0; i < QMI_IPA_MAX_FILTERS_V01; i++) + if (ipa3_qmi_ctx->ipa_offload_cache[i].valid) + ipa3_qmi_ctx->ipa_offload_cache[i].valid = + false; + } + + + memset(&resp, 0, sizeof(struct + ipa_remove_offload_connection_resp_msg_v01)); + resp_desc.max_msg_len = + IPA_REMOVE_OFFLOAD_CONNECTION_RESP_MSG_V01_MAX_MSG_LEN; + resp_desc.msg_id = QMI_IPA_REMOVE_OFFLOAD_CONNECTION_RESP_V01; + resp_desc.ei_array = ipa_remove_offload_connection_resp_msg_v01_ei; + + rc = ipa3_qmi_send_req_wait(ipa_q6_clnt, + &req_desc, req, + &resp_desc, &resp, + QMI_SEND_REQ_TIMEOUT_MS); + + if (rc < 0) { + IPAWANERR("QMI send Req %d failed, rc= %d\n", + QMI_IPA_REMOVE_OFFLOAD_CONNECTION_REQ_V01, + rc); + return rc; + } + IPAWANDBG("left cached conntrack entries (%d)\n", + ipa3_qmi_ctx->num_ipa_offload_connection); + + return ipa3_check_qmi_response(rc, + QMI_IPA_REMOVE_OFFLOAD_CONNECTION_REQ_V01, resp.resp.result, + resp.resp.error, "ipa_rmv_offload_connection"); +} + +/* sending ul-filter-install-request to modem*/ +int ipa3_qmi_ul_filter_request_send( + struct ipa_configure_ul_firewall_rules_req_msg_v01 *req) +{ + struct ipa_configure_ul_firewall_rules_resp_msg_v01 resp; + struct ipa_msg_desc req_desc, resp_desc; + int rc, i; + static bool cache_max_flag = false; + + IPAWANDBG("IPACM pass %u rules to Q6\n", + req->firewall_rules_list_len); + + mutex_lock(&ipa3_qmi_lock); + if (ipa3_qmi_ctx != NULL) { + /* cache the qmi_filter_request */ + if( cache_max_flag != true ) { + ipa3_qmi_ctx->ipa_configure_ul_firewall_rules_req_msg_cache_ptr + [ipa3_qmi_ctx->num_ipa_configure_ul_firewall_rules_req_msg] + = vmalloc( + sizeof(struct ipa_configure_ul_firewall_rules_req_msg_v01)); + } + if(ipa3_qmi_ctx->ipa_configure_ul_firewall_rules_req_msg_cache_ptr + [ipa3_qmi_ctx->num_ipa_configure_ul_firewall_rules_req_msg] == NULL){ + IPAWANERR_RL(" Memory Allocation failed \n"); + } + else{ + memcpy( + (ipa3_qmi_ctx->ipa_configure_ul_firewall_rules_req_msg_cache_ptr[ + ipa3_qmi_ctx->num_ipa_configure_ul_firewall_rules_req_msg]), + req, + sizeof(struct + ipa_configure_ul_firewall_rules_req_msg_v01)); + ipa3_qmi_ctx->num_ipa_configure_ul_firewall_rules_req_msg++; + } + if( ipa3_qmi_ctx->num_ipa_configure_ul_firewall_rules_req_msg == MAX_NUM_QMI_RULE_CACHE ) + cache_max_flag = true; + ipa3_qmi_ctx->num_ipa_configure_ul_firewall_rules_req_msg %= + MAX_NUM_QMI_RULE_CACHE; + } + mutex_unlock(&ipa3_qmi_lock); + + /* check if modem is up */ + if (!ipa3_qmi_indication_fin || + !ipa3_qmi_modem_init_fin || + !ipa_q6_clnt) { + IPAWANDBG("modem QMI service is not up yet\n"); + return -EINVAL; + } + + /* Passing 0 rules means that firewall is disabled */ + if (req->firewall_rules_list_len == 0) + IPAWANDBG("IPACM passed 0 rules to Q6\n"); + + if (req->firewall_rules_list_len >= QMI_IPA_MAX_UL_FIREWALL_RULES_V01) { + IPAWANERR_RL( + "Number of rules passed by IPACM, %d, exceed limit %d\n", + req->firewall_rules_list_len, + QMI_IPA_MAX_UL_FIREWALL_RULES_V01); + return -EINVAL; + } + + /* Check for valid IP type */ + for (i = 0; i < req->firewall_rules_list_len; i++) { + if (req->firewall_rules_list[i].ip_type != + QMI_IPA_IP_TYPE_V4_V01 && + req->firewall_rules_list[i].ip_type != + QMI_IPA_IP_TYPE_V6_V01) { + IPAWANERR_RL("Invalid IP type %d\n", + req->firewall_rules_list[i].ip_type); + return -EINVAL; + } + } + + req_desc.max_msg_len = + QMI_IPA_INSTALL_UL_FIREWALL_RULES_REQ_MAX_MSG_LEN_V01; + req_desc.msg_id = QMI_IPA_INSTALL_UL_FIREWALL_RULES_REQ_V01; + req_desc.ei_array = + ipa3_configure_ul_firewall_rules_req_msg_data_v01_ei; + + memset(&resp, 0, + sizeof(struct ipa_configure_ul_firewall_rules_resp_msg_v01)); + resp_desc.max_msg_len = + QMI_IPA_INSTALL_UL_FIREWALL_RULES_RESP_MAX_MSG_LEN_V01; + resp_desc.msg_id = QMI_IPA_INSTALL_UL_FIREWALL_RULES_RESP_V01; + resp_desc.ei_array = + ipa3_configure_ul_firewall_rules_resp_msg_data_v01_ei; + rc = ipa3_qmi_send_req_wait(ipa_q6_clnt, + &req_desc, req, + &resp_desc, &resp, + QMI_SEND_REQ_TIMEOUT_MS); + if (rc < 0) { + IPAWANERR_RL("send Req %d failed, rc= %d\n", + QMI_IPA_INSTALL_UL_FIREWALL_RULES_REQ_V01, + rc); + return rc; + } + + return ipa3_check_qmi_response(rc, + QMI_IPA_INSTALL_UL_FIREWALL_RULES_REQ_V01, + resp.resp.result, + resp.resp.error, "ipa_received_ul_firewall_filter"); +} + +int ipa3_qmi_enable_force_clear_datapath_send( + struct ipa_enable_force_clear_datapath_req_msg_v01 *req) +{ + struct ipa_enable_force_clear_datapath_resp_msg_v01 resp; + struct ipa_msg_desc req_desc, resp_desc; + int rc = 0; + + if (!req || + !((ipa3_ctx->ipa_hw_type < IPA_HW_v5_0 && + req->source_pipe_bitmask) || + (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0 && + req->source_pipe_bitmask_ext_valid && + (req->source_pipe_bitmask_ext[0] || + req->source_pipe_bitmask_ext[1] || + req->source_pipe_bitmask_ext[2] || + req->source_pipe_bitmask_ext[3])))) { + IPAWANERR("invalid params\n"); + return -EINVAL; + } + + if (ipa3_ctx_get_type(IPA3_HW_MODE) == IPA_HW_MODE_VIRTUAL || + ipa3_ctx_get_type(IPA3_HW_MODE) == IPA_HW_MODE_EMULATION) { + IPAWANDBG("Simulating success on emu/virt mode\n"); + return 0; + } + + req_desc.max_msg_len = + QMI_IPA_ENABLE_FORCE_CLEAR_DATAPATH_REQ_MAX_MSG_LEN_V01; + req_desc.msg_id = QMI_IPA_ENABLE_FORCE_CLEAR_DATAPATH_REQ_V01; + req_desc.ei_array = + ipa3_enable_force_clear_datapath_req_msg_data_v01_ei; + + memset(&resp, 0, sizeof(struct ipa_fltr_installed_notif_resp_msg_v01)); + resp_desc.max_msg_len = + QMI_IPA_ENABLE_FORCE_CLEAR_DATAPATH_RESP_MAX_MSG_LEN_V01; + resp_desc.msg_id = QMI_IPA_ENABLE_FORCE_CLEAR_DATAPATH_RESP_V01; + resp_desc.ei_array = + ipa3_enable_force_clear_datapath_resp_msg_data_v01_ei; + + if (unlikely(!ipa_q6_clnt)) + return -ETIMEDOUT; + rc = ipa3_qmi_send_req_wait(ipa_q6_clnt, + &req_desc, req, + &resp_desc, &resp, + QMI_IPA_FORCE_CLEAR_DATAPATH_TIMEOUT_MS); + + if (rc < 0) { + IPAWANERR("send Req %d failed, rc= %d\n", + QMI_IPA_ENABLE_FORCE_CLEAR_DATAPATH_REQ_V01, + rc); + return rc; + } + + if (resp.resp.result != IPA_QMI_RESULT_SUCCESS_V01) { + IPAWANERR("filter_notify failed %d\n", + resp.resp.result); + return resp.resp.result; + } + + return ipa3_check_qmi_response(rc, + QMI_IPA_ENABLE_FORCE_CLEAR_DATAPATH_REQ_V01, + resp.resp.result, + resp.resp.error, "ipa_enable_force_clear_datapath"); +} +EXPORT_SYMBOL(ipa3_qmi_enable_force_clear_datapath_send); + +int ipa3_qmi_disable_force_clear_datapath_send( + struct ipa_disable_force_clear_datapath_req_msg_v01 *req) +{ + struct ipa_disable_force_clear_datapath_resp_msg_v01 resp; + struct ipa_msg_desc req_desc, resp_desc; + int rc = 0; + + + if (!req) { + IPAWANERR("invalid params\n"); + return -EINVAL; + } + + if (ipa3_ctx_get_type(IPA3_HW_MODE) == IPA_HW_MODE_VIRTUAL || + ipa3_ctx_get_type(IPA3_HW_MODE) == IPA_HW_MODE_EMULATION) { + IPAWANDBG("Simulating success on emu/virt mode\n"); + return 0; + } + + req_desc.max_msg_len = + QMI_IPA_DISABLE_FORCE_CLEAR_DATAPATH_REQ_MAX_MSG_LEN_V01; + req_desc.msg_id = QMI_IPA_DISABLE_FORCE_CLEAR_DATAPATH_REQ_V01; + req_desc.ei_array = + ipa3_disable_force_clear_datapath_req_msg_data_v01_ei; + + memset(&resp, 0, sizeof(struct ipa_fltr_installed_notif_resp_msg_v01)); + resp_desc.max_msg_len = + QMI_IPA_DISABLE_FORCE_CLEAR_DATAPATH_RESP_MAX_MSG_LEN_V01; + resp_desc.msg_id = QMI_IPA_DISABLE_FORCE_CLEAR_DATAPATH_RESP_V01; + resp_desc.ei_array = + ipa3_disable_force_clear_datapath_resp_msg_data_v01_ei; + if (unlikely(!ipa_q6_clnt)) + return -ETIMEDOUT; + rc = ipa3_qmi_send_req_wait(ipa_q6_clnt, + &req_desc, req, + &resp_desc, &resp, + QMI_IPA_FORCE_CLEAR_DATAPATH_TIMEOUT_MS); + + if (rc < 0) { + IPAWANERR("send Req %d failed, rc= %d\n", + QMI_IPA_DISABLE_FORCE_CLEAR_DATAPATH_REQ_V01, + rc); + return rc; + } + + if (resp.resp.result != IPA_QMI_RESULT_SUCCESS_V01) { + IPAWANERR("filter_notify failed %d\n", + resp.resp.result); + return resp.resp.result; + } + + return ipa3_check_qmi_response(rc, + QMI_IPA_DISABLE_FORCE_CLEAR_DATAPATH_REQ_V01, + resp.resp.result, + resp.resp.error, "ipa_disable_force_clear_datapath"); +} +EXPORT_SYMBOL(ipa3_qmi_disable_force_clear_datapath_send); + +/* sending filter-installed-notify-request to modem*/ +int ipa3_qmi_filter_notify_send( + struct ipa_fltr_installed_notif_req_msg_v01 *req) +{ + struct ipa_fltr_installed_notif_resp_msg_v01 resp; + struct ipa_msg_desc req_desc, resp_desc; + int rc = 0; + + /* check if the filter rules from IPACM is valid */ + if (req->rule_id_len == 0) { + IPAWANDBG(" delete UL filter rule for pipe %d\n", + req->source_pipe_index); + } else if (req->rule_id_len > QMI_IPA_MAX_FILTERS_V01) { + IPAWANERR(" UL filter rule for pipe %d exceed max (%u)\n", + req->source_pipe_index, + req->rule_id_len); + return -EINVAL; + } + + if (req->rule_id_ex_len == 0) { + IPAWANDBG(" delete UL filter rule for pipe %d\n", + req->source_pipe_index); + } else if (req->rule_id_ex_len > QMI_IPA_MAX_FILTERS_EX2_V01) { + IPAWANERR_RL(" UL filter rule for pipe %d exceed max (%u)\n", + req->source_pipe_index, + req->rule_id_ex_len); + return -EINVAL; + } + + if (req->install_status != IPA_QMI_RESULT_SUCCESS_V01) { + IPAWANERR_RL(" UL filter rule for pipe %d install_status = %d\n", + req->source_pipe_index, req->install_status); + return -EINVAL; + } else if ((req->rule_id_valid != 1) && + (req->rule_id_ex_valid != 1)) { + IPAWANERR(" UL filter rule for pipe %d rule_id_valid = %d/%d\n", + req->source_pipe_index, req->rule_id_valid, + req->rule_id_ex_valid); + return -EINVAL; + } else if (req->source_pipe_index >= ipa3_ctx_get_num_pipes()) { + IPAWANDBG( + "IPACM passes source pipe index not valid ID = %d\n", + req->source_pipe_index); + return -EINVAL; + } else if (((req->embedded_pipe_index_valid != true) || + (req->embedded_call_mux_id_valid != true)) && + ((req->embedded_pipe_index_valid != false) || + (req->embedded_call_mux_id_valid != false))) { + IPAWANERR( + "IPACM passes embedded pipe and mux valid not valid\n"); + return -EINVAL; + } else if (req->embedded_pipe_index >= ipa3_ctx_get_num_pipes()) { + IPAWANERR("IPACM passes source pipe index not valid ID = %d\n", + req->source_pipe_index); + return -EINVAL; + } + + if (req->source_pipe_index == -1) { + IPAWANERR("Source pipe index invalid\n"); + return -EINVAL; + } + + mutex_lock(&ipa3_qmi_lock); + if (ipa3_qmi_ctx != NULL) { + /* cache the qmi_filter_request */ + memcpy(&(ipa3_qmi_ctx->ipa_fltr_installed_notif_req_msg_cache[ + ipa3_qmi_ctx->num_ipa_fltr_installed_notif_req_msg]), + req, + sizeof(struct ipa_fltr_installed_notif_req_msg_v01)); + ipa3_qmi_ctx->num_ipa_fltr_installed_notif_req_msg++; + ipa3_qmi_ctx->num_ipa_fltr_installed_notif_req_msg %= 10; + } + mutex_unlock(&ipa3_qmi_lock); + + req_desc.max_msg_len = + QMI_IPA_FILTER_INSTALLED_NOTIF_REQ_MAX_MSG_LEN_V01; + req_desc.msg_id = QMI_IPA_FILTER_INSTALLED_NOTIF_REQ_V01; + req_desc.ei_array = ipa3_fltr_installed_notif_req_msg_data_v01_ei; + + memset(&resp, 0, sizeof(struct ipa_fltr_installed_notif_resp_msg_v01)); + resp_desc.max_msg_len = + QMI_IPA_FILTER_INSTALLED_NOTIF_RESP_MAX_MSG_LEN_V01; + resp_desc.msg_id = QMI_IPA_FILTER_INSTALLED_NOTIF_RESP_V01; + resp_desc.ei_array = ipa3_fltr_installed_notif_resp_msg_data_v01_ei; + + if (unlikely(!ipa_q6_clnt)) + return -ETIMEDOUT; + rc = ipa3_qmi_send_req_wait(ipa_q6_clnt, + &req_desc, req, + &resp_desc, &resp, + QMI_SEND_REQ_TIMEOUT_MS); + + if (rc < 0) { + IPAWANERR("send Req %d failed, rc= %d\n", + QMI_IPA_FILTER_INSTALLED_NOTIF_REQ_V01, + rc); + return rc; + } + + return ipa3_check_qmi_response(rc, + QMI_IPA_FILTER_INSTALLED_NOTIF_REQ_V01, resp.resp.result, + resp.resp.error, "ipa_fltr_installed_notif_resp"); +} + +/*sending nat table move result indication to modem */ +int rmnet_ipa3_notify_nat_move_res(bool failure) +{ + int rc; + struct ipa_move_nat_table_complt_ind_msg_v01 ind; + + IPAWANDBG("send nat table move indication to modem (%d)\n", + failure); + + if (nat_move_qmi_disabled) { + IPAWANDBG( + "not sending nat table move indication, nat_move_qmi_disabled is true" + ); + return 0; + } + memset(&ind, 0, sizeof(struct + ipa_move_nat_table_complt_ind_msg_v01)); + if (!failure) + ind.nat_table_move_status.result = + IPA_QMI_RESULT_SUCCESS_V01; + else + ind.nat_table_move_status.result = + IPA_QMI_RESULT_FAILURE_V01; + + if (unlikely(!ipa3_svc_handle)) { + IPAWANERR("Invalid svc handle.Ignore sending ind.\n"); + return -EFAULT; + } + + rc = qmi_send_indication(ipa3_svc_handle, + &ipa3_qmi_ctx->client_sq, + QMI_IPA_MOVE_NAT_COMPLETE_IND_V01, + QMI_IPA_NAT_TABLE_MOVE_COMPLETE_IND_MAX_MSG_LEN_V01, + ipa_move_nat_table_complt_ind_msg_v01_ei, + &ind); + if (rc) + IPAWANERR("qmi indication not succesfull %d\n", rc); + else + IPAWANDBG("qmi indication sent succesfully\n"); + + return rc; +} + +static void ipa3_q6_clnt_quota_reached_ind_cb(struct qmi_handle *handle, + struct sockaddr_qrtr *sq, + struct qmi_txn *txn, + const void *data) +{ + struct ipa_data_usage_quota_reached_ind_msg_v01 *qmi_ind; + bool data_warning = false; + + if (handle != ipa_q6_clnt) { + IPAWANERR("Wrong client\n"); + return; + } + + qmi_ind = (struct ipa_data_usage_quota_reached_ind_msg_v01 *) data; + +#ifdef IPA_DATA_WARNING_QUOTA + data_warning = (qmi_ind->is_warning_limit_valid && + qmi_ind->is_warning_limit); + if (qmi_ind->is_warning_limit_valid && qmi_ind->is_warning_limit) + IPAWANDBG("Warning reached indication on qmux(%d) Mbytes(%lu)\n", + qmi_ind->apn.mux_id, (unsigned long) qmi_ind->apn.num_Mbytes); + else +#endif + IPAWANDBG("Quota reached indication on qmux(%d) Mbytes(%lu)\n", + qmi_ind->apn.mux_id, (unsigned long) qmi_ind->apn.num_Mbytes); + ipa3_broadcast_quota_reach_ind(qmi_ind->apn.mux_id, + IPA_UPSTEAM_MODEM, data_warning); +} + +static void ipa3_q6_clnt_install_firewall_rules_ind_cb( + struct qmi_handle *handle, + struct sockaddr_qrtr *sq, + struct qmi_txn *txn, + const void *data) +{ + struct ipa_configure_ul_firewall_rules_ind_msg_v01 qmi_ul_firewall_ind; + + memset(&qmi_ul_firewall_ind, 0, sizeof( + struct ipa_configure_ul_firewall_rules_ind_msg_v01)); + memcpy(&qmi_ul_firewall_ind, data, sizeof( + struct ipa_configure_ul_firewall_rules_ind_msg_v01)); + + IPAWANDBG("UL firewall rules install indication on Q6"); + if (qmi_ul_firewall_ind.result.is_success == + QMI_IPA_UL_FIREWALL_STATUS_SUCCESS_V01) { + IPAWANDBG(" : Success\n"); + IPAWANDBG + ("Mux ID : %d\n", qmi_ul_firewall_ind.result.mux_id); + } else if (qmi_ul_firewall_ind.result.is_success == + QMI_IPA_UL_FIREWALL_STATUS_FAILURE_V01) { + IPAWANERR(": Failure\n"); + } else { + IPAWANERR(": Unexpected Result"); + } +} + +static void ipa3_q6_clnt_bw_change_ind_cb(struct qmi_handle *handle, + struct sockaddr_qrtr *sq, + struct qmi_txn *txn, + const void *data) +{ + struct ipa_bw_change_ind_msg_v01 *qmi_ind; + uint32_t bw_mbps = 0; + + if (handle != ipa_q6_clnt) { + IPAWANERR("Wrong client\n"); + return; + } + + qmi_ind = (struct ipa_bw_change_ind_msg_v01 *) data; + + IPAWANDBG("Q6 BW change UL valid(%d):(%d)Kbps\n", + qmi_ind->peak_bw_ul_valid, + qmi_ind->peak_bw_ul); + + IPAWANDBG("Q6 BW change DL valid(%d):(%d)Kbps\n", + qmi_ind->peak_bw_dl_valid, + qmi_ind->peak_bw_dl); + + if (qmi_ind->peak_bw_ul_valid) + bw_mbps += qmi_ind->peak_bw_ul/1000; + + if (qmi_ind->peak_bw_dl_valid) + bw_mbps += qmi_ind->peak_bw_dl/1000; + + IPAWANDBG("vote modem BW (%u)\n", bw_mbps); + if (ipa3_vote_for_bus_bw(&bw_mbps)) { + IPAWANERR("Failed to vote BW (%u)\n", bw_mbps); + } + +} + +static void ipa3_handle_ipa_wlan_opt_dp_rsrv_filter_req(struct qmi_handle *qmi_handle, + struct sockaddr_qrtr *sq, + struct qmi_txn *txn, + const void *decoded_msg) +{ + struct ipa_wlan_opt_dp_rsrv_filter_resp_msg_v01 resp; + struct ipa_wlan_opt_dp_rsrv_filter_complt_ind_msg_v01 ind; + struct ipa_wlan_opt_dp_rsrv_filter_req_msg_v01 *req = + (struct ipa_wlan_opt_dp_rsrv_filter_req_msg_v01 *)decoded_msg; + int rc = 0, rc1 = 0; + + memset(&resp, 0, sizeof(resp)); + memset(&ind, 0, sizeof(ind)); + + IPAWANDBG("rsrv_filter_req: num_fltrs %d, timeout_val %d, rtng_table %d\n", + req->num_filters, req->timeout_val_ms, req->q6_rtng_table_index); + + rc = ipa_wdi_opt_dpath_rsrv_filter_req(req, &resp); + + IPAWANDBG("qmi_snd_rsp: result %d, err %d\n", + resp.resp.result, resp.resp.error); + + rc1 = qmi_send_response(qmi_handle, sq, txn, + QMI_IPA_WLAN_OPT_DATAPATH_RSRV_FILTER_RESP_V01, + IPA_WLAN_OPT_DP_RSRV_FILTER_RESP_MSG_V01_MAX_MSG_LEN, + ipa_wlan_opt_dp_rsrv_filter_resp_msg_data_v01_ei, + &resp); + + if (rc1 < 0) + IPAWANERR("Reserve filter rules response failed\n"); + else + IPAWANDBG("Replied to install filter request\n"); + + /* If rsrv filter request, fails, send indication immediately. */ + if (rc < 0) { + ind.rsrv_filter_status = resp.resp; + ipa3_qmi_send_wdi_opt_dpath_rsrv_flt_ind(&ind); + } +} + +static void ipa3_handle_ipa_wlan_opt_dp_remove_all_filter_req(struct qmi_handle *qmi_handle, + struct sockaddr_qrtr *sq, + struct qmi_txn *txn, + const void *decoded_msg) +{ + struct ipa_wlan_opt_dp_remove_all_filter_resp_msg_v01 resp; + struct ipa_wlan_opt_dp_remove_all_filter_complt_ind_msg_v01 ind; + int rc = 0, rc1 = 0; + + memset(&resp, 0, sizeof(resp)); + memset(&ind, 0, sizeof(ind)); + + IPAWANDBG("remove_all_filter_req:\n"); + + rc = ipa_wdi_opt_dpath_remove_all_filter_req( + (struct ipa_wlan_opt_dp_remove_all_filter_req_msg_v01 *)decoded_msg, &resp); + + IPAWANDBG("qmi_snd_rsp: result %d, err %d\n", + resp.resp.result, resp.resp.error); + + rc1 = qmi_send_response(qmi_handle, sq, txn, + QMI_IPA_WLAN_OPT_DATAPATH_REMOVE_ALL_FILTER_RESP_V01, + IPA_WLAN_OPT_DP_REMOVE_ALL_FILTER_RESP_MSG_V01_MAX_MSG_LEN, + ipa_wlan_opt_dp_remove_all_filter_resp_msg_data_v01_ei, + &resp); + + if (rc1 < 0) + IPAWANERR("Remove all filter rules failed\n"); + else + IPAWANDBG("Replied to remove all filter request\n"); + + /* If remove filter request fails, send indication immediately. */ + if (rc < 0) { + ind.filter_removal_all_status = resp.resp; + ipa3_qmi_send_wdi_opt_dpath_rmv_all_flt_ind(&ind); + } + +} + +static void ipa3_handle_ipa_wlan_opt_dp_add_filter_req(struct qmi_handle *qmi_handle, + struct sockaddr_qrtr *sq, + struct qmi_txn *txn, + const void *decoded_msg) +{ + struct ipa_wlan_opt_dp_add_filter_resp_msg_v01 resp; + struct ipa_wlan_opt_dp_add_filter_complt_ind_msg_v01 ind; + struct ipa_wlan_opt_dp_add_filter_req_msg_v01 *req = + (struct ipa_wlan_opt_dp_add_filter_req_msg_v01 *)decoded_msg; + int rc = 0 ; + + memset(&resp, 0, sizeof(resp)); + memset(&ind, 0, sizeof(ind)); + + /* cache the client sq */ + memcpy(&ipa3_qmi_ctx->client_sq, sq, sizeof(*sq)); + + rc = qmi_send_response(qmi_handle, sq, txn, + QMI_IPA_WLAN_OPT_DATAPATH_ADD_FILTER_RESP_V01, + IPA_WLAN_OPT_DP_ADD_FILTER_RESP_MSG_V01_MAX_MSG_LEN, + ipa_wlan_opt_dp_add_filter_resp_msg_data_v01_ei, + &resp); + + IPAWANDBG("add_filter_req: filter_idx %d, iptype %d\n", + req->filter_idx, req->ip_type); + + rc = ipa_wdi_opt_dpath_add_filter_req( + req,&ind); + + IPAWANDBG("qmi_snd_rsp: flt_idx %d, flt_hdl%d\n", + ind.filter_idx, ind.filter_handle); + + IPAWANDBG("qmi_snd_rsp: result %d, err %d\n", + ind.filter_add_status.result, ind.filter_add_status.error); + + rc = qmi_send_indication(qmi_handle, + &ipa3_qmi_ctx->client_sq, + QMI_IPA_WLAN_OPT_DATAPATH_ADD_FILTER_COMPLT_IND_V01, + IPA_WLAN_OPT_DP_ADD_FILTER_COMPLT_IND_MSG_V01_MAX_MSG_LEN, + ipa_wlan_opt_dp_add_filter_complt_ind_msg_v01_ei, + &ind); + + if (rc < 0) + IPAWANERR("Add filter rules failed\n"); + else + IPAWANDBG("Replied to add filter request\n"); +} + +static void ipa3_handle_ipa_wlan_opt_dp_remove_filter_req(struct qmi_handle *qmi_handle, + struct sockaddr_qrtr *sq, + struct qmi_txn *txn, + const void *decoded_msg) +{ + struct ipa_wlan_opt_dp_remove_filter_resp_msg_v01 resp; + struct ipa_wlan_opt_dp_remove_filter_complt_ind_msg_v01 ind; + struct ipa_wlan_opt_dp_remove_filter_req_msg_v01 *req = + (struct ipa_wlan_opt_dp_remove_filter_req_msg_v01 *)decoded_msg; + int rc = 0 ; + + memset(&resp, 0, sizeof(resp)); + memset(&ind, 0, sizeof(ind)); + + /* cache the client sq */ + memcpy(&ipa3_qmi_ctx->client_sq, sq, sizeof(*sq)); + + IPAWANDBG("remove_filter_req: filter_idx %d, filter_hdl %d\n", + req->filter_idx, req->filter_handle); + + rc = qmi_send_response(qmi_handle, sq, txn, + QMI_IPA_WLAN_OPT_DATAPATH_REMOVE_FILTER_RESP_V01, + IPA_WLAN_OPT_DP_REMOVE_FILTER_RESP_MSG_V01_MAX_MSG_LEN, + ipa_wlan_opt_dp_remove_filter_resp_msg_data_v01_ei, + &resp); + + rc = ipa_wdi_opt_dpath_remove_filter_req( + req,&ind); + + IPAWANDBG("qmi_snd_rsp: result %d, err %d\n", + ind.filter_removal_status.result, ind.filter_removal_status.error); + + + rc = qmi_send_indication(qmi_handle, + &ipa3_qmi_ctx->client_sq, + QMI_IPA_WLAN_OPT_DATAPATH_REMOVE_FILTER_COMPLT_IND_V01, + IPA_WLAN_OPT_DP_REM_FILTER_COMPLT_IND_MSG_V01_MAX_MSG_LEN, + ipa_wlan_opt_dp_remove_filter_complt_ind_msg_data_v01_ei, + &ind); + + if (rc < 0) + IPAWANERR("Remove filter rules failed\n"); + else + IPAWANDBG("Replied to remove filter request\n"); +} + +static void ipa3_q6_clnt_svc_arrive(struct work_struct *work) +{ + int rc; + struct ipa_master_driver_init_complt_ind_msg_v01 ind; + + if (unlikely(!ipa_q6_clnt)) { + IPAWANERR("Invalid q6 clnt.Ignore sending ind.\n"); + return; + } + + rc = kernel_connect(ipa_q6_clnt->sock, + (struct sockaddr *) &ipa3_qmi_ctx->server_sq, + sizeof(ipa3_qmi_ctx->server_sq), + 0); + + if (rc < 0) { + IPAWANERR("Couldnt connect Server\n"); + return; + } + + if (!send_qmi_init_q6) + return; + + IPAWANDBG("Q6 QMI service available now\n"); + if (ipa3_is_apq()) { + ipa3_qmi_modem_init_fin = true; + IPAWANDBG("QMI-client complete, ipa3_qmi_modem_init_fin : %d\n", + ipa3_qmi_modem_init_fin); + return; + } + + /* Initialize modem IPA-driver */ + IPAWANDBG("send ipa3_qmi_init_modem_send_sync_msg to modem\n"); + rc = ipa3_qmi_init_modem_send_sync_msg(); + if ((rc == -ENETRESET) || (rc == -ENODEV) || (rc == -ECONNRESET) || + atomic_read(&ipa3_ctx->is_ssr)) { + IPAWANERR( + "ipa3_qmi_init_modem_send_sync_msg failed due to SSR!\n"); + /* Cleanup when ipa3_wwan_remove is called */ + mutex_lock(&ipa3_qmi_lock); + if (ipa_q6_clnt != NULL) { + qmi_handle_release(ipa_q6_clnt); + vfree(ipa_q6_clnt); + ipa_q6_clnt = NULL; + } + mutex_unlock(&ipa3_qmi_lock); + IPAWANERR("Exit from service arrive fun\n"); + return; + } + + if (rc != 0) { + IPAWANERR("ipa3_qmi_init_modem_send_sync_msg failed\n"); + /* + * Hardware not responding. + * This is a very unexpected scenario + * which requires a kernel panic in + * order to force dumps for QMI/Q6 side analysis. + */ + BUG(); + } + ipa3_qmi_modem_init_fin = true; + + /* got modem_init_cmplt_req already, load uc-related register */ + if (ipa3_ctx->apply_rg10_wa && ipa3_modem_init_cmplt == true) { + IPAWANDBG("load uc related registers (%d)\n", + ipa3_modem_init_cmplt); + ipa3_uc_load_notify(); + } + + /* In cold-bootup, first_time_handshake = false */ + ipa3_q6_handshake_complete(first_time_handshake); + first_time_handshake = true; + IPAWANDBG("complete, ipa3_qmi_modem_init_fin : %d\n", + ipa3_qmi_modem_init_fin); + + if (ipa3_qmi_indication_fin) { + IPAWANDBG("send indication to modem (%d)\n", + ipa3_qmi_indication_fin); + memset(&ind, 0, sizeof(struct + ipa_master_driver_init_complt_ind_msg_v01)); + ind.master_driver_init_status.result = + IPA_QMI_RESULT_SUCCESS_V01; + + if (unlikely(!ipa3_svc_handle)) { + IPAWANERR("Invalid svc handle.Ignore sending ind.\n"); + return; + } + + rc = qmi_send_indication(ipa3_svc_handle, + &ipa3_qmi_ctx->client_sq, + QMI_IPA_MASTER_DRIVER_INIT_COMPLETE_IND_V01, + QMI_IPA_MASTER_DRIVER_INIT_COMPLETE_IND_MAX_MSG_LEN_V01, + ipa3_master_driver_init_complt_ind_msg_data_v01_ei, + &ind); + + IPAWANDBG("ipa_qmi_service_client good\n"); + } else { + IPAWANERR("not send indication (%d)\n", + ipa3_qmi_indication_fin); + } + + send_qmi_init_q6 = false; + +} + +static void ipa3_q6_clnt_svc_exit(struct work_struct *work) +{ + if (ipa3_qmi_ctx != NULL) { + ipa3_qmi_ctx->server_sq.sq_family = 0; + ipa3_qmi_ctx->server_sq.sq_node = 0; + ipa3_qmi_ctx->server_sq.sq_port = 0; + } +} + +static int ipa3_q6_clnt_svc_event_notify_svc_new(struct qmi_handle *qmi, + struct qmi_service *service) +{ + IPAWANDBG("QMI svc:%d vers:%d ins:%d node:%d port:%d\n", + service->service, service->version, service->instance, + service->node, service->port); + + if (ipa3_qmi_ctx != NULL) { + ipa3_qmi_ctx->server_sq.sq_family = AF_QIPCRTR; + ipa3_qmi_ctx->server_sq.sq_node = service->node; + ipa3_qmi_ctx->server_sq.sq_port = service->port; + } + if (!workqueues_stopped) { + queue_delayed_work(ipa_clnt_req_workqueue, + &ipa3_work_svc_arrive, 0); + } + return 0; +} + +static void ipa3_q6_clnt_svc_event_notify_net_reset(struct qmi_handle *qmi) +{ + if (!workqueues_stopped) + queue_delayed_work(ipa_clnt_req_workqueue, + &ipa3_work_svc_exit, 0); +} + +static void ipa3_q6_clnt_svc_event_notify_svc_exit(struct qmi_handle *qmi, + struct qmi_service *svc) +{ + IPAWANDBG("QMI svc:%d vers:%d ins:%d node:%d port:%d\n", svc->service, + svc->version, svc->instance, svc->node, svc->port); + + if (!workqueues_stopped) + queue_delayed_work(ipa_clnt_req_workqueue, + &ipa3_work_svc_exit, 0); +} + +static struct qmi_ops server_ops = { + .del_client = ipa3_a5_svc_disconnect_cb, +}; + +static struct qmi_ops client_ops = { + .new_server = ipa3_q6_clnt_svc_event_notify_svc_new, + .del_server = ipa3_q6_clnt_svc_event_notify_svc_exit, + .net_reset = ipa3_q6_clnt_svc_event_notify_net_reset, +}; + +static struct qmi_msg_handler server_handlers[] = { + { + .type = QMI_REQUEST, + .msg_id = QMI_IPA_INDICATION_REGISTER_REQ_V01, + .ei = ipa3_indication_reg_req_msg_data_v01_ei, + .decoded_size = sizeof(struct ipa_indication_reg_req_msg_v01), + .fn = ipa3_handle_indication_req, + }, + { + .type = QMI_REQUEST, + .msg_id = QMI_IPA_INSTALL_FILTER_RULE_REQ_V01, + .ei = ipa3_install_fltr_rule_req_msg_data_v01_ei, + .decoded_size = sizeof( + struct ipa_install_fltr_rule_req_msg_v01), + .fn = ipa3_handle_install_filter_rule_req, + }, + { + .type = QMI_REQUEST, + .msg_id = QMI_IPA_FILTER_INSTALLED_NOTIF_REQ_V01, + .ei = ipa3_fltr_installed_notif_req_msg_data_v01_ei, + .decoded_size = sizeof( + struct ipa_fltr_installed_notif_req_msg_v01), + .fn = ipa3_handle_filter_installed_notify_req, + }, + { + .type = QMI_REQUEST, + .msg_id = QMI_IPA_CONFIG_REQ_V01, + .ei = ipa3_config_req_msg_data_v01_ei, + .decoded_size = sizeof(struct ipa_config_req_msg_v01), + .fn = handle_ipa_config_req, + }, + { + .type = QMI_REQUEST, + .msg_id = QMI_IPA_INIT_MODEM_DRIVER_CMPLT_REQ_V01, + .ei = ipa3_init_modem_driver_cmplt_req_msg_data_v01_ei, + .decoded_size = sizeof( + struct ipa_init_modem_driver_cmplt_req_msg_v01), + .fn = ipa3_handle_modem_init_cmplt_req, + }, + { + .type = QMI_REQUEST, + .msg_id = QMI_IPA_INIT_MODEM_DRIVER_CMPLT_REQ_V01, + .ei = ipa3_init_modem_driver_cmplt_req_msg_data_v01_ei, + .decoded_size = sizeof( + struct ipa_init_modem_driver_cmplt_req_msg_v01), + .fn = ipa3_handle_modem_init_cmplt_req, + }, + { + .type = QMI_REQUEST, + .msg_id = QMI_IPA_MHI_ALLOC_CHANNEL_REQ_V01, + .ei = ipa_mhi_alloc_channel_req_msg_v01_ei, + .decoded_size = sizeof( + struct ipa_mhi_alloc_channel_req_msg_v01), + .fn = ipa3_handle_mhi_alloc_channel_req, + }, + { + .type = QMI_REQUEST, + .msg_id = QMI_IPA_MHI_CLK_VOTE_REQ_V01, + .ei = ipa_mhi_clk_vote_req_msg_v01_ei, + .decoded_size = sizeof(struct ipa_mhi_clk_vote_req_msg_v01), + .fn = ipa3_handle_mhi_vote_req, + }, + { + .type = QMI_REQUEST, + .msg_id = QMI_IPA_MOVE_NAT_REQ_V01, + .ei = ipa_move_nat_req_msg_v01_ei, + .decoded_size = sizeof(struct ipa_move_nat_req_msg_v01), + .fn = ipa3_handle_move_nat_req, + }, + { + .type = QMI_REQUEST, + .msg_id = QMI_IPA_WLAN_OPT_DATAPATH_RSRV_FILTER_REQ_V01, + .ei = ipa_wlan_opt_dp_rsrv_filter_req_msg_data_v01_ei, + .decoded_size = sizeof(struct ipa_wlan_opt_dp_rsrv_filter_req_msg_v01), + .fn = ipa3_handle_ipa_wlan_opt_dp_rsrv_filter_req, + }, + { + .type = QMI_REQUEST, + .msg_id = QMI_IPA_WLAN_OPT_DATAPATH_ADD_FILTER_REQ_V01, + .ei = ipa_wlan_opt_dp_add_filter_req_msg_data_v01_ei, + .decoded_size = sizeof(struct ipa_wlan_opt_dp_add_filter_req_msg_v01), + .fn = ipa3_handle_ipa_wlan_opt_dp_add_filter_req, + }, + { + .type = QMI_REQUEST, + .msg_id = QMI_IPA_WLAN_OPT_DATAPATH_REMOVE_FILTER_REQ_V01, + .ei = ipa_wlan_opt_dp_remove_filter_req_msg_data_v01_ei, + .decoded_size = sizeof(struct ipa_wlan_opt_dp_remove_filter_req_msg_v01), + .fn = ipa3_handle_ipa_wlan_opt_dp_remove_filter_req, + }, + { + .type = QMI_REQUEST, + .msg_id = QMI_IPA_WLAN_OPT_DATAPATH_REMOVE_ALL_FILTER_REQ_V01, + .ei = ipa_wlan_opt_dp_remove_all_filter_req_msg_data_v01_ei, + .decoded_size = sizeof(struct ipa_wlan_opt_dp_remove_all_filter_req_msg_v01), + .fn = ipa3_handle_ipa_wlan_opt_dp_remove_all_filter_req, + }, + {}, + +}; + +/* clinet_handlers are client callbacks that will be called from QMI context + * when an indication from Q6 server arrives. + * In our case, client_handlers needs handling only for QMI_INDICATION, + * since the QMI_REQUEST/ QMI_RESPONSE are handled in a blocking fashion + * at the time of sending QMI_REQUESTs. + */ +static struct qmi_msg_handler client_handlers[] = { + { + .type = QMI_INDICATION, + .msg_id = QMI_IPA_DATA_USAGE_QUOTA_REACHED_IND_V01, + .ei = ipa3_data_usage_quota_reached_ind_msg_data_v01_ei, + .decoded_size = sizeof( + struct ipa_data_usage_quota_reached_ind_msg_v01), + .fn = ipa3_q6_clnt_quota_reached_ind_cb, + }, + { + .type = QMI_INDICATION, + .msg_id = QMI_IPA_INSTALL_UL_FIREWALL_RULES_IND_V01, + .ei = ipa3_install_fltr_rule_req_msg_data_v01_ei, + .decoded_size = sizeof( + struct ipa_configure_ul_firewall_rules_ind_msg_v01), + .fn = ipa3_q6_clnt_install_firewall_rules_ind_cb, + }, + { + .type = QMI_INDICATION, + .msg_id = QMI_IPA_BW_CHANGE_INDICATION_V01, + .ei = ipa_bw_change_ind_msg_v01_ei, + .decoded_size = IPA_BW_CHANGE_IND_MSG_V01_MAX_MSG_LEN, + .fn = ipa3_q6_clnt_bw_change_ind_cb, + }, + {}, +}; + + +static void ipa3_qmi_service_init_worker(struct work_struct *work) +{ + int rc; + + /* start the QMI msg cache */ + ipa3_qmi_ctx = vzalloc(sizeof(*ipa3_qmi_ctx)); + if (!ipa3_qmi_ctx) { + IPAWANERR("Failed to allocate ipa3_qmi_ctx\n"); + return; + } + + if (ipa3_is_apq()) { + /* Only start QMI-client */ + IPAWANDBG("Only start IPA A7 QMI client\n"); + goto qmi_client_start; + } + + /* Initialize QMI-service*/ + IPAWANDBG("IPA A7 QMI init OK :>>>>\n"); + + ipa3_qmi_ctx->modem_cfg_emb_pipe_flt = + ipa3_get_modem_cfg_emb_pipe_flt(); + + ipa3_qmi_ctx->num_ipa_offload_connection = 0; + ipa3_svc_handle = vzalloc(sizeof(*ipa3_svc_handle)); + + if (!ipa3_svc_handle) + goto destroy_ipa_A7_svc_wq; + + rc = qmi_handle_init(ipa3_svc_handle, + QMI_IPA_MAX_MSG_LEN, + &server_ops, + server_handlers); + + if (rc < 0) { + IPAWANERR("Initializing ipa_a5 svc failed %d\n", rc); + goto destroy_qmi_handle; + } + + rc = qmi_add_server(ipa3_svc_handle, + IPA_A5_SERVICE_SVC_ID, + IPA_A5_SVC_VERS, + IPA_A5_SERVICE_INS_ID); + + if (rc < 0) { + IPAWANERR("Registering ipa_a5 svc failed %d\n", + rc); + goto deregister_qmi_srv; + } + +qmi_client_start: + /* Initialize QMI-client */ + ipa_clnt_req_workqueue = create_singlethread_workqueue("clnt_req"); + if (!ipa_clnt_req_workqueue) { + IPAWANERR("Creating clnt_req workqueue failed\n"); + goto deregister_qmi_srv; + } + + /* Create a Local client port for QMI communication */ + ipa_q6_clnt = vzalloc(sizeof(*ipa_q6_clnt)); + + if (!ipa_q6_clnt) + goto destroy_clnt_req_wq; + + rc = qmi_handle_init(ipa_q6_clnt, + QMI_IPA_MAX_MSG_LEN, + &client_ops, + client_handlers); + + if (rc < 0) { + IPAWANERR("Creating clnt handle failed\n"); + goto destroy_qmi_client_handle; + } + + rc = qmi_add_lookup(ipa_q6_clnt, + IPA_Q6_SERVICE_SVC_ID, + IPA_Q6_SVC_VERS, + IPA_Q6_SERVICE_INS_ID); + + if (rc < 0) { + IPAWANERR("Adding Q6 Svc failed\n"); + goto deregister_qmi_client; + } + + /* get Q6 service and start send modem-initial to Q6 */ + IPAWANDBG("wait service available\n"); + return; + +deregister_qmi_client: + qmi_handle_release(ipa_q6_clnt); +destroy_qmi_client_handle: + vfree(ipa_q6_clnt); + ipa_q6_clnt = NULL; +destroy_clnt_req_wq: + destroy_workqueue(ipa_clnt_req_workqueue); + ipa_clnt_req_workqueue = NULL; +deregister_qmi_srv: + if (!ipa3_is_apq()) + qmi_handle_release(ipa3_svc_handle); +destroy_qmi_handle: + vfree(ipa3_qmi_ctx); +destroy_ipa_A7_svc_wq: + if (!ipa3_is_apq()) { + vfree(ipa3_svc_handle); + ipa3_svc_handle = NULL; + } + ipa3_qmi_ctx = NULL; +} + +int ipa3_qmi_service_init(uint32_t wan_platform_type) +{ + ipa_wan_platform = wan_platform_type; + ipa3_qmi_modem_init_fin = false; + ipa3_qmi_indication_fin = false; + ipa3_modem_init_cmplt = false; + send_qmi_init_q6 = true; + workqueues_stopped = false; + + if (!ipa3_svc_handle) { + INIT_WORK(&ipa3_qmi_service_init_work, + ipa3_qmi_service_init_worker); + schedule_work(&ipa3_qmi_service_init_work); + } + return 0; +} + +void ipa3_qmi_service_exit(void) +{ + + workqueues_stopped = true; + + IPADBG("Entry\n"); + /* qmi-service */ + if (ipa3_svc_handle != NULL) { + qmi_handle_release(ipa3_svc_handle); + vfree(ipa3_svc_handle); + ipa3_svc_handle = NULL; + } + + /* Release client handle */ + mutex_lock(&ipa3_qmi_lock); + if (ipa_q6_clnt != NULL) { + qmi_handle_release(ipa_q6_clnt); + vfree(ipa_q6_clnt); + ipa_q6_clnt = NULL; + mutex_unlock(&ipa3_qmi_lock); + if (ipa_clnt_req_workqueue) { + destroy_workqueue(ipa_clnt_req_workqueue); + ipa_clnt_req_workqueue = NULL; + } + mutex_lock(&ipa3_qmi_lock); + } + + /* clean the QMI msg cache */ + if (ipa3_qmi_ctx != NULL) { + vfree(ipa3_qmi_ctx); + ipa3_qmi_ctx = NULL; + } + mutex_unlock(&ipa3_qmi_lock); + + ipa3_qmi_modem_init_fin = false; + ipa3_qmi_indication_fin = false; + ipa3_modem_init_cmplt = false; + send_qmi_init_q6 = true; + IPADBG("Exit\n"); +} + +void ipa3_qmi_stop_workqueues(void) +{ + IPAWANDBG("Stopping all QMI workqueues\n"); + + /* Stopping all workqueues so new work won't be scheduled */ + workqueues_stopped = true; + + /* Making sure that the current scheduled work won't be executed */ + cancel_delayed_work(&ipa3_work_svc_arrive); + cancel_delayed_work(&ipa3_work_svc_exit); +} + +/* voting for bus BW to ipa_rm*/ +int ipa3_vote_for_bus_bw(uint32_t *bw_mbps) +{ + int ret; + + IPAWANDBG("Bus BW is %d\n", *bw_mbps); + + if (bw_mbps == NULL) { + IPAWANERR("Bus BW is invalid\n"); + return -EINVAL; + } + + ret = ipa3_wwan_set_modem_perf_profile(*bw_mbps); + if (ret) + IPAWANERR("Failed to set perf profile to BW %u\n", + *bw_mbps); + else + IPAWANDBG("Succeeded to set perf profile to BW %u\n", + *bw_mbps); + + return ret; +} + +int ipa3_qmi_get_data_stats(struct ipa_get_data_stats_req_msg_v01 *req, + struct ipa_get_data_stats_resp_msg_v01 *resp) +{ + struct ipa_msg_desc req_desc, resp_desc; + int rc; + + req_desc.max_msg_len = QMI_IPA_GET_DATA_STATS_REQ_MAX_MSG_LEN_V01; + req_desc.msg_id = QMI_IPA_GET_DATA_STATS_REQ_V01; + req_desc.ei_array = ipa3_get_data_stats_req_msg_data_v01_ei; + + resp_desc.max_msg_len = QMI_IPA_GET_DATA_STATS_RESP_MAX_MSG_LEN_V01; + resp_desc.msg_id = QMI_IPA_GET_DATA_STATS_RESP_V01; + resp_desc.ei_array = ipa3_get_data_stats_resp_msg_data_v01_ei; + + IPAWANDBG_LOW("Sending QMI_IPA_GET_DATA_STATS_REQ_V01\n"); + + if (unlikely(!ipa_q6_clnt)) + return -ETIMEDOUT; + rc = ipa3_qmi_send_req_wait(ipa_q6_clnt, + &req_desc, req, + &resp_desc, resp, + QMI_SEND_STATS_REQ_TIMEOUT_MS); + + if (rc < 0) { + IPAWANERR("QMI send Req %d failed, rc= %d\n", + QMI_IPA_GET_DATA_STATS_REQ_V01, + rc); + return rc; + } + + IPAWANDBG_LOW("QMI_IPA_GET_DATA_STATS_RESP_V01 received\n"); + + return ipa3_check_qmi_response(rc, + QMI_IPA_GET_DATA_STATS_REQ_V01, resp->resp.result, + resp->resp.error, "ipa_get_data_stats_resp_msg_v01"); +} + +int ipa3_qmi_get_network_stats(struct ipa_get_apn_data_stats_req_msg_v01 *req, + struct ipa_get_apn_data_stats_resp_msg_v01 *resp) +{ + struct ipa_msg_desc req_desc, resp_desc; + int rc; + + req_desc.max_msg_len = QMI_IPA_GET_APN_DATA_STATS_REQ_MAX_MSG_LEN_V01; + req_desc.msg_id = QMI_IPA_GET_APN_DATA_STATS_REQ_V01; + req_desc.ei_array = ipa3_get_apn_data_stats_req_msg_data_v01_ei; + + resp_desc.max_msg_len = QMI_IPA_GET_APN_DATA_STATS_RESP_MAX_MSG_LEN_V01; + resp_desc.msg_id = QMI_IPA_GET_APN_DATA_STATS_RESP_V01; + resp_desc.ei_array = ipa3_get_apn_data_stats_resp_msg_data_v01_ei; + + IPAWANDBG_LOW("Sending QMI_IPA_GET_APN_DATA_STATS_REQ_V01\n"); + + if (unlikely(!ipa_q6_clnt)) + return -ETIMEDOUT; + rc = ipa3_qmi_send_req_wait(ipa_q6_clnt, + &req_desc, req, + &resp_desc, resp, + QMI_SEND_STATS_REQ_TIMEOUT_MS); + + if (rc < 0) { + IPAWANERR("QMI send Req %d failed, rc= %d\n", + QMI_IPA_GET_APN_DATA_STATS_REQ_V01, + rc); + return rc; + } + + IPAWANDBG_LOW("QMI_IPA_GET_APN_DATA_STATS_RESP_V01 received\n"); + + return ipa3_check_qmi_response(rc, + QMI_IPA_GET_APN_DATA_STATS_REQ_V01, resp->resp.result, + resp->resp.error, "ipa_get_apn_data_stats_req_msg_v01"); +} + +int ipa3_qmi_set_data_quota(struct ipa_set_data_usage_quota_req_msg_v01 *req) +{ + struct ipa_set_data_usage_quota_resp_msg_v01 resp; + struct ipa_msg_desc req_desc, resp_desc; + int rc; + + memset(&resp, 0, sizeof(struct ipa_set_data_usage_quota_resp_msg_v01)); + + req_desc.max_msg_len = QMI_IPA_SET_DATA_USAGE_QUOTA_REQ_MAX_MSG_LEN_V01; + req_desc.msg_id = QMI_IPA_SET_DATA_USAGE_QUOTA_REQ_V01; + req_desc.ei_array = ipa3_set_data_usage_quota_req_msg_data_v01_ei; + + resp_desc.max_msg_len = + QMI_IPA_SET_DATA_USAGE_QUOTA_RESP_MAX_MSG_LEN_V01; + resp_desc.msg_id = QMI_IPA_SET_DATA_USAGE_QUOTA_RESP_V01; + resp_desc.ei_array = ipa3_set_data_usage_quota_resp_msg_data_v01_ei; + + IPAWANDBG_LOW("Sending QMI_IPA_SET_DATA_USAGE_QUOTA_REQ_V01\n"); + if (unlikely(!ipa_q6_clnt)) + return -ETIMEDOUT; + rc = ipa3_qmi_send_req_wait(ipa_q6_clnt, + &req_desc, req, + &resp_desc, &resp, + QMI_SEND_STATS_REQ_TIMEOUT_MS); + + if (rc < 0) { + IPAWANERR("QMI send Req %d failed, rc= %d\n", + QMI_IPA_SET_DATA_USAGE_QUOTA_REQ_V01, + rc); + return rc; + } + + IPAWANDBG_LOW("QMI_IPA_SET_DATA_USAGE_QUOTA_RESP_V01 received\n"); + + return ipa3_check_qmi_response(rc, + QMI_IPA_SET_DATA_USAGE_QUOTA_REQ_V01, resp.resp.result, + resp.resp.error, "ipa_set_data_usage_quota_req_msg_v01"); +} + +int ipa3_qmi_set_aggr_info(enum ipa_aggr_enum_type_v01 aggr_enum_type) +{ + struct ipa_mhi_prime_aggr_info_resp_msg_v01 resp; + struct ipa_msg_desc req_desc, resp_desc; + int rc; + + IPAWANDBG("sending aggr_info_request\n"); + + /* replace to right qmap format */ + aggr_req.aggr_info[1].aggr_type = aggr_enum_type; + aggr_req.aggr_info[1].bytes_count = ipa3_ctx->mpm_teth_aggr_size; + aggr_req.aggr_info[2].aggr_type = aggr_enum_type; + aggr_req.aggr_info[3].aggr_type = aggr_enum_type; + aggr_req.aggr_info[4].aggr_type = aggr_enum_type; + + memset(&resp, 0, sizeof(struct ipa_mhi_prime_aggr_info_resp_msg_v01)); + + req_desc.max_msg_len = IPA_MHI_PRIME_AGGR_INFO_REQ_MSG_V01_MAX_MSG_LEN; + req_desc.msg_id = QMI_IPA_MHI_PRIME_AGGR_INFO_REQ_V01; + req_desc.ei_array = ipa_mhi_prime_aggr_info_req_msg_v01_ei; + + resp_desc.max_msg_len = + IPA_MHI_PRIME_AGGR_INFO_RESP_MSG_V01_MAX_MSG_LEN; + resp_desc.msg_id = QMI_IPA_MHI_PRIME_AGGR_INFO_RESP_V01; + resp_desc.ei_array = ipa_mhi_prime_aggr_info_resp_msg_v01_ei; + + IPAWANDBG("Sending QMI_IPA_MHI_PRIME_AGGR_INFO_REQ_V01(%d)\n", + aggr_enum_type); + if (unlikely(!ipa_q6_clnt)) { + IPAWANERR(" ipa_q6_clnt not initialized\n"); + return -ETIMEDOUT; + } + rc = ipa3_qmi_send_req_wait(ipa_q6_clnt, + &req_desc, &aggr_req, + &resp_desc, &resp, + QMI_SEND_STATS_REQ_TIMEOUT_MS); + + if (rc < 0) { + IPAWANERR("QMI send Req %d failed, rc= %d\n", + QMI_IPA_SET_DATA_USAGE_QUOTA_REQ_V01, + rc); + return rc; + } + + IPAWANDBG_LOW("QMI_IPA_MHI_PRIME_AGGR_INFO_RESP_V01 received\n"); + + return ipa3_check_qmi_response(rc, + QMI_IPA_SET_DATA_USAGE_QUOTA_REQ_V01, resp.resp.result, + resp.resp.error, "ipa_mhi_prime_aggr_info_req_msg_v01"); +} + +int ipa3_qmi_req_ind(bool bw_reg) +{ + struct ipa_indication_reg_req_msg_v01 req; + struct ipa_indication_reg_resp_msg_v01 resp; + struct ipa_msg_desc req_desc, resp_desc; + int rc; + + memset(&req, 0, sizeof(struct ipa_indication_reg_req_msg_v01)); + memset(&resp, 0, sizeof(struct ipa_indication_reg_resp_msg_v01)); + + req.bw_change_ind_valid = true; + req.bw_change_ind = bw_reg; + + req_desc.max_msg_len = + QMI_IPA_INDICATION_REGISTER_REQ_MAX_MSG_LEN_V01; + req_desc.msg_id = QMI_IPA_INDICATION_REGISTER_REQ_V01; + req_desc.ei_array = ipa3_indication_reg_req_msg_data_v01_ei; + + resp_desc.max_msg_len = + QMI_IPA_INDICATION_REGISTER_RESP_MAX_MSG_LEN_V01; + resp_desc.msg_id = QMI_IPA_INDICATION_REGISTER_RESP_V01; + resp_desc.ei_array = ipa3_indication_reg_resp_msg_data_v01_ei; + + IPAWANDBG_LOW("Sending QMI_IPA_INDICATION_REGISTER_REQ_V01\n"); + if (unlikely(!ipa_q6_clnt)) + return -ETIMEDOUT; + rc = ipa3_qmi_send_req_wait(ipa_q6_clnt, + &req_desc, &req, + &resp_desc, &resp, + QMI_SEND_STATS_REQ_TIMEOUT_MS); + + if (rc < 0) { + IPAWANERR("QMI send Req %d failed, rc= %d\n", + QMI_IPA_INDICATION_REGISTER_REQ_V01, + rc); + return rc; + } + + IPAWANDBG_LOW("QMI_IPA_INDICATION_REGISTER_RESP_V01 received\n"); + + return ipa3_check_qmi_response(rc, + QMI_IPA_INDICATION_REGISTER_REQ_V01, resp.resp.result, + resp.resp.error, "ipa_indication_reg_req_msg_v01"); +} + +int ipa3_qmi_stop_data_quota(struct ipa_stop_data_usage_quota_req_msg_v01 *req) +{ + struct ipa_stop_data_usage_quota_resp_msg_v01 resp; + struct ipa_msg_desc req_desc, resp_desc; + int rc; + + memset(&resp, 0, sizeof(struct ipa_stop_data_usage_quota_resp_msg_v01)); + + req_desc.max_msg_len = + QMI_IPA_STOP_DATA_USAGE_QUOTA_REQ_MAX_MSG_LEN_V01; + req_desc.msg_id = QMI_IPA_STOP_DATA_USAGE_QUOTA_REQ_V01; + req_desc.ei_array = ipa3_stop_data_usage_quota_req_msg_data_v01_ei; + + resp_desc.max_msg_len = + QMI_IPA_STOP_DATA_USAGE_QUOTA_RESP_MAX_MSG_LEN_V01; + resp_desc.msg_id = QMI_IPA_STOP_DATA_USAGE_QUOTA_RESP_V01; + resp_desc.ei_array = ipa3_stop_data_usage_quota_resp_msg_data_v01_ei; + + IPAWANDBG_LOW("Sending QMI_IPA_STOP_DATA_USAGE_QUOTA_REQ_V01\n"); + if (unlikely(!ipa_q6_clnt)) + return -ETIMEDOUT; + rc = ipa3_qmi_send_req_wait(ipa_q6_clnt, + &req_desc, req, + &resp_desc, &resp, + QMI_SEND_STATS_REQ_TIMEOUT_MS); + + if (rc < 0) { + IPAWANERR("QMI send Req %d failed, rc= %d\n", + QMI_IPA_STOP_DATA_USAGE_QUOTA_REQ_V01, + rc); + return rc; + } + + IPAWANDBG_LOW("QMI_IPA_STOP_DATA_USAGE_QUOTA_RESP_V01 received\n"); + + return ipa3_check_qmi_response(rc, + QMI_IPA_STOP_DATA_USAGE_QUOTA_REQ_V01, resp.resp.result, + resp.resp.error, "ipa_stop_data_usage_quota_req_msg_v01"); +} + +int ipa3_qmi_enable_per_client_stats( + struct ipa_enable_per_client_stats_req_msg_v01 *req, + struct ipa_enable_per_client_stats_resp_msg_v01 *resp) +{ + struct ipa_msg_desc req_desc, resp_desc; + int rc = 0; + + req_desc.max_msg_len = + QMI_IPA_ENABLE_PER_CLIENT_STATS_REQ_MAX_MSG_LEN_V01; + req_desc.msg_id = + QMI_IPA_ENABLE_PER_CLIENT_STATS_REQ_V01; + req_desc.ei_array = + ipa3_enable_per_client_stats_req_msg_data_v01_ei; + + resp_desc.max_msg_len = + QMI_IPA_ENABLE_PER_CLIENT_STATS_RESP_MAX_MSG_LEN_V01; + resp_desc.msg_id = + QMI_IPA_ENABLE_PER_CLIENT_STATS_RESP_V01; + resp_desc.ei_array = + ipa3_enable_per_client_stats_resp_msg_data_v01_ei; + + IPAWANDBG("Sending QMI_IPA_ENABLE_PER_CLIENT_STATS_REQ_V01\n"); + + if (unlikely(!ipa_q6_clnt)) + return -ETIMEDOUT; + rc = ipa3_qmi_send_req_wait(ipa_q6_clnt, + &req_desc, req, + &resp_desc, resp, + QMI_SEND_STATS_REQ_TIMEOUT_MS); + + if (rc < 0) { + IPAWANERR("send Req %d failed, rc= %d\n", + QMI_IPA_ENABLE_PER_CLIENT_STATS_REQ_V01, + rc); + return rc; + } + + IPAWANDBG("QMI_IPA_ENABLE_PER_CLIENT_STATS_RESP_V01 received\n"); + + return ipa3_check_qmi_response(rc, + QMI_IPA_ENABLE_PER_CLIENT_STATS_REQ_V01, resp->resp.result, + resp->resp.error, "ipa3_qmi_enable_per_client_stats"); +} + +int ipa3_qmi_get_per_client_packet_stats( + struct ipa_get_stats_per_client_req_msg_v01 *req, + struct ipa_get_stats_per_client_resp_msg_v01 *resp) +{ + struct ipa_msg_desc req_desc, resp_desc; + int rc; + + req_desc.max_msg_len = QMI_IPA_GET_STATS_PER_CLIENT_REQ_MAX_MSG_LEN_V01; + req_desc.msg_id = QMI_IPA_GET_STATS_PER_CLIENT_REQ_V01; + req_desc.ei_array = ipa3_get_stats_per_client_req_msg_data_v01_ei; + + resp_desc.max_msg_len = + QMI_IPA_GET_STATS_PER_CLIENT_RESP_MAX_MSG_LEN_V01; + resp_desc.msg_id = QMI_IPA_GET_STATS_PER_CLIENT_RESP_V01; + resp_desc.ei_array = ipa3_get_stats_per_client_resp_msg_data_v01_ei; + + IPAWANDBG("Sending QMI_IPA_GET_STATS_PER_CLIENT_REQ_V01\n"); + + if (unlikely(!ipa_q6_clnt)) + return -ETIMEDOUT; + rc = ipa3_qmi_send_req_wait(ipa_q6_clnt, + &req_desc, req, + &resp_desc, resp, + QMI_SEND_STATS_REQ_TIMEOUT_MS); + + if (rc < 0) { + IPAWANERR("send Req %d failed, rc= %d\n", + QMI_IPA_GET_STATS_PER_CLIENT_REQ_V01, + rc); + return rc; + } + + IPAWANDBG("QMI_IPA_GET_STATS_PER_CLIENT_RESP_V01 received\n"); + + return ipa3_check_qmi_response(rc, + QMI_IPA_GET_STATS_PER_CLIENT_REQ_V01, resp->resp.result, + resp->resp.error, + "struct ipa_get_stats_per_client_req_msg_v01"); +} + +int ipa3_qmi_send_mhi_ready_indication( + struct ipa_mhi_ready_indication_msg_v01 *req) +{ + IPAWANDBG("Sending QMI_IPA_MHI_READY_IND_V01\n"); + + if (unlikely(!ipa3_svc_handle)) + return -ETIMEDOUT; + + return qmi_send_indication(ipa3_svc_handle, + &ipa3_qmi_ctx->client_sq, + QMI_IPA_MHI_READY_IND_V01, + IPA_MHI_READY_INDICATION_MSG_V01_MAX_MSG_LEN, + ipa_mhi_ready_indication_msg_v01_ei, + req); +} + +int ipa3_qmi_send_wdi_opt_dpath_rsrv_flt_ind( + struct ipa_wlan_opt_dp_rsrv_filter_complt_ind_msg_v01 *ind) +{ + IPAWANDBG("Sending QMI_IPA_WLAN_OPT_DATAPATH_RSRV_FILTER_COMPLT_IND_V01 \n"); + + if (unlikely(!ipa3_svc_handle)) + return -ETIMEDOUT; + + IPAWANDBG("wdi_opt_dpath_rsrv_flt_ind: result %d, err %d\n", + ind->rsrv_filter_status.result, + ind->rsrv_filter_status.error); + + return qmi_send_indication(ipa3_svc_handle, + &ipa3_qmi_ctx->client_sq, + QMI_IPA_WLAN_OPT_DATAPATH_RSRV_FILTER_COMPLT_IND_V01, + IPA_WLAN_OPT_DP_RSRV_FILTER_COMPLT_IND_MSG_V01_MAX_MSG_LEN, + ipa_wlan_opt_dp_rsrv_filter_complt_ind_msg_data_v01_ei, + ind); +} +EXPORT_SYMBOL(ipa3_qmi_send_wdi_opt_dpath_rsrv_flt_ind); + +int ipa3_qmi_send_wdi_opt_dpath_rmv_all_flt_ind( + struct ipa_wlan_opt_dp_remove_all_filter_complt_ind_msg_v01 *ind) +{ + IPAWANDBG("Sending QMI_IPA_WLAN_OPT_DATAPATH_REMOVE_ALL_FILTER_COMPLT_IND_V01\n"); + + if (unlikely(!ipa3_svc_handle)) + return -ETIMEDOUT; + + if (atomic_read(&ipa3_ctx->is_ssr)) { + IPAWANDBG("SSR in progress , no need to send ind\n"); + return 0; + } + + IPAWANDBG("wdi_opt_dpath_rmv_all_flt_ind: result %d, err %d\n", + ind->filter_removal_all_status.result, + ind->filter_removal_all_status.error); + + return qmi_send_indication(ipa3_svc_handle, + &ipa3_qmi_ctx->client_sq, + QMI_IPA_WLAN_OPT_DATAPATH_REMOVE_ALL_FILTER_COMPLT_IND_V01, + IPA_WLAN_OPT_DP_REM_ALL_FILTER_COMPLT_IND_MSG_V01_MAX_MSG_LEN, + ipa_wlan_opt_dp_remove_all_filter_complt_ind_msg_data_v01_ei, + ind); +} +EXPORT_SYMBOL(ipa3_qmi_send_wdi_opt_dpath_rmv_all_flt_ind); + + +int ipa3_qmi_send_wdi_opt_dpath_ep_info( + struct ipa_wlan_opt_dp_set_wlan_per_info_req_msg_v01 *req) +{ + struct ipa_msg_desc req_desc, resp_desc; + int rc; + struct ipa_wlan_opt_dp_set_wlan_per_info_resp_msg_v01 resp; + + memset(&resp, 0, sizeof(struct ipa_wlan_opt_dp_set_wlan_per_info_resp_msg_v01)); + + req_desc.max_msg_len = IPA_WLAN_OPT_DP_SET_WLAN_PER_INFO_REQ_MSG_V1_MAX_MSG_LEN; + req_desc.msg_id = QMI_IPA_WLAN_OPT_DATAPATH_SET_WLAN_PER_INFO_REQ_V01; + req_desc.ei_array = ipa_wlan_opt_dp_set_wlan_per_info_req_msg_data_v01_ei; + + resp_desc.max_msg_len = IPA_WLAN_OPT_DP_SET_WLAN_PER_INFO_RESP_MSG_V1_MAX_MSG_LEN; + resp_desc.msg_id = QMI_IPA_WLAN_OPT_DATAPATH_SET_WLAN_PER_INFO_RESP_V01; + resp_desc.ei_array = ipa_wlan_opt_dp_set_wlan_per_info_resp_msg_data_v01; + + IPAWANDBG("Sending QMI_IPA_WLAN_OPT_DATAPATH_SET_WLAN_PER_INFO_REQ_V01\n"); + + if (unlikely(!ipa_q6_clnt)) + return -ETIMEDOUT; + rc = ipa3_qmi_send_req_wait(ipa_q6_clnt, + &req_desc, req, + &resp_desc, &resp, + QMI_SEND_STATS_REQ_TIMEOUT_MS); + + if (rc < 0) { + IPAWANERR("QMI send Req %d failed, rc= %d\n", + QMI_IPA_GET_APN_DATA_STATS_REQ_V01, + rc); + return rc; + } + + IPAWANDBG("QMI_IPA_WLAN_OPT_DATAPATH_SET_WLAN_PER_INFO_RESP_V01 received\n"); + + return ipa3_check_qmi_response(rc, + QMI_IPA_WLAN_OPT_DATAPATH_SET_WLAN_PER_INFO_REQ_V01, resp.resp.result, + resp.resp.error, "ipa_wlan_opt_dp_set_wlan_per_info_req_msg_v01"); +} +EXPORT_SYMBOL(ipa3_qmi_send_wdi_opt_dpath_ep_info); + +int ipa3_qmi_send_mhi_cleanup_request(struct ipa_mhi_cleanup_req_msg_v01 *req) +{ + + struct ipa_msg_desc req_desc, resp_desc; + struct ipa_mhi_cleanup_resp_msg_v01 resp; + int rc; + + memset(&resp, 0, sizeof(resp)); + + IPAWANDBG("Sending QMI_IPA_MHI_CLEANUP_REQ_V01\n"); + if (unlikely(!ipa_q6_clnt)) + return -ETIMEDOUT; + + req_desc.max_msg_len = IPA_MHI_CLK_VOTE_REQ_MSG_V01_MAX_MSG_LEN; + req_desc.msg_id = QMI_IPA_MHI_CLEANUP_REQ_V01; + req_desc.ei_array = ipa_mhi_cleanup_req_msg_v01_ei; + + resp_desc.max_msg_len = IPA_MHI_CLK_VOTE_RESP_MSG_V01_MAX_MSG_LEN; + resp_desc.msg_id = QMI_IPA_MHI_CLEANUP_RESP_V01; + resp_desc.ei_array = ipa_mhi_cleanup_resp_msg_v01_ei; + + if (unlikely(!ipa_q6_clnt)) + return -ETIMEDOUT; + rc = ipa3_qmi_send_req_wait(ipa_q6_clnt, + &req_desc, req, + &resp_desc, &resp, + QMI_MHI_SEND_REQ_TIMEOUT_MS); + + IPAWANDBG("QMI_IPA_MHI_CLEANUP_RESP_V01 received\n"); + + return ipa3_check_qmi_response(rc, + QMI_IPA_MHI_CLEANUP_REQ_V01, resp.resp.result, + resp.resp.error, "ipa_mhi_cleanup_req_msg"); +} + +int ipa3_qmi_send_endp_desc_indication( + struct ipa_endp_desc_indication_msg_v01 *req) +{ + IPAWANDBG("Sending QMI_IPA_ENDP_DESC_INDICATION_V01\n"); + + if (unlikely(!ipa3_svc_handle)) + return -ETIMEDOUT; + + return qmi_send_indication(ipa3_svc_handle, + &ipa3_qmi_ctx->client_sq, + QMI_IPA_ENDP_DESC_INDICATION_V01, + IPA_ENDP_DESC_INDICATION_MSG_V01_MAX_MSG_LEN, + ipa_endp_desc_indication_msg_v01_ei, + req); +} + +void ipa3_qmi_init(void) +{ + mutex_init(&ipa3_qmi_lock); + nat_move_qmi_disabled = true; +} + +void ipa3_qmi_cleanup(void) +{ + mutex_destroy(&ipa3_qmi_lock); +} + diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_qmi_service.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_qmi_service.h new file mode 100644 index 0000000000..2a00af8b55 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_qmi_service.h @@ -0,0 +1,632 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2013-2021, The Linux Foundation. All rights reserved. + * + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef IPA_QMI_SERVICE_H +#define IPA_QMI_SERVICE_H + +#include "ipa.h" +#include +#include +#include +#include "ipa_i.h" +#include + +/** + * name of the DL wwan default routing tables for v4 and v6 + */ +#define IPA_A7_QMAP_HDR_NAME "ipa_qmap_hdr" +#define IPA_DFLT_WAN_RT_TBL_NAME "ipa_dflt_wan_rt" +#define MAX_NUM_Q6_RULE 35 +#define MAX_NUM_QMI_RULE_CACHE 10 +#define MAX_NUM_QMI_MPM_AGGR_CACHE 3 +#define DEV_NAME "ipa-wan" +#if IS_ENABLED(CONFIG_QCOM_Q6V5_PAS) +#define SUBSYS_LOCAL_MODEM "mpss" +#else +#define SUBSYS_LOCAL_MODEM "modem" +#endif +#define SUBSYS_REMOTE_MODEM "esoc0" + + +#define IPAWANDBG(fmt, args...) \ + do { \ + pr_debug(DEV_NAME " %s:%d " fmt, __func__,\ + __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf(), \ + DEV_NAME " %s:%d " fmt, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf_low(), \ + DEV_NAME " %s:%d " fmt, ## args); \ + } while (0) + + +#define IPAWANDBG_LOW(fmt, args...) \ + do { \ + pr_debug(DEV_NAME " %s:%d " fmt, __func__,\ + __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf_low(), \ + DEV_NAME " %s:%d " fmt, ## args); \ + } while (0) + +#define IPAWANERR(fmt, args...) \ + do { \ + pr_err(DEV_NAME " %s:%d " fmt, __func__,\ + __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf(), \ + DEV_NAME " %s:%d " fmt, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf_low(), \ + DEV_NAME " %s:%d " fmt, ## args); \ + } while (0) + +#define IPAWANERR_RL(fmt, args...) \ + do { \ + pr_err_ratelimited_ipa(DEV_NAME " %s:%d " fmt, __func__,\ + __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf(), \ + DEV_NAME " %s:%d " fmt, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf_low(), \ + DEV_NAME " %s:%d " fmt, ## args); \ + } while (0) + +#define IPAWANINFO(fmt, args...) \ + do { \ + pr_info(DEV_NAME " %s:%d " fmt, __func__,\ + __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf(), \ + DEV_NAME " %s:%d " fmt, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf_low(), \ + DEV_NAME " %s:%d " fmt, ## args); \ + } while (0) + +extern struct ipa3_qmi_context *ipa3_qmi_ctx; + +struct ipa_offload_connection_val { + enum ipa_ip_type_enum_v01 ip_type; + bool valid; + uint32_t rule_id; + uint32_t rule_hdl; +}; + +struct ipa3_qmi_context { + struct ipa_ioc_ext_intf_prop q6_ul_filter_rule[MAX_NUM_Q6_RULE]; + u32 q6_ul_filter_rule_hdl[MAX_NUM_Q6_RULE]; + int num_ipa_install_fltr_rule_req_ex_msg; + struct ipa_install_fltr_rule_req_ex_msg_v01 + *ipa_install_fltr_rule_req_ex_msg_cache_ptr[MAX_NUM_QMI_RULE_CACHE]; + int num_ipa_fltr_installed_notif_req_msg; + struct ipa_fltr_installed_notif_req_msg_v01 + ipa_fltr_installed_notif_req_msg_cache[MAX_NUM_QMI_RULE_CACHE]; + int num_ipa_configure_ul_firewall_rules_req_msg; + struct ipa_configure_ul_firewall_rules_req_msg_v01 + *ipa_configure_ul_firewall_rules_req_msg_cache_ptr[MAX_NUM_QMI_RULE_CACHE]; + struct ipa_mhi_prime_aggr_info_req_msg_v01 + ipa_mhi_prime_aggr_info_req_msg_cache + [MAX_NUM_QMI_MPM_AGGR_CACHE]; + bool modem_cfg_emb_pipe_flt; + struct sockaddr_qrtr client_sq; + struct sockaddr_qrtr server_sq; + int num_ipa_offload_connection; + struct ipa_offload_connection_val + ipa_offload_cache[QMI_IPA_MAX_FILTERS_V01]; + uint8_t ul_firewall_indices_list_valid; + uint32_t ul_firewall_indices_list_len; + uint32_t ul_firewall_indices_list[QMI_IPA_MAX_FILTERS_V01]; +}; + +struct ipa3_rmnet_mux_val { + uint32_t mux_id; + int8_t vchannel_name[IFNAMSIZ]; + bool mux_channel_set; + bool ul_flt_reg; + bool mux_hdr_set; + uint32_t hdr_hdl; + uint16_t mtu_v4; + uint16_t mtu_v6; +}; + +extern struct qmi_elem_info + ipa3_init_modem_driver_req_msg_data_v01_ei[]; +extern struct qmi_elem_info + ipa3_init_modem_driver_resp_msg_data_v01_ei[]; +extern struct qmi_elem_info + ipa3_indication_reg_req_msg_data_v01_ei[]; +extern struct qmi_elem_info ipa3_indication_reg_resp_msg_data_v01_ei[]; + +extern struct qmi_elem_info + ipa3_master_driver_init_complt_ind_msg_data_v01_ei[]; +extern struct qmi_elem_info ipa3_install_fltr_rule_req_msg_data_v01_ei[]; +extern struct qmi_elem_info ipa3_install_fltr_rule_resp_msg_data_v01_ei[]; +extern struct qmi_elem_info ipa3_fltr_installed_notif_req_msg_data_v01_ei[]; + +extern struct qmi_elem_info + ipa3_fltr_installed_notif_resp_msg_data_v01_ei[]; +extern struct qmi_elem_info + ipa3_enable_force_clear_datapath_req_msg_data_v01_ei[]; +extern struct qmi_elem_info + ipa3_enable_force_clear_datapath_resp_msg_data_v01_ei[]; +extern struct qmi_elem_info + ipa3_disable_force_clear_datapath_req_msg_data_v01_ei[]; +extern struct qmi_elem_info + ipa3_disable_force_clear_datapath_resp_msg_data_v01_ei[]; + +extern struct qmi_elem_info ipa3_config_req_msg_data_v01_ei[]; +extern struct qmi_elem_info ipa3_config_resp_msg_data_v01_ei[]; +extern struct qmi_elem_info ipa3_get_data_stats_req_msg_data_v01_ei[]; +extern struct qmi_elem_info ipa3_get_data_stats_resp_msg_data_v01_ei[]; +extern struct qmi_elem_info ipa3_get_apn_data_stats_req_msg_data_v01_ei[]; +extern struct qmi_elem_info ipa3_get_apn_data_stats_resp_msg_data_v01_ei[]; +extern struct qmi_elem_info ipa3_set_data_usage_quota_req_msg_data_v01_ei[]; + +extern struct qmi_elem_info + ipa3_set_data_usage_quota_resp_msg_data_v01_ei[]; +extern struct qmi_elem_info + ipa3_data_usage_quota_reached_ind_msg_data_v01_ei[]; +extern struct qmi_elem_info + ipa3_stop_data_usage_quota_req_msg_data_v01_ei[]; +extern struct qmi_elem_info + ipa3_stop_data_usage_quota_resp_msg_data_v01_ei[]; +extern struct qmi_elem_info + ipa3_init_modem_driver_cmplt_req_msg_data_v01_ei[]; +extern struct qmi_elem_info + ipa3_init_modem_driver_cmplt_resp_msg_data_v01_ei[]; +extern struct qmi_elem_info + ipa3_install_fltr_rule_req_ex_msg_data_v01_ei[]; +extern struct qmi_elem_info + ipa3_install_fltr_rule_resp_ex_msg_data_v01_ei[]; +extern struct qmi_elem_info + ipa3_ul_firewall_rule_type_data_v01_ei[]; +extern struct qmi_elem_info + ipa3_ul_firewall_config_result_type_data_v01_ei[]; +extern struct + qmi_elem_info ipa3_per_client_stats_info_type_data_v01_ei[]; +extern struct qmi_elem_info + ipa3_enable_per_client_stats_req_msg_data_v01_ei[]; +extern struct qmi_elem_info + ipa3_enable_per_client_stats_resp_msg_data_v01_ei[]; +extern struct qmi_elem_info + ipa3_get_stats_per_client_req_msg_data_v01_ei[]; + +extern struct qmi_elem_info + ipa3_get_stats_per_client_resp_msg_data_v01_ei[]; +extern struct qmi_elem_info + ipa3_configure_ul_firewall_rules_req_msg_data_v01_ei[]; +extern struct qmi_elem_info + ipa3_configure_ul_firewall_rules_resp_msg_data_v01_ei[]; +extern struct qmi_elem_info + ipa3_configure_ul_firewall_rules_ind_msg_data_v01_ei[]; + +extern struct qmi_elem_info ipa_mhi_ready_indication_msg_v01_ei[]; +extern struct qmi_elem_info ipa_mhi_mem_addr_info_type_v01_ei[]; +extern struct qmi_elem_info ipa_mhi_tr_info_type_v01_ei[]; +extern struct qmi_elem_info ipa_mhi_er_info_type_v01_ei[]; +extern struct qmi_elem_info ipa_mhi_alloc_channel_req_msg_v01_ei[]; +extern struct qmi_elem_info ipa_mhi_ch_alloc_resp_type_v01_ei[]; +extern struct qmi_elem_info ipa_mhi_alloc_channel_resp_msg_v01_ei[]; +extern struct qmi_elem_info ipa_mhi_clk_vote_req_msg_v01_ei[]; +extern struct qmi_elem_info ipa_mhi_clk_vote_resp_msg_v01_ei[]; +extern struct qmi_elem_info ipa_mhi_cleanup_req_msg_v01_ei[]; +extern struct qmi_elem_info ipa_mhi_cleanup_resp_msg_v01_ei[]; + +extern struct qmi_elem_info ipa_endp_desc_indication_msg_v01_ei[]; +extern struct qmi_elem_info ipa_mhi_prime_aggr_info_req_msg_v01_ei[]; +extern struct qmi_elem_info ipa_mhi_prime_aggr_info_resp_msg_v01_ei[]; +extern struct qmi_elem_info ipa_add_offload_connection_req_msg_v01_ei[]; +extern struct qmi_elem_info ipa_add_offload_connection_resp_msg_v01_ei[]; +extern struct qmi_elem_info ipa_remove_offload_connection_req_msg_v01_ei[]; +extern struct qmi_elem_info ipa_remove_offload_connection_resp_msg_v01_ei[]; +extern struct qmi_elem_info ipa_bw_change_ind_msg_v01_ei[]; +extern struct qmi_elem_info ipa_move_nat_req_msg_v01_ei[]; +extern struct qmi_elem_info ipa_move_nat_resp_msg_v01_ei[]; +extern struct qmi_elem_info ipa_move_nat_table_complt_ind_msg_v01_ei[]; +extern struct qmi_elem_info ipa_wlan_opt_dp_rsrv_filter_req_msg_data_v01_ei[]; +extern struct qmi_elem_info ipa_wlan_opt_dp_rsrv_filter_resp_msg_data_v01_ei[]; +extern struct qmi_elem_info ipa_wlan_opt_dp_rsrv_filter_complt_ind_msg_data_v01_ei[]; +extern struct qmi_elem_info ipa_wlan_opt_dp_add_filter_req_msg_data_v01_ei[]; +extern struct qmi_elem_info ipa_wlan_opt_dp_add_filter_resp_msg_data_v01_ei[]; +extern struct qmi_elem_info ipa_wlan_opt_dp_add_filter_complt_ind_msg_v01_ei[]; +extern struct qmi_elem_info ipa_wlan_opt_dp_remove_filter_req_msg_data_v01_ei[]; +extern struct qmi_elem_info ipa_wlan_opt_dp_remove_filter_resp_msg_data_v01_ei[]; +extern struct qmi_elem_info ipa_wlan_opt_dp_remove_filter_complt_ind_msg_data_v01_ei[]; +extern struct qmi_elem_info ipa_wlan_opt_dp_remove_all_filter_req_msg_data_v01_ei[]; +extern struct qmi_elem_info ipa_wlan_opt_dp_remove_all_filter_resp_msg_data_v01_ei[]; +extern struct qmi_elem_info ipa_wlan_opt_dp_remove_all_filter_complt_ind_msg_data_v01_ei[]; +extern struct qmi_elem_info ipa_wlan_opt_dp_set_wlan_per_info_req_msg_data_v01_ei[]; +extern struct qmi_elem_info ipa_wlan_opt_dp_set_wlan_per_info_resp_msg_data_v01[]; +/** + * struct ipa3_rmnet_context - IPA rmnet context + * @ipa_rmnet_ssr: support modem SSR + * @polling_interval: Requested interval for polling tethered statistics + * @metered_mux_id: The mux ID on which quota has been set + */ +struct ipa3_rmnet_context { + bool ipa_rmnet_ssr; + u64 polling_interval; + u32 metered_mux_id; +}; + +extern struct ipa3_rmnet_context ipa3_rmnet_ctx; + +#if IS_ENABLED(CONFIG_RMNET_IPA3) + +int ipa3_qmi_service_init(uint32_t wan_platform_type); + +void ipa3_qmi_service_exit(void); + +/* sending filter-install-request to modem*/ +int ipa3_qmi_filter_request_send( + struct ipa_install_fltr_rule_req_msg_v01 *req); + +int ipa3_qmi_filter_request_ex_send( + struct ipa_install_fltr_rule_req_ex_msg_v01 *req); + +int ipa3_qmi_add_offload_request_send( + struct ipa_add_offload_connection_req_msg_v01 *req); + +int ipa3_qmi_rmv_offload_request_send( + struct ipa_remove_offload_connection_req_msg_v01 *req); + +int ipa3_qmi_ul_filter_request_send( + struct ipa_configure_ul_firewall_rules_req_msg_v01 *req); + +/* sending filter-installed-notify-request to modem*/ +int ipa3_qmi_filter_notify_send(struct ipa_fltr_installed_notif_req_msg_v01 + *req); + +/* voting for bus BW to ipa_rm*/ +int ipa3_vote_for_bus_bw(uint32_t *bw_mbps); + +int ipa3_qmi_enable_force_clear_datapath_send( + struct ipa_enable_force_clear_datapath_req_msg_v01 *req); + +int ipa3_qmi_disable_force_clear_datapath_send( + struct ipa_disable_force_clear_datapath_req_msg_v01 *req); + +int ipa3_copy_ul_filter_rule_to_ipa(struct ipa_install_fltr_rule_req_msg_v01 + *rule_req); + +int ipa3_wan_ioctl_init(void); + +void ipa3_wan_ioctl_stop_qmi_messages(void); + +void ipa3_wan_ioctl_enable_qmi_messages(void); + +void ipa3_wan_ioctl_deinit(void); + +void ipa3_qmi_stop_workqueues(void); + +int rmnet_ipa3_poll_tethering_stats(struct wan_ioctl_poll_tethering_stats + *data); + +int rmnet_ipa3_set_data_quota(struct wan_ioctl_set_data_quota *data); + +#ifdef IPA_DATA_WARNING_QUOTA +int rmnet_ipa3_set_data_quota_warning(struct wan_ioctl_set_data_quota_warning + *data); +#endif + +void ipa3_broadcast_quota_reach_ind(uint32_t mux_id, + enum ipa_upstream_type upstream_type, bool is_warning_limit); + +int rmnet_ipa3_set_tether_client_pipe(struct wan_ioctl_set_tether_client_pipe + *data); + +int rmnet_ipa3_query_tethering_stats(struct wan_ioctl_query_tether_stats *data, + bool reset); + +int rmnet_ipa3_query_tethering_stats_all( + struct wan_ioctl_query_tether_stats_all *data); + +int rmnet_ipa3_reset_tethering_stats(struct wan_ioctl_reset_tether_stats *data); +int rmnet_ipa3_set_lan_client_info(struct wan_ioctl_lan_client_info *data); + +int rmnet_ipa3_clear_lan_client_info(struct wan_ioctl_lan_client_info *data); + +int rmnet_ipa3_send_lan_client_msg(struct wan_ioctl_send_lan_client_msg *data); + +int rmnet_ipa3_enable_per_client_stats(bool *data); + +int rmnet_ipa3_query_per_client_stats( + struct wan_ioctl_query_per_client_stats *data); + +int rmnet_ipa3_get_wan_mtu( + struct ipa_mtu_info *data); + +int rmnet_ipa3_query_per_client_stats_v2( + struct wan_ioctl_query_per_client_stats *data); + +int ipa3_qmi_get_data_stats(struct ipa_get_data_stats_req_msg_v01 *req, + struct ipa_get_data_stats_resp_msg_v01 *resp); + +int ipa3_qmi_get_network_stats(struct ipa_get_apn_data_stats_req_msg_v01 *req, + struct ipa_get_apn_data_stats_resp_msg_v01 *resp); + +int ipa3_qmi_set_data_quota(struct ipa_set_data_usage_quota_req_msg_v01 *req); + +int ipa3_qmi_set_aggr_info( + enum ipa_aggr_enum_type_v01 aggr_enum_type); + +int ipa3_qmi_req_ind(bool bw_reg); + +int ipa3_qmi_stop_data_quota(struct ipa_stop_data_usage_quota_req_msg_v01 *req); + +void ipa3_q6_handshake_complete(bool ssr_bootup); + +int ipa3_wwan_set_modem_perf_profile(int throughput); + +int ipa3_wwan_set_modem_state(struct wan_ioctl_notify_wan_state *state); +int ipa3_qmi_enable_per_client_stats( + struct ipa_enable_per_client_stats_req_msg_v01 *req, + struct ipa_enable_per_client_stats_resp_msg_v01 *resp); + +int ipa3_qmi_get_per_client_packet_stats( + struct ipa_get_stats_per_client_req_msg_v01 *req, + struct ipa_get_stats_per_client_resp_msg_v01 *resp); + +int ipa3_qmi_send_mhi_ready_indication( + struct ipa_mhi_ready_indication_msg_v01 *req); + +int ipa3_qmi_send_wdi_opt_dpath_rsrv_flt_ind( + struct ipa_wlan_opt_dp_rsrv_filter_complt_ind_msg_v01 *ind); + +int ipa3_qmi_send_wdi_opt_dpath_rmv_all_flt_ind( + struct ipa_wlan_opt_dp_remove_all_filter_complt_ind_msg_v01 *ind); + +int ipa3_qmi_send_wdi_opt_dpath_ep_info( + struct ipa_wlan_opt_dp_set_wlan_per_info_req_msg_v01 *req); + +int ipa3_qmi_send_endp_desc_indication( + struct ipa_endp_desc_indication_msg_v01 *req); + +int ipa3_qmi_send_mhi_cleanup_request(struct ipa_mhi_cleanup_req_msg_v01 *req); + +/* sending nat table move result indication to modem */ +int rmnet_ipa3_notify_nat_move_res(bool success); + +void ipa3_qmi_init(void); + +void ipa3_qmi_cleanup(void); + +int ipa3_wwan_platform_driver_register(void); + +int ipa3_wwan_init(void); + +void ipa3_wwan_cleanup(void); + +void ipa3_disable_move_nat_resp(void); + +#else /* IS_ENABLED(CONFIG_RMNET_IPA3) */ + +static inline int ipa3_qmi_service_init(uint32_t wan_platform_type) +{ + return -EPERM; +} + +static inline void ipa3_qmi_service_exit(void) { } + +/* sending filter-install-request to modem */ +static inline int ipa3_qmi_filter_request_send( + struct ipa_install_fltr_rule_req_msg_v01 *req) +{ + return -EPERM; +} + +static inline int ipa3_qmi_add_offload_request_send( + struct ipa_add_offload_connection_req_msg_v01 *req) +{ + return -EPERM; +} + +static inline int ipa3_qmi_rmv_offload_request_send( + struct ipa_remove_offload_connection_req_msg_v01 *req) +{ + return -EPERM; +} + +static inline int ipa3_qmi_ul_filter_request_send( + struct ipa_configure_ul_firewall_rules_req_msg_v01 *req) +{ + return -EPERM; +} + +static inline int ipa3_qmi_filter_request_ex_send( + struct ipa_install_fltr_rule_req_ex_msg_v01 *req) +{ + return -EPERM; +} + +/* sending filter-installed-notify-request to modem*/ +static inline int ipa3_qmi_filter_notify_send( + struct ipa_fltr_installed_notif_req_msg_v01 *req) +{ + return -EPERM; +} + +static inline int ipa3_qmi_enable_force_clear_datapath_send( + struct ipa_enable_force_clear_datapath_req_msg_v01 *req) +{ + return -EPERM; +} + +static inline int ipa3_qmi_disable_force_clear_datapath_send( + struct ipa_disable_force_clear_datapath_req_msg_v01 *req) +{ + return -EPERM; +} + +static inline int ipa3_copy_ul_filter_rule_to_ipa( + struct ipa_install_fltr_rule_req_msg_v01 *rule_req) +{ + return -EPERM; +} + +static inline int ipa3_wan_ioctl_init(void) +{ + return -EPERM; +} + +static inline void ipa3_wan_ioctl_stop_qmi_messages(void) { } + +static inline void ipa3_wan_ioctl_enable_qmi_messages(void) { } + +static inline void ipa3_wan_ioctl_deinit(void) { } + +static inline void ipa3_qmi_stop_workqueues(void) { } + +static inline int ipa3_vote_for_bus_bw(uint32_t *bw_mbps) +{ + return -EPERM; +} + +static inline int rmnet_ipa3_poll_tethering_stats( + struct wan_ioctl_poll_tethering_stats *data) +{ + return -EPERM; +} + +static inline int rmnet_ipa3_set_data_quota( + struct wan_ioctl_set_data_quota *data) +{ + return -EPERM; +} + +#ifdef IPA_DATA_WARNING_QUOTA +static inline int rmnet_ipa3_set_data_quota_warning( + struct wan_ioctl_set_data_quota_warning *data) +{ + return -EPERM; +} +#endif + +static inline void ipa3_broadcast_quota_reach_ind(uint32_t mux_id, + enum ipa_upstream_type upstream_type, bool is_warning_limit) { } + +static inline int ipa3_qmi_get_data_stats( + struct ipa_get_data_stats_req_msg_v01 *req, + struct ipa_get_data_stats_resp_msg_v01 *resp) +{ + return -EPERM; +} + +static inline int ipa3_qmi_get_network_stats( + struct ipa_get_apn_data_stats_req_msg_v01 *req, + struct ipa_get_apn_data_stats_resp_msg_v01 *resp) +{ + return -EPERM; +} + +static inline int ipa3_qmi_set_data_quota( + struct ipa_set_data_usage_quota_req_msg_v01 *req) +{ + return -EPERM; +} + +static inline int ipa3_qmi_stop_data_quota( +struct ipa_stop_data_usage_quota_req_msg_v01 *req) +{ + return -EPERM; +} + +static inline void ipa3_q6_handshake_complete(bool ssr_bootup) { } + +static inline int ipa3_qmi_send_mhi_ready_indication( + struct ipa_mhi_ready_indication_msg_v01 *req) +{ + return -EPERM; +} + +static int ipa3_qmi_send_wdi_opt_dpath_rsrv_flt_ind( + struct ipa_wlan_opt_dp_remove_all_filter_complt_ind_msg_v01 *ind) +{ + return -EPERM; +} + +static int ipa3_qmi_send_wdi_opt_dpath_rmv_all_flt_ind( + struct ipa_wlan_opt_dp_remove_all_filter_complt_ind_msg_v01 *ind) +{ + return -EPERM; +} + +static int ipa3_qmi_send_wdi_opt_dpath_ep_info( + struct ipa_wlan_opt_dp_set_wlan_per_info_req_msg_v01 *req) +{ + return -EPERM; +} + +static inline int ipa3_qmi_send_endp_desc_indication( + struct ipa_endp_desc_indication_msg_v01 *req) +{ + return -EPERM; +} + +static inline int ipa3_qmi_send_mhi_cleanup_request( + struct ipa_mhi_cleanup_req_msg_v01 *req) +{ + return -EPERM; +} + +static int rmnet_ipa3_notify_nat_move_res(bool success) +{ + return -EPERM +} + +static inline int ipa3_wwan_set_modem_perf_profile( + int throughput) +{ + return -EPERM; +} +static inline int ipa3_qmi_enable_per_client_stats( + struct ipa_enable_per_client_stats_req_msg_v01 *req, + struct ipa_enable_per_client_stats_resp_msg_v01 *resp) +{ + return -EPERM; +} + +static inline int ipa3_qmi_get_per_client_packet_stats( + struct ipa_get_stats_per_client_req_msg_v01 *req, + struct ipa_get_stats_per_client_resp_msg_v01 *resp) +{ + return -EPERM; +} + +static inline int ipa3_qmi_set_aggr_info( + enum ipa_aggr_enum_type_v01 aggr_enum_type) +{ + return -EPERM; +} + +static inline void ipa3_qmi_init(void) +{ + +} + +static inline void ipa3_qmi_cleanup(void) +{ + +} + +static void ipa3_disable_move_nat_resp(void) +{ + +} + +static inline int ipa3_wwan_platform_driver_register(void) +{ + return -EPERM; +} + +static inline int ipa3_wwan_init(void) +{ + return -EPERM; +} + +static inline void ipa3_wwan_cleanup(void) +{ + +} + +#endif /* IS_ENABLED(CONFIG_RMNET_IPA3) */ + +#endif /* IPA_QMI_SERVICE_H */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_qmi_service_v01.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_qmi_service_v01.c new file mode 100644 index 0000000000..e5da652c0e --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_qmi_service_v01.c @@ -0,0 +1,5954 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2013-2019, 2021 The Linux Foundation. All rights reserved. + * + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +#include + +#include "ipa_qmi_service.h" + +/* Type Definitions */ +static struct qmi_elem_info ipa3_hdr_tbl_info_type_data_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct ipa_hdr_tbl_info_type_v01, + modem_offset_start), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct ipa_hdr_tbl_info_type_v01, + modem_offset_end), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +static struct qmi_elem_info ipa3_route_tbl_info_type_data_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct ipa_route_tbl_info_type_v01, + route_tbl_start_addr), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct ipa_route_tbl_info_type_v01, + num_indices), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +static struct qmi_elem_info ipa3_filter_tbl_info_type_data_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct ipa_filter_stats_info_type_v01, + hw_filter_stats_start_addr), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct ipa_filter_stats_info_type_v01, + hw_filter_stats_size), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct ipa_filter_stats_info_type_v01, + hw_filter_stats_start_index), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct ipa_filter_stats_info_type_v01, + hw_filter_stats_end_index), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +static struct qmi_elem_info ipa3_modem_mem_info_type_data_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct ipa_modem_mem_info_type_v01, + block_start_addr), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct ipa_modem_mem_info_type_v01, + size), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +static struct qmi_elem_info ipa3_hdr_proc_ctx_tbl_info_type_data_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof( + struct ipa_hdr_proc_ctx_tbl_info_type_v01, + modem_offset_start), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof( + struct ipa_hdr_proc_ctx_tbl_info_type_v01, + modem_offset_end), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +static struct qmi_elem_info ipa3_zip_tbl_info_type_data_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct ipa_zip_tbl_info_type_v01, + modem_offset_start), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct ipa_zip_tbl_info_type_v01, + modem_offset_end), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +static struct qmi_elem_info ipa3_ipfltr_range_eq_16_type_data_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof( + struct ipa_ipfltr_range_eq_16_type_v01, + offset), + }, + { + .data_type = QMI_UNSIGNED_2_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint16_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof( + struct ipa_ipfltr_range_eq_16_type_v01, + range_low), + }, + { + .data_type = QMI_UNSIGNED_2_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint16_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof( + struct ipa_ipfltr_range_eq_16_type_v01, + range_high), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +static struct qmi_elem_info ipa3_ipfltr_mask_eq_32_type_data_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof( + struct ipa_ipfltr_mask_eq_32_type_v01, + offset), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof( + struct ipa_ipfltr_mask_eq_32_type_v01, + mask), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof( + struct ipa_ipfltr_mask_eq_32_type_v01, + value), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +static struct qmi_elem_info ipa3_ipfltr_eq_16_type_data_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof( + struct ipa_ipfltr_eq_16_type_v01, + offset), + }, + { + .data_type = QMI_UNSIGNED_2_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint16_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct ipa_ipfltr_eq_16_type_v01, + value), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +static struct qmi_elem_info ipa3_ipfltr_eq_32_type_data_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct ipa_ipfltr_eq_32_type_v01, + offset), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct ipa_ipfltr_eq_32_type_v01, + value), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +static struct qmi_elem_info ipa3_ipfltr_mask_eq_128_type_data_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof( + struct ipa_ipfltr_mask_eq_128_type_v01, + offset), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 16, + .elem_size = sizeof(uint8_t), + .array_type = STATIC_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof( + struct ipa_ipfltr_mask_eq_128_type_v01, + mask), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 16, + .elem_size = sizeof(uint8_t), + .array_type = STATIC_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof( + struct ipa_ipfltr_mask_eq_128_type_v01, + value), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +static struct qmi_elem_info ipa3_filter_rule_type_data_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_2_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint16_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof( + struct ipa_filter_rule_type_v01, + rule_eq_bitmap), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof( + struct ipa_filter_rule_type_v01, + tos_eq_present), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct ipa_filter_rule_type_v01, + tos_eq), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct ipa_filter_rule_type_v01, + protocol_eq_present), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct ipa_filter_rule_type_v01, + protocol_eq), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct ipa_filter_rule_type_v01, + num_ihl_offset_range_16), + }, + { + .data_type = QMI_STRUCT, + .elem_len = QMI_IPA_IPFLTR_NUM_IHL_RANGE_16_EQNS_V01, + .elem_size = sizeof( + struct ipa_ipfltr_range_eq_16_type_v01), + .array_type = STATIC_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct ipa_filter_rule_type_v01, + ihl_offset_range_16), + .ei_array = ipa3_ipfltr_range_eq_16_type_data_v01_ei, + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct ipa_filter_rule_type_v01, + num_offset_meq_32), + }, + { + .data_type = QMI_STRUCT, + .elem_len = QMI_IPA_IPFLTR_NUM_MEQ_32_EQNS_V01, + .elem_size = sizeof(struct ipa_ipfltr_mask_eq_32_type_v01), + .array_type = STATIC_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct ipa_filter_rule_type_v01, + offset_meq_32), + .ei_array = ipa3_ipfltr_mask_eq_32_type_data_v01_ei, + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct ipa_filter_rule_type_v01, + tc_eq_present), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct ipa_filter_rule_type_v01, + tc_eq), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct ipa_filter_rule_type_v01, + flow_eq_present), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct ipa_filter_rule_type_v01, + flow_eq), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct ipa_filter_rule_type_v01, + ihl_offset_eq_16_present), + }, + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct ipa_ipfltr_eq_16_type_v01), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct ipa_filter_rule_type_v01, + ihl_offset_eq_16), + .ei_array = ipa3_ipfltr_eq_16_type_data_v01_ei, + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct ipa_filter_rule_type_v01, + ihl_offset_eq_32_present), + }, + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct ipa_ipfltr_eq_32_type_v01), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct ipa_filter_rule_type_v01, + ihl_offset_eq_32), + .ei_array = ipa3_ipfltr_eq_32_type_data_v01_ei, + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct ipa_filter_rule_type_v01, + num_ihl_offset_meq_32), + }, + { + .data_type = QMI_STRUCT, + .elem_len = QMI_IPA_IPFLTR_NUM_IHL_MEQ_32_EQNS_V01, + .elem_size = sizeof(struct ipa_ipfltr_mask_eq_32_type_v01), + .array_type = STATIC_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct ipa_filter_rule_type_v01, + ihl_offset_meq_32), + .ei_array = ipa3_ipfltr_mask_eq_32_type_data_v01_ei, + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct ipa_filter_rule_type_v01, + num_offset_meq_128), + }, + { + .data_type = QMI_STRUCT, + .elem_len = + QMI_IPA_IPFLTR_NUM_MEQ_128_EQNS_V01, + .elem_size = sizeof( + struct ipa_ipfltr_mask_eq_128_type_v01), + .array_type = STATIC_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof( + struct ipa_filter_rule_type_v01, + offset_meq_128), + .ei_array = ipa3_ipfltr_mask_eq_128_type_data_v01_ei, + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct ipa_filter_rule_type_v01, + metadata_meq32_present), + }, + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct ipa_ipfltr_mask_eq_32_type_v01), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct ipa_filter_rule_type_v01, + metadata_meq32), + .ei_array = ipa3_ipfltr_mask_eq_32_type_data_v01_ei, + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct ipa_filter_rule_type_v01, + ipv4_frag_eq_present), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +static struct qmi_elem_info ipa_filter_spec_type_data_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct ipa_filter_spec_type_v01, + filter_spec_identifier), + }, + { + .data_type = QMI_SIGNED_4_BYTE_ENUM, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct ipa_filter_spec_type_v01, + ip_type), + }, + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct ipa_filter_rule_type_v01), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct ipa_filter_spec_type_v01, + filter_rule), + .ei_array = ipa3_filter_rule_type_data_v01_ei, + }, + { + .data_type = QMI_SIGNED_4_BYTE_ENUM, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct ipa_filter_spec_type_v01, + filter_action), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct ipa_filter_spec_type_v01, + is_routing_table_index_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct ipa_filter_spec_type_v01, + route_table_index), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct ipa_filter_spec_type_v01, + is_mux_id_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct ipa_filter_spec_type_v01, + mux_id), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +static struct qmi_elem_info ipa_filter_spec_ex_type_data_v01_ei[] = { + { + .data_type = QMI_SIGNED_4_BYTE_ENUM, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct ipa_filter_spec_ex_type_v01, + ip_type), + }, + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct ipa_filter_rule_type_v01), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct ipa_filter_spec_ex_type_v01, + filter_rule), + .ei_array = ipa3_filter_rule_type_data_v01_ei, + }, + { + .data_type = QMI_SIGNED_4_BYTE_ENUM, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct ipa_filter_spec_ex_type_v01, + filter_action), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct ipa_filter_spec_ex_type_v01, + is_routing_table_index_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct ipa_filter_spec_ex_type_v01, + route_table_index), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct ipa_filter_spec_ex_type_v01, + is_mux_id_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct ipa_filter_spec_ex_type_v01, + mux_id), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct ipa_filter_spec_ex_type_v01, + rule_id), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct ipa_filter_spec_ex_type_v01, + is_rule_hashable), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +static struct +qmi_elem_info ipa3_filter_rule_identifier_to_handle_map_data_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof( + struct ipa_filter_rule_identifier_to_handle_map_v01, + filter_spec_identifier), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof( + struct ipa_filter_rule_identifier_to_handle_map_v01, + filter_handle), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +static struct qmi_elem_info ipa3_filter_handle_to_index_map_data_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof( + struct ipa_filter_handle_to_index_map_v01, + filter_handle), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof( + struct ipa_filter_handle_to_index_map_v01, + filter_index), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa3_init_modem_driver_req_msg_data_v01_ei[] = { + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_init_modem_driver_req_msg_v01, + platform_type_valid), + }, + { + .data_type = QMI_SIGNED_4_BYTE_ENUM, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_init_modem_driver_req_msg_v01, + platform_type), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof( + struct ipa_init_modem_driver_req_msg_v01, + hdr_tbl_info_valid), + }, + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct ipa_hdr_tbl_info_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof( + struct ipa_init_modem_driver_req_msg_v01, + hdr_tbl_info), + .ei_array = ipa3_hdr_tbl_info_type_data_v01_ei, + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x12, + .offset = offsetof( + struct ipa_init_modem_driver_req_msg_v01, + v4_route_tbl_info_valid), + }, + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct ipa_route_tbl_info_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x12, + .offset = offsetof( + struct ipa_init_modem_driver_req_msg_v01, + v4_route_tbl_info), + .ei_array = ipa3_route_tbl_info_type_data_v01_ei, + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x13, + .offset = offsetof( + struct ipa_init_modem_driver_req_msg_v01, + v6_route_tbl_info_valid), + }, + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct ipa_route_tbl_info_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x13, + .offset = offsetof( + struct ipa_init_modem_driver_req_msg_v01, + v6_route_tbl_info), + .ei_array = ipa3_route_tbl_info_type_data_v01_ei, + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x14, + .offset = offsetof( + struct ipa_init_modem_driver_req_msg_v01, + v4_filter_tbl_start_addr_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x14, + .offset = offsetof( + struct ipa_init_modem_driver_req_msg_v01, + v4_filter_tbl_start_addr), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x15, + .offset = offsetof( + struct ipa_init_modem_driver_req_msg_v01, + v6_filter_tbl_start_addr_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x15, + .offset = offsetof( + struct ipa_init_modem_driver_req_msg_v01, + v6_filter_tbl_start_addr), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x16, + .offset = offsetof( + struct ipa_init_modem_driver_req_msg_v01, + modem_mem_info_valid), + }, + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct ipa_modem_mem_info_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x16, + .offset = offsetof( + struct ipa_init_modem_driver_req_msg_v01, + modem_mem_info), + .ei_array = ipa3_modem_mem_info_type_data_v01_ei, + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x17, + .offset = offsetof( + struct ipa_init_modem_driver_req_msg_v01, + ctrl_comm_dest_end_pt_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x17, + .offset = offsetof( + struct ipa_init_modem_driver_req_msg_v01, + ctrl_comm_dest_end_pt), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x18, + .offset = offsetof( + struct ipa_init_modem_driver_req_msg_v01, + is_ssr_bootup_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x18, + .offset = offsetof( + struct ipa_init_modem_driver_req_msg_v01, + is_ssr_bootup), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x19, + .offset = offsetof( + struct ipa_init_modem_driver_req_msg_v01, + hdr_proc_ctx_tbl_info_valid), + }, + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof( + struct ipa_hdr_proc_ctx_tbl_info_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x19, + .offset = offsetof( + struct ipa_init_modem_driver_req_msg_v01, + hdr_proc_ctx_tbl_info), + .ei_array = ipa3_hdr_proc_ctx_tbl_info_type_data_v01_ei, + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x1A, + .offset = offsetof( + struct ipa_init_modem_driver_req_msg_v01, + zip_tbl_info_valid), + }, + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct ipa_zip_tbl_info_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x1A, + .offset = offsetof( + struct ipa_init_modem_driver_req_msg_v01, + zip_tbl_info), + .ei_array = ipa3_zip_tbl_info_type_data_v01_ei, + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x1B, + .offset = offsetof( + struct ipa_init_modem_driver_req_msg_v01, + v4_hash_route_tbl_info_valid), + }, + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct ipa_route_tbl_info_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x1B, + .offset = offsetof( + struct ipa_init_modem_driver_req_msg_v01, + v4_hash_route_tbl_info), + .ei_array = ipa3_route_tbl_info_type_data_v01_ei, + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x1C, + .offset = offsetof( + struct ipa_init_modem_driver_req_msg_v01, + v6_hash_route_tbl_info_valid), + }, + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct ipa_route_tbl_info_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x1C, + .offset = offsetof( + struct ipa_init_modem_driver_req_msg_v01, + v6_hash_route_tbl_info), + .ei_array = ipa3_route_tbl_info_type_data_v01_ei, + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x1D, + .offset = offsetof( + struct ipa_init_modem_driver_req_msg_v01, + v4_hash_filter_tbl_start_addr_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x1D, + .offset = offsetof( + struct ipa_init_modem_driver_req_msg_v01, + v4_hash_filter_tbl_start_addr), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x1E, + .offset = offsetof( + struct ipa_init_modem_driver_req_msg_v01, + v6_hash_filter_tbl_start_addr_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x1E, + .offset = offsetof( + struct ipa_init_modem_driver_req_msg_v01, + v6_hash_filter_tbl_start_addr), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x1F, + .offset = offsetof( + struct ipa_init_modem_driver_req_msg_v01, + hw_stats_quota_base_addr_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x1F, + .offset = offsetof( + struct ipa_init_modem_driver_req_msg_v01, + hw_stats_quota_base_addr), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x20, + .offset = offsetof( + struct ipa_init_modem_driver_req_msg_v01, + hw_stats_quota_size_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x20, + .offset = offsetof( + struct ipa_init_modem_driver_req_msg_v01, + hw_stats_quota_size), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x21, + .offset = offsetof( + struct ipa_init_modem_driver_req_msg_v01, + hw_drop_stats_base_addr_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x21, + .offset = offsetof( + struct ipa_init_modem_driver_req_msg_v01, + hw_drop_stats_base_addr), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x22, + .offset = offsetof( + struct ipa_init_modem_driver_req_msg_v01, + hw_drop_stats_table_size_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x22, + .offset = offsetof( + struct ipa_init_modem_driver_req_msg_v01, + hw_drop_stats_table_size), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x23, + .offset = offsetof( + struct ipa_init_modem_driver_req_msg_v01, + hw_fiter_stats_info_valid), + }, + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct ipa_filter_stats_info_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x23, + .offset = offsetof( + struct ipa_init_modem_driver_req_msg_v01, + hw_filter_stats_info), + .ei_array = ipa3_filter_tbl_info_type_data_v01_ei, + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x24, + .offset = offsetof( + struct ipa_init_modem_driver_req_msg_v01, + smem_info_valid), + }, + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct ipa_modem_mem_info_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x24, + .offset = offsetof( + struct ipa_init_modem_driver_req_msg_v01, + smem_info), + .ei_array = ipa3_modem_mem_info_type_data_v01_ei, + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x25, + .offset = offsetof( + struct ipa_init_modem_driver_req_msg_v01, + per_stats_smem_info_valid), + }, + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct ipa_modem_mem_info_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x25, + .offset = offsetof( + struct ipa_init_modem_driver_req_msg_v01, + per_stats_smem_info), + .ei_array = ipa3_modem_mem_info_type_data_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, + +}; + +struct qmi_elem_info ipa3_init_modem_driver_resp_msg_data_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof( + struct ipa_init_modem_driver_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_init_modem_driver_resp_msg_v01, + ctrl_comm_dest_end_pt_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_init_modem_driver_resp_msg_v01, + ctrl_comm_dest_end_pt), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof( + struct ipa_init_modem_driver_resp_msg_v01, + default_end_pt_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof( + struct ipa_init_modem_driver_resp_msg_v01, + default_end_pt), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x12, + .offset = offsetof( + struct ipa_init_modem_driver_resp_msg_v01, + modem_driver_init_pending_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x12, + .offset = offsetof( + struct ipa_init_modem_driver_resp_msg_v01, + modem_driver_init_pending), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa3_init_modem_driver_cmplt_req_msg_data_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x01, + .offset = offsetof( + struct ipa_init_modem_driver_cmplt_req_msg_v01, + status), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa3_init_modem_driver_cmplt_resp_msg_data_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof( + struct ipa_init_modem_driver_cmplt_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa3_indication_reg_req_msg_data_v01_ei[] = { + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_indication_reg_req_msg_v01, + master_driver_init_complete_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_indication_reg_req_msg_v01, + master_driver_init_complete), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof( + struct ipa_indication_reg_req_msg_v01, + data_usage_quota_reached_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof( + struct ipa_indication_reg_req_msg_v01, + data_usage_quota_reached), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x12, + .offset = offsetof( + struct ipa_indication_reg_req_msg_v01, + ipa_mhi_ready_ind_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x12, + .offset = offsetof( + struct ipa_indication_reg_req_msg_v01, + ipa_mhi_ready_ind), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x13, + .offset = offsetof( + struct ipa_indication_reg_req_msg_v01, + endpoint_desc_ind_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x13, + .offset = offsetof( + struct ipa_indication_reg_req_msg_v01, + endpoint_desc_ind), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x14, + .offset = offsetof( + struct ipa_indication_reg_req_msg_v01, + bw_change_ind_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x14, + .offset = offsetof( + struct ipa_indication_reg_req_msg_v01, + bw_change_ind), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa3_indication_reg_resp_msg_data_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof( + struct ipa_indication_reg_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa3_master_driver_init_complt_ind_msg_data_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct + ipa_master_driver_init_complt_ind_msg_v01, + master_driver_init_status), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa_move_nat_table_complt_ind_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct + ipa_move_nat_table_complt_ind_msg_v01, + nat_table_move_status), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +static struct qmi_elem_info ipa_filter_rule_req2_type_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_2_BYTE, + .elem_len = 1, + .elem_size = sizeof(u16), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_filter_rule_req2_type_v01, + rule_eq_bitmap), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_filter_rule_req2_type_v01, + pure_ack_eq_present), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_filter_rule_req2_type_v01, + pure_ack_eq), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_filter_rule_req2_type_v01, + protocol_eq_present), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_filter_rule_req2_type_v01, + protocol_eq), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_filter_rule_req2_type_v01, + num_ihl_offset_range_16), + }, + { + .data_type = QMI_STRUCT, + .elem_len = QMI_IPA_IPFLTR_NUM_IHL_RANGE_16_EQNS_V01, + .elem_size = sizeof( + struct ipa_ipfltr_range_eq_16_type_v01), + .array_type = STATIC_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_filter_rule_req2_type_v01, + ihl_offset_range_16), + .ei_array = ipa3_ipfltr_range_eq_16_type_data_v01_ei, + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_filter_rule_req2_type_v01, + num_offset_meq_32), + }, + { + .data_type = QMI_STRUCT, + .elem_len = QMI_IPA_IPFLTR_NUM_MEQ_32_EQNS_V01, + .elem_size = sizeof(struct ipa_ipfltr_mask_eq_32_type_v01), + .array_type = STATIC_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_filter_rule_req2_type_v01, + offset_meq_32), + .ei_array = ipa3_ipfltr_mask_eq_32_type_data_v01_ei, + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_filter_rule_req2_type_v01, + tc_eq_present), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_filter_rule_req2_type_v01, + tc_eq), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_filter_rule_req2_type_v01, + flow_eq_present), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_filter_rule_req2_type_v01, + flow_eq), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_filter_rule_req2_type_v01, + ihl_offset_eq_16_present), + }, + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct ipa_ipfltr_eq_16_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_filter_rule_req2_type_v01, + ihl_offset_eq_16), + .ei_array = ipa3_ipfltr_eq_16_type_data_v01_ei, + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_filter_rule_req2_type_v01, + ihl_offset_eq_32_present), + }, + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct ipa_ipfltr_eq_32_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_filter_rule_req2_type_v01, + ihl_offset_eq_32), + .ei_array = ipa3_ipfltr_eq_32_type_data_v01_ei, + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_filter_rule_req2_type_v01, + num_ihl_offset_meq_32), + }, + { + .data_type = QMI_STRUCT, + .elem_len = QMI_IPA_IPFLTR_NUM_IHL_MEQ_32_EQNS_V01, + .elem_size = sizeof(struct ipa_ipfltr_mask_eq_32_type_v01), + .array_type = STATIC_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_filter_rule_req2_type_v01, + ihl_offset_meq_32), + .ei_array = ipa3_ipfltr_mask_eq_32_type_data_v01_ei, + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_filter_rule_req2_type_v01, + num_offset_meq_128), + }, + { + .data_type = QMI_STRUCT, + .elem_len = QMI_IPA_IPFLTR_NUM_MEQ_128_EQNS_V01, + .elem_size = sizeof( + struct ipa_ipfltr_mask_eq_128_type_v01), + .array_type = STATIC_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_filter_rule_req2_type_v01, + offset_meq_128), + .ei_array = ipa3_ipfltr_mask_eq_128_type_data_v01_ei, + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_filter_rule_req2_type_v01, + metadata_meq32_present), + }, + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct ipa_ipfltr_mask_eq_32_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_filter_rule_req2_type_v01, + metadata_meq32), + .ei_array = ipa3_ipfltr_mask_eq_32_type_data_v01_ei, + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_filter_rule_req2_type_v01, + ipv4_frag_eq_present), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +static struct qmi_elem_info ipa_filter_spec_ex2_type_v01_ei[] = { + { + .data_type = QMI_SIGNED_4_BYTE_ENUM, + .elem_len = 1, + .elem_size = sizeof(enum ipa_ip_type_enum_v01), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_filter_spec_ex2_type_v01, + ip_type), + }, + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct ipa_filter_rule_req2_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_filter_spec_ex2_type_v01, + filter_rule), + .ei_array = ipa_filter_rule_req2_type_v01_ei, + }, + { + .data_type = QMI_SIGNED_4_BYTE_ENUM, + .elem_len = 1, + .elem_size = sizeof(enum ipa_filter_action_enum_v01), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_filter_spec_ex2_type_v01, + filter_action), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_filter_spec_ex2_type_v01, + is_routing_table_index_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_filter_spec_ex2_type_v01, + route_table_index), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_filter_spec_ex2_type_v01, + is_mux_id_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_filter_spec_ex2_type_v01, + mux_id), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_filter_spec_ex2_type_v01, + rule_id), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_filter_spec_ex2_type_v01, + is_rule_hashable), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa3_install_fltr_rule_req_msg_data_v01_ei[] = { + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_install_fltr_rule_req_msg_v01, + filter_spec_list_valid), + }, + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_install_fltr_rule_req_msg_v01, + filter_spec_list_len), + }, + { + .data_type = QMI_STRUCT, + .elem_len = QMI_IPA_MAX_FILTERS_V01, + .elem_size = sizeof(struct ipa_filter_spec_type_v01), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_install_fltr_rule_req_msg_v01, + filter_spec_list), + .ei_array = ipa_filter_spec_type_data_v01_ei, + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof( + struct ipa_install_fltr_rule_req_msg_v01, + source_pipe_index_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof( + struct ipa_install_fltr_rule_req_msg_v01, + source_pipe_index), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x12, + .offset = offsetof( + struct ipa_install_fltr_rule_req_msg_v01, + num_ipv4_filters_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x12, + .offset = offsetof( + struct ipa_install_fltr_rule_req_msg_v01, + num_ipv4_filters), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x13, + .offset = offsetof( + struct ipa_install_fltr_rule_req_msg_v01, + num_ipv6_filters_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x13, + .offset = offsetof( + struct ipa_install_fltr_rule_req_msg_v01, + num_ipv6_filters), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x14, + .offset = offsetof( + struct ipa_install_fltr_rule_req_msg_v01, + xlat_filter_indices_list_valid), + }, + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x14, + .offset = offsetof( + struct ipa_install_fltr_rule_req_msg_v01, + xlat_filter_indices_list_len), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = QMI_IPA_MAX_FILTERS_V01, + .elem_size = sizeof(uint32_t), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x14, + .offset = offsetof( + struct ipa_install_fltr_rule_req_msg_v01, + xlat_filter_indices_list), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x15, + .offset = offsetof( + struct ipa_install_fltr_rule_req_msg_v01, + filter_spec_ex_list_valid), + }, + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x15, + .offset = offsetof( + struct ipa_install_fltr_rule_req_msg_v01, + filter_spec_ex_list_len), + }, + { + .data_type = QMI_STRUCT, + .elem_len = QMI_IPA_MAX_FILTERS_V01, + .elem_size = sizeof(struct ipa_filter_spec_ex_type_v01), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x15, + .offset = offsetof( + struct ipa_install_fltr_rule_req_msg_v01, + filter_spec_ex_list), + .ei_array = ipa_filter_spec_ex_type_data_v01_ei, + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x16, + .offset = offsetof( + struct ipa_install_fltr_rule_req_msg_v01, + filter_spec_ex2_list_valid), + }, + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x16, + .offset = offsetof( + struct ipa_install_fltr_rule_req_msg_v01, + filter_spec_ex2_list_len), + }, + { + .data_type = QMI_STRUCT, + .elem_len = QMI_IPA_MAX_FILTERS_V01, + .elem_size = sizeof(struct ipa_filter_spec_ex2_type_v01), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x16, + .offset = offsetof( + struct ipa_install_fltr_rule_req_msg_v01, + filter_spec_ex2_list), + .ei_array = ipa_filter_spec_ex2_type_v01_ei, + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x17, + .offset = offsetof( + struct ipa_install_fltr_rule_req_msg_v01, + ul_firewall_indices_list_valid), + }, + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x17, + .offset = offsetof( + struct ipa_install_fltr_rule_req_msg_v01, + ul_firewall_indices_list_len), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = QMI_IPA_MAX_FILTERS_V01, + .elem_size = sizeof(uint32_t), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x17, + .offset = offsetof( + struct ipa_install_fltr_rule_req_msg_v01, + ul_firewall_indices_list), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa3_install_fltr_rule_resp_msg_data_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof( + struct ipa_install_fltr_rule_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_install_fltr_rule_resp_msg_v01, + filter_handle_list_valid), + }, + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_install_fltr_rule_resp_msg_v01, + filter_handle_list_len), + }, + { + .data_type = QMI_STRUCT, + .elem_len = QMI_IPA_MAX_FILTERS_V01, + .elem_size = sizeof( + struct ipa_filter_rule_identifier_to_handle_map_v01), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_install_fltr_rule_resp_msg_v01, + filter_handle_list), + .ei_array = + ipa3_filter_rule_identifier_to_handle_map_data_v01_ei, + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof( + struct ipa_install_fltr_rule_resp_msg_v01, + rule_id_valid), + }, + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof( + struct ipa_install_fltr_rule_resp_msg_v01, + rule_id_len), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = QMI_IPA_MAX_FILTERS_V01, + .elem_size = sizeof(uint32_t), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x11, + .offset = offsetof( + struct ipa_install_fltr_rule_resp_msg_v01, + rule_id), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa3_fltr_installed_notif_req_msg_data_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x01, + .offset = offsetof( + struct ipa_fltr_installed_notif_req_msg_v01, + source_pipe_index), + }, + { + .data_type = QMI_UNSIGNED_2_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint16_t), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof( + struct ipa_fltr_installed_notif_req_msg_v01, + install_status), + }, + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x03, + .offset = offsetof( + struct ipa_fltr_installed_notif_req_msg_v01, + filter_index_list_len), + }, + { + .data_type = QMI_STRUCT, + .elem_len = QMI_IPA_MAX_FILTERS_V01, + .elem_size = sizeof( + struct ipa_filter_handle_to_index_map_v01), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x03, + .offset = offsetof( + struct ipa_fltr_installed_notif_req_msg_v01, + filter_index_list), + .ei_array = ipa3_filter_handle_to_index_map_data_v01_ei, + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_fltr_installed_notif_req_msg_v01, + embedded_pipe_index_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_fltr_installed_notif_req_msg_v01, + embedded_pipe_index), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof( + struct ipa_fltr_installed_notif_req_msg_v01, + retain_header_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof( + struct ipa_fltr_installed_notif_req_msg_v01, + retain_header), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x12, + .offset = offsetof( + struct ipa_fltr_installed_notif_req_msg_v01, + embedded_call_mux_id_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x12, + .offset = offsetof( + struct ipa_fltr_installed_notif_req_msg_v01, + embedded_call_mux_id), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x13, + .offset = offsetof( + struct ipa_fltr_installed_notif_req_msg_v01, + num_ipv4_filters_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x13, + .offset = offsetof( + struct ipa_fltr_installed_notif_req_msg_v01, + num_ipv4_filters), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x14, + .offset = offsetof( + struct ipa_fltr_installed_notif_req_msg_v01, + num_ipv6_filters_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x14, + .offset = offsetof( + struct ipa_fltr_installed_notif_req_msg_v01, + num_ipv6_filters), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x15, + .offset = offsetof( + struct ipa_fltr_installed_notif_req_msg_v01, + start_ipv4_filter_idx_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x15, + .offset = offsetof( + struct ipa_fltr_installed_notif_req_msg_v01, + start_ipv4_filter_idx), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x16, + .offset = offsetof( + struct ipa_fltr_installed_notif_req_msg_v01, + start_ipv6_filter_idx_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x16, + .offset = offsetof( + struct ipa_fltr_installed_notif_req_msg_v01, + start_ipv6_filter_idx), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x17, + .offset = offsetof( + struct ipa_fltr_installed_notif_req_msg_v01, + rule_id_valid), + }, + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x17, + .offset = offsetof( + struct ipa_fltr_installed_notif_req_msg_v01, + rule_id_len), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = QMI_IPA_MAX_FILTERS_V01, + .elem_size = sizeof(uint32_t), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x17, + .offset = offsetof( + struct ipa_fltr_installed_notif_req_msg_v01, + rule_id), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x18, + .offset = offsetof( + struct ipa_fltr_installed_notif_req_msg_v01, + dst_pipe_id_valid), + }, + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x18, + .offset = offsetof( + struct ipa_fltr_installed_notif_req_msg_v01, + dst_pipe_id_len), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = QMI_IPA_MAX_CLIENT_DST_PIPES_V01, + .elem_size = sizeof(uint32_t), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x18, + .offset = offsetof( + struct ipa_fltr_installed_notif_req_msg_v01, + dst_pipe_id), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x19, + .offset = offsetof( + struct ipa_fltr_installed_notif_req_msg_v01, + rule_id_ex_valid), + }, + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x19, + .offset = offsetof( + struct ipa_fltr_installed_notif_req_msg_v01, + rule_id_ex_len), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = QMI_IPA_MAX_FILTERS_EX2_V01, + .elem_size = sizeof(uint32_t), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x19, + .offset = offsetof( + struct ipa_fltr_installed_notif_req_msg_v01, + rule_id_ex), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa3_fltr_installed_notif_resp_msg_data_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof( + struct ipa_fltr_installed_notif_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa3_enable_force_clear_datapath_req_msg_data_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x01, + .offset = offsetof( + struct ipa_enable_force_clear_datapath_req_msg_v01, + source_pipe_bitmask), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof( + struct ipa_enable_force_clear_datapath_req_msg_v01, + request_id), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_enable_force_clear_datapath_req_msg_v01, + throttle_source_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_enable_force_clear_datapath_req_msg_v01, + throttle_source), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof( + struct ipa_enable_force_clear_datapath_req_msg_v01, + source_pipe_bitmask_ext_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 4, + .elem_size = sizeof(uint32_t), + .array_type = STATIC_ARRAY, + .tlv_type = 0x11, + .offset = offsetof( + struct ipa_enable_force_clear_datapath_req_msg_v01, + source_pipe_bitmask_ext), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa3_enable_force_clear_datapath_resp_msg_data_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof( + struct ipa_enable_force_clear_datapath_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa3_disable_force_clear_datapath_req_msg_data_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x01, + .offset = offsetof( + struct ipa_disable_force_clear_datapath_req_msg_v01, + request_id), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info + ipa3_disable_force_clear_datapath_resp_msg_data_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof( + struct ipa_disable_force_clear_datapath_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa3_config_req_msg_data_v01_ei[] = { + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_config_req_msg_v01, + peripheral_type_valid), + }, + { + .data_type = QMI_SIGNED_4_BYTE_ENUM, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_config_req_msg_v01, + peripheral_type), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof( + struct ipa_config_req_msg_v01, + hw_deaggr_supported_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof( + struct ipa_config_req_msg_v01, + hw_deaggr_supported), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x12, + .offset = offsetof( + struct ipa_config_req_msg_v01, + max_aggr_frame_size_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x12, + .offset = offsetof( + struct ipa_config_req_msg_v01, + max_aggr_frame_size), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x13, + .offset = offsetof( + struct ipa_config_req_msg_v01, + ipa_ingress_pipe_mode_valid), + }, + { + .data_type = QMI_SIGNED_4_BYTE_ENUM, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x13, + .offset = offsetof( + struct ipa_config_req_msg_v01, + ipa_ingress_pipe_mode), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x14, + .offset = offsetof( + struct ipa_config_req_msg_v01, + peripheral_speed_info_valid), + }, + { + .data_type = QMI_SIGNED_4_BYTE_ENUM, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x14, + .offset = offsetof( + struct ipa_config_req_msg_v01, + peripheral_speed_info), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x15, + .offset = offsetof( + struct ipa_config_req_msg_v01, + dl_accumulation_time_limit_valid), + }, + { + .data_type = QMI_SIGNED_4_BYTE_ENUM, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x15, + .offset = offsetof( + struct ipa_config_req_msg_v01, + dl_accumulation_time_limit), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x16, + .offset = offsetof( + struct ipa_config_req_msg_v01, + dl_accumulation_pkt_limit_valid), + }, + { + .data_type = QMI_SIGNED_4_BYTE_ENUM, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x16, + .offset = offsetof( + struct ipa_config_req_msg_v01, + dl_accumulation_pkt_limit), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x17, + .offset = offsetof( + struct ipa_config_req_msg_v01, + dl_accumulation_byte_limit_valid), + }, + { + .data_type = QMI_SIGNED_4_BYTE_ENUM, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x17, + .offset = offsetof( + struct ipa_config_req_msg_v01, + dl_accumulation_byte_limit), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x18, + .offset = offsetof( + struct ipa_config_req_msg_v01, + ul_accumulation_time_limit_valid), + }, + { + .data_type = QMI_SIGNED_4_BYTE_ENUM, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x18, + .offset = offsetof( + struct ipa_config_req_msg_v01, + ul_accumulation_time_limit), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x19, + .offset = offsetof( + struct ipa_config_req_msg_v01, + hw_control_flags_valid), + }, + { + .data_type = QMI_SIGNED_4_BYTE_ENUM, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x19, + .offset = offsetof( + struct ipa_config_req_msg_v01, + hw_control_flags), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x1A, + .offset = offsetof( + struct ipa_config_req_msg_v01, + ul_msi_event_threshold_valid), + }, + { + .data_type = QMI_SIGNED_4_BYTE_ENUM, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x1A, + .offset = offsetof( + struct ipa_config_req_msg_v01, + ul_msi_event_threshold), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x1B, + .offset = offsetof( + struct ipa_config_req_msg_v01, + dl_msi_event_threshold_valid), + }, + { + .data_type = QMI_SIGNED_4_BYTE_ENUM, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x1B, + .offset = offsetof( + struct ipa_config_req_msg_v01, + dl_msi_event_threshold), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x1C, + .offset = offsetof( + struct ipa_config_req_msg_v01, + ul_fifo_size_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x1C, + .offset = offsetof( + struct ipa_config_req_msg_v01, + ul_fifo_size), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x1D, + .offset = offsetof( + struct ipa_config_req_msg_v01, + dl_fifo_size_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x1D, + .offset = offsetof( + struct ipa_config_req_msg_v01, + dl_fifo_size), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x1E, + .offset = offsetof( + struct ipa_config_req_msg_v01, + dl_buf_size_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x1E, + .offset = offsetof( + struct ipa_config_req_msg_v01, + dl_buf_size), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa3_config_resp_msg_data_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof( + struct ipa_config_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa3_get_data_stats_req_msg_data_v01_ei[] = { + { + .data_type = QMI_SIGNED_4_BYTE_ENUM, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x01, + .offset = offsetof( + struct ipa_get_data_stats_req_msg_v01, + ipa_stats_type), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_get_data_stats_req_msg_v01, + reset_stats_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_get_data_stats_req_msg_v01, + reset_stats), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +static struct qmi_elem_info ipa3_pipe_stats_info_type_data_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct ipa_pipe_stats_info_type_v01, + pipe_index), + }, + { + .data_type = QMI_UNSIGNED_8_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint64_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct ipa_pipe_stats_info_type_v01, + num_ipv4_packets), + }, + { + .data_type = QMI_UNSIGNED_8_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint64_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct ipa_pipe_stats_info_type_v01, + num_ipv4_bytes), + }, + { + .data_type = QMI_UNSIGNED_8_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint64_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct ipa_pipe_stats_info_type_v01, + num_ipv6_packets), + }, + { + .data_type = QMI_UNSIGNED_8_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint64_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct ipa_pipe_stats_info_type_v01, + num_ipv6_bytes), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +static struct qmi_elem_info ipa3_stats_type_filter_rule_data_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct + ipa_stats_type_filter_rule_v01, + filter_rule_index), + }, + { + .data_type = QMI_UNSIGNED_8_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint64_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct + ipa_stats_type_filter_rule_v01, + num_packets), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa3_get_data_stats_resp_msg_data_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof( + struct ipa_get_data_stats_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_get_data_stats_resp_msg_v01, + ipa_stats_type_valid), + }, + { + .data_type = QMI_SIGNED_4_BYTE_ENUM, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_get_data_stats_resp_msg_v01, + ipa_stats_type), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof( + struct ipa_get_data_stats_resp_msg_v01, + ul_src_pipe_stats_list_valid), + }, + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof( + struct ipa_get_data_stats_resp_msg_v01, + ul_src_pipe_stats_list_len), + }, + { + .data_type = QMI_STRUCT, + .elem_len = QMI_IPA_MAX_PIPES_V01, + .elem_size = sizeof(struct ipa_pipe_stats_info_type_v01), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x11, + .offset = offsetof( + struct ipa_get_data_stats_resp_msg_v01, + ul_src_pipe_stats_list), + .ei_array = ipa3_pipe_stats_info_type_data_v01_ei, + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x12, + .offset = offsetof( + struct ipa_get_data_stats_resp_msg_v01, + dl_dst_pipe_stats_list_valid), + }, + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x12, + .offset = offsetof( + struct ipa_get_data_stats_resp_msg_v01, + dl_dst_pipe_stats_list_len), + }, + { + .data_type = QMI_STRUCT, + .elem_len = QMI_IPA_MAX_PIPES_V01, + .elem_size = sizeof(struct ipa_pipe_stats_info_type_v01), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x12, + .offset = offsetof( + struct ipa_get_data_stats_resp_msg_v01, + dl_dst_pipe_stats_list), + .ei_array = ipa3_pipe_stats_info_type_data_v01_ei, + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x13, + .offset = offsetof( + struct ipa_get_data_stats_resp_msg_v01, + dl_filter_rule_stats_list_valid), + }, + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x13, + .offset = offsetof( + struct ipa_get_data_stats_resp_msg_v01, + dl_filter_rule_stats_list_len), + }, + { + .data_type = QMI_STRUCT, + .elem_len = QMI_IPA_MAX_FILTERS_V01, + .elem_size = sizeof(struct ipa_pipe_stats_info_type_v01), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x13, + .offset = offsetof( + struct ipa_get_data_stats_resp_msg_v01, + dl_filter_rule_stats_list), + .ei_array = ipa3_stats_type_filter_rule_data_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +static struct qmi_elem_info ipa3_apn_data_stats_info_type_data_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct + ipa_apn_data_stats_info_type_v01, + mux_id), + }, + { + .data_type = QMI_UNSIGNED_8_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint64_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct + ipa_apn_data_stats_info_type_v01, + num_ul_packets), + }, + { + .data_type = QMI_UNSIGNED_8_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint64_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct + ipa_apn_data_stats_info_type_v01, + num_ul_bytes), + }, + { + .data_type = QMI_UNSIGNED_8_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint64_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct + ipa_apn_data_stats_info_type_v01, + num_dl_packets), + }, + { + .data_type = QMI_UNSIGNED_8_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint64_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct + ipa_apn_data_stats_info_type_v01, + num_dl_bytes), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa3_get_apn_data_stats_req_msg_data_v01_ei[] = { + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_get_apn_data_stats_req_msg_v01, + mux_id_list_valid), + }, + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_get_apn_data_stats_req_msg_v01, + mux_id_list_len), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = QMI_IPA_MAX_APN_V01, + .elem_size = sizeof(uint32_t), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_get_apn_data_stats_req_msg_v01, + mux_id_list), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa3_get_apn_data_stats_resp_msg_data_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof( + struct ipa_get_apn_data_stats_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_get_apn_data_stats_resp_msg_v01, + apn_data_stats_list_valid), + }, + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_get_apn_data_stats_resp_msg_v01, + apn_data_stats_list_len), + }, + { + .data_type = QMI_STRUCT, + .elem_len = QMI_IPA_MAX_APN_V01, + .elem_size = sizeof(struct + ipa_apn_data_stats_info_type_v01), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_get_apn_data_stats_resp_msg_v01, + apn_data_stats_list), + .ei_array = ipa3_apn_data_stats_info_type_data_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +static struct qmi_elem_info ipa3_data_usage_quota_info_type_data_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct + ipa_data_usage_quota_info_type_v01, + mux_id), + }, + { + .data_type = QMI_UNSIGNED_8_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint64_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct + ipa_data_usage_quota_info_type_v01, + num_Mbytes), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa3_set_data_usage_quota_req_msg_data_v01_ei[] = { + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_set_data_usage_quota_req_msg_v01, + apn_quota_list_valid), + }, + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_set_data_usage_quota_req_msg_v01, + apn_quota_list_len), + }, + { + .data_type = QMI_STRUCT, + .elem_len = QMI_IPA_MAX_APN_V01, + .elem_size = sizeof(struct + ipa_data_usage_quota_info_type_v01), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_set_data_usage_quota_req_msg_v01, + apn_quota_list), + .ei_array = ipa3_data_usage_quota_info_type_data_v01_ei, + }, +#ifdef IPA_DATA_WARNING_QUOTA + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof( + struct ipa_set_data_usage_quota_req_msg_v01, + apn_warning_list_valid), + }, + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof( + struct ipa_set_data_usage_quota_req_msg_v01, + apn_warning_list_len), + }, + { + .data_type = QMI_STRUCT, + .elem_len = QMI_IPA_MAX_APN_V01, + .elem_size = sizeof(struct + ipa_data_usage_quota_info_type_v01), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x11, + .offset = offsetof( + struct ipa_set_data_usage_quota_req_msg_v01, + apn_warning_list), + .ei_array = ipa3_data_usage_quota_info_type_data_v01_ei, + }, +#endif + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa3_set_data_usage_quota_resp_msg_data_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof( + struct ipa_set_data_usage_quota_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa3_data_usage_quota_reached_ind_msg_data_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct + ipa_data_usage_quota_info_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x01, + .offset = offsetof( + struct ipa_data_usage_quota_reached_ind_msg_v01, + apn), + .ei_array = ipa3_data_usage_quota_info_type_data_v01_ei, + }, +#ifdef IPA_DATA_WARNING_QUOTA + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_data_usage_quota_reached_ind_msg_v01, + is_warning_limit_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_data_usage_quota_reached_ind_msg_v01, + is_warning_limit), + }, +#endif + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa3_stop_data_usage_quota_req_msg_data_v01_ei[] = { +#ifdef IPA_DATA_WARNING_QUOTA + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_stop_data_usage_quota_req_msg_v01, + is_quota_limit_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_stop_data_usage_quota_req_msg_v01, + is_quota_limit), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof( + struct ipa_stop_data_usage_quota_req_msg_v01, + is_warning_limit_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof( + struct ipa_stop_data_usage_quota_req_msg_v01, + is_warning_limit), + }, +#endif + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa3_stop_data_usage_quota_resp_msg_data_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof( + struct ipa_stop_data_usage_quota_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa3_install_fltr_rule_req_ex_msg_data_v01_ei[] = { + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_install_fltr_rule_req_ex_msg_v01, + filter_spec_ex_list_valid), + }, + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_install_fltr_rule_req_ex_msg_v01, + filter_spec_ex_list_len), + }, + { + .data_type = QMI_STRUCT, + .elem_len = QMI_IPA_MAX_FILTERS_EX_V01, + .elem_size = sizeof(struct + ipa_filter_spec_ex_type_v01), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_install_fltr_rule_req_ex_msg_v01, + filter_spec_ex_list), + .ei_array = ipa_filter_spec_ex_type_data_v01_ei, + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof( + struct ipa_install_fltr_rule_req_ex_msg_v01, + source_pipe_index_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof( + struct ipa_install_fltr_rule_req_ex_msg_v01, + source_pipe_index), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x12, + .offset = offsetof( + struct ipa_install_fltr_rule_req_ex_msg_v01, + num_ipv4_filters_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x12, + .offset = offsetof( + struct ipa_install_fltr_rule_req_ex_msg_v01, + num_ipv4_filters), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x13, + .offset = offsetof( + struct ipa_install_fltr_rule_req_ex_msg_v01, + num_ipv6_filters_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x13, + .offset = offsetof( + struct ipa_install_fltr_rule_req_ex_msg_v01, + num_ipv6_filters), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x14, + .offset = offsetof( + struct ipa_install_fltr_rule_req_ex_msg_v01, + xlat_filter_indices_list_valid), + }, + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x14, + .offset = offsetof( + struct ipa_install_fltr_rule_req_ex_msg_v01, + xlat_filter_indices_list_len), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = QMI_IPA_MAX_FILTERS_EX_V01, + .elem_size = sizeof(uint32_t), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x14, + .offset = offsetof( + struct ipa_install_fltr_rule_req_ex_msg_v01, + xlat_filter_indices_list), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x15, + .offset = offsetof( + struct ipa_install_fltr_rule_req_ex_msg_v01, + filter_spec_ex2_list_valid), + }, + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x15, + .offset = offsetof( + struct ipa_install_fltr_rule_req_ex_msg_v01, + filter_spec_ex2_list_len), + }, + { + .data_type = QMI_STRUCT, + .elem_len = QMI_IPA_MAX_FILTERS_V01, + .elem_size = sizeof(struct ipa_filter_spec_ex2_type_v01), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x15, + .offset = offsetof( + struct ipa_install_fltr_rule_req_ex_msg_v01, + filter_spec_ex2_list), + .ei_array = ipa_filter_spec_ex2_type_v01_ei, + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x16, + .offset = offsetof( + struct ipa_install_fltr_rule_req_ex_msg_v01, + ul_firewall_indices_list_valid), + }, + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x16, + .offset = offsetof( + struct ipa_install_fltr_rule_req_ex_msg_v01, + ul_firewall_indices_list_len), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = QMI_IPA_MAX_FILTERS_V01, + .elem_size = sizeof(uint32_t), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x16, + .offset = offsetof( + struct ipa_install_fltr_rule_req_ex_msg_v01, + ul_firewall_indices_list), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa3_install_fltr_rule_resp_ex_msg_data_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof( + struct ipa_install_fltr_rule_resp_ex_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_install_fltr_rule_resp_ex_msg_v01, + rule_id_valid), + }, + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_install_fltr_rule_resp_ex_msg_v01, + rule_id_len), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = QMI_IPA_MAX_FILTERS_EX_V01, + .elem_size = sizeof(uint32_t), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_install_fltr_rule_resp_ex_msg_v01, + rule_id), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa3_per_client_stats_info_type_data_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof( + struct ipa_per_client_stats_info_type_v01, + client_id), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof( + struct ipa_per_client_stats_info_type_v01, + src_pipe_id), + }, + { + .data_type = QMI_UNSIGNED_8_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint64_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof( + struct ipa_per_client_stats_info_type_v01, + num_ul_ipv4_bytes), + + }, + { + .data_type = QMI_UNSIGNED_8_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint64_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof( + struct ipa_per_client_stats_info_type_v01, + num_ul_ipv6_bytes), + + }, + { + .data_type = QMI_UNSIGNED_8_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint64_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof( + struct ipa_per_client_stats_info_type_v01, + num_dl_ipv4_bytes), + + }, + { + .data_type = QMI_UNSIGNED_8_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint64_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof( + struct ipa_per_client_stats_info_type_v01, + num_dl_ipv6_bytes), + + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof( + struct ipa_per_client_stats_info_type_v01, + num_ul_ipv4_pkts), + + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof( + struct ipa_per_client_stats_info_type_v01, + num_ul_ipv6_pkts), + + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof( + struct ipa_per_client_stats_info_type_v01, + num_dl_ipv4_pkts), + + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof( + struct ipa_per_client_stats_info_type_v01, + num_dl_ipv6_pkts), + + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa3_ul_firewall_rule_type_data_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof( + struct ipa_ul_firewall_rule_type_v01, + ip_type), + }, + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct ipa_filter_rule_type_v01), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct ipa_ul_firewall_rule_type_v01, + filter_rule), + .ei_array = ipa3_filter_rule_type_data_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa3_ul_firewall_config_result_type_data_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof( + struct ipa_ul_firewall_config_result_type_v01, + is_success), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof( + struct ipa_ul_firewall_config_result_type_v01, + mux_id), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa3_enable_per_client_stats_req_msg_data_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x01, + .offset = offsetof(struct + ipa_enable_per_client_stats_req_msg_v01, + enable_per_client_stats), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa3_enable_per_client_stats_resp_msg_data_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof( + struct ipa_enable_per_client_stats_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa3_get_stats_per_client_req_msg_data_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x01, + .offset = offsetof( + struct ipa_get_stats_per_client_req_msg_v01, + client_id), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof( + struct ipa_get_stats_per_client_req_msg_v01, + src_pipe_id), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_get_stats_per_client_req_msg_v01, + reset_stats_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_get_stats_per_client_req_msg_v01, + reset_stats), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa3_get_stats_per_client_resp_msg_data_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof( + struct ipa_get_stats_per_client_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_get_stats_per_client_resp_msg_v01, + per_client_stats_list_valid), + }, + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_get_stats_per_client_resp_msg_v01, + per_client_stats_list_len), + }, + { + .data_type = QMI_STRUCT, + .elem_len = QMI_IPA_MAX_PER_CLIENTS_V01, + .elem_size = + sizeof(struct ipa_per_client_stats_info_type_v01), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_get_stats_per_client_resp_msg_v01, + per_client_stats_list), + .ei_array = + ipa3_per_client_stats_info_type_data_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa3_configure_ul_firewall_rules_req_msg_data_v01_ei[] = { + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x1, + .offset = offsetof( + struct ipa_configure_ul_firewall_rules_req_msg_v01, + firewall_rules_list_len), + }, + { + .data_type = QMI_STRUCT, + .elem_len = QMI_IPA_MAX_UL_FIREWALL_RULES_V01, + .elem_size = sizeof(struct ipa_ul_firewall_rule_type_v01), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x1, + .offset = offsetof( + struct ipa_configure_ul_firewall_rules_req_msg_v01, + firewall_rules_list), + .ei_array = + ipa3_ul_firewall_rule_type_data_v01_ei, + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x2, + .offset = offsetof( + struct ipa_configure_ul_firewall_rules_req_msg_v01, + mux_id), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_configure_ul_firewall_rules_req_msg_v01, + disable_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_configure_ul_firewall_rules_req_msg_v01, + disable), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof( + struct ipa_configure_ul_firewall_rules_req_msg_v01, + are_blacklist_filters_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof( + struct ipa_configure_ul_firewall_rules_req_msg_v01, + are_blacklist_filters), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa3_configure_ul_firewall_rules_resp_msg_data_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof( + struct ipa_configure_ul_firewall_rules_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa3_configure_ul_firewall_rules_ind_msg_data_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof( + struct ipa_ul_firewall_config_result_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x01, + .offset = offsetof( + struct ipa_configure_ul_firewall_rules_ind_msg_v01, + result), + .ei_array = + ipa3_ul_firewall_config_result_type_data_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +static struct qmi_elem_info ipa_mhi_ch_init_info_type_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_mhi_ch_init_info_type_v01, + ch_id), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_mhi_ch_init_info_type_v01, + er_id), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_mhi_ch_init_info_type_v01, + ch_doorbell_addr), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_mhi_ch_init_info_type_v01, + er_doorbell_addr), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_mhi_ch_init_info_type_v01, + direction_type), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +static struct qmi_elem_info ipa_mhi_smmu_info_type_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_8_BYTE, + .elem_len = 1, + .elem_size = sizeof(u64), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_mhi_smmu_info_type_v01, + iova_ctl_base_addr), + }, + { + .data_type = QMI_UNSIGNED_8_BYTE, + .elem_len = 1, + .elem_size = sizeof(u64), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_mhi_smmu_info_type_v01, + iova_ctl_size), + }, + { + .data_type = QMI_UNSIGNED_8_BYTE, + .elem_len = 1, + .elem_size = sizeof(u64), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_mhi_smmu_info_type_v01, + iova_data_base_addr), + }, + { + .data_type = QMI_UNSIGNED_8_BYTE, + .elem_len = 1, + .elem_size = sizeof(u64), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_mhi_smmu_info_type_v01, + iova_data_size), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + + +struct qmi_elem_info ipa_mhi_ready_indication_msg_v01_ei[] = { + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x01, + .offset = offsetof(struct ipa_mhi_ready_indication_msg_v01, + ch_info_arr_len), + }, + { + .data_type = QMI_STRUCT, + .elem_len = QMI_IPA_REMOTE_MHI_CHANNELS_NUM_MAX_V01, + .elem_size = sizeof(struct ipa_mhi_ch_init_info_type_v01), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x01, + .offset = offsetof(struct ipa_mhi_ready_indication_msg_v01, + ch_info_arr), + .ei_array = ipa_mhi_ch_init_info_type_v01_ei, + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct ipa_mhi_ready_indication_msg_v01, + smmu_info_valid), + }, + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct ipa_mhi_smmu_info_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct ipa_mhi_ready_indication_msg_v01, + smmu_info), + .ei_array = ipa_mhi_smmu_info_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa_mhi_mem_addr_info_type_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_8_BYTE, + .elem_len = 1, + .elem_size = sizeof(u64), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_mhi_mem_addr_info_type_v01, + pa), + }, + { + .data_type = QMI_UNSIGNED_8_BYTE, + .elem_len = 1, + .elem_size = sizeof(u64), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_mhi_mem_addr_info_type_v01, + iova), + }, + { + .data_type = QMI_UNSIGNED_8_BYTE, + .elem_len = 1, + .elem_size = sizeof(u64), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_mhi_mem_addr_info_type_v01, + size), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa_mhi_tr_info_type_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_mhi_tr_info_type_v01, + ch_id), + }, + { + .data_type = QMI_UNSIGNED_2_BYTE, + .elem_len = 1, + .elem_size = sizeof(u16), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_mhi_tr_info_type_v01, + poll_cfg), + }, + { + .data_type = QMI_SIGNED_4_BYTE_ENUM, + .elem_len = 1, + .elem_size = sizeof(enum ipa_mhi_brst_mode_enum_v01), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_mhi_tr_info_type_v01, + brst_mode_type), + }, + { + .data_type = QMI_UNSIGNED_8_BYTE, + .elem_len = 1, + .elem_size = sizeof(u64), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_mhi_tr_info_type_v01, + ring_iova), + }, + { + .data_type = QMI_UNSIGNED_8_BYTE, + .elem_len = 1, + .elem_size = sizeof(u64), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_mhi_tr_info_type_v01, + ring_len), + }, + { + .data_type = QMI_UNSIGNED_8_BYTE, + .elem_len = 1, + .elem_size = sizeof(u64), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_mhi_tr_info_type_v01, + rp), + }, + { + .data_type = QMI_UNSIGNED_8_BYTE, + .elem_len = 1, + .elem_size = sizeof(u64), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_mhi_tr_info_type_v01, + wp), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa_mhi_er_info_type_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_mhi_er_info_type_v01, + er_id), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_mhi_er_info_type_v01, + intmod_cycles), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_mhi_er_info_type_v01, + intmod_count), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_mhi_er_info_type_v01, + msi_addr), + }, + { + .data_type = QMI_UNSIGNED_8_BYTE, + .elem_len = 1, + .elem_size = sizeof(u64), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_mhi_er_info_type_v01, + ring_iova), + }, + { + .data_type = QMI_UNSIGNED_8_BYTE, + .elem_len = 1, + .elem_size = sizeof(u64), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_mhi_er_info_type_v01, + ring_len), + }, + { + .data_type = QMI_UNSIGNED_8_BYTE, + .elem_len = 1, + .elem_size = sizeof(u64), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_mhi_er_info_type_v01, + rp), + }, + { + .data_type = QMI_UNSIGNED_8_BYTE, + .elem_len = 1, + .elem_size = sizeof(u64), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_mhi_er_info_type_v01, + wp), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa_mhi_alloc_channel_req_msg_v01_ei[] = { + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x01, + .offset = offsetof(struct ipa_mhi_alloc_channel_req_msg_v01, + tr_info_arr_len), + }, + { + .data_type = QMI_STRUCT, + .elem_len = QMI_IPA_REMOTE_MHI_CHANNELS_NUM_MAX_V01, + .elem_size = sizeof(struct ipa_mhi_tr_info_type_v01), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x01, + .offset = offsetof(struct ipa_mhi_alloc_channel_req_msg_v01, + tr_info_arr), + .ei_array = ipa_mhi_tr_info_type_v01_ei, + }, + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct ipa_mhi_alloc_channel_req_msg_v01, + er_info_arr_len), + }, + { + .data_type = QMI_STRUCT, + .elem_len = QMI_IPA_REMOTE_MHI_CHANNELS_NUM_MAX_V01, + .elem_size = sizeof(struct ipa_mhi_er_info_type_v01), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct ipa_mhi_alloc_channel_req_msg_v01, + er_info_arr), + .ei_array = ipa_mhi_er_info_type_v01_ei, + }, + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x03, + .offset = offsetof(struct ipa_mhi_alloc_channel_req_msg_v01, + ctrl_addr_map_info_len), + }, + { + .data_type = QMI_STRUCT, + .elem_len = QMI_IPA_REMOTE_MHI_MEMORY_MAPPING_NUM_MAX_V01, + .elem_size = sizeof(struct ipa_mhi_mem_addr_info_type_v01), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x03, + .offset = offsetof(struct ipa_mhi_alloc_channel_req_msg_v01, + ctrl_addr_map_info), + .ei_array = ipa_mhi_mem_addr_info_type_v01_ei, + }, + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x04, + .offset = offsetof(struct ipa_mhi_alloc_channel_req_msg_v01, + data_addr_map_info_len), + }, + { + .data_type = QMI_STRUCT, + .elem_len = QMI_IPA_REMOTE_MHI_MEMORY_MAPPING_NUM_MAX_V01, + .elem_size = sizeof(struct ipa_mhi_mem_addr_info_type_v01), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x04, + .offset = offsetof(struct ipa_mhi_alloc_channel_req_msg_v01, + data_addr_map_info), + .ei_array = ipa_mhi_mem_addr_info_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa_mhi_ch_alloc_resp_type_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_mhi_ch_alloc_resp_type_v01, + ch_id), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_mhi_ch_alloc_resp_type_v01, + is_success), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa_mhi_alloc_channel_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct ipa_mhi_alloc_channel_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct ipa_mhi_alloc_channel_resp_msg_v01, + alloc_resp_arr_valid), + }, + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct ipa_mhi_alloc_channel_resp_msg_v01, + alloc_resp_arr_len), + }, + { + .data_type = QMI_STRUCT, + .elem_len = QMI_IPA_REMOTE_MHI_CHANNELS_NUM_MAX_V01, + .elem_size = sizeof(struct ipa_mhi_ch_alloc_resp_type_v01), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct ipa_mhi_alloc_channel_resp_msg_v01, + alloc_resp_arr), + .ei_array = ipa_mhi_ch_alloc_resp_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa_mhi_clk_vote_req_msg_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x01, + .offset = offsetof(struct ipa_mhi_clk_vote_req_msg_v01, + mhi_vote), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_mhi_clk_vote_req_msg_v01, + tput_value_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_mhi_clk_vote_req_msg_v01, + tput_value), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof( + struct ipa_mhi_clk_vote_req_msg_v01, + clk_rate_valid), + }, + { + .data_type = QMI_SIGNED_4_BYTE_ENUM, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof( + struct ipa_mhi_clk_vote_req_msg_v01, + clk_rate), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa_mhi_clk_vote_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct ipa_mhi_clk_vote_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa_mhi_cleanup_req_msg_v01_ei[] = { + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct ipa_mhi_cleanup_req_msg_v01, + cleanup_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct ipa_mhi_cleanup_req_msg_v01, + cleanup), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa_mhi_cleanup_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct ipa_mhi_cleanup_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +static struct qmi_elem_info ipa_ep_id_type_v01_ei[] = { + { + .data_type = QMI_SIGNED_4_BYTE_ENUM, + .elem_len = 1, + .elem_size = sizeof(enum ipa_ic_type_enum_v01), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_ep_id_type_v01, + ic_type), + }, + { + .data_type = QMI_SIGNED_4_BYTE_ENUM, + .elem_len = 1, + .elem_size = sizeof(enum ipa_ep_desc_type_enum_v01), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_ep_id_type_v01, + ep_type), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_ep_id_type_v01, + ep_id), + }, + { + .data_type = QMI_SIGNED_4_BYTE_ENUM, + .elem_len = 1, + .elem_size = sizeof(enum ipa_ep_status_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct ipa_ep_id_type_v01, + ep_status), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa_endp_desc_indication_msg_v01_ei[] = { + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_endp_desc_indication_msg_v01, + ep_info_valid), + }, + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_endp_desc_indication_msg_v01, + ep_info_len), + }, + { + .data_type = QMI_STRUCT, + .elem_len = QMI_IPA_ENDP_DESC_NUM_MAX_V01, + .elem_size = sizeof(struct ipa_ep_id_type_v01), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_endp_desc_indication_msg_v01, + ep_info), + .ei_array = ipa_ep_id_type_v01_ei, + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof( + struct ipa_endp_desc_indication_msg_v01, + num_eps_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof( + struct ipa_endp_desc_indication_msg_v01, + num_eps), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +static struct qmi_elem_info ipa_mhi_prime_aggr_info_type_v01_ei[] = { + { + .data_type = QMI_SIGNED_4_BYTE_ENUM, + .elem_len = 1, + .elem_size = sizeof(enum ipa_ic_type_enum_v01), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof( + struct ipa_mhi_prime_aggr_info_type_v01, + ic_type), + }, + { + .data_type = QMI_SIGNED_4_BYTE_ENUM, + .elem_len = 1, + .elem_size = sizeof(enum ipa_ep_desc_type_enum_v01), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof( + struct ipa_mhi_prime_aggr_info_type_v01, + ep_type), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof( + struct ipa_mhi_prime_aggr_info_type_v01, + bytes_count), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof( + struct ipa_mhi_prime_aggr_info_type_v01, + pkt_count), + }, + { + .data_type = QMI_SIGNED_4_BYTE_ENUM, + .elem_len = 1, + .elem_size = sizeof(enum ipa_aggr_enum_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof( + struct ipa_mhi_prime_aggr_info_type_v01, + aggr_type), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa_mhi_prime_aggr_info_req_msg_v01_ei[] = { + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_mhi_prime_aggr_info_req_msg_v01, + aggr_info_valid), + }, + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_mhi_prime_aggr_info_req_msg_v01, + aggr_info_len), + }, + { + .data_type = QMI_STRUCT, + .elem_len = QMI_IPA_ENDP_DESC_NUM_MAX_V01, + .elem_size = sizeof( + struct ipa_mhi_prime_aggr_info_type_v01), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_mhi_prime_aggr_info_req_msg_v01, + aggr_info), + .ei_array = ipa_mhi_prime_aggr_info_type_v01_ei, + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof( + struct ipa_mhi_prime_aggr_info_req_msg_v01, + num_eps_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof( + struct ipa_mhi_prime_aggr_info_req_msg_v01, + num_eps), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa_mhi_prime_aggr_info_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof( + struct ipa_mhi_prime_aggr_info_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa_add_offload_connection_req_msg_v01_ei[] = { + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_add_offload_connection_req_msg_v01, + num_ipv4_filters_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_add_offload_connection_req_msg_v01, + num_ipv4_filters), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof( + struct ipa_add_offload_connection_req_msg_v01, + num_ipv6_filters_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof( + struct ipa_add_offload_connection_req_msg_v01, + num_ipv6_filters), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x12, + .offset = offsetof( + struct ipa_add_offload_connection_req_msg_v01, + xlat_filter_indices_list_valid), + }, + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x12, + .offset = offsetof( + struct ipa_add_offload_connection_req_msg_v01, + xlat_filter_indices_list_len), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = QMI_IPA_MAX_FILTERS_V01, + .elem_size = sizeof(u32), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x12, + .offset = offsetof( + struct ipa_add_offload_connection_req_msg_v01, + xlat_filter_indices_list), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x13, + .offset = offsetof( + struct ipa_add_offload_connection_req_msg_v01, + filter_spec_ex2_list_valid), + }, + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x13, + .offset = offsetof( + struct ipa_add_offload_connection_req_msg_v01, + filter_spec_ex2_list_len), + }, + { + .data_type = QMI_STRUCT, + .elem_len = QMI_IPA_MAX_FILTERS_V01, + .elem_size = sizeof(struct ipa_filter_spec_ex2_type_v01), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x13, + .offset = offsetof( + struct ipa_add_offload_connection_req_msg_v01, + filter_spec_ex2_list), + .ei_array = ipa_filter_spec_ex2_type_v01_ei, + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x14, + .offset = offsetof( + struct ipa_add_offload_connection_req_msg_v01, + embedded_call_mux_id_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x14, + .offset = offsetof( + struct ipa_add_offload_connection_req_msg_v01, + embedded_call_mux_id), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x15, + .offset = offsetof( + struct ipa_add_offload_connection_req_msg_v01, + default_mhi_path_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x15, + .offset = offsetof( + struct ipa_add_offload_connection_req_msg_v01, + default_mhi_path), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa_add_offload_connection_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof( + struct ipa_add_offload_connection_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_add_offload_connection_resp_msg_v01, + filter_handle_list_valid), + }, + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_add_offload_connection_resp_msg_v01, + filter_handle_list_len), + }, + { + .data_type = QMI_STRUCT, + .elem_len = QMI_IPA_MAX_FILTERS_V01, + .elem_size = sizeof( + struct ipa_filter_rule_identifier_to_handle_map_v01), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_add_offload_connection_resp_msg_v01, + filter_handle_list), + .ei_array = + ipa3_filter_rule_identifier_to_handle_map_data_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa_remove_offload_connection_req_msg_v01_ei[] = { + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_remove_offload_connection_req_msg_v01, + filter_handle_list_valid), + }, + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_remove_offload_connection_req_msg_v01, + filter_handle_list_len), + }, + { + .data_type = QMI_STRUCT, + .elem_len = QMI_IPA_MAX_FILTERS_V01, + .elem_size = sizeof( + struct ipa_filter_rule_identifier_to_handle_map_v01), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_remove_offload_connection_req_msg_v01, + filter_handle_list), + .ei_array = + ipa3_filter_rule_identifier_to_handle_map_data_v01_ei, + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof( + struct ipa_remove_offload_connection_req_msg_v01, + clean_all_rules_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof( + struct ipa_remove_offload_connection_req_msg_v01, + clean_all_rules), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa_remove_offload_connection_resp_msg_v01_ei[] = { + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof( + struct ipa_remove_offload_connection_resp_msg_v01, + resp_valid), + }, + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof( + struct ipa_remove_offload_connection_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa_bw_change_ind_msg_v01_ei[] = { + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct ipa_bw_change_ind_msg_v01, + peak_bw_ul_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct ipa_bw_change_ind_msg_v01, + peak_bw_ul), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof(struct ipa_bw_change_ind_msg_v01, + peak_bw_dl_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof(struct ipa_bw_change_ind_msg_v01, + peak_bw_dl), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + + }, +}; + +struct qmi_elem_info ipa_move_nat_req_msg_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x01, + .offset = offsetof( + struct ipa_move_nat_req_msg_v01, + nat_move_direction), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa_move_nat_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof( + struct ipa_move_nat_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa_wlan_opt_dp_rsrv_filter_req_msg_data_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x01, + .offset = offsetof( + struct ipa_wlan_opt_dp_rsrv_filter_req_msg_v01, + num_filters), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof( + struct ipa_wlan_opt_dp_rsrv_filter_req_msg_v01, + timeout_val_ms), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x03, + .offset = offsetof( + struct ipa_wlan_opt_dp_rsrv_filter_req_msg_v01, + q6_rtng_table_index), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa_wlan_opt_dp_rsrv_filter_resp_msg_data_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof( + struct ipa_wlan_opt_dp_rsrv_filter_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa_wlan_opt_dp_rsrv_filter_complt_ind_msg_data_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof( + struct ipa_wlan_opt_dp_rsrv_filter_complt_ind_msg_v01, + rsrv_filter_status), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ip_hdr_v4_address_info_data_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct ip_hdr_v4_address_info_v01, + source), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof(struct ip_hdr_v4_address_info_v01, + dest), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ip_hdr_v6_address_info_data_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = QMI_IPA_IPV6_WORD_ADDR_LEN_V01, + .elem_size = sizeof(uint32_t), + .array_type = STATIC_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof( + struct ip_hdr_v6_address_info_v01, + source), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = QMI_IPA_IPV6_WORD_ADDR_LEN_V01, + .elem_size = sizeof(uint32_t), + .array_type = STATIC_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + .offset = offsetof( + struct ip_hdr_v6_address_info_v01, + dest), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + + +struct qmi_elem_info ipa_wlan_opt_dp_add_filter_req_msg_data_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x01, + .offset = offsetof( + struct ipa_wlan_opt_dp_add_filter_req_msg_v01, + filter_idx), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof( + struct ipa_wlan_opt_dp_add_filter_req_msg_v01, + ip_type), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_wlan_opt_dp_add_filter_req_msg_v01, + v4_addr_valid), + }, + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct ip_hdr_v4_address_info_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct ipa_wlan_opt_dp_add_filter_req_msg_v01, + v4_addr), + .ei_array = ip_hdr_v4_address_info_data_v01_ei, + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof( + struct ipa_wlan_opt_dp_add_filter_req_msg_v01, + v6_addr_valid), + }, + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct ip_hdr_v6_address_info_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof(struct ipa_wlan_opt_dp_add_filter_req_msg_v01, + v6_addr), + .ei_array = ip_hdr_v6_address_info_data_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa_wlan_opt_dp_add_filter_resp_msg_data_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof( + struct ipa_wlan_opt_dp_add_filter_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa_wlan_opt_dp_add_filter_complt_ind_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof( + struct ipa_wlan_opt_dp_add_filter_complt_ind_msg_v01, + filter_add_status), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x03, + .offset = offsetof( + struct ipa_wlan_opt_dp_add_filter_complt_ind_msg_v01, + filter_idx), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_wlan_opt_dp_add_filter_complt_ind_msg_v01, + filter_handle_valid), + }, + + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_wlan_opt_dp_add_filter_complt_ind_msg_v01, + filter_handle), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa_wlan_opt_dp_remove_filter_req_msg_data_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x01, + .offset = offsetof( + struct ipa_wlan_opt_dp_remove_filter_req_msg_v01, + filter_idx), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof( + struct ipa_wlan_opt_dp_remove_filter_req_msg_v01, + filter_handle), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa_wlan_opt_dp_remove_filter_resp_msg_data_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof( + struct ipa_wlan_opt_dp_remove_filter_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa_wlan_opt_dp_remove_filter_complt_ind_msg_data_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof( + struct ipa_wlan_opt_dp_remove_filter_complt_ind_msg_v01, + filter_removal_status), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x03, + .offset = offsetof( + struct ipa_wlan_opt_dp_remove_filter_complt_ind_msg_v01, + filter_idx), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa_wlan_opt_dp_remove_all_filter_req_msg_data_v01_ei[] = { + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_wlan_opt_dp_remove_all_filter_req_msg_v01, + reserved_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof( + struct ipa_wlan_opt_dp_remove_all_filter_req_msg_v01, + reserved), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa_wlan_opt_dp_remove_all_filter_resp_msg_data_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof( + struct ipa_wlan_opt_dp_remove_all_filter_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa_wlan_opt_dp_remove_all_filter_complt_ind_msg_data_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof( + struct ipa_wlan_opt_dp_remove_all_filter_complt_ind_msg_v01, + filter_removal_all_status), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa_wlan_opt_dp_set_wlan_per_info_req_msg_data_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x01, + .offset = offsetof( + struct ipa_wlan_opt_dp_set_wlan_per_info_req_msg_v01, + src_wlan_endp_id), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof( + struct ipa_wlan_opt_dp_set_wlan_per_info_req_msg_v01, + dest_wlan_endp_id), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x03, + .offset = offsetof( + struct ipa_wlan_opt_dp_set_wlan_per_info_req_msg_v01, + dest_apps_endp_id), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x04, + .offset = offsetof( + struct ipa_wlan_opt_dp_set_wlan_per_info_req_msg_v01, + hdr_len), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x05, + .offset = offsetof( + struct ipa_wlan_opt_dp_set_wlan_per_info_req_msg_v01, + eth_hdr_offset), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 64, + .elem_size = sizeof(uint8_t), + .array_type = STATIC_ARRAY, + .tlv_type = 0x06, + .offset = offsetof( + struct ipa_wlan_opt_dp_set_wlan_per_info_req_msg_v01, + hdr_info), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ipa_wlan_opt_dp_set_wlan_per_info_resp_msg_data_v01[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof( + struct ipa_wlan_opt_dp_set_wlan_per_info_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_rt.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_rt.c new file mode 100644 index 0000000000..add05d6dca --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_rt.c @@ -0,0 +1,2622 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include "ipa_i.h" +#include "ipahal.h" +#include "ipahal_fltrt.h" + +#define IPA_RT_INDEX_BITMAP_SIZE (32) +#define IPA_RT_STATUS_OF_ADD_FAILED (-1) +#define IPA_RT_STATUS_OF_DEL_FAILED (-1) +#define IPA_RT_STATUS_OF_MDFY_FAILED (-1) + +#define IPA_RT_MAX_NUM_OF_COMMIT_TABLES_CMD_DESC 6 + +#define IPA_RT_GET_RULE_TYPE(__entry) \ + ( \ + ((__entry)->rule.hashable) ? \ + (IPA_RULE_HASHABLE) : (IPA_RULE_NON_HASHABLE) \ + ) + +/** + * ipa_generate_rt_hw_rule() - Generated the RT H/W single rule + * This func will do the preparation core driver work and then calls + * the HAL layer for the real work. + * @ip: the ip address family type + * @entry: routing entry + * @buf: output buffer, buf == NULL means + * caller wants to know the size of the rule as seen + * by HW so they did not pass a valid buffer, we will use a + * scratch buffer instead. + * With this scheme we are going to + * generate the rule twice, once to know size using scratch + * buffer and second to write the rule to the actual caller + * supplied buffer which is of required size + * + * Returns: 0 on success, negative on failure + * + * caller needs to hold any needed locks to ensure integrity + */ +static int ipa_generate_rt_hw_rule(enum ipa_ip_type ip, + struct ipa3_rt_entry *entry, u8 *buf) +{ + struct ipahal_rt_rule_gen_params gen_params; + struct ipa3_hdr_entry *hdr_entry; + struct ipa3_hdr_proc_ctx_entry *hdr_proc_entry; + int res = 0; + + memset(&gen_params, 0, sizeof(gen_params)); + + if (entry->rule.hashable && + entry->rule.attrib.attrib_mask & IPA_FLT_IS_PURE_ACK) { + IPAERR_RL("PURE_ACK rule atrb used with hash rule\n"); + WARN_ON_RATELIMIT_IPA(1); + return -EPERM; + } + + gen_params.ipt = ip; + gen_params.dst_pipe_idx = ipa_get_ep_mapping(entry->rule.dst); + if (gen_params.dst_pipe_idx == -1) { + IPAERR_RL("Wrong destination pipe specified in RT rule\n"); + WARN_ON_RATELIMIT_IPA(1); + return -EPERM; + } + if (!IPA_CLIENT_IS_CONS(entry->rule.dst)) { + IPAERR_RL("No RT rule on IPA_client_producer pipe.\n"); + IPAERR_RL("pipe_idx: %d dst_pipe: %d\n", + gen_params.dst_pipe_idx, entry->rule.dst); + WARN_ON_RATELIMIT_IPA(1); + return -EPERM; + } + + /* Adding check to confirm still + * header entry present in header table or not + */ + + if (entry->hdr) { + hdr_entry = ipa3_id_find(entry->rule.hdr_hdl); + if (!hdr_entry || (hdr_entry->cookie != IPA_HDR_COOKIE) || + ipa3_check_idr_if_freed(entry->hdr)) { + IPAERR_RL("Header entry already deleted\n"); + return -EPERM; + } + } else if (entry->proc_ctx) { + hdr_proc_entry = ipa3_id_find(entry->rule.hdr_proc_ctx_hdl); + if (!hdr_proc_entry || + (hdr_proc_entry->cookie != IPA_PROC_HDR_COOKIE) || + ipa3_check_idr_if_freed(entry->proc_ctx)) { + IPAERR_RL("Proc header entry already deleted\n"); + return -EPERM; + } + } + + if (entry->proc_ctx) { + struct ipa3_hdr_proc_ctx_entry *proc_ctx; + + proc_ctx = (entry->proc_ctx) ? : entry->hdr->proc_ctx; + if ((proc_ctx == NULL) || + ipa3_check_idr_if_freed(proc_ctx) || + (proc_ctx->cookie != IPA_PROC_HDR_COOKIE)) { + gen_params.hdr_type = IPAHAL_RT_RULE_HDR_NONE; + gen_params.hdr_ofst = 0; + } else { + gen_params.hdr_lcl = ipa3_ctx->hdr_proc_ctx_tbl_lcl; + gen_params.hdr_type = IPAHAL_RT_RULE_HDR_PROC_CTX; + gen_params.hdr_ofst = proc_ctx->offset_entry->offset + + ipa3_ctx->hdr_proc_ctx_tbl.start_offset; + } + } else if ((entry->hdr != NULL) && + (entry->hdr->cookie == IPA_HDR_COOKIE)) { + gen_params.hdr_type = IPAHAL_RT_RULE_HDR_RAW; + gen_params.hdr_ofst = entry->hdr->offset_entry->offset; + gen_params.hdr_ofst += entry->hdr->is_lcl ? IPA_MEM_PART(modem_hdr_size) : 0; + gen_params.hdr_lcl = entry->hdr->is_lcl; + } else { + gen_params.hdr_type = IPAHAL_RT_RULE_HDR_NONE; + gen_params.hdr_ofst = 0; + } + + gen_params.priority = entry->prio; + gen_params.id = entry->rule_id; + gen_params.rule = (const struct ipa_rt_rule_i *)&entry->rule; + gen_params.cnt_idx = entry->cnt_idx; + + res = ipahal_rt_generate_hw_rule(&gen_params, &entry->hw_len, buf); + if (res) + IPAERR("failed to generate rt h/w rule\n"); + + return res; +} + +/** + * ipa_translate_rt_tbl_to_hw_fmt() - translate the routing driver structures + * (rules and tables) to HW format and fill it in the given buffers + * @ip: the ip address family type + * @rlt: the type of the rules to translate (hashable or non-hashable) + * @base: the rules body buffer to be filled + * @hdr: the rules header (addresses/offsets) buffer to be filled + * @body_ofst: the offset of the rules body from the rules header at + * ipa sram (for local body usage) + * @apps_start_idx: the first rt table index of apps tables + * + * Returns: 0 on success, negative on failure + * + * caller needs to hold any needed locks to ensure integrity + * + */ +static int ipa_translate_rt_tbl_to_hw_fmt(enum ipa_ip_type ip, + enum ipa_rule_type rlt, u8 *base, u8 *hdr, + u32 body_ofst, u32 apps_start_idx) +{ + struct ipa3_rt_tbl_set *set; + struct ipa3_rt_tbl *tbl; + struct ipa_mem_buffer tbl_mem; + u8 *tbl_mem_buf; + struct ipa3_rt_entry *entry; + int res; + u64 offset; + u8 *body_i; + + set = &ipa3_ctx->rt_tbl_set[ip]; + body_i = base; + list_for_each_entry(tbl, &set->head_rt_tbl_list, link) { + if (tbl->sz[rlt] == 0) + continue; + if (tbl->in_sys[rlt]) { + /* only body (no header) */ + tbl_mem.size = tbl->sz[rlt] - + ipahal_get_hw_tbl_hdr_width(); + /* Add prefetech buf size. */ + tbl_mem.size += + ipahal_get_hw_prefetch_buf_size(); + if (ipahal_fltrt_allocate_hw_sys_tbl(&tbl_mem)) { + IPAERR_RL("fail to alloc sys tbl of size %d\n", + tbl_mem.size); + goto err; + } + + if (ipahal_fltrt_write_addr_to_hdr(tbl_mem.phys_base, + hdr, tbl->idx - apps_start_idx, true)) { + IPAERR_RL("fail to wrt sys tbl addr to hdr\n"); + goto hdr_update_fail; + } + + tbl_mem_buf = tbl_mem.base; + + /* generate the rule-set */ + list_for_each_entry(entry, &tbl->head_rt_rule_list, + link) { + if (IPA_RT_GET_RULE_TYPE(entry) != rlt) + continue; + res = ipa_generate_rt_hw_rule(ip, entry, + tbl_mem_buf); + if (res) { + IPAERR_RL("failed to gen HW RT rule\n"); + goto hdr_update_fail; + } + tbl_mem_buf += entry->hw_len; + } + + if (tbl->curr_mem[rlt].phys_base) { + WARN_ON(tbl->prev_mem[rlt].phys_base); + tbl->prev_mem[rlt] = tbl->curr_mem[rlt]; + } + tbl->curr_mem[rlt] = tbl_mem; + } else { + offset = body_i - base + body_ofst; + + /* update the hdr at the right index */ + if (ipahal_fltrt_write_addr_to_hdr(offset, hdr, + tbl->idx, false)) { + IPAERR_RL("fail to wrt lcl tbl ofst to hdr\n"); + goto hdr_update_fail; + } + + /* generate the rule-set */ + list_for_each_entry(entry, &tbl->head_rt_rule_list, + link) { + if (IPA_RT_GET_RULE_TYPE(entry) != rlt) + continue; + res = ipa_generate_rt_hw_rule(ip, entry, + body_i); + if (res) { + IPAERR_RL("failed to gen HW RT rule\n"); + goto err; + } + body_i += entry->hw_len; + } + + /** + * advance body_i to next table alignment as local + * tables + * are order back-to-back + */ + body_i += ipahal_get_lcl_tbl_addr_alignment(); + body_i = (u8 *)((long)body_i & + ~ipahal_get_lcl_tbl_addr_alignment()); + } + } + + return 0; + +hdr_update_fail: + ipahal_free_dma_mem(&tbl_mem); +err: + return -EPERM; +} + +static void __ipa_reap_sys_rt_tbls(enum ipa_ip_type ip) +{ + struct ipa3_rt_tbl *tbl; + struct ipa3_rt_tbl *next; + struct ipa3_rt_tbl_set *set; + int i; + + set = &ipa3_ctx->rt_tbl_set[ip]; + list_for_each_entry(tbl, &set->head_rt_tbl_list, link) { + for (i = 0; i < IPA_RULE_TYPE_MAX; i++) { + if (tbl->prev_mem[i].phys_base) { + IPADBG_LOW( + "reaping sys rt tbl name=%s ip=%d rlt=%d\n", + tbl->name, ip, i); + ipahal_free_dma_mem(&tbl->prev_mem[i]); + memset(&tbl->prev_mem[i], 0, + sizeof(tbl->prev_mem[i])); + } + } + } + + set = &ipa3_ctx->reap_rt_tbl_set[ip]; + list_for_each_entry_safe(tbl, next, &set->head_rt_tbl_list, link) { + for (i = 0; i < IPA_RULE_TYPE_MAX; i++) { + WARN_ON(tbl->prev_mem[i].phys_base != 0); + if (tbl->curr_mem[i].phys_base) { + IPADBG_LOW( + "reaping sys rt tbl name=%s ip=%d rlt=%d\n", + tbl->name, ip, i); + ipahal_free_dma_mem(&tbl->curr_mem[i]); + } + } + list_del(&tbl->link); + kmem_cache_free(ipa3_ctx->rt_tbl_cache, tbl); + } +} + +/** + * ipa_prep_rt_tbl_for_cmt() - preparing the rt table for commit + * assign priorities to the rules, calculate their sizes and calculate + * the overall table size + * @ip: the ip address family type + * @tbl: the rt tbl to be prepared + * + * Return: 0 on success, negative on failure + */ +static int ipa_prep_rt_tbl_for_cmt(enum ipa_ip_type ip, + struct ipa3_rt_tbl *tbl) +{ + struct ipa3_rt_entry *entry; + int prio_i; + int res; + int max_prio; + u32 hdr_width; + + tbl->sz[IPA_RULE_HASHABLE] = 0; + tbl->sz[IPA_RULE_NON_HASHABLE] = 0; + + max_prio = ipahal_get_rule_max_priority(); + + prio_i = max_prio; + list_for_each_entry(entry, &tbl->head_rt_rule_list, link) { + + if (entry->rule.max_prio) { + entry->prio = max_prio; + } else { + if (ipahal_rule_decrease_priority(&prio_i)) { + IPAERR("cannot rule decrease priority - %d\n", + prio_i); + return -EPERM; + } + entry->prio = prio_i; + } + + res = ipa_generate_rt_hw_rule(ip, entry, NULL); + if (res) { + IPAERR_RL("failed to calculate HW RT rule size\n"); + return -EPERM; + } + + IPADBG_LOW("RT rule id (handle) %d hw_len %u priority %u\n", + entry->id, entry->hw_len, entry->prio); + + if (entry->rule.hashable) + tbl->sz[IPA_RULE_HASHABLE] += entry->hw_len; + else + tbl->sz[IPA_RULE_NON_HASHABLE] += entry->hw_len; + } + + if ((tbl->sz[IPA_RULE_HASHABLE] + + tbl->sz[IPA_RULE_NON_HASHABLE]) == 0) { + IPAERR_RL("rt tbl %s is with zero total size\n", tbl->name); + } + + hdr_width = ipahal_get_hw_tbl_hdr_width(); + + if (tbl->sz[IPA_RULE_HASHABLE]) + tbl->sz[IPA_RULE_HASHABLE] += hdr_width; + if (tbl->sz[IPA_RULE_NON_HASHABLE]) + tbl->sz[IPA_RULE_NON_HASHABLE] += hdr_width; + + IPADBG("RT tbl index %u hash_sz %u non-hash sz %u\n", tbl->idx, + tbl->sz[IPA_RULE_HASHABLE], tbl->sz[IPA_RULE_NON_HASHABLE]); + + return 0; +} + +/** + * ipa_generate_rt_hw_tbl_img() - generates the rt hw tbls. + * headers and bodies (sys bodies) are being created into buffers that will + * be filled into the local memory (sram) + * @ip: the ip address family type + * @alloc_params: IN/OUT parameters to hold info regard the tables headers + * and bodies on DDR (DMA buffers), and needed info for the allocation + * that the HAL needs + * + * Return: 0 on success, negative on failure + */ +static int ipa_generate_rt_hw_tbl_img(enum ipa_ip_type ip, + struct ipahal_fltrt_alloc_imgs_params *alloc_params) +{ + u32 hash_bdy_start_ofst, nhash_bdy_start_ofst; + u32 apps_start_idx; + int rc = 0; + + if (ip == IPA_IP_v4) { + nhash_bdy_start_ofst = IPA_MEM_PART(apps_v4_rt_nhash_ofst) - + IPA_MEM_PART(v4_rt_nhash_ofst); + hash_bdy_start_ofst = IPA_MEM_PART(apps_v4_rt_hash_ofst) - + IPA_MEM_PART(v4_rt_hash_ofst); + apps_start_idx = IPA_MEM_PART(v4_apps_rt_index_lo); + } else { + nhash_bdy_start_ofst = IPA_MEM_PART(apps_v6_rt_nhash_ofst) - + IPA_MEM_PART(v6_rt_nhash_ofst); + hash_bdy_start_ofst = IPA_MEM_PART(apps_v6_rt_hash_ofst) - + IPA_MEM_PART(v6_rt_hash_ofst); + apps_start_idx = IPA_MEM_PART(v6_apps_rt_index_lo); + } + + if (ipahal_fltrt_allocate_hw_tbl_imgs(alloc_params)) { + IPAERR("fail to allocate RT HW TBL images. IP %d\n", ip); + rc = -ENOMEM; + goto allocate_fail; + } + + if (ipa_translate_rt_tbl_to_hw_fmt(ip, IPA_RULE_HASHABLE, + alloc_params->hash_bdy.base, alloc_params->hash_hdr.base, + hash_bdy_start_ofst, apps_start_idx)) { + IPAERR("fail to translate hashable rt tbls to hw format\n"); + rc = -EPERM; + goto translate_fail; + } + if (ipa_translate_rt_tbl_to_hw_fmt(ip, IPA_RULE_NON_HASHABLE, + alloc_params->nhash_bdy.base, alloc_params->nhash_hdr.base, + nhash_bdy_start_ofst, apps_start_idx)) { + IPAERR("fail to translate non-hashable rt tbls to hw format\n"); + rc = -EPERM; + goto translate_fail; + } + + return rc; + +translate_fail: + if (alloc_params->hash_hdr.size) + ipahal_free_dma_mem(&alloc_params->hash_hdr); + ipahal_free_dma_mem(&alloc_params->nhash_hdr); + if (alloc_params->hash_bdy.size) + ipahal_free_dma_mem(&alloc_params->hash_bdy); + if (alloc_params->nhash_bdy.size) + ipahal_free_dma_mem(&alloc_params->nhash_bdy); +allocate_fail: + return rc; +} + +/** + * ipa_rt_valid_lcl_tbl_size() - validate if the space allocated for rt tbl + * bodies at the sram is enough for the commit + * @ipt: the ip address family type + * @rlt: the rule type (hashable or non-hashable) + * + * Return: true if enough space available or false in other cases + */ +static bool ipa_rt_valid_lcl_tbl_size(enum ipa_ip_type ipt, + enum ipa_rule_type rlt, struct ipa_mem_buffer *bdy) +{ + u16 avail; + + if (ipt == IPA_IP_v4) + avail = (rlt == IPA_RULE_HASHABLE) ? + IPA_MEM_PART(apps_v4_rt_hash_size) : + IPA_MEM_PART(apps_v4_rt_nhash_size); + else + avail = (rlt == IPA_RULE_HASHABLE) ? + IPA_MEM_PART(apps_v6_rt_hash_size) : + IPA_MEM_PART(apps_v6_rt_nhash_size); + + if (bdy->size <= avail) + return true; + + IPAERR("tbl too big, needed %d avail %d ipt %d rlt %d\n", + bdy->size, avail, ipt, rlt); + return false; +} + +/** + * __ipa_commit_rt_v3() - commit rt tables to the hw + * commit the headers and the bodies if are local with internal cache flushing + * @ipt: the ip address family type + * + * Return: 0 on success, negative on failure + */ +int __ipa_commit_rt_v3(enum ipa_ip_type ip) +{ + struct ipa3_desc desc[IPA_RT_MAX_NUM_OF_COMMIT_TABLES_CMD_DESC]; + struct ipahal_imm_cmd_register_write reg_write_cmd = {0}; + struct ipahal_imm_cmd_dma_shared_mem mem_cmd = {0}; + struct ipahal_imm_cmd_pyld + *cmd_pyld[IPA_RT_MAX_NUM_OF_COMMIT_TABLES_CMD_DESC]; + int num_cmd = 0; + struct ipahal_fltrt_alloc_imgs_params alloc_params; + u32 num_modem_rt_index; + int rc = 0; + u32 lcl_hash_hdr, lcl_nhash_hdr; + u32 lcl_hash_bdy, lcl_nhash_bdy; + bool lcl_hash, lcl_nhash; + struct ipahal_reg_valmask valmask; + int i; + struct ipa3_rt_tbl_set *set; + struct ipa3_rt_tbl *tbl; + u32 tbl_hdr_width; + struct ipahal_imm_cmd_register_write reg_write_coal_close; + + tbl_hdr_width = ipahal_get_hw_tbl_hdr_width(); + memset(desc, 0, sizeof(desc)); + memset(cmd_pyld, 0, sizeof(cmd_pyld)); + memset(&alloc_params, 0, sizeof(alloc_params)); + alloc_params.ipt = ip; + + if (ip == IPA_IP_v4) { + num_modem_rt_index = + IPA_MEM_PART(v4_modem_rt_index_hi) - + IPA_MEM_PART(v4_modem_rt_index_lo) + 1; + lcl_hash_hdr = ipa3_ctx->smem_restricted_bytes + + IPA_MEM_PART(v4_rt_hash_ofst) + + num_modem_rt_index * tbl_hdr_width; + lcl_nhash_hdr = ipa3_ctx->smem_restricted_bytes + + IPA_MEM_PART(v4_rt_nhash_ofst) + + num_modem_rt_index * tbl_hdr_width; + lcl_hash_bdy = ipa3_ctx->smem_restricted_bytes + + IPA_MEM_PART(apps_v4_rt_hash_ofst); + lcl_nhash_bdy = ipa3_ctx->smem_restricted_bytes + + IPA_MEM_PART(apps_v4_rt_nhash_ofst); + lcl_hash = ipa3_ctx->rt_tbl_hash_lcl[IPA_IP_v4]; + lcl_nhash = ipa3_ctx->rt_tbl_nhash_lcl[IPA_IP_v4]; + alloc_params.tbls_num = IPA_MEM_PART(v4_apps_rt_index_hi) - + IPA_MEM_PART(v4_apps_rt_index_lo) + 1; + } else { + num_modem_rt_index = + IPA_MEM_PART(v6_modem_rt_index_hi) - + IPA_MEM_PART(v6_modem_rt_index_lo) + 1; + lcl_hash_hdr = ipa3_ctx->smem_restricted_bytes + + IPA_MEM_PART(v6_rt_hash_ofst) + + num_modem_rt_index * tbl_hdr_width; + lcl_nhash_hdr = ipa3_ctx->smem_restricted_bytes + + IPA_MEM_PART(v6_rt_nhash_ofst) + + num_modem_rt_index * tbl_hdr_width; + lcl_hash_bdy = ipa3_ctx->smem_restricted_bytes + + IPA_MEM_PART(apps_v6_rt_hash_ofst); + lcl_nhash_bdy = ipa3_ctx->smem_restricted_bytes + + IPA_MEM_PART(apps_v6_rt_nhash_ofst); + lcl_hash = ipa3_ctx->rt_tbl_hash_lcl[IPA_IP_v6]; + lcl_nhash = ipa3_ctx->rt_tbl_nhash_lcl[IPA_IP_v6]; + alloc_params.tbls_num = IPA_MEM_PART(v6_apps_rt_index_hi) - + IPA_MEM_PART(v6_apps_rt_index_lo) + 1; + } + + if (!ipa3_ctx->rt_idx_bitmap[ip]) { + IPAERR("no rt tbls present\n"); + rc = -EPERM; + goto no_rt_tbls; + } + + set = &ipa3_ctx->rt_tbl_set[ip]; + list_for_each_entry(tbl, &set->head_rt_tbl_list, link) { + if (ipa_prep_rt_tbl_for_cmt(ip, tbl)) { + rc = -EPERM; + goto no_rt_tbls; + } + if (!tbl->in_sys[IPA_RULE_HASHABLE] && + tbl->sz[IPA_RULE_HASHABLE]) { + alloc_params.num_lcl_hash_tbls++; + alloc_params.total_sz_lcl_hash_tbls += + tbl->sz[IPA_RULE_HASHABLE]; + alloc_params.total_sz_lcl_hash_tbls -= tbl_hdr_width; + } + if (!tbl->in_sys[IPA_RULE_NON_HASHABLE] && + tbl->sz[IPA_RULE_NON_HASHABLE]) { + alloc_params.num_lcl_nhash_tbls++; + alloc_params.total_sz_lcl_nhash_tbls += + tbl->sz[IPA_RULE_NON_HASHABLE]; + alloc_params.total_sz_lcl_nhash_tbls -= tbl_hdr_width; + } + } + + if (ipa_generate_rt_hw_tbl_img(ip, &alloc_params)) { + IPAERR("fail to generate RT HW TBL images. IP %d\n", ip); + rc = -EFAULT; + goto no_rt_tbls; + } + + if (!ipa_rt_valid_lcl_tbl_size(ip, IPA_RULE_HASHABLE, + &alloc_params.hash_bdy)) { + rc = -EFAULT; + goto fail_size_valid; + } + if (!ipa_rt_valid_lcl_tbl_size(ip, IPA_RULE_NON_HASHABLE, + &alloc_params.nhash_bdy)) { + rc = -EFAULT; + goto fail_size_valid; + } + + /* IC to close the coal frame before HPS Clear if coal is enabled */ + if (ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS) != -1 + && !ipa3_ctx->ulso_wa) { + u32 offset = 0; + + i = ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS); + reg_write_coal_close.skip_pipeline_clear = false; + reg_write_coal_close.pipeline_clear_options = IPAHAL_HPS_CLEAR; + if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0) + offset = ipahal_get_reg_ofst( + IPA_AGGR_FORCE_CLOSE); + else + offset = ipahal_get_ep_reg_offset( + IPA_AGGR_FORCE_CLOSE_n, i); + reg_write_coal_close.offset = offset; + ipahal_get_aggr_force_close_valmask(i, &valmask); + reg_write_coal_close.value = valmask.val; + reg_write_coal_close.value_mask = valmask.mask; + cmd_pyld[num_cmd] = ipahal_construct_imm_cmd( + IPA_IMM_CMD_REGISTER_WRITE, + ®_write_coal_close, false); + if (!cmd_pyld[num_cmd]) { + IPAERR("failed to construct coal close IC\n"); + goto fail_size_valid; + } + ipa3_init_imm_cmd_desc(&desc[num_cmd], cmd_pyld[num_cmd]); + ++num_cmd; + } + + /* + * SRAM memory not allocated to hash tables. Sending + * command to hash tables(filer/routing) operation not supported. + */ + if (!ipa3_ctx->ipa_fltrt_not_hashable) { + /* flushing ipa internal hashable rt rules cache */ + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0) { + struct ipahal_reg_fltrt_cache_flush flush_cache; + + memset(&flush_cache, 0, sizeof(flush_cache)); + flush_cache.rt = true; + ipahal_get_fltrt_cache_flush_valmask( + &flush_cache, &valmask); + reg_write_cmd.offset = ipahal_get_reg_ofst( + IPA_FILT_ROUT_CACHE_FLUSH); + } else { + struct ipahal_reg_fltrt_hash_flush flush_hash; + + memset(&flush_hash, 0, sizeof(flush_hash)); + if (ip == IPA_IP_v4) + flush_hash.v4_rt = true; + else + flush_hash.v6_rt = true; + ipahal_get_fltrt_hash_flush_valmask( + &flush_hash, &valmask); + reg_write_cmd.offset = ipahal_get_reg_ofst( + IPA_FILT_ROUT_HASH_FLUSH); + } + reg_write_cmd.skip_pipeline_clear = false; + reg_write_cmd.pipeline_clear_options = IPAHAL_HPS_CLEAR; + reg_write_cmd.value = valmask.val; + reg_write_cmd.value_mask = valmask.mask; + cmd_pyld[num_cmd] = ipahal_construct_imm_cmd( + IPA_IMM_CMD_REGISTER_WRITE, ®_write_cmd, + false); + if (!cmd_pyld[num_cmd]) { + IPAERR( + "fail construct register_write imm cmd. IP %d\n", ip); + goto fail_imm_cmd_construct; + } + ipa3_init_imm_cmd_desc(&desc[num_cmd], cmd_pyld[num_cmd]); + num_cmd++; + } + + mem_cmd.is_read = false; + mem_cmd.skip_pipeline_clear = false; + mem_cmd.pipeline_clear_options = IPAHAL_HPS_CLEAR; + mem_cmd.size = alloc_params.nhash_hdr.size; + mem_cmd.system_addr = alloc_params.nhash_hdr.phys_base; + mem_cmd.local_addr = lcl_nhash_hdr; + cmd_pyld[num_cmd] = ipahal_construct_imm_cmd( + IPA_IMM_CMD_DMA_SHARED_MEM, &mem_cmd, false); + if (!cmd_pyld[num_cmd]) { + IPAERR("fail construct dma_shared_mem imm cmd. IP %d\n", ip); + goto fail_imm_cmd_construct; + } + ipa3_init_imm_cmd_desc(&desc[num_cmd], cmd_pyld[num_cmd]); + num_cmd++; + + /* + * SRAM memory not allocated to hash tables. Sending + * command to hash tables(filer/routing) operation not supported. + */ + if (!ipa3_ctx->ipa_fltrt_not_hashable) { + mem_cmd.is_read = false; + mem_cmd.skip_pipeline_clear = false; + mem_cmd.pipeline_clear_options = IPAHAL_HPS_CLEAR; + mem_cmd.size = alloc_params.hash_hdr.size; + mem_cmd.system_addr = alloc_params.hash_hdr.phys_base; + mem_cmd.local_addr = lcl_hash_hdr; + cmd_pyld[num_cmd] = ipahal_construct_imm_cmd( + IPA_IMM_CMD_DMA_SHARED_MEM, &mem_cmd, false); + if (!cmd_pyld[num_cmd]) { + IPAERR( + "fail construct dma_shared_mem imm cmd. IP %d\n", ip); + goto fail_imm_cmd_construct; + } + ipa3_init_imm_cmd_desc(&desc[num_cmd], cmd_pyld[num_cmd]); + num_cmd++; + } + + if (lcl_nhash) { + if (num_cmd >= IPA_RT_MAX_NUM_OF_COMMIT_TABLES_CMD_DESC) { + IPAERR("number of commands is out of range: IP = %d\n", + ip); + rc = -ENOBUFS; + goto fail_imm_cmd_construct; + } + + mem_cmd.is_read = false; + mem_cmd.skip_pipeline_clear = false; + mem_cmd.pipeline_clear_options = IPAHAL_HPS_CLEAR; + mem_cmd.size = alloc_params.nhash_bdy.size; + mem_cmd.system_addr = alloc_params.nhash_bdy.phys_base; + mem_cmd.local_addr = lcl_nhash_bdy; + cmd_pyld[num_cmd] = ipahal_construct_imm_cmd( + IPA_IMM_CMD_DMA_SHARED_MEM, &mem_cmd, false); + if (!cmd_pyld[num_cmd]) { + IPAERR("fail construct dma_shared_mem cmd. IP %d\n", + ip); + goto fail_imm_cmd_construct; + } + ipa3_init_imm_cmd_desc(&desc[num_cmd], cmd_pyld[num_cmd]); + num_cmd++; + } + if (lcl_hash) { + if (num_cmd >= IPA_RT_MAX_NUM_OF_COMMIT_TABLES_CMD_DESC) { + IPAERR("number of commands is out of range: IP = %d\n", + ip); + rc = -ENOBUFS; + goto fail_imm_cmd_construct; + } + + mem_cmd.is_read = false; + mem_cmd.skip_pipeline_clear = false; + mem_cmd.pipeline_clear_options = IPAHAL_HPS_CLEAR; + mem_cmd.size = alloc_params.hash_bdy.size; + mem_cmd.system_addr = alloc_params.hash_bdy.phys_base; + mem_cmd.local_addr = lcl_hash_bdy; + cmd_pyld[num_cmd] = ipahal_construct_imm_cmd( + IPA_IMM_CMD_DMA_SHARED_MEM, &mem_cmd, false); + if (!cmd_pyld[num_cmd]) { + IPAERR("fail construct dma_shared_mem cmd. IP %d\n", + ip); + goto fail_imm_cmd_construct; + } + ipa3_init_imm_cmd_desc(&desc[num_cmd], cmd_pyld[num_cmd]); + num_cmd++; + } + + if (ipa3_send_cmd(num_cmd, desc)) { + IPAERR_RL("fail to send immediate command\n"); + rc = -EFAULT; + goto fail_imm_cmd_construct; + } + + IPADBG_LOW("Hashable HEAD\n"); + IPA_DUMP_BUFF(alloc_params.hash_hdr.base, + alloc_params.hash_hdr.phys_base, alloc_params.hash_hdr.size); + + IPADBG_LOW("Non-Hashable HEAD\n"); + IPA_DUMP_BUFF(alloc_params.nhash_hdr.base, + alloc_params.nhash_hdr.phys_base, alloc_params.nhash_hdr.size); + + if (alloc_params.hash_bdy.size) { + IPADBG_LOW("Hashable BODY\n"); + IPA_DUMP_BUFF(alloc_params.hash_bdy.base, + alloc_params.hash_bdy.phys_base, + alloc_params.hash_bdy.size); + } + + if (alloc_params.nhash_bdy.size) { + IPADBG_LOW("Non-Hashable BODY\n"); + IPA_DUMP_BUFF(alloc_params.nhash_bdy.base, + alloc_params.nhash_bdy.phys_base, + alloc_params.nhash_bdy.size); + } + + __ipa_reap_sys_rt_tbls(ip); + +fail_imm_cmd_construct: + for (i = 0 ; i < num_cmd ; i++) + ipahal_destroy_imm_cmd(cmd_pyld[i]); +fail_size_valid: + if (alloc_params.hash_hdr.size) + ipahal_free_dma_mem(&alloc_params.hash_hdr); + ipahal_free_dma_mem(&alloc_params.nhash_hdr); + if (alloc_params.hash_bdy.size) + ipahal_free_dma_mem(&alloc_params.hash_bdy); + if (alloc_params.nhash_bdy.size) + ipahal_free_dma_mem(&alloc_params.nhash_bdy); + +no_rt_tbls: + return rc; +} + +/** + * __ipa3_find_rt_tbl() - find the routing table + * which name is given as parameter + * @ip: [in] the ip address family type of the wanted routing table + * @name: [in] the name of the wanted routing table + * + * Returns: the routing table which name is given as parameter, or NULL if it + * doesn't exist + */ +struct ipa3_rt_tbl *__ipa3_find_rt_tbl(enum ipa_ip_type ip, const char *name) +{ + struct ipa3_rt_tbl *entry; + struct ipa3_rt_tbl_set *set; + + if (strnlen(name, IPA_RESOURCE_NAME_MAX) == IPA_RESOURCE_NAME_MAX) { + IPAERR_RL("Name too long: %s\n", name); + return NULL; + } + + set = &ipa3_ctx->rt_tbl_set[ip]; + list_for_each_entry(entry, &set->head_rt_tbl_list, link) { + if (!ipa3_check_idr_if_freed(entry) && + !strcmp(name, entry->name)) + return entry; + } + + return NULL; +} + +/** + * ipa3_query_rt_index() - find the routing table index + * which name and ip type are given as parameters + * @in: [out] the index of the wanted routing table + * + * Returns: the routing table which name is given as parameter, or NULL if it + * doesn't exist + */ +int ipa3_query_rt_index(struct ipa_ioc_get_rt_tbl_indx *in) +{ + struct ipa3_rt_tbl *entry; + + if (in->ip >= IPA_IP_MAX) { + IPAERR_RL("bad param\n"); + return -EINVAL; + } + + mutex_lock(&ipa3_ctx->lock); + in->name[IPA_RESOURCE_NAME_MAX-1] = '\0'; + /* check if this table exists */ + entry = __ipa3_find_rt_tbl(in->ip, in->name); + if (!entry) { + mutex_unlock(&ipa3_ctx->lock); + return -EFAULT; + } + in->idx = entry->idx; + mutex_unlock(&ipa3_ctx->lock); + return 0; +} + +static struct ipa3_rt_tbl *__ipa_add_rt_tbl(enum ipa_ip_type ip, + const char *name) +{ + struct ipa3_rt_tbl *entry; + struct ipa3_rt_tbl_set *set; + int i; + int id; + int max_tbl_indx; + + if (name == NULL) { + IPAERR_RL("no tbl name\n"); + goto error; + } + + if (ip == IPA_IP_v4) { + max_tbl_indx = + max(IPA_MEM_PART(v4_modem_rt_index_hi), + IPA_MEM_PART(v4_apps_rt_index_hi)); + } else if (ip == IPA_IP_v6) { + max_tbl_indx = + max(IPA_MEM_PART(v6_modem_rt_index_hi), + IPA_MEM_PART(v6_apps_rt_index_hi)); + } else { + IPAERR_RL("bad ip family type\n"); + goto error; + } + + set = &ipa3_ctx->rt_tbl_set[ip]; + /* check if this table exists */ + entry = __ipa3_find_rt_tbl(ip, name); + if (!entry) { + entry = kmem_cache_zalloc(ipa3_ctx->rt_tbl_cache, GFP_KERNEL); + if (!entry) + goto error; + + /* find a routing tbl index */ + for (i = 0; i < IPA_RT_INDEX_BITMAP_SIZE; i++) { + if (!test_bit(i, &ipa3_ctx->rt_idx_bitmap[ip])) { + entry->idx = i; + set_bit(i, &ipa3_ctx->rt_idx_bitmap[ip]); + break; + } + } + if (i == IPA_RT_INDEX_BITMAP_SIZE) { + IPAERR_RL("not free RT tbl indices left\n"); + goto fail_rt_idx_alloc; + } + if (i > max_tbl_indx) { + IPAERR_RL("rt tbl index is above max\n"); + goto fail_rt_idx_alloc; + } + + INIT_LIST_HEAD(&entry->head_rt_rule_list); + INIT_LIST_HEAD(&entry->link); + strlcpy(entry->name, name, IPA_RESOURCE_NAME_MAX); + entry->set = set; + entry->cookie = IPA_RT_TBL_COOKIE; + entry->in_sys[IPA_RULE_HASHABLE] = !ipa3_ctx->rt_tbl_hash_lcl[ip]; + entry->in_sys[IPA_RULE_NON_HASHABLE] = !ipa3_ctx->rt_tbl_nhash_lcl[ip]; + set->tbl_cnt++; + entry->rule_ids = &set->rule_ids; + list_add(&entry->link, &set->head_rt_tbl_list); + + IPADBG("add rt tbl idx=%d tbl_cnt=%d ip=%d\n", entry->idx, + set->tbl_cnt, ip); + + id = ipa3_id_alloc(entry); + if (id < 0) { + IPAERR_RL("failed to add to tree\n"); + WARN_ON_RATELIMIT_IPA(1); + goto ipa_insert_failed; + } + entry->id = id; + } + + return entry; +ipa_insert_failed: + set->tbl_cnt--; + list_del(&entry->link); + idr_destroy(entry->rule_ids); +fail_rt_idx_alloc: + entry->cookie = 0; + kmem_cache_free(ipa3_ctx->rt_tbl_cache, entry); +error: + return NULL; +} + +static int __ipa_del_rt_tbl(struct ipa3_rt_tbl *entry) +{ + enum ipa_ip_type ip = IPA_IP_MAX; + u32 id; + struct ipa3_rt_tbl_set *rset; + + if (entry == NULL || (entry->cookie != IPA_RT_TBL_COOKIE)) { + IPAERR_RL("bad params\n"); + return -EINVAL; + } + id = entry->id; + if (ipa3_id_find(id) == NULL) { + IPAERR_RL("lookup failed\n"); + return -EPERM; + } + + if (entry->set == &ipa3_ctx->rt_tbl_set[IPA_IP_v4]) + ip = IPA_IP_v4; + else if (entry->set == &ipa3_ctx->rt_tbl_set[IPA_IP_v6]) + ip = IPA_IP_v6; + else { + WARN_ON_RATELIMIT_IPA(1); + return -EPERM; + } + + rset = &ipa3_ctx->reap_rt_tbl_set[ip]; + + entry->rule_ids = NULL; + if (entry->in_sys[IPA_RULE_HASHABLE] || + entry->in_sys[IPA_RULE_NON_HASHABLE]) { + list_move(&entry->link, &rset->head_rt_tbl_list); + clear_bit(entry->idx, &ipa3_ctx->rt_idx_bitmap[ip]); + entry->set->tbl_cnt--; + IPADBG("del sys rt tbl_idx=%d tbl_cnt=%d ip=%d\n", + entry->idx, entry->set->tbl_cnt, ip); + } else { + list_del(&entry->link); + clear_bit(entry->idx, &ipa3_ctx->rt_idx_bitmap[ip]); + entry->set->tbl_cnt--; + IPADBG("del rt tbl_idx=%d tbl_cnt=%d ip=%d\n", + entry->idx, entry->set->tbl_cnt, ip); + kmem_cache_free(ipa3_ctx->rt_tbl_cache, entry); + } + + /* remove the handle from the database */ + ipa3_id_remove(id); + return 0; +} + +static int __ipa_rt_validate_rule_id(u16 rule_id) +{ + if (!rule_id) + return 0; + + if ((rule_id < ipahal_get_rule_id_hi_bit()) || + (rule_id >= ((ipahal_get_rule_id_hi_bit()<<1)-1))) { + IPAERR_RL("Invalid rule_id provided 0x%x\n", + rule_id); + return -EPERM; + } + + return 0; +} +static int __ipa_rt_validate_hndls(const struct ipa_rt_rule_i *rule, + struct ipa3_hdr_entry **hdr, + struct ipa3_hdr_proc_ctx_entry **proc_ctx) +{ + int index; + + if (rule->hdr_hdl && rule->hdr_proc_ctx_hdl) { + IPAERR_RL("rule contains both hdr_hdl and hdr_proc_ctx_hdl\n"); + return -EPERM; + } + + if (rule->hdr_hdl) { + *hdr = ipa3_id_find(rule->hdr_hdl); + if ((*hdr == NULL) || ((*hdr)->cookie != IPA_HDR_COOKIE)) { + IPAERR_RL("rt rule does not point to valid hdr\n"); + return -EPERM; + } + } else if (rule->hdr_proc_ctx_hdl) { + *proc_ctx = ipa3_id_find(rule->hdr_proc_ctx_hdl); + if ((*proc_ctx == NULL) || + ((*proc_ctx)->cookie != IPA_PROC_HDR_COOKIE)) { + + IPAERR_RL("rt rule does not point to valid proc ctx\n"); + return -EPERM; + } + } + + if (ipa3_ctx->ipa_hw_type < IPA_HW_v4_5 && rule->coalesce) { + IPAERR_RL("rt rule should not allow coalescing\n"); + return -EPERM; + } + + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_5) { + if (rule->enable_stats && rule->cnt_idx) { + if (!ipahal_is_rule_cnt_id_valid(rule->cnt_idx)) { + IPAERR_RL( + "invalid cnt_idx %hhu out of range\n", + rule->cnt_idx); + return -EPERM; + } + index = rule->cnt_idx - 1; + if (!ipa3_ctx->flt_rt_counters.used_hw[index]) { + IPAERR_RL( + "invalid cnt_idx %hhu not alloc by driver\n", + rule->cnt_idx); + return -EPERM; + } + } + } else { + if (rule->enable_stats) { + IPAERR_RL( + "enable_stats won't support on ipa_hw_type %d\n", + ipa3_ctx->ipa_hw_type); + return -EPERM; + } + } + return 0; +} + +static int __ipa_create_rt_entry(struct ipa3_rt_entry **entry, + const struct ipa_rt_rule_i *rule, + struct ipa3_rt_tbl *tbl, struct ipa3_hdr_entry *hdr, + struct ipa3_hdr_proc_ctx_entry *proc_ctx, + u16 rule_id, bool user) +{ + int id; + + *entry = kmem_cache_zalloc(ipa3_ctx->rt_rule_cache, GFP_KERNEL); + if (!*entry) + goto error; + + INIT_LIST_HEAD(&(*entry)->link); + (*(entry))->cookie = IPA_RT_RULE_COOKIE; + (*(entry))->rule = *rule; + (*(entry))->tbl = tbl; + (*(entry))->hdr = hdr; + (*(entry))->proc_ctx = proc_ctx; + if (rule_id) { + id = rule_id; + (*(entry))->rule_id_valid = 1; + } else { + id = ipa3_alloc_rule_id(tbl->rule_ids); + if (id < 0) { + IPAERR_RL("failed to allocate rule id\n"); + WARN_ON_RATELIMIT_IPA(1); + goto alloc_rule_id_fail; + } + } + (*(entry))->rule_id = id; + (*(entry))->ipacm_installed = user; + + if ((*(entry))->rule.coalesce && + IPA_CLIENT_IS_LAN_or_WAN_CONS((*(entry))->rule.dst)) { + int unused; + if ((*(entry))->rule.dst == IPA_CLIENT_APPS_LAN_CONS) { + if (IPA_CLIENT_IS_MAPPED(IPA_CLIENT_APPS_LAN_COAL_CONS, unused)) { + (*(entry))->rule.dst = IPA_CLIENT_APPS_LAN_COAL_CONS; + } + } else { /* == IPA_CLIENT_APPS_WAN_CONS */ + if (IPA_CLIENT_IS_MAPPED(IPA_CLIENT_APPS_WAN_COAL_CONS, unused)) { + (*(entry))->rule.dst = IPA_CLIENT_APPS_WAN_COAL_CONS; + } + } + } + + if (rule->enable_stats) + (*entry)->cnt_idx = rule->cnt_idx; + else + (*entry)->cnt_idx = 0; + return 0; + +alloc_rule_id_fail: + kmem_cache_free(ipa3_ctx->rt_rule_cache, *entry); +error: + return -EPERM; +} + +static int __ipa_finish_rt_rule_add(struct ipa3_rt_entry *entry, u32 *rule_hdl, + struct ipa3_rt_tbl *tbl) +{ + int id, res = 0; + + if (tbl->rule_cnt < IPA_RULE_CNT_MAX) + tbl->rule_cnt++; + else { + res = -EINVAL; + goto failed; + } + if (entry->hdr) + entry->hdr->ref_cnt++; + else if (entry->proc_ctx) + entry->proc_ctx->ref_cnt++; + id = ipa3_id_alloc(entry); + if (id < 0) { + IPAERR_RL("failed to add to tree\n"); + WARN_ON_RATELIMIT_IPA(1); + res = -EPERM; + goto ipa_insert_failed; + } + IPADBG("add rt rule tbl_idx=%d rule_cnt=%d rule_id=%d\n", + tbl->idx, tbl->rule_cnt, entry->rule_id); + *rule_hdl = id; + entry->id = id; + + return 0; + +ipa_insert_failed: + if (entry->hdr) + entry->hdr->ref_cnt--; + else if (entry->proc_ctx) + entry->proc_ctx->ref_cnt--; +failed: + idr_remove(tbl->rule_ids, entry->rule_id); + list_del(&entry->link); + kmem_cache_free(ipa3_ctx->rt_rule_cache, entry); + return res; +} + +static int __ipa_add_rt_rule(enum ipa_ip_type ip, const char *name, + const struct ipa_rt_rule_i *rule, u8 at_rear, u32 *rule_hdl, + u16 rule_id, bool user) +{ + struct ipa3_rt_tbl *tbl; + struct ipa3_rt_entry *entry; + struct ipa3_hdr_entry *hdr = NULL; + struct ipa3_hdr_proc_ctx_entry *proc_ctx = NULL; + + if (__ipa_rt_validate_hndls(rule, &hdr, &proc_ctx)) + goto error; + + if (__ipa_rt_validate_rule_id(rule_id)) + goto error; + + tbl = __ipa_add_rt_tbl(ip, name); + if (tbl == NULL || (tbl->cookie != IPA_RT_TBL_COOKIE)) { + IPAERR_RL("failed adding rt tbl name = %s\n", + name ? name : ""); + goto error; + } + /* + * do not allow any rule to be added at "default" routing + * table + */ + if (!strcmp(tbl->name, IPA_DFLT_RT_TBL_NAME) && + (tbl->rule_cnt > 0)) { + IPAERR_RL("cannot add rules to default rt table\n"); + goto error; + } + + if (__ipa_create_rt_entry(&entry, rule, tbl, hdr, proc_ctx, + rule_id, user)) + goto error; + + if (at_rear) + list_add_tail(&entry->link, &tbl->head_rt_rule_list); + else + list_add(&entry->link, &tbl->head_rt_rule_list); + + if (__ipa_finish_rt_rule_add(entry, rule_hdl, tbl)) + goto error; + + return 0; + +error: + return -EPERM; +} + +static int __ipa_add_rt_rule_after(struct ipa3_rt_tbl *tbl, + const struct ipa_rt_rule_i *rule, u32 *rule_hdl, + struct ipa3_rt_entry **add_after_entry) +{ + struct ipa3_rt_entry *entry; + struct ipa3_hdr_entry *hdr = NULL; + struct ipa3_hdr_proc_ctx_entry *proc_ctx = NULL; + + if (!*add_after_entry) + goto error; + + if (__ipa_rt_validate_hndls(rule, &hdr, &proc_ctx)) + goto error; + + if (__ipa_create_rt_entry(&entry, rule, tbl, hdr, proc_ctx, 0, true)) + goto error; + + list_add(&entry->link, &((*add_after_entry)->link)); + + if (__ipa_finish_rt_rule_add(entry, rule_hdl, tbl)) + goto error; + + /* + * prepare for next insertion + */ + *add_after_entry = entry; + + return 0; + +error: + *add_after_entry = NULL; + return -EPERM; +} + +static void __ipa_convert_rt_rule_in(struct ipa_rt_rule rule_in, + struct ipa_rt_rule_i *rule_out) +{ + if (unlikely(sizeof(struct ipa_rt_rule) > + sizeof(struct ipa_rt_rule_i))) { + IPAERR_RL("invalid size in: %d size out: %d\n", + sizeof(struct ipa_rt_rule), + sizeof(struct ipa_rt_rule_i)); + return; + } + memset(rule_out, 0, sizeof(struct ipa_rt_rule_i)); + memcpy(rule_out, &rule_in, sizeof(struct ipa_rt_rule)); +} + +static void __ipa_convert_rt_rule_out(struct ipa_rt_rule_i rule_in, + struct ipa_rt_rule *rule_out) +{ + if (unlikely(sizeof(struct ipa_rt_rule) > + sizeof(struct ipa_rt_rule_i))) { + IPAERR_RL("invalid size in:%d size out:%d\n", + sizeof(struct ipa_rt_rule), + sizeof(struct ipa_rt_rule_i)); + return; + } + memset(rule_out, 0, sizeof(struct ipa_rt_rule)); + memcpy(rule_out, &rule_in, sizeof(struct ipa_rt_rule)); +} + +static void __ipa_convert_rt_mdfy_in(struct ipa_rt_rule_mdfy rule_in, + struct ipa_rt_rule_mdfy_i *rule_out) +{ + if (unlikely(sizeof(struct ipa_rt_rule_mdfy) > + sizeof(struct ipa_rt_rule_mdfy_i))) { + IPAERR_RL("invalid size in:%d size out:%d\n", + sizeof(struct ipa_rt_rule_mdfy), + sizeof(struct ipa_rt_rule_mdfy_i)); + return; + } + memset(rule_out, 0, sizeof(struct ipa_rt_rule_mdfy_i)); + memcpy(&rule_out->rule, &rule_in.rule, + sizeof(struct ipa_rt_rule)); + rule_out->rt_rule_hdl = rule_in.rt_rule_hdl; + rule_out->status = rule_in.status; +} + +static void __ipa_convert_rt_mdfy_out(struct ipa_rt_rule_mdfy_i rule_in, + struct ipa_rt_rule_mdfy *rule_out) +{ + if (unlikely(sizeof(struct ipa_rt_rule_mdfy) > + sizeof(struct ipa_rt_rule_mdfy_i))) { + IPAERR_RL("invalid size in:%d size out:%d\n", + sizeof(struct ipa_rt_rule_mdfy), + sizeof(struct ipa_rt_rule_mdfy_i)); + return; + } + memset(rule_out, 0, sizeof(struct ipa_rt_rule_mdfy)); + memcpy(&rule_out->rule, &rule_in.rule, + sizeof(struct ipa_rt_rule)); + rule_out->rt_rule_hdl = rule_in.rt_rule_hdl; + rule_out->status = rule_in.status; +} + +/** + * ipa_add_rt_rule() - Add the specified routing rules to SW and optionally + * commit to IPA HW + * @rules: [inout] set of routing rules to add + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ + +int ipa_add_rt_rule(struct ipa_ioc_add_rt_rule *rules) +{ + return ipa3_add_rt_rule_usr(rules, false); +} +EXPORT_SYMBOL(ipa_add_rt_rule); + +/** + * ipa3_add_rt_rule_v2() - Add the specified routing rules to SW + * and optionally commit to IPA HW + * @rules: [inout] set of routing rules to add + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ + +int ipa3_add_rt_rule_v2(struct ipa_ioc_add_rt_rule_v2 *rules) +{ + return ipa3_add_rt_rule_usr_v2(rules, false); +} +EXPORT_SYMBOL(ipa3_add_rt_rule_v2); + +/** + * ipa3_add_rt_rule_usr() - Add the specified routing rules to SW and optionally + * commit to IPA HW + * @rules: [inout] set of routing rules to add + * @user_only: [in] indicate installed by userspace module + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ + +int ipa3_add_rt_rule_usr(struct ipa_ioc_add_rt_rule *rules, bool user_only) +{ + int i; + int ret; + struct ipa_rt_rule_i rule; + + if (rules == NULL || rules->num_rules == 0 || rules->ip >= IPA_IP_MAX) { + IPAERR_RL("bad param\n"); + return -EINVAL; + } + + mutex_lock(&ipa3_ctx->lock); + for (i = 0; i < rules->num_rules; i++) { + rules->rt_tbl_name[IPA_RESOURCE_NAME_MAX-1] = '\0'; + /* if hashing not supported, all tables are non-hash tables*/ + if (ipa3_ctx->ipa_fltrt_not_hashable) + rules->rules[i].rule.hashable = false; + __ipa_convert_rt_rule_in(rules->rules[i].rule, &rule); + if (__ipa_add_rt_rule(rules->ip, rules->rt_tbl_name, + &rule, + rules->rules[i].at_rear, + &rules->rules[i].rt_rule_hdl, + 0, + user_only)) { + IPAERR_RL("failed to add rt rule %d\n", i); + rules->rules[i].status = IPA_RT_STATUS_OF_ADD_FAILED; + } else { + __ipa_convert_rt_rule_out(rule, &rules->rules[i].rule); + rules->rules[i].status = 0; + } + } + + if (rules->commit) + if (ipa3_ctx->ctrl->ipa3_commit_rt(rules->ip)) { + ret = -EPERM; + goto bail; + } + + ret = 0; +bail: + mutex_unlock(&ipa3_ctx->lock); + return ret; +} +EXPORT_SYMBOL(ipa3_add_rt_rule_usr); + +/** + * ipa3_add_rt_rule_usr_v2() - Add the specified routing rules + * to SW and optionally commit to IPA HW + * @rules: [inout] set of routing rules to add + * @user_only: [in] indicate installed by userspace module + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ + +int ipa3_add_rt_rule_usr_v2(struct ipa_ioc_add_rt_rule_v2 *rules, + bool user_only) +{ + int i; + int ret; + + if (rules == NULL || rules->num_rules == 0 || rules->ip >= IPA_IP_MAX) { + IPAERR_RL("bad param\n"); + return -EINVAL; + } + + mutex_lock(&ipa3_ctx->lock); + for (i = 0; i < rules->num_rules; i++) { + rules->rt_tbl_name[IPA_RESOURCE_NAME_MAX-1] = '\0'; + /* if hashing not supported, all tables are non-hash tables*/ + if (ipa3_ctx->ipa_fltrt_not_hashable) + ((struct ipa_rt_rule_add_i *) + rules->rules)[i].rule.hashable = false; + if (__ipa_add_rt_rule(rules->ip, rules->rt_tbl_name, + &(((struct ipa_rt_rule_add_i *) + rules->rules)[i].rule), + ((struct ipa_rt_rule_add_i *) + rules->rules)[i].at_rear, + &(((struct ipa_rt_rule_add_i *) + rules->rules)[i].rt_rule_hdl), + 0, + user_only)) { + IPAERR_RL("failed to add rt rule %d\n", i); + ((struct ipa_rt_rule_add_i *)rules->rules)[i].status + = IPA_RT_STATUS_OF_ADD_FAILED; + } else { + ((struct ipa_rt_rule_add_i *) + rules->rules)[i].status = 0; + } + } + + if (rules->commit) + if (ipa3_ctx->ctrl->ipa3_commit_rt(rules->ip)) { + ret = -EPERM; + goto bail; + } + + ret = 0; +bail: + mutex_unlock(&ipa3_ctx->lock); + return ret; +} +EXPORT_SYMBOL(ipa3_add_rt_rule_usr_v2); + + +/** + * ipa3_add_rt_rule_ext() - Add the specified routing rules to SW with rule id + * and optionally commit to IPA HW + * @rules: [inout] set of routing rules to add + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_add_rt_rule_ext(struct ipa_ioc_add_rt_rule_ext *rules) +{ + int i; + int ret; + struct ipa_rt_rule_i rule; + + if (rules == NULL || rules->num_rules == 0 || rules->ip >= IPA_IP_MAX) { + IPAERR_RL("bad param\n"); + return -EINVAL; + } + + mutex_lock(&ipa3_ctx->lock); + for (i = 0; i < rules->num_rules; i++) { + /* if hashing not supported, all tables are non-hash tables*/ + if (ipa3_ctx->ipa_fltrt_not_hashable) + rules->rules[i].rule.hashable = false; + __ipa_convert_rt_rule_in( + rules->rules[i].rule, &rule); + if (__ipa_add_rt_rule(rules->ip, rules->rt_tbl_name, + &rule, + rules->rules[i].at_rear, + &rules->rules[i].rt_rule_hdl, + rules->rules[i].rule_id, true)) { + IPAERR_RL("failed to add rt rule %d\n", i); + rules->rules[i].status = IPA_RT_STATUS_OF_ADD_FAILED; + } else { + __ipa_convert_rt_rule_out(rule, &rules->rules[i].rule); + rules->rules[i].status = 0; + } + } + + if (rules->commit) + if (ipa3_ctx->ctrl->ipa3_commit_rt(rules->ip)) { + ret = -EPERM; + goto bail; + } + + ret = 0; +bail: + mutex_unlock(&ipa3_ctx->lock); + return ret; +} +EXPORT_SYMBOL(ipa3_add_rt_rule_ext); + +/** + * ipa3_add_rt_rule_ext_v2() - Add the specified routing rules + * to SW with rule id and optionally commit to IPA HW + * @rules: [inout] set of routing rules to add + * @user: [in] true if the rt rules are added from userspace + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_add_rt_rule_ext_v2(struct ipa_ioc_add_rt_rule_ext_v2 *rules, + bool user) +{ + int i; + int ret; + + if (rules == NULL || rules->num_rules == 0 || rules->ip >= IPA_IP_MAX) { + IPAERR_RL("bad param\n"); + return -EINVAL; + } + + mutex_lock(&ipa3_ctx->lock); + for (i = 0; i < rules->num_rules; i++) { + /* if hashing not supported, all tables are non-hash tables*/ + if (ipa3_ctx->ipa_fltrt_not_hashable) + ((struct ipa_rt_rule_add_ext_i *) + rules->rules)[i].rule.hashable = false; + if (__ipa_add_rt_rule(rules->ip, rules->rt_tbl_name, + &(((struct ipa_rt_rule_add_ext_i *) + rules->rules)[i].rule), + ((struct ipa_rt_rule_add_ext_i *) + rules->rules)[i].at_rear, + &(((struct ipa_rt_rule_add_ext_i *) + rules->rules)[i].rt_rule_hdl), + ((struct ipa_rt_rule_add_ext_i *) + rules->rules)[i].rule_id, user)) { + IPAERR_RL("failed to add rt rule %d\n", i); + ((struct ipa_rt_rule_add_ext_i *) + rules->rules)[i].status = IPA_RT_STATUS_OF_ADD_FAILED; + } else { + ((struct ipa_rt_rule_add_ext_i *) + rules->rules)[i].status = 0; + } + } + + if (rules->commit) + if (ipa3_ctx->ctrl->ipa3_commit_rt(rules->ip)) { + ret = -EPERM; + goto bail; + } + + ret = 0; +bail: + mutex_unlock(&ipa3_ctx->lock); + return ret; +} +EXPORT_SYMBOL(ipa3_add_rt_rule_ext_v2); + +/** + * ipa3_add_rt_rule_after() - Add the given routing rules after the + * specified rule to SW and optionally commit to IPA HW + * @rules: [inout] set of routing rules to add + handle where to add + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_add_rt_rule_after(struct ipa_ioc_add_rt_rule_after *rules) +{ + int i; + int ret = 0; + struct ipa3_rt_tbl *tbl = NULL; + struct ipa3_rt_entry *entry = NULL; + struct ipa_rt_rule_i rule; + + if (rules == NULL || rules->num_rules == 0 || rules->ip >= IPA_IP_MAX) { + IPAERR_RL("bad param\n"); + return -EINVAL; + } + + mutex_lock(&ipa3_ctx->lock); + rules->rt_tbl_name[IPA_RESOURCE_NAME_MAX-1] = '\0'; + tbl = __ipa3_find_rt_tbl(rules->ip, rules->rt_tbl_name); + if (tbl == NULL || (tbl->cookie != IPA_RT_TBL_COOKIE)) { + IPAERR_RL("failed finding rt tbl name = %s\n", + rules->rt_tbl_name); + ret = -EINVAL; + goto bail; + } + + if (!tbl->rule_cnt) { + IPAERR_RL("tbl->rule_cnt == 0"); + ret = -EINVAL; + goto bail; + } + + entry = ipa3_id_find(rules->add_after_hdl); + if (!entry) { + IPAERR_RL("failed finding rule %d in rt tbls\n", + rules->add_after_hdl); + ret = -EINVAL; + goto bail; + } + + if (entry->cookie != IPA_RT_RULE_COOKIE) { + IPAERR_RL("Invalid cookie value = %u rule %d in rt tbls\n", + entry->cookie, rules->add_after_hdl); + ret = -EINVAL; + goto bail; + } + + if (entry->tbl != tbl) { + IPAERR_RL("given rt rule does not match the table\n"); + ret = -EINVAL; + goto bail; + } + + /* + * do not allow any rule to be added at "default" routing + * table + */ + if (!strcmp(tbl->name, IPA_DFLT_RT_TBL_NAME) && + (tbl->rule_cnt > 0)) { + IPAERR_RL("cannot add rules to default rt table\n"); + ret = -EINVAL; + goto bail; + } + + /* + * we add all rules one after the other, if one insertion fails, it cuts + * the chain (all following will receive fail status) following calls to + * __ipa_add_rt_rule_after will fail (entry == NULL) + */ + + for (i = 0; i < rules->num_rules; i++) { + /* if hashing not supported, all tables are non-hash tables*/ + if (ipa3_ctx->ipa_fltrt_not_hashable) + rules->rules[i].rule.hashable = false; + __ipa_convert_rt_rule_in( + rules->rules[i].rule, &rule); + if (__ipa_add_rt_rule_after(tbl, + &rule, + &rules->rules[i].rt_rule_hdl, + &entry)) { + IPAERR_RL("failed to add rt rule %d\n", i); + rules->rules[i].status = IPA_RT_STATUS_OF_ADD_FAILED; + } else { + rules->rules[i].status = 0; + __ipa_convert_rt_rule_out(rule, &rules->rules[i].rule); + } + } + + if (rules->commit) + if (ipa3_ctx->ctrl->ipa3_commit_rt(rules->ip)) { + IPAERR_RL("failed to commit\n"); + ret = -EPERM; + goto bail; + } + + ret = 0; + goto bail; + +bail: + mutex_unlock(&ipa3_ctx->lock); + return ret; +} +EXPORT_SYMBOL(ipa3_add_rt_rule_after); + +/** + * ipa3_add_rt_rule_after_v2() - Add the given routing rules + * after the specified rule to SW and optionally commit to IPA + * HW + * @rules: [inout] set of routing rules to add + handle where to add + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_add_rt_rule_after_v2(struct ipa_ioc_add_rt_rule_after_v2 + *rules) +{ + int i; + int ret = 0; + struct ipa3_rt_tbl *tbl = NULL; + struct ipa3_rt_entry *entry = NULL; + + if (rules == NULL || rules->num_rules == 0 || rules->ip >= IPA_IP_MAX) { + IPAERR_RL("bad param\n"); + return -EINVAL; + } + + mutex_lock(&ipa3_ctx->lock); + rules->rt_tbl_name[IPA_RESOURCE_NAME_MAX-1] = '\0'; + tbl = __ipa3_find_rt_tbl(rules->ip, rules->rt_tbl_name); + if (tbl == NULL || (tbl->cookie != IPA_RT_TBL_COOKIE)) { + IPAERR_RL("failed finding rt tbl name = %s\n", + rules->rt_tbl_name); + ret = -EINVAL; + goto bail; + } + + if (!tbl->rule_cnt) { + IPAERR_RL("tbl->rule_cnt == 0"); + ret = -EINVAL; + goto bail; + } + + entry = ipa3_id_find(rules->add_after_hdl); + if (!entry) { + IPAERR_RL("failed finding rule %d in rt tbls\n", + rules->add_after_hdl); + ret = -EINVAL; + goto bail; + } + + if (entry->cookie != IPA_RT_RULE_COOKIE) { + IPAERR_RL("Invalid cookie value = %u rule %d in rt tbls\n", + entry->cookie, rules->add_after_hdl); + ret = -EINVAL; + goto bail; + } + + if (entry->tbl != tbl) { + IPAERR_RL("given rt rule does not match the table\n"); + ret = -EINVAL; + goto bail; + } + + /* + * do not allow any rule to be added at "default" routing + * table + */ + if (!strcmp(tbl->name, IPA_DFLT_RT_TBL_NAME) && + (tbl->rule_cnt > 0)) { + IPAERR_RL("cannot add rules to default rt table\n"); + ret = -EINVAL; + goto bail; + } + + /* + * we add all rules one after the other, if one insertion fails, it cuts + * the chain (all following will receive fail status) following calls to + * __ipa_add_rt_rule_after will fail (entry == NULL) + */ + + for (i = 0; i < rules->num_rules; i++) { + /* if hashing not supported, all tables are non-hash tables*/ + if (ipa3_ctx->ipa_fltrt_not_hashable) + ((struct ipa_rt_rule_add_i *) + rules->rules)[i].rule.hashable = false; + if (__ipa_add_rt_rule_after(tbl, + &(((struct ipa_rt_rule_add_i *) + rules->rules)[i].rule), + &(((struct ipa_rt_rule_add_i *) + rules->rules)[i].rt_rule_hdl), + &entry)) { + IPAERR_RL("failed to add rt rule %d\n", i); + ((struct ipa_rt_rule_add_i *) + rules->rules)[i].status = IPA_RT_STATUS_OF_ADD_FAILED; + } else { + ((struct ipa_rt_rule_add_i *) + rules->rules)[i].status = 0; + } + } + + if (rules->commit) + if (ipa3_ctx->ctrl->ipa3_commit_rt(rules->ip)) { + IPAERR_RL("failed to commit\n"); + ret = -EPERM; + goto bail; + } + + ret = 0; + goto bail; + +bail: + mutex_unlock(&ipa3_ctx->lock); + return ret; +} +EXPORT_SYMBOL(ipa3_add_rt_rule_after_v2); + +int __ipa3_del_rt_rule(u32 rule_hdl) +{ + struct ipa3_rt_entry *entry; + int id; + struct ipa3_hdr_entry *hdr_entry; + struct ipa3_hdr_proc_ctx_entry *hdr_proc_entry; + + entry = ipa3_id_find(rule_hdl); + + if (entry == NULL) { + IPAERR_RL("lookup failed\n"); + return -EINVAL; + } + + if (entry->cookie != IPA_RT_RULE_COOKIE) { + IPAERR_RL("bad params\n"); + return -EINVAL; + } + + if (!ipa3_check_idr_if_freed(entry) && + !strcmp(entry->tbl->name, IPA_DFLT_RT_TBL_NAME)) { + IPADBG("Deleting rule from default rt table idx=%u\n", + entry->tbl->idx); + if (entry->tbl->rule_cnt == 1 && !ipa3_ctx->deepsleep) { + IPAERR_RL("Default tbl last rule cannot be deleted\n"); + return -EINVAL; + } + } + + /* Adding check to confirm still + * header entry present in header table or not + */ + + if (entry->hdr) { + hdr_entry = ipa3_id_find(entry->rule.hdr_hdl); + if (!hdr_entry || hdr_entry->cookie != IPA_HDR_COOKIE) { + IPAERR_RL("Header entry already deleted\n"); + entry->hdr = NULL; + } + } else if (entry->proc_ctx) { + hdr_proc_entry = ipa3_id_find(entry->rule.hdr_proc_ctx_hdl); + if (!hdr_proc_entry || + hdr_proc_entry->cookie != IPA_PROC_HDR_COOKIE) { + IPAERR_RL("Proc header entry already deleted\n"); + entry->proc_ctx = NULL; + } + } + + if (entry->hdr && + (!ipa3_check_idr_if_freed(entry->hdr))) + __ipa3_release_hdr(entry->hdr->id); + else if (entry->proc_ctx && + (!ipa3_check_idr_if_freed(entry->proc_ctx))) + __ipa3_release_hdr_proc_ctx(entry->proc_ctx->id); + list_del(&entry->link); + entry->tbl->rule_cnt--; + IPADBG("del rt rule tbl_idx=%d rule_cnt=%d rule_id=%d\n ref_cnt=%u", + entry->tbl->idx, entry->tbl->rule_cnt, + entry->rule_id, entry->tbl->ref_cnt); + /* if rule id was allocated from idr, remove it */ + if (!entry->rule_id_valid) + idr_remove(entry->tbl->rule_ids, entry->rule_id); + if (entry->tbl->rule_cnt == 0 && entry->tbl->ref_cnt == 0) { + if (__ipa_del_rt_tbl(entry->tbl)) + IPAERR_RL("fail to del RT tbl\n"); + } + entry->cookie = 0; + id = entry->id; + kmem_cache_free(ipa3_ctx->rt_rule_cache, entry); + + /* remove the handle from the database */ + ipa3_id_remove(id); + + return 0; +} + +/** + * ipa3_del_rt_rule() - Remove the specified routing rules to SW and optionally + * commit to IPA HW + * @hdls: [inout] set of routing rules to delete + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_del_rt_rule(struct ipa_ioc_del_rt_rule *hdls) +{ + int i; + int ret; + + if (hdls == NULL || hdls->num_hdls == 0 || hdls->ip >= IPA_IP_MAX) { + IPAERR_RL("bad param\n"); + return -EINVAL; + } + + mutex_lock(&ipa3_ctx->lock); + for (i = 0; i < hdls->num_hdls; i++) { + if (__ipa3_del_rt_rule(hdls->hdl[i].hdl)) { + IPAERR_RL("failed to del rt rule %i\n", i); + hdls->hdl[i].status = IPA_RT_STATUS_OF_DEL_FAILED; + } else { + hdls->hdl[i].status = 0; + } + } + + if (hdls->commit) + if (ipa3_ctx->ctrl->ipa3_commit_rt(hdls->ip)) { + ret = -EPERM; + goto bail; + } + + ret = 0; +bail: + mutex_unlock(&ipa3_ctx->lock); + return ret; +} + +/** + * ipa_commit_rt_rule() - Commit the current SW routing table of specified type + * to IPA HW + * @ip: The family of routing tables + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_commit_rt(enum ipa_ip_type ip) +{ + int ret; + + if (ip >= IPA_IP_MAX) { + IPAERR_RL("bad param\n"); + return -EINVAL; + } + + /* + * issue a commit on the filtering module of same IP type since + * filtering rules point to routing tables + */ + if (ipa3_commit_flt(ip)) + return -EPERM; + + mutex_lock(&ipa3_ctx->lock); + if (ipa3_ctx->ctrl->ipa3_commit_rt(ip)) { + ret = -EPERM; + goto bail; + } + + ret = 0; +bail: + mutex_unlock(&ipa3_ctx->lock); + return ret; +} + +/** + * ipa3_reset_rt() - reset the current SW routing table of specified type + * (does not commit to HW) + * @ip: [in] The family of routing tables + * @user_only: [in] indicate delete rules installed by userspace + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_reset_rt(enum ipa_ip_type ip, bool user_only) +{ + struct ipa3_rt_tbl *tbl; + struct ipa3_rt_tbl *tbl_next; + struct ipa3_rt_tbl_set *set; + struct ipa3_rt_entry *rule; + struct ipa3_rt_entry *rule_next; + struct ipa3_rt_tbl_set *rset; + struct ipa3_hdr_entry *hdr_entry; + struct ipa3_hdr_proc_ctx_entry *hdr_proc_entry; + u32 apps_start_idx; + int id; + bool tbl_user = false; + + if (ip >= IPA_IP_MAX) { + IPAERR_RL("bad param\n"); + return -EINVAL; + } + + if (ip == IPA_IP_v4) + apps_start_idx = + IPA_MEM_PART(v4_apps_rt_index_lo); + else + apps_start_idx = + IPA_MEM_PART(v6_apps_rt_index_lo); + + /* + * issue a reset on the filtering module of same IP type since + * filtering rules point to routing tables + */ + if (ipa3_reset_flt(ip, user_only)) + IPAERR_RL("fail to reset flt ip=%d\n", ip); + + set = &ipa3_ctx->rt_tbl_set[ip]; + rset = &ipa3_ctx->reap_rt_tbl_set[ip]; + mutex_lock(&ipa3_ctx->lock); + IPADBG("reset rt ip=%d\n", ip); + list_for_each_entry_safe(tbl, tbl_next, &set->head_rt_tbl_list, link) { + tbl_user = false; + list_for_each_entry_safe(rule, rule_next, + &tbl->head_rt_rule_list, link) { + if (ipa3_id_find(rule->id) == NULL) { + WARN_ON_RATELIMIT_IPA(1); + mutex_unlock(&ipa3_ctx->lock); + return -EFAULT; + } + + /* indicate if tbl used for user-specified rules*/ + if (rule->ipacm_installed) { + IPADBG("tbl_user %d, tbl-index %d\n", + tbl_user, tbl->id); + tbl_user = true; + } + /* + * for the "default" routing tbl, remove all but the + * last rule + */ + if (tbl->idx == apps_start_idx && tbl->rule_cnt == 1) + continue; + + if (!user_only || + rule->ipacm_installed) { + if (rule->hdr) { + hdr_entry = ipa3_id_find( + rule->rule.hdr_hdl); + if (!hdr_entry || + hdr_entry->cookie != IPA_HDR_COOKIE) { + IPAERR_RL( + "Header already deleted\n"); + rule->hdr = NULL; + } + } else if (rule->proc_ctx) { + hdr_proc_entry = + ipa3_id_find( + rule->rule.hdr_proc_ctx_hdl); + if (!hdr_proc_entry || + hdr_proc_entry->cookie != + IPA_PROC_HDR_COOKIE) { + IPAERR_RL( + "Proc entry already deleted\n"); + rule->proc_ctx = NULL; + } + } + tbl->rule_cnt--; + list_del(&rule->link); + if (rule->hdr && + (!ipa3_check_idr_if_freed( + rule->hdr))) + __ipa3_release_hdr(rule->hdr->id); + else if (rule->proc_ctx && + (!ipa3_check_idr_if_freed( + rule->proc_ctx))) + __ipa3_release_hdr_proc_ctx( + rule->proc_ctx->id); + rule->cookie = 0; + if (!rule->rule_id_valid) + idr_remove(tbl->rule_ids, + rule->rule_id); + id = rule->id; + kmem_cache_free(ipa3_ctx->rt_rule_cache, rule); + + /* remove the handle from the database */ + ipa3_id_remove(id); + } + } + + if (ipa3_id_find(tbl->id) == NULL) { + WARN_ON_RATELIMIT_IPA(1); + mutex_unlock(&ipa3_ctx->lock); + return -EFAULT; + } + id = tbl->id; + + /* do not remove the "default" routing tbl which has index 0 */ + if (tbl->idx != apps_start_idx) { + if (!user_only || tbl_user) { + tbl->rule_ids = NULL; + if (tbl->in_sys[IPA_RULE_HASHABLE] || + tbl->in_sys[IPA_RULE_NON_HASHABLE]) { + list_move(&tbl->link, + &rset->head_rt_tbl_list); + clear_bit(tbl->idx, + &ipa3_ctx->rt_idx_bitmap[ip]); + set->tbl_cnt--; + IPADBG("rst tbl_idx=%d cnt=%d\n", + tbl->idx, set->tbl_cnt); + } else { + list_del(&tbl->link); + set->tbl_cnt--; + clear_bit(tbl->idx, + &ipa3_ctx->rt_idx_bitmap[ip]); + IPADBG("rst rt tbl_idx=%d tbl_cnt=%d\n", + tbl->idx, set->tbl_cnt); + kmem_cache_free(ipa3_ctx->rt_tbl_cache, + tbl); + } + /* remove the handle from the database */ + ipa3_id_remove(id); + } + } + } + + /* commit the change to IPA-HW */ + if (ipa3_ctx->ctrl->ipa3_commit_rt(IPA_IP_v4) || + ipa3_ctx->ctrl->ipa3_commit_rt(IPA_IP_v6)) { + IPAERR_RL("fail to commit rt-rule\n"); + WARN_ON_RATELIMIT_IPA(1); + mutex_unlock(&ipa3_ctx->lock); + return -EPERM; + } + mutex_unlock(&ipa3_ctx->lock); + + return 0; +} + +/** + * ipa3_get_rt_tbl() - lookup the specified routing table and return handle if + * it exists, if lookup succeeds the routing table ref cnt is increased + * @lookup: [inout] routing table to lookup and its handle + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + * Caller should call ipa_put_rt_tbl later if this function succeeds + */ +int ipa3_get_rt_tbl(struct ipa_ioc_get_rt_tbl *lookup) +{ + struct ipa3_rt_tbl *entry; + int result = -EFAULT; + + if (lookup == NULL || lookup->ip >= IPA_IP_MAX) { + IPAERR_RL("bad param\n"); + return -EINVAL; + } + mutex_lock(&ipa3_ctx->lock); + lookup->name[IPA_RESOURCE_NAME_MAX-1] = '\0'; + entry = __ipa3_find_rt_tbl(lookup->ip, lookup->name); + if (entry && entry->cookie == IPA_RT_TBL_COOKIE) { + if (entry->ref_cnt == U32_MAX) { + IPAERR_RL("fail: ref count crossed limit\n"); + goto ret; + } + entry->ref_cnt++; + lookup->hdl = entry->id; + + /* commit for get */ + if (ipa3_ctx->ctrl->ipa3_commit_rt(lookup->ip)) + IPAERR_RL("fail to commit RT tbl\n"); + + result = 0; + } + +ret: + mutex_unlock(&ipa3_ctx->lock); + + return result; +} +EXPORT_SYMBOL(ipa3_get_rt_tbl); + +/** + * ipa_put_rt_tbl() - Release the specified routing table handle + * @rt_tbl_hdl: [in] the routing table handle to release + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa_put_rt_tbl(u32 rt_tbl_hdl) +{ + struct ipa3_rt_tbl *entry; + enum ipa_ip_type ip = IPA_IP_MAX; + int result = 0; + + mutex_lock(&ipa3_ctx->lock); + entry = ipa3_id_find(rt_tbl_hdl); + if (entry == NULL) { + IPAERR_RL("lookup failed\n"); + result = -EINVAL; + goto ret; + } + + if ((entry->cookie != IPA_RT_TBL_COOKIE) || entry->ref_cnt == 0) { + IPAERR_RL("bad params\n"); + result = -EINVAL; + goto ret; + } + + if (entry->set == &ipa3_ctx->rt_tbl_set[IPA_IP_v4]) + ip = IPA_IP_v4; + else if (entry->set == &ipa3_ctx->rt_tbl_set[IPA_IP_v6]) + ip = IPA_IP_v6; + else { + WARN_ON_RATELIMIT_IPA(1); + result = -EINVAL; + goto ret; + } + + entry->ref_cnt--; + if (entry->ref_cnt == 0 && entry->rule_cnt == 0) { + IPADBG("zero ref_cnt, delete rt tbl (idx=%u)\n", + entry->idx); + if (__ipa_del_rt_tbl(entry)) + IPAERR_RL("fail to del RT tbl\n"); + /* commit for put */ + if (ipa3_ctx->ctrl->ipa3_commit_rt(ip)) + IPAERR_RL("fail to commit RT tbl\n"); + } + + result = 0; + +ret: + mutex_unlock(&ipa3_ctx->lock); + + return result; +} +EXPORT_SYMBOL(ipa_put_rt_tbl); + +static int __ipa_mdfy_rt_rule(struct ipa_rt_rule_mdfy_i *rtrule) +{ + struct ipa3_rt_entry *entry; + struct ipa3_hdr_entry *hdr = NULL; + struct ipa3_hdr_proc_ctx_entry *proc_ctx = NULL; + struct ipa3_hdr_entry *hdr_entry; + struct ipa3_hdr_proc_ctx_entry *hdr_proc_entry; + + if (__ipa_rt_validate_hndls(&rtrule->rule, &hdr, &proc_ctx)) + goto error; + + entry = ipa3_id_find(rtrule->rt_rule_hdl); + if (entry == NULL) { + IPAERR_RL("lookup failed\n"); + goto error; + } + + if (entry->cookie != IPA_RT_RULE_COOKIE) { + IPAERR_RL("bad params\n"); + goto error; + } + + if (!ipa3_check_idr_if_freed(entry) && + !strcmp(entry->tbl->name, IPA_DFLT_RT_TBL_NAME)) { + IPAERR_RL("Default tbl rule cannot be modified\n"); + return -EINVAL; + } + /* Adding check to confirm still + * header entry present in header table or not + */ + + if (entry->hdr) { + hdr_entry = ipa3_id_find(entry->rule.hdr_hdl); + if (!hdr_entry || (hdr_entry->cookie != IPA_HDR_COOKIE) || + ipa3_check_idr_if_freed(entry->hdr)) { + IPAERR_RL("Header entry already deleted\n"); + return -EPERM; + } + } else if (entry->proc_ctx) { + hdr_proc_entry = ipa3_id_find(entry->rule.hdr_proc_ctx_hdl); + if (!hdr_proc_entry || + (hdr_proc_entry->cookie != IPA_PROC_HDR_COOKIE) || + ipa3_check_idr_if_freed(entry->proc_ctx)) { + IPAERR_RL("Proc header entry already deleted\n"); + return -EPERM; + } + } + + if (entry->hdr) + entry->hdr->ref_cnt--; + else if (entry->proc_ctx) + entry->proc_ctx->ref_cnt--; + + entry->rule = rtrule->rule; + entry->hdr = hdr; + entry->proc_ctx = proc_ctx; + + if (entry->hdr) + entry->hdr->ref_cnt++; + if (entry->proc_ctx) + entry->proc_ctx->ref_cnt++; + + entry->hw_len = 0; + entry->prio = 0; + if (rtrule->rule.enable_stats) + entry->cnt_idx = rtrule->rule.cnt_idx; + else + entry->cnt_idx = 0; + return 0; + +error: + return -EPERM; +} + +/** + * ipa3_mdfy_rt_rule() - Modify the specified routing rules in SW and optionally + * commit to IPA HW + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_mdfy_rt_rule(struct ipa_ioc_mdfy_rt_rule *hdls) +{ + int i; + int result; + struct ipa_rt_rule_mdfy_i rule; + + if (hdls == NULL || hdls->num_rules == 0 || hdls->ip >= IPA_IP_MAX) { + IPAERR_RL("bad param\n"); + return -EINVAL; + } + + mutex_lock(&ipa3_ctx->lock); + for (i = 0; i < hdls->num_rules; i++) { + /* if hashing not supported, all tables are non-hash tables*/ + if (ipa3_ctx->ipa_fltrt_not_hashable) + hdls->rules[i].rule.hashable = false; + __ipa_convert_rt_mdfy_in(hdls->rules[i], &rule); + if (__ipa_mdfy_rt_rule(&rule)) { + IPAERR_RL("failed to mdfy rt rule %i\n", i); + hdls->rules[i].status = IPA_RT_STATUS_OF_MDFY_FAILED; + } else { + hdls->rules[i].status = 0; + __ipa_convert_rt_mdfy_out(rule, &hdls->rules[i]); + } + } + + if (hdls->commit) + if (ipa3_ctx->ctrl->ipa3_commit_rt(hdls->ip)) { + result = -EPERM; + goto bail; + } + result = 0; +bail: + mutex_unlock(&ipa3_ctx->lock); + + return result; +} + +/** + * ipa3_mdfy_rt_rule_v2() - Modify the specified routing rules + * in SW and optionally commit to IPA HW + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_mdfy_rt_rule_v2(struct ipa_ioc_mdfy_rt_rule_v2 *hdls) +{ + int i; + int result; + + if (hdls == NULL || hdls->num_rules == 0 || hdls->ip >= IPA_IP_MAX) { + IPAERR_RL("bad param\n"); + return -EINVAL; + } + + mutex_lock(&ipa3_ctx->lock); + for (i = 0; i < hdls->num_rules; i++) { + /* if hashing not supported, all tables are non-hash tables*/ + if (ipa3_ctx->ipa_fltrt_not_hashable) + ((struct ipa_rt_rule_mdfy_i *) + hdls->rules)[i].rule.hashable = false; + if (__ipa_mdfy_rt_rule(&(((struct ipa_rt_rule_mdfy_i *) + hdls->rules)[i]))) { + IPAERR_RL("failed to mdfy rt rule %i\n", i); + ((struct ipa_rt_rule_mdfy_i *) + hdls->rules)[i].status = IPA_RT_STATUS_OF_MDFY_FAILED; + } else { + ((struct ipa_rt_rule_mdfy_i *) + hdls->rules)[i].status = 0; + } + } + + if (hdls->commit) + if (ipa3_ctx->ctrl->ipa3_commit_rt(hdls->ip)) { + result = -EPERM; + goto bail; + } + result = 0; +bail: + mutex_unlock(&ipa3_ctx->lock); + + return result; +} + +/** + * ipa3_set_rt_tuple_mask() - Sets the rt tuple masking for the given tbl + * table index must be for AP EP (not modem) + * updates the the routing masking values without changing the flt ones. + * + * @tbl_idx: routing table index to configure the tuple masking + * @tuple: the tuple members masking + * Returns: 0 on success, negative on failure + * + */ +int ipa3_set_rt_tuple_mask(int tbl_idx, struct ipahal_reg_hash_tuple *tuple) +{ + if (!tuple) { + IPAERR_RL("bad tuple\n"); + return -EINVAL; + } + + if (tbl_idx >= + max(IPA_MEM_PART(v6_rt_num_index), + IPA_MEM_PART(v4_rt_num_index)) || + tbl_idx < 0) { + IPAERR_RL("bad table index\n"); + return -EINVAL; + } + + if (tbl_idx >= IPA_MEM_PART(v4_modem_rt_index_lo) && + tbl_idx <= IPA_MEM_PART(v4_modem_rt_index_hi)) { + IPAERR_RL("cannot configure modem v4 rt tuple by AP\n"); + return -EINVAL; + } + + if (tbl_idx >= IPA_MEM_PART(v6_modem_rt_index_lo) && + tbl_idx <= IPA_MEM_PART(v6_modem_rt_index_hi)) { + IPAERR_RL("cannot configure modem v6 rt tuple by AP\n"); + return -EINVAL; + } + + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0) { + struct ipahal_reg_fltrt_cache_tuple cache_tuple; + + ipahal_read_reg_n_fields(IPA_ROUTER_CACHE_CFG_n, + tbl_idx, &cache_tuple); + cache_tuple.tuple = *tuple; + ipahal_write_reg_n_fields(IPA_ROUTER_CACHE_CFG_n, + tbl_idx, &cache_tuple); + } else { + struct ipahal_reg_fltrt_hash_tuple hash_tuple; + + ipahal_read_reg_n_fields(IPA_ENDP_FILTER_ROUTER_HSH_CFG_n, + tbl_idx, &hash_tuple); + hash_tuple.rt = *tuple; + ipahal_write_reg_n_fields(IPA_ENDP_FILTER_ROUTER_HSH_CFG_n, + tbl_idx, &hash_tuple); + } + + return 0; +} + +/** + * ipa3_rt_read_tbl_from_hw() -Read routing table from IPA HW + * @tbl_idx: routing table index + * @ip_type: IPv4 or IPv6 table + * @hashable: hashable or non-hashable table + * @entry: array to fill the table entries + * @num_entry: number of entries in entry array. set by the caller to indicate + * entry array size. Then set by this function as an output parameter to + * indicate the number of entries in the array + * + * This function reads the routing table from IPA SRAM and prepares an array + * of entries. This function is mainly used for debugging purposes. + * + * If empty table or Modem Apps table, zero entries will be returned. + * + * Returns: 0 on success, negative on failure + */ +int ipa3_rt_read_tbl_from_hw(u32 tbl_idx, enum ipa_ip_type ip_type, + bool hashable, struct ipahal_rt_rule_entry entry[], int *num_entry) +{ + void *ipa_sram_mmio; + u64 hdr_base_ofst; + int res = 0; + u64 tbl_addr; + bool is_sys; + struct ipa_mem_buffer *sys_tbl_mem; + u8 *rule_addr; + int rule_idx; + + IPADBG_LOW("tbl_idx=%d ip_t=%d hash=%d entry=0x%pK num_entry=0x%pK\n", + tbl_idx, ip_type, hashable, entry, num_entry); + + /* + * SRAM memory not allocated to hash tables. Reading of hash table + * rules operation not supported + */ + if (hashable && ipa3_ctx->ipa_fltrt_not_hashable) { + IPADBG("Reading hashable rules not supported\n"); + *num_entry = 0; + return 0; + } + + if (ip_type == IPA_IP_v4 && tbl_idx >= IPA_MEM_PART(v4_rt_num_index)) { + IPAERR_RL("Invalid params\n"); + return -EFAULT; + } + + if (ip_type == IPA_IP_v6 && tbl_idx >= IPA_MEM_PART(v6_rt_num_index)) { + IPAERR_RL("Invalid params\n"); + return -EFAULT; + } + + /* map IPA SRAM */ + ipa_sram_mmio = ioremap(ipa3_ctx->ipa_wrapper_base + + ipa3_ctx->ctrl->ipa_reg_base_ofst + + ipahal_get_reg_n_ofst(IPA_SW_AREA_RAM_DIRECT_ACCESS_n, + ipa3_ctx->smem_restricted_bytes / 4), + ipa3_ctx->smem_sz); + if (!ipa_sram_mmio) { + IPAERR("fail to ioremap IPA SRAM\n"); + return -ENOMEM; + } + + memset(entry, 0, sizeof(*entry) * (*num_entry)); + if (hashable) { + if (ip_type == IPA_IP_v4) + hdr_base_ofst = + IPA_MEM_PART(v4_rt_hash_ofst); + else + hdr_base_ofst = + IPA_MEM_PART(v6_rt_hash_ofst); + } else { + if (ip_type == IPA_IP_v4) + hdr_base_ofst = + IPA_MEM_PART(v4_rt_nhash_ofst); + else + hdr_base_ofst = + IPA_MEM_PART(v6_rt_nhash_ofst); + } + + IPADBG_LOW("hdr_base_ofst=0x%llx\n", hdr_base_ofst); + + res = ipahal_fltrt_read_addr_from_hdr(ipa_sram_mmio + hdr_base_ofst, + tbl_idx, &tbl_addr, &is_sys); + if (res) { + IPAERR("failed to read table address from header structure\n"); + goto bail; + } + IPADBG_LOW("rt tbl %d: tbl_addr=0x%llx is_sys=%d\n", + tbl_idx, tbl_addr, is_sys); + if (!tbl_addr) { + IPAERR("invalid rt tbl addr\n"); + res = -EFAULT; + goto bail; + } + + /* for tables which reside in DDR access it from the virtual memory */ + if (is_sys) { + struct ipa3_rt_tbl_set *set; + struct ipa3_rt_tbl *tbl; + + set = &ipa3_ctx->rt_tbl_set[ip_type]; + rule_addr = NULL; + list_for_each_entry(tbl, &set->head_rt_tbl_list, link) { + if (tbl->idx == tbl_idx) { + sys_tbl_mem = &(tbl->curr_mem[hashable ? + IPA_RULE_HASHABLE : + IPA_RULE_NON_HASHABLE]); + if (sys_tbl_mem->phys_base && + sys_tbl_mem->phys_base != tbl_addr) { + IPAERR("mismatch:parsed=%llx sw=%pad\n" + , tbl_addr, + &sys_tbl_mem->phys_base); + } + if (sys_tbl_mem->phys_base) + rule_addr = sys_tbl_mem->base; + else + rule_addr = NULL; + } + } + } else { + rule_addr = ipa_sram_mmio + hdr_base_ofst + tbl_addr; + } + + IPADBG_LOW("First rule addr 0x%pK\n", rule_addr); + + if (!rule_addr) { + /* Modem table in system memory or empty table */ + *num_entry = 0; + goto bail; + } + + rule_idx = 0; + while (rule_idx < *num_entry) { + res = ipahal_rt_parse_hw_rule(rule_addr, &entry[rule_idx]); + if (res) { + IPAERR("failed parsing rt rule\n"); + goto bail; + } + + IPADBG_LOW("rule_size=%d\n", entry[rule_idx].rule_size); + if (!entry[rule_idx].rule_size) + break; + + rule_addr += entry[rule_idx].rule_size; + rule_idx++; + } + *num_entry = rule_idx; +bail: + iounmap(ipa_sram_mmio); + return res; +} + +/** + * ipa3_set_nat_conn_track_exc_rt_tbl() - Set the exception routing handle + * @rt_tbl_hdl: [in] the routing table handle to be set + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_set_nat_conn_track_exc_rt_tbl(u32 rt_tbl_hdl, enum ipa_ip_type ip) +{ + struct ipa3_rt_tbl *entry; + int result = 0; + + if (((ip != IPA_IP_v4) && (ip != IPA_IP_v6)) || + (ipa3_ctx->ipa_hw_type < IPA_HW_v5_5)) { + IPAERR_RL("bad params: %d,\n", ip); + return -EINVAL; + } + + mutex_lock(&ipa3_ctx->lock); + entry = ipa3_id_find(rt_tbl_hdl); + if (entry == NULL) { + IPAERR_RL("lookup failed\n"); + result = -EINVAL; + goto ret; + } + + if ((entry->cookie != IPA_RT_TBL_COOKIE) || entry->ref_cnt == 0) { + IPAERR_RL("bad params\n"); + result = -EINVAL; + goto ret; + } + + if (ip == IPA_IP_v4) + ipahal_write_reg_mn(IPA_IPV4_NAT_EXC_SUPPRESS_ROUT_TABLE_INDX, + 0, 0, entry->idx); + else + ipahal_write_reg_mn(IPA_IPV6_CONN_TRACK_EXC_SUPPRESS_ROUT_TABLE_INDX, + 0, 0, entry->idx); + + IPADBG("Set exception routing table for %d, ID: %d", ip, entry->idx); + + result = 0; + +ret: + mutex_unlock(&ipa3_ctx->lock); + + return result; +} + diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_rtp_genl.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_rtp_genl.c new file mode 100644 index 0000000000..1a860f24bd --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_rtp_genl.c @@ -0,0 +1,908 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ipa_rtp_genl.h" +#include "ipa_i.h" +#include +#include +#include + +#define MAX_OPEN_FRAMES 3 +/* Single-NAL:0, FU-A Type: 1 */ +#define MAX_STREAM_TYPES 2 +#define MAX_IP_TYPES 2 + +#define IPA_RTP_RT_TBL_NAME "ipa_rtp_rt" + +#define IPA_RTP_GENL_OP(_cmd, _func) \ + { \ + .cmd = _cmd, \ + .doit = _func, \ + .dumpit = NULL, \ + .flags = 0, \ + } + +static u8 ipa_rtp_active_streams[MAX_STREAMS]; + +static struct nla_policy ipa_rtp_genl_attr_policy[IPA_RTP_GENL_ATTR_MAX + 1] = { + [IPA_RTP_GENL_ATTR_STR] = { .type = NLA_NUL_STRING, .len = IPA_RTP_GENL_MAX_STR_LEN }, + [IPA_RTP_GENL_ATTR_INT] = { .type = NLA_S32 }, + [IPA_RTP_GENL_ATTR_TUPLE_INFO] = NLA_POLICY_EXACT_LEN(sizeof(struct traffic_tuple_info)), + [IPA_RTP_GENL_ATTR_ASSIGN_STREAM_ID] = + NLA_POLICY_EXACT_LEN(sizeof(struct assign_stream_id)), + [IPA_RTP_GENL_ATTR_ADD_BITSTREAM_BUFF] = + NLA_POLICY_EXACT_LEN(sizeof(struct bitstream_buffers)), + [IPA_RTP_GENL_ATTR_SMMU_MAP_BUFF] = NLA_POLICY_EXACT_LEN(sizeof(struct map_buffer)), + [IPA_RTP_GENL_ATTR_SMMU_UNMAP_BUFF] = NLA_POLICY_EXACT_LEN(sizeof(struct unmap_buffer)), + [IPA_RTP_GENL_ATTR_REMOVE_STREAM_ID] = + NLA_POLICY_EXACT_LEN(sizeof(struct remove_bitstream_buffers)), +}; + +static const struct genl_ops ipa_rtp_genl_ops[] = { + IPA_RTP_GENL_OP(IPA_RTP_GENL_CMD_TUPLE_INFO, + ipa_rtp_tuple_info_req_hdlr), + IPA_RTP_GENL_OP(IPA_RTP_GENL_CMD_ADD_BITSTREAM_BUFF, + ipa_rtp_add_bitstream_buff_req_hdlr), + IPA_RTP_GENL_OP(IPA_RTP_GENL_CMD_SMMU_MAP_BUFF, + ipa_rtp_smmu_map_buff_req_hdlr), + IPA_RTP_GENL_OP(IPA_RTP_GENL_CMD_SMMU_UNMAP_BUFF, + ipa_rtp_smmu_unmap_buff_req_hdlr), + IPA_RTP_GENL_OP(IPA_RTP_GENL_CMD_REMOVE_STREAM_ID, + ipa_rtp_rmv_stream_id_req_hdlr), +}; + +struct genl_family ipa_rtp_genl_family = { + .id = 0, + .hdrsize = 0, + .name = IPA_RTP_GENL_FAMILY_NAME, + .version = IPA_RTP_GENL_VERSION, + .maxattr = IPA_RTP_GENL_ATTR_MAX, + .policy = ipa_rtp_genl_attr_policy, + .ops = ipa_rtp_genl_ops, + .n_ops = ARRAY_SIZE(ipa_rtp_genl_ops), +}; + +static enum ipa_hdr_proc_type ipa3_get_rtp_hdr_proc_type(u32 stream_id) +{ + enum ipa_hdr_proc_type rtp_hdr_proc_type = IPA_HDR_PROC_MAX; + + switch (stream_id) { + case 0: + rtp_hdr_proc_type = IPA_HDR_PROC_RTP_METADATA_STREAM0; + break; + case 1: + rtp_hdr_proc_type = IPA_HDR_PROC_RTP_METADATA_STREAM1; + break; + case 2: + rtp_hdr_proc_type = IPA_HDR_PROC_RTP_METADATA_STREAM2; + break; + case 3: + rtp_hdr_proc_type = IPA_HDR_PROC_RTP_METADATA_STREAM3; + break; + default: + IPAERR("invalid stream_id %u params\n", stream_id); + break; + } + return rtp_hdr_proc_type; +} + +static enum ipa_client_type ipa3_get_rtp_dst_pipe(u32 stream_id) +{ + enum ipa_client_type dst_pipe_num = IPA_CLIENT_MAX; + + switch (stream_id) { + case 0: + dst_pipe_num = IPA_CLIENT_UC_RTP1_CONS; + break; + case 1: + dst_pipe_num = IPA_CLIENT_UC_RTP2_CONS; + break; + case 2: + dst_pipe_num = IPA_CLIENT_UC_RTP3_CONS; + break; + case 3: + dst_pipe_num = IPA_CLIENT_UC_RTP4_CONS; + break; + default: + IPAERR("invalid stream_id %u params\n", stream_id); + break; + } + return dst_pipe_num; +} + +static int ipa3_rtp_del_flt_rule(u32 stream_id) +{ + int rc = 0; + int ipa_ep_idx; + struct ipa3_ep_context *ep; + struct ipa_ioc_del_flt_rule *rtp_del_flt_rule = NULL; + + rtp_del_flt_rule = kzalloc(sizeof(*rtp_del_flt_rule) + + 1 * sizeof(struct ipa_flt_rule_del), GFP_KERNEL); + if (!rtp_del_flt_rule) { + IPAERR("failed at kzalloc of rtp_del_flt_rule\n"); + rc = -ENOMEM; + return rc; + } + + ipa_ep_idx = ipa_get_ep_mapping(IPA_CLIENT_WLAN2_PROD); + ep = &ipa3_ctx->ep[ipa_ep_idx]; + + /* check whether filter rule hdl is deleted or not */ + if (ep->rtp_flt4_rule_hdls[stream_id] != -1) { + IPADBG("Deleting rtp filter rules of stream_id: %u\n", stream_id); + rtp_del_flt_rule->commit = 1; + rtp_del_flt_rule->ip = 0; + rtp_del_flt_rule->num_hdls = 1; + rtp_del_flt_rule->hdl[0].hdl = ep->rtp_flt4_rule_hdls[stream_id]; + if (ipa3_del_flt_rule(rtp_del_flt_rule) || rtp_del_flt_rule->hdl[0].status) { + IPAERR("failed to del rtp_flt_rule\n"); + kfree(rtp_del_flt_rule); + rc = -EPERM; + return rc; + } + ep->rtp_flt4_rule_hdls[stream_id] = -1; + } + + kfree(rtp_del_flt_rule); + return rc; +} + +static int ipa3_rtp_del_rt_rule(u32 stream_id) +{ + int rc = 0; + struct ipa_ioc_del_rt_rule *rtp_del_rt_rule = NULL; + + rtp_del_rt_rule = kzalloc(sizeof(*rtp_del_rt_rule) + + 1 * sizeof(struct ipa_rt_rule_del), GFP_KERNEL); + if (!rtp_del_rt_rule) { + IPAERR("failed at kzalloc of rtp_del_rt_rule\n"); + rc = -ENOMEM; + return rc; + } + + /* check whether route rule hdl is deleted or not */ + if (ipa3_ctx->rtp_rt4_rule_hdls[stream_id] != -1) { + IPADBG("Deleting rtp route rules of stream_id: %u\n", stream_id); + rtp_del_rt_rule->commit = 1; + rtp_del_rt_rule->ip = 0; + rtp_del_rt_rule->num_hdls = 1; + rtp_del_rt_rule->hdl[0].hdl = ipa3_ctx->rtp_rt4_rule_hdls[stream_id]; + if (ipa3_del_rt_rule(rtp_del_rt_rule) || rtp_del_rt_rule->hdl[0].status) { + IPAERR("failed to del rtp_rt_rule\n"); + kfree(rtp_del_rt_rule); + rc = -EPERM; + return rc; + } + ipa3_ctx->rtp_rt4_rule_hdls[stream_id] = -1; + } + + kfree(rtp_del_rt_rule); + return rc; +} + +static int ipa3_rtp_del_hdr_proc_ctx(u32 stream_id) +{ + int buf_size, rc = 0; + + struct ipa_ioc_del_hdr_proc_ctx *rtp_del_proc_ctx = NULL; + struct ipa_hdr_proc_ctx_del *rtp_del_proc_ctx_entry = NULL; + + buf_size = (sizeof(struct ipa_ioc_del_hdr_proc_ctx) + + (sizeof(struct ipa_hdr_proc_ctx_del))); + rtp_del_proc_ctx = kzalloc(buf_size, GFP_KERNEL); + if (!rtp_del_proc_ctx) { + IPAERR("failed at kzalloc of rtp_del_proc_ctx\n"); + rc = -ENOMEM; + return rc; + } + + /* check whether hdr proc ctx hdl is deleted or not */ + if (ipa3_ctx->rtp_proc_hdls[stream_id] != -1) { + IPADBG("Deleting rtp hdr proc ctx of stream_id: %u\n", stream_id); + rtp_del_proc_ctx_entry = &(rtp_del_proc_ctx->hdl[0]); + rtp_del_proc_ctx->commit = 1; + rtp_del_proc_ctx->num_hdls = 1; + rtp_del_proc_ctx->hdl[0].hdl = ipa3_ctx->rtp_proc_hdls[stream_id]; + if (ipa3_del_hdr_proc_ctx(rtp_del_proc_ctx) || rtp_del_proc_ctx->hdl[0].status) { + IPAERR("failed to del rtp proc ctx hdl\n"); + kfree(rtp_del_proc_ctx); + rc = -EPERM; + return rc; + } + ipa3_ctx->rtp_proc_hdls[stream_id] = -1; + } + + kfree(rtp_del_proc_ctx); + return rc; +} + +int ipa3_install_rtp_hdr_proc_rt_flt_rules(struct traffic_tuple_info *tuple_info, u32 stream_id) +{ + int rc = 0; + int buf_size; + static const int num_of_proc_ctx = 1; + struct ipa_ioc_add_hdr_proc_ctx *rtp_proc_ctx = NULL; + struct ipa_hdr_proc_ctx_add *rtp_proc_ctx_entry = NULL; + struct ipa_rtp_hdr_proc_ctx_params rtp_params; + + struct ipa_ioc_add_rt_rule *rtp_rt_rule = NULL; + struct ipa_rt_rule_add *rtp_rt_rule_entry = NULL; + struct ipa3_rt_tbl *entry = NULL; + + struct ipa3_ep_context *ep; + struct ipa_ioc_add_flt_rule *rtp_flt_rule = NULL; + struct ipa_flt_rule_add *rtp_flt_rule_entry = NULL; + int ipa_ep_idx = 0; + + IPADBG("adding rtp proc ctx entry\n"); + buf_size = (sizeof(struct ipa_ioc_add_hdr_proc_ctx) + + (num_of_proc_ctx * sizeof(struct ipa_hdr_proc_ctx_add))); + + rtp_proc_ctx = kzalloc(buf_size, GFP_KERNEL); + if (!rtp_proc_ctx) { + IPAERR("failed at kzalloc of rtp_proc_ctx\n"); + rc = -ENOMEM; + return rc; + } + + memset(rtp_proc_ctx, 0, sizeof(*rtp_proc_ctx)); + + rtp_proc_ctx_entry = &(rtp_proc_ctx->proc_ctx[0]); + rtp_proc_ctx->commit = true; + rtp_proc_ctx->num_proc_ctxs = num_of_proc_ctx; + rtp_proc_ctx_entry->proc_ctx_hdl = -1; + rtp_proc_ctx_entry->status = -1; + if (ipa3_get_rtp_hdr_proc_type(stream_id) >= IPA_HDR_PROC_MAX) { + IPAERR("invalid stream_id %u params\n", stream_id); + rc = -EPERM; + goto free_rtp_proc_ctx; + } + rtp_proc_ctx_entry->type = ipa3_get_rtp_hdr_proc_type(stream_id); + rtp_params.hdr_add_param.input_ip_version = tuple_info->ip_type; + + if (ipa3_add_rtp_hdr_proc_ctx(rtp_proc_ctx, rtp_params, false) + || rtp_proc_ctx_entry->status) { + IPAERR("failed to add rtp hdr proc ctx hdl\n"); + rc = -EPERM; + goto free_rtp_proc_ctx; + } + + IPADBG("rtp proc ctx hdl = %u\n", rtp_proc_ctx_entry->proc_ctx_hdl); + ipa3_ctx->rtp_proc_hdls[stream_id] = rtp_proc_ctx_entry->proc_ctx_hdl; + + IPADBG("adding rtp route rule entry\n"); + + rtp_rt_rule = kzalloc(sizeof(struct ipa_ioc_add_rt_rule) + 1 * + sizeof(struct ipa_rt_rule_add), GFP_KERNEL); + if (!rtp_rt_rule) { + IPAERR("failed at kzalloc of rtp_rt_rule\n"); + rc = -ENOMEM; + goto free_rtp_proc_ctx; + } + + memset(rtp_rt_rule, 0, sizeof(*rtp_rt_rule)); + rtp_rt_rule->num_rules = 1; + rtp_rt_rule->commit = 1; + rtp_rt_rule->ip = tuple_info->ip_type; + strscpy(rtp_rt_rule->rt_tbl_name, IPA_RTP_RT_TBL_NAME, + IPA_RESOURCE_NAME_MAX); + + rtp_rt_rule_entry = &rtp_rt_rule->rules[0]; + rtp_rt_rule_entry->at_rear = 1; + if (ipa3_get_rtp_dst_pipe(stream_id) >= IPA_CLIENT_MAX) { + IPAERR("invalid stream_id %u params\n", stream_id); + rc = -EPERM; + goto free_rtp_rt_rule; + } + rtp_rt_rule_entry->rule.dst = ipa3_get_rtp_dst_pipe(stream_id); + rtp_rt_rule_entry->rule.hdr_hdl = 0; + rtp_rt_rule_entry->rule.hdr_proc_ctx_hdl = ipa3_ctx->rtp_proc_hdls[stream_id]; + rtp_rt_rule_entry->rule.hashable = 1; + rtp_rt_rule_entry->rule.retain_hdr = 1; + rtp_rt_rule_entry->status = -1; + + if (ipa_add_rt_rule(rtp_rt_rule) || rtp_rt_rule_entry->status) { + IPAERR("fail to add rtp_rt_rule\n"); + rc = -EPERM; + goto free_rtp_rt_rule; + } + + ipa3_ctx->rtp_rt4_rule_hdls[stream_id] = rtp_rt_rule_entry->rt_rule_hdl; + rtp_rt_rule->rt_tbl_name[IPA_RESOURCE_NAME_MAX-1] = '\0'; + entry = __ipa3_find_rt_tbl(tuple_info->ip_type, rtp_rt_rule->rt_tbl_name); + ipa3_ctx->rtp_rt4_tbl_idxs[stream_id] = entry->idx; + ipa3_ctx->rtp_rt4_tbl_hdls[stream_id] = entry->id; + + IPADBG("rtp rt rule hdl %d\n", ipa3_ctx->rtp_rt4_rule_hdls[stream_id]); + IPADBG("rtp rt tbl idx %d\n", ipa3_ctx->rtp_rt4_tbl_idxs[stream_id]); + IPADBG("rtp rt tbl hdl %d\n", ipa3_ctx->rtp_rt4_tbl_hdls[stream_id]); + + IPADBG("adding rtp flt rules for %d\n", ipa_ep_idx); + + rtp_flt_rule = kzalloc(sizeof(*rtp_flt_rule) + + 1 * sizeof(struct ipa_flt_rule_add), GFP_KERNEL); + if (!rtp_flt_rule) { + IPAERR("failed at kzalloc of rtp_flt_rule\n"); + rc = -ENOMEM; + goto free_rtp_rt_rule; + } + + memset(rtp_flt_rule, 0, sizeof(*rtp_flt_rule)); + ipa_ep_idx = ipa_get_ep_mapping(IPA_CLIENT_WLAN2_PROD); + ep = &ipa3_ctx->ep[ipa_ep_idx]; + + rtp_flt_rule->commit = 1; + rtp_flt_rule->ip = tuple_info->ip_type; + rtp_flt_rule->ep = IPA_CLIENT_WLAN2_PROD; + rtp_flt_rule->num_rules = 1; + rtp_flt_rule->rules[0].at_rear = 1; + rtp_flt_rule_entry = &rtp_flt_rule->rules[0]; + + rtp_flt_rule_entry->rule.hashable = 1; + rtp_flt_rule_entry->status = -1; + rtp_flt_rule_entry->rule.action = IPA_PASS_TO_ROUTING; + rtp_flt_rule_entry->rule.rt_tbl_hdl = ipa3_ctx->rtp_rt4_tbl_hdls[stream_id]; + rtp_flt_rule_entry->rule.rt_tbl_idx = ipa3_ctx->rtp_rt4_tbl_idxs[stream_id]; + + rtp_flt_rule_entry->rule.attrib.u.v4.dst_addr_mask = 0xFFFFFFFF; + rtp_flt_rule_entry->rule.attrib.u.v4.dst_addr = tuple_info->ip_info.ipv4.dst_ip; + rtp_flt_rule_entry->rule.attrib.u.v4.src_addr_mask = 0xFFFFFFFF; + rtp_flt_rule_entry->rule.attrib.u.v4.src_addr = tuple_info->ip_info.ipv4.src_ip; + rtp_flt_rule_entry->rule.attrib.u.v4.protocol = tuple_info->ip_info.ipv4.protocol; + rtp_flt_rule_entry->rule.attrib.src_port = tuple_info->ip_info.ipv4.src_port_number; + rtp_flt_rule_entry->rule.attrib.dst_port = tuple_info->ip_info.ipv4.dst_port_number; + + rtp_flt_rule_entry->rule.attrib.attrib_mask |= IPA_FLT_SRC_ADDR; + rtp_flt_rule_entry->rule.attrib.attrib_mask |= IPA_FLT_DST_ADDR; + rtp_flt_rule_entry->rule.attrib.attrib_mask |= IPA_FLT_PROTOCOL; + rtp_flt_rule_entry->rule.attrib.attrib_mask |= IPA_FLT_SRC_PORT; + rtp_flt_rule_entry->rule.attrib.attrib_mask |= IPA_FLT_DST_PORT; + + if (ipa3_add_flt_rule(rtp_flt_rule) || rtp_flt_rule_entry->status) { + IPAERR("fail to add rtp_flt_rule\n"); + rc = -EPERM; + goto free_rtp_flt_rule; + } + + ep->rtp_flt4_rule_hdls[stream_id] = rtp_flt_rule->rules[0].flt_rule_hdl; + IPADBG("rtp flt rule hdl is %u\n", ep->rtp_flt4_rule_hdls[stream_id]); + +free_rtp_flt_rule: + kfree(rtp_flt_rule); +free_rtp_rt_rule: + if (rc && !rtp_rt_rule_entry->status) + ipa3_rtp_del_rt_rule(stream_id); + kfree(rtp_rt_rule); +free_rtp_proc_ctx: + if (rc && !rtp_proc_ctx_entry->status) + ipa3_rtp_del_hdr_proc_ctx(stream_id); + kfree(rtp_proc_ctx); + return rc; +} + +int ipa3_delete_rtp_hdr_proc_rt_flt_rules(u32 stream_id) +{ + int rc = 0; + + if (ipa3_rtp_del_flt_rule(stream_id) || + ipa3_rtp_del_rt_rule(stream_id) || + ipa3_rtp_del_hdr_proc_ctx(stream_id)) { + IPAERR("failed to delete rtp hdr proc rt flt rules\n"); + rc = -EPERM; + } + return rc; +} + +int ipa_rtp_send_tuple_info_resp(struct genl_info *info, + struct assign_stream_id *tuple_info_resp) +{ + struct sk_buff *skb; + void *msg_head; + int rc = -1; + + IPADBG_LOW("Entry\n"); + + if (!info || !tuple_info_resp) { + IPAERR("Invalid params\n"); + return rc; + } + + skb = genlmsg_new(sizeof(struct assign_stream_id), GFP_KERNEL); + if (!skb) { + IPAERR("failed to alloc genmsg_new\n"); + return rc; + } + + msg_head = genlmsg_put(skb, 0, info->snd_seq, + &ipa_rtp_genl_family, + 0, IPA_RTP_GENL_CMD_ASSIGN_STREAM_ID); + if (!msg_head) { + IPAERR("failed at genlmsg_put\n"); + goto free_skb; + } + + rc = nla_put(skb, IPA_RTP_GENL_ATTR_ASSIGN_STREAM_ID, + sizeof(struct assign_stream_id), + tuple_info_resp); + if (rc != 0) { + IPAERR("failed at nla_put skb\n"); + goto free_skb; + } + + genlmsg_end(skb, msg_head); + + rc = genlmsg_unicast(genl_info_net(info), skb, info->snd_portid); + if (rc != 0) { + IPAERR("failed in doing genlmsg_unicast\n"); + goto free_skb; + } + + ipa3_ctx->rtp_stream_id_cnt++; + IPADBG("assigned stream-id is %u\n", tuple_info_resp->stream_id); + IPADBG_LOW("Exit\n"); + return rc; + +free_skb: + kfree(skb); + return rc; +} + +int ipa_rtp_tuple_info_req_hdlr(struct sk_buff *skb_2, + struct genl_info *info) +{ + struct nlattr *na; + struct traffic_tuple_info tuple_info_req; + struct assign_stream_id tuple_info_resp; + struct remove_bitstream_buffers rmv_sid_req; + int is_req_valid = 0, i = 0; + int stream_id_available = 0, rc = -1; + + IPADBG("Entry\n"); + + if (!info) { + IPAERR("error genl info is null\n"); + return rc; + } + + na = info->attrs[IPA_RTP_GENL_ATTR_TUPLE_INFO]; + if (na) { + if (nla_memcpy(&tuple_info_req, na, + sizeof(tuple_info_req)) > 0) { + is_req_valid = 1; + } else { + IPAERR("nla_memcpy failed %d\n", + IPA_RTP_GENL_ATTR_TUPLE_INFO); + return rc; + } + } else { + IPAERR("no info->attrs %d\n", + IPA_RTP_GENL_ATTR_TUPLE_INFO); + return rc; + } + + if (tuple_info_req.ts_info.no_of_openframe <= 0 || + tuple_info_req.ts_info.no_of_openframe > MAX_OPEN_FRAMES || + tuple_info_req.ts_info.stream_type >= MAX_STREAM_TYPES || + !tuple_info_req.ts_info.max_pkt_frame || + tuple_info_req.ip_type >= MAX_IP_TYPES) { + IPAERR("invalid no-of-open-frames %u or stream_type %u\n", + tuple_info_req.ts_info.no_of_openframe, + tuple_info_req.ts_info.stream_type); + IPAERR("or max_pkt_frames %u or ip_type %u params\n", + tuple_info_req.ts_info.max_pkt_frame, + tuple_info_req.ip_type); + return rc; + } + + /* IPv4 Type */ + if (!tuple_info_req.ip_type) { + if (tuple_info_req.ip_info.ipv4.protocol != IPPROTO_UDP || + !tuple_info_req.ip_info.ipv4.src_ip || + !tuple_info_req.ip_info.ipv4.dst_ip) { + IPAERR("invalid src_ip %u or dst_ip %u or protocol %u params\n", + tuple_info_req.ip_info.ipv4.src_ip, tuple_info_req.ip_info.ipv4.dst_ip, + tuple_info_req.ip_info.ipv4.protocol); + return rc; + } + } else { + if (tuple_info_req.ip_info.ipv6.protocol != IPPROTO_UDP) { + IPAERR("invalid ipv6 protocol %u params\n", + tuple_info_req.ip_info.ipv6.protocol); + return rc; + } + } + + IPADBG_LOW("no_of_openframes are %u\n", tuple_info_req.ts_info.no_of_openframe); + IPADBG_LOW("max_pkt_frame is %u\n", tuple_info_req.ts_info.max_pkt_frame); + IPADBG_LOW("stream_type is %u\n", tuple_info_req.ts_info.stream_type); + IPADBG_LOW("reorder_timeout is %u\n", tuple_info_req.ts_info.reorder_timeout); + IPADBG_LOW("num_slices_per_frame are %u\n", tuple_info_req.ts_info.num_slices_per_frame); + IPADBG_LOW("ip_type is %u\n", tuple_info_req.ip_type); + IPADBG_LOW("src_port_number is %u\n", tuple_info_req.ip_info.ipv4.src_port_number); + IPADBG_LOW("dst_port_number is %u\n", tuple_info_req.ip_info.ipv4.dst_port_number); + IPADBG_LOW("src_ip is %u\n", tuple_info_req.ip_info.ipv4.src_ip); + IPADBG_LOW("dst_ip is %u\n", tuple_info_req.ip_info.ipv4.dst_ip); + IPADBG_LOW("protocol is %u\n", tuple_info_req.ip_info.ipv4.protocol); + + memset(&tuple_info_resp, 0, sizeof(tuple_info_resp)); + + for (i = 0; i < MAX_STREAMS; i++) { + if (ipa_rtp_active_streams[i] == 0) { + tuple_info_resp.stream_id = i; + stream_id_available = 1; + break; + } + } + + if (!stream_id_available) { + IPAERR("max stream-ids supported are %u only\n", MAX_STREAMS); + return rc; + } + + /* Call IPA driver/uC tuple info API's here */ + if (ipa3_install_rtp_hdr_proc_rt_flt_rules(&tuple_info_req, tuple_info_resp.stream_id) || + ipa3_tuple_info_cmd_to_wlan_uc(&tuple_info_req, tuple_info_resp.stream_id)) { + IPAERR("failed to install hdr proc and flt rules or filters at WLAN\n"); + ipa3_delete_rtp_hdr_proc_rt_flt_rules(tuple_info_resp.stream_id); + return rc; + } + + ipa_rtp_active_streams[tuple_info_resp.stream_id] = 1; + + if (is_req_valid && + ipa_rtp_send_tuple_info_resp(info, &tuple_info_resp)) { + IPAERR("failed in sending stream_id response\n"); + memset(&rmv_sid_req, 0, sizeof(rmv_sid_req)); + rmv_sid_req.stream_id = tuple_info_resp.stream_id; + ipa3_uc_send_remove_stream_cmd(&rmv_sid_req); + ipa3_delete_rtp_hdr_proc_rt_flt_rules(rmv_sid_req.stream_id); + ipa_rtp_active_streams[tuple_info_resp.stream_id] = 0; + } else + rc = 0; + + IPADBG("Exit\n"); + return rc; +} + +int ipa_rtp_smmu_map_buff_req_hdlr(struct sk_buff *skb_2, + struct genl_info *info) +{ + struct nlattr *na; + struct map_buffer map_buffer_req; + int i = 0, is_req_valid = 0; + int rc = -1; + + IPADBG("Entry\n"); + + if (!info) { + IPAERR("error genl info is null\n"); + return rc; + } + + na = info->attrs[IPA_RTP_GENL_ATTR_SMMU_MAP_BUFF]; + if (na) { + if (nla_memcpy(&map_buffer_req, na, + sizeof(map_buffer_req)) > 0) { + is_req_valid = 1; + } else { + IPAERR("nla_memcpy failed %d\n", + IPA_RTP_GENL_ATTR_SMMU_MAP_BUFF); + return rc; + } + } else { + IPAERR("no info->attrs %d\n", + IPA_RTP_GENL_ATTR_SMMU_MAP_BUFF); + return rc; + } + + if (map_buffer_req.nfd <= 0 || map_buffer_req.nfd > MAX_FDS + || map_buffer_req.stream_id > MAX_STREAMS) { + IPAERR("invalid nfd %u or stream_id %u params\n", + map_buffer_req.nfd, map_buffer_req.stream_id); + return rc; + } + + IPADBG_LOW("number of fd's are %u\n", map_buffer_req.nfd); + IPADBG_LOW("stream_id is %u\n", map_buffer_req.stream_id); + + /* If IPA C2 component is providing two fd's for meta fd and bitstream buff fd then + * sizes need to be filled. If it is a single fd for both meta data and bitstream buff + * then meta_buff_fd and bitstream_buffer_fd will be the same. And they need to fill + * bitstream_buffer_size as actual size and meta_buff_size to zero. + */ + + for (i = 0; i < map_buffer_req.nfd; i++) { + if (map_buffer_req.buff_info[i].bitstream_buffer_fd == + map_buffer_req.buff_info[i].meta_buff_fd) { + if (!map_buffer_req.buff_info[i].bitstream_buffer_size || + map_buffer_req.buff_info[i].meta_buff_size) { + IPAERR("invalid bitstream_buff_size %u\n", + map_buffer_req.buff_info[i].bitstream_buffer_size); + IPAERR("or meta_buff_size %u params\n", + map_buffer_req.buff_info[i].meta_buff_size); + return rc; + } + } else { + if (!map_buffer_req.buff_info[i].bitstream_buffer_size || + !map_buffer_req.buff_info[i].meta_buff_size) { + IPAERR("invalid bitstream_buff_size %u\n", + map_buffer_req.buff_info[i].bitstream_buffer_size); + IPAERR("or meta_buff_size %u params\n", + map_buffer_req.buff_info[i].meta_buff_size); + return rc; + } + } + + IPADBG_LOW("bitstream_buffer_fd is %u\n", + map_buffer_req.buff_info[i].bitstream_buffer_fd); + IPADBG_LOW("meta_buff_fd is %u\n", + map_buffer_req.buff_info[i].meta_buff_fd); + IPADBG_LOW("bitstream_buffer_size is %u\n", + map_buffer_req.buff_info[i].bitstream_buffer_size); + IPADBG_LOW("meta_buff_size is %u\n", + map_buffer_req.buff_info[i].meta_buff_size); + } + + /* Call IPA driver/uC API's here */ + if (is_req_valid) + rc = ipa3_map_buff_to_device_addr(&map_buffer_req); + + IPADBG("Exit\n"); + return rc; +} + +int ipa_rtp_smmu_unmap_buff_req_hdlr(struct sk_buff *skb_2, + struct genl_info *info) +{ + struct nlattr *na; + struct unmap_buffer unmap_buffer_req; + int i = 0, is_req_valid = 0, rc = -1; + + IPADBG("Entry\n"); + + if (!info) { + IPAERR("error genl info is null\n"); + return rc; + } + + na = info->attrs[IPA_RTP_GENL_ATTR_SMMU_UNMAP_BUFF]; + if (na) { + if (nla_memcpy(&unmap_buffer_req, na, + sizeof(unmap_buffer_req)) > 0) { + is_req_valid = 1; + } else { + IPAERR("nla_memcpy failed %d\n", + IPA_RTP_GENL_ATTR_SMMU_UNMAP_BUFF); + return rc; + } + } else { + IPAERR("no info->attrs %d\n", + IPA_RTP_GENL_ATTR_SMMU_UNMAP_BUFF); + return rc; + } + + if (unmap_buffer_req.nfd <= 0 || unmap_buffer_req.nfd > MAX_FDS + || unmap_buffer_req.stream_id > MAX_STREAMS) { + IPAERR("invalid nfd %u or stream_id %u params\n", + unmap_buffer_req.nfd, unmap_buffer_req.stream_id); + return rc; + } + + IPADBG_LOW("number of fd's are %u\n", unmap_buffer_req.nfd); + IPADBG_LOW("stream_id is %u\n", unmap_buffer_req.stream_id); + + /* If IPA C2 component is providing two fd's for meta fd and bitstream buff fd then + * sizes need to be filled. If it is a single fd for both meta data and bitstream buff + * then meta_buff_fd and bitstream_buffer_fd will be the same. And they need to fill + * bitstream_buffer_size as actual size and meta_buff_size to zero. + */ + + for (i = 0; i < unmap_buffer_req.nfd; i++) { + if (unmap_buffer_req.buff_info[i].bitstream_buffer_fd == + unmap_buffer_req.buff_info[i].meta_buff_fd) { + if (!unmap_buffer_req.buff_info[i].bitstream_buffer_size || + unmap_buffer_req.buff_info[i].meta_buff_size) { + IPAERR("invalid bitstream_buff_size %u\n", + unmap_buffer_req.buff_info[i].bitstream_buffer_size); + IPAERR("or meta_buff_size %u params\n", + unmap_buffer_req.buff_info[i].meta_buff_size); + return rc; + } + } else { + if (!unmap_buffer_req.buff_info[i].bitstream_buffer_size || + !unmap_buffer_req.buff_info[i].meta_buff_size) { + IPAERR("invalid bitstream_buff_size %u\n", + unmap_buffer_req.buff_info[i].bitstream_buffer_size); + IPAERR("or meta_buff_size %u params\n", + unmap_buffer_req.buff_info[i].meta_buff_size); + return rc; + } + } + + IPADBG_LOW("bitstream_buffer_fd is %u\n", + unmap_buffer_req.buff_info[i].bitstream_buffer_fd); + IPADBG_LOW("meta_buff_fd is %u\n", + unmap_buffer_req.buff_info[i].meta_buff_fd); + IPADBG_LOW("bitstream_buffer_size is %u\n", + unmap_buffer_req.buff_info[i].bitstream_buffer_size); + IPADBG_LOW("meta_buff_size is %u\n", + unmap_buffer_req.buff_info[i].meta_buff_size); + } + + /* Call IPA driver/uC API's here */ + if (is_req_valid) + rc = ipa3_unmap_buff_from_device_addr(&unmap_buffer_req); + + IPADBG("Exit\n"); + return rc; +} + +int ipa_rtp_add_bitstream_buff_req_hdlr(struct sk_buff *skb_2, + struct genl_info *info) +{ + struct nlattr *na; + struct bitstream_buffers bs_buffer_req; + int i = 0, is_req_valid = 0, rc = -1; + + IPADBG("Entry\n"); + + if (!info) { + IPAERR("error genl info is null\n"); + return rc; + } + + na = info->attrs[IPA_RTP_GENL_ATTR_ADD_BITSTREAM_BUFF]; + if (na) { + if (nla_memcpy(&bs_buffer_req, na, + sizeof(bs_buffer_req)) > 0) { + is_req_valid = 1; + } else { + IPAERR("nla_memcpy failed %d\n", + IPA_RTP_GENL_ATTR_ADD_BITSTREAM_BUFF); + return rc; + } + } else { + IPAERR("no info->attrs %d\n", + IPA_RTP_GENL_ATTR_ADD_BITSTREAM_BUFF); + return rc; + } + + if (bs_buffer_req.buff_cnt <= 0 || bs_buffer_req.buff_cnt > MAX_BUFF || + bs_buffer_req.cookie != IPA_BS_BUFF_COOKIE) { + IPAERR("invalid buff_cnt %u or buff_cookie 0x%x params\n", + bs_buffer_req.buff_cnt, bs_buffer_req.cookie); + return rc; + } + + IPADBG_LOW("buff_cnt is %u\n", bs_buffer_req.buff_cnt); + IPADBG_LOW("cookie is 0x%x\n", bs_buffer_req.cookie); + + /* If IPA C2 component is providing two fd's for meta fd and bitstream buff fd then + * sizes need to be filled. If it is a single fd for both meta data and bitstream buff + * then meta_buff_fd and bitstream_buffer_fd will be the same. And they need to fill + * bitstream_buffer_size as actual size and meta_buff_size to zero. + */ + + for (i = 0; i < bs_buffer_req.buff_cnt; i++) { + if (bs_buffer_req.bs_info[i].stream_id >= MAX_STREAMS) { + IPAERR("invalid stream_id in buffer %u params\n", + bs_buffer_req.bs_info[i].stream_id); + return rc; + } + + if (bs_buffer_req.bs_info[i].meta_buff_fd == bs_buffer_req.bs_info[i].buff_fd) { + if (bs_buffer_req.bs_info[i].meta_buff_size || + !bs_buffer_req.bs_info[i].buff_size) { + IPAERR("or meta_buff_size %u or bs_buff_size %u params\n", + bs_buffer_req.bs_info[i].meta_buff_size, + bs_buffer_req.bs_info[i].buff_size); + return rc; + } + } else { + if (!bs_buffer_req.bs_info[i].meta_buff_size || + !bs_buffer_req.bs_info[i].buff_size) { + IPAERR("or meta_buff_size %u or bs_buff_size %u params\n", + bs_buffer_req.bs_info[i].meta_buff_size, + bs_buffer_req.bs_info[i].buff_size); + return rc; + } + } + + IPADBG_LOW("stream_id is %u\n", bs_buffer_req.bs_info[i].stream_id); + IPADBG_LOW("fence_id is %u\n", bs_buffer_req.bs_info[i].fence_id); + IPADBG_LOW("buff_offset is %u\n", bs_buffer_req.bs_info[i].buff_offset); + IPADBG_LOW("buff_fd is %u\n", bs_buffer_req.bs_info[i].buff_fd); + IPADBG_LOW("buff_size is %u\n", bs_buffer_req.bs_info[i].buff_size); + IPADBG_LOW("meta_buff_offset is %u\n", bs_buffer_req.bs_info[i].meta_buff_offset); + IPADBG_LOW("meta_buff_fd is %u\n", bs_buffer_req.bs_info[i].meta_buff_fd); + IPADBG_LOW("meta_buff_size is %u\n", bs_buffer_req.bs_info[i].meta_buff_size); + } + + /* Call IPA driver/uC API's here */ + if (is_req_valid) + rc = ipa3_send_bitstream_buff_info(&bs_buffer_req); + + IPADBG("Exit\n"); + return rc; +} + +int ipa_rtp_rmv_stream_id_req_hdlr(struct sk_buff *skb_2, + struct genl_info *info) +{ + struct nlattr *na; + struct remove_bitstream_buffers rmv_sid_req; + int is_req_valid = 0, rc = -1; + + IPADBG("Entry\n"); + + if (!info) { + IPAERR("error genl info is null\n"); + return rc; + } + + na = info->attrs[IPA_RTP_GENL_CMD_REMOVE_STREAM_ID]; + if (na) { + if (nla_memcpy(&rmv_sid_req, na, + sizeof(rmv_sid_req)) > 0) { + is_req_valid = 1; + } else { + IPAERR("nla_memcpy failed %d\n", + IPA_RTP_GENL_CMD_REMOVE_STREAM_ID); + return rc; + } + } else { + IPAERR("no info->attrs %d\n", + IPA_RTP_GENL_CMD_REMOVE_STREAM_ID); + return rc; + } + + if (rmv_sid_req.stream_id >= MAX_STREAMS) { + IPAERR("invalid stream_id %u params\n", rmv_sid_req.stream_id); + return rc; + } + + /* Call IPA driver/uC API's here */ + if (is_req_valid && (ipa3_uc_send_remove_stream_cmd(&rmv_sid_req) + || ipa3_delete_rtp_hdr_proc_rt_flt_rules(rmv_sid_req.stream_id))) { + IPAERR("failed in removing stream-id, deleting hdr proc and flt rules\n"); + return rc; + } + + ipa_rtp_active_streams[rmv_sid_req.stream_id] = 0; + ipa3_ctx->rtp_stream_id_cnt--; + + IPADBG("Exit\n"); + return rc; +} + +/* register ipa rtp driver family with generic netlink */ +int ipa_rtp_genl_init(void) +{ + int rc = 0; + + rc = genl_register_family(&ipa_rtp_genl_family); + if (rc != 0) { + IPAERR("ipa_rtp genl register family failed: %d", rc); + genl_unregister_family(&ipa_rtp_genl_family); + return rc; + } + + IPAERR("successfully registered ipa_rtp genl family: %s", + IPA_RTP_GENL_FAMILY_NAME); + return rc; +} + +/* Unregister the generic netlink family */ +int ipa_rtp_genl_deinit(void) +{ + int rc = 0; + + rc = genl_unregister_family(&ipa_rtp_genl_family); + if (rc != 0) + IPAERR("unregister ipa_rtp genl family failed: %d", rc); + return rc; +} + diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_rtp_genl.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_rtp_genl.h new file mode 100644 index 0000000000..e14cc710ab --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_rtp_genl.h @@ -0,0 +1,334 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _IPA_RTP_GENL_H_ +#define _IPA_RTP_GENL_H_ + +#include + +/* Generic Netlink Definitions */ +#define IPA_RTP_GENL_VERSION 1 +#define IPA_RTP_GENL_FAMILY_NAME "ipa_rtp" + +#define IPA_RTP_GENL_MAX_STR_LEN 255 +#define MAX_BUFF 10 +#define MAX_FDS 10 +#define IPA_BS_BUFF_COOKIE 0x45670198 + +/* XR IPAC2 <-> IPA Commands */ + +/** + * struct buffer_info - buffer information of map and unmap buffers. + * @bitstream_buffer_fd: bit stream buffer file descriptor. + * @meta_buff_fd: meta buffer file descriptor. + * @bitstream_buffer_size: bit stream buffer fd size. + * @meta_buff_size: meta buffer fd size. + */ + +struct buffer_info { + uint64_t bitstream_buffer_fd; + uint64_t meta_buff_fd; + uint64_t bitstream_buffer_size; + uint64_t meta_buff_size; +}; + +/** + * struct map_buffer - SMMU map buffers. + * @nfd: number of fd's. + * @stream_id: reciving stream ID. + * @buff_info: buffer information to map buffers. + */ + +struct map_buffer { + uint32_t nfd; + uint32_t stream_id; + struct buffer_info buff_info[MAX_BUFF]; +}; + +/** + * struct unmap_buffer - SMMU unmap buffers. + * @nfd: number of fd's. + * @stream_id: reciving stream ID. + * @buff_info: buffer information to unmap buffers. + */ + +struct unmap_buffer { + uint32_t nfd; + uint32_t stream_id; + struct buffer_info buff_info[MAX_BUFF]; +}; + +/** + * struct remove_bitstream_buffers - remove bitstream buffers. + * @stream_id: stream ID to stop using bitstream buffres of the specific stream. + */ + +struct remove_bitstream_buffers { + uint32_t stream_id; +}; + +struct bitstream_buffer_info_to_uc { + uint8_t stream_id; + uint16_t fence_id; + uint8_t reserved; + u64 buff_addr; + u32 buff_fd; + u32 buff_size; + u64 meta_buff_addr; + u32 meta_buff_fd; + u32 meta_buff_size; +} __packed; + +struct bitstream_buffers_to_uc { + uint16_t buff_cnt; + uint16_t cookie; + struct bitstream_buffer_info_to_uc bs_info[MAX_BUFF]; +} __packed; + +/** + * struct traffic_selector_info - traffic selector information. + * @no_of_openframe: no. of openframes in a stream. + * @max_pkt_frame: maximum packets per frame. + * @stream_type: type of stream. + * @reorder_timeout: RTP packets reordering timeout. + * @num_slices_per_frame: no. of slices per frame. + */ + +struct traffic_selector_info { + uint32_t no_of_openframe; + uint32_t max_pkt_frame; + uint32_t stream_type; + uint64_t reorder_timeout; + uint32_t num_slices_per_frame; +}; + +/** + * struct ipv6_tuple_info - ipv6 tuple information. + * @src_port_number: source port number. + * @dst_port_number: dst port number. + * @src_ip: source IP. + * @dst_ip: dst IP. + * @protocol: protocol type. + */ + +struct ipv6_tuple_info { + uint32_t src_port_number; + uint32_t dst_port_number; + uint8_t src_ip[16]; + uint8_t dst_ip[16]; + uint32_t protocol; +}; + +/** + * struct ipv4_tuple_info - ipv4 tuple information. + * @src_port_number: source port number. + * @dst_port_number: dst port number. + * @src_ip: source IP. + * @dst_ip: dst IP. + * @protocol: protocol type. + */ + +struct ipv4_tuple_info { + uint32_t src_port_number; + uint32_t dst_port_number; + uint32_t src_ip; + uint32_t dst_ip; + uint32_t protocol; +}; + +/** + * struct ip_tuple_info - ip tuple information. + * @ipv4_tuple_info: ipv4 tuple information. + * @ipv6_tuple_info: ipv6 tuple information. + */ + +union ip_tuple_info { + struct ipv4_tuple_info ipv4; + struct ipv6_tuple_info ipv6; +}; + +/** + * struct traffic_tuple_info - traffic tuple information. + * @ip_type: ip type (ipv4 or ipv6). + * @ip_tuple_info: ip tuple information. + */ + +struct traffic_tuple_info { + struct traffic_selector_info ts_info; + uint8_t ip_type; + union ip_tuple_info ip_info; +}; + +/** + * struct assign_stream_id - assign stream id for a stream. + * @stream_id: assigned stream id. + */ + +struct assign_stream_id { + uint32_t stream_id; +}; + +/** + * struct bitstream_buffer_info_to_ipa - bitstream buffer info to ipa. + * @stream_id: stream Identifier. + * @fence_id: fence Identifier. + * @buff_offset: bit stream buffer offset. + * @buff_fd: bit stream file descriptor. + * @buff_size: bit stream suffer size. + * @meta_buff_offset: bit stream metadata buffer offset. + * @meta_buff_fd: bit stream metadata buffer file descriptor. + * @meta_buff_size: bit stream metadata buffer size. + */ + +struct bitstream_buffer_info_to_ipa { + uint32_t stream_id; + uint32_t fence_id; + uint32_t buff_offset; + uint32_t buff_fd; + uint32_t buff_size; + uint32_t meta_buff_offset; + uint32_t meta_buff_fd; + uint32_t meta_buff_size; +}; + +/** + * struct bitstream_buffers - bitstream buffers. + * @buff_cnt: number of buffers per stream. + * @cookie: pre-defined macro per stream. + * @bitstream_buffer_info_to_ipa: bitstream buffer info to ipa. + */ + +struct bitstream_buffers { + uint32_t buff_cnt; + uint32_t cookie; + struct bitstream_buffer_info_to_ipa bs_info[MAX_BUFF]; +}; + +/** + * struct bitstream_buffer_info_to_uspace - bitstream buffer info to IPA C2. + * @stream_id: stream Identifier. + * @fence_id: fence Identifier. + * @buff_offset: bit stream buffer offset. + * @buff_fd: bit stream file descriptor. + * @buff_size: bit stream suffer size. + * @meta_buff_offset: bit stream metadata buffer offset. + * @meta_buff_fd: bit stream metadata buffer file descriptor. + * @meta_buff_size: bit stream metadata buffer size. + * @reason_failure: reason for failure. + * @qtime_first_pkt_processed: qtime of first packet processed. + * @qtime_last_pkt_processed: qtime of last packet processed. + */ + +struct bitstream_buffer_info_to_uspace { + uint32_t frame_id; + uint32_t stream_id; + uint32_t fence_id; + uint64_t buff_offset; + uint32_t buff_fd; + uint32_t buff_size; + uint64_t meta_buff_offset; + uint32_t meta_buff_fd; + uint32_t meta_buff_size; + uint32_t reason_failure; + uint64_t qtime_first_pkt_processed; + uint64_t qtime_last_pkt_processed; +}; + +/** + * struct statistics_info - statistics information. + * @avg_reoder_latency: average reodering latency. + * @num_frame_to_sw: no. frames to sw-path. + * @last_frame_to_deco: last frame to decoder. + */ + +struct statistics_info { + uint32_t avg_reoder_latency; + uint32_t num_frame_to_sw; + uint32_t last_frame_to_deco; +}; + +enum { + IPA_RTP_GENL_CMD_UNSPEC, + IPA_RTP_GENL_CMD_STR, + IPA_RTP_GENL_CMD_INT, + IPA_RTP_GENL_CMD_TUPLE_INFO, + IPA_RTP_GENL_CMD_ASSIGN_STREAM_ID, + IPA_RTP_GENL_CMD_ADD_BITSTREAM_BUFF, + IPA_RTP_GENL_CMD_SMMU_MAP_BUFF, + IPA_RTP_GENL_CMD_SMMU_UNMAP_BUFF, + IPA_RTP_GENL_CMD_REMOVE_STREAM_ID, + IPA_RTP_GENL_CMD_MAX, +}; + +enum { + IPA_RTP_GENL_ATTR_UNSPEC, + IPA_RTP_GENL_ATTR_STR, + IPA_RTP_GENL_ATTR_INT, + IPA_RTP_GENL_ATTR_TUPLE_INFO, + IPA_RTP_GENL_ATTR_ASSIGN_STREAM_ID, + IPA_RTP_GENL_ATTR_ADD_BITSTREAM_BUFF, + IPA_RTP_GENL_ATTR_SMMU_MAP_BUFF, + IPA_RTP_GENL_ATTR_SMMU_UNMAP_BUFF, + IPA_RTP_GENL_ATTR_REMOVE_STREAM_ID, + IPA_RTP_GENL_ATTR_MAX, +}; + + +/* Function Prototypes */ +int ipa3_install_rtp_hdr_proc_rt_flt_rules(struct traffic_tuple_info *tuple_info, u32 stream_id); +int ipa3_delete_rtp_hdr_proc_rt_flt_rules(u32 stream_id); + +/* + * This handler will be invoked when IPA C2 sends TUPLE + * info cmd to IPA Driver via generic netlink interface. + */ +int ipa_rtp_tuple_info_req_hdlr(struct sk_buff *skb_2, + struct genl_info *info); + +/* + * This function will be invoked when IPA driver allocates stream + * id and sends it to IPA C2 via generic netlink interface. + */ +int ipa_rtp_send_tuple_info_resp(struct genl_info *info, + struct assign_stream_id *sid); + +/* + * This handler will be invoked when IPA C2 sends SMMU MAP + * info cmd to IPA Driver via generic netlink interface. + */ +int ipa_rtp_smmu_map_buff_req_hdlr(struct sk_buff *skb_2, + struct genl_info *info); + +/* + * This handler will be invoked when IPA C2 sends SMMU UNMAP + * info cmd to IPA Driver via generic netlink interface. + */ +int ipa_rtp_smmu_unmap_buff_req_hdlr(struct sk_buff *skb_2, + struct genl_info *info); + +/* + * This handler will be invoked when IPA C2 sends BITSTREAM BUFF + * info cmd to IPA Driver via generic netlink interface. + */ +int ipa_rtp_add_bitstream_buff_req_hdlr(struct sk_buff *skb_2, + struct genl_info *info); + +/* + * This handler will be invoked when IPA C2 sends REMOVE STREAM + * info cmd to IPA Driver via generic netlink interface. + */ +int ipa_rtp_rmv_stream_id_req_hdlr(struct sk_buff *skb_2, + struct genl_info *info); + +/* + * This is a generic netlink family init from IPA driver + * and when IPA C2 userspace comes, it will connect to this + * family via pre-defined name. + */ +int ipa_rtp_genl_init(void); + +int ipa_rtp_genl_deinit(void); + +#endif /*_IPA_RTP_GENL_H_*/ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_stats.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_stats.c new file mode 100644 index 0000000000..6c281f4d27 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_stats.c @@ -0,0 +1,2251 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include "ipa_stats.h" +#include +#include "ipa_i.h" +#include "ipahal.h" +#include "ipa_odl.h" +#include "ipa_common_i.h" +#include +#include "gsi.h" + +#define DRIVER_NAME "ipa_lnx_stats_ioctl" +#define DEV_NAME_IPA_LNX_STATS "ipa-lnx-stats" + +#define IPA_STATS_DBG(fmt, args...) \ + do { \ + pr_debug(DEV_NAME_IPA_LNX_STATS " %s:%d " fmt, __func__,\ + __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf(), \ + DEV_NAME_IPA_LNX_STATS " %s:%d " fmt, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf_low(), \ + DEV_NAME_IPA_LNX_STATS " %s:%d " fmt, ## args); \ + } while (0) + +#define IPA_STATS_ERR(fmt, args...) \ + do { \ + pr_err(DEV_NAME_IPA_LNX_STATS " %s:%d " fmt, __func__,\ + __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf(), \ + DEV_NAME_IPA_LNX_STATS " %s:%d " fmt, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf_low(), \ + DEV_NAME_IPA_LNX_STATS " %s:%d " fmt, ## args); \ + } while (0) + +#define IPA_PERIPHERAL_STATS_MDM_NUM_ENTRIES 20 +#define IPA_PERIPHERAL_STATS_MSM_NUM_ENTRIES 12 + +static unsigned int dev_num = 1; +static struct cdev ipa_lnx_stats_ioctl_cdev; +static struct class *class; +static dev_t device; + +struct ipa_lnx_stats_tlpd_ctx ipa_lnx_agent_ctx; +static DEFINE_MUTEX(ipa_lnx_ctx_mutex); + +struct wlan_intf_mode_cnt { + u8 ap_cnt; + u8 sta_cnt; +}; + +enum wlan_intf_mode { + AP, + AP_AP, + AP_STA, + AP_AP_STA, + AP_AP_AP, + AP_AP_AP_STA, + AP_AP_AP_AP_, + WLAN_INTF_MODE_MAX +}; + +union ipa_gsi_ring_prev_poll_info { + struct { + uint32_t num_tx_ring_100_perc_with_cred; + uint32_t num_tx_ring_0_perc_with_cred; + uint32_t num_tx_ring_above_75_perc_cred; + uint32_t num_tx_ring_above_25_perc_cred; + uint32_t num_tx_ring_stats_polled; + } tx_cred_info; + struct { + uint32_t num_rx_ring_100_perc_with_pack; + uint32_t num_rx_ring_0_perc_with_pack; + uint32_t num_rx_ring_above_75_perc_pack; + uint32_t num_rx_ring_above_25_perc_pack; + uint32_t num_rx_ring_stats_polled; + } rx_pack_info; +}; + +union ipa_gsi_ring_prev_poll_info poll_pack_and_cred_info[IPA_CLIENT_MAX]; + +static enum wlan_intf_mode ipa_get_wlan_intf_mode(void) +{ + struct wlan_intf_mode_cnt mode_cnt; + mode_cnt.ap_cnt = ipa3_ctx->stats.msg_w[WLAN_AP_CONNECT] - + ipa3_ctx->stats.msg_w[WLAN_AP_DISCONNECT]; + mode_cnt.sta_cnt = ipa3_ctx->stats.msg_w[WLAN_STA_CONNECT] - + ipa3_ctx->stats.msg_w[WLAN_STA_DISCONNECT]; + if ((mode_cnt.ap_cnt < 0) || (mode_cnt.sta_cnt < 0)) + return WLAN_INTF_MODE_MAX; + + switch (mode_cnt.ap_cnt) { + case 1: + if (mode_cnt.sta_cnt == 1) + return AP_STA; + return AP; + case 2: + if (mode_cnt.sta_cnt == 1) + return AP_AP_STA; + return AP_AP; + case 3: + if (mode_cnt.sta_cnt == 1) + return AP_AP_AP_STA; + return AP_AP_AP; + case 4: + return AP_AP_AP_AP_; + default: + if (mode_cnt.ap_cnt > 4) + return AP_AP_AP_AP_; + return WLAN_INTF_MODE_MAX; + } +} + +static int ipa_stats_ioctl_open(struct inode *inode, struct file *filp) +{ + return 0; +} + +static int ipa_get_generic_stats(unsigned long arg) +{ + int res; + int i, j; + struct ipa_lnx_generic_stats *generic_stats; + struct ipa_drop_stats_all *out; + int alloc_size; + int reg_idx; + struct ipa_uc_holb_client_info *holb_client; + struct holb_discard_stats *holb_disc_stats_ptr; + struct holb_monitor_stats *holb_mon_stats_ptr; + + if (!(ipa_lnx_agent_ctx.log_type_mask & TLPD_IPA_LOG_TYPE_GENERIC_STATS)) { + IPA_STATS_ERR("Log type GENERIC mask not set\n"); + return -EFAULT; + } + + alloc_size = sizeof(struct ipa_lnx_generic_stats) + + (sizeof(struct holb_discard_stats) * + ipa_lnx_agent_ctx.alloc_info.num_holb_drop_stats_clients) + + (sizeof(struct holb_monitor_stats) * + ipa_lnx_agent_ctx.alloc_info.num_holb_mon_stats_clients); + + generic_stats = (struct ipa_lnx_generic_stats *) memdup_user(( + const void __user *)arg, alloc_size); + if (IS_ERR(generic_stats)) { + IPA_STATS_ERR("copy from user failed"); + return -ENOMEM; + } + + generic_stats->tx_dma_pkts = ipa3_ctx->stats.tx_sw_pkts; + generic_stats->tx_hw_pkts = ipa3_ctx->stats.tx_hw_pkts; + generic_stats->tx_non_linear = ipa3_ctx->stats.tx_non_linear; + generic_stats->tx_pkts_compl = ipa3_ctx->stats.tx_pkts_compl; + generic_stats->stats_compl = ipa3_ctx->stats.stat_compl; + generic_stats->active_eps = + atomic_read(&ipa3_ctx->ipa3_active_clients.cnt); + generic_stats->wan_rx_empty = ipa3_ctx->stats.wan_rx_empty; + generic_stats->wan_repl_rx_empty = ipa3_ctx->stats.wan_repl_rx_empty; + generic_stats->lan_rx_empty = ipa3_ctx->stats.lan_rx_empty; + generic_stats->lan_repl_rx_empty = ipa3_ctx->stats.lan_repl_rx_empty; + /* Page recycle stats */ + generic_stats->pg_rec_stats.coal_total_repl_buff = + ipa3_ctx->stats.page_recycle_stats[0].total_replenished; + generic_stats->pg_rec_stats.coal_temp_repl_buff = + ipa3_ctx->stats.page_recycle_stats[0].tmp_alloc; + generic_stats->pg_rec_stats.def_total_repl_buff = + ipa3_ctx->stats.page_recycle_stats[1].total_replenished; + generic_stats->pg_rec_stats.def_temp_repl_buff = + ipa3_ctx->stats.page_recycle_stats[1].tmp_alloc; + /* Exception stats */ + generic_stats->excep_stats.excptn_type_none = + ipa3_ctx->stats.rx_excp_pkts[IPAHAL_PKT_STATUS_EXCEPTION_NONE]; + generic_stats->excep_stats.excptn_type_deaggr = + ipa3_ctx->stats.rx_excp_pkts[IPAHAL_PKT_STATUS_EXCEPTION_DEAGGR]; + generic_stats->excep_stats.excptn_type_iptype = + ipa3_ctx->stats.rx_excp_pkts[IPAHAL_PKT_STATUS_EXCEPTION_IPTYPE]; + generic_stats->excep_stats.excptn_type_pkt_len = + ipa3_ctx->stats.rx_excp_pkts[ + IPAHAL_PKT_STATUS_EXCEPTION_PACKET_LENGTH]; + generic_stats->excep_stats.excptn_type_pkt_thrshld = + ipa3_ctx->stats.rx_excp_pkts[ + IPAHAL_PKT_STATUS_EXCEPTION_PACKET_THRESHOLD]; + generic_stats->excep_stats.excptn_type_frag_rule_miss = + ipa3_ctx->stats.rx_excp_pkts[ + IPAHAL_PKT_STATUS_EXCEPTION_FRAG_RULE_MISS]; + generic_stats->excep_stats.excptn_type_sw_flt = + ipa3_ctx->stats.rx_excp_pkts[IPAHAL_PKT_STATUS_EXCEPTION_SW_FILT]; + generic_stats->excep_stats.excptn_type_nat = + ipa3_ctx->stats.rx_excp_pkts[IPAHAL_PKT_STATUS_EXCEPTION_NAT]; + generic_stats->excep_stats.excptn_type_ipv6_ct = + ipa3_ctx->stats.rx_excp_pkts[IPAHAL_PKT_STATUS_EXCEPTION_IPV6CT]; + generic_stats->excep_stats.excptn_type_csum = + ipa3_ctx->stats.rx_excp_pkts[IPAHAL_PKT_STATUS_EXCEPTION_CSUM]; + /* ODL EP stats */ + if (ipa3_odl_ctx) { + generic_stats->odl_stats.rx_pkt = ipa3_odl_ctx->stats.odl_rx_pkt; + generic_stats->odl_stats.processed_pkt = + ipa3_odl_ctx->stats.odl_tx_diag_pkt; + generic_stats->odl_stats.dropped_pkt = + ipa3_odl_ctx->stats.odl_drop_pkt; + generic_stats->odl_stats.num_queue_pkt = + atomic_read(&ipa3_odl_ctx->stats.numer_in_queue); + } + /* HOLB discard stats */ + if (!(ipa3_ctx->hw_stats && ipa3_ctx->hw_stats->enabled)) { + generic_stats->holb_stats.num_holb_disc_pipes = 0; + generic_stats->holb_stats.num_holb_mon_clients = 0; + } + + generic_stats->holb_stats.num_holb_disc_pipes = + ipa_lnx_agent_ctx.alloc_info.num_holb_drop_stats_clients; + generic_stats->holb_stats.num_holb_mon_clients = + ipa_lnx_agent_ctx.alloc_info.num_holb_mon_stats_clients; + + out = kzalloc(sizeof(*out), GFP_KERNEL); + if (!out) { + kfree(generic_stats); + return -ENOMEM; + } + + res = ipa_get_drop_stats(out); + if (res) { + kfree(out); + kfree(generic_stats); + return res; + } + + if(ipa_lnx_agent_ctx.alloc_info.num_holb_drop_stats_clients != 0 ) { + /* HOLB Discard stats */ + holb_disc_stats_ptr = &generic_stats->holb_stats.holb_disc_stats[0]; + for (i = 0; i < IPA_CLIENT_MAX; i++) { + int ep_idx = ipa_get_ep_mapping(i); + + if ((ep_idx == -1) || (!IPA_CLIENT_IS_CONS(i)) || + (IPA_CLIENT_IS_TEST(i))) + continue; + + reg_idx = ipahal_get_ep_reg_idx(ep_idx); + if (!(ipa3_ctx->hw_stats && + (ipa3_ctx->hw_stats->drop.init.enabled_bitmask[reg_idx] & + ipahal_get_ep_bit(ep_idx)))) + continue; + + holb_disc_stats_ptr->client_type = i; + holb_disc_stats_ptr->num_drp_cnt = out->client[i].drop_packet_cnt; + holb_disc_stats_ptr->num_drp_bytes = out->client[i].drop_byte_cnt; + holb_disc_stats_ptr = (struct holb_discard_stats *)(( + uint64_t)holb_disc_stats_ptr + sizeof(struct holb_discard_stats)); + } + } + + if(ipa_lnx_agent_ctx.alloc_info.num_holb_mon_stats_clients != 0 ) { + /* HOLB Monitor stats */ + holb_mon_stats_ptr = (struct holb_monitor_stats *)( + (uint64_t)&generic_stats->holb_stats.holb_disc_stats[0] + + (ipa_lnx_agent_ctx.alloc_info.num_holb_drop_stats_clients * + sizeof(struct holb_discard_stats))); + for (i = 0; i < generic_stats->holb_stats.num_holb_mon_clients; i++) { + holb_client = &(ipa3_ctx->uc_ctx.holb_monitor.client[i]); + /* Get the client type from gsi_hdl */ + for (j = 0; j < IPA5_MAX_NUM_PIPES; j++) { + if (ipa3_ctx->ep[j].gsi_chan_hdl == holb_client->gsi_chan_hdl) { + holb_mon_stats_ptr->client_type = ipa3_ctx->ep[j].client; + break; + } + } + holb_mon_stats_ptr->curr_index = holb_client->current_idx; + holb_mon_stats_ptr->num_en_cnt = holb_client->enable_cnt; + holb_mon_stats_ptr->num_dis_cnt = holb_client->disable_cnt; + holb_mon_stats_ptr = (struct holb_monitor_stats *)(( + uint64_t)holb_mon_stats_ptr + sizeof(struct holb_monitor_stats)); + } + } + + if(copy_to_user((void __user *)arg, + (u8 *)generic_stats, + alloc_size)) { + kfree(generic_stats); + kfree(out); + IPA_STATS_ERR("copy to user failed"); + return -EFAULT; + } + + kfree(out); + kfree(generic_stats); + return 0; +} + +static int ipa_get_clock_stats(unsigned long arg) +{ + struct ipa_lnx_clock_stats *clock_stats; + int i; + int alloc_size; + struct pm_client_stats *pm_stats_ptr; + + if (!(ipa_lnx_agent_ctx.log_type_mask & TLPD_IPA_LOG_TYPE_CLOCK_STATS)) { + IPA_STATS_ERR("Log type CLOCK mask not set\n"); + return -EFAULT; + } + + alloc_size = sizeof(struct ipa_lnx_clock_stats) + + (sizeof(struct pm_client_stats) * + ipa_lnx_agent_ctx.alloc_info.num_pm_clients); + + clock_stats = (struct ipa_lnx_clock_stats *) memdup_user(( + const void __user *)arg, alloc_size); + if (IS_ERR(clock_stats)) { + IPA_STATS_ERR("copy from user failed\n"); + return -ENOMEM; + } + + if(ipa_pm_get_scaling_bw_levels(clock_stats)) + IPA_STATS_ERR("Couldn't get scaling bw levels\n"); + clock_stats->aggr_bw = + ipa_pm_get_aggregated_throughput(); + clock_stats->curr_clk_vote = ipa_pm_get_current_clk_vote(); + clock_stats->active_clients = 0; + + pm_stats_ptr = &clock_stats->pm_clnt_stats[0]; + for (i = 1; i < ipa_lnx_agent_ctx.alloc_info.num_pm_clients; i++) { + if (ipa_get_pm_client_stats_filled(pm_stats_ptr, i)) { + clock_stats->active_clients++; + pm_stats_ptr = (struct pm_client_stats *)((uint64_t)pm_stats_ptr + + sizeof(struct pm_client_stats)); + } + } + + if(copy_to_user((void __user *)arg, + (u8 *)clock_stats, + alloc_size)) { + kfree(clock_stats); + IPA_STATS_ERR("copy to user failed"); + return -EFAULT; + } + + kfree(clock_stats); + return 0; +} + +/** + * ipa_get_gsi_pipe_info - API to fill gsi pipe info + */ +static void ipa_get_gsi_pipe_info( + struct ipa_lnx_pipe_info *pipe_info_ptr_local, struct ipa3_ep_context *ep) +{ + const struct ipa_gsi_ep_config *gsi_ep_info; + + pipe_info_ptr_local->client_type = ep->client; + if (ep->sys) { + pipe_info_ptr_local->buff_size = ep->sys->buff_size; + pipe_info_ptr_local->is_common_evt_ring = + ep->sys->use_comm_evt_ring; + } + pipe_info_ptr_local->direction = IPA_CLIENT_IS_CONS(ep->client); + pipe_info_ptr_local->num_free_buff = 0; + pipe_info_ptr_local->gsi_chan_num = ep->gsi_chan_hdl; + pipe_info_ptr_local->gsi_evt_num = ep->gsi_evt_ring_hdl; + + pipe_info_ptr_local->gsi_prot_type = + gsi_get_chan_prot_type(ep->gsi_chan_hdl); + pipe_info_ptr_local->gsi_chan_state = + gsi_get_chan_state(ep->gsi_chan_hdl); + pipe_info_ptr_local->gsi_chan_stop_stm = + gsi_get_chan_stop_stm(ep->gsi_chan_hdl, gsi_get_peripheral_ee()); + pipe_info_ptr_local->gsi_poll_mode = + gsi_get_chan_poll_mode(ep->gsi_chan_hdl); + pipe_info_ptr_local->gsi_chan_ring_len = + gsi_get_ring_len(ep->gsi_chan_hdl); + pipe_info_ptr_local->gsi_db_in_bytes = + gsi_get_chan_props_db_in_bytes(ep->gsi_chan_hdl); + pipe_info_ptr_local->gsi_chan_ring_bp = + gsi_read_chan_ring_bp(ep->gsi_chan_hdl); + pipe_info_ptr_local->gsi_chan_ring_rp = + gsi_read_chan_ring_rp(ep->gsi_chan_hdl, gsi_get_peripheral_ee()); + pipe_info_ptr_local->gsi_chan_ring_wp = + gsi_read_chan_ring_wp(ep->gsi_chan_hdl, gsi_get_peripheral_ee()); + + gsi_ep_info = ipa_get_gsi_ep_info(ep->client); + pipe_info_ptr_local->gsi_ipa_if_tlv = + gsi_ep_info ? gsi_ep_info->ipa_if_tlv : 0; + pipe_info_ptr_local->gsi_ipa_if_aos = + gsi_ep_info ? gsi_ep_info->ipa_if_aos : 0; + + pipe_info_ptr_local->gsi_desc_size = + gsi_get_evt_ring_re_size(ep->gsi_evt_ring_hdl); + pipe_info_ptr_local->gsi_evt_ring_len = + gsi_get_evt_ring_len(ep->gsi_evt_ring_hdl); + pipe_info_ptr_local->gsi_evt_ring_bp = + gsi_read_event_ring_bp(ep->gsi_evt_ring_hdl); + pipe_info_ptr_local->gsi_evt_ring_rp = + gsi_get_evt_ring_rp(ep->gsi_evt_ring_hdl); + pipe_info_ptr_local->gsi_evt_ring_wp = + gsi_read_event_ring_wp(ep->gsi_evt_ring_hdl, gsi_get_peripheral_ee()); +} + +/** + * ipa_lnx_calculate_gsi_ring_summay - API to calculate gsi ring summary + * GSI tx_summary and rx_summary are calculated based on the difference between + * the previous poll and the current poll. Both summaries are on a scale of 100 + * and will be rated based upon number of credits left(tx) or number or packets + * filled(rx). 100 value being efficient and 0 being non efficient/stall/IPA idle + */ +static void ipa_lnx_calculate_gsi_ring_summay( + struct ipa_lnx_gsi_tx_debug_stats *tx_instance_ptr_local, + struct ipa_lnx_gsi_rx_debug_stats *rx_instance_ptr_local, + int client_type) +{ + uint32_t diff_100_perc_cred; + uint32_t diff_0_perc_cred; + uint32_t diff_75_perc_cred; + uint32_t diff_50_perc_cred; + uint32_t diff_25_perc_cred; + uint32_t diff_tx_polled; + uint32_t diff_100_perc_pack; + uint32_t diff_0_perc_pack; + uint32_t diff_75_perc_pack; + uint32_t diff_50_perc_pack; + uint32_t diff_25_perc_pack; + uint32_t diff_rx_polled; + + if (IPA_CLIENT_IS_CONS(client_type) && tx_instance_ptr_local) { + if (tx_instance_ptr_local->num_tx_ring_100_perc_with_cred >= + poll_pack_and_cred_info[ + client_type].tx_cred_info.num_tx_ring_100_perc_with_cred) + diff_100_perc_cred = + tx_instance_ptr_local->num_tx_ring_100_perc_with_cred - + poll_pack_and_cred_info[ + client_type].tx_cred_info.num_tx_ring_100_perc_with_cred; + else diff_100_perc_cred = (0xFFFFFFFF - poll_pack_and_cred_info[ + client_type].tx_cred_info.num_tx_ring_100_perc_with_cred) + + tx_instance_ptr_local->num_tx_ring_100_perc_with_cred; + if (tx_instance_ptr_local->num_tx_ring_above_75_perc_cred >= + poll_pack_and_cred_info[ + client_type].tx_cred_info.num_tx_ring_above_75_perc_cred) + diff_75_perc_cred = + tx_instance_ptr_local->num_tx_ring_above_75_perc_cred - + poll_pack_and_cred_info[ + client_type].tx_cred_info.num_tx_ring_above_75_perc_cred; + else diff_75_perc_cred = (0xFFFFFFFF - poll_pack_and_cred_info[ + client_type].tx_cred_info.num_tx_ring_above_75_perc_cred) + + tx_instance_ptr_local->num_tx_ring_above_75_perc_cred; + if (tx_instance_ptr_local->num_tx_ring_above_25_perc_cred >= + poll_pack_and_cred_info[ + client_type].tx_cred_info.num_tx_ring_above_25_perc_cred) + diff_25_perc_cred = + tx_instance_ptr_local->num_tx_ring_above_25_perc_cred - + poll_pack_and_cred_info[ + client_type].tx_cred_info.num_tx_ring_above_25_perc_cred; + else diff_25_perc_cred = (0xFFFFFFFF - poll_pack_and_cred_info[ + client_type].tx_cred_info.num_tx_ring_above_25_perc_cred) + + tx_instance_ptr_local->num_tx_ring_above_25_perc_cred; + if (tx_instance_ptr_local->num_tx_ring_0_perc_with_cred >= + poll_pack_and_cred_info[ + client_type].tx_cred_info.num_tx_ring_0_perc_with_cred) + diff_0_perc_cred = + tx_instance_ptr_local->num_tx_ring_0_perc_with_cred - + poll_pack_and_cred_info[ + client_type].tx_cred_info.num_tx_ring_0_perc_with_cred; + else diff_0_perc_cred = (0xFFFFFFFF - poll_pack_and_cred_info[ + client_type].tx_cred_info.num_tx_ring_0_perc_with_cred) + + tx_instance_ptr_local->num_tx_ring_0_perc_with_cred; + if (tx_instance_ptr_local->num_tx_ring_stats_polled >= + poll_pack_and_cred_info[ + client_type].tx_cred_info.num_tx_ring_stats_polled) + diff_tx_polled = + tx_instance_ptr_local->num_tx_ring_stats_polled - + poll_pack_and_cred_info[ + client_type].tx_cred_info.num_tx_ring_stats_polled; + else diff_tx_polled = (0xFFFFFFFF - poll_pack_and_cred_info[ + client_type].tx_cred_info.num_tx_ring_stats_polled) + + tx_instance_ptr_local->num_tx_ring_stats_polled; + + poll_pack_and_cred_info[ + client_type].tx_cred_info.num_tx_ring_100_perc_with_cred = + tx_instance_ptr_local->num_tx_ring_100_perc_with_cred; + poll_pack_and_cred_info[ + client_type].tx_cred_info.num_tx_ring_0_perc_with_cred = + tx_instance_ptr_local->num_tx_ring_0_perc_with_cred; + poll_pack_and_cred_info[ + client_type].tx_cred_info.num_tx_ring_above_75_perc_cred = + tx_instance_ptr_local->num_tx_ring_above_75_perc_cred; + poll_pack_and_cred_info[ + client_type].tx_cred_info.num_tx_ring_above_25_perc_cred = + tx_instance_ptr_local->num_tx_ring_above_25_perc_cred; + poll_pack_and_cred_info[ + client_type].tx_cred_info.num_tx_ring_stats_polled = + tx_instance_ptr_local->num_tx_ring_stats_polled; + + diff_50_perc_cred = diff_tx_polled - (diff_100_perc_cred + + diff_75_perc_cred + diff_25_perc_cred + diff_0_perc_cred); + /** + * TX ring scale(summary) - Varies between 0 to 100 + * If the value tends towards 0, we can assume following things + * 1. DL throughput increasing or + * 2. Peripheral not pulling data fast enough. + * + * If the value tends towards 100, we can assume following things + * 1. Client processing data speed increasing or + * 2. Equal to 100 when no DL data transfer + */ + tx_instance_ptr_local->tx_summary = ((diff_100_perc_cred * 100) + + (diff_75_perc_cred * 75) + + (diff_50_perc_cred * 50) + + (diff_25_perc_cred * 25) + + (diff_0_perc_cred * 0))/diff_tx_polled; + } else if(!IPA_CLIENT_IS_CONS(client_type) && rx_instance_ptr_local) { + if (rx_instance_ptr_local->num_rx_ring_100_perc_with_pack >= + poll_pack_and_cred_info[ + client_type].rx_pack_info.num_rx_ring_100_perc_with_pack) + diff_100_perc_pack = + rx_instance_ptr_local->num_rx_ring_100_perc_with_pack - + poll_pack_and_cred_info[ + client_type].rx_pack_info.num_rx_ring_100_perc_with_pack; + else diff_100_perc_pack = (0xFFFFFFFF - poll_pack_and_cred_info[ + client_type].rx_pack_info.num_rx_ring_100_perc_with_pack) + + rx_instance_ptr_local->num_rx_ring_100_perc_with_pack; + if (rx_instance_ptr_local->num_rx_ring_above_75_perc_pack >= + poll_pack_and_cred_info[ + client_type].rx_pack_info.num_rx_ring_above_75_perc_pack) + diff_75_perc_pack = + rx_instance_ptr_local->num_rx_ring_above_75_perc_pack - + poll_pack_and_cred_info[ + client_type].rx_pack_info.num_rx_ring_above_75_perc_pack; + else diff_75_perc_pack = (0xFFFFFFFF - poll_pack_and_cred_info[ + client_type].rx_pack_info.num_rx_ring_above_75_perc_pack) + + rx_instance_ptr_local->num_rx_ring_above_75_perc_pack; + if (rx_instance_ptr_local->num_rx_ring_above_25_perc_pack >= + poll_pack_and_cred_info[ + client_type].rx_pack_info.num_rx_ring_above_25_perc_pack) + diff_25_perc_pack = + rx_instance_ptr_local->num_rx_ring_above_25_perc_pack - + poll_pack_and_cred_info[ + client_type].rx_pack_info.num_rx_ring_above_25_perc_pack; + else diff_25_perc_pack = (0xFFFFFFFF - poll_pack_and_cred_info[ + client_type].rx_pack_info.num_rx_ring_above_25_perc_pack) + + rx_instance_ptr_local->num_rx_ring_above_25_perc_pack; + if (rx_instance_ptr_local->num_rx_ring_0_perc_with_pack >= + poll_pack_and_cred_info[ + client_type].rx_pack_info.num_rx_ring_0_perc_with_pack) + diff_0_perc_pack = + rx_instance_ptr_local->num_rx_ring_0_perc_with_pack - + poll_pack_and_cred_info[ + client_type].rx_pack_info.num_rx_ring_0_perc_with_pack; + else diff_0_perc_pack = (0xFFFFFFFF - poll_pack_and_cred_info[ + client_type].rx_pack_info.num_rx_ring_0_perc_with_pack) + + rx_instance_ptr_local->num_rx_ring_0_perc_with_pack; + if (rx_instance_ptr_local->num_rx_ring_stats_polled >= + poll_pack_and_cred_info[ + client_type].rx_pack_info.num_rx_ring_stats_polled) + diff_rx_polled = + rx_instance_ptr_local->num_rx_ring_stats_polled - + poll_pack_and_cred_info[ + client_type].rx_pack_info.num_rx_ring_stats_polled; + else diff_rx_polled = (0xFFFFFFFF - poll_pack_and_cred_info[ + client_type].rx_pack_info.num_rx_ring_stats_polled) + + rx_instance_ptr_local->num_rx_ring_stats_polled; + + poll_pack_and_cred_info[ + client_type].rx_pack_info.num_rx_ring_100_perc_with_pack = + rx_instance_ptr_local->num_rx_ring_100_perc_with_pack; + poll_pack_and_cred_info[ + client_type].rx_pack_info.num_rx_ring_0_perc_with_pack = + rx_instance_ptr_local->num_rx_ring_0_perc_with_pack; + poll_pack_and_cred_info[ + client_type].rx_pack_info.num_rx_ring_above_75_perc_pack = + rx_instance_ptr_local->num_rx_ring_above_75_perc_pack; + poll_pack_and_cred_info[ + client_type].rx_pack_info.num_rx_ring_above_25_perc_pack = + rx_instance_ptr_local->num_rx_ring_above_25_perc_pack; + poll_pack_and_cred_info[ + client_type].rx_pack_info.num_rx_ring_stats_polled = + rx_instance_ptr_local->num_rx_ring_stats_polled; + + diff_50_perc_pack = diff_rx_polled - (diff_100_perc_pack + + diff_75_perc_pack + diff_25_perc_pack + diff_0_perc_pack); + /** + * RX ring scale(summary) - Varies between 0 to 100 + * If the value tends towards 0, we can assume following things + * 1. UL throughput is increasing or + * 2. IPA packet processing speed decreasing or + * 3. Q6 packet pulling speed decreasing or + * 4. A7 packet pulling speed decreasing (Lan2Lan) + * + * If the value tends towards 100, we can assume following things + * 1. IPA processing data speed increasing or + * 2. Peripheral data pushing speed decreasing or + * 3. Equal to 100 during no UL data transfer + */ + rx_instance_ptr_local->rx_summary = ((diff_100_perc_pack * 0) + + (diff_75_perc_pack * 25) + + (diff_50_perc_pack * 50) + + (diff_25_perc_pack * 75) + + (diff_0_perc_pack * 100))/diff_rx_polled; + } +} + +static int ipa_get_wlan_inst_stats(unsigned long arg) +{ + struct ipa_lnx_wlan_inst_stats *wlan_stats; + int i, j; + int alloc_size; + int ep_idx; + int client_type; + struct ipa_lnx_pipe_info *pipe_info_ptr = NULL; + struct ipa_lnx_gsi_tx_debug_stats *tx_instance_ptr = NULL; + struct ipa_lnx_gsi_rx_debug_stats *rx_instance_ptr = NULL; + struct ipa_lnx_pipe_info *pipe_info_ptr_local = NULL; + struct ipa_lnx_gsi_tx_debug_stats *tx_instance_ptr_local = NULL; + struct ipa_lnx_gsi_rx_debug_stats *rx_instance_ptr_local = NULL; + struct wlan_instance_info *instance_ptr = NULL; + struct ipa_uc_dbg_ring_stats stats; + + if (!(ipa_lnx_agent_ctx.log_type_mask & TLPD_IPA_LOG_TYPE_WLAN_STATS)) { + IPA_STATS_ERR("Log type WLAN mask not set\n"); + return -EFAULT; + } + + alloc_size = sizeof(struct ipa_lnx_wlan_inst_stats) + + (ipa_lnx_agent_ctx.alloc_info.num_wlan_instances * + sizeof(struct wlan_instance_info)); + for (i = 0; i < ipa_lnx_agent_ctx.alloc_info.num_wlan_instances; i++) { + alloc_size = alloc_size + + (ipa_lnx_agent_ctx.alloc_info.wlan_inst_info[i].num_tx_instances * + sizeof(struct ipa_lnx_gsi_tx_debug_stats)) + + (ipa_lnx_agent_ctx.alloc_info.wlan_inst_info[i].num_rx_instances * + sizeof(struct ipa_lnx_gsi_rx_debug_stats)) + + (ipa_lnx_agent_ctx.alloc_info.wlan_inst_info[i].num_pipes * + sizeof(struct ipa_lnx_pipe_info)); + } + + wlan_stats = (struct ipa_lnx_wlan_inst_stats *) memdup_user(( + const void __user *)arg, alloc_size); + if (IS_ERR(wlan_stats)) { + IPA_STATS_ERR("copy from user failed"); + return -ENOMEM; + } + + if (!ipa_lnx_agent_ctx.alloc_info.num_wlan_instances) + goto success; + wlan_stats->num_wlan_instance = + ipa_lnx_agent_ctx.alloc_info.num_wlan_instances; + + instance_ptr = &wlan_stats->instance_info[0]; + for (i = 0; i < wlan_stats->num_wlan_instance; i++) { + instance_ptr->num_pipes = + ipa_lnx_agent_ctx.alloc_info.wlan_inst_info[i].num_pipes; + instance_ptr->gsi_debug_stats.num_tx_instances = + ipa_lnx_agent_ctx.alloc_info.wlan_inst_info[i].num_tx_instances; + instance_ptr->gsi_debug_stats.num_rx_instances = + ipa_lnx_agent_ctx.alloc_info.wlan_inst_info[i].num_rx_instances; + if(ipa3_get_wdi3_gsi_stats(&stats)) { + instance_ptr = (struct wlan_instance_info *)(( + uint64_t)instance_ptr + sizeof(struct wlan_instance_info) + + (instance_ptr->gsi_debug_stats.num_tx_instances * + sizeof(struct ipa_lnx_gsi_tx_debug_stats)) + + (instance_ptr->gsi_debug_stats.num_rx_instances * + sizeof(struct ipa_lnx_gsi_rx_debug_stats)) + + (instance_ptr->num_pipes * sizeof(struct ipa_lnx_pipe_info))); + continue; + } + instance_ptr->instance_id = i; + instance_ptr->wdi_ver = ipa_get_wdi_version(); + instance_ptr->wlan_mode = ipa_get_wlan_intf_mode(); + instance_ptr->wdi_over_gsi = ipa3_ctx->ipa_wdi3_over_gsi; + instance_ptr->dbs_mode = ipa_wdi_is_tx1_used(); + instance_ptr->pm_bandwidth = + ipa_pm_get_pm_clnt_throughput( + ipa_lnx_agent_ctx.alloc_info.wlan_inst_info[ + i].tx_inst_client_type[0]); + + tx_instance_ptr = (struct ipa_lnx_gsi_tx_debug_stats *)(( + uint64_t)instance_ptr + sizeof(struct wlan_instance_info)); + for (j = 0; j < ipa_lnx_agent_ctx.alloc_info.wlan_inst_info[ + i].num_tx_instances; j++) { + tx_instance_ptr_local = (struct ipa_lnx_gsi_tx_debug_stats *)(( + uint64_t)tx_instance_ptr + (j * + sizeof(struct ipa_lnx_gsi_tx_debug_stats))); + + client_type = ipa_lnx_agent_ctx.alloc_info.wlan_inst_info[ + i].tx_inst_client_type[j]; + tx_instance_ptr_local->tx_client = client_type; + tx_instance_ptr_local->num_tx_ring_100_perc_with_cred = + stats.u.ring[1 + j].ringFull; + tx_instance_ptr_local->num_tx_ring_0_perc_with_cred = + stats.u.ring[1 + j].ringEmpty; + tx_instance_ptr_local->num_tx_ring_above_75_perc_cred = + stats.u.ring[1 + j].ringUsageHigh; + tx_instance_ptr_local->num_tx_ring_above_25_perc_cred = + stats.u.ring[1 + j].ringUsageLow; + tx_instance_ptr_local->num_tx_ring_stats_polled = + stats.u.ring[1 + j].RingUtilCount; + ipa_lnx_calculate_gsi_ring_summay( + tx_instance_ptr_local, NULL, client_type); + + /* Currently reserved until GSI needs anything in future */ + tx_instance_ptr_local->num_tx_oob = 0; + tx_instance_ptr_local->num_tx_oob_time = 0; + tx_instance_ptr_local->gsi_debug1 = 0; + tx_instance_ptr_local->gsi_debug2 = 0; + tx_instance_ptr_local->gsi_debug3 = 0; + tx_instance_ptr_local->gsi_debug4 = 0; + } + + rx_instance_ptr = (struct ipa_lnx_gsi_rx_debug_stats *)(( + uint64_t)instance_ptr + sizeof(struct wlan_instance_info) + + (sizeof(struct ipa_lnx_gsi_tx_debug_stats) * ( + ipa_lnx_agent_ctx.alloc_info.wlan_inst_info[ + i].num_tx_instances))); + for (j = 0; j < ipa_lnx_agent_ctx.alloc_info.wlan_inst_info[ + i].num_rx_instances; j++) { + rx_instance_ptr_local = (struct ipa_lnx_gsi_rx_debug_stats *)(( + uint64_t)rx_instance_ptr + (j * + sizeof(struct ipa_lnx_gsi_rx_debug_stats))); + + client_type = + ipa_lnx_agent_ctx.alloc_info.wlan_inst_info[ + i].rx_inst_client_type[j]; + rx_instance_ptr_local->rx_client = + client_type; + rx_instance_ptr_local->num_rx_ring_100_perc_with_pack = + stats.u.ring[j].ringFull; + rx_instance_ptr_local->num_rx_ring_0_perc_with_pack = + stats.u.ring[j].ringEmpty; + rx_instance_ptr_local->num_rx_ring_above_75_perc_pack = + stats.u.ring[j].ringUsageHigh; + rx_instance_ptr_local->num_rx_ring_above_25_perc_pack = + stats.u.ring[j].ringUsageLow; + rx_instance_ptr_local->num_rx_ring_stats_polled = + stats.u.ring[j].RingUtilCount; + rx_instance_ptr_local->num_rx_drop_stats = 0; + ipa_lnx_calculate_gsi_ring_summay( + NULL, rx_instance_ptr_local, client_type); + + /* Currently reserved until GSI needs anything in future */ + rx_instance_ptr_local->gsi_debug1 = 0; + rx_instance_ptr_local->gsi_debug2 = 0; + rx_instance_ptr_local->gsi_debug3 = 0; + rx_instance_ptr_local->gsi_debug4 = 0; + } + + pipe_info_ptr = (struct ipa_lnx_pipe_info *)((uint64_t)instance_ptr + + sizeof(struct wlan_instance_info) + + (sizeof(struct ipa_lnx_gsi_tx_debug_stats) * + (ipa_lnx_agent_ctx.alloc_info.wlan_inst_info[i].num_tx_instances)) + + (sizeof(struct ipa_lnx_gsi_rx_debug_stats) * + (ipa_lnx_agent_ctx.alloc_info.wlan_inst_info[ + i].num_rx_instances))); + for (j = 0; j < instance_ptr->num_pipes; j++) { + pipe_info_ptr_local = (struct ipa_lnx_pipe_info *)(( + uint64_t)pipe_info_ptr + + (j * sizeof(struct ipa_lnx_pipe_info))); + + ep_idx = ipa_get_ep_mapping( + ipa_lnx_agent_ctx.alloc_info.wlan_inst_info[ + i].pipes_client_type[j]); + if (ep_idx == -1) { + kfree(wlan_stats); + return -EFAULT; + } + pipe_info_ptr_local->pipe_num = ep_idx; + ipa_get_gsi_pipe_info( + pipe_info_ptr_local, &ipa3_ctx->ep[ep_idx]); + } + + instance_ptr = (struct wlan_instance_info *)((uint64_t)pipe_info_ptr + + (sizeof(struct ipa_lnx_pipe_info) * (instance_ptr->num_pipes))); + } + +success: + if(copy_to_user((void __user *)arg, + (u8 *)wlan_stats, + alloc_size)) { + IPA_STATS_ERR("copy to user failed"); + kfree(wlan_stats); + return -EFAULT; + } + + kfree(wlan_stats); + return 0; +} + +static int ipa_get_eth_inst_stats(unsigned long arg) +{ + struct ipa_lnx_eth_inst_stats *eth_stats; + int i, j; + int alloc_size; + int ep_idx; + int client_type; + struct ipa_lnx_pipe_info *pipe_info_ptr = NULL; + struct ipa_lnx_gsi_tx_debug_stats *tx_instance_ptr = NULL; + struct ipa_lnx_gsi_rx_debug_stats *rx_instance_ptr = NULL; + struct ipa_lnx_pipe_info *pipe_info_ptr_local = NULL; + struct ipa_lnx_gsi_tx_debug_stats *tx_instance_ptr_local = NULL; + struct ipa_lnx_gsi_rx_debug_stats *rx_instance_ptr_local = NULL; + struct eth_instance_info *instance_ptr = NULL; + struct ipa_uc_dbg_ring_stats stats; + + if (!(ipa_lnx_agent_ctx.log_type_mask & TLPD_IPA_LOG_TYPE_ETH_STATS)) { + IPA_STATS_ERR("Log type ETH mask not set\n"); + return -EFAULT; + } + + alloc_size = sizeof(struct ipa_lnx_eth_inst_stats) + + (ipa_lnx_agent_ctx.alloc_info.num_eth_instances * + sizeof(struct eth_instance_info)); + for (i = 0; i < ipa_lnx_agent_ctx.alloc_info.num_eth_instances; i++) { + alloc_size = alloc_size + + (ipa_lnx_agent_ctx.alloc_info.eth_inst_info[i].num_tx_instances + * sizeof(struct ipa_lnx_gsi_tx_debug_stats)) + + (ipa_lnx_agent_ctx.alloc_info.eth_inst_info[i].num_rx_instances + * sizeof(struct ipa_lnx_gsi_rx_debug_stats)) + + (ipa_lnx_agent_ctx.alloc_info.eth_inst_info[i].num_pipes + * sizeof(struct ipa_lnx_pipe_info)); + } + + eth_stats = (struct ipa_lnx_eth_inst_stats *) memdup_user(( + const void __user *)arg, alloc_size); + if (IS_ERR(eth_stats)) { + IPA_STATS_ERR("copy from user failed"); + return -ENOMEM; + } + + eth_stats->num_eth_instance = + ipa_lnx_agent_ctx.alloc_info.num_eth_instances; + if (!ipa_lnx_agent_ctx.alloc_info.num_eth_instances) + goto success; + + instance_ptr = ð_stats->instance_info[0]; + for (i = 0; i < eth_stats->num_eth_instance; i++) { + instance_ptr->instance_id = i; + instance_ptr->num_pipes = + ipa_lnx_agent_ctx.alloc_info.eth_inst_info[i].num_pipes; + instance_ptr->gsi_debug_stats.num_tx_instances = + ipa_lnx_agent_ctx.alloc_info.eth_inst_info[i].num_tx_instances; + instance_ptr->gsi_debug_stats.num_rx_instances = + ipa_lnx_agent_ctx.alloc_info.eth_inst_info[i].num_rx_instances; + + tx_instance_ptr = (struct ipa_lnx_gsi_tx_debug_stats *)(( + uint64_t)instance_ptr + sizeof(struct eth_instance_info)); + for (j = 0; j < ipa_lnx_agent_ctx.alloc_info.eth_inst_info[ + i].num_tx_instances; j++) { + tx_instance_ptr_local = (struct ipa_lnx_gsi_tx_debug_stats *)(( + uint64_t)tx_instance_ptr + (j * + sizeof(struct ipa_lnx_gsi_tx_debug_stats))); + + /* Eth mode is sent in the tx_inst_client_type variable only */ + instance_ptr->eth_mode = + ipa_lnx_agent_ctx.alloc_info.eth_inst_info[ + i].tx_inst_client_type[j]; + if (instance_ptr->eth_mode == IPA_ETH_CLIENT_AQC107 || + instance_ptr->eth_mode == IPA_ETH_CLIENT_AQC113 || + instance_ptr->eth_mode == IPA_ETH_CLIENT_NTN || +#if IPA_ETH_API_VER >= 2 + instance_ptr->eth_mode == IPA_ETH_CLIENT_NTN3 || +#endif + instance_ptr->eth_mode == IPA_ETH_CLIENT_EMAC) { + + if(instance_ptr->eth_mode == IPA_ETH_CLIENT_NTN +#if IPA_ETH_API_VER >= 2 + || instance_ptr->eth_mode == IPA_ETH_CLIENT_NTN3 +#endif + ) { + if(ipa3_get_ntn_gsi_stats(&stats)) { + instance_ptr = (struct eth_instance_info *)(( + uint64_t)instance_ptr + + sizeof(struct eth_instance_info) + + (instance_ptr->gsi_debug_stats.num_tx_instances * + sizeof(struct ipa_lnx_gsi_tx_debug_stats)) + + (instance_ptr->gsi_debug_stats.num_rx_instances * + sizeof(struct ipa_lnx_gsi_rx_debug_stats)) + + (instance_ptr->num_pipes * + sizeof(struct ipa_lnx_pipe_info))); + continue; + } + } else { + if(ipa3_get_aqc_gsi_stats(&stats)) { + instance_ptr = (struct eth_instance_info *)(( + uint64_t)instance_ptr + + sizeof(struct eth_instance_info) + + (instance_ptr->gsi_debug_stats.num_tx_instances * + sizeof(struct ipa_lnx_gsi_tx_debug_stats)) + + (instance_ptr->gsi_debug_stats.num_rx_instances * + sizeof(struct ipa_lnx_gsi_rx_debug_stats)) + + (instance_ptr->num_pipes * + sizeof(struct ipa_lnx_pipe_info))); + continue; + } + } + + if (instance_ptr->eth_mode == IPA_ETH_CLIENT_NTN || + instance_ptr->eth_mode == IPA_ETH_CLIENT_EMAC) + tx_instance_ptr_local->tx_client = + IPA_CLIENT_ETHERNET_CONS; + else + tx_instance_ptr_local->tx_client = + IPA_CLIENT_AQC_ETHERNET_CONS; +#if IPA_ETH_API_VER >= 2 + /* Get the client pipe info[0] from the allocation info context only if it is NTN3 */ + if ((instance_ptr->eth_mode == IPA_ETH_CLIENT_NTN3)) { + tx_instance_ptr_local->tx_client = + ipa_lnx_agent_ctx.alloc_info.eth_inst_info[ + i].pipes_client_type[0]; + } +#endif + client_type = tx_instance_ptr_local->tx_client; + instance_ptr->pm_bandwidth = + ipa_pm_get_pm_clnt_throughput(client_type); + tx_instance_ptr_local->num_tx_ring_100_perc_with_cred = + stats.u.ring[1].ringFull; + tx_instance_ptr_local->num_tx_ring_0_perc_with_cred = + stats.u.ring[1].ringEmpty; + tx_instance_ptr_local->num_tx_ring_above_75_perc_cred = + stats.u.ring[1].ringUsageHigh; + tx_instance_ptr_local->num_tx_ring_above_25_perc_cred = + stats.u.ring[1].ringUsageLow; + tx_instance_ptr_local->num_tx_ring_stats_polled = + stats.u.ring[1].RingUtilCount; + ipa_lnx_calculate_gsi_ring_summay( + tx_instance_ptr_local, NULL, client_type); + + /* Currently reserved until GSI needs anything in future */ + tx_instance_ptr_local->num_tx_oob = 0; + tx_instance_ptr_local->num_tx_oob_time = 0; + tx_instance_ptr_local->gsi_debug1 = 0; + tx_instance_ptr_local->gsi_debug2 = 0; + tx_instance_ptr_local->gsi_debug3 = 0; + tx_instance_ptr_local->gsi_debug4 = 0; + } else if (instance_ptr->eth_mode == IPA_ETH_CLIENT_RTK8111K || + instance_ptr->eth_mode == IPA_ETH_CLIENT_RTK8125B) { + + if(ipa3_get_rtk_gsi_stats(&stats)) { + instance_ptr = (struct eth_instance_info *)(( + uint64_t)instance_ptr + + sizeof(struct eth_instance_info) + + (instance_ptr->gsi_debug_stats.num_tx_instances * + sizeof(struct ipa_lnx_gsi_tx_debug_stats)) + + (instance_ptr->gsi_debug_stats.num_rx_instances * + sizeof(struct ipa_lnx_gsi_rx_debug_stats)) + + (instance_ptr->num_pipes * + sizeof(struct ipa_lnx_pipe_info))); + continue; + } + client_type = IPA_CLIENT_RTK_ETHERNET_CONS; + instance_ptr->pm_bandwidth = + ipa_pm_get_pm_clnt_throughput(client_type); + tx_instance_ptr_local->tx_client = client_type; + tx_instance_ptr_local->num_tx_ring_100_perc_with_cred = + stats.u.rtk[1].commStats.ringFull; + tx_instance_ptr_local->num_tx_ring_0_perc_with_cred = + stats.u.rtk[1].commStats.ringEmpty; + tx_instance_ptr_local->num_tx_ring_above_75_perc_cred = + stats.u.rtk[1].commStats.ringUsageHigh; + tx_instance_ptr_local->num_tx_ring_above_25_perc_cred = + stats.u.rtk[1].commStats.ringUsageLow; + tx_instance_ptr_local->num_tx_ring_stats_polled = + stats.u.rtk[1].commStats.RingUtilCount; + ipa_lnx_calculate_gsi_ring_summay( + tx_instance_ptr_local, NULL, client_type); + + /* Currently reserved until GSI needs anything in future */ + tx_instance_ptr_local->num_tx_oob = 0; + tx_instance_ptr_local->num_tx_oob_time = 0; + tx_instance_ptr_local->gsi_debug1 = 0; + tx_instance_ptr_local->gsi_debug2 = 0; + tx_instance_ptr_local->gsi_debug3 = 0; + tx_instance_ptr_local->gsi_debug4 = 0; + } else IPA_STATS_ERR("Eth tx client type not found"); + } + + rx_instance_ptr = (struct ipa_lnx_gsi_rx_debug_stats *)(( + uint64_t)instance_ptr + sizeof(struct eth_instance_info) + + (sizeof(struct ipa_lnx_gsi_tx_debug_stats) * + (ipa_lnx_agent_ctx.alloc_info.eth_inst_info[ + i].num_tx_instances))); + for (j = 0; j < ipa_lnx_agent_ctx.alloc_info.eth_inst_info[ + i].num_rx_instances; j++) { + rx_instance_ptr_local = (struct ipa_lnx_gsi_rx_debug_stats *)(( + uint64_t)rx_instance_ptr + (j * + sizeof(struct ipa_lnx_gsi_rx_debug_stats))); + + if ((instance_ptr->eth_mode == IPA_ETH_CLIENT_AQC107 || + instance_ptr->eth_mode == IPA_ETH_CLIENT_AQC113 || + instance_ptr->eth_mode == IPA_ETH_CLIENT_NTN || +#if IPA_ETH_API_VER >= 2 + instance_ptr->eth_mode == IPA_ETH_CLIENT_NTN3 || +#endif + instance_ptr->eth_mode == IPA_ETH_CLIENT_EMAC)) { + + if (instance_ptr->eth_mode == IPA_ETH_CLIENT_NTN || + instance_ptr->eth_mode == IPA_ETH_CLIENT_EMAC) + rx_instance_ptr_local->rx_client = + IPA_CLIENT_ETHERNET_PROD; + else + rx_instance_ptr_local->rx_client = + IPA_CLIENT_AQC_ETHERNET_PROD; +#if IPA_ETH_API_VER >= 2 + /* Get the client pipe info[1] from the allocation info context only if it is NTN3 */ + if ((instance_ptr->eth_mode == IPA_ETH_CLIENT_NTN3)) { + rx_instance_ptr_local->rx_client = + ipa_lnx_agent_ctx.alloc_info.eth_inst_info[ + i].pipes_client_type[1]; + } +#endif + client_type = rx_instance_ptr_local->rx_client; + rx_instance_ptr_local->num_rx_ring_100_perc_with_pack = + stats.u.ring[0].ringFull; + rx_instance_ptr_local->num_rx_ring_0_perc_with_pack = + stats.u.ring[0].ringEmpty; + rx_instance_ptr_local->num_rx_ring_above_75_perc_pack = + stats.u.ring[0].ringUsageHigh; + rx_instance_ptr_local->num_rx_ring_above_25_perc_pack = + stats.u.ring[0].ringUsageLow; + rx_instance_ptr_local->num_rx_ring_stats_polled = + stats.u.ring[0].RingUtilCount; + rx_instance_ptr_local->num_rx_drop_stats = 0; + ipa_lnx_calculate_gsi_ring_summay( + NULL, rx_instance_ptr_local, client_type); + + /* Currently reserved until GSI needs anything in future */ + rx_instance_ptr_local->gsi_debug1 = 0; + rx_instance_ptr_local->gsi_debug2 = 0; + rx_instance_ptr_local->gsi_debug3 = 0; + rx_instance_ptr_local->gsi_debug4 = 0; + } else if (instance_ptr->eth_mode == IPA_ETH_CLIENT_RTK8111K || + instance_ptr->eth_mode == IPA_ETH_CLIENT_RTK8125B) { + + client_type = IPA_CLIENT_RTK_ETHERNET_PROD; + rx_instance_ptr_local->rx_client = client_type; + rx_instance_ptr_local->num_rx_ring_100_perc_with_pack = + stats.u.rtk[0].commStats.ringFull; + rx_instance_ptr_local->num_rx_ring_0_perc_with_pack = + stats.u.rtk[0].commStats.ringEmpty; + rx_instance_ptr_local->num_rx_ring_above_75_perc_pack = + stats.u.rtk[0].commStats.ringUsageHigh; + rx_instance_ptr_local->num_rx_ring_above_25_perc_pack = + stats.u.rtk[0].commStats.ringUsageLow; + rx_instance_ptr_local->num_rx_ring_stats_polled = + stats.u.rtk[0].commStats.RingUtilCount; + rx_instance_ptr_local->num_rx_drop_stats = 0; + ipa_lnx_calculate_gsi_ring_summay( + NULL, rx_instance_ptr_local, client_type); + + /* Currently reserved until GSI needs anything in future */ + rx_instance_ptr_local->gsi_debug1 = 0; + rx_instance_ptr_local->gsi_debug2 = 0; + rx_instance_ptr_local->gsi_debug3 = 0; + rx_instance_ptr_local->gsi_debug4 = 0; + } else IPA_STATS_ERR("Eth rx client type not found"); + } + + pipe_info_ptr = (struct ipa_lnx_pipe_info *)((uint64_t)instance_ptr + + sizeof(struct eth_instance_info) + + (sizeof(struct ipa_lnx_gsi_tx_debug_stats) * + (ipa_lnx_agent_ctx.alloc_info.eth_inst_info[i].num_tx_instances)) + + (sizeof(struct ipa_lnx_gsi_rx_debug_stats) * + (ipa_lnx_agent_ctx.alloc_info.eth_inst_info[ + i].num_rx_instances))); + for (j = 0; j < instance_ptr->num_pipes; j++) { + pipe_info_ptr_local = (struct ipa_lnx_pipe_info *)(( + uint64_t)pipe_info_ptr + (j * + sizeof(struct ipa_lnx_pipe_info))); + + ep_idx = ipa_get_ep_mapping( + ipa_lnx_agent_ctx.alloc_info.eth_inst_info[ + i].pipes_client_type[j]); + if (ep_idx == -1) { + kfree(eth_stats); + return -EFAULT; + } + + pipe_info_ptr_local->pipe_num = ep_idx; + ipa_get_gsi_pipe_info( + pipe_info_ptr_local, &ipa3_ctx->ep[ep_idx]); + } + + instance_ptr = (struct eth_instance_info *)(( + uint64_t)pipe_info_ptr + (sizeof(struct ipa_lnx_pipe_info) + * (instance_ptr->num_pipes))); + } + +success: + if(copy_to_user((void __user *)arg, + (u8 *)eth_stats, + alloc_size)) { + IPA_STATS_ERR("copy to user failed"); + kfree(eth_stats); + return -EFAULT; + } + + kfree(eth_stats); + return 0; +} + +static int ipa_get_usb_inst_stats(unsigned long arg) +{ + struct ipa_lnx_usb_inst_stats *usb_stats; + int i, j; + int alloc_size; + int ep_idx; + int client_type; + struct ipa_lnx_pipe_info *pipe_info_ptr = NULL; + struct ipa_lnx_gsi_tx_debug_stats *tx_instance_ptr = NULL; + struct ipa_lnx_gsi_rx_debug_stats *rx_instance_ptr = NULL; + struct ipa_lnx_pipe_info *pipe_info_ptr_local = NULL; + struct ipa_lnx_gsi_tx_debug_stats *tx_instance_ptr_local = NULL; + struct ipa_lnx_gsi_rx_debug_stats *rx_instance_ptr_local = NULL; + struct usb_instance_info *instance_ptr = NULL; + struct ipa_uc_dbg_ring_stats stats; + + if (!(ipa_lnx_agent_ctx.log_type_mask & TLPD_IPA_LOG_TYPE_USB_STATS)) { + IPA_STATS_ERR("Log type USB mask not set\n"); + return -EFAULT; + } + + alloc_size = sizeof(struct ipa_lnx_usb_inst_stats) + + (ipa_lnx_agent_ctx.alloc_info.num_usb_instances * + sizeof(struct usb_instance_info)); + for (i = 0; i < ipa_lnx_agent_ctx.alloc_info.num_usb_instances; i++) { + alloc_size = alloc_size + + (ipa_lnx_agent_ctx.alloc_info.usb_inst_info[i].num_tx_instances * + sizeof(struct ipa_lnx_gsi_tx_debug_stats)) + + (ipa_lnx_agent_ctx.alloc_info.usb_inst_info[i].num_rx_instances * + sizeof(struct ipa_lnx_gsi_rx_debug_stats)) + + (ipa_lnx_agent_ctx.alloc_info.usb_inst_info[i].num_pipes * + sizeof(struct ipa_lnx_pipe_info)); + } + + usb_stats = (struct ipa_lnx_usb_inst_stats *) memdup_user(( + const void __user *)arg, alloc_size); + if (IS_ERR(usb_stats)) { + IPA_STATS_ERR("copy from user failed"); + return -ENOMEM; + } + + usb_stats->num_usb_instance = + ipa_lnx_agent_ctx.alloc_info.num_usb_instances; + if (!ipa_lnx_agent_ctx.alloc_info.num_usb_instances) + goto success; + + instance_ptr = &usb_stats->instance_info[0]; + for (i = 0; i < usb_stats->num_usb_instance; i++) { + instance_ptr->instance_id = i; + instance_ptr->usb_mode = ipa_lnx_agent_ctx.usb_teth_prot[i]; + instance_ptr->pm_bandwidth = + ipa_pm_get_pm_clnt_throughput(ipa_lnx_agent_ctx.alloc_info.usb_inst_info[ + i].tx_inst_client_type[0]); + instance_ptr->num_pipes = + ipa_lnx_agent_ctx.alloc_info.usb_inst_info[i].num_pipes; + instance_ptr->gsi_debug_stats.num_tx_instances = + ipa_lnx_agent_ctx.alloc_info.usb_inst_info[i].num_tx_instances; + instance_ptr->gsi_debug_stats.num_rx_instances = + ipa_lnx_agent_ctx.alloc_info.usb_inst_info[i].num_rx_instances; + if(ipa3_get_usb_gsi_stats(&stats)) { + instance_ptr = (struct usb_instance_info *)((uint64_t)instance_ptr + + sizeof(struct usb_instance_info) + + (instance_ptr->gsi_debug_stats.num_tx_instances * + sizeof(struct ipa_lnx_gsi_tx_debug_stats)) + + (instance_ptr->gsi_debug_stats.num_rx_instances * + sizeof(struct ipa_lnx_gsi_rx_debug_stats)) + + (instance_ptr->num_pipes * sizeof(struct ipa_lnx_pipe_info))); + continue; + } + + tx_instance_ptr = (struct ipa_lnx_gsi_tx_debug_stats *)(( + uint64_t)instance_ptr + sizeof(struct usb_instance_info)); + for (j = 0; j < ipa_lnx_agent_ctx.alloc_info.usb_inst_info[ + i].num_tx_instances; j++) { + tx_instance_ptr_local = (struct ipa_lnx_gsi_tx_debug_stats *)(( + uint64_t)tx_instance_ptr + (j * + sizeof(struct ipa_lnx_gsi_tx_debug_stats))); + + client_type = ipa_lnx_agent_ctx.alloc_info.usb_inst_info[ + i].tx_inst_client_type[j]; + tx_instance_ptr_local->tx_client = client_type; + tx_instance_ptr_local->num_tx_ring_100_perc_with_cred = + stats.u.ring[1 + j].ringFull; + tx_instance_ptr_local->num_tx_ring_0_perc_with_cred = + stats.u.ring[1 + j].ringEmpty; + tx_instance_ptr_local->num_tx_ring_above_75_perc_cred = + stats.u.ring[1 + j].ringUsageHigh; + tx_instance_ptr_local->num_tx_ring_above_25_perc_cred = + stats.u.ring[1 + j].ringUsageLow; + tx_instance_ptr_local->num_tx_ring_stats_polled = + stats.u.ring[1 + j].RingUtilCount; + ipa_lnx_calculate_gsi_ring_summay( + tx_instance_ptr_local, NULL, client_type); + + /* Currently reserved until GSI needs anything in future */ + tx_instance_ptr_local->num_tx_oob = 0; + tx_instance_ptr_local->num_tx_oob_time = 0; + tx_instance_ptr_local->gsi_debug1 = 0; + tx_instance_ptr_local->gsi_debug2 = 0; + tx_instance_ptr_local->gsi_debug3 = 0; + tx_instance_ptr_local->gsi_debug4 = 0; + } + + rx_instance_ptr = (struct ipa_lnx_gsi_rx_debug_stats *) (( + uint64_t)instance_ptr + sizeof(struct usb_instance_info) + + (sizeof(struct ipa_lnx_gsi_tx_debug_stats) * + (ipa_lnx_agent_ctx.alloc_info.usb_inst_info[ + i].num_tx_instances))); + for (j = 0; j < ipa_lnx_agent_ctx.alloc_info.usb_inst_info[ + i].num_rx_instances; j++) { + rx_instance_ptr_local = (struct ipa_lnx_gsi_rx_debug_stats *)(( + uint64_t)rx_instance_ptr + + (j * sizeof(struct ipa_lnx_gsi_rx_debug_stats))); + + client_type = ipa_lnx_agent_ctx.alloc_info.usb_inst_info[ + i].rx_inst_client_type[j]; + rx_instance_ptr_local->rx_client = client_type; + rx_instance_ptr_local->num_rx_ring_100_perc_with_pack = + stats.u.ring[j].ringFull; + rx_instance_ptr_local->num_rx_ring_0_perc_with_pack = + stats.u.ring[j].ringEmpty; + rx_instance_ptr_local->num_rx_ring_above_75_perc_pack = + stats.u.ring[j].ringUsageHigh; + rx_instance_ptr_local->num_rx_ring_above_25_perc_pack = + stats.u.ring[j].ringUsageLow; + rx_instance_ptr_local->num_rx_ring_stats_polled = + stats.u.ring[j].RingUtilCount; + rx_instance_ptr_local->num_rx_drop_stats = 0; + ipa_lnx_calculate_gsi_ring_summay( + NULL, rx_instance_ptr_local, client_type); + + /* Currently reserved until GSI needs anything in future */ + rx_instance_ptr_local->gsi_debug1 = 0; + rx_instance_ptr_local->gsi_debug2 = 0; + rx_instance_ptr_local->gsi_debug3 = 0; + rx_instance_ptr_local->gsi_debug4 = 0; + } + + pipe_info_ptr = (struct ipa_lnx_pipe_info *)((uint64_t)instance_ptr + + sizeof(struct usb_instance_info) + + (sizeof(struct ipa_lnx_gsi_tx_debug_stats) * + (ipa_lnx_agent_ctx.alloc_info.usb_inst_info[i].num_tx_instances)) + + (sizeof(struct ipa_lnx_gsi_rx_debug_stats) * + (ipa_lnx_agent_ctx.alloc_info.usb_inst_info[ + i].num_rx_instances))); + for (j = 0; j < instance_ptr->num_pipes; j++) { + pipe_info_ptr_local = (struct ipa_lnx_pipe_info *)(( + uint64_t)pipe_info_ptr + (j * + sizeof(struct ipa_lnx_pipe_info))); + + ep_idx = ipa_get_ep_mapping( + ipa_lnx_agent_ctx.alloc_info.usb_inst_info[ + i].pipes_client_type[j]); + if (ep_idx == -1) { + kfree(usb_stats); + return -EFAULT; + } + pipe_info_ptr_local->pipe_num = ep_idx; + ipa_get_gsi_pipe_info( + pipe_info_ptr_local, &ipa3_ctx->ep[ep_idx]); + } + + instance_ptr = (struct usb_instance_info *) ((uint64_t)pipe_info_ptr + + (sizeof(struct ipa_lnx_pipe_info) * (instance_ptr->num_pipes))); + } + +success: + if(copy_to_user((void __user *)arg, + (u8 *)usb_stats, + alloc_size)) { + IPA_STATS_ERR("copy to user failed"); + kfree(usb_stats); + return -EFAULT; + } + + kfree(usb_stats); + return 0; +} + +#if IS_ENABLED(CONFIG_IPA3_MHI_PRIME_MANAGER) +static int ipa_get_mhip_inst_stats(unsigned long arg) +{ + struct ipa_lnx_mhip_inst_stats *mhip_stats; + int i, j; + int alloc_size; + int ep_idx; + int client_type; + struct ipa_lnx_pipe_info *pipe_info_ptr = NULL; + struct ipa_lnx_gsi_tx_debug_stats *tx_instance_ptr = NULL; + struct ipa_lnx_gsi_rx_debug_stats *rx_instance_ptr = NULL; + struct ipa_lnx_pipe_info *pipe_info_ptr_local = NULL; + struct ipa_lnx_gsi_tx_debug_stats *tx_instance_ptr_local = NULL; + struct ipa_lnx_gsi_rx_debug_stats *rx_instance_ptr_local = NULL; + struct mhip_instance_info *instance_ptr = NULL; + struct ipa_uc_dbg_ring_stats stats; + + if (!(ipa_lnx_agent_ctx.log_type_mask & TLPD_IPA_LOG_TYPE_MHIP_STATS)) { + IPA_STATS_ERR("Log type MHIP mask not set\n"); + return -EFAULT; + } + + alloc_size = sizeof(struct ipa_lnx_mhip_inst_stats) + + (ipa_lnx_agent_ctx.alloc_info.num_mhip_instances * + sizeof(struct mhip_instance_info)); + for (i = 0; i < ipa_lnx_agent_ctx.alloc_info.num_mhip_instances; i++) { + alloc_size = alloc_size + + (ipa_lnx_agent_ctx.alloc_info.mhip_inst_info[i].num_tx_instances * + sizeof(struct ipa_lnx_gsi_tx_debug_stats)) + + (ipa_lnx_agent_ctx.alloc_info.mhip_inst_info[i].num_rx_instances * + sizeof(struct ipa_lnx_gsi_rx_debug_stats)) + + (ipa_lnx_agent_ctx.alloc_info.mhip_inst_info[i].num_pipes * + sizeof(struct ipa_lnx_pipe_info)); + } + + mhip_stats = (struct ipa_lnx_mhip_inst_stats *) memdup_user(( + const void __user *)arg, alloc_size); + if (IS_ERR(mhip_stats)) { + IPA_STATS_ERR("copy from user failed"); + return -ENOMEM; + } + + if (!ipa_lnx_agent_ctx.alloc_info.num_mhip_instances) + goto success; + mhip_stats->num_mhip_instance = + ipa_lnx_agent_ctx.alloc_info.num_mhip_instances; + + instance_ptr = &mhip_stats->instance_info[0]; + for (i = 0; i < mhip_stats->num_mhip_instance; i++) { + instance_ptr->instance_id = i; + instance_ptr->mhip_mode = + ipa_lnx_agent_ctx.usb_teth_prot[i]; + instance_ptr->pm_bandwidth = + ipa_pm_get_pm_clnt_throughput( + ipa_lnx_agent_ctx.alloc_info.mhip_inst_info[ + i].tx_inst_client_type[0]); + instance_ptr->num_pipes = + ipa_lnx_agent_ctx.alloc_info.mhip_inst_info[i].num_pipes; + instance_ptr->gsi_debug_stats.num_tx_instances = + ipa_lnx_agent_ctx.alloc_info.mhip_inst_info[i].num_tx_instances; + instance_ptr->gsi_debug_stats.num_rx_instances = + ipa_lnx_agent_ctx.alloc_info.mhip_inst_info[i].num_rx_instances; + if(ipa3_get_mhip_gsi_stats(&stats)) { + instance_ptr = (struct mhip_instance_info *)(( + uint64_t)instance_ptr + sizeof(struct mhip_instance_info) + + (instance_ptr->gsi_debug_stats.num_tx_instances * + sizeof(struct ipa_lnx_gsi_tx_debug_stats)) + + (instance_ptr->gsi_debug_stats.num_rx_instances * + sizeof(struct ipa_lnx_gsi_rx_debug_stats)) + + (instance_ptr->num_pipes * sizeof(struct ipa_lnx_pipe_info))); + continue; + } + + tx_instance_ptr = (struct ipa_lnx_gsi_tx_debug_stats *)(( + uint64_t)instance_ptr + sizeof(struct mhip_instance_info)); + for (j = 0; j < ipa_lnx_agent_ctx.alloc_info.mhip_inst_info[ + i].num_tx_instances; j++) { + tx_instance_ptr_local = (struct ipa_lnx_gsi_tx_debug_stats *)(( + uint64_t)tx_instance_ptr + (j * + sizeof(struct ipa_lnx_gsi_tx_debug_stats))); + + client_type = ipa_lnx_agent_ctx.alloc_info.mhip_inst_info[ + i].tx_inst_client_type[j]; + tx_instance_ptr_local->tx_client = client_type; + tx_instance_ptr_local->num_tx_ring_100_perc_with_cred = + stats.u.ring[1 + (j*2)].ringFull; + tx_instance_ptr_local->num_tx_ring_0_perc_with_cred = + stats.u.ring[1 + (j*2)].ringEmpty; + tx_instance_ptr_local->num_tx_ring_above_75_perc_cred = + stats.u.ring[1 + (j*2)].ringUsageHigh; + tx_instance_ptr_local->num_tx_ring_above_25_perc_cred = + stats.u.ring[1 + (j*2)].ringUsageLow; + tx_instance_ptr_local->num_tx_ring_stats_polled = + stats.u.ring[1 + (j*2)].RingUtilCount; + ipa_lnx_calculate_gsi_ring_summay( + tx_instance_ptr_local, NULL, client_type); + + /* Currently reserved until GSI needs anything in future */ + tx_instance_ptr_local->num_tx_oob = 0; + tx_instance_ptr_local->num_tx_oob_time = 0; + tx_instance_ptr_local->gsi_debug1 = 0; + tx_instance_ptr_local->gsi_debug2 = 0; + tx_instance_ptr_local->gsi_debug3 = 0; + tx_instance_ptr_local->gsi_debug4 = 0; + } + + rx_instance_ptr = (struct ipa_lnx_gsi_rx_debug_stats *)(( + uint64_t)instance_ptr + sizeof(struct mhip_instance_info) + + (sizeof(struct ipa_lnx_gsi_tx_debug_stats) * ( + ipa_lnx_agent_ctx.alloc_info.mhip_inst_info[ + i].num_tx_instances))); + for (j = 0; j < ipa_lnx_agent_ctx.alloc_info.mhip_inst_info[ + i].num_rx_instances; j++) { + rx_instance_ptr_local = (struct ipa_lnx_gsi_rx_debug_stats *)(( + uint64_t)rx_instance_ptr + + (j * sizeof(struct ipa_lnx_gsi_rx_debug_stats))); + + client_type = ipa_lnx_agent_ctx.alloc_info.mhip_inst_info[ + i].rx_inst_client_type[j]; + rx_instance_ptr_local->rx_client = client_type; + rx_instance_ptr_local->num_rx_ring_100_perc_with_pack = + stats.u.ring[2*j].ringFull; + rx_instance_ptr_local->num_rx_ring_0_perc_with_pack = + stats.u.ring[2*j].ringEmpty; + rx_instance_ptr_local->num_rx_ring_above_75_perc_pack = + stats.u.ring[2*j].ringUsageHigh; + rx_instance_ptr_local->num_rx_ring_above_25_perc_pack = + stats.u.ring[2*j].ringUsageLow; + rx_instance_ptr_local->num_rx_ring_stats_polled = + stats.u.ring[2*j].RingUtilCount; + rx_instance_ptr_local->num_rx_drop_stats = 0; + ipa_lnx_calculate_gsi_ring_summay(NULL, + rx_instance_ptr_local, client_type); + + /* Currently reserved until GSI needs anything in future */ + rx_instance_ptr_local->gsi_debug1 = 0; + rx_instance_ptr_local->gsi_debug2 = 0; + rx_instance_ptr_local->gsi_debug3 = 0; + rx_instance_ptr_local->gsi_debug4 = 0; + } + + pipe_info_ptr = (struct ipa_lnx_pipe_info *)((uint64_t)instance_ptr + + sizeof(struct mhip_instance_info) + + (sizeof(struct ipa_lnx_gsi_tx_debug_stats) * ( + ipa_lnx_agent_ctx.alloc_info.mhip_inst_info[ + i].num_tx_instances)) + + (sizeof(struct ipa_lnx_gsi_rx_debug_stats) * ( + ipa_lnx_agent_ctx.alloc_info.mhip_inst_info[ + i].num_rx_instances))); + for (j = 0; j < instance_ptr->num_pipes; j++) { + pipe_info_ptr_local = (struct ipa_lnx_pipe_info *)((uint64_t) + pipe_info_ptr + (j * sizeof(struct ipa_lnx_pipe_info))); + + ep_idx = ipa_get_ep_mapping( + ipa_lnx_agent_ctx.alloc_info.mhip_inst_info[ + i].pipes_client_type[j]); + if (ep_idx == -1) { + kfree(mhip_stats); + return -EFAULT; + } + pipe_info_ptr_local->pipe_num = ep_idx; + ipa_get_gsi_pipe_info( + pipe_info_ptr_local, &ipa3_ctx->ep[ep_idx]); + } + instance_ptr = (struct mhip_instance_info *)((uint64_t)pipe_info_ptr + + (sizeof(struct ipa_lnx_pipe_info) * (instance_ptr->num_pipes))); + } + +success: + if(copy_to_user((void __user *)arg, + (u8 *)mhip_stats, + alloc_size)) { + IPA_STATS_ERR("copy to user failed"); + kfree(mhip_stats); + return -EFAULT; + } + + kfree(mhip_stats); + return 0; +} +#endif + +static int ipa_get_page_recycle_stats(unsigned long arg) +{ + struct ipa_lnx_pipe_page_recycling_stats *page_recycle_stats; + int alloc_size; + + alloc_size = sizeof(struct ipa_lnx_pipe_page_recycling_stats); + + page_recycle_stats = (struct ipa_lnx_pipe_page_recycling_stats *) memdup_user(( + const void __user *)arg, alloc_size); + if (IS_ERR(page_recycle_stats)) { + IPA_STATS_ERR("copy from user failed"); + return -ENOMEM; + } + + mutex_lock(&ipa3_ctx->recycle_stats_collection_lock); + memcpy(page_recycle_stats, &ipa3_ctx->recycle_stats, + sizeof(struct ipa_lnx_pipe_page_recycling_stats)); + + /* Clear all the data and valid bits */ + memset(&ipa3_ctx->recycle_stats, 0, + sizeof(struct ipa_lnx_pipe_page_recycling_stats)); + + mutex_unlock(&ipa3_ctx->recycle_stats_collection_lock); + + if(copy_to_user((void __user *)arg, + (u8 *)page_recycle_stats, + alloc_size)) { + IPA_STATS_ERR("copy to user failed"); + kfree(page_recycle_stats); + return -EFAULT; + } + + kfree(page_recycle_stats); + return 0; +} + +static int ipa_stats_get_alloc_info(unsigned long arg) +{ + int i = 0; + int j, k; + int holb_drop_stats_num_pipes = 0; + int ipa_ep_idx_tx, ipa_ep_idx_rx; + int ipa_client_type; + int reg_idx; + int index; + int eth_instance_id; + + if (copy_from_user(&ipa_lnx_agent_ctx, u64_to_user_ptr((u64) arg), + sizeof(struct ipa_lnx_stats_tlpd_ctx))) { + IPA_STATS_ERR("copy from user failed"); + return -EFAULT; + } + + /* For generic stats */ + if (ipa_lnx_agent_ctx.log_type_mask & + TLPD_IPA_LOG_TYPE_GENERIC_STATS) { + for (i = 0; i < IPA_CLIENT_MAX; i++) { + int ep_idx = ipa_get_ep_mapping(i); + + if ((ep_idx == -1) || (!IPA_CLIENT_IS_CONS(i)) || + (IPA_CLIENT_IS_TEST(i))) + continue; + + reg_idx = ipahal_get_ep_reg_idx(ep_idx); + if (!(ipa3_ctx->hw_stats && + (ipa3_ctx->hw_stats->drop.init.enabled_bitmask[reg_idx] & + ipahal_get_ep_bit(ep_idx)))) + continue; + + holb_drop_stats_num_pipes++; + } + ipa_lnx_agent_ctx.alloc_info.num_holb_drop_stats_clients = + holb_drop_stats_num_pipes; + ipa_lnx_agent_ctx.alloc_info.num_holb_mon_stats_clients = + ipa3_ctx->uc_ctx.holb_monitor.num_holb_clients; + } + + /* For clock stats */ + if (ipa_lnx_agent_ctx.log_type_mask & TLPD_IPA_LOG_TYPE_CLOCK_STATS) + ipa_lnx_agent_ctx.alloc_info.num_pm_clients = + ipa3_get_max_num_pipes(); + + /* For WLAN instance */ + if (ipa_lnx_agent_ctx.log_type_mask & TLPD_IPA_LOG_TYPE_WLAN_STATS) { + ipa_ep_idx_tx = ipa_get_ep_mapping(IPA_CLIENT_WLAN2_CONS); + ipa_ep_idx_rx = ipa_get_ep_mapping(IPA_CLIENT_WLAN2_PROD); + if ((ipa_ep_idx_tx == -1) || (ipa_ep_idx_rx == -1) || + !ipa3_ctx->ep[ipa_ep_idx_tx].valid || + !ipa3_ctx->ep[ipa_ep_idx_rx].valid) { + ipa_lnx_agent_ctx.alloc_info.num_wlan_instances = 0; + } else { + ipa_lnx_agent_ctx.alloc_info.num_wlan_instances = 1; + ipa_lnx_agent_ctx.alloc_info.wlan_inst_info[0].num_pipes = 2; + ipa_lnx_agent_ctx.alloc_info.wlan_inst_info[0].num_tx_instances = 1; + ipa_lnx_agent_ctx.alloc_info.wlan_inst_info[0].num_rx_instances = 1; + ipa_lnx_agent_ctx.alloc_info.wlan_inst_info[0].pipes_client_type[0] + = IPA_CLIENT_WLAN2_CONS; + ipa_lnx_agent_ctx.alloc_info.wlan_inst_info[0].pipes_client_type[1] + = IPA_CLIENT_WLAN2_PROD; + ipa_lnx_agent_ctx.alloc_info.wlan_inst_info[0].tx_inst_client_type[0] + = IPA_CLIENT_WLAN2_CONS; + ipa_lnx_agent_ctx.alloc_info.wlan_inst_info[0].rx_inst_client_type[0] + = IPA_CLIENT_WLAN2_PROD; + if(ipa_wdi_is_tx1_used() == 1) { + ipa_lnx_agent_ctx.alloc_info.wlan_inst_info[0].num_tx_instances++; + ipa_lnx_agent_ctx.alloc_info.wlan_inst_info[0].num_pipes++; + ipa_lnx_agent_ctx.alloc_info.wlan_inst_info[ + 0].pipes_client_type[2] = IPA_CLIENT_WLAN2_CONS1; + ipa_lnx_agent_ctx.alloc_info.wlan_inst_info[ + 0].tx_inst_client_type[1] = IPA_CLIENT_WLAN2_CONS1; + } + } + } + + /* For ETH instance */ + if (ipa_lnx_agent_ctx.log_type_mask & TLPD_IPA_LOG_TYPE_ETH_STATS) { + ipa_lnx_agent_ctx.alloc_info.num_eth_instances = 0; + for (i = 0; i < IPA_ETH_INST_ID_MAX; i++) { + ipa_lnx_agent_ctx.alloc_info.eth_inst_info[i].num_pipes = 0; + ipa_lnx_agent_ctx.alloc_info.eth_inst_info[i].num_pipes = 0; + ipa_lnx_agent_ctx.alloc_info.eth_inst_info[i].num_tx_instances + = 0; + ipa_lnx_agent_ctx.alloc_info.eth_inst_info[i].num_rx_instances + = 0; + k = 0; + for (j = 0; (j < IPA_ETH_CLIENT_MAX) && + (k < TLPD_NUM_MAX_TX_INSTANCES); j++) { + if (ipa_eth_client_exist(j, i) && + (ipa_lnx_agent_ctx.alloc_info.num_eth_instances < 2)) { + eth_instance_id = ipa_lnx_agent_ctx.alloc_info.num_eth_instances; + ipa_lnx_agent_ctx.alloc_info.eth_inst_info[eth_instance_id].num_pipes = + ipa_lnx_agent_ctx.alloc_info.eth_inst_info[ + eth_instance_id].num_pipes + 2; + ipa_lnx_agent_ctx.alloc_info.eth_inst_info[ + eth_instance_id].num_tx_instances++; + ipa_lnx_agent_ctx.alloc_info.eth_inst_info[ + eth_instance_id].num_rx_instances++; + ipa_lnx_agent_ctx.alloc_info.eth_inst_info[ + eth_instance_id].tx_inst_client_type[k] = j; + ipa_client_type = + ipa_eth_get_ipa_client_type_from_eth_type( + j, IPA_ETH_PIPE_DIR_TX); + if (ipa_client_type >= IPA_CLIENT_MAX) + IPA_STATS_ERR("Eth tx client type not found"); +#if IPA_ETH_API_VER >= 2 + /* Overwrite client type if it is NTN3 and 2nd instance */ + if ((j == IPA_ETH_CLIENT_NTN3) && (i == 1)) + ipa_client_type = IPA_CLIENT_ETHERNET2_CONS; +#endif + ipa_lnx_agent_ctx.alloc_info.eth_inst_info[ + eth_instance_id].pipes_client_type[k*2] = ipa_client_type; + ipa_client_type = + ipa_eth_get_ipa_client_type_from_eth_type( + j, IPA_ETH_PIPE_DIR_RX); + if (ipa_client_type >= IPA_CLIENT_MAX) + IPA_STATS_ERR("Eth rx client type not found"); +#if IPA_ETH_API_VER >= 2 + /* Overwrite client type if it is NTN3 and 2nd instance */ + if ((j == IPA_ETH_CLIENT_NTN3) && (i == 1)) + ipa_client_type = IPA_CLIENT_ETHERNET2_PROD; +#endif + ipa_lnx_agent_ctx.alloc_info.eth_inst_info[ + eth_instance_id].pipes_client_type[(k*2) + 1] = ipa_client_type; + ipa_lnx_agent_ctx.alloc_info.num_eth_instances++; + k++; + } + } + } + } + + /* For USB instance */ + if (ipa_lnx_agent_ctx.log_type_mask & TLPD_IPA_LOG_TYPE_USB_STATS) { + ipa_lnx_agent_ctx.alloc_info.num_usb_instances = 0; + index = 0; + for (i = 0; (i < IPA_USB_MAX_TETH_PROT_SIZE) && + (index < TLPD_NUM_MAX_INSTANCES); i++) { + if(ipa_usb_is_teth_prot_connected(i)) { + if (index == TLPD_NUM_MAX_INSTANCES) { + IPA_STATS_ERR("USB alloc info max size reached\n"); + break; + } + ipa_lnx_agent_ctx.usb_teth_prot[index] = i; + if (ipa_lnx_agent_ctx.usb_teth_prot[index] == + IPA_USB_RMNET_CV2X) { + ipa_lnx_agent_ctx.alloc_info.usb_inst_info[ + index].num_pipes = 2; + ipa_lnx_agent_ctx.alloc_info.usb_inst_info[ + index].num_tx_instances = 1; + ipa_lnx_agent_ctx.alloc_info.usb_inst_info[ + index].num_rx_instances = 1; + ipa_lnx_agent_ctx.alloc_info.usb_inst_info[ + index].pipes_client_type[0] = IPA_CLIENT_USB2_PROD; + ipa_lnx_agent_ctx.alloc_info.usb_inst_info[ + index].pipes_client_type[1] = IPA_CLIENT_USB2_CONS; + ipa_lnx_agent_ctx.alloc_info.usb_inst_info[ + index].tx_inst_client_type[0] = IPA_CLIENT_USB2_CONS; + ipa_lnx_agent_ctx.alloc_info.usb_inst_info[ + index].rx_inst_client_type[0] = IPA_CLIENT_USB2_PROD; + } else if (ipa_lnx_agent_ctx.usb_teth_prot[index] == + IPA_USB_DIAG) { + /* USB DIAG stats not supported, can be added in future */ + continue; + } else { + ipa_lnx_agent_ctx.alloc_info.usb_inst_info[ + index].num_pipes = 2; + ipa_lnx_agent_ctx.alloc_info.usb_inst_info[ + index].num_tx_instances = 1; + ipa_lnx_agent_ctx.alloc_info.usb_inst_info[ + index].num_rx_instances = 1; + ipa_lnx_agent_ctx.alloc_info.usb_inst_info[ + index].pipes_client_type[0] = IPA_CLIENT_USB_PROD; + ipa_lnx_agent_ctx.alloc_info.usb_inst_info[ + index].pipes_client_type[1] = IPA_CLIENT_USB_CONS; + ipa_lnx_agent_ctx.alloc_info.usb_inst_info[ + index].tx_inst_client_type[0] = IPA_CLIENT_USB_CONS; + ipa_lnx_agent_ctx.alloc_info.usb_inst_info[ + index].rx_inst_client_type[0] = IPA_CLIENT_USB_PROD; + } + ipa_lnx_agent_ctx.alloc_info.num_usb_instances++; + index++; + } + } + } + + /* For MHIP instance */ + if (ipa_lnx_agent_ctx.log_type_mask & TLPD_IPA_LOG_TYPE_MHIP_STATS) { +#if IS_ENABLED(CONFIG_IPA3_MHI_PRIME_MANAGER) + if (!ipa3_ctx->mhip_ctx.dbg_stats.uc_dbg_stats_mmio) { + ipa_lnx_agent_ctx.alloc_info.num_mhip_instances = 0; + } else { + if (ipa_usb_is_teth_prot_connected(IPA_USB_RNDIS)) + ipa_lnx_agent_ctx.usb_teth_prot[0] = IPA_USB_RNDIS; + else if(ipa_usb_is_teth_prot_connected(IPA_USB_RMNET)) + ipa_lnx_agent_ctx.usb_teth_prot[0] = IPA_USB_RMNET; + else ipa_lnx_agent_ctx.usb_teth_prot[0] = IPA_USB_MAX_TETH_PROT_SIZE; + ipa_lnx_agent_ctx.alloc_info.num_mhip_instances = 1; + ipa_lnx_agent_ctx.alloc_info.mhip_inst_info[0].num_pipes = 4; + ipa_lnx_agent_ctx.alloc_info.mhip_inst_info[0].num_tx_instances = 2; + ipa_lnx_agent_ctx.alloc_info.mhip_inst_info[0].num_rx_instances = 2; + ipa_lnx_agent_ctx.alloc_info.mhip_inst_info[0].pipes_client_type[0] = + IPA_CLIENT_MHI_PRIME_TETH_CONS; + ipa_lnx_agent_ctx.alloc_info.mhip_inst_info[0].pipes_client_type[1] = + IPA_CLIENT_MHI_PRIME_TETH_PROD; + ipa_lnx_agent_ctx.alloc_info.mhip_inst_info[0].pipes_client_type[2] = + IPA_CLIENT_MHI_PRIME_RMNET_CONS; + ipa_lnx_agent_ctx.alloc_info.mhip_inst_info[0].pipes_client_type[3] = + IPA_CLIENT_MHI_PRIME_RMNET_PROD; + ipa_lnx_agent_ctx.alloc_info.mhip_inst_info[0].tx_inst_client_type[0] + = IPA_CLIENT_MHI_PRIME_TETH_CONS; + ipa_lnx_agent_ctx.alloc_info.mhip_inst_info[0].tx_inst_client_type[1] + = IPA_CLIENT_MHI_PRIME_RMNET_CONS; + ipa_lnx_agent_ctx.alloc_info.mhip_inst_info[0].rx_inst_client_type[0] + = IPA_CLIENT_MHI_PRIME_TETH_PROD; + ipa_lnx_agent_ctx.alloc_info.mhip_inst_info[0].rx_inst_client_type[1] + = IPA_CLIENT_MHI_PRIME_RMNET_PROD; + } +#else + /* MHI Prime is not enabled */ + ipa_lnx_agent_ctx.alloc_info.num_mhip_instances = 0; +#endif + } + + /* For Page recycling stats for default, coal and Low lat pipes */ + if (ipa_lnx_agent_ctx.log_type_mask & TLPD_IPA_LOG_TYPE_RECYCLE_STATS) + ipa_lnx_agent_ctx.alloc_info.num_page_rec_interval = + IPA_LNX_PIPE_PAGE_RECYCLING_INTERVAL_COUNT; + + if(copy_to_user((u8 *)arg, + &ipa_lnx_agent_ctx, + sizeof(struct ipa_lnx_stats_tlpd_ctx))) { + IPA_STATS_ERR("copy to user failed"); + return -EFAULT; + } + return 0; +} + +static long ipa_lnx_stats_ioctl(struct file *filp, + unsigned int cmd, + unsigned long arg) +{ + int retval = IPA_LNX_STATS_SUCCESS; + struct ipa_lnx_consolidated_stats *consolidated_stats; + + if (_IOC_TYPE(cmd) != IPA_LNX_STATS_IOC_MAGIC) { + IPA_STATS_ERR("IOC type mismatch %d\n", cmd); + return -ENOTTY; + } + + if(!ipa3_ctx) { + IPA_STATS_ERR("IPA driver is not up, rejecting the ioctl\n"); + return -EPERM; + } + + mutex_lock(&ipa_lnx_ctx_mutex); + switch (cmd) { + case IPA_LNX_IOC_GET_ALLOC_INFO: + retval = ipa_stats_get_alloc_info(arg); + if (retval) + IPA_STATS_ERR("ipa get alloc info fail"); + break; + case IPA_LNX_IOC_GET_GENERIC_STATS: + retval = ipa_get_generic_stats(arg); + if (retval) + IPA_STATS_ERR("ipa get generic stats fail"); + break; + case IPA_LNX_IOC_GET_CLOCK_STATS: + retval = ipa_get_clock_stats(arg); + if (retval) + IPA_STATS_ERR("ipa get clock stats fail"); + break; + case IPA_LNX_IOC_GET_WLAN_INST_STATS: + retval = ipa_get_wlan_inst_stats(arg); + if (retval) + IPA_STATS_ERR("ipa get wlan inst stats fail"); + break; + case IPA_LNX_IOC_GET_ETH_INST_STATS: + retval = ipa_get_eth_inst_stats(arg); + if (retval) + IPA_STATS_ERR("ipa get eth inst stats fail"); + break; + case IPA_LNX_IOC_GET_USB_INST_STATS: + retval = ipa_get_usb_inst_stats(arg); + if (retval) + IPA_STATS_ERR("ipa get usb inst stats fail"); + break; + case IPA_LNX_IOC_GET_MHIP_INST_STATS: +#if IS_ENABLED(CONFIG_IPA3_MHI_PRIME_MANAGER) + retval = ipa_get_mhip_inst_stats(arg); + if (retval) + IPA_STATS_ERR("ipa get mhip inst stats fail"); +#else + retval = IPA_LNX_STATS_SUCCESS; +#endif + break; + case IPA_LNX_IOC_GET_CONSOLIDATED_STATS: + consolidated_stats = (struct ipa_lnx_consolidated_stats *) memdup_user(( + const void __user *)arg, sizeof(struct ipa_lnx_consolidated_stats)); + if (IS_ERR(consolidated_stats)) { + IPA_STATS_ERR("copy from user failed"); + mutex_unlock(&ipa_lnx_ctx_mutex); + return -ENOMEM; + } + + if (consolidated_stats->log_type_mask & TLPD_IPA_LOG_TYPE_GENERIC_STATS) { + retval = ipa_get_generic_stats((unsigned long) consolidated_stats->generic_stats); + if (retval) { + IPA_STATS_ERR("ipa get generic stats fail"); + break; + } + } + if (consolidated_stats->log_type_mask & TLPD_IPA_LOG_TYPE_CLOCK_STATS) { + retval = ipa_get_clock_stats((unsigned long) consolidated_stats->clock_stats); + if (retval) { + IPA_STATS_ERR("ipa get clock stats fail"); + break; + } + } + if (consolidated_stats->log_type_mask & TLPD_IPA_LOG_TYPE_WLAN_STATS) { + retval = ipa_get_wlan_inst_stats((unsigned long) consolidated_stats->wlan_stats); + if (retval) { + IPA_STATS_ERR("ipa get wlan inst stats fail"); + break; + } + } + if (consolidated_stats->log_type_mask & TLPD_IPA_LOG_TYPE_ETH_STATS) { + retval = ipa_get_eth_inst_stats((unsigned long) consolidated_stats->eth_stats); + if (retval) { + IPA_STATS_ERR("ipa get eth inst stats fail"); + break; + } + } + if (consolidated_stats->log_type_mask & TLPD_IPA_LOG_TYPE_USB_STATS) { + retval = ipa_get_usb_inst_stats((unsigned long) consolidated_stats->usb_stats); + if (retval) { + IPA_STATS_ERR("ipa get usb inst stats fail"); + break; + } + } + if (consolidated_stats->log_type_mask & TLPD_IPA_LOG_TYPE_MHIP_STATS) { +#if IS_ENABLED(CONFIG_IPA3_MHI_PRIME_MANAGER) + retval = ipa_get_mhip_inst_stats((unsigned long) consolidated_stats->mhip_stats); + if (retval) { + IPA_STATS_ERR("ipa get mhip inst stats fail"); + break; + } +#endif + } + if (consolidated_stats->log_type_mask & TLPD_IPA_LOG_TYPE_RECYCLE_STATS) { + retval = ipa_get_page_recycle_stats((unsigned long) consolidated_stats->recycle_stats); + if (retval) { + IPA_STATS_ERR("ipa get page recycle stats fail\n"); + break; + } + } + break; + default: + retval = -ENOTTY; + } + mutex_unlock(&ipa_lnx_ctx_mutex); + return retval; +} + +const struct file_operations ipa_stats_fops = { + .owner = THIS_MODULE, + .open = ipa_stats_ioctl_open, + .read = NULL, + .unlocked_ioctl = ipa_lnx_stats_ioctl, +}; + +static int ipa_tlpd_stats_ioctl_init(void) +{ + unsigned int ipa_lnx_stats_ioctl_major = 0; + int ret; + struct device *dev; + + device = MKDEV(ipa_lnx_stats_ioctl_major, 0); + + ret = alloc_chrdev_region(&device, 0, dev_num, DRIVER_NAME); + if (ret) { + IPA_STATS_ERR(":device_alloc err.\n"); + goto dev_alloc_err; + } + ipa_lnx_stats_ioctl_major = MAJOR(device); + + class = class_create(THIS_MODULE, DRIVER_NAME); + if (IS_ERR(class)) { + IPA_STATS_ERR(":class_create err.\n"); + goto class_err; + } + + dev = device_create(class, NULL, device, + NULL, DRIVER_NAME); + if (IS_ERR(dev)) { + IPA_STATS_ERR(":device_create err.\n"); + goto device_err; + } + + cdev_init(&ipa_lnx_stats_ioctl_cdev, &ipa_stats_fops); + ret = cdev_add(&ipa_lnx_stats_ioctl_cdev, device, dev_num); + if (ret) { + IPA_STATS_ERR(":cdev_add err.\n"); + goto cdev_add_err; + } + + IPA_STATS_ERR("IPA %s major(%d) initial ok :>>>>\n", + DRIVER_NAME, ipa_lnx_stats_ioctl_major); + return 0; + +cdev_add_err: + device_destroy(class, device); +device_err: + class_destroy(class); +class_err: + unregister_chrdev_region(device, dev_num); +dev_alloc_err: + return -ENODEV; +} + +int ipa_tlpd_stats_init(void) +{ + int ret; + + ret = ipa_tlpd_stats_ioctl_init(); + if(ret) { + IPA_STATS_ERR("IPA_LNX_STATS_IOCTL init failure = %d\n", ret); + return -1; + } + memset(&poll_pack_and_cred_info, 0, sizeof(poll_pack_and_cred_info)); + IPA_STATS_ERR("IPA_LNX_STATS_IOCTL init success\n"); + + return 0; +} + +/* Non periodic/Event based stats update */ +int ipa3_update_usb_per_stats(enum ipa_per_stats_type_e stats_type, uint32_t data) { + union ipa_peripheral_stats *peripheral_stats = + (union ipa_peripheral_stats *) ipa3_ctx->per_stats_smem_va; + if (ipa3_ctx->platform_type == IPA_PLAT_TYPE_MDM) { + peripheral_stats->mdm.usb_enum_value = IPA_PER_USB_ENUM_TYPE_INVALID; + peripheral_stats->mdm.usb_prot_enum_value = IPA_PER_USB_PROT_TYPE_INVALID; + peripheral_stats->mdm.usb_max_speed_val = 0; + peripheral_stats->mdm.usb_pipo_val = 0; + } else if (ipa3_ctx->platform_type == IPA_PLAT_TYPE_MSM) { + peripheral_stats->msm.usb_enum_value = IPA_PER_USB_ENUM_TYPE_INVALID; + peripheral_stats->msm.usb_prot_enum_value = IPA_PER_USB_PROT_TYPE_INVALID; + peripheral_stats->msm.usb_max_speed_val = 0; + peripheral_stats->msm.usb_pipo_val = 0; + } + return 0; +} + +int ipa3_update_pcie_per_stats(enum ipa_per_stats_type_e stats_type, uint32_t data) { + union ipa_peripheral_stats *peripheral_stats = + (union ipa_peripheral_stats *) ipa3_ctx->per_stats_smem_va; + if (ipa3_ctx->platform_type == IPA_PLAT_TYPE_MDM) { + peripheral_stats->mdm.pcie_gen_type_val = 0; + peripheral_stats->mdm.pcie_width_type_val = PCIE_LINK_WIDTH_DEF; + peripheral_stats->mdm.pcie_max_speed_val = 0; + peripheral_stats->mdm.pcie_num_lpm_trans_d3 = 0; + peripheral_stats->mdm.pcie_num_lpm_trans_m1 = 0; + peripheral_stats->mdm.pcie_num_lpm_trans_m2 = 0; + peripheral_stats->mdm.pcie_num_lpm_trans_m0 = 0; + } + return 0; +} + +int ipa3_update_wifi_per_stats(enum ipa_per_stats_type_e stats_type, uint32_t data) { + union ipa_peripheral_stats *peripheral_stats = + (union ipa_peripheral_stats *) ipa3_ctx->per_stats_smem_va; + if (ipa3_ctx->platform_type == IPA_PLAT_TYPE_MDM) { + peripheral_stats->mdm.wifi_enum_type_val = IPA_PER_WIFI_ENUM_TYPE_INVALID; + peripheral_stats->mdm.wifi_max_speed_val = 0; + peripheral_stats->mdm.wifi_dual_band_enabled_val = 0; + } else if (ipa3_ctx->platform_type == IPA_PLAT_TYPE_MSM) { + peripheral_stats->msm.wifi_enum_type_val = IPA_PER_WIFI_ENUM_TYPE_INVALID; + peripheral_stats->msm.wifi_max_speed_val = 0; + peripheral_stats->msm.wifi_dual_band_enabled_val = 0; + } + return 0; +} + +int ipa3_update_eth_per_stats(enum ipa_per_stats_type_e stats_type, uint32_t data) { + union ipa_peripheral_stats *peripheral_stats = + (union ipa_peripheral_stats *) ipa3_ctx->per_stats_smem_va; + if (ipa3_ctx->platform_type == IPA_PLAT_TYPE_MDM) { + peripheral_stats->mdm.eth_client_val = 0; + peripheral_stats->mdm.eth_max_speed_val = 0; + } + return 0; +} + +int ipa3_update_apps_per_stats(enum ipa_per_stats_type_e stats_type, uint32_t data) { + union ipa_peripheral_stats *peripheral_stats = + (union ipa_peripheral_stats *) ipa3_ctx->per_stats_smem_va; + if (ipa3_ctx->platform_type == IPA_PLAT_TYPE_MDM) { + peripheral_stats->mdm.periph_val = 0; + peripheral_stats->mdm.periph_wwan_val = 0; + peripheral_stats->mdm.periph_type_val = IPA_PER_TYPE_BITMASK_NONE; + } else if (ipa3_ctx->platform_type == IPA_PLAT_TYPE_MSM) { + peripheral_stats->msm.periph_val = 0; + peripheral_stats->msm.periph_wwan_val = 0; + peripheral_stats->msm.periph_type_val = IPA_PER_TYPE_BITMASK_NONE; + } + return 0; +} + +/* Periodic stats update */ +int ipa3_update_client_holb_per_stats(enum ipa_per_stats_type_e stats_type, uint32_t data) { + union ipa_peripheral_stats *peripheral_stats = + (union ipa_peripheral_stats *) ipa3_ctx->per_stats_smem_va; + if (ipa3_ctx->platform_type == IPA_PLAT_TYPE_MDM) { + peripheral_stats->mdm.wifi_holb_uc_stats_num_periph_bad = 0; + peripheral_stats->mdm.wifi_holb_uc_stats_num_periph_recovered = 0; + + peripheral_stats->mdm.eth_holb_uc_stats_num_periph_bad = 0; + peripheral_stats->mdm.eth_holb_uc_stats_num_periph_recovered = 0; + + peripheral_stats->mdm.usb_holb_uc_stats_num_periph_bad = 0; + peripheral_stats->mdm.usb_holb_uc_stats_num_periph_recovered = 0; + } else if (ipa3_ctx->platform_type == IPA_PLAT_TYPE_MSM) { + peripheral_stats->msm.wifi_holb_uc_stats_num_periph_bad = 0; + peripheral_stats->msm.wifi_holb_uc_stats_num_periph_recovered = 0; + + peripheral_stats->msm.usb_holb_uc_stats_num_periph_bad = 0; + peripheral_stats->msm.usb_holb_uc_stats_num_periph_recovered = 0; + } + return 0; +} + +int ipa3_update_dma_per_stats(enum ipa_per_stats_type_e stats_type, uint32_t data) { + union ipa_peripheral_stats *peripheral_stats = + (union ipa_peripheral_stats *) ipa3_ctx->per_stats_smem_va; + peripheral_stats->mdm.ipa_dma_bytes_val = 0; + return 0; +} + +int ipa3_peripheral_stats_init(union ipa_peripheral_stats *peripheral_stats) { + + if (ipa3_ctx->platform_type == IPA_PLAT_TYPE_MDM) { + peripheral_stats->mdm.num_entries = IPA_PERIPHERAL_STATS_MDM_NUM_ENTRIES; + + /* TLV for number of peripherals connected to APROC */ + /* value = IPA_PER_STATS_TYPE_NUM_PERS */ + peripheral_stats->mdm.periph_id = IPA_PER_STATS_TYPE_NUM_PERS; + peripheral_stats->mdm.periph_len = 4; + peripheral_stats->mdm.periph_val = 0; + + /* TLV for number of periphers from/to traffic flowing from modem */ + /* value = IPA_PER_STATS_TYPE_NUM_PERS_WWAN */ + peripheral_stats->mdm.periph_wwan_id = IPA_PER_STATS_TYPE_NUM_PERS_WWAN; + peripheral_stats->mdm.periph_wwan_len = 4; + peripheral_stats->mdm.periph_wwan_val = 0; + + /* TLV for bitmask for active/connected peripherals */ + /* value = IPA_PER_STATS_TYPE_ACT_PER_TYPE */ + peripheral_stats->mdm.periph_type_id = IPA_PER_STATS_TYPE_ACT_PER_TYPE; + peripheral_stats->mdm.periph_type_len = 4; + peripheral_stats->mdm.periph_type_val = IPA_PER_TYPE_BITMASK_NONE; + + /* TLV for Current gen info if PCIe interconnect is valid */ + /* value = IPA_PER_STATS_TYPE_PCIE_GEN */ + peripheral_stats->mdm.pcie_gen_type_id = IPA_PER_STATS_TYPE_PCIE_GEN; + peripheral_stats->mdm.pcie_gen_type_len = 4; + peripheral_stats->mdm.pcie_gen_type_val = 0; + + /* TLV for Current gen info if PCIe interconnect is valid */ + /* value = IPA_PER_STATS_TYPE_PCIE_GEN */ + peripheral_stats->mdm.pcie_width_type_id = IPA_PER_STATS_TYPE_PCIE_WIDTH; + peripheral_stats->mdm.pcie_width_type_len = 4; + peripheral_stats->mdm.pcie_width_type_val = PCIE_LINK_WIDTH_DEF; + + /* TLV for Max PCIe speed in current gen in Mbps */ + /* value = IPA_PER_STATS_TYPE_PCIE_MAX_SPEED */ + peripheral_stats->mdm.pcie_max_speed_id = IPA_PER_STATS_TYPE_PCIE_MAX_SPEED; + peripheral_stats->mdm.pcie_max_speed_len = 4; + peripheral_stats->mdm.pcie_max_speed_val = 0; + + /* TLV for number PCIe LPM transitions */ + /* value = IPA_PER_STATS_TYPE_PCIE_NUM_LPM */ + peripheral_stats->mdm.pcie_num_lpm_trans_id = IPA_PER_STATS_TYPE_PCIE_NUM_LPM; + peripheral_stats->mdm.pcie_num_lpm_trans_len = 8; + peripheral_stats->mdm.pcie_num_lpm_trans_d3 = 0; + peripheral_stats->mdm.pcie_num_lpm_trans_m1 = 0; + peripheral_stats->mdm.pcie_num_lpm_trans_m2 = 0; + peripheral_stats->mdm.pcie_num_lpm_trans_m0 = 0; + + /* TLV for USB enumeration type */ + /* value = IPA_PER_STATS_TYPE_USB_TYPE */ + peripheral_stats->mdm.usb_enum_id = IPA_PER_STATS_TYPE_USB_TYPE; + peripheral_stats->mdm.usb_enum_len = 4; + peripheral_stats->mdm.usb_enum_value = IPA_PER_USB_ENUM_TYPE_INVALID; + + /* TLV for Current USB protocol enumeration if active */ + /* value = IPA_PER_STATS_TYPE_USB_PROT */ + peripheral_stats->mdm.usb_prot_enum_id = IPA_PER_STATS_TYPE_USB_PROT; + peripheral_stats->mdm.usb_prot_enum_len = 4; + peripheral_stats->mdm.usb_prot_enum_value = IPA_PER_USB_PROT_TYPE_INVALID; + + /* TLV for Max USB speed in current gen in Mbps */ + /* value = IPA_PER_STATS_TYPE_USB_MAX_SPEED */ + peripheral_stats->mdm.usb_max_speed_id = IPA_PER_STATS_TYPE_USB_MAX_SPEED; + peripheral_stats->mdm.usb_max_speed_len = 4; + peripheral_stats->mdm.usb_max_speed_val = 0; + + /* TLV for Total number of USB plug in/outs, count is only plug ins */ + /* value = IPA_PER_STATS_TYPE_USB_PIPO */ + peripheral_stats->mdm.usb_pipo_id = IPA_PER_STATS_TYPE_USB_PIPO; + peripheral_stats->mdm.usb_pipo_len = 4; + peripheral_stats->mdm.usb_pipo_val = 0; + + /* TLV for Wifi enumeration type*/ + /* value = IPA_PER_STATS_TYPE_WIFI_ENUM_TYPE */ + peripheral_stats->mdm.wifi_enum_type_id = IPA_PER_STATS_TYPE_WIFI_ENUM_TYPE; + peripheral_stats->mdm.wifi_enum_type_len = 4; + peripheral_stats->mdm.wifi_enum_type_val = IPA_PER_WIFI_ENUM_TYPE_INVALID; + + /* TLV for Theoritical Max WLAN speed in current gen in Mbps (pipe for 5GHz in case of dual band) */ + /* value = IPA_PER_STATS_TYPE_WIFI_MAX_SPEED */ + peripheral_stats->mdm.wifi_max_speed_id = IPA_PER_STATS_TYPE_WIFI_MAX_SPEED; + peripheral_stats->mdm.wifi_max_speed_len = 4; + peripheral_stats->mdm.wifi_max_speed_val = 0; + + /* TLV for Theoretical Max WLAN speed on the 2.4GHz pipe, value of 0 means disabled */ + /* value = IPA_PER_STATS_TYPE_WIFI_DUAL_BAND_EN */ + peripheral_stats->mdm.wifi_dual_band_enabled_id = IPA_PER_STATS_TYPE_WIFI_DUAL_BAND_EN; + peripheral_stats->mdm.wifi_dual_band_enabled_len = 4; + peripheral_stats->mdm.wifi_dual_band_enabled_val = 0; + + /* TLV for the type of ethernet client - Realtek/AQC */ + /* value = IPA_PER_STATS_TYPE_ETH_CLIENT */ + peripheral_stats->mdm.eth_client_id = IPA_PER_STATS_TYPE_ETH_CLIENT; + peripheral_stats->mdm.eth_client_len = 4; + peripheral_stats->mdm.eth_client_val = 0; + + /* TLV for Max Eth link speed */ + /* value = IPA_PER_STATS_TYPE_ETH_MAX_SPEED */ + peripheral_stats->mdm.eth_max_speed_id = IPA_PER_STATS_TYPE_ETH_MAX_SPEED; + peripheral_stats->mdm.eth_max_speed_len = 4; + peripheral_stats->mdm.eth_max_speed_val = 0; + + /* TLV for Total number of bytes txferred through IPA DMA channels over PCIe */ + /* For cases where GSI used for QDSS direct DMA, need to extract bytes stat from GSI FW */ + /* value = IPA_PER_STATS_TYPE_IPA_DMA_BYTES */ + peripheral_stats->mdm.ipa_dma_bytes_id = IPA_PER_STATS_TYPE_IPA_DMA_BYTES; + peripheral_stats->mdm.ipa_dma_bytes_len = 4; + peripheral_stats->mdm.ipa_dma_bytes_val = 0; + + /* TLV for number of wifi peripherals connected to APROC */ + /* value = IPA_PER_STATS_TYPE_WIFI_HOLB_UC */ + peripheral_stats->mdm.wifi_holb_uc_stats_id = IPA_PER_STATS_TYPE_WIFI_HOLB_UC; + peripheral_stats->mdm.wifi_holb_uc_stats_len = 4; + peripheral_stats->mdm.wifi_holb_uc_stats_num_periph_bad = 0; + peripheral_stats->mdm.wifi_holb_uc_stats_num_periph_recovered = 0; + + /* TLV for number of eth peripherals connected to APROC */ + /* value = IPA_PER_STATS_TYPE_ETH_HOLB_UC */ + peripheral_stats->mdm.eth_holb_uc_stats_id = IPA_PER_STATS_TYPE_ETH_HOLB_UC; + peripheral_stats->mdm.eth_holb_uc_stats_len = 4; + peripheral_stats->mdm.eth_holb_uc_stats_num_periph_bad = 0; + peripheral_stats->mdm.eth_holb_uc_stats_num_periph_recovered = 0; + + /* TLV for number of usb peripherals connected to APROC */ + /* value = IPA_PER_STATS_TYPE_USB_HOLB_UC */ + peripheral_stats->mdm.usb_holb_uc_stats_id = IPA_PER_STATS_TYPE_USB_HOLB_UC; + peripheral_stats->mdm.usb_holb_uc_stats_len = 4; + peripheral_stats->mdm.usb_holb_uc_stats_num_periph_bad = 0; + peripheral_stats->mdm.usb_holb_uc_stats_num_periph_recovered = 0; + + } else if (ipa3_ctx->platform_type == IPA_PLAT_TYPE_MSM) { + peripheral_stats->msm.num_entries = IPA_PERIPHERAL_STATS_MSM_NUM_ENTRIES; + + /* TLV for number of peripherals connected to APROC */ + /* value = IPA_PER_STATS_TYPE_NUM_PERS */ + peripheral_stats->msm.periph_id = IPA_PER_STATS_TYPE_NUM_PERS; + peripheral_stats->msm.periph_len = 4; + peripheral_stats->msm.periph_val = 0; + + /* TLV for number of periphers from/to traffic flowing from modem */ + /* value = IPA_PER_STATS_TYPE_NUM_PERS_WWAN */ + peripheral_stats->msm.periph_wwan_id = IPA_PER_STATS_TYPE_NUM_PERS_WWAN; + peripheral_stats->msm.periph_wwan_len = 4; + peripheral_stats->msm.periph_wwan_val = 0; + + /* TLV for bitmask for active/connected peripherals */ + /* value = IPA_PER_STATS_TYPE_ACT_PER_TYPE */ + peripheral_stats->msm.periph_type_id = IPA_PER_STATS_TYPE_ACT_PER_TYPE; + peripheral_stats->msm.periph_type_len = 4; + peripheral_stats->msm.periph_type_val = IPA_PER_TYPE_BITMASK_NONE; + + /* TLV for USB enumeration type */ + /* value = IPA_PER_STATS_TYPE_USB_TYPE */ + peripheral_stats->msm.usb_enum_id = IPA_PER_STATS_TYPE_USB_TYPE; + peripheral_stats->msm.usb_enum_len = 4; + peripheral_stats->msm.usb_enum_value = IPA_PER_USB_ENUM_TYPE_INVALID; + + /* TLV for Current USB protocol enumeration if active */ + /* value = IPA_PER_STATS_TYPE_USB_PROT */ + peripheral_stats->msm.usb_prot_enum_id = IPA_PER_STATS_TYPE_USB_PROT; + peripheral_stats->msm.usb_prot_enum_len = 4; + peripheral_stats->msm.usb_prot_enum_value = IPA_PER_USB_PROT_TYPE_INVALID; + + /* TLV for Max USB speed in current gen in Mbps */ + /* value = IPA_PER_STATS_TYPE_USB_MAX_SPEED */ + peripheral_stats->msm.usb_max_speed_id = IPA_PER_STATS_TYPE_USB_MAX_SPEED; + peripheral_stats->msm.usb_max_speed_len = 4; + peripheral_stats->msm.usb_max_speed_val = 0; + + /* TLV for Total number of USB plug in/outs, count is only plug ins */ + /* value = IPA_PER_STATS_TYPE_USB_PIPO */ + peripheral_stats->msm.usb_pipo_id = IPA_PER_STATS_TYPE_USB_PIPO; + peripheral_stats->msm.usb_pipo_len = 4; + peripheral_stats->msm.usb_pipo_val = 0; + + /* TLV for Wifi enumeration type*/ + /* value = IPA_PER_STATS_TYPE_WIFI_ENUM_TYPE */ + peripheral_stats->msm.wifi_enum_type_id = IPA_PER_STATS_TYPE_WIFI_ENUM_TYPE; + peripheral_stats->msm.wifi_enum_type_len = 4; + peripheral_stats->msm.wifi_enum_type_val = IPA_PER_WIFI_ENUM_TYPE_INVALID; + + /* TLV for Theoritical Max WLAN speed in current gen in Mbps (pipe for 5GHz in case of dual band) */ + /* value = IPA_PER_STATS_TYPE_WIFI_MAX_SPEED */ + peripheral_stats->msm.wifi_max_speed_id = IPA_PER_STATS_TYPE_WIFI_MAX_SPEED; + peripheral_stats->msm.wifi_max_speed_len = 4; + peripheral_stats->msm.wifi_max_speed_val = 0; + + /* TLV for Theoretical Max WLAN speed on the 2.4GHz pipe, value of 0 means disabled */ + /* value = IPA_PER_STATS_TYPE_WIFI_DUAL_BAND_EN */ + peripheral_stats->msm.wifi_dual_band_enabled_id = IPA_PER_STATS_TYPE_WIFI_DUAL_BAND_EN; + peripheral_stats->msm.wifi_dual_band_enabled_len = 4; + peripheral_stats->msm.wifi_dual_band_enabled_val = 0; + + /* TLV for number of wifi peripherals connected to APROC */ + /* value = IPA_PER_STATS_TYPE_WIFI_HOLB_UC */ + peripheral_stats->msm.wifi_holb_uc_stats_id = IPA_PER_STATS_TYPE_WIFI_HOLB_UC; + peripheral_stats->msm.wifi_holb_uc_stats_len = 4; + peripheral_stats->msm.wifi_holb_uc_stats_num_periph_bad = 0; + peripheral_stats->msm.wifi_holb_uc_stats_num_periph_recovered = 0; + + /* TLV for number of usb peripherals connected to APROC */ + /* value = IPA_PER_STATS_TYPE_USB_HOLB_UC */ + peripheral_stats->msm.usb_holb_uc_stats_id = IPA_PER_STATS_TYPE_USB_HOLB_UC; + peripheral_stats->msm.usb_holb_uc_stats_len = 4; + peripheral_stats->msm.usb_holb_uc_stats_num_periph_bad = 0; + peripheral_stats->msm.usb_holb_uc_stats_num_periph_recovered = 0; + } + + return 0; +} diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_stats.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_stats.h new file mode 100644 index 0000000000..30b6105741 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_stats.h @@ -0,0 +1,641 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _IPA_LNX_STATS_I_H_ +#define _IPA_LNX_STATS_I_H_ + +/* This whole header file is a copy of ipa_lnx_agent.h */ + +/* + * unique magic number of the IPA_LNX_STATS interface + */ +#define IPA_LNX_STATS_IOC_MAGIC 0x72 + +#define IPA_LNX_IOC_GET_ALLOC_INFO _IOWR(IPA_LNX_STATS_IOC_MAGIC, \ + IPA_LNX_CMD_GET_ALLOC_INFO, \ + struct ipa_lnx_stats_tlpd_ctx) + +#define IPA_LNX_IOC_GET_GENERIC_STATS _IOWR(IPA_LNX_STATS_IOC_MAGIC, \ + IPA_LNX_CMD_GENERIC_STATS, \ + struct ipa_lnx_generic_stats) + +#define IPA_LNX_IOC_GET_CLOCK_STATS _IOWR(IPA_LNX_STATS_IOC_MAGIC, \ + IPA_LNX_CMD_CLOCK_STATS, \ + struct ipa_lnx_clock_stats) + +#define IPA_LNX_IOC_GET_WLAN_INST_STATS _IOWR(IPA_LNX_STATS_IOC_MAGIC, \ + IPA_LNX_CMD_WLAN_INST_STATS, \ + struct ipa_lnx_wlan_inst_stats) + +#define IPA_LNX_IOC_GET_ETH_INST_STATS _IOWR(IPA_LNX_STATS_IOC_MAGIC, \ + IPA_LNX_CMD_ETH_INST_STATS, \ + struct ipa_lnx_eth_inst_stats) + +#define IPA_LNX_IOC_GET_USB_INST_STATS _IOWR(IPA_LNX_STATS_IOC_MAGIC, \ + IPA_LNX_CMD_USB_INST_STATS, \ + struct ipa_lnx_usb_inst_stats) + +#define IPA_LNX_IOC_GET_MHIP_INST_STATS _IOWR(IPA_LNX_STATS_IOC_MAGIC, \ + IPA_LNX_CMD_MHIP_INST_STATS, \ + struct ipa_lnx_mhip_inst_stats) + +#define IPA_LNX_IOC_GET_CONSOLIDATED_STATS _IOWR(IPA_LNX_STATS_IOC_MAGIC, \ + IPA_LNX_CMD_CONSOLIDATED_STATS, \ + int) + +#define IPA_LNX_STATS_SUCCESS 0 +#define IPA_LNX_STATS_FAILURE -1 + +#define TLPD_NUM_MAX_PIPES 6 +#define TLPD_NUM_MAX_TX_INSTANCES 3 +#define TLPD_NUM_MAX_RX_INSTANCES 3 + +#define TLPD_NUM_MAX_INSTANCES 2 + +#define IPA_LNX_PIPE_PAGE_RECYCLING_INTERVAL_COUNT 5 +#define IPA_LNX_PIPE_PAGE_RECYCLING_INTERVAL_TIME 10 /* In milli second */ + +/** + * This is used to indicate which set of logs is enabled from IPA + * These bitmapped macros. + */ +#define TLPD_IPA_LOG_TYPE_GENERIC_STATS 0x00001 +#define TLPD_IPA_LOG_TYPE_CLOCK_STATS 0x00002 +#define TLPD_IPA_LOG_TYPE_WLAN_STATS 0x00004 +#define TLPD_IPA_LOG_TYPE_ETH_STATS 0x00008 +#define TLPD_IPA_LOG_TYPE_USB_STATS 0x00010 +#define TLPD_IPA_LOG_TYPE_MHIP_STATS 0x00020 +#define TLPD_IPA_LOG_TYPE_RECYCLE_STATS 0x00040 + + +/** + * Look up table for pm stats client names. + * New entry to be added when new client + * registers with pm + */ +struct pm_client_name_lookup { char *name; int idx_hdl;}; +static struct pm_client_name_lookup client_lookup_table[] = { + {"ODL", 1}, + {"IPA_CLIENT_APPS_LAN_CONS", 2}, + {"EMB MODEM", 3}, + {"TETH MODEM", 4}, + {"rmnet_ipa%d", 5}, + {"USB", 6}, + {"USB DPL", 7}, + {"MODEM (USB RMNET)", 8}, + {"IPA_CLIENT_APPS_WAN_CONS", 9} +}; + +#define NUM_PM_CLIENT_NAMES (sizeof(client_lookup_table)/sizeof(struct pm_client_name_lookup)) + +/** + * Every structure is associated with the underlying macro + * for it's length and that has to be updated every time there + * is structure modification.This is NOT the sizeof(struct) but + * it is addition of the specified type of variable included + * inside the structre. Also update the internal structure lengths + * in ipa_lnx_tlpd_stats.c to overcome backward and forward + * compatibility between userspace and driver structures. + */ +/* IPA Linux generic stats structures */ +struct pg_recycle_stats { + uint64_t coal_total_repl_buff; + uint64_t coal_temp_repl_buff; + uint64_t def_total_repl_buff; + uint64_t def_temp_repl_buff; +}; + +struct exception_stats { + uint32_t excptn_type_none; + uint32_t excptn_type_deaggr; + uint32_t excptn_type_iptype; + uint32_t excptn_type_pkt_len; + uint32_t excptn_type_pkt_thrshld; + uint32_t excptn_type_frag_rule_miss; + uint32_t excptn_type_sw_flt; + uint32_t excptn_type_nat; + uint32_t excptn_type_ipv6_ct; + uint32_t excptn_type_csum; +}; + +struct odl_ep_stats { + uint32_t rx_pkt; + uint32_t processed_pkt; + uint32_t dropped_pkt; + uint32_t num_queue_pkt; +}; + +struct holb_discard_stats { + uint32_t client_type; + uint32_t num_drp_cnt; + uint32_t num_drp_bytes; + uint32_t reserved; +}; + +struct holb_monitor_stats { + uint32_t client_type; + uint32_t curr_index; + uint32_t num_en_cnt; + uint32_t num_dis_cnt; +}; + +struct holb_drop_and_mon_stats { + uint32_t num_holb_disc_pipes; + uint32_t num_holb_mon_clients; + struct holb_discard_stats holb_disc_stats[0]; + struct holb_monitor_stats holb_mon_stats[0]; +}; + +struct ipa_lnx_generic_stats { + uint32_t tx_dma_pkts; + uint32_t tx_hw_pkts; + uint32_t tx_non_linear; + uint32_t tx_pkts_compl; + uint32_t stats_compl; + uint32_t active_eps; + uint32_t wan_rx_empty; + uint32_t wan_repl_rx_empty; + uint32_t lan_rx_empty; + uint32_t lan_repl_rx_empty; + struct pg_recycle_stats pg_rec_stats; + struct exception_stats excep_stats; + struct odl_ep_stats odl_stats; + struct holb_drop_and_mon_stats holb_stats; +}; + +/* IPA Linux clock stats structures */ +struct pm_client_stats { + uint32_t pm_client_state; + uint32_t pm_client_group; + uint32_t pm_client_bw; + uint32_t pm_client_hdl; + uint32_t pm_client_type; + uint32_t reserved; +}; + +struct ipa_lnx_clock_stats { + uint32_t active_clients; + uint32_t scale_thresh_svs; + uint32_t scale_thresh_nom; + uint32_t scale_thresh_tur; + uint32_t aggr_bw; + uint32_t curr_clk_vote; + struct pm_client_stats pm_clnt_stats[0]; +}; + +/* Generic instance structures */ +struct ipa_lnx_gsi_rx_debug_stats { + uint32_t rx_client; + uint32_t num_rx_ring_100_perc_with_pack; + uint32_t num_rx_ring_0_perc_with_pack; + uint32_t num_rx_ring_above_75_perc_pack; + uint32_t num_rx_ring_above_25_perc_pack; + uint32_t num_rx_ring_stats_polled; + uint32_t num_rx_drop_stats; + uint32_t gsi_debug1; + uint32_t gsi_debug2; + uint32_t gsi_debug3; + uint32_t gsi_debug4; + uint32_t rx_summary; +}; + +struct ipa_lnx_gsi_tx_debug_stats { + uint32_t tx_client; + uint32_t num_tx_ring_100_perc_with_cred; + uint32_t num_tx_ring_0_perc_with_cred; + uint32_t num_tx_ring_above_75_perc_cred; + uint32_t num_tx_ring_above_25_perc_cred; + uint32_t num_tx_ring_stats_polled; + uint32_t num_tx_oob; + uint32_t num_tx_oob_time; + uint32_t gsi_debug1; + uint32_t gsi_debug2; + uint32_t gsi_debug3; + uint32_t gsi_debug4; + uint32_t tx_summary; + uint32_t reserved; +}; + +struct ipa_lnx_gsi_debug_stats { + uint32_t num_tx_instances; + uint32_t num_rx_instances; + struct ipa_lnx_gsi_tx_debug_stats gsi_tx_dbg_stats[0]; + struct ipa_lnx_gsi_rx_debug_stats gsi_rx_dbg_stats[0]; +}; + +struct ipa_lnx_pipe_info { + uint64_t gsi_chan_ring_bp; + uint64_t gsi_chan_ring_rp; + uint64_t gsi_chan_ring_wp; + uint64_t gsi_evt_ring_bp; + uint64_t gsi_evt_ring_rp; + uint64_t gsi_evt_ring_wp; + uint32_t gsi_evt_ring_len; + uint32_t gsi_chan_ring_len; + uint32_t buff_size; + uint32_t num_free_buff; + uint32_t gsi_ipa_if_tlv; + uint32_t gsi_ipa_if_aos; + uint32_t gsi_desc_size; + uint32_t pipe_num; + uint32_t direction; + uint32_t client_type; + uint32_t gsi_chan_num; + uint32_t gsi_evt_num; + uint32_t is_common_evt_ring; + uint32_t gsi_prot_type; + uint32_t gsi_chan_state; + uint32_t gsi_chan_stop_stm; + uint32_t gsi_poll_mode; + uint32_t gsi_db_in_bytes; +}; + +/* IPA Linux wlan instance stats structures */ +struct wlan_instance_info { + uint32_t instance_id; + uint32_t wdi_ver; + uint32_t wlan_mode; + uint32_t wdi_over_gsi; + uint32_t dbs_mode; + uint32_t pm_bandwidth; + uint32_t num_pipes; + uint32_t reserved; + struct ipa_lnx_gsi_debug_stats gsi_debug_stats; + struct ipa_lnx_pipe_info pipe_info[0]; +}; + +struct ipa_lnx_wlan_inst_stats { + uint32_t num_wlan_instance; + uint32_t reserved; + struct wlan_instance_info instance_info[0]; +}; + +/* IPA Linux eth instance stats structures */ +struct eth_instance_info { + uint32_t instance_id; + uint32_t eth_mode; + uint32_t pm_bandwidth; + uint32_t num_pipes; + struct ipa_lnx_gsi_debug_stats gsi_debug_stats; + struct ipa_lnx_pipe_info pipe_info[0]; +}; + +struct ipa_lnx_eth_inst_stats { + uint32_t num_eth_instance; + uint32_t reserved; + struct eth_instance_info instance_info[0]; +}; + +/* IPA Linux usb instance stats structures */ +struct usb_instance_info { + uint32_t instance_id; + uint32_t usb_mode; + uint32_t pm_bandwidth; + uint32_t num_pipes; + struct ipa_lnx_gsi_debug_stats gsi_debug_stats; + struct ipa_lnx_pipe_info pipe_info[0]; +}; + +struct ipa_lnx_usb_inst_stats { + uint32_t num_usb_instance; + uint32_t reserved; + struct usb_instance_info instance_info[0]; +}; + +/* IPA Linux mhip instance stats structures */ +struct mhip_instance_info { + uint32_t instance_id; + uint32_t mhip_mode; + uint32_t pm_bandwidth; + uint32_t num_pipes; + struct ipa_lnx_gsi_debug_stats gsi_debug_stats; + struct ipa_lnx_pipe_info pipe_info[0]; +}; + +struct ipa_lnx_mhip_inst_stats { + uint32_t num_mhip_instance; + uint32_t reserved; + struct mhip_instance_info instance_info[0]; +}; + +struct ipa_lnx_consolidated_stats { + uint64_t log_type_mask; + struct ipa_lnx_generic_stats *generic_stats; + struct ipa_lnx_clock_stats *clock_stats; + struct ipa_lnx_wlan_inst_stats *wlan_stats; + struct ipa_lnx_eth_inst_stats *eth_stats; + struct ipa_lnx_usb_inst_stats *usb_stats; + struct ipa_lnx_mhip_inst_stats *mhip_stats; + struct ipa_lnx_pipe_page_recycling_stats *recycle_stats; +}; + +enum rx_channel_type { + RX_WAN_COALESCING, + RX_WAN_DEFAULT, + RX_WAN_LOW_LAT_DATA, + RX_CHANNEL_MAX, +}; + +struct ipa_lnx_recycling_stats { + uint64_t total_cumulative; + uint64_t recycle_cumulative; + uint64_t temp_cumulative; + uint64_t total_diff; + uint64_t recycle_diff; + uint64_t temp_diff; + uint64_t valid; +}; + +/** + * The consolidated stats will be in the 0th index. + * Diff. between each interval values will be in + * indices 1 to (IPA_LNX_PIPE_PAGE_RECYCLING_INTERVAL_COUNT - 1) + * @new_set: Indicates if this is the new set of data or previous data. + * @interval_time_ms: Interval time in millisecond + */ +struct ipa_lnx_pipe_page_recycling_stats { + uint32_t interval_time_in_ms; + uint32_t default_coal_stats_index; + uint32_t low_lat_stats_index; + uint32_t sequence_id; + uint64_t reserved; + struct ipa_lnx_recycling_stats rx_channel[RX_CHANNEL_MAX][IPA_LNX_PIPE_PAGE_RECYCLING_INTERVAL_COUNT]; +}; + +/* Explain below structures */ +struct ipa_lnx_each_inst_alloc_info { + uint32_t pipes_client_type[TLPD_NUM_MAX_PIPES]; + uint32_t tx_inst_client_type[TLPD_NUM_MAX_TX_INSTANCES]; + uint32_t rx_inst_client_type[TLPD_NUM_MAX_RX_INSTANCES]; + uint32_t num_pipes; + uint32_t num_tx_instances; + uint32_t num_rx_instances; + uint32_t reserved; +}; + +struct ipa_lnx_stats_alloc_info { + uint32_t num_holb_drop_stats_clients; + uint32_t num_holb_mon_stats_clients; + uint32_t num_pm_clients; + uint32_t num_wlan_instances; + uint32_t num_eth_instances; + uint32_t num_usb_instances; + uint32_t num_mhip_instances; + uint32_t num_page_rec_interval; + struct ipa_lnx_each_inst_alloc_info wlan_inst_info[TLPD_NUM_MAX_INSTANCES]; + struct ipa_lnx_each_inst_alloc_info eth_inst_info[TLPD_NUM_MAX_INSTANCES]; + struct ipa_lnx_each_inst_alloc_info usb_inst_info[TLPD_NUM_MAX_INSTANCES]; + struct ipa_lnx_each_inst_alloc_info mhip_inst_info[TLPD_NUM_MAX_INSTANCES]; +}; + +struct ipa_lnx_stats_tlpd_ctx { + uint32_t usb_teth_prot[TLPD_NUM_MAX_INSTANCES]; + uint32_t log_type_mask; + struct ipa_lnx_stats_alloc_info alloc_info; +}; + +/* enum ipa_lnx_stats_ioc_cmd_type - IOCTL Command types for IPA lnx stats + * + */ +enum ipa_lnx_stats_ioc_cmd_type { + IPA_LNX_CMD_GET_ALLOC_INFO, + IPA_LNX_CMD_GENERIC_STATS, + IPA_LNX_CMD_CLOCK_STATS, + IPA_LNX_CMD_WLAN_INST_STATS, + IPA_LNX_CMD_ETH_INST_STATS, + IPA_LNX_CMD_USB_INST_STATS, + IPA_LNX_CMD_MHIP_INST_STATS, + IPA_LNX_CMD_CONSOLIDATED_STATS, + IPA_LNX_CMD_STATS_MAX, +}; + +int ipa_tlpd_stats_init(void); + +/* Peripheral stats for Q6, should be in the same order, defined by Q6 */ +struct ipa_peripheral_mdm_stats { + uint32_t canary; + + uint16_t num_entries; + uint16_t reserved; + + /* TLV for number of peripherals connected to APROC */ + /* value = IPA_PER_STATS_TYPE_NUM_PERS */ + uint16_t periph_id; + uint16_t periph_len; + uint32_t periph_val; + + /* TLV for number of periphers from/to traffic flowing from modem */ + /* value = IPA_PER_STATS_TYPE_NUM_PERS_WWAN */ + uint16_t periph_wwan_id; + uint16_t periph_wwan_len; + uint32_t periph_wwan_val; + + /* TLV for bitmask for active/connected peripherals */ + /* value = IPA_PER_STATS_TYPE_PER_TYPE */ + uint16_t periph_type_id; + uint16_t periph_type_len; + uint32_t periph_type_val; + + /* TLV for Current gen info if PCIe interconnect is valid */ + /* value = IPA_PER_STATS_TYPE_PCIE_GEN */ + uint16_t pcie_gen_type_id; + uint16_t pcie_gen_type_len; + uint32_t pcie_gen_type_val; + + /* TLV for Current width info if PCIe interconnect is valid */ + /* value = IPA_PER_STATS_TYPE_PCIE_WIDTH */ + uint16_t pcie_width_type_id; + uint16_t pcie_width_type_len; + uint32_t pcie_width_type_val; + + /* TLV for Max PCIe speed in current gen in Mbps */ + /* value = IPA_PER_STATS_TYPE_PCIE_MAX_SPEED */ + uint16_t pcie_max_speed_id; + uint16_t pcie_max_speed_len; + uint32_t pcie_max_speed_val; + + /* TLV for number PCIe LPM transitions */ + /* value = IPA_PER_STATS_TYPE_PCIE_NUM_LPM */ + uint16_t pcie_num_lpm_trans_id; + uint16_t pcie_num_lpm_trans_len; + uint16_t pcie_num_lpm_trans_d3; + uint16_t pcie_num_lpm_trans_m1; + uint16_t pcie_num_lpm_trans_m2; + uint16_t pcie_num_lpm_trans_m0; + + /* TLV for USB enumeration type */ + /* value = IPA_PER_STATS_TYPE_USB_TYPE */ + uint16_t usb_enum_id; + uint16_t usb_enum_len; + uint32_t usb_enum_value; + + /* TLV for Current USB protocol enumeration if active */ + /* value = IPA_PER_STATS_TYPE_USB_PROT */ + uint16_t usb_prot_enum_id; + uint16_t usb_prot_enum_len; + uint32_t usb_prot_enum_value; + + /* TLV for Max USB speed in current gen in Mbps */ + /* value = IPA_PER_STATS_TYPE_USB_MAX_SPEED */ + uint16_t usb_max_speed_id; + uint16_t usb_max_speed_len; + uint32_t usb_max_speed_val; + + /* TLV for Total number of USB plug in/outs */ + /* value = IPA_PER_STATS_TYPE_USB_PIPO */ + uint16_t usb_pipo_id; + uint16_t usb_pipo_len; + uint32_t usb_pipo_val; + + /* TLV for Wifi enumeration type*/ + /* value = IPA_PER_STATS_TYPE_WIFI_ENUM_TYPE */ + uint16_t wifi_enum_type_id; + uint16_t wifi_enum_type_len; + uint32_t wifi_enum_type_val; + + /* TLV for Theoritical Max WLAN speed in current gen in Mbps (pipe for 5GHz in case of dual band) */ + /* value = IPA_PER_STATS_TYPE_WIFI_MAX_SPEED */ + uint16_t wifi_max_speed_id; + uint16_t wifi_max_speed_len; + uint32_t wifi_max_speed_val; + + /* TLV for Theoretical Max WLAN speed on the 2.4GHz pipe, value of 0 means disabled */ + /* value = IPA_PER_STATS_TYPE_WIFI_DUAL_BAND_EN */ + uint16_t wifi_dual_band_enabled_id; + uint16_t wifi_dual_band_enabled_len; + uint32_t wifi_dual_band_enabled_val; + + /* TLV for the type of ethernet client - Realtek/AQC */ + /* value = IPA_PER_STATS_TYPE_ETH_CLIENT */ + uint16_t eth_client_id; + uint16_t eth_client_len; + uint32_t eth_client_val; + + /* TLV for Max Eth link speed */ + /* value = IPA_PER_STATS_TYPE_ETH_MAX_SPEED */ + uint16_t eth_max_speed_id; + uint16_t eth_max_speed_len; + uint32_t eth_max_speed_val; + + /* TLV for Total number of bytes txferred through IPA DMA channels over PCIe */ + /* For cases where GSI used for QDSS direct DMA, need to extract bytes stats from GSI FW */ + /* value = IPA_PER_STATS_TYPE_IPA_DMA_BYTES */ + uint16_t ipa_dma_bytes_id; + uint16_t ipa_dma_bytes_len; + uint32_t ipa_dma_bytes_val; + + /* TLV for number of wifi peripherals connected to APROC */ + /* value = IPA_PER_STATS_TYPE_WIFI_HOLB_UC */ + uint16_t wifi_holb_uc_stats_id; + uint16_t wifi_holb_uc_stats_len; + uint16_t wifi_holb_uc_stats_num_periph_bad; + uint16_t wifi_holb_uc_stats_num_periph_recovered; + + /* TLV for number of eth peripherals connected to APROC */ + /* value = IPA_PER_STATS_TYPE_ETH_HOLB_UC */ + uint16_t eth_holb_uc_stats_id; + uint16_t eth_holb_uc_stats_len; + uint16_t eth_holb_uc_stats_num_periph_bad; + uint16_t eth_holb_uc_stats_num_periph_recovered; + + /* TLV for number of usb peripherals connected to APROC */ + /* value = IPA_PER_STATS_TYPE_USB_HOLB_UC */ + uint16_t usb_holb_uc_stats_id; + uint16_t usb_holb_uc_stats_len; + uint16_t usb_holb_uc_stats_num_periph_bad; + uint16_t usb_holb_uc_stats_num_periph_recovered; +}; + +struct ipa_peripheral_msm_stats { + uint32_t canary; + + uint16_t num_entries; + uint16_t reserved; + + /* TLV for number of peripherals connected to APROC */ + /* value = IPA_PER_STATS_TYPE_NUM_PERS */ + uint16_t periph_id; + uint16_t periph_len; + uint32_t periph_val; + + /* TLV for number of periphers from/to traffic flowing from modem */ + /* value = IPA_PER_STATS_TYPE_NUM_PERS_WWAN */ + uint16_t periph_wwan_id; + uint16_t periph_wwan_len; + uint32_t periph_wwan_val; + + /* TLV for bitmask for active/connected peripherals */ + /* value = IPA_PER_STATS_TYPE_PER_TYPE */ + uint16_t periph_type_id; + uint16_t periph_type_len; + uint32_t periph_type_val; + + /* TLV for USB enumeration type */ + /* value = IPA_PER_STATS_TYPE_USB_TYPE */ + uint16_t usb_enum_id; + uint16_t usb_enum_len; + uint32_t usb_enum_value; + + /* TLV for Current USB protocol enumeration if active */ + /* value = IPA_PER_STATS_TYPE_USB_PROT */ + uint16_t usb_prot_enum_id; + uint16_t usb_prot_enum_len; + uint32_t usb_prot_enum_value; + + /* TLV for Max USB speed in current gen in Mbps */ + /* value = IPA_PER_STATS_TYPE_USB_MAX_SPEED */ + uint16_t usb_max_speed_id; + uint16_t usb_max_speed_len; + uint32_t usb_max_speed_val; + + /* TLV for Total number of USB plug in/outs */ + /* value = IPA_PER_STATS_TYPE_USB_PIPO */ + uint16_t usb_pipo_id; + uint16_t usb_pipo_len; + uint32_t usb_pipo_val; + + /* TLV for Wifi enumeration type*/ + /* value = IPA_PER_STATS_TYPE_WIFI_ENUM_TYPE */ + uint16_t wifi_enum_type_id; + uint16_t wifi_enum_type_len; + uint32_t wifi_enum_type_val; + + /* TLV for Theoritical Max WLAN speed in current gen in Mbps (pipe for 5GHz in case of dual band) */ + /* value = IPA_PER_STATS_TYPE_WIFI_MAX_SPEED */ + uint16_t wifi_max_speed_id; + uint16_t wifi_max_speed_len; + uint32_t wifi_max_speed_val; + + /* TLV for Theoretical Max WLAN speed on the 2.4GHz pipe, value of 0 means disabled */ + /* value = IPA_PER_STATS_TYPE_WIFI_DUAL_BAND_EN */ + uint16_t wifi_dual_band_enabled_id; + uint16_t wifi_dual_band_enabled_len; + uint32_t wifi_dual_band_enabled_val; + + /* TLV for number of wifi peripherals connected to APROC */ + /* value = IPA_PER_STATS_TYPE_WIFI_HOLB_UC */ + uint16_t wifi_holb_uc_stats_id; + uint16_t wifi_holb_uc_stats_len; + uint16_t wifi_holb_uc_stats_num_periph_bad; + uint16_t wifi_holb_uc_stats_num_periph_recovered; + + /* TLV for number of usb peripherals connected to APROC */ + /* value = IPA_PER_STATS_TYPE_USB_HOLB_UC */ + uint16_t usb_holb_uc_stats_id; + uint16_t usb_holb_uc_stats_len; + uint16_t usb_holb_uc_stats_num_periph_bad; + uint16_t usb_holb_uc_stats_num_periph_recovered; +}; + +union ipa_peripheral_stats { + struct ipa_peripheral_mdm_stats mdm; + struct ipa_peripheral_msm_stats msm; +}; + +int ipa3_peripheral_stats_init(union ipa_peripheral_stats *smem_addr); + +#endif // _UAPI_IPA_LNX_STATS_H_ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_trace.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_trace.h new file mode 100644 index 0000000000..8507f79885 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_trace.h @@ -0,0 +1,404 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#undef TRACE_SYSTEM +#define TRACE_SYSTEM ipa +#define TRACE_INCLUDE_FILE ipa_trace + +#if !defined(_IPA_TRACE_H) || defined(TRACE_HEADER_MULTI_READ) +#define _IPA_TRACE_H + +#include + +TRACE_EVENT( + intr_to_poll3, + + TP_PROTO(unsigned long client), + + TP_ARGS(client), + + TP_STRUCT__entry( + __field(unsigned long, client) + ), + + TP_fast_assign( + __entry->client = client; + ), + + TP_printk("client=%lu", __entry->client) +); + +TRACE_EVENT( + poll_to_intr3, + + TP_PROTO(unsigned long client), + + TP_ARGS(client), + + TP_STRUCT__entry( + __field(unsigned long, client) + ), + + TP_fast_assign( + __entry->client = client; + ), + + TP_printk("client=%lu", __entry->client) +); + +TRACE_EVENT( + idle_sleep_enter3, + + TP_PROTO(unsigned long client), + + TP_ARGS(client), + + TP_STRUCT__entry( + __field(unsigned long, client) + ), + + TP_fast_assign( + __entry->client = client; + ), + + TP_printk("client=%lu", __entry->client) +); + +TRACE_EVENT( + idle_sleep_exit3, + + TP_PROTO(unsigned long client), + + TP_ARGS(client), + + TP_STRUCT__entry( + __field(unsigned long, client) + ), + + TP_fast_assign( + __entry->client = client; + ), + + TP_printk("client=%lu", __entry->client) +); + +TRACE_EVENT( + rmnet_ipa_netifni3, + + TP_PROTO(unsigned long rx_pkt_cnt), + + TP_ARGS(rx_pkt_cnt), + + TP_STRUCT__entry( + __field(unsigned long, rx_pkt_cnt) + ), + + TP_fast_assign( + __entry->rx_pkt_cnt = rx_pkt_cnt; + ), + + TP_printk("rx_pkt_cnt=%lu", __entry->rx_pkt_cnt) +); + +TRACE_EVENT( + rmnet_ipa_netifrx3, + + TP_PROTO(unsigned long rx_pkt_cnt), + + TP_ARGS(rx_pkt_cnt), + + TP_STRUCT__entry( + __field(unsigned long, rx_pkt_cnt) + ), + + TP_fast_assign( + __entry->rx_pkt_cnt = rx_pkt_cnt; + ), + + TP_printk("rx_pkt_cnt=%lu", __entry->rx_pkt_cnt) +); + +TRACE_EVENT( + rmnet_ipa_netif_rcv_skb3, + + TP_PROTO(const struct sk_buff *skb, unsigned long rx_pkt_cnt), + + TP_ARGS(skb, rx_pkt_cnt), + + TP_STRUCT__entry( + __string(name, skb->dev->name) + __field(const void *, skbaddr) + __field(u16, protocol) + __field(unsigned int, len) + __field(unsigned int, data_len) + __field(unsigned long, rx_pkt_cnt) + ), + + TP_fast_assign( + __assign_str(name, skb->dev->name); + __entry->skbaddr = skb; + __entry->protocol = ntohs(skb->protocol); + __entry->len = skb->len; + __entry->data_len = skb->data_len; + __entry->rx_pkt_cnt = rx_pkt_cnt; + ), + + TP_printk("dev=%s skbaddr=%p protocol=0x%04x len=%u data_len=%u rx_pkt_cnt=%lu", + __get_str(name), + __entry->skbaddr, + __entry->protocol, + __entry->len, + __entry->data_len, + __entry->rx_pkt_cnt) +); + +TRACE_EVENT( + ipa3_napi_rx_poll_num, + + TP_PROTO(unsigned long client, int poll_num), + + TP_ARGS(client, poll_num), + + TP_STRUCT__entry( + __field(unsigned long, client) + __field(int, poll_num) + ), + + TP_fast_assign( + __entry->client = client; + __entry->poll_num = poll_num; + ), + + TP_printk("client=%lu each_poll_aggr_pkt_num=%d", + __entry->client, + __entry->poll_num) +); + +TRACE_EVENT( + ipa3_napi_rx_poll_cnt, + + TP_PROTO(unsigned long client, int poll_num), + + TP_ARGS(client, poll_num), + + TP_STRUCT__entry( + __field(unsigned long, client) + __field(int, poll_num) + ), + + TP_fast_assign( + __entry->client = client; + __entry->poll_num = poll_num; + ), + + TP_printk("client=%lu napi_overall_poll_pkt_cnt=%d", + __entry->client, + __entry->poll_num) +); + +TRACE_EVENT( + ipa3_napi_schedule, + + TP_PROTO(unsigned long client), + + TP_ARGS(client), + + TP_STRUCT__entry( + __field(unsigned long, client) + ), + + TP_fast_assign( + __entry->client = client; + ), + + TP_printk("client=%lu", __entry->client) +); + +TRACE_EVENT( + ipa3_napi_poll_entry, + + TP_PROTO(unsigned long client), + + TP_ARGS(client), + + TP_STRUCT__entry( + __field(unsigned long, client) + ), + + TP_fast_assign( + __entry->client = client; + ), + + TP_printk("client=%lu", __entry->client) +); + + +TRACE_EVENT( + ipa3_napi_poll_exit, + + TP_PROTO(unsigned long client), + + TP_ARGS(client), + + TP_STRUCT__entry( + __field(unsigned long, client) + ), + + TP_fast_assign( + __entry->client = client; + ), + + TP_printk("client=%lu", __entry->client) +); + +TRACE_EVENT( + ipa_tx_dp, + + TP_PROTO(const struct sk_buff *skb, unsigned long client), + + TP_ARGS(skb, client), + + TP_STRUCT__entry( + __string(name, skb->dev->name) + __field(const void *, skbaddr) + __field(u16, protocol) + __field(unsigned int, len) + __field(unsigned int, data_len) + __field(unsigned long, client) + ), + + TP_fast_assign( + __assign_str(name, skb->dev->name); + __entry->skbaddr = skb; + __entry->protocol = ntohs(skb->protocol); + __entry->len = skb->len; + __entry->data_len = skb->data_len; + __entry->client = client; + ), + + TP_printk("dev=%s skbaddr=%p protocol=0x%04x len=%u data_len=%u client=%lu", + __get_str(name), + __entry->skbaddr, + __entry->protocol, + __entry->len, + __entry->data_len, + __entry->client) +); + +TRACE_EVENT( + ipa3_tx_done, + + TP_PROTO(unsigned long client), + + TP_ARGS(client), + + TP_STRUCT__entry( + __field(unsigned long, client) + ), + + TP_fast_assign( + __entry->client = client; + ), + + TP_printk("client=%lu", __entry->client) +); + +TRACE_EVENT( + ipa3_replenish_rx_page_recycle, + + TP_PROTO(u32 i, struct page *p, bool is_tmp_alloc), + + TP_ARGS(i, p, is_tmp_alloc), + + TP_STRUCT__entry( + __field(u32, i) + __field(struct page *, p) + __field(bool, is_tmp_alloc) + __field(unsigned long, pfn) + ), + + TP_fast_assign( + __entry->i = i; + __entry->p = p; + __entry->is_tmp_alloc = is_tmp_alloc; + __entry->pfn = page_to_pfn(p); + ), + + TP_printk("wan_cons type=%u: page=0x%pK pfn=0x%lx tmp=%s", + __entry->i, __entry->p, __entry->pfn, + __entry->is_tmp_alloc ? "true" : "false") +); + +TRACE_EVENT( + handle_page_completion, + + TP_PROTO(struct page *p, struct sk_buff *skb, u16 len, + bool is_tmp_alloc, enum ipa_client_type client), + + TP_ARGS(p, skb, len, is_tmp_alloc, client), + + TP_STRUCT__entry( + __field(struct page *, p) + __field(struct sk_buff *, skb) + __field(u16, len) + __field(bool, is_tmp_alloc) + __field(unsigned long, pfn) + __field(enum ipa_client_type, client) + ), + + TP_fast_assign( + __entry->p = p; + __entry->skb = skb; + __entry->len = len; + __entry->is_tmp_alloc = is_tmp_alloc; + __entry->pfn = page_to_pfn(p); + __entry->client = client; + ), + + TP_printk("%s: page=0x%pK pfn=0x%lx skb=0x%pK len=%u tmp=%s", + (__entry->client == IPA_CLIENT_APPS_WAN_CONS) ? "WAN_CONS" + : "WAN_COAL_CONS", + __entry->p, __entry->pfn, __entry->skb, __entry->len, + __entry->is_tmp_alloc ? "true" : "false") +); + +TRACE_EVENT( + ipa3_rx_napi_chain, + + TP_PROTO(struct sk_buff *first_skb, struct sk_buff *prev_skb, + struct sk_buff *rx_skb), + + TP_ARGS(first_skb, prev_skb, rx_skb), + + TP_STRUCT__entry( + __field(struct sk_buff *, first_skb) + __field(struct sk_buff *, prev_skb) + __field(struct sk_buff *, rx_skb) + ), + + TP_fast_assign( + __entry->first_skb = first_skb; + __entry->prev_skb = prev_skb; + __entry->rx_skb = rx_skb; + ), + + TP_printk("first_skb=0x%pK prev_skb=0x%pK rx_skb=0x%pK", + __entry->first_skb, __entry->prev_skb, __entry->rx_skb) +); + +#endif /* _IPA_TRACE_H */ + +/* This part must be outside protection */ +#ifndef IPA_TRACE_INCLUDE_PATH +#ifdef CONFIG_IPA_VENDOR_DLKM +#define IPA_TRACE_INCLUDE_PATH ../../../../vendor/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3 +#else +#define IPA_TRACE_INCLUDE_PATH ../../techpack/dataipa/drivers/platform/msm/ipa/ipa_v3 +#endif +#endif + +#define TRACE_INCLUDE_PATH IPA_TRACE_INCLUDE_PATH +#include diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_tsp.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_tsp.c new file mode 100644 index 0000000000..b3a2f2e4a7 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_tsp.c @@ -0,0 +1,365 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include "ipa_i.h" +#include "ipahal.h" +#include "ipahal_reg.h" +#include "ipahal_tsp.h" + +/* + * Every Producer can hold up to 16 K Queue elements and 8 Queues. + * Thus, software allocates up to 512 Kbytes (32 bytes *16 K QEs) contiguously in memory. + */ +#define IPA_TSP_QM_DRAM_BYTESIZE (16384 * 32) + +static void __ipa_tsp_get_supported_constrains(void) +{ + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_5) { + struct ipahal_ipa_flavor_9 ipa_flavor_9; + + ipahal_read_reg_fields(IPA_FLAVOR_9, &ipa_flavor_9); + ipa3_ctx->tsp.ingr_tc_max = ipa_flavor_9.ipa_tsp_max_ingr_tc; + ipa3_ctx->tsp.egr_ep_max = ipa_flavor_9.ipa_tsp_max_prod; + ipa3_ctx->tsp.egr_tc_max = ipa_flavor_9.ipa_tsp_max_egr_tc; + } else { + ipa3_ctx->tsp.ingr_tc_max = 0; + ipa3_ctx->tsp.egr_ep_max = 0; + ipa3_ctx->tsp.egr_tc_max = 0; + + IPAERR("TSP not supported. ingr_tc_max=%d egr_ep_max=%d egr_tc_max=%d\n", + ipa3_ctx->tsp.ingr_tc_max, ipa3_ctx->tsp.egr_ep_max, ipa3_ctx->tsp.egr_tc_max); + } +} + +int ipa_tsp_init(void) +{ + int i, ret = 0; + gfp_t flag = GFP_KERNEL; + dma_addr_t qm_tlv_base; + u32 qm_tlv_size; + + /* + * Cache the TSP table size constrains + */ + __ipa_tsp_get_supported_constrains(); + if (!ipa3_ctx->tsp.ingr_tc_max || !ipa3_ctx->tsp.egr_ep_max || !ipa3_ctx->tsp.egr_tc_max) { + IPAERR("TSP not supported. ingr_tc_max=%d egr_ep_max=%d egr_tc_max=%d\n", + ipa3_ctx->tsp.ingr_tc_max, ipa3_ctx->tsp.egr_ep_max, ipa3_ctx->tsp.egr_tc_max); + return -EFAULT; + } + + /* + * Allocate DMA accessible memory for HW commitable ipa3_ctx->tsp.ingr_tc_tbl, + * ipa3_ctx->tsp.egr_ep_tbl and ipa3_ctx->tsp.egr_tc_tbl + */ + ipa3_ctx->tsp.ingr_tc_tbl.size = ipa3_ctx->tsp.ingr_tc_max * IPA_TSP_INGR_TC_SIZE; + ipa3_ctx->tsp.egr_ep_tbl.size = ipa3_ctx->tsp.egr_ep_max * IPA_TSP_EGR_EP_SIZE; + ipa3_ctx->tsp.egr_tc_tbl.size = ipa3_ctx->tsp.egr_tc_max * IPA_TSP_EGR_TC_SIZE; + + if (!ipa3_ctx->tsp.ingr_tc_tbl.size || !ipa3_ctx->tsp.egr_ep_tbl.size || !ipa3_ctx->tsp.egr_tc_tbl.size) { + IPAERR("ingr_tc_tbl.size=%d egr_ep_tbl.size=%d egr_tc_tbl.size=%d\n", + ipa3_ctx->tsp.ingr_tc_tbl.size, ipa3_ctx->tsp.egr_ep_tbl.size, ipa3_ctx->tsp.egr_tc_tbl.size); + return -EFAULT; + } + + if (!ipa3_ctx->pdev || !&(ipa3_ctx->tsp.ingr_tc_tbl.phys_base)) { + IPAERR("ipa3_ctx->pdev=%16X &(ipa3_ctx->tsp.ingr_tc_tbl.phys_base)=%16X\n", + ipa3_ctx->pdev, &(ipa3_ctx->tsp.ingr_tc_tbl.phys_base)); + return -EFAULT; + } + IPAERR("ipa3_ctx->pdev=%16X &(ipa3_ctx->tsp.ingr_tc_tbl.phys_base)=%16X\n", + ipa3_ctx->pdev, &(ipa3_ctx->tsp.ingr_tc_tbl.phys_base)); + + ipa3_ctx->tsp.ingr_tc_tbl.base = dma_alloc_coherent(ipa3_ctx->pdev, + ipa3_ctx->tsp.ingr_tc_tbl.size, &(ipa3_ctx->tsp.ingr_tc_tbl.phys_base), GFP_KERNEL); + if (!ipa3_ctx->tsp.ingr_tc_tbl.base) { + IPAERR("Failed to allocate cache memory for ingress TC TSP table.\n"); + return -ENOMEM; + } + + ipa3_ctx->tsp.egr_ep_tbl.base = dma_alloc_coherent(ipa3_ctx->pdev, + ipa3_ctx->tsp.egr_ep_tbl.size, &(ipa3_ctx->tsp.egr_ep_tbl.phys_base), GFP_KERNEL); + if (!ipa3_ctx->tsp.egr_ep_tbl.base) { + IPAERR("Failed to allocate cache memory for egress producer TSP table.\n"); + ret = -ENOMEM; + goto free_ingr; + } + + ipa3_ctx->tsp.egr_tc_tbl.base = dma_alloc_coherent(ipa3_ctx->pdev, + ipa3_ctx->tsp.egr_tc_tbl.size, &(ipa3_ctx->tsp.egr_tc_tbl.phys_base), GFP_KERNEL); + if (!ipa3_ctx->tsp.egr_tc_tbl.base) { + IPAERR("Failed to allocate cache memory for egress TC TSP table.\n"); + ret = -ENOMEM; + goto free_ep; + } + + /* + * Allocate configured producer array + */ + ipa3_ctx->tsp.egr_ep_config = + (enum ipa_client_type *) + kzalloc(ipa3_ctx->tsp.egr_ep_max * sizeof(enum ipa_client_type), GFP_KERNEL); + + if (ipa3_ctx->tsp.egr_ep_config == NULL) { + IPAERR("Failed to allocate cache memory for egress producer config.\n"); + ret = -ENOMEM; + goto free_egr; + } + + /* + * Init configured producer array + */ + for (i = 0; i < ipa3_ctx->tsp.egr_ep_max; i++) + ipa3_ctx->tsp.egr_ep_config[i] = IPA_CLIENT_MAX; + ipa3_ctx->tsp.egr_tc_range_mask = 0; + + /* + * Allocate memory for TLV-IN queues: + * Every Producer can hold up to 16 K Queue elements and 8 Queues. + * Thus, software allocates up to 512 Kbytes (32 bytes *16 K QEs) contiguously in memory. + * Note: All queues of all PRODs have to be together in contiguous memory! + * Must be 128B aligned. + */ + qm_tlv_size = IPA_TSP_QM_DRAM_BYTESIZE; + ipa3_ctx->tsp.qm_tlv_mem.size = qm_tlv_size + 128; // + 128 bytes to fit alignment +alloc: + ipa3_ctx->tsp.qm_tlv_mem.base = dma_alloc_coherent(ipa3_ctx->pdev, + ipa3_ctx->tsp.qm_tlv_mem.size, &(ipa3_ctx->tsp.qm_tlv_mem.phys_base), flag); + if (!ipa3_ctx->tsp.qm_tlv_mem.base) { + if (flag == GFP_KERNEL) { + flag = GFP_ATOMIC; + goto alloc; + } + IPAERR("fail to alloc DMA buff of size %d\n", ipa3_ctx->tsp.qm_tlv_mem.size); + ret = -ENOMEM; + goto free_ep_conf; + } + + /* Get 128B aligned address inside the buffer */ + qm_tlv_base = ipa3_ctx->tsp.qm_tlv_mem.phys_base; + if (qm_tlv_base & 0x7F) { + qm_tlv_base += 0x80; + qm_tlv_base &= !0x7F; + } + + ipahal_write_reg(IPA_TSP_QM_EXTERNAL_BADDR_LSB, qm_tlv_base & 0xFFFFFFFF); + ipahal_write_reg(IPA_TSP_QM_EXTERNAL_BADDR_MSB, qm_tlv_base >> 32); + ipahal_write_reg(IPA_TSP_QM_EXTERNAL_SIZE, qm_tlv_size >> 12); //Size in 4kB resolution + + goto done; + +free_ep_conf: + kfree(ipa3_ctx->tsp.egr_ep_config); + ipa3_ctx->tsp.egr_ep_config = NULL; +free_egr: + dma_free_coherent(ipa3_ctx->pdev, ipa3_ctx->tsp.egr_tc_tbl.size, + ipa3_ctx->tsp.egr_tc_tbl.base, ipa3_ctx->tsp.egr_tc_tbl.phys_base); + ipa3_ctx->tsp.egr_tc_tbl.base = NULL; +free_ep: + dma_free_coherent(ipa3_ctx->pdev, ipa3_ctx->tsp.egr_ep_tbl.size, + ipa3_ctx->tsp.egr_ep_tbl.base, ipa3_ctx->tsp.egr_ep_tbl.phys_base); + ipa3_ctx->tsp.egr_ep_tbl.base = NULL; +free_ingr: + dma_free_coherent(ipa3_ctx->pdev, ipa3_ctx->tsp.ingr_tc_tbl.size, + ipa3_ctx->tsp.ingr_tc_tbl.base, ipa3_ctx->tsp.ingr_tc_tbl.phys_base); + ipa3_ctx->tsp.ingr_tc_tbl.base = NULL; +done: + return ret; +} + +int ipa_tsp_get_ingr_tc(u8 index, struct ipa_ioc_tsp_ingress_class_params *output) +{ + /* The function is internal only, assuming valid params */ + + ipahal_tsp_parse_hw_ingr_tc(ipa3_ctx->tsp.ingr_tc_tbl.base, index, output); + output->include_l2_len = !!(ipahal_read_reg(IPA_TSP_INGRESS_POLICING_CFG) & (0x1 << index)); + + return 0; +} + +int ipa_tsp_get_egr_ep(u8 index, struct ipa_ioc_tsp_egress_prod_params *output) +{ + u32 regval; + struct ipa_ep_cfg_prod_cfg prod_cfg; + + /* The function is internal only, assuming valid params */ + + ipahal_tsp_parse_hw_egr_ep(ipa3_ctx->tsp.egr_ep_tbl.base, index, output); + + output->client = ipa3_ctx->tsp.egr_ep_config[index]; + + regval = ipahal_read_reg_n_fields(IPA_ENDP_INIT_PROD_CFG_n, + ipa_get_ep_mapping(output->client), (void *)&prod_cfg); + + output->max_out_bytes = prod_cfg.max_output_size << 6; // max_output_size*64 + output->policing_by_max_out = prod_cfg.max_output_size_drop_enable; + output->tc_lo = prod_cfg.egress_tc_lowest; + output->tc_hi = prod_cfg.egress_tc_highest; + + return 0; +} + +int ipa_tsp_get_egr_tc(u8 index, struct ipa_ioc_tsp_egress_class_params *output) +{ + /* The function is internal only, assuming valid params */ + + ipahal_tsp_parse_hw_egr_tc(ipa3_ctx->tsp.egr_tc_tbl.base, index, output); + + return 0; +} + +int ipa_tsp_set_ingr_tc(u8 index, const struct ipa_ioc_tsp_ingress_class_params *input) +{ + /* The function is internal only, assuming valid params */ + + ipahal_tsp_fill_hw_ingr_tc(input, ipa3_ctx->tsp.ingr_tc_tbl.base, index); + ipahal_write_reg_mask(IPA_TSP_INGRESS_POLICING_CFG, + 0x1 << input->include_l2_len, 0x1 << index); + + return 0; +} + +int ipa_tsp_set_egr_ep(u8 index, const struct ipa_ioc_tsp_egress_prod_params *input) +{ + u32 regval, ep_index, ep_tc_mask, new_tc_range_mask; + struct ipa_ep_cfg_prod_cfg prod_cfg; + bool cleanup = false; + + ep_tc_mask = GENMASK(input->tc_hi, input->tc_lo); + new_tc_range_mask = ipa3_ctx->tsp.egr_tc_range_mask; + + ep_index = ipa_get_ep_mapping(ipa3_ctx->tsp.egr_ep_config[index]); + regval = ipahal_read_reg_n_fields( + IPA_ENDP_INIT_PROD_CFG_n, ep_index, (void *)&prod_cfg); + + if (ipa3_ctx->tsp.egr_ep_config[index] != IPA_CLIENT_MAX && + ipa3_ctx->tsp.egr_ep_config[index] != input->client) { + cleanup = true; + new_tc_range_mask &= !GENMASK(prod_cfg.egress_tc_highest,prod_cfg.egress_tc_lowest); + } + + if (ep_tc_mask & new_tc_range_mask) { + IPAERR("New egress TC range overlaps existing.\n"); + return -EINVAL; + } + + if (cleanup) { + /* Cleanup old producer config */ + prod_cfg.tsp_enable = false; + prod_cfg.egress_tc_lowest = 0; + prod_cfg.egress_tc_highest = 0; + if (ipa3_cfg_ep_prod_cfg(ep_index, &prod_cfg) != 0) { + IPAERR("Failed configuring the producer EP.\n"); + return -EFAULT; + } + } + + prod_cfg.tsp_enable = true; + prod_cfg.tsp_idx = index; + prod_cfg.max_output_size = input->max_out_bytes >> 6; // max_out_bytes/64 + prod_cfg.max_output_size_drop_enable = input->policing_by_max_out; + prod_cfg.egress_tc_lowest = input->tc_lo; + prod_cfg.egress_tc_highest = input->tc_hi; + if (ipa3_cfg_ep_prod_cfg(ipa_get_ep_mapping(input->client), &prod_cfg) != 0) { + IPAERR("Failed configuring the producer EP.\n"); + return -EFAULT; + } + + ipa3_ctx->tsp.egr_ep_config[index] = input->client; + ipa3_ctx->tsp.egr_tc_range_mask = new_tc_range_mask | ep_tc_mask; + ipahal_tsp_fill_hw_egr_ep(input, ipa3_ctx->tsp.egr_ep_tbl.base, index); + + return 0; +} + +int ipa_tsp_set_egr_tc(u8 index, const struct ipa_ioc_tsp_egress_class_params *input) +{ + /* The function is internal only, assuming valid params */ + + ipahal_tsp_fill_hw_egr_tc(input, ipa3_ctx->tsp.egr_tc_tbl.base, index); + + /* + * If guaranteed_rate and guaranteed_burst are set to 0, + * the guaranteed bandwidth rate will be disabled, + * and only maximal bandwidth rate will be considered. + */ + if (input->guaranteed_rate || input->guaranteed_burst) + ipahal_write_reg_mask(IPA_TSP_EGRESS_POLICING_CFG, 0x1 << index, 0x1 << index); + else + ipahal_write_reg_mask(IPA_TSP_EGRESS_POLICING_CFG, 0x0, 0x1 << index); + + return 0; +} + +int ipa_tsp_commit(void) +{ + int ret = 0; + u32 ingr_tc_base, egr_tc_base, prod_base; + void *ingr_tc_mmio, *egr_tc_mmio, *prod_mmio; + + ingr_tc_base = ipahal_read_reg(IPA_RAM_INGRESS_POLICER_DB_BASE_ADDR); + egr_tc_base = ipahal_read_reg(IPA_RAM_EGRESS_SHAPING_TC_DB_BASE_ADDR); + prod_base = ipahal_read_reg(IPA_RAM_EGRESS_SHAPING_PROD_DB_BASE_ADDR); + + /* map IPA SRAM */ + ingr_tc_mmio = ioremap(ipa3_ctx->ipa_wrapper_base + ingr_tc_base, + ipa3_ctx->tsp.ingr_tc_tbl.size); + egr_tc_mmio = ioremap(ipa3_ctx->ipa_wrapper_base + egr_tc_base, + ipa3_ctx->tsp.egr_tc_tbl.size); + prod_mmio = ioremap(ipa3_ctx->ipa_wrapper_base + prod_base, + ipa3_ctx->tsp.egr_ep_tbl.size); + if (!ingr_tc_mmio || !egr_tc_mmio || !prod_mmio) { + IPAERR("Failed to ioremap TSP SRAM\n"); + ret = -ENOMEM; + goto end; + } + + /* + * The tables are located in the HW SRAM area, and we can't issue the DMA IMM, because + * the offset field is restricted to 16 addresses in it. + * Therefore, we do memcopy instead, but the infrastructure will be ready for DMA + * in future IPA versions. + */ + memcpy_toio(ingr_tc_mmio, ipa3_ctx->tsp.ingr_tc_tbl.base, ipa3_ctx->tsp.ingr_tc_tbl.size); + memcpy_toio(egr_tc_mmio, ipa3_ctx->tsp.egr_tc_tbl.base, ipa3_ctx->tsp.egr_tc_tbl.size); + memcpy_toio(prod_mmio, ipa3_ctx->tsp.egr_ep_tbl.base, ipa3_ctx->tsp.egr_ep_tbl.size); + +end: + if (ingr_tc_mmio) + iounmap(ingr_tc_mmio); + if (egr_tc_mmio) + iounmap(egr_tc_mmio); + if (prod_mmio) + iounmap(prod_mmio); + return ret; +} + +int ipa_tsp_reset(void) +{ + int i; + struct ipa_ep_cfg_prod_cfg prod_cfg = {0}; + + for (i = 0; + i < ipa3_ctx->tsp.egr_ep_max && ipa3_ctx->tsp.egr_ep_config[i] < IPA_CLIENT_MAX; i++) + ipa3_cfg_ep_prod_cfg(ipa_get_ep_mapping(ipa3_ctx->tsp.egr_ep_config[i]), + &prod_cfg); + + if (ipa3_ctx->tsp.ingr_tc_tbl.base) + memset(ipa3_ctx->tsp.ingr_tc_tbl.base, 0, ipa3_ctx->tsp.ingr_tc_tbl.size); + if (ipa3_ctx->tsp.egr_tc_tbl.base) + memset(ipa3_ctx->tsp.egr_tc_tbl.base, 0, ipa3_ctx->tsp.egr_tc_tbl.size); + if (ipa3_ctx->tsp.egr_ep_tbl.base) + memset(ipa3_ctx->tsp.egr_ep_tbl.base, 0, ipa3_ctx->tsp.egr_ep_tbl.size); + + /* Reinit configured producer array */ + for (i = 0; i < ipa3_ctx->tsp.egr_ep_max; i++) + ipa3_ctx->tsp.egr_ep_config[i] = IPA_CLIENT_MAX; + + ipa3_ctx->tsp.egr_tc_range_mask = 0; + + return ipa_tsp_commit(); +} + diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_tsp.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_tsp.h new file mode 100644 index 0000000000..3d7800e33c --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_tsp.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _IPA_TSP_H_ +#define _IPA_TSP_H_ + +#include +/* The following line should be removed once TSP feature is POR */ +#include "ipa_test_module_tsp.h" + +int ipa_tsp_init(void); +int ipa_tsp_commit(void); +int ipa_tsp_reset(void); +int ipa_tsp_get_ingr_tc(u8 index, struct ipa_ioc_tsp_ingress_class_params *output); +int ipa_tsp_get_egr_ep(u8 index, struct ipa_ioc_tsp_egress_prod_params *output); +int ipa_tsp_get_egr_tc(u8 index, struct ipa_ioc_tsp_egress_class_params *output); +int ipa_tsp_set_ingr_tc(u8 index, const struct ipa_ioc_tsp_ingress_class_params *input); +int ipa_tsp_set_egr_ep(u8 index, const struct ipa_ioc_tsp_egress_prod_params *input); +int ipa_tsp_set_egr_tc(u8 index, const struct ipa_ioc_tsp_egress_class_params *input); + +#endif /* _IPA_TSP_H_ */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_uc.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_uc.c new file mode 100644 index 0000000000..84e9a8a4ef --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_uc.c @@ -0,0 +1,2055 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ipa_i.h" +#include + +#define IPA_HW_INTERFACE_VERSION 0x2000 +#define IPA_PKT_FLUSH_TO_US 100 +#define IPA_UC_POLL_SLEEP_USEC 100 +#define IPA_UC_POLL_MAX_RETRY 10000 + +#define IPA_UC_DBG_STATS_GET_PROT_ID(x) (0xff & ((x) >> 24)) +#define IPA_UC_DBG_STATS_GET_OFFSET(x) (0x00ffffff & (x)) +#define IPA_UC_EVENT_RING_SIZE 10 +/** + * Mailbox register to Interrupt HWP for CPU cmd + * Usage of IPA_UC_MAILBOX_m_n doorbell instead of IPA_IRQ_EE_UC_0 + * due to HW limitation. + * + */ +#define IPA_CPU_2_HW_CMD_MBOX_m 0 +#define IPA_CPU_2_HW_CMD_MBOX_n 23 + +#define IPA_UC_ERING_m 0 +#define IPA_UC_ERING_n_r 1 +#define IPA_UC_ERING_n_w 0 +#define IPA_UC_MON_INTERVAL 5 +#define IPA_UC_HOLB_WORKQUEUE_NAME "ipa_uc_holb_wq" + +/** + * enum ipa3_cpu_2_hw_commands - Values that represent the commands from the CPU + * IPA_CPU_2_HW_CMD_NO_OP : No operation is required. + * IPA_CPU_2_HW_CMD_UPDATE_FLAGS : Update SW flags which defines the behavior + * of HW. + * IPA_CPU_2_HW_CMD_DEBUG_RUN_TEST : Launch predefined test over HW. + * IPA_CPU_2_HW_CMD_DEBUG_GET_INFO : Read HW internal debug information. + * IPA_CPU_2_HW_CMD_ERR_FATAL : CPU instructs HW to perform error fatal + * handling. + * IPA_CPU_2_HW_CMD_CLK_GATE : CPU instructs HW to goto Clock Gated state. + * IPA_CPU_2_HW_CMD_CLK_UNGATE : CPU instructs HW to goto Clock Ungated state. + * IPA_CPU_2_HW_CMD_MEMCPY : CPU instructs HW to do memcopy using QMB. + * IPA_CPU_2_HW_CMD_RESET_PIPE : Command to reset a pipe - SW WA for a HW bug. + * IPA_CPU_2_HW_CMD_GSI_CH_EMPTY : Command to check for GSI channel emptiness. + * IPA_CPU_2_HW_CMD_REMOTE_IPA_INFO: Command to store remote IPA Info + * IPA_CPU_2_HW_CMD_SETUP_EVENT_RING: Command to setup the event ring + * IPA_CPU_2_HW_CMD_ENABLE_FLOW_CTL_MONITOR: Command to enable pipe monitoring. + * IPA_CPU_2_HW_CMD_UPDATE_FLOW_CTL_MONITOR: Command to update pipes to monitor. + * IPA_CPU_2_HW_CMD_DISABLE_FLOW_CTL_MONITOR: Command to disable pipe + monitoring, no parameter required. + * IPA_CPU_2_HW_CMD_ENABLE_HOLB_MONITOR: Command to enable HOLB monitoring. + * IPA_CPU_2_HW_CMD_ADD_HOLB_MONITOR: Command to add GSI channel to HOLB + * monitor. + * IPA_CPU_2_HW_CMD_DEL_HOLB_MONITOR: Command to delete GSI channel to HOLB + * monitor. + * IPA_CPU_2_HW_CMD_DISABLE_HOLB_MONITOR: Command to disable HOLB monitoring. + * IPA_CPU_2_HW_CMD_ADD_EOGRE_MAPPING: Command to create/update GRE mapping + */ +enum ipa3_cpu_2_hw_commands { + IPA_CPU_2_HW_CMD_NO_OP = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_COMMON, 0), + IPA_CPU_2_HW_CMD_UPDATE_FLAGS = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_COMMON, 1), + IPA_CPU_2_HW_CMD_DEBUG_RUN_TEST = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_COMMON, 2), + IPA_CPU_2_HW_CMD_DEBUG_GET_INFO = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_COMMON, 3), + IPA_CPU_2_HW_CMD_ERR_FATAL = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_COMMON, 4), + IPA_CPU_2_HW_CMD_CLK_GATE = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_COMMON, 5), + IPA_CPU_2_HW_CMD_CLK_UNGATE = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_COMMON, 6), + IPA_CPU_2_HW_CMD_MEMCPY = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_COMMON, 7), + IPA_CPU_2_HW_CMD_RESET_PIPE = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_COMMON, 8), + IPA_CPU_2_HW_CMD_REG_WRITE = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_COMMON, 9), + IPA_CPU_2_HW_CMD_GSI_CH_EMPTY = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_COMMON, 10), + IPA_CPU_2_HW_CMD_REMOTE_IPA_INFO = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_COMMON, 11), + IPA_CPU_2_HW_CMD_SETUP_EVENT_RING = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_COMMON, 12), + IPA_CPU_2_HW_CMD_ENABLE_FLOW_CTL_MONITOR = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_COMMON, 13), + IPA_CPU_2_HW_CMD_UPDATE_FLOW_CTL_MONITOR = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_COMMON, 14), + IPA_CPU_2_HW_CMD_DISABLE_FLOW_CTL_MONITOR = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_COMMON, 15), + IPA_CPU_2_HW_CMD_ENABLE_HOLB_MONITOR = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_COMMON, 17), + IPA_CPU_2_HW_CMD_ADD_HOLB_MONITOR = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_COMMON, 18), + IPA_CPU_2_HW_CMD_DEL_HOLB_MONITOR = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_COMMON, 19), + IPA_CPU_2_HW_CMD_DISABLE_HOLB_MONITOR = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_COMMON, 20), + IPA_CPU_2_HW_CMD_ADD_EOGRE_MAPPING = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_COMMON, 21), +}; + +/** + * enum ipa3_hw_2_cpu_responses - Values that represent common HW responses + * to CPU commands. + * @IPA_HW_2_CPU_RESPONSE_NO_OP : No operation response + * @IPA_HW_2_CPU_RESPONSE_INIT_COMPLETED : HW shall send this command once + * boot sequence is completed and HW is ready to serve commands from CPU + * @IPA_HW_2_CPU_RESPONSE_CMD_COMPLETED: Response to CPU commands + * @IPA_HW_2_CPU_RESPONSE_DEBUG_GET_INFO : Response to + * IPA_CPU_2_HW_CMD_DEBUG_GET_INFO command + */ +enum ipa3_hw_2_cpu_responses { + IPA_HW_2_CPU_RESPONSE_NO_OP = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_COMMON, 0), + IPA_HW_2_CPU_RESPONSE_INIT_COMPLETED = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_COMMON, 1), + IPA_HW_2_CPU_RESPONSE_CMD_COMPLETED = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_COMMON, 2), + IPA_HW_2_CPU_RESPONSE_DEBUG_GET_INFO = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_COMMON, 3), +}; + +/** + * struct IpaHwMemCopyData_t - Structure holding the parameters + * for IPA_CPU_2_HW_CMD_MEMCPY command. + * + * The parameters are passed as immediate params in the shared memory + */ +struct IpaHwMemCopyData_t { + u32 destination_addr; + u32 source_addr; + u32 dest_buffer_size; + u32 source_buffer_size; +}; + +/** + * struct IpaHwRegWriteCmdData_t - holds the parameters for + * IPA_CPU_2_HW_CMD_REG_WRITE command. Parameters are + * sent as 64b immediate parameters. + * @RegisterAddress: RG10 register address where the value needs to be written + * @RegisterValue: 32-Bit value to be written into the register + */ +struct IpaHwRegWriteCmdData_t { + u32 RegisterAddress; + u32 RegisterValue; +}; + +/** + * union IpaHwCpuCmdCompletedResponseData_t - Structure holding the parameters + * for IPA_HW_2_CPU_RESPONSE_CMD_COMPLETED response. + * @originalCmdOp : The original command opcode + * @status : 0 for success indication, otherwise failure + * @responseData : 16b responseData + * + * Parameters are sent as 32b immediate parameters. + */ +union IpaHwCpuCmdCompletedResponseData_t { + struct IpaHwCpuCmdCompletedResponseParams_t { + #ifdef CONFIG_IPA_RTP + u32 originalCmdOp:16; + #else + u32 originalCmdOp:8; + #endif + u32 status:8; + #ifdef CONFIG_IPA_RTP + u32 responseData:8; + #else + u32 responseData:16; + #endif + } __packed params; + u32 raw32b; +} __packed; + +/** + * union IpaHwUpdateFlagsCmdData_t - Structure holding the parameters for + * IPA_CPU_2_HW_CMD_UPDATE_FLAGS command + * @newFlags: SW flags defined the behavior of HW. + * This field is expected to be used as bitmask for enum ipa3_hw_flags + */ +union IpaHwUpdateFlagsCmdData_t { + struct IpaHwUpdateFlagsCmdParams_t { + u32 newFlags; + } params; + u32 raw32b; +}; + +/** + * union IpaHwChkChEmptyCmdData_t - Structure holding the parameters for + * IPA_CPU_2_HW_CMD_GSI_CH_EMPTY command. Parameters are sent as 32b + * immediate parameters. + * @ee_n : EE owner of the channel + * @vir_ch_id : GSI virtual channel ID of the channel to checked of emptiness + * @reserved_02_04 : Reserved + */ +union IpaHwChkChEmptyCmdData_t { + struct IpaHwChkChEmptyCmdParams_t { + u8 ee_n; + u8 vir_ch_id; + u16 reserved_02_04; + } __packed params; + u32 raw32b; +} __packed; + +struct IpaSetupEventRingCmdParams_t { + u32 ring_base_pa; + u32 ring_base_pa_hi; + u32 ring_size; //size = 10 +} __packed; + + +/** + * Structure holding the parameters for + * IPA_CPU_2_HW_CMD_SETUP_EVENT_RING command. Parameters are + * sent as 32b immediate parameters. + */ +union IpaSetupEventRingCmdData_t { + struct IpaSetupEventRingCmdParams_t event; + u32 raw32b[6]; //uc-internal +} __packed; + + +/** + * Structure holding the parameters for IPA_CPU_2_HW_CMD_REMOTE_IPA_INFO + * command. + * @remoteIPAAddr: 5G IPA address : uC proxies Q6 doorbell to this address + * @mboxN: mbox on which Q6 will interrupt uC + */ +struct IpaHwDbAddrInfo_t { + u32 remoteIPAAddr; + uint32_t mboxN; +} __packed; + +/** + * When resource group 10 limitation mitigation is enabled, uC send + * cmd should be able to run in interrupt context, so using spin lock + * instead of mutex. + */ +#define IPA3_UC_LOCK(flags) \ +do { \ + if (ipa3_ctx->apply_rg10_wa) \ + spin_lock_irqsave(&ipa3_ctx->uc_ctx.uc_spinlock, flags); \ + else \ + mutex_lock(&ipa3_ctx->uc_ctx.uc_lock); \ +} while (0) + +#define IPA3_UC_UNLOCK(flags) \ +do { \ + if (ipa3_ctx->apply_rg10_wa) \ + spin_unlock_irqrestore(&ipa3_ctx->uc_ctx.uc_spinlock, flags); \ + else \ + mutex_unlock(&ipa3_ctx->uc_ctx.uc_lock); \ +} while (0) + + +/** + * Structure holding the parameters for IPA_CPU_2_HW_CMD_ENABLE_PIPE_MONITOR + * command. + * @ipaProdGsiChid IPA prod GSI chid to monitor + * @redMarkerThreshold red marker threshold in elements for the GSI channel + */ +union IpaEnablePipeMonitorCmdData_t { + struct IpaEnablePipeMonitorCmdParams_t { + u32 ipaProdGsiChid:16; + u32 redMarkerThreshold:16; + } __packed params; + u32 raw32b; +} __packed; + +/** + * Structure holding the parameters for IPA_CPU_2_HW_CMD_UPDATE_PIPE_MONITOR + * command. + * + * @bitmask The parameter of bitmask to add/delete channels/pipes from + * global monitoring pipemask + * IPA pipe# bitmask or GSI chid bitmask + * add_delete 1: add pipes to monitor + * 0: delete pipes to monitor + */ +struct IpaUpdateFlowCtlMonitorData_t { + u32 bitmask; + u8 add_delete; +}; + +/** + * @brief Structure holding the parameter for + * IPA_CPU_2_HW_CMD_ENABLE_HOLB_MONITOR command: HOLB + * monitor polling period in ms (expected range min: + * 5ms, max: 50ms) + */ +union IpaEnableHolbMonitorCmdData_t { + struct IpaEnableHolbMonitorParams_t { + uint32_t holbMonitorPollingPeriod; + } params; + uint32_t raw32b; +} __packed; + +/** + * @brief Structure holding the parameters for + * IPA_CPU_2_HW_CMD_ADD_HOLB_MONITOR command + * + * @param ipaProdGsiChid GSI chid to be HOLB monitored + * @param EE EE that the chid belongs to + * @param holbActionMask bit0: uC enables HOLB on + * corresponding pipe with timer = 0 + * bit1: Notify AP of bad chid + * bits can be set independently or + * together + * @param maxStuckSampleCnt Max stuck sample count before + * taking action + */ +union IpaAddHolbMonitorCmdData_t { + struct IpaAddHolbMonitorParams_t { + uint32_t ipaProdGsiChid :8; + uint32_t EE :8; + uint32_t holbActionMask :8; + uint32_t maxStuckSampleCnt :8; + } __packed params; + uint32_t raw32b; +} __packed; + +/** + * @brief Structure holding the parameters for + * IPA_CPU_2_HW_CMD_DEL_HOLB_MONITOR command. + * + * @param ipaProdGsiChid GSI chid to be removed from HOLB + * monitoring + * @param EE EE that the chid belongs to + */ +union IpaDelHolbMonitorCmdData_t { + struct IpaDelHolbMonitorParams_t { + uint32_t ipaProdGsiChid :8; + uint32_t EE :8; + uint32_t reserved :16; + } __packed params; + uint32_t raw32b; +} __packed; + +static DEFINE_MUTEX(uc_loaded_nb_lock); +static BLOCKING_NOTIFIER_HEAD(uc_loaded_notifier); + +static struct workqueue_struct *ipa_uc_holb_wq; +struct ipa3_uc_hdlrs ipa3_uc_hdlrs[IPA_HW_NUM_FEATURES] = { { 0 } }; + +const char *ipa_hw_error_str(enum ipa3_hw_errors err_type) +{ + const char *str; + + switch (err_type) { + case IPA_HW_ERROR_NONE: + str = "IPA_HW_ERROR_NONE"; + break; + case IPA_HW_INVALID_DOORBELL_ERROR: + str = "IPA_HW_INVALID_DOORBELL_ERROR"; + break; + case IPA_HW_DMA_ERROR: + str = "IPA_HW_DMA_ERROR"; + break; + case IPA_HW_FATAL_SYSTEM_ERROR: + str = "IPA_HW_FATAL_SYSTEM_ERROR"; + break; + case IPA_HW_INVALID_OPCODE: + str = "IPA_HW_INVALID_OPCODE"; + break; + case IPA_HW_INVALID_PARAMS: + str = "IPA_HW_INVALID_PARAMS"; + break; + case IPA_HW_CONS_DISABLE_CMD_GSI_STOP_FAILURE: + str = "IPA_HW_CONS_DISABLE_CMD_GSI_STOP_FAILURE"; + break; + case IPA_HW_PROD_DISABLE_CMD_GSI_STOP_FAILURE: + str = "IPA_HW_PROD_DISABLE_CMD_GSI_STOP_FAILURE"; + break; + case IPA_HW_GSI_CH_NOT_EMPTY_FAILURE: + str = "IPA_HW_GSI_CH_NOT_EMPTY_FAILURE"; + break; + default: + str = "INVALID ipa_hw_errors type"; + } + + return str; +} + +static void ipa3_deferred_holb_work(struct work_struct *work) +{ + + int res; + u32 poll_period = ipa3_ctx->uc_ctx.holb_monitor.poll_period; + + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + res = ipa3_uc_enable_holb_monitor(poll_period); + if (res) { + IPAERR("Failed to enable HOLB monitoring %d\n", res); + goto fail_holb_enable; + } + if (!ipa3_ctx->uc_ctx.uc_event_ring_valid) { + if (ipa3_uc_setup_event_ring()) { + IPAERR("failed to set uc event ring\n"); + goto fail_holb_enable; + } + } + + if (ipa3_uc_hdlrs[IPA_HW_FEATURE_COMMON].ipa_uc_holb_enabled_hdlr) + ipa3_uc_hdlrs[IPA_HW_FEATURE_COMMON].ipa_uc_holb_enabled_hdlr(); + + +fail_holb_enable: + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); +} +DECLARE_WORK(ipa3_holb_enabled_work, ipa3_deferred_holb_work); + +static void ipa3_uc_save_dbg_stats(u32 size) +{ + u8 prot_id; + u32 addr_offset; + void __iomem *mmio; + + prot_id = IPA_UC_DBG_STATS_GET_PROT_ID( + ipa3_ctx->uc_ctx.uc_sram_mmio->responseParams_1); + addr_offset = IPA_UC_DBG_STATS_GET_OFFSET( + ipa3_ctx->uc_ctx.uc_sram_mmio->responseParams_1); + mmio = ioremap(ipa3_ctx->ipa_wrapper_base + + addr_offset, sizeof(struct IpaHwRingStats_t) * + MAX_CH_STATS_SUPPORTED); + if (mmio == NULL) { + IPAERR("unexpected NULL mmio\n"); + return; + } + switch (prot_id) { + case IPA_HW_PROTOCOL_AQC: + if (!ipa3_ctx->aqc_ctx.dbg_stats.uc_dbg_stats_mmio) { + ipa3_ctx->aqc_ctx.dbg_stats.uc_dbg_stats_size = + size; + ipa3_ctx->aqc_ctx.dbg_stats.uc_dbg_stats_ofst = + addr_offset; + ipa3_ctx->aqc_ctx.dbg_stats.uc_dbg_stats_mmio = + mmio; + } else + goto unmap; + break; + case IPA_HW_PROTOCOL_RTK: + if (!ipa3_ctx->rtk_ctx.dbg_stats.uc_dbg_stats_mmio) { + ipa3_ctx->rtk_ctx.dbg_stats.uc_dbg_stats_size = + size; + ipa3_ctx->rtk_ctx.dbg_stats.uc_dbg_stats_ofst = + addr_offset; + ipa3_ctx->rtk_ctx.dbg_stats.uc_dbg_stats_mmio = + mmio; + } else + goto unmap; + break; + case IPA_HW_PROTOCOL_NTN3: + if (!ipa3_ctx->ntn_ctx.dbg_stats.uc_dbg_stats_mmio) { + ipa3_ctx->ntn_ctx.dbg_stats.uc_dbg_stats_size = + size; + ipa3_ctx->ntn_ctx.dbg_stats.uc_dbg_stats_ofst = + addr_offset; + ipa3_ctx->ntn_ctx.dbg_stats.uc_dbg_stats_mmio = + mmio; + } else + goto unmap; + break; + case IPA_HW_PROTOCOL_WDI: + if (!ipa3_ctx->wdi2_ctx.dbg_stats.uc_dbg_stats_mmio) { + ipa3_ctx->wdi2_ctx.dbg_stats.uc_dbg_stats_size = + size; + ipa3_ctx->wdi2_ctx.dbg_stats.uc_dbg_stats_ofst = + addr_offset; + ipa3_ctx->wdi2_ctx.dbg_stats.uc_dbg_stats_mmio = + mmio; + } else + goto unmap; + break; + case IPA_HW_PROTOCOL_WDI3: + if (!ipa3_ctx->wdi3_ctx.dbg_stats.uc_dbg_stats_mmio) { + ipa3_ctx->wdi3_ctx.dbg_stats.uc_dbg_stats_size = + size; + ipa3_ctx->wdi3_ctx.dbg_stats.uc_dbg_stats_ofst = + addr_offset; + ipa3_ctx->wdi3_ctx.dbg_stats.uc_dbg_stats_mmio = + mmio; + } else + goto unmap; + break; + case IPA_HW_PROTOCOL_MHIP: + if (!ipa3_ctx->mhip_ctx.dbg_stats.uc_dbg_stats_mmio) { + ipa3_ctx->mhip_ctx.dbg_stats.uc_dbg_stats_size = + size; + ipa3_ctx->mhip_ctx.dbg_stats.uc_dbg_stats_ofst = + addr_offset; + ipa3_ctx->mhip_ctx.dbg_stats.uc_dbg_stats_mmio = + mmio; + } else + goto unmap; + break; + case IPA_HW_PROTOCOL_USB: + if (!ipa3_ctx->usb_ctx.dbg_stats.uc_dbg_stats_mmio) { + ipa3_ctx->usb_ctx.dbg_stats.uc_dbg_stats_size = + size; + ipa3_ctx->usb_ctx.dbg_stats.uc_dbg_stats_ofst = + addr_offset; + ipa3_ctx->usb_ctx.dbg_stats.uc_dbg_stats_mmio = + mmio; + } else + goto unmap; + break; + default: + IPAERR("unknown protocols %d\n", prot_id); + goto unmap; + } + return; +unmap: + iounmap(mmio); +} + +static void ipa3_log_evt_hdlr(void) +{ + int i; + + if (!ipa3_ctx->uc_ctx.uc_event_top_ofst) { + ipa3_ctx->uc_ctx.uc_event_top_ofst = + ipa3_ctx->uc_ctx.uc_sram_mmio->eventParams; + if (ipa3_ctx->uc_ctx.uc_event_top_ofst + + sizeof(struct IpaHwEventLogInfoData_t) >= + ipa3_ctx->ctrl->ipa_reg_base_ofst + + ipahal_get_reg_n_ofst( + IPA_SW_AREA_RAM_DIRECT_ACCESS_n, 0) + + ipa3_ctx->smem_sz) { + IPAERR("uc_top 0x%x outside SRAM\n", + ipa3_ctx->uc_ctx.uc_event_top_ofst); + goto bad_uc_top_ofst; + } + + ipa3_ctx->uc_ctx.uc_event_top_mmio = ioremap( + ipa3_ctx->ipa_wrapper_base + + ipa3_ctx->uc_ctx.uc_event_top_ofst, + sizeof(struct IpaHwEventLogInfoData_t)); + if (!ipa3_ctx->uc_ctx.uc_event_top_mmio) { + IPAERR("fail to ioremap uc top\n"); + goto bad_uc_top_ofst; + } + + for (i = 0; i < IPA_HW_NUM_FEATURES; i++) { + if (ipa3_uc_hdlrs[i].ipa_uc_event_log_info_hdlr) + ipa3_uc_hdlrs[i].ipa_uc_event_log_info_hdlr + (ipa3_ctx->uc_ctx.uc_event_top_mmio); + } + } else { + + if (ipa3_ctx->uc_ctx.uc_sram_mmio->eventParams != + ipa3_ctx->uc_ctx.uc_event_top_ofst) { + IPAERR("uc top ofst changed new=%u cur=%u\n", + ipa3_ctx->uc_ctx.uc_sram_mmio->eventParams, + ipa3_ctx->uc_ctx.uc_event_top_ofst); + } + } + + return; + +bad_uc_top_ofst: + ipa3_ctx->uc_ctx.uc_event_top_ofst = 0; +} + +static void ipa3_event_ring_hdlr(void) +{ + u32 ering_rp, offset; + void *rp_va; + struct ipa_inform_wlan_bw bw_info; + struct eventElement_t *e_b = NULL, *e_q = NULL, *e_h = NULL; + int mul = 0; + + ering_rp = ipahal_read_reg_mn(IPA_UC_MAILBOX_m_n, + IPA_UC_ERING_m, IPA_UC_ERING_n_r); + offset = sizeof(struct eventElement_t); + ipa3_ctx->uc_ctx.ering_rp = ering_rp; + + while (ipa3_ctx->uc_ctx.ering_rp_local != ering_rp) { + rp_va = ipa3_ctx->uc_ctx.event_ring.base + + ipa3_ctx->uc_ctx.ering_rp_local; + + if (((struct eventElement_t *) rp_va)->Opcode == BW_NOTIFY) { + e_b = ((struct eventElement_t *) rp_va); + IPADBG("prot(%d), index (%d) throughput (%lu)\n", + e_b->Protocol, + e_b->Value.bw_param.ThresholdIndex, + e_b->Value.bw_param.throughput); + + memset(&bw_info, 0, sizeof(struct ipa_inform_wlan_bw)); + bw_info.index = + e_b->Value.bw_param.ThresholdIndex; + mul = 1000 / IPA_UC_MON_INTERVAL; + bw_info.throughput = + e_b->Value.bw_param.throughput*mul; + if (ipa3_inform_wlan_bw(&bw_info)) + IPAERR_RL("failed on index %d to wlan\n", + bw_info.index); + } else if (((struct eventElement_t *) rp_va)->Opcode + == QUOTA_NOTIFY) { + e_q = ((struct eventElement_t *) rp_va); + IPADBG("got quota-notify %d reach(%d) usage (%lu)\n", + e_q->Protocol, + e_q->Value.quota_param.ThreasholdReached, + e_q->Value.quota_param.usage); + if (ipa_broadcast_wdi_quota_reach_ind(0, + e_q->Value.quota_param.usage)) + IPAERR_RL("failed on quota_reach for %d\n", + e_q->Protocol); + } else if (((struct eventElement_t *) rp_va)->Opcode + == IPA_HOLB_BAD_PERIPHERAL_EVENT) { + e_h = ((struct eventElement_t *) rp_va); + IPAERR("Bad Periph for Chan %d QTimer %u %u\n", + e_h->Value.holb_notify_param.ipaProdGsiChid, + e_h->Value.holb_notify_param.qTimerMSB, + e_h->Value.holb_notify_param.qTimerLSB); + ipa3_uc_holb_event_log( + e_h->Value.holb_notify_param.ipaProdGsiChid, + true, + e_h->Value.holb_notify_param.qTimerLSB, + e_h->Value.holb_notify_param.qTimerMSB); + } else if (((struct eventElement_t *) rp_va)->Opcode + == IPA_HOLB_PERIPHERAL_RECOVERED_EVENT) { + e_h = ((struct eventElement_t *) rp_va); + IPAERR("Recovered Periph Chan %d QTimer %u %u\n", + e_h->Value.holb_notify_param.ipaProdGsiChid, + e_h->Value.holb_notify_param.qTimerMSB, + e_h->Value.holb_notify_param.qTimerLSB); + ipa3_uc_holb_event_log( + e_h->Value.holb_notify_param.ipaProdGsiChid, + false, + e_h->Value.holb_notify_param.qTimerLSB, + e_h->Value.holb_notify_param.qTimerMSB); + } + ipa3_ctx->uc_ctx.ering_rp_local += offset; + ipa3_ctx->uc_ctx.ering_rp_local %= + ipa3_ctx->uc_ctx.event_ring.size; + /* update wp */ + ipa3_ctx->uc_ctx.ering_wp_local += offset; + ipa3_ctx->uc_ctx.ering_wp_local %= + ipa3_ctx->uc_ctx.event_ring.size; + ipahal_write_reg_mn(IPA_UC_MAILBOX_m_n, IPA_UC_ERING_m, + IPA_UC_ERING_n_w, ipa3_ctx->uc_ctx.ering_wp_local); + } +} + +/** + * ipa3_uc_state_check() - Check the status of the uC interface + * + * Return value: 0 if the uC is loaded, interface is initialized + * and there was no recent failure in one of the commands. + * A negative value is returned otherwise. + */ +int ipa3_uc_state_check(void) +{ + if (!ipa3_ctx->uc_ctx.uc_inited) { + IPAERR("uC interface not initialized\n"); + return -EFAULT; + } + + if (!ipa3_ctx->uc_ctx.uc_loaded) { + IPAERR("uC is not loaded\n"); + return -EFAULT; + } + + if (ipa3_ctx->uc_ctx.uc_failed) { + IPAERR("uC has failed its last command\n"); + return -EFAULT; + } + + return 0; +} +EXPORT_SYMBOL(ipa3_uc_state_check); + +/** + * ipa3_uc_loaded_check() - Check the uC has been loaded + * + * Return value: 1 if the uC is loaded, 0 otherwise + */ +int ipa3_uc_loaded_check(void) +{ + return ipa3_ctx->uc_ctx.uc_loaded; +} +EXPORT_SYMBOL(ipa3_uc_loaded_check); + +/** + * ipa3_uc_holb_enabled_check() - Check the uC has been loaded + * + * Return value: 1 if the uC is loaded, 0 otherwise + */ +int ipa3_uc_holb_enabled_check(void) +{ + return ipa3_ctx->uc_ctx.uc_holb_enabled; +} +EXPORT_SYMBOL(ipa3_uc_holb_enabled_check); + +/** + * ipa3_uc_register_ready_cb() - register a uC ready callback notifier block + * @nb: notifier + * + * Register a callback to be called when uC is ready to receive commands. uC is + * considered to be ready when it sends %IPA_HW_2_CPU_RESPONSE_INIT_COMPLETED. + * + * Return: 0 on successful registration, negative errno otherwise + * + * See blocking_notifier_chain_register() for possible errno values + */ +int ipa3_uc_register_ready_cb(struct notifier_block *nb) +{ + int rc; + + mutex_lock(&uc_loaded_nb_lock); + + rc = blocking_notifier_chain_register(&uc_loaded_notifier, nb); + if (!rc && ipa3_ctx->uc_ctx.uc_loaded) + (void) nb->notifier_call(nb, false, ipa3_ctx); + + mutex_unlock(&uc_loaded_nb_lock); + + return rc; +} +EXPORT_SYMBOL(ipa3_uc_register_ready_cb); + +/** + * ipa3_uc_unregister_ready_cb() - unregister a uC ready callback + * @nb: notifier + * + * Unregister a uC loaded notifier block that was previously registered by + * ipa3_uc_register_ready_cb(). + * + * Return: 0 on successful unregistration, negative errno otherwise + * + * See blocking_notifier_chain_unregister() for possible errno values + */ +int ipa3_uc_unregister_ready_cb(struct notifier_block *nb) +{ + return blocking_notifier_chain_unregister(&uc_loaded_notifier, nb); +} +EXPORT_SYMBOL(ipa3_uc_unregister_ready_cb); + +static void ipa3_uc_event_handler(enum ipa_irq_type interrupt, + void *private_data, + void *interrupt_data) +{ + union IpaHwErrorEventData_t evt; + u8 feature; + + WARN_ON(private_data != ipa3_ctx); + + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + + IPADBG("uC evt opcode=%u\n", + ipa3_ctx->uc_ctx.uc_sram_mmio->eventOp); + + + feature = EXTRACT_UC_FEATURE(ipa3_ctx->uc_ctx.uc_sram_mmio->eventOp); + + if (feature >= IPA_HW_FEATURE_MAX) { + IPAERR("Invalid feature %u for event %u\n", + feature, ipa3_ctx->uc_ctx.uc_sram_mmio->eventOp); + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + return; + } + /* Feature specific handling */ + if (ipa3_uc_hdlrs[feature].ipa_uc_event_hdlr) + ipa3_uc_hdlrs[feature].ipa_uc_event_hdlr + (ipa3_ctx->uc_ctx.uc_sram_mmio); + + /* General handling */ + if (ipa3_ctx->uc_ctx.uc_sram_mmio->eventOp == + IPA_HW_2_CPU_EVENT_ERROR) { + evt.raw32b = ipa3_ctx->uc_ctx.uc_sram_mmio->eventParams; + IPAERR("uC Error, evt errorType = %s\n", + ipa_hw_error_str(evt.params.errorType)); + ipa3_ctx->uc_ctx.uc_failed = true; + ipa3_ctx->uc_ctx.uc_error_type = evt.params.errorType; + ipa3_ctx->uc_ctx.uc_error_timestamp = + ipahal_read_reg(IPA_TAG_TIMER); + /* Unexpected UC hardware state */ + ipa_assert(); + } else if (ipa3_ctx->uc_ctx.uc_sram_mmio->eventOp == + IPA_HW_2_CPU_EVENT_LOG_INFO) { + IPADBG("uC evt log info ofst=0x%x\n", + ipa3_ctx->uc_ctx.uc_sram_mmio->eventParams); + ipa3_log_evt_hdlr(); + } else if (ipa3_ctx->uc_ctx.uc_sram_mmio->eventOp == + IPA_HW_2_CPU_EVNT_RING_NOTIFY) { + IPADBG("uC evt log info ofst=0x%x\n", + ipa3_ctx->uc_ctx.uc_sram_mmio->eventParams); + ipa3_event_ring_hdlr(); + } else { + IPADBG("unsupported uC evt opcode=%u\n", + ipa3_ctx->uc_ctx.uc_sram_mmio->eventOp); + } + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + +} + +int ipa3_uc_panic_notifier(struct notifier_block *this, + unsigned long event, void *ptr) +{ + int result = 0; + struct ipa_active_client_logging_info log_info; + + IPADBG("this=%pK evt=%lu ptr=%pK\n", this, event, ptr); + + result = ipa3_uc_state_check(); + if (result) + goto fail; + + IPA_ACTIVE_CLIENTS_PREP_SIMPLE(log_info); + if (ipa3_inc_client_enable_clks_no_block(&log_info)) + goto fail; + + ipa3_ctx->uc_ctx.uc_sram_mmio->cmdOp = + IPA_CPU_2_HW_CMD_ERR_FATAL; + ipa3_ctx->uc_ctx.pending_cmd = ipa3_ctx->uc_ctx.uc_sram_mmio->cmdOp; + /* ensure write to shared memory is done before triggering uc */ + wmb(); + + if (ipa3_ctx->apply_rg10_wa) + ipahal_write_reg_mn(IPA_UC_MAILBOX_m_n, + IPA_CPU_2_HW_CMD_MBOX_m, + IPA_CPU_2_HW_CMD_MBOX_n, 0x1); + else + ipahal_write_reg_n(IPA_IRQ_EE_UC_n, 0, 0x1); + + /* give uc enough time to save state */ + udelay(IPA_PKT_FLUSH_TO_US); + + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + IPADBG("err_fatal issued\n"); + +fail: + return NOTIFY_DONE; +} + +static void ipa3_uc_response_hdlr(enum ipa_irq_type interrupt, + void *private_data, + void *interrupt_data) +{ + union IpaHwCpuCmdCompletedResponseData_t uc_rsp; + u8 feature; + int res; + int i; + + WARN_ON(private_data != ipa3_ctx); + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + IPADBG("uC rsp opcode=%u\n", + ipa3_ctx->uc_ctx.uc_sram_mmio->responseOp); + + feature = EXTRACT_UC_FEATURE(ipa3_ctx->uc_ctx.uc_sram_mmio->responseOp); + + if (feature >= IPA_HW_FEATURE_MAX) { + IPAERR("Invalid feature %u for event %u\n", + feature, ipa3_ctx->uc_ctx.uc_sram_mmio->eventOp); + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + return; + } + + /* Feature specific handling */ + if (ipa3_uc_hdlrs[feature].ipa3_uc_response_hdlr) { + res = ipa3_uc_hdlrs[feature].ipa3_uc_response_hdlr( + ipa3_ctx->uc_ctx.uc_sram_mmio, + &ipa3_ctx->uc_ctx.uc_status); + if (res == 0) { + IPADBG("feature %d specific response handler\n", + feature); + complete_all(&ipa3_ctx->uc_ctx.uc_completion); + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + return; + } + } + + /* General handling */ + if (ipa3_ctx->uc_ctx.uc_sram_mmio->responseOp == + IPA_HW_2_CPU_RESPONSE_INIT_COMPLETED) { + + if (ipa3_ctx->uc_ctx.uc_loaded) { + IPADBG("uC resp op INIT_COMPLETED is unexpected\n"); + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + return; + } + + mutex_lock(&uc_loaded_nb_lock); + + ipa3_ctx->uc_ctx.uc_loaded = true; + + if (ipa3_ctx->uc_ctx.ipa_use_uc_holb_monitor) + queue_work(ipa_uc_holb_wq, &ipa3_holb_enabled_work); + + (void) blocking_notifier_call_chain(&uc_loaded_notifier, true, + ipa3_ctx); + + mutex_unlock(&uc_loaded_nb_lock); + + IPADBG("IPA uC loaded\n"); + /* + * The proxy vote is held until uC is loaded to ensure that + * IPA_HW_2_CPU_RESPONSE_INIT_COMPLETED is received. + */ + ipa3_proxy_clk_unvote(); + + /* + * To enable ipa power collapse we need to enable rpmh and uc + * handshake So that uc can do register retention. To enable + * this handshake we need to send the below message to rpmh. + */ + ipa_pc_qmp_enable(); + + for (i = 0; i < IPA_HW_NUM_FEATURES; i++) { + if (ipa3_uc_hdlrs[i].ipa_uc_loaded_hdlr) + ipa3_uc_hdlrs[i].ipa_uc_loaded_hdlr(); + } + } else if (ipa3_ctx->uc_ctx.uc_sram_mmio->responseOp == + IPA_HW_2_CPU_RESPONSE_CMD_COMPLETED) { + uc_rsp.raw32b = ipa3_ctx->uc_ctx.uc_sram_mmio->responseParams; + IPADBG("uC cmd response opcode=%u status=%u\n", + uc_rsp.params.originalCmdOp, + uc_rsp.params.status); + if (uc_rsp.params.originalCmdOp == + ipa3_ctx->uc_ctx.pending_cmd) { + ipa3_ctx->uc_ctx.uc_status = uc_rsp.params.status; + if (uc_rsp.params.originalCmdOp == + IPA_CPU_2_HW_CMD_OFFLOAD_STATS_ALLOC) + ipa3_uc_save_dbg_stats( + uc_rsp.params.responseData); + complete_all(&ipa3_ctx->uc_ctx.uc_completion); + } else { + IPAERR("Expected cmd=%u rcvd cmd=%u\n", + ipa3_ctx->uc_ctx.pending_cmd, + uc_rsp.params.originalCmdOp); + } + } else { + IPAERR("Unsupported uC rsp opcode = %u\n", + ipa3_ctx->uc_ctx.uc_sram_mmio->responseOp); + } + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + +} + +static void ipa3_uc_wigig_misc_int_handler(enum ipa_irq_type interrupt, + void *private_data, + void *interrupt_data) +{ + IPADBG("\n"); + + WARN_ON(private_data != ipa3_ctx); + + if (ipa3_ctx->uc_wigig_ctx.misc_notify_cb) + ipa3_ctx->uc_wigig_ctx.misc_notify_cb( + ipa3_ctx->uc_wigig_ctx.priv); + + IPADBG("exit\n"); +} + +static int ipa3_uc_send_cmd_64b_param(u32 cmd_lo, u32 cmd_hi, u32 opcode, + u32 expected_status, bool polling_mode, unsigned long timeout_jiffies) +{ + int index; + union IpaHwCpuCmdCompletedResponseData_t uc_rsp; + unsigned long flags = 0; + int retries = 0; + u32 uc_error_type; + +send_cmd_lock: + IPA3_UC_LOCK(flags); + + if (ipa3_uc_state_check()) { + IPADBG("uC send command aborted\n"); + IPA3_UC_UNLOCK(flags); + return -EBADF; + } +send_cmd: + if (ipa3_ctx->apply_rg10_wa) { + if (!polling_mode) + IPADBG("Overriding mode to polling mode\n"); + polling_mode = true; + } else { + init_completion(&ipa3_ctx->uc_ctx.uc_completion); + } + + ipa3_ctx->uc_ctx.uc_sram_mmio->cmdParams = cmd_lo; + ipa3_ctx->uc_ctx.uc_sram_mmio->cmdParams_hi = cmd_hi; + ipa3_ctx->uc_ctx.uc_sram_mmio->cmdOp = opcode; + ipa3_ctx->uc_ctx.pending_cmd = opcode; + ipa3_ctx->uc_ctx.uc_sram_mmio->responseOp = 0; + ipa3_ctx->uc_ctx.uc_sram_mmio->responseParams = 0; + + ipa3_ctx->uc_ctx.uc_status = 0; + + /* ensure write to shared memory is done before triggering uc */ + wmb(); + if (ipa3_ctx->apply_rg10_wa) + ipahal_write_reg_mn(IPA_UC_MAILBOX_m_n, + IPA_CPU_2_HW_CMD_MBOX_m, + IPA_CPU_2_HW_CMD_MBOX_n, 0x1); + else + ipahal_write_reg_n(IPA_IRQ_EE_UC_n, 0, 0x1); + + if (polling_mode) { + struct IpaHwSharedMemCommonMapping_t *uc_sram_ptr = + ipa3_ctx->uc_ctx.uc_sram_mmio; + for (index = 0; index < IPA_UC_POLL_MAX_RETRY; index++) { + if (uc_sram_ptr->responseOp == + IPA_HW_2_CPU_RESPONSE_CMD_COMPLETED) { + uc_rsp.raw32b = uc_sram_ptr->responseParams; + if (uc_rsp.params.originalCmdOp == + ipa3_ctx->uc_ctx.pending_cmd) { + ipa3_ctx->uc_ctx.uc_status = + uc_rsp.params.status; + break; + } + } + if (ipa3_ctx->apply_rg10_wa) + udelay(IPA_UC_POLL_SLEEP_USEC); + else + usleep_range(IPA_UC_POLL_SLEEP_USEC, + IPA_UC_POLL_SLEEP_USEC); + } + + if (index == IPA_UC_POLL_MAX_RETRY) { + IPAERR("uC max polling retries reached\n"); + if (ipa3_ctx->uc_ctx.uc_failed) { + uc_error_type = ipa3_ctx->uc_ctx.uc_error_type; + IPAERR("uC reported on Error, errorType = %s\n", + ipa_hw_error_str(uc_error_type)); + } + IPA3_UC_UNLOCK(flags); + /* Unexpected UC hardware state */ + ipa_assert(); + } + } else { + if (wait_for_completion_timeout(&ipa3_ctx->uc_ctx.uc_completion, + timeout_jiffies) == 0) { + IPAERR("uC timed out\n"); + if (ipa3_ctx->uc_ctx.uc_failed) { + uc_error_type = ipa3_ctx->uc_ctx.uc_error_type; + IPAERR("uC reported on Error, errorType = %s\n", + ipa_hw_error_str(uc_error_type)); + } + IPA3_UC_UNLOCK(flags); + /* Unexpected UC hardware state */ + ipa_assert(); + } + } + + if (ipa3_ctx->uc_ctx.uc_status != expected_status) { + if (ipa3_ctx->uc_ctx.uc_status == + IPA_HW_PROD_DISABLE_CMD_GSI_STOP_FAILURE || + ipa3_ctx->uc_ctx.uc_status == + IPA_HW_CONS_DISABLE_CMD_GSI_STOP_FAILURE || + ipa3_ctx->uc_ctx.uc_status == + IPA_HW_CONS_STOP_FAILURE || + ipa3_ctx->uc_ctx.uc_status == + IPA_HW_PROD_STOP_FAILURE) { + retries++; + if (retries == IPA_GSI_CHANNEL_STOP_MAX_RETRY) { + IPAERR("Failed after %d tries\n", retries); + IPA3_UC_UNLOCK(flags); + /* Unexpected UC hardware state */ + ipa_assert(); + } + IPA3_UC_UNLOCK(flags); + if (ipa3_ctx->uc_ctx.uc_status == + IPA_HW_PROD_DISABLE_CMD_GSI_STOP_FAILURE) + ipa3_inject_dma_task_for_gsi(); + /* sleep for short period to flush IPA */ + usleep_range(IPA_GSI_CHANNEL_STOP_SLEEP_MIN_USEC, + IPA_GSI_CHANNEL_STOP_SLEEP_MAX_USEC); + goto send_cmd_lock; + } + + if (ipa3_ctx->uc_ctx.uc_status == + IPA_HW_GSI_CH_NOT_EMPTY_FAILURE) { + retries++; + if (retries >= IPA_GSI_CHANNEL_EMPTY_MAX_RETRY) { + IPAERR("Failed after %d tries\n", retries); + IPA3_UC_UNLOCK(flags); + return -EFAULT; + } + if (ipa3_ctx->apply_rg10_wa) + udelay( + IPA_GSI_CHANNEL_EMPTY_SLEEP_MAX_USEC / 2 + + IPA_GSI_CHANNEL_EMPTY_SLEEP_MIN_USEC / 2); + else + usleep_range( + IPA_GSI_CHANNEL_EMPTY_SLEEP_MIN_USEC, + IPA_GSI_CHANNEL_EMPTY_SLEEP_MAX_USEC); + goto send_cmd; + } + + IPAERR("uC cmd(%u): Received status %u, Expected status %u\n", + opcode, ipa3_ctx->uc_ctx.uc_status, expected_status); + IPA3_UC_UNLOCK(flags); + return -EFAULT; + } + + IPA3_UC_UNLOCK(flags); + + IPADBG("uC cmd %u send succeeded\n", opcode); + + return 0; +} + +/** + * ipa3_uc_interface_init() - Initialize the interface with the uC + * + * Return value: 0 on success, negative value otherwise + */ +int ipa3_uc_interface_init(void) +{ + int result; + unsigned long phys_addr; + + if (ipa3_ctx->uc_ctx.uc_inited) { + IPADBG("uC interface already initialized\n"); + return 0; + } + + mutex_init(&ipa3_ctx->uc_ctx.uc_lock); + mutex_init(&ipa3_ctx->uc_ctx.holb_monitor.uc_holb_lock); + spin_lock_init(&ipa3_ctx->uc_ctx.uc_spinlock); + + phys_addr = ipa3_ctx->ipa_wrapper_base + + ipa3_ctx->ctrl->ipa_reg_base_ofst + + ipahal_get_reg_n_ofst(IPA_SW_AREA_RAM_DIRECT_ACCESS_n, 0) + + IPA_MEM_PART(uc_ofst); + ipa3_ctx->uc_ctx.uc_sram_mmio = ioremap(phys_addr, + IPA_MEM_PART(uc_size)); + if (!ipa3_ctx->uc_ctx.uc_sram_mmio) { + IPAERR("Fail to ioremap IPA uC SRAM\n"); + result = -ENOMEM; + goto remap_fail; + } + + if (!ipa3_ctx->apply_rg10_wa) { + result = ipa_add_interrupt_handler(IPA_UC_IRQ_0, + ipa3_uc_event_handler, true, + ipa3_ctx); + if (result) { + IPAERR("Fail to register for UC_IRQ0 event interrupt\n"); + result = -EFAULT; + goto irq_fail0; + } + + result = ipa_add_interrupt_handler(IPA_UC_IRQ_1, + ipa3_uc_response_hdlr, true, + ipa3_ctx); + if (result) { + IPAERR("fail to register for UC_IRQ1 rsp interrupt\n"); + result = -EFAULT; + goto irq_fail1; + } + + result = ipa_add_interrupt_handler(IPA_UC_IRQ_2, + ipa3_uc_wigig_misc_int_handler, true, + ipa3_ctx); + if (result) { + IPAERR("fail to register for UC_IRQ2 wigig misc interrupt\n"); + result = -EFAULT; + goto irq_fail2; + } + + if (ipa3_ctx->uc_ctx.ipa_use_uc_holb_monitor) { + ipa_uc_holb_wq = alloc_workqueue(IPA_UC_HOLB_WORKQUEUE_NAME, + WQ_MEM_RECLAIM | WQ_UNBOUND | WQ_SYSFS, 1); + + if (!ipa_uc_holb_wq) { + IPAERR("Failed to create ipa_uc_holb_wq\n"); + result = -EFAULT; + goto irq_fail3; + } + } + } + + ipa3_ctx->uc_ctx.uc_inited = true; + + IPADBG("IPA uC interface is initialized\n"); + return 0; + +irq_fail3: + ipa3_remove_interrupt_handler(IPA_UC_IRQ_2); +irq_fail2: + ipa3_remove_interrupt_handler(IPA_UC_IRQ_1); +irq_fail1: + ipa3_remove_interrupt_handler(IPA_UC_IRQ_0); +irq_fail0: + iounmap(ipa3_ctx->uc_ctx.uc_sram_mmio); +remap_fail: + return result; +} + + +/** + * ipa3_uc_load_notify() - Notification about uC loading + * + * This function should be called when IPA uC interface layer cannot + * determine by itself about uC loading by waits for external notification. + * Example is resource group 10 limitation were ipa driver does not get uC + * interrupts. + * The function should perform actions that were not done at init due to uC + * not being loaded then. + */ +void ipa3_uc_load_notify(void) +{ + int i; + int result; + + if (!ipa3_ctx->apply_rg10_wa) + return; + + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + ipa3_ctx->uc_ctx.uc_loaded = true; + IPADBG("IPA uC loaded\n"); + + ipa3_proxy_clk_unvote(); + + ipa3_init_interrupts(); + + result = ipa_add_interrupt_handler(IPA_UC_IRQ_0, + ipa3_uc_event_handler, true, + ipa3_ctx); + if (result) + IPAERR("Fail to register for UC_IRQ0 rsp interrupt.\n"); + + for (i = 0; i < IPA_HW_NUM_FEATURES; i++) { + if (ipa3_uc_hdlrs[i].ipa_uc_loaded_hdlr) + ipa3_uc_hdlrs[i].ipa_uc_loaded_hdlr(); + } + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); +} +EXPORT_SYMBOL(ipa3_uc_load_notify); + +void ipa3_uc_interface_destroy(void) +{ + if(ipa3_ctx->uc_ctx.uc_inited) { + ipa3_remove_interrupt_handler(IPA_UC_IRQ_2); + ipa3_remove_interrupt_handler(IPA_UC_IRQ_1); + ipa3_remove_interrupt_handler(IPA_UC_IRQ_0); + iounmap(ipa3_ctx->uc_ctx.uc_sram_mmio); + ipa3_ctx->uc_ctx.uc_inited = false; + } +} + +/** + * ipa3_uc_send_cmd() - Send a command to the uC + * + * Note1: This function sends command with 32bit parameter and do not + * use the higher 32bit of the command parameter (set to zero). + * + * Note2: In case the operation times out (No response from the uC) or + * polling maximal amount of retries has reached, the logic + * considers it as an invalid state of the uC/IPA, and + * issues a kernel panic. + * + * Returns: 0 on success. + * -EINVAL in case of invalid input. + * -EBADF in case uC interface is not initialized / + * or the uC has failed previously. + * -EFAULT in case the received status doesn't match + * the expected. + */ +int ipa3_uc_send_cmd(u32 cmd, u32 opcode, u32 expected_status, + bool polling_mode, unsigned long timeout_jiffies) +{ + return ipa3_uc_send_cmd_64b_param(cmd, 0, opcode, + expected_status, polling_mode, timeout_jiffies); +} + +/** + * ipa3_uc_register_handlers() - Registers event, response and log event + * handlers for a specific feature.Please note + * that currently only one handler can be + * registered per feature. + * + * Return value: None + */ +void ipa3_uc_register_handlers(enum ipa3_hw_features feature, + struct ipa3_uc_hdlrs *hdlrs) +{ + unsigned long flags = 0; + + if (0 > feature || IPA_HW_FEATURE_MAX <= feature) { + IPAERR("Feature %u is invalid, not registering hdlrs\n", + feature); + return; + } + + IPA3_UC_LOCK(flags); + ipa3_uc_hdlrs[feature] = *hdlrs; + IPA3_UC_UNLOCK(flags); + + IPADBG("uC handlers registered for feature %u\n", feature); +} + +int ipa3_uc_is_gsi_channel_empty(enum ipa_client_type ipa_client) +{ + const struct ipa_gsi_ep_config *gsi_ep_info; + union IpaHwChkChEmptyCmdData_t cmd; + int ret; + + gsi_ep_info = ipa_get_gsi_ep_info(ipa_client); + if (!gsi_ep_info) { + IPAERR("Failed getting GSI EP info for client=%d\n", + ipa_client); + return 0; + } + + if (ipa3_uc_state_check()) { + IPADBG("uC cannot be used to validate ch emptiness clnt=%d\n" + , ipa_client); + return 0; + } + + cmd.params.ee_n = gsi_ep_info->ee; + cmd.params.vir_ch_id = gsi_ep_info->ipa_gsi_chan_num; + + IPADBG("uC emptiness check for IPA GSI Channel %d\n", + gsi_ep_info->ipa_gsi_chan_num); + + ret = ipa3_uc_send_cmd(cmd.raw32b, IPA_CPU_2_HW_CMD_GSI_CH_EMPTY, 0, + false, 10*HZ); + + return ret; +} + +/** + * ipa3_uc_enable_holb_monitor() - Enable HOLB monitoring + * + * Return value: 0 on success, negative value otherwise + */ +int ipa3_uc_enable_holb_monitor(uint32_t polling_period) +{ + union IpaEnableHolbMonitorCmdData_t cmd; + int ret; + + cmd.params.holbMonitorPollingPeriod = polling_period; + + IPADBG("Sending uc CMD ENABLE_HOLB_MONITOR with polling_period (%d)\n", + polling_period); + + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + ret = ipa3_uc_send_cmd(cmd.raw32b, IPA_CPU_2_HW_CMD_ENABLE_HOLB_MONITOR, + 0, false, 10*HZ); + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + + return ret; +} + +/** + * ipa3_uc_add_holb_monitor() - Add a gsi channel that needs to be monitored + * + * Return value: 0 on success, negative value otherwise + */ +int ipa3_uc_add_holb_monitor(uint16_t gsi_ch, uint32_t action_mask, + uint32_t max_stuck_cnt, uint8_t ee) +{ + union IpaAddHolbMonitorCmdData_t cmd; + int ret; + + cmd.params.ipaProdGsiChid = gsi_ch; + cmd.params.EE = ee; + cmd.params.holbActionMask = action_mask; + cmd.params.maxStuckSampleCnt = max_stuck_cnt; + + IPADBG("Sending uc CMD ADD_HOLB_MONITOR"); + IPADBG("CMD params gsi_chid (%d), mask (%d), max_stuck_cnt (%d)\n", + gsi_ch, action_mask, max_stuck_cnt); + + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + ret = ipa3_uc_send_cmd(cmd.raw32b, IPA_CPU_2_HW_CMD_ADD_HOLB_MONITOR, 0, + false, 10*HZ); + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + + return ret; +} + +/** + * ipa3_uc_del_holb_monitor() - Disable monitoring for a particular + * gsi channel + * + * Return value: 0 on success, negative value otherwise + */ +int ipa3_uc_del_holb_monitor(uint16_t gsi_ch, uint8_t ee) +{ + union IpaDelHolbMonitorCmdData_t cmd; + int ret; + + cmd.params.ipaProdGsiChid = gsi_ch; + cmd.params.EE = ee; + + IPADBG("Sending uc IPA_CPU_2_HW_CMD_DEL_HOLB_MONITOR for gsi_ch %d\n", + gsi_ch); + + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + ret = ipa3_uc_send_cmd(cmd.raw32b, IPA_CPU_2_HW_CMD_DEL_HOLB_MONITOR, 0, + false, 10*HZ); + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + + return ret; +} + +/** + * ipa3_uc_disable_holb_monitor() - Disable HOLB monitoring + * + * Return value: 0 on success, negative value otherwise + */ +int ipa3_uc_disable_holb_monitor(void) +{ + int ret; + + IPADBG("Sending uc IPA_CPU_2_HW_CMD_DISABLE_HOLB_MONITOR\n"); + + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + ret = ipa3_uc_send_cmd(0, IPA_CPU_2_HW_CMD_DISABLE_HOLB_MONITOR, 0, + false, 10*HZ); + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + + return ret; +} + +/** + * ipa3_uc_notify_clk_state() - notify to uC of clock enable / disable + * @enabled: true if clock are enabled + * + * The function uses the uC interface in order to notify uC before IPA clocks + * are disabled to make sure uC is not in the middle of operation. + * Also after clocks are enabled ned to notify uC to start processing. + * + * Returns: 0 on success, negative on failure + */ +int ipa3_uc_notify_clk_state(bool enabled) +{ + u32 opcode; + + if (ipa3_ctx->ipa_hw_type > IPA_HW_v4_0) { + IPADBG_LOW("not supported past IPA v4.0\n"); + return 0; + } + + /* + * If the uC interface has not been initialized yet, + * don't notify the uC on the enable/disable + */ + if (ipa3_uc_state_check()) { + IPADBG("uC interface will not notify the UC on clock state\n"); + return 0; + } + + IPADBG("uC clock %s notification\n", (enabled) ? "UNGATE" : "GATE"); + + opcode = (enabled) ? IPA_CPU_2_HW_CMD_CLK_UNGATE : + IPA_CPU_2_HW_CMD_CLK_GATE; + + return ipa3_uc_send_cmd(0, opcode, 0, true, 0); +} + +/** + * ipa3_uc_update_hw_flags() - send uC the HW flags to be used + * @flags: This field is expected to be used as bitmask for enum ipa3_hw_flags + * + * Returns: 0 on success, negative on failure + */ +int ipa3_uc_update_hw_flags(u32 flags) +{ + union IpaHwUpdateFlagsCmdData_t cmd; + + memset(&cmd, 0, sizeof(cmd)); + cmd.params.newFlags = flags; + return ipa3_uc_send_cmd(cmd.raw32b, IPA_CPU_2_HW_CMD_UPDATE_FLAGS, 0, + false, HZ); +} + +/** + * ipa3_uc_rg10_write_reg() - write to register possibly via uC + * + * if the RG10 limitation workaround is enabled, then writing + * to a register will be proxied by the uC due to H/W limitation. + * This func should be called for RG10 registers only + * + * @Parameters: Like ipahal_write_reg_n() parameters + * + */ +void ipa3_uc_rg10_write_reg(enum ipahal_reg_name reg, u32 n, u32 val) +{ + int ret; + u32 paddr; + + if (!ipa3_ctx->apply_rg10_wa) + return ipahal_write_reg_n(reg, n, val); + + + /* calculate register physical address */ + paddr = ipa3_ctx->ipa_wrapper_base + ipa3_ctx->ctrl->ipa_reg_base_ofst; + paddr += ipahal_get_reg_n_ofst(reg, n); + + IPADBG("Sending uC cmd to reg write: addr=0x%x val=0x%x\n", + paddr, val); + ret = ipa3_uc_send_cmd_64b_param(paddr, val, + IPA_CPU_2_HW_CMD_REG_WRITE, 0, true, 0); + if (ret) { + IPAERR("failed to send cmd to uC for reg write\n"); + /* Unexpected UC hardware state */ + BUG(); + } +} + + +/** + * ipa3_uc_memcpy() - Perform a memcpy action using IPA uC + * @dest: physical address to store the copied data. + * @src: physical address of the source data to copy. + * @len: number of bytes to copy. + * + * Returns: 0 on success, negative on failure + */ +int ipa3_uc_memcpy(phys_addr_t dest, phys_addr_t src, int len) +{ + int res; + struct ipa_mem_buffer mem; + struct IpaHwMemCopyData_t *cmd; + + IPADBG("dest 0x%pa src 0x%pa len %d\n", &dest, &src, len); + mem.size = sizeof(*cmd); + mem.base = dma_alloc_coherent(ipa3_ctx->pdev, mem.size, &mem.phys_base, + GFP_KERNEL); + if (!mem.base) { + IPAERR("fail to alloc DMA buff of size %d\n", mem.size); + return -ENOMEM; + } + cmd = (struct IpaHwMemCopyData_t *)mem.base; + memset(cmd, 0, sizeof(*cmd)); + cmd->destination_addr = dest; + cmd->dest_buffer_size = len; + cmd->source_addr = src; + cmd->source_buffer_size = len; + res = ipa3_uc_send_cmd((u32)mem.phys_base, IPA_CPU_2_HW_CMD_MEMCPY, 0, + true, 10 * HZ); + if (res) { + IPAERR("ipa3_uc_send_cmd failed %d\n", res); + goto free_coherent; + } + + res = 0; +free_coherent: + dma_free_coherent(ipa3_ctx->pdev, mem.size, mem.base, mem.phys_base); + return res; +} + +int ipa3_uc_send_remote_ipa_info(u32 remote_addr, uint32_t mbox_n) +{ + int res; + struct ipa_mem_buffer cmd; + struct IpaHwDbAddrInfo_t *uc_info; + + cmd.size = sizeof(*uc_info); + cmd.base = dma_alloc_coherent(ipa3_ctx->uc_pdev, cmd.size, + &cmd.phys_base, GFP_KERNEL); + if (cmd.base == NULL) + return -ENOMEM; + + uc_info = (struct IpaHwDbAddrInfo_t *) cmd.base; + uc_info->remoteIPAAddr = remote_addr; + uc_info->mboxN = mbox_n; + + res = ipa3_uc_send_cmd((u32)(cmd.phys_base), + IPA_CPU_2_HW_CMD_REMOTE_IPA_INFO, 0, + false, 10 * HZ); + + if (res) { + IPAERR("fail to map 0x%x to mbox %d\n", + uc_info->remoteIPAAddr, + uc_info->mboxN); + goto free_coherent; + } + + res = 0; +free_coherent: + dma_free_coherent(ipa3_ctx->uc_pdev, cmd.size, cmd.base, cmd.phys_base); + return res; +} + +int ipa3_uc_debug_stats_alloc( + struct IpaHwOffloadStatsAllocCmdData_t cmdinfo) +{ + int result; + struct ipa_mem_buffer cmd; + enum ipa_cpu_2_hw_offload_commands command; + struct IpaHwOffloadStatsAllocCmdData_t *cmd_data; + + cmd.size = sizeof(*cmd_data); + cmd.base = dma_alloc_coherent(ipa3_ctx->uc_pdev, cmd.size, + &cmd.phys_base, GFP_KERNEL); + if (cmd.base == NULL) { + result = -ENOMEM; + return result; + } + cmd_data = (struct IpaHwOffloadStatsAllocCmdData_t *)cmd.base; + memcpy(cmd_data, &cmdinfo, + sizeof(struct IpaHwOffloadStatsAllocCmdData_t)); + command = IPA_CPU_2_HW_CMD_OFFLOAD_STATS_ALLOC; + + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + + result = ipa3_uc_send_cmd((u32)(cmd.phys_base), + command, + IPA_HW_2_CPU_OFFLOAD_CMD_STATUS_SUCCESS, + false, 20 * HZ); + if (result) { + IPAERR("fail to alloc offload stats\n"); + goto cleanup; + } + result = 0; +cleanup: + dma_free_coherent(ipa3_ctx->uc_pdev, + cmd.size, + cmd.base, cmd.phys_base); + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + IPADBG("exit\n"); + return result; +} + +int ipa3_uc_debug_stats_dealloc(uint32_t prot_id) +{ + int result; + enum ipa_cpu_2_hw_offload_commands command; + + IPADBG("protocol %d\n", prot_id); + command = IPA_CPU_2_HW_CMD_OFFLOAD_STATS_DEALLOC; + + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + + /* instead of giving pointer, directly give prot_id */ + result = ipa3_uc_send_cmd(prot_id, + command, + IPA_HW_2_CPU_OFFLOAD_CMD_STATUS_SUCCESS, + false, 10 * HZ); + if (result) { + IPAERR("fail to dealloc offload stats\n"); + goto cleanup; + } + switch (prot_id) { + case IPA_HW_PROTOCOL_AQC: + iounmap(ipa3_ctx->aqc_ctx.dbg_stats.uc_dbg_stats_mmio); + ipa3_ctx->aqc_ctx.dbg_stats.uc_dbg_stats_mmio = NULL; + break; + case IPA_HW_PROTOCOL_RTK: + iounmap(ipa3_ctx->rtk_ctx.dbg_stats.uc_dbg_stats_mmio); + ipa3_ctx->rtk_ctx.dbg_stats.uc_dbg_stats_mmio = NULL; + break; + case IPA_HW_PROTOCOL_NTN3: + iounmap(ipa3_ctx->ntn_ctx.dbg_stats.uc_dbg_stats_mmio); + ipa3_ctx->ntn_ctx.dbg_stats.uc_dbg_stats_mmio = NULL; + break; + case IPA_HW_PROTOCOL_WDI: + iounmap(ipa3_ctx->wdi2_ctx.dbg_stats.uc_dbg_stats_mmio); + ipa3_ctx->wdi2_ctx.dbg_stats.uc_dbg_stats_mmio = NULL; + break; + case IPA_HW_PROTOCOL_WDI3: + iounmap(ipa3_ctx->wdi3_ctx.dbg_stats.uc_dbg_stats_mmio); + ipa3_ctx->wdi3_ctx.dbg_stats.uc_dbg_stats_mmio = NULL; + break; + default: + IPAERR("unknown protocols %d\n", prot_id); + } + result = 0; +cleanup: + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + IPADBG("exit\n"); + return result; +} + +int ipa3_uc_setup_event_ring(void) +{ + int res = 0; + struct ipa_mem_buffer cmd, *ring; + union IpaSetupEventRingCmdData_t *ring_info; + + ring = &ipa3_ctx->uc_ctx.event_ring; + /* Allocate event ring */ + ring->size = sizeof(struct eventElement_t) * IPA_UC_EVENT_RING_SIZE; + ring->base = dma_alloc_coherent(ipa3_ctx->uc_pdev, ring->size, + &ring->phys_base, GFP_KERNEL); + if (ring->base == NULL) + return -ENOMEM; + + cmd.size = sizeof(*ring_info); + cmd.base = dma_alloc_coherent(ipa3_ctx->uc_pdev, cmd.size, + &cmd.phys_base, GFP_KERNEL); + if (cmd.base == NULL) { + dma_free_coherent(ipa3_ctx->uc_pdev, ring->size, + ring->base, ring->phys_base); + return -ENOMEM; + } + + ring_info = (union IpaSetupEventRingCmdData_t *) cmd.base; + ring_info->event.ring_base_pa = (u32) (ring->phys_base & 0xFFFFFFFF); + ring_info->event.ring_base_pa_hi = + (u32) ((ring->phys_base & 0xFFFFFFFF00000000) >> 32); + ring_info->event.ring_size = IPA_UC_EVENT_RING_SIZE; + + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + + res = ipa3_uc_send_cmd((u32)(cmd.phys_base), + IPA_CPU_2_HW_CMD_SETUP_EVENT_RING, 0, + false, 10 * HZ); + + if (res) { + IPAERR(" faile to setup event ring 0x%x 0x%x, size %d\n", + ring_info->event.ring_base_pa, + ring_info->event.ring_base_pa_hi, + ring_info->event.ring_size); + goto free_cmd; + } + + ipa3_ctx->uc_ctx.uc_event_ring_valid = true; + /* write wp/rp values */ + ipa3_ctx->uc_ctx.ering_rp_local = 0; + ipa3_ctx->uc_ctx.ering_wp_local = + ring->size - sizeof(struct eventElement_t); + ipahal_write_reg_mn(IPA_UC_MAILBOX_m_n, + IPA_UC_ERING_m, IPA_UC_ERING_n_r, 0); + ipahal_write_reg_mn(IPA_UC_MAILBOX_m_n, + IPA_UC_ERING_m, IPA_UC_ERING_n_w, + ipa3_ctx->uc_ctx.ering_wp_local); + ipa3_ctx->uc_ctx.ering_wp = + ipa3_ctx->uc_ctx.ering_wp_local; + ipa3_ctx->uc_ctx.ering_rp = 0; + +free_cmd: + dma_free_coherent(ipa3_ctx->uc_pdev, + cmd.size, cmd.base, cmd.phys_base); + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + return res; +} + +int ipa3_uc_quota_monitor(uint64_t quota) +{ + int ind, res = 0; + struct ipa_mem_buffer cmd; + struct IpaQuotaMonitoring_t *quota_info; + + cmd.size = sizeof(*quota_info); + cmd.base = dma_alloc_coherent(ipa3_ctx->uc_pdev, cmd.size, + &cmd.phys_base, GFP_KERNEL); + if (cmd.base == NULL) + return -ENOMEM; + + quota_info = (struct IpaQuotaMonitoring_t *)cmd.base; + quota_info->protocol = IPA_HW_PROTOCOL_WDI3; + quota_info->params.WdiQM.Quota = quota; + quota_info->params.WdiQM.info.Num = 4; + ind = ipa3_ctx->fnr_info.hw_counter_offset + + UL_HW - 1; + quota_info->params.WdiQM.info.Offset[0] = + IPA_MEM_PART(stats_fnr_ofst) + + sizeof(struct ipa_flt_rt_stats) * ind + 8; + ind = ipa3_ctx->fnr_info.hw_counter_offset + + DL_ALL - 1; + quota_info->params.WdiQM.info.Offset[1] = + IPA_MEM_PART(stats_fnr_ofst) + + sizeof(struct ipa_flt_rt_stats) * ind + 8; + ind = ipa3_ctx->fnr_info.sw_counter_offset + + UL_HW_CACHE - 1; + quota_info->params.WdiQM.info.Offset[2] = + IPA_MEM_PART(stats_fnr_ofst) + + sizeof(struct ipa_flt_rt_stats) * ind + 8; + ind = ipa3_ctx->fnr_info.sw_counter_offset + + UL_WLAN_TX - 1; + quota_info->params.WdiQM.info.Offset[3] = + IPA_MEM_PART(stats_fnr_ofst) + + sizeof(struct ipa_flt_rt_stats) * ind + 8; + quota_info->params.WdiQM.info.Interval = + IPA_UC_MON_INTERVAL; + + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + res = ipa3_uc_send_cmd((u32)(cmd.phys_base), + IPA_CPU_2_HW_CMD_QUOTA_MONITORING, + IPA_HW_2_CPU_OFFLOAD_CMD_STATUS_SUCCESS, + false, 10 * HZ); + + if (res) { + IPAERR(" faile to set quota %d, number offset %d\n", + quota_info->params.WdiQM.Quota, + quota_info->params.WdiQM.info.Num); + goto free_cmd; + } + + IPADBG(" offest1 %d offest2 %d offest3 %d offest4 %d\n", + quota_info->params.WdiQM.info.Offset[0], + quota_info->params.WdiQM.info.Offset[1], + quota_info->params.WdiQM.info.Offset[2], + quota_info->params.WdiQM.info.Offset[3]); + +free_cmd: + dma_free_coherent(ipa3_ctx->uc_pdev, cmd.size, cmd.base, cmd.phys_base); + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + + return res; +} + +int ipa_uc_bw_monitor(struct ipa_wdi_bw_info *info) +{ + int i, ind, res = 0; + struct ipa_mem_buffer cmd; + struct IpaBwMonitoring_t *bw_info; + + if (!info) + return -EINVAL; + + /* check max entry */ + if (info->num > BW_MONITORING_MAX_THRESHOLD) { + IPAERR("%d, support max %d bw monitor\n", info->num, + BW_MONITORING_MAX_THRESHOLD); + return -EINVAL; + } + + cmd.size = sizeof(*bw_info); + cmd.base = dma_alloc_coherent(ipa3_ctx->uc_pdev, cmd.size, + &cmd.phys_base, GFP_KERNEL); + if (cmd.base == NULL) + return -ENOMEM; + + bw_info = (struct IpaBwMonitoring_t *)cmd.base; + bw_info->protocol = IPA_HW_PROTOCOL_WDI3; + bw_info->params.WdiBw.NumThresh = info->num; + bw_info->params.WdiBw.Stop = info->stop; + IPADBG("stop bw-monitor? %d\n", bw_info->params.WdiBw.Stop); + + for (i = 0; i < info->num; i++) { + bw_info->params.WdiBw.BwThreshold[i] = info->threshold[i]; + IPADBG("%d-st, %lu\n", i, bw_info->params.WdiBw.BwThreshold[i]); + } + + bw_info->params.WdiBw.info.Num = 8; + ind = ipa3_ctx->fnr_info.hw_counter_offset + + UL_HW - 1; + bw_info->params.WdiBw.info.Offset[0] = + IPA_MEM_PART(stats_fnr_ofst) + + sizeof(struct ipa_flt_rt_stats) * ind + 8; + ind = ipa3_ctx->fnr_info.hw_counter_offset + + DL_HW - 1; + bw_info->params.WdiBw.info.Offset[1] = + IPA_MEM_PART(stats_fnr_ofst) + + sizeof(struct ipa_flt_rt_stats) * ind + 8; + ind = ipa3_ctx->fnr_info.hw_counter_offset + + DL_ALL - 1; + bw_info->params.WdiBw.info.Offset[2] = + IPA_MEM_PART(stats_fnr_ofst) + + sizeof(struct ipa_flt_rt_stats) * ind + 8; + ind = ipa3_ctx->fnr_info.hw_counter_offset + + UL_ALL - 1; + bw_info->params.WdiBw.info.Offset[3] = + IPA_MEM_PART(stats_fnr_ofst) + + sizeof(struct ipa_flt_rt_stats) * ind + 8; + ind = ipa3_ctx->fnr_info.sw_counter_offset + + UL_HW_CACHE - 1; + bw_info->params.WdiBw.info.Offset[4] = + IPA_MEM_PART(stats_fnr_ofst) + + sizeof(struct ipa_flt_rt_stats) * ind + 8; + ind = ipa3_ctx->fnr_info.sw_counter_offset + + DL_HW_CACHE - 1; + bw_info->params.WdiBw.info.Offset[5] = + IPA_MEM_PART(stats_fnr_ofst) + + sizeof(struct ipa_flt_rt_stats) * ind + 8; + ind = ipa3_ctx->fnr_info.sw_counter_offset + + UL_WLAN_TX - 1; + bw_info->params.WdiBw.info.Offset[6] = + IPA_MEM_PART(stats_fnr_ofst) + + sizeof(struct ipa_flt_rt_stats) * ind + 8; + ind = ipa3_ctx->fnr_info.sw_counter_offset + + DL_WLAN_TX - 1; + bw_info->params.WdiBw.info.Offset[7] = + IPA_MEM_PART(stats_fnr_ofst) + + sizeof(struct ipa_flt_rt_stats) * ind + 8; + bw_info->params.WdiBw.info.Interval = + IPA_UC_MON_INTERVAL; + + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + + res = ipa3_uc_send_cmd((u32)(cmd.phys_base), + IPA_CPU_2_HW_CMD_BW_MONITORING, + IPA_HW_2_CPU_OFFLOAD_CMD_STATUS_SUCCESS, + false, 10 * HZ); + + if (res) { + IPAERR(" faile to set bw %d level with %d coutners\n", + bw_info->params.WdiBw.NumThresh, + bw_info->params.WdiBw.info.Num); + goto free_cmd; + } + +free_cmd: + dma_free_coherent(ipa3_ctx->uc_pdev, cmd.size, cmd.base, cmd.phys_base); + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + + return res; +} +EXPORT_SYMBOL(ipa_uc_bw_monitor); + +int ipa3_set_wlan_tx_info(struct ipa_wdi_tx_info *info) +{ + struct ipa_flt_rt_stats stats; + struct ipacm_fnr_info fnr_info; + + memset(&fnr_info, 0, sizeof(struct ipacm_fnr_info)); + if (!ipa_get_fnr_info(&fnr_info)) { + IPAERR("FNR counter haven't configured\n"); + return -EINVAL; + } + + /* update sw counters */ + memset(&stats, 0, sizeof(struct ipa_flt_rt_stats)); + stats.num_bytes = info->sta_tx; + if (ipa_set_flt_rt_stats(fnr_info.sw_counter_offset + + UL_WLAN_TX, stats)) { + IPAERR("Failed to set stats to ul_wlan_tx %d\n", + fnr_info.sw_counter_offset + UL_WLAN_TX); + return -EINVAL; + } + + stats.num_bytes = info->ap_tx; + if (ipa_set_flt_rt_stats(fnr_info.sw_counter_offset + + DL_WLAN_TX, stats)) { + IPAERR("Failed to set stats to dl_wlan_tx %d\n", + fnr_info.sw_counter_offset + DL_WLAN_TX); + return -EINVAL; + } + + return 0; +} +EXPORT_SYMBOL(ipa3_set_wlan_tx_info); + +int ipa3_uc_send_enable_flow_control(uint16_t gsi_chid, + uint16_t redMarkerThreshold) +{ + + int res; + union IpaEnablePipeMonitorCmdData_t cmd; + + cmd.params.ipaProdGsiChid = gsi_chid; + cmd.params.redMarkerThreshold = redMarkerThreshold; + + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + res = ipa3_uc_send_cmd((cmd.raw32b), + IPA_CPU_2_HW_CMD_ENABLE_FLOW_CTL_MONITOR, 0, + false, 10 * HZ); + + if (res) + IPAERR("fail to enable flow ctrl for 0x%x\n", + cmd.params.ipaProdGsiChid); + + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + return res; +} + +int ipa3_uc_send_disable_flow_control(void) +{ + int res; + + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + res = ipa3_uc_send_cmd(0, + IPA_CPU_2_HW_CMD_DISABLE_FLOW_CTL_MONITOR, 0, + false, 10 * HZ); + + if (res) + IPAERR("fail to disable flow control\n"); + + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + return res; +} + +int ipa3_uc_send_update_flow_control(uint32_t bitmask, + uint8_t add_delete) +{ + int res; + + if (bitmask == 0) { + IPAERR("Err update flow control, mask = 0\n"); + return 0; + } + + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + res = ipa3_uc_send_cmd_64b_param(bitmask, add_delete, + IPA_CPU_2_HW_CMD_UPDATE_FLOW_CTL_MONITOR, 0, + false, 10 * HZ); + + if (res) + IPAERR("fail flowCtrl update mask = 0x%x add_del = 0x%x\n", + bitmask, add_delete); + + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + return res; +} + +/** + * ipa3_add_dscp_vlan_pcp_map() - Feed "vlan/pcp to dscp" map into the IPA uC + * @map: The mapping data destined for the uC + * + * Returns: 0 on success, negative on failure + */ +int ipa3_add_dscp_vlan_pcp_map( + struct IpaDscpVlanPcpMap_t *map ) +{ + struct ipa_mem_buffer mem; + struct IpaDscpVlanPcpMap_t *cmd; + int res; + + if (!map) { + IPAERR("null argument (ie. map) passed\n"); + return -EINVAL; + } + + IPADBG("map add attempt. num_vlan: %u\n", map->num_vlan); + + mem.size = sizeof(struct IpaDscpVlanPcpMap_t); + + mem.base = dma_alloc_coherent( + ipa3_ctx->uc_pdev, mem.size, + &mem.phys_base, GFP_KERNEL); + + if (!mem.base) { + IPAERR("Fail to alloc DMA buff of size %d\n", mem.size); + return -ENOMEM; + } + + cmd = (struct IpaDscpVlanPcpMap_t *) mem.base; + + memcpy(cmd, map, sizeof(struct IpaDscpVlanPcpMap_t)); + + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + + res = ipa3_uc_send_cmd( + (u32) mem.phys_base, + IPA_CPU_2_HW_CMD_ADD_EOGRE_MAPPING, + 0, true, 10 * HZ); + + if (res) { + IPAERR("ipa3_uc_send_cmd failed %d\n", res); + goto free_coherent; + } + + IPADBG("map add success\n"); + + res = 0; + +free_coherent: + dma_free_coherent(ipa3_ctx->uc_pdev, mem.size, mem.base, mem.phys_base); + + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + + return res; +} diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_uc_holb_monitor.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_uc_holb_monitor.c new file mode 100644 index 0000000000..7fe800d57e --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_uc_holb_monitor.c @@ -0,0 +1,246 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +#include "ipa_i.h" +#include "ipa_uc_holb_monitor.h" + + +/** + * ipa3_uc_holb_client_handler - Iterates through all HOLB clients and sends + * ADD_HOLB_MONITOR command if necessary. + * + */ +void ipa3_uc_holb_client_handler(void) +{ + int client_idx; + struct ipa_uc_holb_client_info *holb_client; + int num_clients; + + if (!ipa3_ctx->uc_ctx.ipa_use_uc_holb_monitor) + return; + + mutex_lock(&ipa3_ctx->uc_ctx.holb_monitor.uc_holb_lock); + + num_clients = ipa3_ctx->uc_ctx.holb_monitor.num_holb_clients; + ipa3_ctx->uc_ctx.uc_holb_enabled = true; + + for (client_idx = 0; client_idx < num_clients; client_idx++) { + holb_client = + &(ipa3_ctx->uc_ctx.holb_monitor.client[client_idx]); + if (holb_client->state == IPA_HOLB_ADD_PENDING) { + ipa3_uc_add_holb_monitor(holb_client->gsi_chan_hdl, + holb_client->action_mask, holb_client->max_stuck_cnt, + holb_client->ee); + IPADBG("HOLB Client with GSI %d moved to ADD state\n", + holb_client->gsi_chan_hdl); + holb_client->state = IPA_HOLB_ADD; + } + } + + mutex_unlock(&ipa3_ctx->uc_ctx.holb_monitor.uc_holb_lock); +} + +/** + * ipa3_get_holb_client_idx_by_ch() - Get client index in client + * array with a specified gsi channel + * @gsi_chan_hdl: GSI Channel of the client to be monitored + * + * Returns client index in client array + */ +static int ipa3_get_holb_client_idx_by_ch(uint16_t gsi_ch) +{ + int client_idx; + int num_clients = ipa3_ctx->uc_ctx.holb_monitor.num_holb_clients; + struct ipa_uc_holb_client_info *holb_client; + + for (client_idx = 0; client_idx < num_clients; client_idx++) { + holb_client = + &(ipa3_ctx->uc_ctx.holb_monitor.client[client_idx]); + if (holb_client->gsi_chan_hdl == gsi_ch) + return client_idx; + } + return -EINVAL; +} + +/** + * ipa3_set_holb_client_by_ch() - Set client parameters for specific + * gsi channel + * @client: Client values to be set for the gsi channel + * + */ +void ipa3_set_holb_client_by_ch(struct ipa_uc_holb_client_info client) +{ + uint16_t gsi_ch; + int client_idx, num_clients; + struct ipa_uc_holb_client_info *holb_client; + + + mutex_lock(&ipa3_ctx->uc_ctx.holb_monitor.uc_holb_lock); + + gsi_ch = client.gsi_chan_hdl; + client_idx = ipa3_get_holb_client_idx_by_ch(gsi_ch); + + if (client_idx != -EINVAL) { + holb_client = + &(ipa3_ctx->uc_ctx.holb_monitor.client[client_idx]); + } else { + num_clients = ipa3_ctx->uc_ctx.holb_monitor.num_holb_clients; + holb_client = + &(ipa3_ctx->uc_ctx.holb_monitor.client[num_clients]); + ipa3_ctx->uc_ctx.holb_monitor.num_holb_clients = ++num_clients; + holb_client->gsi_chan_hdl = gsi_ch; + } + + holb_client->debugfs_param = client.debugfs_param; + if (holb_client->debugfs_param) + holb_client->max_stuck_cnt = client.max_stuck_cnt; + IPADBG("HOLB gsi_chan %d with max_stuck_cnt %d, set %d\n", + gsi_ch, holb_client->max_stuck_cnt, holb_client->debugfs_param); + + mutex_unlock(&ipa3_ctx->uc_ctx.holb_monitor.uc_holb_lock); +} + +/** + * ipa3_uc_client_add_holb_monitor() - Sends ADD_HOLB_MONITOR for gsi channels + * if uC is enabled, else saves client state + * @gsi_chan_hdl: GSI Channel of the client to be monitored + * @action_mask: HOLB action mask + * @max_stuck_cnt: Max number of attempts uC should try before sending an event + * @ee: EE that the chid belongs to + * + * Return value: 0 on success, negative value otherwise + */ +int ipa3_uc_client_add_holb_monitor(uint16_t gsi_ch, uint32_t action_mask, + uint32_t max_stuck_cnt, uint8_t ee) +{ + + struct ipa_uc_holb_client_info *holb_client; + int ret = 0; + int client_idx, num_clients; + + if (!ipa3_ctx->uc_ctx.ipa_use_uc_holb_monitor) + return ret; + + mutex_lock(&ipa3_ctx->uc_ctx.holb_monitor.uc_holb_lock); + + client_idx = ipa3_get_holb_client_idx_by_ch(gsi_ch); + if (client_idx != -EINVAL) { + holb_client = + &(ipa3_ctx->uc_ctx.holb_monitor.client[client_idx]); + } else { + num_clients = ipa3_ctx->uc_ctx.holb_monitor.num_holb_clients; + holb_client = + &(ipa3_ctx->uc_ctx.holb_monitor.client[num_clients]); + ipa3_ctx->uc_ctx.holb_monitor.num_holb_clients = ++num_clients; + } + + holb_client->gsi_chan_hdl = gsi_ch; + holb_client->action_mask = action_mask; + if (!holb_client->debugfs_param) + holb_client->max_stuck_cnt = max_stuck_cnt; + holb_client->ee = ee; + + if (ipa3_uc_holb_enabled_check()) { + if (holb_client->state != IPA_HOLB_ADD) { + IPADBG("GSI chan %d going to ADD state\n", + holb_client->gsi_chan_hdl); + ret = ipa3_uc_add_holb_monitor( + holb_client->gsi_chan_hdl, + holb_client->action_mask, holb_client->max_stuck_cnt, + holb_client->ee); + holb_client->state = IPA_HOLB_ADD; + } + } else { + IPADBG("GSI chan %d going to ADD_PENDING state\n", + holb_client->gsi_chan_hdl); + holb_client->state = IPA_HOLB_ADD_PENDING; + } + + + mutex_unlock(&ipa3_ctx->uc_ctx.holb_monitor.uc_holb_lock); + return ret; +} + +/** + * ipa3_uc_client_del_holb_monitor() - Sends DEL_HOLB_MONITOR for gsi channels + * if uC is enabled, else saves client state + * @gsi_chan_hdl: GSI Channel of the client to be monitored + * @ee: EE that the chid belongs to + * + * Return value: 0 on success, negative value otherwise + */ +int ipa3_uc_client_del_holb_monitor(uint16_t gsi_ch, uint8_t ee) +{ + + struct ipa_uc_holb_client_info *holb_client; + int ret = 0; + int client_idx; + + if (!ipa3_ctx->uc_ctx.ipa_use_uc_holb_monitor) + return ret; + + mutex_lock(&ipa3_ctx->uc_ctx.holb_monitor.uc_holb_lock); + + client_idx = ipa3_get_holb_client_idx_by_ch(gsi_ch); + if (client_idx == -EINVAL) { + IPAERR("Invalid client with GSI chan %d\n", gsi_ch); + return client_idx; + } + + holb_client = &(ipa3_ctx->uc_ctx.holb_monitor.client[client_idx]); + if (ipa3_uc_holb_enabled_check() && + holb_client->state == IPA_HOLB_ADD) { + IPADBG("GSI chan %d going from ADD to DEL state\n", + holb_client->gsi_chan_hdl); + ret = ipa3_uc_del_holb_monitor(holb_client->gsi_chan_hdl, + ee); + holb_client->state = IPA_HOLB_DEL; + } else if (!ipa3_uc_holb_enabled_check() && + holb_client->state == IPA_HOLB_ADD_PENDING) { + IPADBG("GSI chan %d going from ADD_PENDING to DEL state\n", + holb_client->gsi_chan_hdl); + holb_client->state = IPA_HOLB_DEL; + } + + mutex_unlock(&ipa3_ctx->uc_ctx.holb_monitor.uc_holb_lock); + return ret; +} + +void ipa3_uc_holb_event_log(uint16_t gsi_ch, bool enable, + uint32_t qtimer_lsb, uint32_t qtimer_msb) +{ + struct ipa_uc_holb_client_info *holb_client; + int client_idx; + int current_idx; + + if (!ipa3_ctx->uc_ctx.ipa_use_uc_holb_monitor) + return; + + /* HOLB client indexes are reused when a peripheral is + * disconnected and connected back. And so there is no + * need to acquire the lock here as we get the events from + * uC only after a channel is connected atleast once. Also + * if we acquire a lock here we will run into a deadlock + * as we can get uC holb events and a response to add/delete + * commands at the same time. + */ + client_idx = ipa3_get_holb_client_idx_by_ch(gsi_ch); + if (client_idx == -EINVAL) { + IPAERR("Invalid client with GSI chan %d\n", gsi_ch); + return; + } + holb_client = &(ipa3_ctx->uc_ctx.holb_monitor.client[client_idx]); + current_idx = holb_client->current_idx; + + holb_client->events[current_idx].enable = enable; + holb_client->events[current_idx].qTimerLSB = qtimer_lsb; + holb_client->events[current_idx].qTimerMSB = qtimer_msb; + if (enable) + holb_client->enable_cnt++; + else + holb_client->disable_cnt++; + holb_client->current_idx = (holb_client->current_idx + 1) % + IPA_HOLB_EVENT_LOG_MAX; +} diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_uc_holb_monitor.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_uc_holb_monitor.h new file mode 100644 index 0000000000..5db612af63 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_uc_holb_monitor.h @@ -0,0 +1,141 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +#ifndef IPA_UC_HOLB_MONITOR_H +#define IPA_UC_HOLB_MONITOR_H + +#define IPA_HOLB_MONITOR_MAX_STUCK_COUNT 5 +#define IPA_HOLB_POLLING_PERIOD_MS 10 +#define HOLB_OP 0x1 +#define NOTIFY_AP_ON_HOLB 0x2 +#define HOLB_MONITOR_MASK (HOLB_OP | NOTIFY_AP_ON_HOLB) +#define IPA_HOLB_CLIENT_MAX 30 +#define IPA_HOLB_EVENT_LOG_MAX 20 +#define IPA_CLIENT_IS_HOLB_CONS(x) \ +(x == IPA_CLIENT_USB_CONS || x == IPA_CLIENT_WLAN2_CONS || \ +x == IPA_CLIENT_WLAN1_CONS || x == IPA_CLIENT_WIGIG1_CONS || \ +x == IPA_CLIENT_WIGIG2_CONS || x == IPA_CLIENT_WIGIG3_CONS || \ +x == IPA_CLIENT_WIGIG4_CONS) + +/* + * enum holb_client_state - Client state for HOLB + * IPA_HOLB_INIT : Initial state on bootup before client connect/disconnect + * IPA_HOLB_ADD_PENDING : Client GSI channel started but uC not enabled. + * IPA_HOLB_ADD : ADD_HOLB_MONITOR command sent for client. + * IPA_HOLB_DEL : DEL_HOLB_MONITOR command sent for client. + */ +enum ipa_holb_client_state { + IPA_HOLB_INIT = 0, + IPA_HOLB_ADD_PENDING = 1, + IPA_HOLB_ADD = 2, + IPA_HOLB_DEL = 3, +}; + +/** + * struct ipa_holb_events - HOLB enable/disable events log + * @qTimerLSB: LSB for event qtimer + * @qTimerMSB: MSB for event qtimer + * @enable: Even for enable/disable + */ +struct ipa_holb_events { + uint32_t qTimerLSB; + uint32_t qTimerMSB; + bool enable; +}; + +/** + * struct ipa_uc_holb_client_info - Client info needed for HOLB callback + * @gsi_chan_hdl: GSI Channel of the client to be monitored + * @action_mask: HOLB action mask + * @max_stuck_cnt: Max number of attempts uC should try before sending an event + * @ee: EE that the chid belongs to + * @debugfs_param: If debugfs is used to set the client parameters + * @state: Client state + * @events: HOLB enable/disable events log + * @current_idx: index of current event + * @enable_cnt: accumulate count for enable + * @disable_cnt: accumulate count for disable + */ +struct ipa_uc_holb_client_info { + uint16_t gsi_chan_hdl; + uint32_t action_mask; + uint32_t max_stuck_cnt; + uint8_t ee; + bool debugfs_param; + enum ipa_holb_client_state state; + struct ipa_holb_events events[IPA_HOLB_EVENT_LOG_MAX]; + uint32_t current_idx; + uint32_t enable_cnt; + uint32_t disable_cnt; +}; + +/** + * struct ipa_holb_monitor - Parameters needed for the HOLB monitor feature + * @num_holb_clients: Number of clients with holb monitor enabled + * @client: Array of clients tracked for HOLB Monitor + * @ipa_uc_holb_monitor_poll_period : Polling period in ms + * @uc_holb_lock : Lock for feature operations + * + */ +struct ipa_holb_monitor { + u32 num_holb_clients; + u32 poll_period; + u32 max_cnt_wlan; + u32 max_cnt_usb; + u32 max_cnt_11ad; + struct ipa_uc_holb_client_info client[IPA_HOLB_CLIENT_MAX]; + struct mutex uc_holb_lock; +}; + +/** + * ipa3_uc_holb_client_handler - Iterates through all HOLB clients and sends + * ADD_HOLB_MONITOR command if necessary. + * + */ +void ipa3_uc_holb_client_handler(void); + +/** + * ipa3_uc_client_add_holb_monitor() - Sends ADD_HOLB_MONITOR for gsi channels + * if uC is enabled, else saves client state + * @gsi_chan_hdl: GSI Channel of the client to be monitored + * @action_mask: HOLB action mask + * @max_stuck_cnt: Max number of attempts uC should try before sending an event + * @ee: EE that the chid belongs to + * + * Return value: 0 on success, negative value otherwise + */ +int ipa3_uc_client_add_holb_monitor(uint16_t gsi_ch, uint32_t action_mask, + uint32_t max_stuck_cnt, uint8_t ee); + +/** + * ipa3_uc_client_del_holb_monitor() - Sends DEL_HOLB_MONITOR for gsi channels + * if uC is enabled, else saves client state + * @gsi_chan_hdl: GSI Channel of the client to be monitored + * @ee: EE that the chid belongs to + * + * Return value: 0 on success, negative value otherwise + */ +int ipa3_uc_client_del_holb_monitor(uint16_t gsi_ch, uint8_t ee); + +/** + * ipa3_set_holb_client_by_ch() - Set client parameters for specific + * gsi channel + * @client: Client values to be set for the gsi channel + * + */ +void ipa3_set_holb_client_by_ch(struct ipa_uc_holb_client_info client); + +/** + * ipa3_uc_holb_event_log() - Log HOLB event for specific gsi + * channel + * @gsi_ch: Client values to be set for the gsi channel + * @enable: event is for enable/disable + * @qtimer_lsb: msb for event qtimer + * @qtimer_msb: lsb for event qtimer + */ +void ipa3_uc_holb_event_log(uint16_t gsi_ch, bool enable, + uint32_t qtimer_lsb, uint32_t qtimer_msb); + +#endif /* IPA_UC_HOLB_MONITOR_H */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_uc_mhi.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_uc_mhi.c new file mode 100644 index 0000000000..054cffef99 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_uc_mhi.c @@ -0,0 +1,958 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2015-2019, The Linux Foundation. All rights reserved. + */ + +#include "ipa.h" +#include "ipa_i.h" + +/* MHI uC interface definitions */ +#define IPA_HW_INTERFACE_MHI_VERSION 0x0004 + +#define IPA_HW_MAX_NUMBER_OF_CHANNELS 2 +#define IPA_HW_MAX_NUMBER_OF_EVENTRINGS 2 +#define IPA_HW_MAX_CHANNEL_HANDLE (IPA_HW_MAX_NUMBER_OF_CHANNELS-1) + +/** + * Values that represent the MHI commands from CPU to IPA HW. + * @IPA_CPU_2_HW_CMD_MHI_INIT: Initialize HW to be ready for MHI processing. + * Once operation was completed HW shall respond with + * IPA_HW_2_CPU_RESPONSE_CMD_COMPLETED. + * @IPA_CPU_2_HW_CMD_MHI_INIT_CHANNEL: Initialize specific channel to be ready + * to serve MHI transfers. Once initialization was completed HW shall + * respond with IPA_HW_2_CPU_RESPONSE_MHI_CHANGE_CHANNEL_STATE. + * IPA_HW_MHI_CHANNEL_STATE_ENABLE + * @IPA_CPU_2_HW_CMD_MHI_UPDATE_MSI: Update MHI MSI interrupts data. + * Once operation was completed HW shall respond with + * IPA_HW_2_CPU_RESPONSE_CMD_COMPLETED. + * @IPA_CPU_2_HW_CMD_MHI_CHANGE_CHANNEL_STATE: Change specific channel + * processing state following host request. Once operation was completed + * HW shall respond with IPA_HW_2_CPU_RESPONSE_MHI_CHANGE_CHANNEL_STATE. + * @IPA_CPU_2_HW_CMD_MHI_DL_UL_SYNC_INFO: Info related to DL UL syncronization. + * @IPA_CPU_2_HW_CMD_MHI_STOP_EVENT_UPDATE: Cmd to stop event ring processing. + */ +enum ipa_cpu_2_hw_mhi_commands { + IPA_CPU_2_HW_CMD_MHI_INIT + = FEATURE_ENUM_VAL(IPA_HW_FEATURE_MHI, 0), + IPA_CPU_2_HW_CMD_MHI_INIT_CHANNEL + = FEATURE_ENUM_VAL(IPA_HW_FEATURE_MHI, 1), + IPA_CPU_2_HW_CMD_MHI_UPDATE_MSI + = FEATURE_ENUM_VAL(IPA_HW_FEATURE_MHI, 2), + IPA_CPU_2_HW_CMD_MHI_CHANGE_CHANNEL_STATE + = FEATURE_ENUM_VAL(IPA_HW_FEATURE_MHI, 3), + IPA_CPU_2_HW_CMD_MHI_DL_UL_SYNC_INFO + = FEATURE_ENUM_VAL(IPA_HW_FEATURE_MHI, 4), + IPA_CPU_2_HW_CMD_MHI_STOP_EVENT_UPDATE + = FEATURE_ENUM_VAL(IPA_HW_FEATURE_MHI, 5) +}; + +/** + * Values that represent MHI related HW responses to CPU commands. + * @IPA_HW_2_CPU_RESPONSE_MHI_CHANGE_CHANNEL_STATE: Response to + * IPA_CPU_2_HW_CMD_MHI_INIT_CHANNEL or + * IPA_CPU_2_HW_CMD_MHI_CHANGE_CHANNEL_STATE commands. + */ +enum ipa_hw_2_cpu_mhi_responses { + IPA_HW_2_CPU_RESPONSE_MHI_CHANGE_CHANNEL_STATE + = FEATURE_ENUM_VAL(IPA_HW_FEATURE_MHI, 0), +}; + +/** + * Values that represent MHI related HW event to be sent to CPU. + * @IPA_HW_2_CPU_EVENT_MHI_CHANNEL_ERROR: Event specify the device detected an + * error in an element from the transfer ring associated with the channel + * @IPA_HW_2_CPU_EVENT_MHI_CHANNEL_WAKE_UP_REQUEST: Event specify a transport + * interrupt was asserted when MHI engine is suspended + */ +enum ipa_hw_2_cpu_mhi_events { + IPA_HW_2_CPU_EVENT_MHI_CHANNEL_ERROR + = FEATURE_ENUM_VAL(IPA_HW_FEATURE_MHI, 0), + IPA_HW_2_CPU_EVENT_MHI_CHANNEL_WAKE_UP_REQUEST + = FEATURE_ENUM_VAL(IPA_HW_FEATURE_MHI, 1), +}; + +/** + * Channel error types. + * @IPA_HW_CHANNEL_ERROR_NONE: No error persists. + * @IPA_HW_CHANNEL_INVALID_RE_ERROR: Invalid Ring Element was detected + */ +enum ipa_hw_channel_errors { + IPA_HW_CHANNEL_ERROR_NONE, + IPA_HW_CHANNEL_INVALID_RE_ERROR +}; + +/** + * MHI error types. + * @IPA_HW_INVALID_MMIO_ERROR: Invalid data read from MMIO space + * @IPA_HW_INVALID_CHANNEL_ERROR: Invalid data read from channel context array + * @IPA_HW_INVALID_EVENT_ERROR: Invalid data read from event ring context array + * @IPA_HW_NO_ED_IN_RING_ERROR: No event descriptors are available to report on + * secondary event ring + * @IPA_HW_LINK_ERROR: Link error + */ +enum ipa_hw_mhi_errors { + IPA_HW_INVALID_MMIO_ERROR + = FEATURE_ENUM_VAL(IPA_HW_FEATURE_MHI, 0), + IPA_HW_INVALID_CHANNEL_ERROR + = FEATURE_ENUM_VAL(IPA_HW_FEATURE_MHI, 1), + IPA_HW_INVALID_EVENT_ERROR + = FEATURE_ENUM_VAL(IPA_HW_FEATURE_MHI, 2), + IPA_HW_NO_ED_IN_RING_ERROR + = FEATURE_ENUM_VAL(IPA_HW_FEATURE_MHI, 4), + IPA_HW_LINK_ERROR + = FEATURE_ENUM_VAL(IPA_HW_FEATURE_MHI, 5), +}; + + +/** + * Structure referring to the common and MHI section of 128B shared memory + * located in offset zero of SW Partition in IPA SRAM. + * The shared memory is used for communication between IPA HW and CPU. + * @common: common section in IPA SRAM + * @interfaceVersionMhi: The MHI interface version as reported by HW + * @mhiState: Overall MHI state + * @reserved_2B: reserved + * @mhiCnl0State: State of MHI channel 0. + * The state carries information regarding the error type. + * See IPA_HW_MHI_CHANNEL_STATES. + * @mhiCnl0State: State of MHI channel 1. + * @mhiCnl0State: State of MHI channel 2. + * @mhiCnl0State: State of MHI channel 3 + * @mhiCnl0State: State of MHI channel 4. + * @mhiCnl0State: State of MHI channel 5. + * @mhiCnl0State: State of MHI channel 6. + * @mhiCnl0State: State of MHI channel 7. + * @reserved_37_34: reserved + * @reserved_3B_38: reserved + * @reserved_3F_3C: reserved + */ +struct IpaHwSharedMemMhiMapping_t { + struct IpaHwSharedMemCommonMapping_t common; + u16 interfaceVersionMhi; + u8 mhiState; + u8 reserved_2B; + u8 mhiCnl0State; + u8 mhiCnl1State; + u8 mhiCnl2State; + u8 mhiCnl3State; + u8 mhiCnl4State; + u8 mhiCnl5State; + u8 mhiCnl6State; + u8 mhiCnl7State; + u32 reserved_37_34; + u32 reserved_3B_38; + u32 reserved_3F_3C; +}; + + +/** + * Structure holding the parameters for IPA_CPU_2_HW_CMD_MHI_INIT command. + * Parameters are sent as pointer thus should be reside in address accessible + * to HW. + * @msiAddress: The MSI base (in device space) used for asserting the interrupt + * (MSI) associated with the event ring + * mmioBaseAddress: The address (in device space) of MMIO structure in + * host space + * deviceMhiCtrlBaseAddress: Base address of the memory region in the device + * address space where the MHI control data structures are allocated by + * the host, including channel context array, event context array, + * and rings. This value is used for host/device address translation. + * deviceMhiDataBaseAddress: Base address of the memory region in the device + * address space where the MHI data buffers are allocated by the host. + * This value is used for host/device address translation. + * firstChannelIndex: First channel ID. Doorbell 0 is mapped to this channel + * firstEventRingIndex: First event ring ID. Doorbell 16 is mapped to this + * event ring. + */ +struct IpaHwMhiInitCmdData_t { + u32 msiAddress; + u32 mmioBaseAddress; + u32 deviceMhiCtrlBaseAddress; + u32 deviceMhiDataBaseAddress; + u32 firstChannelIndex; + u32 firstEventRingIndex; +}; + +/** + * Structure holding the parameters for IPA_CPU_2_HW_CMD_MHI_INIT_CHANNEL + * command. Parameters are sent as 32b immediate parameters. + * @hannelHandle: The channel identifier as allocated by driver. + * value is within the range 0 to IPA_HW_MAX_CHANNEL_HANDLE + * @contexArrayIndex: Unique index for channels, between 0 and 255. The index is + * used as an index in channel context array structures. + * @bamPipeId: The IPA pipe number for pipe dedicated for this channel + * @channelDirection: The direction of the channel as defined in the channel + * type field (CHTYPE) in the channel context data structure. + * @reserved: reserved. + */ +union IpaHwMhiInitChannelCmdData_t { + struct IpaHwMhiInitChannelCmdParams_t { + u32 channelHandle:8; + u32 contexArrayIndex:8; + u32 bamPipeId:6; + u32 channelDirection:2; + u32 reserved:8; + } params; + u32 raw32b; +}; + +/** + * Structure holding the parameters for IPA_CPU_2_HW_CMD_MHI_UPDATE_MSI command. + * @msiAddress_low: The MSI lower base addr (in device space) used for asserting + * the interrupt (MSI) associated with the event ring. + * @msiAddress_hi: The MSI higher base addr (in device space) used for asserting + * the interrupt (MSI) associated with the event ring. + * @msiMask: Mask indicating number of messages assigned by the host to device + * @msiData: Data Pattern to use when generating the MSI + */ +struct IpaHwMhiMsiCmdData_t { + u32 msiAddress_low; + u32 msiAddress_hi; + u32 msiMask; + u32 msiData; +}; + +/** + * Structure holding the parameters for + * IPA_CPU_2_HW_CMD_MHI_CHANGE_CHANNEL_STATE command. + * Parameters are sent as 32b immediate parameters. + * @requestedState: The requested channel state as was indicated from Host. + * Use IPA_HW_MHI_CHANNEL_STATES to specify the requested state + * @channelHandle: The channel identifier as allocated by driver. + * value is within the range 0 to IPA_HW_MAX_CHANNEL_HANDLE + * @LPTransitionRejected: Indication that low power state transition was + * rejected + * @reserved: reserved + */ +union IpaHwMhiChangeChannelStateCmdData_t { + struct IpaHwMhiChangeChannelStateCmdParams_t { + u32 requestedState:8; + u32 channelHandle:8; + u32 LPTransitionRejected:8; + u32 reserved:8; + } params; + u32 raw32b; +}; + +/** + * Structure holding the parameters for + * IPA_CPU_2_HW_CMD_MHI_STOP_EVENT_UPDATE command. + * Parameters are sent as 32b immediate parameters. + * @channelHandle: The channel identifier as allocated by driver. + * value is within the range 0 to IPA_HW_MAX_CHANNEL_HANDLE + * @reserved: reserved + */ +union IpaHwMhiStopEventUpdateData_t { + struct IpaHwMhiStopEventUpdateDataParams_t { + u32 channelHandle:8; + u32 reserved:24; + } params; + u32 raw32b; +}; + +/** + * Structure holding the parameters for + * IPA_HW_2_CPU_RESPONSE_MHI_CHANGE_CHANNEL_STATE response. + * Parameters are sent as 32b immediate parameters. + * @state: The new channel state. In case state is not as requested this is + * error indication for the last command + * @channelHandle: The channel identifier + * @additonalParams: For stop: the number of pending transport descriptors + * currently queued + */ +union IpaHwMhiChangeChannelStateResponseData_t { + struct IpaHwMhiChangeChannelStateResponseParams_t { + u32 state:8; + u32 channelHandle:8; + u32 additonalParams:16; + } params; + u32 raw32b; +}; + +/** + * Structure holding the parameters for + * IPA_HW_2_CPU_EVENT_MHI_CHANNEL_ERROR event. + * Parameters are sent as 32b immediate parameters. + * @errorType: Type of error - IPA_HW_CHANNEL_ERRORS + * @channelHandle: The channel identifier as allocated by driver. + * value is within the range 0 to IPA_HW_MAX_CHANNEL_HANDLE + * @reserved: reserved + */ +union IpaHwMhiChannelErrorEventData_t { + struct IpaHwMhiChannelErrorEventParams_t { + u32 errorType:8; + u32 channelHandle:8; + u32 reserved:16; + } params; + u32 raw32b; +}; + +/** + * Structure holding the parameters for + * IPA_HW_2_CPU_EVENT_MHI_CHANNEL_WAKE_UP_REQUEST event. + * Parameters are sent as 32b immediate parameters. + * @channelHandle: The channel identifier as allocated by driver. + * value is within the range 0 to IPA_HW_MAX_CHANNEL_HANDLE + * @reserved: reserved + */ +union IpaHwMhiChannelWakeupEventData_t { + struct IpaHwMhiChannelWakeupEventParams_t { + u32 channelHandle:8; + u32 reserved:24; + } params; + u32 raw32b; +}; + +/** + * Structure holding the MHI Common statistics + * @numULDLSync: Number of times UL activity trigged due to DL activity + * @numULTimerExpired: Number of times UL Accm Timer expired + */ +struct IpaHwStatsMhiCmnInfoData_t { + u32 numULDLSync; + u32 numULTimerExpired; + u32 numChEvCtxWpRead; + u32 reserved; +}; + +/** + * Structure holding the MHI Channel statistics + * @doorbellInt: The number of doorbell int + * @reProccesed: The number of ring elements processed + * @bamFifoFull: Number of times Bam Fifo got full + * @bamFifoEmpty: Number of times Bam Fifo got empty + * @bamFifoUsageHigh: Number of times Bam fifo usage went above 75% + * @bamFifoUsageLow: Number of times Bam fifo usage went below 25% + * @bamInt: Number of BAM Interrupts + * @ringFull: Number of times Transfer Ring got full + * @ringEmpty: umber of times Transfer Ring got empty + * @ringUsageHigh: Number of times Transfer Ring usage went above 75% + * @ringUsageLow: Number of times Transfer Ring usage went below 25% + * @delayedMsi: Number of times device triggered MSI to host after + * Interrupt Moderation Timer expiry + * @immediateMsi: Number of times device triggered MSI to host immediately + * @thresholdMsi: Number of times device triggered MSI due to max pending + * events threshold reached + * @numSuspend: Number of times channel was suspended + * @numResume: Number of times channel was suspended + * @num_OOB: Number of times we indicated that we are OOB + * @num_OOB_timer_expiry: Number of times we indicated that we are OOB + * after timer expiry + * @num_OOB_moderation_timer_start: Number of times we started timer after + * sending OOB and hitting OOB again before we processed threshold + * number of packets + * @num_db_mode_evt: Number of times we indicated that we are in Doorbell mode + */ +struct IpaHwStatsMhiCnlInfoData_t { + u32 doorbellInt; + u32 reProccesed; + u32 bamFifoFull; + u32 bamFifoEmpty; + u32 bamFifoUsageHigh; + u32 bamFifoUsageLow; + u32 bamInt; + u32 ringFull; + u32 ringEmpty; + u32 ringUsageHigh; + u32 ringUsageLow; + u32 delayedMsi; + u32 immediateMsi; + u32 thresholdMsi; + u32 numSuspend; + u32 numResume; + u32 num_OOB; + u32 num_OOB_timer_expiry; + u32 num_OOB_moderation_timer_start; + u32 num_db_mode_evt; +}; + +/** + * Structure holding the MHI statistics + * @mhiCmnStats: Stats pertaining to MHI + * @mhiCnlStats: Stats pertaining to each channel + */ +struct IpaHwStatsMhiInfoData_t { + struct IpaHwStatsMhiCmnInfoData_t mhiCmnStats; + struct IpaHwStatsMhiCnlInfoData_t mhiCnlStats[ + IPA_HW_MAX_NUMBER_OF_CHANNELS]; +}; + +/** + * Structure holding the MHI Common Config info + * @isDlUlSyncEnabled: Flag to indicate if DL-UL synchronization is enabled + * @UlAccmVal: Out Channel(UL) accumulation time in ms when DL UL Sync is + * enabled + * @ulMsiEventThreshold: Threshold at which HW fires MSI to host for UL events + * @dlMsiEventThreshold: Threshold at which HW fires MSI to host for DL events + */ +struct IpaHwConfigMhiCmnInfoData_t { + u8 isDlUlSyncEnabled; + u8 UlAccmVal; + u8 ulMsiEventThreshold; + u8 dlMsiEventThreshold; +}; + +/** + * Structure holding the parameters for MSI info data + * @msiAddress_low: The MSI lower base addr (in device space) used for asserting + * the interrupt (MSI) associated with the event ring. + * @msiAddress_hi: The MSI higher base addr (in device space) used for asserting + * the interrupt (MSI) associated with the event ring. + * @msiMask: Mask indicating number of messages assigned by the host to device + * @msiData: Data Pattern to use when generating the MSI + */ +struct IpaHwConfigMhiMsiInfoData_t { + u32 msiAddress_low; + u32 msiAddress_hi; + u32 msiMask; + u32 msiData; +}; + +/** + * Structure holding the MHI Channel Config info + * @transferRingSize: The Transfer Ring size in terms of Ring Elements + * @transferRingIndex: The Transfer Ring channel number as defined by host + * @eventRingIndex: The Event Ring Index associated with this Transfer Ring + * @bamPipeIndex: The BAM Pipe associated with this channel + * @isOutChannel: Indication for the direction of channel + * @reserved_0: Reserved byte for maintaining 4byte alignment + * @reserved_1: Reserved byte for maintaining 4byte alignment + */ +struct IpaHwConfigMhiCnlInfoData_t { + u16 transferRingSize; + u8 transferRingIndex; + u8 eventRingIndex; + u8 bamPipeIndex; + u8 isOutChannel; + u8 reserved_0; + u8 reserved_1; +}; + +/** + * Structure holding the MHI Event Config info + * @msiVec: msi vector to invoke MSI interrupt + * @intmodtValue: Interrupt moderation timer (in milliseconds) + * @eventRingSize: The Event Ring size in terms of Ring Elements + * @eventRingIndex: The Event Ring number as defined by host + * @reserved_0: Reserved byte for maintaining 4byte alignment + * @reserved_1: Reserved byte for maintaining 4byte alignment + * @reserved_2: Reserved byte for maintaining 4byte alignment + */ +struct IpaHwConfigMhiEventInfoData_t { + u32 msiVec; + u16 intmodtValue; + u16 eventRingSize; + u8 eventRingIndex; + u8 reserved_0; + u8 reserved_1; + u8 reserved_2; +}; + +/** + * Structure holding the MHI Config info + * @mhiCmnCfg: Common Config pertaining to MHI + * @mhiMsiCfg: Config pertaining to MSI config + * @mhiCnlCfg: Config pertaining to each channel + * @mhiEvtCfg: Config pertaining to each event Ring + */ +struct IpaHwConfigMhiInfoData_t { + struct IpaHwConfigMhiCmnInfoData_t mhiCmnCfg; + struct IpaHwConfigMhiMsiInfoData_t mhiMsiCfg; + struct IpaHwConfigMhiCnlInfoData_t mhiCnlCfg[ + IPA_HW_MAX_NUMBER_OF_CHANNELS]; + struct IpaHwConfigMhiEventInfoData_t mhiEvtCfg[ + IPA_HW_MAX_NUMBER_OF_EVENTRINGS]; +}; + + +struct ipa3_uc_mhi_ctx { + u8 expected_responseOp; + u32 expected_responseParams; + void (*ready_cb)(void); + void (*wakeup_request_cb)(void); + u32 mhi_uc_stats_ofst; + struct IpaHwStatsMhiInfoData_t *mhi_uc_stats_mmio; +}; + +#define PRINT_COMMON_STATS(x) \ + (nBytes += scnprintf(&dbg_buff[nBytes], size - nBytes, \ + #x "=0x%x\n", ipa3_uc_mhi_ctx->mhi_uc_stats_mmio->mhiCmnStats.x)) + +#define PRINT_CHANNEL_STATS(ch, x) \ + (nBytes += scnprintf(&dbg_buff[nBytes], size - nBytes, \ + #x "=0x%x\n", ipa3_uc_mhi_ctx->mhi_uc_stats_mmio->mhiCnlStats[ch].x)) + +struct ipa3_uc_mhi_ctx *ipa3_uc_mhi_ctx; + +static int ipa3_uc_mhi_response_hdlr(struct IpaHwSharedMemCommonMapping_t + *uc_sram_mmio, u32 *uc_status) +{ + IPADBG("responseOp=%d\n", uc_sram_mmio->responseOp); + if (uc_sram_mmio->responseOp == ipa3_uc_mhi_ctx->expected_responseOp && + uc_sram_mmio->responseParams == + ipa3_uc_mhi_ctx->expected_responseParams) { + *uc_status = 0; + return 0; + } + return -EINVAL; +} + +static void ipa3_uc_mhi_event_hdlr(struct IpaHwSharedMemCommonMapping_t + *uc_sram_mmio) +{ + if (ipa3_ctx->uc_ctx.uc_sram_mmio->eventOp == + IPA_HW_2_CPU_EVENT_MHI_CHANNEL_ERROR) { + union IpaHwMhiChannelErrorEventData_t evt; + + IPAERR("Channel error\n"); + evt.raw32b = uc_sram_mmio->eventParams; + IPAERR("errorType=%d channelHandle=%d reserved=%d\n", + evt.params.errorType, evt.params.channelHandle, + evt.params.reserved); + } else if (ipa3_ctx->uc_ctx.uc_sram_mmio->eventOp == + IPA_HW_2_CPU_EVENT_MHI_CHANNEL_WAKE_UP_REQUEST) { + union IpaHwMhiChannelWakeupEventData_t evt; + + IPADBG("WakeUp channel request\n"); + evt.raw32b = uc_sram_mmio->eventParams; + IPADBG("channelHandle=%d reserved=%d\n", + evt.params.channelHandle, evt.params.reserved); + ipa3_uc_mhi_ctx->wakeup_request_cb(); + } +} + +static void ipa3_uc_mhi_event_log_info_hdlr( + struct IpaHwEventLogInfoData_t *uc_event_top_mmio) +{ + struct Ipa3HwEventInfoData_t *evt_info_ptr; + u32 size; + + if ((uc_event_top_mmio->protocolMask & (1 << IPA_HW_FEATURE_MHI)) + == 0) { + IPAERR("MHI feature missing 0x%x\n", + uc_event_top_mmio->protocolMask); + return; + } + + evt_info_ptr = &uc_event_top_mmio->statsInfo; + size = evt_info_ptr->featureInfo[IPA_HW_FEATURE_MHI].params.size; + if (size != sizeof(struct IpaHwStatsMhiInfoData_t)) { + IPAERR("mhi stats sz invalid exp=%zu is=%u\n", + sizeof(struct IpaHwStatsMhiInfoData_t), + size); + return; + } + + ipa3_uc_mhi_ctx->mhi_uc_stats_ofst = + evt_info_ptr->baseAddrOffset + + evt_info_ptr->featureInfo[IPA_HW_FEATURE_MHI].params.offset; + IPAERR("MHI stats ofst=0x%x\n", ipa3_uc_mhi_ctx->mhi_uc_stats_ofst); + if (ipa3_uc_mhi_ctx->mhi_uc_stats_ofst + + sizeof(struct IpaHwStatsMhiInfoData_t) >= + ipa3_ctx->ctrl->ipa_reg_base_ofst + + ipahal_get_reg_n_ofst(IPA_SW_AREA_RAM_DIRECT_ACCESS_n, 0) + + ipa3_ctx->smem_sz) { + IPAERR("uc_mhi_stats 0x%x outside SRAM\n", + ipa3_uc_mhi_ctx->mhi_uc_stats_ofst); + return; + } + + ipa3_uc_mhi_ctx->mhi_uc_stats_mmio = + ioremap(ipa3_ctx->ipa_wrapper_base + + ipa3_uc_mhi_ctx->mhi_uc_stats_ofst, + sizeof(struct IpaHwStatsMhiInfoData_t)); + if (!ipa3_uc_mhi_ctx->mhi_uc_stats_mmio) { + IPAERR("fail to ioremap uc mhi stats\n"); + return; + } +} + +int ipa3_uc_mhi_init(void (*ready_cb)(void), void (*wakeup_request_cb)(void)) +{ + struct ipa3_uc_hdlrs hdlrs; + + if (ipa3_uc_mhi_ctx) { + IPAERR("Already initialized\n"); + return -EFAULT; + } + + ipa3_uc_mhi_ctx = kzalloc(sizeof(*ipa3_uc_mhi_ctx), GFP_KERNEL); + if (!ipa3_uc_mhi_ctx) { + IPAERR("no mem\n"); + return -ENOMEM; + } + + ipa3_uc_mhi_ctx->ready_cb = ready_cb; + ipa3_uc_mhi_ctx->wakeup_request_cb = wakeup_request_cb; + + memset(&hdlrs, 0, sizeof(hdlrs)); + hdlrs.ipa_uc_loaded_hdlr = ipa3_uc_mhi_ctx->ready_cb; + hdlrs.ipa3_uc_response_hdlr = ipa3_uc_mhi_response_hdlr; + hdlrs.ipa_uc_event_hdlr = ipa3_uc_mhi_event_hdlr; + hdlrs.ipa_uc_event_log_info_hdlr = ipa3_uc_mhi_event_log_info_hdlr; + ipa3_uc_register_handlers(IPA_HW_FEATURE_MHI, &hdlrs); + + IPADBG("Done\n"); + return 0; +} + +void ipa3_uc_mhi_cleanup(void) +{ + struct ipa3_uc_hdlrs null_hdlrs = { 0 }; + + IPADBG("Enter\n"); + + if (!ipa3_uc_mhi_ctx) { + IPAERR("ipa3_uc_mhi_ctx is not initialized\n"); + return; + } + ipa3_uc_register_handlers(IPA_HW_FEATURE_MHI, &null_hdlrs); + kfree(ipa3_uc_mhi_ctx); + ipa3_uc_mhi_ctx = NULL; + + IPADBG("Done\n"); +} + +int ipa3_uc_mhi_init_engine(struct ipa_mhi_msi_info *msi, u32 mmio_addr, + u32 host_ctrl_addr, u32 host_data_addr, u32 first_ch_idx, + u32 first_evt_idx) +{ + int res; + struct ipa_mem_buffer mem; + struct IpaHwMhiInitCmdData_t *init_cmd_data; + struct IpaHwMhiMsiCmdData_t *msi_cmd; + + if (!ipa3_uc_mhi_ctx) { + IPAERR("Not initialized\n"); + return -EFAULT; + } + + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + + res = ipa3_uc_update_hw_flags(0); + if (res) { + IPAERR("ipa3_uc_update_hw_flags failed %d\n", res); + goto disable_clks; + } + + mem.size = sizeof(*init_cmd_data); + mem.base = dma_alloc_coherent(ipa3_ctx->pdev, mem.size, &mem.phys_base, + GFP_KERNEL); + if (!mem.base) { + IPAERR("fail to alloc DMA buff of size %d\n", mem.size); + res = -ENOMEM; + goto disable_clks; + } + init_cmd_data = (struct IpaHwMhiInitCmdData_t *)mem.base; + init_cmd_data->msiAddress = msi->addr_low; + init_cmd_data->mmioBaseAddress = mmio_addr; + init_cmd_data->deviceMhiCtrlBaseAddress = host_ctrl_addr; + init_cmd_data->deviceMhiDataBaseAddress = host_data_addr; + init_cmd_data->firstChannelIndex = first_ch_idx; + init_cmd_data->firstEventRingIndex = first_evt_idx; + res = ipa3_uc_send_cmd((u32)mem.phys_base, IPA_CPU_2_HW_CMD_MHI_INIT, 0, + false, HZ); + if (res) { + IPAERR("ipa3_uc_send_cmd failed %d\n", res); + dma_free_coherent(ipa3_ctx->pdev, mem.size, mem.base, + mem.phys_base); + goto disable_clks; + } + + dma_free_coherent(ipa3_ctx->pdev, mem.size, mem.base, mem.phys_base); + + mem.size = sizeof(*msi_cmd); + mem.base = dma_alloc_coherent(ipa3_ctx->pdev, mem.size, &mem.phys_base, + GFP_KERNEL); + if (!mem.base) { + IPAERR("fail to alloc DMA buff of size %d\n", mem.size); + res = -ENOMEM; + goto disable_clks; + } + + msi_cmd = (struct IpaHwMhiMsiCmdData_t *)mem.base; + msi_cmd->msiAddress_hi = msi->addr_hi; + msi_cmd->msiAddress_low = msi->addr_low; + msi_cmd->msiData = msi->data; + msi_cmd->msiMask = msi->mask; + res = ipa3_uc_send_cmd((u32)mem.phys_base, + IPA_CPU_2_HW_CMD_MHI_UPDATE_MSI, 0, false, HZ); + if (res) { + IPAERR("ipa3_uc_send_cmd failed %d\n", res); + dma_free_coherent(ipa3_ctx->pdev, mem.size, mem.base, + mem.phys_base); + goto disable_clks; + } + + dma_free_coherent(ipa3_ctx->pdev, mem.size, mem.base, mem.phys_base); + + res = 0; + +disable_clks: + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + return res; + +} + +int ipa3_uc_mhi_init_channel(int ipa_ep_idx, int channelHandle, + int contexArrayIndex, int channelDirection) + +{ + int res; + union IpaHwMhiInitChannelCmdData_t init_cmd; + union IpaHwMhiChangeChannelStateResponseData_t uc_rsp; + + if (!ipa3_uc_mhi_ctx) { + IPAERR("Not initialized\n"); + return -EFAULT; + } + + if (ipa_ep_idx < 0 || ipa_ep_idx >= ipa3_ctx->ipa_num_pipes) { + IPAERR("Invalid ipa_ep_idx.\n"); + return -EINVAL; + } + + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + + memset(&uc_rsp, 0, sizeof(uc_rsp)); + uc_rsp.params.state = IPA_HW_MHI_CHANNEL_STATE_RUN; + uc_rsp.params.channelHandle = channelHandle; + ipa3_uc_mhi_ctx->expected_responseOp = + IPA_HW_2_CPU_RESPONSE_MHI_CHANGE_CHANNEL_STATE; + ipa3_uc_mhi_ctx->expected_responseParams = uc_rsp.raw32b; + + memset(&init_cmd, 0, sizeof(init_cmd)); + init_cmd.params.channelHandle = channelHandle; + init_cmd.params.contexArrayIndex = contexArrayIndex; + init_cmd.params.bamPipeId = ipa_ep_idx; + init_cmd.params.channelDirection = channelDirection; + + res = ipa3_uc_send_cmd(init_cmd.raw32b, + IPA_CPU_2_HW_CMD_MHI_INIT_CHANNEL, 0, false, HZ); + if (res) { + IPAERR("ipa3_uc_send_cmd failed %d\n", res); + goto disable_clks; + } + + res = 0; + +disable_clks: + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + return res; +} + + +int ipa3_uc_mhi_reset_channel(int channelHandle) +{ + union IpaHwMhiChangeChannelStateCmdData_t cmd; + union IpaHwMhiChangeChannelStateResponseData_t uc_rsp; + int res; + + if (!ipa3_uc_mhi_ctx) { + IPAERR("Not initialized\n"); + return -EFAULT; + } + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + + memset(&uc_rsp, 0, sizeof(uc_rsp)); + uc_rsp.params.state = IPA_HW_MHI_CHANNEL_STATE_DISABLE; + uc_rsp.params.channelHandle = channelHandle; + ipa3_uc_mhi_ctx->expected_responseOp = + IPA_HW_2_CPU_RESPONSE_MHI_CHANGE_CHANNEL_STATE; + ipa3_uc_mhi_ctx->expected_responseParams = uc_rsp.raw32b; + + memset(&cmd, 0, sizeof(cmd)); + cmd.params.requestedState = IPA_HW_MHI_CHANNEL_STATE_DISABLE; + cmd.params.channelHandle = channelHandle; + res = ipa3_uc_send_cmd(cmd.raw32b, + IPA_CPU_2_HW_CMD_MHI_CHANGE_CHANNEL_STATE, 0, false, HZ); + if (res) { + IPAERR("ipa3_uc_send_cmd failed %d\n", res); + goto disable_clks; + } + + res = 0; + +disable_clks: + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + return res; +} + +int ipa3_uc_mhi_suspend_channel(int channelHandle) +{ + union IpaHwMhiChangeChannelStateCmdData_t cmd; + union IpaHwMhiChangeChannelStateResponseData_t uc_rsp; + int res; + + if (!ipa3_uc_mhi_ctx) { + IPAERR("Not initialized\n"); + return -EFAULT; + } + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + + memset(&uc_rsp, 0, sizeof(uc_rsp)); + uc_rsp.params.state = IPA_HW_MHI_CHANNEL_STATE_SUSPEND; + uc_rsp.params.channelHandle = channelHandle; + ipa3_uc_mhi_ctx->expected_responseOp = + IPA_HW_2_CPU_RESPONSE_MHI_CHANGE_CHANNEL_STATE; + ipa3_uc_mhi_ctx->expected_responseParams = uc_rsp.raw32b; + + memset(&cmd, 0, sizeof(cmd)); + cmd.params.requestedState = IPA_HW_MHI_CHANNEL_STATE_SUSPEND; + cmd.params.channelHandle = channelHandle; + res = ipa3_uc_send_cmd(cmd.raw32b, + IPA_CPU_2_HW_CMD_MHI_CHANGE_CHANNEL_STATE, 0, false, HZ); + if (res) { + IPAERR("ipa3_uc_send_cmd failed %d\n", res); + goto disable_clks; + } + + res = 0; + +disable_clks: + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + return res; +} + +int ipa3_uc_mhi_resume_channel(int channelHandle, bool LPTransitionRejected) +{ + union IpaHwMhiChangeChannelStateCmdData_t cmd; + union IpaHwMhiChangeChannelStateResponseData_t uc_rsp; + int res; + + if (!ipa3_uc_mhi_ctx) { + IPAERR("Not initialized\n"); + return -EFAULT; + } + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + + memset(&uc_rsp, 0, sizeof(uc_rsp)); + uc_rsp.params.state = IPA_HW_MHI_CHANNEL_STATE_RUN; + uc_rsp.params.channelHandle = channelHandle; + ipa3_uc_mhi_ctx->expected_responseOp = + IPA_HW_2_CPU_RESPONSE_MHI_CHANGE_CHANNEL_STATE; + ipa3_uc_mhi_ctx->expected_responseParams = uc_rsp.raw32b; + + memset(&cmd, 0, sizeof(cmd)); + cmd.params.requestedState = IPA_HW_MHI_CHANNEL_STATE_RUN; + cmd.params.channelHandle = channelHandle; + cmd.params.LPTransitionRejected = LPTransitionRejected; + res = ipa3_uc_send_cmd(cmd.raw32b, + IPA_CPU_2_HW_CMD_MHI_CHANGE_CHANNEL_STATE, 0, false, HZ); + if (res) { + IPAERR("ipa3_uc_send_cmd failed %d\n", res); + goto disable_clks; + } + + res = 0; + +disable_clks: + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + return res; +} + +int ipa3_uc_mhi_stop_event_update_channel(int channelHandle) +{ + union IpaHwMhiStopEventUpdateData_t cmd; + int res; + + if (!ipa3_uc_mhi_ctx) { + IPAERR("Not initialized\n"); + return -EFAULT; + } + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + + memset(&cmd, 0, sizeof(cmd)); + cmd.params.channelHandle = channelHandle; + + ipa3_uc_mhi_ctx->expected_responseOp = + IPA_CPU_2_HW_CMD_MHI_STOP_EVENT_UPDATE; + ipa3_uc_mhi_ctx->expected_responseParams = cmd.raw32b; + + res = ipa3_uc_send_cmd(cmd.raw32b, + IPA_CPU_2_HW_CMD_MHI_STOP_EVENT_UPDATE, 0, false, HZ); + if (res) { + IPAERR("ipa3_uc_send_cmd failed %d\n", res); + goto disable_clks; + } + + res = 0; +disable_clks: + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + return res; +} + +int ipa3_uc_mhi_send_dl_ul_sync_info(union IpaHwMhiDlUlSyncCmdData_t *cmd) +{ + int res; + + if (!ipa3_uc_mhi_ctx) { + IPAERR("Not initialized\n"); + return -EFAULT; + } + + IPADBG("isDlUlSyncEnabled=0x%x UlAccmVal=0x%x\n", + cmd->params.isDlUlSyncEnabled, cmd->params.UlAccmVal); + IPADBG("ulMsiEventThreshold=0x%x dlMsiEventThreshold=0x%x\n", + cmd->params.ulMsiEventThreshold, + cmd->params.dlMsiEventThreshold); + + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + + res = ipa3_uc_send_cmd(cmd->raw32b, + IPA_CPU_2_HW_CMD_MHI_DL_UL_SYNC_INFO, 0, false, HZ); + if (res) { + IPAERR("ipa3_uc_send_cmd failed %d\n", res); + goto disable_clks; + } + + res = 0; +disable_clks: + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + return res; +} + +int ipa3_uc_mhi_print_stats(char *dbg_buff, int size) +{ + int nBytes = 0; + int i; + + if (!ipa3_uc_mhi_ctx->mhi_uc_stats_mmio) { + IPAERR("MHI uc stats is not valid\n"); + return 0; + } + + nBytes += scnprintf(&dbg_buff[nBytes], size - nBytes, + "Common Stats:\n"); + PRINT_COMMON_STATS(numULDLSync); + PRINT_COMMON_STATS(numULTimerExpired); + PRINT_COMMON_STATS(numChEvCtxWpRead); + + for (i = 0; i < IPA_HW_MAX_NUMBER_OF_CHANNELS; i++) { + nBytes += scnprintf(&dbg_buff[nBytes], size - nBytes, + "Channel %d Stats:\n", i); + PRINT_CHANNEL_STATS(i, doorbellInt); + PRINT_CHANNEL_STATS(i, reProccesed); + PRINT_CHANNEL_STATS(i, bamFifoFull); + PRINT_CHANNEL_STATS(i, bamFifoEmpty); + PRINT_CHANNEL_STATS(i, bamFifoUsageHigh); + PRINT_CHANNEL_STATS(i, bamFifoUsageLow); + PRINT_CHANNEL_STATS(i, bamInt); + PRINT_CHANNEL_STATS(i, ringFull); + PRINT_CHANNEL_STATS(i, ringEmpty); + PRINT_CHANNEL_STATS(i, ringUsageHigh); + PRINT_CHANNEL_STATS(i, ringUsageLow); + PRINT_CHANNEL_STATS(i, delayedMsi); + PRINT_CHANNEL_STATS(i, immediateMsi); + PRINT_CHANNEL_STATS(i, thresholdMsi); + PRINT_CHANNEL_STATS(i, numSuspend); + PRINT_CHANNEL_STATS(i, numResume); + PRINT_CHANNEL_STATS(i, num_OOB); + PRINT_CHANNEL_STATS(i, num_OOB_timer_expiry); + PRINT_CHANNEL_STATS(i, num_OOB_moderation_timer_start); + PRINT_CHANNEL_STATS(i, num_db_mode_evt); + } + + return nBytes; +} +EXPORT_SYMBOL(ipa3_uc_mhi_print_stats); diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_uc_ntn.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_uc_ntn.c new file mode 100644 index 0000000000..3f83253c6f --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_uc_ntn.c @@ -0,0 +1,717 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. + */ + +#include "ipa_i.h" + +#define IPA_UC_NTN_DB_PA_TX 0x79620DC +#define IPA_UC_NTN_DB_PA_RX 0x79620D8 + +static void ipa3_uc_ntn_event_log_info_handler( +struct IpaHwEventLogInfoData_t *uc_event_top_mmio) +{ + struct Ipa3HwEventInfoData_t *statsPtr = &uc_event_top_mmio->statsInfo; + + if ((uc_event_top_mmio->protocolMask & + (1 << IPA_HW_PROTOCOL_ETH)) == 0) { + IPAERR("NTN protocol missing 0x%x\n", + uc_event_top_mmio->protocolMask); + return; + } + + if (statsPtr->featureInfo[IPA_HW_PROTOCOL_ETH].params.size != + sizeof(struct Ipa3HwStatsNTNInfoData_t)) { + IPAERR("NTN stats sz invalid exp=%zu is=%u\n", + sizeof(struct Ipa3HwStatsNTNInfoData_t), + statsPtr->featureInfo[IPA_HW_PROTOCOL_ETH].params.size); + return; + } + + ipa3_ctx->uc_ntn_ctx.ntn_uc_stats_ofst = + uc_event_top_mmio->statsInfo.baseAddrOffset + + statsPtr->featureInfo[IPA_HW_PROTOCOL_ETH].params.offset; + IPAERR("NTN stats ofst=0x%x\n", ipa3_ctx->uc_ntn_ctx.ntn_uc_stats_ofst); + if (ipa3_ctx->uc_ntn_ctx.ntn_uc_stats_ofst + + sizeof(struct Ipa3HwStatsNTNInfoData_t) >= + ipa3_ctx->ctrl->ipa_reg_base_ofst + + ipahal_get_reg_n_ofst(IPA_SW_AREA_RAM_DIRECT_ACCESS_n, 0) + + ipa3_ctx->smem_sz) { + IPAERR("uc_ntn_stats 0x%x outside SRAM\n", + ipa3_ctx->uc_ntn_ctx.ntn_uc_stats_ofst); + return; + } + + ipa3_ctx->uc_ntn_ctx.ntn_uc_stats_mmio = + ioremap(ipa3_ctx->ipa_wrapper_base + + ipa3_ctx->uc_ntn_ctx.ntn_uc_stats_ofst, + sizeof(struct Ipa3HwStatsNTNInfoData_t)); + if (!ipa3_ctx->uc_ntn_ctx.ntn_uc_stats_mmio) { + IPAERR("fail to ioremap uc ntn stats\n"); + return; + } +} + +/** + * ipa2_get_wdi_stats() - Query WDI statistics from uc + * @stats: [inout] stats blob from client populated by driver + * + * Returns: 0 on success, negative on failure + * + * @note Cannot be called from atomic context + * + */ +int ipa3_get_ntn_stats(struct Ipa3HwStatsNTNInfoData_t *stats) +{ +#define TX_STATS(x, y) stats->tx_ch_stats[x].y = \ + ipa3_ctx->uc_ntn_ctx.ntn_uc_stats_mmio->tx_ch_stats[0].y +#define RX_STATS(x, y) stats->rx_ch_stats[x].y = \ + ipa3_ctx->uc_ntn_ctx.ntn_uc_stats_mmio->rx_ch_stats[x].y + + int i = 0; + + if (unlikely(!ipa3_ctx)) { + IPAERR("IPA driver was not initialized\n"); + return -EINVAL; + } + + if (!stats || !ipa3_ctx->uc_ntn_ctx.ntn_uc_stats_mmio) { + IPAERR("bad parms stats=%pK ntn_stats=%pK\n", + stats, + ipa3_ctx->uc_ntn_ctx.ntn_uc_stats_mmio); + return -EINVAL; + } + + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + + for (i = 0; i < IPA_UC_MAX_NTN_TX_CHANNELS; i++) { + TX_STATS(i, num_pkts_processed); + TX_STATS(i, ring_stats.ringFull); + TX_STATS(i, ring_stats.ringEmpty); + TX_STATS(i, ring_stats.ringUsageHigh); + TX_STATS(i, ring_stats.ringUsageLow); + TX_STATS(i, ring_stats.RingUtilCount); + TX_STATS(i, gsi_stats.bamFifoFull); + TX_STATS(i, gsi_stats.bamFifoEmpty); + TX_STATS(i, gsi_stats.bamFifoUsageHigh); + TX_STATS(i, gsi_stats.bamFifoUsageLow); + TX_STATS(i, gsi_stats.bamUtilCount); + TX_STATS(i, num_db); + TX_STATS(i, num_qmb_int_handled); + TX_STATS(i, ipa_pipe_number); + } + + for (i = 0; i < IPA_UC_MAX_NTN_RX_CHANNELS; i++) { + RX_STATS(i, num_pkts_processed); + RX_STATS(i, ring_stats.ringFull); + RX_STATS(i, ring_stats.ringEmpty); + RX_STATS(i, ring_stats.ringUsageHigh); + RX_STATS(i, ring_stats.ringUsageLow); + RX_STATS(i, ring_stats.RingUtilCount); + RX_STATS(i, gsi_stats.bamFifoFull); + RX_STATS(i, gsi_stats.bamFifoEmpty); + RX_STATS(i, gsi_stats.bamFifoUsageHigh); + RX_STATS(i, gsi_stats.bamFifoUsageLow); + RX_STATS(i, gsi_stats.bamUtilCount); + RX_STATS(i, num_db); + RX_STATS(i, num_qmb_int_handled); + RX_STATS(i, ipa_pipe_number); + } + + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + + return 0; +} + + +int ipa3_ntn_uc_reg_rdyCB(void (*ipa_ready_cb)(void *), void *user_data) +{ + int ret; + + if (!ipa3_ctx) { + IPAERR("IPA ctx is null\n"); + return -ENXIO; + } + + ret = ipa3_uc_state_check(); + if (ret) { + ipa3_ctx->uc_ntn_ctx.uc_ready_cb = ipa_ready_cb; + ipa3_ctx->uc_ntn_ctx.priv = user_data; + return 0; + } + + return -EEXIST; +} +EXPORT_SYMBOL(ipa3_ntn_uc_reg_rdyCB); + +void ipa3_ntn_uc_dereg_rdyCB(void) +{ + ipa3_ctx->uc_ntn_ctx.uc_ready_cb = NULL; + ipa3_ctx->uc_ntn_ctx.priv = NULL; +} +EXPORT_SYMBOL(ipa3_ntn_uc_dereg_rdyCB); + +static void ipa3_uc_ntn_loaded_handler(void) +{ + if (!ipa3_ctx) { + IPAERR("IPA ctx is null\n"); + return; + } + + if (ipa3_ctx->uc_ntn_ctx.uc_ready_cb) { + ipa3_ctx->uc_ntn_ctx.uc_ready_cb( + ipa3_ctx->uc_ntn_ctx.priv); + + ipa3_ctx->uc_ntn_ctx.uc_ready_cb = + NULL; + ipa3_ctx->uc_ntn_ctx.priv = NULL; + } +} + +int ipa3_ntn_init(void) +{ + struct ipa3_uc_hdlrs uc_ntn_cbs = { 0 }; + + uc_ntn_cbs.ipa_uc_event_log_info_hdlr = + ipa3_uc_ntn_event_log_info_handler; + uc_ntn_cbs.ipa_uc_loaded_hdlr = + ipa3_uc_ntn_loaded_handler; + + ipa3_uc_register_handlers(IPA_HW_FEATURE_NTN, &uc_ntn_cbs); + + /* ntn_init */ + ipa3_ctx->uc_ntn_ctx.uc_ready_cb = NULL; + ipa3_ctx->uc_ntn_ctx.priv = NULL; + ipa3_ctx->uc_ntn_ctx.ntn_reg_base_ptr_pa_rd = 0x0; + ipa3_ctx->uc_ntn_ctx.smmu_mapped = 0; + + return 0; +} + +static int ipa3_uc_send_ntn_setup_pipe_cmd( + struct ipa_ntn_setup_info *ntn_info, u8 dir) +{ + int ipa_ep_idx; + int result = 0; + struct ipa_mem_buffer cmd; + struct uc_channel_setup_cmd_hw_ntn *Ntn_params; + struct IpaHwOffloadSetUpCmdData_t *cmd_data; + struct IpaHwOffloadSetUpCmdData_t_v4_0 *cmd_data_v4_0; + + if (ntn_info == NULL) { + IPAERR("invalid input\n"); + return -EINVAL; + } + + ipa_ep_idx = ipa_get_ep_mapping(ntn_info->client); + if (ipa_ep_idx == -1) { + IPAERR("fail to get ep idx.\n"); + return -EFAULT; + } + + IPADBG("client=%d ep=%d\n", ntn_info->client, ipa_ep_idx); + + IPADBG("ring_base_pa = 0x%pa\n", + &ntn_info->ring_base_pa); + IPADBG("ring_base_iova = 0x%pa\n", + &ntn_info->ring_base_iova); + IPADBG("ntn_ring_size = %d\n", ntn_info->ntn_ring_size); + IPADBG("buff_pool_base_pa = 0x%pa\n", &ntn_info->buff_pool_base_pa); + IPADBG("buff_pool_base_iova = 0x%pa\n", &ntn_info->buff_pool_base_iova); + IPADBG("num_buffers = %d\n", ntn_info->num_buffers); + IPADBG("data_buff_size = %d\n", ntn_info->data_buff_size); + IPADBG("tail_ptr_base_pa = 0x%pa\n", &ntn_info->ntn_reg_base_ptr_pa); + IPADBG("db_mode = %d\n", ntn_info->db_mode); + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_0) + cmd.size = sizeof(*cmd_data_v4_0); + else + cmd.size = sizeof(*cmd_data); + cmd.base = dma_alloc_coherent(ipa3_ctx->uc_pdev, cmd.size, + &cmd.phys_base, GFP_KERNEL); + if (cmd.base == NULL) { + IPAERR("fail to get DMA memory.\n"); + return -ENOMEM; + } + + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_0) { + cmd_data_v4_0 = (struct IpaHwOffloadSetUpCmdData_t_v4_0 *) + cmd.base; + cmd_data_v4_0->protocol = IPA_HW_PROTOCOL_ETH; + Ntn_params = &cmd_data_v4_0->SetupCh_params.ntn_params; + } else { + cmd_data = (struct IpaHwOffloadSetUpCmdData_t *)cmd.base; + cmd_data->protocol = IPA_HW_PROTOCOL_ETH; + Ntn_params = &cmd_data->SetupCh_params.ntn_params; + } + + if (ntn_info->smmu_enabled) { + Ntn_params->ring_base_pa = (u32)ntn_info->ring_base_iova; + Ntn_params->buff_pool_base_pa = + (u32)ntn_info->buff_pool_base_iova; + } else { + Ntn_params->ring_base_pa = ntn_info->ring_base_pa; + Ntn_params->buff_pool_base_pa = ntn_info->buff_pool_base_pa; + } + + Ntn_params->ntn_ring_size = ntn_info->ntn_ring_size; + Ntn_params->num_buffers = ntn_info->num_buffers; + Ntn_params->ntn_reg_base_ptr_pa = ntn_info->ntn_reg_base_ptr_pa; + Ntn_params->data_buff_size = ntn_info->data_buff_size; + Ntn_params->db_mode = ntn_info->db_mode; + Ntn_params->ipa_pipe_number = ipa_ep_idx; + Ntn_params->dir = dir; + + result = ipa3_uc_send_cmd((u32)(cmd.phys_base), + IPA_CPU_2_HW_CMD_OFFLOAD_CHANNEL_SET_UP, + IPA_HW_2_CPU_OFFLOAD_CMD_STATUS_SUCCESS, + false, 10*HZ); + if (result) + result = -EFAULT; + + dma_free_coherent(ipa3_ctx->uc_pdev, cmd.size, cmd.base, cmd.phys_base); + return result; +} + +static int ipa3_smmu_map_uc_ntn_pipes(struct ipa_ntn_setup_info *params, + bool map) +{ + struct iommu_domain *smmu_domain; + int result = 0; + int i; + u64 iova; + phys_addr_t pa; + u64 iova_p; + phys_addr_t pa_p; + u32 size_p; + bool map_unmap_once; + + if (params->data_buff_size > PAGE_SIZE) { + IPAERR("invalid data buff size\n"); + return -EINVAL; + } + + /* only map/unmap once the ntn_reg_base_ptr_pa */ + map_unmap_once = (map && ipa3_ctx->uc_ntn_ctx.smmu_mapped == 0) + || (!map && ipa3_ctx->uc_ntn_ctx.smmu_mapped == 1); + + IPADBG(" %s uC regs, smmu_mapped %d\n", + map ? "map" : "unmap", ipa3_ctx->uc_ntn_ctx.smmu_mapped); + + if (map_unmap_once) { + result = ipa3_smmu_map_peer_reg(rounddown( + params->ntn_reg_base_ptr_pa, PAGE_SIZE), + map, IPA_SMMU_CB_UC); + if (result) { + IPAERR("failed to %s uC regs %d\n", + map ? "map" : "unmap", result); + goto fail; + } + /* backup the ntn_reg_base_ptr_pa_r */ + ipa3_ctx->uc_ntn_ctx.ntn_reg_base_ptr_pa_rd = + rounddown(params->ntn_reg_base_ptr_pa, + PAGE_SIZE); + IPADBG(" %s ntn_reg_base_ptr_pa regs 0X%0x smmu_mapped %d\n", + map ? "map" : "unmap", + (unsigned long long) + ipa3_ctx->uc_ntn_ctx.ntn_reg_base_ptr_pa_rd, + ipa3_ctx->uc_ntn_ctx.smmu_mapped); + } + /* update smmu_mapped reference count */ + if (map) { + ipa3_ctx->uc_ntn_ctx.smmu_mapped++; + IPADBG("uc_ntn_ctx.smmu_mapped %d\n", + ipa3_ctx->uc_ntn_ctx.smmu_mapped); + } else { + if (ipa3_ctx->uc_ntn_ctx.smmu_mapped == 0) { + IPAERR("Invalid smmu_mapped %d\n", + ipa3_ctx->uc_ntn_ctx.smmu_mapped); + goto fail; + } else { + ipa3_ctx->uc_ntn_ctx.smmu_mapped--; + IPADBG("uc_ntn_ctx.smmu_mapped %d\n", + ipa3_ctx->uc_ntn_ctx.smmu_mapped); + } + } + + if (params->smmu_enabled) { + IPADBG("smmu is enabled on EMAC\n"); + result = ipa3_smmu_map_peer_buff((u64)params->ring_base_iova, + params->ntn_ring_size, map, params->ring_base_sgt, + IPA_SMMU_CB_UC); + if (result) { + IPAERR("failed to %s ntn ring %d\n", + map ? "map" : "unmap", result); + goto fail_map_ring; + } + result = ipa3_smmu_map_peer_buff( + (u64)params->buff_pool_base_iova, + params->num_buffers * 4, map, + params->buff_pool_base_sgt, IPA_SMMU_CB_UC); + if (result) { + IPAERR("failed to %s pool buffs %d\n", + map ? "map" : "unmap", result); + goto fail_map_buffer_smmu_enabled; + } + } else { + IPADBG("smmu is disabled on EMAC\n"); + result = ipa3_smmu_map_peer_buff((u64)params->ring_base_pa, + params->ntn_ring_size, map, NULL, IPA_SMMU_CB_UC); + if (result) { + IPAERR("failed to %s ntn ring %d\n", + map ? "map" : "unmap", result); + goto fail_map_ring; + } + result = ipa3_smmu_map_peer_buff(params->buff_pool_base_pa, + params->num_buffers * 4, map, NULL, IPA_SMMU_CB_UC); + if (result) { + IPAERR("failed to %s pool buffs %d\n", + map ? "map" : "unmap", result); + goto fail_map_buffer_smmu_disabled; + } + } + + if (ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_AP]) { + IPADBG("AP SMMU is set to s1 bypass\n"); + return 0; + } + + smmu_domain = ipa3_get_smmu_domain(); + if (!smmu_domain) { + IPAERR("invalid smmu domain\n"); + return -EINVAL; + } + + for (i = 0; i < params->num_buffers; i++) { + iova = (u64)params->data_buff_list[i].iova; + pa = (phys_addr_t)params->data_buff_list[i].pa; + IPA_SMMU_ROUND_TO_PAGE(iova, pa, params->data_buff_size, iova_p, + pa_p, size_p); + IPADBG("%s 0x%llx to 0x%pa size %d\n", map ? "mapping" : + "unmapping", iova_p, &pa_p, size_p); + if (map) { + result = ipa3_iommu_map(smmu_domain, iova_p, pa_p, + size_p, IOMMU_READ | IOMMU_WRITE); + if (result) + IPAERR("Fail to map 0x%llx\n", iova); + } else { + result = iommu_unmap(smmu_domain, iova_p, size_p); + if (result != params->data_buff_size) + IPAERR("Fail to unmap 0x%llx\n", iova); + } + if (result) { + if (params->smmu_enabled) + goto fail_map_data_buff_smmu_enabled; + else + goto fail_map_data_buff_smmu_disabled; + } + } + return 0; + +fail_map_data_buff_smmu_enabled: + ipa3_smmu_map_peer_buff((u64)params->buff_pool_base_iova, + params->num_buffers * 4, !map, NULL, IPA_SMMU_CB_UC); + goto fail_map_buffer_smmu_enabled; +fail_map_data_buff_smmu_disabled: + ipa3_smmu_map_peer_buff(params->buff_pool_base_pa, + params->num_buffers * 4, !map, NULL, IPA_SMMU_CB_UC); + goto fail_map_buffer_smmu_disabled; +fail_map_buffer_smmu_enabled: + ipa3_smmu_map_peer_buff((u64)params->ring_base_iova, + params->ntn_ring_size, !map, params->ring_base_sgt, + IPA_SMMU_CB_UC); + goto fail_map_ring; +fail_map_buffer_smmu_disabled: + ipa3_smmu_map_peer_buff((u64)params->ring_base_pa, + params->ntn_ring_size, !map, NULL, IPA_SMMU_CB_UC); +fail_map_ring: + ipa3_smmu_map_peer_reg(rounddown(params->ntn_reg_base_ptr_pa, + PAGE_SIZE), !map, IPA_SMMU_CB_UC); +fail: + return result; +} + +/** + * ipa3_setup_uc_ntn_pipes() - setup uc offload pipes + */ +int ipa3_setup_uc_ntn_pipes(struct ipa_ntn_conn_in_params *in, + ipa_notify_cb notify, void *priv, u8 hdr_len, + struct ipa_ntn_conn_out_params *outp) +{ + struct ipa3_ep_context *ep_ul; + struct ipa3_ep_context *ep_dl; + int ipa_ep_idx_ul; + int ipa_ep_idx_dl; + int result = 0; + bool is_vlan_mode; + + if (in == NULL) { + IPAERR("invalid input\n"); + return -EINVAL; + } + + ipa_ep_idx_ul = ipa_get_ep_mapping(in->ul.client); + if (ipa_ep_idx_ul == IPA_EP_NOT_ALLOCATED || + ipa_ep_idx_ul >= ipa3_get_max_num_pipes()) { + IPAERR("fail to alloc UL EP ipa_ep_idx_ul=%d\n", + ipa_ep_idx_ul); + return -EFAULT; + } + + ipa_ep_idx_dl = ipa_get_ep_mapping(in->dl.client); + if (ipa_ep_idx_dl == IPA_EP_NOT_ALLOCATED || + ipa_ep_idx_dl >= ipa3_get_max_num_pipes()) { + IPAERR("fail to alloc DL EP ipa_ep_idx_dl=%d\n", + ipa_ep_idx_dl); + return -EFAULT; + } + + ep_ul = &ipa3_ctx->ep[ipa_ep_idx_ul]; + ep_dl = &ipa3_ctx->ep[ipa_ep_idx_dl]; + + if (ep_ul->valid || ep_dl->valid) { + IPAERR("EP already allocated ul:%d dl:%d\n", + ep_ul->valid, ep_dl->valid); + return -EFAULT; + } + + memset(ep_ul, 0, offsetof(struct ipa3_ep_context, sys)); + memset(ep_dl, 0, offsetof(struct ipa3_ep_context, sys)); + + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + + /* setup ul ep cfg */ + ep_ul->valid = 1; + ep_ul->client = in->ul.client; + ep_ul->client_notify = notify; + ep_ul->priv = priv; + + memset(&ep_ul->cfg, 0, sizeof(ep_ul->cfg)); + ep_ul->cfg.nat.nat_en = IPA_SRC_NAT; + ep_ul->cfg.hdr.hdr_len = hdr_len; + ep_ul->cfg.mode.mode = IPA_BASIC; + + result = ipa_is_vlan_mode(IPA_VLAN_IF_ETH, &is_vlan_mode); + if (is_vlan_mode) { + ep_ul->cfg.hdr.hdr_ofst_metadata_valid = 1; + ep_ul->cfg.hdr.hdr_ofst_metadata = ETH_HLEN; + ep_ul->cfg.hdr.hdr_metadata_reg_valid = false; + } + + if (ipa3_cfg_ep(ipa_ep_idx_ul, &ep_ul->cfg)) { + IPAERR("fail to setup ul pipe cfg\n"); + result = -EFAULT; + goto fail; + } + + result = ipa3_smmu_map_uc_ntn_pipes(&in->ul, true); + if (result) { + IPAERR("failed to map SMMU for UL %d\n", result); + goto fail; + } + + result = ipa3_enable_data_path(ipa_ep_idx_ul); + if (result) { + IPAERR("Enable data path failed res=%d pipe=%d.\n", result, + ipa_ep_idx_ul); + result = -EFAULT; + goto fail_smmu_unmap_ul; + } + + if (ipa3_uc_send_ntn_setup_pipe_cmd(&in->ul, IPA_NTN_RX_DIR)) { + IPAERR("fail to send cmd to uc for ul pipe\n"); + result = -EFAULT; + goto fail_disable_dp_ul; + } + ipa3_install_dflt_flt_rules(ipa_ep_idx_ul); + /* Rx: IPA_UC_MAILBOX_m_n m = 1, n =3 mmio*/ + outp->ul_uc_db_iomem = ipa3_ctx->mmio + + ipahal_get_reg_mn_ofst(IPA_UC_MAILBOX_m_n, + 1, 3); + ep_ul->uc_offload_state |= IPA_UC_OFFLOAD_CONNECTED; + IPADBG("client %d (ep: %d) connected\n", in->ul.client, + ipa_ep_idx_ul); + + /* setup dl ep cfg */ + ep_dl->valid = 1; + ep_dl->client = in->dl.client; + memset(&ep_dl->cfg, 0, sizeof(ep_ul->cfg)); + ep_dl->cfg.nat.nat_en = IPA_BYPASS_NAT; + ep_dl->cfg.hdr.hdr_len = hdr_len; + ep_dl->cfg.mode.mode = IPA_BASIC; + + if (ipa3_cfg_ep(ipa_ep_idx_dl, &ep_dl->cfg)) { + IPAERR("fail to setup dl pipe cfg\n"); + result = -EFAULT; + goto fail_disable_dp_ul; + } + + result = ipa3_smmu_map_uc_ntn_pipes(&in->dl, true); + if (result) { + IPAERR("failed to map SMMU for DL %d\n", result); + goto fail_disable_dp_ul; + } + + result = ipa3_enable_data_path(ipa_ep_idx_dl); + if (result) { + IPAERR("Enable data path failed res=%d pipe=%d.\n", result, + ipa_ep_idx_dl); + result = -EFAULT; + goto fail_smmu_unmap_dl; + } + + if (ipa3_uc_send_ntn_setup_pipe_cmd(&in->dl, IPA_NTN_TX_DIR)) { + IPAERR("fail to send cmd to uc for dl pipe\n"); + result = -EFAULT; + goto fail_disable_dp_dl; + } + /* Tx: IPA_UC_MAILBOX_m_n m = 1, n =4 mmio */ + outp->dl_uc_db_iomem = ipa3_ctx->mmio + + ipahal_get_reg_mn_ofst(IPA_UC_MAILBOX_m_n, + 1, 4); + ep_dl->uc_offload_state |= IPA_UC_OFFLOAD_CONNECTED; + + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + IPADBG("client %d (ep: %d) connected\n", in->dl.client, + ipa_ep_idx_dl); + + return 0; + +fail_disable_dp_dl: + ipa3_disable_data_path(ipa_ep_idx_dl); +fail_smmu_unmap_dl: + ipa3_smmu_map_uc_ntn_pipes(&in->dl, false); +fail_disable_dp_ul: + ipa3_disable_data_path(ipa_ep_idx_ul); +fail_smmu_unmap_ul: + ipa3_smmu_map_uc_ntn_pipes(&in->ul, false); +fail: + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + return result; +} +EXPORT_SYMBOL(ipa3_setup_uc_ntn_pipes); + +/** + * ipa3_tear_down_uc_offload_pipes() - tear down uc offload pipes + */ + +int ipa3_tear_down_uc_offload_pipes(int ipa_ep_idx_ul, + int ipa_ep_idx_dl, struct ipa_ntn_conn_in_params *params) +{ + struct ipa_mem_buffer cmd; + struct ipa3_ep_context *ep_ul, *ep_dl; + struct IpaHwOffloadCommonChCmdData_t *cmd_data; + struct IpaHwOffloadCommonChCmdData_t_v4_0 *cmd_data_v4_0; + union uc_channel_teardown_cmd_hw_ntn *tear; + int result = 0; + + IPADBG("ep_ul = %d\n", ipa_ep_idx_ul); + IPADBG("ep_dl = %d\n", ipa_ep_idx_dl); + + if (ipa_ep_idx_ul == IPA_EP_NOT_ALLOCATED || + ipa_ep_idx_ul >= IPA3_MAX_NUM_PIPES) { + IPAERR("ipa_ep_idx_ul %d invalid\n", + ipa_ep_idx_ul); + return -EFAULT; + } + + if (ipa_ep_idx_dl == IPA_EP_NOT_ALLOCATED || + ipa_ep_idx_dl >= IPA3_MAX_NUM_PIPES) { + IPAERR("ep ipa_ep_idx_dl %d invalid\n", + ipa_ep_idx_dl); + return -EFAULT; + } + + ep_ul = &ipa3_ctx->ep[ipa_ep_idx_ul]; + ep_dl = &ipa3_ctx->ep[ipa_ep_idx_dl]; + + if (ep_ul->uc_offload_state != IPA_UC_OFFLOAD_CONNECTED || + ep_dl->uc_offload_state != IPA_UC_OFFLOAD_CONNECTED) { + IPAERR("channel bad state: ul %d dl %d\n", + ep_ul->uc_offload_state, ep_dl->uc_offload_state); + return -EFAULT; + } + + atomic_set(&ep_ul->disconnect_in_progress, 1); + atomic_set(&ep_dl->disconnect_in_progress, 1); + + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_0) + cmd.size = sizeof(*cmd_data_v4_0); + else + cmd.size = sizeof(*cmd_data); + cmd.base = dma_alloc_coherent(ipa3_ctx->uc_pdev, cmd.size, + &cmd.phys_base, GFP_KERNEL); + if (cmd.base == NULL) { + IPAERR("fail to get DMA memory.\n"); + return -ENOMEM; + } + + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_0) { + cmd_data_v4_0 = (struct IpaHwOffloadCommonChCmdData_t_v4_0 *) + cmd.base; + cmd_data_v4_0->protocol = IPA_HW_PROTOCOL_ETH; + tear = &cmd_data_v4_0->CommonCh_params.ntn_params; + } else { + cmd_data = (struct IpaHwOffloadCommonChCmdData_t *)cmd.base; + cmd_data->protocol = IPA_HW_PROTOCOL_ETH; + tear = &cmd_data->CommonCh_params.ntn_params; + } + + /* teardown the DL pipe */ + ipa3_disable_data_path(ipa_ep_idx_dl); + /* + * Reset ep before sending cmd otherwise disconnect + * during data transfer will result into + * enormous suspend interrupts + */ + memset(&ipa3_ctx->ep[ipa_ep_idx_dl], 0, sizeof(struct ipa3_ep_context)); + IPADBG("dl client (ep: %d) disconnected\n", ipa_ep_idx_dl); + tear->params.ipa_pipe_number = ipa_ep_idx_dl; + result = ipa3_uc_send_cmd((u32)(cmd.phys_base), + IPA_CPU_2_HW_CMD_OFFLOAD_CHANNEL_TEAR_DOWN, + IPA_HW_2_CPU_OFFLOAD_CMD_STATUS_SUCCESS, + false, 10*HZ); + if (result) { + IPAERR("fail to tear down dl pipe\n"); + result = -EFAULT; + goto fail; + } + + /* unmap the DL pipe */ + result = ipa3_smmu_map_uc_ntn_pipes(¶ms->dl, false); + if (result) { + IPAERR("failed to unmap SMMU for DL %d\n", result); + goto fail; + } + + /* teardown the UL pipe */ + ipa3_disable_data_path(ipa_ep_idx_ul); + + tear->params.ipa_pipe_number = ipa_ep_idx_ul; + result = ipa3_uc_send_cmd((u32)(cmd.phys_base), + IPA_CPU_2_HW_CMD_OFFLOAD_CHANNEL_TEAR_DOWN, + IPA_HW_2_CPU_OFFLOAD_CMD_STATUS_SUCCESS, + false, 10*HZ); + if (result) { + IPAERR("fail to tear down ul pipe\n"); + result = -EFAULT; + goto fail; + } + + /* unmap the UL pipe */ + result = ipa3_smmu_map_uc_ntn_pipes(¶ms->ul, false); + if (result) { + IPAERR("failed to unmap SMMU for UL %d\n", result); + goto fail; + } + + ipa3_delete_dflt_flt_rules(ipa_ep_idx_ul); + memset(&ipa3_ctx->ep[ipa_ep_idx_ul], 0, sizeof(struct ipa3_ep_context)); + IPADBG("ul client (ep: %d) disconnected\n", ipa_ep_idx_ul); + +fail: + dma_free_coherent(ipa3_ctx->uc_pdev, cmd.size, cmd.base, cmd.phys_base); + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + return result; +} +EXPORT_SYMBOL(ipa3_tear_down_uc_offload_pipes); diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_uc_offload_i.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_uc_offload_i.h new file mode 100644 index 0000000000..7cdc939270 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_uc_offload_i.h @@ -0,0 +1,866 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. + * + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _IPA_UC_OFFLOAD_I_H_ +#define _IPA_UC_OFFLOAD_I_H_ + +#include "ipa.h" +#include "ipa_i.h" + +/* + * Neutrino protocol related data structures + */ + +#define IPA_UC_MAX_NTN_TX_CHANNELS 2 +#define IPA_UC_MAX_NTN_RX_CHANNELS 2 + +#define IPA_NTN_TX_DIR 1 +#define IPA_NTN_RX_DIR 2 + +#define MAX_CH_STATS_SUPPORTED 5 +#define DIR_CONSUMER 0 +#define DIR_PRODUCER 1 + +#define MAX_AQC_CHANNELS 2 +#define MAX_RTK_CHANNELS 2 +#define MAX_NTN_CHANNELS 2 +#define MAX_11AD_CHANNELS 5 +#define MAX_WDI2_CHANNELS 2 +#define MAX_WDI3_CHANNELS 3 +#define MAX_MHIP_CHANNELS 4 +#define MAX_USB_CHANNELS 2 + +#define BW_QUOTA_MONITORING_MAX_ADDR_OFFSET 8 +#define BW_MONITORING_MAX_THRESHOLD 3 +/** + * @brief Enum value determined based on the feature it + * corresponds to + * +----------------+----------------+ + * | 3 bits | 5 bits | + * +----------------+----------------+ + * | HW_FEATURE | OPCODE | + * +----------------+----------------+ + * + */ +#define FEATURE_ENUM_VAL(feature, opcode) ((feature << 5) | opcode) +#define EXTRACT_UC_FEATURE(value) (value >> 5) + +#define IPA_HW_NUM_FEATURES 0x8 + +/** + * enum ipa3_hw_features - Values that represent the features supported + * in IPA HW + * @IPA_HW_FEATURE_COMMON : Feature related to common operation of IPA HW + * @IPA_HW_FEATURE_MHI : Feature related to MHI operation in IPA HW + * @IPA_HW_FEATURE_POWER_COLLAPSE: Feature related to IPA Power collapse + * @IPA_HW_FEATURE_WDI : Feature related to WDI operation in IPA HW + * @IPA_HW_FEATURE_NTN : Feature related to NTN operation in IPA HW + * @IPA_HW_FEATURE_OFFLOAD : Feature related to several protocols operation in + * IPA HW. use protocol field to + * determine (e.g. IPA_HW_PROTOCOL_11ad). + */ +enum ipa3_hw_features { + IPA_HW_FEATURE_COMMON = 0x0, + IPA_HW_FEATURE_MHI = 0x1, + IPA_HW_FEATURE_POWER_COLLAPSE = 0x2, + IPA_HW_FEATURE_WDI = 0x3, + IPA_HW_FEATURE_ZIP = 0x4, + IPA_HW_FEATURE_NTN = 0x5, + IPA_HW_FEATURE_OFFLOAD = 0x6, + IPA_HW_FEATURE_RTP = 0x8, + IPA_HW_FEATURE_MAX = IPA_HW_NUM_FEATURES +}; + +/** + * enum ipa4_hw_protocol - Values that represent the protocols supported + * in IPA HW when using the IPA_HW_FEATURE_OFFLOAD feature. + * @IPA_HW_FEATURE_COMMON : protocol related to common operation of IPA HW + * @IPA_HW_PROTOCOL_AQC : protocol related to AQC operation in IPA HW + * @IPA_HW_PROTOCOL_11ad: protocol related to 11ad operation in IPA HW + * @IPA_HW_PROTOCOL_WDI : protocol related to WDI operation in IPA HW + * @IPA_HW_PROTOCOL_WDI3: protocol related to WDI3 operation in IPA HW + * @IPA_HW_PROTOCOL_ETH : protocol related to ETH operation in IPA HW + * @IPA_HW_PROTOCOL_MHIP: protocol related to MHIP operation in IPA HW + * @IPA_HW_PROTOCOL_USB : protocol related to USB operation in IPA HW + * @IPA_HW_PROTOCOL_RTK : protocol related to RTK operation in IPA HW + * @IPA_HW_PROTOCOL_NTN3 : protocol related to NTN3 operation in IPA HW + */ +enum ipa4_hw_protocol { + IPA_HW_PROTOCOL_COMMON = 0x0, + IPA_HW_PROTOCOL_AQC = 0x1, + IPA_HW_PROTOCOL_11ad = 0x2, + IPA_HW_PROTOCOL_WDI = 0x3, + IPA_HW_PROTOCOL_WDI3 = 0x4, + IPA_HW_PROTOCOL_ETH = 0x5, + IPA_HW_PROTOCOL_MHIP = 0x6, + IPA_HW_PROTOCOL_USB = 0x7, + IPA_HW_PROTOCOL_RTK = 0x9, + IPA_HW_PROTOCOL_NTN3 = 0xA, + IPA_HW_PROTOCOL_MAX +}; + +/** + * enum ipa3_hw_2_cpu_events - Values that represent HW event to be sent to CPU. + * @IPA_HW_2_CPU_EVENT_NO_OP : No event present + * @IPA_HW_2_CPU_EVENT_ERROR : Event specify a system error is detected by the + * device + * @IPA_HW_2_CPU_EVENT_LOG_INFO : Event providing logging specific information + * @IPA_HW_2_CPU_POST_EVNT_RING_NOTIFICAITON : Event to notify APPS + */ +enum ipa3_hw_2_cpu_events { + IPA_HW_2_CPU_EVENT_NO_OP = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_COMMON, 0), + IPA_HW_2_CPU_EVENT_ERROR = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_COMMON, 1), + IPA_HW_2_CPU_EVENT_LOG_INFO = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_COMMON, 2), + IPA_HW_2_CPU_EVNT_RING_NOTIFY = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_COMMON, 3), +}; + +/** + * enum ipa3_hw_errors - Common error types. + * @IPA_HW_ERROR_NONE : No error persists + * @IPA_HW_INVALID_DOORBELL_ERROR : Invalid data read from doorbell + * @IPA_HW_DMA_ERROR : Unexpected DMA error + * @IPA_HW_FATAL_SYSTEM_ERROR : HW has crashed and requires reset. + * @IPA_HW_INVALID_OPCODE : Invalid opcode sent + * @IPA_HW_INVALID_PARAMS : Invalid params for the requested command + * @IPA_HW_GSI_CH_NOT_EMPTY_FAILURE : GSI channel emptiness validation failed + * @IPA_HW_CONS_STOP_FAILURE : NTN/ETH CONS stop failed + * @IPA_HW_PROD_STOP_FAILURE : NTN/ETH PROD stop failed + */ +enum ipa3_hw_errors { + IPA_HW_ERROR_NONE = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_COMMON, 0), + IPA_HW_INVALID_DOORBELL_ERROR = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_COMMON, 1), + IPA_HW_DMA_ERROR = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_COMMON, 2), + IPA_HW_FATAL_SYSTEM_ERROR = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_COMMON, 3), + IPA_HW_INVALID_OPCODE = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_COMMON, 4), + IPA_HW_INVALID_PARAMS = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_COMMON, 5), + IPA_HW_CONS_DISABLE_CMD_GSI_STOP_FAILURE = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_COMMON, 6), + IPA_HW_PROD_DISABLE_CMD_GSI_STOP_FAILURE = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_COMMON, 7), + IPA_HW_GSI_CH_NOT_EMPTY_FAILURE = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_COMMON, 8), + IPA_HW_CONS_STOP_FAILURE = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_COMMON, 9), + IPA_HW_PROD_STOP_FAILURE = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_COMMON, 10) +}; + +/** + * struct IpaHwSharedMemCommonMapping_t - Structure referring to the common + * section in 128B shared memory located in offset zero of SW Partition in IPA + * SRAM. + * @cmdOp : CPU->HW command opcode. See IPA_CPU_2_HW_COMMANDS + * @cmdParams : CPU->HW command parameter lower 32bit. + * @cmdParams_hi : CPU->HW command parameter higher 32bit. + * of parameters (immediate parameters) and point on structure in system memory + * (in such case the address must be accessible for HW) + * @responseOp : HW->CPU response opcode. See IPA_HW_2_CPU_RESPONSES + * @responseParams : HW->CPU response parameter. The parameter filed can hold 32 + * bits of parameters (immediate parameters) and point on structure in system + * memory + * @eventOp : HW->CPU event opcode. See IPA_HW_2_CPU_EVENTS + * @eventParams : HW->CPU event parameter. The parameter filed can hold 32 + * bits of parameters (immediate parameters) and point on + * structure in system memory + * @firstErrorAddress : Contains the address of first error-source on SNOC + * @hwState : State of HW. The state carries information regarding the + * error type. + * @warningCounter : The warnings counter. The counter carries information + * regarding non fatal errors in HW + * @interfaceVersionCommon : The Common interface version as reported by HW + * @responseParams_1: offset addr for uC stats + * + * The shared memory is used for communication between IPA HW and CPU. + */ +struct IpaHwSharedMemCommonMapping_t { +#ifdef CONFIG_IPA_RTP + u16 cmdOp; +#else + u8 cmdOp; + u8 reserved_01; +#endif + u16 reserved_03_02; + u32 cmdParams; + u32 cmdParams_hi; + u8 responseOp; + u8 reserved_0D; + u16 reserved_0F_0E; + u32 responseParams; + u8 eventOp; + u8 reserved_15; + u16 reserved_17_16; + u32 eventParams; + u32 firstErrorAddress; + u8 hwState; + u8 warningCounter; + u16 reserved_23_22; + u16 interfaceVersionCommon; + u16 reserved_27_26; + u32 responseParams_1; +} __packed; + +/** + * union Ipa3HwFeatureInfoData_t - parameters for stats/config blob + * + * @offset : Location of a feature within the EventInfoData + * @size : Size of the feature + */ +union Ipa3HwFeatureInfoData_t { + struct IpaHwFeatureInfoParams_t { + u32 offset:16; + u32 size:16; + } __packed params; + u32 raw32b; +} __packed; + +/** + * union IpaHwErrorEventData_t - HW->CPU Common Events + * @errorType : Entered when a system error is detected by the HW. Type of + * error is specified by IPA_HW_ERRORS + * @reserved : Reserved + */ +union IpaHwErrorEventData_t { + struct IpaHwErrorEventParams_t { + u32 errorType:8; + u32 reserved:24; + } __packed params; + u32 raw32b; +} __packed; + +/** + * struct Ipa3HwEventInfoData_t - Structure holding the parameters for + * statistics and config info + * + * @baseAddrOffset : Base Address Offset of the statistics or config + * structure from IPA_WRAPPER_BASE + * @Ipa3HwFeatureInfoData_t : Location and size of each feature within + * the statistics or config structure + * + * @note Information about each feature in the featureInfo[] + * array is populated at predefined indices per the IPA_HW_FEATURES + * enum definition + */ +struct Ipa3HwEventInfoData_t { + u32 baseAddrOffset; + union Ipa3HwFeatureInfoData_t featureInfo[IPA_HW_NUM_FEATURES]; +} __packed; + +/** + * struct IpaHwEventLogInfoData_t - Structure holding the parameters for + * IPA_HW_2_CPU_EVENT_LOG_INFO Event + * + * @protocolMask : Mask indicating the protocols enabled in HW. + * Refer IPA_HW_FEATURE_MASK + * @circBuffBaseAddrOffset : Base Address Offset of the Circular Event + * Log Buffer structure + * @statsInfo : Statistics related information + * @configInfo : Configuration related information + * + * @note The offset location of this structure from IPA_WRAPPER_BASE + * will be provided as Event Params for the IPA_HW_2_CPU_EVENT_LOG_INFO + * Event + */ +struct IpaHwEventLogInfoData_t { + u32 protocolMask; + u32 circBuffBaseAddrOffset; + struct Ipa3HwEventInfoData_t statsInfo; + struct Ipa3HwEventInfoData_t configInfo; + +} __packed; + +/** + * struct ipa3_uc_ntn_ctx + * @ntn_uc_stats_ofst: Neutrino stats offset + * @ntn_uc_stats_mmio: Neutrino stats + * @priv: private data of client + * @uc_ready_cb: uc Ready cb + */ +struct ipa3_uc_ntn_ctx { + u32 ntn_uc_stats_ofst; + struct Ipa3HwStatsNTNInfoData_t *ntn_uc_stats_mmio; + void *priv; + ipa_uc_ready_cb uc_ready_cb; + phys_addr_t ntn_reg_base_ptr_pa_rd; + u32 smmu_mapped; +}; + +/** + * enum ipa3_hw_ntn_channel_states - Values that represent NTN + * channel state machine. + * @IPA_HW_NTN_CHANNEL_STATE_INITED_DISABLED : Channel is + * initialized but disabled + * @IPA_HW_NTN_CHANNEL_STATE_RUNNING : Channel is running. + * Entered after SET_UP_COMMAND is processed successfully + * @IPA_HW_NTN_CHANNEL_STATE_ERROR : Channel is in error state + * @IPA_HW_NTN_CHANNEL_STATE_INVALID : Invalid state. Shall not + * be in use in operational scenario + * + * These states apply to both Tx and Rx paths. These do not reflect the + * sub-state the state machine may be in. + */ +enum ipa3_hw_ntn_channel_states { + IPA_HW_NTN_CHANNEL_STATE_INITED_DISABLED = 1, + IPA_HW_NTN_CHANNEL_STATE_RUNNING = 2, + IPA_HW_NTN_CHANNEL_STATE_ERROR = 3, + IPA_HW_NTN_CHANNEL_STATE_INVALID = 0xFF +}; + +/** + * enum ipa3_hw_ntn_channel_errors - List of NTN Channel error + * types. This is present in the event param + * @IPA_HW_NTN_CH_ERR_NONE: No error persists + * @IPA_HW_NTN_TX_FSM_ERROR: Error in the state machine + * transition + * @IPA_HW_NTN_TX_COMP_RE_FETCH_FAIL: Error while calculating + * num RE to bring + * @IPA_HW_NTN_RX_RING_WP_UPDATE_FAIL: Write pointer update + * failed in Rx ring + * @IPA_HW_NTN_RX_FSM_ERROR: Error in the state machine + * transition + * @IPA_HW_NTN_RX_CACHE_NON_EMPTY: + * @IPA_HW_NTN_CH_ERR_RESERVED: + * + * These states apply to both Tx and Rx paths. These do not + * reflect the sub-state the state machine may be in. + */ +enum ipa3_hw_ntn_channel_errors { + IPA_HW_NTN_CH_ERR_NONE = 0, + IPA_HW_NTN_TX_RING_WP_UPDATE_FAIL = 1, + IPA_HW_NTN_TX_FSM_ERROR = 2, + IPA_HW_NTN_TX_COMP_RE_FETCH_FAIL = 3, + IPA_HW_NTN_RX_RING_WP_UPDATE_FAIL = 4, + IPA_HW_NTN_RX_FSM_ERROR = 5, + IPA_HW_NTN_RX_CACHE_NON_EMPTY = 6, + IPA_HW_NTN_CH_ERR_RESERVED = 0xFF +}; + + +/** + * struct uc_channel_setup_cmd_hw_ntn - Ntn setup command data + * @ring_base_pa: physical address of the base of the Tx/Rx NTN + * ring + * @buff_pool_base_pa: physical address of the base of the Tx/Rx + * buffer pool + * @ntn_ring_size: size of the Tx/Rx NTN ring + * @num_buffers: Rx/tx buffer pool size + * @ntn_reg_base_ptr_pa: physical address of the Tx/Rx NTN + * Ring's tail pointer + * @ipa_pipe_number: IPA pipe number that has to be used for the + * Tx/Rx path + * @dir: Tx/Rx Direction + * @data_buff_size: size of the each data buffer allocated in + * DDR + */ +struct uc_channel_setup_cmd_hw_ntn { + u32 ring_base_pa; + u32 buff_pool_base_pa; + u16 ntn_ring_size; + u16 num_buffers; + u32 ntn_reg_base_ptr_pa; + u8 ipa_pipe_number; + u8 dir; + u16 data_buff_size; + u8 db_mode; + u8 reserved1; + u16 reserved2; + +} __packed; + +/** + * struct uc_channel_teardown_cmd_hw_ntn - Structure holding the + * parameters for Ntn Tear down command data params + * + *@ipa_pipe_number: IPA pipe number. This could be Tx or an Rx pipe + */ +union uc_channel_teardown_cmd_hw_ntn { + struct IpaHwNtnCommonChCmdParams_t { + u32 ipa_pipe_number :8; + u32 reserved :24; + } __packed params; + uint32_t raw32b; +} __packed; + +/** + * struct NTN3RxInfoData_t - NTN Structure holding the Rx pipe + * information + * + *@num_pkts_processed: Number of packets processed - cumulative + * + *@ring_stats: + *@gsi_stats: + *@num_db: Number of times the doorbell was rung + *@num_qmb_int_handled: Number of QMB interrupts handled + *@ipa_pipe_number: The IPA Rx/Tx pipe number. + */ +struct NTN3RxInfoData_t { + u32 num_pkts_processed; + struct IpaHwRingStats_t ring_stats; + struct IpaHwBamStats_t gsi_stats; + u32 num_db; + u32 num_qmb_int_handled; + u32 ipa_pipe_number; +} __packed; + + +/** + * struct NTN3TxInfoData_t - Structure holding the NTN Tx channel + * Ensure that this is always word aligned + * + *@num_pkts_processed: Number of packets processed - cumulative + *@tail_ptr_val: Latest value of doorbell written to copy engine + *@num_db_fired: Number of DB from uC FW to Copy engine + * + *@tx_comp_ring_stats: + *@bam_stats: + *@num_db: Number of times the doorbell was rung + *@num_qmb_int_handled: Number of QMB interrupts handled + */ +struct NTN3TxInfoData_t { + u32 num_pkts_processed; + struct IpaHwRingStats_t ring_stats; + struct IpaHwBamStats_t gsi_stats; + u32 num_db; + u32 num_qmb_int_handled; + u32 ipa_pipe_number; +} __packed; + + +/** + * struct Ipa3HwStatsNTNInfoData_t - Structure holding the NTN Tx + * channel Ensure that this is always word aligned + * + */ +struct Ipa3HwStatsNTNInfoData_t { + struct NTN3RxInfoData_t rx_ch_stats[IPA_UC_MAX_NTN_RX_CHANNELS]; + struct NTN3TxInfoData_t tx_ch_stats[IPA_UC_MAX_NTN_TX_CHANNELS]; +} __packed; + + +/* + * uC offload related data structures + */ +#define IPA_UC_OFFLOAD_CONNECTED BIT(0) +#define IPA_UC_OFFLOAD_ENABLED BIT(1) +#define IPA_UC_OFFLOAD_RESUMED BIT(2) + +/** + * enum ipa_cpu_2_hw_offload_commands - Values that represent + * the offload commands from CPU + * @IPA_CPU_2_HW_CMD_OFFLOAD_CHANNEL_SET_UP : Command to set up + * Offload protocol's Tx/Rx Path + * @IPA_CPU_2_HW_CMD_OFFLOAD_CHANNEL_TEAR_DOWN : Command to tear + * down Offload protocol's Tx/ Rx Path + * @IPA_CPU_2_HW_CMD_PERIPHERAL_INIT :Command to initialize peripheral + * @IPA_CPU_2_HW_CMD_PERIPHERAL_DEINIT : Command to deinitialize peripheral + * @IPA_CPU_2_HW_CMD_OFFLOAD_STATS_ALLOC: Command to start the + * uC stats calculation for a particular protocol + * @IPA_CPU_2_HW_CMD_OFFLOAD_STATS_DEALLOC: Command to stop the + * uC stats calculation for a particular protocol + * @IPA_CPU_2_HW_CMD_QUOTA_MONITORING : Command to start the Quota monitoring + * @IPA_CPU_2_HW_CMD_BW_MONITORING : Command to start the BW monitoring + */ +enum ipa_cpu_2_hw_offload_commands { + IPA_CPU_2_HW_CMD_OFFLOAD_CHANNEL_SET_UP = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_OFFLOAD, 1), + IPA_CPU_2_HW_CMD_OFFLOAD_CHANNEL_TEAR_DOWN = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_OFFLOAD, 2), + IPA_CPU_2_HW_CMD_PERIPHERAL_INIT = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_OFFLOAD, 3), + IPA_CPU_2_HW_CMD_PERIPHERAL_DEINIT = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_OFFLOAD, 4), + IPA_CPU_2_HW_CMD_OFFLOAD_STATS_ALLOC = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_OFFLOAD, 5), + IPA_CPU_2_HW_CMD_OFFLOAD_STATS_DEALLOC = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_OFFLOAD, 6), + IPA_CPU_2_HW_CMD_QUOTA_MONITORING = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_OFFLOAD, 7), + IPA_CPU_2_HW_CMD_BW_MONITORING = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_OFFLOAD, 8), +}; + +/** + * struct IpaHwOffloadStatsDeAllocCmdData_t - protocol info for + * uC stats stop + * @protocol: Enum that indicates the protocol type + */ +struct IpaHwOffloadStatsDeAllocCmdData_t { + uint32_t protocol; +} __packed; + +/** + * enum ipa3_hw_offload_channel_states - Values that represent + * offload channel state machine. + * @IPA_HW_OFFLOAD_CHANNEL_STATE_INITED_DISABLED : Channel is + * initialized but disabled + * @IPA_HW_OFFLOAD_CHANNEL_STATE_RUNNING : Channel is running. + * Entered after SET_UP_COMMAND is processed successfully + * @IPA_HW_OFFLOAD_CHANNEL_STATE_ERROR : Channel is in error state + * @IPA_HW_OFFLOAD_CHANNEL_STATE_INVALID : Invalid state. Shall not + * be in use in operational scenario + * + * These states apply to both Tx and Rx paths. These do not + * reflect the sub-state the state machine may be in + */ +enum ipa3_hw_offload_channel_states { + IPA_HW_OFFLOAD_CHANNEL_STATE_INITED_DISABLED = 1, + IPA_HW_OFFLOAD_CHANNEL_STATE_RUNNING = 2, + IPA_HW_OFFLOAD_CHANNEL_STATE_ERROR = 3, + IPA_HW_OFFLOAD_CHANNEL_STATE_INVALID = 0xFF +}; + + +/** + * enum ipa3_hw_2_cpu_cmd_resp_status - Values that represent + * offload related command response status to be sent to CPU. + */ +enum ipa3_hw_2_cpu_offload_cmd_resp_status { + IPA_HW_2_CPU_OFFLOAD_CMD_STATUS_SUCCESS = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_OFFLOAD, 0), + IPA_HW_2_CPU_OFFLOAD_MAX_TX_CHANNELS = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_OFFLOAD, 1), + IPA_HW_2_CPU_OFFLOAD_TX_RING_OVERRUN_POSSIBILITY = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_OFFLOAD, 2), + IPA_HW_2_CPU_OFFLOAD_TX_RING_SET_UP_FAILURE = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_OFFLOAD, 3), + IPA_HW_2_CPU_OFFLOAD_TX_RING_PARAMS_UNALIGNED = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_OFFLOAD, 4), + IPA_HW_2_CPU_OFFLOAD_UNKNOWN_TX_CHANNEL = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_OFFLOAD, 5), + IPA_HW_2_CPU_OFFLOAD_TX_INVALID_FSM_TRANSITION = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_OFFLOAD, 6), + IPA_HW_2_CPU_OFFLOAD_TX_FSM_TRANSITION_ERROR = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_OFFLOAD, 7), + IPA_HW_2_CPU_OFFLOAD_MAX_RX_CHANNELS = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_OFFLOAD, 8), + IPA_HW_2_CPU_OFFLOAD_RX_RING_PARAMS_UNALIGNED = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_OFFLOAD, 9), + IPA_HW_2_CPU_OFFLOAD_RX_RING_SET_UP_FAILURE = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_OFFLOAD, 10), + IPA_HW_2_CPU_OFFLOAD_UNKNOWN_RX_CHANNEL = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_OFFLOAD, 11), + IPA_HW_2_CPU_OFFLOAD_RX_INVALID_FSM_TRANSITION = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_OFFLOAD, 12), + IPA_HW_2_CPU_OFFLOAD_RX_FSM_TRANSITION_ERROR = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_OFFLOAD, 13), + IPA_HW_2_CPU_OFFLOAD_RX_RING_OVERRUN_POSSIBILITY = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_OFFLOAD, 14), +}; + +/** + * struct uc_channel_setup_cmd_hw_11ad - 11ad setup channel + * command data + * @dir: Direction RX/TX + * @wifi_ch: 11ad peripheral pipe number + * @gsi_ch: GSI Channel number + * @reserved: 8 bytes padding + * @wifi_hp_addr_lsb: Head/Tail pointer absolute address + * @wifi_hp_addr_msb: Head/Tail pointer absolute address + */ +struct uc_channel_setup_cmd_hw_11ad { + u8 dir; + u8 wifi_ch; + u8 gsi_ch; + u8 reserved; + u32 wifi_hp_addr_lsb; + u32 wifi_hp_addr_msb; +} __packed; + + +/** + * struct uc_channel_teardown_cmd_hw_11ad - 11ad tear down + * channel command data + * @gsi_ch: GSI Channel number + * @reserved_0: padding + * @reserved_1: padding + */ +struct uc_channel_teardown_cmd_hw_11ad { + u8 gsi_ch; + u8 reserved_0; + u16 reserved_1; +} __packed; + +/** + * struct IpaHw11adInitCmdData_t - 11ad peripheral init command data + * @periph_baddr_lsb: Peripheral Base Address LSB (pa/IOVA) + * @periph_baddr_msb: Peripheral Base Address MSB (pa/IOVA) + */ +struct IpaHw11adInitCmdData_t { + u32 periph_baddr_lsb; + u32 periph_baddr_msb; +} __packed; + +/** + * struct IpaHw11adDeinitCmdData_t - 11ad peripheral deinit command data + * @reserved: Reserved for future + */ +struct IpaHw11adDeinitCmdData_t { + u32 reserved; +} __packed; + +/** + * struct uc_channel_setup_cmd_hw_rtk - rtk setup channel + * command data + * @dir: Direction RX/TX + * @gsi_ch: GSI Channel number + * @reserved: 16 bytes padding + */ +struct uc_channel_setup_cmd_hw_rtk { + uint8_t dir; + uint8_t gsi_ch; + uint16_t reserved; +} __packed; + +/** + * struct uc_channel_teardown_cmd_hw_rtk - rtk tear down channel + * command data + * @gsi_ch: GSI Channel number + * @reserved_0: padding + * @reserved_1: padding + */ +struct uc_channel_teardown_cmd_hw_rtk { + uint8_t gsi_ch; + uint8_t reserved_0; + uint16_t reserved_1; +} __packed; + +/** + * struct IpaHwAQCInitCmdData_t - AQC peripheral init command data + * @periph_baddr_lsb: Peripheral Base Address LSB (pa/IOVA) + * @periph_baddr_msb: Peripheral Base Address MSB (pa/IOVA) + */ +struct IpaHwAQCInitCmdData_t { + u32 periph_baddr_lsb; + u32 periph_baddr_msb; +} __packed; + +/** + * struct IpaHwAQCDeinitCmdData_t - AQC peripheral deinit command data + * @reserved: Reserved for future + */ +struct IpaHwAQCDeinitCmdData_t { + u32 reserved; +} __packed; + +/** + * struct uc_channel_setup_cmd_hw_aqc - AQC setup channel + * command data + * @dir: Direction RX/TX + * @aqc_ch: aqc channel number + * @gsi_ch: GSI Channel number + * @reserved: 8 bytes padding + */ +struct uc_channel_setup_cmd_hw_aqc { + u8 dir; + u8 aqc_ch; + u8 gsi_ch; + u8 reserved; +} __packed; + +/** + * struct uc_channel_teardown_cmd_hw_aqc - AQC tear down channel + * command data + * @gsi_ch: GSI Channel number + * @reserved_0: padding + * @reserved_1: padding + */ +struct uc_channel_teardown_cmd_hw_aqc { + u8 gsi_ch; + u8 reserved_0; + u16 reserved_1; +} __packed; + +/** + * struct uc_channel_setup_cmd_hw - Structure holding the + * parameters for IPA_CPU_2_HW_CMD_OFFLOAD_CHANNEL_SET_UP + * + * + */ +union uc_channel_setup_cmd_hw { + struct uc_channel_setup_cmd_hw_ntn ntn_params; + struct uc_channel_setup_cmd_hw_aqc aqc_params; + struct uc_channel_setup_cmd_hw_11ad w11ad_params; + struct uc_channel_setup_cmd_hw_rtk rtk_params; +} __packed; + +struct IpaHwOffloadSetUpCmdData_t { + u8 protocol; + union uc_channel_setup_cmd_hw SetupCh_params; +} __packed; + +struct IpaCommonMonitoringParams_t { + /* max 8 */ + uint8_t Num; + /* Sampling interval in ms */ + uint8_t Interval; + uint16_t Offset[BW_QUOTA_MONITORING_MAX_ADDR_OFFSET]; +} __packed; // 18 bytes + +struct IpaWdiQuotaMonitoringParams_t { + uint64_t Quota; + struct IpaCommonMonitoringParams_t info; +} __packed; + +struct IpaWdiBwMonitoringParams_t { + uint64_t BwThreshold[BW_MONITORING_MAX_THRESHOLD]; + struct IpaCommonMonitoringParams_t info; + uint8_t NumThresh; + /*Variable to Start Stop Bw Monitoring*/ + uint8_t Stop; +} __packed; + +union IpaQuotaMonitoringParams_t { + struct IpaWdiQuotaMonitoringParams_t WdiQM; +} __packed; + +union IpaBwMonitoringParams_t { + struct IpaWdiBwMonitoringParams_t WdiBw; +} __packed; + +struct IpaQuotaMonitoring_t { + /* indicates below union needs to be interpreted */ + uint32_t protocol; + union IpaQuotaMonitoringParams_t params; +} __packed; + +struct IpaBwMonitoring_t { + /* indicates below union needs to be interpreted */ + uint32_t protocol; + union IpaBwMonitoringParams_t params; +} __packed; + + +struct IpaHwOffloadSetUpCmdData_t_v4_0 { + u32 protocol; + union uc_channel_setup_cmd_hw SetupCh_params; +} __packed; + +/** + * struct uc_channel_teardown_cmd_hw - Structure holding the + * parameters for IPA_CPU_2_HW_CMD_OFFLOAD_CHANNEL_TEAR_DOWN + * + * + */ +union uc_channel_teardown_cmd_hw { + union uc_channel_teardown_cmd_hw_ntn ntn_params; + struct uc_channel_teardown_cmd_hw_aqc aqc_params; + struct uc_channel_teardown_cmd_hw_rtk rtk_params; + struct uc_channel_teardown_cmd_hw_11ad w11ad_params; +} __packed; + +struct IpaHwOffloadCommonChCmdData_t { + u8 protocol; + union uc_channel_teardown_cmd_hw CommonCh_params; +} __packed; + +enum EVENT_2_CPU_OPCODE { + BW_NOTIFY = 0x0, + QUOTA_NOTIFY = 0x1, + IPA_HOLB_BAD_PERIPHERAL_EVENT = 0x2, + IPA_HOLB_PERIPHERAL_RECOVERED_EVENT = 0x3 +}; + +struct EventStructureBwMonitoring_t { + uint32_t ThresholdIndex; + uint64_t throughput; +} __packed; + +struct EventStructureQuotaMonitoring_t { + /* indicate threshold has reached */ + uint32_t ThreasholdReached; + uint64_t usage; +} __packed; + + +/** + * @brief Structure holding the parameters for + * IPA_HW_2_CPU_EVENT_PERIPH_BAD and + * IPA_HW_2_CPU_EVENT_PERIPH_RECOVERED events. + * + * @param ipaProdGsiChid bad OR recovered GSI chid + * @param EE EE that the chid belongs to + */ +struct EventStructureHolbMonitoring_t { + uint32_t ipaProdGsiChid :8; + uint32_t EE :8; + uint32_t reserved :16; + uint32_t qTimerLSB; + uint32_t qTimerMSB; +} __packed; + +union EventParamFormat_t { + struct EventStructureBwMonitoring_t bw_param; + struct EventStructureQuotaMonitoring_t quota_param; + struct EventStructureHolbMonitoring_t holb_notify_param; +} __packed; + +/* EVT RING STRUCTURE + * | Word| bit | Field | + * ----------------------------- + * | 0 |0 - 8| Protocol| + * | |8 - 16| Reserved0| + * | |16 - 24| Opcode | + * | |24 - 31| Reserved1| + * | 1 |0 - 31| Word1 | + * | 2 |0 - 31| Word2 | + * | 3 |0 - 31| Word3 | + */ +struct eventElement_t { + uint8_t Protocol; + uint8_t Reserved0; + uint8_t Opcode; + uint8_t Reserved1; + union EventParamFormat_t Value; +} __packed; + +struct IpaHwOffloadCommonChCmdData_t_v4_0 { + u32 protocol; + union uc_channel_teardown_cmd_hw CommonCh_params; +} __packed; + + +/** + * union IpaHwPeripheralInitCmd - Structure holding the parameters + * for IPA_CPU_2_HW_CMD_PERIPHERAL_INIT + * + */ +union IpaHwPeripheralInitCmd { + struct IpaHw11adInitCmdData_t W11AdInit_params; + struct IpaHwAQCInitCmdData_t AqcInit_params; +} __packed; + +struct IpaHwPeripheralInitCmdData_t { + u32 protocol; + union IpaHwPeripheralInitCmd Init_params; +} __packed; + +/** + * union IpaHwPeripheralDeinitCmd - Structure holding the parameters + * for IPA_CPU_2_HW_CMD_PERIPHERAL_DEINIT + * + */ +union IpaHwPeripheralDeinitCmd { + struct IpaHw11adDeinitCmdData_t W11AdDeinit_params; + struct IpaHwAQCDeinitCmdData_t AqcDeinit_params; +} __packed; + +struct IpaHwPeripheralDeinitCmdData_t { + u32 protocol; + union IpaHwPeripheralDeinitCmd PeripheralDeinit_params; + +} __packed; + +#endif /* _IPA_UC_OFFLOAD_I_H_ */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_uc_rtp.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_uc_rtp.c new file mode 100644 index 0000000000..8618431f3b --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_uc_rtp.c @@ -0,0 +1,1076 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ipa_i.h" +#include +#include +#include + +/* ER ==> (16B * 512 entries ) * 4 frames = 8k *4 = 32k */ +#define IPA_UC_PROD_EVENT_RING_SIZE 512 +/* TR ==> (16B *512 entries per frame * 6 frames) * 4 prodpipes=48k *4 = 192k */ +#define IPA_UC_PROD_TRANSFER_RING_SIZE (512 * 3) +/* TR==> 1024B * 8B TRE * 2 pipes */ +#define IPA_UC_CON_TRANSFER_RING_SIZE 1024 + +#define MAX_NUMBER_OF_STREAMS 4 +#define MAX_NUMBER_OF_PARTITIONS MAX_NUMBER_OF_STREAMS + +#define MAX_UC_PROD_PIPES 4 +#define MAX_UC_CONS_PIPES 2 + +#define MAX_UC_PROD_PIPES_TR_INDEX MAX_UC_PROD_PIPES +#define MAX_UC_PROD_PIPES_ER_INDEX (MAX_UC_PROD_PIPES_TR_INDEX + MAX_UC_PROD_PIPES) +#define MAX_UC_CONS_PIPES_TR_INDEX (MAX_UC_PROD_PIPES_ER_INDEX + MAX_UC_CONS_PIPES) + +#define MAX_SYNX_FENCE_SESSION_NAME 64 +#define DMA_DIR DMA_BIDIRECTIONAL + +#define GSI_TRE_RE_XFER 2 +#define TRE_SIZE 2048 + +MODULE_IMPORT_NS(DMA_BUF); + +enum ipa3_cpu_2_hw_rtp_commands { + IPA_CPU_2_HW_CMD_RTP_TUPLE_INFO = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_RTP, 0), + IPA_CPU_2_HW_CMD_RTP_ADD_TEMP_BUFF_INFO = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_RTP, 1), + IPA_CPU_2_HW_CMD_RTP_ADD_BIT_STREAM_BUFF = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_RTP, 2), + IPA_CPU_2_HW_CMD_RTP_GET_HFI_STRUCT = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_RTP, 3), + IPA_CPU_2_HW_CMD_RTP_START_STREAM = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_RTP, 4), + IPA_CPU_2_HW_CMD_RTP_STOP_STREAM = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_RTP, 5), + IPA_CPU_2_HW_CMD_RTP_TEAR_DOWN_STREAM = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_RTP, 6), + IPA_CPU_2_HW_CMD_RTP_UPDATE_STREAM_INFO = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_RTP, 7), + IPA_CPU_2_HW_CMD_RTP_SIGNAL_FENCE = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_RTP, 8), + IPA_CPU_2_HW_CMD_RTP_PIPE_SETUP = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_RTP, 10), + IPA_CPU_2_HW_CMD_RTP_REMOVE_STREAM = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_RTP, 11), +}; + +struct dma_address_map_table { + struct dma_buf *dma_buf_list[2]; + struct dma_buf_attachment *attachment[2]; + struct sg_table *sgt[2]; +}; + +/* Bitstream and meta buffer dma addresses list */ +struct list_node { + struct list_head list_obj; + struct dma_address_map_table *data; +}; + +struct prod_pipe_tre { + uint64_t buffer_ptr; + uint16_t buf_len; + uint16_t resvd1; + uint16_t chain:1; + uint16_t resvd4:7; + uint16_t ieob:1; + uint16_t ieot:1; + uint16_t bei:1; + uint16_t resvd3:5; + uint8_t re_type; + uint8_t resvd2; +} __packed; + +struct con_pipe_tre { + uint16_t bufferIndex; + uint16_t offset2Payload; + uint16_t payloadSize:16; + uint8_t valid:1; + uint8_t ieot:1; + uint8_t tre_type:2; + uint8_t reserved0:4; + uint8_t last_tre:1; + uint8_t reserved1:7; +} __packed; + +struct temp_buff_info { + uint64_t temp_buff_pa; + uint32_t temp_buff_size; +} __packed; + +struct rtp_pipe_setup_cmd_data { + struct temp_buff_info uc_prod_tr[MAX_UC_PROD_PIPES]; + struct temp_buff_info uc_prod_er[MAX_UC_PROD_PIPES]; + struct temp_buff_info uc_cons_tr[MAX_UC_CONS_PIPES]; +} __packed; + +struct hfi_queue_info { + u64 hfi_queue_addr; + u32 hfi_queue_payload_size; + u64 queue_header_start_addr; + u64 queue_payload_start_addr; +} __packed; + +struct temp_buffer_info { + uint64_t temp_buff_pa; + uint32_t temp_buff_size; +} __packed; + +struct uc_temp_buffer_info { + uint16_t number_of_partitions; + struct temp_buffer_info buffer_info[MAX_NUMBER_OF_PARTITIONS]; +} __packed; + +struct er_tr_to_free { + void *cpu_address_prod_tr[MAX_UC_PROD_PIPES]; + void *cpu_address_prod_er[MAX_UC_PROD_PIPES]; + void *cpu_address_cons_tr[MAX_UC_CONS_PIPES]; + struct rtp_pipe_setup_cmd_data rtp_tr_er; + uint8_t prod_tr_no_buffs; + uint8_t prod_er_no_buffs; + uint8_t cons_tr_no_buffs; +} __packed; + +struct er_tr_to_free er_tr_cpu_addresses; +void *cpu_address[NO_OF_BUFFS]; +struct uc_temp_buffer_info tb_info; +struct list_head mapped_bs_buff_lst[MAX_NUMBER_OF_STREAMS]; +struct synx_session *glob_synx_session_ptr; + +int ipa3_uc_send_tuple_info_cmd(struct traffic_tuple_info *data) +{ + int result = 0; + struct ipa_mem_buffer cmd; + struct traffic_tuple_info *cmd_data; + + if (!data) { + IPAERR("Invalid params.\n"); + return -EINVAL; + } + + cmd.size = sizeof(*cmd_data); + cmd.base = dma_alloc_coherent(ipa3_ctx->uc_pdev, cmd.size, + &cmd.phys_base, GFP_KERNEL); + if (cmd.base == NULL) { + IPAERR("failed to alloc DMA memory.\n"); + return -ENOMEM; + } + + cmd_data = (struct traffic_tuple_info *)cmd.base; + cmd_data->ts_info.no_of_openframe = data->ts_info.no_of_openframe; + cmd_data->ts_info.max_pkt_frame = data->ts_info.max_pkt_frame; + cmd_data->ts_info.stream_type = data->ts_info.stream_type; + cmd_data->ts_info.reorder_timeout = data->ts_info.reorder_timeout; + cmd_data->ts_info.num_slices_per_frame = data->ts_info.num_slices_per_frame; + cmd_data->ip_type = data->ip_type; + if (cmd_data->ip_type) { + cmd_data->ip_info.ipv6.src_port_number = data->ip_info.ipv6.src_port_number; + cmd_data->ip_info.ipv6.dst_port_number = data->ip_info.ipv6.dst_port_number; + memcpy(cmd_data->ip_info.ipv6.src_ip, data->ip_info.ipv6.src_ip, 16); + memcpy(cmd_data->ip_info.ipv6.dst_ip, data->ip_info.ipv6.dst_ip, 16); + cmd_data->ip_info.ipv6.protocol = data->ip_info.ipv6.protocol; + } else { + cmd_data->ip_info.ipv4.src_port_number = data->ip_info.ipv4.src_port_number; + cmd_data->ip_info.ipv4.dst_port_number = data->ip_info.ipv4.dst_port_number; + cmd_data->ip_info.ipv4.src_ip = data->ip_info.ipv4.src_ip; + cmd_data->ip_info.ipv4.dst_ip = data->ip_info.ipv4.dst_ip; + cmd_data->ip_info.ipv4.protocol = data->ip_info.ipv4.protocol; + } + + IPADBG("Sending uc CMD RTP_TUPLE_INFO\n"); + result = ipa3_uc_send_cmd((u32)(cmd.phys_base), + IPA_CPU_2_HW_CMD_RTP_TUPLE_INFO, + 0, + false, 10*HZ); + if (result) { + IPAERR("uc send tuple info cmd failed\n"); + result = -EPERM; + } + + dma_free_coherent(ipa3_ctx->uc_pdev, cmd.size, cmd.base, cmd.phys_base); + return result; +} + +int ipa3_tuple_info_cmd_to_wlan_uc(struct traffic_tuple_info *req, u32 stream_id) +{ + int result = 0; + struct ipa_wdi_opt_dpath_flt_add_cb_params flt_add_req; + + if (!req) { + IPAERR("Invalid params.\n"); + return -EINVAL; + } + + if (!atomic_read(&ipa3_ctx->ipa_xr_wdi_flt_rsv_status)) { + result = ipa_xr_wdi_opt_dpath_rsrv_filter_req(); + if (result) { + IPAERR("filter reservation failed at WLAN %d\n", result); + return result; + } + } + + memset(&flt_add_req, 0, sizeof(struct ipa_wdi_opt_dpath_flt_add_cb_params)); + flt_add_req.num_tuples = 1; + flt_add_req.flt_info[0].version = req->ip_type; + if (!flt_add_req.flt_info[0].version) { + flt_add_req.flt_info[0].ipv4_addr.ipv4_saddr = req->ip_info.ipv4.src_ip; + flt_add_req.flt_info[0].ipv4_addr.ipv4_daddr = req->ip_info.ipv4.dst_ip; + flt_add_req.flt_info[0].protocol = req->ip_info.ipv4.protocol; + flt_add_req.flt_info[0].sport = req->ip_info.ipv4.src_port_number; + flt_add_req.flt_info[0].dport = req->ip_info.ipv4.dst_port_number; + IPADBG("IPv4 saddr:0x%x, daddr:0x%x\n", + flt_add_req.flt_info[0].ipv4_addr.ipv4_saddr, + flt_add_req.flt_info[0].ipv4_addr.ipv4_daddr); + } else { + memcpy(flt_add_req.flt_info[0].ipv6_addr.ipv6_saddr, + req->ip_info.ipv6.src_ip, + sizeof(req->ip_info.ipv6.src_ip)); + memcpy(flt_add_req.flt_info[0].ipv6_addr.ipv6_daddr, + req->ip_info.ipv6.dst_ip, + sizeof(req->ip_info.ipv6.dst_ip)); + flt_add_req.flt_info[0].protocol = req->ip_info.ipv6.protocol; + flt_add_req.flt_info[0].sport = req->ip_info.ipv6.src_port_number; + flt_add_req.flt_info[0].dport = req->ip_info.ipv6.dst_port_number; + IPADBG("IPv6 saddr:0x%x:%x:%x:%x, daddr:0x%x:%x:%x:%x\n", + flt_add_req.flt_info[0].ipv6_addr.ipv6_saddr[0], + flt_add_req.flt_info[0].ipv6_addr.ipv6_saddr[1], + flt_add_req.flt_info[0].ipv6_addr.ipv6_saddr[2], + flt_add_req.flt_info[0].ipv6_addr.ipv6_saddr[3], + flt_add_req.flt_info[0].ipv6_addr.ipv6_daddr[0], + flt_add_req.flt_info[0].ipv6_addr.ipv6_daddr[1], + flt_add_req.flt_info[0].ipv6_addr.ipv6_daddr[2], + flt_add_req.flt_info[0].ipv6_addr.ipv6_daddr[3]); + } + + result = ipa3_uc_send_tuple_info_cmd(req); + if (result) { + IPAERR("Fail to send tuple info cmd to uc\n"); + return -EPERM; + } + else + IPADBG("send tuple info cmd to uc succeeded\n"); + + result = ipa_xr_wdi_opt_dpath_add_filter_req(&flt_add_req, stream_id); + if (result) { + IPAERR("Fail to send tuple info cmd to wlan\n"); + return -EPERM; + } + + return result; +} + +int ipa3_uc_send_remove_stream_cmd(struct remove_bitstream_buffers *data) +{ + int result = 0; + struct ipa_mem_buffer cmd; + struct remove_bitstream_buffers *cmd_data; + + if (!data) { + IPAERR("Invalid params.\n"); + return -EINVAL; + } + + result = ipa_xr_wdi_opt_dpath_remove_filter_req(data->stream_id); + if (result) { + IPAERR("Failed to remove wlan filter of stream ID %d\n", data->stream_id); + return result; + } + + cmd.size = sizeof(*cmd_data); + cmd.base = dma_alloc_coherent(ipa3_ctx->uc_pdev, cmd.size, + &cmd.phys_base, GFP_KERNEL); + if (cmd.base == NULL) { + IPAERR("failed to alloc DMA memory.\n"); + return -ENOMEM; + } + + cmd_data = (struct remove_bitstream_buffers *)cmd.base; + cmd_data->stream_id = data->stream_id; + IPADBG("Sending uc CMD RTP_REMOVE_STREAM\n"); + result = ipa3_uc_send_cmd((u32)(cmd.phys_base), + IPA_CPU_2_HW_CMD_RTP_REMOVE_STREAM, + 0, + false, 10*HZ); + if (result) { + IPAERR("uc send remove stream cmd failed\n"); + result = -EPERM; + } + + dma_free_coherent(ipa3_ctx->uc_pdev, cmd.size, cmd.base, cmd.phys_base); + return result; +} + +int ipa3_uc_send_add_bitstream_buffers_cmd(struct bitstream_buffers_to_uc *data) +{ + int result = 0; + struct ipa_mem_buffer cmd; + struct bitstream_buffers_to_uc *cmd_data = NULL; + + if (!data) { + IPAERR("Invalid params.\n"); + return -EINVAL; + } + + cmd.size = sizeof(*cmd_data); + cmd.base = dma_alloc_coherent(ipa3_ctx->uc_pdev, cmd.size, + &cmd.phys_base, GFP_KERNEL); + if (cmd.base == NULL) { + IPAERR("failed to alloc DMA memory.\n"); + return -ENOMEM; + } + + cmd_data = (struct bitstream_buffers_to_uc *)cmd.base; + cmd_data->buff_cnt = data->buff_cnt; + cmd_data->cookie = data->cookie; + memcpy(cmd_data->bs_info, data->bs_info, (cmd_data->buff_cnt * + sizeof(struct bitstream_buffer_info_to_uc))); + IPADBG("Sending uc CMD RTP_ADD_BIT_STREAM_BUFF\n"); + result = ipa3_uc_send_cmd((u32)(cmd.phys_base), + IPA_CPU_2_HW_CMD_RTP_ADD_BIT_STREAM_BUFF, + 0, + false, 10*HZ); + if (result) { + IPAERR("uc send bitstream buffers info cmd failed\n"); + result = -EPERM; + } + + dma_free_coherent(ipa3_ctx->uc_pdev, cmd.size, cmd.base, cmd.phys_base); + return result; +} + +int ipa3_uc_send_temp_buffers_info_cmd(struct uc_temp_buffer_info *data) +{ + int result = 0; + struct ipa_mem_buffer cmd; + struct uc_temp_buffer_info *cmd_data = NULL; + + if (!data) { + IPAERR("Invalid params.\n"); + return -EINVAL; + } + + cmd.size = sizeof(*cmd_data); + cmd.base = dma_alloc_coherent(ipa3_ctx->uc_pdev, cmd.size, + &cmd.phys_base, GFP_KERNEL); + if (cmd.base == NULL) { + IPAERR("failed to alloc DMA memory.\n"); + return -ENOMEM; + } + + cmd_data = (struct uc_temp_buffer_info *)cmd.base; + cmd_data->number_of_partitions = data->number_of_partitions; + memcpy(cmd_data->buffer_info, data->buffer_info, + (sizeof(struct temp_buffer_info)*cmd_data->number_of_partitions)); + IPADBG("Sending uc CMD RTP_ADD_TEMP_BUFF_INFO\n"); + result = ipa3_uc_send_cmd((u32)(cmd.phys_base), + IPA_CPU_2_HW_CMD_RTP_ADD_TEMP_BUFF_INFO, + 0, + false, 10*HZ); + if (result) { + IPAERR("uc send temp buffers info cmd failed\n"); + result = -EPERM; + } + + dma_free_coherent(ipa3_ctx->uc_pdev, cmd.size, cmd.base, cmd.phys_base); + return result; +} + +void ipa3_free_uc_temp_buffs(unsigned int no_of_buffs) +{ + unsigned int indx = 0; + + for (indx = 0; indx < no_of_buffs; indx++) { + dma_free_attrs(ipa3_ctx->uc_pdev, + tb_info.buffer_info[indx].temp_buff_size, cpu_address[indx], + tb_info.buffer_info[indx].temp_buff_pa, + (DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_FORCE_CONTIGUOUS)); + } + + IPADBG("freed uc temp buffs\n"); +} + +int ipa3_alloc_temp_buffs_to_uc(unsigned int size, unsigned int no_of_buffs) +{ + void *cpu_addr = NULL; + unsigned int indx = 0; + dma_addr_t phys_base; + + if (size < 1 || no_of_buffs < 1) { + IPAERR("Invallid params\n"); + return -EINVAL; + } + + for (indx = 0; indx < no_of_buffs; indx++) { + cpu_addr = dma_alloc_attrs(ipa3_ctx->uc_pdev, size, &phys_base, + GFP_KERNEL, DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_FORCE_CONTIGUOUS); + if (!cpu_addr) { + IPAERR("No mem for tmp buffs\n"); + ipa3_free_uc_temp_buffs(indx); + return -ENOMEM; + } + + cpu_address[indx] = cpu_addr; + tb_info.buffer_info[indx].temp_buff_pa = phys_base; + tb_info.buffer_info[indx].temp_buff_size = size; + tb_info.number_of_partitions += 1; + } + + IPADBG("allocated mem for temp buffs\n"); + return ipa3_uc_send_temp_buffers_info_cmd(&tb_info); +} + +int ipa3_uc_send_RTPPipeSetup_cmd(struct rtp_pipe_setup_cmd_data *rtp_cmd_data) +{ + int result = 0; + struct ipa_mem_buffer cmd; + struct rtp_pipe_setup_cmd_data *cmd_data = NULL; + + if (!rtp_cmd_data) { + IPAERR("Invalid params.\n"); + return -EINVAL; + } + + cmd.size = sizeof(*cmd_data); + cmd.base = dma_alloc_coherent(ipa3_ctx->uc_pdev, cmd.size, + &cmd.phys_base, GFP_KERNEL); + if (cmd.base == NULL) { + IPAERR("failed to alloc DMA memory.\n"); + return -ENOMEM; + } + + cmd_data = (struct rtp_pipe_setup_cmd_data *)cmd.base; + memcpy(cmd_data->uc_prod_tr, rtp_cmd_data->uc_prod_tr, + (sizeof(struct temp_buff_info) * MAX_UC_PROD_PIPES)); + memcpy(cmd_data->uc_prod_er, rtp_cmd_data->uc_prod_er, + (sizeof(struct temp_buff_info) * MAX_UC_PROD_PIPES)); + memcpy(cmd_data->uc_cons_tr, rtp_cmd_data->uc_cons_tr, + (sizeof(struct temp_buff_info) * MAX_UC_CONS_PIPES)); + IPADBG("Sending uc CMD RTP_PIPE_SETUP\n"); + result = ipa3_uc_send_cmd((u32)(cmd.phys_base), + IPA_CPU_2_HW_CMD_RTP_PIPE_SETUP, + 0, + false, 10*HZ); + if (result) { + IPAERR("send RTP pipe setup cmd failed\n"); + result = -EPERM; + } + + dma_free_coherent(ipa3_ctx->uc_pdev, cmd.size, cmd.base, cmd.phys_base); + return result; +} + +static int ipa3_uc_setup_prod_pipe_transfer_ring( + struct rtp_pipe_setup_cmd_data *rtp_cmd_data, int idx) +{ + struct ipa_mem_buffer ring; + struct prod_pipe_tre *tr = NULL; + int val = 0; + u64 next = 0; + + if (!rtp_cmd_data) { + IPAERR("Invalid params.\n"); + return -EINVAL; + } + + ring.size = sizeof(struct prod_pipe_tre) * IPA_UC_PROD_TRANSFER_RING_SIZE; + ring.base = dma_alloc_coherent(ipa3_ctx->uc_pdev, ring.size, + &ring.phys_base, GFP_KERNEL); + if (ring.base == NULL) { + IPAERR("dma alloc coherent failed.\n"); + return -ENOMEM; + } + + tr = (struct prod_pipe_tre *)ring.base; + next = tb_info.buffer_info[idx].temp_buff_pa; + + for (val = 0; val < IPA_UC_PROD_TRANSFER_RING_SIZE; val++) { + tr->buffer_ptr = next; + tr->buf_len = TRE_SIZE; + tr->re_type = GSI_TRE_RE_XFER; + tr->bei = 0; + tr->ieot = 1; + next = tr->buffer_ptr + 2048; + tr++; + } + + rtp_cmd_data->uc_prod_tr[idx].temp_buff_pa = ring.phys_base; + rtp_cmd_data->uc_prod_tr[idx].temp_buff_size = ring.size; + er_tr_cpu_addresses.cpu_address_prod_tr[idx] = ring.base; + er_tr_cpu_addresses.prod_tr_no_buffs += 1; + IPADBG("prod pipe transfer ring setup done\n"); + return 0; +} + +static int ipa3_uc_setup_prod_pipe_event_ring( + struct rtp_pipe_setup_cmd_data *rtp_cmd_data, int index) +{ + struct ipa_mem_buffer ring; + + if (!rtp_cmd_data) { + IPAERR("Invalid params.\n"); + return -EINVAL; + } + + ring.size = sizeof(struct prod_pipe_tre) * IPA_UC_PROD_EVENT_RING_SIZE; + ring.base = dma_alloc_coherent(ipa3_ctx->uc_pdev, ring.size, + &ring.phys_base, GFP_KERNEL); + if (ring.base == NULL) { + IPAERR("dma alloc coherent failed.\n"); + return -EFAULT; + } + + rtp_cmd_data->uc_prod_er[index].temp_buff_pa = ring.phys_base; + rtp_cmd_data->uc_prod_er[index].temp_buff_size = ring.size; + er_tr_cpu_addresses.cpu_address_prod_er[index] = ring.base; + er_tr_cpu_addresses.prod_er_no_buffs += 1; + IPADBG("prod pipe event ring setup done\n"); + return 0; +} + +static int ipa3_uc_setup_con_pipe_transfer_ring( + struct rtp_pipe_setup_cmd_data *rtp_cmd_data, int index) +{ + struct ipa_mem_buffer ring; + + if (!rtp_cmd_data) { + IPAERR("Invalid params.\n"); + return -EINVAL; + } + + ring.size = sizeof(struct con_pipe_tre) * IPA_UC_CON_TRANSFER_RING_SIZE; + ring.base = dma_alloc_coherent(ipa3_ctx->uc_pdev, ring.size, + &ring.phys_base, GFP_KERNEL); + if (ring.base == NULL) { + IPAERR("dma alloc coherent failed.\n"); + return -ENOMEM; + } + + rtp_cmd_data->uc_cons_tr[index].temp_buff_pa = ring.phys_base; + rtp_cmd_data->uc_cons_tr[index].temp_buff_size = ring.size; + er_tr_cpu_addresses.cpu_address_cons_tr[index] = ring.base; + er_tr_cpu_addresses.cons_tr_no_buffs += 1; + IPADBG("con pipe transfer ring setup done\n"); + return 0; +} + +void ipa3_free_uc_pipes_er_tr(void) +{ + uint8_t index = 0; + + for (index = 0; index < er_tr_cpu_addresses.prod_tr_no_buffs; index++) { + dma_free_coherent(ipa3_ctx->uc_pdev, + er_tr_cpu_addresses.rtp_tr_er.uc_prod_tr[index].temp_buff_size, + er_tr_cpu_addresses.cpu_address_prod_tr[index], + er_tr_cpu_addresses.rtp_tr_er.uc_prod_tr[index].temp_buff_pa); + } + + for (index = 0; index < er_tr_cpu_addresses.prod_er_no_buffs; index++) { + dma_free_coherent(ipa3_ctx->uc_pdev, + er_tr_cpu_addresses.rtp_tr_er.uc_prod_er[index].temp_buff_size, + er_tr_cpu_addresses.cpu_address_prod_er[index], + er_tr_cpu_addresses.rtp_tr_er.uc_prod_er[index].temp_buff_pa); + } + + for (index = 0; index < er_tr_cpu_addresses.cons_tr_no_buffs; index++) { + dma_free_coherent(ipa3_ctx->uc_pdev, + er_tr_cpu_addresses.rtp_tr_er.uc_cons_tr[index].temp_buff_size, + er_tr_cpu_addresses.cpu_address_cons_tr[index], + er_tr_cpu_addresses.rtp_tr_er.uc_cons_tr[index].temp_buff_pa); + } + + IPADBG("freed uc pipes er and tr memory\n"); +} + +int ipa3_allocate_uc_pipes_er_tr_send_to_uc(void) +{ + int res = 0; + struct rtp_pipe_setup_cmd_data rtp_cmd_data; + int indx = 0; + + for (indx = 0; indx < MAX_UC_PROD_PIPES; indx++) { + res = ipa3_uc_setup_prod_pipe_transfer_ring(&rtp_cmd_data, indx); + if (res) { + IPAERR("In RTP Pipe setup prod tr func failed\n"); + memcpy(&er_tr_cpu_addresses.rtp_tr_er, &rtp_cmd_data, + sizeof(rtp_cmd_data)); + ipa3_free_uc_pipes_er_tr(); + return res; + } + res = ipa3_uc_setup_prod_pipe_event_ring(&rtp_cmd_data, indx); + if (res) { + IPAERR("In RTP Pipe setup pprod er func failed\n"); + memcpy(&er_tr_cpu_addresses.rtp_tr_er, &rtp_cmd_data, + sizeof(rtp_cmd_data)); + ipa3_free_uc_pipes_er_tr(); + return res; + } + + if (indx < MAX_UC_CONS_PIPES) { + res = ipa3_uc_setup_con_pipe_transfer_ring(&rtp_cmd_data, indx); + if (res) { + memcpy(&er_tr_cpu_addresses.rtp_tr_er, &rtp_cmd_data, + sizeof(rtp_cmd_data)); + ipa3_free_uc_pipes_er_tr(); + IPAERR("In RTP Pipe setup con tr func failed\n"); + return res; + } + } + } + + memcpy(&er_tr_cpu_addresses.rtp_tr_er, &rtp_cmd_data, sizeof(rtp_cmd_data)); + res = ipa3_uc_send_RTPPipeSetup_cmd(&rtp_cmd_data); + IPADBG("allocated uc pipes er, tr memory and send to uc\n"); + return res; +} + +int ipa3_insert_dma_info(struct dma_address_map_table *map, uint32_t stream_id) +{ + struct list_node *new_node = kzalloc(sizeof(struct list_node), GFP_KERNEL); + + if (!new_node) { + IPAERR("failed to alloc memory.\n"); + return -ENOMEM; + } + + if (!map) { + IPAERR("Invalid params.\n"); + kfree(new_node); + return -EINVAL; + } + + new_node->data = map; + list_add(&new_node->list_obj, &mapped_bs_buff_lst[stream_id]); + IPADBG("inserted dma buff info into list\n"); + return 0; +} + +struct dma_address_map_table *ipa3_search_dma_info(struct dma_buf *dma_buf, uint32_t stream_id) +{ + struct list_head *ptr = NULL; + struct list_node *entry = NULL; + + if (IS_ERR_OR_NULL(dma_buf)) { + IPAERR("Invalid params.\n"); + return NULL; + } + list_for_each(ptr, &mapped_bs_buff_lst[stream_id]) { + entry = list_entry(ptr, struct list_node, list_obj); + if (!entry || !entry->data) + continue; + + if (dma_buf == entry->data->dma_buf_list[0]) + return entry->data; + } + + IPADBG("Not found dma buff info in list\n"); + return NULL; +} + +struct dma_address_map_table *ipa3_delete_dma_info(struct dma_buf *dma_buf, int stream_id) +{ + struct list_head *ptr = NULL; + struct list_node *entry = NULL; + struct dma_address_map_table *table_entry = NULL; + int found = 0; + + if (IS_ERR_OR_NULL(dma_buf)) { + IPAERR("Invalid params.\n"); + return NULL; + } + list_for_each(ptr, &mapped_bs_buff_lst[stream_id]) { + entry = list_entry(ptr, struct list_node, list_obj); + if (!entry || !entry->data) + continue; + if (dma_buf == entry->data->dma_buf_list[0]) { + found = 1; + break; + } + } + + if (found && entry) { + table_entry = entry->data; + list_del(ptr); + kfree(entry); + } + + IPADBG("deleted dma buff info from list\n"); + return table_entry; +} + +int ipa3_smmu_map_buff(uint64_t bitstream_buffer_fd, + uint64_t meta_buff_fd, int stream_id) +{ + int err = 0; + struct dma_buf *dbuff = NULL; + struct dma_buf_attachment *attachment = NULL; + struct dma_address_map_table *map_table = NULL; + + map_table = kzalloc(sizeof(struct dma_address_map_table), GFP_KERNEL); + if (!map_table) { + IPAERR("failed to alloc memory.\n"); + return -ENOMEM; + } + + dbuff = dma_buf_get(bitstream_buffer_fd); + if (IS_ERR_OR_NULL(dbuff)) { + IPAERR("no dma handle for the fd.\n"); + err = -EFAULT; + goto map_table_free; + } + + attachment = dma_buf_attach(dbuff, ipa3_ctx->rtp_pdev); + if (IS_ERR_OR_NULL(attachment)) { + IPAERR("dma buf attachment failed\n"); + err = -EFAULT; + goto dma_buff_put; + } + + map_table->dma_buf_list[0] = dbuff; + map_table->attachment[0] = attachment; + map_table->sgt[0] = NULL; + + if (bitstream_buffer_fd == meta_buff_fd) { + map_table->dma_buf_list[1] = NULL; + map_table->attachment[1] = NULL; + map_table->sgt[1] = NULL; + err = ipa3_insert_dma_info(map_table, stream_id); + if (err) { + IPAERR("dma info insertion failed.\n"); + goto dma_buff_det; + } + return err; + } + + dbuff = dma_buf_get(meta_buff_fd); + if (IS_ERR_OR_NULL(dbuff)) { + IPAERR("no dma handle for the fd.\n"); + err = -EFAULT; + goto dma_buff_det; + } + + attachment = dma_buf_attach(dbuff, ipa3_ctx->rtp_pdev); + if (IS_ERR_OR_NULL(attachment)) { + IPAERR("dma buf attachment failed.\n"); + err = -EFAULT; + goto dma_buff_det; + } + + map_table->dma_buf_list[1] = dbuff; + map_table->attachment[1] = attachment; + map_table->sgt[1] = NULL; + err = ipa3_insert_dma_info(map_table, stream_id); + if (err) { + IPAERR("dma info insertion failed.\n"); + goto dma_buff_det; + } + + IPADBG("smmu map buff addr done\n"); + return err; + +dma_buff_det: + if (map_table->dma_buf_list[0]) + dma_buf_detach(map_table->dma_buf_list[0], map_table->attachment[0]); + if (map_table->dma_buf_list[1]) + dma_buf_detach(map_table->dma_buf_list[1], map_table->attachment[1]); + +dma_buff_put: + if (map_table->dma_buf_list[0]) + dma_buf_put(map_table->dma_buf_list[0]); + if (map_table->dma_buf_list[1]) + dma_buf_put(map_table->dma_buf_list[1]); + +map_table_free: + kfree(map_table); + + return err; +} + +int ipa3_smmu_unmap_buff(uint64_t bitstream_buffer_fd, uint64_t meta_buff_fd, int stream_id) +{ + struct dma_buf *dbuff = NULL; + struct dma_address_map_table *map_table = NULL; + + dbuff = dma_buf_get(bitstream_buffer_fd); + if (IS_ERR_OR_NULL(dbuff)) { + IPAERR("no dma handle for the fd.\n"); + return -EFAULT; + } + + map_table = ipa3_delete_dma_info(dbuff, stream_id); + if (!map_table) { + dma_buf_put(dbuff); + IPAERR("Buffer is not mapped\n"); + return -EFAULT; + } + + if (map_table->sgt[0] != NULL) { + dma_buf_unmap_attachment(map_table->attachment[0], + map_table->sgt[0], DMA_DIR); + } + + dma_buf_detach(map_table->dma_buf_list[0], map_table->attachment[0]); + dma_buf_put(map_table->dma_buf_list[0]); + if (bitstream_buffer_fd != meta_buff_fd) { + if (map_table->sgt[1] != NULL) { + dma_buf_unmap_attachment(map_table->attachment[1], + map_table->sgt[1], DMA_DIR); + } + dma_buf_detach(map_table->dma_buf_list[1], map_table->attachment[1]); + dma_buf_put(map_table->dma_buf_list[1]); + } + + IPADBG("smmu unmap done\n"); + kfree(map_table); + return 0; +} + +int ipa3_map_buff_to_device_addr(struct map_buffer *map_buffs) +{ + int index = 0; + int err = 0; + + if (!map_buffs) { + IPAERR("Invalid params.\n"); + return -EINVAL; + } + + INIT_LIST_HEAD(&mapped_bs_buff_lst[map_buffs->stream_id]); + for (index = 0; index < map_buffs->nfd; index++) { + err = ipa3_smmu_map_buff(map_buffs->buff_info[index].bitstream_buffer_fd, + map_buffs->buff_info[index].meta_buff_fd, map_buffs->stream_id); + if (err) { + IPAERR("smmu map failed\n"); + return err; + } + } + + IPADBG("maped buff addr to device addr\n"); + return err; +} + +int ipa3_unmap_buff_from_device_addr(struct unmap_buffer *unmap_buffs) +{ + unsigned char index = 0; + int err = 0; + + if (!unmap_buffs) { + IPAERR("Invalid params.\n"); + return -EINVAL; + } + + for (index = 0; index < unmap_buffs->nfd; index++) { + err = ipa3_smmu_unmap_buff(unmap_buffs->buff_info[index].bitstream_buffer_fd, + unmap_buffs->buff_info[index].meta_buff_fd, unmap_buffs->stream_id); + if (err) { + IPAERR("smmu unmap failed\n"); + return err; + } + } + + IPADBG("unmaped buff addr from device addr\n"); + return err; +} + +int ipa3_send_bitstream_buff_info(struct bitstream_buffers *data) +{ + struct bitstream_buffers_to_uc tmp; + int index = 0; + int synx_result = 0; + struct dma_buf *dmab = NULL; + struct dma_address_map_table *map_table = NULL; + struct sg_table *sgt = NULL; + struct synx_import_params params = {0}; + struct dma_fence *fence = NULL; + u32 handle; + + if (!data || data->buff_cnt < 1) { + IPAERR("Invalid params.\n"); + return -EINVAL; + } + + memset(&tmp, 0, sizeof(struct bitstream_buffers_to_uc)); + tmp.buff_cnt = data->buff_cnt; + tmp.cookie = data->cookie; + + for (index = 0; index < data->buff_cnt; index++) { + /* + * We need to get the underlying fence handle/hash on every + * fence fd received from IPA C2 and pass the handle to uC. + */ + params.type = SYNX_IMPORT_INDV_PARAMS; + params.indv.flags = SYNX_IMPORT_DMA_FENCE | SYNX_IMPORT_GLOBAL_FENCE; + fence = sync_file_get_fence(data->bs_info[index].fence_id); + if (!fence) { + IPAERR("sync_file_get_fence failure on %u fd\n", + data->bs_info[index].fence_id); + return -EFAULT; + } + params.indv.fence = fence; + params.indv.new_h_synx = &handle; + + synx_result = synx_import(glob_synx_session_ptr, ¶ms); + if (synx_result) { + IPAERR("synx_import is failed with %d\n", synx_result); + dma_fence_put(fence); + return -EFAULT; + } + + tmp.bs_info[index].fence_id = handle; + + /* + * Irrespective of whether bitstream_buffer cmd is sent to uC, + * we can call synx_release, dma_fence_put to put one refcnt + * taken by synx_import & sync_file_get_fence() respectively. + */ + + if (synx_release(glob_synx_session_ptr, handle)) + IPAERR("synx_release failed on this %u handle\n", handle); + dma_fence_put(fence); + + tmp.bs_info[index].stream_id = data->bs_info[index].stream_id; + tmp.bs_info[index].buff_fd = data->bs_info[index].buff_fd; + tmp.bs_info[index].buff_size = data->bs_info[index].buff_size; + tmp.bs_info[index].meta_buff_fd = data->bs_info[index].meta_buff_fd; + tmp.bs_info[index].meta_buff_size = data->bs_info[index].meta_buff_size; + + dmab = dma_buf_get(tmp.bs_info[index].buff_fd); + if (IS_ERR_OR_NULL(dmab)) { + IPAERR("no dma handle for the fd.\n"); + return -EFAULT; + } + + map_table = ipa3_search_dma_info(dmab, tmp.bs_info[index].stream_id); + if (!map_table) { + IPAERR("no map table from search dma info.\n"); + dma_buf_put(dmab); + return -EFAULT; + } + + if (!map_table->sgt[0]) { + sgt = dma_buf_map_attachment(map_table->attachment[0], DMA_DIR); + if (IS_ERR_OR_NULL(sgt)) { + dma_buf_put(dmab); + IPAERR("dma buf map attachment failed\n"); + return -EFAULT; + } + map_table->sgt[0] = sgt; + } + + if (data->bs_info[index].meta_buff_fd != data->bs_info[index].buff_fd) { + if (!map_table->sgt[1]) { + sgt = dma_buf_map_attachment(map_table->attachment[1], DMA_DIR); + if (IS_ERR_OR_NULL(sgt)) { + dma_buf_detach(map_table->dma_buf_list[0], + map_table->attachment[0]); + dma_buf_put(dmab); + IPAERR("dma buf map attachment failed\n"); + return -EFAULT; + } + map_table->sgt[1] = sgt; + } + + tmp.bs_info[index].buff_addr = map_table->sgt[0]->sgl->dma_address; + tmp.bs_info[index].meta_buff_addr = map_table->sgt[1]->sgl->dma_address; + } else { + tmp.bs_info[index].buff_addr = map_table->sgt[0]->sgl->dma_address + + data->bs_info[index].buff_offset; + tmp.bs_info[index].meta_buff_addr = map_table->sgt[1]->sgl->dma_address; + } + } + + return ipa3_uc_send_add_bitstream_buffers_cmd(&tmp); +} + +int ipa3_uc_send_hfi_cmd(struct hfi_queue_info *data) +{ + int result = 0; + struct ipa_mem_buffer cmd; + struct hfi_queue_info *cmd_data; + + if (!data) { + IPAERR("Invalid params.\n"); + return -EINVAL; + } + + cmd.size = sizeof(*cmd_data); + cmd.base = dma_alloc_coherent(ipa3_ctx->uc_pdev, cmd.size, + &cmd.phys_base, GFP_KERNEL); + if (cmd.base == NULL) { + IPAERR("failed to alloc DMA memory.\n"); + return -ENOMEM; + } + + cmd_data = (struct hfi_queue_info *)cmd.base; + memcpy(cmd_data, data, sizeof(struct hfi_queue_info)); + IPADBG("Sending uc CMD RTP_GET_HFI_STRUCT\n"); + result = ipa3_uc_send_cmd((u32)(cmd.phys_base), + IPA_CPU_2_HW_CMD_RTP_GET_HFI_STRUCT, + 0, + false, 10*HZ); + if (result) { + IPAERR("uc send hfi queue info cmd failed\n"); + result = -EPERM; + } + + dma_free_coherent(ipa3_ctx->uc_pdev, cmd.size, cmd.base, cmd.phys_base); + return result; +} + +int ipa3_create_hfi_send_uc(void) +{ + int res = 0; + struct synx_initialization_params params; + struct synx_queue_desc queue_desc; + char synx_session_name[MAX_SYNX_FENCE_SESSION_NAME]; + struct hfi_queue_info data; + dma_addr_t hfi_queue_addr = 0; + struct ipa_smmu_cb_ctx *cb = NULL; + struct synx_hw_fence_hfi_queue_header *hfi_queue_payload_vptr = NULL; + + snprintf(synx_session_name, MAX_SYNX_FENCE_SESSION_NAME, "ipa synx fence"); + queue_desc.vaddr = NULL; + queue_desc.mem_data = NULL; + queue_desc.size = 0; + queue_desc.dev_addr = 0; + + params.name = (const char *)synx_session_name; + params.ptr = &queue_desc; + params.id = SYNX_CLIENT_HW_FENCE_IPA_CTX0; + params.flags = SYNX_INIT_MAX; + + glob_synx_session_ptr = synx_initialize(¶ms); + if (IS_ERR_OR_NULL(glob_synx_session_ptr)) { + IPAERR("invalid synx fence session\n"); + return -EFAULT; + } + + cb = ipa3_get_smmu_ctx(IPA_SMMU_CB_UC); + res = ipa3_iommu_map(cb->iommu_domain, + queue_desc.dev_addr, queue_desc.dev_addr, + queue_desc.size, IOMMU_READ | IOMMU_WRITE); + if (res) { + IPAERR("HFI - smmu map failed\n"); + synx_uninitialize(glob_synx_session_ptr); + return -EFAULT; + } + + IPADBG("hfi queue addr is 0x%x and size is 0x%x\n", + queue_desc.dev_addr, queue_desc.size); + + hfi_queue_addr = queue_desc.dev_addr; + data.hfi_queue_addr = hfi_queue_addr; + data.queue_header_start_addr = hfi_queue_addr + + sizeof(struct synx_hw_fence_hfi_queue_table_header); + data.queue_payload_start_addr = data.queue_header_start_addr + + sizeof(struct synx_hw_fence_hfi_queue_header); + hfi_queue_payload_vptr = (struct synx_hw_fence_hfi_queue_header *)(queue_desc.vaddr + + sizeof(struct synx_hw_fence_hfi_queue_table_header)); + data.hfi_queue_payload_size = hfi_queue_payload_vptr->queue_size; + IPADBG("hfi queue payload vptr is 0x%x\n", hfi_queue_payload_vptr); + IPADBG("hfi queue payload size is 0x%x\n", data.hfi_queue_payload_size); + res = ipa3_uc_send_hfi_cmd(&data); + return res; +} diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_uc_wdi.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_uc_wdi.c new file mode 100644 index 0000000000..3c768935d5 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_uc_wdi.c @@ -0,0 +1,3503 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ipa_i.h" +#include +#include +#include +#include "ipa_qmi_service.h" + +#define IPA_HW_INTERFACE_WDI_VERSION 0x0001 +#define IPA_HW_WDI_RX_MBOX_START_INDEX 48 +#define IPA_HW_WDI_TX_MBOX_START_INDEX 50 +#define IPA_WDI_RING_ALIGNMENT 8 + +#define IPA_GSI_EVT_RING_INT_MODT (32 * 1) /* 1ms under 32KHz clock */ + +#define IPA_AGGR_PKT_LIMIT 1 +#define IPA_AGGR_HARD_BYTE_LIMIT 2 /*2 Kbytes Agger hard byte limit*/ +#define UPDATE_RI_MODERATION_THRESHOLD 8 + + +#define IPA_WDI_CONNECTED BIT(0) +#define IPA_WDI_ENABLED BIT(1) +#define IPA_WDI_RESUMED BIT(2) +#define IPA_UC_POLL_SLEEP_USEC 100 + +#define GSI_STOP_MAX_RETRY_CNT 10 + +enum ipa_pm_state_wdi_info { + IPA_PM_WDI_PM_REGISTERED = 0x0, + IPA_PM_WDI_PM_ACTIVATE = 0x1, + IPA_PM_WDI_PM_DEACTIVATE_IN_PROC = 0x2, + IPA_PM_WDI_PM_DEACTIVATE = 0x3, + IPA_PM_WDI_PM_DEREGISTER_IN_PROC = 0x4, + IPA_PM_WDI_PM_DEREGISTERED = 0x5 +}; + +struct ipa_pm_wdi_context { + enum ipa_pm_state_wdi_info curr_pm_state; + u32 ipa_wrapper_pm_hdl; +}; + +static struct ipa_pm_wdi_context ipa_pm_wdi_ctx = { + .curr_pm_state = IPA_PM_WDI_PM_DEREGISTERED, + .ipa_wrapper_pm_hdl = 0 +}; + + +struct ipa_wdi_res { + struct ipa_wdi_buffer_info *res; + unsigned int nents; + bool valid; +}; + +static struct ipa_wdi_res wdi_res[IPA_WDI_MAX_RES]; + +static void ipa3_uc_wdi_loaded_handler(void); + +/** + * enum ipa_hw_2_cpu_wdi_events - Values that represent HW event to be sent to + * CPU. + * @IPA_HW_2_CPU_EVENT_WDI_ERROR : Event to specify that HW detected an error + * in WDI + */ +enum ipa_hw_2_cpu_wdi_events { + IPA_HW_2_CPU_EVENT_WDI_ERROR = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_WDI, 0), +}; + +/** + * enum ipa_hw_wdi_channel_states - Values that represent WDI channel state + * machine. + * @IPA_HW_WDI_CHANNEL_STATE_INITED_DISABLED : Channel is initialized but + * disabled + * @IPA_HW_WDI_CHANNEL_STATE_ENABLED_SUSPEND : Channel is enabled but in + * suspended state + * @IPA_HW_WDI_CHANNEL_STATE_RUNNING : Channel is running. Entered after + * SET_UP_COMMAND is processed successfully + * @IPA_HW_WDI_CHANNEL_STATE_ERROR : Channel is in error state + * @IPA_HW_WDI_CHANNEL_STATE_INVALID : Invalid state. Shall not be in use in + * operational scenario + * + * These states apply to both Tx and Rx paths. These do not reflect the + * sub-state the state machine may be in. + */ +enum ipa_hw_wdi_channel_states { + IPA_HW_WDI_CHANNEL_STATE_INITED_DISABLED = 1, + IPA_HW_WDI_CHANNEL_STATE_ENABLED_SUSPEND = 2, + IPA_HW_WDI_CHANNEL_STATE_RUNNING = 3, + IPA_HW_WDI_CHANNEL_STATE_ERROR = 4, + IPA_HW_WDI_CHANNEL_STATE_INVALID = 0xFF +}; + +/** + * enum ipa3_cpu_2_hw_commands - Values that represent the WDI commands from + * CPU + * @IPA_CPU_2_HW_CMD_WDI_TX_SET_UP : Command to set up WDI Tx Path + * @IPA_CPU_2_HW_CMD_WDI_RX_SET_UP : Command to set up WDI Rx Path + * @IPA_CPU_2_HW_CMD_WDI_RX_EXT_CFG : Provide extended config info for Rx path + * @IPA_CPU_2_HW_CMD_WDI_CH_ENABLE : Command to enable a channel + * @IPA_CPU_2_HW_CMD_WDI_CH_DISABLE : Command to disable a channel + * @IPA_CPU_2_HW_CMD_WDI_CH_SUSPEND : Command to suspend a channel + * @IPA_CPU_2_HW_CMD_WDI_CH_RESUME : Command to resume a channel + * @IPA_CPU_2_HW_CMD_WDI_TEAR_DOWN : Command to tear down WDI Tx/ Rx Path + */ +enum ipa_cpu_2_hw_wdi_commands { + IPA_CPU_2_HW_CMD_WDI_TX_SET_UP = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_WDI, 0), + IPA_CPU_2_HW_CMD_WDI_RX_SET_UP = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_WDI, 1), + IPA_CPU_2_HW_CMD_WDI_RX_EXT_CFG = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_WDI, 2), + IPA_CPU_2_HW_CMD_WDI_CH_ENABLE = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_WDI, 3), + IPA_CPU_2_HW_CMD_WDI_CH_DISABLE = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_WDI, 4), + IPA_CPU_2_HW_CMD_WDI_CH_SUSPEND = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_WDI, 5), + IPA_CPU_2_HW_CMD_WDI_CH_RESUME = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_WDI, 6), + IPA_CPU_2_HW_CMD_WDI_TEAR_DOWN = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_WDI, 7), +}; + +/** + * enum ipa_hw_2_cpu_cmd_resp_status - Values that represent WDI related + * command response status to be sent to CPU. + */ +enum ipa_hw_2_cpu_cmd_resp_status { + IPA_HW_2_CPU_WDI_CMD_STATUS_SUCCESS = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_WDI, 0), + IPA_HW_2_CPU_MAX_WDI_TX_CHANNELS = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_WDI, 1), + IPA_HW_2_CPU_WDI_CE_RING_OVERRUN_POSSIBILITY = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_WDI, 2), + IPA_HW_2_CPU_WDI_CE_RING_SET_UP_FAILURE = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_WDI, 3), + IPA_HW_2_CPU_WDI_CE_RING_PARAMS_UNALIGNED = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_WDI, 4), + IPA_HW_2_CPU_WDI_COMP_RING_OVERRUN_POSSIBILITY = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_WDI, 5), + IPA_HW_2_CPU_WDI_COMP_RING_SET_UP_FAILURE = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_WDI, 6), + IPA_HW_2_CPU_WDI_COMP_RING_PARAMS_UNALIGNED = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_WDI, 7), + IPA_HW_2_CPU_WDI_UNKNOWN_TX_CHANNEL = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_WDI, 8), + IPA_HW_2_CPU_WDI_TX_INVALID_FSM_TRANSITION = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_WDI, 9), + IPA_HW_2_CPU_WDI_TX_FSM_TRANSITION_ERROR = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_WDI, 10), + IPA_HW_2_CPU_MAX_WDI_RX_CHANNELS = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_WDI, 11), + IPA_HW_2_CPU_WDI_RX_RING_PARAMS_UNALIGNED = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_WDI, 12), + IPA_HW_2_CPU_WDI_RX_RING_SET_UP_FAILURE = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_WDI, 13), + IPA_HW_2_CPU_WDI_UNKNOWN_RX_CHANNEL = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_WDI, 14), + IPA_HW_2_CPU_WDI_RX_INVALID_FSM_TRANSITION = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_WDI, 15), + IPA_HW_2_CPU_WDI_RX_FSM_TRANSITION_ERROR = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_WDI, 16), +}; + +/** + * enum ipa_hw_wdi_errors - WDI specific error types. + * @IPA_HW_WDI_ERROR_NONE : No error persists + * @IPA_HW_WDI_CHANNEL_ERROR : Error is specific to channel + */ +enum ipa_hw_wdi_errors { + IPA_HW_WDI_ERROR_NONE = 0, + IPA_HW_WDI_CHANNEL_ERROR = 1 +}; + +/** + * enum ipa_hw_wdi_ch_errors = List of WDI Channel error types. This is present + * in the event param. + * @IPA_HW_WDI_CH_ERR_NONE : No error persists + * @IPA_HW_WDI_TX_COMP_RING_WP_UPDATE_FAIL : Write pointer update failed in Tx + * Completion ring + * @IPA_HW_WDI_TX_FSM_ERROR : Error in the state machine transition + * @IPA_HW_WDI_TX_COMP_RE_FETCH_FAIL : Error while calculating num RE to bring + * @IPA_HW_WDI_CH_ERR_RESERVED : Reserved - Not available for CPU to use + */ +enum ipa_hw_wdi_ch_errors { + IPA_HW_WDI_CH_ERR_NONE = 0, + IPA_HW_WDI_TX_COMP_RING_WP_UPDATE_FAIL = 1, + IPA_HW_WDI_TX_FSM_ERROR = 2, + IPA_HW_WDI_TX_COMP_RE_FETCH_FAIL = 3, + IPA_HW_WDI_CH_ERR_RESERVED = 0xFF +}; + +/** + * struct IpaHwSharedMemWdiMapping_t - Structure referring to the common and + * WDI section of 128B shared memory located in offset zero of SW Partition in + * IPA SRAM. + * + * The shared memory is used for communication between IPA HW and CPU. + */ +struct IpaHwSharedMemWdiMapping_t { + struct IpaHwSharedMemCommonMapping_t common; + u32 reserved_2B_28; + u32 reserved_2F_2C; + u32 reserved_33_30; + u32 reserved_37_34; + u32 reserved_3B_38; + u32 reserved_3F_3C; + u16 interfaceVersionWdi; + u16 reserved_43_42; + u8 wdi_tx_ch_0_state; + u8 wdi_rx_ch_0_state; + u16 reserved_47_46; +} __packed; + +/** + * struct IpaHwWdiTxSetUpCmdData_t - Structure holding the parameters for + * IPA_CPU_2_HW_CMD_WDI_TX_SET_UP command. + * @comp_ring_base_pa : This is the physical address of the base of the Tx + * completion ring + * @comp_ring_size : This is the size of the Tx completion ring + * @reserved_comp_ring : Reserved field for expansion of Completion ring params + * @ce_ring_base_pa : This is the physical address of the base of the Copy + * Engine Source Ring + * @ce_ring_size : Copy Engine Ring size + * @reserved_ce_ring : Reserved field for expansion of CE ring params + * @ce_ring_doorbell_pa : This is the physical address of the doorbell that the + * IPA uC has to write into to trigger the copy engine + * @num_tx_buffers : Number of pkt buffers allocated. The size of the CE ring + * and the Tx completion ring has to be atleast ( num_tx_buffers + 1) + * @ipa_pipe_number : This is the IPA pipe number that has to be used for the + * Tx path + * @reserved : Reserved field + * + * Parameters are sent as pointer thus should be reside in address accessible + * to HW + */ +struct IpaHwWdiTxSetUpCmdData_t { + u32 comp_ring_base_pa; + u16 comp_ring_size; + u16 reserved_comp_ring; + u32 ce_ring_base_pa; + u16 ce_ring_size; + u16 reserved_ce_ring; + u32 ce_ring_doorbell_pa; + u16 num_tx_buffers; + u8 ipa_pipe_number; + u8 reserved; +} __packed; + +struct IpaHwWdi2TxSetUpCmdData_t { + u32 comp_ring_base_pa; + u32 comp_ring_base_pa_hi; + u16 comp_ring_size; + u16 reserved_comp_ring; + u32 ce_ring_base_pa; + u32 ce_ring_base_pa_hi; + u16 ce_ring_size; + u16 reserved_ce_ring; + u32 ce_ring_doorbell_pa; + u32 ce_ring_doorbell_pa_hi; + u16 num_tx_buffers; + u8 ipa_pipe_number; + u8 reserved; +} __packed; +/** + * struct IpaHwWdiRxSetUpCmdData_t - Structure holding the parameters for + * IPA_CPU_2_HW_CMD_WDI_RX_SET_UP command. + * @rx_ring_base_pa : This is the physical address of the base of the Rx ring + * (containing Rx buffers) + * @rx_ring_size : This is the size of the Rx ring + * @rx_ring_rp_pa : This is the physical address of the location through which + * IPA uc is expected to communicate about the Read pointer into the Rx Ring + * @ipa_pipe_number : This is the IPA pipe number that has to be used for the + * Rx path + * + * Parameters are sent as pointer thus should be reside in address accessible + * to HW + */ +struct IpaHwWdiRxSetUpCmdData_t { + u32 rx_ring_base_pa; + u32 rx_ring_size; + u32 rx_ring_rp_pa; + u8 ipa_pipe_number; +} __packed; + +struct IpaHwWdi2RxSetUpCmdData_t { + u32 rx_ring_base_pa; + u32 rx_ring_base_pa_hi; + u32 rx_ring_size; + u32 rx_ring_rp_pa; + u32 rx_ring_rp_pa_hi; + u32 rx_comp_ring_base_pa; + u32 rx_comp_ring_base_pa_hi; + u32 rx_comp_ring_size; + u32 rx_comp_ring_wp_pa; + u32 rx_comp_ring_wp_pa_hi; + u8 ipa_pipe_number; +} __packed; +/** + * union IpaHwWdiRxExtCfgCmdData_t - Structure holding the parameters for + * IPA_CPU_2_HW_CMD_WDI_RX_EXT_CFG command. + * @ipa_pipe_number : The IPA pipe number for which this config is passed + * @qmap_id : QMAP ID to be set in the metadata register + * @reserved : Reserved + * + * The parameters are passed as immediate params in the shared memory + */ +union IpaHwWdiRxExtCfgCmdData_t { + struct IpaHwWdiRxExtCfgCmdParams_t { + u32 ipa_pipe_number:8; + u32 qmap_id:8; + u32 reserved:16; + } __packed params; + u32 raw32b; +} __packed; + +/** + * union IpaHwWdiCommonChCmdData_t - Structure holding the parameters for + * IPA_CPU_2_HW_CMD_WDI_TEAR_DOWN, + * IPA_CPU_2_HW_CMD_WDI_CH_ENABLE, + * IPA_CPU_2_HW_CMD_WDI_CH_DISABLE, + * IPA_CPU_2_HW_CMD_WDI_CH_SUSPEND, + * IPA_CPU_2_HW_CMD_WDI_CH_RESUME command. + * @ipa_pipe_number : The IPA pipe number. This could be Tx or an Rx pipe + * @reserved : Reserved + * + * The parameters are passed as immediate params in the shared memory + */ +union IpaHwWdiCommonChCmdData_t { + struct IpaHwWdiCommonChCmdParams_t { + u32 ipa_pipe_number:8; + u32 reserved:24; + } __packed params; + u32 raw32b; +} __packed; + +/** + * union IpaHwWdiErrorEventData_t - parameters for IPA_HW_2_CPU_EVENT_WDI_ERROR + * event. + * @wdi_error_type : The IPA pipe number to be torn down. This could be Tx or + * an Rx pipe + * @reserved : Reserved + * @ipa_pipe_number : IPA pipe number on which error has happened. Applicable + * only if error type indicates channel error + * @wdi_ch_err_type : Information about the channel error (if available) + * + * The parameters are passed as immediate params in the shared memory + */ +union IpaHwWdiErrorEventData_t { + struct IpaHwWdiErrorEventParams_t { + u32 wdi_error_type:8; + u32 reserved:8; + u32 ipa_pipe_number:8; + u32 wdi_ch_err_type:8; + } __packed params; + u32 raw32b; +} __packed; + +static void ipa3_uc_wdi_event_log_info_handler( +struct IpaHwEventLogInfoData_t *uc_event_top_mmio) + +{ + struct Ipa3HwEventInfoData_t *stats_ptr = &uc_event_top_mmio->statsInfo; + + if ((uc_event_top_mmio->protocolMask & + (1 << IPA_HW_PROTOCOL_WDI)) == 0) { + IPAERR("WDI protocol missing 0x%x\n", + uc_event_top_mmio->protocolMask); + return; + } + + if (stats_ptr->featureInfo[IPA_HW_PROTOCOL_WDI].params.size != + sizeof(struct IpaHwStatsWDIInfoData_t)) { + IPAERR("wdi stats sz invalid exp=%zu is=%u\n", + sizeof(struct IpaHwStatsWDIInfoData_t), + stats_ptr->featureInfo[ + IPA_HW_PROTOCOL_WDI].params.size); + return; + } + + ipa3_ctx->uc_wdi_ctx.wdi_uc_stats_ofst = + stats_ptr->baseAddrOffset + + stats_ptr->featureInfo[IPA_HW_PROTOCOL_WDI].params.offset; + IPAERR("WDI stats ofst=0x%x\n", ipa3_ctx->uc_wdi_ctx.wdi_uc_stats_ofst); + if (ipa3_ctx->uc_wdi_ctx.wdi_uc_stats_ofst + + sizeof(struct IpaHwStatsWDIInfoData_t) >= + ipa3_ctx->ctrl->ipa_reg_base_ofst + + ipahal_get_reg_n_ofst(IPA_SW_AREA_RAM_DIRECT_ACCESS_n, 0) + + ipa3_ctx->smem_sz) { + IPAERR("uc_wdi_stats 0x%x outside SRAM\n", + ipa3_ctx->uc_wdi_ctx.wdi_uc_stats_ofst); + return; + } + + ipa3_ctx->uc_wdi_ctx.wdi_uc_stats_mmio = + ioremap(ipa3_ctx->ipa_wrapper_base + + ipa3_ctx->uc_wdi_ctx.wdi_uc_stats_ofst, + sizeof(struct IpaHwStatsWDIInfoData_t)); + if (!ipa3_ctx->uc_wdi_ctx.wdi_uc_stats_mmio) { + IPAERR("fail to ioremap uc wdi stats\n"); + return; + } +} + +static void ipa3_uc_wdi_event_handler(struct IpaHwSharedMemCommonMapping_t + *uc_sram_mmio) + +{ + union IpaHwWdiErrorEventData_t wdi_evt; + struct IpaHwSharedMemWdiMapping_t *wdi_sram_mmio_ext; + + if (uc_sram_mmio->eventOp == + IPA_HW_2_CPU_EVENT_WDI_ERROR) { + wdi_evt.raw32b = uc_sram_mmio->eventParams; + IPADBG("uC WDI evt errType=%u pipe=%d cherrType=%u\n", + wdi_evt.params.wdi_error_type, + wdi_evt.params.ipa_pipe_number, + wdi_evt.params.wdi_ch_err_type); + wdi_sram_mmio_ext = + (struct IpaHwSharedMemWdiMapping_t *) + uc_sram_mmio; + IPADBG("tx_ch_state=%u rx_ch_state=%u\n", + wdi_sram_mmio_ext->wdi_tx_ch_0_state, + wdi_sram_mmio_ext->wdi_rx_ch_0_state); + } +} + +/** + * ipa3_get_wdi_gsi_stats() - Query WDI gsi stats from uc + * @stats: [inout] stats blob from client populated by driver + * + * Returns: 0 on success, negative on failure + * + * @note Cannot be called from atomic context + * + */ +int ipa3_get_wdi_gsi_stats(struct ipa_uc_dbg_ring_stats *stats) +{ + int i; + + if (!ipa3_ctx->wdi2_ctx.dbg_stats.uc_dbg_stats_mmio) { + IPAERR("bad NULL parms for wdi_gsi_stats\n"); + return -EINVAL; + } + + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + for (i = 0; i < MAX_WDI2_CHANNELS; i++) { + stats->u.ring[i].ringFull = ioread32( + ipa3_ctx->wdi2_ctx.dbg_stats.uc_dbg_stats_mmio + + i * IPA3_UC_DEBUG_STATS_OFF + + IPA3_UC_DEBUG_STATS_RINGFULL_OFF); + stats->u.ring[i].ringEmpty = ioread32( + ipa3_ctx->wdi2_ctx.dbg_stats.uc_dbg_stats_mmio + + i * IPA3_UC_DEBUG_STATS_OFF + + IPA3_UC_DEBUG_STATS_RINGEMPTY_OFF); + stats->u.ring[i].ringUsageHigh = ioread32( + ipa3_ctx->wdi2_ctx.dbg_stats.uc_dbg_stats_mmio + + i * IPA3_UC_DEBUG_STATS_OFF + + IPA3_UC_DEBUG_STATS_RINGUSAGEHIGH_OFF); + stats->u.ring[i].ringUsageLow = ioread32( + ipa3_ctx->wdi2_ctx.dbg_stats.uc_dbg_stats_mmio + + i * IPA3_UC_DEBUG_STATS_OFF + + IPA3_UC_DEBUG_STATS_RINGUSAGELOW_OFF); + stats->u.ring[i].RingUtilCount = ioread32( + ipa3_ctx->wdi2_ctx.dbg_stats.uc_dbg_stats_mmio + + i * IPA3_UC_DEBUG_STATS_OFF + + IPA3_UC_DEBUG_STATS_RINGUTILCOUNT_OFF); + } + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + + return 0; +} + +/** + * ipa_get_wdi_stats() - Query WDI statistics from uc + * @stats: [inout] stats blob from client populated by driver + * + * Returns: 0 on success, negative on failure + * + * @note Cannot be called from atomic context + * + */ +int ipa_get_wdi_stats(struct IpaHwStatsWDIInfoData_t *stats) +{ +#define TX_STATS(y) stats->tx_ch_stats.y = \ + ipa3_ctx->uc_wdi_ctx.wdi_uc_stats_mmio->tx_ch_stats.y +#define RX_STATS(y) stats->rx_ch_stats.y = \ + ipa3_ctx->uc_wdi_ctx.wdi_uc_stats_mmio->rx_ch_stats.y + + if (!stats || !ipa3_ctx->uc_wdi_ctx.wdi_uc_stats_mmio) { + IPAERR("bad parms stats=%pK wdi_stats=%pK\n", + stats, + ipa3_ctx->uc_wdi_ctx.wdi_uc_stats_mmio); + return -EINVAL; + } + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + + TX_STATS(num_pkts_processed); + TX_STATS(copy_engine_doorbell_value); + TX_STATS(num_db_fired); + TX_STATS(tx_comp_ring_stats.ringFull); + TX_STATS(tx_comp_ring_stats.ringEmpty); + TX_STATS(tx_comp_ring_stats.ringUsageHigh); + TX_STATS(tx_comp_ring_stats.ringUsageLow); + TX_STATS(tx_comp_ring_stats.RingUtilCount); + TX_STATS(bam_stats.bamFifoFull); + TX_STATS(bam_stats.bamFifoEmpty); + TX_STATS(bam_stats.bamFifoUsageHigh); + TX_STATS(bam_stats.bamFifoUsageLow); + TX_STATS(bam_stats.bamUtilCount); + TX_STATS(num_db); + TX_STATS(num_unexpected_db); + TX_STATS(num_bam_int_handled); + TX_STATS(num_bam_int_in_non_running_state); + TX_STATS(num_qmb_int_handled); + TX_STATS(num_bam_int_handled_while_wait_for_bam); + + RX_STATS(max_outstanding_pkts); + RX_STATS(num_pkts_processed); + RX_STATS(rx_ring_rp_value); + RX_STATS(rx_ind_ring_stats.ringFull); + RX_STATS(rx_ind_ring_stats.ringEmpty); + RX_STATS(rx_ind_ring_stats.ringUsageHigh); + RX_STATS(rx_ind_ring_stats.ringUsageLow); + RX_STATS(rx_ind_ring_stats.RingUtilCount); + RX_STATS(bam_stats.bamFifoFull); + RX_STATS(bam_stats.bamFifoEmpty); + RX_STATS(bam_stats.bamFifoUsageHigh); + RX_STATS(bam_stats.bamFifoUsageLow); + RX_STATS(bam_stats.bamUtilCount); + RX_STATS(num_bam_int_handled); + RX_STATS(num_db); + RX_STATS(num_unexpected_db); + RX_STATS(num_pkts_in_dis_uninit_state); + RX_STATS(num_ic_inj_vdev_change); + RX_STATS(num_ic_inj_fw_desc_change); + RX_STATS(num_qmb_int_handled); + RX_STATS(reserved1); + RX_STATS(reserved2); + + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + + return 0; +} +EXPORT_SYMBOL(ipa_get_wdi_stats); + +int ipa3_wdi_init(void) +{ + struct ipa3_uc_hdlrs uc_wdi_cbs = { 0 }; + + uc_wdi_cbs.ipa_uc_event_hdlr = ipa3_uc_wdi_event_handler; + uc_wdi_cbs.ipa_uc_event_log_info_hdlr = + ipa3_uc_wdi_event_log_info_handler; + uc_wdi_cbs.ipa_uc_loaded_hdlr = + ipa3_uc_wdi_loaded_handler; + + ipa3_uc_register_handlers(IPA_HW_FEATURE_WDI, &uc_wdi_cbs); + + return 0; +} + +static int ipa_create_ap_smmu_mapping_pa(phys_addr_t pa, size_t len, + bool device, unsigned long *iova) +{ + struct ipa_smmu_cb_ctx *cb = ipa3_get_smmu_ctx(IPA_SMMU_CB_AP); + unsigned long va = roundup(cb->next_addr, PAGE_SIZE); + int prot = IOMMU_READ | IOMMU_WRITE; + size_t true_len = roundup(len + pa - rounddown(pa, PAGE_SIZE), + PAGE_SIZE); + int ret; + + if (!cb->valid) { + IPAERR("No SMMU CB setup\n"); + return -EINVAL; + } + + if (len > PAGE_SIZE) + va = roundup(cb->next_addr, len); + + ret = ipa3_iommu_map(cb->iommu_domain, va, rounddown(pa, PAGE_SIZE), + true_len, + device ? (prot | IOMMU_MMIO) : prot); + if (ret) { + IPAERR("iommu map failed for pa=%pa len=%zu\n", &pa, true_len); + return -EINVAL; + } + + ipa3_ctx->wdi_map_cnt++; + cb->next_addr = va + true_len; + if (cb->next_addr >= cb->geometry_end) + cb->next_addr = cb->va_end; + *iova = va + pa - rounddown(pa, PAGE_SIZE); + return 0; +} + +static int ipa_create_uc_smmu_mapping_pa(phys_addr_t pa, size_t len, + bool device, unsigned long *iova) +{ + struct ipa_smmu_cb_ctx *cb = ipa3_get_smmu_ctx(IPA_SMMU_CB_UC); + unsigned long va = roundup(cb->next_addr, PAGE_SIZE); + int prot = IOMMU_READ | IOMMU_WRITE; + size_t true_len = roundup(len + pa - rounddown(pa, PAGE_SIZE), + PAGE_SIZE); + int ret; + + if (!cb->valid) { + IPAERR("No SMMU CB setup\n"); + return -EINVAL; + } + + ret = ipa3_iommu_map(cb->iommu_domain, va, rounddown(pa, PAGE_SIZE), + true_len, + device ? (prot | IOMMU_MMIO) : prot); + if (ret) { + IPAERR("iommu map failed for pa=%pa len=%zu\n", &pa, true_len); + return -EINVAL; + } + + ipa3_ctx->wdi_map_cnt++; + cb->next_addr = va + true_len; + *iova = va + pa - rounddown(pa, PAGE_SIZE); + return 0; +} + +static int ipa_create_ap_smmu_mapping_sgt(struct sg_table *sgt, + unsigned long *iova) +{ + struct ipa_smmu_cb_ctx *cb = ipa3_get_smmu_ctx(IPA_SMMU_CB_AP); + unsigned long va = roundup(cb->next_addr, PAGE_SIZE); + int prot = IOMMU_READ | IOMMU_WRITE; + int ret, i; + struct scatterlist *sg; + unsigned long start_iova = va; + phys_addr_t phys; + size_t len = 0; + int count = 0; + + if (!cb->valid) { + IPAERR("No SMMU CB setup\n"); + return -EINVAL; + } + if (!sgt) { + IPAERR("Bad parameters, scatter / gather list is NULL\n"); + return -EINVAL; + } + + for_each_sg(sgt->sgl, sg, sgt->nents, i) { + /* directly get sg_tbl PA from wlan-driver */ + len += PAGE_ALIGN(sg->offset + sg->length); + } + + if (len > PAGE_SIZE) { + va = roundup(cb->next_addr, + roundup_pow_of_two(len)); + start_iova = va; + } + + for_each_sg(sgt->sgl, sg, sgt->nents, i) { + /* directly get sg_tbl PA from wlan-driver */ + phys = sg->dma_address; + len = PAGE_ALIGN(sg->offset + sg->length); + + ret = ipa3_iommu_map(cb->iommu_domain, va, phys, len, prot); + if (ret) { + IPAERR("iommu map failed for pa=%pa len=%zu\n", + &phys, len); + goto bad_mapping; + } + va += len; + ipa3_ctx->wdi_map_cnt++; + count++; + } + cb->next_addr = va; + + if (cb->next_addr >= cb->geometry_end) + cb->next_addr = cb->va_end; + + *iova = start_iova; + + return 0; + +bad_mapping: + for_each_sg(sgt->sgl, sg, count, i) + iommu_unmap(cb->iommu_domain, sg_dma_address(sg), + sg_dma_len(sg)); + return -EINVAL; +} + + +static int ipa_create_uc_smmu_mapping_sgt(struct sg_table *sgt, + unsigned long *iova) +{ + struct ipa_smmu_cb_ctx *cb = ipa3_get_smmu_ctx(IPA_SMMU_CB_UC); + unsigned long va = roundup(cb->next_addr, PAGE_SIZE); + int prot = IOMMU_READ | IOMMU_WRITE; + int ret; + int i; + struct scatterlist *sg; + unsigned long start_iova = va; + phys_addr_t phys; + size_t len; + int count = 0; + + if (!cb->valid) { + IPAERR("No SMMU CB setup\n"); + return -EINVAL; + } + if (!sgt) { + IPAERR("Bad parameters, scatter / gather list is NULL\n"); + return -EINVAL; + } + + for_each_sg(sgt->sgl, sg, sgt->nents, i) { + /* directly get sg_tbl PA from wlan-driver */ + phys = sg->dma_address; + len = PAGE_ALIGN(sg->offset + sg->length); + + ret = ipa3_iommu_map(cb->iommu_domain, va, phys, len, prot); + if (ret) { + IPAERR("iommu map failed for pa=%pa len=%zu\n", + &phys, len); + goto bad_mapping; + } + va += len; + ipa3_ctx->wdi_map_cnt++; + count++; + } + cb->next_addr = va; + *iova = start_iova; + + return 0; + +bad_mapping: + for_each_sg(sgt->sgl, sg, count, i) + iommu_unmap(cb->iommu_domain, sg_dma_address(sg), + sg_dma_len(sg)); + return -EINVAL; +} + +static void ipa_release_ap_smmu_mappings(enum ipa_client_type client) +{ + struct ipa_smmu_cb_ctx *cb = ipa3_get_smmu_ctx(IPA_SMMU_CB_AP); + int i, j, start, end; + + if (IPA_CLIENT_IS_CONS(client)) { + start = IPA_WDI_TX_RING_RES; + if (ipa_get_wdi_version() >= IPA_WDI_3) + end = IPA_WDI_TX_DB_RES; + else + end = IPA_WDI_CE_DB_RES; + } else { + start = IPA_WDI_RX_RING_RES; + if (ipa3_ctx->ipa_wdi2 || + (ipa_get_wdi_version() >= IPA_WDI_3)) + end = IPA_WDI_RX_COMP_RING_WP_RES; + else + end = IPA_WDI_RX_RING_RP_RES; + } + + for (i = start; i <= end; i++) { + if (wdi_res[i].valid) { + for (j = 0; j < wdi_res[i].nents; j++) { + iommu_unmap(cb->iommu_domain, + wdi_res[i].res[j].iova, + wdi_res[i].res[j].size); + ipa3_ctx->wdi_map_cnt--; + } + kfree(wdi_res[i].res); + wdi_res[i].res = NULL; + wdi_res[i].valid = false; + } + } + + if (ipa3_ctx->wdi_map_cnt == 0) + cb->next_addr = cb->va_end; +} + +static void ipa_release_uc_smmu_mappings(enum ipa_client_type client) +{ + struct ipa_smmu_cb_ctx *cb = ipa3_get_smmu_ctx(IPA_SMMU_CB_UC); + int i; + int j; + int start; + int end; + + if (IPA_CLIENT_IS_CONS(client)) { + start = IPA_WDI_TX_RING_RES; + end = IPA_WDI_CE_DB_RES; + } else { + start = IPA_WDI_RX_RING_RES; + if (ipa3_ctx->ipa_wdi2) + end = IPA_WDI_RX_COMP_RING_WP_RES; + else + end = IPA_WDI_RX_RING_RP_RES; + } + + for (i = start; i <= end; i++) { + if (wdi_res[i].valid) { + for (j = 0; j < wdi_res[i].nents; j++) { + iommu_unmap(cb->iommu_domain, + wdi_res[i].res[j].iova, + wdi_res[i].res[j].size); + ipa3_ctx->wdi_map_cnt--; + } + kfree(wdi_res[i].res); + wdi_res[i].res = NULL; + wdi_res[i].valid = false; + } + } + + if (ipa3_ctx->wdi_map_cnt == 0) + cb->next_addr = cb->va_end; + +} + +static void ipa_save_uc_smmu_mapping_pa(int res_idx, phys_addr_t pa, + unsigned long iova, size_t len) +{ + IPADBG("--res_idx=%d pa=0x%pa iova=0x%lx sz=0x%zx\n", res_idx, + &pa, iova, len); + wdi_res[res_idx].res = kzalloc(sizeof(*wdi_res[res_idx].res), + GFP_KERNEL); + if (!wdi_res[res_idx].res) { + WARN_ON(1); + return; + } + wdi_res[res_idx].nents = 1; + wdi_res[res_idx].valid = true; + wdi_res[res_idx].res->pa = rounddown(pa, PAGE_SIZE); + wdi_res[res_idx].res->iova = rounddown(iova, PAGE_SIZE); + wdi_res[res_idx].res->size = roundup(len + pa - rounddown(pa, + PAGE_SIZE), PAGE_SIZE); + IPADBG("res_idx=%d pa=0x%pa iova=0x%lx sz=0x%zx\n", res_idx, + &wdi_res[res_idx].res->pa, wdi_res[res_idx].res->iova, + wdi_res[res_idx].res->size); +} + +static void ipa_save_uc_smmu_mapping_sgt(int res_idx, struct sg_table *sgt, + unsigned long iova) +{ + int i; + struct scatterlist *sg; + unsigned long curr_iova = iova; + + if (!sgt) { + IPAERR("Bad parameters, scatter / gather list is NULL\n"); + return; + } + + wdi_res[res_idx].res = kcalloc(sgt->nents, + sizeof(*wdi_res[res_idx].res), + GFP_KERNEL); + if (!wdi_res[res_idx].res) { + WARN_ON(1); + return; + } + wdi_res[res_idx].nents = sgt->nents; + wdi_res[res_idx].valid = true; + for_each_sg(sgt->sgl, sg, sgt->nents, i) { + /* directly get sg_tbl PA from wlan */ + wdi_res[res_idx].res[i].pa = sg->dma_address; + wdi_res[res_idx].res[i].iova = curr_iova; + wdi_res[res_idx].res[i].size = PAGE_ALIGN(sg->offset + + sg->length); + IPADBG("res_idx=%d pa=0x%pa iova=0x%lx sz=0x%zx\n", res_idx, + &wdi_res[res_idx].res[i].pa, + wdi_res[res_idx].res[i].iova, + wdi_res[res_idx].res[i].size); + curr_iova += wdi_res[res_idx].res[i].size; + } +} + +int ipa_create_uc_smmu_mapping(int res_idx, bool wlan_smmu_en, + phys_addr_t pa, struct sg_table *sgt, size_t len, bool device, + unsigned long *iova) +{ + /* support for SMMU on WLAN but no SMMU on IPA */ + if (wlan_smmu_en && ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_UC]) { + IPAERR("Unsupported SMMU pairing\n"); + return -EINVAL; + } + + /* legacy: no SMMUs on either end */ + if (!wlan_smmu_en && ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_UC]) { + *iova = pa; + return 0; + } + + /* no SMMU on WLAN but SMMU on IPA */ + if (!wlan_smmu_en && !ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_UC]) { + if (ipa_create_uc_smmu_mapping_pa(pa, len, + (res_idx == IPA_WDI_CE_DB_RES) ? true : false, iova)) { + IPAERR("Fail to create mapping res %d\n", res_idx); + return -EFAULT; + } + ipa_save_uc_smmu_mapping_pa(res_idx, pa, *iova, len); + return 0; + } + + /* SMMU on WLAN and SMMU on IPA */ + if (wlan_smmu_en && !ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_UC]) { + switch (res_idx) { + case IPA_WDI_RX_RING_RP_RES: + case IPA_WDI_RX_COMP_RING_WP_RES: + case IPA_WDI_CE_DB_RES: + case IPA_WDI_TX_DB_RES: + if (ipa_create_uc_smmu_mapping_pa(pa, len, + (res_idx == IPA_WDI_CE_DB_RES) ? true : false, + iova)) { + IPAERR("Fail to create mapping res %d\n", + res_idx); + return -EFAULT; + } + ipa_save_uc_smmu_mapping_pa(res_idx, pa, *iova, len); + break; + case IPA_WDI_RX_RING_RES: + case IPA_WDI_RX_COMP_RING_RES: + case IPA_WDI_TX_RING_RES: + case IPA_WDI_CE_RING_RES: + if (ipa_create_uc_smmu_mapping_sgt(sgt, iova)) { + IPAERR("Fail to create mapping res %d\n", + res_idx); + WARN_ON(1); + return -EFAULT; + } + ipa_save_uc_smmu_mapping_sgt(res_idx, sgt, *iova); + break; + default: + WARN_ON(1); + } + } + + return 0; +} + +void ipa3_release_wdi3_gsi_smmu_mappings(u8 dir) +{ + struct ipa_smmu_cb_ctx *cb = ipa3_get_smmu_ctx(IPA_SMMU_CB_AP); + int i, j, start, end; + + if ((dir == IPA_WDI3_TX_DIR) || (dir == IPA_WDI3_TX1_DIR)) { + start = (dir == IPA_WDI3_TX_DIR) ? + IPA_WDI_TX_RING_RES : + IPA_WDI_TX1_RING_RES; + end = (dir == IPA_WDI3_TX_DIR) ? + IPA_WDI_TX_DB_RES : IPA_WDI_TX1_DB_RES; + } else if (dir == IPA_WDI3_TX2_DIR) { + start = IPA_WDI_TX2_RING_RES; + end = IPA_WDI_TX2_DB_RES; + } else if (dir == IPA_WDI3_RX_DIR) { + start = IPA_WDI_RX_RING_RES; + end = IPA_WDI_RX_COMP_RING_WP_RES; + } else { + start = IPA_WDI_RX2_RING_RES; + end = IPA_WDI_RX2_COMP_RING_WP_RES; + } + + for (i = start; i <= end; i++) { + if (wdi_res[i].valid) { + for (j = 0; j < wdi_res[i].nents; j++) { + iommu_unmap(cb->iommu_domain, + wdi_res[i].res[j].iova, + wdi_res[i].res[j].size); + ipa3_ctx->wdi_map_cnt--; + } + kfree(wdi_res[i].res); + wdi_res[i].res = NULL; + wdi_res[i].valid = false; + } + } + + if (ipa3_ctx->wdi_map_cnt == 0 || cb->next_addr >= cb->geometry_end) + cb->next_addr = cb->va_end; +} + +int ipa_create_gsi_smmu_mapping(int res_idx, bool wlan_smmu_en, + phys_addr_t pa, struct sg_table *sgt, size_t len, bool device, + unsigned long *iova) +{ + /* support for SMMU on WLAN but no SMMU on IPA */ + if (wlan_smmu_en && ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_AP]) { + IPAERR("Unsupported SMMU pairing\n"); + return -EINVAL; + } + + /* legacy: no SMMUs on either end */ + if (!wlan_smmu_en && ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_AP]) { + *iova = pa; + return 0; + } + + /* no SMMU on WLAN but SMMU on IPA */ + if (!wlan_smmu_en && !ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_AP]) { + if (ipa_create_ap_smmu_mapping_pa(pa, len, + (res_idx == IPA_WDI_CE_DB_RES) ? true : false, + iova)) { + IPAERR("Fail to create mapping res %d\n", + res_idx); + return -EFAULT; + } + ipa_save_uc_smmu_mapping_pa(res_idx, pa, *iova, len); + return 0; + } + /* SMMU on WLAN and SMMU on IPA */ + if (wlan_smmu_en && !ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_AP]) { + switch (res_idx) { + case IPA_WDI_RX_RING_RP_RES: + case IPA_WDI_RX_COMP_RING_WP_RES: + case IPA_WDI_CE_DB_RES: + case IPA_WDI_TX_DB_RES: + case IPA_WDI_CE1_DB_RES: + case IPA_WDI_TX1_DB_RES: + case IPA_WDI_RX2_RING_RP_RES: + case IPA_WDI_RX2_COMP_RING_WP_RES: + case IPA_WDI_CE2_DB_RES: + case IPA_WDI_TX2_DB_RES: + + if (ipa_create_ap_smmu_mapping_pa(pa, len, + ((res_idx == IPA_WDI_CE_DB_RES) || + (res_idx == IPA_WDI_CE2_DB_RES)) ? true : false, + iova)) { + IPAERR("Fail to create mapping res %d\n", + res_idx); + return -EFAULT; + } + ipa_save_uc_smmu_mapping_pa(res_idx, pa, *iova, len); + break; + case IPA_WDI_RX_RING_RES: + case IPA_WDI_RX_COMP_RING_RES: + case IPA_WDI_TX_RING_RES: + case IPA_WDI_CE_RING_RES: + case IPA_WDI_TX1_RING_RES: + case IPA_WDI_CE1_RING_RES: + case IPA_WDI_RX2_RING_RES: + case IPA_WDI_RX2_COMP_RING_RES: + case IPA_WDI_TX2_RING_RES: + case IPA_WDI_CE2_RING_RES: + + if (ipa_create_ap_smmu_mapping_sgt(sgt, iova)) { + IPAERR("Fail to create mapping res %d\n", + res_idx); + return -EFAULT; + } + ipa_save_uc_smmu_mapping_sgt(res_idx, sgt, *iova); + break; + default: + WARN_ON(1); + } + } + return 0; +} + +static void ipa_gsi_evt_ring_err_cb(struct gsi_evt_err_notify *notify) +{ + switch (notify->evt_id) { + case GSI_EVT_OUT_OF_BUFFERS_ERR: + IPAERR("Got GSI_EVT_OUT_OF_BUFFERS_ERR\n"); + break; + case GSI_EVT_OUT_OF_RESOURCES_ERR: + IPAERR("Got GSI_EVT_OUT_OF_RESOURCES_ERR\n"); + break; + case GSI_EVT_UNSUPPORTED_INTER_EE_OP_ERR: + IPAERR("Got GSI_EVT_UNSUPPORTED_INTER_EE_OP_ERR\n"); + break; + case GSI_EVT_EVT_RING_EMPTY_ERR: + IPAERR("Got GSI_EVT_EVT_RING_EMPTY_ERR\n"); + break; + default: + IPAERR("Unexpected err evt: %d\n", notify->evt_id); + } + ipa_assert(); +} + +static void ipa_gsi_chan_err_cb(struct gsi_chan_err_notify *notify) +{ + switch (notify->evt_id) { + case GSI_CHAN_INVALID_TRE_ERR: + IPAERR("Got GSI_CHAN_INVALID_TRE_ERR\n"); + break; + case GSI_CHAN_NON_ALLOCATED_EVT_ACCESS_ERR: + IPAERR("Got GSI_CHAN_NON_ALLOCATED_EVT_ACCESS_ERR\n"); + break; + case GSI_CHAN_OUT_OF_BUFFERS_ERR: + IPAERR("Got GSI_CHAN_OUT_OF_BUFFERS_ERR\n"); + break; + case GSI_CHAN_OUT_OF_RESOURCES_ERR: + IPAERR("Got GSI_CHAN_OUT_OF_RESOURCES_ERR\n"); + break; + case GSI_CHAN_UNSUPPORTED_INTER_EE_OP_ERR: + IPAERR("Got GSI_CHAN_UNSUPPORTED_INTER_EE_OP_ERR\n"); + break; + case GSI_CHAN_HWO_1_ERR: + IPAERR("Got GSI_CHAN_HWO_1_ERR\n"); + break; + default: + IPAERR("Unexpected err evt: %d\n", notify->evt_id); + } + ipa_assert(); +} +static int ipa3_wdi2_gsi_alloc_evt_ring( + struct gsi_evt_ring_props *evt_ring_props, + enum ipa_client_type client, + unsigned long *evt_ring_hdl) +{ + union __packed gsi_evt_scratch evt_scratch; + int result = -EFAULT; + + /* GSI EVENT RING allocation */ + evt_ring_props->intf = GSI_EVT_CHTYPE_WDI2_EV; + evt_ring_props->intr = GSI_INTR_IRQ; + + if (IPA_CLIENT_IS_PROD(client)) + evt_ring_props->re_size = GSI_EVT_RING_RE_SIZE_8B; + else + evt_ring_props->re_size = GSI_EVT_RING_RE_SIZE_16B; + + evt_ring_props->exclusive = true; + evt_ring_props->err_cb = ipa_gsi_evt_ring_err_cb; + evt_ring_props->user_data = NULL; + evt_ring_props->int_modt = IPA_GSI_EVT_RING_INT_MODT; + evt_ring_props->int_modc = 1; + IPADBG("GSI evt ring len: %d\n", evt_ring_props->ring_len); + IPADBG("client=%d moderation threshold cycles=%u cnt=%u\n", + client, + evt_ring_props->int_modt, + evt_ring_props->int_modc); + + + result = gsi_alloc_evt_ring(evt_ring_props, + ipa3_ctx->gsi_dev_hdl, evt_ring_hdl); + IPADBG("gsi_alloc_evt_ring result: %d\n", result); + if (result != GSI_STATUS_SUCCESS) + goto fail_alloc_evt_ring; + + evt_scratch.wdi.update_ri_moderation_config = + UPDATE_RI_MODERATION_THRESHOLD; + evt_scratch.wdi.update_ri_mod_timer_running = 0; + evt_scratch.wdi.evt_comp_count = 0; + evt_scratch.wdi.last_update_ri = 0; + evt_scratch.wdi.resvd1 = 0; + evt_scratch.wdi.resvd2 = 0; + result = gsi_write_evt_ring_scratch(*evt_ring_hdl, evt_scratch); + if (result != GSI_STATUS_SUCCESS) { + IPAERR("Error writing WDI event ring scratch: %d\n", result); + gsi_dealloc_evt_ring(*evt_ring_hdl); + return -EFAULT; + } + +fail_alloc_evt_ring: + return result; + +} +static int ipa3_wdi2_gsi_alloc_channel_ring( + struct gsi_chan_props *channel_props, + enum ipa_client_type client, + unsigned long *chan_hdl, + unsigned long evt_ring_hdl) +{ + int result = -EFAULT; + const struct ipa_gsi_ep_config *ep_cfg; + + ep_cfg = ipa_get_gsi_ep_info(client); + if (!ep_cfg) { + IPAERR("Failed getting GSI EP info for client=%d\n", + client); + return -EPERM; + } + + if (IPA_CLIENT_IS_PROD(client)) { + IPAERR("Client is PROD\n"); + channel_props->dir = GSI_CHAN_DIR_TO_GSI; + channel_props->re_size = GSI_CHAN_RE_SIZE_16B; + } else { + IPAERR("Client is CONS"); + channel_props->dir = GSI_CHAN_DIR_FROM_GSI; + channel_props->re_size = GSI_CHAN_RE_SIZE_8B; + } + + channel_props->prot = GSI_CHAN_PROT_WDI2; + channel_props->ch_id = ep_cfg->ipa_gsi_chan_num; + channel_props->evt_ring_hdl = evt_ring_hdl; + + IPADBG("ch_id: %d\n", channel_props->ch_id); + IPADBG("evt_ring_hdl: %ld\n", channel_props->evt_ring_hdl); + IPADBG("re_size: %d\n", channel_props->re_size); + IPADBG("Config GSI xfer cb func"); + IPADBG("GSI channel ring len: %d\n", channel_props->ring_len); + channel_props->xfer_cb = NULL; + + IPADBG("channel ring base vaddr = 0x%pa\n", + channel_props->ring_base_vaddr); + + channel_props->use_db_eng = GSI_CHAN_DB_MODE; + channel_props->max_prefetch = GSI_ONE_PREFETCH_SEG; + channel_props->prefetch_mode = ep_cfg->prefetch_mode; + channel_props->low_weight = 1; + channel_props->err_cb = ipa_gsi_chan_err_cb; + + IPADBG("Allocating GSI channel\n"); + result = gsi_alloc_channel(channel_props, + ipa3_ctx->gsi_dev_hdl, + chan_hdl); + if (result != GSI_STATUS_SUCCESS) + goto fail_alloc_channel; + + IPADBG("gsi_chan_hdl: %ld\n", *chan_hdl); + +fail_alloc_channel: + return result; +} + + +int ipa3_connect_gsi_wdi_pipe(struct ipa_wdi_in_params *in, + struct ipa_wdi_out_params *out) +{ + u32 len; + int ipa_ep_idx, num_ring_ele; + int result = -EFAULT; + enum gsi_status gsi_res; + struct ipa3_ep_context *ep; + struct ipa_ep_cfg_ctrl ep_cfg_ctrl; + struct gsi_chan_props gsi_channel_props; + struct gsi_evt_ring_props gsi_evt_ring_props; + union __packed gsi_channel_scratch gsi_scratch; + phys_addr_t pa; + unsigned long va; + unsigned long wifi_rx_ri_addr = 0; + u32 gsi_db_reg_phs_addr_lsb; + u32 gsi_db_reg_phs_addr_msb; + uint32_t addr_low, addr_high; + bool is_evt_rn_db_pcie_addr, is_txr_rn_db_pcie_addr; + + ipa_ep_idx = ipa_get_ep_mapping(in->sys.client); + if (ipa_ep_idx == -1) { + IPAERR("fail to alloc EP.\n"); + goto fail; + } + + ep = &ipa3_ctx->ep[ipa_ep_idx]; + + if (ep->valid) { + IPAERR("EP already allocated.\n"); + goto fail; + } + + IPA_ACTIVE_CLIENTS_INC_EP(in->sys.client); + + memset(&ipa3_ctx->ep[ipa_ep_idx], 0, sizeof(struct ipa3_ep_context)); + memset(&gsi_evt_ring_props, 0, sizeof(gsi_evt_ring_props)); + memset(&gsi_channel_props, 0, sizeof(gsi_channel_props)); + memset(&gsi_scratch, 0, sizeof(gsi_scratch)); + + IPADBG("client=%d ep=%d\n", in->sys.client, ipa_ep_idx); + + if (IPA_CLIENT_IS_CONS(in->sys.client)) { + if (in->smmu_enabled) { + IPADBG("comp_ring_size=%d\n", + in->u.dl_smmu.comp_ring_size); + IPADBG("ce_ring_size=%d\n", in->u.dl_smmu.ce_ring_size); + IPADBG("ce_ring_doorbell_pa=0x%pa\n", + &in->u.dl_smmu.ce_door_bell_pa); + IPADBG("num_tx_buffers=%d\n", + in->u.dl_smmu.num_tx_buffers); + } else { + IPADBG("comp_ring_base_pa=0x%pa\n", + &in->u.dl.comp_ring_base_pa); + IPADBG("comp_ring_size=%d\n", in->u.dl.comp_ring_size); + IPADBG("ce_ring_base_pa=0x%pa\n", + &in->u.dl.ce_ring_base_pa); + IPADBG("ce_ring_size=%d\n", in->u.dl.ce_ring_size); + IPADBG("ce_ring_doorbell_pa=0x%pa\n", + &in->u.dl.ce_door_bell_pa); + IPADBG("num_tx_buffers=%d\n", in->u.dl.num_tx_buffers); + } + } else { + if (in->smmu_enabled) { + IPADBG("rx_ring_size=%d\n", + in->u.ul_smmu.rdy_ring_size); + IPADBG("rx_ring_rp_pa=0x%pa\n", + &in->u.ul_smmu.rdy_ring_rp_pa); + IPADBG("rx_comp_ring_size=%d\n", + in->u.ul_smmu.rdy_comp_ring_size); + IPADBG("rx_comp_ring_wp_pa=0x%pa\n", + &in->u.ul_smmu.rdy_comp_ring_wp_pa); + ipa3_ctx->wdi2_ctx.rdy_ring_rp_pa = + in->u.ul_smmu.rdy_ring_rp_pa; + ipa3_ctx->wdi2_ctx.rdy_ring_size = + in->u.ul_smmu.rdy_ring_size; + ipa3_ctx->wdi2_ctx.rdy_comp_ring_wp_pa = + in->u.ul_smmu.rdy_comp_ring_wp_pa; + ipa3_ctx->wdi2_ctx.rdy_comp_ring_size = + in->u.ul_smmu.rdy_comp_ring_size; + } else { + IPADBG("rx_ring_base_pa=0x%pa\n", + &in->u.ul.rdy_ring_base_pa); + IPADBG("rx_ring_size=%d\n", + in->u.ul.rdy_ring_size); + IPADBG("rx_ring_rp_pa=0x%pa\n", + &in->u.ul.rdy_ring_rp_pa); + IPADBG("rx_comp_ring_base_pa=0x%pa\n", + &in->u.ul.rdy_comp_ring_base_pa); + IPADBG("rx_comp_ring_size=%d\n", + in->u.ul.rdy_comp_ring_size); + IPADBG("rx_comp_ring_wp_pa=0x%pa\n", + &in->u.ul.rdy_comp_ring_wp_pa); + ipa3_ctx->wdi2_ctx.rdy_ring_base_pa = + in->u.ul.rdy_ring_base_pa; + ipa3_ctx->wdi2_ctx.rdy_ring_rp_pa = + in->u.ul.rdy_ring_rp_pa; + ipa3_ctx->wdi2_ctx.rdy_ring_size = + in->u.ul.rdy_ring_size; + ipa3_ctx->wdi2_ctx.rdy_comp_ring_base_pa = + in->u.ul.rdy_comp_ring_base_pa; + ipa3_ctx->wdi2_ctx.rdy_comp_ring_wp_pa = + in->u.ul.rdy_comp_ring_wp_pa; + ipa3_ctx->wdi2_ctx.rdy_comp_ring_size = + in->u.ul.rdy_comp_ring_size; + } + } + if (IPA_CLIENT_IS_CONS(in->sys.client)) { + len = in->smmu_enabled ? in->u.dl_smmu.comp_ring_size : + in->u.dl.comp_ring_size; + IPADBG("TX ring smmu_en=%d ring_size=%d %d\n", + in->smmu_enabled, + in->u.dl_smmu.comp_ring_size, + in->u.dl.comp_ring_size); + if (ipa_create_gsi_smmu_mapping(IPA_WDI_TX_RING_RES, + in->smmu_enabled, + in->u.dl.comp_ring_base_pa, + &in->u.dl_smmu.comp_ring, + len, + false, + &va)) { + IPAERR("fail to create gsi mapping TX ring.\n"); + result = -ENOMEM; + goto gsi_timeout; + } + gsi_channel_props.ring_base_addr = va; + gsi_channel_props.ring_base_vaddr = NULL; + gsi_channel_props.ring_len = len; + + len = in->smmu_enabled ? in->u.dl_smmu.ce_ring_size : + in->u.dl.ce_ring_size; + IPADBG("CE ring smmu_en=%d ring_size=%d %d\n", + in->smmu_enabled, + in->u.dl_smmu.ce_ring_size, + in->u.dl.ce_ring_size); + + /* WA: wlan passed ce_ring sg_table PA directly */ + if (ipa_create_gsi_smmu_mapping(IPA_WDI_CE_RING_RES, + in->smmu_enabled, + in->u.dl.ce_ring_base_pa, + &in->u.dl_smmu.ce_ring, + len, + false, + &va)) { + IPAERR("fail to create gsi mapping CE ring.\n"); + result = -ENOMEM; + goto gsi_timeout; + } + gsi_evt_ring_props.ring_base_addr = va; + gsi_evt_ring_props.ring_base_vaddr = NULL; + gsi_evt_ring_props.ring_len = len; + pa = in->smmu_enabled ? in->u.dl_smmu.ce_door_bell_pa : + in->u.dl.ce_door_bell_pa; + if (ipa_create_gsi_smmu_mapping(IPA_WDI_CE_DB_RES, + in->smmu_enabled, + pa, + NULL, + 4, + true, + &va)) { + IPAERR("fail to create gsi mapping CE DB.\n"); + result = -ENOMEM; + goto gsi_timeout; + } + gsi_evt_ring_props.rp_update_addr = va; + } else { + len = in->smmu_enabled ? in->u.ul_smmu.rdy_ring_size : + in->u.ul.rdy_ring_size; + IPADBG("RX ring smmu_en=%d ring_size=%d %d\n", + in->smmu_enabled, + in->u.ul_smmu.rdy_ring_size, + in->u.ul.rdy_ring_size); + if (ipa_create_gsi_smmu_mapping(IPA_WDI_RX_RING_RES, + in->smmu_enabled, + in->u.ul.rdy_ring_base_pa, + &in->u.ul_smmu.rdy_ring, + len, + false, + &va)) { + IPAERR("fail to create gsi RX ring.\n"); + result = -ENOMEM; + goto gsi_timeout; + } + gsi_channel_props.ring_base_addr = va; + gsi_channel_props.ring_base_vaddr = NULL; + gsi_channel_props.ring_len = len; + len = in->smmu_enabled ? + in->u.ul_smmu.rdy_comp_ring_size : + in->u.ul.rdy_comp_ring_size; + IPADBG("RX ring smmu_en=%d comp_ring_size=%d %d\n", + in->smmu_enabled, + in->u.ul_smmu.rdy_comp_ring_size, + in->u.ul.rdy_comp_ring_size); + if (ipa_create_gsi_smmu_mapping( + IPA_WDI_RX_COMP_RING_RES, + in->smmu_enabled, + in->u.ul.rdy_comp_ring_base_pa, + &in->u.ul_smmu.rdy_comp_ring, + len, + false, + &va)) { + IPAERR("fail to create gsi RX comp_ring.\n"); + result = -ENOMEM; + goto gsi_timeout; + } + gsi_evt_ring_props.ring_base_addr = va; + pa = in->smmu_enabled ? in->u.ul_smmu.rdy_ring_rp_pa : + in->u.ul.rdy_ring_rp_pa; + if (ipa_create_gsi_smmu_mapping(IPA_WDI_RX_RING_RP_RES, + in->smmu_enabled, + pa, + NULL, + 4, + false, + &wifi_rx_ri_addr)) { + IPAERR("fail to create gsi RX rng RP\n"); + result = -ENOMEM; + goto gsi_timeout; + } + gsi_evt_ring_props.ring_base_vaddr = NULL; + gsi_evt_ring_props.ring_len = len; + pa = in->smmu_enabled ? + in->u.ul_smmu.rdy_comp_ring_wp_pa : + in->u.ul.rdy_comp_ring_wp_pa; + if (ipa_create_gsi_smmu_mapping( + IPA_WDI_RX_COMP_RING_WP_RES, + in->smmu_enabled, + pa, + NULL, + 4, + false, + &va)) { + IPAERR("fail to create gsi RX comp_rng WP\n"); + result = -ENOMEM; + goto gsi_timeout; + } + gsi_evt_ring_props.rp_update_addr = va; + } + + ep->valid = 1; + ep->client = in->sys.client; + ep->keep_ipa_awake = in->sys.keep_ipa_awake; + ep->skip_ep_cfg = in->sys.skip_ep_cfg; + ep->client_notify = in->sys.notify; + ep->priv = in->sys.priv; + if (IPA_CLIENT_IS_CONS(in->sys.client)) { + in->sys.ipa_ep_cfg.aggr.aggr_en = IPA_ENABLE_AGGR; + in->sys.ipa_ep_cfg.aggr.aggr = IPA_GENERIC; + in->sys.ipa_ep_cfg.aggr.aggr_pkt_limit = IPA_AGGR_PKT_LIMIT; + in->sys.ipa_ep_cfg.aggr.aggr_byte_limit = + IPA_AGGR_HARD_BYTE_LIMIT; + in->sys.ipa_ep_cfg.aggr.aggr_hard_byte_limit_en = + IPA_ENABLE_AGGR; + } + if (!ep->skip_ep_cfg) { + if (ipa3_cfg_ep(ipa_ep_idx, &in->sys.ipa_ep_cfg)) { + IPAERR("fail to configure EP.\n"); + goto ipa_cfg_ep_fail; + } + IPADBG("ep configuration successful\n"); + } else { + IPADBG("Skipping endpoint configuration.\n"); + } + result = ipa3_wdi2_gsi_alloc_evt_ring(&gsi_evt_ring_props, + in->sys.client, + &ep->gsi_evt_ring_hdl); + if (result) + goto fail_alloc_evt_ring; + + is_evt_rn_db_pcie_addr = IPA_CLIENT_IS_CONS(in->sys.client) ? + in->u.dl.is_evt_rn_db_pcie_addr : + in->u.ul.is_evt_rn_db_pcie_addr; + + if (IPA_CLIENT_IS_CONS(in->sys.client)) { + is_evt_rn_db_pcie_addr = in->smmu_enabled ? + in->u.dl_smmu.is_evt_rn_db_pcie_addr : + in->u.dl.is_evt_rn_db_pcie_addr; + gsi_evt_ring_props.rp_update_addr = in->smmu_enabled ? + in->u.dl_smmu.ce_door_bell_pa : + in->u.dl.ce_door_bell_pa; + } else { + is_evt_rn_db_pcie_addr = in->smmu_enabled ? + in->u.ul_smmu.is_evt_rn_db_pcie_addr : + in->u.ul.is_evt_rn_db_pcie_addr; + gsi_evt_ring_props.rp_update_addr = in->smmu_enabled ? + in->u.ul_smmu.rdy_comp_ring_wp_pa : + in->u.ul.rdy_comp_ring_wp_pa; + } + if (!in->smmu_enabled) { + IPADBG("smmu disabled\n"); + if (is_evt_rn_db_pcie_addr == true) + IPADBG("is_evt_rn_db_pcie_addr is PCIE addr\n"); + else + IPADBG("is_evt_rn_db_pcie_addr is DDR addr\n"); + + addr_low = (u32)gsi_evt_ring_props.rp_update_addr; + addr_high = (u32)((u64)gsi_evt_ring_props.rp_update_addr >> 32); + } else { + IPADBG("smmu enabled\n"); + if (is_evt_rn_db_pcie_addr == true) + IPADBG("is_evt_rn_db_pcie_addr is PCIE addr\n"); + else + IPADBG("is_evt_rn_db_pcie_addr is DDR addr\n"); + + if (IPA_CLIENT_IS_CONS(in->sys.client)) { + if (ipa_create_gsi_smmu_mapping(IPA_WDI_CE_DB_RES, + true, gsi_evt_ring_props.rp_update_addr, + NULL, 4, true, &va)) { + IPAERR("failed to get smmu mapping\n"); + result = -EFAULT; + goto fail_alloc_evt_ring; + } + } else { + if (ipa_create_gsi_smmu_mapping( + IPA_WDI_RX_COMP_RING_WP_RES, + true, gsi_evt_ring_props.rp_update_addr, + NULL, 4, true, &va)) { + IPAERR("failed to get smmu mapping\n"); + result = -EFAULT; + goto fail_alloc_evt_ring; + } + } + addr_low = (u32)va; + addr_high = (u32)((u64)va >> 32); + } + + /* + * Arch specific: + * pcie addr which are not via smmu, use pa directly! + * pcie and DDR via 2 different port + * assert bit 40 to indicate it is pcie addr + * WDI-3.0, MSM --> pcie via smmu + * WDI-3.0, MDM --> pcie not via smmu + dual port + * assert bit 40 in case + */ + if (!ipa3_is_msm_device() && + in->smmu_enabled) { + /* + * Ir-respective of smmu enabled don't use IOVA addr + * since pcie not via smmu in MDM's + */ + if (is_evt_rn_db_pcie_addr == true) { + addr_low = (u32)gsi_evt_ring_props.rp_update_addr; + addr_high = + (u32)((u64)gsi_evt_ring_props.rp_update_addr + >> 32); + } + } + + /* + * GSI recomendation to set bit-40 for (mdm targets && pcie addr) + * from wdi-3.0 interface document + */ + if (!ipa3_is_msm_device() && is_evt_rn_db_pcie_addr) + addr_high |= (1 << 8); + + gsi_wdi3_write_evt_ring_db(ep->gsi_evt_ring_hdl, addr_low, + addr_high); + + /*copy mem info */ + ep->gsi_mem_info.evt_ring_len = gsi_evt_ring_props.ring_len; + ep->gsi_mem_info.evt_ring_base_addr = gsi_evt_ring_props.ring_base_addr; + ep->gsi_mem_info.evt_ring_base_vaddr = + gsi_evt_ring_props.ring_base_vaddr; + IPAERR("evt ring len: %d\n", ep->gsi_mem_info.evt_ring_len); + IPAERR("element size: %d\n", gsi_evt_ring_props.re_size); + + result = ipa3_wdi2_gsi_alloc_channel_ring(&gsi_channel_props, + in->sys.client, + &ep->gsi_chan_hdl, ep->gsi_evt_ring_hdl); + if (result) + goto fail_alloc_channel; + + if (IPA_CLIENT_IS_PROD(in->sys.client)) { + memset(&ep_cfg_ctrl, 0, sizeof(struct ipa_ep_cfg_ctrl)); + ep_cfg_ctrl.ipa_ep_delay = true; + ipa_cfg_ep_ctrl(ipa_ep_idx, &ep_cfg_ctrl); + } + + ep->gsi_mem_info.chan_ring_len = gsi_channel_props.ring_len; + ep->gsi_mem_info.chan_ring_base_addr = gsi_channel_props.ring_base_addr; + ep->gsi_mem_info.chan_ring_base_vaddr = + gsi_channel_props.ring_base_vaddr; + + num_ring_ele = ep->gsi_mem_info.evt_ring_len/gsi_evt_ring_props.re_size; + IPAERR("UPDATE_RI_MODERATION_THRESHOLD: %d\n", num_ring_ele); + if (ipa3_ctx->ipa_hw_type < IPA_HW_v4_7) { + if (IPA_CLIENT_IS_PROD(in->sys.client)) { + is_txr_rn_db_pcie_addr = + in->smmu_enabled ? + in->u.ul_smmu.is_txr_rn_db_pcie_addr : + in->u.ul.is_txr_rn_db_pcie_addr; + if (!in->smmu_enabled) { + IPADBG("smmu disabled\n"); + gsi_scratch.wdi2_new.wifi_rx_ri_addr_low = + in->u.ul.rdy_ring_rp_pa & 0xFFFFFFFF; + gsi_scratch.wdi2_new.wifi_rx_ri_addr_high = + (in->u.ul.rdy_ring_rp_pa & + 0xFFFFF00000000) >> 32; + } else { + IPADBG("smmu eabled\n"); + gsi_scratch.wdi.wifi_rx_ri_addr_low = + wifi_rx_ri_addr & 0xFFFFFFFF; + gsi_scratch.wdi.wifi_rx_ri_addr_high = + (wifi_rx_ri_addr & 0xFFFFF00000000) >> 32; + } + + /* + * Arch specific: + * pcie addr which are not via smmu, use pa directly! + * pcie and DDR via 2 different port + * assert bit 40 to indicate it is pcie addr + * WDI-3.0, MSM --> pcie via smmu + * WDI-3.0, MDM --> pcie not via smmu + dual port + * assert bit 40 in case + */ + if (!ipa3_is_msm_device() && + in->smmu_enabled) { + /* + * Ir-respective of smmu enabled don't use IOVA + * addr since pcie not via smmu in MDM's + */ + if (is_txr_rn_db_pcie_addr == true) { + gsi_scratch.wdi2_new.wifi_rx_ri_addr_low + = in->u.ul_smmu.rdy_ring_rp_pa + & 0xFFFFFFFF; + gsi_scratch.wdi2_new.wifi_rx_ri_addr_high = + (in->u.ul_smmu.rdy_ring_rp_pa & + 0xFFFFF00000000) >> 32; + } + } + + /* + * GSI recomendation to set bit-40 for + * (mdm targets && pcie addr) from wdi-3.0 + * interface document + */ + + if (!ipa3_is_msm_device() && is_txr_rn_db_pcie_addr) + gsi_scratch.wdi2_new.wifi_rx_ri_addr_high = + (u32)((u32) + gsi_scratch.wdi2_new.wifi_rx_ri_addr_high | + (1 << 8)); + + gsi_scratch.wdi.wdi_rx_vdev_id = 0xff; + gsi_scratch.wdi.wdi_rx_fw_desc = 0xff; + gsi_scratch.wdi.endp_metadatareg_offset = + ipahal_get_reg_mn_ofst( + IPA_ENDP_INIT_HDR_METADATA_n, 0, + ipa_ep_idx)/4; + gsi_scratch.wdi.qmap_id = 0; + } + gsi_scratch.wdi.update_ri_moderation_threshold = + min(UPDATE_RI_MODERATION_THRESHOLD, num_ring_ele); + gsi_scratch.wdi.update_ri_moderation_counter = 0; + gsi_scratch.wdi.wdi_rx_tre_proc_in_progress = 0; + } else { + if (IPA_CLIENT_IS_PROD(in->sys.client)) { + gsi_scratch.wdi2_new.wifi_rx_ri_addr_low = + wifi_rx_ri_addr & 0xFFFFFFFF; + gsi_scratch.wdi2_new.wifi_rx_ri_addr_high = + (wifi_rx_ri_addr & 0xFFFFF00000000) >> 32; + gsi_scratch.wdi2_new.wdi_rx_vdev_id = 0xff; + gsi_scratch.wdi2_new.wdi_rx_fw_desc = 0xff; + gsi_scratch.wdi2_new.endp_metadatareg_offset = + ipahal_get_reg_mn_ofst( + IPA_ENDP_INIT_HDR_METADATA_n, 0, + ipa_ep_idx)/4; + gsi_scratch.wdi2_new.qmap_id = 0; + } + gsi_scratch.wdi2_new.update_ri_moderation_threshold = + min(UPDATE_RI_MODERATION_THRESHOLD, num_ring_ele); + gsi_scratch.wdi2_new.update_ri_moderation_counter = 0; + gsi_scratch.wdi2_new.wdi_rx_tre_proc_in_progress = 0; + } + + result = gsi_write_channel_scratch(ep->gsi_chan_hdl, + gsi_scratch); + if (result != GSI_STATUS_SUCCESS) { + IPAERR("gsi_write_channel_scratch failed %d\n", + result); + goto fail_write_channel_scratch; + } + + /* for AP+STA stats update */ + if (in->wdi_notify) + ipa3_ctx->uc_wdi_ctx.stats_notify = in->wdi_notify; + else + IPADBG("in->wdi_notify is null\n"); + + ipa3_enable_data_path(ipa_ep_idx); + + if (!ep->skip_ep_cfg && IPA_CLIENT_IS_PROD(in->sys.client)) + ipa3_install_dflt_flt_rules(ipa_ep_idx); + + if (!ep->keep_ipa_awake) + IPA_ACTIVE_CLIENTS_DEC_EP(in->sys.client); + + IPADBG("GSI connected.\n"); + gsi_res = gsi_query_channel_db_addr(ep->gsi_chan_hdl, + &gsi_db_reg_phs_addr_lsb, + &gsi_db_reg_phs_addr_msb); + out->uc_door_bell_pa = gsi_db_reg_phs_addr_lsb; + IPADBG("GSI query result: %d\n", gsi_res); + IPADBG("GSI lsb addr: %d\n", gsi_db_reg_phs_addr_lsb); + IPADBG("GSI msb addr: %d\n", gsi_db_reg_phs_addr_msb); + + ep->gsi_offload_state |= IPA_WDI_CONNECTED; + out->clnt_hdl = ipa_ep_idx; + return 0; + +fail_write_channel_scratch: + gsi_dealloc_channel(ep->gsi_chan_hdl); +fail_alloc_channel: + if (ep->gsi_evt_ring_hdl != ~0) { + gsi_dealloc_evt_ring(ep->gsi_evt_ring_hdl); + ep->gsi_evt_ring_hdl = ~0; + } +fail_alloc_evt_ring: +ipa_cfg_ep_fail: + memset(&ipa3_ctx->ep[ipa_ep_idx], 0, sizeof(struct ipa3_ep_context)); +gsi_timeout: + ipa_release_ap_smmu_mappings(in->sys.client); + IPA_ACTIVE_CLIENTS_DEC_EP(in->sys.client); +fail: + return result; +} + +/** + * ipa_connect_wdi_pipe() - WDI client connect + * @in: [in] input parameters from client + * @out: [out] output params to client + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa_connect_wdi_pipe(struct ipa_wdi_in_params *in, + struct ipa_wdi_out_params *out) +{ + int ipa_ep_idx; + int result = -EFAULT; + struct ipa3_ep_context *ep; + struct ipa_mem_buffer cmd; + struct IpaHwWdiTxSetUpCmdData_t *tx; + struct IpaHwWdiRxSetUpCmdData_t *rx; + struct IpaHwWdi2TxSetUpCmdData_t *tx_2; + struct IpaHwWdi2RxSetUpCmdData_t *rx_2; + + struct ipa_ep_cfg_ctrl ep_cfg_ctrl; + unsigned long va; + phys_addr_t pa; + u32 len; + + if (ipa3_ctx->use_pm_wrapper) + return ipa_pm_wrapper_connect_wdi_pipe(in, out); + + if (in == NULL || out == NULL || in->sys.client >= IPA_CLIENT_MAX) { + IPAERR("bad parm. in=%pK out=%pK\n", in, out); + if (in) + IPAERR("client = %d\n", in->sys.client); + return -EINVAL; + } + + if (!in->smmu_enabled) { + if (IPA_CLIENT_IS_CONS(in->sys.client)) { + if (in->u.dl.comp_ring_base_pa % + IPA_WDI_RING_ALIGNMENT || + in->u.dl.ce_ring_base_pa % + IPA_WDI_RING_ALIGNMENT) { + IPAERR("alignment failure on TX\n"); + return -EINVAL; + } + } else { + if (in->u.ul.rdy_ring_base_pa % + IPA_WDI_RING_ALIGNMENT) { + IPAERR("alignment failure on RX\n"); + return -EINVAL; + } + } + } + + if (IPA_WDI2_OVER_GSI()) + return ipa3_connect_gsi_wdi_pipe(in, out); + + result = ipa3_uc_state_check(); + if (result) + return result; + + ipa_ep_idx = ipa_get_ep_mapping(in->sys.client); + if (ipa_ep_idx == -1) { + IPAERR("fail to alloc EP.\n"); + goto fail; + } + + ep = &ipa3_ctx->ep[ipa_ep_idx]; + + if (ep->valid) { + IPAERR("EP already allocated.\n"); + goto fail; + } + + memset(&ipa3_ctx->ep[ipa_ep_idx], 0, sizeof(struct ipa3_ep_context)); + IPA_ACTIVE_CLIENTS_INC_EP(in->sys.client); + + IPADBG("client=%d ep=%d\n", in->sys.client, ipa_ep_idx); + if (IPA_CLIENT_IS_CONS(in->sys.client)) { + if (ipa3_ctx->ipa_wdi2) + cmd.size = sizeof(*tx_2); + else + cmd.size = sizeof(*tx); + if (in->smmu_enabled) { + IPADBG("comp_ring_size=%d\n", + in->u.dl_smmu.comp_ring_size); + IPADBG("ce_ring_size=%d\n", in->u.dl_smmu.ce_ring_size); + IPADBG("ce_ring_doorbell_pa=0x%pa\n", + &in->u.dl_smmu.ce_door_bell_pa); + IPADBG("num_tx_buffers=%d\n", + in->u.dl_smmu.num_tx_buffers); + } else { + IPADBG("comp_ring_base_pa=0x%pa\n", + &in->u.dl.comp_ring_base_pa); + IPADBG("comp_ring_size=%d\n", in->u.dl.comp_ring_size); + IPADBG("ce_ring_base_pa=0x%pa\n", + &in->u.dl.ce_ring_base_pa); + IPADBG("ce_ring_size=%d\n", in->u.dl.ce_ring_size); + IPADBG("ce_ring_doorbell_pa=0x%pa\n", + &in->u.dl.ce_door_bell_pa); + IPADBG("num_tx_buffers=%d\n", in->u.dl.num_tx_buffers); + } + } else { + if (ipa3_ctx->ipa_wdi2) + cmd.size = sizeof(*rx_2); + else + cmd.size = sizeof(*rx); + if (in->smmu_enabled) { + IPADBG("rx_ring_size=%d\n", + in->u.ul_smmu.rdy_ring_size); + IPADBG("rx_ring_rp_pa=0x%pa\n", + &in->u.ul_smmu.rdy_ring_rp_pa); + IPADBG("rx_comp_ring_size=%d\n", + in->u.ul_smmu.rdy_comp_ring_size); + IPADBG("rx_comp_ring_wp_pa=0x%pa\n", + &in->u.ul_smmu.rdy_comp_ring_wp_pa); + ipa3_ctx->uc_ctx.rdy_ring_rp_pa = + in->u.ul_smmu.rdy_ring_rp_pa; + ipa3_ctx->uc_ctx.rdy_ring_size = + in->u.ul_smmu.rdy_ring_size; + ipa3_ctx->uc_ctx.rdy_comp_ring_wp_pa = + in->u.ul_smmu.rdy_comp_ring_wp_pa; + ipa3_ctx->uc_ctx.rdy_comp_ring_size = + in->u.ul_smmu.rdy_comp_ring_size; + } else { + IPADBG("rx_ring_base_pa=0x%pa\n", + &in->u.ul.rdy_ring_base_pa); + IPADBG("rx_ring_size=%d\n", + in->u.ul.rdy_ring_size); + IPADBG("rx_ring_rp_pa=0x%pa\n", + &in->u.ul.rdy_ring_rp_pa); + IPADBG("rx_comp_ring_base_pa=0x%pa\n", + &in->u.ul.rdy_comp_ring_base_pa); + IPADBG("rx_comp_ring_size=%d\n", + in->u.ul.rdy_comp_ring_size); + IPADBG("rx_comp_ring_wp_pa=0x%pa\n", + &in->u.ul.rdy_comp_ring_wp_pa); + ipa3_ctx->uc_ctx.rdy_ring_base_pa = + in->u.ul.rdy_ring_base_pa; + ipa3_ctx->uc_ctx.rdy_ring_rp_pa = + in->u.ul.rdy_ring_rp_pa; + ipa3_ctx->uc_ctx.rdy_ring_size = + in->u.ul.rdy_ring_size; + ipa3_ctx->uc_ctx.rdy_comp_ring_base_pa = + in->u.ul.rdy_comp_ring_base_pa; + ipa3_ctx->uc_ctx.rdy_comp_ring_wp_pa = + in->u.ul.rdy_comp_ring_wp_pa; + ipa3_ctx->uc_ctx.rdy_comp_ring_size = + in->u.ul.rdy_comp_ring_size; + } + } + + cmd.base = dma_alloc_coherent(ipa3_ctx->uc_pdev, cmd.size, + &cmd.phys_base, GFP_KERNEL); + if (cmd.base == NULL) { + IPAERR("fail to get DMA memory.\n"); + result = -ENOMEM; + goto dma_alloc_fail; + } + + if (IPA_CLIENT_IS_CONS(in->sys.client)) { + if (ipa3_ctx->ipa_wdi2) { + tx_2 = (struct IpaHwWdi2TxSetUpCmdData_t *)cmd.base; + + len = in->smmu_enabled ? in->u.dl_smmu.comp_ring_size : + in->u.dl.comp_ring_size; + IPADBG("TX_2 ring smmu_en=%d ring_size=%d %d\n", + in->smmu_enabled, + in->u.dl_smmu.comp_ring_size, + in->u.dl.comp_ring_size); + if (ipa_create_uc_smmu_mapping(IPA_WDI_TX_RING_RES, + in->smmu_enabled, + in->u.dl.comp_ring_base_pa, + &in->u.dl_smmu.comp_ring, + len, + false, + &va)) { + IPAERR("fail to create uc mapping TX ring.\n"); + result = -ENOMEM; + goto uc_timeout; + } + tx_2->comp_ring_base_pa_hi = + (u32) ((va & 0xFFFFFFFF00000000) >> 32); + tx_2->comp_ring_base_pa = (u32) (va & 0xFFFFFFFF); + tx_2->comp_ring_size = len; + IPADBG("TX_2 comp_ring_base_pa_hi=0x%08x :0x%08x\n", + tx_2->comp_ring_base_pa_hi, + tx_2->comp_ring_base_pa); + + len = in->smmu_enabled ? in->u.dl_smmu.ce_ring_size : + in->u.dl.ce_ring_size; + IPADBG("TX_2 CE ring smmu_en=%d ring_size=%d %d\n", + in->smmu_enabled, + in->u.dl_smmu.ce_ring_size, + in->u.dl.ce_ring_size); + /* WA: wlan passed ce_ring sg_table PA directly */ + if (ipa_create_uc_smmu_mapping(IPA_WDI_CE_RING_RES, + in->smmu_enabled, + in->u.dl.ce_ring_base_pa, + &in->u.dl_smmu.ce_ring, + len, + false, + &va)) { + IPAERR("fail to create uc mapping CE ring.\n"); + result = -ENOMEM; + goto uc_timeout; + } + tx_2->ce_ring_base_pa_hi = + (u32) ((va & 0xFFFFFFFF00000000) >> 32); + tx_2->ce_ring_base_pa = (u32) (va & 0xFFFFFFFF); + tx_2->ce_ring_size = len; + IPADBG("TX_2 ce_ring_base_pa_hi=0x%08x :0x%08x\n", + tx_2->ce_ring_base_pa_hi, + tx_2->ce_ring_base_pa); + + pa = in->smmu_enabled ? in->u.dl_smmu.ce_door_bell_pa : + in->u.dl.ce_door_bell_pa; + if (ipa_create_uc_smmu_mapping(IPA_WDI_CE_DB_RES, + in->smmu_enabled, + pa, + NULL, + 4, + true, + &va)) { + IPAERR("fail to create uc mapping CE DB.\n"); + result = -ENOMEM; + goto uc_timeout; + } + tx_2->ce_ring_doorbell_pa_hi = + (u32) ((va & 0xFFFFFFFF00000000) >> 32); + tx_2->ce_ring_doorbell_pa = (u32) (va & 0xFFFFFFFF); + IPADBG("TX_2 ce_ring_doorbell_pa_hi=0x%08x :0x%08x\n", + tx_2->ce_ring_doorbell_pa_hi, + tx_2->ce_ring_doorbell_pa); + + tx_2->num_tx_buffers = in->smmu_enabled ? + in->u.dl_smmu.num_tx_buffers : + in->u.dl.num_tx_buffers; + tx_2->ipa_pipe_number = ipa_ep_idx; + } else { + tx = (struct IpaHwWdiTxSetUpCmdData_t *)cmd.base; + + len = in->smmu_enabled ? in->u.dl_smmu.comp_ring_size : + in->u.dl.comp_ring_size; + IPADBG("TX ring smmu_en=%d ring_size=%d %d\n", + in->smmu_enabled, + in->u.dl_smmu.comp_ring_size, + in->u.dl.comp_ring_size); + if (ipa_create_uc_smmu_mapping(IPA_WDI_TX_RING_RES, + in->smmu_enabled, + in->u.dl.comp_ring_base_pa, + &in->u.dl_smmu.comp_ring, + len, + false, + &va)) { + IPAERR("fail to create uc mapping TX ring.\n"); + result = -ENOMEM; + goto uc_timeout; + } + tx->comp_ring_base_pa = va; + tx->comp_ring_size = len; + len = in->smmu_enabled ? in->u.dl_smmu.ce_ring_size : + in->u.dl.ce_ring_size; + IPADBG("TX CE ring smmu_en=%d ring_size=%d %d 0x%lx\n", + in->smmu_enabled, + in->u.dl_smmu.ce_ring_size, + in->u.dl.ce_ring_size, + va); + if (ipa_create_uc_smmu_mapping(IPA_WDI_CE_RING_RES, + in->smmu_enabled, + in->u.dl.ce_ring_base_pa, + &in->u.dl_smmu.ce_ring, + len, + false, + &va)) { + IPAERR("fail to create uc mapping CE ring.\n"); + result = -ENOMEM; + goto uc_timeout; + } + tx->ce_ring_base_pa = va; + tx->ce_ring_size = len; + pa = in->smmu_enabled ? in->u.dl_smmu.ce_door_bell_pa : + in->u.dl.ce_door_bell_pa; + if (ipa_create_uc_smmu_mapping(IPA_WDI_CE_DB_RES, + in->smmu_enabled, + pa, + NULL, + 4, + true, + &va)) { + IPAERR("fail to create uc mapping CE DB.\n"); + result = -ENOMEM; + goto uc_timeout; + } + + IPADBG("CE doorbell pa: 0x%pa va:0x%lx\n", &pa, va); + IPADBG("Is wdi_over_pcie ? (%s)\n", + ipa3_ctx->wdi_over_pcie ? "Yes":"No"); + + if (ipa3_ctx->wdi_over_pcie) + tx->ce_ring_doorbell_pa = pa; + else + tx->ce_ring_doorbell_pa = va; + + tx->num_tx_buffers = in->smmu_enabled ? + in->u.dl_smmu.num_tx_buffers : + in->u.dl.num_tx_buffers; + tx->ipa_pipe_number = ipa_ep_idx; + } + out->uc_door_bell_pa = ipa3_ctx->ipa_wrapper_base + + ipahal_get_reg_base() + + ipahal_get_reg_mn_ofst(IPA_UC_MAILBOX_m_n, + IPA_HW_WDI_TX_MBOX_START_INDEX/32, + IPA_HW_WDI_TX_MBOX_START_INDEX % 32); + } else { + if (ipa3_ctx->ipa_wdi2) { + rx_2 = (struct IpaHwWdi2RxSetUpCmdData_t *)cmd.base; + + len = in->smmu_enabled ? in->u.ul_smmu.rdy_ring_size : + in->u.ul.rdy_ring_size; + IPADBG("RX_2 ring smmu_en=%d ring_size=%d %d\n", + in->smmu_enabled, + in->u.ul_smmu.rdy_ring_size, + in->u.ul.rdy_ring_size); + if (ipa_create_uc_smmu_mapping(IPA_WDI_RX_RING_RES, + in->smmu_enabled, + in->u.ul.rdy_ring_base_pa, + &in->u.ul_smmu.rdy_ring, + len, + false, + &va)) { + IPAERR("fail to create uc RX_2 ring.\n"); + result = -ENOMEM; + goto uc_timeout; + } + rx_2->rx_ring_base_pa_hi = + (u32) ((va & 0xFFFFFFFF00000000) >> 32); + rx_2->rx_ring_base_pa = (u32) (va & 0xFFFFFFFF); + rx_2->rx_ring_size = len; + IPADBG("RX_2 rx_ring_base_pa_hi=0x%08x:0x%08x\n", + rx_2->rx_ring_base_pa_hi, + rx_2->rx_ring_base_pa); + + pa = in->smmu_enabled ? in->u.ul_smmu.rdy_ring_rp_pa : + in->u.ul.rdy_ring_rp_pa; + if (ipa_create_uc_smmu_mapping(IPA_WDI_RX_RING_RP_RES, + in->smmu_enabled, + pa, + NULL, + 4, + false, + &va)) { + IPAERR("fail to create uc RX_2 rng RP\n"); + result = -ENOMEM; + goto uc_timeout; + } + rx_2->rx_ring_rp_pa_hi = + (u32) ((va & 0xFFFFFFFF00000000) >> 32); + rx_2->rx_ring_rp_pa = (u32) (va & 0xFFFFFFFF); + IPADBG("RX_2 rx_ring_rp_pa_hi=0x%08x :0x%08x\n", + rx_2->rx_ring_rp_pa_hi, + rx_2->rx_ring_rp_pa); + len = in->smmu_enabled ? + in->u.ul_smmu.rdy_comp_ring_size : + in->u.ul.rdy_comp_ring_size; + IPADBG("RX_2 ring smmu_en=%d comp_ring_size=%d %d\n", + in->smmu_enabled, + in->u.ul_smmu.rdy_comp_ring_size, + in->u.ul.rdy_comp_ring_size); + if (ipa_create_uc_smmu_mapping(IPA_WDI_RX_COMP_RING_RES, + in->smmu_enabled, + in->u.ul.rdy_comp_ring_base_pa, + &in->u.ul_smmu.rdy_comp_ring, + len, + false, + &va)) { + IPAERR("fail to create uc RX_2 comp_ring.\n"); + result = -ENOMEM; + goto uc_timeout; + } + rx_2->rx_comp_ring_base_pa_hi = + (u32) ((va & 0xFFFFFFFF00000000) >> 32); + rx_2->rx_comp_ring_base_pa = (u32) (va & 0xFFFFFFFF); + rx_2->rx_comp_ring_size = len; + IPADBG("RX_2 rx_comp_ring_base_pa_hi=0x%08x:0x%08x\n", + rx_2->rx_comp_ring_base_pa_hi, + rx_2->rx_comp_ring_base_pa); + + pa = in->smmu_enabled ? + in->u.ul_smmu.rdy_comp_ring_wp_pa : + in->u.ul.rdy_comp_ring_wp_pa; + if (ipa_create_uc_smmu_mapping( + IPA_WDI_RX_COMP_RING_WP_RES, + in->smmu_enabled, + pa, + NULL, + 4, + false, + &va)) { + IPAERR("fail to create uc RX_2 comp_rng WP\n"); + result = -ENOMEM; + goto uc_timeout; + } + rx_2->rx_comp_ring_wp_pa_hi = + (u32) ((va & 0xFFFFFFFF00000000) >> 32); + rx_2->rx_comp_ring_wp_pa = (u32) (va & 0xFFFFFFFF); + IPADBG("RX_2 rx_comp_ring_wp_pa_hi=0x%08x:0x%08x\n", + rx_2->rx_comp_ring_wp_pa_hi, + rx_2->rx_comp_ring_wp_pa); + rx_2->ipa_pipe_number = ipa_ep_idx; + } else { + rx = (struct IpaHwWdiRxSetUpCmdData_t *)cmd.base; + + len = in->smmu_enabled ? in->u.ul_smmu.rdy_ring_size : + in->u.ul.rdy_ring_size; + IPADBG("RX ring smmu_en=%d ring_size=%d %d\n", + in->smmu_enabled, + in->u.ul_smmu.rdy_ring_size, + in->u.ul.rdy_ring_size); + if (ipa_create_uc_smmu_mapping(IPA_WDI_RX_RING_RES, + in->smmu_enabled, + in->u.ul.rdy_ring_base_pa, + &in->u.ul_smmu.rdy_ring, + len, + false, + &va)) { + IPAERR("fail to create uc mapping RX ring.\n"); + result = -ENOMEM; + goto uc_timeout; + } + rx->rx_ring_base_pa = va; + rx->rx_ring_size = len; + + pa = in->smmu_enabled ? in->u.ul_smmu.rdy_ring_rp_pa : + in->u.ul.rdy_ring_rp_pa; + if (ipa_create_uc_smmu_mapping(IPA_WDI_RX_RING_RP_RES, + in->smmu_enabled, + pa, + NULL, + 4, + false, + &va)) { + IPAERR("fail to create uc mapping RX rng RP\n"); + result = -ENOMEM; + goto uc_timeout; + } + rx->rx_ring_rp_pa = va; + rx->ipa_pipe_number = ipa_ep_idx; + } + out->uc_door_bell_pa = ipa3_ctx->ipa_wrapper_base + + ipahal_get_reg_base() + + ipahal_get_reg_mn_ofst(IPA_UC_MAILBOX_m_n, + IPA_HW_WDI_RX_MBOX_START_INDEX/32, + IPA_HW_WDI_RX_MBOX_START_INDEX % 32); + } + + ep->valid = 1; + ep->client = in->sys.client; + ep->keep_ipa_awake = in->sys.keep_ipa_awake; + result = ipa3_disable_data_path(ipa_ep_idx); + if (result) { + IPAERR("disable data path failed res=%d clnt=%d.\n", result, + ipa_ep_idx); + goto uc_timeout; + } + if (IPA_CLIENT_IS_PROD(in->sys.client)) { + memset(&ep_cfg_ctrl, 0, sizeof(struct ipa_ep_cfg_ctrl)); + ep_cfg_ctrl.ipa_ep_delay = true; + ipa_cfg_ep_ctrl(ipa_ep_idx, &ep_cfg_ctrl); + } + + result = ipa3_uc_send_cmd((u32)(cmd.phys_base), + IPA_CLIENT_IS_CONS(in->sys.client) ? + IPA_CPU_2_HW_CMD_WDI_TX_SET_UP : + IPA_CPU_2_HW_CMD_WDI_RX_SET_UP, + IPA_HW_2_CPU_WDI_CMD_STATUS_SUCCESS, + false, 10*HZ); + + if (result) { + result = -EFAULT; + goto uc_timeout; + } + + ep->skip_ep_cfg = in->sys.skip_ep_cfg; + ep->client_notify = in->sys.notify; + ep->priv = in->sys.priv; + + /* for AP+STA stats update */ + if (in->wdi_notify) + ipa3_ctx->uc_wdi_ctx.stats_notify = in->wdi_notify; + else + IPADBG("in->wdi_notify is null\n"); + + if (IPA_CLIENT_IS_CONS(in->sys.client)) { + in->sys.ipa_ep_cfg.aggr.aggr_en = IPA_ENABLE_AGGR; + in->sys.ipa_ep_cfg.aggr.aggr = IPA_GENERIC; + in->sys.ipa_ep_cfg.aggr.aggr_pkt_limit = IPA_AGGR_PKT_LIMIT; + in->sys.ipa_ep_cfg.aggr.aggr_byte_limit = + IPA_AGGR_HARD_BYTE_LIMIT; + in->sys.ipa_ep_cfg.aggr.aggr_hard_byte_limit_en = + IPA_ENABLE_AGGR; + } + if (!ep->skip_ep_cfg) { + if (ipa3_cfg_ep(ipa_ep_idx, &in->sys.ipa_ep_cfg)) { + IPAERR("fail to configure EP.\n"); + goto ipa_cfg_ep_fail; + } + IPADBG("ep configuration successful\n"); + } else { + IPADBG("Skipping endpoint configuration.\n"); + } + + ipa3_enable_data_path(ipa_ep_idx); + + out->clnt_hdl = ipa_ep_idx; + + if (!ep->skip_ep_cfg && IPA_CLIENT_IS_PROD(in->sys.client)) + ipa3_install_dflt_flt_rules(ipa_ep_idx); + + if (!ep->keep_ipa_awake) + IPA_ACTIVE_CLIENTS_DEC_EP(in->sys.client); + + dma_free_coherent(ipa3_ctx->uc_pdev, cmd.size, cmd.base, cmd.phys_base); + ep->uc_offload_state |= IPA_WDI_CONNECTED; + IPADBG("client %d (ep: %d) connected\n", in->sys.client, ipa_ep_idx); + + return 0; + +ipa_cfg_ep_fail: + memset(&ipa3_ctx->ep[ipa_ep_idx], 0, sizeof(struct ipa3_ep_context)); +uc_timeout: + ipa_release_uc_smmu_mappings(in->sys.client); + dma_free_coherent(ipa3_ctx->uc_pdev, cmd.size, cmd.base, cmd.phys_base); +dma_alloc_fail: + IPA_ACTIVE_CLIENTS_DEC_EP(in->sys.client); +fail: + return result; +} +EXPORT_SYMBOL(ipa_connect_wdi_pipe); + +int ipa3_disconnect_gsi_wdi_pipe(u32 clnt_hdl) +{ + int result = 0; + struct ipa3_ep_context *ep; + + ep = &ipa3_ctx->ep[clnt_hdl]; + + if (ep->gsi_offload_state != IPA_WDI_CONNECTED) { + IPAERR("WDI channel bad state %d\n", ep->gsi_offload_state); + return -EFAULT; + } + + if (!ep->keep_ipa_awake) + IPA_ACTIVE_CLIENTS_INC_EP(ipa3_get_client_mapping(clnt_hdl)); + + ipa3_reset_gsi_channel(clnt_hdl); + ipa3_reset_gsi_event_ring(clnt_hdl); + + if (!ep->keep_ipa_awake) + IPA_ACTIVE_CLIENTS_DEC_EP(ipa3_get_client_mapping(clnt_hdl)); + + result = ipa3_release_gsi_channel(clnt_hdl); + if (result) { + IPAERR("GSI dealloc channel failed %d\n", + result); + goto fail_dealloc_channel; + } + ipa_release_ap_smmu_mappings(clnt_hdl); + + /* for AP+STA stats update */ + if (ipa3_ctx->uc_wdi_ctx.stats_notify) + ipa3_ctx->uc_wdi_ctx.stats_notify = NULL; + else + IPADBG("uc_wdi_ctx.stats_notify already null\n"); + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_5 && + ipa3_ctx->ipa_hw_type != IPA_HW_v4_7 && + ipa3_ctx->ipa_hw_type != IPA_HW_v4_11 && + ipa3_ctx->ipa_hw_type != IPA_HW_v5_2) + ipa3_uc_debug_stats_dealloc(IPA_HW_PROTOCOL_WDI); + IPADBG("client (ep: %d) disconnected\n", clnt_hdl); + +fail_dealloc_channel: + return result; +} + +/** + * ipa_disconnect_wdi_pipe() - WDI client disconnect + * @clnt_hdl: [in] opaque client handle assigned by IPA to client + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa_disconnect_wdi_pipe(u32 clnt_hdl) +{ + int result = 0; + struct ipa3_ep_context *ep; + union IpaHwWdiCommonChCmdData_t tear; + + if (ipa3_ctx->use_pm_wrapper) + return ipa_pm_wrapper_disconnect_wdi_pipe(clnt_hdl); + + if (clnt_hdl >= ipa3_ctx->ipa_num_pipes || + ipa3_ctx->ep[clnt_hdl].valid == 0) { + IPAERR("bad parm, %d\n", clnt_hdl); + return -EINVAL; + } + + if (IPA_WDI2_OVER_GSI()) + return ipa3_disconnect_gsi_wdi_pipe(clnt_hdl); + + result = ipa3_uc_state_check(); + if (result) + return result; + + IPADBG("ep=%d\n", clnt_hdl); + + ep = &ipa3_ctx->ep[clnt_hdl]; + + if (ep->uc_offload_state != IPA_WDI_CONNECTED) { + IPAERR("WDI channel bad state %d\n", ep->uc_offload_state); + return -EFAULT; + } + + if (!ep->keep_ipa_awake) + IPA_ACTIVE_CLIENTS_INC_EP(ipa3_get_client_mapping(clnt_hdl)); + + tear.params.ipa_pipe_number = clnt_hdl; + + result = ipa3_uc_send_cmd(tear.raw32b, + IPA_CPU_2_HW_CMD_WDI_TEAR_DOWN, + IPA_HW_2_CPU_WDI_CMD_STATUS_SUCCESS, + false, 10*HZ); + + if (result) { + result = -EFAULT; + goto uc_timeout; + } + + ipa3_delete_dflt_flt_rules(clnt_hdl); + ipa_release_uc_smmu_mappings(ep->client); + + memset(&ipa3_ctx->ep[clnt_hdl], 0, sizeof(struct ipa3_ep_context)); + + IPADBG("client (ep: %d) disconnected\n", clnt_hdl); + + /* for AP+STA stats update */ + if (ipa3_ctx->uc_wdi_ctx.stats_notify) + ipa3_ctx->uc_wdi_ctx.stats_notify = NULL; + else + IPADBG("uc_wdi_ctx.stats_notify already null\n"); + +uc_timeout: + IPA_ACTIVE_CLIENTS_DEC_EP(ipa3_get_client_mapping(clnt_hdl)); + return result; +} +EXPORT_SYMBOL(ipa_disconnect_wdi_pipe); + +int ipa3_enable_gsi_wdi_pipe(u32 clnt_hdl) +{ + int result = 0; + struct ipa3_ep_context *ep; + struct ipa_ep_cfg_ctrl ep_cfg_ctrl; + int ipa_ep_idx; + struct ipa_ep_cfg_holb holb_cfg; + + IPADBG("ep=%d\n", clnt_hdl); + + ep = &ipa3_ctx->ep[clnt_hdl]; + if (ep->gsi_offload_state != IPA_WDI_CONNECTED) { + IPAERR("WDI channel bad state %d\n", ep->gsi_offload_state); + return -EFAULT; + } + + ipa_ep_idx = ipa_get_ep_mapping(ipa3_get_client_mapping(clnt_hdl)); + if (ipa_ep_idx == -1) { + IPAERR("fail to alloc EP.\n"); + return -EPERM; + } + + IPA_ACTIVE_CLIENTS_INC_EP(ipa3_get_client_mapping(clnt_hdl)); + + memset(&ep_cfg_ctrl, 0, sizeof(struct ipa_ep_cfg_ctrl)); + ipa_cfg_ep_ctrl(ipa_ep_idx, &ep_cfg_ctrl); + + if (IPA_CLIENT_IS_CONS(ep->client)) { + memset(&holb_cfg, 0, sizeof(holb_cfg)); + holb_cfg.en = IPA_HOLB_TMR_DIS; + holb_cfg.tmr_val = 0; + ipa3_cfg_ep_holb(clnt_hdl, &holb_cfg); + } + + + IPA_ACTIVE_CLIENTS_DEC_EP(ipa3_get_client_mapping(clnt_hdl)); + ep->gsi_offload_state |= IPA_WDI_ENABLED; + IPADBG("client (ep: %d) enabled\n", clnt_hdl); + + return result; +} +int ipa3_disable_gsi_wdi_pipe(u32 clnt_hdl) +{ + int result = 0; + struct ipa3_ep_context *ep; + struct ipa_ep_cfg_ctrl ep_cfg_ctrl; + u32 cons_hdl; + + IPADBG("ep=%d\n", clnt_hdl); + + ep = &ipa3_ctx->ep[clnt_hdl]; + + if (ep->gsi_offload_state != (IPA_WDI_CONNECTED | IPA_WDI_ENABLED)) { + IPAERR("WDI channel bad state %d\n", ep->gsi_offload_state); + return -EFAULT; + } + IPA_ACTIVE_CLIENTS_INC_EP(ipa3_get_client_mapping(clnt_hdl)); + + result = ipa3_disable_data_path(clnt_hdl); + if (result) { + IPAERR("disable data path failed res=%d clnt=%d.\n", result, + clnt_hdl); + goto gsi_timeout; + } + + /** + * To avoid data stall during continuous SAP on/off before + * setting delay to IPA Consumer pipe (Client Producer), + * remove delay and enable holb on IPA Producer pipe + */ + if (IPA_CLIENT_IS_PROD(ep->client)) { + IPADBG("Stopping PROD channel - hdl=%d clnt=%d\n", + clnt_hdl, ep->client); + /* remove delay on wlan-prod pipe*/ + memset(&ep_cfg_ctrl, 0, sizeof(struct ipa_ep_cfg_ctrl)); + ipa_cfg_ep_ctrl(clnt_hdl, &ep_cfg_ctrl); + + cons_hdl = ipa_get_ep_mapping(IPA_CLIENT_WLAN1_CONS); + if (cons_hdl == IPA_EP_NOT_ALLOCATED) { + IPAERR("Client %u is not mapped\n", + IPA_CLIENT_WLAN1_CONS); + goto gsi_timeout; + } + if (ipa3_ctx->ep[cons_hdl].valid == 1) { + result = ipa3_disable_data_path(cons_hdl); + if (result) { + IPAERR("disable data path failed\n"); + IPAERR("res=%d clnt=%d\n", + result, cons_hdl); + goto gsi_timeout; + } + } + usleep_range(IPA_UC_POLL_SLEEP_USEC * IPA_UC_POLL_SLEEP_USEC, + IPA_UC_POLL_SLEEP_USEC * IPA_UC_POLL_SLEEP_USEC); + + } + + /* Set the delay after disabling IPA Producer pipe */ + if (IPA_CLIENT_IS_PROD(ep->client)) { + memset(&ep_cfg_ctrl, 0, sizeof(struct ipa_ep_cfg_ctrl)); + ep_cfg_ctrl.ipa_ep_delay = true; + ipa_cfg_ep_ctrl(clnt_hdl, &ep_cfg_ctrl); + } + ep->gsi_offload_state &= ~IPA_WDI_ENABLED; + IPADBG("client (ep: %d) disabled\n", clnt_hdl); + +gsi_timeout: + IPA_ACTIVE_CLIENTS_DEC_EP(ipa3_get_client_mapping(clnt_hdl)); + return result; +} +/** + * ipa_enable_wdi_pipe() - WDI client enable + * @clnt_hdl: [in] opaque client handle assigned by IPA to client + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa_enable_wdi_pipe(u32 clnt_hdl) +{ + int result = 0; + struct ipa3_ep_context *ep; + union IpaHwWdiCommonChCmdData_t enable; + struct ipa_ep_cfg_holb holb_cfg; + + if (ipa3_ctx->use_pm_wrapper) + return ipa_pm_wrapper_enable_wdi_pipe(clnt_hdl); + + if (clnt_hdl >= ipa3_ctx->ipa_num_pipes || + ipa3_ctx->ep[clnt_hdl].valid == 0) { + IPAERR("bad parm, %d\n", clnt_hdl); + return -EINVAL; + } + + if (IPA_WDI2_OVER_GSI()) + return ipa3_enable_gsi_wdi_pipe(clnt_hdl); + + result = ipa3_uc_state_check(); + if (result) + return result; + + IPADBG("ep=%d\n", clnt_hdl); + + ep = &ipa3_ctx->ep[clnt_hdl]; + + if (ep->uc_offload_state != IPA_WDI_CONNECTED) { + IPAERR("WDI channel bad state %d\n", ep->uc_offload_state); + return -EFAULT; + } + IPA_ACTIVE_CLIENTS_INC_EP(ipa3_get_client_mapping(clnt_hdl)); + enable.params.ipa_pipe_number = clnt_hdl; + + result = ipa3_uc_send_cmd(enable.raw32b, + IPA_CPU_2_HW_CMD_WDI_CH_ENABLE, + IPA_HW_2_CPU_WDI_CMD_STATUS_SUCCESS, + false, 10*HZ); + + if (result) { + result = -EFAULT; + goto uc_timeout; + } + + if (IPA_CLIENT_IS_CONS(ep->client)) { + memset(&holb_cfg, 0, sizeof(holb_cfg)); + holb_cfg.en = IPA_HOLB_TMR_DIS; + holb_cfg.tmr_val = 0; + result = ipa3_cfg_ep_holb(clnt_hdl, &holb_cfg); + } + + ep->uc_offload_state |= IPA_WDI_ENABLED; + IPADBG("client (ep: %d) enabled\n", clnt_hdl); + +uc_timeout: + IPA_ACTIVE_CLIENTS_DEC_EP(ipa3_get_client_mapping(clnt_hdl)); + return result; +} +EXPORT_SYMBOL(ipa_enable_wdi_pipe); + +/** + * ipa_disable_wdi_pipe() - WDI client disable + * @clnt_hdl: [in] opaque client handle assigned by IPA to client + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa_disable_wdi_pipe(u32 clnt_hdl) +{ + int result = 0; + struct ipa3_ep_context *ep; + union IpaHwWdiCommonChCmdData_t disable; + struct ipa_ep_cfg_ctrl ep_cfg_ctrl; + u32 cons_hdl; + + if (ipa3_ctx->use_pm_wrapper) + return ipa_pm_wrapper_disable_pipe(clnt_hdl); + + if (clnt_hdl >= ipa3_ctx->ipa_num_pipes || + ipa3_ctx->ep[clnt_hdl].valid == 0) { + IPAERR("bad parm, %d\n", clnt_hdl); + return -EINVAL; + } + + if (IPA_WDI2_OVER_GSI()) + return ipa3_disable_gsi_wdi_pipe(clnt_hdl); + + result = ipa3_uc_state_check(); + if (result) + return result; + + IPADBG("ep=%d\n", clnt_hdl); + + ep = &ipa3_ctx->ep[clnt_hdl]; + + if (ep->uc_offload_state != (IPA_WDI_CONNECTED | IPA_WDI_ENABLED)) { + IPAERR("WDI channel bad state %d\n", ep->uc_offload_state); + return -EFAULT; + } + IPA_ACTIVE_CLIENTS_INC_EP(ipa3_get_client_mapping(clnt_hdl)); + + result = ipa3_disable_data_path(clnt_hdl); + if (result) { + IPAERR("disable data path failed res=%d clnt=%d.\n", result, + clnt_hdl); + result = -EPERM; + goto uc_timeout; + } + + /** + * To avoid data stall during continuous SAP on/off before + * setting delay to IPA Consumer pipe (Client Producer), + * remove delay and enable holb on IPA Producer pipe + */ + if (IPA_CLIENT_IS_PROD(ep->client)) { + IPADBG("Stopping PROD channel - hdl=%d clnt=%d\n", + clnt_hdl, ep->client); + /* remove delay on wlan-prod pipe*/ + memset(&ep_cfg_ctrl, 0, sizeof(struct ipa_ep_cfg_ctrl)); + ipa_cfg_ep_ctrl(clnt_hdl, &ep_cfg_ctrl); + + cons_hdl = ipa_get_ep_mapping(IPA_CLIENT_WLAN1_CONS); + if (cons_hdl == IPA_EP_NOT_ALLOCATED) { + IPAERR("Client %u is not mapped\n", + IPA_CLIENT_WLAN1_CONS); + goto uc_timeout; + } + if (ipa3_ctx->ep[cons_hdl].valid == 1) { + result = ipa3_disable_data_path(cons_hdl); + if (result) { + IPAERR("disable data path failed\n"); + IPAERR("res=%d clnt=%d\n", + result, cons_hdl); + result = -EPERM; + goto uc_timeout; + } + } + usleep_range(IPA_UC_POLL_SLEEP_USEC * IPA_UC_POLL_SLEEP_USEC, + IPA_UC_POLL_SLEEP_USEC * IPA_UC_POLL_SLEEP_USEC); + + } + + disable.params.ipa_pipe_number = clnt_hdl; + result = ipa3_uc_send_cmd(disable.raw32b, + IPA_CPU_2_HW_CMD_WDI_CH_DISABLE, + IPA_HW_2_CPU_WDI_CMD_STATUS_SUCCESS, + false, 10*HZ); + + if (result) { + result = -EFAULT; + goto uc_timeout; + } + + /* Set the delay after disabling IPA Producer pipe */ + if (IPA_CLIENT_IS_PROD(ep->client)) { + memset(&ep_cfg_ctrl, 0, sizeof(struct ipa_ep_cfg_ctrl)); + ep_cfg_ctrl.ipa_ep_delay = true; + ipa_cfg_ep_ctrl(clnt_hdl, &ep_cfg_ctrl); + } + ep->uc_offload_state &= ~IPA_WDI_ENABLED; + IPADBG("client (ep: %d) disabled\n", clnt_hdl); + + +uc_timeout: + IPA_ACTIVE_CLIENTS_DEC_EP(ipa3_get_client_mapping(clnt_hdl)); + return result; +} +EXPORT_SYMBOL(ipa_disable_wdi_pipe); + +int ipa3_resume_gsi_wdi_pipe(u32 clnt_hdl) +{ + int result = 0; + struct ipa3_ep_context *ep; + struct ipa_ep_cfg_ctrl ep_cfg_ctrl; + struct gsi_chan_info chan_info; + union __packed gsi_channel_scratch gsi_scratch; + struct IpaHwOffloadStatsAllocCmdData_t *pcmd_t = NULL; + u32 holb_max_cnt = ipa3_ctx->uc_ctx.holb_monitor.max_cnt_wlan; + int res = 0; + + IPADBG("ep=%d\n", clnt_hdl); + ep = &ipa3_ctx->ep[clnt_hdl]; + + if (ep->gsi_offload_state != (IPA_WDI_CONNECTED | IPA_WDI_ENABLED)) { + IPAERR("WDI channel bad state %d\n", ep->gsi_offload_state); + return -EFAULT; + } + IPA_ACTIVE_CLIENTS_INC_EP(ipa3_get_client_mapping(clnt_hdl)); + + memset(&ep_cfg_ctrl, 0, sizeof(struct ipa_ep_cfg_ctrl)); + result = ipa_cfg_ep_ctrl(clnt_hdl, &ep_cfg_ctrl); + if (result) + IPAERR("client (ep: %d) fail un-susp/delay result=%d\n", + clnt_hdl, result); + else + IPADBG("client (ep: %d) un-susp/delay\n", clnt_hdl); + + result = gsi_start_channel(ep->gsi_chan_hdl); + if (result != GSI_STATUS_SUCCESS) { + IPAERR("gsi_start_channel failed %d\n", result); + ipa_assert(); + } + if (IPA_CLIENT_IS_HOLB_CONS(ep->client)) { + res = ipa3_uc_client_add_holb_monitor(ep->gsi_chan_hdl, + HOLB_MONITOR_MASK, holb_max_cnt, + IPA_EE_AP); + if (res) + IPAERR("Add HOLB monitor failed for gsi ch %d\n", + ep->gsi_chan_hdl); + } + pcmd_t = &ipa3_ctx->gsi_info[IPA_HW_PROTOCOL_WDI]; + /* start uC gsi dbg stats monitor */ + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_5 && + ipa3_ctx->ipa_hw_type != IPA_HW_v4_7 && + ipa3_ctx->ipa_hw_type != IPA_HW_v4_11 && + ipa3_ctx->ipa_hw_type != IPA_HW_v5_2) { + if (IPA_CLIENT_IS_PROD(ep->client)) { + pcmd_t->ch_id_info[0].ch_id + = ep->gsi_chan_hdl; + pcmd_t->ch_id_info[0].dir + = DIR_PRODUCER; + } else { + pcmd_t->ch_id_info[1].ch_id + = ep->gsi_chan_hdl; + pcmd_t->ch_id_info[1].dir + = DIR_CONSUMER; + } + ipa3_uc_debug_stats_alloc( + ipa3_ctx->gsi_info[IPA_HW_PROTOCOL_WDI]); + } + gsi_query_channel_info(ep->gsi_chan_hdl, &chan_info); + gsi_read_channel_scratch(ep->gsi_chan_hdl, &gsi_scratch); + IPADBG("ch=%lu channel base = 0x%llx , event base 0x%llx\n", + ep->gsi_chan_hdl, + ep->gsi_mem_info.chan_ring_base_addr, + ep->gsi_mem_info.evt_ring_base_addr); + IPADBG("RP=0x%llx WP=0x%llx ev_valid=%d ERP=0x%llx EWP=0x%llx\n", + chan_info.rp, chan_info.wp, chan_info.evt_valid, + chan_info.evt_rp, chan_info.evt_wp); + IPADBG("Scratch 0 = %x Scratch 1 = %x Scratch 2 = %x Scratch 3 = %x\n", + gsi_scratch.data.word1, gsi_scratch.data.word2, + gsi_scratch.data.word3, gsi_scratch.data.word4); + + ep->gsi_offload_state |= IPA_WDI_RESUMED; + IPADBG("exit\n"); + return result; +} + +/** + * ipa_resume_wdi_pipe() - WDI client resume + * @clnt_hdl: [in] opaque client handle assigned by IPA to client + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa_resume_wdi_pipe(u32 clnt_hdl) +{ + int result = 0; + struct ipa3_ep_context *ep; + union IpaHwWdiCommonChCmdData_t resume; + struct ipa_ep_cfg_ctrl ep_cfg_ctrl; + + if (clnt_hdl >= ipa3_ctx->ipa_num_pipes || + ipa3_ctx->ep[clnt_hdl].valid == 0) { + IPAERR("bad parm, %d\n", clnt_hdl); + return -EINVAL; + } + + if (IPA_WDI2_OVER_GSI()) + return ipa3_resume_gsi_wdi_pipe(clnt_hdl); + + result = ipa3_uc_state_check(); + if (result) + return result; + + IPADBG("ep=%d\n", clnt_hdl); + + ep = &ipa3_ctx->ep[clnt_hdl]; + + if (ep->uc_offload_state != (IPA_WDI_CONNECTED | IPA_WDI_ENABLED)) { + IPAERR("WDI channel bad state %d\n", ep->uc_offload_state); + return -EFAULT; + } + IPA_ACTIVE_CLIENTS_INC_EP(ipa3_get_client_mapping(clnt_hdl)); + resume.params.ipa_pipe_number = clnt_hdl; + + result = ipa3_uc_send_cmd(resume.raw32b, + IPA_CPU_2_HW_CMD_WDI_CH_RESUME, + IPA_HW_2_CPU_WDI_CMD_STATUS_SUCCESS, + false, 10*HZ); + + if (result) { + result = -EFAULT; + IPA_ACTIVE_CLIENTS_DEC_EP(ipa3_get_client_mapping(clnt_hdl)); + goto uc_timeout; + } + + memset(&ep_cfg_ctrl, 0, sizeof(struct ipa_ep_cfg_ctrl)); + result = ipa_cfg_ep_ctrl(clnt_hdl, &ep_cfg_ctrl); + if (result) + IPAERR("client (ep: %d) fail un-susp/delay result=%d\n", + clnt_hdl, result); + else + IPADBG("client (ep: %d) un-susp/delay\n", clnt_hdl); + + ep->uc_offload_state |= IPA_WDI_RESUMED; + IPADBG("client (ep: %d) resumed\n", clnt_hdl); + +uc_timeout: + return result; +} +EXPORT_SYMBOL(ipa_resume_wdi_pipe); + +int ipa3_suspend_gsi_wdi_pipe(u32 clnt_hdl) +{ + int ipa_ep_idx; + struct ipa3_ep_context *ep; + int res = 0; + u32 source_pipe_bitmask = 0; + u32 source_pipe_reg_idx = 0; + bool disable_force_clear = false; + struct ipahal_ep_cfg_ctrl_scnd ep_ctrl_scnd = { 0 }; + int retry_cnt = 0; + struct gsi_chan_info chan_info; + union __packed gsi_channel_scratch gsi_scratch; + struct IpaHwOffloadStatsAllocCmdData_t *pcmd_t = NULL; + + ipa_ep_idx = ipa_get_ep_mapping(ipa3_get_client_mapping(clnt_hdl)); + if (ipa_ep_idx < 0) { + IPAERR("IPA client mapping failed\n"); + return -EPERM; + } + ep = &ipa3_ctx->ep[ipa_ep_idx]; + + if (ep->gsi_offload_state != (IPA_WDI_CONNECTED | IPA_WDI_ENABLED | + IPA_WDI_RESUMED)) { + IPAERR("WDI channel bad state %d\n", ep->gsi_offload_state); + return -EFAULT; + } + if (ep->valid) { + if (IPA_CLIENT_IS_PROD(ep->client)) { + source_pipe_bitmask = ipahal_get_ep_bit(ipa_ep_idx); + source_pipe_reg_idx = ipahal_get_ep_reg_idx(ipa_ep_idx); + + IPADBG("suspended pipe %d\n", ipa_ep_idx); + res = ipa3_enable_force_clear(clnt_hdl, + false, source_pipe_bitmask, + source_pipe_reg_idx); + if (res) { + /* + * assuming here modem SSR, AP can remove + * the delay in this case + */ + IPAERR("failed to force clear %d\n", res); + IPAERR("remove delay from SCND reg\n"); + if (ipa3_ctx->ipa_endp_delay_wa_v2) { + ipa3_remove_secondary_flow_ctrl( + ep->gsi_chan_hdl); + } else { + ep_ctrl_scnd.endp_delay = false; + ipahal_write_reg_n_fields( + IPA_ENDP_INIT_CTRL_SCND_n, + clnt_hdl, &ep_ctrl_scnd); + } + } else { + disable_force_clear = true; + } + } +retry_gsi_stop: + res = ipa_stop_gsi_channel(ipa_ep_idx); + if (res != 0 && res != -GSI_STATUS_AGAIN && + res != -GSI_STATUS_TIMED_OUT) { + IPAERR("failed to stop channel res = %d\n", res); + goto fail_stop_channel; + } else if (res == -GSI_STATUS_AGAIN) { + IPADBG("GSI stop channel failed retry cnt = %d\n", + retry_cnt); + retry_cnt++; + if (retry_cnt >= GSI_STOP_MAX_RETRY_CNT) + goto fail_stop_channel; + goto retry_gsi_stop; + } else { + IPADBG("GSI channel %ld STOP\n", ep->gsi_chan_hdl); + } + gsi_query_channel_info(ep->gsi_chan_hdl, &chan_info); + gsi_read_channel_scratch(ep->gsi_chan_hdl, &gsi_scratch); + IPADBG("ch=%lu channel base = 0x%llx , event base 0x%llx\n", + ep->gsi_chan_hdl, + ep->gsi_mem_info.chan_ring_base_addr, + ep->gsi_mem_info.evt_ring_base_addr); + IPADBG("RP=0x%llx WP=0x%llx ev_valid=%d ERP=0x%llx", + chan_info.rp, chan_info.wp, + chan_info.evt_valid, chan_info.evt_rp); + IPADBG("EWP=0x%llx\n", chan_info.evt_wp); + IPADBG("Scratch 0 = %x Scratch 1 = %x Scratch 2 = %x", + gsi_scratch.data.word1, gsi_scratch.data.word2, + gsi_scratch.data.word3); + IPADBG("Scratch 3 = %x\n", gsi_scratch.data.word4); + } + pcmd_t = &ipa3_ctx->gsi_info[IPA_HW_PROTOCOL_WDI]; + /* stop uC gsi dbg stats monitor */ + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_5 && + ipa3_ctx->ipa_hw_type != IPA_HW_v4_7 && + ipa3_ctx->ipa_hw_type != IPA_HW_v4_11 && + ipa3_ctx->ipa_hw_type != IPA_HW_v5_2) { + if (IPA_CLIENT_IS_PROD(ep->client)) { + pcmd_t->ch_id_info[0].ch_id + = 0xff; + pcmd_t->ch_id_info[0].dir + = DIR_PRODUCER; + } else { + pcmd_t->ch_id_info[1].ch_id + = 0xff; + pcmd_t->ch_id_info[1].dir + = DIR_CONSUMER; + } + ipa3_uc_debug_stats_alloc( + ipa3_ctx->gsi_info[IPA_HW_PROTOCOL_WDI]); + } + if (disable_force_clear) + ipa3_disable_force_clear(clnt_hdl); + IPA_ACTIVE_CLIENTS_DEC_EP(ipa3_get_client_mapping(clnt_hdl)); + ep->gsi_offload_state &= ~IPA_WDI_RESUMED; + return res; +fail_stop_channel: + ipa_assert(); + return res; +} + +/** + * ipa_suspend_wdi_pipe() - WDI client suspend + * @clnt_hdl: [in] opaque client handle assigned by IPA to client + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa_suspend_wdi_pipe(u32 clnt_hdl) +{ + int result = 0; + struct ipa3_ep_context *ep; + union IpaHwWdiCommonChCmdData_t suspend; + struct ipa_ep_cfg_ctrl ep_cfg_ctrl; + u32 source_pipe_bitmask = 0; + u32 source_pipe_reg_idx = 0; + bool disable_force_clear = false; + struct ipahal_ep_cfg_ctrl_scnd ep_ctrl_scnd = { 0 }; + + if (clnt_hdl >= ipa3_ctx->ipa_num_pipes || + ipa3_ctx->ep[clnt_hdl].valid == 0) { + IPAERR("bad parm, %d\n", clnt_hdl); + return -EINVAL; + } + + if (IPA_WDI2_OVER_GSI()) + return ipa3_suspend_gsi_wdi_pipe(clnt_hdl); + + result = ipa3_uc_state_check(); + if (result) + return result; + + IPADBG("ep=%d\n", clnt_hdl); + + ep = &ipa3_ctx->ep[clnt_hdl]; + + if (ep->uc_offload_state != (IPA_WDI_CONNECTED | IPA_WDI_ENABLED | + IPA_WDI_RESUMED)) { + IPAERR("WDI channel bad state %d\n", ep->uc_offload_state); + return -EFAULT; + } + + suspend.params.ipa_pipe_number = clnt_hdl; + + if (IPA_CLIENT_IS_PROD(ep->client)) { + /* + * For WDI 2.0 need to ensure pipe will be empty before suspend + * as IPA uC will fail to suspend the pipe otherwise. + */ + if (ipa3_ctx->ipa_wdi2) { + source_pipe_bitmask = ipahal_get_ep_bit(clnt_hdl); + source_pipe_reg_idx = ipahal_get_ep_reg_idx(clnt_hdl); + result = ipa3_enable_force_clear(clnt_hdl, + false, source_pipe_bitmask,source_pipe_reg_idx); + if (result) { + /* + * assuming here modem SSR, AP can remove + * the delay in this case + */ + IPAERR("failed to force clear %d\n", result); + IPAERR("remove delay from SCND reg\n"); + if (ipa3_ctx->ipa_endp_delay_wa_v2) { + ipa3_remove_secondary_flow_ctrl( + ep->gsi_chan_hdl); + } else { + ep_ctrl_scnd.endp_delay = false; + ipahal_write_reg_n_fields( + IPA_ENDP_INIT_CTRL_SCND_n, clnt_hdl, + &ep_ctrl_scnd); + } + } else { + disable_force_clear = true; + } + } + + IPADBG("Post suspend event first for IPA Producer\n"); + IPADBG("Client: %d clnt_hdl: %d\n", ep->client, clnt_hdl); + result = ipa3_uc_send_cmd(suspend.raw32b, + IPA_CPU_2_HW_CMD_WDI_CH_SUSPEND, + IPA_HW_2_CPU_WDI_CMD_STATUS_SUCCESS, + false, 10*HZ); + + if (result) { + result = -EFAULT; + goto uc_timeout; + } + } + + memset(&ep_cfg_ctrl, 0, sizeof(struct ipa_ep_cfg_ctrl)); + if (IPA_CLIENT_IS_CONS(ep->client)) { + if (ipa3_ctx->ipa_hw_type < IPA_HW_v4_0) { + ep_cfg_ctrl.ipa_ep_suspend = true; + result = ipa_cfg_ep_ctrl(clnt_hdl, &ep_cfg_ctrl); + if (result) + IPAERR("(ep: %d) failed to suspend result=%d\n", + clnt_hdl, result); + else + IPADBG("(ep: %d) suspended\n", clnt_hdl); + } + } else { + ep_cfg_ctrl.ipa_ep_delay = true; + result = ipa_cfg_ep_ctrl(clnt_hdl, &ep_cfg_ctrl); + if (result) + IPAERR("client (ep: %d) failed to delay result=%d\n", + clnt_hdl, result); + else + IPADBG("client (ep: %d) delayed\n", clnt_hdl); + } + + if (IPA_CLIENT_IS_CONS(ep->client)) { + result = ipa3_uc_send_cmd(suspend.raw32b, + IPA_CPU_2_HW_CMD_WDI_CH_SUSPEND, + IPA_HW_2_CPU_WDI_CMD_STATUS_SUCCESS, + false, 10*HZ); + + if (result) { + result = -EFAULT; + goto uc_timeout; + } + } + + if (disable_force_clear) + ipa3_disable_force_clear(clnt_hdl); + + ipa3_ctx->tag_process_before_gating = true; + IPA_ACTIVE_CLIENTS_DEC_EP(ipa3_get_client_mapping(clnt_hdl)); + ep->uc_offload_state &= ~IPA_WDI_RESUMED; + IPADBG("client (ep: %d) suspended\n", clnt_hdl); + +uc_timeout: + return result; +} +EXPORT_SYMBOL(ipa_suspend_wdi_pipe); + +/** + * ipa_broadcast_wdi_quota_reach_ind() - quota reach + * @uint32_t fid: [in] input netdev ID + * @uint64_t num_bytes: [in] used bytes + * + * Returns: 0 on success, negative on failure + */ +int ipa_broadcast_wdi_quota_reach_ind(uint32_t fid, + uint64_t num_bytes) +{ + IPAERR_RL("Quota reached indication on fid(%d) Mbytes(%lu)\n", + fid, (unsigned long)num_bytes); + ipa3_broadcast_quota_reach_ind(0, IPA_UPSTEAM_WLAN, false); + return 0; +} +EXPORT_SYMBOL(ipa_broadcast_wdi_quota_reach_ind); + +int ipa3_write_qmapid_gsi_wdi_pipe(u32 clnt_hdl, u8 qmap_id) +{ + int result = 0; + struct ipa3_ep_context *ep; + union __packed gsi_wdi_channel_scratch3_reg gsi_scratch3; + union __packed gsi_wdi2_channel_scratch2_reg gsi_scratch2; + + ep = &ipa3_ctx->ep[clnt_hdl]; + IPA_ACTIVE_CLIENTS_INC_EP(ipa3_get_client_mapping(clnt_hdl)); + + if (ipa3_ctx->ipa_hw_type < IPA_HW_v4_7) { + memset(&gsi_scratch3, 0, sizeof(gsi_scratch3)); + gsi_scratch3.wdi.qmap_id = qmap_id; + gsi_scratch3.wdi.endp_metadatareg_offset = + ipahal_get_reg_mn_ofst( + IPA_ENDP_INIT_HDR_METADATA_n, 0, clnt_hdl)/4; + result = gsi_write_channel_scratch3_reg(ep->gsi_chan_hdl, + gsi_scratch3); + } else { + memset(&gsi_scratch2, 0, sizeof(gsi_scratch2)); + gsi_scratch2.wdi.qmap_id = qmap_id; + gsi_scratch2.wdi.endp_metadatareg_offset = + ipahal_get_reg_mn_ofst( + IPA_ENDP_INIT_HDR_METADATA_n, 0, clnt_hdl)/4; + result = gsi_write_channel_scratch2_reg(ep->gsi_chan_hdl, + gsi_scratch2); + } + if (result != GSI_STATUS_SUCCESS) { + IPAERR("gsi_write_channel_scratch failed %d\n", + result); + goto fail_write_channel_scratch; + } + + IPADBG("client (ep: %d) qmap_id %d updated\n", clnt_hdl, qmap_id); + IPA_ACTIVE_CLIENTS_DEC_EP(ipa3_get_client_mapping(clnt_hdl)); + return 0; +fail_write_channel_scratch: + ipa_assert(); + return result; +} +int ipa3_write_qmapid_wdi_pipe(u32 clnt_hdl, u8 qmap_id) +{ + int result = 0; + struct ipa3_ep_context *ep; + union IpaHwWdiRxExtCfgCmdData_t qmap; + + if (clnt_hdl >= ipa3_ctx->ipa_num_pipes || + ipa3_ctx->ep[clnt_hdl].valid == 0) { + IPAERR_RL("bad parm, %d\n", clnt_hdl); + return -EINVAL; + } + if (ipa3_ctx->ipa_wdi2_over_gsi) + return ipa3_write_qmapid_gsi_wdi_pipe(clnt_hdl, qmap_id); + + result = ipa3_uc_state_check(); + if (result) + return result; + + IPADBG("ep=%d\n", clnt_hdl); + + ep = &ipa3_ctx->ep[clnt_hdl]; + + if (!(ep->uc_offload_state & IPA_WDI_CONNECTED)) { + IPAERR_RL("WDI channel bad state %d\n", ep->uc_offload_state); + return -EFAULT; + } + IPA_ACTIVE_CLIENTS_INC_EP(ipa3_get_client_mapping(clnt_hdl)); + qmap.params.ipa_pipe_number = clnt_hdl; + qmap.params.qmap_id = qmap_id; + + result = ipa3_uc_send_cmd(qmap.raw32b, + IPA_CPU_2_HW_CMD_WDI_RX_EXT_CFG, + IPA_HW_2_CPU_WDI_CMD_STATUS_SUCCESS, + false, 10*HZ); + + if (result) { + result = -EFAULT; + goto uc_timeout; + } + + IPADBG("client (ep: %d) qmap_id %d updated\n", clnt_hdl, qmap_id); + +uc_timeout: + IPA_ACTIVE_CLIENTS_DEC_EP(ipa3_get_client_mapping(clnt_hdl)); + return result; +} + +/** + * ipa3_uc_reg_rdyCB() - To register uC + * ready CB if uC not ready + * @inout: [in/out] input/output parameters + * from/to client + * + * Returns: 0 on success, negative on failure + * + */ +int ipa3_uc_reg_rdyCB( + struct ipa_wdi_uc_ready_params *inout) +{ + int result = 0; + + if (inout == NULL) { + IPAERR("bad parm. inout=%pK ", inout); + return -EINVAL; + } + + result = ipa3_uc_state_check(); + if (result) { + inout->is_uC_ready = false; + ipa3_ctx->uc_wdi_ctx.uc_ready_cb = inout->notify; + ipa3_ctx->uc_wdi_ctx.priv = inout->priv; + } else { + inout->is_uC_ready = true; + } + + return 0; +} +EXPORT_SYMBOL(ipa3_uc_reg_rdyCB); + +/** + * ipa3_uc_dereg_rdyCB() - To de-register uC ready CB + * + * Returns: 0 on success, negative on failure + * + */ +int ipa3_uc_dereg_rdyCB(void) +{ + ipa3_ctx->uc_wdi_ctx.uc_ready_cb = NULL; + ipa3_ctx->uc_wdi_ctx.priv = NULL; + + return 0; +} + + +/** + * ipa_uc_wdi_get_dbpa() - To retrieve + * doorbell physical address of wlan pipes + * @param: [in/out] input/output parameters + * from/to client + * + * Returns: 0 on success, negative on failure + * + */ +int ipa_uc_wdi_get_dbpa( + struct ipa_wdi_db_params *param) +{ + if (param == NULL || param->client >= IPA_CLIENT_MAX) { + IPAERR("bad parm. param=%pK ", param); + if (param) + IPAERR("client = %d\n", param->client); + return -EINVAL; + } + + if (IPA_CLIENT_IS_CONS(param->client)) { + param->uc_door_bell_pa = ipa3_ctx->ipa_wrapper_base + + ipahal_get_reg_base() + + ipahal_get_reg_mn_ofst(IPA_UC_MAILBOX_m_n, + IPA_HW_WDI_TX_MBOX_START_INDEX/32, + IPA_HW_WDI_TX_MBOX_START_INDEX % 32); + } else { + param->uc_door_bell_pa = ipa3_ctx->ipa_wrapper_base + + ipahal_get_reg_base() + + ipahal_get_reg_mn_ofst(IPA_UC_MAILBOX_m_n, + IPA_HW_WDI_RX_MBOX_START_INDEX/32, + IPA_HW_WDI_RX_MBOX_START_INDEX % 32); + } + + return 0; +} +EXPORT_SYMBOL(ipa_uc_wdi_get_dbpa); + +static void ipa3_uc_wdi_loaded_handler(void) +{ + if (!ipa3_ctx) { + IPAERR("IPA ctx is null\n"); + return; + } + + if (ipa3_ctx->uc_wdi_ctx.uc_ready_cb) { + ipa3_ctx->uc_wdi_ctx.uc_ready_cb( + ipa3_ctx->uc_wdi_ctx.priv); + + ipa3_ctx->uc_wdi_ctx.uc_ready_cb = + NULL; + ipa3_ctx->uc_wdi_ctx.priv = NULL; + } +} + +int ipa3_create_wdi_mapping(u32 num_buffers, struct ipa_wdi_buffer_info *info) +{ + struct ipa_smmu_cb_ctx *cb = ipa3_get_smmu_ctx(IPA_SMMU_CB_WLAN); + int i; + int ret = 0; + int prot = IOMMU_READ | IOMMU_WRITE; + + if (!info) { + IPAERR_RL("info = %pK\n", info); + return -EINVAL; + } + + if (!cb->valid) { + IPAERR_RL("No SMMU CB setup\n"); + return -EINVAL; + } + + if (ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_WLAN]) { + IPAERR_RL("IPA SMMU not enabled\n"); + return -EINVAL; + } + + for (i = 0; i < num_buffers; i++) { + IPADBG_LOW("i=%d pa=0x%pa iova=0x%lx sz=0x%zx\n", i, + &info[i].pa, info[i].iova, info[i].size); + info[i].result = ipa3_iommu_map(cb->iommu_domain, + rounddown(info[i].iova, PAGE_SIZE), + rounddown(info[i].pa, PAGE_SIZE), + roundup(info[i].size + info[i].pa - + rounddown(info[i].pa, PAGE_SIZE), PAGE_SIZE), + prot); + } + + return ret; +} +EXPORT_SYMBOL(ipa3_create_wdi_mapping); + +int ipa3_release_wdi_mapping(u32 num_buffers, struct ipa_wdi_buffer_info *info) +{ + struct ipa_smmu_cb_ctx *cb = ipa3_get_smmu_ctx(IPA_SMMU_CB_WLAN); + int i; + int ret = 0; + + if (!info) { + IPAERR("info = %pK\n", info); + return -EINVAL; + } + + if (!cb->valid) { + IPAERR("No SMMU CB setup\n"); + return -EINVAL; + } + + for (i = 0; i < num_buffers; i++) { + IPADBG_LOW("i=%d pa=0x%pa iova=0x%lx sz=0x%zx\n", i, + &info[i].pa, info[i].iova, info[i].size); + info[i].result = iommu_unmap(cb->iommu_domain, + rounddown(info[i].iova, PAGE_SIZE), + roundup(info[i].size + info[i].pa - + rounddown(info[i].pa, PAGE_SIZE), PAGE_SIZE)); + } + + return ret; +} +EXPORT_SYMBOL(ipa3_release_wdi_mapping); + +static void ipa_wdi_pm_wrapper_cb(void *p, enum ipa_pm_cb_event event) +{ + IPADBG("received pm event %d\n", event); +} + +int ipa_pm_wrapper_wdi_set_perf_profile_internal(struct ipa_wdi_perf_profile *profile) +{ + int res = 0; + + if (profile == NULL) { + IPAERR("Invalid input\n"); + return -EINVAL; + } + + res = ipa_pm_set_throughput(ipa_pm_wdi_ctx.ipa_wrapper_pm_hdl, + profile->max_supported_bw_mbps); + if (res) { + IPAERR("fail to set pm throughput\n"); + return -EFAULT; + } + + return 0; +} +EXPORT_SYMBOL(ipa_pm_wrapper_wdi_set_perf_profile_internal); + +int ipa_pm_wrapper_connect_wdi_pipe(struct ipa_wdi_in_params *in, + struct ipa_wdi_out_params *out) +{ + int ret = 0; + struct ipa_pm_register_params pm_params; + + if (!(in && out)) { + IPAERR("empty parameters. in=%pK out=%pK\n", in, out); + return -EINVAL; + } + if (ipa_pm_wdi_ctx.curr_pm_state != IPA_PM_WDI_PM_DEREGISTERED && + ipa_pm_wdi_ctx.curr_pm_state != IPA_PM_WDI_PM_REGISTERED) { + IPAERR("Unexpected current ipa pm state\n"); + return -EINVAL; + } + + if (ipa_pm_wdi_ctx.curr_pm_state != IPA_PM_WDI_PM_REGISTERED) { + memset(&pm_params, 0, sizeof(pm_params)); + pm_params.name = "wdi"; + pm_params.callback = ipa_wdi_pm_wrapper_cb; + pm_params.user_data = NULL; + pm_params.group = IPA_PM_GROUP_DEFAULT; + if (ipa_pm_register(&pm_params, &ipa_pm_wdi_ctx.ipa_wrapper_pm_hdl)) { + IPAERR("fail to register ipa pm\n"); + ret = -EFAULT; + return ret; + } + ipa_pm_wdi_ctx.curr_pm_state = IPA_PM_WDI_PM_REGISTERED; + } + + if (ipa_connect_wdi_pipe(in,out)) { + IPAERR("fail to setup pipe\n"); + ret = -EFAULT; + return ret; + } + + return ret; +} +EXPORT_SYMBOL(ipa_pm_wrapper_connect_wdi_pipe); + +int ipa_pm_wrapper_disconnect_wdi_pipe(u32 clnt_hdl) +{ + int ret = 0; + if (ipa_pm_wdi_ctx.curr_pm_state == IPA_PM_WDI_PM_DEACTIVATE_IN_PROC || + ipa_pm_wdi_ctx.curr_pm_state == IPA_PM_WDI_PM_ACTIVATE) { + IPAERR("Unexpected current ipa pm state\n"); + return -EFAULT; + } + if (ipa_disconnect_wdi_pipe(clnt_hdl)) { + IPAERR("fail to tear down pipe\n"); + return -EFAULT; + } + + if (ipa_pm_wdi_ctx.curr_pm_state != IPA_PM_WDI_PM_DEREGISTER_IN_PROC) { + ipa_pm_wdi_ctx.curr_pm_state = IPA_PM_WDI_PM_DEREGISTER_IN_PROC; + } + else { + if (ipa_pm_deregister(ipa_pm_wdi_ctx.ipa_wrapper_pm_hdl)) { + IPAERR("fail to deregister ipa pm\n"); + return -EFAULT; + } + ipa_pm_wdi_ctx.curr_pm_state = IPA_PM_WDI_PM_DEREGISTERED; + } + + return ret; +} +EXPORT_SYMBOL(ipa_pm_wrapper_disconnect_wdi_pipe); + +int ipa_pm_wrapper_enable_wdi_pipe(u32 clnt_hdl) +{ + int ret = 0; + if (ipa_pm_wdi_ctx.curr_pm_state == IPA_PM_WDI_PM_DEREGISTER_IN_PROC || + ipa_pm_wdi_ctx.curr_pm_state == IPA_PM_WDI_PM_DEREGISTERED || + ipa_pm_wdi_ctx.curr_pm_state == IPA_PM_WDI_PM_DEACTIVATE_IN_PROC) { + IPAERR("Unexpected current ipa pm state\n"); + return -EFAULT; + } + + if (ipa_pm_wdi_ctx.curr_pm_state != IPA_PM_WDI_PM_ACTIVATE) { + if (ipa_pm_activate_sync(ipa_pm_wdi_ctx.ipa_wrapper_pm_hdl)) { + IPAERR("fail to activate ipa pm\n"); + return -EFAULT; + } + ipa_pm_wdi_ctx.curr_pm_state = IPA_PM_WDI_PM_ACTIVATE; + } + + if (ipa_enable_wdi_pipe(clnt_hdl)) { + IPAERR("fail to enable wdi pipe\n"); + return -EFAULT; + } + return ret; +} +EXPORT_SYMBOL(ipa_pm_wrapper_enable_wdi_pipe); + +int ipa_pm_wrapper_disable_pipe(u32 clnt_hdl) +{ + int ret = 0; + if (ipa_pm_wdi_ctx.curr_pm_state == IPA_PM_WDI_PM_REGISTERED || + ipa_pm_wdi_ctx.curr_pm_state == IPA_PM_WDI_PM_DEREGISTER_IN_PROC || + ipa_pm_wdi_ctx.curr_pm_state == IPA_PM_WDI_PM_DEREGISTERED) { + IPAERR("Unexpected current ipa pm state\n"); + return -EFAULT; + } + + if (ipa_disable_wdi_pipe(clnt_hdl)) { + IPAERR("fail to disable wdi pipe\n"); + return -EFAULT; + } + + if (ipa_pm_wdi_ctx.curr_pm_state != IPA_PM_WDI_PM_DEACTIVATE_IN_PROC) { + ipa_pm_wdi_ctx.curr_pm_state = IPA_PM_WDI_PM_DEACTIVATE_IN_PROC; + } + else { + if(ipa_pm_deactivate_sync(ipa_pm_wdi_ctx.ipa_wrapper_pm_hdl)) { + IPAERR("fail to deactivate ipa pm\n"); + return -EFAULT; + } + ipa_pm_wdi_ctx.curr_pm_state = IPA_PM_WDI_PM_DEACTIVATE; + } + return ret; +} +EXPORT_SYMBOL(ipa_pm_wrapper_disable_pipe); diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c new file mode 100644 index 0000000000..5f8bef7c7c --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c @@ -0,0 +1,14569 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include /* gen_pool_alloc() */ +#include +#include +#include +#include +#include +#include "ipa_i.h" +#include "ipahal.h" +#include "ipahal_nat.h" +#include "ipahal_fltrt.h" +#include "ipahal_hw_stats.h" +#include "ipa_rm_i.h" +#include "gsi.h" + +/* + * The following for adding code (ie. for EMULATION) not found on x86. + */ +#if defined(CONFIG_IPA_EMULATION) +# include "ipa_emulation_stubs.h" +#endif + +#define IPA_V3_0_CLK_RATE_SVS2 (37.5 * 1000 * 1000UL) +#define IPA_V3_0_CLK_RATE_SVS (75 * 1000 * 1000UL) +#define IPA_V3_0_CLK_RATE_NOMINAL (150 * 1000 * 1000UL) +#define IPA_V3_0_CLK_RATE_TURBO (200 * 1000 * 1000UL) + +#define IPA_V3_5_CLK_RATE_SVS2 (100 * 1000 * 1000UL) +#define IPA_V3_5_CLK_RATE_SVS (200 * 1000 * 1000UL) +#define IPA_V3_5_CLK_RATE_NOMINAL (400 * 1000 * 1000UL) +#define IPA_V3_5_CLK_RATE_TURBO (42640 * 10 * 1000UL) + +#define IPA_V4_0_CLK_RATE_SVS2 (60 * 1000 * 1000UL) +#define IPA_V4_0_CLK_RATE_SVS (125 * 1000 * 1000UL) +#define IPA_V4_0_CLK_RATE_NOMINAL (220 * 1000 * 1000UL) +#define IPA_V4_0_CLK_RATE_TURBO (250 * 1000 * 1000UL) + +#define IPA_V5_0_CLK_RATE_SVS2 (120 * 1000 * 1000UL) +#define IPA_V5_0_CLK_RATE_SVS (240 * 1000 * 1000UL) +#define IPA_V5_0_CLK_RATE_NOMINAL (500 * 1000 * 1000UL) +#define IPA_V5_0_CLK_RATE_TURBO (600 * 1000 * 1000UL) + +#define IPA_MAX_HOLB_TMR_VAL (4294967296 - 1) + +#define IPA_V3_0_BW_THRESHOLD_TURBO_MBPS (1000) +#define IPA_V3_0_BW_THRESHOLD_NOMINAL_MBPS (600) +#define IPA_V3_0_BW_THRESHOLD_SVS_MBPS (310) + +#define IPA_ENDP_INIT_HDR_METADATA_n_MUX_ID_BMASK 0xFF0000 +#define IPA_ENDP_INIT_HDR_METADATA_n_MUX_ID_SHFT 0x10 + +/* Max pipes + ICs for TAG process */ +#define IPA_TAG_MAX_DESC (IPA3_MAX_NUM_PIPES + 6) + +#define IPA_TAG_SLEEP_MIN_USEC (1000) +#define IPA_TAG_SLEEP_MAX_USEC (2000) +#define IPA_FORCE_CLOSE_TAG_PROCESS_TIMEOUT (10 * HZ) +#define IPA_BCR_REG_VAL_v3_0 (0x00000001) +#define IPA_BCR_REG_VAL_v3_5 (0x0000003B) +#define IPA_BCR_REG_VAL_v4_0 (0x00000039) +#define IPA_BCR_REG_VAL_v4_2 (0x00000000) +#define IPA_AGGR_GRAN_MIN (1) +#define IPA_AGGR_GRAN_MAX (32) +#define IPA_EOT_COAL_GRAN_MIN (1) +#define IPA_EOT_COAL_GRAN_MAX (16) + +#define IPA_FILT_ROUT_HASH_REG_VAL_v4_2 (0x00000000) +#define IPA_DMA_TASK_FOR_GSI_TIMEOUT_MSEC (15) +#define IPA_COAL_CLOSE_FRAME_CMD_TIMEOUT_MSEC (500) + +#define IPA_AGGR_BYTE_LIMIT (\ + IPA_ENDP_INIT_AGGR_N_AGGR_BYTE_LIMIT_BMSK >> \ + IPA_ENDP_INIT_AGGR_N_AGGR_BYTE_LIMIT_SHFT) +#define IPA_AGGR_PKT_LIMIT (\ + IPA_ENDP_INIT_AGGR_n_AGGR_PKT_LIMIT_BMSK >> \ + IPA_ENDP_INIT_AGGR_n_AGGR_PKT_LIMIT_SHFT) + +/* In IPAv3 only endpoints 0-3 can be configured to deaggregation */ +#define IPA_EP_SUPPORTS_DEAGGR(idx) ((idx) >= 0 && (idx) <= 3) + +#define IPA_TAG_TIMER_TIMESTAMP_SHFT (14) /* ~0.8msec */ +#define IPA_NAT_TIMER_TIMESTAMP_SHFT (24) /* ~0.8sec */ + +/* + * Units of time per a specific granularity + * The limitation based on H/W HOLB/AGGR time limit field width + */ +#define IPA_TIMER_SCALED_TIME_LIMIT 31 + +/* HPS, DPS sequencers Types*/ + +/* DMA Only */ +#define IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY 0x00000000 +/* Packet Processing + no decipher + uCP (for Ethernet Bridging) */ +#define IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_UCP 0x00000002 +/* Packet Processing + no decipher + no uCP */ +#define IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_NO_UCP 0x00000006 +/* 2 Packet Processing pass + no decipher + uCP */ +#define IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP 0x00000004 +/* 2 Packet Processing pass + decipher + uCP + * Deprecated since IPA 5.0 + */ +#define IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_DEC_UCP 0x00000015 +/* 2 Packet Processing pass + no decipher + uCP + HPS REP DMA Parser. */ +#define IPA_DPS_HPS_REP_SEQ_TYPE_2PKT_PROC_PASS_NO_DEC_UCP_DMAP 0x00000804 +/* Packet Processing + no decipher + no uCP + HPS REP DMA Parser.*/ +#define IPA_DPS_HPS_REP_SEQ_TYPE_PKT_PROCESS_NO_DEC_NO_UCP_DMAP 0x00000806 +/* COMP/DECOMP */ +#define IPA_DPS_HPS_SEQ_TYPE_DMA_COMP_DECOMP 0x00000020 +/* 2 Packet Processing + no decipher + 2 uCP */ +#define IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_2ND_UCP 0x0000000a +/* 3 Packet Processing + no decipher + 2 uCP */ +#define IPA_DPS_HPS_SEQ_TYPE_3RD_PKT_PROCESS_PASS_NO_DEC_2ND_UCP 0x0000000c +/* 2 Packet Processing + no decipher + 2 uCP + HPS REP DMA Parser */ +#define IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_2ND_UCP_DMAP 0x0000080a +/* 3 Packet Processing + no decipher + 2 uCP + HPS REP DMA Parser */ +#define IPA_DPS_HPS_SEQ_TYPE_3RD_PKT_PROCESS_PASS_NO_DEC_2ND_UCP_DMAP 0x0000080c +/* Invalid sequencer type */ +#define IPA_DPS_HPS_SEQ_TYPE_INVALID 0xFFFFFFFF + +#define IPA_DPS_HPS_SEQ_TYPE_IS_DMA(seq_type) \ + (seq_type == IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY || \ + seq_type == IPA_DPS_HPS_SEQ_TYPE_DMA_COMP_DECOMP) + + +/* Resource Group index*/ +#define IPA_v3_0_GROUP_UL (0) +#define IPA_v3_0_GROUP_DL (1) +#define IPA_v3_0_GROUP_DPL IPA_v3_0_GROUP_DL +#define IPA_v3_0_GROUP_DIAG (2) +#define IPA_v3_0_GROUP_DMA (3) +#define IPA_v3_0_GROUP_IMM_CMD IPA_v3_0_GROUP_UL +#define IPA_v3_0_GROUP_Q6ZIP (4) +#define IPA_v3_0_GROUP_Q6ZIP_GENERAL IPA_v3_0_GROUP_Q6ZIP +#define IPA_v3_0_GROUP_UC_RX_Q (5) +#define IPA_v3_0_GROUP_Q6ZIP_ENGINE IPA_v3_0_GROUP_UC_RX_Q +#define IPA_v3_0_GROUP_MAX (6) + +#define IPA_v3_5_GROUP_LWA_DL (0) /* currently not used */ +#define IPA_v3_5_MHI_GROUP_PCIE IPA_v3_5_GROUP_LWA_DL +#define IPA_v3_5_GROUP_UL_DL (1) +#define IPA_v3_5_MHI_GROUP_DDR IPA_v3_5_GROUP_UL_DL +#define IPA_v3_5_MHI_GROUP_DMA (2) +#define IPA_v3_5_GROUP_UC_RX_Q (3) /* currently not used */ +#define IPA_v3_5_SRC_GROUP_MAX (4) +#define IPA_v3_5_DST_GROUP_MAX (3) + +#define IPA_v4_0_GROUP_LWA_DL (0) +#define IPA_v4_0_MHI_GROUP_PCIE (0) +#define IPA_v4_0_ETHERNET (0) +#define IPA_v4_0_GROUP_UL_DL (1) +#define IPA_v4_0_MHI_GROUP_DDR (1) +#define IPA_v4_0_MHI_GROUP_DMA (2) +#define IPA_v4_0_GROUP_UC_RX_Q (3) +#define IPA_v4_0_SRC_GROUP_MAX (4) +#define IPA_v4_0_DST_GROUP_MAX (4) + +#define IPA_v4_2_GROUP_UL_DL (0) +#define IPA_v4_2_SRC_GROUP_MAX (1) +#define IPA_v4_2_DST_GROUP_MAX (1) + +#define IPA_v4_5_MHI_GROUP_PCIE (0) +#define IPA_v4_5_GROUP_UL_DL (1) +#define IPA_v4_5_MHI_GROUP_DDR (1) +#define IPA_v4_5_MHI_GROUP_DMA (2) +#define IPA_v4_5_GROUP_CV2X (2) +#define IPA_v4_5_MHI_GROUP_QDSS (3) +#define IPA_v4_5_GROUP_UC_RX_Q (4) +#define IPA_v4_5_SRC_GROUP_MAX (5) +#define IPA_v4_5_DST_GROUP_MAX (5) + +#define IPA_v4_7_GROUP_UL_DL (0) +#define IPA_v4_7_SRC_GROUP_MAX (1) +#define IPA_v4_7_DST_GROUP_MAX (1) + +#define IPA_v4_9_GROUP_UL_DL (0) +#define IPA_v4_9_GROUP_DMA (1) +#define IPA_v4_9_GROUP_UC_RX (2) +#define IPA_v4_9_GROUP_DRB_IP (3) +#define IPA_v4_9_SRC_GROUP_MAX (3) +#define IPA_v4_9_DST_GROUP_MAX (4) + +#define IPA_v4_11_GROUP_UL_DL (0) +#define IPA_v4_11_GROUP_NOT_USE (1) +#define IPA_v4_11_GROUP_DRB_IP (2) +#define IPA_v4_11_SRC_GROUP_MAX (3) +#define IPA_v4_11_DST_GROUP_MAX (3) + +#define IPA_v5_0_GROUP_UL (0) +#define IPA_v5_0_GROUP_DL (1) +#define IPA_v5_0_GROUP_DMA (2) +#define IPA_v5_0_GROUP_QDSS (3) +#define IPA_v5_0_GROUP_URLLC (4) +#define IPA_v5_0_GROUP_CV2X (4) +#define IPA_v5_0_GROUP_UC (5) +#define IPA_v5_0_GROUP_DRB_IP (6) +#define IPA_v5_0_SRC_GROUP_MAX (6) +#define IPA_v5_0_DST_GROUP_MAX (7) +#define IPA_v5_0_GROUP_MAX (7) + +#define IPA_v5_2_GROUP_UL (0) +#define IPA_v5_2_GROUP_DL (1) +#define IPA_v5_2_GROUP_URLLC (2) +#define IPA_v5_2_GROUP_DRB_IP (3) +#define IPA_v5_2_SRC_GROUP_MAX (3) +#define IPA_v5_2_DST_GROUP_MAX (4) + +#define IPA_v5_5_GROUP_UL (0) +#define IPA_v5_5_GROUP_DL (1) +#define IPA_v5_5_GROUP_DMA (2) +#define IPA_v5_5_GROUP_QDSS (3) +#define IPA_v5_5_GROUP_URLLC (4) +#define IPA_v5_5_GROUP_CV2X (4) +#define IPA_v5_5_GROUP_UC (5) +#define IPA_v5_5_GROUP_DRB_IP (6) +#define IPA_v5_5_SRC_GROUP_MAX (6) +#define IPA_v5_5_DST_GROUP_MAX (7) +#define IPA_v5_5_GROUP_MAX (7) + +#define IPA_GROUP_MAX IPA_v5_5_GROUP_MAX + +enum ipa_rsrc_grp_type_src { + IPA_v3_0_RSRC_GRP_TYPE_SRC_PKT_CONTEXTS, + IPA_v3_0_RSRC_GRP_TYPE_SRC_HDR_SECTORS, + IPA_v3_0_RSRC_GRP_TYPE_SRC_HDRI1_BUFFER, + IPA_v3_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_LISTS, + IPA_v3_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_BUFF, + IPA_v3_0_RSRC_GRP_TYPE_SRC_HDRI2_BUFFERS, + IPA_v3_0_RSRC_GRP_TYPE_SRC_HPS_DMARS, + IPA_v3_0_RSRC_GRP_TYPE_SRC_ACK_ENTRIES, + IPA_v3_0_RSRC_GRP_TYPE_SRC_MAX, + + IPA_v3_5_RSRC_GRP_TYPE_SRC_PKT_CONTEXTS = 0, + IPA_v3_5_RSRC_GRP_TYPE_SRC_DESCRIPTOR_LISTS, + IPA_v3_5_RSRC_GRP_TYPE_SRC_DESCRIPTOR_BUFF, + IPA_v3_5_RSRC_GRP_TYPE_SRC_HPS_DMARS, + IPA_v3_5_RSRC_GRP_TYPE_SRC_ACK_ENTRIES, + IPA_v3_5_RSRC_GRP_TYPE_SRC_MAX, + + IPA_v4_0_RSRC_GRP_TYPE_SRC_PKT_CONTEXTS = 0, + IPA_v4_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_LISTS, + IPA_v4_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_BUFF, + IPA_v4_0_RSRC_GRP_TYPE_SRC_HPS_DMARS, + IPA_v4_0_RSRC_GRP_TYPE_SRC_ACK_ENTRIES, + IPA_v4_0_RSRC_GRP_TYPE_SRC_MAX, + + IPA_v5_0_RSRC_GRP_TYPE_SRC_PKT_CONTEXTS = 0, + IPA_v5_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_LISTS, + IPA_v5_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_BUFF, + IPA_v5_0_RSRC_GRP_TYPE_SRC_HPS_DMARS, + IPA_v5_0_RSRC_GRP_TYPE_SRC_ACK_ENTRIES, + IPA_v5_0_RSRC_GRP_TYPE_SRC_MAX +}; + +#define IPA_RSRC_GRP_TYPE_SRC_MAX IPA_v3_0_RSRC_GRP_TYPE_SRC_MAX + +enum ipa_rsrc_grp_type_dst { + IPA_v3_0_RSRC_GRP_TYPE_DST_DATA_SECTORS, + IPA_v3_0_RSRC_GRP_TYPE_DST_DATA_SECTOR_LISTS, + IPA_v3_0_RSRC_GRP_TYPE_DST_DPS_DMARS, + IPA_v3_0_RSRC_GRP_TYPE_DST_MAX, + + IPA_v3_5_RSRC_GRP_TYPE_DST_DATA_SECTORS = 0, + IPA_v3_5_RSRC_GRP_TYPE_DST_DPS_DMARS, + IPA_v3_5_RSRC_GRP_TYPE_DST_MAX, + + IPA_v4_0_RSRC_GRP_TYPE_DST_DATA_SECTORS = 0, + IPA_v4_0_RSRC_GRP_TYPE_DST_DPS_DMARS, + IPA_v4_0_RSRC_GRP_TYPE_DST_MAX, + + IPA_v5_0_RSRC_GRP_TYPE_DST_DATA_SECTORS = 0, + IPA_v5_0_RSRC_GRP_TYPE_DST_DPS_DMARS, + IPA_v5_0_RSRC_GRP_TYPE_DST_ULSO_SEGMENTS, + IPA_v5_0_RSRC_GRP_TYPE_DST_MAX +}; +#define IPA_RSRC_GRP_TYPE_DST_MAX IPA_v3_0_RSRC_GRP_TYPE_DST_MAX + +enum ipa_rsrc_grp_type_rx { + IPA_RSRC_GRP_TYPE_RX_HPS_CMDQ, + IPA_RSRC_GRP_TYPE_RX_MAX +}; + +enum ipa_rsrc_grp_rx_hps_weight_config { + IPA_RSRC_GRP_TYPE_RX_HPS_WEIGHT_CONFIG, + IPA_RSRC_GRP_TYPE_RX_HPS_WEIGHT_MAX +}; + +struct rsrc_min_max { + u32 min; + u32 max; +}; + +struct ipa_rsrc_cfg { + u8 src_grp_index; + bool src_grp_valid; + u8 dst_pipe_index; + bool dst_pipe_valid; + u8 dst_grp_index; + bool dst_grp_valid; + u8 src_grp_2nd_prio_index; + bool src_grp_2nd_prio_valid; +}; + +enum ipa_ver { + IPA_3_0, + IPA_3_5, + IPA_3_5_MHI, + IPA_3_5_1, + IPA_4_0, + IPA_4_0_MHI, + IPA_4_1, + IPA_4_1_APQ, + IPA_4_2, + IPA_4_5, + IPA_4_5_MHI, + IPA_4_5_APQ, + IPA_4_5_AUTO, + IPA_4_5_AUTO_MHI, + IPA_4_7, + IPA_4_9, + IPA_4_11, + IPA_5_0, + IPA_5_0_MHI, + IPA_5_1, + IPA_5_1_APQ, + IPA_5_2, + IPA_5_5, + IPA_5_5_XR, + IPA_VER_MAX, +}; + + +static const struct rsrc_min_max ipa3_rsrc_src_grp_config + [IPA_VER_MAX][IPA_RSRC_GRP_TYPE_SRC_MAX][IPA_GROUP_MAX] = { + [IPA_3_0] = { + /* UL DL DIAG DMA Not Used uC Rx */ + [IPA_v3_0_RSRC_GRP_TYPE_SRC_PKT_CONTEXTS] = { + {3, 255}, {3, 255}, {1, 255}, {1, 255}, {1, 255}, {2, 255} }, + [IPA_v3_0_RSRC_GRP_TYPE_SRC_HDR_SECTORS] = { + {0, 255}, {0, 255}, {0, 255}, {0, 255}, {0, 255}, {0, 255} }, + [IPA_v3_0_RSRC_GRP_TYPE_SRC_HDRI1_BUFFER] = { + {0, 255}, {0, 255}, {0, 255}, {0, 255}, {0, 255}, {0, 255} }, + [IPA_v3_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_LISTS] = { + {14, 14}, {16, 16}, {5, 5}, {5, 5}, {0, 0}, {8, 8} }, + [IPA_v3_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_BUFF] = { + {19, 19}, {26, 26}, {3, 3}, {7, 7}, {0, 0}, {8, 8} }, + [IPA_v3_0_RSRC_GRP_TYPE_SRC_HDRI2_BUFFERS] = { + {0, 255}, {0, 255}, {0, 255}, {0, 255}, {0, 255}, {0, 255} }, + [IPA_v3_0_RSRC_GRP_TYPE_SRC_HPS_DMARS] = { + {0, 255}, {0, 255}, {0, 255}, {0, 255}, {0, 255}, {0, 255} }, + [IPA_v3_0_RSRC_GRP_TYPE_SRC_ACK_ENTRIES] = { + {14, 14}, {16, 16}, {5, 5}, {5, 5}, {0, 0}, {8, 8} }, + }, + [IPA_3_5] = { + /* LWA_DL UL_DL unused UC_RX_Q, other are invalid */ + [IPA_v3_5_RSRC_GRP_TYPE_SRC_PKT_CONTEXTS] = { + {0, 0}, {1, 255}, {0, 0}, {1, 255}, {0, 0}, {0, 0} }, + [IPA_v3_5_RSRC_GRP_TYPE_SRC_DESCRIPTOR_LISTS] = { + {0, 0}, {10, 10}, {0, 0}, {8, 8}, {0, 0}, {0, 0} }, + [IPA_v3_5_RSRC_GRP_TYPE_SRC_DESCRIPTOR_BUFF] = { + {0, 0}, {14, 14}, {0, 0}, {8, 8}, {0, 0}, {0, 0} }, + [IPA_v3_5_RSRC_GRP_TYPE_SRC_HPS_DMARS] = { + {0, 255}, {0, 255}, {0, 255}, {0, 255}, {0, 0}, {0, 0} }, + [IPA_v3_5_RSRC_GRP_TYPE_SRC_ACK_ENTRIES] = { + {0, 0}, {20, 20}, {0, 0}, {14, 14}, {0, 0}, {0, 0} }, + }, + [IPA_3_5_MHI] = { + /* PCIE DDR DMA unused, other are invalid */ + [IPA_v3_5_RSRC_GRP_TYPE_SRC_PKT_CONTEXTS] = { + {4, 4}, {5, 5}, {1, 1}, {0, 0}, {0, 0}, {0, 0} }, + [IPA_v3_5_RSRC_GRP_TYPE_SRC_DESCRIPTOR_LISTS] = { + {10, 10}, {10, 10}, {8, 8}, {0, 0}, {0, 0}, {0, 0} }, + [IPA_v3_5_RSRC_GRP_TYPE_SRC_DESCRIPTOR_BUFF] = { + {12, 12}, {12, 12}, {8, 8}, {0, 0}, {0, 0}, {0, 0} }, + [IPA_v3_5_RSRC_GRP_TYPE_SRC_HPS_DMARS] = { + {0, 255}, {0, 255}, {0, 255}, {0, 255}, {0, 0}, {0, 0} }, + [IPA_v3_5_RSRC_GRP_TYPE_SRC_ACK_ENTRIES] = { + {14, 14}, {14, 14}, {14, 14}, {0, 0}, {0, 0}, {0, 0} }, + }, + [IPA_3_5_1] = { + /* LWA_DL UL_DL unused UC_RX_Q, other are invalid */ + [IPA_v3_5_RSRC_GRP_TYPE_SRC_PKT_CONTEXTS] = { + {1, 255}, {1, 255}, {0, 0}, {1, 255}, {0, 0}, {0, 0} }, + [IPA_v3_5_RSRC_GRP_TYPE_SRC_DESCRIPTOR_LISTS] = { + {10, 10}, {10, 10}, {0, 0}, {8, 8}, {0, 0}, {0, 0} }, + [IPA_v3_5_RSRC_GRP_TYPE_SRC_DESCRIPTOR_BUFF] = { + {12, 12}, {14, 14}, {0, 0}, {8, 8}, {0, 0}, {0, 0} }, + [IPA_v3_5_RSRC_GRP_TYPE_SRC_HPS_DMARS] = { + {0, 255}, {0, 255}, {0, 255}, {0, 255}, {0, 0}, {0, 0} }, + [IPA_v3_5_RSRC_GRP_TYPE_SRC_ACK_ENTRIES] = { + {14, 14}, {20, 20}, {0, 0}, {14, 14}, {0, 0}, {0, 0} }, + }, + [IPA_4_0] = { + /* LWA_DL UL_DL unused UC_RX_Q, other are invalid */ + [IPA_v4_0_RSRC_GRP_TYPE_SRC_PKT_CONTEXTS] = { + {1, 255}, {1, 255}, {0, 0}, {1, 255}, {0, 0}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_LISTS] = { + {10, 10}, {10, 10}, {0, 0}, {8, 8}, {0, 0}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_BUFF] = { + {12, 12}, {14, 14}, {0, 0}, {8, 8}, {0, 0}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_SRC_HPS_DMARS] = { + {0, 255}, {0, 255}, {0, 255}, {0, 255}, {0, 0}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_SRC_ACK_ENTRIES] = { + {14, 14}, {20, 20}, {0, 0}, {14, 14}, {0, 0}, {0, 0} }, + }, + [IPA_4_0_MHI] = { + /* PCIE DDR DMA unused, other are invalid */ + [IPA_v4_0_RSRC_GRP_TYPE_SRC_PKT_CONTEXTS] = { + {4, 4}, {5, 5}, {1, 1}, {0, 0}, {0, 0}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_LISTS] = { + {10, 10}, {10, 10}, {8, 8}, {0, 0}, {0, 0}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_BUFF] = { + {12, 12}, {12, 12}, {8, 8}, {0, 0}, {0, 0}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_SRC_HPS_DMARS] = { + {0, 255}, {0, 255}, {0, 255}, {0, 255}, {0, 0}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_SRC_ACK_ENTRIES] = { + {14, 14}, {14, 14}, {14, 14}, {0, 0}, {0, 0}, {0, 0} }, + }, + [IPA_4_1] = { + /* LWA_DL UL_DL unused UC_RX_Q, other are invalid */ + [IPA_v4_0_RSRC_GRP_TYPE_SRC_PKT_CONTEXTS] = { + {1, 63}, {1, 63}, {0, 0}, {1, 63}, {0, 0}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_LISTS] = { + {10, 10}, {10, 10}, {0, 0}, {8, 8}, {0, 0}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_BUFF] = { + {12, 12}, {14, 14}, {0, 0}, {8, 8}, {0, 0}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_SRC_HPS_DMARS] = { + {0, 63}, {0, 63}, {0, 63}, {0, 63}, {0, 0}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_SRC_ACK_ENTRIES] = { + {14, 14}, {20, 20}, {0, 0}, {14, 14}, {0, 0}, {0, 0} }, + }, + [IPA_4_2] = { + /* UL_DL other are invalid */ + [IPA_v4_0_RSRC_GRP_TYPE_SRC_PKT_CONTEXTS] = { + {3, 63}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_LISTS] = { + {3, 3}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_BUFF] = { + {10, 10}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_SRC_HPS_DMARS] = { + {1, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_SRC_ACK_ENTRIES] = { + {5, 5}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0} }, + }, + [IPA_4_5] = { + /* unused UL_DL unused unused UC_RX_Q N/A */ + [IPA_v4_0_RSRC_GRP_TYPE_SRC_PKT_CONTEXTS] = { + {0, 0}, {1, 11}, {0, 0}, {0, 0}, {1, 63}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_LISTS] = { + {0, 0}, {14, 14}, {0, 0}, {0, 0}, {3, 3}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_BUFF] = { + {0, 0}, {18, 18}, {0, 0}, {0, 0}, {8, 8}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_SRC_HPS_DMARS] = { + {0, 63}, {0, 63}, {0, 63}, {0, 63}, {0, 63}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_SRC_ACK_ENTRIES] = { + {0, 0}, {24, 24}, {0, 0}, {0, 0}, {8, 8}, {0, 0} }, + }, + [IPA_4_5_MHI] = { + /* PCIE DDR DMA QDSS unused N/A */ + [IPA_v4_0_RSRC_GRP_TYPE_SRC_PKT_CONTEXTS] = { + {3, 8}, {4, 11}, {1, 6}, {1, 1}, {0, 0}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_LISTS] = { + {9, 9}, {12, 12}, {2, 2}, {2, 2}, {0, 0}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_BUFF] = { + {9, 9}, {14, 14}, {4, 4}, {4, 4}, {0, 0}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_SRC_HPS_DMARS] = { + {0, 63}, {0, 63}, {0, 63}, {0, 63}, {0, 63}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_SRC_ACK_ENTRIES] = { + {22, 22}, {16, 16}, {6, 6}, {2, 2}, {0, 0}, {0, 0} }, + }, + [IPA_4_5_APQ] = { + /* unused UL_DL unused unused UC_RX_Q N/A */ + [IPA_v4_0_RSRC_GRP_TYPE_SRC_PKT_CONTEXTS] = { + {0, 0}, {1, 11}, {0, 0}, {0, 0}, {1, 63}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_LISTS] = { + {0, 0}, {14, 14}, {0, 0}, {0, 0}, {3, 3}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_BUFF] = { + {0, 0}, {18, 18}, {0, 0}, {0, 0}, {8, 8}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_SRC_HPS_DMARS] = { + {0, 63}, {0, 63}, {0, 63}, {0, 63}, {0, 63}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_SRC_ACK_ENTRIES] = { + {0, 0}, {24, 24}, {0, 0}, {0, 0}, {8, 8}, {0, 0} }, + }, + [IPA_4_5_AUTO] = { + /* unused UL_DL DMA/CV2X unused UC_RX_Q N/A */ + [IPA_v4_0_RSRC_GRP_TYPE_SRC_PKT_CONTEXTS] = { + {0, 0}, {1, 11}, {1, 1}, {0, 0}, {1, 63}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_LISTS] = { + {0, 0}, {14, 14}, {2, 2}, {0, 0}, {3, 3}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_BUFF] = { + {0, 0}, {18, 18}, {4, 4}, {0, 0}, {8, 8}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_SRC_HPS_DMARS] = { + {0, 63}, {0, 63}, {0, 63}, {0, 63}, {0, 63}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_SRC_ACK_ENTRIES] = { + {0, 0}, {24, 24}, {6, 6}, {0, 0}, {8, 8}, {0, 0} }, + }, + [IPA_4_5_AUTO_MHI] = { + /* PCIE DDR DMA/CV2X QDSS unused N/A */ + [IPA_v4_0_RSRC_GRP_TYPE_SRC_PKT_CONTEXTS] = { + {3, 8}, {4, 11}, {1, 6}, {1, 1}, {0, 0}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_LISTS] = { + {9, 9}, {12, 12}, {2, 2}, {2, 2}, {0, 0}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_BUFF] = { + {9, 9}, {14, 14}, {4, 4}, {4, 4}, {0, 0}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_SRC_HPS_DMARS] = { + {0, 63}, {0, 63}, {0, 63}, {0, 63}, {0, 63}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_SRC_ACK_ENTRIES] = { + {22, 22}, {16, 16}, {6, 6}, {2, 2}, {0, 0}, {0, 0} }, + }, + [IPA_4_7] = { + /* UL_DL other are invalid */ + [IPA_v4_0_RSRC_GRP_TYPE_SRC_PKT_CONTEXTS] = { + {8, 8}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_LISTS] = { + {8, 8}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_BUFF] = { + {18, 18}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_SRC_HPS_DMARS] = { + {2, 2}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_SRC_ACK_ENTRIES] = { + {15, 15}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0} }, + }, + [IPA_4_9] = { + /* UL_DL DMA UC_RX_Q unused unused N/A */ + [IPA_v4_0_RSRC_GRP_TYPE_SRC_PKT_CONTEXTS] = { + {1, 12}, {1, 1}, {1, 12}, {0, 0}, {0, 0}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_LISTS] = { + {20, 20}, {2, 2}, {3, 3}, {0, 0}, {0, 0}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_BUFF] = { + {38, 38}, {4, 4}, {8, 8}, {0, 0}, {0, 0}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_SRC_HPS_DMARS] = { + {0, 4}, {0, 4}, {0, 4}, {0, 0}, {0, 0}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_SRC_ACK_ENTRIES] = { + {30, 30}, {8, 8}, {8, 8}, {0, 0}, {0, 0}, {0, 0} }, + }, + [IPA_4_11] = { + /* UL_DL other are invalid */ + [IPA_v4_0_RSRC_GRP_TYPE_SRC_PKT_CONTEXTS] = { + {6, 6}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_LISTS] = { + {8, 8}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_BUFF] = { + {18, 18}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_SRC_HPS_DMARS] = { + {2, 2}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_SRC_ACK_ENTRIES] = { + {15, 15}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0} }, + }, + [IPA_5_0] = { + /* UL DL unused unused URLLC UC_RX_Q N/A */ + [IPA_v5_0_RSRC_GRP_TYPE_SRC_PKT_CONTEXTS] = { + {3, 9}, {4, 10}, {0, 0}, {0, 0}, {1, 63}, {0, 63}, {0, 0}, }, + [IPA_v5_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_LISTS] = { + {9, 9}, {12, 12}, {0, 0}, {0, 0}, {10, 10}, {0, 0}, {0, 0}, }, + [IPA_v5_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_BUFF] = { + {9, 9}, {24, 24}, {0, 0}, {0, 0}, {20, 20}, {0, 0}, {0, 0}, }, + [IPA_v5_0_RSRC_GRP_TYPE_SRC_HPS_DMARS] = { + {0, 63}, {0, 63}, {0, 63}, {0, 63}, {1, 63}, {0, 63}, {0, 0}, }, + [IPA_v5_0_RSRC_GRP_TYPE_SRC_ACK_ENTRIES] = { + {22, 22}, {16, 16}, {0, 0}, {0, 0}, {16, 16}, {0, 0}, {0, 0}, }, + }, + [IPA_5_0_MHI] = { + /* UL DL unused unused URLLC UC_RX_Q N/A */ + [IPA_v5_0_RSRC_GRP_TYPE_SRC_PKT_CONTEXTS] = { + {3, 9}, {4, 10}, {1, 1}, {1, 1}, {1, 63}, {0, 63}, {0, 0}, }, + [IPA_v5_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_LISTS] = { + {9, 9}, {12, 12}, {2, 2}, {2, 2}, {10, 10}, {0, 0}, {0, 0}, }, + [IPA_v5_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_BUFF] = { + {9, 9}, {24, 24}, {4, 4}, {4, 4}, {20, 20}, {0, 0}, {0, 0}, }, + [IPA_v5_0_RSRC_GRP_TYPE_SRC_HPS_DMARS] = { + {0, 63}, {0, 63}, {0, 63}, {0, 63}, {1, 63}, {0, 0}, {0, 0}, }, + [IPA_v5_0_RSRC_GRP_TYPE_SRC_ACK_ENTRIES] = { + {22, 22}, {16, 16}, {6, 6}, {2, 2}, {16, 16}, {0, 0}, {0, 0}, }, + }, + + [IPA_5_1] = { + /* UL DL unused unused URLLC UC_RX_Q N/A */ + [IPA_v5_0_RSRC_GRP_TYPE_SRC_PKT_CONTEXTS] = { + {7, 12}, {0, 0}, {0, 0}, {0, 0}, {1, 63}, {0, 63}, {0, 0}, }, + [IPA_v5_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_LISTS] = { + {21, 21}, {0, 0}, {0, 0}, {0, 0}, {10, 10}, {0, 0}, {0, 0}, }, + [IPA_v5_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_BUFF] = { + {33, 33}, {0, 0}, {0, 0}, {0, 0}, {20, 20}, {0, 0}, {0, 0}, }, + [IPA_v5_0_RSRC_GRP_TYPE_SRC_HPS_DMARS] = { + {0, 63}, {0, 0}, {0, 63}, {0, 63}, {1, 63}, {0, 63}, {0, 0}, }, + [IPA_v5_0_RSRC_GRP_TYPE_SRC_ACK_ENTRIES] = { + {38, 38}, {0, 0}, {0, 0}, {0, 0}, {16, 16}, {0, 0}, {0, 0}, }, + }, + + [IPA_5_1_APQ] = { + /* UL DL unused unused URLLC UC_RX_Q N/A */ + [IPA_v5_0_RSRC_GRP_TYPE_SRC_PKT_CONTEXTS] = { + {3, 9}, {4, 10}, {0, 0}, {0, 0}, {1, 63}, {0, 63}, {0, 0}, }, + [IPA_v5_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_LISTS] = { + {9, 9}, {12, 12}, {0, 0}, {0, 0}, {10, 10}, {0, 0}, {0, 0}, }, + [IPA_v5_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_BUFF] = { + {9, 9}, {24, 24}, {0, 0}, {0, 0}, {20, 20}, {0, 0}, {0, 0}, }, + [IPA_v5_0_RSRC_GRP_TYPE_SRC_HPS_DMARS] = { + {0, 63}, {0, 63}, {0, 63}, {0, 63}, {1, 63}, {0, 63}, {0, 0}, }, + [IPA_v5_0_RSRC_GRP_TYPE_SRC_ACK_ENTRIES] = { + {22, 22}, {16, 16}, {0, 0}, {0, 0}, {16, 16}, {0, 0}, {0, 0}, }, + }, + + [IPA_5_2] = { + /* what does above comment mean. */ + [IPA_v5_0_RSRC_GRP_TYPE_SRC_PKT_CONTEXTS] = { + {1, 7}, {1, 7}, {0, 5}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, }, + [IPA_v5_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_LISTS] = { + {8, 8}, {8, 8}, {8, 8}, {0, 0}, {0, 0}, {0, 0}, {0, 0} }, + [IPA_v5_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_BUFF] = { + {10, 10}, {12, 12}, {12, 12}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, }, + [IPA_v5_0_RSRC_GRP_TYPE_SRC_HPS_DMARS] = { + {0, 63}, {0, 63}, {0, 63}, {0, 0}, {0, 0}, {0, 0}, {0, 0} }, + [IPA_v5_0_RSRC_GRP_TYPE_SRC_ACK_ENTRIES] = { + {15, 15}, {15, 15}, {12, 12}, {0, 0}, {0, 0}, {0, 0}, {0, 0} }, + }, + + [IPA_5_5] = { + /* UL DL unused unused URLLC UC_RX_Q N/A */ + [IPA_v5_0_RSRC_GRP_TYPE_SRC_PKT_CONTEXTS] = { + {3, 9}, {4, 10}, {0, 0}, {0, 0}, {1, 63}, {0, 63}, {0, 0}, }, + [IPA_v5_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_LISTS] = { + {9, 9}, {12, 12}, {0, 0}, {0, 0}, {10, 10}, {0, 0}, {0, 0}, }, + [IPA_v5_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_BUFF] = { + {9, 9}, {24, 24}, {0, 0}, {0, 0}, {20, 20}, {0, 0}, {0, 0}, }, + [IPA_v5_0_RSRC_GRP_TYPE_SRC_HPS_DMARS] = { + {0, 63}, {0, 63}, {0, 63}, {0, 63}, {1, 63}, {0, 63}, {0, 0}, }, + [IPA_v5_0_RSRC_GRP_TYPE_SRC_ACK_ENTRIES] = { + {22, 22}, {16, 16}, {0, 0}, {0, 0}, {16, 16}, {0, 0}, {0, 0}, }, + }, + + [IPA_5_5_XR] = { + /* UL DL DMA QDSS URLLC UC_RX_Q N/A */ + [IPA_v5_0_RSRC_GRP_TYPE_SRC_PKT_CONTEXTS] = { + {3, 9}, {4, 10}, {1, 1}, {1, 1}, {1, 63}, {0, 63}, {0, 0}, }, + [IPA_v5_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_LISTS] = { + {9, 9}, {12, 12}, {2, 2}, {2, 2}, {10, 10}, {0, 0}, {0, 0}, }, + [IPA_v5_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_BUFF] = { + {9, 9}, {24, 24}, {4, 4}, {4, 4}, {20, 20}, {0, 0}, {0, 0}, }, + [IPA_v5_0_RSRC_GRP_TYPE_SRC_HPS_DMARS] = { + {0, 63}, {0, 63}, {0, 63}, {0, 63}, {1, 63}, {0, 63}, {0, 0}, }, + [IPA_v5_0_RSRC_GRP_TYPE_SRC_ACK_ENTRIES] = { + {22, 22}, {16, 16}, {6, 6}, {2, 2}, {16, 16}, {0, 0}, {0, 0}, }, + }, +}; + +static const struct rsrc_min_max ipa3_rsrc_dst_grp_config + [IPA_VER_MAX][IPA_RSRC_GRP_TYPE_DST_MAX][IPA_GROUP_MAX] = { + [IPA_3_0] = { + /* UL DL/DPL DIAG DMA Q6zip_gen Q6zip_eng */ + [IPA_v3_0_RSRC_GRP_TYPE_DST_DATA_SECTORS] = { + {2, 2}, {3, 3}, {0, 0}, {2, 2}, {3, 3}, {3, 3} }, + [IPA_v3_0_RSRC_GRP_TYPE_DST_DATA_SECTOR_LISTS] = { + {0, 255}, {0, 255}, {0, 255}, {0, 255}, {0, 255}, {0, 255} }, + [IPA_v3_0_RSRC_GRP_TYPE_DST_DPS_DMARS] = { + {1, 1}, {1, 1}, {1, 1}, {1, 1}, {1, 1}, {0, 0} }, + }, + [IPA_3_5] = { + /* unused UL/DL/DPL unused N/A N/A N/A */ + [IPA_v3_5_RSRC_GRP_TYPE_DST_DATA_SECTORS] = { + {4, 4}, {4, 4}, {3, 3}, {0, 0}, {0, 0}, {0, 0} }, + [IPA_v3_5_RSRC_GRP_TYPE_DST_DPS_DMARS] = { + {2, 255}, {1, 255}, {1, 2}, {0, 0}, {0, 0}, {0, 0} }, + }, + [IPA_3_5_MHI] = { + /* PCIE DDR DMA N/A N/A N/A */ + [IPA_v3_5_RSRC_GRP_TYPE_DST_DATA_SECTORS] = { + {4, 4}, {4, 4}, {3, 3}, {0, 0}, {0, 0}, {0, 0} }, + [IPA_v3_5_RSRC_GRP_TYPE_DST_DPS_DMARS] = { + {2, 255}, {1, 255}, {1, 2}, {0, 0}, {0, 0}, {0, 0} }, + }, + [IPA_3_5_1] = { + /* LWA_DL UL/DL/DPL unused N/A N/A N/A */ + [IPA_v3_5_RSRC_GRP_TYPE_DST_DATA_SECTORS] = { + {4, 4}, {4, 4}, {3, 3}, {0, 0}, {0, 0}, {0, 0} }, + [IPA_v3_5_RSRC_GRP_TYPE_DST_DPS_DMARS] = { + {2, 255}, {1, 255}, {1, 2}, {0, 0}, {0, 0}, {0, 0} }, + }, + [IPA_4_0] = { + /* LWA_DL UL/DL/DPL uC, other are invalid */ + [IPA_v4_0_RSRC_GRP_TYPE_DST_DATA_SECTORS] = { + {4, 4}, {4, 4}, {3, 3}, {2, 2}, {0, 0}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_DST_DPS_DMARS] = { + {2, 255}, {1, 255}, {1, 2}, {0, 2}, {0, 0}, {0, 0} }, + }, + [IPA_4_0_MHI] = { + /* LWA_DL UL/DL/DPL uC, other are invalid */ + [IPA_v4_0_RSRC_GRP_TYPE_DST_DATA_SECTORS] = { + {4, 4}, {4, 4}, {3, 3}, {2, 2}, {0, 0}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_DST_DPS_DMARS] = { + {2, 255}, {1, 255}, {1, 2}, {0, 2}, {0, 0}, {0, 0} }, + }, + [IPA_4_1] = { + /* LWA_DL UL/DL/DPL uC, other are invalid */ + [IPA_v4_0_RSRC_GRP_TYPE_DST_DATA_SECTORS] = { + {4, 4}, {4, 4}, {3, 3}, {2, 2}, {0, 0}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_DST_DPS_DMARS] = { + {2, 63}, {1, 63}, {1, 2}, {0, 2}, {0, 0}, {0, 0} }, + }, + [IPA_4_2] = { + /* UL/DL/DPL, other are invalid */ + [IPA_v4_0_RSRC_GRP_TYPE_DST_DATA_SECTORS] = { + {3, 3}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_DST_DPS_DMARS] = { + {1, 63}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0} }, + }, + [IPA_4_5] = { + /* unused UL/DL/DPL unused unused uC N/A */ + [IPA_v4_0_RSRC_GRP_TYPE_DST_DATA_SECTORS] = { + {0, 0}, {16, 16}, {2, 2}, {2, 2}, {0, 0}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_DST_DPS_DMARS] = { + {0, 0}, {2, 63}, {1, 2}, {1, 2}, {0, 2}, {0, 0} }, + }, + [IPA_4_5_MHI] = { + /* PCIE/DPL DDR DMA/CV2X QDSS uC N/A */ + [IPA_v4_0_RSRC_GRP_TYPE_DST_DATA_SECTORS] = { + {16, 16}, {5, 5}, {2, 2}, {2, 2}, {0, 0}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_DST_DPS_DMARS] = { + {2, 63}, {1, 63}, {1, 2}, {1, 2}, {0, 2}, {0, 0} }, + }, + [IPA_4_5_APQ] = { + /* unused UL/DL/DPL unused unused uC N/A */ + [IPA_v4_0_RSRC_GRP_TYPE_DST_DATA_SECTORS] = { + {0, 0}, {16, 16}, {2, 2}, {2, 2}, {0, 0}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_DST_DPS_DMARS] = { + {0, 0}, {2, 63}, {1, 2}, {1, 2}, {0, 2}, {0, 0} }, + }, + [IPA_4_5_AUTO] = { + /* unused UL/DL/DPL DMA/CV2X unused uC N/A */ + [IPA_v4_0_RSRC_GRP_TYPE_DST_DATA_SECTORS] = { + {0, 0}, {16, 16}, {2, 2}, {2, 2}, {0, 0}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_DST_DPS_DMARS] = { + {0, 0}, {2, 63}, {1, 2}, {1, 2}, {0, 2}, {0, 0} }, + }, + [IPA_4_5_AUTO_MHI] = { + /* PCIE/DPL DDR DMA/CV2X QDSS uC N/A */ + [IPA_v4_0_RSRC_GRP_TYPE_DST_DATA_SECTORS] = { + {16, 16}, {5, 5}, {2, 2}, {2, 2}, {0, 0}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_DST_DPS_DMARS] = { + {2, 63}, {1, 63}, {1, 2}, {1, 2}, {0, 2}, {0, 0} }, + }, + [IPA_4_7] = { + /* UL/DL/DPL, other are invalid */ + [IPA_v4_0_RSRC_GRP_TYPE_DST_DATA_SECTORS] = { + {7, 7}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_DST_DPS_DMARS] = { + {2, 2}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0} }, + }, + [IPA_4_9] = { + /*UL/DL/DPL DM uC DRB IP unused unused */ + [IPA_v4_0_RSRC_GRP_TYPE_DST_DATA_SECTORS] = { + {9, 9}, {1, 1}, {1, 1}, {39, 39}, {0, 0}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_DST_DPS_DMARS] = { + {2, 3}, {1, 2}, {0, 2}, {0, 0}, {0, 0}, {0, 0} }, + }, + [IPA_4_11] = { + /* UL/DL/DPL, other are invalid */ + [IPA_v4_0_RSRC_GRP_TYPE_DST_DATA_SECTORS] = { + {3,3}, {0, 0}, {25, 25}, {0, 0}, {0, 0}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_DST_DPS_DMARS] = { + {2, 2}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0} }, + }, + [IPA_5_0] = { + /* UL DL unused unused unused UC_RX_Q DRBIP N/A */ + [IPA_v5_0_RSRC_GRP_TYPE_DST_DATA_SECTORS] = { + {6, 6}, {5, 5}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {39, 39}, }, + [IPA_v5_0_RSRC_GRP_TYPE_DST_DPS_DMARS] = { + {0, 3}, {0, 3}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, }, + [IPA_v5_0_RSRC_GRP_TYPE_DST_ULSO_SEGMENTS] = { + {0, 0x3f}, {0, 0x3f}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, }, + }, + [IPA_5_0_MHI] = { + /* UL DL IPADMA QDSS unused unused CV2X */ + [IPA_v5_0_RSRC_GRP_TYPE_DST_DATA_SECTORS] = { + {6, 6}, {5, 5}, {2, 2}, {2, 2}, {0, 0}, {0, 0}, {30, 39}, }, + [IPA_v5_0_RSRC_GRP_TYPE_DST_DPS_DMARS] = { + {0, 3}, {0, 3}, {1, 2}, {1, 1}, {0, 0}, {0, 0}, {0, 0}, }, + }, + + [IPA_5_1] = { + /* UL DL unused unused unused UC_RX_Q DRBIP N/A */ + [IPA_v5_0_RSRC_GRP_TYPE_DST_DATA_SECTORS] = { + {6, 6}, {5, 5}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {39, 39}, }, + [IPA_v5_0_RSRC_GRP_TYPE_DST_DPS_DMARS] = { + {0, 3}, {0, 3}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, }, + [IPA_v5_0_RSRC_GRP_TYPE_DST_ULSO_SEGMENTS] = { + {0, 0x3f}, {0, 0x3f}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, }, + }, + + [IPA_5_1_APQ] = { + /* UL DL unused unused unused UC_RX_Q DRBIP N/A */ + [IPA_v5_0_RSRC_GRP_TYPE_DST_DATA_SECTORS] = { + {6, 6}, {5, 5}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {39, 39}, }, + [IPA_v5_0_RSRC_GRP_TYPE_DST_DPS_DMARS] = { + {0, 3}, {0, 3}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, }, + }, + + [IPA_5_2] = { + /* UL DL unused unused unused UC_RX_Q DRBIP N/A */ + [IPA_v5_0_RSRC_GRP_TYPE_DST_DATA_SECTORS] = { + {3, 3}, {3, 3}, {0, 0}, {23, 23}, {0, 0}, {0, 0}, {0, 0}, }, + + [IPA_v5_0_RSRC_GRP_TYPE_DST_DPS_DMARS] = { + {1, 2}, {1, 2}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, }, + [IPA_v5_0_RSRC_GRP_TYPE_DST_ULSO_SEGMENTS] = { + {1, 63}, {1, 63}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, }, + }, + + [IPA_5_5] = { + /* UL DL unused unused unused UC_RX_Q DRBIP N/A */ + [IPA_v5_0_RSRC_GRP_TYPE_DST_DATA_SECTORS] = { + {6, 6}, {5, 5}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {39, 39}, }, + [IPA_v5_0_RSRC_GRP_TYPE_DST_DPS_DMARS] = { + {0, 3}, {0, 3}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, }, + [IPA_v5_0_RSRC_GRP_TYPE_DST_ULSO_SEGMENTS] = { + {0, 0x3f}, {0, 0x3f}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, }, + }, + + [IPA_5_5_XR] = { + /* UL DL DMA QDSS unused UC_RX_Q DRBIP N/A */ + [IPA_v5_0_RSRC_GRP_TYPE_DST_DATA_SECTORS] = { + {6, 6}, {5, 5}, {2, 2}, {2, 2}, {0, 0}, {0, 0}, {0, 0}, }, + [IPA_v5_0_RSRC_GRP_TYPE_DST_DPS_DMARS] = { + {0, 3}, {0, 3}, {1, 2}, {1, 1}, {0, 0}, {0, 0}, {0, 0}, }, + [IPA_v5_0_RSRC_GRP_TYPE_DST_ULSO_SEGMENTS] = { + {0, 0x3f}, {0, 0x3f}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, }, + }, +}; + +static const struct rsrc_min_max ipa3_rsrc_rx_grp_config + [IPA_VER_MAX][IPA_RSRC_GRP_TYPE_RX_MAX][IPA_GROUP_MAX] = { + [IPA_3_0] = { + /* UL DL DIAG DMA unused uC Rx */ + [IPA_RSRC_GRP_TYPE_RX_HPS_CMDQ] = { + {16, 16}, {24, 24}, {8, 8}, {8, 8}, {0, 0}, {8, 8} }, + }, + [IPA_3_5] = { + /* unused UL_DL unused UC_RX_Q N/A N/A */ + [IPA_RSRC_GRP_TYPE_RX_HPS_CMDQ] = { + {0, 0}, {7, 7}, {0, 0}, {2, 2}, {0, 0}, {0, 0} }, + }, + [IPA_3_5_MHI] = { + /* PCIE DDR DMA unused N/A N/A */ + [IPA_RSRC_GRP_TYPE_RX_HPS_CMDQ] = { + {3, 3}, {7, 7}, {2, 2}, {0, 0}, {0, 0}, {0, 0} }, + }, + [IPA_3_5_1] = { + /* LWA_DL UL_DL unused UC_RX_Q N/A N/A */ + [IPA_RSRC_GRP_TYPE_RX_HPS_CMDQ] = { + {3, 3}, {7, 7}, {0, 0}, {2, 2}, {0, 0}, {0, 0} }, + }, + [IPA_4_0] = { + /* LWA_DL UL_DL unused UC_RX_Q, other are invalid */ + [IPA_RSRC_GRP_TYPE_RX_HPS_CMDQ] = { + {3, 3}, {7, 7}, {0, 0}, {2, 2}, {0, 0}, {0, 0} }, + }, + [IPA_4_0_MHI] = { + /* PCIE DDR DMA unused N/A N/A */ + [IPA_RSRC_GRP_TYPE_RX_HPS_CMDQ] = { + {3, 3}, {7, 7}, {2, 2}, {0, 0}, {0, 0}, {0, 0} }, + }, + [IPA_4_1] = { + /* LWA_DL UL_DL unused UC_RX_Q, other are invalid */ + [IPA_RSRC_GRP_TYPE_RX_HPS_CMDQ] = { + {3, 3}, {7, 7}, {0, 0}, {2, 2}, {0, 0}, {0, 0} }, + }, + [IPA_4_2] = { + /* UL_DL, other are invalid */ + [IPA_RSRC_GRP_TYPE_RX_HPS_CMDQ] = { + {4, 4}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0} }, + }, + [IPA_4_5] = { + /* unused UL_DL unused unused UC_RX_Q N/A */ + [IPA_RSRC_GRP_TYPE_RX_HPS_CMDQ] = { + {0, 0}, {3, 3}, {0, 0}, {0, 0}, {0, 0}, {0, 0} }, + }, + [IPA_4_5_MHI] = { + /* PCIE DDR DMA QDSS unused N/A */ + [IPA_RSRC_GRP_TYPE_RX_HPS_CMDQ] = { + {3, 3}, {3, 3}, {3, 3}, {3, 3}, {0, 0}, {0, 0} }, + }, + [IPA_4_5_APQ] = { + /* unused UL_DL unused unused UC_RX_Q N/A */ + [IPA_RSRC_GRP_TYPE_RX_HPS_CMDQ] = { + {0, 0}, {3, 3}, {0, 0}, {0, 0}, {0, 0}, {0, 0} }, + }, + [IPA_4_5_AUTO] = { + /* unused UL_DL DMA/CV2X unused UC_RX_Q N/A */ + [IPA_RSRC_GRP_TYPE_RX_HPS_CMDQ] = { + {0, 0}, {3, 3}, {3, 3}, {0, 0}, {0, 0}, {0, 0} }, + }, + [IPA_4_5_AUTO_MHI] = { + /* PCIE DDR DMA QDSS unused N/A */ + [IPA_RSRC_GRP_TYPE_RX_HPS_CMDQ] = { + { 3, 3 }, {3, 3}, {3, 3}, {3, 3}, {0, 0}, { 0, 0 } }, + }, + [IPA_4_7] = { + /* unused UL_DL unused unused UC_RX_Q N/A */ + [IPA_RSRC_GRP_TYPE_RX_HPS_CMDQ] = { + {3, 3}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0} }, + }, + [IPA_4_9] = { + /* unused UL_DL unused unused UC_RX_Q N/A */ + [IPA_RSRC_GRP_TYPE_RX_HPS_CMDQ] = { + {3, 3}, {3, 3}, {0, 0}, {0, 0}, {0, 0}, {0, 0} }, + }, + [IPA_4_11] = { + /* unused UL_DL unused unused UC_RX_Q N/A */ + [IPA_RSRC_GRP_TYPE_RX_HPS_CMDQ] = { + {3, 3}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0} }, + }, + [IPA_5_0] = { + /* UL DL unused unused URLLC UC_RX_Q */ + [IPA_RSRC_GRP_TYPE_RX_HPS_CMDQ] = { + {3, 3}, {3, 3}, {0, 0}, {0, 0}, {3, 3}, {0, 0} }, + }, + [IPA_5_0_MHI] = { + /* UL DL unused unused URLLC UC_RX_Q */ + [IPA_RSRC_GRP_TYPE_RX_HPS_CMDQ] = { + {3, 3}, {3, 3}, {3, 3}, {3, 3}, {3, 3}, {0, 0} }, + }, + + [IPA_5_1] = { + /* UL DL unused unused URLLC UC_RX_Q */ + [IPA_RSRC_GRP_TYPE_RX_HPS_CMDQ] = { + {3, 3}, {3, 3}, {0, 0}, {0, 0}, {3, 3}, {0, 0} }, + }, + + [IPA_5_1_APQ] = { + /* UL DL unused unused URLLC UC_RX_Q */ + [IPA_RSRC_GRP_TYPE_RX_HPS_CMDQ] = { + {3, 3}, {3, 3}, {0, 0}, {0, 0}, {3, 3}, {0, 0} }, + }, + [IPA_5_2] = { + /* UL DL unused unused URLLC UC_RX_Q */ + [IPA_RSRC_GRP_TYPE_RX_HPS_CMDQ] = { + {3, 3}, {3, 3}, {3, 3}, {0, 0}, {0, 0}, {0, 0} }, + }, + + [IPA_5_5] = { + /* UL DL unused unused URLLC UC_RX_Q */ + [IPA_RSRC_GRP_TYPE_RX_HPS_CMDQ] = { + {3, 3}, {3, 3}, {0, 0}, {0, 0}, {3, 3}, {0, 0} }, + }, + + [IPA_5_5_XR] = { + /* UL DL DMA QDSS URLLC UC_RX_Q */ + [IPA_RSRC_GRP_TYPE_RX_HPS_CMDQ] = { + {3, 3}, {3, 3}, {3, 3}, {3, 3}, {3, 3}, {0, 0} }, + }, +}; + +static const u32 ipa3_rsrc_rx_grp_hps_weight_config + [IPA_VER_MAX][IPA_RSRC_GRP_TYPE_RX_HPS_WEIGHT_MAX][IPA_GROUP_MAX] = { + [IPA_3_0] = { + /* UL DL DIAG DMA unused uC Rx */ + [IPA_RSRC_GRP_TYPE_RX_HPS_WEIGHT_CONFIG] = { 0, 0, 0, 0, 0, 0 }, + }, + [IPA_3_5] = { + /* unused UL_DL unused UC_RX_Q N/A N/A */ + [IPA_RSRC_GRP_TYPE_RX_HPS_WEIGHT_CONFIG] = { 1, 1, 1, 1, 0, 0 }, + }, + [IPA_3_5_MHI] = { + /* PCIE DDR DMA unused N/A N/A */ + [IPA_RSRC_GRP_TYPE_RX_HPS_WEIGHT_CONFIG] = { 3, 5, 1, 1, 0, 0 }, + }, + [IPA_3_5_1] = { + /* LWA_DL UL_DL unused UC_RX_Q N/A N/A */ + [IPA_RSRC_GRP_TYPE_RX_HPS_WEIGHT_CONFIG] = { 1, 1, 1, 1, 0, 0 }, + }, + [IPA_4_0] = { + /* LWA_DL UL_DL unused UC_RX_Q N/A */ + [IPA_RSRC_GRP_TYPE_RX_HPS_WEIGHT_CONFIG] = { 1, 1, 1, 1, 0, 0 }, + }, + [IPA_4_0_MHI] = { + /* PCIE DDR DMA unused N/A N/A */ + [IPA_RSRC_GRP_TYPE_RX_HPS_WEIGHT_CONFIG] = { 3, 5, 1, 1, 0, 0 }, + }, + [IPA_4_1] = { + /* LWA_DL UL_DL unused UC_RX_Q, other are invalid */ + [IPA_RSRC_GRP_TYPE_RX_HPS_WEIGHT_CONFIG] = { 1, 1, 1, 1, 0, 0 }, + }, +}; + +static const struct ipa_rsrc_cfg ipa_rsrc_config[IPA_VER_MAX] = { + [IPA_5_0] = { + .src_grp_index = 4, + .src_grp_valid = 1, + .dst_pipe_index = 0, + .dst_pipe_valid = 0, + .dst_grp_index = 0, + .dst_grp_valid = 0, + .src_grp_2nd_prio_index = 1, + .src_grp_2nd_prio_valid = 1, + }, + [IPA_5_1] = { + .src_grp_index = 4, + .src_grp_valid = 1, + .dst_pipe_index = 0, + .dst_pipe_valid = 0, + .dst_grp_index = 0, + .dst_grp_valid = 0, + .src_grp_2nd_prio_index = 1, + .src_grp_2nd_prio_valid = 1, + }, + [IPA_5_2] = { + .src_grp_index = 2, + .src_grp_valid = 1, + .dst_pipe_index = 0, + .dst_pipe_valid = 0, + .dst_grp_index = 0, + .dst_grp_valid = 0, + .src_grp_2nd_prio_index = 0, + .src_grp_2nd_prio_valid = 0, + }, +}; + +enum ipa_qmb_instance_type { + IPA_QMB_INSTANCE_DDR = 0, + IPA_QMB_INSTANCE_PCIE = 1, + IPA_QMB_INSTANCE_MAX +}; + +#define QMB_MASTER_SELECT_DDR IPA_QMB_INSTANCE_DDR +#define QMB_MASTER_SELECT_PCIE IPA_QMB_INSTANCE_PCIE + +struct ipa_qmb_outstanding { + u16 ot_reads; + u16 ot_writes; + u16 ot_read_beats; +}; + +/*TODO: Update correct values of max_read_beats for all targets*/ + +static const struct ipa_qmb_outstanding ipa3_qmb_outstanding + [IPA_VER_MAX][IPA_QMB_INSTANCE_MAX] = { + [IPA_3_0][IPA_QMB_INSTANCE_DDR] = {8, 8, 0}, + [IPA_3_0][IPA_QMB_INSTANCE_PCIE] = {8, 2, 0}, + [IPA_3_5][IPA_QMB_INSTANCE_DDR] = {8, 8, 0}, + [IPA_3_5][IPA_QMB_INSTANCE_PCIE] = {12, 4, 0}, + [IPA_3_5_MHI][IPA_QMB_INSTANCE_DDR] = {8, 8, 0}, + [IPA_3_5_MHI][IPA_QMB_INSTANCE_PCIE] = {12, 4, 0}, + [IPA_3_5_1][IPA_QMB_INSTANCE_DDR] = {8, 8, 0}, + [IPA_3_5_1][IPA_QMB_INSTANCE_PCIE] = {12, 4, 0}, + [IPA_4_0][IPA_QMB_INSTANCE_DDR] = {12, 8, 120}, + [IPA_4_0][IPA_QMB_INSTANCE_PCIE] = {12, 4, 0}, + [IPA_4_0_MHI][IPA_QMB_INSTANCE_DDR] = {12, 8, 0}, + [IPA_4_0_MHI][IPA_QMB_INSTANCE_PCIE] = {12, 4, 0}, + [IPA_4_1][IPA_QMB_INSTANCE_DDR] = {12, 8, 120}, + [IPA_4_1][IPA_QMB_INSTANCE_PCIE] = {12, 4, 0}, + [IPA_4_2][IPA_QMB_INSTANCE_DDR] = {12, 8, 0}, + [IPA_4_5][IPA_QMB_INSTANCE_DDR] = {16, 8, 120}, + [IPA_4_5][IPA_QMB_INSTANCE_PCIE] = {12, 8, 0}, + [IPA_4_5_MHI][IPA_QMB_INSTANCE_DDR] = {16, 8, 120}, + [IPA_4_5_MHI][IPA_QMB_INSTANCE_PCIE] = {12, 8, 0}, + [IPA_4_5_APQ][IPA_QMB_INSTANCE_DDR] = {16, 8, 120}, + [IPA_4_5_APQ][IPA_QMB_INSTANCE_PCIE] = {12, 8, 0}, + [IPA_4_5_AUTO][IPA_QMB_INSTANCE_DDR] = {16, 8, 0}, + [IPA_4_5_AUTO][IPA_QMB_INSTANCE_PCIE] = {12, 8, 0}, + [IPA_4_5_AUTO_MHI][IPA_QMB_INSTANCE_DDR] = {16, 8, 0}, + [IPA_4_5_AUTO_MHI][IPA_QMB_INSTANCE_PCIE] = {12, 8, 0}, + [IPA_4_7][IPA_QMB_INSTANCE_DDR] = {13, 12, 120}, + [IPA_4_9][IPA_QMB_INSTANCE_DDR] = {16, 8, 120}, + [IPA_4_11][IPA_QMB_INSTANCE_DDR] = {13, 12, 120}, + [IPA_5_2][IPA_QMB_INSTANCE_DDR] = {13, 13, 0}, + [IPA_5_5][IPA_QMB_INSTANCE_DDR] = {16, 12, 0}, + [IPA_5_5][IPA_QMB_INSTANCE_PCIE] = {16, 8, 0}, + [IPA_5_5_XR][IPA_QMB_INSTANCE_DDR] = {16, 12, 0}, + [IPA_5_5_XR][IPA_QMB_INSTANCE_PCIE] = {16, 8, 0}, +}; + +enum ipa_tx_instance { + IPA_TX_INSTANCE_UL = 0, + IPA_TX_INSTANCE_DL = 1, + IPA_TX_INSTANCE_NA = 0xff +}; + +struct ipa_ep_configuration { + bool valid; + int group_num; + bool support_flt; + int sequencer_type; + u8 qmb_master_sel; + struct ipa_gsi_ep_config ipa_gsi_ep_info; + u8 tx_instance; +}; + +/* clients not included in the list below are considered as invalid */ +static const struct ipa_ep_configuration ipa3_ep_mapping + [IPA_VER_MAX][IPA_CLIENT_MAX] = { + [IPA_3_0][IPA_CLIENT_WLAN1_PROD] = { + true, IPA_v3_0_GROUP_UL, true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 10, 1, 8, 16, IPA_EE_UC }, IPA_TX_INSTANCE_NA }, + [IPA_3_0][IPA_CLIENT_USB_PROD] = { + true, IPA_v3_0_GROUP_UL, true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 1, 3, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_0][IPA_CLIENT_APPS_LAN_PROD] = { + true, IPA_v3_0_GROUP_DL, false, + IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 14, 11, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_0][IPA_CLIENT_APPS_WAN_PROD] = { + true, IPA_v3_0_GROUP_UL, true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 3, 5, 16, 32, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_0][IPA_CLIENT_APPS_CMD_PROD] = { + true, IPA_v3_0_GROUP_IMM_CMD, false, + IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY, + QMB_MASTER_SELECT_DDR, + { 22, 6, 18, 28, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_0][IPA_CLIENT_ODU_PROD] = { + true, IPA_v3_0_GROUP_UL, true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 12, 9, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_0][IPA_CLIENT_MHI_PROD] = { + true, IPA_v3_0_GROUP_UL, true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_PCIE, + { 0, 0, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_0][IPA_CLIENT_Q6_LAN_PROD] = { + true, IPA_v3_0_GROUP_UL, false, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 9, 4, 8, 12, IPA_EE_Q6 }, IPA_TX_INSTANCE_NA }, + [IPA_3_0][IPA_CLIENT_Q6_WAN_PROD] = { + true, IPA_v3_0_GROUP_DL, true, + IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 5, 0, 16, 32, IPA_EE_Q6 }, IPA_TX_INSTANCE_NA }, + [IPA_3_0][IPA_CLIENT_Q6_CMD_PROD] = { + true, IPA_v3_0_GROUP_IMM_CMD, false, + IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 6, 1, 18, 28, IPA_EE_Q6 }, IPA_TX_INSTANCE_NA }, + [IPA_3_0][IPA_CLIENT_Q6_DECOMP_PROD] = { + true, IPA_v3_0_GROUP_Q6ZIP, + false, IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 7, 2, 0, 0, IPA_EE_Q6 }, IPA_TX_INSTANCE_NA }, + [IPA_3_0][IPA_CLIENT_Q6_DECOMP2_PROD] = { + true, IPA_v3_0_GROUP_Q6ZIP, + false, IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 8, 3, 0, 0, IPA_EE_Q6 }, IPA_TX_INSTANCE_NA }, + [IPA_3_0][IPA_CLIENT_MEMCPY_DMA_SYNC_PROD] = { + true, IPA_v3_0_GROUP_DMA, false, + IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY, + QMB_MASTER_SELECT_PCIE, + { 12, 9, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_0][IPA_CLIENT_MEMCPY_DMA_ASYNC_PROD] = { + true, IPA_v3_0_GROUP_DMA, false, + IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY, + QMB_MASTER_SELECT_PCIE, + { 13, 10, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_0][IPA_CLIENT_ETHERNET_PROD] = { + true, IPA_v3_0_GROUP_UL, true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + {2, 0, 8, 16, IPA_EE_UC}, IPA_TX_INSTANCE_NA }, + /* Only for test purpose */ + [IPA_3_0][IPA_CLIENT_TEST_PROD] = { + true, IPA_v3_0_GROUP_UL, true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 1, 3, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_0][IPA_CLIENT_TEST1_PROD] = { + true, IPA_v3_0_GROUP_UL, true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 1, 3, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_0][IPA_CLIENT_TEST2_PROD] = { + true, IPA_v3_0_GROUP_UL, true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 3, 5, 16, 32, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_0][IPA_CLIENT_TEST3_PROD] = { + true, IPA_v3_0_GROUP_UL, true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 12, 9, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_0][IPA_CLIENT_TEST4_PROD] = { + true, IPA_v3_0_GROUP_UL, true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 13, 10, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + + [IPA_3_0][IPA_CLIENT_WLAN1_CONS] = { + true, IPA_v3_0_GROUP_DL, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 25, 4, 8, 8, IPA_EE_UC }, IPA_TX_INSTANCE_NA }, + [IPA_3_0][IPA_CLIENT_WLAN2_CONS] = { + true, IPA_v3_0_GROUP_DL, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 27, 4, 8, 8, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_0][IPA_CLIENT_WLAN3_CONS] = { + true, IPA_v3_0_GROUP_DL, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 28, 13, 8, 8, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_0][IPA_CLIENT_WLAN4_CONS] = { + true, IPA_v3_0_GROUP_DL, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 29, 14, 8, 8, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_0][IPA_CLIENT_USB_CONS] = { + true, IPA_v3_0_GROUP_DL, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 26, 12, 8, 8, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_0][IPA_CLIENT_USB_DPL_CONS] = { + true, IPA_v3_0_GROUP_DPL, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 17, 2, 8, 12, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_0][IPA_CLIENT_APPS_LAN_CONS] = { + true, IPA_v3_0_GROUP_UL, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 15, 7, 8, 12, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_0][IPA_CLIENT_APPS_WAN_CONS] = { + true, IPA_v3_0_GROUP_DL, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 16, 8, 8, 12, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_0][IPA_CLIENT_ODU_EMB_CONS] = { + true, IPA_v3_0_GROUP_DL, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 23, 1, 8, 8, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_0][IPA_CLIENT_MHI_CONS] = { + true, IPA_v3_0_GROUP_DL, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_PCIE, + { 23, 1, 8, 8, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_0][IPA_CLIENT_Q6_LAN_CONS] = { + true, IPA_v3_0_GROUP_DL, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 19, 6, 8, 12, IPA_EE_Q6 }, IPA_TX_INSTANCE_NA }, + [IPA_3_0][IPA_CLIENT_Q6_WAN_CONS] = { + true, IPA_v3_0_GROUP_UL, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 18, 5, 8, 12, IPA_EE_Q6 }, IPA_TX_INSTANCE_NA }, + [IPA_3_0][IPA_CLIENT_Q6_DUN_CONS] = { + true, IPA_v3_0_GROUP_DIAG, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 30, 7, 4, 4, IPA_EE_Q6 }, IPA_TX_INSTANCE_NA }, + [IPA_3_0][IPA_CLIENT_Q6_DECOMP_CONS] = { + true, IPA_v3_0_GROUP_Q6ZIP, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 21, 8, 4, 4, IPA_EE_Q6 }, IPA_TX_INSTANCE_NA }, + [IPA_3_0][IPA_CLIENT_Q6_DECOMP2_CONS] = { + true, IPA_v3_0_GROUP_Q6ZIP, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 4, 9, 4, 4, IPA_EE_Q6 }, IPA_TX_INSTANCE_NA }, + [IPA_3_0][IPA_CLIENT_MEMCPY_DMA_SYNC_CONS] = { + true, IPA_v3_0_GROUP_DMA, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_PCIE, + { 28, 13, 8, 8, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_0][IPA_CLIENT_MEMCPY_DMA_ASYNC_CONS] = { + true, IPA_v3_0_GROUP_DMA, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_PCIE, + { 29, 14, 8, 8, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_0][IPA_CLIENT_ETHERNET_CONS] = { + true, IPA_v3_0_GROUP_DL, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + {24, 3, 8, 8, IPA_EE_UC}, IPA_TX_INSTANCE_NA }, + /* Only for test purpose */ + [IPA_3_0][IPA_CLIENT_TEST_CONS] = { + true, IPA_v3_0_GROUP_DL, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 26, 12, 8, 8, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_0][IPA_CLIENT_TEST1_CONS] = { + true, IPA_v3_0_GROUP_DL, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 26, 12, 8, 8, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_0][IPA_CLIENT_TEST2_CONS] = { + true, IPA_v3_0_GROUP_DL, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 27, 4, 8, 8, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_0][IPA_CLIENT_TEST3_CONS] = { + true, IPA_v3_0_GROUP_DL, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 28, 13, 8, 8, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_0][IPA_CLIENT_TEST4_CONS] = { + true, IPA_v3_0_GROUP_DL, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 29, 14, 8, 8, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + /* Dummy consumer (pipe 31) is used in L2TP rt rule */ + [IPA_3_0][IPA_CLIENT_DUMMY_CONS] = { + true, IPA_v3_0_GROUP_DL, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 31, 31, 8, 8, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + + /* IPA_3_5 */ + [IPA_3_5][IPA_CLIENT_WLAN1_PROD] = { + true, IPA_v3_5_GROUP_UL_DL, true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 6, 1, 8, 16, IPA_EE_UC }, IPA_TX_INSTANCE_NA }, + [IPA_3_5][IPA_CLIENT_USB_PROD] = { + true, IPA_v3_5_GROUP_UL_DL, true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 0, 7, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_5][IPA_CLIENT_APPS_LAN_PROD] = { + true, IPA_v3_5_GROUP_UL_DL, false, + IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 8, 9, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_5][IPA_CLIENT_APPS_WAN_PROD] = { + true, IPA_v3_5_GROUP_UL_DL, true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 2, 3, 16, 32, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_5][IPA_CLIENT_APPS_CMD_PROD] = { + true, IPA_v3_5_GROUP_UL_DL, false, + IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY, + QMB_MASTER_SELECT_DDR, + { 5, 4, 20, 23, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_5][IPA_CLIENT_ODU_PROD] = { + true, IPA_v3_5_GROUP_UL_DL, true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 1, 0, 8, 16, IPA_EE_UC }, IPA_TX_INSTANCE_NA }, + [IPA_3_5][IPA_CLIENT_Q6_LAN_PROD] = { + true, IPA_v3_5_GROUP_UL_DL, true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 3, 0, 16, 32, IPA_EE_Q6 }, IPA_TX_INSTANCE_NA }, + [IPA_3_5][IPA_CLIENT_Q6_CMD_PROD] = { + true, IPA_v3_5_GROUP_UL_DL, false, + IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 4, 1, 20, 23, IPA_EE_Q6 }, IPA_TX_INSTANCE_NA }, + /* Only for test purpose */ + [IPA_3_5][IPA_CLIENT_TEST_PROD] = { + true, IPA_v3_5_GROUP_UL_DL, true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + {0, 7, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_5][IPA_CLIENT_TEST1_PROD] = { + true, IPA_v3_5_GROUP_UL_DL, true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + {0, 7, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_5][IPA_CLIENT_TEST2_PROD] = { + true, IPA_v3_5_GROUP_UL_DL, true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 1, 0, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_5][IPA_CLIENT_TEST3_PROD] = { + true, IPA_v3_5_GROUP_UL_DL, true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + {7, 8, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_5][IPA_CLIENT_TEST4_PROD] = { + true, IPA_v3_5_GROUP_UL_DL, true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 8, 9, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + + [IPA_3_5][IPA_CLIENT_WLAN1_CONS] = { + true, IPA_v3_5_GROUP_UL_DL, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 16, 3, 8, 8, IPA_EE_UC }, IPA_TX_INSTANCE_NA }, + [IPA_3_5][IPA_CLIENT_WLAN2_CONS] = { + true, IPA_v3_5_GROUP_UL_DL, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 18, 12, 8, 8, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_5][IPA_CLIENT_WLAN3_CONS] = { + true, IPA_v3_5_GROUP_UL_DL, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 19, 13, 8, 8, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_5][IPA_CLIENT_USB_CONS] = { + true, IPA_v3_5_GROUP_UL_DL, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_PCIE, + { 17, 11, 8, 8, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_5][IPA_CLIENT_USB_DPL_CONS] = { + true, IPA_v3_5_GROUP_UL_DL, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 14, 10, 4, 6, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_5][IPA_CLIENT_APPS_LAN_CONS] = { + true, IPA_v3_5_GROUP_UL_DL, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 9, 5, 8, 12, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_5][IPA_CLIENT_APPS_WAN_CONS] = { + true, IPA_v3_5_GROUP_UL_DL, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 10, 6, 8, 12, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_5][IPA_CLIENT_ODU_EMB_CONS] = { + true, IPA_v3_5_GROUP_UL_DL, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 15, 1, 8, 8, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_5][IPA_CLIENT_Q6_LAN_CONS] = { + true, IPA_v3_5_GROUP_UL_DL, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 13, 3, 8, 12, IPA_EE_Q6 }, IPA_TX_INSTANCE_NA }, + [IPA_3_5][IPA_CLIENT_Q6_WAN_CONS] = { + true, IPA_v3_5_GROUP_UL_DL, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 12, 2, 8, 12, IPA_EE_Q6 }, IPA_TX_INSTANCE_NA }, + /* Only for test purpose */ + /* MBIM aggregation test pipes should have the same QMB as USB_CONS */ + [IPA_3_5][IPA_CLIENT_TEST_CONS] = { + true, IPA_v3_5_GROUP_UL_DL, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_PCIE, + { 15, 1, 8, 8, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_5][IPA_CLIENT_TEST1_CONS] = { + true, IPA_v3_5_GROUP_UL_DL, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 15, 1, 8, 8, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_5][IPA_CLIENT_TEST2_CONS] = { + true, IPA_v3_5_GROUP_UL_DL, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_PCIE, + { 17, 11, 8, 8, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_5][IPA_CLIENT_TEST3_CONS] = { + true, IPA_v3_5_GROUP_UL_DL, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 18, 12, 8, 8, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_5][IPA_CLIENT_TEST4_CONS] = { + true, IPA_v3_5_GROUP_UL_DL, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_PCIE, + { 19, 13, 8, 8, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + /* Dummy consumer (pipe 31) is used in L2TP rt rule */ + [IPA_3_5][IPA_CLIENT_DUMMY_CONS] = { + true, IPA_v3_5_GROUP_UL_DL, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_PCIE, + { 31, 31, 8, 8, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + + /* IPA_3_5_MHI */ + [IPA_3_5_MHI][IPA_CLIENT_USB_PROD] = { + false, IPA_EP_NOT_ALLOCATED, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { -1, -1, -1, -1, -1 }, IPA_TX_INSTANCE_NA }, + [IPA_3_5_MHI][IPA_CLIENT_APPS_WAN_PROD] = { + true, IPA_v3_5_MHI_GROUP_DDR, true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 2, 3, 16, 32, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_5_MHI][IPA_CLIENT_APPS_CMD_PROD] = { + true, IPA_v3_5_MHI_GROUP_DDR, false, + IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY, + QMB_MASTER_SELECT_DDR, + { 5, 4, 20, 23, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_5_MHI][IPA_CLIENT_MHI_PROD] = { + true, IPA_v3_5_MHI_GROUP_PCIE, true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_PCIE, + { 1, 0, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_5_MHI][IPA_CLIENT_Q6_LAN_PROD] = { + true, IPA_v3_5_MHI_GROUP_DDR, true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 3, 0, 16, 32, IPA_EE_Q6 }, IPA_TX_INSTANCE_NA }, + [IPA_3_5_MHI][IPA_CLIENT_Q6_WAN_PROD] = { + true, IPA_v3_5_MHI_GROUP_DDR, true, + IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 6, 4, 10, 30, IPA_EE_Q6 }, IPA_TX_INSTANCE_NA }, + [IPA_3_5_MHI][IPA_CLIENT_Q6_CMD_PROD] = { + true, IPA_v3_5_MHI_GROUP_PCIE, false, + IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 4, 1, 20, 23, IPA_EE_Q6 }, IPA_TX_INSTANCE_NA }, + [IPA_3_5_MHI][IPA_CLIENT_MEMCPY_DMA_SYNC_PROD] = { + true, IPA_v3_5_MHI_GROUP_DMA, false, + IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY, + QMB_MASTER_SELECT_DDR, + { 7, 8, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_5_MHI][IPA_CLIENT_MEMCPY_DMA_ASYNC_PROD] = { + true, IPA_v3_5_MHI_GROUP_DMA, false, + IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY, + QMB_MASTER_SELECT_DDR, + { 8, 9, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + /* Only for test purpose */ + [IPA_3_5_MHI][IPA_CLIENT_TEST_PROD] = { + true, IPA_v3_5_MHI_GROUP_DDR, true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + {0, 7, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_5_MHI][IPA_CLIENT_TEST1_PROD] = { + 0, IPA_v3_5_MHI_GROUP_DDR, true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + {0, 7, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_5_MHI][IPA_CLIENT_TEST2_PROD] = { + true, IPA_v3_5_MHI_GROUP_PCIE, true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_PCIE, + { 1, 0, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_5_MHI][IPA_CLIENT_TEST3_PROD] = { + true, IPA_v3_5_MHI_GROUP_DMA, true, + IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY, + QMB_MASTER_SELECT_DDR, + { 7, 8, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_5_MHI][IPA_CLIENT_TEST4_PROD] = { + true, IPA_v3_5_MHI_GROUP_DMA, true, + IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY, + QMB_MASTER_SELECT_DDR, + { 8, 9, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + + [IPA_3_5_MHI][IPA_CLIENT_WLAN1_CONS] = { + true, IPA_v3_5_MHI_GROUP_DDR, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 16, 3, 8, 8, IPA_EE_UC }, IPA_TX_INSTANCE_NA }, + [IPA_3_5_MHI][IPA_CLIENT_USB_CONS] = { + false, IPA_EP_NOT_ALLOCATED, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { -1, -1, -1, -1, -1 }, IPA_TX_INSTANCE_NA }, + [IPA_3_5_MHI][IPA_CLIENT_USB_DPL_CONS] = { + false, IPA_EP_NOT_ALLOCATED, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { -1, -1, -1, -1, -1 }, IPA_TX_INSTANCE_NA }, + [IPA_3_5_MHI][IPA_CLIENT_APPS_LAN_CONS] = { + true, IPA_v3_5_MHI_GROUP_DDR, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 9, 5, 8, 12, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_5_MHI][IPA_CLIENT_APPS_WAN_CONS] = { + true, IPA_v3_5_MHI_GROUP_DDR, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 10, 6, 8, 12, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_5_MHI][IPA_CLIENT_MHI_CONS] = { + true, IPA_v3_5_MHI_GROUP_PCIE, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_PCIE, + { 15, 1, 8, 8, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_5_MHI][IPA_CLIENT_Q6_LAN_CONS] = { + true, IPA_v3_5_MHI_GROUP_DDR, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 13, 3, 8, 12, IPA_EE_Q6 }, IPA_TX_INSTANCE_NA }, + [IPA_3_5_MHI][IPA_CLIENT_Q6_WAN_CONS] = { + true, IPA_v3_5_MHI_GROUP_DDR, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 12, 2, 8, 12, IPA_EE_Q6 }, IPA_TX_INSTANCE_NA }, + [IPA_3_5_MHI][IPA_CLIENT_MEMCPY_DMA_SYNC_CONS] = { + true, IPA_v3_5_MHI_GROUP_DMA, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_PCIE, + { 18, 12, 8, 8, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_5_MHI][IPA_CLIENT_MEMCPY_DMA_ASYNC_CONS] = { + true, IPA_v3_5_MHI_GROUP_DMA, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_PCIE, + { 19, 13, 8, 8, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + /* Only for test purpose */ + [IPA_3_5_MHI][IPA_CLIENT_TEST_CONS] = { + true, IPA_v3_5_MHI_GROUP_PCIE, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_PCIE, + { 15, 1, 8, 8, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_5_MHI][IPA_CLIENT_TEST1_CONS] = { + true, IPA_v3_5_MHI_GROUP_PCIE, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_PCIE, + { 15, 1, 8, 8, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_5_MHI][IPA_CLIENT_TEST2_CONS] = { + true, IPA_v3_5_MHI_GROUP_DDR, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 17, 11, 8, 8, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_5_MHI][IPA_CLIENT_TEST3_CONS] = { + true, IPA_v3_5_MHI_GROUP_DMA, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_PCIE, + { 18, 12, 8, 8, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_5_MHI][IPA_CLIENT_TEST4_CONS] = { + true, IPA_v3_5_MHI_GROUP_DMA, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_PCIE, + { 19, 13, 8, 8, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + /* Dummy consumer (pipe 31) is used in L2TP rt rule */ + [IPA_3_5_MHI][IPA_CLIENT_DUMMY_CONS] = { + true, IPA_v3_5_MHI_GROUP_DMA, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_PCIE, + { 31, 31, 8, 8, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + + /* IPA_3_5_1 */ + [IPA_3_5_1][IPA_CLIENT_WLAN1_PROD] = { + true, IPA_v3_5_GROUP_UL_DL, true, + IPA_DPS_HPS_REP_SEQ_TYPE_2PKT_PROC_PASS_NO_DEC_UCP_DMAP, + QMB_MASTER_SELECT_DDR, + { 7, 1, 8, 16, IPA_EE_UC }, IPA_TX_INSTANCE_NA }, + [IPA_3_5_1][IPA_CLIENT_USB_PROD] = { + true, IPA_v3_5_GROUP_UL_DL, true, + IPA_DPS_HPS_REP_SEQ_TYPE_2PKT_PROC_PASS_NO_DEC_UCP_DMAP, + QMB_MASTER_SELECT_DDR, + { 0, 0, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_5_1][IPA_CLIENT_APPS_LAN_PROD] = { + true, IPA_v3_5_GROUP_UL_DL, false, + IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 8, 7, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_5_1][IPA_CLIENT_APPS_WAN_PROD] = { + true, IPA_v3_5_GROUP_UL_DL, true, + IPA_DPS_HPS_REP_SEQ_TYPE_2PKT_PROC_PASS_NO_DEC_UCP_DMAP, + QMB_MASTER_SELECT_DDR, + { 2, 3, 16, 32, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_5_1][IPA_CLIENT_APPS_CMD_PROD] = { + true, IPA_v3_5_GROUP_UL_DL, false, + IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY, + QMB_MASTER_SELECT_DDR, + { 5, 4, 20, 23, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_5_1][IPA_CLIENT_Q6_LAN_PROD] = { + true, IPA_v3_5_GROUP_UL_DL, true, + IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 3, 0, 16, 32, IPA_EE_Q6 }, IPA_TX_INSTANCE_NA }, + [IPA_3_5_1][IPA_CLIENT_Q6_WAN_PROD] = { + true, IPA_v3_5_GROUP_UL_DL, true, + IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 6, 4, 12, 30, IPA_EE_Q6 }, IPA_TX_INSTANCE_NA }, + [IPA_3_5_1][IPA_CLIENT_Q6_CMD_PROD] = { + true, IPA_v3_5_GROUP_UL_DL, false, + IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 4, 1, 20, 23, IPA_EE_Q6 }, IPA_TX_INSTANCE_NA }, + /* Only for test purpose */ + [IPA_3_5_1][IPA_CLIENT_TEST_PROD] = { + true, IPA_v3_5_GROUP_UL_DL, true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 0, 0, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_5_1][IPA_CLIENT_TEST1_PROD] = { + true, IPA_v3_5_GROUP_UL_DL, true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 0, 0, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_5_1][IPA_CLIENT_TEST2_PROD] = { + true, IPA_v3_5_GROUP_UL_DL, true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 2, 3, 16, 32, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_5_1][IPA_CLIENT_TEST3_PROD] = { + true, IPA_v3_5_GROUP_UL_DL, true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 4, 1, 20, 23, IPA_EE_Q6 }, IPA_TX_INSTANCE_NA }, + [IPA_3_5_1][IPA_CLIENT_TEST4_PROD] = { + true, IPA_v3_5_GROUP_UL_DL, true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 1, 0, 8, 16, IPA_EE_UC }, IPA_TX_INSTANCE_NA }, + + [IPA_3_5_1][IPA_CLIENT_WLAN1_CONS] = { + true, IPA_v3_5_GROUP_UL_DL, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 16, 11, 8, 8, IPA_EE_UC }, IPA_TX_INSTANCE_NA }, + [IPA_3_5_1][IPA_CLIENT_WLAN2_CONS] = { + true, IPA_v3_5_GROUP_UL_DL, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 18, 9, 8, 8, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_5_1][IPA_CLIENT_WLAN3_CONS] = { + true, IPA_v3_5_GROUP_UL_DL, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 19, 10, 8, 8, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_5_1][IPA_CLIENT_USB_CONS] = { + true, IPA_v3_5_GROUP_UL_DL, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 17, 8, 8, 8, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_5_1][IPA_CLIENT_USB_DPL_CONS] = { + true, IPA_v3_5_GROUP_UL_DL, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 11, 2, 4, 6, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_5_1][IPA_CLIENT_APPS_LAN_CONS] = { + true, IPA_v3_5_GROUP_UL_DL, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 9, 5, 8, 12, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_5_1][IPA_CLIENT_APPS_WAN_CONS] = { + true, IPA_v3_5_GROUP_UL_DL, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 10, 6, 8, 12, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_5_1][IPA_CLIENT_Q6_LAN_CONS] = { + true, IPA_v3_5_GROUP_UL_DL, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 13, 3, 8, 12, IPA_EE_Q6 }, IPA_TX_INSTANCE_NA }, + [IPA_3_5_1][IPA_CLIENT_Q6_WAN_CONS] = { + true, IPA_v3_5_GROUP_UL_DL, false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 12, 2, 8, 12, IPA_EE_Q6 }, IPA_TX_INSTANCE_NA }, + /* Only for test purpose */ + [IPA_3_5_1][IPA_CLIENT_TEST_CONS] = { + true, IPA_v3_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 17, 8, 8, 8, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_5_1][IPA_CLIENT_TEST1_CONS] = { + true, IPA_v3_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 17, 8, 8, 8, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_5_1][IPA_CLIENT_TEST2_CONS] = { + true, IPA_v3_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 18, 9, 8, 8, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_5_1][IPA_CLIENT_TEST3_CONS] = { + true, IPA_v3_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 19, 10, 8, 8, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_3_5_1][IPA_CLIENT_TEST4_CONS] = { + true, IPA_v3_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 11, 2, 4, 6, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + /* Dummy consumer (pipe 31) is used in L2TP rt rule */ + [IPA_3_5_1][IPA_CLIENT_DUMMY_CONS] = { + true, IPA_v3_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 31, 31, 8, 8, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + + /* IPA_4_0 */ + [IPA_4_0][IPA_CLIENT_WLAN1_PROD] = { + true, IPA_v4_0_GROUP_UL_DL, + true, + IPA_DPS_HPS_REP_SEQ_TYPE_2PKT_PROC_PASS_NO_DEC_UCP_DMAP, + QMB_MASTER_SELECT_DDR, + { 6, 2, 8, 16, IPA_EE_UC }, IPA_TX_INSTANCE_NA }, + [IPA_4_0][IPA_CLIENT_USB_PROD] = { + true, IPA_v4_0_GROUP_UL_DL, + true, + IPA_DPS_HPS_REP_SEQ_TYPE_2PKT_PROC_PASS_NO_DEC_UCP_DMAP, + QMB_MASTER_SELECT_DDR, + { 0, 8, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_0][IPA_CLIENT_APPS_LAN_PROD] = { + true, IPA_v4_0_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 8, 10, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_0][IPA_CLIENT_APPS_WAN_PROD] = { + true, IPA_v4_0_GROUP_UL_DL, + true, + IPA_DPS_HPS_REP_SEQ_TYPE_2PKT_PROC_PASS_NO_DEC_UCP_DMAP, + QMB_MASTER_SELECT_DDR, + { 2, 3, 16, 32, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_0][IPA_CLIENT_APPS_CMD_PROD] = { + true, IPA_v4_0_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY, + QMB_MASTER_SELECT_DDR, + { 5, 4, 20, 24, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_0][IPA_CLIENT_ODU_PROD] = { + true, IPA_v4_0_GROUP_UL_DL, + true, + IPA_DPS_HPS_REP_SEQ_TYPE_2PKT_PROC_PASS_NO_DEC_UCP_DMAP, + QMB_MASTER_SELECT_DDR, + { 1, 0, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_0][IPA_CLIENT_ETHERNET_PROD] = { + true, IPA_v4_0_GROUP_UL_DL, + true, + IPA_DPS_HPS_REP_SEQ_TYPE_2PKT_PROC_PASS_NO_DEC_UCP_DMAP, + QMB_MASTER_SELECT_DDR, + { 9, 0, 8, 16, IPA_EE_UC }, IPA_TX_INSTANCE_NA }, + [IPA_4_0][IPA_CLIENT_Q6_WAN_PROD] = { + true, IPA_v4_0_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 3, 0, 16, 32, IPA_EE_Q6 }, IPA_TX_INSTANCE_NA }, + [IPA_4_0][IPA_CLIENT_Q6_CMD_PROD] = { + true, IPA_v4_0_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 4, 1, 20, 24, IPA_EE_Q6 }, IPA_TX_INSTANCE_NA }, + /* Only for test purpose */ + [IPA_4_0][IPA_CLIENT_TEST_PROD] = { + true, IPA_v4_0_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + {0, 8, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_0][IPA_CLIENT_TEST1_PROD] = { + true, IPA_v4_0_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + {0, 8, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_0][IPA_CLIENT_TEST2_PROD] = { + true, IPA_v4_0_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 1, 0, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_0][IPA_CLIENT_TEST3_PROD] = { + true, IPA_v4_0_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 7, 9, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_0][IPA_CLIENT_TEST4_PROD] = { + true, IPA_v4_0_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + {8, 10, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + + + [IPA_4_0][IPA_CLIENT_WLAN1_CONS] = { + true, IPA_v4_0_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 18, 3, 6, 9, IPA_EE_UC }, IPA_TX_INSTANCE_NA }, + [IPA_4_0][IPA_CLIENT_WLAN2_CONS] = { + true, IPA_v4_0_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 20, 13, 9, 9, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_0][IPA_CLIENT_WLAN3_CONS] = { + true, IPA_v4_0_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 21, 14, 9, 9, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_0][IPA_CLIENT_USB_CONS] = { + true, IPA_v4_0_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 19, 12, 9, 9, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_0][IPA_CLIENT_USB_DPL_CONS] = { + true, IPA_v4_0_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 15, 7, 5, 5, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_0][IPA_CLIENT_APPS_LAN_CONS] = { + true, IPA_v4_0_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 10, 5, 9, 9, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_0][IPA_CLIENT_APPS_WAN_CONS] = { + true, IPA_v4_0_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 11, 6, 9, 9, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_0][IPA_CLIENT_ODU_EMB_CONS] = { + true, IPA_v4_0_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 17, 1, 17, 17, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_0][IPA_CLIENT_ETHERNET_CONS] = { + true, IPA_v4_0_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 22, 1, 17, 17, IPA_EE_UC }, IPA_TX_INSTANCE_NA }, + [IPA_4_0][IPA_CLIENT_Q6_LAN_CONS] = { + true, IPA_v4_0_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 14, 4, 9, 9, IPA_EE_Q6 }, IPA_TX_INSTANCE_NA }, + [IPA_4_0][IPA_CLIENT_Q6_WAN_CONS] = { + true, IPA_v4_0_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 13, 3, 9, 9, IPA_EE_Q6 }, IPA_TX_INSTANCE_NA }, + [IPA_4_0][IPA_CLIENT_Q6_LTE_WIFI_AGGR_CONS] = { + true, IPA_v4_0_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 16, 5, 9, 9, IPA_EE_Q6 }, IPA_TX_INSTANCE_NA }, + /* Only for test purpose */ + /* MBIM aggregation test pipes should have the same QMB as USB_CONS */ + [IPA_4_0][IPA_CLIENT_TEST_CONS] = { + true, IPA_v4_0_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 11, 6, 9, 9, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_0][IPA_CLIENT_TEST1_CONS] = { + true, IPA_v4_0_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 11, 6, 9, 9, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_0][IPA_CLIENT_TEST2_CONS] = { + true, IPA_v4_0_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 12, 2, 5, 5, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_0][IPA_CLIENT_TEST3_CONS] = { + true, IPA_v4_0_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 19, 12, 9, 9, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_0][IPA_CLIENT_TEST4_CONS] = { + true, IPA_v4_0_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 21, 14, 9, 9, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + /* Dummy consumer (pipe 31) is used in L2TP rt rule */ + [IPA_4_0][IPA_CLIENT_DUMMY_CONS] = { + true, IPA_v4_0_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 31, 31, 8, 8, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + + /* IPA_4_0_MHI */ + [IPA_4_0_MHI][IPA_CLIENT_APPS_WAN_PROD] = { + true, IPA_v4_0_MHI_GROUP_DDR, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 2, 3, 16, 32, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_0_MHI][IPA_CLIENT_APPS_CMD_PROD] = { + true, IPA_v4_0_MHI_GROUP_DDR, + false, + IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY, + QMB_MASTER_SELECT_DDR, + { 5, 4, 20, 24, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_0_MHI][IPA_CLIENT_MHI_PROD] = { + true, IPA_v4_0_MHI_GROUP_PCIE, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_PCIE, + { 1, 0, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_0_MHI][IPA_CLIENT_Q6_WAN_PROD] = { + true, IPA_v4_0_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 3, 0, 16, 32, IPA_EE_Q6 }, IPA_TX_INSTANCE_NA }, + [IPA_4_0_MHI][IPA_CLIENT_Q6_CMD_PROD] = { + true, IPA_v4_0_MHI_GROUP_PCIE, + false, + IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 4, 1, 20, 24, IPA_EE_Q6 }, IPA_TX_INSTANCE_NA }, + [IPA_4_0_MHI][IPA_CLIENT_MEMCPY_DMA_SYNC_PROD] = { + true, IPA_v4_0_MHI_GROUP_DMA, + false, + IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY, + QMB_MASTER_SELECT_DDR, + { 7, 9, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_0_MHI][IPA_CLIENT_MEMCPY_DMA_ASYNC_PROD] = { + true, IPA_v4_0_MHI_GROUP_DMA, + false, + IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY, + QMB_MASTER_SELECT_DDR, + { 8, 10, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + /* Only for test purpose */ + [IPA_4_0_MHI][IPA_CLIENT_TEST_PROD] = { + true, IPA_v4_0_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + {0, 8, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_0][IPA_CLIENT_TEST1_PROD] = { + true, IPA_v4_0_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + {0, 8, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_0_MHI][IPA_CLIENT_TEST2_PROD] = { + true, IPA_v4_0_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 1, 0, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_0_MHI][IPA_CLIENT_TEST3_PROD] = { + true, IPA_v4_0_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 7, 9, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_0_MHI][IPA_CLIENT_TEST4_PROD] = { + true, IPA_v4_0_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 8, 10, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_0_MHI][IPA_CLIENT_APPS_LAN_CONS] = { + true, IPA_v4_0_MHI_GROUP_DDR, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 10, 5, 9, 9, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_0_MHI][IPA_CLIENT_APPS_WAN_CONS] = { + true, IPA_v4_0_MHI_GROUP_DDR, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 11, 6, 9, 9, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_0_MHI][IPA_CLIENT_MHI_CONS] = { + true, IPA_v4_0_MHI_GROUP_PCIE, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_PCIE, + { 17, 1, 17, 17, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_0_MHI][IPA_CLIENT_Q6_LAN_CONS] = { + true, IPA_v4_0_MHI_GROUP_DDR, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 14, 4, 9, 9, IPA_EE_Q6 }, IPA_TX_INSTANCE_NA }, + [IPA_4_0_MHI][IPA_CLIENT_Q6_WAN_CONS] = { + true, IPA_v4_0_MHI_GROUP_DDR, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 13, 3, 9, 9, IPA_EE_Q6 }, IPA_TX_INSTANCE_NA }, + [IPA_4_0_MHI][IPA_CLIENT_MEMCPY_DMA_SYNC_CONS] = { + true, IPA_v4_0_MHI_GROUP_DMA, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_PCIE, + { 20, 13, 9, 9, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_0_MHI][IPA_CLIENT_MEMCPY_DMA_ASYNC_CONS] = { + true, IPA_v4_0_MHI_GROUP_DMA, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_PCIE, + { 21, 14, 9, 9, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_0_MHI][IPA_CLIENT_Q6_LTE_WIFI_AGGR_CONS] = { + true, IPA_v4_0_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 16, 5, 9, 9, IPA_EE_Q6 }, IPA_TX_INSTANCE_NA }, + [IPA_4_0_MHI][IPA_CLIENT_USB_DPL_CONS] = { + true, IPA_v4_0_MHI_GROUP_DDR, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 15, 7, 5, 5, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY }, IPA_TX_INSTANCE_NA }, + [IPA_4_0_MHI][IPA_CLIENT_MHI_DPL_CONS] = { + true, IPA_v4_0_MHI_GROUP_PCIE, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_PCIE, + { 12, 2, 5, 5, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY }, IPA_TX_INSTANCE_NA }, + /* Only for test purpose */ + [IPA_4_0_MHI][IPA_CLIENT_TEST_CONS] = { + true, IPA_v4_0_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_PCIE, + { 11, 6, 9, 9, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_0_MHI][IPA_CLIENT_TEST1_CONS] = { + true, IPA_v4_0_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_PCIE, + { 11, 6, 9, 9, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_0_MHI][IPA_CLIENT_TEST2_CONS] = { + true, IPA_v4_0_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 12, 2, 5, 5, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_0_MHI][IPA_CLIENT_TEST3_CONS] = { + true, IPA_v4_0_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_PCIE, + { 19, 12, 9, 9, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_0_MHI][IPA_CLIENT_TEST4_CONS] = { + true, IPA_v4_0_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_PCIE, + { 21, 14, 9, 9, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + /* Dummy consumer (pipe 31) is used in L2TP rt rule */ + [IPA_4_0_MHI][IPA_CLIENT_DUMMY_CONS] = { + true, IPA_v4_0_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 31, 31, 8, 8, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + /* IPA_4_1 */ + [IPA_4_1][IPA_CLIENT_WLAN1_PROD] = { + true, IPA_v4_0_GROUP_UL_DL, + true, + IPA_DPS_HPS_REP_SEQ_TYPE_2PKT_PROC_PASS_NO_DEC_UCP_DMAP, + QMB_MASTER_SELECT_DDR, + { 6, 2, 8, 16, IPA_EE_UC }, IPA_TX_INSTANCE_NA }, + [IPA_4_1][IPA_CLIENT_WLAN2_PROD] = { + true, IPA_v4_0_GROUP_UL_DL, + true, + IPA_DPS_HPS_REP_SEQ_TYPE_2PKT_PROC_PASS_NO_DEC_UCP_DMAP, + QMB_MASTER_SELECT_DDR, + { 7, 9, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_1][IPA_CLIENT_USB_PROD] = { + true, IPA_v4_0_GROUP_UL_DL, + true, + IPA_DPS_HPS_REP_SEQ_TYPE_2PKT_PROC_PASS_NO_DEC_UCP_DMAP, + QMB_MASTER_SELECT_DDR, + { 0, 8, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_1][IPA_CLIENT_APPS_LAN_PROD] = { + true, IPA_v4_0_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 8, 10, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_1][IPA_CLIENT_APPS_WAN_PROD] = { + true, IPA_v4_0_GROUP_UL_DL, + true, + IPA_DPS_HPS_REP_SEQ_TYPE_2PKT_PROC_PASS_NO_DEC_UCP_DMAP, + QMB_MASTER_SELECT_DDR, + { 2, 3, 16, 32, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_1][IPA_CLIENT_APPS_CMD_PROD] = { + true, IPA_v4_0_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY, + QMB_MASTER_SELECT_DDR, + { 5, 4, 20, 24, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_1][IPA_CLIENT_ODU_PROD] = { + true, IPA_v4_0_GROUP_UL_DL, + true, + IPA_DPS_HPS_REP_SEQ_TYPE_2PKT_PROC_PASS_NO_DEC_UCP_DMAP, + QMB_MASTER_SELECT_DDR, + { 1, 0, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_1][IPA_CLIENT_ETHERNET_PROD] = { + true, IPA_v4_0_GROUP_UL_DL, + true, + IPA_DPS_HPS_REP_SEQ_TYPE_2PKT_PROC_PASS_NO_DEC_UCP_DMAP, + QMB_MASTER_SELECT_DDR, + { 9, 0, 8, 16, IPA_EE_UC }, IPA_TX_INSTANCE_NA }, + [IPA_4_1][IPA_CLIENT_Q6_WAN_PROD] = { + true, IPA_v4_0_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 3, 0, 16, 32, IPA_EE_Q6 }, IPA_TX_INSTANCE_NA }, + [IPA_4_1][IPA_CLIENT_Q6_CMD_PROD] = { + true, IPA_v4_0_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 4, 1, 20, 24, IPA_EE_Q6 }, IPA_TX_INSTANCE_NA }, + /* Only for test purpose */ + [IPA_4_1][IPA_CLIENT_TEST_PROD] = { + true, IPA_v4_0_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + {0, 8, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_1][IPA_CLIENT_TEST1_PROD] = { + true, IPA_v4_0_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 0, 8, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_1][IPA_CLIENT_TEST2_PROD] = { + true, IPA_v4_0_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 1, 0, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_1][IPA_CLIENT_TEST3_PROD] = { + true, IPA_v4_0_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + {7, 9, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_1][IPA_CLIENT_TEST4_PROD] = { + true, IPA_v4_0_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 8, 10, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + + + [IPA_4_1][IPA_CLIENT_WLAN1_CONS] = { + true, IPA_v4_0_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 18, 3, 9, 9, IPA_EE_UC }, IPA_TX_INSTANCE_NA }, + [IPA_4_1][IPA_CLIENT_WLAN2_CONS] = { + true, IPA_v4_0_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 17, 1, 8, 13, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_1][IPA_CLIENT_WLAN3_CONS] = { + true, IPA_v4_0_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 21, 14, 9, 9, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_1][IPA_CLIENT_USB_CONS] = { + true, IPA_v4_0_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 19, 12, 9, 9, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_1][IPA_CLIENT_USB_DPL_CONS] = { + true, IPA_v4_0_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 15, 7, 5, 5, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_1][IPA_CLIENT_APPS_LAN_CONS] = { + true, IPA_v4_0_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 10, 5, 9, 9, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_1][IPA_CLIENT_APPS_WAN_CONS] = { + true, IPA_v4_0_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 11, 6, 9, 9, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_1][IPA_CLIENT_ODL_DPL_CONS] = { + true, IPA_v4_0_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 12, 2, 9, 9, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_1][IPA_CLIENT_ETHERNET_CONS] = { + true, IPA_v4_0_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 22, 1, 9, 9, IPA_EE_UC }, IPA_TX_INSTANCE_NA }, + [IPA_4_1][IPA_CLIENT_Q6_LAN_CONS] = { + true, IPA_v4_0_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 14, 4, 9, 9, IPA_EE_Q6 }, IPA_TX_INSTANCE_NA }, + [IPA_4_1][IPA_CLIENT_Q6_WAN_CONS] = { + true, IPA_v4_0_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 13, 3, 9, 9, IPA_EE_Q6 }, IPA_TX_INSTANCE_NA }, + [IPA_4_1][IPA_CLIENT_Q6_LTE_WIFI_AGGR_CONS] = { + true, IPA_v4_0_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 16, 5, 9, 9, IPA_EE_Q6 }, IPA_TX_INSTANCE_NA }, + /* Only for test purpose */ + /* MBIM aggregation test pipes should have the same QMB as USB_CONS */ + [IPA_4_1][IPA_CLIENT_TEST_CONS] = { + true, IPA_v4_0_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 11, 6, 9, 9, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_1][IPA_CLIENT_TEST1_CONS] = { + true, IPA_v4_0_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 11, 6, 9, 9, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_1][IPA_CLIENT_TEST2_CONS] = { + true, IPA_v4_0_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 12, 2, 9, 9, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_1][IPA_CLIENT_TEST3_CONS] = { + true, IPA_v4_0_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 19, 12, 9, 9, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_1][IPA_CLIENT_TEST4_CONS] = { + true, IPA_v4_0_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 21, 14, 9, 9, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + /* Dummy consumer (pipe 31) is used in L2TP rt rule */ + [IPA_4_1][IPA_CLIENT_DUMMY_CONS] = { + true, IPA_v4_0_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 31, 31, 8, 8, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + + /* MHI PRIME PIPES - Client producer / IPA Consumer pipes */ + [IPA_4_1_APQ][IPA_CLIENT_MHI_PRIME_DPL_PROD] = { + true, IPA_v4_0_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY, + QMB_MASTER_SELECT_DDR, + {7, 9, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_1_APQ][IPA_CLIENT_MHI_PRIME_TETH_PROD] = { + true, IPA_v4_0_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 1, 0, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_1_APQ][IPA_CLIENT_MHI_PRIME_RMNET_PROD] = { + true, IPA_v4_0_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY, + QMB_MASTER_SELECT_DDR, + { 2, 3, 16, 32, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + /* MHI PRIME PIPES - Client Consumer / IPA Producer pipes */ + [IPA_4_1_APQ][IPA_CLIENT_MHI_PRIME_TETH_CONS] = { + true, IPA_v4_0_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 20, 13, 9, 9, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_1_APQ][IPA_CLIENT_MHI_PRIME_RMNET_CONS] = { + true, IPA_v4_0_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 17, 14, 9, 9, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + + /* IPA_4_2 */ + [IPA_4_2][IPA_CLIENT_WLAN1_PROD] = { + true, IPA_v4_2_GROUP_UL_DL, + true, + IPA_DPS_HPS_REP_SEQ_TYPE_PKT_PROCESS_NO_DEC_NO_UCP_DMAP, + QMB_MASTER_SELECT_DDR, + { 3, 7, 6, 7, IPA_EE_AP, GSI_USE_PREFETCH_BUFS}, IPA_TX_INSTANCE_NA }, + [IPA_4_2][IPA_CLIENT_USB_PROD] = { + true, IPA_v4_2_GROUP_UL_DL, + true, + IPA_DPS_HPS_REP_SEQ_TYPE_PKT_PROCESS_NO_DEC_NO_UCP_DMAP, + QMB_MASTER_SELECT_DDR, + { 0, 5, 8, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY}, IPA_TX_INSTANCE_NA }, + [IPA_4_2][IPA_CLIENT_APPS_LAN_PROD] = { + true, IPA_v4_2_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_NO_UCP, + QMB_MASTER_SELECT_DDR, + { 2, 6, 8, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY}, IPA_TX_INSTANCE_NA }, + [IPA_4_2][IPA_CLIENT_APPS_WAN_PROD] = { + true, IPA_v4_2_GROUP_UL_DL, + true, + IPA_DPS_HPS_REP_SEQ_TYPE_PKT_PROCESS_NO_DEC_NO_UCP_DMAP, + QMB_MASTER_SELECT_DDR, + { 1, 0, 8, 12, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY}, IPA_TX_INSTANCE_NA }, + [IPA_4_2][IPA_CLIENT_APPS_CMD_PROD] = { + true, IPA_v4_2_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY, + QMB_MASTER_SELECT_DDR, + { 6, 1, 20, 20, IPA_EE_AP, GSI_USE_PREFETCH_BUFS}, IPA_TX_INSTANCE_NA }, + [IPA_4_2][IPA_CLIENT_Q6_WAN_PROD] = { + true, IPA_v4_2_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_NO_UCP, + QMB_MASTER_SELECT_DDR, + { 4, 0, 8, 12, IPA_EE_Q6, GSI_USE_PREFETCH_BUFS}, IPA_TX_INSTANCE_NA }, + [IPA_4_2][IPA_CLIENT_Q6_CMD_PROD] = { + true, IPA_v4_2_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_NO_UCP, + QMB_MASTER_SELECT_DDR, + { 5, 1, 20, 20, IPA_EE_Q6, GSI_USE_PREFETCH_BUFS}, IPA_TX_INSTANCE_NA }, + [IPA_4_2][IPA_CLIENT_ETHERNET_PROD] = { + true, IPA_v4_2_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_NO_UCP, + QMB_MASTER_SELECT_DDR, + { 7, 0, 8, 10, IPA_EE_UC, GSI_USE_PREFETCH_BUFS}, IPA_TX_INSTANCE_NA }, + /* Only for test purpose */ + [IPA_4_2][IPA_CLIENT_TEST_PROD] = { + true, IPA_v4_2_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_NO_UCP, + QMB_MASTER_SELECT_DDR, + {0, 5, 8, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY}, IPA_TX_INSTANCE_NA }, + [IPA_4_2][IPA_CLIENT_TEST1_PROD] = { + true, IPA_v4_2_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_NO_UCP, + QMB_MASTER_SELECT_DDR, + { 0, 5, 8, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY}, IPA_TX_INSTANCE_NA }, + [IPA_4_2][IPA_CLIENT_TEST2_PROD] = { + true, IPA_v4_2_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_NO_UCP, + QMB_MASTER_SELECT_DDR, + { 3, 7, 6, 7, IPA_EE_AP, GSI_USE_PREFETCH_BUFS}, IPA_TX_INSTANCE_NA }, + [IPA_4_2][IPA_CLIENT_TEST3_PROD] = { + true, IPA_v4_2_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_NO_UCP, + QMB_MASTER_SELECT_DDR, + {1, 0, 8, 12, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY}, IPA_TX_INSTANCE_NA }, + [IPA_4_2][IPA_CLIENT_TEST4_PROD] = { + true, IPA_v4_2_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_NO_UCP, + QMB_MASTER_SELECT_DDR, + { 7, 0, 8, 10, IPA_EE_AP, GSI_USE_PREFETCH_BUFS}, IPA_TX_INSTANCE_NA }, + + + [IPA_4_2][IPA_CLIENT_WLAN1_CONS] = { + true, IPA_v4_2_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 14, 8, 6, 9, IPA_EE_AP, GSI_USE_PREFETCH_BUFS}, IPA_TX_INSTANCE_NA }, + [IPA_4_2][IPA_CLIENT_USB_CONS] = { + true, IPA_v4_2_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 15, 9, 6, 6, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY}, IPA_TX_INSTANCE_NA }, + [IPA_4_2][IPA_CLIENT_USB_DPL_CONS] = { + true, IPA_v4_2_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 12, 4, 4, 4, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY}, IPA_TX_INSTANCE_NA }, + [IPA_4_2][IPA_CLIENT_APPS_LAN_CONS] = { + true, IPA_v4_2_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 8, 2, 6, 6, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY}, IPA_TX_INSTANCE_NA }, + [IPA_4_2][IPA_CLIENT_APPS_WAN_CONS] = { + true, IPA_v4_2_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 9, 3, 6, 6, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY}, IPA_TX_INSTANCE_NA }, + [IPA_4_2][IPA_CLIENT_Q6_LAN_CONS] = { + true, IPA_v4_2_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 11, 3, 6, 6, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY}, IPA_TX_INSTANCE_NA }, + [IPA_4_2][IPA_CLIENT_Q6_WAN_CONS] = { + true, IPA_v4_2_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 10, 2, 6, 6, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY}, IPA_TX_INSTANCE_NA }, + [IPA_4_2][IPA_CLIENT_Q6_LTE_WIFI_AGGR_CONS] = { + true, IPA_v4_2_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 13, 4, 6, 6, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY}, IPA_TX_INSTANCE_NA }, + [IPA_4_2][IPA_CLIENT_ETHERNET_CONS] = { + true, IPA_v4_2_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 16, 1, 6, 6, IPA_EE_UC, GSI_USE_PREFETCH_BUFS}, IPA_TX_INSTANCE_NA }, + /* Only for test purpose */ + /* MBIM aggregation test pipes should have the same QMB as USB_CONS */ + [IPA_4_2][IPA_CLIENT_TEST_CONS] = { + true, IPA_v4_2_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 15, 9, 6, 6, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY}, IPA_TX_INSTANCE_NA }, + [IPA_4_2][IPA_CLIENT_TEST1_CONS] = { + true, IPA_v4_2_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 15, 9, 6, 6, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY}, IPA_TX_INSTANCE_NA }, + [IPA_4_2][IPA_CLIENT_TEST2_CONS] = { + true, IPA_v4_2_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 12, 4, 4, 4, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY}, IPA_TX_INSTANCE_NA }, + [IPA_4_2][IPA_CLIENT_TEST3_CONS] = { + true, IPA_v4_2_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 14, 8, 6, 9, IPA_EE_AP, GSI_USE_PREFETCH_BUFS}, IPA_TX_INSTANCE_NA }, + [IPA_4_2][IPA_CLIENT_TEST4_CONS] = { + true, IPA_v4_2_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 9, 3, 6, 6, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY}, IPA_TX_INSTANCE_NA }, + /* Dummy consumer (pipe 31) is used in L2TP rt rule */ + [IPA_4_2][IPA_CLIENT_DUMMY_CONS] = { + true, IPA_v4_2_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 31, 31, 8, 8, IPA_EE_AP, GSI_USE_PREFETCH_BUFS}, IPA_TX_INSTANCE_NA }, + + /* IPA_4_5 */ + [IPA_4_5][IPA_CLIENT_WLAN2_PROD] = { + true, IPA_v4_5_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 9, 12, 8, 16, IPA_EE_AP, GSI_FREE_PRE_FETCH, 2 }, IPA_TX_INSTANCE_NA }, + [IPA_4_5][IPA_CLIENT_USB_PROD] = { + true, IPA_v4_5_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 1, 0, 8, 16, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 }, IPA_TX_INSTANCE_NA }, + [IPA_4_5][IPA_CLIENT_APPS_LAN_PROD] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 11, 14, 10, 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 2 }, IPA_TX_INSTANCE_NA }, + [IPA_4_5][IPA_CLIENT_APPS_WAN_PROD] = { + true, IPA_v4_5_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 2, 7, 16, 32, IPA_EE_AP, GSI_SMART_PRE_FETCH, 7 }, IPA_TX_INSTANCE_NA }, + [IPA_4_5][IPA_CLIENT_APPS_CMD_PROD] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY, + QMB_MASTER_SELECT_DDR, + { 7, 9, 20, 24, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 }, IPA_TX_INSTANCE_NA }, + [IPA_4_5][IPA_CLIENT_ODU_PROD] = { + true, IPA_v4_5_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 3, 5, 8, 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, IPA_TX_INSTANCE_NA }, + [IPA_4_5][IPA_CLIENT_ETHERNET_PROD] = { + true, IPA_v4_5_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 12, 0, 8, 16, IPA_EE_UC, GSI_SMART_PRE_FETCH, 3 }, IPA_TX_INSTANCE_NA }, + [IPA_4_5][IPA_CLIENT_Q6_WAN_PROD] = { + true, IPA_v4_5_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 5, 0, 16, 28, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 2 }, IPA_TX_INSTANCE_NA }, + [IPA_4_5][IPA_CLIENT_Q6_CMD_PROD] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 6, 1, 20, 24, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0 }, IPA_TX_INSTANCE_NA }, + [IPA_4_5][IPA_CLIENT_Q6_DL_NLO_DATA_PROD] = { + true, IPA_v4_5_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 8, 2, 27, 32, IPA_EE_Q6, GSI_FREE_PRE_FETCH, 3 }, IPA_TX_INSTANCE_NA }, + [IPA_4_5][IPA_CLIENT_RTK_ETHERNET_PROD] = { + true, IPA_v4_5_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 10, 13, 8, 16, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 }, IPA_TX_INSTANCE_NA }, + /* Only for test purpose */ + [IPA_4_5][IPA_CLIENT_TEST_PROD] = { + true, IPA_v4_5_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 1, 0, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_5][IPA_CLIENT_TEST1_PROD] = { + true, IPA_v4_5_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 1, 0, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_5][IPA_CLIENT_TEST2_PROD] = { + true, IPA_v4_5_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 3, 5, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_5][IPA_CLIENT_TEST3_PROD] = { + true, IPA_v4_5_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 9, 12, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_5][IPA_CLIENT_TEST4_PROD] = { + true, IPA_v4_5_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 11, 14, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_5][IPA_CLIENT_WLAN2_CONS] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 24, 3, 8, 14, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, IPA_TX_INSTANCE_NA }, + [IPA_4_5][IPA_CLIENT_WLAN2_CONS1] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 27, 18, 8, 14, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, IPA_TX_INSTANCE_NA}, + [IPA_4_5][IPA_CLIENT_USB_CONS] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 26, 17, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 }, IPA_TX_INSTANCE_NA }, + [IPA_4_5][IPA_CLIENT_USB_DPL_CONS] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 15, 15, 5, 5, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 }, IPA_TX_INSTANCE_NA }, + [IPA_4_5][IPA_CLIENT_ODL_DPL_CONS] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 22, 2, 5, 5, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 }, IPA_TX_INSTANCE_NA }, + [IPA_4_5][IPA_CLIENT_APPS_LAN_CONS] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 16, 10, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 }, IPA_TX_INSTANCE_NA }, + [IPA_4_5][IPA_CLIENT_APPS_WAN_COAL_CONS] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 13, 4, 8, 11, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, IPA_TX_INSTANCE_NA }, + [IPA_4_5][IPA_CLIENT_APPS_WAN_CONS] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 14, 1, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 }, IPA_TX_INSTANCE_NA }, + [IPA_4_5][IPA_CLIENT_ODU_EMB_CONS] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 30, 6, 9, 9, IPA_EE_AP, GSI_SMART_PRE_FETCH, 4 }, IPA_TX_INSTANCE_NA }, + [IPA_4_5][IPA_CLIENT_ETHERNET_CONS] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 28, 1, 9, 9, IPA_EE_UC, GSI_SMART_PRE_FETCH, 4 }, IPA_TX_INSTANCE_NA }, + [IPA_4_5][IPA_CLIENT_Q6_LAN_CONS] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 17, 3, 9, 9, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0 }, IPA_TX_INSTANCE_NA }, + [IPA_4_5][IPA_CLIENT_Q6_WAN_CONS] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 21, 7, 9, 9, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0 }, IPA_TX_INSTANCE_NA }, + [IPA_4_5][IPA_CLIENT_Q6_UL_NLO_DATA_CONS] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 19, 5, 5, 5, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 2 }, IPA_TX_INSTANCE_NA }, + [IPA_4_5][IPA_CLIENT_Q6_UL_NLO_ACK_CONS] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 20, 6, 5, 5, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 2 }, IPA_TX_INSTANCE_NA }, + [IPA_4_5][IPA_CLIENT_Q6_QBAP_STATUS_CONS] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 18, 4, 9, 9, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0 }, IPA_TX_INSTANCE_NA }, + [IPA_4_5][IPA_CLIENT_RTK_ETHERNET_CONS] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 23, 8, 9, 9, IPA_EE_AP, GSI_SMART_PRE_FETCH, 4 }, IPA_TX_INSTANCE_NA }, + /* Only for test purpose */ + /* MBIM aggregation test pipes should have the same QMB as USB_CONS */ + [IPA_4_5][IPA_CLIENT_TEST_CONS] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 14, 1, 9, 9, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_5][IPA_CLIENT_TEST1_CONS] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 14, 1, 9, 9, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_5][IPA_CLIENT_TEST2_CONS] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 24, 3, 8, 14, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_5][IPA_CLIENT_TEST3_CONS] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 26, 17, 9, 9, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_5][IPA_CLIENT_TEST4_CONS] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 27, 18, 9, 9, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + /* Dummy consumer (pipe 31) is used in L2TP rt rule */ + [IPA_4_5][IPA_CLIENT_DUMMY_CONS] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 31, 31, 8, 8, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_5][IPA_CLIENT_TPUT_CONS] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 25, 16, 9, 9, IPA_EE_AP, GSI_SMART_PRE_FETCH, 4 } }, + /* IPA_4_5_MHI */ + [IPA_4_5_MHI][IPA_CLIENT_APPS_CMD_PROD] = { + true, IPA_v4_5_MHI_GROUP_DDR, + false, + IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY, + QMB_MASTER_SELECT_DDR, + { 7, 9, 20, 24, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 }, IPA_TX_INSTANCE_NA }, + [IPA_4_5_MHI][IPA_CLIENT_Q6_WAN_PROD] = { + true, IPA_v4_5_MHI_GROUP_DDR, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 5, 0, 16, 28, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 2 }, IPA_TX_INSTANCE_NA }, + [IPA_4_5_MHI][IPA_CLIENT_Q6_CMD_PROD] = { + true, IPA_v4_5_MHI_GROUP_PCIE, + false, + IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 6, 1, 20, 24, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0 }, IPA_TX_INSTANCE_NA }, + [IPA_4_5_MHI][IPA_CLIENT_Q6_DL_NLO_DATA_PROD] = { + true, IPA_v4_5_MHI_GROUP_DDR, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 8, 2, 27, 32, IPA_EE_Q6, GSI_FREE_PRE_FETCH, 3 }, IPA_TX_INSTANCE_NA }, + [IPA_4_5_MHI][IPA_CLIENT_Q6_AUDIO_DMA_MHI_PROD] = { + true, IPA_v4_5_MHI_GROUP_DMA, + false, + IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY, + QMB_MASTER_SELECT_DDR, + { 4, 8, 8, 16, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 3 }, IPA_TX_INSTANCE_NA }, + [IPA_4_5_MHI][IPA_CLIENT_MHI_PROD] = { + true, IPA_v4_5_MHI_GROUP_PCIE, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_PCIE, + { 1, 0, 16, 20, IPA_EE_AP, GSI_SMART_PRE_FETCH, 7 }, IPA_TX_INSTANCE_NA }, + [IPA_4_5_MHI][IPA_CLIENT_MEMCPY_DMA_SYNC_PROD] = { + true, IPA_v4_5_MHI_GROUP_DMA, + false, + IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY, + QMB_MASTER_SELECT_DDR, + { 9, 12, 8, 16, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 }, IPA_TX_INSTANCE_NA }, + [IPA_4_5_MHI][IPA_CLIENT_MEMCPY_DMA_ASYNC_PROD] = { + true, IPA_v4_5_MHI_GROUP_DMA, + false, + IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY, + QMB_MASTER_SELECT_DDR, + { 10, 13, 8, 16, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 }, IPA_TX_INSTANCE_NA }, + [IPA_4_5_MHI][IPA_CLIENT_MHI_LOW_LAT_PROD] = { + true, IPA_v4_5_MHI_GROUP_PCIE, + false, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_PCIE, + { 3, 5, 8, 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, IPA_TX_INSTANCE_NA }, + [IPA_4_5_MHI][IPA_CLIENT_QDSS_PROD] = { + true, IPA_v4_5_MHI_GROUP_QDSS, + false, + IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY, + QMB_MASTER_SELECT_DDR, + { 11, 14, 10, 16, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 } }, + /* Only for test purpose */ + [IPA_4_5_MHI][IPA_CLIENT_TEST_PROD] = { + true, QMB_MASTER_SELECT_DDR, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 1, 0, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + + [IPA_4_5_MHI][IPA_CLIENT_APPS_LAN_CONS] = { + true, IPA_v4_5_MHI_GROUP_DDR, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 16, 10, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 }, IPA_TX_INSTANCE_NA }, + [IPA_4_5_MHI][IPA_CLIENT_USB_DPL_CONS] = { + true, IPA_v4_5_MHI_GROUP_DDR, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 15, 15, 5, 5, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 }, IPA_TX_INSTANCE_NA }, + [IPA_4_5_MHI][IPA_CLIENT_Q6_LAN_CONS] = { + true, IPA_v4_5_MHI_GROUP_DDR, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 17, 3, 9, 9, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0 }, IPA_TX_INSTANCE_NA }, + [IPA_4_5_MHI][IPA_CLIENT_Q6_WAN_CONS] = { + true, IPA_v4_5_MHI_GROUP_DDR, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 21, 7, 9, 9, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0 }, IPA_TX_INSTANCE_NA }, + [IPA_4_5_MHI][IPA_CLIENT_Q6_UL_NLO_DATA_CONS] = { + true, IPA_v4_5_MHI_GROUP_DDR, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 19, 5, 5, 5, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 2 }, IPA_TX_INSTANCE_NA }, + [IPA_4_5_MHI][IPA_CLIENT_Q6_UL_NLO_ACK_CONS] = { + true, IPA_v4_5_MHI_GROUP_DDR, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 20, 6, 5, 5, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 2 }, IPA_TX_INSTANCE_NA }, + [IPA_4_5_MHI][IPA_CLIENT_Q6_QBAP_STATUS_CONS] = { + true, IPA_v4_5_MHI_GROUP_DDR, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 18, 4, 9, 9, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0 }, IPA_TX_INSTANCE_NA }, + [IPA_4_5_MHI][IPA_CLIENT_Q6_AUDIO_DMA_MHI_CONS] = { + true, IPA_v4_5_MHI_GROUP_DMA, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_PCIE, + { 29, 9, 9, 9, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 4 }, IPA_TX_INSTANCE_NA }, + [IPA_4_5_MHI][IPA_CLIENT_MEMCPY_DMA_SYNC_CONS] = { + true, IPA_v4_5_MHI_GROUP_DMA, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_PCIE, + { 26, 17, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 }, IPA_TX_INSTANCE_NA }, + [IPA_4_5_MHI][IPA_CLIENT_MEMCPY_DMA_ASYNC_CONS] = { + true, IPA_v4_5_MHI_GROUP_DMA, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_PCIE, + { 27, 18, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 }, IPA_TX_INSTANCE_NA }, + [IPA_4_5_MHI][IPA_CLIENT_MHI_CONS] = { + true, IPA_v4_5_MHI_GROUP_PCIE, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_PCIE, + { 14, 1, 9, 9, IPA_EE_AP, GSI_SMART_PRE_FETCH, 4 }, IPA_TX_INSTANCE_NA }, + [IPA_4_5_MHI][IPA_CLIENT_MHI_DPL_CONS] = { + true, IPA_v4_5_MHI_GROUP_PCIE, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_PCIE, + { 22, 2, 5, 5, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 }, IPA_TX_INSTANCE_NA }, + [IPA_4_5_MHI][IPA_CLIENT_MHI_LOW_LAT_CONS] = { + true, IPA_v4_5_MHI_GROUP_PCIE, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_PCIE, + { 30, 6, 9, 9, IPA_EE_AP, GSI_SMART_PRE_FETCH, 4 }, IPA_TX_INSTANCE_NA }, + [IPA_4_5_MHI][IPA_CLIENT_MHI_QDSS_CONS] = { + true, IPA_v4_5_MHI_GROUP_QDSS, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_PCIE, + { 24, 3, 8, 14, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 } }, + /* Dummy consumer (pipe 31) is used in L2TP rt rule */ + [IPA_4_5_MHI][IPA_CLIENT_DUMMY_CONS] = { + true, QMB_MASTER_SELECT_DDR, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 31, 31, 8, 8, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + + /* IPA_4_5_AUTO */ + [IPA_4_5_AUTO][IPA_CLIENT_WLAN2_PROD] = { + false, IPA_v4_5_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 9, 12, 8, 16, IPA_EE_AP, GSI_FREE_PRE_FETCH, 2 } }, + [IPA_4_5_AUTO][IPA_CLIENT_WLAN1_PROD] = { + false, IPA_v4_5_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 9, 12, 8, 16, IPA_EE_AP, GSI_FREE_PRE_FETCH, 2 } }, + [IPA_4_5_AUTO][IPA_CLIENT_USB_PROD] = { + true, IPA_v4_5_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 1, 0, 8, 16, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 } }, + [IPA_4_5_AUTO][IPA_CLIENT_APPS_LAN_PROD] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 11, 14, 10, 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 2 } }, + [IPA_4_5_AUTO][IPA_CLIENT_APPS_WAN_PROD] = { + true, IPA_v4_5_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 2, 7, 16, 32, IPA_EE_AP, GSI_SMART_PRE_FETCH, 7 } }, + [IPA_4_5_AUTO][IPA_CLIENT_APPS_CMD_PROD] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY, + QMB_MASTER_SELECT_DDR, + { 7, 9, 20, 24, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 } }, + [IPA_4_5_AUTO][IPA_CLIENT_USB2_PROD] = { + true, IPA_v4_5_GROUP_CV2X, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 3, 5, 8, 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 } }, + [IPA_4_5_AUTO][IPA_CLIENT_ETHERNET_PROD] = { + true, IPA_v4_5_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 12, 0, 8, 16, IPA_EE_UC, GSI_SMART_PRE_FETCH, 3 } }, + [IPA_4_5_AUTO][IPA_CLIENT_ETHERNET2_PROD] = { + true, IPA_v4_5_GROUP_CV2X, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 10, 13, 8, 16, IPA_EE_UC, GSI_SMART_PRE_FETCH, 3 } }, + [IPA_4_5_AUTO][IPA_CLIENT_Q6_WAN_PROD] = { + true, IPA_v4_5_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 5, 0, 16, 28, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 2 } }, + [IPA_4_5_AUTO][IPA_CLIENT_Q6_CMD_PROD] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 6, 1, 20, 24, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0 } }, + [IPA_4_5_AUTO][IPA_CLIENT_Q6_DL_NLO_DATA_PROD] = { + true, IPA_v4_5_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 8, 2, 27, 32, IPA_EE_Q6, GSI_FREE_PRE_FETCH, 3 } }, + [IPA_4_5_AUTO][IPA_CLIENT_Q6_CV2X_PROD] = { + true, IPA_v4_5_GROUP_CV2X, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 4, 8, 4, 8, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 2 } }, + [IPA_4_5_AUTO][IPA_CLIENT_AQC_ETHERNET_PROD] = { + false, IPA_v4_5_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 10, 13, 8, 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 } }, + /* Only for test purpose */ + [IPA_4_5_AUTO][IPA_CLIENT_TEST_PROD] = { + true, IPA_v4_5_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 1, 0, 8, 16, IPA_EE_AP } }, + [IPA_4_5_AUTO][IPA_CLIENT_TEST1_PROD] = { + true, IPA_v4_5_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 1, 0, 8, 16, IPA_EE_AP } }, + [IPA_4_5_AUTO][IPA_CLIENT_TEST2_PROD] = { + true, IPA_v4_5_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 3, 5, 8, 16, IPA_EE_AP } }, + [IPA_4_5_AUTO][IPA_CLIENT_TEST3_PROD] = { + true, IPA_v4_5_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 9, 12, 8, 16, IPA_EE_AP } }, + [IPA_4_5_AUTO][IPA_CLIENT_TEST4_PROD] = { + true, IPA_v4_5_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 11, 14, 8, 16, IPA_EE_AP } }, + + [IPA_4_5_AUTO][IPA_CLIENT_WLAN2_CONS] = { + false, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 24, 18, 8, 14, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 } }, + [IPA_4_5_AUTO][IPA_CLIENT_WLAN1_CONS] = { + false, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 24, 18, 8, 14, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 } }, + [IPA_4_5_AUTO][IPA_CLIENT_USB_CONS] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 26, 3, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 } }, + [IPA_4_5_AUTO][IPA_CLIENT_USB_DPL_CONS] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 15, 15, 5, 5, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 } }, + [IPA_4_5_AUTO][IPA_CLIENT_ODL_DPL_CONS] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 22, 2, 5, 5, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 } }, + [IPA_4_5_AUTO][IPA_CLIENT_APPS_LAN_CONS] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 16, 10, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 } }, + [IPA_4_5_AUTO][IPA_CLIENT_APPS_WAN_CONS] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 14, 1, 9, 9, IPA_EE_AP, GSI_SMART_PRE_FETCH, 4 } }, + [IPA_4_5_AUTO][IPA_CLIENT_USB2_CONS] = { + true, IPA_v4_5_GROUP_CV2X, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 30, 6, 9, 9, IPA_EE_AP, GSI_SMART_PRE_FETCH, 4 } }, + [IPA_4_5_AUTO][IPA_CLIENT_ETHERNET_CONS] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 28, 1, 9, 9, IPA_EE_UC, GSI_SMART_PRE_FETCH, 4 } }, + [IPA_4_5_AUTO][IPA_CLIENT_ETHERNET2_CONS] = { + true, IPA_v4_5_GROUP_CV2X, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 25, 16, 9, 9, IPA_EE_UC, GSI_SMART_PRE_FETCH, 4 } }, + [IPA_4_5_AUTO][IPA_CLIENT_Q6_LAN_CONS] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 17, 3, 9, 9, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0 } }, + [IPA_4_5_AUTO][IPA_CLIENT_Q6_CV2X_CONS] = { + true, IPA_v4_5_GROUP_CV2X, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 29, 9, 9, 9, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 4 } }, + [IPA_4_5_AUTO][IPA_CLIENT_Q6_WAN_CONS] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 21, 7, 9, 9, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0 } }, + [IPA_4_5_AUTO][IPA_CLIENT_Q6_UL_NLO_DATA_CONS] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 19, 5, 5, 5, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 2 } }, + [IPA_4_5_AUTO][IPA_CLIENT_Q6_UL_NLO_ACK_CONS] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 20, 6, 5, 5, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 2 } }, + [IPA_4_5_AUTO][IPA_CLIENT_Q6_QBAP_STATUS_CONS] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 18, 4, 9, 9, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0 } }, + [IPA_4_5_AUTO][IPA_CLIENT_AQC_ETHERNET_CONS] = { + false, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 23, 17, 9, 9, IPA_EE_AP, GSI_SMART_PRE_FETCH, 4 } }, + /* Only for test purpose */ + /* MBIM aggregation test pipes should have the same QMB as USB_CONS */ + [IPA_4_5_AUTO][IPA_CLIENT_TEST_CONS] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 14, 1, 9, 9, IPA_EE_AP } }, + [IPA_4_5_AUTO][IPA_CLIENT_TEST1_CONS] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 14, 1, 9, 9, IPA_EE_AP } }, + [IPA_4_5_AUTO][IPA_CLIENT_TEST2_CONS] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 24, 3, 8, 14, IPA_EE_AP } }, + [IPA_4_5_AUTO][IPA_CLIENT_TEST3_CONS] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 26, 17, 9, 9, IPA_EE_AP } }, + [IPA_4_5_AUTO][IPA_CLIENT_TEST4_CONS] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 27, 18, 9, 9, IPA_EE_AP } }, + /* Dummy consumer (pipe 31) is used in L2TP rt rule */ + [IPA_4_5_AUTO][IPA_CLIENT_DUMMY_CONS] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 31, 31, 8, 8, IPA_EE_AP } }, + + /* IPA_4_5_AUTO_MHI */ + [IPA_4_5_AUTO_MHI][IPA_CLIENT_APPS_CMD_PROD] = { + true, IPA_v4_5_MHI_GROUP_DDR, + false, + IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY, + QMB_MASTER_SELECT_DDR, + { 7, 9, 20, 24, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 } }, + [IPA_4_5_AUTO_MHI][IPA_CLIENT_APPS_LAN_PROD] = { + true, IPA_v4_5_MHI_GROUP_DDR, + false, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 11, 14, 10, 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 2 } }, + [IPA_4_5_AUTO_MHI][IPA_CLIENT_APPS_WAN_PROD] = { + true, IPA_v4_5_MHI_GROUP_DDR, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 2, 7, 16, 32, IPA_EE_AP, GSI_SMART_PRE_FETCH, 7 } }, + [IPA_4_5_AUTO_MHI][IPA_CLIENT_MHI2_PROD] = { + true, IPA_v4_5_GROUP_CV2X, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_PCIE, + { 3, 5, 8, 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 } }, + [IPA_4_5_AUTO_MHI][IPA_CLIENT_Q6_CV2X_PROD] = { + true, IPA_v4_5_GROUP_CV2X, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 4, 8, 10, 16, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 2 } }, + [IPA_4_5_AUTO_MHI][IPA_CLIENT_ETHERNET_PROD] = { + true, IPA_v4_5_MHI_GROUP_DDR, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 12, 0, 8, 16, IPA_EE_UC, GSI_SMART_PRE_FETCH, 3 } }, + [IPA_4_5_AUTO_MHI][IPA_CLIENT_Q6_WAN_PROD] = { + true, IPA_v4_5_MHI_GROUP_DDR, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 5, 0, 16, 28, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 2 } }, + [IPA_4_5_AUTO_MHI][IPA_CLIENT_USB_PROD] = { + true, IPA_v4_5_MHI_GROUP_DDR, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_DEC_UCP, + QMB_MASTER_SELECT_DDR, + {0, 11, 8, 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3} }, + [IPA_4_5_AUTO_MHI][IPA_CLIENT_Q6_CMD_PROD] = { + true, IPA_v4_5_MHI_GROUP_PCIE, + false, + IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 6, 1, 20, 24, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0 } }, + [IPA_4_5_AUTO_MHI][IPA_CLIENT_Q6_DL_NLO_DATA_PROD] = { + true, IPA_v4_5_MHI_GROUP_DDR, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 8, 2, 27, 32, IPA_EE_Q6, GSI_FREE_PRE_FETCH, 3 } }, + [IPA_4_5_AUTO_MHI][IPA_CLIENT_Q6_AUDIO_DMA_MHI_PROD] = { + true, IPA_v4_5_MHI_GROUP_DMA, + false, + IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY, + QMB_MASTER_SELECT_DDR, + { 4, 8, 8, 16, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 3 } }, + [IPA_4_5_AUTO_MHI][IPA_CLIENT_MHI_PROD] = { + true, IPA_v4_5_MHI_GROUP_PCIE, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_PCIE, + { 1, 0, 8, 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 7 } }, + [IPA_4_5_AUTO_MHI][IPA_CLIENT_MEMCPY_DMA_SYNC_PROD] = { + true, IPA_v4_5_MHI_GROUP_DMA, + false, + IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY, + QMB_MASTER_SELECT_DDR, + { 9, 12, 8, 16, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 } }, + [IPA_4_5_AUTO_MHI][IPA_CLIENT_MEMCPY_DMA_ASYNC_PROD] = { + true, IPA_v4_5_MHI_GROUP_DMA, + false, + IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY, + QMB_MASTER_SELECT_DDR, + { 10, 13, 8, 16, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 } }, + /* Only for test purpose */ + [IPA_4_5_AUTO_MHI][IPA_CLIENT_TEST_PROD] = { + true, QMB_MASTER_SELECT_DDR, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 1, 0, 8, 16, IPA_EE_AP } }, + + [IPA_4_5_AUTO_MHI][IPA_CLIENT_APPS_LAN_CONS] = { + true, IPA_v4_5_MHI_GROUP_DDR, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 16, 10, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 } }, + [IPA_4_5_AUTO_MHI][IPA_CLIENT_APPS_WAN_CONS] = { + true, IPA_v4_5_MHI_GROUP_DDR, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 25, 16, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 } }, + [IPA_4_5_AUTO_MHI][IPA_CLIENT_ETHERNET_CONS] = { + true, IPA_v4_5_MHI_GROUP_DDR, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 28, 1, 9, 9, IPA_EE_UC, GSI_SMART_PRE_FETCH, 4 } }, + [IPA_4_5_AUTO_MHI][IPA_CLIENT_USB_DPL_CONS] = { + true, IPA_v4_5_MHI_GROUP_DDR, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 15, 15, 5, 5, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 } }, + [IPA_4_5_AUTO_MHI][IPA_CLIENT_Q6_LAN_CONS] = { + true, IPA_v4_5_MHI_GROUP_DDR, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 17, 3, 9, 9, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0 } }, + [IPA_4_5_AUTO_MHI][IPA_CLIENT_Q6_CV2X_CONS] = { + true, IPA_v4_5_GROUP_CV2X, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_PCIE, + { 29, 9, 9, 9, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 4 } }, + [IPA_4_5_AUTO_MHI][IPA_CLIENT_MHI2_CONS] = { + true, IPA_v4_5_GROUP_CV2X, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_PCIE, + { 30, 6, 9, 9, IPA_EE_AP, GSI_SMART_PRE_FETCH, 4 } }, + [IPA_4_5_AUTO_MHI][IPA_CLIENT_Q6_WAN_CONS] = { + true, IPA_v4_5_MHI_GROUP_DDR, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 21, 7, 9, 9, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0 } }, + [IPA_4_5_AUTO_MHI][IPA_CLIENT_USB_CONS] = { + true, IPA_v4_5_MHI_GROUP_DDR, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + {13, 4, 9, 9, IPA_EE_AP, GSI_SMART_PRE_FETCH, 4} }, + [IPA_4_5_AUTO_MHI][IPA_CLIENT_Q6_UL_NLO_DATA_CONS] = { + true, IPA_v4_5_MHI_GROUP_DDR, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 19, 5, 5, 5, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 2 } }, + [IPA_4_5_AUTO_MHI][IPA_CLIENT_Q6_UL_NLO_ACK_CONS] = { + true, IPA_v4_5_MHI_GROUP_DDR, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 20, 6, 5, 5, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 2 } }, + [IPA_4_5_AUTO_MHI][IPA_CLIENT_Q6_QBAP_STATUS_CONS] = { + true, IPA_v4_5_MHI_GROUP_DDR, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 18, 4, 9, 9, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0 } }, + [IPA_4_5_AUTO_MHI][IPA_CLIENT_Q6_AUDIO_DMA_MHI_CONS] = { + true, IPA_v4_5_MHI_GROUP_DMA, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_PCIE, + { 29, 9, 9, 9, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 4 } }, + [IPA_4_5_AUTO_MHI][IPA_CLIENT_MEMCPY_DMA_SYNC_CONS] = { + true, IPA_v4_5_MHI_GROUP_DMA, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_PCIE, + { 23, 17, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 } }, + [IPA_4_5_AUTO_MHI][IPA_CLIENT_MEMCPY_DMA_ASYNC_CONS] = { + true, IPA_v4_5_MHI_GROUP_DMA, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_PCIE, + { 24, 18, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 } }, + [IPA_4_5_AUTO_MHI][IPA_CLIENT_MHI_CONS] = { + true, IPA_v4_5_MHI_GROUP_PCIE, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_PCIE, + { 14, 1, 9, 9, IPA_EE_AP, GSI_SMART_PRE_FETCH, 4 } }, + [IPA_4_5_AUTO_MHI][IPA_CLIENT_MHI_DPL_CONS] = { + true, IPA_v4_5_MHI_GROUP_PCIE, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_PCIE, + { 22, 2, 5, 5, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 } }, + + /* Dummy consumer (pipe 31) is used in L2TP rt rule */ + [IPA_4_5_AUTO_MHI][IPA_CLIENT_DUMMY_CONS] = { + true, QMB_MASTER_SELECT_DDR, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 31, 31, 8, 8, IPA_EE_AP } }, + + /* IPA_4_5 APQ */ + [IPA_4_5_APQ][IPA_CLIENT_WLAN2_PROD] = { + true, IPA_v4_5_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 9, 3, 8, 16, IPA_EE_AP, GSI_FREE_PRE_FETCH, 2 }, IPA_TX_INSTANCE_NA }, + [IPA_4_5_APQ][IPA_CLIENT_WIGIG_PROD] = { + true, IPA_v4_5_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 1, 1, 8, 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, IPA_TX_INSTANCE_NA }, + [IPA_4_5_APQ][IPA_CLIENT_USB_PROD] = { + true, IPA_v4_5_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 0, 0, 8, 16, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 }, IPA_TX_INSTANCE_NA }, + [IPA_4_5_APQ][IPA_CLIENT_APPS_LAN_PROD] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 11, 4, 8, 16, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 }, IPA_TX_INSTANCE_NA }, + [IPA_4_5_APQ][IPA_CLIENT_APPS_CMD_PROD] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY, + QMB_MASTER_SELECT_DDR, + { 7, 12, 20, 24, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 }, IPA_TX_INSTANCE_NA }, + /* MHI PRIME PIPES - Client producer / IPA Consumer pipes */ + [IPA_4_5_APQ][IPA_CLIENT_MHI_PRIME_DPL_PROD] = { + true, IPA_v4_5_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY, + QMB_MASTER_SELECT_DDR, + {3, 2, 8, 16, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 }, IPA_TX_INSTANCE_NA }, + [IPA_4_5_APQ][IPA_CLIENT_MHI_PRIME_TETH_PROD] = { + true, IPA_v4_5_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 2, 7, 8, 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, IPA_TX_INSTANCE_NA }, + [IPA_4_5_APQ][IPA_CLIENT_MHI_PRIME_RMNET_PROD] = { + true, IPA_v4_5_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY, + QMB_MASTER_SELECT_DDR, + { 4, 11, 16, 32, IPA_EE_AP, GSI_SMART_PRE_FETCH, 7 }, IPA_TX_INSTANCE_NA }, + /* Only for test purpose */ + [IPA_4_5_APQ][IPA_CLIENT_TEST_PROD] = { + true, IPA_v4_5_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 0, 0, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_5_APQ][IPA_CLIENT_TEST1_PROD] = { + true, IPA_v4_5_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 0, 0, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_5_APQ][IPA_CLIENT_TEST2_PROD] = { + true, IPA_v4_5_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 1, 1, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_5_APQ][IPA_CLIENT_TEST3_PROD] = { + true, IPA_v4_5_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 9, 3, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_5_APQ][IPA_CLIENT_TEST4_PROD] = { + true, IPA_v4_5_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 10, 10, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + + [IPA_4_5_APQ][IPA_CLIENT_WLAN2_CONS] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 23, 8, 8, 14, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, IPA_TX_INSTANCE_NA }, + [IPA_4_5_APQ][IPA_CLIENT_WIGIG1_CONS] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 14, 14, 8, 14, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, IPA_TX_INSTANCE_NA }, + [IPA_4_5_APQ][IPA_CLIENT_WIGIG2_CONS] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 20, 18, 8, 14, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, IPA_TX_INSTANCE_NA }, + [IPA_4_5_APQ][IPA_CLIENT_WIGIG3_CONS] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 22, 5, 8, 14, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, IPA_TX_INSTANCE_NA }, + [IPA_4_5_APQ][IPA_CLIENT_WIGIG4_CONS] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 29, 10, 8, 14, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, IPA_TX_INSTANCE_NA }, + [IPA_4_5_APQ][IPA_CLIENT_USB_CONS] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 24, 9, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 }, IPA_TX_INSTANCE_NA }, + [IPA_4_5_APQ][IPA_CLIENT_USB_DPL_CONS] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 16, 16, 5, 5, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 }, IPA_TX_INSTANCE_NA }, + [IPA_4_5_APQ][IPA_CLIENT_APPS_LAN_CONS] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 13, 13, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 }, IPA_TX_INSTANCE_NA }, + [IPA_4_5_APQ][IPA_CLIENT_ODL_DPL_CONS] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 21, 19, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 }, IPA_TX_INSTANCE_NA }, + /* MHI PRIME PIPES - Client Consumer / IPA Producer pipes */ + [IPA_4_5_APQ][IPA_CLIENT_MHI_PRIME_TETH_CONS] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 28, 6, 8, 9, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, IPA_TX_INSTANCE_NA }, + [IPA_4_5_APQ][IPA_CLIENT_MHI_PRIME_RMNET_CONS] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 17, 17, 8, 9, IPA_EE_AP, GSI_SMART_PRE_FETCH, 4 }, IPA_TX_INSTANCE_NA }, + /* Only for test purpose */ + /* MBIM aggregation test pipes should have the same QMB as USB_CONS */ + [IPA_4_5_APQ][IPA_CLIENT_TEST_CONS] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 16, 16, 5, 5, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_5_APQ][IPA_CLIENT_TEST1_CONS] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 16, 16, 5, 5, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_5_APQ][IPA_CLIENT_TEST2_CONS] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 22, 5, 9, 9, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_5_APQ][IPA_CLIENT_TEST3_CONS] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 24, 9, 9, 9, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_5_APQ][IPA_CLIENT_TEST4_CONS] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 23, 8, 8, 13, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + /* Dummy consumer (pipe 31) is used in L2TP rt rule */ + [IPA_4_5_APQ][IPA_CLIENT_DUMMY_CONS] = { + true, IPA_v4_5_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 31, 31, 8, 8, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + + /* IPA_4_7 */ + [IPA_4_7][IPA_CLIENT_WLAN1_PROD] = { + true, IPA_v4_7_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 3, 3, 8, 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, IPA_TX_INSTANCE_NA }, + [IPA_4_7][IPA_CLIENT_USB_PROD] = { + true, IPA_v4_7_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 0, 0, 8, 16, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 }, IPA_TX_INSTANCE_NA }, + [IPA_4_7][IPA_CLIENT_APPS_LAN_PROD] = { + true, IPA_v4_7_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 4, 4, 8, 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, IPA_TX_INSTANCE_NA }, + [IPA_4_7][IPA_CLIENT_APPS_WAN_PROD] = { + true, IPA_v4_7_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 2, 2, 16, 32, IPA_EE_AP, GSI_SMART_PRE_FETCH, 7 }, IPA_TX_INSTANCE_NA }, + [IPA_4_7][IPA_CLIENT_APPS_CMD_PROD] = { + true, IPA_v4_7_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY, + QMB_MASTER_SELECT_DDR, + { 7, 5, 20, 24, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 8 }, IPA_TX_INSTANCE_NA }, + [IPA_4_7][IPA_CLIENT_Q6_WAN_PROD] = { + true, IPA_v4_7_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 5, 0, 16, 28, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 2 }, IPA_TX_INSTANCE_NA }, + [IPA_4_7][IPA_CLIENT_Q6_CMD_PROD] = { + true, IPA_v4_7_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 6, 1, 20, 24, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 8 }, IPA_TX_INSTANCE_NA }, + [IPA_4_7][IPA_CLIENT_Q6_DL_NLO_DATA_PROD] = { + true, IPA_v4_7_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 8, 2, 27, 32, IPA_EE_Q6, GSI_FREE_PRE_FETCH, 3 }, IPA_TX_INSTANCE_NA }, + /* Only for test purpose */ + [IPA_4_7][IPA_CLIENT_TEST_PROD] = { + true, IPA_v4_7_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 0, 0, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_7][IPA_CLIENT_TEST1_PROD] = { + true, IPA_v4_7_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 0, 0, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_7][IPA_CLIENT_TEST2_PROD] = { + true, IPA_v4_7_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 1, 1, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_7][IPA_CLIENT_TEST3_PROD] = { + true, IPA_v4_7_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 2, 2, 16, 32, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_7][IPA_CLIENT_TEST4_PROD] = { + true, IPA_v4_7_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 1, 1, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + + [IPA_4_7][IPA_CLIENT_WLAN1_CONS] = { + true, IPA_v4_7_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 18, 9, 8, 13, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, IPA_TX_INSTANCE_NA }, + [IPA_4_7][IPA_CLIENT_USB_CONS] = { + true, IPA_v4_7_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 19, 10, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 }, IPA_TX_INSTANCE_NA }, + [IPA_4_7][IPA_CLIENT_USB_DPL_CONS] = { + true, IPA_v4_7_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 17, 8, 5, 5, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 }, IPA_TX_INSTANCE_NA }, + [IPA_4_7][IPA_CLIENT_ODL_DPL_CONS] = { + true, IPA_v4_7_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 22, 13, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 }, IPA_TX_INSTANCE_NA }, + [IPA_4_7][IPA_CLIENT_APPS_LAN_CONS] = { + true, IPA_v4_7_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 9, 14, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 }, IPA_TX_INSTANCE_NA }, + [IPA_4_7][IPA_CLIENT_APPS_WAN_CONS] = { + true, IPA_v4_7_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 16, 7, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 }, IPA_TX_INSTANCE_NA }, + [IPA_4_7][IPA_CLIENT_APPS_WAN_COAL_CONS] = { + true, IPA_v4_7_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 15, 6, 8, 11, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, IPA_TX_INSTANCE_NA }, + [IPA_4_7][IPA_CLIENT_Q6_LAN_CONS] = { + true, IPA_v4_7_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 10, 3, 9, 9, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0 }, IPA_TX_INSTANCE_NA }, + [IPA_4_7][IPA_CLIENT_Q6_WAN_CONS] = { + true, IPA_v4_7_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 14, 7, 9, 9, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0 }, IPA_TX_INSTANCE_NA }, + [IPA_4_7][IPA_CLIENT_Q6_UL_NLO_DATA_CONS] = { + true, IPA_v4_7_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 12, 5, 5, 5, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 2 }, IPA_TX_INSTANCE_NA }, + [IPA_4_7][IPA_CLIENT_Q6_UL_NLO_ACK_CONS] = { + true, IPA_v4_7_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 13, 6, 5, 5, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 2 }, IPA_TX_INSTANCE_NA }, + [IPA_4_7][IPA_CLIENT_Q6_QBAP_STATUS_CONS] = { + true, IPA_v4_7_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 11, 4, 9, 9, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0 }, IPA_TX_INSTANCE_NA }, + /* Only for test purpose */ + /* MBIM aggregation test pipes should have the same QMB as USB_CONS */ + [IPA_4_7][IPA_CLIENT_TEST_CONS] = { + true, IPA_v4_7_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 16, 7, 9, 9, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_7][IPA_CLIENT_TEST1_CONS] = { + true, IPA_v4_7_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 16, 7, 9, 9, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_7][IPA_CLIENT_TEST2_CONS] = { + true, IPA_v4_7_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 21, 12, 9, 9, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_7][IPA_CLIENT_TEST3_CONS] = { + true, IPA_v4_7_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 19, 10, 9, 9, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_7][IPA_CLIENT_TEST4_CONS] = { + true, IPA_v4_7_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 20, 11, 9, 9, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + /* Dummy consumer (pipe 31) is used in L2TP rt rule */ + [IPA_4_7][IPA_CLIENT_DUMMY_CONS] = { + true, IPA_v4_7_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 31, 31, 8, 8, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + + /* IPA_4_9 */ + [IPA_4_9][IPA_CLIENT_USB_PROD] = { + true, IPA_v4_9_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 0, 0, 8, 16, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 }, IPA_TX_INSTANCE_NA }, + [IPA_4_9][IPA_CLIENT_APPS_WAN_PROD] = { + true, IPA_v4_9_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 2, 2, 16, 32, IPA_EE_AP, GSI_SMART_PRE_FETCH, 8 }, IPA_TX_INSTANCE_NA }, + [IPA_4_9][IPA_CLIENT_APPS_WAN_LOW_LAT_PROD] = { + true, IPA_v4_9_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY, + QMB_MASTER_SELECT_DDR, + { 1, 1, 4, 4, IPA_EE_AP, GSI_SMART_PRE_FETCH, 1 }, IPA_TX_INSTANCE_NA }, + [IPA_4_9][IPA_CLIENT_WLAN2_PROD] = { + true, IPA_v4_9_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 3, 3, 8, 16, IPA_EE_AP, GSI_FREE_PRE_FETCH, 2 }, IPA_TX_INSTANCE_NA }, + [IPA_4_9][IPA_CLIENT_APPS_LAN_PROD] = { + true, IPA_v4_9_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 4, 4, 10, 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 2 }, IPA_TX_INSTANCE_NA }, + [IPA_4_9][IPA_CLIENT_WIGIG_PROD] = { + true, IPA_v4_9_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 9, 5, 8, 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, IPA_TX_INSTANCE_NA }, + [IPA_4_9][IPA_CLIENT_APPS_CMD_PROD] = { + true, IPA_v4_9_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY, + QMB_MASTER_SELECT_DDR, + { 7, 6, 20, 24, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 }, IPA_TX_INSTANCE_NA }, + [IPA_4_9][IPA_CLIENT_Q6_WAN_PROD] = { + true, IPA_v4_9_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 5, 0, 16, 28, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 2 }, IPA_TX_INSTANCE_NA }, + [IPA_4_9][IPA_CLIENT_Q6_CMD_PROD] = { + true, IPA_v4_9_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 6, 1, 20, 24, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0 }, IPA_TX_INSTANCE_NA }, + [IPA_4_9][IPA_CLIENT_Q6_DL_NLO_DATA_PROD] = { + true, IPA_v4_9_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 8, 2, 27, 32, IPA_EE_Q6, GSI_FREE_PRE_FETCH, 3 }, IPA_TX_INSTANCE_NA }, + + + [IPA_4_9][IPA_CLIENT_APPS_WAN_COAL_CONS] = { + true, IPA_v4_9_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 19, 11, 8, 11, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, IPA_TX_INSTANCE_NA }, + [IPA_4_9][IPA_CLIENT_APPS_WAN_CONS] = { + true, IPA_v4_9_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 20, 12, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 }, IPA_TX_INSTANCE_NA }, + [IPA_4_9][IPA_CLIENT_APPS_WAN_LOW_LAT_CONS] = { + true, IPA_v4_9_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 17, 9, 6, 6, IPA_EE_AP, GSI_SMART_PRE_FETCH, 2 }, IPA_TX_INSTANCE_NA }, + [IPA_4_9][IPA_CLIENT_USB_DPL_CONS] = { + true, IPA_v4_9_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 21, 13, 5, 5, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 }, IPA_TX_INSTANCE_NA }, + [IPA_4_9][IPA_CLIENT_ODL_DPL_CONS] = { + true, IPA_v4_9_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 22, 14, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 }, IPA_TX_INSTANCE_NA }, + [IPA_4_9][IPA_CLIENT_WIGIG1_CONS] = { + true, IPA_v4_9_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 23, 15, 8, 14, IPA_EE_AP, GSI_SMART_PRE_FETCH, 2 }, IPA_TX_INSTANCE_NA }, + [IPA_4_9][IPA_CLIENT_WLAN2_CONS] = { + true, IPA_v4_9_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 24, 16, 8, 14, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, IPA_TX_INSTANCE_NA }, + [IPA_4_9][IPA_CLIENT_USB_CONS] = { + true, IPA_v4_9_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 25, 17, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 }, IPA_TX_INSTANCE_NA }, + [IPA_4_9][IPA_CLIENT_WIGIG2_CONS] = { + true, IPA_v4_9_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 26, 18, 8, 14, IPA_EE_AP, GSI_SMART_PRE_FETCH, 2 }, IPA_TX_INSTANCE_NA }, + [IPA_4_9][IPA_CLIENT_WIGIG3_CONS] = { + true, IPA_v4_9_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 27, 19, 8, 14, IPA_EE_AP, GSI_SMART_PRE_FETCH, 2 }, IPA_TX_INSTANCE_NA }, + [IPA_4_9][IPA_CLIENT_WIGIG4_CONS] = { + true, IPA_v4_9_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 28, 20, 8, 14, IPA_EE_AP, GSI_SMART_PRE_FETCH, 2 }, IPA_TX_INSTANCE_NA }, + [IPA_4_9][IPA_CLIENT_APPS_LAN_CONS] = { + true, IPA_v4_9_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 11, 7, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 }, IPA_TX_INSTANCE_NA }, + [IPA_4_9][IPA_CLIENT_Q6_LAN_CONS] = { + true, IPA_v4_9_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 12, 3, 9, 9, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0 }, IPA_TX_INSTANCE_NA }, + [IPA_4_9][IPA_CLIENT_Q6_QBAP_STATUS_CONS] = { + true, IPA_v4_9_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 13, 4, 9, 9, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0 }, IPA_TX_INSTANCE_NA }, + [IPA_4_9][IPA_CLIENT_Q6_UL_NLO_DATA_CONS] = { + true, IPA_v4_9_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 14, 5, 5, 5, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 2 }, IPA_TX_INSTANCE_NA }, + [IPA_4_9][IPA_CLIENT_Q6_UL_NLO_ACK_CONS] = { + true, IPA_v4_9_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 15, 6, 5, 5, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 2 }, IPA_TX_INSTANCE_NA }, + [IPA_4_9][IPA_CLIENT_Q6_WAN_CONS] = { + true, IPA_v4_9_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 16, 7, 9, 9, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0 }, IPA_TX_INSTANCE_NA }, + + /* IPA_4_11 */ + [IPA_4_11][IPA_CLIENT_WLAN1_PROD] = { + true, IPA_v4_11_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 3, 3, 8, 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, IPA_TX_INSTANCE_NA }, + [IPA_4_11][IPA_CLIENT_USB_PROD] = { + true, IPA_v4_11_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 0, 0, 8, 16, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 }, IPA_TX_INSTANCE_NA }, + [IPA_4_11][IPA_CLIENT_APPS_LAN_PROD] = { + true, IPA_v4_11_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 4, 4, 8, 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, IPA_TX_INSTANCE_NA }, + [IPA_4_11][IPA_CLIENT_APPS_WAN_PROD] = { + true, IPA_v4_11_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 2, 2, 16, 32, IPA_EE_AP, GSI_SMART_PRE_FETCH, 7 }, IPA_TX_INSTANCE_NA }, + [IPA_4_11][IPA_CLIENT_APPS_CMD_PROD] = { + true, IPA_v4_11_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY, + QMB_MASTER_SELECT_DDR, + { 7, 5, 20, 24, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 8 }, IPA_TX_INSTANCE_NA }, + [IPA_4_11][IPA_CLIENT_APPS_WAN_LOW_LAT_PROD] = { + true, IPA_v4_11_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY, + QMB_MASTER_SELECT_DDR, + { 1, 1, 4, 4, IPA_EE_AP, GSI_SMART_PRE_FETCH, 1 }, IPA_TX_INSTANCE_NA }, + [IPA_4_11][IPA_CLIENT_Q6_WAN_PROD] = { + true, IPA_v4_11_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 5, 0, 16, 28, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 2 }, IPA_TX_INSTANCE_NA }, + [IPA_4_11][IPA_CLIENT_Q6_CMD_PROD] = { + true, IPA_v4_11_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 6, 1, 20, 24, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 8 }, IPA_TX_INSTANCE_NA }, + [IPA_4_11][IPA_CLIENT_Q6_DL_NLO_DATA_PROD] = { + true, IPA_v4_11_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 8, 2, 24, 32, IPA_EE_Q6, GSI_FREE_PRE_FETCH, 3 }, IPA_TX_INSTANCE_NA }, + /* Only for test purpose */ + [IPA_4_11][IPA_CLIENT_TEST_PROD] = { + true, IPA_v4_11_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 0, 0, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_11][IPA_CLIENT_TEST1_PROD] = { + true, IPA_v4_11_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 0, 0, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_11][IPA_CLIENT_TEST2_PROD] = { + true, IPA_v4_11_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 1, 1, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_11][IPA_CLIENT_TEST3_PROD] = { + true, IPA_v4_11_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 2, 2, 16, 32, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_11][IPA_CLIENT_TEST4_PROD] = { + true, IPA_v4_11_GROUP_UL_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 1, 1, 8, 16, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_11][IPA_CLIENT_WLAN1_CONS] = { + true, IPA_v4_11_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 18, 9, 8, 14, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, IPA_TX_INSTANCE_NA }, + [IPA_4_11][IPA_CLIENT_USB_CONS] = { + true, IPA_v4_11_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 19, 10, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 }, IPA_TX_INSTANCE_NA }, + [IPA_4_11][IPA_CLIENT_USB_DPL_CONS] = { + true, IPA_v4_11_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 17, 8, 5, 5, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 }, IPA_TX_INSTANCE_NA }, + [IPA_4_11][IPA_CLIENT_ODL_DPL_CONS] = { + true, IPA_v4_11_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 22, 13, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 }, IPA_TX_INSTANCE_NA }, + [IPA_4_11][IPA_CLIENT_APPS_LAN_CONS] = { + true, IPA_v4_11_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 9, 14, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 }, IPA_TX_INSTANCE_NA }, + [IPA_4_11][IPA_CLIENT_APPS_WAN_CONS] = { + true, IPA_v4_11_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 16, 7, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 }, IPA_TX_INSTANCE_NA }, + [IPA_4_11][IPA_CLIENT_APPS_WAN_COAL_CONS] = { + true, IPA_v4_11_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 15, 6, 8, 11, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, IPA_TX_INSTANCE_NA }, + [IPA_4_11][IPA_CLIENT_APPS_WAN_LOW_LAT_CONS] = { + true, IPA_v4_11_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 20, 11, 4, 4, IPA_EE_AP, GSI_SMART_PRE_FETCH, 1 }, IPA_TX_INSTANCE_NA }, + [IPA_4_11][IPA_CLIENT_Q6_LAN_CONS] = { + true, IPA_v4_11_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 10, 3, 9, 9, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0 }, IPA_TX_INSTANCE_NA }, + [IPA_4_11][IPA_CLIENT_Q6_WAN_CONS] = { + true, IPA_v4_11_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 14, 7, 9, 9, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0 }, IPA_TX_INSTANCE_NA }, + [IPA_4_11][IPA_CLIENT_Q6_UL_NLO_DATA_CONS] = { + true, IPA_v4_11_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 12, 5, 5, 5, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 2 }, IPA_TX_INSTANCE_NA }, + [IPA_4_11][IPA_CLIENT_Q6_UL_NLO_ACK_CONS] = { + true, IPA_v4_11_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 13, 6, 5, 5, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 2 }, IPA_TX_INSTANCE_NA }, + [IPA_4_11][IPA_CLIENT_Q6_QBAP_STATUS_CONS] = { + true, IPA_v4_11_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 11, 4, 9, 9, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0 }, IPA_TX_INSTANCE_NA }, +/* Only for test purpose */ + /* MBIM aggregation test pipes should have the same QMB as USB_CONS */ + [IPA_4_11][IPA_CLIENT_TEST_CONS] = { + true, IPA_v4_11_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 16, 7, 9, 9, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_11][IPA_CLIENT_TEST1_CONS] = { + true, IPA_v4_11_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 16, 7, 9, 9, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_11][IPA_CLIENT_TEST2_CONS] = { + true, IPA_v4_11_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 21, 12, 9, 9, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_11][IPA_CLIENT_TEST3_CONS] = { + true, IPA_v4_11_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 19, 10, 9, 9, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + [IPA_4_11][IPA_CLIENT_TEST4_CONS] = { + true, IPA_v4_11_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 20, 11, 9, 9, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + /* Dummy consumer (pipe 31) is used in L2TP rt rule */ + [IPA_4_11][IPA_CLIENT_DUMMY_CONS] = { + true, IPA_v4_11_GROUP_UL_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 31, 31, 8, 8, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + + /* IPA_5_0 */ + [IPA_5_0][IPA_CLIENT_USB_PROD] = { + true, IPA_v5_0_GROUP_UL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 0 , 14 , 8, 16, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0}, + IPA_TX_INSTANCE_NA }, + [IPA_5_0][IPA_CLIENT_APPS_WAN_PROD] = { + true, IPA_v5_0_GROUP_UL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 2 , 11, 25, 32, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3}, + IPA_TX_INSTANCE_NA }, + [IPA_5_0][IPA_CLIENT_APPS_WAN_LOW_LAT_PROD] = { + true, IPA_v5_0_GROUP_URLLC, + false, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 4 , 9 , 16, 24, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3}, + IPA_TX_INSTANCE_NA }, + [IPA_5_0][IPA_CLIENT_WLAN2_PROD] ={ + true, IPA_v5_0_GROUP_UL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 6 , 16, 8 , 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 2}, + IPA_TX_INSTANCE_NA }, + [IPA_5_0][IPA_CLIENT_USB2_PROD] = { + true, IPA_v5_0_GROUP_UL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 7 , 17, 8 , 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3}, + IPA_TX_INSTANCE_NA }, + [IPA_5_0][IPA_CLIENT_ETHERNET_PROD] = { + true, IPA_v5_0_GROUP_UL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 8 , 18, 8 , 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3}, + IPA_TX_INSTANCE_NA }, + [IPA_5_0][IPA_CLIENT_AQC_ETHERNET_PROD] = { + true, IPA_v5_0_GROUP_UL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 8 , 18, 8 , 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3}, + IPA_TX_INSTANCE_NA }, + [IPA_5_0][IPA_CLIENT_RTK_ETHERNET_PROD] = { + true, IPA_v5_0_GROUP_UL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 8 , 18, 8 , 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3}, + IPA_TX_INSTANCE_NA }, + [IPA_5_0][IPA_CLIENT_ETHERNET_PROD] = { + true, IPA_v5_0_GROUP_UL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 8 , 18, 8 , 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3}, + IPA_TX_INSTANCE_NA }, + [IPA_5_0][IPA_CLIENT_ETHERNET2_PROD] = { + true, IPA_v5_0_GROUP_UL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 3 , 7, 8 , 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3}, + IPA_TX_INSTANCE_NA }, + [IPA_5_0][IPA_CLIENT_APPS_LAN_PROD] = { + true, IPA_v5_0_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 9 , 19, 25, 32, IPA_EE_AP, GSI_SMART_PRE_FETCH, 4}, + IPA_TX_INSTANCE_NA }, + [IPA_5_0][IPA_CLIENT_ODU_PROD] = { + true, IPA_v5_0_GROUP_UL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 7, 17, 8, 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, + IPA_TX_INSTANCE_NA }, + [IPA_5_0][IPA_CLIENT_WLAN3_PROD] = { + true, IPA_v5_0_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 1 , 0, 8, 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 2}, + IPA_TX_INSTANCE_NA }, + [IPA_5_0][IPA_CLIENT_APPS_CMD_PROD] = { + true, IPA_v5_0_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY, + QMB_MASTER_SELECT_DDR, + { 14, 12, 20, 24, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0}, + IPA_TX_INSTANCE_NA }, + [IPA_5_0][IPA_CLIENT_Q6_WAN_PROD] = { + true, IPA_v5_0_GROUP_UL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 12, 0, 16, 28, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 2 }, + IPA_TX_INSTANCE_NA }, + [IPA_5_0][IPA_CLIENT_Q6_CMD_PROD] = { + true, IPA_v5_0_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 13, 1, 20, 24, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 8 }, + IPA_TX_INSTANCE_NA }, + [IPA_5_0][IPA_CLIENT_Q6_DL_NLO_DATA_PROD] = { + true, IPA_v5_0_GROUP_UL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 15, 2, 28, 32, IPA_EE_Q6, GSI_FREE_PRE_FETCH, 3 }, + IPA_TX_INSTANCE_NA }, + [IPA_5_0][IPA_CLIENT_Q6_DL_NLO_LL_DATA_PROD] = { + true, IPA_v5_0_GROUP_URLLC, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 5, 8, 28, 32, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 3 }, + IPA_TX_INSTANCE_UL }, + [IPA_5_0][IPA_CLIENT_TEST_PROD] = { + true, IPA_v5_0_GROUP_UL, + true, + IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_NO_UCP, + QMB_MASTER_SELECT_DDR, + { 0, 14, 8, 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3}, + IPA_TX_INSTANCE_NA }, + [IPA_5_0][IPA_CLIENT_TEST1_PROD] = { + true, IPA_v5_0_GROUP_UL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 3, 15, 8, 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3}, + IPA_TX_INSTANCE_NA }, + [IPA_5_0][IPA_CLIENT_TEST2_PROD] = { + true, IPA_v5_0_GROUP_UL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 1, 0, 16, 24, IPA_EE_AP, GSI_SMART_PRE_FETCH, 7}, + IPA_TX_INSTANCE_NA }, + [IPA_5_0][IPA_CLIENT_TEST3_PROD] = { + true, IPA_v5_0_GROUP_UL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 10, 5, 8, 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3}, + IPA_TX_INSTANCE_NA }, + [IPA_5_0][IPA_CLIENT_TEST4_PROD] = { + true, IPA_v5_0_GROUP_UL, + true, + IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY, + QMB_MASTER_SELECT_DDR, + { 7, 17, 8, 16, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0}, + IPA_TX_INSTANCE_NA }, + + [IPA_5_0][IPA_CLIENT_APPS_LAN_CONS] = { + true, IPA_v5_0_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 16, 13, 9 , 9 , IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0}, + IPA_TX_INSTANCE_UL }, + [IPA_5_0][IPA_CLIENT_APPS_WAN_COAL_CONS] = { + true, IPA_v5_0_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 22, 4 , 8 , 11, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3}, + IPA_TX_INSTANCE_DL }, + [IPA_5_0][IPA_CLIENT_APPS_WAN_CONS] = { + true, IPA_v5_0_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 23, 1 , 9 , 9 , IPA_EE_AP, GSI_SMART_PRE_FETCH, 3}, + IPA_TX_INSTANCE_DL }, + [IPA_5_0][IPA_CLIENT_USB_DPL_CONS] = { + true, IPA_v5_0_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 24, 20, 5 , 5 , IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0}, + IPA_TX_INSTANCE_DL }, + [IPA_5_0][IPA_CLIENT_ODL_DPL_CONS] = { + true, IPA_v5_0_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 25, 2 , 5 , 5 , IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0}, + IPA_TX_INSTANCE_DL }, + [IPA_5_0][IPA_CLIENT_AQC_ETHERNET_CONS] = { + true, IPA_v5_0_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 26, 21, 9 , 9 , IPA_EE_AP, GSI_SMART_PRE_FETCH, 3}, + IPA_TX_INSTANCE_DL }, + [IPA_5_0][IPA_CLIENT_RTK_ETHERNET_CONS] = { + true, IPA_v5_0_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 26, 21, 9 , 9 , IPA_EE_AP, GSI_SMART_PRE_FETCH, 3}, + IPA_TX_INSTANCE_DL }, + [IPA_5_0][IPA_CLIENT_ETHERNET_CONS] = { + true, IPA_v5_0_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 26, 21, 9 , 9 , IPA_EE_AP, GSI_SMART_PRE_FETCH, 3}, + IPA_TX_INSTANCE_DL }, + [IPA_5_0][IPA_CLIENT_ETHERNET2_CONS] = { + true, IPA_v5_0_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 30, 24, 9 , 9 , IPA_EE_AP, GSI_SMART_PRE_FETCH, 3}, + IPA_TX_INSTANCE_DL }, + [IPA_5_0][IPA_CLIENT_WLAN2_CONS] = { + true, IPA_v5_0_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 27, 3 , 8 , 14, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3}, + IPA_TX_INSTANCE_DL }, + [IPA_5_0][IPA_CLIENT_WLAN2_CONS1] = { + true, IPA_v5_0_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 28, 22 , 8 , 14, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3}, + IPA_TX_INSTANCE_DL }, + [IPA_5_0][IPA_CLIENT_USB_CONS] = { + true, IPA_v5_0_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 29, 23, 9 , 9 , IPA_EE_AP, GSI_SMART_PRE_FETCH, 3}, + IPA_TX_INSTANCE_DL }, + [IPA_5_0][IPA_CLIENT_APPS_WAN_LOW_LAT_CONS] = { + true, IPA_v5_0_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 32, 10, 9 , 9 , IPA_EE_AP, GSI_SMART_PRE_FETCH, 3}, + IPA_TX_INSTANCE_DL }, + [IPA_5_0][IPA_CLIENT_USB2_CONS] = { + true, IPA_v5_0_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 34, 8, 9 , 9 , IPA_EE_AP, GSI_SMART_PRE_FETCH, 4}, + IPA_TX_INSTANCE_DL }, + [IPA_5_0][IPA_CLIENT_WLAN4_CONS] = { + true, IPA_v5_0_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 35, 26 , 8 , 14, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3}, + IPA_TX_INSTANCE_DL }, + [IPA_5_0][IPA_CLIENT_ODU_EMB_CONS] = { + true, IPA_v5_0_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 34, 8, 9, 9, IPA_EE_AP, GSI_SMART_PRE_FETCH, 4 }, + IPA_TX_INSTANCE_DL }, + [IPA_5_0][IPA_CLIENT_TEST_CONS] = { + true, IPA_v5_0_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_PCIE, + { 28, 22, 9, 9, IPA_EE_AP, GSI_SMART_PRE_FETCH, 1}, + IPA_TX_INSTANCE_DL }, + [IPA_5_0][IPA_CLIENT_TEST1_CONS] = { + true, IPA_v5_0_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_PCIE, + { 30, 24, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0}, + IPA_TX_INSTANCE_DL }, + [IPA_5_0][IPA_CLIENT_TEST2_CONS] = { + true, IPA_v5_0_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 33, 6, 9, 9, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3}, + IPA_TX_INSTANCE_DL }, + [IPA_5_0][IPA_CLIENT_TEST3_CONS] = { + true, IPA_v5_0_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_PCIE, + { 29, 23, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0}, + IPA_TX_INSTANCE_DL }, + [IPA_5_0][IPA_CLIENT_TEST4_CONS] = { + true, IPA_v5_0_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_PCIE, + { 34, 8, 9, 9, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3}, + IPA_TX_INSTANCE_DL }, + [IPA_5_0][IPA_CLIENT_Q6_LAN_CONS] = { + true, IPA_v5_0_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 17, 3, 9, 9, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0 }, + IPA_TX_INSTANCE_DL }, + [IPA_5_0][IPA_CLIENT_Q6_WAN_CONS] = { + true, IPA_v5_0_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 21, 7, 9, 9, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0 }, + IPA_TX_INSTANCE_UL }, + [IPA_5_0][IPA_CLIENT_Q6_UL_NLO_DATA_CONS] = { + true, IPA_v5_0_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 19, 5, 5, 5, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 2 }, + IPA_TX_INSTANCE_UL }, + [IPA_5_0][IPA_CLIENT_Q6_UL_NLO_ACK_CONS] = { + true, IPA_v5_0_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 20, 6, 5, 5, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 2 }, + IPA_TX_INSTANCE_UL }, + [IPA_5_0][IPA_CLIENT_Q6_QBAP_STATUS_CONS] = { + true, IPA_v5_0_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 18, 4, 9, 9, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0 }, + IPA_TX_INSTANCE_UL }, + [IPA_5_0][IPA_CLIENT_TPUT_CONS] = { + true, IPA_v5_0_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 33, 6, 9, 9, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3}, + IPA_TX_INSTANCE_DL }, + + [IPA_5_0][IPA_CLIENT_DUMMY_CONS] = { + true, IPA_v5_0_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 36, 36, 8, 8, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + + + /* IPA_5_0_MHI */ + [IPA_5_0_MHI][IPA_CLIENT_USB_PROD] = { + true, IPA_v5_0_GROUP_UL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 0 , 14 , 8, 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3}, + IPA_TX_INSTANCE_NA }, + [IPA_5_0_MHI][IPA_CLIENT_MHI_PROD] = { + true, IPA_v5_0_GROUP_UL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_PCIE, + { 1 , 0 , 16, 24, IPA_EE_AP, GSI_SMART_PRE_FETCH, 7}, + IPA_TX_INSTANCE_NA }, + [IPA_5_0_MHI][IPA_CLIENT_APPS_WAN_PROD] = { + true, IPA_v5_0_GROUP_UL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 2 , 11, 25, 32, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3}, + IPA_TX_INSTANCE_NA }, + [IPA_5_0_MHI][IPA_CLIENT_MHI_LOW_LAT_PROD] = { + true, IPA_v5_0_GROUP_URLLC, + false, + IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_UCP, + QMB_MASTER_SELECT_PCIE, + { 10, 5, 10, 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3}, + IPA_TX_INSTANCE_NA }, + [IPA_5_0_MHI][IPA_CLIENT_MEMCPY_DMA_SYNC_PROD] ={ + true, IPA_v5_0_GROUP_DMA, + false, + IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY, + QMB_MASTER_SELECT_DDR, + { 6 , 16, 8 , 16, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0}, + IPA_TX_INSTANCE_NA }, + [IPA_5_0_MHI][IPA_CLIENT_MEMCPY_DMA_ASYNC_PROD] = { + true, IPA_v5_0_GROUP_DMA, + false, + IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY, + QMB_MASTER_SELECT_DDR, + { 7 , 17, 8 , 16, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0}, + IPA_TX_INSTANCE_NA }, + [IPA_5_0_MHI][IPA_CLIENT_QDSS_PROD] = { + true, IPA_v5_0_GROUP_QDSS, + false, + IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY, + QMB_MASTER_SELECT_DDR, + { 8 , 18, 4 , 8, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0}, + IPA_TX_INSTANCE_NA }, + [IPA_5_0_MHI][IPA_CLIENT_APPS_CMD_PROD] = { + true, IPA_v5_0_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY, + QMB_MASTER_SELECT_DDR, + { 14, 12, 20, 24, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0}, + IPA_TX_INSTANCE_NA }, + [IPA_5_0_MHI][IPA_CLIENT_ODU_PROD] = { + true, IPA_v5_0_GROUP_UL, + true, + IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_NO_UCP, + QMB_MASTER_SELECT_DDR, + { 0, 14, 8, 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3}, + IPA_TX_INSTANCE_NA }, + [IPA_5_0_MHI][IPA_CLIENT_Q6_WAN_PROD] = { + true, IPA_v5_0_GROUP_UL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 12, 0, 16, 28, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 2 }, + IPA_TX_INSTANCE_NA }, + [IPA_5_0_MHI][IPA_CLIENT_Q6_CMD_PROD] = { + true, IPA_v5_0_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 13, 1, 20, 24, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 8 }, + IPA_TX_INSTANCE_NA }, + [IPA_5_0_MHI][IPA_CLIENT_Q6_DL_NLO_DATA_PROD] = { + true, IPA_v5_0_GROUP_UL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 15, 2, 28, 32, IPA_EE_Q6, GSI_FREE_PRE_FETCH, 3 }, + IPA_TX_INSTANCE_NA }, + [IPA_5_0_MHI][IPA_CLIENT_Q6_DL_NLO_LL_DATA_PROD] = { + true, IPA_v5_0_GROUP_URLLC, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 5, 8, 28, 32, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 3 }, + IPA_TX_INSTANCE_UL }, + [IPA_5_0_MHI][IPA_CLIENT_TEST_PROD] = { + true, IPA_v5_0_GROUP_UL, + true, + IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_NO_UCP, + QMB_MASTER_SELECT_DDR, + { 0, 14, 8, 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3}, + IPA_TX_INSTANCE_NA }, + + [IPA_5_0_MHI][IPA_CLIENT_APPS_LAN_CONS] = { + true, IPA_v5_0_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 16, 13, 9 , 9 , IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0}, + IPA_TX_INSTANCE_UL }, + [IPA_5_0_MHI][IPA_CLIENT_APPS_WAN_COAL_CONS] = { + true, IPA_v5_0_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 22, 4 , 8 , 11, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3}, + IPA_TX_INSTANCE_DL }, + [IPA_5_0_MHI][IPA_CLIENT_APPS_WAN_CONS] = { + true, IPA_v5_0_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 26, 21 , 9 , 9 , IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0}, + IPA_TX_INSTANCE_DL}, + [IPA_5_0_MHI][IPA_CLIENT_MHI_CONS] = { + true, IPA_v5_0_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_PCIE, + { 23, 1 , 9 , 9 , IPA_EE_AP, GSI_SMART_PRE_FETCH, 3}, + IPA_TX_INSTANCE_DL }, + [IPA_5_0_MHI][IPA_CLIENT_MHI_DPL_CONS] = { + true, IPA_v5_0_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_PCIE, + { 25, 2, 5, 5, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 }, + IPA_TX_INSTANCE_DL }, + [IPA_5_0_MHI][IPA_CLIENT_USB_DPL_CONS] = { + true, IPA_v5_0_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 24, 20, 5 , 5 , IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0}, + IPA_TX_INSTANCE_DL }, + [IPA_5_0_MHI][IPA_CLIENT_MHI_QDSS_CONS] = { + true, IPA_v5_0_GROUP_QDSS, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_PCIE, + { 27, 3 , 5 , 5 , IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0}, + IPA_TX_INSTANCE_DL }, + [IPA_5_0_MHI][IPA_CLIENT_USB_CONS] = { + true, IPA_v5_0_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 28, 22 , 9 , 9, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3}, + IPA_TX_INSTANCE_DL }, + [IPA_5_0_MHI][IPA_CLIENT_MEMCPY_DMA_SYNC_CONS] = { + true, IPA_v5_0_GROUP_DMA, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_PCIE, + { 29, 23, 5 , 5 , IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0}, + IPA_TX_INSTANCE_DL }, + [IPA_5_0_MHI][IPA_CLIENT_MEMCPY_DMA_ASYNC_CONS] = { + true, IPA_v5_0_GROUP_DMA, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_PCIE, + { 30, 24, 5 , 5 , IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0}, + IPA_TX_INSTANCE_DL }, + [IPA_5_0_MHI][IPA_CLIENT_MHI_LOW_LAT_CONS] = { + true, IPA_v5_0_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_PCIE, + { 33, 6, 9 , 9 , IPA_EE_AP, GSI_SMART_PRE_FETCH, 3}, + IPA_TX_INSTANCE_DL }, + [IPA_5_0_MHI][IPA_CLIENT_ODU_EMB_CONS] = { + true, IPA_v5_0_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 28, 22, 9, 9, IPA_EE_AP, GSI_SMART_PRE_FETCH, 1}, + IPA_TX_INSTANCE_DL }, + [IPA_5_0_MHI][IPA_CLIENT_TEST_CONS] = { + true, IPA_v5_0_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_PCIE, + { 28, 22, 9, 9, IPA_EE_AP, GSI_SMART_PRE_FETCH, 1}, + IPA_TX_INSTANCE_DL }, + [IPA_5_0_MHI][IPA_CLIENT_Q6_LAN_CONS] = { + true, IPA_v5_0_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 17, 3, 9, 9, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0 }, + IPA_TX_INSTANCE_DL }, + [IPA_5_0_MHI][IPA_CLIENT_Q6_WAN_CONS] = { + true, IPA_v5_0_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 21, 7, 9, 9, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0 }, + IPA_TX_INSTANCE_UL }, + [IPA_5_0_MHI][IPA_CLIENT_Q6_UL_NLO_DATA_CONS] = { + true, IPA_v5_0_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 19, 5, 5, 5, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 2 }, + IPA_TX_INSTANCE_UL }, + [IPA_5_0_MHI][IPA_CLIENT_Q6_UL_NLO_ACK_CONS] = { + true, IPA_v5_0_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 20, 6, 5, 5, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 2 }, + IPA_TX_INSTANCE_UL }, + [IPA_5_0_MHI][IPA_CLIENT_Q6_QBAP_STATUS_CONS] = { + true, IPA_v5_0_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 18, 4, 9, 9, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0 }, + IPA_TX_INSTANCE_UL }, + + [IPA_5_0_MHI][IPA_CLIENT_DUMMY_CONS] = { + true, IPA_v5_0_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 36, 36, 8, 8, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + + /* IPA_5_1 */ + [IPA_5_1][IPA_CLIENT_USB_PROD] = { + true, IPA_v5_0_GROUP_UL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 1, 0, 8, 16, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 }, + IPA_TX_INSTANCE_NA }, + + [IPA_5_1][IPA_CLIENT_APPS_WAN_PROD] = { + true, IPA_v5_0_GROUP_UL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 2, 11, 25, 32, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, + IPA_TX_INSTANCE_NA }, + + [IPA_5_1][IPA_CLIENT_WLAN2_PROD] = { + true, IPA_v5_0_GROUP_UL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 6, 16, 8, 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 2 }, + IPA_TX_INSTANCE_NA }, + + [IPA_5_1][IPA_CLIENT_WIGIG_PROD] = { + true, IPA_v5_0_GROUP_UL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 7, 17, 8, 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 2 }, + IPA_TX_INSTANCE_NA }, + + [IPA_5_1][IPA_CLIENT_APPS_LAN_PROD] = { + true, IPA_v5_0_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 9, 19, 26, 32, IPA_EE_AP, GSI_SMART_PRE_FETCH, 4 }, + IPA_TX_INSTANCE_NA }, + + [IPA_5_1][IPA_CLIENT_APPS_CMD_PROD] = { + true, IPA_v5_0_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY, + QMB_MASTER_SELECT_DDR, + { 14, 12, 20, 24, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 }, + IPA_TX_INSTANCE_NA }, + + [IPA_5_1][IPA_CLIENT_APPS_WAN_LOW_LAT_PROD] = { + true, IPA_v5_0_GROUP_URLLC, + false, + IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY, + QMB_MASTER_SELECT_DDR, + { 4, 9, 16, 24, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, + IPA_TX_INSTANCE_NA }, + + [IPA_5_1][IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_PROD] = { + true, IPA_v5_0_GROUP_URLLC, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 10, 5, 10, 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, + IPA_TX_INSTANCE_NA }, + + [IPA_5_1][IPA_CLIENT_Q6_WAN_PROD] = { + true, IPA_v5_0_GROUP_UL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 12, 0, 16, 28, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 2 }, + IPA_TX_INSTANCE_NA }, + + [IPA_5_1][IPA_CLIENT_Q6_CMD_PROD] = { + true, IPA_v5_0_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 13, 1, 20, 24, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0 }, + IPA_TX_INSTANCE_NA }, + + [IPA_5_1][IPA_CLIENT_Q6_DL_NLO_DATA_PROD] = { + true, IPA_v5_0_GROUP_UL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 15, 2, 28, 32, IPA_EE_Q6, GSI_FREE_PRE_FETCH, 3 }, + IPA_TX_INSTANCE_NA }, + + [IPA_5_1][IPA_CLIENT_Q6_DL_NLO_LL_DATA_PROD] = { + true, IPA_v5_0_GROUP_URLLC, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 5, 8, 28, 32, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 3 }, + IPA_TX_INSTANCE_UL }, + + [IPA_5_1][IPA_CLIENT_APPS_LAN_CONS] = { + true, IPA_v5_0_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 16, 13, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 }, + IPA_TX_INSTANCE_UL }, + + [IPA_5_1][IPA_CLIENT_APPS_WAN_COAL_CONS] = { + true, IPA_v5_0_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 22, 4, 8, 11, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, + IPA_TX_INSTANCE_DL }, + + [IPA_5_1][IPA_CLIENT_APPS_WAN_CONS] = { + true, IPA_v5_0_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 23, 1, 9, 9, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, + IPA_TX_INSTANCE_DL }, + + [IPA_5_1][IPA_CLIENT_USB_DPL_CONS] = { + true, IPA_v5_0_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 24, 20, 5, 5, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 }, + IPA_TX_INSTANCE_DL }, + + [IPA_5_1][IPA_CLIENT_ODL_DPL_CONS] = { + true, IPA_v5_0_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 25, 2, 5, 5, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 }, + IPA_TX_INSTANCE_DL }, + + [IPA_5_1][IPA_CLIENT_WIGIG1_CONS] = { + true, IPA_v5_0_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 26, 21, 8, 14, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, + IPA_TX_INSTANCE_DL }, + + [IPA_5_1][IPA_CLIENT_WLAN1_CONS] = { + true, IPA_v5_0_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 27, 3, 8, 14, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, + IPA_TX_INSTANCE_DL }, + + [IPA_5_1][IPA_CLIENT_WLAN2_CONS] = { + true, IPA_v5_0_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 28, 22, 8, 14, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, + IPA_TX_INSTANCE_DL }, + + [IPA_5_1][IPA_CLIENT_USB_CONS] = { + true, IPA_v5_0_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 29, 23, 9, 9, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, + IPA_TX_INSTANCE_DL }, + + [IPA_5_1][IPA_CLIENT_WIGIG2_CONS] = { + true, IPA_v5_0_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 30, 24, 8, 14, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, + IPA_TX_INSTANCE_DL }, + + [IPA_5_1][IPA_CLIENT_WIGIG3_CONS] = { + true, IPA_v5_0_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 34, 25, 8, 14, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, + IPA_TX_INSTANCE_DL }, + + [IPA_5_1][IPA_CLIENT_WIGIG4_CONS] = { + true, IPA_v5_0_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 35, 26, 8, 14, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, + IPA_TX_INSTANCE_DL }, + + [IPA_5_1][IPA_CLIENT_APPS_WAN_LOW_LAT_CONS] = { + true, IPA_v5_0_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 32, 10, 9, 9, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, + IPA_TX_INSTANCE_DL }, + + [IPA_5_1][IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_CONS] = { + true, IPA_v5_0_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 33, 6, 9, 9, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, + IPA_TX_INSTANCE_DL }, + + [IPA_5_1][IPA_CLIENT_Q6_LAN_CONS] = { + true, IPA_v5_0_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 17, 3, 9, 9, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0 }, + IPA_TX_INSTANCE_DL }, + + [IPA_5_1][IPA_CLIENT_Q6_QBAP_STATUS_CONS] = { + true, IPA_v5_0_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 18, 4, 9, 9, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0 }, + IPA_TX_INSTANCE_UL }, + + [IPA_5_1][IPA_CLIENT_Q6_UL_NLO_DATA_CONS] = { + true, IPA_v5_0_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 19, 5, 5, 5, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 2 }, + IPA_TX_INSTANCE_UL }, + + [IPA_5_1][IPA_CLIENT_Q6_UL_NLO_ACK_CONS] = { + true, IPA_v5_0_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 20, 6, 5, 5, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 2 }, + IPA_TX_INSTANCE_UL }, + + [IPA_5_1][IPA_CLIENT_Q6_WAN_CONS] = { + true, IPA_v5_0_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 21, 7, 9, 9, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0 }, + IPA_TX_INSTANCE_UL }, + + [IPA_5_1][IPA_CLIENT_DUMMY_CONS] = { + true, IPA_v5_0_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 36, 36, 8, 8, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + + /*For test purposes only*/ + [IPA_5_1][IPA_CLIENT_TEST_PROD] = { + true, IPA_v5_0_GROUP_UL, + true, + IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_NO_UCP, + QMB_MASTER_SELECT_DDR, + { 0, 14, 8, 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, + IPA_TX_INSTANCE_NA }, + + [IPA_5_1][IPA_CLIENT_TEST1_PROD] = { + true, IPA_v5_0_GROUP_UL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 3, 15, 8, 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, + IPA_TX_INSTANCE_NA }, + + [IPA_5_1][IPA_CLIENT_TEST2_PROD] = { + true, IPA_v5_0_GROUP_UL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 1, 0, 16, 24, IPA_EE_AP, GSI_SMART_PRE_FETCH, 7 }, + IPA_TX_INSTANCE_NA }, + + [IPA_5_1][IPA_CLIENT_TEST3_PROD] = { + true, IPA_v5_0_GROUP_UL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 10, 5, 8, 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, + IPA_TX_INSTANCE_NA }, + + [IPA_5_1][IPA_CLIENT_TEST4_PROD] = { + true, IPA_v5_0_GROUP_UL, + true, + IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY, + QMB_MASTER_SELECT_DDR, + { 7, 17, 8, 16, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 }, + IPA_TX_INSTANCE_NA }, + + [IPA_5_1][IPA_CLIENT_TEST_CONS] = { + true, IPA_v5_0_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_PCIE, + { 32, 8, 9, 9, IPA_EE_AP, GSI_SMART_PRE_FETCH, 1 }, + IPA_TX_INSTANCE_DL }, + + [IPA_5_1][IPA_CLIENT_TEST1_CONS] = { + true, IPA_v5_0_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_PCIE, + { 30, 24, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 }, + IPA_TX_INSTANCE_DL }, + + [IPA_5_1][IPA_CLIENT_TEST2_CONS] = { + true, IPA_v5_0_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 33, 6, 9, 9, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, + IPA_TX_INSTANCE_DL }, + + [IPA_5_1][IPA_CLIENT_TEST3_CONS] = { + true, IPA_v5_0_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_PCIE, + { 29, 23, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 }, + IPA_TX_INSTANCE_DL }, + + [IPA_5_1][IPA_CLIENT_TEST4_CONS] = { + true, IPA_v5_0_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_PCIE, + { 34, 25, 9, 9, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, + IPA_TX_INSTANCE_DL }, + + /* IPA_5_1_APQ */ + [IPA_5_1_APQ][IPA_CLIENT_MHI_PRIME_DPL_PROD] = { + true, IPA_v5_0_GROUP_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY, + QMB_MASTER_SELECT_DDR, + {8, 18, 8, 16, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 }, + IPA_TX_INSTANCE_NA }, + [IPA_5_1_APQ][IPA_CLIENT_MHI_PRIME_RMNET_PROD] = { + true, IPA_v5_0_GROUP_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY, + QMB_MASTER_SELECT_DDR, + { 3, 15, 8, 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, + IPA_TX_INSTANCE_NA }, + [IPA_5_1_APQ][IPA_CLIENT_USB_PROD] = { + true, IPA_v5_0_GROUP_UL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 1, 0, 8, 16, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0}, + IPA_TX_INSTANCE_NA }, + [IPA_5_1_APQ][IPA_CLIENT_APPS_WAN_PROD] = { + true, IPA_v5_0_GROUP_UL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 2, 11, 25, 32, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3}, + IPA_TX_INSTANCE_NA }, + [IPA_5_1_APQ][IPA_CLIENT_APPS_LAN_PROD] = { + true, IPA_v5_0_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 9, 19, 26, 32, IPA_EE_AP, GSI_SMART_PRE_FETCH, 4}, + IPA_TX_INSTANCE_NA }, + [IPA_5_1_APQ][IPA_CLIENT_APPS_CMD_PROD] = { + true, IPA_v5_0_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY, + QMB_MASTER_SELECT_DDR, + { 14, 12, 20, 24, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0}, + IPA_TX_INSTANCE_NA }, + + [IPA_5_1_APQ][IPA_CLIENT_MHI_PRIME_RMNET_CONS] = { + true, IPA_v5_0_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 31, 8, 9, 9, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, + IPA_TX_INSTANCE_UL }, + [IPA_5_1_APQ][IPA_CLIENT_APPS_LAN_CONS] = { + true, IPA_v5_0_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 16, 13, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0}, + IPA_TX_INSTANCE_UL }, + [IPA_5_1_APQ][IPA_CLIENT_USB_DPL_CONS] = { + true, IPA_v5_0_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 24, 20, 5, 5, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0}, + IPA_TX_INSTANCE_DL }, + [IPA_5_1_APQ][IPA_CLIENT_ODL_DPL_CONS] = { + true, IPA_v5_0_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 25, 2, 5, 5, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0}, + IPA_TX_INSTANCE_DL }, + [IPA_5_1_APQ][IPA_CLIENT_USB_CONS] = { + true, IPA_v5_0_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 29, 23, 9, 9, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3}, + IPA_TX_INSTANCE_DL }, + + [IPA_5_1_APQ][IPA_CLIENT_DUMMY_CONS] = { + true, IPA_v5_0_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 36, 36, 8, 8, IPA_EE_AP }, IPA_TX_INSTANCE_NA }, + + /* IPA_5_2 */ + [IPA_5_2][IPA_CLIENT_USB_PROD] = { + true, IPA_v5_2_GROUP_UL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 0, 0, 8, 16, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0}, IPA_TX_INSTANCE_NA }, + + [IPA_5_2][IPA_CLIENT_APPS_WAN_LOW_LAT_PROD] = { + true, IPA_v5_2_GROUP_URLLC, + false, + IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY, + QMB_MASTER_SELECT_DDR, + { 3, 2, 12, 20, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3}, IPA_TX_INSTANCE_NA }, + + [IPA_5_2][IPA_CLIENT_Q6_DL_NLO_LL_DATA_PROD] = { + true, IPA_v5_2_GROUP_URLLC, + false, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 4, 8, 28, 32, IPA_EE_Q6, GSI_FREE_PRE_FETCH, 3}, IPA_TX_INSTANCE_NA }, + + [IPA_5_2][IPA_CLIENT_WLAN2_PROD] = { + true, IPA_v5_2_GROUP_UL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 5, 3, 8, 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 2}, IPA_TX_INSTANCE_NA }, + + [IPA_5_2][IPA_CLIENT_APPS_LAN_PROD] = { + true, IPA_v5_2_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_NO_UCP, + QMB_MASTER_SELECT_DDR, + { 6, 4, 26, 32, IPA_EE_AP, GSI_SMART_PRE_FETCH, 4}, IPA_TX_INSTANCE_NA }, + + + [IPA_5_2][IPA_CLIENT_APPS_WAN_PROD] = { + true, IPA_v5_2_GROUP_UL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 2, 5, 25, 32, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3}, IPA_TX_INSTANCE_NA }, + + [IPA_5_2][IPA_CLIENT_Q6_WAN_PROD] = { + true, IPA_v5_2_GROUP_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 7, 0, 16, 28, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 2}, IPA_TX_INSTANCE_NA }, + + [IPA_5_2][IPA_CLIENT_Q6_CMD_PROD] = { + true, IPA_v5_2_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_NO_UCP, + QMB_MASTER_SELECT_DDR, + { 8, 1, 20, 24, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0}, IPA_TX_INSTANCE_NA }, + + [IPA_5_2][IPA_CLIENT_APPS_CMD_PROD] = { + true, IPA_v5_2_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY, + QMB_MASTER_SELECT_DDR, + { 9, 6, 20, 24, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0}, IPA_TX_INSTANCE_NA }, + [IPA_5_2][IPA_CLIENT_Q6_DL_NLO_DATA_PROD] = { + true, IPA_v5_2_GROUP_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 10, 2, 28, 32, IPA_EE_Q6, GSI_FREE_PRE_FETCH, 3}, IPA_TX_INSTANCE_NA }, + + [IPA_5_2][IPA_CLIENT_APPS_WAN_COAL_CONS] = { + true, IPA_v5_2_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 17, 8, 8, 11, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3}, IPA_TX_INSTANCE_UL }, + + [IPA_5_2][IPA_CLIENT_APPS_WAN_CONS] = { + true, IPA_v5_2_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 18, 9, 9, 9, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3}, IPA_TX_INSTANCE_UL }, + + [IPA_5_2][IPA_CLIENT_USB_DPL_CONS] = { + true, IPA_v5_2_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 19, 10, 5, 5, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0}, IPA_TX_INSTANCE_UL }, + + [IPA_5_2][IPA_CLIENT_ODL_DPL_CONS] = { + true, IPA_v5_2_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 20, 11, 5, 5, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0}, IPA_TX_INSTANCE_UL }, + + [IPA_5_2][IPA_CLIENT_WLAN2_CONS] = { + true, IPA_v5_2_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 21, 12, 8, 14, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3}, IPA_TX_INSTANCE_UL }, + + [IPA_5_2][IPA_CLIENT_WLAN2_CONS1] = { + true, IPA_v5_2_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 22, 13, 8, 14, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3}, IPA_TX_INSTANCE_UL }, + + [IPA_5_2][IPA_CLIENT_USB_CONS] = { + true, IPA_v5_2_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 23, 14, 9, 9, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3}, IPA_TX_INSTANCE_UL }, + + + [IPA_5_2][IPA_CLIENT_APPS_WAN_LOW_LAT_CONS] = { + true, IPA_v5_2_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 24, 15, 9, 9, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3}, IPA_TX_INSTANCE_UL }, + + + [IPA_5_2][IPA_CLIENT_APPS_LAN_CONS] = { + true, IPA_v5_2_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 11, 7, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0}, IPA_TX_INSTANCE_UL }, + + [IPA_5_2][IPA_CLIENT_Q6_LAN_CONS] = { + true, IPA_v5_2_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 12, 3, 9, 9, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0}, IPA_TX_INSTANCE_UL }, + + [IPA_5_2][IPA_CLIENT_Q6_QBAP_STATUS_CONS] = { + true, IPA_v5_2_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 13, 4, 9, 9, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0}, IPA_TX_INSTANCE_UL }, + + [IPA_5_2][IPA_CLIENT_Q6_UL_NLO_DATA_CONS] = { + true, IPA_v5_2_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 14, 5, 5, 5, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 2}, IPA_TX_INSTANCE_UL }, + + [IPA_5_2][IPA_CLIENT_Q6_UL_NLO_ACK_CONS] = { + true, IPA_v5_2_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 15, 6, 5, 5, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 2}, IPA_TX_INSTANCE_UL }, + + [IPA_5_2][IPA_CLIENT_Q6_WAN_CONS] = { + true, IPA_v5_2_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 16, 7, 9, 9, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0}, IPA_TX_INSTANCE_UL }, + + [IPA_5_2][IPA_CLIENT_TEST_PROD] = { + true, IPA_v5_2_GROUP_URLLC, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 3, 2, 12, 20, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3}, IPA_TX_INSTANCE_NA }, + + [IPA_5_2][IPA_CLIENT_TEST1_PROD] = { + true, IPA_v5_2_GROUP_UL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 1, 1, 8, 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3}, IPA_TX_INSTANCE_NA }, + + [IPA_5_2][IPA_CLIENT_TEST2_PROD] = { + true, IPA_v5_2_GROUP_UL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 0, 0, 8, 16, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0}, IPA_TX_INSTANCE_NA }, + + [IPA_5_2][IPA_CLIENT_TEST3_PROD] = { + true, IPA_v5_2_GROUP_UL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 5, 3, 8, 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3}, IPA_TX_INSTANCE_NA }, + + [IPA_5_2][IPA_CLIENT_TEST4_PROD] = { + true, IPA_v5_2_GROUP_UL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 2, 5, 25, 32, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3}, IPA_TX_INSTANCE_NA }, + + [IPA_5_2][IPA_CLIENT_TEST_CONS] = { + true, IPA_v5_2_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 19, 10, 5, 5, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0}, IPA_TX_INSTANCE_UL }, + + [IPA_5_2][IPA_CLIENT_TEST1_CONS] = { + true, IPA_v5_2_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 21, 12, 8, 14, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3}, IPA_TX_INSTANCE_UL }, + + [IPA_5_2][IPA_CLIENT_TEST2_CONS] = { + true, IPA_v5_2_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 22, 13, 8, 14, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3}, IPA_TX_INSTANCE_DL }, + + [IPA_5_2][IPA_CLIENT_TEST3_CONS] = { + true, IPA_v5_2_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 23, 14, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0}, IPA_TX_INSTANCE_UL }, + + [IPA_5_2][IPA_CLIENT_TEST4_CONS] = { + true, IPA_v5_2_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, //UPDATE AS DDR + { 20, 11, 5, 5, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0}, IPA_TX_INSTANCE_UL }, + + /* IPA_5_5 */ + [IPA_5_5][IPA_CLIENT_USB_PROD] = { + true, IPA_v5_5_GROUP_UL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 1, 0, 8, 16, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 }, + IPA_TX_INSTANCE_NA }, + + [IPA_5_5][IPA_CLIENT_APPS_WAN_PROD] = { + true, IPA_v5_5_GROUP_UL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 2, 11, 25, 32, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, + IPA_TX_INSTANCE_NA }, + + [IPA_5_5][IPA_CLIENT_APPS_WAN_LOW_LAT_PROD] = { + true, IPA_v5_5_GROUP_URLLC, + false, + IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY, + QMB_MASTER_SELECT_DDR, + { 4, 9, 8, 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, + IPA_TX_INSTANCE_NA }, + + [IPA_5_5][IPA_CLIENT_WLAN2_PROD] = { + true, IPA_v5_5_GROUP_UL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 6, 16, 8, 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 2 }, + IPA_TX_INSTANCE_NA }, + + [IPA_5_5][IPA_CLIENT_WIGIG_PROD] = { + true, IPA_v5_5_GROUP_UL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 7, 17, 8, 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 2 }, + IPA_TX_INSTANCE_NA }, + + [IPA_5_5][IPA_CLIENT_APPS_LAN_PROD] = { + true, IPA_v5_5_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 9, 19, 26, 32, IPA_EE_AP, GSI_SMART_PRE_FETCH, 4 }, + IPA_TX_INSTANCE_NA }, + + [IPA_5_5][IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_PROD] = { + true, IPA_v5_5_GROUP_URLLC, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 10, 5, 10, 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, + IPA_TX_INSTANCE_NA }, + + [IPA_5_5][IPA_CLIENT_APPS_CMD_PROD] = { + true, IPA_v5_5_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY, + QMB_MASTER_SELECT_DDR, + { 14, 12, 20, 24, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 }, + IPA_TX_INSTANCE_NA }, + + [IPA_5_5][IPA_CLIENT_Q6_WAN_PROD] = { + true, IPA_v5_5_GROUP_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 12, 0, 16, 28, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 2 }, + IPA_TX_INSTANCE_NA }, + + [IPA_5_5][IPA_CLIENT_Q6_CMD_PROD] = { + true, IPA_v5_5_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 13, 1, 20, 24, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0 }, + IPA_TX_INSTANCE_NA }, + + [IPA_5_5][IPA_CLIENT_Q6_DL_NLO_DATA_PROD] = { + true, IPA_v5_5_GROUP_DL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 15, 2, 28, 32, IPA_EE_Q6, GSI_FREE_PRE_FETCH, 3 }, + IPA_TX_INSTANCE_NA }, + + [IPA_5_5][IPA_CLIENT_Q6_DL_NLO_LL_DATA_PROD] = { + true, IPA_v5_5_GROUP_URLLC, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 5, 8, 28, 32, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 3 }, + IPA_TX_INSTANCE_NA }, + + [IPA_5_5][IPA_CLIENT_APPS_LAN_COAL_CONS] = { + true, IPA_v5_5_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 16, 13, 8, 23, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, + IPA_TX_INSTANCE_UL }, + + [IPA_5_5][IPA_CLIENT_APPS_LAN_CONS] = { + true, IPA_v5_5_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 17, 14, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 }, + IPA_TX_INSTANCE_UL }, + + [IPA_5_5][IPA_CLIENT_APPS_WAN_COAL_CONS] = { + true, IPA_v5_5_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 23, 4, 8, 23, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, + IPA_TX_INSTANCE_DL }, + + [IPA_5_5][IPA_CLIENT_APPS_WAN_CONS] = { + true, IPA_v5_5_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 24, 1, 9, 9, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, + IPA_TX_INSTANCE_DL }, + + [IPA_5_5][IPA_CLIENT_USB_DPL_CONS] = { + true, IPA_v5_5_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 25, 20, 5, 5, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 }, + IPA_TX_INSTANCE_DL }, + + [IPA_5_5][IPA_CLIENT_ODL_DPL_CONS] = { + true, IPA_v5_5_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 26, 2, 5, 5, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 }, + IPA_TX_INSTANCE_DL }, + + [IPA_5_5][IPA_CLIENT_WIGIG1_CONS] = { + true, IPA_v5_5_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 27, 21, 8, 14, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, + IPA_TX_INSTANCE_DL }, + + [IPA_5_5][IPA_CLIENT_WLAN2_CONS] = { + true, IPA_v5_5_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 28, 3, 8, 14, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, + IPA_TX_INSTANCE_DL }, + + [IPA_5_5][IPA_CLIENT_WLAN2_CONS1] = { + true, IPA_v5_5_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 29, 22, 8, 14, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, + IPA_TX_INSTANCE_DL }, + + [IPA_5_5][IPA_CLIENT_USB_CONS] = { + true, IPA_v5_5_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 30, 23, 9, 9, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, + IPA_TX_INSTANCE_DL }, + + [IPA_5_5][IPA_CLIENT_APPS_WAN_LOW_LAT_CONS] = { + true, IPA_v5_5_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 32, 8, 9, 9, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, + IPA_TX_INSTANCE_DL }, + + [IPA_5_5][IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_CONS] = { + true, IPA_v5_5_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 33, 10, 9, 9, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, + IPA_TX_INSTANCE_DL }, + + [IPA_5_5][IPA_CLIENT_WIGIG2_CONS] = { + true, IPA_v5_5_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 34, 6, 8, 14, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, + IPA_TX_INSTANCE_DL }, + + [IPA_5_5][IPA_CLIENT_WIGIG3_CONS] = { + true, IPA_v5_5_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 35, 25, 8, 14, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, + IPA_TX_INSTANCE_DL }, + + [IPA_5_5][IPA_CLIENT_Q6_LAN_CONS] = { + true, IPA_v5_5_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 18, 3, 9, 9, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0 }, + IPA_TX_INSTANCE_DL }, + + [IPA_5_5][IPA_CLIENT_Q6_QBAP_STATUS_CONS] = { + true, IPA_v5_5_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 19, 4, 9, 9, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0 }, + IPA_TX_INSTANCE_UL }, + + [IPA_5_5][IPA_CLIENT_Q6_UL_NLO_DATA_CONS] = { + true, IPA_v5_5_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 20, 5, 5, 5, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 2 }, + IPA_TX_INSTANCE_UL }, + + [IPA_5_5][IPA_CLIENT_Q6_UL_NLO_ACK_CONS] = { + true, IPA_v5_5_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 21, 6, 5, 5, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 2 }, + IPA_TX_INSTANCE_UL }, + + [IPA_5_5][IPA_CLIENT_Q6_WAN_CONS] = { + true, IPA_v5_5_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 22, 7, 9, 9, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0 }, + IPA_TX_INSTANCE_UL }, + + /*For test purposes only*/ + [IPA_5_5][IPA_CLIENT_TEST_PROD] = { + true, IPA_v5_5_GROUP_URLLC, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 4, 9, 8, 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, + IPA_TX_INSTANCE_NA }, + + [IPA_5_5][IPA_CLIENT_TEST1_PROD] = { + true, IPA_v5_5_GROUP_UL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 3, 7, 8, 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, + IPA_TX_INSTANCE_NA }, + + [IPA_5_5][IPA_CLIENT_TEST2_PROD] = { + true, IPA_v5_5_GROUP_UL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 1, 0, 8, 16, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 }, + IPA_TX_INSTANCE_NA }, + + [IPA_5_5][IPA_CLIENT_TEST3_PROD] = { + true, IPA_v5_5_GROUP_URLLC, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 10, 5, 10, 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, + IPA_TX_INSTANCE_NA }, + + [IPA_5_5][IPA_CLIENT_TEST4_PROD] = { + true, IPA_v5_5_GROUP_UL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 2, 11, 25, 32, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, + IPA_TX_INSTANCE_NA }, + + [IPA_5_5][IPA_CLIENT_TEST_CONS] = { + true, IPA_v5_5_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 32, 8, 9, 9, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, + IPA_TX_INSTANCE_DL }, + + [IPA_5_5][IPA_CLIENT_TEST1_CONS] = { + true, IPA_v5_5_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 26, 2, 5, 5, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 }, + IPA_TX_INSTANCE_DL }, + + [IPA_5_5][IPA_CLIENT_TEST2_CONS] = { + true, IPA_v5_5_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 33, 10, 9, 9, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, + IPA_TX_INSTANCE_DL }, + + [IPA_5_5][IPA_CLIENT_TEST3_CONS] = { + true, IPA_v5_5_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 30, 23, 9, 9, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, + IPA_TX_INSTANCE_DL }, + + [IPA_5_5][IPA_CLIENT_TEST4_CONS] = { + true, IPA_v5_5_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 24, 1, 9, 9, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 }, + IPA_TX_INSTANCE_DL }, + + /* IPA_5_5_XR */ + + [IPA_5_5_XR][IPA_CLIENT_APPS_LAN_PROD] = { + true, IPA_v5_5_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 9, 19, 26, 32, IPA_EE_AP, GSI_SMART_PRE_FETCH, 4}, + IPA_TX_INSTANCE_NA }, + [IPA_5_5_XR][IPA_CLIENT_APPS_CMD_PROD] = { + true, IPA_v5_5_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY, + QMB_MASTER_SELECT_DDR, + { 14, 11, 20, 24, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0}, + IPA_TX_INSTANCE_NA }, + [IPA_5_5_XR][IPA_CLIENT_WLAN2_PROD] = { + true, IPA_v5_5_GROUP_UL, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 6, 16, 8, 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 2}, + IPA_TX_INSTANCE_NA }, + + [IPA_5_5_XR][IPA_CLIENT_APPS_LAN_CONS] = { + true, IPA_v5_5_GROUP_UL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 17, 13, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0}, + IPA_TX_INSTANCE_UL }, + + [IPA_5_5_XR][IPA_CLIENT_WLAN2_CONS] = { + true, IPA_v5_5_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 28, 3, 8, 14, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3}, + IPA_TX_INSTANCE_DL }, + + [IPA_5_5_XR][IPA_CLIENT_UC_RTP1_CONS] = { + true, IPA_v5_5_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 31, 2, 9, 9, IPA_EE_UC, GSI_SMART_PRE_FETCH, 3}, + IPA_TX_INSTANCE_DL}, + + [IPA_5_5_XR][IPA_CLIENT_UC_RTP2_CONS] = { + true, IPA_v5_5_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 32, 3, 9, 9, IPA_EE_UC, GSI_SMART_PRE_FETCH, 3}, + IPA_TX_INSTANCE_DL}, + + [IPA_5_5_XR][IPA_CLIENT_UC_RTP3_CONS] = { + true, IPA_v5_5_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 33, 4, 9, 9, IPA_EE_UC, GSI_SMART_PRE_FETCH, 3}, + IPA_TX_INSTANCE_DL}, + + [IPA_5_5_XR][IPA_CLIENT_UC_RTP4_CONS] = { + true, IPA_v5_5_GROUP_DL, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 34, 5, 9, 9, IPA_EE_UC, GSI_SMART_PRE_FETCH, 3}, + IPA_TX_INSTANCE_DL}, +}; + +static struct ipa3_mem_partition ipa_3_0_mem_part = { + .uc_ofst = 0x0, + .uc_size = 0x80, + .ofst_start = 0x280, + .v4_flt_hash_ofst = 0x288, + .v4_flt_hash_size = 0x78, + .v4_flt_hash_size_ddr = 0x4000, + .v4_flt_nhash_ofst = 0x308, + .v4_flt_nhash_size = 0x78, + .v4_flt_nhash_size_ddr = 0x4000, + .v6_flt_hash_ofst = 0x388, + .v6_flt_hash_size = 0x78, + .v6_flt_hash_size_ddr = 0x4000, + .v6_flt_nhash_ofst = 0x408, + .v6_flt_nhash_size = 0x78, + .v6_flt_nhash_size_ddr = 0x4000, + .v4_rt_num_index = 0xf, + .v4_modem_rt_index_lo = 0x0, + .v4_modem_rt_index_hi = 0x7, + .v4_apps_rt_index_lo = 0x8, + .v4_apps_rt_index_hi = 0xe, + .v4_rt_hash_ofst = 0x488, + .v4_rt_hash_size = 0x78, + .v4_rt_hash_size_ddr = 0x4000, + .v4_rt_nhash_ofst = 0x508, + .v4_rt_nhash_size = 0x78, + .v4_rt_nhash_size_ddr = 0x4000, + .v6_rt_num_index = 0xf, + .v6_modem_rt_index_lo = 0x0, + .v6_modem_rt_index_hi = 0x7, + .v6_apps_rt_index_lo = 0x8, + .v6_apps_rt_index_hi = 0xe, + .v6_rt_hash_ofst = 0x588, + .v6_rt_hash_size = 0x78, + .v6_rt_hash_size_ddr = 0x4000, + .v6_rt_nhash_ofst = 0x608, + .v6_rt_nhash_size = 0x78, + .v6_rt_nhash_size_ddr = 0x4000, + .modem_hdr_ofst = 0x688, + .modem_hdr_size = 0x140, + .apps_hdr_ofst = 0x7c8, + .apps_hdr_size = 0x0, + .apps_hdr_size_ddr = 0x800, + .modem_hdr_proc_ctx_ofst = 0x7d0, + .modem_hdr_proc_ctx_size = 0x200, + .apps_hdr_proc_ctx_ofst = 0x9d0, + .apps_hdr_proc_ctx_size = 0x200, + .apps_hdr_proc_ctx_size_ddr = 0x0, + .modem_comp_decomp_ofst = 0x0, + .modem_comp_decomp_size = 0x0, + .modem_ofst = 0xBD8, + .modem_size = 0x1424, + .apps_v4_flt_hash_ofst = 0x2000, + .apps_v4_flt_hash_size = 0x0, + .apps_v4_flt_nhash_ofst = 0x2000, + .apps_v4_flt_nhash_size = 0x0, + .apps_v6_flt_hash_ofst = 0x2000, + .apps_v6_flt_hash_size = 0x0, + .apps_v6_flt_nhash_ofst = 0x2000, + .apps_v6_flt_nhash_size = 0x0, + .uc_info_ofst = 0x80, + .uc_info_size = 0x200, + .end_ofst = 0x2000, + .apps_v4_rt_hash_ofst = 0x2000, + .apps_v4_rt_hash_size = 0x0, + .apps_v4_rt_nhash_ofst = 0x2000, + .apps_v4_rt_nhash_size = 0x0, + .apps_v6_rt_hash_ofst = 0x2000, + .apps_v6_rt_hash_size = 0x0, + .apps_v6_rt_nhash_ofst = 0x2000, + .apps_v6_rt_nhash_size = 0x0, + .uc_descriptor_ram_ofst = 0x2000, + .uc_descriptor_ram_size = 0x0, + .pdn_config_ofst = 0x2000, + .pdn_config_size = 0x0, + .stats_quota_q6_ofst = 0x2000, + .stats_quota_q6_size = 0x0, + .stats_quota_ap_ofst = 0, + .stats_quota_ap_size = 0, + .stats_tethering_ofst = 0x2000, + .stats_tethering_size = 0x0, + .stats_flt_v4_ofst = 0x2000, + .stats_flt_v4_size = 0x0, + .stats_flt_v6_ofst = 0x2000, + .stats_flt_v6_size = 0x0, + .stats_rt_v4_ofst = 0x2000, + .stats_rt_v4_size = 0x0, + .stats_rt_v6_ofst = 0x2000, + .stats_rt_v6_size = 0x0, + .stats_drop_ofst = 0x2000, + .stats_drop_size = 0x0, +}; + +static struct ipa3_mem_partition ipa_4_1_mem_part = { + .uc_ofst = 0x0, + .uc_size = 0x80, + .ofst_start = 0x280, + .v4_flt_hash_ofst = 0x288, + .v4_flt_hash_size = 0x78, + .v4_flt_hash_size_ddr = 0x4000, + .v4_flt_nhash_ofst = 0x308, + .v4_flt_nhash_size = 0x78, + .v4_flt_nhash_size_ddr = 0x4000, + .v6_flt_hash_ofst = 0x388, + .v6_flt_hash_size = 0x78, + .v6_flt_hash_size_ddr = 0x4000, + .v6_flt_nhash_ofst = 0x408, + .v6_flt_nhash_size = 0x78, + .v6_flt_nhash_size_ddr = 0x4000, + .v4_rt_num_index = 0xf, + .v4_modem_rt_index_lo = 0x0, + .v4_modem_rt_index_hi = 0x7, + .v4_apps_rt_index_lo = 0x8, + .v4_apps_rt_index_hi = 0xe, + .v4_rt_hash_ofst = 0x488, + .v4_rt_hash_size = 0x78, + .v4_rt_hash_size_ddr = 0x4000, + .v4_rt_nhash_ofst = 0x508, + .v4_rt_nhash_size = 0x78, + .v4_rt_nhash_size_ddr = 0x4000, + .v6_rt_num_index = 0xf, + .v6_modem_rt_index_lo = 0x0, + .v6_modem_rt_index_hi = 0x7, + .v6_apps_rt_index_lo = 0x8, + .v6_apps_rt_index_hi = 0xe, + .v6_rt_hash_ofst = 0x588, + .v6_rt_hash_size = 0x78, + .v6_rt_hash_size_ddr = 0x4000, + .v6_rt_nhash_ofst = 0x608, + .v6_rt_nhash_size = 0x78, + .v6_rt_nhash_size_ddr = 0x4000, + .modem_hdr_ofst = 0x688, + .modem_hdr_size = 0x140, + .apps_hdr_ofst = 0x7c8, + .apps_hdr_size = 0x0, + .apps_hdr_size_ddr = 0x800, + .modem_hdr_proc_ctx_ofst = 0x7d0, + .modem_hdr_proc_ctx_size = 0x200, + .apps_hdr_proc_ctx_ofst = 0x9d0, + .apps_hdr_proc_ctx_size = 0x200, + .apps_hdr_proc_ctx_size_ddr = 0x0, + .modem_comp_decomp_ofst = 0x0, + .modem_comp_decomp_size = 0x0, + .modem_ofst = 0x13f0, + .modem_size = 0x100c, + .apps_v4_flt_hash_ofst = 0x23fc, + .apps_v4_flt_hash_size = 0x0, + .apps_v4_flt_nhash_ofst = 0x23fc, + .apps_v4_flt_nhash_size = 0x0, + .apps_v6_flt_hash_ofst = 0x23fc, + .apps_v6_flt_hash_size = 0x0, + .apps_v6_flt_nhash_ofst = 0x23fc, + .apps_v6_flt_nhash_size = 0x0, + .uc_info_ofst = 0x80, + .uc_info_size = 0x200, + .end_ofst = 0x2800, + .apps_v4_rt_hash_ofst = 0x23fc, + .apps_v4_rt_hash_size = 0x0, + .apps_v4_rt_nhash_ofst = 0x23fc, + .apps_v4_rt_nhash_size = 0x0, + .apps_v6_rt_hash_ofst = 0x23fc, + .apps_v6_rt_hash_size = 0x0, + .apps_v6_rt_nhash_ofst = 0x23fc, + .apps_v6_rt_nhash_size = 0x0, + .uc_descriptor_ram_ofst = 0x2400, + .uc_descriptor_ram_size = 0x400, + .pdn_config_ofst = 0xbd8, + .pdn_config_size = 0x50, + .stats_quota_q6_ofst = 0xc30, + .stats_quota_q6_size = 0x60, + .stats_quota_ap_ofst = 0, + .stats_quota_ap_size = 0, + .stats_tethering_ofst = 0xc90, + .stats_tethering_size = 0x140, + .stats_flt_v4_ofst = 0xdd0, + .stats_flt_v4_size = 0x180, + .stats_flt_v6_ofst = 0xf50, + .stats_flt_v6_size = 0x180, + .stats_rt_v4_ofst = 0x10d0, + .stats_rt_v4_size = 0x180, + .stats_rt_v6_ofst = 0x1250, + .stats_rt_v6_size = 0x180, + .stats_drop_ofst = 0x13d0, + .stats_drop_size = 0x20, +}; + +static struct ipa3_mem_partition ipa_4_2_mem_part = { + .uc_ofst = 0x0, + .uc_size = 0x80, + .ofst_start = 0x280, + .v4_flt_hash_ofst = 0x288, + .v4_flt_hash_size = 0x0, + .v4_flt_hash_size_ddr = 0x0, + .v4_flt_nhash_ofst = 0x290, + .v4_flt_nhash_size = 0x78, + .v4_flt_nhash_size_ddr = 0x4000, + .v6_flt_hash_ofst = 0x310, + .v6_flt_hash_size = 0x0, + .v6_flt_hash_size_ddr = 0x0, + .v6_flt_nhash_ofst = 0x318, + .v6_flt_nhash_size = 0x78, + .v6_flt_nhash_size_ddr = 0x4000, + .v4_rt_num_index = 0xf, + .v4_modem_rt_index_lo = 0x0, + .v4_modem_rt_index_hi = 0x7, + .v4_apps_rt_index_lo = 0x8, + .v4_apps_rt_index_hi = 0xe, + .v4_rt_hash_ofst = 0x398, + .v4_rt_hash_size = 0x0, + .v4_rt_hash_size_ddr = 0x0, + .v4_rt_nhash_ofst = 0x3A0, + .v4_rt_nhash_size = 0x78, + .v4_rt_nhash_size_ddr = 0x4000, + .v6_rt_num_index = 0xf, + .v6_modem_rt_index_lo = 0x0, + .v6_modem_rt_index_hi = 0x7, + .v6_apps_rt_index_lo = 0x8, + .v6_apps_rt_index_hi = 0xe, + .v6_rt_hash_ofst = 0x420, + .v6_rt_hash_size = 0x0, + .v6_rt_hash_size_ddr = 0x0, + .v6_rt_nhash_ofst = 0x428, + .v6_rt_nhash_size = 0x78, + .v6_rt_nhash_size_ddr = 0x4000, + .modem_hdr_ofst = 0x4A8, + .modem_hdr_size = 0x140, + .apps_hdr_ofst = 0x5E8, + .apps_hdr_size = 0x0, + .apps_hdr_size_ddr = 0x800, + .modem_hdr_proc_ctx_ofst = 0x5F0, + .modem_hdr_proc_ctx_size = 0x200, + .apps_hdr_proc_ctx_ofst = 0x7F0, + .apps_hdr_proc_ctx_size = 0x200, + .apps_hdr_proc_ctx_size_ddr = 0x0, + .modem_comp_decomp_ofst = 0x0, + .modem_comp_decomp_size = 0x0, + .modem_ofst = 0xbf0, + .modem_size = 0x140c, + .apps_v4_flt_hash_ofst = 0x1bfc, + .apps_v4_flt_hash_size = 0x0, + .apps_v4_flt_nhash_ofst = 0x1bfc, + .apps_v4_flt_nhash_size = 0x0, + .apps_v6_flt_hash_ofst = 0x1bfc, + .apps_v6_flt_hash_size = 0x0, + .apps_v6_flt_nhash_ofst = 0x1bfc, + .apps_v6_flt_nhash_size = 0x0, + .uc_info_ofst = 0x80, + .uc_info_size = 0x200, + .end_ofst = 0x2000, + .apps_v4_rt_hash_ofst = 0x1bfc, + .apps_v4_rt_hash_size = 0x0, + .apps_v4_rt_nhash_ofst = 0x1bfc, + .apps_v4_rt_nhash_size = 0x0, + .apps_v6_rt_hash_ofst = 0x1bfc, + .apps_v6_rt_hash_size = 0x0, + .apps_v6_rt_nhash_ofst = 0x1bfc, + .apps_v6_rt_nhash_size = 0x0, + .uc_descriptor_ram_ofst = 0x2000, + .uc_descriptor_ram_size = 0x0, + .pdn_config_ofst = 0x9F8, + .pdn_config_size = 0x50, + .stats_quota_q6_ofst = 0xa50, + .stats_quota_q6_size = 0x60, + .stats_quota_ap_ofst = 0, + .stats_quota_ap_size = 0, + .stats_tethering_ofst = 0xab0, + .stats_tethering_size = 0x140, + .stats_flt_v4_ofst = 0xbf0, + .stats_flt_v4_size = 0x0, + .stats_flt_v6_ofst = 0xbf0, + .stats_flt_v6_size = 0x0, + .stats_rt_v4_ofst = 0xbf0, + .stats_rt_v4_size = 0x0, + .stats_rt_v6_ofst = 0xbf0, + .stats_rt_v6_size = 0x0, + .stats_drop_ofst = 0xbf0, + .stats_drop_size = 0x0, +}; + +static struct ipa3_mem_partition ipa_4_5_mem_part = { + .uc_ofst = 0x0, + .uc_size = 0x80, + .uc_info_ofst = 0x80, + .uc_info_size = 0x200, + .ofst_start = 0x280, + .v4_flt_hash_ofst = 0x288, + .v4_flt_hash_size = 0x78, + .v4_flt_hash_size_ddr = 0x4000, + .v4_flt_nhash_ofst = 0x308, + .v4_flt_nhash_size = 0x78, + .v4_flt_nhash_size_ddr = 0x4000, + .v6_flt_hash_ofst = 0x388, + .v6_flt_hash_size = 0x78, + .v6_flt_hash_size_ddr = 0x4000, + .v6_flt_nhash_ofst = 0x408, + .v6_flt_nhash_size = 0x78, + .v6_flt_nhash_size_ddr = 0x4000, + .v4_rt_num_index = 0xf, + .v4_modem_rt_index_lo = 0x0, + .v4_modem_rt_index_hi = 0x7, + .v4_apps_rt_index_lo = 0x8, + .v4_apps_rt_index_hi = 0xe, + .v4_rt_hash_ofst = 0x488, + .v4_rt_hash_size = 0x78, + .v4_rt_hash_size_ddr = 0x4000, + .v4_rt_nhash_ofst = 0x508, + .v4_rt_nhash_size = 0x78, + .v4_rt_nhash_size_ddr = 0x4000, + .v6_rt_num_index = 0xf, + .v6_modem_rt_index_lo = 0x0, + .v6_modem_rt_index_hi = 0x7, + .v6_apps_rt_index_lo = 0x8, + .v6_apps_rt_index_hi = 0xe, + .v6_rt_hash_ofst = 0x588, + .v6_rt_hash_size = 0x78, + .v6_rt_hash_size_ddr = 0x4000, + .v6_rt_nhash_ofst = 0x608, + .v6_rt_nhash_size = 0x78, + .v6_rt_nhash_size_ddr = 0x4000, + .modem_hdr_ofst = 0x688, + .modem_hdr_size = 0x240, + .apps_hdr_ofst = 0x8c8, + .apps_hdr_size = 0x200, + .apps_hdr_size_ddr = 0x800, + .modem_hdr_proc_ctx_ofst = 0xad0, + .modem_hdr_proc_ctx_size = 0xb20, + .apps_hdr_proc_ctx_ofst = 0x15f0, + .apps_hdr_proc_ctx_size = 0x200, + .apps_hdr_proc_ctx_size_ddr = 0x0, + .nat_tbl_ofst = 0x1800, + .nat_tbl_size = 0xd00, + .stats_quota_q6_ofst = 0x2510, + .stats_quota_q6_size = 0x30, + .stats_quota_ap_ofst = 0x2540, + .stats_quota_ap_size = 0x48, + .stats_tethering_ofst = 0x2588, + .stats_tethering_size = 0x238, + .stats_flt_v4_ofst = 0, + .stats_flt_v4_size = 0, + .stats_flt_v6_ofst = 0, + .stats_flt_v6_size = 0, + .stats_rt_v4_ofst = 0, + .stats_rt_v4_size = 0, + .stats_rt_v6_ofst = 0, + .stats_rt_v6_size = 0, + .stats_fnr_ofst = 0x27c0, + .stats_fnr_size = 0x800, + .stats_drop_ofst = 0x2fc0, + .stats_drop_size = 0x20, + .modem_comp_decomp_ofst = 0x0, + .modem_comp_decomp_size = 0x0, + .modem_ofst = 0x2fe8, + .modem_size = 0x800, + .apps_v4_flt_hash_ofst = 0x2718, + .apps_v4_flt_hash_size = 0x0, + .apps_v4_flt_nhash_ofst = 0x2718, + .apps_v4_flt_nhash_size = 0x0, + .apps_v6_flt_hash_ofst = 0x2718, + .apps_v6_flt_hash_size = 0x0, + .apps_v6_flt_nhash_ofst = 0x2718, + .apps_v6_flt_nhash_size = 0x0, + .apps_v4_rt_hash_ofst = 0x2718, + .apps_v4_rt_hash_size = 0x0, + .apps_v4_rt_nhash_ofst = 0x2718, + .apps_v4_rt_nhash_size = 0x0, + .apps_v6_rt_hash_ofst = 0x2718, + .apps_v6_rt_hash_size = 0x0, + .apps_v6_rt_nhash_ofst = 0x2718, + .apps_v6_rt_nhash_size = 0x0, + .uc_descriptor_ram_ofst = 0x3800, + .uc_descriptor_ram_size = 0x1000, + .pdn_config_ofst = 0x4800, + .pdn_config_size = 0x50, + .end_ofst = 0x4850, +}; + +static struct ipa3_mem_partition ipa_4_7_mem_part = { + .uc_ofst = 0x0, + .uc_size = 0x80, + .uc_info_ofst = 0x80, + .uc_info_size = 0x200, + .ofst_start = 0x280, + .v4_flt_hash_ofst = 0x288, + .v4_flt_hash_size = 0x78, + .v4_flt_hash_size_ddr = 0x4000, + .v4_flt_nhash_ofst = 0x308, + .v4_flt_nhash_size = 0x78, + .v4_flt_nhash_size_ddr = 0x4000, + .v6_flt_hash_ofst = 0x388, + .v6_flt_hash_size = 0x78, + .v6_flt_hash_size_ddr = 0x4000, + .v6_flt_nhash_ofst = 0x408, + .v6_flt_nhash_size = 0x78, + .v6_flt_nhash_size_ddr = 0x4000, + .v4_rt_num_index = 0xf, + .v4_modem_rt_index_lo = 0x0, + .v4_modem_rt_index_hi = 0x7, + .v4_apps_rt_index_lo = 0x8, + .v4_apps_rt_index_hi = 0xe, + .v4_rt_hash_ofst = 0x488, + .v4_rt_hash_size = 0x78, + .v4_rt_hash_size_ddr = 0x4000, + .v4_rt_nhash_ofst = 0x508, + .v4_rt_nhash_size = 0x78, + .v4_rt_nhash_size_ddr = 0x4000, + .v6_rt_num_index = 0xf, + .v6_modem_rt_index_lo = 0x0, + .v6_modem_rt_index_hi = 0x7, + .v6_apps_rt_index_lo = 0x8, + .v6_apps_rt_index_hi = 0xe, + .v6_rt_hash_ofst = 0x588, + .v6_rt_hash_size = 0x78, + .v6_rt_hash_size_ddr = 0x4000, + .v6_rt_nhash_ofst = 0x608, + .v6_rt_nhash_size = 0x78, + .v6_rt_nhash_size_ddr = 0x4000, + .modem_hdr_ofst = 0x688, + .modem_hdr_size = 0x240, + .apps_hdr_ofst = 0x8c8, + .apps_hdr_size = 0x200, + .apps_hdr_size_ddr = 0x800, + .modem_hdr_proc_ctx_ofst = 0xad0, + .modem_hdr_proc_ctx_size = 0x200, + .apps_hdr_proc_ctx_ofst = 0xcd0, + .apps_hdr_proc_ctx_size = 0x200, + .apps_hdr_proc_ctx_size_ddr = 0x0, + .nat_tbl_ofst = 0xee0, + .nat_tbl_size = 0xd00, + .pdn_config_ofst = 0x1be8, + .pdn_config_size = 0x50, + .stats_quota_q6_ofst = 0x1c40, + .stats_quota_q6_size = 0x30, + .stats_quota_ap_ofst = 0x1c70, + .stats_quota_ap_size = 0x48, + .stats_tethering_ofst = 0x1cb8, + .stats_tethering_size = 0x238, + .stats_flt_v4_ofst = 0, + .stats_flt_v4_size = 0, + .stats_flt_v6_ofst = 0, + .stats_flt_v6_size = 0, + .stats_rt_v4_ofst = 0, + .stats_rt_v4_size = 0, + .stats_rt_v6_ofst = 0, + .stats_rt_v6_size = 0, + .stats_fnr_ofst = 0x1ef0, + .stats_fnr_size = 0x0, + .stats_drop_ofst = 0x1ef0, + .stats_drop_size = 0x20, + .modem_comp_decomp_ofst = 0x0, + .modem_comp_decomp_size = 0x0, + .modem_ofst = 0x1f18, + .modem_size = 0x100c, + .apps_v4_flt_hash_ofst = 0x1f18, + .apps_v4_flt_hash_size = 0x0, + .apps_v4_flt_nhash_ofst = 0x1f18, + .apps_v4_flt_nhash_size = 0x0, + .apps_v6_flt_hash_ofst = 0x1f18, + .apps_v6_flt_hash_size = 0x0, + .apps_v6_flt_nhash_ofst = 0x1f18, + .apps_v6_flt_nhash_size = 0x0, + .apps_v4_rt_hash_ofst = 0x1f18, + .apps_v4_rt_hash_size = 0x0, + .apps_v4_rt_nhash_ofst = 0x1f18, + .apps_v4_rt_nhash_size = 0x0, + .apps_v6_rt_hash_ofst = 0x1f18, + .apps_v6_rt_hash_size = 0x0, + .apps_v6_rt_nhash_ofst = 0x1f18, + .apps_v6_rt_nhash_size = 0x0, + .uc_descriptor_ram_ofst = 0x3000, + .uc_descriptor_ram_size = 0x0000, + .end_ofst = 0x3000, +}; + +static struct ipa3_mem_partition ipa_4_9_mem_part = { + .uc_ofst = 0x0, + .uc_size = 0x80, + .uc_info_ofst = 0x80, + .uc_info_size = 0x200, + .ofst_start = 0x280, + .v4_flt_hash_ofst = 0x288, + .v4_flt_hash_size = 0x78, + .v4_flt_hash_size_ddr = 0x4000, + .v4_flt_nhash_ofst = 0x308, + .v4_flt_nhash_size = 0x78, + .v4_flt_nhash_size_ddr = 0x4000, + .v6_flt_hash_ofst = 0x388, + .v6_flt_hash_size = 0x78, + .v6_flt_hash_size_ddr = 0x4000, + .v6_flt_nhash_ofst = 0x408, + .v6_flt_nhash_size = 0x78, + .v6_flt_nhash_size_ddr = 0x4000, + .v4_rt_num_index = 0xf, + .v4_modem_rt_index_lo = 0x0, + .v4_modem_rt_index_hi = 0x7, + .v4_apps_rt_index_lo = 0x8, + .v4_apps_rt_index_hi = 0xe, + .v4_rt_hash_ofst = 0x488, + .v4_rt_hash_size = 0x78, + .v4_rt_hash_size_ddr = 0x4000, + .v4_rt_nhash_ofst = 0x508, + .v4_rt_nhash_size = 0x78, + .v4_rt_nhash_size_ddr = 0x4000, + .v6_rt_num_index = 0xf, + .v6_modem_rt_index_lo = 0x0, + .v6_modem_rt_index_hi = 0x7, + .v6_apps_rt_index_lo = 0x8, + .v6_apps_rt_index_hi = 0xe, + .v6_rt_hash_ofst = 0x588, + .v6_rt_hash_size = 0x78, + .v6_rt_hash_size_ddr = 0x4000, + .v6_rt_nhash_ofst = 0x608, + .v6_rt_nhash_size = 0x78, + .v6_rt_nhash_size_ddr = 0x4000, + .modem_hdr_ofst = 0x688, + .modem_hdr_size = 0x240, + .apps_hdr_ofst = 0x8c8, + .apps_hdr_size = 0x200, + .apps_hdr_size_ddr = 0x800, + .modem_hdr_proc_ctx_ofst = 0xad0, + .modem_hdr_proc_ctx_size = 0xb20, + .apps_hdr_proc_ctx_ofst = 0x15f0, + .apps_hdr_proc_ctx_size = 0x200, + .apps_hdr_proc_ctx_size_ddr = 0x0, + .nat_tbl_ofst = 0x1800, + .nat_tbl_size = 0xd00, + .stats_quota_q6_ofst = 0x2510, + .stats_quota_q6_size = 0x30, + .stats_quota_ap_ofst = 0x2540, + .stats_quota_ap_size = 0x48, + .stats_tethering_ofst = 0x2588, + .stats_tethering_size = 0x238, + .stats_flt_v4_ofst = 0, + .stats_flt_v4_size = 0, + .stats_flt_v6_ofst = 0, + .stats_flt_v6_size = 0, + .stats_rt_v4_ofst = 0, + .stats_rt_v4_size = 0, + .stats_rt_v6_ofst = 0, + .stats_rt_v6_size = 0, + .stats_fnr_ofst = 0x27c0, + .stats_fnr_size = 0x800, + .stats_drop_ofst = 0x2fc0, + .stats_drop_size = 0x20, + .modem_comp_decomp_ofst = 0x0, + .modem_comp_decomp_size = 0x0, + .modem_ofst = 0x2fe8, + .modem_size = 0x800, + .apps_v4_flt_hash_ofst = 0x2718, + .apps_v4_flt_hash_size = 0x0, + .apps_v4_flt_nhash_ofst = 0x2718, + .apps_v4_flt_nhash_size = 0x0, + .apps_v6_flt_hash_ofst = 0x2718, + .apps_v6_flt_hash_size = 0x0, + .apps_v6_flt_nhash_ofst = 0x2718, + .apps_v6_flt_nhash_size = 0x0, + .apps_v4_rt_hash_ofst = 0x2718, + .apps_v4_rt_hash_size = 0x0, + .apps_v4_rt_nhash_ofst = 0x2718, + .apps_v4_rt_nhash_size = 0x0, + .apps_v6_rt_hash_ofst = 0x2718, + .apps_v6_rt_hash_size = 0x0, + .apps_v6_rt_nhash_ofst = 0x2718, + .apps_v6_rt_nhash_size = 0x0, + .uc_descriptor_ram_ofst = 0x3800, + .uc_descriptor_ram_size = 0x1000, + .pdn_config_ofst = 0x4800, + .pdn_config_size = 0x50, + .end_ofst = 0x4850, +}; + +static struct ipa3_mem_partition ipa_4_11_mem_part = { + .uc_ofst = 0x0, + .uc_size = 0x80, + .uc_info_ofst = 0x80, + .uc_info_size = 0x200, + .ofst_start = 0x280, + .v4_flt_hash_ofst = 0x288, + .v4_flt_hash_size = 0x78, + .v4_flt_hash_size_ddr = 0x4000, + .v4_flt_nhash_ofst = 0x308, + .v4_flt_nhash_size = 0x78, + .v4_flt_nhash_size_ddr = 0x4000, + .v6_flt_hash_ofst = 0x388, + .v6_flt_hash_size = 0x78, + .v6_flt_hash_size_ddr = 0x4000, + .v6_flt_nhash_ofst = 0x408, + .v6_flt_nhash_size = 0x78, + .v6_flt_nhash_size_ddr = 0x4000, + .v4_rt_num_index = 0xf, + .v4_modem_rt_index_lo = 0x0, + .v4_modem_rt_index_hi = 0x7, + .v4_apps_rt_index_lo = 0x8, + .v4_apps_rt_index_hi = 0xe, + .v4_rt_hash_ofst = 0x488, + .v4_rt_hash_size = 0x78, + .v4_rt_hash_size_ddr = 0x4000, + .v4_rt_nhash_ofst = 0x508, + .v4_rt_nhash_size = 0x78, + .v4_rt_nhash_size_ddr = 0x4000, + .v6_rt_num_index = 0xf, + .v6_modem_rt_index_lo = 0x0, + .v6_modem_rt_index_hi = 0x7, + .v6_apps_rt_index_lo = 0x8, + .v6_apps_rt_index_hi = 0xe, + .v6_rt_hash_ofst = 0x588, + .v6_rt_hash_size = 0x78, + .v6_rt_hash_size_ddr = 0x4000, + .v6_rt_nhash_ofst = 0x608, + .v6_rt_nhash_size = 0x78, + .v6_rt_nhash_size_ddr = 0x4000, + .modem_hdr_ofst = 0x688, + .modem_hdr_size = 0x240, + .apps_hdr_ofst = 0x8c8, + .apps_hdr_size = 0x200, + .apps_hdr_size_ddr = 0x800, + .modem_hdr_proc_ctx_ofst = 0xad0, + .modem_hdr_proc_ctx_size = 0xAC0, + .apps_hdr_proc_ctx_ofst = 0x1590, + .apps_hdr_proc_ctx_size = 0x200, + .apps_hdr_proc_ctx_size_ddr = 0x0, + .nat_tbl_ofst = 0x17A0, + .nat_tbl_size = 0x800, + .pdn_config_ofst = 0x24A8, + .pdn_config_size = 0x50, + .stats_quota_q6_ofst = 0x2500, + .stats_quota_q6_size = 0x30, + .stats_quota_ap_ofst = 0x2530, + .stats_quota_ap_size = 0x48, + .stats_tethering_ofst = 0x2578, + .stats_tethering_size = 0x238, + .stats_flt_v4_ofst = 0, + .stats_flt_v4_size = 0, + .stats_flt_v6_ofst = 0, + .stats_flt_v6_size = 0, + .stats_rt_v4_ofst = 0, + .stats_rt_v4_size = 0, + .stats_rt_v6_ofst = 0, + .stats_rt_v6_size = 0, + .stats_fnr_ofst = 0x27B0, + .stats_fnr_size = 0x0, + .stats_drop_ofst = 0x27B0, + .stats_drop_size = 0x20, + .modem_comp_decomp_ofst = 0x0, + .modem_comp_decomp_size = 0x0, + .modem_ofst = 0x27D8, + .modem_size = 0x800, + .apps_v4_flt_hash_ofst = 0x27B0, + .apps_v4_flt_hash_size = 0x0, + .apps_v4_flt_nhash_ofst = 0x27B0, + .apps_v4_flt_nhash_size = 0x0, + .apps_v6_flt_hash_ofst = 0x27B0, + .apps_v6_flt_hash_size = 0x0, + .apps_v6_flt_nhash_ofst = 0x27B0, + .apps_v6_flt_nhash_size = 0x0, + .apps_v4_rt_hash_ofst = 0x27B0, + .apps_v4_rt_hash_size = 0x0, + .apps_v4_rt_nhash_ofst = 0x27B0, + .apps_v4_rt_nhash_size = 0x0, + .apps_v6_rt_hash_ofst = 0x27B0, + .apps_v6_rt_hash_size = 0x0, + .apps_v6_rt_nhash_ofst = 0x27B0, + .apps_v6_rt_nhash_size = 0x0, + .uc_descriptor_ram_ofst = 0x3000, + .uc_descriptor_ram_size = 0x0000, + .end_ofst = 0x3000, +}; + +static struct ipa3_mem_partition ipa_5_0_mem_part = { + .uc_descriptor_ram_ofst = 0x0, + .uc_descriptor_ram_size = 0x1000, + .uc_ofst = 0x1000, + .uc_size = 0x80, + .uc_info_ofst = 0x1080, + .uc_info_size = 0x200, + .ofst_start = 0x1280, + .v4_flt_hash_ofst = 0x1288, + .v4_flt_hash_size = 0x78, + .v4_flt_hash_size_ddr = 0x4000, + .v4_flt_nhash_ofst = 0x1308, + .v4_flt_nhash_size = 0x78, + .v4_flt_nhash_size_ddr = 0x4000, + .v6_flt_hash_ofst = 0x1388, + .v6_flt_hash_size = 0x78, + .v6_flt_hash_size_ddr = 0x4000, + .v6_flt_nhash_ofst = 0x1408, + .v6_flt_nhash_size = 0x78, + .v6_flt_nhash_size_ddr = 0x4000, + .v4_rt_num_index = 0x13, + .v4_modem_rt_index_lo = 0x0, + .v4_modem_rt_index_hi = 0xa, + .v4_apps_rt_index_lo = 0xb, + .v4_apps_rt_index_hi = 0x12, + .v4_rt_hash_ofst = 0x1488, + .v4_rt_hash_size = 0x98, + .v4_rt_hash_size_ddr = 0x4000, + .v4_rt_nhash_ofst = 0x1528, + .v4_rt_nhash_size = 0x98, + .v4_rt_nhash_size_ddr = 0x4000, + .v6_rt_num_index = 0x13, + .v6_modem_rt_index_lo = 0x0, + .v6_modem_rt_index_hi = 0xa, + .v6_apps_rt_index_lo = 0xb, + .v6_apps_rt_index_hi = 0x12, + .v6_rt_hash_ofst = 0x15c8, + .v6_rt_hash_size = 0x98, + .v6_rt_hash_size_ddr = 0x4000, + .v6_rt_nhash_ofst = 0x1668, + .v6_rt_nhash_size = 0x098, + .v6_rt_nhash_size_ddr = 0x4000, + .modem_hdr_ofst = 0x1708, + .modem_hdr_size = 0x240, + .apps_hdr_ofst = 0x1948, + .apps_hdr_size = 0x1e0, + .apps_hdr_size_ddr = 0x800, + .modem_hdr_proc_ctx_ofst = 0x1b40, + .modem_hdr_proc_ctx_size = 0xb20, + .apps_hdr_proc_ctx_ofst = 0x2660, + .apps_hdr_proc_ctx_size = 0x200, + .apps_hdr_proc_ctx_size_ddr = 0x0, + .stats_quota_q6_ofst = 0x2868, + .stats_quota_q6_size = 0x60, + .stats_quota_ap_ofst = 0x28C8, + .stats_quota_ap_size = 0x48, + .stats_tethering_ofst = 0x2910, + .stats_tethering_size = 0x0, + .apps_v4_flt_nhash_ofst = 0x2918, + .apps_v4_flt_nhash_size = 0x188, + .apps_v6_flt_nhash_ofst = 0x2aa0, + .apps_v6_flt_nhash_size = 0x228, + .stats_flt_v4_ofst = 0, + .stats_flt_v4_size = 0, + .stats_flt_v6_ofst = 0, + .stats_flt_v6_size = 0, + .stats_rt_v4_ofst = 0, + .stats_rt_v4_size = 0, + .stats_rt_v6_ofst = 0, + .stats_rt_v6_size = 0, + .stats_fnr_ofst = 0x2cd0, + .stats_fnr_size = 0xba0, + .stats_drop_ofst = 0x3870, + .stats_drop_size = 0x20, + .modem_comp_decomp_ofst = 0x0, + .modem_comp_decomp_size = 0x0, + .modem_ofst = 0x3898, + .modem_size = 0xd48, + .nat_tbl_ofst = 0x45e0, + .nat_tbl_size = 0x900, + .apps_v4_flt_hash_ofst = 0x2718, + .apps_v4_flt_hash_size = 0x0, + .apps_v6_flt_hash_ofst = 0x2718, + .apps_v6_flt_hash_size = 0x0, + .apps_v4_rt_hash_ofst = 0x2718, + .apps_v4_rt_hash_size = 0x0, + .apps_v4_rt_nhash_ofst = 0x2718, + .apps_v4_rt_nhash_size = 0x0, + .apps_v6_rt_hash_ofst = 0x2718, + .apps_v6_rt_hash_size = 0x0, + .apps_v6_rt_nhash_ofst = 0x2718, + .apps_v6_rt_nhash_size = 0x0, + .pdn_config_ofst = 0x4ee8, + .pdn_config_size = 0x100, + .end_ofst = 0x4fe8, +}; + +static struct ipa3_mem_partition ipa_5_1_mem_part = { + .uc_descriptor_ram_ofst = 0x0, + .uc_descriptor_ram_size = 0x1000, + .uc_ofst = 0x1000, + .uc_size = 0x80, + .uc_info_ofst = 0x1080, + .uc_info_size = 0x200, + .ofst_start = 0x1280, + .v4_flt_hash_ofst = 0x1288, + .v4_flt_hash_size = 0x78, + .v4_flt_hash_size_ddr = 0x4000, + .v4_flt_nhash_ofst = 0x1308, + .v4_flt_nhash_size = 0x78, + .v4_flt_nhash_size_ddr = 0x4000, + .v6_flt_hash_ofst = 0x1388, + .v6_flt_hash_size = 0x78, + .v6_flt_hash_size_ddr = 0x4000, + .v6_flt_nhash_ofst = 0x1408, + .v6_flt_nhash_size = 0x78, + .v6_flt_nhash_size_ddr = 0x4000, + .v4_rt_num_index = 0x13, + .v4_modem_rt_index_lo = 0x0, + .v4_modem_rt_index_hi = 0xa, + .v4_apps_rt_index_lo = 0xb, + .v4_apps_rt_index_hi = 0x12, + .v4_rt_hash_ofst = 0x1488, + .v4_rt_hash_size = 0x98, + .v4_rt_hash_size_ddr = 0x4000, + .v4_rt_nhash_ofst = 0x1528, + .v4_rt_nhash_size = 0x98, + .v4_rt_nhash_size_ddr = 0x4000, + .v6_rt_num_index = 0x13, + .v6_modem_rt_index_lo = 0x0, + .v6_modem_rt_index_hi = 0xa, + .v6_apps_rt_index_lo = 0xb, + .v6_apps_rt_index_hi = 0x12, + .v6_rt_hash_ofst = 0x15c8, + .v6_rt_hash_size = 0x98, + .v6_rt_hash_size_ddr = 0x4000, + .v6_rt_nhash_ofst = 0x1668, + .v6_rt_nhash_size = 0x098, + .v6_rt_nhash_size_ddr = 0x4000, + .modem_hdr_ofst = 0x1708, + .modem_hdr_size = 0x240, + .apps_hdr_ofst = 0x1948, + .apps_hdr_size = 0x1e0, + .apps_hdr_size_ddr = 0x800, + .modem_hdr_proc_ctx_ofst = 0x1b40, + .modem_hdr_proc_ctx_size = 0xb20, + .apps_hdr_proc_ctx_ofst = 0x2660, + .apps_hdr_proc_ctx_size = 0x200, + .apps_hdr_proc_ctx_size_ddr = 0x0, + .stats_quota_q6_ofst = 0x2868, + .stats_quota_q6_size = 0x60, + .stats_quota_ap_ofst = 0x28C8, + .stats_quota_ap_size = 0x48, + .stats_tethering_ofst = 0x2910, + .stats_tethering_size = 0x3c0, + .stats_flt_v4_ofst = 0, + .stats_flt_v4_size = 0, + .stats_flt_v6_ofst = 0, + .stats_flt_v6_size = 0, + .stats_rt_v4_ofst = 0, + .stats_rt_v4_size = 0, + .stats_rt_v6_ofst = 0, + .stats_rt_v6_size = 0, + .stats_fnr_ofst = 0x2cd0, + .stats_fnr_size = 0xba0, + .stats_drop_ofst = 0x3870, + .stats_drop_size = 0x20, + .modem_comp_decomp_ofst = 0x0, + .modem_comp_decomp_size = 0x0, + .modem_ofst = 0x3898, + .modem_size = 0xd48, + .nat_tbl_ofst = 0x45e0, + .nat_tbl_size = 0x900, + .apps_v4_flt_hash_ofst = 0x2718, + .apps_v4_flt_hash_size = 0x0, + .apps_v4_flt_nhash_ofst = 0x2718, + .apps_v4_flt_nhash_size = 0x0, + .apps_v6_flt_hash_ofst = 0x2718, + .apps_v6_flt_hash_size = 0x0, + .apps_v6_flt_nhash_ofst = 0x2718, + .apps_v6_flt_nhash_size = 0x0, + .apps_v4_rt_hash_ofst = 0x2718, + .apps_v4_rt_hash_size = 0x0, + .apps_v4_rt_nhash_ofst = 0x2718, + .apps_v4_rt_nhash_size = 0x0, + .apps_v6_rt_hash_ofst = 0x2718, + .apps_v6_rt_hash_size = 0x0, + .apps_v6_rt_nhash_ofst = 0x2718, + .apps_v6_rt_nhash_size = 0x0, + .pdn_config_ofst = 0x4ee8, + .pdn_config_size = 0x100, + .end_ofst = 0x4fe8, +}; + +static struct ipa3_mem_partition ipa_5_2_mem_part = { + .uc_ofst = 0x0, + .uc_size = 0x80, + .uc_info_ofst = 0x80, + .uc_info_size = 0x200, + .ofst_start = 0x280, + .v4_flt_hash_ofst = 0x288, + .v4_flt_hash_size = 0x78, + .v4_flt_hash_size_ddr = 0x4000, + .v4_flt_nhash_ofst = 0x308, + .v4_flt_nhash_size = 0x78, + .v4_flt_nhash_size_ddr = 0x4000, + .v6_flt_hash_ofst = 0x388, + .v6_flt_hash_size = 0x78, + .v6_flt_hash_size_ddr = 0x4000, + .v6_flt_nhash_ofst = 0x408, + .v6_flt_nhash_size = 0x78, + .v6_flt_nhash_size_ddr = 0x4000, + .v4_rt_num_index = 0x13, + .v4_modem_rt_index_lo = 0x0, + .v4_modem_rt_index_hi = 0xa, + .v4_apps_rt_index_lo = 0xb, + .v4_apps_rt_index_hi = 0x12, + .v4_rt_hash_ofst = 0x488, + .v4_rt_hash_size = 0x98, + .v4_rt_hash_size_ddr = 0x4000, + .v4_rt_nhash_ofst = 0x528, + .v4_rt_nhash_size = 0x98, + .v4_rt_nhash_size_ddr = 0x4000, + .v6_rt_num_index = 0x13, + .v6_modem_rt_index_lo = 0x0, + .v6_modem_rt_index_hi = 0xa, + .v6_apps_rt_index_lo = 0xb, + .v6_apps_rt_index_hi = 0x12, + .v6_rt_hash_ofst = 0x5c8, + .v6_rt_hash_size = 0x98, + .v6_rt_hash_size_ddr = 0x4000, + .v6_rt_nhash_ofst = 0x668, + .v6_rt_nhash_size = 0x098, + .v6_rt_nhash_size_ddr = 0x4000, + .modem_hdr_ofst = 0x708, + .modem_hdr_size = 0x240, + .apps_hdr_ofst = 0x948, + .apps_hdr_size = 0x1e0, + .apps_hdr_size_ddr = 0x800, + .modem_hdr_proc_ctx_ofst = 0xb40, + .modem_hdr_proc_ctx_size = 0xb20, + .apps_hdr_proc_ctx_ofst = 0x1660, + .apps_hdr_proc_ctx_size = 0x200, + .apps_hdr_proc_ctx_size_ddr = 0x0, + .stats_quota_q6_ofst = 0x1868, + .stats_quota_q6_size = 0x60, + .stats_quota_ap_ofst = 0x18C8, + .stats_quota_ap_size = 0x48, + .stats_tethering_ofst = 0x1910, + .stats_tethering_size = 0x3c0, + .stats_flt_v4_ofst = 0, + .stats_flt_v4_size = 0, + .stats_flt_v6_ofst = 0, + .stats_flt_v6_size = 0, + .stats_rt_v4_ofst = 0, + .stats_rt_v4_size = 0, + .stats_rt_v6_ofst = 0, + .stats_rt_v6_size = 0, + .stats_fnr_ofst = 0x1cd0, + .stats_fnr_size = 0xba0, + .stats_drop_ofst = 0x2870, + .stats_drop_size = 0x20, + .modem_comp_decomp_ofst = 0x0, + .modem_comp_decomp_size = 0x0, + .modem_ofst = 0x2898, + .modem_size = 0xd48, + .nat_tbl_ofst = 0x35e0, + .nat_tbl_size = 0x900, + .apps_v4_flt_hash_ofst = 0x2718, + .apps_v4_flt_hash_size = 0x0, + .apps_v6_flt_hash_ofst = 0x2718, + .apps_v6_flt_hash_size = 0x0, + .apps_v4_flt_nhash_ofst = 0x2718, + .apps_v4_flt_nhash_size = 0x0, + .apps_v6_flt_nhash_ofst = 0x2718, + .apps_v6_flt_nhash_size = 0x0, + .apps_v4_rt_hash_ofst = 0x2718, + .apps_v4_rt_hash_size = 0x0, + .apps_v4_rt_nhash_ofst = 0x2718, + .apps_v4_rt_nhash_size = 0x0, + .apps_v6_rt_hash_ofst = 0x2718, + .apps_v6_rt_hash_size = 0x0, + .apps_v6_rt_nhash_ofst = 0x2718, + .apps_v6_rt_nhash_size = 0x0, + .pdn_config_ofst = 0x3ee8, + .pdn_config_size = 0x100, + .end_ofst = 0x3fe8, +}; + +static struct ipa3_mem_partition ipa_5_5_mem_part = { + .uc_descriptor_ram_ofst = 0x0, + .uc_descriptor_ram_size = 0x1000, + .uc_ofst = 0x1000, + .uc_size = 0x80, + .uc_info_ofst = 0x1080, + .uc_info_size = 0x200, + .ofst_start = 0x1280, + .v4_flt_hash_ofst = 0x1288, + .v4_flt_hash_size = 0x78, + .v4_flt_hash_size_ddr = 0x4000, + .v4_flt_nhash_ofst = 0x1308, + .v4_flt_nhash_size = 0x78, + .v4_flt_nhash_size_ddr = 0x4000, + .v6_flt_hash_ofst = 0x1388, + .v6_flt_hash_size = 0x78, + .v6_flt_hash_size_ddr = 0x4000, + .v6_flt_nhash_ofst = 0x1408, + .v6_flt_nhash_size = 0x78, + .v6_flt_nhash_size_ddr = 0x4000, + .v4_rt_num_index = 0x13, + .v4_modem_rt_index_lo = 0x0, + .v4_modem_rt_index_hi = 0xa, + .v4_apps_rt_index_lo = 0xb, + .v4_apps_rt_index_hi = 0x12, + .v4_rt_hash_ofst = 0x1488, + .v4_rt_hash_size = 0x98, + .v4_rt_hash_size_ddr = 0x4000, + .v4_rt_nhash_ofst = 0x1528, + .v4_rt_nhash_size = 0x98, + .v4_rt_nhash_size_ddr = 0x4000, + .v6_rt_num_index = 0x13, + .v6_modem_rt_index_lo = 0x0, + .v6_modem_rt_index_hi = 0xa, + .v6_apps_rt_index_lo = 0xb, + .v6_apps_rt_index_hi = 0x12, + .v6_rt_hash_ofst = 0x15c8, + .v6_rt_hash_size = 0x98, + .v6_rt_hash_size_ddr = 0x4000, + .v6_rt_nhash_ofst = 0x1668, + .v6_rt_nhash_size = 0x098, + .v6_rt_nhash_size_ddr = 0x4000, + .modem_hdr_ofst = 0x1708, + .modem_hdr_size = 0x240, + .apps_hdr_ofst = 0x1948, + .apps_hdr_size = 0x1e0, + .apps_hdr_size_ddr = 0x800, + .modem_hdr_proc_ctx_ofst = 0x1b40, + .modem_hdr_proc_ctx_size = 0xb20, + .apps_hdr_proc_ctx_ofst = 0x2660, + .apps_hdr_proc_ctx_size = 0x200, + .apps_hdr_proc_ctx_size_ddr = 0x0, + .stats_quota_q6_ofst = 0x2868, + .stats_quota_q6_size = 0x60, + .stats_quota_ap_ofst = 0x28C8, + .stats_quota_ap_size = 0x48, + .stats_tethering_ofst = 0x2910, + .stats_tethering_size = 0x3c0, + .stats_flt_v4_ofst = 0, + .stats_flt_v4_size = 0, + .stats_flt_v6_ofst = 0, + .stats_flt_v6_size = 0, + .stats_rt_v4_ofst = 0, + .stats_rt_v4_size = 0, + .stats_rt_v6_ofst = 0, + .stats_rt_v6_size = 0, + .stats_fnr_ofst = 0x2cd0, + .stats_fnr_size = 0xba0, + .stats_drop_ofst = 0x3870, + .stats_drop_size = 0x20, + .modem_comp_decomp_ofst = 0x0, + .modem_comp_decomp_size = 0x0, + .modem_ofst = 0x3898, + .modem_size = 0xd48, + .nat_tbl_ofst = 0x45e0, + .nat_tbl_size = 0x900, + .apps_v4_flt_hash_ofst = 0x2718, + .apps_v4_flt_hash_size = 0x0, + .apps_v4_flt_nhash_ofst = 0x2718, + .apps_v4_flt_nhash_size = 0x0, + .apps_v6_flt_hash_ofst = 0x2718, + .apps_v6_flt_hash_size = 0x0, + .apps_v6_flt_nhash_ofst = 0x2718, + .apps_v6_flt_nhash_size = 0x0, + .apps_v4_rt_hash_ofst = 0x2718, + .apps_v4_rt_hash_size = 0x0, + .apps_v4_rt_nhash_ofst = 0x2718, + .apps_v4_rt_nhash_size = 0x0, + .apps_v6_rt_hash_ofst = 0x2718, + .apps_v6_rt_hash_size = 0x0, + .apps_v6_rt_nhash_ofst = 0x2718, + .apps_v6_rt_nhash_size = 0x0, + .pdn_config_ofst = 0x4ee8, + .pdn_config_size = 0x100, + .end_ofst = 0x4fe8, +}; + +const char *ipa_clients_strings[IPA_CLIENT_MAX] = { + __stringify(IPA_CLIENT_HSIC1_PROD), + __stringify(IPA_CLIENT_HSIC1_CONS), + __stringify(IPA_CLIENT_HSIC2_PROD), + __stringify(IPA_CLIENT_HSIC2_CONS), + __stringify(IPA_CLIENT_HSIC3_PROD), + __stringify(IPA_CLIENT_HSIC3_CONS), + __stringify(IPA_CLIENT_HSIC4_PROD), + __stringify(IPA_CLIENT_HSIC4_CONS), + __stringify(IPA_CLIENT_HSIC5_PROD), + __stringify(IPA_CLIENT_HSIC5_CONS), + __stringify(IPA_CLIENT_WLAN1_PROD), + __stringify(IPA_CLIENT_WLAN1_CONS), + __stringify(IPA_CLIENT_WLAN2_PROD), + __stringify(IPA_CLIENT_WLAN2_CONS), + __stringify(IPA_CLIENT_WLAN3_PROD), + __stringify(IPA_CLIENT_WLAN3_CONS), + __stringify(RESERVED_PROD_16), + __stringify(IPA_CLIENT_WLAN4_CONS), + __stringify(IPA_CLIENT_USB_PROD), + __stringify(IPA_CLIENT_USB_CONS), + __stringify(IPA_CLIENT_USB2_PROD), + __stringify(IPA_CLIENT_USB2_CONS), + __stringify(IPA_CLIENT_USB3_PROD), + __stringify(IPA_CLIENT_USB3_CONS), + __stringify(IPA_CLIENT_USB4_PROD), + __stringify(IPA_CLIENT_USB4_CONS), + __stringify(IPA_CLIENT_UC_USB_PROD), + __stringify(IPA_CLIENT_USB_DPL_CONS), + __stringify(IPA_CLIENT_A2_EMBEDDED_PROD), + __stringify(IPA_CLIENT_A2_EMBEDDED_CONS), + __stringify(IPA_CLIENT_A2_TETHERED_PROD), + __stringify(IPA_CLIENT_A2_TETHERED_CONS), + __stringify(IPA_CLIENT_APPS_LAN_PROD), + __stringify(IPA_CLIENT_APPS_LAN_CONS), + __stringify(IPA_CLIENT_APPS_WAN_PROD), + __stringify(IPA_CLIENT_APPS_WAN_CONS), + __stringify(IPA_CLIENT_APPS_CMD_PROD), + __stringify(IPA_CLIENT_A5_LAN_WAN_CONS), + __stringify(IPA_CLIENT_ODU_PROD), + __stringify(IPA_CLIENT_ODU_EMB_CONS), + __stringify(RESERVED_PROD_40), + __stringify(IPA_CLIENT_ODU_TETH_CONS), + __stringify(IPA_CLIENT_MHI_PROD), + __stringify(IPA_CLIENT_MHI_CONS), + __stringify(IPA_CLIENT_MEMCPY_DMA_SYNC_PROD), + __stringify(IPA_CLIENT_MEMCPY_DMA_SYNC_CONS), + __stringify(IPA_CLIENT_MEMCPY_DMA_ASYNC_PROD), + __stringify(IPA_CLIENT_MEMCPY_DMA_ASYNC_CONS), + __stringify(IPA_CLIENT_ETHERNET_PROD), + __stringify(IPA_CLIENT_ETHERNET_CONS), + __stringify(IPA_CLIENT_Q6_LAN_PROD), + __stringify(IPA_CLIENT_Q6_LAN_CONS), + __stringify(IPA_CLIENT_Q6_WAN_PROD), + __stringify(IPA_CLIENT_Q6_WAN_CONS), + __stringify(IPA_CLIENT_Q6_CMD_PROD), + __stringify(IPA_CLIENT_Q6_DUN_CONS), + __stringify(IPA_CLIENT_Q6_DECOMP_PROD), + __stringify(IPA_CLIENT_Q6_DECOMP_CONS), + __stringify(IPA_CLIENT_Q6_DECOMP2_PROD), + __stringify(IPA_CLIENT_Q6_DECOMP2_CONS), + __stringify(RESERVED_PROD_60), + __stringify(IPA_CLIENT_Q6_LTE_WIFI_AGGR_CONS), + __stringify(IPA_CLIENT_TEST_PROD), + __stringify(IPA_CLIENT_TEST_CONS), + __stringify(IPA_CLIENT_TEST1_PROD), + __stringify(IPA_CLIENT_TEST1_CONS), + __stringify(IPA_CLIENT_TEST2_PROD), + __stringify(IPA_CLIENT_TEST2_CONS), + __stringify(IPA_CLIENT_TEST3_PROD), + __stringify(IPA_CLIENT_TEST3_CONS), + __stringify(IPA_CLIENT_TEST4_PROD), + __stringify(IPA_CLIENT_TEST4_CONS), + __stringify(RESERVED_PROD_72), + __stringify(IPA_CLIENT_DUMMY_CONS), + __stringify(IPA_CLIENT_Q6_DL_NLO_DATA_PROD), + __stringify(IPA_CLIENT_Q6_UL_NLO_DATA_CONS), + __stringify(RESERVED_PROD_76), + __stringify(IPA_CLIENT_Q6_UL_NLO_ACK_CONS), + __stringify(RESERVED_PROD_78), + __stringify(IPA_CLIENT_Q6_QBAP_STATUS_CONS), + __stringify(RESERVED_PROD_80), + __stringify(IPA_CLIENT_MHI_DPL_CONS), + __stringify(RESERVED_PROD_82), + __stringify(IPA_CLIENT_ODL_DPL_CONS), + __stringify(IPA_CLIENT_Q6_AUDIO_DMA_MHI_PROD), + __stringify(IPA_CLIENT_Q6_AUDIO_DMA_MHI_CONS), + __stringify(IPA_CLIENT_WIGIG_PROD), + __stringify(IPA_CLIENT_WIGIG1_CONS), + __stringify(RESERVERD_PROD_88), + __stringify(IPA_CLIENT_WIGIG2_CONS), + __stringify(RESERVERD_PROD_90), + __stringify(IPA_CLIENT_WIGIG3_CONS), + __stringify(RESERVERD_PROD_92), + __stringify(IPA_CLIENT_WIGIG4_CONS), + __stringify(RESERVERD_PROD_94), + __stringify(IPA_CLIENT_APPS_WAN_COAL_CONS), + __stringify(IPA_CLIENT_MHI_PRIME_TETH_PROD), + __stringify(IPA_CLIENT_MHI_PRIME_TETH_CONS), + __stringify(IPA_CLIENT_MHI_PRIME_RMNET_PROD), + __stringify(IPA_CLIENT_MHI_PRIME_RMNET_CONS), + __stringify(IPA_CLIENT_MHI_PRIME_DPL_PROD), + __stringify(RESERVERD_CONS_101), + __stringify(IPA_CLIENT_AQC_ETHERNET_PROD), + __stringify(IPA_CLIENT_AQC_ETHERNET_CONS), + __stringify(IPA_CLIENT_APPS_WAN_LOW_LAT_PROD), + __stringify(IPA_CLIENT_APPS_WAN_LOW_LAT_CONS), + __stringify(IPA_CLIENT_QDSS_PROD), + __stringify(IPA_CLIENT_MHI_QDSS_CONS), + __stringify(IPA_CLIENT_RTK_ETHERNET_PROD), + __stringify(IPA_CLIENT_RTK_ETHERNET_CONS), + __stringify(IPA_CLIENT_MHI_LOW_LAT_PROD), + __stringify(IPA_CLIENT_MHI_LOW_LAT_CONS), + __stringify(IPA_CLIENT_MHI2_PROD), + __stringify(IPA_CLIENT_MHI2_CONS), + __stringify(IPA_CLIENT_Q6_CV2X_PROD), + __stringify(IPA_CLIENT_Q6_CV2X_CONS), + __stringify(IPA_CLIENT_ETHERNET2_PROD), + __stringify(IPA_CLIENT_ETHERNET2_CONS), + __stringify(RESERVERD_PROD_118), + __stringify(IPA_CLIENT_WLAN2_CONS1), + __stringify(IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_PROD), + __stringify(IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_CONS), + __stringify(IPA_CLIENT_Q6_DL_NLO_LL_DATA_PROD), + __stringify(RESERVERD_CONS_123), + __stringify(RESERVERD_PROD_124), + __stringify(IPA_CLIENT_TPUT_CONS), + __stringify(RESERVERD_PROD_126), + __stringify(IPA_CLIENT_APPS_LAN_COAL_CONS), +}; +EXPORT_SYMBOL(ipa_clients_strings); + +static void _set_coalescing_disposition( + bool force_to_default ) +{ + if ( ipa3_ctx->ipa_initialization_complete + && + ipa3_ctx->ipa_hw_type >= IPA_HW_v5_5 ) { + + struct ipahal_reg_coal_master_cfg master_cfg; + + memset(&master_cfg, 0, sizeof(master_cfg)); + + ipahal_read_reg_fields(IPA_COAL_MASTER_CFG, &master_cfg); + + master_cfg.coal_force_to_default = force_to_default; + + ipahal_write_reg_fields(IPA_COAL_MASTER_CFG, &master_cfg); + } +} + +void start_coalescing(void) +{ + if ( ipa3_ctx->coal_stopped ) { + _set_coalescing_disposition(false); + ipa3_ctx->coal_stopped = false; + } +} + +void stop_coalescing(void) +{ + if ( ! ipa3_ctx->coal_stopped ) { + _set_coalescing_disposition(true); + ipa3_ctx->coal_stopped = true; + } +} + +bool lan_coal_enabled(void) +{ + if ( ipa3_ctx->ipa_initialization_complete && ipa3_ctx->lan_coal_enable) { + int ep_idx; + if ( IPA_CLIENT_IS_MAPPED_VALID(IPA_CLIENT_APPS_LAN_COAL_CONS, ep_idx) ) { + return true; + } + } + return false; +} + +int ipa3_set_evict_policy( + struct ipa_ioc_coal_evict_policy *evict_pol) +{ + if (!evict_pol) { + IPAERR_RL("Bad arg evict_pol(%p)\n", evict_pol); + return -1; + } + + if ( ipa3_ctx->ipa_hw_type >= IPA_HW_v4_5 ) + { + struct ipahal_reg_coal_evict_lru evict_lru_reg; + + memset(&evict_lru_reg, 0, sizeof(evict_lru_reg)); + + evict_lru_reg.coal_vp_lru_thrshld = + evict_pol->coal_vp_thrshld; + evict_lru_reg.coal_eviction_en = + evict_pol->coal_eviction_en; + evict_lru_reg.coal_vp_lru_gran_sel = + evict_pol->coal_vp_gran_sel; + evict_lru_reg.coal_vp_lru_udp_thrshld = + evict_pol->coal_vp_udp_thrshld; + evict_lru_reg.coal_vp_lru_tcp_thrshld = + evict_pol->coal_vp_tcp_thrshld; + evict_lru_reg.coal_vp_lru_udp_thrshld_en = + evict_pol->coal_vp_udp_thrshld_en; + evict_lru_reg.coal_vp_lru_tcp_thrshld_en = + evict_pol->coal_vp_tcp_thrshld_en; + evict_lru_reg.coal_vp_lru_tcp_num = + evict_pol->coal_vp_tcp_num; + + ipahal_write_reg_fields(IPA_COAL_EVICT_LRU, &evict_lru_reg); + } + + return 0; +} + +/** + * ipa_get_version_string() - Get string representation of IPA version + * @ver: IPA version + * + * Return: Constant string representation + */ +const char *ipa_get_version_string(enum ipa_hw_type ver) +{ + const char *str; + + switch (ver) { + case IPA_HW_v1_0: + str = "1.0"; + break; + case IPA_HW_v1_1: + str = "1.1"; + break; + case IPA_HW_v2_0: + str = "2.0"; + break; + case IPA_HW_v2_1: + str = "2.1"; + break; + case IPA_HW_v2_5: + str = "2.5/2.6"; + break; + case IPA_HW_v2_6L: + str = "2.6L"; + break; + case IPA_HW_v3_0: + str = "3.0"; + break; + case IPA_HW_v3_1: + str = "3.1"; + break; + case IPA_HW_v3_5: + str = "3.5"; + break; + case IPA_HW_v3_5_1: + str = "3.5.1"; + break; + case IPA_HW_v4_0: + str = "4.0"; + break; + case IPA_HW_v4_1: + str = "4.1"; + break; + case IPA_HW_v4_2: + str = "4.2"; + break; + case IPA_HW_v4_5: + str = "4.5"; + break; + case IPA_HW_v4_7: + str = "4.7"; + break; + case IPA_HW_v4_9: + str = "4.9"; + break; + case IPA_HW_v4_11: + str = "4.11"; + break; + case IPA_HW_v5_0: + str = "5.0"; + break; + case IPA_HW_v5_1: + str = "5.1"; + fallthrough; + case IPA_HW_v5_2: + str = "5.2"; + fallthrough; + case IPA_HW_v5_5: + str = "5.5"; + fallthrough; + default: + str = "Invalid version"; + break; + } + + return str; +} +EXPORT_SYMBOL(ipa_get_version_string); + +/** + * ipa3_get_clients_from_rm_resource() - get IPA clients which are related to an + * IPA_RM resource + * + * @resource: [IN] IPA Resource Manager resource + * @clients: [OUT] Empty array which will contain the list of clients. The + * caller must initialize this array. + * + * Return codes: 0 on success, negative on failure. + */ +int ipa3_get_clients_from_rm_resource( + enum ipa_rm_resource_name resource, + struct ipa3_client_names *clients) +{ + int i = 0; + + if (resource < 0 || + resource >= IPA_RM_RESOURCE_MAX || + !clients) { + IPAERR("Bad parameters\n"); + return -EINVAL; + } + + switch (resource) { + case IPA_RM_RESOURCE_USB_CONS: + if (ipa_get_ep_mapping(IPA_CLIENT_USB_CONS) != -1) + clients->names[i++] = IPA_CLIENT_USB_CONS; + break; + case IPA_RM_RESOURCE_USB_DPL_CONS: + if (ipa_get_ep_mapping(IPA_CLIENT_USB_DPL_CONS) != -1) + clients->names[i++] = IPA_CLIENT_USB_DPL_CONS; + break; + case IPA_RM_RESOURCE_HSIC_CONS: + clients->names[i++] = IPA_CLIENT_HSIC1_CONS; + break; + case IPA_RM_RESOURCE_WLAN_CONS: + clients->names[i++] = IPA_CLIENT_WLAN1_CONS; + clients->names[i++] = IPA_CLIENT_WLAN2_CONS; + clients->names[i++] = IPA_CLIENT_WLAN3_CONS; + clients->names[i++] = IPA_CLIENT_WLAN2_CONS1; + break; + case IPA_RM_RESOURCE_MHI_CONS: + clients->names[i++] = IPA_CLIENT_MHI_CONS; + break; + case IPA_RM_RESOURCE_ODU_ADAPT_CONS: + clients->names[i++] = IPA_CLIENT_ODU_EMB_CONS; + clients->names[i++] = IPA_CLIENT_ODU_TETH_CONS; + break; + case IPA_RM_RESOURCE_ETHERNET_CONS: + clients->names[i++] = IPA_CLIENT_ETHERNET_CONS; + break; + case IPA_RM_RESOURCE_USB_PROD: + if (ipa_get_ep_mapping(IPA_CLIENT_USB_PROD) != -1) + clients->names[i++] = IPA_CLIENT_USB_PROD; + break; + case IPA_RM_RESOURCE_HSIC_PROD: + clients->names[i++] = IPA_CLIENT_HSIC1_PROD; + break; + case IPA_RM_RESOURCE_MHI_PROD: + clients->names[i++] = IPA_CLIENT_MHI_PROD; + break; + case IPA_RM_RESOURCE_ODU_ADAPT_PROD: + clients->names[i++] = IPA_CLIENT_ODU_PROD; + break; + case IPA_RM_RESOURCE_ETHERNET_PROD: + clients->names[i++] = IPA_CLIENT_ETHERNET_PROD; + break; + default: + break; + } + clients->length = i; + + return 0; +} + +/** + * ipa3_should_pipe_be_suspended() - returns true when the client's pipe should + * be suspended during a power save scenario. False otherwise. + * + * @client: [IN] IPA client + */ +bool ipa3_should_pipe_be_suspended(enum ipa_client_type client) +{ + struct ipa3_ep_context *ep; + int ipa_ep_idx; + + ipa_ep_idx = ipa_get_ep_mapping(client); + if (ipa_ep_idx == -1) { + IPAERR("Invalid client.\n"); + WARN_ON(1); + return false; + } + + ep = &ipa3_ctx->ep[ipa_ep_idx]; + + /* + * starting IPA 4.0 pipe no longer can be suspended. Instead, + * the corresponding GSI channel should be stopped. Usually client + * driver will take care of stopping the channel. For client drivers + * that are not stopping the channel, IPA RM will do that based on + * ipa3_should_pipe_channel_be_stopped(). + */ + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_0) + return false; + + if (ep->keep_ipa_awake) + return false; + + if (client == IPA_CLIENT_USB_CONS || + client == IPA_CLIENT_USB2_CONS || + client == IPA_CLIENT_USB_DPL_CONS || + client == IPA_CLIENT_MHI_CONS || + client == IPA_CLIENT_MHI_DPL_CONS || + client == IPA_CLIENT_MHI_QDSS_CONS || + client == IPA_CLIENT_HSIC1_CONS || + client == IPA_CLIENT_WLAN1_CONS || + client == IPA_CLIENT_WLAN2_CONS || + client == IPA_CLIENT_WLAN3_CONS || + client == IPA_CLIENT_WLAN2_CONS1 || + client == IPA_CLIENT_WLAN4_CONS || + client == IPA_CLIENT_ODU_EMB_CONS || + client == IPA_CLIENT_ODU_TETH_CONS || + client == IPA_CLIENT_ETHERNET_CONS || + client == IPA_CLIENT_ETHERNET2_CONS) + return true; + + return false; +} + +/** + * ipa3_should_pipe_channel_be_stopped() - returns true when the client's + * channel should be stopped during a power save scenario. False otherwise. + * Most client already stops the GSI channel on suspend, and are not included + * in the list below. + * + * @client: [IN] IPA client + */ +static bool ipa3_should_pipe_channel_be_stopped(enum ipa_client_type client) +{ + struct ipa3_ep_context *ep; + int ipa_ep_idx; + + if (ipa3_ctx->ipa_hw_type < IPA_HW_v4_0) + return false; + + ipa_ep_idx = ipa_get_ep_mapping(client); + if (ipa_ep_idx == -1) { + IPAERR("Invalid client.\n"); + WARN_ON(1); + return false; + } + + ep = &ipa3_ctx->ep[ipa_ep_idx]; + + if (ep->keep_ipa_awake) + return false; + + if (client == IPA_CLIENT_ODU_EMB_CONS || + client == IPA_CLIENT_ODU_TETH_CONS) + return true; + + return false; +} + +/** + * ipa3_suspend_resource_sync() - suspend client endpoints related to the IPA_RM + * resource and decrement active clients counter, which may result in clock + * gating of IPA clocks. + * + * @resource: [IN] IPA Resource Manager resource + * + * Return codes: 0 on success, negative on failure. + */ +int ipa3_suspend_resource_sync(enum ipa_rm_resource_name resource) +{ + struct ipa3_client_names clients; + int res; + int index; + struct ipa_ep_cfg_ctrl suspend; + enum ipa_client_type client; + int ipa_ep_idx; + bool pipe_suspended = false; + + memset(&clients, 0, sizeof(clients)); + res = ipa3_get_clients_from_rm_resource(resource, &clients); + if (res) { + IPAERR("Bad params.\n"); + return res; + } + + for (index = 0; index < clients.length; index++) { + client = clients.names[index]; + ipa_ep_idx = ipa_get_ep_mapping(client); + if (ipa_ep_idx == -1) { + IPAERR("Invalid client.\n"); + res = -EINVAL; + continue; + } + ipa3_ctx->resume_on_connect[client] = false; + if (ipa3_ctx->ep[ipa_ep_idx].client == client && + ipa3_should_pipe_be_suspended(client)) { + if (ipa3_ctx->ep[ipa_ep_idx].valid) { + /* suspend endpoint */ + memset(&suspend, 0, sizeof(suspend)); + suspend.ipa_ep_suspend = true; + ipa_cfg_ep_ctrl(ipa_ep_idx, &suspend); + pipe_suspended = true; + } + } + + if (ipa3_ctx->ep[ipa_ep_idx].client == client && + ipa3_should_pipe_channel_be_stopped(client)) { + if (ipa3_ctx->ep[ipa_ep_idx].valid) { + /* Stop GSI channel */ + res = ipa_stop_gsi_channel(ipa_ep_idx); + if (res) { + IPAERR("failed stop gsi ch %lu\n", + ipa3_ctx->ep[ipa_ep_idx].gsi_chan_hdl); + return res; + } + } + } + } + /* Sleep ~1 msec */ + if (pipe_suspended) + usleep_range(1000, 2000); + + /* before gating IPA clocks do TAG process */ + ipa3_ctx->tag_process_before_gating = true; + IPA_ACTIVE_CLIENTS_DEC_RESOURCE(ipa_rm_resource_str(resource)); + + return 0; +} + +/** + * ipa3_suspend_resource_no_block() - suspend client endpoints related to the + * IPA_RM resource and decrement active clients counter. This function is + * guaranteed to avoid sleeping. + * + * @resource: [IN] IPA Resource Manager resource + * + * Return codes: 0 on success, negative on failure. + */ +int ipa3_suspend_resource_no_block(enum ipa_rm_resource_name resource) +{ + int res; + struct ipa3_client_names clients; + int index; + enum ipa_client_type client; + struct ipa_ep_cfg_ctrl suspend; + int ipa_ep_idx; + struct ipa_active_client_logging_info log_info; + + memset(&clients, 0, sizeof(clients)); + res = ipa3_get_clients_from_rm_resource(resource, &clients); + if (res) { + IPAERR( + "ipa3_get_clients_from_rm_resource() failed, name = %d.\n", + resource); + goto bail; + } + + for (index = 0; index < clients.length; index++) { + client = clients.names[index]; + ipa_ep_idx = ipa_get_ep_mapping(client); + if (ipa_ep_idx == -1) { + IPAERR("Invalid client.\n"); + res = -EINVAL; + continue; + } + ipa3_ctx->resume_on_connect[client] = false; + if (ipa3_ctx->ep[ipa_ep_idx].client == client && + ipa3_should_pipe_be_suspended(client)) { + if (ipa3_ctx->ep[ipa_ep_idx].valid) { + /* suspend endpoint */ + memset(&suspend, 0, sizeof(suspend)); + suspend.ipa_ep_suspend = true; + ipa_cfg_ep_ctrl(ipa_ep_idx, &suspend); + } + } + + if (ipa3_ctx->ep[ipa_ep_idx].client == client && + ipa3_should_pipe_channel_be_stopped(client)) { + res = -EPERM; + goto bail; + } + } + + if (res == 0) { + IPA_ACTIVE_CLIENTS_PREP_RESOURCE(log_info, + ipa_rm_resource_str(resource)); + /* before gating IPA clocks do TAG process */ + ipa3_ctx->tag_process_before_gating = true; + ipa3_dec_client_disable_clks_no_block(&log_info); + } +bail: + return res; +} + +/** + * ipa3_resume_resource() - resume client endpoints related to the IPA_RM + * resource. + * + * @resource: [IN] IPA Resource Manager resource + * + * Return codes: 0 on success, negative on failure. + */ +int ipa3_resume_resource(enum ipa_rm_resource_name resource) +{ + + struct ipa3_client_names clients; + int res; + int index; + struct ipa_ep_cfg_ctrl suspend; + enum ipa_client_type client; + int ipa_ep_idx; + + memset(&clients, 0, sizeof(clients)); + res = ipa3_get_clients_from_rm_resource(resource, &clients); + if (res) { + IPAERR("ipa3_get_clients_from_rm_resource() failed.\n"); + return res; + } + + for (index = 0; index < clients.length; index++) { + client = clients.names[index]; + ipa_ep_idx = ipa_get_ep_mapping(client); + if (ipa_ep_idx == -1) { + IPAERR("Invalid client.\n"); + res = -EINVAL; + continue; + } + /* + * The related ep, will be resumed on connect + * while its resource is granted + */ + ipa3_ctx->resume_on_connect[client] = true; + IPADBG("%d will be resumed on connect.\n", client); + if (ipa3_ctx->ep[ipa_ep_idx].client == client && + ipa3_should_pipe_be_suspended(client)) { + if (ipa3_ctx->ep[ipa_ep_idx].valid) { + memset(&suspend, 0, sizeof(suspend)); + suspend.ipa_ep_suspend = false; + ipa_cfg_ep_ctrl(ipa_ep_idx, &suspend); + } + } + + if (ipa3_ctx->ep[ipa_ep_idx].client == client && + ipa3_should_pipe_channel_be_stopped(client)) { + if (ipa3_ctx->ep[ipa_ep_idx].valid) { + res = gsi_start_channel( + ipa3_ctx->ep[ipa_ep_idx].gsi_chan_hdl); + if (res) { + IPAERR("failed to start gsi ch %lu\n", + ipa3_ctx->ep[ipa_ep_idx].gsi_chan_hdl); + return res; + } + } + } + } + + return res; +} + +/** + * ipa3_get_hw_type_index() - Get HW type index which is used as the entry index + * for ep\resource groups related arrays . + * + * Return value: HW type index + */ +u8 ipa3_get_hw_type_index(void) +{ + u8 hw_type_index; + + switch (ipa3_ctx->ipa_hw_type) { + case IPA_HW_v3_0: + case IPA_HW_v3_1: + hw_type_index = IPA_3_0; + break; + case IPA_HW_v3_5: + hw_type_index = IPA_3_5; + /* + *this flag is initialized only after fw load trigger from + * user space (ipa3_write) + */ + if (ipa3_ctx->ipa_config_is_mhi) + hw_type_index = IPA_3_5_MHI; + break; + case IPA_HW_v3_5_1: + hw_type_index = IPA_3_5_1; + break; + case IPA_HW_v4_0: + hw_type_index = IPA_4_0; + /* + *this flag is initialized only after fw load trigger from + * user space (ipa3_write) + */ + if (ipa3_ctx->ipa_config_is_mhi) + hw_type_index = IPA_4_0_MHI; + break; + case IPA_HW_v4_1: + hw_type_index = IPA_4_1; + break; + case IPA_HW_v4_2: + hw_type_index = IPA_4_2; + break; + case IPA_HW_v4_5: + hw_type_index = IPA_4_5; + if (ipa3_ctx->ipa_config_is_mhi) + hw_type_index = IPA_4_5_MHI; + if (ipa3_ctx->platform_type == IPA_PLAT_TYPE_APQ) + hw_type_index = IPA_4_5_APQ; + if (ipa3_ctx->ipa_config_is_auto) + hw_type_index = IPA_4_5_AUTO; + if (ipa3_ctx->ipa_config_is_auto && + ipa3_ctx->ipa_config_is_mhi) + hw_type_index = IPA_4_5_AUTO_MHI; + break; + case IPA_HW_v4_7: + hw_type_index = IPA_4_7; + break; + case IPA_HW_v4_9: + hw_type_index = IPA_4_9; + break; + case IPA_HW_v4_11: + hw_type_index = IPA_4_11; + break; + case IPA_HW_v5_0: + hw_type_index = IPA_5_0; + if (ipa3_ctx->ipa_config_is_mhi) + hw_type_index = IPA_5_0_MHI; + break; + case IPA_HW_v5_1: + hw_type_index = IPA_5_1; + if (ipa3_ctx->platform_type == IPA_PLAT_TYPE_APQ) + hw_type_index = IPA_5_1_APQ; + break; + case IPA_HW_v5_2: + hw_type_index = IPA_5_2; + break; + case IPA_HW_v5_5: + hw_type_index = IPA_5_5; + if (ipa3_ctx->platform_type == IPA_PLAT_TYPE_XR) + hw_type_index = IPA_5_5_XR; + break; + default: + IPAERR("Incorrect IPA version %d\n", ipa3_ctx->ipa_hw_type); + hw_type_index = IPA_3_0; + break; + } + + return hw_type_index; +} + +/** + * _ipa_sram_settings_read_v3_0() - Read SRAM settings from HW + * + * Returns: None + */ +void _ipa_sram_settings_read_v3_0(void) +{ + struct ipahal_reg_shared_mem_size smem_sz; + + memset(&smem_sz, 0, sizeof(smem_sz)); + + ipahal_read_reg_fields(IPA_SHARED_MEM_SIZE, &smem_sz); + + ipa3_ctx->smem_restricted_bytes = smem_sz.shared_mem_baddr; + ipa3_ctx->smem_sz = smem_sz.shared_mem_sz; + + /* reg fields are in 8B units */ + ipa3_ctx->smem_restricted_bytes *= 8; + ipa3_ctx->smem_sz *= 8; + ipa3_ctx->smem_reqd_sz = IPA_MEM_PART(end_ofst); + ipa3_ctx->hdr_proc_ctx_tbl_lcl = true; + + /* + * when proc ctx table is located in internal memory, + * modem entries resides first. + */ + if (ipa3_ctx->hdr_proc_ctx_tbl_lcl) { + ipa3_ctx->hdr_proc_ctx_tbl.start_offset = + IPA_MEM_PART(modem_hdr_proc_ctx_size); + } + + ipa3_ctx->rt_tbl_hash_lcl[IPA_IP_v4] = false; + ipa3_ctx->rt_tbl_nhash_lcl[IPA_IP_v4] = false; + ipa3_ctx->rt_tbl_hash_lcl[IPA_IP_v6] = false; + ipa3_ctx->rt_tbl_nhash_lcl[IPA_IP_v6] = false; + ipa3_ctx->flt_tbl_hash_lcl[IPA_IP_v4] = false; + ipa3_ctx->flt_tbl_hash_lcl[IPA_IP_v6] = false; + + if (ipa3_ctx->ipa_hw_type == IPA_HW_v5_0) { + ipa3_ctx->flt_tbl_nhash_lcl[IPA_IP_v4] = true; + ipa3_ctx->flt_tbl_nhash_lcl[IPA_IP_v6] = true; + } else { + ipa3_ctx->flt_tbl_nhash_lcl[IPA_IP_v4] = false; + ipa3_ctx->flt_tbl_nhash_lcl[IPA_IP_v6] = false; + } +} + +/** + * ipa3_cfg_route() - configure IPA route + * @route: IPA route + * + * Return codes: + * 0: success + */ +int ipa3_cfg_route(struct ipahal_reg_route *route) +{ + + IPADBG("disable_route_block=%d, default_pipe=%d, default_hdr_tbl=%d\n", + route->route_dis, + route->route_def_pipe, + route->route_def_hdr_table); + IPADBG("default_hdr_ofst=%d, default_frag_pipe=%d\n", + route->route_def_hdr_ofst, + route->route_frag_def_pipe); + + IPADBG("default_retain_hdr=%d\n", + route->route_def_retain_hdr); + + if (route->route_dis) { + IPAERR("Route disable is not supported!\n"); + return -EPERM; + } + + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + + ipahal_write_reg_fields(IPA_ROUTE, route); + + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + + return 0; +} + +/** + * ipa3_cfg_filter() - configure filter + * @disable: disable value + * + * Return codes: + * 0: success + */ +int ipa3_cfg_filter(u32 disable) +{ + IPAERR_RL("Filter disable is not supported!\n"); + return -EPERM; +} + +/** + * ipa_disable_hashing_rt_flt_v4_2() - Disable filer and route hashing. + * + * Return codes: 0 for success, negative value for failure + */ +static int ipa_disable_hashing_rt_flt_v4_2(void) +{ + /* + * note this register deprecated starting IPAv5 if need to disable + * use alternative + */ + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0) { + IPAERR("reg deprecated\n"); + WARN_ON(1); + return -EPERM; + } + IPADBG("Disable hashing for filter and route table in IPA 4.2 HW\n"); + ipahal_write_reg(IPA_FILT_ROUT_HASH_EN, + IPA_FILT_ROUT_HASH_REG_VAL_v4_2); + return 0; +} + + +/** + * ipa_comp_cfg() - Configure QMB/Master port selection + * + * Returns: None + */ +static void ipa_comp_cfg(void) +{ + struct ipahal_reg_comp_cfg comp_cfg; + + /* IPAv4 specific, on NON-MHI config*/ + if ((ipa3_ctx->ipa_hw_type == IPA_HW_v4_0) && + (!ipa3_ctx->ipa_config_is_mhi)) { + + ipahal_read_reg_fields(IPA_COMP_CFG, &comp_cfg); + IPADBG("Before comp config\n"); + IPADBG("ipa_qmb_select_by_address_global_en = %d\n", + comp_cfg.ipa_qmb_select_by_address_global_en); + + IPADBG("ipa_qmb_select_by_address_prod_en = %d\n", + comp_cfg.ipa_qmb_select_by_address_prod_en); + + IPADBG("ipa_qmb_select_by_address_cons_en = %d\n", + comp_cfg.ipa_qmb_select_by_address_cons_en); + + comp_cfg.ipa_qmb_select_by_address_global_en = false; + comp_cfg.ipa_qmb_select_by_address_prod_en = false; + comp_cfg.ipa_qmb_select_by_address_cons_en = false; + + ipahal_write_reg_fields(IPA_COMP_CFG, &comp_cfg); + + ipahal_read_reg_fields(IPA_COMP_CFG, &comp_cfg); + IPADBG("After comp config\n"); + IPADBG("ipa_qmb_select_by_address_global_en = %d\n", + comp_cfg.ipa_qmb_select_by_address_global_en); + + IPADBG("ipa_qmb_select_by_address_prod_en = %d\n", + comp_cfg.ipa_qmb_select_by_address_prod_en); + + IPADBG("ipa_qmb_select_by_address_cons_en = %d\n", + comp_cfg.ipa_qmb_select_by_address_cons_en); + } + + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_0) { + ipahal_read_reg_fields(IPA_COMP_CFG, &comp_cfg); + IPADBG("Before comp config\n"); + IPADBG("gsi_multi_inorder_rd_dis = %d\n", + comp_cfg.gsi_multi_inorder_rd_dis); + + IPADBG("gsi_multi_inorder_wr_dis = %d\n", + comp_cfg.gsi_multi_inorder_wr_dis); + + comp_cfg.gsi_multi_inorder_rd_dis = true; + comp_cfg.gsi_multi_inorder_wr_dis = true; + + ipahal_write_reg_fields(IPA_COMP_CFG, &comp_cfg); + + ipahal_read_reg_fields(IPA_COMP_CFG, &comp_cfg); + IPADBG("After comp config\n"); + IPADBG("gsi_multi_inorder_rd_dis = %d\n", + comp_cfg.gsi_multi_inorder_rd_dis); + + IPADBG("gsi_multi_inorder_wr_dis = %d\n", + comp_cfg.gsi_multi_inorder_wr_dis); + } + + /* set GSI_MULTI_AXI_MASTERS_DIS = true after HW.4.1 */ + if ((ipa3_ctx->ipa_hw_type == IPA_HW_v4_1) || + (ipa3_ctx->ipa_hw_type == IPA_HW_v4_2)) { + ipahal_read_reg_fields(IPA_COMP_CFG, &comp_cfg); + IPADBG("Before comp config\n"); + IPADBG("gsi_multi_axi_masters_dis = %d\n", + comp_cfg.gsi_multi_axi_masters_dis); + + comp_cfg.gsi_multi_axi_masters_dis = true; + + ipahal_write_reg_fields(IPA_COMP_CFG, &comp_cfg); + + ipahal_read_reg_fields(IPA_COMP_CFG, &comp_cfg); + IPADBG("After comp config\n"); + IPADBG("gsi_multi_axi_masters_dis = %d\n", + comp_cfg.gsi_multi_axi_masters_dis); + } +} + +/** + * ipa3_cfg_qsb() - Configure IPA QSB maximal reads and writes + * + * Returns: None + */ +static void ipa3_cfg_qsb(void) +{ + u8 hw_type_idx; + const struct ipa_qmb_outstanding *qmb_ot; + struct ipahal_reg_qsb_max_reads max_reads = { 0 }; + struct ipahal_reg_qsb_max_writes max_writes = { 0 }; + + hw_type_idx = ipa3_ctx->hw_type_index; + + /* + * Read the register values before writing to them to ensure + * other values are not overwritten + */ + ipahal_read_reg_fields(IPA_QSB_MAX_WRITES, &max_writes); + ipahal_read_reg_fields(IPA_QSB_MAX_READS, &max_reads); + + qmb_ot = &(ipa3_qmb_outstanding[hw_type_idx][IPA_QMB_INSTANCE_DDR]); + max_reads.qmb_0_max_reads = qmb_ot->ot_reads; + max_writes.qmb_0_max_writes = qmb_ot->ot_writes; + max_reads.qmb_0_max_read_beats = qmb_ot->ot_read_beats; + + qmb_ot = &(ipa3_qmb_outstanding[hw_type_idx][IPA_QMB_INSTANCE_PCIE]); + max_reads.qmb_1_max_reads = qmb_ot->ot_reads; + max_writes.qmb_1_max_writes = qmb_ot->ot_writes; + + ipahal_write_reg_fields(IPA_QSB_MAX_WRITES, &max_writes); + ipahal_write_reg_fields(IPA_QSB_MAX_READS, &max_reads); +} + +/* relevant starting IPA4.5 */ +static void ipa_cfg_qtime(void) +{ + struct ipahal_reg_qtime_timestamp_cfg ts_cfg; + struct ipahal_reg_timers_pulse_gran_cfg gran_cfg; + struct ipahal_reg_timers_xo_clk_div_cfg div_cfg; + u32 val; + + /* Configure timestamp resolution */ + memset(&ts_cfg, 0, sizeof(ts_cfg)); + ts_cfg.dpl_timestamp_lsb = IPA_TAG_TIMER_TIMESTAMP_SHFT; + ts_cfg.dpl_timestamp_sel = true; + ts_cfg.tag_timestamp_lsb = IPA_TAG_TIMER_TIMESTAMP_SHFT; + ts_cfg.nat_timestamp_lsb = IPA_NAT_TIMER_TIMESTAMP_SHFT; + val = ipahal_read_reg(IPA_QTIME_TIMESTAMP_CFG); + IPADBG("qtime timestamp before cfg: 0x%x\n", val); + ipahal_write_reg_fields(IPA_QTIME_TIMESTAMP_CFG, &ts_cfg); + val = ipahal_read_reg(IPA_QTIME_TIMESTAMP_CFG); + IPADBG("qtime timestamp after cfg: 0x%x\n", val); + + /* Configure timers pulse generators granularity */ + memset(&gran_cfg, 0, sizeof(gran_cfg)); + if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0) + { + gran_cfg.gran_0 = IPA_TIMERS_TIME_GRAN_100_USEC; + gran_cfg.gran_1 = IPA_TIMERS_TIME_GRAN_1_MSEC; + gran_cfg.gran_2 = IPA_TIMERS_TIME_GRAN_1_MSEC; + gran_cfg.gran_3 = IPA_TIMERS_TIME_GRAN_1_MSEC; + } + else + { + gran_cfg.gran_0 = IPA_TIMERS_TIME_GRAN_100_USEC; + gran_cfg.gran_1 = IPA_TIMERS_TIME_GRAN_1_MSEC; + gran_cfg.gran_2 = IPA_TIMERS_TIME_GRAN_10_MSEC; + gran_cfg.gran_3 = IPA_TIMERS_TIME_GRAN_10_MSEC; + } + val = ipahal_read_reg(IPA_TIMERS_PULSE_GRAN_CFG); + IPADBG("timer pulse granularity before cfg: 0x%x\n", val); + ipahal_write_reg_fields(IPA_TIMERS_PULSE_GRAN_CFG, &gran_cfg); + val = ipahal_read_reg(IPA_TIMERS_PULSE_GRAN_CFG); + IPADBG("timer pulse granularity after cfg: 0x%x\n", val); + + /* Configure timers XO Clock divider */ + memset(&div_cfg, 0, sizeof(div_cfg)); + ipahal_read_reg_fields(IPA_TIMERS_XO_CLK_DIV_CFG, &div_cfg); + IPADBG("timer XO clk divider before cfg: enabled=%d divider=%u\n", + div_cfg.enable, div_cfg.value); + + /* Make sure divider is disabled */ + if (div_cfg.enable) { + div_cfg.enable = false; + ipahal_write_reg_fields(IPA_TIMERS_XO_CLK_DIV_CFG, &div_cfg); + } + + /* At emulation systems XO clock is lower than on real target. + * (e.g. 19.2Mhz compared to 96Khz) + * Use lowest possible divider. + */ + if (ipa3_ctx->ipa3_hw_mode == IPA_HW_MODE_VIRTUAL || + ipa3_ctx->ipa3_hw_mode == IPA_HW_MODE_EMULATION) { + div_cfg.value = 0; + } + + div_cfg.enable = true; /* Enable the divider */ + ipahal_write_reg_fields(IPA_TIMERS_XO_CLK_DIV_CFG, &div_cfg); + ipahal_read_reg_fields(IPA_TIMERS_XO_CLK_DIV_CFG, &div_cfg); + IPADBG("timer XO clk divider after cfg: enabled=%d divider=%u\n", + div_cfg.enable, div_cfg.value); +} + +/** + * ipa3_init_hw() - initialize HW + * + * Return codes: + * 0: success + */ +int ipa3_init_hw(void) +{ + u32 ipa_version = 0; + struct ipahal_reg_counter_cfg cnt_cfg; + struct ipahal_reg_coal_master_cfg master_cfg; + + /* Read IPA version and make sure we have access to the registers */ + ipa_version = ipahal_read_reg(IPA_VERSION); + IPADBG("IPA_VERSION=%u\n", ipa_version); + if (ipa_version == 0) + return -EFAULT; + + switch (ipa3_ctx->ipa_hw_type) { + case IPA_HW_v3_0: + case IPA_HW_v3_1: + ipahal_write_reg(IPA_BCR, IPA_BCR_REG_VAL_v3_0); + break; + case IPA_HW_v3_5: + case IPA_HW_v3_5_1: + ipahal_write_reg(IPA_BCR, IPA_BCR_REG_VAL_v3_5); + break; + case IPA_HW_v4_0: + case IPA_HW_v4_1: + ipahal_write_reg(IPA_BCR, IPA_BCR_REG_VAL_v4_0); + break; + case IPA_HW_v4_2: + ipahal_write_reg(IPA_BCR, IPA_BCR_REG_VAL_v4_2); + break; + default: + IPADBG("Do not update BCR - hw_type=%d\n", + ipa3_ctx->ipa_hw_type); + break; + } + + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_0 && + ipa3_ctx->ipa_hw_type < IPA_HW_v4_5) { + struct ipahal_reg_clkon_cfg clkon_cfg; + struct ipahal_reg_tx_cfg tx_cfg; + + memset(&clkon_cfg, 0, sizeof(clkon_cfg)); + + /*enable open global clocks*/ + clkon_cfg.open_global_2x_clk = true; + clkon_cfg.open_global = true; + ipahal_write_reg_fields(IPA_CLKON_CFG, &clkon_cfg); + + ipahal_read_reg_fields(IPA_TX_CFG, &tx_cfg); + /* disable PA_MASK_EN to allow holb drop */ + tx_cfg.pa_mask_en = 0; + ipahal_write_reg_fields(IPA_TX_CFG, &tx_cfg); + } + + ipa3_cfg_qsb(); + + /* IPA version <3.5 IPA_COUNTER_CFG register config not required */ + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v3_5) { + if (ipa3_ctx->ipa_hw_type < IPA_HW_v4_5) { + /* set aggr granularity for 0.5 msec*/ + cnt_cfg.aggr_granularity = GRAN_VALUE_500_USEC; + ipahal_write_reg_fields(IPA_COUNTER_CFG, &cnt_cfg); + } else { + ipa_cfg_qtime(); + } + } + + if (ipa3_is_ulso_supported()) { + ipahal_write_reg_n(IPA_ULSO_CFG_IP_ID_MIN_VALUE_n, 0, + ipa3_ctx->ulso_ip_id_min); + ipahal_write_reg_n(IPA_ULSO_CFG_IP_ID_MAX_VALUE_n, 0, + ipa3_ctx->ulso_ip_id_max); + } + + /* Configure COAL_MASTER_CFG */ + if(ipa3_ctx->ipa_hw_type >= IPA_HW_v5_5) { + memset(&master_cfg, 0, sizeof(master_cfg)); + ipahal_read_reg_fields(IPA_COAL_MASTER_CFG, &master_cfg); + master_cfg.coal_ipv4_id_ignore = ipa3_ctx->coal_ipv4_id_ignore; + ipahal_write_reg_fields(IPA_COAL_MASTER_CFG, &master_cfg); + + IPADBG( + ": coal-ipv4-id-ignore = %s\n", + master_cfg.coal_ipv4_id_ignore ? + "True" : "False"); + } + + ipa_comp_cfg(); + + /* + * In IPA 4.2 filter and routing hashing not supported + * disabling hash enable register. + */ + if (ipa3_ctx->ipa_fltrt_not_hashable) + ipa_disable_hashing_rt_flt_v4_2(); + + return 0; +} + +/** + * ipa_get_ep_mapping() - provide endpoint mapping + * @client: client type + * + * Return value: endpoint mapping + */ +int ipa_get_ep_mapping(enum ipa_client_type client) +{ + int ipa_ep_idx; + u8 hw_idx; + + hw_idx = ipa3_ctx->hw_type_index; + + if (client >= IPA_CLIENT_MAX || client < 0) { + IPAERR_RL("Bad client number! client =%d\n", client); + return IPA_EP_NOT_ALLOCATED; + } + + if (!ipa3_ep_mapping[hw_idx][client].valid) + return IPA_EP_NOT_ALLOCATED; + + ipa_ep_idx = + ipa3_ep_mapping[hw_idx][client].ipa_gsi_ep_info.ipa_ep_num; + if (ipa_ep_idx < 0 || (ipa_ep_idx >= ipa3_get_max_num_pipes() + && client != IPA_CLIENT_DUMMY_CONS)) + return IPA_EP_NOT_ALLOCATED; + + return ipa_ep_idx; +} +EXPORT_SYMBOL(ipa_get_ep_mapping); + +/** + * ipa_get_ep_mapping_from_gsi() - provide endpoint mapping + * @ch_id: GSI Virt CH id + * + * Return value: endpoint mapping + */ +int ipa_get_ep_mapping_from_gsi(int ch_id) +{ + int ipa_ep_idx = IPA_EP_NOT_ALLOCATED; + u8 hw_idx; + int i = 0; + + hw_idx = ipa3_ctx->hw_type_index; + + if (ch_id >= GSI_CHAN_MAX || ch_id < 0) { + IPAERR_RL("Bad ch_id number! ch_id =%d\n", ch_id); + return IPA_EP_NOT_ALLOCATED; + } + + for (i = 0; i < IPA_CLIENT_MAX; i++) { + if (ipa3_ep_mapping[hw_idx][i].valid && + ipa3_ep_mapping[hw_idx][i].ipa_gsi_ep_info.ipa_gsi_chan_num + == ch_id) { + ipa_ep_idx = ipa3_ep_mapping[hw_idx][i].ipa_gsi_ep_info.ipa_ep_num; + break; + } + } + + return ipa_ep_idx; +} + +/** + * ipa_get_gsi_ep_info() - provide gsi ep information + * @client: IPA client value + * + * Return value: pointer to ipa_gsi_ep_info + */ +const struct ipa_gsi_ep_config *ipa_get_gsi_ep_info + (enum ipa_client_type client) +{ + int ep_idx; + u8 hw_idx; + + hw_idx = ipa3_ctx->hw_type_index; + + ep_idx = ipa_get_ep_mapping(client); + if (ep_idx == IPA_EP_NOT_ALLOCATED) + return NULL; + + if (!ipa3_ep_mapping[hw_idx][client].valid) + return NULL; + + return &(ipa3_ep_mapping[hw_idx] + [client].ipa_gsi_ep_info); +} +EXPORT_SYMBOL(ipa_get_gsi_ep_info); + +/** + * ipa_get_ep_group() - provide endpoint group by client + * @client: client type + * + * Return value: endpoint group + */ +int ipa_get_ep_group(enum ipa_client_type client) +{ + u8 hw_idx; + + hw_idx = ipa3_ctx->hw_type_index; + + if (client >= IPA_CLIENT_MAX || client < 0) { + IPAERR("Bad client number! client =%d\n", client); + return -EINVAL; + } + + if (!ipa3_ep_mapping[hw_idx][client].valid) + return -EINVAL; + + return ipa3_ep_mapping[hw_idx][client].group_num; +} + +/** + * ipa3_get_qmb_master_sel() - provide QMB master selection for the client + * @client: client type + * + * Return value: QMB master index + */ +u8 ipa3_get_qmb_master_sel(enum ipa_client_type client) +{ + u8 hw_idx; + + hw_idx = ipa3_ctx->hw_type_index; + + if (client >= IPA_CLIENT_MAX || client < 0) { + IPAERR("Bad client number! client =%d\n", client); + return -EINVAL; + } + + if (!ipa3_ep_mapping[hw_idx][client].valid) + return -EINVAL; + + return ipa3_ep_mapping[hw_idx] + [client].qmb_master_sel; +} + +/** + * ipa3_get_tx_instance() - provide TX instance selection for the client + * @client: client type + * + * Return value: TX instance + */ +u8 ipa3_get_tx_instance(enum ipa_client_type client) +{ + u8 hw_idx; + + hw_idx = ipa3_ctx->hw_type_index; + + IPADBG("ipa_get_ep_group: hw_idx = %d\n", hw_idx); + + if (client >= IPA_CLIENT_MAX || client < 0) { + IPAERR("Bad client number! client =%d\n", client); + return -EINVAL; + } + + if (!ipa3_ep_mapping[hw_idx][client].valid) + return -EINVAL; + + return ipa3_ep_mapping[hw_idx] + [client].tx_instance; +} + +/** + * ipa3_set_client() - provide client mapping + * @client: client type + * + * Return value: none + */ + +void ipa3_set_client(int index, enum ipacm_client_enum client, bool uplink) +{ + if (client > IPACM_CLIENT_MAX || client < IPACM_CLIENT_USB) { + IPAERR("Bad client number! client =%d\n", client); + } else if (index >= ipa3_get_max_num_pipes() || index < 0) { + IPAERR("Bad pipe index! index =%d\n", index); + } else { + ipa3_ctx->ipacm_client[index].client_enum = client; + ipa3_ctx->ipacm_client[index].uplink = uplink; + } +} +/** + * ipa3_get_wlan_stats() - get ipa wifi stats + * + * Return value: success or failure + */ +int ipa3_get_wlan_stats(struct ipa_get_wdi_sap_stats *wdi_sap_stats) +{ + if (ipa3_ctx->uc_wdi_ctx.stats_notify) { + ipa3_ctx->uc_wdi_ctx.stats_notify(IPA_GET_WDI_SAP_STATS, + wdi_sap_stats); + } else { + IPAERR_RL("uc_wdi_ctx.stats_notify NULL\n"); + return -EFAULT; + } + return 0; +} + +/** + * ipa3_set_wlan_quota() - set ipa wifi quota + * @wdi_quota: quota requirement + * + * Return value: success or failure + */ +int ipa3_set_wlan_quota(struct ipa_set_wifi_quota *wdi_quota) +{ + if (ipa3_ctx->uc_wdi_ctx.stats_notify) { + ipa3_ctx->uc_wdi_ctx.stats_notify(IPA_SET_WIFI_QUOTA, + wdi_quota); + } else { + IPAERR("uc_wdi_ctx.stats_notify NULL\n"); + return -EFAULT; + } + return 0; +} + +/** + * ipa3_inform_wlan_bw() - inform wlan bw-index + * + * Return value: success or failure + */ +int ipa3_inform_wlan_bw(struct ipa_inform_wlan_bw *wdi_bw) +{ + if (ipa3_ctx->uc_wdi_ctx.stats_notify) { + ipa3_ctx->uc_wdi_ctx.stats_notify(IPA_INFORM_WLAN_BW, + wdi_bw); + } else { + IPAERR("uc_wdi_ctx.stats_notify NULL\n"); + return -EFAULT; + } + return 0; +} + +/** + * ipa3_get_client() - provide client mapping + * @client: client type + * + * Return value: client mapping enum + */ +enum ipacm_client_enum ipa3_get_client(int pipe_idx) +{ + if (pipe_idx >= ipa3_get_max_num_pipes() || pipe_idx < 0) { + IPAERR("Bad pipe index! pipe_idx =%d\n", pipe_idx); + return IPACM_CLIENT_MAX; + } else { + return ipa3_ctx->ipacm_client[pipe_idx].client_enum; + } +} +EXPORT_SYMBOL(ipa3_get_client); + +/** + * ipa2_get_client_uplink() - provide client mapping + * @client: client type + * + * Return value: none + */ +bool ipa3_get_client_uplink(int pipe_idx) +{ + if (pipe_idx < 0 || pipe_idx >= ipa3_get_max_num_pipes()) { + IPAERR("invalid pipe idx %d\n", pipe_idx); + return false; + } + + return ipa3_ctx->ipacm_client[pipe_idx].uplink; +} + + +/** + * ipa3_get_client_mapping() - provide client mapping + * @pipe_idx: IPA end-point number + * + * Return value: client mapping + */ +enum ipa_client_type ipa3_get_client_mapping(int pipe_idx) +{ + if (pipe_idx >= ipa3_ctx->ipa_num_pipes || pipe_idx < 0) { + IPAERR("Bad pipe index!\n"); + WARN_ON(1); + return -EINVAL; + } + + return ipa3_ctx->ep[pipe_idx].client; +} +EXPORT_SYMBOL(ipa3_get_client_mapping); + +/** + * ipa3_get_client_by_pipe() - return client type relative to pipe + * index + * @pipe_idx: IPA end-point number + * + * Return value: client type + */ +enum ipa_client_type ipa3_get_client_by_pipe(int pipe_idx) +{ + int j = 0; + u8 hw_type_idx; + + hw_type_idx = ipa3_ctx->hw_type_index; + + for (j = 0; j < IPA_CLIENT_MAX; j++) { + const struct ipa_ep_configuration *iec_ptr = + &(ipa3_ep_mapping[hw_type_idx][j]); + if (iec_ptr->valid && + iec_ptr->ipa_gsi_ep_info.ipa_ep_num == pipe_idx) + break; + } + + return j; +} + +/** + * ipa_init_ep_flt_bitmap() - Initialize the bitmap + * that represents the End-points that supports filtering + */ +void ipa_init_ep_flt_bitmap(void) +{ + enum ipa_client_type cl; + u8 hw_idx; + u64 bitmap; + u32 pipe_num; + const struct ipa_gsi_ep_config *gsi_ep_ptr; + + hw_idx = ipa3_ctx->hw_type_index; + bitmap = 0; + if (ipa3_ctx->ep_flt_bitmap) { + WARN_ON(1); + return; + } + + for (cl = 0; cl < IPA_CLIENT_MAX ; cl++) { + /* In normal mode don't add filter support test pipes*/ + if (ipa3_ep_mapping[hw_idx][cl].support_flt && + (!IPA_CLIENT_IS_TEST(cl) || + ipa3_ctx->ipa3_hw_mode == IPA_HW_MODE_VIRTUAL || + ipa3_ctx->ipa3_hw_mode == IPA_HW_MODE_EMULATION || + ipa3_ctx->ipa3_hw_mode == IPA_HW_MODE_TEST)) { + gsi_ep_ptr = + &ipa3_ep_mapping[hw_idx][cl].ipa_gsi_ep_info; + pipe_num = gsi_ep_ptr->ipa_ep_num; + bitmap |= (1ULL << pipe_num); + if (bitmap != ipa3_ctx->ep_flt_bitmap) { + ipa3_ctx->ep_flt_bitmap = bitmap; + ipa3_ctx->ep_flt_num++; + } + } + } +} + +/** + * ipa_is_ep_support_flt() - Given an End-point check + * whether it supports filtering or not. + * + * @pipe_idx: + * + * Return values: + * true if supports and false if not + */ +bool ipa_is_ep_support_flt(int pipe_idx) +{ + if (pipe_idx >= ipa3_ctx->ipa_num_pipes || pipe_idx < 0) { + IPAERR("Bad pipe index!\n"); + return false; + } + + return ipa3_ctx->ep_flt_bitmap & (1ULL<= ipa3_ctx->ipa_num_pipes || + ipa3_ctx->ep[clnt_hdl].valid == 0) { + IPAERR("bad param, clnt_hdl = %d", clnt_hdl); + return -EINVAL; + } + + if (IPA_CLIENT_IS_CONS(ipa3_ctx->ep[clnt_hdl].client)) { + IPAERR("SEQ does not apply to IPA consumer EP %d\n", clnt_hdl); + return -EINVAL; + } + + /* + * Skip Configure sequencers type for test clients. + * These are configured dynamically in ipa3_cfg_ep_mode + */ + if (IPA_CLIENT_IS_TEST(ipa3_ctx->ep[clnt_hdl].client)) { + IPADBG("Skip sequencers configuration for test clients\n"); + return 0; + } + + if (seq_cfg->set_dynamic) + type = seq_cfg->seq_type; + else + type = ipa3_ep_mapping[ipa3_ctx->hw_type_index] + [ipa3_ctx->ep[clnt_hdl].client].sequencer_type; + + if (type != IPA_DPS_HPS_SEQ_TYPE_INVALID) { + if (ipa3_ctx->ep[clnt_hdl].cfg.mode.mode == IPA_DMA && + !IPA_DPS_HPS_SEQ_TYPE_IS_DMA(type)) { + IPAERR("Configuring non-DMA SEQ type to DMA pipe\n"); + WARN_ON(1); + return -EINVAL; + } + IPA_ACTIVE_CLIENTS_INC_EP(ipa3_get_client_mapping(clnt_hdl)); + /* Configure sequencers type*/ + + IPADBG("set sequencers to sequence 0x%x, ep = %d\n", type, + clnt_hdl); + ipahal_write_reg_n(IPA_ENDP_INIT_SEQ_n, clnt_hdl, type); + + IPA_ACTIVE_CLIENTS_DEC_EP(ipa3_get_client_mapping(clnt_hdl)); + } else { + IPADBG("should not set sequencer type of ep = %d\n", clnt_hdl); + } + + return 0; +} + +/** + * ipa3_cfg_ep - IPA end-point configuration + * @clnt_hdl: [in] opaque client handle assigned by IPA to client + * @ipa_ep_cfg: [in] IPA end-point configuration params + * + * This includes nat, IPv6CT, header, mode, aggregation and route settings and + * is a one shot API to configure the IPA end-point fully + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_cfg_ep(u32 clnt_hdl, const struct ipa_ep_cfg *ipa_ep_cfg) +{ + int result = -EINVAL; + + if (clnt_hdl >= ipa3_ctx->ipa_num_pipes || + ipa3_ctx->ep[clnt_hdl].valid == 0 || ipa_ep_cfg == NULL) { + IPAERR("bad parm.\n"); + return -EINVAL; + } + + result = ipa3_cfg_ep_hdr(clnt_hdl, &ipa_ep_cfg->hdr); + if (result) + return result; + + result = ipa3_cfg_ep_hdr_ext(clnt_hdl, &ipa_ep_cfg->hdr_ext); + if (result) + return result; + + result = ipa3_cfg_ep_aggr(clnt_hdl, &ipa_ep_cfg->aggr); + if (result) + return result; + + result = ipa3_cfg_ep_cfg(clnt_hdl, &ipa_ep_cfg->cfg); + if (result) + return result; + + if (ipa3_is_ulso_supported()) { + result = ipa3_cfg_ep_ulso(clnt_hdl, + &ipa_ep_cfg->ulso); + if (result) + return result; + } + + if (IPA_CLIENT_IS_PROD(ipa3_ctx->ep[clnt_hdl].client)) { + result = ipa3_cfg_ep_nat(clnt_hdl, &ipa_ep_cfg->nat); + if (result) + return result; + + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_0) { + result = ipa3_cfg_ep_conn_track(clnt_hdl, + &ipa_ep_cfg->conn_track); + if (result) + return result; + } + + result = ipa3_cfg_ep_mode(clnt_hdl, &ipa_ep_cfg->mode); + if (result) + return result; + + result = ipa3_cfg_ep_seq(clnt_hdl, &ipa_ep_cfg->seq); + if (result) + return result; + + result = ipa3_cfg_ep_route(clnt_hdl, &ipa_ep_cfg->route); + if (result) + return result; + + result = ipa3_cfg_ep_deaggr(clnt_hdl, &ipa_ep_cfg->deaggr); + if (result) + return result; + } else { + result = ipa3_cfg_ep_metadata_mask(clnt_hdl, + &ipa_ep_cfg->metadata_mask); + if (result) + return result; + + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_5) { + result = ipa3_cfg_ep_prod_cfg(clnt_hdl, &ipa_ep_cfg->prod_cfg); + if (result) + return result; + } + } + + return 0; +} +EXPORT_SYMBOL(ipa3_cfg_ep); + +static const char *ipa3_get_nat_en_str(enum ipa_nat_en_type nat_en) +{ + switch (nat_en) { + case (IPA_BYPASS_NAT): + return "NAT disabled"; + case (IPA_SRC_NAT): + return "Source NAT"; + case (IPA_DST_NAT): + return "Dst NAT"; + } + + return "undefined"; +} + +static const char *ipa3_get_ipv6ct_en_str(enum ipa_ipv6ct_en_type ipv6ct_en) +{ + switch (ipv6ct_en) { + case (IPA_BYPASS_IPV6CT): + return "ipv6ct disabled"; + case (IPA_ENABLE_IPV6CT): + return "ipv6ct enabled"; + } + + return "undefined"; +} + +/** + * ipa3_cfg_ep_nat() - IPA end-point NAT configuration + * @clnt_hdl: [in] opaque client handle assigned by IPA to client + * @ep_nat: [in] IPA NAT end-point configuration params + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_cfg_ep_nat(u32 clnt_hdl, const struct ipa_ep_cfg_nat *ep_nat) +{ + if (clnt_hdl >= ipa3_ctx->ipa_num_pipes || + ipa3_ctx->ep[clnt_hdl].valid == 0 || ep_nat == NULL) { + IPAERR("bad parm, clnt_hdl = %d , ep_valid = %d\n", + clnt_hdl, + ipa3_ctx->ep[clnt_hdl].valid); + return -EINVAL; + } + + if (IPA_CLIENT_IS_CONS(ipa3_ctx->ep[clnt_hdl].client)) { + IPAERR("NAT does not apply to IPA out EP %d\n", clnt_hdl); + return -EINVAL; + } + + IPADBG("pipe=%d, nat_en=%d(%s), nat_exc_suppress=%d\n", + clnt_hdl, + ep_nat->nat_en, + ipa3_get_nat_en_str(ep_nat->nat_en), + ep_nat->nat_exc_suppress); + + /* copy over EP cfg */ + ipa3_ctx->ep[clnt_hdl].cfg.nat = *ep_nat; + + IPA_ACTIVE_CLIENTS_INC_EP(ipa3_get_client_mapping(clnt_hdl)); + + ipahal_write_reg_n_fields(IPA_ENDP_INIT_NAT_n, clnt_hdl, ep_nat); + + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_5) { + ipahal_write_reg_n_fields(IPA_ENDP_INIT_NAT_EXC_SUPPRESS_n, + clnt_hdl, ep_nat); + } + + IPA_ACTIVE_CLIENTS_DEC_EP(ipa3_get_client_mapping(clnt_hdl)); + + return 0; +} + +/** + * ipa3_cfg_ep_conn_track() - IPA end-point IPv6CT configuration + * @clnt_hdl: [in] opaque client handle assigned by IPA to client + * @ep_conn_track: [in] IPA IPv6CT end-point configuration params + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_cfg_ep_conn_track(u32 clnt_hdl, + const struct ipa_ep_cfg_conn_track *ep_conn_track) +{ + if (clnt_hdl >= ipa3_ctx->ipa_num_pipes || + ipa3_ctx->ep[clnt_hdl].valid == 0 || ep_conn_track == NULL) { + IPAERR("bad parm, clnt_hdl = %d , ep_valid = %d\n", + clnt_hdl, + ipa3_ctx->ep[clnt_hdl].valid); + return -EINVAL; + } + + if (IPA_CLIENT_IS_CONS(ipa3_ctx->ep[clnt_hdl].client)) { + IPAERR("IPv6CT does not apply to IPA out EP %d\n", clnt_hdl); + return -EINVAL; + } + + IPADBG("pipe=%d, conn_track_en=%d(%s)\n", + clnt_hdl, + ep_conn_track->conn_track_en, + ipa3_get_ipv6ct_en_str(ep_conn_track->conn_track_en)); + + /* copy over EP cfg */ + ipa3_ctx->ep[clnt_hdl].cfg.conn_track = *ep_conn_track; + + IPA_ACTIVE_CLIENTS_INC_EP(ipa3_get_client_mapping(clnt_hdl)); + + ipahal_write_reg_n_fields(IPA_ENDP_INIT_CONN_TRACK_n, clnt_hdl, + ep_conn_track); + + IPA_ACTIVE_CLIENTS_DEC_EP(ipa3_get_client_mapping(clnt_hdl)); + + return 0; +} + + +/** + * ipa3_cfg_ep_status() - IPA end-point status configuration + * @clnt_hdl: [in] opaque client handle assigned by IPA to client + * @ipa_ep_cfg: [in] IPA end-point configuration params + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_cfg_ep_status(u32 clnt_hdl, + const struct ipahal_reg_ep_cfg_status *ep_status) +{ + if (clnt_hdl >= ipa3_ctx->ipa_num_pipes || + ipa3_ctx->ep[clnt_hdl].valid == 0 || ep_status == NULL) { + IPAERR("bad parm, clnt_hdl = %d , ep_valid = %d\n", + clnt_hdl, + ipa3_ctx->ep[clnt_hdl].valid); + return -EINVAL; + } + + IPADBG("pipe=%d, status_en=%d status_ep=%d status_location=%d\n", + clnt_hdl, + ep_status->status_en, + ep_status->status_ep, + ep_status->status_location); + + /* copy over EP cfg */ + ipa3_ctx->ep[clnt_hdl].status = *ep_status; + + IPA_ACTIVE_CLIENTS_INC_EP(ipa3_get_client_mapping(clnt_hdl)); + + ipahal_write_reg_n_fields(IPA_ENDP_STATUS_n, clnt_hdl, ep_status); + + IPA_ACTIVE_CLIENTS_DEC_EP(ipa3_get_client_mapping(clnt_hdl)); + + return 0; +} + +/** + * ipa3_cfg_ep_cfg_pipe_replicate() - IPA end-point cfg + * pipe replication + * @clnt_hdl: [in] opaque client handle assigned by IPA to client + * + * Return value: none + */ +void ipa3_cfg_ep_cfg_pipe_replicate(u32 clnt_hdl) +{ + /* Enable ADPL v6 Feature for certain IPA clients */ + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_5) { + switch (ipa3_get_client_mapping(clnt_hdl)) { + case IPA_CLIENT_USB_PROD: + case IPA_CLIENT_APPS_WAN_PROD: + case IPA_CLIENT_WLAN2_PROD: + case IPA_CLIENT_WIGIG_PROD: + case IPA_CLIENT_APPS_LAN_PROD: + case IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_PROD: + case IPA_CLIENT_APPS_LAN_COAL_CONS: + case IPA_CLIENT_APPS_LAN_CONS: + case IPA_CLIENT_APPS_WAN_COAL_CONS: + case IPA_CLIENT_APPS_WAN_CONS: + case IPA_CLIENT_WIGIG1_CONS: + case IPA_CLIENT_WLAN2_CONS: + case IPA_CLIENT_WLAN2_CONS1: + case IPA_CLIENT_USB_CONS: + case IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_CONS: + case IPA_CLIENT_WIGIG2_CONS: + case IPA_CLIENT_WIGIG3_CONS: + case IPA_CLIENT_WLAN3_PROD: + case IPA_CLIENT_ETHERNET2_PROD: + case IPA_CLIENT_USB2_PROD: + case IPA_CLIENT_ETHERNET_PROD: + case IPA_CLIENT_ETHERNET_CONS: + case IPA_CLIENT_ETHERNET2_CONS: + case IPA_CLIENT_USB2_CONS: + case IPA_CLIENT_WLAN4_CONS: + ipa3_ctx->ep[clnt_hdl].cfg.cfg.pipe_replicate_en = 1; + break; + default: + ipa3_ctx->ep[clnt_hdl].cfg.cfg.pipe_replicate_en = 0; + } + } +} + +/** + * ipa3_cfg_ep_cfg() - IPA end-point cfg configuration + * @clnt_hdl: [in] opaque client handle assigned by IPA to client + * @ipa_ep_cfg: [in] IPA end-point configuration params + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_cfg_ep_cfg(u32 clnt_hdl, const struct ipa_ep_cfg_cfg *cfg) +{ + u8 qmb_master_sel; + u8 tx_instance; + + if (clnt_hdl >= ipa3_ctx->ipa_num_pipes || + ipa3_ctx->ep[clnt_hdl].valid == 0 || cfg == NULL) { + IPAERR("bad parm, clnt_hdl = %d , ep_valid = %d\n", + clnt_hdl, + ipa3_ctx->ep[clnt_hdl].valid); + return -EINVAL; + } + + /* copy over EP cfg */ + ipa3_ctx->ep[clnt_hdl].cfg.cfg = *cfg; + + ipa3_cfg_ep_cfg_pipe_replicate(clnt_hdl); + + /* Override QMB master selection */ + qmb_master_sel = ipa3_get_qmb_master_sel(ipa3_ctx->ep[clnt_hdl].client); + ipa3_ctx->ep[clnt_hdl].cfg.cfg.gen_qmb_master_sel = qmb_master_sel; + IPADBG( + "pipe=%d, frag_ofld_en=%d cs_ofld_en=%d mdata_hdr_ofst=%d " + "gen_qmb_master_sel=%d pipe_replicate_en=%d\n", + clnt_hdl, + ipa3_ctx->ep[clnt_hdl].cfg.cfg.frag_offload_en, + ipa3_ctx->ep[clnt_hdl].cfg.cfg.cs_offload_en, + ipa3_ctx->ep[clnt_hdl].cfg.cfg.cs_metadata_hdr_offset, + ipa3_ctx->ep[clnt_hdl].cfg.cfg.gen_qmb_master_sel, + ipa3_ctx->ep[clnt_hdl].cfg.cfg.pipe_replicate_en); + + IPA_ACTIVE_CLIENTS_INC_EP(ipa3_get_client_mapping(clnt_hdl)); + + ipahal_write_reg_n_fields(IPA_ENDP_INIT_CFG_n, clnt_hdl, + &ipa3_ctx->ep[clnt_hdl].cfg.cfg); + + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0 && + IPA_CLIENT_IS_CONS(ipa3_ctx->ep[clnt_hdl].client)) { + tx_instance = ipa3_get_tx_instance(ipa3_ctx->ep[clnt_hdl].client); + if (tx_instance == -EINVAL) { + IPAERR("bad parm, clnt_hdl = %d , ep_valid = %d\n", + clnt_hdl, + ipa3_ctx->ep[clnt_hdl].valid); + return -EINVAL; + } + ipa3_ctx->ep[clnt_hdl].cfg.cfg.tx_instance = tx_instance; + ipahal_write_reg_n(IPA_ENDP_INIT_PROD_CFG_n, clnt_hdl, + ipa3_ctx->ep[clnt_hdl].cfg.cfg.tx_instance); + } + + IPA_ACTIVE_CLIENTS_DEC_EP(ipa3_get_client_mapping(clnt_hdl)); + + return 0; +} + +/** + * ipa3_cfg_ep_prod_cfg() - IPA Producer end-point configuration + * @clnt_hdl: [in] opaque client handle assigned by IPA to client + * @prod_cfg: [in] Producer specific configuration + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_cfg_ep_prod_cfg(u32 clnt_hdl, const struct ipa_ep_cfg_prod_cfg *prod_cfg) +{ + u8 tx_instance; + + if (clnt_hdl >= ipa3_ctx->ipa_num_pipes || + ipa3_ctx->ep[clnt_hdl].valid == 0 || + IPA_CLIENT_IS_PROD(ipa3_ctx->ep[clnt_hdl].client) || + prod_cfg == NULL) { + IPAERR("bad parm, clnt_hdl = %d , ep_valid = %d\n", + clnt_hdl, + ipa3_ctx->ep[clnt_hdl].valid); + return -EINVAL; + } + + /* copy over EP cfg */ + ipa3_ctx->ep[clnt_hdl].cfg.prod_cfg = *prod_cfg; + + tx_instance = ipa3_get_tx_instance(ipa3_ctx->ep[clnt_hdl].client); + if (tx_instance == -EINVAL) { + IPAERR("bad parm, clnt_hdl = %d , ep_valid = %d\n", + clnt_hdl, + ipa3_ctx->ep[clnt_hdl].valid); + return -EINVAL; + } + ipa3_ctx->ep[clnt_hdl].cfg.cfg.tx_instance = tx_instance; + ipa3_ctx->ep[clnt_hdl].cfg.prod_cfg.tx_instance = tx_instance; + + IPA_ACTIVE_CLIENTS_INC_EP(ipa3_get_client_mapping(clnt_hdl)); + + ipahal_write_reg_n_fields(IPA_ENDP_INIT_PROD_CFG_n, clnt_hdl, + &ipa3_ctx->ep[clnt_hdl].cfg.prod_cfg); + + IPA_ACTIVE_CLIENTS_DEC_EP(ipa3_get_client_mapping(clnt_hdl)); + + return 0; +} + + +/** + * ipa3_cfg_ep_metadata_mask() - IPA end-point meta-data mask configuration + * @clnt_hdl: [in] opaque client handle assigned by IPA to client + * @ipa_ep_cfg: [in] IPA end-point configuration params + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_cfg_ep_metadata_mask(u32 clnt_hdl, + const struct ipa_ep_cfg_metadata_mask + *metadata_mask) +{ + if (clnt_hdl >= ipa3_ctx->ipa_num_pipes || + ipa3_ctx->ep[clnt_hdl].valid == 0 || metadata_mask == NULL) { + IPAERR("bad parm, clnt_hdl = %d , ep_valid = %d\n", + clnt_hdl, + ipa3_ctx->ep[clnt_hdl].valid); + return -EINVAL; + } + + IPADBG("pipe=%d, metadata_mask=0x%x\n", + clnt_hdl, + metadata_mask->metadata_mask); + + /* copy over EP cfg */ + ipa3_ctx->ep[clnt_hdl].cfg.metadata_mask = *metadata_mask; + + IPA_ACTIVE_CLIENTS_INC_EP(ipa3_get_client_mapping(clnt_hdl)); + + ipahal_write_reg_n_fields(IPA_ENDP_INIT_HDR_METADATA_MASK_n, + clnt_hdl, metadata_mask); + + IPA_ACTIVE_CLIENTS_DEC_EP(ipa3_get_client_mapping(clnt_hdl)); + + return 0; +} + +/** + * ipa3_cfg_ep_hdr() - IPA end-point header configuration + * @clnt_hdl: [in] opaque client handle assigned by IPA to client + * @ipa_ep_cfg: [in] IPA end-point configuration params + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_cfg_ep_hdr(u32 clnt_hdl, const struct ipa_ep_cfg_hdr *ep_hdr) +{ + struct ipa3_ep_context *ep; + + if (clnt_hdl >= ipa3_ctx->ipa_num_pipes || + ipa3_ctx->ep[clnt_hdl].valid == 0 || ep_hdr == NULL) { + IPAERR("bad parm, clnt_hdl = %d , ep_valid = %d\n", + clnt_hdl, ipa3_ctx->ep[clnt_hdl].valid); + return -EINVAL; + } + IPADBG("pipe=%d metadata_reg_valid=%d\n", + clnt_hdl, + ep_hdr->hdr_metadata_reg_valid); + + IPADBG("remove_additional=%d, a5_mux=%d, ofst_pkt_size=0x%x\n", + ep_hdr->hdr_remove_additional, + ep_hdr->hdr_a5_mux, + ep_hdr->hdr_ofst_pkt_size); + + IPADBG("ofst_pkt_size_valid=%d, additional_const_len=0x%x\n", + ep_hdr->hdr_ofst_pkt_size_valid, + ep_hdr->hdr_additional_const_len); + + IPADBG("ofst_metadata=0x%x, ofst_metadata_valid=%d, len=0x%x\n", + ep_hdr->hdr_ofst_metadata, + ep_hdr->hdr_ofst_metadata_valid, + ep_hdr->hdr_len); + + ep = &ipa3_ctx->ep[clnt_hdl]; + + /* copy over EP cfg */ + ep->cfg.hdr = *ep_hdr; + + IPA_ACTIVE_CLIENTS_INC_EP(ipa3_get_client_mapping(clnt_hdl)); + + ipahal_write_reg_n_fields(IPA_ENDP_INIT_HDR_n, clnt_hdl, &ep->cfg.hdr); + + IPA_ACTIVE_CLIENTS_DEC_EP(ipa3_get_client_mapping(clnt_hdl)); + + return 0; +} + +/** + * ipa3_cfg_ep_hdr_ext() - IPA end-point extended header configuration + * @clnt_hdl: [in] opaque client handle assigned by IPA to client + * @ep_hdr_ext: [in] IPA end-point configuration params + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_cfg_ep_hdr_ext(u32 clnt_hdl, + const struct ipa_ep_cfg_hdr_ext *ep_hdr_ext) +{ + struct ipa3_ep_context *ep; + + if (clnt_hdl >= ipa3_ctx->ipa_num_pipes || + ipa3_ctx->ep[clnt_hdl].valid == 0 || ep_hdr_ext == NULL) { + IPAERR("bad parm, clnt_hdl = %d , ep_valid = %d\n", + clnt_hdl, ipa3_ctx->ep[clnt_hdl].valid); + return -EINVAL; + } + + IPADBG("pipe=%d hdr_pad_to_alignment=%d\n", + clnt_hdl, + ep_hdr_ext->hdr_pad_to_alignment); + + IPADBG("hdr_total_len_or_pad_offset=%d\n", + ep_hdr_ext->hdr_total_len_or_pad_offset); + + IPADBG("hdr_payload_len_inc_padding=%d hdr_total_len_or_pad=%d\n", + ep_hdr_ext->hdr_payload_len_inc_padding, + ep_hdr_ext->hdr_total_len_or_pad); + + IPADBG("hdr_total_len_or_pad_valid=%d hdr_little_endian=%d\n", + ep_hdr_ext->hdr_total_len_or_pad_valid, + ep_hdr_ext->hdr_little_endian); + + ep = &ipa3_ctx->ep[clnt_hdl]; + + /* copy over EP cfg */ + ep->cfg.hdr_ext = *ep_hdr_ext; + ep->cfg.hdr_ext.hdr = &ep->cfg.hdr; + + IPA_ACTIVE_CLIENTS_INC_EP(ipa3_get_client_mapping(clnt_hdl)); + + ipahal_write_reg_n_fields(IPA_ENDP_INIT_HDR_EXT_n, clnt_hdl, + &ep->cfg.hdr_ext); + + IPA_ACTIVE_CLIENTS_DEC_EP(ipa3_get_client_mapping(clnt_hdl)); + + return 0; +} + +/** + * ipa3_cfg_ep_ulso() - IPA end-point ulso configuration + * @clnt_hdl: [in] opaque client handle assigned by IPA to client + * @ep_ulso: [in] IPA end-point ulso configuration params + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_cfg_ep_ulso(u32 clnt_hdl, const struct ipa_ep_cfg_ulso *ep_ulso) +{ + struct ipa3_ep_context *ep; + + if (clnt_hdl >= ipa3_ctx->ipa_num_pipes || + ipa3_ctx->ep[clnt_hdl].valid == 0 || ep_ulso == NULL) { + IPAERR("bad parm, clnt_hdl = %d , ep_valid = %d\n", + clnt_hdl, ipa3_ctx->ep[clnt_hdl].valid); + return -EINVAL; + } + + IPADBG("pipe=%d ipid_min_max_idx=%d is_ulso_pipe=%d\n", + clnt_hdl, ep_ulso->ipid_min_max_idx, ep_ulso->is_ulso_pipe); + + ep = &ipa3_ctx->ep[clnt_hdl]; + + /* copy over EP cfg */ + ep->cfg.ulso = *ep_ulso; + + IPA_ACTIVE_CLIENTS_INC_EP(ipa3_get_client_mapping(clnt_hdl)); + + ipahal_write_reg_n(IPA_ENDP_INIT_ULSO_CFG_n, clnt_hdl, + ep->cfg.ulso.ipid_min_max_idx); + + IPA_ACTIVE_CLIENTS_DEC_EP(ipa3_get_client_mapping(clnt_hdl)); + + return 0; +} + +/** + * ipa_cfg_ep_ctrl() - IPA end-point Control configuration + * @clnt_hdl: [in] opaque client handle assigned by IPA to client + * @ipa_ep_cfg_ctrl: [in] IPA end-point configuration params + * + * Returns: 0 on success, negative on failure + */ +int ipa_cfg_ep_ctrl(u32 clnt_hdl, const struct ipa_ep_cfg_ctrl *ep_ctrl) +{ + int code = 0, result; + struct ipa3_ep_context *ep; + bool primary_secondry; + + if (clnt_hdl >= ipa3_ctx->ipa_num_pipes || ep_ctrl == NULL) { + IPAERR("bad parm, clnt_hdl = %d\n", clnt_hdl); + return -EINVAL; + } + + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_0 && ep_ctrl->ipa_ep_suspend) { + IPAERR("pipe suspend is not supported\n"); + WARN_ON(1); + return -EPERM; + } + + if (ipa3_ctx->ipa_endp_delay_wa) { + IPAERR("pipe setting delay is not supported\n"); + return 0; + } + + IPADBG("pipe=%d ep_suspend=%d, ep_delay=%d\n", + clnt_hdl, + ep_ctrl->ipa_ep_suspend, + ep_ctrl->ipa_ep_delay); + ep = &ipa3_ctx->ep[clnt_hdl]; + + if (ipa3_ctx->ipa_endp_delay_wa_v2 && + IPA_CLIENT_IS_PROD(ep->client)) { + + IPADBG("Configuring flow control for pipe = %d\n", clnt_hdl); + /* Configure enhanced flow control instead of delay + * Q6 controlled AP pipes(USB PROD and MHI_PROD) configuring the + * secondary flow control. + * AP controlled pipe configuring primary flow control. + */ + if (ep->client == IPA_CLIENT_USB_PROD || + ep->client == IPA_CLIENT_MHI_PROD || + ep->client == IPA_CLIENT_MHI_LOW_LAT_PROD) + primary_secondry = true; + else + primary_secondry = false; + + result = gsi_flow_control_ee(ep->gsi_chan_hdl, clnt_hdl, 0, + ep_ctrl->ipa_ep_delay, primary_secondry, &code); + if (result == GSI_STATUS_SUCCESS) { + IPADBG("flow control sussess gsi ch %d with code %d\n", + ep->gsi_chan_hdl, code); + } else { + IPADBG("failed to flow control gsi ch %d code %d\n", + ep->gsi_chan_hdl, code); + } + return 0; + } + + ipahal_write_reg_n_fields(IPA_ENDP_INIT_CTRL_n, clnt_hdl, ep_ctrl); + + if (ep_ctrl->ipa_ep_suspend == true && + IPA_CLIENT_IS_CONS(ipa3_ctx->ep[clnt_hdl].client)) + ipa3_suspend_active_aggr_wa(clnt_hdl); + + return 0; +} +EXPORT_SYMBOL(ipa_cfg_ep_ctrl); + +const char *ipa3_get_mode_type_str(enum ipa_mode_type mode) +{ + switch (mode) { + case (IPA_BASIC): + return "Basic"; + case (IPA_ENABLE_FRAMING_HDLC): + return "HDLC framing"; + case (IPA_ENABLE_DEFRAMING_HDLC): + return "HDLC de-framing"; + case (IPA_DMA): + return "DMA"; + } + + return "undefined"; +} + +/** + * ipa3_cfg_ep_mode() - IPA end-point mode configuration + * @clnt_hdl: [in] opaque client handle assigned by IPA to client + * @ipa_ep_cfg: [in] IPA end-point configuration params + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_cfg_ep_mode(u32 clnt_hdl, const struct ipa_ep_cfg_mode *ep_mode) +{ + int ep; + int type; + struct ipahal_reg_endp_init_mode init_mode; + + if (clnt_hdl >= ipa3_ctx->ipa_num_pipes || + ipa3_ctx->ep[clnt_hdl].valid == 0 || ep_mode == NULL) { + IPAERR("bad params clnt_hdl=%d , ep_valid=%d ep_mode=%pK\n", + clnt_hdl, ipa3_ctx->ep[clnt_hdl].valid, + ep_mode); + return -EINVAL; + } + + if (IPA_CLIENT_IS_CONS(ipa3_ctx->ep[clnt_hdl].client)) { + IPAERR("MODE does not apply to IPA out EP %d\n", clnt_hdl); + return -EINVAL; + } + + ep = ipa_get_ep_mapping(ep_mode->dst); + if (ep == -1 && ep_mode->mode == IPA_DMA) { + IPAERR("dst %d does not exist in DMA mode\n", ep_mode->dst); + return -EINVAL; + } + + WARN_ON(ep_mode->mode == IPA_DMA && IPA_CLIENT_IS_PROD(ep_mode->dst)); + + if (!IPA_CLIENT_IS_CONS(ep_mode->dst)) + ep = ipa_get_ep_mapping(IPA_CLIENT_APPS_LAN_CONS); + + IPADBG("pipe=%d mode=%d(%s), dst_client_number=%d\n", + clnt_hdl, + ep_mode->mode, + ipa3_get_mode_type_str(ep_mode->mode), + ep_mode->dst); + + /* copy over EP cfg */ + ipa3_ctx->ep[clnt_hdl].cfg.mode = *ep_mode; + ipa3_ctx->ep[clnt_hdl].dst_pipe_index = ep; + + IPA_ACTIVE_CLIENTS_INC_EP(ipa3_get_client_mapping(clnt_hdl)); + + init_mode.dst_pipe_number = ipa3_ctx->ep[clnt_hdl].dst_pipe_index; + init_mode.ep_mode = *ep_mode; + ipahal_write_reg_n_fields(IPA_ENDP_INIT_MODE_n, clnt_hdl, &init_mode); + + /* Configure sequencers type for test clients*/ + if (IPA_CLIENT_IS_TEST(ipa3_ctx->ep[clnt_hdl].client)) { + if (ep_mode->mode == IPA_DMA) + type = IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY; + else + /* In IPA4.2 only single pass only supported*/ + if (ipa3_ctx->ipa_hw_type == IPA_HW_v4_2) + type = + IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_NO_UCP; + else + type = + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP; + + IPADBG(" set sequencers to sequance 0x%x, ep = %d\n", type, + clnt_hdl); + ipahal_write_reg_n(IPA_ENDP_INIT_SEQ_n, clnt_hdl, type); + } + IPA_ACTIVE_CLIENTS_DEC_EP(ipa3_get_client_mapping(clnt_hdl)); + + return 0; +} + +const char *ipa3_get_aggr_enable_str(enum ipa_aggr_en_type aggr_en) +{ + switch (aggr_en) { + case (IPA_BYPASS_AGGR): + return "no aggregation"; + case (IPA_ENABLE_AGGR): + return "aggregation enabled"; + case (IPA_ENABLE_DEAGGR): + return "de-aggregation enabled"; + } + + return "undefined"; +} + +const char *ipa3_get_aggr_type_str(enum ipa_aggr_type aggr_type) +{ + switch (aggr_type) { + case (IPA_MBIM_16): + return "MBIM_16"; + case (IPA_HDLC): + return "HDLC"; + case (IPA_TLP): + return "TLP"; + case (IPA_RNDIS): + return "RNDIS"; + case (IPA_GENERIC): + return "GENERIC"; + case (IPA_QCMAP): + return "QCMAP"; + case (IPA_COALESCE): + return "COALESCE"; + } + return "undefined"; +} + +static u32 ipa3_time_gran_usec_step(enum ipa_timers_time_gran_type gran) +{ + switch (gran) { + case IPA_TIMERS_TIME_GRAN_10_USEC: return 10; + case IPA_TIMERS_TIME_GRAN_20_USEC: return 20; + case IPA_TIMERS_TIME_GRAN_50_USEC: return 50; + case IPA_TIMERS_TIME_GRAN_100_USEC: return 100; + case IPA_TIMERS_TIME_GRAN_1_MSEC: return 1000; + case IPA_TIMERS_TIME_GRAN_10_MSEC: return 10000; + case IPA_TIMERS_TIME_GRAN_100_MSEC: return 100000; + case IPA_TIMERS_TIME_GRAN_NEAR_HALF_SEC: return 655350; + default: + IPAERR("Invalid granularity time unit %d\n", gran); + ipa_assert(); + break; + } + + return 100; +} + +/* + * ipa3_process_timer_cfg() - Check and produce timer config + * + * Relevant for IPA 4.5 and above + * + * Assumes clocks are voted + */ +static int ipa3_process_timer_cfg(u32 time_us, + u8 *pulse_gen, u8 *time_units) +{ + struct ipahal_reg_timers_pulse_gran_cfg gran_cfg; + u32 gran0_step, gran1_step, gran2_step; + + IPADBG("time in usec=%u\n", time_us); + + if (ipa3_ctx->ipa_hw_type < IPA_HW_v4_5) { + IPAERR("Invalid IPA version %d\n", ipa3_ctx->ipa_hw_type); + return -EPERM; + } + + if (!time_us) { + *pulse_gen = 0; + *time_units = 0; + return 0; + } + + ipahal_read_reg_fields(IPA_TIMERS_PULSE_GRAN_CFG, &gran_cfg); + + gran0_step = ipa3_time_gran_usec_step(gran_cfg.gran_0); + gran1_step = ipa3_time_gran_usec_step(gran_cfg.gran_1); + gran2_step = ipa3_time_gran_usec_step(gran_cfg.gran_2); + /* gran_3 is not used by AP */ + + IPADBG("gran0 usec step=%u gran1 usec step=%u gran2 usec step=%u\n", + gran0_step, gran1_step, gran2_step); + + /* Lets try pulse generator #0 granularity */ + if (!(time_us % gran0_step)) { + if ((time_us / gran0_step) <= IPA_TIMER_SCALED_TIME_LIMIT) { + *pulse_gen = 0; + *time_units = time_us / gran0_step; + IPADBG("Matched: generator=0, units=%u\n", + *time_units); + return 0; + } + IPADBG("gran0 cannot be used due to range limit\n"); + } + + /* Lets try pulse generator #1 granularity */ + if (!(time_us % gran1_step)) { + if ((time_us / gran1_step) <= IPA_TIMER_SCALED_TIME_LIMIT) { + *pulse_gen = 1; + *time_units = time_us / gran1_step; + IPADBG("Matched: generator=1, units=%u\n", + *time_units); + return 0; + } + IPADBG("gran1 cannot be used due to range limit\n"); + } + + /* Lets try pulse generator #2 granularity */ + if (!(time_us % gran2_step)) { + if ((time_us / gran2_step) <= IPA_TIMER_SCALED_TIME_LIMIT) { + *pulse_gen = 2; + *time_units = time_us / gran2_step; + IPADBG("Matched: generator=2, units=%u\n", + *time_units); + return 0; + } + IPADBG("gran2 cannot be used due to range limit\n"); + } + + IPAERR("Cannot match requested time to configured granularities\n"); + return -EPERM; +} + +/** + * ipa3_cfg_ep_aggr() - IPA end-point aggregation configuration + * @clnt_hdl: [in] opaque client handle assigned by IPA to client + * @ipa_ep_cfg: [in] IPA end-point configuration params + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_cfg_ep_aggr(u32 clnt_hdl, const struct ipa_ep_cfg_aggr *ep_aggr) +{ + int res = 0; + + if (clnt_hdl >= ipa3_ctx->ipa_num_pipes || + ipa3_ctx->ep[clnt_hdl].valid == 0 || ep_aggr == NULL) { + IPAERR("bad parm, clnt_hdl = %d , ep_valid = %d\n", + clnt_hdl, ipa3_ctx->ep[clnt_hdl].valid); + return -EINVAL; + } + + if (ep_aggr->aggr_en == IPA_ENABLE_DEAGGR && + !IPA_EP_SUPPORTS_DEAGGR(clnt_hdl)) { + IPAERR("pipe=%d cannot be configured to DEAGGR\n", clnt_hdl); + WARN_ON(1); + return -EINVAL; + } + + IPADBG("pipe=%d en=%d(%s), type=%d(%s), byte_limit=%d, time_limit=%d\n", + clnt_hdl, + ep_aggr->aggr_en, + ipa3_get_aggr_enable_str(ep_aggr->aggr_en), + ep_aggr->aggr, + ipa3_get_aggr_type_str(ep_aggr->aggr), + ep_aggr->aggr_byte_limit, + ep_aggr->aggr_time_limit); + IPADBG("hard_byte_limit_en=%d aggr_sw_eof_active=%d\n", + ep_aggr->aggr_hard_byte_limit_en, + ep_aggr->aggr_sw_eof_active); + + /* copy over EP cfg */ + ipa3_ctx->ep[clnt_hdl].cfg.aggr = *ep_aggr; + + IPA_ACTIVE_CLIENTS_INC_EP(ipa3_get_client_mapping(clnt_hdl)); + + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_5) { + res = ipa3_process_timer_cfg(ep_aggr->aggr_time_limit, + &ipa3_ctx->ep[clnt_hdl].cfg.aggr.pulse_generator, + &ipa3_ctx->ep[clnt_hdl].cfg.aggr.scaled_time); + if (res) { + IPAERR("failed to process AGGR timer tmr=%u\n", + ep_aggr->aggr_time_limit); + res = -EINVAL; + goto complete; + } + /* + * HW bug on IPA4.5 where gran is used from pipe 0 instead of + * coal pipe. Add this check to make sure that RSC pipe will use + * gran 0 per the requested time needed; pipe 0 will use always + * gran 0 as gran 0 is the POR value of it and s/w never change + * it. + */ + if (ipa3_ctx->ipa_hw_type == IPA_HW_v4_5 && + ipa3_get_client_mapping(clnt_hdl) == + IPA_CLIENT_APPS_WAN_COAL_CONS && + ipa3_ctx->ep[clnt_hdl].cfg.aggr.pulse_generator != 0) { + IPAERR("coal pipe using GRAN_SEL = %d\n", + ipa3_ctx->ep[clnt_hdl].cfg.aggr.pulse_generator); + ipa_assert(); + } + } else { + /* + * Global aggregation granularity is 0.5msec. + * So if H/W programmed with 1msec, it will be + * 0.5msec defacto. + * So finest granularity is 0.5msec + */ + if (ep_aggr->aggr_time_limit % 500) { + IPAERR("given time limit %u is not in 0.5msec\n", + ep_aggr->aggr_time_limit); + WARN_ON(1); + res = -EINVAL; + goto complete; + } + + /* Due to described above global granularity */ + ipa3_ctx->ep[clnt_hdl].cfg.aggr.aggr_time_limit *= 2; + } + + ipahal_write_reg_n_fields(IPA_ENDP_INIT_AGGR_n, clnt_hdl, + &ipa3_ctx->ep[clnt_hdl].cfg.aggr); +complete: + IPA_ACTIVE_CLIENTS_DEC_EP(ipa3_get_client_mapping(clnt_hdl)); + return res; +} + +/** + * ipa3_cfg_ep_route() - IPA end-point routing configuration + * @clnt_hdl: [in] opaque client handle assigned by IPA to client + * @ipa_ep_cfg: [in] IPA end-point configuration params + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_cfg_ep_route(u32 clnt_hdl, const struct ipa_ep_cfg_route *ep_route) +{ + struct ipahal_reg_endp_init_route init_rt; + + if (clnt_hdl >= ipa3_ctx->ipa_num_pipes || + ipa3_ctx->ep[clnt_hdl].valid == 0 || ep_route == NULL) { + IPAERR("bad parm, clnt_hdl = %d , ep_valid = %d\n", + clnt_hdl, ipa3_ctx->ep[clnt_hdl].valid); + return -EINVAL; + } + + if (IPA_CLIENT_IS_CONS(ipa3_ctx->ep[clnt_hdl].client)) { + IPAERR("ROUTE does not apply to IPA out EP %d\n", + clnt_hdl); + return -EINVAL; + } + + /* + * if DMA mode was configured previously for this EP, return with + * success + */ + if (ipa3_ctx->ep[clnt_hdl].cfg.mode.mode == IPA_DMA) { + IPADBG("DMA enabled for ep %d, dst pipe is part of DMA\n", + clnt_hdl); + return 0; + } + + if (ep_route->rt_tbl_hdl) + IPAERR("client specified non-zero RT TBL hdl - ignore it\n"); + + IPADBG("pipe=%d, rt_tbl_hdl=%d\n", + clnt_hdl, + ep_route->rt_tbl_hdl); + + /* always use "default" routing table when programming EP ROUTE reg */ + ipa3_ctx->ep[clnt_hdl].rt_tbl_idx = + IPA_MEM_PART(v4_apps_rt_index_lo); + + if (ipa3_ctx->ipa_hw_type < IPA_HW_v4_0) { + IPA_ACTIVE_CLIENTS_INC_EP(ipa3_get_client_mapping(clnt_hdl)); + + init_rt.route_table_index = ipa3_ctx->ep[clnt_hdl].rt_tbl_idx; + ipahal_write_reg_n_fields(IPA_ENDP_INIT_ROUTE_n, + clnt_hdl, &init_rt); + + IPA_ACTIVE_CLIENTS_DEC_EP(ipa3_get_client_mapping(clnt_hdl)); + } + + return 0; +} + +#define MAX_ALLOWED_BASE_VAL 0x1f +#define MAX_ALLOWED_SCALE_VAL 0x1f + +/** + * ipa3_cal_ep_holb_scale_base_val - calculate base and scale value from tmr_val + * + * In IPA4.2 HW version need configure base and scale value in HOL timer reg + * @tmr_val: [in] timer value for HOL timer + * @ipa_ep_cfg: [out] Fill IPA end-point configuration base and scale value + * and return + */ +void ipa3_cal_ep_holb_scale_base_val(u32 tmr_val, + struct ipa_ep_cfg_holb *ep_holb) +{ + u32 base_val, scale, scale_val = 1, base = 2; + + for (scale = 0; scale <= MAX_ALLOWED_SCALE_VAL; scale++) { + base_val = tmr_val/scale_val; + if (scale != 0) + scale_val *= base; + if (base_val <= MAX_ALLOWED_BASE_VAL) + break; + } + ep_holb->base_val = base_val; + ep_holb->scale = scale_val; + +} + +/** + * ipa3_cfg_ep_holb() - IPA end-point holb configuration + * + * If an IPA producer pipe is full, IPA HW by default will block + * indefinitely till space opens up. During this time no packets + * including those from unrelated pipes will be processed. Enabling + * HOLB means IPA HW will be allowed to drop packets as/when needed + * and indefinite blocking is avoided. + * + * @clnt_hdl: [in] opaque client handle assigned by IPA to client + * @ipa_ep_cfg: [in] IPA end-point configuration params + * + * Returns: 0 on success, negative on failure + */ +int ipa3_cfg_ep_holb(u32 clnt_hdl, const struct ipa_ep_cfg_holb *ep_holb) +{ + if (clnt_hdl >= ipa3_ctx->ipa_num_pipes || + ipa3_ctx->ep[clnt_hdl].valid == 0 || ep_holb == NULL || + ep_holb->tmr_val > ipa3_ctx->ctrl->max_holb_tmr_val || + ep_holb->en > 1) { + IPAERR("bad parm.\n"); + return -EINVAL; + } + + if (IPA_CLIENT_IS_PROD(ipa3_ctx->ep[clnt_hdl].client)) { + IPAERR("HOLB does not apply to IPA in EP %d\n", clnt_hdl); + return -EINVAL; + } + + ipa3_ctx->ep[clnt_hdl].holb = *ep_holb; + + IPA_ACTIVE_CLIENTS_INC_EP(ipa3_get_client_mapping(clnt_hdl)); + + if (ep_holb->en == IPA_HOLB_TMR_DIS) { + ipahal_write_reg_n_fields(IPA_ENDP_INIT_HOL_BLOCK_EN_n, + clnt_hdl, ep_holb); + goto success; + } + + /* Follow HPG sequence to DIS_HOLB, Configure Timer, and HOLB_EN */ + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_5) { + ipa3_ctx->ep[clnt_hdl].holb.en = IPA_HOLB_TMR_DIS; + ipahal_write_reg_n_fields(IPA_ENDP_INIT_HOL_BLOCK_EN_n, + clnt_hdl, ep_holb); + } + + /* Configure timer */ + if (ipa3_ctx->ipa_hw_type == IPA_HW_v4_2) { + ipa3_cal_ep_holb_scale_base_val(ep_holb->tmr_val, + &ipa3_ctx->ep[clnt_hdl].holb); + } + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_5) { + int res; + + res = ipa3_process_timer_cfg(ep_holb->tmr_val * 1000, + &ipa3_ctx->ep[clnt_hdl].holb.pulse_generator, + &ipa3_ctx->ep[clnt_hdl].holb.scaled_time); + if (res) { + IPAERR("failed to process HOLB timer tmr=%u\n", + ep_holb->tmr_val); + ipa_assert(); + return res; + } + } + + ipahal_write_reg_n_fields(IPA_ENDP_INIT_HOL_BLOCK_TIMER_n, + clnt_hdl, &ipa3_ctx->ep[clnt_hdl].holb); + + /* Enable HOLB */ + ipa3_ctx->ep[clnt_hdl].holb.en = IPA_HOLB_TMR_EN; + ipahal_write_reg_n_fields(IPA_ENDP_INIT_HOL_BLOCK_EN_n, + clnt_hdl, ep_holb); + /* IPA4.5 issue requires HOLB_EN to be written twice */ + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_0) + ipahal_write_reg_n_fields(IPA_ENDP_INIT_HOL_BLOCK_EN_n, + clnt_hdl, ep_holb); + +success: + IPA_ACTIVE_CLIENTS_DEC_EP(ipa3_get_client_mapping(clnt_hdl)); + IPADBG("cfg holb %u ep=%d tmr=%d\n", ep_holb->en, clnt_hdl, + ep_holb->tmr_val); + return 0; +} +EXPORT_SYMBOL(ipa3_cfg_ep_holb); + +/** + * ipa3_force_cfg_ep_holb() - IPA end-point holb configuration + * for QDSS_MHI_CONS pipe + * + * If an IPA producer pipe is full, IPA HW by default will block + * indefinitely till space opens up. During this time no packets + * including those from unrelated pipes will be processed. Enabling + * HOLB means IPA HW will be allowed to drop packets as/when needed + * and indefinite blocking is avoided. + * + * @clnt_hdl: [in] opaque client handle assigned by IPA to client + * @ipa_ep_cfg: [in] IPA end-point configuration params + * + * Returns: 0 on success, negative on failure + */ +int ipa3_force_cfg_ep_holb(u32 clnt_hdl, + struct ipa_ep_cfg_holb *ep_holb) +{ + if (clnt_hdl >= ipa3_ctx->ipa_num_pipes || + ep_holb == NULL) { + IPAERR("bad parm.\n"); + return -EINVAL; + } + + IPA_ACTIVE_CLIENTS_INC_EP(ipa3_get_client_mapping(clnt_hdl)); + + if (ep_holb->en == IPA_HOLB_TMR_DIS) { + ipahal_write_reg_n_fields(IPA_ENDP_INIT_HOL_BLOCK_EN_n, + clnt_hdl, ep_holb); + goto success; + } + + /* Follow HPG sequence to DIS_HOLB, Configure Timer, and HOLB_EN */ + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_5) { + ep_holb->en = IPA_HOLB_TMR_DIS; + ipahal_write_reg_n_fields(IPA_ENDP_INIT_HOL_BLOCK_EN_n, + clnt_hdl, ep_holb); + } + + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_5) { + int res; + + res = ipa3_process_timer_cfg(ep_holb->tmr_val * 1000, + &ep_holb->pulse_generator, + &ep_holb->scaled_time); + if (res) { + IPAERR("failed to process HOLB timer tmr=%u\n", + ep_holb->tmr_val); + ipa_assert(); + return res; + } + } + + ipahal_write_reg_n_fields(IPA_ENDP_INIT_HOL_BLOCK_TIMER_n, + clnt_hdl, ep_holb); + + /* Enable HOLB */ + ep_holb->en = IPA_HOLB_TMR_EN; + ipahal_write_reg_n_fields(IPA_ENDP_INIT_HOL_BLOCK_EN_n, + clnt_hdl, ep_holb); + /* IPA4.5 issue requires HOLB_EN to be written twice */ + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_5) + ipahal_write_reg_n_fields(IPA_ENDP_INIT_HOL_BLOCK_EN_n, + clnt_hdl, ep_holb); + +success: + IPA_ACTIVE_CLIENTS_DEC_EP(ipa3_get_client_mapping(clnt_hdl)); + IPADBG("cfg holb %u ep=%d tmr=%d\n", ep_holb->en, clnt_hdl, + ep_holb->tmr_val); + return 0; +} + +/** + * ipa3_cfg_ep_holb_by_client() - IPA end-point holb configuration + * + * Wrapper function for ipa3_cfg_ep_holb() with client name instead of + * client handle. This function is used for clients that does not have + * client handle. + * + * @client: [in] client name + * @ipa_ep_cfg: [in] IPA end-point configuration params + * + * Returns: 0 on success, negative on failure + */ +int ipa3_cfg_ep_holb_by_client(enum ipa_client_type client, + const struct ipa_ep_cfg_holb *ep_holb) +{ + return ipa3_cfg_ep_holb(ipa_get_ep_mapping(client), ep_holb); +} + +/** + * ipa3_cfg_ep_deaggr() - IPA end-point deaggregation configuration + * @clnt_hdl: [in] opaque client handle assigned by IPA to client + * @ep_deaggr: [in] IPA end-point configuration params + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_cfg_ep_deaggr(u32 clnt_hdl, + const struct ipa_ep_cfg_deaggr *ep_deaggr) +{ + struct ipa3_ep_context *ep; + + if (clnt_hdl >= ipa3_ctx->ipa_num_pipes || + ipa3_ctx->ep[clnt_hdl].valid == 0 || ep_deaggr == NULL) { + IPAERR("bad parm, clnt_hdl = %d , ep_valid = %d\n", + clnt_hdl, ipa3_ctx->ep[clnt_hdl].valid); + return -EINVAL; + } + + IPADBG("pipe=%d deaggr_hdr_len=%d\n", + clnt_hdl, + ep_deaggr->deaggr_hdr_len); + + IPADBG("syspipe_err_detection=%d\n", + ep_deaggr->syspipe_err_detection); + + IPADBG("packet_offset_valid=%d\n", + ep_deaggr->packet_offset_valid); + + IPADBG("packet_offset_location=%d max_packet_len=%d\n", + ep_deaggr->packet_offset_location, + ep_deaggr->max_packet_len); + + IPADBG("ignore_min_pkt_err=%d\n", + ep_deaggr->ignore_min_pkt_err); + + ep = &ipa3_ctx->ep[clnt_hdl]; + + /* copy over EP cfg */ + ep->cfg.deaggr = *ep_deaggr; + + IPA_ACTIVE_CLIENTS_INC_EP(ipa3_get_client_mapping(clnt_hdl)); + + ipahal_write_reg_n_fields(IPA_ENDP_INIT_DEAGGR_n, clnt_hdl, + &ep->cfg.deaggr); + + IPA_ACTIVE_CLIENTS_DEC_EP(ipa3_get_client_mapping(clnt_hdl)); + + return 0; +} + +/** + * ipa3_cfg_ep_metadata() - IPA end-point metadata configuration + * @clnt_hdl: [in] opaque client handle assigned by IPA to client + * @ipa_ep_cfg: [in] IPA end-point configuration params + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_cfg_ep_metadata(u32 clnt_hdl, const struct ipa_ep_cfg_metadata *ep_md) +{ + u32 qmap_id = 0; + struct ipa_ep_cfg_metadata ep_md_reg_wrt; + + if (clnt_hdl >= ipa3_ctx->ipa_num_pipes || + ipa3_ctx->ep[clnt_hdl].valid == 0 || ep_md == NULL) { + IPAERR("bad parm, clnt_hdl = %d , ep_valid = %d\n", + clnt_hdl, ipa3_ctx->ep[clnt_hdl].valid); + return -EINVAL; + } + + IPADBG("pipe=%d, mux id=%d\n", clnt_hdl, ep_md->qmap_id); + + /* copy over EP cfg */ + ipa3_ctx->ep[clnt_hdl].cfg.meta = *ep_md; + + IPA_ACTIVE_CLIENTS_INC_EP(ipa3_get_client_mapping(clnt_hdl)); + + if (ipa3_ctx->eogre_enabled) { + /* reconfigure ep metadata reg to override mux-id */ + ipa3_ctx->ep[clnt_hdl].cfg.hdr.hdr_ofst_metadata_valid = 0; + ipa3_ctx->ep[clnt_hdl].cfg.hdr.hdr_ofst_metadata = 0; + ipa3_ctx->ep[clnt_hdl].cfg.hdr.hdr_metadata_reg_valid = 1; + ipahal_write_reg_n_fields(IPA_ENDP_INIT_HDR_n, clnt_hdl, + &ipa3_ctx->ep[clnt_hdl].cfg.hdr); + } + + ep_md_reg_wrt = *ep_md; + qmap_id = (ep_md->qmap_id << + IPA_ENDP_INIT_HDR_METADATA_n_MUX_ID_SHFT) & + IPA_ENDP_INIT_HDR_METADATA_n_MUX_ID_BMASK; + + /* mark tethering bit for remote modem */ + if (ipa3_ctx->ipa_hw_type == IPA_HW_v4_1) + qmap_id |= IPA_QMAP_TETH_BIT; + + ep_md_reg_wrt.qmap_id = qmap_id; + ipahal_write_reg_n_fields(IPA_ENDP_INIT_HDR_METADATA_n, clnt_hdl, + &ep_md_reg_wrt); + if (ipa3_ctx->ipa_hw_type < IPA_HW_v4_5) { + ipa3_ctx->ep[clnt_hdl].cfg.hdr.hdr_metadata_reg_valid = 1; + ipahal_write_reg_n_fields(IPA_ENDP_INIT_HDR_n, clnt_hdl, + &ipa3_ctx->ep[clnt_hdl].cfg.hdr); + } + + IPA_ACTIVE_CLIENTS_DEC_EP(ipa3_get_client_mapping(clnt_hdl)); + + return 0; +} + +int ipa3_write_qmap_id(struct ipa_ioc_write_qmapid *param_in) +{ + struct ipa_ep_cfg_metadata meta; + struct ipa3_ep_context *ep; + int ipa_ep_idx; + int result = -EINVAL; + + if (param_in->client >= IPA_CLIENT_MAX) { + IPAERR_RL("bad parm client:%d\n", param_in->client); + goto fail; + } + + ipa_ep_idx = ipa_get_ep_mapping(param_in->client); + if (ipa_ep_idx == -1) { + IPAERR_RL("Invalid client.\n"); + goto fail; + } + + ep = &ipa3_ctx->ep[ipa_ep_idx]; + if (!ep->valid) { + IPAERR_RL("EP not allocated.\n"); + goto fail; + } + + meta.qmap_id = param_in->qmap_id; + if (param_in->client == IPA_CLIENT_USB_PROD || + param_in->client == IPA_CLIENT_USB2_PROD || + param_in->client == IPA_CLIENT_HSIC1_PROD || + param_in->client == IPA_CLIENT_ODU_PROD || + param_in->client == IPA_CLIENT_ETHERNET_PROD || + param_in->client == IPA_CLIENT_ETHERNET2_PROD || + param_in->client == IPA_CLIENT_WIGIG_PROD || + param_in->client == IPA_CLIENT_AQC_ETHERNET_PROD || + param_in->client == IPA_CLIENT_RTK_ETHERNET_PROD) { + result = ipa3_cfg_ep_metadata(ipa_ep_idx, &meta); + } else if (param_in->client == IPA_CLIENT_WLAN1_PROD || + param_in->client == IPA_CLIENT_WLAN2_PROD) { + ipa3_ctx->ep[ipa_ep_idx].cfg.meta = meta; + if (param_in->client == IPA_CLIENT_WLAN2_PROD) + result = ipa3_write_qmapid_wdi3_gsi_pipe( + ipa_ep_idx, meta.qmap_id); + else + result = ipa3_write_qmapid_wdi_pipe( + ipa_ep_idx, meta.qmap_id); + if (result) + IPAERR_RL("qmap_id %d write failed on ep=%d\n", + meta.qmap_id, ipa_ep_idx); + result = 0; + } + +fail: + return result; +} + +/** + * ipa3_dump_buff_internal() - dumps buffer for debug purposes + * @base: buffer base address + * @phy_base: buffer physical base address + * @size: size of the buffer + */ +void ipa3_dump_buff_internal(void *base, dma_addr_t phy_base, u32 size) +{ + int i; + u32 *cur = (u32 *)base; + u8 *byt; + + IPADBG("system phys addr=%pa len=%u\n", &phy_base, size); + for (i = 0; i < size / 4; i++) { + byt = (u8 *)(cur + i); + IPADBG("%2d %08x %02x %02x %02x %02x\n", i, *(cur + i), + byt[0], byt[1], byt[2], byt[3]); + } + IPADBG("END\n"); +} + +/** + * ipa_set_aggr_mode() - Set the aggregation mode which is a global setting + * @mode: [in] the desired aggregation mode for e.g. straight MBIM, QCNCM, + * etc + * + * Returns: 0 on success + */ +int ipa_set_aggr_mode(enum ipa_aggr_mode mode) +{ + struct ipahal_reg_qcncm qcncm; + + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_0) { + if (mode != IPA_MBIM_AGGR) { + IPAERR("Only MBIM mode is supported staring 4.0\n"); + return -EPERM; + } + } else { + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + ipahal_read_reg_fields(IPA_QCNCM, &qcncm); + qcncm.mode_en = mode; + ipahal_write_reg_fields(IPA_QCNCM, &qcncm); + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + } + + return 0; +} +EXPORT_SYMBOL(ipa_set_aggr_mode); + +/** + * ipa_set_qcncm_ndp_sig() - Set the NDP signature used for QCNCM aggregation + * mode + * @sig: [in] the first 3 bytes of QCNCM NDP signature (expected to be + * "QND") + * + * Set the NDP signature used for QCNCM aggregation mode. The fourth byte + * (expected to be 'P') needs to be set using the header addition mechanism + * + * Returns: 0 on success, negative on failure + */ +int ipa_set_qcncm_ndp_sig(char sig[3]) +{ + struct ipahal_reg_qcncm qcncm; + + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_0) { + IPAERR("QCNCM mode is not supported staring 4.0\n"); + return -EPERM; + } + + if (sig == NULL) { + IPAERR("bad argument\n"); + return -EINVAL; + } + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + ipahal_read_reg_fields(IPA_QCNCM, &qcncm); + qcncm.mode_val = ((sig[0] << 16) | (sig[1] << 8) | sig[2]); + ipahal_write_reg_fields(IPA_QCNCM, &qcncm); + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + + return 0; +} +EXPORT_SYMBOL(ipa_set_qcncm_ndp_sig); + +/** + * ipa_set_single_ndp_per_mbim() - Enable/disable single NDP per MBIM frame + * configuration + * @enable: [in] true for single NDP/MBIM; false otherwise + * + * Returns: 0 on success + */ +int ipa_set_single_ndp_per_mbim(bool enable) +{ + struct ipahal_reg_single_ndp_mode mode; + + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_0) { + IPAERR("QCNCM mode is not supported staring 4.0\n"); + return -EPERM; + } + + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + ipahal_read_reg_fields(IPA_SINGLE_NDP_MODE, &mode); + mode.single_ndp_en = enable; + ipahal_write_reg_fields(IPA_SINGLE_NDP_MODE, &mode); + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + + return 0; +} +EXPORT_SYMBOL(ipa_set_single_ndp_per_mbim); + +/** + * ipa3_straddle_boundary() - Checks whether a memory buffer straddles a + * boundary + * @start: start address of the memory buffer + * @end: end address of the memory buffer + * @boundary: boundary + * + * Return value: + * 1: if the interval [start, end] straddles boundary + * 0: otherwise + */ +int ipa3_straddle_boundary(u32 start, u32 end, u32 boundary) +{ + u32 next_start; + u32 prev_end; + + IPADBG("start=%u end=%u boundary=%u\n", start, end, boundary); + + next_start = (start + (boundary - 1)) & ~(boundary - 1); + prev_end = ((end + (boundary - 1)) & ~(boundary - 1)) - boundary; + + while (next_start < prev_end) + next_start += boundary; + + if (next_start == prev_end) + return 1; + else + return 0; +} + +/** + * ipa3_init_mem_partition() - Assigns the static memory partition + * based on the IPA version + * + * Returns: 0 on success + */ +int ipa3_init_mem_partition(enum ipa_hw_type type) +{ + switch (type) { + case IPA_HW_v4_1: + ipa3_ctx->ctrl->mem_partition = &ipa_4_1_mem_part; + break; + case IPA_HW_v4_2: + ipa3_ctx->ctrl->mem_partition = &ipa_4_2_mem_part; + break; + case IPA_HW_v4_5: + ipa3_ctx->ctrl->mem_partition = &ipa_4_5_mem_part; + break; + case IPA_HW_v4_7: + ipa3_ctx->ctrl->mem_partition = &ipa_4_7_mem_part; + break; + case IPA_HW_v4_9: + ipa3_ctx->ctrl->mem_partition = &ipa_4_9_mem_part; + break; + case IPA_HW_v4_11: + ipa3_ctx->ctrl->mem_partition = &ipa_4_11_mem_part; + break; + case IPA_HW_v5_0: + ipa3_ctx->ctrl->mem_partition = &ipa_5_0_mem_part; + break; + case IPA_HW_v5_1: + ipa3_ctx->ctrl->mem_partition = &ipa_5_1_mem_part; + break; + case IPA_HW_v5_2: + ipa3_ctx->ctrl->mem_partition = &ipa_5_2_mem_part; + break; + case IPA_HW_v5_5: + ipa3_ctx->ctrl->mem_partition = &ipa_5_5_mem_part; + break; + case IPA_HW_None: + case IPA_HW_v1_0: + case IPA_HW_v1_1: + case IPA_HW_v2_0: + case IPA_HW_v2_1: + case IPA_HW_v2_5: + case IPA_HW_v2_6L: + case IPA_HW_v3_0: + ipa3_ctx->ctrl->mem_partition = &ipa_3_0_mem_part; + break; + case IPA_HW_v3_1: + case IPA_HW_v3_5: + case IPA_HW_v3_5_1: + case IPA_HW_v4_0: + default: + IPAERR("unsupported version %d\n", type); + return -EPERM; + } + + IPADBG("UC OFST 0x%x SIZE 0x%x\n", + IPA_MEM_PART(uc_ofst), IPA_MEM_PART(uc_size)); + + if (IPA_MEM_PART(uc_info_ofst) & 3) { + IPAERR("UC INFO OFST 0x%x is unaligned\n", + IPA_MEM_PART(uc_info_ofst)); + return -ENODEV; + } + + IPADBG("UC INFO OFST 0x%x SIZE 0x%x\n", + IPA_MEM_PART(uc_info_ofst), IPA_MEM_PART(uc_info_size)); + + IPADBG("RAM OFST 0x%x\n", IPA_MEM_PART(ofst_start)); + + if (IPA_MEM_PART(v4_flt_hash_ofst) & 7) { + IPAERR("V4 FLT HASHABLE OFST 0x%x is unaligned\n", + IPA_MEM_PART(v4_flt_hash_ofst)); + return -ENODEV; + } + + IPADBG("V4 FLT HASHABLE OFST 0x%x SIZE 0x%x DDR SIZE 0x%x\n", + IPA_MEM_PART(v4_flt_hash_ofst), + IPA_MEM_PART(v4_flt_hash_size), + IPA_MEM_PART(v4_flt_hash_size_ddr)); + + if (IPA_MEM_PART(v4_flt_nhash_ofst) & 7) { + IPAERR("V4 FLT NON-HASHABLE OFST 0x%x is unaligned\n", + IPA_MEM_PART(v4_flt_nhash_ofst)); + return -ENODEV; + } + + IPADBG("V4 FLT NON-HASHABLE OFST 0x%x SIZE 0x%x DDR SIZE 0x%x\n", + IPA_MEM_PART(v4_flt_nhash_ofst), + IPA_MEM_PART(v4_flt_nhash_size), + IPA_MEM_PART(v4_flt_nhash_size_ddr)); + + if (IPA_MEM_PART(v6_flt_hash_ofst) & 7) { + IPAERR("V6 FLT HASHABLE OFST 0x%x is unaligned\n", + IPA_MEM_PART(v6_flt_hash_ofst)); + return -ENODEV; + } + + IPADBG("V6 FLT HASHABLE OFST 0x%x SIZE 0x%x DDR SIZE 0x%x\n", + IPA_MEM_PART(v6_flt_hash_ofst), IPA_MEM_PART(v6_flt_hash_size), + IPA_MEM_PART(v6_flt_hash_size_ddr)); + + if (IPA_MEM_PART(v6_flt_nhash_ofst) & 7) { + IPAERR("V6 FLT NON-HASHABLE OFST 0x%x is unaligned\n", + IPA_MEM_PART(v6_flt_nhash_ofst)); + return -ENODEV; + } + + IPADBG("V6 FLT NON-HASHABLE OFST 0x%x SIZE 0x%x DDR SIZE 0x%x\n", + IPA_MEM_PART(v6_flt_nhash_ofst), + IPA_MEM_PART(v6_flt_nhash_size), + IPA_MEM_PART(v6_flt_nhash_size_ddr)); + + IPADBG("V4 RT NUM INDEX 0x%x\n", IPA_MEM_PART(v4_rt_num_index)); + + IPADBG("V4 RT MODEM INDEXES 0x%x - 0x%x\n", + IPA_MEM_PART(v4_modem_rt_index_lo), + IPA_MEM_PART(v4_modem_rt_index_hi)); + + IPADBG("V4 RT APPS INDEXES 0x%x - 0x%x\n", + IPA_MEM_PART(v4_apps_rt_index_lo), + IPA_MEM_PART(v4_apps_rt_index_hi)); + + if (IPA_MEM_PART(v4_rt_hash_ofst) & 7) { + IPAERR("V4 RT HASHABLE OFST 0x%x is unaligned\n", + IPA_MEM_PART(v4_rt_hash_ofst)); + return -ENODEV; + } + + IPADBG("V4 RT HASHABLE OFST 0x%x\n", IPA_MEM_PART(v4_rt_hash_ofst)); + + IPADBG("V4 RT HASHABLE SIZE 0x%x DDR SIZE 0x%x\n", + IPA_MEM_PART(v4_rt_hash_size), + IPA_MEM_PART(v4_rt_hash_size_ddr)); + + if (IPA_MEM_PART(v4_rt_nhash_ofst) & 7) { + IPAERR("V4 RT NON-HASHABLE OFST 0x%x is unaligned\n", + IPA_MEM_PART(v4_rt_nhash_ofst)); + return -ENODEV; + } + + IPADBG("V4 RT NON-HASHABLE OFST 0x%x\n", + IPA_MEM_PART(v4_rt_nhash_ofst)); + + IPADBG("V4 RT HASHABLE SIZE 0x%x DDR SIZE 0x%x\n", + IPA_MEM_PART(v4_rt_nhash_size), + IPA_MEM_PART(v4_rt_nhash_size_ddr)); + + IPADBG("V6 RT NUM INDEX 0x%x\n", IPA_MEM_PART(v6_rt_num_index)); + + IPADBG("V6 RT MODEM INDEXES 0x%x - 0x%x\n", + IPA_MEM_PART(v6_modem_rt_index_lo), + IPA_MEM_PART(v6_modem_rt_index_hi)); + + IPADBG("V6 RT APPS INDEXES 0x%x - 0x%x\n", + IPA_MEM_PART(v6_apps_rt_index_lo), + IPA_MEM_PART(v6_apps_rt_index_hi)); + + if (IPA_MEM_PART(v6_rt_hash_ofst) & 7) { + IPAERR("V6 RT HASHABLE OFST 0x%x is unaligned\n", + IPA_MEM_PART(v6_rt_hash_ofst)); + return -ENODEV; + } + + IPADBG("V6 RT HASHABLE OFST 0x%x\n", IPA_MEM_PART(v6_rt_hash_ofst)); + + IPADBG("V6 RT HASHABLE SIZE 0x%x DDR SIZE 0x%x\n", + IPA_MEM_PART(v6_rt_hash_size), + IPA_MEM_PART(v6_rt_hash_size_ddr)); + + if (IPA_MEM_PART(v6_rt_nhash_ofst) & 7) { + IPAERR("V6 RT NON-HASHABLE OFST 0x%x is unaligned\n", + IPA_MEM_PART(v6_rt_nhash_ofst)); + return -ENODEV; + } + + IPADBG("V6 RT NON-HASHABLE OFST 0x%x\n", + IPA_MEM_PART(v6_rt_nhash_ofst)); + + IPADBG("V6 RT NON-HASHABLE SIZE 0x%x DDR SIZE 0x%x\n", + IPA_MEM_PART(v6_rt_nhash_size), + IPA_MEM_PART(v6_rt_nhash_size_ddr)); + + if (IPA_MEM_PART(modem_hdr_ofst) & 7) { + IPAERR("MODEM HDR OFST 0x%x is unaligned\n", + IPA_MEM_PART(modem_hdr_ofst)); + return -ENODEV; + } + + IPADBG("MODEM HDR OFST 0x%x SIZE 0x%x\n", + IPA_MEM_PART(modem_hdr_ofst), IPA_MEM_PART(modem_hdr_size)); + + if (IPA_MEM_PART(apps_hdr_ofst) & 7) { + IPAERR("APPS HDR OFST 0x%x is unaligned\n", + IPA_MEM_PART(apps_hdr_ofst)); + return -ENODEV; + } + + IPADBG("APPS HDR OFST 0x%x SIZE 0x%x DDR SIZE 0x%x\n", + IPA_MEM_PART(apps_hdr_ofst), IPA_MEM_PART(apps_hdr_size), + IPA_MEM_PART(apps_hdr_size_ddr)); + + if (IPA_MEM_PART(modem_hdr_proc_ctx_ofst) & 7) { + IPAERR("MODEM HDR PROC CTX OFST 0x%x is unaligned\n", + IPA_MEM_PART(modem_hdr_proc_ctx_ofst)); + return -ENODEV; + } + + IPADBG("MODEM HDR PROC CTX OFST 0x%x SIZE 0x%x\n", + IPA_MEM_PART(modem_hdr_proc_ctx_ofst), + IPA_MEM_PART(modem_hdr_proc_ctx_size)); + + if (IPA_MEM_PART(apps_hdr_proc_ctx_ofst) & 7) { + IPAERR("APPS HDR PROC CTX OFST 0x%x is unaligned\n", + IPA_MEM_PART(apps_hdr_proc_ctx_ofst)); + return -ENODEV; + } + + IPADBG("APPS HDR PROC CTX OFST 0x%x SIZE 0x%x DDR SIZE 0x%x\n", + IPA_MEM_PART(apps_hdr_proc_ctx_ofst), + IPA_MEM_PART(apps_hdr_proc_ctx_size), + IPA_MEM_PART(apps_hdr_proc_ctx_size_ddr)); + + if (IPA_MEM_PART(pdn_config_ofst) & 7) { + IPAERR("PDN CONFIG OFST 0x%x is unaligned\n", + IPA_MEM_PART(pdn_config_ofst)); + return -ENODEV; + } + + /* + * Routing rules points to hdr_proc_ctx in 32byte offsets from base. + * Base is modem hdr_proc_ctx first address. + * AP driver install APPS hdr_proc_ctx starting at the beginning of + * apps hdr_proc_ctx part. + * So first apps hdr_proc_ctx offset at some routing + * rule will be modem_hdr_proc_ctx_size >> 5 (32B). + */ + if (IPA_MEM_PART(modem_hdr_proc_ctx_size) & 31) { + IPAERR("MODEM HDR PROC CTX SIZE 0x%x is not 32B aligned\n", + IPA_MEM_PART(modem_hdr_proc_ctx_size)); + return -ENODEV; + } + + /* + * AP driver when installing routing rule, it calcs the hdr_proc_ctx + * offset by local offset (from base of apps part) + + * modem_hdr_proc_ctx_size. This is to get offset from modem part base. + * Thus apps part must be adjacent to modem part + */ + if (IPA_MEM_PART(apps_hdr_proc_ctx_ofst) != + IPA_MEM_PART(modem_hdr_proc_ctx_ofst) + + IPA_MEM_PART(modem_hdr_proc_ctx_size)) { + IPAERR("APPS HDR PROC CTX SIZE not adjacent to MODEM one!\n"); + return -ENODEV; + } + + IPADBG("NAT TBL OFST 0x%x SIZE 0x%x\n", + IPA_MEM_PART(nat_tbl_ofst), + IPA_MEM_PART(nat_tbl_size)); + + if (IPA_MEM_PART(nat_tbl_ofst) & 31) { + IPAERR("NAT TBL OFST 0x%x is not aligned properly\n", + IPA_MEM_PART(nat_tbl_ofst)); + return -ENODEV; + } + + IPADBG("PDN CONFIG OFST 0x%x SIZE 0x%x\n", + IPA_MEM_PART(pdn_config_ofst), + IPA_MEM_PART(pdn_config_size)); + + if (IPA_MEM_PART(pdn_config_ofst) & 7) { + IPAERR("PDN CONFIG OFST 0x%x is unaligned\n", + IPA_MEM_PART(pdn_config_ofst)); + return -ENODEV; + } + + IPADBG("Q6 QUOTA STATS OFST 0x%x SIZE 0x%x\n", + IPA_MEM_PART(stats_quota_q6_ofst), + IPA_MEM_PART(stats_quota_q6_size)); + + if (IPA_MEM_PART(stats_quota_q6_ofst) & 7) { + IPAERR("Q6 QUOTA STATS OFST 0x%x is unaligned\n", + IPA_MEM_PART(stats_quota_q6_ofst)); + return -ENODEV; + } + + IPADBG("AP QUOTA STATS OFST 0x%x SIZE 0x%x\n", + IPA_MEM_PART(stats_quota_ap_ofst), + IPA_MEM_PART(stats_quota_ap_size)); + + if (IPA_MEM_PART(stats_quota_ap_ofst) & 7) { + IPAERR("AP QUOTA STATS OFST 0x%x is unaligned\n", + IPA_MEM_PART(stats_quota_ap_ofst)); + return -ENODEV; + } + + IPADBG("TETHERING STATS OFST 0x%x SIZE 0x%x\n", + IPA_MEM_PART(stats_tethering_ofst), + IPA_MEM_PART(stats_tethering_size)); + + if (IPA_MEM_PART(stats_tethering_ofst) & 7) { + IPAERR("TETHERING STATS OFST 0x%x is unaligned\n", + IPA_MEM_PART(stats_tethering_ofst)); + return -ENODEV; + } + + IPADBG("FILTER AND ROUTING STATS OFST 0x%x SIZE 0x%x\n", + IPA_MEM_PART(stats_fnr_ofst), + IPA_MEM_PART(stats_fnr_size)); + + if (IPA_MEM_PART(stats_fnr_ofst) & 7) { + IPAERR("FILTER AND ROUTING STATS OFST 0x%x is unaligned\n", + IPA_MEM_PART(stats_fnr_ofst)); + return -ENODEV; + } + + IPADBG("DROP STATS OFST 0x%x SIZE 0x%x\n", + IPA_MEM_PART(stats_drop_ofst), + IPA_MEM_PART(stats_drop_size)); + + if (IPA_MEM_PART(stats_drop_ofst) & 7) { + IPAERR("DROP STATS OFST 0x%x is unaligned\n", + IPA_MEM_PART(stats_drop_ofst)); + return -ENODEV; + } + + IPADBG("V4 APPS HASHABLE FLT OFST 0x%x SIZE 0x%x\n", + IPA_MEM_PART(apps_v4_flt_hash_ofst), + IPA_MEM_PART(apps_v4_flt_hash_size)); + + IPADBG("V4 APPS NON-HASHABLE FLT OFST 0x%x SIZE 0x%x\n", + IPA_MEM_PART(apps_v4_flt_nhash_ofst), + IPA_MEM_PART(apps_v4_flt_nhash_size)); + + IPADBG("V6 APPS HASHABLE FLT OFST 0x%x SIZE 0x%x\n", + IPA_MEM_PART(apps_v6_flt_hash_ofst), + IPA_MEM_PART(apps_v6_flt_hash_size)); + + IPADBG("V6 APPS NON-HASHABLE FLT OFST 0x%x SIZE 0x%x\n", + IPA_MEM_PART(apps_v6_flt_nhash_ofst), + IPA_MEM_PART(apps_v6_flt_nhash_size)); + + IPADBG("RAM END OFST 0x%x\n", + IPA_MEM_PART(end_ofst)); + + IPADBG("V4 APPS HASHABLE RT OFST 0x%x SIZE 0x%x\n", + IPA_MEM_PART(apps_v4_rt_hash_ofst), + IPA_MEM_PART(apps_v4_rt_hash_size)); + + IPADBG("V4 APPS NON-HASHABLE RT OFST 0x%x SIZE 0x%x\n", + IPA_MEM_PART(apps_v4_rt_nhash_ofst), + IPA_MEM_PART(apps_v4_rt_nhash_size)); + + IPADBG("V6 APPS HASHABLE RT OFST 0x%x SIZE 0x%x\n", + IPA_MEM_PART(apps_v6_rt_hash_ofst), + IPA_MEM_PART(apps_v6_rt_hash_size)); + + IPADBG("V6 APPS NON-HASHABLE RT OFST 0x%x SIZE 0x%x\n", + IPA_MEM_PART(apps_v6_rt_nhash_ofst), + IPA_MEM_PART(apps_v6_rt_nhash_size)); + + if (IPA_MEM_PART(modem_ofst) & 7) { + IPAERR("MODEM OFST 0x%x is unaligned\n", + IPA_MEM_PART(modem_ofst)); + return -ENODEV; + } + + IPADBG("MODEM OFST 0x%x SIZE 0x%x\n", IPA_MEM_PART(modem_ofst), + IPA_MEM_PART(modem_size)); + + if (IPA_MEM_PART(uc_descriptor_ram_ofst) & 1023) { + IPAERR("UC DESCRIPTOR RAM OFST 0x%x is unaligned\n", + IPA_MEM_PART(uc_descriptor_ram_ofst)); + return -ENODEV; + } + + IPADBG("UC DESCRIPTOR RAM OFST 0x%x SIZE 0x%x\n", + IPA_MEM_PART(uc_descriptor_ram_ofst), + IPA_MEM_PART(uc_descriptor_ram_size)); + + return 0; +} + +/** + * ipa_ctrl_static_bind() - set the appropriate methods for + * IPA Driver based on the HW version + * + * @ctrl: data structure which holds the function pointers + * @hw_type: the HW type in use + * + * This function can avoid the runtime assignment by using C99 special + * struct initialization - hard decision... time.vs.mem + */ +int ipa3_controller_static_bind(struct ipa3_controller *ctrl, + enum ipa_hw_type hw_type, u32 ipa_cfg_offset) +{ + if (hw_type >= IPA_HW_v5_0) { + ctrl->ipa_clk_rate_turbo = IPA_V5_0_CLK_RATE_TURBO; + ctrl->ipa_clk_rate_nominal = IPA_V5_0_CLK_RATE_NOMINAL; + ctrl->ipa_clk_rate_svs = IPA_V5_0_CLK_RATE_SVS; + ctrl->ipa_clk_rate_svs2 = IPA_V5_0_CLK_RATE_SVS2; + } else if (hw_type >= IPA_HW_v4_0) { + ctrl->ipa_clk_rate_turbo = IPA_V4_0_CLK_RATE_TURBO; + ctrl->ipa_clk_rate_nominal = IPA_V4_0_CLK_RATE_NOMINAL; + ctrl->ipa_clk_rate_svs = IPA_V4_0_CLK_RATE_SVS; + ctrl->ipa_clk_rate_svs2 = IPA_V4_0_CLK_RATE_SVS2; + } else if (hw_type >= IPA_HW_v3_5) { + ctrl->ipa_clk_rate_turbo = IPA_V3_5_CLK_RATE_TURBO; + ctrl->ipa_clk_rate_nominal = IPA_V3_5_CLK_RATE_NOMINAL; + ctrl->ipa_clk_rate_svs = IPA_V3_5_CLK_RATE_SVS; + ctrl->ipa_clk_rate_svs2 = IPA_V3_5_CLK_RATE_SVS2; + } else { + ctrl->ipa_clk_rate_turbo = IPA_V3_0_CLK_RATE_TURBO; + ctrl->ipa_clk_rate_nominal = IPA_V3_0_CLK_RATE_NOMINAL; + ctrl->ipa_clk_rate_svs = IPA_V3_0_CLK_RATE_SVS; + ctrl->ipa_clk_rate_svs2 = IPA_V3_0_CLK_RATE_SVS2; + } + + ctrl->ipa_init_rt4 = _ipa_init_rt4_v3; + ctrl->ipa_init_rt6 = _ipa_init_rt6_v3; + ctrl->ipa_init_flt4 = _ipa_init_flt4_v3; + ctrl->ipa_init_flt6 = _ipa_init_flt6_v3; + ctrl->ipa3_read_ep_reg = _ipa_read_ep_reg_v3_0; + ctrl->ipa3_commit_flt = __ipa_commit_flt_v3; + ctrl->ipa3_commit_rt = __ipa_commit_rt_v3; + ctrl->ipa3_commit_hdr = __ipa_commit_hdr_v3_0; + ctrl->ipa3_enable_clks = _ipa_enable_clks_v3_0; + ctrl->ipa3_disable_clks = _ipa_disable_clks_v3_0; + ctrl->clock_scaling_bw_threshold_svs = + IPA_V3_0_BW_THRESHOLD_SVS_MBPS; + ctrl->clock_scaling_bw_threshold_nominal = + IPA_V3_0_BW_THRESHOLD_NOMINAL_MBPS; + ctrl->clock_scaling_bw_threshold_turbo = + IPA_V3_0_BW_THRESHOLD_TURBO_MBPS; + ctrl->ipa_reg_base_ofst = ipa_cfg_offset == 0 ? + ipahal_get_reg_base() : ipa_cfg_offset; + ctrl->ipa_init_sram = _ipa_init_sram_v3; + ctrl->ipa_sram_read_settings = _ipa_sram_settings_read_v3_0; + ctrl->ipa_init_hdr = _ipa_init_hdr_v3_0; + ctrl->max_holb_tmr_val = IPA_MAX_HOLB_TMR_VAL; + + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_0) + ctrl->ipa3_read_ep_reg = _ipa_read_ep_reg_v4_0; + + return 0; +} + +void ipa3_skb_recycle(struct sk_buff *skb) +{ + struct skb_shared_info *shinfo; + + shinfo = skb_shinfo(skb); + memset(shinfo, 0, offsetof(struct skb_shared_info, dataref)); + atomic_set(&shinfo->dataref, 1); + + memset(skb, 0, offsetof(struct sk_buff, tail)); + skb->data = skb->head + NET_SKB_PAD; + skb_reset_tail_pointer(skb); +} + +int ipa3_alloc_rule_id(struct idr *rule_ids) +{ + /* There is two groups of rule-Ids, Modem ones and Apps ones. + * Distinction by high bit: Modem Ids are high bit asserted. + */ + return idr_alloc(rule_ids, NULL, + ipahal_get_low_rule_id(), + ipahal_get_rule_id_hi_bit(), + GFP_KERNEL); +} + +static int __ipa3_alloc_counter_hdl + (struct ipa_ioc_flt_rt_counter_alloc *counter) +{ + int id; + + /* assign a handle using idr to this counter block */ + id = idr_alloc(&ipa3_ctx->flt_rt_counters.hdl, counter, + ipahal_get_low_hdl_id(), ipahal_get_high_hdl_id(), + GFP_ATOMIC); + + return id; +} + +int ipa3_alloc_counter_id(struct ipa_ioc_flt_rt_counter_alloc *header) +{ + int i, unused_cnt, unused_max, unused_start_id; + struct ipa_ioc_flt_rt_counter_alloc *counter; + + counter = kmem_cache_zalloc(ipa3_ctx->fnr_stats_cache, GFP_KERNEL); + if (!counter) { + IPAERR_RL("failed to alloc fnr stats counter object\n"); + spin_unlock(&ipa3_ctx->flt_rt_counters.hdl_lock); + return -ENOMEM; + } + + idr_preload(GFP_KERNEL); + spin_lock(&ipa3_ctx->flt_rt_counters.hdl_lock); + memcpy(counter, header, sizeof(struct ipa_ioc_flt_rt_counter_alloc)); + + /* allocate hw counters */ + counter->hw_counter.start_id = 0; + counter->hw_counter.end_id = 0; + unused_cnt = 0; + unused_max = 0; + unused_start_id = 0; + if (counter->hw_counter.num_counters == 0) + goto sw_counter_alloc; + /* find the start id which can be used for the block */ + for (i = 0; i < IPA_FLT_RT_HW_COUNTER; i++) { + if (!ipa3_ctx->flt_rt_counters.used_hw[i]) + unused_cnt++; + else { + /* tracking max unused block in case allow less */ + if (unused_cnt > unused_max) { + unused_start_id = i - unused_cnt + 2; + unused_max = unused_cnt; + } + unused_cnt = 0; + } + /* find it, break and use this 1st possible block */ + if (unused_cnt == counter->hw_counter.num_counters) { + counter->hw_counter.start_id = i - unused_cnt + 2; + counter->hw_counter.end_id = i + 1; + break; + } + } + if (counter->hw_counter.start_id == 0) { + /* if not able to find such a block but allow less */ + if (counter->hw_counter.allow_less && unused_max) { + /* give the max possible unused blocks */ + counter->hw_counter.num_counters = unused_max; + counter->hw_counter.start_id = unused_start_id; + counter->hw_counter.end_id = + unused_start_id + unused_max - 1; + } else { + /* not able to find such a block */ + counter->hw_counter.num_counters = 0; + counter->hw_counter.start_id = 0; + counter->hw_counter.end_id = 0; + goto err; + } + } + +sw_counter_alloc: + /* allocate sw counters */ + counter->sw_counter.start_id = 0; + counter->sw_counter.end_id = 0; + unused_cnt = 0; + unused_max = 0; + unused_start_id = 0; + if (counter->sw_counter.num_counters == 0) + goto mark_hw_cnt; + /* find the start id which can be used for the block */ + for (i = 0; i < IPA_FLT_RT_SW_COUNTER; i++) { + if (!ipa3_ctx->flt_rt_counters.used_sw[i]) + unused_cnt++; + else { + /* tracking max unused block in case allow less */ + if (unused_cnt > unused_max) { + unused_start_id = i - unused_cnt + + 2 + IPA_FLT_RT_HW_COUNTER; + unused_max = unused_cnt; + } + unused_cnt = 0; + } + /* find it, break and use this 1st possible block */ + if (unused_cnt == counter->sw_counter.num_counters) { + counter->sw_counter.start_id = i - unused_cnt + + 2 + IPA_FLT_RT_HW_COUNTER; + counter->sw_counter.end_id = + i + 1 + IPA_FLT_RT_HW_COUNTER; + break; + } + } + if (counter->sw_counter.start_id == 0) { + /* if not able to find such a block but allow less */ + if (counter->sw_counter.allow_less && unused_max) { + /* give the max possible unused blocks */ + counter->sw_counter.num_counters = unused_max; + counter->sw_counter.start_id = unused_start_id; + counter->sw_counter.end_id = + unused_start_id + unused_max - 1; + } else { + /* not able to find such a block */ + counter->sw_counter.num_counters = 0; + counter->sw_counter.start_id = 0; + counter->sw_counter.end_id = 0; + goto err; + } + } + +mark_hw_cnt: + /* add hw counters, set used to 1 */ + if (counter->hw_counter.num_counters == 0) + goto mark_sw_cnt; + unused_start_id = counter->hw_counter.start_id; + if (unused_start_id < 1 || + unused_start_id > IPA_FLT_RT_HW_COUNTER) { + IPAERR_RL("unexpected hw_counter start id %d\n", + unused_start_id); + goto err; + } + for (i = 0; i < counter->hw_counter.num_counters; i++) + ipa3_ctx->flt_rt_counters.used_hw[unused_start_id + i - 1] + = true; +mark_sw_cnt: + /* add sw counters, set used to 1 */ + if (counter->sw_counter.num_counters == 0) + goto done; + unused_start_id = counter->sw_counter.start_id + - IPA_FLT_RT_HW_COUNTER; + if (unused_start_id < 1 || + unused_start_id > IPA_FLT_RT_SW_COUNTER) { + IPAERR_RL("unexpected sw_counter start id %d\n", + unused_start_id); + goto err; + } + for (i = 0; i < counter->sw_counter.num_counters; i++) + ipa3_ctx->flt_rt_counters.used_sw[unused_start_id + i - 1] + = true; +done: + /* get a handle from idr for dealloc */ + counter->hdl = __ipa3_alloc_counter_hdl(counter); + memcpy(header, counter, sizeof(struct ipa_ioc_flt_rt_counter_alloc)); + spin_unlock(&ipa3_ctx->flt_rt_counters.hdl_lock); + idr_preload_end(); + return 0; + +err: + counter->hdl = -1; + kmem_cache_free(ipa3_ctx->fnr_stats_cache, counter); + spin_unlock(&ipa3_ctx->flt_rt_counters.hdl_lock); + idr_preload_end(); + return -ENOMEM; +} + +void ipa3_counter_remove_hdl(int hdl) +{ + struct ipa_ioc_flt_rt_counter_alloc *counter; + int offset = 0; + + spin_lock(&ipa3_ctx->flt_rt_counters.hdl_lock); + counter = idr_find(&ipa3_ctx->flt_rt_counters.hdl, hdl); + if (counter == NULL) { + IPAERR_RL("unexpected hdl %d\n", hdl); + goto err; + } + /* remove counters belong to this hdl, set used back to 0 */ + offset = counter->hw_counter.start_id - 1; + if (offset >= 0 && (offset + counter->hw_counter.num_counters) + < IPA_FLT_RT_HW_COUNTER) { + memset(&ipa3_ctx->flt_rt_counters.used_hw[offset], + 0, counter->hw_counter.num_counters * sizeof(bool)); + } else { + IPAERR_RL("unexpected hdl %d\n", hdl); + goto err; + } + offset = counter->sw_counter.start_id - 1 - IPA_FLT_RT_HW_COUNTER; + if (offset >= 0 && (offset + counter->sw_counter.num_counters) + < IPA_FLT_RT_SW_COUNTER) { + memset(&ipa3_ctx->flt_rt_counters.used_sw[offset], + 0, counter->sw_counter.num_counters * sizeof(bool)); + } else { + IPAERR_RL("unexpected hdl %d\n", hdl); + goto err; + } + /* remove the handle */ + idr_remove(&ipa3_ctx->flt_rt_counters.hdl, hdl); + kmem_cache_free(ipa3_ctx->fnr_stats_cache, counter); +err: + spin_unlock(&ipa3_ctx->flt_rt_counters.hdl_lock); +} + +void ipa3_counter_id_remove_all(void) +{ + struct ipa_ioc_flt_rt_counter_alloc *counter; + int hdl; + + spin_lock(&ipa3_ctx->flt_rt_counters.hdl_lock); + /* remove all counters, set used back to 0 */ + memset(&ipa3_ctx->flt_rt_counters.used_hw, 0, + sizeof(ipa3_ctx->flt_rt_counters.used_hw)); + memset(&ipa3_ctx->flt_rt_counters.used_sw, 0, + sizeof(ipa3_ctx->flt_rt_counters.used_sw)); + /* remove all handles */ + idr_for_each_entry(&ipa3_ctx->flt_rt_counters.hdl, counter, hdl) { + idr_remove(&ipa3_ctx->flt_rt_counters.hdl, hdl); + kmem_cache_free(ipa3_ctx->fnr_stats_cache, counter); + } + spin_unlock(&ipa3_ctx->flt_rt_counters.hdl_lock); +} + +int ipa3_id_alloc(void *ptr) +{ + int id; + + idr_preload(GFP_KERNEL); + spin_lock(&ipa3_ctx->idr_lock); + id = idr_alloc(&ipa3_ctx->ipa_idr, ptr, 0, 0, GFP_NOWAIT); + spin_unlock(&ipa3_ctx->idr_lock); + idr_preload_end(); + + return id; +} + +void *ipa3_id_find(u32 id) +{ + void *ptr; + + spin_lock(&ipa3_ctx->idr_lock); + ptr = idr_find(&ipa3_ctx->ipa_idr, id); + spin_unlock(&ipa3_ctx->idr_lock); + + return ptr; +} + +bool ipa3_check_idr_if_freed(void *ptr) +{ + int id; + void *iter_ptr; + + spin_lock(&ipa3_ctx->idr_lock); + idr_for_each_entry(&ipa3_ctx->ipa_idr, iter_ptr, id) { + if ((uintptr_t)ptr == (uintptr_t)iter_ptr) { + spin_unlock(&ipa3_ctx->idr_lock); + return false; + } + } + spin_unlock(&ipa3_ctx->idr_lock); + return true; +} + +void ipa3_id_remove(u32 id) +{ + spin_lock(&ipa3_ctx->idr_lock); + idr_remove(&ipa3_ctx->ipa_idr, id); + spin_unlock(&ipa3_ctx->idr_lock); +} + +void ipa3_tag_destroy_imm(void *user1, int user2) +{ + ipahal_destroy_imm_cmd(user1); +} + +static void ipa3_tag_free_skb(void *user1, int user2) +{ + dev_kfree_skb_any((struct sk_buff *)user1); +} + +#define REQUIRED_TAG_PROCESS_DESCRIPTORS 4 +#define MAX_RETRY_ALLOC 10 +#define ALLOC_MIN_SLEEP_RX 100000 +#define ALLOC_MAX_SLEEP_RX 200000 + +/* ipa3_tag_process() - Initiates a tag process. Incorporates the input + * descriptors + * + * @desc: descriptors with commands for IC + * @desc_size: amount of descriptors in the above variable + * + * Note: The descriptors are copied (if there's room), the client needs to + * free his descriptors afterwards + * + * Return: 0 or negative in case of failure + */ +int ipa3_tag_process(struct ipa3_desc desc[], + int descs_num, + unsigned long timeout) +{ + struct ipa3_sys_context *sys; + struct ipa3_desc *tag_desc; + int desc_idx = 0; + struct ipahal_imm_cmd_ip_packet_init pktinit_cmd; + struct ipahal_imm_cmd_pyld *cmd_pyld = NULL; + struct ipahal_imm_cmd_ip_packet_tag_status status; + int i; + struct sk_buff *dummy_skb; + int res = 0; + struct ipa3_tag_completion *comp; + int ep_idx; + u32 retry_cnt = 0; + struct ipahal_reg_valmask valmask; + struct ipahal_imm_cmd_register_write reg_write_coal_close; + struct ipahal_imm_cmd_register_read dummy_reg_read; + int req_num_tag_desc = REQUIRED_TAG_PROCESS_DESCRIPTORS; + struct ipa_mem_buffer cmd; + u32 offset = 0; + + memset(&cmd, 0, sizeof(struct ipa_mem_buffer)); + /** + * We use a descriptor for closing coalsceing endpoint + * by immediate command. So, REQUIRED_TAG_PROCESS_DESCRIPTORS + * should be incremented by 1 to overcome buffer overflow. + */ + if (ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS) != -1) + req_num_tag_desc += 1; + + /* Not enough room for the required descriptors for the tag process */ + if (IPA_TAG_MAX_DESC - descs_num < req_num_tag_desc) { + IPAERR("up to %d descriptors are allowed (received %d)\n", + IPA_TAG_MAX_DESC - req_num_tag_desc, + descs_num); + return -ENOMEM; + } + + ep_idx = ipa_get_ep_mapping(IPA_CLIENT_APPS_CMD_PROD); + if (-1 == ep_idx) { + IPAERR("Client %u is not mapped\n", + IPA_CLIENT_APPS_CMD_PROD); + return -EFAULT; + } + sys = ipa3_ctx->ep[ep_idx].sys; + + tag_desc = kzalloc(sizeof(*tag_desc) * IPA_TAG_MAX_DESC, GFP_KERNEL); + if (!tag_desc) { + IPAERR("failed to allocate memory\n"); + return -ENOMEM; + } + + /* Copy the required descriptors from the client now */ + if (desc) { + memcpy(&(tag_desc[0]), desc, descs_num * + sizeof(tag_desc[0])); + desc_idx += descs_num; + } else { + res = -EFAULT; + IPAERR("desc is NULL\n"); + goto fail_free_tag_desc; + } + + /* IC to close the coal frame before HPS Clear if coal is enabled */ + if (ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS) != -1) { + ep_idx = ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS); + reg_write_coal_close.skip_pipeline_clear = false; + if (ipa3_ctx->ulso_wa) { + reg_write_coal_close.pipeline_clear_options = IPAHAL_SRC_GRP_CLEAR; + } else { + reg_write_coal_close.pipeline_clear_options = IPAHAL_HPS_CLEAR; + } + if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0) + offset = ipahal_get_reg_ofst( + IPA_AGGR_FORCE_CLOSE); + else + offset = ipahal_get_ep_reg_offset( + IPA_AGGR_FORCE_CLOSE_n, ep_idx); + reg_write_coal_close.offset = offset; + ipahal_get_aggr_force_close_valmask(ep_idx, &valmask); + reg_write_coal_close.value = valmask.val; + reg_write_coal_close.value_mask = valmask.mask; + cmd_pyld = ipahal_construct_imm_cmd( + IPA_IMM_CMD_REGISTER_WRITE, + ®_write_coal_close, false); + if (!cmd_pyld) { + IPAERR("failed to construct coal close IC\n"); + res = -ENOMEM; + goto fail_free_tag_desc; + } + ipa3_init_imm_cmd_desc(&tag_desc[desc_idx], cmd_pyld); + tag_desc[desc_idx].callback = ipa3_tag_destroy_imm; + tag_desc[desc_idx].user1 = cmd_pyld; + ++desc_idx; + } + if (ipa3_ctx->ulso_wa) { + /* dummary regsiter read IC with HPS clear*/ + cmd.size = 4; + cmd.base = dma_alloc_coherent(ipa3_ctx->pdev, cmd.size, + &cmd.phys_base, GFP_KERNEL); + if (cmd.base == NULL) { + res = -ENOMEM; + goto fail_free_desc; + } + offset = ipahal_get_reg_n_ofst(IPA_STAT_QUOTA_BASE_n, + ipa3_ctx->ee); + dummy_reg_read.skip_pipeline_clear = false; + dummy_reg_read.pipeline_clear_options = IPAHAL_HPS_CLEAR; + dummy_reg_read.offset = offset; + dummy_reg_read.sys_addr = cmd.phys_base; + cmd_pyld = ipahal_construct_imm_cmd( + IPA_IMM_CMD_REGISTER_READ, + &dummy_reg_read, false); + if (!cmd_pyld) { + IPAERR("failed to construct DUMMY READ IC\n"); + res = -ENOMEM; + goto fail_free_desc; + } + ipa3_init_imm_cmd_desc(&tag_desc[desc_idx], cmd_pyld); + tag_desc[desc_idx].callback = ipa3_tag_destroy_imm; + tag_desc[desc_idx].user1 = cmd_pyld; + ++desc_idx; + } + + /* NO-OP IC for ensuring that IPA pipeline is empty */ + if (!ipa3_ctx->ulso_wa) + { + cmd_pyld = ipahal_construct_nop_imm_cmd( + false, IPAHAL_FULL_PIPELINE_CLEAR, false); + if (!cmd_pyld) { + IPAERR("failed to construct NOP imm cmd\n"); + res = -ENOMEM; + goto fail_free_desc; + } + ipa3_init_imm_cmd_desc(&tag_desc[desc_idx], cmd_pyld); + tag_desc[desc_idx].callback = ipa3_tag_destroy_imm; + tag_desc[desc_idx].user1 = cmd_pyld; + ++desc_idx; + } + + /* IP_PACKET_INIT IC for tag status to be sent to apps */ + pktinit_cmd.destination_pipe_index = + ipa_get_ep_mapping(IPA_CLIENT_APPS_LAN_CONS); + cmd_pyld = ipahal_construct_imm_cmd( + IPA_IMM_CMD_IP_PACKET_INIT, &pktinit_cmd, false); + if (!cmd_pyld) { + IPAERR("failed to construct ip_packet_init imm cmd\n"); + res = -ENOMEM; + goto fail_free_desc; + } + ipa3_init_imm_cmd_desc(&tag_desc[desc_idx], cmd_pyld); + tag_desc[desc_idx].callback = ipa3_tag_destroy_imm; + tag_desc[desc_idx].user1 = cmd_pyld; + ++desc_idx; + + /* status IC */ + status.tag = IPA_COOKIE; + cmd_pyld = ipahal_construct_imm_cmd( + IPA_IMM_CMD_IP_PACKET_TAG_STATUS, &status, false); + if (!cmd_pyld) { + IPAERR("failed to construct ip_packet_tag_status imm cmd\n"); + res = -ENOMEM; + goto fail_free_desc; + } + ipa3_init_imm_cmd_desc(&tag_desc[desc_idx], cmd_pyld); + tag_desc[desc_idx].callback = ipa3_tag_destroy_imm; + tag_desc[desc_idx].user1 = cmd_pyld; + ++desc_idx; + + comp = kzalloc(sizeof(*comp), GFP_KERNEL); + if (!comp) { + IPAERR("no mem\n"); + res = -ENOMEM; + goto fail_free_desc; + } + init_completion(&comp->comp); + + /* completion needs to be released from both here and rx handler */ + atomic_set(&comp->cnt, 2); + + /* dummy packet to send to IPA. packet payload is a completion object */ + dummy_skb = alloc_skb(sizeof(comp), GFP_KERNEL); + if (!dummy_skb) { + IPAERR("failed to allocate memory\n"); + res = -ENOMEM; + goto fail_free_comp; + } + + memcpy(skb_put(dummy_skb, sizeof(comp)), &comp, sizeof(comp)); + + if (desc_idx >= IPA_TAG_MAX_DESC) { + IPAERR("number of commands is out of range\n"); + res = -ENOBUFS; + goto fail_free_skb; + } + + tag_desc[desc_idx].pyld = dummy_skb->data; + tag_desc[desc_idx].len = dummy_skb->len; + tag_desc[desc_idx].type = IPA_DATA_DESC_SKB; + tag_desc[desc_idx].callback = ipa3_tag_free_skb; + tag_desc[desc_idx].user1 = dummy_skb; + desc_idx++; +retry_alloc: + /* send all descriptors to IPA with single EOT */ + res = ipa3_send(sys, desc_idx, tag_desc, true); + if (res) { + if (res == -ENOMEM) { + if (retry_cnt < MAX_RETRY_ALLOC) { + IPADBG( + "failed to alloc memory retry cnt = %d\n", + retry_cnt); + retry_cnt++; + usleep_range(ALLOC_MIN_SLEEP_RX, + ALLOC_MAX_SLEEP_RX); + goto retry_alloc; + } + + } + IPAERR("failed to send TAG packets %d\n", res); + res = -ENOMEM; + goto fail_free_skb; + } + kfree(tag_desc); + tag_desc = NULL; + ipa3_ctx->tag_process_before_gating = false; + + IPADBG("waiting for TAG response\n"); + res = wait_for_completion_timeout(&comp->comp, timeout); + if (res == 0) { + IPAERR("timeout (%lu msec) on waiting for TAG response\n", + timeout); + WARN_ON(1); + if (atomic_dec_return(&comp->cnt) == 0) + kfree(comp); + if (cmd.base) { + dma_free_coherent(ipa3_ctx->pdev, cmd.size, + cmd.base, cmd.phys_base); + } + return -ETIME; + } + + IPADBG("TAG response arrived!\n"); + if (atomic_dec_return(&comp->cnt) == 0) + kfree(comp); + + if (cmd.base) { + dma_free_coherent(ipa3_ctx->pdev, cmd.size, + cmd.base, cmd.phys_base); + } + + /* + * sleep for short period to ensure IPA wrote all packets to + * the transport + */ + usleep_range(IPA_TAG_SLEEP_MIN_USEC, IPA_TAG_SLEEP_MAX_USEC); + + return 0; + +fail_free_skb: + kfree_skb(dummy_skb); +fail_free_comp: + kfree(comp); +fail_free_desc: + /* + * Free only the first descriptors allocated here. + * [nop, pkt_init, status, dummy_skb] + * The user is responsible to free his allocations + * in case of failure. + * The min is required because we may fail during + * of the initial allocations above + */ + for (i = descs_num; + i < min(req_num_tag_desc, desc_idx); i++) + if (tag_desc[i].callback) + tag_desc[i].callback(tag_desc[i].user1, + tag_desc[i].user2); + if (cmd.base) { + dma_free_coherent(ipa3_ctx->pdev, cmd.size, + cmd.base, cmd.phys_base); + } +fail_free_tag_desc: + kfree(tag_desc); + return res; +} + +/** + * ipa3_tag_generate_force_close_desc() - generate descriptors for force close + * immediate command + * + * @desc: descriptors for IC + * @desc_size: desc array size + * @start_pipe: first pipe to close aggregation + * @end_pipe: last (non-inclusive) pipe to close aggregation + * + * Return: number of descriptors written or negative in case of failure + */ +static int ipa3_tag_generate_force_close_desc(struct ipa3_desc desc[], + int desc_size, int start_pipe, int end_pipe) +{ + int i; + struct ipa_ep_cfg_aggr ep_aggr; + int desc_idx = 0; + int res; + struct ipahal_imm_cmd_register_write reg_write_agg_close; + struct ipahal_imm_cmd_pyld *cmd_pyld; + struct ipahal_reg_valmask valmask; + u32 offset = 0; + + for (i = start_pipe; i < end_pipe; i++) { + ipahal_read_reg_n_fields(IPA_ENDP_INIT_AGGR_n, i, &ep_aggr); + if (!ep_aggr.aggr_en) + continue; + /* Skip Coalescing pipe when ulso wa is enabled. */ + if (ipa3_ctx->ulso_wa && + (i == ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS))) + continue; + IPADBG("Force close ep: %d\n", i); + if (desc_idx + 1 > desc_size) { + IPAERR("Internal error - no descriptors\n"); + res = -EFAULT; + goto fail_no_desc; + } + + if (!ipa3_ctx->ulso_wa) { + reg_write_agg_close.skip_pipeline_clear = false; + reg_write_agg_close.pipeline_clear_options = + IPAHAL_FULL_PIPELINE_CLEAR; + } else { + reg_write_agg_close.skip_pipeline_clear = true; + } + + if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0) + offset = ipahal_get_reg_ofst( + IPA_AGGR_FORCE_CLOSE); + else + offset = ipahal_get_ep_reg_offset( + IPA_AGGR_FORCE_CLOSE_n, i); + reg_write_agg_close.offset = offset; + ipahal_get_aggr_force_close_valmask(i, &valmask); + reg_write_agg_close.value = valmask.val; + reg_write_agg_close.value_mask = valmask.mask; + cmd_pyld = ipahal_construct_imm_cmd(IPA_IMM_CMD_REGISTER_WRITE, + ®_write_agg_close, false); + if (!cmd_pyld) { + IPAERR("failed to construct register_write imm cmd\n"); + res = -ENOMEM; + goto fail_alloc_reg_write_agg_close; + } + + ipa3_init_imm_cmd_desc(&desc[desc_idx], cmd_pyld); + desc[desc_idx].callback = ipa3_tag_destroy_imm; + desc[desc_idx].user1 = cmd_pyld; + ++desc_idx; + } + + return desc_idx; + +fail_alloc_reg_write_agg_close: + for (i = 0; i < desc_idx; ++i) + if (desc[desc_idx].callback) + desc[desc_idx].callback(desc[desc_idx].user1, + desc[desc_idx].user2); +fail_no_desc: + return res; +} + +/** + * ipa3_tag_aggr_force_close() - Force close aggregation + * + * @pipe_num: pipe number or -1 for all pipes + */ +int ipa3_tag_aggr_force_close(int pipe_num) +{ + struct ipa3_desc *desc; + int res = -1; + int start_pipe; + int end_pipe; + int num_descs; + int num_aggr_descs; + + if (pipe_num < -1 || pipe_num >= (int)ipa3_ctx->ipa_num_pipes) { + IPAERR("Invalid pipe number %d\n", pipe_num); + return -EINVAL; + } + + if (pipe_num == -1) { + start_pipe = 0; + end_pipe = ipa3_ctx->ipa_num_pipes; + } else { + start_pipe = pipe_num; + end_pipe = pipe_num + 1; + } + + num_descs = end_pipe - start_pipe; + + desc = kcalloc(num_descs, sizeof(*desc), GFP_KERNEL); + if (!desc) { + IPAERR("no mem\n"); + return -ENOMEM; + } + + /* Force close aggregation on all valid pipes with aggregation */ + num_aggr_descs = ipa3_tag_generate_force_close_desc(desc, num_descs, + start_pipe, end_pipe); + if (num_aggr_descs < 0) { + IPAERR("ipa3_tag_generate_force_close_desc failed %d\n", + num_aggr_descs); + goto fail_free_desc; + } + + res = ipa3_tag_process(desc, num_aggr_descs, + IPA_FORCE_CLOSE_TAG_PROCESS_TIMEOUT); + +fail_free_desc: + kfree(desc); + + return res; +} + +/** + * ipa_is_ready() - check if IPA module was initialized + * successfully + * + * Return value: true for yes; false for no + */ +bool ipa_is_ready(void) +{ + bool complete; + + if (ipa3_ctx == NULL) + return false; + mutex_lock(&ipa3_ctx->lock); + complete = ipa3_ctx->ipa_initialization_complete; + mutex_unlock(&ipa3_ctx->lock); + return complete; +} +EXPORT_SYMBOL(ipa_is_ready); + +/** + * ipa3_is_client_handle_valid() - check if IPA client handle is valid handle + * + * Return value: true for yes; false for no + */ +bool ipa3_is_client_handle_valid(u32 clnt_hdl) +{ + if (clnt_hdl >= 0 && clnt_hdl < ipa3_ctx->ipa_num_pipes) + return true; + return false; +} +EXPORT_SYMBOL(ipa3_is_client_handle_valid); + +/** + * ipa3_proxy_clk_unvote() - called to remove IPA clock proxy vote + * + * Return value: none + */ +void ipa3_proxy_clk_unvote(void) +{ + if (ipa3_ctx == NULL) + return; + mutex_lock(&ipa3_ctx->q6_proxy_clk_vote_mutex); + if (ipa3_ctx->q6_proxy_clk_vote_valid) { + IPA_ACTIVE_CLIENTS_DEC_SPECIAL("PROXY_CLK_VOTE"); + ipa3_ctx->q6_proxy_clk_vote_cnt--; + if (ipa3_ctx->q6_proxy_clk_vote_cnt == 0) + ipa3_ctx->q6_proxy_clk_vote_valid = false; + } + mutex_unlock(&ipa3_ctx->q6_proxy_clk_vote_mutex); +} + +/** + * ipa3_proxy_clk_vote() - called to add IPA clock proxy vote + * + * Return value: none + */ +void ipa3_proxy_clk_vote(bool is_ssr) +{ + if (ipa3_ctx == NULL) + return; + + /* Avoid duplicate votes in case we are in SSR even before uC is loaded. */ + if (is_ssr && !ipa3_uc_loaded_check()) { + IPADBG("Dup proxy vote. Ignore as uC is not yet loaded\n"); + return; + } + mutex_lock(&ipa3_ctx->q6_proxy_clk_vote_mutex); + if (!ipa3_ctx->q6_proxy_clk_vote_valid || + (ipa3_ctx->q6_proxy_clk_vote_cnt > 0)) { + IPA_ACTIVE_CLIENTS_INC_SPECIAL("PROXY_CLK_VOTE"); + ipa3_ctx->q6_proxy_clk_vote_cnt++; + ipa3_ctx->q6_proxy_clk_vote_valid = true; + } + mutex_unlock(&ipa3_ctx->q6_proxy_clk_vote_mutex); +} +EXPORT_SYMBOL(ipa3_proxy_clk_vote); + +/** + * ipa3_get_smem_restr_bytes()- Return IPA smem restricted bytes + * + * Return value: u16 - number of IPA smem restricted bytes + */ +u16 ipa3_get_smem_restr_bytes(void) +{ + if (ipa3_ctx) + return ipa3_ctx->smem_restricted_bytes; + + IPAERR("IPA Driver not initialized\n"); + + return 0; +} + +/** + * ipa3_get_modem_cfg_emb_pipe_flt()- Return ipa3_ctx->modem_cfg_emb_pipe_flt + * + * Return value: true if modem configures embedded pipe flt, false otherwise + */ +bool ipa3_get_modem_cfg_emb_pipe_flt(void) +{ + if (ipa3_ctx) + return ipa3_ctx->modem_cfg_emb_pipe_flt; + + IPAERR("IPA driver has not been initialized\n"); + + return false; +} + +/** + * ipa3_get_transport_type() + * + * Return value: enum ipa_transport_type + */ +enum ipa_transport_type ipa3_get_transport_type(void) +{ + return IPA_TRANSPORT_TYPE_GSI; +} +EXPORT_SYMBOL(ipa3_get_transport_type); + +/** + * ipa3_get_max_num_pipes() + * + * Return value: maximal possible pipes num per hw_ver (not necessarily the + * actual pipes num) + */ +u32 ipa3_get_max_num_pipes(void) +{ + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0) + return IPA5_PIPES_NUM; + else + return IPA3_MAX_NUM_PIPES; +} + +u32 ipa3_get_num_pipes(void) +{ + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0) { + struct ipahal_ipa_flavor_0 ipa_flavor; + + ipahal_read_reg_fields(IPA_FLAVOR_0, &ipa_flavor); + return ipa_flavor.ipa_pipes; + } + return ipahal_read_reg(IPA_ENABLED_PIPES); +} + +/** + * ipa3_disable_apps_wan_cons_deaggr()- + * set ipa3_ctx->ipa_client_apps_wan_cons_agg_gro + * + * Return value: 0 or negative in case of failure + */ +int ipa3_disable_apps_wan_cons_deaggr(uint32_t agg_size, uint32_t agg_count) +{ + int res = -1; + + /* ipahal will adjust limits based on HW capabilities */ + + if (ipa3_ctx) { + ipa3_ctx->ipa_client_apps_wan_cons_agg_gro = true; + return 0; + } + return res; +} + +void *ipa3_get_ipc_logbuf(void) +{ + if (ipa3_ctx) + return ipa3_ctx->logbuf; + + return NULL; +} +EXPORT_SYMBOL(ipa3_get_ipc_logbuf); + +void *ipa3_get_ipc_logbuf_low(void) +{ + if (ipa3_ctx) + return ipa3_ctx->logbuf_low; + + return NULL; +} +EXPORT_SYMBOL(ipa3_get_ipc_logbuf_low); + +void ipa3_get_holb(int ep_idx, struct ipa_ep_cfg_holb *holb) +{ + *holb = ipa3_ctx->ep[ep_idx].holb; +} + +void ipa3_set_tag_process_before_gating(bool val) +{ + ipa3_ctx->tag_process_before_gating = val; +} +EXPORT_SYMBOL(ipa3_set_tag_process_before_gating); + +/** + * ipa_is_vlan_mode - check if a LAN driver should load in VLAN mode + * @iface - type of vlan capable device + * @res - query result: true for vlan mode, false for non vlan mode + * + * API must be called after ipa_is_ready() returns true, otherwise it will fail + * + * Returns: 0 on success, negative on failure + */ +int ipa_is_vlan_mode(enum ipa_vlan_ifaces iface, bool *res) +{ + if (!res) { + IPAERR("NULL out param\n"); + return -EINVAL; + } + + if (iface < 0 || iface >= IPA_VLAN_IF_MAX) { + IPAERR("invalid iface %d\n", iface); + return -EINVAL; + } + + if (!ipa_is_ready()) { + IPAERR("IPA is not ready yet\n"); + return -ENODEV; + } + + *res = ipa3_ctx->vlan_mode_iface[iface]; + + IPADBG("Driver %d vlan mode is %d\n", iface, *res); + return 0; +} +EXPORT_SYMBOL(ipa_is_vlan_mode); + +/** + * ipa_is_modem_pipe()- Checks if pipe is owned by the modem + * + * @pipe_idx: pipe number + * Return value: true if owned by modem, false otherwize + */ +bool ipa_is_modem_pipe(int pipe_idx) +{ + int client_idx; + + if (pipe_idx >= ipa3_ctx->ipa_num_pipes || pipe_idx < 0) { + IPAERR("Bad pipe index!\n"); + return false; + } + + for (client_idx = 0; client_idx < IPA_CLIENT_MAX; client_idx++) { + if (!IPA_CLIENT_IS_Q6_CONS(client_idx) && + !IPA_CLIENT_IS_Q6_PROD(client_idx)) + continue; + if (ipa_get_ep_mapping(client_idx) == pipe_idx) + return true; + } + + return false; +} + +static void ipa3_write_rsrc_grp_type_reg(int group_index, + enum ipa_rsrc_grp_type_src n, bool src, + struct ipahal_reg_rsrc_grp_xy_cfg *val) +{ + u8 hw_type_idx; + + hw_type_idx = ipa3_ctx->hw_type_index; + + switch (hw_type_idx) { + case IPA_3_0: + if (src) { + switch (group_index) { + case IPA_v3_0_GROUP_UL: + case IPA_v3_0_GROUP_DL: + ipahal_write_reg_n_fields( + IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n, + n, val); + break; + case IPA_v3_0_GROUP_DIAG: + case IPA_v3_0_GROUP_DMA: + ipahal_write_reg_n_fields( + IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n, + n, val); + break; + case IPA_v3_0_GROUP_Q6ZIP: + case IPA_v3_0_GROUP_UC_RX_Q: + ipahal_write_reg_n_fields( + IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n, + n, val); + break; + default: + IPAERR( + " Invalid source resource group,index #%d\n", + group_index); + break; + } + } else { + switch (group_index) { + case IPA_v3_0_GROUP_UL: + case IPA_v3_0_GROUP_DL: + ipahal_write_reg_n_fields( + IPA_DST_RSRC_GRP_01_RSRC_TYPE_n, + n, val); + break; + case IPA_v3_0_GROUP_DIAG: + case IPA_v3_0_GROUP_DMA: + ipahal_write_reg_n_fields( + IPA_DST_RSRC_GRP_23_RSRC_TYPE_n, + n, val); + break; + case IPA_v3_0_GROUP_Q6ZIP_GENERAL: + case IPA_v3_0_GROUP_Q6ZIP_ENGINE: + ipahal_write_reg_n_fields( + IPA_DST_RSRC_GRP_45_RSRC_TYPE_n, + n, val); + break; + default: + IPAERR( + " Invalid destination resource group,index #%d\n", + group_index); + break; + } + } + break; + case IPA_3_5: + case IPA_3_5_MHI: + case IPA_3_5_1: + if (src) { + switch (group_index) { + case IPA_v3_5_GROUP_LWA_DL: + case IPA_v3_5_GROUP_UL_DL: + ipahal_write_reg_n_fields( + IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n, + n, val); + break; + case IPA_v3_5_MHI_GROUP_DMA: + case IPA_v3_5_GROUP_UC_RX_Q: + ipahal_write_reg_n_fields( + IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n, + n, val); + break; + default: + IPAERR( + " Invalid source resource group,index #%d\n", + group_index); + break; + } + } else { + switch (group_index) { + case IPA_v3_5_GROUP_LWA_DL: + case IPA_v3_5_GROUP_UL_DL: + ipahal_write_reg_n_fields( + IPA_DST_RSRC_GRP_01_RSRC_TYPE_n, + n, val); + break; + case IPA_v3_5_MHI_GROUP_DMA: + ipahal_write_reg_n_fields( + IPA_DST_RSRC_GRP_23_RSRC_TYPE_n, + n, val); + break; + default: + IPAERR( + " Invalid destination resource group,index #%d\n", + group_index); + break; + } + } + break; + case IPA_4_0: + case IPA_4_0_MHI: + case IPA_4_1: + if (src) { + switch (group_index) { + case IPA_v4_0_GROUP_LWA_DL: + fallthrough; + case IPA_v4_0_GROUP_UL_DL: + ipahal_write_reg_n_fields( + IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n, + n, val); + break; + case IPA_v4_0_MHI_GROUP_DMA: + fallthrough; + case IPA_v4_0_GROUP_UC_RX_Q: + ipahal_write_reg_n_fields( + IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n, + n, val); + break; + default: + IPAERR( + " Invalid source resource group,index #%d\n", + group_index); + break; + } + } else { + switch (group_index) { + case IPA_v4_0_GROUP_LWA_DL: + fallthrough; + case IPA_v4_0_GROUP_UL_DL: + ipahal_write_reg_n_fields( + IPA_DST_RSRC_GRP_01_RSRC_TYPE_n, + n, val); + break; + case IPA_v4_0_MHI_GROUP_DMA: + ipahal_write_reg_n_fields( + IPA_DST_RSRC_GRP_23_RSRC_TYPE_n, + n, val); + break; + default: + IPAERR( + " Invalid destination resource group,index #%d\n", + group_index); + break; + } + } + break; + case IPA_4_2: + if (src) { + switch (group_index) { + case IPA_v4_2_GROUP_UL_DL: + ipahal_write_reg_n_fields( + IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n, + n, val); + break; + default: + IPAERR( + " Invalid source resource group,index #%d\n", + group_index); + break; + } + } else { + switch (group_index) { + case IPA_v4_2_GROUP_UL_DL: + ipahal_write_reg_n_fields( + IPA_DST_RSRC_GRP_01_RSRC_TYPE_n, + n, val); + break; + default: + IPAERR( + " Invalid destination resource group,index #%d\n", + group_index); + break; + } + } + break; + case IPA_4_5: + case IPA_4_5_MHI: + case IPA_4_5_APQ: + case IPA_4_5_AUTO: + case IPA_4_5_AUTO_MHI: + if (src) { + switch (group_index) { + case IPA_v4_5_MHI_GROUP_PCIE: + case IPA_v4_5_GROUP_UL_DL: + ipahal_write_reg_n_fields( + IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n, + n, val); + break; + case IPA_v4_5_MHI_GROUP_DMA: + case IPA_v4_5_MHI_GROUP_QDSS: + ipahal_write_reg_n_fields( + IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n, + n, val); + break; + case IPA_v4_5_GROUP_UC_RX_Q: + ipahal_write_reg_n_fields( + IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n, + n, val); + break; + default: + IPAERR( + " Invalid source resource group,index #%d\n", + group_index); + break; + } + } else { + switch (group_index) { + case IPA_v4_5_MHI_GROUP_PCIE: + case IPA_v4_5_GROUP_UL_DL: + ipahal_write_reg_n_fields( + IPA_DST_RSRC_GRP_01_RSRC_TYPE_n, + n, val); + break; + case IPA_v4_5_MHI_GROUP_DMA: + case IPA_v4_5_MHI_GROUP_QDSS: + ipahal_write_reg_n_fields( + IPA_DST_RSRC_GRP_23_RSRC_TYPE_n, + n, val); + break; + case IPA_v4_5_GROUP_UC_RX_Q: + ipahal_write_reg_n_fields( + IPA_DST_RSRC_GRP_45_RSRC_TYPE_n, + n, val); + break; + default: + IPAERR( + " Invalid destination resource group,index #%d\n", + group_index); + break; + } + } + break; + case IPA_4_7: + if (src) { + switch (group_index) { + case IPA_v4_7_GROUP_UL_DL: + ipahal_write_reg_n_fields( + IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n, + n, val); + break; + default: + IPAERR( + " Invalid source resource group,index #%d\n", + group_index); + break; + } + } else { + switch (group_index) { + case IPA_v4_7_GROUP_UL_DL: + ipahal_write_reg_n_fields( + IPA_DST_RSRC_GRP_01_RSRC_TYPE_n, + n, val); + break; + default: + IPAERR( + " Invalid destination resource group,index #%d\n", + group_index); + break; + } + } + break; + case IPA_4_9: + if (src) { + switch (group_index) { + case IPA_v4_9_GROUP_UL_DL: + case IPA_v4_9_GROUP_DMA: + ipahal_write_reg_n_fields( + IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n, + n, val); + break; + case IPA_v4_9_GROUP_UC_RX: + ipahal_write_reg_n_fields( + IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n, + n, val); + break; + default: + IPAERR( + " Invalid source resource group,index #%d\n", + group_index); + break; + } + } else { + switch (group_index) { + case IPA_v4_9_GROUP_UL_DL: + case IPA_v4_9_GROUP_DMA: + ipahal_write_reg_n_fields( + IPA_DST_RSRC_GRP_01_RSRC_TYPE_n, + n, val); + break; + case IPA_v4_9_GROUP_UC_RX: + case IPA_v4_9_GROUP_DRB_IP: + ipahal_write_reg_n_fields( + IPA_DST_RSRC_GRP_23_RSRC_TYPE_n, + n, val); + break; + default: + IPAERR( + " Invalid destination resource group,index #%d\n", + group_index); + break; + } + } + break; + case IPA_4_11: + if (src) { + switch (group_index) { + case IPA_v4_11_GROUP_UL_DL: + ipahal_write_reg_n_fields( + IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n, + n, val); + break; + default: + IPAERR( + " Invalid source resource group,index #%d\n", + group_index); + break; + } + } else { + switch (group_index) { + case IPA_v4_11_GROUP_UL_DL: + ipahal_write_reg_n_fields( + IPA_DST_RSRC_GRP_01_RSRC_TYPE_n, + n, val); + break; + case IPA_v4_11_GROUP_DRB_IP: + ipahal_write_reg_n_fields( + IPA_DST_RSRC_GRP_23_RSRC_TYPE_n, + n, val); + break; + default: + IPAERR( + " Invalid destination resource group,index #%d\n", + group_index); + break; + } + } + break; + case IPA_5_0: + case IPA_5_0_MHI: + case IPA_5_1: + case IPA_5_1_APQ: + if (src) { + switch (group_index) { + case IPA_v5_0_GROUP_UL: + case IPA_v5_0_GROUP_DL: + ipahal_write_reg_n_fields( + IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n, + n, val); + break; + case IPA_v5_0_GROUP_DMA: + case IPA_v5_0_GROUP_QDSS: + ipahal_write_reg_n_fields( + IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n, + n, val); + break; + case IPA_v5_0_GROUP_URLLC: + case IPA_v5_0_GROUP_UC: + ipahal_write_reg_n_fields( + IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n, + n, val); + break; + default: + IPAERR( + " Invalid source resource group,index #%d\n", + group_index); + break; + } + } else { + switch (group_index) { + case IPA_v5_0_GROUP_UL: + case IPA_v5_0_GROUP_DL: + ipahal_write_reg_n_fields( + IPA_DST_RSRC_GRP_01_RSRC_TYPE_n, + n, val); + break; + case IPA_v5_0_GROUP_DMA: + case IPA_v5_0_GROUP_QDSS: + ipahal_write_reg_n_fields( + IPA_DST_RSRC_GRP_23_RSRC_TYPE_n, + n, val); + break; + case IPA_v5_0_GROUP_URLLC: + case IPA_v5_0_GROUP_UC: + ipahal_write_reg_n_fields( + IPA_DST_RSRC_GRP_45_RSRC_TYPE_n, + n, val); + break; + case IPA_v5_0_GROUP_DRB_IP: + ipahal_write_reg_n_fields( + IPA_DST_RSRC_GRP_67_RSRC_TYPE_n, + n, val); + break; + default: + IPAERR( + " Invalid destination resource group,index #%d\n", + group_index); + break; + } + } + break; + + case IPA_5_2: + if (src) { + switch (group_index) { + case IPA_v5_2_GROUP_UL: + case IPA_v5_2_GROUP_DL: + ipahal_write_reg_n_fields( + IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n, + n, val); + break; + case IPA_v5_2_GROUP_URLLC: + case IPA_v5_2_GROUP_DRB_IP: + ipahal_write_reg_n_fields( + IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n, + n, val); + break; + default: + IPAERR( + " Invalid source resource group,index #%d\n", + group_index); + break; + } + } else { + switch (group_index) { + case IPA_v5_2_GROUP_UL: + case IPA_v5_2_GROUP_DL: + ipahal_write_reg_n_fields( + IPA_DST_RSRC_GRP_01_RSRC_TYPE_n, + n, val); + break; + case IPA_v5_2_GROUP_URLLC: + case IPA_v5_2_GROUP_DRB_IP: + ipahal_write_reg_n_fields( + IPA_DST_RSRC_GRP_23_RSRC_TYPE_n, + n, val); + break; + default: + IPAERR( + " Invalid destination resource group,index #%d\n", + group_index); + break; + } + } + break; + + case IPA_5_5: + case IPA_5_5_XR: + if (src) { + switch (group_index) { + case IPA_v5_5_GROUP_UL: + case IPA_v5_5_GROUP_DL: + ipahal_write_reg_n_fields( + IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n, + n, val); + break; + case IPA_v5_5_GROUP_DMA: + case IPA_v5_5_GROUP_QDSS: + ipahal_write_reg_n_fields( + IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n, + n, val); + break; + case IPA_v5_5_GROUP_URLLC: + case IPA_v5_5_GROUP_UC: + ipahal_write_reg_n_fields( + IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n, + n, val); + break; + default: + IPAERR( + " Invalid source resource group,index #%d\n", + group_index); + break; + } + } else { + switch (group_index) { + case IPA_v5_5_GROUP_UL: + case IPA_v5_5_GROUP_DL: + ipahal_write_reg_n_fields( + IPA_DST_RSRC_GRP_01_RSRC_TYPE_n, + n, val); + break; + case IPA_v5_5_GROUP_DMA: + case IPA_v5_5_GROUP_QDSS: + ipahal_write_reg_n_fields( + IPA_DST_RSRC_GRP_23_RSRC_TYPE_n, + n, val); + break; + case IPA_v5_5_GROUP_URLLC: + case IPA_v5_5_GROUP_UC: + ipahal_write_reg_n_fields( + IPA_DST_RSRC_GRP_45_RSRC_TYPE_n, + n, val); + break; + case IPA_v5_5_GROUP_DRB_IP: + ipahal_write_reg_n_fields( + IPA_DST_RSRC_GRP_67_RSRC_TYPE_n, + n, val); + break; + default: + IPAERR( + " Invalid destination resource group,index #%d\n", + group_index); + break; + } + } + break; + + default: + IPAERR("invalid hw type\n"); + WARN_ON(1); + return; + } +} + +static void ipa3_configure_rx_hps_clients(int depth, + int max_clnt_in_depth, int base_index, bool min) +{ + int i; + struct ipahal_reg_rx_hps_clients val; + u8 hw_type_idx; + + hw_type_idx = ipa3_ctx->hw_type_index; + + for (i = 0 ; i < max_clnt_in_depth ; i++) { + if (min) + val.client_minmax[i] = + ipa3_rsrc_rx_grp_config + [hw_type_idx] + [IPA_RSRC_GRP_TYPE_RX_HPS_CMDQ] + [i + base_index].min; + else + val.client_minmax[i] = + ipa3_rsrc_rx_grp_config + [hw_type_idx] + [IPA_RSRC_GRP_TYPE_RX_HPS_CMDQ] + [i + base_index].max; + } + if (depth) { + ipahal_write_reg_fields(min ? IPA_RX_HPS_CLIENTS_MIN_DEPTH_1 : + IPA_RX_HPS_CLIENTS_MAX_DEPTH_1, + &val); + } else { + ipahal_write_reg_fields(min ? IPA_RX_HPS_CLIENTS_MIN_DEPTH_0 : + IPA_RX_HPS_CLIENTS_MAX_DEPTH_0, + &val); + } +} + +static void ipa3_configure_rx_hps_weight(void) +{ + struct ipahal_reg_rx_hps_weights val; + u8 hw_type_idx; + + hw_type_idx = ipa3_ctx->hw_type_index; + + val.hps_queue_weight_0 = + ipa3_rsrc_rx_grp_hps_weight_config + [hw_type_idx][IPA_RSRC_GRP_TYPE_RX_HPS_WEIGHT_CONFIG] + [0]; + val.hps_queue_weight_1 = + ipa3_rsrc_rx_grp_hps_weight_config + [hw_type_idx][IPA_RSRC_GRP_TYPE_RX_HPS_WEIGHT_CONFIG] + [1]; + val.hps_queue_weight_2 = + ipa3_rsrc_rx_grp_hps_weight_config + [hw_type_idx][IPA_RSRC_GRP_TYPE_RX_HPS_WEIGHT_CONFIG] + [2]; + val.hps_queue_weight_3 = + ipa3_rsrc_rx_grp_hps_weight_config + [hw_type_idx][IPA_RSRC_GRP_TYPE_RX_HPS_WEIGHT_CONFIG] + [3]; + + ipahal_write_reg_fields(IPA_HPS_FTCH_ARB_QUEUE_WEIGHT, &val); +} + +static void ipa3_configure_rx_hps(void) +{ + int rx_hps_max_clnt_in_depth0; + + IPADBG("Assign RX_HPS CMDQ rsrc groups min-max limits\n"); + + /* Starting IPA4.5 we have 5 RX_HPS_CMDQ */ + if (ipa3_ctx->ipa_hw_type < IPA_HW_v4_5) + rx_hps_max_clnt_in_depth0 = 4; + else + rx_hps_max_clnt_in_depth0 = 5; + + ipa3_configure_rx_hps_clients(0, rx_hps_max_clnt_in_depth0, 0, true); + ipa3_configure_rx_hps_clients(0, rx_hps_max_clnt_in_depth0, 0, false); + + /* + * IPA 3.0/3.1 uses 6 RX_HPS_CMDQ and needs depths1 for that + * which has two clients + */ + if (ipa3_ctx->ipa_hw_type <= IPA_HW_v3_1) { + ipa3_configure_rx_hps_clients(1, 2, rx_hps_max_clnt_in_depth0, + true); + ipa3_configure_rx_hps_clients(1, 2, rx_hps_max_clnt_in_depth0, + false); + } + + /* Starting IPA4.2 no support to HPS weight config */ + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v3_5 && + (ipa3_ctx->ipa_hw_type < IPA_HW_v4_2)) + ipa3_configure_rx_hps_weight(); +} + +void ipa3_set_resorce_groups_min_max_limits(void) +{ + int i; + int j; + int src_rsrc_type_max; + int dst_rsrc_type_max; + int src_grp_idx_max; + int dst_grp_idx_max; + struct ipahal_reg_rsrc_grp_xy_cfg val; + u8 hw_type_idx; + + IPADBG("ENTER\n"); + + hw_type_idx = ipa3_ctx->hw_type_index; + + switch (hw_type_idx) { + case IPA_3_0: + src_rsrc_type_max = IPA_v3_0_RSRC_GRP_TYPE_SRC_MAX; + dst_rsrc_type_max = IPA_v3_0_RSRC_GRP_TYPE_DST_MAX; + src_grp_idx_max = IPA_v3_0_GROUP_MAX; + dst_grp_idx_max = IPA_v3_0_GROUP_MAX; + break; + case IPA_3_5: + case IPA_3_5_MHI: + case IPA_3_5_1: + src_rsrc_type_max = IPA_v3_5_RSRC_GRP_TYPE_SRC_MAX; + dst_rsrc_type_max = IPA_v3_5_RSRC_GRP_TYPE_DST_MAX; + src_grp_idx_max = IPA_v3_5_SRC_GROUP_MAX; + dst_grp_idx_max = IPA_v3_5_DST_GROUP_MAX; + break; + case IPA_4_0: + case IPA_4_0_MHI: + case IPA_4_1: + src_rsrc_type_max = IPA_v4_0_RSRC_GRP_TYPE_SRC_MAX; + dst_rsrc_type_max = IPA_v4_0_RSRC_GRP_TYPE_DST_MAX; + src_grp_idx_max = IPA_v4_0_SRC_GROUP_MAX; + dst_grp_idx_max = IPA_v4_0_DST_GROUP_MAX; + break; + case IPA_4_2: + src_rsrc_type_max = IPA_v4_0_RSRC_GRP_TYPE_SRC_MAX; + dst_rsrc_type_max = IPA_v4_0_RSRC_GRP_TYPE_DST_MAX; + src_grp_idx_max = IPA_v4_2_SRC_GROUP_MAX; + dst_grp_idx_max = IPA_v4_2_DST_GROUP_MAX; + break; + case IPA_4_5: + case IPA_4_5_MHI: + case IPA_4_5_APQ: + src_rsrc_type_max = IPA_v4_0_RSRC_GRP_TYPE_SRC_MAX; + dst_rsrc_type_max = IPA_v4_0_RSRC_GRP_TYPE_DST_MAX; + src_grp_idx_max = IPA_v4_5_SRC_GROUP_MAX; + dst_grp_idx_max = IPA_v4_5_DST_GROUP_MAX; + break; + case IPA_4_5_AUTO: + case IPA_4_5_AUTO_MHI: + src_rsrc_type_max = IPA_v4_0_RSRC_GRP_TYPE_SRC_MAX; + dst_rsrc_type_max = IPA_v4_0_RSRC_GRP_TYPE_DST_MAX; + src_grp_idx_max = IPA_v4_5_SRC_GROUP_MAX; + dst_grp_idx_max = IPA_v4_5_DST_GROUP_MAX; + break; + case IPA_4_7: + src_rsrc_type_max = IPA_v4_0_RSRC_GRP_TYPE_SRC_MAX; + dst_rsrc_type_max = IPA_v4_0_RSRC_GRP_TYPE_DST_MAX; + src_grp_idx_max = IPA_v4_7_SRC_GROUP_MAX; + dst_grp_idx_max = IPA_v4_7_DST_GROUP_MAX; + break; + case IPA_4_9: + src_rsrc_type_max = IPA_v4_0_RSRC_GRP_TYPE_SRC_MAX; + dst_rsrc_type_max = IPA_v4_0_RSRC_GRP_TYPE_DST_MAX; + src_grp_idx_max = IPA_v4_9_SRC_GROUP_MAX; + dst_grp_idx_max = IPA_v4_9_DST_GROUP_MAX; + break; + case IPA_4_11: + src_rsrc_type_max = IPA_v4_0_RSRC_GRP_TYPE_SRC_MAX; + dst_rsrc_type_max = IPA_v4_0_RSRC_GRP_TYPE_DST_MAX; + src_grp_idx_max = IPA_v4_11_SRC_GROUP_MAX; + dst_grp_idx_max = IPA_v4_11_DST_GROUP_MAX; + break; + case IPA_5_0: + case IPA_5_0_MHI: + case IPA_5_1: + case IPA_5_1_APQ: + src_rsrc_type_max = IPA_v5_0_RSRC_GRP_TYPE_SRC_MAX; + dst_rsrc_type_max = IPA_v5_0_RSRC_GRP_TYPE_DST_MAX; + src_grp_idx_max = IPA_v5_0_SRC_GROUP_MAX; + dst_grp_idx_max = IPA_v5_0_DST_GROUP_MAX; + break; + case IPA_5_2: + src_rsrc_type_max = IPA_v5_0_RSRC_GRP_TYPE_SRC_MAX; + dst_rsrc_type_max = IPA_v5_0_RSRC_GRP_TYPE_DST_MAX; + src_grp_idx_max = IPA_v5_2_SRC_GROUP_MAX; + dst_grp_idx_max = IPA_v5_2_DST_GROUP_MAX; + break; + case IPA_5_5: + case IPA_5_5_XR: + src_rsrc_type_max = IPA_v5_0_RSRC_GRP_TYPE_SRC_MAX; + dst_rsrc_type_max = IPA_v5_0_RSRC_GRP_TYPE_DST_MAX; + src_grp_idx_max = IPA_v5_5_SRC_GROUP_MAX; + dst_grp_idx_max = IPA_v5_5_DST_GROUP_MAX; + break; + default: + IPAERR("invalid hw type index\n"); + WARN_ON(1); + return; + } + + IPADBG("Assign source rsrc groups min-max limits\n"); + for (i = 0; i < src_rsrc_type_max; i++) { + for (j = 0; j < src_grp_idx_max; j = j + 2) { + val.x_min = + ipa3_rsrc_src_grp_config[hw_type_idx][i][j].min; + val.x_max = + ipa3_rsrc_src_grp_config[hw_type_idx][i][j].max; + if ((j + 1) < IPA_GROUP_MAX) { + val.y_min = + ipa3_rsrc_src_grp_config[hw_type_idx][i][j + 1].min; + val.y_max = + ipa3_rsrc_src_grp_config[hw_type_idx][i][j + 1].max; + } + ipa3_write_rsrc_grp_type_reg(j, i, true, &val); + } + } + + IPADBG("Assign destination rsrc groups min-max limits\n"); + for (i = 0; i < dst_rsrc_type_max; i++) { + for (j = 0; j < dst_grp_idx_max; j = j + 2) { + val.x_min = + ipa3_rsrc_dst_grp_config[hw_type_idx][i][j].min; + val.x_max = + ipa3_rsrc_dst_grp_config[hw_type_idx][i][j].max; + if ((j + 1) < IPA_GROUP_MAX) { + val.y_min = + ipa3_rsrc_dst_grp_config[hw_type_idx][i][j + 1].min; + val.y_max = + ipa3_rsrc_dst_grp_config[hw_type_idx][i][j + 1].max; + } + ipa3_write_rsrc_grp_type_reg(j, i, false, &val); + } + } + + /* move rx_hps resource group configuration from HLOS to TZ + * on real platform with IPA 3.1 or later + */ + if (ipa3_ctx->ipa_hw_type < IPA_HW_v3_1 || + ipa3_ctx->ipa3_hw_mode == IPA_HW_MODE_VIRTUAL || + ipa3_ctx->ipa3_hw_mode == IPA_HW_MODE_EMULATION) { + ipa3_configure_rx_hps(); + } + + IPADBG("EXIT\n"); +} + +void ipa3_set_resorce_groups_config(void) +{ + struct ipahal_reg_rsrc_grp_cfg cfg; + struct ipahal_reg_rsrc_grp_cfg_ext cfg_ext; + + IPADBG("ENTER\n"); + + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0) { + cfg.src_grp_index = ipa_rsrc_config[ipa3_ctx->hw_type_index].src_grp_index; + cfg.src_grp_valid = ipa_rsrc_config[ipa3_ctx->hw_type_index].src_grp_valid; + cfg.dst_pipe_index = ipa_rsrc_config[ipa3_ctx->hw_type_index].dst_pipe_index; + cfg.dst_pipe_valid = ipa_rsrc_config[ipa3_ctx->hw_type_index].dst_pipe_valid; + cfg.dst_grp_index = ipa_rsrc_config[ipa3_ctx->hw_type_index].dst_grp_index; + cfg.src_grp_valid = ipa_rsrc_config[ipa3_ctx->hw_type_index].src_grp_valid; + cfg_ext.index = ipa_rsrc_config[ipa3_ctx->hw_type_index].src_grp_2nd_prio_index; + cfg_ext.valid = ipa_rsrc_config[ipa3_ctx->hw_type_index].src_grp_2nd_prio_valid; + + IPADBG("Write IPA_RSRC_GRP_CFG\n"); + ipahal_write_reg_fields(IPA_RSRC_GRP_CFG, &cfg); + IPADBG("Write IPA_RSRC_GRP_CFG_EXT\n"); + ipahal_write_reg_fields(IPA_RSRC_GRP_CFG_EXT, &cfg_ext); + } + IPADBG("EXIT\n"); +} + +static void ipa3_gsi_poll_after_suspend(struct ipa3_ep_context *ep) +{ + bool empty; + + IPADBG("switch ch %ld to poll\n", ep->gsi_chan_hdl); + gsi_config_channel_mode(ep->gsi_chan_hdl, GSI_CHAN_MODE_POLL); + gsi_is_channel_empty(ep->gsi_chan_hdl, &empty); + if (!empty) { + IPADBG("ch %ld not empty\n", ep->gsi_chan_hdl); + /* queue a work to start polling if don't have one */ + atomic_set(&ipa3_ctx->transport_pm.eot_activity, 1); + if (!atomic_read(&ep->sys->curr_polling_state)) { + ipa3_inc_acquire_wakelock(); + atomic_set(&ep->sys->curr_polling_state, 1); + queue_work(ep->sys->wq, &ep->sys->work); + } + } +} + + +static bool ipa3_gsi_channel_is_quite(struct ipa3_ep_context *ep) +{ + bool empty; + + gsi_is_channel_empty(ep->gsi_chan_hdl, &empty); + if (!empty) + IPADBG("ch %ld not empty\n", ep->gsi_chan_hdl); + /*Schedule NAPI only from interrupt context to avoid race conditions*/ + return empty; +} + +static int __ipa_stop_gsi_channel(u32 clnt_hdl) +{ + struct ipa_mem_buffer mem; + int res = 0; + int result = 0; + int i; + struct ipa3_ep_context *ep; + enum ipa_client_type client_type; + struct IpaHwOffloadStatsAllocCmdData_t *gsi_info; + + if (clnt_hdl >= ipa3_ctx->ipa_num_pipes || + ipa3_ctx->ep[clnt_hdl].valid == 0) { + IPAERR("bad parm.\n"); + return -EINVAL; + } + + ep = &ipa3_ctx->ep[clnt_hdl]; + client_type = ipa3_get_client_mapping(clnt_hdl); + if (IPA_CLIENT_IS_HOLB_CONS(client_type)) { + res = ipa3_uc_client_del_holb_monitor(ep->gsi_chan_hdl, + IPA_EE_AP); + if (res) + IPAERR("Delete HOLB monitor failed for ch %d\n", + ep->gsi_chan_hdl); + /* Set HOLB back if it was set previously. + * There is a possibility that uC will reset as part of HOLB + * monitoring. + */ + if (ep->holb.en) { + ipa3_cfg_ep_holb(clnt_hdl, &ep->holb); + } + } + memset(&mem, 0, sizeof(mem)); + + /* stop uC gsi dbg stats monitor */ + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_5 && + ipa3_ctx->ipa_hw_type != IPA_HW_v4_7 && + ipa3_ctx->ipa_hw_type != IPA_HW_v4_11 && + ipa3_ctx->ipa_hw_type != IPA_HW_v5_2) { + switch (client_type) { + case IPA_CLIENT_MHI_PRIME_TETH_PROD: + gsi_info = &ipa3_ctx->gsi_info[IPA_HW_PROTOCOL_MHIP]; + gsi_info->ch_id_info[0].ch_id = 0xff; + gsi_info->ch_id_info[0].dir = DIR_PRODUCER; + ipa3_uc_debug_stats_alloc(*gsi_info); + break; + case IPA_CLIENT_MHI_PRIME_TETH_CONS: + gsi_info = &ipa3_ctx->gsi_info[IPA_HW_PROTOCOL_MHIP]; + gsi_info->ch_id_info[1].ch_id = 0xff; + gsi_info->ch_id_info[1].dir = DIR_CONSUMER; + ipa3_uc_debug_stats_alloc(*gsi_info); + break; + case IPA_CLIENT_MHI_PRIME_RMNET_PROD: + gsi_info = &ipa3_ctx->gsi_info[IPA_HW_PROTOCOL_MHIP]; + gsi_info->ch_id_info[2].ch_id = 0xff; + gsi_info->ch_id_info[2].dir = DIR_PRODUCER; + ipa3_uc_debug_stats_alloc(*gsi_info); + break; + case IPA_CLIENT_MHI_PRIME_RMNET_CONS: + gsi_info = &ipa3_ctx->gsi_info[IPA_HW_PROTOCOL_MHIP]; + gsi_info->ch_id_info[3].ch_id = 0xff; + gsi_info->ch_id_info[3].dir = DIR_CONSUMER; + ipa3_uc_debug_stats_alloc(*gsi_info); + break; + case IPA_CLIENT_USB_PROD: + gsi_info = &ipa3_ctx->gsi_info[IPA_HW_PROTOCOL_USB]; + gsi_info->ch_id_info[0].ch_id = 0xff; + gsi_info->ch_id_info[0].dir = DIR_PRODUCER; + ipa3_uc_debug_stats_alloc(*gsi_info); + break; + case IPA_CLIENT_USB_CONS: + gsi_info = &ipa3_ctx->gsi_info[IPA_HW_PROTOCOL_USB]; + gsi_info->ch_id_info[1].ch_id = 0xff; + gsi_info->ch_id_info[1].dir = DIR_CONSUMER; + ipa3_uc_debug_stats_alloc(*gsi_info); + break; + default: + IPADBG("client_type %d not supported\n", + client_type); + } + } + + /* + * Apply the GSI stop retry logic if GSI returns err code to retry. + * Apply the retry logic for ipa_client_prod as well as ipa_client_cons. + */ + for (i = 0; i < IPA_GSI_CHANNEL_STOP_MAX_RETRY; i++) { + IPADBG("Calling gsi_stop_channel ch:%lu\n", + ep->gsi_chan_hdl); + res = gsi_stop_channel(ep->gsi_chan_hdl); + IPADBG("gsi_stop_channel ch: %lu returned %d\n", + ep->gsi_chan_hdl, res); + if (res != -GSI_STATUS_AGAIN && res != -GSI_STATUS_TIMED_OUT) + return res; + /* + * From >=IPA4.0 version not required to send dma send command, + * this issue was fixed in latest versions. + */ + if (ipa3_ctx->ipa_hw_type < IPA_HW_v4_0) { + IPADBG("Inject a DMA_TASK with 1B packet to IPA\n"); + /* Send a 1B packet DMA_TASK to IPA and try again */ + result = ipa3_inject_dma_task_for_gsi(); + if (result) { + IPAERR("Failed to inject DMA TASk for GSI\n"); + return result; + } + } + /* sleep for short period to flush IPA */ + usleep_range(IPA_GSI_CHANNEL_STOP_SLEEP_MIN_USEC, + IPA_GSI_CHANNEL_STOP_SLEEP_MAX_USEC); + } + + IPAERR("Failed to stop GSI channel with retries\n"); + return res; +} + +/** + * ipa_stop_gsi_channel()- Stops a GSI channel in IPA + * @chan_hdl: GSI channel handle + * + * This function implements the sequence to stop a GSI channel + * in IPA. This function returns when the channel is in STOP state. + * + * Return value: 0 on success, negative otherwise + */ +int ipa_stop_gsi_channel(u32 clnt_hdl) +{ + int res; + + IPA_ACTIVE_CLIENTS_INC_EP(ipa3_get_client_mapping(clnt_hdl)); + res = __ipa_stop_gsi_channel(clnt_hdl); + IPA_ACTIVE_CLIENTS_DEC_EP(ipa3_get_client_mapping(clnt_hdl)); + + return res; +} +EXPORT_SYMBOL(ipa_stop_gsi_channel); + +static int _ipa_suspend_resume_pipe(enum ipa_client_type client, bool suspend) +{ + struct ipa_ep_cfg_ctrl cfg; + int ipa_ep_idx, wan_coal_ep_idx, lan_coal_ep_idx; + struct ipa3_ep_context *ep; + int res; + + ipa_ep_idx = ipa_get_ep_mapping(client); + if (ipa_ep_idx < 0) { + IPADBG("client %d not configured\n", client); + return 0; + } + + ep = &ipa3_ctx->ep[ipa_ep_idx]; + if (!ep->valid) + return 0; + + IPADBG("%s pipe %d\n", suspend ? "suspend" : "unsuspend", ipa_ep_idx); + + if (ipa3_ctx->ipa_hw_type < IPA_HW_v4_0) { + if(client == IPA_CLIENT_APPS_WAN_CONS || + client == IPA_CLIENT_APPS_LAN_CONS) { + memset(&cfg, 0, sizeof(cfg)); + cfg.ipa_ep_suspend = suspend; + ipa_cfg_ep_ctrl(ipa_ep_idx, &cfg); + if (suspend) + ipa3_gsi_poll_after_suspend(ep); + else if (!atomic_read(&ep->sys->curr_polling_state)) + gsi_config_channel_mode(ep->gsi_chan_hdl, + GSI_CHAN_MODE_CALLBACK); + } + return 0; + } + + /* + * Configure the callback mode only one time after starting the channel + * otherwise observing IEOB interrupt received before configure callmode + * second time. It was leading race condition in updating current + * polling state. + */ + + if (suspend) { + res = __ipa_stop_gsi_channel(ipa_ep_idx); + if (res) { + IPAERR("failed to stop LAN channel\n"); + ipa_assert(); + } + } else { + res = gsi_start_channel(ep->gsi_chan_hdl); + if (res) { + IPAERR("failed to start LAN channel\n"); + ipa_assert(); + } + } + + /* Apps prod pipes use common event ring so cannot configure mode*/ + + /* + * Skipping to configure mode for default [w|l]an pipe, + * as both pipes using commong event ring. if both pipes + * configure same event ring observing race condition in + * updating current polling state. + */ + + if (IPA_CLIENT_IS_APPS_PROD(client) || + (client == IPA_CLIENT_APPS_WAN_CONS && + IPA_CLIENT_IS_MAPPED(IPA_CLIENT_APPS_WAN_COAL_CONS, wan_coal_ep_idx)) || + (client == IPA_CLIENT_APPS_LAN_CONS && + IPA_CLIENT_IS_MAPPED(IPA_CLIENT_APPS_LAN_COAL_CONS, lan_coal_ep_idx))) + return 0; + + if (suspend) { + IPADBG("switch ch %ld to poll\n", ep->gsi_chan_hdl); + gsi_config_channel_mode(ep->gsi_chan_hdl, GSI_CHAN_MODE_POLL); + if (!ipa3_gsi_channel_is_quite(ep)) + return -EAGAIN; + } else if (!atomic_read(&ep->sys->curr_polling_state)) { + IPADBG("switch ch %ld to callback\n", ep->gsi_chan_hdl); + gsi_config_channel_mode(ep->gsi_chan_hdl, + GSI_CHAN_MODE_CALLBACK); + } + + return 0; +} + +void ipa3_force_close_coal( + bool close_wan, + bool close_lan ) +{ + struct ipa3_desc desc[ MAX_CCP_SUB ]; + + int ep_idx, num_desc = 0; + + if ( close_wan + && + IPA_CLIENT_IS_MAPPED_VALID(IPA_CLIENT_APPS_WAN_COAL_CONS, ep_idx) + && + ipa3_ctx->coal_cmd_pyld[WAN_COAL_SUB] ) { + + ipa3_init_imm_cmd_desc( + &desc[num_desc], + ipa3_ctx->coal_cmd_pyld[WAN_COAL_SUB]); + + num_desc++; + } + + if ( close_lan + && + IPA_CLIENT_IS_MAPPED_VALID(IPA_CLIENT_APPS_LAN_COAL_CONS, ep_idx) + && + ipa3_ctx->coal_cmd_pyld[LAN_COAL_SUB] ) { + + ipa3_init_imm_cmd_desc( + &desc[num_desc], + ipa3_ctx->coal_cmd_pyld[LAN_COAL_SUB]); + + num_desc++; + } + + if (ipa3_ctx->ulso_wa && ipa3_ctx->coal_cmd_pyld[ULSO_COAL_SUB] ) { + ipa3_init_imm_cmd_desc( + &desc[num_desc], + ipa3_ctx->coal_cmd_pyld[ULSO_COAL_SUB]); + + num_desc++; + } + + if ( num_desc ) { + IPADBG("Sending %d descriptor(s) for coal force close\n", num_desc); + if ( ipa3_send_cmd_timeout( + num_desc, + desc, + IPA_COAL_CLOSE_FRAME_CMD_TIMEOUT_MSEC) ) { + IPADBG("ipa3_send_cmd_timeout timedout\n"); + } + } +} + +int ipa3_suspend_apps_pipes(bool suspend) +{ + int res, i; + struct ipa_ep_cfg_holb holb_cfg; + int odl_ep_idx; + + if (suspend) { + stop_coalescing(); + ipa3_force_close_coal(true, true); + } + + /* As per HPG first need start/stop coalescing channel + * then default one. Coalescing client number was greater then + * default one so starting the last client. + */ + res = _ipa_suspend_resume_pipe(IPA_CLIENT_APPS_WAN_COAL_CONS, suspend); + if (res == -EAGAIN) { + if (suspend) start_coalescing(); + goto undo_coal_cons; + } + + res = _ipa_suspend_resume_pipe(IPA_CLIENT_APPS_WAN_CONS, suspend); + if (res == -EAGAIN) { + if (suspend) start_coalescing(); + goto undo_wan_cons; + } + + res = _ipa_suspend_resume_pipe(IPA_CLIENT_APPS_LAN_COAL_CONS, suspend); + if (res == -EAGAIN) { + if (suspend) start_coalescing(); + goto undo_lan_coal_cons; + } + + res = _ipa_suspend_resume_pipe(IPA_CLIENT_APPS_LAN_CONS, suspend); + if (res == -EAGAIN) { + if (suspend) start_coalescing(); + goto undo_lan_cons; + } + + if (suspend) start_coalescing(); + + res = _ipa_suspend_resume_pipe(IPA_CLIENT_ODL_DPL_CONS, suspend); + if (res == -EAGAIN) { + goto undo_odl_cons; + } + + odl_ep_idx = ipa_get_ep_mapping(IPA_CLIENT_ODL_DPL_CONS); + if (odl_ep_idx != IPA_EP_NOT_ALLOCATED && ipa3_ctx->ep[odl_ep_idx].valid) { + memset(&holb_cfg, 0, sizeof(holb_cfg)); + if (suspend) + holb_cfg.en = 0; + else + holb_cfg.en = 1; + + ipahal_write_reg_n_fields(IPA_ENDP_INIT_HOL_BLOCK_EN_n, + odl_ep_idx, &holb_cfg); + /* IPA4.5 issue requires HOLB_EN to be written twice */ + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_5 && holb_cfg.en) + ipahal_write_reg_n_fields( + IPA_ENDP_INIT_HOL_BLOCK_EN_n, + odl_ep_idx, &holb_cfg); + + } + + res = _ipa_suspend_resume_pipe(IPA_CLIENT_APPS_WAN_LOW_LAT_CONS, + suspend); + if (res == -EAGAIN) { + goto undo_qmap_cons; + } + + res = _ipa_suspend_resume_pipe(IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_CONS, + suspend); + if (res == -EAGAIN) { + goto undo_low_lat_data_cons; + } + + if (suspend) { + struct ipahal_reg_tx_wrapper tx; + int ep_idx; + + ep_idx = ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS); + if (ep_idx == IPA_EP_NOT_ALLOCATED || + (!ipa3_ctx->ep[ep_idx].valid)) + goto do_prod; + + ipahal_read_reg_fields(IPA_STATE_TX_WRAPPER, &tx); + if (tx.coal_slave_open_frame != 0) { + IPADBG("COAL frame is open 0x%x\n", + tx.coal_slave_open_frame); + res = -EAGAIN; + goto undo_low_lat_data_cons; + } + + usleep_range(IPA_TAG_SLEEP_MIN_USEC, IPA_TAG_SLEEP_MAX_USEC); + + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0) { + for (i = 0; i < IPA_EP_ARR_SIZE; i++) { + res = ipahal_read_reg_nk( + IPA_SUSPEND_IRQ_INFO_EE_n_REG_k, + ipa3_ctx->ee, i); + if (res) { + IPADBG("suspend irq is pending 0x%x\n", + res); + goto undo_low_lat_data_cons; + } + } + } else { + res = ipahal_read_reg_n(IPA_SUSPEND_IRQ_INFO_EE_n, + ipa3_ctx->ee); + if (res) { + IPADBG("suspend irq is pending 0x%x\n", res); + goto undo_qmap_cons; + } + } + } +do_prod: + res = _ipa_suspend_resume_pipe(IPA_CLIENT_APPS_LAN_PROD, suspend); + if (res == -EAGAIN) + goto undo_lan_prod; + res = _ipa_suspend_resume_pipe(IPA_CLIENT_APPS_WAN_LOW_LAT_PROD, + suspend); + if (res == -EAGAIN) + goto undo_qmap_prod; + res = _ipa_suspend_resume_pipe(IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_PROD, + suspend); + if (res == -EAGAIN) + goto undo_low_lat_data_prod; + res = _ipa_suspend_resume_pipe(IPA_CLIENT_APPS_WAN_PROD, suspend); + if (res == -EAGAIN) + goto undo_wan_prod; + return 0; + +undo_wan_prod: + _ipa_suspend_resume_pipe(IPA_CLIENT_APPS_WAN_PROD, !suspend); +undo_low_lat_data_prod: + _ipa_suspend_resume_pipe(IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_PROD, + !suspend); +undo_qmap_prod: + _ipa_suspend_resume_pipe(IPA_CLIENT_APPS_WAN_LOW_LAT_PROD, + !suspend); +undo_lan_prod: + _ipa_suspend_resume_pipe(IPA_CLIENT_APPS_LAN_PROD, !suspend); +undo_low_lat_data_cons: + _ipa_suspend_resume_pipe(IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_CONS, + !suspend); +undo_qmap_cons: + _ipa_suspend_resume_pipe(IPA_CLIENT_APPS_WAN_LOW_LAT_CONS, + !suspend); +undo_odl_cons: + _ipa_suspend_resume_pipe(IPA_CLIENT_ODL_DPL_CONS, !suspend); +undo_lan_cons: + _ipa_suspend_resume_pipe(IPA_CLIENT_APPS_LAN_CONS, !suspend); +undo_lan_coal_cons: + _ipa_suspend_resume_pipe(IPA_CLIENT_APPS_LAN_COAL_CONS, !suspend); +undo_wan_cons: + _ipa_suspend_resume_pipe(IPA_CLIENT_APPS_WAN_COAL_CONS, !suspend); + _ipa_suspend_resume_pipe(IPA_CLIENT_APPS_WAN_CONS, !suspend); + return res; + +undo_coal_cons: + _ipa_suspend_resume_pipe(IPA_CLIENT_APPS_WAN_COAL_CONS, !suspend); + + return res; +} + +int ipa3_allocate_dma_task_for_gsi(void) +{ + struct ipahal_imm_cmd_dma_task_32b_addr cmd = { 0 }; + + IPADBG("Allocate mem\n"); + ipa3_ctx->dma_task_info.mem.size = IPA_GSI_CHANNEL_STOP_PKT_SIZE; + ipa3_ctx->dma_task_info.mem.base = dma_alloc_coherent(ipa3_ctx->pdev, + ipa3_ctx->dma_task_info.mem.size, + &ipa3_ctx->dma_task_info.mem.phys_base, + GFP_KERNEL); + if (!ipa3_ctx->dma_task_info.mem.base) { + IPAERR("no mem\n"); + return -EFAULT; + } + + cmd.flsh = true; + cmd.size1 = ipa3_ctx->dma_task_info.mem.size; + cmd.addr1 = ipa3_ctx->dma_task_info.mem.phys_base; + cmd.packet_size = ipa3_ctx->dma_task_info.mem.size; + ipa3_ctx->dma_task_info.cmd_pyld = ipahal_construct_imm_cmd( + IPA_IMM_CMD_DMA_TASK_32B_ADDR, &cmd, false); + if (!ipa3_ctx->dma_task_info.cmd_pyld) { + IPAERR("failed to construct dma_task_32b_addr cmd\n"); + dma_free_coherent(ipa3_ctx->pdev, + ipa3_ctx->dma_task_info.mem.size, + ipa3_ctx->dma_task_info.mem.base, + ipa3_ctx->dma_task_info.mem.phys_base); + memset(&ipa3_ctx->dma_task_info, 0, + sizeof(ipa3_ctx->dma_task_info)); + return -EFAULT; + } + + return 0; +} + +void ipa3_free_dma_task_for_gsi(void) +{ + dma_free_coherent(ipa3_ctx->pdev, + ipa3_ctx->dma_task_info.mem.size, + ipa3_ctx->dma_task_info.mem.base, + ipa3_ctx->dma_task_info.mem.phys_base); + ipahal_destroy_imm_cmd(ipa3_ctx->dma_task_info.cmd_pyld); + memset(&ipa3_ctx->dma_task_info, 0, sizeof(ipa3_ctx->dma_task_info)); +} + +int ipa3_allocate_coal_close_frame(void) +{ + struct ipahal_imm_cmd_register_write reg_write_cmd = { 0 }; + struct ipahal_imm_cmd_register_read dummy_reg_read = { 0 }; + struct ipahal_reg_valmask valmask; + u32 offset = 0; + int ep_idx, num_desc = 0; + + if ( IPA_CLIENT_IS_MAPPED(IPA_CLIENT_APPS_WAN_COAL_CONS, ep_idx) ) { + + IPADBG("Allocate wan coal close frame cmd\n"); + + reg_write_cmd.skip_pipeline_clear = false; + if (ipa3_ctx->ulso_wa) { + reg_write_cmd.pipeline_clear_options = IPAHAL_SRC_GRP_CLEAR; + } else { + reg_write_cmd.pipeline_clear_options = IPAHAL_HPS_CLEAR; + } + if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0) + offset = ipahal_get_reg_ofst( + IPA_AGGR_FORCE_CLOSE); + else + offset = ipahal_get_ep_reg_offset( + IPA_AGGR_FORCE_CLOSE_n, ep_idx); + reg_write_cmd.offset = offset; + ipahal_get_aggr_force_close_valmask(ep_idx, &valmask); + reg_write_cmd.value = valmask.val; + reg_write_cmd.value_mask = valmask.mask; + ipa3_ctx->coal_cmd_pyld[WAN_COAL_SUB] = + ipahal_construct_imm_cmd( + IPA_IMM_CMD_REGISTER_WRITE, + ®_write_cmd, false); + if (!ipa3_ctx->coal_cmd_pyld[WAN_COAL_SUB]) { + IPAERR("fail construct register_write imm cmd\n"); + ipa_assert(); + return 0; + } + num_desc++; + } + + if ( IPA_CLIENT_IS_MAPPED(IPA_CLIENT_APPS_LAN_COAL_CONS, ep_idx) ) { + + IPADBG("Allocate lan coal close frame cmd\n"); + + reg_write_cmd.skip_pipeline_clear = false; + if (ipa3_ctx->ulso_wa) { + reg_write_cmd.pipeline_clear_options = IPAHAL_SRC_GRP_CLEAR; + } else { + reg_write_cmd.pipeline_clear_options = IPAHAL_HPS_CLEAR; + } + if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0) + offset = ipahal_get_reg_ofst( + IPA_AGGR_FORCE_CLOSE); + else + offset = ipahal_get_ep_reg_offset( + IPA_AGGR_FORCE_CLOSE_n, ep_idx); + reg_write_cmd.offset = offset; + ipahal_get_aggr_force_close_valmask(ep_idx, &valmask); + reg_write_cmd.value = valmask.val; + reg_write_cmd.value_mask = valmask.mask; + ipa3_ctx->coal_cmd_pyld[LAN_COAL_SUB] = + ipahal_construct_imm_cmd( + IPA_IMM_CMD_REGISTER_WRITE, + ®_write_cmd, false); + if (!ipa3_ctx->coal_cmd_pyld[LAN_COAL_SUB]) { + IPAERR("fail construct register_write imm cmd\n"); + ipa_assert(); + return 0; + } + num_desc++; + } + + if ( ipa3_ctx->ulso_wa ) { + /* + * Dummy regsiter read IC with HPS clear + */ + ipa3_ctx->ulso_wa_cmd.size = 4; + ipa3_ctx->ulso_wa_cmd.base = + dma_alloc_coherent( + ipa3_ctx->pdev, + ipa3_ctx->ulso_wa_cmd.size, + &ipa3_ctx->ulso_wa_cmd.phys_base, GFP_KERNEL); + if (ipa3_ctx->ulso_wa_cmd.base == NULL) { + ipa_assert(); + } + offset = ipahal_get_reg_n_ofst( + IPA_STAT_QUOTA_BASE_n, + ipa3_ctx->ee); + dummy_reg_read.skip_pipeline_clear = false; + dummy_reg_read.pipeline_clear_options = IPAHAL_HPS_CLEAR; + dummy_reg_read.offset = offset; + dummy_reg_read.sys_addr = ipa3_ctx->ulso_wa_cmd.phys_base; + ipa3_ctx->coal_cmd_pyld[ULSO_COAL_SUB] = + ipahal_construct_imm_cmd( + IPA_IMM_CMD_REGISTER_READ, + &dummy_reg_read, false); + if (!ipa3_ctx->coal_cmd_pyld[ULSO_COAL_SUB]) { + IPAERR("failed to construct DUMMY READ IC\n"); + ipa_assert(); + } + } + + return 0; +} + +void ipa3_free_coal_close_frame(void) +{ + if (ipa3_ctx->coal_cmd_pyld[WAN_COAL_SUB]) { + ipahal_destroy_imm_cmd(ipa3_ctx->coal_cmd_pyld[WAN_COAL_SUB]); + } + + if (ipa3_ctx->coal_cmd_pyld[LAN_COAL_SUB]) { + ipahal_destroy_imm_cmd(ipa3_ctx->coal_cmd_pyld[LAN_COAL_SUB]); + } + + if (ipa3_ctx->coal_cmd_pyld[ULSO_COAL_SUB]) { + ipahal_destroy_imm_cmd(ipa3_ctx->coal_cmd_pyld[ULSO_COAL_SUB]); + } + + if ( ipa3_ctx->ulso_wa_cmd.base ) { + dma_free_coherent( + ipa3_ctx->pdev, + ipa3_ctx->ulso_wa_cmd.size, + ipa3_ctx->ulso_wa_cmd.base, + ipa3_ctx->ulso_wa_cmd.phys_base); + } +} + +/** + * ipa3_inject_dma_task_for_gsi()- Send DMA_TASK to IPA for GSI stop channel + * + * Send a DMA_TASK of 1B to IPA to unblock GSI channel in STOP_IN_PROG. + * Return value: 0 on success, negative otherwise + */ +int ipa3_inject_dma_task_for_gsi(void) +{ + struct ipa3_desc desc; + + ipa3_init_imm_cmd_desc(&desc, ipa3_ctx->dma_task_info.cmd_pyld); + + IPADBG("sending 1B packet to IPA\n"); + if (ipa3_send_cmd_timeout(1, &desc, + IPA_DMA_TASK_FOR_GSI_TIMEOUT_MSEC)) { + IPAERR("ipa3_send_cmd failed\n"); + return -EFAULT; + } + + return 0; +} + +static int ipa3_load_single_fw(const struct firmware *firmware, + const struct elf32_phdr *phdr) +{ + uint32_t *fw_mem_base; + int index; + const uint32_t *elf_data_ptr; + + if (phdr->p_offset > firmware->size) { + IPAERR("Invalid ELF: offset=%u is beyond elf_size=%zu\n", + phdr->p_offset, firmware->size); + return -EINVAL; + } + if ((firmware->size - phdr->p_offset) < phdr->p_filesz) { + IPAERR("Invalid ELF: offset=%u filesz=%u elf_size=%zu\n", + phdr->p_offset, phdr->p_filesz, firmware->size); + return -EINVAL; + } + + if (phdr->p_memsz % sizeof(uint32_t)) { + IPAERR("FW mem size %u doesn't align to 32bit\n", + phdr->p_memsz); + return -EFAULT; + } + + if (phdr->p_filesz > phdr->p_memsz) { + IPAERR("FW image too big src_size=%u dst_size=%u\n", + phdr->p_filesz, phdr->p_memsz); + return -EFAULT; + } + + fw_mem_base = ioremap(phdr->p_vaddr, phdr->p_memsz); + if (!fw_mem_base) { + IPAERR("Failed to map 0x%x for the size of %u\n", + phdr->p_vaddr, phdr->p_memsz); + return -ENOMEM; + } + + /* Set the entire region to 0s */ + memset(fw_mem_base, 0, phdr->p_memsz); + + elf_data_ptr = (uint32_t *)(firmware->data + phdr->p_offset); + + /* Write the FW */ + for (index = 0; index < phdr->p_filesz/sizeof(uint32_t); index++) { + writel_relaxed(*elf_data_ptr, &fw_mem_base[index]); + elf_data_ptr++; + } + + iounmap(fw_mem_base); + + return 0; +} + +struct ipa3_hps_dps_areas_info { + u32 dps_abs_addr; + u32 dps_sz; + u32 hps_abs_addr; + u32 hps_sz; +}; + +static void ipa3_get_hps_dps_areas_absolute_addr_and_sz( + struct ipa3_hps_dps_areas_info *info) +{ + u32 dps_area_start; + u32 dps_area_end; + u32 hps_area_start; + u32 hps_area_end; + + if (ipa3_ctx->ipa_hw_type < IPA_HW_v4_5) { + dps_area_start = ipahal_get_reg_ofst(IPA_DPS_SEQUENCER_FIRST); + dps_area_end = ipahal_get_reg_ofst(IPA_DPS_SEQUENCER_LAST); + hps_area_start = ipahal_get_reg_ofst(IPA_HPS_SEQUENCER_FIRST); + hps_area_end = ipahal_get_reg_ofst(IPA_HPS_SEQUENCER_LAST); + + info->dps_abs_addr = ipa3_ctx->ipa_wrapper_base + + ipahal_get_reg_base() + dps_area_start; + info->hps_abs_addr = ipa3_ctx->ipa_wrapper_base + + ipahal_get_reg_base() + hps_area_start; + } else { + dps_area_start = ipahal_read_reg(IPA_DPS_SEQUENCER_FIRST); + dps_area_end = ipahal_read_reg(IPA_DPS_SEQUENCER_LAST); + hps_area_start = ipahal_read_reg(IPA_HPS_SEQUENCER_FIRST); + hps_area_end = ipahal_read_reg(IPA_HPS_SEQUENCER_LAST); + + info->dps_abs_addr = ipa3_ctx->ipa_wrapper_base + + dps_area_start; + info->hps_abs_addr = ipa3_ctx->ipa_wrapper_base + + hps_area_start; + } + + info->dps_sz = dps_area_end - dps_area_start + sizeof(u32); + info->hps_sz = hps_area_end - hps_area_start + sizeof(u32); + + IPADBG("dps area: start offset=0x%x end offset=0x%x\n", + dps_area_start, dps_area_end); + IPADBG("hps area: start offset=0x%x end offset=0x%x\n", + hps_area_start, hps_area_end); +} + +/** + * emulator_load_single_fw() - load firmware into emulator's memory + * + * @firmware: Structure which contains the FW data from the user space. + * @phdr: ELF program header + * @loc_to_map: physical location to map into virtual space + * @size_to_map: the size of memory to map into virtual space + * + * Return value: 0 on success, negative otherwise + */ +static int emulator_load_single_fw( + const struct firmware *firmware, + const struct elf32_phdr *phdr, + u32 loc_to_map, + u32 size_to_map) +{ + int index; + uint32_t ofb; + const uint32_t *elf_data_ptr; + void __iomem *fw_base; + + IPADBG("firmware(%pK) phdr(%pK) loc_to_map(0x%X) size_to_map(%u)\n", + firmware, phdr, loc_to_map, size_to_map); + + if (phdr->p_offset > firmware->size) { + IPAERR("Invalid ELF: offset=%u is beyond elf_size=%zu\n", + phdr->p_offset, firmware->size); + return -EINVAL; + } + if ((firmware->size - phdr->p_offset) < phdr->p_filesz) { + IPAERR("Invalid ELF: offset=%u filesz=%u elf_size=%zu\n", + phdr->p_offset, phdr->p_filesz, firmware->size); + return -EINVAL; + } + + if (phdr->p_memsz % sizeof(uint32_t)) { + IPAERR("FW mem size %u doesn't align to 32bit\n", + phdr->p_memsz); + return -EFAULT; + } + + if (phdr->p_filesz > phdr->p_memsz) { + IPAERR("FW image too big src_size=%u dst_size=%u\n", + phdr->p_filesz, phdr->p_memsz); + return -EFAULT; + } + + IPADBG("ELF: p_memsz(0x%x) p_filesz(0x%x) p_filesz/4(0x%x)\n", + (uint32_t) phdr->p_memsz, + (uint32_t) phdr->p_filesz, + (uint32_t) (phdr->p_filesz/sizeof(uint32_t))); + + fw_base = ioremap(loc_to_map, size_to_map); + if (!fw_base) { + IPAERR("Failed to map 0x%X for the size of %u\n", + loc_to_map, size_to_map); + return -ENOMEM; + } + + IPADBG("Physical base(0x%X) mapped to virtual (%pK) with len (%u)\n", + loc_to_map, + fw_base, + size_to_map); + + /* Set the entire region to 0s */ + ofb = 0; + for (index = 0; index < phdr->p_memsz/sizeof(uint32_t); index++) { + writel_relaxed(0, fw_base + ofb); + ofb += sizeof(uint32_t); + } + + elf_data_ptr = (uint32_t *)(firmware->data + phdr->p_offset); + + /* Write the FW */ + ofb = 0; + for (index = 0; index < phdr->p_filesz/sizeof(uint32_t); index++) { + writel_relaxed(*elf_data_ptr, fw_base + ofb); + elf_data_ptr++; + ofb += sizeof(uint32_t); + } + + iounmap(fw_base); + + return 0; +} + +/** + * ipa3_load_fws() - Load the IPAv3 FWs into IPA&GSI SRAM. + * + * @firmware: Structure which contains the FW data from the user space. + * @gsi_mem_base: GSI base address + * @gsi_ver: GSI Version + * + * Return value: 0 on success, negative otherwise + * + */ +int ipa3_load_fws(const struct firmware *firmware, phys_addr_t gsi_mem_base, + enum gsi_ver gsi_ver) +{ + const struct elf32_hdr *ehdr; + const struct elf32_phdr *phdr; + unsigned long gsi_iram_ofst; + unsigned long gsi_iram_size; + int rc; + struct ipa3_hps_dps_areas_info dps_hps_info; + + if (gsi_ver == GSI_VER_ERR) { + IPAERR("Invalid GSI Version\n"); + return -EINVAL; + } + + if (!gsi_mem_base) { + IPAERR("Invalid GSI base address\n"); + return -EINVAL; + } + + ipa_assert_on(!firmware); + /* One program header per FW image: GSI, DPS and HPS */ + if (firmware->size < (sizeof(*ehdr) + 3 * sizeof(*phdr))) { + IPAERR("Missing ELF and Program headers firmware size=%zu\n", + firmware->size); + return -EINVAL; + } + + ehdr = (struct elf32_hdr *) firmware->data; + ipa_assert_on(!ehdr); + if (ehdr->e_phnum != 3 && ehdr->e_phnum != 5) { + IPAERR("Unexpected number of ELF program headers\n"); + return -EINVAL; + } + + phdr = (struct elf32_phdr *)(firmware->data + sizeof(*ehdr)); + + if (ehdr->e_phnum == 5) + phdr = phdr + 2; + /* + * Each ELF program header represents a FW image and contains: + * p_vaddr : The starting address to which the FW needs to loaded. + * p_memsz : The size of the IRAM (where the image loaded) + * p_filesz: The size of the FW image embedded inside the ELF + * p_offset: Absolute offset to the image from the head of the ELF + */ + + /* Load GSI FW image */ + gsi_get_inst_ram_offset_and_size(&gsi_iram_ofst, &gsi_iram_size, + gsi_ver); + if (phdr->p_vaddr != (gsi_mem_base + gsi_iram_ofst)) { + IPAERR( + "Invalid GSI FW img load addr vaddr=0x%x gsi_mem_base=%pa gsi_iram_ofst=0x%lx\n" + , phdr->p_vaddr, &gsi_mem_base, gsi_iram_ofst); + return -EINVAL; + } + if (phdr->p_memsz > gsi_iram_size) { + IPAERR("Invalid GSI FW img size memsz=%d gsi_iram_size=%lu\n", + phdr->p_memsz, gsi_iram_size); + return -EINVAL; + } + rc = ipa3_load_single_fw(firmware, phdr); + if (rc) + return rc; + + phdr++; + ipa3_get_hps_dps_areas_absolute_addr_and_sz(&dps_hps_info); + + /* Load IPA DPS FW image */ + if (phdr->p_vaddr != dps_hps_info.dps_abs_addr) { + IPAERR( + "Invalid IPA DPS img load addr vaddr=0x%x dps_abs_addr=0x%x\n" + , phdr->p_vaddr, dps_hps_info.dps_abs_addr); + return -EINVAL; + } + if (phdr->p_memsz > dps_hps_info.dps_sz) { + IPAERR("Invalid IPA DPS img size memsz=%d dps_area_size=%u\n", + phdr->p_memsz, dps_hps_info.dps_sz); + return -EINVAL; + } + rc = ipa3_load_single_fw(firmware, phdr); + if (rc) + return rc; + + phdr++; + + /* Load IPA HPS FW image */ + if (phdr->p_vaddr != dps_hps_info.hps_abs_addr) { + IPAERR( + "Invalid IPA HPS img load addr vaddr=0x%x hps_abs_addr=0x%x\n" + , phdr->p_vaddr, dps_hps_info.hps_abs_addr); + return -EINVAL; + } + if (phdr->p_memsz > dps_hps_info.hps_sz) { + IPAERR("Invalid IPA HPS img size memsz=%d hps_area_size=%u\n", + phdr->p_memsz, dps_hps_info.hps_sz); + return -EINVAL; + } + rc = ipa3_load_single_fw(firmware, phdr); + if (rc) + return rc; + + IPADBG("IPA FWs (GSI FW, DPS and HPS) loaded successfully\n"); + return 0; +} + +/* + * The following needed for the EMULATION system. On a non-emulation + * system (ie. the real UE), this functionality is done in the + * TZ... + */ + +static void ipa_gsi_setup_reg(void) +{ + u32 reg_val, start; + int i; + const struct ipa_gsi_ep_config *gsi_ep_info_cfg; + enum ipa_client_type type; + + IPADBG("Setting up registers in preparation for firmware download\n"); + + /* setup IPA_ENDP_GSI_CFG_TLV_n reg */ + start = 0; + ipa3_ctx->ipa_num_pipes = ipa3_get_num_pipes(); + IPADBG("ipa_num_pipes=%u\n", ipa3_ctx->ipa_num_pipes); + + for (i = 0; i < ipa3_ctx->ipa_num_pipes; i++) { + type = ipa3_get_client_by_pipe(i); + gsi_ep_info_cfg = ipa_get_gsi_ep_info(type); + IPAERR("for ep %d client is %d gsi_ep_info_cfg=%pK\n", + i, type, gsi_ep_info_cfg); + if (!gsi_ep_info_cfg) + continue; + reg_val = ((gsi_ep_info_cfg->ipa_if_tlv << 16) & 0x00FF0000); + reg_val += (start & 0xFFFF); + start += gsi_ep_info_cfg->ipa_if_tlv; + ipahal_write_reg_n(IPA_ENDP_GSI_CFG_TLV_n, i, reg_val); + } + + /* setup IPA_ENDP_GSI_CFG_AOS_n reg */ + for (i = 0; i < ipa3_ctx->ipa_num_pipes; i++) { + type = ipa3_get_client_by_pipe(i); + gsi_ep_info_cfg = ipa_get_gsi_ep_info(type); + if (!gsi_ep_info_cfg) + continue; + reg_val = ((gsi_ep_info_cfg->ipa_if_aos << 16) & 0x00FF0000); + reg_val += (start & 0xFFFF); + start += gsi_ep_info_cfg->ipa_if_aos; + ipahal_write_reg_n(IPA_ENDP_GSI_CFG_AOS_n, i, reg_val); + } + + /* setup GSI_MAP_EE_n_CH_k_VP_TABLE reg */ + for (i = 0; i < ipa3_ctx->ipa_num_pipes; i++) { + type = ipa3_get_client_by_pipe(i); + gsi_ep_info_cfg = ipa_get_gsi_ep_info(type); + if (!gsi_ep_info_cfg) + continue; + reg_val = i & 0xFF; + gsi_map_virtual_ch_to_per_ep( + gsi_ep_info_cfg->ee, + gsi_ep_info_cfg->ipa_gsi_chan_num, + reg_val); + } + + /* setup IPA_ENDP_GSI_CFG1_n reg */ + for (i = 0; i < ipa3_ctx->ipa_num_pipes; i++) { + type = ipa3_get_client_by_pipe(i); + gsi_ep_info_cfg = ipa_get_gsi_ep_info(type); + if (!gsi_ep_info_cfg) + continue; + reg_val = (1 << 31) + (1 << 16); + ipahal_write_reg_n(IPA_ENDP_GSI_CFG1_n, i, 1<<16); + ipahal_write_reg_n(IPA_ENDP_GSI_CFG1_n, i, reg_val); + ipahal_write_reg_n(IPA_ENDP_GSI_CFG1_n, i, 1<<16); + } +} + +/** + * emulator_load_fws() - Load the IPAv3 FWs into IPA&GSI SRAM. + * + * @firmware: Structure which contains the FW data from the user space. + * @transport_mem_base: Where to load + * @transport_mem_size: Space available to load into + * @gsi_ver: Version of the gsi + * + * Return value: 0 on success, negative otherwise + */ +int emulator_load_fws( + const struct firmware *firmware, + u32 transport_mem_base, + u32 transport_mem_size, + enum gsi_ver gsi_ver) +{ + const struct elf32_hdr *ehdr; + const struct elf32_phdr *phdr; + unsigned long gsi_offset, gsi_ram_size; + struct ipa3_hps_dps_areas_info dps_hps_info; + int rc; + + IPADBG("Loading firmware(%pK)\n", firmware); + + if (!firmware) { + IPAERR("firmware pointer passed to function is NULL\n"); + return -EINVAL; + } + + /* One program header per FW image: GSI, DPS and HPS */ + if (firmware->size < (sizeof(*ehdr) + 3 * sizeof(*phdr))) { + IPAERR( + "Missing ELF and Program headers firmware size=%zu\n", + firmware->size); + return -EINVAL; + } + + ehdr = (struct elf32_hdr *) firmware->data; + + ipa_assert_on(!ehdr); + + if (ehdr->e_phnum != 3) { + IPAERR("Unexpected number of ELF program headers\n"); + return -EINVAL; + } + + ipa3_get_hps_dps_areas_absolute_addr_and_sz(&dps_hps_info); + + /* + * Each ELF program header represents a FW image and contains: + * p_vaddr : The starting address to which the FW needs to loaded. + * p_memsz : The size of the IRAM (where the image loaded) + * p_filesz: The size of the FW image embedded inside the ELF + * p_offset: Absolute offset to the image from the head of the ELF + * + * NOTE WELL: On the emulation platform, the p_vaddr address + * is not relevant and is unused. This is because + * on the emulation platform, the registers' + * address location is mutable, since it's mapped + * in via a PCIe probe. Given this, it is the + * mapped address info that's used while p_vaddr is + * ignored. + */ + phdr = (struct elf32_phdr *)(firmware->data + sizeof(*ehdr)); + + phdr += 2; + + /* + * Attempt to load IPA HPS FW image + */ + if (phdr->p_memsz > dps_hps_info.hps_sz) { + IPAERR("Invalid IPA HPS img size memsz=%d hps_size=%u\n", + phdr->p_memsz, dps_hps_info.hps_sz); + return -EINVAL; + } + IPADBG("Loading HPS FW\n"); + rc = emulator_load_single_fw( + firmware, phdr, + dps_hps_info.hps_abs_addr, dps_hps_info.hps_sz); + if (rc) + return rc; + IPADBG("Loading HPS FW complete\n"); + + --phdr; + + /* + * Attempt to load IPA DPS FW image + */ + if (phdr->p_memsz > dps_hps_info.dps_sz) { + IPAERR("Invalid IPA DPS img size memsz=%d dps_size=%u\n", + phdr->p_memsz, dps_hps_info.dps_sz); + return -EINVAL; + } + IPADBG("Loading DPS FW\n"); + rc = emulator_load_single_fw( + firmware, phdr, + dps_hps_info.dps_abs_addr, dps_hps_info.dps_sz); + if (rc) + return rc; + IPADBG("Loading DPS FW complete\n"); + + /* + * Run gsi register setup which is normally done in TZ on + * non-EMULATION systems... + */ + ipa_gsi_setup_reg(); + + --phdr; + + gsi_get_inst_ram_offset_and_size(&gsi_offset, &gsi_ram_size, gsi_ver); + + /* + * Attempt to load GSI FW image + */ + if (phdr->p_memsz > gsi_ram_size) { + IPAERR( + "Invalid GSI FW img size memsz=%d gsi_ram_size=%lu\n", + phdr->p_memsz, gsi_ram_size); + return -EINVAL; + } + IPADBG("Loading GSI FW\n"); + rc = emulator_load_single_fw( + firmware, phdr, + transport_mem_base + (u32) gsi_offset, gsi_ram_size); + if (rc) + return rc; + IPADBG("Loading GSI FW complete\n"); + + IPADBG("IPA FWs (GSI FW, DPS and HPS) loaded successfully\n"); + + return 0; +} + +/** + * ipa3_is_msm_device() - Is the running device a MSM or MDM + * Determine according to IPA version + * + * Return value: true if MSM, false if MDM + * + */ +bool ipa3_is_msm_device(void) +{ + switch (ipa3_ctx->ipa_hw_type){ + case IPA_HW_v3_0: + case IPA_HW_v3_5: + case IPA_HW_v4_0: + case IPA_HW_v4_5: + case IPA_HW_v5_0: + return false; + case IPA_HW_v3_1: + case IPA_HW_v3_5_1: + case IPA_HW_v4_1: + case IPA_HW_v4_2: + case IPA_HW_v4_7: + case IPA_HW_v4_9: + case IPA_HW_v4_11: + case IPA_HW_v5_1: + case IPA_HW_v5_2: + case IPA_HW_v5_5: + return true; + default: + IPAERR("unknown HW type %d\n", ipa3_ctx->ipa_hw_type); + ipa_assert(); + } + + return false; +} + +/** + * ipa3_is_apq() - indicate apq platform or not + * + * Return value: true if apq, false if not apq platform + * + */ +bool ipa3_is_apq(void) +{ + if (ipa3_ctx->platform_type == IPA_PLAT_TYPE_APQ) + return true; + else + return false; +} + +/** + * ipa_get_fnr_info() - get fnr_info + * + * Return value: true if set, false if not set + * + */ +bool ipa_get_fnr_info(struct ipacm_fnr_info *fnr_info) +{ + bool res = false; + + if (ipa3_ctx->fnr_info.valid) { + fnr_info->valid = ipa3_ctx->fnr_info.valid; + fnr_info->hw_counter_offset = + ipa3_ctx->fnr_info.hw_counter_offset; + fnr_info->sw_counter_offset = + ipa3_ctx->fnr_info.sw_counter_offset; + res = true; + } else { + IPAERR("fnr_info not valid!\n"); + res = false; + } + return res; +} + +/** + * ipa3_disable_prefetch() - disable\enable tx prefetch + * + * @client: the client which is related to the TX where prefetch will be + * disabled + * + * Return value: Non applicable + * + */ +void ipa3_disable_prefetch(enum ipa_client_type client) +{ + struct ipahal_reg_tx_cfg cfg; + u8 qmb; + + qmb = ipa3_get_qmb_master_sel(client); + + IPADBG("disabling prefetch for qmb %d\n", (int)qmb); + + ipahal_read_reg_fields(IPA_TX_CFG, &cfg); + /* QMB0 (DDR) correlates with TX0, QMB1(PCIE) correlates with TX1 */ + if (qmb == QMB_MASTER_SELECT_DDR) + cfg.tx0_prefetch_disable = true; + else + cfg.tx1_prefetch_disable = true; + ipahal_write_reg_fields(IPA_TX_CFG, &cfg); +} + +/** + * ipa3_get_pdev() - return a pointer to IPA dev struct + * + * Return value: a pointer to IPA dev struct + * + */ +struct device *ipa3_get_pdev(void) +{ + if (!ipa3_ctx) + return NULL; + + return ipa3_ctx->pdev; +} +EXPORT_SYMBOL(ipa3_get_pdev); + +/** + * ipa3_enable_dcd() - enable dynamic clock division on IPA + * + * Return value: Non applicable + * + */ +void ipa3_enable_dcd(void) +{ + struct ipahal_reg_idle_indication_cfg idle_indication_cfg; + + /* recommended values for IPA 3.5 according to IPA HPG */ + idle_indication_cfg.const_non_idle_enable = false; + idle_indication_cfg.enter_idle_debounce_thresh = 256; + + ipahal_write_reg_fields(IPA_IDLE_INDICATION_CFG, + &idle_indication_cfg); +} + +void ipa3_init_imm_cmd_desc(struct ipa3_desc *desc, + struct ipahal_imm_cmd_pyld *cmd_pyld) +{ + memset(desc, 0, sizeof(*desc)); + desc->opcode = cmd_pyld->opcode; + desc->pyld = cmd_pyld->data; + desc->len = cmd_pyld->len; + desc->type = IPA_IMM_CMD_DESC; +} + +u32 ipa3_get_r_rev_version(void) +{ + static u32 r_rev; + + if (r_rev != 0) + return r_rev; + + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + r_rev = ipahal_read_reg(IPA_VERSION); + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + + return r_rev; +} +EXPORT_SYMBOL(ipa3_get_r_rev_version); + +/** + * ipa3_ctx_get_type() - to get platform type, hw type + * and hw mode + * + * Return value: enumerated types of platform and ipa hw + * + */ +int ipa3_ctx_get_type(enum ipa_type_mode type) +{ + switch (type) { + case IPA_HW_TYPE: + return ipa3_ctx->ipa_hw_type; + case PLATFORM_TYPE: + return ipa3_ctx->platform_type; + case IPA3_HW_MODE: + return ipa3_ctx->ipa3_hw_mode; + default: + IPAERR("cannot read ipa3_ctx types\n"); + return 0; + } +} + +/** + * ipa3_get_gsi_stats() - Query gsi stats from uc + * @prot_id: IPA_HW_FEATURE_OFFLOAD protocol id + * @stats: [inout] stats blob from client populated by driver + * + * @note Cannot be called from atomic context + * + */ +void ipa3_get_gsi_stats(int prot_id, + struct ipa_uc_dbg_ring_stats *stats) +{ + switch (prot_id) { + case IPA_HW_PROTOCOL_AQC: + stats->num_ch = MAX_AQC_CHANNELS; + ipa3_get_aqc_gsi_stats(stats); + break; + case IPA_HW_PROTOCOL_RTK: + stats->num_ch = MAX_RTK_CHANNELS; + ipa3_get_rtk_gsi_stats(stats); + break; + case IPA_HW_PROTOCOL_11ad: + break; + case IPA_HW_PROTOCOL_WDI: + stats->num_ch = MAX_WDI2_CHANNELS; + ipa3_get_wdi_gsi_stats(stats); + break; + case IPA_HW_PROTOCOL_WDI3: + stats->num_ch = MAX_WDI3_CHANNELS; + ipa3_get_wdi3_gsi_stats(stats); + break; + case IPA_HW_PROTOCOL_NTN3: + stats->num_ch = MAX_NTN_CHANNELS; + ipa3_get_ntn_gsi_stats(stats); + break; + case IPA_HW_PROTOCOL_MHIP: + stats->num_ch = MAX_MHIP_CHANNELS; + ipa3_get_mhip_gsi_stats(stats); + break; + case IPA_HW_PROTOCOL_USB: + stats->num_ch = MAX_USB_CHANNELS; + ipa3_get_usb_gsi_stats(stats); + break; + default: + IPAERR("unsupported HW feature %d\n", prot_id); + } +} + +/** + * ipa3_ctx_get_flag() - to read some ipa3_ctx_flags + * + * Return value: true/false based on read value + * + */ +bool ipa3_ctx_get_flag(enum ipa_flag flag) +{ + switch (flag) { + case IPA_ENDP_DELAY_WA_EN: + return ipa3_ctx->ipa_endp_delay_wa; + case IPA_HW_STATS_EN: + return (ipa3_ctx->hw_stats && ipa3_ctx->hw_stats->enabled); + case IPA_MHI_EN: + return ipa3_ctx->ipa_config_is_mhi; + case IPA_FLTRT_NOT_HASHABLE_EN: + return ipa3_ctx->ipa_fltrt_not_hashable; + default: + IPAERR("cannot read ipa3_ctx flags\n"); + return false; + } +} + +/** + * ipa3_ctx_get_num_pipes() - to read pipe number from ipa3_ctx + * + * Return value: unsigned number + * + */ +u32 ipa3_ctx_get_num_pipes(void) +{ + return ipa3_ctx->ipa_num_pipes; +} + +int ipa3_app_clk_vote( + enum ipa_app_clock_vote_type vote_type) +{ + const char *str_ptr = "APP_VOTE"; + int ret = 0; + + IPADBG("In\n"); + + mutex_lock(&ipa3_ctx->app_clock_vote.mutex); + + switch (vote_type) { + case IPA_APP_CLK_VOTE: + if ((ipa3_ctx->app_clock_vote.cnt + 1) <= IPA_APP_VOTE_MAX) { + ipa3_ctx->app_clock_vote.cnt++; + IPA_ACTIVE_CLIENTS_INC_SPECIAL(str_ptr); + } else { + IPAERR_RL("App vote count max hit\n"); + ret = -EPERM; + break; + } + break; + case IPA_APP_CLK_DEVOTE: + if (ipa3_ctx->app_clock_vote.cnt) { + ipa3_ctx->app_clock_vote.cnt--; + IPA_ACTIVE_CLIENTS_DEC_SPECIAL(str_ptr); + } + break; + case IPA_APP_CLK_RESET_VOTE: + while (ipa3_ctx->app_clock_vote.cnt > 0) { + IPA_ACTIVE_CLIENTS_DEC_SPECIAL(str_ptr); + ipa3_ctx->app_clock_vote.cnt--; + } + break; + default: + IPAERR_RL("Unknown vote_type(%u)\n", vote_type); + ret = -EPERM; + break; + } + + mutex_unlock(&ipa3_ctx->app_clock_vote.mutex); + + IPADBG("Out\n"); + + return ret; +} + +/* + * ipa3_get_prot_id() - Query gsi protocol id + * @client: ipa_client_type + * + * return the prot_id based on the client type, + * return -EINVAL when no such mapping exists. + */ +int ipa3_get_prot_id(enum ipa_client_type client) +{ + int prot_id = -EINVAL; + + switch (client) { + case IPA_CLIENT_AQC_ETHERNET_CONS: + case IPA_CLIENT_AQC_ETHERNET_PROD: + prot_id = IPA_HW_PROTOCOL_AQC; + break; + case IPA_CLIENT_RTK_ETHERNET_CONS: + case IPA_CLIENT_RTK_ETHERNET_PROD: + prot_id = IPA_HW_PROTOCOL_RTK; + break; + case IPA_CLIENT_MHI_PRIME_TETH_PROD: + case IPA_CLIENT_MHI_PRIME_TETH_CONS: + case IPA_CLIENT_MHI_PRIME_RMNET_PROD: + case IPA_CLIENT_MHI_PRIME_RMNET_CONS: + prot_id = IPA_HW_PROTOCOL_MHIP; + break; + case IPA_CLIENT_WLAN1_PROD: + case IPA_CLIENT_WLAN1_CONS: + prot_id = IPA_HW_PROTOCOL_WDI; + break; + case IPA_CLIENT_WLAN2_PROD: + case IPA_CLIENT_WLAN2_CONS: + case IPA_CLIENT_WLAN2_CONS1: + prot_id = IPA_HW_PROTOCOL_WDI3; + break; + case IPA_CLIENT_USB_PROD: + case IPA_CLIENT_USB_CONS: + prot_id = IPA_HW_PROTOCOL_USB; + break; + case IPA_CLIENT_ETHERNET2_PROD: + case IPA_CLIENT_ETHERNET2_CONS: + case IPA_CLIENT_ETHERNET_PROD: + case IPA_CLIENT_ETHERNET_CONS: + prot_id = IPA_HW_PROTOCOL_ETH; + break; + case IPA_CLIENT_WIGIG_PROD: + case IPA_CLIENT_WIGIG1_CONS: + case IPA_CLIENT_WIGIG2_CONS: + case IPA_CLIENT_WIGIG3_CONS: + case IPA_CLIENT_WIGIG4_CONS: + prot_id = IPA_HW_PROTOCOL_11ad; + break; + default: + IPAERR("unknown prot_id for client %d\n", + client); + } + + return prot_id; +} + +void __ipa_ntn3_prod_stats_get(struct ipa_ntn3_stats_rx *stats, enum ipa_client_type client) +{ + int ch_id, ipa_ep_idx; + + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + ipa_ep_idx = ipa_get_ep_mapping(client); + if (ipa_ep_idx == IPA_EP_NOT_ALLOCATED) + return; + ch_id = ipa3_ctx->ep[ipa_ep_idx].gsi_chan_hdl; + + stats->pending_db_after_rollback = gsi_ntn3_client_stats_get(ipa_ep_idx, 4, ch_id); + stats->msi_db_idx = gsi_ntn3_client_stats_get(ipa_ep_idx, 5, ch_id); + stats->chain_cnt = gsi_ntn3_client_stats_get(ipa_ep_idx, 6, ch_id); + stats->err_cnt = gsi_ntn3_client_stats_get(ipa_ep_idx, 7, ch_id); + stats->tres_handled = gsi_ntn3_client_stats_get(ipa_ep_idx, 8, ch_id); + stats->rollbacks_cnt = gsi_ntn3_client_stats_get(ipa_ep_idx, 9, ch_id); + stats->msi_db_cnt = gsi_ntn3_client_stats_get(ipa_ep_idx, -1, ch_id); + + stats->wp = gsi_get_refetch_reg(ch_id, false); + stats->rp = gsi_get_refetch_reg(ch_id, true); + + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + +} + +void __ipa_ntn3_cons_stats_get(struct ipa_ntn3_stats_tx *stats, enum ipa_client_type client) +{ + int ch_id, ipa_ep_idx; + + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + ipa_ep_idx = ipa_get_ep_mapping(client); + if (ipa_ep_idx == IPA_EP_NOT_ALLOCATED) + return; + ch_id = ipa3_ctx->ep[ipa_ep_idx].gsi_chan_hdl; + + stats->pending_db_after_rollback = gsi_ntn3_client_stats_get(ipa_ep_idx, 4, ch_id); + stats->msi_db_idx = gsi_ntn3_client_stats_get(ipa_ep_idx, 5, ch_id); + stats->derr_cnt = gsi_ntn3_client_stats_get(ipa_ep_idx, 6, ch_id); + stats->oob_cnt = gsi_ntn3_client_stats_get(ipa_ep_idx, 7, ch_id); + stats->tres_handled = gsi_ntn3_client_stats_get(ipa_ep_idx, 8, ch_id); + stats->rollbacks_cnt = gsi_ntn3_client_stats_get(ipa_ep_idx, 9, ch_id); + stats->msi_db_cnt = gsi_ntn3_client_stats_get(ipa_ep_idx, -1, ch_id); + + stats->wp = gsi_get_refetch_reg(ch_id, false); + stats->rp = gsi_get_refetch_reg(ch_id, true); + + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + +} + +void ipa_eth_ntn3_get_status(struct ipa_ntn3_client_stats *s, unsigned inst_id) +{ + if (inst_id == 0) { + __ipa_ntn3_cons_stats_get(&s->tx_stats, IPA_CLIENT_ETHERNET_CONS); + __ipa_ntn3_prod_stats_get(&s->rx_stats, IPA_CLIENT_ETHERNET_PROD); + } else { + __ipa_ntn3_cons_stats_get(&s->tx_stats, IPA_CLIENT_ETHERNET2_CONS); + __ipa_ntn3_prod_stats_get(&s->rx_stats, IPA_CLIENT_ETHERNET2_PROD); + } + +} + +void ipa3_eth_get_status(u32 client, int scratch_id, + struct ipa3_eth_error_stats *stats) +{ +#define RTK_GSI_SCRATCH_ID 5 +#define AQC_GSI_SCRATCH_ID 7 +#define NTN_GSI_SCRATCH_ID 6 + + int ch_id; + int ipa_ep_idx; + + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + ipa_ep_idx = ipa_get_ep_mapping(client); + if (ipa_ep_idx == IPA_EP_NOT_ALLOCATED) + return; + ch_id = ipa3_ctx->ep[ipa_ep_idx].gsi_chan_hdl; + + /* + * drop stats sometimes exist for RX and sometimes for Tx, + * wp sometimes acquired from ch_cntxt_6 and sometimes from refetch, + * depending on protocol. + */ + stats->err = 0; + switch (client) { + case IPA_CLIENT_RTK_ETHERNET_PROD: + stats->err = gsi_get_drop_stats(ipa_ep_idx, RTK_GSI_SCRATCH_ID, + ch_id); + fallthrough; + case IPA_CLIENT_RTK_ETHERNET_CONS: + stats->wp = gsi_get_refetch_reg(ch_id, false); + stats->rp = gsi_get_refetch_reg(ch_id, true); + break; + + case IPA_CLIENT_AQC_ETHERNET_PROD: + stats->err = gsi_get_drop_stats(ipa_ep_idx, AQC_GSI_SCRATCH_ID, + ch_id); + stats->wp = gsi_get_wp(ch_id); + stats->rp = gsi_get_refetch_reg(ch_id, true); + break; + case IPA_CLIENT_AQC_ETHERNET_CONS: + stats->wp = gsi_get_refetch_reg(ch_id, false); + stats->rp = gsi_get_refetch_reg(ch_id, true); + break; + case IPA_CLIENT_ETHERNET_PROD: + stats->wp = gsi_get_refetch_reg(ch_id, false); + stats->rp = gsi_get_refetch_reg(ch_id, true); + break; + case IPA_CLIENT_ETHERNET_CONS: + stats->err = gsi_get_drop_stats(ipa_ep_idx, NTN_GSI_SCRATCH_ID, + ch_id); + stats->wp = gsi_get_refetch_reg(ch_id, false); + stats->rp = gsi_get_refetch_reg(ch_id, true); + break; + } + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); +} + +/** + * ipa3_get_max_pdn() - get max PDN number based on hardware version + * Returns: IPA_MAX_PDN_NUM of IPAv4_5 and IPA_MAX_PDN_NUM_v4 for others + * + */ + +int ipa3_get_max_pdn(void) +{ + size_t pdn_entry_size; + int max_pdn; + + ipahal_nat_entry_size(IPAHAL_NAT_IPV4_PDN, &pdn_entry_size); + max_pdn = IPA_MEM_PART(pdn_config_size)/pdn_entry_size; + IPADBG("IPA offload max_pdn = %d\n", max_pdn); + + return max_pdn; +} + +bool ipa3_is_modem_up(void) +{ + bool is_up; + + mutex_lock(&ipa3_ctx->ssr_lock); + is_up = ipa3_ctx->is_modem_up; + mutex_unlock(&ipa3_ctx->ssr_lock); + return is_up; +} + +void ipa3_set_modem_up(bool is_up) +{ + mutex_lock(&ipa3_ctx->ssr_lock); + ipa3_ctx->is_modem_up = is_up; + mutex_unlock(&ipa3_ctx->ssr_lock); +} + +/** + * ipa3_is_ulso_supported() - Query IPA for ulso support + * + * Return value: true if ulso is supported, false otherwise + * + */ +bool ipa3_is_ulso_supported(void) +{ + if (!ipa3_ctx) + return false; + + return ipa3_ctx->ulso_supported; +} +EXPORT_SYMBOL(ipa3_is_ulso_supported); + + + +/** + * ipa_hdrs_hpc_destroy() - remove the IPA headers hpc + * configuration done for the driver data path. + * @hdr_hdl: the hpc handle + * + * Remove the header addition hpc associated with hdr_hdl. + * + * Return value: 0 on success, kernel error code otherwise + */ +int ipa_hdrs_hpc_destroy(u32 hdr_hdl) +{ + struct ipa_ioc_del_hdr *del_wrapper; + struct ipa_hdr_del *hdr_del; + int result; + + del_wrapper = kzalloc(sizeof(*del_wrapper) + sizeof(*hdr_del), GFP_KERNEL); + if (!del_wrapper) + return -ENOMEM; + + del_wrapper->commit = 1; + del_wrapper->num_hdls = 1; + hdr_del = &del_wrapper->hdl[0]; + hdr_del->hdl = hdr_hdl; + + result = ipa3_del_hdr_hpc(del_wrapper); + if (result || hdr_del->status) + IPAERR("ipa_del_hdr failed\n"); + kfree(del_wrapper); + + return result; +} +EXPORT_SYMBOL(ipa_hdrs_hpc_destroy); + +/** + * qmap_encapsulate_skb() - encapsulate a given skb with a QMAP + * header + * @skb: the packet that will be encapsulated with QMAP header + * + * Return value: sk_buff encapsulated by a qmap header on + * success, Null otherwise. + */ +struct sk_buff* qmap_encapsulate_skb(struct sk_buff *skb, const struct qmap_hdr *qh) +{ + struct qmap_hdr *qh_ptr; + + if (unlikely(!qh)) + return NULL; + + /* if there is no room in this skb, allocate a new one */ + if (unlikely(skb_headroom(skb) < sizeof(*qh))) { + struct sk_buff *new_skb = skb_copy_expand(skb, sizeof(*qh), 0, GFP_ATOMIC); + + if (!new_skb) { + IPAERR("no memory for skb expand\n"); + return skb; + } + IPADBG("skb expanded. old %pK new %pK\n", skb, new_skb); + dev_kfree_skb_any(skb); + skb = new_skb; + } + + /* make room at the head of the SKB to put the QMAP header */ + qh_ptr = (struct qmap_hdr *)skb_push(skb, sizeof(*qh)); + *qh_ptr = *qh; + qh_ptr->packet_len_with_pad = htons(skb->len); + + return skb; +} +EXPORT_SYMBOL(qmap_encapsulate_skb); + +static void ipa3_eogre_info_free_cb( + void *buff, + u32 len, + u32 type) +{ + if (buff) { + kfree(buff); + } +} + +/** + * ipa3_check_eogre() - Check if the eogre is worthy of sending to + * recipients who would use the data. + * + * Returns: 0 on success, negative on failure + */ +int ipa3_check_eogre( + struct ipa_ioc_eogre_info *eogre_info, + bool *send2uC, + bool *send2ipacm ) +{ + struct ipa_ioc_eogre_info null_eogre; + + bool cache_is_null, eogre_is_null, same; + + int ret = 0; + + if (eogre_info == NULL || send2uC == NULL || send2ipacm == NULL) { + IPAERR("NULL ptr: eogre_info(%pK) and/or " + "send2uC(%pK) and/or send2ipacm(%pK)\n", + eogre_info, send2uC, send2ipacm); + ret = -EIO; + goto done; + } + + memset(&null_eogre, 0, sizeof(null_eogre)); + + cache_is_null = + !memcmp( + &ipa3_ctx->eogre_cache, + &null_eogre, + sizeof(null_eogre)); + + eogre_is_null = + !memcmp( + eogre_info, + &null_eogre, + sizeof(null_eogre)); + + *send2uC = *send2ipacm = false; + + if (cache_is_null) { + + if (eogre_is_null) { + IPAERR( + "Attempting to disable EoGRE. EoGRE is " + "already disabled. No work needs to be done.\n"); + ret = -EIO; + goto done; + } + + *send2uC = *send2ipacm = true; + + } else { /* (!cache_is_null) */ + + if (!eogre_is_null) { + IPAERR( + "EoGRE is already enabled for iptype(%d). " + "No work needs to be done.\n", + ipa3_ctx->eogre_cache.ipgre_info.iptype); + ret = -EIO; + goto done; + } + + same = !memcmp( + &ipa3_ctx->eogre_cache.map_info, + &eogre_info->map_info, + sizeof(struct IpaDscpVlanPcpMap_t)); + + *send2uC = !same; + + same = !memcmp( + &ipa3_ctx->eogre_cache.ipgre_info, + &eogre_info->ipgre_info, + sizeof(struct ipa_ipgre_info)); + + *send2ipacm = !same; + } + + ipa3_ctx->eogre_cache = *eogre_info; + + IPADBG("send2uC(%u) send2ipacm(%u)\n", + *send2uC, *send2ipacm); + +done: + return ret; +} + +/** + * ipa3_send_eogre_info() - Notify ipacm of incoming eogre event + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_send_eogre_info( + enum ipa_eogre_event etype, + struct ipa_ioc_eogre_info *info ) +{ + struct ipa_msg_meta msg_meta; + struct ipa_ipgre_info *eogre_info; + + int res = 0; + + if (!info) { + IPAERR("Bad arg: info is NULL\n"); + res = -EIO; + goto done; + } + + /* + * Prep and send msg to ipacm + */ + memset(&msg_meta, 0, sizeof(struct ipa_msg_meta)); + + eogre_info = kzalloc( + sizeof(struct ipa_ipgre_info), GFP_KERNEL); + + if (!eogre_info) { + IPAERR("eogre_info memory allocation failed !\n"); + res = -ENOMEM; + goto done; + } + + memcpy(eogre_info, + &(info->ipgre_info), + sizeof(struct ipa_ipgre_info)); + + msg_meta.msg_type = etype; + msg_meta.msg_len = sizeof(struct ipa_ipgre_info); + + /* + * Post event to ipacm + */ + res = ipa_send_msg(&msg_meta, eogre_info, ipa3_eogre_info_free_cb); + + if (res) { + IPAERR_RL("ipa_send_msg failed: %d\n", res); + kfree(eogre_info); + goto done; + } + +done: + return res; +} + +/* Send MHI endpoint info to modem using QMI indication message */ +int ipa_send_mhi_endp_ind_to_modem(void) +{ + struct ipa_endp_desc_indication_msg_v01 req; + struct ipa_ep_id_type_v01 *ep_info; + int ipa_mhi_prod_ep_idx = + ipa_get_ep_mapping(IPA_CLIENT_MHI_LOW_LAT_PROD); + int ipa_mhi_cons_ep_idx = + ipa_get_ep_mapping(IPA_CLIENT_MHI_LOW_LAT_CONS); + + mutex_lock(&ipa3_ctx->lock); + /* only modem up and MHI ctrl pipes are ready, then send QMI*/ + if (!ipa3_ctx->is_modem_up || + ipa3_ctx->mhi_ctrl_state != IPA_MHI_CTRL_SETUP_ALL) { + mutex_unlock(&ipa3_ctx->lock); + return 0; + } + mutex_unlock(&ipa3_ctx->lock); + + IPADBG("Sending MHI end point indication to modem\n"); + memset(&req, 0, sizeof(struct ipa_endp_desc_indication_msg_v01)); + req.ep_info_len = 2; + req.ep_info_valid = true; + req.num_eps_valid = true; + req.num_eps = 2; + ep_info = &req.ep_info[0]; + ep_info->ep_id = ipa_mhi_cons_ep_idx; + ep_info->ic_type = DATA_IC_TYPE_MHI_V01; + ep_info->ep_type = DATA_EP_DESC_TYPE_EMB_FLOW_CTL_PROD_V01; + ep_info->ep_status = DATA_EP_STATUS_CONNECTED_V01; + ep_info = &req.ep_info[1]; + ep_info->ep_id = ipa_mhi_prod_ep_idx; + ep_info->ic_type = DATA_IC_TYPE_MHI_V01; + ep_info->ep_type = DATA_EP_DESC_TYPE_EMB_FLOW_CTL_CONS_V01; + ep_info->ep_status = DATA_EP_STATUS_CONNECTED_V01; + return ipa3_qmi_send_endp_desc_indication(&req); +} + +void ipa3_update_mhi_ctrl_state(u8 state, bool set) +{ + mutex_lock(&ipa3_ctx->lock); + if (set) + ipa3_ctx->mhi_ctrl_state |= state; + else + ipa3_ctx->mhi_ctrl_state &= ~state; + mutex_unlock(&ipa3_ctx->lock); + ipa_send_mhi_endp_ind_to_modem(); +} +EXPORT_SYMBOL(ipa3_update_mhi_ctrl_state); + +/** + * ipa3_setup_uc_act_tbl() - IPA setup uc_act_tbl + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa3_setup_uc_act_tbl(void) +{ + int res = 0; + struct ipa_mem_buffer *tbl; + struct ipahal_reg_nat_uc_external_cfg nat_ex_cfg; + struct ipahal_reg_nat_uc_shared_cfg nat_share_cfg; + struct ipahal_reg_conn_track_uc_external_cfg ct_ex_cfg; + struct ipahal_reg_conn_track_uc_shared_cfg ct_share_cfg; + + /* IPA version check */ + if (ipa3_ctx->ipa_hw_type < IPA_HW_v4_5) { + IPAERR("Not support!\n"); + return -EPERM; + } + + if (ipa3_ctx->uc_act_tbl_valid) { + IPAERR(" already allocate uC act tbl\n"); + return -EEXIST; + } + + tbl = &ipa3_ctx->uc_act_tbl; + /* Allocate uc act tbl */ + tbl->size = sizeof(struct ipa_socksv5_uc_tmpl) * IPA_UC_ACT_TBL_SIZE; + tbl->base = dma_alloc_coherent(ipa3_ctx->pdev, tbl->size, + &tbl->phys_base, GFP_KERNEL); + if (tbl->base == NULL) + return -ENOMEM; + memset(tbl->base, 0, tbl->size); + + ipa3_ctx->uc_act_tbl_valid = true; + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + + /* LSB 32 bits*/ + nat_ex_cfg.nat_uc_external_table_addr_lsb = + (u32) (tbl->phys_base & 0xFFFFFFFF); + ipahal_write_reg_fields(IPA_NAT_UC_EXTERNAL_CFG, &nat_ex_cfg); + /* MSB 16 bits */ + nat_share_cfg.nat_uc_external_table_addr_msb = + (u16) (((tbl->phys_base & 0xFFFFFFFF00000000) >> 32) & 0xFFFF); + ipahal_write_reg_fields(IPA_NAT_UC_SHARED_CFG, &nat_share_cfg); + + /* LSB 32 bits*/ + ct_ex_cfg.conn_track_uc_external_table_addr_lsb = + (u32) (tbl->phys_base & 0xFFFFFFFF); + + ipahal_write_reg_fields(IPA_CONN_TRACK_UC_EXTERNAL_CFG, &ct_ex_cfg); + /* MSB 16 bits */ + ct_share_cfg.conn_track_uc_external_table_addr_msb = + (u16) (((tbl->phys_base & 0xFFFFFFFF00000000) >> 32) & 0xFFFF); + ipahal_write_reg_fields(IPA_CONN_TRACK_UC_SHARED_CFG, &ct_share_cfg); + + + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + return res; +} + +static void ipa3_socksv5_msg_free_cb(void *buff, u32 len, u32 type) +{ + if (!buff) { + IPAERR("Null buffer\n"); + return; + } + + if (type != IPA_SOCKV5_ADD && + type != IPA_SOCKV5_DEL) { + IPAERR("Wrong type given. buff %pK type %d\n", buff, type); + kfree(buff); + return; + } + + kfree(buff); +} + +/** + * ipa_add_socksv5_conn() - IPA add socksv5_conn + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa_add_socksv5_conn(struct ipa_socksv5_info *info) +{ + int res = 0; + void *rp_va, *wp_va; + struct ipa_socksv5_msg *socksv5_msg; + struct ipa_msg_meta msg_meta; + + /* IPA version check */ + if (ipa3_ctx->ipa_hw_type < IPA_HW_v4_5) { + IPAERR("Not support !\n"); + return -EPERM; + } + + if (!ipa3_ctx->uc_act_tbl_valid) { + IPAERR("uC act tbl haven't allocated\n"); + return -ENOENT; + } + + if (!info) { + IPAERR("Null info\n"); + return -EIO; + } + + mutex_lock(&ipa3_ctx->act_tbl_lock); + /* check the left # of entries */ + if (ipa3_ctx->uc_act_tbl_total + >= IPA_UC_ACT_TBL_SIZE) { + IPAERR("uc act tbl is full!\n"); + res = -EFAULT; + goto error; + } + + /* Copied the act-info to tbl */ + wp_va = ipa3_ctx->uc_act_tbl.base + + ipa3_ctx->uc_act_tbl_next_index + * sizeof(struct ipa_socksv5_uc_tmpl); + + /* check entry valid */ + if ((info->ul_out.cmd_id != IPA_SOCKsv5_ADD_COM_ID) + || (info->dl_out.cmd_id != IPA_SOCKsv5_ADD_COM_ID)) { + IPAERR("cmd_id not set UL%d DL%d!\n", + info->ul_out.cmd_id, + info->dl_out.cmd_id); + res = -EINVAL; + goto error; + } + + if ((info->ul_out.cmd_param < IPA_SOCKsv5_ADD_V6_V4_COM_PM) + || (info->ul_out.cmd_param > IPA_SOCKsv5_ADD_V6_V6_COM_PM)) { + IPAERR("ul cmd_param is not support%d!\n", + info->ul_out.cmd_param); + res = -EINVAL; + goto error; + } + + if ((info->dl_out.cmd_param < IPA_SOCKsv5_ADD_V6_V4_COM_PM) + || (info->dl_out.cmd_param > IPA_SOCKsv5_ADD_V6_V6_COM_PM)) { + IPAERR("dl cmd_param is not support%d!\n", + info->dl_out.cmd_param); + res = -EINVAL; + goto error; + } + + /* indicate entry valid */ + info->ul_out.ipa_sockv5_mask |= IPA_SOCKSv5_ENTRY_VALID; + info->dl_out.ipa_sockv5_mask |= IPA_SOCKSv5_ENTRY_VALID; + + memcpy(wp_va, &(info->ul_out), sizeof(info->ul_out)); + memcpy(wp_va + sizeof(struct ipa_socksv5_uc_tmpl), + &(info->dl_out), sizeof(info->dl_out)); + + /* set output handle */ + info->handle = (uint16_t) ipa3_ctx->uc_act_tbl_next_index; + + ipa3_ctx->uc_act_tbl_total += 2; + + /* send msg to ipacm */ + socksv5_msg = kzalloc(sizeof(*socksv5_msg), GFP_KERNEL); + if (!socksv5_msg) { + IPAERR("socksv5_msg memory allocation failed !\n"); + res = -ENOMEM; + goto error; + } + memcpy(&(socksv5_msg->ul_in), &(info->ul_in), sizeof(info->ul_in)); + memcpy(&(socksv5_msg->dl_in), &(info->dl_in), sizeof(info->dl_in)); + socksv5_msg->handle = info->handle; + socksv5_msg->ul_in.index = + (uint16_t) ipa3_ctx->uc_act_tbl_next_index; + socksv5_msg->dl_in.index = + (uint16_t) ipa3_ctx->uc_act_tbl_next_index + 1; + + memset(&msg_meta, 0, sizeof(struct ipa_msg_meta)); + msg_meta.msg_type = IPA_SOCKV5_ADD; + msg_meta.msg_len = sizeof(struct ipa_socksv5_msg); + /* post event to ipacm*/ + res = ipa_send_msg(&msg_meta, socksv5_msg, ipa3_socksv5_msg_free_cb); + if (res) { + IPAERR_RL("ipa_send_msg failed: %d\n", res); + kfree(socksv5_msg); + goto error; + } + + if (ipa3_ctx->uc_act_tbl_total < IPA_UC_ACT_TBL_SIZE) { + /* find next free spot */ + do { + ipa3_ctx->uc_act_tbl_next_index += 2; + ipa3_ctx->uc_act_tbl_next_index %= + IPA_UC_ACT_TBL_SIZE; + + rp_va = ipa3_ctx->uc_act_tbl.base + + ipa3_ctx->uc_act_tbl_next_index + * sizeof(struct ipa_socksv5_uc_tmpl); + + if (!((((struct ipa_socksv5_uc_tmpl *) rp_va)-> + ipa_sockv5_mask) & IPA_SOCKSv5_ENTRY_VALID)) { + IPADBG("next available entry %d, total %d\n", + ipa3_ctx->uc_act_tbl_next_index, + ipa3_ctx->uc_act_tbl_total); + break; + } + } while (rp_va != wp_va); + + if (rp_va == wp_va) { + /* set to max tbl size to debug */ + IPAERR("can't find available spot!\n"); + ipa3_ctx->uc_act_tbl_total = IPA_UC_ACT_TBL_SIZE; + res = -EFAULT; + } + } + +error: + mutex_unlock(&ipa3_ctx->act_tbl_lock); + return res; +} + +void ipa3_default_evict_register( void ) +{ + struct ipahal_reg_coal_evict_lru evict_lru; + + if ( ipa3_ctx->ipa_hw_type >= IPA_HW_v4_5 + && + ipa3_ctx->set_evict_reg == false ) + { + ipa3_ctx->set_evict_reg = true; + + IPADBG("Setting COAL eviction register with default values\n"); + + ipa3_get_default_evict_values(&evict_lru); + + ipahal_write_reg_fields(IPA_COAL_EVICT_LRU, &evict_lru); + } +} + +/** + * ipa_del_socksv5_conn() - IPA add socksv5_conn + * + * Returns: 0 on success, negative on failure + * + * Note: Should not be called from atomic context + */ +int ipa_del_socksv5_conn(uint32_t handle) +{ + int res = 0; + void *rp_va; + uint32_t *socksv5_handle; + struct ipa_msg_meta msg_meta; + + /* IPA version check */ + if (ipa3_ctx->ipa_hw_type < IPA_HW_v4_5) { + IPAERR("Not support !\n"); + return -EPERM; + } + + if (!ipa3_ctx->uc_act_tbl_valid) { + IPAERR("uC act tbl haven't allocated\n"); + return -ENOENT; + } + + if (handle > IPA_UC_ACT_TBL_SIZE || handle < 0) { + IPAERR("invalid handle!\n"); + return -EINVAL; + } + + if ((handle % 2) != 0) { + IPAERR("invalid handle!\n"); + return -EINVAL; + } + + if (ipa3_ctx->uc_act_tbl_total < 2) { + IPAERR("invalid handle, all tbl is empty!\n"); + return -EINVAL; + } + + rp_va = ipa3_ctx->uc_act_tbl.base + + handle * sizeof(struct ipa_socksv5_uc_tmpl); + + /* check entry is valid or not */ + mutex_lock(&ipa3_ctx->act_tbl_lock); + if (!((((struct ipa_socksv5_uc_tmpl *) rp_va)-> + ipa_sockv5_mask) & IPA_SOCKSv5_ENTRY_VALID)) { + IPADBG(" entry %d already free\n", handle); + } + + if (!((((struct ipa_socksv5_uc_tmpl *) (rp_va + + sizeof(struct ipa_socksv5_uc_tmpl)))-> + ipa_sockv5_mask) & IPA_SOCKSv5_ENTRY_VALID)) { + IPADBG(" entry %d already free\n", handle); + } + + ((struct ipa_socksv5_uc_tmpl *) rp_va)->ipa_sockv5_mask + &= ~IPA_SOCKSv5_ENTRY_VALID; + ((struct ipa_socksv5_uc_tmpl *) (rp_va + + sizeof(struct ipa_socksv5_uc_tmpl)))->ipa_sockv5_mask + &= ~IPA_SOCKSv5_ENTRY_VALID; + ipa3_ctx->uc_act_tbl_total -= 2; + + IPADBG("free entry %d and %d, left total %d\n", + handle, + handle + 1, + ipa3_ctx->uc_act_tbl_total); + + /* send msg to ipacm */ + socksv5_handle = kzalloc(sizeof(*socksv5_handle), GFP_KERNEL); + if (!socksv5_handle) { + IPAERR("socksv5_handle memory allocation failed!\n"); + res = -ENOMEM; + goto error; + } + memcpy(socksv5_handle, &handle, sizeof(handle)); + msg_meta.msg_type = IPA_SOCKV5_DEL; + msg_meta.msg_len = sizeof(uint32_t); + res = ipa_send_msg(&msg_meta, socksv5_handle, + ipa3_socksv5_msg_free_cb); + if (res) { + IPAERR_RL("ipa_send_msg failed: %d\n", res); + kfree(socksv5_handle); + } + +error: + mutex_unlock(&ipa3_ctx->act_tbl_lock); + return res; +} diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_wdi3_i.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_wdi3_i.c new file mode 100644 index 0000000000..ddb09b2365 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_wdi3_i.c @@ -0,0 +1,1502 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2018 - 2021, The Linux Foundation. All rights reserved. + * + * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ipa_i.h" +#include "ipa_wdi3.h" + +#define UPDATE_RP_MODERATION_CONFIG 1 +#define UPDATE_RP_MODERATION_THRESHOLD 8 +#define UPDATE_RP_MODERATION_THRESHOLD_OPT_DP 1 + + +#define IPA_WLAN_AGGR_PKT_LIMIT 1 +#define IPA_WLAN_AGGR_BYTE_LIMIT 2 /*2 Kbytes Agger hard byte limit*/ + +#define IPA_WDI3_GSI_EVT_RING_INT_MODT 32 +#define IPA_WDI3_MAX_VALUE_OF_BANK_ID 63 + +static void ipa3_wdi3_gsi_evt_ring_err_cb(struct gsi_evt_err_notify *notify) +{ + switch (notify->evt_id) { + case GSI_EVT_OUT_OF_BUFFERS_ERR: + IPAERR("Got GSI_EVT_OUT_OF_BUFFERS_ERR\n"); + break; + case GSI_EVT_OUT_OF_RESOURCES_ERR: + IPAERR("Got GSI_EVT_OUT_OF_RESOURCES_ERR\n"); + break; + case GSI_EVT_UNSUPPORTED_INTER_EE_OP_ERR: + IPAERR("Got GSI_EVT_UNSUPPORTED_INTER_EE_OP_ERR\n"); + break; + case GSI_EVT_EVT_RING_EMPTY_ERR: + IPAERR("Got GSI_EVT_EVT_RING_EMPTY_ERR\n"); + break; + default: + IPAERR("Unexpected err evt: %d\n", notify->evt_id); + } + ipa_assert(); +} + +static void ipa3_wdi3_gsi_chan_err_cb(struct gsi_chan_err_notify *notify) +{ + switch (notify->evt_id) { + case GSI_CHAN_INVALID_TRE_ERR: + IPAERR("Got GSI_CHAN_INVALID_TRE_ERR\n"); + break; + case GSI_CHAN_NON_ALLOCATED_EVT_ACCESS_ERR: + IPAERR("Got GSI_CHAN_NON_ALLOCATED_EVT_ACCESS_ERR\n"); + break; + case GSI_CHAN_OUT_OF_BUFFERS_ERR: + IPAERR("Got GSI_CHAN_OUT_OF_BUFFERS_ERR\n"); + break; + case GSI_CHAN_OUT_OF_RESOURCES_ERR: + IPAERR("Got GSI_CHAN_OUT_OF_RESOURCES_ERR\n"); + break; + case GSI_CHAN_UNSUPPORTED_INTER_EE_OP_ERR: + IPAERR("Got GSI_CHAN_UNSUPPORTED_INTER_EE_OP_ERR\n"); + break; + case GSI_CHAN_HWO_1_ERR: + IPAERR("Got GSI_CHAN_HWO_1_ERR\n"); + break; + default: + IPAERR("Unexpected err evt: %d\n", notify->evt_id); + } + ipa_assert(); +} + +static int ipa3_setup_wdi3_gsi_channel(u8 is_smmu_enabled, + struct ipa_wdi_pipe_setup_info *info, + struct ipa_wdi_pipe_setup_info_smmu *info_smmu, u8 dir, + struct ipa3_ep_context *ep) +{ + struct gsi_evt_ring_props gsi_evt_ring_props; + struct gsi_chan_props gsi_channel_props; + union __packed gsi_channel_scratch ch_scratch; + union __packed gsi_evt_scratch evt_scratch; + const struct ipa_gsi_ep_config *gsi_ep_info; + int result, len; + unsigned long va; + uint32_t addr_low, addr_high; + + if (!info || !info_smmu || !ep) { + IPAERR("invalid input\n"); + return -EINVAL; + } + memset(&gsi_evt_ring_props, 0, sizeof(gsi_evt_ring_props)); + memset(&gsi_channel_props, 0, sizeof(gsi_channel_props)); + + if(ipa_get_wdi_version() == IPA_WDI_3_V2) { + gsi_channel_props.prot = GSI_CHAN_PROT_WDI3_V2; + gsi_evt_ring_props.intf = GSI_EVT_CHTYPE_WDI3_V2_EV; + } + else { + gsi_channel_props.prot = GSI_CHAN_PROT_WDI3; + gsi_evt_ring_props.intf = GSI_EVT_CHTYPE_WDI3_EV; + } + + /* setup event ring */ + + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_9) { + gsi_evt_ring_props.intr = GSI_INTR_MSI; + /* 32 (for Tx) and 8 (for Rx) */ + if ((dir == IPA_WDI3_TX_DIR) || (dir == IPA_WDI3_TX1_DIR) || + (dir == IPA_WDI3_TX2_DIR)) + gsi_evt_ring_props.re_size = GSI_EVT_RING_RE_SIZE_32B; + else + gsi_evt_ring_props.re_size = GSI_EVT_RING_RE_SIZE_8B; + } else { + gsi_evt_ring_props.intr = GSI_INTR_IRQ; + /* 16 (for Tx) and 8 (for Rx) */ + if ((dir == IPA_WDI3_TX_DIR) || (dir == IPA_WDI3_TX1_DIR) || + (dir == IPA_WDI3_TX2_DIR)) + gsi_evt_ring_props.re_size = GSI_EVT_RING_RE_SIZE_16B; + else + gsi_evt_ring_props.re_size = GSI_EVT_RING_RE_SIZE_8B; + } + if (!is_smmu_enabled) { + gsi_evt_ring_props.ring_len = info->event_ring_size; + gsi_evt_ring_props.ring_base_addr = + (u64)info->event_ring_base_pa; + } else { + len = info_smmu->event_ring_size; + if ((dir == IPA_WDI3_TX_DIR) || (dir == IPA_WDI3_TX1_DIR)) { + if (ipa_create_gsi_smmu_mapping(( + dir == IPA_WDI3_TX_DIR) ? + IPA_WDI_CE_RING_RES : IPA_WDI_CE1_RING_RES, + true, info->event_ring_base_pa, + &info_smmu->event_ring_base, len, + false, &va)) { + IPAERR("failed to get smmu mapping\n"); + return -EFAULT; + } + } else if (dir == IPA_WDI3_TX2_DIR) { + if (ipa_create_gsi_smmu_mapping( + IPA_WDI_CE2_RING_RES, + true, info->event_ring_base_pa, + &info_smmu->event_ring_base, len, + false, &va)) { + IPAERR("failed to get smmu mapping\n"); + return -EFAULT; + } + } else if (dir == IPA_WDI3_RX_DIR) { + if (ipa_create_gsi_smmu_mapping( + IPA_WDI_RX_COMP_RING_RES, true, + info->event_ring_base_pa, + &info_smmu->event_ring_base, len, + false, &va)) { + IPAERR("failed to get smmu mapping\n"); + return -EFAULT; + } + } else { + if (ipa_create_gsi_smmu_mapping( + IPA_WDI_RX2_COMP_RING_RES, true, + info->event_ring_base_pa, + &info_smmu->event_ring_base, len, + false, &va)) { + IPAERR("failed to get smmu mapping\n"); + return -EFAULT; + } + } + gsi_evt_ring_props.ring_len = len; + gsi_evt_ring_props.ring_base_addr = (u64)va; + } + gsi_evt_ring_props.int_modt = IPA_WDI3_GSI_EVT_RING_INT_MODT; + gsi_evt_ring_props.int_modc = 1; + gsi_evt_ring_props.exclusive = true; + gsi_evt_ring_props.err_cb = ipa3_wdi3_gsi_evt_ring_err_cb; + gsi_evt_ring_props.user_data = NULL; + + result = gsi_alloc_evt_ring(&gsi_evt_ring_props, ipa3_ctx->gsi_dev_hdl, + &ep->gsi_evt_ring_hdl); + if (result != GSI_STATUS_SUCCESS) { + IPAERR("fail to alloc RX event ring\n"); + result = -EFAULT; + goto fail_smmu_mapping; + } + + ep->gsi_mem_info.evt_ring_len = gsi_evt_ring_props.ring_len; + ep->gsi_mem_info.evt_ring_base_addr = + gsi_evt_ring_props.ring_base_addr; + + /* setup channel ring */ + if ((dir == IPA_WDI3_TX_DIR) || (dir == IPA_WDI3_TX1_DIR) || + (dir == IPA_WDI3_TX2_DIR)) + gsi_channel_props.dir = GSI_CHAN_DIR_FROM_GSI; + else + gsi_channel_props.dir = GSI_CHAN_DIR_TO_GSI; + + gsi_ep_info = ipa_get_gsi_ep_info(ep->client); + if (!gsi_ep_info) { + IPAERR("Failed getting GSI EP info for client=%d\n", + ep->client); + result = -EINVAL; + goto fail_get_gsi_ep_info; + } else + gsi_channel_props.ch_id = gsi_ep_info->ipa_gsi_chan_num; + + gsi_channel_props.db_in_bytes = 0; + gsi_channel_props.evt_ring_hdl = ep->gsi_evt_ring_hdl; + + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_9) { + /* 32 (for Tx) and 64 (for Rx) */ + if ((dir == IPA_WDI3_TX_DIR) || (dir == IPA_WDI3_TX1_DIR) || + (dir == IPA_WDI3_TX2_DIR)) + gsi_channel_props.re_size = GSI_CHAN_RE_SIZE_32B; + else { + if (gsi_channel_props.prot == GSI_CHAN_PROT_WDI3_V2) + gsi_channel_props.re_size = GSI_CHAN_RE_SIZE_32B; + else + gsi_channel_props.re_size = GSI_CHAN_RE_SIZE_64B; + } + + } else + gsi_channel_props.re_size = GSI_CHAN_RE_SIZE_16B; + + gsi_channel_props.use_db_eng = GSI_CHAN_DB_MODE; + gsi_channel_props.max_prefetch = GSI_ONE_PREFETCH_SEG; + gsi_channel_props.prefetch_mode = + gsi_ep_info->prefetch_mode; + gsi_channel_props.empty_lvl_threshold = + gsi_ep_info->prefetch_threshold; + gsi_channel_props.low_weight = 1; + gsi_channel_props.err_cb = ipa3_wdi3_gsi_chan_err_cb; + + if (!is_smmu_enabled) { + gsi_channel_props.ring_len = (u16)info->transfer_ring_size; + gsi_channel_props.ring_base_addr = + (u64)info->transfer_ring_base_pa; + } else { + len = info_smmu->transfer_ring_size; + if ((dir == IPA_WDI3_TX_DIR) || (dir == IPA_WDI3_TX1_DIR)) { + if (ipa_create_gsi_smmu_mapping(( + dir == IPA_WDI3_TX_DIR) ? + IPA_WDI_TX_RING_RES : IPA_WDI_TX1_RING_RES, + true, info->transfer_ring_base_pa, + &info_smmu->transfer_ring_base, len, + false, &va)) { + IPAERR("failed to get smmu mapping\n"); + result = -EFAULT; + goto fail_get_gsi_ep_info; + } + } else if (dir == IPA_WDI3_TX2_DIR) { + if (ipa_create_gsi_smmu_mapping( + IPA_WDI_TX2_RING_RES, + true, info->transfer_ring_base_pa, + &info_smmu->transfer_ring_base, len, + false, &va)) { + IPAERR("failed to get smmu mapping\n"); + result = -EFAULT; + goto fail_get_gsi_ep_info; + } + } else if (dir == IPA_WDI3_RX_DIR) { + if (ipa_create_gsi_smmu_mapping( + IPA_WDI_RX_RING_RES, true, + info->transfer_ring_base_pa, + &info_smmu->transfer_ring_base, len, + false, &va)) { + IPAERR("failed to get smmu mapping\n"); + result = -EFAULT; + goto fail_get_gsi_ep_info; + } + } else { + if (ipa_create_gsi_smmu_mapping( + IPA_WDI_RX2_RING_RES, true, + info->transfer_ring_base_pa, + &info_smmu->transfer_ring_base, len, + false, &va)) { + IPAERR("failed to get smmu mapping\n"); + result = -EFAULT; + goto fail_get_gsi_ep_info; + } + } + gsi_channel_props.ring_len = len; + gsi_channel_props.ring_base_addr = (u64)va; + } + + result = gsi_alloc_channel(&gsi_channel_props, ipa3_ctx->gsi_dev_hdl, + &ep->gsi_chan_hdl); + if (result != GSI_STATUS_SUCCESS) + goto fail_get_gsi_ep_info; + + ep->gsi_mem_info.chan_ring_len = gsi_channel_props.ring_len; + ep->gsi_mem_info.chan_ring_base_addr = + gsi_channel_props.ring_base_addr; + + /* write event scratch */ + memset(&evt_scratch, 0, sizeof(evt_scratch)); + evt_scratch.wdi3.update_rp_moderation_config = + UPDATE_RP_MODERATION_CONFIG; + result = gsi_write_evt_ring_scratch(ep->gsi_evt_ring_hdl, evt_scratch); + if (result != GSI_STATUS_SUCCESS) { + IPAERR("failed to write evt ring scratch\n"); + goto fail_write_scratch; + } + + if (!is_smmu_enabled) { + IPADBG("smmu disabled\n"); + if (info->is_evt_rn_db_pcie_addr == true) + IPADBG_LOW("is_evt_rn_db_pcie_addr is PCIE addr\n"); + else + IPADBG_LOW("is_evt_rn_db_pcie_addr is DDR addr\n"); + IPADBG_LOW("LSB 0x%x\n", + (u32)info->event_ring_doorbell_pa); + IPADBG_LOW("MSB 0x%x\n", + (u32)((u64)info->event_ring_doorbell_pa >> 32)); + } else { + IPADBG("smmu enabled\n"); + if (info_smmu->is_evt_rn_db_pcie_addr == true) + IPADBG_LOW("is_evt_rn_db_pcie_addr is PCIE addr\n"); + else + IPADBG_LOW("is_evt_rn_db_pcie_addr is DDR addr\n"); + IPADBG_LOW("LSB 0x%x\n", + (u32)info_smmu->event_ring_doorbell_pa); + IPADBG_LOW("MSB 0x%x\n", + (u32)((u64)info_smmu->event_ring_doorbell_pa >> 32)); + } + + if (!is_smmu_enabled) { + addr_low = (u32)info->event_ring_doorbell_pa; + addr_high = (u32)((u64)info->event_ring_doorbell_pa >> 32); + } else { + if ((dir == IPA_WDI3_TX_DIR) || (dir == IPA_WDI3_TX1_DIR)) { + if (ipa_create_gsi_smmu_mapping(( + dir == IPA_WDI3_TX_DIR) ? + IPA_WDI_CE_DB_RES : IPA_WDI_CE1_DB_RES, + true, info_smmu->event_ring_doorbell_pa, + NULL, 4, true, &va)) { + IPAERR("failed to get smmu mapping\n"); + result = -EFAULT; + goto fail_write_scratch; + } + } else if (dir == IPA_WDI3_TX2_DIR) { + if (ipa_create_gsi_smmu_mapping( + IPA_WDI_CE2_DB_RES, + true, info_smmu->event_ring_doorbell_pa, + NULL, 4, true, &va)) { + IPAERR("failed to get smmu mapping\n"); + result = -EFAULT; + goto fail_write_scratch; + } + } else if (dir == IPA_WDI3_RX_DIR) { + if (ipa_create_gsi_smmu_mapping( + IPA_WDI_RX_COMP_RING_WP_RES, + true, info_smmu->event_ring_doorbell_pa, + NULL, 4, true, &va)) { + IPAERR("failed to get smmu mapping\n"); + result = -EFAULT; + goto fail_write_scratch; + } + } else { + if (ipa_create_gsi_smmu_mapping( + IPA_WDI_RX2_COMP_RING_WP_RES, + true, info_smmu->event_ring_doorbell_pa, + NULL, 4, true, &va)) { + IPAERR("failed to get smmu mapping\n"); + result = -EFAULT; + goto fail_write_scratch; + } + } + addr_low = (u32)va; + addr_high = (u32)((u64)va >> 32); + } + + /* + * Arch specific: + * pcie addr which are not via smmu, use pa directly! + * pcie and DDR via 2 different port + * assert bit 40 to indicate it is pcie addr + * WDI-3.0, MSM --> pcie via smmu + * WDI-3.0, MDM --> pcie not via smmu + dual port + * assert bit 40 in case + */ + if ((ipa3_ctx->platform_type == IPA_PLAT_TYPE_MDM) && + is_smmu_enabled) { + /* + * Ir-respective of smmu enabled don't use IOVA addr + * since pcie not via smmu in MDM's + */ + if (info_smmu->is_evt_rn_db_pcie_addr == true) { + addr_low = (u32)info_smmu->event_ring_doorbell_pa; + addr_high = + (u32)((u64)info_smmu->event_ring_doorbell_pa + >> 32); + } + } + + /* + * GSI recomendation to set bit-40 for (mdm targets && pcie addr) + * from wdi-3.0 interface document + */ + if (!is_smmu_enabled) { + if ((ipa3_ctx->platform_type == IPA_PLAT_TYPE_MDM) && + info->is_evt_rn_db_pcie_addr) + addr_high |= (1 << 8); + } else { + if ((ipa3_ctx->platform_type == IPA_PLAT_TYPE_MDM) && + info_smmu->is_evt_rn_db_pcie_addr) + addr_high |= (1 << 8); + } + + gsi_wdi3_write_evt_ring_db(ep->gsi_evt_ring_hdl, + addr_low, + addr_high); + + /* write channel scratch */ + memset(&ch_scratch, 0, sizeof(ch_scratch)); + ch_scratch.wdi3.update_rp_moderation_threshold = + (ipa3_ctx->ipa_wdi_opt_dpath) ? + UPDATE_RP_MODERATION_THRESHOLD_OPT_DP : + UPDATE_RP_MODERATION_THRESHOLD; + if ((dir == IPA_WDI3_RX_DIR) || (dir == IPA_WDI3_RX2_DIR)) { + if (!is_smmu_enabled) + ch_scratch.wdi3.rx_pkt_offset = info->pkt_offset; + else + ch_scratch.wdi3.rx_pkt_offset = info_smmu->pkt_offset; + /* this metadata reg offset need to be in words */ + ch_scratch.wdi3.endp_metadata_reg_offset = + ipahal_get_reg_mn_ofst(IPA_ENDP_INIT_HDR_METADATA_n, 0, + gsi_ep_info->ipa_ep_num) / 4; + } + + if (!is_smmu_enabled) { + IPADBG_LOW("smmu disabled\n"); + if (info->is_txr_rn_db_pcie_addr == true) + IPADBG_LOW("is_txr_rn_db_pcie_addr is PCIE addr\n"); + else + IPADBG_LOW("is_txr_rn_db_pcie_addr is DDR addr\n"); + IPADBG_LOW("LSB 0x%x\n", + (u32)info->transfer_ring_doorbell_pa); + IPADBG_LOW("MSB 0x%x\n", + (u32)((u64)info->transfer_ring_doorbell_pa >> 32)); + } else { + IPADBG_LOW("smmu eabled\n"); + if (info_smmu->is_txr_rn_db_pcie_addr == true) + IPADBG_LOW("is_txr_rn_db_pcie_addr is PCIE addr\n"); + else + IPADBG_LOW("is_txr_rn_db_pcie_addr is DDR addr\n"); + IPADBG_LOW("LSB 0x%x\n", + (u32)info_smmu->transfer_ring_doorbell_pa); + IPADBG_LOW("MSB 0x%x\n", + (u32)((u64)info_smmu->transfer_ring_doorbell_pa >> 32)); + } + + if (!is_smmu_enabled) { + ch_scratch.wdi3.wifi_rp_address_low = + (u32)info->transfer_ring_doorbell_pa; + ch_scratch.wdi3.wifi_rp_address_high = + (u32)((u64)info->transfer_ring_doorbell_pa >> 32); + } else { + if ((dir == IPA_WDI3_TX_DIR) || (dir == IPA_WDI3_TX1_DIR)) { + if (ipa_create_gsi_smmu_mapping(( + dir == IPA_WDI3_TX_DIR) ? + IPA_WDI_TX_DB_RES : IPA_WDI_TX1_DB_RES, + true, info_smmu->transfer_ring_doorbell_pa, + NULL, 4, true, &va)) { + IPAERR("failed to get smmu mapping\n"); + result = -EFAULT; + goto fail_write_scratch; + } + ch_scratch.wdi3.wifi_rp_address_low = (u32)va; + ch_scratch.wdi3.wifi_rp_address_high = + (u32)((u64)va >> 32); + } else if (dir == IPA_WDI3_TX2_DIR) { + if (ipa_create_gsi_smmu_mapping( + IPA_WDI_TX2_DB_RES, + true, info_smmu->transfer_ring_doorbell_pa, + NULL, 4, true, &va)) { + IPAERR("failed to get smmu mapping\n"); + result = -EFAULT; + goto fail_write_scratch; + } + ch_scratch.wdi3.wifi_rp_address_low = (u32)va; + ch_scratch.wdi3.wifi_rp_address_high = + (u32)((u64)va >> 32); + } else if (dir == IPA_WDI3_RX_DIR){ + if (ipa_create_gsi_smmu_mapping(IPA_WDI_RX_RING_RP_RES, + true, info_smmu->transfer_ring_doorbell_pa, + NULL, 4, true, &va)) { + IPAERR("failed to get smmu mapping\n"); + result = -EFAULT; + goto fail_write_scratch; + } + ch_scratch.wdi3.wifi_rp_address_low = (u32)va; + ch_scratch.wdi3.wifi_rp_address_high = + (u32)((u64)va >> 32); + } else { + if (ipa_create_gsi_smmu_mapping(IPA_WDI_RX2_RING_RP_RES, + true, info_smmu->transfer_ring_doorbell_pa, + NULL, 4, true, &va)) { + IPAERR("failed to get smmu mapping\n"); + result = -EFAULT; + goto fail_write_scratch; + } + ch_scratch.wdi3.wifi_rp_address_low = (u32)va; + ch_scratch.wdi3.wifi_rp_address_high = + (u32)((u64)va >> 32); + } + } + + /* + * Arch specific: + * pcie addr which are not via smmu, use pa directly! + * pcie and DDR via 2 different port + * assert bit 40 to indicate it is pcie addr + * WDI-3.0, MSM --> pcie via smmu + * WDI-3.0, MDM --> pcie not via smmu + dual port + * assert bit 40 in case + */ + if ((ipa3_ctx->platform_type == IPA_PLAT_TYPE_MDM) && + is_smmu_enabled) { + /* + * Ir-respective of smmu enabled don't use IOVA addr + * since pcie not via smmu in MDM's + */ + if (info_smmu->is_txr_rn_db_pcie_addr == true) { + ch_scratch.wdi3.wifi_rp_address_low = + (u32)info_smmu->transfer_ring_doorbell_pa; + ch_scratch.wdi3.wifi_rp_address_high = + (u32)((u64)info_smmu->transfer_ring_doorbell_pa + >> 32); + } + } + + /* + * GSI recomendation to set bit-40 for (mdm targets && pcie addr) + * from wdi-3.0 interface document + */ + if (!is_smmu_enabled) { + if ((ipa3_ctx->platform_type == IPA_PLAT_TYPE_MDM) && + info->is_txr_rn_db_pcie_addr) + ch_scratch.wdi3.wifi_rp_address_high = + (u32)((u32)ch_scratch.wdi3.wifi_rp_address_high | + (1 << 8)); + } else { + if ((ipa3_ctx->platform_type == IPA_PLAT_TYPE_MDM) && + info_smmu->is_txr_rn_db_pcie_addr) + ch_scratch.wdi3.wifi_rp_address_high = + (u32)((u32)ch_scratch.wdi3.wifi_rp_address_high | + (1 << 8)); + } + + if(ipa_get_wdi_version() == IPA_WDI_3_V2) { + + ch_scratch.wdi3_v2.wifi_rp_address_high = + ch_scratch.wdi3.wifi_rp_address_high; + + ch_scratch.wdi3_v2.wifi_rp_address_low = + ch_scratch.wdi3.wifi_rp_address_low; + + ch_scratch.wdi3_v2.update_rp_moderation_threshold = + ch_scratch.wdi3.update_rp_moderation_threshold; + + + if ( dir == IPA_WDI3_RX_DIR) { + + ch_scratch.wdi3_v2.rx_pkt_offset = ch_scratch.wdi3.rx_pkt_offset; + ch_scratch.wdi3_v2.endp_metadata_reg_offset = + ch_scratch.wdi3.endp_metadata_reg_offset; + } else { + + + if(is_smmu_enabled) { + if(info_smmu->rx_bank_id > IPA_WDI3_MAX_VALUE_OF_BANK_ID) { + IPAERR("Incorrect bank id value %d Exceeding the 6bit range\n", info_smmu->rx_bank_id); + goto fail_write_scratch; + } + ch_scratch.wdi3_v2.bank_id = info_smmu->rx_bank_id; + } + else { + if(info->rx_bank_id > IPA_WDI3_MAX_VALUE_OF_BANK_ID) { + IPAERR("Incorrect bank id value %d Exceeding the 6bit range\n", info->rx_bank_id); + goto fail_write_scratch; + } + + ch_scratch.wdi3_v2.bank_id = info->rx_bank_id; + } + } + + ch_scratch.wdi3_v2.qmap_id = 0; + ch_scratch.wdi3_v2.reserved1 = 0; + ch_scratch.wdi3_v2.reserved2 = 0; + } + + result = gsi_write_channel_scratch(ep->gsi_chan_hdl, ch_scratch); + if (result != GSI_STATUS_SUCCESS) { + IPAERR("failed to write evt ring scratch\n"); + goto fail_write_scratch; + } + return 0; + +fail_write_scratch: + gsi_dealloc_channel(ep->gsi_chan_hdl); + ep->gsi_chan_hdl = ~0; +fail_get_gsi_ep_info: + gsi_dealloc_evt_ring(ep->gsi_evt_ring_hdl); + ep->gsi_evt_ring_hdl = ~0; +fail_smmu_mapping: + ipa3_release_wdi3_gsi_smmu_mappings(dir); + return result; +} + +int ipa3_conn_wdi3_pipes(struct ipa_wdi_conn_in_params *in, + struct ipa_wdi_conn_out_params *out, + ipa_wdi_meter_notifier_cb wdi_notify) +{ + enum ipa_client_type rx_client; + enum ipa_client_type tx_client; + enum ipa_client_type tx1_client; + struct ipa3_ep_context *ep_rx; + struct ipa3_ep_context *ep_tx; + struct ipa3_ep_context *ep_tx1; + int ipa_ep_idx_rx; + int ipa_ep_idx_tx; + int ipa_ep_idx_tx1 = IPA_EP_NOT_ALLOCATED; + int result = 0; + u32 gsi_db_addr_low, gsi_db_addr_high; + void __iomem *db_addr; + u32 evt_ring_db_addr_low, evt_ring_db_addr_high, db_val = 0; + u8 rx_dir, tx_dir; + + /* wdi3 only support over gsi */ + if (ipa_get_wdi_version() < IPA_WDI_3) { + IPAERR("wdi3 over uc offload not supported"); + WARN_ON(1); + return -EFAULT; + } + + if (in == NULL || out == NULL) { + IPAERR("invalid input\n"); + return -EINVAL; + } + + if (in->is_smmu_enabled == false) { + rx_client = in->u_rx.rx.client; + tx_client = in->u_tx.tx.client; + } else { + rx_client = in->u_rx.rx_smmu.client; + tx_client = in->u_tx.tx_smmu.client; + } + + ipa_ep_idx_rx = ipa_get_ep_mapping(rx_client); + ipa_ep_idx_tx = ipa_get_ep_mapping(tx_client); + + if (ipa_ep_idx_rx == -1 || ipa_ep_idx_tx == -1) { + IPAERR("fail to alloc EP.\n"); + return -EFAULT; + } + if (ipa_ep_idx_rx >= ipa3_get_max_num_pipes() || + ipa_ep_idx_tx >= ipa3_get_max_num_pipes()) { + IPAERR("ep out of range.\n"); + return -EFAULT; + } + + ep_rx = &ipa3_ctx->ep[ipa_ep_idx_rx]; + ep_tx = &ipa3_ctx->ep[ipa_ep_idx_tx]; + + if (ep_rx->valid || ep_tx->valid) { + IPAERR("EP already allocated.\n"); + return -EFAULT; + } + + memset(ep_rx, 0, offsetof(struct ipa3_ep_context, sys)); + memset(ep_tx, 0, offsetof(struct ipa3_ep_context, sys)); + + if (in->is_tx1_used && + ipa3_ctx->is_wdi3_tx1_needed) { + tx1_client = (in->is_smmu_enabled) ? + in->u_tx1.tx_smmu.client : in->u_tx1.tx.client; + ipa_ep_idx_tx1 = ipa_get_ep_mapping(tx1_client); + + if (ipa_ep_idx_tx1 == IPA_EP_NOT_ALLOCATED || + ipa_ep_idx_tx1 >= IPA3_MAX_NUM_PIPES) { + IPAERR("fail to alloc ep2 tx clnt %d not supprtd %d", + tx1_client, ipa_ep_idx_tx1); + return -EINVAL; + } else { + ep_tx1 = &ipa3_ctx->ep[ipa_ep_idx_tx1]; + if (ep_tx1->valid) { + IPAERR("EP already allocated.\n"); + return -EFAULT; + } + } + memset(ep_tx1, 0, offsetof(struct ipa3_ep_context, sys)); + } + + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + +#ifdef IPA_WAN_MSG_IPv6_ADDR_GW_LEN + if (wdi_notify) + ipa3_ctx->uc_wdi_ctx.stats_notify = wdi_notify; + else + IPADBG("wdi_notify is null\n"); +#endif + + /* setup rx ep cfg */ + ep_rx->valid = 1; + ep_rx->client = rx_client; + result = ipa3_disable_data_path(ipa_ep_idx_rx); + if (result) { + IPAERR("disable data path failed res=%d clnt=%d.\n", result, + ipa_ep_idx_rx); + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + return -EFAULT; + } + ep_rx->client_notify = in->notify; + ep_rx->priv = in->priv; + + if (in->is_smmu_enabled == false) + memcpy(&ep_rx->cfg, &in->u_rx.rx.ipa_ep_cfg, + sizeof(ep_rx->cfg)); + else + memcpy(&ep_rx->cfg, &in->u_rx.rx_smmu.ipa_ep_cfg, + sizeof(ep_rx->cfg)); + + if (ipa3_ctx->ipa_wdi_opt_dpath && + ipa3_ctx->platform_type != IPA_PLAT_TYPE_XR) { + ep_rx->cfg.cfg.frag_offload_en = true; + ep_rx->status.status_en = true; + ep_rx->status.status_ep = + ipa_get_ep_mapping(IPA_CLIENT_Q6_WAN_CONS); + ep_rx->status.status_pkt_suppress = true; + } + + if (ipa3_cfg_ep(ipa_ep_idx_rx, &ep_rx->cfg)) { + IPAERR("fail to setup rx pipe cfg\n"); + result = -EFAULT; + goto fail; + } + + if (ipa3_cfg_ep_status(ipa_ep_idx_rx, &ep_rx->status)) { + IPAERR("fail to configure status of EP.\n"); + goto fail; + } + + /* setup RX gsi channel */ + rx_dir = (rx_client == IPA_CLIENT_WLAN2_PROD) ? + IPA_WDI3_RX_DIR : IPA_WDI3_RX2_DIR; + + if (ipa3_setup_wdi3_gsi_channel(in->is_smmu_enabled, + &in->u_rx.rx, &in->u_rx.rx_smmu, rx_dir, + ep_rx)) { + IPAERR("fail to setup wdi3 gsi rx channel\n"); + result = -EFAULT; + goto fail; + } + if (gsi_query_channel_db_addr(ep_rx->gsi_chan_hdl, + &gsi_db_addr_low, &gsi_db_addr_high)) { + IPAERR("failed to query gsi rx db addr\n"); + result = -EFAULT; + goto fail; + } + /* only 32 bit lsb is used */ + out->rx_uc_db_pa = (phys_addr_t)(gsi_db_addr_low); + IPADBG("out->rx_uc_db_pa %llu\n", out->rx_uc_db_pa); + + ipa3_install_dflt_flt_rules(ipa_ep_idx_rx); + IPADBG("client %d (ep: %d) connected\n", rx_client, + ipa_ep_idx_rx); + + /* setup tx ep cfg */ + ep_tx->valid = 1; + ep_tx->client = tx_client; + result = ipa3_disable_data_path(ipa_ep_idx_tx); + if (result) { + IPAERR("disable data path failed res=%d ep=%d.\n", result, + ipa_ep_idx_tx); + result = -EFAULT; + goto fail; + } + + if (in->is_smmu_enabled == false) + memcpy(&ep_tx->cfg, &in->u_tx.tx.ipa_ep_cfg, + sizeof(ep_tx->cfg)); + else + memcpy(&ep_tx->cfg, &in->u_tx.tx_smmu.ipa_ep_cfg, + sizeof(ep_tx->cfg)); + + ep_tx->cfg.aggr.aggr_en = IPA_ENABLE_AGGR; + ep_tx->cfg.aggr.aggr = IPA_GENERIC; + ep_tx->cfg.aggr.aggr_byte_limit = IPA_WLAN_AGGR_BYTE_LIMIT; + ep_tx->cfg.aggr.aggr_pkt_limit = IPA_WLAN_AGGR_PKT_LIMIT; + ep_tx->cfg.aggr.aggr_hard_byte_limit_en = IPA_ENABLE_AGGR; + if (ipa3_cfg_ep(ipa_ep_idx_tx, &ep_tx->cfg)) { + IPAERR("fail to setup tx pipe cfg\n"); + result = -EFAULT; + goto fail; + } + + /* setup TX gsi channel */ + tx_dir = (tx_client == IPA_CLIENT_WLAN2_CONS) ? + IPA_WDI3_TX_DIR : IPA_WDI3_TX2_DIR; + + if (ipa3_setup_wdi3_gsi_channel(in->is_smmu_enabled, + &in->u_tx.tx, &in->u_tx.tx_smmu, tx_dir, + ep_tx)) { + IPAERR("fail to setup wdi3 gsi tx channel\n"); + result = -EFAULT; + goto fail; + } + if (gsi_query_channel_db_addr(ep_tx->gsi_chan_hdl, + &gsi_db_addr_low, &gsi_db_addr_high)) { + IPAERR("failed to query gsi tx db addr\n"); + result = -EFAULT; + goto fail; + } + /* only 32 bit lsb is used */ + out->tx_uc_db_pa = (phys_addr_t)(gsi_db_addr_low); + IPADBG("out->tx_uc_db_pa %llu\n", out->tx_uc_db_pa); + IPADBG("client %d (ep: %d) connected\n", tx_client, + ipa_ep_idx_tx); + + /* ring initial event ring dbs */ + gsi_query_evt_ring_db_addr(ep_rx->gsi_evt_ring_hdl, + &evt_ring_db_addr_low, &evt_ring_db_addr_high); + IPADBG("evt_ring_hdl %lu, db_addr_low %u db_addr_high %u\n", + ep_rx->gsi_evt_ring_hdl, evt_ring_db_addr_low, + evt_ring_db_addr_high); + + /* only 32 bit lsb is used */ + db_addr = ioremap((phys_addr_t)(evt_ring_db_addr_low), 4); + /* + * IPA/GSI driver should ring the event DB once after + * initialization of the event, with a value that is + * outside of the ring range. Eg: ring base = 0x1000, + * ring size = 0x100 => AP can write value > 0x1100 + * into the doorbell address. Eg: 0x 1110. + * Use event ring base addr + event ring size + 1 element size. + */ + db_val = (u32)ep_rx->gsi_mem_info.evt_ring_base_addr; + db_val += ((in->is_smmu_enabled) ? in->u_rx.rx_smmu.event_ring_size : + in->u_rx.rx.event_ring_size); + db_val += GSI_EVT_RING_RE_SIZE_8B; + iowrite32(db_val, db_addr); + IPADBG("RX base_addr 0x%x evt wp val: 0x%x\n", + ep_rx->gsi_mem_info.evt_ring_base_addr, db_val); + + gsi_query_evt_ring_db_addr(ep_tx->gsi_evt_ring_hdl, + &evt_ring_db_addr_low, &evt_ring_db_addr_high); + + /* only 32 bit lsb is used */ + db_addr = ioremap((phys_addr_t)(evt_ring_db_addr_low), 4); + /* + * IPA/GSI driver should ring the event DB once after + * initialization of the event, with a value that is + * outside of the ring range. Eg: ring base = 0x1000, + * ring size = 0x100 => AP can write value > 0x1100 + * into the doorbell address. Eg: 0x 1110 + * Use event ring base addr + event ring size + 1 element size. + */ + db_val = (u32)ep_tx->gsi_mem_info.evt_ring_base_addr; + db_val += ((in->is_smmu_enabled) ? in->u_tx.tx_smmu.event_ring_size : + in->u_tx.tx.event_ring_size); + db_val += ((ipa3_ctx->ipa_hw_type >= IPA_HW_v4_9) ? + GSI_EVT_RING_RE_SIZE_32B : GSI_EVT_RING_RE_SIZE_16B); + iowrite32(db_val, db_addr); + IPADBG("db_addr %u TX base_addr 0x%x evt wp val: 0x%x\n", + evt_ring_db_addr_low, + ep_tx->gsi_mem_info.evt_ring_base_addr, db_val); + + /* setup tx1 ep cfg */ + if (in->is_tx1_used && + ipa3_ctx->is_wdi3_tx1_needed && (ipa_ep_idx_tx1 != + IPA_EP_NOT_ALLOCATED) && (ipa_ep_idx_tx1 < + IPA3_MAX_NUM_PIPES)) { + ep_tx1->valid = 1; + ep_tx1->client = tx1_client; + result = ipa3_disable_data_path(ipa_ep_idx_tx1); + if (result) { + IPAERR("disable data path failed res=%d ep=%d.\n", + result, ipa_ep_idx_tx1); + result = -EFAULT; + goto fail; + } + + if (in->is_smmu_enabled == false) + memcpy(&ep_tx1->cfg, &in->u_tx1.tx.ipa_ep_cfg, + sizeof(ep_tx1->cfg)); + else + memcpy(&ep_tx1->cfg, &in->u_tx1.tx_smmu.ipa_ep_cfg, + sizeof(ep_tx1->cfg)); + + ep_tx1->cfg.aggr.aggr_en = IPA_ENABLE_AGGR; + ep_tx1->cfg.aggr.aggr = IPA_GENERIC; + ep_tx1->cfg.aggr.aggr_byte_limit = IPA_WLAN_AGGR_BYTE_LIMIT; + ep_tx1->cfg.aggr.aggr_pkt_limit = IPA_WLAN_AGGR_PKT_LIMIT; + ep_tx1->cfg.aggr.aggr_hard_byte_limit_en = IPA_ENABLE_AGGR; + if (ipa3_cfg_ep(ipa_ep_idx_tx1, &ep_tx1->cfg)) { + IPAERR("fail to setup tx pipe cfg\n"); + result = -EFAULT; + goto fail; + } + + /* setup TX1 gsi channel */ + if (ipa3_setup_wdi3_gsi_channel(in->is_smmu_enabled, + &in->u_tx1.tx, &in->u_tx1.tx_smmu, IPA_WDI3_TX1_DIR, + ep_tx1)) { + IPAERR("fail to setup wdi3 gsi tx1 channel\n"); + result = -EFAULT; + goto fail; + } + + if (gsi_query_channel_db_addr(ep_tx1->gsi_chan_hdl, + &gsi_db_addr_low, &gsi_db_addr_high)) { + IPAERR("failed to query gsi tx1 db addr\n"); + result = -EFAULT; + goto fail; + } + + /* only 32 bit lsb is used */ + out->tx1_uc_db_pa = (phys_addr_t)(gsi_db_addr_low); + IPADBG("out->tx1_uc_db_pa %llu\n", out->tx1_uc_db_pa); + IPADBG("client %d (ep: %d) connected\n", tx1_client, + ipa_ep_idx_tx1); + + /* ring initial event ring dbs */ + gsi_query_evt_ring_db_addr(ep_tx1->gsi_evt_ring_hdl, + &evt_ring_db_addr_low, &evt_ring_db_addr_high); + /* only 32 bit lsb is used */ + db_addr = ioremap((phys_addr_t)(evt_ring_db_addr_low), 4); + /* + * IPA/GSI driver should ring the event DB once after + * initialization of the event, with a value that is + * outside of the ring range. Eg: ring base = 0x1000, + * ring size = 0x100 => AP can write value > 0x1100 + * into the doorbell address. Eg: 0x 1110 + * Use event ring base addr + event ring size + 1 element size. + */ + db_val = (u32)ep_tx1->gsi_mem_info.evt_ring_base_addr; + db_val += ((in->is_smmu_enabled) ? + in->u_tx1.tx_smmu.event_ring_size : + in->u_tx1.tx.event_ring_size); + db_val += GSI_EVT_RING_RE_SIZE_16B; + iowrite32(db_val, db_addr); + IPADBG("db_addr %u TX1 base_addr 0x%x evt wp val: 0x%x\n", + evt_ring_db_addr_low, + ep_tx1->gsi_mem_info.evt_ring_base_addr, db_val); + } + +fail: + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + return result; +} +EXPORT_SYMBOL(ipa3_conn_wdi3_pipes); + +int ipa3_disconn_wdi3_pipes(int ipa_ep_idx_tx, int ipa_ep_idx_rx, + int ipa_ep_idx_tx1) +{ + struct ipa3_ep_context *ep_tx, *ep_rx, *ep_tx1; + enum ipa_client_type rx_client; + enum ipa_client_type tx_client; + int result = 0; + + /* wdi3 only support over gsi */ + if (ipa_get_wdi_version() < IPA_WDI_3) { + IPAERR("wdi3 over uc offload not supported"); + WARN_ON(1); + return -EFAULT; + } + + IPADBG("ep_tx = %d\n", ipa_ep_idx_tx); + IPADBG("ep_rx = %d\n", ipa_ep_idx_rx); + IPADBG("ep_tx1 = %d\n", ipa_ep_idx_tx1); + + if (ipa_ep_idx_tx < 0 || ipa_ep_idx_tx >= ipa3_get_max_num_pipes() || + ipa_ep_idx_rx < 0 || + ipa_ep_idx_rx >= ipa3_get_max_num_pipes()) { + IPAERR("invalid ipa ep index\n"); + return -EINVAL; + } + + ep_tx = &ipa3_ctx->ep[ipa_ep_idx_tx]; + ep_rx = &ipa3_ctx->ep[ipa_ep_idx_rx]; + rx_client = ipa3_get_client_mapping(ipa_ep_idx_rx); + tx_client = ipa3_get_client_mapping(ipa_ep_idx_tx); + IPA_ACTIVE_CLIENTS_INC_EP(ipa3_get_client_mapping(ipa_ep_idx_tx)); + /* tear down tx1 pipe */ + if (ipa_ep_idx_tx1 >= 0) { + ep_tx1 = &ipa3_ctx->ep[ipa_ep_idx_tx1]; + result = ipa3_reset_gsi_channel(ipa_ep_idx_tx1); + if (result != GSI_STATUS_SUCCESS) { + IPAERR("failed to reset gsi channel: %d.\n", result); + goto exit; + } + result = gsi_reset_evt_ring(ep_tx1->gsi_evt_ring_hdl); + if (result != GSI_STATUS_SUCCESS) { + IPAERR("failed to reset evt ring: %d.\n", result); + goto exit; + } + result = ipa3_release_gsi_channel(ipa_ep_idx_tx1); + if (result) { + IPAERR("failed to release gsi channel: %d\n", result); + goto exit; + } + ipa3_release_wdi3_gsi_smmu_mappings(IPA_WDI3_TX1_DIR); + + memset(ep_tx1, 0, sizeof(struct ipa3_ep_context)); + IPADBG("tx client (ep: %d) disconnected\n", ipa_ep_idx_tx1); + } + + /* tear down tx pipe */ + result = ipa3_reset_gsi_channel(ipa_ep_idx_tx); + if (result != GSI_STATUS_SUCCESS) { + IPAERR("failed to reset gsi channel: %d.\n", result); + goto exit; + } + result = gsi_reset_evt_ring(ep_tx->gsi_evt_ring_hdl); + if (result != GSI_STATUS_SUCCESS) { + IPAERR("failed to reset evt ring: %d.\n", result); + goto exit; + } + result = ipa3_release_gsi_channel(ipa_ep_idx_tx); + if (result) { + IPAERR("failed to release gsi channel: %d\n", result); + goto exit; + } + if (tx_client == IPA_CLIENT_WLAN2_CONS) + ipa3_release_wdi3_gsi_smmu_mappings(IPA_WDI3_TX_DIR); + else + ipa3_release_wdi3_gsi_smmu_mappings(IPA_WDI3_TX2_DIR); + + memset(ep_tx, 0, sizeof(struct ipa3_ep_context)); + IPADBG("tx client (ep: %d) disconnected\n", ipa_ep_idx_tx); + + /* tear down rx pipe */ + result = ipa3_reset_gsi_channel(ipa_ep_idx_rx); + if (result != GSI_STATUS_SUCCESS) { + IPAERR("failed to reset gsi channel: %d.\n", result); + goto exit; + } + result = gsi_reset_evt_ring(ep_rx->gsi_evt_ring_hdl); + if (result != GSI_STATUS_SUCCESS) { + IPAERR("failed to reset evt ring: %d.\n", result); + goto exit; + } + result = ipa3_release_gsi_channel(ipa_ep_idx_rx); + if (result) { + IPAERR("failed to release gsi channel: %d\n", result); + goto exit; + } + if (rx_client == IPA_CLIENT_WLAN2_PROD) + ipa3_release_wdi3_gsi_smmu_mappings(IPA_WDI3_RX_DIR); + else + ipa3_release_wdi3_gsi_smmu_mappings(IPA_WDI3_RX2_DIR); + + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_5 && ipa3_ctx->ipa_hw_type != IPA_HW_v5_2 + && ipa3_ctx->platform_type != IPA_PLAT_TYPE_XR) + ipa3_uc_debug_stats_dealloc(IPA_HW_PROTOCOL_WDI3); + + if (ipa3_ctx->ipa_wdi_opt_dpath) + ipa3_disable_wdi3_opt_dpath(ipa_ep_idx_rx, ipa_ep_idx_tx); + + ipa3_delete_dflt_flt_rules(ipa_ep_idx_rx); + memset(ep_rx, 0, sizeof(struct ipa3_ep_context)); + IPADBG("rx client (ep: %d) disconnected\n", ipa_ep_idx_rx); + +exit: + IPA_ACTIVE_CLIENTS_DEC_EP(ipa3_get_client_by_pipe(ipa_ep_idx_tx)); + return result; +} +EXPORT_SYMBOL(ipa3_disconn_wdi3_pipes); + +int ipa3_enable_wdi3_pipes(int ipa_ep_idx_tx, int ipa_ep_idx_rx, + int ipa_ep_idx_tx1) +{ + struct ipa3_ep_context *ep_tx, *ep_rx; + struct ipa3_ep_context *ep_tx1 = NULL; + int result = 0; + struct ipa_ep_cfg_holb holb_cfg; + u32 holb_max_cnt = ipa3_ctx->uc_ctx.holb_monitor.max_cnt_wlan; + + /* wdi3 only support over gsi */ + if (ipa_get_wdi_version() < IPA_WDI_3) { + IPAERR("wdi3 over uc offload not supported"); + WARN_ON(1); + return -EFAULT; + } + + IPADBG("ep_tx = %d\n", ipa_ep_idx_tx); + IPADBG("ep_rx = %d\n", ipa_ep_idx_rx); + IPADBG("ep_tx1 = %d\n", ipa_ep_idx_tx1); + + ep_tx = &ipa3_ctx->ep[ipa_ep_idx_tx]; + ep_rx = &ipa3_ctx->ep[ipa_ep_idx_rx]; + if (ipa_ep_idx_tx1 >= 0) + ep_tx1 = &ipa3_ctx->ep[ipa_ep_idx_tx1]; + + IPA_ACTIVE_CLIENTS_INC_EP(ipa3_get_client_mapping(ipa_ep_idx_tx)); + + /* start uC event ring */ + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_5 && ipa3_ctx->ipa_hw_type != IPA_HW_v5_2) { + if (ipa3_ctx->uc_ctx.uc_loaded && + !ipa3_ctx->uc_ctx.uc_event_ring_valid) { + if (ipa3_uc_setup_event_ring()) { + IPAERR("failed to set uc_event ring\n"); + return -EFAULT; + } + } else + IPAERR("uc-loaded %d, ring-valid %d\n", + ipa3_ctx->uc_ctx.uc_loaded, + ipa3_ctx->uc_ctx.uc_event_ring_valid); + } + + /* enable data path */ + result = ipa3_enable_data_path(ipa_ep_idx_rx); + if (result) { + IPAERR("enable data path failed res=%d clnt=%d\n", result, + ipa_ep_idx_rx); + goto exit; + } + + result = ipa3_enable_data_path(ipa_ep_idx_tx); + if (result) { + IPAERR("enable data path failed res=%d clnt=%d\n", result, + ipa_ep_idx_tx); + goto fail_enable_path1; + } + + /* Enable and config HOLB TO for both tx pipes */ + if (ipa_ep_idx_tx1 >= 0) { + result = ipa3_enable_data_path(ipa_ep_idx_tx1); + if (result) { + IPAERR("enable data path failed res=%d clnt=%d\n", + result, ipa_ep_idx_tx1); + goto fail_enable_path2; + } + memset(&holb_cfg, 0, sizeof(holb_cfg)); + holb_cfg.en = IPA_HOLB_TMR_EN; + holb_cfg.tmr_val = ipa3_ctx->ipa_wdi3_5g_holb_timeout; + IPADBG("Configuring HOLB TO on tx return = %d\n", + ipa3_cfg_ep_holb(ipa_ep_idx_tx, &holb_cfg)); + holb_cfg.tmr_val = ipa3_ctx->ipa_wdi3_2g_holb_timeout; + IPADBG("Configuring HOLB TO on tx1 return = %d\n", + ipa3_cfg_ep_holb(ipa_ep_idx_tx1, &holb_cfg)); + } + + /* start gsi tx channel */ + result = gsi_start_channel(ep_tx->gsi_chan_hdl); + if (result) { + IPAERR("failed to start gsi tx channel\n"); + goto fail_start_channel1; + } + + /* start gsi tx1 channel */ + if (ipa_ep_idx_tx1 >= 0) { + result = gsi_start_channel(ep_tx1->gsi_chan_hdl); + if (result) { + IPAERR("failed to start gsi tx1 channel\n"); + goto fail_start_channel2; + } + } + + result = ipa3_uc_client_add_holb_monitor(ep_tx->gsi_chan_hdl, + HOLB_MONITOR_MASK, holb_max_cnt, + IPA_EE_AP); + if (result) + IPAERR("Add HOLB monitor failed for gsi ch %d\n", + ep_tx->gsi_chan_hdl); + + /* start gsi rx channel */ + result = gsi_start_channel(ep_rx->gsi_chan_hdl); + if (result) { + IPAERR("failed to start gsi rx channel\n"); + goto fail_start_channel3; + } + /* start uC gsi dbg stats monitor */ + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_5 && ipa3_ctx->ipa_hw_type != IPA_HW_v5_2 + && ipa3_ctx->platform_type != IPA_PLAT_TYPE_XR) { + ipa3_ctx->gsi_info[IPA_HW_PROTOCOL_WDI3].ch_id_info[0].ch_id + = ep_rx->gsi_chan_hdl; + ipa3_ctx->gsi_info[IPA_HW_PROTOCOL_WDI3].ch_id_info[0].dir + = DIR_PRODUCER; + ipa3_ctx->gsi_info[IPA_HW_PROTOCOL_WDI3].ch_id_info[1].ch_id + = ep_tx->gsi_chan_hdl; + ipa3_ctx->gsi_info[IPA_HW_PROTOCOL_WDI3].ch_id_info[1].dir + = DIR_CONSUMER; + if (ipa_ep_idx_tx1 >= 0) { + ipa3_ctx->gsi_info[ + IPA_HW_PROTOCOL_WDI3].ch_id_info[2].ch_id + = ep_tx1->gsi_chan_hdl; + ipa3_ctx->gsi_info[ + IPA_HW_PROTOCOL_WDI3].ch_id_info[2].dir + = DIR_CONSUMER; + } + ipa3_uc_debug_stats_alloc( + ipa3_ctx->gsi_info[IPA_HW_PROTOCOL_WDI3]); + } + goto exit; + +fail_start_channel3: + if (ipa_ep_idx_tx1 >= 0) + gsi_stop_channel(ep_tx1->gsi_chan_hdl); +fail_start_channel2: + gsi_stop_channel(ep_tx->gsi_chan_hdl); +fail_start_channel1: + if (ipa_ep_idx_tx1 >= 0) + ipa3_disable_data_path(ipa_ep_idx_tx1); +fail_enable_path2: + ipa3_disable_data_path(ipa_ep_idx_tx); +fail_enable_path1: + ipa3_disable_data_path(ipa_ep_idx_rx); +exit: + IPA_ACTIVE_CLIENTS_DEC_EP(ipa3_get_client_mapping(ipa_ep_idx_tx)); + return result; +} +EXPORT_SYMBOL(ipa3_enable_wdi3_pipes); + +int ipa3_disable_wdi3_pipes(int ipa_ep_idx_tx, int ipa_ep_idx_rx, + int ipa_ep_idx_tx1) +{ + int result = 0; + struct ipa3_ep_context *ep; + u32 source_pipe_bitmask = 0; + u32 source_pipe_reg_idx = 0; + bool disable_force_clear = false; + struct ipahal_ep_cfg_ctrl_scnd ep_ctrl_scnd = { 0 }; + + /* wdi3 only support over gsi */ + if (ipa_get_wdi_version() < IPA_WDI_3) { + IPAERR("wdi3 over uc offload not supported"); + WARN_ON(1); + return -EFAULT; + } + + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + + /* disable tx data path */ + result = ipa3_disable_data_path(ipa_ep_idx_tx); + if (result) { + IPAERR("disable data path failed res=%d clnt=%d.\n", result, + ipa_ep_idx_tx); + result = -EFAULT; + goto fail; + } + + /* disable tx1 data path */ + if (ipa_ep_idx_tx1 >= 0) { + result = ipa3_disable_data_path(ipa_ep_idx_tx1); + if (result) { + IPAERR("disable data path failed res=%d clnt=%d.\n", result, + ipa_ep_idx_tx1); + result = -EFAULT; + goto fail; + } + } + + /* disable rx data path */ + result = ipa3_disable_data_path(ipa_ep_idx_rx); + if (result) { + IPAERR("disable data path failed res=%d clnt=%d.\n", result, + ipa_ep_idx_rx); + result = -EFAULT; + goto fail; + } + /* + * For WDI 3.0 need to ensure pipe will be empty before suspend + * as IPA uC will fail to suspend the pipe otherwise. + */ + ep = &ipa3_ctx->ep[ipa_ep_idx_rx]; + if (IPA_CLIENT_IS_PROD(ep->client)) { + source_pipe_bitmask = ipahal_get_ep_bit(ipa_ep_idx_rx); + source_pipe_reg_idx = ipahal_get_ep_reg_idx(ipa_ep_idx_rx); + result = ipa3_enable_force_clear(ipa_ep_idx_rx, + false, source_pipe_bitmask, + source_pipe_reg_idx); + if (result) { + /* + * assuming here modem SSR, AP can remove + * the delay in this case + */ + IPAERR("failed to force clear %d\n", result); + IPAERR("remove delay from SCND reg\n"); + if (ipa3_ctx->ipa_endp_delay_wa_v2) { + ipa3_remove_secondary_flow_ctrl( + ep->gsi_chan_hdl); + } else { + ep_ctrl_scnd.endp_delay = false; + ipahal_write_reg_n_fields( + IPA_ENDP_INIT_CTRL_SCND_n, + ipa_ep_idx_rx, + &ep_ctrl_scnd); + } + } else { + disable_force_clear = true; + } + } + + /* stop gsi rx channel */ + result = ipa_stop_gsi_channel(ipa_ep_idx_rx); + if (result) { + IPAERR("failed to stop gsi rx channel\n"); + result = -EFAULT; + goto fail; + } + + /* stop gsi tx channel */ + result = ipa_stop_gsi_channel(ipa_ep_idx_tx); + if (result) { + IPAERR("failed to stop gsi tx channel\n"); + result = -EFAULT; + goto fail; + } + /* stop gsi tx1 channel */ + if (ipa_ep_idx_tx1 >= 0) { + result = ipa_stop_gsi_channel(ipa_ep_idx_tx1); + if (result) { + IPAERR("failed to stop gsi tx1 channel\n"); + result = -EFAULT; + goto fail; + } + } + /* stop uC gsi dbg stats monitor */ + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_5 && ipa3_ctx->ipa_hw_type != IPA_HW_v5_2 + && ipa3_ctx->platform_type != IPA_PLAT_TYPE_XR) { + ipa3_ctx->gsi_info[IPA_HW_PROTOCOL_WDI3].ch_id_info[0].ch_id + = 0xff; + ipa3_ctx->gsi_info[IPA_HW_PROTOCOL_WDI3].ch_id_info[0].dir + = DIR_PRODUCER; + ipa3_ctx->gsi_info[IPA_HW_PROTOCOL_WDI3].ch_id_info[1].ch_id + = 0xff; + ipa3_ctx->gsi_info[IPA_HW_PROTOCOL_WDI3].ch_id_info[1].dir + = DIR_CONSUMER; + if (ipa_ep_idx_tx1 >= 0) { + ipa3_ctx->gsi_info[ + IPA_HW_PROTOCOL_WDI3].ch_id_info[2].ch_id + = 0xff; + ipa3_ctx->gsi_info[ + IPA_HW_PROTOCOL_WDI3].ch_id_info[2].dir + = DIR_CONSUMER; + } + ipa3_uc_debug_stats_alloc( + ipa3_ctx->gsi_info[IPA_HW_PROTOCOL_WDI3]); + } + if (disable_force_clear) + ipa3_disable_force_clear(ipa_ep_idx_rx); + +fail: + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + return result; + +} +EXPORT_SYMBOL(ipa3_disable_wdi3_pipes); + +int ipa3_write_qmapid_wdi3_gsi_pipe(u32 clnt_hdl, u8 qmap_id) +{ + int result = 0; + struct ipa3_ep_context *ep; + union __packed gsi_wdi3_channel_scratch2_reg scratch2_reg; + + memset(&scratch2_reg, 0, sizeof(scratch2_reg)); + if (clnt_hdl >= ipa3_ctx->ipa_num_pipes || + ipa3_ctx->ep[clnt_hdl].valid == 0) { + IPAERR_RL("bad parm, %d\n", clnt_hdl); + return -EINVAL; + } + ep = &ipa3_ctx->ep[clnt_hdl]; + IPA_ACTIVE_CLIENTS_INC_EP(ipa3_get_client_mapping(clnt_hdl)); + result = gsi_read_wdi3_channel_scratch2_reg(ep->gsi_chan_hdl, + &scratch2_reg); + + if (result != GSI_STATUS_SUCCESS) { + IPAERR("failed to read channel scratch2 reg %d\n", result); + goto exit; + } + + scratch2_reg.wdi.qmap_id = qmap_id; + result = gsi_write_wdi3_channel_scratch2_reg(ep->gsi_chan_hdl, + scratch2_reg); + if (result != GSI_STATUS_SUCCESS) { + IPAERR("failed to write channel scratch2 reg %d\n", result); + goto exit; + } + +exit: + IPA_ACTIVE_CLIENTS_DEC_EP(ipa3_get_client_mapping(clnt_hdl)); + return result; +} + +/** + * ipa3_get_wdi3_gsi_stats() - Query WDI3 gsi stats from uc + * @stats: [inout] stats blob from client populated by driver + * + * Returns: 0 on success, negative on failure + * + * @note Cannot be called from atomic context + * + */ +int ipa3_get_wdi3_gsi_stats(struct ipa_uc_dbg_ring_stats *stats) +{ + int i; + + if (!ipa3_ctx->wdi3_ctx.dbg_stats.uc_dbg_stats_mmio) + return -EINVAL; + + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + for (i = 0; i < MAX_WDI3_CHANNELS; i++) { + stats->u.ring[i].ringFull = ioread32( + ipa3_ctx->wdi3_ctx.dbg_stats.uc_dbg_stats_mmio + + i * IPA3_UC_DEBUG_STATS_OFF + + IPA3_UC_DEBUG_STATS_RINGFULL_OFF); + stats->u.ring[i].ringEmpty = ioread32( + ipa3_ctx->wdi3_ctx.dbg_stats.uc_dbg_stats_mmio + + i * IPA3_UC_DEBUG_STATS_OFF + + IPA3_UC_DEBUG_STATS_RINGEMPTY_OFF); + stats->u.ring[i].ringUsageHigh = ioread32( + ipa3_ctx->wdi3_ctx.dbg_stats.uc_dbg_stats_mmio + + i * IPA3_UC_DEBUG_STATS_OFF + + IPA3_UC_DEBUG_STATS_RINGUSAGEHIGH_OFF); + stats->u.ring[i].ringUsageLow = ioread32( + ipa3_ctx->wdi3_ctx.dbg_stats.uc_dbg_stats_mmio + + i * IPA3_UC_DEBUG_STATS_OFF + + IPA3_UC_DEBUG_STATS_RINGUSAGELOW_OFF); + stats->u.ring[i].RingUtilCount = ioread32( + ipa3_ctx->wdi3_ctx.dbg_stats.uc_dbg_stats_mmio + + i * IPA3_UC_DEBUG_STATS_OFF + + IPA3_UC_DEBUG_STATS_RINGUTILCOUNT_OFF); + } + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + + return 0; +} + +int ipa3_enable_wdi3_opt_dpath(int ipa_ep_idx_rx, int ipa_ep_idx_tx, + u32 rt_tbl_idx) +{ + int result = 0; + struct ipa3_ep_context *ep_tx = NULL; + + /* wdi3 only support over gsi */ + if (ipa_get_wdi_version() < IPA_WDI_3) { + IPADBG("wdi3 over uc offload not supported"); + return -EFAULT; + } + + IPADBG("ep_rx = %d, ep_tx = %d\n", ipa_ep_idx_rx, ipa_ep_idx_tx); + IPADBG("rt_tbl_idx = %d\n", rt_tbl_idx); + + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + + /* Install default filter rules.*/ + ipa3_install_dl_opt_wdi_dpath_flt_rules(ipa_ep_idx_rx, rt_tbl_idx); + + result = ipa3_enable_data_path(ipa_ep_idx_tx); + if (result) { + IPADBG("enable data path failed res=%d clnt=%d\n", result, + ipa_ep_idx_tx); + } + + ep_tx = &ipa3_ctx->ep[ipa_ep_idx_tx]; + /* start gsi tx channel */ + result = gsi_start_channel(ep_tx->gsi_chan_hdl); + if (result) { + IPADBG("failed to start gsi tx channel\n"); + } + + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + + return result; +} +EXPORT_SYMBOL(ipa3_enable_wdi3_opt_dpath); + +int ipa3_disable_wdi3_opt_dpath(int ipa_ep_idx_rx, int ipa_ep_idx_tx) +{ + int result = 0; + + /* wdi3 only support over gsi */ + if (ipa_get_wdi_version() < IPA_WDI_3) { + IPADBG("wdi3 over uc offload not supported"); + return -EFAULT; + } + + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + + IPADBG("ep_rx = %d, ep_tx = %d\n", ipa_ep_idx_rx, ipa_ep_idx_tx); + + /* Install default filter rules.*/ + ipa3_delete_dl_opt_wdi_dpath_flt_rules(ipa_ep_idx_rx); + + /* disable tx data path */ + result = ipa3_disable_data_path(ipa_ep_idx_tx); + if (result) { + IPADBG("disable data path failed res=%d clnt=%d.\n", result, + ipa_ep_idx_tx); + result = -EFAULT; + goto fail; + } + + /* stop gsi tx channel */ + result = ipa_stop_gsi_channel(ipa_ep_idx_tx); + if (result) { + IPADBG("failed to stop gsi tx channel\n"); + result = -EFAULT; + goto fail; + } + +fail: + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + return result; +} +EXPORT_SYMBOL(ipa3_disable_wdi3_opt_dpath); + diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_wigig_i.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_wigig_i.c new file mode 100644 index 0000000000..f5ccd75b0d --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_wigig_i.c @@ -0,0 +1,1987 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. + */ + +#include "ipa_i.h" +#include +#include +#include +#include "ipa_wigig.h" + +#define IPA_WIGIG_DESC_RING_EL_SIZE 32 +#define IPA_WIGIG_STATUS_RING_EL_SIZE 16 + +#define GSI_STOP_MAX_RETRY_CNT 10 + +#define IPA_WIGIG_CONNECTED BIT(0) +#define IPA_WIGIG_ENABLED BIT(1) +#define IPA_WIGIG_MSB_MASK 0xFFFFFFFF00000000 +#define IPA_WIGIG_LSB_MASK 0x00000000FFFFFFFF +#define IPA_WIGIG_MSB(num) ((u32)((num & IPA_WIGIG_MSB_MASK) >> 32)) +#define IPA_WIGIG_LSB(num) ((u32)(num & IPA_WIGIG_LSB_MASK)) +/* extract PCIE addresses [0:39] relevant msb */ +#define IPA_WIGIG_8_MSB_MASK 0xFF00000000 +#define IPA_WIGIG_8_MSB(num) ((u32)((num & IPA_WIGIG_8_MSB_MASK) >> 32)) +#define W11AD_RX 0 +#define W11AD_TX 1 +#define W11AD_TO_GSI_DB_m 1 +#define W11AD_TO_GSI_DB_n 1 + +static LIST_HEAD(smmu_reg_addr_list); +static LIST_HEAD(smmu_ring_addr_list); +static DEFINE_MUTEX(smmu_lock); +struct dentry *wigig_dent; + +struct ipa_wigig_smmu_reg_addr { + struct list_head link; + phys_addr_t phys_addr; + enum ipa_smmu_cb_type cb_type; + u8 count; +}; + +struct ipa_wigig_smmu_ring_addr { + struct list_head link; + u64 iova; + enum ipa_smmu_cb_type cb_type; + u8 count; +}; + + +static int ipa3_wigig_uc_loaded_handler(struct notifier_block *self, + unsigned long val, void *data) +{ + IPADBG("val %ld\n", val); + + if (!ipa3_ctx) { + IPAERR("IPA ctx is null\n"); + return -EINVAL; + } + + WARN_ON(data != ipa3_ctx); + + if (ipa3_ctx->uc_wigig_ctx.uc_ready_cb) { + ipa3_ctx->uc_wigig_ctx.uc_ready_cb( + ipa3_ctx->uc_wigig_ctx.priv); + + ipa3_ctx->uc_wigig_ctx.uc_ready_cb = + NULL; + ipa3_ctx->uc_wigig_ctx.priv = NULL; + } + + IPADBG("exit\n"); + return 0; +} + +static struct notifier_block uc_loaded_notifier = { + .notifier_call = ipa3_wigig_uc_loaded_handler, +}; + +int ipa3_wigig_init_i(void) +{ + IPADBG("\n"); + + ipa3_uc_register_ready_cb(&uc_loaded_notifier); + + IPADBG("exit\n"); + + return 0; +} + +int ipa3_wigig_internal_init( + struct ipa_wdi_uc_ready_params *inout, + ipa_wigig_misc_int_cb int_notify, + phys_addr_t *uc_db_pa) +{ + int result = 0; + + IPADBG("\n"); + + if (inout == NULL) { + IPAERR("inout is NULL"); + return -EINVAL; + } + + if (int_notify == NULL) { + IPAERR("int_notify is NULL"); + return -EINVAL; + } + + result = ipa3_uc_state_check(); + if (result) { + inout->is_uC_ready = false; + ipa3_ctx->uc_wigig_ctx.uc_ready_cb = inout->notify; + } else { + inout->is_uC_ready = true; + } + ipa3_ctx->uc_wigig_ctx.priv = inout->priv; + ipa3_ctx->uc_wigig_ctx.misc_notify_cb = int_notify; + + *uc_db_pa = ipa3_ctx->ipa_wrapper_base + + ipahal_get_reg_base() + + ipahal_get_reg_mn_ofst( + IPA_UC_MAILBOX_m_n, + W11AD_TO_GSI_DB_m, + W11AD_TO_GSI_DB_n); + + IPADBG("exit\n"); + + return 0; +} +EXPORT_SYMBOL(ipa3_wigig_internal_init); + +static int ipa3_wigig_tx_bit_to_ep( + const u8 tx_bit_num, + enum ipa_client_type *type) +{ + IPADBG("tx_bit_num %d\n", tx_bit_num); + + switch (tx_bit_num) { + case 2: + *type = IPA_CLIENT_WIGIG1_CONS; + break; + case 3: + *type = IPA_CLIENT_WIGIG2_CONS; + break; + case 4: + *type = IPA_CLIENT_WIGIG3_CONS; + break; + case 5: + *type = IPA_CLIENT_WIGIG4_CONS; + break; + default: + IPAERR("invalid tx_bit_num %d\n", tx_bit_num); + return -EINVAL; + } + + IPADBG("exit\n"); + return 0; +} + +static int ipa3_wigig_smmu_map_buffers(bool Rx, + struct ipa_wigig_pipe_setup_info_smmu *pipe_smmu, + void *buff, + bool map) +{ + int result; + + /* data buffers */ + if (Rx) { + struct ipa_wigig_rx_pipe_data_buffer_info_smmu *dbuff_smmu = + (struct ipa_wigig_rx_pipe_data_buffer_info_smmu *)buff; + + int num_elem = + pipe_smmu->desc_ring_size / + IPA_WIGIG_DESC_RING_EL_SIZE; + + result = ipa3_smmu_map_peer_buff( + dbuff_smmu->data_buffer_base_iova, + dbuff_smmu->data_buffer_size * num_elem, + map, + &dbuff_smmu->data_buffer_base, + IPA_SMMU_CB_11AD); + if (result) { + IPAERR( + "failed to %s rx data_buffer %d, num elem %d\n" + , map ? "map" : "unmap", + result, num_elem); + goto fail_map_buff; + } + + } else { + int i; + struct ipa_wigig_tx_pipe_data_buffer_info_smmu *dbuff_smmu = + (struct ipa_wigig_tx_pipe_data_buffer_info_smmu *)buff; + + for (i = 0; i < dbuff_smmu->num_buffers; i++) { + result = ipa3_smmu_map_peer_buff( + *(dbuff_smmu->data_buffer_base_iova + i), + dbuff_smmu->data_buffer_size, + map, + (dbuff_smmu->data_buffer_base + i), + IPA_SMMU_CB_11AD); + if (result) { + IPAERR( + "%d: failed to %s tx data buffer %d\n" + , i, map ? "map" : "unmap", + result); + for (i--; i >= 0; i--) { + result = ipa3_smmu_map_peer_buff( + *(dbuff_smmu->data_buffer_base_iova + + i), + dbuff_smmu->data_buffer_size, + !map, + (dbuff_smmu->data_buffer_base + + i), + IPA_SMMU_CB_11AD); + } + goto fail_map_buff; + } + } + } + + IPADBG("exit\n"); + return 0; + +fail_map_buff: + return result; +} + +static int ipa3_wigig_smmu_map_reg(phys_addr_t phys_addr, bool map, + enum ipa_smmu_cb_type cb_type) +{ + struct ipa_wigig_smmu_reg_addr *entry; + struct ipa_wigig_smmu_reg_addr *next; + int result = 0; + + IPADBG("addr %pa, %s\n", &phys_addr, map ? "map" : "unmap"); + mutex_lock(&smmu_lock); + list_for_each_entry_safe(entry, next, &smmu_reg_addr_list, link) { + if ((entry->phys_addr == phys_addr) && + (entry->cb_type == cb_type)) { + IPADBG("cb %d, page %pa already mapped, ", cb_type, + &phys_addr); + if (map) { + entry->count++; + IPADBG("inc to %d\n", (entry->count)); + } else { + --entry->count; + IPADBG("dec to %d\n", entry->count); + if (!(entry->count)) { + IPADBG("unmap and delete\n"); + result = ipa3_smmu_map_peer_reg( + phys_addr, map, cb_type); + if (result) { + IPAERR("failed to unmap %pa\n", + &phys_addr); + goto finish; + } + list_del(&entry->link); + kfree(entry); + } + } + goto finish; + } + } + IPADBG("new page found %pa, map and add to list CB %d\n", &phys_addr, + cb_type); + result = ipa3_smmu_map_peer_reg(phys_addr, map, cb_type); + if (result) { + IPAERR("failed to map %pa\n", &phys_addr); + goto finish; + } + + entry = kzalloc(sizeof(*entry), GFP_KERNEL); + if (entry == NULL) { + IPAERR("couldn't allocate for %pa\n", &phys_addr); + ipa3_smmu_map_peer_reg(phys_addr, !map, cb_type); + result = -ENOMEM; + goto finish; + } + INIT_LIST_HEAD(&entry->link); + entry->phys_addr = phys_addr; + entry->cb_type = cb_type; + entry->count = 1; + list_add(&entry->link, &smmu_reg_addr_list); + +finish: + mutex_unlock(&smmu_lock); + IPADBG("exit\n"); + return result; +} + +static int ipa3_wigig_smmu_map_ring(u64 iova, u32 size, bool map, + struct sg_table *sgt, enum ipa_smmu_cb_type cb_type) +{ + struct ipa_wigig_smmu_ring_addr *entry; + struct ipa_wigig_smmu_ring_addr *next; + int result = 0; + + IPADBG("iova %llX, %s\n", iova, map ? "map" : "unmap"); + mutex_lock(&smmu_lock); + list_for_each_entry_safe(entry, next, &smmu_ring_addr_list, link) { + if ((entry->iova == iova) && + (entry->cb_type == cb_type)) { + IPADBG("cb %d, page 0x%llX already mapped, ", cb_type, + iova); + if (map) { + entry->count++; + IPADBG("inc to %d\n", (entry->count)); + } else { + --entry->count; + IPADBG("dec to %d\n", entry->count); + if (!(entry->count)) { + IPADBG("unmap and delete\n"); + result = ipa3_smmu_map_peer_buff( + iova, size, map, sgt, cb_type); + if (result) { + IPAERR( + "failed to unmap 0x%llX\n", + iova); + goto finish; + } + list_del(&entry->link); + kfree(entry); + } + } + goto finish; + } + } + IPADBG("new page found 0x%llX, map and add to list\n", iova); + result = ipa3_smmu_map_peer_buff(iova, size, map, sgt, cb_type); + if (result) { + IPAERR("failed to map 0x%llX\n", iova); + goto finish; + } + + entry = kzalloc(sizeof(*entry), GFP_KERNEL); + if (entry == NULL) { + IPAERR("couldn't allocate for 0x%llX\n", iova); + ipa3_smmu_map_peer_buff(iova, size, !map, sgt, cb_type); + result = -ENOMEM; + goto finish; + } + INIT_LIST_HEAD(&entry->link); + entry->iova = iova; + entry->cb_type = cb_type; + entry->count = 1; + list_add(&entry->link, &smmu_ring_addr_list); + +finish: + mutex_unlock(&smmu_lock); + IPADBG("exit\n"); + return result; +} + +static int ipa3_wigig_smmu_map_channel(bool Rx, + struct ipa_wigig_pipe_setup_info_smmu *pipe_smmu, + void *buff, + bool map) +{ + int result = 0; + struct ipa_smmu_cb_ctx *smmu_ctx = ipa3_get_smmu_ctx(IPA_SMMU_CB_11AD); + + IPADBG("\n"); + + /* + * -------------------------------------------------------------------- + * entity |HWHEAD|HWTAIL|HWHEAD|HWTAIL| misc | buffers| rings| + * |Sring |Sring |Dring |Dring | regs | | | + * -------------------------------------------------------------------- + * GSI (apps CB) | TX |RX, TX| |RX, TX| | |Rx, TX| + * -------------------------------------------------------------------- + * IPA (11AD CB) | | | | | | RX, TX | | + * -------------------------------------------------------------------- + * uc (uC CB) | RX | | TX | |always| | | + * -------------------------------------------------------------------- + * + * buffers are mapped to 11AD CB. in case this context bank is shared, + * mapping is done by 11ad driver only and applies to both 11ad and + * IPA HWs (page tables are shared). Otherwise, mapping is done here. + */ + + if (!smmu_ctx) { + IPAERR("11AD SMMU ctx is null\n"); + return -EINVAL; + } + + if (Rx) { + IPADBG("RX %s status_ring_HWHEAD_pa %pa uC CB\n", + map ? "map" : "unmap", + &pipe_smmu->status_ring_HWHEAD_pa); + result = ipa3_wigig_smmu_map_reg( + rounddown(pipe_smmu->status_ring_HWHEAD_pa, PAGE_SIZE), + map, + IPA_SMMU_CB_UC); + if (result) { + IPAERR( + "failed to %s status_ring_HWAHEAD %d\n", + map ? "map" : "unmap", + result); + goto fail; + } + } else { + IPADBG("TX %s status_ring_HWHEAD_pa %pa AP CB\n", + map ? "map" : "unmap", + &pipe_smmu->status_ring_HWHEAD_pa); + result = ipa3_wigig_smmu_map_reg( + rounddown(pipe_smmu->status_ring_HWHEAD_pa, + PAGE_SIZE), + map, + IPA_SMMU_CB_AP); + if (result) { + IPAERR( + "failed to %s status_ring_HWAHEAD %d\n", + map ? "map" : "unmap", + result); + goto fail; + } + + IPADBG("TX %s desc_ring_HWHEAD_pa %pa uC CB\n", + map ? "map" : "unmap", + &pipe_smmu->desc_ring_HWHEAD_pa); + result = ipa3_wigig_smmu_map_reg( + rounddown(pipe_smmu->desc_ring_HWHEAD_pa, + PAGE_SIZE), + map, + IPA_SMMU_CB_UC); + if (result) { + IPAERR("failed to %s desc_ring_HWHEAD %d\n", + map ? "map" : "unmap", + result); + goto fail_desc_HWHEAD; + } + } + + IPADBG("%s status_ring_HWTAIL_pa %pa AP CB\n", + map ? "map" : "unmap", + &pipe_smmu->status_ring_HWTAIL_pa); + result = ipa3_wigig_smmu_map_reg( + rounddown(pipe_smmu->status_ring_HWTAIL_pa, PAGE_SIZE), + map, + IPA_SMMU_CB_AP); + if (result) { + IPAERR( + "failed to %s status_ring_HWTAIL %d\n", + map ? "map" : "unmap", + result); + goto fail_status_HWTAIL; + } + + IPADBG("%s desc_ring_HWTAIL_pa %pa AP CB\n", + map ? "map" : "unmap", + &pipe_smmu->desc_ring_HWTAIL_pa); + result = ipa3_wigig_smmu_map_reg( + rounddown(pipe_smmu->desc_ring_HWTAIL_pa, PAGE_SIZE), + map, + IPA_SMMU_CB_AP); + if (result) { + IPAERR("failed to %s desc_ring_HWTAIL %d\n", + map ? "map" : "unmap", + result); + goto fail_desc_HWTAIL; + } + + /* rings */ + IPADBG("%s desc_ring_base_iova %llX AP CB\n", + map ? "map" : "unmap", + pipe_smmu->desc_ring_base_iova); + result = ipa3_wigig_smmu_map_ring( + pipe_smmu->desc_ring_base_iova, + pipe_smmu->desc_ring_size, + map, + &pipe_smmu->desc_ring_base, + IPA_SMMU_CB_AP); + if (result) { + IPAERR("failed to %s desc_ring_base %d\n", + map ? "map" : "unmap", + result); + goto fail_desc_ring; + } + + IPADBG("%s status_ring_base_iova %llX AP CB\n", + map ? "map" : "unmap", + pipe_smmu->status_ring_base_iova); + result = ipa3_wigig_smmu_map_ring( + pipe_smmu->status_ring_base_iova, + pipe_smmu->status_ring_size, + map, + &pipe_smmu->status_ring_base, + IPA_SMMU_CB_AP); + if (result) { + IPAERR("failed to %s status_ring_base %d\n", + map ? "map" : "unmap", + result); + goto fail_status_ring; + } + + if (!smmu_ctx->shared) { + IPADBG("CB not shared - map buffers\n"); + result = ipa3_wigig_smmu_map_buffers(Rx, pipe_smmu, buff, map); + if (result) { + IPAERR("failed to %s buffers %d\n", + map ? "map" : "unmap", + result); + goto fail_buffers; + } + } + + IPADBG("exit\n"); + return 0; +fail_buffers: + ipa3_wigig_smmu_map_ring( + pipe_smmu->status_ring_base_iova, pipe_smmu->status_ring_size, + !map, &pipe_smmu->status_ring_base, IPA_SMMU_CB_AP); +fail_status_ring: + ipa3_wigig_smmu_map_ring( + pipe_smmu->desc_ring_base_iova, pipe_smmu->desc_ring_size, + !map, &pipe_smmu->desc_ring_base, IPA_SMMU_CB_AP); +fail_desc_ring: + ipa3_wigig_smmu_map_reg( + rounddown(pipe_smmu->desc_ring_HWTAIL_pa, PAGE_SIZE), + !map, IPA_SMMU_CB_AP); +fail_desc_HWTAIL: + ipa3_wigig_smmu_map_reg( + rounddown(pipe_smmu->status_ring_HWTAIL_pa, PAGE_SIZE), + !map, IPA_SMMU_CB_AP); +fail_status_HWTAIL: + if (Rx) + ipa3_wigig_smmu_map_reg( + rounddown(pipe_smmu->status_ring_HWHEAD_pa, PAGE_SIZE), + !map, IPA_SMMU_CB_UC); + else + ipa3_wigig_smmu_map_reg( + rounddown(pipe_smmu->desc_ring_HWHEAD_pa, PAGE_SIZE), + !map, IPA_SMMU_CB_UC); +fail_desc_HWHEAD: + if (!Rx) + ipa3_wigig_smmu_map_reg( + rounddown(pipe_smmu->status_ring_HWHEAD_pa, PAGE_SIZE), + !map, IPA_SMMU_CB_AP); +fail: + return result; +} + +static void ipa_gsi_chan_err_cb(struct gsi_chan_err_notify *notify) +{ + switch (notify->evt_id) { + case GSI_CHAN_INVALID_TRE_ERR: + IPAERR("Got GSI_CHAN_INVALID_TRE_ERR\n"); + break; + case GSI_CHAN_NON_ALLOCATED_EVT_ACCESS_ERR: + IPAERR("Got GSI_CHAN_NON_ALLOCATED_EVT_ACCESS_ERR\n"); + break; + case GSI_CHAN_OUT_OF_BUFFERS_ERR: + IPAERR("Got GSI_CHAN_OUT_OF_BUFFERS_ERR\n"); + break; + case GSI_CHAN_OUT_OF_RESOURCES_ERR: + IPAERR("Got GSI_CHAN_OUT_OF_RESOURCES_ERR\n"); + break; + case GSI_CHAN_UNSUPPORTED_INTER_EE_OP_ERR: + IPAERR("Got GSI_CHAN_UNSUPPORTED_INTER_EE_OP_ERR\n"); + break; + case GSI_CHAN_HWO_1_ERR: + IPAERR("Got GSI_CHAN_HWO_1_ERR\n"); + break; + default: + IPAERR("Unexpected err evt: %d\n", notify->evt_id); + } + ipa_assert(); +} + +static void ipa_gsi_evt_ring_err_cb(struct gsi_evt_err_notify *notify) +{ + switch (notify->evt_id) { + case GSI_EVT_OUT_OF_BUFFERS_ERR: + IPAERR("Got GSI_EVT_OUT_OF_BUFFERS_ERR\n"); + break; + case GSI_EVT_OUT_OF_RESOURCES_ERR: + IPAERR("Got GSI_EVT_OUT_OF_RESOURCES_ERR\n"); + break; + case GSI_EVT_UNSUPPORTED_INTER_EE_OP_ERR: + IPAERR("Got GSI_EVT_UNSUPPORTED_INTER_EE_OP_ERR\n"); + break; + case GSI_EVT_EVT_RING_EMPTY_ERR: + IPAERR("Got GSI_EVT_EVT_RING_EMPTY_ERR\n"); + break; + default: + IPAERR("Unexpected err evt: %d\n", notify->evt_id); + } + ipa_assert(); +} + +static uint16_t int_modt = 15; +static uint8_t int_modc = 200; +static uint8_t tx_hwtail_mod_threshold = 200; +static uint8_t rx_hwtail_mod_threshold = 200; + +static int ipa3_wigig_config_gsi(bool Rx, + bool smmu_en, + void *pipe_info, + void *buff, + const struct ipa_gsi_ep_config *ep_gsi, + struct ipa3_ep_context *ep) +{ + struct gsi_evt_ring_props evt_props; + struct gsi_chan_props channel_props; + union __packed gsi_channel_scratch gsi_scratch; + int gsi_res; + struct ipa_wigig_pipe_setup_info_smmu *pipe_smmu; + struct ipa_wigig_pipe_setup_info *pipe; + struct ipa_wigig_rx_pipe_data_buffer_info *rx_dbuff; + struct ipa_wigig_rx_pipe_data_buffer_info_smmu *rx_dbuff_smmu; + struct ipa_wigig_tx_pipe_data_buffer_info *tx_dbuff; + struct ipa_wigig_tx_pipe_data_buffer_info_smmu *tx_dbuff_smmu; + + IPADBG("%s, %s\n", Rx ? "Rx" : "Tx", smmu_en ? "smmu en" : "smmu dis"); + + /* alloc event ring */ + memset(&evt_props, 0, sizeof(evt_props)); + evt_props.intf = GSI_EVT_CHTYPE_11AD_EV; + evt_props.re_size = GSI_EVT_RING_RE_SIZE_16B; + evt_props.intr = GSI_INTR_MSI; + evt_props.intvec = 0; + evt_props.exclusive = true; + evt_props.err_cb = ipa_gsi_evt_ring_err_cb; + evt_props.user_data = NULL; + evt_props.int_modc = int_modc; + evt_props.int_modt = int_modt; + evt_props.ring_base_vaddr = NULL; + + if (smmu_en) { + pipe_smmu = (struct ipa_wigig_pipe_setup_info_smmu *)pipe_info; + evt_props.ring_base_addr = + pipe_smmu->desc_ring_base_iova; + evt_props.ring_len = pipe_smmu->desc_ring_size; + evt_props.msi_addr = pipe_smmu->desc_ring_HWTAIL_pa; + } else { + pipe = (struct ipa_wigig_pipe_setup_info *)pipe_info; + evt_props.ring_base_addr = pipe->desc_ring_base_pa; + evt_props.ring_len = pipe->desc_ring_size; + evt_props.msi_addr = pipe->desc_ring_HWTAIL_pa; + } + + gsi_res = gsi_alloc_evt_ring(&evt_props, + ipa3_ctx->gsi_dev_hdl, + &ep->gsi_evt_ring_hdl); + if (gsi_res != GSI_STATUS_SUCCESS) { + IPAERR("Error allocating event ring: %d\n", gsi_res); + return -EFAULT; + } + + /* event scratch not configured by SW for TX channels */ + if (Rx) { + union __packed gsi_evt_scratch evt_scratch; + + memset(&evt_scratch, 0, sizeof(evt_scratch)); + evt_scratch.w11ad.update_status_hwtail_mod_threshold = + rx_hwtail_mod_threshold; + gsi_res = gsi_write_evt_ring_scratch(ep->gsi_evt_ring_hdl, + evt_scratch); + if (gsi_res != GSI_STATUS_SUCCESS) { + IPAERR("Error writing WIGIG event ring scratch: %d\n", + gsi_res); + goto fail_write_evt_scratch; + } + } + + ep->gsi_mem_info.evt_ring_len = evt_props.ring_len; + ep->gsi_mem_info.evt_ring_base_addr = evt_props.ring_base_addr; + ep->gsi_mem_info.evt_ring_base_vaddr = evt_props.ring_base_vaddr; + + /* alloc channel ring */ + memset(&channel_props, 0, sizeof(channel_props)); + memset(&gsi_scratch, 0, sizeof(gsi_scratch)); + + if (Rx) + channel_props.dir = GSI_CHAN_DIR_TO_GSI; + else + channel_props.dir = GSI_CHAN_DIR_FROM_GSI; + + channel_props.re_size = GSI_CHAN_RE_SIZE_16B; + channel_props.prot = GSI_CHAN_PROT_11AD; + channel_props.ch_id = ep_gsi->ipa_gsi_chan_num; + channel_props.evt_ring_hdl = ep->gsi_evt_ring_hdl; + channel_props.xfer_cb = NULL; + + channel_props.db_in_bytes = 0; + channel_props.use_db_eng = GSI_CHAN_DB_MODE; + channel_props.max_prefetch = GSI_ONE_PREFETCH_SEG; + channel_props.prefetch_mode = ep_gsi->prefetch_mode; + channel_props.empty_lvl_threshold = ep_gsi->prefetch_threshold; + channel_props.low_weight = 1; + channel_props.err_cb = ipa_gsi_chan_err_cb; + + channel_props.ring_base_vaddr = NULL; + + if (Rx) { + if (smmu_en) { + rx_dbuff_smmu = + (struct ipa_wigig_rx_pipe_data_buffer_info_smmu *)buff; + + channel_props.ring_base_addr = + pipe_smmu->status_ring_base_iova; + channel_props.ring_len = + pipe_smmu->status_ring_size; + + gsi_scratch.rx_11ad.status_ring_hwtail_address_lsb = + IPA_WIGIG_LSB( + pipe_smmu->status_ring_HWTAIL_pa); + gsi_scratch.rx_11ad.status_ring_hwtail_address_msb = + IPA_WIGIG_MSB( + pipe_smmu->status_ring_HWTAIL_pa); + + gsi_scratch.rx_11ad.data_buffers_base_address_lsb = + IPA_WIGIG_LSB( + rx_dbuff_smmu->data_buffer_base_iova); + gsi_scratch.rx_11ad.data_buffers_base_address_msb = + IPA_WIGIG_MSB( + rx_dbuff_smmu->data_buffer_base_iova); + gsi_scratch.rx_11ad.fixed_data_buffer_size_pow_2 = + ilog2(rx_dbuff_smmu->data_buffer_size); + } else { + rx_dbuff = + (struct ipa_wigig_rx_pipe_data_buffer_info *)buff; + + channel_props.ring_base_addr = + pipe->status_ring_base_pa; + channel_props.ring_len = pipe->status_ring_size; + + gsi_scratch.rx_11ad.status_ring_hwtail_address_lsb = + IPA_WIGIG_LSB(pipe->status_ring_HWTAIL_pa); + gsi_scratch.rx_11ad.status_ring_hwtail_address_msb = + IPA_WIGIG_MSB(pipe->status_ring_HWTAIL_pa); + + gsi_scratch.rx_11ad.data_buffers_base_address_lsb = + IPA_WIGIG_LSB(rx_dbuff->data_buffer_base_pa); + gsi_scratch.rx_11ad.data_buffers_base_address_msb = + IPA_WIGIG_MSB(rx_dbuff->data_buffer_base_pa); + gsi_scratch.rx_11ad.fixed_data_buffer_size_pow_2 = + ilog2(rx_dbuff->data_buffer_size); + } + IPADBG("rx scratch: status_ring_hwtail_address_lsb 0x%X\n", + gsi_scratch.rx_11ad.status_ring_hwtail_address_lsb); + IPADBG("rx scratch: status_ring_hwtail_address_msb 0x%X\n", + gsi_scratch.rx_11ad.status_ring_hwtail_address_msb); + IPADBG("rx scratch: data_buffers_base_address_lsb 0x%X\n", + gsi_scratch.rx_11ad.data_buffers_base_address_lsb); + IPADBG("rx scratch: data_buffers_base_address_msb 0x%X\n", + gsi_scratch.rx_11ad.data_buffers_base_address_msb); + IPADBG("rx scratch: fixed_data_buffer_size_pow_2 %d\n", + gsi_scratch.rx_11ad.fixed_data_buffer_size_pow_2); + IPADBG("rx scratch 0x[%X][%X][%X][%X]\n", + gsi_scratch.data.word1, + gsi_scratch.data.word2, + gsi_scratch.data.word3, + gsi_scratch.data.word4); + } else { + if (smmu_en) { + tx_dbuff_smmu = + (struct ipa_wigig_tx_pipe_data_buffer_info_smmu *)buff; + channel_props.ring_base_addr = + pipe_smmu->desc_ring_base_iova; + channel_props.ring_len = + pipe_smmu->desc_ring_size; + + gsi_scratch.tx_11ad.status_ring_hwtail_address_lsb = + IPA_WIGIG_LSB( + pipe_smmu->status_ring_HWTAIL_pa); + gsi_scratch.tx_11ad.status_ring_hwhead_address_lsb = + IPA_WIGIG_LSB( + pipe_smmu->status_ring_HWHEAD_pa); + gsi_scratch.tx_11ad.status_ring_hwhead_hwtail_8_msb = + IPA_WIGIG_8_MSB( + pipe_smmu->status_ring_HWHEAD_pa); + + gsi_scratch.tx_11ad.fixed_data_buffer_size_pow_2 = + ilog2(tx_dbuff_smmu->data_buffer_size); + + gsi_scratch.tx_11ad.status_ring_num_elem = + pipe_smmu->status_ring_size / + IPA_WIGIG_STATUS_RING_EL_SIZE; + } else { + tx_dbuff = + (struct ipa_wigig_tx_pipe_data_buffer_info *)buff; + + channel_props.ring_base_addr = pipe->desc_ring_base_pa; + channel_props.ring_len = pipe->desc_ring_size; + + gsi_scratch.tx_11ad.status_ring_hwtail_address_lsb = + IPA_WIGIG_LSB( + pipe->status_ring_HWTAIL_pa); + gsi_scratch.tx_11ad.status_ring_hwhead_address_lsb = + IPA_WIGIG_LSB( + pipe->status_ring_HWHEAD_pa); + gsi_scratch.tx_11ad.status_ring_hwhead_hwtail_8_msb = + IPA_WIGIG_8_MSB(pipe->status_ring_HWHEAD_pa); + + gsi_scratch.tx_11ad.status_ring_num_elem = + pipe->status_ring_size / + IPA_WIGIG_STATUS_RING_EL_SIZE; + + gsi_scratch.tx_11ad.fixed_data_buffer_size_pow_2 = + ilog2(tx_dbuff->data_buffer_size); + } + gsi_scratch.tx_11ad.update_status_hwtail_mod_threshold = + tx_hwtail_mod_threshold; + IPADBG("tx scratch: status_ring_hwtail_address_lsb 0x%X\n", + gsi_scratch.tx_11ad.status_ring_hwtail_address_lsb); + IPADBG("tx scratch: status_ring_hwhead_address_lsb 0x%X\n", + gsi_scratch.tx_11ad.status_ring_hwhead_address_lsb); + IPADBG("tx scratch: status_ring_hwhead_hwtail_8_msb 0x%X\n", + gsi_scratch.tx_11ad.status_ring_hwhead_hwtail_8_msb); + IPADBG("tx scratch:status_ring_num_elem %d\n", + gsi_scratch.tx_11ad.status_ring_num_elem); + IPADBG("tx scratch:fixed_data_buffer_size_pow_2 %d\n", + gsi_scratch.tx_11ad.fixed_data_buffer_size_pow_2); + IPADBG("tx scratch 0x[%X][%X][%X][%X]\n", + gsi_scratch.data.word1, + gsi_scratch.data.word2, + gsi_scratch.data.word3, + gsi_scratch.data.word4); + } + + IPADBG("ch_id: %d\n", channel_props.ch_id); + IPADBG("evt_ring_hdl: %ld\n", channel_props.evt_ring_hdl); + IPADBG("re_size: %d\n", channel_props.re_size); + IPADBG("GSI channel ring len: %d\n", channel_props.ring_len); + IPADBG("channel ring base addr = 0x%llX\n", + (unsigned long long)channel_props.ring_base_addr); + + IPADBG("Allocating GSI channel\n"); + gsi_res = gsi_alloc_channel(&channel_props, + ipa3_ctx->gsi_dev_hdl, + &ep->gsi_chan_hdl); + if (gsi_res != GSI_STATUS_SUCCESS) { + IPAERR("gsi_alloc_channel failed %d\n", gsi_res); + goto fail_alloc_channel; + } + + IPADBG("Writing Channel scratch\n"); + ep->gsi_mem_info.chan_ring_len = channel_props.ring_len; + ep->gsi_mem_info.chan_ring_base_addr = channel_props.ring_base_addr; + ep->gsi_mem_info.chan_ring_base_vaddr = + channel_props.ring_base_vaddr; + + gsi_res = gsi_write_channel_scratch(ep->gsi_chan_hdl, + gsi_scratch); + if (gsi_res != GSI_STATUS_SUCCESS) { + IPAERR("gsi_write_channel_scratch failed %d\n", + gsi_res); + goto fail_write_channel_scratch; + } + + IPADBG("exit\n"); + + return 0; +fail_write_channel_scratch: + gsi_dealloc_channel(ep->gsi_chan_hdl); +fail_alloc_channel: +fail_write_evt_scratch: + gsi_dealloc_evt_ring(ep->gsi_evt_ring_hdl); + return -EFAULT; +} + +static int ipa3_wigig_config_uc(bool init, + bool Rx, + u8 wifi_ch, + u8 gsi_ch, + phys_addr_t HWHEAD) +{ + struct ipa_mem_buffer cmd; + enum ipa_cpu_2_hw_offload_commands command; + int result; + + IPADBG("%s\n", init ? "init" : "Deinit"); + if (init) { + struct IpaHwOffloadSetUpCmdData_t_v4_0 *cmd_data; + + cmd.size = sizeof(*cmd_data); + cmd.base = dma_alloc_coherent(ipa3_ctx->uc_pdev, cmd.size, + &cmd.phys_base, GFP_KERNEL); + if (cmd.base == NULL) { + IPAERR("fail to get DMA memory.\n"); + return -ENOMEM; + } + + cmd_data = + (struct IpaHwOffloadSetUpCmdData_t_v4_0 *)cmd.base; + + cmd_data->protocol = IPA_HW_PROTOCOL_11ad; + cmd_data->SetupCh_params.w11ad_params.dir = + Rx ? W11AD_RX : W11AD_TX; + cmd_data->SetupCh_params.w11ad_params.gsi_ch = gsi_ch; + cmd_data->SetupCh_params.w11ad_params.wifi_ch = wifi_ch; + cmd_data->SetupCh_params.w11ad_params.wifi_hp_addr_msb = + IPA_WIGIG_MSB(HWHEAD); + cmd_data->SetupCh_params.w11ad_params.wifi_hp_addr_lsb = + IPA_WIGIG_LSB(HWHEAD); + command = IPA_CPU_2_HW_CMD_OFFLOAD_CHANNEL_SET_UP; + + } else { + struct IpaHwOffloadCommonChCmdData_t_v4_0 *cmd_data; + + cmd.size = sizeof(*cmd_data); + cmd.base = dma_alloc_coherent(ipa3_ctx->uc_pdev, cmd.size, + &cmd.phys_base, GFP_KERNEL); + if (cmd.base == NULL) { + IPAERR("fail to get DMA memory.\n"); + return -ENOMEM; + } + + cmd_data = + (struct IpaHwOffloadCommonChCmdData_t_v4_0 *)cmd.base; + + cmd_data->protocol = IPA_HW_PROTOCOL_11ad; + cmd_data->CommonCh_params.w11ad_params.gsi_ch = gsi_ch; + command = IPA_CPU_2_HW_CMD_OFFLOAD_CHANNEL_TEAR_DOWN; + } + + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + + result = ipa3_uc_send_cmd((u32)(cmd.phys_base), + command, + IPA_HW_2_CPU_OFFLOAD_CMD_STATUS_SUCCESS, + false, 10 * HZ); + if (result) { + IPAERR("fail to %s uc for %s gsi channel %d\n", + init ? "init" : "deinit", + Rx ? "Rx" : "Tx", gsi_ch); + } + + dma_free_coherent(ipa3_ctx->uc_pdev, + cmd.size, cmd.base, cmd.phys_base); + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + + IPADBG("exit\n"); + return result; +} + +int ipa3_conn_wigig_rx_pipe_i(void *in, struct ipa_wigig_conn_out_params *out, + struct dentry **parent) +{ + int ipa_ep_idx; + struct ipa3_ep_context *ep; + struct ipa_ep_cfg ep_cfg; + enum ipa_client_type rx_client = IPA_CLIENT_WIGIG_PROD; + bool is_smmu_enabled; + struct ipa_wigig_conn_rx_in_params_smmu *input_smmu = NULL; + struct ipa_wigig_conn_rx_in_params *input = NULL; + const struct ipa_gsi_ep_config *ep_gsi; + void *pipe_info; + void *buff; + phys_addr_t status_ring_HWHEAD_pa; + int result; + + IPADBG("\n"); + + *parent = wigig_dent; + + ipa_ep_idx = ipa_get_ep_mapping(rx_client); + if (ipa_ep_idx == IPA_EP_NOT_ALLOCATED || + ipa_ep_idx >= ipa3_get_max_num_pipes()) { + IPAERR("fail to get ep (IPA_CLIENT_WIGIG_PROD) %d.\n", + ipa_ep_idx); + return -EFAULT; + } + + ep = &ipa3_ctx->ep[ipa_ep_idx]; + if (ep->valid) { + IPAERR("EP %d already allocated.\n", ipa_ep_idx); + return -EFAULT; + } + + if (ep->gsi_offload_state) { + IPAERR("WIGIG channel bad state 0x%X\n", + ep->gsi_offload_state); + return -EFAULT; + } + + ep_gsi = ipa_get_gsi_ep_info(rx_client); + if (!ep_gsi) { + IPAERR("Failed getting GSI EP info for client=%d\n", + rx_client); + return -EPERM; + } + + memset(ep, 0, offsetof(struct ipa3_ep_context, sys)); + + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + + /* setup rx ep cfg */ + ep->valid = 1; + ep->client = rx_client; + result = ipa3_disable_data_path(ipa_ep_idx); + if (result) { + IPAERR("disable data path failed res=%d clnt=%d.\n", result, + ipa_ep_idx); + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + return -EFAULT; + } + + is_smmu_enabled = !ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_11AD]; + if (is_smmu_enabled) { + struct ipa_wigig_rx_pipe_data_buffer_info_smmu *dbuff_smmu; + + input_smmu = (struct ipa_wigig_conn_rx_in_params_smmu *)in; + dbuff_smmu = &input_smmu->dbuff_smmu; + ep->client_notify = input_smmu->notify; + ep->priv = input_smmu->priv; + + IPADBG( + "desc_ring_base_iova 0x%llX desc_ring_size %d status_ring_base_iova 0x%llX status_ring_size %d", + (unsigned long long)input_smmu->pipe_smmu.desc_ring_base_iova, + input_smmu->pipe_smmu.desc_ring_size, + (unsigned long long)input_smmu->pipe_smmu.status_ring_base_iova, + input_smmu->pipe_smmu.status_ring_size); + IPADBG("data_buffer_base_iova 0x%llX data_buffer_size %d", + (unsigned long long)dbuff_smmu->data_buffer_base_iova, + input_smmu->dbuff_smmu.data_buffer_size); + + if (IPA_WIGIG_MSB( + dbuff_smmu->data_buffer_base_iova) & + 0xFFFFFF00) { + IPAERR( + "data_buffers_base_address_msb is over the 8 bit limit (0x%llX)\n", + (unsigned long long)dbuff_smmu->data_buffer_base_iova); + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + return -EFAULT; + } + if (dbuff_smmu->data_buffer_size >> 16) { + IPAERR( + "data_buffer_size is over the 16 bit limit (%d)\n" + , dbuff_smmu->data_buffer_size); + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + return -EFAULT; + } + } else { + input = (struct ipa_wigig_conn_rx_in_params *)in; + ep->client_notify = input->notify; + ep->priv = input->priv; + + IPADBG( + "desc_ring_base_pa %pa desc_ring_size %d status_ring_base_pa %pa status_ring_size %d", + &input->pipe.desc_ring_base_pa, + input->pipe.desc_ring_size, + &input->pipe.status_ring_base_pa, + input->pipe.status_ring_size); + IPADBG("data_buffer_base_pa %pa data_buffer_size %d", + &input->dbuff.data_buffer_base_pa, + input->dbuff.data_buffer_size); + + if ( + IPA_WIGIG_MSB(input->dbuff.data_buffer_base_pa) & 0xFFFFFF00) { + IPAERR( + "data_buffers_base_address_msb is over the 8 bit limit (0x%pa)\n" + , &input->dbuff.data_buffer_base_pa); + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + return -EFAULT; + } + if (input->dbuff.data_buffer_size >> 16) { + IPAERR( + "data_buffer_size is over the 16 bit limit (0x%X)\n" + , input->dbuff.data_buffer_size); + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + return -EFAULT; + } + } + + memset(&ep_cfg, 0, sizeof(ep_cfg)); + ep_cfg.nat.nat_en = IPA_SRC_NAT; + ep_cfg.hdr.hdr_len = ETH_HLEN; + ep_cfg.hdr.hdr_ofst_pkt_size_valid = 0; + ep_cfg.hdr.hdr_ofst_pkt_size = 0; + ep_cfg.hdr.hdr_additional_const_len = 0; + ep_cfg.hdr_ext.hdr_little_endian = true; + ep_cfg.hdr.hdr_ofst_metadata_valid = 0; + ep_cfg.hdr.hdr_metadata_reg_valid = 1; + ep_cfg.mode.mode = IPA_BASIC; + + + if (ipa3_cfg_ep(ipa_ep_idx, &ep_cfg)) { + IPAERR("fail to setup rx pipe cfg\n"); + result = -EFAULT; + goto fail; + } + + if (is_smmu_enabled) { + result = ipa3_wigig_smmu_map_channel(true, + &input_smmu->pipe_smmu, + &input_smmu->dbuff_smmu, + true); + if (result) { + IPAERR("failed to setup rx pipe smmu map\n"); + result = -EFAULT; + goto fail; + } + + pipe_info = &input_smmu->pipe_smmu; + buff = &input_smmu->dbuff_smmu; + status_ring_HWHEAD_pa = + input_smmu->pipe_smmu.status_ring_HWHEAD_pa; + } else { + pipe_info = &input->pipe; + buff = &input->dbuff; + status_ring_HWHEAD_pa = + input->pipe.status_ring_HWHEAD_pa; + } + + result = ipa3_wigig_config_gsi(true, + is_smmu_enabled, + pipe_info, + buff, + ep_gsi, ep); + if (result) + goto fail_gsi; + + result = ipa3_wigig_config_uc( + true, true, 0, + ep_gsi->ipa_gsi_chan_num, + status_ring_HWHEAD_pa); + if (result) + goto fail_uc_config; + + ipa3_install_dflt_flt_rules(ipa_ep_idx); + + out->client = IPA_CLIENT_WIGIG_PROD; + ep->gsi_offload_state |= IPA_WIGIG_CONNECTED; + + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + + IPADBG("wigig rx pipe connected successfully\n"); + IPADBG("exit\n"); + + return 0; + +fail_uc_config: + /* Release channel and evt*/ + ipa3_release_gsi_channel(ipa_ep_idx); +fail_gsi: + if (input_smmu) + ipa3_wigig_smmu_map_channel(true, &input_smmu->pipe_smmu, + &input_smmu->dbuff_smmu, false); +fail: + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + return result; +} +EXPORT_SYMBOL(ipa3_conn_wigig_rx_pipe_i); + +int ipa3_conn_wigig_client_i(void *in, + struct ipa_wigig_conn_out_params *out, + ipa_notify_cb tx_notify, + void *priv) +{ + int ipa_ep_idx; + struct ipa3_ep_context *ep; + struct ipa_ep_cfg ep_cfg; + enum ipa_client_type tx_client; + bool is_smmu_enabled; + struct ipa_wigig_conn_tx_in_params_smmu *input_smmu = NULL; + struct ipa_wigig_conn_tx_in_params *input = NULL; + const struct ipa_gsi_ep_config *ep_gsi; + u32 aggr_byte_limit; + int result; + void *pipe_info; + void *buff; + phys_addr_t desc_ring_HWHEAD_pa; + u8 wifi_ch; + + IPADBG("\n"); + + is_smmu_enabled = !ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_11AD]; + if (is_smmu_enabled) { + input_smmu = (struct ipa_wigig_conn_tx_in_params_smmu *)in; + + IPADBG( + "desc_ring_base_iova 0x%llX desc_ring_size %d status_ring_base_iova 0x%llX status_ring_size %d", + (unsigned long long)input_smmu->pipe_smmu.desc_ring_base_iova, + input_smmu->pipe_smmu.desc_ring_size, + (unsigned long long)input_smmu->pipe_smmu.status_ring_base_iova, + input_smmu->pipe_smmu.status_ring_size); + IPADBG("num buffers %d, data buffer size %d\n", + input_smmu->dbuff_smmu.num_buffers, + input_smmu->dbuff_smmu.data_buffer_size); + + if (ipa3_wigig_tx_bit_to_ep(input_smmu->int_gen_tx_bit_num, + &tx_client)) { + return -EINVAL; + } + if (input_smmu->dbuff_smmu.data_buffer_size >> 16) { + IPAERR( + "data_buffer_size is over the 16 bit limit (0x%X)\n" + , input_smmu->dbuff_smmu.data_buffer_size); + return -EFAULT; + } + + if (IPA_WIGIG_8_MSB( + input_smmu->pipe_smmu.status_ring_HWHEAD_pa) + != IPA_WIGIG_8_MSB( + input_smmu->pipe_smmu.status_ring_HWTAIL_pa)) { + IPAERR( + "status ring HWHEAD and HWTAIL differ in 8 MSbs head 0x%llX tail 0x%llX\n" + , input_smmu->pipe_smmu.status_ring_HWHEAD_pa, + input_smmu->pipe_smmu.status_ring_HWTAIL_pa); + return -EFAULT; + } + + wifi_ch = input_smmu->int_gen_tx_bit_num; + + /* convert to kBytes */ + aggr_byte_limit = IPA_ADJUST_AGGR_BYTE_HARD_LIMIT( + input_smmu->dbuff_smmu.data_buffer_size); + } else { + input = (struct ipa_wigig_conn_tx_in_params *)in; + + IPADBG( + "desc_ring_base_pa %pa desc_ring_size %d status_ring_base_pa %pa status_ring_size %d", + &input->pipe.desc_ring_base_pa, + input->pipe.desc_ring_size, + &input->pipe.status_ring_base_pa, + input->pipe.status_ring_size); + IPADBG("data_buffer_size %d", input->dbuff.data_buffer_size); + + if (ipa3_wigig_tx_bit_to_ep(input->int_gen_tx_bit_num, + &tx_client)) { + return -EINVAL; + } + + if (input->dbuff.data_buffer_size >> 16) { + IPAERR( + "data_buffer_size is over the 16 bit limit (0x%X)\n" + , input->dbuff.data_buffer_size); + return -EFAULT; + } + + if (IPA_WIGIG_8_MSB( + input->pipe.status_ring_HWHEAD_pa) + != IPA_WIGIG_8_MSB( + input->pipe.status_ring_HWTAIL_pa)) { + IPAERR( + "status ring HWHEAD and HWTAIL differ in 8 MSbs head 0x%llX tail 0x%llX\n" + , input->pipe.status_ring_HWHEAD_pa, + input->pipe.status_ring_HWTAIL_pa); + return -EFAULT; + } + + wifi_ch = input->int_gen_tx_bit_num; + + /* convert to kBytes */ + aggr_byte_limit = IPA_ADJUST_AGGR_BYTE_HARD_LIMIT( + input->dbuff.data_buffer_size); + } + IPADBG("client type is %d\n", tx_client); + + ipa_ep_idx = ipa_get_ep_mapping(tx_client); + if (ipa_ep_idx == IPA_EP_NOT_ALLOCATED || + ipa_ep_idx >= ipa3_get_max_num_pipes()) { + IPAERR("fail to get ep (%d) %d.\n", + tx_client, ipa_ep_idx); + return -EFAULT; + } + + ep = &ipa3_ctx->ep[ipa_ep_idx]; + if (ep->valid) { + IPAERR("EP %d already allocated.\n", ipa_ep_idx); + return -EFAULT; + } + + if (ep->gsi_offload_state) { + IPAERR("WIGIG channel bad state 0x%X\n", + ep->gsi_offload_state); + return -EFAULT; + } + + ep_gsi = ipa_get_gsi_ep_info(tx_client); + if (!ep_gsi) { + IPAERR("Failed getting GSI EP info for client=%d\n", + tx_client); + return -EFAULT; + } + + memset(ep, 0, offsetof(struct ipa3_ep_context, sys)); + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + + /* setup tx ep cfg */ + ep->valid = 1; + ep->client = tx_client; + result = ipa3_disable_data_path(ipa_ep_idx); + if (result) { + IPAERR("disable data path failed res=%d clnt=%d.\n", result, + ipa_ep_idx); + goto fail; + } + + ep->client_notify = tx_notify; + ep->priv = priv; + + memset(&ep_cfg, 0, sizeof(ep_cfg)); + ep_cfg.nat.nat_en = IPA_DST_NAT; + ep_cfg.hdr.hdr_len = ETH_HLEN; + ep_cfg.hdr.hdr_ofst_pkt_size_valid = 0; + ep_cfg.hdr.hdr_ofst_pkt_size = 0; + ep_cfg.hdr.hdr_additional_const_len = 0; + ep_cfg.hdr_ext.hdr_little_endian = true; + ep_cfg.mode.mode = IPA_BASIC; + + /* config hard byte limit, max is the buffer size (in kB)*/ + ep_cfg.aggr.aggr_en = IPA_ENABLE_AGGR; + ep_cfg.aggr.aggr = IPA_GENERIC; + ep_cfg.aggr.aggr_pkt_limit = 1; + ep_cfg.aggr.aggr_byte_limit = aggr_byte_limit; + ep_cfg.aggr.aggr_hard_byte_limit_en = IPA_ENABLE_AGGR; + + if (ipa3_cfg_ep(ipa_ep_idx, &ep_cfg)) { + IPAERR("fail to setup rx pipe cfg\n"); + result = -EFAULT; + goto fail; + } + + if (is_smmu_enabled) { + result = ipa3_wigig_smmu_map_channel(false, + &input_smmu->pipe_smmu, + &input_smmu->dbuff_smmu, + true); + if (result) { + IPAERR( + "failed to setup tx pipe smmu map client %d (ep %d)\n" + , tx_client, ipa_ep_idx); + result = -EFAULT; + goto fail; + } + + pipe_info = &input_smmu->pipe_smmu; + buff = &input_smmu->dbuff_smmu; + desc_ring_HWHEAD_pa = + input_smmu->pipe_smmu.desc_ring_HWHEAD_pa; + } else { + pipe_info = &input->pipe; + buff = &input->dbuff; + desc_ring_HWHEAD_pa = + input->pipe.desc_ring_HWHEAD_pa; + } + + result = ipa3_wigig_config_gsi(false, + is_smmu_enabled, + pipe_info, + buff, + ep_gsi, ep); + if (result) + goto fail_gsi; + + result = ipa3_wigig_config_uc( + true, false, wifi_ch, + ep_gsi->ipa_gsi_chan_num, + desc_ring_HWHEAD_pa); + if (result) + goto fail_uc_config; + + out->client = tx_client; + ep->gsi_offload_state |= IPA_WIGIG_CONNECTED; + + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + + IPADBG("wigig client %d (ep %d) connected successfully\n", tx_client, + ipa_ep_idx); + return 0; + +fail_uc_config: + /* Release channel and evt*/ + ipa3_release_gsi_channel(ipa_ep_idx); +fail_gsi: + if (input_smmu) + ipa3_wigig_smmu_map_channel(false, &input_smmu->pipe_smmu, + &input_smmu->dbuff_smmu, false); +fail: + ep->valid = 0; + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + return result; +} +EXPORT_SYMBOL(ipa3_conn_wigig_client_i); + +int ipa3_disconn_wigig_pipe_i(enum ipa_client_type client, + struct ipa_wigig_pipe_setup_info_smmu *pipe_smmu, + void *dbuff) +{ + bool is_smmu_enabled; + int ipa_ep_idx; + struct ipa3_ep_context *ep; + const struct ipa_gsi_ep_config *ep_gsi; + int result; + bool rx = false; + + IPADBG("\n"); + + ipa_ep_idx = ipa_get_ep_mapping(client); + if (ipa_ep_idx == IPA_EP_NOT_ALLOCATED || + ipa_ep_idx >= ipa3_get_max_num_pipes()) { + IPAERR("fail to get ep (%d) %d.\n", + client, ipa_ep_idx); + return -EFAULT; + } + + ep = &ipa3_ctx->ep[ipa_ep_idx]; + if (!ep->valid) { + IPAERR("Invalid EP\n"); + return -EFAULT; + } + + ep_gsi = ipa_get_gsi_ep_info(client); + if (!ep_gsi) { + IPAERR("Failed getting GSI EP info for client=%d\n", + client); + return -EFAULT; + } + + if (ep->gsi_offload_state != IPA_WIGIG_CONNECTED) { + IPAERR("client in bad state(client %d) 0x%X\n", + client, ep->gsi_offload_state); + return -EFAULT; + } + + if (client == IPA_CLIENT_WIGIG_PROD) + rx = true; + + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + + /* Release channel and evt*/ + result = ipa3_release_gsi_channel(ipa_ep_idx); + if (result) { + IPAERR("failed to deallocate channel\n"); + goto fail; + } + + /* only gsi ch number and dir are necessary */ + result = ipa3_wigig_config_uc( + false, rx, 0, + ep_gsi->ipa_gsi_chan_num, 0); + if (result) { + IPAERR("failed uC channel teardown %d\n", result); + WARN_ON(1); + } + + is_smmu_enabled = !ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_11AD]; + if (is_smmu_enabled) { + if (!pipe_smmu || !dbuff) { + IPAERR("smmu input is null %pK %pK\n", + pipe_smmu, dbuff); + WARN_ON(1); + } else { + result = ipa3_wigig_smmu_map_channel(rx, + pipe_smmu, + dbuff, + false); + if (result) { + IPAERR( + "failed to unmap pipe smmu %d (ep %d)\n" + , client, ipa_ep_idx); + result = -EFAULT; + goto fail; + } + } + + if (rx) { + if (!list_empty(&smmu_reg_addr_list)) { + IPAERR("smmu_reg_addr_list not empty\n"); + WARN_ON(1); + } + + if (!list_empty(&smmu_ring_addr_list)) { + IPAERR("smmu_ring_addr_list not empty\n"); + WARN_ON(1); + } + } + } else if (pipe_smmu || dbuff) { + IPAERR("smmu input is not null %pK %pK\n", + pipe_smmu, dbuff); + WARN_ON(1); + } + + memset(ep, 0, sizeof(struct ipa3_ep_context)); + + ep->gsi_offload_state = 0; + + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + + IPADBG("client (ep: %d) disconnected\n", ipa_ep_idx); + + IPADBG("exit\n"); + return 0; + +fail: + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + return result; +} +EXPORT_SYMBOL(ipa3_disconn_wigig_pipe_i); + +int ipa3_wigig_uc_msi_init(bool init, + phys_addr_t periph_baddr_pa, + phys_addr_t pseudo_cause_pa, + phys_addr_t int_gen_tx_pa, + phys_addr_t int_gen_rx_pa, + phys_addr_t dma_ep_misc_pa) +{ + int result; + struct ipa_mem_buffer cmd; + enum ipa_cpu_2_hw_offload_commands command; + bool map = false; + + IPADBG("params: %s, %pa, %pa, %pa, %pa, %pa\n", + init ? "init" : "deInit", + &periph_baddr_pa, + &pseudo_cause_pa, + &int_gen_tx_pa, + &int_gen_rx_pa, + &dma_ep_misc_pa); + + /* first make sure registers are SMMU mapped if necessary*/ + if ((!ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_UC])) { + if (init) + map = true; + + IPADBG("SMMU enabled, map %d\n", map); + + result = ipa3_smmu_map_peer_reg( + rounddown(pseudo_cause_pa, PAGE_SIZE), + map, + IPA_SMMU_CB_UC); + if (result) { + IPAERR( + "failed to %s pseudo_cause reg %d\n", + map ? "map" : "unmap", + result); + goto fail; + } + + result = ipa3_smmu_map_peer_reg( + rounddown(int_gen_tx_pa, PAGE_SIZE), + map, + IPA_SMMU_CB_UC); + if (result) { + IPAERR( + "failed to %s int_gen_tx reg %d\n", + map ? "map" : "unmap", + result); + goto fail_gen_tx; + } + + result = ipa3_smmu_map_peer_reg( + rounddown(int_gen_rx_pa, PAGE_SIZE), + map, + IPA_SMMU_CB_UC); + if (result) { + IPAERR( + "failed to %s int_gen_rx reg %d\n", + map ? "map" : "unmap", + result); + goto fail_gen_rx; + } + + result = ipa3_smmu_map_peer_reg( + rounddown(dma_ep_misc_pa, PAGE_SIZE), + map, + IPA_SMMU_CB_UC); + if (result) { + IPAERR( + "failed to %s dma_ep_misc reg %d\n", + map ? "map" : "unmap", + result); + goto fail_dma_ep_misc; + } + } + + /* now send the wigig hw base address to uC*/ + if (init) { + struct IpaHwPeripheralInitCmdData_t *cmd_data; + + cmd.size = sizeof(*cmd_data); + cmd.base = dma_alloc_coherent(ipa3_ctx->uc_pdev, cmd.size, + &cmd.phys_base, GFP_KERNEL); + if (cmd.base == NULL) { + IPAERR("fail to get DMA memory.\n"); + result = -ENOMEM; + if (map) + goto fail_alloc; + return result; + } + cmd_data = (struct IpaHwPeripheralInitCmdData_t *)cmd.base; + cmd_data->protocol = IPA_HW_PROTOCOL_11ad; + cmd_data->Init_params.W11AdInit_params.periph_baddr_msb = + IPA_WIGIG_MSB(periph_baddr_pa); + cmd_data->Init_params.W11AdInit_params.periph_baddr_lsb = + IPA_WIGIG_LSB(periph_baddr_pa); + command = IPA_CPU_2_HW_CMD_PERIPHERAL_INIT; + } else { + struct IpaHwPeripheralDeinitCmdData_t *cmd_data; + + cmd.size = sizeof(*cmd_data); + cmd.base = dma_alloc_coherent(ipa3_ctx->uc_pdev, cmd.size, + &cmd.phys_base, GFP_KERNEL); + if (cmd.base == NULL) { + IPAERR("fail to get DMA memory.\n"); + result = -ENOMEM; + if (map) + goto fail_alloc; + return result; + } + cmd_data = (struct IpaHwPeripheralDeinitCmdData_t *)cmd.base; + cmd_data->protocol = IPA_HW_PROTOCOL_11ad; + command = IPA_CPU_2_HW_CMD_PERIPHERAL_DEINIT; + } + + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + + result = ipa3_uc_send_cmd((u32)(cmd.phys_base), + command, + IPA_HW_2_CPU_OFFLOAD_CMD_STATUS_SUCCESS, + false, 10 * HZ); + if (result) { + IPAERR("fail to %s uc MSI config\n", init ? "init" : "deinit"); + goto fail_command; + } + + dma_free_coherent(ipa3_ctx->uc_pdev, cmd.size, + cmd.base, cmd.phys_base); + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + + IPADBG("exit\n"); + + return 0; +fail_command: + dma_free_coherent(ipa3_ctx->uc_pdev, + cmd.size, + cmd.base, cmd.phys_base); + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); +fail_alloc: + ipa3_smmu_map_peer_reg( + rounddown(dma_ep_misc_pa, PAGE_SIZE), !map, IPA_SMMU_CB_UC); +fail_dma_ep_misc: + ipa3_smmu_map_peer_reg( + rounddown(int_gen_rx_pa, PAGE_SIZE), !map, IPA_SMMU_CB_UC); +fail_gen_rx: + ipa3_smmu_map_peer_reg( + rounddown(int_gen_tx_pa, PAGE_SIZE), !map, IPA_SMMU_CB_UC); +fail_gen_tx: + ipa3_smmu_map_peer_reg( + rounddown(pseudo_cause_pa, PAGE_SIZE), !map, IPA_SMMU_CB_UC); +fail: + return result; +} +EXPORT_SYMBOL(ipa3_wigig_uc_msi_init); + +int ipa3_enable_wigig_pipe_i(enum ipa_client_type client) +{ + int ipa_ep_idx, res; + struct ipa3_ep_context *ep; + struct ipa_ep_cfg_ctrl ep_cfg_ctrl; + int retry_cnt = 0; + uint64_t val; + u32 holb_max_cnt = ipa3_ctx->uc_ctx.holb_monitor.max_cnt_11ad; + + IPADBG("\n"); + + ipa_ep_idx = ipa_get_ep_mapping(client); + if (ipa_ep_idx == IPA_EP_NOT_ALLOCATED || + ipa_ep_idx >= ipa3_get_max_num_pipes()) { + IPAERR("fail to get ep (%d) %d.\n", + client, ipa_ep_idx); + return -EFAULT; + } + + ep = &ipa3_ctx->ep[ipa_ep_idx]; + + if (!ep->valid) { + IPAERR("Invalid EP\n"); + return -EFAULT; + } + + if (ep->gsi_offload_state != IPA_WIGIG_CONNECTED) { + IPAERR("WIGIG channel bad state 0x%X\n", + ep->gsi_offload_state); + return -EFAULT; + } + + IPA_ACTIVE_CLIENTS_INC_EP(client); + + res = ipa3_enable_data_path(ipa_ep_idx); + if (res) + goto fail_enable_datapath; + + memset(&ep_cfg_ctrl, 0, sizeof(struct ipa_ep_cfg_ctrl)); + ipa_cfg_ep_ctrl(ipa_ep_idx, &ep_cfg_ctrl); + + /* ring the event db (outside the ring boundary)*/ + val = ep->gsi_mem_info.evt_ring_base_addr + + ep->gsi_mem_info.evt_ring_len; + res = gsi_ring_evt_ring_db(ep->gsi_evt_ring_hdl, val); + if (res) { + IPAERR( + "fail to ring evt ring db %d. hdl=%lu wp=0x%llx\n" + , res, ep->gsi_evt_ring_hdl, + (unsigned long long)val); + res = -EFAULT; + goto fail_ring_evt; + } + + IPADBG("start channel\n"); + res = gsi_start_channel(ep->gsi_chan_hdl); + if (res != GSI_STATUS_SUCCESS) { + IPAERR("gsi_start_channel failed %d\n", res); + WARN_ON(1); + res = -EFAULT; + goto fail_gsi_start; + } + if (IPA_CLIENT_IS_HOLB_CONS(ep->client)) { + res = ipa3_uc_client_add_holb_monitor(ep->gsi_chan_hdl, + HOLB_MONITOR_MASK, holb_max_cnt, + IPA_EE_AP); + if (res) + IPAERR("Add HOLB monitor failed for gsi ch %d\n", + ep->gsi_chan_hdl); + } + + /* for TX we have to ring the channel db (last desc in the ring) */ + if (client != IPA_CLIENT_WIGIG_PROD) { + uint64_t val; + + val = ep->gsi_mem_info.chan_ring_base_addr + + ep->gsi_mem_info.chan_ring_len - + IPA_WIGIG_DESC_RING_EL_SIZE; + + IPADBG("ring ch doorbell (0x%llX) TX %ld\n", val, + ep->gsi_chan_hdl); + res = gsi_ring_ch_ring_db(ep->gsi_chan_hdl, val); + if (res) { + IPAERR( + "fail to ring channel db %d. hdl=%lu wp=0x%llx\n" + , res, ep->gsi_chan_hdl, + (unsigned long long)val); + res = -EFAULT; + goto fail_ring_ch; + } + } + + ep->gsi_offload_state |= IPA_WIGIG_ENABLED; + + IPADBG("exit\n"); + + return 0; + +fail_ring_ch: + res = ipa_stop_gsi_channel(ipa_ep_idx); + if (res != 0 && res != -GSI_STATUS_AGAIN && + res != -GSI_STATUS_TIMED_OUT) { + IPAERR("failed to stop channel res = %d\n", res); + } else if (res == -GSI_STATUS_AGAIN) { + IPADBG("GSI stop channel failed retry cnt = %d\n", + retry_cnt); + retry_cnt++; + if (retry_cnt < GSI_STOP_MAX_RETRY_CNT) + goto fail_ring_ch; + } else { + IPADBG("GSI channel %ld STOP\n", ep->gsi_chan_hdl); + } + res = -EFAULT; +fail_gsi_start: +fail_ring_evt: + ipa3_disable_data_path(ipa_ep_idx); +fail_enable_datapath: + IPA_ACTIVE_CLIENTS_DEC_EP(client); + return res; +} +EXPORT_SYMBOL(ipa3_enable_wigig_pipe_i); + +int ipa3_disable_wigig_pipe_i(enum ipa_client_type client) +{ + int ipa_ep_idx, res; + struct ipa3_ep_context *ep; + struct ipahal_ep_cfg_ctrl_scnd ep_ctrl_scnd = { 0 }; + struct ipa_ep_cfg_ctrl ep_cfg_ctrl; + bool disable_force_clear = false; + u32 source_pipe_bitmask = 0; + u32 source_pipe_reg_idx = 0; + int retry_cnt = 0; + + IPADBG("\n"); + + ipa_ep_idx = ipa_get_ep_mapping(client); + if (ipa_ep_idx == IPA_EP_NOT_ALLOCATED) { + IPAERR("fail to get ep (%d) %d.\n", + client, ipa_ep_idx); + return -EFAULT; + } + if (ipa_ep_idx >= ipa3_get_max_num_pipes()) { + IPAERR("ep %d out of range.\n", ipa_ep_idx); + return -EFAULT; + } + + ep = &ipa3_ctx->ep[ipa_ep_idx]; + + if (!ep->valid) { + IPAERR("Invalid EP\n"); + return -EFAULT; + } + + if (ep->gsi_offload_state != + (IPA_WIGIG_CONNECTED | IPA_WIGIG_ENABLED)) { + IPAERR("WIGIG channel bad state 0x%X\n", + ep->gsi_offload_state); + return -EFAULT; + } + + IPADBG("pipe %d\n", ipa_ep_idx); + if (IPA_CLIENT_IS_PROD(ep->client)) { + source_pipe_bitmask = ipahal_get_ep_bit(ipa_ep_idx); + source_pipe_reg_idx = ipahal_get_ep_reg_idx(ipa_ep_idx); + res = ipa3_enable_force_clear(ipa_ep_idx, + false, source_pipe_bitmask, + source_pipe_reg_idx); + if (res) { + /* + * assuming here modem SSR, AP can remove + * the delay in this case + */ + IPAERR("failed to force clear %d\n", res); + IPAERR("remove delay from SCND reg\n"); + if (ipa3_ctx->ipa_endp_delay_wa_v2) { + ipa3_remove_secondary_flow_ctrl( + ep->gsi_chan_hdl); + } else { + ep_ctrl_scnd.endp_delay = false; + ipahal_write_reg_n_fields( + IPA_ENDP_INIT_CTRL_SCND_n, + ipa_ep_idx, + &ep_ctrl_scnd); + } + } else { + disable_force_clear = true; + } + } +retry_gsi_stop: + res = ipa_stop_gsi_channel(ipa_ep_idx); + if (res != 0 && res != -GSI_STATUS_AGAIN && + res != -GSI_STATUS_TIMED_OUT) { + IPAERR("failed to stop channel res = %d\n", res); + goto fail_stop_channel; + } else if (res == -GSI_STATUS_AGAIN) { + IPADBG("GSI stop channel failed retry cnt = %d\n", + retry_cnt); + retry_cnt++; + if (retry_cnt >= GSI_STOP_MAX_RETRY_CNT) + goto fail_stop_channel; + goto retry_gsi_stop; + } else { + IPADBG("GSI channel %ld STOP\n", ep->gsi_chan_hdl); + } + + res = ipa3_reset_gsi_channel(ipa_ep_idx); + if (res != GSI_STATUS_SUCCESS) { + IPAERR("Failed to reset chan: %d.\n", res); + goto fail_stop_channel; + } + + if (disable_force_clear) + ipa3_disable_force_clear(ipa_ep_idx); + + res = ipa3_disable_data_path(ipa_ep_idx); + if (res) { + WARN_ON(1); + return res; + } + + /* Set the delay after disabling IPA Producer pipe */ + if (IPA_CLIENT_IS_PROD(ep->client)) { + memset(&ep_cfg_ctrl, 0, sizeof(struct ipa_ep_cfg_ctrl)); + ep_cfg_ctrl.ipa_ep_delay = true; + ipa_cfg_ep_ctrl(ipa_ep_idx, &ep_cfg_ctrl); + } + + ep->gsi_offload_state &= ~IPA_WIGIG_ENABLED; + + IPA_ACTIVE_CLIENTS_DEC_EP(ipa3_get_client_mapping(ipa_ep_idx)); + IPADBG("exit\n"); + return 0; + +fail_stop_channel: + ipa_assert(); + return res; +} +EXPORT_SYMBOL(ipa3_disable_wigig_pipe_i); + +static void ipa_wigig_free_msg(void *msg, uint32_t len, uint32_t type) +{ + IPADBG("free msg type:%d, len:%d, buff %pK", type, len, msg); + kfree(msg); + IPADBG("exit\n"); +} + +int ipa_wigig_send_wlan_msg(enum ipa_wlan_event msg_type, + const char *netdev_name, u8 *mac) +{ + struct ipa_msg_meta msg_meta; + struct ipa_wlan_msg *wlan_msg; + int ret; + + IPADBG("%d\n", msg_type); + + wlan_msg = kzalloc(sizeof(*wlan_msg), GFP_KERNEL); + if (wlan_msg == NULL) + return -ENOMEM; + strlcpy(wlan_msg->name, netdev_name, IPA_RESOURCE_NAME_MAX); + memcpy(wlan_msg->mac_addr, mac, IPA_MAC_ADDR_SIZE); + msg_meta.msg_len = sizeof(struct ipa_wlan_msg); + msg_meta.msg_type = msg_type; + + IPADBG("send msg type:%d, len:%d, buff %pK", msg_meta.msg_type, + msg_meta.msg_len, wlan_msg); + ret = ipa_send_msg(&msg_meta, wlan_msg, ipa_wigig_free_msg); + + IPADBG("exit\n"); + + return ret; +} +EXPORT_SYMBOL(ipa_wigig_send_wlan_msg); + +int ipa_wigig_send_msg(int msg_type, + const char *netdev_name, u8 *mac, + enum ipa_client_type client, bool to_wigig) +{ + struct ipa_msg_meta msg_meta; + struct ipa_wigig_msg *wigig_msg; + int ret; + + IPADBG("\n"); + + wigig_msg = kzalloc(sizeof(struct ipa_wigig_msg), GFP_KERNEL); + if (wigig_msg == NULL) + return -ENOMEM; + strlcpy(wigig_msg->name, netdev_name, IPA_RESOURCE_NAME_MAX); + memcpy(wigig_msg->client_mac_addr, mac, IPA_MAC_ADDR_SIZE); + if (msg_type == WIGIG_CLIENT_CONNECT) + wigig_msg->u.ipa_client = client; + else + wigig_msg->u.to_wigig = to_wigig; + + msg_meta.msg_type = msg_type; + msg_meta.msg_len = sizeof(struct ipa_wigig_msg); + + IPADBG("send msg type:%d, len:%d, buff %pK", msg_meta.msg_type, + msg_meta.msg_len, wigig_msg); + ret = ipa_send_msg(&msg_meta, wigig_msg, ipa_wigig_free_msg); + + IPADBG("exit\n"); + + return ret; +} +EXPORT_SYMBOL(ipa_wigig_send_msg); + +#ifndef CONFIG_DEBUG_FS +int ipa3_wigig_init_debugfs_i(struct dentry *parent) { return 0; } +#else +int ipa3_wigig_init_debugfs_i(struct dentry *parent) +{ + const mode_t read_write_mode = 0664; + struct dentry *dent; + + dent = debugfs_create_dir("ipa_wigig", parent); + if (IS_ERR_OR_NULL(dent)) { + IPAERR("fail to create folder in debug_fs\n"); + return -EFAULT; + } + + wigig_dent = dent; + + debugfs_create_u8("modc", read_write_mode, dent, + &int_modc); + + debugfs_create_u16("modt", read_write_mode, dent, + &int_modt); + + debugfs_create_u8("rx_mod_th", read_write_mode, dent, + &rx_hwtail_mod_threshold); + + debugfs_create_u8("tx_mod_th", read_write_mode, dent, + &tx_hwtail_mod_threshold); + + return 0; +} +#endif diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal.c new file mode 100644 index 0000000000..52e8e908b9 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal.c @@ -0,0 +1,2879 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include "ipahal.h" +#include "ipahal_i.h" +#include "ipahal_reg_i.h" +#include "ipahal_fltrt_i.h" +#include "ipahal_hw_stats_i.h" +#include "ipahal_nat_i.h" + +#define CHECK_SET_PARAM(member, p_cmd_data, p_params, p_params_mask) \ + if ((p_params_mask)->member) {\ + (p_cmd_data)->member = (p_params)->member;\ + } + +#define IPA_GET_UCP_RTP_CMD(type) \ + do { \ + if (type == IPA_HDR_PROC_RTP_METADATA_STREAM0) \ + type = IPA_HDR_UCP_RTP_METADATA_STREAM0; \ + if (type == IPA_HDR_PROC_RTP_METADATA_STREAM1) \ + type = IPA_HDR_UCP_RTP_METADATA_STREAM1; \ + if (type == IPA_HDR_PROC_RTP_METADATA_STREAM2) \ + type = IPA_HDR_UCP_RTP_METADATA_STREAM2; \ + if (type == IPA_HDR_PROC_RTP_METADATA_STREAM3) \ + type = IPA_HDR_UCP_RTP_METADATA_STREAM3; \ + } while (0) + +struct ipahal_context *ipahal_ctx; + +static const char *ipahal_imm_cmd_name_to_str[IPA_IMM_CMD_MAX] = { + __stringify(IPA_IMM_CMD_IP_V4_FILTER_INIT), + __stringify(IPA_IMM_CMD_IP_V6_FILTER_INIT), + __stringify(IPA_IMM_CMD_IP_V4_NAT_INIT), + __stringify(IPA_IMM_CMD_IP_V4_ROUTING_INIT), + __stringify(IPA_IMM_CMD_IP_V6_ROUTING_INIT), + __stringify(IPA_IMM_CMD_HDR_INIT_LOCAL), + __stringify(IPA_IMM_CMD_HDR_INIT_SYSTEM), + __stringify(IPA_IMM_CMD_REGISTER_WRITE), + __stringify(IPA_IMM_CMD_REGISTER_READ), + __stringify(IPA_IMM_CMD_NAT_DMA), + __stringify(IPA_IMM_CMD_IP_PACKET_INIT), + __stringify(IPA_IMM_CMD_DMA_SHARED_MEM), + __stringify(IPA_IMM_CMD_IP_PACKET_TAG_STATUS), + __stringify(IPA_IMM_CMD_DMA_TASK_32B_ADDR), + __stringify(IPA_IMM_CMD_TABLE_DMA), + __stringify(IPA_IMM_CMD_IP_V6_CT_INIT), + __stringify(IPA_IMM_CMD_IP_PACKET_INIT_EX), +}; + +static const char *ipahal_pkt_status_exception_to_str + [IPAHAL_PKT_STATUS_EXCEPTION_MAX] = { + __stringify(IPAHAL_PKT_STATUS_EXCEPTION_NONE), + __stringify(IPAHAL_PKT_STATUS_EXCEPTION_DEAGGR), + __stringify(IPAHAL_PKT_STATUS_EXCEPTION_IPTYPE), + __stringify(IPAHAL_PKT_STATUS_EXCEPTION_PACKET_LENGTH), + __stringify(IPAHAL_PKT_STATUS_EXCEPTION_PACKET_THRESHOLD), + __stringify(IPAHAL_PKT_STATUS_EXCEPTION_TTL), + __stringify(IPAHAL_PKT_STATUS_EXCEPTION_FRAG_RULE_MISS), + __stringify(IPAHAL_PKT_STATUS_EXCEPTION_SW_FILT), + __stringify(IPAHAL_PKT_STATUS_EXCEPTION_NAT), + __stringify(IPAHAL_PKT_STATUS_EXCEPTION_IPV6CT), + __stringify(IPAHAL_PKT_STATUS_EXCEPTION_UCP), + __stringify(IPAHAL_PKT_STATUS_EXCEPTION_INVALID_PIPE), + __stringify(IPAHAL_PKT_STATUS_EXCEPTION_HDRI), + __stringify(IPAHAL_PKT_STATUS_EXCEPTION_CSUM), +}; + +/* + * Forward declarations. + */ +static u16 ipahal_imm_cmd_get_opcode(enum ipahal_imm_cmd_name cmd); +static int ipahal_qmap_init(enum ipa_hw_type ipa_hw_type); + +static struct ipahal_imm_cmd_pyld *ipa_imm_cmd_construct_dma_task_32b_addr( + enum ipahal_imm_cmd_name cmd, const void *params, bool is_atomic_ctx) +{ + struct ipahal_imm_cmd_pyld *pyld; + struct ipa_imm_cmd_hw_dma_task_32b_addr *data; + struct ipahal_imm_cmd_dma_task_32b_addr *dma_params = + (struct ipahal_imm_cmd_dma_task_32b_addr *)params; + + pyld = IPAHAL_MEM_ALLOC(sizeof(*pyld) + sizeof(*data), is_atomic_ctx); + if (unlikely(!pyld)) + return pyld; + + /* Currently supports only one packet */ + pyld->opcode = ipahal_imm_cmd_get_opcode(cmd) + (1 << 8); + pyld->len = sizeof(*data); + data = (struct ipa_imm_cmd_hw_dma_task_32b_addr *)pyld->data; + + if (unlikely(dma_params->size1 & ~0xFFFF)) { + WARN(1, "Size1 is bigger than 16bit width 0x%x\n", + dma_params->size1); + } + if (unlikely(dma_params->packet_size & ~0xFFFF)) { + WARN(1, "Pkt size is bigger than 16bit width 0x%x\n", + dma_params->packet_size); + } + data->cmplt = dma_params->cmplt ? 1 : 0; + data->eof = dma_params->eof ? 1 : 0; + data->flsh = dma_params->flsh ? 1 : 0; + data->lock = dma_params->lock ? 1 : 0; + data->unlock = dma_params->unlock ? 1 : 0; + data->size1 = dma_params->size1; + data->addr1 = dma_params->addr1; + data->packet_size = dma_params->packet_size; + + return pyld; +} + +static struct ipahal_imm_cmd_pyld *ipa_imm_cmd_construct_ip_packet_tag_status( + enum ipahal_imm_cmd_name cmd, const void *params, bool is_atomic_ctx) +{ + struct ipahal_imm_cmd_pyld *pyld; + struct ipa_imm_cmd_hw_ip_packet_tag_status *data; + struct ipahal_imm_cmd_ip_packet_tag_status *tag_params = + (struct ipahal_imm_cmd_ip_packet_tag_status *)params; + + pyld = IPAHAL_MEM_ALLOC(sizeof(*pyld) + sizeof(*data), is_atomic_ctx); + if (unlikely(!pyld)) { + IPAHAL_ERR("kzalloc err\n"); + return pyld; + } + pyld->opcode = ipahal_imm_cmd_get_opcode(cmd); + pyld->len = sizeof(*data); + data = (struct ipa_imm_cmd_hw_ip_packet_tag_status *)pyld->data; + + if (unlikely(tag_params->tag & ~0xFFFFFFFFFFFF)) { + IPAHAL_ERR("tag is bigger than 48bit width 0x%llx\n", + tag_params->tag); + WARN_ON(1); + } + data->tag = tag_params->tag; + + return pyld; +} + +static struct ipahal_imm_cmd_pyld *ipa_imm_cmd_construct_dma_shared_mem( + enum ipahal_imm_cmd_name cmd, const void *params, bool is_atomic_ctx) +{ + struct ipahal_imm_cmd_pyld *pyld; + struct ipa_imm_cmd_hw_dma_shared_mem *data; + struct ipahal_imm_cmd_dma_shared_mem *mem_params = + (struct ipahal_imm_cmd_dma_shared_mem *)params; + + pyld = IPAHAL_MEM_ALLOC(sizeof(*pyld) + sizeof(*data), is_atomic_ctx); + if (unlikely(!pyld)) + return pyld; + + pyld->opcode = ipahal_imm_cmd_get_opcode(cmd); + pyld->len = sizeof(*data); + data = (struct ipa_imm_cmd_hw_dma_shared_mem *)pyld->data; + + if (unlikely(mem_params->size & ~0xFFFF)) { + WARN(1, "Size is bigger than 16bit width 0x%x\n", + mem_params->size); + } + if (unlikely(mem_params->local_addr & ~0xFFFF)) { + WARN(1, "Local addr is bigger than 16bit width 0x%x\n", + mem_params->local_addr); + } + data->direction = mem_params->is_read ? 1 : 0; + data->size = mem_params->size; + data->local_addr = mem_params->local_addr; + data->system_addr = mem_params->system_addr; + data->skip_pipeline_clear = mem_params->skip_pipeline_clear ? 1 : 0; + switch (mem_params->pipeline_clear_options) { + case IPAHAL_HPS_CLEAR: + data->pipeline_clear_options = 0; + break; + case IPAHAL_SRC_GRP_CLEAR: + data->pipeline_clear_options = 1; + break; + case IPAHAL_FULL_PIPELINE_CLEAR: + data->pipeline_clear_options = 2; + break; + default: + IPAHAL_ERR("unsupported pipline clear option %d\n", + mem_params->pipeline_clear_options); + WARN_ON(1); + } + + return pyld; +} + +static struct ipahal_imm_cmd_pyld *ipa_imm_cmd_construct_dma_shared_mem_v_4_0( + enum ipahal_imm_cmd_name cmd, const void *params, bool is_atomic_ctx) +{ + struct ipahal_imm_cmd_pyld *pyld; + struct ipa_imm_cmd_hw_dma_shared_mem_v_4_0 *data; + struct ipahal_imm_cmd_dma_shared_mem *mem_params = + (struct ipahal_imm_cmd_dma_shared_mem *)params; + + if (unlikely(mem_params->size & ~0xFFFF)) { + IPAHAL_ERR("Size is bigger than 16bit width 0x%x\n", + mem_params->size); + WARN_ON(1); + return NULL; + } + if (unlikely(mem_params->local_addr & ~0xFFFF)) { + IPAHAL_ERR("Local addr is bigger than 16bit width 0x%x\n", + mem_params->local_addr); + WARN_ON(1); + return NULL; + } + + pyld = IPAHAL_MEM_ALLOC(sizeof(*pyld) + sizeof(*data), is_atomic_ctx); + if (unlikely(!pyld)) { + WARN_ON(1); + return pyld; + } + + pyld->opcode = ipahal_imm_cmd_get_opcode(cmd); + pyld->len = sizeof(*data); + data = (struct ipa_imm_cmd_hw_dma_shared_mem_v_4_0 *)pyld->data; + + data->direction = mem_params->is_read ? 1 : 0; + data->clear_after_read = mem_params->clear_after_read; + data->size = mem_params->size; + data->local_addr = mem_params->local_addr; + data->system_addr = mem_params->system_addr; + pyld->opcode |= (mem_params->skip_pipeline_clear ? 1 : 0) << 8; + switch (mem_params->pipeline_clear_options) { + case IPAHAL_HPS_CLEAR: + break; + case IPAHAL_SRC_GRP_CLEAR: + pyld->opcode |= (1 << 9); + break; + case IPAHAL_FULL_PIPELINE_CLEAR: + pyld->opcode |= (2 << 9); + break; + default: + IPAHAL_ERR("unsupported pipline clear option %d\n", + mem_params->pipeline_clear_options); + WARN_ON(1); + } + + return pyld; +} + +static struct ipahal_imm_cmd_pyld *ipa_imm_cmd_construct_register_write( + enum ipahal_imm_cmd_name cmd, const void *params, bool is_atomic_ctx) +{ + struct ipahal_imm_cmd_pyld *pyld; + struct ipa_imm_cmd_hw_register_write *data; + struct ipahal_imm_cmd_register_write *regwrt_params = + (struct ipahal_imm_cmd_register_write *)params; + + pyld = IPAHAL_MEM_ALLOC(sizeof(*pyld) + sizeof(*data), is_atomic_ctx); + if (unlikely(!pyld)) { + IPAHAL_ERR("kzalloc err\n"); + return pyld; + } + pyld->opcode = ipahal_imm_cmd_get_opcode(cmd); + pyld->len = sizeof(*data); + data = (struct ipa_imm_cmd_hw_register_write *)pyld->data; + + if (unlikely(regwrt_params->offset & ~0xFFFF)) { + IPAHAL_ERR("Offset is bigger than 16bit width 0x%x\n", + regwrt_params->offset); + WARN_ON(1); + } + data->offset = regwrt_params->offset; + data->value = regwrt_params->value; + data->value_mask = regwrt_params->value_mask; + + data->skip_pipeline_clear = regwrt_params->skip_pipeline_clear ? 1 : 0; + switch (regwrt_params->pipeline_clear_options) { + case IPAHAL_HPS_CLEAR: + data->pipeline_clear_options = 0; + break; + case IPAHAL_SRC_GRP_CLEAR: + data->pipeline_clear_options = 1; + break; + case IPAHAL_FULL_PIPELINE_CLEAR: + data->pipeline_clear_options = 2; + break; + default: + IPAHAL_ERR("unsupported pipline clear option %d\n", + regwrt_params->pipeline_clear_options); + WARN_ON(1); + } + + return pyld; +} + +static struct ipahal_imm_cmd_pyld *ipa_imm_cmd_construct_register_write_v_4_0( + enum ipahal_imm_cmd_name cmd, const void *params, bool is_atomic_ctx) +{ + struct ipahal_imm_cmd_pyld *pyld; + struct ipa_imm_cmd_hw_register_write_v_4_0 *data; + struct ipahal_imm_cmd_register_write *regwrt_params = + (struct ipahal_imm_cmd_register_write *)params; + + if (unlikely(regwrt_params->offset & ~0xFFFF)) { + IPAHAL_ERR("Offset is bigger than 16bit width 0x%x\n", + regwrt_params->offset); + WARN_ON(1); + return NULL; + } + + pyld = IPAHAL_MEM_ALLOC(sizeof(*pyld) + sizeof(*data), is_atomic_ctx); + if (unlikely(!pyld)) { + WARN_ON(1); + return pyld; + } + pyld->opcode = ipahal_imm_cmd_get_opcode(cmd); + pyld->len = sizeof(*data); + data = (struct ipa_imm_cmd_hw_register_write_v_4_0 *)pyld->data; + + data->offset = regwrt_params->offset; + data->offset_high = regwrt_params->offset >> 16; + data->value = regwrt_params->value; + data->value_mask = regwrt_params->value_mask; + + pyld->opcode |= (regwrt_params->skip_pipeline_clear ? 1 : 0) << 8; + switch (regwrt_params->pipeline_clear_options) { + case IPAHAL_HPS_CLEAR: + break; + case IPAHAL_SRC_GRP_CLEAR: + pyld->opcode |= (1 << 9); + break; + case IPAHAL_FULL_PIPELINE_CLEAR: + pyld->opcode |= (2 << 9); + break; + default: + IPAHAL_ERR("unsupported pipline clear option %d\n", + regwrt_params->pipeline_clear_options); + WARN_ON(1); + } + + return pyld; +} + +static struct ipahal_imm_cmd_pyld *ipa_imm_cmd_construct_register_read( + enum ipahal_imm_cmd_name cmd, const void *params, bool is_atomic_ctx) +{ + struct ipahal_imm_cmd_pyld *pyld; + struct ipa_imm_cmd_hw_register_read *data; + struct ipahal_imm_cmd_register_read *regrd_params = + (struct ipahal_imm_cmd_register_read *)params; + + if (unlikely(regrd_params->offset & ~0xFFFF)) { + IPAHAL_ERR("Offset is bigger than 16bit width 0x%x\n", + regrd_params->offset); + WARN_ON(1); + return NULL; + } + + pyld = IPAHAL_MEM_ALLOC(sizeof(*pyld) + sizeof(*data), is_atomic_ctx); + if (unlikely(!pyld)) { + WARN_ON(1); + return pyld; + } + pyld->opcode = ipahal_imm_cmd_get_opcode(cmd); + pyld->len = sizeof(*data); + data = (struct ipa_imm_cmd_hw_register_read *)pyld->data; + + data->offset = regrd_params->offset; + data->offset_high = regrd_params->offset >> 16; + data->sys_addr = regrd_params->sys_addr; + + pyld->opcode |= (regrd_params->skip_pipeline_clear ? 1 : 0) << 8; + switch (regrd_params->pipeline_clear_options) { + case IPAHAL_HPS_CLEAR: + break; + case IPAHAL_SRC_GRP_CLEAR: + pyld->opcode |= (1 << 9); + break; + case IPAHAL_FULL_PIPELINE_CLEAR: + pyld->opcode |= (2 << 9); + break; + default: + IPAHAL_ERR("unsupported pipline clear option %d\n", + regrd_params->pipeline_clear_options); + WARN_ON(1); + } + + return pyld; +} + +static struct ipahal_imm_cmd_pyld *ipa_imm_cmd_construct_ip_packet_init( + enum ipahal_imm_cmd_name cmd, const void *params, bool is_atomic_ctx) +{ + struct ipahal_imm_cmd_pyld *pyld; + struct ipa_imm_cmd_hw_ip_packet_init *data; + struct ipahal_imm_cmd_ip_packet_init *pktinit_params = + (struct ipahal_imm_cmd_ip_packet_init *)params; + + pyld = IPAHAL_MEM_ALLOC(sizeof(*pyld) + sizeof(*data), is_atomic_ctx); + if (unlikely(!pyld)) { + IPAHAL_ERR("kzalloc err\n"); + return pyld; + } + pyld->opcode = ipahal_imm_cmd_get_opcode(cmd); + pyld->len = sizeof(*data); + data = (struct ipa_imm_cmd_hw_ip_packet_init *)pyld->data; + + if (unlikely(pktinit_params->destination_pipe_index & ~0x1F)) { + IPAHAL_ERR("Dst pipe idx is bigger than 5bit width 0x%x\n", + pktinit_params->destination_pipe_index); + WARN_ON(1); + } + data->destination_pipe_index = pktinit_params->destination_pipe_index; + + return pyld; +} + +static struct ipahal_imm_cmd_pyld *ipa_imm_cmd_construct_ip_packet_init_v_5_0( + enum ipahal_imm_cmd_name cmd, const void *params, bool is_atomic_ctx) +{ + struct ipahal_imm_cmd_pyld *pyld; + struct ipa_imm_cmd_hw_ip_packet_init_v_5_0 *data; + struct ipahal_imm_cmd_ip_packet_init *pktinit_params = + (struct ipahal_imm_cmd_ip_packet_init *)params; + + pyld = IPAHAL_MEM_ALLOC(sizeof(*pyld) + sizeof(*data), is_atomic_ctx); + if (unlikely(!pyld)) { + IPAHAL_ERR("kzalloc err\n"); + return pyld; + } + pyld->opcode = ipahal_imm_cmd_get_opcode(cmd); + pyld->len = sizeof(*data); + data = (struct ipa_imm_cmd_hw_ip_packet_init_v_5_0 *)pyld->data; + + if (unlikely(pktinit_params->destination_pipe_index & ~0xFF)) { + IPAHAL_ERR("Dst pipe idx is bigger than 8bit width 0x%x\n", + pktinit_params->destination_pipe_index); + WARN_ON(1); + } + data->destination_pipe_index = pktinit_params->destination_pipe_index; + + return pyld; +} + +static struct ipahal_imm_cmd_pyld *ipa_imm_cmd_construct_ip_packet_init_ex( + enum ipahal_imm_cmd_name cmd, const void *params, bool is_atomic_ctx) +{ + struct ipahal_imm_cmd_pyld *pyld; + struct ipa_imm_cmd_hw_ip_packet_init_ex *data; + struct ipahal_imm_cmd_ip_packet_init_ex *packet_init_ex_params = + (struct ipahal_imm_cmd_ip_packet_init_ex *)params; + + pyld = IPAHAL_MEM_ALLOC(sizeof(*pyld) + sizeof(*data), is_atomic_ctx); + if (unlikely(!pyld)) { + IPAHAL_ERR("kzalloc err\n"); + return pyld; + } + pyld->opcode = ipahal_imm_cmd_get_opcode(cmd); + pyld->len = sizeof(*data); + data = (struct ipa_imm_cmd_hw_ip_packet_init_ex *)pyld->data; + + data->frag_disable = packet_init_ex_params->frag_disable; + data->filter_disable = packet_init_ex_params->filter_disable; + data->nat_disable = packet_init_ex_params->nat_disable; + data->route_disable = packet_init_ex_params->route_disable; + data->hdr_removal_insertion_disable = + packet_init_ex_params->hdr_removal_insertion_disable; + data->cs_disable = packet_init_ex_params->cs_disable; + data->quota_tethering_stats_disable = + packet_init_ex_params->quota_tethering_stats_disable; + data->flt_rt_tbl_idx = packet_init_ex_params->flt_rt_tbl_idx; + data->flt_stats_cnt_idx = packet_init_ex_params->flt_stats_cnt_idx; + data->flt_priority = packet_init_ex_params->flt_priority; + data->flt_close_aggr_irq_mod = + packet_init_ex_params->flt_close_aggr_irq_mod; + /* rule id value of 0x3FF is required */ + /* (if not set correctly, filtering stats may be updated) */ + data->flt_rule_id = 0x3FF; + data->flt_action = packet_init_ex_params->flt_action; + data->flt_pdn_idx = packet_init_ex_params->flt_pdn_idx; + data->flt_set_metadata = packet_init_ex_params->flt_set_metadata; + data->flt_retain_hdr = packet_init_ex_params->flt_retain_hdr; + data->rt_pipe_dest_idx = packet_init_ex_params->rt_pipe_dest_idx; + data->rt_stats_cnt_idx = packet_init_ex_params->rt_stats_cnt_idx; + data->rt_priority = packet_init_ex_params->rt_priority; + data->rt_close_aggr_irq_mod = + packet_init_ex_params->rt_close_aggr_irq_mod; + /* rule id value of 0x3FF is required */ + /* (if not set correctly, filtering stats may be updated) */ + data->rt_rule_id = 0x3FF; + data->rt_hdr_offset = packet_init_ex_params->rt_hdr_offset; + data->rt_proc_ctx = packet_init_ex_params->rt_proc_ctx; + data->rt_retain_hdr = packet_init_ex_params->rt_retain_hdr; + data->rt_system = packet_init_ex_params->rt_system; + + return pyld; +} + +static struct ipahal_imm_cmd_pyld *ipa_imm_cmd_construct_ip_packet_init_ex_v5_5( + enum ipahal_imm_cmd_name cmd, const void *params, bool is_atomic_ctx) +{ + struct ipahal_imm_cmd_pyld *pyld; + struct ipa_imm_cmd_hw_ip_packet_init_ex_v5_5 *data; + struct ipahal_imm_cmd_ip_packet_init_ex *packet_init_ex_params = + (struct ipahal_imm_cmd_ip_packet_init_ex *)params; + + pyld = IPAHAL_MEM_ALLOC(sizeof(*pyld) + sizeof(*data), is_atomic_ctx); + if (unlikely(!pyld)) { + IPAHAL_ERR("kzalloc err\n"); + return pyld; + } + pyld->opcode = ipahal_imm_cmd_get_opcode(cmd); + pyld->len = sizeof(*data); + data = (struct ipa_imm_cmd_hw_ip_packet_init_ex_v5_5 *)pyld->data; + + data->frag_disable = packet_init_ex_params->frag_disable; + data->filter_disable = packet_init_ex_params->filter_disable; + data->nat_disable = packet_init_ex_params->nat_disable; + data->route_disable = packet_init_ex_params->route_disable; + data->hdr_removal_insertion_disable = + packet_init_ex_params->hdr_removal_insertion_disable; + data->cs_disable = packet_init_ex_params->cs_disable; + data->quota_tethering_stats_disable = + packet_init_ex_params->quota_tethering_stats_disable; + data->dpl_disable = packet_init_ex_params->dpl_disable; + data->flt_rt_tbl_idx = packet_init_ex_params->flt_rt_tbl_idx; + data->flt_stats_cnt_idx = packet_init_ex_params->flt_stats_cnt_idx; + data->flt_priority = packet_init_ex_params->flt_priority; + data->flt_ext_hdr = packet_init_ex_params->flt_ext_hdr; + data->flt_close_aggr_irq_mod = + packet_init_ex_params->flt_close_aggr_irq_mod; + /* rule id value of 0x3FF is required */ + /* (if not set correctly, filtering stats may be updated) */ + data->flt_rule_id = 0x3FF; + data->flt_action = packet_init_ex_params->flt_action; + data->flt_pdn_idx = packet_init_ex_params->flt_pdn_idx; + data->flt_set_metadata = packet_init_ex_params->flt_set_metadata; + data->flt_retain_hdr = packet_init_ex_params->flt_retain_hdr; + data->flt_ttl = packet_init_ex_params->flt_ttl; + data->flt_qos_class = packet_init_ex_params->flt_qos_class; + data->rt_pipe_dest_idx = packet_init_ex_params->rt_pipe_dest_idx; + data->rt_stats_cnt_idx = packet_init_ex_params->rt_stats_cnt_idx; + data->rt_priority = packet_init_ex_params->rt_priority; + data->rt_ext_hdr = packet_init_ex_params->rt_ext_hdr; + data->rt_close_aggr_irq_mod = + packet_init_ex_params->rt_close_aggr_irq_mod; + /* rule id value of 0x3FF is required */ + /* (if not set correctly, filtering stats may be updated) */ + data->rt_rule_id = 0x3FF; + data->rt_hdr_offset = packet_init_ex_params->rt_hdr_offset; + data->rt_proc_ctx = packet_init_ex_params->rt_proc_ctx; + data->rt_retain_hdr = packet_init_ex_params->rt_retain_hdr; + data->rt_system = packet_init_ex_params->rt_system; + data->rt_ttl = packet_init_ex_params->rt_ttl; + data->rt_qos_class = packet_init_ex_params->rt_qos_class; + data->rt_skip_ingress = packet_init_ex_params->rt_skip_ingress; + return pyld; +} + +int ipa_imm_cmd_modify_ip_packet_init_ex( + enum ipahal_imm_cmd_name cmd, + const void *cmd_data, + const void *params, + const void *params_mask) +{ + struct ipa_imm_cmd_hw_ip_packet_init_ex *data = + (struct ipa_imm_cmd_hw_ip_packet_init_ex *)cmd_data; + struct ipahal_imm_cmd_ip_packet_init_ex *mask = + (struct ipahal_imm_cmd_ip_packet_init_ex *)params_mask; + struct ipahal_imm_cmd_ip_packet_init_ex *prms = + (struct ipahal_imm_cmd_ip_packet_init_ex *)params; + + CHECK_SET_PARAM(frag_disable, data, prms, mask); + CHECK_SET_PARAM(filter_disable, data, prms, mask); + CHECK_SET_PARAM(nat_disable, data, prms, mask); + CHECK_SET_PARAM(route_disable, data, prms, mask); + CHECK_SET_PARAM(hdr_removal_insertion_disable, data, prms, mask); + CHECK_SET_PARAM(cs_disable, data, prms, mask); + CHECK_SET_PARAM(quota_tethering_stats_disable, data, prms, mask); + CHECK_SET_PARAM(flt_rt_tbl_idx, data, prms, mask); + CHECK_SET_PARAM(flt_stats_cnt_idx, data, prms, mask); + CHECK_SET_PARAM(flt_priority, data, prms, mask); + CHECK_SET_PARAM(flt_close_aggr_irq_mod, data, prms, mask); + CHECK_SET_PARAM(flt_action, data, prms, mask); + CHECK_SET_PARAM(flt_pdn_idx, data, prms, mask); + CHECK_SET_PARAM(flt_set_metadata, data, prms, mask); + CHECK_SET_PARAM(flt_retain_hdr, data, prms, mask); + CHECK_SET_PARAM(rt_pipe_dest_idx, data, prms, mask); + CHECK_SET_PARAM(rt_stats_cnt_idx, data, prms, mask); + CHECK_SET_PARAM(rt_priority, data, prms, mask); + CHECK_SET_PARAM(rt_close_aggr_irq_mod, data, prms, mask); + CHECK_SET_PARAM(rt_hdr_offset, data, prms, mask); + CHECK_SET_PARAM(rt_proc_ctx, data, prms, mask); + CHECK_SET_PARAM(rt_retain_hdr, data, prms, mask); + CHECK_SET_PARAM(rt_system, data, prms, mask); + + return 0; +} + +static int ipa_imm_cmd_modify_ip_packet_init_ex_v5_5( + enum ipahal_imm_cmd_name cmd, + const void *cmd_data, + const void *params, + const void *params_mask) +{ + struct ipa_imm_cmd_hw_ip_packet_init_ex_v5_5 *data = + (struct ipa_imm_cmd_hw_ip_packet_init_ex_v5_5 *)cmd_data; + struct ipahal_imm_cmd_ip_packet_init_ex *mask = + (struct ipahal_imm_cmd_ip_packet_init_ex *)params_mask; + struct ipahal_imm_cmd_ip_packet_init_ex *prms = + (struct ipahal_imm_cmd_ip_packet_init_ex *)params; + + CHECK_SET_PARAM(frag_disable, data, prms, mask); + CHECK_SET_PARAM(filter_disable, data, prms, mask); + CHECK_SET_PARAM(nat_disable, data, prms, mask); + CHECK_SET_PARAM(route_disable, data, prms, mask); + CHECK_SET_PARAM(hdr_removal_insertion_disable, data, prms, mask); + CHECK_SET_PARAM(cs_disable, data, prms, mask); + CHECK_SET_PARAM(quota_tethering_stats_disable, data, prms, mask); + CHECK_SET_PARAM(dpl_disable, data, prms, mask); + CHECK_SET_PARAM(flt_rt_tbl_idx, data, prms, mask); + CHECK_SET_PARAM(flt_stats_cnt_idx, data, prms, mask); + CHECK_SET_PARAM(flt_priority, data, prms, mask); + CHECK_SET_PARAM(flt_close_aggr_irq_mod, data, prms, mask); + CHECK_SET_PARAM(flt_action, data, prms, mask); + CHECK_SET_PARAM(flt_pdn_idx, data, prms, mask); + CHECK_SET_PARAM(flt_set_metadata, data, prms, mask); + CHECK_SET_PARAM(flt_retain_hdr, data, prms, mask); + CHECK_SET_PARAM(rt_pipe_dest_idx, data, prms, mask); + CHECK_SET_PARAM(rt_stats_cnt_idx, data, prms, mask); + CHECK_SET_PARAM(rt_priority, data, prms, mask); + CHECK_SET_PARAM(rt_close_aggr_irq_mod, data, prms, mask); + CHECK_SET_PARAM(rt_hdr_offset, data, prms, mask); + CHECK_SET_PARAM(rt_proc_ctx, data, prms, mask); + CHECK_SET_PARAM(rt_retain_hdr, data, prms, mask); + CHECK_SET_PARAM(rt_system, data, prms, mask); + CHECK_SET_PARAM(flt_ext_hdr, data, prms, mask); + CHECK_SET_PARAM(flt_ttl, data, prms, mask); + CHECK_SET_PARAM(flt_qos_class, data, prms, mask); + CHECK_SET_PARAM(rt_ext_hdr, data, prms, mask); + CHECK_SET_PARAM(rt_ttl, data, prms, mask); + CHECK_SET_PARAM(rt_qos_class, data, prms, mask); + CHECK_SET_PARAM(rt_skip_ingress, data, prms, mask); + return 0; +} + +inline void ipa_imm_cmd_modify_ip_packet_init_ex_dest_pipe_v5_5( + const void *cmd_data, + u64 pipe_dest_idx) +{ + ((struct ipa_imm_cmd_hw_ip_packet_init_ex_v5_5 *)cmd_data)->rt_pipe_dest_idx + = pipe_dest_idx; +} + +inline void ipa_imm_cmd_modify_ip_packet_init_ex_dest_pipe( + const void *cmd_data, + u64 pipe_dest_idx) +{ + if (ipahal_ctx->hw_type >= IPA_HW_v5_5) + return ipa_imm_cmd_modify_ip_packet_init_ex_dest_pipe_v5_5(cmd_data, + pipe_dest_idx); + else + ((struct ipa_imm_cmd_hw_ip_packet_init_ex *)cmd_data)->rt_pipe_dest_idx + = pipe_dest_idx; +} + +static struct ipahal_imm_cmd_pyld *ipa_imm_cmd_construct_nat_dma( + enum ipahal_imm_cmd_name cmd, const void *params, bool is_atomic_ctx) +{ + struct ipahal_imm_cmd_pyld *pyld; + struct ipa_imm_cmd_hw_nat_dma *data; + struct ipahal_imm_cmd_table_dma *nat_params = + (struct ipahal_imm_cmd_table_dma *)params; + + pyld = IPAHAL_MEM_ALLOC(sizeof(*pyld) + sizeof(*data), is_atomic_ctx); + if (unlikely(!pyld)) { + IPAHAL_ERR("kzalloc err\n"); + return pyld; + } + pyld->opcode = ipahal_imm_cmd_get_opcode(cmd); + pyld->len = sizeof(*data); + data = (struct ipa_imm_cmd_hw_nat_dma *)pyld->data; + + data->table_index = nat_params->table_index; + data->base_addr = nat_params->base_addr; + data->offset = nat_params->offset; + data->data = nat_params->data; + + return pyld; +} + +static struct ipahal_imm_cmd_pyld *ipa_imm_cmd_construct_table_dma_ipav4( + enum ipahal_imm_cmd_name cmd, const void *params, bool is_atomic_ctx) +{ + struct ipahal_imm_cmd_pyld *pyld; + struct ipa_imm_cmd_hw_table_dma_ipav4 *data; + struct ipahal_imm_cmd_table_dma *nat_params = + (struct ipahal_imm_cmd_table_dma *)params; + + pyld = IPAHAL_MEM_ALLOC(sizeof(*pyld) + sizeof(*data), is_atomic_ctx); + if (unlikely(!pyld)) { + IPAHAL_ERR("kzalloc err\n"); + return pyld; + } + pyld->opcode = ipahal_imm_cmd_get_opcode(cmd); + pyld->len = sizeof(*data); + data = (struct ipa_imm_cmd_hw_table_dma_ipav4 *)pyld->data; + + data->table_index = nat_params->table_index; + data->base_addr = nat_params->base_addr; + data->offset = nat_params->offset; + data->data = nat_params->data; + + return pyld; +} + +static struct ipahal_imm_cmd_pyld *ipa_imm_cmd_construct_hdr_init_system( + enum ipahal_imm_cmd_name cmd, const void *params, bool is_atomic_ctx) +{ + struct ipahal_imm_cmd_pyld *pyld; + struct ipa_imm_cmd_hw_hdr_init_system *data; + struct ipahal_imm_cmd_hdr_init_system *syshdr_params = + (struct ipahal_imm_cmd_hdr_init_system *)params; + + pyld = IPAHAL_MEM_ALLOC(sizeof(*pyld) + sizeof(*data), is_atomic_ctx); + if (unlikely(!pyld)) { + IPAHAL_ERR("kzalloc err\n"); + return pyld; + } + pyld->opcode = ipahal_imm_cmd_get_opcode(cmd); + pyld->len = sizeof(*data); + data = (struct ipa_imm_cmd_hw_hdr_init_system *)pyld->data; + + data->hdr_table_addr = syshdr_params->hdr_table_addr; + + return pyld; +} + +static struct ipahal_imm_cmd_pyld *ipa_imm_cmd_construct_hdr_init_local( + enum ipahal_imm_cmd_name cmd, const void *params, bool is_atomic_ctx) +{ + struct ipahal_imm_cmd_pyld *pyld; + struct ipa_imm_cmd_hw_hdr_init_local *data; + struct ipahal_imm_cmd_hdr_init_local *lclhdr_params = + (struct ipahal_imm_cmd_hdr_init_local *)params; + + pyld = IPAHAL_MEM_ALLOC(sizeof(*pyld) + sizeof(*data), is_atomic_ctx); + if (unlikely(!pyld)) { + IPAHAL_ERR("kzalloc err\n"); + return pyld; + } + pyld->opcode = ipahal_imm_cmd_get_opcode(cmd); + pyld->len = sizeof(*data); + data = (struct ipa_imm_cmd_hw_hdr_init_local *)pyld->data; + + if (unlikely(lclhdr_params->size_hdr_table & ~0xFFF)) { + IPAHAL_ERR("Hdr tble size is bigger than 12bit width 0x%x\n", + lclhdr_params->size_hdr_table); + WARN_ON(1); + } + data->hdr_table_addr = lclhdr_params->hdr_table_addr; + data->size_hdr_table = lclhdr_params->size_hdr_table; + data->hdr_addr = lclhdr_params->hdr_addr; + + return pyld; +} + +static struct ipahal_imm_cmd_pyld *ipa_imm_cmd_construct_ip_v6_routing_init( + enum ipahal_imm_cmd_name cmd, const void *params, bool is_atomic_ctx) +{ + struct ipahal_imm_cmd_pyld *pyld; + struct ipa_imm_cmd_hw_ip_v6_routing_init *data; + struct ipahal_imm_cmd_ip_v6_routing_init *rt6_params = + (struct ipahal_imm_cmd_ip_v6_routing_init *)params; + + pyld = IPAHAL_MEM_ALLOC(sizeof(*pyld) + sizeof(*data), is_atomic_ctx); + if (unlikely(!pyld)) { + IPAHAL_ERR("kzalloc err\n"); + return pyld; + } + pyld->opcode = ipahal_imm_cmd_get_opcode(cmd); + pyld->len = sizeof(*data); + data = (struct ipa_imm_cmd_hw_ip_v6_routing_init *)pyld->data; + + data->hash_rules_addr = rt6_params->hash_rules_addr; + data->hash_rules_size = rt6_params->hash_rules_size; + data->hash_local_addr = rt6_params->hash_local_addr; + data->nhash_rules_addr = rt6_params->nhash_rules_addr; + data->nhash_rules_size = rt6_params->nhash_rules_size; + data->nhash_local_addr = rt6_params->nhash_local_addr; + + return pyld; +} + +static struct ipahal_imm_cmd_pyld *ipa_imm_cmd_construct_ip_v4_routing_init( + enum ipahal_imm_cmd_name cmd, const void *params, bool is_atomic_ctx) +{ + struct ipahal_imm_cmd_pyld *pyld; + struct ipa_imm_cmd_hw_ip_v4_routing_init *data; + struct ipahal_imm_cmd_ip_v4_routing_init *rt4_params = + (struct ipahal_imm_cmd_ip_v4_routing_init *)params; + + pyld = IPAHAL_MEM_ALLOC(sizeof(*pyld) + sizeof(*data), is_atomic_ctx); + if (unlikely(!pyld)) { + IPAHAL_ERR("kzalloc err\n"); + return pyld; + } + pyld->opcode = ipahal_imm_cmd_get_opcode(cmd); + pyld->len = sizeof(*data); + data = (struct ipa_imm_cmd_hw_ip_v4_routing_init *)pyld->data; + + data->hash_rules_addr = rt4_params->hash_rules_addr; + data->hash_rules_size = rt4_params->hash_rules_size; + data->hash_local_addr = rt4_params->hash_local_addr; + data->nhash_rules_addr = rt4_params->nhash_rules_addr; + data->nhash_rules_size = rt4_params->nhash_rules_size; + data->nhash_local_addr = rt4_params->nhash_local_addr; + + return pyld; +} + +static struct ipahal_imm_cmd_pyld *ipa_imm_cmd_construct_ip_v4_nat_init( + enum ipahal_imm_cmd_name cmd, const void *params, bool is_atomic_ctx) +{ + struct ipahal_imm_cmd_pyld *pyld; + struct ipa_imm_cmd_hw_ip_v4_nat_init *data; + struct ipahal_imm_cmd_ip_v4_nat_init *nat4_params = + (struct ipahal_imm_cmd_ip_v4_nat_init *)params; + + pyld = IPAHAL_MEM_ALLOC(sizeof(*pyld) + sizeof(*data), is_atomic_ctx); + if (unlikely(!pyld)) { + IPAHAL_ERR("kzalloc err\n"); + return pyld; + } + pyld->opcode = ipahal_imm_cmd_get_opcode(cmd); + pyld->len = sizeof(*data); + data = (struct ipa_imm_cmd_hw_ip_v4_nat_init *)pyld->data; + + data->ipv4_rules_addr = nat4_params->table_init.base_table_addr; + data->ipv4_expansion_rules_addr = + nat4_params->table_init.expansion_table_addr; + data->index_table_addr = nat4_params->index_table_addr; + data->index_table_expansion_addr = + nat4_params->index_table_expansion_addr; + data->table_index = nat4_params->table_init.table_index; + data->ipv4_rules_addr_type = + nat4_params->table_init.base_table_addr_shared ? 1 : 0; + data->ipv4_expansion_rules_addr_type = + nat4_params->table_init.expansion_table_addr_shared ? 1 : 0; + data->index_table_addr_type = + nat4_params->index_table_addr_shared ? 1 : 0; + data->index_table_expansion_addr_type = + nat4_params->index_table_expansion_addr_shared ? 1 : 0; + data->size_base_tables = nat4_params->table_init.size_base_table; + data->size_expansion_tables = + nat4_params->table_init.size_expansion_table; + data->public_addr_info = nat4_params->public_addr_info; + + return pyld; +} + +static struct ipahal_imm_cmd_pyld *ipa_imm_cmd_construct_ip_v6_ct_init( + enum ipahal_imm_cmd_name cmd, const void *params, bool is_atomic_ctx) +{ + struct ipahal_imm_cmd_pyld *pyld; + struct ipa_imm_cmd_hw_ip_v6_ct_init *data; + struct ipahal_imm_cmd_ip_v6_ct_init *ipv6ct_params = + (struct ipahal_imm_cmd_ip_v6_ct_init *)params; + + pyld = IPAHAL_MEM_ALLOC(sizeof(*pyld) + sizeof(*data), is_atomic_ctx); + if (unlikely(!pyld)) + return pyld; + pyld->opcode = ipahal_imm_cmd_get_opcode(cmd); + pyld->len = sizeof(*data); + data = (struct ipa_imm_cmd_hw_ip_v6_ct_init *)pyld->data; + + data->table_addr = ipv6ct_params->table_init.base_table_addr; + data->expansion_table_addr = + ipv6ct_params->table_init.expansion_table_addr; + data->table_index = ipv6ct_params->table_init.table_index; + data->table_addr_type = + ipv6ct_params->table_init.base_table_addr_shared ? 1 : 0; + data->expansion_table_addr_type = + ipv6ct_params->table_init.expansion_table_addr_shared ? 1 : 0; + data->size_base_table = ipv6ct_params->table_init.size_base_table; + data->size_expansion_table = + ipv6ct_params->table_init.size_expansion_table; + + return pyld; +} + +static struct ipahal_imm_cmd_pyld *ipa_imm_cmd_construct_ip_v6_filter_init( + enum ipahal_imm_cmd_name cmd, const void *params, bool is_atomic_ctx) +{ + struct ipahal_imm_cmd_pyld *pyld; + struct ipa_imm_cmd_hw_ip_v6_filter_init *data; + struct ipahal_imm_cmd_ip_v6_filter_init *flt6_params = + (struct ipahal_imm_cmd_ip_v6_filter_init *)params; + + pyld = IPAHAL_MEM_ALLOC(sizeof(*pyld) + sizeof(*data), is_atomic_ctx); + if (unlikely(!pyld)) { + IPAHAL_ERR("kzalloc err\n"); + return pyld; + } + pyld->opcode = ipahal_imm_cmd_get_opcode(cmd); + pyld->len = sizeof(*data); + data = (struct ipa_imm_cmd_hw_ip_v6_filter_init *)pyld->data; + + data->hash_rules_addr = flt6_params->hash_rules_addr; + data->hash_rules_size = flt6_params->hash_rules_size; + data->hash_local_addr = flt6_params->hash_local_addr; + data->nhash_rules_addr = flt6_params->nhash_rules_addr; + data->nhash_rules_size = flt6_params->nhash_rules_size; + data->nhash_local_addr = flt6_params->nhash_local_addr; + + return pyld; +} + +static struct ipahal_imm_cmd_pyld *ipa_imm_cmd_construct_ip_v4_filter_init( + enum ipahal_imm_cmd_name cmd, const void *params, bool is_atomic_ctx) +{ + struct ipahal_imm_cmd_pyld *pyld; + struct ipa_imm_cmd_hw_ip_v4_filter_init *data; + struct ipahal_imm_cmd_ip_v4_filter_init *flt4_params = + (struct ipahal_imm_cmd_ip_v4_filter_init *)params; + + pyld = IPAHAL_MEM_ALLOC(sizeof(*pyld) + sizeof(*data), is_atomic_ctx); + if (unlikely(!pyld)) { + IPAHAL_ERR("kzalloc err\n"); + return pyld; + } + pyld->opcode = ipahal_imm_cmd_get_opcode(cmd); + pyld->len = sizeof(*data); + data = (struct ipa_imm_cmd_hw_ip_v4_filter_init *)pyld->data; + + data->hash_rules_addr = flt4_params->hash_rules_addr; + data->hash_rules_size = flt4_params->hash_rules_size; + data->hash_local_addr = flt4_params->hash_local_addr; + data->nhash_rules_addr = flt4_params->nhash_rules_addr; + data->nhash_rules_size = flt4_params->nhash_rules_size; + data->nhash_local_addr = flt4_params->nhash_local_addr; + + return pyld; +} + +static struct ipahal_imm_cmd_pyld *ipa_imm_cmd_construct_dummy( + enum ipahal_imm_cmd_name cmd, const void *params, bool is_atomic_ctx) +{ + IPAHAL_ERR("no construct function for IMM_CMD=%s, IPA ver %d\n", + ipahal_imm_cmd_name_str(cmd), ipahal_ctx->hw_type); + WARN_ON(1); + return NULL; +} + +static int ipa_imm_cmd_modify_dummy( + enum ipahal_imm_cmd_name cmd, + const void *cmd_data, + const void *params, + const void *params_mask) +{ + IPAHAL_ERR("no modify function for IMM_CMD=%s, IPA ver %d\n", + ipahal_imm_cmd_name_str(cmd), ipahal_ctx->hw_type); + WARN_ON(1); + return -EINVAL; +} + +/* + * struct ipahal_imm_cmd_obj - immediate command H/W information for + * specific IPA version + * @construct - CB to construct imm command payload from abstracted structure + * @modify - CB to modify imm command payload from abstracted structure + * @opcode - Immediate command OpCode + */ +struct ipahal_imm_cmd_obj { + struct ipahal_imm_cmd_pyld *(*construct)(enum ipahal_imm_cmd_name cmd, + const void *params, bool is_atomic_ctx); + int (*modify)(enum ipahal_imm_cmd_name cmd, + const void *cmd_data, + const void *params, + const void *params_mask); + u16 opcode; +}; + +/* + * This table contains the info regard each immediate command for IPAv3 + * and later. + * Information like: opcode and construct functions. + * All the information on the IMM on IPAv3 are statically defined below. + * If information is missing regard some IMM on some IPA version, + * the init function will fill it with the information from the previous + * IPA version. + * Information is considered missing if all of the fields are 0 + * If opcode is -1, this means that the IMM is removed on the + * specific version + */ +static struct ipahal_imm_cmd_obj + ipahal_imm_cmd_objs[IPA_HW_MAX][IPA_IMM_CMD_MAX] = { + /* IPAv3 */ + [IPA_HW_v3_0][IPA_IMM_CMD_IP_V4_FILTER_INIT] = { + ipa_imm_cmd_construct_ip_v4_filter_init, + ipa_imm_cmd_modify_dummy, + 3}, + [IPA_HW_v3_0][IPA_IMM_CMD_IP_V6_FILTER_INIT] = { + ipa_imm_cmd_construct_ip_v6_filter_init, + ipa_imm_cmd_modify_dummy, + 4}, + [IPA_HW_v3_0][IPA_IMM_CMD_IP_V4_NAT_INIT] = { + ipa_imm_cmd_construct_ip_v4_nat_init, + ipa_imm_cmd_modify_dummy, + 5}, + [IPA_HW_v3_0][IPA_IMM_CMD_IP_V4_ROUTING_INIT] = { + ipa_imm_cmd_construct_ip_v4_routing_init, + ipa_imm_cmd_modify_dummy, + 7}, + [IPA_HW_v3_0][IPA_IMM_CMD_IP_V6_ROUTING_INIT] = { + ipa_imm_cmd_construct_ip_v6_routing_init, + ipa_imm_cmd_modify_dummy, + 8}, + [IPA_HW_v3_0][IPA_IMM_CMD_HDR_INIT_LOCAL] = { + ipa_imm_cmd_construct_hdr_init_local, + ipa_imm_cmd_modify_dummy, + 9}, + [IPA_HW_v3_0][IPA_IMM_CMD_HDR_INIT_SYSTEM] = { + ipa_imm_cmd_construct_hdr_init_system, + ipa_imm_cmd_modify_dummy, + 10}, + [IPA_HW_v3_0][IPA_IMM_CMD_REGISTER_WRITE] = { + ipa_imm_cmd_construct_register_write, + ipa_imm_cmd_modify_dummy, + 12}, + [IPA_HW_v3_0][IPA_IMM_CMD_NAT_DMA] = { + ipa_imm_cmd_construct_nat_dma, + ipa_imm_cmd_modify_dummy, + 14}, + [IPA_HW_v3_0][IPA_IMM_CMD_IP_PACKET_INIT] = { + ipa_imm_cmd_construct_ip_packet_init, + ipa_imm_cmd_modify_dummy, + 16}, + [IPA_HW_v3_0][IPA_IMM_CMD_DMA_TASK_32B_ADDR] = { + ipa_imm_cmd_construct_dma_task_32b_addr, + ipa_imm_cmd_modify_dummy, + 17}, + [IPA_HW_v3_0][IPA_IMM_CMD_DMA_SHARED_MEM] = { + ipa_imm_cmd_construct_dma_shared_mem, + ipa_imm_cmd_modify_dummy, + 19}, + [IPA_HW_v3_0][IPA_IMM_CMD_IP_PACKET_TAG_STATUS] = { + ipa_imm_cmd_construct_ip_packet_tag_status, + ipa_imm_cmd_modify_dummy, + 20}, + + /* IPAv4 */ + [IPA_HW_v4_0][IPA_IMM_CMD_REGISTER_WRITE] = { + ipa_imm_cmd_construct_register_write_v_4_0, + ipa_imm_cmd_modify_dummy, + 12}, + /* NAT_DMA was renamed to TABLE_DMA for IPAv4 */ + [IPA_HW_v4_0][IPA_IMM_CMD_NAT_DMA] = { + ipa_imm_cmd_construct_dummy, + ipa_imm_cmd_modify_dummy, + -1}, + [IPA_HW_v4_0][IPA_IMM_CMD_TABLE_DMA] = { + ipa_imm_cmd_construct_table_dma_ipav4, + ipa_imm_cmd_modify_dummy, + 14}, + [IPA_HW_v4_0][IPA_IMM_CMD_DMA_SHARED_MEM] = { + ipa_imm_cmd_construct_dma_shared_mem_v_4_0, + ipa_imm_cmd_modify_dummy, + 19}, + [IPA_HW_v4_0][IPA_IMM_CMD_IP_V6_CT_INIT] = { + ipa_imm_cmd_construct_ip_v6_ct_init, + ipa_imm_cmd_modify_dummy, + 23}, + + /* IPAv5 */ + [IPA_HW_v5_0][IPA_IMM_CMD_IP_PACKET_INIT] = { + ipa_imm_cmd_construct_ip_packet_init_v_5_0, + ipa_imm_cmd_modify_dummy, + 16}, + [IPA_HW_v5_0][IPA_IMM_CMD_IP_PACKET_INIT_EX] = { + ipa_imm_cmd_construct_ip_packet_init_ex, + ipa_imm_cmd_modify_ip_packet_init_ex, + 18}, + + [IPA_HW_v5_1][IPA_IMM_CMD_REGISTER_READ] = { + ipa_imm_cmd_construct_register_read, + ipa_imm_cmd_modify_dummy, + 13}, + /* IPAv5_5 */ + [IPA_HW_v5_5][IPA_IMM_CMD_IP_PACKET_INIT_EX] = { + ipa_imm_cmd_construct_ip_packet_init_ex_v5_5, + ipa_imm_cmd_modify_ip_packet_init_ex_v5_5, + 18}, +}; + +/* + * ipahal_imm_cmd_init() - Build the Immediate command information table + * See ipahal_imm_cmd_objs[][] comments + */ +static int ipahal_imm_cmd_init(enum ipa_hw_type ipa_hw_type) +{ + int i; + int j; + struct ipahal_imm_cmd_obj zero_obj; + + IPAHAL_DBG_LOW("Entry - HW_TYPE=%d\n", ipa_hw_type); + + if ((ipa_hw_type < 0) || (ipa_hw_type >= IPA_HW_MAX)) { + IPAHAL_ERR("invalid IPA HW type (%d)\n", ipa_hw_type); + return -EINVAL; + } + + memset(&zero_obj, 0, sizeof(zero_obj)); + for (i = IPA_HW_v3_0 ; i < ipa_hw_type ; i++) { + for (j = 0; j < IPA_IMM_CMD_MAX ; j++) { + if (!memcmp(&ipahal_imm_cmd_objs[i+1][j], &zero_obj, + sizeof(struct ipahal_imm_cmd_obj))) { + memcpy(&ipahal_imm_cmd_objs[i+1][j], + &ipahal_imm_cmd_objs[i][j], + sizeof(struct ipahal_imm_cmd_obj)); + } else { + /* + * explicitly overridden immediate command. + * Check validity + */ + if (!ipahal_imm_cmd_objs[i+1][j].opcode) { + IPAHAL_ERR( + "imm_cmd=%s with zero opcode ipa_ver=%d\n", + ipahal_imm_cmd_name_str(j), i+1); + WARN_ON(1); + } + if (!ipahal_imm_cmd_objs[i+1][j].construct) { + IPAHAL_ERR( + "imm_cmd=%s with NULL construct func ipa_ver=%d\n", + ipahal_imm_cmd_name_str(j), i+1); + WARN_ON(1); + } + } + } + } + + return 0; +} + +/* + * ipahal_imm_cmd_name_str() - returns string that represent the imm cmd + * @cmd_name: [in] Immediate command name + */ +const char *ipahal_imm_cmd_name_str(enum ipahal_imm_cmd_name cmd_name) +{ + if (cmd_name < 0 || cmd_name >= IPA_IMM_CMD_MAX) { + IPAHAL_ERR("requested name of invalid imm_cmd=%d\n", cmd_name); + return "Invalid IMM_CMD"; + } + + return ipahal_imm_cmd_name_to_str[cmd_name]; +} + +/* + * ipahal_imm_cmd_get_opcode() - Get the fixed opcode of the immediate command + */ +static u16 ipahal_imm_cmd_get_opcode(enum ipahal_imm_cmd_name cmd) +{ + u32 opcode; + + if (cmd >= IPA_IMM_CMD_MAX) { + IPAHAL_ERR("Invalid immediate command imm_cmd=%u\n", cmd); + ipa_assert(); + return -EFAULT; + } + + IPAHAL_DBG_LOW("Get opcode of IMM_CMD=%s\n", + ipahal_imm_cmd_name_str(cmd)); + opcode = ipahal_imm_cmd_objs[ipahal_ctx->hw_type][cmd].opcode; + if (opcode == -1) { + IPAHAL_ERR("Try to get opcode of obsolete IMM_CMD=%s\n", + ipahal_imm_cmd_name_str(cmd)); + ipa_assert(); + return -EFAULT; + } + + return opcode; +} + +/* + * ipahal_construct_imm_cmd() - Construct immdiate command + * This function builds imm cmd bulk that can be be sent to IPA + * The command will be allocated dynamically. + * After done using it, call ipahal_destroy_imm_cmd() to release it + */ +struct ipahal_imm_cmd_pyld *ipahal_construct_imm_cmd( + enum ipahal_imm_cmd_name cmd, const void *params, bool is_atomic_ctx) +{ + if (!params) { + IPAHAL_ERR("Input error: params=%pK\n", params); + ipa_assert(); + return NULL; + } + + if (cmd >= IPA_IMM_CMD_MAX) { + IPAHAL_ERR("Invalid immediate command %u\n", cmd); + return NULL; + } + + IPAHAL_DBG_LOW("construct IMM_CMD:%s\n", ipahal_imm_cmd_name_str(cmd)); + return ipahal_imm_cmd_objs[ipahal_ctx->hw_type][cmd].construct( + cmd, params, is_atomic_ctx); +} + +/* + * ipahal_modify_imm_cmd() - Modify immdiate command in an existing buffer + * This function modifies an existing imm cmd buffer + * @cmd_name: [in] Immediate command name + * @cmd_data: [in] Constructed immediate command buffer data + * @params: [in] Structure with specific IMM params + * @params_mask: [in] Same structure, but the fields filled with 0, + * if they should not be changed, or any non-zero for fields to be updated + */ +int ipahal_modify_imm_cmd( + enum ipahal_imm_cmd_name cmd, + const void *cmd_data, + const void *params, + const void *params_mask) +{ + if (!cmd_data || !params || !params_mask) { + WARN_ONCE(true, + "Input error: cmd_data=%pK params=%pK params_mask=%pK\n", + cmd_data, params, params_mask); + return -EINVAL; + } + + if (cmd >= IPA_IMM_CMD_MAX) { + IPAHAL_ERR("Invalid immediate command %u\n", cmd); + return -EINVAL; + } + + IPAHAL_DBG_LOW("Modify IMM_CMD:%s\n", ipahal_imm_cmd_name_str(cmd)); + return ipahal_imm_cmd_objs[ipahal_ctx->hw_type][cmd].modify( + cmd, + cmd_data, + params, + params_mask); +} + +/* + * ipahal_construct_nop_imm_cmd() - Construct immediate comamnd for NO-Op + * Core driver may want functionality to inject NOP commands to IPA + * to ensure e.g., PIPLINE clear before someother operation. + * The functionality given by this function can be reached by + * ipahal_construct_imm_cmd(). This function is helper to the core driver + * to reach this NOP functionlity easily. + * @skip_pipline_clear: if to skip pipeline clear waiting (don't wait) + * @pipline_clr_opt: options for pipeline clear waiting + * @is_atomic_ctx: is called in atomic context or can sleep? + */ +struct ipahal_imm_cmd_pyld *ipahal_construct_nop_imm_cmd( + bool skip_pipline_clear, + enum ipahal_pipeline_clear_option pipline_clr_opt, + bool is_atomic_ctx) +{ + struct ipahal_imm_cmd_register_write cmd; + struct ipahal_imm_cmd_pyld *cmd_pyld; + + memset(&cmd, 0, sizeof(cmd)); + cmd.skip_pipeline_clear = skip_pipline_clear; + cmd.pipeline_clear_options = pipline_clr_opt; + cmd.value_mask = 0x0; + + cmd_pyld = ipahal_construct_imm_cmd(IPA_IMM_CMD_REGISTER_WRITE, + &cmd, is_atomic_ctx); + + if (!cmd_pyld) + IPAHAL_ERR("failed to construct register_write imm cmd\n"); + + return cmd_pyld; +} + + +/* IPA Packet Status Logic */ + +#define IPA_PKT_STATUS_SET_MSK(__hw_bit_msk, __shft) \ + (status->status_mask |= \ + ((hw_status_mask) & (__hw_bit_msk) ? 1 : 0) << (__shft)) + +static enum ipahal_pkt_status_exception pkt_status_parse_exception( + bool is_ipv6, u64 exception) +{ + enum ipahal_pkt_status_exception exception_type = 0; + + switch (exception) { + case 0: + exception_type = IPAHAL_PKT_STATUS_EXCEPTION_NONE; + break; + case 1: + exception_type = IPAHAL_PKT_STATUS_EXCEPTION_DEAGGR; + break; + case 4: + exception_type = IPAHAL_PKT_STATUS_EXCEPTION_IPTYPE; + break; + case 8: + exception_type = IPAHAL_PKT_STATUS_EXCEPTION_PACKET_LENGTH; + break; + case 10: + exception_type = IPAHAL_PKT_STATUS_EXCEPTION_TTL; + break; + case 16: + exception_type = IPAHAL_PKT_STATUS_EXCEPTION_FRAG_RULE_MISS; + break; + case 32: + exception_type = IPAHAL_PKT_STATUS_EXCEPTION_SW_FILT; + break; + case 64: + if (is_ipv6) + exception_type = IPAHAL_PKT_STATUS_EXCEPTION_IPV6CT; + else + exception_type = IPAHAL_PKT_STATUS_EXCEPTION_NAT; + break; + case 128: + exception_type = IPAHAL_PKT_STATUS_EXCEPTION_UCP; + break; + case 129: + exception_type = IPAHAL_PKT_STATUS_EXCEPTION_INVALID_PIPE; + break; + case 131: + exception_type = IPAHAL_PKT_STATUS_EXCEPTION_RQOS; + break; + case 136: + exception_type = IPAHAL_PKT_STATUS_EXCEPTION_HDRI; + break; + case 229: + exception_type = IPAHAL_PKT_STATUS_EXCEPTION_CSUM; + break; + default: + IPAHAL_ERR("unsupported Status Exception type 0x%x\n", + exception); + WARN_ON(1); + } + + return exception_type; +} + +static void __ipa_parse_gen_pkt(struct ipahal_pkt_status *status, + const void *unparsed_status) +{ + bool is_ipv6; + union ipa_pkt_status_hw *hw_status = + (union ipa_pkt_status_hw *)unparsed_status; + + is_ipv6 = (hw_status->ipa_pkt.status_mask & 0x80) ? false : true; + status->pkt_len = hw_status->ipa_pkt.pkt_len; + status->endp_src_idx = hw_status->ipa_pkt.endp_src_idx; + status->endp_dest_idx = hw_status->ipa_pkt.endp_dest_idx; + status->metadata = hw_status->ipa_pkt.metadata; + status->flt_local = hw_status->ipa_pkt.flt_local; + status->flt_hash = hw_status->ipa_pkt.flt_hash; + status->flt_global = hw_status->ipa_pkt.flt_hash; + status->flt_ret_hdr = hw_status->ipa_pkt.flt_ret_hdr; + status->flt_miss = (hw_status->ipa_pkt.rt_rule_id == + IPAHAL_PKT_STATUS_FLTRT_RULE_MISS_ID); + status->flt_rule_id = hw_status->ipa_pkt.flt_rule_id; + status->rt_local = hw_status->ipa_pkt.rt_local; + status->rt_hash = hw_status->ipa_pkt.rt_hash; + status->ucp = hw_status->ipa_pkt.ucp; + status->rt_tbl_idx = hw_status->ipa_pkt.rt_tbl_idx; + status->rt_miss = (hw_status->ipa_pkt.rt_rule_id == + IPAHAL_PKT_STATUS_FLTRT_RULE_MISS_ID); + status->rt_rule_id = hw_status->ipa_pkt.rt_rule_id; + status->nat_hit = hw_status->ipa_pkt.nat_hit; + status->nat_entry_idx = hw_status->ipa_pkt.nat_entry_idx; + status->tag_info = hw_status->ipa_pkt.tag_info; + status->seq_num = hw_status->ipa_pkt.seq_num; + status->time_of_day_ctr = hw_status->ipa_pkt.time_of_day_ctr; + status->hdr_local = hw_status->ipa_pkt.hdr_local; + status->hdr_offset = hw_status->ipa_pkt.hdr_offset; + status->frag_hit = hw_status->ipa_pkt.frag_hit; + status->frag_rule = hw_status->ipa_pkt.frag_rule; + status->nat_type = hw_status->ipa_pkt.nat_type; + + status->exception = pkt_status_parse_exception(is_ipv6, + hw_status->ipa_pkt.exception); +} + +static void __ipa_parse_frag_pkt(struct ipahal_pkt_status *status, + const void *unparsed_status) +{ + union ipa_pkt_status_hw *hw_status = + (union ipa_pkt_status_hw *)unparsed_status; + + status->frag_rule_idx = hw_status->frag_pkt.frag_rule_idx; + status->tbl_idx = hw_status->frag_pkt.tbl_idx; + status->src_ip_addr = hw_status->frag_pkt.src_ip_addr; + status->dest_ip_addr = hw_status->frag_pkt.dest_ip_addr; + status->protocol = hw_status->frag_pkt.protocol; + status->ip_id = hw_status->frag_pkt.ip_id; + status->tlated_ip_addr = hw_status->frag_pkt.tlated_ip_addr; + status->ip_cksum_diff = hw_status->frag_pkt.ip_cksum_diff; + status->endp_src_idx = hw_status->frag_pkt.endp_src_idx; + status->endp_dest_idx = hw_status->frag_pkt.endp_dest_idx; + status->metadata = hw_status->frag_pkt.metadata; + status->seq_num = hw_status->frag_pkt.seq_num; + status->hdr_local = hw_status->frag_pkt.hdr_local; + status->hdr_offset = hw_status->frag_pkt.hdr_offset; + status->exception = hw_status->frag_pkt.exception; + status->nat_type = hw_status->frag_pkt.nat_type; +} + +static void __ipa_parse_gen_pkt_v5_0(struct ipahal_pkt_status *status, + const void *unparsed_status) +{ + bool is_ipv6; + union ipa_pkt_status_hw_v5_0 *hw_status = + (union ipa_pkt_status_hw_v5_0 *)unparsed_status; + + is_ipv6 = (hw_status->ipa_pkt.status_mask & 0x80) ? false : true; + status->pkt_len = hw_status->ipa_pkt.pkt_len; + status->endp_src_idx = hw_status->ipa_pkt.endp_src_idx; + status->endp_dest_idx = hw_status->ipa_pkt.endp_dest_idx; + status->metadata = hw_status->ipa_pkt.metadata; + status->flt_local = hw_status->ipa_pkt.flt_local; + status->flt_hash = hw_status->ipa_pkt.flt_hash; + status->flt_global = hw_status->ipa_pkt.flt_hash; + status->flt_ret_hdr = hw_status->ipa_pkt.flt_ret_hdr; + status->flt_miss = (hw_status->ipa_pkt.rt_rule_id == + IPAHAL_PKT_STATUS_FLTRT_RULE_MISS_ID); + status->flt_rule_id = hw_status->ipa_pkt.flt_rule_id; + status->rt_local = hw_status->ipa_pkt.rt_local; + status->rt_hash = hw_status->ipa_pkt.rt_hash; + status->ucp = hw_status->ipa_pkt.ucp; + status->rt_tbl_idx = hw_status->ipa_pkt.rt_tbl_idx; + status->rt_miss = (hw_status->ipa_pkt.rt_rule_id == + IPAHAL_PKT_STATUS_FLTRT_RULE_MISS_ID); + status->rt_rule_id = hw_status->ipa_pkt.rt_rule_id; + status->nat_hit = hw_status->ipa_pkt.nat_hit; + status->nat_entry_idx = hw_status->ipa_pkt.nat_entry_idx; + status->tag_info = hw_status->ipa_pkt.tag_info; + status->seq_num = hw_status->ipa_pkt.seq_num; + status->time_of_day_ctr = hw_status->ipa_pkt.time_of_day_ctr; + status->hdr_local = hw_status->ipa_pkt.hdr_local; + status->hdr_offset = hw_status->ipa_pkt.hdr_offset; + status->frag_hit = hw_status->ipa_pkt.frag_hit; + status->frag_rule = hw_status->ipa_pkt.frag_rule; + status->nat_type = hw_status->ipa_pkt.nat_type; + + status->exception = pkt_status_parse_exception(is_ipv6, + hw_status->ipa_pkt.exception); +} + +static void __ipa_parse_frag_pkt_v5_0(struct ipahal_pkt_status *status, + const void *unparsed_status) +{ + union ipa_pkt_status_hw_v5_0 *hw_status = + (union ipa_pkt_status_hw_v5_0 *)unparsed_status; + + status->frag_rule_idx = hw_status->frag_pkt.frag_rule_idx; + status->tbl_idx = hw_status->frag_pkt.tbl_idx; + status->src_ip_addr = hw_status->frag_pkt.src_ip_addr; + status->dest_ip_addr = hw_status->frag_pkt.dest_ip_addr; + status->protocol = hw_status->frag_pkt.protocol; + status->ip_id = hw_status->frag_pkt.ip_id; + status->tlated_ip_addr = hw_status->frag_pkt.tlated_ip_addr; + status->ip_cksum_diff = hw_status->frag_pkt.ip_cksum_diff; + status->endp_src_idx = hw_status->frag_pkt.endp_src_idx; + status->endp_dest_idx = hw_status->frag_pkt.endp_dest_idx; + status->metadata = hw_status->frag_pkt.metadata; + status->seq_num = hw_status->frag_pkt.seq_num; + status->hdr_local = hw_status->frag_pkt.hdr_local; + status->hdr_offset = hw_status->frag_pkt.hdr_offset; + status->exception = hw_status->frag_pkt.exception; + status->nat_type = hw_status->frag_pkt.nat_type; +} + +static void __ipa_parse_gen_pkt_v5_5(struct ipahal_pkt_status *status, + const void *unparsed_status) +{ + bool is_ipv6; + union ipa_pkt_status_hw_v5_5 *hw_status = + (union ipa_pkt_status_hw_v5_5 *)unparsed_status; + + is_ipv6 = (hw_status->ipa_pkt.status_mask & 0x80) ? false : true; + status->pkt_len = hw_status->ipa_pkt.pkt_len; + status->endp_src_idx = hw_status->ipa_pkt.endp_src_idx; + status->endp_dest_idx = hw_status->ipa_pkt.endp_dest_idx; + status->metadata = hw_status->ipa_pkt.metadata; + status->flt_local = hw_status->ipa_pkt.flt_local; + status->flt_hash = hw_status->ipa_pkt.flt_hash; + status->flt_global = hw_status->ipa_pkt.flt_hash; + status->flt_ret_hdr = hw_status->ipa_pkt.flt_ret_hdr; + status->flt_miss = (hw_status->ipa_pkt.rt_rule_id == + IPAHAL_PKT_STATUS_FLTRT_RULE_MISS_ID); + status->flt_rule_id = hw_status->ipa_pkt.flt_rule_id; + status->rt_local = hw_status->ipa_pkt.rt_local; + status->rt_hash = hw_status->ipa_pkt.rt_hash; + status->ucp = hw_status->ipa_pkt.ucp; + status->rt_tbl_idx = hw_status->ipa_pkt.rt_tbl_idx; + status->rt_miss = (hw_status->ipa_pkt.rt_rule_id == + IPAHAL_PKT_STATUS_FLTRT_RULE_MISS_ID); + status->rt_rule_id = hw_status->ipa_pkt.rt_rule_id; + status->nat_hit = hw_status->ipa_pkt.nat_hit; + status->nat_entry_idx = hw_status->ipa_pkt.nat_entry_idx; + status->tag_info = hw_status->ipa_pkt.tag_info; + status->egress_tc = hw_status->ipa_pkt.egress_tc; + status->ingress_tc = hw_status->ipa_pkt.ingress_tc; + status->seq_num = hw_status->ipa_pkt.seq_num; + status->time_of_day_ctr = hw_status->ipa_pkt.time_of_day_ctr; + status->hdr_local = hw_status->ipa_pkt.hdr_local; + status->hdr_offset = hw_status->ipa_pkt.hdr_offset; + status->frag_hit = hw_status->ipa_pkt.frag_hit; + status->frag_rule = hw_status->ipa_pkt.frag_rule; + status->nat_type = hw_status->ipa_pkt.nat_type; + status->nat_exc_suppress = hw_status->ipa_pkt.nat_exc_suppress; + status->tsp = hw_status->ipa_pkt.tsp; + status->ttl_dec = hw_status->ipa_pkt.ttl_dec; + + status->exception = pkt_status_parse_exception(is_ipv6, + hw_status->ipa_pkt.exception); +} + + +static void __ipa_parse_frag_pkt_v5_5(struct ipahal_pkt_status *status, + const void *unparsed_status) +{ + union ipa_pkt_status_hw_v5_5 *hw_status = + (union ipa_pkt_status_hw_v5_5 *)unparsed_status; + + status->frag_rule_idx = hw_status->frag_pkt.frag_rule_idx; + status->tbl_idx = hw_status->frag_pkt.tbl_idx; + status->src_ip_addr = hw_status->frag_pkt.src_ip_addr; + status->dest_ip_addr = hw_status->frag_pkt.dest_ip_addr; + status->protocol = hw_status->frag_pkt.protocol; + status->ip_id = hw_status->frag_pkt.ip_id; + status->tlated_ip_addr = hw_status->frag_pkt.tlated_ip_addr; + status->ip_cksum_diff = hw_status->frag_pkt.ip_cksum_diff; + status->endp_src_idx = hw_status->frag_pkt.endp_src_idx; + status->endp_dest_idx = hw_status->frag_pkt.endp_dest_idx; + status->metadata = hw_status->frag_pkt.metadata; + status->seq_num = hw_status->frag_pkt.seq_num; + status->hdr_local = hw_status->frag_pkt.hdr_local; + status->hdr_offset = hw_status->frag_pkt.hdr_offset; + status->exception = hw_status->frag_pkt.exception; + status->nat_type = hw_status->frag_pkt.nat_type; + status->hdr_ret = hw_status->frag_pkt.ret; + status->ll = hw_status->frag_pkt.ll; + status->ingress_tc = hw_status->frag_pkt.ingress_tc; + status->egress_tc = hw_status->frag_pkt.egress_tc; + status->pd = hw_status->frag_pkt.pd; +} + + +static void ipa_pkt_status_parse( + const void *unparsed_status, struct ipahal_pkt_status *status); +static void ipa_pkt_status_parse_thin(const void *unparsed_status, + struct ipahal_pkt_status_thin *status); +static void ipa_pkt_status_parse_thin_v5_0(const void *unparsed_status, + struct ipahal_pkt_status_thin *status); +static void ipa_pkt_status_parse_thin_v5_5(const void *unparsed_status, + struct ipahal_pkt_status_thin *status); +static void ipa_pkt_status_parse( + const void *unparsed_status, struct ipahal_pkt_status *status); +static void ipa_pkt_status_parse_v5_0( + const void *unparsed_status, struct ipahal_pkt_status *status); +static void ipa_pkt_status_parse_v5_5( + const void *unparsed_status, struct ipahal_pkt_status *status); +/* + * struct ipahal_pkt_status_obj - Pakcet Status H/W information for + * specific IPA version + * @size: H/W size of the status packet + * @parse: CB that parses the H/W packet status into the abstracted structure + * @parse_thin: light weight CB that parses only some of the fields for + * data path optimization + */ +struct ipahal_pkt_status_obj { + u32 size; + void (*parse)(const void *unparsed_status, + struct ipahal_pkt_status *status); + void (*parse_thin)(const void *unparsed_status, + struct ipahal_pkt_status_thin *status); + void (*__parse_gen_pkt)(struct ipahal_pkt_status *status, + const void *unparsed_status); + void (*__parse_frag_pkt)(struct ipahal_pkt_status *status, + const void *unparsed_status); +}; + +/* + * This table contains the info regard packet status for IPAv3 and later + * Information like: size of packet status and parsing function + * All the information on the pkt Status on IPAv3 are statically defined below. + * If information is missing regard some IPA version, the init function + * will fill it with the information from the previous IPA version. + * Information is considered missing if all of the fields are 0 + */ +static struct ipahal_pkt_status_obj ipahal_pkt_status_objs[IPA_HW_MAX] = { + /* IPAv3 */ + [IPA_HW_v3_0] = { + IPA3_0_PKT_STATUS_SIZE, + ipa_pkt_status_parse, + ipa_pkt_status_parse_thin, + __ipa_parse_gen_pkt, + __ipa_parse_frag_pkt, + }, + /* IPAv5 */ + [IPA_HW_v5_0] = { + IPA3_0_PKT_STATUS_SIZE, + ipa_pkt_status_parse_v5_0, + ipa_pkt_status_parse_thin_v5_0, + __ipa_parse_gen_pkt_v5_0, + __ipa_parse_frag_pkt_v5_0, + }, + /* IPAv5.5 */ + [IPA_HW_v5_5] = { + IPA3_0_PKT_STATUS_SIZE, + ipa_pkt_status_parse_v5_5, + ipa_pkt_status_parse_thin_v5_5, + __ipa_parse_gen_pkt_v5_5, + __ipa_parse_frag_pkt_v5_5, + }, +}; + +static inline enum ipahal_pkt_status_opcode ipa_hw_opcode_to_opcode( + const u8 hw_opcode) +{ + enum ipahal_pkt_status_opcode opcode = 0; + + switch (hw_opcode) { + case 0x1: + opcode = IPAHAL_PKT_STATUS_OPCODE_PACKET; + break; + case 0x2: + opcode = IPAHAL_PKT_STATUS_OPCODE_NEW_FRAG_RULE; + break; + case 0x4: + opcode = IPAHAL_PKT_STATUS_OPCODE_DROPPED_PACKET; + break; + case 0x8: + opcode = IPAHAL_PKT_STATUS_OPCODE_SUSPENDED_PACKET; + break; + case 0x10: + opcode = IPAHAL_PKT_STATUS_OPCODE_LOG; + break; + case 0x20: + opcode = IPAHAL_PKT_STATUS_OPCODE_DCMP; + break; + case 0x40: + opcode = IPAHAL_PKT_STATUS_OPCODE_PACKET_2ND_PASS; + break; + default: + IPAHAL_ERR_RL("unsupported Status Opcode 0x%x\n", hw_opcode); + } + + return opcode; +} + +static inline enum ipahal_pkt_status_nat_type ipa_hw_nat_type_to_nat_type( + const enum ipahal_pkt_status_nat_type hw_nat_type) +{ + enum ipahal_pkt_status_nat_type nat_type = IPAHAL_PKT_STATUS_NAT_NONE; + + switch (hw_nat_type) { + case 0: + nat_type = IPAHAL_PKT_STATUS_NAT_NONE; + break; + case 1: + nat_type = IPAHAL_PKT_STATUS_NAT_SRC; + break; + case 2: + nat_type = IPAHAL_PKT_STATUS_NAT_DST; + break; + default: + IPAHAL_ERR_RL("unsupported Status NAT type 0x%x\n",hw_nat_type); + } + + return nat_type; +} + +static inline void ipa_set_pkt_status_mask(const u16 hw_status_mask, + struct ipahal_pkt_status *status) +{ + IPA_PKT_STATUS_SET_MSK(0x1, IPAHAL_PKT_STATUS_MASK_FRAG_PROCESS_SHFT); + IPA_PKT_STATUS_SET_MSK(0x2, IPAHAL_PKT_STATUS_MASK_FILT_PROCESS_SHFT); + IPA_PKT_STATUS_SET_MSK(0x4, IPAHAL_PKT_STATUS_MASK_NAT_PROCESS_SHFT); + IPA_PKT_STATUS_SET_MSK(0x8, IPAHAL_PKT_STATUS_MASK_ROUTE_PROCESS_SHFT); + IPA_PKT_STATUS_SET_MSK(0x10, IPAHAL_PKT_STATUS_MASK_TAG_VALID_SHFT); + IPA_PKT_STATUS_SET_MSK(0x20, IPAHAL_PKT_STATUS_MASK_FRAGMENT_SHFT); + IPA_PKT_STATUS_SET_MSK(0x40, + IPAHAL_PKT_STATUS_MASK_FIRST_FRAGMENT_SHFT); + IPA_PKT_STATUS_SET_MSK(0x80, IPAHAL_PKT_STATUS_MASK_V4_SHFT); + IPA_PKT_STATUS_SET_MSK(0x100, + IPAHAL_PKT_STATUS_MASK_CKSUM_PROCESS_SHFT); + IPA_PKT_STATUS_SET_MSK(0x200, IPAHAL_PKT_STATUS_MASK_AGGR_PROCESS_SHFT); + IPA_PKT_STATUS_SET_MSK(0x400, IPAHAL_PKT_STATUS_MASK_DEST_EOT_SHFT); + IPA_PKT_STATUS_SET_MSK(0x800, + IPAHAL_PKT_STATUS_MASK_DEAGGR_PROCESS_SHFT); + IPA_PKT_STATUS_SET_MSK(0x1000, IPAHAL_PKT_STATUS_MASK_DEAGG_FIRST_SHFT); + IPA_PKT_STATUS_SET_MSK(0x2000, IPAHAL_PKT_STATUS_MASK_SRC_EOT_SHFT); + IPA_PKT_STATUS_SET_MSK(0x4000, IPAHAL_PKT_STATUS_MASK_PREV_EOT_SHFT); + IPA_PKT_STATUS_SET_MSK(0x8000, IPAHAL_PKT_STATUS_MASK_BYTE_LIMIT_SHFT); + status->status_mask &= 0xFFFF; +} + +static inline void ipa_set_pkt_status_mask_v5_5(const u16 hw_status_mask, + struct ipahal_pkt_status *status) +{ + IPA_PKT_STATUS_SET_MSK(0x1, IPAHAL_PKT_STATUS_MASK_FRAG_PROCESS_SHFT); + IPA_PKT_STATUS_SET_MSK(0x2, IPAHAL_PKT_STATUS_MASK_FILT_PROCESS_SHFT); + IPA_PKT_STATUS_SET_MSK(0x4, IPAHAL_PKT_STATUS_MASK_NAT_PROCESS_SHFT); + IPA_PKT_STATUS_SET_MSK(0x8, IPAHAL_PKT_STATUS_MASK_ROUTE_PROCESS_SHFT); + IPA_PKT_STATUS_SET_MSK(0x10, IPAHAL_PKT_STATUS_MASK_TAG_VALID_SHFT); + IPA_PKT_STATUS_SET_MSK(0x20, IPAHAL_PKT_STATUS_MASK_FRAGMENT_SHFT); + IPA_PKT_STATUS_SET_MSK(0x40, + IPAHAL_PKT_STATUS_MASK_FIRST_FRAGMENT_SHFT); + IPA_PKT_STATUS_SET_MSK(0x80, IPAHAL_PKT_STATUS_MASK_V4_SHFT); + IPA_PKT_STATUS_SET_MSK(0x100, + IPAHAL_PKT_STATUS_MASK_CKSUM_PROCESS_SHFT); + IPA_PKT_STATUS_SET_MSK(0x200, IPAHAL_PKT_STATUS_MASK_AGGR_PROCESS_SHFT); + IPA_PKT_STATUS_SET_MSK(0x400, IPAHAL_PKT_STATUS_MASK_OPENED_FRAME_SHFT); + IPA_PKT_STATUS_SET_MSK(0x800, + IPAHAL_PKT_STATUS_MASK_DEAGGR_PROCESS_SHFT); + IPA_PKT_STATUS_SET_MSK(0x1000, IPAHAL_PKT_STATUS_MASK_DEAGG_FIRST_SHFT); + IPA_PKT_STATUS_SET_MSK(0x2000, IPAHAL_PKT_STATUS_MASK_SRC_EOT_SHFT); + IPA_PKT_STATUS_SET_MSK(0x4000, IPAHAL_PKT_STATUS_MASK_RQOS_NAS_SHFT); + IPA_PKT_STATUS_SET_MSK(0x8000, IPAHAL_PKT_STATUS_MASK_RQOS_AS_SHFT); + status->status_mask &= 0xFFFF; +} + + +static void ipa_pkt_status_parse( + const void *unparsed_status, struct ipahal_pkt_status *status) +{ + union ipa_pkt_status_hw *hw_status = + (union ipa_pkt_status_hw *)unparsed_status; + + status->status_opcode = + ipa_hw_opcode_to_opcode(hw_status->ipa_pkt.status_opcode); + + if (status->status_opcode == IPAHAL_PKT_STATUS_OPCODE_NEW_FRAG_RULE) + ipahal_pkt_status_objs[ipahal_ctx->hw_type].\ + __parse_frag_pkt(status, unparsed_status); + else + ipahal_pkt_status_objs[ipahal_ctx->hw_type].\ + __parse_gen_pkt(status, unparsed_status); + + status->nat_type = ipa_hw_nat_type_to_nat_type(status->nat_type); + + ipa_set_pkt_status_mask((u16)(hw_status->ipa_pkt.status_mask), status); +} + +static void ipa_pkt_status_parse_v5_0( + const void *unparsed_status, struct ipahal_pkt_status *status) +{ + union ipa_pkt_status_hw_v5_0 *hw_status = + (union ipa_pkt_status_hw_v5_0 *)unparsed_status; + + status->status_opcode = + ipa_hw_opcode_to_opcode(hw_status->ipa_pkt.status_opcode); + + if (status->status_opcode == IPAHAL_PKT_STATUS_OPCODE_NEW_FRAG_RULE) + ipahal_pkt_status_objs[ipahal_ctx->hw_type].\ + __parse_frag_pkt(status, unparsed_status); + else + ipahal_pkt_status_objs[ipahal_ctx->hw_type].\ + __parse_gen_pkt(status, unparsed_status); + + status->nat_type = ipa_hw_nat_type_to_nat_type(status->nat_type); + + ipa_set_pkt_status_mask((u16)(hw_status->ipa_pkt.status_mask), status); +} + +static void ipa_pkt_status_parse_v5_5( + const void *unparsed_status, struct ipahal_pkt_status *status) +{ + union ipa_pkt_status_hw_v5_5 *hw_status = + (union ipa_pkt_status_hw_v5_5 *)unparsed_status; + + status->status_opcode = + ipa_hw_opcode_to_opcode(hw_status->ipa_pkt.status_opcode); + + if (status->status_opcode == IPAHAL_PKT_STATUS_OPCODE_NEW_FRAG_RULE) + ipahal_pkt_status_objs[ipahal_ctx->hw_type].\ + __parse_frag_pkt(status, unparsed_status); + else + ipahal_pkt_status_objs[ipahal_ctx->hw_type].\ + __parse_gen_pkt(status, unparsed_status); + + status->nat_type = ipa_hw_nat_type_to_nat_type(status->nat_type); + + ipa_set_pkt_status_mask_v5_5((u16)(hw_status->ipa_pkt.status_mask), status); +} + +/* + * ipa_pkt_status_parse_thin() - Parse some of the packet status fields + * for specific usage in the LAN rx data path where parsing needs to be done + * but only for specific fields. + * @unparsed_status: Pointer to H/W format of the packet status as read from HW + * @status: Pointer to pre-allocated buffer where the parsed info will be + * stored + */ +static void ipa_pkt_status_parse_thin(const void *unparsed_status, + struct ipahal_pkt_status_thin *status) +{ + union ipa_pkt_status_hw *hw_status = + (union ipa_pkt_status_hw *)unparsed_status; + bool is_ipv6 = (hw_status->ipa_pkt.status_mask & 0x80) ? false : true; + + IPAHAL_DBG_LOW("Parse Thin Status Packet\n"); + status->metadata = hw_status->ipa_pkt.metadata; + status->endp_src_idx = hw_status->ipa_pkt.endp_src_idx; + status->ucp = hw_status->ipa_pkt.ucp; + status->exception = pkt_status_parse_exception(is_ipv6, + hw_status->ipa_pkt.exception); +} + +/* + * ipa_pkt_status_parse_thin_v5_0() - Parse some of the v5.0 packet status + * fields for specific usage in the LAN rx data path where parsing needs + * to be done but only for specific fields. + * @unparsed_status: Pointer to H/W format of the packet status as read from HW + * @status: Pointer to pre-allocated buffer where the parsed info will be + * stored + */ +static void ipa_pkt_status_parse_thin_v5_0(const void *unparsed_status, + struct ipahal_pkt_status_thin *status) +{ + union ipa_pkt_status_hw_v5_0 *hw_status = + (union ipa_pkt_status_hw_v5_0 *)unparsed_status; + bool is_ipv6 = + (hw_status->ipa_pkt.status_mask & 0x80) ? false : true; + + IPAHAL_DBG_LOW("Parse Thin Status Packet\n"); + status->metadata = hw_status->ipa_pkt.metadata; + status->endp_src_idx = hw_status->ipa_pkt.endp_src_idx; + status->ucp = hw_status->ipa_pkt.ucp; + status->exception = pkt_status_parse_exception(is_ipv6, + hw_status->ipa_pkt.exception); +} + +/* + * ipa_pkt_status_parse_thin_v5_5() - Parse some of the v5.5 packet status + * fields for specific usage in the LAN rx data path where parsing needs + * to be done but only for specific fields. + * @unparsed_status: Pointer to H/W format of the packet status as read from HW + * @status: Pointer to pre-allocated buffer where the parsed info will be + * stored + */ +static void ipa_pkt_status_parse_thin_v5_5(const void *unparsed_status, + struct ipahal_pkt_status_thin *status) +{ + union ipa_pkt_status_hw_v5_5 *hw_status = + (union ipa_pkt_status_hw_v5_5 *)unparsed_status; + bool is_ipv6 = + (hw_status->ipa_pkt.status_mask & 0x80) ? false : true; + + IPAHAL_DBG_LOW("Parse Thin Status Packet\n"); + status->metadata = hw_status->ipa_pkt.metadata; + status->endp_src_idx = hw_status->ipa_pkt.endp_src_idx; + status->ucp = hw_status->ipa_pkt.ucp; + status->exception = pkt_status_parse_exception(is_ipv6, + hw_status->ipa_pkt.exception); +} + +/* + * ipahal_pkt_status_init() - Build the packet status information array + * for the different IPA versions + * See ipahal_pkt_status_objs[] comments + */ +static int ipahal_pkt_status_init(enum ipa_hw_type ipa_hw_type) +{ + int i; + struct ipahal_pkt_status_obj zero_obj; + + IPAHAL_DBG_LOW("Entry - HW_TYPE=%d\n", ipa_hw_type); + + if ((ipa_hw_type < 0) || (ipa_hw_type >= IPA_HW_MAX)) { + IPAHAL_ERR("invalid IPA HW type (%d)\n", ipa_hw_type); + return -EINVAL; + } + + /* + * Since structure alignment is implementation dependent, + * add test to avoid different and incompatible data layouts. + * If test fails it also means that ipahal_pkt_status_parse_thin + * need to be checked. + * + * In case new H/W has different size or structure of status packet, + * add a compile time validty check for it like below (as well as + * the new defines and/or the new strucutre in the internal header). + */ + BUILD_BUG_ON(sizeof(union ipa_pkt_status_hw) != + IPA3_0_PKT_STATUS_SIZE); + + memset(&zero_obj, 0, sizeof(zero_obj)); + for (i = IPA_HW_v3_0 ; i < ipa_hw_type ; i++) { + if (!memcmp(&ipahal_pkt_status_objs[i+1], &zero_obj, + sizeof(struct ipahal_pkt_status_obj))) { + memcpy(&ipahal_pkt_status_objs[i+1], + &ipahal_pkt_status_objs[i], + sizeof(struct ipahal_pkt_status_obj)); + } else { + /* + * explicitly overridden Packet Status info + * Check validity + */ + if (!ipahal_pkt_status_objs[i+1].size) { + IPAHAL_ERR( + "Packet Status with zero size ipa_ver=%d\n", + i+1); + WARN_ON(1); + } + if (!ipahal_pkt_status_objs[i+1].parse) { + IPAHAL_ERR( + "Packet Status without Parse func ipa_ver=%d\n", + i+1); + WARN_ON(1); + } + if (!ipahal_pkt_status_objs[i+1].parse_thin) { + IPAHAL_ERR( + "Packet Status without Parse_thin func ipa_ver=%d\n", + i+1); + WARN_ON(1); + } + if (!ipahal_pkt_status_objs[i+1].__parse_gen_pkt) { + IPAHAL_ERR( + "Packet Status without parse_gen func ipa_ver=%d\n", + i+1); + WARN_ON(1); + } + if (!ipahal_pkt_status_objs[i+1].__parse_frag_pkt) { + IPAHAL_ERR( + "Packet Status without parse_frag func ipa_ver=%d\n", + i+1); + WARN_ON(1); + } + } + } + + return 0; +} + +/* + * ipahal_pkt_status_get_size() - Get H/W size of packet status + */ +u32 ipahal_pkt_status_get_size(void) +{ + return ipahal_pkt_status_objs[ipahal_ctx->hw_type].size; +} + +/* + * ipahal_pkt_status_parse() - Parse Packet Status payload to abstracted form + * @unparsed_status: Pointer to H/W format of the packet status as read from H/W + * @status: Pointer to pre-allocated buffer where the parsed info will be stored + */ +void ipahal_pkt_status_parse(const void *unparsed_status, + struct ipahal_pkt_status *status) +{ + if (!unparsed_status || !status) { + IPAHAL_ERR("Input Error: unparsed_status=%pK status=%pK\n", + unparsed_status, status); + return; + } + + IPAHAL_DBG_LOW("Parse Status Packet\n"); + memset(status, 0, sizeof(*status)); + ipahal_pkt_status_objs[ipahal_ctx->hw_type].parse(unparsed_status, + status); +} + +/* + * ipahal_pkt_status_parse_thin() - Similar to ipahal_pkt_status_parse, + * the difference is it only parses some of the status packet fields + * used for TP optimization. + * @unparsed_status: Pointer to H/W format of the packet status as read from H/W + * @status: Pointer to pre-allocated buffer where the parsed info will be stored + */ +void ipahal_pkt_status_parse_thin(const void *unparsed_status, + struct ipahal_pkt_status_thin *status) +{ + if (!unparsed_status || !status) { + IPAHAL_ERR("Input Error: unparsed_status=%pK status=%pK\n", + unparsed_status, status); + return; + } + IPAHAL_DBG_LOW("Parse_thin Status Packet\n"); + ipahal_pkt_status_objs[ipahal_ctx->hw_type].parse_thin(unparsed_status, + status); +} + +/* + * ipahal_pkt_status_exception_str() - returns string represents exception type + * @exception: [in] The exception type + */ +const char *ipahal_pkt_status_exception_str( + enum ipahal_pkt_status_exception exception) +{ + if (exception < 0 || exception >= IPAHAL_PKT_STATUS_EXCEPTION_MAX) { + IPAHAL_ERR( + "requested string of invalid pkt_status exception=%d\n", + exception); + return "Invalid PKT_STATUS_EXCEPTION"; + } + + return ipahal_pkt_status_exception_to_str[exception]; +} + +#ifdef CONFIG_DEBUG_FS +static void ipahal_debugfs_init(void) +{ + ipahal_ctx->dent = debugfs_create_dir("ipahal", 0); + if (!ipahal_ctx->dent || IS_ERR(ipahal_ctx->dent)) { + IPAHAL_ERR("fail to create ipahal debugfs folder\n"); + goto fail; + } + + return; +fail: + debugfs_remove_recursive(ipahal_ctx->dent); + ipahal_ctx->dent = NULL; +} + +static void ipahal_debugfs_remove(void) +{ + if (!ipahal_ctx) + return; + + if (IS_ERR(ipahal_ctx->dent)) { + IPAHAL_ERR("ipahal debugfs folder was not created\n"); + return; + } + + debugfs_remove_recursive(ipahal_ctx->dent); +} +#else /* CONFIG_DEBUG_FS */ +static void ipahal_debugfs_init(void) {} +static void ipahal_debugfs_remove(void) {} +#endif /* CONFIG_DEBUG_FS */ + +/* + * ipahal_cp_hdr_to_hw_buff_v3() - copy header to hardware buffer according to + * base address and offset given. + * @base: dma base address + * @offset: offset from base address where the data will be copied + * @hdr: the header to be copied + * @hdr_len: the length of the header + */ +static void ipahal_cp_hdr_to_hw_buff_v3(void *const base, u32 offset, + u8 *const hdr, u32 hdr_len) +{ + memcpy(base + offset, hdr, hdr_len); +} + +/* Header address update logic. */ +#define IPAHAL_CP_PROC_CTX_HEADER_UPDATE(hdr_lsb, hdr_msb, addr) \ + do { \ + hdr_lsb = lower_32_bits(addr); \ + hdr_msb = upper_32_bits(addr); \ + } while (0) + +/* + * ipahal_cp_proc_ctx_to_hw_buff_v3() - copy processing context to + * base address and offset given. + * @type: header processing context type (no processing context, + * IPA_HDR_PROC_ETHII_TO_ETHII etc.) + * @base: dma base address + * @offset: offset from base address where the data will be copied + * @hdr_len: the length of the header + * @hdr_base_addr: base address in table + * @offset_entry: offset from hdr_base_addr in table + * @l2tp_params: l2tp parameters + * @eogre_params: eogre parameters + * @generic_params: generic proc_ctx params + * @rtp_params: rtp proc_ctx params + * @is_64: Indicates whether header base address/dma base address is 64 bit. + */ +static int ipahal_cp_proc_ctx_to_hw_buff_v3(enum ipa_hdr_proc_type type, + void *const base, u32 offset, + u32 hdr_len, u64 hdr_base_addr, + struct ipa_hdr_offset_entry *offset_entry, + struct ipa_l2tp_hdr_proc_ctx_params *l2tp_params, + struct ipa_eogre_hdr_proc_ctx_params *eogre_params, + struct ipa_eth_II_to_eth_II_ex_procparams *generic_params, + struct ipa_rtp_hdr_proc_ctx_params *rtp_params, + bool is_64) +{ + u64 hdr_addr; + + if (type == IPA_HDR_PROC_NONE) { + struct ipa_hw_hdr_proc_ctx_add_hdr_seq *ctx; + + ctx = (struct ipa_hw_hdr_proc_ctx_add_hdr_seq *) + (base + offset); + ctx->hdr_add.tlv.type = IPA_PROC_CTX_TLV_TYPE_HDR_ADD; + ctx->hdr_add.tlv.length = 2; + ctx->hdr_add.tlv.value = hdr_len; + hdr_addr = hdr_base_addr + offset_entry->offset; + IPAHAL_DBG("header address 0x%llx\n", + hdr_addr); + IPAHAL_CP_PROC_CTX_HEADER_UPDATE(ctx->hdr_add.hdr_addr, + ctx->hdr_add.hdr_addr_hi, hdr_addr); + if (!is_64) + ctx->hdr_add.hdr_addr_hi = 0; + ctx->end.type = IPA_PROC_CTX_TLV_TYPE_END; + ctx->end.length = 0; + ctx->end.value = 0; + } else if ((type == IPA_HDR_PROC_L2TP_HEADER_ADD) || + (type == IPA_HDR_PROC_L2TP_UDP_HEADER_ADD)) { + struct ipa_hw_hdr_proc_ctx_add_l2tp_hdr_cmd_seq *ctx; + + ctx = (struct ipa_hw_hdr_proc_ctx_add_l2tp_hdr_cmd_seq *) + (base + offset); + ctx->hdr_add.tlv.type = IPA_PROC_CTX_TLV_TYPE_HDR_ADD; + ctx->hdr_add.tlv.length = 2; + ctx->hdr_add.tlv.value = hdr_len; + hdr_addr = hdr_base_addr + offset_entry->offset; + IPAHAL_DBG("header address 0x%llx\n", + hdr_addr); + IPAHAL_CP_PROC_CTX_HEADER_UPDATE(ctx->hdr_add.hdr_addr, + ctx->hdr_add.hdr_addr_hi, hdr_addr); + if (!is_64) + ctx->hdr_add.hdr_addr_hi = 0; + ctx->l2tp_params.tlv.type = IPA_PROC_CTX_TLV_TYPE_PROC_CMD; + ctx->l2tp_params.tlv.length = 1; + if (type == IPA_HDR_PROC_L2TP_HEADER_ADD) + ctx->l2tp_params.tlv.value = + IPA_HDR_UCP_L2TP_HEADER_ADD; + else + ctx->l2tp_params.tlv.value = + IPA_HDR_UCP_L2TP_UDP_HEADER_ADD; + ctx->l2tp_params.l2tp_params.second_pass = + l2tp_params->hdr_add_param.second_pass; + ctx->l2tp_params.l2tp_params.eth_hdr_retained = + l2tp_params->hdr_add_param.eth_hdr_retained; + ctx->l2tp_params.l2tp_params.input_ip_version = + l2tp_params->hdr_add_param.input_ip_version; + ctx->l2tp_params.l2tp_params.output_ip_version = + l2tp_params->hdr_add_param.output_ip_version; + + IPAHAL_DBG("command id %d\n", ctx->l2tp_params.tlv.value); + ctx->end.type = IPA_PROC_CTX_TLV_TYPE_END; + ctx->end.length = 0; + ctx->end.value = 0; + } else if (type == IPA_HDR_PROC_L2TP_HEADER_REMOVE) { + struct ipa_hw_hdr_proc_ctx_remove_l2tp_hdr_cmd_seq *ctx; + + ctx = (struct ipa_hw_hdr_proc_ctx_remove_l2tp_hdr_cmd_seq *) + (base + offset); + ctx->hdr_add.tlv.type = IPA_PROC_CTX_TLV_TYPE_HDR_ADD; + ctx->hdr_add.tlv.length = 2; + ctx->hdr_add.tlv.value = hdr_len; + hdr_addr = hdr_base_addr + offset_entry->offset; + IPAHAL_DBG("header address 0x%llx length %d\n", + hdr_addr, ctx->hdr_add.tlv.value); + IPAHAL_CP_PROC_CTX_HEADER_UPDATE(ctx->hdr_add.hdr_addr, + ctx->hdr_add.hdr_addr_hi, hdr_addr); + if (!is_64) + ctx->hdr_add.hdr_addr_hi = 0; + ctx->l2tp_params.tlv.type = IPA_PROC_CTX_TLV_TYPE_PROC_CMD; + ctx->l2tp_params.tlv.length = 1; + ctx->l2tp_params.tlv.value = + IPA_HDR_UCP_L2TP_HEADER_REMOVE; + ctx->l2tp_params.l2tp_params.hdr_len_remove = + l2tp_params->hdr_remove_param.hdr_len_remove; + ctx->l2tp_params.l2tp_params.eth_hdr_retained = + l2tp_params->hdr_remove_param.eth_hdr_retained; + ctx->l2tp_params.l2tp_params.hdr_ofst_pkt_size_valid = + l2tp_params->hdr_remove_param.hdr_ofst_pkt_size_valid; + ctx->l2tp_params.l2tp_params.hdr_ofst_pkt_size = + l2tp_params->hdr_remove_param.hdr_ofst_pkt_size; + ctx->l2tp_params.l2tp_params.hdr_endianness = + l2tp_params->hdr_remove_param.hdr_endianness; + IPAHAL_DBG("hdr ofst valid: %d, hdr ofst pkt size: %d\n", + ctx->l2tp_params.l2tp_params.hdr_ofst_pkt_size_valid, + ctx->l2tp_params.l2tp_params.hdr_ofst_pkt_size); + IPAHAL_DBG("endianness: %d\n", + ctx->l2tp_params.l2tp_params.hdr_endianness); + + IPAHAL_DBG("command id %d\n", ctx->l2tp_params.tlv.value); + ctx->end.type = IPA_PROC_CTX_TLV_TYPE_END; + ctx->end.length = 0; + ctx->end.value = 0; + } else if (type == IPA_HDR_PROC_L2TP_UDP_HEADER_REMOVE) { + struct ipa_hw_hdr_proc_ctx_remove_l2tp_hdr_cmd_seq *ctx; + + ctx = (struct ipa_hw_hdr_proc_ctx_remove_l2tp_hdr_cmd_seq *) + (base + offset); + ctx->hdr_add.tlv.type = IPA_PROC_CTX_TLV_TYPE_HDR_ADD; + ctx->hdr_add.tlv.length = 2; + if (l2tp_params->hdr_remove_param.eth_hdr_retained) { + ctx->hdr_add.tlv.value = hdr_len; + hdr_addr = hdr_base_addr + offset_entry->offset; + IPAHAL_DBG("header address 0x%llx length %d\n", + hdr_addr, ctx->hdr_add.tlv.value); + IPAHAL_CP_PROC_CTX_HEADER_UPDATE(ctx->hdr_add.hdr_addr, + ctx->hdr_add.hdr_addr_hi, hdr_addr); + if (!is_64) + ctx->hdr_add.hdr_addr_hi = 0; + } else { + ctx->hdr_add.tlv.value = 0; + } + ctx->l2tp_params.tlv.type = IPA_PROC_CTX_TLV_TYPE_PROC_CMD; + ctx->l2tp_params.tlv.length = 1; + ctx->l2tp_params.tlv.value = + IPA_HDR_UCP_L2TP_UDP_HEADER_REMOVE; + ctx->l2tp_params.l2tp_params.hdr_len_remove = + l2tp_params->hdr_remove_param.hdr_len_remove; + ctx->l2tp_params.l2tp_params.eth_hdr_retained = + l2tp_params->hdr_remove_param.eth_hdr_retained; + ctx->l2tp_params.l2tp_params.hdr_ofst_pkt_size_valid = + l2tp_params->hdr_remove_param.hdr_ofst_pkt_size_valid; + ctx->l2tp_params.l2tp_params.hdr_ofst_pkt_size = + l2tp_params->hdr_remove_param.hdr_ofst_pkt_size; + ctx->l2tp_params.l2tp_params.hdr_endianness = + l2tp_params->hdr_remove_param.hdr_endianness; + IPAHAL_DBG("hdr ofst valid: %d, hdr ofst pkt size: %d\n", + ctx->l2tp_params.l2tp_params.hdr_ofst_pkt_size_valid, + ctx->l2tp_params.l2tp_params.hdr_ofst_pkt_size); + IPAHAL_DBG("endianness: %d\n", + ctx->l2tp_params.l2tp_params.hdr_endianness); + + IPAHAL_DBG("command id %d\n", ctx->l2tp_params.tlv.value); + ctx->end.type = IPA_PROC_CTX_TLV_TYPE_END; + ctx->end.length = 0; + ctx->end.value = 0; + } else if (type == IPA_HDR_PROC_ETHII_TO_ETHII_EX) { + struct ipa_hw_hdr_proc_ctx_add_hdr_cmd_seq_ex *ctx; + + ctx = (struct ipa_hw_hdr_proc_ctx_add_hdr_cmd_seq_ex *) + (base + offset); + + ctx->hdr_add.tlv.type = IPA_PROC_CTX_TLV_TYPE_HDR_ADD; + ctx->hdr_add.tlv.length = 2; + ctx->hdr_add.tlv.value = hdr_len; + hdr_addr = hdr_base_addr + offset_entry->offset; + IPAHAL_DBG("header address 0x%x\n", + ctx->hdr_add.hdr_addr); + IPAHAL_CP_PROC_CTX_HEADER_UPDATE(ctx->hdr_add.hdr_addr, + ctx->hdr_add.hdr_addr_hi, hdr_addr); + if (!is_64) + ctx->hdr_add.hdr_addr_hi = 0; + + ctx->hdr_add_ex.tlv.type = IPA_PROC_CTX_TLV_TYPE_PROC_CMD; + ctx->hdr_add_ex.tlv.length = 1; + ctx->hdr_add_ex.tlv.value = IPA_HDR_UCP_ETHII_TO_ETHII_EX; + + ctx->hdr_add_ex.params.input_ethhdr_negative_offset = + generic_params->input_ethhdr_negative_offset; + ctx->hdr_add_ex.params.output_ethhdr_negative_offset = + generic_params->output_ethhdr_negative_offset; + ctx->hdr_add_ex.params.reserved = 0; + + ctx->end.type = IPA_PROC_CTX_TLV_TYPE_END; + ctx->end.length = 0; + ctx->end.value = 0; + } else if (type == IPA_HDR_PROC_EoGRE_HEADER_ADD) { + struct ipa_hw_hdr_proc_ctx_add_eogre_hdr_cmd_seq *ctx = + (struct ipa_hw_hdr_proc_ctx_add_eogre_hdr_cmd_seq *) + (base + offset); + + ctx->hdr_add.tlv.type = IPA_PROC_CTX_TLV_TYPE_HDR_ADD; + ctx->hdr_add.tlv.length = 2; + ctx->hdr_add.tlv.value = hdr_len; + hdr_addr = hdr_base_addr + offset_entry->offset; + IPAHAL_DBG("header address 0x%llx\n", + hdr_addr); + IPAHAL_CP_PROC_CTX_HEADER_UPDATE(ctx->hdr_add.hdr_addr, + ctx->hdr_add.hdr_addr_hi, hdr_addr); + if (!is_64) + ctx->hdr_add.hdr_addr_hi = 0; + ctx->eogre_params.tlv.type = IPA_PROC_CTX_TLV_TYPE_PROC_CMD; + ctx->eogre_params.tlv.length = 1; + ctx->eogre_params.tlv.value = IPA_HDR_UCP_EoGRE_HEADER_ADD; + ctx->eogre_params.eogre_params.eth_hdr_retained = + eogre_params->hdr_add_param.eth_hdr_retained; + ctx->eogre_params.eogre_params.input_ip_version = + eogre_params->hdr_add_param.input_ip_version; + ctx->eogre_params.eogre_params.output_ip_version = + eogre_params->hdr_add_param.output_ip_version; + ctx->eogre_params.eogre_params.second_pass = + eogre_params->hdr_add_param.second_pass; + IPAHAL_DBG("command id %d\n", ctx->eogre_params.tlv.value); + IPAHAL_DBG("eth_hdr_retained %d input_ip_version %d output_ip_version %d second_pass %d\n", + eogre_params->hdr_add_param.eth_hdr_retained, + eogre_params->hdr_add_param.input_ip_version, + eogre_params->hdr_add_param.output_ip_version, + eogre_params->hdr_add_param.second_pass); + ctx->end.type = IPA_PROC_CTX_TLV_TYPE_END; + ctx->end.length = 0; + ctx->end.value = 0; + } else if (type == IPA_HDR_PROC_EoGRE_HEADER_REMOVE) { + struct ipa_hw_hdr_proc_ctx_remove_eogre_hdr_cmd_seq *ctx = + (struct ipa_hw_hdr_proc_ctx_remove_eogre_hdr_cmd_seq *) + (base + offset); + + ctx->hdr_add.tlv.type = IPA_PROC_CTX_TLV_TYPE_HDR_ADD; + ctx->hdr_add.tlv.length = 2; + ctx->hdr_add.tlv.value = hdr_len; + hdr_addr = hdr_base_addr + offset_entry->offset; + IPAHAL_DBG("header address 0x%llx length %d\n", + hdr_addr, ctx->hdr_add.tlv.value); + IPAHAL_CP_PROC_CTX_HEADER_UPDATE( + ctx->hdr_add.hdr_addr, + ctx->hdr_add.hdr_addr_hi, hdr_addr); + if (!is_64) + ctx->hdr_add.hdr_addr_hi = 0; + ctx->eogre_params.tlv.type = IPA_PROC_CTX_TLV_TYPE_PROC_CMD; + ctx->eogre_params.tlv.length = 1; + ctx->eogre_params.tlv.value = IPA_HDR_UCP_EoGRE_HEADER_REMOVE; + ctx->eogre_params.eogre_params.hdr_len_remove = + eogre_params->hdr_remove_param.hdr_len_remove; + ctx->end.type = IPA_PROC_CTX_TLV_TYPE_END; + ctx->end.length = 0; + ctx->end.value = 0; + } else if ((type == IPA_HDR_PROC_RTP_METADATA_STREAM0) || + (type == IPA_HDR_PROC_RTP_METADATA_STREAM1) || + (type == IPA_HDR_PROC_RTP_METADATA_STREAM2) || + (type == IPA_HDR_PROC_RTP_METADATA_STREAM3)) { + struct ipa_hw_hdr_proc_ctx_rtp_hdr_cmd_seq *ctx = + (struct ipa_hw_hdr_proc_ctx_rtp_hdr_cmd_seq *) + (base + offset); + ctx->hdr_add.tlv.type = IPA_PROC_CTX_TLV_TYPE_HDR_ADD; + ctx->hdr_add.tlv.length = 2; + ctx->hdr_add.tlv.value = 0; + hdr_addr = hdr_base_addr + offset_entry->offset; + IPAHAL_DBG("header address 0x%llx length %d\n", + hdr_addr, ctx->hdr_add.tlv.value); + IPAHAL_CP_PROC_CTX_HEADER_UPDATE( + ctx->hdr_add.hdr_addr, + ctx->hdr_add.hdr_addr_hi, hdr_addr); + if (!is_64) + ctx->hdr_add.hdr_addr_hi = 0; + ctx->rtp_params.tlv.type = IPA_PROC_CTX_TLV_TYPE_PROC_CMD; + ctx->rtp_params.tlv.length = 1; + IPA_GET_UCP_RTP_CMD(type); + ctx->rtp_params.tlv.value = type; + ctx->rtp_params.rtp_params.input_ip_version = + rtp_params->hdr_add_param.input_ip_version; + ctx->end.type = IPA_PROC_CTX_TLV_TYPE_END; + ctx->end.length = 0; + ctx->end.value = 0; + } else { + struct ipa_hw_hdr_proc_ctx_add_hdr_cmd_seq *ctx; + + ctx = (struct ipa_hw_hdr_proc_ctx_add_hdr_cmd_seq *) + (base + offset); + ctx->hdr_add.tlv.type = IPA_PROC_CTX_TLV_TYPE_HDR_ADD; + ctx->hdr_add.tlv.length = 2; + ctx->hdr_add.tlv.value = hdr_len; + hdr_addr = hdr_base_addr + offset_entry->offset; + IPAHAL_DBG("header address 0x%llx\n", + hdr_addr); + IPAHAL_CP_PROC_CTX_HEADER_UPDATE(ctx->hdr_add.hdr_addr, + ctx->hdr_add.hdr_addr_hi, hdr_addr); + if (!is_64) + ctx->hdr_add.hdr_addr_hi = 0; + ctx->cmd.type = IPA_PROC_CTX_TLV_TYPE_PROC_CMD; + ctx->cmd.length = 0; + switch (type) { + case IPA_HDR_PROC_ETHII_TO_ETHII: + ctx->cmd.value = IPA_HDR_UCP_ETHII_TO_ETHII; + break; + case IPA_HDR_PROC_ETHII_TO_802_3: + ctx->cmd.value = IPA_HDR_UCP_ETHII_TO_802_3; + break; + case IPA_HDR_PROC_802_3_TO_ETHII: + ctx->cmd.value = IPA_HDR_UCP_802_3_TO_ETHII; + break; + case IPA_HDR_PROC_802_3_TO_802_3: + ctx->cmd.value = IPA_HDR_UCP_802_3_TO_802_3; + break; + case IPA_HDR_PROC_SET_DSCP: + ctx->cmd.value = IPA_HDR_UCP_SET_DSCP; + break; + default: + IPAHAL_ERR("unknown ipa_hdr_proc_type %d", type); + WARN_ON(1); + return -EINVAL; + } + IPAHAL_DBG("command id %d\n", ctx->cmd.value); + ctx->end.type = IPA_PROC_CTX_TLV_TYPE_END; + ctx->end.length = 0; + ctx->end.value = 0; + } + + return 0; +} + +/* + * ipahal_get_proc_ctx_needed_len_v3() - calculates the needed length for + * addition of header processing context according to the type of processing + * context. + * @type: header processing context type (no processing context, + * IPA_HDR_PROC_ETHII_TO_ETHII etc.) + */ +static int ipahal_get_proc_ctx_needed_len_v3(enum ipa_hdr_proc_type type) +{ + int ret; + + switch (type) { + case IPA_HDR_PROC_NONE: + ret = sizeof(struct ipa_hw_hdr_proc_ctx_add_hdr_seq); + break; + case IPA_HDR_PROC_ETHII_TO_ETHII: + case IPA_HDR_PROC_ETHII_TO_802_3: + case IPA_HDR_PROC_802_3_TO_ETHII: + case IPA_HDR_PROC_802_3_TO_802_3: + ret = sizeof(struct ipa_hw_hdr_proc_ctx_add_hdr_cmd_seq); + break; + case IPA_HDR_PROC_L2TP_HEADER_ADD: + ret = sizeof(struct ipa_hw_hdr_proc_ctx_add_l2tp_hdr_cmd_seq); + break; + case IPA_HDR_PROC_L2TP_HEADER_REMOVE: + ret = + sizeof(struct ipa_hw_hdr_proc_ctx_remove_l2tp_hdr_cmd_seq); + break; + case IPA_HDR_PROC_L2TP_UDP_HEADER_ADD: + ret = sizeof(struct ipa_hw_hdr_proc_ctx_add_l2tp_hdr_cmd_seq); + break; + case IPA_HDR_PROC_L2TP_UDP_HEADER_REMOVE: + ret = + sizeof(struct ipa_hw_hdr_proc_ctx_remove_l2tp_hdr_cmd_seq); + break; + case IPA_HDR_PROC_ETHII_TO_ETHII_EX: + ret = sizeof(struct ipa_hw_hdr_proc_ctx_add_hdr_cmd_seq_ex); + break; + case IPA_HDR_PROC_EoGRE_HEADER_ADD: + ret = sizeof(struct ipa_hw_hdr_proc_ctx_add_eogre_hdr_cmd_seq); + break; + case IPA_HDR_PROC_EoGRE_HEADER_REMOVE: + ret = + sizeof(struct ipa_hw_hdr_proc_ctx_remove_eogre_hdr_cmd_seq); + break; + case IPA_HDR_PROC_RTP_METADATA_STREAM0: + case IPA_HDR_PROC_RTP_METADATA_STREAM1: + case IPA_HDR_PROC_RTP_METADATA_STREAM2: + case IPA_HDR_PROC_RTP_METADATA_STREAM3: + ret = + sizeof(struct ipa_hw_hdr_proc_ctx_rtp_hdr_cmd_seq); + break; + default: + /* invalid value to make sure failure */ + IPAHAL_ERR_RL("invalid ipa_hdr_proc_type %d\n", type); + ret = -1; + } + + return ret; +} + +/* + * struct ipahal_hdr_funcs - headers handling functions for specific IPA + * version + * @ipahal_cp_hdr_to_hw_buff - copy function for regular headers + */ +struct ipahal_hdr_funcs { + void (*ipahal_cp_hdr_to_hw_buff)(void *const base, u32 offset, + u8 *const hdr, u32 hdr_len); + + int (*ipahal_cp_proc_ctx_to_hw_buff)(enum ipa_hdr_proc_type type, + void *const base, u32 offset, u32 hdr_len, + u64 hdr_base_addr, + struct ipa_hdr_offset_entry *offset_entry, + struct ipa_l2tp_hdr_proc_ctx_params *l2tp_params, + struct ipa_eogre_hdr_proc_ctx_params *eogre_params, + struct ipa_eth_II_to_eth_II_ex_procparams + *generic_params, + struct ipa_rtp_hdr_proc_ctx_params *rtp_params, + bool is_64); + + int (*ipahal_get_proc_ctx_needed_len)(enum ipa_hdr_proc_type type); +}; + +static struct ipahal_hdr_funcs hdr_funcs; + +static void ipahal_hdr_init(enum ipa_hw_type ipa_hw_type) +{ + + IPAHAL_DBG("Entry - HW_TYPE=%d\n", ipa_hw_type); + + /* + * once there are changes in HW and need to use different case, insert + * new case for the new h/w. put the default always for the latest HW + * and make sure all previous supported versions have their cases. + */ + switch (ipa_hw_type) { + case IPA_HW_v3_0: + default: + hdr_funcs.ipahal_cp_hdr_to_hw_buff = + ipahal_cp_hdr_to_hw_buff_v3; + hdr_funcs.ipahal_cp_proc_ctx_to_hw_buff = + ipahal_cp_proc_ctx_to_hw_buff_v3; + hdr_funcs.ipahal_get_proc_ctx_needed_len = + ipahal_get_proc_ctx_needed_len_v3; + } + IPAHAL_DBG("Exit\n"); +} + +/* + * ipahal_cp_hdr_to_hw_buff() - copy header to hardware buffer according to + * base address and offset given. + * @base: dma base address + * @offset: offset from base address where the data will be copied + * @hdr: the header to be copied + * @hdr_len: the length of the header + */ +void ipahal_cp_hdr_to_hw_buff(void *base, u32 offset, u8 *const hdr, + u32 hdr_len) +{ + IPAHAL_DBG_LOW("Entry\n"); + IPAHAL_DBG("base %pK, offset %d, hdr %pK, hdr_len %d\n", base, + offset, hdr, hdr_len); + if (!base || !hdr) { + IPAHAL_ERR("failed on validating params\n"); + return; + } + + hdr_funcs.ipahal_cp_hdr_to_hw_buff(base, offset, hdr, hdr_len); + + IPAHAL_DBG_LOW("Exit\n"); +} + +/* + * ipahal_cp_proc_ctx_to_hw_buff() - copy processing context to + * base address and offset given. + * @type: type of header processing context + * @base: dma base address + * @offset: offset from base address where the data will be copied + * @hdr_len: the length of the header + * @hdr_base_addr: base address in table + * @offset_entry: offset from hdr_base_addr in table + * @l2tp_params: l2tp parameters + * @eogre_params: eogre parameters + * @generic_params: generic proc_ctx params + * @rtp_params: rtp proc_ctx params + * @is_64: Indicates whether header base address/dma base address is 64 bit. + */ +int ipahal_cp_proc_ctx_to_hw_buff(enum ipa_hdr_proc_type type, + void *const base, u32 offset, u32 hdr_len, + u64 hdr_base_addr, struct ipa_hdr_offset_entry *offset_entry, + struct ipa_l2tp_hdr_proc_ctx_params *l2tp_params, + struct ipa_eogre_hdr_proc_ctx_params *eogre_params, + struct ipa_eth_II_to_eth_II_ex_procparams *generic_params, + struct ipa_rtp_hdr_proc_ctx_params *rtp_params, + bool is_64) +{ + IPAHAL_DBG( + "type %d, base %pK, offset %d, hdr_len %d, hdr_base_addr %llu, offset_entry %pK, bool %d\n" + , type, base, offset, hdr_len, hdr_base_addr, offset_entry, is_64); + + if (!base || !offset_entry || !hdr_base_addr) { + IPAHAL_ERR( + "invalid input: hdr_len:%u hdr_base_addr:%llu offset_entry:%pK\n", + hdr_len, hdr_base_addr, offset_entry); + return -EINVAL; + } + + return hdr_funcs.ipahal_cp_proc_ctx_to_hw_buff(type, base, offset, + hdr_len, hdr_base_addr, offset_entry, l2tp_params, + eogre_params, generic_params, rtp_params, is_64); +} + +/* + * ipahal_get_proc_ctx_needed_len() - calculates the needed length for + * addition of header processing context according to the type of processing + * context + * @type: header processing context type (no processing context, + * IPA_HDR_PROC_ETHII_TO_ETHII etc.) + */ +int ipahal_get_proc_ctx_needed_len(enum ipa_hdr_proc_type type) +{ + int res; + + IPAHAL_DBG("entry\n"); + + res = hdr_funcs.ipahal_get_proc_ctx_needed_len(type); + + IPAHAL_DBG("Exit\n"); + + return res; +} + +int ipahal_init(enum ipa_hw_type ipa_hw_type, void __iomem *base, + u32 ipa_cfg_offset, struct device *ipa_pdev) +{ + int result; + + IPAHAL_DBG("Entry - IPA HW TYPE=%d base=%pK ipa_pdev=%pK\n", + ipa_hw_type, base, ipa_pdev); + + ipahal_ctx = kzalloc(sizeof(*ipahal_ctx), GFP_KERNEL); + if (!ipahal_ctx) { + IPAHAL_ERR("kzalloc err for ipahal_ctx\n"); + result = -ENOMEM; + goto bail_err_exit; + } + + if (ipa_hw_type < IPA_HW_v3_0) { + IPAHAL_ERR("ipahal supported on IPAv3 and later only\n"); + result = -EINVAL; + goto bail_free_ctx; + } + + if (ipa_hw_type >= IPA_HW_MAX) { + IPAHAL_ERR("invalid IPA HW type (%d)\n", ipa_hw_type); + result = -EINVAL; + goto bail_free_ctx; + } + + if (!base) { + IPAHAL_ERR("invalid memory io mapping addr\n"); + result = -EINVAL; + goto bail_free_ctx; + } + + if (!ipa_pdev) { + IPAHAL_ERR("invalid IPA platform device\n"); + result = -EINVAL; + goto bail_free_ctx; + } + + ipahal_ctx->hw_type = ipa_hw_type; + ipahal_ctx->base = base; + ipahal_ctx->ipa_cfg_offset = ipa_cfg_offset; + ipahal_ctx->ipa_pdev = ipa_pdev; + + if (ipahal_reg_init(ipa_hw_type)) { + IPAHAL_ERR("failed to init ipahal reg\n"); + result = -EFAULT; + goto bail_free_ctx; + } + + if (ipahal_imm_cmd_init(ipa_hw_type)) { + IPAHAL_ERR("failed to init ipahal imm cmd\n"); + result = -EFAULT; + goto bail_free_ctx; + } + + if (ipahal_pkt_status_init(ipa_hw_type)) { + IPAHAL_ERR("failed to init ipahal pkt status\n"); + result = -EFAULT; + goto bail_free_ctx; + } + + if (ipahal_qmap_init(ipa_hw_type)) { + IPAHAL_ERR("failed to init ipahal qmap\n"); + result = -EFAULT; + goto bail_free_ctx; + } + + ipahal_hdr_init(ipa_hw_type); + + if (ipahal_fltrt_init(ipa_hw_type)) { + IPAHAL_ERR("failed to init ipahal flt rt\n"); + result = -EFAULT; + goto bail_free_ctx; + } + + if (ipahal_hw_stats_init(ipa_hw_type)) { + IPAHAL_ERR("failed to init ipahal hw stats\n"); + result = -EFAULT; + goto bail_free_fltrt; + } + + if (ipahal_nat_init(ipa_hw_type)) { + IPAHAL_ERR("failed to init ipahal NAT\n"); + result = -EFAULT; + goto bail_free_fltrt; + } + + /* create an IPC buffer for the registers dump */ + ipahal_ctx->regdumpbuf = ipc_log_context_create(IPAHAL_IPC_LOG_PAGES, + "ipa_regs", MINIDUMP_MASK); + if (ipahal_ctx->regdumpbuf == NULL) + IPAHAL_ERR("failed to create IPA regdump log, continue...\n"); + + ipahal_debugfs_init(); + + return 0; + +bail_free_fltrt: + ipahal_fltrt_destroy(); +bail_free_ctx: + if (ipahal_ctx->regdumpbuf) + ipc_log_context_destroy(ipahal_ctx->regdumpbuf); + kfree(ipahal_ctx); + ipahal_ctx = NULL; +bail_err_exit: + return result; +} + +void ipahal_destroy(void) +{ + IPAHAL_DBG("Entry\n"); + ipahal_fltrt_destroy(); + ipahal_debugfs_remove(); + kfree(ipahal_ctx); + ipahal_ctx = NULL; +} + +void ipahal_free_dma_mem(struct ipa_mem_buffer *mem) +{ + if (likely(mem)) { + dma_free_coherent(ipahal_ctx->ipa_pdev, mem->size, mem->base, + mem->phys_base); + mem->size = 0; + mem->base = NULL; + mem->phys_base = 0; + } +} + +/* + * *************************************************************** + * + * To follow, a generalized qmap header manipulation API. + * + * The functions immediately following this comment are version + * specific qmap parsing functions. The referred to in the + * ipahal_qmap_parse_tbl below. + * + * *************************************************************** + */ +void ipa_qmap_hdr_parse_v4_5( + union qmap_hdr_u* qmap_hdr, + struct qmap_hdr_data* qmap_data_rslt ) +{ + qmap_data_rslt->cd = qmap_hdr->qmap5_0.cd; + qmap_data_rslt->qmap_next_hdr = qmap_hdr->qmap5_0.qmap_next_hdr; + qmap_data_rslt->pad = qmap_hdr->qmap5_0.pad; + qmap_data_rslt->mux_id = qmap_hdr->qmap5_0.mux_id; + qmap_data_rslt->packet_len_with_pad = qmap_hdr->qmap5_0.packet_len_with_pad; + + qmap_data_rslt->hdr_type = qmap_hdr->qmap5_0.hdr_type; + qmap_data_rslt->coal_next_hdr = qmap_hdr->qmap5_0.coal_next_hdr; + qmap_data_rslt->zero_checksum = qmap_hdr->qmap5_0.zero_checksum; +} + +void ipa_qmap_hdr_parse_v5_0( + union qmap_hdr_u* qmap_hdr, + struct qmap_hdr_data* qmap_data_rslt ) +{ + qmap_data_rslt->cd = qmap_hdr->qmap5_0.cd; + qmap_data_rslt->qmap_next_hdr = qmap_hdr->qmap5_0.qmap_next_hdr; + qmap_data_rslt->pad = qmap_hdr->qmap5_0.pad; + qmap_data_rslt->mux_id = qmap_hdr->qmap5_0.mux_id; + qmap_data_rslt->packet_len_with_pad = qmap_hdr->qmap5_0.packet_len_with_pad; + + qmap_data_rslt->hdr_type = qmap_hdr->qmap5_0.hdr_type; + qmap_data_rslt->coal_next_hdr = qmap_hdr->qmap5_0.coal_next_hdr; + qmap_data_rslt->ip_id_cfg = qmap_hdr->qmap5_0.ip_id_cfg; + qmap_data_rslt->zero_checksum = qmap_hdr->qmap5_0.zero_checksum; + qmap_data_rslt->additional_hdr_size = qmap_hdr->qmap5_0.additional_hdr_size; + qmap_data_rslt->segment_size = qmap_hdr->qmap5_0.segment_size; +} + +void ipa_qmap_hdr_parse_v5_5( + union qmap_hdr_u* qmap_hdr, + struct qmap_hdr_data* qmap_data_rslt ) +{ + qmap_data_rslt->cd = qmap_hdr->qmap5_5.cd; + qmap_data_rslt->qmap_next_hdr = qmap_hdr->qmap5_5.qmap_next_hdr; + qmap_data_rslt->pad = qmap_hdr->qmap5_5.pad; + qmap_data_rslt->mux_id = qmap_hdr->qmap5_5.mux_id; + qmap_data_rslt->packet_len_with_pad = ntohs(qmap_hdr->qmap5_5.packet_len_with_pad); + + qmap_data_rslt->hdr_type = qmap_hdr->qmap5_5.hdr_type; + qmap_data_rslt->coal_next_hdr = qmap_hdr->qmap5_5.coal_next_hdr; + qmap_data_rslt->chksum_valid = qmap_hdr->qmap5_5.chksum_valid; + qmap_data_rslt->num_nlos = qmap_hdr->qmap5_5.num_nlos; + qmap_data_rslt->inc_ip_id = qmap_hdr->qmap5_5.inc_ip_id; + qmap_data_rslt->rnd_ip_id = qmap_hdr->qmap5_5.rnd_ip_id; + qmap_data_rslt->close_value = qmap_hdr->qmap5_5.close_value; + qmap_data_rslt->close_type = qmap_hdr->qmap5_5.close_type; + qmap_data_rslt->vcid = qmap_hdr->qmap5_5.vcid; +} + +/* + * Structure used to describe a version specific qmap parsing table. + */ +struct ipahal_qmap_parse_s { + /* + * Function prototype for a version specific qmap parsing + * function. + */ + void (*parse)( + union qmap_hdr_u* qmap_hdr, + struct qmap_hdr_data* qmap_data_rslt ); +}; + +/* + * Table used to contain and drive version specific qmap parsing + * functions. + */ +static struct ipahal_qmap_parse_s ipahal_qmap_parse_tbl[IPA_HW_MAX] = { + /* IPAv4.5 */ + [IPA_HW_v4_5] = { + ipa_qmap_hdr_parse_v4_5 + }, + /* IPAv5.0 */ + [IPA_HW_v5_0] = { + ipa_qmap_hdr_parse_v5_0 + }, + /* IPAv5.5 */ + [IPA_HW_v5_5] = { + ipa_qmap_hdr_parse_v5_5 + }, +}; + +static int ipahal_qmap_init( + enum ipa_hw_type ipa_hw_type) +{ + struct ipahal_qmap_parse_s zero_obj; + int i; + + IPAHAL_DBG_LOW("Entry - HW_TYPE=%d\n", ipa_hw_type); + + if (ipa_hw_type < 0 || ipa_hw_type >= IPA_HW_MAX) { + IPAHAL_ERR("invalid IPA HW type (%d)\n", ipa_hw_type); + return -EINVAL; + } + + memset(&zero_obj, 0, sizeof(zero_obj)); + + for (i = IPA_HW_v4_5; i < (IPA_HW_MAX - 1); i++) { + + if (memcmp(&ipahal_qmap_parse_tbl[i+1], + &zero_obj, + sizeof(struct ipahal_qmap_parse_s)) == 0 ) { + memcpy( + &ipahal_qmap_parse_tbl[i+1], + &ipahal_qmap_parse_tbl[i], + sizeof(struct ipahal_qmap_parse_s)); + } else { + if (ipahal_qmap_parse_tbl[i+1].parse == 0) { + IPAHAL_ERR( + "QMAP parse table missing parse function ipa_ver=%d\n", + i+1); + WARN_ON(1); + } + } + } + + return 0; +} + +/* + * FUNCTION: ipahal_qmap_parse() + * + * The following Function to be called when version specific qmap parsing is + * required. + * + * ARGUMENTS: + * + * unparsed_qmap + * + * The QMAP header off of a freshly recieved data packet. As per + * the architecture documentation, the data contained herein will + * be in network order. + * + * qmap_data_rslt + * + * A location to store the parsed data from unparsed_qmap above. + */ +int ipahal_qmap_parse( + const void* unparsed_qmap, + struct qmap_hdr_data* qmap_data_rslt ) +{ + union qmap_hdr_u qmap_hdr; + + IPAHAL_DBG_LOW("Parse qmap/coal header\n"); + + if (!unparsed_qmap || !qmap_data_rslt) { + IPAHAL_ERR( + "Input Error: unparsed_qmap=%pK qmap_data_rslt=%pK\n", + unparsed_qmap, qmap_data_rslt); + return -EINVAL; + } + + if (ipahal_ctx->hw_type < IPA_HW_v4_5) { + IPAHAL_ERR( + "Unsupported qmap parse for IPA HW type (%d)\n", + ipahal_ctx->hw_type); + return -EINVAL; + } + + ipahal_qmap_ntoh(unparsed_qmap, &qmap_hdr); + + ipahal_qmap_parse_tbl[ipahal_ctx->hw_type].parse(&qmap_hdr, qmap_data_rslt); + + return 0; +} diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal.h new file mode 100644 index 0000000000..5a0bf6d041 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal.h @@ -0,0 +1,1139 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _IPAHAL_H_ +#define _IPAHAL_H_ + +#include "ipa_defs.h" +#include "ipa_common_i.h" + +/* + * Immediate command names + * + * NOTE:: Any change to this enum, need to change to ipahal_imm_cmd_name_to_str + * array as well. + */ +enum ipahal_imm_cmd_name { + IPA_IMM_CMD_IP_V4_FILTER_INIT, + IPA_IMM_CMD_IP_V6_FILTER_INIT, + IPA_IMM_CMD_IP_V4_NAT_INIT, + IPA_IMM_CMD_IP_V4_ROUTING_INIT, + IPA_IMM_CMD_IP_V6_ROUTING_INIT, + IPA_IMM_CMD_HDR_INIT_LOCAL, + IPA_IMM_CMD_HDR_INIT_SYSTEM, + IPA_IMM_CMD_REGISTER_WRITE, + IPA_IMM_CMD_REGISTER_READ, + IPA_IMM_CMD_NAT_DMA, + IPA_IMM_CMD_IP_PACKET_INIT, + IPA_IMM_CMD_DMA_SHARED_MEM, + IPA_IMM_CMD_IP_PACKET_TAG_STATUS, + IPA_IMM_CMD_DMA_TASK_32B_ADDR, + IPA_IMM_CMD_TABLE_DMA, + IPA_IMM_CMD_IP_V6_CT_INIT, + IPA_IMM_CMD_IP_PACKET_INIT_EX, + IPA_IMM_CMD_MAX, +}; + +/* Immediate commands abstracted structures */ + +/* + * struct ipahal_imm_cmd_ip_v4_filter_init - IP_V4_FILTER_INIT cmd payload + * Inits IPv4 filter block. + * @hash_rules_addr: Addr in sys mem where ipv4 hashable flt tbl starts + * @nhash_rules_addr: Addr in sys mem where ipv4 non-hashable flt tbl starts + * @hash_rules_size: Size in bytes of the hashable tbl to cpy to local mem + * @hash_local_addr: Addr in shared mem where ipv4 hashable flt tbl should + * be copied to + * @nhash_rules_size: Size in bytes of the non-hashable tbl to cpy to local mem + * @nhash_local_addr: Addr in shared mem where ipv4 non-hashable flt tbl should + * be copied to + */ +struct ipahal_imm_cmd_ip_v4_filter_init { + u64 hash_rules_addr; + u64 nhash_rules_addr; + u32 hash_rules_size; + u32 hash_local_addr; + u32 nhash_rules_size; + u32 nhash_local_addr; +}; + +/* + * struct ipahal_imm_cmd_ip_v6_filter_init - IP_V6_FILTER_INIT cmd payload + * Inits IPv6 filter block. + * @hash_rules_addr: Addr in sys mem where ipv6 hashable flt tbl starts + * @nhash_rules_addr: Addr in sys mem where ipv6 non-hashable flt tbl starts + * @hash_rules_size: Size in bytes of the hashable tbl to cpy to local mem + * @hash_local_addr: Addr in shared mem where ipv6 hashable flt tbl should + * be copied to + * @nhash_rules_size: Size in bytes of the non-hashable tbl to cpy to local mem + * @nhash_local_addr: Addr in shared mem where ipv6 non-hashable flt tbl should + * be copied to + */ +struct ipahal_imm_cmd_ip_v6_filter_init { + u64 hash_rules_addr; + u64 nhash_rules_addr; + u32 hash_rules_size; + u32 hash_local_addr; + u32 nhash_rules_size; + u32 nhash_local_addr; +}; + +/* + * struct ipahal_imm_cmd_nat_ipv6ct_init_common - NAT/IPv6CT table init command + * common part + * @base_table_addr: Address in sys/shared mem where base table start + * @expansion_table_addr: Address in sys/shared mem where expansion table + * starts. Entries that result in hash collision are located in this table. + * @base_table_addr_shared: base_table_addr in shared mem (if not, then sys) + * @expansion_table_addr_shared: expansion_rules_addr in + * shared mem (if not, then sys) + * @size_base_table: Num of entries in the base table + * @size_expansion_table: Num of entries in the expansion table + * @table_index: For future support of multiple tables + */ +struct ipahal_imm_cmd_nat_ipv6ct_init_common { + u64 base_table_addr; + u64 expansion_table_addr; + bool base_table_addr_shared; + bool expansion_table_addr_shared; + u16 size_base_table; + u16 size_expansion_table; + u8 table_index; +}; + +/* + * struct ipahal_imm_cmd_ip_v4_nat_init - IP_V4_NAT_INIT cmd payload + * Inits IPv4 NAT block. Initiate NAT table with it dimensions, location + * cache address and other related parameters. + * @table_init: table initialization parameters + * @index_table_addr: Addr in sys/shared mem where index table, which points + * to NAT table starts + * @index_table_expansion_addr: Addr in sys/shared mem where expansion index + * table starts + * @index_table_addr_shared: index_table_addr in shared mem (if not, then sys) + * @index_table_expansion_addr_shared: index_table_expansion_addr in + * shared mem (if not, then sys) + * @public_addr_info: Public IP addresses info suitable to the IPA H/W version + * IPA H/W >= 4.0 - PDN config table offset in SMEM + * IPA H/W < 4.0 - The public IP address + */ +struct ipahal_imm_cmd_ip_v4_nat_init { + struct ipahal_imm_cmd_nat_ipv6ct_init_common table_init; + u64 index_table_addr; + u64 index_table_expansion_addr; + bool index_table_addr_shared; + bool index_table_expansion_addr_shared; + u32 public_addr_info; +}; + +/* + * struct ipahal_imm_cmd_ip_v6_ct_init - IP_V6_CONN_TRACK_INIT cmd payload + * Inits IPv6CT block. Initiate IPv6CT table with it dimensions, location + * cache address and other related parameters. + * @table_init: table initialization parameters + */ +struct ipahal_imm_cmd_ip_v6_ct_init { + struct ipahal_imm_cmd_nat_ipv6ct_init_common table_init; +}; + +/* + * struct ipahal_imm_cmd_ip_v4_routing_init - IP_V4_ROUTING_INIT cmd payload + * Inits IPv4 routing table/structure - with the rules and other related params + * @hash_rules_addr: Addr in sys mem where ipv4 hashable rt tbl starts + * @nhash_rules_addr: Addr in sys mem where ipv4 non-hashable rt tbl starts + * @hash_rules_size: Size in bytes of the hashable tbl to cpy to local mem + * @hash_local_addr: Addr in shared mem where ipv4 hashable rt tbl should + * be copied to + * @nhash_rules_size: Size in bytes of the non-hashable tbl to cpy to local mem + * @nhash_local_addr: Addr in shared mem where ipv4 non-hashable rt tbl should + * be copied to + */ +struct ipahal_imm_cmd_ip_v4_routing_init { + u64 hash_rules_addr; + u64 nhash_rules_addr; + u32 hash_rules_size; + u32 hash_local_addr; + u32 nhash_rules_size; + u32 nhash_local_addr; +}; + +/* + * struct ipahal_imm_cmd_ip_v6_routing_init - IP_V6_ROUTING_INIT cmd payload + * Inits IPv6 routing table/structure - with the rules and other related params + * @hash_rules_addr: Addr in sys mem where ipv6 hashable rt tbl starts + * @nhash_rules_addr: Addr in sys mem where ipv6 non-hashable rt tbl starts + * @hash_rules_size: Size in bytes of the hashable tbl to cpy to local mem + * @hash_local_addr: Addr in shared mem where ipv6 hashable rt tbl should + * be copied to + * @nhash_rules_size: Size in bytes of the non-hashable tbl to cpy to local mem + * @nhash_local_addr: Addr in shared mem where ipv6 non-hashable rt tbl should + * be copied to + */ +struct ipahal_imm_cmd_ip_v6_routing_init { + u64 hash_rules_addr; + u64 nhash_rules_addr; + u32 hash_rules_size; + u32 hash_local_addr; + u32 nhash_rules_size; + u32 nhash_local_addr; +}; + +/* + * struct ipahal_imm_cmd_hdr_init_local - HDR_INIT_LOCAL cmd payload + * Inits hdr table within local mem with the hdrs and their length. + * @hdr_table_addr: Word address in sys mem where the table starts (SRC) + * @size_hdr_table: Size of the above (in bytes) + * @hdr_addr: header address in IPA sram (used as DST for memory copy) + * @rsvd: reserved + */ +struct ipahal_imm_cmd_hdr_init_local { + u64 hdr_table_addr; + u32 size_hdr_table; + u32 hdr_addr; +}; + +/* + * struct ipahal_imm_cmd_hdr_init_system - HDR_INIT_SYSTEM cmd payload + * Inits hdr table within sys mem with the hdrs and their length. + * @hdr_table_addr: Word address in system memory where the hdrs tbl starts. + */ +struct ipahal_imm_cmd_hdr_init_system { + u64 hdr_table_addr; +}; + +/* + * struct ipahal_imm_cmd_table_dma - TABLE_DMA cmd payload + * Perform DMA operation on NAT and IPV6 connection tracking related mem + * addresses. Copy data into different locations within IPv6CT and NAT + * associated tbls. (For add/remove NAT rules) + * @offset: offset in bytes from base addr to write 'data' to + * @data: data to be written + * @table_index: NAT tbl index. Defines the tbl on which to perform DMA op. + * @base_addr: Base addr to which the DMA operation should be performed. + */ +struct ipahal_imm_cmd_table_dma { + u32 offset; + u16 data; + u8 table_index; + u8 base_addr; +}; + +/* + * struct ipahal_imm_cmd_ip_packet_init - IP_PACKET_INIT cmd payload + * Configuration for specific IP pkt. Shall be called prior to an IP pkt + * data. Pkt will not go through IP pkt processing. + * @destination_pipe_index: Destination pipe index (in case routing + * is enabled, this field will overwrite the rt rule) + */ +struct ipahal_imm_cmd_ip_packet_init { + u32 destination_pipe_index; +}; + +/* + * struct ipahal_imm_cmd_ip_packet_init_ex - IP_PACKET_INIT_EX cmd payload + * @frag_disable: true - disabled. overrides IPA_ENDP_CONFIG_n:FRAG_OFFLOAD_EN + * @filter_disable: true - disabled, false - enabled + * @nat_disable: true - disabled, false - enabled + * @route_disable: true - disabled, false - enabled + * @hdr_removal_insertion_disable: true - disabled, false - enabled + * @cs_disable: true - disabled, false - enabled + * @quota_tethering_stats_disable: true - disabled, false - enabled + * fields @flt_rt_tbl_idx - @flt_retain_hdr are a logical software translation + * of ipa5_0_flt_rule_hw_hdr/ipa5_5_flt_rule_hw_hdr + * fields @rt_pipe_dest_idx - @rt_system are a logical software translation + * ipa5_0_rt_rule_hw_hdr/ipa5_5_flt_rule_hw_hdr + * @dpl_disable: true - disabled, false - enabled, valid from IPAv5_5. + * @flt_ext_hdr: true - flt ext_hdr enabled, false - disabled. Note all fields of + * ext header are valid in immediate command irrespective of this flag. + * fields @flt_ttl - @flt_qos_class are a logical software translation + * of ipa5_5_flt_rule_hw_hdr_ext. + * @rt_ext_hdr: true - rt ext_hdr enabled, false - disabled. Note all fields of + * ext header are valid in immediate command irrespective of this flag. + * fields @rt_ttl - @rt_skip_ingress are a logical software translation + * ipa5_5_rt_rule_hw_hdr_ext + */ +struct ipahal_imm_cmd_ip_packet_init_ex { + bool frag_disable; + bool filter_disable; + bool nat_disable; + bool route_disable; + bool hdr_removal_insertion_disable; + bool cs_disable; + bool quota_tethering_stats_disable; + u8 flt_rt_tbl_idx; + u8 flt_stats_cnt_idx; + u8 flt_priority; + bool flt_close_aggr_irq_mod; + u8 flt_action; + u8 flt_pdn_idx; + bool flt_set_metadata; + bool flt_retain_hdr; + u8 rt_pipe_dest_idx; + u8 rt_stats_cnt_idx; + u8 rt_priority; + bool rt_close_aggr_irq_mod; + u16 rt_hdr_offset; + bool rt_proc_ctx; + bool rt_retain_hdr; + bool rt_system; + bool dpl_disable; + bool flt_ext_hdr; + bool flt_ttl; + u8 flt_qos_class; + bool rt_ext_hdr; + bool rt_ttl; + u8 rt_qos_class; + bool rt_skip_ingress; +}; + +/* + * enum ipa_pipeline_clear_option - Values for pipeline clear waiting options + * @IPAHAL_HPS_CLEAR: Wait for HPS clear. All queues except high priority queue + * shall not be serviced until HPS is clear of packets or immediate commands. + * The high priority Rx queue / Q6ZIP group shall still be serviced normally. + * + * @IPAHAL_SRC_GRP_CLEAR: Wait for originating source group to be clear + * (for no packet contexts allocated to the originating source group). + * The source group / Rx queue shall not be serviced until all previously + * allocated packet contexts are released. All other source groups/queues shall + * be serviced normally. + * + * @IPAHAL_FULL_PIPELINE_CLEAR: Wait for full pipeline to be clear. + * All groups / Rx queues shall not be serviced until IPA pipeline is fully + * clear. This should be used for debug only. + */ +enum ipahal_pipeline_clear_option { + IPAHAL_HPS_CLEAR, + IPAHAL_SRC_GRP_CLEAR, + IPAHAL_FULL_PIPELINE_CLEAR +}; + +/* + * struct ipahal_imm_cmd_register_write - REGISTER_WRITE cmd payload + * Write value to register. Allows reg changes to be synced with data packet + * and other immediate commands. Can be used to access the sram + * @offset: offset from IPA base address - Lower 16bit of the IPA reg addr + * @value: value to write to register + * @value_mask: mask specifying which value bits to write to the register + * @skip_pipeline_clear: if to skip pipeline clear waiting (don't wait) + * @pipeline_clear_option: options for pipeline clear waiting + */ +struct ipahal_imm_cmd_register_write { + u32 offset; + u32 value; + u32 value_mask; + bool skip_pipeline_clear; + enum ipahal_pipeline_clear_option pipeline_clear_options; +}; + +/* + * struct ipahal_imm_cmd_register_read - REGISTER_READ cmd payload + * Read value from register. Allows reg changes to be synced with data packet + * and other immediate commands. Can be used to access the sram + * @offset: offset from IPA base address - Lower 16bit of the IPA reg addr + * @sys_addr: Address in system memory for storing register value + * @skip_pipeline_clear: if to skip pipeline clear waiting (don't wait) + * @pipeline_clear_option: options for pipeline clear waiting + */ +struct ipahal_imm_cmd_register_read { + u32 offset; + u32 sys_addr; + bool skip_pipeline_clear; + enum ipahal_pipeline_clear_option pipeline_clear_options; +}; + +/* + * struct ipahal_imm_cmd_dma_shared_mem - DMA_SHARED_MEM cmd payload + * Perform mem copy into or out of the SW area of IPA local mem + * @system_addr: Address in system memory + * @size: Size in bytes of data to copy. Expected size is up to 2K bytes + * @local_addr: Address in IPA local memory + * @clear_after_read: Clear local memory at the end of a read operation allows + * atomic read and clear if HPS is clear. Ignore for writes. + * @is_read: Read operation from local memory? If not, then write. + * @skip_pipeline_clear: if to skip pipeline clear waiting (don't wait) + * @pipeline_clear_option: options for pipeline clear waiting + */ +struct ipahal_imm_cmd_dma_shared_mem { + u64 system_addr; + u32 size; + u32 local_addr; + bool clear_after_read; + bool is_read; + bool skip_pipeline_clear; + enum ipahal_pipeline_clear_option pipeline_clear_options; +}; + +/* + * struct ipahal_imm_cmd_ip_packet_tag_status - IP_PACKET_TAG_STATUS cmd payload + * This cmd is used for to allow SW to track HW processing by setting a TAG + * value that is passed back to SW inside Packet Status information. + * TAG info will be provided as part of Packet Status info generated for + * the next pkt transferred over the pipe. + * This immediate command must be followed by a packet in the same transfer. + * @tag: Tag that is provided back to SW + */ +struct ipahal_imm_cmd_ip_packet_tag_status { + u64 tag; +}; + +/* + * struct ipahal_imm_cmd_dma_task_32b_addr - IPA_DMA_TASK_32B_ADDR cmd payload + * Used by clients using 32bit addresses. Used to perform DMA operation on + * multiple descriptors. + * The Opcode is dynamic, where it holds the number of buffer to process + * @cmplt: Complete flag: If true, IPA interrupt SW when the entire + * DMA related data was completely xfered to its destination. + * @eof: Enf Of Frame flag: If true, IPA assert the EOT to the + * dest client. This is used used for aggr sequence + * @flsh: Flush flag: If true pkt will go through the IPA blocks but + * will not be xfered to dest client but rather will be discarded + * @lock: Lock pipe flag: If true, IPA will stop processing descriptors + * from other EPs in the same src grp (RX queue) + * @unlock: Unlock pipe flag: If true, IPA will stop exclusively + * servicing current EP out of the src EPs of the grp (RX queue) + * @size1: Size of buffer1 data + * @addr1: Pointer to buffer1 data + * @packet_size: Total packet size. If a pkt send using multiple DMA_TASKs, + * only the first one needs to have this field set. It will be ignored + * in subsequent DMA_TASKs until the packet ends (EOT). First DMA_TASK + * must contain this field (2 or more buffers) or EOT. + */ +struct ipahal_imm_cmd_dma_task_32b_addr { + bool cmplt; + bool eof; + bool flsh; + bool lock; + bool unlock; + u32 size1; + u32 addr1; + u32 packet_size; +}; + +/* + * struct ipahal_imm_cmd_pyld - Immediate cmd payload information + * @len: length of the buffer + * @opcode: opcode of the immediate command + * @data: buffer contains the immediate command payload. Buffer goes + * back to back with this structure + */ +struct ipahal_imm_cmd_pyld { + u16 len; + u16 opcode; + u8 data[0]; +}; + + +/* Immediate command Function APIs */ + +/* + * ipahal_imm_cmd_name_str() - returns string that represent the imm cmd + * @cmd_name: [in] Immediate command name + */ +const char *ipahal_imm_cmd_name_str(enum ipahal_imm_cmd_name cmd_name); + +/* + * ipahal_construct_imm_cmd() - Construct immdiate command + * This function builds imm cmd bulk that can be be sent to IPA + * The command will be allocated dynamically. + * After done using it, call ipahal_destroy_imm_cmd() to release it + */ +struct ipahal_imm_cmd_pyld *ipahal_construct_imm_cmd( + enum ipahal_imm_cmd_name cmd, const void *params, bool is_atomic_ctx); + +/* + * ipahal_modify_imm_cmd() - Modify immdiate command in an existing buffer + * This function modifies an existing imm cmd buffer + * @cmd_name: [in] Immediate command name + * @cmd_data: [in] Constructed immediate command buffer data + * @params: [in] Structure with specific IMM params + * @params_mask: [in] Same structure, but the fields filled with 0, + * if they should not be changed, or any non-zero for fields to be updated + */ +int ipahal_modify_imm_cmd( + enum ipahal_imm_cmd_name cmd, + const void *cmd_data, + const void *params, + const void *params_mask); + +/* + * ipa_imm_cmd_modify_ip_packet_init_ex_dest_pipe() - + * Modify ip_packet_init_ex immdiate command pipe_dest_idx field + * This function modifies an existing imm cmd buffer + * @cmd_data: [in] Constructed immediate command buffer data + * @pipe_dest_idx: [in] destination pipe index to set + */ +void ipa_imm_cmd_modify_ip_packet_init_ex_dest_pipe( + const void *cmd_data, + u64 pipe_dest_idx); + +/* + * ipahal_construct_nop_imm_cmd() - Construct immediate comamnd for NO-Op + * Core driver may want functionality to inject NOP commands to IPA + * to ensure e.g., PIPLINE clear before someother operation. + * The functionality given by this function can be reached by + * ipahal_construct_imm_cmd(). This function is helper to the core driver + * to reach this NOP functionlity easily. + * @skip_pipline_clear: if to skip pipeline clear waiting (don't wait) + * @pipline_clr_opt: options for pipeline clear waiting + * @is_atomic_ctx: is called in atomic context or can sleep? + */ +struct ipahal_imm_cmd_pyld *ipahal_construct_nop_imm_cmd( + bool skip_pipline_clear, + enum ipahal_pipeline_clear_option pipline_clr_opt, + bool is_atomic_ctx); + +/* + * ipahal_destroy_imm_cmd() - Destroy/Release bulk that was built + * by the construction functions + */ +static inline void ipahal_destroy_imm_cmd(struct ipahal_imm_cmd_pyld *pyld) +{ + kfree(pyld); +} + + +/* IPA Status packet Structures and Function APIs */ + +/* + * enum ipahal_pkt_status_opcode - Packet Status Opcode + * @IPAHAL_STATUS_OPCODE_PACKET_2ND_PASS: Packet Status generated as part of + * IPA second processing pass for a packet (i.e. IPA XLAT processing for + * the translated packet). + */ +enum ipahal_pkt_status_opcode { + IPAHAL_PKT_STATUS_OPCODE_PACKET = 0, + IPAHAL_PKT_STATUS_OPCODE_NEW_FRAG_RULE, + IPAHAL_PKT_STATUS_OPCODE_DROPPED_PACKET, + IPAHAL_PKT_STATUS_OPCODE_SUSPENDED_PACKET, + IPAHAL_PKT_STATUS_OPCODE_LOG, + IPAHAL_PKT_STATUS_OPCODE_DCMP, + IPAHAL_PKT_STATUS_OPCODE_PACKET_2ND_PASS, +}; + +/* + * enum ipahal_pkt_status_exception - Packet Status exception type + * @IPAHAL_PKT_STATUS_EXCEPTION_PACKET_LENGTH: formerly IHL exception. + * + * Note: IPTYPE, PACKET_LENGTH and PACKET_THRESHOLD exceptions means that + * partial / no IP processing took place and corresponding Status Mask + * fields should be ignored. Flt and rt info is not valid. + * + * NOTE:: Any change to this enum, need to change to + * ipahal_pkt_status_exception_to_str array as well. + */ +enum ipahal_pkt_status_exception { + IPAHAL_PKT_STATUS_EXCEPTION_NONE = 0, + IPAHAL_PKT_STATUS_EXCEPTION_DEAGGR, + IPAHAL_PKT_STATUS_EXCEPTION_IPTYPE, + IPAHAL_PKT_STATUS_EXCEPTION_PACKET_LENGTH, + IPAHAL_PKT_STATUS_EXCEPTION_PACKET_THRESHOLD, + IPAHAL_PKT_STATUS_EXCEPTION_TTL, + IPAHAL_PKT_STATUS_EXCEPTION_FRAG_RULE_MISS, + IPAHAL_PKT_STATUS_EXCEPTION_SW_FILT, + /* + * NAT and IPv6CT have the same value at HW. + * NAT for IPv4 and IPv6CT for IPv6 exceptions + */ + IPAHAL_PKT_STATUS_EXCEPTION_NAT, + IPAHAL_PKT_STATUS_EXCEPTION_IPV6CT, + IPAHAL_PKT_STATUS_EXCEPTION_UCP, + IPAHAL_PKT_STATUS_EXCEPTION_INVALID_PIPE, + IPAHAL_PKT_STATUS_EXCEPTION_RQOS, + IPAHAL_PKT_STATUS_EXCEPTION_HDRI, + IPAHAL_PKT_STATUS_EXCEPTION_CSUM, + IPAHAL_PKT_STATUS_EXCEPTION_MAX, +}; + +/* + * enum ipahal_pkt_status_mask - Packet Status bitmask shift values of + * the contained flags. This bitmask indicates flags on the properties of + * the packet as well as IPA processing it may had. + * @FRAG_PROCESS: Frag block processing flag: Was pkt processed by frag block? + * Also means the frag info is valid unless exception or first frag + * @FILT_PROCESS: Flt block processing flag: Was pkt processed by flt block? + * Also means that flt info is valid. + * @NAT_PROCESS: NAT block processing flag: Was pkt processed by NAT block? + * Also means that NAT info is valid, unless exception. + * @ROUTE_PROCESS: Rt block processing flag: Was pkt processed by rt block? + * Also means that rt info is valid, unless exception. + * @TAG_VALID: Flag specifying if TAG and TAG info valid? + * @FRAGMENT: Flag specifying if pkt is IP fragment. + * @FIRST_FRAGMENT: Flag specifying if pkt is first fragment. In this case, frag + * info is invalid + * @V4: Flag specifying pkt is IPv4 or IPv6 + * @CKSUM_PROCESS: CSUM block processing flag: Was pkt processed by csum block? + * If so, csum trailer exists + * @AGGR_PROCESS: Aggr block processing flag: Was pkt processed by aggr block? + * @DEST_EOT: Flag specifying if EOT was asserted for the pkt on dest endp + * @DEAGGR_PROCESS: Deaggr block processing flag: Was pkt processed by deaggr + * block? + * @DEAGG_FIRST: Flag specifying if this is the first pkt in deaggr frame + * @SRC_EOT: Flag specifying if EOT asserted by src endp when sending the buffer + * @PREV_EOT: Flag specifying if EOT was sent just before the pkt as part of + * aggr hard-byte-limit + * @BYTE_LIMIT: Flag specifying if pkt is over a configured byte limit. + */ +enum ipahal_pkt_status_mask { + IPAHAL_PKT_STATUS_MASK_FRAG_PROCESS_SHFT = 0, + IPAHAL_PKT_STATUS_MASK_FILT_PROCESS_SHFT, + IPAHAL_PKT_STATUS_MASK_NAT_PROCESS_SHFT, + IPAHAL_PKT_STATUS_MASK_ROUTE_PROCESS_SHFT, + IPAHAL_PKT_STATUS_MASK_TAG_VALID_SHFT, + IPAHAL_PKT_STATUS_MASK_FRAGMENT_SHFT, + IPAHAL_PKT_STATUS_MASK_FIRST_FRAGMENT_SHFT, + IPAHAL_PKT_STATUS_MASK_V4_SHFT, + IPAHAL_PKT_STATUS_MASK_CKSUM_PROCESS_SHFT, + IPAHAL_PKT_STATUS_MASK_AGGR_PROCESS_SHFT, + IPAHAL_PKT_STATUS_MASK_DEST_EOT_SHFT, + IPAHAL_PKT_STATUS_MASK_OPENED_FRAME_SHFT = + IPAHAL_PKT_STATUS_MASK_DEST_EOT_SHFT, + IPAHAL_PKT_STATUS_MASK_DEAGGR_PROCESS_SHFT, + IPAHAL_PKT_STATUS_MASK_DEAGG_FIRST_SHFT, + IPAHAL_PKT_STATUS_MASK_SRC_EOT_SHFT, + IPAHAL_PKT_STATUS_MASK_PREV_EOT_SHFT, + IPAHAL_PKT_STATUS_MASK_RQOS_NAS_SHFT = + IPAHAL_PKT_STATUS_MASK_PREV_EOT_SHFT, + IPAHAL_PKT_STATUS_MASK_BYTE_LIMIT_SHFT, + IPAHAL_PKT_STATUS_MASK_RQOS_AS_SHFT = + IPAHAL_PKT_STATUS_MASK_BYTE_LIMIT_SHFT, +}; + +/* + * Returns boolean value representing a property of the a packet. + * @__flag_shft: The shift value of the flag of the status bitmask of + * @__status: Pointer to abstracrted status structure + * the needed property. See enum ipahal_pkt_status_mask + */ +#define IPAHAL_PKT_STATUS_MASK_FLAG_VAL(__flag_shft, __status) \ + (((__status)->status_mask) & ((u32)0x1<<(__flag_shft)) ? true : false) + +/* + * enum ipahal_pkt_status_nat_type - Type of NAT + */ +enum ipahal_pkt_status_nat_type { + IPAHAL_PKT_STATUS_NAT_NONE, + IPAHAL_PKT_STATUS_NAT_SRC, + IPAHAL_PKT_STATUS_NAT_DST, +}; + +/* + * struct ipahal_pkt_status - IPA status packet abstracted payload. + * This structure describes the status packet fields for the + * following statuses: IPA_STATUS_PACKET, IPA_STATUS_DROPPED_PACKET, + * IPA_STATUS_SUSPENDED_PACKET. + * Other statuses types has different status packet structure. + * @tag_info: S/W defined value provided via immediate command + * @status_opcode: The Type of the status (Opcode). + * @exception: The first exception that took place. + * In case of exception, src endp and pkt len are always valid. + * @status_mask: Bit mask for flags on several properties on the packet + * and processing it may passed at IPA. See enum ipahal_pkt_status_mask + * @pkt_len: Pkt pyld len including hdr and retained hdr if used. Does + * not include padding or checksum trailer len. + * @metadata: meta data value used by packet + * @flt_local: Filter table location flag: Does matching flt rule belongs to + * flt tbl that resides in lcl memory? (if not, then system mem) + * @flt_hash: Filter hash hit flag: Does matching flt rule was in hash tbl? + * @flt_global: Global filter rule flag: Does matching flt rule belongs to + * the global flt tbl? (if not, then the per endp tables) + * @flt_ret_hdr: Retain header in filter rule flag: Does matching flt rule + * specifies to retain header? + * Starting IPA4.5, this will be true only if packet has L2 header. + * @flt_miss: Filtering miss flag: Was their a filtering rule miss? + * In case of miss, all flt info to be ignored + * @rt_local: Route table location flag: Does matching rt rule belongs to + * rt tbl that resides in lcl memory? (if not, then system mem) + * @rt_hash: Route hash hit flag: Does matching rt rule was in hash tbl? + * @ucp: UC Processing flag + * @rt_miss: Routing miss flag: Was their a routing rule miss? + * @nat_hit: NAT hit flag: Was their NAT hit? + * @nat_type: Defines the type of the NAT operation: + * @time_of_day_ctr: running counter from IPA clock + * @hdr_local: Header table location flag: In header insertion, was the header + * taken from the table resides in local memory? (If no, then system mem) + * @frag_hit: Frag hit flag: Was their frag rule hit in H/W frag table? + * @flt_rule_id: The ID of the matching filter rule (if no miss). + * This info can be combined with endp_src_idx to locate the exact rule. + * @rt_rule_id: The ID of the matching rt rule. (if no miss). This info + * can be combined with rt_tbl_idx to locate the exact rule. + * @nat_entry_idx: Index of the NAT entry used of NAT processing + * @hdr_offset: Offset of used header in the header table + * @endp_src_idx: Source end point index. + * @endp_dest_idx: Destination end point index. + * Not valid in case of exception + * @rt_tbl_idx: Index of rt tbl that contains the rule on which was a match + * @seq_num: Per source endp unique packet sequence number + * @frag_rule: Frag rule index in H/W frag table in case of frag hit + * @frag_rule_idx: Frag rule index value. + * @tbl_idx: Table index valid or not. + * @src_ip_addr: Source packet IP address. + * @dest_ip_addr: Destination packet IP address. + * @protocol: Protocal number. + * @ip_id: IP packet IP ID number. + * @tlated_ip_addr: IP address. + * @ip_cksum_diff: IP packet checksum difference. + * @hdr_ret: l2 header retained flag, indicates whether l2 header is retained + * or not. + * @ll: low latency indication. + * @tsp: Traffic shaping policing flag, indicates traffic class info + * overwrites tag info. + * @ttl_dec: ttl update flag, indicates whether ttl is updated. + * @nat_exc_suppress: nat exception supress flag, indicates whether + * nat exception is suppressed. + * @ingress_tc: Ingress traffic class index. + * @egress_tc: Egress traffic class index. + * @pd: router disabled ingress policer. + */ +struct ipahal_pkt_status { + u64 tag_info; + enum ipahal_pkt_status_opcode status_opcode; + enum ipahal_pkt_status_exception exception; + u32 status_mask; + u32 pkt_len; + u32 metadata; + bool flt_local; + bool flt_hash; + bool flt_global; + bool flt_ret_hdr; + bool flt_miss; + bool rt_local; + bool rt_hash; + bool ucp; + bool rt_miss; + bool nat_hit; + enum ipahal_pkt_status_nat_type nat_type; + u32 time_of_day_ctr; + bool hdr_local; + bool frag_hit; + u16 flt_rule_id; + u16 rt_rule_id; + u16 nat_entry_idx; + u16 hdr_offset; + u8 endp_src_idx; + u8 endp_dest_idx; + u8 rt_tbl_idx; + u8 seq_num; + u8 frag_rule; + u8 frag_rule_idx; + bool tbl_idx; + u32 src_ip_addr; + u32 dest_ip_addr; + u8 protocol; + u16 ip_id; + u32 tlated_ip_addr; + u16 ip_cksum_diff; + bool hdr_ret; + bool ll; + bool tsp; + bool ttl_dec; + bool nat_exc_suppress; + u8 ingress_tc; + u8 egress_tc; + bool pd; +}; + +/* + * struct ipahal_pkt_status_thin - this struct is used to parse only + * a few fields from the status packet, needed for LAN optimization. + * @exception: The first exception that took place. + * @metadata: meta data value used by packet + * @endp_src_idx: Source end point index. + * @ucp: UC Processing flag + */ +struct ipahal_pkt_status_thin { + enum ipahal_pkt_status_exception exception; + u32 metadata; + u8 endp_src_idx; + bool ucp; +}; + +/* + * ipahal_pkt_status_get_size() - Get H/W size of packet status + */ +u32 ipahal_pkt_status_get_size(void); + +/* + * ipahal_pkt_status_parse() - Parse Packet Status payload to abstracted form + * @unparsed_status: Pointer to H/W format of the packet status as read from H/W + * @status: Pointer to pre-allocated buffer where the parsed info will be stored + */ +void ipahal_pkt_status_parse(const void *unparsed_status, + struct ipahal_pkt_status *status); + +/* + * ipahal_pkt_status_parse_thin() - Parse some of the packet status fields + * for specific usage in the LAN rx data path where parsing needs to be done + * but only for specific fields. + * @unparsed_status: Pointer to H/W format of the packet status as read from HW + * @status: Pointer to pre-allocated buffer where the parsed info will be + * stored + */ +void ipahal_pkt_status_parse_thin(const void *unparsed_status, + struct ipahal_pkt_status_thin *status); + +/* + * ipahal_pkt_status_exception_str() - returns string represents exception type + * @exception: [in] The exception type + */ +const char *ipahal_pkt_status_exception_str( + enum ipahal_pkt_status_exception exception); + +/* + * ipahal_cp_hdr_to_hw_buff() - copy header to hardware buffer according to + * base address and offset given. + * @base: dma base address + * @offset: offset from base address where the data will be copied + * @hdr: the header to be copied + * @hdr_len: the length of the header + */ +void ipahal_cp_hdr_to_hw_buff(void *base, u32 offset, u8 *hdr, u32 hdr_len); + +/* + * ipahal_cp_proc_ctx_to_hw_buff() - copy processing context to + * base address and offset given. + * @type: type of header processing context + * @base: dma base address + * @offset: offset from base address where the data will be copied + * @hdr_len: the length of the header + * @hdr_base_addr: base address in table + * @offset_entry: offset from hdr_base_addr in table + * @l2tp_params: l2tp parameters + * @eogre_params: eogre parameters + * @generic_params: generic proc_ctx params + * @rtp_params: rtp proc_ctx params + * @is_64: Indicates whether header base address/dma base address is 64 bit. + */ +int ipahal_cp_proc_ctx_to_hw_buff(enum ipa_hdr_proc_type type, + void *base, u32 offset, u32 hdr_len, + u64 hdr_base_addr, + struct ipa_hdr_offset_entry *offset_entry, + struct ipa_l2tp_hdr_proc_ctx_params *l2tp_params, + struct ipa_eogre_hdr_proc_ctx_params *eogre_params, + struct ipa_eth_II_to_eth_II_ex_procparams *generic_params, + struct ipa_rtp_hdr_proc_ctx_params *rtp_params, + bool is_64); + +/* + * ipahal_get_proc_ctx_needed_len() - calculates the needed length for addition + * of header processing context according to the type of processing context + * @type: header processing context type (no processing context, + * IPA_HDR_PROC_ETHII_TO_ETHII etc.) + */ +int ipahal_get_proc_ctx_needed_len(enum ipa_hdr_proc_type type); + +int ipahal_init(enum ipa_hw_type ipa_hw_type, void __iomem *base, + u32 ipa_cfg_offset, struct device *ipa_pdev); +void ipahal_destroy(void); +void ipahal_free_dma_mem(struct ipa_mem_buffer *mem); + +/* +* ipahal_test_ep_bit() - return true if a ep bit is set +*/ +bool ipahal_test_ep_bit(u32 reg_val, u32 ep_num); + +/* +* ipahal_get_ep_bit() - get ep bit set in the right offset +*/ +u32 ipahal_get_ep_bit(u32 ep_num); + +/* +* ipahal_get_ep_reg_idx() - get ep reg index according to ep num +*/ +u32 ipahal_get_ep_reg_idx(u32 ep_num); + +/* + * *************************************************************** + * + * To follow, a generalized qmap header manipulation API. + * + * *************************************************************** + */ +/** + * qmap_hdr_v4_5 - + * + * @cd - + * @qmap_next_hdr - + * @pad - + * @mux_id - + * @packet_len_with_pad - + * @hdr_type - + * @coal_next_hdr - + * @zero_checksum - + * + * The following bit layout is when the data are in host order. + * + * FIXME FINDME Need to be reordered properly to reflect network + * ordering as seen by little endian host (qmap_hdr_v5_5 + * below proplerly done). + */ +struct qmap_hdr_v4_5 { + /* + * 32 bits of qmap header to follow + */ + u64 cd: 1; + u64 qmap_next_hdr: 1; + u64 pad: 6; + u64 mux_id: 8; + u64 packet_len_with_pad: 16; + /* + * 32 bits of coalescing frame header to follow + */ + u64 hdr_type: 7; + u64 coal_next_hdr: 1; + u64 zero_checksum: 1; + u64 rsrvd1: 7; + u64 rsrvd2: 16; +} __packed; + +/** + * qmap_hdr_v5_0 - + * + * @cd - + * @qmap_next_hdr - + * @pad - + * @mux_id - + * @packet_len_with_pad - + * @hdr_type - + * @coal_next_hdr - + * @ip_id_cfg - + * @zero_checksum - + * @additional_hdr_size - + * @segment_size - + * + * The following bit layout is when the data are in host order. + * + * FIXME FINDME Need to be reordered properly to reflect network + * ordering as seen by little endian host (qmap_hdr_v5_5 + * below proplerly done). + */ +struct qmap_hdr_v5_0 { + /* + * 32 bits of qmap header to follow + */ + u64 cd: 1; + u64 qmap_next_hdr: 1; + u64 pad: 6; + u64 mux_id: 8; + u64 packet_len_with_pad: 16; + /* + * 32 bits of coalescing frame header to follow + */ + u64 hdr_type: 7; + u64 coal_next_hdr: 1; + u64 ip_id_cfg: 1; + u64 zero_checksum: 1; + u64 rsrvd: 1; + u64 additional_hdr_size: 5; + u64 segment_size: 16; +} __packed; + +/** + * qmap_hdr_v5_5 - + * + * @cd - + * @qmap_next_hdr - + * @pad - + * @mux_id - + * @packet_len_with_pad - + * @hdr_type - + * @coal_next_hdr - + * @chksum_valid - + * @num_nlos - + * @inc_ip_id - + * @rnd_ip_id - + * @close_value - + * @close_type - + * @vcid - + * + * NOTE: + * + * The layout below is different when compared against + * documentation, which shows the fields as they are in network byte + * order - and network byte order is how we receive the data from + * the IPA. To avoid using cycles converting from network to host + * order, we've defined the stucture below such that we can access + * the correct fields while the data are still in network order. + */ +struct qmap_hdr_v5_5 { + /* + * 32 bits of qmap header to follow + */ + u8 pad: 6; + u8 qmap_next_hdr: 1; + u8 cd: 1; + u8 mux_id; + u16 packet_len_with_pad; + /* + * 32 bits of coalescing frame header to follow + */ + u8 coal_next_hdr: 1; + u8 hdr_type: 7; + u8 rsrvd1: 2; + u8 rnd_ip_id: 1; + u8 inc_ip_id: 1; + u8 num_nlos: 3; + u8 chksum_valid: 1; + + u8 close_type: 4; + u8 close_value: 4; + u8 rsrvd2: 4; + u8 vcid: 4; +} __packed; + +/** + * qmap_hdr_u - + * + * The following is a union of all of the qmap versions above. + * + * NOTE WELL: REMEMBER to keep it in sync with the bit strucure + * definitions above. + */ +union qmap_hdr_u { + struct qmap_hdr_v4_5 qmap4_5; + struct qmap_hdr_v5_0 qmap5_0; + struct qmap_hdr_v5_5 qmap5_5; + u32 words[2]; /* these used to flip from ntoh and hton */ +} __packed; + +/** + * qmap_hdr_data - + * + * The following is an aggregation of the qmap header bit structures + * above. + * + * NOTE WELL: REMEMBER to keep it in sync with the bit structure + * definitions above. + */ +struct qmap_hdr_data { + /* + * Data from qmap header to follow + */ + u8 cd; + u8 qmap_next_hdr; + u8 pad; + u8 mux_id; + u16 packet_len_with_pad; + /* + * Data from coalescing frame header to follow + */ + u8 hdr_type; + u8 coal_next_hdr; + u8 ip_id_cfg; + u8 zero_checksum; + u8 additional_hdr_size; + u16 segment_size; + u8 chksum_valid; + u8 num_nlos; + u8 inc_ip_id; + u8 rnd_ip_id; + u8 close_value; + u8 close_type; + u8 vcid; +}; + +/** + * FUNCTION: ipahal_qmap_parse() + * + * The following function to be called when version specific qmap parsing is + * required. + * + * ARGUMENTS: + * + * unparsed_qmap + * + * The QMAP header off of a freshly recieved data packet. As per + * the architecture documentation, the data contained herein will + * be in network order. + * + * qmap_data_rslt + * + * A location to store the parsed data from unparsed_qmap above. + */ +int ipahal_qmap_parse( + const void* unparsed_qmap, + struct qmap_hdr_data* qmap_data_rslt); + + +/** + * FUNCTION: ipahal_qmap_ntoh() + * + * The following function will take a QMAP header, which you know is + * in network order, and convert it to host order. + * + * NOTE WELL: Once in host order, the data will align with the bit + * descriptions in the headers above. + * + * ARGUMENTS: + * + * src_data_from_packet + * + * The QMAP header off of a freshly recieved data packet. As per + * the architecture documentation, the data contained herein will + * be in network order. + * + * dst_result + * + * A location to where the original data will be copied, then + * converted to host order. + */ +static inline void ipahal_qmap_ntoh( + const void* src_data_from_packet, + union qmap_hdr_u* dst_result) +{ + /* + * Nothing to do, since we define the bit fields in the + * structure, such that we can access them correctly while + * keeping the data in network order... + */ + if (src_data_from_packet && dst_result) { + memcpy( + dst_result, + src_data_from_packet, + sizeof(union qmap_hdr_u)); + } +} + +/** + * FUNCTION: ipahal_qmap_hton() + * + * The following function will take QMAP data, that you've assembled + * in host otder (ie. via using the bit structures definitions above), + * and convert it to network order. + * + * This function is to be used for QMAP data destined for network + * transmission. + * + * ARGUMENTS: + * + * src_data_from_host + * + * QMAP data in host order. + * + * dst_result + * + * A location to where the host ordered data above will be copied, + * then converted to network order. + */ +static inline void ipahal_qmap_hton( + union qmap_hdr_u* src_data_from_host, + void* dst_result) +{ + if (src_data_from_host && dst_result) { + memcpy( + dst_result, + src_data_from_host, + sizeof(union qmap_hdr_u)); + /* + * Reusing variable below to do the host to network swap... + */ + src_data_from_host = (union qmap_hdr_u*) dst_result; + src_data_from_host->words[0] = htonl(src_data_from_host->words[0]); + src_data_from_host->words[1] = htonl(src_data_from_host->words[1]); + } +} + +#endif /* _IPAHAL_H_ */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_fltrt.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_fltrt.c new file mode 100644 index 0000000000..04bc9e3096 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_fltrt.c @@ -0,0 +1,5568 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ipa.h" +#include +#include +#include +#include "ipahal.h" +#include "ipahal_fltrt.h" +#include "ipahal_fltrt_i.h" +#include "ipahal_i.h" +#include "ipa_common_i.h" + +/* SRAM OFFSET for empty table */ +#define IPA_EMPTY_SRAM_OFFSET (0x1000) +#define IPA_MAC_FLT_BITS (IPA_FLT_MAC_DST_ADDR_ETHER_II | \ + IPA_FLT_MAC_SRC_ADDR_ETHER_II | IPA_FLT_MAC_DST_ADDR_802_3 | \ + IPA_FLT_MAC_SRC_ADDR_802_3 | IPA_FLT_MAC_DST_ADDR_802_1Q | \ + IPA_FLT_MAC_SRC_ADDR_802_1Q) + +static u64 ipa_fltrt_create_flt_bitmap(u64 ep_bitmap) +{ + /* At IPA3, there global configuration is possible but not used */ + return (ep_bitmap << 1) & ~0x1; +} + +static u64 ipa_fltrt_create_flt_bitmap_v5_0(u64 ep_bitmap) +{ + /* At IPA5, ep_bitmap is all 64 bits bit map */ + return ep_bitmap; +} + +static u64 ipa_fltrt_create_tbl_addr(bool is_sys, u64 addr) +{ + if (is_sys) { + if (addr & IPA3_0_HW_TBL_SYSADDR_ALIGNMENT) { + IPAHAL_ERR( + "sys addr is not aligned accordingly addr=0x%pad\n", + &addr); + ipa_assert(); + return 0; + } + } else { + if (addr & IPA3_0_HW_TBL_LCLADDR_ALIGNMENT) { + IPAHAL_ERR("addr/ofst isn't lcl addr aligned %llu\n", + addr); + ipa_assert(); + return 0; + } + /* + * for local tables (at sram) offsets is used as tables + * addresses. offset need to be in 8B units + * (local address aligned) and left shifted to its place. + * Local bit need to be enabled. + */ + addr /= IPA3_0_HW_TBL_LCLADDR_ALIGNMENT + 1; + addr *= IPA3_0_HW_TBL_ADDR_MASK + 1; + addr += 1; + } + + return addr; +} + +static void ipa_fltrt_parse_tbl_addr(u64 hwaddr, u64 *addr, bool *is_sys) +{ + IPAHAL_DBG_LOW("Parsing hwaddr 0x%llx\n", hwaddr); + + *is_sys = !(hwaddr & 0x1); + hwaddr &= (~0ULL - 1); + if (hwaddr & IPA3_0_HW_TBL_SYSADDR_ALIGNMENT) { + IPAHAL_ERR( + "sys addr is not aligned accordingly addr=0x%pad\n", + &hwaddr); + ipa_assert(); + return; + } + + if (!*is_sys) { + hwaddr /= IPA3_0_HW_TBL_ADDR_MASK + 1; + hwaddr *= IPA3_0_HW_TBL_LCLADDR_ALIGNMENT + 1; + } + + *addr = hwaddr; +} + +/* Update these tables of the number of equations changes */ +static const int ipa3_0_ofst_meq32[] = { IPA_OFFSET_MEQ32_0, + IPA_OFFSET_MEQ32_1}; +static const int ipa3_0_ofst_meq128[] = { IPA_OFFSET_MEQ128_0, + IPA_OFFSET_MEQ128_1}; +static const int ipa3_0_ihl_ofst_rng16[] = { IPA_IHL_OFFSET_RANGE16_0, + IPA_IHL_OFFSET_RANGE16_1}; +static const int ipa3_0_ihl_ofst_meq32[] = { IPA_IHL_OFFSET_MEQ32_0, + IPA_IHL_OFFSET_MEQ32_1}; + +static int ipa_fltrt_generate_hw_rule_bdy(enum ipa_ip_type ipt, + const struct ipa_rule_attrib *attrib, u8 **buf, u16 *en_rule); +static int ipa_fltrt_generate_hw_rule_bdy_5_5(enum ipa_ip_type ipt, + const struct ipa_rule_attrib *attrib, u8 **buf, u16 *en_rule, bool ext_hdr); +static int ipa_fltrt_generate_hw_rule_bdy_from_eq( + const struct ipa_ipfltri_rule_eq *attrib, u8 **buf); +static int ipa_fltrt_generate_hw_rule_bdy_from_eq_5_5( + const struct ipa_ipfltri_rule_eq *attrib, u8 **buf, bool ext_hdr); +static int ipa_flt_generate_eq_ip4(enum ipa_ip_type ip, + const struct ipa_rule_attrib *attrib, + struct ipa_ipfltri_rule_eq *eq_atrb); +static int ipa_flt_generate_eq_ip6(enum ipa_ip_type ip, + const struct ipa_rule_attrib *attrib, + struct ipa_ipfltri_rule_eq *eq_atrb); +static int ipa_flt_generate_eq(enum ipa_ip_type ipt, + const struct ipa_rule_attrib *attrib, + struct ipa_ipfltri_rule_eq *eq_atrb); +static int ipa_rt_parse_hw_rule(u8 *addr, + struct ipahal_rt_rule_entry *rule); +static int ipa_rt_parse_hw_rule_ipav4_5(u8 *addr, + struct ipahal_rt_rule_entry *rule); +static int ipa_rt_parse_hw_rule_ipav5_0(u8 *addr, + struct ipahal_rt_rule_entry *rule); +static int ipa_rt_parse_hw_rule_ipav5_5(u8 *addr, + struct ipahal_rt_rule_entry *rule); +static int ipa_flt_parse_hw_rule(u8 *addr, + struct ipahal_flt_rule_entry *rule); +static int ipa_flt_parse_hw_rule_ipav4(u8 *addr, + struct ipahal_flt_rule_entry *rule); +static int ipa_flt_parse_hw_rule_ipav4_5(u8 *addr, + struct ipahal_flt_rule_entry *rule); +static int ipa_flt_parse_hw_rule_ipav5_0(u8 *addr, + struct ipahal_flt_rule_entry *rule); + static int ipa_flt_parse_hw_rule_ipav5_5(u8 *addr, + struct ipahal_flt_rule_entry *rule); + +#define IPA_IS_RAN_OUT_OF_EQ(__eq_array, __eq_index) \ + (ARRAY_SIZE(__eq_array) <= (__eq_index)) + +#define IPA_GET_RULE_EQ_BIT_PTRN(__eq) \ + (BIT(ipahal_fltrt_objs[ipahal_ctx->hw_type].eq_bitfield[(__eq)])) + +#define IPA_IS_RULE_EQ_VALID(__eq) \ + (ipahal_fltrt_objs[ipahal_ctx->hw_type].eq_bitfield[(__eq)] != 0xFF) + +/* + * ipa_fltrt_rule_generation_err_check() - check basic validity on the rule + * attribs before starting building it + * checks if not not using ipv4 attribs on ipv6 and vice-versa + * @ip: IP address type + * @attrib: IPA rule attribute + * + * Return: 0 on success, -EPERM on failure + */ +static int ipa_fltrt_rule_generation_err_check( + enum ipa_ip_type ipt, const struct ipa_rule_attrib *attrib) +{ + if (ipt == IPA_IP_v4) { + if (attrib->attrib_mask & IPA_FLT_NEXT_HDR || + attrib->attrib_mask & IPA_FLT_TC || + attrib->attrib_mask & IPA_FLT_FLOW_LABEL) { + IPAHAL_ERR_RL("v6 attrib's specified for v4 rule\n"); + return -EPERM; + } + } else if (ipt == IPA_IP_v6) { + if (attrib->attrib_mask & IPA_FLT_TOS || + attrib->attrib_mask & IPA_FLT_PROTOCOL) { + IPAHAL_ERR_RL("v4 attrib's specified for v6 rule\n"); + return -EPERM; + } + } else { + IPAHAL_ERR_RL("unsupported ip %d\n", ipt); + return -EPERM; + } + + return 0; +} + +static int ipa_rt_gen_hw_rule(struct ipahal_rt_rule_gen_params *params, + u32 *hw_len, u8 *buf) +{ + struct ipa3_0_rt_rule_hw_hdr *rule_hdr; + u8 *start; + u16 en_rule = 0; + + start = buf; + rule_hdr = (struct ipa3_0_rt_rule_hw_hdr *)buf; + + ipa_assert_on(params->dst_pipe_idx & ~0x1F); + rule_hdr->u.hdr.pipe_dest_idx = params->dst_pipe_idx; + switch (params->hdr_type) { + case IPAHAL_RT_RULE_HDR_PROC_CTX: + rule_hdr->u.hdr.system = !params->hdr_lcl; + rule_hdr->u.hdr.proc_ctx = 1; + ipa_assert_on(params->hdr_ofst & 31); + rule_hdr->u.hdr.hdr_offset = (params->hdr_ofst) >> 5; + break; + case IPAHAL_RT_RULE_HDR_RAW: + rule_hdr->u.hdr.system = !params->hdr_lcl; + rule_hdr->u.hdr.proc_ctx = 0; + ipa_assert_on(params->hdr_ofst & 3); + rule_hdr->u.hdr.hdr_offset = (params->hdr_ofst) >> 2; + break; + case IPAHAL_RT_RULE_HDR_NONE: + rule_hdr->u.hdr.system = !params->hdr_lcl; + rule_hdr->u.hdr.proc_ctx = 0; + rule_hdr->u.hdr.hdr_offset = 0; + break; + default: + IPAHAL_ERR("Invalid HDR type %d\n", params->hdr_type); + WARN_ON_RATELIMIT_IPA(1); + return -EINVAL; + } + + ipa_assert_on(params->priority & ~0x3FF); + rule_hdr->u.hdr.priority = params->priority; + rule_hdr->u.hdr.retain_hdr = params->rule->retain_hdr ? 0x1 : 0x0; + ipa_assert_on(params->id & ~((1 << IPA3_0_RULE_ID_BIT_LEN) - 1)); + ipa_assert_on(params->id == ((1 << IPA3_0_RULE_ID_BIT_LEN) - 1)); + rule_hdr->u.hdr.rule_id = params->id; + + buf += sizeof(struct ipa3_0_rt_rule_hw_hdr); + + if (ipa_fltrt_generate_hw_rule_bdy(params->ipt, ¶ms->rule->attrib, + &buf, &en_rule)) { + IPAHAL_ERR("fail to generate hw rule\n"); + return -EPERM; + } + rule_hdr->u.hdr.en_rule = en_rule; + + IPAHAL_DBG_LOW("en_rule 0x%x\n", en_rule); + ipa_write_64(rule_hdr->u.word, (u8 *)rule_hdr); + + if (*hw_len == 0) { + *hw_len = buf - start; + } else if (*hw_len != (buf - start)) { + IPAHAL_ERR("hw_len differs b/w passed=0x%x calc=%td\n", + *hw_len, (buf - start)); + return -EPERM; + } + + return 0; +} + +static int ipa_rt_gen_hw_rule_ipav4_5(struct ipahal_rt_rule_gen_params *params, + u32 *hw_len, u8 *buf) +{ + struct ipa4_5_rt_rule_hw_hdr *rule_hdr; + u8 *start; + u16 en_rule = 0; + + start = buf; + rule_hdr = (struct ipa4_5_rt_rule_hw_hdr *)buf; + + ipa_assert_on(params->dst_pipe_idx & ~0x1F); + rule_hdr->u.hdr.pipe_dest_idx = params->dst_pipe_idx; + switch (params->hdr_type) { + case IPAHAL_RT_RULE_HDR_PROC_CTX: + rule_hdr->u.hdr.system = !params->hdr_lcl; + rule_hdr->u.hdr.proc_ctx = 1; + ipa_assert_on(params->hdr_ofst & 31); + rule_hdr->u.hdr.hdr_offset = (params->hdr_ofst) >> 5; + break; + case IPAHAL_RT_RULE_HDR_RAW: + rule_hdr->u.hdr.system = !params->hdr_lcl; + rule_hdr->u.hdr.proc_ctx = 0; + ipa_assert_on(params->hdr_ofst & 3); + rule_hdr->u.hdr.hdr_offset = (params->hdr_ofst) >> 2; + break; + case IPAHAL_RT_RULE_HDR_NONE: + rule_hdr->u.hdr.system = !params->hdr_lcl; + rule_hdr->u.hdr.proc_ctx = 0; + rule_hdr->u.hdr.hdr_offset = 0; + break; + default: + IPAHAL_ERR("Invalid HDR type %d\n", params->hdr_type); + WARN_ON_RATELIMIT_IPA(1); + return -EINVAL; + } + + ipa_assert_on(params->priority & ~0x3FF); + rule_hdr->u.hdr.priority = params->priority; + rule_hdr->u.hdr.retain_hdr = params->rule->retain_hdr ? 0x1 : 0x0; + ipa_assert_on(params->id & ~((1 << IPA3_0_RULE_ID_BIT_LEN) - 1)); + ipa_assert_on(params->id == ((1 << IPA3_0_RULE_ID_BIT_LEN) - 1)); + rule_hdr->u.hdr.rule_id = params->id; + rule_hdr->u.hdr.stats_cnt_idx_lsb = params->cnt_idx & 0x3F; + rule_hdr->u.hdr.stats_cnt_idx_msb = (params->cnt_idx & 0xC0) >> 6; + + buf += sizeof(struct ipa4_5_rt_rule_hw_hdr); + + if (ipa_fltrt_generate_hw_rule_bdy(params->ipt, ¶ms->rule->attrib, + &buf, &en_rule)) { + IPAHAL_ERR("fail to generate hw rule\n"); + return -EPERM; + } + rule_hdr->u.hdr.en_rule = en_rule; + + IPAHAL_DBG_LOW("en_rule 0x%x\n", en_rule); + ipa_write_64(rule_hdr->u.word, (u8 *)rule_hdr); + + if (*hw_len == 0) { + *hw_len = buf - start; + } else if (*hw_len != (buf - start)) { + IPAHAL_ERR("hw_len differs b/w passed=0x%x calc=%td\n", + *hw_len, (buf - start)); + return -EPERM; + } + + return 0; +} + +static int ipa_rt_gen_hw_rule_ipav5_0(struct ipahal_rt_rule_gen_params *params, + u32 *hw_len, u8 *buf) +{ + struct ipa5_0_rt_rule_hw_hdr *rule_hdr; + u8 *start; + u16 en_rule = 0; + + start = buf; + rule_hdr = (struct ipa5_0_rt_rule_hw_hdr *)buf; + + ipa_assert_on(params->dst_pipe_idx & ~0xFF); + rule_hdr->u.hdr.pipe_dest_idx = params->dst_pipe_idx; + switch (params->hdr_type) { + case IPAHAL_RT_RULE_HDR_PROC_CTX: + rule_hdr->u.hdr.system = !params->hdr_lcl; + rule_hdr->u.hdr.proc_ctx = 1; + ipa_assert_on(params->hdr_ofst & 31); + rule_hdr->u.hdr.hdr_offset = (params->hdr_ofst) >> 5; + break; + case IPAHAL_RT_RULE_HDR_RAW: + rule_hdr->u.hdr.system = !params->hdr_lcl; + rule_hdr->u.hdr.proc_ctx = 0; + ipa_assert_on(params->hdr_ofst & 3); + rule_hdr->u.hdr.hdr_offset = (params->hdr_ofst) >> 2; + break; + case IPAHAL_RT_RULE_HDR_NONE: + rule_hdr->u.hdr.system = !params->hdr_lcl; + rule_hdr->u.hdr.proc_ctx = 0; + rule_hdr->u.hdr.hdr_offset = 0; + break; + default: + IPAHAL_ERR("Invalid HDR type %d\n", params->hdr_type); + WARN_ON_RATELIMIT_IPA(1); + return -EINVAL; + } + + ipa_assert_on(params->priority & ~0xFF); + rule_hdr->u.hdr.priority = params->priority; + rule_hdr->u.hdr.retain_hdr = params->rule->retain_hdr ? 0x1 : 0x0; + ipa_assert_on(params->id & ~((1 << IPA3_0_RULE_ID_BIT_LEN) - 1)); + ipa_assert_on(params->id == ((1 << IPA3_0_RULE_ID_BIT_LEN) - 1)); + rule_hdr->u.hdr.rule_id = params->id; + rule_hdr->u.hdr.stats_cnt_idx = params->cnt_idx; + rule_hdr->u.hdr.close_aggr_irq_mod = + params->rule->close_aggr_irq_mod ? 0x1 : 0x0; + + buf += sizeof(struct ipa5_0_rt_rule_hw_hdr); + + if (ipa_fltrt_generate_hw_rule_bdy(params->ipt, ¶ms->rule->attrib, + &buf, &en_rule)) { + IPAHAL_ERR("fail to generate hw rule\n"); + return -EPERM; + } + rule_hdr->u.hdr.en_rule = en_rule; + + IPAHAL_DBG_LOW("en_rule 0x%x\n", en_rule); + ipa_write_64(rule_hdr->u.word, (u8 *)rule_hdr); + + if (*hw_len == 0) { + *hw_len = buf - start; + } else if (*hw_len != (buf - start)) { + IPAHAL_ERR("hw_len differs b/w passed=0x%x calc=%td\n", + *hw_len, (buf - start)); + return -EPERM; + } + + return 0; +} + +static int ipa_rt_gen_hw_rule_ipav5_5(struct ipahal_rt_rule_gen_params *params, + u32 *hw_len, u8 *buf) +{ + struct ipa5_5_rt_rule_hw_hdr *rule_hdr; + struct ipa5_5_rt_rule_hw_hdr_ext *ext_hdr; + u8 *start; + u16 en_rule = 0; + + start = buf; + rule_hdr = (struct ipa5_5_rt_rule_hw_hdr *)buf; + + ipa_assert_on(params->dst_pipe_idx & ~0xFF); + rule_hdr->u.hdr.pipe_dest_idx = params->dst_pipe_idx; + switch (params->hdr_type) { + case IPAHAL_RT_RULE_HDR_PROC_CTX: + rule_hdr->u.hdr.system = !params->hdr_lcl; + rule_hdr->u.hdr.proc_ctx = 1; + ipa_assert_on(params->hdr_ofst & 31); + rule_hdr->u.hdr.hdr_offset = (params->hdr_ofst) >> 5; + break; + case IPAHAL_RT_RULE_HDR_RAW: + rule_hdr->u.hdr.system = !params->hdr_lcl; + rule_hdr->u.hdr.proc_ctx = 0; + ipa_assert_on(params->hdr_ofst & 3); + rule_hdr->u.hdr.hdr_offset = (params->hdr_ofst) >> 2; + break; + case IPAHAL_RT_RULE_HDR_NONE: + rule_hdr->u.hdr.system = !params->hdr_lcl; + rule_hdr->u.hdr.proc_ctx = 0; + rule_hdr->u.hdr.hdr_offset = 0; + break; + default: + IPAHAL_ERR("Invalid HDR type %d\n", params->hdr_type); + WARN_ON_RATELIMIT_IPA(1); + return -EINVAL; + } + + ipa_assert_on(params->priority & ~0xFF); + rule_hdr->u.hdr.priority = params->priority; + rule_hdr->u.hdr.retain_hdr = params->rule->retain_hdr ? 0x1 : 0x0; + ipa_assert_on(params->id & ~((1 << IPA3_0_RULE_ID_BIT_LEN) - 1)); + ipa_assert_on(params->id == ((1 << IPA3_0_RULE_ID_BIT_LEN) - 1)); + rule_hdr->u.hdr.rule_id = params->id; + rule_hdr->u.hdr.stats_cnt_idx = params->cnt_idx; + rule_hdr->u.hdr.close_aggr_irq_mod = + params->rule->close_aggr_irq_mod ? 0x1 : 0x0; + + buf += sizeof(struct ipa5_5_rt_rule_hw_hdr); + + if (params->rule->ttl_update || params->rule->qos_class || + params->rule->skip_ingress) { + ext_hdr = (struct ipa5_5_rt_rule_hw_hdr_ext *)buf; + rule_hdr->u.hdr.ext_hdr = 1; + ext_hdr->u.hdr.ttl = params->rule->ttl_update ? 0x1 : 0x0; + ext_hdr->u.hdr.qos_class = params->rule->qos_class; + ext_hdr->u.hdr.skip_ingress = params->rule->skip_ingress ? 0x1 : 0x0; + buf += sizeof(struct ipa5_5_rt_rule_hw_hdr_ext); + } else { + rule_hdr->u.hdr.ext_hdr = 0; + } + + if (ipa_fltrt_generate_hw_rule_bdy_5_5(params->ipt, ¶ms->rule->attrib, + &buf, &en_rule, rule_hdr->u.hdr.ext_hdr)) { + IPAHAL_ERR("fail to generate hw rule\n"); + return -EPERM; + } + rule_hdr->u.hdr.en_rule = en_rule; + + IPAHAL_DBG_LOW("en_rule 0x%x\n", en_rule); + ipa_write_64(rule_hdr->u.word, (u8 *)rule_hdr); + + if (*hw_len == 0) { + *hw_len = buf - start; + } else if (*hw_len != (buf - start)) { + IPAHAL_ERR("hw_len differs b/w passed=0x%x calc=%td\n", + *hw_len, (buf - start)); + return -EPERM; + } + + return 0; +} + +static int ipa_flt_gen_hw_rule(struct ipahal_flt_rule_gen_params *params, + u32 *hw_len, u8 *buf) +{ + struct ipa3_0_flt_rule_hw_hdr *rule_hdr; + u8 *start; + u16 en_rule = 0; + + start = buf; + rule_hdr = (struct ipa3_0_flt_rule_hw_hdr *)buf; + + switch (params->rule->action) { + case IPA_PASS_TO_ROUTING: + rule_hdr->u.hdr.action = 0x0; + break; + case IPA_PASS_TO_SRC_NAT: + rule_hdr->u.hdr.action = 0x1; + break; + case IPA_PASS_TO_DST_NAT: + rule_hdr->u.hdr.action = 0x2; + break; + case IPA_PASS_TO_EXCEPTION: + rule_hdr->u.hdr.action = 0x3; + break; + default: + IPAHAL_ERR_RL("Invalid Rule Action %d\n", params->rule->action); + WARN_ON_RATELIMIT_IPA(1); + return -EINVAL; + } + ipa_assert_on(params->rt_tbl_idx & ~0x1F); + rule_hdr->u.hdr.rt_tbl_idx = params->rt_tbl_idx; + rule_hdr->u.hdr.retain_hdr = params->rule->retain_hdr ? 0x1 : 0x0; + rule_hdr->u.hdr.rsvd1 = 0; + rule_hdr->u.hdr.rsvd2 = 0; + rule_hdr->u.hdr.rsvd3 = 0; + + ipa_assert_on(params->priority & ~0x3FF); + rule_hdr->u.hdr.priority = params->priority; + ipa_assert_on(params->id & ~((1 << IPA3_0_RULE_ID_BIT_LEN) - 1)); + ipa_assert_on(params->id == ((1 << IPA3_0_RULE_ID_BIT_LEN) - 1)); + rule_hdr->u.hdr.rule_id = params->id; + + buf += sizeof(struct ipa3_0_flt_rule_hw_hdr); + + if (params->rule->eq_attrib_type) { + if (ipa_fltrt_generate_hw_rule_bdy_from_eq( + ¶ms->rule->eq_attrib, &buf)) { + IPAHAL_ERR_RL("fail to generate hw rule from eq\n"); + return -EPERM; + } + en_rule = params->rule->eq_attrib.rule_eq_bitmap; + } else { + if (ipa_fltrt_generate_hw_rule_bdy(params->ipt, + ¶ms->rule->attrib, &buf, &en_rule)) { + IPAHAL_ERR_RL("fail to generate hw rule\n"); + return -EPERM; + } + } + rule_hdr->u.hdr.en_rule = en_rule; + + IPAHAL_DBG_LOW("en_rule=0x%x, action=%d, rt_idx=%d, retain_hdr=%d\n", + en_rule, + rule_hdr->u.hdr.action, + rule_hdr->u.hdr.rt_tbl_idx, + rule_hdr->u.hdr.retain_hdr); + IPAHAL_DBG_LOW("priority=%d, rule_id=%d\n", + rule_hdr->u.hdr.priority, + rule_hdr->u.hdr.rule_id); + + ipa_write_64(rule_hdr->u.word, (u8 *)rule_hdr); + + if (*hw_len == 0) { + *hw_len = buf - start; + } else if (*hw_len != (buf - start)) { + IPAHAL_ERR_RL("hw_len differs b/w passed=0x%x calc=%td\n", + *hw_len, (buf - start)); + return -EPERM; + } + + return 0; +} + +static int ipa_flt_gen_hw_rule_ipav4(struct ipahal_flt_rule_gen_params *params, + u32 *hw_len, u8 *buf) +{ + struct ipa4_0_flt_rule_hw_hdr *rule_hdr; + u8 *start; + u16 en_rule = 0; + + start = buf; + rule_hdr = (struct ipa4_0_flt_rule_hw_hdr *)buf; + + switch (params->rule->action) { + case IPA_PASS_TO_ROUTING: + rule_hdr->u.hdr.action = 0x0; + break; + case IPA_PASS_TO_SRC_NAT: + rule_hdr->u.hdr.action = 0x1; + break; + case IPA_PASS_TO_DST_NAT: + rule_hdr->u.hdr.action = 0x2; + break; + case IPA_PASS_TO_EXCEPTION: + rule_hdr->u.hdr.action = 0x3; + break; + default: + IPAHAL_ERR("Invalid Rule Action %d\n", params->rule->action); + WARN_ON_RATELIMIT_IPA(1); + return -EINVAL; + } + + ipa_assert_on(params->rt_tbl_idx & ~0x1F); + rule_hdr->u.hdr.rt_tbl_idx = params->rt_tbl_idx; + rule_hdr->u.hdr.retain_hdr = params->rule->retain_hdr ? 0x1 : 0x0; + + ipa_assert_on(params->rule->pdn_idx & ~0xF); + rule_hdr->u.hdr.pdn_idx = params->rule->pdn_idx; + rule_hdr->u.hdr.set_metadata = params->rule->set_metadata; + rule_hdr->u.hdr.rsvd2 = 0; + rule_hdr->u.hdr.rsvd3 = 0; + + ipa_assert_on(params->priority & ~0x3FF); + rule_hdr->u.hdr.priority = params->priority; + ipa_assert_on(params->id & ~((1 << IPA3_0_RULE_ID_BIT_LEN) - 1)); + ipa_assert_on(params->id == ((1 << IPA3_0_RULE_ID_BIT_LEN) - 1)); + rule_hdr->u.hdr.rule_id = params->id; + + buf += sizeof(struct ipa4_0_flt_rule_hw_hdr); + + if (params->rule->eq_attrib_type) { + if (ipa_fltrt_generate_hw_rule_bdy_from_eq( + ¶ms->rule->eq_attrib, &buf)) { + IPAHAL_ERR("fail to generate hw rule from eq\n"); + return -EPERM; + } + en_rule = params->rule->eq_attrib.rule_eq_bitmap; + } else { + if (ipa_fltrt_generate_hw_rule_bdy(params->ipt, + ¶ms->rule->attrib, &buf, &en_rule)) { + IPAHAL_ERR("fail to generate hw rule\n"); + return -EPERM; + } + } + rule_hdr->u.hdr.en_rule = en_rule; + + IPAHAL_DBG_LOW("en_rule=0x%x, action=%d, rt_idx=%d, retain_hdr=%d\n", + en_rule, + rule_hdr->u.hdr.action, + rule_hdr->u.hdr.rt_tbl_idx, + rule_hdr->u.hdr.retain_hdr); + IPAHAL_DBG_LOW("priority=%d, rule_id=%d, pdn=%d, set_metadata=%d\n", + rule_hdr->u.hdr.priority, + rule_hdr->u.hdr.rule_id, + rule_hdr->u.hdr.pdn_idx, + rule_hdr->u.hdr.set_metadata); + + ipa_write_64(rule_hdr->u.word, (u8 *)rule_hdr); + + if (*hw_len == 0) { + *hw_len = buf - start; + } else if (*hw_len != (buf - start)) { + IPAHAL_ERR("hw_len differs b/w passed=0x%x calc=%td\n", + *hw_len, (buf - start)); + return -EPERM; + } + + return 0; +} + +static int ipa_flt_gen_hw_rule_ipav4_5( + struct ipahal_flt_rule_gen_params *params, + u32 *hw_len, u8 *buf) +{ + struct ipa4_5_flt_rule_hw_hdr *rule_hdr; + u8 *start; + u16 en_rule = 0; + + start = buf; + rule_hdr = (struct ipa4_5_flt_rule_hw_hdr *)buf; + + switch (params->rule->action) { + case IPA_PASS_TO_ROUTING: + rule_hdr->u.hdr.action = 0x0; + break; + case IPA_PASS_TO_SRC_NAT: + rule_hdr->u.hdr.action = 0x1; + break; + case IPA_PASS_TO_DST_NAT: + rule_hdr->u.hdr.action = 0x2; + break; + case IPA_PASS_TO_EXCEPTION: + rule_hdr->u.hdr.action = 0x3; + break; + default: + IPAHAL_ERR("Invalid Rule Action %d\n", params->rule->action); + WARN_ON_RATELIMIT_IPA(1); + return -EINVAL; + } + + ipa_assert_on(params->rt_tbl_idx & ~0x1F); + rule_hdr->u.hdr.rt_tbl_idx = params->rt_tbl_idx; + rule_hdr->u.hdr.retain_hdr = params->rule->retain_hdr ? 0x1 : 0x0; + + ipa_assert_on(params->rule->pdn_idx & ~0xF); + rule_hdr->u.hdr.pdn_idx = params->rule->pdn_idx; + rule_hdr->u.hdr.set_metadata = params->rule->set_metadata; + rule_hdr->u.hdr.rsvd2 = 0; + + ipa_assert_on(params->priority & ~0x3FF); + rule_hdr->u.hdr.priority = params->priority; + ipa_assert_on(params->id & ~((1 << IPA3_0_RULE_ID_BIT_LEN) - 1)); + ipa_assert_on(params->id == ((1 << IPA3_0_RULE_ID_BIT_LEN) - 1)); + rule_hdr->u.hdr.rule_id = params->id; + rule_hdr->u.hdr.stats_cnt_idx_lsb = params->cnt_idx & 0x3F; + rule_hdr->u.hdr.stats_cnt_idx_msb = (params->cnt_idx & 0xC0) >> 6; + + buf += sizeof(struct ipa4_5_flt_rule_hw_hdr); + + if (params->rule->eq_attrib_type) { + if (ipa_fltrt_generate_hw_rule_bdy_from_eq( + ¶ms->rule->eq_attrib, &buf)) { + IPAHAL_ERR("fail to generate hw rule from eq\n"); + return -EPERM; + } + en_rule = params->rule->eq_attrib.rule_eq_bitmap; + } else { + if (ipa_fltrt_generate_hw_rule_bdy(params->ipt, + ¶ms->rule->attrib, &buf, &en_rule)) { + IPAHAL_ERR("fail to generate hw rule\n"); + return -EPERM; + } + } + rule_hdr->u.hdr.en_rule = en_rule; + + IPAHAL_DBG_LOW("en_rule=0x%x, action=%d, rt_idx=%d, retain_hdr=%d\n", + en_rule, + rule_hdr->u.hdr.action, + rule_hdr->u.hdr.rt_tbl_idx, + rule_hdr->u.hdr.retain_hdr); + IPAHAL_DBG_LOW("priority=%d, rule_id=%d, pdn=%d, set_metadata=%d\n", + rule_hdr->u.hdr.priority, + rule_hdr->u.hdr.rule_id, + rule_hdr->u.hdr.pdn_idx, + rule_hdr->u.hdr.set_metadata); + + ipa_write_64(rule_hdr->u.word, (u8 *)rule_hdr); + + if (*hw_len == 0) { + *hw_len = buf - start; + } else if (*hw_len != (buf - start)) { + IPAHAL_ERR("hw_len differs b/w passed=0x%x calc=%td\n", + *hw_len, (buf - start)); + return -EPERM; + } + + return 0; +} + +static int ipa_flt_gen_hw_rule_ipav5_0( + struct ipahal_flt_rule_gen_params *params, + u32 *hw_len, u8 *buf) +{ + struct ipa5_0_flt_rule_hw_hdr *rule_hdr; + u8 *start; + u16 en_rule = 0; + + start = buf; + rule_hdr = (struct ipa5_0_flt_rule_hw_hdr *)buf; + + switch (params->rule->action) { + case IPA_PASS_TO_ROUTING: + rule_hdr->u.hdr.action = 0x0; + break; + case IPA_PASS_TO_SRC_NAT: + rule_hdr->u.hdr.action = 0x1; + break; + case IPA_PASS_TO_DST_NAT: + rule_hdr->u.hdr.action = 0x2; + break; + case IPA_PASS_TO_EXCEPTION: + rule_hdr->u.hdr.action = 0x3; + break; + default: + IPAHAL_ERR_RL("Invalid Rule Action %d\n", params->rule->action); + WARN_ON_RATELIMIT_IPA(1); + return -EINVAL; + } + + if (params->rt_tbl_idx & ~0xFF) { + IPAHAL_ERR_RL("Invalid RT table idx 0x%X\n", + params->rt_tbl_idx); + WARN_ON_RATELIMIT_IPA(1); + return -EINVAL; + } + rule_hdr->u.hdr.rt_tbl_idx = params->rt_tbl_idx; + rule_hdr->u.hdr.retain_hdr = params->rule->retain_hdr ? 0x1 : 0x0; + + if (params->rule->pdn_idx & ~0xF) { + IPAHAL_ERR_RL("Invalid PDN idx 0x%X\n", params->rule->pdn_idx); + WARN_ON_RATELIMIT_IPA(1); + return -EINVAL; + } + rule_hdr->u.hdr.pdn_idx = params->rule->pdn_idx; + rule_hdr->u.hdr.set_metadata = params->rule->set_metadata ? 0x1 : 0x0; + rule_hdr->u.hdr.rsvd1 = 0; + rule_hdr->u.hdr.rsvd2 = 0; + + if (params->priority & ~0xFF) { + IPAHAL_ERR_RL("Invalid priority 0x%X\n", params->priority); + WARN_ON_RATELIMIT_IPA(1); + return -EINVAL; + } + rule_hdr->u.hdr.priority = params->priority; + if ((params->id & ~((1 << IPA3_0_RULE_ID_BIT_LEN) - 1)) || + (params->id == ((1 << IPA3_0_RULE_ID_BIT_LEN) - 1))) { + IPAHAL_ERR_RL("Invalid id 0x%X\n", params->id); + WARN_ON_RATELIMIT_IPA(1); + return -EINVAL; + } + rule_hdr->u.hdr.rule_id = params->id; + rule_hdr->u.hdr.stats_cnt_idx = params->cnt_idx; + rule_hdr->u.hdr.close_aggr_irq_mod = + params->rule->close_aggr_irq_mod ? 0x1 : 0x0; + + buf += sizeof(struct ipa5_0_flt_rule_hw_hdr); + + if (params->rule->eq_attrib_type) { + if (ipa_fltrt_generate_hw_rule_bdy_from_eq( + ¶ms->rule->eq_attrib, &buf)) { + IPAHAL_ERR("fail to generate hw rule from eq\n"); + return -EPERM; + } + en_rule = params->rule->eq_attrib.rule_eq_bitmap; + } else { + if (ipa_fltrt_generate_hw_rule_bdy(params->ipt, + ¶ms->rule->attrib, &buf, &en_rule)) { + IPAHAL_ERR("fail to generate hw rule\n"); + return -EPERM; + } + } + rule_hdr->u.hdr.en_rule = en_rule; + + IPAHAL_DBG_LOW("en_rule=0x%x, action=%d, rt_idx=%d, retain_hdr=%d\n", + en_rule, + rule_hdr->u.hdr.action, + rule_hdr->u.hdr.rt_tbl_idx, + rule_hdr->u.hdr.retain_hdr); + IPAHAL_DBG_LOW("priority=%d, rule_id=%d, pdn=%d, set_metadata=%d\n", + rule_hdr->u.hdr.priority, + rule_hdr->u.hdr.rule_id, + rule_hdr->u.hdr.pdn_idx, + rule_hdr->u.hdr.set_metadata); + + ipa_write_64(rule_hdr->u.word, (u8 *)rule_hdr); + + if (*hw_len == 0) { + *hw_len = buf - start; + } else if (*hw_len != (buf - start)) { + IPAHAL_ERR("hw_len differs b/w passed=0x%x calc=%td\n", + *hw_len, (buf - start)); + return -EPERM; + } + + return 0; +} + +static int ipa_flt_gen_hw_rule_ipav5_5( + struct ipahal_flt_rule_gen_params *params, + u32 *hw_len, u8 *buf) +{ + struct ipa5_5_flt_rule_hw_hdr *rule_hdr; + struct ipa5_5_flt_rule_hw_hdr_ext *ext_hdr; + u8 *start; + u16 en_rule = 0; + + start = buf; + rule_hdr = (struct ipa5_5_flt_rule_hw_hdr *)buf; + + switch (params->rule->action) { + case IPA_PASS_TO_ROUTING: + rule_hdr->u.hdr.action = 0x0; + break; + case IPA_PASS_TO_SRC_NAT: + rule_hdr->u.hdr.action = 0x1; + break; + case IPA_PASS_TO_DST_NAT: + rule_hdr->u.hdr.action = 0x2; + break; + case IPA_PASS_TO_EXCEPTION: + rule_hdr->u.hdr.action = 0x3; + break; + default: + IPAHAL_ERR_RL("Invalid Rule Action %d\n", params->rule->action); + WARN_ON_RATELIMIT_IPA(1); + return -EINVAL; + } + + if (params->rt_tbl_idx & ~0xFF) { + IPAHAL_ERR_RL("Invalid RT table idx 0x%X\n", + params->rt_tbl_idx); + WARN_ON_RATELIMIT_IPA(1); + return -EINVAL; + } + rule_hdr->u.hdr.rt_tbl_idx = params->rt_tbl_idx; + rule_hdr->u.hdr.retain_hdr = params->rule->retain_hdr ? 0x1 : 0x0; + + if (params->rule->pdn_idx & ~0xF) { + IPAHAL_ERR_RL("Invalid PDN idx 0x%X\n", params->rule->pdn_idx); + WARN_ON_RATELIMIT_IPA(1); + return -EINVAL; + } + rule_hdr->u.hdr.pdn_idx = params->rule->pdn_idx; + rule_hdr->u.hdr.set_metadata = params->rule->set_metadata ? 0x1 : 0x0; + rule_hdr->u.hdr.rsvd = 0; + + if (params->priority & ~0xFF) { + IPAHAL_ERR_RL("Invalid priority 0x%X\n", params->priority); + WARN_ON_RATELIMIT_IPA(1); + return -EINVAL; + } + rule_hdr->u.hdr.priority = params->priority; + if ((params->id & ~((1 << IPA3_0_RULE_ID_BIT_LEN) - 1)) || + (params->id == ((1 << IPA3_0_RULE_ID_BIT_LEN) - 1))) { + IPAHAL_ERR_RL("Invalid id 0x%X\n", params->id); + WARN_ON_RATELIMIT_IPA(1); + return -EINVAL; + } + rule_hdr->u.hdr.rule_id = params->id; + rule_hdr->u.hdr.stats_cnt_idx = params->cnt_idx; + rule_hdr->u.hdr.close_aggr_irq_mod = + params->rule->close_aggr_irq_mod ? 0x1 : 0x0; + + buf += sizeof(struct ipa5_5_flt_rule_hw_hdr); + + if (params->rule->ttl_update || params->rule->qos_class) { + ext_hdr = (struct ipa5_5_flt_rule_hw_hdr_ext *)buf; + rule_hdr->u.hdr.ext_hdr = 1; + ext_hdr->u.hdr.ttl = params->rule->ttl_update ? 0x1 : 0x0; + ext_hdr->u.hdr.qos_class = params->rule->qos_class; + buf += sizeof(struct ipa5_5_flt_rule_hw_hdr_ext); + } else { + rule_hdr->u.hdr.ext_hdr = 0; + } + + if (params->rule->eq_attrib_type) { + if (ipa_fltrt_generate_hw_rule_bdy_from_eq_5_5( + ¶ms->rule->eq_attrib, &buf, rule_hdr->u.hdr.ext_hdr)) { + IPAHAL_ERR("fail to generate hw rule from eq\n"); + return -EPERM; + } + en_rule = params->rule->eq_attrib.rule_eq_bitmap; + } else { + if (ipa_fltrt_generate_hw_rule_bdy_5_5(params->ipt, + ¶ms->rule->attrib, &buf, &en_rule, rule_hdr->u.hdr.ext_hdr)) { + IPAHAL_ERR("fail to generate hw rule\n"); + return -EPERM; + } + } + rule_hdr->u.hdr.en_rule = en_rule; + + IPAHAL_DBG_LOW("en_rule=0x%x, action=%d, rt_idx=%d, retain_hdr=%d\n", + en_rule, + rule_hdr->u.hdr.action, + rule_hdr->u.hdr.rt_tbl_idx, + rule_hdr->u.hdr.retain_hdr); + IPAHAL_DBG_LOW("priority=%d, rule_id=%d, pdn=%d, set_metadata=%d\n", + rule_hdr->u.hdr.priority, + rule_hdr->u.hdr.rule_id, + rule_hdr->u.hdr.pdn_idx, + rule_hdr->u.hdr.set_metadata); + + ipa_write_64(rule_hdr->u.word, (u8 *)rule_hdr); + + if (*hw_len == 0) { + *hw_len = buf - start; + } else if (*hw_len != (buf - start)) { + IPAHAL_ERR("hw_len differs b/w passed=0x%x calc=%td\n", + *hw_len, (buf - start)); + return -EPERM; + } + + return 0; +} + + +/* +* struct ipahal_fltrt_obj - Flt/Rt H/W information for specific IPA version +* @support_hash: Is hashable tables supported +* @tbl_width: Width of table in bytes +* @sysaddr_alignment: System table address alignment +* @lcladdr_alignment: Local table offset alignment +* @blk_sz_alignment: Rules block size alignment +* @rule_start_alignment: Rule start address alignment +* @tbl_hdr_width: Width of the header structure in bytes +* @tbl_addr_mask: Masking for Table address +* @rule_max_prio: Max possible priority of a rule +* @rule_min_prio: Min possible priority of a rule +* @low_rule_id: Low value of Rule ID that can be used +* @rule_id_bit_len: Rule is high (MSB) bit len +* @rule_buf_size: Max size rule may utilize. +* @write_val_to_hdr: Write address or offset to header entry +* @create_flt_bitmap: Create bitmap in H/W format using given bitmap +* @create_tbl_addr: Given raw table address, create H/W formated one +* @parse_tbl_addr: Parse the given H/W address (hdr format) +* @rt_generate_hw_rule: Generate RT rule in H/W format +* @flt_generate_hw_rule: Generate FLT rule in H/W format +* @flt_generate_eq: Generate flt equation attributes from rule attributes +* @rt_parse_hw_rule: Parse rt rule read from H/W +* @flt_parse_hw_rule: Parse flt rule read from H/W +* @eq_bitfield: Array of the bit fields of the support equations. +* 0xFF means the equation is not supported +* @prefetech_buf_size: Prefetch buf size; +*/ +struct ipahal_fltrt_obj { + bool support_hash; + u32 tbl_width; + u32 sysaddr_alignment; + u32 lcladdr_alignment; + u32 blk_sz_alignment; + u32 rule_start_alignment; + u32 tbl_hdr_width; + u32 tbl_addr_mask; + int rule_max_prio; + int rule_min_prio; + u32 low_rule_id; + u32 rule_id_bit_len; + u32 rule_buf_size; + u8* (*write_val_to_hdr)(u64 val, u8 *hdr); + u64(*create_flt_bitmap)(u64 ep_bitmap); + u64(*create_tbl_addr)(bool is_sys, u64 addr); + void(*parse_tbl_addr)(u64 hwaddr, u64 *addr, bool *is_sys); + int(*rt_generate_hw_rule)(struct ipahal_rt_rule_gen_params *params, + u32 *hw_len, u8 *buf); + int(*flt_generate_hw_rule)(struct ipahal_flt_rule_gen_params *params, + u32 *hw_len, u8 *buf); + int(*flt_generate_eq)(enum ipa_ip_type ipt, + const struct ipa_rule_attrib *attrib, + struct ipa_ipfltri_rule_eq *eq_atrb); + int(*rt_parse_hw_rule)(u8 *addr, struct ipahal_rt_rule_entry *rule); + int(*flt_parse_hw_rule)(u8 *addr, struct ipahal_flt_rule_entry *rule); + u8 eq_bitfield[IPA_EQ_MAX]; + u32 prefetech_buf_size; +}; + +/* + * This array contains the FLT/RT info for IPAv3 and later. + * All the information on IPAv3 are statically defined below. + * If information is missing regarding on some IPA version, + * the init function will fill it with the information from the previous + * IPA version. + * Information is considered missing if all of the fields are 0. + */ +static struct ipahal_fltrt_obj ipahal_fltrt_objs[IPA_HW_MAX] = { + /* IPAv3 */ + [IPA_HW_v3_0] = { + true, + IPA3_0_HW_TBL_WIDTH, + IPA3_0_HW_TBL_SYSADDR_ALIGNMENT, + IPA3_0_HW_TBL_LCLADDR_ALIGNMENT, + IPA3_0_HW_TBL_BLK_SIZE_ALIGNMENT, + IPA3_0_HW_RULE_START_ALIGNMENT, + IPA3_0_HW_TBL_HDR_WIDTH, + IPA3_0_HW_TBL_ADDR_MASK, + IPA3_0_RULE_MAX_PRIORITY, + IPA3_0_RULE_MIN_PRIORITY, + IPA3_0_LOW_RULE_ID, + IPA3_0_RULE_ID_BIT_LEN, + IPA3_0_HW_RULE_BUF_SIZE, + ipa_write_64, + ipa_fltrt_create_flt_bitmap, + ipa_fltrt_create_tbl_addr, + ipa_fltrt_parse_tbl_addr, + ipa_rt_gen_hw_rule, + ipa_flt_gen_hw_rule, + ipa_flt_generate_eq, + ipa_rt_parse_hw_rule, + ipa_flt_parse_hw_rule, + { + [IPA_TOS_EQ] = 0, + [IPA_PROTOCOL_EQ] = 1, + [IPA_TC_EQ] = 2, + [IPA_OFFSET_MEQ128_0] = 3, + [IPA_OFFSET_MEQ128_1] = 4, + [IPA_OFFSET_MEQ32_0] = 5, + [IPA_OFFSET_MEQ32_1] = 6, + [IPA_IHL_OFFSET_MEQ32_0] = 7, + [IPA_IHL_OFFSET_MEQ32_1] = 8, + [IPA_METADATA_COMPARE] = 9, + [IPA_IHL_OFFSET_RANGE16_0] = 10, + [IPA_IHL_OFFSET_RANGE16_1] = 11, + [IPA_IHL_OFFSET_EQ_32] = 12, + [IPA_IHL_OFFSET_EQ_16] = 13, + [IPA_FL_EQ] = 14, + [IPA_IS_FRAG] = 15, + [IPA_IS_PURE_ACK] = 0xFF, + }, + IPA3_0_HW_RULE_PREFETCH_BUF_SIZE, + }, + + /* IPAv4 */ + [IPA_HW_v4_0] = { + true, + IPA3_0_HW_TBL_WIDTH, + IPA3_0_HW_TBL_SYSADDR_ALIGNMENT, + IPA3_0_HW_TBL_LCLADDR_ALIGNMENT, + IPA3_0_HW_TBL_BLK_SIZE_ALIGNMENT, + IPA3_0_HW_RULE_START_ALIGNMENT, + IPA3_0_HW_TBL_HDR_WIDTH, + IPA3_0_HW_TBL_ADDR_MASK, + IPA3_0_RULE_MAX_PRIORITY, + IPA3_0_RULE_MIN_PRIORITY, + IPA3_0_LOW_RULE_ID, + IPA3_0_RULE_ID_BIT_LEN, + IPA3_0_HW_RULE_BUF_SIZE, + ipa_write_64, + ipa_fltrt_create_flt_bitmap, + ipa_fltrt_create_tbl_addr, + ipa_fltrt_parse_tbl_addr, + ipa_rt_gen_hw_rule, + ipa_flt_gen_hw_rule_ipav4, + ipa_flt_generate_eq, + ipa_rt_parse_hw_rule, + ipa_flt_parse_hw_rule_ipav4, + { + [IPA_TOS_EQ] = 0, + [IPA_PROTOCOL_EQ] = 1, + [IPA_TC_EQ] = 2, + [IPA_OFFSET_MEQ128_0] = 3, + [IPA_OFFSET_MEQ128_1] = 4, + [IPA_OFFSET_MEQ32_0] = 5, + [IPA_OFFSET_MEQ32_1] = 6, + [IPA_IHL_OFFSET_MEQ32_0] = 7, + [IPA_IHL_OFFSET_MEQ32_1] = 8, + [IPA_METADATA_COMPARE] = 9, + [IPA_IHL_OFFSET_RANGE16_0] = 10, + [IPA_IHL_OFFSET_RANGE16_1] = 11, + [IPA_IHL_OFFSET_EQ_32] = 12, + [IPA_IHL_OFFSET_EQ_16] = 13, + [IPA_FL_EQ] = 14, + [IPA_IS_FRAG] = 15, + [IPA_IS_PURE_ACK] = 0xFF, + }, + IPA3_0_HW_RULE_PREFETCH_BUF_SIZE, + }, + + /* IPAv4.2 */ + [IPA_HW_v4_2] = { + false, + IPA3_0_HW_TBL_WIDTH, + IPA3_0_HW_TBL_SYSADDR_ALIGNMENT, + IPA3_0_HW_TBL_LCLADDR_ALIGNMENT, + IPA3_0_HW_TBL_BLK_SIZE_ALIGNMENT, + IPA3_0_HW_RULE_START_ALIGNMENT, + IPA3_0_HW_TBL_HDR_WIDTH, + IPA3_0_HW_TBL_ADDR_MASK, + IPA3_0_RULE_MAX_PRIORITY, + IPA3_0_RULE_MIN_PRIORITY, + IPA3_0_LOW_RULE_ID, + IPA3_0_RULE_ID_BIT_LEN, + IPA3_0_HW_RULE_BUF_SIZE, + ipa_write_64, + ipa_fltrt_create_flt_bitmap, + ipa_fltrt_create_tbl_addr, + ipa_fltrt_parse_tbl_addr, + ipa_rt_gen_hw_rule, + ipa_flt_gen_hw_rule_ipav4, + ipa_flt_generate_eq, + ipa_rt_parse_hw_rule, + ipa_flt_parse_hw_rule_ipav4, + { + [IPA_TOS_EQ] = 0, + [IPA_PROTOCOL_EQ] = 1, + [IPA_TC_EQ] = 2, + [IPA_OFFSET_MEQ128_0] = 3, + [IPA_OFFSET_MEQ128_1] = 4, + [IPA_OFFSET_MEQ32_0] = 5, + [IPA_OFFSET_MEQ32_1] = 6, + [IPA_IHL_OFFSET_MEQ32_0] = 7, + [IPA_IHL_OFFSET_MEQ32_1] = 8, + [IPA_METADATA_COMPARE] = 9, + [IPA_IHL_OFFSET_RANGE16_0] = 10, + [IPA_IHL_OFFSET_RANGE16_1] = 11, + [IPA_IHL_OFFSET_EQ_32] = 12, + [IPA_IHL_OFFSET_EQ_16] = 13, + [IPA_FL_EQ] = 14, + [IPA_IS_FRAG] = 15, + [IPA_IS_PURE_ACK] = 0xFF, + }, + IPA3_0_HW_RULE_PREFETCH_BUF_SIZE, + }, + + /* IPAv4.5 */ + [IPA_HW_v4_5] = { + true, + IPA3_0_HW_TBL_WIDTH, + IPA3_0_HW_TBL_SYSADDR_ALIGNMENT, + IPA3_0_HW_TBL_LCLADDR_ALIGNMENT, + IPA3_0_HW_TBL_BLK_SIZE_ALIGNMENT, + IPA3_0_HW_RULE_START_ALIGNMENT, + IPA3_0_HW_TBL_HDR_WIDTH, + IPA3_0_HW_TBL_ADDR_MASK, + IPA3_0_RULE_MAX_PRIORITY, + IPA3_0_RULE_MIN_PRIORITY, + IPA3_0_LOW_RULE_ID, + IPA3_0_RULE_ID_BIT_LEN, + IPA3_0_HW_RULE_BUF_SIZE, + ipa_write_64, + ipa_fltrt_create_flt_bitmap, + ipa_fltrt_create_tbl_addr, + ipa_fltrt_parse_tbl_addr, + ipa_rt_gen_hw_rule_ipav4_5, + ipa_flt_gen_hw_rule_ipav4_5, + ipa_flt_generate_eq, + ipa_rt_parse_hw_rule_ipav4_5, + ipa_flt_parse_hw_rule_ipav4_5, + { + [IPA_TOS_EQ] = 0xFF, + [IPA_PROTOCOL_EQ] = 1, + [IPA_TC_EQ] = 2, + [IPA_OFFSET_MEQ128_0] = 3, + [IPA_OFFSET_MEQ128_1] = 4, + [IPA_OFFSET_MEQ32_0] = 5, + [IPA_OFFSET_MEQ32_1] = 6, + [IPA_IHL_OFFSET_MEQ32_0] = 7, + [IPA_IHL_OFFSET_MEQ32_1] = 8, + [IPA_METADATA_COMPARE] = 9, + [IPA_IHL_OFFSET_RANGE16_0] = 10, + [IPA_IHL_OFFSET_RANGE16_1] = 11, + [IPA_IHL_OFFSET_EQ_32] = 12, + [IPA_IHL_OFFSET_EQ_16] = 13, + [IPA_FL_EQ] = 14, + [IPA_IS_FRAG] = 15, + [IPA_IS_PURE_ACK] = 0, + }, + IPA3_0_HW_RULE_PREFETCH_BUF_SIZE, + }, + + /* IPAv5 */ + [IPA_HW_v5_0] = { + true, + IPA3_0_HW_TBL_WIDTH, + IPA3_0_HW_TBL_SYSADDR_ALIGNMENT, + IPA3_0_HW_TBL_LCLADDR_ALIGNMENT, + IPA3_0_HW_TBL_BLK_SIZE_ALIGNMENT, + IPA3_0_HW_RULE_START_ALIGNMENT, + IPA3_0_HW_TBL_HDR_WIDTH, + IPA3_0_HW_TBL_ADDR_MASK, + IPA5_0_RULE_MAX_PRIORITY, + IPA5_0_RULE_MIN_PRIORITY, + IPA3_0_LOW_RULE_ID, + IPA3_0_RULE_ID_BIT_LEN, + IPA3_0_HW_RULE_BUF_SIZE, + ipa_write_64, + ipa_fltrt_create_flt_bitmap_v5_0, + ipa_fltrt_create_tbl_addr, + ipa_fltrt_parse_tbl_addr, + ipa_rt_gen_hw_rule_ipav5_0, + ipa_flt_gen_hw_rule_ipav5_0, + ipa_flt_generate_eq, + ipa_rt_parse_hw_rule_ipav5_0, + ipa_flt_parse_hw_rule_ipav5_0, + { + [IPA_TOS_EQ] = 0xFF, + [IPA_PROTOCOL_EQ] = 1, + [IPA_TC_EQ] = 2, + [IPA_OFFSET_MEQ128_0] = 3, + [IPA_OFFSET_MEQ128_1] = 4, + [IPA_OFFSET_MEQ32_0] = 5, + [IPA_OFFSET_MEQ32_1] = 6, + [IPA_IHL_OFFSET_MEQ32_0] = 7, + [IPA_IHL_OFFSET_MEQ32_1] = 8, + [IPA_METADATA_COMPARE] = 9, + [IPA_IHL_OFFSET_RANGE16_0] = 10, + [IPA_IHL_OFFSET_RANGE16_1] = 11, + [IPA_IHL_OFFSET_EQ_32] = 12, + [IPA_IHL_OFFSET_EQ_16] = 13, + [IPA_FL_EQ] = 14, + [IPA_IS_FRAG] = 15, + [IPA_IS_PURE_ACK] = 0, + }, + IPA3_0_HW_RULE_PREFETCH_BUF_SIZE, + }, + + /* IPAv5.5 */ + [IPA_HW_v5_5] = { + true, + IPA3_0_HW_TBL_WIDTH, + IPA3_0_HW_TBL_SYSADDR_ALIGNMENT, + IPA3_0_HW_TBL_LCLADDR_ALIGNMENT, + IPA3_0_HW_TBL_BLK_SIZE_ALIGNMENT, + IPA3_0_HW_RULE_START_ALIGNMENT, + IPA3_0_HW_TBL_HDR_WIDTH, + IPA3_0_HW_TBL_ADDR_MASK, + IPA5_0_RULE_MAX_PRIORITY, + IPA5_0_RULE_MIN_PRIORITY, + IPA3_0_LOW_RULE_ID, + IPA3_0_RULE_ID_BIT_LEN, + IPA3_0_HW_RULE_BUF_SIZE, + ipa_write_64, + ipa_fltrt_create_flt_bitmap_v5_0, + ipa_fltrt_create_tbl_addr, + ipa_fltrt_parse_tbl_addr, + ipa_rt_gen_hw_rule_ipav5_5, + ipa_flt_gen_hw_rule_ipav5_5, + ipa_flt_generate_eq, + ipa_rt_parse_hw_rule_ipav5_5, + ipa_flt_parse_hw_rule_ipav5_5, + { + [IPA_TOS_EQ] = 0xFF, + [IPA_PROTOCOL_EQ] = 1, + [IPA_TC_EQ] = 2, + [IPA_OFFSET_MEQ128_0] = 3, + [IPA_OFFSET_MEQ128_1] = 4, + [IPA_OFFSET_MEQ32_0] = 5, + [IPA_OFFSET_MEQ32_1] = 6, + [IPA_IHL_OFFSET_MEQ32_0] = 7, + [IPA_IHL_OFFSET_MEQ32_1] = 8, + [IPA_METADATA_COMPARE] = 9, + [IPA_IHL_OFFSET_RANGE16_0] = 10, + [IPA_IHL_OFFSET_RANGE16_1] = 11, + [IPA_IHL_OFFSET_EQ_32] = 12, + [IPA_IHL_OFFSET_EQ_16] = 13, + [IPA_FL_EQ] = 14, + [IPA_IS_FRAG] = 15, + [IPA_IS_PURE_ACK] = 0, + }, + IPA3_0_HW_RULE_PREFETCH_BUF_SIZE, + }, + +}; + +static int ipa_flt_generate_eq(enum ipa_ip_type ipt, + const struct ipa_rule_attrib *attrib, + struct ipa_ipfltri_rule_eq *eq_atrb) +{ + if (ipa_fltrt_rule_generation_err_check(ipt, attrib)) + return -EPERM; + + if (ipt == IPA_IP_v4) { + if (ipa_flt_generate_eq_ip4(ipt, attrib, eq_atrb)) { + IPAHAL_ERR_RL("failed to build ipv4 flt eq rule\n"); + return -EPERM; + } + } else if (ipt == IPA_IP_v6) { + if (ipa_flt_generate_eq_ip6(ipt, attrib, eq_atrb)) { + IPAHAL_ERR_RL("failed to build ipv6 flt eq rule\n"); + return -EPERM; + } + } else { + IPAHAL_ERR("unsupported ip %d\n", ipt); + return -EPERM; + } + + /* + * default "rule" means no attributes set -> map to + * OFFSET_MEQ32_0 with mask of 0 and val of 0 and offset 0 + */ + if ((attrib->attrib_mask == 0) && (attrib->ext_attrib_mask == 0)) { + eq_atrb->rule_eq_bitmap = 0; + eq_atrb->rule_eq_bitmap |= IPA_GET_RULE_EQ_BIT_PTRN( + IPA_OFFSET_MEQ32_0); + eq_atrb->offset_meq_32[0].offset = 0; + eq_atrb->offset_meq_32[0].mask = 0; + eq_atrb->offset_meq_32[0].value = 0; + } + + return 0; +} + +static void ipa_fltrt_generate_mac_addr_hw_rule(u8 **extra, u8 **rest, + u8 hdr_mac_addr_offset, + const uint8_t mac_addr_mask[ETH_ALEN], + const uint8_t mac_addr[ETH_ALEN]) +{ + int i; + + *extra = ipa_write_8(hdr_mac_addr_offset, *extra); + + /* LSB MASK and ADDR */ + *rest = ipa_write_64(0, *rest); + *rest = ipa_write_64(0, *rest); + + /* MSB MASK and ADDR */ + *rest = ipa_write_16(0, *rest); + for (i = 5; i >= 0; i--) + *rest = ipa_write_8(mac_addr_mask[i], *rest); + *rest = ipa_write_16(0, *rest); + for (i = 5; i >= 0; i--) + *rest = ipa_write_8(mac_addr[i], *rest); +} + +static inline void ipa_fltrt_get_mac_data(const struct ipa_rule_attrib *attrib, + uint32_t attrib_mask, u8 *offset, const uint8_t **mac_addr, + const uint8_t **mac_addr_mask) +{ + if (attrib_mask & IPA_FLT_MAC_DST_ADDR_ETHER_II) { + *offset = -14; + *mac_addr = attrib->dst_mac_addr; + *mac_addr_mask = attrib->dst_mac_addr_mask; + return; + } + + if (attrib_mask & IPA_FLT_MAC_SRC_ADDR_ETHER_II) { + *offset = -8; + *mac_addr = attrib->src_mac_addr; + *mac_addr_mask = attrib->src_mac_addr_mask; + return; + } + + if (attrib_mask & IPA_FLT_MAC_DST_ADDR_802_3) { + *offset = -22; + *mac_addr = attrib->dst_mac_addr; + *mac_addr_mask = attrib->dst_mac_addr_mask; + return; + } + + if (attrib_mask & IPA_FLT_MAC_SRC_ADDR_802_3) { + *offset = -16; + *mac_addr = attrib->src_mac_addr; + *mac_addr_mask = attrib->src_mac_addr_mask; + return; + } + + if (attrib_mask & IPA_FLT_MAC_DST_ADDR_802_1Q) { + *offset = -18; + *mac_addr = attrib->dst_mac_addr; + *mac_addr_mask = attrib->dst_mac_addr_mask; + return; + } + + if (attrib_mask & IPA_FLT_MAC_SRC_ADDR_802_1Q) { + *offset = -10; + *mac_addr = attrib->src_mac_addr; + *mac_addr_mask = attrib->src_mac_addr_mask; + return; + } +} + +static int ipa_fltrt_generate_mac_hw_rule_bdy(u16 *en_rule, + const struct ipa_rule_attrib *attrib, + u8 *ofst_meq128, u8 **extra, u8 **rest) +{ + u8 offset = 0; + const uint8_t *mac_addr = NULL; + const uint8_t *mac_addr_mask = NULL; + int i; + uint32_t attrib_mask; + + for (i = 0; i < hweight_long(IPA_MAC_FLT_BITS); i++) { + switch (i) { + case 0: + attrib_mask = IPA_FLT_MAC_DST_ADDR_ETHER_II; + break; + case 1: + attrib_mask = IPA_FLT_MAC_SRC_ADDR_ETHER_II; + break; + case 2: + attrib_mask = IPA_FLT_MAC_DST_ADDR_802_3; + break; + case 3: + attrib_mask = IPA_FLT_MAC_SRC_ADDR_802_3; + break; + case 4: + attrib_mask = IPA_FLT_MAC_DST_ADDR_802_1Q; + break; + case 5: + attrib_mask = IPA_FLT_MAC_SRC_ADDR_802_1Q; + break; + default: + return -EPERM; + } + + attrib_mask &= attrib->attrib_mask; + if (!attrib_mask) + continue; + + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ofst_meq128, *ofst_meq128)) { + IPAHAL_ERR("ran out of meq128 eq\n"); + return -EPERM; + } + + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ofst_meq128[*ofst_meq128]); + + ipa_fltrt_get_mac_data(attrib, attrib_mask, &offset, + &mac_addr, &mac_addr_mask); + + ipa_fltrt_generate_mac_addr_hw_rule(extra, rest, offset, + mac_addr_mask, + mac_addr); + + (*ofst_meq128)++; + } + + return 0; +} + +static inline int ipa_fltrt_generate_vlan_hw_rule_bdy(u16 *en_rule, + const struct ipa_rule_attrib *attrib, + u8 *ofst_meq32, u8 **extra, u8 **rest) +{ + if (attrib->attrib_mask & IPA_FLT_VLAN_ID) { + uint32_t vlan_tag; + + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ofst_meq32, *ofst_meq32)) { + IPAHAL_ERR("ran out of meq32 eq\n"); + return -EPERM; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ofst_meq32[*ofst_meq32]); + /* -6 => offset of 802_1Q tag in L2 hdr */ + *extra = ipa_write_8((u8)-6, *extra); + /* filter vlan packets: 0x8100 TPID + required VLAN ID */ + vlan_tag = (0x8100 << 16) | (attrib->vlan_id & 0xFFF); + *rest = ipa_write_32(0xFFFF0FFF, *rest); + *rest = ipa_write_32(vlan_tag, *rest); + (*ofst_meq32)++; + } + + return 0; +} + +static int ipa_fltrt_generate_hw_rule_bdy_ip4(u16 *en_rule, + const struct ipa_rule_attrib *attrib, + u8 **extra_wrds, u8 **rest_wrds) +{ + u8 *extra = *extra_wrds; + u8 *rest = *rest_wrds; + u8 ofst_meq32 = 0; + u8 ihl_ofst_rng16 = 0; + u8 ihl_ofst_meq32 = 0; + u8 ofst_meq128 = 0; + int rc = 0; + bool tos_done = false; + + if (attrib->attrib_mask & IPA_FLT_IS_PURE_ACK) { + if (!IPA_IS_RULE_EQ_VALID(IPA_IS_PURE_ACK)) { + IPAHAL_ERR("is_pure_ack eq not supported\n"); + goto err; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN(IPA_IS_PURE_ACK); + extra = ipa_write_8(0, extra); + } + + if (attrib->attrib_mask & IPA_FLT_TOS && !tos_done) { + if (!IPA_IS_RULE_EQ_VALID(IPA_TOS_EQ)) { + IPAHAL_DBG("tos eq not supported\n"); + } else { + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN(IPA_TOS_EQ); + extra = ipa_write_8(attrib->u.v4.tos, extra); + tos_done = true; + } + } + + if (attrib->attrib_mask & IPA_FLT_PROTOCOL) { + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN(IPA_PROTOCOL_EQ); + extra = ipa_write_8(attrib->u.v4.protocol, extra); + } + + if (attrib->attrib_mask & IPA_MAC_FLT_BITS) { + if (ipa_fltrt_generate_mac_hw_rule_bdy(en_rule, attrib, + &ofst_meq128, &extra, &rest)) + goto err; + } + + if (attrib->attrib_mask & IPA_FLT_TOS_MASKED) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ofst_meq32, ofst_meq32)) { + IPAHAL_ERR("ran out of meq32 eq\n"); + goto err; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ofst_meq32[ofst_meq32]); + /* 0 => Take the first word. offset of TOS in v4 header is 1 */ + extra = ipa_write_8(0, extra); + rest = ipa_write_32((attrib->tos_mask << 16), rest); + rest = ipa_write_32((attrib->tos_value << 16), rest); + ofst_meq32++; + } + + if (attrib->attrib_mask & IPA_FLT_SRC_ADDR) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ofst_meq32, ofst_meq32)) { + IPAHAL_ERR("ran out of meq32 eq\n"); + goto err; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ofst_meq32[ofst_meq32]); + /* 12 => offset of src ip in v4 header */ + extra = ipa_write_8(12, extra); + rest = ipa_write_32(attrib->u.v4.src_addr_mask, rest); + rest = ipa_write_32(attrib->u.v4.src_addr, rest); + ofst_meq32++; + } + + if (attrib->attrib_mask & IPA_FLT_DST_ADDR) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ofst_meq32, ofst_meq32)) { + IPAHAL_ERR("ran out of meq32 eq\n"); + goto err; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ofst_meq32[ofst_meq32]); + /* 16 => offset of dst ip in v4 header */ + extra = ipa_write_8(16, extra); + rest = ipa_write_32(attrib->u.v4.dst_addr_mask, rest); + rest = ipa_write_32(attrib->u.v4.dst_addr, rest); + ofst_meq32++; + } + + if (attrib->attrib_mask & IPA_FLT_MAC_ETHER_TYPE) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ofst_meq32, ofst_meq32)) { + IPAHAL_ERR("ran out of meq32 eq\n"); + goto err; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ofst_meq32[ofst_meq32]); + /* -2 => offset of ether type in L2 hdr */ + extra = ipa_write_8((u8)-2, extra); + rest = ipa_write_16(0, rest); + rest = ipa_write_16(htons(attrib->ether_type), rest); + rest = ipa_write_16(0, rest); + rest = ipa_write_16(htons(attrib->ether_type), rest); + ofst_meq32++; + } + + if (attrib->attrib_mask & IPA_FLT_TOS && !tos_done) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ofst_meq32, ofst_meq32)) { + IPAHAL_DBG("ran out of meq32 eq\n"); + } else { + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ofst_meq32[ofst_meq32]); + /* + * 0 => Take the first word. + * offset of TOS in v4 header is 1 + */ + extra = ipa_write_8(0, extra); + rest = ipa_write_32(0xFF << 16, rest); + rest = ipa_write_32((attrib->u.v4.tos << 16), rest); + ofst_meq32++; + tos_done = true; + } + } + + if (ipa_fltrt_generate_vlan_hw_rule_bdy(en_rule, attrib, &ofst_meq32, + &extra, &rest)) + goto err; + + if (attrib->attrib_mask & IPA_FLT_TYPE) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ihl_ofst_meq32, + ihl_ofst_meq32)) { + IPAHAL_ERR("ran out of ihl_meq32 eq\n"); + goto err; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ihl_ofst_meq32[ihl_ofst_meq32]); + /* 0 => offset of type after v4 header */ + extra = ipa_write_8(0, extra); + rest = ipa_write_32(0xFF, rest); + rest = ipa_write_32(attrib->type, rest); + ihl_ofst_meq32++; + } + + if (attrib->attrib_mask & IPA_FLT_CODE) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ihl_ofst_meq32, + ihl_ofst_meq32)) { + IPAHAL_ERR("ran out of ihl_meq32 eq\n"); + goto err; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ihl_ofst_meq32[ihl_ofst_meq32]); + /* 1 => offset of code after v4 header */ + extra = ipa_write_8(1, extra); + rest = ipa_write_32(0xFF, rest); + rest = ipa_write_32(attrib->code, rest); + ihl_ofst_meq32++; + } + + if (attrib->attrib_mask & IPA_FLT_SPI) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ihl_ofst_meq32, + ihl_ofst_meq32)) { + IPAHAL_ERR("ran out of ihl_meq32 eq\n"); + goto err; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ihl_ofst_meq32[ihl_ofst_meq32]); + /* 0 => offset of SPI after v4 header */ + extra = ipa_write_8(0, extra); + rest = ipa_write_32(0xFFFFFFFF, rest); + rest = ipa_write_32(attrib->spi, rest); + ihl_ofst_meq32++; + } + + if (attrib->attrib_mask & IPA_FLT_MAC_DST_ADDR_L2TP) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ihl_ofst_meq32, + ihl_ofst_meq32) || IPA_IS_RAN_OUT_OF_EQ( + ipa3_0_ihl_ofst_meq32, ihl_ofst_meq32 + 1)) { + IPAHAL_ERR("ran out of ihl_meq32 eq\n"); + goto err; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ihl_ofst_meq32[ihl_ofst_meq32]); + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ihl_ofst_meq32[ihl_ofst_meq32 + 1]); + /* populate first ihl meq eq */ + extra = ipa_write_8(8, extra); + rest = ipa_write_8(attrib->dst_mac_addr_mask[3], rest); + rest = ipa_write_8(attrib->dst_mac_addr_mask[2], rest); + rest = ipa_write_8(attrib->dst_mac_addr_mask[1], rest); + rest = ipa_write_8(attrib->dst_mac_addr_mask[0], rest); + rest = ipa_write_8(attrib->dst_mac_addr[3], rest); + rest = ipa_write_8(attrib->dst_mac_addr[2], rest); + rest = ipa_write_8(attrib->dst_mac_addr[1], rest); + rest = ipa_write_8(attrib->dst_mac_addr[0], rest); + /* populate second ihl meq eq */ + extra = ipa_write_8(12, extra); + rest = ipa_write_16(0, rest); + rest = ipa_write_8(attrib->dst_mac_addr_mask[5], rest); + rest = ipa_write_8(attrib->dst_mac_addr_mask[4], rest); + rest = ipa_write_16(0, rest); + rest = ipa_write_8(attrib->dst_mac_addr[5], rest); + rest = ipa_write_8(attrib->dst_mac_addr[4], rest); + ihl_ofst_meq32 += 2; + } + + if (attrib->attrib_mask & IPA_FLT_L2TP_UDP_INNER_MAC_DST_ADDR) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ihl_ofst_meq32, + ihl_ofst_meq32) || IPA_IS_RAN_OUT_OF_EQ( + ipa3_0_ihl_ofst_meq32, ihl_ofst_meq32 + 1)) { + IPAHAL_ERR("ran out of ihl_meq32 eq\n"); + goto err; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ihl_ofst_meq32[ihl_ofst_meq32]); + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ihl_ofst_meq32[ihl_ofst_meq32 + 1]); + /* populate first ihl meq eq */ + extra = ipa_write_8(24, extra); + rest = ipa_write_8(attrib->dst_mac_addr_mask[3], rest); + rest = ipa_write_8(attrib->dst_mac_addr_mask[2], rest); + rest = ipa_write_8(attrib->dst_mac_addr_mask[1], rest); + rest = ipa_write_8(attrib->dst_mac_addr_mask[0], rest); + rest = ipa_write_8(attrib->dst_mac_addr[3], rest); + rest = ipa_write_8(attrib->dst_mac_addr[2], rest); + rest = ipa_write_8(attrib->dst_mac_addr[1], rest); + rest = ipa_write_8(attrib->dst_mac_addr[0], rest); + /* populate second ihl meq eq */ + extra = ipa_write_8(28, extra); + rest = ipa_write_16(0, rest); + rest = ipa_write_8(attrib->dst_mac_addr_mask[5], rest); + rest = ipa_write_8(attrib->dst_mac_addr_mask[4], rest); + rest = ipa_write_16(0, rest); + rest = ipa_write_8(attrib->dst_mac_addr[5], rest); + rest = ipa_write_8(attrib->dst_mac_addr[4], rest); + ihl_ofst_meq32 += 2; + } + + if (attrib->ext_attrib_mask & IPA_FLT_EXT_L2TP_UDP_INNER_ETHER_TYPE) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ofst_meq32, ofst_meq32)) { + IPAHAL_ERR("ran out of meq32 eq\n"); + goto err; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ofst_meq32[ofst_meq32]); + /* 76 => offset of inner ether type in L2TP over UDP hdr */ + extra = ipa_write_8(76, extra); + rest = ipa_write_16(0, rest); + rest = ipa_write_16(attrib->ether_type, rest); + rest = ipa_write_16(0, rest); + rest = ipa_write_16(attrib->ether_type, rest); + ofst_meq32++; + } + + if (attrib->attrib_mask & IPA_FLT_TCP_SYN) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ihl_ofst_meq32, + ihl_ofst_meq32)) { + IPAHAL_ERR("ran out of ihl_meq32 eq\n"); + goto err; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ihl_ofst_meq32[ihl_ofst_meq32]); + /* 12 => offset of SYN after v4 header */ + extra = ipa_write_8(12, extra); + rest = ipa_write_32(0x20000, rest); + rest = ipa_write_32(0x20000, rest); + ihl_ofst_meq32++; + } + + if (attrib->attrib_mask & IPA_FLT_TOS && !tos_done) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ihl_ofst_meq32, + ihl_ofst_meq32)) { + IPAHAL_DBG("ran out of ihl_meq32 eq\n"); + } else { + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ihl_ofst_meq32[ihl_ofst_meq32]); + /* + * 0 => Take the first word. offset of TOS in + * v4 header is 1. MSB bit asserted at IHL means + * to ignore packet IHL and do offset inside IPA header + */ + extra = ipa_write_8(0x80, extra); + rest = ipa_write_32(0xFF << 16, rest); + rest = ipa_write_32((attrib->u.v4.tos << 16), rest); + ihl_ofst_meq32++; + tos_done = true; + } + } + + if (attrib->attrib_mask & IPA_FLT_META_DATA) { + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN(IPA_METADATA_COMPARE); + rest = ipa_write_32(attrib->meta_data_mask, rest); + rest = ipa_write_32(attrib->meta_data, rest); + } + + if (attrib->ext_attrib_mask & IPA_FLT_EXT_MTU) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ihl_ofst_rng16, + ihl_ofst_rng16)) { + IPAHAL_ERR("ran out of ihl_rng16 eq\n"); + goto err; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ihl_ofst_rng16[ihl_ofst_rng16]); + /* 130 => (130 - 128) = 2 offset of length in v4 header */ + extra = ipa_write_8(130, extra); + rest = ipa_write_16(attrib->payload_length, rest); + rest = ipa_write_16(0, rest); + ihl_ofst_rng16++; + } + + if (attrib->attrib_mask & IPA_FLT_SRC_PORT_RANGE) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ihl_ofst_rng16, + ihl_ofst_rng16)) { + IPAHAL_ERR("ran out of ihl_rng16 eq\n"); + goto err; + } + if (attrib->src_port_hi < attrib->src_port_lo) { + IPAHAL_ERR("bad src port range param\n"); + goto err; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ihl_ofst_rng16[ihl_ofst_rng16]); + /* 0 => offset of src port after v4 header */ + extra = ipa_write_8(0, extra); + rest = ipa_write_16(attrib->src_port_hi, rest); + rest = ipa_write_16(attrib->src_port_lo, rest); + ihl_ofst_rng16++; + } + + if (attrib->attrib_mask & IPA_FLT_DST_PORT_RANGE) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ihl_ofst_rng16, + ihl_ofst_rng16)) { + IPAHAL_ERR("ran out of ihl_rng16 eq\n"); + goto err; + } + if (attrib->dst_port_hi < attrib->dst_port_lo) { + IPAHAL_ERR("bad dst port range param\n"); + goto err; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ihl_ofst_rng16[ihl_ofst_rng16]); + /* 2 => offset of dst port after v4 header */ + extra = ipa_write_8(2, extra); + rest = ipa_write_16(attrib->dst_port_hi, rest); + rest = ipa_write_16(attrib->dst_port_lo, rest); + ihl_ofst_rng16++; + } + + if (attrib->attrib_mask & IPA_FLT_SRC_PORT) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ihl_ofst_rng16, + ihl_ofst_rng16)) { + IPAHAL_ERR("ran out of ihl_rng16 eq\n"); + goto err; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ihl_ofst_rng16[ihl_ofst_rng16]); + /* 0 => offset of src port after v4 header */ + extra = ipa_write_8(0, extra); + rest = ipa_write_16(attrib->src_port, rest); + rest = ipa_write_16(attrib->src_port, rest); + ihl_ofst_rng16++; + } + + if (attrib->attrib_mask & IPA_FLT_DST_PORT) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ihl_ofst_rng16, + ihl_ofst_rng16)) { + IPAHAL_ERR("ran out of ihl_rng16 eq\n"); + goto err; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ihl_ofst_rng16[ihl_ofst_rng16]); + /* 2 => offset of dst port after v4 header */ + extra = ipa_write_8(2, extra); + rest = ipa_write_16(attrib->dst_port, rest); + rest = ipa_write_16(attrib->dst_port, rest); + ihl_ofst_rng16++; + } + + if (attrib->attrib_mask & IPA_FLT_FRAGMENT) + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN(IPA_IS_FRAG); + + if (attrib->attrib_mask & IPA_FLT_TOS && !tos_done) { + IPAHAL_ERR("could not find equation for tos\n"); + goto err; + } + + goto done; + +err: + rc = -EPERM; +done: + *extra_wrds = extra; + *rest_wrds = rest; + return rc; +} + +static int ipa_fltrt_generate_hw_rule_bdy_ip6(u16 *en_rule, + const struct ipa_rule_attrib *attrib, + u8 **extra_wrds, u8 **rest_wrds) +{ + u8 *extra = *extra_wrds; + u8 *rest = *rest_wrds; + u8 ofst_meq32 = 0; + u8 ihl_ofst_rng16 = 0; + u8 ihl_ofst_meq32 = 0; + u8 ofst_meq128 = 0; + int rc = 0; + + /* v6 code below assumes no extension headers TODO: fix this */ + if (attrib->attrib_mask & IPA_FLT_IS_PURE_ACK) { + if (!IPA_IS_RULE_EQ_VALID(IPA_IS_PURE_ACK)) { + IPAHAL_ERR("is_pure_ack eq not supported\n"); + goto err; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN(IPA_IS_PURE_ACK); + extra = ipa_write_8(0, extra); + } + + if (attrib->attrib_mask & IPA_FLT_NEXT_HDR) { + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN(IPA_PROTOCOL_EQ); + extra = ipa_write_8(attrib->u.v6.next_hdr, extra); + } + + if (attrib->ext_attrib_mask & IPA_FLT_EXT_NEXT_HDR) { + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ihl_ofst_meq32[ihl_ofst_meq32]); + /* 134 => offset of Next header after v6 header. */ + extra = ipa_write_8(134, extra); + rest = ipa_write_32(0xFF000000, rest); + rest = ipa_write_32(attrib->u.v6.next_hdr << 24, rest); + extra = ipa_write_8(attrib->u.v6.next_hdr, extra); + ihl_ofst_meq32++; + } + + if (attrib->attrib_mask & IPA_FLT_TC) { + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN(IPA_TC_EQ); + extra = ipa_write_8(attrib->u.v6.tc, extra); + } + + if (attrib->attrib_mask & IPA_FLT_SRC_ADDR) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ofst_meq128, ofst_meq128)) { + IPAHAL_ERR("ran out of meq128 eq\n"); + goto err; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ofst_meq128[ofst_meq128]); + /* 8 => offset of src ip in v6 header */ + extra = ipa_write_8(8, extra); + rest = ipa_write_32(attrib->u.v6.src_addr_mask[3], rest); + rest = ipa_write_32(attrib->u.v6.src_addr_mask[2], rest); + rest = ipa_write_32(attrib->u.v6.src_addr[3], rest); + rest = ipa_write_32(attrib->u.v6.src_addr[2], rest); + rest = ipa_write_32(attrib->u.v6.src_addr_mask[1], rest); + rest = ipa_write_32(attrib->u.v6.src_addr_mask[0], rest); + rest = ipa_write_32(attrib->u.v6.src_addr[1], rest); + rest = ipa_write_32(attrib->u.v6.src_addr[0], rest); + ofst_meq128++; + } + + if (attrib->attrib_mask & IPA_FLT_DST_ADDR) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ofst_meq128, ofst_meq128)) { + IPAHAL_ERR("ran out of meq128 eq\n"); + goto err; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ofst_meq128[ofst_meq128]); + /* 24 => offset of dst ip in v6 header */ + extra = ipa_write_8(24, extra); + rest = ipa_write_32(attrib->u.v6.dst_addr_mask[3], rest); + rest = ipa_write_32(attrib->u.v6.dst_addr_mask[2], rest); + rest = ipa_write_32(attrib->u.v6.dst_addr[3], rest); + rest = ipa_write_32(attrib->u.v6.dst_addr[2], rest); + rest = ipa_write_32(attrib->u.v6.dst_addr_mask[1], rest); + rest = ipa_write_32(attrib->u.v6.dst_addr_mask[0], rest); + rest = ipa_write_32(attrib->u.v6.dst_addr[1], rest); + rest = ipa_write_32(attrib->u.v6.dst_addr[0], rest); + ofst_meq128++; + } + + if (attrib->attrib_mask & IPA_FLT_TOS_MASKED) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ofst_meq128, ofst_meq128)) { + IPAHAL_ERR("ran out of meq128 eq\n"); + goto err; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ofst_meq128[ofst_meq128]); + /* 0 => offset of TOS in v6 header */ + extra = ipa_write_8(0, extra); + rest = ipa_write_64(0, rest); + rest = ipa_write_64(0, rest); + rest = ipa_write_32(0, rest); + rest = ipa_write_32((attrib->tos_mask << 20), rest); + rest = ipa_write_32(0, rest); + rest = ipa_write_32((attrib->tos_value << 20), rest); + ofst_meq128++; + } + + if (attrib->attrib_mask & IPA_MAC_FLT_BITS) { + if (ipa_fltrt_generate_mac_hw_rule_bdy(en_rule, attrib, + &ofst_meq128, &extra, &rest)) + goto err; + } + + if (attrib->attrib_mask & IPA_FLT_MAC_ETHER_TYPE) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ofst_meq32, ofst_meq32)) { + IPAHAL_ERR("ran out of meq32 eq\n"); + goto err; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ofst_meq32[ofst_meq32]); + /* -2 => offset of ether type in L2 hdr */ + extra = ipa_write_8((u8)-2, extra); + rest = ipa_write_16(0, rest); + rest = ipa_write_16(htons(attrib->ether_type), rest); + rest = ipa_write_16(0, rest); + rest = ipa_write_16(htons(attrib->ether_type), rest); + ofst_meq32++; + } + + if (ipa_fltrt_generate_vlan_hw_rule_bdy(en_rule, attrib, &ofst_meq32, + &extra, &rest)) + goto err; + + if (attrib->attrib_mask & IPA_FLT_TYPE) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ihl_ofst_meq32, + ihl_ofst_meq32)) { + IPAHAL_ERR("ran out of ihl_meq32 eq\n"); + goto err; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ihl_ofst_meq32[ihl_ofst_meq32]); + /* 0 => offset of type after v6 header */ + extra = ipa_write_8(0, extra); + rest = ipa_write_32(0xFF, rest); + rest = ipa_write_32(attrib->type, rest); + ihl_ofst_meq32++; + } + + if (attrib->attrib_mask & IPA_FLT_CODE) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ihl_ofst_meq32, + ihl_ofst_meq32)) { + IPAHAL_ERR("ran out of ihl_meq32 eq\n"); + goto err; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ihl_ofst_meq32[ihl_ofst_meq32]); + /* 1 => offset of code after v6 header */ + extra = ipa_write_8(1, extra); + rest = ipa_write_32(0xFF, rest); + rest = ipa_write_32(attrib->code, rest); + ihl_ofst_meq32++; + } + + if (attrib->attrib_mask & IPA_FLT_SPI) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ihl_ofst_meq32, + ihl_ofst_meq32)) { + IPAHAL_ERR("ran out of ihl_meq32 eq\n"); + goto err; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ihl_ofst_meq32[ihl_ofst_meq32]); + /* 0 => offset of SPI after v6 header FIXME */ + extra = ipa_write_8(0, extra); + rest = ipa_write_32(0xFFFFFFFF, rest); + rest = ipa_write_32(attrib->spi, rest); + ihl_ofst_meq32++; + } + + if (attrib->attrib_mask & IPA_FLT_MAC_DST_ADDR_L2TP) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ihl_ofst_meq32, + ihl_ofst_meq32) || IPA_IS_RAN_OUT_OF_EQ( + ipa3_0_ihl_ofst_meq32, ihl_ofst_meq32 + 1)) { + IPAHAL_ERR("ran out of ihl_meq32 eq\n"); + goto err; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ihl_ofst_meq32[ihl_ofst_meq32]); + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ihl_ofst_meq32[ihl_ofst_meq32 + 1]); + /* populate first ihl meq eq */ + extra = ipa_write_8(8, extra); + rest = ipa_write_8(attrib->dst_mac_addr_mask[3], rest); + rest = ipa_write_8(attrib->dst_mac_addr_mask[2], rest); + rest = ipa_write_8(attrib->dst_mac_addr_mask[1], rest); + rest = ipa_write_8(attrib->dst_mac_addr_mask[0], rest); + rest = ipa_write_8(attrib->dst_mac_addr[3], rest); + rest = ipa_write_8(attrib->dst_mac_addr[2], rest); + rest = ipa_write_8(attrib->dst_mac_addr[1], rest); + rest = ipa_write_8(attrib->dst_mac_addr[0], rest); + /* populate second ihl meq eq */ + extra = ipa_write_8(12, extra); + rest = ipa_write_16(0, rest); + rest = ipa_write_8(attrib->dst_mac_addr_mask[5], rest); + rest = ipa_write_8(attrib->dst_mac_addr_mask[4], rest); + rest = ipa_write_16(0, rest); + rest = ipa_write_8(attrib->dst_mac_addr[5], rest); + rest = ipa_write_8(attrib->dst_mac_addr[4], rest); + ihl_ofst_meq32 += 2; + } + + if (attrib->attrib_mask & IPA_FLT_L2TP_UDP_INNER_MAC_DST_ADDR) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ihl_ofst_meq32, + ihl_ofst_meq32) || IPA_IS_RAN_OUT_OF_EQ( + ipa3_0_ihl_ofst_meq32, ihl_ofst_meq32 + 1)) { + IPAHAL_ERR("ran out of ihl_meq32 eq\n"); + goto err; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ihl_ofst_meq32[ihl_ofst_meq32]); + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ihl_ofst_meq32[ihl_ofst_meq32 + 1]); + /* populate first ihl meq eq */ + extra = ipa_write_8(24, extra); + rest = ipa_write_8(attrib->dst_mac_addr_mask[3], rest); + rest = ipa_write_8(attrib->dst_mac_addr_mask[2], rest); + rest = ipa_write_8(attrib->dst_mac_addr_mask[1], rest); + rest = ipa_write_8(attrib->dst_mac_addr_mask[0], rest); + rest = ipa_write_8(attrib->dst_mac_addr[3], rest); + rest = ipa_write_8(attrib->dst_mac_addr[2], rest); + rest = ipa_write_8(attrib->dst_mac_addr[1], rest); + rest = ipa_write_8(attrib->dst_mac_addr[0], rest); + /* populate second ihl meq eq */ + extra = ipa_write_8(28, extra); + rest = ipa_write_16(0, rest); + rest = ipa_write_8(attrib->dst_mac_addr_mask[5], rest); + rest = ipa_write_8(attrib->dst_mac_addr_mask[4], rest); + rest = ipa_write_16(0, rest); + rest = ipa_write_8(attrib->dst_mac_addr[5], rest); + rest = ipa_write_8(attrib->dst_mac_addr[4], rest); + ihl_ofst_meq32 += 2; + } + + if (attrib->ext_attrib_mask & IPA_FLT_EXT_L2TP_UDP_INNER_ETHER_TYPE) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ofst_meq32, ofst_meq32)) { + IPAHAL_ERR("ran out of meq32 eq\n"); + goto err; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ofst_meq32[ofst_meq32]); + /* 76 => offset of inner ether type in L2TP over UDP */ + extra = ipa_write_8(76, extra); + rest = ipa_write_16(0, rest); + rest = ipa_write_16(attrib->ether_type, rest); + rest = ipa_write_16(0, rest); + rest = ipa_write_16(attrib->ether_type, rest); + ofst_meq32++; + } + + if (attrib->ext_attrib_mask & IPA_FLT_EXT_L2TP_UDP_TCP_SYN) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ihl_ofst_meq32, + ihl_ofst_meq32) || IPA_IS_RAN_OUT_OF_EQ( + ipa3_0_ihl_ofst_meq32, ihl_ofst_meq32 + 1)) { + IPAHAL_ERR("ran out of ihl_meq32 eq\n"); + goto err; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ihl_ofst_meq32[ihl_ofst_meq32]); + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ihl_ofst_meq32[ihl_ofst_meq32 + 1]); + + /* populate TCP protocol eq */ + if (attrib->ether_type == 0x0800) { + extra = ipa_write_8(46, extra); + rest = ipa_write_32(0xFF0000, rest); + rest = ipa_write_32(0x60000, rest); + } else { + extra = ipa_write_8(42, extra); + rest = ipa_write_32(0xFF00, rest); + rest = ipa_write_32(0x600, rest); + } + + /* populate TCP SYN eq */ + if (attrib->ether_type == 0x0800) { + extra = ipa_write_8(70, extra); + rest = ipa_write_32(0x20000, rest); + rest = ipa_write_32(0x20000, rest); + } else { + extra = ipa_write_8(90, extra); + rest = ipa_write_32(0x20000, rest); + rest = ipa_write_32(0x20000, rest); + } + ihl_ofst_meq32 += 2; + } + + if (attrib->ext_attrib_mask & IPA_FLT_EXT_L2TP_UDP_INNER_NEXT_HDR) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ihl_ofst_meq32, + ihl_ofst_meq32)) { + IPAHAL_ERR("ran out of ihl_meq32 eq\n"); + goto err; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ihl_ofst_meq32[ihl_ofst_meq32]); + + /* Populate next header */ + if (attrib->ether_type == 0x0800) { + /* 46 => offset of inner next hdr type in + * L2TP over UDP (IPv4). + * 46 = UDP (8) + L2TP (16) + ETH (14) + 8 bytes + * in Ipv4 header. + */ + extra = ipa_write_8(46, extra); + rest = ipa_write_32(0xFF0000, rest); + rest = ipa_write_32((attrib->l2tp_udp_next_hdr << 16), + rest); + } else { + /* 42 => offset of inner next hdr type in + * L2TP over UDP (Ipv6). + * 42 = UDP (8) + L2TP (16) + ETH (14) + 4 bytes + * in Ipv6 header. + */ + extra = ipa_write_8(42, extra); + rest = ipa_write_32(0xFF00, rest); + rest = ipa_write_32((attrib->l2tp_udp_next_hdr << 8), + rest); + } + ihl_ofst_meq32++; + } + + if (attrib->attrib_mask & IPA_FLT_TCP_SYN) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ihl_ofst_meq32, + ihl_ofst_meq32)) { + IPAHAL_ERR("ran out of ihl_meq32 eq\n"); + goto err; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ihl_ofst_meq32[ihl_ofst_meq32]); + /* 12 => offset of SYN after v4 header */ + extra = ipa_write_8(12, extra); + rest = ipa_write_32(0x20000, rest); + rest = ipa_write_32(0x20000, rest); + ihl_ofst_meq32++; + } + + if (attrib->attrib_mask & IPA_FLT_TCP_SYN_L2TP) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ihl_ofst_meq32, + ihl_ofst_meq32) || IPA_IS_RAN_OUT_OF_EQ( + ipa3_0_ihl_ofst_meq32, ihl_ofst_meq32 + 1)) { + IPAHAL_ERR("ran out of ihl_meq32 eq\n"); + goto err; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ihl_ofst_meq32[ihl_ofst_meq32]); + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ihl_ofst_meq32[ihl_ofst_meq32 + 1]); + + /* populate TCP protocol eq */ + if (attrib->ether_type == 0x0800) { + extra = ipa_write_8(30, extra); + rest = ipa_write_32(0xFF0000, rest); + rest = ipa_write_32(0x60000, rest); + } else { + extra = ipa_write_8(26, extra); + rest = ipa_write_32(0xFF00, rest); + rest = ipa_write_32(0x600, rest); + } + + /* populate TCP SYN eq */ + if (attrib->ether_type == 0x0800) { + extra = ipa_write_8(54, extra); + rest = ipa_write_32(0x20000, rest); + rest = ipa_write_32(0x20000, rest); + } else { + extra = ipa_write_8(74, extra); + rest = ipa_write_32(0x20000, rest); + rest = ipa_write_32(0x20000, rest); + } + ihl_ofst_meq32 += 2; + } + + if (attrib->attrib_mask & IPA_FLT_L2TP_INNER_IP_TYPE) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ihl_ofst_meq32, + ihl_ofst_meq32)) { + IPAHAL_ERR("ran out of ihl_meq32 eq\n"); + goto err; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ihl_ofst_meq32[ihl_ofst_meq32]); + /* 22 => offset of IP type after v6 header */ + extra = ipa_write_8(22, extra); + rest = ipa_write_32(0xF0000000, rest); + if (attrib->type == 0x40) + rest = ipa_write_32(0x40000000, rest); + else + rest = ipa_write_32(0x60000000, rest); + ihl_ofst_meq32++; + } + + if (attrib->attrib_mask & IPA_FLT_L2TP_INNER_IPV4_DST_ADDR) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ihl_ofst_meq32, + ihl_ofst_meq32)) { + IPAHAL_ERR("ran out of ihl_meq32 eq\n"); + goto err; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ihl_ofst_meq32[ihl_ofst_meq32]); + /* 38 => offset of inner IPv4 addr */ + extra = ipa_write_8(38, extra); + rest = ipa_write_32(attrib->u.v4.dst_addr_mask, rest); + rest = ipa_write_32(attrib->u.v4.dst_addr, rest); + ihl_ofst_meq32++; + } + + if (attrib->attrib_mask & IPA_FLT_META_DATA) { + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN(IPA_METADATA_COMPARE); + rest = ipa_write_32(attrib->meta_data_mask, rest); + rest = ipa_write_32(attrib->meta_data, rest); + } + + if (attrib->attrib_mask & IPA_FLT_SRC_PORT) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ihl_ofst_rng16, + ihl_ofst_rng16)) { + IPAHAL_ERR("ran out of ihl_rng16 eq\n"); + goto err; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ihl_ofst_rng16[ihl_ofst_rng16]); + /* 0 => offset of src port after v6 header */ + extra = ipa_write_8(0, extra); + rest = ipa_write_16(attrib->src_port, rest); + rest = ipa_write_16(attrib->src_port, rest); + ihl_ofst_rng16++; + } + + if (attrib->attrib_mask & IPA_FLT_DST_PORT) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ihl_ofst_rng16, + ihl_ofst_rng16)) { + IPAHAL_ERR("ran out of ihl_rng16 eq\n"); + goto err; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ihl_ofst_rng16[ihl_ofst_rng16]); + /* 2 => offset of dst port after v6 header */ + extra = ipa_write_8(2, extra); + rest = ipa_write_16(attrib->dst_port, rest); + rest = ipa_write_16(attrib->dst_port, rest); + ihl_ofst_rng16++; + } + + if (attrib->attrib_mask & IPA_FLT_SRC_PORT_RANGE) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ihl_ofst_rng16, + ihl_ofst_rng16)) { + IPAHAL_ERR("ran out of ihl_rng16 eq\n"); + goto err; + } + if (attrib->src_port_hi < attrib->src_port_lo) { + IPAHAL_ERR("bad src port range param\n"); + goto err; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ihl_ofst_rng16[ihl_ofst_rng16]); + /* 0 => offset of src port after v6 header */ + extra = ipa_write_8(0, extra); + rest = ipa_write_16(attrib->src_port_hi, rest); + rest = ipa_write_16(attrib->src_port_lo, rest); + ihl_ofst_rng16++; + } + + if (attrib->attrib_mask & IPA_FLT_DST_PORT_RANGE) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ihl_ofst_rng16, + ihl_ofst_rng16)) { + IPAHAL_ERR("ran out of ihl_rng16 eq\n"); + goto err; + } + if (attrib->dst_port_hi < attrib->dst_port_lo) { + IPAHAL_ERR("bad dst port range param\n"); + goto err; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ihl_ofst_rng16[ihl_ofst_rng16]); + /* 2 => offset of dst port after v6 header */ + extra = ipa_write_8(2, extra); + rest = ipa_write_16(attrib->dst_port_hi, rest); + rest = ipa_write_16(attrib->dst_port_lo, rest); + ihl_ofst_rng16++; + } + + if (attrib->attrib_mask & IPA_FLT_TCP_SYN_L2TP) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ihl_ofst_rng16, + ihl_ofst_rng16)) { + IPAHAL_ERR("ran out of ihl_rng16 eq\n"); + goto err; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ihl_ofst_rng16[ihl_ofst_rng16]); + /* 20 => offset of Ethertype after v4 header */ + if (attrib->ether_type == 0x0800) { + extra = ipa_write_8(21, extra); + rest = ipa_write_16(0x0045, rest); + rest = ipa_write_16(0x0045, rest); + } else { + extra = ipa_write_8(20, extra); + rest = ipa_write_16(attrib->ether_type, rest); + rest = ipa_write_16(attrib->ether_type, rest); + } + ihl_ofst_rng16++; + } + + if (attrib->attrib_mask & IPA_FLT_FLOW_LABEL) { + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN(IPA_FL_EQ); + rest = ipa_write_32(attrib->u.v6.flow_label & 0xFFFFF, + rest); + } + + if (attrib->attrib_mask & IPA_FLT_FRAGMENT) + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN(IPA_IS_FRAG); + + goto done; + +err: + rc = -EPERM; +done: + *extra_wrds = extra; + *rest_wrds = rest; + return rc; +} + +static u8 *ipa_fltrt_copy_mem(u8 *src, u8 *dst, int cnt) +{ + while (cnt--) + *dst++ = *src++; + + return dst; +} + +/* + * ipa_fltrt_generate_hw_rule_bdy() - generate HW rule body (w/o header) + * @ip: IP address type + * @attrib: IPA rule attribute + * @buf: output buffer. Advance it after building the rule + * @en_rule: enable rule + * + * Return codes: + * 0: success + * -EPERM: wrong input + */ +static int ipa_fltrt_generate_hw_rule_bdy(enum ipa_ip_type ipt, + const struct ipa_rule_attrib *attrib, u8 **buf, u16 *en_rule) +{ + int sz; + int rc = 0; + u8 *extra_wrd_buf; + u8 *rest_wrd_buf; + u8 *extra_wrd_start; + u8 *rest_wrd_start; + u8 *extra_wrd_i; + u8 *rest_wrd_i; + + sz = IPA3_0_HW_TBL_WIDTH * 2 + IPA3_0_HW_RULE_START_ALIGNMENT; + extra_wrd_buf = kzalloc(sz, GFP_KERNEL); + if (!extra_wrd_buf) { + rc = -ENOMEM; + goto fail_extra_alloc; + } + + sz = IPA3_0_HW_RULE_BUF_SIZE + IPA3_0_HW_RULE_START_ALIGNMENT; + rest_wrd_buf = kzalloc(sz, GFP_KERNEL); + if (!rest_wrd_buf) { + rc = -ENOMEM; + goto fail_rest_alloc; + } + + extra_wrd_start = extra_wrd_buf + IPA3_0_HW_RULE_START_ALIGNMENT; + extra_wrd_start = (u8 *)((long)extra_wrd_start & + ~IPA3_0_HW_RULE_START_ALIGNMENT); + + rest_wrd_start = rest_wrd_buf + IPA3_0_HW_RULE_START_ALIGNMENT; + rest_wrd_start = (u8 *)((long)rest_wrd_start & + ~IPA3_0_HW_RULE_START_ALIGNMENT); + + extra_wrd_i = extra_wrd_start; + rest_wrd_i = rest_wrd_start; + + rc = ipa_fltrt_rule_generation_err_check(ipt, attrib); + if (rc) { + IPAHAL_ERR_RL("rule generation err check failed\n"); + goto fail_err_check; + } + + if (ipt == IPA_IP_v4) { + if (ipa_fltrt_generate_hw_rule_bdy_ip4(en_rule, attrib, + &extra_wrd_i, &rest_wrd_i)) { + IPAHAL_ERR_RL("failed to build ipv4 hw rule\n"); + rc = -EPERM; + goto fail_err_check; + } + + } else if (ipt == IPA_IP_v6) { + if (ipa_fltrt_generate_hw_rule_bdy_ip6(en_rule, attrib, + &extra_wrd_i, &rest_wrd_i)) { + IPAHAL_ERR_RL("failed to build ipv6 hw rule\n"); + rc = -EPERM; + goto fail_err_check; + } + } else { + IPAHAL_ERR_RL("unsupported ip %d\n", ipt); + goto fail_err_check; + } + + /* + * default "rule" means no attributes set -> map to + * OFFSET_MEQ32_0 with mask of 0 and val of 0 and offset 0 + */ + if (attrib->attrib_mask == 0) { + IPAHAL_DBG_LOW("building default rule\n"); + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN(ipa3_0_ofst_meq32[0]); + extra_wrd_i = ipa_write_8(0, extra_wrd_i); /* offset */ + rest_wrd_i = ipa_write_32(0, rest_wrd_i); /* mask */ + rest_wrd_i = ipa_write_32(0, rest_wrd_i); /* val */ + } + + IPAHAL_DBG_LOW("extra_word_1 0x%llx\n", *(u64 *)extra_wrd_start); + IPAHAL_DBG_LOW("extra_word_2 0x%llx\n", + *(u64 *)(extra_wrd_start + IPA3_0_HW_TBL_WIDTH)); + + extra_wrd_i = ipa_pad_to_64(extra_wrd_i); + sz = extra_wrd_i - extra_wrd_start; + IPAHAL_DBG_LOW("extra words params sz %d\n", sz); + *buf = ipa_fltrt_copy_mem(extra_wrd_start, *buf, sz); + + rest_wrd_i = ipa_pad_to_64(rest_wrd_i); + sz = rest_wrd_i - rest_wrd_start; + IPAHAL_DBG_LOW("non extra words params sz %d\n", sz); + *buf = ipa_fltrt_copy_mem(rest_wrd_start, *buf, sz); + +fail_err_check: + kfree(rest_wrd_buf); +fail_rest_alloc: + kfree(extra_wrd_buf); +fail_extra_alloc: + return rc; +} + +/* + * ipa_fltrt_generate_hw_rule_bdy_5_5() - generate HW rule body (w/o header) for 5.5 + * @ip: IP address type + * @attrib: IPA rule attribute + * @buf: output buffer. Advance it after building the rule + * @en_rule: enable rule + * + * Return codes: + * 0: success + * -EPERM: wrong input + */ +static int ipa_fltrt_generate_hw_rule_bdy_5_5(enum ipa_ip_type ipt, + const struct ipa_rule_attrib *attrib, u8 **buf, u16 *en_rule, bool ext_hdr) +{ + int sz; + int rc = 0; + u8 *extra_wrd_buf; + u8 *rest_wrd_buf; + u8 *extra_wrd_start; + u8 *rest_wrd_start; + u8 *extra_wrd_i; + u8 *rest_wrd_i; + + sz = IPA3_0_HW_TBL_WIDTH * 2 + IPA3_0_HW_RULE_START_ALIGNMENT; + extra_wrd_buf = kzalloc(sz, GFP_KERNEL); + if (!extra_wrd_buf) { + rc = -ENOMEM; + goto fail_extra_alloc; + } + + sz = IPA3_0_HW_RULE_BUF_SIZE + IPA3_0_HW_RULE_START_ALIGNMENT; + rest_wrd_buf = kzalloc(sz, GFP_KERNEL); + if (!rest_wrd_buf) { + rc = -ENOMEM; + goto fail_rest_alloc; + } + + extra_wrd_start = extra_wrd_buf + IPA3_0_HW_RULE_START_ALIGNMENT; + extra_wrd_start = (u8 *)((long)extra_wrd_start & + ~IPA3_0_HW_RULE_START_ALIGNMENT); + + rest_wrd_start = rest_wrd_buf + IPA3_0_HW_RULE_START_ALIGNMENT; + rest_wrd_start = (u8 *)((long)rest_wrd_start & + ~IPA3_0_HW_RULE_START_ALIGNMENT); + + extra_wrd_i = extra_wrd_start; + rest_wrd_i = rest_wrd_start; + + rc = ipa_fltrt_rule_generation_err_check(ipt, attrib); + if (rc) { + IPAHAL_ERR_RL("rule generation err check failed\n"); + goto fail_err_check; + } + + if (ipt == IPA_IP_v4) { + if (ipa_fltrt_generate_hw_rule_bdy_ip4(en_rule, attrib, + &extra_wrd_i, &rest_wrd_i)) { + IPAHAL_ERR_RL("failed to build ipv4 hw rule\n"); + rc = -EPERM; + goto fail_err_check; + } + + } else if (ipt == IPA_IP_v6) { + if (ipa_fltrt_generate_hw_rule_bdy_ip6(en_rule, attrib, + &extra_wrd_i, &rest_wrd_i)) { + IPAHAL_ERR_RL("failed to build ipv6 hw rule\n"); + rc = -EPERM; + goto fail_err_check; + } + } else { + IPAHAL_ERR_RL("unsupported ip %d\n", ipt); + goto fail_err_check; + } + + /* + * default "rule" means no attributes set -> map to + * OFFSET_MEQ32_0 with mask of 0 and val of 0 and offset 0 + */ + if (attrib->attrib_mask == 0) { + IPAHAL_DBG_LOW("building default rule\n"); + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN(ipa3_0_ofst_meq32[0]); + extra_wrd_i = ipa_write_8(0, extra_wrd_i); /* offset */ + rest_wrd_i = ipa_write_32(0, rest_wrd_i); /* mask */ + rest_wrd_i = ipa_write_32(0, rest_wrd_i); /* val */ + } + + IPAHAL_DBG_LOW("extra_word_1 0x%llx\n", *(u64 *)extra_wrd_start); + IPAHAL_DBG_LOW("extra_word_2 0x%llx\n", + *(u64 *)(extra_wrd_start + IPA3_0_HW_TBL_WIDTH)); + + if (ext_hdr) { + sz = extra_wrd_i - extra_wrd_start; + IPAHAL_DBG_LOW("extra words params sz %d, buf: 0x%llx, \n", sz, *buf); + *buf = ipa_fltrt_copy_mem(extra_wrd_start, *buf, sz); + IPAHAL_DBG_LOW("After extra copy *buf 0x%llx\n", *buf); + *buf = ipa_pad_to_64(*buf); + } else { + extra_wrd_i = ipa_pad_to_64(extra_wrd_i); + sz = extra_wrd_i - extra_wrd_start; + IPAHAL_DBG_LOW("extra words params sz %d, buf: 0x%llx, \n", sz, *buf); + *buf = ipa_fltrt_copy_mem(extra_wrd_start, *buf, sz); + } + IPAHAL_DBG_LOW("Updated *buf 0x%llx\n", *buf); + + rest_wrd_i = ipa_pad_to_64(rest_wrd_i); + sz = rest_wrd_i - rest_wrd_start; + IPAHAL_DBG_LOW("non extra words params sz %d\n", sz); + *buf = ipa_fltrt_copy_mem(rest_wrd_start, *buf, sz); + IPAHAL_DBG_LOW("After rest copy *buf 0x%llx\n", *buf); + +fail_err_check: + kfree(rest_wrd_buf); +fail_rest_alloc: + kfree(extra_wrd_buf); +fail_extra_alloc: + return rc; +} + + +/** + * ipa_fltrt_calc_extra_wrd_bytes()- Calculate the number of extra words for eq + * @attrib: equation attribute + * + * Return value: 0 on success, negative otherwise + */ +static int ipa_fltrt_calc_extra_wrd_bytes( + const struct ipa_ipfltri_rule_eq *attrib) +{ + int num = 0; + + /* + * tos_eq_present field has two meanings: + * tos equation for IPA ver < 4.5 (as the field name reveals) + * pure_ack equation for IPA ver >= 4.5 + * In both cases it needs one extra word. + */ + if (attrib->tos_eq_present) + num++; + if (attrib->protocol_eq_present) + num++; + if (attrib->tc_eq_present) + num++; + num += attrib->num_offset_meq_128; + num += attrib->num_offset_meq_32; + num += attrib->num_ihl_offset_meq_32; + num += attrib->num_ihl_offset_range_16; + if (attrib->ihl_offset_eq_32_present) + num++; + if (attrib->ihl_offset_eq_16_present) + num++; + + IPAHAL_DBG_LOW("extra bytes number %d\n", num); + + return num; +} + +static int ipa_fltrt_generate_hw_rule_bdy_from_eq( + const struct ipa_ipfltri_rule_eq *attrib, u8 **buf) +{ + uint8_t num_offset_meq_32 = attrib->num_offset_meq_32; + uint8_t num_ihl_offset_range_16 = attrib->num_ihl_offset_range_16; + uint8_t num_ihl_offset_meq_32 = attrib->num_ihl_offset_meq_32; + uint8_t num_offset_meq_128 = attrib->num_offset_meq_128; + int i; + int extra_bytes; + u8 *extra; + u8 *rest; + + extra_bytes = ipa_fltrt_calc_extra_wrd_bytes(attrib); + /* only 3 eq does not have extra word param, 13 out of 16 is the number + * of equations that needs extra word param + */ + if (extra_bytes > 13) { + IPAHAL_ERR_RL("too much extra bytes\n"); + return -EPERM; + } else if (extra_bytes > IPA3_0_HW_TBL_HDR_WIDTH) { + /* two extra words */ + extra = *buf; + rest = *buf + IPA3_0_HW_TBL_HDR_WIDTH * 2; + } else if (extra_bytes > 0) { + /* single exra word */ + extra = *buf; + rest = *buf + IPA3_0_HW_TBL_HDR_WIDTH; + } else { + /* no extra words */ + extra = NULL; + rest = *buf; + } + + /* + * tos_eq_present field has two meanings: + * tos equation for IPA ver < 4.5 (as the field name reveals) + * pure_ack equation for IPA ver >= 4.5 + * In both cases it needs one extra word. + */ + if (attrib->tos_eq_present) { + if (IPA_IS_RULE_EQ_VALID(IPA_IS_PURE_ACK)) { + extra = ipa_write_8(0, extra); + } else if (IPA_IS_RULE_EQ_VALID(IPA_TOS_EQ)) { + extra = ipa_write_8(attrib->tos_eq, extra); + } else { + IPAHAL_ERR("no support for pure_ack and tos eqs\n"); + return -EPERM; + } + } + + if (attrib->protocol_eq_present) + extra = ipa_write_8(attrib->protocol_eq, extra); + + if (attrib->tc_eq_present) + extra = ipa_write_8(attrib->tc_eq, extra); + + if (num_offset_meq_128) { + extra = ipa_write_8(attrib->offset_meq_128[0].offset, extra); + for (i = 0; i < 8; i++) + rest = ipa_write_8(attrib->offset_meq_128[0].mask[i], + rest); + for (i = 0; i < 8; i++) + rest = ipa_write_8(attrib->offset_meq_128[0].value[i], + rest); + for (i = 8; i < 16; i++) + rest = ipa_write_8(attrib->offset_meq_128[0].mask[i], + rest); + for (i = 8; i < 16; i++) + rest = ipa_write_8(attrib->offset_meq_128[0].value[i], + rest); + num_offset_meq_128--; + } + + if (num_offset_meq_128) { + extra = ipa_write_8(attrib->offset_meq_128[1].offset, extra); + for (i = 0; i < 8; i++) + rest = ipa_write_8(attrib->offset_meq_128[1].mask[i], + rest); + for (i = 0; i < 8; i++) + rest = ipa_write_8(attrib->offset_meq_128[1].value[i], + rest); + for (i = 8; i < 16; i++) + rest = ipa_write_8(attrib->offset_meq_128[1].mask[i], + rest); + for (i = 8; i < 16; i++) + rest = ipa_write_8(attrib->offset_meq_128[1].value[i], + rest); + num_offset_meq_128--; + } + + if (num_offset_meq_32) { + extra = ipa_write_8(attrib->offset_meq_32[0].offset, extra); + rest = ipa_write_32(attrib->offset_meq_32[0].mask, rest); + rest = ipa_write_32(attrib->offset_meq_32[0].value, rest); + num_offset_meq_32--; + } + + if (num_offset_meq_32) { + extra = ipa_write_8(attrib->offset_meq_32[1].offset, extra); + rest = ipa_write_32(attrib->offset_meq_32[1].mask, rest); + rest = ipa_write_32(attrib->offset_meq_32[1].value, rest); + num_offset_meq_32--; + } + + if (num_ihl_offset_meq_32) { + extra = ipa_write_8(attrib->ihl_offset_meq_32[0].offset, + extra); + + rest = ipa_write_32(attrib->ihl_offset_meq_32[0].mask, rest); + rest = ipa_write_32(attrib->ihl_offset_meq_32[0].value, rest); + num_ihl_offset_meq_32--; + } + + if (num_ihl_offset_meq_32) { + extra = ipa_write_8(attrib->ihl_offset_meq_32[1].offset, + extra); + + rest = ipa_write_32(attrib->ihl_offset_meq_32[1].mask, rest); + rest = ipa_write_32(attrib->ihl_offset_meq_32[1].value, rest); + num_ihl_offset_meq_32--; + } + + if (attrib->metadata_meq32_present) { + rest = ipa_write_32(attrib->metadata_meq32.mask, rest); + rest = ipa_write_32(attrib->metadata_meq32.value, rest); + } + + if (num_ihl_offset_range_16) { + extra = ipa_write_8(attrib->ihl_offset_range_16[0].offset, + extra); + + rest = ipa_write_16(attrib->ihl_offset_range_16[0].range_high, + rest); + rest = ipa_write_16(attrib->ihl_offset_range_16[0].range_low, + rest); + num_ihl_offset_range_16--; + } + + if (num_ihl_offset_range_16) { + extra = ipa_write_8(attrib->ihl_offset_range_16[1].offset, + extra); + + rest = ipa_write_16(attrib->ihl_offset_range_16[1].range_high, + rest); + rest = ipa_write_16(attrib->ihl_offset_range_16[1].range_low, + rest); + num_ihl_offset_range_16--; + } + + if (attrib->ihl_offset_eq_32_present) { + extra = ipa_write_8(attrib->ihl_offset_eq_32.offset, extra); + rest = ipa_write_32(attrib->ihl_offset_eq_32.value, rest); + } + + if (attrib->ihl_offset_eq_16_present) { + extra = ipa_write_8(attrib->ihl_offset_eq_16.offset, extra); + rest = ipa_write_16(attrib->ihl_offset_eq_16.value, rest); + rest = ipa_write_16(0, rest); + } + + if (attrib->fl_eq_present) + rest = ipa_write_32(attrib->fl_eq & 0xFFFFF, rest); + + if (extra) + extra = ipa_pad_to_64(extra); + rest = ipa_pad_to_64(rest); + *buf = rest; + + return 0; +} + +static int ipa_fltrt_generate_hw_rule_bdy_from_eq_5_5( + const struct ipa_ipfltri_rule_eq *attrib, u8 **buf, bool ext_hdr) +{ + uint8_t num_offset_meq_32 = attrib->num_offset_meq_32; + uint8_t num_ihl_offset_range_16 = attrib->num_ihl_offset_range_16; + uint8_t num_ihl_offset_meq_32 = attrib->num_ihl_offset_meq_32; + uint8_t num_offset_meq_128 = attrib->num_offset_meq_128; + int i; + int extra_bytes; + u8 *extra; + u8 *rest; + + extra_bytes = ipa_fltrt_calc_extra_wrd_bytes(attrib); + /* only 3 eq does not have extra word param, 13 out of 16 is the number + * of equations that needs extra word param + */ + if (extra_bytes > 13) { + IPAHAL_ERR_RL("too much extra bytes\n"); + return -EPERM; + } else if (extra_bytes > IPA3_0_HW_TBL_HDR_WIDTH) { + /* two extra words */ + extra = *buf; + rest = *buf + IPA3_0_HW_TBL_HDR_WIDTH * 2 - ext_hdr * 2; + } else if (extra_bytes > 0) { + /* single exra word */ + extra = *buf; + /* With ext_hdr, 2 bytes are already occupied. */ + if (ext_hdr && extra_bytes > (IPA3_0_HW_TBL_HDR_WIDTH - 2)) + rest = *buf + IPA3_0_HW_TBL_HDR_WIDTH * 2 - ext_hdr * 2; + else + rest = *buf + IPA3_0_HW_TBL_HDR_WIDTH - ext_hdr * 2; + } else { + /* no extra words */ + extra = ext_hdr ? *buf : NULL; + rest = *buf - ext_hdr * 2 + ext_hdr * IPA3_0_HW_TBL_HDR_WIDTH; + } + + /* + * tos_eq_present field has two meanings: + * tos equation for IPA ver < 4.5 (as the field name reveals) + * pure_ack equation for IPA ver >= 4.5 + * In both cases it needs one extra word. + */ + if (attrib->tos_eq_present) { + if (IPA_IS_RULE_EQ_VALID(IPA_IS_PURE_ACK)) { + extra = ipa_write_8(0, extra); + } else if (IPA_IS_RULE_EQ_VALID(IPA_TOS_EQ)) { + extra = ipa_write_8(attrib->tos_eq, extra); + } else { + IPAHAL_ERR("no support for pure_ack and tos eqs\n"); + return -EPERM; + } + } + + if (attrib->protocol_eq_present) + extra = ipa_write_8(attrib->protocol_eq, extra); + + if (attrib->tc_eq_present) + extra = ipa_write_8(attrib->tc_eq, extra); + + if (num_offset_meq_128) { + extra = ipa_write_8(attrib->offset_meq_128[0].offset, extra); + for (i = 0; i < 8; i++) + rest = ipa_write_8(attrib->offset_meq_128[0].mask[i], + rest); + for (i = 0; i < 8; i++) + rest = ipa_write_8(attrib->offset_meq_128[0].value[i], + rest); + for (i = 8; i < 16; i++) + rest = ipa_write_8(attrib->offset_meq_128[0].mask[i], + rest); + for (i = 8; i < 16; i++) + rest = ipa_write_8(attrib->offset_meq_128[0].value[i], + rest); + num_offset_meq_128--; + } + + if (num_offset_meq_128) { + extra = ipa_write_8(attrib->offset_meq_128[1].offset, extra); + for (i = 0; i < 8; i++) + rest = ipa_write_8(attrib->offset_meq_128[1].mask[i], + rest); + for (i = 0; i < 8; i++) + rest = ipa_write_8(attrib->offset_meq_128[1].value[i], + rest); + for (i = 8; i < 16; i++) + rest = ipa_write_8(attrib->offset_meq_128[1].mask[i], + rest); + for (i = 8; i < 16; i++) + rest = ipa_write_8(attrib->offset_meq_128[1].value[i], + rest); + num_offset_meq_128--; + } + + if (num_offset_meq_32) { + extra = ipa_write_8(attrib->offset_meq_32[0].offset, extra); + rest = ipa_write_32(attrib->offset_meq_32[0].mask, rest); + rest = ipa_write_32(attrib->offset_meq_32[0].value, rest); + num_offset_meq_32--; + } + + if (num_offset_meq_32) { + extra = ipa_write_8(attrib->offset_meq_32[1].offset, extra); + rest = ipa_write_32(attrib->offset_meq_32[1].mask, rest); + rest = ipa_write_32(attrib->offset_meq_32[1].value, rest); + num_offset_meq_32--; + } + + if (num_ihl_offset_meq_32) { + extra = ipa_write_8(attrib->ihl_offset_meq_32[0].offset, + extra); + + rest = ipa_write_32(attrib->ihl_offset_meq_32[0].mask, rest); + rest = ipa_write_32(attrib->ihl_offset_meq_32[0].value, rest); + num_ihl_offset_meq_32--; + } + + if (num_ihl_offset_meq_32) { + extra = ipa_write_8(attrib->ihl_offset_meq_32[1].offset, + extra); + + rest = ipa_write_32(attrib->ihl_offset_meq_32[1].mask, rest); + rest = ipa_write_32(attrib->ihl_offset_meq_32[1].value, rest); + num_ihl_offset_meq_32--; + } + + if (attrib->metadata_meq32_present) { + rest = ipa_write_32(attrib->metadata_meq32.mask, rest); + rest = ipa_write_32(attrib->metadata_meq32.value, rest); + } + + if (num_ihl_offset_range_16) { + extra = ipa_write_8(attrib->ihl_offset_range_16[0].offset, + extra); + + rest = ipa_write_16(attrib->ihl_offset_range_16[0].range_high, + rest); + rest = ipa_write_16(attrib->ihl_offset_range_16[0].range_low, + rest); + num_ihl_offset_range_16--; + } + + if (num_ihl_offset_range_16) { + extra = ipa_write_8(attrib->ihl_offset_range_16[1].offset, + extra); + + rest = ipa_write_16(attrib->ihl_offset_range_16[1].range_high, + rest); + rest = ipa_write_16(attrib->ihl_offset_range_16[1].range_low, + rest); + num_ihl_offset_range_16--; + } + + if (attrib->ihl_offset_eq_32_present) { + extra = ipa_write_8(attrib->ihl_offset_eq_32.offset, extra); + rest = ipa_write_32(attrib->ihl_offset_eq_32.value, rest); + } + + if (attrib->ihl_offset_eq_16_present) { + extra = ipa_write_8(attrib->ihl_offset_eq_16.offset, extra); + rest = ipa_write_16(attrib->ihl_offset_eq_16.value, rest); + rest = ipa_write_16(0, rest); + } + + if (attrib->fl_eq_present) + rest = ipa_write_32(attrib->fl_eq & 0xFFFFF, rest); + + if (extra) + extra = ipa_pad_to_64(extra); + rest = ipa_pad_to_64(rest); + *buf = rest; + + return 0; +} + + +static void ipa_flt_generate_mac_addr_eq(struct ipa_ipfltri_rule_eq *eq_atrb, + u8 hdr_mac_addr_offset, const uint8_t mac_addr_mask[ETH_ALEN], + const uint8_t mac_addr[ETH_ALEN], u8 ofst_meq128) +{ + int i; + + eq_atrb->offset_meq_128[ofst_meq128].offset = hdr_mac_addr_offset; + + /* LSB MASK and ADDR */ + memset(eq_atrb->offset_meq_128[ofst_meq128].mask, 0, 8); + memset(eq_atrb->offset_meq_128[ofst_meq128].value, 0, 8); + + /* MSB MASK and ADDR */ + memset(eq_atrb->offset_meq_128[ofst_meq128].mask + 8, 0, 2); + for (i = 0; i <= 5; i++) + eq_atrb->offset_meq_128[ofst_meq128].mask[15 - i] = + mac_addr_mask[i]; + + memset(eq_atrb->offset_meq_128[ofst_meq128].value + 8, 0, 2); + for (i = 0; i <= 5; i++) + eq_atrb->offset_meq_128[ofst_meq128].value[15 - i] = + mac_addr[i]; +} + +static int ipa_flt_generate_mac_eq( + const struct ipa_rule_attrib *attrib, u16 *en_rule, u8 *ofst_meq128, + struct ipa_ipfltri_rule_eq *eq_atrb) +{ + u8 offset = 0; + const uint8_t *mac_addr = NULL; + const uint8_t *mac_addr_mask = NULL; + int i; + uint32_t attrib_mask; + + for (i = 0; i < hweight_long(IPA_MAC_FLT_BITS); i++) { + switch (i) { + case 0: + attrib_mask = IPA_FLT_MAC_DST_ADDR_ETHER_II; + break; + case 1: + attrib_mask = IPA_FLT_MAC_SRC_ADDR_ETHER_II; + break; + case 2: + attrib_mask = IPA_FLT_MAC_DST_ADDR_802_3; + break; + case 3: + attrib_mask = IPA_FLT_MAC_SRC_ADDR_802_3; + break; + case 4: + attrib_mask = IPA_FLT_MAC_DST_ADDR_802_1Q; + break; + case 5: + attrib_mask = IPA_FLT_MAC_SRC_ADDR_802_1Q; + break; + default: + return -EPERM; + } + + attrib_mask &= attrib->attrib_mask; + if (!attrib_mask) + continue; + + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ofst_meq128, *ofst_meq128)) { + IPAHAL_ERR("ran out of meq128 eq\n"); + return -EPERM; + } + + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ofst_meq128[*ofst_meq128]); + + ipa_fltrt_get_mac_data(attrib, attrib_mask, &offset, + &mac_addr, &mac_addr_mask); + + ipa_flt_generate_mac_addr_eq(eq_atrb, offset, + mac_addr_mask, mac_addr, + *ofst_meq128); + + (*ofst_meq128)++; + } + + return 0; +} + +static inline int ipa_flt_generat_vlan_eq( + const struct ipa_rule_attrib *attrib, u16 *en_rule, u8 *ofst_meq32, + struct ipa_ipfltri_rule_eq *eq_atrb) +{ + if (attrib->attrib_mask & IPA_FLT_VLAN_ID) { + uint32_t vlan_tag; + + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ofst_meq32, *ofst_meq32)) { + IPAHAL_ERR("ran out of meq32 eq\n"); + return -EPERM; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ofst_meq32[*ofst_meq32]); + /* -6 => offset of 802_1Q tag in L2 hdr */ + eq_atrb->offset_meq_32[*ofst_meq32].offset = -6; + /* filter vlan packets: 0x8100 TPID + required VLAN ID */ + vlan_tag = (0x8100 << 16) | (attrib->vlan_id & 0xFFF); + eq_atrb->offset_meq_32[*ofst_meq32].mask = 0xFFFF0FFF; + eq_atrb->offset_meq_32[*ofst_meq32].value = vlan_tag; + (*ofst_meq32)++; + } + + return 0; +} + +static int ipa_flt_generate_eq_ip4(enum ipa_ip_type ip, + const struct ipa_rule_attrib *attrib, + struct ipa_ipfltri_rule_eq *eq_atrb) +{ + u8 ofst_meq32 = 0; + u8 ihl_ofst_rng16 = 0; + u8 ihl_ofst_meq32 = 0; + u8 ofst_meq128 = 0; + u16 eq_bitmap = 0; + u16 *en_rule = &eq_bitmap; + bool tos_done = false; + + if (attrib->attrib_mask & IPA_FLT_IS_PURE_ACK) { + if (!IPA_IS_RULE_EQ_VALID(IPA_IS_PURE_ACK)) { + IPAHAL_ERR("is_pure_ack eq not supported\n"); + return -EPERM; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN(IPA_IS_PURE_ACK); + /* + * Starting IPA 4.5, where PURE ACK equation supported + * and TOS equation support removed, field tos_eq_present + * represent pure_ack presence. + */ + eq_atrb->tos_eq_present = 1; + eq_atrb->tos_eq = 0; + } + + if (attrib->attrib_mask & IPA_FLT_TOS && !tos_done) { + if (!IPA_IS_RULE_EQ_VALID(IPA_TOS_EQ)) { + IPAHAL_DBG("tos eq not supported\n"); + } else { + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN(IPA_TOS_EQ); + eq_atrb->tos_eq_present = 1; + eq_atrb->tos_eq = attrib->u.v4.tos; + } + } + + if (attrib->attrib_mask & IPA_FLT_PROTOCOL) { + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN(IPA_PROTOCOL_EQ); + eq_atrb->protocol_eq_present = 1; + eq_atrb->protocol_eq = attrib->u.v4.protocol; + } + + if (attrib->attrib_mask & IPA_MAC_FLT_BITS) { + if (ipa_flt_generate_mac_eq(attrib, en_rule, + &ofst_meq128, eq_atrb)) + return -EPERM; + } + + if (attrib->attrib_mask & IPA_FLT_MAC_DST_ADDR_L2TP) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ihl_ofst_meq32, + ihl_ofst_meq32) || IPA_IS_RAN_OUT_OF_EQ( + ipa3_0_ihl_ofst_meq32, ihl_ofst_meq32 + 1)) { + IPAHAL_ERR("ran out of ihl_meq32 eq\n"); + return -EPERM; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ihl_ofst_meq32[ihl_ofst_meq32]); + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ihl_ofst_meq32[ihl_ofst_meq32 + 1]); + /* populate the first ihl meq 32 eq */ + eq_atrb->ihl_offset_meq_32[ihl_ofst_meq32].offset = 8; + eq_atrb->ihl_offset_meq_32[ihl_ofst_meq32].mask = + (attrib->dst_mac_addr_mask[3] & 0xFF) | + ((attrib->dst_mac_addr_mask[2] << 8) & 0xFF00) | + ((attrib->dst_mac_addr_mask[1] << 16) & 0xFF0000) | + ((attrib->dst_mac_addr_mask[0] << 24) & 0xFF000000); + eq_atrb->ihl_offset_meq_32[ihl_ofst_meq32].value = + (attrib->dst_mac_addr[3] & 0xFF) | + ((attrib->dst_mac_addr[2] << 8) & 0xFF00) | + ((attrib->dst_mac_addr[1] << 16) & 0xFF0000) | + ((attrib->dst_mac_addr[0] << 24) & 0xFF000000); + /* populate the second ihl meq 32 eq */ + eq_atrb->ihl_offset_meq_32[ihl_ofst_meq32 + 1].offset = 12; + eq_atrb->ihl_offset_meq_32[ihl_ofst_meq32 + 1].mask = + ((attrib->dst_mac_addr_mask[5] << 16) & 0xFF0000) | + ((attrib->dst_mac_addr_mask[4] << 24) & 0xFF000000); + eq_atrb->ihl_offset_meq_32[ihl_ofst_meq32 + 1].value = + ((attrib->dst_mac_addr[5] << 16) & 0xFF0000) | + ((attrib->dst_mac_addr[4] << 24) & 0xFF000000); + ihl_ofst_meq32 += 2; + } + + if (attrib->attrib_mask & IPA_FLT_TCP_SYN) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ihl_ofst_meq32, + ihl_ofst_meq32)) { + IPAHAL_ERR("ran out of ihl_meq32 eq\n"); + return -EPERM; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ihl_ofst_meq32[ihl_ofst_meq32]); + /* 12 => offset of SYN after v4 header */ + eq_atrb->ihl_offset_meq_32[ihl_ofst_meq32].offset = 12; + eq_atrb->ihl_offset_meq_32[ihl_ofst_meq32].mask = 0x20000; + eq_atrb->ihl_offset_meq_32[ihl_ofst_meq32].value = 0x20000; + ihl_ofst_meq32++; + } + + if (attrib->attrib_mask & IPA_FLT_TOS_MASKED) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ofst_meq32, ofst_meq32)) { + IPAHAL_ERR("ran out of meq32 eq\n"); + return -EPERM; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ofst_meq32[ofst_meq32]); + eq_atrb->offset_meq_32[ofst_meq32].offset = 0; + eq_atrb->offset_meq_32[ofst_meq32].mask = + attrib->tos_mask << 16; + eq_atrb->offset_meq_32[ofst_meq32].value = + attrib->tos_value << 16; + ofst_meq32++; + } + + if (attrib->attrib_mask & IPA_FLT_SRC_ADDR) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ofst_meq32, ofst_meq32)) { + IPAHAL_ERR("ran out of meq32 eq\n"); + return -EPERM; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ofst_meq32[ofst_meq32]); + eq_atrb->offset_meq_32[ofst_meq32].offset = 12; + eq_atrb->offset_meq_32[ofst_meq32].mask = + attrib->u.v4.src_addr_mask; + eq_atrb->offset_meq_32[ofst_meq32].value = + attrib->u.v4.src_addr; + ofst_meq32++; + } + + if (attrib->attrib_mask & IPA_FLT_DST_ADDR) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ofst_meq32, ofst_meq32)) { + IPAHAL_ERR("ran out of meq32 eq\n"); + return -EPERM; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ofst_meq32[ofst_meq32]); + eq_atrb->offset_meq_32[ofst_meq32].offset = 16; + eq_atrb->offset_meq_32[ofst_meq32].mask = + attrib->u.v4.dst_addr_mask; + eq_atrb->offset_meq_32[ofst_meq32].value = + attrib->u.v4.dst_addr; + ofst_meq32++; + } + + if (attrib->attrib_mask & IPA_FLT_MAC_ETHER_TYPE) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ofst_meq32, ofst_meq32)) { + IPAHAL_ERR("ran out of meq32 eq\n"); + return -EPERM; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ofst_meq32[ofst_meq32]); + eq_atrb->offset_meq_32[ofst_meq32].offset = -2; + eq_atrb->offset_meq_32[ofst_meq32].mask = + htons(attrib->ether_type); + eq_atrb->offset_meq_32[ofst_meq32].value = + htons(attrib->ether_type); + ofst_meq32++; + } + + if (attrib->attrib_mask & IPA_FLT_TOS && !tos_done) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ofst_meq32, ofst_meq32)) { + IPAHAL_DBG("ran out of meq32 eq\n"); + } else { + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ofst_meq32[ofst_meq32]); + /* + * offset 0 => Take the first word. + * offset of TOS in v4 header is 1 + */ + eq_atrb->offset_meq_32[ofst_meq32].offset = 0; + eq_atrb->offset_meq_32[ofst_meq32].mask = + 0xFF << 16; + eq_atrb->offset_meq_32[ofst_meq32].value = + attrib->u.v4.tos << 16; + ofst_meq32++; + tos_done = true; + } + } + + if (ipa_flt_generat_vlan_eq(attrib, en_rule, &ofst_meq32, eq_atrb)) + return -EPERM; + + if (attrib->attrib_mask & IPA_FLT_TYPE) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ihl_ofst_meq32, + ihl_ofst_meq32)) { + IPAHAL_ERR("ran out of ihl_meq32 eq\n"); + return -EPERM; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ihl_ofst_meq32[ihl_ofst_meq32]); + eq_atrb->ihl_offset_meq_32[ihl_ofst_meq32].offset = 0; + eq_atrb->ihl_offset_meq_32[ihl_ofst_meq32].mask = 0xFF; + eq_atrb->ihl_offset_meq_32[ihl_ofst_meq32].value = + attrib->type; + ihl_ofst_meq32++; + } + + if (attrib->attrib_mask & IPA_FLT_CODE) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ihl_ofst_meq32, + ihl_ofst_meq32)) { + IPAHAL_ERR("ran out of ihl_meq32 eq\n"); + return -EPERM; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ihl_ofst_meq32[ihl_ofst_meq32]); + eq_atrb->ihl_offset_meq_32[ihl_ofst_meq32].offset = 1; + eq_atrb->ihl_offset_meq_32[ihl_ofst_meq32].mask = 0xFF; + eq_atrb->ihl_offset_meq_32[ihl_ofst_meq32].value = + attrib->code; + ihl_ofst_meq32++; + } + + if (attrib->attrib_mask & IPA_FLT_SPI) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ihl_ofst_meq32, + ihl_ofst_meq32)) { + IPAHAL_ERR("ran out of ihl_meq32 eq\n"); + return -EPERM; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ihl_ofst_meq32[ihl_ofst_meq32]); + eq_atrb->ihl_offset_meq_32[ihl_ofst_meq32].offset = 0; + eq_atrb->ihl_offset_meq_32[ihl_ofst_meq32].mask = + 0xFFFFFFFF; + eq_atrb->ihl_offset_meq_32[ihl_ofst_meq32].value = + attrib->spi; + ihl_ofst_meq32++; + } + + if (attrib->attrib_mask & IPA_FLT_TOS && !tos_done) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ihl_ofst_meq32, + ihl_ofst_meq32)) { + IPAHAL_DBG("ran out of ihl_meq32 eq\n"); + } else { + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ihl_ofst_meq32[ihl_ofst_meq32]); + /* + * 0 => Take the first word. offset of TOS in + * v4 header is 1. MSB bit asserted at IHL means + * to ignore packet IHL and do offset inside IPA header + */ + eq_atrb->ihl_offset_meq_32[ihl_ofst_meq32].offset = + 0x80; + eq_atrb->ihl_offset_meq_32[ihl_ofst_meq32].mask = + 0xFF << 16; + eq_atrb->ihl_offset_meq_32[ihl_ofst_meq32].value = + attrib->u.v4.tos << 16; + ihl_ofst_meq32++; + tos_done = true; + } + } + + if (attrib->attrib_mask & IPA_FLT_META_DATA) { + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + IPA_METADATA_COMPARE); + eq_atrb->metadata_meq32_present = 1; + eq_atrb->metadata_meq32.offset = 0; + eq_atrb->metadata_meq32.mask = attrib->meta_data_mask; + eq_atrb->metadata_meq32.value = attrib->meta_data; + } + + if (attrib->attrib_mask & IPA_FLT_SRC_PORT_RANGE) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ihl_ofst_rng16, + ihl_ofst_rng16)) { + IPAHAL_ERR("ran out of ihl_rng16 eq\n"); + return -EPERM; + } + if (attrib->src_port_hi < attrib->src_port_lo) { + IPAHAL_ERR("bad src port range param\n"); + return -EPERM; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ihl_ofst_rng16[ihl_ofst_rng16]); + eq_atrb->ihl_offset_range_16[ihl_ofst_rng16].offset = 0; + eq_atrb->ihl_offset_range_16[ihl_ofst_rng16].range_low + = attrib->src_port_lo; + eq_atrb->ihl_offset_range_16[ihl_ofst_rng16].range_high + = attrib->src_port_hi; + ihl_ofst_rng16++; + } + + if (attrib->attrib_mask & IPA_FLT_DST_PORT_RANGE) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ihl_ofst_rng16, + ihl_ofst_rng16)) { + IPAHAL_ERR("ran out of ihl_rng16 eq\n"); + return -EPERM; + } + if (attrib->dst_port_hi < attrib->dst_port_lo) { + IPAHAL_ERR("bad dst port range param\n"); + return -EPERM; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ihl_ofst_rng16[ihl_ofst_rng16]); + eq_atrb->ihl_offset_range_16[ihl_ofst_rng16].offset = 2; + eq_atrb->ihl_offset_range_16[ihl_ofst_rng16].range_low + = attrib->dst_port_lo; + eq_atrb->ihl_offset_range_16[ihl_ofst_rng16].range_high + = attrib->dst_port_hi; + ihl_ofst_rng16++; + } + + if (attrib->attrib_mask & IPA_FLT_SRC_PORT) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ihl_ofst_rng16, + ihl_ofst_rng16)) { + IPAHAL_ERR("ran out of ihl_rng16 eq\n"); + return -EPERM; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ihl_ofst_rng16[ihl_ofst_rng16]); + eq_atrb->ihl_offset_range_16[ihl_ofst_rng16].offset = 0; + eq_atrb->ihl_offset_range_16[ihl_ofst_rng16].range_low + = attrib->src_port; + eq_atrb->ihl_offset_range_16[ihl_ofst_rng16].range_high + = attrib->src_port; + ihl_ofst_rng16++; + } + + if (attrib->attrib_mask & IPA_FLT_DST_PORT) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ihl_ofst_rng16, + ihl_ofst_rng16)) { + IPAHAL_ERR("ran out of ihl_rng16 eq\n"); + return -EPERM; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ihl_ofst_rng16[ihl_ofst_rng16]); + eq_atrb->ihl_offset_range_16[ihl_ofst_rng16].offset = 2; + eq_atrb->ihl_offset_range_16[ihl_ofst_rng16].range_low + = attrib->dst_port; + eq_atrb->ihl_offset_range_16[ihl_ofst_rng16].range_high + = attrib->dst_port; + ihl_ofst_rng16++; + } + + if (attrib->attrib_mask & IPA_FLT_FRAGMENT) { + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN(IPA_IS_FRAG); + eq_atrb->ipv4_frag_eq_present = 1; + } + + if (attrib->attrib_mask & IPA_FLT_TOS && !tos_done) { + IPAHAL_ERR("could not find equation for tos\n"); + return -EPERM; + } + + eq_atrb->rule_eq_bitmap = *en_rule; + eq_atrb->num_offset_meq_32 = ofst_meq32; + eq_atrb->num_ihl_offset_range_16 = ihl_ofst_rng16; + eq_atrb->num_ihl_offset_meq_32 = ihl_ofst_meq32; + eq_atrb->num_offset_meq_128 = ofst_meq128; + + return 0; +} + +static int ipa_flt_generate_eq_ip6(enum ipa_ip_type ip, + const struct ipa_rule_attrib *attrib, + struct ipa_ipfltri_rule_eq *eq_atrb) +{ + u8 ofst_meq32 = 0; + u8 ihl_ofst_rng16 = 0; + u8 ihl_ofst_meq32 = 0; + u8 ofst_meq128 = 0; + u16 eq_bitmap = 0; + u16 *en_rule = &eq_bitmap; + + if (attrib->attrib_mask & IPA_FLT_IS_PURE_ACK) { + if (!IPA_IS_RULE_EQ_VALID(IPA_IS_PURE_ACK)) { + IPAHAL_ERR("is_pure_ack eq not supported\n"); + return -EPERM; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN(IPA_IS_PURE_ACK); + /* + * Starting IPA 4.5, where PURE ACK equation supported + * and TOS equation support removed, field tos_eq_present + * represent pure_ack presenence. + */ + eq_atrb->tos_eq_present = 1; + eq_atrb->tos_eq = 0; + } + + if (attrib->attrib_mask & IPA_FLT_NEXT_HDR) { + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + IPA_PROTOCOL_EQ); + eq_atrb->protocol_eq_present = 1; + eq_atrb->protocol_eq = attrib->u.v6.next_hdr; + } + + if (attrib->attrib_mask & IPA_FLT_TC) { + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + IPA_TC_EQ); + eq_atrb->tc_eq_present = 1; + eq_atrb->tc_eq = attrib->u.v6.tc; + } + + if (attrib->attrib_mask & IPA_FLT_SRC_ADDR) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ofst_meq128, ofst_meq128)) { + IPAHAL_ERR_RL("ran out of meq128 eq\n"); + return -EPERM; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ofst_meq128[ofst_meq128]); + /* use the same word order as in ipa v2 */ + eq_atrb->offset_meq_128[ofst_meq128].offset = 8; + *(u32 *)(eq_atrb->offset_meq_128[ofst_meq128].mask + 0) + = attrib->u.v6.src_addr_mask[0]; + *(u32 *)(eq_atrb->offset_meq_128[ofst_meq128].mask + 4) + = attrib->u.v6.src_addr_mask[1]; + *(u32 *)(eq_atrb->offset_meq_128[ofst_meq128].mask + 8) + = attrib->u.v6.src_addr_mask[2]; + *(u32 *)(eq_atrb->offset_meq_128[ofst_meq128].mask + 12) + = attrib->u.v6.src_addr_mask[3]; + *(u32 *)(eq_atrb->offset_meq_128[ofst_meq128].value + 0) + = attrib->u.v6.src_addr[0]; + *(u32 *)(eq_atrb->offset_meq_128[ofst_meq128].value + 4) + = attrib->u.v6.src_addr[1]; + *(u32 *)(eq_atrb->offset_meq_128[ofst_meq128].value + 8) + = attrib->u.v6.src_addr[2]; + *(u32 *)(eq_atrb->offset_meq_128[ofst_meq128].value + + 12) = attrib->u.v6.src_addr[3]; + ofst_meq128++; + } + + if (attrib->attrib_mask & IPA_FLT_DST_ADDR) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ofst_meq128, ofst_meq128)) { + IPAHAL_ERR_RL("ran out of meq128 eq\n"); + return -EPERM; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ofst_meq128[ofst_meq128]); + eq_atrb->offset_meq_128[ofst_meq128].offset = 24; + /* use the same word order as in ipa v2 */ + *(u32 *)(eq_atrb->offset_meq_128[ofst_meq128].mask + 0) + = attrib->u.v6.dst_addr_mask[0]; + *(u32 *)(eq_atrb->offset_meq_128[ofst_meq128].mask + 4) + = attrib->u.v6.dst_addr_mask[1]; + *(u32 *)(eq_atrb->offset_meq_128[ofst_meq128].mask + 8) + = attrib->u.v6.dst_addr_mask[2]; + *(u32 *)(eq_atrb->offset_meq_128[ofst_meq128].mask + 12) + = attrib->u.v6.dst_addr_mask[3]; + *(u32 *)(eq_atrb->offset_meq_128[ofst_meq128].value + 0) + = attrib->u.v6.dst_addr[0]; + *(u32 *)(eq_atrb->offset_meq_128[ofst_meq128].value + 4) + = attrib->u.v6.dst_addr[1]; + *(u32 *)(eq_atrb->offset_meq_128[ofst_meq128].value + 8) + = attrib->u.v6.dst_addr[2]; + *(u32 *)(eq_atrb->offset_meq_128[ofst_meq128].value + + 12) = attrib->u.v6.dst_addr[3]; + ofst_meq128++; + } + + if (attrib->attrib_mask & IPA_FLT_TOS_MASKED) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ofst_meq128, ofst_meq128)) { + IPAHAL_ERR_RL("ran out of meq128 eq\n"); + return -EPERM; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ofst_meq128[ofst_meq128]); + eq_atrb->offset_meq_128[ofst_meq128].offset = 0; + memset(eq_atrb->offset_meq_128[ofst_meq128].mask, 0, 12); + *(u32 *)(eq_atrb->offset_meq_128[ofst_meq128].mask + 12) + = attrib->tos_mask << 20; + memset(eq_atrb->offset_meq_128[ofst_meq128].value, 0, 12); + *(u32 *)(eq_atrb->offset_meq_128[ofst_meq128].value + + 12) = attrib->tos_value << 20; + ofst_meq128++; + } + + if (attrib->attrib_mask & IPA_MAC_FLT_BITS) { + if (ipa_flt_generate_mac_eq(attrib, en_rule, + &ofst_meq128, eq_atrb)) + return -EPERM; + } + + if (attrib->attrib_mask & IPA_FLT_MAC_DST_ADDR_L2TP) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ihl_ofst_meq32, + ihl_ofst_meq32) || IPA_IS_RAN_OUT_OF_EQ( + ipa3_0_ihl_ofst_meq32, ihl_ofst_meq32 + 1)) { + IPAHAL_ERR_RL("ran out of ihl_meq32 eq\n"); + return -EPERM; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ihl_ofst_meq32[ihl_ofst_meq32]); + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ihl_ofst_meq32[ihl_ofst_meq32 + 1]); + /* populate the first ihl meq 32 eq */ + eq_atrb->ihl_offset_meq_32[ihl_ofst_meq32].offset = 8; + eq_atrb->ihl_offset_meq_32[ihl_ofst_meq32].mask = + (attrib->dst_mac_addr_mask[3] & 0xFF) | + ((attrib->dst_mac_addr_mask[2] << 8) & 0xFF00) | + ((attrib->dst_mac_addr_mask[1] << 16) & 0xFF0000) | + ((attrib->dst_mac_addr_mask[0] << 24) & 0xFF000000); + eq_atrb->ihl_offset_meq_32[ihl_ofst_meq32].value = + (attrib->dst_mac_addr[3] & 0xFF) | + ((attrib->dst_mac_addr[2] << 8) & 0xFF00) | + ((attrib->dst_mac_addr[1] << 16) & 0xFF0000) | + ((attrib->dst_mac_addr[0] << 24) & 0xFF000000); + /* populate the second ihl meq 32 eq */ + eq_atrb->ihl_offset_meq_32[ihl_ofst_meq32 + 1].offset = 12; + eq_atrb->ihl_offset_meq_32[ihl_ofst_meq32 + 1].mask = + ((attrib->dst_mac_addr_mask[5] << 16) & 0xFF0000) | + ((attrib->dst_mac_addr_mask[4] << 24) & 0xFF000000); + eq_atrb->ihl_offset_meq_32[ihl_ofst_meq32 + 1].value = + ((attrib->dst_mac_addr[5] << 16) & 0xFF0000) | + ((attrib->dst_mac_addr[4] << 24) & 0xFF000000); + ihl_ofst_meq32 += 2; + } + + if (attrib->attrib_mask & IPA_FLT_TCP_SYN) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ihl_ofst_meq32, + ihl_ofst_meq32)) { + IPAHAL_ERR_RL("ran out of ihl_meq32 eq\n"); + return -EPERM; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ihl_ofst_meq32[ihl_ofst_meq32]); + /* 12 => offset of SYN after v4 header */ + eq_atrb->ihl_offset_meq_32[ihl_ofst_meq32].offset = 12; + eq_atrb->ihl_offset_meq_32[ihl_ofst_meq32].mask = 0x20000; + eq_atrb->ihl_offset_meq_32[ihl_ofst_meq32].value = 0x20000; + ihl_ofst_meq32++; + } + + if (attrib->attrib_mask & IPA_FLT_TCP_SYN_L2TP) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ihl_ofst_meq32, + ihl_ofst_meq32) || IPA_IS_RAN_OUT_OF_EQ( + ipa3_0_ihl_ofst_meq32, ihl_ofst_meq32 + 1)) { + IPAHAL_ERR_RL("ran out of ihl_meq32 eq\n"); + return -EPERM; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ihl_ofst_meq32[ihl_ofst_meq32]); + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ihl_ofst_meq32[ihl_ofst_meq32 + 1]); + + /* populate TCP protocol eq */ + if (attrib->ether_type == 0x0800) { + eq_atrb->ihl_offset_meq_32[ihl_ofst_meq32].offset = 30; + eq_atrb->ihl_offset_meq_32[ihl_ofst_meq32].mask = + 0xFF0000; + eq_atrb->ihl_offset_meq_32[ihl_ofst_meq32].value = + 0x60000; + } else { + eq_atrb->ihl_offset_meq_32[ihl_ofst_meq32].offset = 26; + eq_atrb->ihl_offset_meq_32[ihl_ofst_meq32].mask = + 0xFF00; + eq_atrb->ihl_offset_meq_32[ihl_ofst_meq32].value = + 0x600; + } + + /* populate TCP SYN eq */ + if (attrib->ether_type == 0x0800) { + eq_atrb->ihl_offset_meq_32[ihl_ofst_meq32].offset = 54; + eq_atrb->ihl_offset_meq_32[ihl_ofst_meq32].mask = + 0x20000; + eq_atrb->ihl_offset_meq_32[ihl_ofst_meq32].value = + 0x20000; + } else { + eq_atrb->ihl_offset_meq_32[ihl_ofst_meq32].offset = 74; + eq_atrb->ihl_offset_meq_32[ihl_ofst_meq32].mask = + 0x20000; + eq_atrb->ihl_offset_meq_32[ihl_ofst_meq32].value = + 0x20000; + } + ihl_ofst_meq32 += 2; + } + + if (attrib->attrib_mask & IPA_FLT_L2TP_INNER_IP_TYPE) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ihl_ofst_meq32, + ihl_ofst_meq32)) { + IPAHAL_ERR("ran out of ihl_meq32 eq\n"); + return -EPERM; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ihl_ofst_meq32[ihl_ofst_meq32]); + /* 22 => offset of inner IP type after v6 header */ + eq_atrb->ihl_offset_meq_32[ihl_ofst_meq32].offset = 22; + eq_atrb->ihl_offset_meq_32[ihl_ofst_meq32].mask = + 0xF0000000; + eq_atrb->ihl_offset_meq_32[ihl_ofst_meq32].value = + (u32)attrib->type << 24; + ihl_ofst_meq32++; + } + + if (attrib->attrib_mask & IPA_FLT_L2TP_INNER_IPV4_DST_ADDR) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ihl_ofst_meq32, + ihl_ofst_meq32)) { + IPAHAL_ERR("ran out of ihl_meq32 eq\n"); + return -EPERM; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ihl_ofst_meq32[ihl_ofst_meq32]); + /* 38 => offset of inner IPv4 addr */ + eq_atrb->ihl_offset_meq_32[ihl_ofst_meq32].offset = 38; + eq_atrb->ihl_offset_meq_32[ihl_ofst_meq32].mask = + attrib->u.v4.dst_addr_mask; + eq_atrb->ihl_offset_meq_32[ihl_ofst_meq32].value = + attrib->u.v4.dst_addr; + ihl_ofst_meq32++; + } + + if (attrib->attrib_mask & IPA_FLT_MAC_ETHER_TYPE) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ofst_meq32, ofst_meq32)) { + IPAHAL_ERR_RL("ran out of meq32 eq\n"); + return -EPERM; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ofst_meq32[ofst_meq32]); + eq_atrb->offset_meq_32[ofst_meq32].offset = -2; + eq_atrb->offset_meq_32[ofst_meq32].mask = + htons(attrib->ether_type); + eq_atrb->offset_meq_32[ofst_meq32].value = + htons(attrib->ether_type); + ofst_meq32++; + } + + if (ipa_flt_generat_vlan_eq(attrib, en_rule, &ofst_meq32, eq_atrb)) + return -EPERM; + + if (attrib->attrib_mask & IPA_FLT_TYPE) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ihl_ofst_meq32, + ihl_ofst_meq32)) { + IPAHAL_ERR_RL("ran out of ihl_meq32 eq\n"); + return -EPERM; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ihl_ofst_meq32[ihl_ofst_meq32]); + eq_atrb->ihl_offset_meq_32[ihl_ofst_meq32].offset = 0; + eq_atrb->ihl_offset_meq_32[ihl_ofst_meq32].mask = 0xFF; + eq_atrb->ihl_offset_meq_32[ihl_ofst_meq32].value = + attrib->type; + ihl_ofst_meq32++; + } + + if (attrib->attrib_mask & IPA_FLT_CODE) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ihl_ofst_meq32, + ihl_ofst_meq32)) { + IPAHAL_ERR_RL("ran out of ihl_meq32 eq\n"); + return -EPERM; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ihl_ofst_meq32[ihl_ofst_meq32]); + eq_atrb->ihl_offset_meq_32[ihl_ofst_meq32].offset = 1; + eq_atrb->ihl_offset_meq_32[ihl_ofst_meq32].mask = 0xFF; + eq_atrb->ihl_offset_meq_32[ihl_ofst_meq32].value = + attrib->code; + ihl_ofst_meq32++; + } + + if (attrib->attrib_mask & IPA_FLT_SPI) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ihl_ofst_meq32, + ihl_ofst_meq32)) { + IPAHAL_ERR_RL("ran out of ihl_meq32 eq\n"); + return -EPERM; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ihl_ofst_meq32[ihl_ofst_meq32]); + eq_atrb->ihl_offset_meq_32[ihl_ofst_meq32].offset = 0; + eq_atrb->ihl_offset_meq_32[ihl_ofst_meq32].mask = + 0xFFFFFFFF; + eq_atrb->ihl_offset_meq_32[ihl_ofst_meq32].value = + attrib->spi; + ihl_ofst_meq32++; + } + + if (attrib->attrib_mask & IPA_FLT_META_DATA) { + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + IPA_METADATA_COMPARE); + eq_atrb->metadata_meq32_present = 1; + eq_atrb->metadata_meq32.offset = 0; + eq_atrb->metadata_meq32.mask = attrib->meta_data_mask; + eq_atrb->metadata_meq32.value = attrib->meta_data; + } + + if (attrib->attrib_mask & IPA_FLT_SRC_PORT) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ihl_ofst_rng16, + ihl_ofst_rng16)) { + IPAHAL_ERR_RL("ran out of ihl_rng16 eq\n"); + return -EPERM; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ihl_ofst_rng16[ihl_ofst_rng16]); + eq_atrb->ihl_offset_range_16[ihl_ofst_rng16].offset = 0; + eq_atrb->ihl_offset_range_16[ihl_ofst_rng16].range_low + = attrib->src_port; + eq_atrb->ihl_offset_range_16[ihl_ofst_rng16].range_high + = attrib->src_port; + ihl_ofst_rng16++; + } + + if (attrib->attrib_mask & IPA_FLT_DST_PORT) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ihl_ofst_rng16, + ihl_ofst_rng16)) { + IPAHAL_ERR_RL("ran out of ihl_rng16 eq\n"); + return -EPERM; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ihl_ofst_rng16[ihl_ofst_rng16]); + eq_atrb->ihl_offset_range_16[ihl_ofst_rng16].offset = 2; + eq_atrb->ihl_offset_range_16[ihl_ofst_rng16].range_low + = attrib->dst_port; + eq_atrb->ihl_offset_range_16[ihl_ofst_rng16].range_high + = attrib->dst_port; + ihl_ofst_rng16++; + } + + if (attrib->attrib_mask & IPA_FLT_SRC_PORT_RANGE) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ihl_ofst_rng16, + ihl_ofst_rng16)) { + IPAHAL_ERR_RL("ran out of ihl_rng16 eq\n"); + return -EPERM; + } + if (attrib->src_port_hi < attrib->src_port_lo) { + IPAHAL_ERR_RL("bad src port range param\n"); + return -EPERM; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ihl_ofst_rng16[ihl_ofst_rng16]); + eq_atrb->ihl_offset_range_16[ihl_ofst_rng16].offset = 0; + eq_atrb->ihl_offset_range_16[ihl_ofst_rng16].range_low + = attrib->src_port_lo; + eq_atrb->ihl_offset_range_16[ihl_ofst_rng16].range_high + = attrib->src_port_hi; + ihl_ofst_rng16++; + } + + if (attrib->attrib_mask & IPA_FLT_DST_PORT_RANGE) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ihl_ofst_rng16, + ihl_ofst_rng16)) { + IPAHAL_ERR_RL("ran out of ihl_rng16 eq\n"); + return -EPERM; + } + if (attrib->dst_port_hi < attrib->dst_port_lo) { + IPAHAL_ERR_RL("bad dst port range param\n"); + return -EPERM; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ihl_ofst_rng16[ihl_ofst_rng16]); + eq_atrb->ihl_offset_range_16[ihl_ofst_rng16].offset = 2; + eq_atrb->ihl_offset_range_16[ihl_ofst_rng16].range_low + = attrib->dst_port_lo; + eq_atrb->ihl_offset_range_16[ihl_ofst_rng16].range_high + = attrib->dst_port_hi; + ihl_ofst_rng16++; + } + + if (attrib->attrib_mask & IPA_FLT_TCP_SYN_L2TP) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ihl_ofst_rng16, + ihl_ofst_rng16)) { + IPAHAL_ERR("ran out of ihl_rng16 eq\n"); + return -EPERM; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ihl_ofst_rng16[ihl_ofst_rng16]); + if (attrib->ether_type == 0x0800) { + eq_atrb->ihl_offset_range_16[ihl_ofst_rng16].offset + = 21; + eq_atrb->ihl_offset_range_16[ihl_ofst_rng16].range_low + = 0x0045; + eq_atrb->ihl_offset_range_16[ihl_ofst_rng16].range_high + = 0x0045; + } else { + eq_atrb->ihl_offset_range_16[ihl_ofst_rng16].offset = + 20; + eq_atrb->ihl_offset_range_16[ihl_ofst_rng16].range_low + = attrib->ether_type; + eq_atrb->ihl_offset_range_16[ihl_ofst_rng16].range_high + = attrib->ether_type; + } + ihl_ofst_rng16++; + } + + if (attrib->attrib_mask & IPA_FLT_TCP_SYN_L2TP) { + if (IPA_IS_RAN_OUT_OF_EQ(ipa3_0_ihl_ofst_rng16, + ihl_ofst_rng16)) { + IPAHAL_ERR_RL("ran out of ihl_rng16 eq\n"); + return -EPERM; + } + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + ipa3_0_ihl_ofst_rng16[ihl_ofst_rng16]); + if (attrib->ether_type == 0x0800) { + eq_atrb->ihl_offset_range_16[ihl_ofst_rng16].offset + = 21; + eq_atrb->ihl_offset_range_16[ihl_ofst_rng16].range_low + = 0x0045; + eq_atrb->ihl_offset_range_16[ihl_ofst_rng16].range_high + = 0x0045; + } else { + eq_atrb->ihl_offset_range_16[ihl_ofst_rng16].offset = + 20; + eq_atrb->ihl_offset_range_16[ihl_ofst_rng16].range_low + = attrib->ether_type; + eq_atrb->ihl_offset_range_16[ihl_ofst_rng16].range_high + = attrib->ether_type; + } + ihl_ofst_rng16++; + } + + if (attrib->attrib_mask & IPA_FLT_FLOW_LABEL) { + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN(IPA_FL_EQ); + eq_atrb->fl_eq_present = 1; + eq_atrb->fl_eq = attrib->u.v6.flow_label; + } + + if (attrib->attrib_mask & IPA_FLT_FRAGMENT) { + *en_rule |= IPA_GET_RULE_EQ_BIT_PTRN( + IPA_IS_FRAG); + eq_atrb->ipv4_frag_eq_present = 1; + } + + eq_atrb->rule_eq_bitmap = *en_rule; + eq_atrb->num_offset_meq_32 = ofst_meq32; + eq_atrb->num_ihl_offset_range_16 = ihl_ofst_rng16; + eq_atrb->num_ihl_offset_meq_32 = ihl_ofst_meq32; + eq_atrb->num_offset_meq_128 = ofst_meq128; + + return 0; +} + +static int ipa_fltrt_parse_hw_rule_eq(u8 *addr, u32 hdr_sz, + struct ipa_ipfltri_rule_eq *atrb, u32 *rule_size) +{ + u16 eq_bitmap; + int extra_bytes; + u8 *extra; + u8 *rest; + int i; + u8 dummy_extra_wrd; + + if (!addr || !atrb || !rule_size) { + IPAHAL_ERR("Input error: addr=%pK atrb=%pK rule_size=%pK\n", + addr, atrb, rule_size); + return -EINVAL; + } + + eq_bitmap = atrb->rule_eq_bitmap; + + IPAHAL_DBG_LOW("eq_bitmap=0x%x\n", eq_bitmap); + + if (IPA_IS_RULE_EQ_VALID(IPA_IS_PURE_ACK) && + (eq_bitmap & IPA_GET_RULE_EQ_BIT_PTRN(IPA_IS_PURE_ACK))) { + /* + * tos_eq_present field represents pure_ack when pure + * ack equation valid (started IPA 4.5). In this case + * tos equation should not be supported. + */ + atrb->tos_eq_present = true; + } + if (IPA_IS_RULE_EQ_VALID(IPA_TOS_EQ) && + (eq_bitmap & IPA_GET_RULE_EQ_BIT_PTRN(IPA_TOS_EQ))) { + atrb->tos_eq_present = true; + } + if (eq_bitmap & IPA_GET_RULE_EQ_BIT_PTRN(IPA_PROTOCOL_EQ)) + atrb->protocol_eq_present = true; + if (eq_bitmap & IPA_GET_RULE_EQ_BIT_PTRN(IPA_TC_EQ)) + atrb->tc_eq_present = true; + if (eq_bitmap & IPA_GET_RULE_EQ_BIT_PTRN(IPA_OFFSET_MEQ128_0)) + atrb->num_offset_meq_128++; + if (eq_bitmap & IPA_GET_RULE_EQ_BIT_PTRN(IPA_OFFSET_MEQ128_1)) + atrb->num_offset_meq_128++; + if (eq_bitmap & IPA_GET_RULE_EQ_BIT_PTRN(IPA_OFFSET_MEQ32_0)) + atrb->num_offset_meq_32++; + if (eq_bitmap & IPA_GET_RULE_EQ_BIT_PTRN(IPA_OFFSET_MEQ32_1)) + atrb->num_offset_meq_32++; + if (eq_bitmap & IPA_GET_RULE_EQ_BIT_PTRN(IPA_IHL_OFFSET_MEQ32_0)) + atrb->num_ihl_offset_meq_32++; + if (eq_bitmap & IPA_GET_RULE_EQ_BIT_PTRN(IPA_IHL_OFFSET_MEQ32_1)) + atrb->num_ihl_offset_meq_32++; + if (eq_bitmap & IPA_GET_RULE_EQ_BIT_PTRN(IPA_METADATA_COMPARE)) + atrb->metadata_meq32_present = true; + if (eq_bitmap & IPA_GET_RULE_EQ_BIT_PTRN(IPA_IHL_OFFSET_RANGE16_0)) + atrb->num_ihl_offset_range_16++; + if (eq_bitmap & IPA_GET_RULE_EQ_BIT_PTRN(IPA_IHL_OFFSET_RANGE16_1)) + atrb->num_ihl_offset_range_16++; + if (eq_bitmap & IPA_GET_RULE_EQ_BIT_PTRN(IPA_IHL_OFFSET_EQ_32)) + atrb->ihl_offset_eq_32_present = true; + if (eq_bitmap & IPA_GET_RULE_EQ_BIT_PTRN(IPA_IHL_OFFSET_EQ_16)) + atrb->ihl_offset_eq_16_present = true; + if (eq_bitmap & IPA_GET_RULE_EQ_BIT_PTRN(IPA_FL_EQ)) + atrb->fl_eq_present = true; + if (eq_bitmap & IPA_GET_RULE_EQ_BIT_PTRN(IPA_IS_FRAG)) + atrb->ipv4_frag_eq_present = true; + + extra_bytes = ipa_fltrt_calc_extra_wrd_bytes(atrb); + /* only 3 eq does not have extra word param, 13 out of 16 is the number + * of equations that needs extra word param + */ + if (extra_bytes > 13) { + IPAHAL_ERR("too much extra bytes\n"); + return -EPERM; + } else if (extra_bytes > IPA3_0_HW_TBL_HDR_WIDTH) { + /* two extra words */ + extra = addr + hdr_sz; + rest = extra + IPA3_0_HW_TBL_HDR_WIDTH * 2; + } else if (extra_bytes > 0) { + /* single extra word */ + extra = addr + hdr_sz; + rest = extra + IPA3_0_HW_TBL_HDR_WIDTH; + } else { + /* no extra words */ + dummy_extra_wrd = 0; + extra = &dummy_extra_wrd; + rest = addr + hdr_sz; + } + IPAHAL_DBG_LOW("addr=0x%pK extra=0x%pK rest=0x%pK\n", + addr, extra, rest); + + if (IPA_IS_RULE_EQ_VALID(IPA_TOS_EQ) && atrb->tos_eq_present) + atrb->tos_eq = *extra++; + if (IPA_IS_RULE_EQ_VALID(IPA_IS_PURE_ACK) && atrb->tos_eq_present) { + atrb->tos_eq = 0; + extra++; + } + if (atrb->protocol_eq_present) + atrb->protocol_eq = *extra++; + if (atrb->tc_eq_present) + atrb->tc_eq = *extra++; + + if (atrb->num_offset_meq_128 > 0) { + atrb->offset_meq_128[0].offset = *extra++; + for (i = 0; i < 8; i++) + atrb->offset_meq_128[0].mask[i] = *rest++; + for (i = 0; i < 8; i++) + atrb->offset_meq_128[0].value[i] = *rest++; + for (i = 8; i < 16; i++) + atrb->offset_meq_128[0].mask[i] = *rest++; + for (i = 8; i < 16; i++) + atrb->offset_meq_128[0].value[i] = *rest++; + } + if (atrb->num_offset_meq_128 > 1) { + atrb->offset_meq_128[1].offset = *extra++; + for (i = 0; i < 8; i++) + atrb->offset_meq_128[1].mask[i] = *rest++; + for (i = 0; i < 8; i++) + atrb->offset_meq_128[1].value[i] = *rest++; + for (i = 8; i < 16; i++) + atrb->offset_meq_128[1].mask[i] = *rest++; + for (i = 8; i < 16; i++) + atrb->offset_meq_128[1].value[i] = *rest++; + } + + if (atrb->num_offset_meq_32 > 0) { + atrb->offset_meq_32[0].offset = *extra++; + atrb->offset_meq_32[0].mask = *((u32 *)rest); + rest += 4; + atrb->offset_meq_32[0].value = *((u32 *)rest); + rest += 4; + } + if (atrb->num_offset_meq_32 > 1) { + atrb->offset_meq_32[1].offset = *extra++; + atrb->offset_meq_32[1].mask = *((u32 *)rest); + rest += 4; + atrb->offset_meq_32[1].value = *((u32 *)rest); + rest += 4; + } + + if (atrb->num_ihl_offset_meq_32 > 0) { + atrb->ihl_offset_meq_32[0].offset = *extra++; + atrb->ihl_offset_meq_32[0].mask = *((u32 *)rest); + rest += 4; + atrb->ihl_offset_meq_32[0].value = *((u32 *)rest); + rest += 4; + } + if (atrb->num_ihl_offset_meq_32 > 1) { + atrb->ihl_offset_meq_32[1].offset = *extra++; + atrb->ihl_offset_meq_32[1].mask = *((u32 *)rest); + rest += 4; + atrb->ihl_offset_meq_32[1].value = *((u32 *)rest); + rest += 4; + } + + if (atrb->metadata_meq32_present) { + atrb->metadata_meq32.mask = *((u32 *)rest); + rest += 4; + atrb->metadata_meq32.value = *((u32 *)rest); + rest += 4; + } + + if (atrb->num_ihl_offset_range_16 > 0) { + atrb->ihl_offset_range_16[0].offset = *extra++; + atrb->ihl_offset_range_16[0].range_high = *((u16 *)rest); + rest += 2; + atrb->ihl_offset_range_16[0].range_low = *((u16 *)rest); + rest += 2; + } + if (atrb->num_ihl_offset_range_16 > 1) { + atrb->ihl_offset_range_16[1].offset = *extra++; + atrb->ihl_offset_range_16[1].range_high = *((u16 *)rest); + rest += 2; + atrb->ihl_offset_range_16[1].range_low = *((u16 *)rest); + rest += 2; + } + + if (atrb->ihl_offset_eq_32_present) { + atrb->ihl_offset_eq_32.offset = *extra++; + atrb->ihl_offset_eq_32.value = *((u32 *)rest); + rest += 4; + } + + if (atrb->ihl_offset_eq_16_present) { + atrb->ihl_offset_eq_16.offset = *extra++; + atrb->ihl_offset_eq_16.value = *((u16 *)rest); + rest += 4; + } + + if (atrb->fl_eq_present) { + atrb->fl_eq = *((u32 *)rest); + atrb->fl_eq &= 0xfffff; + rest += 4; + } + + IPAHAL_DBG_LOW("before rule alignment rest=0x%pK\n", rest); + rest = (u8 *)(((unsigned long)rest + IPA3_0_HW_RULE_START_ALIGNMENT) & + ~IPA3_0_HW_RULE_START_ALIGNMENT); + IPAHAL_DBG_LOW("after rule alignment rest=0x%pK\n", rest); + + *rule_size = rest - addr; + IPAHAL_DBG_LOW("rule_size=0x%x\n", *rule_size); + + return 0; +} + +static int ipa_rt_parse_hw_rule(u8 *addr, struct ipahal_rt_rule_entry *rule) +{ + struct ipa3_0_rt_rule_hw_hdr *rule_hdr; + struct ipa_ipfltri_rule_eq *atrb; + + IPAHAL_DBG_LOW("Entry\n"); + + rule_hdr = (struct ipa3_0_rt_rule_hw_hdr *)addr; + atrb = &rule->eq_attrib; + + IPAHAL_DBG_LOW("read hdr 0x%llx\n", rule_hdr->u.word); + + if (rule_hdr->u.word == 0) { + /* table terminator - empty table */ + rule->rule_size = 0; + return 0; + } + + rule->dst_pipe_idx = rule_hdr->u.hdr.pipe_dest_idx; + if (rule_hdr->u.hdr.proc_ctx) { + rule->hdr_type = IPAHAL_RT_RULE_HDR_PROC_CTX; + rule->hdr_ofst = (rule_hdr->u.hdr.hdr_offset) << 5; + } else { + rule->hdr_type = IPAHAL_RT_RULE_HDR_RAW; + rule->hdr_ofst = (rule_hdr->u.hdr.hdr_offset) << 2; + } + rule->hdr_lcl = !rule_hdr->u.hdr.system; + + rule->priority = rule_hdr->u.hdr.priority; + rule->retain_hdr = rule_hdr->u.hdr.retain_hdr; + rule->id = rule_hdr->u.hdr.rule_id; + + atrb->rule_eq_bitmap = rule_hdr->u.hdr.en_rule; + return ipa_fltrt_parse_hw_rule_eq(addr, sizeof(*rule_hdr), + atrb, &rule->rule_size); +} + +static int ipa_rt_parse_hw_rule_ipav4_5(u8 *addr, + struct ipahal_rt_rule_entry *rule) +{ + struct ipa4_5_rt_rule_hw_hdr *rule_hdr; + struct ipa_ipfltri_rule_eq *atrb; + + IPAHAL_DBG_LOW("Entry\n"); + + rule_hdr = (struct ipa4_5_rt_rule_hw_hdr *)addr; + atrb = &rule->eq_attrib; + + IPAHAL_DBG_LOW("read hdr 0x%llx\n", rule_hdr->u.word); + + if (rule_hdr->u.word == 0) { + /* table terminator - empty table */ + rule->rule_size = 0; + return 0; + } + + rule->dst_pipe_idx = rule_hdr->u.hdr.pipe_dest_idx; + if (rule_hdr->u.hdr.proc_ctx) { + rule->hdr_type = IPAHAL_RT_RULE_HDR_PROC_CTX; + rule->hdr_ofst = (rule_hdr->u.hdr.hdr_offset) << 5; + } else { + rule->hdr_type = IPAHAL_RT_RULE_HDR_RAW; + rule->hdr_ofst = (rule_hdr->u.hdr.hdr_offset) << 2; + } + rule->hdr_lcl = !rule_hdr->u.hdr.system; + + rule->priority = rule_hdr->u.hdr.priority; + rule->retain_hdr = rule_hdr->u.hdr.retain_hdr; + rule->cnt_idx = rule_hdr->u.hdr.stats_cnt_idx_lsb | + (rule_hdr->u.hdr.stats_cnt_idx_msb) << 6; + rule->id = rule_hdr->u.hdr.rule_id; + + atrb->rule_eq_bitmap = rule_hdr->u.hdr.en_rule; + return ipa_fltrt_parse_hw_rule_eq(addr, sizeof(*rule_hdr), + atrb, &rule->rule_size); +} + +static int ipa_rt_parse_hw_rule_ipav5_0(u8 *addr, + struct ipahal_rt_rule_entry *rule) +{ + struct ipa5_0_rt_rule_hw_hdr *rule_hdr; + struct ipa_ipfltri_rule_eq *atrb; + + IPAHAL_DBG_LOW("Entry\n"); + + rule_hdr = (struct ipa5_0_rt_rule_hw_hdr *)addr; + atrb = &rule->eq_attrib; + + IPAHAL_DBG_LOW("read hdr 0x%llx\n", rule_hdr->u.word); + + if (rule_hdr->u.word == 0) { + /* table terminator - empty table */ + rule->rule_size = 0; + return 0; + } + + rule->dst_pipe_idx = rule_hdr->u.hdr.pipe_dest_idx; + if (rule_hdr->u.hdr.proc_ctx) { + rule->hdr_type = IPAHAL_RT_RULE_HDR_PROC_CTX; + rule->hdr_ofst = (rule_hdr->u.hdr.hdr_offset) << 5; + } else { + rule->hdr_type = IPAHAL_RT_RULE_HDR_RAW; + rule->hdr_ofst = (rule_hdr->u.hdr.hdr_offset) << 2; + } + rule->hdr_lcl = !rule_hdr->u.hdr.system; + + rule->priority = rule_hdr->u.hdr.priority; + rule->retain_hdr = rule_hdr->u.hdr.retain_hdr; + rule->cnt_idx = rule_hdr->u.hdr.stats_cnt_idx; + rule->id = rule_hdr->u.hdr.rule_id; + rule->close_aggr_irq_mod = rule_hdr->u.hdr.close_aggr_irq_mod; + + atrb->rule_eq_bitmap = rule_hdr->u.hdr.en_rule; + return ipa_fltrt_parse_hw_rule_eq(addr, sizeof(*rule_hdr), + atrb, &rule->rule_size); +} + +static int ipa_rt_parse_hw_rule_ipav5_5(u8 *addr, + struct ipahal_rt_rule_entry *rule) +{ + struct ipa5_5_rt_rule_hw_hdr *rule_hdr; + struct ipa5_5_rt_rule_hw_hdr_ext *ext_hdr; + struct ipa_ipfltri_rule_eq *atrb; + u32 ext_hdr_sz = 0; + + IPAHAL_DBG_LOW("Entry\n"); + + rule_hdr = (struct ipa5_5_rt_rule_hw_hdr *)addr; + atrb = &rule->eq_attrib; + + IPAHAL_DBG_LOW("read hdr 0x%llx\n", rule_hdr->u.word); + + if (rule_hdr->u.word == 0) { + /* table terminator - empty table */ + rule->rule_size = 0; + return 0; + } + + rule->dst_pipe_idx = rule_hdr->u.hdr.pipe_dest_idx; + if (rule_hdr->u.hdr.proc_ctx) { + rule->hdr_type = IPAHAL_RT_RULE_HDR_PROC_CTX; + rule->hdr_ofst = (rule_hdr->u.hdr.hdr_offset) << 5; + } else { + rule->hdr_type = IPAHAL_RT_RULE_HDR_RAW; + rule->hdr_ofst = (rule_hdr->u.hdr.hdr_offset) << 2; + } + rule->hdr_lcl = !rule_hdr->u.hdr.system; + + rule->priority = rule_hdr->u.hdr.priority; + rule->retain_hdr = rule_hdr->u.hdr.retain_hdr; + rule->cnt_idx = rule_hdr->u.hdr.stats_cnt_idx; + rule->id = rule_hdr->u.hdr.rule_id; + rule->close_aggr_irq_mod = rule_hdr->u.hdr.close_aggr_irq_mod; + + atrb->rule_eq_bitmap = rule_hdr->u.hdr.en_rule; + + if (rule_hdr->u.hdr.ext_hdr) { + ext_hdr = + (struct ipa5_5_rt_rule_hw_hdr_ext *)(addr + sizeof(*rule_hdr)); + rule->ttl_update = ext_hdr->u.hdr.ttl; + rule->qos_class = ext_hdr->u.hdr.qos_class; + rule->skip_ingress = ext_hdr->u.hdr.skip_ingress; + ext_hdr_sz = sizeof(*ext_hdr); + } + + return ipa_fltrt_parse_hw_rule_eq(addr, sizeof(*rule_hdr) + ext_hdr_sz, + atrb, &rule->rule_size); +} + +static int ipa_flt_parse_hw_rule(u8 *addr, struct ipahal_flt_rule_entry *rule) +{ + struct ipa3_0_flt_rule_hw_hdr *rule_hdr; + struct ipa_ipfltri_rule_eq *atrb; + + IPAHAL_DBG_LOW("Entry\n"); + + rule_hdr = (struct ipa3_0_flt_rule_hw_hdr *)addr; + atrb = &rule->rule.eq_attrib; + + if (rule_hdr->u.word == 0) { + /* table termintator - empty table */ + rule->rule_size = 0; + return 0; + } + + switch (rule_hdr->u.hdr.action) { + case 0x0: + rule->rule.action = IPA_PASS_TO_ROUTING; + break; + case 0x1: + rule->rule.action = IPA_PASS_TO_SRC_NAT; + break; + case 0x2: + rule->rule.action = IPA_PASS_TO_DST_NAT; + break; + case 0x3: + rule->rule.action = IPA_PASS_TO_EXCEPTION; + break; + default: + IPAHAL_ERR("Invalid Rule Action %d\n", rule_hdr->u.hdr.action); + WARN_ON_RATELIMIT_IPA(1); + rule->rule.action = rule_hdr->u.hdr.action; + } + + rule->rule.rt_tbl_idx = rule_hdr->u.hdr.rt_tbl_idx; + rule->rule.retain_hdr = rule_hdr->u.hdr.retain_hdr; + rule->priority = rule_hdr->u.hdr.priority; + rule->id = rule_hdr->u.hdr.rule_id; + + atrb->rule_eq_bitmap = rule_hdr->u.hdr.en_rule; + rule->rule.eq_attrib_type = 1; + return ipa_fltrt_parse_hw_rule_eq(addr, sizeof(*rule_hdr), + atrb, &rule->rule_size); +} + +static int ipa_flt_parse_hw_rule_ipav4(u8 *addr, + struct ipahal_flt_rule_entry *rule) +{ + struct ipa4_0_flt_rule_hw_hdr *rule_hdr; + struct ipa_ipfltri_rule_eq *atrb; + + IPAHAL_DBG_LOW("Entry\n"); + + rule_hdr = (struct ipa4_0_flt_rule_hw_hdr *)addr; + atrb = &rule->rule.eq_attrib; + + if (rule_hdr->u.word == 0) { + /* table termintator - empty table */ + rule->rule_size = 0; + return 0; + } + + switch (rule_hdr->u.hdr.action) { + case 0x0: + rule->rule.action = IPA_PASS_TO_ROUTING; + break; + case 0x1: + rule->rule.action = IPA_PASS_TO_SRC_NAT; + break; + case 0x2: + rule->rule.action = IPA_PASS_TO_DST_NAT; + break; + case 0x3: + rule->rule.action = IPA_PASS_TO_EXCEPTION; + break; + default: + IPAHAL_ERR("Invalid Rule Action %d\n", rule_hdr->u.hdr.action); + WARN_ON_RATELIMIT_IPA(1); + rule->rule.action = rule_hdr->u.hdr.action; + } + + rule->rule.rt_tbl_idx = rule_hdr->u.hdr.rt_tbl_idx; + rule->rule.retain_hdr = rule_hdr->u.hdr.retain_hdr; + rule->priority = rule_hdr->u.hdr.priority; + rule->id = rule_hdr->u.hdr.rule_id; + rule->rule.pdn_idx = rule_hdr->u.hdr.pdn_idx; + rule->rule.set_metadata = rule_hdr->u.hdr.set_metadata; + + atrb->rule_eq_bitmap = rule_hdr->u.hdr.en_rule; + rule->rule.eq_attrib_type = 1; + return ipa_fltrt_parse_hw_rule_eq(addr, sizeof(*rule_hdr), + atrb, &rule->rule_size); +} + +static int ipa_flt_parse_hw_rule_ipav4_5(u8 *addr, + struct ipahal_flt_rule_entry *rule) +{ + struct ipa4_5_flt_rule_hw_hdr *rule_hdr; + struct ipa_ipfltri_rule_eq *atrb; + + IPAHAL_DBG_LOW("Entry\n"); + + rule_hdr = (struct ipa4_5_flt_rule_hw_hdr *)addr; + atrb = &rule->rule.eq_attrib; + + if (rule_hdr->u.word == 0) { + /* table terminator - empty table */ + rule->rule_size = 0; + return 0; + } + + switch (rule_hdr->u.hdr.action) { + case 0x0: + rule->rule.action = IPA_PASS_TO_ROUTING; + break; + case 0x1: + rule->rule.action = IPA_PASS_TO_SRC_NAT; + break; + case 0x2: + rule->rule.action = IPA_PASS_TO_DST_NAT; + break; + case 0x3: + rule->rule.action = IPA_PASS_TO_EXCEPTION; + break; + default: + IPAHAL_ERR("Invalid Rule Action %d\n", rule_hdr->u.hdr.action); + WARN_ON_RATELIMIT_IPA(1); + rule->rule.action = rule_hdr->u.hdr.action; + } + + rule->rule.rt_tbl_idx = rule_hdr->u.hdr.rt_tbl_idx; + rule->rule.retain_hdr = rule_hdr->u.hdr.retain_hdr; + rule->priority = rule_hdr->u.hdr.priority; + rule->id = rule_hdr->u.hdr.rule_id; + rule->rule.pdn_idx = rule_hdr->u.hdr.pdn_idx; + rule->rule.set_metadata = rule_hdr->u.hdr.set_metadata; + rule->cnt_idx = rule_hdr->u.hdr.stats_cnt_idx_lsb | + (rule_hdr->u.hdr.stats_cnt_idx_msb) << 6; + + atrb->rule_eq_bitmap = rule_hdr->u.hdr.en_rule; + rule->rule.eq_attrib_type = 1; + return ipa_fltrt_parse_hw_rule_eq(addr, sizeof(*rule_hdr), + atrb, &rule->rule_size); +} + +static int ipa_flt_parse_hw_rule_ipav5_0(u8 *addr, + struct ipahal_flt_rule_entry *rule) +{ + struct ipa5_0_flt_rule_hw_hdr *rule_hdr; + struct ipa_ipfltri_rule_eq *atrb; + + IPAHAL_DBG_LOW("Entry\n"); + + rule_hdr = (struct ipa5_0_flt_rule_hw_hdr *)addr; + atrb = &rule->rule.eq_attrib; + + if (rule_hdr->u.word == 0) { + /* table terminator - empty table */ + rule->rule_size = 0; + return 0; + } + + switch (rule_hdr->u.hdr.action) { + case 0x0: + rule->rule.action = IPA_PASS_TO_ROUTING; + break; + case 0x1: + rule->rule.action = IPA_PASS_TO_SRC_NAT; + break; + case 0x2: + rule->rule.action = IPA_PASS_TO_DST_NAT; + break; + case 0x3: + rule->rule.action = IPA_PASS_TO_EXCEPTION; + break; + default: + IPAHAL_ERR("Invalid Rule Action %d\n", rule_hdr->u.hdr.action); + WARN_ON_RATELIMIT_IPA(1); + rule->rule.action = rule_hdr->u.hdr.action; + } + + rule->rule.rt_tbl_idx = rule_hdr->u.hdr.rt_tbl_idx; + rule->rule.retain_hdr = rule_hdr->u.hdr.retain_hdr; + rule->priority = rule_hdr->u.hdr.priority; + rule->id = rule_hdr->u.hdr.rule_id; + rule->rule.pdn_idx = rule_hdr->u.hdr.pdn_idx; + rule->rule.set_metadata = rule_hdr->u.hdr.set_metadata; + rule->cnt_idx = rule_hdr->u.hdr.stats_cnt_idx; + rule->rule.close_aggr_irq_mod = rule_hdr->u.hdr.close_aggr_irq_mod; + + atrb->rule_eq_bitmap = rule_hdr->u.hdr.en_rule; + rule->rule.eq_attrib_type = 1; + return ipa_fltrt_parse_hw_rule_eq(addr, sizeof(*rule_hdr), + atrb, &rule->rule_size); +} + +static int ipa_flt_parse_hw_rule_ipav5_5(u8 *addr, + struct ipahal_flt_rule_entry *rule) +{ + struct ipa5_5_flt_rule_hw_hdr *rule_hdr; + struct ipa5_5_flt_rule_hw_hdr_ext *ext_hdr; + struct ipa_ipfltri_rule_eq *atrb; + u32 ext_hdr_sz = 0; + + IPAHAL_DBG_LOW("Entry\n"); + + rule_hdr = (struct ipa5_5_flt_rule_hw_hdr *)addr; + atrb = &rule->rule.eq_attrib; + + if (rule_hdr->u.word == 0) { + /* table terminator - empty table */ + rule->rule_size = 0; + return 0; + } + + switch (rule_hdr->u.hdr.action) { + case 0x0: + rule->rule.action = IPA_PASS_TO_ROUTING; + break; + case 0x1: + rule->rule.action = IPA_PASS_TO_SRC_NAT; + break; + case 0x2: + rule->rule.action = IPA_PASS_TO_DST_NAT; + break; + case 0x3: + rule->rule.action = IPA_PASS_TO_EXCEPTION; + break; + default: + IPAHAL_ERR("Invalid Rule Action %d\n", rule_hdr->u.hdr.action); + WARN_ON_RATELIMIT_IPA(1); + rule->rule.action = rule_hdr->u.hdr.action; + } + + rule->rule.rt_tbl_idx = rule_hdr->u.hdr.rt_tbl_idx; + rule->rule.retain_hdr = rule_hdr->u.hdr.retain_hdr; + rule->priority = rule_hdr->u.hdr.priority; + rule->id = rule_hdr->u.hdr.rule_id; + rule->rule.pdn_idx = rule_hdr->u.hdr.pdn_idx; + rule->rule.set_metadata = rule_hdr->u.hdr.set_metadata; + rule->cnt_idx = rule_hdr->u.hdr.stats_cnt_idx; + rule->rule.close_aggr_irq_mod = rule_hdr->u.hdr.close_aggr_irq_mod; + + atrb->rule_eq_bitmap = rule_hdr->u.hdr.en_rule; + rule->rule.eq_attrib_type = 1; + if (rule_hdr->u.hdr.ext_hdr) { + ext_hdr = + (struct ipa5_5_flt_rule_hw_hdr_ext *)(addr + sizeof(*rule_hdr)); + rule->rule.ttl_update = ext_hdr->u.hdr.ttl; + rule->rule.qos_class = ext_hdr->u.hdr.qos_class; + ext_hdr_sz = sizeof(*ext_hdr); + } + return ipa_fltrt_parse_hw_rule_eq(addr, sizeof(*rule_hdr) + ext_hdr_sz, + atrb, &rule->rule_size); +} + + +/* + * ipahal_fltrt_init() - Build the FLT/RT information table + * See ipahal_fltrt_objs[] comments + * + * Note: As global variables are initialized with zero, any un-overridden + * register entry will be zero. By this we recognize them. + */ +int ipahal_fltrt_init(enum ipa_hw_type ipa_hw_type) +{ + struct ipahal_fltrt_obj zero_obj; + int i; + struct ipa_mem_buffer *mem; + int rc = -EFAULT; + u32 eq_bits; + u8 *eq_bitfield; + + IPAHAL_DBG("Entry - HW_TYPE=%d\n", ipa_hw_type); + + if (ipa_hw_type >= IPA_HW_MAX) { + IPAHAL_ERR("Invalid H/W type\n"); + return -EFAULT; + } + + memset(&zero_obj, 0, sizeof(zero_obj)); + for (i = IPA_HW_v3_0 ; i < ipa_hw_type ; i++) { + if (!memcmp(&ipahal_fltrt_objs[i+1], &zero_obj, + sizeof(struct ipahal_fltrt_obj))) { + memcpy(&ipahal_fltrt_objs[i+1], + &ipahal_fltrt_objs[i], + sizeof(struct ipahal_fltrt_obj)); + } else { + /* + * explicitly overridden FLT RT info + * Check validity + */ + if (!ipahal_fltrt_objs[i+1].tbl_width) { + IPAHAL_ERR( + "Zero tbl width ipaver=%d\n", + i+1); + WARN_ON(1); + } + if (!ipahal_fltrt_objs[i+1].sysaddr_alignment) { + IPAHAL_ERR( + "No tbl sysaddr alignment ipaver=%d\n", + i+1); + WARN_ON(1); + } + if (!ipahal_fltrt_objs[i+1].lcladdr_alignment) { + IPAHAL_ERR( + "No tbl lcladdr alignment ipaver=%d\n", + i+1); + WARN_ON(1); + } + if (!ipahal_fltrt_objs[i+1].blk_sz_alignment) { + IPAHAL_ERR( + "No blk sz alignment ipaver=%d\n", + i+1); + WARN_ON(1); + } + if (!ipahal_fltrt_objs[i+1].rule_start_alignment) { + IPAHAL_ERR( + "No rule start alignment ipaver=%d\n", + i+1); + WARN_ON(1); + } + if (!ipahal_fltrt_objs[i+1].tbl_hdr_width) { + IPAHAL_ERR( + "Zero tbl hdr width ipaver=%d\n", + i+1); + WARN_ON(1); + } + if (!ipahal_fltrt_objs[i+1].tbl_addr_mask) { + IPAHAL_ERR( + "Zero tbl hdr width ipaver=%d\n", + i+1); + WARN_ON(1); + } + if (ipahal_fltrt_objs[i+1].rule_id_bit_len < 2) { + IPAHAL_ERR( + "Too little bits for rule_id ipaver=%d\n", + i+1); + WARN_ON(1); + } + if (!ipahal_fltrt_objs[i+1].rule_buf_size) { + IPAHAL_ERR( + "zero rule buf size ipaver=%d\n", + i+1); + WARN_ON(1); + } + if (!ipahal_fltrt_objs[i+1].write_val_to_hdr) { + IPAHAL_ERR( + "No write_val_to_hdr CB ipaver=%d\n", + i+1); + WARN_ON(1); + } + if (!ipahal_fltrt_objs[i+1].create_flt_bitmap) { + IPAHAL_ERR( + "No create_flt_bitmap CB ipaver=%d\n", + i+1); + WARN_ON(1); + } + if (!ipahal_fltrt_objs[i+1].create_tbl_addr) { + IPAHAL_ERR( + "No create_tbl_addr CB ipaver=%d\n", + i+1); + WARN_ON(1); + } + if (!ipahal_fltrt_objs[i+1].parse_tbl_addr) { + IPAHAL_ERR( + "No parse_tbl_addr CB ipaver=%d\n", + i+1); + WARN_ON(1); + } + if (!ipahal_fltrt_objs[i+1].rt_generate_hw_rule) { + IPAHAL_ERR( + "No rt_generate_hw_rule CB ipaver=%d\n", + i+1); + WARN_ON(1); + } + if (!ipahal_fltrt_objs[i+1].flt_generate_hw_rule) { + IPAHAL_ERR( + "No flt_generate_hw_rule CB ipaver=%d\n", + i+1); + WARN_ON(1); + } + if (!ipahal_fltrt_objs[i+1].flt_generate_eq) { + IPAHAL_ERR( + "No flt_generate_eq CB ipaver=%d\n", + i+1); + WARN_ON(1); + } + if (!ipahal_fltrt_objs[i+1].rt_parse_hw_rule) { + IPAHAL_ERR( + "No rt_parse_hw_rule CB ipaver=%d\n", + i+1); + WARN_ON(1); + } + if (!ipahal_fltrt_objs[i+1].flt_parse_hw_rule) { + IPAHAL_ERR( + "No flt_parse_hw_rule CB ipaver=%d\n", + i+1); + WARN_ON(1); + } + } + } + + eq_bits = 0; + eq_bitfield = ipahal_fltrt_objs[ipa_hw_type].eq_bitfield; + for (i = 0; i < IPA_EQ_MAX; i++) { + if (!IPA_IS_RULE_EQ_VALID(i)) + continue; + + if (eq_bits & IPA_GET_RULE_EQ_BIT_PTRN(i)) { + IPAHAL_ERR("more than eq with same bit. eq=%d\n", i); + WARN_ON(1); + return -EFAULT; + } + eq_bits |= IPA_GET_RULE_EQ_BIT_PTRN(i); + } + + mem = &ipahal_ctx->empty_fltrt_tbl; + + /* setup an empty table in system memory; This will + * be used, for example, to delete a rt tbl safely + */ + mem->size = ipahal_fltrt_objs[ipa_hw_type].tbl_width; + mem->base = dma_alloc_coherent(ipahal_ctx->ipa_pdev, mem->size, + &mem->phys_base, GFP_KERNEL); + if (!mem->base) { + IPAHAL_ERR("DMA buff alloc fail %d bytes for empty tbl\n", + mem->size); + return -ENOMEM; + } + + if (mem->phys_base & + ipahal_fltrt_objs[ipa_hw_type].sysaddr_alignment) { + IPAHAL_ERR("Empty table buf is not address aligned 0x%pad\n", + &mem->phys_base); + rc = -EFAULT; + goto clear_empty_tbl; + } + + memset(mem->base, 0, mem->size); + IPAHAL_DBG("empty table allocated in system memory"); + + return 0; + +clear_empty_tbl: + dma_free_coherent(ipahal_ctx->ipa_pdev, mem->size, mem->base, + mem->phys_base); + return rc; +} + +void ipahal_fltrt_destroy(void) +{ + IPAHAL_DBG("Entry\n"); + + if (ipahal_ctx && ipahal_ctx->empty_fltrt_tbl.base) + dma_free_coherent(ipahal_ctx->ipa_pdev, + ipahal_ctx->empty_fltrt_tbl.size, + ipahal_ctx->empty_fltrt_tbl.base, + ipahal_ctx->empty_fltrt_tbl.phys_base); +} + +/* Get the H/W table (flt/rt) header width */ +u32 ipahal_get_hw_tbl_hdr_width(void) +{ + return ipahal_fltrt_objs[ipahal_ctx->hw_type].tbl_hdr_width; +} + +/* Get the H/W local table (SRAM) address alignment + * Tables headers references to local tables via offsets in SRAM + * This function return the alignment of the offset that IPA expects + */ +u32 ipahal_get_lcl_tbl_addr_alignment(void) +{ + return ipahal_fltrt_objs[ipahal_ctx->hw_type].lcladdr_alignment; +} + +/* Get the H/W (flt/rt) prefetch buf size */ +u32 ipahal_get_hw_prefetch_buf_size(void) +{ + return ipahal_fltrt_objs[ipahal_ctx->hw_type].prefetech_buf_size; +} + +/* + * Rule priority is used to distinguish rules order + * at the integrated table consisting from hashable and + * non-hashable tables. Max priority are rules that once are + * scanned by IPA, IPA will not look for further rules and use it. + */ +int ipahal_get_rule_max_priority(void) +{ + return ipahal_fltrt_objs[ipahal_ctx->hw_type].rule_max_prio; +} + +/* Given a priority, calc and return the next lower one if it is in + * legal range. + */ +int ipahal_rule_decrease_priority(int *prio) +{ + struct ipahal_fltrt_obj *obj; + + obj = &ipahal_fltrt_objs[ipahal_ctx->hw_type]; + + if (!prio) { + IPAHAL_ERR("Invalid Input\n"); + return -EINVAL; + } + + /* Priority logic is reverse. 0 priority considred max priority */ + if (*prio > obj->rule_min_prio || *prio < obj->rule_max_prio) { + IPAHAL_ERR("Invalid given priority %d\n", *prio); + return -EINVAL; + } + + *prio += 1; + + if (*prio > obj->rule_min_prio) { + IPAHAL_ERR("Cannot decrease priority. Already on min\n"); + *prio -= 1; + return -EFAULT; + } + + return 0; +} + +/* Does the given ID represents rule miss? + * Rule miss ID, is always the max ID possible in the bit-pattern + */ +bool ipahal_is_rule_miss_id(u32 id) +{ + return (id == + ((1U << ipahal_fltrt_objs[ipahal_ctx->hw_type].rule_id_bit_len) + -1)); +} + +/* Get rule ID with high bit only asserted + * Used e.g. to create groups of IDs according to this bit + */ +u32 ipahal_get_rule_id_hi_bit(void) +{ + return BIT(ipahal_fltrt_objs[ipahal_ctx->hw_type].rule_id_bit_len - 1); +} + +/* Get the low value possible to be used for rule-id */ +u32 ipahal_get_low_rule_id(void) +{ + return ipahal_fltrt_objs[ipahal_ctx->hw_type].low_rule_id; +} + +/* + * Is the given counter id valid + */ +bool ipahal_is_rule_cnt_id_valid(u8 cnt_id) +{ + if (cnt_id < 0 || cnt_id > IPA_FLT_RT_HW_COUNTER) + return false; + return true; +} + + +/* + * low value possible for counter hdl id + */ +u32 ipahal_get_low_hdl_id(void) +{ + return IPA4_5_LOW_CNT_ID; +} + +/* + * max counter hdl id for stats + */ +u32 ipahal_get_high_hdl_id(void) +{ + return IPA_MAX_FLT_RT_CNT_INDEX; +} + +/* + * ipahal_rt_generate_empty_img() - Generate empty route image + * Creates routing header buffer for the given tables number. + * For each table, make it point to the empty table on DDR. + * @tbls_num: Number of tables. For each will have an entry in the header + * @hash_hdr_size: SRAM buf size of the hash tbls hdr. Used for space check + * @nhash_hdr_size: SRAM buf size of the nhash tbls hdr. Used for space check + * @mem: mem object that points to DMA mem representing the hdr structure + * @atomic: should DMA allocation be executed with atomic flag + */ +int ipahal_rt_generate_empty_img(u32 tbls_num, u32 hash_hdr_size, + u32 nhash_hdr_size, struct ipa_mem_buffer *mem, bool atomic) +{ + int i; + u64 addr; + struct ipahal_fltrt_obj *obj; + int flag; + + IPAHAL_DBG("Entry\n"); + + flag = atomic ? GFP_ATOMIC : GFP_KERNEL; + obj = &ipahal_fltrt_objs[ipahal_ctx->hw_type]; + + if (!tbls_num || !nhash_hdr_size || !mem) { + IPAHAL_ERR("Input Error: tbls_num=%d nhash_hdr_sz=%d mem=%pK\n", + tbls_num, nhash_hdr_size, mem); + return -EINVAL; + } + if (obj->support_hash && !hash_hdr_size) { + IPAHAL_ERR("Input Error: hash_hdr_sz=%d\n", hash_hdr_size); + return -EINVAL; + } + + if (nhash_hdr_size < (tbls_num * obj->tbl_hdr_width)) { + IPAHAL_ERR("No enough spc at non-hash hdr blk for all tbls\n"); + WARN_ON(1); + return -EINVAL; + } + if (obj->support_hash && + (hash_hdr_size < (tbls_num * obj->tbl_hdr_width))) { + IPAHAL_ERR("No enough spc at hash hdr blk for all tbls\n"); + WARN_ON(1); + return -EINVAL; + } + + mem->size = tbls_num * obj->tbl_hdr_width; + mem->base = dma_alloc_coherent(ipahal_ctx->ipa_pdev, mem->size, + &mem->phys_base, flag); + if (!mem->base) { + IPAHAL_ERR("fail to alloc DMA buff of size %d\n", mem->size); + return -ENOMEM; + } + /* fetch empty tbl from SRAM */ + addr = obj->create_tbl_addr(false, + IPA_EMPTY_SRAM_OFFSET); + for (i = 0; i < tbls_num; i++) + obj->write_val_to_hdr(addr, + mem->base + i * obj->tbl_hdr_width); + + return 0; +} + +/* + * ipahal_flt_generate_empty_img() - Generate empty filter image + * Creates filter header buffer for the given tables number. + * For each table, make it point to the empty table on DDR. + * @tbls_num: Number of tables. For each will have an entry in the header + * @hash_hdr_size: SRAM buf size of the hash tbls hdr. Used for space check + * @nhash_hdr_size: SRAM buf size of the nhash tbls hdr. Used for space check + * @ep_bitmap: Bitmap representing the EP that has flt tables. The format + * should be: bit0->EP0, bit1->EP1 + * If bitmap is zero -> create tbl without bitmap entry + * @mem: mem object that points to DMA mem representing the hdr structure + * @atomic: should DMA allocation be executed with atomic flag + */ +int ipahal_flt_generate_empty_img(u32 tbls_num, u32 hash_hdr_size, + u32 nhash_hdr_size, u64 ep_bitmap, struct ipa_mem_buffer *mem, + bool atomic) +{ + int flt_spc; + u64 flt_bitmap; + int i; + u64 addr; + struct ipahal_fltrt_obj *obj; + int flag; + + IPAHAL_DBG("Entry - ep_bitmap 0x%llx\n", ep_bitmap); + + flag = atomic ? GFP_ATOMIC : GFP_KERNEL; + obj = &ipahal_fltrt_objs[ipahal_ctx->hw_type]; + + if (!tbls_num || !nhash_hdr_size || !mem) { + IPAHAL_ERR("Input Error: tbls_num=%d nhash_hdr_sz=%d mem=%pK\n", + tbls_num, nhash_hdr_size, mem); + return -EINVAL; + } + if (obj->support_hash && !hash_hdr_size) { + IPAHAL_ERR("Input Error: hash_hdr_sz=%d\n", hash_hdr_size); + return -EINVAL; + } + + if (obj->support_hash) { + flt_spc = hash_hdr_size; + /* bitmap word */ + if (ep_bitmap) + flt_spc -= obj->tbl_hdr_width; + flt_spc /= obj->tbl_hdr_width; + if (tbls_num > flt_spc) { + IPAHAL_ERR("space for hash flt hdr is too small\n"); + WARN_ON(1); + return -EPERM; + } + } + + flt_spc = nhash_hdr_size; + /* bitmap word */ + if (ep_bitmap) + flt_spc -= obj->tbl_hdr_width; + flt_spc /= obj->tbl_hdr_width; + if (tbls_num > flt_spc) { + IPAHAL_ERR("space for non-hash flt hdr is too small\n"); + WARN_ON(1); + return -EPERM; + } + + mem->size = tbls_num * obj->tbl_hdr_width; + if (ep_bitmap) + mem->size += obj->tbl_hdr_width; + mem->base = dma_alloc_coherent(ipahal_ctx->ipa_pdev, mem->size, + &mem->phys_base, flag); + if (!mem->base) { + IPAHAL_ERR("fail to alloc DMA buff of size %d\n", mem->size); + return -ENOMEM; + } + + if (ep_bitmap) { + flt_bitmap = obj->create_flt_bitmap(ep_bitmap); + IPAHAL_DBG("flt bitmap 0x%llx\n", flt_bitmap); + obj->write_val_to_hdr(flt_bitmap, mem->base); + } + + /* fetch empty tbl from SRAM */ + addr = obj->create_tbl_addr(false, + IPA_EMPTY_SRAM_OFFSET); + + if (ep_bitmap) { + for (i = 1; i <= tbls_num; i++) + obj->write_val_to_hdr(addr, + mem->base + i * obj->tbl_hdr_width); + } else { + for (i = 0; i < tbls_num; i++) + obj->write_val_to_hdr(addr, + mem->base + i * obj->tbl_hdr_width); + } + + return 0; +} + +/* + * ipa_fltrt_alloc_init_tbl_hdr() - allocate and initialize buffers for + * flt/rt tables headers to be filled into sram. Init each table to point + * to empty system table + * @params: Allocate IN and OUT params + * + * Return: 0 on success, negative on failure + */ +static int ipa_fltrt_alloc_init_tbl_hdr( + struct ipahal_fltrt_alloc_imgs_params *params) +{ + u64 addr; + int i; + struct ipahal_fltrt_obj *obj; + gfp_t flag = GFP_KERNEL; + + obj = &ipahal_fltrt_objs[ipahal_ctx->hw_type]; + + if (!params) { + IPAHAL_ERR_RL("Input error: params=%pK\n", params); + return -EINVAL; + } + + params->nhash_hdr.size = params->tbls_num * obj->tbl_hdr_width; +alloc: + params->nhash_hdr.base = dma_alloc_coherent(ipahal_ctx->ipa_pdev, + params->nhash_hdr.size, + ¶ms->nhash_hdr.phys_base, flag); + if (!params->nhash_hdr.base) { + if (flag == GFP_KERNEL) { + flag = GFP_ATOMIC; + goto alloc; + } + IPAHAL_ERR_RL("fail to alloc DMA buff of size %d\n", + params->nhash_hdr.size); + goto nhash_alloc_fail; + } + + if (obj->support_hash) { + params->hash_hdr.size = params->tbls_num * obj->tbl_hdr_width; + params->hash_hdr.base = dma_alloc_coherent(ipahal_ctx->ipa_pdev, + params->hash_hdr.size, ¶ms->hash_hdr.phys_base, + GFP_KERNEL); + if (!params->hash_hdr.base) { + IPAHAL_ERR_RL("fail to alloc DMA buff of size %d\n", + params->hash_hdr.size); + goto hash_alloc_fail; + } + } + + addr = obj->create_tbl_addr(false, + IPA_EMPTY_SRAM_OFFSET); + for (i = 0; i < params->tbls_num; i++) { + obj->write_val_to_hdr(addr, + params->nhash_hdr.base + i * obj->tbl_hdr_width); + if (obj->support_hash) + obj->write_val_to_hdr(addr, + params->hash_hdr.base + + i * obj->tbl_hdr_width); + } + + return 0; + +hash_alloc_fail: + ipahal_free_dma_mem(¶ms->nhash_hdr); +nhash_alloc_fail: + return -ENOMEM; +} + +u32 ipa_fltrt_get_aligned_lcl_bdy_size(u32 num_lcl_tbls, u32 total_sz_lcl_tbls) +{ + u32 result = total_sz_lcl_tbls; + struct ipahal_fltrt_obj *obj = &ipahal_fltrt_objs[ipahal_ctx->hw_type]; + + /* for table terminator */ + result += obj->tbl_width * num_lcl_tbls; + /* align the start of local rule-set */ + result += obj->lcladdr_alignment * num_lcl_tbls; + /* SRAM block size alignment */ + result += obj->blk_sz_alignment; + result &= ~(obj->blk_sz_alignment); + + IPAHAL_DBG_LOW("num_lcl_tbls = %u total_sz_lcl_tbls = %u tbl_width = %u" + " lcladdr_alignment = %u blk_sz_alignment = %u result = %u\n", + num_lcl_tbls, total_sz_lcl_tbls, + obj->tbl_width, obj->lcladdr_alignment, obj->blk_sz_alignment, + result); + + return result; +} + +/* + * ipa_fltrt_alloc_lcl_bdy() - allocate and initialize buffers for + * local flt/rt tables bodies to be filled into sram + * @params: Allocate IN and OUT params + * + * Return: 0 on success, negative on failure + */ +static int ipa_fltrt_alloc_lcl_bdy( + struct ipahal_fltrt_alloc_imgs_params *params) +{ + struct ipahal_fltrt_obj *obj; + gfp_t flag = GFP_KERNEL; + + obj = &ipahal_fltrt_objs[ipahal_ctx->hw_type]; + + /* The HAL allocates larger sizes than the given effective ones + * for alignments and border indications + */ + IPAHAL_DBG_LOW("lcl tbl bdy total effective sizes: hash=%u nhash=%u\n", + params->total_sz_lcl_hash_tbls, + params->total_sz_lcl_nhash_tbls); + + IPAHAL_DBG_LOW("lcl tbl bdy count: hash=%u nhash=%u\n", + params->num_lcl_hash_tbls, + params->num_lcl_nhash_tbls); + + /* Align the sizes to coop with termination word + * and H/W local table start offset alignment + */ + if (params->total_sz_lcl_nhash_tbls + params->num_lcl_nhash_tbls > 0) { + params->nhash_bdy.size = + ipa_fltrt_get_aligned_lcl_bdy_size(params->num_lcl_nhash_tbls, + params->total_sz_lcl_nhash_tbls); + + IPAHAL_DBG_LOW("nhash lcl tbl bdy total h/w size = %u\n", + params->nhash_bdy.size); + +alloc1: + params->nhash_bdy.base = dma_alloc_coherent( + ipahal_ctx->ipa_pdev, params->nhash_bdy.size, + ¶ms->nhash_bdy.phys_base, flag); + if (!params->nhash_bdy.base) { + if (flag == GFP_KERNEL) { + flag = GFP_ATOMIC; + goto alloc1; + } + IPAHAL_ERR("fail to alloc DMA buff of size %d\n", + params->nhash_bdy.size); + return -ENOMEM; + } + } + + if (!obj->support_hash && params->hash_bdy.size) { + IPAHAL_ERR("No HAL Hash tbls support - Will be ignored\n"); + WARN_ON(1); + } + + if (obj->support_hash && params->hash_bdy.size) { + params->hash_bdy.size = + ipa_fltrt_get_aligned_lcl_bdy_size(params->num_lcl_hash_tbls, + params->total_sz_lcl_hash_tbls); + + IPAHAL_DBG_LOW("hash lcl tbl bdy total h/w size = %u\n", + params->hash_bdy.size); + +alloc2: + params->hash_bdy.base = dma_alloc_coherent( + ipahal_ctx->ipa_pdev, params->hash_bdy.size, + ¶ms->hash_bdy.phys_base, flag); + if (!params->hash_bdy.base) { + if (flag == GFP_KERNEL) { + flag = GFP_ATOMIC; + goto alloc2; + } + IPAHAL_ERR("fail to alloc DMA buff of size %d\n", + params->hash_bdy.size); + goto hash_bdy_fail; + } + } + + return 0; + +hash_bdy_fail: + if (params->nhash_bdy.size) + ipahal_free_dma_mem(¶ms->nhash_bdy); + + return -ENOMEM; +} + +/* + * ipahal_fltrt_allocate_hw_tbl_imgs() - Allocate tbl images DMA structures + * Used usually during commit. + * Allocates header structures and init them to point to empty DDR table + * Allocate body strucutres for local bodies tables + * @params: Parameters for IN and OUT regard the allocation. + */ +int ipahal_fltrt_allocate_hw_tbl_imgs( + struct ipahal_fltrt_alloc_imgs_params *params) +{ + IPAHAL_DBG_LOW("Entry\n"); + + /* Input validation */ + if (!params) { + IPAHAL_ERR_RL("Input err: no params\n"); + return -EINVAL; + } + if (params->ipt >= IPA_IP_MAX) { + IPAHAL_ERR_RL("Input err: Invalid ip type %d\n", params->ipt); + return -EINVAL; + } + + if (ipa_fltrt_alloc_init_tbl_hdr(params)) { + IPAHAL_ERR_RL("fail to alloc and init tbl hdr\n"); + return -ENOMEM; + } + + if (ipa_fltrt_alloc_lcl_bdy(params)) { + IPAHAL_ERR_RL("fail to alloc tbl bodies\n"); + goto bdy_alloc_fail; + } + + return 0; + +bdy_alloc_fail: + ipahal_free_dma_mem(¶ms->nhash_hdr); + if (params->hash_hdr.size) + ipahal_free_dma_mem(¶ms->hash_hdr); + return -ENOMEM; +} + +/* + * ipahal_fltrt_allocate_hw_sys_tbl() - Allocate DMA mem for H/W flt/rt sys tbl + * @tbl_mem: IN/OUT param. size for effective table size. Pointer, for the + * allocated memory. + * + * The size is adapted for needed alignments/borders. + */ +int ipahal_fltrt_allocate_hw_sys_tbl(struct ipa_mem_buffer *tbl_mem) +{ + struct ipahal_fltrt_obj *obj; + gfp_t flag = GFP_KERNEL; + + IPAHAL_DBG_LOW("Entry\n"); + + if (!tbl_mem) { + IPAHAL_ERR("Input err\n"); + return -EINVAL; + } + + if (!tbl_mem->size) { + IPAHAL_ERR("Input err: zero table size\n"); + return -EINVAL; + } + + obj = &ipahal_fltrt_objs[ipahal_ctx->hw_type]; + + /* add word for rule-set terminator */ + tbl_mem->size += obj->tbl_width; +alloc: + tbl_mem->base = dma_alloc_coherent(ipahal_ctx->ipa_pdev, tbl_mem->size, + &tbl_mem->phys_base, flag); + if (!tbl_mem->base) { + if (flag == GFP_KERNEL) { + flag = GFP_ATOMIC; + goto alloc; + } + IPAHAL_ERR("fail to alloc DMA buf of size %d\n", + tbl_mem->size); + return -ENOMEM; + } + if (tbl_mem->phys_base & obj->sysaddr_alignment) { + IPAHAL_ERR("sys rt tbl address is not aligned\n"); + goto align_err; + } + + memset(tbl_mem->base, 0, tbl_mem->size); + + return 0; + +align_err: + ipahal_free_dma_mem(tbl_mem); + return -EPERM; +} + +/* + * ipahal_fltrt_write_addr_to_hdr() - Fill table header with table address + * Given table addr/offset, adapt it to IPA H/W format and write it + * to given header index. + * @addr: Address or offset to be used + * @hdr_base: base address of header structure to write the address + * @hdr_idx: index of the address in the header structure + * @is_sys: Is it system address or local offset + */ +int ipahal_fltrt_write_addr_to_hdr(u64 addr, void *hdr_base, u32 hdr_idx, + bool is_sys) +{ + struct ipahal_fltrt_obj *obj; + u64 hwaddr; + u8 *hdr; + + IPAHAL_DBG_LOW("Entry\n"); + + obj = &ipahal_fltrt_objs[ipahal_ctx->hw_type]; + + if (!addr || !hdr_base) { + IPAHAL_ERR("Input err: addr=0x%llx hdr_base=%pK\n", + addr, hdr_base); + return -EINVAL; + } + + hdr = (u8 *)hdr_base; + hdr += hdr_idx * obj->tbl_hdr_width; + hwaddr = obj->create_tbl_addr(is_sys, addr); + obj->write_val_to_hdr(hwaddr, hdr); + + return 0; +} + +/* + * ipahal_fltrt_read_addr_from_hdr() - Given sram address, read it's + * content (physical address or offset) and parse it. + * @hdr_base: base sram address of the header structure. + * @hdr_idx: index of the header entry line in the header structure. + * @addr: The parsed address - Out parameter + * @is_sys: Is this system or local address - Out parameter + */ +int ipahal_fltrt_read_addr_from_hdr(void *hdr_base, u32 hdr_idx, u64 *addr, + bool *is_sys) +{ + struct ipahal_fltrt_obj *obj; + u64 hwaddr; + u8 *hdr; + + IPAHAL_DBG_LOW("Entry\n"); + + obj = &ipahal_fltrt_objs[ipahal_ctx->hw_type]; + + if (!addr || !hdr_base || !is_sys) { + IPAHAL_ERR("Input err: addr=%pK hdr_base=%pK is_sys=%pK\n", + addr, hdr_base, is_sys); + return -EINVAL; + } + + hdr = (u8 *)hdr_base; + hdr += hdr_idx * obj->tbl_hdr_width; + hwaddr = *((u64 *)hdr); + obj->parse_tbl_addr(hwaddr, addr, is_sys); + return 0; +} + +/* + * ipahal_rt_generate_hw_rule() - generates the routing hardware rule + * @params: Params for the rule creation. + * @hw_len: Size of the H/W rule to be returned + * @buf: Buffer to build the rule in. If buf is NULL, then the rule will + * be built in internal temp buf. This is used e.g. to get the rule size + * only. + */ +int ipahal_rt_generate_hw_rule(struct ipahal_rt_rule_gen_params *params, + u32 *hw_len, u8 *buf) +{ + struct ipahal_fltrt_obj *obj; + u8 *tmp = NULL; + int rc; + + IPAHAL_DBG_LOW("Entry\n"); + + if (!params || !hw_len) { + IPAHAL_ERR("Input err: params=%pK hw_len=%pK\n", + params, hw_len); + return -EINVAL; + } + if (!params->rule) { + IPAHAL_ERR("Input err: invalid rule\n"); + return -EINVAL; + } + if (params->ipt >= IPA_IP_MAX) { + IPAHAL_ERR("Input err: Invalid ip type %d\n", params->ipt); + return -EINVAL; + } + + obj = &ipahal_fltrt_objs[ipahal_ctx->hw_type]; + + if (buf == NULL) { + tmp = kzalloc(obj->rule_buf_size, GFP_KERNEL); + if (!tmp) + return -ENOMEM; + buf = tmp; + } else { + if ((long)buf & obj->rule_start_alignment) { + IPAHAL_ERR("buff is not rule start aligned\n"); + return -EPERM; + } + } + + rc = obj->rt_generate_hw_rule(params, hw_len, buf); + if (!tmp && !rc) { + /* write the rule-set terminator */ + memset(buf + *hw_len, 0, obj->tbl_width); + } + + kfree(tmp); + + return rc; +} + +/* + * ipahal_flt_generate_hw_rule() - generates the filtering hardware rule. + * @params: Params for the rule creation. + * @hw_len: Size of the H/W rule to be returned + * @buf: Buffer to build the rule in. If buf is NULL, then the rule will + * be built in internal temp buf. This is used e.g. to get the rule size + * only. + */ +int ipahal_flt_generate_hw_rule(struct ipahal_flt_rule_gen_params *params, + u32 *hw_len, u8 *buf) +{ + struct ipahal_fltrt_obj *obj; + u8 *tmp = NULL; + int rc; + + IPAHAL_DBG_LOW("Entry\n"); + + if (!params || !hw_len) { + IPAHAL_ERR("Input err: params=%pK hw_len=%pK\n", + params, hw_len); + return -EINVAL; + } + if (!params->rule) { + IPAHAL_ERR("Input err: invalid rule\n"); + return -EINVAL; + } + if (params->ipt >= IPA_IP_MAX) { + IPAHAL_ERR("Input err: Invalid ip type %d\n", params->ipt); + return -EINVAL; + } + + obj = &ipahal_fltrt_objs[ipahal_ctx->hw_type]; + + if (buf == NULL) { + tmp = kzalloc(obj->rule_buf_size, GFP_KERNEL); + if (!tmp) { + IPAHAL_ERR("failed to alloc %u bytes\n", + obj->rule_buf_size); + return -ENOMEM; + } + buf = tmp; + } else + if ((long)buf & obj->rule_start_alignment) { + IPAHAL_ERR("buff is not rule rule start aligned\n"); + return -EPERM; + } + + rc = obj->flt_generate_hw_rule(params, hw_len, buf); + if (!tmp && !rc) { + /* write the rule-set terminator */ + memset(buf + *hw_len, 0, obj->tbl_width); + } + + kfree(tmp); + + return rc; + +} + +/* + * ipahal_flt_generate_equation() - generate flt rule in equation form + * Will build equation form flt rule from given info. + * @ipt: IP family + * @attrib: Rule attribute to be generated + * @eq_atrb: Equation form generated rule + * Note: Usage example: Pass the generated form to other sub-systems + * for inter-subsystems rules exchange. + */ +int ipahal_flt_generate_equation(enum ipa_ip_type ipt, + const struct ipa_rule_attrib *attrib, + struct ipa_ipfltri_rule_eq *eq_atrb) +{ + IPAHAL_DBG_LOW("Entry\n"); + + if (ipt >= IPA_IP_MAX) { + IPAHAL_ERR_RL("Input err: Invalid ip type %d\n", ipt); + return -EINVAL; + } + + if (!attrib || !eq_atrb) { + IPAHAL_ERR_RL("Input err: attrib=%pK eq_atrb=%pK\n", + attrib, eq_atrb); + return -EINVAL; + } + + return ipahal_fltrt_objs[ipahal_ctx->hw_type].flt_generate_eq(ipt, + attrib, eq_atrb); + +} + +/* + * ipahal_rt_parse_hw_rule() - Parse H/W formated rt rule + * Given the rule address, read the rule info from H/W and parse it. + * @rule_addr: Rule address (virtual memory) + * @rule: Out parameter for parsed rule info + */ +int ipahal_rt_parse_hw_rule(u8 *rule_addr, + struct ipahal_rt_rule_entry *rule) +{ + IPAHAL_DBG_LOW("Entry\n"); + + if (!rule_addr || !rule) { + IPAHAL_ERR("Input err: rule_addr=%pK rule=%pK\n", + rule_addr, rule); + return -EINVAL; + } + + return ipahal_fltrt_objs[ipahal_ctx->hw_type].rt_parse_hw_rule( + rule_addr, rule); +} + +/* + * ipahal_flt_parse_hw_rule() - Parse H/W formated flt rule + * Given the rule address, read the rule info from H/W and parse it. + * @rule_addr: Rule address (virtual memory) + * @rule: Out parameter for parsed rule info + */ +int ipahal_flt_parse_hw_rule(u8 *rule_addr, + struct ipahal_flt_rule_entry *rule) +{ + IPAHAL_DBG_LOW("Entry\n"); + + if (!rule_addr || !rule) { + IPAHAL_ERR("Input err: rule_addr=%pK rule=%pK\n", + rule_addr, rule); + return -EINVAL; + } + + return ipahal_fltrt_objs[ipahal_ctx->hw_type].flt_parse_hw_rule( + rule_addr, rule); +} + diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_fltrt.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_fltrt.h new file mode 100644 index 0000000000..34e6bfd12a --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_fltrt.h @@ -0,0 +1,328 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _IPAHAL_FLTRT_H_ +#define _IPAHAL_FLTRT_H_ + +/* + * struct ipahal_fltrt_alloc_imgs_params - Params for tbls imgs allocations + * The allocation logic will allocate DMA memory representing the header. + * If the bodies are local (SRAM) the allocation will allocate + * a DMA buffers that would contain the content of these local tables in raw + * @ipt: IP version type + * @tbls_num: Number of tables to represent by the header + * @num_lcl_hash_tbls: Number of local (sram) hashable tables + * @num_lcl_nhash_tbls: Number of local (sram) non-hashable tables + * @total_sz_lcl_hash_tbls: Total size of local hashable tables + * @total_sz_lcl_nhash_tbls: Total size of local non-hashable tables + * @hash_hdr/nhash_hdr: OUT params for the header structures + * @hash_bdy/nhash_bdy: OUT params for the local body structures + */ +struct ipahal_fltrt_alloc_imgs_params { + enum ipa_ip_type ipt; + u32 tbls_num; + u32 num_lcl_hash_tbls; + u32 num_lcl_nhash_tbls; + u32 total_sz_lcl_hash_tbls; + u32 total_sz_lcl_nhash_tbls; + + /* OUT PARAMS */ + struct ipa_mem_buffer hash_hdr; + struct ipa_mem_buffer nhash_hdr; + struct ipa_mem_buffer hash_bdy; + struct ipa_mem_buffer nhash_bdy; +}; + +/* + * enum ipahal_rt_rule_hdr_type - Header type used in rt rules + * @IPAHAL_RT_RULE_HDR_NONE: No header is used + * @IPAHAL_RT_RULE_HDR_RAW: Raw header is used + * @IPAHAL_RT_RULE_HDR_PROC_CTX: Header Processing context is used + */ +enum ipahal_rt_rule_hdr_type { + IPAHAL_RT_RULE_HDR_NONE, + IPAHAL_RT_RULE_HDR_RAW, + IPAHAL_RT_RULE_HDR_PROC_CTX, +}; + +/* + * struct ipahal_rt_rule_gen_params - Params for generating rt rule + * @ipt: IP family version + * @dst_pipe_idx: Destination pipe index + * @hdr_type: Header type to be used + * @hdr_lcl: Does header on local or system table? + * @hdr_ofst: Offset of the header in the header table + * @priority: Rule priority + * @id: Rule ID + * @cnt_idx: Stats counter index + * @rule: Rule info + */ +struct ipahal_rt_rule_gen_params { + enum ipa_ip_type ipt; + int dst_pipe_idx; + enum ipahal_rt_rule_hdr_type hdr_type; + bool hdr_lcl; + u32 hdr_ofst; + u32 priority; + u32 id; + u8 cnt_idx; + const struct ipa_rt_rule_i *rule; +}; + +/* + * struct ipahal_rt_rule_entry - Rt rule info parsed from H/W + * @dst_pipe_idx: Destination pipe index + * @hdr_lcl: Does the references header located in sram or system mem? + * @hdr_ofst: Offset of the header in the header table + * @hdr_type: Header type to be used + * @priority: Rule priority + * @retain_hdr: to retain the removed header in header removal + * @id: Rule ID + * @cnt_idx: stats counter index + * @close_aggr_irq_mod: close aggregation/coalescing and close GSI + * interrupt moderation + * @ttl_update: bool to indicate whether TTL update is needed or not. + * @qos_class: QOS classification value. + * @skip_ingress: bool to skip ingress policing. + * @eq_attrib: Equations and their params in the rule + * @rule_size: Rule size in memory + */ +struct ipahal_rt_rule_entry { + int dst_pipe_idx; + bool hdr_lcl; + u32 hdr_ofst; + enum ipahal_rt_rule_hdr_type hdr_type; + u32 priority; + bool retain_hdr; + u32 id; + u8 cnt_idx; + u8 close_aggr_irq_mod; + u8 ttl_update; + u8 qos_class; + u8 skip_ingress; + struct ipa_ipfltri_rule_eq eq_attrib; + u32 rule_size; +}; + +/* + * struct ipahal_flt_rule_gen_params - Params for generating flt rule + * @ipt: IP family version + * @rt_tbl_idx: Routing table the rule pointing to + * @priority: Rule priority + * @id: Rule ID + * @cnt_idx: Stats counter index + * @rule: Rule info + */ +struct ipahal_flt_rule_gen_params { + enum ipa_ip_type ipt; + u32 rt_tbl_idx; + u32 priority; + u32 id; + u8 cnt_idx; + const struct ipa_flt_rule_i *rule; +}; + +/* + * struct ipahal_flt_rule_entry - Flt rule info parsed from H/W + * @rule: Rule info + * @priority: Rule priority + * @id: Rule ID + * @cnt_idx: stats counter index + * @rule_size: Rule size in memory + */ +struct ipahal_flt_rule_entry { + struct ipa_flt_rule_i rule; + u32 priority; + u32 id; + u8 cnt_idx; + u32 rule_size; +}; + +/* Get the H/W table (flt/rt) header width */ +u32 ipahal_get_hw_tbl_hdr_width(void); + +/* Get the H/W local table (SRAM) address alignment + * Tables headers references to local tables via offsets in SRAM + * This function return the alignment of the offset that IPA expects + */ +u32 ipahal_get_lcl_tbl_addr_alignment(void); + +/* Get the H/W (flt/rt) prefetch buf size */ +u32 ipahal_get_hw_prefetch_buf_size(void); + +/* + * Rule priority is used to distinguish rules order + * at the integrated table consisting from hashable and + * non-hashable tables. Max priority are rules that once are + * scanned by IPA, IPA will not look for further rules and use it. + */ +int ipahal_get_rule_max_priority(void); + +/* Given a priority, calc and return the next lower one if it is in + * legal range. + */ +int ipahal_rule_decrease_priority(int *prio); + +/* Does the given ID represents rule miss? */ +bool ipahal_is_rule_miss_id(u32 id); + +/* Get rule ID with high bit only asserted + * Used e.g. to create groups of IDs according to this bit + */ +u32 ipahal_get_rule_id_hi_bit(void); + +/* Get the low value possible to be used for rule-id */ +u32 ipahal_get_low_rule_id(void); + +/* + * low value possible for counter hdl id + */ +u32 ipahal_get_low_hdl_id(void); + +/* + * max counter hdl id for stats + */ +u32 ipahal_get_high_hdl_id(void); + +/* used for query check and associated with rt/flt rules */ +bool ipahal_is_rule_cnt_id_valid(u8 cnt_id); + +/* max rule id for stats */ +bool ipahal_get_max_stats_rule_id(void); + +/* + * ipahal_rt_generate_empty_img() - Generate empty route image + * Creates routing header buffer for the given tables number. + * For each table, make it point to the empty table on DDR. + * @tbls_num: Number of tables. For each will have an entry in the header + * @hash_hdr_size: SRAM buf size of the hash tbls hdr. Used for space check + * @nhash_hdr_size: SRAM buf size of the nhash tbls hdr. Used for space check + * @mem: mem object that points to DMA mem representing the hdr structure + * @atomic: should DMA allocation be executed with atomic flag + */ +int ipahal_rt_generate_empty_img(u32 tbls_num, u32 hash_hdr_size, + u32 nhash_hdr_size, struct ipa_mem_buffer *mem, bool atomic); + +/* + * ipahal_flt_generate_empty_img() - Generate empty filter image + * Creates filter header buffer for the given tables number. + * For each table, make it point to the empty table on DDR. + * @tbls_num: Number of tables. For each will have an entry in the header + * @hash_hdr_size: SRAM buf size of the hash tbls hdr. Used for space check + * @nhash_hdr_size: SRAM buf size of the nhash tbls hdr. Used for space check + * @ep_bitmap: Bitmap representing the EP that has flt tables. The format + * should be: bit0->EP0, bit1->EP1 + * @mem: mem object that points to DMA mem representing the hdr structure + * @atomic: should DMA allocation be executed with atomic flag + */ +int ipahal_flt_generate_empty_img(u32 tbls_num, u32 hash_hdr_size, + u32 nhash_hdr_size, u64 ep_bitmap, struct ipa_mem_buffer *mem, + bool atomic); + +/* + * ipahal_fltrt_allocate_hw_tbl_imgs() - Allocate tbl images DMA structures + * Used usually during commit. + * Allocates header structures and init them to point to empty DDR table + * Allocate body strucutres for local bodies tables + * @params: Parameters for IN and OUT regard the allocation. + */ +int ipahal_fltrt_allocate_hw_tbl_imgs( + struct ipahal_fltrt_alloc_imgs_params *params); + +/* + * ipahal_fltrt_allocate_hw_sys_tbl() - Allocate DMA mem for H/W flt/rt sys tbl + * @tbl_mem: IN/OUT param. size for effective table size. Pointer, for the + * allocated memory. + * + * The size is adapted for needed alignments/borders. + */ +int ipahal_fltrt_allocate_hw_sys_tbl(struct ipa_mem_buffer *tbl_mem); + +/* + * ipahal_fltrt_write_addr_to_hdr() - Fill table header with table address + * Given table addr/offset, adapt it to IPA H/W format and write it + * to given header index. + * @addr: Address or offset to be used + * @hdr_base: base address of header structure to write the address + * @hdr_idx: index of the address in the header structure + * @is_sys: Is it system address or local offset + */ +int ipahal_fltrt_write_addr_to_hdr(u64 addr, void *hdr_base, u32 hdr_idx, + bool is_sys); + +/* + * ipahal_fltrt_read_addr_from_hdr() - Given sram address, read it's + * content (physical address or offset) and parse it. + * @hdr_base: base sram address of the header structure. + * @hdr_idx: index of the header entry line in the header structure. + * @addr: The parsed address - Out parameter + * @is_sys: Is this system or local address - Out parameter + */ +int ipahal_fltrt_read_addr_from_hdr(void *hdr_base, u32 hdr_idx, u64 *addr, + bool *is_sys); + +/* + * ipahal_rt_generate_hw_rule() - generates the routing hardware rule. + * @params: Params for the rule creation. + * @hw_len: Size of the H/W rule to be returned + * @buf: Buffer to build the rule in. If buf is NULL, then the rule will + * be built in internal temp buf. This is used e.g. to get the rule size + * only. + */ +int ipahal_rt_generate_hw_rule(struct ipahal_rt_rule_gen_params *params, + u32 *hw_len, u8 *buf); + +/* + * ipahal_flt_generate_hw_rule() - generates the filtering hardware rule. + * @params: Params for the rule creation. + * @hw_len: Size of the H/W rule to be returned + * @buf: Buffer to build the rule in. If buf is NULL, then the rule will + * be built in internal temp buf. This is used e.g. to get the rule size + * only. + */ +int ipahal_flt_generate_hw_rule(struct ipahal_flt_rule_gen_params *params, + u32 *hw_len, u8 *buf); + +/* + * ipahal_flt_generate_equation() - generate flt rule in equation form + * Will build equation form flt rule from given info. + * @ipt: IP family + * @attrib: Rule attribute to be generated + * @eq_atrb: Equation form generated rule + * Note: Usage example: Pass the generated form to other sub-systems + * for inter-subsystems rules exchange. + */ +int ipahal_flt_generate_equation(enum ipa_ip_type ipt, + const struct ipa_rule_attrib *attrib, + struct ipa_ipfltri_rule_eq *eq_atrb); + +/* + * ipahal_rt_parse_hw_rule() - Parse H/W formated rt rule + * Given the rule address, read the rule info from H/W and parse it. + * @rule_addr: Rule address (virtual memory) + * @rule: Out parameter for parsed rule info + */ +int ipahal_rt_parse_hw_rule(u8 *rule_addr, + struct ipahal_rt_rule_entry *rule); + +/* + * ipahal_flt_parse_hw_rule() - Parse H/W formated flt rule + * Given the rule address, read the rule info from H/W and parse it. + * @rule_addr: Rule address (virtual memory) + * @rule: Out parameter for parsed rule info + */ +int ipahal_flt_parse_hw_rule(u8 *rule_addr, + struct ipahal_flt_rule_entry *rule); + +/* + * ipa_fltrt_get_aligned_lcl_bdy_size() - Calculate real SRAM block aligned size + * required for flt table bodies + * @num_lcl_tbls: [in] Number of the tables + * @total_sz_lcl_tbls: [in] The size in driver cashe + */ +u32 ipa_fltrt_get_aligned_lcl_bdy_size(u32 num_lcl_tbls, u32 total_sz_lcl_tbls); + + +#endif /* _IPAHAL_FLTRT_H_ */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_fltrt_i.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_fltrt_i.h new file mode 100644 index 0000000000..a5ac3180c9 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_fltrt_i.h @@ -0,0 +1,466 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _IPAHAL_FLTRT_I_H_ +#define _IPAHAL_FLTRT_I_H_ + +/* + * enum ipa_fltrt_equations - RULE equations + * These are names values to the equations that can be used + * The HAL layer holds mapping between these names and H/W + * presentation. + */ +enum ipa_fltrt_equations { + IPA_TOS_EQ, + IPA_PROTOCOL_EQ, + IPA_TC_EQ, + IPA_OFFSET_MEQ128_0, + IPA_OFFSET_MEQ128_1, + IPA_OFFSET_MEQ32_0, + IPA_OFFSET_MEQ32_1, + IPA_IHL_OFFSET_MEQ32_0, + IPA_IHL_OFFSET_MEQ32_1, + IPA_METADATA_COMPARE, + IPA_IHL_OFFSET_RANGE16_0, + IPA_IHL_OFFSET_RANGE16_1, + IPA_IHL_OFFSET_EQ_32, + IPA_IHL_OFFSET_EQ_16, + IPA_FL_EQ, + IPA_IS_FRAG, + IPA_IS_PURE_ACK, + IPA_EQ_MAX, +}; + +/* Width and Alignment values for H/W structures. + * Specific for IPA version. + */ +#define IPA3_0_HW_TBL_SYSADDR_ALIGNMENT (127) +#define IPA3_0_HW_TBL_LCLADDR_ALIGNMENT (7) +#define IPA3_0_HW_TBL_BLK_SIZE_ALIGNMENT (127) +#define IPA3_0_HW_TBL_WIDTH (8) +#define IPA3_0_HW_TBL_HDR_WIDTH (8) +#define IPA3_0_HW_TBL_ADDR_MASK (127) +#define IPA3_0_HW_RULE_BUF_SIZE (256) +#define IPA3_0_HW_RULE_START_ALIGNMENT (7) +#define IPA3_0_HW_RULE_PREFETCH_BUF_SIZE (256) + + +/* + * Rules Priority. + * Needed due to rules classification to hashable and non-hashable. + * Higher priority is lower in number. i.e. 0 is highest priority + */ +#define IPA3_0_RULE_MAX_PRIORITY (0) +#define IPA3_0_RULE_MIN_PRIORITY (1023) + +#define IPA5_0_RULE_MAX_PRIORITY (0) +#define IPA5_0_RULE_MIN_PRIORITY (255) + +/* + * RULE ID, bit length (e.g. 10 bits). + */ +#define IPA3_0_RULE_ID_BIT_LEN (10) +#define IPA3_0_LOW_RULE_ID (1) + +/* + * COUNTER ID, LOW COUNTER ID. + */ +#define IPA4_5_LOW_CNT_ID (1) + +/** + * struct ipa3_0_rt_rule_hw_hdr - HW header of IPA routing rule + * @word: routing rule header properties + * @en_rule: enable rule - Equation bit fields + * @pipe_dest_idx: destination pipe index + * @system: Is referenced header is lcl or sys memory + * @hdr_offset: header offset + * @proc_ctx: whether hdr_offset points to header table or to + * header processing context table + * @priority: Rule priority. Added to distinguish rules order + * at the integrated table consisting from hashable and + * non-hashable parts + * @rsvd1: reserved bits + * @retain_hdr: added to add back to the packet the header removed + * as part of header removal. This will be done as part of + * header insertion block. + * @rule_id: rule ID that will be returned in the packet status + * @rsvd2: reserved bits + */ +struct ipa3_0_rt_rule_hw_hdr { + union { + u64 word; + struct { + u64 en_rule:16; + u64 pipe_dest_idx:5; + u64 system:1; + u64 hdr_offset:9; + u64 proc_ctx:1; + u64 priority:10; + u64 rsvd1:5; + u64 retain_hdr:1; + u64 rule_id:10; + u64 rsvd2:6; + } hdr; + } u; +}; + +/** + * struct ipa4_5_rt_rule_hw_hdr - HW header of IPA routing rule + * @word: routing rule header properties + * @en_rule: enable rule - Equation bit fields + * @pipe_dest_idx: destination pipe index + * @system: Is referenced header is lcl or sys memory + * @hdr_offset: header offset + * @proc_ctx: whether hdr_offset points to header table or to + * header processing context table + * @priority: Rule priority. Added to distinguish rules order + * at the integrated table consisting from hashable and + * non-hashable parts + * @stats_cnt_idx_msb: stats cnt index msb + * @rsvd2: reserved bits + * @retain_hdr: added to add back to the packet the header removed + * as part of header removal. This will be done as part of + * header insertion block. + * @rule_id: rule ID that will be returned in the packet status + * @stats_cnt_idx_lsb: stats cnt index lsb + */ +struct ipa4_5_rt_rule_hw_hdr { + union { + u64 word; + struct { + u64 en_rule:16; + u64 pipe_dest_idx:5; + u64 system:1; + u64 hdr_offset:9; + u64 proc_ctx:1; + u64 priority:10; + u64 stats_cnt_idx_msb : 2; + u64 rsvd2 : 3; + u64 retain_hdr:1; + u64 rule_id:10; + u64 stats_cnt_idx_lsb : 6; + } hdr; + } u; +}; + +/** + * struct ipa5_0_rt_rule_hw_hdr - HW header of IPA routing rule + * @word: routing rule header properties + * @en_rule: enable rule - Equation bit fields + * @pipe_dest_idx: destination pipe index + * @stats_cnt_idx_lsb: stats cnt index + * @priority: Rule priority. Added to distinguish rules order + * at the integrated table consisting from hashable and + * non-hashable parts + * @rsvd: reserved bit + * @close_aggr_irq_mod: close aggregation/coalescing and close GSI + * interrupt moderation + * @rule_id: rule ID that will be returned in the packet status + * @hdr_offset: header offset + * @proc_ctx: whether hdr_offset points to header table or to + * header processing context table + * @retain_hdr: added to add back to the packet the header removed + * as part of header removal. This will be done as part of + * header insertion block. + * @system: Is referenced header is lcl or sys memory + */ +struct ipa5_0_rt_rule_hw_hdr { + union { + u64 word; + struct { + u64 en_rule : 16; + u64 pipe_dest_idx : 8; + u64 stats_cnt_idx : 8; + u64 priority : 8; + u64 rsvd : 1; + u64 close_aggr_irq_mod : 1; + u64 rule_id : 10; + u64 hdr_offset : 9; + u64 proc_ctx : 1; + u64 retain_hdr : 1; + u64 system : 1; + } hdr; + } u; +}; + +/** + * struct ipa5_5_rt_rule_hw_hdr - HW header of IPA routing rule + * @word: routing rule header properties + * @en_rule: enable rule - Equation bit fields + * @pipe_dest_idx: destination pipe index + * @stats_cnt_idx_lsb: stats cnt index + * @priority: Rule priority. Added to distinguish rules order + * at the integrated table consisting from hashable and + * non-hashable parts + * @ext_hdr: indicates whethere extention header is present or not. + * @close_aggr_irq_mod: close aggregation/coalescing and close GSI + * interrupt moderation + * @rule_id: rule ID that will be returned in the packet status + * @hdr_offset: header offset + * @proc_ctx: whether hdr_offset points to header table or to + * header processing context table + * @retain_hdr: added to add back to the packet the header removed + * as part of header removal. This will be done as part of + * header insertion block. + * @system: Is referenced header is lcl or sys memory + */ +struct ipa5_5_rt_rule_hw_hdr { + union { + u64 word; + struct { + u64 en_rule : 16; + u64 pipe_dest_idx : 8; + u64 stats_cnt_idx : 8; + u64 priority : 8; + u64 ext_hdr : 1; + u64 close_aggr_irq_mod : 1; + u64 rule_id : 10; + u64 hdr_offset : 9; + u64 proc_ctx : 1; + u64 retain_hdr : 1; + u64 system : 1; + } hdr; + } u; +}; + +/** + * struct ipa5_5_rt_rule_hw_hdr_ext - HW header of IPA routing rule + * extention + * @word: routing rule extention header properties + * @ttl: enable ttl decrement. + * @qos_class: qos classification value. + * @skip_ingress: Skip ingress policing. + * @rsvd: Reserved bits + */ +struct ipa5_5_rt_rule_hw_hdr_ext { + union { + u16 word; + struct { + u16 ttl : 1; + u16 qos_class : 6; + u16 skip_ingress : 1; + u16 rsvd : 8; + } hdr; + } u; +}; + + +/** + * struct ipa3_0_flt_rule_hw_hdr - HW header of IPA filter rule + * @word: filtering rule properties + * @en_rule: enable rule + * @action: post filtering action + * @rt_tbl_idx: index in routing table + * @retain_hdr: added to add back to the packet the header removed + * as part of header removal. This will be done as part of + * header insertion block. + * @rsvd1: reserved bits + * @priority: Rule priority. Added to distinguish rules order + * at the integrated table consisting from hashable and + * non-hashable parts + * @rsvd2: reserved bits + * @rule_id: rule ID that will be returned in the packet status + * @rsvd3: reserved bits + */ +struct ipa3_0_flt_rule_hw_hdr { + union { + u64 word; + struct { + u64 en_rule:16; + u64 action:5; + u64 rt_tbl_idx:5; + u64 retain_hdr:1; + u64 rsvd1:5; + u64 priority:10; + u64 rsvd2:6; + u64 rule_id:10; + u64 rsvd3:6; + } hdr; + } u; +}; + +/** + * struct ipa4_0_flt_rule_hw_hdr - HW header of IPA filter rule + * @word: filtering rule properties + * @en_rule: enable rule + * @action: post filtering action + * @rt_tbl_idx: index in routing table + * @retain_hdr: added to add back to the packet the header removed + * as part of header removal. This will be done as part of + * header insertion block. + * @pdn_idx: in case of go to src nat action possible to input the pdn index to + * the NAT block + * @set_metadata: enable metadata replacement in the NAT block + * @priority: Rule priority. Added to distinguish rules order + * at the integrated table consisting from hashable and + * non-hashable parts + * @rsvd2: reserved bits + * @rule_id: rule ID that will be returned in the packet status + * @rsvd3: reserved bits + */ +struct ipa4_0_flt_rule_hw_hdr { + union { + u64 word; + struct { + u64 en_rule : 16; + u64 action : 5; + u64 rt_tbl_idx : 5; + u64 retain_hdr : 1; + u64 pdn_idx : 4; + u64 set_metadata : 1; + u64 priority : 10; + u64 rsvd2 : 6; + u64 rule_id : 10; + u64 rsvd3 : 6; + } hdr; + } u; +}; + +/** + * struct ipa4_5_flt_rule_hw_hdr - HW header of IPA filter rule + * @word: filtering rule properties + * @en_rule: enable rule + * @action: post filtering action + * @rt_tbl_idx: index in routing table + * @retain_hdr: added to add back to the packet the header removed + * as part of header removal. This will be done as part of + * header insertion block. + * @pdn_idx: in case of go to src nat action possible to input the pdn index to + * the NAT block + * @set_metadata: enable metadata replacement in the NAT block + * @priority: Rule priority. Added to distinguish rules order + * at the integrated table consisting from hashable and + * non-hashable parts + * @stats_cnt_idx_msb: stats cnt index msb + * @rsvd2: reserved bits + * @rule_id: rule ID that will be returned in the packet status + * @stats_cnt_idx_lsb: stats cnt index lsb + */ +struct ipa4_5_flt_rule_hw_hdr { + union { + u64 word; + struct { + u64 en_rule : 16; + u64 action : 5; + u64 rt_tbl_idx : 5; + u64 retain_hdr : 1; + u64 pdn_idx : 4; + u64 set_metadata : 1; + u64 priority : 10; + u64 stats_cnt_idx_msb : 2; + u64 rsvd2 : 4; + u64 rule_id : 10; + u64 stats_cnt_idx_lsb : 6; + } hdr; + } u; +}; + +/** + * struct ipa5_0_flt_rule_hw_hdr - HW header of IPA filter rule + * @word: filtering rule properties + * @en_rule: enable rule + * @rt_tbl_idx: index in routing table + * @stats_cnt_idx: stats cnt index + * @priority: Rule priority. Added to distinguish rules order + * at the integrated table consisting from hashable and + * non-hashable parts + * @close_aggr_irq_mod: close aggregation/coalescing and close GSI + * interrupt moderation + * @rule_id: rule ID that will be returned in the packet status + * @action: post filtering action + * @pdn_idx: in case of go to src nat action possible to input the pdn index to + * the NAT block + * @set_metadata: enable metadata replacement in the NAT block + * @retain_hdr: added to add back to the packet the header removed + * as part of header removal. This will be done as part of + * header insertion block. + * @rsvd1\rsvd2: reserved bits + */ +struct ipa5_0_flt_rule_hw_hdr { + union { + u64 word; + struct { + u64 en_rule : 16; + u64 rt_tbl_idx : 8; + u64 stats_cnt_idx : 8; + u64 priority : 8; + u64 rsvd1 : 1; + u64 close_aggr_irq_mod : 1; + u64 rule_id : 10; + u64 action : 5; + u64 pdn_idx : 4; + u64 set_metadata : 1; + u64 retain_hdr : 1; + u64 rsvd2 : 1; + } hdr; + } u; +}; + +/** + * struct ipa5_5_flt_rule_hw_hdr - HW header of IPA filter rule + * @word: filtering rule properties + * @en_rule: enable rule + * @rt_tbl_idx: index in routing table + * @stats_cnt_idx: stats cnt index + * @priority: Rule priority. Added to distinguish rules order + * at the integrated table consisting from hashable and + * non-hashable parts + * @ext_hdr: indicates whethere extention header is present or not. + * @close_aggr_irq_mod: close aggregation/coalescing and close GSI + * interrupt moderation + * @rule_id: rule ID that will be returned in the packet status + * @action: post filtering action + * @pdn_idx: in case of go to src nat action possible to input the pdn index to + * the NAT block + * @set_metadata: enable metadata replacement in the NAT block + * @retain_hdr: added to add back to the packet the header removed + * as part of header removal. This will be done as part of + * header insertion block. + * @rsvd: reserved bits + */ +struct ipa5_5_flt_rule_hw_hdr { + union { + u64 word; + struct { + u64 en_rule : 16; + u64 rt_tbl_idx : 8; + u64 stats_cnt_idx : 8; + u64 priority : 8; + u64 ext_hdr : 1; + u64 close_aggr_irq_mod : 1; + u64 rule_id : 10; + u64 action : 5; + u64 pdn_idx : 4; + u64 set_metadata : 1; + u64 retain_hdr : 1; + u64 rsvd : 1; + } hdr; + } u; +}; + +/** + * struct ipa5_5_flt_rule_hw_hdr_ext - HW header of IPA filter rule + * extention + * @word: filtering rule extention header properties + * @ttl: enable ttl decrement. + * @qos_class: qos classification value. + * @rsvd: Reserved bits + */ +struct ipa5_5_flt_rule_hw_hdr_ext { + union { + u16 word; + struct { + u16 ttl : 1; + u16 qos_class : 6; + u16 rsvd : 9; + } hdr; + } u; +}; + +int ipahal_fltrt_init(enum ipa_hw_type ipa_hw_type); +void ipahal_fltrt_destroy(void); + +#endif /* _IPAHAL_FLTRT_I_H_ */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_hw_stats.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_hw_stats.c new file mode 100644 index 0000000000..786e928cf4 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_hw_stats.c @@ -0,0 +1,1107 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ipahal.h" +#include "ipahal_hw_stats.h" +#include "ipahal_hw_stats_i.h" +#include "ipahal_i.h" + +struct ipahal_hw_stats_obj { + struct ipahal_stats_init_pyld *(*generate_init_pyld)(void *params, + bool is_atomic_ctx); + int (*get_offset)(void *params, struct ipahal_stats_offset *out); + int (*parse_stats)(void *init_params, void *raw_stats, + void *parsed_stats); +}; + +static int _count_ones(u32 number) +{ + int count = 0; + + while (number) { + count++; + number = number & (number - 1); + } + + return count; +} + +static struct ipahal_stats_init_pyld *ipahal_generate_init_pyld_quota( + void *params, bool is_atomic_ctx) +{ + struct ipahal_stats_init_pyld *pyld; + struct ipahal_stats_init_quota *in = + (struct ipahal_stats_init_quota *)params; + int entries = _count_ones(in->enabled_bitmask[0]); + + IPAHAL_DBG_LOW("entries = %d\n", entries); + pyld = IPAHAL_MEM_ALLOC(sizeof(*pyld) + + entries * sizeof(struct ipahal_stats_quota_hw), is_atomic_ctx); + if (!pyld) { + IPAHAL_ERR("no mem\n"); + return NULL; + } + + pyld->len = entries * sizeof(struct ipahal_stats_quota_hw); + return pyld; +} + +static struct ipahal_stats_init_pyld *ipahal_generate_init_pyld_quota_v5_0( + void *params, bool is_atomic_ctx) +{ + struct ipahal_stats_init_pyld *pyld; + struct ipahal_stats_init_quota *in = + (struct ipahal_stats_init_quota *)params; + int i; + int entries = 0; + + for (i = 0; i < IPAHAL_IPA5_PIPE_REG_NUM; i++) + entries += _count_ones(in->enabled_bitmask[i]); + + IPAHAL_DBG_LOW("entries = %d\n", entries); + pyld = IPAHAL_MEM_ALLOC(sizeof(*pyld) + + entries * sizeof(struct ipahal_stats_quota_hw), is_atomic_ctx); + if (!pyld) { + IPAHAL_ERR("no mem\n"); + return NULL; + } + + pyld->len = entries * sizeof(struct ipahal_stats_quota_hw); + return pyld; +} + +static int ipahal_get_offset_quota(void *params, + struct ipahal_stats_offset *out) +{ + struct ipahal_stats_get_offset_quota *in = + (struct ipahal_stats_get_offset_quota *)params; + int entries = _count_ones(in->init.enabled_bitmask[0]); + + IPAHAL_DBG_LOW("\n"); + out->offset = 0; + out->size = entries * sizeof(struct ipahal_stats_quota_hw); + + return 0; +} + +static int ipahal_get_offset_quota_v5_0(void *params, + struct ipahal_stats_offset *out) +{ + struct ipahal_stats_get_offset_quota *in = + (struct ipahal_stats_get_offset_quota *)params; + int i, entries = 0; + + for (i = 0; i < IPAHAL_IPA5_PIPE_REG_NUM; i++) + entries += _count_ones(in->init.enabled_bitmask[i]); + + IPAHAL_DBG_LOW("\n"); + out->offset = 0; + out->size = entries * sizeof(struct ipahal_stats_quota_hw); + + return 0; +} + +static int ipahal_parse_stats_quota(void *init_params, void *raw_stats, + void *parsed_stats) +{ + struct ipahal_stats_init_quota *init = + (struct ipahal_stats_init_quota *)init_params; + struct ipahal_stats_quota_hw *raw_hw = + (struct ipahal_stats_quota_hw *)raw_stats; + struct ipahal_stats_quota_all *out = + (struct ipahal_stats_quota_all *)parsed_stats; + int stat_idx = 0; + int i; + + memset(out, 0, sizeof(*out)); + IPAHAL_DBG_LOW("\n"); + for (i = 0; i < IPAHAL_MAX_PIPES; i++) { + if (init->enabled_bitmask[0] & (1 << i)) { + IPAHAL_DBG_LOW("pipe %d stat_idx %d\n", i, stat_idx); + out->stats[i].num_ipv4_bytes = + raw_hw[stat_idx].num_ipv4_bytes; + out->stats[i].num_ipv4_pkts = + raw_hw[stat_idx].num_ipv4_pkts; + out->stats[i].num_ipv6_pkts = + raw_hw[stat_idx].num_ipv6_pkts; + out->stats[i].num_ipv6_bytes = + raw_hw[stat_idx].num_ipv6_bytes; + stat_idx++; + } + } + + return 0; +} + +static int ipahal_parse_stats_quota_v5_0(void *init_params, void *raw_stats, + void *parsed_stats) +{ + struct ipahal_stats_init_quota *init = + (struct ipahal_stats_init_quota *)init_params; + struct ipahal_stats_quota_hw *raw_hw = + (struct ipahal_stats_quota_hw *)raw_stats; + struct ipahal_stats_quota_all *out = + (struct ipahal_stats_quota_all *)parsed_stats; + int stat_idx = 0; + int i, reg_idx; + + memset(out, 0, sizeof(*out)); + IPAHAL_DBG_LOW("\n"); + for (i = 0; i < IPAHAL_IPA5_PIPES_NUM; i++) { + reg_idx = ipahal_get_ep_reg_idx(i); + if (init->enabled_bitmask[reg_idx] & ipahal_get_ep_bit(i)) { + IPAHAL_DBG_LOW("pipe %d stat_idx %d\n", i, stat_idx); + out->stats[i].num_ipv4_bytes = + raw_hw[stat_idx].num_ipv4_bytes; + out->stats[i].num_ipv4_pkts = + raw_hw[stat_idx].num_ipv4_pkts; + out->stats[i].num_ipv6_pkts = + raw_hw[stat_idx].num_ipv6_pkts; + out->stats[i].num_ipv6_bytes = + raw_hw[stat_idx].num_ipv6_bytes; + stat_idx++; + } + } + + return 0; +} + +static struct ipahal_stats_init_pyld *ipahal_generate_init_pyld_tethering( + void *params, bool is_atomic_ctx) +{ + struct ipahal_stats_init_pyld *pyld; + struct ipahal_stats_init_tethering *in = + (struct ipahal_stats_init_tethering *)params; + int hdr_entries = _count_ones(in->prod_bitmask[0]); + int entries = 0; + int i; + void *pyld_ptr; + u32 incremental_offset; + + IPAHAL_DBG_LOW("prod entries = %d\n", hdr_entries); + for (i = 0; i < sizeof(in->prod_bitmask[0]) * 8; i++) { + if (in->prod_bitmask[0] & (1 << i)) { + if (in->cons_bitmask[i][0] == 0) { + IPAHAL_ERR("no cons bitmask for prod %d\n", i); + return NULL; + } + entries += _count_ones(in->cons_bitmask[i][0]); + } + } + IPAHAL_DBG_LOW("sum all entries = %d\n", entries); + + pyld = IPAHAL_MEM_ALLOC(sizeof(*pyld) + + hdr_entries * sizeof(struct ipahal_stats_tethering_hdr_hw) + + entries * sizeof(struct ipahal_stats_tethering_hw), + is_atomic_ctx); + if (!pyld) + return NULL; + + pyld->len = hdr_entries * sizeof(struct ipahal_stats_tethering_hdr_hw) + + entries * sizeof(struct ipahal_stats_tethering_hw); + + pyld_ptr = pyld->data; + incremental_offset = + (hdr_entries * sizeof(struct ipahal_stats_tethering_hdr_hw)) + / 8; + for (i = 0; i < sizeof(in->prod_bitmask[0]) * 8; i++) { + if (in->prod_bitmask[0] & (1 << i)) { + struct ipahal_stats_tethering_hdr_hw *hdr = pyld_ptr; + + hdr->dst_mask = in->cons_bitmask[i][0]; + hdr->offset = incremental_offset; + IPAHAL_DBG_LOW("hdr->dst_mask=0x%x\n", hdr->dst_mask); + IPAHAL_DBG_LOW("hdr->offset=0x%x\n", hdr->offset); + /* add the stats entry */ + incremental_offset += _count_ones( + in->cons_bitmask[i][0]) * + sizeof(struct ipahal_stats_tethering_hw) / 8; + pyld_ptr += sizeof(*hdr); + } + } + + return pyld; +} + +static struct ipahal_stats_init_pyld *ipahal_generate_init_pyld_tethering_v5_0( + void *params, bool is_atomic_ctx) +{ + struct ipahal_stats_init_pyld *pyld; + struct ipahal_stats_init_tethering *in = + (struct ipahal_stats_init_tethering *)params; + int hdr_entries = 0; + int entries = 0; + int i, j, reg_idx; + void *pyld_ptr; + u32 incremental_offset; + + for (i = 0; i < IPAHAL_IPA5_PIPE_REG_NUM; i++) + hdr_entries += _count_ones(in->prod_bitmask[i]); + + IPAHAL_DBG_LOW("prod entries = %d\n", hdr_entries); + reg_idx = 0; + for (i = 0; i < IPAHAL_IPA5_PIPES_NUM; i++) { + if (i > 0 && !(i % IPAHAL_MAX_PIPES_PER_REG)) { + reg_idx++; + } + if ((reg_idx < IPAHAL_IPA5_PIPE_REG_NUM) && + (in->prod_bitmask[reg_idx] & ipahal_get_ep_bit(i))) { + bool has_cons = false; + + for (j = 0; j < IPAHAL_IPA5_PIPE_REG_NUM; j++) { + if (in->cons_bitmask[i][j]) { + has_cons = true; + entries += + _count_ones(in->cons_bitmask[i][j]); + } + } + if (!has_cons) { + IPAHAL_ERR("no cons bitmask for prod %d\n", i); + return NULL; + } + } + } + IPAHAL_DBG_LOW("sum all entries = %d\n", entries); + + pyld = IPAHAL_MEM_ALLOC(sizeof(*pyld) + + hdr_entries * + sizeof(struct ipahal_stats_tethering_hdr_v5_0_hw) + + entries * sizeof(struct ipahal_stats_tethering_hw), + is_atomic_ctx); + if (!pyld) + return NULL; + + pyld->len = hdr_entries * + sizeof(struct ipahal_stats_tethering_hdr_v5_0_hw) + + entries * sizeof(struct ipahal_stats_tethering_hw); + + pyld_ptr = pyld->data; + + /* + * Note that the address of the offset in the RAM line is of RAM line + *(8-byte address) and not like the address in the “BASE” register, + * which is a byte address + */ + incremental_offset = + (hdr_entries * + sizeof(struct ipahal_stats_tethering_hdr_v5_0_hw)) + / 8; + + reg_idx = 0; + for (i = 0; i < IPAHAL_IPA5_PIPES_NUM; i++) { + + if (i > 0 && !(i % IPAHAL_MAX_PIPES_PER_REG)) + reg_idx++; + + if ((reg_idx < IPAHAL_IPA5_PIPE_REG_NUM) && + (in->prod_bitmask[reg_idx] & ipahal_get_ep_bit(i))) { + struct ipahal_stats_tethering_hdr_v5_0_hw *hdr = + pyld_ptr; + // TODO: for future versions of num HW consumers > 16 + hdr->dst_mask_31_0 = + ((in->cons_bitmask[i][0] >> IPAHAL_IPA5_PRODUCER_PIPE_NUM) | + (in->cons_bitmask[i][1] << + (IPAHAL_MAX_PIPES_PER_REG - IPAHAL_IPA5_PRODUCER_PIPE_NUM))); + hdr->dst_mask_63_32 = + in->cons_bitmask[i][1] >> IPAHAL_IPA5_PRODUCER_PIPE_NUM; + + // TODO: for future when num pipes > 64 + hdr->dst_mask_95_64 = 0; + hdr->dst_mask_127_96 = 0; + hdr->offset = incremental_offset; + IPAHAL_DBG_LOW("Pipe: %d\n", i); + IPAHAL_DBG_LOW("hdr->dst_mask_31_0=[0x%x], hdr->dst_mask_63_32=[0x%x]\n", + hdr->dst_mask_31_0, hdr->dst_mask_63_32); + IPAHAL_DBG_LOW("hdr->dst_mask_95_64=[0x%x], hdr->dst_mask_127_96=[0x%x]\n", + hdr->dst_mask_95_64, hdr->dst_mask_127_96); + IPAHAL_DBG_LOW("hdr->offset=0x%x\n", hdr->offset); + /* add the stats entry */ + incremental_offset += + (_count_ones(in->cons_bitmask[i][0]) + + _count_ones(in->cons_bitmask[i][1])) * + sizeof(struct ipahal_stats_tethering_hw) / 8; + pyld_ptr += sizeof(*hdr); + } + } + + return pyld; +} + +static struct ipahal_stats_init_pyld *ipahal_generate_init_pyld_tethering_v5_2( + void *params, bool is_atomic_ctx) +{ + struct ipahal_stats_init_pyld *pyld; + struct ipahal_stats_init_tethering *in = + (struct ipahal_stats_init_tethering *)params; + int hdr_entries = 0; + int entries = 0; + int i, j, reg_idx; + void *pyld_ptr; + u32 incremental_offset; + + for (i = 0; i < IPAHAL_IPA5_PIPE_REG_NUM; i++) + hdr_entries += _count_ones(in->prod_bitmask[i]); + + IPAHAL_DBG_LOW("prod entries = %d\n", hdr_entries); + reg_idx = 0; + for (i = 0; i < IPAHAL_IPA5_PIPES_NUM; i++) { + if (i > 0 && !(i % IPAHAL_MAX_PIPES_PER_REG)) + reg_idx++; + if ((reg_idx < IPAHAL_IPA5_PIPE_REG_NUM) && + (in->prod_bitmask[reg_idx] & ipahal_get_ep_bit(i))) { + bool has_cons = false; + + for (j = 0; j < IPAHAL_IPA5_PIPE_REG_NUM; j++) { + if (in->cons_bitmask[i][j]) { + has_cons = true; + entries += + _count_ones(in->cons_bitmask[i][j]); + } + } + if (!has_cons) { + IPAHAL_ERR("no cons bitmask for prod %d\n", i); + return NULL; + } + } + } + IPAHAL_DBG_LOW("sum all entries = %d\n", entries); + + pyld = IPAHAL_MEM_ALLOC(sizeof(*pyld) + + hdr_entries * + sizeof(struct ipahal_stats_tethering_hdr_v5_0_hw) + + entries * sizeof(struct ipahal_stats_tethering_hw), + is_atomic_ctx); + if (!pyld) + return NULL; + + pyld->len = hdr_entries * + sizeof(struct ipahal_stats_tethering_hdr_v5_0_hw) + + entries * sizeof(struct ipahal_stats_tethering_hw); + + pyld_ptr = pyld->data; + + /* + * Note that the address of the offset in the RAM line is of RAM line + *(8-byte address) and not like the address in the “BASE” register, + * which is a byte address + */ + incremental_offset = + (hdr_entries * + sizeof(struct ipahal_stats_tethering_hdr_v5_0_hw)) + / 8; + + reg_idx = 0; + for (i = 0; i < IPAHAL_IPA5_PIPES_NUM; i++) { + + if (i > 0 && !(i % IPAHAL_MAX_PIPES_PER_REG)) + reg_idx++; + + if ((reg_idx < IPAHAL_IPA5_PIPE_REG_NUM) && + (in->prod_bitmask[reg_idx] & ipahal_get_ep_bit(i))) { + struct ipahal_stats_tethering_hdr_v5_0_hw *hdr = + pyld_ptr; + // TODO: for future versions of num HW consumers > 16 + hdr->dst_mask_31_0 = + ((in->cons_bitmask[i][0] >> IPAHAL_IPA5_2_PRODUCER_PIPE_NUM) | + (in->cons_bitmask[i][1] << + (IPAHAL_MAX_PIPES_PER_REG - IPAHAL_IPA5_2_PRODUCER_PIPE_NUM))); + hdr->dst_mask_63_32 = + in->cons_bitmask[i][1] >> IPAHAL_IPA5_2_PRODUCER_PIPE_NUM; + + // TODO: for future when num pipes > 64 + hdr->dst_mask_95_64 = 0; + hdr->dst_mask_127_96 = 0; + hdr->offset = incremental_offset; + IPAHAL_DBG_LOW("Pipe: %d\n", i); + IPAHAL_DBG_LOW("hdr->dst_mask_31_0=[0x%x], hdr->dst_mask_63_32=[0x%x]\n", + hdr->dst_mask_31_0, hdr->dst_mask_63_32); + IPAHAL_DBG_LOW("hdr->dst_mask_95_64=[0x%x], hdr->dst_mask_127_96=[0x%x]\n", + hdr->dst_mask_95_64, hdr->dst_mask_127_96); + IPAHAL_DBG_LOW("hdr->offset=0x%x\n", hdr->offset); + /* add the stats entry */ + incremental_offset += + (_count_ones(in->cons_bitmask[i][0]) + + _count_ones(in->cons_bitmask[i][1])) * + sizeof(struct ipahal_stats_tethering_hw) / 8; + pyld_ptr += sizeof(*hdr); + } + } + + return pyld; +} + +static int ipahal_get_offset_tethering(void *params, + struct ipahal_stats_offset *out) +{ + struct ipahal_stats_get_offset_tethering *in = + (struct ipahal_stats_get_offset_tethering *)params; + int entries = 0; + int i; + + for (i = 0; i < sizeof(in->init.prod_bitmask[0]) * 8; i++) { + if (in->init.prod_bitmask[0] & (1 << i)) { + if (in->init.cons_bitmask[i][0] == 0) { + IPAHAL_ERR("no cons bitmask for prod %d\n", i); + return -EPERM; + } + entries += _count_ones(in->init.cons_bitmask[i][0]); + } + } + IPAHAL_DBG_LOW("sum all entries = %d\n", entries); + + /* skip the header */ + out->offset = _count_ones(in->init.prod_bitmask[0]) * + sizeof(struct ipahal_stats_tethering_hdr_hw); + out->size = entries * sizeof(struct ipahal_stats_tethering_hw); + + return 0; +} + +static int ipahal_get_offset_tethering_v5_0(void *params, + struct ipahal_stats_offset *out) +{ + struct ipahal_stats_get_offset_tethering *in = + (struct ipahal_stats_get_offset_tethering *)params; + int entries = 0; + int i, j, reg_idx; + + for (i = 0; i < IPAHAL_IPA5_PIPES_NUM; i++) { + reg_idx = ipahal_get_ep_reg_idx(i); + + if (in->init.prod_bitmask[reg_idx] & ipahal_get_ep_bit(i)) { + bool has_cons = false; + + for (j = 0; j < IPAHAL_IPA5_PIPE_REG_NUM; j++) { + if (in->init.cons_bitmask[i][j]) { + has_cons = true; + entries +=_count_ones( + in->init.cons_bitmask[i][j]); + } + } + if (!has_cons) { + IPAHAL_ERR("no cons bitmask for prod %d\n", i); + return -EPERM; + } + } + } + IPAHAL_DBG_LOW("sum all entries = %d\n", entries); + + /* skip the header */ + out->offset = 0; + for (j = 0; j < IPAHAL_IPA5_PIPE_REG_NUM; j++) + out->offset += _count_ones(in->init.prod_bitmask[j]) * + sizeof(struct ipahal_stats_tethering_hdr_v5_0_hw); + + out->size = entries * sizeof(struct ipahal_stats_tethering_hw); + + return 0; +} + +static int ipahal_parse_stats_tethering(void *init_params, void *raw_stats, + void *parsed_stats) +{ + struct ipahal_stats_init_tethering *init = + (struct ipahal_stats_init_tethering *)init_params; + struct ipahal_stats_tethering_hw *raw_hw = + (struct ipahal_stats_tethering_hw *)raw_stats; + struct ipahal_stats_tethering_all *out = + (struct ipahal_stats_tethering_all *)parsed_stats; + int i, j; + int stat_idx = 0; + + memset(out, 0, sizeof(*out)); + IPAHAL_DBG_LOW("\n"); + for (i = 0; i < IPAHAL_MAX_PIPES; i++) { + for (j = 0; j < IPAHAL_MAX_PIPES; j++) { + if ((init->prod_bitmask[0] & (1 << i)) && + init->cons_bitmask[i][0] & (1 << j)) { + IPAHAL_DBG_LOW("prod %d cons %d\n", i, j); + IPAHAL_DBG_LOW("stat_idx %d\n", stat_idx); + out->stats[i][j].num_ipv4_bytes = + raw_hw[stat_idx].num_ipv4_bytes; + IPAHAL_DBG_LOW("num_ipv4_bytes %lld\n", + out->stats[i][j].num_ipv4_bytes); + out->stats[i][j].num_ipv4_pkts = + raw_hw[stat_idx].num_ipv4_pkts; + IPAHAL_DBG_LOW("num_ipv4_pkts %lld\n", + out->stats[i][j].num_ipv4_pkts); + out->stats[i][j].num_ipv6_pkts = + raw_hw[stat_idx].num_ipv6_pkts; + IPAHAL_DBG_LOW("num_ipv6_pkts %lld\n", + out->stats[i][j].num_ipv6_pkts); + out->stats[i][j].num_ipv6_bytes = + raw_hw[stat_idx].num_ipv6_bytes; + IPAHAL_DBG_LOW("num_ipv6_bytes %lld\n", + out->stats[i][j].num_ipv6_bytes); + stat_idx++; + } + } + } + + return 0; +} + +static int ipahal_parse_stats_tethering_v5_0(void *init_params, void *raw_stats, + void *parsed_stats) +{ + struct ipahal_stats_init_tethering *init = + (struct ipahal_stats_init_tethering *)init_params; + struct ipahal_stats_tethering_hw *raw_hw = + (struct ipahal_stats_tethering_hw *)raw_stats; + struct ipahal_stats_tethering_all *out = + (struct ipahal_stats_tethering_all *)parsed_stats; + int i, j; + int stat_idx = 0; + int prod_idx, cons_idx; + + memset(out, 0, sizeof(*out)); + IPAHAL_DBG_LOW("\n"); + for (i = 0; i < IPAHAL_IPA5_PIPES_NUM; i++) { + prod_idx = ipahal_get_ep_reg_idx(i); + for (j = 0; j < IPAHAL_IPA5_PIPES_NUM; j++) { + cons_idx = ipahal_get_ep_reg_idx(j); + if ((init->prod_bitmask[prod_idx] & + ipahal_get_ep_bit(i)) && + init->cons_bitmask[i][cons_idx] & + ipahal_get_ep_bit(j)) { + IPAHAL_DBG_LOW("prod %d cons %d\n", i, j); + IPAHAL_DBG_LOW("stat_idx %d\n", stat_idx); + out->stats[i][j].num_ipv4_bytes = + raw_hw[stat_idx].num_ipv4_bytes; + IPAHAL_DBG_LOW("num_ipv4_bytes %lld\n", + out->stats[i][j].num_ipv4_bytes); + out->stats[i][j].num_ipv4_pkts = + raw_hw[stat_idx].num_ipv4_pkts; + IPAHAL_DBG_LOW("num_ipv4_pkts %lld\n", + out->stats[i][j].num_ipv4_pkts); + out->stats[i][j].num_ipv6_pkts = + raw_hw[stat_idx].num_ipv6_pkts; + IPAHAL_DBG_LOW("num_ipv6_pkts %lld\n", + out->stats[i][j].num_ipv6_pkts); + out->stats[i][j].num_ipv6_bytes = + raw_hw[stat_idx].num_ipv6_bytes; + IPAHAL_DBG_LOW("num_ipv6_bytes %lld\n", + out->stats[i][j].num_ipv6_bytes); + stat_idx++; + } + } + } + + return 0; +} + +static struct ipahal_stats_init_pyld *ipahal_generate_init_pyld_flt_rt_v4_5( + void *params, bool is_atomic_ctx) +{ + struct ipahal_stats_init_pyld *pyld; + long num = (long)(params); /* params is treated as a pointer. */ + + if (num > IPA_MAX_FLT_RT_CNT_INDEX || + num <= 0) { + IPAHAL_ERR("num %d not valid\n", num); + return NULL; + } + pyld = IPAHAL_MEM_ALLOC(sizeof(*pyld) + + num * + sizeof(struct ipahal_stats_flt_rt_v4_5_hw), + is_atomic_ctx); + if (!pyld) + return NULL; + pyld->len = num * + sizeof(struct ipahal_stats_flt_rt_v4_5_hw); + return pyld; +} + +static int ipahal_get_offset_flt_rt_v4_5(void *params, + struct ipahal_stats_offset *out) +{ + struct ipahal_stats_get_offset_flt_rt_v4_5 *in = + (struct ipahal_stats_get_offset_flt_rt_v4_5 *)params; + int num; + + out->offset = (in->start_id - 1) * + sizeof(struct ipahal_stats_flt_rt_v4_5); + num = in->end_id - in->start_id + 1; + out->size = num * sizeof(struct ipahal_stats_flt_rt_v4_5); + + return 0; +} + +static int ipahal_parse_stats_flt_rt_v4_5(void *init_params, + void *raw_stats, void *parsed_stats) +{ + struct ipahal_stats_flt_rt_v4_5_hw *raw_hw = + (struct ipahal_stats_flt_rt_v4_5_hw *)raw_stats; + struct ipa_ioc_flt_rt_query *query = + (struct ipa_ioc_flt_rt_query *)parsed_stats; + int num, i; + + num = query->end_id - query->start_id + 1; + IPAHAL_DBG_LOW("\n"); + for (i = 0; i < num; i++) { + ((struct ipa_flt_rt_stats *) + query->stats)[i].num_bytes = + raw_hw[i].num_bytes; + ((struct ipa_flt_rt_stats *) + query->stats)[i].num_pkts_hash = + raw_hw[i].num_packets_hash; + ((struct ipa_flt_rt_stats *) + query->stats)[i].num_pkts = + raw_hw[i].num_packets; + } + + return 0; +} + + +static struct ipahal_stats_init_pyld *ipahal_generate_init_pyld_flt_rt( + void *params, bool is_atomic_ctx) +{ + struct ipahal_stats_init_pyld *pyld; + struct ipahal_stats_init_flt_rt *in = + (struct ipahal_stats_init_flt_rt *)params; + int hdr_entries; + int num_rules = 0; + int i, start_entry; + void *pyld_ptr; + u32 incremental_offset; + + for (i = 0; i < IPAHAL_MAX_RULE_ID_32; i++) + num_rules += _count_ones(in->rule_id_bitmask[i]); + + if (num_rules == 0) { + IPAHAL_ERR("no rule ids provided\n"); + return NULL; + } + IPAHAL_DBG_LOW("num_rules = %d\n", num_rules); + + hdr_entries = IPAHAL_MAX_RULE_ID_32; + for (i = 0; i < IPAHAL_MAX_RULE_ID_32; i++) { + if (in->rule_id_bitmask[i] != 0) + break; + hdr_entries--; + } + start_entry = i; + + for (i = IPAHAL_MAX_RULE_ID_32 - 1; i >= start_entry; i--) { + if (in->rule_id_bitmask[i] != 0) + break; + hdr_entries--; + } + IPAHAL_DBG_LOW("hdr_entries = %d\n", hdr_entries); + + pyld = IPAHAL_MEM_ALLOC(sizeof(*pyld) + + hdr_entries * sizeof(struct ipahal_stats_flt_rt_hdr_hw) + + num_rules * sizeof(struct ipahal_stats_flt_rt_hw), + is_atomic_ctx); + if (!pyld) { + IPAHAL_ERR("no mem\n"); + return NULL; + } + + pyld->len = hdr_entries * sizeof(struct ipahal_stats_flt_rt_hdr_hw) + + num_rules * sizeof(struct ipahal_stats_flt_rt_hw); + + pyld_ptr = pyld->data; + incremental_offset = + (hdr_entries * sizeof(struct ipahal_stats_flt_rt_hdr_hw)) + / 8; + for (i = start_entry; i < hdr_entries; i++) { + struct ipahal_stats_flt_rt_hdr_hw *hdr = pyld_ptr; + + hdr->en_mask = in->rule_id_bitmask[i]; + hdr->cnt_offset = incremental_offset; + /* add the stats entry */ + incremental_offset += _count_ones(in->rule_id_bitmask[i]) * + sizeof(struct ipahal_stats_flt_rt_hw) / 8; + pyld_ptr += sizeof(*hdr); + } + + return pyld; +} + +static int ipahal_get_offset_flt_rt(void *params, + struct ipahal_stats_offset *out) +{ + struct ipahal_stats_get_offset_flt_rt *in = + (struct ipahal_stats_get_offset_flt_rt *)params; + int i; + int hdr_entries; + int skip_rules = 0; + int start_entry; + int rule_bit = in->rule_id % 32; + int rule_idx = in->rule_id / 32; + + if (rule_idx >= IPAHAL_MAX_RULE_ID_32) { + IPAHAL_ERR("invalid rule_id %d\n", in->rule_id); + return -EPERM; + } + + hdr_entries = IPAHAL_MAX_RULE_ID_32; + for (i = 0; i < IPAHAL_MAX_RULE_ID_32; i++) { + if (in->init.rule_id_bitmask[i] != 0) + break; + hdr_entries--; + } + + if (hdr_entries == 0) { + IPAHAL_ERR("no rule ids provided\n"); + return -EPERM; + } + start_entry = i; + + for (i = IPAHAL_MAX_RULE_ID_32 - 1; i >= 0; i--) { + if (in->init.rule_id_bitmask[i] != 0) + break; + hdr_entries--; + } + IPAHAL_DBG_LOW("hdr_entries = %d\n", hdr_entries); + + /* skip the header */ + out->offset = hdr_entries * sizeof(struct ipahal_stats_flt_rt_hdr_hw); + + /* skip the previous rules */ + for (i = start_entry; i < rule_idx; i++) + skip_rules += _count_ones(in->init.rule_id_bitmask[i]); + + for (i = 0; i < rule_bit; i++) + if (in->init.rule_id_bitmask[rule_idx] & (1 << i)) + skip_rules++; + + out->offset += skip_rules * sizeof(struct ipahal_stats_flt_rt_hw); + out->size = sizeof(struct ipahal_stats_flt_rt_hw); + + return 0; +} + +static int ipahal_parse_stats_flt_rt(void *init_params, void *raw_stats, + void *parsed_stats) +{ + struct ipahal_stats_flt_rt_hw *raw_hw = + (struct ipahal_stats_flt_rt_hw *)raw_stats; + struct ipahal_stats_flt_rt *out = + (struct ipahal_stats_flt_rt *)parsed_stats; + + memset(out, 0, sizeof(*out)); + IPAHAL_DBG_LOW("\n"); + out->num_packets = raw_hw->num_packets; + out->num_packets_hash = raw_hw->num_packets_hash; + + return 0; +} + +static struct ipahal_stats_init_pyld *ipahal_generate_init_pyld_drop( + void *params, bool is_atomic_ctx) +{ + struct ipahal_stats_init_pyld *pyld; + struct ipahal_stats_init_drop *in = + (struct ipahal_stats_init_drop *)params; + int entries = _count_ones(in->enabled_bitmask[0]); + + IPAHAL_DBG_LOW("entries = %d\n", entries); + pyld = IPAHAL_MEM_ALLOC(sizeof(*pyld) + + entries * sizeof(struct ipahal_stats_drop_hw), is_atomic_ctx); + if (!pyld) + return NULL; + + pyld->len = entries * sizeof(struct ipahal_stats_drop_hw); + + return pyld; +} + +static struct ipahal_stats_init_pyld *ipahal_generate_init_pyld_drop_v5_0( + void *params, bool is_atomic_ctx) +{ + struct ipahal_stats_init_pyld *pyld; + struct ipahal_stats_init_drop *in = + (struct ipahal_stats_init_drop *)params; + int entries = 0; + int i; + + for (i = 0; i < IPAHAL_IPA5_PIPE_REG_NUM; i++) + entries += _count_ones(in->enabled_bitmask[i]); + IPAHAL_DBG_LOW("entries = %d\n", entries); + pyld = IPAHAL_MEM_ALLOC(sizeof(*pyld) + + entries * sizeof(struct ipahal_stats_drop_hw), is_atomic_ctx); + if (!pyld) + return NULL; + + pyld->len = entries * sizeof(struct ipahal_stats_drop_hw); + + return pyld; +} + +static int ipahal_get_offset_drop(void *params, + struct ipahal_stats_offset *out) +{ + struct ipahal_stats_get_offset_drop *in = + (struct ipahal_stats_get_offset_drop *)params; + int entries = _count_ones(in->init.enabled_bitmask[0]); + + IPAHAL_DBG_LOW("\n"); + out->offset = 0; + out->size = entries * sizeof(struct ipahal_stats_drop_hw); + + return 0; +} + +static int ipahal_get_offset_drop_v5_0(void *params, + struct ipahal_stats_offset *out) +{ + struct ipahal_stats_get_offset_drop *in = + (struct ipahal_stats_get_offset_drop *)params; + int entries = 0; + int i; + + for (i = 0; i < IPAHAL_IPA5_PIPE_REG_NUM; i++) + entries += _count_ones(in->init.enabled_bitmask[i]); + IPAHAL_DBG_LOW("entries %d\n", entries); + + out->offset = 0; + out->size = entries * sizeof(struct ipahal_stats_drop_hw); + + return 0; +} + +static int ipahal_parse_stats_drop(void *init_params, void *raw_stats, + void *parsed_stats) +{ + struct ipahal_stats_init_drop *init = + (struct ipahal_stats_init_drop *)init_params; + struct ipahal_stats_drop_hw *raw_hw = + (struct ipahal_stats_drop_hw *)raw_stats; + struct ipahal_stats_drop_all *out = + (struct ipahal_stats_drop_all *)parsed_stats; + int stat_idx = 0; + int i; + + memset(out, 0, sizeof(*out)); + IPAHAL_DBG_LOW("\n"); + for (i = 0; i < IPAHAL_MAX_PIPES; i++) { + if (init->enabled_bitmask[0] & (1 << i)) { + out->stats[i].drop_byte_cnt = + raw_hw[stat_idx].drop_byte_cnt; + out->stats[i].drop_packet_cnt = + raw_hw[stat_idx].drop_packet_cnt; + stat_idx++; + } + } + + return 0; +} + +static int ipahal_parse_stats_drop_v5_0(void *init_params, void *raw_stats, + void *parsed_stats) +{ + struct ipahal_stats_init_drop *init = + (struct ipahal_stats_init_drop *)init_params; + struct ipahal_stats_drop_hw *raw_hw = + (struct ipahal_stats_drop_hw *)raw_stats; + struct ipahal_stats_drop_all *out = + (struct ipahal_stats_drop_all *)parsed_stats; + int stat_idx = 0; + int i, reg_idx; + + memset(out, 0, sizeof(*out)); + IPAHAL_DBG_LOW("\n"); + for (i = 0; i < IPAHAL_IPA5_PIPES_NUM; i++) { + reg_idx = ipahal_get_ep_reg_idx(i); + if (init->enabled_bitmask[reg_idx] & ipahal_get_ep_bit(i)) { + out->stats[i].drop_byte_cnt = + raw_hw[stat_idx].drop_byte_cnt; + out->stats[i].drop_packet_cnt = + raw_hw[stat_idx].drop_packet_cnt; + stat_idx++; + } + } + + return 0; +} + +static struct ipahal_hw_stats_obj + ipahal_hw_stats_objs[IPA_HW_MAX][IPAHAL_HW_STATS_MAX] = { + /* IPAv4 */ + [IPA_HW_v4_0][IPAHAL_HW_STATS_QUOTA] = { + ipahal_generate_init_pyld_quota, + ipahal_get_offset_quota, + ipahal_parse_stats_quota + }, + [IPA_HW_v4_0][IPAHAL_HW_STATS_TETHERING] = { + ipahal_generate_init_pyld_tethering, + ipahal_get_offset_tethering, + ipahal_parse_stats_tethering + }, + [IPA_HW_v4_0][IPAHAL_HW_STATS_FNR] = { + ipahal_generate_init_pyld_flt_rt, + ipahal_get_offset_flt_rt, + ipahal_parse_stats_flt_rt + }, + [IPA_HW_v4_0][IPAHAL_HW_STATS_DROP] = { + ipahal_generate_init_pyld_drop, + ipahal_get_offset_drop, + ipahal_parse_stats_drop + }, + + /* IPAv4_5 */ + [IPA_HW_v4_5][IPAHAL_HW_STATS_QUOTA] = { + ipahal_generate_init_pyld_quota, + ipahal_get_offset_quota, + ipahal_parse_stats_quota + }, + [IPA_HW_v4_5][IPAHAL_HW_STATS_FNR] = { + ipahal_generate_init_pyld_flt_rt_v4_5, + ipahal_get_offset_flt_rt_v4_5, + ipahal_parse_stats_flt_rt_v4_5 + }, + [IPA_HW_v4_5][IPAHAL_HW_STATS_TETHERING] = { + ipahal_generate_init_pyld_tethering, + ipahal_get_offset_tethering, + ipahal_parse_stats_tethering + }, + [IPA_HW_v4_5][IPAHAL_HW_STATS_DROP] = { + ipahal_generate_init_pyld_drop, + ipahal_get_offset_drop, + ipahal_parse_stats_drop + }, + + /* IPAv5_0 */ + [IPA_HW_v5_0][IPAHAL_HW_STATS_TETHERING] = { + ipahal_generate_init_pyld_tethering_v5_0, + ipahal_get_offset_tethering_v5_0, + ipahal_parse_stats_tethering_v5_0 + }, + [IPA_HW_v5_0][IPAHAL_HW_STATS_QUOTA] = { + ipahal_generate_init_pyld_quota_v5_0, + ipahal_get_offset_quota_v5_0, + ipahal_parse_stats_quota_v5_0 + }, + [IPA_HW_v5_0][IPAHAL_HW_STATS_DROP] = { + ipahal_generate_init_pyld_drop_v5_0, + ipahal_get_offset_drop_v5_0, + ipahal_parse_stats_drop_v5_0 + }, + + /* IPAv5_2 */ + [IPA_HW_v5_2][IPAHAL_HW_STATS_TETHERING] = { + ipahal_generate_init_pyld_tethering_v5_2, + ipahal_get_offset_tethering_v5_0, + ipahal_parse_stats_tethering_v5_0 + }, + + /* IPAv5_5 */ + [IPA_HW_v5_5][IPAHAL_HW_STATS_TETHERING] = { + ipahal_generate_init_pyld_tethering_v5_0, + ipahal_get_offset_tethering_v5_0, + ipahal_parse_stats_tethering_v5_0 + }, +}; + +int ipahal_hw_stats_init(enum ipa_hw_type ipa_hw_type) +{ + int i; + int j; + struct ipahal_hw_stats_obj zero_obj; + struct ipahal_hw_stats_obj *hw_stat_ptr; + + IPAHAL_DBG_LOW("Entry - HW_TYPE=%d\n", ipa_hw_type); + + if ((ipa_hw_type < 0) || (ipa_hw_type >= IPA_HW_MAX)) { + IPAHAL_ERR("invalid IPA HW type (%d)\n", ipa_hw_type); + return -EINVAL; + } + + memset(&zero_obj, 0, sizeof(zero_obj)); + for (i = IPA_HW_v4_0 ; i < ipa_hw_type ; i++) { + for (j = 0; j < IPAHAL_HW_STATS_MAX; j++) { + if (!memcmp(&ipahal_hw_stats_objs[i + 1][j], &zero_obj, + sizeof(struct ipahal_hw_stats_obj))) { + memcpy(&ipahal_hw_stats_objs[i + 1][j], + &ipahal_hw_stats_objs[i][j], + sizeof(struct ipahal_hw_stats_obj)); + } else { + /* + * explicitly overridden stat. + * Check validity + */ + hw_stat_ptr = &ipahal_hw_stats_objs[i + 1][j]; + if (!hw_stat_ptr->get_offset) { + IPAHAL_ERR( + "stat=%d get_offset null ver=%d\n", + j, i+1); + WARN_ON(1); + } + if (!hw_stat_ptr->parse_stats) { + IPAHAL_ERR( + "stat=%d parse_stats null ver=%d\n", + j, i + 1); + WARN_ON(1); + } + } + } + } + + return 0; +} + +int ipahal_stats_get_offset(enum ipahal_hw_stats_type type, void *params, + struct ipahal_stats_offset *out) +{ + if (type < 0 || type >= IPAHAL_HW_STATS_MAX) { + IPAHAL_ERR("Invalid type stat=%d\n", type); + WARN_ON(1); + return -EFAULT; + } + + if (!params || !out) { + IPAHAL_ERR("Null arg\n"); + WARN_ON(1); + return -EFAULT; + } + + return ipahal_hw_stats_objs[ipahal_ctx->hw_type][type].get_offset( + params, out); +} + +struct ipahal_stats_init_pyld *ipahal_stats_generate_init_pyld( + enum ipahal_hw_stats_type type, void *params, bool is_atomic_ctx) +{ + struct ipahal_hw_stats_obj *hw_obj_ptr; + + if (type < 0 || type >= IPAHAL_HW_STATS_MAX) { + IPAHAL_ERR("Invalid type stat=%d\n", type); + WARN_ON(1); + return NULL; + } + + hw_obj_ptr = &ipahal_hw_stats_objs[ipahal_ctx->hw_type][type]; + return hw_obj_ptr->generate_init_pyld(params, is_atomic_ctx); +} + +int ipahal_parse_stats(enum ipahal_hw_stats_type type, void *init_params, + void *raw_stats, void *parsed_stats) +{ + if (WARN((type < 0 || type >= IPAHAL_HW_STATS_MAX), + "Invalid type stat = %d\n", type)) + return -EFAULT; + + if (WARN((!raw_stats || !parsed_stats), "Null arg\n")) + return -EFAULT; + + return ipahal_hw_stats_objs[ipahal_ctx->hw_type][type].parse_stats( + init_params, raw_stats, parsed_stats); +} + +void ipahal_set_flt_rt_sw_stats(void *raw_stats, + struct ipa_flt_rt_stats sw_stats) +{ + struct ipahal_stats_flt_rt_v4_5_hw *raw_hw = + (struct ipahal_stats_flt_rt_v4_5_hw *)raw_stats; + + IPAHAL_DBG_LOW("\n"); + raw_hw->num_bytes = sw_stats.num_bytes; + raw_hw->num_packets_hash = sw_stats.num_pkts_hash; + raw_hw->num_packets = sw_stats.num_pkts; +} diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_hw_stats.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_hw_stats.h new file mode 100644 index 0000000000..b7aff3b193 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_hw_stats.h @@ -0,0 +1,279 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _IPAHAL_HW_STATS_H_ +#define _IPAHAL_HW_STATS_H_ + +#include "ipa.h" + +#define IPAHAL_MAX_PIPES 32 +#define IPAHAL_MAX_PIPES_PER_REG 32 +#define IPAHAL_IPA5_PIPES_NUM 36 +#define IPAHAL_IPA5_PIPE_REG_NUM 2 +#define IPAHAL_IPA5_PRODUCER_PIPE_NUM 16 +#define IPAHAL_IPA5_2_PRODUCER_PIPE_NUM 11 +#define IPAHAL_MAX_RULE_ID_32 (1024 / 32) /* 10 bits of rule id */ + +enum ipahal_hw_stats_type { + IPAHAL_HW_STATS_QUOTA, + IPAHAL_HW_STATS_TETHERING, + IPAHAL_HW_STATS_FNR, + IPAHAL_HW_STATS_DROP, + IPAHAL_HW_STATS_MAX +}; + +/* + * struct ipahal_stats_init_pyld - Statistics initialization payload + * @len: length of payload + * @data: actual payload data + */ +struct ipahal_stats_init_pyld { + u16 len; + u16 reserved; + u8 data[0]; +}; + +/* + * struct ipahal_stats_offset - Statistics offset parameters + * @offset: offset of the statistic from beginning of stats table + * @size: size of the statistics + */ +struct ipahal_stats_offset { + u32 offset; + u16 size; +}; + +/* + * struct ipahal_stats_init_quota - Initializations parameters for quota + * @enabled_bitmask: bit mask of pipes to be monitored + */ +struct ipahal_stats_init_quota { + u32 enabled_bitmask[IPAHAL_IPA5_PIPE_REG_NUM]; +}; + +/* + * struct ipahal_stats_get_offset_quota - Get offset parameters for quota + * @init: initialization parameters used in initialization of stats + */ +struct ipahal_stats_get_offset_quota { + struct ipahal_stats_init_quota init; +}; + +/* + * struct ipahal_stats_quota - Quota statistics + * @num_ipv4_bytes: IPv4 bytes + * @num_ipv6_bytes: IPv6 bytes + * @num_ipv4_pkts: IPv4 packets + * @num_ipv6_pkts: IPv6 packets + */ +struct ipahal_stats_quota { + u64 num_ipv4_bytes; + u64 num_ipv6_bytes; + u64 num_ipv4_pkts; + u64 num_ipv6_pkts; +}; + +/* + * struct ipahal_stats_quota_all - Quota statistics for all pipes + * @stats: array of statistics per pipe + */ +struct ipahal_stats_quota_all { + struct ipahal_stats_quota stats[IPAHAL_IPA5_PIPES_NUM]; +}; + +/* + * struct ipahal_stats_init_tethering - Initializations parameters for tethering + * @prod_bitmask: bit mask of producer pipes to be monitored + * @cons_bitmask: bit mask of consumer pipes to be monitored per producer + */ +struct ipahal_stats_init_tethering { + u32 prod_bitmask[IPAHAL_IPA5_PIPE_REG_NUM]; + u32 cons_bitmask[IPAHAL_IPA5_PIPES_NUM][IPAHAL_IPA5_PIPE_REG_NUM]; +}; + +/* + * struct ipahal_stats_get_offset_tethering - Get offset parameters for + * tethering + * @init: initialization parameters used in initialization of stats + */ +struct ipahal_stats_get_offset_tethering { + struct ipahal_stats_init_tethering init; +}; + +/* + * struct ipahal_stats_tethering - Tethering statistics + * @num_ipv4_bytes: IPv4 bytes + * @num_ipv6_bytes: IPv6 bytes + * @num_ipv4_pkts: IPv4 packets + * @num_ipv6_pkts: IPv6 packets + */ +struct ipahal_stats_tethering { + u64 num_ipv4_bytes; + u64 num_ipv6_bytes; + u64 num_ipv4_pkts; + u64 num_ipv6_pkts; +}; + +/* + * struct ipahal_stats_tethering_all - Tethering statistics for all pipes + * @stats: matrix of statistics per pair of pipes + */ +struct ipahal_stats_tethering_all { + struct ipahal_stats_tethering + stats[IPAHAL_IPA5_PIPES_NUM][IPAHAL_IPA5_PIPES_NUM]; +}; + +/* + * struct ipahal_stats_init_flt_rt - Initializations parameters for flt_rt + * @rule_id_bitmask: array describes which rule ids to monitor. + * rule_id bit is determined by: + * index to the array => rule_id / 32 + * bit to enable => rule_id % 32 + */ +struct ipahal_stats_init_flt_rt { + u32 rule_id_bitmask[IPAHAL_MAX_RULE_ID_32]; +}; + +/* + * struct ipahal_stats_get_offset_flt_rt - Get offset parameters for flt_rt + * @init: initialization parameters used in initialization of stats + * @rule_id: rule_id to get the offset for + */ +struct ipahal_stats_get_offset_flt_rt { + struct ipahal_stats_init_flt_rt init; + u32 rule_id; +}; + +/* + * struct ipahal_stats_flt_rt - flt_rt statistics + * @num_packets: Total number of packets hit this rule + * @num_packets_hash: Total number of packets hit this rule in hash table + */ +struct ipahal_stats_flt_rt { + u32 num_packets; + u32 num_packets_hash; +}; + +/* + * struct ipahal_stats_flt_rt_v4_5 - flt_rt statistics + * @num_packets: Total number of packets hit this rule + * @num_packets_hash: Total number of packets hit this rule in hash table + * @num_bytes: Total number of bytes hit this rule + */ +struct ipahal_stats_flt_rt_v4_5 { + u32 num_packets; + u32 num_packets_hash; + u64 num_bytes; +}; + +/* + * struct ipahal_stats_get_offset_flt_rt_v4_5 - Get offset parameters for flt_rt + * @start_id: start_id to get the offset + * @end_id: end_id to get the offset + */ +struct ipahal_stats_get_offset_flt_rt_v4_5 { + u8 start_id; + u8 end_id; +}; + +/* + * struct ipahal_stats_init_drop - Initializations parameters for Drop + * @enabled_bitmask: bit mask of pipes to be monitored + */ +struct ipahal_stats_init_drop { + u32 enabled_bitmask[IPAHAL_IPA5_PIPE_REG_NUM]; +}; + +/* + * struct ipahal_stats_get_offset_drop - Get offset parameters for Drop + * @init: initialization parameters used in initialization of stats + */ +struct ipahal_stats_get_offset_drop { + struct ipahal_stats_init_drop init; +}; + +/* + * struct ipahal_stats_drop - Packet Drop statistics + * @drop_packet_cnt: number of packets dropped + * @drop_byte_cnt: number of bytes dropped + */ +struct ipahal_stats_drop { + u32 drop_packet_cnt; + u32 drop_byte_cnt; +}; + +/* + * struct ipahal_stats_drop_all - Drop statistics for all pipes + * @stats: array of statistics per pipes + */ +struct ipahal_stats_drop_all { + struct ipahal_stats_drop stats[IPAHAL_IPA5_PIPES_NUM]; +}; + +/* + * ipahal_stats_generate_init_pyld - Generate the init payload for stats + * @type: type of stats + * @params: init_pyld parameters based of stats type + * @is_atomic_ctx: is calling context atomic ? + * + * This function will generate the initialization payload for a particular + * statistic in hardware. IPA driver is expected to use this payload to + * initialize the SRAM. + * + * Return: pointer to ipahal_stats_init_pyld on success or NULL on failure. + */ +struct ipahal_stats_init_pyld *ipahal_stats_generate_init_pyld( + enum ipahal_hw_stats_type type, void *params, bool is_atomic_ctx); + +/* + * ipahal_destroy_stats_init_pyld() - Destroy/Release bulk that was built + * by the ipahal_stats_generate_init_pyld function. + */ +static inline void ipahal_destroy_stats_init_pyld( + struct ipahal_stats_init_pyld *pyld) +{ + kfree(pyld); +} + +/* + * ipahal_stats_get_offset - Get the offset / size of payload for stats + * @type: type of stats + * @params: get_offset parameters based of stats type + * @out: out parameter for the offset and size. + * + * This function will return the offset of the counter from beginning of + * the table.IPA driver is expected to read this portion in SRAM and pass + * it to ipahal_parse_stats() to interprete the stats. + * + * Return: 0 on success and negative on failure + */ +int ipahal_stats_get_offset(enum ipahal_hw_stats_type type, void *params, + struct ipahal_stats_offset *out); + +/* + * ipahal_parse_stats - parse statistics + * @type: type of stats + * @init_params: init_pyld parameters used on init + * @raw_stats: stats read from IPA SRAM + * @parsed_stats: pointer to parsed stats based on type + * + * Return: 0 on success and negative on failure + */ +int ipahal_parse_stats(enum ipahal_hw_stats_type type, void *init_params, + void *raw_stats, void *parsed_stats); + + +/* + * ipahal_set_flt_rt_sw_stats - set sw counter stats for FnR + * @raw_stats: stats write to IPA SRAM + * @sw_stats: FnR sw stats to be written + * + * Return: None + */ +void ipahal_set_flt_rt_sw_stats(void *raw_stats, + struct ipa_flt_rt_stats sw_stats); + +#endif /* _IPAHAL_HW_STATS_H_ */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_hw_stats_i.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_hw_stats_i.h new file mode 100644 index 0000000000..1eef2e5864 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_hw_stats_i.h @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. + */ + +#ifndef _IPAHAL_HW_STATS_I_H_ +#define _IPAHAL_HW_STATS_I_H_ + +#include "ipahal_hw_stats.h" + +int ipahal_hw_stats_init(enum ipa_hw_type ipa_hw_type); + +struct ipahal_stats_quota_hw { + u64 num_ipv4_bytes; + u64 num_ipv4_pkts:32; + u64 num_ipv6_pkts:32; + u64 num_ipv6_bytes; +}; + +struct ipahal_stats_tethering_hdr_hw { + u64 dst_mask:32; + u64 offset:32; +}; + +struct ipahal_stats_tethering_hdr_v5_0_hw { + u64 dst_mask_31_0:32; + u64 dst_mask_63_32:32; + u64 dst_mask_95_64:32; + u64 dst_mask_127_96:32; + u64 offset:32; + u64 reserved:32; +}; + +struct ipahal_stats_tethering_hw { + u64 num_ipv4_bytes; + u64 num_ipv4_pkts:32; + u64 num_ipv6_pkts:32; + u64 num_ipv6_bytes; +}; + +struct ipahal_stats_flt_rt_hdr_hw { + u64 en_mask:32; + u64 reserved:16; + u64 cnt_offset:16; +}; + +struct ipahal_stats_flt_rt_hw { + u64 num_packets_hash:32; + u64 num_packets:32; +}; + +struct ipahal_stats_flt_rt_v4_5_hw { + u64 num_packets_hash:32; + u64 num_packets:32; + u64 num_bytes; +}; + +struct ipahal_stats_drop_hw { + u64 drop_byte_cnt:40; + u64 drop_packet_cnt:24; +}; + +#endif /* _IPAHAL_HW_STATS_I_H_ */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_i.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_i.h new file mode 100644 index 0000000000..71c94da192 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_i.h @@ -0,0 +1,1360 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _IPAHAL_I_H_ +#define _IPAHAL_I_H_ + +#include "ipa.h" +#include "ipa_common_i.h" + +#define IPAHAL_DRV_NAME "ipahal" + +#define IPAHAL_DBG(fmt, args...) \ + do { \ + pr_debug(IPAHAL_DRV_NAME " %s:%d " fmt, __func__, __LINE__, \ + ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf(), \ + IPAHAL_DRV_NAME " %s:%d " fmt, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf_low(), \ + IPAHAL_DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) + +#define IPAHAL_DBG_LOW(fmt, args...) \ + do { \ + pr_debug(IPAHAL_DRV_NAME " %s:%d " fmt, __func__, __LINE__, \ + ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf_low(), \ + IPAHAL_DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) + +#define IPAHAL_ERR(fmt, args...) \ + do { \ + pr_err(IPAHAL_DRV_NAME " %s:%d " fmt, __func__, __LINE__, \ + ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf(), \ + IPAHAL_DRV_NAME " %s:%d " fmt, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf_low(), \ + IPAHAL_DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) + +#define IPAHAL_ERR_RL(fmt, args...) \ + do { \ + pr_err_ratelimited_ipa(IPAHAL_DRV_NAME " %s:%d " fmt, \ + __func__, __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf(), \ + IPAHAL_DRV_NAME " %s:%d " fmt, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf_low(), \ + IPAHAL_DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) + +#define IPAHAL_DBG_REG(fmt, args...) \ + do { \ + pr_err(fmt, ## args); \ + IPA_IPC_LOGGING(ipahal_ctx->regdumpbuf, \ + " %s:%d " fmt, ## args); \ + } while (0) + +#define IPAHAL_DBG_REG_IPC_ONLY(fmt, args...) \ + IPA_IPC_LOGGING(ipahal_ctx->regdumpbuf, " %s:%d " fmt, ## args) + +#define IPAHAL_MEM_ALLOC(__size, __is_atomic_ctx) \ + (kzalloc((__size), ((__is_atomic_ctx) ? GFP_ATOMIC : GFP_KERNEL))) + +#define IPAHAL_IPC_LOG_PAGES 50 + +#define IPAHAL_PKT_STATUS_FLTRT_RULE_MISS_ID 0x3ff + +/* + * struct ipahal_context - HAL global context data + * @hw_type: IPA H/W type/version. + * @base: Base address to be used for accessing IPA memory. This is + * I/O memory mapped address. + * Controlled by debugfs. default is off + * @dent: Debugfs folder dir entry + * @ipa_pdev: IPA Platform Device. Will be used for DMA memory + * @empty_fltrt_tbl: Empty table to be used at tables init. + */ +struct ipahal_context { + enum ipa_hw_type hw_type; + void __iomem *base; + u32 ipa_cfg_offset; + struct dentry *dent; + struct device *ipa_pdev; + struct ipa_mem_buffer empty_fltrt_tbl; + void *regdumpbuf; +}; + +extern struct ipahal_context *ipahal_ctx; + + + +/* Immediate commands H/W structures */ + +/* + * struct ipa_imm_cmd_hw_ip_v4_filter_init - IP_V4_FILTER_INIT command payload + * in H/W format. + * Inits IPv4 filter block. + * @hash_rules_addr: Addr in system mem where ipv4 hashable flt rules starts + * @hash_rules_size: Size in bytes of the hashable tbl to cpy to local mem + * @hash_local_addr: Addr in shared mem where ipv4 hashable flt tbl should + * be copied to + * @nhash_rules_size: Size in bytes of the non-hashable tbl to cpy to local mem + * @nhash_local_addr: Addr in shared mem where ipv4 non-hashable flt tbl should + * be copied to + * @rsvd: reserved + * @nhash_rules_addr: Addr in sys mem where ipv4 non-hashable flt tbl starts + */ +struct ipa_imm_cmd_hw_ip_v4_filter_init { + u64 hash_rules_addr:64; + u64 hash_rules_size:12; + u64 hash_local_addr:16; + u64 nhash_rules_size:12; + u64 nhash_local_addr:16; + u64 rsvd:8; + u64 nhash_rules_addr:64; +}; + +/* + * struct ipa_imm_cmd_hw_ip_v6_filter_init - IP_V6_FILTER_INIT command payload + * in H/W format. + * Inits IPv6 filter block. + * @hash_rules_addr: Addr in system mem where ipv6 hashable flt rules starts + * @hash_rules_size: Size in bytes of the hashable tbl to cpy to local mem + * @hash_local_addr: Addr in shared mem where ipv6 hashable flt tbl should + * be copied to + * @nhash_rules_size: Size in bytes of the non-hashable tbl to cpy to local mem + * @nhash_local_addr: Addr in shared mem where ipv6 non-hashable flt tbl should + * be copied to + * @rsvd: reserved + * @nhash_rules_addr: Addr in sys mem where ipv6 non-hashable flt tbl starts + */ +struct ipa_imm_cmd_hw_ip_v6_filter_init { + u64 hash_rules_addr:64; + u64 hash_rules_size:12; + u64 hash_local_addr:16; + u64 nhash_rules_size:12; + u64 nhash_local_addr:16; + u64 rsvd:8; + u64 nhash_rules_addr:64; +}; + +/* + * struct ipa_imm_cmd_hw_ip_v4_nat_init - IP_V4_NAT_INIT command payload + * in H/W format. + * Inits IPv4 NAT block. Initiate NAT table with it dimensions, location + * cache address and other related parameters. + * @ipv4_rules_addr: Addr in sys/shared mem where ipv4 NAT rules start + * @ipv4_expansion_rules_addr: Addr in sys/shared mem where expansion NAT + * table starts. IPv4 NAT rules that result in hash collision are located + * in this table. + * @index_table_addr: Addr in sys/shared mem where index table, which points + * to NAT table starts + * @index_table_expansion_addr: Addr in sys/shared mem where expansion index + * table starts + * @table_index: For future support of multiple NAT tables + * @rsvd1: reserved + * @ipv4_rules_addr_type: ipv4_rules_addr in sys or shared mem + * @ipv4_expansion_rules_addr_type: ipv4_expansion_rules_addr in + * sys or shared mem + * @index_table_addr_type: index_table_addr in sys or shared mem + * @index_table_expansion_addr_type: index_table_expansion_addr in + * sys or shared mem + * @size_base_tables: Num of entries in NAT tbl and idx tbl (each) + * @size_expansion_tables: Num of entries in NAT expansion tbl and expansion + * idx tbl (each) + * @rsvd2: reserved + * @public_addr_info: Public IP addresses info suitable to the IPA H/W version + * IPA H/W >= 4.0 - PDN config table offset in SMEM + * IPA H/W < 4.0 - The public IP address + */ +struct ipa_imm_cmd_hw_ip_v4_nat_init { + u64 ipv4_rules_addr:64; + u64 ipv4_expansion_rules_addr:64; + u64 index_table_addr:64; + u64 index_table_expansion_addr:64; + u64 table_index:3; + u64 rsvd1:1; + u64 ipv4_rules_addr_type:1; + u64 ipv4_expansion_rules_addr_type:1; + u64 index_table_addr_type:1; + u64 index_table_expansion_addr_type:1; + u64 size_base_tables:12; + u64 size_expansion_tables:10; + u64 rsvd2:2; + u64 public_addr_info:32; +}; + +/* + * struct ipa_imm_cmd_hw_ip_v6_ct_init - IP_V6_CONN_TRACK_INIT command payload + * in H/W format. + * Inits IPv6CT block. Initiate IPv6CT table with it dimensions, location + * cache address and other related parameters. + * @table_addr: Address in sys/shared mem where IPv6CT rules start + * @expansion_table_addr: Address in sys/shared mem where IPv6CT expansion + * table starts. IPv6CT rules that result in hash collision are located + * in this table. + * @table_index: For future support of multiple IPv6CT tables + * @rsvd1: reserved + * @table_addr_type: table_addr in sys or shared mem + * @expansion_table_addr_type: expansion_table_addr in sys or shared mem + * @rsvd2: reserved + * @size_base_tables: Number of entries in IPv6CT table + * @size_expansion_tables: Number of entries in IPv6CT expansion table + * @rsvd3: reserved + */ +struct ipa_imm_cmd_hw_ip_v6_ct_init { + u64 table_addr:64; + u64 expansion_table_addr:64; + u64 table_index:3; + u64 rsvd1:1; + u64 table_addr_type:1; + u64 expansion_table_addr_type:1; + u64 rsvd2:2; + u64 size_base_table:12; + u64 size_expansion_table:10; + u64 rsvd3:34; +}; + +/* + * struct ipa_imm_cmd_hw_ip_v4_routing_init - IP_V4_ROUTING_INIT command payload + * in H/W format. + * Inits IPv4 routing table/structure - with the rules and other related params + * @hash_rules_addr: Addr in system mem where ipv4 hashable rt rules starts + * @hash_rules_size: Size in bytes of the hashable tbl to cpy to local mem + * @hash_local_addr: Addr in shared mem where ipv4 hashable rt tbl should + * be copied to + * @nhash_rules_size: Size in bytes of the non-hashable tbl to cpy to local mem + * @nhash_local_addr: Addr in shared mem where ipv4 non-hashable rt tbl should + * be copied to + * @rsvd: reserved + * @nhash_rules_addr: Addr in sys mem where ipv4 non-hashable rt tbl starts + */ +struct ipa_imm_cmd_hw_ip_v4_routing_init { + u64 hash_rules_addr:64; + u64 hash_rules_size:12; + u64 hash_local_addr:16; + u64 nhash_rules_size:12; + u64 nhash_local_addr:16; + u64 rsvd:8; + u64 nhash_rules_addr:64; +}; + +/* + * struct ipa_imm_cmd_hw_ip_v6_routing_init - IP_V6_ROUTING_INIT command payload + * in H/W format. + * Inits IPv6 routing table/structure - with the rules and other related params + * @hash_rules_addr: Addr in system mem where ipv6 hashable rt rules starts + * @hash_rules_size: Size in bytes of the hashable tbl to cpy to local mem + * @hash_local_addr: Addr in shared mem where ipv6 hashable rt tbl should + * be copied to + * @nhash_rules_size: Size in bytes of the non-hashable tbl to cpy to local mem + * @nhash_local_addr: Addr in shared mem where ipv6 non-hashable rt tbl should + * be copied to + * @rsvd: reserved + * @nhash_rules_addr: Addr in sys mem where ipv6 non-hashable rt tbl starts + */ +struct ipa_imm_cmd_hw_ip_v6_routing_init { + u64 hash_rules_addr:64; + u64 hash_rules_size:12; + u64 hash_local_addr:16; + u64 nhash_rules_size:12; + u64 nhash_local_addr:16; + u64 rsvd:8; + u64 nhash_rules_addr:64; +}; + +/* + * struct ipa_imm_cmd_hw_hdr_init_local - HDR_INIT_LOCAL command payload + * in H/W format. + * Inits hdr table within local mem with the hdrs and their length. + * @hdr_table_addr: Word address in sys mem where the table starts (SRC) + * @size_hdr_table: Size of the above (in bytes) + * @hdr_addr: header address in IPA sram (used as DST for memory copy) + * @rsvd: reserved + */ +struct ipa_imm_cmd_hw_hdr_init_local { + u64 hdr_table_addr:64; + u64 size_hdr_table:12; + u64 hdr_addr:16; + u64 rsvd:4; +}; + +/* + * struct ipa_imm_cmd_hw_nat_dma - NAT_DMA command payload + * in H/W format + * Perform DMA operation on NAT related mem addressess. Copy data into + * different locations within NAT associated tbls. (For add/remove NAT rules) + * @table_index: NAT tbl index. Defines the NAT tbl on which to perform DMA op. + * @rsvd1: reserved + * @base_addr: Base addr to which the DMA operation should be performed. + * @rsvd2: reserved + * @offset: offset in bytes from base addr to write 'data' to + * @data: data to be written + * @rsvd3: reserved + */ +struct ipa_imm_cmd_hw_nat_dma { + u64 table_index:3; + u64 rsvd1:1; + u64 base_addr:2; + u64 rsvd2:2; + u64 offset:32; + u64 data:16; + u64 rsvd3:8; +}; + +/* + * struct ipa_imm_cmd_hw_table_dma_ipav4 - TABLE_DMA command payload + * in H/W format + * Perform DMA operation on NAT and ipv6 connection tracking related mem + * addresses. Copy data into different locations within NAT associated tbls + * (For add/remove NAT rules) + * @table_index: NAT tbl index. Defines the NAT tbl on which to perform DMA op. + * @rsvd1: reserved + * @base_addr: Base addr to which the DMA operation should be performed. + * @rsvd2: reserved + * @offset: offset in bytes from base addr to write 'data' to + * @data: data to be written + * @rsvd3: reserved + */ +struct ipa_imm_cmd_hw_table_dma_ipav4 { + u64 table_index : 3; + u64 rsvd1 : 1; + u64 base_addr : 3; + u64 rsvd2 : 1; + u64 offset : 32; + u64 data : 16; + u64 rsvd3 : 8; +}; + +/* + * struct ipa_imm_cmd_hw_hdr_init_system - HDR_INIT_SYSTEM command payload + * in H/W format. + * Inits hdr table within sys mem with the hdrs and their length. + * @hdr_table_addr: Word address in system memory where the hdrs tbl starts. + */ +struct ipa_imm_cmd_hw_hdr_init_system { + u64 hdr_table_addr:64; +}; + +/* + * struct ipa_imm_cmd_hw_ip_packet_init - IP_PACKET_INIT command payload + * in H/W format. + * Configuration for specific IP pkt. Shall be called prior to an IP pkt + * data. Pkt will not go through IP pkt processing. + * @destination_pipe_index: Destination pipe index (in case routing + * is enabled, this field will overwrite the rt rule) + * @rsvd: reserved + */ +struct ipa_imm_cmd_hw_ip_packet_init { + u64 destination_pipe_index:5; + u64 rsv1:59; +}; + + +/* + * struct ipa_imm_cmd_hw_ip_packet_init_v_5_0 - IP_PACKET_INIT command payload + * in H/W format for IPA v5_0. + * Configuration for specific IP pkt. Shall be called prior to an IP pkt + * data. Pkt will not go through IP pkt processing. + * @destination_pipe_index: Destination pipe index (in case routing + * is enabled, this field will overwrite the rt rule) + * @rsvd: reserved + */ +struct ipa_imm_cmd_hw_ip_packet_init_v_5_0 { + u64 destination_pipe_index : 8; + u64 rsv1 : 56; +}; + +/* + * struct ipa_imm_cmd_hw_ip_packet_init_ex - IP_PACKET_INIT_EX command payload + * in H/W format for IPA v5_0. + * @frag_disable: 1 - disabled. overrides IPA_ENDP_CONFIG_n:FRAG_OFFLOAD_EN + * @filter_disable: 1 - disabled, 0 enabled + * @nat_disable: 1 - disabled, 0 enabled + * @route_disable: 1 - disabled, 0 enabled + * @hdr_removal_insertion_disable: 1 - disabled, 0 enabled + * @cs_disable: 1 - disabled, 0 enabled + * @quota_tethering_stats_disable: 1 - disabled, 0 enabled + * fields @flt_rt_tbl_idx - @rsvd4 are a copy of ipa5_0_flt_rule_hw_hdr + * fields @rt_pipe_dest_idx - @rt_system are a copy of ipa5_0_rt_rule_hw_hdr + */ +struct ipa_imm_cmd_hw_ip_packet_init_ex { + u64 rsvd1 : 16; + u64 frag_disable : 1; + u64 filter_disable : 1; + u64 nat_disable : 1; + u64 route_disable : 1; + u64 hdr_removal_insertion_disable : 1; + u64 cs_disable : 1; + u64 quota_tethering_stats_disable : 1; + u64 rsvd2 : 9; + u64 flt_rt_tbl_idx : 8; + u64 flt_stats_cnt_idx : 8; + u64 flt_priority : 8; + u64 rsvd3 : 1; + u64 flt_close_aggr_irq_mod : 1; + u64 flt_rule_id : 10; + u64 flt_action : 5; + u64 flt_pdn_idx : 4; + u64 flt_set_metadata : 1; + u64 flt_retain_hdr : 1; + u64 rsvd4 : 1; + u64 rt_pipe_dest_idx : 8; + u64 rt_stats_cnt_idx : 8; + u64 rt_priority : 8; + u64 rt_rsvd : 1; + u64 rt_close_aggr_irq_mod : 1; + u64 rt_rule_id : 10; + u64 rt_hdr_offset : 9; + u64 rt_proc_ctx : 1; + u64 rt_retain_hdr : 1; + u64 rt_system : 1; +} __packed; + +/* + * struct ipa_imm_cmd_hw_ip_packet_init_ex_v5_5 - IP_PACKET_INIT_EX command payload + * in H/W format for IPA v5_5. + * @frag_disable: 1 - disabled. overrides IPA_ENDP_CONFIG_n:FRAG_OFFLOAD_EN + * @filter_disable: 1 - disabled, 0 enabled + * @nat_disable: 1 - disabled, 0 enabled + * @route_disable: 1 - disabled, 0 enabled + * @hdr_removal_insertion_disable: 1 - disabled, 0 enabled + * @cs_disable: 1 - disabled, 0 enabled + * @quota_tethering_stats_disable: 1 - disabled, 0 enabled + * @dpl_disable: 1 - disabled, 0 enabled + * fields @flt_rt_tbl_idx - @rsvd4 are a copy of ipa5_5_flt_rule_hw_hdr + * fields @rt_pipe_dest_idx - @rsvd5 are a copy of ipa5_5_rt_rule_hw_hdr + */ +struct ipa_imm_cmd_hw_ip_packet_init_ex_v5_5 { + u64 rsvd1 : 16; + u64 frag_disable : 1; + u64 filter_disable : 1; + u64 nat_disable : 1; + u64 route_disable : 1; + u64 hdr_removal_insertion_disable : 1; + u64 cs_disable : 1; + u64 quota_tethering_stats_disable : 1; + u64 dpl_disable : 1; + u64 rsvd2 : 40; + u64 flt_rt_tbl_idx : 8; + u64 flt_stats_cnt_idx : 8; + u64 flt_priority : 8; + u64 flt_ext_hdr : 1; + u64 flt_close_aggr_irq_mod : 1; + u64 flt_rule_id : 10; + u64 flt_action : 5; + u64 flt_pdn_idx : 4; + u64 flt_set_metadata : 1; + u64 flt_retain_hdr : 1; + u64 rsvd3 : 1; + u64 flt_ttl : 1; + u64 flt_qos_class : 6; + u64 rsvd4 : 9; + u64 rt_pipe_dest_idx : 8; + u64 rt_stats_cnt_idx : 8; + u64 rt_priority : 8; + u64 rt_ext_hdr : 1; + u64 rt_close_aggr_irq_mod : 1; + u64 rt_rule_id : 10; + u64 rt_hdr_offset : 9; + u64 rt_proc_ctx : 1; + u64 rt_retain_hdr : 1; + u64 rt_system : 1; + u64 rt_ttl : 1; + u64 rt_qos_class : 6; + u64 rt_skip_ingress : 1; + u64 rsvd5 : 8; +} __packed; + +/* + * struct ipa_imm_cmd_hw_register_write - REGISTER_WRITE command payload + * in H/W format. + * Write value to register. Allows reg changes to be synced with data packet + * and other immediate command. Can be used to access the sram + * @sw_rsvd: Ignored by H/W. May be used by S/W + * @skip_pipeline_clear: 0 to wait until IPA pipeline is clear. 1 don't wait + * @offset: offset from IPA base address - Lower 16bit of the IPA reg addr + * @value: value to write to register + * @value_mask: mask specifying which value bits to write to the register + * @pipeline_clear_options: options for pipeline to clear + * 0: HPS - no pkt inside HPS (not grp specific) + * 1: source group - The immediate cmd src grp does not use any pkt ctxs + * 2: Wait until no pkt reside inside IPA pipeline + * 3: reserved + * @rsvd: reserved - should be set to zero + */ +struct ipa_imm_cmd_hw_register_write { + u64 sw_rsvd:15; + u64 skip_pipeline_clear:1; + u64 offset:16; + u64 value:32; + u64 value_mask:32; + u64 pipeline_clear_options:2; + u64 rsvd:30; +}; + +/* + * struct ipa_imm_cmd_hw_register_write - REGISTER_WRITE command payload + * in H/W format. + * Write value to register. Allows reg changes to be synced with data packet + * and other immediate command. Can be used to access the sram + * @sw_rsvd: Ignored by H/W. May be used by S/W + * @offset_high: high bits of the Offset field - bits 17-20 + * @rsvd: reserved - should be set to zero + * @offset: offset from IPA base address - Lower 16bit of the IPA reg addr + * @value: value to write to register + * @value_mask: mask specifying which value bits to write to the register + * @rsvd2: reserved - should be set to zero + */ +struct ipa_imm_cmd_hw_register_write_v_4_0 { + u64 sw_rsvd:11; + u64 offset_high:4; + u64 rsvd:1; + u64 offset:16; + u64 value:32; + u64 value_mask:32; + u64 rsvd2:32; +}; + +/* + * struct ipa_imm_cmd_hw_register_read - REGISTER_READ command payload + * in H/W format. + * Read value from register. Allows reg changes to be synced with data packet + * and other immediate command. Can be used to access the sram + * @sw_rsvd: Ignored by H/W. May be used by S/W + * @offset_high: high bits of the Offset field - bits 17-20 + * @rsvd: reserved - should be set to zero + * @offset: offset from IPA base address - Lower 16bit of the IPA reg addr + * @sys_addr: Address in system memory for storing register value + */ +struct ipa_imm_cmd_hw_register_read { + u64 sw_rsvd:11; + u64 offset_high:4; + u64 rsvd:1; + u64 offset:16; + u64 sys_addr:32; +}; + +/* + * struct ipa_imm_cmd_hw_dma_shared_mem - DMA_SHARED_MEM command payload + * in H/W format. + * Perform mem copy into or out of the SW area of IPA local mem + * @sw_rsvd: Ignored by H/W. My be used by S/W + * @size: Size in bytes of data to copy. Expected size is up to 2K bytes + * @local_addr: Address in IPA local memory + * @direction: Read or write? + * 0: IPA write, Write to local address from system address + * 1: IPA read, Read from local address to system address + * @skip_pipeline_clear: 0 to wait until IPA pipeline is clear. 1 don't wait + * @pipeline_clear_options: options for pipeline to clear + * 0: HPS - no pkt inside HPS (not grp specific) + * 1: source group - The immediate cmd src grp does npt use any pkt ctxs + * 2: Wait until no pkt reside inside IPA pipeline + * 3: reserved + * @rsvd: reserved - should be set to zero + * @system_addr: Address in system memory + */ +struct ipa_imm_cmd_hw_dma_shared_mem { + u64 sw_rsvd:16; + u64 size:16; + u64 local_addr:16; + u64 direction:1; + u64 skip_pipeline_clear:1; + u64 pipeline_clear_options:2; + u64 rsvd:12; + u64 system_addr:64; +}; + +/* + * struct ipa_imm_cmd_hw_dma_shared_mem - DMA_SHARED_MEM command payload + * in H/W format. + * Perform mem copy into or out of the SW area of IPA local mem + * @sw_rsvd: Ignored by H/W. My be used by S/W + * @size: Size in bytes of data to copy. Expected size is up to 2K bytes + * @clear_after_read: Clear local memory at the end of a read operation allows + * atomic read and clear if HPS is clear. Ignore for writes. + * @local_addr: Address in IPA local memory + * @direction: Read or write? + * 0: IPA write, Write to local address from system address + * 1: IPA read, Read from local address to system address + * @rsvd: reserved - should be set to zero + * @system_addr: Address in system memory + */ +struct ipa_imm_cmd_hw_dma_shared_mem_v_4_0 { + u64 sw_rsvd:15; + u64 clear_after_read:1; + u64 size:16; + u64 local_addr:16; + u64 direction:1; + u64 rsvd:15; + u64 system_addr:64; +}; + +/* + * struct ipa_imm_cmd_hw_ip_packet_tag_status - + * IP_PACKET_TAG_STATUS command payload in H/W format. + * This cmd is used for to allow SW to track HW processing by setting a TAG + * value that is passed back to SW inside Packet Status information. + * TAG info will be provided as part of Packet Status info generated for + * the next pkt transferred over the pipe. + * This immediate command must be followed by a packet in the same transfer. + * @sw_rsvd: Ignored by H/W. My be used by S/W + * @tag: Tag that is provided back to SW + */ +struct ipa_imm_cmd_hw_ip_packet_tag_status { + u64 sw_rsvd:16; + u64 tag:48; +}; + +/* + * struct ipa_imm_cmd_hw_dma_task_32b_addr - + * IPA_DMA_TASK_32B_ADDR command payload in H/W format. + * Used by clients using 32bit addresses. Used to perform DMA operation on + * multiple descriptors. + * The Opcode is dynamic, where it holds the number of buffer to process + * @sw_rsvd: Ignored by H/W. My be used by S/W + * @cmplt: Complete flag: When asserted IPA will interrupt SW when the entire + * DMA related data was completely xfered to its destination. + * @eof: Enf Of Frame flag: When asserted IPA will assert the EOT to the + * dest client. This is used used for aggr sequence + * @flsh: Flush flag: When asserted, pkt will go through the IPA blocks but + * will not be xfered to dest client but rather will be discarded + * @lock: Lock pipe flag: When asserted, IPA will stop processing descriptors + * from other EPs in the same src grp (RX queue) + * @unlock: Unlock pipe flag: When asserted, IPA will stop exclusively + * servicing current EP out of the src EPs of the grp (RX queue) + * @size1: Size of buffer1 data + * @addr1: Pointer to buffer1 data + * @packet_size: Total packet size. If a pkt send using multiple DMA_TASKs, + * only the first one needs to have this field set. It will be ignored + * in subsequent DMA_TASKs until the packet ends (EOT). First DMA_TASK + * must contain this field (2 or more buffers) or EOT. + */ +struct ipa_imm_cmd_hw_dma_task_32b_addr { + u64 sw_rsvd:11; + u64 cmplt:1; + u64 eof:1; + u64 flsh:1; + u64 lock:1; + u64 unlock:1; + u64 size1:16; + u64 addr1:32; + u64 packet_size:16; +}; + + + +/* IPA Status packet H/W structures and info */ + +/* + * struct ipa_status_pkt_hw - IPA status packet payload in H/W format. + * This structure describes the status packet H/W structure for the + * following statuses: IPA_STATUS_PACKET, IPA_STATUS_DROPPED_PACKET, + * IPA_STATUS_SUSPENDED_PACKET. + * Other statuses types has different status packet structure. + * @status_opcode: The Type of the status (Opcode). + * @exception: (not bitmask) - the first exception that took place. + * In case of exception, src endp and pkt len are always valid. + * @status_mask: Bit mask specifying on which H/W blocks the pkt was processed. + * @pkt_len: Pkt pyld len including hdr, include retained hdr if used. Does + * not include padding or checksum trailer len. + * @endp_src_idx: Source end point index. + * @rsvd1: reserved + * @endp_dest_idx: Destination end point index. + * Not valid in case of exception + * @rsvd2: reserved + * @metadata: meta data value used by packet + * @flt_local: Filter table location flag: Does matching flt rule belongs to + * flt tbl that resides in lcl memory? (if not, then system mem) + * @flt_hash: Filter hash hit flag: Does matching flt rule was in hash tbl? + * @flt_global: Global filter rule flag: Does matching flt rule belongs to + * the global flt tbl? (if not, then the per endp tables) + * @flt_ret_hdr: Retain header in filter rule flag: Does matching flt rule + * specifies to retain header? + * Starting IPA4.5, this will be true only if packet has L2 header. + * @flt_rule_id: The ID of the matching filter rule. This info can be combined + * with endp_src_idx to locate the exact rule. ID=0x3FF reserved to specify + * flt miss. In case of miss, all flt info to be ignored + * @rt_local: Route table location flag: Does matching rt rule belongs to + * rt tbl that resides in lcl memory? (if not, then system mem) + * @rt_hash: Route hash hit flag: Does matching rt rule was in hash tbl? + * @ucp: UC Processing flag. + * @rt_tbl_idx: Index of rt tbl that contains the rule on which was a match + * @rt_rule_id: The ID of the matching rt rule. This info can be combined + * with rt_tbl_idx to locate the exact rule. ID=0x3FF reserved to specify + * rt miss. In case of miss, all rt info to be ignored + * @nat_hit: NAT hit flag: Was their NAT hit? + * @nat_entry_idx: Index of the NAT entry used of NAT processing + * @nat_type: Defines the type of the NAT operation: + * 00: No NAT + * 01: Source NAT + * 10: Destination NAT + * 11: Reserved + * @tag_info: S/W defined value provided via immediate command + * @seq_num: Per source endp unique packet sequence number + * @time_of_day_ctr: running counter from IPA clock + * @hdr_local: Header table location flag: In header insertion, was the header + * taken from the table resides in local memory? (If no, then system mem) + * @hdr_offset: Offset of used header in the header table + * @frag_hit: Frag hit flag: Was their frag rule hit in H/W frag table? + * @frag_rule: Frag rule index in H/W frag table in case of frag hit + * @hw_specific: H/W specific reserved value + */ +struct ipa_gen_pkt_status_hw { + u64 status_opcode:8; + u64 exception:8; + u64 status_mask:16; + u64 pkt_len:16; + u64 endp_src_idx:5; + u64 rsvd1:3; + u64 endp_dest_idx:5; + u64 rsvd2:3; + u64 metadata:32; + u64 flt_local:1; + u64 flt_hash:1; + u64 flt_global:1; + u64 flt_ret_hdr:1; + u64 flt_rule_id:10; + u64 rt_local:1; + u64 rt_hash:1; + u64 ucp:1; + u64 rt_tbl_idx:5; + u64 rt_rule_id:10; + u64 nat_hit:1; + u64 nat_entry_idx:13; + u64 nat_type:2; + u64 tag_info:48; + u64 seq_num:8; + u64 time_of_day_ctr:24; + u64 hdr_local:1; + u64 hdr_offset:10; + u64 frag_hit:1; + u64 frag_rule:4; + u64 hw_specific:16; +} __packed; + +/* + * struct ipa_frag_pkt_status_hw - IPA status packet payload in H/W format. + * This structure describes the frag status packet H/W structure for the + * following statuses: IPA_NEW_FRAG_RULE. + * @status_opcode: The Type of the status (Opcode). + * @frag_rule_idx: Frag rule index value. + * @rsvd1: reserved + * @tbl_idx: Table index valid or not. + * @endp_src_idx: Source end point index. + * @exception: (not bitmask) - the first exception that took place. + * In case of exception, src endp and pkt len are always valid. + * @rsvd2: reserved + * @seq_num: Packet sequence number. + * @src_ip_addr: Source packet IP address. + * @dest_ip_addr: Destination packet IP address. + * @rsvd3: reserved + * @nat_type: Defines the type of the NAT operation: + * 00: No NAT + * 01: Source NAT + * 10: Destination NAT + * 11: Reserved + * @protocol: Protocal number. + * @ip_id: IP packet IP ID number. + * @tlated_ip_addr: IP address. + * @hdr_local: Header table location flag: In header insertion, was the header + * taken from the table resides in local memory? (If no, then system mem) + * @hdr_offset: Offset of used header in the header table + * @endp_dest_idx: Destination end point index. + * @ip_cksum_diff: IP packet checksum difference. + * @metadata: meta data value used by packet + * @rsvd4: reserved + */ +struct ipa_frag_pkt_status_hw { + u64 status_opcode:8; + u64 frag_rule_idx:4; + u64 reserved_1:3; + u64 tbl_idx:1; + u64 endp_src_idx:5; + u64 exception:1; + u64 reserved_2:2; + u64 seq_num:8; + u64 src_ip_addr:32; + u64 dest_ip_addr:32; + u64 reserved_3:6; + u64 nat_type:2; + u64 protocol:8; + u64 ip_id:16; + u64 tlated_ip_addr:32; + u64 hdr_local:1; + u64 hdr_offset:10; + u64 endp_dest_idx:5; + u64 ip_cksum_diff:16; + u64 metadata:32; + u64 reserved_4:32; +} __packed; + +/* + * struct ipa_status_pkt_hw_v5_0 - IPA v5.0 status packet payload in H/W format. + * This structure describes the status packet H/W structure for the + * following statuses: IPA_STATUS_PACKET, IPA_STATUS_DROPPED_PACKET, + * IPA_STATUS_SUSPENDED_PACKET. + * Other statuses types has different status packet structure. + * @status_opcode: The Type of the status (Opcode). + * @exception: (not bitmask) - the first exception that took place. + * In case of exception, src endp and pkt len are always valid. + * @status_mask: Bit mask specifying on which H/W blocks the pkt was processed. + * @pkt_len: Pkt pyld len including hdr, include retained hdr if used. Does + * not include padding or checksum trailer len. + * @endp_src_idx: Source end point index. + * @reserved_1: reserved + * @rt_local: Route table location flag: Does matching rt rule belongs to + * rt tbl that resides in lcl memory? (if not, then system mem) + * @rt_hash: Route hash hit flag: Does matching rt rule was in hash tbl? + * Not valid in case of exception + * @reserved_2: reserved + * @metadata: meta data value used by packet + * @flt_local: Filter table location flag: Does matching flt rule belongs to + * flt tbl that resides in lcl memory? (if not, then system mem) + * @flt_hash: Filter hash hit flag: Does matching flt rule was in hash tbl? + * @flt_global: Global filter rule flag: Does matching flt rule belongs to + * the global flt tbl? (if not, then the per endp tables) + * @flt_ret_hdr: Retain header in filter rule flag: Does matching flt rule + * specifies to retain header? + * Starting IPA4.5, this will be true only if packet has L2 header. + * @flt_rule_id: The ID of the matching filter rule. This info can be combined + * with endp_src_idx to locate the exact rule. ID=0x3FF reserved to specify + * flt miss. In case of miss, all flt info to be ignored + * @rt_tbl_idx: Index of rt tbl that contains the rule on which was a match + * @rt_rule_id: The ID of the matching rt rule. This info can be combined + * with rt_tbl_idx to locate the exact rule. ID=0x3FF reserved to specify + * rt miss. In case of miss, all rt info to be ignored + * @nat_hit: NAT hit flag: Was their NAT hit? + * @nat_entry_idx: Index of the NAT entry used of NAT processing + * @nat_type: Defines the type of the NAT operation: + * 00: No NAT + * 01: Source NAT + * 10: Destination NAT + * 11: Reserved + * @tag_info: S/W defined value provided via immediate command + * @seq_num: Per source endp unique packet sequence number + * @time_of_day_ctr: running counter from IPA clock + * @hdr_local: Header table location flag: In header insertion, was the header + * taken from the table resides in local memory? (If no, then system mem) + * @hdr_offset: Offset of used header in the header table + * @frag_hit: Frag hit flag: Was their frag rule hit in H/W frag table? + * @frag_rule: Frag rule index in H/W frag table in case of frag hit + * @endp_dest_idx: Destination end point index. + * @hw_specific: H/W specific reserved value + * @ucp: UC Processing flag. + */ +struct ipa_gen_pkt_status_hw_v5_0 { + u64 status_opcode:8; + u64 exception:8; + u64 status_mask:16; + u64 pkt_len:16; + u64 endp_src_idx:8; + u64 reserved_1:3; + u64 rt_local:1; + u64 rt_hash:1; + u64 reserved_2:3; + u64 metadata:32; + u64 flt_local:1; + u64 flt_hash:1; + u64 flt_global:1; + u64 flt_ret_hdr:1; + u64 flt_rule_id:10; + u64 rt_tbl_idx:8; + u64 rt_rule_id:10; + u64 nat_hit:1; + u64 nat_entry_idx:13; + u64 nat_type:2; + u64 tag_info:48; + u64 seq_num:8; + u64 time_of_day_ctr:24; + u64 hdr_local:1; + u64 hdr_offset:10; + u64 frag_hit:1; + u64 frag_rule:4; + u64 endp_dest_idx:8; + u64 hw_specific:7; + u64 ucp:1; +} __packed; + +/* + * struct ipa_frag_pkt_status_hw_v5_0 - + * IPA v5.0 status packet payload in H/W format. + * This structure describes the frag status packet H/W structure for the + * following statuses: IPA_NEW_FRAG_RULE. + * @status_opcode: The Type of the status (Opcode). + * @frag_rule_idx: Frag rule index value. + * @reserved_1: reserved + * @exception: (not bitmask) - the first exception that took place. + * @tbl_idx: Table index valid or not. + * @endp_src_idx: Source end point index. + * In case of exception, src endp and pkt len are always valid. + * @seq_num: Packet sequence number. + * @src_ip_addr: Source packet IP address. + * @dest_ip_addr: Destination packet IP address. + * @reserved_2: reserved + * @nat_type: Defines the type of the NAT operation: + * 00: No NAT + * 01: Source NAT + * 10: Destination NAT + * 11: Reserved + * @protocol: Protocal number. + * @ip_id: IP packet IP ID number. + * @tlated_ip_addr: IP address. + * @hdr_local: Header table location flag: In header insertion, was the header + * taken from the table resides in local memory? (If no, then system mem) + * @hdr_offset: Offset of used header in the header table + * @reserved_3: reserved + * @ip_cksum_diff: IP packet checksum difference. + * @metadata: meta data value used by packet + * @reserved_4: reserved + * @endp_dest_idx: Destination end point index. + * @reserved_5: reserved + */ +struct ipa_frag_pkt_status_hw_v5_0 { + u64 status_opcode:8; + u64 frag_rule_idx:4; + u64 reserved_1:2; + u64 exception:1; + u64 tbl_idx:1; + u64 endp_src_idx:8; + u64 seq_num:8; + u64 src_ip_addr:32; + u64 dest_ip_addr:32; + u64 reserved_2:6; + u64 nat_type:2; + u64 protocol:8; + u64 ip_id:16; + u64 tlated_ip_addr:32; + u64 hdr_local:1; + u64 hdr_offset:10; + u64 reserved_3:5; + u64 ip_cksum_diff:16; + u64 metadata:32; + u64 reserved_4:16; + u64 endp_dest_idx:8; + u64 reserved_5:8; +} __packed; + +/* + * struct ipa_status_pkt_hw_v5_5 - IPA v5.5 status packet payload in H/W format. + * This structure describes the status packet H/W structure for the + * following statuses: IPA_STATUS_PACKET, IPA_STATUS_DROPPED_PACKET, + * IPA_STATUS_SUSPENDED_PACKET. + * Other statuses types has different status packet structure. + * @status_opcode: The Type of the status (Opcode). + * @exception: (not bitmask) - the first exception that took place. + * In case of exception, src endp and pkt len are always valid. + * @status_mask: Bit mask specifying on which H/W blocks the pkt was processed. + * @pkt_len: Pkt pyld len including hdr, include retained hdr if used. Does + * not include padding or checksum trailer len. + * @endp_src_idx: Source end point index. + * @reserved_1: reserved + * @rt_local: Route table location flag: Does matching rt rule belongs to + * rt tbl that resides in lcl memory? (if not, then system mem) + * @rt_hash: Route hash hit flag: Does matching rt rule was in hash tbl? + * Not valid in case of exception + * @reserved_2: reserved + * @metadata: meta data value used by packet + * @flt_local: Filter table location flag: Does matching flt rule belongs to + * flt tbl that resides in lcl memory? (if not, then system mem) + * @flt_hash: Filter hash hit flag: Does matching flt rule was in hash tbl? + * @flt_global: Global filter rule flag: Does matching flt rule belongs to + * the global flt tbl? (if not, then the per endp tables) + * @flt_ret_hdr: Retain header in filter rule flag: Does matching flt rule + * specifies to retain header? + * Starting IPA4.5, this will be true only if packet has L2 header. + * @flt_rule_id: The ID of the matching filter rule. This info can be combined + * with endp_src_idx to locate the exact rule. ID=0x3FF reserved to specify + * flt miss. In case of miss, all flt info to be ignored + * @rt_tbl_idx: Index of rt tbl that contains the rule on which was a match + * @rt_rule_id: The ID of the matching rt rule. This info can be combined + * with rt_tbl_idx to locate the exact rule. ID=0x3FF reserved to specify + * rt miss. In case of miss, all rt info to be ignored + * @nat_hit: NAT hit flag: Was their NAT hit? + * @nat_entry_idx: Index of the NAT entry used of NAT processing + * @nat_type: Defines the type of the NAT operation: + * 00: No NAT + * 01: Source NAT + * 10: Destination NAT + * 11: Reserved + * @tag_info: S/W defined value provided via immediate command + * @egress_tc: Egress traffic class index. + * @ingress_tc: Ingress traffic class index. + * @seq_num: Per source endp unique packet sequence number + * @time_of_day_ctr: running counter from IPA clock + * @hdr_local: Header table location flag: In header insertion, was the header + * taken from the table resides in local memory? (If no, then system mem) + * @hdr_offset: Offset of used header in the header table + * @frag_hit: Frag hit flag: Was their frag rule hit in H/W frag table? + * @frag_rule: Frag rule index in H/W frag table in case of frag hit + * @endp_dest_idx: Destination end point index. + * @hw_specific: H/W specific reserved value + * @ucp: UC Processing flag. + * @nat_exc_suppress: nat exception supress flag, indicates whether + * nat exception is suppressed. + * @tsp: Traffic shaping policing flag, indicates traffic class info + * overwrites tag info. + * @ttl_dec: ttl update flag, indicates whether ttl is updated. + */ +struct ipa_gen_pkt_status_hw_v5_5 { + u64 status_opcode:8; + u64 exception:8; + u64 status_mask:16; + u64 pkt_len:16; + u64 endp_src_idx:8; + u64 reserved_1:3; + u64 rt_local:1; + u64 rt_hash:1; + u64 reserved_2:3; + u64 metadata:32; + u64 flt_local:1; + u64 flt_hash:1; + u64 flt_global:1; + u64 flt_ret_hdr:1; + u64 flt_rule_id:10; + u64 rt_tbl_idx:8; + u64 rt_rule_id:10; + u64 nat_hit:1; + u64 nat_entry_idx:13; + u64 nat_type:2; + u64 tag_info:36; + u64 egress_tc:6; + u64 ingress_tc:6; + u64 seq_num:8; + u64 time_of_day_ctr:24; + u64 hdr_local:1; + u64 hdr_offset:10; + u64 frag_hit:1; + u64 frag_rule:4; + u64 endp_dest_idx:8; + u64 hw_specific:4; + u64 nat_exc_suppress:1; + u64 tsp:1; + u64 ttl_dec:1; + u64 ucp:1; +} __packed; + +/* + * struct ipa_frag_pkt_status_hw_v5_5 - + * IPA v5.5 status packet payload in H/W format. + * This structure describes the frag status packet H/W structure for the + * following statuses: IPA_NEW_FRAG_RULE. + * @status_opcode: The Type of the status (Opcode). + * @frag_rule_idx: Frag rule index value. + * @reserved_1: reserved + * @exception: (not bitmask) - the first exception that took place. + * @tbl_idx: Table index valid or not. + * @endp_src_idx: Source end point index. + * In case of exception, src endp and pkt len are always valid. + * @seq_num: Packet sequence number. + * @src_ip_addr: Source packet IP address. + * @dest_ip_addr: Destination packet IP address. + * @ret: l2 header retained flag, indicates whether l2 header is retained + * or not. + * @ll: low latency indication. + * @ttl_dec: ttl update indication. + * @reserved_2: reserved + * @nat_type: Defines the type of the NAT operation: + * 00: No NAT + * 01: Source NAT + * 10: Destination NAT + * 11: Reserved + * @protocol: Protocal number. + * @ip_id: IP packet IP ID number. + * @tlated_ip_addr: IP address. + * @hdr_offset: Offset of used header in the header table + * @ingress_tc: ingress traffic class index + * @ip_cksum_diff: IP packet checksum difference. + * @metadata: meta data value used by packet + * @reserved_4: reserved + * @endp_dest_idx: Destination end point index. + * @egress_tc: egress traffic class index + * @pd: router disabled ingress policer. + * @hdr_local: Header table location flag: In header insertion, was the header + * taken from the table resides in local memory? (If no, then system mem) + */ +struct ipa_frag_pkt_status_hw_v5_5 { + u64 status_opcode:8; + u64 frag_rule_idx:4; + u64 reserved_1:2; + u64 exception:1; + u64 tbl_idx:1; + u64 endp_src_idx:8; + u64 seq_num:8; + u64 src_ip_addr:32; + u64 dest_ip_addr:32; + u64 ret:1; + u64 ll:1; + u64 ttl_dec:1; + u64 reserved_2:3; + u64 nat_type:2; + u64 protocol:8; + u64 ip_id:16; + u64 tlated_ip_addr:32; + u64 hdr_offset:10; + u64 ingress_tc:6; + u64 ip_cksum_diff:16; + u64 metadata:32; + u64 reserved_4:16; + u64 endp_dest_idx:8; + u64 egress_tc:6; + u64 pd:1; + u64 hdr_local:1; +} __packed; + + +union ipa_pkt_status_hw { + struct ipa_gen_pkt_status_hw ipa_pkt; + struct ipa_frag_pkt_status_hw frag_pkt; +} __packed; + +union ipa_pkt_status_hw_v5_0 { + struct ipa_gen_pkt_status_hw_v5_0 ipa_pkt; + struct ipa_frag_pkt_status_hw_v5_0 frag_pkt; +} __packed; + +union ipa_pkt_status_hw_v5_5 { + struct ipa_gen_pkt_status_hw_v5_5 ipa_pkt; + struct ipa_frag_pkt_status_hw_v5_5 frag_pkt; +} __packed; + +/* Size of H/W Packet Status */ +#define IPA3_0_PKT_STATUS_SIZE 32 + +/* Headers and processing context H/W structures and definitions */ + +/* uCP command numbers */ +#define IPA_HDR_UCP_RTP_METADATA_STREAM0 0 +#define IPA_HDR_UCP_RTP_METADATA_STREAM1 1 +#define IPA_HDR_UCP_RTP_METADATA_STREAM2 2 +#define IPA_HDR_UCP_RTP_METADATA_STREAM3 3 +#define IPA_HDR_UCP_802_3_TO_802_3 6 +#define IPA_HDR_UCP_802_3_TO_ETHII 7 +#define IPA_HDR_UCP_ETHII_TO_802_3 8 +#define IPA_HDR_UCP_ETHII_TO_ETHII 9 +#define IPA_HDR_UCP_L2TP_HEADER_ADD 10 +#define IPA_HDR_UCP_L2TP_HEADER_REMOVE 11 +#define IPA_HDR_UCP_L2TP_UDP_HEADER_ADD 12 +#define IPA_HDR_UCP_L2TP_UDP_HEADER_REMOVE 13 +#define IPA_HDR_UCP_ETHII_TO_ETHII_EX 14 +#define IPA_HDR_UCP_SET_DSCP 16 +#define IPA_HDR_UCP_EoGRE_HEADER_ADD 17 +#define IPA_HDR_UCP_EoGRE_HEADER_REMOVE 18 + +/* Processing context TLV type */ +#define IPA_PROC_CTX_TLV_TYPE_END 0 +#define IPA_PROC_CTX_TLV_TYPE_HDR_ADD 1 +#define IPA_PROC_CTX_TLV_TYPE_PROC_CMD 3 + +/** + * struct ipa_hw_hdr_proc_ctx_tlv - + * HW structure of IPA processing context header - TLV part + * @type: 0 - end type + * 1 - header addition type + * 3 - processing command type + * @length: number of bytes after tlv + * for type: + * 0 - needs to be 0 + * 1 - header addition length + * 3 - number of 32B including type and length. + * @value: specific value for type + * for type: + * 0 - needs to be 0 + * 1 - header length + * 3 - command ID (see IPA_HDR_UCP_* definitions) + */ +struct ipa_hw_hdr_proc_ctx_tlv { + u32 type:8; + u32 length:8; + u32 value:16; +}; + +/** + * struct ipa_hw_hdr_proc_ctx_hdr_add - + * HW structure of IPA processing context - add header tlv + * @tlv: IPA processing context TLV + * @hdr_addr: processing context header address + */ +struct ipa_hw_hdr_proc_ctx_hdr_add { + struct ipa_hw_hdr_proc_ctx_tlv tlv; + u32 hdr_addr; + u32 hdr_addr_hi; +}; + +struct ipa_hw_hdr_proc_ctx_rtp_add_hdr { + struct ipa_hw_hdr_proc_ctx_tlv tlv; + struct ipa_rtp_header_add_procparams rtp_params; +}; + +/** + * struct ipa_hw_hdr_proc_ctx_l2tp_add_hdr - + * HW structure of IPA processing context - add l2tp header tlv + * @tlv: IPA processing context TLV + * @l2tp_params: l2tp parameters + */ +struct ipa_hw_hdr_proc_ctx_l2tp_add_hdr { + struct ipa_hw_hdr_proc_ctx_tlv tlv; + struct ipa_l2tp_header_add_procparams l2tp_params; +}; + +/** + * struct ipa_hw_hdr_proc_ctx_l2tp_remove_hdr - + * HW structure of IPA processing context - remove l2tp header tlv + * @tlv: IPA processing context TLV + * @l2tp_params: l2tp parameters + */ +struct ipa_hw_hdr_proc_ctx_l2tp_remove_hdr { + struct ipa_hw_hdr_proc_ctx_tlv tlv; + struct ipa_l2tp_header_remove_procparams l2tp_params; +}; + +/** + * struct ipa_hw_hdr_proc_ctx_add_hdr_seq - + * IPA processing context header - add header sequence + * @hdr_add: add header command + * @end: tlv end command (cmd.type must be 0) + */ +struct ipa_hw_hdr_proc_ctx_add_hdr_seq { + struct ipa_hw_hdr_proc_ctx_hdr_add hdr_add; + struct ipa_hw_hdr_proc_ctx_tlv end; +}; + +/** + * struct ipa_hw_hdr_proc_ctx_add_hdr_cmd_seq - + * IPA processing context header - process command sequence + * @hdr_add: add header command + * @cmd: tlv processing command (cmd.type must be 3) + * @end: tlv end command (cmd.type must be 0) + */ +struct ipa_hw_hdr_proc_ctx_add_hdr_cmd_seq { + struct ipa_hw_hdr_proc_ctx_hdr_add hdr_add; + struct ipa_hw_hdr_proc_ctx_tlv cmd; + struct ipa_hw_hdr_proc_ctx_tlv end; +}; + +/** + * struct ipa_hw_hdr_proc_ctx_add_l2tp_hdr_cmd_seq - + * IPA processing context header - process command sequence + * @hdr_add: add header command + * @l2tp_params: l2tp params for header addition + * @end: tlv end command (cmd.type must be 0) + */ +struct ipa_hw_hdr_proc_ctx_add_l2tp_hdr_cmd_seq { + struct ipa_hw_hdr_proc_ctx_hdr_add hdr_add; + struct ipa_hw_hdr_proc_ctx_l2tp_add_hdr l2tp_params; + struct ipa_hw_hdr_proc_ctx_tlv end; +}; + +/** + * struct ipa_hw_hdr_proc_ctx_remove_l2tp_hdr_cmd_seq - + * IPA processing context header - process command sequence + * @hdr_add: add header command + * @l2tp_params: l2tp params for header removal + * @end: tlv end command (cmd.type must be 0) + */ +struct ipa_hw_hdr_proc_ctx_remove_l2tp_hdr_cmd_seq { + struct ipa_hw_hdr_proc_ctx_hdr_add hdr_add; + struct ipa_hw_hdr_proc_ctx_l2tp_remove_hdr l2tp_params; + struct ipa_hw_hdr_proc_ctx_tlv end; +}; + +/** + * struct ipa_hw_hdr_proc_ctx_add_hdr_ex - + * HW structure of IPA processing context - add generic header + * @tlv: IPA processing context TLV + * @params: generic eth2 to eth2 parameters + */ +struct ipa_hw_hdr_proc_ctx_add_hdr_ex { + struct ipa_hw_hdr_proc_ctx_tlv tlv; + struct ipa_eth_II_to_eth_II_ex_procparams params; +}; + +/** + * struct ipa_hw_hdr_proc_ctx_add_hdr_cmd_seq_ex - + * IPA processing context header - process command sequence + * @hdr_add: add header command + * @params: params for header generic header add + * @end: tlv end command (cmd.type must be 0) + */ +struct ipa_hw_hdr_proc_ctx_add_hdr_cmd_seq_ex { + struct ipa_hw_hdr_proc_ctx_hdr_add hdr_add; + struct ipa_hw_hdr_proc_ctx_add_hdr_ex hdr_add_ex; + struct ipa_hw_hdr_proc_ctx_tlv end; +}; + +/** + * struct ipa_hw_hdr_proc_ctx_remove_l2tp_udp_hdr_cmd_seq - + * IPA processing context header - process command sequence + * @l2tp_params: l2tp params for header removal + * @end: tlv end command (cmd.type must be 0) + */ +struct ipa_hw_hdr_proc_ctx_remove_l2tp_udp_hdr_cmd_seq { + struct ipa_hw_hdr_proc_ctx_l2tp_remove_hdr l2tp_params; + struct ipa_hw_hdr_proc_ctx_tlv end; +}; + +/** + * struct ipa_hw_hdr_proc_ctx_eogre_add_hdr - + * HW structure of IPA processing context - add eogre header tlv + * @tlv: IPA processing context TLV + * @eogre_params: eogre parameters + */ +struct ipa_hw_hdr_proc_ctx_eogre_add_hdr { + struct ipa_hw_hdr_proc_ctx_tlv tlv; + struct ipa_eogre_header_add_procparams eogre_params; +}; + +/** + * struct ipa_hw_hdr_proc_ctx_eogre_remove_hdr - + * HW structure of IPA processing context - remove eogre header tlv + * @tlv: IPA processing context TLV + * @eogre_params: eogre parameters + */ +struct ipa_hw_hdr_proc_ctx_eogre_remove_hdr { + struct ipa_hw_hdr_proc_ctx_tlv tlv; + struct ipa_eogre_header_remove_procparams eogre_params; +}; + +/** + * struct ipa_hw_hdr_proc_ctx_add_eogre_hdr_cmd_seq - + * IPA processing context header - process command sequence + * @hdr_add: add header command + * @eogre_params: eogre params for header addition + * @end: tlv end command (cmd.type must be 0) + */ +struct ipa_hw_hdr_proc_ctx_add_eogre_hdr_cmd_seq { + struct ipa_hw_hdr_proc_ctx_hdr_add hdr_add; + struct ipa_hw_hdr_proc_ctx_eogre_add_hdr eogre_params; + struct ipa_hw_hdr_proc_ctx_tlv end; +}; + +/** + * struct ipa_hw_hdr_proc_ctx_remove_eogre_hdr_cmd_seq - + * IPA processing context header - process command sequence + * @hdr_add: add header command + * @eogre_params: eogre params for header removal + * @end: tlv end command (cmd.type must be 0) + */ +struct ipa_hw_hdr_proc_ctx_remove_eogre_hdr_cmd_seq { + struct ipa_hw_hdr_proc_ctx_hdr_add hdr_add; + struct ipa_hw_hdr_proc_ctx_eogre_remove_hdr eogre_params; + struct ipa_hw_hdr_proc_ctx_tlv end; +}; + +/** + * struct ipa_hw_hdr_proc_ctx_rtp_hdr_cmd_seq - + * IPA processing context header - process command sequence + * @hdr_add: add header command + * @rtp_params: rtp params for header addition + * @end: tlv end command (cmd.type must be 0) + */ +struct ipa_hw_hdr_proc_ctx_rtp_hdr_cmd_seq { + struct ipa_hw_hdr_proc_ctx_hdr_add hdr_add; + struct ipa_hw_hdr_proc_ctx_rtp_add_hdr rtp_params; + struct ipa_hw_hdr_proc_ctx_tlv end; +}; + +#endif /* _IPAHAL_I_H_ */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_nat.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_nat.c new file mode 100644 index 0000000000..53e5efb0f9 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_nat.c @@ -0,0 +1,563 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. + */ + +#include +#include "ipahal_nat.h" +#include "ipahal_nat_i.h" +#include "ipahal_i.h" + +#define IPA_64_LOW_32_MASK (0xFFFFFFFF) +#define IPA_64_HIGH_32_MASK (0xFFFFFFFF00000000ULL) + +static const char *ipahal_nat_type_to_str[IPA_NAT_MAX] = { + __stringify(IPAHAL_NAT_IPV4), + __stringify(IPAHAL_NAT_IPV4_INDEX), + __stringify(IPAHAL_NAT_IPV4_PDN), + __stringify(IPAHAL_NAT_IPV6CT) +}; + +static size_t ipa_nat_ipv4_entry_size_v_3_0(void) +{ + return sizeof(struct ipa_nat_hw_ipv4_entry); +} + +static size_t ipa_nat_ipv4_index_entry_size_v_3_0(void) +{ + return sizeof(struct ipa_nat_hw_indx_entry); +} + +static size_t ipa_nat_ipv4_pdn_entry_size_v_4_0(void) +{ + return sizeof(struct ipa_nat_hw_pdn_entry); +} + +static size_t ipa_nat_ipv6ct_entry_size_v_4_0(void) +{ + return sizeof(struct ipa_nat_hw_ipv6ct_entry); +} + +static bool ipa_nat_ipv4_is_entry_zeroed_v_3_0(const void *entry) +{ + struct ipa_nat_hw_ipv4_entry zero_entry = { 0 }; + + return (memcmp(&zero_entry, entry, sizeof(zero_entry))) ? false : true; +} + +static bool ipa_nat_ipv4_is_index_entry_zeroed_v_3_0(const void *entry) +{ + struct ipa_nat_hw_indx_entry zero_entry = { 0 }; + + return (memcmp(&zero_entry, entry, sizeof(zero_entry))) ? false : true; +} + +static bool ipa_nat_ipv4_is_pdn_entry_zeroed_v_4_0(const void *entry) +{ + struct ipa_nat_hw_pdn_entry zero_entry = { 0 }; + + return (memcmp(&zero_entry, entry, sizeof(zero_entry))) ? false : true; +} + +static bool ipa_nat_ipv6ct_is_entry_zeroed_v_4_0(const void *entry) +{ + struct ipa_nat_hw_ipv6ct_entry zero_entry = { 0 }; + + return (memcmp(&zero_entry, entry, sizeof(zero_entry))) ? false : true; +} + +static bool ipa_nat_ipv4_is_entry_valid_v_3_0(const void *entry) +{ + struct ipa_nat_hw_ipv4_entry *hw_entry = + (struct ipa_nat_hw_ipv4_entry *)entry; + + return hw_entry->enable && + hw_entry->protocol != IPAHAL_NAT_INVALID_PROTOCOL; +} + +static bool ipa_nat_ipv4_is_index_entry_valid_v_3_0(const void *entry) +{ + struct ipa_nat_hw_indx_entry *hw_entry = + (struct ipa_nat_hw_indx_entry *)entry; + + return hw_entry->tbl_entry != 0; +} + +static bool ipa_nat_ipv4_is_pdn_entry_valid_v_4_0(const void *entry) +{ + struct ipa_nat_hw_pdn_entry *hw_entry = + (struct ipa_nat_hw_pdn_entry *)entry; + + return hw_entry->public_ip != 0; +} + +static bool ipa_nat_ipv6ct_is_entry_valid_v_4_0(const void *entry) +{ + struct ipa_nat_hw_ipv6ct_entry *hw_entry = + (struct ipa_nat_hw_ipv6ct_entry *)entry; + + return hw_entry->enable && + hw_entry->protocol != IPAHAL_NAT_INVALID_PROTOCOL; +} + +static int ipa_nat_ipv4_stringify_entry_v_3_0(const void *entry, + char *buff, size_t buff_size) +{ + const struct ipa_nat_hw_ipv4_entry *nat_entry = + (const struct ipa_nat_hw_ipv4_entry *)entry; + + return scnprintf(buff, buff_size, + "\t\tPrivate_IP=%pI4h Target_IP=%pI4h\n" + "\t\tNext_Index=%d Public_Port=%d\n" + "\t\tPrivate_Port=%d Target_Port=%d\n" + "\t\tIP_CKSM_delta=0x%x Enable=%s Redirect=%s\n" + "\t\tTime_stamp=0x%x Proto=%d\n" + "\t\tPrev_Index=%d Indx_tbl_entry=%d\n" + "\t\tTCP_UDP_cksum_delta=0x%x\n", + &nat_entry->private_ip, &nat_entry->target_ip, + nat_entry->next_index, nat_entry->public_port, + nat_entry->private_port, nat_entry->target_port, + nat_entry->ip_chksum, + (nat_entry->enable) ? "true" : "false", + (nat_entry->redirect) ? "Direct_To_APPS" : "Fwd_to_route", + nat_entry->time_stamp, nat_entry->protocol, + nat_entry->prev_index, nat_entry->indx_tbl_entry, + nat_entry->tcp_udp_chksum); +} + +static int ipa_nat_ipv4_stringify_entry_v_4_0(const void *entry, + char *buff, size_t buff_size) +{ + int length; + const struct ipa_nat_hw_ipv4_entry *nat_entry = + (const struct ipa_nat_hw_ipv4_entry *)entry; + + length = ipa_nat_ipv4_stringify_entry_v_3_0(entry, buff, buff_size); + + length += scnprintf(buff + length, buff_size - length, + "\t\tPDN_Index=%d\n", + nat_entry->pdn_index); + + return length; +} + + +static int ipa_nat_ipv4_stringify_entry_v_4_5(const void *entry, + char *buff, size_t buff_size) +{ + int length; + const struct ipa_nat_hw_ipv4_entry *nat_entry = + (const struct ipa_nat_hw_ipv4_entry *)entry; + + length = ipa_nat_ipv4_stringify_entry_v_4_0(entry, buff, buff_size); + + length += scnprintf(buff + length, buff_size - length, + "\t\tucp=%s address=%s uc_activation_index=%d\n", + (nat_entry->ucp) ? "Enabled" : "Disabled", + (nat_entry->s) ? "System" : "Local", + nat_entry->uc_activation_index); + + return length; +} + + +static int ipa_nat_ipv4_index_stringify_entry_v_3_0(const void *entry, + char *buff, size_t buff_size) +{ + const struct ipa_nat_hw_indx_entry *index_entry = + (const struct ipa_nat_hw_indx_entry *)entry; + + return scnprintf(buff, buff_size, + "\t\tTable_Entry=%d Next_Index=%d\n", + index_entry->tbl_entry, index_entry->next_index); +} + +static int ipa_nat_ipv4_pdn_stringify_entry_v_4_0(const void *entry, + char *buff, size_t buff_size) +{ + const struct ipa_nat_hw_pdn_entry *pdn_entry = + (const struct ipa_nat_hw_pdn_entry *)entry; + + return scnprintf(buff, buff_size, + "ip=%pI4h src_metadata=0x%X, dst_metadata=0x%X\n", + &pdn_entry->public_ip, + pdn_entry->src_metadata, pdn_entry->dst_metadata); +} + +static inline int ipa_nat_ipv6_stringify_addr(char *buff, size_t buff_size, + const char *msg, u64 lsb, u64 msb) +{ + struct in6_addr addr; + + addr.s6_addr32[0] = cpu_to_be32((msb & IPA_64_HIGH_32_MASK) >> 32); + addr.s6_addr32[1] = cpu_to_be32(msb & IPA_64_LOW_32_MASK); + addr.s6_addr32[2] = cpu_to_be32((lsb & IPA_64_HIGH_32_MASK) >> 32); + addr.s6_addr32[3] = cpu_to_be32(lsb & IPA_64_LOW_32_MASK); + + return scnprintf(buff, buff_size, + "\t\t%s_IPv6_Addr=%pI6c\n", msg, &addr); +} + +static int ipa_nat_ipv6ct_stringify_entry_v_4_0(const void *entry, + char *buff, size_t buff_size) +{ + int length = 0; + const struct ipa_nat_hw_ipv6ct_entry *ipv6ct_entry = + (const struct ipa_nat_hw_ipv6ct_entry *)entry; + + length += ipa_nat_ipv6_stringify_addr( + buff + length, + buff_size - length, + "Src", + ipv6ct_entry->src_ipv6_lsb, + ipv6ct_entry->src_ipv6_msb); + + length += ipa_nat_ipv6_stringify_addr( + buff + length, + buff_size - length, + "Dest", + ipv6ct_entry->dest_ipv6_lsb, + ipv6ct_entry->dest_ipv6_msb); + + length += scnprintf(buff + length, buff_size - length, + "\t\tEnable=%s Redirect=%s Time_Stamp=0x%x Proto=%d\n" + "\t\tNext_Index=%d Dest_Port=%d Src_Port=%d\n" + "\t\tDirection Settings: Out=%s In=%s\n" + "\t\tPrev_Index=%d\n", + (ipv6ct_entry->enable) ? "true" : "false", + (ipv6ct_entry->redirect) ? "Direct_To_APPS" : "Fwd_to_route", + ipv6ct_entry->time_stamp, + ipv6ct_entry->protocol, + ipv6ct_entry->next_index, + ipv6ct_entry->dest_port, + ipv6ct_entry->src_port, + (ipv6ct_entry->out_allowed) ? "Allow" : "Deny", + (ipv6ct_entry->in_allowed) ? "Allow" : "Deny", + ipv6ct_entry->prev_index); + + return length; +} + +static int ipa_nat_ipv6ct_stringify_entry_v_4_5(const void *entry, + char *buff, size_t buff_size) +{ + int length; + const struct ipa_nat_hw_ipv6ct_entry *ipv6ct_entry = + (const struct ipa_nat_hw_ipv6ct_entry *)entry; + + length = ipa_nat_ipv6ct_stringify_entry_v_4_0(entry, buff, buff_size); + + length += scnprintf(buff + length, buff_size - length, + "\t\tucp=%s address=%s uc_activation_index=%d\n", + (ipv6ct_entry->ucp) ? "Enabled" : "Disabled", + (ipv6ct_entry->s) ? "System" : "Local", + ipv6ct_entry->uc_activation_index); + + return length; +} + +static void ipa_nat_ipv4_pdn_construct_entry_v_4_0(const void *fields, + u32 *address) +{ + const struct ipahal_nat_pdn_entry *pdn_entry = + (const struct ipahal_nat_pdn_entry *)fields; + + struct ipa_nat_hw_pdn_entry *pdn_entry_address = + (struct ipa_nat_hw_pdn_entry *)address; + + memset(pdn_entry_address, 0, sizeof(struct ipa_nat_hw_pdn_entry)); + + pdn_entry_address->public_ip = pdn_entry->public_ip; + pdn_entry_address->src_metadata = pdn_entry->src_metadata; + pdn_entry_address->dst_metadata = pdn_entry->dst_metadata; +} + +static void ipa_nat_ipv4_pdn_parse_entry_v_4_0(void *fields, + const u32 *address) +{ + struct ipahal_nat_pdn_entry *pdn_entry = + (struct ipahal_nat_pdn_entry *)fields; + + const struct ipa_nat_hw_pdn_entry *pdn_entry_address = + (const struct ipa_nat_hw_pdn_entry *)address; + + pdn_entry->public_ip = pdn_entry_address->public_ip; + pdn_entry->src_metadata = pdn_entry_address->src_metadata; + pdn_entry->dst_metadata = pdn_entry_address->dst_metadata; +} + +/* + * struct ipahal_nat_obj - H/W information for specific IPA version + * @entry_size - CB to get the size of the entry + * @is_entry_zeroed - CB to determine whether an entry is definitely zero + * @is_entry_valid - CB to determine whether an entry is valid + * Validity criterium depends on entry type. E.g. for NAT base table + * Entry need to be with valid protocol and enabled. + * @stringify_entry - CB to create string that represents an entry + * @construct_entry - CB to create NAT entry using the given fields + * @parse_entry - CB to parse NAT entry to the given fields structure + */ +struct ipahal_nat_obj { + size_t (*entry_size)(void); + bool (*is_entry_zeroed)(const void *entry); + bool (*is_entry_valid)(const void *entry); + int (*stringify_entry)(const void *entry, char *buff, size_t buff_size); + void (*construct_entry)(const void *fields, u32 *address); + void (*parse_entry)(void *fields, const u32 *address); +}; + +/* + * This table contains the info regard each NAT type for IPAv3 and later. + * Information like: get entry size and stringify entry functions. + * All the information on all the NAT types on IPAv3 are statically + * defined below. If information is missing regard some NAT type on some + * IPA version, the init function will fill it with the information from the + * previous IPA version. + * Information is considered missing if all of the fields are 0 + */ +static struct ipahal_nat_obj ipahal_nat_objs[IPA_HW_MAX][IPA_NAT_MAX] = { + /* IPAv3 */ + [IPA_HW_v3_0][IPAHAL_NAT_IPV4] = { + ipa_nat_ipv4_entry_size_v_3_0, + ipa_nat_ipv4_is_entry_zeroed_v_3_0, + ipa_nat_ipv4_is_entry_valid_v_3_0, + ipa_nat_ipv4_stringify_entry_v_3_0 + }, + [IPA_HW_v3_0][IPAHAL_NAT_IPV4_INDEX] = { + ipa_nat_ipv4_index_entry_size_v_3_0, + ipa_nat_ipv4_is_index_entry_zeroed_v_3_0, + ipa_nat_ipv4_is_index_entry_valid_v_3_0, + ipa_nat_ipv4_index_stringify_entry_v_3_0 + }, + + /* IPAv4 */ + [IPA_HW_v4_0][IPAHAL_NAT_IPV4] = { + ipa_nat_ipv4_entry_size_v_3_0, + ipa_nat_ipv4_is_entry_zeroed_v_3_0, + ipa_nat_ipv4_is_entry_valid_v_3_0, + ipa_nat_ipv4_stringify_entry_v_4_0 + }, + [IPA_HW_v4_0][IPAHAL_NAT_IPV4_PDN] = { + ipa_nat_ipv4_pdn_entry_size_v_4_0, + ipa_nat_ipv4_is_pdn_entry_zeroed_v_4_0, + ipa_nat_ipv4_is_pdn_entry_valid_v_4_0, + ipa_nat_ipv4_pdn_stringify_entry_v_4_0, + ipa_nat_ipv4_pdn_construct_entry_v_4_0, + ipa_nat_ipv4_pdn_parse_entry_v_4_0 + }, + [IPA_HW_v4_0][IPAHAL_NAT_IPV6CT] = { + ipa_nat_ipv6ct_entry_size_v_4_0, + ipa_nat_ipv6ct_is_entry_zeroed_v_4_0, + ipa_nat_ipv6ct_is_entry_valid_v_4_0, + ipa_nat_ipv6ct_stringify_entry_v_4_0 + }, + + /* IPAv4.5 */ + [IPA_HW_v4_5][IPAHAL_NAT_IPV4] = { + ipa_nat_ipv4_entry_size_v_3_0, + ipa_nat_ipv4_is_entry_zeroed_v_3_0, + ipa_nat_ipv4_is_entry_valid_v_3_0, + ipa_nat_ipv4_stringify_entry_v_4_5 + }, + [IPA_HW_v4_5][IPAHAL_NAT_IPV6CT] = { + ipa_nat_ipv6ct_entry_size_v_4_0, + ipa_nat_ipv6ct_is_entry_zeroed_v_4_0, + ipa_nat_ipv6ct_is_entry_valid_v_4_0, + ipa_nat_ipv6ct_stringify_entry_v_4_5 + } +}; + +static void ipahal_nat_check_obj(struct ipahal_nat_obj *obj, + int nat_type, int ver) +{ + WARN(obj->entry_size == NULL, "%s missing entry_size for version %d\n", + ipahal_nat_type_str(nat_type), ver); + WARN(obj->is_entry_zeroed == NULL, + "%s missing is_entry_zeroed for version %d\n", + ipahal_nat_type_str(nat_type), ver); + WARN(obj->stringify_entry == NULL, + "%s missing stringify_entry for version %d\n", + ipahal_nat_type_str(nat_type), ver); +} + +/* + * ipahal_nat_init() - Build the NAT information table + * See ipahal_nat_objs[][] comments + */ +int ipahal_nat_init(enum ipa_hw_type ipa_hw_type) +{ + int i; + int j; + struct ipahal_nat_obj zero_obj, *next_obj; + + IPAHAL_DBG("Entry - HW_TYPE=%d\n", ipa_hw_type); + + memset(&zero_obj, 0, sizeof(zero_obj)); + + if ((ipa_hw_type < 0) || (ipa_hw_type >= IPA_HW_MAX)) { + IPAHAL_ERR("invalid IPA HW type (%d)\n", ipa_hw_type); + return -EINVAL; + } + + for (i = IPA_HW_v3_0 ; i < ipa_hw_type ; ++i) { + for (j = 0; j < IPA_NAT_MAX; ++j) { + next_obj = &ipahal_nat_objs[i + 1][j]; + if (!memcmp(next_obj, &zero_obj, sizeof(*next_obj))) { + memcpy(next_obj, &ipahal_nat_objs[i][j], + sizeof(*next_obj)); + } else { + ipahal_nat_check_obj(next_obj, j, i + 1); + } + } + } + + return 0; +} + +const char *ipahal_nat_type_str(enum ipahal_nat_type nat_type) +{ + if (nat_type < 0 || nat_type >= IPA_NAT_MAX) { + IPAHAL_ERR("requested NAT type %d is invalid\n", nat_type); + return "Invalid NAT type"; + } + + return ipahal_nat_type_to_str[nat_type]; +} + +int ipahal_nat_entry_size(enum ipahal_nat_type nat_type, size_t *entry_size) +{ + if (WARN(entry_size == NULL, "entry_size is NULL\n")) + return -EINVAL; + if (WARN(nat_type < 0 || nat_type >= IPA_NAT_MAX, + "requested NAT type %d is invalid\n", nat_type)) + return -EINVAL; + + IPAHAL_DBG("Get the entry size for NAT type=%s\n", + ipahal_nat_type_str(nat_type)); + + *entry_size = + ipahal_nat_objs[ipahal_ctx->hw_type][nat_type].entry_size(); + + IPAHAL_DBG("The entry size is %zu\n", *entry_size); + + return 0; +} + +int ipahal_nat_is_entry_zeroed(enum ipahal_nat_type nat_type, void *entry, + bool *entry_zeroed) +{ + struct ipahal_nat_obj *nat_ptr; + + if (WARN(entry == NULL || entry_zeroed == NULL, + "NULL pointer received\n")) + return -EINVAL; + if (WARN(nat_type < 0 || nat_type >= IPA_NAT_MAX, + "requested NAT type %d is invalid\n", nat_type)) + return -EINVAL; + + IPAHAL_DBG_LOW("Determine whether the entry is zeroed for NAT type=%s\n", + ipahal_nat_type_str(nat_type)); + + nat_ptr = + &ipahal_nat_objs[ipahal_ctx->hw_type][nat_type]; + + *entry_zeroed = nat_ptr->is_entry_zeroed(entry); + + IPAHAL_DBG_LOW("The entry is %szeroed\n", (*entry_zeroed) ? "" : "not "); + + return 0; +} + +int ipahal_nat_is_entry_valid(enum ipahal_nat_type nat_type, void *entry, + bool *entry_valid) +{ + struct ipahal_nat_obj *nat_obj; + + if (WARN(entry == NULL || entry_valid == NULL, + "NULL pointer received\n")) + return -EINVAL; + if (WARN(nat_type < 0 || nat_type >= IPA_NAT_MAX, + "requested NAT type %d is invalid\n", nat_type)) + return -EINVAL; + + IPAHAL_DBG("Determine whether the entry is valid for NAT type=%s\n", + ipahal_nat_type_str(nat_type)); + nat_obj = &ipahal_nat_objs[ipahal_ctx->hw_type][nat_type]; + *entry_valid = nat_obj->is_entry_valid(entry); + IPAHAL_DBG("The entry is %svalid\n", (*entry_valid) ? "" : "not "); + + return 0; +} + +int ipahal_nat_stringify_entry(enum ipahal_nat_type nat_type, void *entry, + char *buff, size_t buff_size) +{ + int result; + struct ipahal_nat_obj *nat_obj_ptr; + + if (WARN(entry == NULL || buff == NULL, "NULL pointer received\n")) + return -EINVAL; + if (WARN(!buff_size, "The output buff size is zero\n")) + return -EINVAL; + if (WARN(nat_type < 0 || nat_type >= IPA_NAT_MAX, + "requested NAT type %d is invalid\n", nat_type)) + return -EINVAL; + + nat_obj_ptr = + &ipahal_nat_objs[ipahal_ctx->hw_type][nat_type]; + + IPAHAL_DBG("Create the string for the entry of NAT type=%s\n", + ipahal_nat_type_str(nat_type)); + + result = nat_obj_ptr->stringify_entry(entry, buff, buff_size); + + IPAHAL_DBG("The string successfully created with length %d\n", + result); + + return result; +} + +int ipahal_nat_construct_entry(enum ipahal_nat_type nat_type, + const void *fields, + void *address) +{ + struct ipahal_nat_obj *nat_obj_ptr; + + if (WARN(address == NULL || fields == NULL, "NULL pointer received\n")) + return -EINVAL; + if (WARN(nat_type < 0 || nat_type >= IPA_NAT_MAX, + "requested NAT type %d is invalid\n", nat_type)) + return -EINVAL; + + IPAHAL_DBG("Create %s entry using given fields\n", + ipahal_nat_type_str(nat_type)); + + nat_obj_ptr = + &ipahal_nat_objs[ipahal_ctx->hw_type][nat_type]; + + nat_obj_ptr->construct_entry(fields, address); + + return 0; +} + +int ipahal_nat_parse_entry(enum ipahal_nat_type nat_type, void *fields, + const void *address) +{ + struct ipahal_nat_obj *nat_obj_ptr; + + if (WARN(address == NULL || fields == NULL, "NULL pointer received\n")) + return -EINVAL; + if (WARN(nat_type < 0 || nat_type >= IPA_NAT_MAX, + "requested NAT type %d is invalid\n", nat_type)) + return -EINVAL; + + IPAHAL_DBG("Get the parsed values for NAT type=%s\n", + ipahal_nat_type_str(nat_type)); + + nat_obj_ptr = + &ipahal_nat_objs[ipahal_ctx->hw_type][nat_type]; + + nat_obj_ptr->parse_entry(fields, address); + + return 0; +} diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_nat.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_nat.h new file mode 100644 index 0000000000..edc9b0b834 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_nat.h @@ -0,0 +1,103 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _IPAHAL_NAT_H_ +#define _IPAHAL_NAT_H_ + +/* + * NAT types + * + * NOTE:: Any change to this enum, need to change to ipahal_nat_to_str + * array as well. + */ +enum ipahal_nat_type { + IPAHAL_NAT_IPV4, + IPAHAL_NAT_IPV4_INDEX, + IPAHAL_NAT_IPV4_PDN, + IPAHAL_NAT_IPV6CT, + IPA_NAT_MAX +}; + +/** + * struct ipahal_nat_pdn_entry - IPA PDN config table entry + * @public_ip: the PDN's public ip + * @src_metadata: the PDN's metadata to be replaced for source NAT + * @dst_metadata: the PDN's metadata to be replaced for destination NAT + */ +struct ipahal_nat_pdn_entry { + u32 public_ip; + u32 src_metadata; + u32 dst_metadata; +}; + +/* NAT Function APIs */ + +/* + * ipahal_nat_type_str() - returns string that represent the NAT type + * @nat_type: [in] NAT type + */ +const char *ipahal_nat_type_str(enum ipahal_nat_type nat_type); + +/* + * ipahal_nat_entry_size() - Gets the size of HW NAT entry + * @nat_type: [in] The type of the NAT entry + * @entry_size: [out] The size of the HW NAT entry + */ +int ipahal_nat_entry_size(enum ipahal_nat_type nat_type, size_t *entry_size); + +/* + * ipahal_nat_is_entry_zeroed() - Determines whether HW NAT entry is + * definitely zero + * @nat_type: [in] The type of the NAT entry + * @entry: [in] The NAT entry + * @entry_zeroed: [out] True if the received entry is definitely zero + */ +int ipahal_nat_is_entry_zeroed(enum ipahal_nat_type nat_type, void *entry, + bool *entry_zeroed); + +/* + * ipahal_nat_is_entry_valid() - Determines whether HW NAT entry is + * valid. + * Validity criterium depends on entry type. E.g. for NAT base table + * Entry need to be with valid protocol and enabled. + * @nat_type: [in] The type of the NAT entry + * @entry: [in] The NAT entry + * @entry_valid: [out] True if the received entry is valid + */ +int ipahal_nat_is_entry_valid(enum ipahal_nat_type nat_type, void *entry, + bool *entry_valid); + +/* + * ipahal_nat_stringify_entry() - Creates a string for HW NAT entry + * @nat_type: [in] The type of the NAT entry + * @entry: [in] The NAT entry + * @buff: [out] Output buffer for the result string + * @buff_size: [in] The size of the output buffer + * @return the number of characters written into buff not including + * the trailing '\0' + */ +int ipahal_nat_stringify_entry(enum ipahal_nat_type nat_type, void *entry, + char *buff, size_t buff_size); + +/* + * ipahal_nat_construct_entry() - Create NAT entry using the given fields + * @nat_type: [in] The type of the NAT entry + * @fields: [in] The fields need to be written in the entry + * @address: [in] The address of the memory need to be written + */ +int ipahal_nat_construct_entry(enum ipahal_nat_type nat_type, + void const *fields, + void *address); + +/* + * ipahal_nat_parse_entry() - Parse NAT entry to the given fields structure + * @nat_type: [in] The type of the NAT entry + * @fields: [in] The fields need to be parsed from the entry + * @address: [in] The address of the memory need to be parsed + */ +int ipahal_nat_parse_entry(enum ipahal_nat_type nat_type, void *fields, + const void *address); + +#endif /* _IPAHAL_NAT_H_ */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_nat_i.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_nat_i.h new file mode 100644 index 0000000000..553cc6e5f7 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_nat_i.h @@ -0,0 +1,183 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _IPAHAL_NAT_I_H_ +#define _IPAHAL_NAT_I_H_ + +#include + +/* ----------------------- IPv4 NAT Table Entry ------------------------- + * + * ----------------------------------------------------------------------- + * | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | + * ----------------------------------------------------------------------- + * | Target IP(4B) | Private IP(4B) | + * ----------------------------------------------------------------------- + * |Target Port(2B) |Private Port(2B)| Public Port(2B) | Next Index(2B) | + * ----------------------------------------------------------------------- + * |Proto| TimeStamp(3B) | Flags(2B) |IP check sum Diff| + * |(1B) | | | (2B) | + * ----------------------------------------------------------------------- + * |TCP/UDP checksum| PDN info(2B) | SW Specific Parameters(4B) | + * | diff (2B) |Info|Resv |index table entry| prev index | + * ----------------------------------------------------------------------- + */ +struct ipa_nat_hw_ipv4_entry { + /* An IP address can't be bit-field, because its address is used */ + u32 private_ip; + u32 target_ip; + + u32 next_index : 16; + u32 public_port : 16; + u32 private_port : 16; + u32 target_port : 16; + u32 ip_chksum : 16; + + /*--------------------------------------------------- + *IPA NAT Flag is interpreted as follows + *--------------------------------------------------- + *| EN |FIN/RST| S | IPv4 uC activation index | + *| [15] | [14] | [13] | [12:0] | + *--------------------------------------------------- + */ + u32 uc_activation_index: 13; + u32 s : 1; + u32 redirect : 1; + u32 enable : 1; + + u32 time_stamp : 24; + u32 protocol : 8; + + /*-------------------------------------------------- + *32 bit sw_spec_params is interpreted as follows + *------------------------------------ + *| 16 bits | 16 bits | + *------------------------------------ + *| index table | prev index | + *| entry | | + *------------------------------------ + */ + u32 prev_index : 16; + u32 indx_tbl_entry : 16; + + u32 rsvd2 : 11; //including next 3 reserved buts + + /*----------------------------------------- + *8 bit PDN info is interpreted as following + *----------------------------------------------------- + *| 4 bits | 1 bit | 3 bits | + *----------------------------------------------------- + *| PDN index | uC processing | Reserved | + *| [7:4] | [3] | [2:0] | + *----------------------------------------------------- + */ + u32 ucp : 1; /* IPA 4.0 and greater */ + u32 pdn_index : 4; /* IPA 4.0 and greater */ + + u32 tcp_udp_chksum : 16; +}; + +/*--- IPV4 NAT Index Table Entry -- + *--------------------------------- + *| 3 | 2 | 1 | 0 | + *--------------------------------- + *|next index(2B) |table entry(2B)| + *--------------------------------- + */ +struct ipa_nat_hw_indx_entry { + u16 tbl_entry; + u16 next_index; +}; + +/** + * struct ipa_nat_hw_pdn_entry - IPA PDN config table entry + * @public_ip: the PDN's public ip + * @src_metadata: the PDN's metadata to be replaced for source NAT + * @dst_metadata: the PDN's metadata to be replaced for destination NAT + * @resrvd: reserved field + * --------------------------------- + * | 3 | 2 | 1 | 0 | + * --------------------------------- + * | public_ip (4B) | + * --------------------------------- + * | src_metadata (4B) | + * --------------------------------- + * | dst_metadata (4B) | + * --------------------------------- + * | resrvd (4B) | + * --------------------------------- + */ +struct ipa_nat_hw_pdn_entry { + u32 public_ip; + u32 src_metadata; + u32 dst_metadata; + u32 resrvd; +}; + +/*------------------------- IPV6CT Table Entry ------------------------------ + *----------------------------------------------------------------------------- + *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | + *----------------------------------------------------------------------------- + *| Outbound Src IPv6 Address (8 LSB Bytes) | + *----------------------------------------------------------------------------- + *| Outbound Src IPv6 Address (8 MSB Bytes) | + *----------------------------------------------------------------------------- + *| Outbound Dest IPv6 Address (8 LSB Bytes) | + *----------------------------------------------------------------------------- + *| Outbound Dest IPv6 Address (8 MSB Bytes) | + *----------------------------------------------------------------------------- + *|Protocol| TimeStamp (3B) | Flags (2B) |Rsvd |S |uC ACT| + *| (1B) | |Enable|Redirect|Resv |[15:14]|13|[12:0]| + *----------------------------------------------------------------------------- + *|Reserved|Settings| Src Port(2B) | Dest Port (2B) | Next Index(2B) | + *| (1B) | (1B) | | | | + *----------------------------------------------------------------------------- + *| SW Specific Parameters(4B) | Reserved (4B) | + *| Prev Index (2B) |Reserved(2B)| | + *----------------------------------------------------------------------------- + *| Reserved (8B) | + *----------------------------------------------------------------------------- + * + * Settings + *----------------------------------------------- + *|IN Allowed|OUT Allowed|Reserved|uC processing| + *|[7:7] |[6:6] |[5:1] |[0:0] | + *----------------------------------------------- + */ +struct ipa_nat_hw_ipv6ct_entry { + /* An IP address can't be bit-field, because its address is used */ + u64 src_ipv6_lsb; + u64 src_ipv6_msb; + u64 dest_ipv6_lsb; + u64 dest_ipv6_msb; + + u64 uc_activation_index : 13; + u64 s : 1; + u64 rsvd1 : 16; + u64 redirect : 1; + u64 enable : 1; + + u64 time_stamp : 24; + u64 protocol : 8; + + u64 next_index : 16; + u64 dest_port : 16; + u64 src_port : 16; + u64 ucp : 1; + u64 rsvd2 : 5; + u64 out_allowed : 1; + u64 in_allowed : 1; + u64 rsvd3 : 8; + + u64 rsvd4 : 48; + u64 prev_index : 16; + + u64 rsvd5 : 64; +}; + +int ipahal_nat_init(enum ipa_hw_type ipa_hw_type); + +#endif /* _IPAHAL_NAT_I_H_ */ + diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.c new file mode 100644 index 0000000000..55094494cb --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.c @@ -0,0 +1,5838 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include "ipa.h" +#include +#include +#include "ipahal_i.h" +#include "ipahal_reg.h" +#include "ipahal_reg_i.h" + +#define IPA_MAX_MSG_LEN 4096 + +#define IPA_BIT_MAP_CELL_NUM(num) ((num) >> 5) +#define IPA_BIT_MAP_CELL_MSK(num) \ + (1 << (num - (IPA_BIT_MAP_CELL_NUM(num) << 5))) + +static const char *ipareg_name_to_str[IPA_REG_MAX] = { + __stringify(IPA_ROUTE), + __stringify(IPA_IRQ_STTS_EE_n), + __stringify(IPA_IRQ_EN_EE_n), + __stringify(IPA_IRQ_CLR_EE_n), + __stringify(IPA_SUSPEND_IRQ_INFO_EE_n), + __stringify(IPA_SUSPEND_IRQ_EN_EE_n), + __stringify(IPA_SUSPEND_IRQ_CLR_EE_n), + __stringify(IPA_HOLB_DROP_IRQ_INFO_EE_n), + __stringify(IPA_HOLB_DROP_IRQ_EN_EE_n), + __stringify(IPA_HOLB_DROP_IRQ_CLR_EE_n), + __stringify(IPA_BCR), + __stringify(IPA_ENABLED_PIPES), + __stringify(IPA_VERSION), + __stringify(IPA_TAG_TIMER), + __stringify(IPA_NAT_TIMER), + __stringify(IPA_COMP_HW_VERSION), + __stringify(IPA_COMP_CFG), + __stringify(IPA_STATE_TX_WRAPPER), + __stringify(IPA_STATE_TX1), + __stringify(IPA_STATE_FETCHER), + __stringify(IPA_STATE_FETCHER_MASK), + __stringify(IPA_STATE_FETCHER_MASK_0), + __stringify(IPA_STATE_FETCHER_MASK_1), + __stringify(IPA_STATE_DFETCHER), + __stringify(IPA_STATE_ACL), + __stringify(IPA_STATE), + __stringify(IPA_STATE_RX_ACTIVE), + __stringify(IPA_STATE_TX0), + __stringify(IPA_STATE_TSP), + __stringify(IPA_STATE_AGGR_ACTIVE), + __stringify(IPA_COUNTER_CFG), + __stringify(IPA_STATE_GSI_TLV), + __stringify(IPA_STATE_GSI_AOS), + __stringify(IPA_STATE_GSI_IF), + __stringify(IPA_STATE_GSI_SKIP), + __stringify(IPA_STATE_GSI_IF_CONS), + __stringify(IPA_STATE_DPL_FIFO), + __stringify(IPA_STATE_COAL_MASTER), + __stringify(IPA_GENERIC_RAM_ARBITER_PRIORITY), + __stringify(IPA_STATE_NLO_AGGR), + __stringify(IPA_STATE_COAL_MASTER_1), + __stringify(IPA_ENDP_INIT_HDR_n), + __stringify(IPA_ENDP_INIT_HDR_EXT_n), + __stringify(IPA_ENDP_INIT_AGGR_n), + __stringify(IPA_AGGR_FORCE_CLOSE), + __stringify(IPA_ENDP_INIT_ROUTE_n), + __stringify(IPA_ENDP_INIT_MODE_n), + __stringify(IPA_ENDP_INIT_NAT_n), + __stringify(IPA_ENDP_INIT_CONN_TRACK_n), + __stringify(IPA_ENDP_INIT_CTRL_n), + __stringify(IPA_ENDP_INIT_CTRL_SCND_n), + __stringify(IPA_ENDP_INIT_CTRL_STATUS_n), + __stringify(IPA_ENDP_INIT_HOL_BLOCK_EN_n), + __stringify(IPA_ENDP_INIT_HOL_BLOCK_TIMER_n), + __stringify(IPA_ENDP_INIT_DEAGGR_n), + __stringify(IPA_ENDP_INIT_SEQ_n), + __stringify(IPA_DEBUG_CNT_REG_n), + __stringify(IPA_ENDP_INIT_CFG_n), + __stringify(IPA_IRQ_EE_UC_n), + __stringify(IPA_ENDP_INIT_HDR_METADATA_MASK_n), + __stringify(IPA_ENDP_INIT_HDR_METADATA_n), + __stringify(IPA_ENDP_INIT_PROD_CFG_n), + __stringify(IPA_ENDP_INIT_RSRC_GRP_n), + __stringify(IPA_SHARED_MEM_SIZE), + __stringify(IPA_SW_AREA_RAM_DIRECT_ACCESS_n), + __stringify(IPA_DEBUG_CNT_CTRL_n), + __stringify(IPA_UC_MAILBOX_m_n), + __stringify(IPA_FILT_ROUT_HASH_FLUSH), + __stringify(IPA_FILT_ROUT_HASH_EN), + __stringify(IPA_SINGLE_NDP_MODE), + __stringify(IPA_QCNCM), + __stringify(IPA_SYS_PKT_PROC_CNTXT_BASE), + __stringify(IPA_LOCAL_PKT_PROC_CNTXT_BASE), + __stringify(IPA_ENDP_STATUS_n), + __stringify(IPA_ENDP_YELLOW_RED_MARKER_CFG_n), + __stringify(IPA_ENDP_FILTER_ROUTER_HSH_CFG_n), + __stringify(IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n), + __stringify(IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n), + __stringify(IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n), + __stringify(IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n), + __stringify(IPA_DST_RSRC_GRP_01_RSRC_TYPE_n), + __stringify(IPA_DST_RSRC_GRP_23_RSRC_TYPE_n), + __stringify(IPA_DST_RSRC_GRP_45_RSRC_TYPE_n), + __stringify(IPA_DST_RSRC_GRP_67_RSRC_TYPE_n), + __stringify(IPA_RSRC_GRP_CFG), + __stringify(IPA_RSRC_GRP_CFG_EXT), + __stringify(IPA_RX_HPS_CLIENTS_MIN_DEPTH_0), + __stringify(IPA_RX_HPS_CLIENTS_MIN_DEPTH_1), + __stringify(IPA_RX_HPS_CLIENTS_MAX_DEPTH_0), + __stringify(IPA_RX_HPS_CLIENTS_MAX_DEPTH_1), + __stringify(IPA_HPS_FTCH_ARB_QUEUE_WEIGHT), + __stringify(IPA_QSB_MAX_WRITES), + __stringify(IPA_QSB_MAX_READS), + __stringify(IPA_TX_CFG), + __stringify(IPA_IDLE_INDICATION_CFG), + __stringify(IPA_DPS_SEQUENCER_FIRST), + __stringify(IPA_DPS_SEQUENCER_LAST), + __stringify(IPA_HPS_SEQUENCER_FIRST), + __stringify(IPA_HPS_SEQUENCER_LAST), + __stringify(IPA_CLKON_CFG), + __stringify(IPA_QTIME_TIMESTAMP_CFG), + __stringify(IPA_TIMERS_PULSE_GRAN_CFG), + __stringify(IPA_TIMERS_XO_CLK_DIV_CFG), + __stringify(IPA_STAT_QUOTA_BASE_n), + __stringify(IPA_STAT_QUOTA_MASK_n), + __stringify(IPA_STAT_TETHERING_BASE_n), + __stringify(IPA_STAT_TETHERING_MASK_n), + __stringify(IPA_STAT_FILTER_IPV4_BASE), + __stringify(IPA_STAT_FILTER_IPV6_BASE), + __stringify(IPA_STAT_ROUTER_IPV4_BASE), + __stringify(IPA_STAT_ROUTER_IPV6_BASE), + __stringify(IPA_STAT_FILTER_IPV4_START_ID), + __stringify(IPA_STAT_FILTER_IPV6_START_ID), + __stringify(IPA_STAT_ROUTER_IPV4_START_ID), + __stringify(IPA_STAT_ROUTER_IPV6_START_ID), + __stringify(IPA_STAT_FILTER_IPV4_END_ID), + __stringify(IPA_STAT_FILTER_IPV6_END_ID), + __stringify(IPA_STAT_ROUTER_IPV4_END_ID), + __stringify(IPA_STAT_ROUTER_IPV6_END_ID), + __stringify(IPA_STAT_DROP_CNT_BASE_n), + __stringify(IPA_STAT_DROP_CNT_MASK_n), + __stringify(IPA_SNOC_FEC_EE_n), + __stringify(IPA_FEC_ADDR_EE_n), + __stringify(IPA_FEC_ADDR_MSB_EE_n), + __stringify(IPA_FEC_ATTR_EE_n), + __stringify(IPA_ENDP_GSI_CFG1_n), + __stringify(IPA_ENDP_GSI_CFG_AOS_n), + __stringify(IPA_ENDP_GSI_CFG_TLV_n), + __stringify(IPA_COAL_EVICT_LRU), + __stringify(IPA_COAL_QMAP_CFG), + __stringify(IPA_FLAVOR_0), + __stringify(IPA_FLAVOR_9), + __stringify(IPA_STATE_AGGR_ACTIVE_n), + __stringify(IPA_AGGR_FORCE_CLOSE_n), + __stringify(IPA_STAT_QUOTA_MASK_EE_n_REG_k), + __stringify(IPA_SUSPEND_IRQ_INFO_EE_n_REG_k), + __stringify(IPA_SUSPEND_IRQ_CLR_EE_n_REG_k), + __stringify(IPA_SUSPEND_IRQ_EN_EE_n_REG_k), + __stringify(IPA_STAT_TETHERING_MASK_EE_n_REG_k), + __stringify(IPA_STAT_DROP_CNT_MASK_EE_n_REG_k), + __stringify(IPA_FILT_ROUT_CACHE_FLUSH), + __stringify(IPA_FILTER_CACHE_CFG_n), + __stringify(IPA_ROUTER_CACHE_CFG_n), + __stringify(IPA_NAT_UC_EXTERNAL_CFG), + __stringify(IPA_NAT_UC_LOCAL_CFG), + __stringify(IPA_NAT_UC_SHARED_CFG), + __stringify(IPA_CONN_TRACK_UC_EXTERNAL_CFG), + __stringify(IPA_CONN_TRACK_UC_LOCAL_CFG), + __stringify(IPA_CONN_TRACK_UC_SHARED_CFG), + __stringify(IPA_ULSO_CFG_IP_ID_MIN_VALUE_n), + __stringify(IPA_ULSO_CFG_IP_ID_MAX_VALUE_n), + __stringify(IPA_ENDP_INIT_ULSO_CFG_n), + __stringify(IPA_TSP_QM_EXTERNAL_BADDR_LSB), + __stringify(IPA_TSP_QM_EXTERNAL_BADDR_MSB), + __stringify(IPA_TSP_QM_EXTERNAL_SIZE), + __stringify(IPA_TSP_INGRESS_POLICING_CFG), + __stringify(IPA_TSP_EGRESS_POLICING_CFG), + __stringify(IPA_STAT_TSP_DROP_BASE), + __stringify(IPA_STATE_QMNGR_QUEUE_NONEMPTY), + __stringify(IPA_RAM_INGRESS_POLICER_DB_BASE_ADDR), + __stringify(IPA_RAM_EGRESS_SHAPING_PROD_DB_BASE_ADDR), + __stringify(IPA_RAM_EGRESS_SHAPING_TC_DB_BASE_ADDR), + __stringify(IPA_COAL_MASTER_CFG), + __stringify(IPA_IPV4_NAT_EXC_SUPPRESS_ROUT_TABLE_INDX), + __stringify(IPA_IPV6_CONN_TRACK_EXC_SUPPRESS_ROUT_TABLE_INDX), +}; + +static void ipareg_construct_dummy(enum ipahal_reg_name reg, + const void *fields, u32 *val) +{ + IPAHAL_ERR("No construct function for %s\n", + ipahal_reg_name_str(reg)); + WARN(1, "invalid register operation"); +} + +static void ipareg_parse_dummy(enum ipahal_reg_name reg, + void *fields, u32 val) +{ + IPAHAL_ERR("No parse function for %s\n", + ipahal_reg_name_str(reg)); + WARN(1, "invalid register operation"); +} + +static void ipareg_construct_rx_hps_clients_depth1( + enum ipahal_reg_name reg, const void *fields, u32 *val) +{ + struct ipahal_reg_rx_hps_clients *clients = + (struct ipahal_reg_rx_hps_clients *)fields; + + IPA_SETFIELD_IN_REG(*val, clients->client_minmax[0], + IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_X_CLIENT_n_SHFT(0), + IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_X_CLIENT_n_BMSK(0)); + + IPA_SETFIELD_IN_REG(*val, clients->client_minmax[1], + IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_X_CLIENT_n_SHFT(1), + IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_X_CLIENT_n_BMSK(1)); +} + +static void ipareg_construct_rx_hps_clients_depth0( + enum ipahal_reg_name reg, const void *fields, u32 *val) +{ + struct ipahal_reg_rx_hps_clients *clients = + (struct ipahal_reg_rx_hps_clients *)fields; + + IPA_SETFIELD_IN_REG(*val, clients->client_minmax[0], + IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_X_CLIENT_n_SHFT(0), + IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_X_CLIENT_n_BMSK(0)); + + IPA_SETFIELD_IN_REG(*val, clients->client_minmax[1], + IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_X_CLIENT_n_SHFT(1), + IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_X_CLIENT_n_BMSK(1)); + + IPA_SETFIELD_IN_REG(*val, clients->client_minmax[2], + IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_X_CLIENT_n_SHFT(2), + IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_X_CLIENT_n_BMSK(2)); + + IPA_SETFIELD_IN_REG(*val, clients->client_minmax[3], + IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_X_CLIENT_n_SHFT(3), + IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_X_CLIENT_n_BMSK(3)); +} + +static void ipareg_construct_rx_hps_clients_depth0_v3_5( + enum ipahal_reg_name reg, const void *fields, u32 *val) +{ + struct ipahal_reg_rx_hps_clients *clients = + (struct ipahal_reg_rx_hps_clients *)fields; + + IPA_SETFIELD_IN_REG(*val, clients->client_minmax[0], + IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_X_CLIENT_n_SHFT(0), + IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_X_CLIENT_n_BMSK_V3_5(0)); + + IPA_SETFIELD_IN_REG(*val, clients->client_minmax[1], + IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_X_CLIENT_n_SHFT(1), + IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_X_CLIENT_n_BMSK_V3_5(1)); + + IPA_SETFIELD_IN_REG(*val, clients->client_minmax[2], + IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_X_CLIENT_n_SHFT(2), + IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_X_CLIENT_n_BMSK_V3_5(2)); + + IPA_SETFIELD_IN_REG(*val, clients->client_minmax[3], + IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_X_CLIENT_n_SHFT(3), + IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_X_CLIENT_n_BMSK_V3_5(3)); +} + +static void ipareg_construct_rx_hps_clients_depth0_v4_5( + enum ipahal_reg_name reg, const void *fields, u32 *val) +{ + struct ipahal_reg_rx_hps_clients *clients = + (struct ipahal_reg_rx_hps_clients *)fields; + + IPA_SETFIELD_IN_REG(*val, clients->client_minmax[0], + IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_0_CLIENT_0_SHFT_v4_5, + IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_0_CLIENT_0_BMSK_v4_5); + + IPA_SETFIELD_IN_REG(*val, clients->client_minmax[1], + IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_0_CLIENT_1_SHFT_v4_5, + IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_0_CLIENT_1_BMSK_v4_5); + + IPA_SETFIELD_IN_REG(*val, clients->client_minmax[2], + IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_0_CLIENT_2_SHFT_v4_5, + IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_0_CLIENT_2_BMSK_v4_5); + + IPA_SETFIELD_IN_REG(*val, clients->client_minmax[3], + IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_0_CLIENT_3_SHFT_v4_5, + IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_0_CLIENT_3_BMSK_v4_5); + + IPA_SETFIELD_IN_REG(*val, clients->client_minmax[4], + IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_0_CLIENT_4_SHFT_v4_5, + IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_0_CLIENT_4_BMSK_v4_5); +} + +static void ipareg_construct_rsrg_grp_xy( + enum ipahal_reg_name reg, const void *fields, u32 *val) +{ + struct ipahal_reg_rsrc_grp_xy_cfg *grp = + (struct ipahal_reg_rsrc_grp_xy_cfg *)fields; + + IPA_SETFIELD_IN_REG(*val, grp->x_min, + IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MIN_LIM_SHFT, + IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MIN_LIM_BMSK); + IPA_SETFIELD_IN_REG(*val, grp->x_max, + IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MAX_LIM_SHFT, + IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MAX_LIM_BMSK); + IPA_SETFIELD_IN_REG(*val, grp->y_min, + IPA_RSRC_GRP_XY_RSRC_TYPE_n_Y_MIN_LIM_SHFT, + IPA_RSRC_GRP_XY_RSRC_TYPE_n_Y_MIN_LIM_BMSK); + IPA_SETFIELD_IN_REG(*val, grp->y_max, + IPA_RSRC_GRP_XY_RSRC_TYPE_n_Y_MAX_LIM_SHFT, + IPA_RSRC_GRP_XY_RSRC_TYPE_n_Y_MAX_LIM_BMSK); +} + +static void ipareg_construct_rsrg_grp_xy_v3_5( + enum ipahal_reg_name reg, const void *fields, u32 *val) +{ + struct ipahal_reg_rsrc_grp_xy_cfg *grp = + (struct ipahal_reg_rsrc_grp_xy_cfg *)fields; + + IPA_SETFIELD_IN_REG(*val, grp->x_min, + IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MIN_LIM_SHFT_V3_5, + IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MIN_LIM_BMSK_V3_5); + IPA_SETFIELD_IN_REG(*val, grp->x_max, + IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MAX_LIM_SHFT_V3_5, + IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MAX_LIM_BMSK_V3_5); + + /* DST_23 register has only X fields at ipa V3_5 */ + if (reg == IPA_DST_RSRC_GRP_23_RSRC_TYPE_n) + return; + + IPA_SETFIELD_IN_REG(*val, grp->y_min, + IPA_RSRC_GRP_XY_RSRC_TYPE_n_Y_MIN_LIM_SHFT_V3_5, + IPA_RSRC_GRP_XY_RSRC_TYPE_n_Y_MIN_LIM_BMSK_V3_5); + IPA_SETFIELD_IN_REG(*val, grp->y_max, + IPA_RSRC_GRP_XY_RSRC_TYPE_n_Y_MAX_LIM_SHFT_V3_5, + IPA_RSRC_GRP_XY_RSRC_TYPE_n_Y_MAX_LIM_BMSK_V3_5); +} + +static void ipareg_construct_rsrg_grp_xy_v4_5( + enum ipahal_reg_name reg, const void *fields, u32 *val) +{ + struct ipahal_reg_rsrc_grp_xy_cfg *grp = + (struct ipahal_reg_rsrc_grp_xy_cfg *)fields; + + IPA_SETFIELD_IN_REG(*val, grp->x_min, + IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MIN_LIM_SHFT_V3_5, + IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MIN_LIM_BMSK_V3_5); + IPA_SETFIELD_IN_REG(*val, grp->x_max, + IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MAX_LIM_SHFT_V3_5, + IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MAX_LIM_BMSK_V3_5); + + /* SRC_45 and DST_45 register has only X fields at ipa V4_5 */ + if (reg == IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n || + reg == IPA_DST_RSRC_GRP_45_RSRC_TYPE_n) + return; + + IPA_SETFIELD_IN_REG(*val, grp->y_min, + IPA_RSRC_GRP_XY_RSRC_TYPE_n_Y_MIN_LIM_SHFT_V3_5, + IPA_RSRC_GRP_XY_RSRC_TYPE_n_Y_MIN_LIM_BMSK_V3_5); + IPA_SETFIELD_IN_REG(*val, grp->y_max, + IPA_RSRC_GRP_XY_RSRC_TYPE_n_Y_MAX_LIM_SHFT_V3_5, + IPA_RSRC_GRP_XY_RSRC_TYPE_n_Y_MAX_LIM_BMSK_V3_5); +} + +static void ipareg_construct_rsrg_grp_xy_v5_0( + enum ipahal_reg_name reg, const void *fields, u32 *val) +{ + struct ipahal_reg_rsrc_grp_xy_cfg *grp = + (struct ipahal_reg_rsrc_grp_xy_cfg *)fields; + + IPA_SETFIELD_IN_REG(*val, grp->x_min, + IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MIN_LIM_SHFT_V3_5, + IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MIN_LIM_BMSK_V3_5); + IPA_SETFIELD_IN_REG(*val, grp->x_max, + IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MAX_LIM_SHFT_V3_5, + IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MAX_LIM_BMSK_V3_5); + + IPA_SETFIELD_IN_REG(*val, grp->y_min, + IPA_RSRC_GRP_XY_RSRC_TYPE_n_Y_MIN_LIM_SHFT_V3_5, + IPA_RSRC_GRP_XY_RSRC_TYPE_n_Y_MIN_LIM_BMSK_V3_5); + IPA_SETFIELD_IN_REG(*val, grp->y_max, + IPA_RSRC_GRP_XY_RSRC_TYPE_n_Y_MAX_LIM_SHFT_V3_5, + IPA_RSRC_GRP_XY_RSRC_TYPE_n_Y_MAX_LIM_BMSK_V3_5); +} + +static void ipareg_construct_rsrg_grp_cfg( + enum ipahal_reg_name reg, const void *fields, u32 *val) +{ + struct ipahal_reg_rsrc_grp_cfg *cfg = + (struct ipahal_reg_rsrc_grp_cfg *)fields; + + + IPA_SETFIELD_IN_REG(*val, cfg->src_grp_index, + IPA_RSRC_GRP_CFG_SRC_GRP_SPECIAL_INDEX_SHFT, + IPA_RSRC_GRP_CFG_SRC_GRP_SPECIAL_INDEX_BMSK); + IPA_SETFIELD_IN_REG(*val, cfg->src_grp_valid, + IPA_RSRC_GRP_CFG_SRC_GRP_SPECIAL_VALID_SHFT, + IPA_RSRC_GRP_CFG_SRC_GRP_SPECIAL_VALID_BMSK); + IPA_SETFIELD_IN_REG(*val, cfg->dst_pipe_index, + IPA_RSRC_GRP_CFG_DST_PIPE_SPECIAL_INDEX_SHFT, + IPA_RSRC_GRP_CFG_DST_PIPE_SPECIAL_INDEX_BMSK); + IPA_SETFIELD_IN_REG(*val, cfg->dst_pipe_valid, + IPA_RSRC_GRP_CFG_DST_PIPE_SPECIAL_VALID_SHFT, + IPA_RSRC_GRP_CFG_DST_PIPE_SPECIAL_VALID_BMSK); + IPA_SETFIELD_IN_REG(*val, cfg->dst_grp_index, + IPA_RSRC_GRP_CFG_DST_GRP_SPECIAL_INDEX_SHFT, + IPA_RSRC_GRP_CFG_DST_GRP_SPECIAL_INDEX_BMSK); + IPA_SETFIELD_IN_REG(*val, cfg->dst_grp_valid, + IPA_RSRC_GRP_CFG_DST_GRP_SPECIAL_VALID_SHFT, + IPA_RSRC_GRP_CFG_DST_GRP_SPECIAL_VALID_BMSK); +} + +static void ipareg_construct_rsrg_grp_cfg_ext( + enum ipahal_reg_name reg, const void *fields, u32 *val) +{ + struct ipahal_reg_rsrc_grp_cfg_ext *cfg = + (struct ipahal_reg_rsrc_grp_cfg_ext *)fields; + + IPA_SETFIELD_IN_REG(*val, cfg->index, + IPA_RSRC_GRP_CFG_EXT_SRC_GRP_2ND_PRIORITY_SPECIAL_INDEX_SHFT, + IPA_RSRC_GRP_CFG_EXT_SRC_GRP_2ND_PRIORITY_SPECIAL_INDEX_BMSK); + IPA_SETFIELD_IN_REG(*val, cfg->valid, + IPA_RSRC_GRP_CFG_EXT_SRC_GRP_2ND_PRIORITY_SPECIAL_VALID_SHFT, + IPA_RSRC_GRP_CFG_EXT_SRC_GRP_2ND_PRIORITY_SPECIAL_VALID_BMSK); +} + +static void ipareg_construct_hash_cfg_n( + enum ipahal_reg_name reg, const void *fields, u32 *val) +{ + struct ipahal_reg_fltrt_hash_tuple *tuple = + (struct ipahal_reg_fltrt_hash_tuple *)fields; + + IPA_SETFIELD_IN_REG(*val, tuple->flt.src_id, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_SRC_ID_SHFT, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_SRC_ID_BMSK); + IPA_SETFIELD_IN_REG(*val, tuple->flt.src_ip_addr, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_SRC_IP_SHFT, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_SRC_IP_BMSK); + IPA_SETFIELD_IN_REG(*val, tuple->flt.dst_ip_addr, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_DST_IP_SHFT, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_DST_IP_BMSK); + IPA_SETFIELD_IN_REG(*val, tuple->flt.src_port, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_SRC_PORT_SHFT, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_SRC_PORT_BMSK); + IPA_SETFIELD_IN_REG(*val, tuple->flt.dst_port, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_DST_PORT_SHFT, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_DST_PORT_BMSK); + IPA_SETFIELD_IN_REG(*val, tuple->flt.protocol, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_PROTOCOL_SHFT, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_PROTOCOL_BMSK); + IPA_SETFIELD_IN_REG(*val, tuple->flt.meta_data, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_METADATA_SHFT, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_METADATA_BMSK); + IPA_SETFIELD_IN_REG(*val, tuple->undefined1, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_UNDEFINED1_SHFT, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_UNDEFINED1_BMSK); + IPA_SETFIELD_IN_REG(*val, tuple->rt.src_id, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_SRC_ID_SHFT, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_SRC_ID_BMSK); + IPA_SETFIELD_IN_REG(*val, tuple->rt.src_ip_addr, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_SRC_IP_SHFT, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_SRC_IP_BMSK); + IPA_SETFIELD_IN_REG(*val, tuple->rt.dst_ip_addr, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_DST_IP_SHFT, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_DST_IP_BMSK); + IPA_SETFIELD_IN_REG(*val, tuple->rt.src_port, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_SRC_PORT_SHFT, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_SRC_PORT_BMSK); + IPA_SETFIELD_IN_REG(*val, tuple->rt.dst_port, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_DST_PORT_SHFT, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_DST_PORT_BMSK); + IPA_SETFIELD_IN_REG(*val, tuple->rt.protocol, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_PROTOCOL_SHFT, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_PROTOCOL_BMSK); + IPA_SETFIELD_IN_REG(*val, tuple->rt.meta_data, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_METADATA_SHFT, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_METADATA_BMSK); + IPA_SETFIELD_IN_REG(*val, tuple->undefined2, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_UNDEFINED2_SHFT, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_UNDEFINED2_BMSK); +} + +static void ipareg_construct_cache_cfg_n( + enum ipahal_reg_name reg, const void *fields, u32 *val) +{ + struct ipahal_reg_fltrt_cache_tuple *tuple = + (struct ipahal_reg_fltrt_cache_tuple *)fields; + + IPA_SETFIELD_IN_REG(*val, tuple->tuple.src_id, + IPA_ENDP_FILTER_ROUTER_CACHE_CFG_n_CACHE_MSK_SRC_ID_SHFT, + IPA_ENDP_FILTER_ROUTER_CACHE_CFG_n_CACHE_MSK_SRC_ID_BMSK); + IPA_SETFIELD_IN_REG(*val, tuple->tuple.src_ip_addr, + IPA_ENDP_FILTER_ROUTER_CACHE_CFG_n_CACHE_MSK_SRC_IP_SHFT, + IPA_ENDP_FILTER_ROUTER_CACHE_CFG_n_CACHE_MSK_SRC_IP_BMSK); + IPA_SETFIELD_IN_REG(*val, tuple->tuple.dst_ip_addr, + IPA_ENDP_FILTER_ROUTER_CACHE_CFG_n_CACHE_MSK_DST_IP_SHFT, + IPA_ENDP_FILTER_ROUTER_CACHE_CFG_n_CACHE_MSK_DST_IP_BMSK); + IPA_SETFIELD_IN_REG(*val, tuple->tuple.src_port, + IPA_ENDP_FILTER_ROUTER_CACHE_CFG_n_CACHE_MSK_SRC_PORT_SHFT, + IPA_ENDP_FILTER_ROUTER_CACHE_CFG_n_CACHE_MSK_SRC_PORT_BMSK); + IPA_SETFIELD_IN_REG(*val, tuple->tuple.dst_port, + IPA_ENDP_FILTER_ROUTER_CACHE_CFG_n_CACHE_MSK_DST_PORT_SHFT, + IPA_ENDP_FILTER_ROUTER_CACHE_CFG_n_CACHE_MSK_DST_PORT_BMSK); + IPA_SETFIELD_IN_REG(*val, tuple->tuple.protocol, + IPA_ENDP_FILTER_ROUTER_CACHE_CFG_n_CACHE_MSK_PROTOCOL_SHFT, + IPA_ENDP_FILTER_ROUTER_CACHE_CFG_n_CACHE_MSK_PROTOCOL_BMSK); + IPA_SETFIELD_IN_REG(*val, tuple->tuple.meta_data, + IPA_ENDP_FILTER_ROUTER_CACHE_CFG_n_CACHE_MSK_METADATA_SHFT, + IPA_ENDP_FILTER_ROUTER_CACHE_CFG_n_CACHE_MSK_METADATA_BMSK); + IPA_SETFIELD_IN_REG(*val, tuple->undefined, + IPA_ENDP_FILTER_ROUTER_CACHE_CFG_n_UNDEFINED_SHFT, + IPA_ENDP_FILTER_ROUTER_CACHE_CFG_n_UNDEFINED_BMSK); +} +static void ipareg_parse_hash_cfg_n( + enum ipahal_reg_name reg, void *fields, u32 val) +{ + struct ipahal_reg_fltrt_hash_tuple *tuple = + (struct ipahal_reg_fltrt_hash_tuple *)fields; + + tuple->flt.src_id = + IPA_GETFIELD_FROM_REG(val, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_SRC_ID_SHFT, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_SRC_ID_BMSK); + tuple->flt.src_ip_addr = + IPA_GETFIELD_FROM_REG(val, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_SRC_IP_SHFT, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_SRC_IP_BMSK); + tuple->flt.dst_ip_addr = + IPA_GETFIELD_FROM_REG(val, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_DST_IP_SHFT, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_DST_IP_BMSK); + tuple->flt.src_port = + IPA_GETFIELD_FROM_REG(val, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_SRC_PORT_SHFT, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_SRC_PORT_BMSK); + tuple->flt.dst_port = + IPA_GETFIELD_FROM_REG(val, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_DST_PORT_SHFT, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_DST_PORT_BMSK); + tuple->flt.protocol = + IPA_GETFIELD_FROM_REG(val, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_PROTOCOL_SHFT, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_PROTOCOL_BMSK); + tuple->flt.meta_data = + IPA_GETFIELD_FROM_REG(val, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_METADATA_SHFT, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_METADATA_BMSK); + tuple->undefined1 = + IPA_GETFIELD_FROM_REG(val, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_UNDEFINED1_SHFT, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_UNDEFINED1_BMSK); + tuple->rt.src_id = + IPA_GETFIELD_FROM_REG(val, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_SRC_ID_SHFT, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_SRC_ID_BMSK); + tuple->rt.src_ip_addr = + IPA_GETFIELD_FROM_REG(val, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_SRC_IP_SHFT, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_SRC_IP_BMSK); + tuple->rt.dst_ip_addr = + IPA_GETFIELD_FROM_REG(val, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_DST_IP_SHFT, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_DST_IP_BMSK); + tuple->rt.src_port = + IPA_GETFIELD_FROM_REG(val, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_SRC_PORT_SHFT, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_SRC_PORT_BMSK); + tuple->rt.dst_port = + IPA_GETFIELD_FROM_REG(val, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_DST_PORT_SHFT, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_DST_PORT_BMSK); + tuple->rt.protocol = + IPA_GETFIELD_FROM_REG(val, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_PROTOCOL_SHFT, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_PROTOCOL_BMSK); + tuple->rt.meta_data = + IPA_GETFIELD_FROM_REG(val, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_METADATA_SHFT, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_METADATA_BMSK); + tuple->undefined2 = + IPA_GETFIELD_FROM_REG(val, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_UNDEFINED2_SHFT, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_UNDEFINED2_BMSK); +} + +static void ipareg_parse_cache_cfg_n( + enum ipahal_reg_name reg, void *fields, u32 val) +{ + struct ipahal_reg_fltrt_cache_tuple *tuple = + (struct ipahal_reg_fltrt_cache_tuple *)fields; + + tuple->tuple.src_id = + IPA_GETFIELD_FROM_REG(val, + IPA_ENDP_FILTER_ROUTER_CACHE_CFG_n_CACHE_MSK_SRC_ID_SHFT, + IPA_ENDP_FILTER_ROUTER_CACHE_CFG_n_CACHE_MSK_SRC_ID_BMSK); + tuple->tuple.src_ip_addr = + IPA_GETFIELD_FROM_REG(val, + IPA_ENDP_FILTER_ROUTER_CACHE_CFG_n_CACHE_MSK_SRC_IP_SHFT, + IPA_ENDP_FILTER_ROUTER_CACHE_CFG_n_CACHE_MSK_SRC_IP_BMSK); + tuple->tuple.dst_ip_addr = + IPA_GETFIELD_FROM_REG(val, + IPA_ENDP_FILTER_ROUTER_CACHE_CFG_n_CACHE_MSK_DST_IP_SHFT, + IPA_ENDP_FILTER_ROUTER_CACHE_CFG_n_CACHE_MSK_DST_IP_BMSK); + tuple->tuple.src_port = + IPA_GETFIELD_FROM_REG(val, + IPA_ENDP_FILTER_ROUTER_CACHE_CFG_n_CACHE_MSK_SRC_PORT_SHFT, + IPA_ENDP_FILTER_ROUTER_CACHE_CFG_n_CACHE_MSK_SRC_PORT_BMSK); + tuple->tuple.dst_port = + IPA_GETFIELD_FROM_REG(val, + IPA_ENDP_FILTER_ROUTER_CACHE_CFG_n_CACHE_MSK_DST_PORT_SHFT, + IPA_ENDP_FILTER_ROUTER_CACHE_CFG_n_CACHE_MSK_DST_PORT_BMSK); + tuple->tuple.protocol = + IPA_GETFIELD_FROM_REG(val, + IPA_ENDP_FILTER_ROUTER_CACHE_CFG_n_CACHE_MSK_PROTOCOL_SHFT, + IPA_ENDP_FILTER_ROUTER_CACHE_CFG_n_CACHE_MSK_PROTOCOL_BMSK); + tuple->tuple.meta_data = + IPA_GETFIELD_FROM_REG(val, + IPA_ENDP_FILTER_ROUTER_CACHE_CFG_n_CACHE_MSK_METADATA_SHFT, + IPA_ENDP_FILTER_ROUTER_CACHE_CFG_n_CACHE_MSK_METADATA_BMSK); + tuple->undefined = + IPA_GETFIELD_FROM_REG(val, + IPA_ENDP_FILTER_ROUTER_CACHE_CFG_n_UNDEFINED_SHFT, + IPA_ENDP_FILTER_ROUTER_CACHE_CFG_n_UNDEFINED_BMSK); +} + +static void ipareg_construct_endp_status_n_common( + const struct ipahal_reg_ep_cfg_status *ep_status, u32 *val) +{ + IPA_SETFIELD_IN_REG(*val, ep_status->status_en, + IPA_ENDP_STATUS_n_STATUS_EN_SHFT, + IPA_ENDP_STATUS_n_STATUS_EN_BMSK); + + IPA_SETFIELD_IN_REG(*val, ep_status->status_ep, + IPA_ENDP_STATUS_n_STATUS_ENDP_SHFT, + IPA_ENDP_STATUS_n_STATUS_ENDP_BMSK); +} + +static void ipareg_construct_endp_status_n( + enum ipahal_reg_name reg, const void *fields, u32 *val) +{ + const struct ipahal_reg_ep_cfg_status *ep_status = + (const struct ipahal_reg_ep_cfg_status *)fields; + + ipareg_construct_endp_status_n_common(ep_status, val); + + IPA_SETFIELD_IN_REG(*val, ep_status->status_location, + IPA_ENDP_STATUS_n_STATUS_LOCATION_SHFT, + IPA_ENDP_STATUS_n_STATUS_LOCATION_BMSK); +} + +static void ipareg_construct_endp_status_n_v4_0( + enum ipahal_reg_name reg, const void *fields, u32 *val) +{ + struct ipahal_reg_ep_cfg_status *ep_status = + (struct ipahal_reg_ep_cfg_status *)fields; + + ipareg_construct_endp_status_n_common(ep_status, val); + + IPA_SETFIELD_IN_REG(*val, ep_status->status_location, + IPA_ENDP_STATUS_n_STATUS_LOCATION_SHFT, + IPA_ENDP_STATUS_n_STATUS_LOCATION_BMSK); + + IPA_SETFIELD_IN_REG(*val, ep_status->status_pkt_suppress, + IPA_ENDP_STATUS_n_STATUS_PKT_SUPPRESS_SHFT, + IPA_ENDP_STATUS_n_STATUS_PKT_SUPPRESS_BMSK); +} + +static void ipareg_construct_endp_status_n_v4_5( + enum ipahal_reg_name reg, const void *fields, u32 *val) +{ + struct ipahal_reg_ep_cfg_status *ep_status = + (struct ipahal_reg_ep_cfg_status *)fields; + + ipareg_construct_endp_status_n_common(ep_status, val); + + IPA_SETFIELD_IN_REG(*val, ep_status->status_pkt_suppress, + IPA_ENDP_STATUS_n_STATUS_PKT_SUPPRESS_SHFT, + IPA_ENDP_STATUS_n_STATUS_PKT_SUPPRESS_BMSK); +} + +static void ipareg_construct_endp_status_n_v5_0( + enum ipahal_reg_name reg, const void *fields, u32 *val) +{ + struct ipahal_reg_ep_cfg_status *ep_status = + (struct ipahal_reg_ep_cfg_status *)fields; + + IPA_SETFIELD_IN_REG(*val, ep_status->status_en, + IPA_ENDP_STATUS_n_STATUS_EN_SHFT, + IPA_ENDP_STATUS_n_STATUS_EN_BMSK); + + IPA_SETFIELD_IN_REG(*val, ep_status->status_ep, + IPA_ENDP_STATUS_n_STATUS_ENDP_SHFT_V5_0, + IPA_ENDP_STATUS_n_STATUS_ENDP_BMSK_V5_0); + + IPA_SETFIELD_IN_REG(*val, ep_status->status_pkt_suppress, + IPA_ENDP_STATUS_n_STATUS_PKT_SUPPRESS_SHFT, + IPA_ENDP_STATUS_n_STATUS_PKT_SUPPRESS_BMSK); +} + +static void ipareg_construct_clkon_cfg_common( + const struct ipahal_reg_clkon_cfg *clkon_cfg, u32 *val) +{ + IPA_SETFIELD_IN_REG(*val, !!clkon_cfg->open_global_2x_clk, + IPA_CLKON_CFG_OPEN_GLOBAL_2X_CLK_SHFT, + IPA_CLKON_CFG_OPEN_GLOBAL_2X_CLK_BMSK); + + IPA_SETFIELD_IN_REG(*val, !!clkon_cfg->open_global, + IPA_CLKON_CFG_OPEN_GLOBAL_SHFT, + IPA_CLKON_CFG_OPEN_GLOBAL_BMSK); + + IPA_SETFIELD_IN_REG(*val, !!clkon_cfg->open_gsi_if, + IPA_CLKON_CFG_OPEN_GSI_IF_SHFT, + IPA_CLKON_CFG_OPEN_GSI_IF_BMSK); + + IPA_SETFIELD_IN_REG(*val, !!clkon_cfg->open_weight_arb, + IPA_CLKON_CFG_OPEN_WEIGHT_ARB_SHFT, + IPA_CLKON_CFG_OPEN_WEIGHT_ARB_BMSK); + + IPA_SETFIELD_IN_REG(*val, !!clkon_cfg->open_qmb, + IPA_CLKON_CFG_OPEN_QMB_SHFT, + IPA_CLKON_CFG_OPEN_QMB_BMSK); + + IPA_SETFIELD_IN_REG(*val, !!clkon_cfg->open_ram_slaveway, + IPA_CLKON_CFG_OPEN_RAM_SLAVEWAY_SHFT, + IPA_CLKON_CFG_OPEN_RAM_SLAVEWAY_BMSK); + + IPA_SETFIELD_IN_REG(*val, !!clkon_cfg->open_aggr_wrapper, + IPA_CLKON_CFG_OPEN_AGGR_WRAPPER_SHFT, + IPA_CLKON_CFG_OPEN_AGGR_WRAPPER_BMSK); + + IPA_SETFIELD_IN_REG(*val, !!clkon_cfg->open_qsb2axi_cmdq_l, + IPA_CLKON_CFG_OPEN_QSB2AXI_CMDQ_L_SHFT, + IPA_CLKON_CFG_OPEN_QSB2AXI_CMDQ_L_BMSK); + + IPA_SETFIELD_IN_REG(*val, !!clkon_cfg->open_fnr, + IPA_CLKON_CFG_OPEN_FNR_SHFT, + IPA_CLKON_CFG_OPEN_FNR_BMSK); + + IPA_SETFIELD_IN_REG(*val, !!clkon_cfg->open_tx_1, + IPA_CLKON_CFG_OPEN_TX_1_SHFT, + IPA_CLKON_CFG_OPEN_TX_1_BMSK); + + IPA_SETFIELD_IN_REG(*val, !!clkon_cfg->open_tx_0, + IPA_CLKON_CFG_OPEN_TX_0_SHFT, + IPA_CLKON_CFG_OPEN_TX_0_BMSK); + + IPA_SETFIELD_IN_REG(*val, !!clkon_cfg->open_ntf_tx_cmdqs, + IPA_CLKON_CFG_OPEN_NTF_TX_CMDQS_SHFT, + IPA_CLKON_CFG_OPEN_NTF_TX_CMDQS_BMSK); + + IPA_SETFIELD_IN_REG(*val, !!clkon_cfg->open_h_dcph, + IPA_CLKON_CFG_OPEN_H_DCPH_SHFT, + IPA_CLKON_CFG_OPEN_H_DCPH_BMSK); + + IPA_SETFIELD_IN_REG(*val, !!clkon_cfg->open_d_dcph, + IPA_CLKON_CFG_OPEN_D_DCPH_SHFT, + IPA_CLKON_CFG_OPEN_D_DCPH_BMSK); + + IPA_SETFIELD_IN_REG(*val, !!clkon_cfg->open_ack_mngr, + IPA_CLKON_CFG_OPEN_ACK_MNGR_SHFT, + IPA_CLKON_CFG_OPEN_ACK_MNGR_BMSK); + + IPA_SETFIELD_IN_REG(*val, !!clkon_cfg->open_ctx_handler, + IPA_CLKON_CFG_OPEN_CTX_HANDLER_SHFT, + IPA_CLKON_CFG_OPEN_CTX_HANDLER_BMSK); + + IPA_SETFIELD_IN_REG(*val, !!clkon_cfg->open_rsrc_mngr, + IPA_CLKON_CFG_OPEN_RSRC_MNGR_SHFT, + IPA_CLKON_CFG_OPEN_RSRC_MNGR_BMSK); + + IPA_SETFIELD_IN_REG(*val, !!clkon_cfg->open_dps_tx_cmdqs, + IPA_CLKON_CFG_OPEN_DPS_TX_CMDQS_SHFT, + IPA_CLKON_CFG_OPEN_DPS_TX_CMDQS_BMSK); + + IPA_SETFIELD_IN_REG(*val, !!clkon_cfg->open_hps_dps_cmdqs, + IPA_CLKON_CFG_OPEN_HPS_DPS_CMDQS_SHFT, + IPA_CLKON_CFG_OPEN_HPS_DPS_CMDQS_BMSK); + + IPA_SETFIELD_IN_REG(*val, !!clkon_cfg->open_rx_hps_cmdqs, + IPA_CLKON_CFG_OPEN_RX_HPS_CMDQS_SHFT, + IPA_CLKON_CFG_OPEN_RX_HPS_CMDQS_BMSK); + + IPA_SETFIELD_IN_REG(*val, !!clkon_cfg->open_dps, + IPA_CLKON_CFG_OPEN_DPS_SHFT, + IPA_CLKON_CFG_OPEN_DPS_BMSK); + + IPA_SETFIELD_IN_REG(*val, !!clkon_cfg->open_hps, + IPA_CLKON_CFG_OPEN_HPS_SHFT, + IPA_CLKON_CFG_OPEN_HPS_BMSK); + + IPA_SETFIELD_IN_REG(*val, !!clkon_cfg->open_ftch_dps, + IPA_CLKON_CFG_OPEN_FTCH_DPS_SHFT, + IPA_CLKON_CFG_OPEN_FTCH_DPS_BMSK); + + IPA_SETFIELD_IN_REG(*val, !!clkon_cfg->open_ftch_hps, + IPA_CLKON_CFG_OPEN_FTCH_HPS_SHFT, + IPA_CLKON_CFG_OPEN_FTCH_HPS_BMSK); + + IPA_SETFIELD_IN_REG(*val, !!clkon_cfg->open_ram_arb, + IPA_CLKON_CFG_OPEN_RAM_ARB_SHFT, + IPA_CLKON_CFG_OPEN_RAM_ARB_BMSK); + + IPA_SETFIELD_IN_REG(*val, !!clkon_cfg->open_misc, + IPA_CLKON_CFG_OPEN_MISC_SHFT, + IPA_CLKON_CFG_OPEN_MISC_BMSK); + + IPA_SETFIELD_IN_REG(*val, !!clkon_cfg->open_tx_wrapper, + IPA_CLKON_CFG_OPEN_TX_WRAPPER_SHFT, + IPA_CLKON_CFG_OPEN_TX_WRAPPER_BMSK); + + IPA_SETFIELD_IN_REG(*val, !!clkon_cfg->open_proc, + IPA_CLKON_CFG_OPEN_PROC_SHFT, + IPA_CLKON_CFG_OPEN_PROC_BMSK); + + IPA_SETFIELD_IN_REG(*val, !!clkon_cfg->open_rx, + IPA_CLKON_CFG_OPEN_RX_SHFT, + IPA_CLKON_CFG_OPEN_RX_BMSK); +} + +static void ipareg_construct_clkon_cfg( + enum ipahal_reg_name reg, const void *fields, u32 *val) +{ + struct ipahal_reg_clkon_cfg *clkon_cfg = + (struct ipahal_reg_clkon_cfg *)fields; + + ipareg_construct_clkon_cfg_common(clkon_cfg, val); + + IPA_SETFIELD_IN_REG(*val, !!clkon_cfg->open_dcmp, + IPA_CLKON_CFG_OPEN_DCMP_SHFT, + IPA_CLKON_CFG_OPEN_DCMP_BMSK); +} + +static void ipareg_construct_clkon_cfg_v4_5( + enum ipahal_reg_name reg, const void *fields, u32 *val) +{ + struct ipahal_reg_clkon_cfg *clkon_cfg = + (struct ipahal_reg_clkon_cfg *)fields; + + ipareg_construct_clkon_cfg_common(clkon_cfg, val); + + IPA_SETFIELD_IN_REG(*val, !!clkon_cfg->open_dpl_fifo, + IPA_CLKON_CFG_CGC_OPEN_DPL_FIFO_SHFT_V4_5, + IPA_CLKON_CFG_CGC_OPEN_DPL_FIFO_BMSK_V4_5); +} + +static void ipareg_parse_clkon_cfg_common( + struct ipahal_reg_clkon_cfg *clkon_cfg, u32 val) +{ + memset(clkon_cfg, 0, sizeof(struct ipahal_reg_clkon_cfg)); + + clkon_cfg->open_global_2x_clk = IPA_GETFIELD_FROM_REG(val, + IPA_CLKON_CFG_OPEN_GLOBAL_2X_CLK_SHFT, + IPA_CLKON_CFG_OPEN_GLOBAL_2X_CLK_BMSK); + + clkon_cfg->open_global = IPA_GETFIELD_FROM_REG(val, + IPA_CLKON_CFG_OPEN_GLOBAL_SHFT, + IPA_CLKON_CFG_OPEN_GLOBAL_BMSK); + + clkon_cfg->open_gsi_if = IPA_GETFIELD_FROM_REG(val, + IPA_CLKON_CFG_OPEN_GSI_IF_SHFT, + IPA_CLKON_CFG_OPEN_GSI_IF_BMSK); + + clkon_cfg->open_weight_arb = IPA_GETFIELD_FROM_REG(val, + IPA_CLKON_CFG_OPEN_WEIGHT_ARB_SHFT, + IPA_CLKON_CFG_OPEN_WEIGHT_ARB_BMSK); + + clkon_cfg->open_qmb = IPA_GETFIELD_FROM_REG(val, + IPA_CLKON_CFG_OPEN_QMB_SHFT, + IPA_CLKON_CFG_OPEN_QMB_BMSK); + + clkon_cfg->open_ram_slaveway = IPA_GETFIELD_FROM_REG(val, + IPA_CLKON_CFG_OPEN_RAM_SLAVEWAY_SHFT, + IPA_CLKON_CFG_OPEN_RAM_SLAVEWAY_BMSK); + + clkon_cfg->open_aggr_wrapper = IPA_GETFIELD_FROM_REG(val, + IPA_CLKON_CFG_OPEN_AGGR_WRAPPER_SHFT, + IPA_CLKON_CFG_OPEN_AGGR_WRAPPER_BMSK); + + clkon_cfg->open_qsb2axi_cmdq_l = IPA_GETFIELD_FROM_REG(val, + IPA_CLKON_CFG_OPEN_QSB2AXI_CMDQ_L_SHFT, + IPA_CLKON_CFG_OPEN_QSB2AXI_CMDQ_L_BMSK); + + clkon_cfg->open_fnr = IPA_GETFIELD_FROM_REG(val, + IPA_CLKON_CFG_OPEN_FNR_SHFT, + IPA_CLKON_CFG_OPEN_FNR_BMSK); + + clkon_cfg->open_tx_1 = IPA_GETFIELD_FROM_REG(val, + IPA_CLKON_CFG_OPEN_TX_1_SHFT, + IPA_CLKON_CFG_OPEN_TX_1_BMSK); + + clkon_cfg->open_tx_0 = IPA_GETFIELD_FROM_REG(val, + IPA_CLKON_CFG_OPEN_TX_0_SHFT, + IPA_CLKON_CFG_OPEN_TX_0_BMSK); + + clkon_cfg->open_ntf_tx_cmdqs = IPA_GETFIELD_FROM_REG(val, + IPA_CLKON_CFG_OPEN_NTF_TX_CMDQS_SHFT, + IPA_CLKON_CFG_OPEN_NTF_TX_CMDQS_BMSK); + + clkon_cfg->open_h_dcph = IPA_GETFIELD_FROM_REG(val, + IPA_CLKON_CFG_OPEN_H_DCPH_SHFT, + IPA_CLKON_CFG_OPEN_H_DCPH_BMSK); + + clkon_cfg->open_d_dcph = IPA_GETFIELD_FROM_REG(val, + IPA_CLKON_CFG_OPEN_D_DCPH_SHFT, + IPA_CLKON_CFG_OPEN_D_DCPH_BMSK); + + clkon_cfg->open_ack_mngr = IPA_GETFIELD_FROM_REG(val, + IPA_CLKON_CFG_OPEN_ACK_MNGR_SHFT, + IPA_CLKON_CFG_OPEN_ACK_MNGR_BMSK); + + clkon_cfg->open_ctx_handler = IPA_GETFIELD_FROM_REG(val, + IPA_CLKON_CFG_OPEN_CTX_HANDLER_SHFT, + IPA_CLKON_CFG_OPEN_CTX_HANDLER_BMSK); + + clkon_cfg->open_rsrc_mngr = IPA_GETFIELD_FROM_REG(val, + IPA_CLKON_CFG_OPEN_RSRC_MNGR_SHFT, + IPA_CLKON_CFG_OPEN_RSRC_MNGR_BMSK); + + clkon_cfg->open_dps_tx_cmdqs = IPA_GETFIELD_FROM_REG(val, + IPA_CLKON_CFG_OPEN_DPS_TX_CMDQS_SHFT, + IPA_CLKON_CFG_OPEN_DPS_TX_CMDQS_BMSK); + + clkon_cfg->open_hps_dps_cmdqs = IPA_GETFIELD_FROM_REG(val, + IPA_CLKON_CFG_OPEN_HPS_DPS_CMDQS_SHFT, + IPA_CLKON_CFG_OPEN_HPS_DPS_CMDQS_BMSK); + + clkon_cfg->open_rx_hps_cmdqs = IPA_GETFIELD_FROM_REG(val, + IPA_CLKON_CFG_OPEN_RX_HPS_CMDQS_SHFT, + IPA_CLKON_CFG_OPEN_RX_HPS_CMDQS_BMSK); + + clkon_cfg->open_dps = IPA_GETFIELD_FROM_REG(val, + IPA_CLKON_CFG_OPEN_DPS_SHFT, + IPA_CLKON_CFG_OPEN_DPS_BMSK); + + clkon_cfg->open_hps = IPA_GETFIELD_FROM_REG(val, + IPA_CLKON_CFG_OPEN_HPS_SHFT, + IPA_CLKON_CFG_OPEN_HPS_BMSK); + + clkon_cfg->open_ftch_dps = IPA_GETFIELD_FROM_REG(val, + IPA_CLKON_CFG_OPEN_FTCH_DPS_SHFT, + IPA_CLKON_CFG_OPEN_FTCH_DPS_BMSK); + + clkon_cfg->open_ftch_hps = IPA_GETFIELD_FROM_REG(val, + IPA_CLKON_CFG_OPEN_FTCH_HPS_SHFT, + IPA_CLKON_CFG_OPEN_FTCH_HPS_BMSK); + + clkon_cfg->open_ram_arb = IPA_GETFIELD_FROM_REG(val, + IPA_CLKON_CFG_OPEN_RAM_ARB_SHFT, + IPA_CLKON_CFG_OPEN_RAM_ARB_BMSK); + + clkon_cfg->open_misc = IPA_GETFIELD_FROM_REG(val, + IPA_CLKON_CFG_OPEN_MISC_SHFT, + IPA_CLKON_CFG_OPEN_MISC_BMSK); + + clkon_cfg->open_tx_wrapper = IPA_GETFIELD_FROM_REG(val, + IPA_CLKON_CFG_OPEN_TX_WRAPPER_SHFT, + IPA_CLKON_CFG_OPEN_TX_WRAPPER_BMSK); + + clkon_cfg->open_proc = IPA_GETFIELD_FROM_REG(val, + IPA_CLKON_CFG_OPEN_PROC_SHFT, + IPA_CLKON_CFG_OPEN_PROC_BMSK); + + clkon_cfg->open_rx = IPA_GETFIELD_FROM_REG(val, + IPA_CLKON_CFG_OPEN_RX_SHFT, + IPA_CLKON_CFG_OPEN_RX_BMSK); +} + +static void ipareg_parse_clkon_cfg( + enum ipahal_reg_name reg, void *fields, u32 val) +{ + struct ipahal_reg_clkon_cfg *clkon_cfg = + (struct ipahal_reg_clkon_cfg *)fields; + + ipareg_parse_clkon_cfg_common(clkon_cfg, val); + + clkon_cfg->open_dcmp = IPA_GETFIELD_FROM_REG(val, + IPA_CLKON_CFG_OPEN_DCMP_SHFT, + IPA_CLKON_CFG_OPEN_DCMP_BMSK); +} + +static void ipareg_parse_clkon_cfg_v4_5( + enum ipahal_reg_name reg, void *fields, u32 val) +{ + struct ipahal_reg_clkon_cfg *clkon_cfg = + (struct ipahal_reg_clkon_cfg *)fields; + + ipareg_parse_clkon_cfg_common(clkon_cfg, val); + + clkon_cfg->open_dpl_fifo = IPA_GETFIELD_FROM_REG(val, + IPA_CLKON_CFG_CGC_OPEN_DPL_FIFO_SHFT_V4_5, + IPA_CLKON_CFG_CGC_OPEN_DPL_FIFO_BMSK_V4_5); +} + +static void ipareg_construct_qtime_timestamp_cfg( + enum ipahal_reg_name reg, const void *fields, u32 *val) +{ + const struct ipahal_reg_qtime_timestamp_cfg *ts_cfg = + (const struct ipahal_reg_qtime_timestamp_cfg *)fields; + + if (!ts_cfg->dpl_timestamp_sel && + ts_cfg->dpl_timestamp_lsb) { + IPAHAL_ERR("non zero DPL shift while legacy mode\n"); + WARN_ON(1); + } + + IPA_SETFIELD_IN_REG(*val, + ts_cfg->dpl_timestamp_lsb, + IPA_QTIME_TIMESTAMP_CFG_DPL_TIMESTAMP_LSB_SHFT, + IPA_QTIME_TIMESTAMP_CFG_DPL_TIMESTAMP_LSB_BMSK); + IPA_SETFIELD_IN_REG(*val, + ts_cfg->dpl_timestamp_sel ? 1 : 0, + IPA_QTIME_TIMESTAMP_CFG_DPL_TIMESTAMP_SEL_SHFT, + IPA_QTIME_TIMESTAMP_CFG_DPL_TIMESTAMP_SEL_BMSK); + IPA_SETFIELD_IN_REG(*val, + ts_cfg->tag_timestamp_lsb, + IPA_QTIME_TIMESTAMP_CFG_TAG_TIMESTAMP_LSB_SHFT, + IPA_QTIME_TIMESTAMP_CFG_TAG_TIMESTAMP_LSB_BMSK); + IPA_SETFIELD_IN_REG(*val, + ts_cfg->nat_timestamp_lsb, + IPA_QTIME_TIMESTAMP_CFG_NAT_TIMESTAMP_LSB_SHFT, + IPA_QTIME_TIMESTAMP_CFG_NAT_TIMESTAMP_LSB_BMSK); +} + +static void ipareg_construct_qtime_timestamp_cfg_v5_5( + enum ipahal_reg_name reg, const void *fields, u32 *val) +{ + const struct ipahal_reg_qtime_timestamp_cfg *ts_cfg = + (const struct ipahal_reg_qtime_timestamp_cfg *)fields; + + IPA_SETFIELD_IN_REG(*val, + ts_cfg->tag_timestamp_lsb, + IPA_QTIME_TIMESTAMP_CFG_TAG_TIMESTAMP_LSB_SHFT, + IPA_QTIME_TIMESTAMP_CFG_TAG_TIMESTAMP_LSB_BMSK); + IPA_SETFIELD_IN_REG(*val, + ts_cfg->nat_timestamp_lsb, + IPA_QTIME_TIMESTAMP_CFG_NAT_TIMESTAMP_LSB_SHFT, + IPA_QTIME_TIMESTAMP_CFG_NAT_TIMESTAMP_LSB_BMSK); +} + +static u8 ipareg_timers_pulse_gran_code( + enum ipa_timers_time_gran_type gran) +{ + switch (gran) { + case IPA_TIMERS_TIME_GRAN_10_USEC: return 0; + case IPA_TIMERS_TIME_GRAN_20_USEC: return 1; + case IPA_TIMERS_TIME_GRAN_50_USEC: return 2; + case IPA_TIMERS_TIME_GRAN_100_USEC: return 3; + case IPA_TIMERS_TIME_GRAN_1_MSEC: return 4; + case IPA_TIMERS_TIME_GRAN_10_MSEC: return 5; + case IPA_TIMERS_TIME_GRAN_100_MSEC: return 6; + case IPA_TIMERS_TIME_GRAN_NEAR_HALF_SEC: return 7; + default: + IPAHAL_ERR("Invalid granularity %d\n", gran); + break; + } + + return 3; +} + +static enum ipa_timers_time_gran_type + ipareg_timers_pulse_gran_decode(u8 code) +{ + switch (code) { + case 0: return IPA_TIMERS_TIME_GRAN_10_USEC; + case 1: return IPA_TIMERS_TIME_GRAN_20_USEC; + case 2: return IPA_TIMERS_TIME_GRAN_50_USEC; + case 3: return IPA_TIMERS_TIME_GRAN_100_USEC; + case 4: return IPA_TIMERS_TIME_GRAN_1_MSEC; + case 5: return IPA_TIMERS_TIME_GRAN_10_MSEC; + case 6: return IPA_TIMERS_TIME_GRAN_100_MSEC; + case 7: return IPA_TIMERS_TIME_GRAN_NEAR_HALF_SEC; + default: + IPAHAL_ERR("Invalid coded granularity %d\n", code); + break; + } + + return IPA_TIMERS_TIME_GRAN_100_USEC; +} + +static void ipareg_construct_timers_pulse_gran_cfg( + enum ipahal_reg_name reg, const void *fields, u32 *val) +{ + const struct ipahal_reg_timers_pulse_gran_cfg *gran_cfg = + (const struct ipahal_reg_timers_pulse_gran_cfg *)fields; + + IPA_SETFIELD_IN_REG(*val, + ipareg_timers_pulse_gran_code(gran_cfg->gran_0), + IPA_TIMERS_PULSE_GRAN_CFG_GRAN_X_SHFT(0), + IPA_TIMERS_PULSE_GRAN_CFG_GRAN_X_BMSK(0)); + + IPA_SETFIELD_IN_REG(*val, + ipareg_timers_pulse_gran_code(gran_cfg->gran_1), + IPA_TIMERS_PULSE_GRAN_CFG_GRAN_X_SHFT(1), + IPA_TIMERS_PULSE_GRAN_CFG_GRAN_X_BMSK(1)); + + IPA_SETFIELD_IN_REG(*val, + ipareg_timers_pulse_gran_code(gran_cfg->gran_2), + IPA_TIMERS_PULSE_GRAN_CFG_GRAN_X_SHFT(2), + IPA_TIMERS_PULSE_GRAN_CFG_GRAN_X_BMSK(2)); +} + +static void ipareg_construct_timers_pulse_gran_cfg_v5_0( + enum ipahal_reg_name reg, const void *fields, u32 *val) +{ + const struct ipahal_reg_timers_pulse_gran_cfg *gran_cfg = + (const struct ipahal_reg_timers_pulse_gran_cfg *)fields; + + ipareg_construct_timers_pulse_gran_cfg(reg, fields, val); + + IPA_SETFIELD_IN_REG(*val, + ipareg_timers_pulse_gran_code(gran_cfg->gran_3), + IPA_TIMERS_PULSE_GRAN_CFG_GRAN_X_SHFT(3), + IPA_TIMERS_PULSE_GRAN_CFG_GRAN_X_BMSK(3)); +} + +static void ipareg_parse_timers_pulse_gran_cfg( + enum ipahal_reg_name reg, void *fields, u32 val) +{ + u8 code; + struct ipahal_reg_timers_pulse_gran_cfg *gran_cfg = + (struct ipahal_reg_timers_pulse_gran_cfg *)fields; + + code = IPA_GETFIELD_FROM_REG(val, + IPA_TIMERS_PULSE_GRAN_CFG_GRAN_X_SHFT(0), + IPA_TIMERS_PULSE_GRAN_CFG_GRAN_X_BMSK(0)); + gran_cfg->gran_0 = ipareg_timers_pulse_gran_decode(code); + + code = IPA_GETFIELD_FROM_REG(val, + IPA_TIMERS_PULSE_GRAN_CFG_GRAN_X_SHFT(1), + IPA_TIMERS_PULSE_GRAN_CFG_GRAN_X_BMSK(1)); + gran_cfg->gran_1 = ipareg_timers_pulse_gran_decode(code); + + code = IPA_GETFIELD_FROM_REG(val, + IPA_TIMERS_PULSE_GRAN_CFG_GRAN_X_SHFT(2), + IPA_TIMERS_PULSE_GRAN_CFG_GRAN_X_BMSK(2)); + gran_cfg->gran_2 = ipareg_timers_pulse_gran_decode(code); +} + +static void ipareg_parse_timers_pulse_gran_cfg_v5_0( + enum ipahal_reg_name reg, void *fields, u32 val) +{ + u8 code; + struct ipahal_reg_timers_pulse_gran_cfg *gran_cfg = + (struct ipahal_reg_timers_pulse_gran_cfg *)fields; + + ipareg_parse_timers_pulse_gran_cfg(reg, fields, val); + + code = IPA_GETFIELD_FROM_REG(val, + IPA_TIMERS_PULSE_GRAN_CFG_GRAN_X_SHFT(3), + IPA_TIMERS_PULSE_GRAN_CFG_GRAN_X_BMSK(3)); + gran_cfg->gran_3 = ipareg_timers_pulse_gran_decode(code); +} + +static void ipareg_construct_timers_xo_clk_div_cfg( + enum ipahal_reg_name reg, const void *fields, u32 *val) +{ + const struct ipahal_reg_timers_xo_clk_div_cfg *div_cfg = + (const struct ipahal_reg_timers_xo_clk_div_cfg *)fields; + + IPA_SETFIELD_IN_REG(*val, + div_cfg->enable ? 1 : 0, + IPA_TIMERS_XO_CLK_DIV_CFG_ENABLE_SHFT, + IPA_TIMERS_XO_CLK_DIV_CFG_ENABLE_BMSK); + + IPA_SETFIELD_IN_REG(*val, + div_cfg->value, + IPA_TIMERS_XO_CLK_DIV_CFG_VALUE_SHFT, + IPA_TIMERS_XO_CLK_DIV_CFG_VALUE_BMSK); +} + +static void ipareg_parse_timers_xo_clk_div_cfg( + enum ipahal_reg_name reg, void *fields, u32 val) +{ + struct ipahal_reg_timers_xo_clk_div_cfg *div_cfg = + (struct ipahal_reg_timers_xo_clk_div_cfg *)fields; + + div_cfg->enable = + IPA_GETFIELD_FROM_REG(val, + IPA_TIMERS_XO_CLK_DIV_CFG_ENABLE_SHFT, + IPA_TIMERS_XO_CLK_DIV_CFG_ENABLE_BMSK); + + div_cfg->value = + IPA_GETFIELD_FROM_REG(val, + IPA_TIMERS_XO_CLK_DIV_CFG_VALUE_SHFT, + IPA_TIMERS_XO_CLK_DIV_CFG_VALUE_BMSK); +} + +static void ipareg_construct_comp_cfg_comon( + const struct ipahal_reg_comp_cfg *comp_cfg, u32 *val) +{ + + IPA_SETFIELD_IN_REG(*val, + !!comp_cfg->ipa_qmb_select_by_address_global_en, + IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_GLOBAL_EN_SHFT, + IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_GLOBAL_EN_BMSK); + + IPA_SETFIELD_IN_REG(*val, + !!comp_cfg->gsi_multi_axi_masters_dis, + IPA_COMP_CFG_GSI_MULTI_AXI_MASTERS_DIS_SHFT, + IPA_COMP_CFG_GSI_MULTI_AXI_MASTERS_DIS_BMSK); + + IPA_SETFIELD_IN_REG(*val, + !!comp_cfg->gsi_snoc_cnoc_loop_protection_disable, + IPA_COMP_CFG_GSI_SNOC_CNOC_LOOP_PROTECTION_DISABLE_SHFT, + IPA_COMP_CFG_GSI_SNOC_CNOC_LOOP_PROTECTION_DISABLE_BMSK); + + IPA_SETFIELD_IN_REG(*val, + !!comp_cfg->gen_qmb_0_snoc_cnoc_loop_protection_disable, + IPA_COMP_CFG_GEN_QMB_0_SNOC_CNOC_LOOP_PROTECTION_DISABLE_SHFT, + IPA_COMP_CFG_GEN_QMB_0_SNOC_CNOC_LOOP_PROTECTION_DISABLE_BMSK); + + IPA_SETFIELD_IN_REG(*val, + !!comp_cfg->gen_qmb_1_multi_inorder_wr_dis, + IPA_COMP_CFG_GEN_QMB_1_MULTI_INORDER_WR_DIS_SHFT, + IPA_COMP_CFG_GEN_QMB_1_MULTI_INORDER_WR_DIS_BMSK); + + IPA_SETFIELD_IN_REG(*val, + !!comp_cfg->gen_qmb_0_multi_inorder_wr_dis, + IPA_COMP_CFG_GEN_QMB_0_MULTI_INORDER_WR_DIS_SHFT, + IPA_COMP_CFG_GEN_QMB_0_MULTI_INORDER_WR_DIS_BMSK); + + IPA_SETFIELD_IN_REG(*val, + !!comp_cfg->gen_qmb_1_multi_inorder_rd_dis, + IPA_COMP_CFG_GEN_QMB_1_MULTI_INORDER_RD_DIS_SHFT, + IPA_COMP_CFG_GEN_QMB_1_MULTI_INORDER_RD_DIS_BMSK); + + IPA_SETFIELD_IN_REG(*val, + !!comp_cfg->gen_qmb_0_multi_inorder_rd_dis, + IPA_COMP_CFG_GEN_QMB_0_MULTI_INORDER_RD_DIS_SHFT, + IPA_COMP_CFG_GEN_QMB_0_MULTI_INORDER_RD_DIS_BMSK); + + IPA_SETFIELD_IN_REG(*val, + !!comp_cfg->gsi_multi_inorder_wr_dis, + IPA_COMP_CFG_GSI_MULTI_INORDER_WR_DIS_SHFT, + IPA_COMP_CFG_GSI_MULTI_INORDER_WR_DIS_BMSK); + + IPA_SETFIELD_IN_REG(*val, + !!comp_cfg->gsi_multi_inorder_rd_dis, + IPA_COMP_CFG_GSI_MULTI_INORDER_RD_DIS_SHFT, + IPA_COMP_CFG_GSI_MULTI_INORDER_RD_DIS_BMSK); + + IPA_SETFIELD_IN_REG(*val, + !!comp_cfg->ipa_qmb_select_by_address_prod_en, + IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_PROD_EN_SHFT, + IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_PROD_EN_BMSK); + + IPA_SETFIELD_IN_REG(*val, + !!comp_cfg->ipa_qmb_select_by_address_cons_en, + IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_CONS_EN_SHFT, + IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_CONS_EN_BMSK); + + IPA_SETFIELD_IN_REG(*val, + !!comp_cfg->gen_qmb_1_snoc_bypass_dis, + IPA_COMP_CFG_GEN_QMB_1_SNOC_BYPASS_DIS_SHFT, + IPA_COMP_CFG_GEN_QMB_1_SNOC_BYPASS_DIS_BMSK); + + IPA_SETFIELD_IN_REG(*val, + !!comp_cfg->gen_qmb_0_snoc_bypass_dis, + IPA_COMP_CFG_GEN_QMB_0_SNOC_BYPASS_DIS_SHFT, + IPA_COMP_CFG_GEN_QMB_0_SNOC_BYPASS_DIS_BMSK); + + IPA_SETFIELD_IN_REG(*val, + !!comp_cfg->gsi_snoc_bypass_dis, + IPA_COMP_CFG_GSI_SNOC_BYPASS_DIS_SHFT, + IPA_COMP_CFG_GSI_SNOC_BYPASS_DIS_BMSK); +} + +static void ipareg_construct_comp_cfg( + enum ipahal_reg_name reg, const void *fields, u32 *val) +{ + struct ipahal_reg_comp_cfg *comp_cfg = + (struct ipahal_reg_comp_cfg *)fields; + + ipareg_construct_comp_cfg_comon(comp_cfg, val); + + IPA_SETFIELD_IN_REG(*val, + comp_cfg->ipa_atomic_fetcher_arb_lock_dis, + IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_SHFT, + IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_BMSK); + + IPA_SETFIELD_IN_REG(*val, + !!comp_cfg->enable, + IPA_COMP_CFG_ENABLE_SHFT, + IPA_COMP_CFG_ENABLE_BMSK); + + IPA_SETFIELD_IN_REG(*val, + !!comp_cfg->ipa_dcmp_fast_clk_en, + IPA_COMP_CFG_IPA_DCMP_FAST_CLK_EN_SHFT, + IPA_COMP_CFG_IPA_DCMP_FAST_CLK_EN_BMSK); +} + +static void ipareg_construct_comp_cfg_v4_5( + enum ipahal_reg_name reg, const void *fields, u32 *val) +{ + struct ipahal_reg_comp_cfg *comp_cfg = + (struct ipahal_reg_comp_cfg *)fields; + + ipareg_construct_comp_cfg_comon(comp_cfg, val); + + IPA_SETFIELD_IN_REG(*val, + comp_cfg->ipa_atomic_fetcher_arb_lock_dis, + IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_SHFT, + IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_BMSK); + + IPA_SETFIELD_IN_REG(*val, + !!comp_cfg->ipa_full_flush_wait_rsc_closure_en, + IPA_COMP_CFG_IPA_FULL_FLUSH_WAIT_RSC_CLOSURE_EN_SHFT_v4_5, + IPA_COMP_CFG_IPA_FULL_FLUSH_WAIT_RSC_CLOSURE_EN_BMSK_v4_5); +} + +static void ipareg_construct_comp_cfg_v4_9( + enum ipahal_reg_name reg, const void *fields, u32 *val) +{ + struct ipahal_reg_comp_cfg *comp_cfg = + (struct ipahal_reg_comp_cfg *)fields; + + ipareg_construct_comp_cfg_comon(comp_cfg, val); + + IPA_SETFIELD_IN_REG(*val, + !!comp_cfg->gen_qmb_0_dynamic_asize, + IPA_COMP_CFG_GEN_QMB_0_DYNAMIC_ASIZE_SHFT_v4_9, + IPA_COMP_CFG_GEN_QMB_0_DYNAMIC_ASIZE_BMSK_v4_9); + + IPA_SETFIELD_IN_REG(*val, + !!comp_cfg->gen_qmb_1_dynamic_asize, + IPA_COMP_CFG_GEN_QMB_1_DYNAMIC_ASIZE_SHFT_v4_9, + IPA_COMP_CFG_GEN_QMB_1_DYNAMIC_ASIZE_BMSK_v4_9); + + IPA_SETFIELD_IN_REG(*val, + !!comp_cfg->ipa_atomic_fetcher_arb_lock_dis, + IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_SHFT_v4_9, + IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_BMSK_v4_9); + + IPA_SETFIELD_IN_REG(*val, + !!comp_cfg->gsi_if_out_of_buf_stop_reset_mask_enable, + IPA_COMP_CFG_GSI_IF_OUT_OF_BUF_STOP_RESET_MASK_ENABLE_SHFT_v4_9, + IPA_COMP_CFG_GSI_IF_OUT_OF_BUF_STOP_RESET_MASK_ENABLE_BMSK_v4_9); + + IPA_SETFIELD_IN_REG(*val, + !!comp_cfg->genqmb_aooowr, + IPA_COMP_CFG_GENQMB_AOOOWR_SHFT_v4_9, + IPA_COMP_CFG_GENQMB_AOOOWR_BMSK_v4_9); + + IPA_SETFIELD_IN_REG(*val, + !!comp_cfg->qmb_ram_rd_cache_disable, + IPA_COMP_CFG_QMB_RAM_RD_CACHE_DISABLE_SHFT_v4_9, + IPA_COMP_CFG_QMB_RAM_RD_CACHE_DISABLE_BMSK_v4_9); + + IPA_SETFIELD_IN_REG(*val, + !!comp_cfg->ipa_full_flush_wait_rsc_closure_en, + IPA_COMP_CFG_IPA_FULL_FLUSH_WAIT_RSC_CLOSURE_EN_SHFT_v4_9, + IPA_COMP_CFG_IPA_FULL_FLUSH_WAIT_RSC_CLOSURE_EN_BMSK_v4_9); + + IPA_SETFIELD_IN_REG(*val, + !!comp_cfg->ram_arb_priority_client_samp_fix_disable, + IPA_COMP_CFG_RAM_ARB_PRIORITY_CLIENT_SAMP_FIX_DISABLE_SHFT_v4_9, + IPA_COMP_CFG_RAM_ARB_PRIORITY_CLIENT_SAMP_FIX_DISABLE_BMSK_v4_9); + + +} + +static void ipareg_construct_comp_cfg_v5_0( + enum ipahal_reg_name reg, const void *fields, u32 *val) +{ + struct ipahal_reg_comp_cfg *comp_cfg = + (struct ipahal_reg_comp_cfg *)fields; + + ipareg_construct_comp_cfg_comon(comp_cfg, val); + + IPA_SETFIELD_IN_REG(*val, + !!comp_cfg->gen_qmb_0_dynamic_asize, + IPA_COMP_CFG_GEN_QMB_0_DYNAMIC_ASIZE_SHFT_v5_0, + IPA_COMP_CFG_GEN_QMB_0_DYNAMIC_ASIZE_BMSK_v5_0); + + IPA_SETFIELD_IN_REG(*val, + !!comp_cfg->gen_qmb_1_dynamic_asize, + IPA_COMP_CFG_GEN_QMB_1_DYNAMIC_ASIZE_SHFT_v5_0, + IPA_COMP_CFG_GEN_QMB_1_DYNAMIC_ASIZE_BMSK_v5_0); + + IPA_SETFIELD_IN_REG(*val, + !!comp_cfg->ipa_atomic_fetcher_arb_lock_dis, + IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_SHFT_v5_0, + IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_BMSK_v5_0); + + IPA_SETFIELD_IN_REG(*val, + !!comp_cfg->gsi_if_out_of_buf_stop_reset_mask_enable, + IPA_COMP_CFG_GSI_IF_OUT_OF_BUF_STOP_RESET_MASK_ENABLE_SHFT_v5_0, + IPA_COMP_CFG_GSI_IF_OUT_OF_BUF_STOP_RESET_MASK_ENABLE_BMSK_v5_0); + + IPA_SETFIELD_IN_REG(*val, + !!comp_cfg->genqmb_aooowr, + IPA_COMP_CFG_GENQMB_AOOOWR_SHFT_v5_0, + IPA_COMP_CFG_GENQMB_AOOOWR_BMSK_v5_0); + + IPA_SETFIELD_IN_REG(*val, + !!comp_cfg->qmb_ram_rd_cache_disable, + IPA_COMP_CFG_QMB_RAM_RD_CACHE_DISABLE_SHFT_v5_0, + IPA_COMP_CFG_QMB_RAM_RD_CACHE_DISABLE_BMSK_v5_0); + + IPA_SETFIELD_IN_REG(*val, + !!comp_cfg->ipa_full_flush_wait_rsc_closure_en, + IPA_COMP_CFG_IPA_FULL_FLUSH_WAIT_RSC_CLOSURE_EN_SHFT_v5_0, + IPA_COMP_CFG_IPA_FULL_FLUSH_WAIT_RSC_CLOSURE_EN_BMSK_v5_0); + + IPA_SETFIELD_IN_REG(*val, + !!comp_cfg->ram_arb_priority_client_samp_fix_disable, + IPA_COMP_CFG_RAM_ARB_PRIORITY_CLIENT_SAMP_FIX_DISABLE_SHFT_v5_0, + IPA_COMP_CFG_RAM_ARB_PRIORITY_CLIENT_SAMP_FIX_DISABLE_BMSK_v5_0); +} + +static void ipareg_parse_comp_cfg_common( + struct ipahal_reg_comp_cfg *comp_cfg, u32 val) +{ + memset(comp_cfg, 0, sizeof(struct ipahal_reg_comp_cfg)); + + + comp_cfg->ipa_qmb_select_by_address_global_en = + IPA_GETFIELD_FROM_REG(val, + IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_GLOBAL_EN_SHFT, + IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_GLOBAL_EN_BMSK); + + comp_cfg->gsi_multi_axi_masters_dis = + IPA_GETFIELD_FROM_REG(val, + IPA_COMP_CFG_GSI_MULTI_AXI_MASTERS_DIS_SHFT, + IPA_COMP_CFG_GSI_MULTI_AXI_MASTERS_DIS_BMSK); + + comp_cfg->gsi_snoc_cnoc_loop_protection_disable = + IPA_GETFIELD_FROM_REG(val, + IPA_COMP_CFG_GSI_SNOC_CNOC_LOOP_PROTECTION_DISABLE_SHFT, + IPA_COMP_CFG_GSI_SNOC_CNOC_LOOP_PROTECTION_DISABLE_BMSK); + + comp_cfg->gen_qmb_0_snoc_cnoc_loop_protection_disable = + IPA_GETFIELD_FROM_REG(val, + IPA_COMP_CFG_GEN_QMB_0_SNOC_CNOC_LOOP_PROTECTION_DISABLE_SHFT, + IPA_COMP_CFG_GEN_QMB_0_SNOC_CNOC_LOOP_PROTECTION_DISABLE_BMSK); + + comp_cfg->gen_qmb_1_multi_inorder_wr_dis = + IPA_GETFIELD_FROM_REG(val, + IPA_COMP_CFG_GEN_QMB_1_MULTI_INORDER_WR_DIS_SHFT, + IPA_COMP_CFG_GEN_QMB_1_MULTI_INORDER_WR_DIS_BMSK); + + comp_cfg->gen_qmb_0_multi_inorder_wr_dis = + IPA_GETFIELD_FROM_REG(val, + IPA_COMP_CFG_GEN_QMB_0_MULTI_INORDER_WR_DIS_SHFT, + IPA_COMP_CFG_GEN_QMB_0_MULTI_INORDER_WR_DIS_BMSK); + + comp_cfg->gen_qmb_1_multi_inorder_rd_dis = + IPA_GETFIELD_FROM_REG(val, + IPA_COMP_CFG_GEN_QMB_1_MULTI_INORDER_RD_DIS_SHFT, + IPA_COMP_CFG_GEN_QMB_1_MULTI_INORDER_RD_DIS_BMSK); + + comp_cfg->gen_qmb_0_multi_inorder_rd_dis = + IPA_GETFIELD_FROM_REG(val, + IPA_COMP_CFG_GEN_QMB_0_MULTI_INORDER_RD_DIS_SHFT, + IPA_COMP_CFG_GEN_QMB_0_MULTI_INORDER_RD_DIS_BMSK); + + comp_cfg->gsi_multi_inorder_wr_dis = + IPA_GETFIELD_FROM_REG(val, + IPA_COMP_CFG_GSI_MULTI_INORDER_WR_DIS_SHFT, + IPA_COMP_CFG_GSI_MULTI_INORDER_WR_DIS_BMSK); + + comp_cfg->gsi_multi_inorder_rd_dis = + IPA_GETFIELD_FROM_REG(val, + IPA_COMP_CFG_GSI_MULTI_INORDER_RD_DIS_SHFT, + IPA_COMP_CFG_GSI_MULTI_INORDER_RD_DIS_BMSK); + + comp_cfg->ipa_qmb_select_by_address_prod_en = + IPA_GETFIELD_FROM_REG(val, + IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_PROD_EN_SHFT, + IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_PROD_EN_BMSK); + + comp_cfg->ipa_qmb_select_by_address_cons_en = + IPA_GETFIELD_FROM_REG(val, + IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_CONS_EN_SHFT, + IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_CONS_EN_BMSK); + + comp_cfg->gen_qmb_1_snoc_bypass_dis = + IPA_GETFIELD_FROM_REG(val, + IPA_COMP_CFG_GEN_QMB_1_SNOC_BYPASS_DIS_SHFT, + IPA_COMP_CFG_GEN_QMB_1_SNOC_BYPASS_DIS_BMSK); + + comp_cfg->gen_qmb_0_snoc_bypass_dis = + IPA_GETFIELD_FROM_REG(val, + IPA_COMP_CFG_GEN_QMB_0_SNOC_BYPASS_DIS_SHFT, + IPA_COMP_CFG_GEN_QMB_0_SNOC_BYPASS_DIS_BMSK); + + comp_cfg->gsi_snoc_bypass_dis = + IPA_GETFIELD_FROM_REG(val, + IPA_COMP_CFG_GSI_SNOC_BYPASS_DIS_SHFT, + IPA_COMP_CFG_GSI_SNOC_BYPASS_DIS_BMSK); +} + +static void ipareg_parse_comp_cfg( + enum ipahal_reg_name reg, void *fields, u32 val) +{ + struct ipahal_reg_comp_cfg *comp_cfg = + (struct ipahal_reg_comp_cfg *)fields; + + ipareg_parse_comp_cfg_common(comp_cfg, val); + + comp_cfg->ipa_atomic_fetcher_arb_lock_dis = + IPA_GETFIELD_FROM_REG(val, + IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_SHFT, + IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_BMSK); + + comp_cfg->enable = + IPA_GETFIELD_FROM_REG(val, + IPA_COMP_CFG_ENABLE_SHFT, + IPA_COMP_CFG_ENABLE_BMSK); + + comp_cfg->ipa_dcmp_fast_clk_en = + IPA_GETFIELD_FROM_REG(val, + IPA_COMP_CFG_IPA_DCMP_FAST_CLK_EN_SHFT, + IPA_COMP_CFG_IPA_DCMP_FAST_CLK_EN_BMSK); +} + +static void ipareg_parse_comp_cfg_v4_5( + enum ipahal_reg_name reg, void *fields, u32 val) +{ + struct ipahal_reg_comp_cfg *comp_cfg = + (struct ipahal_reg_comp_cfg *)fields; + + ipareg_parse_comp_cfg_common(comp_cfg, val); + + comp_cfg->ipa_atomic_fetcher_arb_lock_dis = + IPA_GETFIELD_FROM_REG(val, + IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_SHFT, + IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_BMSK); + + comp_cfg->ipa_full_flush_wait_rsc_closure_en = + IPA_GETFIELD_FROM_REG(val, + IPA_COMP_CFG_IPA_FULL_FLUSH_WAIT_RSC_CLOSURE_EN_SHFT_v4_5, + IPA_COMP_CFG_IPA_FULL_FLUSH_WAIT_RSC_CLOSURE_EN_BMSK_v4_5); +} + +static void ipareg_parse_comp_cfg_v4_9( + enum ipahal_reg_name reg, void *fields, u32 val) +{ + struct ipahal_reg_comp_cfg *comp_cfg = + (struct ipahal_reg_comp_cfg *)fields; + + ipareg_parse_comp_cfg_common(comp_cfg, val); + + comp_cfg->gen_qmb_0_dynamic_asize = + IPA_GETFIELD_FROM_REG(val, + IPA_COMP_CFG_GEN_QMB_0_DYNAMIC_ASIZE_SHFT_v4_9, + IPA_COMP_CFG_GEN_QMB_0_DYNAMIC_ASIZE_BMSK_v4_9); + + comp_cfg->gen_qmb_1_dynamic_asize = + IPA_GETFIELD_FROM_REG(val, + IPA_COMP_CFG_GEN_QMB_1_DYNAMIC_ASIZE_SHFT_v4_9, + IPA_COMP_CFG_GEN_QMB_1_DYNAMIC_ASIZE_BMSK_v4_9); + + comp_cfg->ipa_atomic_fetcher_arb_lock_dis = + IPA_GETFIELD_FROM_REG(val, + IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_SHFT_v4_9, + IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_BMSK_v4_9); + + comp_cfg->gsi_if_out_of_buf_stop_reset_mask_enable = + IPA_GETFIELD_FROM_REG(val, + IPA_COMP_CFG_GSI_IF_OUT_OF_BUF_STOP_RESET_MASK_ENABLE_SHFT_v4_9, + IPA_COMP_CFG_GSI_IF_OUT_OF_BUF_STOP_RESET_MASK_ENABLE_BMSK_v4_9); + + comp_cfg->genqmb_aooowr = + IPA_GETFIELD_FROM_REG(val, + IPA_COMP_CFG_GENQMB_AOOOWR_SHFT_v4_9, + IPA_COMP_CFG_GENQMB_AOOOWR_BMSK_v4_9); + + comp_cfg->qmb_ram_rd_cache_disable = + IPA_GETFIELD_FROM_REG(val, + IPA_COMP_CFG_QMB_RAM_RD_CACHE_DISABLE_SHFT_v4_9, + IPA_COMP_CFG_QMB_RAM_RD_CACHE_DISABLE_BMSK_v4_9); + + comp_cfg->ipa_full_flush_wait_rsc_closure_en = + IPA_GETFIELD_FROM_REG(val, + IPA_COMP_CFG_IPA_FULL_FLUSH_WAIT_RSC_CLOSURE_EN_SHFT_v4_9, + IPA_COMP_CFG_IPA_FULL_FLUSH_WAIT_RSC_CLOSURE_EN_BMSK_v4_9); + + comp_cfg->ram_arb_priority_client_samp_fix_disable = + IPA_GETFIELD_FROM_REG(val, + IPA_COMP_CFG_RAM_ARB_PRIORITY_CLIENT_SAMP_FIX_DISABLE_SHFT_v4_9, + IPA_COMP_CFG_RAM_ARB_PRIORITY_CLIENT_SAMP_FIX_DISABLE_BMSK_v4_9); + +} + +static void ipareg_parse_comp_cfg_v5_0( + enum ipahal_reg_name reg, void *fields, u32 val) +{ + struct ipahal_reg_comp_cfg *comp_cfg = + (struct ipahal_reg_comp_cfg *)fields; + + ipareg_parse_comp_cfg_common(comp_cfg, val); + + comp_cfg->gen_qmb_0_dynamic_asize = + IPA_GETFIELD_FROM_REG(val, + IPA_COMP_CFG_GEN_QMB_0_DYNAMIC_ASIZE_SHFT_v5_0, + IPA_COMP_CFG_GEN_QMB_0_DYNAMIC_ASIZE_BMSK_v5_0); + + comp_cfg->gen_qmb_1_dynamic_asize = + IPA_GETFIELD_FROM_REG(val, + IPA_COMP_CFG_GEN_QMB_1_DYNAMIC_ASIZE_SHFT_v5_0, + IPA_COMP_CFG_GEN_QMB_1_DYNAMIC_ASIZE_BMSK_v5_0); + + comp_cfg->ipa_atomic_fetcher_arb_lock_dis = + IPA_GETFIELD_FROM_REG(val, + IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_SHFT_v5_0, + IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_BMSK_v5_0); + + comp_cfg->gsi_if_out_of_buf_stop_reset_mask_enable = + IPA_GETFIELD_FROM_REG(val, + IPA_COMP_CFG_GSI_IF_OUT_OF_BUF_STOP_RESET_MASK_ENABLE_SHFT_v5_0, + IPA_COMP_CFG_GSI_IF_OUT_OF_BUF_STOP_RESET_MASK_ENABLE_BMSK_v5_0); + + comp_cfg->genqmb_aooowr = + IPA_GETFIELD_FROM_REG(val, + IPA_COMP_CFG_GENQMB_AOOOWR_SHFT_v5_0, + IPA_COMP_CFG_GENQMB_AOOOWR_BMSK_v5_0); + + comp_cfg->qmb_ram_rd_cache_disable = + IPA_GETFIELD_FROM_REG(val, + IPA_COMP_CFG_QMB_RAM_RD_CACHE_DISABLE_SHFT_v5_0, + IPA_COMP_CFG_QMB_RAM_RD_CACHE_DISABLE_BMSK_v5_0); + + comp_cfg->ipa_full_flush_wait_rsc_closure_en = + IPA_GETFIELD_FROM_REG(val, + IPA_COMP_CFG_IPA_FULL_FLUSH_WAIT_RSC_CLOSURE_EN_SHFT_v5_0, + IPA_COMP_CFG_IPA_FULL_FLUSH_WAIT_RSC_CLOSURE_EN_BMSK_v5_0); + + comp_cfg->ram_arb_priority_client_samp_fix_disable = + IPA_GETFIELD_FROM_REG(val, + IPA_COMP_CFG_RAM_ARB_PRIORITY_CLIENT_SAMP_FIX_DISABLE_SHFT_v5_0, + IPA_COMP_CFG_RAM_ARB_PRIORITY_CLIENT_SAMP_FIX_DISABLE_BMSK_v5_0); + +} + +static void ipareg_parse_state_tx_wrapper_v4_5( + enum ipahal_reg_name reg, void *fields, u32 val) +{ + struct ipahal_reg_tx_wrapper *tx = + (struct ipahal_reg_tx_wrapper *)fields; + + tx->tx0_idle = IPA_GETFIELD_FROM_REG(val, + IPA_STATE_TX_WRAPPER_TX0_IDLE_SHFT, + IPA_STATE_TX_WRAPPER_TX0_IDLE_BMSK); + + tx->tx1_idle = IPA_GETFIELD_FROM_REG(val, + IPA_STATE_TX_WRAPPER_TX1_IDLE_SHFT, + IPA_STATE_TX_WRAPPER_TX1_IDLE_BMSK); + + tx->ipa_prod_ackmngr_db_empty = IPA_GETFIELD_FROM_REG(val, + IPA_STATE_TX_WRAPPER_IPA_PROD_ACKMNGR_DB_EMPTY_SHFT, + IPA_STATE_TX_WRAPPER_IPA_PROD_ACKMNGR_DB_EMPTY_BMSK); + + tx->ipa_prod_ackmngr_state_idle = IPA_GETFIELD_FROM_REG(val, + IPA_STATE_TX_WRAPPER_IPA_PROD_ACKMNGR_STATE_IDLE_SHFT, + IPA_STATE_TX_WRAPPER_IPA_PROD_ACKMNGR_STATE_IDLE_BMSK); + + tx->ipa_prod_prod_bresp_empty = IPA_GETFIELD_FROM_REG(val, + IPA_STATE_TX_WRAPPER_IPA_PROD_BRESP_EMPTY_SHFT, + IPA_STATE_TX_WRAPPER_IPA_PROD_BRESP_EMPTY_BMSK); + + tx->ipa_prod_prod_bresp_toggle_idle = IPA_GETFIELD_FROM_REG(val, + IPA_STATE_TX_WRAPPER_IPA_PROD_BRESP_EMPTY_SHFT, + IPA_STATE_TX_WRAPPER_IPA_PROD_BRESP_EMPTY_BMSK); + + tx->ipa_mbim_pkt_fms_idle = IPA_GETFIELD_FROM_REG(val, + IPA_STATE_TX_WRAPPER_IPA_MBIM_PKT_FMS_IDLE_SHFT, + IPA_STATE_TX_WRAPPER_IPA_MBIM_PKT_FMS_IDLE_BMSK); + + tx->mbim_direct_dma = IPA_GETFIELD_FROM_REG(val, + IPA_STATE_TX_WRAPPER_MBIM_DIRECT_DMA_SHFT, + IPA_STATE_TX_WRAPPER_MBIM_DIRECT_DMA_BMSK); + + tx->trnseq_force_valid = IPA_GETFIELD_FROM_REG(val, + IPA_STATE_TX_WRAPPER_TRNSEQ_FORCE_VALID_SHFT, + IPA_STATE_TX_WRAPPER_TRNSEQ_FORCE_VALID_BMSK); + + tx->pkt_drop_cnt_idle = IPA_GETFIELD_FROM_REG(val, + IPA_STATE_TX_WRAPPER_PKT_DROP_CNT_IDLE_SHFT, + IPA_STATE_TX_WRAPPER_PKT_DROP_CNT_IDLE_BMSK); + + tx->nlo_direct_dma = IPA_GETFIELD_FROM_REG(val, + IPA_STATE_TX_WRAPPER_NLO_DIRECT_DMA_SHFT, + IPA_STATE_TX_WRAPPER_NLO_DIRECT_DMA_BMSK); + + tx->coal_direct_dma = IPA_GETFIELD_FROM_REG(val, + IPA_STATE_TX_WRAPPER_COAL_DIRECT_DMA_SHFT, + IPA_STATE_TX_WRAPPER_COAL_DIRECT_DMA_BMSK); + + tx->coal_slave_idle = IPA_GETFIELD_FROM_REG(val, + IPA_STATE_TX_WRAPPER_COAL_SLAVE_IDLE_SHFT, + IPA_STATE_TX_WRAPPER_COAL_SLAVE_IDLE_BMSK); + + tx->coal_slave_ctx_idle = IPA_GETFIELD_FROM_REG(val, + IPA_STATE_TX_WRAPPER_COAL_SLAVE_CTX_IDLE_SHFT, + IPA_STATE_TX_WRAPPER_COAL_SLAVE_CTX_IDLE_BMSK); + + tx->coal_slave_open_frame = IPA_GETFIELD_FROM_REG(val, + IPA_STATE_TX_WRAPPER_COAL_SLAVE_OPEN_FRAME_SHFT, + IPA_STATE_TX_WRAPPER_COAL_SLAVE_OPEN_FRAME_BMSK); +} + +static void ipareg_parse_state_tx_wrapper_v4_7( + enum ipahal_reg_name reg, void *fields, u32 val) +{ + struct ipahal_reg_tx_wrapper *tx = + (struct ipahal_reg_tx_wrapper *)fields; + + tx->tx0_idle = IPA_GETFIELD_FROM_REG(val, + IPA_STATE_TX_WRAPPER_TX0_IDLE_SHFT_v4_7, + IPA_STATE_TX_WRAPPER_TX0_IDLE_BMSK_v4_7); + + tx->tx1_idle = IPA_GETFIELD_FROM_REG(val, + IPA_STATE_TX_WRAPPER_TX1_IDLE_SHFT_v4_7, + IPA_STATE_TX_WRAPPER_TX1_IDLE_BMSK_v4_7); + + tx->ipa_prod_ackmngr_db_empty = IPA_GETFIELD_FROM_REG(val, + IPA_STATE_TX_WRAPPER_IPA_PROD_ACKMNGR_DB_EMPTY_SHFT_v4_7, + IPA_STATE_TX_WRAPPER_IPA_PROD_ACKMNGR_DB_EMPTY_BMSK_v4_7); + + tx->ipa_prod_ackmngr_state_idle = IPA_GETFIELD_FROM_REG(val, + IPA_STATE_TX_WRAPPER_IPA_PROD_ACKMNGR_STATE_IDLE_SHFT_v4_7, + IPA_STATE_TX_WRAPPER_IPA_PROD_ACKMNGR_STATE_IDLE_BMSK_v4_7); + + tx->ipa_prod_prod_bresp_empty = IPA_GETFIELD_FROM_REG(val, + IPA_STATE_TX_WRAPPER_IPA_PROD_BRESP_EMPTY_SHFT_v4_7, + IPA_STATE_TX_WRAPPER_IPA_PROD_BRESP_EMPTY_BMSK_v4_7); + + tx->coal_slave_idle = IPA_GETFIELD_FROM_REG(val, + IPA_STATE_TX_WRAPPER_COAL_SLAVE_IDLE_SHFT_v4_7, + IPA_STATE_TX_WRAPPER_COAL_SLAVE_IDLE_BMSK_v4_7); + + tx->coal_slave_ctx_idle = IPA_GETFIELD_FROM_REG(val, + IPA_STATE_TX_WRAPPER_COAL_SLAVE_CTX_IDLE_SHFT_v4_7, + IPA_STATE_TX_WRAPPER_COAL_SLAVE_CTX_IDLE_BMSK_v4_7); + + tx->coal_slave_open_frame = IPA_GETFIELD_FROM_REG(val, + IPA_STATE_TX_WRAPPER_COAL_SLAVE_OPEN_FRAME_SHFT_v4_7, + IPA_STATE_TX_WRAPPER_COAL_SLAVE_OPEN_FRAME_BMSK_v4_7); +} + +static void ipareg_construct_qcncm( + enum ipahal_reg_name reg, const void *fields, u32 *val) +{ + struct ipahal_reg_qcncm *qcncm = + (struct ipahal_reg_qcncm *)fields; + + IPA_SETFIELD_IN_REG(*val, qcncm->mode_en ? 1 : 0, + IPA_QCNCM_MODE_EN_SHFT, + IPA_QCNCM_MODE_EN_BMSK); + IPA_SETFIELD_IN_REG(*val, qcncm->mode_val, + IPA_QCNCM_MODE_VAL_SHFT, + IPA_QCNCM_MODE_VAL_BMSK); + IPA_SETFIELD_IN_REG(*val, qcncm->undefined, + 0, IPA_QCNCM_MODE_VAL_BMSK); +} + +static void ipareg_parse_qcncm( + enum ipahal_reg_name reg, void *fields, u32 val) +{ + struct ipahal_reg_qcncm *qcncm = + (struct ipahal_reg_qcncm *)fields; + + memset(qcncm, 0, sizeof(struct ipahal_reg_qcncm)); + qcncm->mode_en = IPA_GETFIELD_FROM_REG(val, + IPA_QCNCM_MODE_EN_SHFT, + IPA_QCNCM_MODE_EN_BMSK); + qcncm->mode_val = IPA_GETFIELD_FROM_REG(val, + IPA_QCNCM_MODE_VAL_SHFT, + IPA_QCNCM_MODE_VAL_BMSK); + qcncm->undefined = IPA_GETFIELD_FROM_REG(val, + 0, IPA_QCNCM_UNDEFINED1_BMSK); + qcncm->undefined |= IPA_GETFIELD_FROM_REG(val, + 0, IPA_QCNCM_MODE_UNDEFINED2_BMSK); +} + +static void ipareg_construct_single_ndp_mode( + enum ipahal_reg_name reg, const void *fields, u32 *val) +{ + struct ipahal_reg_single_ndp_mode *mode = + (struct ipahal_reg_single_ndp_mode *)fields; + + IPA_SETFIELD_IN_REG(*val, mode->single_ndp_en ? 1 : 0, + IPA_SINGLE_NDP_MODE_SINGLE_NDP_EN_SHFT, + IPA_SINGLE_NDP_MODE_SINGLE_NDP_EN_BMSK); + + IPA_SETFIELD_IN_REG(*val, mode->undefined, + IPA_SINGLE_NDP_MODE_UNDEFINED_SHFT, + IPA_SINGLE_NDP_MODE_UNDEFINED_BMSK); +} + +static void ipareg_parse_single_ndp_mode( + enum ipahal_reg_name reg, void *fields, u32 val) +{ + struct ipahal_reg_single_ndp_mode *mode = + (struct ipahal_reg_single_ndp_mode *)fields; + + memset(mode, 0, sizeof(struct ipahal_reg_single_ndp_mode)); + mode->single_ndp_en = IPA_GETFIELD_FROM_REG(val, + IPA_SINGLE_NDP_MODE_SINGLE_NDP_EN_SHFT, + IPA_SINGLE_NDP_MODE_SINGLE_NDP_EN_BMSK); + mode->undefined = IPA_GETFIELD_FROM_REG(val, + IPA_SINGLE_NDP_MODE_UNDEFINED_SHFT, + IPA_SINGLE_NDP_MODE_UNDEFINED_BMSK); +} + +static void ipareg_construct_debug_cnt_ctrl_n( + enum ipahal_reg_name reg, const void *fields, u32 *val) +{ + struct ipahal_reg_debug_cnt_ctrl *dbg_cnt_ctrl = + (struct ipahal_reg_debug_cnt_ctrl *)fields; + u8 type; + + IPA_SETFIELD_IN_REG(*val, dbg_cnt_ctrl->en ? 1 : 0, + IPA_DEBUG_CNT_CTRL_n_DBG_CNT_EN_SHFT, + IPA_DEBUG_CNT_CTRL_n_DBG_CNT_EN_BMSK); + + switch (dbg_cnt_ctrl->type) { + case DBG_CNT_TYPE_IPV4_FLTR: + type = 0x0; + if (!dbg_cnt_ctrl->rule_idx_pipe_rule) { + IPAHAL_ERR("No FLT global rules\n"); + WARN_ON(1); + } + break; + case DBG_CNT_TYPE_IPV4_ROUT: + type = 0x1; + break; + case DBG_CNT_TYPE_GENERAL: + type = 0x2; + break; + case DBG_CNT_TYPE_IPV6_FLTR: + type = 0x4; + if (!dbg_cnt_ctrl->rule_idx_pipe_rule) { + IPAHAL_ERR("No FLT global rules\n"); + WARN_ON(1); + } + break; + case DBG_CNT_TYPE_IPV6_ROUT: + type = 0x5; + break; + default: + IPAHAL_ERR("Invalid dbg_cnt_ctrl type (%d) for %s\n", + dbg_cnt_ctrl->type, ipahal_reg_name_str(reg)); + WARN_ON(1); + return; + + } + + IPA_SETFIELD_IN_REG(*val, type, + IPA_DEBUG_CNT_CTRL_n_DBG_CNT_TYPE_SHFT, + IPA_DEBUG_CNT_CTRL_n_DBG_CNT_TYPE_BMSK); + + IPA_SETFIELD_IN_REG(*val, dbg_cnt_ctrl->product ? 1 : 0, + IPA_DEBUG_CNT_CTRL_n_DBG_CNT_PRODUCT_SHFT, + IPA_DEBUG_CNT_CTRL_n_DBG_CNT_PRODUCT_BMSK); + + IPA_SETFIELD_IN_REG(*val, dbg_cnt_ctrl->src_pipe, + IPA_DEBUG_CNT_CTRL_n_DBG_CNT_SOURCE_PIPE_SHFT, + IPA_DEBUG_CNT_CTRL_n_DBG_CNT_SOURCE_PIPE_BMSK); + + if (ipahal_ctx->hw_type <= IPA_HW_v3_1) { + IPA_SETFIELD_IN_REG(*val, dbg_cnt_ctrl->rule_idx, + IPA_DEBUG_CNT_CTRL_n_DBG_CNT_RULE_INDEX_SHFT, + IPA_DEBUG_CNT_CTRL_n_DBG_CNT_RULE_INDEX_BMSK); + IPA_SETFIELD_IN_REG(*val, dbg_cnt_ctrl->rule_idx_pipe_rule, + IPA_DEBUG_CNT_CTRL_n_DBG_CNT_RULE_INDEX_PIPE_RULE_SHFT, + IPA_DEBUG_CNT_CTRL_n_DBG_CNT_RULE_INDEX_PIPE_RULE_BMSK + ); + } else { + IPA_SETFIELD_IN_REG(*val, dbg_cnt_ctrl->rule_idx, + IPA_DEBUG_CNT_CTRL_n_DBG_CNT_RULE_INDEX_SHFT, + IPA_DEBUG_CNT_CTRL_n_DBG_CNT_RULE_INDEX_BMSK_V3_5); + } +} + +static void ipareg_parse_shared_mem_size( + enum ipahal_reg_name reg, void *fields, u32 val) +{ + struct ipahal_reg_shared_mem_size *smem_sz = + (struct ipahal_reg_shared_mem_size *)fields; + + memset(smem_sz, 0, sizeof(struct ipahal_reg_shared_mem_size)); + smem_sz->shared_mem_sz = IPA_GETFIELD_FROM_REG(val, + IPA_SHARED_MEM_SIZE_SHARED_MEM_SIZE_SHFT, + IPA_SHARED_MEM_SIZE_SHARED_MEM_SIZE_BMSK); + + smem_sz->shared_mem_baddr = IPA_GETFIELD_FROM_REG(val, + IPA_SHARED_MEM_SIZE_SHARED_MEM_BADDR_SHFT, + IPA_SHARED_MEM_SIZE_SHARED_MEM_BADDR_BMSK); +} + +static void ipareg_construct_endp_init_rsrc_grp_n( + enum ipahal_reg_name reg, const void *fields, u32 *val) +{ + struct ipahal_reg_endp_init_rsrc_grp *rsrc_grp = + (struct ipahal_reg_endp_init_rsrc_grp *)fields; + + IPA_SETFIELD_IN_REG(*val, rsrc_grp->rsrc_grp, + IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_SHFT, + IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_BMSK); +} + +static void ipareg_construct_endp_init_rsrc_grp_n_v3_5( + enum ipahal_reg_name reg, const void *fields, u32 *val) +{ + struct ipahal_reg_endp_init_rsrc_grp *rsrc_grp = + (struct ipahal_reg_endp_init_rsrc_grp *)fields; + + IPA_SETFIELD_IN_REG(*val, rsrc_grp->rsrc_grp, + IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_SHFT_v3_5, + IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_BMSK_v3_5); +} + +static void ipareg_construct_endp_init_rsrc_grp_n_v4_5( + enum ipahal_reg_name reg, const void *fields, u32 *val) +{ + struct ipahal_reg_endp_init_rsrc_grp *rsrc_grp = + (struct ipahal_reg_endp_init_rsrc_grp *)fields; + + IPA_SETFIELD_IN_REG(*val, rsrc_grp->rsrc_grp, + IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_SHFT_v4_5, + IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_BMSK_v4_5); +} + +static void ipareg_construct_endp_init_rsrc_grp_n_v4_9( + enum ipahal_reg_name reg, const void *fields, u32 *val) +{ + struct ipahal_reg_endp_init_rsrc_grp *rsrc_grp = + (struct ipahal_reg_endp_init_rsrc_grp *)fields; + + IPA_SETFIELD_IN_REG(*val, rsrc_grp->rsrc_grp, + IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_SHFT_v4_9, + IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_BMSK_v4_9); +} + +static void ipareg_construct_endp_init_rsrc_grp_n_v5_0( + enum ipahal_reg_name reg, const void *fields, u32 *val) +{ + struct ipahal_reg_endp_init_rsrc_grp *rsrc_grp = + (struct ipahal_reg_endp_init_rsrc_grp *)fields; + + IPA_SETFIELD_IN_REG(*val, rsrc_grp->rsrc_grp, + IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_SHFT_v5_0, + IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_BMSK_v5_0); +} + +static void ipareg_construct_endp_init_hdr_metadata_n( + enum ipahal_reg_name reg, const void *fields, u32 *val) +{ + struct ipa_ep_cfg_metadata *metadata = + (struct ipa_ep_cfg_metadata *)fields; + + IPA_SETFIELD_IN_REG(*val, metadata->qmap_id, + IPA_ENDP_INIT_HDR_METADATA_n_METADATA_SHFT, + IPA_ENDP_INIT_HDR_METADATA_n_METADATA_BMSK); +} + +static void ipareg_construct_endp_init_hdr_metadata_mask_n( + enum ipahal_reg_name reg, const void *fields, u32 *val) +{ + struct ipa_ep_cfg_metadata_mask *metadata_mask = + (struct ipa_ep_cfg_metadata_mask *)fields; + + IPA_SETFIELD_IN_REG(*val, metadata_mask->metadata_mask, + IPA_ENDP_INIT_HDR_METADATA_MASK_n_METADATA_MASK_SHFT, + IPA_ENDP_INIT_HDR_METADATA_MASK_n_METADATA_MASK_BMSK); +} + +static void ipareg_construct_endp_init_cfg_n( + enum ipahal_reg_name reg, const void *fields, u32 *val) +{ + struct ipa_ep_cfg_cfg *cfg = + (struct ipa_ep_cfg_cfg *)fields; + u32 cs_offload_en; + + switch (cfg->cs_offload_en) { + case IPA_DISABLE_CS_OFFLOAD: + cs_offload_en = 0; + break; + case IPA_ENABLE_CS_OFFLOAD_UL: + cs_offload_en = 1; + break; + case IPA_ENABLE_CS_OFFLOAD_DL: + cs_offload_en = 2; + break; + default: + IPAHAL_ERR("Invalid cs_offload_en value for %s\n", + ipahal_reg_name_str(reg)); + WARN_ON(1); + return; + } + + IPA_SETFIELD_IN_REG(*val, cfg->frag_offload_en ? 1 : 0, + IPA_ENDP_INIT_CFG_n_FRAG_OFFLOAD_EN_SHFT, + IPA_ENDP_INIT_CFG_n_FRAG_OFFLOAD_EN_BMSK); + IPA_SETFIELD_IN_REG(*val, cs_offload_en, + IPA_ENDP_INIT_CFG_n_CS_OFFLOAD_EN_SHFT, + IPA_ENDP_INIT_CFG_n_CS_OFFLOAD_EN_BMSK); + IPA_SETFIELD_IN_REG(*val, cfg->cs_metadata_hdr_offset, + IPA_ENDP_INIT_CFG_n_CS_METADATA_HDR_OFFSET_SHFT, + IPA_ENDP_INIT_CFG_n_CS_METADATA_HDR_OFFSET_BMSK); + IPA_SETFIELD_IN_REG(*val, cfg->gen_qmb_master_sel, + IPA_ENDP_INIT_CFG_n_CS_GEN_QMB_MASTER_SEL_SHFT, + IPA_ENDP_INIT_CFG_n_CS_GEN_QMB_MASTER_SEL_BMSK); + if (ipahal_ctx->hw_type >= IPA_HW_v5_5) + IPA_SETFIELD_IN_REG(*val, cfg->pipe_replicate_en, + IPA_ENDP_INIT_CFG_n_PIPE_REPLICATE_EN_SEL_SHFT_V5_5, + IPA_ENDP_INIT_CFG_n_PIPE_REPLICATE_EN_SEL_BMSK_V5_5); +} + +static void ipareg_construct_endp_init_prod_cfg_n_v5_5( + enum ipahal_reg_name reg, const void *fields, u32 *val) +{ + struct ipa_ep_cfg_prod_cfg *cfg = + (struct ipa_ep_cfg_prod_cfg *)fields; + + IPA_SETFIELD_IN_REG(*val, cfg->tx_instance ? 1 : 0, + IPA_ENDP_INIT_PROD_CFG_n_TX_SEL_SHIFT, + IPA_ENDP_INIT_PROD_CFG_n_TX_SEL_BMASK); + IPA_SETFIELD_IN_REG(*val, cfg->tsp_enable ? 1 : 0, + IPA_ENDP_INIT_PROD_CFG_n_TSP_ENABLE_SHIFT, + IPA_ENDP_INIT_PROD_CFG_n_TSP_ENABLE_BMASK); + IPA_SETFIELD_IN_REG(*val, cfg->max_output_size_drop_enable ? 1 : 0, + IPA_ENDP_INIT_PROD_CFG_n_MAX_OUTPUT_SIZE_DROP_ENABLE_SHIFT, + IPA_ENDP_INIT_PROD_CFG_n_MAX_OUTPUT_SIZE_DROP_ENABLE_BMASK); + IPA_SETFIELD_IN_REG(*val, cfg->tsp_idx, + IPA_ENDP_INIT_PROD_CFG_n_TSP_INDEX_SHIFT, + IPA_ENDP_INIT_PROD_CFG_n_TSP_INDEX_BMASK); + IPA_SETFIELD_IN_REG(*val, cfg->max_output_size, + IPA_ENDP_INIT_PROD_CFG_n_MAX_OUTPUT_SIZE_SHIFT, + IPA_ENDP_INIT_PROD_CFG_n_MAX_OUTPUT_SIZE_BMASK); + IPA_SETFIELD_IN_REG(*val, cfg->egress_tc_lowest, + IPA_ENDP_INIT_PROD_CFG_n_EGRESS_TC_LOWEST_SHIFT, + IPA_ENDP_INIT_PROD_CFG_n_EGRESS_TC_LOWEST_BMASK); + IPA_SETFIELD_IN_REG(*val, cfg->egress_tc_highest, + IPA_ENDP_INIT_PROD_CFG_n_EGRESS_TC_HIGHEST_SHIFT, + IPA_ENDP_INIT_PROD_CFG_n_EGRESS_TC_HIGHEST_BMASK); +} + +static void ipareg_parse_endp_init_prod_cfg_n_v5_5(enum ipahal_reg_name reg, + void *fields, u32 val) +{ + struct ipa_ep_cfg_prod_cfg *cfg = + (struct ipa_ep_cfg_prod_cfg *)fields; + + cfg->tx_instance = + ((val & IPA_ENDP_INIT_PROD_CFG_n_TX_SEL_BMASK) >> + IPA_ENDP_INIT_PROD_CFG_n_TX_SEL_SHIFT); + cfg->tsp_enable = + ((val & IPA_ENDP_INIT_PROD_CFG_n_TSP_ENABLE_BMASK) >> + IPA_ENDP_INIT_PROD_CFG_n_TSP_ENABLE_SHIFT); + cfg->max_output_size_drop_enable = + ((val & IPA_ENDP_INIT_PROD_CFG_n_MAX_OUTPUT_SIZE_DROP_ENABLE_BMASK) >> + IPA_ENDP_INIT_PROD_CFG_n_MAX_OUTPUT_SIZE_DROP_ENABLE_SHIFT); + cfg->tsp_idx = + ((val & IPA_ENDP_INIT_PROD_CFG_n_TSP_INDEX_BMASK) >> + IPA_ENDP_INIT_PROD_CFG_n_TSP_INDEX_SHIFT); + cfg->max_output_size = + ((val & IPA_ENDP_INIT_PROD_CFG_n_MAX_OUTPUT_SIZE_BMASK) >> + IPA_ENDP_INIT_PROD_CFG_n_MAX_OUTPUT_SIZE_SHIFT); + cfg->egress_tc_lowest = + ((val & IPA_ENDP_INIT_PROD_CFG_n_EGRESS_TC_LOWEST_BMASK) >> + IPA_ENDP_INIT_PROD_CFG_n_EGRESS_TC_LOWEST_SHIFT); + cfg->egress_tc_highest = + ((val & IPA_ENDP_INIT_PROD_CFG_n_EGRESS_TC_HIGHEST_BMASK) >> + IPA_ENDP_INIT_PROD_CFG_n_EGRESS_TC_HIGHEST_SHIFT); +} + +static void ipareg_construct_endp_init_deaggr_n( + enum ipahal_reg_name reg, const void *fields, u32 *val) +{ + struct ipa_ep_cfg_deaggr *ep_deaggr = + (struct ipa_ep_cfg_deaggr *)fields; + + IPA_SETFIELD_IN_REG(*val, ep_deaggr->deaggr_hdr_len, + IPA_ENDP_INIT_DEAGGR_n_DEAGGR_HDR_LEN_SHFT, + IPA_ENDP_INIT_DEAGGR_n_DEAGGR_HDR_LEN_BMSK); + + IPA_SETFIELD_IN_REG(*val, ep_deaggr->packet_offset_valid, + IPA_ENDP_INIT_DEAGGR_n_PACKET_OFFSET_VALID_SHFT, + IPA_ENDP_INIT_DEAGGR_n_PACKET_OFFSET_VALID_BMSK); + + IPA_SETFIELD_IN_REG(*val, ep_deaggr->packet_offset_location, + IPA_ENDP_INIT_DEAGGR_n_PACKET_OFFSET_LOCATION_SHFT, + IPA_ENDP_INIT_DEAGGR_n_PACKET_OFFSET_LOCATION_BMSK); + + IPA_SETFIELD_IN_REG(*val, ep_deaggr->max_packet_len, + IPA_ENDP_INIT_DEAGGR_n_MAX_PACKET_LEN_SHFT, + IPA_ENDP_INIT_DEAGGR_n_MAX_PACKET_LEN_BMSK); +} + +static void ipareg_construct_endp_init_deaggr_n_v4_5( + enum ipahal_reg_name reg, const void *fields, u32 *val) +{ + struct ipa_ep_cfg_deaggr *ep_deaggr = + (struct ipa_ep_cfg_deaggr *)fields; + + IPA_SETFIELD_IN_REG(*val, ep_deaggr->deaggr_hdr_len, + IPA_ENDP_INIT_DEAGGR_n_DEAGGR_HDR_LEN_SHFT, + IPA_ENDP_INIT_DEAGGR_n_DEAGGR_HDR_LEN_BMSK); + + IPA_SETFIELD_IN_REG(*val, ep_deaggr->syspipe_err_detection, + IPA_ENDP_INIT_DEAGGR_n_SYSPIPE_ERR_DETECTION_SHFT, + IPA_ENDP_INIT_DEAGGR_n_SYSPIPE_ERR_DETECTION_BMSK); + + IPA_SETFIELD_IN_REG(*val, ep_deaggr->packet_offset_valid, + IPA_ENDP_INIT_DEAGGR_n_PACKET_OFFSET_VALID_SHFT, + IPA_ENDP_INIT_DEAGGR_n_PACKET_OFFSET_VALID_BMSK); + + IPA_SETFIELD_IN_REG(*val, ep_deaggr->packet_offset_location, + IPA_ENDP_INIT_DEAGGR_n_PACKET_OFFSET_LOCATION_SHFT, + IPA_ENDP_INIT_DEAGGR_n_PACKET_OFFSET_LOCATION_BMSK); + + IPA_SETFIELD_IN_REG(*val, ep_deaggr->ignore_min_pkt_err, + IPA_ENDP_INIT_DEAGGR_n_IGNORE_MIN_PKT_ERR_SHFT, + IPA_ENDP_INIT_DEAGGR_n_IGNORE_MIN_PKT_ERR_BMSK); + + IPA_SETFIELD_IN_REG(*val, ep_deaggr->max_packet_len, + IPA_ENDP_INIT_DEAGGR_n_MAX_PACKET_LEN_SHFT, + IPA_ENDP_INIT_DEAGGR_n_MAX_PACKET_LEN_BMSK); +} + +static void ipareg_construct_endp_init_hol_block_en_n( + enum ipahal_reg_name reg, const void *fields, u32 *val) +{ + struct ipa_ep_cfg_holb *ep_holb = + (struct ipa_ep_cfg_holb *)fields; + + IPA_SETFIELD_IN_REG(*val, ep_holb->en, + IPA_ENDP_INIT_HOL_BLOCK_EN_n_EN_SHFT, + IPA_ENDP_INIT_HOL_BLOCK_EN_n_EN_BMSK); +} + +static void ipareg_construct_endp_init_hol_block_timer_n( + enum ipahal_reg_name reg, const void *fields, u32 *val) +{ + struct ipa_ep_cfg_holb *ep_holb = + (struct ipa_ep_cfg_holb *)fields; + + IPA_SETFIELD_IN_REG(*val, ep_holb->tmr_val, + IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_TIMER_SHFT, + IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_TIMER_BMSK); +} + + +static void ipareg_construct_endp_init_hol_block_timer_n_v4_2( + enum ipahal_reg_name reg, const void *fields, u32 *val) +{ + struct ipa_ep_cfg_holb *ep_holb = + (struct ipa_ep_cfg_holb *)fields; + + IPA_SETFIELD_IN_REG(*val, ep_holb->scale, + IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_SCALE_SHFT_V_4_2, + IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_SCALE_BMSK_V_4_2); + IPA_SETFIELD_IN_REG(*val, ep_holb->base_val, + IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_BASE_VALUE_SHFT_V_4_2, + IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_BASE_VALUE_BMSK_V_4_2); +} + +static void ipareg_construct_endp_init_hol_block_timer_n_v4_5( + enum ipahal_reg_name reg, const void *fields, u32 *val) +{ + struct ipa_ep_cfg_holb *ep_holb = + (struct ipa_ep_cfg_holb *)fields; + + if (ep_holb->pulse_generator != !!ep_holb->pulse_generator) { + IPAHAL_ERR("Pulse generator is not 0 or 1 %d\n", + ep_holb->pulse_generator); + WARN_ON(1); + } + + IPA_SETFIELD_IN_REG(*val, ep_holb->scaled_time, + IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_TIME_LIMIT_SHFT_V4_5, + IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_TIME_LIMIT_BMSK_V4_5); + + IPA_SETFIELD_IN_REG(*val, ep_holb->pulse_generator, + IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_GRAN_SEL_SHFT_V4_5, + IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_GRAN_SEL_BMSK_V4_5); +} + +static void ipareg_construct_endp_init_hol_block_timer_n_v5_0( + enum ipahal_reg_name reg, const void *fields, u32 *val) +{ + struct ipa_ep_cfg_holb *ep_holb = + (struct ipa_ep_cfg_holb *)fields; + + IPA_SETFIELD_IN_REG(*val, ep_holb->scaled_time, + IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_TIME_LIMIT_SHFT_V5_0, + IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_TIME_LIMIT_BMSK_V5_0); + + IPA_SETFIELD_IN_REG(*val, ep_holb->pulse_generator, + IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_GRAN_SEL_SHFT_V5_0, + IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_GRAN_SEL_BMSK_V5_0); +} + +static void ipareg_construct_endp_init_ctrl_n(enum ipahal_reg_name reg, + const void *fields, u32 *val) +{ + struct ipa_ep_cfg_ctrl *ep_ctrl = + (struct ipa_ep_cfg_ctrl *)fields; + + IPA_SETFIELD_IN_REG(*val, ep_ctrl->ipa_ep_suspend, + IPA_ENDP_INIT_CTRL_n_ENDP_SUSPEND_SHFT, + IPA_ENDP_INIT_CTRL_n_ENDP_SUSPEND_BMSK); + + IPA_SETFIELD_IN_REG(*val, ep_ctrl->ipa_ep_delay, + IPA_ENDP_INIT_CTRL_n_ENDP_DELAY_SHFT, + IPA_ENDP_INIT_CTRL_n_ENDP_DELAY_BMSK); +} + +static void ipareg_parse_endp_init_ctrl_n(enum ipahal_reg_name reg, + void *fields, u32 val) +{ + struct ipa_ep_cfg_ctrl *ep_ctrl = + (struct ipa_ep_cfg_ctrl *)fields; + + ep_ctrl->ipa_ep_suspend = + ((val & IPA_ENDP_INIT_CTRL_n_ENDP_SUSPEND_BMSK) >> + IPA_ENDP_INIT_CTRL_n_ENDP_SUSPEND_SHFT); + + ep_ctrl->ipa_ep_delay = + ((val & IPA_ENDP_INIT_CTRL_n_ENDP_DELAY_BMSK) >> + IPA_ENDP_INIT_CTRL_n_ENDP_DELAY_SHFT); +} + +static void ipareg_construct_endp_init_ctrl_n_v4_0(enum ipahal_reg_name reg, + const void *fields, u32 *val) +{ + struct ipa_ep_cfg_ctrl *ep_ctrl = + (struct ipa_ep_cfg_ctrl *)fields; + + WARN_ON(ep_ctrl->ipa_ep_suspend); + + IPA_SETFIELD_IN_REG(*val, ep_ctrl->ipa_ep_delay, + IPA_ENDP_INIT_CTRL_n_ENDP_DELAY_SHFT, + IPA_ENDP_INIT_CTRL_n_ENDP_DELAY_BMSK); +} + +static void ipareg_construct_endp_init_ctrl_scnd_n(enum ipahal_reg_name reg, + const void *fields, u32 *val) +{ + struct ipahal_ep_cfg_ctrl_scnd *ep_ctrl_scnd = + (struct ipahal_ep_cfg_ctrl_scnd *)fields; + + IPA_SETFIELD_IN_REG(*val, ep_ctrl_scnd->endp_delay, + IPA_ENDP_INIT_CTRL_SCND_n_ENDP_DELAY_SHFT, + IPA_ENDP_INIT_CTRL_SCND_n_ENDP_DELAY_BMSK); +} + +static void ipareg_construct_endp_init_nat_n(enum ipahal_reg_name reg, + const void *fields, u32 *val) +{ + struct ipa_ep_cfg_nat *ep_nat = + (struct ipa_ep_cfg_nat *)fields; + + IPA_SETFIELD_IN_REG(*val, ep_nat->nat_en, + IPA_ENDP_INIT_NAT_n_NAT_EN_SHFT, + IPA_ENDP_INIT_NAT_n_NAT_EN_BMSK); +} + +static void ipareg_construct_endp_init_nat_exc_suppress_n +( + enum ipahal_reg_name reg, + const void *fields, u32 *val +) +{ + struct ipa_ep_cfg_nat *ep_nat = + (struct ipa_ep_cfg_nat *)fields; + + IPA_SETFIELD_IN_REG(*val, ep_nat->nat_exc_suppress ? 1 : 0, + IPA_ENDP_INIT_NAT_EXC_SUPPRESS_n_EN_SHFT, + IPA_ENDP_INIT_NAT_EXC_SUPPRESS_n_EN_BMSK); +} + +static void ipareg_construct_endp_init_conn_track_n(enum ipahal_reg_name reg, + const void *fields, u32 *val) +{ + struct ipa_ep_cfg_conn_track *ep_ipv6ct = + (struct ipa_ep_cfg_conn_track *)fields; + + IPA_SETFIELD_IN_REG(*val, ep_ipv6ct->conn_track_en, + IPA_ENDP_INIT_CONN_TRACK_n_CONN_TRACK_EN_SHFT, + IPA_ENDP_INIT_CONN_TRACK_n_CONN_TRACK_EN_BMSK); +} + +static void ipareg_construct_endp_init_mode_n(enum ipahal_reg_name reg, + const void *fields, u32 *val) +{ + struct ipahal_reg_endp_init_mode *init_mode = + (struct ipahal_reg_endp_init_mode *)fields; + + IPA_SETFIELD_IN_REG(*val, init_mode->ep_mode.mode, + IPA_ENDP_INIT_MODE_n_MODE_SHFT, + IPA_ENDP_INIT_MODE_n_MODE_BMSK); + + IPA_SETFIELD_IN_REG(*val, init_mode->dst_pipe_number, + IPA_ENDP_INIT_MODE_n_DEST_PIPE_INDEX_SHFT, + IPA_ENDP_INIT_MODE_n_DEST_PIPE_INDEX_BMSK); +} + +static void ipareg_construct_endp_init_mode_n_v4_5(enum ipahal_reg_name reg, + const void *fields, u32 *val) +{ + struct ipahal_reg_endp_init_mode *init_mode = + (struct ipahal_reg_endp_init_mode *)fields; + + IPA_SETFIELD_IN_REG(*val, init_mode->ep_mode.mode, + IPA_ENDP_INIT_MODE_n_MODE_SHFT_V4_5, + IPA_ENDP_INIT_MODE_n_MODE_BMSK_V4_5); + + IPA_SETFIELD_IN_REG(*val, init_mode->dst_pipe_number, + IPA_ENDP_INIT_MODE_n_DEST_PIPE_INDEX_SHFT_V4_5, + IPA_ENDP_INIT_MODE_n_DEST_PIPE_INDEX_BMSK_V4_5); +} + +static void ipareg_construct_endp_init_mode_n_v5_0(enum ipahal_reg_name reg, + const void *fields, u32 *val) +{ + struct ipahal_reg_endp_init_mode *init_mode = + (struct ipahal_reg_endp_init_mode *)fields; + + IPA_SETFIELD_IN_REG(*val, init_mode->ep_mode.mode, + IPA_ENDP_INIT_MODE_n_MODE_SHFT_V4_5, + IPA_ENDP_INIT_MODE_n_MODE_BMSK_V4_5); + + IPA_SETFIELD_IN_REG(*val, init_mode->dst_pipe_number, + IPA_ENDP_INIT_MODE_n_DEST_PIPE_INDEX_SHFT_V5_0, + IPA_ENDP_INIT_MODE_n_DEST_PIPE_INDEX_BMSK_V5_0); +} + +static void ipareg_construct_endp_init_route_n(enum ipahal_reg_name reg, + const void *fields, u32 *val) +{ + struct ipahal_reg_endp_init_route *ep_init_rt = + (struct ipahal_reg_endp_init_route *)fields; + + IPA_SETFIELD_IN_REG(*val, ep_init_rt->route_table_index, + IPA_ENDP_INIT_ROUTE_n_ROUTE_TABLE_INDEX_SHFT, + IPA_ENDP_INIT_ROUTE_n_ROUTE_TABLE_INDEX_BMSK); + +} + +static void ipareg_parse_endp_init_aggr_n(enum ipahal_reg_name reg, + void *fields, u32 val) +{ + struct ipa_ep_cfg_aggr *ep_aggr = + (struct ipa_ep_cfg_aggr *)fields; + + memset(ep_aggr, 0, sizeof(struct ipa_ep_cfg_aggr)); + + ep_aggr->aggr_en = + (((val & IPA_ENDP_INIT_AGGR_n_AGGR_EN_BMSK) >> + IPA_ENDP_INIT_AGGR_n_AGGR_EN_SHFT) + == IPA_ENABLE_AGGR); + ep_aggr->aggr = + ((val & IPA_ENDP_INIT_AGGR_n_AGGR_TYPE_BMSK) >> + IPA_ENDP_INIT_AGGR_n_AGGR_TYPE_SHFT); + ep_aggr->aggr_byte_limit = + ((val & IPA_ENDP_INIT_AGGR_n_AGGR_BYTE_LIMIT_BMSK) >> + IPA_ENDP_INIT_AGGR_n_AGGR_BYTE_LIMIT_SHFT); + ep_aggr->aggr_time_limit = + ((val & IPA_ENDP_INIT_AGGR_n_AGGR_TIME_LIMIT_BMSK) >> + IPA_ENDP_INIT_AGGR_n_AGGR_TIME_LIMIT_SHFT); + ep_aggr->aggr_time_limit *= 1000; /* HW works in msec */ + ep_aggr->aggr_pkt_limit = + ((val & IPA_ENDP_INIT_AGGR_n_AGGR_PKT_LIMIT_BMSK) >> + IPA_ENDP_INIT_AGGR_n_AGGR_PKT_LIMIT_SHFT); + ep_aggr->aggr_sw_eof_active = + ((val & IPA_ENDP_INIT_AGGR_n_AGGR_SW_EOF_ACTIVE_BMSK) >> + IPA_ENDP_INIT_AGGR_n_AGGR_SW_EOF_ACTIVE_SHFT); + ep_aggr->aggr_hard_byte_limit_en = + ((val & IPA_ENDP_INIT_AGGR_n_AGGR_HARD_BYTE_LIMIT_ENABLE_BMSK) + >> + IPA_ENDP_INIT_AGGR_n_AGGR_HARD_BYTE_LIMIT_ENABLE_SHFT); +} + +static void ipareg_parse_endp_init_aggr_n_v4_5(enum ipahal_reg_name reg, + void *fields, u32 val) +{ + struct ipa_ep_cfg_aggr *ep_aggr = + (struct ipa_ep_cfg_aggr *)fields; + + memset(ep_aggr, 0, sizeof(struct ipa_ep_cfg_aggr)); + + ep_aggr->aggr_en = + (((val & IPA_ENDP_INIT_AGGR_n_AGGR_EN_BMSK_V4_5) >> + IPA_ENDP_INIT_AGGR_n_AGGR_EN_SHFT_V4_5) + == IPA_ENABLE_AGGR); + ep_aggr->aggr = + ((val & IPA_ENDP_INIT_AGGR_n_AGGR_TYPE_BMSK_V4_5) >> + IPA_ENDP_INIT_AGGR_n_AGGR_TYPE_SHFT_V4_5); + ep_aggr->aggr_byte_limit = + ((val & IPA_ENDP_INIT_AGGR_n_AGGR_BYTE_LIMIT_BMSK_V4_5) >> + IPA_ENDP_INIT_AGGR_n_AGGR_BYTE_LIMIT_SHFT_V4_5); + ep_aggr->scaled_time = + ((val & IPA_ENDP_INIT_AGGR_n_AGGR_TIME_LIMIT_BMSK_V4_5) >> + IPA_ENDP_INIT_AGGR_n_AGGR_TIME_LIMIT_SHFT_V4_5); + ep_aggr->aggr_pkt_limit = + ((val & IPA_ENDP_INIT_AGGR_n_AGGR_PKT_LIMIT_BMSK_V4_5) >> + IPA_ENDP_INIT_AGGR_n_AGGR_PKT_LIMIT_SHFT_V4_5); + ep_aggr->aggr_sw_eof_active = + ((val & IPA_ENDP_INIT_AGGR_n_AGGR_SW_EOF_ACTIVE_BMSK_V4_5) >> + IPA_ENDP_INIT_AGGR_n_AGGR_SW_EOF_ACTIVE_SHFT_V4_5); + ep_aggr->aggr_hard_byte_limit_en = + ((val & + IPA_ENDP_INIT_AGGR_n_AGGR_HARD_BYTE_LIMIT_ENABLE_BMSK_V4_5) + >> + IPA_ENDP_INIT_AGGR_n_AGGR_HARD_BYTE_LIMIT_ENABLE_SHFT_V4_5); + ep_aggr->pulse_generator = + ((val & IPA_ENDP_INIT_AGGR_n_AGGR_GRAN_SEL_BMSK_V4_5) >> + IPA_ENDP_INIT_AGGR_n_AGGR_GRAN_SEL_SHFT_V4_5); + + if (ipahal_ctx->hw_type >= IPA_HW_v5_5) + ep_aggr->aggr_coal_l2 = + ((val & IPA_ENDP_INIT_AGGR_n_AGGR_COAL_L2_BMSK_V5_5) >> + IPA_ENDP_INIT_AGGR_n_AGGR_COAL_L2_SHFT_V5_5); +} + +static void ipareg_construct_endp_init_aggr_n(enum ipahal_reg_name reg, + const void *fields, u32 *val) +{ + struct ipa_ep_cfg_aggr *ep_aggr = + (struct ipa_ep_cfg_aggr *)fields; + u32 byte_limit; + u32 pkt_limit; + u32 max_byte_limit; + u32 max_pkt_limit; + + IPA_SETFIELD_IN_REG(*val, ep_aggr->aggr_en, + IPA_ENDP_INIT_AGGR_n_AGGR_EN_SHFT, + IPA_ENDP_INIT_AGGR_n_AGGR_EN_BMSK); + + IPA_SETFIELD_IN_REG(*val, ep_aggr->aggr, + IPA_ENDP_INIT_AGGR_n_AGGR_TYPE_SHFT, + IPA_ENDP_INIT_AGGR_n_AGGR_TYPE_BMSK); + + /* make sure aggregation byte limit does not cross HW boundaries */ + max_byte_limit = IPA_ENDP_INIT_AGGR_n_AGGR_BYTE_LIMIT_BMSK >> + IPA_ENDP_INIT_AGGR_n_AGGR_BYTE_LIMIT_SHFT; + byte_limit = (ep_aggr->aggr_byte_limit > max_byte_limit) ? + max_byte_limit : ep_aggr->aggr_byte_limit; + IPA_SETFIELD_IN_REG(*val, byte_limit, + IPA_ENDP_INIT_AGGR_n_AGGR_BYTE_LIMIT_SHFT, + IPA_ENDP_INIT_AGGR_n_AGGR_BYTE_LIMIT_BMSK); + + /* HW works in msec */ + IPA_SETFIELD_IN_REG(*val, ep_aggr->aggr_time_limit / 1000, + IPA_ENDP_INIT_AGGR_n_AGGR_TIME_LIMIT_SHFT, + IPA_ENDP_INIT_AGGR_n_AGGR_TIME_LIMIT_BMSK); + + /* make sure aggregation pkt limit does not cross HW boundaries */ + max_pkt_limit = IPA_ENDP_INIT_AGGR_n_AGGR_PKT_LIMIT_BMSK >> + IPA_ENDP_INIT_AGGR_n_AGGR_PKT_LIMIT_SHFT; + pkt_limit = (ep_aggr->aggr_pkt_limit > max_pkt_limit) ? + max_pkt_limit : ep_aggr->aggr_pkt_limit; + IPA_SETFIELD_IN_REG(*val, pkt_limit, + IPA_ENDP_INIT_AGGR_n_AGGR_PKT_LIMIT_SHFT, + IPA_ENDP_INIT_AGGR_n_AGGR_PKT_LIMIT_BMSK); + + IPA_SETFIELD_IN_REG(*val, ep_aggr->aggr_sw_eof_active, + IPA_ENDP_INIT_AGGR_n_AGGR_SW_EOF_ACTIVE_SHFT, + IPA_ENDP_INIT_AGGR_n_AGGR_SW_EOF_ACTIVE_BMSK); + + /*IPA 3.5.1 and above target versions hard byte limit enable supported*/ + IPA_SETFIELD_IN_REG(*val, ep_aggr->aggr_hard_byte_limit_en, + IPA_ENDP_INIT_AGGR_n_AGGR_HARD_BYTE_LIMIT_ENABLE_SHFT, + IPA_ENDP_INIT_AGGR_n_AGGR_HARD_BYTE_LIMIT_ENABLE_BMSK); +} + +static void ipareg_construct_endp_init_aggr_n_v4_5(enum ipahal_reg_name reg, + const void *fields, u32 *val) +{ + struct ipa_ep_cfg_aggr *ep_aggr = + (struct ipa_ep_cfg_aggr *)fields; + u32 byte_limit; + u32 pkt_limit; + u32 max_byte_limit; + u32 max_pkt_limit; + + IPA_SETFIELD_IN_REG(*val, ep_aggr->aggr_en, + IPA_ENDP_INIT_AGGR_n_AGGR_EN_SHFT_V4_5, + IPA_ENDP_INIT_AGGR_n_AGGR_EN_BMSK_V4_5); + + IPA_SETFIELD_IN_REG(*val, ep_aggr->aggr, + IPA_ENDP_INIT_AGGR_n_AGGR_TYPE_SHFT_V4_5, + IPA_ENDP_INIT_AGGR_n_AGGR_TYPE_BMSK_V4_5); + + /* make sure aggregation byte limit does not cross HW boundaries */ + max_byte_limit = IPA_ENDP_INIT_AGGR_n_AGGR_BYTE_LIMIT_BMSK_V4_5 >> + IPA_ENDP_INIT_AGGR_n_AGGR_BYTE_LIMIT_SHFT_V4_5; + byte_limit = (ep_aggr->aggr_byte_limit > max_byte_limit) ? + max_byte_limit : ep_aggr->aggr_byte_limit; + IPA_SETFIELD_IN_REG(*val, byte_limit, + IPA_ENDP_INIT_AGGR_n_AGGR_BYTE_LIMIT_SHFT_V4_5, + IPA_ENDP_INIT_AGGR_n_AGGR_BYTE_LIMIT_BMSK_V4_5); + + IPA_SETFIELD_IN_REG(*val, ep_aggr->scaled_time, + IPA_ENDP_INIT_AGGR_n_AGGR_TIME_LIMIT_SHFT_V4_5, + IPA_ENDP_INIT_AGGR_n_AGGR_TIME_LIMIT_BMSK_V4_5); + + /* make sure aggregation pkt limit does not cross HW boundaries */ + max_pkt_limit = IPA_ENDP_INIT_AGGR_n_AGGR_PKT_LIMIT_BMSK_V4_5 >> + IPA_ENDP_INIT_AGGR_n_AGGR_PKT_LIMIT_SHFT_V4_5; + pkt_limit = (ep_aggr->aggr_pkt_limit > max_pkt_limit) ? + max_pkt_limit : ep_aggr->aggr_pkt_limit; + IPA_SETFIELD_IN_REG(*val, ep_aggr->aggr_pkt_limit, + IPA_ENDP_INIT_AGGR_n_AGGR_PKT_LIMIT_SHFT_V4_5, + IPA_ENDP_INIT_AGGR_n_AGGR_PKT_LIMIT_BMSK_V4_5); + + IPA_SETFIELD_IN_REG(*val, ep_aggr->aggr_sw_eof_active, + IPA_ENDP_INIT_AGGR_n_AGGR_SW_EOF_ACTIVE_SHFT_V4_5, + IPA_ENDP_INIT_AGGR_n_AGGR_SW_EOF_ACTIVE_BMSK_V4_5); + + IPA_SETFIELD_IN_REG(*val, ep_aggr->aggr_hard_byte_limit_en, + IPA_ENDP_INIT_AGGR_n_AGGR_HARD_BYTE_LIMIT_ENABLE_SHFT_V4_5, + IPA_ENDP_INIT_AGGR_n_AGGR_HARD_BYTE_LIMIT_ENABLE_BMSK_V4_5); + + IPA_SETFIELD_IN_REG(*val, ep_aggr->pulse_generator, + IPA_ENDP_INIT_AGGR_n_AGGR_GRAN_SEL_SHFT_V4_5, + IPA_ENDP_INIT_AGGR_n_AGGR_GRAN_SEL_BMSK_V4_5); + + if (ipahal_ctx->hw_type >= IPA_HW_v5_5) + IPA_SETFIELD_IN_REG(*val, ep_aggr->aggr_coal_l2, + IPA_ENDP_INIT_AGGR_n_AGGR_COAL_L2_SHFT_V5_5, + IPA_ENDP_INIT_AGGR_n_AGGR_COAL_L2_BMSK_V5_5); +} + +static void ipareg_construct_endp_init_hdr_ext_n_common( + const struct ipa_ep_cfg_hdr_ext *ep_hdr_ext, u32 *val) +{ + u8 hdr_endianness; + + hdr_endianness = ep_hdr_ext->hdr_little_endian ? 0 : 1; + IPA_SETFIELD_IN_REG(*val, ep_hdr_ext->hdr_pad_to_alignment, + IPA_ENDP_INIT_HDR_EXT_n_HDR_PAD_TO_ALIGNMENT_SHFT, + IPA_ENDP_INIT_HDR_EXT_n_HDR_PAD_TO_ALIGNMENT_BMSK); + + IPA_SETFIELD_IN_REG(*val, ep_hdr_ext->hdr_total_len_or_pad_offset, + IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_OFFSET_SHFT, + IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_OFFSET_BMSK); + + IPA_SETFIELD_IN_REG(*val, ep_hdr_ext->hdr_payload_len_inc_padding, + IPA_ENDP_INIT_HDR_EXT_n_HDR_PAYLOAD_LEN_INC_PADDING_SHFT, + IPA_ENDP_INIT_HDR_EXT_n_HDR_PAYLOAD_LEN_INC_PADDING_BMSK); + + IPA_SETFIELD_IN_REG(*val, ep_hdr_ext->hdr_total_len_or_pad, + IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_SHFT, + IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_BMSK); + + IPA_SETFIELD_IN_REG(*val, ep_hdr_ext->hdr_total_len_or_pad_valid, + IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_VALID_SHFT, + IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_VALID_BMSK); + + IPA_SETFIELD_IN_REG(*val, hdr_endianness, + IPA_ENDP_INIT_HDR_EXT_n_HDR_ENDIANNESS_SHFT, + IPA_ENDP_INIT_HDR_EXT_n_HDR_ENDIANNESS_BMSK); +} + +static void ipareg_construct_endp_init_hdr_ext_n(enum ipahal_reg_name reg, + const void *fields, u32 *val) +{ + ipareg_construct_endp_init_hdr_ext_n_common(fields, val); +} + +static void ipareg_construct_endp_init_hdr_ext_n_v4_5(enum ipahal_reg_name reg, + const void *fields, u32 *val) +{ + const struct ipa_ep_cfg_hdr_ext *ep_hdr_ext = + (const struct ipa_ep_cfg_hdr_ext *)fields; + u32 msb; + + ipareg_construct_endp_init_hdr_ext_n_common(ep_hdr_ext, val); + + msb = ep_hdr_ext->hdr_total_len_or_pad_offset >> + hweight_long( + IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_OFFSET_BMSK); + IPA_SETFIELD_IN_REG(*val, msb, + IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB_SHFT_v4_5, + IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB_BMSK_v4_5); + + if (!ep_hdr_ext->hdr) { + IPAHAL_ERR("No header info, skipping it.\n"); + return; + } + + msb = ep_hdr_ext->hdr->hdr_ofst_pkt_size >> + hweight_long(IPA_ENDP_INIT_HDR_n_HDR_OFST_PKT_SIZE_BMSK_v4_5); + IPA_SETFIELD_IN_REG(*val, msb, + IPA_ENDP_INIT_HDR_EXT_n_HDR_OFST_PKT_SIZE_MSB_SHFT_v4_5, + IPA_ENDP_INIT_HDR_EXT_n_HDR_OFST_PKT_SIZE_MSB_BMSK_v4_5); + + msb = ep_hdr_ext->hdr->hdr_additional_const_len >> + hweight_long( + IPA_ENDP_INIT_HDR_n_HDR_ADDITIONAL_CONST_LEN_BMSK_v4_5); + IPA_SETFIELD_IN_REG(*val, msb, + IPA_ENDP_INIT_HDR_EXT_n_HDR_ADDITIONAL_CONST_LEN_MSB_SHFT_v4_5, + IPA_ENDP_INIT_HDR_EXT_n_HDR_ADDITIONAL_CONST_LEN_MSB_BMSK_v4_5 + ); +} + +static void ipareg_construct_endp_init_hdr_ext_n_v5_0(enum ipahal_reg_name reg, + const void *fields, u32 *val) +{ + const struct ipa_ep_cfg_hdr_ext *ep_hdr_ext = + (const struct ipa_ep_cfg_hdr_ext *)fields; + + ipareg_construct_endp_init_hdr_ext_n_v4_5(reg, fields, val); + + IPA_SETFIELD_IN_REG(*val, ep_hdr_ext->hdr_bytes_to_remove_valid, + IPA_ENDP_INIT_HDR_EXT_n_HDR_BYTES_TO_REMOVE_VALID_SHFT_v5_0, + IPA_ENDP_INIT_HDR_EXT_n_HDR_BYTES_TO_REMOVE_VALID_BMSK_v5_0); + + IPA_SETFIELD_IN_REG(*val, ep_hdr_ext->hdr_bytes_to_remove, + IPA_ENDP_INIT_HDR_EXT_n_HDR_BYTES_TO_REMOVE_SHFT_v5_0, + IPA_ENDP_INIT_HDR_EXT_n_HDR_BYTES_TO_REMOVE_BMSK_v5_0); +} + +static void ipareg_construct_endp_init_hdr_n(enum ipahal_reg_name reg, + const void *fields, u32 *val) +{ + struct ipa_ep_cfg_hdr *ep_hdr; + + ep_hdr = (struct ipa_ep_cfg_hdr *)fields; + + IPA_SETFIELD_IN_REG(*val, ep_hdr->hdr_metadata_reg_valid, + IPA_ENDP_INIT_HDR_n_HDR_METADATA_REG_VALID_SHFT, + IPA_ENDP_INIT_HDR_n_HDR_METADATA_REG_VALID_BMSK); + + IPA_SETFIELD_IN_REG(*val, ep_hdr->hdr_remove_additional, + IPA_ENDP_INIT_HDR_n_HDR_LEN_INC_DEAGG_HDR_SHFT, + IPA_ENDP_INIT_HDR_n_HDR_LEN_INC_DEAGG_HDR_BMSK); + + IPA_SETFIELD_IN_REG(*val, ep_hdr->hdr_a5_mux, + IPA_ENDP_INIT_HDR_n_HDR_A5_MUX_SHFT, + IPA_ENDP_INIT_HDR_n_HDR_A5_MUX_BMSK); + + IPA_SETFIELD_IN_REG(*val, ep_hdr->hdr_ofst_pkt_size, + IPA_ENDP_INIT_HDR_n_HDR_OFST_PKT_SIZE_SHFT, + IPA_ENDP_INIT_HDR_n_HDR_OFST_PKT_SIZE_BMSK); + + IPA_SETFIELD_IN_REG(*val, ep_hdr->hdr_ofst_pkt_size_valid, + IPA_ENDP_INIT_HDR_n_HDR_OFST_PKT_SIZE_VALID_SHFT, + IPA_ENDP_INIT_HDR_n_HDR_OFST_PKT_SIZE_VALID_BMSK); + + IPA_SETFIELD_IN_REG(*val, ep_hdr->hdr_additional_const_len, + IPA_ENDP_INIT_HDR_n_HDR_ADDITIONAL_CONST_LEN_SHFT, + IPA_ENDP_INIT_HDR_n_HDR_ADDITIONAL_CONST_LEN_BMSK); + + IPA_SETFIELD_IN_REG(*val, ep_hdr->hdr_ofst_metadata, + IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_SHFT, + IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_BMSK); + + IPA_SETFIELD_IN_REG(*val, ep_hdr->hdr_ofst_metadata_valid, + IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_VALID_SHFT, + IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_VALID_BMSK); + + IPA_SETFIELD_IN_REG(*val, ep_hdr->hdr_len, + IPA_ENDP_INIT_HDR_n_HDR_LEN_SHFT, + IPA_ENDP_INIT_HDR_n_HDR_LEN_BMSK); +} + +static void ipareg_construct_endp_init_hdr_n_common( + struct ipa_ep_cfg_hdr *ep_hdr, u32 *val) +{ + u32 msb; + + msb = ep_hdr->hdr_ofst_metadata >> + hweight_long(IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_BMSK_v4_5); + IPA_SETFIELD_IN_REG(*val, msb, + IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_MSB_SHFT_v4_5, + IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_MSB_BMSK_v4_5); + + msb = ep_hdr->hdr_len >> + hweight_long(IPA_ENDP_INIT_HDR_n_HDR_LEN_BMSK_v4_5); + IPA_SETFIELD_IN_REG(*val, msb, + IPA_ENDP_INIT_HDR_n_HDR_LEN_MSB_SHFT_v4_5, + IPA_ENDP_INIT_HDR_n_HDR_LEN_MSB_BMSK_v4_5); + + IPA_SETFIELD_IN_REG(*val, ep_hdr->hdr_remove_additional, + IPA_ENDP_INIT_HDR_n_HDR_LEN_INC_DEAGG_HDR_SHFT_v4_5, + IPA_ENDP_INIT_HDR_n_HDR_LEN_INC_DEAGG_HDR_BMSK_v4_5); + + IPA_SETFIELD_IN_REG(*val, ep_hdr->hdr_ofst_pkt_size, + IPA_ENDP_INIT_HDR_n_HDR_OFST_PKT_SIZE_SHFT_v4_5, + IPA_ENDP_INIT_HDR_n_HDR_OFST_PKT_SIZE_BMSK_v4_5); + + IPA_SETFIELD_IN_REG(*val, ep_hdr->hdr_ofst_pkt_size_valid, + IPA_ENDP_INIT_HDR_n_HDR_OFST_PKT_SIZE_VALID_SHFT_v4_5, + IPA_ENDP_INIT_HDR_n_HDR_OFST_PKT_SIZE_VALID_BMSK_v4_5); + + IPA_SETFIELD_IN_REG(*val, ep_hdr->hdr_additional_const_len, + IPA_ENDP_INIT_HDR_n_HDR_ADDITIONAL_CONST_LEN_SHFT_v4_5, + IPA_ENDP_INIT_HDR_n_HDR_ADDITIONAL_CONST_LEN_BMSK_v4_5); + + IPA_SETFIELD_IN_REG(*val, ep_hdr->hdr_ofst_metadata, + IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_SHFT_v4_5, + IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_BMSK_v4_5); + + IPA_SETFIELD_IN_REG(*val, ep_hdr->hdr_ofst_metadata_valid, + IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_VALID_SHFT_v4_5, + IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_VALID_BMSK_v4_5); + + IPA_SETFIELD_IN_REG(*val, ep_hdr->hdr_len, + IPA_ENDP_INIT_HDR_n_HDR_LEN_SHFT_v4_5, + IPA_ENDP_INIT_HDR_n_HDR_LEN_BMSK_v4_5); +} + +static void ipareg_construct_endp_init_hdr_n_v4_5(enum ipahal_reg_name reg, + const void *fields, u32 *val) +{ + struct ipa_ep_cfg_hdr *ep_hdr; + + ep_hdr = (struct ipa_ep_cfg_hdr *)fields; + + ipareg_construct_endp_init_hdr_n_common(ep_hdr, val); + + IPA_SETFIELD_IN_REG(*val, ep_hdr->hdr_a5_mux, + IPA_ENDP_INIT_HDR_n_HDR_A5_MUX_SHFT_v4_5, + IPA_ENDP_INIT_HDR_n_HDR_A5_MUX_BMSK_v4_5); + +} + +static void ipareg_construct_endp_init_hdr_n_v4_9(enum ipahal_reg_name reg, + const void *fields, u32 *val) +{ + struct ipa_ep_cfg_hdr *ep_hdr; + + ep_hdr = (struct ipa_ep_cfg_hdr *)fields; + + ipareg_construct_endp_init_hdr_n_common(ep_hdr, val); + +} + +static void ipareg_construct_route(enum ipahal_reg_name reg, + const void *fields, u32 *val) +{ + struct ipahal_reg_route *route; + + route = (struct ipahal_reg_route *)fields; + + IPA_SETFIELD_IN_REG(*val, route->route_dis, + IPA_ROUTE_ROUTE_DIS_SHFT, + IPA_ROUTE_ROUTE_DIS_BMSK); + + IPA_SETFIELD_IN_REG(*val, route->route_def_pipe, + IPA_ROUTE_ROUTE_DEF_PIPE_SHFT, + IPA_ROUTE_ROUTE_DEF_PIPE_BMSK); + + IPA_SETFIELD_IN_REG(*val, route->route_def_hdr_table, + IPA_ROUTE_ROUTE_DEF_HDR_TABLE_SHFT, + IPA_ROUTE_ROUTE_DEF_HDR_TABLE_BMSK); + + IPA_SETFIELD_IN_REG(*val, route->route_def_hdr_ofst, + IPA_ROUTE_ROUTE_DEF_HDR_OFST_SHFT, + IPA_ROUTE_ROUTE_DEF_HDR_OFST_BMSK); + + IPA_SETFIELD_IN_REG(*val, route->route_frag_def_pipe, + IPA_ROUTE_ROUTE_FRAG_DEF_PIPE_SHFT, + IPA_ROUTE_ROUTE_FRAG_DEF_PIPE_BMSK); + + IPA_SETFIELD_IN_REG(*val, route->route_def_retain_hdr, + IPA_ROUTE_ROUTE_DEF_RETAIN_HDR_SHFT, + IPA_ROUTE_ROUTE_DEF_RETAIN_HDR_BMSK); +} + +static void ipareg_construct_route_v5_0(enum ipahal_reg_name reg, + const void *fields, u32 *val) +{ + struct ipahal_reg_route *route; + + route = (struct ipahal_reg_route *)fields; + + IPA_SETFIELD_IN_REG(*val, route->route_dis, + IPA_ROUTE_ROUTE_DIS_SHFT_v5_0, + IPA_ROUTE_ROUTE_DIS_BMSK_v5_0); + + IPA_SETFIELD_IN_REG(*val, route->route_def_pipe, + IPA_ROUTE_ROUTE_DEF_PIPE_SHFT_v5_0, + IPA_ROUTE_ROUTE_DEF_PIPE_BMSK_v5_0); + + IPA_SETFIELD_IN_REG(*val, route->route_def_hdr_table, + IPA_ROUTE_ROUTE_DEF_HDR_TABLE_SHFT_v5_0, + IPA_ROUTE_ROUTE_DEF_HDR_TABLE_BMSK_v5_0); + + IPA_SETFIELD_IN_REG(*val, route->route_def_hdr_ofst, + IPA_ROUTE_ROUTE_DEF_HDR_OFST_SHFT_v5_0, + IPA_ROUTE_ROUTE_DEF_HDR_OFST_BMSK_v5_0); + + IPA_SETFIELD_IN_REG(*val, route->route_frag_def_pipe, + IPA_ROUTE_ROUTE_FRAG_DEF_PIPE_SHFT_v5_0, + IPA_ROUTE_ROUTE_FRAG_DEF_PIPE_BMSK_v5_0); + + IPA_SETFIELD_IN_REG(*val, route->route_def_retain_hdr, + IPA_ROUTE_ROUTE_DEF_RETAIN_HDR_SHFT_v5_0, + IPA_ROUTE_ROUTE_DEF_RETAIN_HDR_BMSK_v5_0); +} + +static void ipareg_construct_qsb_max_writes(enum ipahal_reg_name reg, + const void *fields, u32 *val) +{ + struct ipahal_reg_qsb_max_writes *max_writes; + + max_writes = (struct ipahal_reg_qsb_max_writes *)fields; + + IPA_SETFIELD_IN_REG(*val, max_writes->qmb_0_max_writes, + IPA_QSB_MAX_WRITES_GEN_QMB_0_MAX_WRITES_SHFT, + IPA_QSB_MAX_WRITES_GEN_QMB_0_MAX_WRITES_BMSK); + IPA_SETFIELD_IN_REG(*val, max_writes->qmb_1_max_writes, + IPA_QSB_MAX_WRITES_GEN_QMB_1_MAX_WRITES_SHFT, + IPA_QSB_MAX_WRITES_GEN_QMB_1_MAX_WRITES_BMSK); +} + +static void ipareg_construct_qsb_max_reads(enum ipahal_reg_name reg, + const void *fields, u32 *val) +{ + struct ipahal_reg_qsb_max_reads *max_reads; + + max_reads = (struct ipahal_reg_qsb_max_reads *)fields; + + IPA_SETFIELD_IN_REG(*val, max_reads->qmb_0_max_reads, + IPA_QSB_MAX_READS_GEN_QMB_0_MAX_READS_SHFT, + IPA_QSB_MAX_READS_GEN_QMB_0_MAX_READS_BMSK); + IPA_SETFIELD_IN_REG(*val, max_reads->qmb_1_max_reads, + IPA_QSB_MAX_READS_GEN_QMB_1_MAX_READS_SHFT, + IPA_QSB_MAX_READS_GEN_QMB_1_MAX_READS_BMSK); +} + +static void ipareg_construct_qsb_max_reads_v4_0(enum ipahal_reg_name reg, + const void *fields, u32 *val) +{ + struct ipahal_reg_qsb_max_reads *max_reads; + + max_reads = (struct ipahal_reg_qsb_max_reads *)fields; + + IPA_SETFIELD_IN_REG(*val, max_reads->qmb_0_max_reads, + IPA_QSB_MAX_READS_GEN_QMB_0_MAX_READS_SHFT, + IPA_QSB_MAX_READS_GEN_QMB_0_MAX_READS_BMSK); + IPA_SETFIELD_IN_REG(*val, max_reads->qmb_1_max_reads, + IPA_QSB_MAX_READS_GEN_QMB_1_MAX_READS_SHFT, + IPA_QSB_MAX_READS_GEN_QMB_1_MAX_READS_BMSK); + IPA_SETFIELD_IN_REG(*val, max_reads->qmb_0_max_read_beats, + IPA_QSB_MAX_READS_GEN_QMB_0_MAX_READS_BEATS_SHFT_V4_0, + IPA_QSB_MAX_READS_GEN_QMB_0_MAX_READS_BEATS_BMSK_V4_0); + IPA_SETFIELD_IN_REG(*val, max_reads->qmb_1_max_read_beats, + IPA_QSB_MAX_READS_GEN_QMB_1_MAX_READS_BEATS_SHFT_V4_0, + IPA_QSB_MAX_READS_GEN_QMB_1_MAX_READS_BEATS_BMSK_V4_0); +} + +static void ipareg_parse_qsb_max_reads(enum ipahal_reg_name reg, + void *fields, u32 val) +{ + struct ipahal_reg_qsb_max_reads *max_reads; + + max_reads = (struct ipahal_reg_qsb_max_reads *)fields; + + max_reads->qmb_0_max_reads = IPA_GETFIELD_FROM_REG(val, + IPA_QSB_MAX_READS_GEN_QMB_0_MAX_READS_SHFT, + IPA_QSB_MAX_READS_GEN_QMB_0_MAX_READS_BMSK); + max_reads->qmb_1_max_reads = IPA_GETFIELD_FROM_REG(val, + IPA_QSB_MAX_READS_GEN_QMB_1_MAX_READS_SHFT, + IPA_QSB_MAX_READS_GEN_QMB_1_MAX_READS_BMSK); + max_reads->qmb_0_max_read_beats = IPA_GETFIELD_FROM_REG(val, + IPA_QSB_MAX_READS_GEN_QMB_0_MAX_READS_BEATS_SHFT_V4_0, + IPA_QSB_MAX_READS_GEN_QMB_0_MAX_READS_BEATS_BMSK_V4_0); + max_reads->qmb_1_max_read_beats = IPA_GETFIELD_FROM_REG(val, + IPA_QSB_MAX_READS_GEN_QMB_1_MAX_READS_BEATS_SHFT_V4_0, + IPA_QSB_MAX_READS_GEN_QMB_1_MAX_READS_BEATS_BMSK_V4_0); +} + +static void ipareg_parse_qsb_max_writes(enum ipahal_reg_name reg, + void *fields, u32 val) +{ + struct ipahal_reg_qsb_max_writes *max_writes; + + max_writes = (struct ipahal_reg_qsb_max_writes *)fields; + + max_writes->qmb_0_max_writes = IPA_GETFIELD_FROM_REG(val, + IPA_QSB_MAX_WRITES_GEN_QMB_0_MAX_WRITES_SHFT, + IPA_QSB_MAX_WRITES_GEN_QMB_0_MAX_WRITES_BMSK); + max_writes->qmb_1_max_writes = IPA_GETFIELD_FROM_REG(val, + IPA_QSB_MAX_WRITES_GEN_QMB_1_MAX_WRITES_SHFT, + IPA_QSB_MAX_WRITES_GEN_QMB_1_MAX_WRITES_BMSK); +} + +static void ipareg_parse_tx_cfg(enum ipahal_reg_name reg, + void *fields, u32 val) +{ + struct ipahal_reg_tx_cfg *tx_cfg; + + tx_cfg = (struct ipahal_reg_tx_cfg *)fields; + + tx_cfg->tx0_prefetch_disable = IPA_GETFIELD_FROM_REG(val, + IPA_TX_CFG_TX0_PREFETCH_DISABLE_SHFT_V3_5, + IPA_TX_CFG_TX0_PREFETCH_DISABLE_BMSK_V3_5); + + tx_cfg->tx1_prefetch_disable = IPA_GETFIELD_FROM_REG(val, + IPA_TX_CFG_TX1_PREFETCH_DISABLE_SHFT_V3_5, + IPA_TX_CFG_TX1_PREFETCH_DISABLE_BMSK_V3_5); + + tx_cfg->tx0_prefetch_almost_empty_size = IPA_GETFIELD_FROM_REG(val, + IPA_TX_CFG_PREFETCH_ALMOST_EMPTY_SIZE_SHFT_V3_5, + IPA_TX_CFG_PREFETCH_ALMOST_EMPTY_SIZE_BMSK_V3_5); + + tx_cfg->tx1_prefetch_almost_empty_size = + tx_cfg->tx0_prefetch_almost_empty_size; +} + +static void ipareg_parse_tx_cfg_v4_0(enum ipahal_reg_name reg, + void *fields, u32 val) +{ + struct ipahal_reg_tx_cfg *tx_cfg; + + tx_cfg = (struct ipahal_reg_tx_cfg *)fields; + + tx_cfg->tx0_prefetch_almost_empty_size = IPA_GETFIELD_FROM_REG(val, + IPA_TX_CFG_PREFETCH_ALMOST_EMPTY_SIZE_TX0_SHFT_V4_0, + IPA_TX_CFG_PREFETCH_ALMOST_EMPTY_SIZE_TX0_BMSK_V4_0); + + tx_cfg->tx1_prefetch_almost_empty_size = IPA_GETFIELD_FROM_REG(val, + IPA_TX_CFG_PREFETCH_ALMOST_EMPTY_SIZE_TX1_SHFT_V4_0, + IPA_TX_CFG_PREFETCH_ALMOST_EMPTY_SIZE_TX1_BMSK_V4_0); + + tx_cfg->dmaw_scnd_outsd_pred_en = IPA_GETFIELD_FROM_REG(val, + IPA_TX_CFG_DMAW_SCND_OUTSD_PRED_EN_SHFT_V4_0, + IPA_TX_CFG_DMAW_SCND_OUTSD_PRED_EN_BMSK_V4_0); + + tx_cfg->dmaw_scnd_outsd_pred_threshold = IPA_GETFIELD_FROM_REG(val, + IPA_TX_CFG_DMAW_SCND_OUTSD_PRED_THRESHOLD_SHFT_V4_0, + IPA_TX_CFG_DMAW_SCND_OUTSD_PRED_THRESHOLD_BMSK_V4_0); + + tx_cfg->dmaw_max_beats_256_dis = IPA_GETFIELD_FROM_REG(val, + IPA_TX_CFG_DMAW_MAX_BEATS_256_DIS_SHFT_V4_0, + IPA_TX_CFG_DMAW_MAX_BEATS_256_DIS_BMSK_V4_0); + + tx_cfg->pa_mask_en = IPA_GETFIELD_FROM_REG(val, + IPA_TX_CFG_PA_MASK_EN_SHFT_V4_0, + IPA_TX_CFG_PA_MASK_EN_BMSK_V4_0); +} + +static void ipareg_parse_tx_cfg_v4_5(enum ipahal_reg_name reg, + void *fields, u32 val) +{ + struct ipahal_reg_tx_cfg *tx_cfg; + + ipareg_parse_tx_cfg_v4_0(reg, fields, val); + + tx_cfg = (struct ipahal_reg_tx_cfg *)fields; + + tx_cfg->dual_tx_enable = IPA_GETFIELD_FROM_REG(val, + IPA_TX_CFG_DUAL_TX_ENABLE_SHFT_V4_5, + IPA_TX_CFG_DUAL_TX_ENABLE_BMSK_V4_5); +} + +static void ipareg_parse_tx_cfg_v4_9(enum ipahal_reg_name reg, + void *fields, u32 val) +{ + struct ipahal_reg_tx_cfg *tx_cfg; + + ipareg_parse_tx_cfg_v4_5(reg, fields, val); + + tx_cfg = (struct ipahal_reg_tx_cfg *)fields; + + tx_cfg->sspnd_pa_no_start_state = IPA_GETFIELD_FROM_REG(val, + IPA_TX_CFG_SSPND_PA_NO_START_STATE_SHFT_V4_9, + IPA_TX_CFG_SSPND_PA_NO_START_STATE_BMSK_V4_9); +} + +static void ipareg_parse_tx_cfg_v5_0(enum ipahal_reg_name reg, + void *fields, u32 val) +{ + struct ipahal_reg_tx_cfg *tx_cfg; + + ipareg_parse_tx_cfg_v4_9(reg, fields, val); + + tx_cfg = (struct ipahal_reg_tx_cfg *)fields; + + tx_cfg->holb_sticky_drop_en = IPA_GETFIELD_FROM_REG(val, + IPA_TX_CFG_HOLB_STICKY_DROP_EN_SHFT_v5_0, + IPA_TX_CFG_HOLB_STICKY_DROP_EN_BMSK_v5_0); +} + +static void ipareg_construct_tx_cfg(enum ipahal_reg_name reg, + const void *fields, u32 *val) +{ + struct ipahal_reg_tx_cfg *tx_cfg; + + tx_cfg = (struct ipahal_reg_tx_cfg *)fields; + + if (tx_cfg->tx0_prefetch_almost_empty_size != + tx_cfg->tx1_prefetch_almost_empty_size) + ipa_assert(); + + IPA_SETFIELD_IN_REG(*val, tx_cfg->tx0_prefetch_disable, + IPA_TX_CFG_TX0_PREFETCH_DISABLE_SHFT_V3_5, + IPA_TX_CFG_TX0_PREFETCH_DISABLE_BMSK_V3_5); + + IPA_SETFIELD_IN_REG(*val, tx_cfg->tx1_prefetch_disable, + IPA_TX_CFG_TX1_PREFETCH_DISABLE_SHFT_V3_5, + IPA_TX_CFG_TX1_PREFETCH_DISABLE_BMSK_V3_5); + + IPA_SETFIELD_IN_REG(*val, tx_cfg->tx0_prefetch_almost_empty_size, + IPA_TX_CFG_PREFETCH_ALMOST_EMPTY_SIZE_SHFT_V3_5, + IPA_TX_CFG_PREFETCH_ALMOST_EMPTY_SIZE_BMSK_V3_5); +} + +static void ipareg_construct_tx_cfg_v4_0(enum ipahal_reg_name reg, + const void *fields, u32 *val) +{ + struct ipahal_reg_tx_cfg *tx_cfg; + + tx_cfg = (struct ipahal_reg_tx_cfg *)fields; + + IPA_SETFIELD_IN_REG(*val, tx_cfg->tx0_prefetch_almost_empty_size, + IPA_TX_CFG_PREFETCH_ALMOST_EMPTY_SIZE_TX0_SHFT_V4_0, + IPA_TX_CFG_PREFETCH_ALMOST_EMPTY_SIZE_TX0_BMSK_V4_0); + + IPA_SETFIELD_IN_REG(*val, tx_cfg->tx1_prefetch_almost_empty_size, + IPA_TX_CFG_PREFETCH_ALMOST_EMPTY_SIZE_TX1_SHFT_V4_0, + IPA_TX_CFG_PREFETCH_ALMOST_EMPTY_SIZE_TX1_BMSK_V4_0); + + IPA_SETFIELD_IN_REG(*val, tx_cfg->dmaw_scnd_outsd_pred_threshold, + IPA_TX_CFG_DMAW_SCND_OUTSD_PRED_THRESHOLD_SHFT_V4_0, + IPA_TX_CFG_DMAW_SCND_OUTSD_PRED_THRESHOLD_BMSK_V4_0); + + IPA_SETFIELD_IN_REG(*val, tx_cfg->dmaw_max_beats_256_dis, + IPA_TX_CFG_DMAW_MAX_BEATS_256_DIS_SHFT_V4_0, + IPA_TX_CFG_DMAW_MAX_BEATS_256_DIS_BMSK_V4_0); + + IPA_SETFIELD_IN_REG(*val, tx_cfg->dmaw_scnd_outsd_pred_en, + IPA_TX_CFG_DMAW_SCND_OUTSD_PRED_EN_SHFT_V4_0, + IPA_TX_CFG_DMAW_SCND_OUTSD_PRED_EN_BMSK_V4_0); + + IPA_SETFIELD_IN_REG(*val, tx_cfg->pa_mask_en, + IPA_TX_CFG_PA_MASK_EN_SHFT_V4_0, + IPA_TX_CFG_PA_MASK_EN_BMSK_V4_0); +} + +static void ipareg_construct_tx_cfg_v4_5(enum ipahal_reg_name reg, + const void *fields, u32 *val) +{ + struct ipahal_reg_tx_cfg *tx_cfg; + + ipareg_construct_tx_cfg_v4_0(reg, fields, val); + + tx_cfg = (struct ipahal_reg_tx_cfg *)fields; + + IPA_SETFIELD_IN_REG(*val, tx_cfg->dual_tx_enable, + IPA_TX_CFG_DUAL_TX_ENABLE_SHFT_V4_5, + IPA_TX_CFG_DUAL_TX_ENABLE_BMSK_V4_5); +} + +static void ipareg_construct_tx_cfg_v4_9(enum ipahal_reg_name reg, + const void *fields, u32 *val) +{ + struct ipahal_reg_tx_cfg *tx_cfg; + + ipareg_construct_tx_cfg_v4_5(reg, fields, val); + + tx_cfg = (struct ipahal_reg_tx_cfg *)fields; + + IPA_SETFIELD_IN_REG(*val, tx_cfg->sspnd_pa_no_start_state, + IPA_TX_CFG_SSPND_PA_NO_START_STATE_SHFT_V4_9, + IPA_TX_CFG_SSPND_PA_NO_START_STATE_BMSK_V4_9); +} + +static void ipareg_construct_tx_cfg_v5_0(enum ipahal_reg_name reg, + const void *fields, u32 *val) +{ + struct ipahal_reg_tx_cfg *tx_cfg; + + ipareg_construct_tx_cfg_v4_9(reg, fields, val); + + tx_cfg = (struct ipahal_reg_tx_cfg *)fields; + + IPA_SETFIELD_IN_REG(*val, tx_cfg->holb_sticky_drop_en, + IPA_TX_CFG_HOLB_STICKY_DROP_EN_SHFT_v5_0, + IPA_TX_CFG_HOLB_STICKY_DROP_EN_BMSK_v5_0); +} + +static void ipareg_construct_idle_indication_cfg(enum ipahal_reg_name reg, + const void *fields, u32 *val) +{ + struct ipahal_reg_idle_indication_cfg *idle_indication_cfg; + + idle_indication_cfg = (struct ipahal_reg_idle_indication_cfg *)fields; + + IPA_SETFIELD_IN_REG(*val, + idle_indication_cfg->enter_idle_debounce_thresh, + IPA_IDLE_INDICATION_CFG_ENTER_IDLE_DEBOUNCE_THRESH_SHFT_V3_5, + IPA_IDLE_INDICATION_CFG_ENTER_IDLE_DEBOUNCE_THRESH_BMSK_V3_5); + + IPA_SETFIELD_IN_REG(*val, + idle_indication_cfg->const_non_idle_enable, + IPA_IDLE_INDICATION_CFG_CONST_NON_IDLE_ENABLE_SHFT_V3_5, + IPA_IDLE_INDICATION_CFG_CONST_NON_IDLE_ENABLE_BMSK_V3_5); +} + +static void ipareg_construct_hps_queue_weights(enum ipahal_reg_name reg, + const void *fields, u32 *val) +{ + struct ipahal_reg_rx_hps_weights *hps_weights; + + hps_weights = (struct ipahal_reg_rx_hps_weights *)fields; + + IPA_SETFIELD_IN_REG(*val, + hps_weights->hps_queue_weight_0, + IPA_HPS_FTCH_ARB_QUEUE_WEIGHTS_RX_HPS_QUEUE_WEIGHT_0_SHFT, + IPA_HPS_FTCH_ARB_QUEUE_WEIGHTS_RX_HPS_QUEUE_WEIGHT_0_BMSK); + + IPA_SETFIELD_IN_REG(*val, + hps_weights->hps_queue_weight_1, + IPA_HPS_FTCH_ARB_QUEUE_WEIGHTS_RX_HPS_QUEUE_WEIGHT_1_SHFT, + IPA_HPS_FTCH_ARB_QUEUE_WEIGHTS_RX_HPS_QUEUE_WEIGHT_1_BMSK); + + IPA_SETFIELD_IN_REG(*val, + hps_weights->hps_queue_weight_2, + IPA_HPS_FTCH_ARB_QUEUE_WEIGHTS_RX_HPS_QUEUE_WEIGHT_2_SHFT, + IPA_HPS_FTCH_ARB_QUEUE_WEIGHTS_RX_HPS_QUEUE_WEIGHT_2_BMSK); + + IPA_SETFIELD_IN_REG(*val, + hps_weights->hps_queue_weight_3, + IPA_HPS_FTCH_ARB_QUEUE_WEIGHTS_RX_HPS_QUEUE_WEIGHT_3_SHFT, + IPA_HPS_FTCH_ARB_QUEUE_WEIGHTS_RX_HPS_QUEUE_WEIGHT_3_BMSK); +} + +static void ipareg_parse_hps_queue_weights( + enum ipahal_reg_name reg, void *fields, u32 val) +{ + struct ipahal_reg_rx_hps_weights *hps_weights = + (struct ipahal_reg_rx_hps_weights *)fields; + + memset(hps_weights, 0, sizeof(struct ipahal_reg_rx_hps_weights)); + + hps_weights->hps_queue_weight_0 = IPA_GETFIELD_FROM_REG(val, + IPA_HPS_FTCH_ARB_QUEUE_WEIGHTS_RX_HPS_QUEUE_WEIGHT_0_SHFT, + IPA_HPS_FTCH_ARB_QUEUE_WEIGHTS_RX_HPS_QUEUE_WEIGHT_0_BMSK); + + hps_weights->hps_queue_weight_1 = IPA_GETFIELD_FROM_REG(val, + IPA_HPS_FTCH_ARB_QUEUE_WEIGHTS_RX_HPS_QUEUE_WEIGHT_1_SHFT, + IPA_HPS_FTCH_ARB_QUEUE_WEIGHTS_RX_HPS_QUEUE_WEIGHT_1_BMSK); + + hps_weights->hps_queue_weight_2 = IPA_GETFIELD_FROM_REG(val, + IPA_HPS_FTCH_ARB_QUEUE_WEIGHTS_RX_HPS_QUEUE_WEIGHT_2_SHFT, + IPA_HPS_FTCH_ARB_QUEUE_WEIGHTS_RX_HPS_QUEUE_WEIGHT_2_BMSK); + + hps_weights->hps_queue_weight_3 = IPA_GETFIELD_FROM_REG(val, + IPA_HPS_FTCH_ARB_QUEUE_WEIGHTS_RX_HPS_QUEUE_WEIGHT_3_SHFT, + IPA_HPS_FTCH_ARB_QUEUE_WEIGHTS_RX_HPS_QUEUE_WEIGHT_3_BMSK); +} + +static void ipareg_construct_counter_cfg(enum ipahal_reg_name reg, + const void *fields, u32 *val) +{ + struct ipahal_reg_counter_cfg *counter_cfg = + (struct ipahal_reg_counter_cfg *)fields; + + IPA_SETFIELD_IN_REG(*val, counter_cfg->aggr_granularity, + IPA_COUNTER_CFG_AGGR_GRANULARITY_SHFT, + IPA_COUNTER_CFG_AGGR_GRANULARITY_BMSK); +} + +static void ipareg_parse_counter_cfg( + enum ipahal_reg_name reg, void *fields, u32 val) +{ + struct ipahal_reg_counter_cfg *counter_cfg = + (struct ipahal_reg_counter_cfg *)fields; + + memset(counter_cfg, 0, sizeof(*counter_cfg)); + + counter_cfg->aggr_granularity = IPA_GETFIELD_FROM_REG(val, + IPA_COUNTER_CFG_AGGR_GRANULARITY_SHFT, + IPA_COUNTER_CFG_AGGR_GRANULARITY_BMSK); +} + +static void ipareg_parse_state_coal_master( + enum ipahal_reg_name reg, void *fields, u32 val) +{ + struct ipahal_reg_state_coal_master *state_coal_master = + (struct ipahal_reg_state_coal_master *)fields; + + memset(state_coal_master, 0, sizeof(*state_coal_master)); + + state_coal_master->vp_timer_expired = IPA_GETFIELD_FROM_REG(val, + IPA_STATE_COAL_MASTER_VP_TIMER_EXPIRED_SHFT, + IPA_STATE_COAL_MASTER_VP_TIMER_EXPIRED_BMSK); + + state_coal_master->lru_vp = IPA_GETFIELD_FROM_REG(val, + IPA_STATE_COAL_MASTER_LRU_VP_SHFT, + IPA_STATE_COAL_MASTER_LRU_VP_BMSK); + + state_coal_master->init_vp_fsm_state = IPA_GETFIELD_FROM_REG(val, + IPA_STATE_COAL_MASTER_INIT_VP_FSM_STATE_SHFT, + IPA_STATE_COAL_MASTER_INIT_VP_FSM_STATE_BMSK); + + state_coal_master->check_fir_fsm_state = IPA_GETFIELD_FROM_REG(val, + IPA_STATE_COAL_MASTER_CHECK_FIR_FSM_STATE_SHFT, + IPA_STATE_COAL_MASTER_CHECK_FIR_FSM_STATE_BMSK); + + state_coal_master->hash_calc_fsm_state = IPA_GETFIELD_FROM_REG(val, + IPA_STATE_COAL_MASTER_HASH_CALC_FSM_STATE_SHFT, + IPA_STATE_COAL_MASTER_HASH_CALC_FSM_STATE_BMSK); + + state_coal_master->find_open_fsm_state = IPA_GETFIELD_FROM_REG(val, + IPA_STATE_COAL_MASTER_FIND_OPEN_FSM_STATE_SHFT, + IPA_STATE_COAL_MASTER_FIND_OPEN_FSM_STATE_BMSK); + + state_coal_master->main_fsm_state = IPA_GETFIELD_FROM_REG(val, + IPA_STATE_COAL_MASTER_MAIN_FSM_STATE_SHFT, + IPA_STATE_COAL_MASTER_MAIN_FSM_STATE_BMSK); + + state_coal_master->vp_vld = IPA_GETFIELD_FROM_REG(val, + IPA_STATE_COAL_MASTER_VP_VLD_SHFT, + IPA_STATE_COAL_MASTER_VP_VLD_BMSK); +} + +static void ipareg_construct_coal_evict_lru(enum ipahal_reg_name reg, + const void *fields, u32 *val) +{ + struct ipahal_reg_coal_evict_lru *evict_lru = + (struct ipahal_reg_coal_evict_lru *)fields; + + IPA_SETFIELD_IN_REG(*val, evict_lru->coal_vp_lru_thrshld, + IPA_COAL_VP_LRU_THRSHLD_SHFT, IPA_COAL_VP_LRU_THRSHLD_BMSK); + + IPA_SETFIELD_IN_REG(*val, evict_lru->coal_eviction_en, + IPA_COAL_EVICTION_EN_SHFT, IPA_COAL_EVICTION_EN_BMSK); +} + +static void ipareg_construct_coal_evict_lru_v5_5(enum ipahal_reg_name reg, + const void *fields, u32 *val) +{ + struct ipahal_reg_coal_evict_lru *evict_lru = + (struct ipahal_reg_coal_evict_lru *)fields; + + IPA_SETFIELD_IN_REG(*val, evict_lru->coal_eviction_en, + IPA_COAL_EVICTION_EN_SHFT_v5_5, + IPA_COAL_EVICTION_EN_BMSK_v5_5); + + IPA_SETFIELD_IN_REG(*val, evict_lru->coal_vp_lru_gran_sel, + IPA_COAL_VP_LRU_GRAN_SEL_SHFT_v5_5, + IPA_COAL_VP_LRU_GRAN_SEL_BMSK_v5_5); + + IPA_SETFIELD_IN_REG(*val, evict_lru->coal_vp_lru_udp_thrshld, + IPA_COAL_VP_LRU_UDP_THRSHLD_SHFT_v5_5, + IPA_COAL_VP_LRU_UDP_THRSHLD_BMSK_v5_5); + + IPA_SETFIELD_IN_REG(*val, evict_lru->coal_vp_lru_tcp_thrshld, + IPA_COAL_VP_LRU_TCP_THRSHLD_SHFT_v5_5, + IPA_COAL_VP_LRU_TCP_THRSHLD_BMSK_v5_5); + + IPA_SETFIELD_IN_REG(*val, evict_lru->coal_vp_lru_udp_thrshld_en, + IPA_COAL_VP_LRU_UDP_THRSHLD_EN_SHFT_v5_5, + IPA_COAL_VP_LRU_UDP_THRSHLD_EN_BMSK_v5_5); + + IPA_SETFIELD_IN_REG(*val, evict_lru->coal_vp_lru_tcp_thrshld_en, + IPA_COAL_VP_LRU_TCP_THRSHLD_EN_SHFT_v5_5, + IPA_COAL_VP_LRU_TCP_THRSHLD_EN_BMSK_v5_5); + + IPA_SETFIELD_IN_REG(*val, evict_lru->coal_vp_lru_tcp_num, + IPA_COAL_VP_LRU_TCP_NUM_SHFT_v5_5, + IPA_COAL_VP_LRU_TCP_NUM_BMSK_v5_5); +} + +static void ipareg_parse_coal_evict_lru(enum ipahal_reg_name reg, + void *fields, u32 val) +{ + struct ipahal_reg_coal_evict_lru *evict_lru = + (struct ipahal_reg_coal_evict_lru *)fields; + + memset(evict_lru, 0, sizeof(*evict_lru)); + + evict_lru->coal_vp_lru_thrshld = IPA_GETFIELD_FROM_REG(val, + IPA_COAL_VP_LRU_THRSHLD_SHFT, IPA_COAL_VP_LRU_THRSHLD_BMSK); + + evict_lru->coal_eviction_en = IPA_GETFIELD_FROM_REG(val, + IPA_COAL_EVICTION_EN_SHFT, IPA_COAL_EVICTION_EN_BMSK); +} + +static void ipareg_parse_coal_evict_lru_v5_5(enum ipahal_reg_name reg, + void *fields, u32 val) +{ + struct ipahal_reg_coal_evict_lru *evict_lru = + (struct ipahal_reg_coal_evict_lru *)fields; + + memset(evict_lru, 0, sizeof(*evict_lru)); + + evict_lru->coal_eviction_en = IPA_GETFIELD_FROM_REG(val, + IPA_COAL_EVICTION_EN_SHFT_v5_5, + IPA_COAL_EVICTION_EN_BMSK_v5_5); + + evict_lru->coal_vp_lru_gran_sel = IPA_GETFIELD_FROM_REG(val, + IPA_COAL_VP_LRU_GRAN_SEL_SHFT_v5_5, + IPA_COAL_VP_LRU_GRAN_SEL_BMSK_v5_5); + + evict_lru->coal_vp_lru_udp_thrshld = IPA_GETFIELD_FROM_REG(val, + IPA_COAL_VP_LRU_UDP_THRSHLD_SHFT_v5_5, + IPA_COAL_VP_LRU_UDP_THRSHLD_BMSK_v5_5); + + evict_lru->coal_vp_lru_tcp_thrshld = IPA_GETFIELD_FROM_REG(val, + IPA_COAL_VP_LRU_TCP_THRSHLD_SHFT_v5_5, + IPA_COAL_VP_LRU_TCP_THRSHLD_BMSK_v5_5); + + evict_lru->coal_vp_lru_udp_thrshld_en = IPA_GETFIELD_FROM_REG(val, + IPA_COAL_VP_LRU_UDP_THRSHLD_EN_SHFT_v5_5, + IPA_COAL_VP_LRU_UDP_THRSHLD_EN_BMSK_v5_5); + + evict_lru->coal_vp_lru_tcp_thrshld_en = IPA_GETFIELD_FROM_REG(val, + IPA_COAL_VP_LRU_TCP_THRSHLD_EN_SHFT_v5_5, + IPA_COAL_VP_LRU_TCP_THRSHLD_EN_BMSK_v5_5); + + evict_lru->coal_vp_lru_tcp_num = IPA_GETFIELD_FROM_REG(val, + IPA_COAL_VP_LRU_TCP_NUM_SHFT_v5_5, + IPA_COAL_VP_LRU_TCP_NUM_BMSK_v5_5); +} + +static void ipareg_construct_coal_qmap_cfg(enum ipahal_reg_name reg, + const void *fields, u32 *val) +{ + struct ipahal_reg_coal_qmap_cfg *qmap_cfg = + (struct ipahal_reg_coal_qmap_cfg *)fields; + + IPA_SETFIELD_IN_REG(*val, qmap_cfg->mux_id_byte_sel, + IPA_COAL_QMAP_CFG_SHFT, IPA_COAL_QMAP_CFG_BMSK); +} + +static void ipareg_parse_coal_qmap_cfg(enum ipahal_reg_name reg, + void *fields, u32 val) +{ + struct ipahal_reg_coal_qmap_cfg *qmap_cfg = + (struct ipahal_reg_coal_qmap_cfg *)fields; + + memset(qmap_cfg, 0, sizeof(*qmap_cfg)); + + qmap_cfg->mux_id_byte_sel = IPA_GETFIELD_FROM_REG(val, + IPA_COAL_QMAP_CFG_SHFT, IPA_COAL_QMAP_CFG_BMSK); +} + +static void ipareg_construct_coal_master_cfg(enum ipahal_reg_name reg, + const void *fields, u32 *val) +{ + struct ipahal_reg_coal_master_cfg *master_cfg = + (struct ipahal_reg_coal_master_cfg *)fields; + + IPA_SETFIELD_IN_REG(*val, master_cfg->coal_ipv4_id_ignore, + IPA_COAL_MASTER_CFG_IPV4_ID_IGNORE_EN_SHFT, + IPA_COAL_MASTER_CFG_IPV4_ID_IGNORE_EN_BMSK); + + IPA_SETFIELD_IN_REG(*val, master_cfg->coal_enhanced_ipv4_id_en, + IPA_COAL_MASTER_CFG_ENHANCED_IPV4_ID_EN_SHFT, + IPA_COAL_MASTER_CFG_ENHANCED_IPV4_ID_EN_BMSK); + + IPA_SETFIELD_IN_REG(*val, master_cfg->coal_force_to_default, + IPA_COAL_MASTER_CFG_FORCE_TO_DEFAULT_EN_SHFT, + IPA_COAL_MASTER_CFG_FORCE_TO_DEFAULT_EN_BMSK); +} + +static void ipareg_parse_coal_master_cfg(enum ipahal_reg_name reg, + void *fields, u32 val) +{ + struct ipahal_reg_coal_master_cfg *master_cfg = + (struct ipahal_reg_coal_master_cfg *)fields; + + memset(master_cfg, 0, sizeof(*master_cfg)); + + master_cfg->coal_ipv4_id_ignore = IPA_GETFIELD_FROM_REG(val, + IPA_COAL_MASTER_CFG_IPV4_ID_IGNORE_EN_SHFT, + IPA_COAL_MASTER_CFG_IPV4_ID_IGNORE_EN_BMSK); + + master_cfg->coal_enhanced_ipv4_id_en = IPA_GETFIELD_FROM_REG(val, + IPA_COAL_MASTER_CFG_ENHANCED_IPV4_ID_EN_SHFT, + IPA_COAL_MASTER_CFG_ENHANCED_IPV4_ID_EN_BMSK); + + master_cfg->coal_force_to_default = IPA_GETFIELD_FROM_REG(val, + IPA_COAL_MASTER_CFG_FORCE_TO_DEFAULT_EN_SHFT, + IPA_COAL_MASTER_CFG_FORCE_TO_DEFAULT_EN_BMSK); +} + +static void ipareg_parse_ipa_flavor_0(enum ipahal_reg_name reg, + void *fields, u32 val) +{ + struct ipahal_ipa_flavor_0 *ipa_flavor = + (struct ipahal_ipa_flavor_0 *)fields; + + memset(ipa_flavor, 0, sizeof(*ipa_flavor)); + + ipa_flavor->ipa_pipes = IPA_GETFIELD_FROM_REG(val, + IPA_FLAVOR_0_IPA_PIPES_SHFT, + IPA_FLAVOR_0_IPA_PIPES_BMSK); + ipa_flavor->ipa_cons_pipes = IPA_GETFIELD_FROM_REG(val, + IPA_FLAVOR_0_IPA_CONS_PIPES_SHFT, + IPA_FLAVOR_0_IPA_CONS_PIPES_BMSK); + ipa_flavor->ipa_prod_pipes = IPA_GETFIELD_FROM_REG(val, + IPA_FLAVOR_0_IPA_PROD_PIPES_SHFT, + IPA_FLAVOR_0_IPA_PROD_PIPES_BMSK); + ipa_flavor->ipa_prod_lowest = IPA_GETFIELD_FROM_REG(val, + IPA_FLAVOR_0_IPA_PROD_LOWEST_SHFT, + IPA_FLAVOR_0_IPA_PROD_LOWEST_BMSK); +} + +static void ipareg_parse_ipa_flavor_9(enum ipahal_reg_name reg, + void *fields, u32 val) +{ + struct ipahal_ipa_flavor_9 *ipa_flavor = + (struct ipahal_ipa_flavor_9 *)fields; + + memset(ipa_flavor, 0, sizeof(*ipa_flavor)); + + ipa_flavor->ipa_tsp_max_ingr_tc = IPA_GETFIELD_FROM_REG(val, + IPA_FLAVOR_9_IPA_TSP_MAX_INGR_TC_SHFT, + IPA_FLAVOR_9_IPA_TSP_MAX_INGR_TC_BMSK); + ipa_flavor->ipa_tsp_max_egr_tc = IPA_GETFIELD_FROM_REG(val, + IPA_FLAVOR_9_IPA_TSP_MAX_EGR_TC_SHFT, + IPA_FLAVOR_9_IPA_TSP_MAX_EGR_TC_BMSK); + ipa_flavor->ipa_tsp_max_prod = IPA_GETFIELD_FROM_REG(val, + IPA_FLAVOR_9_IPA_TSP_MAX_PROD_SHFT, + IPA_FLAVOR_9_IPA_TSP_MAX_PROD_BMSK); +} + +static void ipareg_parse_state_tsp(enum ipahal_reg_name reg, + void *fields, u32 val) +{ + struct ipahal_ipa_state_tsp *state_tsp = + (struct ipahal_ipa_state_tsp *)fields; + + memset(state_tsp, 0, sizeof(*state_tsp)); + + state_tsp->traffic_shaper_idle = IPA_GETFIELD_FROM_REG(val, + IPA_STATE_TSP_TRAFFIC_SHAPER_IDLE_SHFT, + IPA_STATE_TSP_TRAFFIC_SHAPER_IDLE_BMSK); + state_tsp->traffic_shaper_fifo_empty = IPA_GETFIELD_FROM_REG(val, + IPA_STATE_TSP_TRAFFIC_SHAPER_FIFO_EMPTY_SHFT, + IPA_STATE_TSP_TRAFFIC_SHAPER_FIFO_EMPTY_BMSK); + state_tsp->queue_mngr_idle = IPA_GETFIELD_FROM_REG(val, + IPA_STATE_TSP_QUEUE_MNGR_IDLE_SHFT, + IPA_STATE_TSP_QUEUE_MNGR_IDLE_BMSK); + state_tsp->queue_mngr_head_idle = IPA_GETFIELD_FROM_REG(val, + IPA_STATE_TSP_QUEUE_MNGR_HEAD_IDLE_SHFT, + IPA_STATE_TSP_QUEUE_MNGR_HEAD_IDLE_BMSK); + state_tsp->queue_mngr_shared_idle = IPA_GETFIELD_FROM_REG(val, + IPA_STATE_TSP_QUEUE_MNGR_SHARED_IDLE_SHFT, + IPA_STATE_TSP_QUEUE_MNGR_SHARED_IDLE_BMSK); + state_tsp->queue_mngr_tail_idle = IPA_GETFIELD_FROM_REG(val, + IPA_STATE_TSP_QUEUE_MNGR_TAIL_IDLE_SHFT, + IPA_STATE_TSP_QUEUE_MNGR_TAIL_IDLE_BMSK); + state_tsp->queue_mngr_block_ctrl_idle = IPA_GETFIELD_FROM_REG(val, + IPA_STATE_TSP_QUEUE_MNGR_BLOCK_CTRL_IDLE_SHFT, + IPA_STATE_TSP_QUEUE_MNGR_BLOCK_CTRL_IDLE_BMSK); +} + +static void ipareg_construct_nat_uc_external_cfg(enum ipahal_reg_name reg, + const void *fields, u32 *val) +{ + struct ipahal_reg_nat_uc_external_cfg *nat_uc_external_cfg = + (struct ipahal_reg_nat_uc_external_cfg *)fields; + + IPA_SETFIELD_IN_REG(*val, + nat_uc_external_cfg->nat_uc_external_table_addr_lsb, + IPA_NAT_UC_EXTERNAL_CFG_SHFT, IPA_NAT_UC_EXTERNAL_CFG_BMSK); +} + +static void ipareg_parse_nat_uc_external_cfg(enum ipahal_reg_name reg, + void *fields, u32 val) +{ + struct ipahal_reg_nat_uc_external_cfg *nat_uc_external_cfg = + (struct ipahal_reg_nat_uc_external_cfg *)fields; + + memset(nat_uc_external_cfg, 0, sizeof(*nat_uc_external_cfg)); + + nat_uc_external_cfg->nat_uc_external_table_addr_lsb = + IPA_GETFIELD_FROM_REG(val, IPA_NAT_UC_EXTERNAL_CFG_SHFT, + IPA_NAT_UC_EXTERNAL_CFG_BMSK); +} + +static void ipareg_construct_nat_uc_local_cfg(enum ipahal_reg_name reg, + const void *fields, u32 *val) +{ + struct ipahal_reg_nat_uc_local_cfg *nat_uc_local_cfg = + (struct ipahal_reg_nat_uc_local_cfg *)fields; + + IPA_SETFIELD_IN_REG(*val, nat_uc_local_cfg->nat_uc_local_table_addr_lsb, + IPA_NAT_UC_LOCAL_CFG_SHFT, IPA_NAT_UC_LOCAL_CFG_BMSK); +} + +static void ipareg_parse_nat_uc_local_cfg(enum ipahal_reg_name reg, + void *fields, u32 val) +{ + struct ipahal_reg_nat_uc_local_cfg *nat_uc_local_cfg = + (struct ipahal_reg_nat_uc_local_cfg *)fields; + + memset(nat_uc_local_cfg, 0, sizeof(*nat_uc_local_cfg)); + + nat_uc_local_cfg->nat_uc_local_table_addr_lsb = + IPA_GETFIELD_FROM_REG(val, IPA_NAT_UC_LOCAL_CFG_SHFT, + IPA_NAT_UC_LOCAL_CFG_BMSK); +} + +static void ipareg_construct_nat_uc_shared_cfg(enum ipahal_reg_name reg, + const void *fields, u32 *val) +{ + struct ipahal_reg_nat_uc_shared_cfg *nat_uc_shared_cfg = + (struct ipahal_reg_nat_uc_shared_cfg *)fields; + + IPA_SETFIELD_IN_REG(*val, + nat_uc_shared_cfg->nat_uc_local_table_addr_msb, + IPA_NAT_UC_SHARED_CFG_LOCAL_TABLE_ADDR_MSB_SHFT, + IPA_NAT_UC_SHARED_CFG_LOCAL_TABLE_ADDR_MSB_BMSK); + + IPA_SETFIELD_IN_REG(*val, + nat_uc_shared_cfg->nat_uc_external_table_addr_msb, + IPA_NAT_UC_SHARED_CFG_EXTERNAL_TABLE_ADDR_MSB_SHFT, + IPA_NAT_UC_SHARED_CFG_EXTERNAL_TABLE_ADDR_MSB_BMSK); +} + +static void ipareg_parse_nat_uc_shared_cfg(enum ipahal_reg_name reg, + void *fields, u32 val) +{ + struct ipahal_reg_nat_uc_shared_cfg *nat_uc_shared_cfg = + (struct ipahal_reg_nat_uc_shared_cfg *)fields; + + memset(nat_uc_shared_cfg, 0, sizeof(*nat_uc_shared_cfg)); + + nat_uc_shared_cfg->nat_uc_local_table_addr_msb = + IPA_GETFIELD_FROM_REG(val, + IPA_NAT_UC_SHARED_CFG_LOCAL_TABLE_ADDR_MSB_SHFT, + IPA_NAT_UC_SHARED_CFG_LOCAL_TABLE_ADDR_MSB_BMSK); + + nat_uc_shared_cfg->nat_uc_external_table_addr_msb = + IPA_GETFIELD_FROM_REG(val, + IPA_NAT_UC_SHARED_CFG_EXTERNAL_TABLE_ADDR_MSB_SHFT, + IPA_NAT_UC_SHARED_CFG_EXTERNAL_TABLE_ADDR_MSB_BMSK); +} + +static void ipareg_construct_conn_track_uc_external_cfg + (enum ipahal_reg_name reg, const void *fields, u32 *val) +{ + struct ipahal_reg_conn_track_uc_external_cfg *conn_track_uc_external_cfg + = (struct ipahal_reg_conn_track_uc_external_cfg *)fields; + + IPA_SETFIELD_IN_REG(*val, + conn_track_uc_external_cfg->conn_track_uc_external_table_addr_lsb, + IPA_CONN_TRACK_UC_EXTERNAL_CFG_SHFT, + IPA_CONN_TRACK_UC_EXTERNAL_CFG_BMSK); +} + +static void ipareg_parse_conn_track_uc_external_cfg(enum ipahal_reg_name reg, + void *fields, u32 val) +{ + struct ipahal_reg_conn_track_uc_external_cfg *conn_track_uc_external_cfg + = (struct ipahal_reg_conn_track_uc_external_cfg *)fields; + + memset(conn_track_uc_external_cfg, 0, + sizeof(*conn_track_uc_external_cfg)); + + conn_track_uc_external_cfg->conn_track_uc_external_table_addr_lsb = + IPA_GETFIELD_FROM_REG(val, IPA_CONN_TRACK_UC_EXTERNAL_CFG_SHFT, + IPA_CONN_TRACK_UC_EXTERNAL_CFG_BMSK); +} + +static void ipareg_construct_conn_track_uc_local_cfg(enum ipahal_reg_name reg, + const void *fields, u32 *val) +{ + struct ipahal_reg_conn_track_uc_local_cfg *conn_track_uc_local_cfg = + (struct ipahal_reg_conn_track_uc_local_cfg *)fields; + + IPA_SETFIELD_IN_REG(*val, + conn_track_uc_local_cfg->conn_track_uc_local_table_addr_lsb, + IPA_CONN_TRACK_UC_LOCAL_CFG_SHFT, + IPA_CONN_TRACK_UC_LOCAL_CFG_BMSK); +} + +static void ipareg_parse_conn_track_uc_local_cfg(enum ipahal_reg_name reg, + void *fields, u32 val) +{ + struct ipahal_reg_conn_track_uc_local_cfg *conn_track_uc_local_cfg = + (struct ipahal_reg_conn_track_uc_local_cfg *)fields; + + memset(conn_track_uc_local_cfg, 0, sizeof(*conn_track_uc_local_cfg)); + + conn_track_uc_local_cfg->conn_track_uc_local_table_addr_lsb = + IPA_GETFIELD_FROM_REG(val, IPA_CONN_TRACK_UC_LOCAL_CFG_SHFT, + IPA_CONN_TRACK_UC_LOCAL_CFG_BMSK); +} + +static void ipareg_construct_conn_track_uc_shared_cfg(enum ipahal_reg_name reg, + const void *fields, u32 *val) +{ + struct ipahal_reg_conn_track_uc_shared_cfg *conn_track_uc_shared_cfg = + (struct ipahal_reg_conn_track_uc_shared_cfg *)fields; + + IPA_SETFIELD_IN_REG(*val, + conn_track_uc_shared_cfg->conn_track_uc_local_table_addr_msb, + IPA_CONN_TRACK_UC_SHARED_CFG_LOCAL_TABLE_ADDR_MSB_SHFT, + IPA_CONN_TRACK_UC_SHARED_CFG_LOCAL_TABLE_ADDR_MSB_BMSK); + + IPA_SETFIELD_IN_REG(*val, + conn_track_uc_shared_cfg->conn_track_uc_external_table_addr_msb, + IPA_CONN_TRACK_UC_SHARED_CFG_EXTERNAL_TABLE_ADDR_MSB_SHFT, + IPA_CONN_TRACK_UC_SHARED_CFG_EXTERNAL_TABLE_ADDR_MSB_BMSK); +} + +static void ipareg_parse_conn_track_uc_shared_cfg(enum ipahal_reg_name reg, + void *fields, u32 val) +{ + struct ipahal_reg_conn_track_uc_shared_cfg *conn_track_uc_shared_cfg = + (struct ipahal_reg_conn_track_uc_shared_cfg *)fields; + + memset(conn_track_uc_shared_cfg, 0, sizeof(*conn_track_uc_shared_cfg)); + + conn_track_uc_shared_cfg->conn_track_uc_local_table_addr_msb = + IPA_GETFIELD_FROM_REG(val, + IPA_CONN_TRACK_UC_SHARED_CFG_LOCAL_TABLE_ADDR_MSB_SHFT, + IPA_CONN_TRACK_UC_SHARED_CFG_LOCAL_TABLE_ADDR_MSB_BMSK); + + conn_track_uc_shared_cfg->conn_track_uc_external_table_addr_msb = + IPA_GETFIELD_FROM_REG(val, + IPA_CONN_TRACK_UC_SHARED_CFG_EXTERNAL_TABLE_ADDR_MSB_SHFT, + IPA_CONN_TRACK_UC_SHARED_CFG_EXTERNAL_TABLE_ADDR_MSB_BMSK); +} + +/* + * struct ipahal_reg_obj - Register H/W information for specific IPA version + * @construct - CB to construct register value from abstracted structure + * @parse - CB to parse register value to abstracted structure + * @offset - register offset relative to base address + * @n_ofst - N parameterized register sub-offset + * @n_start - starting n for n_registers used for printing + * @n_end - ending n for n_registers used for printing + * @en_print - enable this register to be printed when the device crashes + */ +struct ipahal_reg_obj { + void (*construct)(enum ipahal_reg_name reg, const void *fields, + u32 *val); + void (*parse)(enum ipahal_reg_name reg, void *fields, + u32 val); + u32 offset; + u32 n_ofst; + int n_start; + int n_end; + bool en_print; + u32 m_ofst; +}; + +/* + * This table contains the info regarding each register for IPAv3 and later. + * Information like: offset and construct/parse functions. + * All the information on the register on IPAv3 are statically defined below. + * If information is missing regarding some register on some IPA version, + * the init function will fill it with the information from the previous + * IPA version. + * Information is considered missing if all of the fields are 0. + * If offset is -1, this means that the register is removed on the + * specific version. + */ +static struct ipahal_reg_obj ipahal_reg_objs[IPA_HW_MAX][IPA_REG_MAX] = { + /* IPAv3 */ + [IPA_HW_v3_0][IPA_ROUTE] = { + ipareg_construct_route, ipareg_parse_dummy, + 0x00000048, 0, 0, 0, 0, 0}, + [IPA_HW_v3_0][IPA_IRQ_STTS_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00003008, 0x1000, 0, 0, 0, 0}, + [IPA_HW_v3_0][IPA_IRQ_EN_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000300c, 0x1000, 0, 0, 0, 0}, + [IPA_HW_v3_0][IPA_IRQ_CLR_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00003010, 0x1000, 0, 0, 0, 0}, + [IPA_HW_v3_0][IPA_SUSPEND_IRQ_INFO_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00003098, 0x1000, 0, 0, 0, 0}, + [IPA_HW_v3_0][IPA_BCR] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000001D0, 0, 0, 0, 0, 0}, + [IPA_HW_v3_0][IPA_ENABLED_PIPES] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000038, 0, 0, 0, 0, 0}, + [IPA_HW_v3_0][IPA_VERSION] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000034, 0, 0, 0, 0, 0}, + [IPA_HW_v3_0][IPA_TAG_TIMER] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000060, 0, 0, 0, 0, 0}, + [IPA_HW_v3_0][IPA_COMP_HW_VERSION] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000030, 0, 0, 0, 0, 0}, + [IPA_HW_v3_0][IPA_COMP_CFG] = { + ipareg_construct_comp_cfg, ipareg_parse_comp_cfg, + 0x0000003C, 0, 0, 0, 0, 0}, + [IPA_HW_v3_0][IPA_STATE_AGGR_ACTIVE] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000010C, 0, 0, 0, 0, 0}, + [IPA_HW_v3_0][IPA_ENDP_INIT_HDR_n] = { + ipareg_construct_endp_init_hdr_n, ipareg_parse_dummy, + 0x00000810, 0x70, 0, 0, 0, 0}, + [IPA_HW_v3_0][IPA_ENDP_INIT_HDR_EXT_n] = { + ipareg_construct_endp_init_hdr_ext_n, ipareg_parse_dummy, + 0x00000814, 0x70, 0, 0, 0, 0}, + [IPA_HW_v3_0][IPA_ENDP_INIT_AGGR_n] = { + ipareg_construct_endp_init_aggr_n, + ipareg_parse_endp_init_aggr_n, + 0x00000824, 0x70, 0, 0, 0, 0}, + [IPA_HW_v3_0][IPA_AGGR_FORCE_CLOSE] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000001EC, 0, 0, 0, 0, 0}, + [IPA_HW_v3_0][IPA_ENDP_INIT_ROUTE_n] = { + ipareg_construct_endp_init_route_n, ipareg_parse_dummy, + 0x00000828, 0x70, 0, 0, 0, 0}, + [IPA_HW_v3_0][IPA_ENDP_INIT_MODE_n] = { + ipareg_construct_endp_init_mode_n, ipareg_parse_dummy, + 0x00000820, 0x70, 0, 0, 0, 0}, + [IPA_HW_v3_0][IPA_ENDP_INIT_NAT_n] = { + ipareg_construct_endp_init_nat_n, ipareg_parse_dummy, + 0x0000080C, 0x70, 0, 0, 0, 0}, + [IPA_HW_v3_0][IPA_ENDP_INIT_CTRL_n] = { + ipareg_construct_endp_init_ctrl_n, + ipareg_parse_endp_init_ctrl_n, + 0x00000800, 0x70, 0, 0, 0, 0}, + [IPA_HW_v3_0][IPA_ENDP_INIT_CTRL_SCND_n] = { + ipareg_construct_endp_init_ctrl_scnd_n, ipareg_parse_dummy, + 0x00000804, 0x70, 0, 0, 0, 0}, + [IPA_HW_v3_0][IPA_ENDP_INIT_HOL_BLOCK_EN_n] = { + ipareg_construct_endp_init_hol_block_en_n, + ipareg_parse_dummy, + 0x0000082c, 0x70, 0, 0, 0, 0}, + [IPA_HW_v3_0][IPA_ENDP_INIT_HOL_BLOCK_TIMER_n] = { + ipareg_construct_endp_init_hol_block_timer_n, + ipareg_parse_dummy, + 0x00000830, 0x70, 0, 0, 0, 0}, + [IPA_HW_v3_0][IPA_ENDP_INIT_DEAGGR_n] = { + ipareg_construct_endp_init_deaggr_n, + ipareg_parse_dummy, + 0x00000834, 0x70, 0, 0, 0, 0}, + [IPA_HW_v3_0][IPA_ENDP_INIT_SEQ_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000083C, 0x70, 0, 0, 0, 0}, + [IPA_HW_v3_0][IPA_DEBUG_CNT_REG_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000600, 0x4, 0, 0, 0, 0}, + [IPA_HW_v3_0][IPA_ENDP_INIT_CFG_n] = { + ipareg_construct_endp_init_cfg_n, ipareg_parse_dummy, + 0x00000808, 0x70, 0, 0, 0, 0}, + [IPA_HW_v3_0][IPA_IRQ_EE_UC_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000301c, 0x1000, 0, 0, 0, 0}, + [IPA_HW_v3_0][IPA_ENDP_INIT_HDR_METADATA_MASK_n] = { + ipareg_construct_endp_init_hdr_metadata_mask_n, + ipareg_parse_dummy, + 0x00000818, 0x70, 0, 0, 0, 0}, + [IPA_HW_v3_0][IPA_ENDP_INIT_HDR_METADATA_n] = { + ipareg_construct_endp_init_hdr_metadata_n, + ipareg_parse_dummy, + 0x0000081c, 0x70, 0, 0, 0, 0}, + [IPA_HW_v3_0][IPA_ENDP_INIT_RSRC_GRP_n] = { + ipareg_construct_endp_init_rsrc_grp_n, + ipareg_parse_dummy, + 0x00000838, 0x70, 0, 0, 0, 0}, + [IPA_HW_v3_0][IPA_SHARED_MEM_SIZE] = { + ipareg_construct_dummy, ipareg_parse_shared_mem_size, + 0x00000054, 0, 0, 0, 0, 0}, + [IPA_HW_v3_0][IPA_SW_AREA_RAM_DIRECT_ACCESS_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00007000, 0x4, 0, 0, 0, 0}, + [IPA_HW_v3_0][IPA_DEBUG_CNT_CTRL_n] = { + ipareg_construct_debug_cnt_ctrl_n, ipareg_parse_dummy, + 0x00000640, 0x4, 0, 0, 0, 0}, + [IPA_HW_v3_0][IPA_UC_MAILBOX_m_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00032000, 0x4, 0, 0, 0, 0x80}, + [IPA_HW_v3_0][IPA_FILT_ROUT_HASH_FLUSH] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000090, 0, 0, 0, 0, 0}, + [IPA_HW_v3_0][IPA_SINGLE_NDP_MODE] = { + ipareg_construct_single_ndp_mode, ipareg_parse_single_ndp_mode, + 0x00000068, 0, 0, 0, 0, 0}, + [IPA_HW_v3_0][IPA_QCNCM] = { + ipareg_construct_qcncm, ipareg_parse_qcncm, + 0x00000064, 0, 0, 0, 0, 0}, + [IPA_HW_v3_0][IPA_SYS_PKT_PROC_CNTXT_BASE] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000001e0, 0, 0, 0, 0, 0}, + [IPA_HW_v3_0][IPA_LOCAL_PKT_PROC_CNTXT_BASE] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000001e8, 0, 0, 0, 0, 0}, + [IPA_HW_v3_0][IPA_ENDP_STATUS_n] = { + ipareg_construct_endp_status_n, ipareg_parse_dummy, + 0x00000840, 0x70, 0, 0, 0, 0}, + [IPA_HW_v3_0][IPA_ENDP_FILTER_ROUTER_HSH_CFG_n] = { + ipareg_construct_hash_cfg_n, ipareg_parse_hash_cfg_n, + 0x0000085C, 0x70, 0, 0, 0, 0}, + [IPA_HW_v3_0][IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n] = { + ipareg_construct_rsrg_grp_xy, ipareg_parse_dummy, + 0x00000400, 0x20, 0, 0, 0, 0}, + [IPA_HW_v3_0][IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n] = { + ipareg_construct_rsrg_grp_xy, ipareg_parse_dummy, + 0x00000404, 0x20, 0, 0, 0, 0}, + [IPA_HW_v3_0][IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n] = { + ipareg_construct_rsrg_grp_xy, ipareg_parse_dummy, + 0x00000408, 0x20, 0, 0, 0, 0}, + [IPA_HW_v3_0][IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n] = { + ipareg_construct_rsrg_grp_xy, ipareg_parse_dummy, + 0x0000040C, 0x20, 0, 0, 0, 0}, + [IPA_HW_v3_0][IPA_DST_RSRC_GRP_01_RSRC_TYPE_n] = { + ipareg_construct_rsrg_grp_xy, ipareg_parse_dummy, + 0x00000500, 0x20, 0, 0, 0, 0}, + [IPA_HW_v3_0][IPA_DST_RSRC_GRP_23_RSRC_TYPE_n] = { + ipareg_construct_rsrg_grp_xy, ipareg_parse_dummy, + 0x00000504, 0x20, 0, 0, 0, 0}, + [IPA_HW_v3_0][IPA_DST_RSRC_GRP_45_RSRC_TYPE_n] = { + ipareg_construct_rsrg_grp_xy, ipareg_parse_dummy, + 0x00000508, 0x20, 0, 0, 0, 0}, + [IPA_HW_v3_0][IPA_DST_RSRC_GRP_67_RSRC_TYPE_n] = { + ipareg_construct_rsrg_grp_xy, ipareg_parse_dummy, + 0x0000050c, 0x20, 0, 0, 0, 0}, + [IPA_HW_v3_0][IPA_RX_HPS_CLIENTS_MIN_DEPTH_0] = { + ipareg_construct_rx_hps_clients_depth0, ipareg_parse_dummy, + 0x000023C4, 0, 0, 0, 0, 0}, + [IPA_HW_v3_0][IPA_RX_HPS_CLIENTS_MIN_DEPTH_1] = { + ipareg_construct_rx_hps_clients_depth1, ipareg_parse_dummy, + 0x000023C8, 0, 0, 0, 0, 0}, + [IPA_HW_v3_0][IPA_RX_HPS_CLIENTS_MAX_DEPTH_0] = { + ipareg_construct_rx_hps_clients_depth0, ipareg_parse_dummy, + 0x000023CC, 0, 0, 0, 0, 0}, + [IPA_HW_v3_0][IPA_RX_HPS_CLIENTS_MAX_DEPTH_1] = { + ipareg_construct_rx_hps_clients_depth1, ipareg_parse_dummy, + 0x000023D0, 0, 0, 0, 0, 0}, + [IPA_HW_v3_0][IPA_QSB_MAX_WRITES] = { + ipareg_construct_qsb_max_writes, ipareg_parse_qsb_max_writes, + 0x00000074, 0, 0, 0, 0, 0}, + [IPA_HW_v3_0][IPA_QSB_MAX_READS] = { + ipareg_construct_qsb_max_reads, ipareg_parse_qsb_max_reads, + 0x00000078, 0, 0, 0, 0, 0}, + [IPA_HW_v3_0][IPA_DPS_SEQUENCER_FIRST] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0001e000, 0, 0, 0, 0, 0}, + [IPA_HW_v3_0][IPA_DPS_SEQUENCER_LAST] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0001e07c, 0, 0, 0, 0, 0}, + [IPA_HW_v3_0][IPA_HPS_SEQUENCER_FIRST] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0001e080, 0, 0, 0, 0, 0}, + [IPA_HW_v3_0][IPA_HPS_SEQUENCER_LAST] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0001e26c, 0, 0, 0, 0, 0}, + + + /* IPAv3.1 */ + [IPA_HW_v3_1][IPA_SUSPEND_IRQ_INFO_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00003030, 0x1000, 0, 0, 0, 0}, + [IPA_HW_v3_1][IPA_SUSPEND_IRQ_EN_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00003034, 0x1000, 0, 0, 0, 0}, + [IPA_HW_v3_1][IPA_SUSPEND_IRQ_CLR_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00003038, 0x1000, 0, 0, 0, 0}, + + + /* IPAv3.5 */ + [IPA_HW_v3_5][IPA_TX_CFG] = { + ipareg_construct_tx_cfg, ipareg_parse_tx_cfg, + 0x000001FC, 0, 0, 0, 0, 0}, + [IPA_HW_v3_5][IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n] = { + ipareg_construct_rsrg_grp_xy_v3_5, ipareg_parse_dummy, + 0x00000400, 0x20, 0, 0, 0, 0}, + [IPA_HW_v3_5][IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n] = { + ipareg_construct_rsrg_grp_xy_v3_5, ipareg_parse_dummy, + 0x00000404, 0x20, 0, 0, 0, 0}, + [IPA_HW_v3_5][IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0, 0, 0, 0, 0}, + [IPA_HW_v3_5][IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0, 0, 0, 0, 0}, + [IPA_HW_v3_5][IPA_DST_RSRC_GRP_01_RSRC_TYPE_n] = { + ipareg_construct_rsrg_grp_xy_v3_5, ipareg_parse_dummy, + 0x00000500, 0x20, 0, 0, 0, 0}, + [IPA_HW_v3_5][IPA_DST_RSRC_GRP_23_RSRC_TYPE_n] = { + ipareg_construct_rsrg_grp_xy_v3_5, ipareg_parse_dummy, + 0x00000504, 0x20, 0, 0, 0, 0}, + [IPA_HW_v3_5][IPA_DST_RSRC_GRP_45_RSRC_TYPE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0, 0, 0, 0, 0}, + [IPA_HW_v3_5][IPA_DST_RSRC_GRP_67_RSRC_TYPE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0, 0, 0, 0, 0}, + [IPA_HW_v3_5][IPA_ENDP_INIT_RSRC_GRP_n] = { + ipareg_construct_endp_init_rsrc_grp_n_v3_5, + ipareg_parse_dummy, + 0x00000838, 0x70, 0, 0, 0, 0}, + [IPA_HW_v3_5][IPA_RX_HPS_CLIENTS_MIN_DEPTH_0] = { + ipareg_construct_rx_hps_clients_depth0_v3_5, + ipareg_parse_dummy, + 0x000023C4, 0, 0, 0, 0, 0}, + [IPA_HW_v3_5][IPA_RX_HPS_CLIENTS_MIN_DEPTH_1] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0, 0, 0, 0, 0}, + [IPA_HW_v3_5][IPA_RX_HPS_CLIENTS_MAX_DEPTH_0] = { + ipareg_construct_rx_hps_clients_depth0_v3_5, + ipareg_parse_dummy, + 0x000023CC, 0, 0, 0, 0, 0}, + [IPA_HW_v3_5][IPA_RX_HPS_CLIENTS_MAX_DEPTH_1] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0, 0, 0, 0, 0}, + [IPA_HW_v3_5][IPA_IDLE_INDICATION_CFG] = { + ipareg_construct_idle_indication_cfg, ipareg_parse_dummy, + 0x00000220, 0, 0, 0, 0, 0}, + [IPA_HW_v3_5][IPA_HPS_FTCH_ARB_QUEUE_WEIGHT] = { + ipareg_construct_hps_queue_weights, + ipareg_parse_hps_queue_weights, 0x000005a4, 0, 0, 0, 0, 0}, + [IPA_HW_v3_5][IPA_COUNTER_CFG] = { + ipareg_construct_counter_cfg, ipareg_parse_counter_cfg, + 0x000001F0, 0, 0, 0, 0, 0}, + [IPA_HW_v3_5][IPA_ENDP_GSI_CFG1_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00002794, 0x4, 0, 0, 0, 0}, + [IPA_HW_v3_5][IPA_ENDP_GSI_CFG_AOS_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000029A8, 0x4, 0, 0, 0, 0}, + [IPA_HW_v3_5][IPA_ENDP_GSI_CFG_TLV_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00002924, 0x4, 0, 0, 0, 0}, + [IPA_HW_v3_5][IPA_HPS_SEQUENCER_LAST] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0001e1fc, 0, 0, 0, 0, 0}, + + /* IPAv4.0 */ + [IPA_HW_v4_0][IPA_SUSPEND_IRQ_INFO_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00003030, 0x1000, 0, 0, 1, 0}, + [IPA_HW_v4_0][IPA_SUSPEND_IRQ_EN_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00003034, 0x1000, 0, 0, 1, 0}, + [IPA_HW_v4_0][IPA_SUSPEND_IRQ_CLR_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00003038, 0x1000, 0, 0, 1, 0}, + [IPA_HW_v4_0][IPA_IRQ_EN_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000300c, 0x1000, 0, 0, 1, 0}, + [IPA_HW_v4_0][IPA_TAG_TIMER] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000060, 0, 0, 0, 1, 0}, + [IPA_HW_v4_0][IPA_ENDP_INIT_CTRL_n] = { + ipareg_construct_endp_init_ctrl_n_v4_0, ipareg_parse_dummy, + 0x00000800, 0x70, 0, 22, 1, 0}, + [IPA_HW_v4_0][IPA_ENDP_INIT_HDR_EXT_n] = { + ipareg_construct_endp_init_hdr_ext_n, ipareg_parse_dummy, + 0x00000814, 0x70, 0, 22, 1, 0}, + [IPA_HW_v4_0][IPA_ENDP_INIT_AGGR_n] = { + ipareg_construct_endp_init_aggr_n, + ipareg_parse_endp_init_aggr_n, + 0x00000824, 0x70, 0, 22, 1, 0}, + [IPA_HW_v4_0][IPA_TX_CFG] = { + ipareg_construct_tx_cfg_v4_0, ipareg_parse_tx_cfg_v4_0, + 0x000001FC, 0, 0, 0, 0, 0}, + [IPA_HW_v4_0][IPA_DEBUG_CNT_REG_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0, 0, 0, 0, 0}, + [IPA_HW_v4_0][IPA_DEBUG_CNT_CTRL_n] = { + ipareg_construct_debug_cnt_ctrl_n, ipareg_parse_dummy, + -1, 0, 0, 0, 0, 0}, + [IPA_HW_v4_0][IPA_QCNCM] = { + ipareg_construct_qcncm, ipareg_parse_qcncm, + -1, 0, 0, 0, 0, 0}, + [IPA_HW_v4_0][IPA_SINGLE_NDP_MODE] = { + ipareg_construct_single_ndp_mode, ipareg_parse_single_ndp_mode, + -1, 0, 0, 0, 0, 0}, + [IPA_HW_v4_0][IPA_QSB_MAX_READS] = { + ipareg_construct_qsb_max_reads_v4_0, ipareg_parse_qsb_max_reads, + 0x00000078, 0, 0, 0, 0, 0}, + [IPA_HW_v4_0][IPA_FILT_ROUT_HASH_FLUSH] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000014c, 0, 0, 0, 0, 0}, + [IPA_HW_v4_0][IPA_ENDP_INIT_HDR_n] = { + ipareg_construct_endp_init_hdr_n, ipareg_parse_dummy, + 0x00000810, 0x70, 0, 22, 1, 0}, + [IPA_HW_v4_0][IPA_ENDP_INIT_ROUTE_n] = { + ipareg_construct_endp_init_route_n, ipareg_parse_dummy, + -1, 0, 0, 0, 0, 0}, + [IPA_HW_v4_0][IPA_ENDP_INIT_MODE_n] = { + ipareg_construct_endp_init_mode_n, ipareg_parse_dummy, + 0x00000820, 0x70, 0, 9, 1, 0}, + [IPA_HW_v4_0][IPA_ENDP_INIT_NAT_n] = { + ipareg_construct_endp_init_nat_n, ipareg_parse_dummy, + 0x0000080C, 0x70, 0, 9, 1, 0}, + [IPA_HW_v4_0][IPA_ENDP_STATUS_n] = { + ipareg_construct_endp_status_n_v4_0, ipareg_parse_dummy, + 0x00000840, 0x70, 0, 22, 1, 0}, + [IPA_HW_v4_0][IPA_ENDP_FILTER_ROUTER_HSH_CFG_n] = { + ipareg_construct_hash_cfg_n, ipareg_parse_hash_cfg_n, + 0x0000085C, 0x70, 0, 31, 1, 0}, + [IPA_HW_v4_0][IPA_ENDP_INIT_CONN_TRACK_n] = { + ipareg_construct_endp_init_conn_track_n, + ipareg_parse_dummy, + 0x00000850, 0x70, 0, 9, 1, 0}, + [IPA_HW_v4_0][IPA_ENDP_INIT_CTRL_SCND_n] = { + ipareg_construct_endp_init_ctrl_scnd_n, ipareg_parse_dummy, + 0x00000804, 0x70, 0, 22, 1, 0}, + [IPA_HW_v4_0][IPA_ENDP_INIT_HOL_BLOCK_EN_n] = { + ipareg_construct_endp_init_hol_block_en_n, + ipareg_parse_dummy, + 0x0000082c, 0x70, 10, 22, 1, 0}, + [IPA_HW_v4_0][IPA_ENDP_INIT_HOL_BLOCK_TIMER_n] = { + ipareg_construct_endp_init_hol_block_timer_n, + ipareg_parse_dummy, + 0x00000830, 0x70, 10, 22, 1, 0}, + [IPA_HW_v4_0][IPA_ENDP_INIT_DEAGGR_n] = { + ipareg_construct_endp_init_deaggr_n, + ipareg_parse_dummy, + 0x00000834, 0x70, 0, 9, 1, 0}, + [IPA_HW_v4_0][IPA_ENDP_INIT_SEQ_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000083C, 0x70, 0, 9, 1, 0}, + [IPA_HW_v4_0][IPA_ENDP_INIT_CFG_n] = { + ipareg_construct_endp_init_cfg_n, ipareg_parse_dummy, + 0x00000808, 0x70, 0, 22, 1, 0}, + [IPA_HW_v4_0][IPA_IRQ_EE_UC_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000301c, 0x1000, 0, 0, 1, 0}, + [IPA_HW_v4_0][IPA_ENDP_INIT_HDR_METADATA_MASK_n] = { + ipareg_construct_endp_init_hdr_metadata_mask_n, + ipareg_parse_dummy, + 0x00000818, 0x70, 10, 22, 1, 0}, + [IPA_HW_v4_0][IPA_ENDP_INIT_HDR_METADATA_n] = { + ipareg_construct_endp_init_hdr_metadata_n, + ipareg_parse_dummy, + 0x0000081c, 0x70, 0, 9, 1, 0}, + [IPA_HW_v4_0][IPA_CLKON_CFG] = { + ipareg_construct_clkon_cfg, ipareg_parse_clkon_cfg, + 0x00000044, 0, 0, 0, 0, 0}, + [IPA_HW_v4_0][IPA_STAT_QUOTA_BASE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000700, 0x4, 0, 0, 0, 0}, + [IPA_HW_v4_0][IPA_STAT_QUOTA_MASK_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000708, 0x4, 0, 0, 0, 0}, + [IPA_HW_v4_0][IPA_STAT_TETHERING_BASE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000710, 0x4, 0, 0, 0, 0}, + [IPA_HW_v4_0][IPA_STAT_TETHERING_MASK_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000718, 0x4, 0, 0, 0, 0}, + [IPA_HW_v4_0][IPA_STAT_FILTER_IPV4_BASE] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000720, 0, 0, 0, 0, 0}, + [IPA_HW_v4_0][IPA_STAT_FILTER_IPV6_BASE] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000724, 0, 0, 0, 0, 0}, + [IPA_HW_v4_0][IPA_STAT_ROUTER_IPV4_BASE] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000728, 0, 0, 0, 0, 0}, + [IPA_HW_v4_0][IPA_STAT_ROUTER_IPV6_BASE] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000072C, 0, 0, 0, 0, 0}, + [IPA_HW_v4_0][IPA_STAT_FILTER_IPV4_START_ID] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000730, 0, 0, 0, 0, 0}, + [IPA_HW_v4_0][IPA_STAT_FILTER_IPV6_START_ID] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000734, 0, 0, 0, 0, 0}, + [IPA_HW_v4_0][IPA_STAT_ROUTER_IPV4_START_ID] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000738, 0, 0, 0, 0, 0}, + [IPA_HW_v4_0][IPA_STAT_ROUTER_IPV6_START_ID] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000073C, 0, 0, 0, 0, 0}, + [IPA_HW_v4_0][IPA_STAT_FILTER_IPV4_END_ID] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000740, 0, 0, 0, 0, 0}, + [IPA_HW_v4_0][IPA_STAT_FILTER_IPV6_END_ID] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000744, 0, 0, 0, 0, 0}, + [IPA_HW_v4_0][IPA_STAT_ROUTER_IPV4_END_ID] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000748, 0, 0, 0, 0, 0}, + [IPA_HW_v4_0][IPA_STAT_ROUTER_IPV6_END_ID] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000074C, 0, 0, 0, 0, 0}, + [IPA_HW_v4_0][IPA_STAT_DROP_CNT_BASE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000750, 0x4, 0, 0, 1, 0}, + [IPA_HW_v4_0][IPA_STAT_DROP_CNT_MASK_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000758, 0x4, 0, 0, 1, 0}, + [IPA_HW_v4_0][IPA_STATE_TX_WRAPPER] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000090, 0, 0, 0, 1, 0}, + [IPA_HW_v4_0][IPA_STATE_TX1] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000094, 0, 0, 0, 1, 0}, + [IPA_HW_v4_0][IPA_STATE_FETCHER] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000098, 0, 0, 0, 1, 0}, + [IPA_HW_v4_0][IPA_STATE_FETCHER_MASK] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000009C, 0, 0, 0, 1, 0}, + [IPA_HW_v4_0][IPA_STATE_DFETCHER] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000000A0, 0, 0, 0, 1, 0}, + [IPA_HW_v4_0][IPA_STATE_ACL] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000000A4, 0, 0, 0, 1, 0}, + [IPA_HW_v4_0][IPA_STATE] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000000A8, 0, 0, 0, 1, 0}, + [IPA_HW_v4_0][IPA_STATE_RX_ACTIVE] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000000AC, 0, 0, 0, 1, 0}, + [IPA_HW_v4_0][IPA_STATE_TX0] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000000B0, 0, 0, 0, 1, 0}, + [IPA_HW_v4_0][IPA_STATE_AGGR_ACTIVE] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000000B4, 0, 0, 0, 1, 0}, + [IPA_HW_v4_0][IPA_STATE_GSI_TLV] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000000B8, 0, 0, 0, 1, 0}, + [IPA_HW_v4_0][IPA_STATE_GSI_AOS] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000000BC, 0, 0, 0, 1, 0}, + [IPA_HW_v4_0][IPA_STATE_GSI_IF] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000000C0, 0, 0, 0, 1, 0}, + [IPA_HW_v4_0][IPA_STATE_GSI_SKIP] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000000C4, 0, 0, 0, 1, 0}, + [IPA_HW_v4_0][IPA_SNOC_FEC_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00003018, 0x1000, 0, 0, 1, 0}, + [IPA_HW_v4_0][IPA_FEC_ADDR_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00003020, 0x1000, 0, 0, 1, 0}, + [IPA_HW_v4_0][IPA_FEC_ADDR_MSB_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00003024, 0x1000, 0, 0, 1, 0}, + [IPA_HW_v4_0][IPA_FEC_ATTR_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00003028, 0x1000, 0, 0, 1, 0}, + [IPA_HW_v4_0][IPA_HOLB_DROP_IRQ_INFO_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000303C, 0x1000, 0, 0, 1, 0}, + [IPA_HW_v4_0][IPA_HOLB_DROP_IRQ_EN_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00003040, 0x1000, 0, 0, 1, 0}, + [IPA_HW_v4_0][IPA_HOLB_DROP_IRQ_CLR_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00003044, 0x1000, 0, 0, 1, 0}, + [IPA_HW_v4_0][IPA_ENDP_INIT_CTRL_STATUS_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000864, 0x70, 0, 22, 1, 0}, + [IPA_HW_v4_0][IPA_ENDP_INIT_PROD_CFG_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000CC8, 0x70, 10, 22, 1, 0}, + [IPA_HW_v4_0][IPA_ENDP_INIT_RSRC_GRP_n] = { + ipareg_construct_endp_init_rsrc_grp_n_v3_5, + ipareg_parse_dummy, + 0x00000838, 0x70, 0, 22, 1, 0}, + [IPA_HW_v4_0][IPA_ENDP_YELLOW_RED_MARKER_CFG_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000CC0, 0x70, 10, 22, 1, 0}, + + /* IPA4.2 */ + [IPA_HW_v4_2][IPA_IDLE_INDICATION_CFG] = { + ipareg_construct_idle_indication_cfg, ipareg_parse_dummy, + 0x00000240, 0, 0, 0, 0, 0}, + [IPA_HW_v4_2][IPA_ENDP_INIT_HOL_BLOCK_TIMER_n] = { + ipareg_construct_endp_init_hol_block_timer_n_v4_2, + ipareg_parse_dummy, + 0x00000830, 0x70, 8, 16, 1, 0}, + [IPA_HW_v4_2][IPA_ENDP_FILTER_ROUTER_HSH_CFG_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0, 0, 0, 0, 0}, + [IPA_HW_v4_2][IPA_HPS_FTCH_ARB_QUEUE_WEIGHT] = { + ipareg_construct_dummy, + ipareg_parse_dummy, -1, 0, 0, 0, 0, 0}, + [IPA_HW_v4_2][IPA_FILT_ROUT_HASH_EN] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000148, 0, 0, 0, 0, 0}, + + /* IPA4.5 */ + [IPA_HW_v4_5][IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n] = { + ipareg_construct_rsrg_grp_xy_v4_5, ipareg_parse_dummy, + 0x00000400, 0x20, 0, 0, 0, 0}, + [IPA_HW_v4_5][IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n] = { + ipareg_construct_rsrg_grp_xy_v4_5, ipareg_parse_dummy, + 0x00000404, 0x20, 0, 0, 0, 0}, + [IPA_HW_v4_5][IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n] = { + ipareg_construct_rsrg_grp_xy_v4_5, ipareg_parse_dummy, + 0x00000408, 0x20, 0, 0, 0, 0}, + [IPA_HW_v4_5][IPA_DST_RSRC_GRP_01_RSRC_TYPE_n] = { + ipareg_construct_rsrg_grp_xy_v4_5, ipareg_parse_dummy, + 0x00000500, 0x20, 0, 0, 0, 0}, + [IPA_HW_v4_5][IPA_DST_RSRC_GRP_23_RSRC_TYPE_n] = { + ipareg_construct_rsrg_grp_xy_v4_5, ipareg_parse_dummy, + 0x00000504, 0x20, 0, 0, 0, 0}, + [IPA_HW_v4_5][IPA_DST_RSRC_GRP_45_RSRC_TYPE_n] = { + ipareg_construct_rsrg_grp_xy_v4_5, ipareg_parse_dummy, + 0x00000508, 0x20, 0, 0, 0, 0}, + [IPA_HW_v4_5][IPA_RX_HPS_CLIENTS_MIN_DEPTH_0] = { + ipareg_construct_rx_hps_clients_depth0_v4_5, + ipareg_parse_dummy, + 0x000023c4, 0, 0, 0, 0, 0}, + [IPA_HW_v4_5][IPA_RX_HPS_CLIENTS_MAX_DEPTH_0] = { + ipareg_construct_rx_hps_clients_depth0_v4_5, + ipareg_parse_dummy, + 0x000023cc, 0, 0, 0, 0, 0}, + [IPA_HW_v4_5][IPA_BCR] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0, 0, 0, 0, 0}, + [IPA_HW_v4_5][IPA_COMP_CFG] = { + ipareg_construct_comp_cfg_v4_5, ipareg_parse_comp_cfg_v4_5, + 0x0000003C, 0, 0, 0, 0, 0}, + [IPA_HW_v4_5][IPA_STATE_TX_WRAPPER] = { + ipareg_construct_dummy, ipareg_parse_state_tx_wrapper_v4_5, + 0x00000090, 0, 0, 0, 1, 0}, + [IPA_HW_v4_5][IPA_STATE_FETCHER_MASK] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0, 0, 0, 0, 0}, + [IPA_HW_v4_5][IPA_STATE_FETCHER_MASK_0] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000009C, 0, 0, 0, 1, 0}, + [IPA_HW_v4_5][IPA_STATE_FETCHER_MASK_1] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000000CC, 0, 0, 0, 1, 0}, + [IPA_HW_v4_5][IPA_COUNTER_CFG] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0, 0, 0, 0, 0}, + [IPA_HW_v4_5][IPA_STATE_GSI_IF_CONS] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000000C8, 0, 0, 0, 1, 0}, + [IPA_HW_v4_5][IPA_STATE_DPL_FIFO] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000000D0, 0, 0, 0, 1, 0}, + [IPA_HW_v4_5][IPA_STATE_COAL_MASTER] = { + ipareg_construct_dummy, ipareg_parse_state_coal_master, + 0x000000D4, 0, 0, 0, 1, 0}, + [IPA_HW_v4_5][IPA_GENERIC_RAM_ARBITER_PRIORITY] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000000D8, 0, 0, 0, 1, 0}, + [IPA_HW_v4_5][IPA_STATE_NLO_AGGR] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000000DC, 0, 0, 0, 1, 0}, + [IPA_HW_v4_5][IPA_STATE_COAL_MASTER_1] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000000E0, 0, 0, 0, 1, 0}, + [IPA_HW_v4_5][IPA_ENDP_YELLOW_RED_MARKER_CFG_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000860, 0x70, 13, 30, 1, 0}, + [IPA_HW_v4_5][IPA_ENDP_INIT_MODE_n] = { + ipareg_construct_endp_init_mode_n_v4_5, ipareg_parse_dummy, + 0x00000820, 0x70, 0, 12, 1, 0}, + [IPA_HW_v4_5][IPA_TX_CFG] = { + ipareg_construct_tx_cfg_v4_5, ipareg_parse_tx_cfg_v4_5, + 0x000001FC, 0, 0, 0, 0, 0}, + [IPA_HW_v4_5][IPA_CLKON_CFG] = { + ipareg_construct_clkon_cfg_v4_5, ipareg_parse_clkon_cfg_v4_5, + 0x00000044, 0, 0, 0, 0, 0}, + [IPA_HW_v4_5][IPA_QTIME_TIMESTAMP_CFG] = { + ipareg_construct_qtime_timestamp_cfg, ipareg_parse_dummy, + 0x00000024c, 0, 0, 0, 1, 0}, + [IPA_HW_v4_5][IPA_TIMERS_PULSE_GRAN_CFG] = { + ipareg_construct_timers_pulse_gran_cfg, + ipareg_parse_timers_pulse_gran_cfg, + 0x000000254, 0, 0, 0, 1, 0}, + [IPA_HW_v4_5][IPA_TIMERS_XO_CLK_DIV_CFG] = { + ipareg_construct_timers_xo_clk_div_cfg, + ipareg_parse_timers_xo_clk_div_cfg, + 0x000000250, 0, 0, 0, 1, 0}, + [IPA_HW_v4_5][IPA_STAT_QUOTA_BASE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000700, 0x4, 0, 0, 0, 0}, + [IPA_HW_v4_5][IPA_STAT_QUOTA_MASK_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000708, 0x4, 0, 0, 0, 0}, + [IPA_HW_v4_5][IPA_STAT_TETHERING_BASE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000710, 0x4, 0, 0, 0, 0}, + [IPA_HW_v4_5][IPA_STAT_TETHERING_MASK_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000718, 0x4, 0, 0, 0, 0}, + [IPA_HW_v4_5][IPA_STAT_FILTER_IPV4_BASE] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000720, 0, 0, 0, 0, 0}, + [IPA_HW_v4_5][IPA_STAT_FILTER_IPV6_BASE] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000724, 0, 0, 0, 0, 0}, + [IPA_HW_v4_5][IPA_STAT_ROUTER_IPV4_BASE] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000728, 0, 0, 0, 0, 0}, + [IPA_HW_v4_5][IPA_STAT_ROUTER_IPV6_BASE] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000072C, 0, 0, 0, 0, 0}, + [IPA_HW_v4_5][IPA_STAT_DROP_CNT_BASE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000750, 0x4, 0, 0, 1, 0}, + [IPA_HW_v4_5][IPA_STAT_DROP_CNT_MASK_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000758, 0x4, 0, 0, 1, 0}, + [IPA_HW_v4_5][IPA_ENDP_INIT_SEQ_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000083C, 0x70, 0, 12, 1, 0}, + [IPA_HW_v4_5][IPA_ENDP_INIT_CFG_n] = { + ipareg_construct_endp_init_cfg_n, ipareg_parse_dummy, + 0x00000808, 0x70, 0, 30, 1, 0}, + [IPA_HW_v4_5][IPA_ENDP_INIT_DEAGGR_n] = { + ipareg_construct_endp_init_deaggr_n_v4_5, + ipareg_parse_dummy, + 0x00000834, 0x70, 0, 12, 1, 0}, + [IPA_HW_v4_5][IPA_ENDP_INIT_CTRL_n] = { + ipareg_construct_endp_init_ctrl_n_v4_0, ipareg_parse_dummy, + 0x00000800, 0x70, 0, 30, 1, 0}, + [IPA_HW_v4_5][IPA_ENDP_INIT_CTRL_SCND_n] = { + ipareg_construct_endp_init_ctrl_scnd_n, ipareg_parse_dummy, + 0x00000804, 0x70, 0, 30, 1, 0}, + [IPA_HW_v4_5][IPA_ENDP_INIT_CTRL_STATUS_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000864, 0x70, 0, 30, 1, 0}, + [IPA_HW_v4_5][IPA_ENDP_INIT_PROD_CFG_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000CC8, 0x70, 13, 30, 1, 0}, + [IPA_HW_v4_5][IPA_ENDP_FILTER_ROUTER_HSH_CFG_n] = { + ipareg_construct_hash_cfg_n, ipareg_parse_hash_cfg_n, + 0x0000085C, 0x70, 0, 31, 1, 0}, + [IPA_HW_v4_5][IPA_ENDP_STATUS_n] = { + ipareg_construct_endp_status_n_v4_5, ipareg_parse_dummy, + 0x00000840, 0x70, 0, 30, 1, 0}, + [IPA_HW_v4_5][IPA_ENDP_INIT_NAT_n] = { + ipareg_construct_endp_init_nat_n, ipareg_parse_dummy, + 0x0000080C, 0x70, 0, 12, 1, 0}, + [IPA_HW_v4_5][IPA_ENDP_INIT_CONN_TRACK_n] = { + ipareg_construct_endp_init_conn_track_n, + ipareg_parse_dummy, + 0x00000850, 0x70, 0, 12, 1, 0}, + [IPA_HW_v4_5][IPA_ENDP_INIT_RSRC_GRP_n] = { + ipareg_construct_endp_init_rsrc_grp_n_v4_5, + ipareg_parse_dummy, + 0x00000838, 0x70, 0, 30, 1, 0}, + [IPA_HW_v4_5][IPA_STAT_FILTER_IPV4_START_ID] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0, 0, 0, 0, 0}, + [IPA_HW_v4_5][IPA_STAT_FILTER_IPV6_START_ID] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0, 0, 0, 0, 0}, + [IPA_HW_v4_5][IPA_STAT_ROUTER_IPV4_START_ID] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0, 0, 0, 0, 0}, + [IPA_HW_v4_5][IPA_STAT_ROUTER_IPV6_START_ID] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0, 0, 0, 0, 0}, + [IPA_HW_v4_5][IPA_STAT_FILTER_IPV4_END_ID] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0, 0, 0, 0, 0}, + [IPA_HW_v4_5][IPA_STAT_FILTER_IPV6_END_ID] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0, 0, 0, 0, 0}, + [IPA_HW_v4_5][IPA_STAT_ROUTER_IPV4_END_ID] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0, 0, 0, 0, 0}, + [IPA_HW_v4_5][IPA_STAT_ROUTER_IPV6_END_ID] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0, 0, 0, 0, 0}, + [IPA_HW_v4_5][IPA_DPS_SEQUENCER_FIRST] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00002570, 0, 0, 0, 0, 0}, + [IPA_HW_v4_5][IPA_DPS_SEQUENCER_LAST] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00002574, 0, 0, 0, 0, 0}, + [IPA_HW_v4_5][IPA_HPS_SEQUENCER_FIRST] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00002578, 0, 0, 0, 0, 0}, + [IPA_HW_v4_5][IPA_HPS_SEQUENCER_LAST] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000257c, 0, 0, 0, 0, 0}, + [IPA_HW_v4_5][IPA_NAT_TIMER] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000058, 0, 0, 0, 1, 0}, + [IPA_HW_v4_5][IPA_ENDP_INIT_HOL_BLOCK_EN_n] = { + ipareg_construct_endp_init_hol_block_en_n, + ipareg_parse_dummy, + 0x0000082c, 0x70, 13, 30, 1, 0}, + [IPA_HW_v4_5][IPA_ENDP_INIT_HOL_BLOCK_TIMER_n] = { + ipareg_construct_endp_init_hol_block_timer_n_v4_5, + ipareg_parse_dummy, + 0x00000830, 0x70, 13, 30, 1, 0}, + [IPA_HW_v4_5][IPA_ENDP_INIT_AGGR_n] = { + ipareg_construct_endp_init_aggr_n_v4_5, + ipareg_parse_endp_init_aggr_n_v4_5, + 0x00000824, 0x70, 0, 30, 1, 0}, + [IPA_HW_v4_5][IPA_SW_AREA_RAM_DIRECT_ACCESS_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000010000, 0x4, 0, 0, 0, 0}, + [IPA_HW_v4_5][IPA_ENDP_INIT_HDR_n] = { + ipareg_construct_endp_init_hdr_n_v4_5, ipareg_parse_dummy, + 0x00000810, 0x70, 0, 30, 1, 0}, + [IPA_HW_v4_5][IPA_ENDP_INIT_HDR_EXT_n] = { + ipareg_construct_endp_init_hdr_ext_n_v4_5, ipareg_parse_dummy, + 0x00000814, 0x70, 0, 30, 1, 0}, + [IPA_HW_v4_5][IPA_ENDP_INIT_HDR_METADATA_n] = { + ipareg_construct_endp_init_hdr_metadata_n, + ipareg_parse_dummy, + 0x0000081c, 0x70, 0, 12, 1, 0}, + [IPA_HW_v4_5][IPA_ENDP_INIT_HDR_METADATA_MASK_n] = { + ipareg_construct_endp_init_hdr_metadata_mask_n, + ipareg_parse_dummy, + 0x00000818, 0x70, 13, 30, 1, 0}, + [IPA_HW_v4_5][IPA_UC_MAILBOX_m_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00082000, 0x4, 0, 0, 0, 0x80}, + [IPA_HW_v4_5][IPA_COAL_EVICT_LRU] = { + ipareg_construct_coal_evict_lru, ipareg_parse_coal_evict_lru, + 0x0000180C, 0, 0, 0, 0, 0}, + [IPA_HW_v4_5][IPA_COAL_QMAP_CFG] = { + ipareg_construct_coal_qmap_cfg, ipareg_parse_coal_qmap_cfg, + 0x00001810, 0, 0, 0, 0, 0}, + [IPA_HW_v4_5][IPA_NAT_UC_EXTERNAL_CFG] = { + ipareg_construct_nat_uc_external_cfg, + ipareg_parse_nat_uc_external_cfg, + 0x00000200, 0, 0, 0, 0, 0}, + [IPA_HW_v4_5][IPA_NAT_UC_LOCAL_CFG] = { + ipareg_construct_nat_uc_local_cfg, + ipareg_parse_nat_uc_local_cfg, + 0x00000204, 0, 0, 0, 0, 0}, + [IPA_HW_v4_5][IPA_NAT_UC_SHARED_CFG] = { + ipareg_construct_nat_uc_shared_cfg, + ipareg_parse_nat_uc_shared_cfg, + 0x00000208, 0, 0, 0, 0, 0}, + [IPA_HW_v4_5][IPA_CONN_TRACK_UC_EXTERNAL_CFG] = { + ipareg_construct_conn_track_uc_external_cfg, + ipareg_parse_conn_track_uc_external_cfg, + 0x00000230, 0, 0, 0, 0, 0}, + [IPA_HW_v4_5][IPA_CONN_TRACK_UC_LOCAL_CFG] = { + ipareg_construct_conn_track_uc_local_cfg, + ipareg_parse_conn_track_uc_local_cfg, + 0x00000234, 0, 0, 0, 0, 0}, + [IPA_HW_v4_5][IPA_CONN_TRACK_UC_SHARED_CFG] = { + ipareg_construct_conn_track_uc_shared_cfg, + ipareg_parse_conn_track_uc_shared_cfg, + 0x00000238, 0, 0, 0, 0, 0}, + [IPA_HW_v4_7][IPA_STATE_TX_WRAPPER] = { + ipareg_construct_dummy, ipareg_parse_state_tx_wrapper_v4_7, + 0x00000090, 0, 0, 0, 1, 0}, + + /* IPA4.9 */ + + /* IPA_DEBUG */ + [IPA_HW_v4_9][IPA_ENDP_GSI_CFG1_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000026C0, 0x4, 0, 30, 0, 0}, + [IPA_HW_v4_9][IPA_ENDP_GSI_CFG_TLV_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00002758, 0x4, 0, 30, 0, 0}, + [IPA_HW_v4_9][IPA_ENDP_GSI_CFG_AOS_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000027D4, 0x4, 0, 30, 0, 0}, + + + /* IPA_CFG */ + [IPA_HW_v4_9][IPA_COMP_CFG] = { + ipareg_construct_comp_cfg_v4_9, ipareg_parse_comp_cfg_v4_9, + 0x0000003C, 0, 0, 0, 0, 0}, + [IPA_HW_v4_9][IPA_QSB_MAX_READS] = { + ipareg_construct_qsb_max_reads_v4_0, ipareg_parse_qsb_max_reads, + 0x00000078, 0, 0, 0, 0, 0}, + [IPA_HW_v4_9][IPA_QSB_MAX_WRITES] = { + ipareg_construct_qsb_max_writes, ipareg_parse_qsb_max_writes, + 0x00000074, 0, 0, 0, 0, 0}, + [IPA_HW_v4_9][IPA_TX_CFG] = { + ipareg_construct_tx_cfg_v4_9, ipareg_parse_tx_cfg_v4_9, + 0x000001FC, 0, 0, 0, 0, 0}, + [IPA_HW_v4_9][IPA_ENDP_INIT_NAT_n] = { + ipareg_construct_endp_init_nat_n, ipareg_parse_dummy, + 0x0000080C, 0x70, 0, 10, 0, 0}, + [IPA_HW_v4_9][IPA_ENDP_INIT_HDR_n] = { + ipareg_construct_endp_init_hdr_n_v4_9, ipareg_parse_dummy, + 0x00000810, 0x70, 0, 30, 0, 0}, + [IPA_HW_v4_9][IPA_ENDP_INIT_HDR_METADATA_n] = { + ipareg_construct_endp_init_hdr_metadata_n, + ipareg_parse_dummy, + 0x0000081c, 0x70, 0, 10, 0, 0}, + [IPA_HW_v4_9][IPA_ENDP_INIT_MODE_n] = { + ipareg_construct_endp_init_mode_n_v4_5, ipareg_parse_dummy, + 0x00000820, 0x70, 0, 10, 0, 0}, + [IPA_HW_v4_9][IPA_ENDP_INIT_DEAGGR_n] = { + ipareg_construct_endp_init_deaggr_n_v4_5, + ipareg_parse_dummy, + 0x00000834, 0x70, 0, 10, 0, 0}, + [IPA_HW_v4_9][IPA_ENDP_INIT_RSRC_GRP_n] = { + ipareg_construct_endp_init_rsrc_grp_n_v4_9, + ipareg_parse_dummy, + 0x00000838, 0x70, 0, 30, 0, 0}, + [IPA_HW_v4_9][IPA_ENDP_INIT_SEQ_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000083C, 0x70, 0, 10, 0, 0}, + [IPA_HW_v4_9][IPA_ENDP_INIT_CONN_TRACK_n] = { + ipareg_construct_endp_init_conn_track_n, + ipareg_parse_dummy, + 0x00000850, 0x70, 0, 10, 0, 0}, + [IPA_HW_v4_9][IPA_GENERIC_RAM_ARBITER_PRIORITY] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000000DC, 0, 0, 0, 1, 0}, + + /* IPA_EE */ + [IPA_HW_v4_9][IPA_IRQ_STTS_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00004008, 0x1000, 0, 0, 0, 0}, + [IPA_HW_v4_9][IPA_IRQ_EN_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000400c, 0x1000, 0, 0, 0, 0}, + [IPA_HW_v4_9][IPA_IRQ_CLR_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00004010, 0x1000, 0, 0, 0, 0}, + [IPA_HW_v4_9][IPA_SNOC_FEC_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00004018, 0x1000, 0, 0, 0, 0}, + [IPA_HW_v4_9][IPA_SUSPEND_IRQ_INFO_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00004030, 0x1000, 0, 0, 0, 0}, + [IPA_HW_v4_9][IPA_SUSPEND_IRQ_EN_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00004034, 0x1000, 0, 0, 0, 0}, + [IPA_HW_v4_9][IPA_SUSPEND_IRQ_CLR_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00004038, 0x1000, 0, 0, 0, 0}, + [IPA_HW_v4_9][IPA_HOLB_DROP_IRQ_INFO_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000403C, 0x1000, 0, 0, 0, 0}, + [IPA_HW_v4_9][IPA_HOLB_DROP_IRQ_EN_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00004040, 0x1000, 0, 0, 0, 0}, + [IPA_HW_v4_9][IPA_HOLB_DROP_IRQ_CLR_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00004044, 0x1000, 0, 0, 0, 0}, + [IPA_HW_v4_9][IPA_IRQ_EE_UC_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000401c, 0x1000, 0, 0, 1, 0}, + [IPA_HW_v4_9][IPA_FEC_ADDR_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00004020, 0x1000, 0, 0, 1, 0}, + [IPA_HW_v4_9][IPA_FEC_ADDR_MSB_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00004024, 0x1000, 0, 0, 1, 0}, + [IPA_HW_v4_9][IPA_FEC_ATTR_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00004028, 0x1000, 0, 0, 1, 0}, + + /* IPA5.0 */ + + /* IPA_CFG */ + [IPA_HW_v5_0][IPA_COMP_HW_VERSION] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000024, 0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_VERSION] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000028, 0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_FLAVOR_0] = { + ipareg_construct_dummy, ipareg_parse_ipa_flavor_0, + 0x00000000, 0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_ENABLED_PIPES] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_COMP_CFG] = { + ipareg_construct_comp_cfg_v5_0, ipareg_parse_comp_cfg_v5_0, + 0x0000002C, 0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_CLKON_CFG] = { + ipareg_construct_clkon_cfg_v4_5, ipareg_parse_clkon_cfg_v4_5, + 0x00000034, 0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_ROUTE] = { + ipareg_construct_route_v5_0, ipareg_parse_dummy, + 0x00000038, 0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_SHARED_MEM_SIZE] = { + ipareg_construct_dummy, ipareg_parse_shared_mem_size, + 0x00000040, 0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_NAT_TIMER] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000048, 0, 0, 0, 1, 0}, + [IPA_HW_v5_0][IPA_TAG_TIMER] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000044, 0, 0, 0, 1, 0}, + [IPA_HW_v5_0][IPA_QSB_MAX_WRITES] = { + ipareg_construct_qsb_max_writes, ipareg_parse_qsb_max_writes, + 0x00000054, 0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_QSB_MAX_READS] = { + ipareg_construct_qsb_max_reads_v4_0, ipareg_parse_qsb_max_reads, + 0x00000058, 0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_STATE_TX1] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000098, 0, 0, 0, 1, 0}, + [IPA_HW_v5_0][IPA_STATE_FETCHER] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000000A4, 0, 0, 0, 1, 0}, + [IPA_HW_v5_0][IPA_STATE_FETCHER_MASK_0] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000000A8, 0, 0, 0, 1, 0}, + [IPA_HW_v5_0][IPA_STATE_DFETCHER] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000000AC, 0, 0, 0, 1, 0}, + [IPA_HW_v5_0][IPA_STATE_ACL] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000000B0, 0, 0, 0, 1, 0}, + [IPA_HW_v5_0][IPA_STATE] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000000B4, 0, 0, 0, 1, 0}, + [IPA_HW_v5_0][IPA_STATE_RX_ACTIVE] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0, 0, 0, 1, 0}, + [IPA_HW_v5_0][IPA_STATE_TX0] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000094, 0, 0, 0, 1, 0}, + [IPA_HW_v5_0][IPA_STATE_AGGR_ACTIVE] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0, 0, 0, 1, 0}, + [IPA_HW_v5_0][IPA_STATE_AGGR_ACTIVE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000100, 0x4, 0, 0, 1, 0}, + [IPA_HW_v5_0][IPA_STATE_GSI_TLV] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0, 0, 0, 1, 0}, + [IPA_HW_v5_0][IPA_STATE_GSI_AOS] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000000B8, 0, 0, 0, 1, 0}, + [IPA_HW_v5_0][IPA_GENERIC_RAM_ARBITER_PRIORITY] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000004DC, 0, 0, 0, 1, 0}, + [IPA_HW_v5_0][IPA_STATE_COAL_MASTER_1] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000000DC, 0, 0, 0, 1, 0}, + [IPA_HW_v5_0][IPA_FILT_ROUT_HASH_EN] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_FILT_ROUT_HASH_FLUSH] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_FILT_ROUT_CACHE_FLUSH] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000404, 0, 0, 0, 0, 0 }, + [IPA_HW_v5_0][IPA_SYS_PKT_PROC_CNTXT_BASE] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000470, 0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_LOCAL_PKT_PROC_CNTXT_BASE] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000478, 0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_AGGR_FORCE_CLOSE] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_AGGR_FORCE_CLOSE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000006B0, 0x4, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_TX_CFG] = { + ipareg_construct_tx_cfg_v5_0, ipareg_parse_tx_cfg_v5_0, + 0x00000488, 0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_IDLE_INDICATION_CFG] = { + ipareg_construct_idle_indication_cfg, ipareg_parse_dummy, + 0x000004A8, 0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_QTIME_TIMESTAMP_CFG] = { + ipareg_construct_qtime_timestamp_cfg, ipareg_parse_dummy, + 0x0000004Ac, 0, 0, 0, 1, 0}, + [IPA_HW_v5_0][IPA_TIMERS_XO_CLK_DIV_CFG] = { + ipareg_construct_timers_xo_clk_div_cfg, + ipareg_parse_timers_xo_clk_div_cfg, + 0x0000004B0, 0, 0, 0, 1, 0}, + [IPA_HW_v5_0][IPA_TIMERS_PULSE_GRAN_CFG] = { + ipareg_construct_timers_pulse_gran_cfg_v5_0, + ipareg_parse_timers_pulse_gran_cfg_v5_0, + 0x0000004B4, 0, 0, 0, 1, 0}, + [IPA_HW_v5_0][IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n] = { + ipareg_construct_rsrg_grp_xy_v5_0, ipareg_parse_dummy, + 0x00000500, 0x20, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n] = { + ipareg_construct_rsrg_grp_xy_v5_0, ipareg_parse_dummy, + 0x00000504, 0x20, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_DST_RSRC_GRP_01_RSRC_TYPE_n] = { + ipareg_construct_rsrg_grp_xy_v5_0, ipareg_parse_dummy, + 0x00000600, 0x20, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_DST_RSRC_GRP_23_RSRC_TYPE_n] = { + ipareg_construct_rsrg_grp_xy_v5_0, ipareg_parse_dummy, + 0x00000604, 0x20, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n] = { + ipareg_construct_rsrg_grp_xy_v5_0, ipareg_parse_dummy, + 0x00000508, 0x20, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n] = { + ipareg_construct_rsrg_grp_xy_v5_0, ipareg_parse_dummy, + 0x0000050C, 0x20, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_DST_RSRC_GRP_45_RSRC_TYPE_n] = { + ipareg_construct_rsrg_grp_xy_v5_0, ipareg_parse_dummy, + 0x00000608, 0x20, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_DST_RSRC_GRP_67_RSRC_TYPE_n] = { + ipareg_construct_rsrg_grp_xy_v5_0, ipareg_parse_dummy, + 0x0000060C, 0x20, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_RSRC_GRP_CFG] = { + ipareg_construct_rsrg_grp_cfg, ipareg_parse_dummy, + 0x000006A0, 0x0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_RSRC_GRP_CFG_EXT] = { + ipareg_construct_rsrg_grp_cfg_ext, ipareg_parse_dummy, + 0x000006A4, 0x0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_STAT_QUOTA_BASE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000006D0, 0x4, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_STAT_QUOTA_MASK_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0x4, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_STAT_QUOTA_MASK_EE_n_REG_k] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000710, 0x4, 0, 0, 0, 0x8}, + [IPA_HW_v5_0][IPA_STAT_TETHERING_BASE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000006E0, 0x4, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_STAT_TETHERING_MASK_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0x4, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_STAT_TETHERING_MASK_EE_n_REG_k] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000750, 0x4, 0, 0, 0, 0x8}, + [IPA_HW_v5_0][IPA_STAT_FILTER_IPV4_BASE] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000700, 0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_STAT_FILTER_IPV6_BASE] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000704, 0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_STAT_ROUTER_IPV4_BASE] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000708, 0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_STAT_ROUTER_IPV6_BASE] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000070C, 0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_STAT_DROP_CNT_BASE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000006F0, 0x4, 0, 0, 1, 0}, + [IPA_HW_v5_0][IPA_STAT_DROP_CNT_MASK_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0x4, 0, 0, 1, 0}, + [IPA_HW_v5_0][IPA_STAT_DROP_CNT_MASK_EE_n_REG_k] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000790 , 0x4, 0, 0, 1, 0x8}, + [IPA_HW_v5_0][IPA_ENDP_INIT_CTRL_n] = { + ipareg_construct_endp_init_ctrl_n_v4_0, ipareg_parse_dummy, + 0x00001000, 0x80, 0, 30, 1, 0}, + [IPA_HW_v5_0][IPA_ENDP_INIT_CTRL_SCND_n] = { + ipareg_construct_endp_init_ctrl_scnd_n, ipareg_parse_dummy, + 0x00001004, 0x80, 0, 30, 1, 0}, + [IPA_HW_v5_0][IPA_ENDP_INIT_CFG_n] = { + ipareg_construct_endp_init_cfg_n, ipareg_parse_dummy, + 0x00001008, 0x80, 0, 30, 1, 0}, + [IPA_HW_v5_0][IPA_ENDP_INIT_NAT_n] = { + ipareg_construct_endp_init_nat_n, ipareg_parse_dummy, + 0x0000100C, 0x80, 0, 10, 0, 0}, + [IPA_HW_v5_0][IPA_ENDP_INIT_HDR_n] = { + ipareg_construct_endp_init_hdr_n_v4_9, ipareg_parse_dummy, + 0x00001010, 0x80, 0, 30, 0, 0}, + [IPA_HW_v5_0][IPA_ENDP_INIT_HDR_EXT_n] = { + ipareg_construct_endp_init_hdr_ext_n_v5_0, ipareg_parse_dummy, + 0x00001014, 0x80, 0, 30, 1, 0}, + [IPA_HW_v5_0][IPA_ENDP_INIT_HDR_METADATA_n] = { + ipareg_construct_endp_init_hdr_metadata_n, + ipareg_parse_dummy, + 0x0000101c, 0x80, 0, 10, 0, 0}, + [IPA_HW_v5_0][IPA_ENDP_INIT_MODE_n] = { + ipareg_construct_endp_init_mode_n_v5_0, ipareg_parse_dummy, + 0x00001020, 0x80, 0, 10, 0, 0}, + [IPA_HW_v5_0][IPA_ENDP_INIT_AGGR_n] = { + ipareg_construct_endp_init_aggr_n_v4_5, + ipareg_parse_endp_init_aggr_n_v4_5, + 0x00001024, 0x80, 0, 30, 1, 0}, + [IPA_HW_v5_0][IPA_ENDP_INIT_DEAGGR_n] = { + ipareg_construct_endp_init_deaggr_n_v4_5, + ipareg_parse_dummy, + 0x00001034, 0x80, 0, 10, 0, 0}, + [IPA_HW_v5_0][IPA_ENDP_INIT_RSRC_GRP_n] = { + ipareg_construct_endp_init_rsrc_grp_n_v5_0, + ipareg_parse_dummy, + 0x00001038, 0x80, 0, 30, 0, 0}, + [IPA_HW_v5_0][IPA_ENDP_INIT_SEQ_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000103C, 0x80, 0, 10, 0, 0}, + [IPA_HW_v5_0][IPA_ENDP_STATUS_n] = { + ipareg_construct_endp_status_n_v5_0, ipareg_parse_dummy, + 0x00001040, 0x80, 0, 30, 1, 0}, + [IPA_HW_v5_0][IPA_ENDP_INIT_CONN_TRACK_n] = { + ipareg_construct_endp_init_conn_track_n, + ipareg_parse_dummy, + 0x00001050, 0x80, 0, 10, 0, 0}, + [IPA_HW_v5_0][IPA_ENDP_FILTER_ROUTER_HSH_CFG_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0x70, 0, 31, 1, 0}, + [IPA_HW_v5_0][IPA_FILTER_CACHE_CFG_n] = { + ipareg_construct_cache_cfg_n, ipareg_parse_cache_cfg_n, + 0x0000105C , 0x80, 0, 31, 1, 0}, + [IPA_HW_v5_0][IPA_ROUTER_CACHE_CFG_n] = { + ipareg_construct_cache_cfg_n, ipareg_parse_cache_cfg_n, + 0x00001070 , 0x80, 0, 31, 1, 0}, + [IPA_HW_v5_0][IPA_ENDP_INIT_CTRL_STATUS_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00001064, 0x80, 0, 30, 1, 0}, + [IPA_HW_v5_0][IPA_ENDP_INIT_HDR_METADATA_MASK_n] = { + ipareg_construct_endp_init_hdr_metadata_mask_n, + ipareg_parse_dummy, + 0x00001018, 0x80, 13, 30, 1, 0}, + [IPA_HW_v5_0][IPA_ENDP_INIT_HOL_BLOCK_EN_n] = { + ipareg_construct_endp_init_hol_block_en_n, + ipareg_parse_dummy, + 0x0000102c, 0x80, 13, 30, 1, 0}, + [IPA_HW_v5_0][IPA_ENDP_INIT_HOL_BLOCK_TIMER_n] = { + ipareg_construct_endp_init_hol_block_timer_n_v5_0, + ipareg_parse_dummy, + 0x00001030, 0x80, 13, 30, 1, 0}, + [IPA_HW_v5_0][IPA_ENDP_INIT_PROD_CFG_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00001068, 0x80, 13, 30, 1, 0}, + [IPA_HW_v5_0][IPA_COAL_EVICT_LRU] = { + ipareg_construct_coal_evict_lru, ipareg_parse_coal_evict_lru, + 0x00000918, 0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_COAL_QMAP_CFG] = { + ipareg_construct_coal_qmap_cfg, ipareg_parse_coal_qmap_cfg, + 0x0000091c, 0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_ULSO_CFG_IP_ID_MIN_VALUE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000934, 0x4, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_ULSO_CFG_IP_ID_MAX_VALUE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000924, 0x4, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_ENDP_INIT_ULSO_CFG_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000106c, 0x80, 0, 0, 0, 0}, + + /* IPA_DEBUG */ + [IPA_HW_v5_0][IPA_RX_HPS_CLIENTS_MIN_DEPTH_1] = { //TODO contstruct not matching previous version + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000082C8, 0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_RX_HPS_CLIENTS_MAX_DEPTH_1] = { //TODO contstruct not matching previous version + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000082D0, 0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_RX_HPS_CLIENTS_MIN_DEPTH_0] = { + ipareg_construct_rx_hps_clients_depth0_v4_5, + ipareg_parse_dummy, + 0x000082c4, 0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_RX_HPS_CLIENTS_MAX_DEPTH_0] = { + ipareg_construct_rx_hps_clients_depth0_v4_5, + ipareg_parse_dummy, + 0x000082CC, 0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_DPS_SEQUENCER_FIRST] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00008584, 0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_DPS_SEQUENCER_LAST] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00008588, 0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_HPS_SEQUENCER_FIRST] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000858C, 0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_HPS_SEQUENCER_LAST] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00008590, 0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_ENDP_GSI_CFG1_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00008800, 0x4, 0, 30, 0, 0}, + [IPA_HW_v5_0][IPA_ENDP_GSI_CFG_TLV_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00009000, 0x4, 0, 30, 0, 0}, + [IPA_HW_v5_0][IPA_ENDP_GSI_CFG_AOS_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00009400, 0x4, 0, 30, 0, 0}, + + /* IPA_EE */ + [IPA_HW_v5_0][IPA_IRQ_STTS_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000C008, 0x1000, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_IRQ_EN_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000C00c, 0x1000, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_IRQ_CLR_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000C010, 0x1000, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_SNOC_FEC_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000C018, 0x1000, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_SUSPEND_IRQ_INFO_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0x1000, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_SUSPEND_IRQ_INFO_EE_n_REG_k] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000C030, 0x1000, 0, 0, 0, 0x4}, + [IPA_HW_v5_0][IPA_SUSPEND_IRQ_EN_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0x1000, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_SUSPEND_IRQ_EN_EE_n_REG_k] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000C050, 0x1000, 0, 0, 0, 0x4}, + [IPA_HW_v5_0][IPA_SUSPEND_IRQ_CLR_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0x1000, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_SUSPEND_IRQ_CLR_EE_n_REG_k] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000C070, 0x1000, 0, 0, 0, 0x4}, + [IPA_HW_v5_0][IPA_HOLB_DROP_IRQ_INFO_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0x1000, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_HOLB_DROP_IRQ_EN_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0x1000, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_HOLB_DROP_IRQ_CLR_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0x1000, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_IRQ_EE_UC_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000C01c, 0x1000, 0, 0, 1, 0}, + [IPA_HW_v5_0][IPA_FEC_ADDR_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000C020, 0x1000, 0, 0, 1, 0}, + [IPA_HW_v5_0][IPA_FEC_ADDR_MSB_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000C024, 0x1000, 0, 0, 1, 0}, + [IPA_HW_v5_0][IPA_FEC_ATTR_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000C028, 0x1000, 0, 0, 1, 0}, + + /* IPA_CFG */ + [IPA_HW_v5_5][IPA_COMP_HW_VERSION] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000040, 0, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_VERSION] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000044, 0, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_FLAVOR_0] = { + ipareg_construct_dummy, ipareg_parse_ipa_flavor_0, + 0x00000000, 0, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_FLAVOR_9] = { + ipareg_construct_dummy, ipareg_parse_ipa_flavor_9, + 0x00000024, 0, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_ENABLED_PIPES] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_COMP_CFG] = { + ipareg_construct_comp_cfg_v5_0, ipareg_parse_comp_cfg_v5_0, + 0x00000048, 0, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_CLKON_CFG] = { + ipareg_construct_clkon_cfg_v4_5, ipareg_parse_clkon_cfg_v4_5, + 0x00000050, 0, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_ROUTE] = { + ipareg_construct_route_v5_0, ipareg_parse_dummy, + 0x00000054, 0, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_SHARED_MEM_SIZE] = { + ipareg_construct_dummy, ipareg_parse_shared_mem_size, + 0x0000005C, 0, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_NAT_TIMER] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000060, 0, 0, 0, 1, 0}, + [IPA_HW_v5_5][IPA_TAG_TIMER] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000064, 0, 0, 0, 1, 0}, + [IPA_HW_v5_5][IPA_QSB_MAX_WRITES] = { + ipareg_construct_qsb_max_writes, ipareg_parse_qsb_max_writes, + 0x00000070, 0, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_QSB_MAX_READS] = { + ipareg_construct_qsb_max_reads_v4_0, ipareg_parse_qsb_max_reads, + 0x00000074, 0, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_STATE_TX1] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0, 0, 0, 1, 0}, + [IPA_HW_v5_5][IPA_STATE_FETCHER] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000000C4, 0, 0, 0, 1, 0}, + [IPA_HW_v5_5][IPA_STATE_FETCHER_MASK_0] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000000C8, 0, 0, 0, 1, 0}, + [IPA_HW_v5_5][IPA_STATE_DFETCHER] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000000CC, 0, 0, 0, 1, 0}, + [IPA_HW_v5_5][IPA_STATE_ACL] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000000D0, 0, 0, 0, 1, 0}, + [IPA_HW_v5_5][IPA_STATE] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000000D4, 0, 0, 0, 1, 0}, + [IPA_HW_v5_5][IPA_STATE_RX_ACTIVE] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0, 0, 0, 1, 0}, + [IPA_HW_v5_5][IPA_STATE_TX0] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0, 0, 0, 1, 0}, + [IPA_HW_v5_5][IPA_STATE_TSP] = { + ipareg_construct_dummy, ipareg_parse_state_tsp, + 0x0000011C, 0, 0, 0, 1, 0}, + [IPA_HW_v5_5][IPA_STATE_AGGR_ACTIVE] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0, 0, 0, 1, 0}, + [IPA_HW_v5_5][IPA_STATE_AGGR_ACTIVE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000120, 0x4, 0, 0, 1, 0}, + [IPA_HW_v5_5][IPA_STATE_GSI_TLV] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0, 0, 0, 1, 0}, + [IPA_HW_v5_5][IPA_STATE_GSI_AOS] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000000D8, 0, 0, 0, 1, 0}, + [IPA_HW_v5_5][IPA_GENERIC_RAM_ARBITER_PRIORITY] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000004DC, 0, 0, 0, 1, 0}, + [IPA_HW_v5_5][IPA_STATE_COAL_MASTER_1] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000000FC, 0, 0, 0, 1, 0}, + [IPA_HW_v5_5][IPA_FILT_ROUT_HASH_EN] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_FILT_ROUT_HASH_FLUSH] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_FILT_ROUT_CACHE_FLUSH] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000404, 0, 0, 0, 0, 0 }, + [IPA_HW_v5_5][IPA_SYS_PKT_PROC_CNTXT_BASE] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000470, 0, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_LOCAL_PKT_PROC_CNTXT_BASE] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000478, 0, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_TX_CFG] = { + ipareg_construct_tx_cfg_v5_0, ipareg_parse_tx_cfg_v5_0, + 0x00000488, 0, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_IDLE_INDICATION_CFG] = { + ipareg_construct_idle_indication_cfg, ipareg_parse_dummy, + 0x000004A8, 0, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_QTIME_TIMESTAMP_CFG] = { + ipareg_construct_qtime_timestamp_cfg_v5_5, ipareg_parse_dummy, + 0x0000004Ac, 0, 0, 0, 1, 0}, + [IPA_HW_v5_5][IPA_TIMERS_XO_CLK_DIV_CFG] = { + ipareg_construct_timers_xo_clk_div_cfg, + ipareg_parse_timers_xo_clk_div_cfg, + 0x0000004B0, 0, 0, 0, 1, 0}, + [IPA_HW_v5_5][IPA_TIMERS_PULSE_GRAN_CFG] = { + ipareg_construct_timers_pulse_gran_cfg_v5_0, + ipareg_parse_timers_pulse_gran_cfg_v5_0, + 0x0000004B4, 0, 0, 0, 1, 0}, + [IPA_HW_v5_5][IPA_IPV4_NAT_EXC_SUPPRESS_ROUT_TABLE_INDX] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000004E4, 0, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_IPV6_CONN_TRACK_EXC_SUPPRESS_ROUT_TABLE_INDX] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000004E8, 0, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n] = { + ipareg_construct_rsrg_grp_xy_v5_0, ipareg_parse_dummy, + 0x00000500, 0x20, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n] = { + ipareg_construct_rsrg_grp_xy_v5_0, ipareg_parse_dummy, + 0x00000504, 0x20, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_DST_RSRC_GRP_01_RSRC_TYPE_n] = { + ipareg_construct_rsrg_grp_xy_v5_0, ipareg_parse_dummy, + 0x00000600, 0x20, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_DST_RSRC_GRP_23_RSRC_TYPE_n] = { + ipareg_construct_rsrg_grp_xy_v5_0, ipareg_parse_dummy, + 0x00000604, 0x20, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n] = { + ipareg_construct_rsrg_grp_xy_v5_0, ipareg_parse_dummy, + 0x00000508, 0x20, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n] = { + ipareg_construct_rsrg_grp_xy_v5_0, ipareg_parse_dummy, + 0x0000050C, 0x20, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_DST_RSRC_GRP_45_RSRC_TYPE_n] = { + ipareg_construct_rsrg_grp_xy_v5_0, ipareg_parse_dummy, + 0x00000608, 0x20, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_DST_RSRC_GRP_67_RSRC_TYPE_n] = { + ipareg_construct_rsrg_grp_xy_v5_0, ipareg_parse_dummy, + 0x0000060C, 0x20, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_AGGR_FORCE_CLOSE] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_AGGR_FORCE_CLOSE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000006B0, 0x4, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_STAT_QUOTA_BASE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000006D0, 0x4, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_STAT_QUOTA_MASK_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0x4, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_STAT_QUOTA_MASK_EE_n_REG_k] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000710, 0x4, 0, 0, 0, 0x8}, + [IPA_HW_v5_5][IPA_STAT_TETHERING_BASE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000006E0, 0x4, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_STAT_TETHERING_MASK_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0x4, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_STAT_TETHERING_MASK_EE_n_REG_k] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000750, 0x4, 0, 0, 0, 0x8}, + [IPA_HW_v5_5][IPA_STAT_FILTER_IPV4_BASE] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000700, 0, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_STAT_FILTER_IPV6_BASE] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000704, 0, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_STAT_ROUTER_IPV4_BASE] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000708, 0, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_STAT_ROUTER_IPV6_BASE] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000070C, 0, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_STAT_DROP_CNT_BASE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000006F0, 0x4, 0, 0, 1, 0}, + [IPA_HW_v5_5][IPA_STAT_DROP_CNT_MASK_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0x4, 0, 0, 1, 0}, + [IPA_HW_v5_5][IPA_STAT_DROP_CNT_MASK_EE_n_REG_k] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000790 , 0x4, 0, 0, 1, 0x8}, + [IPA_HW_v5_5][IPA_ENDP_INIT_CTRL_n] = { + ipareg_construct_endp_init_ctrl_n_v4_0, ipareg_parse_dummy, + 0x00001000, 0x80, 0, 30, 1, 0}, + [IPA_HW_v5_5][IPA_ENDP_INIT_CTRL_SCND_n] = { + ipareg_construct_endp_init_ctrl_scnd_n, ipareg_parse_dummy, + 0x00001004, 0x80, 0, 30, 1, 0}, + [IPA_HW_v5_5][IPA_ENDP_INIT_CFG_n] = { + ipareg_construct_endp_init_cfg_n, ipareg_parse_dummy, + 0x00001008, 0x80, 0, 30, 1, 0}, + [IPA_HW_v5_5][IPA_ENDP_INIT_NAT_n] = { + ipareg_construct_endp_init_nat_n, ipareg_parse_dummy, + 0x0000100C, 0x80, 0, 10, 0, 0}, + [IPA_HW_v5_5][IPA_ENDP_INIT_HDR_n] = { + ipareg_construct_endp_init_hdr_n_v4_9, ipareg_parse_dummy, + 0x00001010, 0x80, 0, 30, 0, 0}, + [IPA_HW_v5_5][IPA_ENDP_INIT_HDR_EXT_n] = { + ipareg_construct_endp_init_hdr_ext_n_v5_0, ipareg_parse_dummy, + 0x00001014, 0x80, 0, 30, 1, 0}, + [IPA_HW_v5_5][IPA_ENDP_INIT_HDR_METADATA_n] = { + ipareg_construct_endp_init_hdr_metadata_n, + ipareg_parse_dummy, + 0x0000101c, 0x80, 0, 10, 0, 0}, + [IPA_HW_v5_5][IPA_ENDP_INIT_MODE_n] = { + ipareg_construct_endp_init_mode_n_v5_0, ipareg_parse_dummy, + 0x00001020, 0x80, 0, 10, 0, 0}, + [IPA_HW_v5_5][IPA_ENDP_INIT_AGGR_n] = { + ipareg_construct_endp_init_aggr_n_v4_5, + ipareg_parse_endp_init_aggr_n_v4_5, + 0x00001024, 0x80, 0, 30, 1, 0}, + [IPA_HW_v5_5][IPA_ENDP_INIT_DEAGGR_n] = { + ipareg_construct_endp_init_deaggr_n_v4_5, + ipareg_parse_dummy, + 0x00001034, 0x80, 0, 10, 0, 0}, + [IPA_HW_v5_5][IPA_ENDP_INIT_RSRC_GRP_n] = { + ipareg_construct_endp_init_rsrc_grp_n_v5_0, + ipareg_parse_dummy, + 0x00001038, 0x80, 0, 30, 0, 0}, + [IPA_HW_v5_5][IPA_ENDP_INIT_SEQ_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000103C, 0x80, 0, 10, 0, 0}, + [IPA_HW_v5_5][IPA_ENDP_STATUS_n] = { + ipareg_construct_endp_status_n_v5_0, ipareg_parse_dummy, + 0x00001040, 0x80, 0, 30, 1, 0}, + [IPA_HW_v5_5][IPA_ENDP_INIT_CONN_TRACK_n] = { + ipareg_construct_endp_init_conn_track_n, + ipareg_parse_dummy, + 0x00001050, 0x80, 0, 10, 0, 0}, + [IPA_HW_v5_5][IPA_ENDP_FILTER_ROUTER_HSH_CFG_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0x70, 0, 31, 1, 0}, + [IPA_HW_v5_5][IPA_FILTER_CACHE_CFG_n] = { + ipareg_construct_cache_cfg_n, ipareg_parse_cache_cfg_n, + 0x0000105C , 0x80, 0, 31, 1, 0}, + [IPA_HW_v5_5][IPA_ROUTER_CACHE_CFG_n] = { + ipareg_construct_cache_cfg_n, ipareg_parse_cache_cfg_n, + 0x00001070 , 0x80, 0, 31, 1, 0}, + [IPA_HW_v5_5][IPA_ENDP_INIT_CTRL_STATUS_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00001068, 0x80, 0, 30, 1, 0}, + [IPA_HW_v5_5][IPA_ENDP_INIT_HDR_METADATA_MASK_n] = { + ipareg_construct_endp_init_hdr_metadata_mask_n, + ipareg_parse_dummy, + 0x00001018, 0x80, 13, 30, 1, 0}, + [IPA_HW_v5_5][IPA_ENDP_INIT_HOL_BLOCK_EN_n] = { + ipareg_construct_endp_init_hol_block_en_n, + ipareg_parse_dummy, + 0x0000102c, 0x80, 13, 30, 1, 0}, + [IPA_HW_v5_5][IPA_ENDP_INIT_HOL_BLOCK_TIMER_n] = { + ipareg_construct_endp_init_hol_block_timer_n_v5_0, + ipareg_parse_dummy, + 0x00001030, 0x80, 13, 30, 1, 0}, + [IPA_HW_v5_5][IPA_ENDP_INIT_PROD_CFG_n] = { + ipareg_construct_endp_init_prod_cfg_n_v5_5, ipareg_parse_endp_init_prod_cfg_n_v5_5, + 0x0000106C, 0x80, 13, 30, 1, 0}, + [IPA_HW_v5_5][IPA_COAL_EVICT_LRU] = { + ipareg_construct_coal_evict_lru_v5_5, ipareg_parse_coal_evict_lru_v5_5, + 0x00000918, 0, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_COAL_MASTER_CFG] = { + ipareg_construct_coal_master_cfg, ipareg_parse_coal_master_cfg, + 0x00000914, 0, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_COAL_QMAP_CFG] = { + ipareg_construct_coal_qmap_cfg, ipareg_parse_coal_qmap_cfg, + 0x0000091c, 0, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_ULSO_CFG_IP_ID_MIN_VALUE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000934, 0x4, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_ULSO_CFG_IP_ID_MAX_VALUE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000924, 0x4, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_TSP_QM_EXTERNAL_BADDR_LSB] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000A00, 0, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_TSP_QM_EXTERNAL_BADDR_MSB] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000A04, 0, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_TSP_QM_EXTERNAL_SIZE] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000A08, 0, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_TSP_INGRESS_POLICING_CFG] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000A0C, 0, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_TSP_EGRESS_POLICING_CFG] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000A10, 0, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_STAT_TSP_DROP_BASE] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000A14, 0, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_STATE_QMNGR_QUEUE_NONEMPTY] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000A18, 0, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_ENDP_INIT_ULSO_CFG_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00001070, 0x80, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_ENDP_INIT_NAT_EXC_SUPPRESS_n] = { + ipareg_construct_endp_init_nat_exc_suppress_n, ipareg_parse_dummy, + 0x00001078, 0x80, 0, 0, 0, 0}, + + /* IPA_DEBUG */ + [IPA_HW_v5_5][IPA_RX_HPS_CLIENTS_MIN_DEPTH_1] = { //TODO contstruct not matching previous version + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000082C8, 0, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_RX_HPS_CLIENTS_MAX_DEPTH_1] = { //TODO contstruct not matching previous version + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000082D0, 0, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_RX_HPS_CLIENTS_MIN_DEPTH_0] = { + ipareg_construct_rx_hps_clients_depth0_v4_5, + ipareg_parse_dummy, + 0x000082c4, 0, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_RX_HPS_CLIENTS_MAX_DEPTH_0] = { + ipareg_construct_rx_hps_clients_depth0_v4_5, + ipareg_parse_dummy, + 0x000082CC, 0, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_DPS_SEQUENCER_FIRST] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00008584, 0, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_DPS_SEQUENCER_LAST] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00008588, 0, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_HPS_SEQUENCER_FIRST] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000858C, 0, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_HPS_SEQUENCER_LAST] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00008590, 0, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_RAM_INGRESS_POLICER_DB_BASE_ADDR] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000085DC, 0, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_RAM_EGRESS_SHAPING_PROD_DB_BASE_ADDR] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000085E0, 0, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_RAM_EGRESS_SHAPING_TC_DB_BASE_ADDR] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000085E4, 0, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_ENDP_GSI_CFG1_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00008800, 0x4, 0, 30, 0, 0}, + [IPA_HW_v5_5][IPA_ENDP_GSI_CFG_TLV_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00009000, 0x4, 0, 30, 0, 0}, + [IPA_HW_v5_5][IPA_ENDP_GSI_CFG_AOS_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00009400, 0x4, 0, 30, 0, 0}, + + /* IPA_EE */ + [IPA_HW_v5_5][IPA_IRQ_STTS_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000C008, 0x1000, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_IRQ_EN_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000C00c, 0x1000, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_IRQ_CLR_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000C010, 0x1000, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_SNOC_FEC_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000C018, 0x1000, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_SUSPEND_IRQ_INFO_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0x1000, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_SUSPEND_IRQ_INFO_EE_n_REG_k] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000C030, 0x1000, 0, 0, 0, 0x4}, + [IPA_HW_v5_5][IPA_SUSPEND_IRQ_EN_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0x1000, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_SUSPEND_IRQ_EN_EE_n_REG_k] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000C050, 0x1000, 0, 0, 0, 0x4}, + [IPA_HW_v5_5][IPA_SUSPEND_IRQ_CLR_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0x1000, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_SUSPEND_IRQ_CLR_EE_n_REG_k] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000C070, 0x1000, 0, 0, 0, 0x4}, + [IPA_HW_v5_5][IPA_HOLB_DROP_IRQ_INFO_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0x1000, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_HOLB_DROP_IRQ_EN_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0x1000, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_HOLB_DROP_IRQ_CLR_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0x1000, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_IRQ_EE_UC_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000C01c, 0x1000, 0, 0, 1, 0}, + [IPA_HW_v5_5][IPA_FEC_ADDR_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_FEC_ADDR_MSB_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0, 0, 0, 0, 0}, + [IPA_HW_v5_5][IPA_FEC_ATTR_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0, 0, 0, 0, 0}, + +}; + +/* + * ipahal_print_all_regs() - Loop and read and print all the valid registers + * Parameterized registers are also printed for all the valid ranges. + * Print to dmsg and IPC logs + */ +void ipahal_print_all_regs(bool print_to_dmesg) +{ + int i, j; + struct ipahal_reg_obj *reg; + + IPAHAL_DBG("Printing all registers for ipa_hw_type %d\n", + ipahal_ctx->hw_type); + + if ((ipahal_ctx->hw_type < IPA_HW_v4_0) || + (ipahal_ctx->hw_type >= IPA_HW_MAX)) { + IPAHAL_ERR("invalid IPA HW type (%d)\n", ipahal_ctx->hw_type); + return; + } + + for (i = 0; i < IPA_REG_MAX ; i++) { + reg = &(ipahal_reg_objs[ipahal_ctx->hw_type][i]); + + /* skip obsolete registers */ + if (reg->offset == -1) + continue; + + if (!reg->en_print) + continue; + + j = reg->n_start; + + if (j == reg->n_end && (reg->n_ofst == 0)) { + if (print_to_dmesg) + IPAHAL_DBG_REG("%s=0x%x\n", + ipahal_reg_name_str(i), + ipahal_read_reg_n(i, j)); + else + IPAHAL_DBG_REG_IPC_ONLY("%s=0x%x\n", + ipahal_reg_name_str(i), + ipahal_read_reg_n(i, j)); + } else { + for (; j <= reg->n_end; j++) { + if (print_to_dmesg) + IPAHAL_DBG_REG("%s_%u=0x%x\n", + ipahal_reg_name_str(i), + j, ipahal_read_reg_n(i, j)); + else + IPAHAL_DBG_REG_IPC_ONLY("%s_%u=0x%x\n", + ipahal_reg_name_str(i), + j, ipahal_read_reg_n(i, j)); + } + } + } +} + +/* + * ipahal_reg_init() - Build the registers information table + * See ipahal_reg_objs[][] comments + * + * Note: As global variables are initialized with zero, any un-overridden + * register entry will be zero. By this we recognize them. + */ +int ipahal_reg_init(enum ipa_hw_type ipa_hw_type) +{ + int i; + int j; + struct ipahal_reg_obj zero_obj; + + IPAHAL_DBG_LOW("Entry - HW_TYPE=%d\n", ipa_hw_type); + + if ((ipa_hw_type < 0) || (ipa_hw_type >= IPA_HW_MAX)) { + IPAHAL_ERR("invalid IPA HW type (%d)\n", ipa_hw_type); + return -EINVAL; + } + + memset(&zero_obj, 0, sizeof(zero_obj)); + for (i = IPA_HW_v3_0 ; i < ipa_hw_type ; i++) { + for (j = 0; j < IPA_REG_MAX ; j++) { + if (!memcmp(&ipahal_reg_objs[i+1][j], &zero_obj, + sizeof(struct ipahal_reg_obj))) { + memcpy(&ipahal_reg_objs[i+1][j], + &ipahal_reg_objs[i][j], + sizeof(struct ipahal_reg_obj)); + } else { + /* + * explicitly overridden register. + * Check validity + */ + if (!ipahal_reg_objs[i+1][j].offset && + (i + 1 < IPA_HW_v5_0 || j != IPA_FLAVOR_0)) { + IPAHAL_ERR( + "reg=%s with zero offset ipa_ver=%d\n", + ipahal_reg_name_str(j), i+1); + WARN_ON(1); + } + if (!ipahal_reg_objs[i+1][j].construct) { + IPAHAL_ERR( + "reg=%s with NULL construct func ipa_ver=%d\n", + ipahal_reg_name_str(j), i+1); + WARN_ON(1); + } + if (!ipahal_reg_objs[i+1][j].parse) { + IPAHAL_ERR( + "reg=%s with NULL parse func ipa_ver=%d\n", + ipahal_reg_name_str(j), i+1); + WARN_ON(1); + } + } + } + } + + return 0; +} + +/* + * ipahal_reg_name_str() - returns string that represent the register + * @reg_name: [in] register name + */ +const char *ipahal_reg_name_str(enum ipahal_reg_name reg_name) +{ + if (reg_name < 0 || reg_name >= IPA_REG_MAX) { + IPAHAL_ERR("requested name of invalid reg=%d\n", reg_name); + return "Invalid Register"; + } + + return ipareg_name_to_str[reg_name]; +} + +/* + * ipahal_read_reg_n() - Get n parameterized reg value + */ +u32 ipahal_read_reg_n(enum ipahal_reg_name reg, u32 n) +{ + u32 offset; + + if (reg >= IPA_REG_MAX) { + IPAHAL_ERR("Invalid register reg=%u\n", reg); + WARN_ON(1); + return -EINVAL; + } + + IPAHAL_DBG_LOW("read from %s n=%u\n", + ipahal_reg_name_str(reg), n); + + offset = ipahal_reg_objs[ipahal_ctx->hw_type][reg].offset; + if (offset == -1) { + IPAHAL_ERR("Read access to obsolete reg=%s\n", + ipahal_reg_name_str(reg)); + WARN_ON(1); + return -EPERM; + } + offset += ipahal_reg_objs[ipahal_ctx->hw_type][reg].n_ofst * n; + return ioread32(ipahal_ctx->base + offset); +} + +/* +* ipahal_read_ep_reg() - Get the raw value of a ep reg +*/ +u32 ipahal_read_ep_reg(enum ipahal_reg_name reg, u32 ep_num) +{ + return ipahal_read_reg_n(reg, IPA_BIT_MAP_CELL_NUM(ep_num)); +} + +/* + * ipahal_test_ep_bit() - return true if a ep bit is set + */ +bool ipahal_test_ep_bit(u32 reg_val, u32 ep_num) +{ + return !!(reg_val & IPA_BIT_MAP_CELL_MSK(ep_num)); +} + +/* + * ipahal_get_ep_bit() - get ep bit set in the right offset + */ +u32 ipahal_get_ep_bit(u32 ep_num) +{ + return IPA_BIT_MAP_CELL_MSK(ep_num); +} +EXPORT_SYMBOL(ipahal_get_ep_bit); + +/* + * ipahal_get_ep_reg_idx() - get ep reg index according to ep num + */ +u32 ipahal_get_ep_reg_idx(u32 ep_num) +{ + return IPA_BIT_MAP_CELL_NUM(ep_num); +} +EXPORT_SYMBOL(ipahal_get_ep_reg_idx); + +/* + * ipahal_read_reg_mn() - Get mn parameterized reg value + */ +u32 ipahal_read_reg_mn(enum ipahal_reg_name reg, u32 m, u32 n) +{ + u32 offset; + + if (reg >= IPA_REG_MAX) { + IPAHAL_ERR("Invalid register reg=%u\n", reg); + WARN_ON(1); + return -EINVAL; + } + + IPAHAL_DBG_LOW("read %s m=%u n=%u\n", + ipahal_reg_name_str(reg), m, n); + offset = ipahal_reg_objs[ipahal_ctx->hw_type][reg].offset; + if (offset == -1) { + IPAHAL_ERR("Read access to obsolete reg=%s\n", + ipahal_reg_name_str(reg)); + WARN_ON_ONCE(1); + return -EPERM; + } + + offset += ipahal_reg_objs[ipahal_ctx->hw_type][reg].m_ofst * m; + offset += ipahal_reg_objs[ipahal_ctx->hw_type][reg].n_ofst * n; + return ioread32(ipahal_ctx->base + offset); +} + +/* +* ipahal_read_ep_reg_n() - Get n parameterized reg value according to ep +*/ +u32 ipahal_read_ep_reg_n(enum ipahal_reg_name reg, u32 n, u32 ep_num) +{ + return ipahal_read_reg_mn(reg, IPA_BIT_MAP_CELL_NUM(ep_num), n); +} + +/* + * ipahal_write_reg_mn() - Write to m/n parameterized reg a raw value + */ +void ipahal_write_reg_mn(enum ipahal_reg_name reg, u32 m, u32 n, u32 val) +{ + u32 offset; + + if (reg >= IPA_REG_MAX) { + IPAHAL_ERR("Invalid register reg=%u\n", reg); + WARN_ON(1); + return; + } + + IPAHAL_DBG_LOW("write to %s m=%u n=%u val=%u\n", + ipahal_reg_name_str(reg), m, n, val); + offset = ipahal_reg_objs[ipahal_ctx->hw_type][reg].offset; + if (offset == -1) { + IPAHAL_ERR("Write access to obsolete reg=%s\n", + ipahal_reg_name_str(reg)); + WARN_ON(1); + return; + } + + offset += ipahal_reg_objs[ipahal_ctx->hw_type][reg].m_ofst * m; + offset += ipahal_reg_objs[ipahal_ctx->hw_type][reg].n_ofst * n; + iowrite32(val, ipahal_ctx->base + offset); +} + +/* + * ipahal_write_ep_reg() - Write to ep reg a raw value + */ +void ipahal_write_ep_reg(enum ipahal_reg_name reg, u32 ep_num, u32 val) +{ + return ipahal_write_reg_n(reg, IPA_BIT_MAP_CELL_NUM(ep_num), val); +} + +/* + * ipahal_write_ep_reg_n() - Write to ep reg a raw value + */ +void ipahal_write_ep_reg_n(enum ipahal_reg_name reg, u32 n, u32 ep_num, u32 val) +{ + return ipahal_write_reg_mn(reg, IPA_BIT_MAP_CELL_NUM(ep_num), n, val); +} + +/* + * ipahal_read_reg_n_fields() - Get the parsed value of n parameterized reg + */ +u32 ipahal_read_reg_n_fields(enum ipahal_reg_name reg, u32 n, void *fields) +{ + u32 val = 0; + u32 offset; + + if (!fields) { + IPAHAL_ERR("Input error fields\n"); + WARN_ON(1); + return -EINVAL; + } + + if (reg >= IPA_REG_MAX) { + IPAHAL_ERR("Invalid register reg=%u\n", reg); + WARN_ON(1); + return -EINVAL; + } + + IPAHAL_DBG_LOW("read from %s n=%u and parse it\n", + ipahal_reg_name_str(reg), n); + offset = ipahal_reg_objs[ipahal_ctx->hw_type][reg].offset; + if (offset == -1) { + IPAHAL_ERR("Read access to obsolete reg=%s\n", + ipahal_reg_name_str(reg)); + WARN_ON(1); + return -EPERM; + } + offset += ipahal_reg_objs[ipahal_ctx->hw_type][reg].n_ofst * n; + val = ioread32(ipahal_ctx->base + offset); + ipahal_reg_objs[ipahal_ctx->hw_type][reg].parse(reg, fields, val); + + return val; +} + +/* + * ipahal_write_reg_n_fields() - Write to n parameterized reg a prased value + */ +void ipahal_write_reg_n_fields(enum ipahal_reg_name reg, u32 n, + const void *fields) +{ + u32 val = 0; + u32 offset; + + if (!fields) { + IPAHAL_ERR("Input error fields=%pK\n", fields); + WARN_ON(1); + return; + } + + if (reg >= IPA_REG_MAX) { + IPAHAL_ERR("Invalid register reg=%u\n", reg); + WARN_ON(1); + return; + } + + IPAHAL_DBG_LOW("write to %s n=%u after constructing it\n", + ipahal_reg_name_str(reg), n); + offset = ipahal_reg_objs[ipahal_ctx->hw_type][reg].offset; + if (offset == -1) { + IPAHAL_ERR("Write access to obsolete reg=%s\n", + ipahal_reg_name_str(reg)); + WARN_ON(1); + return; + } + offset += ipahal_reg_objs[ipahal_ctx->hw_type][reg].n_ofst * n; + ipahal_reg_objs[ipahal_ctx->hw_type][reg].construct(reg, fields, &val); + + iowrite32(val, ipahal_ctx->base + offset); +} + +/* + * Get the offset of a m/n parameterized register + */ +u32 ipahal_get_reg_mn_ofst(enum ipahal_reg_name reg, u32 m, u32 n) +{ + u32 offset; + + if (reg >= IPA_REG_MAX) { + IPAHAL_ERR("Invalid register reg=%u\n", reg); + WARN_ON(1); + return -EINVAL; + } + + IPAHAL_DBG_LOW("get offset of %s m=%u n=%u\n", + ipahal_reg_name_str(reg), m, n); + offset = ipahal_reg_objs[ipahal_ctx->hw_type][reg].offset; + if (offset == -1) { + IPAHAL_ERR("Access to obsolete reg=%s\n", + ipahal_reg_name_str(reg)); + WARN_ON(1); + return -EPERM; + } + + offset += ipahal_reg_objs[ipahal_ctx->hw_type][reg].m_ofst * m; + offset += ipahal_reg_objs[ipahal_ctx->hw_type][reg].n_ofst * n; + + return offset; +} + +/* + * Get the offset of a ep register according to ep index + */ +u32 ipahal_get_ep_reg_offset(enum ipahal_reg_name reg, u32 ep_num) +{ + return ipahal_get_reg_mn_ofst(reg, 0, IPA_BIT_MAP_CELL_NUM(ep_num)); +} + +/* +* Get the offset of a ep n register according to ep index and n +*/ +u32 ipahal_get_reg_nk_offset(enum ipahal_reg_name reg, u32 n, u32 k) +{ + return ipahal_get_reg_mn_ofst(reg, k, n); +} + +u32 ipahal_get_reg_base(void) +{ + if (!ipahal_ctx || ipahal_ctx->ipa_cfg_offset == 0) + return 0x00040000; + else + return ipahal_ctx->ipa_cfg_offset; +} + + +/* + * Specific functions + * These functions supply specific register values for specific operations + * that cannot be reached by generic functions. + * E.g. To disable aggregation, need to write to specific bits of the AGGR + * register. The other bits should be untouched. This oeprate is very specific + * and cannot be generically defined. For such operations we define these + * specific functions. + */ + +void ipahal_get_aggr_force_close_valmask(int ep_idx, + struct ipahal_reg_valmask *valmask) +{ + u32 shft = 0; + u32 bmsk = 0; + + if (!valmask) { + IPAHAL_ERR("Input error\n"); + return; + } + + memset(valmask, 0, sizeof(struct ipahal_reg_valmask)); + + if (ipahal_ctx->hw_type <= IPA_HW_v3_1) { + shft = IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_SHFT; + bmsk = IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_BMSK; + } else if (ipahal_ctx->hw_type <= IPA_HW_v3_5_1) { + shft = + IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_SHFT_V3_5; + bmsk = + IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_BMSK_V3_5; + } else if (ipahal_ctx->hw_type <= IPA_HW_v4_1) { + shft = + IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_SHFT_V4_0; + bmsk = + IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_BMSK_V4_0; + } else if (ipahal_ctx->hw_type <= IPA_HW_v4_2) { + shft = + IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_SHFT_V4_2; + bmsk = + IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_BMSK_V4_2; + } else if (ipahal_ctx->hw_type <= IPA_HW_v4_5) { + shft = + IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_SHFT_V4_5; + bmsk = + IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_BMSK_V4_5; + } else if (ipahal_ctx->hw_type <= IPA_HW_v4_9) { + shft = + IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_SHFT_V4_9; + bmsk = + IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_BMSK_V4_9; + } else if (ipahal_ctx->hw_type <= IPA_HW_v5_5) { + u8 reg_idx; + + shft = + IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_SHFT_V5_0; + + reg_idx = IPA_BIT_MAP_CELL_NUM(ep_idx); + bmsk = (reg_idx ? + IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_BMSK_2_v5_0 : + IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_BMSK_v5_0); + } else { + IPAHAL_ERR("unknown ipa ver %d\n", ipahal_ctx->hw_type); + ipa_assert(); + return; + } + + IPA_SETFIELD_IN_REG(valmask->val, + IPA_BIT_MAP_CELL_MSK(ep_idx), + shft, bmsk); + valmask->mask = bmsk; +} + +void ipahal_get_fltrt_hash_flush_valmask( + struct ipahal_reg_fltrt_hash_flush *flush, + struct ipahal_reg_valmask *valmask) +{ + if (!flush || !valmask) { + IPAHAL_ERR("Input error: flush=%pK ; valmask=%pK\n", + flush, valmask); + return; + } + + memset(valmask, 0, sizeof(struct ipahal_reg_valmask)); + + if (flush->v6_rt) + valmask->val |= + (1<v6_flt) + valmask->val |= + (1<v4_rt) + valmask->val |= + (1<v4_flt) + valmask->val |= + (1<mask = valmask->val; +} + +void ipahal_get_fltrt_cache_flush_valmask( + struct ipahal_reg_fltrt_cache_flush *flush, + struct ipahal_reg_valmask *valmask) +{ + if (!flush || !valmask) { + IPAHAL_ERR("Input error: flush=%pK ; valmask=%pK\n", + flush, valmask); + return; + } + + memset(valmask, 0, sizeof(struct ipahal_reg_valmask)); + + if (flush->rt) + valmask->val |= + (1 << IPA_FILT_ROUT_CACHE_FLUSH_ROUT_SHFT); + if (flush->flt) + valmask->val |= + (1 << IPA_FILT_ROUT_CACHE_FLUSH_FILT_SHFT); + valmask->mask = valmask->val; +} diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.h new file mode 100644 index 0000000000..0293629c12 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.h @@ -0,0 +1,1129 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _IPAHAL_REG_H_ +#define _IPAHAL_REG_H_ + +#include "ipa.h" + +/* + * Registers names + * + * NOTE:: Any change to this enum, need to change to ipareg_name_to_str + * array as well. + */ +enum ipahal_reg_name { + IPA_ROUTE, + IPA_IRQ_STTS_EE_n, + IPA_IRQ_EN_EE_n, + IPA_IRQ_CLR_EE_n, + IPA_SUSPEND_IRQ_INFO_EE_n, + IPA_SUSPEND_IRQ_EN_EE_n, + IPA_SUSPEND_IRQ_CLR_EE_n, + IPA_HOLB_DROP_IRQ_INFO_EE_n, + IPA_HOLB_DROP_IRQ_EN_EE_n, + IPA_HOLB_DROP_IRQ_CLR_EE_n, + IPA_BCR, + IPA_ENABLED_PIPES, + IPA_VERSION, + IPA_TAG_TIMER, + IPA_NAT_TIMER, + IPA_COMP_HW_VERSION, + IPA_COMP_CFG, + IPA_STATE_TX_WRAPPER, + IPA_STATE_TX1, + IPA_STATE_FETCHER, + IPA_STATE_FETCHER_MASK, + IPA_STATE_FETCHER_MASK_0, + IPA_STATE_FETCHER_MASK_1, + IPA_STATE_DFETCHER, + IPA_STATE_ACL, + IPA_STATE, + IPA_STATE_RX_ACTIVE, + IPA_STATE_TX0, + IPA_STATE_TSP, + IPA_STATE_AGGR_ACTIVE, + IPA_COUNTER_CFG, + IPA_STATE_GSI_TLV, + IPA_STATE_GSI_AOS, + IPA_STATE_GSI_IF, + IPA_STATE_GSI_SKIP, + IPA_STATE_GSI_IF_CONS, + IPA_STATE_DPL_FIFO, + IPA_STATE_COAL_MASTER, + IPA_GENERIC_RAM_ARBITER_PRIORITY, + IPA_STATE_NLO_AGGR, + IPA_STATE_COAL_MASTER_1, + IPA_ENDP_INIT_HDR_n, + IPA_ENDP_INIT_HDR_EXT_n, + IPA_ENDP_INIT_AGGR_n, + IPA_AGGR_FORCE_CLOSE, + IPA_ENDP_INIT_ROUTE_n, + IPA_ENDP_INIT_MODE_n, + IPA_ENDP_INIT_NAT_n, + IPA_ENDP_INIT_CONN_TRACK_n, + IPA_ENDP_INIT_CTRL_n, + IPA_ENDP_INIT_CTRL_SCND_n, + IPA_ENDP_INIT_CTRL_STATUS_n, + IPA_ENDP_INIT_HOL_BLOCK_EN_n, + IPA_ENDP_INIT_HOL_BLOCK_TIMER_n, + IPA_ENDP_INIT_DEAGGR_n, + IPA_ENDP_INIT_SEQ_n, + IPA_DEBUG_CNT_REG_n, + IPA_ENDP_INIT_CFG_n, + IPA_IRQ_EE_UC_n, + IPA_ENDP_INIT_HDR_METADATA_MASK_n, + IPA_ENDP_INIT_HDR_METADATA_n, + IPA_ENDP_INIT_PROD_CFG_n, + IPA_ENDP_INIT_RSRC_GRP_n, + IPA_SHARED_MEM_SIZE, + IPA_SW_AREA_RAM_DIRECT_ACCESS_n, + IPA_DEBUG_CNT_CTRL_n, + IPA_UC_MAILBOX_m_n, + IPA_FILT_ROUT_HASH_FLUSH, + IPA_FILT_ROUT_HASH_EN, + IPA_SINGLE_NDP_MODE, + IPA_QCNCM, + IPA_SYS_PKT_PROC_CNTXT_BASE, + IPA_LOCAL_PKT_PROC_CNTXT_BASE, + IPA_ENDP_STATUS_n, + IPA_ENDP_YELLOW_RED_MARKER_CFG_n, + IPA_ENDP_FILTER_ROUTER_HSH_CFG_n, + IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n, + IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n, + IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n, + IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n, + IPA_DST_RSRC_GRP_01_RSRC_TYPE_n, + IPA_DST_RSRC_GRP_23_RSRC_TYPE_n, + IPA_DST_RSRC_GRP_45_RSRC_TYPE_n, + IPA_DST_RSRC_GRP_67_RSRC_TYPE_n, + IPA_RSRC_GRP_CFG, + IPA_RSRC_GRP_CFG_EXT, + IPA_RX_HPS_CLIENTS_MIN_DEPTH_0, + IPA_RX_HPS_CLIENTS_MIN_DEPTH_1, + IPA_RX_HPS_CLIENTS_MAX_DEPTH_0, + IPA_RX_HPS_CLIENTS_MAX_DEPTH_1, + IPA_HPS_FTCH_ARB_QUEUE_WEIGHT, + IPA_QSB_MAX_WRITES, + IPA_QSB_MAX_READS, + IPA_TX_CFG, + IPA_IDLE_INDICATION_CFG, + IPA_DPS_SEQUENCER_FIRST, + IPA_DPS_SEQUENCER_LAST, + IPA_HPS_SEQUENCER_FIRST, + IPA_HPS_SEQUENCER_LAST, + IPA_CLKON_CFG, + IPA_QTIME_TIMESTAMP_CFG, + IPA_TIMERS_PULSE_GRAN_CFG, + IPA_TIMERS_XO_CLK_DIV_CFG, + IPA_STAT_QUOTA_BASE_n, + IPA_STAT_QUOTA_MASK_n, + IPA_STAT_TETHERING_BASE_n, + IPA_STAT_TETHERING_MASK_n, + IPA_STAT_FILTER_IPV4_BASE, + IPA_STAT_FILTER_IPV6_BASE, + IPA_STAT_ROUTER_IPV4_BASE, + IPA_STAT_ROUTER_IPV6_BASE, + IPA_STAT_FILTER_IPV4_START_ID, + IPA_STAT_FILTER_IPV6_START_ID, + IPA_STAT_ROUTER_IPV4_START_ID, + IPA_STAT_ROUTER_IPV6_START_ID, + IPA_STAT_FILTER_IPV4_END_ID, + IPA_STAT_FILTER_IPV6_END_ID, + IPA_STAT_ROUTER_IPV4_END_ID, + IPA_STAT_ROUTER_IPV6_END_ID, + IPA_STAT_DROP_CNT_BASE_n, + IPA_STAT_DROP_CNT_MASK_n, + IPA_SNOC_FEC_EE_n, + IPA_FEC_ADDR_EE_n, + IPA_FEC_ADDR_MSB_EE_n, + IPA_FEC_ATTR_EE_n, + IPA_ENDP_GSI_CFG1_n, + IPA_ENDP_GSI_CFG_AOS_n, + IPA_ENDP_GSI_CFG_TLV_n, + IPA_COAL_EVICT_LRU, + IPA_COAL_QMAP_CFG, + IPA_FLAVOR_0, + IPA_FLAVOR_9, + IPA_STATE_AGGR_ACTIVE_n, + IPA_AGGR_FORCE_CLOSE_n, + IPA_STAT_QUOTA_MASK_EE_n_REG_k, + IPA_SUSPEND_IRQ_INFO_EE_n_REG_k, + IPA_SUSPEND_IRQ_CLR_EE_n_REG_k, + IPA_SUSPEND_IRQ_EN_EE_n_REG_k, + IPA_STAT_TETHERING_MASK_EE_n_REG_k, + IPA_STAT_DROP_CNT_MASK_EE_n_REG_k, + IPA_FILT_ROUT_CACHE_FLUSH, + IPA_FILTER_CACHE_CFG_n, + IPA_ROUTER_CACHE_CFG_n, + IPA_NAT_UC_EXTERNAL_CFG, + IPA_NAT_UC_LOCAL_CFG, + IPA_NAT_UC_SHARED_CFG, + IPA_CONN_TRACK_UC_EXTERNAL_CFG, + IPA_CONN_TRACK_UC_LOCAL_CFG, + IPA_CONN_TRACK_UC_SHARED_CFG, + IPA_ULSO_CFG_IP_ID_MIN_VALUE_n, + IPA_ULSO_CFG_IP_ID_MAX_VALUE_n, + IPA_ENDP_INIT_ULSO_CFG_n, + IPA_ENDP_INIT_NAT_EXC_SUPPRESS_n, + IPA_TSP_QM_EXTERNAL_BADDR_LSB, + IPA_TSP_QM_EXTERNAL_BADDR_MSB, + IPA_TSP_QM_EXTERNAL_SIZE, + IPA_TSP_INGRESS_POLICING_CFG, + IPA_TSP_EGRESS_POLICING_CFG, + IPA_STAT_TSP_DROP_BASE, + IPA_STATE_QMNGR_QUEUE_NONEMPTY, + IPA_RAM_INGRESS_POLICER_DB_BASE_ADDR, + IPA_RAM_EGRESS_SHAPING_PROD_DB_BASE_ADDR, + IPA_RAM_EGRESS_SHAPING_TC_DB_BASE_ADDR, + IPA_COAL_MASTER_CFG, + IPA_IPV4_NAT_EXC_SUPPRESS_ROUT_TABLE_INDX, + IPA_IPV6_CONN_TRACK_EXC_SUPPRESS_ROUT_TABLE_INDX, + IPA_REG_MAX, +}; + +/* + * struct ipahal_reg_route - IPA route register + * @route_dis: route disable + * @route_def_pipe: route default pipe + * @route_def_hdr_table: route default header table + * @route_def_hdr_ofst: route default header offset table + * @route_frag_def_pipe: Default pipe to route fragmented exception + * packets and frag new rule statues, if source pipe does not have + * a notification status pipe defined. + * @route_def_retain_hdr: default value of retain header. It is used + * when no rule was hit + */ +struct ipahal_reg_route { + u32 route_dis; + u32 route_def_pipe; + u32 route_def_hdr_table; + u32 route_def_hdr_ofst; + u8 route_frag_def_pipe; + u32 route_def_retain_hdr; +}; + +/* + * struct ipahal_reg_endp_init_route - IPA ENDP_INIT_ROUTE_n register + * @route_table_index: Default index of routing table (IPA Consumer). + */ +struct ipahal_reg_endp_init_route { + u32 route_table_index; +}; + +/* + * struct ipahal_reg_endp_init_rsrc_grp - IPA_ENDP_INIT_RSRC_GRP_n register + * @rsrc_grp: Index of group for this ENDP. If this ENDP is a source-ENDP, + * index is for source-resource-group. If destination ENPD, index is + * for destination-resoruce-group. + */ +struct ipahal_reg_endp_init_rsrc_grp { + u32 rsrc_grp; +}; + +/* + * struct ipahal_reg_endp_init_mode - IPA ENDP_INIT_MODE_n register + * @dst_pipe_number: This parameter specifies destination output-pipe-packets + * will be routed to. Valid for DMA mode only and for Input + * Pipes only (IPA Consumer) + */ +struct ipahal_reg_endp_init_mode { + u32 dst_pipe_number; + struct ipa_ep_cfg_mode ep_mode; +}; + +/* + * struct ipahal_reg_shared_mem_size - IPA_SHARED_MEM_SIZE register + * @shared_mem_sz: Available size [in 8Bytes] of SW partition within + * IPA shared memory. + * @shared_mem_baddr: Offset of SW partition within IPA + * shared memory[in 8Bytes]. To get absolute address of SW partition, + * add this offset to IPA_SW_AREA_RAM_DIRECT_ACCESS_n baddr. + */ +struct ipahal_reg_shared_mem_size { + u32 shared_mem_sz; + u32 shared_mem_baddr; +}; + +/* + * struct ipahal_reg_ep_cfg_status - status configuration in IPA end-point + * @status_en: Determines if end point supports Status Indications. SW should + * set this bit in order to enable Statuses. Output Pipe - send + * Status indications only if bit is set. Input Pipe - forward Status + * indication to STATUS_ENDP only if bit is set. Valid for Input + * and Output Pipes (IPA Consumer and Producer) + * @status_ep: Statuses generated for this endpoint will be forwarded to the + * specified Status End Point. Status endpoint needs to be + * configured with STATUS_EN=1 Valid only for Input Pipes (IPA + * Consumer) + * @status_location: Location of PKT-STATUS on destination pipe. + * If set to 0 (default), PKT-STATUS will be appended before the packet + * for this endpoint. If set to 1, PKT-STATUS will be appended after the + * packet for this endpoint. Valid only for Output Pipes (IPA Producer) + * @status_pkt_suppress: Disable notification status, when statistics is enabled + */ +struct ipahal_reg_ep_cfg_status { + bool status_en; + u8 status_ep; + bool status_location; + u8 status_pkt_suppress; +}; + +/* + * struct ipahal_reg_clkon_cfg- Enables SW bypass clock-gating for the IPA core + * + * @all: Enables SW bypass clock-gating controls for this sub-module; + * 0: CGC is enabled by internal logic, 1: No CGC (clk is always 'ON'). + * sub-module affected is based on var name -> ex: open_rx refers + * to IPA_RX sub-module and open_global refers to global IPA 1x clock + */ +struct ipahal_reg_clkon_cfg { + bool open_dpl_fifo; + bool open_global_2x_clk; + bool open_global; + bool open_gsi_if; + bool open_weight_arb; + bool open_qmb; + bool open_ram_slaveway; + bool open_aggr_wrapper; + bool open_qsb2axi_cmdq_l; + bool open_fnr; + bool open_tx_1; + bool open_tx_0; + bool open_ntf_tx_cmdqs; + bool open_dcmp; + bool open_h_dcph; + bool open_d_dcph; + bool open_ack_mngr; + bool open_ctx_handler; + bool open_rsrc_mngr; + bool open_dps_tx_cmdqs; + bool open_hps_dps_cmdqs; + bool open_rx_hps_cmdqs; + bool open_dps; + bool open_hps; + bool open_ftch_dps; + bool open_ftch_hps; + bool open_ram_arb; + bool open_misc; + bool open_tx_wrapper; + bool open_proc; + bool open_rx; +}; + +/* + * struct ipahal_reg_qtime_timestamp_cfg - IPA timestamp configuration + * Relevant starting IPA 4.5. + * IPA timestamps are based on QTIMER which is 56bit length which is + * based on XO clk running at 19.2MHz (52nsec resolution). + * Specific timestamps (TAG, NAT, DPL) my require lower resolution. + * This can be achieved by omitting LSB bits from 56bit QTIMER. + * e.g. if we omit (shift) 24 bit then we get (2^24)*(52n)=0.87sec resolution. + * + * @dpl_timestamp_lsb: Shifting Qtime value. Value will be used as LSB of + * DPL timestamp. + * @dpl_timestamp_sel: if false, DPL timestamp will be based on legacy + * DPL_TIMER which counts in 1ms. if true, it will be based on QTIME + * value shifted by dpl_timestamp_lsb. + * @tag_timestamp_lsb: Shifting Qtime value. Value will be used as LSB of + * TAG timestamp. + * @nat_timestamp_lsb: Shifting Qtime value. Value will be used as LSB of + * NAT timestamp. + */ +struct ipahal_reg_qtime_timestamp_cfg { + u32 dpl_timestamp_lsb; + bool dpl_timestamp_sel; + u32 tag_timestamp_lsb; + u32 nat_timestamp_lsb; +}; + +/* + * enum ipa_timers_time_gran_type - Time granularity to be used with timers + * + * e.g. for HOLB and Aggregation timers + */ +enum ipa_timers_time_gran_type { + IPA_TIMERS_TIME_GRAN_10_USEC, + IPA_TIMERS_TIME_GRAN_20_USEC, + IPA_TIMERS_TIME_GRAN_50_USEC, + IPA_TIMERS_TIME_GRAN_100_USEC, + IPA_TIMERS_TIME_GRAN_1_MSEC, + IPA_TIMERS_TIME_GRAN_10_MSEC, + IPA_TIMERS_TIME_GRAN_100_MSEC, + IPA_TIMERS_TIME_GRAN_NEAR_HALF_SEC, /* 0.65536s */ + IPA_TIMERS_TIME_GRAN_MAX, +}; + +/* + * struct ipahal_reg_timers_pulse_gran_cfg - Counters tick granularities + * Relevant starting IPA 4.5. + * IPA timers are based on XO CLK running 19.2MHz (52ns resolution) deviced + * by clock divider (see IPA_TIMERS_XO_CLK_DIV_CFG) - default 100Khz (10usec). + * IPA timers instances (e.g. HOLB or AGGR) may require different resolutions. + * There are 3 global pulse generators with configurable granularity. Each + * timer instance can choose one of the three generators to work with. + * Each generator granularity can be one of supported ones. + * + * @gran_X: granularity tick of counterX + */ +struct ipahal_reg_timers_pulse_gran_cfg { + enum ipa_timers_time_gran_type gran_0; + enum ipa_timers_time_gran_type gran_1; + enum ipa_timers_time_gran_type gran_2; + enum ipa_timers_time_gran_type gran_3; +}; + +/* + * struct ipahal_reg_timers_xo_clk_div_cfg - IPA timers clock divider + * Used to control clock divider which gets XO_CLK of 19.2MHz as input. + * Output of CDIV is used to generate IPA timers granularity + * + * @enable: Enable of the clock divider for all IPA and GSI timers. + * clock is disabled by default, and need to be enabled when system is up. + * @value: Divided value to be used by CDIV. POR value is set to 191 + * to generate 100KHz clk based on XO_CLK. + * Values of ipahal_reg_timers_pulse_gran_cfg are based on this default. + */ +struct ipahal_reg_timers_xo_clk_div_cfg { + bool enable; + u32 value; +}; + +/* + * struct ipahal_reg_comp_cfg- IPA Core QMB/Master Port selection + * + * @enable / @ipa_dcmp_fast_clk_en: are not relevant starting IPA4.5 + * @ipa_full_flush_wait_rsc_closure_en: relevant starting IPA4.5 + */ +struct ipahal_reg_comp_cfg { + bool gen_qmb_0_dynamic_asize; + bool gen_qmb_1_dynamic_asize; + bool ipa_full_flush_wait_rsc_closure_en; + u8 ipa_atomic_fetcher_arb_lock_dis; + bool gsi_if_out_of_buf_stop_reset_mask_enable; + bool genqmb_aooowr; + bool qmb_ram_rd_cache_disable; + bool ipa_qmb_select_by_address_global_en; + bool gsi_multi_axi_masters_dis; + bool gsi_snoc_cnoc_loop_protection_disable; + bool gen_qmb_0_snoc_cnoc_loop_protection_disable; + bool gen_qmb_1_multi_inorder_wr_dis; + bool gen_qmb_0_multi_inorder_wr_dis; + bool gen_qmb_1_multi_inorder_rd_dis; + bool gen_qmb_0_multi_inorder_rd_dis; + bool gsi_multi_inorder_wr_dis; + bool gsi_multi_inorder_rd_dis; + bool ipa_qmb_select_by_address_prod_en; + bool ipa_qmb_select_by_address_cons_en; + bool ipa_dcmp_fast_clk_en; + bool gen_qmb_1_snoc_bypass_dis; + bool gen_qmb_0_snoc_bypass_dis; + bool gsi_snoc_bypass_dis; + bool ram_arb_priority_client_samp_fix_disable; + bool enable; +}; + +/* + * struct ipahal_reg_tx_wrapper- IPA TX Wrapper state information + */ +struct ipahal_reg_tx_wrapper { + bool tx0_idle; + bool tx1_idle; + bool ipa_prod_ackmngr_db_empty; + bool ipa_prod_ackmngr_state_idle; + bool ipa_prod_prod_bresp_empty; + bool ipa_prod_prod_bresp_toggle_idle; + bool ipa_mbim_pkt_fms_idle; + u8 mbim_direct_dma; + bool trnseq_force_valid; + bool pkt_drop_cnt_idle; + u8 nlo_direct_dma; + u8 coal_direct_dma; + bool coal_slave_idle; + bool coal_slave_ctx_idle; + u8 coal_slave_open_frame; +}; + +/* + * struct ipa_hash_tuple - Hash tuple members for flt and rt + * the fields tells if to be masked or not + * @src_id: pipe number for flt, table index for rt + * @src_ip_addr: IP source address + * @dst_ip_addr: IP destination address + * @src_port: L4 source port + * @dst_port: L4 destination port + * @protocol: IP protocol field + * @meta_data: packet meta-data + * + */ +struct ipahal_reg_hash_tuple { + /* src_id: pipe in flt, tbl index in rt */ + bool src_id; + bool src_ip_addr; + bool dst_ip_addr; + bool src_port; + bool dst_port; + bool protocol; + bool meta_data; +}; + +/* + * struct ipahal_reg_fltrt_hash_tuple - IPA hash tuple register + * @flt: Hash tuple info for filtering + * @rt: Hash tuple info for routing + * @undefinedX: Undefined/Unused bit fields set of the register + */ +struct ipahal_reg_fltrt_hash_tuple { + struct ipahal_reg_hash_tuple flt; + struct ipahal_reg_hash_tuple rt; + u32 undefined1; + u32 undefined2; +}; + +/* +* struct ipahal_reg_fltrt_cache_tuple - IPA cache tuple register +* @flt: cache tuple info for flt\rt +* @undefinedX: Undefined/Unused bit fields set of the register +*/ +struct ipahal_reg_fltrt_cache_tuple { + struct ipahal_reg_hash_tuple tuple; + u32 undefined; +}; + +/* + * enum ipahal_reg_dbg_cnt_type - Debug Counter Type + * DBG_CNT_TYPE_IPV4_FLTR - Count IPv4 filtering rules + * DBG_CNT_TYPE_IPV4_ROUT - Count IPv4 routing rules + * DBG_CNT_TYPE_GENERAL - General counter + * DBG_CNT_TYPE_IPV6_FLTR - Count IPv6 filtering rules + * DBG_CNT_TYPE_IPV4_ROUT - Count IPv6 routing rules + */ +enum ipahal_reg_dbg_cnt_type { + DBG_CNT_TYPE_IPV4_FLTR, + DBG_CNT_TYPE_IPV4_ROUT, + DBG_CNT_TYPE_GENERAL, + DBG_CNT_TYPE_IPV6_FLTR, + DBG_CNT_TYPE_IPV6_ROUT, +}; + +/* + * struct ipahal_reg_debug_cnt_ctrl - IPA_DEBUG_CNT_CTRL_n register + * @en - Enable debug counter + * @type - Type of debugging couting + * @product - False->Count Bytes . True->Count #packets + * @src_pipe - Specific Pipe to match. If FF, no need to match + * specific pipe + * @rule_idx_pipe_rule - Global Rule or Pipe Rule. If pipe, then indicated by + * src_pipe. Starting at IPA V3_5, + * no support on Global Rule. This field will be ignored. + * @rule_idx - Rule index. Irrelevant for type General + */ +struct ipahal_reg_debug_cnt_ctrl { + bool en; + enum ipahal_reg_dbg_cnt_type type; + bool product; + u8 src_pipe; + bool rule_idx_pipe_rule; + u16 rule_idx; +}; + +/* + * struct ipahal_reg_rsrc_grp_xy_cfg - Min/Max values for two rsrc groups + * @x_min - first group min value + * @x_max - first group max value + * @y_min - second group min value + * @y_max - second group max value + */ +struct ipahal_reg_rsrc_grp_xy_cfg { + u32 x_min; + u32 x_max; + u32 y_min; + u32 y_max; +}; + +/* + * struct ipahal_reg_rsrc_grp_cfg - General configuration of resource group behavior + * @src_grp_index - Index of special source resource group + * @src_grp_valid - Set to 1 if a special source resrouce group exists + * @dst_pipe_index - Index of special destination pipe + * @dst_pipe_valid - Set to 1 if a special destination pipe exists + * @dst_grp_index - Index of special destination resource group + * @dst_grp_valid - Set to 1 if a special destination resrouce group exists + */ +struct ipahal_reg_rsrc_grp_cfg { + u8 src_grp_index; + bool src_grp_valid; + u8 dst_pipe_index; + bool dst_pipe_valid; + u8 dst_grp_index; + bool dst_grp_valid; +}; + +/* + * struct ipahal_reg_rsrc_grp_cfg_ext - General configuration of resource group behavior extended + * @index - Index of 2nd-priority special source resource group. + * Will be chosen only in case 1st-level priority group is not requesting service. + * @valid - Set to 1 if a 2nd-priority special source resrouce group exists + */ +struct ipahal_reg_rsrc_grp_cfg_ext { + u8 index; + bool valid; +}; + +/* + * struct ipahal_reg_rx_hps_clients - Min or Max values for RX HPS clients + * @client_minmax - Min or Max values. In case of depth 0 the 4 or 5 values + * are used. In case of depth 1, only the first 2 values are used + */ +struct ipahal_reg_rx_hps_clients { + u32 client_minmax[5]; +}; + +/* + * struct ipahal_reg_rx_hps_weights - weight values for RX HPS clients + * @hps_queue_weight_0 - 4 bit Weight for RX_HPS_CMDQ #0 (3:0) + * @hps_queue_weight_1 - 4 bit Weight for RX_HPS_CMDQ #1 (7:4) + * @hps_queue_weight_2 - 4 bit Weight for RX_HPS_CMDQ #2 (11:8) + * @hps_queue_weight_3 - 4 bit Weight for RX_HPS_CMDQ #3 (15:12) + */ +struct ipahal_reg_rx_hps_weights { + u32 hps_queue_weight_0; + u32 hps_queue_weight_1; + u32 hps_queue_weight_2; + u32 hps_queue_weight_3; +}; + +/* + * struct ipahal_reg_counter_cfg - granularity of counter registers + * @aggr_granularity -Defines the granularity of AGGR timers + * granularity [msec]=(x+1)/(32) + */ +struct ipahal_reg_counter_cfg { + enum { + GRAN_VALUE_125_USEC = 3, + GRAN_VALUE_250_USEC = 7, + GRAN_VALUE_500_USEC = 15, + GRAN_VALUE_MSEC = 31, + } aggr_granularity; +}; + + +/* + * struct ipahal_reg_valmask - holding values and masking for registers + * HAL application may require only value and mask of it for some + * register fields. + * @val - The value + * @mask - Tha mask of the value + */ +struct ipahal_reg_valmask { + u32 val; + u32 mask; +}; + +/* + * struct ipahal_reg_fltrt_hash_flush - Flt/Rt flush configuration + * @v6_rt - Flush IPv6 Routing cache + * @v6_flt - Flush IPv6 Filtering cache + * @v4_rt - Flush IPv4 Routing cache + * @v4_flt - Flush IPv4 Filtering cache + */ +struct ipahal_reg_fltrt_hash_flush { + bool v6_rt; + bool v6_flt; + bool v4_rt; + bool v4_flt; +}; + +/* +* struct ipahal_reg_fltrt_cache_flush - Flt/Rt flush configuration +* @rt - Flush Routing cache +* @flt - Flush Filtering cache +*/ +struct ipahal_reg_fltrt_cache_flush { + bool rt; + bool flt; +}; + +/* + * struct ipahal_reg_single_ndp_mode - IPA SINGLE_NDP_MODE register + * @single_ndp_en: When set to '1', IPA builds MBIM frames with up to 1 + * NDP-header. + * @unused: undefined bits of the register + */ +struct ipahal_reg_single_ndp_mode { + bool single_ndp_en; + u32 undefined; +}; + +/* + * struct ipahal_reg_qcncm - IPA QCNCM register + * @mode_en: When QCNCM_MODE_EN=1, IPA will use QCNCM signature. + * @mode_val: Used only when QCNCM_MODE_EN=1 and sets SW Signature in + * the NDP header. + * @unused: undefined bits of the register + */ +struct ipahal_reg_qcncm { + bool mode_en; + u32 mode_val; + u32 undefined; +}; + +/* + * struct ipahal_reg_qsb_max_writes - IPA QSB Max Writes register + * @qmb_0_max_writes: Max number of outstanding writes for GEN_QMB_0 + * @qmb_1_max_writes: Max number of outstanding writes for GEN_QMB_1 + */ +struct ipahal_reg_qsb_max_writes { + u32 qmb_0_max_writes; + u32 qmb_1_max_writes; +}; + +/* + * struct ipahal_reg_qsb_max_reads - IPA QSB Max Reads register + * @qmb_0_max_reads: Max number of outstanding reads for GEN_QMB_0 + * @qmb_1_max_reads: Max number of outstanding reads for GEN_QMB_1 + * @qmb_0_max_read_beats: Max number of outstanding read beats for GEN_QMB_0 + * @qmb_1_max_read_beats: Max number of outstanding read beats for GEN_QMB_1 + */ +struct ipahal_reg_qsb_max_reads { + u32 qmb_0_max_reads; + u32 qmb_1_max_reads; + u32 qmb_0_max_read_beats; + u32 qmb_1_max_read_beats; +}; + +/* + * struct ipahal_reg_tx_cfg - IPA TX_CFG register + * @tx0_prefetch_disable: Disable prefetch on TX0 + * @tx1_prefetch_disable: Disable prefetch on TX1 + * @tx0_prefetch_almost_empty_size: Prefetch almost empty size on TX0 + * @tx1_prefetch_almost_empty_size: Prefetch almost empty size on TX1 + * @dmaw_scnd_outsd_pred_threshold: threshold for DMAW_SCND_OUTSD_PRED_EN + * @dmaw_max_beats_256_dis: + * @dmaw_scnd_outsd_pred_en: + * @pa_mask_en: + * @dual_tx_enable: When 1 TX0 and TX1 are enabled. When 0 only TX0 is enabled + * @sspnd_pa_no_start_state: When 1 sspnd_req does not take inco account + PA FSM state START. + When 0 sspnd_req_ will not be answered + on that state. + * Relevant starting IPA4.5 + */ +struct ipahal_reg_tx_cfg { + bool tx0_prefetch_disable; + bool tx1_prefetch_disable; + u32 tx0_prefetch_almost_empty_size; + u32 tx1_prefetch_almost_empty_size; + u32 dmaw_scnd_outsd_pred_threshold; + u32 dmaw_max_beats_256_dis; + u32 dmaw_scnd_outsd_pred_en; + u32 pa_mask_en; + bool dual_tx_enable; + bool sspnd_pa_no_start_state; + bool holb_sticky_drop_en; +}; + +/* + * struct ipahal_reg_idle_indication_cfg - IPA IDLE_INDICATION_CFG register + * @const_non_idle_enable: enable the asserting of the IDLE value and DCD + * @enter_idle_debounce_thresh: configure the debounce threshold + */ +struct ipahal_reg_idle_indication_cfg { + u16 enter_idle_debounce_thresh; + bool const_non_idle_enable; +}; + +/* + * struct ipa_ep_cfg_ctrl_scnd - IPA_ENDP_INIT_CTRL_SCND_n register + * @endp_delay: delay endpoint + */ +struct ipahal_ep_cfg_ctrl_scnd { + bool endp_delay; +}; + +/* + * struct ipahal_reg_state_coal_master- IPA_STATE_COAL_MASTER register + * @vp_timer_expired: VP bitmap. If set, Vp aggregation timer has expired + * @lru_cp: least recently used VP index + * @init_vp_fsm_state: init VP FSM current state + * @check_fir_fsm_state: check fir FMS current state + * @hash_calc_fsm_state: hash calculation FSM current state + * @find_open_fsm_state: find open VP FSM current state + * @main_fsm_state: main coalescing master state FSM current state + * @vp_vld: VP bitmap. If set, VP is valid, and coalescing frame is open. + */ +struct ipahal_reg_state_coal_master { + u32 vp_timer_expired; + u32 lru_vp; + u32 init_vp_fsm_state; + u32 check_fir_fsm_state; + u32 hash_calc_fsm_state; + u32 find_open_fsm_state; + u32 main_fsm_state; + u32 vp_vld; +}; + +/* + * struct ipahal_reg_coal_evict_lru - IPA_COAL_EVICT_LRU register + * @coal_vp_lru_thrshld: Connection that is opened below this val + * will not get evicted. valid till v5_2. + * @coal_eviction_en: Enable eviction + * @coal_vp_lru_gran_sel: select the appropiate granularity out of 4 options + * Valid from v5_5. + * @coal_vp_lru_udp_thrshld: Coalescing eviction threshold. LRU VP + * stickness/inactivity defined by this threshold fot UDP connectiom. + * 0 mean all UDP's non sticky. Valid from v5_5. + * @coal_vp_lru_tcp_thrshld: Coalescing eviction threshold. LRU VP + * stickness/inactivity defined by this threshold fot TCP connection. + * 0 mean all TCP's non sticky. Valid from v5_5. + * @coal_vp_lru_udp_thrshld_en: Coalescing eviction enable for UDP connections + * when UDP pacjet arrived. 0-disable these evictions. Valid from v5_5. + * @coal_vp_lru_tcp_thrshld_en: Coalescing eviction enable for TCP connections + * when TCP pacjet arrived. 0-disable these evictions. Valid from v5_5. + * @coal_vp_lru_tcp_num: configured TCP NUM value , SW define when TCP/UDP will + * treat as exceed during eviction process. Valid from v5_5. + */ +struct ipahal_reg_coal_evict_lru { + u32 coal_vp_lru_thrshld; + bool coal_eviction_en; + u8 coal_vp_lru_gran_sel; + u8 coal_vp_lru_udp_thrshld; + u8 coal_vp_lru_tcp_thrshld; + bool coal_vp_lru_udp_thrshld_en; + bool coal_vp_lru_tcp_thrshld_en; + bool coal_vp_lru_tcp_num; +}; + +/* + * struct ipahal_reg_coal_qmap_cfg - IPA_COAL_QMAP_CFG register + * @mux_id_byte_sel: MUX_ID field in the QMAP portion in COALESCING header is + * taken from injected packet metadata field in PKT_CTX. + * Metadata consists of 4 bytes, configuring value 0 to MUX_ID_BYTE_SEL will + * take bits 7:0 from metadata field, value 1 will take bits 15:8 and so on ... + */ +struct ipahal_reg_coal_qmap_cfg { + u32 mux_id_byte_sel; +}; + +/* + * struct ipahal_reg_coal_master_cfg - IPA_COAL_MASTER_CFG register + * @coal_ipv4_id_ignore: 1 - global ignore IPV4 ID checks regardles DF, + * val 0 -keep checks according to DF/MF conditions. + * @coal_enhanced_ipv4_id_en: 1 - if (DF == 1 && MF == 0 && frag_offset == 0) + * Coalescingwill ignore IPv4 identification field, else legacy behaviour + * is used. + * 0 - Coalescing will use original legacy IPv4 identification field check. + * @coal_force_to_default: 1 - force any new packet that arrives to coal master + * to default pipe, and close any open frames with the same tuple + * 0 - regular coalescing activity. + */ +struct ipahal_reg_coal_master_cfg { + bool coal_ipv4_id_ignore; + bool coal_enhanced_ipv4_id_en; + bool coal_force_to_default; +}; + +/* + * struct ipahal_ipa_flavor_0 - IPA_FLAVOR_0 register + * @ipa_pipes: Number of supported pipes + * @ipa_cons_pipes: Number of consumer pipes + * @ipa_prod_pipes: Number of producer pipes + * @ipa_prod_lowest: Number of first producer pipe + */ +struct ipahal_ipa_flavor_0 { + u8 ipa_pipes; + u8 ipa_cons_pipes; + u8 ipa_prod_pipes; + u8 ipa_prod_lowest; +}; + +/* + * struct ipahal_ipa_flavor_9 - IPA_FLAVOR_9 register + * @ipa_tsp_max_ingr_tc: Maximal number of ingress (consumer-based) traffic-classes. + * Does not include invalid traffic-class 0x00. + * @ipa_tsp_max_egr_tc: Maximal number of egress (producer-based) traffic-classes. + * Does not include invalid traffic-class 0x00. + * @ipa_tsp_max_prod: Maximal number of TSP-enabled producers. + * @reserved: Reserved + */ +struct ipahal_ipa_flavor_9 { + u8 ipa_tsp_max_ingr_tc; + u8 ipa_tsp_max_egr_tc; + u8 ipa_tsp_max_prod; + u8 reserved; +}; + +/* + * struct ipahal_ipa_state_tsp - TSP engine state register + * @traffic_shaper_idle: Traffic-Shaper module IDLE indication + * @traffic_shaper_fifo_empty: Traffic-Shaper FIFO empty indication + * @queue_mngr_idle: QMNGR overall IDLE indication + * @queue_mngr_head_idle: QMNGR head module IDLE indication + * @queue_mngr_shared_idle: QMNGR shared module IDLE indication + * @queue_mngr_tail_idle: QMNGR tail module IDLE indication + * @queue_mngr_block_ctrl_idle: Block control module IDLE indication + */ +struct ipahal_ipa_state_tsp { + bool traffic_shaper_idle; + bool traffic_shaper_fifo_empty; + bool queue_mngr_idle; + bool queue_mngr_head_idle; + bool queue_mngr_shared_idle; + bool queue_mngr_tail_idle; + bool queue_mngr_block_ctrl_idle; +}; + +/* + * struct ipahal_reg_nat_uc_local_cfg - IPA_NAT_UC_EXTERNAL_CFG register + * @nat_uc_external_table_addr_lsb: 32 LSb bits of system-memory address of + * external UC-activation entry table. + */ +struct ipahal_reg_nat_uc_external_cfg { + u32 nat_uc_external_table_addr_lsb; +}; + +/* + * struct ipahal_reg_nat_uc_local_cfg - IPA_NAT_UC_LOCAL_CFG register + * @nat_uc_local_table_addr_lsb: 32 LSb bits of local address of local + * UC-activation entry table. Address is memory-map based, + * i.e. includes IPA address from chip level. + */ +struct ipahal_reg_nat_uc_local_cfg { + u32 nat_uc_local_table_addr_lsb; +}; + +/* + * struct ipahal_reg_nat_uc_shared_cfg - IPA_NAT_UC_SHARED_CFG register + * @nat_uc_external_table_addr_msb: 16 MSb of external UC-ativation entry table. + * @nat_uc_local_table_addr_msb: 16 MSb bits of local UC-ativation entry table. + */ +struct ipahal_reg_nat_uc_shared_cfg { + u32 nat_uc_local_table_addr_msb; + u32 nat_uc_external_table_addr_msb; +}; + +/* + * struct ipahal_reg_conn_track_uc_local_cfg - IPA_conn_track_UC_EXTERNAL_CFG + * register + * @conn_track_uc_external_table_addr_lsb: 32 LSb bits of system-memory address + * of external UC-activation entry table. + */ +struct ipahal_reg_conn_track_uc_external_cfg { + u32 conn_track_uc_external_table_addr_lsb; +}; + +/* + * struct ipahal_reg_conn_track_uc_local_cfg - IPA_conn_track_UC_LOCAL_CFG + * register + * @conn_track_uc_local_table_addr_lsb: 32 LSb bits of local address of local + * UC-activation entry table. Address is memory-map based, + * i.e. includes IPA address from chip level. + */ +struct ipahal_reg_conn_track_uc_local_cfg { + u32 conn_track_uc_local_table_addr_lsb; +}; + +/* + * struct ipahal_reg_conn_track_uc_shared_cfg - IPA_conn_track_UC_SHARED_CFG + * register + * @conn_track_uc_external_table_addr_msb: 16 MSb of external UC-ativation + * entry table. + * @conn_track_uc_local_table_addr_msb: 16 MSb bits of local UC-ativation + * entry table. + */ +struct ipahal_reg_conn_track_uc_shared_cfg { + u16 conn_track_uc_local_table_addr_msb; + u16 conn_track_uc_external_table_addr_msb; +}; + +/* + * ipahal_print_all_regs() - Loop and read and print all the valid registers + * Parameterized registers are also printed for all the valid ranges. + * Print to dmsg and IPC logs + */ +void ipahal_print_all_regs(bool print_to_dmesg); + +/* + * ipahal_reg_name_str() - returns string that represent the register + * @reg_name: [in] register name + */ +const char *ipahal_reg_name_str(enum ipahal_reg_name reg_name); + +/* + * ipahal_read_reg_n() - Get the raw value of n parameterized reg + */ +u32 ipahal_read_reg_n(enum ipahal_reg_name reg, u32 n); + +/* + * ipahal_read_reg_mn() - Get mn parameterized reg value + */ +u32 ipahal_read_reg_mn(enum ipahal_reg_name reg, u32 m, u32 n); + +/* +* ipahal_read_reg_nk() - Read from n/k parameterized reg +*/ +static inline u32 ipahal_read_reg_nk(enum ipahal_reg_name reg, u32 n, u32 k) +{ + return ipahal_read_reg_mn(reg, k, n); +} + +/* +* ipahal_read_ep_reg_n() - Get n parameterized reg value according to ep +*/ +u32 ipahal_read_ep_reg_n(enum ipahal_reg_name reg, u32 n, u32 ep_num); + +/* + * ipahal_write_reg_mn() - Write to m/n parameterized reg a raw value + */ +void ipahal_write_reg_mn(enum ipahal_reg_name reg, u32 m, u32 n, u32 val); + +/* +* ipahal_write_reg_nk() - Write to n/k parameterized reg a raw value +*/ +static inline void ipahal_write_reg_nk( + enum ipahal_reg_name reg, u32 n, u32 k, u32 val) +{ + ipahal_write_reg_mn(reg, k, n, val); +} + +/* + * ipahal_write_reg_n() - Write to n parameterized reg a raw value + */ +static inline void ipahal_write_reg_n(enum ipahal_reg_name reg, + u32 n, u32 val) +{ + ipahal_write_reg_mn(reg, 0, n, val); +} + +/* + * ipahal_read_reg_n_fields() - Get the parsed value of n parameterized reg + */ +u32 ipahal_read_reg_n_fields(enum ipahal_reg_name reg, u32 n, void *fields); + +/* + * ipahal_write_reg_n_fields() - Write to n parameterized reg a prased value + */ +void ipahal_write_reg_n_fields(enum ipahal_reg_name reg, u32 n, + const void *fields); + +/* + * ipahal_read_reg() - Get the raw value of a reg + */ +static inline u32 ipahal_read_reg(enum ipahal_reg_name reg) +{ + return ipahal_read_reg_n(reg, 0); +} + +/* + * ipahal_read_ep_reg() - Get the raw value of a ep reg + */ +u32 ipahal_read_ep_reg(enum ipahal_reg_name reg, u32 ep_num); + +/* + * ipahal_write_reg() - Write to reg a raw value + */ +static inline void ipahal_write_reg(enum ipahal_reg_name reg, + u32 val) +{ + ipahal_write_reg_mn(reg, 0, 0, val); +} + +/* + * ipahal_write_reg_mask() - Overwrite a masked raw value in reg + */ +static inline void ipahal_write_reg_mask(enum ipahal_reg_name reg, u32 val, u32 mask) +{ + u32 new_val = ipahal_read_reg(reg); + new_val &= !mask; + new_val &= (val & mask); + ipahal_write_reg(reg, val); +} + +/* + * ipahal_read_reg_fields() - Get the parsed value of a reg + */ +static inline u32 ipahal_read_reg_fields(enum ipahal_reg_name reg, void *fields) +{ + return ipahal_read_reg_n_fields(reg, 0, fields); +} + +/* + * ipahal_write_reg_fields() - Write to reg a parsed value + */ +static inline void ipahal_write_reg_fields(enum ipahal_reg_name reg, + const void *fields) +{ + ipahal_write_reg_n_fields(reg, 0, fields); +} + +/* + * ipahal_write_ep_reg() - Write to ep reg a raw value + */ +void ipahal_write_ep_reg(enum ipahal_reg_name reg, u32 ep_num, u32 val); + +/* + * ipahal_write_ep_reg_n() - Write to ep reg a raw value + */ +void ipahal_write_ep_reg_n(enum ipahal_reg_name reg, u32 n, u32 ep_num, u32 val); + +/* + * Get the offset of a m/n parameterized register + */ +u32 ipahal_get_reg_mn_ofst(enum ipahal_reg_name reg, u32 m, u32 n); + +/* +* Get the offset of a n,k register +*/ +u32 ipahal_get_reg_nk_offset(enum ipahal_reg_name reg, u32 n, u32 l); + +/* + * Get the offset of a n parameterized register + */ +static inline u32 ipahal_get_reg_n_ofst(enum ipahal_reg_name reg, u32 n) +{ + return ipahal_get_reg_mn_ofst(reg, 0, n); +} + +/* + * Get the offset of a ep register according to ep index + */ +u32 ipahal_get_ep_reg_offset(enum ipahal_reg_name reg, u32 ep_num); + +/* + * Get the offset of a register + */ +static inline u32 ipahal_get_reg_ofst(enum ipahal_reg_name reg) +{ + return ipahal_get_reg_mn_ofst(reg, 0, 0); +} + +/* + * Get the register base address + */ +u32 ipahal_get_reg_base(void); + +/* + * Specific functions + * These functions supply specific register values for specific operations + * that cannot be reached by generic functions. + * E.g. To disable aggregation, need to write to specific bits of the AGGR + * register. The other bits should be untouched. This operation is very + * specific and cannot be generically defined. For such operations we define + * these specific functions. + */ +u32 ipahal_aggr_get_max_byte_limit(void); +u32 ipahal_aggr_get_max_pkt_limit(void); +void ipahal_get_aggr_force_close_valmask(int ep_idx, + struct ipahal_reg_valmask *valmask); +void ipahal_get_fltrt_hash_flush_valmask( + struct ipahal_reg_fltrt_hash_flush *flush, + struct ipahal_reg_valmask *valmask); + +void ipahal_get_fltrt_cache_flush_valmask( + struct ipahal_reg_fltrt_cache_flush *flush, + struct ipahal_reg_valmask *valmask); + +#endif /* _IPAHAL_REG_H_ */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg_i.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg_i.h new file mode 100644 index 0000000000..9df13aff86 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg_i.h @@ -0,0 +1,914 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _IPAHAL_REG_I_H_ +#define _IPAHAL_REG_I_H_ + +int ipahal_reg_init(enum ipa_hw_type ipa_hw_type); + +#define IPA_SETFIELD(val, shift, mask) (((val) << (shift)) & (mask)) +#define IPA_SETFIELD_IN_REG(reg, val, shift, mask) \ + (reg |= ((val) << (shift)) & (mask)) +#define IPA_GETFIELD_FROM_REG(reg, shift, mask) \ + (((reg) & (mask)) >> (shift)) + +/* IPA_ROUTE register */ +#define IPA_ROUTE_ROUTE_DEF_PIPE_SHFT_v5_0 0 +#define IPA_ROUTE_ROUTE_DEF_PIPE_BMSK_v5_0 0xFF +#define IPA_ROUTE_ROUTE_FRAG_DEF_PIPE_SHFT_v5_0 8 +#define IPA_ROUTE_ROUTE_FRAG_DEF_PIPE_BMSK_v5_0 0xFF00 +#define IPA_ROUTE_ROUTE_DEF_HDR_OFST_SHFT_v5_0 16 +#define IPA_ROUTE_ROUTE_DEF_HDR_OFST_BMSK_v5_0 0x3ff00 +#define IPA_ROUTE_ROUTE_DEF_HDR_TABLE_SHFT_v5_0 26 +#define IPA_ROUTE_ROUTE_DEF_HDR_TABLE_BMSK_v5_0 0X4000000 +#define IPA_ROUTE_ROUTE_DEF_RETAIN_HDR_SHFT_v5_0 27 +#define IPA_ROUTE_ROUTE_DEF_RETAIN_HDR_BMSK_v5_0 0x8000000 +#define IPA_ROUTE_ROUTE_DIS_SHFT_v5_0 28 +#define IPA_ROUTE_ROUTE_DIS_BMSK_v5_0 0x10000000 + +#define IPA_ROUTE_ROUTE_DIS_SHFT 0x0 +#define IPA_ROUTE_ROUTE_DIS_BMSK 0x1 +#define IPA_ROUTE_ROUTE_DEF_PIPE_SHFT 0x1 +#define IPA_ROUTE_ROUTE_DEF_PIPE_BMSK 0x3e +#define IPA_ROUTE_ROUTE_DEF_HDR_TABLE_SHFT 0x6 +#define IPA_ROUTE_ROUTE_DEF_HDR_TABLE_BMSK 0X40 +#define IPA_ROUTE_ROUTE_DEF_HDR_OFST_SHFT 0x7 +#define IPA_ROUTE_ROUTE_DEF_HDR_OFST_BMSK 0x1ff80 +#define IPA_ROUTE_ROUTE_FRAG_DEF_PIPE_BMSK 0x3e0000 +#define IPA_ROUTE_ROUTE_FRAG_DEF_PIPE_SHFT 0x11 +#define IPA_ROUTE_ROUTE_DEF_RETAIN_HDR_BMSK 0x1000000 +#define IPA_ROUTE_ROUTE_DEF_RETAIN_HDR_SHFT 0x18 + +/* IPA_ENDP_INIT_HDR_n register */ +#define IPA_ENDP_INIT_HDR_n_HDR_LEN_BMSK 0x3f +#define IPA_ENDP_INIT_HDR_n_HDR_LEN_SHFT 0x0 +#define IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_VALID_BMSK 0x40 +#define IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_VALID_SHFT 0x6 +#define IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_SHFT 0x7 +#define IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_BMSK 0x1f80 +#define IPA_ENDP_INIT_HDR_n_HDR_ADDITIONAL_CONST_LEN_BMSK 0x7e000 +#define IPA_ENDP_INIT_HDR_n_HDR_ADDITIONAL_CONST_LEN_SHFT 0xd +#define IPA_ENDP_INIT_HDR_n_HDR_OFST_PKT_SIZE_VALID_BMSK 0x80000 +#define IPA_ENDP_INIT_HDR_n_HDR_OFST_PKT_SIZE_VALID_SHFT 0x13 +#define IPA_ENDP_INIT_HDR_n_HDR_OFST_PKT_SIZE_BMSK 0x3f00000 +#define IPA_ENDP_INIT_HDR_n_HDR_OFST_PKT_SIZE_SHFT 0x14 +#define IPA_ENDP_INIT_HDR_n_HDR_A5_MUX_BMSK 0x4000000 +#define IPA_ENDP_INIT_HDR_n_HDR_A5_MUX_SHFT 0x1a +#define IPA_ENDP_INIT_HDR_n_HDR_LEN_INC_DEAGG_HDR_BMSK 0x8000000 +#define IPA_ENDP_INIT_HDR_n_HDR_LEN_INC_DEAGG_HDR_SHFT 0x1b +#define IPA_ENDP_INIT_HDR_n_HDR_METADATA_REG_VALID_BMSK 0x10000000 +#define IPA_ENDP_INIT_HDR_n_HDR_METADATA_REG_VALID_SHFT 0x1c + +#define IPA_ENDP_INIT_HDR_n_HDR_LEN_BMSK_v4_5 0x3f +#define IPA_ENDP_INIT_HDR_n_HDR_LEN_SHFT_v4_5 0x0 +#define IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_VALID_BMSK_v4_5 0x40 +#define IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_VALID_SHFT_v4_5 0x6 +#define IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_SHFT_v4_5 0x7 +#define IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_BMSK_v4_5 0x1f80 +#define IPA_ENDP_INIT_HDR_n_HDR_ADDITIONAL_CONST_LEN_BMSK_v4_5 0x7e000 +#define IPA_ENDP_INIT_HDR_n_HDR_ADDITIONAL_CONST_LEN_SHFT_v4_5 0xd +#define IPA_ENDP_INIT_HDR_n_HDR_OFST_PKT_SIZE_VALID_BMSK_v4_5 0x80000 +#define IPA_ENDP_INIT_HDR_n_HDR_OFST_PKT_SIZE_VALID_SHFT_v4_5 0x13 +#define IPA_ENDP_INIT_HDR_n_HDR_OFST_PKT_SIZE_BMSK_v4_5 0x3f00000 +#define IPA_ENDP_INIT_HDR_n_HDR_OFST_PKT_SIZE_SHFT_v4_5 0x14 +#define IPA_ENDP_INIT_HDR_n_HDR_A5_MUX_BMSK_v4_5 0x4000000 +#define IPA_ENDP_INIT_HDR_n_HDR_A5_MUX_SHFT_v4_5 0x1a +#define IPA_ENDP_INIT_HDR_n_HDR_LEN_INC_DEAGG_HDR_BMSK_v4_5 0x8000000 +#define IPA_ENDP_INIT_HDR_n_HDR_LEN_INC_DEAGG_HDR_SHFT_v4_5 0x1b +#define IPA_ENDP_INIT_HDR_n_HDR_LEN_MSB_BMSK_v4_5 0x30000000 +#define IPA_ENDP_INIT_HDR_n_HDR_LEN_MSB_SHFT_v4_5 0x1c +#define IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_MSB_BMSK_v4_5 0xc0000000 +#define IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_MSB_SHFT_v4_5 0x1e + +/* IPA_ENDP_INIT_HDR_EXT_n register */ +#define IPA_ENDP_INIT_HDR_EXT_n_HDR_ENDIANNESS_BMSK 0x1 +#define IPA_ENDP_INIT_HDR_EXT_n_HDR_ENDIANNESS_SHFT 0x0 +#define IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_VALID_BMSK 0x2 +#define IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_VALID_SHFT 0x1 +#define IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_BMSK 0x4 +#define IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_SHFT 0x2 +#define IPA_ENDP_INIT_HDR_EXT_n_HDR_PAYLOAD_LEN_INC_PADDING_BMSK 0x8 +#define IPA_ENDP_INIT_HDR_EXT_n_HDR_PAYLOAD_LEN_INC_PADDING_SHFT 0x3 +#define IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_OFFSET_BMSK 0x3f0 +#define IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_OFFSET_SHFT 0x4 +#define IPA_ENDP_INIT_HDR_EXT_n_HDR_PAD_TO_ALIGNMENT_SHFT 0xa +#define IPA_ENDP_INIT_HDR_EXT_n_HDR_PAD_TO_ALIGNMENT_BMSK 0x3c00 +#define IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB_SHFT_v4_5 0x10 +#define IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB_BMSK_v4_5 \ + 0x30000 +#define IPA_ENDP_INIT_HDR_EXT_n_HDR_OFST_PKT_SIZE_MSB_SHFT_v4_5 0x12 +#define IPA_ENDP_INIT_HDR_EXT_n_HDR_OFST_PKT_SIZE_MSB_BMSK_v4_5 0xC0000 +#define IPA_ENDP_INIT_HDR_EXT_n_HDR_ADDITIONAL_CONST_LEN_MSB_SHFT_v4_5 0x14 +#define IPA_ENDP_INIT_HDR_EXT_n_HDR_ADDITIONAL_CONST_LEN_MSB_BMSK_v4_5 0x300000 + +#define IPA_ENDP_INIT_HDR_EXT_n_HDR_BYTES_TO_REMOVE_VALID_SHFT_v5_0 0x16 +#define IPA_ENDP_INIT_HDR_EXT_n_HDR_BYTES_TO_REMOVE_VALID_BMSK_v5_0 0x400000 +#define IPA_ENDP_INIT_HDR_EXT_n_HDR_BYTES_TO_REMOVE_SHFT_v5_0 0x18 +#define IPA_ENDP_INIT_HDR_EXT_n_HDR_BYTES_TO_REMOVE_BMSK_v5_0 0xFF000000 + +/* IPA_ENDP_INIT_AGGR_n register */ +#define IPA_ENDP_INIT_AGGR_n_AGGR_HARD_BYTE_LIMIT_ENABLE_BMSK 0x1000000 +#define IPA_ENDP_INIT_AGGR_n_AGGR_HARD_BYTE_LIMIT_ENABLE_SHFT 0x18 +#define IPA_ENDP_INIT_AGGR_n_AGGR_FORCE_CLOSE_BMSK 0x400000 +#define IPA_ENDP_INIT_AGGR_n_AGGR_FORCE_CLOSE_SHFT 0x16 +#define IPA_ENDP_INIT_AGGR_n_AGGR_SW_EOF_ACTIVE_BMSK 0x200000 +#define IPA_ENDP_INIT_AGGR_n_AGGR_SW_EOF_ACTIVE_SHFT 0x15 +#define IPA_ENDP_INIT_AGGR_n_AGGR_PKT_LIMIT_BMSK 0x1f8000 +#define IPA_ENDP_INIT_AGGR_n_AGGR_PKT_LIMIT_SHFT 0xf +#define IPA_ENDP_INIT_AGGR_n_AGGR_TIME_LIMIT_BMSK 0x7c00 +#define IPA_ENDP_INIT_AGGR_n_AGGR_TIME_LIMIT_SHFT 0xa +#define IPA_ENDP_INIT_AGGR_n_AGGR_BYTE_LIMIT_BMSK 0x3e0 +#define IPA_ENDP_INIT_AGGR_n_AGGR_BYTE_LIMIT_SHFT 0x5 +#define IPA_ENDP_INIT_AGGR_n_AGGR_TYPE_BMSK 0x1c +#define IPA_ENDP_INIT_AGGR_n_AGGR_TYPE_SHFT 0x2 +#define IPA_ENDP_INIT_AGGR_n_AGGR_EN_BMSK 0x3 +#define IPA_ENDP_INIT_AGGR_n_AGGR_EN_SHFT 0x0 + +#define IPA_ENDP_INIT_AGGR_n_AGGR_COAL_L2_BMSK_V5_5 0x10000000 +#define IPA_ENDP_INIT_AGGR_n_AGGR_COAL_L2_SHFT_V5_5 28 +#define IPA_ENDP_INIT_AGGR_n_AGGR_GRAN_SEL_BMSK_V4_5 0x8000000 +#define IPA_ENDP_INIT_AGGR_n_AGGR_GRAN_SEL_SHFT_V4_5 27 +#define IPA_ENDP_INIT_AGGR_n_AGGR_HARD_BYTE_LIMIT_ENABLE_BMSK_V4_5 0x4000000 +#define IPA_ENDP_INIT_AGGR_n_AGGR_HARD_BYTE_LIMIT_ENABLE_SHFT_V4_5 26 +#define IPA_ENDP_INIT_AGGR_n_AGGR_FORCE_CLOSE_BMSK_V4_5 0x1000000 +#define IPA_ENDP_INIT_AGGR_n_AGGR_FORCE_CLOSE_SHFT_V4_5 24 +#define IPA_ENDP_INIT_AGGR_n_AGGR_SW_EOF_ACTIVE_BMSK_V4_5 0x800000 +#define IPA_ENDP_INIT_AGGR_n_AGGR_SW_EOF_ACTIVE_SHFT_V4_5 23 +#define IPA_ENDP_INIT_AGGR_n_AGGR_PKT_LIMIT_BMSK_V4_5 0x7e0000 +#define IPA_ENDP_INIT_AGGR_n_AGGR_PKT_LIMIT_SHFT_V4_5 17 +#define IPA_ENDP_INIT_AGGR_n_AGGR_TIME_LIMIT_BMSK_V4_5 0x1f000 +#define IPA_ENDP_INIT_AGGR_n_AGGR_TIME_LIMIT_SHFT_V4_5 12 +#define IPA_ENDP_INIT_AGGR_n_AGGR_BYTE_LIMIT_BMSK_V4_5 0x7e0 +#define IPA_ENDP_INIT_AGGR_n_AGGR_BYTE_LIMIT_SHFT_V4_5 5 +#define IPA_ENDP_INIT_AGGR_n_AGGR_TYPE_BMSK_V4_5 0x1c +#define IPA_ENDP_INIT_AGGR_n_AGGR_TYPE_SHFT_V4_5 2 +#define IPA_ENDP_INIT_AGGR_n_AGGR_EN_BMSK_V4_5 0x3 +#define IPA_ENDP_INIT_AGGR_n_AGGR_EN_SHFT_V4_5 0 + +/* IPA_AGGR_FORCE_CLOSE register */ +#define IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_BMSK 0x3fffffff +#define IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_SHFT 0 +#define IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_BMSK_V3_5 0xfffff +#define IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_SHFT_V3_5 0 +#define IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_BMSK_V4_0 0x7fffff +#define IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_SHFT_V4_0 0 +#define IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_BMSK_V4_2 0x1ffff +#define IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_SHFT_V4_2 0 +#define IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_BMSK_V4_5 0x7fffffff +#define IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_SHFT_V4_5 0 +#define IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_BMSK_V4_9 0x7fffff +#define IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_SHFT_V4_9 0 +#define IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_BMSK_v5_0 0xffffffff +#define IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_BMSK_2_v5_0 0xf +#define IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_SHFT_V5_0 0 + +/* IPA_ENDP_INIT_ROUTE_n register */ +#define IPA_ENDP_INIT_ROUTE_n_ROUTE_TABLE_INDEX_BMSK 0x1f +#define IPA_ENDP_INIT_ROUTE_n_ROUTE_TABLE_INDEX_SHFT 0x0 + +/* IPA_ENDP_INIT_MODE_n register */ +#define IPA_ENDP_INIT_MODE_n_HDR_FTCH_DISABLE_BMSK 0x40000000 +#define IPA_ENDP_INIT_MODE_n_HDR_FTCH_DISABLE_SHFT 0x1e +#define IPA_ENDP_INIT_MODE_n_PAD_EN_BMSK 0x20000000 +#define IPA_ENDP_INIT_MODE_n_PAD_EN_SHFT 0x1d +#define IPA_ENDP_INIT_MODE_n_PIPE_REPLICATION_EN_BMSK 0x10000000 +#define IPA_ENDP_INIT_MODE_n_PIPE_REPLICATION_EN_SHFT 0x1c +#define IPA_ENDP_INIT_MODE_n_BYTE_THRESHOLD_BMSK 0xffff000 +#define IPA_ENDP_INIT_MODE_n_BYTE_THRESHOLD_SHFT 0xc +#define IPA_ENDP_INIT_MODE_n_DEST_PIPE_INDEX_BMSK 0x1f0 +#define IPA_ENDP_INIT_MODE_n_DEST_PIPE_INDEX_SHFT 0x4 +#define IPA_ENDP_INIT_MODE_n_MODE_BMSK 0x7 +#define IPA_ENDP_INIT_MODE_n_MODE_SHFT 0x0 + +#define IPA_ENDP_INIT_MODE_n_PAD_EN_BMSK_V4_5 0x20000000 +#define IPA_ENDP_INIT_MODE_n_PAD_EN_SHFT_V4_5 0x1d +#define IPA_ENDP_INIT_MODE_n_PIPE_REPLICATION_EN_BMSK_V4_5 0x10000000 +#define IPA_ENDP_INIT_MODE_n_PIPE_REPLICATION_EN_SHFT_V4_5 0x1c +#define IPA_ENDP_INIT_MODE_n_BYTE_THRESHOLD_BMSK_V4_5 0xffff000 +#define IPA_ENDP_INIT_MODE_n_BYTE_THRESHOLD_SHFT_V4_5 0xc +#define IPA_ENDP_INIT_MODE_n_DEST_PIPE_INDEX_BMSK_V4_5 0x1f0 +#define IPA_ENDP_INIT_MODE_n_DEST_PIPE_INDEX_SHFT_V4_5 0x4 +#define IPA_ENDP_INIT_MODE_n_DCPH_ENABLE_BMSK_V4_5 0x8 +#define IPA_ENDP_INIT_MODE_n_DCPH_ENABLE_SHFT_V4_5 0x3 +#define IPA_ENDP_INIT_MODE_n_MODE_BMSK_V4_5 0x7 +#define IPA_ENDP_INIT_MODE_n_MODE_SHFT_V4_5 0x0 + +#define IPA_ENDP_INIT_MODE_n_DEST_PIPE_INDEX_BMSK_V5_0 0xff0 +#define IPA_ENDP_INIT_MODE_n_DEST_PIPE_INDEX_SHFT_V5_0 0x4 + +/* IPA_ENDP_INIT_NAT_n register */ +#define IPA_ENDP_INIT_NAT_n_NAT_EN_BMSK 0x3 +#define IPA_ENDP_INIT_NAT_n_NAT_EN_SHFT 0x0 + +/* IPA_ENDP_INIT_CONN_TRACK_n register */ +#define IPA_ENDP_INIT_CONN_TRACK_n_CONN_TRACK_EN_BMSK 0x1 +#define IPA_ENDP_INIT_CONN_TRACK_n_CONN_TRACK_EN_SHFT 0x0 + +/* IPA_ENDP_INIT_CTRL_n register */ +#define IPA_ENDP_INIT_CTRL_n_ENDP_SUSPEND_BMSK 0x1 +#define IPA_ENDP_INIT_CTRL_n_ENDP_SUSPEND_SHFT 0x0 +#define IPA_ENDP_INIT_CTRL_n_ENDP_DELAY_BMSK 0x2 +#define IPA_ENDP_INIT_CTRL_n_ENDP_DELAY_SHFT 0x1 + +/* IPA_ENDP_INIT_CTRL_SCND_n register */ +#define IPA_ENDP_INIT_CTRL_SCND_n_ENDP_DELAY_BMSK 0x2 +#define IPA_ENDP_INIT_CTRL_SCND_n_ENDP_DELAY_SHFT 0x1 + +/* IPA_ENDP_INIT_HOL_BLOCK_EN_n register */ +#define IPA_ENDP_INIT_HOL_BLOCK_EN_n_RMSK 0x1 +#define IPA_ENDP_INIT_HOL_BLOCK_EN_n_MAX 19 +#define IPA_ENDP_INIT_HOL_BLOCK_EN_n_MAX_V_4_0 22 +#define IPA_ENDP_INIT_HOL_BLOCK_EN_n_EN_BMSK 0x1 +#define IPA_ENDP_INIT_HOL_BLOCK_EN_n_EN_SHFT 0x0 + +/* IPA_ENDP_INIT_HOL_BLOCK_TIMER_n register */ +#define IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_TIMER_BMSK 0xffffffff +#define IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_TIMER_SHFT 0x0 + +#define IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_BASE_VALUE_SHFT_V_4_2 0 +#define IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_BASE_VALUE_BMSK_V_4_2 0x1f +#define IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_SCALE_SHFT_V_4_2 0x8 +#define IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_SCALE_BMSK_V_4_2 0x1f00 + +#define IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_TIME_LIMIT_BMSK_V4_5 0x1F +#define IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_TIME_LIMIT_SHFT_V4_5 0 +#define IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_GRAN_SEL_BMSK_V4_5 0x100 +#define IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_GRAN_SEL_SHFT_V4_5 0x8 + +#define IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_TIME_LIMIT_BMSK_V5_0 0x1F +#define IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_TIME_LIMIT_SHFT_V5_0 0 +#define IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_GRAN_SEL_BMSK_V5_0 0x300 +#define IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_GRAN_SEL_SHFT_V5_0 0x8 + +/* IPA_ENDP_INIT_DEAGGR_n register */ +#define IPA_ENDP_INIT_DEAGGR_n_MAX_PACKET_LEN_BMSK 0xFFFF0000 +#define IPA_ENDP_INIT_DEAGGR_n_MAX_PACKET_LEN_SHFT 0x10 +#define IPA_ENDP_INIT_DEAGGR_n_IGNORE_MIN_PKT_ERR_BMSK 0x4000 +#define IPA_ENDP_INIT_DEAGGR_n_IGNORE_MIN_PKT_ERR_SHFT 0xe +#define IPA_ENDP_INIT_DEAGGR_n_PACKET_OFFSET_LOCATION_BMSK 0x3F00 +#define IPA_ENDP_INIT_DEAGGR_n_PACKET_OFFSET_LOCATION_SHFT 0x8 +#define IPA_ENDP_INIT_DEAGGR_n_PACKET_OFFSET_VALID_BMSK 0x80 +#define IPA_ENDP_INIT_DEAGGR_n_PACKET_OFFSET_VALID_SHFT 0x7 +#define IPA_ENDP_INIT_DEAGGR_n_SYSPIPE_ERR_DETECTION_BMSK 0x40 +#define IPA_ENDP_INIT_DEAGGR_n_SYSPIPE_ERR_DETECTION_SHFT 0x6 +#define IPA_ENDP_INIT_DEAGGR_n_DEAGGR_HDR_LEN_BMSK 0x3F +#define IPA_ENDP_INIT_DEAGGR_n_DEAGGR_HDR_LEN_SHFT 0x0 + +/* IPA_IPA_ENDP_INIT_SEQ_n register */ +#define IPA_ENDP_INIT_SEQ_n_DPS_REP_SEQ_TYPE_BMSK 0xf000 +#define IPA_ENDP_INIT_SEQ_n_DPS_REP_SEQ_TYPE_SHFT 0xc +#define IPA_ENDP_INIT_SEQ_n_HPS_REP_SEQ_TYPE_BMSK 0xf00 +#define IPA_ENDP_INIT_SEQ_n_HPS_REP_SEQ_TYPE_SHFT 0x8 +#define IPA_ENDP_INIT_SEQ_n_DPS_SEQ_TYPE_BMSK 0xf0 +#define IPA_ENDP_INIT_SEQ_n_DPS_SEQ_TYPE_SHFT 0x4 +#define IPA_ENDP_INIT_SEQ_n_HPS_SEQ_TYPE_BMSK 0xf +#define IPA_ENDP_INIT_SEQ_n_HPS_SEQ_TYPE_SHFT 0x0 + +/* IPA_DEBUG_CNT_REG_m register */ +#define IPA_DEBUG_CNT_REG_N_RMSK 0xffffffff +#define IPA_DEBUG_CNT_REG_N_MAX 15 +#define IPA_DEBUG_CNT_REG_N_DBG_CNT_REG_BMSK 0xffffffff +#define IPA_DEBUG_CNT_REG_N_DBG_CNT_REG_SHFT 0x0 + +/* IPA_ENDP_INIT_CFG_n register */ +#define IPA_ENDP_INIT_CFG_n_PIPE_REPLICATE_EN_SEL_BMSK_V5_5 0x200 +#define IPA_ENDP_INIT_CFG_n_PIPE_REPLICATE_EN_SEL_SHFT_V5_5 0x9 +#define IPA_ENDP_INIT_CFG_n_CS_GEN_QMB_MASTER_SEL_BMSK 0x100 +#define IPA_ENDP_INIT_CFG_n_CS_GEN_QMB_MASTER_SEL_SHFT 0x8 +#define IPA_ENDP_INIT_CFG_n_CS_METADATA_HDR_OFFSET_BMSK 0x78 +#define IPA_ENDP_INIT_CFG_n_CS_METADATA_HDR_OFFSET_SHFT 0x3 +#define IPA_ENDP_INIT_CFG_n_CS_OFFLOAD_EN_BMSK 0x6 +#define IPA_ENDP_INIT_CFG_n_CS_OFFLOAD_EN_SHFT 0x1 +#define IPA_ENDP_INIT_CFG_n_FRAG_OFFLOAD_EN_BMSK 0x1 +#define IPA_ENDP_INIT_CFG_n_FRAG_OFFLOAD_EN_SHFT 0x0 + +/* IPA_ENDP_INIT_PROD_CFG_n register */ +#define IPA_ENDP_INIT_PROD_CFG_n_EGRESS_TC_HIGHEST_BMASK 0xFF000000 +#define IPA_ENDP_INIT_PROD_CFG_n_EGRESS_TC_HIGHEST_SHIFT 0x18 +#define IPA_ENDP_INIT_PROD_CFG_n_EGRESS_TC_LOWEST_BMASK 0xFF0000 +#define IPA_ENDP_INIT_PROD_CFG_n_EGRESS_TC_LOWEST_SHIFT 0x10 +#define IPA_ENDP_INIT_PROD_CFG_n_MAX_OUTPUT_SIZE_BMASK 0xFF00 +#define IPA_ENDP_INIT_PROD_CFG_n_MAX_OUTPUT_SIZE_SHIFT 0x8 +#define IPA_ENDP_INIT_PROD_CFG_n_TSP_INDEX_BMASK 0xF0 +#define IPA_ENDP_INIT_PROD_CFG_n_TSP_INDEX_SHIFT 0x3 +#define IPA_ENDP_INIT_PROD_CFG_n_MAX_OUTPUT_SIZE_DROP_ENABLE_BMASK 0x4 +#define IPA_ENDP_INIT_PROD_CFG_n_MAX_OUTPUT_SIZE_DROP_ENABLE_SHIFT 0x2 +#define IPA_ENDP_INIT_PROD_CFG_n_TSP_ENABLE_BMASK 0x2 +#define IPA_ENDP_INIT_PROD_CFG_n_TSP_ENABLE_SHIFT 0x1 +#define IPA_ENDP_INIT_PROD_CFG_n_TX_SEL_BMASK 0x1 +#define IPA_ENDP_INIT_PROD_CFG_n_TX_SEL_SHIFT 0x0 + + +/* IPA_ENDP_INIT_HDR_METADATA_MASK_n register */ +#define IPA_ENDP_INIT_HDR_METADATA_MASK_n_METADATA_MASK_BMSK 0xffffffff +#define IPA_ENDP_INIT_HDR_METADATA_MASK_n_METADATA_MASK_SHFT 0x0 + +/* IPA_IPA_ENDP_INIT_HDR_METADATA_n register */ +#define IPA_ENDP_INIT_HDR_METADATA_n_METADATA_BMSK 0xffffffff +#define IPA_ENDP_INIT_HDR_METADATA_n_METADATA_SHFT 0x0 + +/* IPA_ENDP_INIT_RSRC_GRP_n register */ +#define IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_BMSK 0x7 +#define IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_SHFT 0 +#define IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_BMSK_v3_5 0x3 +#define IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_SHFT_v3_5 0 +#define IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_BMSK_v4_5 0x7 +#define IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_SHFT_v4_5 0 +#define IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_BMSK_v4_9 0x3 +#define IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_SHFT_v4_9 0 +#define IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_BMSK_v5_0 0x7 +#define IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_SHFT_v5_0 0 + +/* IPA_SHARED_MEM_SIZE register */ +#define IPA_SHARED_MEM_SIZE_SHARED_MEM_BADDR_BMSK 0xffff0000 +#define IPA_SHARED_MEM_SIZE_SHARED_MEM_BADDR_SHFT 0x10 +#define IPA_SHARED_MEM_SIZE_SHARED_MEM_SIZE_BMSK 0xffff +#define IPA_SHARED_MEM_SIZE_SHARED_MEM_SIZE_SHFT 0x0 + +/* IPA_DEBUG_CNT_CTRL_n register */ +#define IPA_DEBUG_CNT_CTRL_n_DBG_CNT_RULE_INDEX_PIPE_RULE_BMSK 0x10000000 +#define IPA_DEBUG_CNT_CTRL_n_DBG_CNT_RULE_INDEX_PIPE_RULE_SHFT 0x1c +#define IPA_DEBUG_CNT_CTRL_n_DBG_CNT_RULE_INDEX_BMSK 0x0ff00000 +#define IPA_DEBUG_CNT_CTRL_n_DBG_CNT_RULE_INDEX_BMSK_V3_5 0x1ff00000 +#define IPA_DEBUG_CNT_CTRL_n_DBG_CNT_RULE_INDEX_SHFT 0x14 +#define IPA_DEBUG_CNT_CTRL_n_DBG_CNT_SOURCE_PIPE_BMSK 0x1f000 +#define IPA_DEBUG_CNT_CTRL_n_DBG_CNT_SOURCE_PIPE_SHFT 0xc +#define IPA_DEBUG_CNT_CTRL_n_DBG_CNT_PRODUCT_BMSK 0x100 +#define IPA_DEBUG_CNT_CTRL_n_DBG_CNT_PRODUCT_SHFT 0x8 +#define IPA_DEBUG_CNT_CTRL_n_DBG_CNT_TYPE_BMSK 0x70 +#define IPA_DEBUG_CNT_CTRL_n_DBG_CNT_TYPE_SHFT 0x4 +#define IPA_DEBUG_CNT_CTRL_n_DBG_CNT_EN_BMSK 0x1 +#define IPA_DEBUG_CNT_CTRL_n_DBG_CNT_EN_SHFT 0x0 + +/* IPA_FILT_ROUT_HASH_FLUSH register */ +#define IPA_FILT_ROUT_HASH_FLUSH_IPv4_FILT_SHFT 12 +#define IPA_FILT_ROUT_HASH_FLUSH_IPv4_ROUT_SHFT 8 +#define IPA_FILT_ROUT_HASH_FLUSH_IPv6_FILT_SHFT 4 +#define IPA_FILT_ROUT_HASH_FLUSH_IPv6_ROUT_SHFT 0 + +/* IPA_FILT_ROUT_CACHE_FLUSH register */ +#define IPA_FILT_ROUT_CACHE_FLUSH_FILT_SHFT 4 +#define IPA_FILT_ROUT_CACHE_FLUSH_ROUT_SHFT 0 + +/* IPA_SINGLE_NDP_MODE register */ +#define IPA_SINGLE_NDP_MODE_UNDEFINED_BMSK 0xfffffffe +#define IPA_SINGLE_NDP_MODE_UNDEFINED_SHFT 0x1 +#define IPA_SINGLE_NDP_MODE_SINGLE_NDP_EN_BMSK 0x1 +#define IPA_SINGLE_NDP_MODE_SINGLE_NDP_EN_SHFT 0 + +/* IPA_QCNCM register */ +#define IPA_QCNCM_MODE_UNDEFINED2_BMSK 0xf0000000 +#define IPA_QCNCM_MODE_UNDEFINED2_SHFT 0x1c +#define IPA_QCNCM_MODE_VAL_BMSK 0xffffff0 +#define IPA_QCNCM_MODE_VAL_SHFT 0x4 +#define IPA_QCNCM_UNDEFINED1_BMSK 0xe +#define IPA_QCNCM_UNDEFINED1_SHFT 0x1 +#define IPA_QCNCM_MODE_EN_BMSK 0x1 +#define IPA_QCNCM_MODE_EN_SHFT 0 + +/* IPA_ENDP_STATUS_n register */ +#define IPA_ENDP_STATUS_n_STATUS_PKT_SUPPRESS_BMSK 0x200 +#define IPA_ENDP_STATUS_n_STATUS_PKT_SUPPRESS_SHFT 0x9 +#define IPA_ENDP_STATUS_n_STATUS_LOCATION_BMSK 0x100 +#define IPA_ENDP_STATUS_n_STATUS_LOCATION_SHFT 0x8 +#define IPA_ENDP_STATUS_n_STATUS_ENDP_BMSK 0x3e +#define IPA_ENDP_STATUS_n_STATUS_ENDP_SHFT 0x1 +#define IPA_ENDP_STATUS_n_STATUS_EN_BMSK 0x1 +#define IPA_ENDP_STATUS_n_STATUS_EN_SHFT 0x0 + +#define IPA_ENDP_STATUS_n_STATUS_ENDP_BMSK_V5_0 0x1fe +#define IPA_ENDP_STATUS_n_STATUS_ENDP_SHFT_V5_0 0x1 + +/* IPA_CLKON_CFG register */ +#define IPA_CLKON_CFG_CGC_OPEN_DPL_FIFO_BMSK_V4_5 0x40000000 +#define IPA_CLKON_CFG_CGC_OPEN_DPL_FIFO_SHFT_V4_5 30 +#define IPA_CLKON_CFG_OPEN_GLOBAL_2X_CLK_BMSK 0x20000000 +#define IPA_CLKON_CFG_OPEN_GLOBAL_2X_CLK_SHFT 29 +#define IPA_CLKON_CFG_OPEN_GLOBAL_BMSK 0x10000000 +#define IPA_CLKON_CFG_OPEN_GLOBAL_SHFT 28 +#define IPA_CLKON_CFG_OPEN_GSI_IF_BMSK 0x8000000 +#define IPA_CLKON_CFG_OPEN_GSI_IF_SHFT 27 +#define IPA_CLKON_CFG_OPEN_WEIGHT_ARB_SHFT 26 +#define IPA_CLKON_CFG_OPEN_WEIGHT_ARB_BMSK 0x4000000 +#define IPA_CLKON_CFG_OPEN_QMB_SHFT 25 +#define IPA_CLKON_CFG_OPEN_QMB_BMSK 0x2000000 +#define IPA_CLKON_CFG_OPEN_RAM_SLAVEWAY_SHFT 24 +#define IPA_CLKON_CFG_OPEN_RAM_SLAVEWAY_BMSK 0x1000000 +#define IPA_CLKON_CFG_OPEN_AGGR_WRAPPER_SHFT 23 +#define IPA_CLKON_CFG_OPEN_AGGR_WRAPPER_BMSK 0x800000 +#define IPA_CLKON_CFG_OPEN_QSB2AXI_CMDQ_L_SHFT 22 +#define IPA_CLKON_CFG_OPEN_QSB2AXI_CMDQ_L_BMSK 0x400000 +#define IPA_CLKON_CFG_OPEN_FNR_SHFT 21 +#define IPA_CLKON_CFG_OPEN_FNR_BMSK 0x200000 +#define IPA_CLKON_CFG_OPEN_TX_1_SHFT 20 +#define IPA_CLKON_CFG_OPEN_TX_1_BMSK 0x100000 +#define IPA_CLKON_CFG_OPEN_TX_0_SHFT 19 +#define IPA_CLKON_CFG_OPEN_TX_0_BMSK 0x80000 +#define IPA_CLKON_CFG_OPEN_NTF_TX_CMDQS_SHFT 18 +#define IPA_CLKON_CFG_OPEN_NTF_TX_CMDQS_BMSK 0x40000 +#define IPA_CLKON_CFG_OPEN_DCMP_SHFT 17 +#define IPA_CLKON_CFG_OPEN_DCMP_BMSK 0x20000 +#define IPA_CLKON_CFG_OPEN_H_DCPH_SHFT 16 +#define IPA_CLKON_CFG_OPEN_H_DCPH_BMSK 0x10000 +#define IPA_CLKON_CFG_OPEN_D_DCPH_SHFT 15 +#define IPA_CLKON_CFG_OPEN_D_DCPH_BMSK 0x8000 +#define IPA_CLKON_CFG_OPEN_ACK_MNGR_SHFT 14 +#define IPA_CLKON_CFG_OPEN_ACK_MNGR_BMSK 0x4000 +#define IPA_CLKON_CFG_OPEN_CTX_HANDLER_SHFT 13 +#define IPA_CLKON_CFG_OPEN_CTX_HANDLER_BMSK 0x2000 +#define IPA_CLKON_CFG_OPEN_RSRC_MNGR_SHFT 12 +#define IPA_CLKON_CFG_OPEN_RSRC_MNGR_BMSK 0x1000 +#define IPA_CLKON_CFG_OPEN_DPS_TX_CMDQS_SHFT 11 +#define IPA_CLKON_CFG_OPEN_DPS_TX_CMDQS_BMSK 0x800 +#define IPA_CLKON_CFG_OPEN_HPS_DPS_CMDQS_SHFT 10 +#define IPA_CLKON_CFG_OPEN_HPS_DPS_CMDQS_BMSK 0x400 +#define IPA_CLKON_CFG_OPEN_RX_HPS_CMDQS_SHFT 9 +#define IPA_CLKON_CFG_OPEN_RX_HPS_CMDQS_BMSK 0x200 +#define IPA_CLKON_CFG_OPEN_DPS_SHFT 8 +#define IPA_CLKON_CFG_OPEN_DPS_BMSK 0x100 +#define IPA_CLKON_CFG_OPEN_HPS_SHFT 7 +#define IPA_CLKON_CFG_OPEN_HPS_BMSK 0x80 +#define IPA_CLKON_CFG_OPEN_FTCH_DPS_SHFT 6 +#define IPA_CLKON_CFG_OPEN_FTCH_DPS_BMSK 0x40 +#define IPA_CLKON_CFG_OPEN_FTCH_HPS_SHFT 5 +#define IPA_CLKON_CFG_OPEN_FTCH_HPS_BMSK 0x20 +#define IPA_CLKON_CFG_OPEN_RAM_ARB_SHFT 4 +#define IPA_CLKON_CFG_OPEN_RAM_ARB_BMSK 0x10 +#define IPA_CLKON_CFG_OPEN_MISC_SHFT 3 +#define IPA_CLKON_CFG_OPEN_MISC_BMSK 0x8 +#define IPA_CLKON_CFG_OPEN_TX_WRAPPER_SHFT 2 +#define IPA_CLKON_CFG_OPEN_TX_WRAPPER_BMSK 0x4 +#define IPA_CLKON_CFG_OPEN_PROC_SHFT 1 +#define IPA_CLKON_CFG_OPEN_PROC_BMSK 0x2 +#define IPA_CLKON_CFG_OPEN_RX_BMSK 0x1 +#define IPA_CLKON_CFG_OPEN_RX_SHFT 0 + +/* IPA_QTIME_TIMESTAMP_CFG register */ +#define IPA_QTIME_TIMESTAMP_CFG_DPL_TIMESTAMP_LSB_SHFT 0 +#define IPA_QTIME_TIMESTAMP_CFG_DPL_TIMESTAMP_LSB_BMSK 0x1F +#define IPA_QTIME_TIMESTAMP_CFG_DPL_TIMESTAMP_SEL_SHFT 7 +#define IPA_QTIME_TIMESTAMP_CFG_DPL_TIMESTAMP_SEL_BMSK 0x80 +#define IPA_QTIME_TIMESTAMP_CFG_TAG_TIMESTAMP_LSB_SHFT 8 +#define IPA_QTIME_TIMESTAMP_CFG_TAG_TIMESTAMP_LSB_BMSK 0x1F00 +#define IPA_QTIME_TIMESTAMP_CFG_NAT_TIMESTAMP_LSB_SHFT 16 +#define IPA_QTIME_TIMESTAMP_CFG_NAT_TIMESTAMP_LSB_BMSK 0x1F0000 + +/* IPA_TIMERS_PULSE_GRAN_CFG register */ +#define IPA_TIMERS_PULSE_GRAN_CFG_GRAN_X_SHFT(x) (3 * (x)) +#define IPA_TIMERS_PULSE_GRAN_CFG_GRAN_X_BMSK(x) (0x7 << (3 * (x))) + +/* IPA_TIMERS_XO_CLK_DIV_CFG register */ +#define IPA_TIMERS_XO_CLK_DIV_CFG_VALUE_SHFT 0 +#define IPA_TIMERS_XO_CLK_DIV_CFG_VALUE_BMSK 0x1FF +#define IPA_TIMERS_XO_CLK_DIV_CFG_ENABLE_SHFT 31 +#define IPA_TIMERS_XO_CLK_DIV_CFG_ENABLE_BMSK 0x80000000 + +/* IPA_ENDP_FILTER_ROUTER_HSH_CFG_n register */ +#define IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_SRC_ID_SHFT 0 +#define IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_SRC_ID_BMSK 0x1 +#define IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_SRC_IP_SHFT 1 +#define IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_SRC_IP_BMSK 0x2 +#define IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_DST_IP_SHFT 2 +#define IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_DST_IP_BMSK 0x4 +#define IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_SRC_PORT_SHFT 3 +#define IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_SRC_PORT_BMSK 0x8 +#define IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_DST_PORT_SHFT 4 +#define IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_DST_PORT_BMSK 0x10 +#define IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_PROTOCOL_SHFT 5 +#define IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_PROTOCOL_BMSK 0x20 +#define IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_METADATA_SHFT 6 +#define IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_METADATA_BMSK 0x40 +#define IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_UNDEFINED1_SHFT 7 +#define IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_UNDEFINED1_BMSK 0xff80 +#define IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_SRC_ID_SHFT 16 +#define IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_SRC_ID_BMSK 0x10000 +#define IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_SRC_IP_SHFT 17 +#define IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_SRC_IP_BMSK 0x20000 +#define IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_DST_IP_SHFT 18 +#define IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_DST_IP_BMSK 0x40000 +#define IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_SRC_PORT_SHFT 19 +#define IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_SRC_PORT_BMSK 0x80000 +#define IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_DST_PORT_SHFT 20 +#define IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_DST_PORT_BMSK 0x100000 +#define IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_PROTOCOL_SHFT 21 +#define IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_PROTOCOL_BMSK 0x200000 +#define IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_METADATA_SHFT 22 +#define IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_METADATA_BMSK 0x400000 +#define IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_UNDEFINED2_SHFT 23 +#define IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_UNDEFINED2_BMSK 0xff800000 + +/* IPA_FILTER_CACHE_CFG_n and IPA_ROUTER_CACHE_CFG_n registers*/ +#define IPA_ENDP_FILTER_ROUTER_CACHE_CFG_n_CACHE_MSK_SRC_ID_SHFT 0 +#define IPA_ENDP_FILTER_ROUTER_CACHE_CFG_n_CACHE_MSK_SRC_ID_BMSK 0x1 +#define IPA_ENDP_FILTER_ROUTER_CACHE_CFG_n_CACHE_MSK_SRC_IP_SHFT 1 +#define IPA_ENDP_FILTER_ROUTER_CACHE_CFG_n_CACHE_MSK_SRC_IP_BMSK 0x2 +#define IPA_ENDP_FILTER_ROUTER_CACHE_CFG_n_CACHE_MSK_DST_IP_SHFT 2 +#define IPA_ENDP_FILTER_ROUTER_CACHE_CFG_n_CACHE_MSK_DST_IP_BMSK 0x4 +#define IPA_ENDP_FILTER_ROUTER_CACHE_CFG_n_CACHE_MSK_SRC_PORT_SHFT 3 +#define IPA_ENDP_FILTER_ROUTER_CACHE_CFG_n_CACHE_MSK_SRC_PORT_BMSK 0x8 +#define IPA_ENDP_FILTER_ROUTER_CACHE_CFG_n_CACHE_MSK_DST_PORT_SHFT 4 +#define IPA_ENDP_FILTER_ROUTER_CACHE_CFG_n_CACHE_MSK_DST_PORT_BMSK 0x10 +#define IPA_ENDP_FILTER_ROUTER_CACHE_CFG_n_CACHE_MSK_PROTOCOL_SHFT 5 +#define IPA_ENDP_FILTER_ROUTER_CACHE_CFG_n_CACHE_MSK_PROTOCOL_BMSK 0x20 +#define IPA_ENDP_FILTER_ROUTER_CACHE_CFG_n_CACHE_MSK_METADATA_SHFT 6 +#define IPA_ENDP_FILTER_ROUTER_CACHE_CFG_n_CACHE_MSK_METADATA_BMSK 0x40 +#define IPA_ENDP_FILTER_ROUTER_CACHE_CFG_n_UNDEFINED_SHFT 7 +#define IPA_ENDP_FILTER_ROUTER_CACHE_CFG_n_UNDEFINED_BMSK 0xffffff80 + + +/* IPA_RSRC_GRP_XY_RSRC_TYPE_n register */ +#define IPA_RSRC_GRP_XY_RSRC_TYPE_n_Y_MAX_LIM_BMSK 0xFF000000 +#define IPA_RSRC_GRP_XY_RSRC_TYPE_n_Y_MAX_LIM_SHFT 24 +#define IPA_RSRC_GRP_XY_RSRC_TYPE_n_Y_MIN_LIM_BMSK 0xFF0000 +#define IPA_RSRC_GRP_XY_RSRC_TYPE_n_Y_MIN_LIM_SHFT 16 +#define IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MAX_LIM_BMSK 0xFF00 +#define IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MAX_LIM_SHFT 8 +#define IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MIN_LIM_BMSK 0xFF +#define IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MIN_LIM_SHFT 0 +#define IPA_RSRC_GRP_XY_RSRC_TYPE_n_Y_MAX_LIM_BMSK_V3_5 0x3F000000 +#define IPA_RSRC_GRP_XY_RSRC_TYPE_n_Y_MAX_LIM_SHFT_V3_5 24 +#define IPA_RSRC_GRP_XY_RSRC_TYPE_n_Y_MIN_LIM_BMSK_V3_5 0x3F0000 +#define IPA_RSRC_GRP_XY_RSRC_TYPE_n_Y_MIN_LIM_SHFT_V3_5 16 +#define IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MAX_LIM_BMSK_V3_5 0x3F00 +#define IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MAX_LIM_SHFT_V3_5 8 +#define IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MIN_LIM_BMSK_V3_5 0x3F +#define IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MIN_LIM_SHFT_V3_5 0 + +/* IPA_RX_HPS_CLIENTS_MIN/MAX_DEPTH_0/1 registers */ +#define IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_X_CLIENT_n_BMSK(n) (0x7F << (8 * (n))) +#define IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_X_CLIENT_n_BMSK_V3_5(n) \ + (0xF << (8 * (n))) +#define IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_X_CLIENT_n_SHFT(n) (8 * (n)) +#define IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_0_CLIENT_4_BMSK_v4_5 0xF0000000 +#define IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_0_CLIENT_4_SHFT_v4_5 28 +#define IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_0_CLIENT_3_BMSK_v4_5 0xF000000 +#define IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_0_CLIENT_3_SHFT_v4_5 24 +#define IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_0_CLIENT_2_BMSK_v4_5 0xF0000 +#define IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_0_CLIENT_2_SHFT_v4_5 16 +#define IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_0_CLIENT_1_BMSK_v4_5 0xF00 +#define IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_0_CLIENT_1_SHFT_v4_5 8 +#define IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_0_CLIENT_0_BMSK_v4_5 0xF +#define IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_0_CLIENT_0_SHFT_v4_5 0 + +/* IPA_QSB_MAX_WRITES register */ +#define IPA_QSB_MAX_WRITES_GEN_QMB_0_MAX_WRITES_BMSK (0xf) +#define IPA_QSB_MAX_WRITES_GEN_QMB_0_MAX_WRITES_SHFT (0) +#define IPA_QSB_MAX_WRITES_GEN_QMB_1_MAX_WRITES_BMSK (0xf0) +#define IPA_QSB_MAX_WRITES_GEN_QMB_1_MAX_WRITES_SHFT (4) + +/* IPA_QSB_MAX_READS register */ +#define IPA_QSB_MAX_READS_GEN_QMB_0_MAX_READS_BMSK (0xf) +#define IPA_QSB_MAX_READS_GEN_QMB_0_MAX_READS_SHFT (0) +#define IPA_QSB_MAX_READS_GEN_QMB_1_MAX_READS_BMSK (0xf0) +#define IPA_QSB_MAX_READS_GEN_QMB_1_MAX_READS_SHFT (4) + +/* IPA_QSB_MAX_READS_BEATS register */ +#define IPA_QSB_MAX_READS_GEN_QMB_0_MAX_READS_BEATS_BMSK_V4_0 (0xff0000) +#define IPA_QSB_MAX_READS_GEN_QMB_0_MAX_READS_BEATS_SHFT_V4_0 (0x10) +#define IPA_QSB_MAX_READS_GEN_QMB_1_MAX_READS_BEATS_BMSK_V4_0 (0xff000000) +#define IPA_QSB_MAX_READS_GEN_QMB_1_MAX_READS_BEATS_SHFT_V4_0 (0x18) + +/* IPA_TX_CFG register */ +#define IPA_TX_CFG_TX0_PREFETCH_DISABLE_BMSK_V3_5 (0x1) +#define IPA_TX_CFG_TX0_PREFETCH_DISABLE_SHFT_V3_5 (0) +#define IPA_TX_CFG_TX1_PREFETCH_DISABLE_BMSK_V3_5 (0x2) +#define IPA_TX_CFG_TX1_PREFETCH_DISABLE_SHFT_V3_5 (1) +#define IPA_TX_CFG_PREFETCH_ALMOST_EMPTY_SIZE_BMSK_V3_5 (0x1C) +#define IPA_TX_CFG_PREFETCH_ALMOST_EMPTY_SIZE_SHFT_V3_5 (2) + +#define IPA_TX_CFG_HOLB_STICKY_DROP_EN_BMSK_v5_0 (0x100000) +#define IPA_TX_CFG_HOLB_STICKY_DROP_EN_SHFT_v5_0 (0x14) +#define IPA_TX_CFG_SSPND_PA_NO_START_STATE_BMSK_V4_9 (0x40000) +#define IPA_TX_CFG_SSPND_PA_NO_START_STATE_SHFT_V4_9 (0x12) +#define IPA_TX_CFG_DUAL_TX_ENABLE_BMSK_V4_5 (0x20000) +#define IPA_TX_CFG_DUAL_TX_ENABLE_SHFT_V4_5 (0x11) +#define IPA_TX_CFG_PREFETCH_ALMOST_EMPTY_SIZE_TX1_BMSK_V4_0 (0x1e000) +#define IPA_TX_CFG_PREFETCH_ALMOST_EMPTY_SIZE_TX1_SHFT_V4_0 (0xd) +#define IPA_TX_CFG_PA_MASK_EN_BMSK_V4_0 (0x1000) +#define IPA_TX_CFG_PA_MASK_EN_SHFT_V4_0 (0xc) +#define IPA_TX_CFG_DMAW_SCND_OUTSD_PRED_EN_BMSK_V4_0 (0x800) +#define IPA_TX_CFG_DMAW_SCND_OUTSD_PRED_EN_SHFT_V4_0 (0xb) +#define IPA_TX_CFG_DMAW_MAX_BEATS_256_DIS_BMSK_V4_0 (0x400) +#define IPA_TX_CFG_DMAW_MAX_BEATS_256_DIS_SHFT_V4_0 (0xa) +#define IPA_TX_CFG_DMAW_SCND_OUTSD_PRED_THRESHOLD_BMSK_V4_0 (0x3c0) +#define IPA_TX_CFG_DMAW_SCND_OUTSD_PRED_THRESHOLD_SHFT_V4_0 (0x6) +#define IPA_TX_CFG_PREFETCH_ALMOST_EMPTY_SIZE_TX0_BMSK_V4_0 (0x3c) +#define IPA_TX_CFG_PREFETCH_ALMOST_EMPTY_SIZE_TX0_SHFT_V4_0 (0x2) + +/* IPA_IDLE_INDICATION_CFG regiser */ +#define IPA_IDLE_INDICATION_CFG_ENTER_IDLE_DEBOUNCE_THRESH_BMSK_V3_5 (0xffff) +#define IPA_IDLE_INDICATION_CFG_ENTER_IDLE_DEBOUNCE_THRESH_SHFT_V3_5 (0) +#define IPA_IDLE_INDICATION_CFG_CONST_NON_IDLE_ENABLE_BMSK_V3_5 (0x10000) +#define IPA_IDLE_INDICATION_CFG_CONST_NON_IDLE_ENABLE_SHFT_V3_5 (16) + +/* IPA_HPS_FTCH_QUEUE_WEIGHT register */ +#define IPA_HPS_FTCH_ARB_QUEUE_WEIGHTS_RX_HPS_QUEUE_WEIGHT_0_BMSK (0xf) +#define IPA_HPS_FTCH_ARB_QUEUE_WEIGHTS_RX_HPS_QUEUE_WEIGHT_0_SHFT (0x0) +#define IPA_HPS_FTCH_ARB_QUEUE_WEIGHTS_RX_HPS_QUEUE_WEIGHT_1_BMSK (0xf0) +#define IPA_HPS_FTCH_ARB_QUEUE_WEIGHTS_RX_HPS_QUEUE_WEIGHT_1_SHFT (0x4) +#define IPA_HPS_FTCH_ARB_QUEUE_WEIGHTS_RX_HPS_QUEUE_WEIGHT_2_BMSK (0xf00) +#define IPA_HPS_FTCH_ARB_QUEUE_WEIGHTS_RX_HPS_QUEUE_WEIGHT_2_SHFT (0x8) +#define IPA_HPS_FTCH_ARB_QUEUE_WEIGHTS_RX_HPS_QUEUE_WEIGHT_3_BMSK (0xf000) +#define IPA_HPS_FTCH_ARB_QUEUE_WEIGHTS_RX_HPS_QUEUE_WEIGHT_3_SHFT (0xc) + +/* IPA_COUNTER_CFG register */ +#define IPA_COUNTER_CFG_AGGR_GRANULARITY_BMSK (0x1f0) +#define IPA_COUNTER_CFG_AGGR_GRANULARITY_SHFT (0x4) + +/* IPA_COMP_CFG register*/ +#define IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_BMSK 0x1E0000 +#define IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_SHFT 17 +#define IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_GLOBAL_EN_BMSK 0x10000 +#define IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_GLOBAL_EN_SHFT 16 +#define IPA_COMP_CFG_GSI_MULTI_AXI_MASTERS_DIS_BMSK 0x8000 +#define IPA_COMP_CFG_GSI_MULTI_AXI_MASTERS_DIS_SHFT 15 +#define IPA_COMP_CFG_GSI_SNOC_CNOC_LOOP_PROTECTION_DISABLE_BMSK 0x4000 +#define IPA_COMP_CFG_GSI_SNOC_CNOC_LOOP_PROTECTION_DISABLE_SHFT 14 +#define IPA_COMP_CFG_GEN_QMB_0_SNOC_CNOC_LOOP_PROTECTION_DISABLE_BMSK 0x2000 +#define IPA_COMP_CFG_GEN_QMB_0_SNOC_CNOC_LOOP_PROTECTION_DISABLE_SHFT 13 +#define IPA_COMP_CFG_GEN_QMB_1_MULTI_INORDER_WR_DIS_BMSK 0x1000 +#define IPA_COMP_CFG_GEN_QMB_1_MULTI_INORDER_WR_DIS_SHFT 12 +#define IPA_COMP_CFG_GEN_QMB_0_MULTI_INORDER_WR_DIS_BMSK 0x800 +#define IPA_COMP_CFG_GEN_QMB_0_MULTI_INORDER_WR_DIS_SHFT 11 +#define IPA_COMP_CFG_GEN_QMB_1_MULTI_INORDER_RD_DIS_BMSK 0x400 +#define IPA_COMP_CFG_GEN_QMB_1_MULTI_INORDER_RD_DIS_SHFT 10 +#define IPA_COMP_CFG_GEN_QMB_0_MULTI_INORDER_RD_DIS_BMSK 0x200 +#define IPA_COMP_CFG_GEN_QMB_0_MULTI_INORDER_RD_DIS_SHFT 9 +#define IPA_COMP_CFG_GSI_MULTI_INORDER_WR_DIS_BMSK 0x100 +#define IPA_COMP_CFG_GSI_MULTI_INORDER_WR_DIS_SHFT 8 +#define IPA_COMP_CFG_GSI_MULTI_INORDER_RD_DIS_BMSK 0x80 +#define IPA_COMP_CFG_GSI_MULTI_INORDER_RD_DIS_SHFT 7 +#define IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_PROD_EN_BMSK 0x40 +#define IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_PROD_EN_SHFT 6 +#define IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_CONS_EN_BMSK 0x20 +#define IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_CONS_EN_SHFT 5 +#define IPA_COMP_CFG_IPA_DCMP_FAST_CLK_EN_BMSK 0x10 +#define IPA_COMP_CFG_IPA_DCMP_FAST_CLK_EN_SHFT 4 +#define IPA_COMP_CFG_GEN_QMB_1_SNOC_BYPASS_DIS_BMSK 0x8 +#define IPA_COMP_CFG_GEN_QMB_1_SNOC_BYPASS_DIS_SHFT 3 +#define IPA_COMP_CFG_GEN_QMB_0_SNOC_BYPASS_DIS_BMSK 0x4 +#define IPA_COMP_CFG_GEN_QMB_0_SNOC_BYPASS_DIS_SHFT 2 +#define IPA_COMP_CFG_GSI_SNOC_BYPASS_DIS_BMSK 0x2 +#define IPA_COMP_CFG_GSI_SNOC_BYPASS_DIS_SHFT 1 +#define IPA_COMP_CFG_ENABLE_BMSK 0x1 +#define IPA_COMP_CFG_ENABLE_SHFT 0 + +#define IPA_COMP_CFG_IPA_FULL_FLUSH_WAIT_RSC_CLOSURE_EN_BMSK_v4_5 0x200000 +#define IPA_COMP_CFG_IPA_FULL_FLUSH_WAIT_RSC_CLOSURE_EN_SHFT_v4_5 21 +#define IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_BMSK_v4_5 0x1E0000 +#define IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_SHFT_v4_5 17 +#define IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_GLOBAL_EN_BMSK_v4_5 0x10000 +#define IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_GLOBAL_EN_SHFT_v4_5 16 +#define IPA_COMP_CFG_GSI_MULTI_AXI_MASTERS_DIS_BMSK_v4_5 0x8000 +#define IPA_COMP_CFG_GSI_MULTI_AXI_MASTERS_DIS_SHFT_v4_5 15 +#define IPA_COMP_CFG_GSI_SNOC_CNOC_LOOP_PROTECTION_DISABLE_BMSK_v4_5 0x4000 +#define IPA_COMP_CFG_GSI_SNOC_CNOC_LOOP_PROTECTION_DISABLE_SHFT_v4_5 14 +#define IPA_COMP_CFG_GEN_QMB_0_SNOC_CNOC_LOOP_PROTECTION_DISABLE_BMSK_v4_5 \ + 0x2000 +#define IPA_COMP_CFG_GEN_QMB_0_SNOC_CNOC_LOOP_PROTECTION_DISABLE_SHFT_v4_5 13 +#define IPA_COMP_CFG_GEN_QMB_1_MULTI_INORDER_WR_DIS_BMSK_v4_5 0x1000 +#define IPA_COMP_CFG_GEN_QMB_1_MULTI_INORDER_WR_DIS_SHFT_v4_5 12 +#define IPA_COMP_CFG_GEN_QMB_0_MULTI_INORDER_WR_DIS_BMSK_v4_5 0x800 +#define IPA_COMP_CFG_GEN_QMB_0_MULTI_INORDER_WR_DIS_SHFT_v4_5 11 +#define IPA_COMP_CFG_GEN_QMB_1_MULTI_INORDER_RD_DIS_BMSK_v4_5 0x400 +#define IPA_COMP_CFG_GEN_QMB_1_MULTI_INORDER_RD_DIS_SHFT_v4_5 10 +#define IPA_COMP_CFG_GEN_QMB_0_MULTI_INORDER_RD_DIS_BMSK_v4_5 0x200 +#define IPA_COMP_CFG_GEN_QMB_0_MULTI_INORDER_RD_DIS_SHFT_v4_5 9 +#define IPA_COMP_CFG_GSI_MULTI_INORDER_WR_DIS_BMSK_v4_5 0x100 +#define IPA_COMP_CFG_GSI_MULTI_INORDER_WR_DIS_SHFT_v4_5 8 +#define IPA_COMP_CFG_GSI_MULTI_INORDER_RD_DIS_BMSK_v4_5 0x80 +#define IPA_COMP_CFG_GSI_MULTI_INORDER_RD_DIS_SHFT_v4_5 7 +#define IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_PROD_EN_BMSK_v4_5 0x40 +#define IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_PROD_EN_SHFT_v4_5 6 +#define IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_CONS_EN_BMSK_v4_5 0x20 +#define IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_CONS_EN_SHFT_v4_5 5 +#define IPA_COMP_CFG_GEN_QMB_1_SNOC_BYPASS_DIS_BMSK_v4_5 0x8 +#define IPA_COMP_CFG_GEN_QMB_1_SNOC_BYPASS_DIS_SHFT_v4_5 3 +#define IPA_COMP_CFG_GEN_QMB_0_SNOC_BYPASS_DIS_BMSK_v4_5 0x4 +#define IPA_COMP_CFG_GEN_QMB_0_SNOC_BYPASS_DIS_SHFT_v4_5 2 +#define IPA_COMP_CFG_GSI_SNOC_BYPASS_DIS_BMSK_v4_5 0x2 +#define IPA_COMP_CFG_GSI_SNOC_BYPASS_DIS_SHFT_v4_5 1 + + +/*IPA 4.9*/ +#define IPA_COMP_CFG_GEN_QMB_0_DYNAMIC_ASIZE_BMSK_v4_9 0x80000000 +#define IPA_COMP_CFG_GEN_QMB_0_DYNAMIC_ASIZE_SHFT_v4_9 31 +#define IPA_COMP_CFG_GEN_QMB_1_DYNAMIC_ASIZE_BMSK_v4_9 0x40000000 +#define IPA_COMP_CFG_GEN_QMB_1_DYNAMIC_ASIZE_SHFT_v4_9 30 +#define IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_BMSK_v4_9 0x1C00000 +#define IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_SHFT_v4_9 22 +#define IPA_COMP_CFG_GSI_IF_OUT_OF_BUF_STOP_RESET_MASK_ENABLE_BMSK_v4_9 0x200000 +#define IPA_COMP_CFG_GSI_IF_OUT_OF_BUF_STOP_RESET_MASK_ENABLE_SHFT_v4_9 21 +#define IPA_COMP_CFG_GENQMB_AOOOWR_BMSK_v4_9 0x100000 +#define IPA_COMP_CFG_GENQMB_AOOOWR_SHFT_v4_9 20 +#define IPA_COMP_CFG_QMB_RAM_RD_CACHE_DISABLE_BMSK_v4_9 0x80000 +#define IPA_COMP_CFG_QMB_RAM_RD_CACHE_DISABLE_SHFT_v4_9 19 +#define IPA_COMP_CFG_IPA_FULL_FLUSH_WAIT_RSC_CLOSURE_EN_BMSK_v4_9 0x20000 +#define IPA_COMP_CFG_IPA_FULL_FLUSH_WAIT_RSC_CLOSURE_EN_SHFT_v4_9 17 +#define IPA_COMP_CFG_RAM_ARB_PRIORITY_CLIENT_SAMP_FIX_DISABLE_BMSK_v4_9 0x1 +#define IPA_COMP_CFG_RAM_ARB_PRIORITY_CLIENT_SAMP_FIX_DISABLE_SHFT_v4_9 0 + +/* IPA_COAL registers*/ +#define IPA_STATE_COAL_MASTER_VP_TIMER_EXPIRED_BMSK 0xF0000000 +#define IPA_STATE_COAL_MASTER_VP_TIMER_EXPIRED_SHFT 28 +#define IPA_STATE_COAL_MASTER_LRU_VP_BMSK 0xF000000 +#define IPA_STATE_COAL_MASTER_LRU_VP_SHFT 24 +#define IPA_STATE_COAL_MASTER_INIT_VP_FSM_STATE_BMSK 0xF00000 +#define IPA_STATE_COAL_MASTER_INIT_VP_FSM_STATE_SHFT 20 +#define IPA_STATE_COAL_MASTER_CHECK_FIR_FSM_STATE_BMSK 0xF0000 +#define IPA_STATE_COAL_MASTER_CHECK_FIR_FSM_STATE_SHFT 16 +#define IPA_STATE_COAL_MASTER_HASH_CALC_FSM_STATE_BMSK 0xF000 +#define IPA_STATE_COAL_MASTER_HASH_CALC_FSM_STATE_SHFT 12 +#define IPA_STATE_COAL_MASTER_FIND_OPEN_FSM_STATE_BMSK 0xF00 +#define IPA_STATE_COAL_MASTER_FIND_OPEN_FSM_STATE_SHFT 8 +#define IPA_STATE_COAL_MASTER_MAIN_FSM_STATE_BMSK 0xF0 +#define IPA_STATE_COAL_MASTER_MAIN_FSM_STATE_SHFT 4 +#define IPA_STATE_COAL_MASTER_VP_VLD_BMSK 0xF0 +#define IPA_STATE_COAL_MASTER_VP_VLD_SHFT 0 +#define IPA_COAL_VP_LRU_THRSHLD_BMSK 0x3E +#define IPA_COAL_VP_LRU_THRSHLD_SHFT 1 +#define IPA_COAL_EVICTION_EN_BMSK 0x1 +#define IPA_COAL_EVICTION_EN_SHFT 0 +#define IPA_COAL_QMAP_CFG_BMSK 0x3 +#define IPA_COAL_QMAP_CFG_SHFT 0 +#define IPA_NAT_UC_EXTERNAL_CFG_BMSK 0xFFFFFFFF +#define IPA_NAT_UC_EXTERNAL_CFG_SHFT 0 +#define IPA_NAT_UC_LOCAL_CFG_BMSK 0xFFFFFFFF +#define IPA_NAT_UC_LOCAL_CFG_SHFT 0 +#define IPA_NAT_UC_SHARED_CFG_LOCAL_TABLE_ADDR_MSB_BMSK 0xFFFF0000 +#define IPA_NAT_UC_SHARED_CFG_LOCAL_TABLE_ADDR_MSB_SHFT 16 +#define IPA_NAT_UC_SHARED_CFG_EXTERNAL_TABLE_ADDR_MSB_BMSK 0x0000FFFF +#define IPA_NAT_UC_SHARED_CFG_EXTERNAL_TABLE_ADDR_MSB_SHFT 0 +#define IPA_CONN_TRACK_UC_EXTERNAL_CFG_BMSK 0xFFFFFFFF +#define IPA_CONN_TRACK_UC_EXTERNAL_CFG_SHFT 0 +#define IPA_CONN_TRACK_UC_LOCAL_CFG_BMSK 0xFFFFFFFF +#define IPA_CONN_TRACK_UC_LOCAL_CFG_SHFT 0 +#define IPA_CONN_TRACK_UC_SHARED_CFG_LOCAL_TABLE_ADDR_MSB_BMSK 0xFFFF0000 +#define IPA_CONN_TRACK_UC_SHARED_CFG_LOCAL_TABLE_ADDR_MSB_SHFT 16 +#define IPA_CONN_TRACK_UC_SHARED_CFG_EXTERNAL_TABLE_ADDR_MSB_BMSK 0x0000FFFF +#define IPA_CONN_TRACK_UC_SHARED_CFG_EXTERNAL_TABLE_ADDR_MSB_SHFT 0 +#define IPA_STATE_TX_WRAPPER_COAL_SLAVE_OPEN_FRAME_BMSK 0xf0000000 +#define IPA_STATE_TX_WRAPPER_COAL_SLAVE_OPEN_FRAME_SHFT 0x1f +#define IPA_STATE_TX_WRAPPER_COAL_SLAVE_CTX_IDLE_BMSK 0x100000 +#define IPA_STATE_TX_WRAPPER_COAL_SLAVE_CTX_IDLE_SHFT 0x10 +#define IPA_STATE_TX_WRAPPER_COAL_SLAVE_IDLE_BMSK 0x8000 +#define IPA_STATE_TX_WRAPPER_COAL_SLAVE_IDLE_SHFT 0xf +#define IPA_STATE_TX_WRAPPER_COAL_DIRECT_DMA_BMSK 0x6000 +#define IPA_STATE_TX_WRAPPER_COAL_DIRECT_DMA_SHFT 0xd +#define IPA_STATE_TX_WRAPPER_NLO_DIRECT_DMA_BMSK 0x1800 +#define IPA_STATE_TX_WRAPPER_NLO_DIRECT_DMA_SHFT 0xb +#define IPA_STATE_TX_WRAPPER_PKT_DROP_CNT_IDLE_BMSK 0x400 +#define IPA_STATE_TX_WRAPPER_PKT_DROP_CNT_IDLE_SHFT 0xa +#define IPA_STATE_TX_WRAPPER_TRNSEQ_FORCE_VALID_BMSK 0x200 +#define IPA_STATE_TX_WRAPPER_TRNSEQ_FORCE_VALID_SHFT 0x9 +#define IPA_STATE_TX_WRAPPER_MBIM_DIRECT_DMA_BMSK 0x180 +#define IPA_STATE_TX_WRAPPER_MBIM_DIRECT_DMA_SHFT 0x7 +#define IPA_STATE_TX_WRAPPER_IPA_MBIM_PKT_FMS_IDLE_BMSK 0x40 +#define IPA_STATE_TX_WRAPPER_IPA_MBIM_PKT_FMS_IDLE_SHFT 0x6 +#define IPA_STATE_TX_WRAPPER_IPA_PROD_BRESP_TOGGLE_IDLE_BMSK 0x20 +#define IPA_STATE_TX_WRAPPER_IPA_PROD_BRESP_TOGGLE_IDLE_SHFT 0x5 +#define IPA_STATE_TX_WRAPPER_IPA_PROD_BRESP_EMPTY_BMSK 0x10 +#define IPA_STATE_TX_WRAPPER_IPA_PROD_BRESP_EMPTY_SHFT 0x4 +#define IPA_STATE_TX_WRAPPER_IPA_PROD_ACKMNGR_STATE_IDLE_BMSK 0x8 +#define IPA_STATE_TX_WRAPPER_IPA_PROD_ACKMNGR_STATE_IDLE_SHFT 0x3 +#define IPA_STATE_TX_WRAPPER_IPA_PROD_ACKMNGR_DB_EMPTY_BMSK 0x4 +#define IPA_STATE_TX_WRAPPER_IPA_PROD_ACKMNGR_DB_EMPTY_SHFT 0x2 +#define IPA_STATE_TX_WRAPPER_TX1_IDLE_BMSK 0x2 +#define IPA_STATE_TX_WRAPPER_TX1_IDLE_SHFT 0x1 +#define IPA_STATE_TX_WRAPPER_TX0_IDLE_BMSK 0x1 +#define IPA_STATE_TX_WRAPPER_TX0_IDLE_SHFT 0x0 + +#define IPA_STATE_TX_WRAPPER_COAL_SLAVE_OPEN_FRAME_BMSK_v4_7 0xf0000000 +#define IPA_STATE_TX_WRAPPER_COAL_SLAVE_OPEN_FRAME_SHFT_v4_7 28 +#define IPA_STATE_TX_WRAPPER_COAL_SLAVE_CTX_IDLE_BMSK_v4_7 0x80000 +#define IPA_STATE_TX_WRAPPER_COAL_SLAVE_CTX_IDLE_SHFT_v4_7 19 +#define IPA_STATE_TX_WRAPPER_COAL_SLAVE_IDLE_BMSK_v4_7 0x40000 +#define IPA_STATE_TX_WRAPPER_COAL_SLAVE_IDLE_SHFT_v4_7 18 +#define IPA_STATE_TX_WRAPPER_IPA_PROD_BRESP_EMPTY_BMSK_v4_7 0x10 +#define IPA_STATE_TX_WRAPPER_IPA_PROD_BRESP_EMPTY_SHFT_v4_7 4 +#define IPA_STATE_TX_WRAPPER_IPA_PROD_ACKMNGR_STATE_IDLE_BMSK_v4_7 0x8 +#define IPA_STATE_TX_WRAPPER_IPA_PROD_ACKMNGR_STATE_IDLE_SHFT_v4_7 3 +#define IPA_STATE_TX_WRAPPER_IPA_PROD_ACKMNGR_DB_EMPTY_BMSK_v4_7 0x4 +#define IPA_STATE_TX_WRAPPER_IPA_PROD_ACKMNGR_DB_EMPTY_SHFT_v4_7 2 +#define IPA_STATE_TX_WRAPPER_TX1_IDLE_BMSK_v4_7 0x2 +#define IPA_STATE_TX_WRAPPER_TX1_IDLE_SHFT_v4_7 1 +#define IPA_STATE_TX_WRAPPER_TX0_IDLE_BMSK_v4_7 0x1 +#define IPA_STATE_TX_WRAPPER_TX0_IDLE_SHFT_v4_7 0 + +/* IPA 5.0 */ + +#define IPA_FLAVOR_0_IPA_PROD_LOWEST_BMSK 0xFF000000 +#define IPA_FLAVOR_0_IPA_PROD_LOWEST_SHFT 24 +#define IPA_FLAVOR_0_IPA_PROD_PIPES_BMSK 0xFF0000 +#define IPA_FLAVOR_0_IPA_PROD_PIPES_SHFT 16 +#define IPA_FLAVOR_0_IPA_CONS_PIPES_BMSK 0xFF00 +#define IPA_FLAVOR_0_IPA_CONS_PIPES_SHFT 8 +#define IPA_FLAVOR_0_IPA_PIPES_BMSK 0xFF +#define IPA_FLAVOR_0_IPA_PIPES_SHFT 0 + +#define IPA_FLAVOR_9_IPA_TSP_MAX_PROD_BMSK 0xFF0000 +#define IPA_FLAVOR_9_IPA_TSP_MAX_PROD_SHFT 16 +#define IPA_FLAVOR_9_IPA_TSP_MAX_EGR_TC_BMSK 0xFF00 +#define IPA_FLAVOR_9_IPA_TSP_MAX_EGR_TC_SHFT 8 +#define IPA_FLAVOR_9_IPA_TSP_MAX_INGR_TC_BMSK 0xFF +#define IPA_FLAVOR_9_IPA_TSP_MAX_INGR_TC_SHFT 0 + +#define IPA_STATE_TSP_TRAFFIC_SHAPER_IDLE_BMSK 0x1 +#define IPA_STATE_TSP_TRAFFIC_SHAPER_IDLE_SHFT 0 +#define IPA_STATE_TSP_TRAFFIC_SHAPER_FIFO_EMPTY_BMSK 0x2 +#define IPA_STATE_TSP_TRAFFIC_SHAPER_FIFO_EMPTY_SHFT 1 +#define IPA_STATE_TSP_QUEUE_MNGR_IDLE_BMSK 0x4 +#define IPA_STATE_TSP_QUEUE_MNGR_IDLE_SHFT 2 +#define IPA_STATE_TSP_QUEUE_MNGR_HEAD_IDLE_BMSK 0x8 +#define IPA_STATE_TSP_QUEUE_MNGR_HEAD_IDLE_SHFT 3 +#define IPA_STATE_TSP_QUEUE_MNGR_SHARED_IDLE_BMSK 0x10 +#define IPA_STATE_TSP_QUEUE_MNGR_SHARED_IDLE_SHFT 4 +#define IPA_STATE_TSP_QUEUE_MNGR_TAIL_IDLE_BMSK 0x20 +#define IPA_STATE_TSP_QUEUE_MNGR_TAIL_IDLE_SHFT 6 +#define IPA_STATE_TSP_QUEUE_MNGR_BLOCK_CTRL_IDLE_BMSK 0x40 +#define IPA_STATE_TSP_QUEUE_MNGR_BLOCK_CTRL_IDLE_SHFT 7 + +#define IPA_COMP_CFG_GEN_QMB_0_DYNAMIC_ASIZE_BMSK_v5_0 0x80000000 +#define IPA_COMP_CFG_GEN_QMB_0_DYNAMIC_ASIZE_SHFT_v5_0 31 +#define IPA_COMP_CFG_GEN_QMB_1_DYNAMIC_ASIZE_BMSK_v5_0 0x40000000 +#define IPA_COMP_CFG_GEN_QMB_1_DYNAMIC_ASIZE_SHFT_v5_0 30 +#define IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_BMSK_v5_0 0xFC00000 +#define IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_SHFT_v5_0 22 +#define IPA_COMP_CFG_GSI_IF_OUT_OF_BUF_STOP_RESET_MASK_ENABLE_BMSK_v5_0 0x200000 +#define IPA_COMP_CFG_GSI_IF_OUT_OF_BUF_STOP_RESET_MASK_ENABLE_SHFT_v5_0 21 +#define IPA_COMP_CFG_GENQMB_AOOOWR_BMSK_v5_0 0x100000 +#define IPA_COMP_CFG_GENQMB_AOOOWR_SHFT_v5_0 20 +#define IPA_COMP_CFG_QMB_RAM_RD_CACHE_DISABLE_BMSK_v5_0 0x80000 +#define IPA_COMP_CFG_QMB_RAM_RD_CACHE_DISABLE_SHFT_v5_0 19 +#define IPA_COMP_CFG_IPA_FULL_FLUSH_WAIT_RSC_CLOSURE_EN_BMSK_v5_0 0x20000 +#define IPA_COMP_CFG_IPA_FULL_FLUSH_WAIT_RSC_CLOSURE_EN_SHFT_v5_0 17 +#define IPA_COMP_CFG_RAM_ARB_PRIORITY_CLIENT_SAMP_FIX_DISABLE_BMSK_v5_0 0x1 +#define IPA_COMP_CFG_RAM_ARB_PRIORITY_CLIENT_SAMP_FIX_DISABLE_SHFT_v5_0 0 + +/* IPA_RSRC_GRP_CFG register */ +#define IPA_RSRC_GRP_CFG_SRC_GRP_SPECIAL_VALID_BMSK 0x1 +#define IPA_RSRC_GRP_CFG_SRC_GRP_SPECIAL_VALID_SHFT 0 +#define IPA_RSRC_GRP_CFG_SRC_GRP_SPECIAL_INDEX_BMSK 0x70 +#define IPA_RSRC_GRP_CFG_SRC_GRP_SPECIAL_INDEX_SHFT 4 +#define IPA_RSRC_GRP_CFG_DST_PIPE_SPECIAL_VALID_BMSK 0x100 +#define IPA_RSRC_GRP_CFG_DST_PIPE_SPECIAL_VALID_SHFT 8 +#define IPA_RSRC_GRP_CFG_DST_PIPE_SPECIAL_INDEX_BMSK 0xFF000 +#define IPA_RSRC_GRP_CFG_DST_PIPE_SPECIAL_INDEX_SHFT 12 +#define IPA_RSRC_GRP_CFG_DST_GRP_SPECIAL_VALID_BMSK 0x100000 +#define IPA_RSRC_GRP_CFG_DST_GRP_SPECIAL_VALID_SHFT 20 +#define IPA_RSRC_GRP_CFG_DST_GRP_SPECIAL_INDEX_BMSK 0x3F000000 +#define IPA_RSRC_GRP_CFG_DST_GRP_SPECIAL_INDEX_SHFT 24 + +/* IPA_RSRC_GRP_CFG_EXT register */ +#define IPA_RSRC_GRP_CFG_EXT_SRC_GRP_2ND_PRIORITY_SPECIAL_VALID_BMSK 0x0 +#define IPA_RSRC_GRP_CFG_EXT_SRC_GRP_2ND_PRIORITY_SPECIAL_VALID_SHFT 1 +#define IPA_RSRC_GRP_CFG_EXT_SRC_GRP_2ND_PRIORITY_SPECIAL_INDEX_BMSK 0x70 +#define IPA_RSRC_GRP_CFG_EXT_SRC_GRP_2ND_PRIORITY_SPECIAL_INDEX_SHFT 4 + +/* IPA_ULSO registers */ + +/* IPA_ULSO_CFG_IP_ID_MIN_VALUE_n register */ +#define IPA_ULSO_CFG_IP_ID_MIN_VALUE_n_IP_ID_MIN_VALUE_BMSK 0xffff +#define IPA_ULSO_CFG_IP_ID_MIN_VALUE_n_IP_ID_MIN_VALUE_SHFT 0 + + /* IPA_ULSO_CFG_IP_ID_MAX_VALUE_n register */ +#define IPA_ULSO_CFG_IP_ID_MAX_VALUE_n_IP_ID_MAX_VALUE_BMSK 0xffff +#define IPA_ULSO_CFG_IP_ID_MAX_VALUE_n_IP_ID_MAX_VALUE_SHFT 0 + + /* IPA_ENDP_INIT_ULSO_CFG_n register */ +#define IPA_ENDP_INIT_ULSO_CFG_n_IPV4_ID_MIN_MAX_VAL_INDEX_BMSK 0x3 +#define IPA_ENDP_INIT_ULSO_CFG_n_IPV4_ID_MIN_MAX_VAL_INDEX_SHFT 0 + +/* IPA 5.5 */ +/* IPA_COAL registers*/ +#define IPA_COAL_VP_LRU_TCP_NUM_BMSK_v5_5 0xF8000 +#define IPA_COAL_VP_LRU_TCP_NUM_SHFT_v5_5 15 +#define IPA_COAL_VP_LRU_TCP_THRSHLD_EN_BMSK_v5_5 0x4000 +#define IPA_COAL_VP_LRU_TCP_THRSHLD_EN_SHFT_v5_5 14 +#define IPA_COAL_VP_LRU_UDP_THRSHLD_EN_BMSK_v5_5 0x2000 +#define IPA_COAL_VP_LRU_UDP_THRSHLD_EN_SHFT_v5_5 13 +#define IPA_COAL_VP_LRU_TCP_THRSHLD_BMSK_v5_5 0x1F00 +#define IPA_COAL_VP_LRU_TCP_THRSHLD_SHFT_v5_5 8 +#define IPA_COAL_VP_LRU_UDP_THRSHLD_BMSK_v5_5 0xF8 +#define IPA_COAL_VP_LRU_UDP_THRSHLD_SHFT_v5_5 3 +#define IPA_COAL_VP_LRU_GRAN_SEL_BMSK_v5_5 0x6 +#define IPA_COAL_VP_LRU_GRAN_SEL_SHFT_v5_5 1 +#define IPA_COAL_EVICTION_EN_BMSK_v5_5 0x1 +#define IPA_COAL_EVICTION_EN_SHFT_v5_5 0 + +/* IPA_COAL_MASTER_CFG */ +#define IPA_COAL_MASTER_CFG_IPV4_ID_IGNORE_EN_BMSK 0x4 +#define IPA_COAL_MASTER_CFG_IPV4_ID_IGNORE_EN_SHFT 2 +#define IPA_COAL_MASTER_CFG_ENHANCED_IPV4_ID_EN_BMSK 0x2 +#define IPA_COAL_MASTER_CFG_ENHANCED_IPV4_ID_EN_SHFT 1 +#define IPA_COAL_MASTER_CFG_FORCE_TO_DEFAULT_EN_BMSK 0x1 +#define IPA_COAL_MASTER_CFG_FORCE_TO_DEFAULT_EN_SHFT 0 + +/* IPA_ENDP_INIT_NAT_EXC_SUPPRESS_n register */ +#define IPA_ENDP_INIT_NAT_EXC_SUPPRESS_n_EN_BMSK 0x1 +#define IPA_ENDP_INIT_NAT_EXC_SUPPRESS_n_EN_SHFT 0x0 + +#endif /* _IPAHAL_REG_I_H_ */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_tsp.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_tsp.c new file mode 100644 index 0000000000..948ab23cfd --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_tsp.c @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + + +#include "ipa_tsp.h" +#include "ipahal_i.h" +#include "ipahal_tsp_i.h" +#include "ipahal_reg.h" +#include "ipahal_tsp.h" + + +void ipahal_tsp_fill_hw_ingr_tc(const struct ipa_ioc_tsp_ingress_class_params *input, + void *table, u8 index) +{ + /* The first index is 1 */ + struct ipahal_tsp_ingress_class *hal_ingr_tc = + (struct ipahal_tsp_ingress_class *)table + index - 1; + + hal_ingr_tc->max_rate = input->max_rate; + hal_ingr_tc->max_burst = input->max_burst; + hal_ingr_tc->max_bucket = input->max_burst; + hal_ingr_tc->last_rtc = 0x0; +} + +void ipahal_tsp_fill_hw_egr_ep(const struct ipa_ioc_tsp_egress_prod_params *input, + void *table, u8 index) +{ + union ipahal_tsp_egress_prod *hal_egr_ep = + (union ipahal_tsp_egress_prod *)table + index; + + if ((index & 0x1)) { + /* even index */ + hal_egr_ep->even.max_rate = input->max_rate; + hal_egr_ep->even.max_freq = 65536 / input->max_rate; + hal_egr_ep->even.max_burst = input->max_burst; + hal_egr_ep->even.max_bucket = input->max_burst; + hal_egr_ep->even.last_rtc = 0x0; + } else { + /* odd index */ + hal_egr_ep->odd.max_rate = input->max_rate; + hal_egr_ep->odd.max_freq = 65536 / input->max_rate; + hal_egr_ep->odd.max_burst = input->max_burst; + hal_egr_ep->odd.max_bucket = input->max_burst; + hal_egr_ep->odd.last_rtc = 0x0; + } +} + +void ipahal_tsp_fill_hw_egr_tc(const struct ipa_ioc_tsp_egress_class_params *input, + void *table, u8 index) +{ + /* The first index is 1 */ + union ipahal_tsp_egress_class *hal_egr_tc = + (union ipahal_tsp_egress_class *)table + index - 1; + + if (!(index & 0x1)) { + /* even index */ + hal_egr_tc->even.guaranteed_rate = input->guaranteed_rate; + hal_egr_tc->even.max_rate = input->max_rate; + hal_egr_tc->even.guaranteed_freq = 65536 / input->guaranteed_rate; + hal_egr_tc->even.max_freq = 65536 / input->max_rate; + hal_egr_tc->even.guaranteed_burst = input->guaranteed_burst; + hal_egr_tc->even.max_burst = input->max_burst; + hal_egr_tc->even.max_bucket = input->max_burst; + hal_egr_tc->even.last_rtc = 0x0; + } else { + /* odd index */ + hal_egr_tc->odd.guaranteed_rate = input->guaranteed_rate; + hal_egr_tc->odd.max_rate = input->max_rate; + hal_egr_tc->odd.guaranteed_freq = 65536 / input->guaranteed_rate; + hal_egr_tc->odd.max_freq = 65536 / input->max_rate; + hal_egr_tc->odd.guaranteed_burst = input->guaranteed_burst; + hal_egr_tc->odd.max_burst = input->max_burst; + hal_egr_tc->odd.max_bucket = input->max_burst; + hal_egr_tc->odd.last_rtc = 0x0; + } +} + +void ipahal_tsp_parse_hw_ingr_tc(const void *table, u8 index, + struct ipa_ioc_tsp_ingress_class_params *output) +{ + /* The first index is 1 */ + struct ipahal_tsp_ingress_class *hal_ingr_tc = + (struct ipahal_tsp_ingress_class *)table + index - 1; + + output->max_rate = hal_ingr_tc->max_rate; + output->max_burst = hal_ingr_tc->max_burst; +} + +void ipahal_tsp_parse_hw_egr_tc(const void *table, u8 index, + struct ipa_ioc_tsp_egress_class_params *output) +{ + /* The first index is 1 */ + union ipahal_tsp_egress_class *hal_egr_tc = + (union ipahal_tsp_egress_class *)table + index - 1; + + if (!(index & 0x1)) { + /* even index */ + output->guaranteed_rate = hal_egr_tc->even.guaranteed_rate; + output->max_rate = hal_egr_tc->even.max_rate; + output->guaranteed_burst = hal_egr_tc->even.guaranteed_burst; + output->max_burst = hal_egr_tc->even.max_burst; + } else { + /* odd index */ + output->guaranteed_rate = hal_egr_tc->odd.guaranteed_rate; + output->max_rate = hal_egr_tc->odd.max_rate; + output->guaranteed_burst = hal_egr_tc->odd.guaranteed_burst; + output->max_burst = hal_egr_tc->odd.max_burst; + } +} + +void ipahal_tsp_parse_hw_egr_ep(const void *table, u8 index, + struct ipa_ioc_tsp_egress_prod_params *output) +{ + union ipahal_tsp_egress_prod *hal_egr_ep = + (union ipahal_tsp_egress_prod *)table + index; + + if ((index & 0x1)) { + /* even index */ + output->max_rate = hal_egr_ep->even.max_rate; + output->max_burst = hal_egr_ep->even.max_burst; + } else { + /* odd index */ + output->max_rate = hal_egr_ep->odd.max_rate; + output->max_burst = hal_egr_ep->odd.max_burst; + } +} diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_tsp.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_tsp.h new file mode 100644 index 0000000000..1ec92bcd47 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_tsp.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _IPAHAL_TSP_H_ +#define _IPAHAL_TSP_H_ + +#include +#include "ipa_tsp.h" + +#define IPA_TSP_IN_TC_NUM 16 // TBD: Get rid of it + +#define IPA_TSP_INGR_TC_SIZE 8 +#define IPA_TSP_EGR_EP_SIZE 12 +#define IPA_TSP_EGR_TC_SIZE 20 + + +void ipahal_tsp_fill_hw_ingr_tc(const struct ipa_ioc_tsp_ingress_class_params *input, + void *table, u8 index); +void ipahal_tsp_fill_hw_egr_ep(const struct ipa_ioc_tsp_egress_prod_params *input, + void *table, u8 index); +void ipahal_tsp_fill_hw_egr_tc(const struct ipa_ioc_tsp_egress_class_params *input, + void *table, u8 index); +void ipahal_tsp_parse_hw_ingr_tc(const void *table, u8 index, + struct ipa_ioc_tsp_ingress_class_params *output); +void ipahal_tsp_parse_hw_egr_ep(const void *table, u8 index, + struct ipa_ioc_tsp_egress_prod_params *output); +void ipahal_tsp_parse_hw_egr_tc(const void *table, u8 index, + struct ipa_ioc_tsp_egress_class_params *output); + +#endif /* _IPAHAL_TSP_H_ */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_tsp_i.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_tsp_i.h new file mode 100644 index 0000000000..1ffae6542c --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_tsp_i.h @@ -0,0 +1,167 @@ + +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _IPAHAL_TSP_I_H_ +#define _IPAHAL_TSP_I_H_ + +/** +* struct ipahal_tsp_ingress_class - IPA Ingress traffic-class +* +* @last_rtc: For HW use, initialize to 0x0000 +* @max_bucket: For HW use, initialize to same value as max_burst +* @max_burst: Maximal-burst allowed in bytes +* @max_rate: Maximal bandwidth rate for matching ingress traffic-class in 1.2MB/second units +*/ +struct ipahal_tsp_ingress_class { + u16 last_rtc; + u16 max_bucket; + u16 max_burst; + u16 max_rate; +}; + +/** + * struct ipahal_tsp_egress_prod_even - IPA TSP-enabled producer (even index) + * + * @last_rtc: For HW use, initialize to 0x0000 + * @max_bucket: For HW use, initialize to same value as max_burst + * @max_rate: Maximal bandwidth rate for producer in 1.2MB/second units + * @max_freq: In units of 0.833*usec/64KB. Claculated as: + * MAX-Freq = 65536/max_rate (always be rounded up) + * @max_burst: Maximal-burst allowed in bytes + * @reserved: Reserved + */ +struct ipahal_tsp_egress_prod_even { + u16 last_rtc; + u16 max_bucket; + u16 max_rate; + u16 max_freq; + u16 max_burst; + u16 reserved; +}; + +/** + * struct ipahal_tsp_egress_prod_odd - IPA TSP-enabled producer (odd index) + * + * @reserved: Reserved + * @max_burst: Maximal-burst allowed in bytes + * @last_rtc: For HW use, initialize to 0x0000 + * @max_bucket: For HW use, initialize to same value as max_burst + * @max_rate: Maximal bandwidth rate for producer in 1.2MB/second units + * @max_freq: In units of 0.833*usec/64KB. Claculated as: + * MAX-Freq = 65536/max_rate (always be rounded up) + */ +struct ipahal_tsp_egress_prod_odd { + u16 reserved; + u16 max_burst; + u16 last_rtc; + u16 max_bucket; + u16 max_rate; + u16 max_freq; +}; + +/** + * union ipahal_tsp_egress_prod - IPA TSP-enabled producer (even or odd) + * + * @even: TSP-enabled producer (even index) + * @odd: TSP-enabled producer (odd index) + */ +union ipahal_tsp_egress_prod { + struct ipahal_tsp_egress_prod_even even; + struct ipahal_tsp_egress_prod_odd odd; +}; + +/** + * struct ipahal_tsp_egress_prod_pair - IPA TSP-enabled producer pair (even and odd) + * + * @even: TSP-enabled producer (even index) + * @odd: TSP-enabled producer (odd index) + */ +struct ipahal_tsp_egress_prod_pair { + struct ipahal_tsp_egress_prod_even even; + struct ipahal_tsp_egress_prod_odd odd; +}; + +/** + * struct ipahal_tsp_egress_class_even - IPA egress traffic-class (even index) + * + * @last_rtc: For HW use, initialize to 0x0000 + * @reserved: Reserved + * @guaranteed_bucket: For HW use, initialize to same value as guaranteed_burst + * @max_bucket: For HW use, initialize to same value as max_burst + * @guaranteed_rate: Guaranteed bandwidth rate for traffic-class in 1.2MB/second units + * @max_rate: Maximal bandwidth rate for traffic-class in 1.2MB/second units + * @guaranteed_freq: In units of 0.833*usec/64KB, Calculated as: + * guaranteed_freq = 65536/guaranteed_rate (always be rounded up) + * @max_freq: In units of 0.833*usec/64KB, Calculated as: + * max_freq = 65536/max_rate (always be rounded up) + * @guaranteed_burst: Maximal-burst allowed for guaranteed bandwidth rate (in bytes) + * @max_burst: Maximal-burst allowed for maximal bandwidth rate (in bytes) + */ +struct ipahal_tsp_egress_class_even { + u16 last_rtc; + u16 reserved; + u16 guaranteed_bucket; + u16 max_bucket; + u16 guaranteed_rate; + u16 max_rate; + u16 guaranteed_freq; + u16 max_freq; + u16 guaranteed_burst; + u16 max_burst; +}; + +/** + * struct ipahal_tsp_egress_class_odd - IPA egress traffic-class (odd index) + * + * @guaranteed_burst: Maximal-burst allowed for guaranteed bandwidth rate (in bytes) + * @max_burst: Maximal-burst allowed for maximal bandwidth rate (in bytes) + * @last_rtc: For HW use, initialize to 0x0000 + * @reserved: Reserved + * @guaranteed_bucket: For HW use, initialize to same value as guaranteed_burst + * @max_bucket: For HW use, initialize to same value as max_burst + * @guaranteed_rate: Guaranteed bandwidth rate for traffic-class in 1.2MB/second units + * @max_rate: Maximal bandwidth rate for traffic-class in 1.2MB/second units + * @guaranteed_freq: In units of 0.833*usec/64KB, Calculated as: + * guaranteed_freq = 65536/guaranteed_rate (always be rounded up) + * @max_freq: In units of 0.833*usec/64KB, Calculated as: + * max_freq = 65536/max_rate (always be rounded up) + */ +struct ipahal_tsp_egress_class_odd { + u16 guaranteed_burst; + u16 max_burst; + u16 last_rtc; + u16 reserved; + u16 guaranteed_bucket; + u16 max_bucket; + u16 guaranteed_rate; + u16 max_rate; + u16 guaranteed_freq; + u16 max_freq; +}; + +/** + * union ipahal_tsp_egress_prod - IPA egress traffic-class (even or odd) + * + * @even: egress traffic-class (even index) + * @odd: egress traffic-class (odd index) + */ +union ipahal_tsp_egress_class { + struct ipahal_tsp_egress_class_even even; + struct ipahal_tsp_egress_class_odd odd; +}; + +/** + * struct ipahal_tsp_egress_prod_pair - IPA egress traffic-class pair (even and odd) + * + * @even: egress traffic-class (even index) + * @odd: egress traffic-class (odd index) + */ +struct ipahal_tsp_egress_class_pair { + struct ipahal_tsp_egress_class_even even; + struct ipahal_tsp_egress_class_odd odd; +}; + +#endif /* _IPAHAL_TSP_I_H_ */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/rmnet_ctl_ipa.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/rmnet_ctl_ipa.c new file mode 100644 index 0000000000..ab1a2d8add --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/rmnet_ctl_ipa.c @@ -0,0 +1,752 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include "ipa.h" +#include +#include "ipa_i.h" + +enum ipa_rmnet_ctl_state { + IPA_RMNET_CTL_NOT_REG, + IPA_RMNET_CTL_REGD, /* rmnet_ctl register */ + IPA_RMNET_CTL_PIPE_READY, /* sys pipe setup */ + IPA_RMNET_CTL_START, /* rmnet_ctl register + pipe setup */ +}; + +#define IPA_RMNET_CTL_PIPE_NOT_READY (0) +#define IPA_RMNET_CTL_PIPE_TX_READY (1 << 0) +#define IPA_RMNET_CTL_PIPE_RX_READY (1 << 1) +#define IPA_RMNET_CTL_PIPE_READY_ALL (IPA_RMNET_CTL_PIPE_TX_READY | \ + IPA_RMNET_CTL_PIPE_RX_READY) /* TX Ready + RX ready */ + + +#define IPA_WWAN_CONS_DESC_FIFO_SZ 256 +#define RMNET_CTRL_QUEUE_MAX (2 * IPA_WWAN_CONS_DESC_FIFO_SZ) + +struct ipa3_rmnet_ctl_cb_info { + ipa_rmnet_ctl_ready_cb ready_cb; + ipa_rmnet_ctl_stop_cb stop_cb; + ipa_rmnet_ctl_rx_notify_cb rx_notify_cb; + void *ready_cb_user_data; + void *stop_cb_user_data; + void *rx_notify_cb_user_data; +}; + +struct ipa3_rmnet_ctl_stats { + atomic_t outstanding_pkts; + u32 tx_pkt_sent; + u32 rx_pkt_rcvd; + u64 tx_byte_sent; + u64 rx_byte_rcvd; + u32 tx_pkt_dropped; + u32 rx_pkt_dropped; + u64 tx_byte_dropped; + u64 rx_byte_dropped; +}; + +struct rmnet_ctl_ipa3_context { + struct ipa3_rmnet_ctl_stats stats; + enum ipa_rmnet_ctl_state state; + u8 pipe_state; + struct ipa_sys_connect_params apps_to_ipa_low_lat_ep_cfg; + struct ipa_sys_connect_params ipa_to_apps_low_lat_ep_cfg; + u32 apps_to_ipa3_low_lat_hdl; + u32 ipa3_to_apps_low_lat_hdl; + spinlock_t tx_lock; + struct ipa3_rmnet_ctl_cb_info cb_info; + struct sk_buff_head tx_queue; + u32 rmnet_ctl_pm_hdl; + struct mutex lock; + struct workqueue_struct *wq; +}; + +static struct rmnet_ctl_ipa3_context *rmnet_ctl_ipa3_ctx; + +static void rmnet_ctl_wakeup_ipa(struct work_struct *work); +static DECLARE_DELAYED_WORK(rmnet_ctl_wakeup_work, + rmnet_ctl_wakeup_ipa); +static void apps_rmnet_ctl_tx_complete_notify(void *priv, + enum ipa_dp_evt_type evt, unsigned long data); +static void apps_rmnet_ctl_receive_notify(void *priv, + enum ipa_dp_evt_type evt, unsigned long data); +static int ipa3_rmnet_ctl_register_pm_client(void); +static void ipa3_rmnet_ctl_deregister_pm_client(void); + +int ipa3_rmnet_ctl_init(void) +{ + char buff[IPA_RESOURCE_NAME_MAX]; + + if (!ipa3_ctx) { + IPAERR("ipa3_ctx was not initialized\n"); + return -EINVAL; + } + + if (ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_LOW_LAT_PROD) == -1 || + ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_LOW_LAT_CONS) == -1) + { + IPAERR("invalid low lat endpoints\n"); + return -EINVAL; + } + + rmnet_ctl_ipa3_ctx = kzalloc(sizeof(*rmnet_ctl_ipa3_ctx), + GFP_KERNEL); + + if (!rmnet_ctl_ipa3_ctx) + return -ENOMEM; + + snprintf(buff, IPA_RESOURCE_NAME_MAX, "rmnet_ctlwq"); + rmnet_ctl_ipa3_ctx->wq = alloc_workqueue(buff, + WQ_MEM_RECLAIM | WQ_UNBOUND | WQ_SYSFS, 1); + if (!rmnet_ctl_ipa3_ctx->wq) { + kfree(rmnet_ctl_ipa3_ctx); + rmnet_ctl_ipa3_ctx = NULL; + return -ENOMEM; + } + memset(&rmnet_ctl_ipa3_ctx->apps_to_ipa_low_lat_ep_cfg, 0, + sizeof(struct ipa_sys_connect_params)); + memset(&rmnet_ctl_ipa3_ctx->ipa_to_apps_low_lat_ep_cfg, 0, + sizeof(struct ipa_sys_connect_params)); + skb_queue_head_init(&rmnet_ctl_ipa3_ctx->tx_queue); + rmnet_ctl_ipa3_ctx->state = IPA_RMNET_CTL_NOT_REG; + mutex_init(&rmnet_ctl_ipa3_ctx->lock); + spin_lock_init(&rmnet_ctl_ipa3_ctx->tx_lock); + rmnet_ctl_ipa3_ctx->pipe_state = IPA_RMNET_CTL_PIPE_NOT_READY; + return 0; +} + +int ipa_register_rmnet_ctl_cb( + void (*ipa_rmnet_ctl_ready_cb)(void *user_data1), + void *user_data1, + void (*ipa_rmnet_ctl_stop_cb)(void *user_data2), + void *user_data2, + void (*ipa_rmnet_ctl_rx_notify_cb)( + void *user_data3, void *rx_data), + void *user_data3) +{ + /* check ipa3_ctx existed or not */ + if (!ipa3_ctx) { + IPADBG("rmnet_ctl_ctx haven't initialized\n"); + return -EAGAIN; + } + + if (!ipa3_ctx->rmnet_ctl_enable) { + IPAERR("low lat pipes are not supported"); + return -ENXIO; + } + + if (!rmnet_ctl_ipa3_ctx) { + IPADBG("rmnet_ctl_ctx haven't initialized\n"); + return -EAGAIN; + } + + mutex_lock(&rmnet_ctl_ipa3_ctx->lock); + if (rmnet_ctl_ipa3_ctx->state != IPA_RMNET_CTL_NOT_REG && + rmnet_ctl_ipa3_ctx->state != IPA_RMNET_CTL_PIPE_READY) { + IPADBG("rmnet_ctl registered already\n"); + mutex_unlock(&rmnet_ctl_ipa3_ctx->lock); + return -EEXIST; + } + rmnet_ctl_ipa3_ctx->cb_info.ready_cb = ipa_rmnet_ctl_ready_cb; + rmnet_ctl_ipa3_ctx->cb_info.ready_cb_user_data = user_data1; + rmnet_ctl_ipa3_ctx->cb_info.stop_cb = ipa_rmnet_ctl_stop_cb; + rmnet_ctl_ipa3_ctx->cb_info.stop_cb_user_data = user_data2; + rmnet_ctl_ipa3_ctx->cb_info.rx_notify_cb = ipa_rmnet_ctl_rx_notify_cb; + rmnet_ctl_ipa3_ctx->cb_info.rx_notify_cb_user_data = user_data3; + if (rmnet_ctl_ipa3_ctx->state == IPA_RMNET_CTL_NOT_REG) { + rmnet_ctl_ipa3_ctx->state = IPA_RMNET_CTL_REGD; + } else { + (*ipa_rmnet_ctl_ready_cb)(user_data1); + rmnet_ctl_ipa3_ctx->state = IPA_RMNET_CTL_START; + } + ipa3_rmnet_ctl_register_pm_client(); + mutex_unlock(&rmnet_ctl_ipa3_ctx->lock); + IPADBG("rmnet_ctl registered successfually\n"); + return 0; +} +EXPORT_SYMBOL(ipa_register_rmnet_ctl_cb); + +int ipa_unregister_rmnet_ctl_cb(void) +{ + /* check ipa3_ctx existed or not */ + if (!ipa3_ctx) { + IPADBG("IPA driver haven't initialized\n"); + return -EAGAIN; + } + + if (!ipa3_ctx->rmnet_ctl_enable) { + IPAERR("low lat pipe is disabled"); + return -ENXIO; + } + + if (!rmnet_ctl_ipa3_ctx) { + IPADBG("rmnet_ctl_ctx haven't initialized\n"); + return -EAGAIN; + } + + mutex_lock(&rmnet_ctl_ipa3_ctx->lock); + if (rmnet_ctl_ipa3_ctx->state != IPA_RMNET_CTL_REGD && + rmnet_ctl_ipa3_ctx->state != IPA_RMNET_CTL_START) { + IPADBG("rmnet_ctl unregistered already\n"); + mutex_unlock(&rmnet_ctl_ipa3_ctx->lock); + return 0; + } + rmnet_ctl_ipa3_ctx->cb_info.ready_cb = NULL; + rmnet_ctl_ipa3_ctx->cb_info.ready_cb_user_data = NULL; + rmnet_ctl_ipa3_ctx->cb_info.stop_cb = NULL; + rmnet_ctl_ipa3_ctx->cb_info.stop_cb_user_data = NULL; + rmnet_ctl_ipa3_ctx->cb_info.rx_notify_cb = NULL; + rmnet_ctl_ipa3_ctx->cb_info.rx_notify_cb_user_data = NULL; + if (rmnet_ctl_ipa3_ctx->state == IPA_RMNET_CTL_REGD) + rmnet_ctl_ipa3_ctx->state = IPA_RMNET_CTL_NOT_REG; + else + rmnet_ctl_ipa3_ctx->state = IPA_RMNET_CTL_PIPE_READY; + + ipa3_rmnet_ctl_deregister_pm_client(); + mutex_unlock(&rmnet_ctl_ipa3_ctx->lock); + + IPADBG("rmnet_ctl unregistered successfually\n"); + return 0; +} +EXPORT_SYMBOL(ipa_unregister_rmnet_ctl_cb); + +int ipa3_setup_apps_low_lat_cons_pipe(bool rmnet_config, + struct rmnet_ingress_param *ingress_param) +{ + struct ipa_sys_connect_params *ipa_low_lat_ep_cfg; + int ret = 0; + int ep_idx; + + if (!ipa3_ctx->rmnet_ctl_enable) { + IPAERR("low lat pipe is disabled"); + return 0; + } + ep_idx = ipa_get_ep_mapping( + IPA_CLIENT_APPS_WAN_LOW_LAT_CONS); + if (ep_idx == IPA_EP_NOT_ALLOCATED) { + IPADBG("Low lat datapath not supported\n"); + return -ENXIO; + } + if (rmnet_ctl_ipa3_ctx->state != IPA_RMNET_CTL_NOT_REG && + rmnet_ctl_ipa3_ctx->state != IPA_RMNET_CTL_REGD) { + IPADBG("rmnet_ctl in bad state %d\n", + rmnet_ctl_ipa3_ctx->state); + return -ENXIO; + } + ipa_low_lat_ep_cfg = + &rmnet_ctl_ipa3_ctx->ipa_to_apps_low_lat_ep_cfg; + /* + * Removing bypass aggr from assign_policy + * and placing it here for future enablement + */ + ipa_low_lat_ep_cfg->ipa_ep_cfg.aggr.aggr_en = IPA_BYPASS_AGGR; + if (rmnet_config && ingress_param) { + /* Open for future cs offload disablement on low lat pipe */ + if (ingress_param->cs_offload_en) { + ipa_low_lat_ep_cfg->ipa_ep_cfg.cfg.cs_offload_en = + IPA_ENABLE_CS_DL_QMAP; + } else { + ipa_low_lat_ep_cfg->ipa_ep_cfg.cfg.cs_offload_en = + IPA_DISABLE_CS_OFFLOAD; + } + ipa_low_lat_ep_cfg->ext_ioctl_v2 = true; + ipa_low_lat_ep_cfg->int_modt = ingress_param->int_modt; + ipa_low_lat_ep_cfg->int_modc = ingress_param->int_modc; + ipa_low_lat_ep_cfg->buff_size = ingress_param->buff_size; + ipa_low_lat_ep_cfg->ipa_ep_cfg.aggr.aggr_byte_limit = + ingress_param->agg_byte_limit; + ipa_low_lat_ep_cfg->ipa_ep_cfg.aggr.aggr_pkt_limit = + ingress_param->agg_pkt_limit; + ipa_low_lat_ep_cfg->ipa_ep_cfg.aggr.aggr_time_limit = + ingress_param->agg_time_limit; + } else { + ipa_low_lat_ep_cfg->ext_ioctl_v2 = false; + ipa_low_lat_ep_cfg->ipa_ep_cfg.cfg.cs_offload_en = + IPA_ENABLE_CS_DL_QMAP; + ipa_low_lat_ep_cfg->ipa_ep_cfg.aggr.aggr_byte_limit = + 0; + ipa_low_lat_ep_cfg->ipa_ep_cfg.aggr.aggr_pkt_limit = + 0; + } + + ipa_low_lat_ep_cfg->ipa_ep_cfg.hdr.hdr_len = 8; + ipa_low_lat_ep_cfg->ipa_ep_cfg.hdr.hdr_ofst_metadata_valid + = 1; + ipa_low_lat_ep_cfg->ipa_ep_cfg.hdr.hdr_ofst_metadata + = 1; + ipa_low_lat_ep_cfg->ipa_ep_cfg.hdr.hdr_ofst_pkt_size_valid + = 1; + ipa_low_lat_ep_cfg->ipa_ep_cfg.hdr.hdr_ofst_pkt_size + = 2; + ipa_low_lat_ep_cfg->ipa_ep_cfg.hdr_ext.hdr_total_len_or_pad_valid + = true; + ipa_low_lat_ep_cfg->ipa_ep_cfg.hdr_ext.hdr_total_len_or_pad + = 0; + ipa_low_lat_ep_cfg->ipa_ep_cfg.hdr_ext.hdr_payload_len_inc_padding + = true; + ipa_low_lat_ep_cfg->ipa_ep_cfg.hdr_ext.hdr_total_len_or_pad_offset + = 0; + ipa_low_lat_ep_cfg->ipa_ep_cfg.hdr_ext.hdr_little_endian + = 0; + ipa_low_lat_ep_cfg->ipa_ep_cfg.metadata_mask.metadata_mask + = 0xFF000000; + ipa_low_lat_ep_cfg->client = IPA_CLIENT_APPS_WAN_LOW_LAT_CONS; + ipa_low_lat_ep_cfg->notify = apps_rmnet_ctl_receive_notify; + ipa_low_lat_ep_cfg->priv = NULL; + ipa_low_lat_ep_cfg->desc_fifo_sz = + IPA_WWAN_CONS_DESC_FIFO_SZ * IPA_FIFO_ELEMENT_SIZE; + ret = ipa_setup_sys_pipe( + &rmnet_ctl_ipa3_ctx->ipa_to_apps_low_lat_ep_cfg, + &rmnet_ctl_ipa3_ctx->ipa3_to_apps_low_lat_hdl); + if (ret) { + IPADBG("Low lat pipe setup fails\n"); + return ret; + } + rmnet_ctl_ipa3_ctx->pipe_state |= IPA_RMNET_CTL_PIPE_RX_READY; + if (rmnet_ctl_ipa3_ctx->cb_info.ready_cb) { + (*(rmnet_ctl_ipa3_ctx->cb_info.ready_cb)) + (rmnet_ctl_ipa3_ctx->cb_info.ready_cb_user_data); + } + /* + * if no ready_cb yet, which means rmnet_ctl not + * register to IPA, we will move state to pipe + * ready and will wait for register event + * coming and move to start state. + * The ready_cb will called from regsiter itself. + */ + mutex_lock(&rmnet_ctl_ipa3_ctx->lock); + if (rmnet_ctl_ipa3_ctx->state == IPA_RMNET_CTL_NOT_REG) + rmnet_ctl_ipa3_ctx->state = IPA_RMNET_CTL_PIPE_READY; + else + rmnet_ctl_ipa3_ctx->state = IPA_RMNET_CTL_START; + mutex_unlock(&rmnet_ctl_ipa3_ctx->lock); + + return 0; +} + +int ipa3_setup_apps_low_lat_prod_pipe(bool rmnet_config, + struct rmnet_egress_param *egress_param) +{ + struct ipa_sys_connect_params *ipa_low_lat_ep_cfg; + int ret = 0; + int ep_idx; + + if (!ipa3_ctx->rmnet_ctl_enable) { + IPAERR("Low lat pipe is disabled"); + return 0; + } + ep_idx = ipa_get_ep_mapping( + IPA_CLIENT_APPS_WAN_LOW_LAT_PROD); + if (ep_idx == IPA_EP_NOT_ALLOCATED) { + IPAERR("low lat pipe not supported\n"); + return -EFAULT; + } + ipa_low_lat_ep_cfg = + &rmnet_ctl_ipa3_ctx->apps_to_ipa_low_lat_ep_cfg; + if (rmnet_config && egress_param) { + /* Open for future cs offload disablement on low lat pipe */ + IPAERR("Configuring low lat prod with rmnet config\n"); + ipa_low_lat_ep_cfg->ext_ioctl_v2 = true; + ipa_low_lat_ep_cfg->int_modt = egress_param->int_modt; + ipa_low_lat_ep_cfg->int_modc = egress_param->int_modc; + if (egress_param->cs_offload_en) { + ipa_low_lat_ep_cfg->ipa_ep_cfg.hdr.hdr_len = 8; + ipa_low_lat_ep_cfg->ipa_ep_cfg.cfg.cs_offload_en = + IPA_ENABLE_CS_OFFLOAD_UL; + ipa_low_lat_ep_cfg->ipa_ep_cfg.cfg.cs_metadata_hdr_offset + = 1; + ipa_low_lat_ep_cfg->ipa_ep_cfg.hdr.hdr_ofst_metadata_valid + = 1; + /* modem want offset at 0! */ + ipa_low_lat_ep_cfg->ipa_ep_cfg.hdr.hdr_ofst_metadata = 0; + } else { + ipa_low_lat_ep_cfg->ipa_ep_cfg.cfg.cs_offload_en = + IPA_DISABLE_CS_OFFLOAD; + } + + /* Open for future deaggr enablement on low lat pipe */ + if (!egress_param->aggr_en) { + ipa_low_lat_ep_cfg->ipa_ep_cfg.aggr.aggr_en = + IPA_BYPASS_AGGR; + } + } else { + IPAERR("Configuring low lat prod without rmnet config\n"); + ipa_low_lat_ep_cfg->ext_ioctl_v2 = false; + ipa_low_lat_ep_cfg->ipa_ep_cfg.hdr.hdr_len = 8; + ipa_low_lat_ep_cfg->ipa_ep_cfg.cfg.cs_offload_en = + IPA_ENABLE_CS_OFFLOAD_UL; + ipa_low_lat_ep_cfg->ipa_ep_cfg.aggr.aggr_en = + IPA_BYPASS_AGGR; + ipa_low_lat_ep_cfg->ipa_ep_cfg.cfg.cs_metadata_hdr_offset + = 1; + ipa_low_lat_ep_cfg->ipa_ep_cfg.hdr.hdr_ofst_metadata_valid + = 1; + /* modem want offset at 0! */ + ipa_low_lat_ep_cfg->ipa_ep_cfg.hdr.hdr_ofst_metadata = 0; + } + ipa_low_lat_ep_cfg->ipa_ep_cfg.mode.dst = + IPA_CLIENT_Q6_WAN_CONS; + ipa_low_lat_ep_cfg->ipa_ep_cfg.mode.mode = + IPA_DMA; + ipa_low_lat_ep_cfg->client = + IPA_CLIENT_APPS_WAN_LOW_LAT_PROD; + ipa_low_lat_ep_cfg->notify = + apps_rmnet_ctl_tx_complete_notify; + ipa_low_lat_ep_cfg->desc_fifo_sz = + IPA_SYS_TX_DATA_DESC_FIFO_SZ_8K; + ipa_low_lat_ep_cfg->priv = NULL; + + ret = ipa_setup_sys_pipe(ipa_low_lat_ep_cfg, + &rmnet_ctl_ipa3_ctx->apps_to_ipa3_low_lat_hdl); + if (ret) { + IPAERR("failed to config apps low lat prod pipe\n"); + return ret; + } + rmnet_ctl_ipa3_ctx->pipe_state |= IPA_RMNET_CTL_PIPE_TX_READY; + return 0; +} + +int ipa3_teardown_apps_low_lat_pipes(void) +{ + int ret = 0; + + if (rmnet_ctl_ipa3_ctx->state != IPA_RMNET_CTL_PIPE_READY && + rmnet_ctl_ipa3_ctx->state != IPA_RMNET_CTL_START && + rmnet_ctl_ipa3_ctx->pipe_state == IPA_RMNET_CTL_PIPE_NOT_READY) { + IPAERR("rmnet_ctl in bad state %d\n", + rmnet_ctl_ipa3_ctx->state); + return -EFAULT; + } + if (rmnet_ctl_ipa3_ctx->pipe_state == IPA_RMNET_CTL_PIPE_READY || + rmnet_ctl_ipa3_ctx->state == IPA_RMNET_CTL_START) { + if (rmnet_ctl_ipa3_ctx->cb_info.stop_cb) { + (*(rmnet_ctl_ipa3_ctx->cb_info.stop_cb)) + (rmnet_ctl_ipa3_ctx->cb_info.stop_cb_user_data); + } else { + IPAERR("Invalid stop_cb\n"); + return -EFAULT; + } + if (rmnet_ctl_ipa3_ctx->state == IPA_RMNET_CTL_PIPE_READY) + rmnet_ctl_ipa3_ctx->state = IPA_RMNET_CTL_NOT_REG; + else + rmnet_ctl_ipa3_ctx->state = IPA_RMNET_CTL_REGD; + } + if (rmnet_ctl_ipa3_ctx->pipe_state & IPA_RMNET_CTL_PIPE_RX_READY) { + ret = ipa_teardown_sys_pipe( + rmnet_ctl_ipa3_ctx->ipa3_to_apps_low_lat_hdl); + if (ret < 0) { + IPAERR("Failed to teardown APPS->IPA low lat pipe\n"); + return ret; + } + rmnet_ctl_ipa3_ctx->ipa3_to_apps_low_lat_hdl = -1; + rmnet_ctl_ipa3_ctx->pipe_state &= ~IPA_RMNET_CTL_PIPE_RX_READY; + } + + if (rmnet_ctl_ipa3_ctx->pipe_state & IPA_RMNET_CTL_PIPE_TX_READY) { + ret = ipa_teardown_sys_pipe( + rmnet_ctl_ipa3_ctx->apps_to_ipa3_low_lat_hdl); + if (ret < 0) { + return ret; + IPAERR("Failed to teardown APPS->IPA low lat pipe\n"); + } + rmnet_ctl_ipa3_ctx->apps_to_ipa3_low_lat_hdl = -1; + rmnet_ctl_ipa3_ctx->pipe_state &= ~IPA_RMNET_CTL_PIPE_TX_READY; + } + return ret; +} + +int ipa_rmnet_ctl_xmit(struct sk_buff *skb) +{ + int ret; + int len; + unsigned long flags; + + if (!ipa3_ctx->rmnet_ctl_enable) { + IPAERR("low lat pipe not supported\n"); + kfree_skb(skb); + return 0; + } + + spin_lock_irqsave(&rmnet_ctl_ipa3_ctx->tx_lock, flags); + /* we cannot infinitely queue the packet */ + if (skb_queue_len(&rmnet_ctl_ipa3_ctx->tx_queue) >= + RMNET_CTRL_QUEUE_MAX) { + IPAERR("rmnet_ctl tx queue full\n"); + rmnet_ctl_ipa3_ctx->stats.tx_pkt_dropped++; + rmnet_ctl_ipa3_ctx->stats.tx_byte_dropped += + skb->len; + spin_unlock_irqrestore(&rmnet_ctl_ipa3_ctx->tx_lock, + flags); + kfree_skb(skb); + return -EAGAIN; + } + + if (rmnet_ctl_ipa3_ctx->state != IPA_RMNET_CTL_START) { + IPAERR("bad rmnet_ctl state %d\n", + rmnet_ctl_ipa3_ctx->state); + rmnet_ctl_ipa3_ctx->stats.tx_pkt_dropped++; + rmnet_ctl_ipa3_ctx->stats.tx_byte_dropped += + skb->len; + spin_unlock_irqrestore(&rmnet_ctl_ipa3_ctx->tx_lock, + flags); + kfree_skb(skb); + return 0; + } + + /* if queue is not empty, means we still have pending wq */ + if (skb_queue_len(&rmnet_ctl_ipa3_ctx->tx_queue) != 0) { + skb_queue_tail(&rmnet_ctl_ipa3_ctx->tx_queue, skb); + spin_unlock_irqrestore(&rmnet_ctl_ipa3_ctx->tx_lock, + flags); + return 0; + } + + /* rmnet_ctl is calling from atomic context */ + ret = ipa_pm_activate(rmnet_ctl_ipa3_ctx->rmnet_ctl_pm_hdl); + if (ret == -EINPROGRESS) { + skb_queue_tail(&rmnet_ctl_ipa3_ctx->tx_queue, skb); + /* + * delayed work is required here since we need to + * reschedule in the same workqueue context on error + */ + queue_delayed_work(rmnet_ctl_ipa3_ctx->wq, + &rmnet_ctl_wakeup_work, 0); + spin_unlock_irqrestore(&rmnet_ctl_ipa3_ctx->tx_lock, + flags); + return 0; + } else if (ret) { + IPAERR("[%s] fatal: ipa pm activate failed %d\n", + __func__, ret); + rmnet_ctl_ipa3_ctx->stats.tx_pkt_dropped++; + rmnet_ctl_ipa3_ctx->stats.tx_byte_dropped += + skb->len; + spin_unlock_irqrestore(&rmnet_ctl_ipa3_ctx->tx_lock, + flags); + kfree_skb(skb); + return 0; + } + spin_unlock_irqrestore(&rmnet_ctl_ipa3_ctx->tx_lock, flags); + + len = skb->len; + /* + * both data packets and command will be routed to + * IPA_CLIENT_Q6_WAN_CONS based on DMA settings + */ + ret = ipa_tx_dp(IPA_CLIENT_APPS_WAN_LOW_LAT_PROD, skb, NULL); + if (ret) { + if (ret == -EPIPE) { + IPAERR("Low lat fatal: pipe is not valid\n"); + spin_lock_irqsave(&rmnet_ctl_ipa3_ctx->tx_lock, + flags); + rmnet_ctl_ipa3_ctx->stats.tx_pkt_dropped++; + rmnet_ctl_ipa3_ctx->stats.tx_byte_dropped += + skb->len; + spin_unlock_irqrestore(&rmnet_ctl_ipa3_ctx->tx_lock, + flags); + kfree_skb(skb); + return 0; + } + spin_lock_irqsave(&rmnet_ctl_ipa3_ctx->tx_lock, flags); + skb_queue_head(&rmnet_ctl_ipa3_ctx->tx_queue, skb); + ret = 0; + goto out; + } + + spin_lock_irqsave(&rmnet_ctl_ipa3_ctx->tx_lock, flags); + atomic_inc(&rmnet_ctl_ipa3_ctx->stats.outstanding_pkts); + rmnet_ctl_ipa3_ctx->stats.tx_pkt_sent++; + rmnet_ctl_ipa3_ctx->stats.tx_byte_sent += len; + ret = 0; + +out: + if (atomic_read( + &rmnet_ctl_ipa3_ctx->stats.outstanding_pkts) + == 0) + ipa_pm_deferred_deactivate(rmnet_ctl_ipa3_ctx->rmnet_ctl_pm_hdl); + spin_unlock_irqrestore(&rmnet_ctl_ipa3_ctx->tx_lock, flags); + return ret; +} +EXPORT_SYMBOL(ipa_rmnet_ctl_xmit); + +static void rmnet_ctl_wakeup_ipa(struct work_struct *work) +{ + int ret; + unsigned long flags; + struct sk_buff *skb; + int len = 0; + + /* calling from WQ */ + ret = ipa_pm_activate_sync(rmnet_ctl_ipa3_ctx->rmnet_ctl_pm_hdl); + if (ret) { + IPAERR("[%s] fatal: ipa pm activate failed %d\n", + __func__, ret); + queue_delayed_work(rmnet_ctl_ipa3_ctx->wq, + &rmnet_ctl_wakeup_work, + msecs_to_jiffies(1)); + return; + } + + spin_lock_irqsave(&rmnet_ctl_ipa3_ctx->tx_lock, flags); + /* dequeue the skb */ + while (skb_queue_len(&rmnet_ctl_ipa3_ctx->tx_queue) > 0) { + skb = skb_dequeue(&rmnet_ctl_ipa3_ctx->tx_queue); + if (skb == NULL) + continue; + len = skb->len; + spin_unlock_irqrestore(&rmnet_ctl_ipa3_ctx->tx_lock, flags); + /* + * both data packets and command will be routed to + * IPA_CLIENT_Q6_WAN_CONS based on DMA settings + */ + ret = ipa_tx_dp(IPA_CLIENT_APPS_WAN_LOW_LAT_PROD, skb, NULL); + if (ret) { + if (ret == -EPIPE) { + /* try to drain skb from queue if pipe teardown */ + IPAERR_RL("Low lat fatal: pipe is not valid\n"); + spin_lock_irqsave(&rmnet_ctl_ipa3_ctx->tx_lock, + flags); + rmnet_ctl_ipa3_ctx->stats.tx_pkt_dropped++; + rmnet_ctl_ipa3_ctx->stats.tx_byte_dropped += + skb->len; + kfree_skb(skb); + continue; + } + spin_lock_irqsave(&rmnet_ctl_ipa3_ctx->tx_lock, flags); + skb_queue_head(&rmnet_ctl_ipa3_ctx->tx_queue, skb); + spin_unlock_irqrestore(&rmnet_ctl_ipa3_ctx->tx_lock, flags); + goto delayed_work; + } + + atomic_inc(&rmnet_ctl_ipa3_ctx->stats.outstanding_pkts); + spin_lock_irqsave(&rmnet_ctl_ipa3_ctx->tx_lock, flags); + rmnet_ctl_ipa3_ctx->stats.tx_pkt_sent++; + rmnet_ctl_ipa3_ctx->stats.tx_byte_sent += len; + } + spin_unlock_irqrestore(&rmnet_ctl_ipa3_ctx->tx_lock, flags); + goto out; + +delayed_work: + queue_delayed_work(rmnet_ctl_ipa3_ctx->wq, + &rmnet_ctl_wakeup_work, + msecs_to_jiffies(1)); +out: + if (atomic_read( + &rmnet_ctl_ipa3_ctx->stats.outstanding_pkts) + == 0) { + ipa_pm_deferred_deactivate(rmnet_ctl_ipa3_ctx->rmnet_ctl_pm_hdl); + } + +} + +/** + * apps_rmnet_ctl_tx_complete_notify() - Rx notify + * + * @priv: driver context + * @evt: event type + * @data: data provided with event + * + * Check that the packet is the one we sent and release it + * This function will be called in defered context in IPA wq. + */ +static void apps_rmnet_ctl_tx_complete_notify(void *priv, + enum ipa_dp_evt_type evt, unsigned long data) +{ + struct sk_buff *skb = (struct sk_buff *)data; + unsigned long flags; + + if (evt != IPA_WRITE_DONE) { + IPAERR("unsupported evt on Tx callback, Drop the packet\n"); + spin_lock_irqsave(&rmnet_ctl_ipa3_ctx->tx_lock, + flags); + rmnet_ctl_ipa3_ctx->stats.tx_pkt_dropped++; + rmnet_ctl_ipa3_ctx->stats.tx_byte_dropped += + skb->len; + spin_unlock_irqrestore(&rmnet_ctl_ipa3_ctx->tx_lock, + flags); + kfree_skb(skb); + return; + } + + atomic_dec(&rmnet_ctl_ipa3_ctx->stats.outstanding_pkts); + + if (atomic_read( + &rmnet_ctl_ipa3_ctx->stats.outstanding_pkts) == 0) + ipa_pm_deferred_deactivate(rmnet_ctl_ipa3_ctx->rmnet_ctl_pm_hdl); + + kfree_skb(skb); +} + +/** + * apps_rmnet_ctl_receive_notify() - Rmnet_ctl RX notify + * + * @priv: driver context + * @evt: event type + * @data: data provided with event + * + * IPA will pass a packet to the Linux network stack with skb->data + */ +static void apps_rmnet_ctl_receive_notify(void *priv, + enum ipa_dp_evt_type evt, unsigned long data) +{ + void *rx_notify_cb_rx_data; + struct sk_buff *low_lat_data; + int len; + + low_lat_data = (struct sk_buff *)data; + if (low_lat_data == NULL) { + IPAERR("Rx packet is invalid"); + return; + } + len = low_lat_data->len; + if (evt == IPA_RECEIVE) { + IPADBG_LOW("Rx packet was received"); + rx_notify_cb_rx_data = (void *)data; + if (rmnet_ctl_ipa3_ctx->cb_info.rx_notify_cb) { + (*(rmnet_ctl_ipa3_ctx->cb_info.rx_notify_cb))( + rmnet_ctl_ipa3_ctx->cb_info.rx_notify_cb_user_data, + rx_notify_cb_rx_data); + } else + goto fail; + rmnet_ctl_ipa3_ctx->stats.rx_pkt_rcvd++; + rmnet_ctl_ipa3_ctx->stats.rx_byte_rcvd += + len; + } else { + IPAERR("Invalid evt %d received in rmnet_ctl\n", evt); + goto fail; + } + return; + +fail: + kfree_skb(low_lat_data); + rmnet_ctl_ipa3_ctx->stats.rx_pkt_dropped++; +} + + +static int ipa3_rmnet_ctl_register_pm_client(void) +{ + int result; + struct ipa_pm_register_params pm_reg; + + memset(&pm_reg, 0, sizeof(pm_reg)); + pm_reg.name = "rmnet_ctl"; + pm_reg.group = IPA_PM_GROUP_APPS; + result = ipa_pm_register(&pm_reg, &rmnet_ctl_ipa3_ctx->rmnet_ctl_pm_hdl); + if (result) { + IPAERR("failed to create IPA PM client %d\n", result); + return result; + } + + IPAERR("%s register done\n", pm_reg.name); + + return 0; +} + +static void ipa3_rmnet_ctl_deregister_pm_client(void) +{ + ipa_pm_deactivate_sync(rmnet_ctl_ipa3_ctx->rmnet_ctl_pm_hdl); + ipa_pm_deregister(rmnet_ctl_ipa3_ctx->rmnet_ctl_pm_hdl); +} + diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c new file mode 100644 index 0000000000..e2c9b894cb --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c @@ -0,0 +1,6806 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2014-2021, The Linux Foundation. All rights reserved. + * + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/* + * WWAN Transport Network Driver. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 14, 0)) +#include +#include +#endif +#include +#include "ipa_qmi_service.h" +#include +#include "ipa.h" +#include +#include +#include +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 14, 0)) +#include +#else +#include +#endif +#include "ipa_mhi_proxy.h" + +#include "ipa_trace.h" +#include "ipa_odl.h" + + +#define OUTSTANDING_HIGH_DEFAULT 256 +#define OUTSTANDING_HIGH_CTL_DEFAULT (OUTSTANDING_HIGH_DEFAULT + 32) +#define OUTSTANDING_LOW_DEFAULT 128 + +#define WWAN_METADATA_SHFT 24 +#define WWAN_METADATA_MASK 0xFF000000 +#define WWAN_DATA_LEN 9216 +#define HEADROOM_FOR_QMAP 8 /* for mux header */ +#define TAILROOM 0 /* for padding by mux layer */ +#define MAX_NUM_OF_MUX_CHANNEL 15 /* max mux channels */ +#define UL_FILTER_RULE_HANDLE_START 69 + +#define IPA_WWAN_DEV_NAME "rmnet_ipa%d" +#define IPA_UPSTEAM_WLAN_IFACE_NAME "wlan0" +#define IPA_UPSTEAM_WLAN1_IFACE_NAME "wlan1" + +enum ipa_ap_ingress_ep_enum { + IPA_AP_INGRESS_NONE = 0, + IPA_AP_INGRESS_EP_DEFAULT = 1 << 0, + IPA_AP_INGRESS_EP_COALS = 1 << 1, + IPA_AP_INGRESS_EP_LOW_LAT = 1 << 2, + IPA_AP_INGRESS_EP_LOW_LAT_DATA = 1 << 3, +}; + +#define IPA_WWAN_RX_SOFTIRQ_THRESH 16 + +#define INVALID_MUX_ID 0xFF +#define IPA_QUOTA_REACH_ALERT_MAX_SIZE 64 +#define IPA_QUOTA_REACH_IF_NAME_MAX_SIZE 64 +#define IPA_UEVENT_NUM_EVNP 4 /* number of event pointers */ +#define IPA_UPSTREAM_ALERT_MAX_SIZE 64 + +#define IPA_NETDEV() \ + ((rmnet_ipa3_ctx && rmnet_ipa3_ctx->wwan_priv) ? \ + rmnet_ipa3_ctx->wwan_priv->net : NULL) + +#define IPA_WWAN_CONS_DESC_FIFO_SZ 256 + +#define LAN_STATS_FOR_ALL_CLIENTS 0xFFFFFFFF +#define RMNET_IPA_ULCS_FEATURE \ + (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM) +#define RMNET_IPA_ULSO_FEATURE \ + (NETIF_F_SG | NETIF_F_ALL_TSO) +#define RMNET_IPA_ULSO_SIZE_LIMIT 64000 +#define MAX_WIGIG_CLIENTS_IPA_5_5 3 +#define MAX_WIGIG_CLIENTS_IPA_4_11 0 +#define MAX_WIGIG_CLIENTS 4 + +static void rmnet_ipa_free_msg(void *buff, u32 len, u32 type); +static void rmnet_ipa_get_stats_and_update(void); + +static int ipa3_wwan_add_ul_flt_rule_to_ipa(void); +static int ipa3_wwan_del_ul_flt_rule_to_ipa(void); +static void ipa3_wwan_msg_free_cb(void*, u32, u32); +static int ipa3_rmnet_poll(struct napi_struct *napi, int budget); + +static void ipa3_wake_tx_queue(struct work_struct *work); +static DECLARE_WORK(ipa3_tx_wakequeue_work, ipa3_wake_tx_queue); + +static void tethering_stats_poll_queue(struct work_struct *work); +static DECLARE_DELAYED_WORK(ipa_tether_stats_poll_wakequeue_work, + tethering_stats_poll_queue); + +static int rmnet_ipa_send_coalesce_notification(uint8_t qmap_id, bool enable, + bool tcp, bool udp); + +static int rmnet_ipa_send_set_mtu_notification(char *if_name, + uint16_t mtu_v4, uint16_t mtu_v6, enum ipa_ip_type ip); + + +enum ipa3_wwan_device_status { + WWAN_DEVICE_INACTIVE = 0, + WWAN_DEVICE_ACTIVE = 1 +}; + +enum dflt_wan_rt_rule { + WAN_RT_COMMON = 0, + WAN_RT_ICMP, + WAN_RT_RULES_TOTAL, +}; + +struct ipa3_rmnet_plat_drv_res { + bool ipa_rmnet_ssr; + bool ipa_advertise_sg_support; + bool ipa_napi_enable; + u32 wan_rx_desc_size; +}; + + + +/** + * struct ipa3_wwan_private - WWAN private data + * @net: network interface struct implemented by this driver + * @stats: iface statistics + * @outstanding_pkts: number of packets sent to IPA without TX complete ACKed + * @ch_id: channel id + * @lock: spinlock for mutual exclusion + * @device_status: holds device status + * + * WWAN private - holds all relevant info about WWAN driver + */ +struct ipa3_wwan_private { + struct net_device *net; + struct net_device_stats stats; + atomic_t outstanding_pkts; + uint32_t ch_id; + spinlock_t lock; + struct completion resource_granted_completion; + enum ipa3_wwan_device_status device_status; + struct napi_struct napi; +}; + +struct ipa3_netmgr_clock_vote { + struct mutex mutex; + uint32_t cnt; +}; + +struct rmnet_ipa_debugfs { + struct dentry *dent; + struct dentry *dfile_outstanding_high; + struct dentry *dfile_outstanding_high_ctl; + struct dentry *dfile_outstanding_low; +}; + +struct rmnet_ipa3_context { + struct ipa3_wwan_private *wwan_priv; + struct ipa_sys_connect_params apps_to_ipa_ep_cfg; + struct ipa_sys_connect_params ipa_to_apps_ep_cfg; + u32 qmap_hdr_hdl; + /* For both IPv4 and IPv6, one rule for ICMP and one for the rest */ + u32 dflt_wan_rt_hdl[IPA_IP_MAX][WAN_RT_RULES_TOTAL]; + u32 low_lat_rt_hdl[IPA_IP_MAX][WAN_RT_RULES_TOTAL]; + struct ipa3_rmnet_mux_val mux_channel[MAX_NUM_OF_MUX_CHANNEL]; + int num_q6_rules; + int old_num_q6_rules; + int rmnet_index; + bool egress_set; + bool a7_ul_flt_set; + atomic_t is_initialized; + atomic_t is_ssr; + void *lcl_mdm_subsys_notify_handle; + void *rmt_mdm_subsys_notify_handle; + u32 apps_to_ipa3_hdl; + u32 ipa3_to_apps_hdl; + struct mutex pipe_handle_guard; + struct mutex add_mux_channel_lock; + u32 pm_hdl; + u32 q6_pm_hdl; + u32 q6_teth_pm_hdl; + struct mutex per_client_stats_guard; + struct ipa_tether_device_info + tether_device + [IPACM_MAX_CLIENT_DEVICE_TYPES]; + u32 outstanding_high; + u32 outstanding_high_ctl; + u32 outstanding_low; + struct rmnet_ipa_debugfs dbgfs; + bool dl_csum_offload_enabled; + atomic_t ap_suspend; + bool ipa_config_is_apq; + bool ipa_mhi_aggr_formet_set; + struct ipa3_netmgr_clock_vote clock_vote; + int ingress_eps_mask; + bool wan_rt_table_setup; +}; + +static struct rmnet_ipa3_context *rmnet_ipa3_ctx; +static struct ipa3_rmnet_plat_drv_res ipa3_rmnet_res; +bool ipa_net_initialized = false; + +struct rmnet_ipa_pipe_setup_status { + int ep_type; + int status; +}; + +static struct rmnet_ipa_pipe_setup_status egress_pipe_status[ + RMNET_EGRESS_MAX]; +static struct rmnet_ipa_pipe_setup_status ingress_pipe_status[ + RMNET_INGRESS_MAX]; + +/** + * ipa3_setup_a7_qmap_hdr() - Setup default a7 qmap hdr + * + * Return codes: + * 0: success + * -ENOMEM: failed to allocate memory + * -EPERM: failed to add the tables + */ +static int ipa3_setup_a7_qmap_hdr(void) +{ + struct ipa_ioc_add_hdr *hdr; + struct ipa_hdr_add *hdr_entry; + u32 pyld_sz; + int ret; + + /* install the basic exception header */ + pyld_sz = sizeof(struct ipa_ioc_add_hdr) + 1 * + sizeof(struct ipa_hdr_add); + hdr = kzalloc(pyld_sz, GFP_KERNEL); + if (!hdr) + return -ENOMEM; + + hdr->num_hdrs = 1; + hdr->commit = 1; + hdr_entry = &hdr->hdr[0]; + hdr_entry->status = IPA_HDR_TO_DDR_PATTERN; + + strlcpy(hdr_entry->name, IPA_A7_QMAP_HDR_NAME, + IPA_RESOURCE_NAME_MAX); + if (ipa3_ctx_get_type(IPA_HW_TYPE) >= IPA_HW_v4_5 && + rmnet_ipa3_ctx->dl_csum_offload_enabled) { + hdr_entry->hdr_len = IPA_DL_CHECKSUM_LENGTH; /* 8 bytes */ + /* new DL QMAP header format */ + hdr_entry->hdr[0] = 0x40; + hdr_entry->hdr[1] = 0; + hdr_entry->hdr[2] = 0; + hdr_entry->hdr[3] = 0; + hdr_entry->hdr[4] = 0x4; + /* + * Need to set csum required/valid bit on which will be replaced + * by HW if checksum is incorrect after validation + */ + hdr_entry->hdr[5] = 0x80; + hdr_entry->hdr[6] = 0; + hdr_entry->hdr[7] = 0; + } else + hdr_entry->hdr_len = IPA_QMAP_HEADER_LENGTH; /* 4 bytes */ + + if (ipa_add_hdr(hdr)) { + IPAWANERR("fail to add IPA_A7_QMAP hdr\n"); + ret = -EPERM; + goto bail; + } + + if (hdr_entry->status) { + IPAWANERR("fail to add IPA_A7_QMAP hdr\n"); + ret = -EPERM; + goto bail; + } + rmnet_ipa3_ctx->qmap_hdr_hdl = hdr_entry->hdr_hdl; + + ret = 0; +bail: + kfree(hdr); + return ret; +} + +static void ipa3_del_a7_qmap_hdr(void) +{ + struct ipa_ioc_del_hdr *del_hdr; + struct ipa_hdr_del *hdl_entry; + u32 pyld_sz; + int ret; + + pyld_sz = sizeof(struct ipa_ioc_del_hdr) + 1 * + sizeof(struct ipa_hdr_del); + del_hdr = kzalloc(pyld_sz, GFP_KERNEL); + if (!del_hdr) { + IPAWANERR_RL("fail to alloc exception hdr_del\n"); + return; + } + + del_hdr->commit = 1; + del_hdr->num_hdls = 1; + hdl_entry = &del_hdr->hdl[0]; + hdl_entry->hdl = rmnet_ipa3_ctx->qmap_hdr_hdl; + + ret = ipa_del_hdr(del_hdr); + if (ret || hdl_entry->status) + IPAWANERR_RL("ipa_del_hdr failed\n"); + else + IPAWANDBG("hdrs deletion done\n"); + + rmnet_ipa3_ctx->qmap_hdr_hdl = 0; + kfree(del_hdr); +} + +static void ipa3_del_qmap_hdr(uint32_t hdr_hdl) +{ + struct ipa_ioc_del_hdr *del_hdr; + struct ipa_hdr_del *hdl_entry; + u32 pyld_sz; + int ret; + + if (hdr_hdl == 0) { + IPAWANERR("Invalid hdr_hdl provided\n"); + return; + } + + pyld_sz = sizeof(struct ipa_ioc_del_hdr) + 1 * + sizeof(struct ipa_hdr_del); + del_hdr = kzalloc(pyld_sz, GFP_KERNEL); + if (!del_hdr) { + IPAWANERR("fail to alloc exception hdr_del\n"); + return; + } + + del_hdr->commit = 1; + del_hdr->num_hdls = 1; + hdl_entry = &del_hdr->hdl[0]; + hdl_entry->hdl = hdr_hdl; + + ret = ipa_del_hdr(del_hdr); + if (ret || hdl_entry->status) + IPAWANERR("ipa_del_hdr failed\n"); + else + IPAWANDBG("header deletion done\n"); + + rmnet_ipa3_ctx->qmap_hdr_hdl = 0; + kfree(del_hdr); +} + +static void ipa3_del_mux_qmap_hdrs(void) +{ + int index; + + for (index = 0; index < rmnet_ipa3_ctx->rmnet_index; index++) { + ipa3_del_qmap_hdr(rmnet_ipa3_ctx->mux_channel[index].hdr_hdl); + rmnet_ipa3_ctx->mux_channel[index].hdr_hdl = 0; + } +} + +static int ipa3_add_qmap_hdr(uint32_t mux_id, uint32_t *hdr_hdl) +{ + struct ipa_ioc_add_hdr *hdr; + struct ipa_hdr_add *hdr_entry; + char hdr_name[IPA_RESOURCE_NAME_MAX]; + u32 pyld_sz; + int ret; + + pyld_sz = sizeof(struct ipa_ioc_add_hdr) + 1 * + sizeof(struct ipa_hdr_add); + hdr = kzalloc(pyld_sz, GFP_KERNEL); + if (!hdr) + return -ENOMEM; + + hdr->num_hdrs = 1; + hdr->commit = 1; + hdr_entry = &hdr->hdr[0]; + hdr_entry->status = IPA_HDR_TO_DDR_PATTERN; + + snprintf(hdr_name, IPA_RESOURCE_NAME_MAX, "%s%d", + A2_MUX_HDR_NAME_V4_PREF, + mux_id); + strlcpy(hdr_entry->name, hdr_name, + IPA_RESOURCE_NAME_MAX); + + if (rmnet_ipa3_ctx->dl_csum_offload_enabled) { + if (rmnet_ipa3_ctx->ipa_config_is_apq || + ipa3_ctx_get_type(IPA_HW_TYPE) >= IPA_HW_v4_5) { + hdr_entry->hdr_len = + IPA_DL_CHECKSUM_LENGTH; /* 8 bytes */ + /* new DL QMAP header format */ + hdr_entry->hdr[0] = 0x40; + hdr_entry->hdr[1] = (uint8_t) mux_id; + hdr_entry->hdr[2] = 0; + hdr_entry->hdr[3] = 0; + hdr_entry->hdr[4] = 0x4; + /* + * Need to set csum required/valid bit on + * which will be replaced by HW if checksum + * is incorrect after validation + */ + hdr_entry->hdr[5] = 0x80; + hdr_entry->hdr[6] = 0; + hdr_entry->hdr[7] = 0; + } else { + hdr_entry->hdr_len = + IPA_QMAP_HEADER_LENGTH; /* 4 bytes */ + hdr_entry->hdr[1] = (uint8_t) mux_id; + } + } else { + hdr_entry->hdr_len = IPA_QMAP_HEADER_LENGTH; /* 4 bytes */ + hdr_entry->hdr[1] = (uint8_t) mux_id; + } + + IPAWANDBG("header (%s) with mux-id: (%d)\n", + hdr_name, + hdr_entry->hdr[1]); + if (ipa_add_hdr(hdr)) { + IPAWANERR("fail to add IPA_QMAP hdr\n"); + ret = -EPERM; + goto bail; + } + + if (hdr_entry->status) { + IPAWANERR("fail to add IPA_QMAP hdr\n"); + ret = -EPERM; + goto bail; + } + + ret = 0; + *hdr_hdl = hdr_entry->hdr_hdl; +bail: + kfree(hdr); + return ret; +} + +/** + * ipa3_setup_dflt_wan_rt_tables() - Setup default wan routing tables + * + * Return codes: + * 0: success + * -ENOMEM: failed to allocate memory + * -EPERM: failed to add the tables + */ +static int ipa3_setup_dflt_wan_rt_tables(void) +{ + int ret = 0; + struct ipa_ioc_add_rt_rule_ext_v2 *rt_rule; + struct ipa_rt_rule_add_ext_v2 *rt_rule_entry; + + rt_rule = kzalloc(sizeof(struct ipa_ioc_add_rt_rule_ext_v2), + GFP_KERNEL); + if (!rt_rule) + return -ENOMEM; + rt_rule->num_rules = + ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0 ? WAN_RT_RULES_TOTAL : 1; + rt_rule->rules = (uint64_t)kzalloc( + rt_rule->num_rules * sizeof(struct ipa_rt_rule_add_ext_v2), + GFP_KERNEL); + if (!(struct ipa_rt_rule_add_ext_v2 *)(rt_rule->rules)) { + ret = -ENOMEM; + goto free_rule; + } + + /* setup a default v4 route to point to Apps */ + rt_rule->commit = 1; + rt_rule->rule_add_ext_size = sizeof(struct ipa_rt_rule_add_ext_v2); + rt_rule->ip = IPA_IP_v4; + strlcpy(rt_rule->rt_tbl_name, IPA_DFLT_WAN_RT_TBL_NAME, + IPA_RESOURCE_NAME_MAX); + + rt_rule_entry = (struct ipa_rt_rule_add_ext_v2 *)rt_rule->rules; + rt_rule_entry[WAN_RT_COMMON].at_rear = 1; + rt_rule_entry[WAN_RT_COMMON].rule.dst = IPA_CLIENT_APPS_WAN_CONS; + rt_rule_entry[WAN_RT_COMMON].rule.hdr_hdl = + rmnet_ipa3_ctx->qmap_hdr_hdl; + rt_rule_entry[WAN_RT_COMMON].rule.hashable = true; + + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0) { + rt_rule_entry[WAN_RT_ICMP].at_rear = 0; + rt_rule_entry[WAN_RT_ICMP].rule.dst = IPA_CLIENT_APPS_WAN_CONS; + rt_rule_entry[WAN_RT_ICMP].rule.hdr_hdl = + rmnet_ipa3_ctx->qmap_hdr_hdl; + rt_rule_entry[WAN_RT_ICMP].rule.close_aggr_irq_mod = true; + rt_rule_entry[WAN_RT_ICMP].rule.attrib.attrib_mask = + IPA_FLT_PROTOCOL; + rt_rule_entry[WAN_RT_ICMP].rule.attrib.u.v4.protocol = + (uint8_t)IPPROTO_ICMP; + } + + if (ipa3_add_rt_rule_ext_v2(rt_rule, + false)) { + IPAWANERR("fail to add dflt_wan v4 rule\n"); + ret = -EPERM; + goto free_rule_entry; + } + IPAWANDBG("dflt v4 rt rule hdl[WAN_RT_COMMON]=%x\n", + rt_rule_entry[WAN_RT_COMMON].rt_rule_hdl); + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0) + IPAWANDBG("dflt v4 rt rule hdl[WAN_RT_ICMP]=%x\n", + rt_rule_entry[WAN_RT_ICMP].rt_rule_hdl); + rmnet_ipa3_ctx->dflt_wan_rt_hdl[IPA_IP_v4][WAN_RT_COMMON] = + rt_rule_entry[WAN_RT_COMMON].rt_rule_hdl; + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0) + rmnet_ipa3_ctx->dflt_wan_rt_hdl[IPA_IP_v4][WAN_RT_ICMP] = + rt_rule_entry[WAN_RT_ICMP].rt_rule_hdl; + + /* setup a default v6 route to point to A5 */ + rt_rule->ip = IPA_IP_v6; + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0) { + rt_rule_entry[WAN_RT_ICMP].rule.attrib.attrib_mask = + IPA_FLT_NEXT_HDR; + rt_rule_entry[WAN_RT_ICMP].rule.attrib.u.v6.next_hdr = + (uint8_t)NEXTHDR_ICMP; + } + if (ipa3_add_rt_rule_ext_v2(rt_rule, + false)) { + IPAWANERR("fail to add dflt_wan v6 rule\n"); + ret = -EPERM; + goto free_rule_entry; + } + IPAWANDBG("dflt v6 rt rule hdl[WAN_RT_COMMON]=%x\n", + rt_rule_entry[WAN_RT_COMMON].rt_rule_hdl); + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0) + IPAWANDBG("dflt v6 rt rule hdl[WAN_RT_ICMP]=%x\n", + rt_rule_entry[WAN_RT_ICMP].rt_rule_hdl); + rmnet_ipa3_ctx->dflt_wan_rt_hdl[IPA_IP_v6][WAN_RT_COMMON] = + rt_rule_entry[WAN_RT_COMMON].rt_rule_hdl; + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0) + rmnet_ipa3_ctx->dflt_wan_rt_hdl[IPA_IP_v6][WAN_RT_ICMP] = + rt_rule_entry[WAN_RT_ICMP].rt_rule_hdl; + +free_rule_entry: + kfree((void *)(rt_rule->rules)); +free_rule: + kfree(rt_rule); + return ret; +} + +/** + * ipa3_setup_low_lat_rt_rules() - Setup default wan routing tables + * + * Return codes: + * 0: success + * -ENOMEM: failed to allocate memory + * -EPERM: failed to add the tables + */ +static int ipa3_setup_low_lat_rt_rules(void) +{ + int ret = 0; + struct ipa_ioc_add_rt_rule_ext_v2 *rt_rule; + struct ipa_rt_rule_add_ext_v2 *rt_rule_entry; + + rt_rule = kzalloc(sizeof(struct ipa_ioc_add_rt_rule_ext_v2), + GFP_KERNEL); + if (!rt_rule) + return -ENOMEM; + rt_rule->num_rules = 2; + rt_rule->rules = (uint64_t)kzalloc( + rt_rule->num_rules * sizeof(struct ipa_rt_rule_add_ext_v2), + GFP_KERNEL); + if (!(struct ipa_rt_rule_add_ext_v2 *)(rt_rule->rules)) { + ret = -ENOMEM; + goto free_rule; + } + + /* setup a low lat v4 route to point to Apps */ + rt_rule->commit = 1; + rt_rule->rule_add_ext_size = sizeof(struct ipa_rt_rule_add_ext_v2); + rt_rule->ip = IPA_IP_v4; + strlcpy(rt_rule->rt_tbl_name, IPA_DFLT_WAN_RT_TBL_NAME, + IPA_RESOURCE_NAME_MAX); + + rt_rule_entry = (struct ipa_rt_rule_add_ext_v2 *)rt_rule->rules; + rt_rule_entry[WAN_RT_COMMON].at_rear = 0; + rt_rule_entry[WAN_RT_COMMON].rule.dst = + IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_CONS; + rt_rule_entry[WAN_RT_COMMON].rule.hdr_hdl = + rmnet_ipa3_ctx->qmap_hdr_hdl; + rt_rule_entry[WAN_RT_COMMON].rule.attrib.attrib_mask = + IPA_FLT_META_DATA; + /* Low lat routing is based on metadata */ + rt_rule_entry[WAN_RT_COMMON].rule.attrib.meta_data = + ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_CONS); + rt_rule_entry[WAN_RT_COMMON].rule.attrib.meta_data_mask = + 0xFF; + + rt_rule_entry[WAN_RT_ICMP].at_rear = 0; + rt_rule_entry[WAN_RT_ICMP].rule.dst = + IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_CONS; + rt_rule_entry[WAN_RT_ICMP].rule.hdr_hdl = + rmnet_ipa3_ctx->qmap_hdr_hdl; + rt_rule_entry[WAN_RT_ICMP].rule.attrib.attrib_mask = + IPA_FLT_META_DATA; + rt_rule_entry[WAN_RT_ICMP].rule.attrib.meta_data = + ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_CONS); + rt_rule_entry[WAN_RT_ICMP].rule.attrib.meta_data_mask = + 0xFF; + rt_rule_entry[WAN_RT_ICMP].rule.attrib.attrib_mask |= + IPA_FLT_PROTOCOL; + rt_rule_entry[WAN_RT_ICMP].rule.attrib.u.v4.protocol = + (uint8_t)IPPROTO_ICMP; + + if (ipa3_add_rt_rule_ext_v2(rt_rule, + false)) { + IPAWANERR("fail to add low lat v4 rule\n"); + ret = -EPERM; + goto free_rule_entry; + } + IPAWANDBG("low lat v4 rt rule hdl[WAN_RT_COMMON]=%x\n", + rt_rule_entry[WAN_RT_COMMON].rt_rule_hdl); + rmnet_ipa3_ctx->low_lat_rt_hdl[IPA_IP_v4][WAN_RT_COMMON] = + rt_rule_entry[WAN_RT_COMMON].rt_rule_hdl; + IPAWANDBG("low lat v4 rt rule hdl[WAN_RT_ICMP]=%x\n", + rt_rule_entry[WAN_RT_ICMP].rt_rule_hdl); + rmnet_ipa3_ctx->low_lat_rt_hdl[IPA_IP_v4][WAN_RT_ICMP] = + rt_rule_entry[WAN_RT_ICMP].rt_rule_hdl; + + /* setup low lat v6 route to point to A5 */ + rt_rule->ip = IPA_IP_v6; + rt_rule_entry[WAN_RT_ICMP].rule.attrib.attrib_mask = + IPA_FLT_META_DATA | IPA_FLT_NEXT_HDR; + rt_rule_entry[WAN_RT_ICMP].rule.attrib.u.v6.next_hdr = + (uint8_t)IPPROTO_ICMP; + if (ipa3_add_rt_rule_ext_v2(rt_rule, + false)) { + IPAWANERR("fail to add low lat v6 rule\n"); + ret = -EPERM; + goto free_rule_entry; + } + IPAWANDBG("low lat v6 rt rule hdl[WAN_RT_COMMON]=%x\n", + rt_rule_entry[WAN_RT_COMMON].rt_rule_hdl); + rmnet_ipa3_ctx->low_lat_rt_hdl[IPA_IP_v6][WAN_RT_COMMON] = + rt_rule_entry[WAN_RT_COMMON].rt_rule_hdl; + IPAWANDBG("low lat v6 rt rule hdl[WAN_RT_ICMP]=%x\n", + rt_rule_entry[WAN_RT_ICMP].rt_rule_hdl); + rmnet_ipa3_ctx->low_lat_rt_hdl[IPA_IP_v6][WAN_RT_ICMP] = + rt_rule_entry[WAN_RT_ICMP].rt_rule_hdl; + +free_rule_entry: + kfree((void *)(rt_rule->rules)); +free_rule: + kfree(rt_rule); + return ret; +} + +static void ipa3_del_dflt_wan_rt_tables(void) +{ + struct ipa_ioc_del_rt_rule *rt_rule; + struct ipa_rt_rule_del *rt_rule_entry; + int i, len, num_of_rules_per_ip_type; + enum ipa_ip_type ip_type; + + num_of_rules_per_ip_type = + ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0 ? WAN_RT_RULES_TOTAL : 1; + + len = sizeof(struct ipa_ioc_del_rt_rule) + 1 * + sizeof(struct ipa_rt_rule_del); + rt_rule = kzalloc(len, GFP_KERNEL); + if (!rt_rule) + return; + + rt_rule->commit = 1; + rt_rule->num_hdls = 1; + + rt_rule_entry = &rt_rule->hdl[0]; + rt_rule_entry->status = -1; + + for (ip_type = IPA_IP_v4; ip_type <= IPA_IP_v6; ip_type++) { + for (i = WAN_RT_COMMON; i < num_of_rules_per_ip_type; i++) { + rt_rule->ip = ip_type; + rt_rule_entry->hdl = + rmnet_ipa3_ctx->dflt_wan_rt_hdl[ip_type][i]; + IPAWANDBG("Deleting Route hdl:(0x%x) with ip type: %d\n", + rt_rule_entry->hdl, ip_type); + if (ipa3_del_rt_rule(rt_rule) || + (rt_rule_entry->status)) { + IPAWANERR("Routing rule deletion failed\n"); + } + } + } + + kfree(rt_rule); +} + +static void ipa3_del_low_lat_rt_rule(void) +{ + struct ipa_ioc_del_rt_rule *rt_rule; + struct ipa_rt_rule_del *rt_rule_entry; + int i, len, num_of_rules_per_ip_type; + enum ipa_ip_type ip_type; + + num_of_rules_per_ip_type = 2; + + len = sizeof(struct ipa_ioc_del_rt_rule) + 1 * + sizeof(struct ipa_rt_rule_del); + rt_rule = kzalloc(len, GFP_KERNEL); + if (!rt_rule) + return; + + rt_rule->commit = 1; + rt_rule->num_hdls = 1; + + rt_rule_entry = &rt_rule->hdl[0]; + rt_rule_entry->status = -1; + + for (ip_type = IPA_IP_v4; ip_type <= IPA_IP_v6; ip_type++) { + for (i = WAN_RT_COMMON; i < num_of_rules_per_ip_type; i++) { + rt_rule->ip = ip_type; + rt_rule_entry->hdl = + rmnet_ipa3_ctx->low_lat_rt_hdl[ip_type][i]; + IPAWANDBG("Deleting Route hdl:(0x%x) with ip type: %d\n", + rt_rule_entry->hdl, ip_type); + if (ipa3_del_rt_rule(rt_rule) || + (rt_rule_entry->status)) { + IPAWANERR("Routing rule deletion failed\n"); + } + } + } + + kfree(rt_rule); +} + +static void ipa3_copy_qmi_flt_rule_ex( + struct ipa_ioc_ext_intf_prop *q6_ul_flt_rule_ptr, + void *flt_spec_ptr_void) +{ + int j; + struct ipa_filter_spec_ex_type_v01 *flt_spec_ptr; + struct ipa_ipfltr_range_eq_16 *q6_ul_filter_nat_ptr; + struct ipa_ipfltr_range_eq_16_type_v01 *filter_spec_nat_ptr; + + /* + * pure_ack and tos has the same size and type and we will treat tos + * field as pure_ack in ipa4.5 version + */ + flt_spec_ptr = (struct ipa_filter_spec_ex_type_v01 *) flt_spec_ptr_void; + + q6_ul_flt_rule_ptr->ip = (enum ipa_ip_type)flt_spec_ptr->ip_type; + q6_ul_flt_rule_ptr->action = (enum ipa_flt_action)flt_spec_ptr->filter_action; + if (flt_spec_ptr->is_routing_table_index_valid == true) + q6_ul_flt_rule_ptr->rt_tbl_idx = + flt_spec_ptr->route_table_index; + if (flt_spec_ptr->is_mux_id_valid == true) + q6_ul_flt_rule_ptr->mux_id = + flt_spec_ptr->mux_id; + q6_ul_flt_rule_ptr->rule_id = + flt_spec_ptr->rule_id; + q6_ul_flt_rule_ptr->is_rule_hashable = + flt_spec_ptr->is_rule_hashable; + q6_ul_flt_rule_ptr->eq_attrib.rule_eq_bitmap = + flt_spec_ptr->filter_rule.rule_eq_bitmap; + q6_ul_flt_rule_ptr->eq_attrib.tos_eq_present = + flt_spec_ptr->filter_rule.tos_eq_present; + q6_ul_flt_rule_ptr->eq_attrib.tos_eq = + flt_spec_ptr->filter_rule.tos_eq; + q6_ul_flt_rule_ptr->eq_attrib.protocol_eq_present = + flt_spec_ptr->filter_rule.protocol_eq_present; + q6_ul_flt_rule_ptr->eq_attrib.protocol_eq = + flt_spec_ptr->filter_rule.protocol_eq; + q6_ul_flt_rule_ptr->eq_attrib.num_ihl_offset_range_16 = + flt_spec_ptr->filter_rule.num_ihl_offset_range_16; + + for (j = 0; + j < q6_ul_flt_rule_ptr->eq_attrib.num_ihl_offset_range_16; + j++) { + q6_ul_filter_nat_ptr = + &q6_ul_flt_rule_ptr->eq_attrib.ihl_offset_range_16[j]; + filter_spec_nat_ptr = + &flt_spec_ptr->filter_rule.ihl_offset_range_16[j]; + q6_ul_filter_nat_ptr->offset = + filter_spec_nat_ptr->offset; + q6_ul_filter_nat_ptr->range_low = + filter_spec_nat_ptr->range_low; + q6_ul_filter_nat_ptr->range_high = + filter_spec_nat_ptr->range_high; + } + q6_ul_flt_rule_ptr->eq_attrib.num_offset_meq_32 = + flt_spec_ptr->filter_rule.num_offset_meq_32; + for (j = 0; + j < q6_ul_flt_rule_ptr->eq_attrib.num_offset_meq_32; + j++) { + q6_ul_flt_rule_ptr->eq_attrib.offset_meq_32[j].offset = + flt_spec_ptr->filter_rule.offset_meq_32[j].offset; + q6_ul_flt_rule_ptr->eq_attrib.offset_meq_32[j].mask = + flt_spec_ptr->filter_rule.offset_meq_32[j].mask; + q6_ul_flt_rule_ptr->eq_attrib.offset_meq_32[j].value = + flt_spec_ptr->filter_rule.offset_meq_32[j].value; + } + + q6_ul_flt_rule_ptr->eq_attrib.tc_eq_present = + flt_spec_ptr->filter_rule.tc_eq_present; + q6_ul_flt_rule_ptr->eq_attrib.tc_eq = + flt_spec_ptr->filter_rule.tc_eq; + q6_ul_flt_rule_ptr->eq_attrib.fl_eq_present = + flt_spec_ptr->filter_rule.flow_eq_present; + q6_ul_flt_rule_ptr->eq_attrib.fl_eq = + flt_spec_ptr->filter_rule.flow_eq; + q6_ul_flt_rule_ptr->eq_attrib.ihl_offset_eq_16_present = + flt_spec_ptr->filter_rule.ihl_offset_eq_16_present; + q6_ul_flt_rule_ptr->eq_attrib.ihl_offset_eq_16.offset = + flt_spec_ptr->filter_rule.ihl_offset_eq_16.offset; + q6_ul_flt_rule_ptr->eq_attrib.ihl_offset_eq_16.value = + flt_spec_ptr->filter_rule.ihl_offset_eq_16.value; + + q6_ul_flt_rule_ptr->eq_attrib.ihl_offset_eq_32_present = + flt_spec_ptr->filter_rule.ihl_offset_eq_32_present; + q6_ul_flt_rule_ptr->eq_attrib.ihl_offset_eq_32.offset = + flt_spec_ptr->filter_rule.ihl_offset_eq_32.offset; + q6_ul_flt_rule_ptr->eq_attrib.ihl_offset_eq_32.value = + flt_spec_ptr->filter_rule.ihl_offset_eq_32.value; + + q6_ul_flt_rule_ptr->eq_attrib.num_ihl_offset_meq_32 = + flt_spec_ptr->filter_rule.num_ihl_offset_meq_32; + for (j = 0; + j < q6_ul_flt_rule_ptr->eq_attrib.num_ihl_offset_meq_32; + j++) { + q6_ul_flt_rule_ptr->eq_attrib.ihl_offset_meq_32[j].offset = + flt_spec_ptr->filter_rule.ihl_offset_meq_32[j].offset; + q6_ul_flt_rule_ptr->eq_attrib.ihl_offset_meq_32[j].mask = + flt_spec_ptr->filter_rule.ihl_offset_meq_32[j].mask; + q6_ul_flt_rule_ptr->eq_attrib.ihl_offset_meq_32[j].value = + flt_spec_ptr->filter_rule.ihl_offset_meq_32[j].value; + } + q6_ul_flt_rule_ptr->eq_attrib.num_offset_meq_128 = + flt_spec_ptr->filter_rule.num_offset_meq_128; + for (j = 0; + j < q6_ul_flt_rule_ptr->eq_attrib.num_offset_meq_128; + j++) { + q6_ul_flt_rule_ptr->eq_attrib.offset_meq_128[j].offset = + flt_spec_ptr->filter_rule.offset_meq_128[j].offset; + memcpy(q6_ul_flt_rule_ptr->eq_attrib.offset_meq_128[j].mask, + flt_spec_ptr->filter_rule.offset_meq_128[j].mask, 16); + memcpy(q6_ul_flt_rule_ptr->eq_attrib.offset_meq_128[j].value, + flt_spec_ptr->filter_rule.offset_meq_128[j].value, 16); + } + + q6_ul_flt_rule_ptr->eq_attrib.metadata_meq32_present = + flt_spec_ptr->filter_rule.metadata_meq32_present; + q6_ul_flt_rule_ptr->eq_attrib.metadata_meq32.offset = + flt_spec_ptr->filter_rule.metadata_meq32.offset; + q6_ul_flt_rule_ptr->eq_attrib.metadata_meq32.mask = + flt_spec_ptr->filter_rule.metadata_meq32.mask; + q6_ul_flt_rule_ptr->eq_attrib.metadata_meq32.value = + flt_spec_ptr->filter_rule.metadata_meq32.value; + q6_ul_flt_rule_ptr->eq_attrib.ipv4_frag_eq_present = + flt_spec_ptr->filter_rule.ipv4_frag_eq_present; +} + +int ipa3_copy_ul_filter_rule_to_ipa(struct ipa_install_fltr_rule_req_msg_v01 + *rule_req) +{ + int i; + + /* prevent multi-threads accessing rmnet_ipa3_ctx->num_q6_rules */ + mutex_lock(&rmnet_ipa3_ctx->add_mux_channel_lock); + if (rule_req->filter_spec_ex_list_valid == true && + rule_req->filter_spec_ex2_list_valid == false) { + rmnet_ipa3_ctx->num_q6_rules = + rule_req->filter_spec_ex_list_len; + IPAWANDBG("Received (%d) install_flt_req_ex_list\n", + rmnet_ipa3_ctx->num_q6_rules); + } else if (rule_req->filter_spec_ex2_list_valid == true && + rule_req->filter_spec_ex_list_valid == false) { + rmnet_ipa3_ctx->num_q6_rules = + rule_req->filter_spec_ex2_list_len; + IPAWANDBG("Received (%d) install_flt_req_ex2_list\n", + rmnet_ipa3_ctx->num_q6_rules); + } else { + rmnet_ipa3_ctx->num_q6_rules = 0; + if (rule_req->filter_spec_ex2_list_valid == true) + IPAWANERR( + "both ex and ex2 flt rules are set to valid\n"); + else + IPAWANERR("got no UL rules from modem\n"); + mutex_unlock( + &rmnet_ipa3_ctx->add_mux_channel_lock); + return -EINVAL; + } + + /* copy UL filter rules from Modem*/ + for (i = 0; i < rmnet_ipa3_ctx->num_q6_rules; i++) { + /* check if rules overside the cache*/ + if (i == MAX_NUM_Q6_RULE) { + IPAWANERR("Reaching (%d) max cache ", + MAX_NUM_Q6_RULE); + IPAWANERR(" however total (%d)\n", + rmnet_ipa3_ctx->num_q6_rules); + goto failure; + } + if (rule_req->filter_spec_ex_list_valid == true) + ipa3_copy_qmi_flt_rule_ex( + &ipa3_qmi_ctx->q6_ul_filter_rule[i], + &rule_req->filter_spec_ex_list[i]); + else if (rule_req->filter_spec_ex2_list_valid == true) + ipa3_copy_qmi_flt_rule_ex( + &ipa3_qmi_ctx->q6_ul_filter_rule[i], + &rule_req->filter_spec_ex2_list[i]); + } + + if (rule_req->xlat_filter_indices_list_valid) { + if (rule_req->xlat_filter_indices_list_len > + rmnet_ipa3_ctx->num_q6_rules) { + IPAWANERR("Number of xlat indices is not valid: %d\n", + rule_req->xlat_filter_indices_list_len); + goto failure; + } + IPAWANDBG("Receive %d XLAT indices: ", + rule_req->xlat_filter_indices_list_len); + for (i = 0; i < rule_req->xlat_filter_indices_list_len; i++) + IPAWANDBG("%d ", rule_req->xlat_filter_indices_list[i]); + IPAWANDBG("\n"); + + for (i = 0; i < rule_req->xlat_filter_indices_list_len; i++) { + if (rule_req->xlat_filter_indices_list[i] + >= rmnet_ipa3_ctx->num_q6_rules) { + IPAWANERR("Xlat rule idx is wrong: %d\n", + rule_req->xlat_filter_indices_list[i]); + goto failure; + } else { + ipa3_qmi_ctx->q6_ul_filter_rule + [rule_req->xlat_filter_indices_list[i]] + .is_xlat_rule = 1; + IPAWANDBG("Rule %d is xlat rule\n", + rule_req->xlat_filter_indices_list[i]); + } + } + } + + if (rule_req->ul_firewall_indices_list_valid) { + IPAWANDBG("Receive ul_firewall_indices_list_len = (%d)", + rule_req->ul_firewall_indices_list_len); + + if (rule_req->ul_firewall_indices_list_len > + rmnet_ipa3_ctx->num_q6_rules) { + IPAWANERR("UL rule indices are not valid: (%d/%d)\n", + rule_req->xlat_filter_indices_list_len, + rmnet_ipa3_ctx->num_q6_rules); + goto failure; + } + + ipa3_qmi_ctx->ul_firewall_indices_list_valid = 1; + ipa3_qmi_ctx->ul_firewall_indices_list_len = + rule_req->ul_firewall_indices_list_len; + + for (i = 0; i < rule_req->ul_firewall_indices_list_len; i++) { + ipa3_qmi_ctx->ul_firewall_indices_list[i] = + rule_req->ul_firewall_indices_list[i]; + } + + for (i = 0; i < rule_req->ul_firewall_indices_list_len; i++) { + if (rule_req->ul_firewall_indices_list[i] + >= rmnet_ipa3_ctx->num_q6_rules) { + IPAWANERR("UL rule idx is wrong: %d\n", + rule_req->ul_firewall_indices_list[i]); + goto failure; + } else { + ipa3_qmi_ctx->q6_ul_filter_rule + [rule_req->ul_firewall_indices_list[i]] + .replicate_needed = 1; + } + } + } + goto success; + +failure: + rmnet_ipa3_ctx->num_q6_rules = 0; + memset(ipa3_qmi_ctx->q6_ul_filter_rule, 0, + sizeof(ipa3_qmi_ctx->q6_ul_filter_rule)); + mutex_unlock( + &rmnet_ipa3_ctx->add_mux_channel_lock); + return -EINVAL; + +success: + mutex_unlock( + &rmnet_ipa3_ctx->add_mux_channel_lock); + return 0; +} + +static int ipa3_wwan_add_ul_flt_rule_to_ipa(void) +{ + u32 pyld_sz; + int i, retval = 0; + struct ipa_ioc_add_flt_rule *param; + struct ipa_flt_rule_add flt_rule_entry; + struct ipa_fltr_installed_notif_req_msg_v01 *req; + + pyld_sz = sizeof(struct ipa_ioc_add_flt_rule) + + sizeof(struct ipa_flt_rule_add); + param = kzalloc(pyld_sz, GFP_KERNEL); + if (!param) + return -ENOMEM; + + req = kzalloc(sizeof(struct ipa_fltr_installed_notif_req_msg_v01), + GFP_KERNEL); + if (!req) { + kfree(param); + return -ENOMEM; + } + + param->commit = 1; + param->ep = IPA_CLIENT_APPS_WAN_PROD; + param->global = false; + param->num_rules = (uint8_t)1; + + memset(req, 0, sizeof(struct ipa_fltr_installed_notif_req_msg_v01)); + + for (i = 0; i < rmnet_ipa3_ctx->num_q6_rules; i++) { + param->ip = ipa3_qmi_ctx->q6_ul_filter_rule[i].ip; + memset(&flt_rule_entry, 0, sizeof(struct ipa_flt_rule_add)); + flt_rule_entry.at_rear = true; + flt_rule_entry.rule.action = + ipa3_qmi_ctx->q6_ul_filter_rule[i].action; + flt_rule_entry.rule.rt_tbl_idx + = ipa3_qmi_ctx->q6_ul_filter_rule[i].rt_tbl_idx; + flt_rule_entry.rule.retain_hdr = true; + flt_rule_entry.rule.hashable = + ipa3_qmi_ctx->q6_ul_filter_rule[i].is_rule_hashable; + flt_rule_entry.rule.rule_id = + ipa3_qmi_ctx->q6_ul_filter_rule[i].rule_id; + + /* debug rt-hdl*/ + IPAWANDBG("install-IPA index(%d),rt-tbl:(%d)\n", + i, flt_rule_entry.rule.rt_tbl_idx); + flt_rule_entry.rule.eq_attrib_type = true; + memcpy(&(flt_rule_entry.rule.eq_attrib), + &ipa3_qmi_ctx->q6_ul_filter_rule[i].eq_attrib, + sizeof(struct ipa_ipfltri_rule_eq)); + memcpy(&(param->rules[0]), &flt_rule_entry, + sizeof(struct ipa_flt_rule_add)); + if (ipa3_add_flt_rule((struct ipa_ioc_add_flt_rule *)param)) { + retval = -EFAULT; + IPAWANERR("add A7 UL filter rule(%d) failed\n", i); + } else { + /* store the rule handler */ + ipa3_qmi_ctx->q6_ul_filter_rule_hdl[i] = + param->rules[0].flt_rule_hdl; + } + } + + /* send ipa_fltr_installed_notif_req_msg_v01 to Q6*/ + req->source_pipe_index = + ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_PROD); + if (req->source_pipe_index == IPA_EP_NOT_ALLOCATED) { + IPAWANERR("ep mapping failed\n"); + retval = -EFAULT; + } + + req->install_status = QMI_RESULT_SUCCESS_V01; + req->rule_id_valid = 1; + req->rule_id_len = rmnet_ipa3_ctx->num_q6_rules; + for (i = 0; i < rmnet_ipa3_ctx->num_q6_rules; i++) { + req->rule_id[i] = + ipa3_qmi_ctx->q6_ul_filter_rule[i].rule_id; + } + if (ipa3_qmi_filter_notify_send(req)) { + IPAWANDBG("add filter rule index on A7-RX failed\n"); + retval = -EFAULT; + } + rmnet_ipa3_ctx->old_num_q6_rules = rmnet_ipa3_ctx->num_q6_rules; + IPAWANDBG("add (%d) filter rule index on A7-RX\n", + rmnet_ipa3_ctx->old_num_q6_rules); + kfree(param); + kfree(req); + return retval; +} + +static int ipa3_wwan_del_ul_flt_rule_to_ipa(void) +{ + u32 pyld_sz; + int i, retval = 0; + struct ipa_ioc_del_flt_rule *param; + struct ipa_flt_rule_del flt_rule_entry; + + pyld_sz = sizeof(struct ipa_ioc_del_flt_rule) + + sizeof(struct ipa_flt_rule_del); + param = kzalloc(pyld_sz, GFP_KERNEL); + if (!param) + return -ENOMEM; + + + param->commit = 1; + param->num_hdls = (uint8_t) 1; + + for (i = 0; i < rmnet_ipa3_ctx->old_num_q6_rules; i++) { + param->ip = ipa3_qmi_ctx->q6_ul_filter_rule[i].ip; + memset(&flt_rule_entry, 0, sizeof(struct ipa_flt_rule_del)); + flt_rule_entry.hdl = ipa3_qmi_ctx->q6_ul_filter_rule_hdl[i]; + /* debug rt-hdl*/ + IPAWANDBG("delete-IPA rule index(%d)\n", i); + memcpy(&(param->hdl[0]), &flt_rule_entry, + sizeof(struct ipa_flt_rule_del)); + if (ipa3_del_flt_rule((struct ipa_ioc_del_flt_rule *)param)) { + IPAWANERR("del A7 UL filter rule(%d) failed\n", i); + kfree(param); + return -EFAULT; + } + } + + /* set UL filter-rule add-indication */ + rmnet_ipa3_ctx->a7_ul_flt_set = false; + rmnet_ipa3_ctx->old_num_q6_rules = 0; + + kfree(param); + return retval; +} + +static int ipa3_find_mux_channel_index(uint32_t mux_id) +{ + int i; + + for (i = 0; i < MAX_NUM_OF_MUX_CHANNEL; i++) { + if (mux_id == rmnet_ipa3_ctx->mux_channel[i].mux_id) + return i; + } + return MAX_NUM_OF_MUX_CHANNEL; +} + +static int find_vchannel_name_index(const char *vchannel_name) +{ + int i; + + for (i = 0; i < rmnet_ipa3_ctx->rmnet_index; i++) { + if (strcmp(rmnet_ipa3_ctx->mux_channel[i].vchannel_name, + vchannel_name) == 0) + return i; + } + return MAX_NUM_OF_MUX_CHANNEL; +} + +static enum ipa_upstream_type find_upstream_type(const char *upstreamIface) +{ + int i; + + for (i = 0; i < MAX_NUM_OF_MUX_CHANNEL; i++) { + if (strcmp(rmnet_ipa3_ctx->mux_channel[i].vchannel_name, + upstreamIface) == 0) + return IPA_UPSTEAM_MODEM; + } + + if ((strcmp(IPA_UPSTEAM_WLAN_IFACE_NAME, upstreamIface) == 0) || + (strcmp(IPA_UPSTEAM_WLAN1_IFACE_NAME, upstreamIface) == 0)) + return IPA_UPSTEAM_WLAN; + else + return MAX_NUM_OF_MUX_CHANNEL; +} + +static int ipa3_wwan_register_to_ipa(int index) +{ + struct ipa_tx_intf tx_properties = {0}; + struct ipa_ioc_tx_intf_prop tx_ioc_properties[2] = { {0}, {0} }; + struct ipa_ioc_tx_intf_prop *tx_ipv4_property; + struct ipa_ioc_tx_intf_prop *tx_ipv6_property; + struct ipa_rx_intf rx_properties = {0}; + struct ipa_ioc_rx_intf_prop rx_ioc_properties[2] = { {0}, {0} }; + struct ipa_ioc_rx_intf_prop *rx_ipv4_property; + struct ipa_ioc_rx_intf_prop *rx_ipv6_property; + struct ipa_ext_intf ext_properties = {0}; + struct ipa_ioc_ext_intf_prop *ext_ioc_properties; + u32 pyld_sz; + int ret = 0, i; + + IPAWANDBG("index(%d) device[%s]:\n", index, + rmnet_ipa3_ctx->mux_channel[index].vchannel_name); + if (!rmnet_ipa3_ctx->mux_channel[index].mux_hdr_set) { + ret = ipa3_add_qmap_hdr( + rmnet_ipa3_ctx->mux_channel[index].mux_id, + &rmnet_ipa3_ctx->mux_channel[index].hdr_hdl); + if (ret) { + IPAWANERR_RL("ipa_add_mux_hdr failed (%d)\n", index); + return ret; + } + rmnet_ipa3_ctx->mux_channel[index].mux_hdr_set = true; + } + tx_properties.prop = tx_ioc_properties; + tx_ipv4_property = &tx_properties.prop[0]; + tx_ipv4_property->ip = IPA_IP_v4; + if (rmnet_ipa3_ctx->ipa_config_is_apq) + tx_ipv4_property->dst_pipe = IPA_CLIENT_MHI_PRIME_TETH_CONS; + else + tx_ipv4_property->dst_pipe = IPA_CLIENT_APPS_WAN_CONS; + snprintf(tx_ipv4_property->hdr_name, IPA_RESOURCE_NAME_MAX, "%s%d", + A2_MUX_HDR_NAME_V4_PREF, + rmnet_ipa3_ctx->mux_channel[index].mux_id); + tx_ipv6_property = &tx_properties.prop[1]; + tx_ipv6_property->ip = IPA_IP_v6; + if (rmnet_ipa3_ctx->ipa_config_is_apq) + tx_ipv6_property->dst_pipe = IPA_CLIENT_MHI_PRIME_TETH_CONS; + else + tx_ipv6_property->dst_pipe = IPA_CLIENT_APPS_WAN_CONS; + /* no need use A2_MUX_HDR_NAME_V6_PREF, same header */ + snprintf(tx_ipv6_property->hdr_name, IPA_RESOURCE_NAME_MAX, "%s%d", + A2_MUX_HDR_NAME_V4_PREF, + rmnet_ipa3_ctx->mux_channel[index].mux_id); + tx_properties.num_props = 2; + + rx_properties.prop = rx_ioc_properties; + rx_ipv4_property = &rx_properties.prop[0]; + rx_ipv4_property->ip = IPA_IP_v4; + rx_ipv4_property->attrib.attrib_mask |= IPA_FLT_META_DATA; + rx_ipv4_property->attrib.meta_data = + rmnet_ipa3_ctx->mux_channel[index].mux_id << WWAN_METADATA_SHFT; + rx_ipv4_property->attrib.meta_data_mask = WWAN_METADATA_MASK; + if (rmnet_ipa3_ctx->ipa_config_is_apq) + rx_ipv4_property->src_pipe = IPA_CLIENT_MHI_PRIME_TETH_PROD; + else + rx_ipv4_property->src_pipe = IPA_CLIENT_APPS_WAN_PROD; + rx_ipv6_property = &rx_properties.prop[1]; + rx_ipv6_property->ip = IPA_IP_v6; + rx_ipv6_property->attrib.attrib_mask |= IPA_FLT_META_DATA; + rx_ipv6_property->attrib.meta_data = + rmnet_ipa3_ctx->mux_channel[index].mux_id << WWAN_METADATA_SHFT; + rx_ipv6_property->attrib.meta_data_mask = WWAN_METADATA_MASK; + if (rmnet_ipa3_ctx->ipa_config_is_apq) + rx_ipv6_property->src_pipe = IPA_CLIENT_MHI_PRIME_TETH_PROD; + else + rx_ipv6_property->src_pipe = IPA_CLIENT_APPS_WAN_PROD; + rx_properties.num_props = 2; + + if (rmnet_ipa3_ctx->ipa_config_is_apq) { + /* provide mux-id to ipacm in apq platform*/ + pyld_sz = sizeof(struct ipa_ioc_ext_intf_prop); + ext_ioc_properties = kmalloc(pyld_sz, GFP_KERNEL); + if (!ext_ioc_properties) + return -ENOMEM; + + ext_properties.prop = ext_ioc_properties; + ext_properties.num_props = 1; + ext_properties.prop[0].mux_id = + rmnet_ipa3_ctx->mux_channel[index].mux_id; + ext_properties.prop[0].ip = IPA_IP_MAX; + IPAWANDBG("ip: %d mux:%d\n", + ext_properties.prop[0].ip, + ext_properties.prop[0].mux_id); + ret = ipa3_register_intf_ext( + rmnet_ipa3_ctx->mux_channel[index].vchannel_name, + &tx_properties, + &rx_properties, + &ext_properties); + if (ret) { + IPAWANERR_RL("[%d]ipa3_register_intf failed %d\n", + index, + ret); + goto fail; + } + goto end; + } + /* non apq case */ + pyld_sz = rmnet_ipa3_ctx->num_q6_rules * + sizeof(struct ipa_ioc_ext_intf_prop); + ext_ioc_properties = kmalloc(pyld_sz, GFP_KERNEL); + if (!ext_ioc_properties) + return -ENOMEM; + + ext_properties.prop = ext_ioc_properties; + ext_properties.excp_pipe_valid = true; + ext_properties.excp_pipe = IPA_CLIENT_APPS_WAN_CONS; + ext_properties.num_props = rmnet_ipa3_ctx->num_q6_rules; + for (i = 0; i < rmnet_ipa3_ctx->num_q6_rules; i++) { + memcpy(&(ext_properties.prop[i]), + &(ipa3_qmi_ctx->q6_ul_filter_rule[i]), + sizeof(struct ipa_ioc_ext_intf_prop)); + ext_properties.prop[i].mux_id = + rmnet_ipa3_ctx->mux_channel[index].mux_id; + IPAWANDBG("index %d ip: %d rt-tbl:%d\n", i, + ext_properties.prop[i].ip, + ext_properties.prop[i].rt_tbl_idx); + IPAWANDBG("action: %d mux:%d\n", + ext_properties.prop[i].action, + ext_properties.prop[i].mux_id); + } + ret = ipa3_register_intf_ext( + rmnet_ipa3_ctx->mux_channel[index].vchannel_name, + &tx_properties, + &rx_properties, + &ext_properties); + if (ret) { + IPAWANERR_RL("[%s]:ipa3_register_intf failed %d\n", + rmnet_ipa3_ctx->mux_channel[index].vchannel_name, + ret); + goto fail; + } +end: + rmnet_ipa3_ctx->mux_channel[index].ul_flt_reg = true; +fail: + kfree(ext_ioc_properties); + return ret; +} + +static void ipa3_cleanup_deregister_intf(void) +{ + int i; + int ret; + int8_t *v_name; + + for (i = 0; i < rmnet_ipa3_ctx->rmnet_index; i++) { + v_name = rmnet_ipa3_ctx->mux_channel[i].vchannel_name; + + if (rmnet_ipa3_ctx->mux_channel[i].ul_flt_reg) { + ret = ipa_deregister_intf(v_name); + if (ret < 0) { + IPAWANERR("de-register device %s(%d) failed\n", + v_name, + i); + return; + } + IPAWANDBG("de-register device %s(%d) success\n", + v_name, + i); + } + rmnet_ipa3_ctx->mux_channel[i].ul_flt_reg = false; + } +} + +#ifdef INIT_COMPLETION +#define reinit_completion(x) INIT_COMPLETION(*(x)) +#endif /* INIT_COMPLETION */ + +static int __ipa_wwan_open(struct net_device *dev) +{ + struct ipa3_wwan_private *wwan_ptr = netdev_priv(dev); + + IPAWANDBG("[%s] __wwan_open()\n", dev->name); + if (wwan_ptr->device_status != WWAN_DEVICE_ACTIVE) + reinit_completion(&wwan_ptr->resource_granted_completion); + wwan_ptr->device_status = WWAN_DEVICE_ACTIVE; + + if (ipa3_rmnet_res.ipa_napi_enable) + napi_enable(&(wwan_ptr->napi)); + return 0; +} + +/** + * wwan_open() - Opens the wwan network interface. Opens logical + * channel on A2 MUX driver and starts the network stack queue + * + * @dev: network device + * + * Return codes: + * 0: success + * -ENODEV: Error while opening logical channel on A2 MUX driver + */ +static int ipa3_wwan_open(struct net_device *dev) +{ + int rc = 0; + + IPAWANDBG("[%s] wwan_open()\n", dev->name); + rc = __ipa_wwan_open(dev); + if (rc == 0) + netif_start_queue(dev); + return rc; +} + +static int __ipa_wwan_close(struct net_device *dev) +{ + struct ipa3_wwan_private *wwan_ptr = netdev_priv(dev); + int rc = 0; + + if (wwan_ptr->device_status == WWAN_DEVICE_ACTIVE) { + wwan_ptr->device_status = WWAN_DEVICE_INACTIVE; + /* do not close wwan port once up, this causes + * remote side to hang if tried to open again + */ + reinit_completion(&wwan_ptr->resource_granted_completion); + rc = ipa_deregister_intf(dev->name); + if (rc) { + IPAWANERR("[%s]: ipa_deregister_intf failed %d\n", + dev->name, rc); + return rc; + } + return rc; + } else { + return -EBADF; + } +} + +/** + * ipa3_wwan_stop() - Stops the wwan network interface. Closes + * logical channel on A2 MUX driver and stops the network stack + * queue + * + * @dev: network device + * + * Return codes: + * 0: success + * -ENODEV: Error while opening logical channel on A2 MUX driver + */ +static int ipa3_wwan_stop(struct net_device *dev) +{ + IPAWANDBG("[%s]\n", dev->name); + __ipa_wwan_close(dev); + netif_stop_queue(dev); + return 0; +} + +static int ipa3_wwan_change_mtu(struct net_device *dev, int new_mtu) +{ + if (0 > new_mtu || WWAN_DATA_LEN < new_mtu) + return -EINVAL; + IPAWANDBG("[%s] MTU change: old=%d new=%d\n", + dev->name, dev->mtu, new_mtu); + dev->mtu = new_mtu; + return 0; +} + +/** + * ipa3_wwan_xmit() - Transmits an skb. + * + * @skb: skb to be transmitted + * @dev: network device + * + * Return codes: + * 0: success + * NETDEV_TX_BUSY: Error while transmitting the skb. Try again + * later + * -EFAULT: Error while transmitting the skb + */ +static netdev_tx_t ipa3_wwan_xmit(struct sk_buff *skb, struct net_device *dev) +{ + int ret = 0; + bool qmap_check; + struct ipa3_wwan_private *wwan_ptr = netdev_priv(dev); + unsigned long flags; + + if (rmnet_ipa3_ctx->ipa_config_is_apq) { + IPAWANERR_RL("IPA embedded data on APQ platform\n"); + dev_kfree_skb_any(skb); + dev->stats.tx_dropped++; + return NETDEV_TX_OK; + } + + if (skb->protocol != htons(ETH_P_MAP)) { + IPAWANDBG_LOW + ("SW filtering out none QMAP packet received from %s", + current->comm); + dev_kfree_skb_any(skb); + dev->stats.tx_dropped++; + return NETDEV_TX_OK; + } + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 14, 0)) + qmap_check = RMNET_MAP_GET_CD_BIT(skb); +#else + qmap_check = (((struct rmnet_map_header *)(void *)(skb->data))->flags & MAP_CMD_FLAG) ? + true : false; +#endif + spin_lock_irqsave(&wwan_ptr->lock, flags); + /* There can be a race between enabling the wake queue and + * suspend in progress. Check if suspend is pending and + * return from here itself. + */ + if (atomic_read(&rmnet_ipa3_ctx->ap_suspend)) { + netif_stop_queue(dev); + spin_unlock_irqrestore(&wwan_ptr->lock, flags); + return NETDEV_TX_BUSY; + } + if (netif_queue_stopped(dev)) { + if (qmap_check && + atomic_read(&wwan_ptr->outstanding_pkts) < + rmnet_ipa3_ctx->outstanding_high_ctl) { + IPAWANERR("[%s]Queue stop, send ctrl pkts\n", + dev->name); + goto send; + } else { + IPAWANERR("[%s]fatal: %s stopped\n", dev->name, + __func__); + spin_unlock_irqrestore(&wwan_ptr->lock, flags); + return NETDEV_TX_BUSY; + } + } + /* checking High WM hit */ + if (atomic_read(&wwan_ptr->outstanding_pkts) >= + rmnet_ipa3_ctx->outstanding_high) { + if (!qmap_check) { + IPAWANDBG_LOW("pending(%d)/(%d)- stop(%d)\n", + atomic_read(&wwan_ptr->outstanding_pkts), + rmnet_ipa3_ctx->outstanding_high, + netif_queue_stopped(dev)); + IPAWANDBG_LOW("qmap_chk(%d)\n", qmap_check); + netif_stop_queue(dev); + spin_unlock_irqrestore(&wwan_ptr->lock, flags); + return NETDEV_TX_BUSY; + } + } + +send: + /* IPA_PM checking start */ + /* activate the modem pm for clock scaling */ + ipa_pm_activate(rmnet_ipa3_ctx->q6_pm_hdl); + ret = ipa_pm_activate(rmnet_ipa3_ctx->pm_hdl); + + if (ret == -EINPROGRESS) { + netif_stop_queue(dev); + spin_unlock_irqrestore(&wwan_ptr->lock, flags); + return NETDEV_TX_BUSY; + } + if (ret) { + IPAWANERR("[%s] fatal: ipa pm activate failed %d\n", + dev->name, ret); + dev_kfree_skb_any(skb); + dev->stats.tx_dropped++; + spin_unlock_irqrestore(&wwan_ptr->lock, flags); + return NETDEV_TX_OK; + } + /* IPA_PM checking end */ + + /* + * increase the outstanding_pkts count first + * to avoid suspend happens in parallel + * after unlock + */ + atomic_inc(&wwan_ptr->outstanding_pkts); + spin_unlock_irqrestore(&wwan_ptr->lock, flags); + + /* + * both data packets and command will be routed to + * IPA_CLIENT_Q6_WAN_CONS based on status configuration + */ + ret = ipa_tx_dp(IPA_CLIENT_APPS_WAN_PROD, skb, NULL); + if (ret) { + atomic_dec(&wwan_ptr->outstanding_pkts); + if (ret == -EPIPE) { + IPAWANERR_RL("[%s] fatal: pipe is not valid\n", + dev->name); + dev_kfree_skb_any(skb); + dev->stats.tx_dropped++; + return NETDEV_TX_OK; + } + ret = NETDEV_TX_BUSY; + goto out; + } + + dev->stats.tx_packets++; + dev->stats.tx_bytes += skb->len; + ret = NETDEV_TX_OK; +out: + if (atomic_read(&wwan_ptr->outstanding_pkts) == 0) { + ipa_pm_deferred_deactivate(rmnet_ipa3_ctx->pm_hdl); + ipa_pm_deferred_deactivate(rmnet_ipa3_ctx->q6_pm_hdl); + + } + return ret; +} + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 6, 0)) +static void ipa3_wwan_tx_timeout(struct net_device *dev, + unsigned int txqueue) +#else /* Legacy API. */ +static void ipa3_wwan_tx_timeout(struct net_device *dev) +#endif +{ + struct ipa3_wwan_private *wwan_ptr = netdev_priv(dev); + + if (atomic_read(&wwan_ptr->outstanding_pkts) != 0) + IPAWANERR("[%s] data stall in UL, %d outstanding\n", + dev->name, atomic_read(&wwan_ptr->outstanding_pkts)); +} +/** + * apps_ipa_tx_complete_notify() - Rx notify + * + * @priv: driver context + * @evt: event type + * @data: data provided with event + * + * Check that the packet is the one we sent and release it + * This function will be called in defered context in IPA wq. + */ +static void apps_ipa_tx_complete_notify(void *priv, + enum ipa_dp_evt_type evt, + unsigned long data) +{ + struct sk_buff *skb = (struct sk_buff *)data; + struct net_device *dev = (struct net_device *)priv; + struct ipa3_wwan_private *wwan_ptr; + + if (dev != IPA_NETDEV()) { + IPAWANDBG("Received pre-SSR packet completion\n"); + dev_kfree_skb_any(skb); + return; + } + + if (evt != IPA_WRITE_DONE) { + IPAWANERR("unsupported evt on Tx callback, Drop the packet\n"); + dev_kfree_skb_any(skb); + dev->stats.tx_dropped++; + return; + } + + wwan_ptr = netdev_priv(dev); + atomic_dec(&wwan_ptr->outstanding_pkts); + __netif_tx_lock_bh(netdev_get_tx_queue(dev, 0)); + if (!atomic_read(&rmnet_ipa3_ctx->is_ssr) && + netif_queue_stopped(wwan_ptr->net) && + atomic_read(&wwan_ptr->outstanding_pkts) < + rmnet_ipa3_ctx->outstanding_low) { + IPAWANDBG_LOW("Outstanding low (%d) - waking up queue\n", + rmnet_ipa3_ctx->outstanding_low); + netif_wake_queue(wwan_ptr->net); + } + + if (atomic_read(&wwan_ptr->outstanding_pkts) == 0) { + ipa_pm_deferred_deactivate(rmnet_ipa3_ctx->pm_hdl); + ipa_pm_deferred_deactivate(rmnet_ipa3_ctx->q6_pm_hdl); + + } + __netif_tx_unlock_bh(netdev_get_tx_queue(dev, 0)); + dev_kfree_skb_any(skb); +} + +/** + * apps_ipa_packet_receive_notify() - Rx notify + * + * @priv: driver context + * @evt: event type + * @data: data provided with event + * + * IPA will pass a packet to the Linux network stack with skb->data + */ +static void apps_ipa_packet_receive_notify(void *priv, + enum ipa_dp_evt_type evt, + unsigned long data) +{ + struct net_device *dev = (struct net_device *)priv; + + if (evt == IPA_RECEIVE) { + struct sk_buff *skb = (struct sk_buff *)data; + int result = 0; + unsigned int packet_len = skb->len; + + IPAWANDBG_LOW("Rx packet was received"); + skb->dev = IPA_NETDEV(); + skb->protocol = htons(ETH_P_MAP); + skb_set_mac_header(skb, 0); + + /* default traffic uses rx-0 queue. */ + skb_record_rx_queue(skb, 0); + if (ipa3_rmnet_res.ipa_napi_enable) { + trace_rmnet_ipa_netif_rcv_skb3(skb, dev->stats.rx_packets); + result = netif_receive_skb(skb); + } else { + if (dev->stats.rx_packets % IPA_WWAN_RX_SOFTIRQ_THRESH + == 0) { +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 18, 0)) + trace_rmnet_ipa_netifni3(dev->stats.rx_packets); + result = netif_rx_ni(skb); + } else { +#endif + trace_rmnet_ipa_netifrx3(dev->stats.rx_packets); + result = netif_rx(skb); + } + } + + if (result) { + pr_err_ratelimited(DEV_NAME " %s:%d fail on netif_receive_skb\n", + __func__, __LINE__); + dev->stats.rx_dropped++; + } + dev->stats.rx_packets++; + dev->stats.rx_bytes += packet_len; + } else { + IPAWANERR("Invalid evt %d received in wan_ipa_receive\n", evt); + } +} + +/* Send RSC endpoint info to modem using QMI indication message */ +static int ipa_send_wan_pipe_ind_to_modem(int ingress_eps_mask) +{ + struct ipa_endp_desc_indication_msg_v01 req; + struct ipa_ep_id_type_v01 *ep_info; + + if (ingress_eps_mask == IPA_AP_INGRESS_NONE) + return 0; + + memset(&req, 0, sizeof(struct ipa_endp_desc_indication_msg_v01)); + if (ingress_eps_mask & IPA_AP_INGRESS_EP_COALS) { + req.ep_info_len++; + req.ep_info_valid = true; + req.num_eps_valid = true; + req.num_eps++; + ep_info = &req.ep_info[req.ep_info_len - 1]; + ep_info->ep_id = rmnet_ipa3_ctx->ipa3_to_apps_hdl; + ep_info->ic_type = DATA_IC_TYPE_AP_V01; + ep_info->ep_type = DATA_EP_DESC_TYPE_RSC_PROD_V01; + ep_info->ep_status = DATA_EP_STATUS_CONNECTED_V01; + } + + if (ingress_eps_mask & IPA_AP_INGRESS_EP_LOW_LAT) { + req.ep_info_len++; + req.ep_info_valid = true; + req.num_eps_valid = true; + req.num_eps++; + ep_info = &req.ep_info[req.ep_info_len - 1]; + ep_info->ep_id = ipa_get_ep_mapping( + IPA_CLIENT_APPS_WAN_LOW_LAT_CONS); + ep_info->ic_type = DATA_IC_TYPE_AP_V01; + ep_info->ep_type = DATA_EP_DESC_TYPE_EMB_FLOW_CTL_PROD_V01; + ep_info->ep_status = DATA_EP_STATUS_CONNECTED_V01; + req.ep_info_len++; + req.num_eps++; + ep_info = &req.ep_info[req.ep_info_len - 1]; + ep_info->ep_id = ipa_get_ep_mapping( + IPA_CLIENT_APPS_WAN_LOW_LAT_PROD); + ep_info->ic_type = DATA_IC_TYPE_AP_V01; + ep_info->ep_type = DATA_EP_DESC_TYPE_EMB_FLOW_CTL_CONS_V01; + ep_info->ep_status = DATA_EP_STATUS_CONNECTED_V01; + } + + if (req.num_eps > 0) + return ipa3_qmi_send_endp_desc_indication(&req); + else + return 0; +} + +static int handle3_ingress_format(struct net_device *dev, + struct rmnet_ioctl_extended_s *in) +{ + int ret = 0; + struct ipa_sys_connect_params *ipa_wan_ep_cfg; + int ep_idx; + int ingress_eps_mask = IPA_AP_INGRESS_NONE; + bool rmnet_config; + + IPAWANDBG("Get RMNET_IOCTL_SET_INGRESS_DATA_FORMAT\n"); + + ep_idx = ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_CONS); + if (ep_idx == IPA_EP_NOT_ALLOCATED) { + IPAWANDBG("Embedded datapath not supported\n"); + return -EFAULT; + } + + ipa_wan_ep_cfg = &rmnet_ipa3_ctx->ipa_to_apps_ep_cfg; + if ((in->u.data) & RMNET_IOCTL_INGRESS_FORMAT_CHECKSUM) { + if (ipa3_ctx_get_type(IPA_HW_TYPE) >= IPA_HW_v4_5) + ipa_wan_ep_cfg->ipa_ep_cfg.cfg.cs_offload_en = + IPA_ENABLE_CS_DL_QMAP; + else + ipa_wan_ep_cfg->ipa_ep_cfg.cfg.cs_offload_en = + IPA_ENABLE_CS_OFFLOAD_DL; + IPAWANDBG("DL chksum set\n"); + } + + if ((in->u.data) & RMNET_IOCTL_INGRESS_FORMAT_AGG_DATA) { + IPAWANDBG("get AGG size %d count %d\n", + in->u.ingress_format.agg_size, + in->u.ingress_format.agg_count); + + ret = ipa3_disable_apps_wan_cons_deaggr( + in->u.ingress_format.agg_size, + in->u.ingress_format.agg_count); + + if (!ret) { + ipa_wan_ep_cfg->ipa_ep_cfg.aggr.aggr_byte_limit = + in->u.ingress_format.agg_size; + ipa_wan_ep_cfg->ipa_ep_cfg.aggr.aggr_pkt_limit = + in->u.ingress_format.agg_count; + } + } + + if (ipa3_ctx_get_type(IPA_HW_TYPE) >= IPA_HW_v4_5 && + (in->u.data) & RMNET_IOCTL_INGRESS_FORMAT_CHECKSUM) { + ipa_wan_ep_cfg->ipa_ep_cfg.hdr.hdr_len = 8; + rmnet_ipa3_ctx->dl_csum_offload_enabled = true; + } else { + ipa_wan_ep_cfg->ipa_ep_cfg.hdr.hdr_len = 4; + rmnet_ipa3_ctx->dl_csum_offload_enabled = false; + } + + ipa_wan_ep_cfg->ipa_ep_cfg.hdr.hdr_ofst_metadata_valid = 1; + ipa_wan_ep_cfg->ipa_ep_cfg.hdr.hdr_ofst_metadata = 1; + ipa_wan_ep_cfg->ipa_ep_cfg.hdr.hdr_ofst_pkt_size_valid = 1; + ipa_wan_ep_cfg->ipa_ep_cfg.hdr.hdr_ofst_pkt_size = 2; + + ipa_wan_ep_cfg->ipa_ep_cfg.hdr_ext.hdr_total_len_or_pad_valid = true; + ipa_wan_ep_cfg->ipa_ep_cfg.hdr_ext.hdr_total_len_or_pad = 0; + ipa_wan_ep_cfg->ipa_ep_cfg.hdr_ext.hdr_payload_len_inc_padding = true; + ipa_wan_ep_cfg->ipa_ep_cfg.hdr_ext.hdr_total_len_or_pad_offset = 0; + ipa_wan_ep_cfg->ipa_ep_cfg.hdr_ext.hdr_little_endian = 0; + ipa_wan_ep_cfg->ipa_ep_cfg.metadata_mask.metadata_mask = 0xFF000000; + + ipa_wan_ep_cfg->client = IPA_CLIENT_APPS_WAN_CONS; + ingress_eps_mask |= IPA_AP_INGRESS_EP_DEFAULT; + + if (dev->features & NETIF_F_GRO_HW) { + /* Setup coalescing pipes */ + ipa_wan_ep_cfg->client = IPA_CLIENT_APPS_WAN_COAL_CONS; + ingress_eps_mask |= IPA_AP_INGRESS_EP_COALS; + } + ipa_wan_ep_cfg->ext_ioctl_v2 = false; + + ipa_wan_ep_cfg->notify = apps_ipa_packet_receive_notify; + ipa_wan_ep_cfg->priv = dev; + + if (ipa3_rmnet_res.ipa_napi_enable) + ipa_wan_ep_cfg->napi_obj = &(rmnet_ipa3_ctx->wwan_priv->napi); + ipa_wan_ep_cfg->desc_fifo_sz = + ipa3_rmnet_res.wan_rx_desc_size * IPA_FIFO_ELEMENT_SIZE; + + mutex_lock(&rmnet_ipa3_ctx->pipe_handle_guard); + + if (atomic_read(&rmnet_ipa3_ctx->is_ssr)) { + IPAWANDBG("In SSR sequence/recovery\n"); + mutex_unlock(&rmnet_ipa3_ctx->pipe_handle_guard); + return -EFAULT; + } + ret = ipa_setup_sys_pipe(&rmnet_ipa3_ctx->ipa_to_apps_ep_cfg, + &rmnet_ipa3_ctx->ipa3_to_apps_hdl); + + if (ret) { + mutex_unlock(&rmnet_ipa3_ctx->pipe_handle_guard); + goto end; + } + IPAWANDBG("ingress WAN pipe setup successfully\n"); + + if (ipa3_ctx->rmnet_ctl_enable) { + rmnet_config = false; + ret = ipa3_setup_apps_low_lat_cons_pipe(rmnet_config, NULL); + if (ret) + goto low_lat_fail; + ingress_eps_mask |= IPA_AP_INGRESS_EP_LOW_LAT; + IPAWANDBG("ingress low latency pipe setup successfully\n"); + } +low_lat_fail: + mutex_unlock(&rmnet_ipa3_ctx->pipe_handle_guard); + /* construct default WAN RT tbl for IPACM */ + ret = ipa3_setup_a7_qmap_hdr(); + if (ret) + goto end; + + ret = ipa3_setup_dflt_wan_rt_tables(); + if (ret) + ipa3_del_a7_qmap_hdr(); + + /* Sending QMI indication message share RSC/QMAP pipe details*/ + ipa_send_wan_pipe_ind_to_modem(ingress_eps_mask); +end: + if (ret) + IPAWANERR_RL("failed to configure ingress\n"); + + return ret; +} + +/** + * handle3_egress_format() - Egress data format configuration + * + * Setup IPA egress system pipe and Configure: + * header handling, checksum, de-aggregation and fifo size + * + * @dev: network device + * @e: egress configuration + */ +static int handle3_egress_format(struct net_device *dev, + struct rmnet_ioctl_extended_s *e) +{ + int rc; + struct ipa_sys_connect_params *ipa_wan_ep_cfg; + int ep_idx; + bool rmnet_config; + + IPAWANDBG("get RMNET_IOCTL_SET_EGRESS_DATA_FORMAT %x\n", e->u.data); + /* + * in APQ platform, only set QMAP format. + * MHIP is using QMAP format only. + */ + if (rmnet_ipa3_ctx->ipa_config_is_apq) { + /* QMAP */ + rmnet_ipa3_ctx->dl_csum_offload_enabled = false; + /* send aggr_info_qmi */ + rc = ipa3_qmi_set_aggr_info(DATA_AGGR_TYPE_QMAP_V01); + rmnet_ipa3_ctx->ipa_mhi_aggr_formet_set = true; + return rc; + } + + ep_idx = ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_PROD); + if (ep_idx == IPA_EP_NOT_ALLOCATED) { + IPAWANDBG("Embedded datapath not supported\n"); + return -EFAULT; + } + + ipa_wan_ep_cfg = &rmnet_ipa3_ctx->apps_to_ipa_ep_cfg; + if ((e->u.data) & RMNET_IOCTL_EGRESS_FORMAT_CHECKSUM) { + IPAWANDBG("UL chksum set\n"); + ipa_wan_ep_cfg->ipa_ep_cfg.hdr.hdr_len = 8; + ipa_wan_ep_cfg->ipa_ep_cfg.cfg.cs_offload_en = + IPA_ENABLE_CS_OFFLOAD_UL; + ipa_wan_ep_cfg->ipa_ep_cfg.cfg.cs_metadata_hdr_offset = 1; + } else { + ipa_wan_ep_cfg->ipa_ep_cfg.hdr.hdr_len = 4; + } + + if ((e->u.data) & RMNET_IOCTL_EGRESS_FORMAT_AGGREGATION) { + IPAWANDBG("WAN UL Aggregation enabled\n"); + ipa_wan_ep_cfg->ipa_ep_cfg.aggr.aggr_en = IPA_ENABLE_DEAGGR; + ipa_wan_ep_cfg->ipa_ep_cfg.aggr.aggr = IPA_QCMAP; + + ipa_wan_ep_cfg->ipa_ep_cfg.deaggr.packet_offset_valid = false; + + ipa_wan_ep_cfg->ipa_ep_cfg.hdr.hdr_ofst_pkt_size = 2; + + ipa_wan_ep_cfg->ipa_ep_cfg.hdr_ext.hdr_total_len_or_pad_valid = + true; + ipa_wan_ep_cfg->ipa_ep_cfg.hdr_ext.hdr_total_len_or_pad = + IPA_HDR_PAD; + ipa_wan_ep_cfg->ipa_ep_cfg.hdr_ext.hdr_pad_to_alignment = + 2; + ipa_wan_ep_cfg->ipa_ep_cfg.hdr_ext.hdr_payload_len_inc_padding = + true; + ipa_wan_ep_cfg->ipa_ep_cfg.hdr_ext.hdr_total_len_or_pad_offset = + 0; + ipa_wan_ep_cfg->ipa_ep_cfg.hdr_ext.hdr_little_endian = + false; + } else { + IPAWANDBG("WAN UL Aggregation disabled\n"); + ipa_wan_ep_cfg->ipa_ep_cfg.aggr.aggr_en = IPA_BYPASS_AGGR; + } + + ipa_wan_ep_cfg->ipa_ep_cfg.hdr.hdr_ofst_metadata_valid = 1; + /* modem want offset at 0! */ + ipa_wan_ep_cfg->ipa_ep_cfg.hdr.hdr_ofst_metadata = 0; + + ipa_wan_ep_cfg->ipa_ep_cfg.mode.dst = IPA_CLIENT_APPS_WAN_PROD; + ipa_wan_ep_cfg->ipa_ep_cfg.mode.mode = IPA_BASIC; + + ipa_wan_ep_cfg->client = IPA_CLIENT_APPS_WAN_PROD; + ipa_wan_ep_cfg->notify = apps_ipa_tx_complete_notify; + ipa_wan_ep_cfg->desc_fifo_sz = IPA_SYS_TX_DATA_DESC_FIFO_SZ; + ipa_wan_ep_cfg->priv = dev; + ipa_wan_ep_cfg->ext_ioctl_v2 = false; + + mutex_lock(&rmnet_ipa3_ctx->pipe_handle_guard); + if (atomic_read(&rmnet_ipa3_ctx->is_ssr)) { + IPAWANDBG("In SSR sequence/recovery\n"); + mutex_unlock(&rmnet_ipa3_ctx->pipe_handle_guard); + return -EFAULT; + } + rc = ipa_setup_sys_pipe( + ipa_wan_ep_cfg, &rmnet_ipa3_ctx->apps_to_ipa3_hdl); + if (rc) { + IPAWANERR_RL("failed to setup egress endpoint\n"); + mutex_unlock(&rmnet_ipa3_ctx->pipe_handle_guard); + return rc; + } + IPAWANDBG("engress WAN pipe setup successfully\n"); + if (ipa3_ctx->rmnet_ctl_enable) { + rmnet_config = false; + rc = ipa3_setup_apps_low_lat_prod_pipe(rmnet_config, NULL); + if (rc) { + IPAWANERR_RL("failed to setup egress low lat endpoint\n"); + mutex_unlock(&rmnet_ipa3_ctx->pipe_handle_guard); + goto low_lat_fail; + } + IPAWANDBG("engress low lat pipe setup successfully\n"); + } + mutex_unlock(&rmnet_ipa3_ctx->pipe_handle_guard); + +low_lat_fail: + if (rmnet_ipa3_ctx->num_q6_rules != 0) { + /* already got Q6 UL filter rules*/ + if (!ipa3_qmi_ctx->modem_cfg_emb_pipe_flt) { + /* prevent multi-threads accessing num_q6_rules */ + mutex_lock(&rmnet_ipa3_ctx->add_mux_channel_lock); + rc = ipa3_wwan_add_ul_flt_rule_to_ipa(); + mutex_unlock( + &rmnet_ipa3_ctx->add_mux_channel_lock); + } + if (rc) + IPAWANERR_RL("install UL rules failed\n"); + else + rmnet_ipa3_ctx->a7_ul_flt_set = true; + } else { + /* wait Q6 UL filter rules*/ + IPAWANDBG("no UL-rules\n"); + } + rmnet_ipa3_ctx->egress_set = true; + + return rc; +} + +/** + * ipa3_setup_apps_wan_cons_pipes() - wan/coal pipe config + * + * Setup IPA Ingress wan pipes and Configure them: + */ +static int ipa3_setup_apps_wan_cons_pipes( + struct rmnet_ingress_param *ingress_param, + struct rmnet_ipa_pipe_setup_status *pipe_status, + int *ingress_eps_mask, + struct net_device *dev) +{ + struct ipa_sys_connect_params *ipa_wan_ep_cfg; + int ep_idx, coal_ep_idx; + int rc = 0; + int wan_hdl; + + if (ingress_param->pipe_setup_status == IPA_PIPE_SETUP_EXISTS) + return rc; + + coal_ep_idx = ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS); + ep_idx = ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_CONS); + if (ep_idx == IPA_EP_NOT_ALLOCATED) { + IPAWANERR("Embedded datapath not supported\n"); + return rc; + } + + ipa_wan_ep_cfg = &rmnet_ipa3_ctx->ipa_to_apps_ep_cfg; + ipa_wan_ep_cfg->ipa_ep_cfg.cfg.cs_offload_en = + IPA_ENABLE_CS_DL_QMAP; + + if (!ipa3_disable_apps_wan_cons_deaggr( + ingress_param->agg_byte_limit, + ingress_param->agg_pkt_limit)) { + ipa_wan_ep_cfg->ipa_ep_cfg.aggr.aggr_byte_limit = + ingress_param->agg_byte_limit; + ipa_wan_ep_cfg->ipa_ep_cfg.aggr.aggr_pkt_limit = + ingress_param->agg_pkt_limit; + ipa_wan_ep_cfg->ipa_ep_cfg.aggr.aggr_time_limit = + ingress_param->agg_time_limit; + if (ipa3_ctx->ulso_wa && + ingress_param->ingress_ep_type == RMNET_INGRESS_COALS) { + /* WAR: overriding the time limit of coalescing to 0*/ + ipa_wan_ep_cfg->ipa_ep_cfg.aggr.aggr_time_limit = 0; + } + } + + if (ingress_param->cs_offload_en) { + ipa_wan_ep_cfg->ipa_ep_cfg.hdr.hdr_len = 8; + rmnet_ipa3_ctx->dl_csum_offload_enabled = true; + } else { + ipa_wan_ep_cfg->ipa_ep_cfg.hdr.hdr_len = 4; + rmnet_ipa3_ctx->dl_csum_offload_enabled = false; + } + + ipa_wan_ep_cfg->ipa_ep_cfg.hdr.hdr_ofst_metadata_valid = 1; + ipa_wan_ep_cfg->ipa_ep_cfg.hdr.hdr_ofst_metadata = 1; + ipa_wan_ep_cfg->ipa_ep_cfg.hdr.hdr_ofst_pkt_size_valid = 1; + ipa_wan_ep_cfg->ipa_ep_cfg.hdr.hdr_ofst_pkt_size = 2; + + ipa_wan_ep_cfg->ipa_ep_cfg.hdr_ext.hdr_total_len_or_pad_valid + = true; + ipa_wan_ep_cfg->ipa_ep_cfg.hdr_ext.hdr_total_len_or_pad + = 0; + ipa_wan_ep_cfg->ipa_ep_cfg.hdr_ext.hdr_payload_len_inc_padding + = true; + ipa_wan_ep_cfg->ipa_ep_cfg.hdr_ext.hdr_total_len_or_pad_offset + = 0; + ipa_wan_ep_cfg->ipa_ep_cfg.hdr_ext.hdr_little_endian + = 0; + ipa_wan_ep_cfg->ipa_ep_cfg.metadata_mask.metadata_mask + = 0xFF000000; + + if (ingress_param->ingress_ep_type == RMNET_INGRESS_DEFAULT) { + /* Reject the whole ioctl if coal pipe is not setup first */ + if (dev->features & NETIF_F_GRO_HW) { + if (coal_ep_idx == IPA_EP_NOT_ALLOCATED) { + IPAWANERR("Trying to setup def WAN before coals"); + mutex_unlock(&rmnet_ipa3_ctx->pipe_handle_guard); + return -EFAULT; + } + else if (!ipa3_ctx->ep[coal_ep_idx].valid) { + IPAWANERR("Trying to setup def WAN before coals."); + mutex_unlock(&rmnet_ipa3_ctx->pipe_handle_guard); + return -EFAULT; + } + } + + /* Setup default pipe */ + IPAWANDBG("Setting up default pipe\n"); + ipa_wan_ep_cfg->client = IPA_CLIENT_APPS_WAN_CONS; + pipe_status->ep_type = RMNET_INGRESS_DEFAULT; + *ingress_eps_mask |= IPA_AP_INGRESS_EP_DEFAULT; + } else if (ingress_param->ingress_ep_type == + RMNET_INGRESS_COALS && (dev->features & NETIF_F_GRO_HW)) { + /* Setup coalescing pipes */ + IPAWANDBG("Setting up coalescing pipe\n"); + ipa_wan_ep_cfg->client = IPA_CLIENT_APPS_WAN_COAL_CONS; + pipe_status->ep_type = RMNET_INGRESS_COALS; + *ingress_eps_mask |= IPA_AP_INGRESS_EP_COALS; + } else { + return rc; + } + + ipa_wan_ep_cfg->notify = apps_ipa_packet_receive_notify; + ipa_wan_ep_cfg->priv = dev; + + if (ipa3_rmnet_res.ipa_napi_enable) + ipa_wan_ep_cfg->napi_obj = &(rmnet_ipa3_ctx->wwan_priv->napi); + ipa_wan_ep_cfg->desc_fifo_sz = + ipa3_rmnet_res.wan_rx_desc_size * IPA_FIFO_ELEMENT_SIZE; + + if (atomic_read(&rmnet_ipa3_ctx->is_ssr)) { + IPAWANERR("In SSR sequence/recovery\n"); + return rc; + } + ipa_wan_ep_cfg->ext_ioctl_v2 = true; + ipa_wan_ep_cfg->int_modt = ingress_param->int_modt; + ipa_wan_ep_cfg->int_modc = ingress_param->int_modc; + ipa_wan_ep_cfg->buff_size = ingress_param->buff_size; + + /* Pass dummy handle if coal is already setup to avoid overriding */ + if (ipa_wan_ep_cfg->client == IPA_CLIENT_APPS_WAN_CONS && + (*ingress_eps_mask & IPA_AP_INGRESS_EP_COALS)) + rc = ipa_setup_sys_pipe(&rmnet_ipa3_ctx->ipa_to_apps_ep_cfg, + &wan_hdl); + else + rc = ipa_setup_sys_pipe(&rmnet_ipa3_ctx->ipa_to_apps_ep_cfg, + &rmnet_ipa3_ctx->ipa3_to_apps_hdl); + + if (rc) { + pipe_status->status = IPA_PIPE_SETUP_FAILURE; + IPAWANERR("failed to setup default/coal pipe rc = %d\n", rc); + return rc; + } + + IPAWANDBG("Ingress default/coal pipe setup successfully\n"); + + ingress_param->pipe_setup_status = IPA_PIPE_SETUP_SUCCESS; + /* caching the success status of the pipe */ + pipe_status->status = IPA_PIPE_SETUP_EXISTS; + + return rc; +} + +/** + * handle3_ingress_format_v2() - Ingress data format configuration + * + * Setup IPA Ingress system pipes and Configure them: + * + * @dev: network device + * @ioctl_ptr: Pointer to ingress pipes' config info + */ +static int handle3_ingress_format_v2(struct net_device *dev, + __u64 ioctl_ptr) +{ + struct ingress_format_v2 ingress_ioctl_v2_data; + struct rmnet_ingress_param ingress_param[RMNET_INGRESS_MAX]; + int i, j; + bool rmnet_config; + int rc = 0; + + if(copy_from_user(&ingress_ioctl_v2_data, u64_to_user_ptr(ioctl_ptr), + sizeof(struct ingress_format_v2))) { + IPAWANERR_RL("failed to copy ingress extended ioctl v2 data\n"); + return -EFAULT; + } + + if(ingress_ioctl_v2_data.number_of_eps > + RMNET_INGRESS_MAX) { + IPAWANERR_RL("Ingress pipe count mismatch\n"); + return -EFAULT; + } + + if(ingress_ioctl_v2_data.ingress_param_size != + sizeof(struct rmnet_ingress_param)) { + IPAWANERR_RL("Ingress pipe param size mismatch\n"); + return -EFAULT; + } + + if(copy_from_user(&ingress_param, u64_to_user_ptr( + ingress_ioctl_v2_data.ingress_param_ptr), + sizeof(struct rmnet_ingress_param) * + ingress_ioctl_v2_data.number_of_eps)) { + IPAWANERR_RL("Failed to copy all ingress pipes' params\n"); + return -EFAULT; + } + + IPAWANDBG("ingress_ioctl_v2_data.number_of_eps = %d\n", + ingress_ioctl_v2_data.number_of_eps); + + mutex_lock(&rmnet_ipa3_ctx->pipe_handle_guard); + + for (i = 0; i < ingress_ioctl_v2_data.number_of_eps; i++) { + ingress_param[i].pipe_setup_status = IPA_PIPE_SETUP_FAILURE; + IPAWANDBG("pipe ep_type = %d cs_offload_en = %d buff_size =%d\n", + ingress_param[i].ingress_ep_type, + ingress_param[i].cs_offload_en, + ingress_param[i].buff_size); + IPAWANDBG("agg_limit byte =%d time =%d pkt =%d\n", + ingress_param[i].agg_byte_limit, + ingress_param[i].agg_time_limit, + ingress_param[i].agg_pkt_limit); + IPAWANDBG("int_modt = %d int_modc = %d\n", + ingress_param[i].int_modt, ingress_param[i].int_modc); + if (ingress_param[i].ingress_ep_type == RMNET_INGRESS_DEFAULT || + ingress_param[i].ingress_ep_type == RMNET_INGRESS_COALS) { + + memset(&rmnet_ipa3_ctx->ipa_to_apps_ep_cfg, 0, + sizeof(struct ipa_sys_connect_params)); + + /* Searching through the static table, if pipe exists already */ + for (j = 0; j < RMNET_INGRESS_MAX; j++) { + if (ingress_param[i].ingress_ep_type == + RMNET_INGRESS_DEFAULT && + ingress_pipe_status[j].ep_type == + RMNET_INGRESS_DEFAULT && + ingress_pipe_status[j].status == IPA_PIPE_SETUP_EXISTS) { + ingress_param[i].pipe_setup_status = + IPA_PIPE_SETUP_EXISTS; + IPAWANERR_RL("Receiving ingress wan default ioctl again\n"); + break; + } + } + + /* Searching through the static table, if pipe exists already */ + for (j = 0; j < RMNET_INGRESS_MAX; j++) { + if (ingress_param[i].ingress_ep_type == RMNET_INGRESS_COALS && + ingress_pipe_status[j].ep_type == RMNET_INGRESS_COALS && + ingress_pipe_status[j].status == IPA_PIPE_SETUP_EXISTS) { + ingress_param[i].pipe_setup_status = + IPA_PIPE_SETUP_EXISTS; + IPAWANERR_RL("Receiving ingress coal ioctl again\n"); + break; + } + } + + rc = ipa3_setup_apps_wan_cons_pipes(&ingress_param[i], + &ingress_pipe_status[i], + &rmnet_ipa3_ctx->ingress_eps_mask, + dev); + + if (rc == -EFAULT) { + IPAWANERR_RL("Failed to setup wan/coal cons pipes\n"); + mutex_unlock(&rmnet_ipa3_ctx->pipe_handle_guard); + return rc; + } + + } else if (ingress_param[i].ingress_ep_type == + RMNET_INGRESS_LOW_LAT_CTRL) { + /* Searching through the static table, if pipe exists already */ + for (j = 0; j < RMNET_INGRESS_MAX; j++) { + if (ingress_pipe_status[j].ep_type == + RMNET_INGRESS_LOW_LAT_CTRL && + ingress_pipe_status[j].status == IPA_PIPE_SETUP_EXISTS) { + ingress_param[i].pipe_setup_status + = IPA_PIPE_SETUP_EXISTS; + IPAWANERR_RL("Receiving ingress low lat ctrl ioctl again"); + break; + } + } + + if (ipa3_ctx->rmnet_ctl_enable && + (ingress_param[i].pipe_setup_status == IPA_PIPE_SETUP_EXISTS)) + continue; + + ingress_pipe_status[i].ep_type = RMNET_INGRESS_LOW_LAT_CTRL; + rmnet_config = true; + rc = ipa3_setup_apps_low_lat_cons_pipe(rmnet_config, + &ingress_param[i]); + if (rc) { + IPAWANERR_RL("failed to setup ingress low lat endpoint\n"); + ingress_pipe_status[i].status = IPA_PIPE_SETUP_FAILURE; + continue; + } + rmnet_ipa3_ctx->ingress_eps_mask |= IPA_AP_INGRESS_EP_LOW_LAT; + IPAWANDBG("Ingress LOW LAT CTRL pipe setup successfully\n"); + ingress_param[i].pipe_setup_status = IPA_PIPE_SETUP_SUCCESS; + /* caching the success status of the pipe */ + ingress_pipe_status[i].status = IPA_PIPE_SETUP_EXISTS; + + } else if (ingress_param[i].ingress_ep_type == + RMNET_INGRESS_LOW_LAT_DATA) { + /* Searching through the static table, if pipe exists already */ + for (j = 0; j < RMNET_INGRESS_MAX; j++) { + if (ingress_pipe_status[j].ep_type == + RMNET_INGRESS_LOW_LAT_DATA && + ingress_pipe_status[j].status == IPA_PIPE_SETUP_EXISTS) { + ingress_param[i].pipe_setup_status + = IPA_PIPE_SETUP_EXISTS; + IPAWANERR_RL("Receiving ingress low lat data ioctl again"); + break; + } + } + + if (ipa3_ctx->rmnet_ll_enable && + (ingress_param[i].pipe_setup_status == IPA_PIPE_SETUP_EXISTS)) + continue; + + ingress_pipe_status[i].ep_type = RMNET_INGRESS_LOW_LAT_DATA; + rc = ipa3_setup_apps_low_lat_data_cons_pipe( + &ingress_param[i], dev); + if (rc) { + IPAWANERR_RL("failed to setup ingress low lat data endpoint\n"); + ingress_pipe_status[i].status = IPA_PIPE_SETUP_FAILURE; + continue; + } + rmnet_ipa3_ctx->ingress_eps_mask |= IPA_AP_INGRESS_EP_LOW_LAT_DATA; + IPAWANDBG("Ingress LOW LAT DATA pipe setup successfully\n"); + ingress_param[i].pipe_setup_status = IPA_PIPE_SETUP_SUCCESS; + /* caching the success status of the pipe */ + ingress_pipe_status[i].status = IPA_PIPE_SETUP_EXISTS; + } else { + IPAWANERR_RL("Ingress ep_type not defined\n"); + } + } + + if(copy_to_user(u64_to_user_ptr(ingress_ioctl_v2_data.ingress_param_ptr), + &ingress_param, + sizeof(struct rmnet_ingress_param) * + ingress_ioctl_v2_data.number_of_eps)) { + IPAWANERR_RL("Ingress copy to user failed\n"); + mutex_unlock(&rmnet_ipa3_ctx->pipe_handle_guard); + return -EFAULT; + } + + mutex_unlock(&rmnet_ipa3_ctx->pipe_handle_guard); + + if ((dev->features & NETIF_F_GRO_HW) ? (rmnet_ipa3_ctx->ingress_eps_mask & + (IPA_AP_INGRESS_EP_DEFAULT | IPA_AP_INGRESS_EP_COALS)) : ( + rmnet_ipa3_ctx->ingress_eps_mask & IPA_AP_INGRESS_EP_DEFAULT)) { + if (rmnet_ipa3_ctx->wan_rt_table_setup) { + IPAWANERR_RL("WAN rt table already exists\n"); + return -EPERM; + } + /* construct default WAN RT tbl for IPACM */ + rc = ipa3_setup_a7_qmap_hdr(); + if (rc) { + IPAWANERR_RL("A7 QMAP header setup failed\n"); + return -EFAULT; + } + + rc = ipa3_setup_dflt_wan_rt_tables(); + if (rc) { + ipa3_del_a7_qmap_hdr(); + return rc; + } + + if(ipa3_ctx->rmnet_ll_enable) { + rc = ipa3_setup_low_lat_rt_rules(); + if (rc) + IPAWANERR_RL("low lat rt rule add failed = %d\n", rc); + } + /* Sending QMI indication message share RSC/QMAP pipe details*/ + IPAWANDBG("ingress_ep_mask = %d\n", rmnet_ipa3_ctx->ingress_eps_mask); + ipa_send_wan_pipe_ind_to_modem(rmnet_ipa3_ctx->ingress_eps_mask); + rmnet_ipa3_ctx->wan_rt_table_setup = true; + } + return 0; +} + +/** + * ipa3_setup_apps_wan_prod_pipes() - wan prod pipe config + * + * Setup IPA egress wan pipes and Configure them: + */ +static int ipa3_setup_apps_wan_prod_pipes( + struct rmnet_egress_param *egress_param, + struct rmnet_ipa_pipe_setup_status *pipe_status, + struct net_device *dev) +{ + struct ipa_sys_connect_params *ipa_wan_ep_cfg; + int ep_idx; + int rc = 0; + + if(egress_param->pipe_setup_status == IPA_PIPE_SETUP_EXISTS) + return rc; + + ep_idx = ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_PROD); + if (ep_idx == IPA_EP_NOT_ALLOCATED) { + IPAWANERR("Embedded datapath not supported\n"); + return rc; + } + + if (!egress_param->cs_offload_en && egress_param->ulso_en) { + /* cs_offload has to be enabled for ULSO */ + IPAWANERR("ULSO enabled but cs_offload not enabled\n"); + pipe_status->status = IPA_PIPE_SETUP_FAILURE; + return rc; + } + ipa_wan_ep_cfg = &rmnet_ipa3_ctx->apps_to_ipa_ep_cfg; + if (egress_param->cs_offload_en && + (dev->features & RMNET_IPA_ULCS_FEATURE)) { + IPAWANDBG("UL Chksum set\n"); + ipa_wan_ep_cfg->ipa_ep_cfg.hdr.hdr_len = 8; + ipa_wan_ep_cfg->ipa_ep_cfg.cfg.cs_offload_en + = IPA_ENABLE_CS_OFFLOAD_UL; + ipa_wan_ep_cfg->ipa_ep_cfg.cfg.cs_metadata_hdr_offset + = 1; + if (egress_param->ulso_en && + (dev->features & RMNET_IPA_ULSO_FEATURE)) { + IPAWANDBG("ULSO set\n"); + ipa_wan_ep_cfg->ipa_ep_cfg.ulso.ipid_min_max_idx = + egress_param->ipid_min_max_idx; + ipa_wan_ep_cfg->ipa_ep_cfg.ulso.is_ulso_pipe = true; + } + } else { + ipa_wan_ep_cfg->ipa_ep_cfg.hdr.hdr_len = 4; + ipa_wan_ep_cfg->ipa_ep_cfg.cfg.cs_offload_en + = IPA_DISABLE_CS_OFFLOAD; + } + + if (egress_param->aggr_en) { + IPAWANDBG("WAN UL Aggr enabled\n"); + ipa_wan_ep_cfg->ipa_ep_cfg.aggr.aggr_en = IPA_ENABLE_DEAGGR; + ipa_wan_ep_cfg->ipa_ep_cfg.aggr.aggr = IPA_QCMAP; + ipa_wan_ep_cfg->ipa_ep_cfg.deaggr.packet_offset_valid = false; + ipa_wan_ep_cfg->ipa_ep_cfg.hdr.hdr_ofst_pkt_size = 2; + ipa_wan_ep_cfg-> + ipa_ep_cfg.hdr_ext.hdr_total_len_or_pad_valid = true; + ipa_wan_ep_cfg-> + ipa_ep_cfg.hdr_ext.hdr_total_len_or_pad = IPA_HDR_PAD; + ipa_wan_ep_cfg->ipa_ep_cfg.hdr_ext.hdr_pad_to_alignment = 2; + ipa_wan_ep_cfg-> + ipa_ep_cfg.hdr_ext.hdr_payload_len_inc_padding = true; + ipa_wan_ep_cfg-> + ipa_ep_cfg.hdr_ext.hdr_total_len_or_pad_offset = 0; + ipa_wan_ep_cfg->ipa_ep_cfg.hdr_ext.hdr_little_endian = false; + } else { + IPAWANERR("WAN UL Aggregation disabled\n"); + ipa_wan_ep_cfg->ipa_ep_cfg.aggr.aggr_en = IPA_BYPASS_AGGR; + } + + ipa_wan_ep_cfg->ipa_ep_cfg.hdr.hdr_ofst_metadata_valid = 1; + /* modem want offset at 0! */ + ipa_wan_ep_cfg->ipa_ep_cfg.hdr.hdr_ofst_metadata = 0; + ipa_wan_ep_cfg->ipa_ep_cfg.mode.dst = IPA_CLIENT_APPS_WAN_PROD; + ipa_wan_ep_cfg->ipa_ep_cfg.mode.mode = IPA_BASIC; + ipa_wan_ep_cfg->client = IPA_CLIENT_APPS_WAN_PROD; + ipa_wan_ep_cfg->notify = apps_ipa_tx_complete_notify; + ipa_wan_ep_cfg->desc_fifo_sz = IPA_SYS_TX_DATA_DESC_FIFO_SZ; + ipa_wan_ep_cfg->priv = dev; + + ipa_wan_ep_cfg->ext_ioctl_v2 = true; + ipa_wan_ep_cfg->int_modt = egress_param->int_modt; + ipa_wan_ep_cfg->int_modc = egress_param->int_modc; + if (atomic_read(&rmnet_ipa3_ctx->is_ssr)) { + IPAWANERR("In SSR sequence/recovery\n"); + return rc; + } + + pipe_status->ep_type = RMNET_EGRESS_DEFAULT; + + rc = ipa_setup_sys_pipe( + ipa_wan_ep_cfg, &rmnet_ipa3_ctx->apps_to_ipa3_hdl); + + if (rc) { + IPAWANERR("failed to setup egress default pipe\n"); + pipe_status->status = IPA_PIPE_SETUP_FAILURE; + return rc; + } + + IPAWANDBG("Egress WAN pipe setup successful\n"); + egress_param->pipe_setup_status = IPA_PIPE_SETUP_SUCCESS; + /* caching the success status of the pipe */ + pipe_status->status = IPA_PIPE_SETUP_EXISTS; + + return rc; +} + +/** + * handle3_egress_format_v2() - Egress data format configuration + * + * Setup IPA egress system pipes and Configure them: + * + * @dev: network device + * @ioctl_ptr: Pointer to egress pipes' config info + */ +static int handle3_egress_format_v2(struct net_device *dev, + __u64 ioctl_ptr) +{ + struct egress_format_v2 egress_ioctl_v2_data; + struct rmnet_egress_param egress_param[RMNET_EGRESS_MAX]; + int i, j; + int rc = 0; + bool rmnet_config; + + if(copy_from_user(&egress_ioctl_v2_data, u64_to_user_ptr(ioctl_ptr), + sizeof(struct egress_format_v2))) { + IPAWANERR_RL("failed to copy egress extended ioctl v2 data\n"); + return -EFAULT; + } + + if(egress_ioctl_v2_data.number_of_eps > + RMNET_EGRESS_MAX) { + IPAWANERR_RL("Egress pipe count mismatch = %d\n", + egress_ioctl_v2_data.number_of_eps); + return -EFAULT; + } + + if(egress_ioctl_v2_data.egress_param_size != + sizeof(struct rmnet_egress_param)) { + IPAWANERR_RL("Egress pipe param size mismatch\n"); + return -EFAULT; + } + + if(copy_from_user(&egress_param, u64_to_user_ptr( + egress_ioctl_v2_data.egress_param_ptr), + sizeof(struct rmnet_egress_param) * + egress_ioctl_v2_data.number_of_eps)) { + IPAWANERR_RL("Failed to copy all egress pipes' params\n"); + return -EFAULT; + } + + IPAWANDBG("egress_ioctl_v2_data.number_of_eps = %d\n", + egress_ioctl_v2_data.number_of_eps); + + mutex_lock(&rmnet_ipa3_ctx->pipe_handle_guard); + + for (i = 0; i < egress_ioctl_v2_data.number_of_eps; i++) { + egress_param[i].pipe_setup_status = IPA_PIPE_SETUP_FAILURE; + IPAWANDBG("cs_offload_en = %d, aggr_en = %d, ulso_en = %d\n", + egress_param[i].cs_offload_en, + egress_param[i].aggr_en, + egress_param[i].ulso_en); + IPAWANDBG("ipid_min_max_idx = %d, int_modt = %d, int_modc = %d\n", + egress_param[i].ipid_min_max_idx, + egress_param[i].int_modt, + egress_param[i].int_modc); + if (egress_param[i].egress_ep_type == RMNET_EGRESS_DEFAULT) { + /* Searching through the static table, if pipe exists already */ + for (j = 0; j < RMNET_EGRESS_MAX; j++) { + if (egress_pipe_status[j].ep_type == RMNET_EGRESS_DEFAULT && + egress_pipe_status[j].status == IPA_PIPE_SETUP_EXISTS) { + IPAWANERR_RL("Receiving egress default ioctl again"); + egress_param[i].pipe_setup_status = IPA_PIPE_SETUP_EXISTS; + break; + } + } + + rc = ipa3_setup_apps_wan_prod_pipes(&egress_param[i], + &egress_pipe_status[i], + dev); + + if (rc == -EFAULT) { + IPAWANERR_RL("Failed to setup wan prod pipes\n"); + mutex_unlock(&rmnet_ipa3_ctx->pipe_handle_guard); + return rc; + } + + } else if (egress_param[i].egress_ep_type == + RMNET_EGRESS_LOW_LAT_CTRL) { + /* Searching through the static table, if pipe exists already */ + for (j = 0; j < RMNET_EGRESS_MAX; j++) { + if (egress_pipe_status[j].ep_type == + RMNET_EGRESS_LOW_LAT_CTRL && + egress_pipe_status[j].status == IPA_PIPE_SETUP_EXISTS) { + egress_param[i].pipe_setup_status = IPA_PIPE_SETUP_EXISTS; + IPAWANERR_RL("Receiving egress low lat ioctl again"); + break; + } + } + + if (ipa3_ctx->rmnet_ctl_enable && + (egress_param[i].pipe_setup_status == IPA_PIPE_SETUP_EXISTS)) + continue; + + egress_pipe_status[i].ep_type = RMNET_EGRESS_LOW_LAT_CTRL; + + rmnet_config = true; + rc = ipa3_setup_apps_low_lat_prod_pipe( + rmnet_config, &egress_param[i]); + if (rc) { + IPAWANERR_RL("failed to setup egress low lat endpoint\n"); + egress_pipe_status[i].status = IPA_PIPE_SETUP_FAILURE; + continue; + } + IPAWANDBG("Egress LOW LAT CTRL pipe setup successfully\n"); + egress_param[i].pipe_setup_status = IPA_PIPE_SETUP_SUCCESS; + /* caching the success status of the pipe */ + egress_pipe_status[i].status = IPA_PIPE_SETUP_EXISTS; + + } else if (egress_param[i].egress_ep_type == + RMNET_EGRESS_LOW_LAT_DATA) { + /* Searching through the static table, if pipe exists already */ + for (j = 0; j < RMNET_EGRESS_MAX; j++) { + if (egress_pipe_status[j].ep_type == + RMNET_EGRESS_LOW_LAT_DATA && + egress_pipe_status[j].status == IPA_PIPE_SETUP_EXISTS) { + egress_param[i].pipe_setup_status = IPA_PIPE_SETUP_EXISTS; + IPAWANERR_RL("Receiving egress low lat data ioctl again"); + break; + } + } + + if (ipa3_ctx->rmnet_ll_enable && + (egress_param[i].pipe_setup_status == IPA_PIPE_SETUP_EXISTS)) + continue; + + egress_pipe_status[i].ep_type = RMNET_EGRESS_LOW_LAT_DATA; + + rc = ipa3_setup_apps_low_lat_data_prod_pipe( + &egress_param[i], dev); + if (rc) { + IPAWANERR("failed to setup egress low lat data endpoint\n"); + egress_pipe_status[i].status = IPA_PIPE_SETUP_FAILURE; + continue; + } + IPAWANDBG("Egress LOW LAT DATA pipe setup successfully\n"); + egress_param[i].pipe_setup_status = IPA_PIPE_SETUP_SUCCESS; + /* caching the success status of the pipe */ + egress_pipe_status[i].status = IPA_PIPE_SETUP_EXISTS; + } else { + IPAWANERR_RL("Egress ep type not defined"); + } + } + + if(copy_to_user(u64_to_user_ptr(egress_ioctl_v2_data.egress_param_ptr), + &egress_param, + sizeof(struct rmnet_egress_param) * egress_ioctl_v2_data.number_of_eps)) { + IPAWANERR_RL("Egress copy to user failed\n"); + mutex_unlock(&rmnet_ipa3_ctx->pipe_handle_guard); + return -EFAULT; + } + mutex_unlock(&rmnet_ipa3_ctx->pipe_handle_guard); + rmnet_ipa3_ctx->egress_set = true; + + return 0; +} + +/** + * ipa3_wwan_ioctl() - I/O control for wwan network driver. + * + * @dev: network device + * @ifr: ignored + * @cmd: cmd to be excecuded. can be one of the following: + * IPA_WWAN_IOCTL_OPEN - Open the network interface + * IPA_WWAN_IOCTL_CLOSE - Close the network interface + * + * Return codes: + * 0: success + * NETDEV_TX_BUSY: Error while transmitting the skb. Try again + * later + * -EFAULT: Error while transmitting the skb + */ +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(5, 14, 14)) +static int ipa3_wwan_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) +#else +static int ipa3_wwan_ioctl(struct net_device *dev, struct ifreq *ifr, void __user *data, int cmd) +#endif +{ + int rc = 0; + int mru = 1000, epid = 1, mux_index, len, epid_ll = 5; + struct ipa_msg_meta msg_meta; + struct ipa_wan_msg *wan_msg = NULL; + struct rmnet_ioctl_extended_s ext_ioctl_data; + struct rmnet_ioctl_extended_s_v2 ext_ioctl_v2_data; + struct rmnet_ioctl_data_s ioctl_data; + struct ipa3_rmnet_mux_val *mux_channel; + int rmnet_index; + uint32_t mux_id; + int8_t *v_name; + struct mutex *mux_mutex_ptr; + int wan_ep, rmnet_ll_ep; + bool tcp_en = false, udp_en = false; + bool mtu_v4_set = false, mtu_v6_set = false; + enum ipa_ip_type iptype; + + IPAWANDBG("rmnet_ipa got ioctl number 0x%08x", cmd); + switch (cmd) { + /* Set Ethernet protocol */ + case RMNET_IOCTL_SET_LLP_ETHERNET: + break; + /* Set RAWIP protocol */ + case RMNET_IOCTL_SET_LLP_IP: + break; + /* Get link protocol */ + case RMNET_IOCTL_GET_LLP: + ioctl_data.u.operation_mode = RMNET_MODE_LLP_IP; + if (copy_to_user(ifr->ifr_ifru.ifru_data, &ioctl_data, + sizeof(struct rmnet_ioctl_data_s))) + rc = -EFAULT; + break; + /* Set QoS header enabled */ + case RMNET_IOCTL_SET_QOS_ENABLE: + return -EINVAL; + /* Set QoS header disabled */ + case RMNET_IOCTL_SET_QOS_DISABLE: + break; + /* Get QoS header state */ + case RMNET_IOCTL_GET_QOS: + ioctl_data.u.operation_mode = RMNET_MODE_NONE; + if (copy_to_user(ifr->ifr_ifru.ifru_data, &ioctl_data, + sizeof(struct rmnet_ioctl_data_s))) + rc = -EFAULT; + break; + /* Get operation mode */ + case RMNET_IOCTL_GET_OPMODE: + ioctl_data.u.operation_mode = RMNET_MODE_LLP_IP; + if (copy_to_user(ifr->ifr_ifru.ifru_data, &ioctl_data, + sizeof(struct rmnet_ioctl_data_s))) + rc = -EFAULT; + break; + /* Open transport port */ + case RMNET_IOCTL_OPEN: + break; + /* Close transport port */ + case RMNET_IOCTL_CLOSE: + break; + /* Flow enable */ + case RMNET_IOCTL_FLOW_ENABLE: + IPAWANERR_RL("RMNET_IOCTL_FLOW_ENABLE not supported\n"); + rc = -EFAULT; + break; + /* Flow disable */ + case RMNET_IOCTL_FLOW_DISABLE: + IPAWANERR_RL("RMNET_IOCTL_FLOW_DISABLE not supported\n"); + rc = -EFAULT; + break; + /* Set flow handle */ + case RMNET_IOCTL_FLOW_SET_HNDL: + break; + + /* Extended IOCTLs */ + case RMNET_IOCTL_EXTENDED: + if (!ns_capable(dev_net(dev)->user_ns, CAP_NET_ADMIN)) + return -EPERM; + IPAWANDBG("get ioctl: RMNET_IOCTL_EXTENDED\n"); + if (copy_from_user(&ext_ioctl_data, + (u8 *)ifr->ifr_ifru.ifru_data, + sizeof(struct rmnet_ioctl_extended_s))) { + IPAWANERR_RL("failed to copy extended ioctl data\n"); + rc = -EFAULT; + break; + } + switch (ext_ioctl_data.extended_ioctl) { + /* Get features */ + case RMNET_IOCTL_GET_SUPPORTED_FEATURES: + IPAWANDBG("get RMNET_IOCTL_GET_SUPPORTED_FEATURES\n"); + ext_ioctl_data.u.data = + (RMNET_IOCTL_FEAT_NOTIFY_MUX_CHANNEL | + RMNET_IOCTL_FEAT_SET_EGRESS_DATA_FORMAT | + RMNET_IOCTL_FEAT_SET_INGRESS_DATA_FORMAT); + if (copy_to_user((u8 *)ifr->ifr_ifru.ifru_data, + &ext_ioctl_data, + sizeof(struct rmnet_ioctl_extended_s))) + rc = -EFAULT; + break; + /* Set MRU */ + case RMNET_IOCTL_SET_MRU: + mru = ext_ioctl_data.u.data; + IPAWANDBG("get MRU size %d\n", + ext_ioctl_data.u.data); + break; + /* Get MRU */ + case RMNET_IOCTL_GET_MRU: + ext_ioctl_data.u.data = mru; + if (copy_to_user((u8 *)ifr->ifr_ifru.ifru_data, + &ext_ioctl_data, + sizeof(struct rmnet_ioctl_extended_s))) + rc = -EFAULT; + break; + /* GET SG support */ + case RMNET_IOCTL_GET_SG_SUPPORT: + ext_ioctl_data.u.data = + ipa3_rmnet_res.ipa_advertise_sg_support; + if (copy_to_user((u8 *)ifr->ifr_ifru.ifru_data, + &ext_ioctl_data, + sizeof(struct rmnet_ioctl_extended_s))) + rc = -EFAULT; + break; + /* Get endpoint ID */ + case RMNET_IOCTL_GET_EPID: + IPAWANDBG("get ioctl: RMNET_IOCTL_GET_EPID\n"); + ext_ioctl_data.u.data = epid; + if (copy_to_user((u8 *)ifr->ifr_ifru.ifru_data, + &ext_ioctl_data, + sizeof(struct rmnet_ioctl_extended_s))) + rc = -EFAULT; + if (copy_from_user(&ext_ioctl_data, + (u8 *)ifr->ifr_ifru.ifru_data, + sizeof(struct rmnet_ioctl_extended_s))) { + IPAWANERR_RL("copy extended ioctl data failed\n"); + rc = -EFAULT; + break; + } + IPAWANDBG("RMNET_IOCTL_GET_EPID return %d\n", + ext_ioctl_data.u.data); + break; + /* Endpoint pair */ + case RMNET_IOCTL_GET_EP_PAIR: + IPAWANDBG("get ioctl: RMNET_IOCTL_GET_EP_PAIR\n"); + wan_ep = ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_CONS); + if (wan_ep == IPA_EP_NOT_ALLOCATED) { + IPAWANERR_RL("Embedded datapath not supported\n"); + rc = -EFAULT; + break; + } + ext_ioctl_data.u.ipa_ep_pair.producer_pipe_num = + wan_ep; + + wan_ep = ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_PROD); + if (wan_ep == IPA_EP_NOT_ALLOCATED) { + IPAWANERR_RL("Embedded datapath not supported\n"); + rc = -EFAULT; + break; + } + ext_ioctl_data.u.ipa_ep_pair.consumer_pipe_num = + wan_ep; + if (copy_to_user((u8 *)ifr->ifr_ifru.ifru_data, + &ext_ioctl_data, + sizeof(struct rmnet_ioctl_extended_s))) + rc = -EFAULT; + if (copy_from_user(&ext_ioctl_data, + (u8 *)ifr->ifr_ifru.ifru_data, + sizeof(struct rmnet_ioctl_extended_s))) { + IPAWANERR_RL("copy extended ioctl data failed\n"); + rc = -EFAULT; + break; + } + IPAWANDBG("RMNET_IOCTL_GET_EP_PAIR c: %d p: %d\n", + ext_ioctl_data.u.ipa_ep_pair.consumer_pipe_num, + ext_ioctl_data.u.ipa_ep_pair.producer_pipe_num); + break; + /* Get endpoint ID for LL */ + case RMNET_IOCTL_GET_EPID_LL: + IPAWANDBG("get ioctl: RMNET_IOCTL_GET_EPID_LL\n"); + ext_ioctl_data.u.data = epid_ll; + if (copy_to_user((u8 *)ifr->ifr_ifru.ifru_data, + &ext_ioctl_data, + sizeof(struct rmnet_ioctl_extended_s))) + rc = -EFAULT; + IPAWANDBG("RMNET_IOCTL_GET_EPID_LL return %d\n", + ext_ioctl_data.u.data); + break; + /* Endpoint pair */ + case RMNET_IOCTL_GET_EP_PAIR_LL: + IPAWANDBG("get ioctl: RMNET_IOCTL_GET_EP_PAIR_LL\n"); + rmnet_ll_ep = + ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_CONS); + if (rmnet_ll_ep == IPA_EP_NOT_ALLOCATED) { + IPAWANERR_RL("Embedded datapath not supported\n"); + rc = -EFAULT; + break; + } + ext_ioctl_data.u.ipa_ep_pair.producer_pipe_num = + rmnet_ll_ep; + + rmnet_ll_ep = + ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_PROD); + if (rmnet_ll_ep == IPA_EP_NOT_ALLOCATED) { + IPAWANERR_RL("Embedded datapath not supported\n"); + rc = -EFAULT; + break; + } + ext_ioctl_data.u.ipa_ep_pair.consumer_pipe_num = + rmnet_ll_ep; + if (copy_to_user((u8 *)ifr->ifr_ifru.ifru_data, + &ext_ioctl_data, + sizeof(struct rmnet_ioctl_extended_s))) + rc = -EFAULT; + IPAWANDBG("RMNET_IOCTL_GET_EP_PAIR_LL c: %d p: %d\n", + ext_ioctl_data.u.ipa_ep_pair.consumer_pipe_num, + ext_ioctl_data.u.ipa_ep_pair.producer_pipe_num); + break; + /* Get driver name */ + case RMNET_IOCTL_GET_DRIVER_NAME: + if (IPA_NETDEV() != NULL) { + memcpy(&ext_ioctl_data.u.if_name, + IPA_NETDEV()->name, IFNAMSIZ); + ext_ioctl_data.u.if_name[IFNAMSIZ - 1] = '\0'; + if (copy_to_user(ifr->ifr_ifru.ifru_data, + &ext_ioctl_data, + sizeof(struct rmnet_ioctl_extended_s))) + rc = -EFAULT; + } else { + IPAWANDBG("IPA_NETDEV is NULL\n"); + rc = -EFAULT; + } + break; + /* Add MUX ID */ + case RMNET_IOCTL_ADD_MUX_CHANNEL: + mux_id = ext_ioctl_data.u.rmnet_mux_val.mux_id; + mux_index = ipa3_find_mux_channel_index( + ext_ioctl_data.u.rmnet_mux_val.mux_id); + if (mux_index < MAX_NUM_OF_MUX_CHANNEL) { + IPAWANDBG("already setup mux(%d)\n", mux_id); + return rc; + } + mutex_lock(&rmnet_ipa3_ctx->add_mux_channel_lock); + if (rmnet_ipa3_ctx->rmnet_index + >= MAX_NUM_OF_MUX_CHANNEL) { + IPAWANERR_RL("Exceed mux_channel limit(%d)\n", + rmnet_ipa3_ctx->rmnet_index); + mutex_unlock( + &rmnet_ipa3_ctx->add_mux_channel_lock); + return -EFAULT; + } + ext_ioctl_data.u.rmnet_mux_val.vchannel_name + [IFNAMSIZ-1] = '\0'; + IPAWANDBG("ADD_MUX_CHANNEL(%d, name: %s)\n", + ext_ioctl_data.u.rmnet_mux_val.mux_id, + ext_ioctl_data.u.rmnet_mux_val.vchannel_name); + /* cache the mux name and id */ + mux_channel = rmnet_ipa3_ctx->mux_channel; + rmnet_index = rmnet_ipa3_ctx->rmnet_index; + + mux_channel[rmnet_index].mux_id = + ext_ioctl_data.u.rmnet_mux_val.mux_id; + memcpy(mux_channel[rmnet_index].vchannel_name, + ext_ioctl_data.u.rmnet_mux_val.vchannel_name, + sizeof(mux_channel[rmnet_index] + .vchannel_name)); + mux_channel[rmnet_index].vchannel_name[ + IFNAMSIZ - 1] = '\0'; + + IPAWANDBG("cashe device[%s:%d] in IPA_wan[%d]\n", + mux_channel[rmnet_index].vchannel_name, + mux_channel[rmnet_index].mux_id, + rmnet_index); + /* check if UL filter rules coming*/ + v_name = + ext_ioctl_data.u.rmnet_mux_val.vchannel_name; + if (rmnet_ipa3_ctx->num_q6_rules != 0 || + (rmnet_ipa3_ctx->ipa_config_is_apq)) { + mux_mutex_ptr = + &rmnet_ipa3_ctx->add_mux_channel_lock; + IPAWANERR_RL("dev(%s) register to IPA\n", + v_name); + rc = ipa3_wwan_register_to_ipa( + rmnet_ipa3_ctx->rmnet_index); + if (rc < 0) { + IPAWANERR_RL("device %s reg IPA failed\n", + v_name); + mutex_unlock(mux_mutex_ptr); + return -ENODEV; + } + mux_channel[rmnet_index].mux_channel_set = + true; + mux_channel[rmnet_index].ul_flt_reg = + true; + } else { + IPAWANDBG("dev(%s) haven't registered to IPA\n", + v_name); + mux_channel[rmnet_index].mux_channel_set = + true; + mux_channel[rmnet_index].ul_flt_reg = + false; + } + rmnet_ipa3_ctx->rmnet_index++; + mutex_unlock(&rmnet_ipa3_ctx->add_mux_channel_lock); + break; + case RMNET_IOCTL_SET_EGRESS_DATA_FORMAT: + rc = handle3_egress_format(dev, &ext_ioctl_data); + break; + case RMNET_IOCTL_SET_INGRESS_DATA_FORMAT:/* Set IDF */ + rc = handle3_ingress_format(dev, &ext_ioctl_data); + break; + case RMNET_IOCTL_SET_XLAT_DEV_INFO: + wan_msg = kzalloc(sizeof(struct ipa_wan_msg), + GFP_KERNEL); + if (!wan_msg) + return -ENOMEM; + ext_ioctl_data.u.if_name[IFNAMSIZ-1] = '\0'; + len = sizeof(wan_msg->upstream_ifname) > + sizeof(ext_ioctl_data.u.if_name) ? + sizeof(ext_ioctl_data.u.if_name) : + sizeof(wan_msg->upstream_ifname); + strlcpy(wan_msg->upstream_ifname, + ext_ioctl_data.u.if_name, len); + wan_msg->upstream_ifname[len-1] = '\0'; + memset(&msg_meta, 0, sizeof(struct ipa_msg_meta)); + msg_meta.msg_type = WAN_XLAT_CONNECT; + msg_meta.msg_len = sizeof(struct ipa_wan_msg); + rc = ipa_send_msg(&msg_meta, wan_msg, + ipa3_wwan_msg_free_cb); + if (rc) { + IPAWANERR_RL("Failed to send XLAT_CONNECT msg\n"); + kfree(wan_msg); + } + break; + /* Get agg count */ + case RMNET_IOCTL_GET_AGGREGATION_COUNT: + break; + /* Set agg count */ + case RMNET_IOCTL_SET_AGGREGATION_COUNT: + break; + /* Get agg size */ + case RMNET_IOCTL_GET_AGGREGATION_SIZE: + break; + /* Set agg size */ + case RMNET_IOCTL_SET_AGGREGATION_SIZE: + break; + /* Do flow control */ + case RMNET_IOCTL_FLOW_CONTROL: + break; + /* For legacy use */ + case RMNET_IOCTL_GET_DFLT_CONTROL_CHANNEL: + break; + /* Get HW/SW map */ + case RMNET_IOCTL_GET_HWSW_MAP: + break; + /* Set RX Headroom */ + case RMNET_IOCTL_SET_RX_HEADROOM: + break; + /* Set RSC/RSB */ + case RMNET_IOCTL_SET_OFFLOAD: + if (ext_ioctl_data.u.offload_params.flags + & RMNET_IOCTL_COALESCING_FORMAT_TCP) + tcp_en = true; + if (ext_ioctl_data.u.offload_params.flags + & RMNET_IOCTL_COALESCING_FORMAT_UDP) + udp_en = true; + rc = rmnet_ipa_send_coalesce_notification( + ext_ioctl_data.u.offload_params.mux_id, + tcp_en || udp_en, tcp_en, udp_en); + break; + /* vote ipa clock on/off */ + case RMNET_IOCTL_SET_SLEEP_STATE: + mutex_lock(&rmnet_ipa3_ctx->clock_vote.mutex); + if (ext_ioctl_data.u.data) { + /* Request to enable LPM */ + IPAWANDBG("ioctl: unvote IPA clock\n"); + if (rmnet_ipa3_ctx->clock_vote.cnt) { + rmnet_ipa3_ctx->clock_vote.cnt--; + IPA_ACTIVE_CLIENTS_DEC_SPECIAL("NETMGR"); + } + } else { + /* Request to disable LPM */ + IPAWANDBG("ioctl: vote IPA clock\n"); + if ((rmnet_ipa3_ctx->clock_vote.cnt + 1) + <= IPA_APP_VOTE_MAX) { + IPA_ACTIVE_CLIENTS_INC_SPECIAL("NETMGR"); + rmnet_ipa3_ctx->clock_vote.cnt++; + } + } + mutex_unlock(&rmnet_ipa3_ctx->clock_vote.mutex); + break; + /* Get MTU */ + case RMNET_IOCTL_GET_MTU: + mux_channel = rmnet_ipa3_ctx->mux_channel; + ext_ioctl_data.u.mtu_params.if_name + [IFNAMSIZ-1] = '\0'; + rmnet_index = + find_vchannel_name_index(ext_ioctl_data.u.mtu_params.if_name); + + if (rmnet_index == MAX_NUM_OF_MUX_CHANNEL) { + IPAWANERR_RL("%s is an invalid iface name\n", + ext_ioctl_data.u.mtu_params.if_name); + return -ENODEV; + } + + IPAWANDBG("getting v4 MTU = %d\n", mux_channel[rmnet_index].mtu_v4); + ext_ioctl_data.u.mtu_params.mtu_v4 = + mux_channel[rmnet_index].mtu_v4; + + IPAWANDBG("getting v6 MTU = %d\n", mux_channel[rmnet_index].mtu_v6); + ext_ioctl_data.u.mtu_params.mtu_v6 = + mux_channel[rmnet_index].mtu_v6; + break; + /* Set MTU */ + case RMNET_IOCTL_SET_MTU: + mux_channel = rmnet_ipa3_ctx->mux_channel; + ext_ioctl_data.u.mtu_params.if_name + [IFNAMSIZ-1] = '\0'; + rmnet_index = + find_vchannel_name_index(ext_ioctl_data.u.mtu_params.if_name); + + if (rmnet_index == MAX_NUM_OF_MUX_CHANNEL) { + IPAWANERR_RL("%s is an invalid iface name\n", + ext_ioctl_data.u.mtu_params.if_name); + return -ENODEV; + } + + /* V4 case */ + if (ext_ioctl_data.u.mtu_params.mtu_v4 > 0) { + mux_channel[rmnet_index].mtu_v4 = + ext_ioctl_data.u.mtu_params.mtu_v4; + mtu_v4_set = true; + IPAWANDBG("Set v4 MTU = %d\n", mux_channel[rmnet_index].mtu_v4); + iptype = IPA_IP_v4; + } + /* V6 case */ + if (ext_ioctl_data.u.mtu_params.mtu_v6 > 0) { + mux_channel[rmnet_index].mtu_v6 = + ext_ioctl_data.u.mtu_params.mtu_v6; + mtu_v6_set = true; + IPAWANDBG("Set v6 MTU = %d\n", mux_channel[rmnet_index].mtu_v6); + iptype = IPA_IP_v6; + } + + if (mtu_v4_set && mtu_v6_set) + iptype = IPA_IP_MAX; + + if (mtu_v4_set || mtu_v6_set) + rc = rmnet_ipa_send_set_mtu_notification( + ext_ioctl_data.u.mtu_params.if_name, + mux_channel[rmnet_index].mtu_v4, + mux_channel[rmnet_index].mtu_v6, + iptype); + + break; + default: + IPAWANERR_RL("[%s] unsupported extended cmd[%d]", + dev->name, + ext_ioctl_data.extended_ioctl); + rc = -EINVAL; + } + break; + case RMNET_IOCTL_EXTENDED_V2: + IPAWANDBG("RMNET_IOCTL_EXTENDED_V2 received\n"); + if (copy_from_user(&ext_ioctl_v2_data, + (u8 *)ifr->ifr_ifru.ifru_data, + sizeof(struct rmnet_ioctl_extended_s_v2))) { + IPAWANERR_RL("failed to copy extended ioctl data\n"); + rc = -EFAULT; + break; + } + switch (ext_ioctl_v2_data.extended_v2_ioctl_type) { + case RMNET_IOCTL_SET_EGRESS_DATA_FORMAT_V2: + if (ext_ioctl_v2_data.ioctl_data_size != + sizeof(struct egress_format_v2)) { + IPAWANERR_RL("Egress ioctl v2 format size mismatch\n"); + rc = -EFAULT; + break; + } + rc = handle3_egress_format_v2(dev, + ext_ioctl_v2_data.ioctl_ptr); + break; + case RMNET_IOCTL_SET_INGRESS_DATA_FORMAT_V2: + if (ext_ioctl_v2_data.ioctl_data_size != + sizeof(struct ingress_format_v2)) { + IPAWANERR_RL("ingress ioctl v2 format size mismatch\n"); + rc = -EFAULT; + break; + } + rc = handle3_ingress_format_v2(dev, + ext_ioctl_v2_data.ioctl_ptr); + break; + default: + IPAWANERR_RL("%d is Unsupported extended ioctl v2\n", + ext_ioctl_v2_data.extended_v2_ioctl_type); + rc = -EINVAL; + break; + } + break; + default: + IPAWANERR_RL("[%s] unsupported cmd[%d]", + dev->name, cmd); + rc = -EINVAL; + } + return rc; +} + +static const struct net_device_ops ipa3_wwan_ops_ip = { + .ndo_open = ipa3_wwan_open, + .ndo_stop = ipa3_wwan_stop, + .ndo_start_xmit = ipa3_wwan_xmit, + .ndo_tx_timeout = ipa3_wwan_tx_timeout, +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(5, 14, 14)) + .ndo_do_ioctl = ipa3_wwan_ioctl, +#else + .ndo_siocdevprivate = ipa3_wwan_ioctl, +#endif + .ndo_change_mtu = ipa3_wwan_change_mtu, + .ndo_set_mac_address = 0, + .ndo_validate_addr = 0, +}; + +/** + * wwan_setup() - Setups the wwan network driver. + * + * @dev: network device + * + * Return codes: + * None + */ + +static void ipa3_wwan_setup(struct net_device *dev) +{ + dev->netdev_ops = &ipa3_wwan_ops_ip; + ether_setup(dev); + /* set this after calling ether_setup */ + dev->header_ops = 0; /* No header */ + dev->type = ARPHRD_RAWIP; + dev->hard_header_len = 0; + dev->mtu = WWAN_DATA_LEN; + dev->addr_len = 0; + dev->flags &= ~(IFF_BROADCAST | IFF_MULTICAST); + dev->needed_headroom = HEADROOM_FOR_QMAP; + dev->needed_tailroom = TAILROOM; + dev->watchdog_timeo = msecs_to_jiffies(10000); +} + +/** + * rmnet_ipa_send_coalesce_notification + * (uint8_t qmap_id, bool enable, bool tcp, bool udp) + * send RSC notification + * + * This function sends the rsc enable/disable notification + * fot tcp, udp to user-space module + */ +static int rmnet_ipa_send_coalesce_notification(uint8_t qmap_id, + bool enable, + bool tcp, + bool udp) +{ + struct ipa_msg_meta msg_meta; + struct ipa_coalesce_info *coalesce_info; + int rc; + + memset(&msg_meta, 0, sizeof(struct ipa_msg_meta)); + coalesce_info = kzalloc(sizeof(*coalesce_info), GFP_KERNEL); + if (!coalesce_info) + return -ENOMEM; + + coalesce_info->qmap_id = qmap_id; + coalesce_info->tcp_enable = tcp; + coalesce_info->udp_enable = udp; + msg_meta.msg_len = sizeof(struct ipa_coalesce_info); + if (enable) + msg_meta.msg_type = IPA_COALESCE_ENABLE; + else + msg_meta.msg_type = IPA_COALESCE_DISABLE; + rc = ipa_send_msg(&msg_meta, coalesce_info, ipa3_wwan_msg_free_cb); + if (rc) { + IPAWANERR_RL("ipa_send_msg failed: %d\n", rc); + return -EFAULT; + } + IPAWANDBG("qmap-id(%d),enable(%d),tcp(%d),udp(%d)\n", + qmap_id, enable, tcp, udp); + return 0; +} + +static int rmnet_ipa_send_set_mtu_notification(char *if_name, + uint16_t mtu_v4, uint16_t mtu_v6, enum ipa_ip_type ip) +{ + struct ipa_msg_meta msg_meta; + struct ipa_mtu_info *mtu_info; + int rc; + + memset(&msg_meta, 0, sizeof(struct ipa_msg_meta)); + mtu_info = kzalloc(sizeof(*mtu_info), GFP_KERNEL); + if (!mtu_info) + return -ENOMEM; + + strlcpy(mtu_info->if_name, if_name, IPA_RESOURCE_NAME_MAX); + mtu_info->mtu_v4 = mtu_v4; + mtu_info->mtu_v6 = mtu_v6; + mtu_info->ip_type = ip; + msg_meta.msg_type = IPA_SET_MTU; + msg_meta.msg_len = sizeof(struct ipa_mtu_info); + + rc = ipa_send_msg(&msg_meta, mtu_info, ipa3_wwan_msg_free_cb); + if (rc) { + IPAWANERR("ipa_send_msg failed: %d\n", rc); + return -EFAULT; + } + IPAWANDBG( + "sent new mtu_v4(%d)/mtu_v6(%d) with iptype(%d) for iface(%s) to IPACM", + mtu_v4, mtu_v6, ip, if_name); + + return 0; +} + +int ipa3_wwan_set_modem_state(struct wan_ioctl_notify_wan_state *state) +{ + int ret = 0; + char alert_msg[IPA_UPSTREAM_ALERT_MAX_SIZE]; + char wan_iface[IPA_UPSTREAM_ALERT_MAX_SIZE]; + char wan_state[IPA_UPSTREAM_ALERT_MAX_SIZE]; + char *envp[IPA_UEVENT_NUM_EVNP] = { + alert_msg, wan_iface, wan_state, NULL}; + int res; + + if (!state) + return -EINVAL; + + if (state->up) + ret = ipa_pm_activate_sync(rmnet_ipa3_ctx->q6_teth_pm_hdl); + else + ret = ipa_pm_deactivate_sync(rmnet_ipa3_ctx->q6_teth_pm_hdl); + + /* Send upstream state uevent if RSC/RSB is enabled. */ + if (IPA_NETDEV() && (IPA_NETDEV()->features & NETIF_F_GRO_HW)) { + res = snprintf(alert_msg, IPA_UPSTREAM_ALERT_MAX_SIZE, + "ALERT_NAME=%s", "upstreamEvent"); + + if ((res >= IPA_UPSTREAM_ALERT_MAX_SIZE) || (res < 0)) { + IPAWANERR("alert message invalid (%d)", res); + } else { + state->upstreamIface[IFNAMSIZ - 1] = '\0'; + res = snprintf(wan_iface, + IPA_UPSTREAM_ALERT_MAX_SIZE, + "UPSTREAM=%s", state->upstreamIface); + if ((res >= IPA_UPSTREAM_ALERT_MAX_SIZE) || + (res < 0)) { + IPAWANERR("Iface name invalid (%d)", res); + } else { + res = snprintf(wan_state, + IPA_UPSTREAM_ALERT_MAX_SIZE, + "STATE=%s", + (state->up ? "UP" : "DOWN")); + if ((res >= IPA_UPSTREAM_ALERT_MAX_SIZE) || + (res < 0)) { + IPAWANERR("Iface state invalid (%d)", + res); + } else { + IPAWANERR("nlmsg: <%s> <%s> <%s>\n", + alert_msg, wan_iface, wan_state); + if (IPA_NETDEV()) + kobject_uevent_env( + &(IPA_NETDEV()->dev.kobj), + KOBJ_CHANGE, envp); + } + } + } + } + + return ret; +} + +/** + * ipa3_q6_register_pm - Register modem clients for PM + * + * This function will register 2 client with IPA PM to represent modem + * in clock scaling calculation: + * - "EMB MODEM" - this client will be activated with embedded traffic + - "TETH MODEM" - this client we be activated by IPACM on offload to + modem. +*/ +static int ipa3_q6_register_pm(void) +{ + int result; + struct ipa_pm_register_params pm_reg; + + memset(&pm_reg, 0, sizeof(pm_reg)); + pm_reg.name = "EMB MODEM"; + pm_reg.group = IPA_PM_GROUP_MODEM; + pm_reg.skip_clk_vote = true; + result = ipa_pm_register(&pm_reg, &rmnet_ipa3_ctx->q6_pm_hdl); + if (result) { + IPAERR("failed to create IPA PM client %d\n", result); + return result; + } + + pm_reg.name = "TETH MODEM"; + pm_reg.group = IPA_PM_GROUP_MODEM; + pm_reg.skip_clk_vote = true; + result = ipa_pm_register(&pm_reg, &rmnet_ipa3_ctx->q6_teth_pm_hdl); + if (result) { + IPAERR("failed to create IPA PM client %d\n", result); + return result; + } + + return 0; +} + +static void ipa3_q6_deregister_pm(void) +{ + ipa_pm_deactivate_sync(rmnet_ipa3_ctx->q6_pm_hdl); + ipa_pm_deregister(rmnet_ipa3_ctx->q6_pm_hdl); +} + +int ipa3_wwan_set_modem_perf_profile(int throughput) +{ + int ret; + + IPAWANDBG("throughput: %d\n", throughput); + /* for TETH MODEM on softap/rndis */ + ret = ipa_pm_set_throughput(rmnet_ipa3_ctx->q6_teth_pm_hdl, + throughput); + + return ret; +} + +static void ipa3_wake_tx_queue(struct work_struct *work) +{ + if (IPA_NETDEV()) { + __netif_tx_lock_bh(netdev_get_tx_queue(IPA_NETDEV(), 0)); + IPAWANDBG("Waking up the workqueue.\n"); + netif_wake_queue(IPA_NETDEV()); + __netif_tx_unlock_bh(netdev_get_tx_queue(IPA_NETDEV(), 0)); + } +} + +/** + * ipa3_pm_resource_granted() - Called upon + * IPA_PM_RESOURCE_GRANTED event. Wakes up the tx workqueue. + * + * @work: work object supplied ny workqueue + * + * Return codes: + * None + */ +static void ipa3_pm_resource_granted(void *dev) +{ + IPAWANDBG_LOW("Resource Granted - starting queue\n"); + schedule_work(&ipa3_tx_wakequeue_work); +} + +/* IPA_PM related functions end*/ + +static int ipa3_lcl_mdm_ssr_notifier_cb(struct notifier_block *this, + unsigned long code, + void *data); + +static int ipa3_rmt_mdm_ssr_notifier_cb(struct notifier_block *this, + unsigned long code, + void *data); + +static struct notifier_block ipa3_lcl_mdm_ssr_notifier = { + .notifier_call = ipa3_lcl_mdm_ssr_notifier_cb, +}; + +static struct notifier_block ipa3_rmt_mdm_ssr_notifier = { + .notifier_call = ipa3_rmt_mdm_ssr_notifier_cb, +}; + +static int get_ipa_rmnet_dts_configuration(struct platform_device *pdev, + struct ipa3_rmnet_plat_drv_res *ipa_rmnet_drv_res) +{ + int result; + + ipa_rmnet_drv_res->wan_rx_desc_size = IPA_WWAN_CONS_DESC_FIFO_SZ; + ipa_rmnet_drv_res->ipa_rmnet_ssr = + of_property_read_bool(pdev->dev.of_node, + "qcom,rmnet-ipa-ssr"); + pr_info("IPA SSR support = %s\n", + ipa_rmnet_drv_res->ipa_rmnet_ssr ? "True" : "False"); + + ipa_rmnet_drv_res->ipa_advertise_sg_support = + of_property_read_bool(pdev->dev.of_node, + "qcom,ipa-advertise-sg-support"); + pr_info("IPA SG support = %s\n", + ipa_rmnet_drv_res->ipa_advertise_sg_support ? "True" : "False"); + + ipa_rmnet_drv_res->ipa_napi_enable = + of_property_read_bool(pdev->dev.of_node, + "qcom,ipa-napi-enable"); + pr_info("IPA Napi Enable = %s\n", + ipa_rmnet_drv_res->ipa_napi_enable ? "True" : "False"); + + /* Get IPA WAN RX desc fifo size */ + result = of_property_read_u32(pdev->dev.of_node, + "qcom,wan-rx-desc-size", + &ipa_rmnet_drv_res->wan_rx_desc_size); + if (result) + pr_info("using default for wan-rx-desc-size = %u\n", + ipa_rmnet_drv_res->wan_rx_desc_size); + else + IPAWANDBG(": found ipa_drv_res->wan-rx-desc-size = %u\n", + ipa_rmnet_drv_res->wan_rx_desc_size); + + return 0; +} + +struct ipa3_rmnet_context ipa3_rmnet_ctx; +static int ipa3_wwan_probe(struct platform_device *pdev); +static struct platform_device *m_pdev; + +static void ipa3_delayed_probe(struct work_struct *work) +{ + (void)ipa3_wwan_probe(m_pdev); +} + +static DECLARE_WORK(ipa3_scheduled_probe, ipa3_delayed_probe); + +static void ipa3_ready_cb(void *user_data) +{ + struct platform_device *pdev = (struct platform_device *)(user_data); + + m_pdev = pdev; + + IPAWANDBG("IPA ready callback has been triggered\n"); + + schedule_work(&ipa3_scheduled_probe); +} + +static void ipa_pm_wwan_pm_cb(void *p, enum ipa_pm_cb_event event) +{ + struct net_device *dev = (struct net_device *)p; + struct ipa3_wwan_private *wwan_ptr = netdev_priv(dev); + + IPAWANDBG_LOW("event %d\n", event); + switch (event) { + case IPA_PM_CLIENT_ACTIVATED: + if (wwan_ptr->device_status == WWAN_DEVICE_INACTIVE) { + complete_all(&wwan_ptr->resource_granted_completion); + break; + } + ipa3_pm_resource_granted(dev); + break; + default: + pr_err("%s: unknown event %d\n", __func__, event); + break; + } +} + +static int ipa3_wwan_register_netdev_pm_client(struct net_device *dev) +{ + int result; + struct ipa_pm_register_params pm_reg; + + memset(&pm_reg, 0, sizeof(pm_reg)); + pm_reg.name = IPA_NETDEV()->name; + pm_reg.user_data = dev; + pm_reg.callback = ipa_pm_wwan_pm_cb; + pm_reg.group = IPA_PM_GROUP_APPS; + result = ipa_pm_register(&pm_reg, &rmnet_ipa3_ctx->pm_hdl); + if (result) { + IPAWANERR("failed to create IPA PM client %d\n", result); + return result; + } + + IPAWANERR("%s register done\n", pm_reg.name); + + return 0; +} + +static void ipa3_wwan_deregister_netdev_pm_client(void) +{ + ipa_pm_deactivate_sync(rmnet_ipa3_ctx->pm_hdl); + ipa_pm_deregister(rmnet_ipa3_ctx->pm_hdl); +} + +/** + * ipa3_wwan_probe() - Initialized the module and registers as a + * network interface to the network stack + * + * Note: In case IPA driver hasn't initialized already, the probe function + * will return immediately after registering a callback to be invoked when + * IPA driver initialization is complete. + * + * Return codes: + * 0: success + * -ENOMEM: No memory available + * -EFAULT: Internal error + */ +static int ipa3_wwan_probe(struct platform_device *pdev) +{ + int ret, i, j; + struct net_device *dev; + int wan_cons_ep; + + pr_info("rmnet_ipa3 started initialization\n"); + + if (!ipa_is_ready()) { + IPAWANDBG("IPA driver not ready, registering callback\n"); + ret = ipa_register_ipa_ready_cb(ipa3_ready_cb, (void *)pdev); + + /* + * If we received -EEXIST, IPA has initialized. So we need + * to continue the probing process. + */ + if (ret != -EEXIST) { + if (ret) + IPAWANERR("IPA CB reg failed - %d\n", ret); + return ret; + } + } + + wan_cons_ep = ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_CONS); + ret = get_ipa_rmnet_dts_configuration(pdev, &ipa3_rmnet_res); + ipa3_rmnet_ctx.ipa_rmnet_ssr = ipa3_rmnet_res.ipa_rmnet_ssr; + + /* check if booting as mhi-prime */ + rmnet_ipa3_ctx->ipa_config_is_apq + = ipa3_is_apq(); + + ret = ipa3_init_q6_smem(); + if (ret) { + IPAWANERR("ipa3_init_q6_smem failed\n"); + return ret; + } + + /* initialize tx/rx endpoint setup */ + memset(&rmnet_ipa3_ctx->apps_to_ipa_ep_cfg, 0, + sizeof(struct ipa_sys_connect_params)); + memset(&rmnet_ipa3_ctx->ipa_to_apps_ep_cfg, 0, + sizeof(struct ipa_sys_connect_params)); + + /* initialize ex property setup */ + rmnet_ipa3_ctx->num_q6_rules = 0; + rmnet_ipa3_ctx->old_num_q6_rules = 0; + rmnet_ipa3_ctx->rmnet_index = 0; + rmnet_ipa3_ctx->egress_set = false; + rmnet_ipa3_ctx->a7_ul_flt_set = false; + rmnet_ipa3_ctx->ipa_mhi_aggr_formet_set = false; + rmnet_ipa3_ctx->ingress_eps_mask = IPA_AP_INGRESS_NONE; + rmnet_ipa3_ctx->wan_rt_table_setup = false; + for (i = 0; i < MAX_NUM_OF_MUX_CHANNEL; i++) + memset(&rmnet_ipa3_ctx->mux_channel[i], 0, + sizeof(struct ipa3_rmnet_mux_val)); + + /* start A7 QMI service/client */ + if (ipa3_ctx_get_type(PLATFORM_TYPE) == IPA_PLAT_TYPE_MSM || + ipa3_ctx_get_type(PLATFORM_TYPE) == IPA_PLAT_TYPE_APQ) + /* Android platform loads uC */ + ipa3_qmi_service_init(QMI_IPA_PLATFORM_TYPE_MSM_ANDROID_V01); + else if (ipa3_ctx_get_flag(IPA_MHI_EN)) + /* LE MHI platform */ + ipa3_qmi_service_init(QMI_IPA_PLATFORM_TYPE_LE_MHI_V01); + else + /* LE platform not loads uC */ + ipa3_qmi_service_init(QMI_IPA_PLATFORM_TYPE_LE_V01); + + if (!atomic_read(&rmnet_ipa3_ctx->is_ssr)) { + /* Start transport-driver fd ioctl for ipacm for first init */ + ret = ipa3_wan_ioctl_init(); + if (ret) + goto wan_ioctl_init_err; + } else { + /* Enable sending QMI messages after SSR */ + ipa3_wan_ioctl_enable_qmi_messages(); + } + + /* initialize wan-driver netdev */ + dev = alloc_netdev_mqs(sizeof(struct ipa3_wwan_private), + IPA_WWAN_DEV_NAME, + NET_NAME_UNKNOWN, + ipa3_wwan_setup, 1, 2); + if (!dev) { + IPAWANERR("no memory for netdev\n"); + ret = -ENOMEM; + goto alloc_netdev_err; + } + rmnet_ipa3_ctx->wwan_priv = netdev_priv(dev); + memset(rmnet_ipa3_ctx->wwan_priv, 0, + sizeof(*(rmnet_ipa3_ctx->wwan_priv))); + IPAWANDBG("wwan_ptr (private) = %pK", rmnet_ipa3_ctx->wwan_priv); + rmnet_ipa3_ctx->wwan_priv->net = dev; + atomic_set(&rmnet_ipa3_ctx->wwan_priv->outstanding_pkts, 0); + spin_lock_init(&rmnet_ipa3_ctx->wwan_priv->lock); + init_completion( + &rmnet_ipa3_ctx->wwan_priv->resource_granted_completion); + + if (!atomic_read(&rmnet_ipa3_ctx->is_ssr)) { + /* IPA_PM configuration starts */ + ret = ipa3_q6_register_pm(); + if (ret) { + IPAWANERR("ipa3_q6_register_pm failed, ret: %d\n", + ret); + goto q6_init_err; + } + } + + ret = ipa3_wwan_register_netdev_pm_client(dev); + if (ret) { + IPAWANERR("fail to create/register pm resources\n"); + goto fail_pm; + } + + /* Enable SG support in netdevice. */ + if (ipa3_rmnet_res.ipa_advertise_sg_support) + dev->hw_features |= NETIF_F_SG; + + if (ipa3_is_ulso_supported()) { + dev->hw_features |= NETIF_F_GSO_UDP_L4; + dev->hw_features |= NETIF_F_ALL_TSO; + dev->gso_max_size = RMNET_IPA_ULSO_SIZE_LIMIT; + } + + if (ipa3_rmnet_res.ipa_napi_enable) +#if (LINUX_VERSION_CODE > KERNEL_VERSION(6, 0, 14)) + netif_napi_add(dev, &(rmnet_ipa3_ctx->wwan_priv->napi), + ipa3_rmnet_poll); +#else + netif_napi_add(dev, &(rmnet_ipa3_ctx->wwan_priv->napi), + ipa3_rmnet_poll, NAPI_WEIGHT); +#endif + ret = register_netdev(dev); + if (ret) { + IPAWANERR("unable to register ipa_netdev %d rc=%d\n", + 0, ret); + goto set_perf_err; + } + + IPAWANDBG("IPA-WWAN devices (%s) initialization ok :>>>>\n", dev->name); + if (ret) { + IPAWANERR("default configuration failed rc=%d\n", + ret); + goto config_err; + } + + /* for > IPA 4.5, we set the colaescing/cs offload feature flag on */ + if (ipa3_ctx_get_type(IPA_HW_TYPE) >= IPA_HW_v4_5) { + dev->hw_features |= NETIF_F_GRO_HW | NETIF_F_RXCSUM; + dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; + } + + /* + * for IPA 4.0 offline charge is not needed and we need to prevent + * power collapse until IPA uC is loaded. + */ + atomic_set(&rmnet_ipa3_ctx->is_initialized, 1); + if (!atomic_read(&rmnet_ipa3_ctx->is_ssr) && + ipa3_ctx_get_type(IPA_HW_TYPE) != + IPA_HW_v4_0) { + /* offline charging mode */ + ipa3_proxy_clk_unvote(); + } + atomic_set(&rmnet_ipa3_ctx->is_ssr, 0); + atomic_set(&rmnet_ipa3_ctx->ap_suspend, 0); + ipa3_update_ssr_state(false); + + for (j = 0; j < RMNET_INGRESS_MAX; j++) { + ingress_pipe_status[j].ep_type = 0; + ingress_pipe_status[j].status = 0; + } + for (j = 0; j < RMNET_EGRESS_MAX; j++) { + egress_pipe_status[j].ep_type = 0; + egress_pipe_status[j].status = 0; + } + + IPAWANERR("rmnet_ipa completed initialization\n"); + return 0; +config_err: + if (ipa3_rmnet_res.ipa_napi_enable) + netif_napi_del(&(rmnet_ipa3_ctx->wwan_priv->napi)); + unregister_netdev(dev); +set_perf_err: + + ipa3_wwan_deregister_netdev_pm_client(); +fail_pm: + if (!atomic_read(&rmnet_ipa3_ctx->is_ssr)) + ipa3_q6_deregister_pm(); +q6_init_err: + free_netdev(dev); + rmnet_ipa3_ctx->wwan_priv = NULL; +alloc_netdev_err: + ipa3_wan_ioctl_deinit(); +wan_ioctl_init_err: + ipa3_qmi_service_exit(); + atomic_set(&rmnet_ipa3_ctx->is_ssr, 0); + return ret; +} + +static int ipa3_wwan_remove(struct platform_device *pdev) +{ + int ret, j; + + IPAWANINFO("rmnet_ipa started deinitialization\n"); + mutex_lock(&rmnet_ipa3_ctx->pipe_handle_guard); + if (ipa3_ctx->rmnet_ctl_enable) { + ret = ipa3_teardown_apps_low_lat_pipes(); + if (ret < 0) + IPAWANERR("Failed to teardown IPA->APPS qmap pipe\n"); + } + if (ipa3_ctx->rmnet_ll_enable) { + ret = ipa3_teardown_apps_low_lat_data_pipes(); + if (ret < 0) + IPAWANERR("Failed to teardown IPA->APPS LL pipe\n"); + } + ret = ipa_teardown_sys_pipe(rmnet_ipa3_ctx->ipa3_to_apps_hdl); + if (ret < 0) + IPAWANERR("Failed to teardown IPA->APPS pipe\n"); + else + rmnet_ipa3_ctx->ipa3_to_apps_hdl = -1; + ret = ipa_teardown_sys_pipe(rmnet_ipa3_ctx->apps_to_ipa3_hdl); + if (ret < 0) + IPAWANERR("Failed to teardown APPS->IPA pipe\n"); + else + rmnet_ipa3_ctx->apps_to_ipa3_hdl = -1; + /* Clear pipe setup info */ + for (j = 0; j < RMNET_INGRESS_MAX; j++) { + ingress_pipe_status[j].ep_type = 0; + ingress_pipe_status[j].status = 0; + } + for (j = 0; j < RMNET_EGRESS_MAX; j++) { + egress_pipe_status[j].ep_type = 0; + egress_pipe_status[j].status = 0; + } + rmnet_ipa3_ctx->ingress_eps_mask = IPA_AP_INGRESS_NONE; + rmnet_ipa3_ctx->wan_rt_table_setup = false; + mutex_unlock(&rmnet_ipa3_ctx->pipe_handle_guard); + /* Clean up netdev resources in BEFORE_SHUTDOWN for non remoteproc + * targets. */ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 14, 0)) + IPAWANINFO("rmnet_ipa unregister_netdev\n"); + if (IPA_NETDEV()) + unregister_netdev(IPA_NETDEV()); + ipa3_wwan_deregister_netdev_pm_client(); +#endif + cancel_work_sync(&ipa3_tx_wakequeue_work); + cancel_delayed_work(&ipa_tether_stats_poll_wakequeue_work); +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 14, 0)) + if (IPA_NETDEV()) + free_netdev(IPA_NETDEV()); + rmnet_ipa3_ctx->wwan_priv = NULL; +#endif + /* No need to remove wwan_ioctl during SSR */ + if (!atomic_read(&rmnet_ipa3_ctx->is_ssr)) + ipa3_wan_ioctl_deinit(); + if (ipa3_ctx->rmnet_ll_enable && + (ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_CONS) != + IPA_EP_NOT_ALLOCATED)) + ipa3_del_low_lat_rt_rule(); + if (ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_CONS) != + IPA_EP_NOT_ALLOCATED) { + ipa3_del_dflt_wan_rt_tables(); + ipa3_del_a7_qmap_hdr(); + } + ipa3_del_mux_qmap_hdrs(); + if (ipa3_qmi_ctx && !ipa3_qmi_ctx->modem_cfg_emb_pipe_flt) + ipa3_wwan_del_ul_flt_rule_to_ipa(); + ipa3_cleanup_deregister_intf(); + /* reset dl_csum_offload_enabled */ + rmnet_ipa3_ctx->dl_csum_offload_enabled = false; + atomic_set(&rmnet_ipa3_ctx->is_initialized, 0); + IPAWANINFO("rmnet_ipa completed deinitialization\n"); + return 0; +} + +/** + * rmnet_ipa_ap_suspend() - suspend callback for runtime_pm + * @dev: pointer to device + * + * This callback will be invoked by the runtime_pm framework when an AP suspend + * operation is invoked, usually by pressing a suspend button. + * + * Returns -EAGAIN to runtime_pm framework in case there are pending packets + * in the Tx queue. This will postpone the suspend operation until all the + * pending packets will be transmitted. + * + * In case there are no packets to send, releases the WWAN0_PROD entity. + * As an outcome, the number of IPA active clients should be decremented + * until IPA clocks can be gated. + */ +static int rmnet_ipa_ap_suspend(struct device *dev) +{ + struct net_device *netdev = IPA_NETDEV(); + struct ipa3_wwan_private *wwan_ptr; + int ret; + unsigned long flags; + + IPAWANDBG("Enter...\n"); + + if (netdev == NULL) { + IPAWANERR("netdev is NULL.\n"); + ret = 0; + goto bail; + } + + wwan_ptr = netdev_priv(netdev); + if (wwan_ptr == NULL) { + IPAWANERR("wwan_ptr is NULL.\n"); + ret = 0; + goto bail; + } + + /* + * Rmnert supend and xmit are executing at the same time, In those + * scenarios observing the data was processed when IPA clock are off. + * Added changes to synchronize rmnet supend and xmit. + */ + atomic_set(&rmnet_ipa3_ctx->ap_suspend, 1); + spin_lock_irqsave(&wwan_ptr->lock, flags); + /* Do not allow A7 to suspend in case there are outstanding packets */ + if (atomic_read(&wwan_ptr->outstanding_pkts) != 0) { + IPAWANDBG("Outstanding packets, postponing AP suspend.\n"); + ret = -EAGAIN; + atomic_set(&rmnet_ipa3_ctx->ap_suspend, 0); + spin_unlock_irqrestore(&wwan_ptr->lock, flags); + goto bail; + } + + /* Make sure that there is no Tx operation ongoing */ + netif_device_detach(netdev); + spin_unlock_irqrestore(&wwan_ptr->lock, flags); + + IPAWANDBG("De-activating the PM resource.\n"); + ipa_pm_deactivate_sync(rmnet_ipa3_ctx->pm_hdl); + ret = 0; +bail: + IPAWANDBG("Exit with %d\n", ret); + return ret; +} + +/** + * rmnet_ipa_ap_resume() - resume callback for runtime_pm + * @dev: pointer to device + * + * This callback will be invoked by the runtime_pm framework when an AP resume + * operation is invoked. + * + * Enables the network interface queue and returns success to the + * runtime_pm framework. + */ +static int rmnet_ipa_ap_resume(struct device *dev) +{ + struct net_device *netdev = IPA_NETDEV(); + + IPAWANDBG("Enter...\n"); + /* Clear the suspend in progress flag. */ + if (rmnet_ipa3_ctx) + atomic_set(&rmnet_ipa3_ctx->ap_suspend, 0); + if (netdev) { + netif_device_attach(netdev); + netif_trans_update(netdev); + } + IPAWANDBG("Exit\n"); + + return 0; +} + +static void ipa_stop_polling_stats(void) +{ + cancel_delayed_work(&ipa_tether_stats_poll_wakequeue_work); + ipa3_rmnet_ctx.polling_interval = 0; +} + +static const struct of_device_id rmnet_ipa_dt_match[] = { + {.compatible = "qcom,rmnet-ipa3"}, + {}, +}; +MODULE_DEVICE_TABLE(of, rmnet_ipa_dt_match); + +static const struct dev_pm_ops rmnet_ipa_pm_ops = { + .suspend_late = rmnet_ipa_ap_suspend, + .resume_early = rmnet_ipa_ap_resume, +}; + +static struct platform_driver rmnet_ipa_driver = { + .driver = { + .name = "rmnet_ipa3", + .pm = &rmnet_ipa_pm_ops, + .of_match_table = rmnet_ipa_dt_match, + }, + .probe = ipa3_wwan_probe, + .remove = ipa3_wwan_remove, +}; + +/** + * rmnet_ipa_send_ssr_notification(bool ssr_done) - send SSR notification + * + * This function sends the SSR notification before modem shutdown and + * after_powerup from SSR framework, to user-space module + */ +static void rmnet_ipa_send_ssr_notification(bool ssr_done) +{ + struct ipa_msg_meta msg_meta; + int rc; + + memset(&msg_meta, 0, sizeof(struct ipa_msg_meta)); + if (ssr_done) + msg_meta.msg_type = IPA_SSR_AFTER_POWERUP; + else + msg_meta.msg_type = IPA_SSR_BEFORE_SHUTDOWN; + rc = ipa_send_msg(&msg_meta, NULL, NULL); + if (rc) { + IPAWANERR("ipa_send_msg failed: %d\n", rc); + return; + } +} + +static int ipa3_lcl_mdm_ssr_notifier_cb(struct notifier_block *this, + unsigned long code, + void *data) +{ + if (!ipa3_rmnet_ctx.ipa_rmnet_ssr) + return NOTIFY_DONE; + + if (!ipa3_ctx) { + IPAWANERR_RL("ipa3_ctx was not initialized\n"); + return NOTIFY_DONE; + } + + if (rmnet_ipa3_ctx->ipa_config_is_apq) { + IPAWANERR("Local modem SSR event=%lu on APQ platform\n", + code); + return NOTIFY_DONE; + } + + switch (code) { +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 14, 0)) + case QCOM_SSR_BEFORE_SHUTDOWN: +#else + case SUBSYS_BEFORE_SHUTDOWN: +#endif + IPAWANINFO("IPA received MPSS BEFORE_SHUTDOWN\n"); + /* hold a proxy vote for the modem. */ + ipa3_proxy_clk_vote(atomic_read(&rmnet_ipa3_ctx->is_ssr)); + /* send SSR before-shutdown notification to IPACM */ + ipa3_set_modem_up(false); + rmnet_ipa_send_ssr_notification(false); + atomic_set(&rmnet_ipa3_ctx->is_ssr, 1); + ipa3_q6_pre_shutdown_cleanup(); + if (IPA_NETDEV()) + netif_device_detach(IPA_NETDEV()); + ipa3_qmi_stop_workqueues(); + ipa3_wan_ioctl_stop_qmi_messages(); + ipa_stop_polling_stats(); + if (atomic_read(&rmnet_ipa3_ctx->is_initialized)) + platform_driver_unregister(&rmnet_ipa_driver); + if (ipa3_ctx->ipa_mhi_proxy) + imp_handle_modem_shutdown(); + if (atomic_read(&rmnet_ipa3_ctx->is_ssr) && + ipa3_ctx_get_type(IPA_HW_TYPE) >= IPA_HW_v4_0) + ipa3_q6_post_shutdown_cleanup(); + ipa3_odl_pipe_cleanup_from_ssr(); + IPAWANINFO("IPA BEFORE_SHUTDOWN handling is complete\n"); + break; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 14, 0)) + case QCOM_SSR_AFTER_SHUTDOWN: +#else + case SUBSYS_AFTER_SHUTDOWN: +#endif + IPAWANINFO("IPA Received MPSS AFTER_SHUTDOWN\n"); + ipa3_proxy_clk_unvote(); + /* Clean up netdev resources in AFTER_SHUTDOWN for remoteproc + * enabled targets. */ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 14, 0)) + IPAWANINFO("rmnet_ipa unregister_netdev\n"); + if (IPA_NETDEV()) + unregister_netdev(IPA_NETDEV()); + ipa3_wwan_deregister_netdev_pm_client(); + if (IPA_NETDEV()) + free_netdev(IPA_NETDEV()); + rmnet_ipa3_ctx->wwan_priv = NULL; +#endif + if (atomic_read(&rmnet_ipa3_ctx->is_ssr) && + ipa3_ctx_get_type(IPA_HW_TYPE) < IPA_HW_v4_0) + ipa3_q6_post_shutdown_cleanup(); + + if (ipa3_ctx_get_flag(IPA_ENDP_DELAY_WA_EN)) + ipa3_client_prod_post_shutdown_cleanup(); + IPAWANINFO("IPA AFTER_SHUTDOWN handling is complete\n"); + break; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 14, 0)) + case QCOM_SSR_BEFORE_POWERUP: +#else + case SUBSYS_BEFORE_POWERUP: +#endif + IPAWANINFO("IPA received MPSS BEFORE_POWERUP\n"); + if (atomic_read(&rmnet_ipa3_ctx->is_ssr)) { + /* clean up cached QMI msg/handlers */ + ipa3_qmi_service_exit(); + ipa3_q6_pre_powerup_cleanup(); + } + /* hold a proxy vote for the modem. */ + ipa3_proxy_clk_vote(atomic_read(&rmnet_ipa3_ctx->is_ssr)); + ipa3_reset_freeze_vote(); + IPAWANINFO("IPA BEFORE_POWERUP handling is complete\n"); + break; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 14, 0)) + case QCOM_SSR_AFTER_POWERUP: +#else + case SUBSYS_AFTER_POWERUP: +#endif + IPAWANINFO("IPA received MPSS AFTER_POWERUP\n"); + if (!atomic_read(&rmnet_ipa3_ctx->is_initialized) && + atomic_read(&rmnet_ipa3_ctx->is_ssr)) + platform_driver_register(&rmnet_ipa_driver); + ipa3_odl_pipe_open_from_ssr(); + IPAWANINFO("IPA AFTER_POWERUP handling is complete\n"); + break; + default: + IPAWANDBG("Unsupported subsys notification, IPA received: %lu", + code); + break; + } + + IPAWANDBG_LOW("Exit\n"); + return NOTIFY_DONE; +} + +static int ipa3_rmt_mdm_ssr_notifier_cb(struct notifier_block *this, + unsigned long code, + void *data) +{ + if (!ipa3_rmnet_ctx.ipa_rmnet_ssr) { + IPAWANERR("SSR event=%lu while not enabled\n", code); + return NOTIFY_DONE; + } + + if (!rmnet_ipa3_ctx->ipa_config_is_apq) { + IPAWANERR("Remote mdm SSR event=%lu on non-APQ platform=%d\n", + code, ipa3_ctx_get_type(PLATFORM_TYPE)); + return NOTIFY_DONE; + } + + switch (code) { +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 14, 0)) + case QCOM_SSR_BEFORE_SHUTDOWN: +#else + case SUBSYS_BEFORE_SHUTDOWN: +#endif + IPAWANINFO("IPA received RMT MPSS BEFORE_SHUTDOWN\n"); + break; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 14, 0)) + case QCOM_SSR_AFTER_SHUTDOWN: +#else + case SUBSYS_AFTER_SHUTDOWN: +#endif + IPAWANINFO("IPA Received RMT MPSS AFTER_SHUTDOWN\n"); + break; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 14, 0)) + case QCOM_SSR_BEFORE_POWERUP: +#else + case SUBSYS_BEFORE_POWERUP: +#endif + IPAWANINFO("IPA received RMT MPSS BEFORE_POWERUP\n"); + break; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 14, 0)) + case QCOM_SSR_AFTER_POWERUP: +#else + case SUBSYS_AFTER_POWERUP: +#endif + IPAWANINFO("IPA received RMT MPSS AFTER_POWERUP\n"); + break; + default: + IPAWANDBG("IPA received RMT MPSS event %lu", code); + break; + } + return NOTIFY_DONE; +} + +/** + * rmnet_ipa_free_msg() - Free the msg sent to user space via ipa_send_msg + * @buff: pointer to buffer containing the message + * @len: message len + * @type: message type + * + * This function is invoked when ipa_send_msg is complete (Provided as a + * free function pointer along with the message). + */ +static void rmnet_ipa_free_msg(void *buff, u32 len, u32 type) +{ + if (!buff) { + IPAWANERR("Null buffer\n"); + return; + } + + if (type != IPA_TETHERING_STATS_UPDATE_STATS && + type != IPA_TETHERING_STATS_UPDATE_NETWORK_STATS && + type != IPA_PER_CLIENT_STATS_CONNECT_EVENT && + type != IPA_PER_CLIENT_STATS_DISCONNECT_EVENT) { + IPAWANERR("Wrong type given. buff %pK type %d\n", + buff, type); + } + kfree(buff); +} + +/** + * rmnet_ipa_get_stats_and_update() - Gets pipe stats from Modem + * + * This function queries the IPA Modem driver for the pipe stats + * via QMI, and updates the user space IPA entity. + */ +static void rmnet_ipa_get_stats_and_update(void) +{ + struct ipa_get_data_stats_req_msg_v01 req; + struct ipa_get_data_stats_resp_msg_v01 *resp; + struct ipa_msg_meta msg_meta; + int rc; + + resp = kzalloc(sizeof(struct ipa_get_data_stats_resp_msg_v01), + GFP_KERNEL); + if (!resp) + return; + + memset(&req, 0, sizeof(struct ipa_get_data_stats_req_msg_v01)); + memset(resp, 0, sizeof(struct ipa_get_data_stats_resp_msg_v01)); + + req.ipa_stats_type = QMI_IPA_STATS_TYPE_PIPE_V01; + + rc = ipa3_qmi_get_data_stats(&req, resp); + if (rc) { + IPAWANERR("ipa3_qmi_get_data_stats failed: %d\n", rc); + kfree(resp); + return; + } + + memset(&msg_meta, 0, sizeof(struct ipa_msg_meta)); + msg_meta.msg_type = IPA_TETHERING_STATS_UPDATE_STATS; + msg_meta.msg_len = sizeof(struct ipa_get_data_stats_resp_msg_v01); + rc = ipa_send_msg(&msg_meta, resp, rmnet_ipa_free_msg); + if (rc) { + IPAWANERR("ipa_send_msg failed: %d\n", rc); + kfree(resp); + return; + } +} + +/** + * tethering_stats_poll_queue() - Stats polling function + * @work - Work entry + * + * This function is scheduled periodically (per the interval) in + * order to poll the IPA Modem driver for the pipe stats. + */ +static void tethering_stats_poll_queue(struct work_struct *work) +{ + rmnet_ipa_get_stats_and_update(); + + /* Schedule again only if there's an active polling interval */ + if (ipa3_rmnet_ctx.polling_interval != 0) + schedule_delayed_work(&ipa_tether_stats_poll_wakequeue_work, + msecs_to_jiffies(ipa3_rmnet_ctx.polling_interval*1000)); +} + +/** + * rmnet_ipa_get_network_stats_and_update() - Get network stats from IPA Modem + * + * This function retrieves the data usage (used quota) from the IPA Modem driver + * via QMI, and updates IPA user space entity. + */ +static void rmnet_ipa_get_network_stats_and_update(void) +{ + struct ipa_get_apn_data_stats_req_msg_v01 req; + struct ipa_get_apn_data_stats_resp_msg_v01 *resp; + struct ipa_msg_meta msg_meta; + int rc; + + resp = kzalloc(sizeof(struct ipa_get_apn_data_stats_resp_msg_v01), + GFP_KERNEL); + if (!resp) + return; + + memset(&req, 0, sizeof(struct ipa_get_apn_data_stats_req_msg_v01)); + memset(resp, 0, sizeof(struct ipa_get_apn_data_stats_resp_msg_v01)); + + req.mux_id_list_valid = true; + req.mux_id_list_len = 1; + req.mux_id_list[0] = ipa3_rmnet_ctx.metered_mux_id; + + rc = ipa3_qmi_get_network_stats(&req, resp); + if (rc) { + IPAWANERR("ipa3_qmi_get_network_stats failed: %d\n", rc); + kfree(resp); + return; + } + + memset(&msg_meta, 0, sizeof(struct ipa_msg_meta)); + msg_meta.msg_type = IPA_TETHERING_STATS_UPDATE_NETWORK_STATS; + msg_meta.msg_len = sizeof(struct ipa_get_apn_data_stats_resp_msg_v01); + rc = ipa_send_msg(&msg_meta, resp, rmnet_ipa_free_msg); + if (rc) { + IPAWANERR("ipa_send_msg failed: %d\n", rc); + kfree(resp); + return; + } +} + +/** + * rmnet_ipa_send_quota_reach_ind() - send quota_reach notification from + * IPA Modem + * This function sends the quota_reach indication from the IPA Modem driver + * via QMI, to user-space module + */ +static void rmnet_ipa_send_quota_reach_ind(bool is_warning_limit) +{ + struct ipa_msg_meta msg_meta; + int rc; + + memset(&msg_meta, 0, sizeof(struct ipa_msg_meta)); + if (!is_warning_limit) + msg_meta.msg_type = IPA_QUOTA_REACH; +#ifdef IPA_DATA_WARNING_QUOTA + else + msg_meta.msg_type = IPA_WARNING_LIMIT_REACHED; +#endif + rc = ipa_send_msg(&msg_meta, NULL, NULL); + if (rc) { + IPAWANERR("ipa_send_msg failed: %d\n", rc); + return; + } +} + +/** + * rmnet_ipa3_poll_tethering_stats() - Tethering stats polling IOCTL handler + * @data - IOCTL data + * + * This function handles WAN_IOC_POLL_TETHERING_STATS. + * In case polling interval received is 0, polling will stop + * (If there's a polling in progress, it will allow it to finish), and then will + * fetch network stats, and update the IPA user space. + * + * Return codes: + * 0: Success + */ +int rmnet_ipa3_poll_tethering_stats(struct wan_ioctl_poll_tethering_stats *data) +{ + struct ipa_stop_data_usage_quota_req_msg_v01 stop_req; + memset(&stop_req, 0, + sizeof(struct ipa_stop_data_usage_quota_req_msg_v01)); + + ipa3_rmnet_ctx.polling_interval = data->polling_interval_secs; + + cancel_delayed_work_sync(&ipa_tether_stats_poll_wakequeue_work); + + if (ipa3_rmnet_ctx.polling_interval == 0) { + /* stop quota */ +#ifdef IPA_DATA_WARNING_QUOTA + stop_req.is_quota_limit_valid = true; + stop_req.is_quota_limit = true; +#endif + ipa3_qmi_stop_data_quota(&stop_req); + + rmnet_ipa_get_network_stats_and_update(); + rmnet_ipa_get_stats_and_update(); + return 0; + } + + schedule_delayed_work(&ipa_tether_stats_poll_wakequeue_work, 0); + return 0; +} + +/** + * rmnet_ipa_set_data_quota_modem() - Data quota setting IOCTL handler + * @data - IOCTL data + * + * This function handles WAN_IOC_SET_DATA_QUOTA on modem interface. + * It translates the given interface name to the Modem MUX ID and + * sends the request of the quota to the IPA Modem driver via QMI. + * + * Return codes: + * 0: Success + * -EFAULT: Invalid interface name provided + * other: See ipa_qmi_set_data_quota + */ +static int rmnet_ipa3_set_data_quota_modem( + struct wan_ioctl_set_data_quota *data) +{ + u32 mux_id; + int index; + struct ipa_set_data_usage_quota_req_msg_v01 req; + struct ipa_stop_data_usage_quota_req_msg_v01 stop_req; + + /* stop quota */ + memset(&stop_req, 0, + sizeof(struct ipa_stop_data_usage_quota_req_msg_v01)); + if (!data->set_quota) { +#ifdef IPA_DATA_WARNING_QUOTA + stop_req.is_quota_limit_valid = true; + stop_req.is_quota_limit = true; +#endif + ipa3_qmi_stop_data_quota(&stop_req); + } + + /* prevent string buffer overflows */ + data->interface_name[IFNAMSIZ-1] = '\0'; + + index = find_vchannel_name_index(data->interface_name); + IPAWANERR("iface name %s, quota %lu\n", + data->interface_name, (unsigned long) data->quota_mbytes); + + if (index == MAX_NUM_OF_MUX_CHANNEL) { + IPAWANERR("%s is an invalid iface name\n", + data->interface_name); + return -ENODEV; + } + + mux_id = rmnet_ipa3_ctx->mux_channel[index].mux_id; + ipa3_rmnet_ctx.metered_mux_id = mux_id; + + memset(&req, 0, sizeof(struct ipa_set_data_usage_quota_req_msg_v01)); + req.apn_quota_list_valid = true; + req.apn_quota_list_len = 1; + req.apn_quota_list[0].mux_id = mux_id; + req.apn_quota_list[0].num_Mbytes = data->quota_mbytes; + + return ipa3_qmi_set_data_quota(&req); +} + +#ifdef IPA_DATA_WARNING_QUOTA +/** + * rmnet_ipa_set_data_quota_warning_modem() - Data quota and warning + * setting handler + * @data - IOCTL data + * + * This function handles WAN_IOC_SET_DATA_QUOTA_WARNING on modem interface. + * It translates the given interface name to the Modem MUX ID and + * sends the request of the quota to the IPA Modem driver via QMI. + * + * Return codes: + * 0: Success + * -EFAULT: Invalid interface name provided + * other: See ipa_qmi_set_data_quota_warning + */ +static int rmnet_ipa3_set_data_quota_warning_modem +( + struct wan_ioctl_set_data_quota_warning *data +) +{ + u32 mux_id; + int index; + struct ipa_set_data_usage_quota_req_msg_v01 req; + struct ipa_stop_data_usage_quota_req_msg_v01 stop_req; + + /* prevent string buffer overflows */ + data->interface_name[IFNAMSIZ-1] = '\0'; + + index = find_vchannel_name_index(data->interface_name); + IPAWANERR("iface name %s, quota %lu, warning %lu\n", + data->interface_name, (unsigned long) data->quota_mbytes, + (unsigned long) data->warning_mbytes); + + if (index == MAX_NUM_OF_MUX_CHANNEL) { + IPAWANERR("%s is an invalid iface name\n", + data->interface_name); + return -ENODEV; + } + /* stop quota or warning */ + memset(&stop_req, 0, + sizeof(struct ipa_stop_data_usage_quota_req_msg_v01)); + if (!data->set_quota || !data->set_warning) { + + if (!data->set_quota) { + stop_req.is_quota_limit_valid = true; + stop_req.is_quota_limit = true; + } + + if (!data->set_warning) { + stop_req.is_warning_limit_valid = true; + stop_req.is_warning_limit = true; + } + ipa3_qmi_stop_data_quota(&stop_req); + } + + mux_id = rmnet_ipa3_ctx->mux_channel[index].mux_id; + ipa3_rmnet_ctx.metered_mux_id = mux_id; + + memset(&req, 0, sizeof(struct ipa_set_data_usage_quota_req_msg_v01)); + if (data->set_quota && (data->quota_mbytes != 0)) { + req.apn_quota_list_valid = true; + req.apn_quota_list_len = 1; + req.apn_quota_list[0].mux_id = mux_id; + req.apn_quota_list[0].num_Mbytes = data->quota_mbytes; + } + + if (data->set_warning && (data->warning_mbytes != 0)) { + req.apn_warning_list_valid = true; + req.apn_warning_list_len = 1; + req.apn_warning_list[0].mux_id = mux_id; + req.apn_warning_list[0].num_Mbytes = data->warning_mbytes; + } + return ipa3_qmi_set_data_quota(&req); +} +#endif + +static int rmnet_ipa3_set_data_quota_wifi(struct wan_ioctl_set_data_quota *data) +{ + struct ipa_set_wifi_quota wifi_quota; + int rc = 0; + + memset(&wifi_quota, 0, sizeof(struct ipa_set_wifi_quota)); + wifi_quota.set_quota = data->set_quota; + wifi_quota.quota_bytes = data->quota_mbytes; + IPAWANDBG("iface name %s, quota %lu\n", + data->interface_name, (unsigned long) data->quota_mbytes); + + if (ipa3_ctx_get_type(IPA_HW_TYPE) >= IPA_HW_v4_5 && + ipa3_ctx_get_type(IPA_HW_TYPE) != IPA_HW_v4_11 && + ipa3_ctx_get_type(IPA_HW_TYPE) != IPA_HW_v5_2) { + IPADBG("use ipa-uc for quota\n"); + rc = ipa3_uc_quota_monitor(data->set_quota); + } else { + rc = ipa3_set_wlan_quota(&wifi_quota); + /* check if wlan-fw takes this quota-set */ + if (!wifi_quota.set_valid) + rc = -EFAULT; + } + return rc; +} + +/** + * rmnet_ipa_set_data_quota() - Data quota setting IOCTL handler + * @data - IOCTL data + * + * This function handles WAN_IOC_SET_DATA_QUOTA. + * It translates the given interface name to the Modem MUX ID and + * sends the request of the quota to the IPA Modem driver via QMI. + * + * Return codes: + * 0: Success + * -EFAULT: Invalid interface name provided + * other: See ipa_qmi_set_data_quota + */ +int rmnet_ipa3_set_data_quota(struct wan_ioctl_set_data_quota *data) +{ + enum ipa_upstream_type upstream_type; + int rc = 0; + + /* prevent string buffer overflows */ + data->interface_name[IFNAMSIZ-1] = '\0'; + + /* get IPA backhaul type */ + upstream_type = find_upstream_type(data->interface_name); + + if (upstream_type == IPA_UPSTEAM_MAX) { + IPAWANERR("Wrong interface_name name %s\n", + data->interface_name); + } else if (upstream_type == IPA_UPSTEAM_WLAN) { + rc = rmnet_ipa3_set_data_quota_wifi(data); + if (rc) { + IPAWANERR("set quota on wifi failed\n"); + return rc; + } + } else { + rc = rmnet_ipa3_set_data_quota_modem(data); + if (rc) { + IPAWANERR("set quota on modem failed\n"); + return rc; + } + } + return rc; +} + +#ifdef IPA_DATA_WARNING_QUOTA +/** + * rmnet_ipa_set_data_quota_warning() - Data quota and warning setting handler + * @data - IOCTL data + * + * This function handles WAN_IOC_SET_DATA_QUOTA_WARNING. + * It translates the given interface name to the Modem MUX ID and + * sends the request of the quota and warning to the IPA Modem driver via QMI. + * + * Return codes: + * 0: Success + * -EFAULT: Invalid interface name provided + * other: See ipa_qmi_set_data_quota + */ +int rmnet_ipa3_set_data_quota_warning +( + struct wan_ioctl_set_data_quota_warning *data +) +{ + enum ipa_upstream_type upstream_type; + int rc = 0; + + /* prevent string buffer overflows */ + data->interface_name[IFNAMSIZ-1] = '\0'; + + /* get IPA backhaul type */ + upstream_type = find_upstream_type(data->interface_name); + + if (upstream_type == IPA_UPSTEAM_MAX) { + IPAWANERR("Wrong interface_name name %s\n", + data->interface_name); + } else if (upstream_type == IPA_UPSTEAM_WLAN) { + /* No support for Data Warning for WLAN backhaul. + * Support only Data Quota. + */ + rc = rmnet_ipa3_set_data_quota_wifi( + (struct wan_ioctl_set_data_quota *)data); + if (rc) { + IPAWANERR("set quota and warning on wifi failed\n"); + return rc; + } + } else { + rc = rmnet_ipa3_set_data_quota_warning_modem(data); + if (rc) { + IPAWANERR("set quota and warning on modem failed\n"); + return rc; + } + } + return rc; +} +#endif + +/* rmnet_ipa_set_tether_client_pipe() - + * @data - IOCTL data + * + * This function handles WAN_IOC_SET_DATA_QUOTA. + * It translates the given interface name to the Modem MUX ID and + * sends the request of the quota to the IPA Modem driver via QMI. + * + * Return codes: + * 0: Success + * -EFAULT: Invalid interface name provided + * other: See ipa_qmi_set_data_quota + */ +int rmnet_ipa3_set_tether_client_pipe( + struct wan_ioctl_set_tether_client_pipe *data) +{ + int number, i; + + /* error checking if ul_src_pipe_len valid or not*/ + if (data->ul_src_pipe_len > QMI_IPA_MAX_PIPES_V01 || + data->ul_src_pipe_len < 0) { + IPAWANERR("UL src pipes %d exceeding max %d\n", + data->ul_src_pipe_len, + QMI_IPA_MAX_PIPES_V01); + return -EFAULT; + } + /* error checking if dl_dst_pipe_len valid or not*/ + if (data->dl_dst_pipe_len > QMI_IPA_MAX_PIPES_V01 || + data->dl_dst_pipe_len < 0) { + IPAWANERR("DL dst pipes %d exceeding max %d\n", + data->dl_dst_pipe_len, + QMI_IPA_MAX_PIPES_V01); + return -EFAULT; + } + + IPAWANDBG("client %d, UL %d, DL %d, reset %d\n", + data->ipa_client, + data->ul_src_pipe_len, + data->dl_dst_pipe_len, + data->reset_client); + number = data->ul_src_pipe_len; + for (i = 0; i < number; i++) { + IPAWANDBG("UL index-%d pipe %d\n", i, + data->ul_src_pipe_list[i]); + if (data->reset_client) + ipa3_set_client(data->ul_src_pipe_list[i], + 0, false); + else + ipa3_set_client(data->ul_src_pipe_list[i], + data->ipa_client, true); + } + number = data->dl_dst_pipe_len; + for (i = 0; i < number; i++) { + IPAWANDBG("DL index-%d pipe %d\n", i, + data->dl_dst_pipe_list[i]); + if (data->reset_client) + ipa3_set_client(data->dl_dst_pipe_list[i], + 0, false); + else + ipa3_set_client(data->dl_dst_pipe_list[i], + data->ipa_client, false); + } + return 0; +} + +static int rmnet_ipa3_query_tethering_stats_wifi( + struct wan_ioctl_query_tether_stats *data, bool reset) +{ + struct ipa_get_wdi_sap_stats *sap_stats; + int rc; + + sap_stats = kzalloc(sizeof(struct ipa_get_wdi_sap_stats), + GFP_KERNEL); + if (!sap_stats) + return -ENOMEM; + + memset(sap_stats, 0, sizeof(struct ipa_get_wdi_sap_stats)); + + sap_stats->reset_stats = reset; + IPAWANDBG("reset the pipe stats %d\n", sap_stats->reset_stats); + + rc = ipa3_get_wlan_stats(sap_stats); + if (rc) { + IPAWANERR_RL("can't get ipa3_get_wlan_stats\n"); + kfree(sap_stats); + return rc; + } else if (data == NULL) { + IPAWANDBG("only reset wlan stats\n"); + kfree(sap_stats); + return 0; + } + + if (sap_stats->stats_valid) { + data->ipv4_tx_packets = sap_stats->ipv4_tx_packets; + data->ipv4_tx_bytes = sap_stats->ipv4_tx_bytes; + data->ipv4_rx_packets = sap_stats->ipv4_rx_packets; + data->ipv4_rx_bytes = sap_stats->ipv4_rx_bytes; + data->ipv6_tx_packets = sap_stats->ipv6_tx_packets; + data->ipv6_tx_bytes = sap_stats->ipv6_tx_bytes; + data->ipv6_rx_packets = sap_stats->ipv6_rx_packets; + data->ipv6_rx_bytes = sap_stats->ipv6_rx_bytes; + } + + IPAWANDBG("v4_rx_p(%lu) v6_rx_p(%lu) v4_rx_b(%lu) v6_rx_b(%lu)\n", + (unsigned long) data->ipv4_rx_packets, + (unsigned long) data->ipv6_rx_packets, + (unsigned long) data->ipv4_rx_bytes, + (unsigned long) data->ipv6_rx_bytes); + IPAWANDBG("tx_p_v4(%lu)v6(%lu)tx_b_v4(%lu) v6(%lu)\n", + (unsigned long) data->ipv4_tx_packets, + (unsigned long) data->ipv6_tx_packets, + (unsigned long) data->ipv4_tx_bytes, + (unsigned long) data->ipv6_tx_bytes); + + kfree(sap_stats); + return rc; +} + +static int rmnet_ipa3_query_tethering_stats_modem( + struct wan_ioctl_query_tether_stats *data, bool reset) +{ + struct ipa_get_data_stats_req_msg_v01 *req; + struct ipa_get_data_stats_resp_msg_v01 *resp; + int pipe_len, rc; + struct ipa_pipe_stats_info_type_v01 *stat_ptr; + + req = kzalloc(sizeof(struct ipa_get_data_stats_req_msg_v01), + GFP_KERNEL); + if (!req) + return -ENOMEM; + + resp = kzalloc(sizeof(struct ipa_get_data_stats_resp_msg_v01), + GFP_KERNEL); + if (!resp) { + kfree(req); + return -ENOMEM; + } + memset(req, 0, sizeof(struct ipa_get_data_stats_req_msg_v01)); + memset(resp, 0, sizeof(struct ipa_get_data_stats_resp_msg_v01)); + + req->ipa_stats_type = QMI_IPA_STATS_TYPE_PIPE_V01; + if (reset) { + req->reset_stats_valid = true; + req->reset_stats = true; + IPAWANDBG("reset the pipe stats\n"); + } + + rc = ipa3_qmi_get_data_stats(req, resp); + if (rc) { + IPAWANERR("can't get ipa_qmi_get_data_stats\n"); + kfree(req); + kfree(resp); + return rc; + } else if (data == NULL) { + IPAWANDBG("only reset modem stats\n"); + kfree(req); + kfree(resp); + return 0; + } + + if (resp->dl_dst_pipe_stats_list_valid) { + for (pipe_len = 0; pipe_len < resp->dl_dst_pipe_stats_list_len; + pipe_len++) { + stat_ptr = + &resp->dl_dst_pipe_stats_list[pipe_len]; + + IPAWANDBG_LOW("Check entry(%d) dl_dst_pipe(%d)\n", + pipe_len, + stat_ptr->pipe_index); + IPAWANDBG_LOW("dl_p_v4(%lu)v6(%lu)\n", + (unsigned long) stat_ptr->num_ipv4_packets, + (unsigned long) stat_ptr->num_ipv6_packets + ); + IPAWANDBG_LOW("dl_b_v4(%lu)v6(%lu)\n", + (unsigned long) stat_ptr->num_ipv4_bytes, + (unsigned long) stat_ptr->num_ipv6_bytes); + if (ipa3_get_client_uplink( + stat_ptr->pipe_index) == false) { + if (data->ipa_client == ipa3_get_client( + stat_ptr->pipe_index)) { + /* update the DL stats */ + data->ipv4_rx_packets += + stat_ptr->num_ipv4_packets; + data->ipv6_rx_packets += + stat_ptr->num_ipv6_packets; + data->ipv4_rx_bytes += + stat_ptr->num_ipv4_bytes; + data->ipv6_rx_bytes += + stat_ptr->num_ipv6_bytes; + } + } + } + } + IPAWANDBG("v4_rx_p(%lu) v6_rx_p(%lu) v4_rx_b(%lu) v6_rx_b(%lu)\n", + (unsigned long) data->ipv4_rx_packets, + (unsigned long) data->ipv6_rx_packets, + (unsigned long) data->ipv4_rx_bytes, + (unsigned long) data->ipv6_rx_bytes); + + if (resp->ul_src_pipe_stats_list_valid) { + for (pipe_len = 0; pipe_len < resp->ul_src_pipe_stats_list_len; + pipe_len++) { + stat_ptr = + &resp->ul_src_pipe_stats_list[pipe_len]; + IPAWANDBG_LOW("Check entry(%d) ul_dst_pipe(%d)\n", + pipe_len, + stat_ptr->pipe_index); + IPAWANDBG_LOW("ul_p_v4(%lu)v6(%lu)\n", + (unsigned long) stat_ptr->num_ipv4_packets, + (unsigned long) stat_ptr->num_ipv6_packets + ); + IPAWANDBG_LOW("ul_b_v4(%lu)v6(%lu)\n", + (unsigned long)stat_ptr->num_ipv4_bytes, + (unsigned long) stat_ptr->num_ipv6_bytes); + if (ipa3_get_client_uplink( + stat_ptr->pipe_index) == true) { + if (data->ipa_client == ipa3_get_client( + stat_ptr->pipe_index)) { + /* update the DL stats */ + data->ipv4_tx_packets += + stat_ptr->num_ipv4_packets; + data->ipv6_tx_packets += + stat_ptr->num_ipv6_packets; + data->ipv4_tx_bytes += + stat_ptr->num_ipv4_bytes; + data->ipv6_tx_bytes += + stat_ptr->num_ipv6_bytes; + } + } + } + } + IPAWANDBG("tx_p_v4(%lu)v6(%lu)tx_b_v4(%lu) v6(%lu)\n", + (unsigned long) data->ipv4_tx_packets, + (unsigned long) data->ipv6_tx_packets, + (unsigned long) data->ipv4_tx_bytes, + (unsigned long) data->ipv6_tx_bytes); + kfree(req); + kfree(resp); + return 0; +} + +static inline enum ipa_client_type rmnet_ipa3_get_wigig_cons(int idx) +{ + switch (idx) { + case 0: + return IPA_CLIENT_WIGIG1_CONS; + case 1: + return IPA_CLIENT_WIGIG2_CONS; + case 2: + return IPA_CLIENT_WIGIG3_CONS; + case 3: + return IPA_CLIENT_WIGIG4_CONS; + default: + IPAWANERR("invalid index %d\n", idx); + return IPA_CLIENT_MAX; + } +} + +static inline int rmnet_ipa3_get_max_wigig_clnt(void) +{ + switch (ipa3_ctx->ipa_hw_type) { + case IPA_HW_v5_5: + return MAX_WIGIG_CLIENTS_IPA_5_5; + case IPA_HW_v4_11: + case IPA_HW_v5_2: + return MAX_WIGIG_CLIENTS_IPA_4_11; + default: + return MAX_WIGIG_CLIENTS; + } +} + +static int rmnet_ipa3_query_tethering_stats_hw( + struct wan_ioctl_query_tether_stats *data, bool reset) +{ + + int rc = 0, index = 0, i = 0; + struct ipa_quota_stats_all *con_stats; + enum ipa_client_type wlan_client; + int ep_idx, wlan_ep_idx, usb_ep_idx, max_wigig_clnts; + + max_wigig_clnts = rmnet_ipa3_get_max_wigig_clnt(); + + /* qet HW-stats */ + rc = ipa_get_teth_stats(); + if (rc) { + IPAWANDBG("ipa_get_teth_stats failed %d,\n", rc); + return rc; + } + + /* query DL stats */ + IPAWANDBG("reset the pipe stats? (%d)\n", reset); + con_stats = kzalloc(sizeof(*con_stats), GFP_KERNEL); + if (!con_stats) { + IPAWANERR("no memory\n"); + return -ENOMEM; + } + + if (rmnet_ipa3_ctx->ipa_config_is_apq) { + rc = ipa_query_teth_stats(IPA_CLIENT_MHI_PRIME_TETH_PROD, + con_stats, reset); + if (rc) { + IPAERR("MHI_PRIME_TETH_PROD query failed %d,\n", rc); + kfree(con_stats); + return rc; + } + } else { + rc = ipa_query_teth_stats(IPA_CLIENT_Q6_WAN_PROD, + con_stats, reset); + if (rc) { + IPAERR("IPA_CLIENT_Q6_WAN_PROD query failed %d,\n", rc); + kfree(con_stats); + return rc; + } + } + + if (ipa3_ctx->ipa_wdi3_over_gsi) + wlan_client = IPA_CLIENT_WLAN2_CONS; + else + wlan_client = IPA_CLIENT_WLAN1_CONS; + + wlan_ep_idx = ipa_get_ep_mapping( wlan_client ); + + if (wlan_ep_idx == -1 || wlan_ep_idx >= ipa3_get_max_num_pipes()) + return wlan_ep_idx ; + + IPAWANDBG("wlan: v4_rx_p-b(%d,%lld) v6_rx_p-b(%d,%lld),client(%d)\n", + con_stats->client[wlan_ep_idx].num_ipv4_pkts, + con_stats->client[wlan_ep_idx].num_ipv4_bytes, + con_stats->client[wlan_ep_idx].num_ipv6_pkts, + con_stats->client[wlan_ep_idx].num_ipv6_bytes, + wlan_client); + + + usb_ep_idx = ipa_get_ep_mapping( IPA_CLIENT_USB_CONS ); + + if (usb_ep_idx == -1 || usb_ep_idx >= ipa3_get_max_num_pipes()) + return usb_ep_idx ; + + IPAWANDBG("usb: v4_rx_p(%d) b(%lld) v6_rx_p(%d) b(%lld)\n", + con_stats->client[usb_ep_idx].num_ipv4_pkts, + con_stats->client[usb_ep_idx].num_ipv4_bytes, + con_stats->client[usb_ep_idx].num_ipv6_pkts, + con_stats->client[usb_ep_idx].num_ipv6_bytes); + + for (i = 0; i < max_wigig_clnts; i++) { + enum ipa_client_type wigig_client = + rmnet_ipa3_get_wigig_cons(i); + + ep_idx = ipa_get_ep_mapping( wigig_client ); + + if (ep_idx == -1 || ep_idx >= ipa3_get_max_num_pipes()) + return ep_idx ; + + + IPAWANDBG("wigig%d: v4_rx_p(%d) b(%lld) v6_rx_p(%d) b(%lld)\n", + i + 1, + con_stats->client[ep_idx].num_ipv4_pkts, + con_stats->client[ep_idx].num_ipv4_bytes, + con_stats->client[ep_idx].num_ipv6_pkts, + con_stats->client[ep_idx].num_ipv6_bytes); + } + + /* update the DL stats */ + data->ipv4_rx_packets = + con_stats->client[wlan_ep_idx].num_ipv4_pkts + + con_stats->client[usb_ep_idx].num_ipv4_pkts; + data->ipv6_rx_packets = + con_stats->client[wlan_ep_idx].num_ipv6_pkts + + con_stats->client[usb_ep_idx].num_ipv6_pkts; + data->ipv4_rx_bytes = + con_stats->client[wlan_ep_idx].num_ipv4_bytes + + con_stats->client[usb_ep_idx].num_ipv4_bytes; + data->ipv6_rx_bytes = + con_stats->client[wlan_ep_idx].num_ipv6_bytes + + con_stats->client[usb_ep_idx].num_ipv6_bytes; + + for (i = 0; i < max_wigig_clnts; i++) { + enum ipa_client_type wigig_client = + rmnet_ipa3_get_wigig_cons(i); + + ep_idx = ipa_get_ep_mapping( wigig_client ); + + if (ep_idx == -1 || ep_idx >= ipa3_get_max_num_pipes()) + return ep_idx ; + + data->ipv4_rx_packets += + con_stats->client[ep_idx].num_ipv4_pkts; + data->ipv6_rx_packets += + con_stats->client[ep_idx].num_ipv6_pkts; + data->ipv4_rx_bytes += + con_stats->client[ep_idx].num_ipv4_bytes; + data->ipv6_rx_bytes += + con_stats->client[ep_idx].num_ipv6_bytes; + } + + IPAWANDBG("v4_rx_p(%lu) v6_rx_p(%lu) v4_rx_b(%lu) v6_rx_b(%lu)\n", + (unsigned long) data->ipv4_rx_packets, + (unsigned long) data->ipv6_rx_packets, + (unsigned long) data->ipv4_rx_bytes, + (unsigned long) data->ipv6_rx_bytes); + + if (ipa3_ctx->ipa_hw_type < IPA_HW_v4_5 || + ipa3_ctx->platform_type == IPA_PLAT_TYPE_APQ) + goto skip_nlo_stats; + + memset(con_stats, 0, sizeof(struct ipa_quota_stats_all)); + rc = ipa_query_teth_stats(IPA_CLIENT_Q6_DL_NLO_DATA_PROD, + con_stats, reset); + if (rc) { + IPAERR("IPA_CLIENT_Q6_DL_NLO_DATA_PROD query failed %d,\n", rc); + kfree(con_stats); + return rc; + } + + if (ipa3_ctx->ipa_wdi3_over_gsi) + wlan_client = IPA_CLIENT_WLAN2_CONS; + else + wlan_client = IPA_CLIENT_WLAN1_CONS; + + wlan_ep_idx = ipa_get_ep_mapping( wlan_client ); + + if (wlan_ep_idx == -1 || wlan_ep_idx >= ipa3_get_max_num_pipes()) + return wlan_ep_idx ; + + IPAWANDBG("wlan: v4_rx_p-b(%d,%lld) v6_rx_p-b(%d,%lld),client(%d)\n", + con_stats->client[wlan_ep_idx].num_ipv4_pkts, + con_stats->client[wlan_ep_idx].num_ipv4_bytes, + con_stats->client[wlan_ep_idx].num_ipv6_pkts, + con_stats->client[wlan_ep_idx].num_ipv6_bytes, + wlan_client); + + IPAWANDBG("usb: v4_rx_p(%d) b(%lld) v6_rx_p(%d) b(%lld)\n", + con_stats->client[usb_ep_idx].num_ipv4_pkts, + con_stats->client[usb_ep_idx].num_ipv4_bytes, + con_stats->client[usb_ep_idx].num_ipv6_pkts, + con_stats->client[usb_ep_idx].num_ipv6_bytes); + + for (i = 0; i < max_wigig_clnts; i++) { + enum ipa_client_type wigig_client = + rmnet_ipa3_get_wigig_cons(i); + + ep_idx = ipa_get_ep_mapping( wigig_client ); + + if (ep_idx == -1 || ep_idx >= ipa3_get_max_num_pipes()) + return ep_idx ; + + IPAWANDBG("wigig%d: v4_rx_p(%d) b(%lld) v6_rx_p(%d) b(%lld)\n", + i + 1, + con_stats->client[ep_idx].num_ipv4_pkts, + con_stats->client[ep_idx].num_ipv4_bytes, + con_stats->client[ep_idx].num_ipv6_pkts, + con_stats->client[ep_idx].num_ipv6_bytes); + } + + /* update the DL stats */ + data->ipv4_rx_packets += + con_stats->client[wlan_ep_idx].num_ipv4_pkts + + con_stats->client[usb_ep_idx].num_ipv4_pkts; + data->ipv6_rx_packets += + con_stats->client[wlan_ep_idx].num_ipv6_pkts + + con_stats->client[usb_ep_idx].num_ipv6_pkts; + data->ipv4_rx_bytes += + con_stats->client[wlan_ep_idx].num_ipv4_bytes + + con_stats->client[usb_ep_idx].num_ipv4_bytes; + data->ipv6_rx_bytes += + con_stats->client[wlan_ep_idx].num_ipv6_bytes + + con_stats->client[usb_ep_idx].num_ipv6_bytes; + + for (i = 0; i < max_wigig_clnts; i++) { + enum ipa_client_type wigig_client = + rmnet_ipa3_get_wigig_cons(i); + + ep_idx = ipa_get_ep_mapping( wigig_client ); + + if (ep_idx == -1 || ep_idx >= ipa3_get_max_num_pipes()) + return ep_idx ; + + data->ipv4_rx_packets += + con_stats->client[ep_idx].num_ipv4_pkts; + data->ipv6_rx_packets += + con_stats->client[ep_idx].num_ipv6_pkts; + data->ipv4_rx_bytes += + con_stats->client[ep_idx].num_ipv4_bytes; + data->ipv6_rx_bytes += + con_stats->client[ep_idx].num_ipv6_bytes; + } + + IPAWANDBG("v4_rx_p(%lu) v6_rx_p(%lu) v4_rx_b(%lu) v6_rx_b(%lu)\n", + (unsigned long) data->ipv4_rx_packets, + (unsigned long) data->ipv6_rx_packets, + (unsigned long) data->ipv4_rx_bytes, + (unsigned long) data->ipv6_rx_bytes); + + if(ipa3_ctx->ipa_hw_type < IPA_HW_v5_0) + goto skip_nlo_stats; + + memset(con_stats, 0, sizeof(struct ipa_quota_stats_all)); + rc = ipa_query_teth_stats(IPA_CLIENT_Q6_DL_NLO_LL_DATA_PROD, + con_stats, reset); + if (rc) { + IPAERR("IPA_CLIENT_Q6_DL_NLO_DATA_PROD query failed %d,\n", rc); + kfree(con_stats); + return rc; + } + + if (ipa3_ctx->ipa_wdi3_over_gsi) + wlan_client = IPA_CLIENT_WLAN2_CONS; + else + wlan_client = IPA_CLIENT_WLAN1_CONS; + + wlan_ep_idx = ipa_get_ep_mapping( wlan_client ); + + if (wlan_ep_idx == -1 || wlan_ep_idx >= ipa3_get_max_num_pipes()) + return wlan_ep_idx ; + + IPAWANDBG("wlan: v4_rx_p-b(%d,%lld) v6_rx_p-b(%d,%lld),client(%d)\n", + con_stats->client[wlan_ep_idx].num_ipv4_pkts, + con_stats->client[wlan_ep_idx].num_ipv4_bytes, + con_stats->client[wlan_ep_idx].num_ipv6_pkts, + con_stats->client[wlan_ep_idx].num_ipv6_bytes, + wlan_client); + + IPAWANDBG("usb: v4_rx_p(%d) b(%lld) v6_rx_p(%d) b(%lld)\n", + con_stats->client[usb_ep_idx].num_ipv4_pkts, + con_stats->client[usb_ep_idx].num_ipv4_bytes, + con_stats->client[usb_ep_idx].num_ipv6_pkts, + con_stats->client[usb_ep_idx].num_ipv6_bytes); + + for (i = 0; i < max_wigig_clnts; i++) { + enum ipa_client_type wigig_client = + rmnet_ipa3_get_wigig_cons(i); + + ep_idx = ipa_get_ep_mapping( wigig_client ); + + if (ep_idx == -1 || ep_idx >= ipa3_get_max_num_pipes()) + return ep_idx ; + + IPAWANDBG("wigig%d: v4_rx_p(%d) b(%lld) v6_rx_p(%d) b(%lld)\n", + i + 1, + con_stats->client[ep_idx].num_ipv4_pkts, + con_stats->client[ep_idx].num_ipv4_bytes, + con_stats->client[ep_idx].num_ipv6_pkts, + con_stats->client[ep_idx].num_ipv6_bytes); + } + + /* update the DL stats */ + data->ipv4_rx_packets += + con_stats->client[wlan_ep_idx].num_ipv4_pkts + + con_stats->client[IPA_CLIENT_USB_CONS].num_ipv4_pkts; + data->ipv6_rx_packets += + con_stats->client[wlan_ep_idx].num_ipv6_pkts + + con_stats->client[IPA_CLIENT_USB_CONS].num_ipv6_pkts; + data->ipv4_rx_bytes += + con_stats->client[wlan_ep_idx].num_ipv4_bytes + + con_stats->client[IPA_CLIENT_USB_CONS].num_ipv4_bytes; + data->ipv6_rx_bytes += + con_stats->client[wlan_ep_idx].num_ipv6_bytes + + con_stats->client[IPA_CLIENT_USB_CONS].num_ipv6_bytes; + + for (i = 0; i < max_wigig_clnts; i++) { + enum ipa_client_type wigig_client = + rmnet_ipa3_get_wigig_cons(i); + + ep_idx = ipa_get_ep_mapping( wigig_client ); + + if (ep_idx == -1 || ep_idx >= ipa3_get_max_num_pipes()) + return ep_idx ; + data->ipv4_rx_packets += + con_stats->client[ep_idx].num_ipv4_pkts; + data->ipv6_rx_packets += + con_stats->client[ep_idx].num_ipv6_pkts; + data->ipv4_rx_bytes += + con_stats->client[ep_idx].num_ipv4_bytes; + data->ipv6_rx_bytes += + con_stats->client[ep_idx].num_ipv6_bytes; + } + + IPAWANDBG("v4_rx_p(%lu) v6_rx_p(%lu) v4_rx_b(%lu) v6_rx_b(%lu)\n", + (unsigned long) data->ipv4_rx_packets, + (unsigned long) data->ipv6_rx_packets, + (unsigned long) data->ipv4_rx_bytes, + (unsigned long) data->ipv6_rx_bytes); + +skip_nlo_stats: + /* query USB UL stats */ + memset(con_stats, 0, sizeof(struct ipa_quota_stats_all)); + rc = ipa_query_teth_stats(IPA_CLIENT_USB_PROD, con_stats, reset); + if (rc) { + IPAERR("IPA_CLIENT_USB_PROD query failed %d\n", rc); + kfree(con_stats); + return rc; + } + + if (rmnet_ipa3_ctx->ipa_config_is_apq) + index = IPA_CLIENT_MHI_PRIME_TETH_CONS; + else + index = IPA_CLIENT_Q6_WAN_CONS; + ep_idx = ipa_get_ep_mapping( index ); + + if (ep_idx == -1 || ep_idx >= ipa3_get_max_num_pipes()) + return ep_idx ; + + IPAWANDBG("usb: v4_tx_p(%d) b(%lld) v6_tx_p(%d) b(%lld)\n", + con_stats->client[ep_idx].num_ipv4_pkts, + con_stats->client[ep_idx].num_ipv4_bytes, + con_stats->client[ep_idx].num_ipv6_pkts, + con_stats->client[ep_idx].num_ipv6_bytes); + + /* update the USB UL stats */ + data->ipv4_tx_packets = + con_stats->client[ep_idx].num_ipv4_pkts; + data->ipv6_tx_packets = + con_stats->client[ep_idx].num_ipv6_pkts; + data->ipv4_tx_bytes = + con_stats->client[ep_idx].num_ipv4_bytes; + data->ipv6_tx_bytes = + con_stats->client[ep_idx].num_ipv6_bytes; + + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_5 && + ipa3_ctx->platform_type == IPA_PLAT_TYPE_MSM) { + + index = IPA_CLIENT_Q6_UL_NLO_DATA_CONS; + + ep_idx = ipa_get_ep_mapping( index ); + + if (ep_idx == -1 || ep_idx >= ipa3_get_max_num_pipes()) + return ep_idx ; + + IPAWANDBG("usb: v4_tx_p(%d) b(%lld) v6_tx_p(%d) b(%lld)\n", + con_stats->client[ep_idx].num_ipv4_pkts, + con_stats->client[ep_idx].num_ipv4_bytes, + con_stats->client[ep_idx].num_ipv6_pkts, + con_stats->client[ep_idx].num_ipv6_bytes); + + /* update the USB UL stats */ + data->ipv4_tx_packets += + con_stats->client[ep_idx].num_ipv4_pkts; + data->ipv6_tx_packets += + con_stats->client[ep_idx].num_ipv6_pkts; + data->ipv4_tx_bytes += + con_stats->client[ep_idx].num_ipv4_bytes; + data->ipv6_tx_bytes += + con_stats->client[ep_idx].num_ipv6_bytes; + } + /* query WLAN UL stats */ + memset(con_stats, 0, sizeof(struct ipa_quota_stats_all)); + + if (ipa3_ctx->ipa_wdi3_over_gsi) + rc = ipa_query_teth_stats(IPA_CLIENT_WLAN2_PROD, + con_stats, reset); + else + rc = ipa_query_teth_stats(IPA_CLIENT_WLAN1_PROD, + con_stats, reset); + + if (rc) { + IPAERR("IPA_CLIENT_WLAN_PROD query failed %d\n", rc); + kfree(con_stats); + return rc; + } + + if (rmnet_ipa3_ctx->ipa_config_is_apq) + index = IPA_CLIENT_MHI_PRIME_TETH_CONS; + else + index = IPA_CLIENT_Q6_WAN_CONS; + + ep_idx = ipa_get_ep_mapping( index ); + + if (ep_idx == -1 || ep_idx >= ipa3_get_max_num_pipes()) + return ep_idx ; + + IPAWANDBG("wlan1: v4_tx_p(%d) b(%lld) v6_tx_p(%d) b(%lld)\n", + con_stats->client[ep_idx].num_ipv4_pkts, + con_stats->client[ep_idx].num_ipv4_bytes, + con_stats->client[ep_idx].num_ipv6_pkts, + con_stats->client[ep_idx].num_ipv6_bytes); + + /* update the wlan UL stats */ + data->ipv4_tx_packets += + con_stats->client[ep_idx].num_ipv4_pkts; + data->ipv6_tx_packets += + con_stats->client[ep_idx].num_ipv6_pkts; + data->ipv4_tx_bytes += + con_stats->client[ep_idx].num_ipv4_bytes; + data->ipv6_tx_bytes += + con_stats->client[ep_idx].num_ipv6_bytes; + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_5 && + ipa3_ctx->platform_type == IPA_PLAT_TYPE_MSM) { + index = IPA_CLIENT_Q6_UL_NLO_DATA_CONS; + + ep_idx = ipa_get_ep_mapping( index ); + + if (ep_idx == -1 || ep_idx >= ipa3_get_max_num_pipes()) + return ep_idx ; + IPAWANDBG("wlan1: v4_tx_p(%d) b(%lld) v6_tx_p(%d) b(%lld)\n", + con_stats->client[ep_idx].num_ipv4_pkts, + con_stats->client[ep_idx].num_ipv4_bytes, + con_stats->client[ep_idx].num_ipv6_pkts, + con_stats->client[ep_idx].num_ipv6_bytes); + + /* update the USB UL stats */ + data->ipv4_tx_packets += + con_stats->client[ep_idx].num_ipv4_pkts; + data->ipv6_tx_packets += + con_stats->client[ep_idx].num_ipv6_pkts; + data->ipv4_tx_bytes += + con_stats->client[ep_idx].num_ipv4_bytes; + data->ipv6_tx_bytes += + con_stats->client[ep_idx].num_ipv6_bytes; + } + + if (ipa_get_ep_mapping(IPA_CLIENT_WIGIG_PROD) != + IPA_EP_NOT_ALLOCATED) { + /* query WIGIG UL stats */ + memset(con_stats, 0, sizeof(struct ipa_quota_stats_all)); + rc = ipa_query_teth_stats(IPA_CLIENT_WIGIG_PROD, con_stats, + reset); + if (rc) { + IPAERR("IPA_CLIENT_WIGIG_PROD query failed %d\n", rc); + kfree(con_stats); + return rc; + } + + if (rmnet_ipa3_ctx->ipa_config_is_apq) + index = IPA_CLIENT_MHI_PRIME_TETH_CONS; + else + index = IPA_CLIENT_Q6_WAN_CONS; + + ep_idx = ipa_get_ep_mapping( index ); + + if (ep_idx == -1 || ep_idx >= ipa3_get_max_num_pipes()) + return ep_idx ; + + IPAWANDBG("wigig: v4_tx_p(%d) b(%lld) v6_tx_p(%d) b(%lld)\n", + con_stats->client[ep_idx].num_ipv4_pkts, + con_stats->client[ep_idx].num_ipv4_bytes, + con_stats->client[ep_idx].num_ipv6_pkts, + con_stats->client[ep_idx].num_ipv6_bytes); + + /* update the WIGIG UL stats */ + data->ipv4_tx_packets += + con_stats->client[ep_idx].num_ipv4_pkts; + data->ipv6_tx_packets += + con_stats->client[ep_idx].num_ipv6_pkts; + data->ipv4_tx_bytes += + con_stats->client[ep_idx].num_ipv4_bytes; + data->ipv6_tx_bytes += + con_stats->client[ep_idx].num_ipv6_bytes; + + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_5 && + ipa3_ctx->platform_type == IPA_PLAT_TYPE_MSM) { + index = IPA_CLIENT_Q6_UL_NLO_DATA_CONS; + + ep_idx = ipa_get_ep_mapping( index ); + + if (ep_idx == -1 || ep_idx >= ipa3_get_max_num_pipes()) + return ep_idx ; + /* update the WIGIG UL stats */ + data->ipv4_tx_packets += + con_stats->client[ep_idx].num_ipv4_pkts; + data->ipv6_tx_packets += + con_stats->client[ep_idx].num_ipv6_pkts; + data->ipv4_tx_bytes += + con_stats->client[ep_idx].num_ipv4_bytes; + data->ipv6_tx_bytes += + con_stats->client[ep_idx].num_ipv6_bytes; + } + + } else { + IPAWANDBG("IPA_CLIENT_WIGIG_PROD client not supported\n"); + } + + IPAWANDBG("v4_tx_p(%lu) v6_tx_p(%lu) v4_tx_b(%lu) v6_tx_b(%lu)\n", + (unsigned long) data->ipv4_tx_packets, + (unsigned long) data->ipv6_tx_packets, + (unsigned long) data->ipv4_tx_bytes, + (unsigned long) data->ipv6_tx_bytes); + kfree(con_stats); + return rc; +} + +static int rmnet_ipa3_query_tethering_stats_fnr( + struct wan_ioctl_query_tether_stats_all *data) +{ + int rc = 0; + int num_counters; + struct ipa_ioc_flt_rt_query fnr_stats, fnr_stats_sw; + struct ipacm_fnr_info fnr_info; + + memset(&fnr_stats, 0, sizeof(struct ipa_ioc_flt_rt_query)); + memset(&fnr_stats_sw, 0, sizeof(struct ipa_ioc_flt_rt_query)); + memset(&fnr_info, 0, sizeof(struct ipacm_fnr_info)); + + if (!ipa_get_fnr_info(&fnr_info)) { + IPAERR("FNR counter haven't configured\n"); + return -EINVAL; + } + + fnr_stats.start_id = fnr_info.hw_counter_offset + UL_HW; + fnr_stats.end_id = fnr_info.hw_counter_offset + DL_HW; + fnr_stats.reset = data->reset_stats; + num_counters = fnr_stats.end_id - fnr_stats.start_id + 1; + + if (num_counters != 2) { + IPAWANERR("Only query 2 counters\n"); + return -EINVAL; + } + + fnr_stats.stats = (uint64_t)kcalloc( + num_counters, + sizeof(struct ipa_flt_rt_stats), + GFP_KERNEL); + if (!fnr_stats.stats) { + IPAERR("Failed to allocate memory for query hw-stats\n"); + return -ENOMEM; + } + + if (ipa_get_flt_rt_stats(&fnr_stats)) { + IPAERR("Failed to request stats from h/w\n"); + rc = -EINVAL; + goto free_stats; + } + + IPAWANDBG("ul: bytes = %llu, pkts = %u, pkts_hash = %u\n", + ((struct ipa_flt_rt_stats *)fnr_stats.stats)[0].num_bytes, + ((struct ipa_flt_rt_stats *)fnr_stats.stats)[0].num_pkts, + ((struct ipa_flt_rt_stats *)fnr_stats.stats)[0].num_pkts_hash); + IPAWANDBG("dl: bytes = %llu, pkts = %u, pkts_hash = %u\n", + ((struct ipa_flt_rt_stats *)fnr_stats.stats)[1].num_bytes, + ((struct ipa_flt_rt_stats *)fnr_stats.stats)[1].num_pkts, + ((struct ipa_flt_rt_stats *)fnr_stats.stats)[1].num_pkts_hash); + + data->tx_bytes = + ((struct ipa_flt_rt_stats *)fnr_stats.stats)[0].num_bytes; + data->rx_bytes = + ((struct ipa_flt_rt_stats *)fnr_stats.stats)[1].num_bytes; + + /* get the sw stats */ + fnr_stats_sw.start_id = fnr_info.sw_counter_offset + UL_HW_CACHE; + fnr_stats_sw.end_id = fnr_info.sw_counter_offset + DL_HW_CACHE; + fnr_stats_sw.reset = data->reset_stats; + num_counters = fnr_stats_sw.end_id - fnr_stats_sw.start_id + 1; + + if (num_counters != 2) { + IPAWANERR("Only query 2 counters\n"); + return -EINVAL; + } + + fnr_stats_sw.stats = (uint64_t)kcalloc( + num_counters, + sizeof(struct ipa_flt_rt_stats), + GFP_KERNEL); + if (!fnr_stats_sw.stats) { + IPAERR("Failed to allocate memory for query sw-stats\n"); + return -ENOMEM; + } + + if (ipa_get_flt_rt_stats(&fnr_stats_sw)) { + IPAERR("Failed to request stats from h/w\n"); + rc = -EINVAL; + goto free_stats2; + } + + IPAWANDBG("ul sw: bytes = %llu, pkts = %u, pkts_hash = %u\n", + ((struct ipa_flt_rt_stats *)fnr_stats_sw.stats)[0].num_bytes, + ((struct ipa_flt_rt_stats *)fnr_stats_sw.stats)[0].num_pkts, + ((struct ipa_flt_rt_stats *)fnr_stats_sw.stats)[0].num_pkts_hash); + IPAWANDBG("dl sw: bytes = %llu, pkts = %u, pkts_hash = %u\n", + ((struct ipa_flt_rt_stats *)fnr_stats_sw.stats)[1].num_bytes, + ((struct ipa_flt_rt_stats *)fnr_stats_sw.stats)[1].num_pkts, + ((struct ipa_flt_rt_stats *)fnr_stats_sw.stats)[1].num_pkts_hash); + + /* update the sw-cache */ + ((struct ipa_flt_rt_stats *)fnr_stats_sw.stats)[0].num_bytes += + ((struct ipa_flt_rt_stats *)fnr_stats.stats)[0].num_bytes; + ((struct ipa_flt_rt_stats *)fnr_stats_sw.stats)[0].num_pkts += + ((struct ipa_flt_rt_stats *)fnr_stats.stats)[0].num_pkts; + ((struct ipa_flt_rt_stats *)fnr_stats_sw.stats)[0].num_pkts_hash += + ((struct ipa_flt_rt_stats *)fnr_stats.stats)[0].num_pkts_hash; + ((struct ipa_flt_rt_stats *)fnr_stats_sw.stats)[1].num_bytes += + ((struct ipa_flt_rt_stats *)fnr_stats.stats)[1].num_bytes; + ((struct ipa_flt_rt_stats *)fnr_stats_sw.stats)[1].num_pkts += + ((struct ipa_flt_rt_stats *)fnr_stats.stats)[1].num_pkts; + ((struct ipa_flt_rt_stats *)fnr_stats_sw.stats)[1].num_pkts_hash += + ((struct ipa_flt_rt_stats *)fnr_stats.stats)[1].num_pkts_hash; + + IPAWANDBG("ul sw: bytes = %llu, pkts = %u, pkts_hash = %u\n", + ((struct ipa_flt_rt_stats *)fnr_stats_sw.stats)[0].num_bytes, + ((struct ipa_flt_rt_stats *)fnr_stats_sw.stats)[0].num_pkts, + ((struct ipa_flt_rt_stats *)fnr_stats_sw.stats)[0].num_pkts_hash); + IPAWANDBG("dl sw: bytes = %llu, pkts = %u, pkts_hash = %u\n", + ((struct ipa_flt_rt_stats *)fnr_stats_sw.stats)[1].num_bytes, + ((struct ipa_flt_rt_stats *)fnr_stats_sw.stats)[1].num_pkts, + ((struct ipa_flt_rt_stats *)fnr_stats_sw.stats)[1].num_pkts_hash); + /* write to the sw cache */ + if (ipa_set_flt_rt_stats(fnr_info.sw_counter_offset + + UL_HW_CACHE, + ((struct ipa_flt_rt_stats *)fnr_stats_sw.stats)[0])) { + IPAERR("Failed to set stats to sw-cache %d\n", + fnr_info.sw_counter_offset + UL_HW_CACHE); + rc = -EINVAL; + goto free_stats2; + } + + if (ipa_set_flt_rt_stats(fnr_info.sw_counter_offset + + DL_HW_CACHE, + ((struct ipa_flt_rt_stats *)fnr_stats_sw.stats)[1])) { + IPAERR("Failed to set stats to sw-cache %d\n", + fnr_info.sw_counter_offset + DL_HW_CACHE); + rc = -EINVAL; + goto free_stats2; + } + +free_stats2: + kfree((void *)fnr_stats_sw.stats); +free_stats: + kfree((void *)fnr_stats.stats); + return rc; +} + +int rmnet_ipa3_query_tethering_stats(struct wan_ioctl_query_tether_stats *data, + bool reset) +{ + enum ipa_upstream_type upstream_type; + int rc = 0; + + /* prevent string buffer overflows */ + data->upstreamIface[IFNAMSIZ-1] = '\0'; + data->tetherIface[IFNAMSIZ-1] = '\0'; + + /* get IPA backhaul type */ + upstream_type = find_upstream_type(data->upstreamIface); + + if (upstream_type == IPA_UPSTEAM_MAX) { + IPAWANERR(" Wrong upstreamIface name %s\n", + data->upstreamIface); + } else if (upstream_type == IPA_UPSTEAM_WLAN) { + IPAWANDBG_LOW(" query wifi-backhaul stats\n"); + rc = rmnet_ipa3_query_tethering_stats_wifi( + data, false); + if (rc) { + IPAWANERR("wlan WAN_IOC_QUERY_TETHER_STATS failed\n"); + return rc; + } + } else { + IPAWANDBG_LOW(" query modem-backhaul stats\n"); + rc = rmnet_ipa3_query_tethering_stats_modem( + data, false); + if (rc) { + IPAWANERR("modem WAN_IOC_QUERY_TETHER_STATS failed\n"); + return rc; + } + } + return rc; +} + +int rmnet_ipa3_query_tethering_stats_all( + struct wan_ioctl_query_tether_stats_all *data) +{ + struct wan_ioctl_query_tether_stats tether_stats; + enum ipa_upstream_type upstream_type; + int rc = 0; + + memset(&tether_stats, 0, sizeof(struct wan_ioctl_query_tether_stats)); + + /* prevent string buffer overflows */ + data->upstreamIface[IFNAMSIZ-1] = '\0'; + + /* get IPA backhaul type */ + upstream_type = find_upstream_type(data->upstreamIface); + + if (upstream_type == IPA_UPSTEAM_MAX) { + IPAWANERR(" Wrong upstreamIface name %s\n", + data->upstreamIface); + } else if (upstream_type == IPA_UPSTEAM_WLAN) { + IPAWANDBG_LOW(" query wifi-backhaul stats\n"); + if (ipa3_ctx_get_type(IPA_HW_TYPE) < IPA_HW_v4_5 || + !ipa3_ctx_get_flag(IPA_HW_STATS_EN)) { + IPAWANDBG("hw version %d,hw_stats.enabled %d\n", + ipa3_ctx_get_type(IPA_HW_TYPE), + ipa3_ctx_get_flag(IPA_HW_STATS_EN)); + rc = rmnet_ipa3_query_tethering_stats_wifi( + &tether_stats, data->reset_stats); + if (rc) { + IPAWANERR_RL( + "wlan WAN_IOC_QUERY_TETHER_STATS failed\n"); + return rc; + } + data->tx_bytes = tether_stats.ipv4_tx_bytes + + tether_stats.ipv6_tx_bytes; + data->rx_bytes = tether_stats.ipv4_rx_bytes + + tether_stats.ipv6_rx_bytes; + } else { + rc = rmnet_ipa3_query_tethering_stats_fnr(data); + if (rc) { + IPAWANERR_RL( + "wlan WAN_IOC_QUERY_TETHER_STATS failed\n"); + return rc; + } + } + } else { + IPAWANDBG_LOW(" query modem-backhaul stats\n"); + tether_stats.ipa_client = data->ipa_client; + if (ipa3_ctx_get_type(IPA_HW_TYPE) < IPA_HW_v4_0 || + !ipa3_ctx_get_flag(IPA_HW_STATS_EN)) { + IPAWANDBG("hw version %d,hw_stats.enabled %d\n", + ipa3_ctx_get_type(IPA_HW_TYPE), + ipa3_ctx_get_flag(IPA_HW_STATS_EN)); + /* get modem stats from QMI */ + rc = rmnet_ipa3_query_tethering_stats_modem( + &tether_stats, data->reset_stats); + if (rc) { + IPAWANERR("modem QUERY_TETHER_STATS failed\n"); + return rc; + } + } else { + /* get modem stats from IPA-HW counters */ + rc = rmnet_ipa3_query_tethering_stats_hw( + &tether_stats, data->reset_stats); + if (rc) { + IPAWANERR("modem QUERY_TETHER_STATS failed\n"); + return rc; + } + } + data->tx_bytes = tether_stats.ipv4_tx_bytes + + tether_stats.ipv6_tx_bytes; + data->rx_bytes = tether_stats.ipv4_rx_bytes + + tether_stats.ipv6_rx_bytes; + } + return rc; +} + +int rmnet_ipa3_reset_tethering_stats(struct wan_ioctl_reset_tether_stats *data) +{ + enum ipa_upstream_type upstream_type; + int rc = 0; + + /* prevent string buffer overflows */ + data->upstreamIface[IFNAMSIZ-1] = '\0'; + + /* get IPA backhaul type */ + upstream_type = find_upstream_type(data->upstreamIface); + + if (upstream_type == IPA_UPSTEAM_MAX) { + IPAWANERR(" Wrong upstreamIface name %s\n", + data->upstreamIface); + } else if (upstream_type == IPA_UPSTEAM_WLAN) { + IPAWANERR(" reset wifi-backhaul stats\n"); + rc = rmnet_ipa3_query_tethering_stats_wifi( + NULL, true); + if (rc) { + IPAWANERR("reset WLAN stats failed\n"); + return rc; + } + } else { + IPAWANERR(" reset modem-backhaul stats\n"); + rc = rmnet_ipa3_query_tethering_stats_modem( + NULL, true); + if (rc) { + IPAWANERR("reset MODEM stats failed\n"); + return rc; + } + } + return rc; +} + +/** + * ipa3_broadcast_quota_reach_ind() - Send Netlink broadcast on Quota + * @mux_id - The MUX ID on which the quota has been reached + * + * This function broadcasts a Netlink event using the kobject of the + * rmnet_ipa interface in order to alert the user space that the quota + * on the specific interface which matches the mux_id has been reached. + * + */ +void ipa3_broadcast_quota_reach_ind(u32 mux_id, + enum ipa_upstream_type upstream_type, bool is_warning_limit) +{ + char alert_msg[IPA_QUOTA_REACH_ALERT_MAX_SIZE]; + char iface_name_m[IPA_QUOTA_REACH_IF_NAME_MAX_SIZE]; + char iface_name_l[IPA_QUOTA_REACH_IF_NAME_MAX_SIZE]; + char *envp[IPA_UEVENT_NUM_EVNP] = { + alert_msg, iface_name_l, iface_name_m, NULL}; + int res; + int index; + + /* check upstream_type*/ + if (upstream_type == IPA_UPSTEAM_MAX) { + IPAWANERR(" Wrong upstreamIface type %d\n", upstream_type); + return; + } else if (upstream_type == IPA_UPSTEAM_WLAN) { + /* TODO: Fix this case when adding quota on WLAN Backhaul*/ + IPAWANERR_RL("Quota indication is not supported for WLAN\n"); + return; + } else if (upstream_type == IPA_UPSTEAM_MODEM) { + index = ipa3_find_mux_channel_index(mux_id); + if (index == MAX_NUM_OF_MUX_CHANNEL) { + IPAWANERR("%u is an mux ID\n", mux_id); + return; + } + } + if (!is_warning_limit) + res = snprintf(alert_msg, IPA_QUOTA_REACH_ALERT_MAX_SIZE, + "ALERT_NAME=%s", "quotaReachedAlert"); + else + res = snprintf(alert_msg, IPA_QUOTA_REACH_ALERT_MAX_SIZE, + "ALERT_NAME=%s", "warningReachedAlert"); + if (res >= IPA_QUOTA_REACH_ALERT_MAX_SIZE) { + IPAWANERR("message too long (%d)", res); + return; + } + /* posting msg for L-release for CNE */ + if (upstream_type == IPA_UPSTEAM_MODEM) { + res = snprintf(iface_name_l, + IPA_QUOTA_REACH_IF_NAME_MAX_SIZE, + "UPSTREAM=%s", + rmnet_ipa3_ctx->mux_channel[index].vchannel_name); + } else { + res = snprintf(iface_name_l, IPA_QUOTA_REACH_IF_NAME_MAX_SIZE, + "UPSTREAM=%s", IPA_UPSTEAM_WLAN_IFACE_NAME); + } + if (res >= IPA_QUOTA_REACH_IF_NAME_MAX_SIZE) { + IPAWANERR("message too long (%d)", res); + return; + } + /* posting msg for M-release for CNE */ + if (upstream_type == IPA_UPSTEAM_MODEM) { + res = snprintf(iface_name_m, + IPA_QUOTA_REACH_IF_NAME_MAX_SIZE, + "INTERFACE=%s", + rmnet_ipa3_ctx->mux_channel[index].vchannel_name); + } else { + res = snprintf(iface_name_m, + IPA_QUOTA_REACH_IF_NAME_MAX_SIZE, + "INTERFACE=%s", + IPA_UPSTEAM_WLAN_IFACE_NAME); + } + if (res >= IPA_QUOTA_REACH_IF_NAME_MAX_SIZE) { + IPAWANERR("message too long (%d)", res); + return; + } + + IPAWANDBG("putting nlmsg: <%s> <%s> <%s>\n", + alert_msg, iface_name_l, iface_name_m); + kobject_uevent_env(&(IPA_NETDEV()->dev.kobj), + KOBJ_CHANGE, envp); + + rmnet_ipa_send_quota_reach_ind(is_warning_limit); +} + +/** + * ipa3_q6_handshake_complete() - Perform operations once Q6 is up + * @ssr_bootup - Indicates whether this is a cold boot-up or post-SSR. + * + * This function is invoked once the handshake between the IPA AP driver + * and IPA Q6 driver is complete. At this point, it is possible to perform + * operations which can't be performed until IPA Q6 driver is up. + * + */ +void ipa3_q6_handshake_complete(bool ssr_bootup) +{ + /* It is required to recover the network stats after SSR recovery */ + if (ssr_bootup) { + /* + * In case the uC is required to be loaded by the Modem, + * the proxy vote will be removed only when uC loading is + * complete and indication is received by the AP. After SSR, + * uC is already loaded. Therefore, proxy vote can be removed + * once Modem init is complete. + */ + ipa3_proxy_clk_unvote(); + + /* send SSR power-up notification to IPACM */ + rmnet_ipa_send_ssr_notification(true); + + /* + * It is required to recover the network stats after + * SSR recovery + */ + rmnet_ipa_get_network_stats_and_update(); + } + + if (ipa3_ctx->ipa_mhi_proxy) + imp_handle_modem_ready(); + + ipa3_set_modem_up(true); + if (ipa3_ctx->ipa_config_is_mhi) + ipa_send_mhi_endp_ind_to_modem(); +} + +static inline bool rmnet_ipa3_check_any_client_inited +( + enum ipacm_per_client_device_type device_type +) +{ + int i = 0; + struct ipa_tether_device_info *teth_ptr = NULL; + + for (; i < IPA_MAX_NUM_HW_PATH_CLIENTS; i++) { + teth_ptr = &rmnet_ipa3_ctx->tether_device[device_type]; + + if (teth_ptr->lan_client[i].client_idx != -1 && + teth_ptr->lan_client[i].inited) { + IPAWANERR("Found client index: %d which is inited\n", + i); + return true; + } + } + + return false; +} + +static inline int rmnet_ipa3_get_lan_client_info +( + enum ipacm_per_client_device_type device_type, + uint8_t mac[] +) +{ + int i = 0; + struct ipa_tether_device_info *teth_ptr = NULL; + + IPAWANDBG("Client MAC %02x:%02x:%02x:%02x:%02x:%02x\n", + mac[0], mac[1], mac[2], + mac[3], mac[4], mac[5]); + + for (; i < IPA_MAX_NUM_HW_PATH_CLIENTS; i++) { + teth_ptr = &rmnet_ipa3_ctx->tether_device[device_type]; + + if (memcmp( + teth_ptr->lan_client[i].mac, + mac, + IPA_MAC_ADDR_SIZE) == 0) { + IPAWANDBG("Matched client index: %d\n", i); + return i; + } + } + + return -EINVAL; +} + +static inline int rmnet_ipa3_delete_lan_client_info +( + enum ipacm_per_client_device_type device_type, + int lan_clnt_idx +) +{ + struct ipa_lan_client *lan_client = NULL; + int i; + struct ipa_tether_device_info *teth_ptr = NULL; + + IPAWANDBG("Delete lan client info: %d, %d, %d\n", + rmnet_ipa3_ctx->tether_device[device_type].num_clients, + lan_clnt_idx, device_type); + /* Check if Device type is valid. */ + + if (device_type >= IPACM_MAX_CLIENT_DEVICE_TYPES || + device_type < 0) { + IPAWANERR("Invalid Device type: %d\n", device_type); + return -EINVAL; + } + + /* Check if the request is to clean up all clients. */ + teth_ptr = &rmnet_ipa3_ctx->tether_device[device_type]; + + if (lan_clnt_idx == 0xffffffff) { + /* Reset the complete device info. */ + memset(teth_ptr, 0, + sizeof(struct ipa_tether_device_info)); + teth_ptr->ul_src_pipe = -1; + for (i = 0; i < IPA_MAX_NUM_HW_PATH_CLIENTS; i++) + teth_ptr->lan_client[i].client_idx = -1; + } else { + lan_client = &teth_ptr->lan_client[lan_clnt_idx]; + + /* Reset the client info before sending the message. */ + memset(lan_client, 0, sizeof(struct ipa_lan_client)); + lan_client->client_idx = -1; + /* Decrement the number of clients. */ + rmnet_ipa3_ctx->tether_device[device_type].num_clients--; + + } + return 0; +} + +/* Query must be free-d by the caller */ +static int rmnet_ipa_get_hw_fnr_stats_v2( + struct ipa_lan_client_cntr_index *client, + struct wan_ioctl_query_per_client_stats *data, + struct ipa_ioc_flt_rt_query *query) +{ + int num_counters; + + query->start_id = client->ul_cnt_idx; + query->end_id = client->dl_cnt_idx; + + query->reset = data->reset_stats; + num_counters = query->end_id - query->start_id + 1; + + if (num_counters != 2) { + IPAWANERR("Dont support more than 2 counter\n"); + return -EINVAL; + } + + IPAWANDBG(" Start/End %u/%u, num counters = %d\n", + query->start_id, query->end_id, num_counters); + + query->stats = (uint64_t)kcalloc( + num_counters, + sizeof(struct ipa_flt_rt_stats), + GFP_KERNEL); + if (!query->stats) { + IPAERR("Failed to allocate memory for query stats\n"); + return -ENOMEM; + } + + if (ipa_get_flt_rt_stats(query)) { + IPAERR("Failed to request stats from h/w\n"); + return -EINVAL; + } + + IPAWANDBG("ul: bytes = %llu, pkts = %u, pkts_hash = %u\n", + ((struct ipa_flt_rt_stats *)query->stats)[0].num_bytes, + ((struct ipa_flt_rt_stats *)query->stats)[0].num_pkts, + ((struct ipa_flt_rt_stats *)query->stats)[0].num_pkts_hash); + IPAWANDBG("dl: bytes = %llu, pkts = %u, pkts_hash = %u\n", + ((struct ipa_flt_rt_stats *)query->stats)[1].num_bytes, + ((struct ipa_flt_rt_stats *)query->stats)[1].num_pkts, + ((struct ipa_flt_rt_stats *)query->stats)[1].num_pkts_hash); + + return 0; +} + +/* rmnet_ipa3_set_lan_client_info() - + * @data - IOCTL data + * + * This function handles WAN_IOC_SET_LAN_CLIENT_INFO. + * It is used to store LAN client information which + * is used to fetch the packet stats for a client. + * + * Return codes: + * 0: Success + * -EINVAL: Invalid args provided + */ +int rmnet_ipa3_set_lan_client_info( + struct wan_ioctl_lan_client_info *data) +{ + struct ipa_lan_client *lan_client = NULL; + struct ipa_lan_client_cntr_index + *client_index = NULL; + struct ipa_tether_device_info *teth_ptr = NULL; + + + IPAWANDBG("Client MAC %02x:%02x:%02x:%02x:%02x:%02x\n", + data->mac[0], data->mac[1], data->mac[2], + data->mac[3], data->mac[4], data->mac[5]); + + /* Check if Device type is valid. */ + if (data->device_type >= IPACM_MAX_CLIENT_DEVICE_TYPES || + data->device_type < 0) { + IPAWANERR("Invalid Device type: %d\n", data->device_type); + return -EINVAL; + } + + /* Check if Client index is valid. */ + if (data->client_idx >= IPA_MAX_NUM_HW_PATH_CLIENTS || + data->client_idx < 0) { + IPAWANERR("Invalid Client Index: %d\n", data->client_idx); + return -EINVAL; + } + + /* This should be done when allocation of hw fnr counters happens */ + if (!(data->ul_cnt_idx > 0 && + data->dl_cnt_idx == (data->ul_cnt_idx + 1))) { + IPAWANERR("Invalid counter indices %u, %u\n", + data->ul_cnt_idx, data->dl_cnt_idx); + return -EINVAL; + } + + mutex_lock(&rmnet_ipa3_ctx->per_client_stats_guard); + if (data->client_init) { + /* check if the client is already inited. */ + if (rmnet_ipa3_ctx->tether_device[data->device_type] + .lan_client[data->client_idx].inited) { + IPAWANERR("Client already inited: %d:%d\n", + data->device_type, data->client_idx); + mutex_unlock(&rmnet_ipa3_ctx->per_client_stats_guard); + return -EINVAL; + } + } + + teth_ptr = &rmnet_ipa3_ctx->tether_device[data->device_type]; + lan_client = &teth_ptr->lan_client[data->client_idx]; + client_index = &teth_ptr->lan_client_indices[data->client_idx]; + + memcpy(lan_client->mac, data->mac, IPA_MAC_ADDR_SIZE); + + lan_client->client_idx = data->client_idx; + + /* Update the Source pipe. */ + rmnet_ipa3_ctx->tether_device[data->device_type].ul_src_pipe = + ipa_get_ep_mapping(data->ul_src_pipe); + + /* Update the header length if not set. */ + if (!rmnet_ipa3_ctx->tether_device[data->device_type].hdr_len) + rmnet_ipa3_ctx->tether_device[data->device_type].hdr_len = + data->hdr_len; + client_index->ul_cnt_idx = data->ul_cnt_idx; + client_index->dl_cnt_idx = data->dl_cnt_idx; + + IPAWANDBG("Device type %d, ul/dl = %d/%d\n", + data->device_type, + data->ul_cnt_idx, + data->dl_cnt_idx); + + lan_client->inited = true; + + rmnet_ipa3_ctx->tether_device[data->device_type].num_clients++; + + IPAWANDBG("Set the lan client info: %d, %d, %d\n", + lan_client->client_idx, + rmnet_ipa3_ctx->tether_device[data->device_type].ul_src_pipe, + rmnet_ipa3_ctx->tether_device[data->device_type].num_clients); + + mutex_unlock(&rmnet_ipa3_ctx->per_client_stats_guard); + + return 0; +} + +/* rmnet_ipa3_delete_lan_client_info() - + * @data - IOCTL data + * + * This function handles WAN_IOC_DELETE_LAN_CLIENT_INFO. + * It is used to delete LAN client information which + * is used to fetch the packet stats for a client. + * + * Return codes: + * 0: Success + * -EINVAL: Invalid args provided + */ +int rmnet_ipa3_clear_lan_client_info( + struct wan_ioctl_lan_client_info *data) +{ + struct ipa_lan_client *lan_client = NULL; + struct ipa_tether_device_info *teth_ptr = NULL; + + IPAWANDBG("Client MAC %02x:%02x:%02x:%02x:%02x:%02x\n", + data->mac[0], data->mac[1], data->mac[2], + data->mac[3], data->mac[4], data->mac[5]); + + /* Check if Device type is valid. */ + if (data->device_type >= IPACM_MAX_CLIENT_DEVICE_TYPES || + data->device_type < 0) { + IPAWANERR("Invalid Device type: %d\n", data->device_type); + return -EINVAL; + } + + /* Check if Client index is valid. */ + if (data->client_idx >= IPA_MAX_NUM_HW_PATH_CLIENTS || + data->client_idx < 0) { + IPAWANERR("Invalid Client Index: %d\n", data->client_idx); + return -EINVAL; + } + + IPAWANDBG("Client : %d:%d:%d\n", + data->device_type, data->client_idx, + rmnet_ipa3_ctx->tether_device[data->device_type].num_clients); + + teth_ptr = &rmnet_ipa3_ctx->tether_device[data->device_type]; + mutex_lock(&rmnet_ipa3_ctx->per_client_stats_guard); + lan_client = &teth_ptr->lan_client[data->client_idx]; + + if (!data->client_init) { + /* check if the client is already de-inited. */ + if (!lan_client->inited) { + IPAWANERR("Client already de-inited: %d:%d\n", + data->device_type, data->client_idx); + mutex_unlock(&rmnet_ipa3_ctx->per_client_stats_guard); + return -EINVAL; + } + } + + lan_client->inited = false; + mutex_unlock(&rmnet_ipa3_ctx->per_client_stats_guard); + + return 0; +} + + +/* rmnet_ipa3_send_lan_client_msg() - + * @data - IOCTL data + * + * This function handles WAN_IOC_SEND_LAN_CLIENT_MSG. + * It is used to send LAN client information to IPACM. + * + * Return codes: + * 0: Success + * -EINVAL: Invalid args provided + */ +int rmnet_ipa3_send_lan_client_msg( + struct wan_ioctl_send_lan_client_msg *data) +{ + struct ipa_msg_meta msg_meta; + int rc; + struct ipa_lan_client_msg *lan_client; + + /* Notify IPACM to reset the client index. */ + lan_client = kzalloc(sizeof(struct ipa_lan_client_msg), + GFP_KERNEL); + if (!lan_client) { + IPAWANERR("Can't allocate memory for tether_info\n"); + return -ENOMEM; + } + + if (data->client_event != IPA_PER_CLIENT_STATS_CONNECT_EVENT && + data->client_event != IPA_PER_CLIENT_STATS_DISCONNECT_EVENT) { + IPAWANERR("Wrong event given. Event:- %d\n", + data->client_event); + kfree(lan_client); + return -EINVAL; + } + data->lan_client.lanIface[IPA_RESOURCE_NAME_MAX-1] = '\0'; + memset(&msg_meta, 0, sizeof(struct ipa_msg_meta)); + memcpy(lan_client, &data->lan_client, + sizeof(struct ipa_lan_client_msg)); + msg_meta.msg_type = data->client_event; + msg_meta.msg_len = sizeof(struct ipa_lan_client_msg); + + rc = ipa_send_msg(&msg_meta, lan_client, rmnet_ipa_free_msg); + if (rc) { + IPAWANERR("ipa_send_msg failed: %d\n", rc); + kfree(lan_client); + return rc; + } + return 0; +} + +/* rmnet_ipa3_enable_per_client_stats() - + * @data - IOCTL data + * + * This function handles WAN_IOC_ENABLE_PER_CLIENT_STATS. + * It is used to indicate Q6 to start capturing per client stats. + * + * Return codes: + * 0: Success + * -EINVAL: Invalid args provided + */ +int rmnet_ipa3_enable_per_client_stats( + bool *data) +{ + struct ipa_enable_per_client_stats_req_msg_v01 *req; + struct ipa_enable_per_client_stats_resp_msg_v01 *resp; + int rc; + + req = + kzalloc(sizeof(struct ipa_enable_per_client_stats_req_msg_v01), + GFP_KERNEL); + if (!req) { + IPAWANERR("Can't allocate memory for stats message\n"); + return -ENOMEM; + } + resp = + kzalloc(sizeof(struct ipa_enable_per_client_stats_resp_msg_v01), + GFP_KERNEL); + if (!resp) { + IPAWANERR("Can't allocate memory for stats message\n"); + kfree(req); + return -ENOMEM; + } + memset(req, 0, + sizeof(struct ipa_enable_per_client_stats_req_msg_v01)); + memset(resp, 0, + sizeof(struct ipa_enable_per_client_stats_resp_msg_v01)); + + if (*data) + req->enable_per_client_stats = 1; + else + req->enable_per_client_stats = 0; + + rc = ipa3_qmi_enable_per_client_stats(req, resp); + if (rc) { + IPAWANERR("can't enable per client stats\n"); + kfree(req); + kfree(resp); + return rc; + } + + kfree(req); + kfree(resp); + return 0; +} + +int rmnet_ipa3_query_per_client_stats( + struct wan_ioctl_query_per_client_stats *data) +{ + struct ipa_get_stats_per_client_req_msg_v01 *req; + struct ipa_get_stats_per_client_resp_msg_v01 *resp; + int rc, lan_clnt_idx, lan_clnt_idx1, i; + struct ipa_lan_client *lan_client = NULL; + struct ipa_tether_device_info *teth_ptr = NULL; + + IPAWANDBG("Client MAC %02x:%02x:%02x:%02x:%02x:%02x\n", + data->client_info[0].mac[0], + data->client_info[0].mac[1], + data->client_info[0].mac[2], + data->client_info[0].mac[3], + data->client_info[0].mac[4], + data->client_info[0].mac[5]); + + /* Check if Device type is valid. */ + if (data->device_type >= IPACM_MAX_CLIENT_DEVICE_TYPES || + data->device_type < 0) { + IPAWANERR("Invalid Device type: %d\n", data->device_type); + return -EINVAL; + } + + /* Check if num_clients is valid. */ + if (data->num_clients != IPA_MAX_NUM_HW_PATH_CLIENTS && + data->num_clients != 1) { + IPAWANERR("Invalid number of clients: %d\n", data->num_clients); + return -EINVAL; + } + + mutex_lock(&rmnet_ipa3_ctx->per_client_stats_guard); + + /* Check if Source pipe is valid. */ + if (rmnet_ipa3_ctx->tether_device + [data->device_type].ul_src_pipe == -1) { + IPAWANERR_RL("Device not initialized: %d\n", data->device_type); + mutex_unlock(&rmnet_ipa3_ctx->per_client_stats_guard); + return -EINVAL; + } + + /* Check if we have clients connected. */ + if (rmnet_ipa3_ctx->tether_device[data->device_type].num_clients == 0) { + IPAWANERR("No clients connected: %d\n", data->device_type); + mutex_unlock(&rmnet_ipa3_ctx->per_client_stats_guard); + return -EINVAL; + } + + teth_ptr = &rmnet_ipa3_ctx->tether_device[data->device_type]; + if (data->num_clients == 1) { + /* Check if the client info is valid.*/ + lan_clnt_idx1 = rmnet_ipa3_get_lan_client_info( + data->device_type, + data->client_info[0].mac); + if (lan_clnt_idx1 < 0) { + IPAWANERR("Client info not available return.\n"); + mutex_unlock(&rmnet_ipa3_ctx->per_client_stats_guard); + return -EINVAL; + } + + lan_client = &teth_ptr->lan_client[lan_clnt_idx1]; + + /* + * Check if disconnect flag is set and + * see if all the clients info are cleared. + */ + if (data->disconnect_clnt && + lan_client->inited) { + IPAWANERR_RL("Client not inited. Try again.\n"); + mutex_unlock(&rmnet_ipa3_ctx->per_client_stats_guard); + return -EAGAIN; + } + + } else { + /* Max number of clients. */ + /* Check if disconnect flag is set and + * see if all the clients info are cleared. + */ + if (data->disconnect_clnt && + rmnet_ipa3_check_any_client_inited(data->device_type)) { + IPAWANERR_RL("CLient not inited. Try again.\n"); + mutex_unlock(&rmnet_ipa3_ctx->per_client_stats_guard); + return -EAGAIN; + } + lan_clnt_idx1 = 0xffffffff; + } + + req = kzalloc(sizeof(struct ipa_get_stats_per_client_req_msg_v01), + GFP_KERNEL); + if (!req) { + IPAWANERR("Can't allocate memory for stats message\n"); + mutex_unlock(&rmnet_ipa3_ctx->per_client_stats_guard); + return -ENOMEM; + } + resp = kzalloc(sizeof(struct ipa_get_stats_per_client_resp_msg_v01), + GFP_KERNEL); + if (!resp) { + IPAWANERR("Can't allocate memory for stats message\n"); + mutex_unlock(&rmnet_ipa3_ctx->per_client_stats_guard); + kfree(req); + return -ENOMEM; + } + memset(req, 0, sizeof(struct ipa_get_stats_per_client_req_msg_v01)); + memset(resp, 0, sizeof(struct ipa_get_stats_per_client_resp_msg_v01)); + + IPAWANDBG("Reset stats: %s", + data->reset_stats?"Yes":"No"); + + if (data->reset_stats) { + req->reset_stats_valid = true; + req->reset_stats = true; + IPAWANDBG("fetch and reset the client stats\n"); + } + + req->client_id = lan_clnt_idx1; + req->src_pipe_id = + rmnet_ipa3_ctx->tether_device[data->device_type].ul_src_pipe; + + IPAWANDBG("fetch the client stats for %d, %d\n", req->client_id, + req->src_pipe_id); + + rc = ipa3_qmi_get_per_client_packet_stats(req, resp); + if (rc) { + IPAWANERR("can't get per client stats\n"); + mutex_unlock(&rmnet_ipa3_ctx->per_client_stats_guard); + kfree(req); + kfree(resp); + return rc; + } + + if (resp->per_client_stats_list_valid && teth_ptr) { + for (i = 0; i < resp->per_client_stats_list_len + && i < IPA_MAX_NUM_HW_PATH_CLIENTS; i++) { + /* Subtract the header bytes from the DL bytes. */ + data->client_info[i].ipv4_rx_bytes = + (resp->per_client_stats_list[i].num_dl_ipv4_bytes) - + (teth_ptr->hdr_len * + resp->per_client_stats_list[i].num_dl_ipv4_pkts); + /* UL header bytes are subtracted by Q6. */ + data->client_info[i].ipv4_tx_bytes = + resp->per_client_stats_list[i].num_ul_ipv4_bytes; + /* Subtract the header bytes from the DL bytes. */ + data->client_info[i].ipv6_rx_bytes = + (resp->per_client_stats_list[i].num_dl_ipv6_bytes) - + (teth_ptr->hdr_len * + resp->per_client_stats_list[i].num_dl_ipv6_pkts); + /* UL header bytes are subtracted by Q6. */ + data->client_info[i].ipv6_tx_bytes = + resp->per_client_stats_list[i].num_ul_ipv6_bytes; + + IPAWANDBG("tx_b_v4(%lu)v6(%lu)rx_b_v4(%lu) v6(%lu)\n", + (unsigned long) data->client_info[i].ipv4_tx_bytes, + (unsigned long) data->client_info[i].ipv6_tx_bytes, + (unsigned long) data->client_info[i].ipv4_rx_bytes, + (unsigned long) data->client_info[i].ipv6_rx_bytes); + + /* Get the lan client index. */ + lan_clnt_idx = resp->per_client_stats_list[i].client_id; + /* Check if lan_clnt_idx is valid. */ + if (lan_clnt_idx < 0 || + lan_clnt_idx >= IPA_MAX_NUM_HW_PATH_CLIENTS) { + IPAWANERR("Lan client index not valid.\n"); + mutex_unlock( + &rmnet_ipa3_ctx->per_client_stats_guard); + kfree(req); + kfree(resp); + ipa_assert(); + return -EINVAL; + } + memcpy(data->client_info[i].mac, + teth_ptr->lan_client[lan_clnt_idx].mac, + IPA_MAC_ADDR_SIZE); + } + } + + IPAWANDBG("Disconnect clnt: %s", + data->disconnect_clnt?"Yes":"No"); + + if (data->disconnect_clnt) { + rmnet_ipa3_delete_lan_client_info(data->device_type, + lan_clnt_idx1); + } + + mutex_unlock(&rmnet_ipa3_ctx->per_client_stats_guard); + kfree(req); + kfree(resp); + return 0; +} + +/* rmnet_ipa3_get_wan_mtu() - + * @data - IOCTL data + * + * This function handles WAN_IOC_GET_WAN_MTU. + * It is used to send WAN MTU information to IPACM. + * + * Return codes: + * 0: Success + * -EINVAL: Invalid args provided + */ +int rmnet_ipa3_get_wan_mtu( + struct ipa_mtu_info *data) +{ + struct ipa3_rmnet_mux_val *mux_channel; + int rmnet_index; + + mux_channel = rmnet_ipa3_ctx->mux_channel; + + /* prevent string buffer overflows */ + data->if_name[IPA_RESOURCE_NAME_MAX-1] = '\0'; + + rmnet_index = + find_vchannel_name_index(data->if_name); + + if (rmnet_index == MAX_NUM_OF_MUX_CHANNEL) { + IPAWANERR("%s is an invalid iface name\n", + data->if_name); + return -ENODEV; + } + + IPAWANDBG("getting v4 MTU = %d\n", mux_channel[rmnet_index].mtu_v4); + data->mtu_v4 = + mux_channel[rmnet_index].mtu_v4; + + IPAWANDBG("getting v6 MTU = %d\n", mux_channel[rmnet_index].mtu_v6); + data->mtu_v6 = + mux_channel[rmnet_index].mtu_v6; + + return 0; +} +#ifdef CONFIG_DEBUG_FS +static char dbg_buff[4096]; + +static ssize_t rmnet_ipa_set_mtu(struct file *file, + const char __user *buf, size_t count, loff_t *ppos) +{ + __s8 if_name[IFNAMSIZ]; + uint16_t mtu_v4 = 0, mtu_v6 = 0; + unsigned long missing; + char *sptr, *token; + + if (count >= sizeof(dbg_buff)) + return -EFAULT; + + missing = copy_from_user(dbg_buff, buf, count); + if (missing) + return -EFAULT; + + dbg_buff[count] = '\0'; + + sptr = dbg_buff; + + memset(if_name, 0, IFNAMSIZ); + token = strsep(&sptr, " "); + if (!token) + return -EINVAL; + strlcpy(if_name, token, IFNAMSIZ); + + token = strsep(&sptr, " "); + if (!token) + return -EINVAL; + if (kstrtou16(token, 0, &mtu_v4)) + return -EINVAL; + + token = strsep(&sptr, " "); + if (!token) + return -EINVAL; + if (kstrtou16(token, 0, &mtu_v6)) + return -EINVAL; + + rmnet_ipa_send_set_mtu_notification( + if_name, + mtu_v4, + mtu_v6, IPA_IP_MAX); + + return count; +} + + +#define RMNET_IPA_WRITE_ONLY_MODE 0220 + +struct rmnet_ipa_debugfs_file { + const char *name; + umode_t mode; + void *data; + const struct file_operations fops; +}; + +static const struct rmnet_ipa_debugfs_file debugfs_files[] = { + { + "mtu", RMNET_IPA_WRITE_ONLY_MODE, NULL, { + .write = rmnet_ipa_set_mtu, + } + }, +}; + +static void rmnet_ipa_debugfs_init(void) +{ + const mode_t read_write_mode = 0664; + int i = 0; + struct dentry *file; + struct rmnet_ipa_debugfs *dbgfs = &rmnet_ipa3_ctx->dbgfs; + const size_t debugfs_files_num = + sizeof(debugfs_files) / sizeof(struct rmnet_ipa_debugfs_file); + + + dbgfs->dent = debugfs_create_dir("rmnet_ipa", 0); + if (IS_ERR(dbgfs->dent)) { + pr_err("fail to create folder in debug_fs\n"); + return; + } + + for (i = 0; i < debugfs_files_num; ++i) { + const struct rmnet_ipa_debugfs_file *curr = &debugfs_files[i]; + + file = debugfs_create_file(curr->name, curr->mode, dbgfs->dent, + curr->data, &curr->fops); + if (!file || IS_ERR(file)) { + IPAERR("fail to create file for debug_fs %s\n", + curr->name); + debugfs_remove_recursive(dbgfs->dent); + memset(dbgfs, 0, sizeof(struct rmnet_ipa_debugfs)); + return; + } + } + + debugfs_create_u32("outstanding_high", + read_write_mode, dbgfs->dent, + &rmnet_ipa3_ctx->outstanding_high); + + debugfs_create_u32("outstanding_high_ctl", + read_write_mode, dbgfs->dent, + &rmnet_ipa3_ctx->outstanding_high_ctl); + + debugfs_create_u32("outstanding_low", + read_write_mode, dbgfs->dent, + &rmnet_ipa3_ctx->outstanding_low); + + return; +} + +static void rmnet_ipa_debugfs_remove(void) +{ + if (IS_ERR(rmnet_ipa3_ctx->dbgfs.dent)) + return; + + debugfs_remove_recursive(rmnet_ipa3_ctx->dbgfs.dent); + memset(&rmnet_ipa3_ctx->dbgfs, 0, sizeof(struct rmnet_ipa_debugfs)); +} +#else /* CONFIG_DEBUG_FS */ +static void rmnet_ipa_debugfs_init(void){} +static void rmnet_ipa_debugfs_remove(void){} +#endif /* CONFIG_DEBUG_FS */ + +int ipa3_wwan_platform_driver_register(void) +{ + int rc = platform_driver_register(&rmnet_ipa_driver); + if (rc) + IPAWANERR_RL("rmnet_ipa driver register fail rc=%d\n", rc); + + /* We are here, network stack initialization is finished */ + ipa_net_initialized = true; + + return rc; +} +EXPORT_SYMBOL(ipa3_wwan_platform_driver_register); + +int rmnet_ipa3_query_per_client_stats_v2( + struct wan_ioctl_query_per_client_stats *data) +{ + int lan_clnt_idx, i, j, result = 1, stats_idx = 0; + struct ipa_lan_client *lan_client = NULL; + struct ipa_lan_client_cntr_index + *lan_client_index = NULL; + struct ipa_tether_device_info *teth_ptr = NULL; + struct ipa_ioc_flt_rt_query query_f; + struct ipa_ioc_flt_rt_query *query = &query_f; + struct ipa_flt_rt_stats *fnr_stats = NULL; + int ret = 1; + + /* Check if Device type is valid. */ + if (data->device_type >= IPACM_MAX_CLIENT_DEVICE_TYPES || + data->device_type < 0) { + IPAWANERR("Invalid Device type: %d\n", data->device_type); + return -EINVAL; + } + + /* Check if num_clients is valid. */ + if (data->num_clients != IPA_MAX_NUM_HW_PATH_CLIENTS && + data->num_clients != 1) { + IPAWANERR("Invalid number of clients: %d\n", data->num_clients); + return -EINVAL; + } + + mutex_lock(&rmnet_ipa3_ctx->per_client_stats_guard); + + /* Check if Source pipe is valid. */ + if (rmnet_ipa3_ctx->tether_device + [data->device_type].ul_src_pipe == -1) { + IPAWANERR("Device not initialized: %d\n", data->device_type); + mutex_unlock(&rmnet_ipa3_ctx->per_client_stats_guard); + return -EINVAL; + } + + /* Check if we have clients connected. */ + if (rmnet_ipa3_ctx->tether_device[data->device_type].num_clients == 0) { + IPAWANERR("No clients connected: %d\n", data->device_type); + mutex_unlock(&rmnet_ipa3_ctx->per_client_stats_guard); + return -EINVAL; + } + + if (data->num_clients == 1) { + /* Check if the client info is valid.*/ + lan_clnt_idx = rmnet_ipa3_get_lan_client_info( + data->device_type, + data->client_info[0].mac); + if (lan_clnt_idx < 0) { + IPAWANERR("Client info not available return.\n"); + mutex_unlock(&rmnet_ipa3_ctx->per_client_stats_guard); + return -EINVAL; + } + + } else { + /* Max number of clients. */ + /* Check if disconnect flag is set and + * see if all the clients info are cleared. + */ + if (data->disconnect_clnt && + rmnet_ipa3_check_any_client_inited(data->device_type)) { + IPAWANERR("CLient not inited. Try again.\n"); + mutex_unlock(&rmnet_ipa3_ctx->per_client_stats_guard); + return -EAGAIN; + } + lan_clnt_idx = LAN_STATS_FOR_ALL_CLIENTS; + } + + IPAWANDBG("Query stats for client index (0x%x)\n", + lan_clnt_idx); + + teth_ptr = &rmnet_ipa3_ctx->tether_device[data->device_type]; + lan_client = teth_ptr->lan_client; + lan_client_index = teth_ptr->lan_client_indices; + + if (lan_clnt_idx == LAN_STATS_FOR_ALL_CLIENTS) { + i = 0; + j = IPA_MAX_NUM_HW_PATH_CLIENTS; + } else { + i = lan_clnt_idx; + j = i + 1; + } + + for (; i < j; i++) { + if (!lan_client[i].inited && !data->disconnect_clnt) + continue; + + IPAWANDBG("Client MAC %02x:%02x:%02x:%02x:%02x:%02x\n", + lan_client[i].mac[0], + lan_client[i].mac[1], + lan_client[i].mac[2], + lan_client[i].mac[3], + lan_client[i].mac[4], + lan_client[i].mac[5]); + IPAWANDBG("Lan client %d inited\n", i); + IPAWANDBG("Query stats ul/dl indices = %u/%u\n", + lan_client_index[i].ul_cnt_idx, + lan_client_index[i].dl_cnt_idx); + memset(query, 0, sizeof(query_f)); + result = rmnet_ipa_get_hw_fnr_stats_v2(&lan_client_index[i], + data, query); + if (result) { + IPAWANERR("Failed: Client type %d, idx %d\n", + data->device_type, i); + kfree((void *)query->stats); + continue; + } + fnr_stats = &((struct ipa_flt_rt_stats *) + query->stats)[0]; + if (data->num_clients == 1) + stats_idx = 0; + else + stats_idx = i; + data->client_info[stats_idx].ipv4_tx_bytes = + fnr_stats->num_bytes; + fnr_stats = &((struct ipa_flt_rt_stats *) + query->stats)[1]; + data->client_info[stats_idx].ipv4_rx_bytes = + fnr_stats->num_bytes; + memcpy(data->client_info[stats_idx].mac, + lan_client[i].mac, + IPA_MAC_ADDR_SIZE); + + IPAWANDBG("Client ipv4_tx_bytes = %llu, ipv4_rx_bytes = %llu\n", + data->client_info[stats_idx].ipv4_tx_bytes, + data->client_info[stats_idx].ipv4_rx_bytes); + + kfree((void *)query->stats); + ret = result; + } + + /* Legacy per-client stats */ + IPAWANDBG("Disconnect clnt: %s", + data->disconnect_clnt?"Yes":"No"); + + if (data->disconnect_clnt) { + rmnet_ipa3_delete_lan_client_info(data->device_type, + lan_clnt_idx); + } + + mutex_unlock(&rmnet_ipa3_ctx->per_client_stats_guard); + return ret; +} + +int ipa3_wwan_init(void) +{ + int i, j; + struct ipa_tether_device_info *teth_ptr = NULL; + void *ssr_hdl; + int rc = 0; + + if (!ipa3_ctx) { + IPAWANERR_RL("ipa3_ctx was not initialized\n"); + return -EINVAL; + } + rmnet_ipa3_ctx = kzalloc(sizeof(*rmnet_ipa3_ctx), GFP_KERNEL); + + if (!rmnet_ipa3_ctx) + return -ENOMEM; + + atomic_set(&rmnet_ipa3_ctx->is_initialized, 0); + atomic_set(&rmnet_ipa3_ctx->is_ssr, 0); + rmnet_ipa3_ctx->clock_vote.cnt = 0; + + mutex_init(&rmnet_ipa3_ctx->pipe_handle_guard); + mutex_init(&rmnet_ipa3_ctx->add_mux_channel_lock); + mutex_init(&rmnet_ipa3_ctx->per_client_stats_guard); + mutex_init(&rmnet_ipa3_ctx->clock_vote.mutex); + /* Reset the Lan Stats. */ + for (i = 0; i < IPACM_MAX_CLIENT_DEVICE_TYPES; i++) { + teth_ptr = &rmnet_ipa3_ctx->tether_device[i]; + teth_ptr->ul_src_pipe = -1; + + for (j = 0; j < IPA_MAX_NUM_HW_PATH_CLIENTS; j++) + teth_ptr->lan_client[j].client_idx = -1; + } + rmnet_ipa3_ctx->ipa3_to_apps_hdl = -1; + rmnet_ipa3_ctx->apps_to_ipa3_hdl = -1; + + ipa3_qmi_init(); + + rmnet_ipa3_ctx->outstanding_high = OUTSTANDING_HIGH_DEFAULT; + rmnet_ipa3_ctx->outstanding_high_ctl = OUTSTANDING_HIGH_CTL_DEFAULT; + rmnet_ipa3_ctx->outstanding_low = OUTSTANDING_LOW_DEFAULT; + + rmnet_ipa_debugfs_init(); + + /* Register for Local Modem SSR */ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 14, 0)) + ssr_hdl = qcom_register_ssr_notifier(SUBSYS_LOCAL_MODEM, + &ipa3_lcl_mdm_ssr_notifier); +#else + ssr_hdl = subsys_notif_register_notifier(SUBSYS_LOCAL_MODEM, + &ipa3_lcl_mdm_ssr_notifier); +#endif + if (!IS_ERR(ssr_hdl)) + rmnet_ipa3_ctx->lcl_mdm_subsys_notify_handle = ssr_hdl; + else if (!rmnet_ipa3_ctx->ipa_config_is_apq) { + rc = PTR_ERR(ssr_hdl); + IPAWANERR_RL("local modem ssr register fail rc=%d\n", rc); + goto fail_dbgfs_rm; + } + + if (rmnet_ipa3_ctx->ipa_config_is_apq) { + /* Register for Remote Modem SSR */ + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 14, 0)) + ssr_hdl = qcom_register_ssr_notifier(SUBSYS_REMOTE_MODEM, + &ipa3_rmt_mdm_ssr_notifier); + #else + ssr_hdl = subsys_notif_register_notifier(SUBSYS_REMOTE_MODEM, + &ipa3_rmt_mdm_ssr_notifier); + #endif + if (IS_ERR(ssr_hdl)) { + rc = PTR_ERR(ssr_hdl); + IPAWANERR_RL("remote modem ssr register fail rc=%d\n", + rc); + goto fail_unreg_lcl_mdm_ssr; + } + rmnet_ipa3_ctx->rmt_mdm_subsys_notify_handle = ssr_hdl; + } + + /* The platform driver register is done later in the ipa_late_init */ + + return 0; + +fail_unreg_lcl_mdm_ssr: + if (rmnet_ipa3_ctx->lcl_mdm_subsys_notify_handle) { +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 14, 0)) + qcom_unregister_ssr_notifier( + rmnet_ipa3_ctx->lcl_mdm_subsys_notify_handle, + &ipa3_lcl_mdm_ssr_notifier); +#else + subsys_notif_unregister_notifier( + rmnet_ipa3_ctx->lcl_mdm_subsys_notify_handle, + &ipa3_lcl_mdm_ssr_notifier); +#endif + rmnet_ipa3_ctx->lcl_mdm_subsys_notify_handle = NULL; + } +fail_dbgfs_rm: + rmnet_ipa_debugfs_remove(); + return rc; +} + +void ipa3_wwan_cleanup(void) +{ + int ret; + + platform_driver_unregister(&rmnet_ipa_driver); + if (rmnet_ipa3_ctx->lcl_mdm_subsys_notify_handle) { +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 14, 0)) + ret = qcom_unregister_ssr_notifier( + rmnet_ipa3_ctx->lcl_mdm_subsys_notify_handle, + &ipa3_lcl_mdm_ssr_notifier); +#else + ret = subsys_notif_unregister_notifier( + rmnet_ipa3_ctx->lcl_mdm_subsys_notify_handle, + &ipa3_lcl_mdm_ssr_notifier); +#endif + if (ret) + IPAWANERR( + "Failed to unregister subsys %s notifier ret=%d\n", + SUBSYS_LOCAL_MODEM, ret); + } + if (rmnet_ipa3_ctx->rmt_mdm_subsys_notify_handle) { +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 14, 0)) + ret = qcom_unregister_ssr_notifier( + rmnet_ipa3_ctx->rmt_mdm_subsys_notify_handle, + &ipa3_rmt_mdm_ssr_notifier); +#else + ret = subsys_notif_unregister_notifier( + rmnet_ipa3_ctx->rmt_mdm_subsys_notify_handle, + &ipa3_rmt_mdm_ssr_notifier); +#endif + if (ret) + IPAWANERR( + "Failed to unregister subsys %s notifier ret=%d\n", + SUBSYS_REMOTE_MODEM, ret); + } + rmnet_ipa_debugfs_remove(); + ipa3_qmi_cleanup(); + mutex_destroy(&rmnet_ipa3_ctx->per_client_stats_guard); + mutex_destroy(&rmnet_ipa3_ctx->add_mux_channel_lock); + mutex_destroy(&rmnet_ipa3_ctx->pipe_handle_guard); + kfree(rmnet_ipa3_ctx); + rmnet_ipa3_ctx = NULL; +} +EXPORT_SYMBOL(ipa3_wwan_cleanup); + +static void ipa3_wwan_msg_free_cb(void *buff, u32 len, u32 type) +{ + kfree(buff); +} + +static int ipa3_rmnet_poll(struct napi_struct *napi, int budget) +{ + int rcvd_pkts = 0; + + rcvd_pkts = ipa3_rx_poll(rmnet_ipa3_ctx->ipa3_to_apps_hdl, + NAPI_WEIGHT); + IPAWANDBG_LOW("rcvd packets: %d\n", rcvd_pkts); + return rcvd_pkts; +} diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa_fd_ioctl.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa_fd_ioctl.c new file mode 100644 index 0000000000..617cb82651 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa_fd_ioctl.c @@ -0,0 +1,672 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2013-2021, The Linux Foundation. All rights reserved. + * + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ipa_qmi_service.h" +#include "ipa_i.h" + +#define DRIVER_NAME "wwan_ioctl" + +#ifdef CONFIG_COMPAT +#define WAN_IOC_ADD_FLT_RULE32 _IOWR(WAN_IOC_MAGIC, \ + WAN_IOCTL_ADD_FLT_RULE, \ + compat_uptr_t) +#define WAN_IOC_ADD_FLT_RULE_INDEX32 _IOWR(WAN_IOC_MAGIC, \ + WAN_IOCTL_ADD_FLT_INDEX, \ + compat_uptr_t) +#define WAN_IOC_POLL_TETHERING_STATS32 _IOWR(WAN_IOC_MAGIC, \ + WAN_IOCTL_POLL_TETHERING_STATS, \ + compat_uptr_t) +#define WAN_IOC_SET_DATA_QUOTA32 _IOWR(WAN_IOC_MAGIC, \ + WAN_IOCTL_SET_DATA_QUOTA, \ + compat_uptr_t) +#define WAN_IOC_SET_TETHER_CLIENT_PIPE32 _IOWR(WAN_IOC_MAGIC, \ + WAN_IOCTL_SET_TETHER_CLIENT_PIPE, \ + compat_uptr_t) +#define WAN_IOC_QUERY_TETHER_STATS32 _IOWR(WAN_IOC_MAGIC, \ + WAN_IOCTL_QUERY_TETHER_STATS, \ + compat_uptr_t) +#define WAN_IOC_RESET_TETHER_STATS32 _IOWR(WAN_IOC_MAGIC, \ + WAN_IOCTL_RESET_TETHER_STATS, \ + compat_uptr_t) +#define WAN_IOC_QUERY_DL_FILTER_STATS32 _IOWR(WAN_IOC_MAGIC, \ + WAN_IOCTL_QUERY_DL_FILTER_STATS, \ + compat_uptr_t) +#define WAN_IOC_QUERY_TETHER_STATS_ALL32 _IOWR(WAN_IOC_MAGIC, \ + WAN_IOCTL_QUERY_TETHER_STATS_ALL, \ + compat_uptr_t) +#define WAN_IOC_NOTIFY_WAN_STATE32 _IOWR(WAN_IOC_MAGIC, \ + WAN_IOCTL_NOTIFY_WAN_STATE, \ + compat_uptr_t) +#define WAN_IOCTL_ENABLE_PER_CLIENT_STATS32 _IOWR(WAN_IOC_MAGIC, \ + WAN_IOCTL_ENABLE_PER_CLIENT_STATS, \ + compat_uptr_t) +#define WAN_IOCTL_QUERY_PER_CLIENT_STATS32 _IOWR(WAN_IOC_MAGIC, \ + WAN_IOCTL_QUERY_PER_CLIENT_STATS, \ + compat_uptr_t) +#define WAN_IOCTL_SET_LAN_CLIENT_INFO32 _IOWR(WAN_IOC_MAGIC, \ + WAN_IOCTL_SET_LAN_CLIENT_INFO, \ + compat_uptr_t) +#endif + +static unsigned int dev_num = 1; +static struct cdev ipa3_wan_ioctl_cdev; +static unsigned int ipa3_process_ioctl = 1; +static struct class *class; +static dev_t device; + +static long ipa3_wan_ioctl(struct file *filp, + unsigned int cmd, + unsigned long arg) +{ + int retval = 0, rc = 0, rmv_offload_req__msg_size = 0; + u32 pyld_sz; + u8 *param = NULL; + + IPAWANDBG("device %s got ioctl events :>>>\n", + DRIVER_NAME); + + rmv_offload_req__msg_size = + sizeof(struct ipa_remove_offload_connection_req_msg_v01); + if (!ipa3_process_ioctl) { + + if ((cmd == WAN_IOC_SET_LAN_CLIENT_INFO) || + (cmd == WAN_IOC_CLEAR_LAN_CLIENT_INFO)) { + IPAWANDBG("Modem is in SSR\n"); + IPAWANDBG("Still allow IOCTL for exceptions (%d)\n", + cmd); + } else { + IPAWANERR_RL("Modem is in SSR, ignoring ioctl (%d)\n", + cmd); + return -EAGAIN; + } + } + + switch (cmd) { + case WAN_IOC_ADD_FLT_RULE_EX: + IPAWANDBG("device %s got WAN_IOC_ADD_FLT_RULE_EX :>>>\n", + DRIVER_NAME); + pyld_sz = sizeof(struct ipa_install_fltr_rule_req_ex_msg_v01); + param = vmemdup_user((const void __user *)arg, pyld_sz); + + if (IS_ERR(param)) { + retval = PTR_ERR(param); + break; + } + if (ipa3_qmi_filter_request_ex_send( + (struct ipa_install_fltr_rule_req_ex_msg_v01 *)param)) { + IPAWANDBG("IPACM->Q6 add filter rule failed\n"); + retval = -EFAULT; + break; + } + if (copy_to_user((u8 *)arg, param, pyld_sz)) { + retval = -EFAULT; + break; + } + break; + + case WAN_IOC_ADD_OFFLOAD_CONNECTION: + IPAWANDBG("device %s got WAN_IOC_ADD_OFFLOAD_CONNECTION :>>>\n", + DRIVER_NAME); + pyld_sz = sizeof(struct ipa_add_offload_connection_req_msg_v01); + param = vmemdup_user((const void __user *)arg, pyld_sz); + + if (IS_ERR(param)) { + retval = PTR_ERR(param); + break; + } + if (ipa3_qmi_add_offload_request_send( + (struct ipa_add_offload_connection_req_msg_v01 *) + param)) { + IPAWANDBG("IPACM->Q6 add offload connection failed\n"); + retval = -EFAULT; + break; + } + if (copy_to_user((void __user *)arg, param, pyld_sz)) { + retval = -EFAULT; + break; + } + break; + + case WAN_IOC_RMV_OFFLOAD_CONNECTION: + IPAWANDBG("device %s got WAN_IOC_RMV_OFFLOAD_CONNECTION :>>>\n", + DRIVER_NAME); + pyld_sz = rmv_offload_req__msg_size; + param = vmemdup_user((const void __user *)arg, pyld_sz); + + if (IS_ERR(param)) { + retval = PTR_ERR(param); + break; + } + if (ipa3_qmi_rmv_offload_request_send( + (struct ipa_remove_offload_connection_req_msg_v01 *) + param)) { + IPAWANDBG("IPACM->Q6 add offload connection failed\n"); + retval = -EFAULT; + break; + } + if (copy_to_user((void __user *)arg, param, pyld_sz)) { + retval = -EFAULT; + break; + } + break; + + case WAN_IOC_ADD_UL_FLT_RULE: + IPAWANDBG("device %s got WAN_IOC_UL_ADD_FLT_RULE :>>>\n", + DRIVER_NAME); + pyld_sz = + sizeof(struct ipa_configure_ul_firewall_rules_req_msg_v01); + param = vmemdup_user((const void __user *)arg, pyld_sz); + + if (IS_ERR(param)) { + retval = PTR_ERR(param); + break; + } + if (ipa3_qmi_ul_filter_request_send( + (struct ipa_configure_ul_firewall_rules_req_msg_v01 *) + param)) { + IPAWANDBG("IPACM->Q6 add ul filter rule failed\n"); + retval = -EFAULT; + break; + } + if (copy_to_user((void __user *)arg, param, pyld_sz)) { + retval = -EFAULT; + break; + } + break; + + case WAN_IOC_ADD_FLT_RULE_INDEX: + IPAWANDBG("device %s got WAN_IOC_ADD_FLT_RULE_INDEX :>>>\n", + DRIVER_NAME); + pyld_sz = sizeof(struct ipa_fltr_installed_notif_req_msg_v01); + param = vmemdup_user((const void __user *)arg, pyld_sz); + + if (IS_ERR(param)) { + retval = PTR_ERR(param); + break; + } + if (ipa3_qmi_filter_notify_send( + (struct ipa_fltr_installed_notif_req_msg_v01 *)param)) { + IPAWANDBG("IPACM->Q6 rule index fail\n"); + retval = -EFAULT; + break; + } + if (copy_to_user((u8 *)arg, param, pyld_sz)) { + retval = -EFAULT; + break; + } + break; + + case WAN_IOC_VOTE_FOR_BW_MBPS: + IPAWANDBG("device %s got WAN_IOC_VOTE_FOR_BW_MBPS :>>>\n", + DRIVER_NAME); + pyld_sz = sizeof(uint32_t); + param = vmemdup_user((const void __user *)arg, pyld_sz); + + if (IS_ERR(param)) { + retval = PTR_ERR(param); + break; + } + if (ipa3_vote_for_bus_bw((uint32_t *)param)) { + IPAWANERR("Failed to vote for bus BW\n"); + retval = -EFAULT; + break; + } + if (copy_to_user((u8 *)arg, param, pyld_sz)) { + retval = -EFAULT; + break; + } + break; + + case WAN_IOC_POLL_TETHERING_STATS: + IPAWANDBG_LOW("got WAN_IOCTL_POLL_TETHERING_STATS :>>>\n"); + pyld_sz = sizeof(struct wan_ioctl_poll_tethering_stats); + param = vmemdup_user((const void __user *)arg, pyld_sz); + + if (IS_ERR(param)) { + retval = PTR_ERR(param); + break; + } + if (rmnet_ipa3_poll_tethering_stats( + (struct wan_ioctl_poll_tethering_stats *)param)) { + IPAWANERR_RL("WAN_IOCTL_POLL_TETHERING_STATS failed\n"); + retval = -EFAULT; + break; + } + if (copy_to_user((u8 *)arg, param, pyld_sz)) { + retval = -EFAULT; + break; + } + break; + + case WAN_IOC_SET_DATA_QUOTA: + IPAWANDBG_LOW("device %s got WAN_IOCTL_SET_DATA_QUOTA :>>>\n", + DRIVER_NAME); + pyld_sz = sizeof(struct wan_ioctl_set_data_quota); + param = vmemdup_user((const void __user *)arg, pyld_sz); + + if (IS_ERR(param)) { + retval = PTR_ERR(param); + break; + } + rc = rmnet_ipa3_set_data_quota( + (struct wan_ioctl_set_data_quota *)param); + if (rc != 0) { + IPAWANERR("WAN_IOC_SET_DATA_QUOTA failed\n"); + if (rc == -ENODEV) + retval = -ENODEV; + else + retval = -EFAULT; + break; + } + if (copy_to_user((u8 *)arg, param, pyld_sz)) { + retval = -EFAULT; + break; + } + break; + +#ifdef IPA_DATA_WARNING_QUOTA + case WAN_IOC_SET_DATA_QUOTA_WARNING: + IPAWANDBG_LOW("device %s got WAN_IOC_SET_DATA_QUOTA_WARNING :>>>\n", + DRIVER_NAME); + pyld_sz = sizeof(struct wan_ioctl_set_data_quota_warning); + if (pyld_sz > _IOC_SIZE(cmd)) { + IPAWANERR("SET_DATA_QUOTA_WARNING failed, invalid params\n"); + retval = -EINVAL; + break; + } + param = memdup_user((const void __user *)arg, pyld_sz); + if (IS_ERR(param)) { + retval = PTR_ERR(param); + break; + } + rc = rmnet_ipa3_set_data_quota_warning( + (struct wan_ioctl_set_data_quota_warning *)param); + if (rc != 0) { + IPAWANERR("SET_DATA_QUOTA_WARNING failed\n"); + if (rc == -ENODEV) + retval = -ENODEV; + else + retval = -EFAULT; + break; + } + if (copy_to_user((u8 *)arg, param, pyld_sz)) { + retval = -EFAULT; + break; + } + break; +#endif + + case WAN_IOC_SET_TETHER_CLIENT_PIPE: + IPAWANDBG_LOW("got WAN_IOC_SET_TETHER_CLIENT_PIPE :>>>\n"); + pyld_sz = sizeof(struct wan_ioctl_set_tether_client_pipe); + param = vmemdup_user((const void __user *)arg, pyld_sz); + + if (IS_ERR(param)) { + retval = PTR_ERR(param); + break; + } + if (rmnet_ipa3_set_tether_client_pipe( + (struct wan_ioctl_set_tether_client_pipe *)param)) { + IPAWANERR("WAN_IOC_SET_TETHER_CLIENT_PIPE failed\n"); + retval = -EFAULT; + break; + } + break; + + case WAN_IOC_QUERY_TETHER_STATS: + IPAWANDBG_LOW("got WAN_IOC_QUERY_TETHER_STATS :>>>\n"); + pyld_sz = sizeof(struct wan_ioctl_query_tether_stats); + param = vmemdup_user((const void __user *)arg, pyld_sz); + + if (IS_ERR(param)) { + retval = PTR_ERR(param); + break; + } + + if (rmnet_ipa3_query_tethering_stats( + (struct wan_ioctl_query_tether_stats *)param, false)) { + IPAWANERR("WAN_IOC_QUERY_TETHER_STATS failed\n"); + retval = -EFAULT; + break; + } + + if (copy_to_user((u8 *)arg, param, pyld_sz)) { + retval = -EFAULT; + break; + } + break; + + case WAN_IOC_QUERY_TETHER_STATS_ALL: + IPAWANDBG_LOW("got WAN_IOC_QUERY_TETHER_STATS_ALL :>>>\n"); + pyld_sz = sizeof(struct wan_ioctl_query_tether_stats_all); + param = vmemdup_user((const void __user *)arg, pyld_sz); + + if (IS_ERR(param)) { + retval = PTR_ERR(param); + break; + } + + if (rmnet_ipa3_query_tethering_stats_all( + (struct wan_ioctl_query_tether_stats_all *)param)) { + IPAWANERR("WAN_IOC_QUERY_TETHER_STATS failed\n"); + retval = -EFAULT; + break; + } + + if (copy_to_user((void __user *)arg, param, pyld_sz)) { + retval = -EFAULT; + break; + } + break; + + case WAN_IOC_RESET_TETHER_STATS: + IPAWANDBG_LOW("device %s got WAN_IOC_RESET_TETHER_STATS :>>>\n", + DRIVER_NAME); + pyld_sz = sizeof(struct wan_ioctl_reset_tether_stats); + param = vmemdup_user((const void __user *)arg, pyld_sz); + + if (IS_ERR(param)) { + retval = PTR_ERR(param); + break; + } + + if (rmnet_ipa3_reset_tethering_stats( + (struct wan_ioctl_reset_tether_stats *)param)) { + IPAWANERR("WAN_IOC_RESET_TETHER_STATS failed\n"); + retval = -EFAULT; + break; + } + break; + + case WAN_IOC_NOTIFY_WAN_STATE: + IPAWANDBG_LOW("device %s got WAN_IOC_NOTIFY_WAN_STATE :>>>\n", + DRIVER_NAME); + pyld_sz = sizeof(struct wan_ioctl_notify_wan_state); + param = vmemdup_user((const void __user *)arg, pyld_sz); + + if (IS_ERR(param)) { + retval = PTR_ERR(param); + break; + } + + if (ipa3_wwan_set_modem_state( + (struct wan_ioctl_notify_wan_state *)param)) { + IPAWANERR("WAN_IOC_NOTIFY_WAN_STATE failed\n"); + retval = -EFAULT; + break; + } + + if (ipa_mpm_notify_wan_state( + (struct wan_ioctl_notify_wan_state *)param)) { + IPAWANERR("WAN_IOC_NOTIFY_WAN_STATE failed\n"); + retval = -EPERM; + } + break; + case WAN_IOC_ENABLE_PER_CLIENT_STATS: + IPAWANDBG_LOW("got WAN_IOC_ENABLE_PER_CLIENT_STATS :>>>\n"); + pyld_sz = sizeof(bool); + param = vmemdup_user((const void __user *)arg, pyld_sz); + + if (IS_ERR(param)) { + retval = PTR_ERR(param); + break; + } + if (rmnet_ipa3_enable_per_client_stats( + (bool *)param)) { + IPAWANERR("WAN_IOC_ENABLE_PER_CLIENT_STATS failed\n"); + retval = -EFAULT; + break; + } + break; + case WAN_IOC_QUERY_PER_CLIENT_STATS: + IPAWANDBG_LOW("got WAN_IOC_QUERY_PER_CLIENT_STATS :>>>\n"); + pyld_sz = sizeof(struct wan_ioctl_query_per_client_stats); + param = vmemdup_user((const void __user *)arg, pyld_sz); + + if (IS_ERR(param)) { + retval = PTR_ERR(param); + break; + } + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_5) + retval = rmnet_ipa3_query_per_client_stats_v2( + (struct wan_ioctl_query_per_client_stats *)param); + else + retval = rmnet_ipa3_query_per_client_stats( + (struct wan_ioctl_query_per_client_stats *)param); + if (retval) { + IPAWANERR("WAN_IOC_QUERY_PER_CLIENT_STATS failed\n"); + break; + } + + if (copy_to_user((void __user *)arg, param, pyld_sz)) { + retval = -EFAULT; + break; + } + break; + + case WAN_IOC_SET_LAN_CLIENT_INFO: + IPAWANDBG_LOW("got WAN_IOC_SET_LAN_CLIENT_INFO :>>>\n"); + pyld_sz = sizeof(struct wan_ioctl_lan_client_info); + param = vmemdup_user((const void __user *)arg, pyld_sz); + + if (IS_ERR(param)) { + retval = PTR_ERR(param); + break; + } + if (rmnet_ipa3_set_lan_client_info( + (struct wan_ioctl_lan_client_info *)param)) { + IPAWANERR("WAN_IOC_SET_LAN_CLIENT_INFO failed\n"); + retval = -EFAULT; + break; + } + break; + + case WAN_IOC_CLEAR_LAN_CLIENT_INFO: + IPAWANDBG_LOW("got WAN_IOC_CLEAR_LAN_CLIENT_INFO :>>>\n"); + pyld_sz = sizeof(struct wan_ioctl_lan_client_info); + param = vmemdup_user((const void __user *)arg, pyld_sz); + + if (IS_ERR(param)) { + retval = PTR_ERR(param); + break; + } + if (rmnet_ipa3_clear_lan_client_info( + (struct wan_ioctl_lan_client_info *)param)) { + IPAWANERR("WAN_IOC_CLEAR_LAN_CLIENT_INFO failed\n"); + retval = -EFAULT; + break; + } + break; + + + case WAN_IOC_SEND_LAN_CLIENT_MSG: + IPAWANDBG_LOW("got WAN_IOC_SEND_LAN_CLIENT_MSG :>>>\n"); + pyld_sz = sizeof(struct wan_ioctl_send_lan_client_msg); + param = vmemdup_user((const void __user *)arg, pyld_sz); + + if (IS_ERR(param)) { + retval = PTR_ERR(param); + break; + } + if (rmnet_ipa3_send_lan_client_msg( + (struct wan_ioctl_send_lan_client_msg *) + param)) { + IPAWANERR("IOC_SEND_LAN_CLIENT_MSG failed\n"); + retval = -EFAULT; + break; + } + break; + case WAN_IOC_NOTIFY_NAT_MOVE_RES: + IPAWANDBG_LOW("got WAN_IOC_NOTIFY_NAT_MOVE_RES :>>>\n"); + if (rmnet_ipa3_notify_nat_move_res(arg)) { + IPAWANERR("WAN_IOC_NOTIFY_NAT_MOVE_RES failed\n"); + retval = -EFAULT; + break; + } + break; + + case WAN_IOC_GET_WAN_MTU: + IPAWANDBG_LOW("got WAN_IOC_GET_WAN_MTU :>>>\n"); + pyld_sz = sizeof(struct ipa_mtu_info); + param = memdup_user((const void __user *)arg, pyld_sz); + if (IS_ERR(param)) { + retval = PTR_ERR(param); + break; + } + if (rmnet_ipa3_get_wan_mtu( + (struct ipa_mtu_info *) + param)) { + IPAWANERR("WAN_IOC_GET_WAN_MTU failed\n"); + retval = -EFAULT; + break; + } + + if (copy_to_user((void __user *)arg, param, pyld_sz)) { + retval = -EFAULT; + break; + } + break; + + default: + retval = -ENOTTY; + } + if (!IS_ERR(param)) + kvfree(param); + + return retval; +} + +#ifdef CONFIG_COMPAT +long ipa3_compat_wan_ioctl(struct file *file, + unsigned int cmd, + unsigned long arg) +{ + switch (cmd) { + case WAN_IOC_ADD_FLT_RULE32: + cmd = WAN_IOC_ADD_FLT_RULE; + break; + case WAN_IOC_ADD_FLT_RULE_INDEX32: + cmd = WAN_IOC_ADD_FLT_RULE_INDEX; + break; + case WAN_IOC_POLL_TETHERING_STATS32: + cmd = WAN_IOC_POLL_TETHERING_STATS; + break; + case WAN_IOC_SET_DATA_QUOTA32: + cmd = WAN_IOC_SET_DATA_QUOTA; + break; + case WAN_IOC_SET_TETHER_CLIENT_PIPE32: + cmd = WAN_IOC_SET_TETHER_CLIENT_PIPE; + break; + case WAN_IOC_QUERY_TETHER_STATS32: + cmd = WAN_IOC_QUERY_TETHER_STATS; + break; + case WAN_IOC_RESET_TETHER_STATS32: + cmd = WAN_IOC_RESET_TETHER_STATS; + break; + case WAN_IOC_QUERY_DL_FILTER_STATS32: + cmd = WAN_IOC_QUERY_DL_FILTER_STATS; + break; + default: + return -ENOIOCTLCMD; + } + return ipa3_wan_ioctl(file, cmd, (unsigned long) compat_ptr(arg)); +} +#endif + +static int ipa3_wan_ioctl_open(struct inode *inode, struct file *filp) +{ + IPAWANDBG("\n IPA A7 ipa3_wan_ioctl open OK :>>>> "); + return 0; +} + +static const struct file_operations rmnet_ipa3_fops = { + .owner = THIS_MODULE, + .open = ipa3_wan_ioctl_open, + .read = NULL, + .unlocked_ioctl = ipa3_wan_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl = ipa3_compat_wan_ioctl, +#endif +}; + +int ipa3_wan_ioctl_init(void) +{ + unsigned int wan_ioctl_major = 0; + int ret; + struct device *dev; + + device = MKDEV(wan_ioctl_major, 0); + + ret = alloc_chrdev_region(&device, 0, dev_num, DRIVER_NAME); + if (ret) { + IPAWANERR(":device_alloc err.\n"); + goto dev_alloc_err; + } + wan_ioctl_major = MAJOR(device); + + class = class_create(THIS_MODULE, DRIVER_NAME); + if (IS_ERR(class)) { + IPAWANERR(":class_create err.\n"); + goto class_err; + } + + dev = device_create(class, NULL, device, + NULL, DRIVER_NAME); + if (IS_ERR(dev)) { + IPAWANERR(":device_create err.\n"); + goto device_err; + } + + cdev_init(&ipa3_wan_ioctl_cdev, &rmnet_ipa3_fops); + ret = cdev_add(&ipa3_wan_ioctl_cdev, device, dev_num); + if (ret) { + IPAWANERR(":cdev_add err.\n"); + goto cdev_add_err; + } + + ipa3_process_ioctl = 1; + + IPAWANDBG("IPA %s major(%d) initial ok :>>>>\n", + DRIVER_NAME, wan_ioctl_major); + return 0; + +cdev_add_err: + device_destroy(class, device); +device_err: + class_destroy(class); +class_err: + unregister_chrdev_region(device, dev_num); +dev_alloc_err: + return -ENODEV; +} + +void ipa3_wan_ioctl_stop_qmi_messages(void) +{ + ipa3_process_ioctl = 0; +} + +void ipa3_wan_ioctl_enable_qmi_messages(void) +{ + ipa3_process_ioctl = 1; +} + +void ipa3_wan_ioctl_deinit(void) +{ + cdev_del(&ipa3_wan_ioctl_cdev); + device_destroy(class, device); + class_destroy(class); + unregister_chrdev_region(device, dev_num); +} diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/rmnet_ll_ipa.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/rmnet_ll_ipa.c new file mode 100644 index 0000000000..2aa5cad4e7 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/rmnet_ll_ipa.c @@ -0,0 +1,976 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include "ipa.h" +#include +#include "ipa_i.h" + +enum ipa_rmnet_ll_state { + IPA_RMNET_LL_NOT_REG, + IPA_RMNET_LL_REGD, /* rmnet_ll register */ + IPA_RMNET_LL_PIPE_READY, /* sys pipe setup */ + IPA_RMNET_LL_START, /* rmnet_ll register + pipe setup */ +}; + +#define IPA_RMNET_LL_PIPE_NOT_READY (0) +#define IPA_RMNET_LL_PIPE_TX_READY (1 << 0) +#define IPA_RMNET_LL_PIPE_RX_READY (1 << 1) +#define IPA_RMNET_LL_PIPE_READY_ALL (IPA_RMNET_LL_PIPE_TX_READY | \ + IPA_RMNET_LL_PIPE_RX_READY) /* TX Ready + RX ready */ + + +#define IPA_WWAN_CONS_DESC_FIFO_SZ 256 +/* Allow max -2 packets, to account for any frags. */ +#define RMNET_LL_QUEUE_MAX ((2 * IPA_WWAN_CONS_DESC_FIFO_SZ) - 2) + +#define IPA_RMNET_LL_RECEIVE 1 +#define IPA_RMNET_LL_FLOW_EVT 2 + +#define IPA_RMNET_LL_FREE_CREDIT_THRSHLD 64 +#define IPA_RMNET_LL_FREE_CREDIT_THRSHLD_MAX 128 + +struct ipa3_rmnet_ll_cb_info { + ipa_rmnet_ll_ready_cb ready_cb; + ipa_rmnet_ll_stop_cb stop_cb; + ipa_rmnet_ll_rx_notify_cb rx_notify_cb; + void *ready_cb_user_data; + void *stop_cb_user_data; + void *rx_notify_cb_user_data; +}; + +struct ipa3_rmnet_ll_stats { + atomic_t outstanding_pkts; + u32 tx_pkt_sent; + u32 rx_pkt_rcvd; + u64 tx_byte_sent; + u64 rx_byte_rcvd; + u32 tx_pkt_dropped; + u32 rx_pkt_dropped; + u64 tx_byte_dropped; + u64 rx_byte_dropped; +}; + +struct rmnet_ll_ipa3_debugfs_file { + const char *name; + umode_t mode; + void *data; + const struct file_operations fops; +}; + +struct rmnet_ll_ipa3_debugfs { + struct dentry *dent; +}; + +struct rmnet_ll_ipa3_context { + struct ipa3_rmnet_ll_stats stats; + enum ipa_rmnet_ll_state state; + u8 pipe_state; + struct ipa_sys_connect_params apps_to_ipa_low_lat_data_ep_cfg; + struct ipa_sys_connect_params ipa_to_apps_low_lat_data_ep_cfg; + u32 apps_to_ipa3_low_lat_data_hdl; + u32 ipa3_to_apps_low_lat_data_hdl; + spinlock_t tx_lock; + struct ipa3_rmnet_ll_cb_info cb_info; + atomic_t under_flow_controlled_state; + u32 free_credit_thrshld; + struct sk_buff_head tx_queue; + u32 rmnet_ll_pm_hdl; + struct rmnet_ll_ipa3_debugfs dbgfs; + struct mutex lock; + struct workqueue_struct *wq; +}; + +static struct rmnet_ll_ipa3_context *rmnet_ll_ipa3_ctx; + +static void rmnet_ll_wakeup_ipa(struct work_struct *work); +static DECLARE_DELAYED_WORK(rmnet_ll_wakeup_work, + rmnet_ll_wakeup_ipa); +static void apps_rmnet_ll_tx_complete_notify(void *priv, + enum ipa_dp_evt_type evt, unsigned long data); +static void apps_rmnet_ll_receive_notify(void *priv, + enum ipa_dp_evt_type evt, unsigned long data); +static int ipa3_rmnet_ll_register_pm_client(void); +static void ipa3_rmnet_ll_deregister_pm_client(void); +#ifdef CONFIG_DEBUG_FS +#define IPA_MAX_MSG_LEN 4096 +static char dbg_buff[IPA_MAX_MSG_LEN + 1]; + +static ssize_t rmnet_ll_ipa3_read_stats(struct file *file, char __user *ubuf, + size_t count, loff_t *ppos) +{ + int nbytes; + int cnt = 0; + + nbytes = scnprintf(dbg_buff, IPA_MAX_MSG_LEN, + "Queue Leng=%u\n" + "outstanding_pkts=%u\n" + "tx_pkt_sent=%u\n" + "rx_pkt_rcvd=%u\n" + "tx_byte_sent=%lu\n" + "rx_byte_rcvd=%lu\n" + "tx_pkt_dropped=%u\n" + "rx_pkt_dropped=%u\n" + "tx_byte_dropped=%lu\n" + "rx_byte_dropped=%lu\n", + skb_queue_len(&rmnet_ll_ipa3_ctx->tx_queue), + atomic_read( + &rmnet_ll_ipa3_ctx->stats.outstanding_pkts), + rmnet_ll_ipa3_ctx->stats.tx_pkt_sent, + rmnet_ll_ipa3_ctx->stats.rx_pkt_rcvd, + rmnet_ll_ipa3_ctx->stats.tx_byte_sent, + rmnet_ll_ipa3_ctx->stats.rx_byte_rcvd, + rmnet_ll_ipa3_ctx->stats.tx_pkt_dropped, + rmnet_ll_ipa3_ctx->stats.rx_pkt_dropped, + rmnet_ll_ipa3_ctx->stats.tx_byte_dropped, + rmnet_ll_ipa3_ctx->stats.rx_byte_dropped); + cnt += nbytes; + + return simple_read_from_buffer(ubuf, count, ppos, dbg_buff, cnt); +} + +static ssize_t rmnet_ll_ipa3_read_free_credit_threshld +(struct file *file, char __user *buf, size_t count, loff_t *ppos) { + + int nbytes; + nbytes = scnprintf(dbg_buff, IPA_MAX_MSG_LEN, + "Free credit Threshold = %d\n", + rmnet_ll_ipa3_ctx->free_credit_thrshld); + return simple_read_from_buffer(buf, count, ppos, dbg_buff, nbytes); + +} +static ssize_t rmnet_ll_ipa3_write_free_credit_threshld +(struct file *file, const char __user *buf, size_t count, loff_t *ppos) { + + int ret; + u32 free_credit_thrshld =0; + + if (count >= sizeof(dbg_buff)) + return -EFAULT; + + ret = kstrtou32_from_user(buf, count, 0, &free_credit_thrshld); + if(ret) + return ret; + + if(free_credit_thrshld != 0 && + free_credit_thrshld <= IPA_RMNET_LL_FREE_CREDIT_THRSHLD_MAX) + rmnet_ll_ipa3_ctx->free_credit_thrshld = free_credit_thrshld; + else + IPAERR("Invalid value \n"); + + IPADBG("Updated free credit threshold = %d", + rmnet_ll_ipa3_ctx->free_credit_thrshld); + + return count; +} + + +#define READ_WRITE_MODE 0664 +#define READ_ONLY_MODE 0444 +static const struct rmnet_ll_ipa3_debugfs_file debugfs_files[] = { + { + "stats", READ_ONLY_MODE, NULL, { + .read = rmnet_ll_ipa3_read_stats + } + }, { + "free_credit_threshld", READ_WRITE_MODE, NULL, { + .read = rmnet_ll_ipa3_read_free_credit_threshld, + .write = rmnet_ll_ipa3_write_free_credit_threshld, + } + }, +}; + +static void rmnet_ll_ipa3_debugfs_remove(void) +{ + if (IS_ERR(rmnet_ll_ipa3_ctx->dbgfs.dent)) + return; + + debugfs_remove_recursive(rmnet_ll_ipa3_ctx->dbgfs.dent); + memset(&rmnet_ll_ipa3_ctx->dbgfs, 0, + sizeof(struct rmnet_ll_ipa3_debugfs)); +} + +static void rmnet_ll_ipa3_debugfs_init(void) +{ + struct rmnet_ll_ipa3_debugfs *dbgfs = &rmnet_ll_ipa3_ctx->dbgfs; + struct dentry *file; + const size_t debugfs_files_num = + sizeof(debugfs_files) / sizeof(struct rmnet_ll_ipa3_debugfs_file); + size_t i; + + dbgfs->dent = debugfs_create_dir("rmnet_ll_ipa", 0); + if (IS_ERR(dbgfs->dent)) { + pr_err("fail to create folder in debug_fs\n"); + return; + } + + for (i = 0; i < debugfs_files_num; ++i) { + const struct rmnet_ll_ipa3_debugfs_file *curr = &debugfs_files[i]; + + file = debugfs_create_file(curr->name, curr->mode, dbgfs->dent, + curr->data, &curr->fops); + if (!file || IS_ERR(file)) { + IPAERR("fail to create file for debug_fs %s\n", + curr->name); + goto fail; + } + } + + return; + +fail: + rmnet_ll_ipa3_debugfs_remove(); +} +#else /* CONFIG_DEBUG_FS */ +static void rmnet_ll_ipa3_debugfs_init(void){} +static void rmnet_ll_ipa3_debugfs_remove(void){} +#endif /* CONFIG_DEBUG_FS */ + +int ipa3_rmnet_ll_init(void) +{ + char buff[IPA_RESOURCE_NAME_MAX]; + + if (!ipa3_ctx) { + IPAERR("ipa3_ctx was not initialized\n"); + return -EINVAL; + } + + if (ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_PROD) == -1 || + ipa_get_ep_mapping(IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_CONS) == -1) + { + IPAERR("invalid low lat data endpoints\n"); + return -EINVAL; + } + + rmnet_ll_ipa3_ctx = kzalloc(sizeof(*rmnet_ll_ipa3_ctx), + GFP_KERNEL); + + if (!rmnet_ll_ipa3_ctx) + return -ENOMEM; + + snprintf(buff, IPA_RESOURCE_NAME_MAX, "rmnet_llwq"); + rmnet_ll_ipa3_ctx->wq = alloc_workqueue(buff, + WQ_MEM_RECLAIM | WQ_UNBOUND | WQ_SYSFS, 1); + if (!rmnet_ll_ipa3_ctx->wq) { + kfree(rmnet_ll_ipa3_ctx); + rmnet_ll_ipa3_ctx = NULL; + return -ENOMEM; + } + memset(&rmnet_ll_ipa3_ctx->apps_to_ipa_low_lat_data_ep_cfg, 0, + sizeof(struct ipa_sys_connect_params)); + memset(&rmnet_ll_ipa3_ctx->ipa_to_apps_low_lat_data_ep_cfg, 0, + sizeof(struct ipa_sys_connect_params)); + skb_queue_head_init(&rmnet_ll_ipa3_ctx->tx_queue); + rmnet_ll_ipa3_ctx->state = IPA_RMNET_LL_NOT_REG; + mutex_init(&rmnet_ll_ipa3_ctx->lock); + spin_lock_init(&rmnet_ll_ipa3_ctx->tx_lock); + rmnet_ll_ipa3_ctx->pipe_state = IPA_RMNET_LL_PIPE_NOT_READY; + rmnet_ll_ipa3_ctx->free_credit_thrshld = IPA_RMNET_LL_FREE_CREDIT_THRSHLD; + rmnet_ll_ipa3_debugfs_init(); + return 0; +} + +int ipa_register_rmnet_ll_cb( + void (*ipa_rmnet_ll_ready_cb)(void *user_data1), + void *user_data1, + void (*ipa_rmnet_ll_stop_cb)(void *user_data2), + void *user_data2, + void (*ipa_rmnet_ll_rx_notify_cb)( + void *user_data3, void *rx_data), + void *user_data3) +{ + /* check ipa3_ctx existed or not */ + if (!ipa3_ctx) { + IPADBG("rmnet_ll_ctx haven't initialized\n"); + return -EAGAIN; + } + + if (!ipa3_ctx->rmnet_ll_enable) { + IPAERR("low lat data pipes are not supported"); + return -ENXIO; + } + + if (!rmnet_ll_ipa3_ctx) { + IPADBG("rmnet_ll_ctx haven't initialized\n"); + return -EAGAIN; + } + + mutex_lock(&rmnet_ll_ipa3_ctx->lock); + if (rmnet_ll_ipa3_ctx->state != IPA_RMNET_LL_NOT_REG && + rmnet_ll_ipa3_ctx->state != IPA_RMNET_LL_PIPE_READY) { + IPADBG("rmnet_ll registered already\n"); + mutex_unlock(&rmnet_ll_ipa3_ctx->lock); + return -EEXIST; + } + rmnet_ll_ipa3_ctx->cb_info.ready_cb = ipa_rmnet_ll_ready_cb; + rmnet_ll_ipa3_ctx->cb_info.ready_cb_user_data = user_data1; + rmnet_ll_ipa3_ctx->cb_info.stop_cb = ipa_rmnet_ll_stop_cb; + rmnet_ll_ipa3_ctx->cb_info.stop_cb_user_data = user_data2; + rmnet_ll_ipa3_ctx->cb_info.rx_notify_cb = ipa_rmnet_ll_rx_notify_cb; + rmnet_ll_ipa3_ctx->cb_info.rx_notify_cb_user_data = user_data3; + if (rmnet_ll_ipa3_ctx->state == IPA_RMNET_LL_NOT_REG) { + rmnet_ll_ipa3_ctx->state = IPA_RMNET_LL_REGD; + } else { + (*ipa_rmnet_ll_ready_cb)(user_data1); + rmnet_ll_ipa3_ctx->state = IPA_RMNET_LL_START; + } + ipa3_rmnet_ll_register_pm_client(); + mutex_unlock(&rmnet_ll_ipa3_ctx->lock); + IPADBG("rmnet_ll registered successfually\n"); + return 0; +} +EXPORT_SYMBOL(ipa_register_rmnet_ll_cb); + +int ipa_unregister_rmnet_ll_cb(void) +{ + /* check ipa3_ctx existed or not */ + if (!ipa3_ctx) { + IPADBG("IPA driver haven't initialized\n"); + return -EAGAIN; + } + + if (!ipa3_ctx->rmnet_ll_enable) { + IPAERR("low lat data pipe is disabled"); + return -ENXIO; + } + + if (!rmnet_ll_ipa3_ctx) { + IPADBG("rmnet_ll_ctx haven't initialized\n"); + return -EAGAIN; + } + + mutex_lock(&rmnet_ll_ipa3_ctx->lock); + if (rmnet_ll_ipa3_ctx->state != IPA_RMNET_LL_REGD && + rmnet_ll_ipa3_ctx->state != IPA_RMNET_LL_START) { + IPADBG("rmnet_ll unregistered already\n"); + mutex_unlock(&rmnet_ll_ipa3_ctx->lock); + return 0; + } + rmnet_ll_ipa3_ctx->cb_info.ready_cb = NULL; + rmnet_ll_ipa3_ctx->cb_info.ready_cb_user_data = NULL; + rmnet_ll_ipa3_ctx->cb_info.stop_cb = NULL; + rmnet_ll_ipa3_ctx->cb_info.stop_cb_user_data = NULL; + rmnet_ll_ipa3_ctx->cb_info.rx_notify_cb = NULL; + rmnet_ll_ipa3_ctx->cb_info.rx_notify_cb_user_data = NULL; + if (rmnet_ll_ipa3_ctx->state == IPA_RMNET_LL_REGD) + rmnet_ll_ipa3_ctx->state = IPA_RMNET_LL_NOT_REG; + else + rmnet_ll_ipa3_ctx->state = IPA_RMNET_LL_PIPE_READY; + + ipa3_rmnet_ll_deregister_pm_client(); + mutex_unlock(&rmnet_ll_ipa3_ctx->lock); + + IPADBG("rmnet_ll unregistered successfually\n"); + return 0; +} +EXPORT_SYMBOL(ipa_unregister_rmnet_ll_cb); + +int ipa3_setup_apps_low_lat_data_cons_pipe( + struct rmnet_ingress_param *ingress_param, + struct net_device *dev) +{ + struct ipa_sys_connect_params *ipa_low_lat_data_ep_cfg; + int ret = 0; + int ep_idx; + + if (!ipa3_ctx->rmnet_ll_enable) { + IPAERR("low lat data pipe is disabled"); + return 0; + } + ep_idx = ipa_get_ep_mapping( + IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_CONS); + if (ep_idx == IPA_EP_NOT_ALLOCATED) { + IPADBG("Low lat datapath not supported\n"); + return -ENXIO; + } + if (rmnet_ll_ipa3_ctx->state != IPA_RMNET_LL_NOT_REG && + rmnet_ll_ipa3_ctx->state != IPA_RMNET_LL_REGD) { + IPADBG("rmnet_ll in bad state %d\n", + rmnet_ll_ipa3_ctx->state); + return -ENXIO; + } + ipa_low_lat_data_ep_cfg = + &rmnet_ll_ipa3_ctx->ipa_to_apps_low_lat_data_ep_cfg; + /* + * Removing enable aggr from assign_policy + * and placing it here for future enablement + */ + ipa_low_lat_data_ep_cfg->ipa_ep_cfg.aggr.aggr_en = IPA_ENABLE_AGGR; + if (ingress_param) { + /* Open for future cs offload disablement on low lat pipe */ + if (ingress_param->cs_offload_en) { + ipa_low_lat_data_ep_cfg->ipa_ep_cfg.cfg.cs_offload_en = + IPA_ENABLE_CS_DL_QMAP; + } else { + ipa_low_lat_data_ep_cfg->ipa_ep_cfg.cfg.cs_offload_en = + IPA_DISABLE_CS_OFFLOAD; + } + ipa_low_lat_data_ep_cfg->ext_ioctl_v2 = true; + ipa_low_lat_data_ep_cfg->int_modt = ingress_param->int_modt; + ipa_low_lat_data_ep_cfg->int_modc = ingress_param->int_modc; + ipa_low_lat_data_ep_cfg->buff_size = ingress_param->buff_size; + ipa_low_lat_data_ep_cfg->ipa_ep_cfg.aggr.aggr_byte_limit = + ingress_param->agg_byte_limit; + ipa_low_lat_data_ep_cfg->ipa_ep_cfg.aggr.aggr_pkt_limit = + ingress_param->agg_pkt_limit; + ipa_low_lat_data_ep_cfg->ipa_ep_cfg.aggr.aggr_time_limit = + ingress_param->agg_time_limit; + } else { + ipa_low_lat_data_ep_cfg->ext_ioctl_v2 = false; + ipa_low_lat_data_ep_cfg->ipa_ep_cfg.cfg.cs_offload_en = + IPA_ENABLE_CS_DL_QMAP; + ipa_low_lat_data_ep_cfg->ipa_ep_cfg.aggr.aggr_byte_limit = + 0; + ipa_low_lat_data_ep_cfg->ipa_ep_cfg.aggr.aggr_pkt_limit = + 0; + } + + ipa_low_lat_data_ep_cfg->ipa_ep_cfg.hdr.hdr_len = 8; + ipa_low_lat_data_ep_cfg->ipa_ep_cfg.hdr.hdr_ofst_metadata_valid + = 1; + ipa_low_lat_data_ep_cfg->ipa_ep_cfg.hdr.hdr_ofst_metadata + = 1; + ipa_low_lat_data_ep_cfg->ipa_ep_cfg.hdr.hdr_ofst_pkt_size_valid + = 1; + ipa_low_lat_data_ep_cfg->ipa_ep_cfg.hdr.hdr_ofst_pkt_size + = 2; + ipa_low_lat_data_ep_cfg->ipa_ep_cfg.hdr_ext.hdr_total_len_or_pad_valid + = true; + ipa_low_lat_data_ep_cfg->ipa_ep_cfg.hdr_ext.hdr_total_len_or_pad + = 0; + ipa_low_lat_data_ep_cfg->ipa_ep_cfg.hdr_ext.hdr_payload_len_inc_padding + = true; + ipa_low_lat_data_ep_cfg->ipa_ep_cfg.hdr_ext.hdr_total_len_or_pad_offset + = 0; + ipa_low_lat_data_ep_cfg->ipa_ep_cfg.hdr_ext.hdr_little_endian + = 0; + ipa_low_lat_data_ep_cfg->ipa_ep_cfg.metadata_mask.metadata_mask + = 0xFF000000; + ipa_low_lat_data_ep_cfg->client = IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_CONS; + ipa_low_lat_data_ep_cfg->notify = apps_rmnet_ll_receive_notify; + ipa_low_lat_data_ep_cfg->priv = dev; + ipa_low_lat_data_ep_cfg->desc_fifo_sz = + IPA_WWAN_CONS_DESC_FIFO_SZ * IPA_FIFO_ELEMENT_SIZE; + ipa_low_lat_data_ep_cfg->priv = dev; + ret = ipa_setup_sys_pipe( + &rmnet_ll_ipa3_ctx->ipa_to_apps_low_lat_data_ep_cfg, + &rmnet_ll_ipa3_ctx->ipa3_to_apps_low_lat_data_hdl); + if (ret) { + IPADBG("Low lat data pipe setup fails\n"); + return ret; + } + rmnet_ll_ipa3_ctx->pipe_state |= IPA_RMNET_LL_PIPE_RX_READY; + if (rmnet_ll_ipa3_ctx->cb_info.ready_cb) { + (*(rmnet_ll_ipa3_ctx->cb_info.ready_cb)) + (rmnet_ll_ipa3_ctx->cb_info.ready_cb_user_data); + } + /* + * if no ready_cb yet, which means rmnet_ll not + * register to IPA, we will move state to pipe + * ready and will wait for register event + * coming and move to start state. + * The ready_cb will called from regsiter itself. + */ + mutex_lock(&rmnet_ll_ipa3_ctx->lock); + if (rmnet_ll_ipa3_ctx->state == IPA_RMNET_LL_NOT_REG) + rmnet_ll_ipa3_ctx->state = IPA_RMNET_LL_PIPE_READY; + else + rmnet_ll_ipa3_ctx->state = IPA_RMNET_LL_START; + atomic_set(&rmnet_ll_ipa3_ctx->under_flow_controlled_state, 0); + mutex_unlock(&rmnet_ll_ipa3_ctx->lock); + + return 0; +} + +int ipa3_setup_apps_low_lat_data_prod_pipe( + struct rmnet_egress_param *egress_param, + struct net_device *dev) +{ + struct ipa_sys_connect_params *ipa_low_lat_data_ep_cfg; + int ret = 0; + int ep_idx; + + if (!ipa3_ctx->rmnet_ll_enable) { + IPAERR("Low lat pipe is disabled"); + return 0; + } + ep_idx = ipa_get_ep_mapping( + IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_PROD); + if (ep_idx == IPA_EP_NOT_ALLOCATED) { + IPAERR("low lat data pipe not supported\n"); + return -EFAULT; + } + ipa_low_lat_data_ep_cfg = + &rmnet_ll_ipa3_ctx->apps_to_ipa_low_lat_data_ep_cfg; + if (egress_param) { + /* Open for future cs offload disablement on low lat pipe */ + IPAERR("Configuring low lat data prod with rmnet config\n"); + ipa_low_lat_data_ep_cfg->ext_ioctl_v2 = true; + ipa_low_lat_data_ep_cfg->int_modt = egress_param->int_modt; + ipa_low_lat_data_ep_cfg->int_modc = egress_param->int_modc; + if (egress_param->cs_offload_en) { + ipa_low_lat_data_ep_cfg->ipa_ep_cfg.hdr.hdr_len = 8; + ipa_low_lat_data_ep_cfg->ipa_ep_cfg.cfg.cs_offload_en = + IPA_ENABLE_CS_OFFLOAD_UL; + ipa_low_lat_data_ep_cfg->ipa_ep_cfg.cfg.cs_metadata_hdr_offset + = 1; + ipa_low_lat_data_ep_cfg->ipa_ep_cfg.hdr.hdr_ofst_metadata_valid + = 1; + /* modem want offset at 0! */ + ipa_low_lat_data_ep_cfg->ipa_ep_cfg.hdr.hdr_ofst_metadata = 0; + } else { + ipa_low_lat_data_ep_cfg->ipa_ep_cfg.cfg.cs_offload_en = + IPA_DISABLE_CS_OFFLOAD; + } + + /* Open for future deaggr enablement on low lat pipe */ + if (egress_param->aggr_en) { + IPAERR("Enabling deaggr on low_lat_prod\n"); + ipa_low_lat_data_ep_cfg->ipa_ep_cfg.aggr.aggr_en = + IPA_ENABLE_DEAGGR; + ipa_low_lat_data_ep_cfg->ipa_ep_cfg.aggr.aggr = IPA_QCMAP; + ipa_low_lat_data_ep_cfg-> + ipa_ep_cfg.deaggr.packet_offset_valid = false; + } else { + IPAERR("Not enabling deaggr on low_lat_prod\n"); + ipa_low_lat_data_ep_cfg->ipa_ep_cfg.aggr.aggr_en = + IPA_BYPASS_AGGR; + } + } else { + IPAERR("Configuring low lat data prod without rmnet config\n"); + ipa_low_lat_data_ep_cfg->ext_ioctl_v2 = false; + ipa_low_lat_data_ep_cfg->ipa_ep_cfg.hdr.hdr_len = 8; + ipa_low_lat_data_ep_cfg->ipa_ep_cfg.cfg.cs_offload_en = + IPA_ENABLE_CS_OFFLOAD_UL; + ipa_low_lat_data_ep_cfg->ipa_ep_cfg.aggr.aggr_en = + IPA_BYPASS_AGGR; + ipa_low_lat_data_ep_cfg->ipa_ep_cfg.cfg.cs_metadata_hdr_offset + = 1; + ipa_low_lat_data_ep_cfg->ipa_ep_cfg.hdr.hdr_ofst_metadata_valid + = 1; + /* modem want offset at 0 */ + ipa_low_lat_data_ep_cfg->ipa_ep_cfg.hdr.hdr_ofst_metadata = 0; + } + ipa_low_lat_data_ep_cfg->ipa_ep_cfg.metadata_mask.metadata_mask + = 0; + /* modem want offset at 0! */ + ipa_low_lat_data_ep_cfg->ipa_ep_cfg.hdr.hdr_ofst_metadata = 0x00010000; + ipa_low_lat_data_ep_cfg->ipa_ep_cfg.deaggr.syspipe_err_detection = true; + ipa_low_lat_data_ep_cfg->ipa_ep_cfg.mode.dst = + IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_PROD; + ipa_low_lat_data_ep_cfg->client = + IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_PROD; + ipa_low_lat_data_ep_cfg->notify = + apps_rmnet_ll_tx_complete_notify; + ipa_low_lat_data_ep_cfg->priv = dev; + ipa_low_lat_data_ep_cfg->desc_fifo_sz = + IPA_SYS_TX_DATA_DESC_FIFO_SZ_8K; + + ret = ipa_setup_sys_pipe(ipa_low_lat_data_ep_cfg, + &rmnet_ll_ipa3_ctx->apps_to_ipa3_low_lat_data_hdl); + if (ret) { + IPAERR("failed to config apps low lat dtaa prod pipe\n"); + return ret; + } + rmnet_ll_ipa3_ctx->pipe_state |= IPA_RMNET_LL_PIPE_TX_READY; + return 0; +} + +int ipa3_teardown_apps_low_lat_data_pipes(void) +{ + int ret = 0; + + if (rmnet_ll_ipa3_ctx->state != IPA_RMNET_LL_PIPE_READY && + rmnet_ll_ipa3_ctx->state != IPA_RMNET_LL_START && + rmnet_ll_ipa3_ctx->pipe_state == IPA_RMNET_LL_PIPE_NOT_READY) { + IPAERR("rmnet_ll in bad state %d\n", + rmnet_ll_ipa3_ctx->state); + return -EFAULT; + } + if (rmnet_ll_ipa3_ctx->pipe_state == IPA_RMNET_LL_PIPE_READY || + rmnet_ll_ipa3_ctx->state == IPA_RMNET_LL_START) { + if (rmnet_ll_ipa3_ctx->cb_info.stop_cb) { + (*(rmnet_ll_ipa3_ctx->cb_info.stop_cb)) + (rmnet_ll_ipa3_ctx->cb_info.stop_cb_user_data); + } else { + IPAERR("Invalid stop_cb\n"); + return -EFAULT; + } + if (rmnet_ll_ipa3_ctx->state == IPA_RMNET_LL_PIPE_READY) + rmnet_ll_ipa3_ctx->state = IPA_RMNET_LL_NOT_REG; + else + rmnet_ll_ipa3_ctx->state = IPA_RMNET_LL_REGD; + } + if (rmnet_ll_ipa3_ctx->pipe_state & IPA_RMNET_LL_PIPE_RX_READY) { + ret = ipa_teardown_sys_pipe( + rmnet_ll_ipa3_ctx->ipa3_to_apps_low_lat_data_hdl); + if (ret < 0) { + IPAERR("Failed to teardown APPS->IPA low lat data pipe\n"); + return ret; + } + rmnet_ll_ipa3_ctx->ipa3_to_apps_low_lat_data_hdl = -1; + rmnet_ll_ipa3_ctx->pipe_state &= ~IPA_RMNET_LL_PIPE_RX_READY; + } + + if (rmnet_ll_ipa3_ctx->pipe_state & IPA_RMNET_LL_PIPE_TX_READY) { + ret = ipa_teardown_sys_pipe( + rmnet_ll_ipa3_ctx->apps_to_ipa3_low_lat_data_hdl); + if (ret < 0) { + return ret; + IPAERR("Failed to teardown APPS->IPA low lat data pipe\n"); + } + rmnet_ll_ipa3_ctx->apps_to_ipa3_low_lat_data_hdl = -1; + rmnet_ll_ipa3_ctx->pipe_state &= ~IPA_RMNET_LL_PIPE_TX_READY; + } + return ret; +} + +int ipa_rmnet_ll_xmit(struct sk_buff *skb) +{ + int ret; + int len, free_desc = 0; + unsigned long flags; + + if (!ipa3_ctx->rmnet_ll_enable) { + IPAERR("low lat data pipe not supported\n"); + kfree_skb(skb); + return -ENODEV; + } + + spin_lock_irqsave(&rmnet_ll_ipa3_ctx->tx_lock, flags); + + if (rmnet_ll_ipa3_ctx->state != IPA_RMNET_LL_START) { + IPAERR("bad rmnet_ll state %d\n", + rmnet_ll_ipa3_ctx->state); + rmnet_ll_ipa3_ctx->stats.tx_pkt_dropped++; + rmnet_ll_ipa3_ctx->stats.tx_byte_dropped += + skb->len; + spin_unlock_irqrestore(&rmnet_ll_ipa3_ctx->tx_lock, + flags); + kfree_skb(skb); + return -EINVAL; + } + + /* Letting RMNET LL layer to do the flow control. */ + if (!atomic_read( + &rmnet_ll_ipa3_ctx->under_flow_controlled_state) && + (atomic_read( + &rmnet_ll_ipa3_ctx->stats.outstanding_pkts) >= 0) && + ((atomic_read( + &rmnet_ll_ipa3_ctx->stats.outstanding_pkts)+ + skb_queue_len(&rmnet_ll_ipa3_ctx->tx_queue)) + >= RMNET_LL_QUEUE_MAX)) { + IPADBG("IPA LL TX queue full, %d + %d\n", + atomic_read( + &rmnet_ll_ipa3_ctx->stats.outstanding_pkts), + skb_queue_len(&rmnet_ll_ipa3_ctx->tx_queue)); + atomic_set(&rmnet_ll_ipa3_ctx->under_flow_controlled_state, 1); + spin_unlock_irqrestore(&rmnet_ll_ipa3_ctx->tx_lock, + flags); + return -EAGAIN; + } + + /* if queue is not empty, means we still have pending wq */ + if (skb_queue_len(&rmnet_ll_ipa3_ctx->tx_queue) != 0) { + skb_queue_tail(&rmnet_ll_ipa3_ctx->tx_queue, skb); + free_desc = (RMNET_LL_QUEUE_MAX - (atomic_read( + &rmnet_ll_ipa3_ctx->stats.outstanding_pkts)+ + skb_queue_len(&rmnet_ll_ipa3_ctx->tx_queue))); + spin_unlock_irqrestore(&rmnet_ll_ipa3_ctx->tx_lock, + flags); + return (free_desc > 0) ? free_desc : 0; + } + + /* rmnet_ll is calling from atomic context */ + ret = ipa_pm_activate(rmnet_ll_ipa3_ctx->rmnet_ll_pm_hdl); + if (ret == -EINPROGRESS) { + skb_queue_tail(&rmnet_ll_ipa3_ctx->tx_queue, skb); + /* + * delayed work is required here since we need to + * reschedule in the same workqueue context on error + */ + queue_delayed_work(rmnet_ll_ipa3_ctx->wq, + &rmnet_ll_wakeup_work, 0); + free_desc = (RMNET_LL_QUEUE_MAX - (atomic_read( + &rmnet_ll_ipa3_ctx->stats.outstanding_pkts)+ + skb_queue_len(&rmnet_ll_ipa3_ctx->tx_queue))); + spin_unlock_irqrestore(&rmnet_ll_ipa3_ctx->tx_lock, + flags); + return (free_desc > 0) ? free_desc : 0; + } else if (ret) { + IPAERR("[%s] fatal: ipa pm activate failed %d\n", + __func__, ret); + rmnet_ll_ipa3_ctx->stats.tx_pkt_dropped++; + rmnet_ll_ipa3_ctx->stats.tx_byte_dropped += + skb->len; + spin_unlock_irqrestore(&rmnet_ll_ipa3_ctx->tx_lock, + flags); + kfree_skb(skb); + return -EPERM; + } + spin_unlock_irqrestore(&rmnet_ll_ipa3_ctx->tx_lock, flags); + + len = skb->len; + /* + * both data packets and command will be routed to + * IPA_CLIENT_Q6_WAN_CONS based on DMA settings + */ + ret = ipa_tx_dp(IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_PROD, skb, NULL); + if (ret) { + if (ret == -EPIPE) { + IPAERR("Low lat data fatal: pipe is not valid\n"); + spin_lock_irqsave(&rmnet_ll_ipa3_ctx->tx_lock, + flags); + rmnet_ll_ipa3_ctx->stats.tx_pkt_dropped++; + rmnet_ll_ipa3_ctx->stats.tx_byte_dropped += + skb->len; + spin_unlock_irqrestore(&rmnet_ll_ipa3_ctx->tx_lock, + flags); + kfree_skb(skb); + return ret; + } + spin_lock_irqsave(&rmnet_ll_ipa3_ctx->tx_lock, flags); + skb_queue_head(&rmnet_ll_ipa3_ctx->tx_queue, skb); + queue_delayed_work(rmnet_ll_ipa3_ctx->wq, + &rmnet_ll_wakeup_work, 0); + free_desc = (RMNET_LL_QUEUE_MAX - (atomic_read( + &rmnet_ll_ipa3_ctx->stats.outstanding_pkts)+ + skb_queue_len(&rmnet_ll_ipa3_ctx->tx_queue))); + goto out; + } + spin_lock_irqsave(&rmnet_ll_ipa3_ctx->tx_lock, flags); + atomic_inc(&rmnet_ll_ipa3_ctx->stats.outstanding_pkts); + free_desc = (RMNET_LL_QUEUE_MAX - (atomic_read( + &rmnet_ll_ipa3_ctx->stats.outstanding_pkts)+ + skb_queue_len(&rmnet_ll_ipa3_ctx->tx_queue))); + rmnet_ll_ipa3_ctx->stats.tx_pkt_sent++; + rmnet_ll_ipa3_ctx->stats.tx_byte_sent += len; + +out: + if (atomic_read( + &rmnet_ll_ipa3_ctx->stats.outstanding_pkts) + == 0) + ipa_pm_deferred_deactivate(rmnet_ll_ipa3_ctx->rmnet_ll_pm_hdl); + spin_unlock_irqrestore(&rmnet_ll_ipa3_ctx->tx_lock, flags); + return (free_desc > 0) ? free_desc : 0; +} +EXPORT_SYMBOL(ipa_rmnet_ll_xmit); + +static void rmnet_ll_wakeup_ipa(struct work_struct *work) +{ + int ret; + unsigned long flags; + struct sk_buff *skb; + int len = 0; + + /* calling from WQ */ + ret = ipa_pm_activate_sync(rmnet_ll_ipa3_ctx->rmnet_ll_pm_hdl); + if (ret) { + IPAERR("[%s] fatal: ipa pm activate failed %d\n", + __func__, ret); + queue_delayed_work(rmnet_ll_ipa3_ctx->wq, + &rmnet_ll_wakeup_work, + msecs_to_jiffies(1)); + return; + } + + spin_lock_irqsave(&rmnet_ll_ipa3_ctx->tx_lock, flags); + /* dequeue the skb */ + while (skb_queue_len(&rmnet_ll_ipa3_ctx->tx_queue) > 0) { + skb = skb_dequeue(&rmnet_ll_ipa3_ctx->tx_queue); + if (skb == NULL) + continue; + len = skb->len; + spin_unlock_irqrestore(&rmnet_ll_ipa3_ctx->tx_lock, flags); + /* + * both data packets and command will be routed to + * IPA_CLIENT_Q6_WAN_CONS based on DMA settings + */ + ret = ipa_tx_dp(IPA_CLIENT_APPS_WAN_LOW_LAT_DATA_PROD, skb, NULL); + if (ret) { + if (ret == -EPIPE) { + /* try to drain skb from queue if pipe teardown */ + IPAERR_RL("Low lat data fatal: pipe is not valid\n"); + spin_lock_irqsave(&rmnet_ll_ipa3_ctx->tx_lock, + flags); + rmnet_ll_ipa3_ctx->stats.tx_pkt_dropped++; + rmnet_ll_ipa3_ctx->stats.tx_byte_dropped += + skb->len; + kfree_skb(skb); + continue; + } + spin_lock_irqsave(&rmnet_ll_ipa3_ctx->tx_lock, flags); + skb_queue_head(&rmnet_ll_ipa3_ctx->tx_queue, skb); + spin_unlock_irqrestore(&rmnet_ll_ipa3_ctx->tx_lock, flags); + goto delayed_work; + } + + atomic_inc(&rmnet_ll_ipa3_ctx->stats.outstanding_pkts); + spin_lock_irqsave(&rmnet_ll_ipa3_ctx->tx_lock, flags); + rmnet_ll_ipa3_ctx->stats.tx_pkt_sent++; + rmnet_ll_ipa3_ctx->stats.tx_byte_sent += len; + } + spin_unlock_irqrestore(&rmnet_ll_ipa3_ctx->tx_lock, flags); + goto out; + +delayed_work: + queue_delayed_work(rmnet_ll_ipa3_ctx->wq, + &rmnet_ll_wakeup_work, + msecs_to_jiffies(1)); +out: + if (atomic_read( + &rmnet_ll_ipa3_ctx->stats.outstanding_pkts) + == 0) { + ipa_pm_deferred_deactivate(rmnet_ll_ipa3_ctx->rmnet_ll_pm_hdl); + } + +} + +/** + * apps_rmnet_ll_tx_complete_notify() - Rx notify + * + * @priv: driver context + * @evt: event type + * @data: data provided with event + * + * Check that the packet is the one we sent and release it + * This function will be called in defered context in IPA wq. + */ +static void apps_rmnet_ll_tx_complete_notify(void *priv, + enum ipa_dp_evt_type evt, unsigned long data) +{ + struct sk_buff *skb = (struct sk_buff *)data; + unsigned long flags; + u32 pending_credits = 0; + + if (evt != IPA_WRITE_DONE) { + IPAERR("unsupported evt on Tx callback, Drop the packet\n"); + spin_lock_irqsave(&rmnet_ll_ipa3_ctx->tx_lock, + flags); + rmnet_ll_ipa3_ctx->stats.tx_pkt_dropped++; + rmnet_ll_ipa3_ctx->stats.tx_byte_dropped += + skb->len; + spin_unlock_irqrestore(&rmnet_ll_ipa3_ctx->tx_lock, + flags); + dev_kfree_skb_any(skb); + return; + } + + dev_kfree_skb_any(skb); + spin_lock_irqsave(&rmnet_ll_ipa3_ctx->tx_lock, + flags); + atomic_dec(&rmnet_ll_ipa3_ctx->stats.outstanding_pkts); + + if (atomic_read( + &rmnet_ll_ipa3_ctx->stats.outstanding_pkts) == 0) + ipa_pm_deferred_deactivate(rmnet_ll_ipa3_ctx->rmnet_ll_pm_hdl); + + if (atomic_read( + &rmnet_ll_ipa3_ctx->under_flow_controlled_state)) { + pending_credits = (atomic_read( + &rmnet_ll_ipa3_ctx->stats.outstanding_pkts) + + skb_queue_len(&rmnet_ll_ipa3_ctx->tx_queue)); + + if ((RMNET_LL_QUEUE_MAX >= pending_credits) && + ((RMNET_LL_QUEUE_MAX - pending_credits) >= + rmnet_ll_ipa3_ctx->free_credit_thrshld)) { + + atomic_set(&rmnet_ll_ipa3_ctx->under_flow_controlled_state, 0); + IPADBG("IPA LL flow control lifted, %d + %d, %d\n", + atomic_read( + &rmnet_ll_ipa3_ctx->stats.outstanding_pkts), + skb_queue_len(&rmnet_ll_ipa3_ctx->tx_queue), + atomic_read( + &rmnet_ll_ipa3_ctx->under_flow_controlled_state)); + spin_unlock_irqrestore(&rmnet_ll_ipa3_ctx->tx_lock, + flags); + if (rmnet_ll_ipa3_ctx->cb_info.rx_notify_cb) { + (*(rmnet_ll_ipa3_ctx->cb_info.rx_notify_cb))( + (void *)(uintptr_t)(IPA_RMNET_LL_FLOW_EVT), + NULL); + } + } else { + spin_unlock_irqrestore(&rmnet_ll_ipa3_ctx->tx_lock, + flags); + } + } else { + spin_unlock_irqrestore(&rmnet_ll_ipa3_ctx->tx_lock, + flags); + } +} + +/** + * apps_rmnet_ll_receive_notify() - Rmnet_ll RX notify + * + * @priv: driver context + * @evt: event type + * @data: data provided with event + * + * IPA will pass a packet to the Linux network stack with skb->data + */ +static void apps_rmnet_ll_receive_notify(void *priv, + enum ipa_dp_evt_type evt, unsigned long data) +{ + void *rx_notify_cb_rx_data; + struct sk_buff *low_lat_data; + int len; + + low_lat_data = (struct sk_buff *)data; + if (low_lat_data == NULL) { + IPAERR("Rx packet is invalid"); + return; + } + len = low_lat_data->len; + if (evt == IPA_RECEIVE) { + IPADBG_LOW("Rx packet was received"); + rx_notify_cb_rx_data = (void *)data; + if (rmnet_ll_ipa3_ctx->cb_info.rx_notify_cb) { + (*(rmnet_ll_ipa3_ctx->cb_info.rx_notify_cb))( + (void *)(uintptr_t)(IPA_RMNET_LL_RECEIVE), + rx_notify_cb_rx_data); + } else + goto fail; + rmnet_ll_ipa3_ctx->stats.rx_pkt_rcvd++; + rmnet_ll_ipa3_ctx->stats.rx_byte_rcvd += + len; + } else { + IPAERR("Invalid evt %d received in rmnet_ll\n", evt); + goto fail; + } + return; + +fail: + kfree_skb(low_lat_data); + rmnet_ll_ipa3_ctx->stats.rx_pkt_dropped++; +} + + +static int ipa3_rmnet_ll_register_pm_client(void) +{ + int result; + struct ipa_pm_register_params pm_reg; + + memset(&pm_reg, 0, sizeof(pm_reg)); + pm_reg.name = "rmnet_ll"; + pm_reg.group = IPA_PM_GROUP_APPS; + result = ipa_pm_register(&pm_reg, &rmnet_ll_ipa3_ctx->rmnet_ll_pm_hdl); + if (result) { + IPAERR("failed to create IPA PM client %d\n", result); + return result; + } + + IPAERR("%s register done\n", pm_reg.name); + + return 0; +} + +static void ipa3_rmnet_ll_deregister_pm_client(void) +{ + ipa_pm_deactivate_sync(rmnet_ll_ipa3_ctx->rmnet_ll_pm_hdl); + ipa_pm_deregister(rmnet_ll_ipa3_ctx->rmnet_ll_pm_hdl); +} diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/teth_bridge.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/teth_bridge.c new file mode 100644 index 0000000000..995d41c79d --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/ipa_v3/teth_bridge.c @@ -0,0 +1,299 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2013-2019, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ipa.h" +#include +#include "ipa_i.h" + +#define TETH_BRIDGE_DRV_NAME "ipa_tethering_bridge" + +#define TETH_DBG(fmt, args...) \ + pr_debug(TETH_BRIDGE_DRV_NAME " %s:%d " fmt, \ + __func__, __LINE__, ## args) +#define TETH_DBG_FUNC_ENTRY() \ + pr_debug(TETH_BRIDGE_DRV_NAME " %s:%d ENTRY\n", __func__, __LINE__) +#define TETH_DBG_FUNC_EXIT() \ + pr_debug(TETH_BRIDGE_DRV_NAME " %s:%d EXIT\n", __func__, __LINE__) +#define TETH_ERR(fmt, args...) \ + pr_err(TETH_BRIDGE_DRV_NAME " %s:%d " fmt, __func__, __LINE__, ## args) +#define TETH_ERR_RL(fmt, args...) \ + pr_err_ratelimited_ipa(TETH_BRIDGE_DRV_NAME " %s:%d " fmt, __func__, __LINE__, ## args) + +enum ipa_num_teth_iface { + IPA_TETH_IFACE_1 = 0, + IPA_TETH_IFACE_2 = 1, + IPA_TETH_IFACE_MAX +}; + +/** + * struct ipa3_teth_bridge_ctx - Tethering bridge driver context information + * @class: kernel class pointer + * @dev_num: kernel device number + * @dev: kernel device struct pointer + * @cdev: kernel character device struct + */ +struct ipa3_teth_bridge_ctx { + struct class *class; + dev_t dev_num; + struct device *dev; + struct cdev cdev; + u32 modem_pm_hdl[IPA_TETH_IFACE_MAX]; +}; +static struct ipa3_teth_bridge_ctx *ipa3_teth_ctx; + +/** + * teth_bridge_ipa_cb() - Callback to handle IPA data path events + * @priv - private data + * @evt - event type + * @data - event specific data (usually skb) + * + * This callback is called by IPA driver for exception packets from USB. + * All exception packets are handled by Q6 and should not reach this function. + * Packets will arrive to AP exception pipe only in case where packets are + * sent from USB before Q6 has setup the call. + */ +static void teth_bridge_ipa_cb(void *priv, enum ipa_dp_evt_type evt, + unsigned long data) +{ + struct sk_buff *skb = (struct sk_buff *)data; + + TETH_DBG_FUNC_ENTRY(); + if (evt != IPA_RECEIVE) { + TETH_ERR("unexpected event %d\n", evt); + WARN_ON(1); + return; + } + + TETH_ERR_RL("Unexpected exception packet from USB, dropping packet\n"); + dev_kfree_skb_any(skb); + TETH_DBG_FUNC_EXIT(); +} + +/** + * ipa3_teth_bridge_init() - Initialize the Tethering bridge driver + * @params - in/out params for USB initialization API (please look at struct + * definition for more info) + * + * USB driver gets a pointer to a callback function (usb_notify_cb) and an + * associated data. + * + * Builds IPA resource manager dependency graph. + * + * Return codes: 0: success, + * -EINVAL - Bad parameter + * Other negative value - Failure + */ +int ipa3_teth_bridge_init(struct teth_bridge_init_params *params) +{ + TETH_DBG_FUNC_ENTRY(); + + if (!params) { + TETH_ERR("Bad parameter\n"); + TETH_DBG_FUNC_EXIT(); + return -EINVAL; + } + + params->usb_notify_cb = teth_bridge_ipa_cb; + params->private_data = NULL; + params->skip_ep_cfg = true; + + TETH_DBG_FUNC_EXIT(); + return 0; +} +EXPORT_SYMBOL(ipa3_teth_bridge_init); + +/** + * ipa3_teth_bridge_get_pm_hdl() - Get the Tethering bridge Driver pm hdl + * + * + * Return codes: handle + * -EINVAL - Bad parameter + */ +int ipa3_teth_bridge_get_pm_hdl(enum ipa_client_type client) +{ + u32 pm_hdl; + + TETH_DBG_FUNC_ENTRY(); + if (client == IPA_CLIENT_USB2_PROD) + pm_hdl = ipa3_teth_ctx->modem_pm_hdl[IPA_TETH_IFACE_2]; + else + pm_hdl = ipa3_teth_ctx->modem_pm_hdl[IPA_TETH_IFACE_1]; + + if (pm_hdl == ~0) { + TETH_ERR("Bad parameter\n"); + TETH_DBG_FUNC_EXIT(); + return -EINVAL; + } + + TETH_DBG("Return pm-handle %d\n", pm_hdl); + TETH_DBG_FUNC_EXIT(); + return pm_hdl; +} + +/** + * ipa3_teth_bridge_disconnect() - Disconnect tethering bridge module + */ +int ipa3_teth_bridge_disconnect(enum ipa_client_type client) +{ + int res = 0; + int *pm_hdl = NULL; + + TETH_DBG_FUNC_ENTRY(); + + if (client == IPA_CLIENT_USB2_PROD) + pm_hdl = &ipa3_teth_ctx->modem_pm_hdl[IPA_TETH_IFACE_2]; + else + pm_hdl = &ipa3_teth_ctx->modem_pm_hdl[IPA_TETH_IFACE_1]; + + res = ipa_pm_deactivate_sync(*pm_hdl); + if (res) { + TETH_ERR("fail to deactivate modem %d\n", res); + return res; + } + res = ipa_pm_deregister(*pm_hdl); + *pm_hdl = ~0; + + TETH_DBG_FUNC_EXIT(); + + return res; +} +EXPORT_SYMBOL(ipa3_teth_bridge_disconnect); + +/** + * ipa3_teth_bridge_connect() - Connect bridge for a tethered Rmnet / MBIM call + * @connect_params: Connection info + * + * Return codes: 0: success + * -EINVAL: invalid parameters + * -EPERM: Operation not permitted as the bridge is already + * connected + */ +int ipa3_teth_bridge_connect(struct teth_bridge_connect_params *connect_params) +{ + int res = 0; + struct ipa_pm_register_params reg_params; + u32 *pm = NULL; + + memset(®_params, 0, sizeof(reg_params)); + + TETH_DBG_FUNC_ENTRY(); + + if (connect_params->tethering_mode == + TETH_TETHERING_MODE_RMNET_2) { + reg_params.name = "MODEM (USB RMNET_CV2X)"; + pm = &ipa3_teth_ctx->modem_pm_hdl[IPA_TETH_IFACE_2]; + } else { + reg_params.name = "MODEM (USB RMNET)"; + pm = &ipa3_teth_ctx->modem_pm_hdl[IPA_TETH_IFACE_1]; + } + reg_params.group = IPA_PM_GROUP_MODEM; + reg_params.skip_clk_vote = true; + res = ipa_pm_register(®_params, + pm); + if (res) { + TETH_ERR("fail to register with PM %d\n", res); + return res; + } + res = ipa_pm_activate_sync(*pm); + + TETH_DBG_FUNC_EXIT(); + return res; +} +EXPORT_SYMBOL(ipa3_teth_bridge_connect); + +static long ipa3_teth_bridge_ioctl(struct file *filp, + unsigned int cmd, + unsigned long arg) +{ + IPAERR("No ioctls are supported!\n"); + return -ENOIOCTLCMD; +} + +static const struct file_operations ipa3_teth_bridge_drv_fops = { + .owner = THIS_MODULE, + .unlocked_ioctl = ipa3_teth_bridge_ioctl, +}; + +/** + * ipa3_teth_bridge_driver_init() - Initialize tethering bridge driver + * + */ +int ipa3_teth_bridge_driver_init(void) +{ + int res, i; + + if(ipa3_teth_ctx) { + TETH_DBG("Tethering bridge already initlized\n"); + return 0; + } + + TETH_DBG("Tethering bridge driver init\n"); + ipa3_teth_ctx = kzalloc(sizeof(*ipa3_teth_ctx), GFP_KERNEL); + if (!ipa3_teth_ctx) + return -ENOMEM; + + ipa3_teth_ctx->class = class_create(THIS_MODULE, TETH_BRIDGE_DRV_NAME); + + res = alloc_chrdev_region(&ipa3_teth_ctx->dev_num, 0, 1, + TETH_BRIDGE_DRV_NAME); + if (res) { + TETH_ERR("alloc_chrdev_region err.\n"); + res = -ENODEV; + goto fail_alloc_chrdev_region; + } + + ipa3_teth_ctx->dev = device_create(ipa3_teth_ctx->class, + NULL, + ipa3_teth_ctx->dev_num, + ipa3_teth_ctx, + TETH_BRIDGE_DRV_NAME); + if (IS_ERR(ipa3_teth_ctx->dev)) { + TETH_ERR(":device_create err.\n"); + res = -ENODEV; + goto fail_device_create; + } + + cdev_init(&ipa3_teth_ctx->cdev, &ipa3_teth_bridge_drv_fops); + ipa3_teth_ctx->cdev.owner = THIS_MODULE; + ipa3_teth_ctx->cdev.ops = &ipa3_teth_bridge_drv_fops; + + res = cdev_add(&ipa3_teth_ctx->cdev, ipa3_teth_ctx->dev_num, 1); + if (res) { + TETH_ERR(":cdev_add err=%d\n", -res); + res = -ENODEV; + goto fail_cdev_add; + } + + for (i = 0; i < IPA_TETH_IFACE_MAX; i++) + ipa3_teth_ctx->modem_pm_hdl[i] = ~0; + + TETH_DBG("Tethering bridge driver init OK\n"); + + return 0; +fail_cdev_add: + device_destroy(ipa3_teth_ctx->class, ipa3_teth_ctx->dev_num); +fail_device_create: + unregister_chrdev_region(ipa3_teth_ctx->dev_num, 1); +fail_alloc_chrdev_region: + kfree(ipa3_teth_ctx); + ipa3_teth_ctx = NULL; + + return res; +} + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("Tethering bridge driver"); diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/test/ipa_pm_ut.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/test/ipa_pm_ut.c new file mode 100644 index 0000000000..08c9c90ff5 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/test/ipa_pm_ut.c @@ -0,0 +1,1810 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. + */ + +#include "ipa.h" +#include "ipa_pm.h" +#include "ipa_i.h" +#include "ipa_ut_framework.h" +#include + +struct callback_param { + struct completion complete; + enum ipa_pm_cb_event evt; +}; + +static int ipa_pm_ut_setup(void **ppriv) +{ + int i; + int vote; + + IPA_UT_DBG("Start Setup\n"); + + /* decrement UT vote */ + IPA_ACTIVE_CLIENTS_DEC_SPECIAL("IPA_UT"); + + vote = atomic_read(&ipa3_ctx->ipa3_active_clients.cnt); + if (vote) { + IPA_UT_ERR("clock vote is not zero %d\n", vote); + IPA_UT_TEST_FAIL_REPORT("clock is voted"); + IPA_ACTIVE_CLIENTS_INC_SPECIAL("IPA_UT"); + return -EINVAL; + } + + /*decouple PM from RPM */ + ipa3_ctx->enable_clock_scaling = false; + + for (i = 0; i < IPA_PM_MAX_CLIENTS; i++) { + ipa_pm_deactivate_sync(i); + ipa_pm_deregister(i); + } + + ipa_pm_destroy(); + + return 0; +} + +static int ipa_pm_ut_teardown(void *priv) +{ + IPA_UT_DBG("Start Teardown\n"); + IPA_UT_ERR("WARNING: IPA_PM HAS BEEN DESTROYED, REBOOT TO RE_INIT\n"); + + /* undo UT vote */ + IPA_ACTIVE_CLIENTS_INC_SPECIAL("IPA_UT"); + return 0; +} + +/* pass completion struct as the user data/callback params */ +static void ipa_pm_call_back(void *user_data, enum ipa_pm_cb_event evt) +{ + struct callback_param *param; + + param = (struct callback_param *) user_data; + param->evt = evt; + + if (evt == IPA_PM_CLIENT_ACTIVATED) { + IPA_UT_DBG("Activate callback called\n"); + complete_all(¶m->complete); + } else if (evt == IPA_PM_REQUEST_WAKEUP) { + IPA_UT_DBG("Request Wakeup callback called\n"); + complete_all(¶m->complete); + } else + IPA_UT_ERR("invalid callback - callback #%d\n", evt); +} + +static int clean_up(int n, ...) +{ + va_list args; + int i, hdl, rc = 0; + + va_start(args, n); + + IPA_UT_DBG("n = %d\n", n); + + IPA_UT_DBG("Clean up Started"); + + for (i = 0; i < n; i++) { + hdl = va_arg(args, int); + + rc = ipa_pm_deactivate_sync(hdl); + if (rc) { + IPA_UT_ERR("fail to deactivate client - rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("deactivate failed"); + return -EFAULT; + } + rc = ipa_pm_deregister(hdl); + if (rc) { + IPA_UT_ERR("fail to deregister client - rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("deregister failed"); + return -EFAULT; + } + } + va_end(args); + rc = ipa_pm_destroy(); + if (rc) { + IPA_UT_ERR("fail to destroy pm - rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("destroy failed"); + return -EFAULT; + } + + return 0; +} + + +/* test 1 */ +static int ipa_pm_ut_single_registration(void *priv) +{ + int rc = 0; + int hdl, vote; + struct callback_param user_data; + + struct ipa_pm_init_params init_params = { + .threshold_size = 2, + .default_threshold = {600, 1000} + }; + + struct ipa_pm_register_params register_params = { + .name = "USB", + .group = IPA_PM_GROUP_DEFAULT, + .skip_clk_vote = 0, + .callback = ipa_pm_call_back, + .user_data = &user_data + }; + user_data.evt = IPA_PM_CB_EVENT_MAX; + + rc = ipa_pm_init(&init_params); + if (rc) { + IPA_UT_ERR("Fail to init ipa_pm rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail to init params"); + return -EFAULT; + } + + init_completion(&user_data.complete); + + rc = ipa_pm_register(®ister_params, &hdl); + if (rc) { + IPA_UT_ERR("fail to register client rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail to register"); + return -EFAULT; + } + + rc = ipa_pm_activate(hdl); + if (rc != -EINPROGRESS) { + IPA_UT_ERR("fail to queue work - rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("queue activate work failed"); + return -EFAULT; + } + + if (!wait_for_completion_timeout(&user_data.complete, + msecs_to_jiffies(2000))) { + IPA_UT_ERR("timeout waiting for activate_callback\n"); + IPA_UT_TEST_FAIL_REPORT("activate callback not called"); + return -ETIME; + } + + if (user_data.evt != IPA_PM_CLIENT_ACTIVATED) { + IPA_UT_ERR("Callback = %d\n", user_data.evt); + IPA_UT_TEST_FAIL_REPORT("wrong callback called"); + return -EFAULT; + } + + vote = atomic_read(&ipa3_ctx->ipa3_active_clients.cnt); + if (vote != 1) { + IPA_UT_ERR("clock vote is at %d\n", vote); + IPA_UT_TEST_FAIL_REPORT("wrong clock vote"); + return -EINVAL; + } + + rc = ipa_pm_deregister(hdl); + if (rc == 0) { + IPA_UT_ERR("deregister succeeded while it should not\n"); + IPA_UT_TEST_FAIL_REPORT("deregister should not succeed"); + return -EFAULT; + } + + rc = ipa_pm_deferred_deactivate(hdl); + if (rc) { + IPA_UT_ERR("fail to deferred deactivate client - rc = %d\n" + , rc); + IPA_UT_TEST_FAIL_REPORT("fail to deferred deactivate client"); + return -EFAULT; + } + + vote = atomic_read(&ipa3_ctx->ipa3_active_clients.cnt); + if (vote != 1) { + IPA_UT_ERR("clock vote is at %d\n", vote); + IPA_UT_TEST_FAIL_REPORT("wrong clock vote"); + return -EINVAL; + } + + msleep(2000); + + vote = atomic_read(&ipa3_ctx->ipa3_active_clients.cnt); + if (vote != 0) { + IPA_UT_ERR("clock vote is at %d\n", vote); + IPA_UT_TEST_FAIL_REPORT("wrong clock vote"); + return -EINVAL; + } + + rc = ipa_pm_deregister(hdl); + if (rc) { + IPA_UT_ERR("fail to deregister client - rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail to deregister client"); + return -EFAULT; + } + + rc = ipa_pm_activate(hdl); + if (rc == 0) { + IPA_UT_ERR("activate succeeded while it should not\n"); + IPA_UT_TEST_FAIL_REPORT("activate should not succeed"); + return -EFAULT; + } + + rc = ipa_pm_destroy(); + if (rc) { + IPA_UT_ERR("terminate failed - rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("terminate_failed"); + } + + return 0; +} + +/* test 2 */ +static int ipa_pm_ut_double_register_activate(void *priv) +{ + int rc = 0; + int hdl, hdl_test, vote; + struct callback_param user_data; + + struct ipa_pm_init_params init_params = { + .threshold_size = 2, + .default_threshold = {600, 1000} + }; + + struct ipa_pm_register_params register_params = { + .name = "USB", + .group = IPA_PM_GROUP_DEFAULT, + .skip_clk_vote = 0, + .callback = ipa_pm_call_back, + .user_data = &user_data + }; + user_data.evt = IPA_PM_CB_EVENT_MAX; + + rc = ipa_pm_init(&init_params); + if (rc) { + IPA_UT_ERR("Fail to init ipa_pm rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail to init params"); + return -EFAULT; + } + + init_completion(&user_data.complete); + + rc = ipa_pm_register(®ister_params, &hdl); + if (rc) { + IPA_UT_ERR("fail to register client rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail to register"); + return -EFAULT; + } + + rc = ipa_pm_register(®ister_params, &hdl_test); + if (rc != -EEXIST) { + IPA_UT_ERR("registered client with same name rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("did not to fail register"); + return -EFAULT; + } + + rc = ipa_pm_activate(hdl); + if (rc != -EINPROGRESS) { + IPA_UT_ERR("fail to queue work - rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("queue activate work failed"); + return -EFAULT; + } + + /* It is possible that previous activation already completed. */ + rc = ipa_pm_activate(hdl); + if (rc != -EINPROGRESS && rc != 0) { + IPA_UT_ERR("second time activation failed - rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("second time activation failed"); + return -EFAULT; + } + + if (!wait_for_completion_timeout(&user_data.complete, + msecs_to_jiffies(2000))) { + IPA_UT_ERR("timeout waiting for activate_callback\n"); + IPA_UT_TEST_FAIL_REPORT("activate callback not called"); + return -ETIME; + } + + if (user_data.evt != IPA_PM_CLIENT_ACTIVATED) { + IPA_UT_ERR("Callback = %d\n", user_data.evt); + IPA_UT_TEST_FAIL_REPORT("wrong callback called"); + return -EFAULT; + } + + rc = ipa_pm_activate(hdl); + if (rc) { + IPA_UT_ERR("fail to do nothing on 2nd activate = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail to not reactivate"); + return -EFAULT; + } + + msleep(2000); + + vote = atomic_read(&ipa3_ctx->ipa3_active_clients.cnt); + if (vote != 1) { + IPA_UT_ERR("clock vote is at %d\n", vote); + IPA_UT_TEST_FAIL_REPORT("wrong clock vote"); + return -EINVAL; + } + + rc = ipa_pm_deactivate_sync(hdl); + if (rc) { + IPA_UT_ERR("fail to deactivate client - rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail to deactivate client"); + return -EFAULT; + } + + vote = atomic_read(&ipa3_ctx->ipa3_active_clients.cnt); + if (vote != 0) { + IPA_UT_ERR("clock vote is at %d\n", vote); + IPA_UT_TEST_FAIL_REPORT("wrong clock vote"); + return -EINVAL; + } + + rc = clean_up(1, hdl); + return rc; +} + +/* test 3 */ +static int ipa_pm_ut_deferred_deactivate(void *priv) +{ + int rc = 0; + int hdl, vote; + struct callback_param user_data; + + struct ipa_pm_init_params init_params = { + .threshold_size = 2, + .default_threshold = {600, 1000} + }; + + struct ipa_pm_register_params register_params = { + .name = "USB", + .group = IPA_PM_GROUP_DEFAULT, + .skip_clk_vote = 0, + .callback = ipa_pm_call_back, + .user_data = &user_data + }; + user_data.evt = IPA_PM_CB_EVENT_MAX; + + rc = ipa_pm_init(&init_params); + if (rc) { + IPA_UT_ERR("Fail to init ipa_pm - rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail to init params"); + return -EFAULT; + } + + init_completion(&user_data.complete); + + rc = ipa_pm_register(®ister_params, &hdl); + if (rc) { + IPA_UT_ERR("fail to register client rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail to register"); + return -EFAULT; + } + + rc = ipa_pm_activate(hdl); + if (rc != -EINPROGRESS) { + IPA_UT_ERR("fail to queue work - rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("queue activate work failed"); + return -EFAULT; + } + + if (!wait_for_completion_timeout(&user_data.complete, + msecs_to_jiffies(2000))) { + IPA_UT_ERR("timeout waiting for activate_callback\n"); + IPA_UT_TEST_FAIL_REPORT("activate callback not called"); + return -ETIME; + } + + if (user_data.evt != IPA_PM_CLIENT_ACTIVATED) { + IPA_UT_ERR("Callback = %d\n", user_data.evt); + IPA_UT_TEST_FAIL_REPORT("wrong callback called"); + return -EFAULT; + } + + vote = atomic_read(&ipa3_ctx->ipa3_active_clients.cnt); + if (vote != 1) { + IPA_UT_ERR("clock vote is at %d\n", vote); + IPA_UT_TEST_FAIL_REPORT("wrong clock vote"); + return -EINVAL; + } + + rc = ipa_pm_deferred_deactivate(hdl); + if (rc) { + IPA_UT_ERR("fail to deferred deactivate client - rc = %d\n", + rc); + IPA_UT_TEST_FAIL_REPORT("deferred deactivate fail"); + return -EFAULT; + } + + rc = ipa_pm_activate(hdl); + if (rc) { + IPA_UT_ERR("fail to reactivate client - rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("reactivate client failed"); + return -EFAULT; + } + + msleep(2000); + + vote = atomic_read(&ipa3_ctx->ipa3_active_clients.cnt); + if (vote != 1) { + IPA_UT_ERR("clock vote is at %d\n", vote); + IPA_UT_TEST_FAIL_REPORT("wrong clock vote"); + return -EINVAL; + } + + rc = ipa_pm_deactivate_sync(hdl); + if (rc) { + IPA_UT_ERR("fail to deactivate_sync client - rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("deactivate sync failed"); + return -EFAULT; + } + + vote = atomic_read(&ipa3_ctx->ipa3_active_clients.cnt); + if (vote) { + IPA_UT_ERR("clock vote is at %d\n", vote); + IPA_UT_TEST_FAIL_REPORT("wrong clock vote"); + return -EINVAL; + } + + rc = clean_up(1, hdl); + return rc; +} + + +/* test 4 */ +static int ipa_pm_ut_two_clients_activate(void *priv) +{ + int rc = 0; + int hdl_USB, hdl_WLAN, vote; + u32 pipes[IPA_EP_ARR_SIZE] = {0, 0}; + struct callback_param user_data_USB; + struct callback_param user_data_WLAN; + bool wait_for_completion; + int ep, i; + + struct ipa_pm_init_params init_params = { + .threshold_size = 2, + .default_threshold = {600, 1000} + }; + + struct ipa_pm_register_params USB_params = { + .name = "USB", + .group = IPA_PM_GROUP_DEFAULT, + .skip_clk_vote = 0, + .callback = ipa_pm_call_back, + .user_data = &user_data_USB + }; + + struct ipa_pm_register_params WLAN_params = { + .name = "WLAN", + .group = IPA_PM_GROUP_DEFAULT, + .skip_clk_vote = 0, + .callback = ipa_pm_call_back, + .user_data = &user_data_WLAN + }; + user_data_USB.evt = IPA_PM_CB_EVENT_MAX; + user_data_WLAN.evt = IPA_PM_CB_EVENT_MAX; + + rc = ipa_pm_init(&init_params); + if (rc) { + IPA_UT_ERR("Fail to init ipa_pm - rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail to init params"); + return -EFAULT; + } + + init_completion(&user_data_USB.complete); + init_completion(&user_data_WLAN.complete); + + rc = ipa_pm_register(&USB_params, &hdl_USB); + if (rc) { + IPA_UT_ERR("fail to register client 1 rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail to register"); + return -EFAULT; + } + + rc = ipa_pm_register(&WLAN_params, &hdl_WLAN); + if (rc) { + IPA_UT_ERR("fail to register client 2 rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail to register"); + return -EFAULT; + } + + rc = ipa_pm_associate_ipa_cons_to_client(hdl_USB, IPA_CLIENT_USB_CONS); + if (rc) { + IPA_UT_ERR("fail to map client 1 rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail to map client"); + return -EFAULT; + } + + rc = ipa_pm_associate_ipa_cons_to_client(hdl_WLAN, + IPA_CLIENT_WLAN1_CONS); + if (rc) { + IPA_UT_ERR("fail to map client 2 rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail to map client"); + return -EFAULT; + } + + rc = ipa_pm_associate_ipa_cons_to_client(hdl_WLAN, + IPA_CLIENT_USB_DPL_CONS); + if (rc) { + IPA_UT_ERR("fail to map client 2 to multiplt pipes rc = %d\n", + rc); + IPA_UT_TEST_FAIL_REPORT("fail to map client"); + return -EFAULT; + } + + rc = ipa_pm_activate(hdl_USB); + if (rc != -EINPROGRESS) { + IPA_UT_ERR("fail to queue work for client 1 - rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("queue activate work failed"); + return -EFAULT; + } + + /* It could be that USB enabled clocks so WLAN will be activated + * without delay. + */ + rc = ipa_pm_activate(hdl_WLAN); + if (rc != -EINPROGRESS && rc != 0) { + IPA_UT_ERR("failed to activate WLAN - rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("failed to activate WLAN"); + return -EFAULT; + } + wait_for_completion = !rc ? false : true; + + if (!wait_for_completion_timeout(&user_data_USB.complete, + msecs_to_jiffies(2000))) { + IPA_UT_ERR("timeout waiting for activate_callback 1\n"); + IPA_UT_TEST_FAIL_REPORT("activate callback not called"); + return -ETIME; + } + + if (user_data_USB.evt != IPA_PM_CLIENT_ACTIVATED) { + IPA_UT_ERR("Callback = %d\n", user_data_USB.evt); + IPA_UT_TEST_FAIL_REPORT("wrong callback called"); + return -EFAULT; + } + + if (wait_for_completion && + !wait_for_completion_timeout(&user_data_WLAN.complete, + msecs_to_jiffies(2000))) { + IPA_UT_ERR("timeout waiting for activate_callback 2\n"); + IPA_UT_TEST_FAIL_REPORT("activate callback not called"); + return -ETIME; + } + + /* In case WLAN activated immediately, there will be no event */ + if (wait_for_completion && + user_data_WLAN.evt != IPA_PM_CLIENT_ACTIVATED) { + IPA_UT_ERR("Callback = %d\n", user_data_WLAN.evt); + IPA_UT_TEST_FAIL_REPORT("wrong callback called"); + return -EFAULT; + } + + reinit_completion(&user_data_USB.complete); + reinit_completion(&user_data_WLAN.complete); + + vote = atomic_read(&ipa3_ctx->ipa3_active_clients.cnt); + if (vote != 2) { + IPA_UT_ERR("clock vote is at %d\n", vote); + IPA_UT_TEST_FAIL_REPORT("wrong clock vote"); + return -EINVAL; + } + + rc = ipa_pm_deferred_deactivate(hdl_USB); + if (rc) { + IPA_UT_ERR("fail to deferred deactivate client 1 - rc = %d\n", + rc); + IPA_UT_TEST_FAIL_REPORT("deferred deactivate fail"); + return -EFAULT; + } + + msleep(2000); + + rc = ipa_pm_activate(hdl_USB); + if (rc) { + IPA_UT_ERR("no-block activate failed - rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("no-block activate fail"); + return -EFAULT; + } + + ep = ipa_get_ep_mapping(IPA_CLIENT_USB_CONS); + if (ep != IPA_EP_NOT_ALLOCATED) + pipes[ipahal_get_ep_reg_idx(ep)] |= ipahal_get_ep_bit(ep); + + ep = ipa_get_ep_mapping(IPA_CLIENT_WLAN1_CONS); + if (ep != IPA_EP_NOT_ALLOCATED) + pipes[ipahal_get_ep_reg_idx(ep)] |= ipahal_get_ep_bit(ep); + + ep = ipa_get_ep_mapping(IPA_CLIENT_USB_DPL_CONS); + if (ep != IPA_EP_NOT_ALLOCATED) + pipes[ipahal_get_ep_reg_idx(ep)] |= ipahal_get_ep_bit(ep); + + for (i = 0; i < IPA_EP_ARR_SIZE; i++) { + IPA_UT_DBG("pipes[%d] = %d\n", i, pipes[i]); + if (pipes[i]) + ipa_pm_handle_suspend(pipes[i], i); + } + + if (!wait_for_completion_timeout(&user_data_USB.complete, + msecs_to_jiffies(2000))) { + IPA_UT_ERR("timeout waiting for wakeup_callback 1\n"); + IPA_UT_TEST_FAIL_REPORT("wakeup callback not called"); + return -ETIME; + } + + if (user_data_USB.evt != IPA_PM_REQUEST_WAKEUP) { + IPA_UT_ERR("Callback = %d\n", user_data_USB.evt); + IPA_UT_TEST_FAIL_REPORT("wrong callback called"); + return -EFAULT; + } + + if (!wait_for_completion_timeout(&user_data_WLAN.complete, + msecs_to_jiffies(2000))) { + IPA_UT_ERR("timeout waiting for wakeup_callback 2\n"); + IPA_UT_TEST_FAIL_REPORT("wakeup callback not called"); + return -ETIME; + } + + if (user_data_WLAN.evt != IPA_PM_REQUEST_WAKEUP) { + IPA_UT_ERR("Callback = %d\n", user_data_WLAN.evt); + IPA_UT_TEST_FAIL_REPORT("wrong callback called"); + return -EFAULT; + } + + reinit_completion(&user_data_USB.complete); + + rc = ipa_pm_deactivate_sync(hdl_USB); + if (rc) { + IPA_UT_ERR("fail to deactivate_sync client 1 - rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail to deactivate_sync"); + return -EFAULT; + } + + rc = ipa_pm_activate(hdl_USB); + if (rc) { + IPA_UT_ERR("no-block activate failed - rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("no-block activate fail"); + return -EFAULT; + } + + for (i = 0; i < IPA_EP_ARR_SIZE; i++) + pipes[i] = 0; + + ep = ipa_get_ep_mapping(IPA_CLIENT_USB_CONS); + if (ep != IPA_EP_NOT_ALLOCATED) + pipes[ipahal_get_ep_reg_idx(ep)] |= ipahal_get_ep_bit(ep); + + for (i = 0; i < IPA_EP_ARR_SIZE; i++) { + IPA_UT_DBG("pipes[%d] = %d\n", i, pipes[i]); + if (pipes[i]) + ipa_pm_handle_suspend(pipes[i], i); + } + + if (!wait_for_completion_timeout(&user_data_USB.complete, + msecs_to_jiffies(2000))) { + IPA_UT_ERR("timeout waiting for wakeup_callback 1\n"); + IPA_UT_TEST_FAIL_REPORT("wakeup callback not called"); + return -ETIME; + } + + if (user_data_USB.evt != IPA_PM_REQUEST_WAKEUP) { + IPA_UT_ERR("Callback = %d\n", user_data_USB.evt); + IPA_UT_TEST_FAIL_REPORT("wrong callback called"); + return -EFAULT; + } + + rc = clean_up(2, hdl_USB, hdl_WLAN); + return rc; +} + +/* test 5 */ +static int ipa_pm_ut_deactivate_all_deferred(void *priv) +{ + + int rc = 0; + int hdl_USB, hdl_WLAN, hdl_MODEM, vote; + struct callback_param user_data; + + struct ipa_pm_init_params init_params = { + .threshold_size = 2, + .default_threshold = {600, 1000} + }; + + struct ipa_pm_register_params USB_params = { + .name = "USB", + .group = IPA_PM_GROUP_DEFAULT, + .skip_clk_vote = 0, + .callback = ipa_pm_call_back, + .user_data = &user_data + }; + + struct ipa_pm_register_params WLAN_params = { + .name = "WLAN", + .group = IPA_PM_GROUP_DEFAULT, + .skip_clk_vote = 0, + .callback = ipa_pm_call_back, + }; + + struct ipa_pm_register_params MODEM_params = { + .name = "MODEM", + .group = IPA_PM_GROUP_DEFAULT, + .skip_clk_vote = 0, + .callback = ipa_pm_call_back, + }; + user_data.evt = IPA_PM_CB_EVENT_MAX; + + rc = ipa_pm_init(&init_params); + if (rc) { + IPA_UT_ERR("Fail to init ipa_pm - rce %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail to init params"); + return -EFAULT; + } + + init_completion(&user_data.complete); + + rc = ipa_pm_register(&USB_params, &hdl_USB); + if (rc) { + IPA_UT_ERR("fail to register client 1 rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail to register"); + return -EFAULT; + } + + rc = ipa_pm_register(&WLAN_params, &hdl_WLAN); + if (rc) { + IPA_UT_ERR("fail to register client 2 rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail to register"); + return -EFAULT; + } + + rc = ipa_pm_activate(hdl_USB); + if (rc != -EINPROGRESS) { + IPA_UT_ERR("fail to queue work for client 1 - rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("queue activate work failed"); + return -EFAULT; + } + + rc = ipa_pm_activate_sync(hdl_WLAN); + if (rc) { + IPA_UT_ERR("fail to activate sync for client 2- rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("activate sync failed"); + return -EFAULT; + } + + if (!wait_for_completion_timeout(&user_data.complete, + msecs_to_jiffies(2000))) { + IPA_UT_ERR("timeout waiting for activate_callback 1\n"); + IPA_UT_TEST_FAIL_REPORT("activate callback not called"); + return -ETIME; + } + + if (user_data.evt != IPA_PM_CLIENT_ACTIVATED) { + IPA_UT_ERR("Callback = %d\n", user_data.evt); + IPA_UT_TEST_FAIL_REPORT("wrong callback called"); + return -EFAULT; + } + + vote = atomic_read(&ipa3_ctx->ipa3_active_clients.cnt); + if (vote != 2) { + IPA_UT_ERR("clock vote is at %d\n", vote); + IPA_UT_TEST_FAIL_REPORT("wrong clock vote"); + return -EINVAL; + } + + rc = ipa_pm_register(&MODEM_params, &hdl_MODEM); + if (rc) { + IPA_UT_ERR("fail to register client 3 rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail to register"); + return -EFAULT; + } + + rc = ipa_pm_activate(hdl_MODEM); + if (rc) { + IPA_UT_ERR("fail to no-block activate - rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("no-block-activate failed"); + return -EFAULT; + } + + vote = atomic_read(&ipa3_ctx->ipa3_active_clients.cnt); + if (vote != 3) { + IPA_UT_ERR("clock vote is at %d\n", vote); + IPA_UT_TEST_FAIL_REPORT("wrong clock vote"); + return -EINVAL; + } + + rc = ipa_pm_deferred_deactivate(hdl_USB); + if (rc) { + IPA_UT_ERR("fail to deferred deactivate client 1 - rc = %d\n", + rc); + IPA_UT_TEST_FAIL_REPORT("deferred deactivate fail"); + return -EFAULT; + } + + rc = ipa_pm_deferred_deactivate(hdl_WLAN); + if (rc) { + IPA_UT_ERR("fail to deferred deactivate client 2 - rc = %d\n", + rc); + IPA_UT_TEST_FAIL_REPORT("deferred deactivate fail"); + return -EFAULT; + } + + rc = ipa_pm_deactivate_all_deferred(); + vote = atomic_read(&ipa3_ctx->ipa3_active_clients.cnt); + if (vote != 1) { + IPA_UT_ERR("clock vote is at %d\n", vote); + IPA_UT_TEST_FAIL_REPORT("deactivate_all_deferred failed"); + return -EINVAL; + } + + msleep(2000); + vote = atomic_read(&ipa3_ctx->ipa3_active_clients.cnt); + if (vote != 1) { + IPA_UT_ERR("clock vote is at %d\n", vote); + IPA_UT_TEST_FAIL_REPORT("clock vote went below 1"); + return -EINVAL; + } + + rc = clean_up(3, hdl_USB, hdl_WLAN, hdl_MODEM); + return rc; +} + +/* test 5 */ +static int ipa_pm_ut_deactivate_after_activate(void *priv) +{ + + int rc = 0; + int hdl, vote; + struct callback_param user_data; + + struct ipa_pm_init_params init_params = { + .threshold_size = 2, + .default_threshold = {600, 1000} + }; + + struct ipa_pm_register_params USB_params = { + .name = "USB", + .group = IPA_PM_GROUP_DEFAULT, + .skip_clk_vote = 0, + .callback = ipa_pm_call_back, + .user_data = &user_data + }; + + rc = ipa_pm_init(&init_params); + if (rc) { + IPA_UT_ERR("Fail to init ipa_pm - rce %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail to init params"); + return -EFAULT; + } + + init_completion(&user_data.complete); + + rc = ipa_pm_register(&USB_params, &hdl); + if (rc) { + IPA_UT_ERR("fail to register client 1 rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail to register"); + return -EFAULT; + } + + rc = ipa_pm_activate(hdl); + if (rc != -EINPROGRESS) { + IPA_UT_ERR("fail to queue work for client rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("queue activate work failed"); + return -EFAULT; + } + + rc = ipa_pm_deferred_deactivate(hdl); + if (rc) { + IPA_UT_ERR("fail to deferred deactivate client - rc = %d\n", + rc); + IPA_UT_TEST_FAIL_REPORT("deferred deactivate fail"); + return -EFAULT; + } + + msleep(2000); + vote = atomic_read(&ipa3_ctx->ipa3_active_clients.cnt); + if (vote) { + IPA_UT_ERR("clock vote is at %d\n", vote); + IPA_UT_TEST_FAIL_REPORT("wrong clock vote"); + return -EINVAL; + } + + + rc = ipa_pm_activate(hdl); + if (rc != -EINPROGRESS) { + IPA_UT_ERR("fail to queue work for client rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("queue activate work failed"); + return -EFAULT; + } + + rc = ipa_pm_deactivate_sync(hdl); + if (rc) { + IPA_UT_ERR("fail to deactivate sync client - rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("deactivate sync fail"); + return -EFAULT; + } + + msleep(2000); + vote = atomic_read(&ipa3_ctx->ipa3_active_clients.cnt); + if (vote) { + IPA_UT_ERR("clock vote is at %d\n", vote); + IPA_UT_TEST_FAIL_REPORT("wrong clock vote"); + return -EINVAL; + } + + rc = clean_up(1, hdl); + return rc; +} + +/* test 6 */ +static int ipa_pm_ut_atomic_activate(void *priv) +{ + int rc = 0; + int hdl, vote; + struct callback_param user_data; + spinlock_t lock; + unsigned long flags; + + struct ipa_pm_init_params init_params = { + .threshold_size = 2, + .default_threshold = {600, 1000} + }; + + struct ipa_pm_register_params register_params = { + .name = "USB", + .group = IPA_PM_GROUP_DEFAULT, + .skip_clk_vote = 0, + .callback = ipa_pm_call_back, + .user_data = &user_data + }; + user_data.evt = IPA_PM_CB_EVENT_MAX; + + + spin_lock_init(&lock); + + rc = ipa_pm_init(&init_params); + if (rc) { + IPA_UT_ERR("Fail to init ipa_pm rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail to init params"); + return -EFAULT; + } + + init_completion(&user_data.complete); + + rc = ipa_pm_register(®ister_params, &hdl); + if (rc) { + IPA_UT_ERR("fail to register client rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail to register"); + return -EFAULT; + } + + spin_lock_irqsave(&lock, flags); + rc = ipa_pm_activate(hdl); + if (rc != -EINPROGRESS) { + IPA_UT_ERR("fail to queue work - rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("queue activate work failed"); + spin_unlock_irqrestore(&lock, flags); + return -EFAULT; + } + spin_unlock_irqrestore(&lock, flags); + + if (!wait_for_completion_timeout(&user_data.complete, + msecs_to_jiffies(2000))) { + IPA_UT_ERR("timeout waiting for activate_callback\n"); + IPA_UT_TEST_FAIL_REPORT("activate callback not called"); + return -ETIME; + } + + if (user_data.evt != IPA_PM_CLIENT_ACTIVATED) { + IPA_UT_ERR("Callback = %d\n", user_data.evt); + IPA_UT_TEST_FAIL_REPORT("wrong callback called"); + return -EFAULT; + } + + vote = atomic_read(&ipa3_ctx->ipa3_active_clients.cnt); + if (vote != 1) { + IPA_UT_ERR("clock vote is at %d\n", vote); + IPA_UT_TEST_FAIL_REPORT("wrong clock vote"); + return -EINVAL; + } + + rc = clean_up(1, hdl); + return rc; +} + +/* test 7 */ +static int ipa_pm_ut_deactivate_loop(void *priv) +{ + int rc = 0; + int i, hdl_USB, hdl_WLAN, vote; + + struct ipa_pm_init_params init_params = { + .threshold_size = 2, + .default_threshold = {600, 1000} + }; + + struct ipa_pm_register_params USB_params = { + .name = "USB", + .group = IPA_PM_GROUP_DEFAULT, + .skip_clk_vote = 0, + .callback = ipa_pm_call_back, + }; + + struct ipa_pm_register_params WLAN_params = { + .name = "WLAN", + .group = IPA_PM_GROUP_DEFAULT, + .skip_clk_vote = 0, + .callback = ipa_pm_call_back, + }; + + rc = ipa_pm_init(&init_params); + if (rc) { + IPA_UT_ERR("Fail to init ipa_pm - rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail to init params"); + return -EFAULT; + } + + rc = ipa_pm_register(&USB_params, &hdl_USB); + if (rc) { + IPA_UT_ERR("fail to register client 1 rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail to register"); + return -EFAULT; + } + + rc = ipa_pm_set_throughput(hdl_USB, 1200); + if (rc) { + IPA_UT_ERR("fail to set tput for client 1 rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail to set perf profile"); + return -EFAULT; + } + + rc = ipa_pm_register(&WLAN_params, &hdl_WLAN); + if (rc) { + IPA_UT_ERR("fail to register client 2 rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail to register"); + return -EFAULT; + } + + rc = ipa_pm_set_throughput(hdl_WLAN, 800); + if (rc) { + IPA_UT_ERR("fail to set tput for client 2 rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail to set perf profile"); + return -EFAULT; + } + + rc = ipa_pm_activate_sync(hdl_USB); + if (rc) { + IPA_UT_ERR("fail to activate sync for client 1- rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("activate sync failed"); + return -EFAULT; + } + + vote = atomic_read(&ipa3_ctx->ipa3_active_clients.cnt); + if (vote != 1) { + IPA_UT_ERR("clock vote is at %d\n", vote); + IPA_UT_TEST_FAIL_REPORT("wrong clock vote"); + return -EINVAL; + } + + rc = ipa_pm_activate(hdl_WLAN); + if (rc) { + IPA_UT_ERR("fail to activate no block for client 2 - rc = %d\n", + rc); + IPA_UT_TEST_FAIL_REPORT("activate no block failed"); + return -EFAULT; + } + + msleep(2000); + vote = atomic_read(&ipa3_ctx->ipa3_active_clients.cnt); + if (vote != 2) { + IPA_UT_ERR("clock vote is at %d\n", vote); + IPA_UT_TEST_FAIL_REPORT("wrong clock vote"); + return -EINVAL; + } + + rc = ipa_pm_deferred_deactivate(hdl_WLAN); + if (rc) { + IPA_UT_ERR("fail to deferred deactivate client 2 - rc = %d\n", + rc); + IPA_UT_TEST_FAIL_REPORT("deferred deactivate fail"); + return -EFAULT; + } + + for (i = 0; i < 50; i++) { + IPA_UT_DBG("Loop iteration #%d\n", i); + + vote = atomic_read(&ipa3_ctx->ipa3_active_clients.cnt); + if (vote != 2) { + IPA_UT_ERR("clock vote is at %d\n", vote); + IPA_UT_TEST_FAIL_REPORT("wrong clock vote"); + return -EINVAL; + } + + rc = ipa_pm_activate(hdl_WLAN); + if (rc) { + IPA_UT_ERR("fail to undo deactivate for client 2"); + IPA_UT_ERR(" - rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("undo deactivate failed"); + return -EFAULT; + } + + rc = ipa_pm_deferred_deactivate(hdl_WLAN); + if (rc) { + IPA_UT_ERR("fail to deferred deactivate client"); + IPA_UT_ERR(" - rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("deferred deactivate fail"); + return -EFAULT; + } + } + + msleep(2000); + vote = atomic_read(&ipa3_ctx->ipa3_active_clients.cnt); + if (vote != 1) { + IPA_UT_ERR("clock vote is at %d\n", vote); + IPA_UT_TEST_FAIL_REPORT("wrong clock vote"); + return -EINVAL; + } + rc = clean_up(2, hdl_USB, hdl_WLAN); + return rc; + +} + + +/*test 8*/ +static int ipa_pm_ut_set_perf_profile(void *priv) +{ + int rc = 0; + int hdl_USB, hdl_WLAN, vote, idx; + + struct ipa_pm_init_params init_params = { + .threshold_size = 2, + .default_threshold = {600, 1000} + }; + + struct ipa_pm_register_params USB_params = { + .name = "USB", + .group = IPA_PM_GROUP_DEFAULT, + .skip_clk_vote = 0, + .callback = ipa_pm_call_back, + }; + + struct ipa_pm_register_params WLAN_params = { + .name = "WLAN", + .group = IPA_PM_GROUP_DEFAULT, + .skip_clk_vote = 0, + .callback = ipa_pm_call_back, + }; + + rc = ipa_pm_init(&init_params); + if (rc) { + IPA_UT_ERR("Fail to init ipa_pm - rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail to init params"); + return -EFAULT; + } + + rc = ipa_pm_register(&USB_params, &hdl_USB); + if (rc) { + IPA_UT_ERR("fail to register client 1 rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail to register"); + return -EFAULT; + } + + rc = ipa_pm_set_throughput(hdl_USB, 1200); + if (rc) { + IPA_UT_ERR("fail to set tput for client 1 rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail to set perf profile"); + return -EFAULT; + } + + rc = ipa_pm_register(&WLAN_params, &hdl_WLAN); + if (rc) { + IPA_UT_ERR("fail to register client 2 rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail to register"); + return -EFAULT; + } + + rc = ipa_pm_set_throughput(hdl_WLAN, 800); + if (rc) { + IPA_UT_ERR("fail to set tput for client 2 rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail to set perf profile"); + return -EFAULT; + } + + rc = ipa_pm_activate_sync(hdl_USB); + if (rc) { + IPA_UT_ERR("fail to activate sync for client 1- rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("activate sync failed"); + return -EFAULT; + } + + idx = ipa3_ctx->ipa3_active_clients.bus_vote_idx; + if (idx != 1) { + IPA_UT_ERR("clock plan is at %d\n", idx); + IPA_UT_TEST_FAIL_REPORT("wrong clock plan"); + return -EINVAL; + } + + rc = ipa_pm_activate(hdl_WLAN); + if (rc) { + IPA_UT_ERR("fail to activate no block for client 2 - rc = %d\n", + rc); + IPA_UT_TEST_FAIL_REPORT("activate no block failed"); + return -EFAULT; + } + + msleep(2000); + idx = ipa3_ctx->ipa3_active_clients.bus_vote_idx; + if (idx != 2) { + IPA_UT_ERR("clock plan is at %d\n", idx); + IPA_UT_TEST_FAIL_REPORT("wrong clock plan"); + return -EINVAL; + } + + vote = atomic_read(&ipa3_ctx->ipa3_active_clients.cnt); + if (vote != 2) { + IPA_UT_ERR("clock vote is at %d\n", vote); + IPA_UT_TEST_FAIL_REPORT("wrong clock vote"); + return -EINVAL; + } + + rc = ipa_pm_set_throughput(hdl_WLAN, 1200); + if (rc) { + IPA_UT_ERR("fail to set tput for client 2 rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail to set perf profile"); + return -EFAULT; + } + + idx = ipa3_ctx->ipa3_active_clients.bus_vote_idx; + if (idx != 3) { + IPA_UT_ERR("clock plan is at %d\n", idx); + IPA_UT_TEST_FAIL_REPORT("wrong clock plan"); + return -EINVAL; + } + + rc = clean_up(2, hdl_USB, hdl_WLAN); + return rc; +} + +/*test 9*/ +static int ipa_pm_ut_group_tput(void *priv) +{ + int rc = 0; + int hdl_USB, hdl_WLAN, hdl_MODEM, vote, idx; + + struct ipa_pm_init_params init_params = { + .threshold_size = 2, + .default_threshold = {600, 1000} + }; + + struct ipa_pm_register_params USB_params = { + .name = "USB", + .group = IPA_PM_GROUP_APPS, + .skip_clk_vote = 0, + .callback = ipa_pm_call_back, + }; + + struct ipa_pm_register_params WLAN_params = { + .name = "WLAN", + .group = IPA_PM_GROUP_APPS, + .skip_clk_vote = 0, + .callback = ipa_pm_call_back, + }; + + struct ipa_pm_register_params MODEM_params = { + .name = "MODEM", + .group = IPA_PM_GROUP_DEFAULT, + .skip_clk_vote = 0, + .callback = ipa_pm_call_back, + }; + + rc = ipa_pm_init(&init_params); + if (rc) { + IPA_UT_ERR("Fail to init ipa_pm - rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail to init params"); + return -EFAULT; + } + + rc = ipa_pm_register(&USB_params, &hdl_USB); + if (rc) { + IPA_UT_ERR("fail to register client 1 rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail to register"); + return -EFAULT; + } + + rc = ipa_pm_register(&WLAN_params, &hdl_WLAN); + if (rc) { + IPA_UT_ERR("fail to register client 2 rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail to register"); + return -EFAULT; + } + + rc = ipa_pm_set_throughput(hdl_USB, 500); + if (rc) { + IPA_UT_ERR("fail to set tput for client 1 rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail to set perf profile"); + return -EFAULT; + } + + rc = ipa_pm_set_throughput(hdl_WLAN, 800); + if (rc) { + IPA_UT_ERR("fail to set tput for client 2 rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail to set perf profile"); + return -EFAULT; + } + + rc = ipa_pm_activate_sync(hdl_USB); + if (rc) { + IPA_UT_ERR("fail to activate sync for client 1- rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("activate sync failed"); + return -EFAULT; + } + + idx = ipa3_ctx->ipa3_active_clients.bus_vote_idx; + if (idx != 1) { + IPA_UT_ERR("clock plan is at %d\n", idx); + IPA_UT_TEST_FAIL_REPORT("wrong clock plan"); + return -EINVAL; + } + + rc = ipa_pm_activate(hdl_WLAN); + if (rc) { + IPA_UT_ERR("fail to activate no block for client 2 - rc = %d\n", + rc); + IPA_UT_TEST_FAIL_REPORT("activate no block failed"); + return -EFAULT; + } + + vote = atomic_read(&ipa3_ctx->ipa3_active_clients.cnt); + if (vote != 2) { + IPA_UT_ERR("clock vote is at %d\n", vote); + IPA_UT_TEST_FAIL_REPORT("wrong clock vote"); + return -EINVAL; + } + + msleep(2000); + idx = ipa3_ctx->ipa3_active_clients.bus_vote_idx; + if (idx != 1) { + IPA_UT_ERR("clock plan is at %d\n", idx); + IPA_UT_TEST_FAIL_REPORT("wrong clock plan"); + return -EINVAL; + } + + rc = ipa_pm_register(&MODEM_params, &hdl_MODEM); + if (rc) { + IPA_UT_ERR("fail to register client 3 rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail to register"); + return -EFAULT; + } + + rc = ipa_pm_set_throughput(hdl_MODEM, 1000); + if (rc) { + IPA_UT_ERR("fail to set tput for client 2 rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail to set perf profile"); + return -EFAULT; + } + + rc = ipa_pm_activate(hdl_MODEM); + if (rc) { + IPA_UT_ERR("fail to activate no block for client 3 - rc = %d\n", + rc); + IPA_UT_TEST_FAIL_REPORT("activate no block failed"); + return -EFAULT; + } + + vote = atomic_read(&ipa3_ctx->ipa3_active_clients.cnt); + if (vote != 3) { + IPA_UT_ERR("clock vote is at %d\n", vote); + IPA_UT_TEST_FAIL_REPORT("wrong clock vote"); + return -EINVAL; + } + + msleep(2000); + idx = ipa3_ctx->ipa3_active_clients.bus_vote_idx; + if (idx != 2) { + IPA_UT_ERR("clock plan is at %d\n", idx); + IPA_UT_TEST_FAIL_REPORT("wrong clock plan"); + return -EINVAL; + } + + rc = ipa_pm_deactivate_sync(hdl_WLAN); + if (rc) { + IPA_UT_ERR("fail to deactivate client - rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("deactivate failed"); + return -EFAULT; + } + + vote = atomic_read(&ipa3_ctx->ipa3_active_clients.cnt); + if (vote != 2) { + IPA_UT_ERR("clock vote is at %d\n", vote); + IPA_UT_TEST_FAIL_REPORT("wrong clock vote"); + return -EINVAL; + } + + idx = ipa3_ctx->ipa3_active_clients.bus_vote_idx; + if (idx != 2) { + IPA_UT_ERR("clock plan is at %d\n", idx); + IPA_UT_TEST_FAIL_REPORT("wrong clock plan"); + return -EINVAL; + } + + rc = clean_up(3, hdl_USB, hdl_WLAN, hdl_MODEM); + return rc; + +} + +/*test 10*/ +static int ipa_pm_ut_skip_clk_vote_tput(void *priv) +{ + int rc = 0; + int hdl_USB, hdl_WLAN, hdl_MODEM, vote, idx; + + struct ipa_pm_init_params init_params = { + .threshold_size = 2, + .default_threshold = {600, 1000} + }; + + struct ipa_pm_register_params USB_params = { + .name = "USB", + .group = IPA_PM_GROUP_DEFAULT, + .skip_clk_vote = 0, + .callback = ipa_pm_call_back, + }; + + struct ipa_pm_register_params WLAN_params = { + .name = "WLAN", + .group = IPA_PM_GROUP_MODEM, + .skip_clk_vote = 1, + .callback = ipa_pm_call_back, + }; + + struct ipa_pm_register_params MODEM_params = { + .name = "MODEM", + .group = IPA_PM_GROUP_MODEM, + .skip_clk_vote = 1, + .callback = ipa_pm_call_back, + }; + + rc = ipa_pm_init(&init_params); + if (rc) { + IPA_UT_ERR("Fail to init ipa_pm - rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail to init params"); + return -EFAULT; + } + + rc = ipa_pm_register(&USB_params, &hdl_USB); + if (rc) { + IPA_UT_ERR("fail to register client 1 rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail to register"); + return -EFAULT; + } + + rc = ipa_pm_register(&WLAN_params, &hdl_WLAN); + if (rc) { + IPA_UT_ERR("fail to register client 2 rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail to register"); + return -EFAULT; + } + + rc = ipa_pm_set_throughput(hdl_USB, 1200); + if (rc) { + IPA_UT_ERR("fail to set tput for client 1 rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail to set perf profile"); + return -EFAULT; + } + + rc = ipa_pm_set_throughput(hdl_WLAN, 800); + if (rc) { + IPA_UT_ERR("fail to set tput for client 2 rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail to set perf profile"); + return -EFAULT; + } + + rc = ipa_pm_activate_sync(hdl_USB); + if (rc) { + IPA_UT_ERR("fail to activate sync for client 1- rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("activate sync failed"); + return -EFAULT; + } + + idx = ipa3_ctx->ipa3_active_clients.bus_vote_idx; + if (idx != 1) { + IPA_UT_ERR("clock plan is at %d\n", idx); + IPA_UT_TEST_FAIL_REPORT("wrong clock plan"); + return -EINVAL; + } + + rc = ipa_pm_activate(hdl_WLAN); + if (rc) { + IPA_UT_ERR("fail to activate no block for client 2 - rc = %d\n", + rc); + IPA_UT_TEST_FAIL_REPORT("activate no block failed"); + return -EFAULT; + } + + vote = atomic_read(&ipa3_ctx->ipa3_active_clients.cnt); + if (vote != 1) { + IPA_UT_ERR("clock vote is at %d\n", vote); + IPA_UT_TEST_FAIL_REPORT("wrong clock vote"); + return -EINVAL; + } + + msleep(2000); + idx = ipa3_ctx->ipa3_active_clients.bus_vote_idx; + if (idx != 2) { + IPA_UT_ERR("clock plan is at %d\n", idx); + IPA_UT_TEST_FAIL_REPORT("wrong clock plan"); + return -EINVAL; + } + + rc = ipa_pm_register(&MODEM_params, &hdl_MODEM); + if (rc) { + IPA_UT_ERR("fail to register client 3 rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail to register"); + return -EFAULT; + } + + rc = ipa_pm_set_throughput(hdl_MODEM, 2000); + if (rc) { + IPA_UT_ERR("fail to set tput for client 2 rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail to set perf profile"); + return -EFAULT; + } + + rc = ipa_pm_activate(hdl_MODEM); + if (rc) { + IPA_UT_ERR("fail to activate no block for client 3 - rc = %d\n", + rc); + IPA_UT_TEST_FAIL_REPORT("activate no block failed"); + return -EFAULT; + } + + vote = atomic_read(&ipa3_ctx->ipa3_active_clients.cnt); + if (vote != 1) { + IPA_UT_ERR("clock vote is at %d\n", vote); + IPA_UT_TEST_FAIL_REPORT("wrong clock vote"); + return -EINVAL; + } + + msleep(2000); + idx = ipa3_ctx->ipa3_active_clients.bus_vote_idx; + if (idx != 3) { + IPA_UT_ERR("clock plan is at %d\n", idx); + IPA_UT_TEST_FAIL_REPORT("wrong clock plan"); + return -EINVAL; + } + + + rc = ipa_pm_deactivate_sync(hdl_USB); + if (rc) { + IPA_UT_ERR("fail to deactivate client - rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("deactivate failed"); + return -EFAULT; + } + + vote = atomic_read(&ipa3_ctx->ipa3_active_clients.cnt); + if (vote != 0) { + IPA_UT_ERR("clock vote is at %d\n", vote); + IPA_UT_TEST_FAIL_REPORT("wrong clock vote"); + return -EINVAL; + } + + rc = clean_up(3, hdl_USB, hdl_WLAN, hdl_MODEM); + return rc; +} + +/* Test 11 */ +static int ipa_pm_ut_simple_exception(void *priv) +{ + int rc = 0; + int hdl_USB, hdl_WLAN, hdl_MODEM, vote, idx; + + struct ipa_pm_exception exceptions = { + .usecase = "USB", + .threshold = {1000, 1800}, + }; + + struct ipa_pm_init_params init_params = { + .threshold_size = 2, + .default_threshold = {600, 1000}, + .exception_size = 1, + .exceptions[0] = exceptions, + }; + + struct ipa_pm_register_params USB_params = { + .name = "USB", + .group = IPA_PM_GROUP_DEFAULT, + .skip_clk_vote = 0, + .callback = ipa_pm_call_back, + }; + + struct ipa_pm_register_params WLAN_params = { + .name = "WLAN", + .group = IPA_PM_GROUP_DEFAULT, + .skip_clk_vote = 0, + .callback = ipa_pm_call_back, + }; + + struct ipa_pm_register_params MODEM_params = { + .name = "MODEM", + .group = IPA_PM_GROUP_DEFAULT, + .skip_clk_vote = 0, + .callback = ipa_pm_call_back, + }; + + rc = ipa_pm_init(&init_params); + if (rc) { + IPA_UT_ERR("Fail to init ipa_pm - rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail to init params"); + return -EFAULT; + } + + rc = ipa_pm_register(&USB_params, &hdl_USB); + if (rc) { + IPA_UT_ERR("fail to register client 1 rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail to register"); + return -EFAULT; + } + + rc = ipa_pm_register(&WLAN_params, &hdl_WLAN); + if (rc) { + IPA_UT_ERR("fail to register client 2 rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail to register"); + return -EFAULT; + } + + rc = ipa_pm_set_throughput(hdl_USB, 1200); + if (rc) { + IPA_UT_ERR("fail to set tput for client 1 rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail to set perf profile"); + return -EFAULT; + } + + rc = ipa_pm_set_throughput(hdl_WLAN, 2000); + if (rc) { + IPA_UT_ERR("fail to set tput for client 2 rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail to set perf profile"); + return -EFAULT; + } + + rc = ipa_pm_activate_sync(hdl_USB); + if (rc) { + IPA_UT_ERR("fail to activate sync for client 1- rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("activate sync failed"); + return -EFAULT; + } + + idx = ipa3_ctx->ipa3_active_clients.bus_vote_idx; + if (idx != 1) { + IPA_UT_ERR("clock plan is at %d\n", idx); + IPA_UT_TEST_FAIL_REPORT("wrong clock plan"); + return -EINVAL; + } + + rc = ipa_pm_activate(hdl_WLAN); + if (rc) { + IPA_UT_ERR("fail to activate no block for client 2 - rc = %d\n", + rc); + IPA_UT_TEST_FAIL_REPORT("activate no block failed"); + return -EFAULT; + } + + vote = atomic_read(&ipa3_ctx->ipa3_active_clients.cnt); + if (vote != 2) { + IPA_UT_ERR("clock vote is at %d\n", vote); + IPA_UT_TEST_FAIL_REPORT("wrong clock vote"); + return -EINVAL; + } + + msleep(2000); + idx = ipa3_ctx->ipa3_active_clients.bus_vote_idx; + if (idx != 2) { + IPA_UT_ERR("clock plan is at %d\n", idx); + IPA_UT_TEST_FAIL_REPORT("wrong clock plan"); + return -EINVAL; + } + + rc = ipa_pm_register(&MODEM_params, &hdl_MODEM); + if (rc) { + IPA_UT_ERR("fail to register client 3 rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail to register"); + return -EFAULT; + } + + rc = ipa_pm_set_throughput(hdl_MODEM, 800); + if (rc) { + IPA_UT_ERR("fail to set tput for client 2 rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail to set perf profile"); + return -EFAULT; + } + + rc = ipa_pm_activate(hdl_MODEM); + if (rc) { + IPA_UT_ERR("fail to activate no block for client 3 - rc = %d\n", + rc); + IPA_UT_TEST_FAIL_REPORT("activate no block failed"); + return -EFAULT; + } + + vote = atomic_read(&ipa3_ctx->ipa3_active_clients.cnt); + if (vote != 3) { + IPA_UT_ERR("clock vote is at %d\n", vote); + IPA_UT_TEST_FAIL_REPORT("wrong clock vote"); + return -EINVAL; + } + + msleep(2000); + idx = ipa3_ctx->ipa3_active_clients.bus_vote_idx; + if (idx != 3) { + IPA_UT_ERR("clock plan is at %d\n", idx); + IPA_UT_TEST_FAIL_REPORT("wrong clock plan"); + return -EINVAL; + } + + rc = ipa_pm_deactivate_sync(hdl_USB); + if (rc) { + IPA_UT_ERR("fail to deactivate client - rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("deactivate failed"); + return -EFAULT; + } + + vote = atomic_read(&ipa3_ctx->ipa3_active_clients.cnt); + if (vote != 2) { + IPA_UT_ERR("clock vote is at %d\n", vote); + IPA_UT_TEST_FAIL_REPORT("wrong clock vote"); + return -EINVAL; + } + + idx = ipa3_ctx->ipa3_active_clients.bus_vote_idx; + if (idx != 2) { + IPA_UT_ERR("clock plan is at %d\n", idx); + IPA_UT_TEST_FAIL_REPORT("wrong clock plan"); + return -EINVAL; + } + + rc = clean_up(3, hdl_USB, hdl_WLAN, hdl_MODEM); + return rc; +} + +/* Suite definition block */ +IPA_UT_DEFINE_SUITE_START(pm, "PM for IPA", + ipa_pm_ut_setup, ipa_pm_ut_teardown) +{ + IPA_UT_ADD_TEST(single_registration, + "Single Registration/Basic Functions", + ipa_pm_ut_single_registration, + true, IPA_HW_v4_0, IPA_HW_MAX), + IPA_UT_ADD_TEST(double_register_activate, + "double register/activate", + ipa_pm_ut_double_register_activate, + true, IPA_HW_v4_0, IPA_HW_MAX), + IPA_UT_ADD_TEST(deferred_deactivate, + "Deferred_deactivate", + ipa_pm_ut_deferred_deactivate, + true, IPA_HW_v4_0, IPA_HW_MAX), + IPA_UT_ADD_TEST(two_clients_activate, + "Activate two clients", + ipa_pm_ut_two_clients_activate, + true, IPA_HW_v4_0, IPA_HW_MAX), + IPA_UT_ADD_TEST(deactivate_all_deferred, + "Deactivate all deferred", + ipa_pm_ut_deactivate_all_deferred, + true, IPA_HW_v4_0, IPA_HW_MAX), + IPA_UT_ADD_TEST(deactivate_after_activate, + "Deactivate after activate", + ipa_pm_ut_deactivate_after_activate, + true, IPA_HW_v4_0, IPA_HW_MAX), + IPA_UT_ADD_TEST(atomic_activate, + "Atomic activate", + ipa_pm_ut_atomic_activate, + true, IPA_HW_v4_0, IPA_HW_MAX), + IPA_UT_ADD_TEST(deactivate_loop, + "Deactivate Loop", + ipa_pm_ut_deactivate_loop, + true, IPA_HW_v4_0, IPA_HW_MAX), + IPA_UT_ADD_TEST(set_perf_profile, + "Set perf profile", + ipa_pm_ut_set_perf_profile, + true, IPA_HW_v4_0, IPA_HW_MAX), + IPA_UT_ADD_TEST(group_tput, + "Group throughputs", + ipa_pm_ut_group_tput, + true, IPA_HW_v4_0, IPA_HW_MAX), + IPA_UT_ADD_TEST(skip_clk_vote_tput, + "Skip clock vote and tput", + ipa_pm_ut_skip_clk_vote_tput, + true, IPA_HW_v4_0, IPA_HW_MAX), + IPA_UT_ADD_TEST(simple_exception, + "throughput while passing simple exception", + ipa_pm_ut_simple_exception, + true, IPA_HW_v4_0, IPA_HW_MAX), +} IPA_UT_DEFINE_SUITE_END(pm); diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/test/ipa_test_dma.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/test/ipa_test_dma.c new file mode 100644 index 0000000000..6adf3c7c34 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/test/ipa_test_dma.c @@ -0,0 +1,1136 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. + */ + +#include "ipa.h" +#include "ipa_i.h" +#include "ipa_ut_framework.h" + +#define IPA_TEST_DMA_WQ_NAME_BUFF_SZ 64 +#define IPA_TEST_DMA_MT_TEST_NUM_WQ 200 +#define IPA_TEST_DMA_MEMCPY_BUFF_SIZE 16384 +#define IPA_TEST_DMA_MAX_PKT_SIZE 0xFF00 +#define IPA_DMA_TEST_LOOP_NUM 1000 +#define IPA_DMA_TEST_INT_LOOP_NUM 50 +#define IPA_DMA_TEST_ASYNC_PARALLEL_LOOP_NUM 128 +#define IPA_DMA_RUN_TEST_UNIT_IN_LOOP(test_unit, iters, rc, args...) \ + do { \ + int __i; \ + for (__i = 0; __i < iters; __i++) { \ + IPA_UT_LOG(#test_unit " START iter %d\n", __i); \ + rc = test_unit(args); \ + if (!rc) \ + continue; \ + IPA_UT_LOG(#test_unit " failed %d\n", rc); \ + break; \ + } \ + } while (0) + +/** + * struct ipa_test_dma_async_user_data - user_data structure for async memcpy + * @src_mem: source memory buffer + * @dest_mem: destination memory buffer + * @call_serial_number: Id of the caller + * @copy_done: Completion object + */ +struct ipa_test_dma_async_user_data { + struct ipa_mem_buffer src_mem; + struct ipa_mem_buffer dest_mem; + int call_serial_number; + struct completion copy_done; +}; + +/** + * ipa_test_dma_setup() - Suite setup function + */ +static int ipa_test_dma_setup(void **ppriv) +{ + int rc; + + IPA_UT_DBG("Start Setup\n"); + + if (!ipa3_ctx) { + IPA_UT_ERR("No IPA ctx\n"); + return -EINVAL; + } + + rc = ipa_dma_init(); + if (rc) + IPA_UT_ERR("Fail to init ipa_dma - return code %d\n", rc); + else + IPA_UT_DBG("ipa_dma_init() Completed successfully!\n"); + + *ppriv = NULL; + + return rc; +} + +/** + * ipa_test_dma_teardown() - Suite teardown function + */ +static int ipa_test_dma_teardown(void *priv) +{ + IPA_UT_DBG("Start Teardown\n"); + ipa_dma_destroy(); + return 0; +} + +static int ipa_test_dma_alloc_buffs(struct ipa_mem_buffer *src, + struct ipa_mem_buffer *dest, + int size) +{ + int i; + static int val = 1; + int rc; + + val++; + src->size = size; + src->base = dma_alloc_coherent(ipa3_ctx->pdev, src->size, + &src->phys_base, GFP_KERNEL); + if (!src->base) { + IPA_UT_LOG("fail to alloc dma mem %d bytes\n", size); + IPA_UT_TEST_FAIL_REPORT("fail to alloc dma mem"); + return -ENOMEM; + } + + dest->size = size; + dest->base = dma_alloc_coherent(ipa3_ctx->pdev, dest->size, + &dest->phys_base, GFP_KERNEL); + if (!dest->base) { + IPA_UT_LOG("fail to alloc dma mem %d bytes\n", size); + IPA_UT_TEST_FAIL_REPORT("fail to alloc dma mem"); + rc = -ENOMEM; + goto fail_alloc_dest; + } + + for (i = 0; i < src->size; i++) + memset(src->base + i, (val + i) & 0xFF, 1); + rc = memcmp(dest->base, src->base, dest->size); + if (rc == 0) { + IPA_UT_LOG("dest & src buffers are equal\n"); + IPA_UT_TEST_FAIL_REPORT("dest & src buffers are equal"); + rc = -EFAULT; + goto fail_buf_cmp; + } + + return 0; + +fail_buf_cmp: + dma_free_coherent(ipa3_ctx->pdev, dest->size, dest->base, + dest->phys_base); +fail_alloc_dest: + dma_free_coherent(ipa3_ctx->pdev, src->size, src->base, + src->phys_base); + return rc; +} + +static void ipa_test_dma_destroy_buffs(struct ipa_mem_buffer *src, + struct ipa_mem_buffer *dest) +{ + dma_free_coherent(ipa3_ctx->pdev, src->size, src->base, + src->phys_base); + dma_free_coherent(ipa3_ctx->pdev, dest->size, dest->base, + dest->phys_base); +} + +/** + * ipa_test_dma_memcpy_sync() - memcpy in sync mode + * + * @size: buffer size + * @expect_fail: test expects the memcpy to fail + * + * To be run during tests + * 1. Alloc src and dst buffers + * 2. sync memcpy src to dst via dma + * 3. compare src and dts if memcpy succeeded as expected + */ +static int ipa_test_dma_memcpy_sync(int size, bool expect_fail) +{ + int rc = 0; + int i; + struct ipa_mem_buffer src_mem; + struct ipa_mem_buffer dest_mem; + u8 *src; + u8 *dest; + + rc = ipa_test_dma_alloc_buffs(&src_mem, &dest_mem, size); + if (rc) { + IPA_UT_LOG("fail to alloc buffers\n"); + IPA_UT_TEST_FAIL_REPORT("fail to alloc buffers"); + return rc; + } + + rc = ipa_dma_sync_memcpy(dest_mem.phys_base, src_mem.phys_base, size); + if (!expect_fail && rc) { + IPA_UT_LOG("fail to sync memcpy - rc = %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("sync memcpy failed"); + goto free_buffs; + } + if (expect_fail && !rc) { + IPA_UT_LOG("sync memcpy succeeded while expected to fail\n"); + IPA_UT_TEST_FAIL_REPORT( + "sync memcpy succeeded while expected to fail"); + rc = -EFAULT; + goto free_buffs; + } + + if (!rc) { + /* if memcpy succeeded, compare the buffers */ + rc = memcmp(dest_mem.base, src_mem.base, size); + if (rc) { + IPA_UT_LOG("BAD memcpy - buffs are not equals\n"); + IPA_UT_TEST_FAIL_REPORT( + "BAD memcpy - buffs are not equals"); + src = src_mem.base; + dest = dest_mem.base; + for (i = 0; i < size; i++) { + if (*(src + i) != *(dest + i)) { + IPA_UT_LOG("byte: %d 0x%x != 0x%x\n", + i, *(src + i), *(dest + i)); + } + } + } + } else { + /* if memcpy failed as expected, update the rc */ + rc = 0; + } + +free_buffs: + ipa_test_dma_destroy_buffs(&src_mem, &dest_mem); + return rc; +} + +static void ipa_test_dma_async_memcpy_cb(void *comp_obj) +{ + struct completion *xfer_done; + + if (!comp_obj) { + IPA_UT_ERR("Invalid Input\n"); + return; + } + xfer_done = (struct completion *)comp_obj; + complete(xfer_done); +} + +static void ipa_test_dma_async_memcpy_cb_user_data(void *user_param) +{ + int rc; + int i; + u8 *src; + u8 *dest; + struct ipa_test_dma_async_user_data *udata = + (struct ipa_test_dma_async_user_data *)user_param; + + if (!udata) { + IPA_UT_ERR("Invalid user param\n"); + return; + } + + rc = memcmp(udata->dest_mem.base, udata->src_mem.base, + udata->src_mem.size); + if (rc) { + IPA_UT_LOG("BAD memcpy - buffs are not equal sn=%d\n", + udata->call_serial_number); + IPA_UT_TEST_FAIL_REPORT( + "BAD memcpy - buffs are not equal"); + src = udata->src_mem.base; + dest = udata->dest_mem.base; + for (i = 0; i < udata->src_mem.size; i++) { + if (*(src + i) != *(dest + i)) { + IPA_UT_ERR("byte: %d 0x%x != 0x%x\n", i, + *(src + i), *(dest + i)); + } + } + return; + } + + IPA_UT_LOG("Notify on async memcopy sn=%d\n", + udata->call_serial_number); + complete(&(udata->copy_done)); +} + +/** + * ipa_test_dma_memcpy_async() - memcpy in async mode + * + * @size: buffer size + * @expect_fail: test expected the memcpy to fail + * + * To be run during tests + * 1. Alloc src and dst buffers + * 2. async memcpy src to dst via dma and wait for completion + * 3. compare src and dts if memcpy succeeded as expected + */ +static int ipa_test_dma_memcpy_async(int size, bool expect_fail) +{ + int rc = 0; + int i; + struct ipa_mem_buffer src_mem; + struct ipa_mem_buffer dest_mem; + u8 *src; + u8 *dest; + struct completion xfer_done; + + rc = ipa_test_dma_alloc_buffs(&src_mem, &dest_mem, size); + if (rc) { + IPA_UT_LOG("fail to alloc buffers\n"); + IPA_UT_TEST_FAIL_REPORT("fail to alloc buffers"); + return rc; + } + + init_completion(&xfer_done); + rc = ipa_dma_async_memcpy(dest_mem.phys_base, src_mem.phys_base, size, + ipa_test_dma_async_memcpy_cb, &xfer_done); + if (!expect_fail && rc) { + IPA_UT_LOG("fail to initiate async memcpy - rc=%d\n", + rc); + IPA_UT_TEST_FAIL_REPORT("async memcpy initiate failed"); + goto free_buffs; + } + if (expect_fail && !rc) { + IPA_UT_LOG("async memcpy succeeded while expected to fail\n"); + IPA_UT_TEST_FAIL_REPORT( + "async memcpy succeeded while expected to fail"); + rc = -EFAULT; + goto free_buffs; + } + + if (!rc) { + /* if memcpy succeeded, compare the buffers */ + wait_for_completion(&xfer_done); + rc = memcmp(dest_mem.base, src_mem.base, size); + if (rc) { + IPA_UT_LOG("BAD memcpy - buffs are not equals\n"); + IPA_UT_TEST_FAIL_REPORT( + "BAD memcpy - buffs are not equals"); + src = src_mem.base; + dest = dest_mem.base; + for (i = 0; i < size; i++) { + if (*(src + i) != *(dest + i)) { + IPA_UT_LOG("byte: %d 0x%x != 0x%x\n", + i, *(src + i), *(dest + i)); + } + } + } + } else { + /* if memcpy failed as expected, update the rc */ + rc = 0; + } + +free_buffs: + ipa_test_dma_destroy_buffs(&src_mem, &dest_mem); + return rc; +} + +/** + * ipa_test_dma_sync_async_memcpy() - memcpy in sync and then async mode + * + * @size: buffer size + * + * To be run during tests + * 1. several sync memcopy in row + * 2. several async memcopy - + * back-to-back (next async try initiated after prev is completed) + */ +static int ipa_test_dma_sync_async_memcpy(int size) +{ + int rc; + + IPA_DMA_RUN_TEST_UNIT_IN_LOOP(ipa_test_dma_memcpy_sync, + IPA_DMA_TEST_INT_LOOP_NUM, rc, size, false); + if (rc) { + IPA_UT_LOG("sync memcopy fail rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("sync memcopy fail"); + return rc; + } + + IPA_DMA_RUN_TEST_UNIT_IN_LOOP(ipa_test_dma_memcpy_async, + IPA_DMA_TEST_INT_LOOP_NUM, rc, size, false); + if (rc) { + IPA_UT_LOG("async memcopy fail rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("async memcopy fail"); + return rc; + } + + return 0; +} + +/** + * TEST: test enable/disable dma + * 1. enable dma + * 2. disable dma + */ +static int ipa_test_dma_enable_disable(void *priv) +{ + int rc; + + IPA_UT_LOG("Test Start\n"); + + rc = ipa_dma_enable(); + if (rc) { + IPA_UT_LOG("DMA enable failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail enable dma"); + return rc; + } + + rc = ipa_dma_disable(); + if (rc) { + IPA_UT_LOG("DMA disable failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail disable dma"); + return rc; + } + + return 0; +} + +/** + * TEST: test init/enable/disable/destroy dma + * 1. init dma + * 2. enable dma + * 3. disable dma + * 4. destroy dma + */ +static int ipa_test_dma_init_enbl_disable_destroy(void *priv) +{ + int rc; + + IPA_UT_LOG("Test Start\n"); + + rc = ipa_dma_init(); + if (rc) { + IPA_UT_LOG("DMA Init failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail init dma"); + return rc; + } + + rc = ipa_dma_enable(); + if (rc) { + ipa_dma_destroy(); + IPA_UT_LOG("DMA enable failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail enable dma"); + return rc; + } + + rc = ipa_dma_disable(); + if (rc) { + IPA_UT_LOG("DMA disable failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail disable dma"); + return rc; + } + + ipa_dma_destroy(); + + return 0; +} + +/** + * TEST: test enablex2/disablex2 dma + * 1. enable dma + * 2. enable dma + * 3. disable dma + * 4. disable dma + */ +static int ipa_test_dma_enblx2_disablex2(void *priv) +{ + int rc; + + IPA_UT_LOG("Test Start\n"); + + rc = ipa_dma_enable(); + if (rc) { + ipa_dma_destroy(); + IPA_UT_LOG("DMA enable failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail enable dma"); + return rc; + } + + rc = ipa_dma_enable(); + if (rc) { + ipa_dma_destroy(); + IPA_UT_LOG("DMA enable failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail enable dma"); + return rc; + } + + rc = ipa_dma_disable(); + if (rc) { + IPA_UT_LOG("DMA disable failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail disable dma"); + return rc; + } + + rc = ipa_dma_disable(); + if (rc) { + IPA_UT_LOG("DMA disable failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail disable dma"); + return rc; + } + + return 0; +} + +/** + * TEST: memcpy before dma enable + * + * 1. sync memcpy - should fail + * 2. async memcpy - should fail + */ +static int ipa_test_dma_memcpy_before_enable(void *priv) +{ + int rc; + + IPA_UT_LOG("Test Start\n"); + + rc = ipa_test_dma_memcpy_sync(IPA_TEST_DMA_MEMCPY_BUFF_SIZE, true); + if (rc) { + IPA_UT_LOG("sync memcpy succeeded unexpectedly rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("sync memcpy succeeded unexpectedly"); + return rc; + } + + rc = ipa_test_dma_memcpy_async(IPA_TEST_DMA_MEMCPY_BUFF_SIZE, true); + if (rc) { + IPA_UT_LOG("async memcpy succeeded unexpectedly rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("sync memcpy succeeded unexpectedly"); + return rc; + } + + return 0; +} + +/** + * TEST: Sync memory copy + * + * 1. dma enable + * 2. sync memcpy + * 3. dma disable + */ +static int ipa_test_dma_sync_memcpy(void *priv) +{ + int rc; + + IPA_UT_LOG("Test Start\n"); + + rc = ipa_dma_enable(); + if (rc) { + IPA_UT_LOG("DMA enable failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail enable dma"); + return rc; + } + + rc = ipa_test_dma_memcpy_sync(IPA_TEST_DMA_MEMCPY_BUFF_SIZE, false); + if (rc) { + IPA_UT_LOG("sync memcpy failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("sync memcpy failed"); + (void)ipa_dma_disable(); + return rc; + } + + rc = ipa_dma_disable(); + if (rc) { + IPA_UT_LOG("DMA disable failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail disable dma"); + return rc; + } + + return 0; +} + +/** + * TEST: Small sync memory copy + * + * 1. dma enable + * 2. small sync memcpy + * 3. small sync memcpy + * 4. dma disable + */ +static int ipa_test_dma_sync_memcpy_small(void *priv) +{ + int rc; + + IPA_UT_LOG("Test Start\n"); + + rc = ipa_dma_enable(); + if (rc) { + IPA_UT_LOG("DMA enable failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail enable dma"); + return rc; + } + + rc = ipa_test_dma_memcpy_sync(4, false); + if (rc) { + IPA_UT_LOG("sync memcpy failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("sync memcpy failed"); + (void)ipa_dma_disable(); + return rc; + } + + rc = ipa_test_dma_memcpy_sync(7, false); + if (rc) { + IPA_UT_LOG("sync memcpy failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("sync memcpy failed"); + (void)ipa_dma_disable(); + return rc; + } + + rc = ipa_dma_disable(); + if (rc) { + IPA_UT_LOG("DMA disable failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail disable dma"); + return rc; + } + + return 0; +} + +/** + * TEST: Async memory copy + * + * 1. dma enable + * 2. async memcpy + * 3. dma disable + */ +static int ipa_test_dma_async_memcpy(void *priv) +{ + int rc; + + IPA_UT_LOG("Test Start\n"); + + rc = ipa_dma_enable(); + if (rc) { + IPA_UT_LOG("DMA enable failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail enable dma"); + return rc; + } + + rc = ipa_test_dma_memcpy_async(IPA_TEST_DMA_MEMCPY_BUFF_SIZE, false); + if (rc) { + IPA_UT_LOG("async memcpy failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("async memcpy failed"); + (void)ipa_dma_disable(); + return rc; + } + + rc = ipa_dma_disable(); + if (rc) { + IPA_UT_LOG("DMA disable failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail disable dma"); + return rc; + } + + return 0; +} + +/** + * TEST: Small async memory copy + * + * 1. dma enable + * 2. async memcpy + * 3. async memcpy + * 4. dma disable + */ +static int ipa_test_dma_async_memcpy_small(void *priv) +{ + int rc; + + IPA_UT_LOG("Test Start\n"); + + rc = ipa_dma_enable(); + if (rc) { + IPA_UT_LOG("DMA enable failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail enable dma"); + return rc; + } + + rc = ipa_test_dma_memcpy_async(4, false); + if (rc) { + IPA_UT_LOG("async memcpy failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("async memcpy failed"); + (void)ipa_dma_disable(); + return rc; + } + + rc = ipa_test_dma_memcpy_async(7, false); + if (rc) { + IPA_UT_LOG("async memcpy failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("async memcpy failed"); + (void)ipa_dma_disable(); + return rc; + } + + rc = ipa_dma_disable(); + if (rc) { + IPA_UT_LOG("DMA disable failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail disable dma"); + return rc; + } + + return 0; +} + +/** + * TEST: Iteration of sync memory copy + * + * 1. dma enable + * 2. sync memcpy in loop - in row + * 3. dma disable + */ +static int ipa_test_dma_sync_memcpy_in_loop(void *priv) +{ + int rc; + + IPA_UT_LOG("Test Start\n"); + + rc = ipa_dma_enable(); + if (rc) { + IPA_UT_LOG("DMA enable failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail enable dma"); + return rc; + } + + IPA_DMA_RUN_TEST_UNIT_IN_LOOP(ipa_test_dma_memcpy_sync, + IPA_DMA_TEST_LOOP_NUM, rc, + IPA_TEST_DMA_MEMCPY_BUFF_SIZE, false); + if (rc) { + IPA_UT_LOG("Iterations of sync memcpy failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("Iterations of sync memcpy failed"); + (void)ipa_dma_disable(); + return rc; + } + + rc = ipa_dma_disable(); + if (rc) { + IPA_UT_LOG("DMA disable failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail disable dma"); + return rc; + } + + return 0; +} + +/** + * TEST: Iteration of async memory copy + * + * 1. dma enable + * 2. async memcpy in loop - back-to-back + * next async copy is initiated once previous one completed + * 3. dma disable + */ +static int ipa_test_dma_async_memcpy_in_loop(void *priv) +{ + int rc; + + IPA_UT_LOG("Test Start\n"); + + rc = ipa_dma_enable(); + if (rc) { + IPA_UT_LOG("DMA enable failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail enable dma"); + return rc; + } + + IPA_DMA_RUN_TEST_UNIT_IN_LOOP(ipa_test_dma_memcpy_async, + IPA_DMA_TEST_LOOP_NUM, rc, + IPA_TEST_DMA_MEMCPY_BUFF_SIZE, false); + if (rc) { + IPA_UT_LOG("Iterations of async memcpy failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("Iterations of async memcpy failed"); + (void)ipa_dma_disable(); + return rc; + } + + rc = ipa_dma_disable(); + if (rc) { + IPA_UT_LOG("DMA disable failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail disable dma"); + return rc; + } + + return 0; +} + +/** + * TEST: Iteration of interleaved sync and async memory copy + * + * 1. dma enable + * 2. sync and async memcpy in loop - interleaved + * 3. dma disable + */ +static int ipa_test_dma_interleaved_sync_async_memcpy_in_loop(void *priv) +{ + int rc; + + IPA_UT_LOG("Test Start\n"); + + rc = ipa_dma_enable(); + if (rc) { + IPA_UT_LOG("DMA enable failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail enable dma"); + return rc; + } + + IPA_DMA_RUN_TEST_UNIT_IN_LOOP(ipa_test_dma_sync_async_memcpy, + IPA_DMA_TEST_INT_LOOP_NUM, rc, + IPA_TEST_DMA_MEMCPY_BUFF_SIZE); + if (rc) { + IPA_UT_LOG( + "Iterations of interleaved sync async memcpy failed rc=%d\n" + , rc); + IPA_UT_TEST_FAIL_REPORT( + "Iterations of interleaved sync async memcpy failed"); + (void)ipa_dma_disable(); + return rc; + } + + rc = ipa_dma_disable(); + if (rc) { + IPA_UT_LOG("DMA disable failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail disable dma"); + return rc; + } + + return 0; +} + +static atomic_t ipa_test_dma_mt_test_pass; + +struct one_memcpy_work { + struct work_struct work_s; + int size; +}; + +static void ipa_test_dma_wrapper_test_one_sync(struct work_struct *work) +{ + int rc; + struct one_memcpy_work *data = + container_of(work, struct one_memcpy_work, work_s); + + rc = ipa_test_dma_memcpy_sync(data->size, false); + if (rc) { + IPA_UT_LOG("fail sync memcpy from thread rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail sync memcpy from thread"); + return; + } + atomic_inc(&ipa_test_dma_mt_test_pass); +} + +static void ipa_test_dma_wrapper_test_one_async(struct work_struct *work) +{ + int rc; + struct one_memcpy_work *data = + container_of(work, struct one_memcpy_work, work_s); + + rc = ipa_test_dma_memcpy_async(data->size, false); + if (rc) { + IPA_UT_LOG("fail async memcpy from thread rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail async memcpy from thread"); + return; + } + atomic_inc(&ipa_test_dma_mt_test_pass); +} + +/** + * TEST: Multiple threads running sync and sync mem copy + * + * 1. dma enable + * 2. In-loop + * 2.1 create wq for sync memcpy + * 2.2 create wq for async memcpy + * 2.3 queue sync memcpy work + * 2.4 queue async memcoy work + * 3. In-loop + * 3.1 flush and destroy wq sync + * 3.2 flush and destroy wq async + * 3. dma disable + */ +static int ipa_test_dma_mt_sync_async(void *priv) +{ + int rc; + int i; + static struct workqueue_struct *wq_sync[IPA_TEST_DMA_MT_TEST_NUM_WQ]; + static struct workqueue_struct *wq_async[IPA_TEST_DMA_MT_TEST_NUM_WQ]; + static struct one_memcpy_work async[IPA_TEST_DMA_MT_TEST_NUM_WQ]; + static struct one_memcpy_work sync[IPA_TEST_DMA_MT_TEST_NUM_WQ]; + char buff[IPA_TEST_DMA_WQ_NAME_BUFF_SZ]; + + memset(wq_sync, 0, sizeof(wq_sync)); + memset(wq_sync, 0, sizeof(wq_async)); + memset(async, 0, sizeof(async)); + memset(sync, 0, sizeof(sync)); + + rc = ipa_dma_enable(); + if (rc) { + IPA_UT_LOG("DMA enable failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail enable dma"); + return rc; + } + + atomic_set(&ipa_test_dma_mt_test_pass, 0); + for (i = 0; i < IPA_TEST_DMA_MT_TEST_NUM_WQ; i++) { + snprintf(buff, sizeof(buff), "ipa_test_dmaSwq%d", i); + wq_sync[i] = create_singlethread_workqueue(buff); + if (!wq_sync[i]) { + IPA_UT_ERR("failed to create sync wq#%d\n", i); + rc = -EFAULT; + goto fail_create_wq; + } + snprintf(buff, IPA_RESOURCE_NAME_MAX, "ipa_test_dmaAwq%d", i); + wq_async[i] = create_singlethread_workqueue(buff); + if (!wq_async[i]) { + IPA_UT_ERR("failed to create async wq#%d\n", i); + rc = -EFAULT; + goto fail_create_wq; + } + + if (i % 2) { + sync[i].size = IPA_TEST_DMA_MEMCPY_BUFF_SIZE; + async[i].size = IPA_TEST_DMA_MEMCPY_BUFF_SIZE; + } else { + sync[i].size = 4; + async[i].size = 4; + } + INIT_WORK(&sync[i].work_s, ipa_test_dma_wrapper_test_one_sync); + queue_work(wq_sync[i], &sync[i].work_s); + INIT_WORK(&async[i].work_s, + ipa_test_dma_wrapper_test_one_async); + queue_work(wq_async[i], &async[i].work_s); + } + + for (i = 0; i < IPA_TEST_DMA_MT_TEST_NUM_WQ; i++) { + flush_workqueue(wq_sync[i]); + destroy_workqueue(wq_sync[i]); + flush_workqueue(wq_async[i]); + destroy_workqueue(wq_async[i]); + } + + rc = ipa_dma_disable(); + if (rc) { + IPA_UT_LOG("DMA disable failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail disable dma"); + return rc; + } + + if ((2 * IPA_TEST_DMA_MT_TEST_NUM_WQ) != + atomic_read(&ipa_test_dma_mt_test_pass)) { + IPA_UT_LOG( + "Multi-threaded sync/async memcopy failed passed=%d\n" + , atomic_read(&ipa_test_dma_mt_test_pass)); + IPA_UT_TEST_FAIL_REPORT( + "Multi-threaded sync/async memcopy failed"); + return -EFAULT; + } + + return 0; + +fail_create_wq: + (void)ipa_dma_disable(); + for (i = 0; i < IPA_TEST_DMA_MT_TEST_NUM_WQ; i++) { + if (wq_sync[i]) + destroy_workqueue(wq_sync[i]); + if (wq_async[i]) + destroy_workqueue(wq_async[i]); + } + + return rc; +} + +/** + * TEST: Several parallel async memory copy iterations + * + * 1. create several user_data structures - one per iteration + * 2. allocate buffs. Give slice for each iteration + * 3. iterations of async mem copy + * 4. wait for all to complete + * 5. dma disable + */ +static int ipa_test_dma_parallel_async_memcpy_in_loop(void *priv) +{ + int rc; + struct ipa_test_dma_async_user_data *udata; + struct ipa_mem_buffer all_src_mem; + struct ipa_mem_buffer all_dest_mem; + int i; + bool is_fail = false; + + IPA_UT_LOG("Test Start\n"); + + rc = ipa_dma_enable(); + if (rc) { + IPA_UT_LOG("DMA enable failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail enable dma"); + return rc; + } + + udata = kzalloc(IPA_DMA_TEST_ASYNC_PARALLEL_LOOP_NUM * + sizeof(struct ipa_test_dma_async_user_data), GFP_KERNEL); + if (!udata) { + IPA_UT_ERR("fail allocate user_data array\n"); + (void)ipa_dma_disable(); + return -ENOMEM; + } + + rc = ipa_test_dma_alloc_buffs(&all_src_mem, &all_dest_mem, + IPA_TEST_DMA_MEMCPY_BUFF_SIZE); + if (rc) { + IPA_UT_LOG("fail to alloc buffers\n"); + IPA_UT_TEST_FAIL_REPORT("fail to alloc buffers"); + kfree(udata); + (void)ipa_dma_disable(); + return rc; + } + + for (i = 0 ; i < IPA_DMA_TEST_ASYNC_PARALLEL_LOOP_NUM ; i++) { + udata[i].src_mem.size = + IPA_TEST_DMA_MEMCPY_BUFF_SIZE / + IPA_DMA_TEST_ASYNC_PARALLEL_LOOP_NUM; + udata[i].src_mem.base = all_src_mem.base + i * + (IPA_TEST_DMA_MEMCPY_BUFF_SIZE / + IPA_DMA_TEST_ASYNC_PARALLEL_LOOP_NUM); + udata[i].src_mem.phys_base = all_src_mem.phys_base + i * + (IPA_TEST_DMA_MEMCPY_BUFF_SIZE / + IPA_DMA_TEST_ASYNC_PARALLEL_LOOP_NUM); + + udata[i].dest_mem.size = + (IPA_TEST_DMA_MEMCPY_BUFF_SIZE / + IPA_DMA_TEST_ASYNC_PARALLEL_LOOP_NUM); + udata[i].dest_mem.base = all_dest_mem.base + i * + (IPA_TEST_DMA_MEMCPY_BUFF_SIZE / + IPA_DMA_TEST_ASYNC_PARALLEL_LOOP_NUM); + udata[i].dest_mem.phys_base = all_dest_mem.phys_base + i * + (IPA_TEST_DMA_MEMCPY_BUFF_SIZE / + IPA_DMA_TEST_ASYNC_PARALLEL_LOOP_NUM); + + udata[i].call_serial_number = i + 1; + init_completion(&(udata[i].copy_done)); + rc = ipa_dma_async_memcpy(udata[i].dest_mem.phys_base, + udata[i].src_mem.phys_base, + (IPA_TEST_DMA_MEMCPY_BUFF_SIZE / + IPA_DMA_TEST_ASYNC_PARALLEL_LOOP_NUM), + ipa_test_dma_async_memcpy_cb_user_data, &udata[i]); + if (rc) { + IPA_UT_LOG("async memcpy initiation fail i=%d rc=%d\n", + i, rc); + is_fail = true; + } + } + + for (i = 0; i < IPA_DMA_TEST_ASYNC_PARALLEL_LOOP_NUM ; i++) + wait_for_completion(&udata[i].copy_done); + + ipa_test_dma_destroy_buffs(&all_src_mem, &all_dest_mem); + kfree(udata); + rc = ipa_dma_disable(); + if (rc) { + IPA_UT_LOG("DMA disable failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail disable dma"); + return rc; + } + + if (is_fail) { + IPA_UT_LOG("async memcopy failed\n"); + IPA_UT_TEST_FAIL_REPORT("async memcopy failed"); + return -EFAULT; + } + + return 0; +} + +/** + * TEST: Sync memory copy + * + * 1. dma enable + * 2. sync memcpy with max packet size + * 3. dma disable + */ +static int ipa_test_dma_sync_memcpy_max_pkt_size(void *priv) +{ + int rc; + + IPA_UT_LOG("Test Start\n"); + + rc = ipa_dma_enable(); + if (rc) { + IPA_UT_LOG("DMA enable failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail enable dma"); + return rc; + } + + rc = ipa_test_dma_memcpy_sync(IPA_TEST_DMA_MAX_PKT_SIZE, false); + if (rc) { + IPA_UT_LOG("sync memcpy failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("sync memcpy failed"); + (void)ipa_dma_disable(); + return rc; + } + + rc = ipa_dma_disable(); + if (rc) { + IPA_UT_LOG("DMA disable failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail disable dma"); + return rc; + } + + return 0; +} + +/* Suite definition block */ +IPA_UT_DEFINE_SUITE_START(dma, "DMA for GSI", + ipa_test_dma_setup, ipa_test_dma_teardown) +{ + IPA_UT_ADD_TEST(init_enable_disable_destroy, + "Init->Enable->Disable->Destroy", + ipa_test_dma_enable_disable, + true, IPA_HW_v3_0, IPA_HW_MAX), + IPA_UT_ADD_TEST(initx2_enable_disable_destroyx2, + "Initx2->Enable->Disable->Destroyx2", + ipa_test_dma_init_enbl_disable_destroy, + true, IPA_HW_v3_0, IPA_HW_MAX), + IPA_UT_ADD_TEST(init_enablex2_disablex2_destroy, + "Init->Enablex2->Disablex2->Destroy", + ipa_test_dma_enblx2_disablex2, + true, IPA_HW_v3_0, IPA_HW_MAX), + IPA_UT_ADD_TEST(memcpy_before_enable, + "Call memcpy before dma enable and expect it to fail", + ipa_test_dma_memcpy_before_enable, + true, IPA_HW_v3_0, IPA_HW_MAX), + IPA_UT_ADD_TEST(sync_memcpy, + "Sync memory copy", + ipa_test_dma_sync_memcpy, + true, IPA_HW_v3_0, IPA_HW_MAX), + IPA_UT_ADD_TEST(sync_memcpy_small, + "Small Sync memory copy", + ipa_test_dma_sync_memcpy_small, + true, IPA_HW_v3_5, IPA_HW_MAX), + IPA_UT_ADD_TEST(async_memcpy, + "Async memory copy", + ipa_test_dma_async_memcpy, + true, IPA_HW_v3_0, IPA_HW_MAX), + IPA_UT_ADD_TEST(async_memcpy_small, + "Small async memory copy", + ipa_test_dma_async_memcpy_small, + true, IPA_HW_v3_5, IPA_HW_MAX), + IPA_UT_ADD_TEST(sync_memcpy_in_loop, + "Several sync memory copy iterations", + ipa_test_dma_sync_memcpy_in_loop, + true, IPA_HW_v3_0, IPA_HW_MAX), + IPA_UT_ADD_TEST(async_memcpy_in_loop, + "Several async memory copy iterations", + ipa_test_dma_async_memcpy_in_loop, + true, IPA_HW_v3_0, IPA_HW_MAX), + IPA_UT_ADD_TEST(interleaved_sync_async_memcpy_in_loop, + "Several interleaved sync and async memory copy iterations", + ipa_test_dma_interleaved_sync_async_memcpy_in_loop, + true, IPA_HW_v3_0, IPA_HW_MAX), + IPA_UT_ADD_TEST(multi_threaded_multiple_sync_async_memcpy, + "Several multi-threaded sync and async memory copy iterations", + ipa_test_dma_mt_sync_async, + true, IPA_HW_v3_0, IPA_HW_MAX), + IPA_UT_ADD_TEST(parallel_async_memcpy_in_loop, + "Several parallel async memory copy iterations", + ipa_test_dma_parallel_async_memcpy_in_loop, + true, IPA_HW_v3_0, IPA_HW_MAX), + IPA_UT_ADD_TEST(sync_memcpy_max_pkt_size, + "Sync memory copy with max packet size", + ipa_test_dma_sync_memcpy_max_pkt_size, + true, IPA_HW_v3_0, IPA_HW_MAX), +} IPA_UT_DEFINE_SUITE_END(dma); diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/test/ipa_test_example.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/test/ipa_test_example.c new file mode 100644 index 0000000000..515102fed8 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/test/ipa_test_example.c @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + */ + +#include "ipa_ut_framework.h" + +/** + * Example IPA Unit-test suite + * To be a reference for writing new suites and tests. + * This suite is also used as unit-test for the testing framework itself. + * Structure: + * 1- Define the setup and teardown functions + * Not Mandatory. Null may be used as well + * 2- For each test, define its Run() function + * 3- Use IPA_UT_DEFINE_SUITE_START() to start defining the suite + * 4- use IPA_UT_ADD_TEST() for adding tests within + * the suite definition block + * 5- IPA_UT_DEFINE_SUITE_END() close the suite definition + */ + +static int ipa_test_example_dummy; + +static int ipa_test_example_suite_setup(void **ppriv) +{ + IPA_UT_DBG("Start Setup - set 0x1234F\n"); + + ipa_test_example_dummy = 0x1234F; + *ppriv = (void *)&ipa_test_example_dummy; + + return 0; +} + +static int ipa_test_example_teardown(void *priv) +{ + IPA_UT_DBG("Start Teardown\n"); + IPA_UT_DBG("priv=0x%pK - value=0x%x\n", priv, *((int *)priv)); + + return 0; +} + +static int ipa_test_example_test1(void *priv) +{ + IPA_UT_LOG("priv=0x%pK - value=0x%x\n", priv, *((int *)priv)); + ipa_test_example_dummy++; + + return 0; +} + +static int ipa_test_example_test2(void *priv) +{ + IPA_UT_LOG("priv=0x%pK - value=0x%x\n", priv, *((int *)priv)); + ipa_test_example_dummy++; + + return 0; +} + +static int ipa_test_example_test3(void *priv) +{ + IPA_UT_LOG("priv=0x%pK - value=0x%x\n", priv, *((int *)priv)); + ipa_test_example_dummy++; + + return 0; +} + +static int ipa_test_example_test4(void *priv) +{ + IPA_UT_LOG("priv=0x%pK - value=0x%x\n", priv, *((int *)priv)); + ipa_test_example_dummy++; + + IPA_UT_TEST_FAIL_REPORT("failed on test"); + + return -EFAULT; +} + +/* Suite definition block */ +IPA_UT_DEFINE_SUITE_START(example, "Example suite", + ipa_test_example_suite_setup, ipa_test_example_teardown) +{ + IPA_UT_ADD_TEST(test1, "This is test number 1", + ipa_test_example_test1, false, IPA_HW_v1_0, IPA_HW_MAX), + + IPA_UT_ADD_TEST(test2, "This is test number 2", + ipa_test_example_test2, false, IPA_HW_v1_0, IPA_HW_MAX), + + IPA_UT_ADD_TEST(test3, "This is test number 3", + ipa_test_example_test3, false, IPA_HW_v1_1, IPA_HW_v2_6), + + IPA_UT_ADD_TEST(test4, "This is test number 4", + ipa_test_example_test4, false, IPA_HW_v1_1, IPA_HW_MAX), + +} IPA_UT_DEFINE_SUITE_END(example); diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/test/ipa_test_hw_stats.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/test/ipa_test_hw_stats.c new file mode 100644 index 0000000000..315336009b --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/test/ipa_test_hw_stats.c @@ -0,0 +1,1201 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + */ + +#include "ipa_ut_framework.h" +#include "ipa_i.h" +#include + +struct ipa_test_hw_stats_ctx { + u32 odu_prod_hdl; + u32 odu_cons_hdl; + u32 rt4_usb; + u32 rt4_usb_cnt_id; + u32 rt6_usb; + u32 rt6_usb_cnt_id; + u32 rt4_odu_cons; + u32 rt4_odu_cnt_id; + u32 rt6_odu_cons; + u32 rt6_odu_cnt_id; + u32 flt4_usb_cnt_id; + u32 flt6_usb_cnt_id; + u32 flt4_odu_cnt_id; + u32 flt6_odu_cnt_id; + atomic_t odu_pending; +}; + +static struct ipa_test_hw_stats_ctx *ctx; + +static int ipa_test_hw_stats_suite_setup(void **ppriv) +{ + IPA_UT_DBG("Start Setup\n"); + + if (!ctx) + ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); + + return 0; +} + +static int ipa_test_hw_stats_suite_teardown(void *priv) +{ + IPA_UT_DBG("Start Teardown\n"); + + return 0; +} + +static void odu_prod_notify(void *priv, enum ipa_dp_evt_type evt, + unsigned long data) +{ + struct sk_buff *skb = (struct sk_buff *)data; + + switch (evt) { + case IPA_RECEIVE: + dev_kfree_skb_any(skb); + break; + case IPA_WRITE_DONE: + atomic_dec(&ctx->odu_pending); + dev_kfree_skb_any(skb); + break; + default: + IPA_UT_ERR("unexpected evt %d\n", evt); + } +} +static void odu_cons_notify(void *priv, enum ipa_dp_evt_type evt, + unsigned long data) +{ + struct sk_buff *skb = (struct sk_buff *)data; + int ret; + + switch (evt) { + case IPA_RECEIVE: + if (atomic_read(&ctx->odu_pending) >= 64) + msleep(20); + atomic_inc(&ctx->odu_pending); + skb_put(skb, 100); + ret = ipa_tx_dp(IPA_CLIENT_ODU_PROD, skb, NULL); + while (ret) { + msleep(100); + ret = ipa_tx_dp(IPA_CLIENT_ODU_PROD, skb, NULL); + } + break; + case IPA_WRITE_DONE: + dev_kfree_skb_any(skb); + break; + default: + IPA_UT_ERR("unexpected evt %d\n", evt); + } +} + +static int ipa_test_hw_stats_configure(void *priv) +{ + struct ipa_sys_connect_params odu_prod_params; + struct ipa_sys_connect_params odu_emb_cons_params; + int res; + + /* first connect all additional pipe */ + memset(&odu_prod_params, 0, sizeof(odu_prod_params)); + memset(&odu_emb_cons_params, 0, sizeof(odu_emb_cons_params)); + + odu_prod_params.client = IPA_CLIENT_ODU_PROD; + odu_prod_params.desc_fifo_sz = 0x1000; + odu_prod_params.priv = NULL; + odu_prod_params.notify = odu_prod_notify; + res = ipa_setup_sys_pipe(&odu_prod_params, + &ctx->odu_prod_hdl); + if (res) { + IPA_UT_ERR("fail to setup sys pipe ODU_PROD %d\n", res); + return res; + } + + odu_emb_cons_params.client = IPA_CLIENT_ODU_EMB_CONS; + odu_emb_cons_params.desc_fifo_sz = 0x1000; + odu_emb_cons_params.priv = NULL; + odu_emb_cons_params.notify = odu_cons_notify; + res = ipa_setup_sys_pipe(&odu_emb_cons_params, + &ctx->odu_cons_hdl); + if (res) { + IPA_UT_ERR("fail to setup sys pipe ODU_EMB_CONS %d\n", res); + ipa_teardown_sys_pipe(ctx->odu_prod_hdl); + return res; + } + + IPA_UT_INFO("Configured. Please connect USB RNDIS now\n"); + + return 0; +} + +static int ipa_test_hw_stats_add_FnR(void *priv) +{ + struct ipa_ioc_add_rt_rule_v2 *rt_rule; + struct ipa_ioc_add_flt_rule_v2 *flt_rule; + struct ipa_ioc_get_rt_tbl rt_lookup; + struct ipa_ioc_flt_rt_counter_alloc *counter = NULL; + struct ipa_ioc_flt_rt_query *query; + int pyld_size = 0; + int ret; + + rt_rule = kzalloc(sizeof(*rt_rule), GFP_KERNEL); + if (!rt_rule) { + IPA_UT_DBG("no mem\n"); + return -ENOMEM; + } + rt_rule->rules = (uint64_t)kzalloc(1 * + sizeof(struct ipa_rt_rule_add_v2), GFP_KERNEL); + if (!rt_rule->rules) { + IPA_UT_DBG("no mem\n"); + ret = -ENOMEM; + goto free_rt; + } + + flt_rule = kzalloc(sizeof(*flt_rule), GFP_KERNEL); + if (!flt_rule) { + IPA_UT_DBG("no mem\n"); + ret = -ENOMEM; + goto free_rt; + } + flt_rule->rules = (uint64_t)kzalloc(1 * + sizeof(struct ipa_flt_rule_add_v2), GFP_KERNEL); + if (!flt_rule->rules) { + ret = -ENOMEM; + goto free_flt; + } + + counter = kzalloc(sizeof(struct ipa_ioc_flt_rt_counter_alloc), + GFP_KERNEL); + if (!counter) { + ret = -ENOMEM; + goto free_flt; + } + counter->hw_counter.num_counters = 8; + counter->sw_counter.num_counters = 1; + + /* allocate counters */ + ret = ipa3_alloc_counter_id(counter); + if (ret < 0) { + IPA_UT_DBG("ipa3_alloc_counter_id fails\n"); + ret = -ENOMEM; + goto free_counter; + } + + /* initially clean all allocated counters */ + query = kzalloc(sizeof(struct ipa_ioc_flt_rt_query), + GFP_KERNEL); + if (!query) { + ret = -ENOMEM; + goto free_counter; + } + query->start_id = counter->hw_counter.start_id; + query->end_id = counter->hw_counter.start_id + + counter->hw_counter.num_counters - 1; + query->reset = true; + query->stats_size = sizeof(struct ipa_flt_rt_stats); + pyld_size = IPA_MAX_FLT_RT_CNT_INDEX * + sizeof(struct ipa_flt_rt_stats); + query->stats = (uint64_t)kzalloc(pyld_size, GFP_KERNEL); + if (!query->stats) { + ret = -ENOMEM; + goto free_query; + } + ipa_get_flt_rt_stats(query); + + query->start_id = counter->sw_counter.start_id; + query->end_id = counter->sw_counter.start_id + + counter->sw_counter.num_counters - 1; + query->reset = true; + query->stats_size = sizeof(struct ipa_flt_rt_stats); + ipa_get_flt_rt_stats(query); + + rt_rule->commit = 1; + rt_rule->ip = IPA_IP_v4; + rt_lookup.ip = rt_rule->ip; + strlcpy(rt_rule->rt_tbl_name, "V4_RT_TO_USB_CONS", + IPA_RESOURCE_NAME_MAX); + strlcpy(rt_lookup.name, rt_rule->rt_tbl_name, IPA_RESOURCE_NAME_MAX); + rt_rule->num_rules = 1; + ((struct ipa_rt_rule_add_v2 *) + rt_rule->rules)[0].rule.dst = IPA_CLIENT_USB_CONS; + ((struct ipa_rt_rule_add_v2 *) + rt_rule->rules)[0].rule.attrib.attrib_mask = IPA_FLT_DST_PORT; + ((struct ipa_rt_rule_add_v2 *) + rt_rule->rules)[0].rule.attrib.dst_port = 5002; + ((struct ipa_rt_rule_add_v2 *) + rt_rule->rules)[0].rule.hashable = true; + ctx->rt4_usb_cnt_id = counter->hw_counter.start_id; + IPA_UT_INFO("rt4_usb_cnt_id %u\n", ctx->rt4_usb_cnt_id); + ((struct ipa_rt_rule_add_v2 *) + rt_rule->rules)[0].rule.cnt_idx = ctx->rt4_usb_cnt_id; + ((struct ipa_rt_rule_add_v2 *) + rt_rule->rules)[0].rule.enable_stats = true; + if (ipa3_add_rt_rule_v2(rt_rule) || ((struct ipa_rt_rule_add_v2 *) + rt_rule->rules)[0].status) { + IPA_UT_ERR("failed to install V4 rules\n"); + ret = -EFAULT; + goto free_query; + } + if (ipa3_get_rt_tbl(&rt_lookup)) { + IPA_UT_ERR("failed to query V4 rules\n"); + ret = -EFAULT; + goto free_query; + } + ctx->rt4_usb = rt_lookup.hdl; + + rt_rule->commit = 1; + rt_rule->ip = IPA_IP_v6; + rt_lookup.ip = rt_rule->ip; + strlcpy(rt_rule->rt_tbl_name, "V6_RT_TO_USB_CONS", + IPA_RESOURCE_NAME_MAX); + strlcpy(rt_lookup.name, rt_rule->rt_tbl_name, IPA_RESOURCE_NAME_MAX); + rt_rule->num_rules = 1; + ((struct ipa_rt_rule_add_v2 *) + rt_rule->rules)[0].rule.dst = IPA_CLIENT_USB_CONS; + ((struct ipa_rt_rule_add_v2 *) + rt_rule->rules)[0].rule.attrib.attrib_mask = IPA_FLT_DST_PORT; + ((struct ipa_rt_rule_add_v2 *) + rt_rule->rules)[0].rule.attrib.dst_port = 5002; + ((struct ipa_rt_rule_add_v2 *) + rt_rule->rules)[0].rule.hashable = true; + ctx->rt6_usb_cnt_id = counter->hw_counter.start_id + 1; + IPA_UT_INFO("rt6_usb_cnt_id %u\n", ctx->rt6_usb_cnt_id); + ((struct ipa_rt_rule_add_v2 *) + rt_rule->rules)[0].rule.cnt_idx = ctx->rt6_usb_cnt_id; + ((struct ipa_rt_rule_add_v2 *) + rt_rule->rules)[0].rule.enable_stats = true; + if (ipa3_add_rt_rule_v2(rt_rule) || ((struct ipa_rt_rule_add_v2 *) + rt_rule->rules)[0].status) { + IPA_UT_ERR("failed to install V4 rules\n"); + ret = -EFAULT; + goto free_query; + } + if (ipa3_get_rt_tbl(&rt_lookup)) { + IPA_UT_ERR("failed to query V4 rules\n"); + ret = -EFAULT; + goto free_query; + } + ctx->rt6_usb = rt_lookup.hdl; + + rt_rule->commit = 1; + rt_rule->ip = IPA_IP_v4; + rt_lookup.ip = rt_rule->ip; + strlcpy(rt_rule->rt_tbl_name, "V4_RT_TO_ODU_CONS", + IPA_RESOURCE_NAME_MAX); + strlcpy(rt_lookup.name, rt_rule->rt_tbl_name, IPA_RESOURCE_NAME_MAX); + rt_rule->num_rules = 1; + ((struct ipa_rt_rule_add_v2 *) + rt_rule->rules)[0].rule.dst = IPA_CLIENT_ODU_EMB_CONS; + ((struct ipa_rt_rule_add_v2 *) + rt_rule->rules)[0].rule.attrib.attrib_mask = IPA_FLT_DST_PORT; + ((struct ipa_rt_rule_add_v2 *) + rt_rule->rules)[0].rule.attrib.dst_port = 5002; + ((struct ipa_rt_rule_add_v2 *) + rt_rule->rules)[0].rule.hashable = true; + ctx->rt4_odu_cnt_id = counter->hw_counter.start_id + 2; + IPA_UT_INFO("rt4_odu_cnt_id %u\n", ctx->rt4_odu_cnt_id); + ((struct ipa_rt_rule_add_v2 *) + rt_rule->rules)[0].rule.cnt_idx = ctx->rt4_odu_cnt_id; + ((struct ipa_rt_rule_add_v2 *) + rt_rule->rules)[0].rule.enable_stats = true; + if (ipa3_add_rt_rule_v2(rt_rule) || ((struct ipa_rt_rule_add_v2 *) + rt_rule->rules)[0].status) { + IPA_UT_ERR("failed to install V4 rules\n"); + ret = -EFAULT; + goto free_query; + } + if (ipa3_get_rt_tbl(&rt_lookup)) { + IPA_UT_ERR("failed to query V4 rules\n"); + ret = -EFAULT; + goto free_query; + } + ctx->rt4_odu_cons = rt_lookup.hdl; + + rt_rule->commit = 1; + rt_rule->ip = IPA_IP_v6; + rt_lookup.ip = rt_rule->ip; + strlcpy(rt_rule->rt_tbl_name, "V6_RT_TO_ODU_CONS", + IPA_RESOURCE_NAME_MAX); + strlcpy(rt_lookup.name, rt_rule->rt_tbl_name, IPA_RESOURCE_NAME_MAX); + rt_rule->num_rules = 1; + ((struct ipa_rt_rule_add_v2 *) + rt_rule->rules)[0].rule.dst = IPA_CLIENT_ODU_EMB_CONS; + ((struct ipa_rt_rule_add_v2 *) + rt_rule->rules)[0].rule.attrib.attrib_mask = IPA_FLT_DST_PORT; + ((struct ipa_rt_rule_add_v2 *) + rt_rule->rules)[0].rule.attrib.dst_port = 5002; + ((struct ipa_rt_rule_add_v2 *) + rt_rule->rules)[0].rule.hashable = true; + ctx->rt6_odu_cnt_id = counter->hw_counter.start_id + 3; + IPA_UT_INFO("rt6_odu_cnt_id %u\n", ctx->rt6_odu_cnt_id); + ((struct ipa_rt_rule_add_v2 *) + rt_rule->rules)[0].rule.cnt_idx = ctx->rt6_odu_cnt_id; + ((struct ipa_rt_rule_add_v2 *) + rt_rule->rules)[0].rule.enable_stats = true; + if (ipa3_add_rt_rule_v2(rt_rule) || ((struct ipa_rt_rule_add_v2 *) + rt_rule->rules)[0].status) { + IPA_UT_ERR("failed to install V4 rules\n"); + ret = -EFAULT; + goto free_query; + } + if (ipa3_get_rt_tbl(&rt_lookup)) { + IPA_UT_ERR("failed to query V4 rules\n"); + ret = -EFAULT; + goto free_query; + } + ctx->rt6_odu_cons = rt_lookup.hdl; + + flt_rule->commit = 1; + flt_rule->ip = IPA_IP_v4; + flt_rule->ep = IPA_CLIENT_USB_PROD; + flt_rule->num_rules = 1; + ((struct ipa_flt_rule_add_v2 *) + flt_rule->rules)[0].at_rear = 0; + ((struct ipa_flt_rule_add_v2 *) + flt_rule->rules)[0].rule.action = IPA_PASS_TO_ROUTING; + ((struct ipa_flt_rule_add_v2 *) + flt_rule->rules)[0].rule.attrib.attrib_mask = IPA_FLT_DST_PORT; + ((struct ipa_flt_rule_add_v2 *) + flt_rule->rules)[0].rule.attrib.dst_port = 5002; + ((struct ipa_flt_rule_add_v2 *) + flt_rule->rules)[0].rule.rt_tbl_hdl = ctx->rt4_odu_cons; + ((struct ipa_flt_rule_add_v2 *) + flt_rule->rules)[0].rule.hashable = 1; + ctx->flt4_usb_cnt_id = counter->hw_counter.start_id + 4; + IPA_UT_INFO("flt4_usb_cnt_id %u\n", ctx->flt4_usb_cnt_id); + ((struct ipa_flt_rule_add_v2 *) + flt_rule->rules)[0].rule.cnt_idx = ctx->flt4_usb_cnt_id; + ((struct ipa_flt_rule_add_v2 *) + flt_rule->rules)[0].rule.enable_stats = true; + if (ipa3_add_flt_rule_v2(flt_rule) || ((struct ipa_flt_rule_add_v2 *) + flt_rule->rules)[0].status) { + IPA_UT_ERR("failed to install V4 rules\n"); + ret = -EFAULT; + goto free_query; + } + + flt_rule->commit = 1; + flt_rule->ip = IPA_IP_v6; + flt_rule->ep = IPA_CLIENT_USB_PROD; + flt_rule->num_rules = 1; + ((struct ipa_flt_rule_add_v2 *) + flt_rule->rules)[0].at_rear = 0; + ((struct ipa_flt_rule_add_v2 *) + flt_rule->rules)[0].rule.action = IPA_PASS_TO_ROUTING; + ((struct ipa_flt_rule_add_v2 *) + flt_rule->rules)[0].rule.attrib.attrib_mask = IPA_FLT_DST_PORT; + ((struct ipa_flt_rule_add_v2 *) + flt_rule->rules)[0].rule.attrib.dst_port = 5002; + ((struct ipa_flt_rule_add_v2 *) + flt_rule->rules)[0].rule.rt_tbl_hdl = ctx->rt6_odu_cons; + ((struct ipa_flt_rule_add_v2 *) + flt_rule->rules)[0].rule.hashable = 1; + ctx->flt6_usb_cnt_id = counter->hw_counter.start_id + 5; + IPA_UT_INFO("flt6_usb_cnt_id %u\n", ctx->flt6_usb_cnt_id); + ((struct ipa_flt_rule_add_v2 *) + flt_rule->rules)[0].rule.cnt_idx = ctx->flt6_usb_cnt_id; + ((struct ipa_flt_rule_add_v2 *) + flt_rule->rules)[0].rule.enable_stats = true; + if (ipa3_add_flt_rule_v2(flt_rule) || ((struct ipa_flt_rule_add_v2 *) + flt_rule->rules)[0].status) { + IPA_UT_ERR("failed to install V6 rules\n"); + ret = -EFAULT; + goto free_query; + } + + flt_rule->commit = 1; + flt_rule->ip = IPA_IP_v4; + flt_rule->ep = IPA_CLIENT_ODU_PROD; + flt_rule->num_rules = 1; + ((struct ipa_flt_rule_add_v2 *) + flt_rule->rules)[0].at_rear = 0; + ((struct ipa_flt_rule_add_v2 *) + flt_rule->rules)[0].rule.action = IPA_PASS_TO_ROUTING; + ((struct ipa_flt_rule_add_v2 *) + flt_rule->rules)[0].rule.attrib.attrib_mask = IPA_FLT_DST_PORT; + ((struct ipa_flt_rule_add_v2 *) + flt_rule->rules)[0].rule.attrib.dst_port = 5002; + ((struct ipa_flt_rule_add_v2 *) + flt_rule->rules)[0].rule.rt_tbl_hdl = ctx->rt4_usb; + ((struct ipa_flt_rule_add_v2 *) + flt_rule->rules)[0].rule.hashable = 1; + ctx->flt4_odu_cnt_id = counter->hw_counter.start_id + 6; + IPA_UT_INFO("flt4_odu_cnt_id %u\n", ctx->flt4_odu_cnt_id); + ((struct ipa_flt_rule_add_v2 *) + flt_rule->rules)[0].rule.cnt_idx = ctx->flt4_odu_cnt_id; + ((struct ipa_flt_rule_add_v2 *) + flt_rule->rules)[0].rule.enable_stats = true; + if (ipa3_add_flt_rule_v2(flt_rule) || ((struct ipa_flt_rule_add_v2 *) + flt_rule->rules)[0].status) { + IPA_UT_ERR("failed to install V4 rules\n"); + ret = -EFAULT; + goto free_query; + } + + flt_rule->commit = 1; + flt_rule->ip = IPA_IP_v6; + flt_rule->ep = IPA_CLIENT_ODU_PROD; + flt_rule->num_rules = 1; + ((struct ipa_flt_rule_add_v2 *) + flt_rule->rules)[0].at_rear = 0; + ((struct ipa_flt_rule_add_v2 *) + flt_rule->rules)[0].rule.action = IPA_PASS_TO_ROUTING; + ((struct ipa_flt_rule_add_v2 *) + flt_rule->rules)[0].rule.attrib.attrib_mask = IPA_FLT_DST_PORT; + ((struct ipa_flt_rule_add_v2 *) + flt_rule->rules)[0].rule.attrib.dst_port = 5002; + ((struct ipa_flt_rule_add_v2 *) + flt_rule->rules)[0].rule.rt_tbl_hdl = ctx->rt6_usb; + ((struct ipa_flt_rule_add_v2 *) + flt_rule->rules)[0].rule.hashable = 1; + ctx->flt6_odu_cnt_id = counter->hw_counter.start_id + 7; + IPA_UT_INFO("flt4_odu_cnt_id %u\n", ctx->flt6_odu_cnt_id); + ((struct ipa_flt_rule_add_v2 *) + flt_rule->rules)[0].rule.cnt_idx = ctx->flt6_odu_cnt_id; + ((struct ipa_flt_rule_add_v2 *) + flt_rule->rules)[0].rule.enable_stats = true; + if (ipa3_add_flt_rule_v2(flt_rule) || ((struct ipa_flt_rule_add_v2 *) + flt_rule->rules)[0].status) { + IPA_UT_ERR("failed to install V6 rules\n"); + ret = -EFAULT; + goto free_query; + } + IPA_UT_INFO( + "Rules added. Please start data transfer on ports 5001/5002\n"); + ret = 0; + +free_query: + kfree((void *)(query->stats)); + kfree(query); +free_counter: + kfree(counter); +free_flt: + kfree((void *)(flt_rule->rules)); + kfree(flt_rule); +free_rt: + kfree((void *)(rt_rule->rules)); + kfree(rt_rule); + return ret; +} + +static int ipa_test_hw_stats_query_FnR_one_by_one(void *priv) +{ + int ret; + struct ipa_ioc_flt_rt_query *query; + int pyld_size = 0; + + query = kzalloc(sizeof(struct ipa_ioc_flt_rt_query), GFP_KERNEL); + if (!query) + return -ENOMEM; + pyld_size = IPA_MAX_FLT_RT_CNT_INDEX * + sizeof(struct ipa_flt_rt_stats); + query->stats = (uint64_t)kzalloc(pyld_size, GFP_KERNEL); + if (!query->stats) { + kfree(query); + return -ENOMEM; + } + /* query 1 by 1 */ + IPA_UT_INFO("========query 1 by 1========\n"); + query->start_id = ctx->rt4_usb_cnt_id; + query->end_id = ctx->rt4_usb_cnt_id; + ipa_get_flt_rt_stats(query); + IPA_UT_INFO( + "usb v4 route counter %u pkt_cnt %u bytes cnt %llu\n", + ctx->rt4_usb_cnt_id, ((struct ipa_flt_rt_stats *) + query->stats)[0].num_pkts, + ((struct ipa_flt_rt_stats *) + query->stats)[0].num_bytes); + + query->start_id = ctx->rt6_usb_cnt_id; + query->end_id = ctx->rt6_usb_cnt_id; + ipa_get_flt_rt_stats(query); + IPA_UT_INFO( + "usb v6 route counter %u pkt_cnt %u bytes cnt %llu\n", + ctx->rt6_usb_cnt_id, ((struct ipa_flt_rt_stats *) + query->stats)[0].num_pkts, + ((struct ipa_flt_rt_stats *) + query->stats)[0].num_bytes); + + query->start_id = ctx->rt4_odu_cnt_id; + query->end_id = ctx->rt4_odu_cnt_id; + ipa_get_flt_rt_stats(query); + IPA_UT_INFO( + "odu v4 route counter %u pkt_cnt %u bytes cnt %llu\n", + ctx->rt4_odu_cnt_id, ((struct ipa_flt_rt_stats *) + query->stats)[0].num_pkts, + ((struct ipa_flt_rt_stats *) + query->stats)[0].num_bytes); + + query->start_id = ctx->rt6_odu_cnt_id; + query->end_id = ctx->rt6_odu_cnt_id; + ipa_get_flt_rt_stats(query); + IPA_UT_INFO( + "odu v6 route counter %u pkt_cnt %u bytes cnt %llu\n", + ctx->rt6_odu_cnt_id, ((struct ipa_flt_rt_stats *) + query->stats)[0].num_pkts, + ((struct ipa_flt_rt_stats *) + query->stats)[0].num_bytes); + + query->start_id = ctx->flt4_usb_cnt_id; + query->end_id = ctx->flt4_usb_cnt_id; + ipa_get_flt_rt_stats(query); + IPA_UT_INFO( + "usb v4 filter counter %u pkt_cnt %u bytes cnt %llu\n", + ctx->flt4_usb_cnt_id, ((struct ipa_flt_rt_stats *) + query->stats)[0].num_pkts, + ((struct ipa_flt_rt_stats *) + query->stats)[0].num_bytes); + + query->start_id = ctx->flt6_usb_cnt_id; + query->end_id = ctx->flt6_usb_cnt_id; + ipa_get_flt_rt_stats(query); + IPA_UT_INFO( + "usb v6 filter counter %u pkt_cnt %u bytes cnt %llu\n", + ctx->flt6_usb_cnt_id, ((struct ipa_flt_rt_stats *) + query->stats)[0].num_pkts, + ((struct ipa_flt_rt_stats *) + query->stats)[0].num_bytes); + + query->start_id = ctx->flt4_odu_cnt_id; + query->end_id = ctx->flt4_odu_cnt_id; + ipa_get_flt_rt_stats(query); + IPA_UT_INFO( + "odu v4 filter counter %u pkt_cnt %u bytes cnt %llu\n", + ctx->flt4_odu_cnt_id, ((struct ipa_flt_rt_stats *) + query->stats)[0].num_pkts, + ((struct ipa_flt_rt_stats *) + query->stats)[0].num_bytes); + + query->start_id = ctx->flt6_odu_cnt_id; + query->end_id = ctx->flt6_odu_cnt_id; + ipa_get_flt_rt_stats(query); + IPA_UT_INFO( + "odu v6 filter counter %u pkt_cnt %u bytes cnt %llu\n", + ctx->flt6_odu_cnt_id, ((struct ipa_flt_rt_stats *) + query->stats)[0].num_pkts, + ((struct ipa_flt_rt_stats *) + query->stats)[0].num_bytes); + IPA_UT_INFO("================ done ============\n"); + + ret = 0; + kfree(query); + return ret; +} + +static int ipa_test_hw_stats_query_FnR_one_shot(void *priv) +{ + int ret, i, start = 0; + struct ipa_ioc_flt_rt_query *query; + int pyld_size = 0; + + query = kzalloc(sizeof(struct ipa_ioc_flt_rt_query), GFP_KERNEL); + if (!query) + return -ENOMEM; + pyld_size = IPA_MAX_FLT_RT_CNT_INDEX * + sizeof(struct ipa_flt_rt_stats); + query->stats = (uint64_t)kzalloc(pyld_size, GFP_KERNEL); + if (!query->stats) { + kfree(query); + return -ENOMEM; + } + + /* query all together */ + IPA_UT_INFO("========query all together========\n"); + query->start_id = ctx->rt4_usb_cnt_id; + query->end_id = ctx->flt6_odu_cnt_id; + ipa_get_flt_rt_stats(query); + start = 0; + for (i = ctx->rt4_usb_cnt_id; + i <= ctx->flt6_odu_cnt_id; i++) { + IPA_UT_INFO( + "counter %u pkt_cnt %u bytes cnt %llu\n", + i, ((struct ipa_flt_rt_stats *) + query->stats)[start].num_pkts, + ((struct ipa_flt_rt_stats *) + query->stats)[start].num_bytes); + start++; + } + IPA_UT_INFO("================ done ============\n"); + + ret = 0; + kfree((void *)(query->stats)); + kfree(query); + return ret; +} + +static int ipa_test_hw_stats_query_FnR_clean(void *priv) +{ + int ret, i, start = 0; + struct ipa_ioc_flt_rt_query *query; + int pyld_size = 0; + + query = kzalloc(sizeof(struct ipa_ioc_flt_rt_query), GFP_KERNEL); + if (!query) { + IPA_UT_DBG("no mem\n"); + return -ENOMEM; + } + pyld_size = IPA_MAX_FLT_RT_CNT_INDEX * + sizeof(struct ipa_flt_rt_stats); + query->stats = (uint64_t)kzalloc(pyld_size, GFP_KERNEL); + if (!query->stats) { + kfree(query); + return -ENOMEM; + } + + /* query and reset */ + IPA_UT_INFO("========query and reset========\n"); + query->start_id = ctx->rt4_usb_cnt_id; + query->reset = true; + query->end_id = ctx->flt6_odu_cnt_id; + start = 0; + ipa_get_flt_rt_stats(query); + for (i = ctx->rt4_usb_cnt_id; + i <= ctx->flt6_odu_cnt_id; i++) { + IPA_UT_INFO( + "counter %u pkt_cnt %u bytes cnt %llu\n", + i, ((struct ipa_flt_rt_stats *) + query->stats)[start].num_pkts, + ((struct ipa_flt_rt_stats *) + query->stats)[start].num_bytes); + start++; + } + IPA_UT_INFO("================ done ============\n"); + + ret = 0; + kfree((void *)(query->stats)); + kfree(query); + return ret; +} + + +static int ipa_test_hw_stats_query_sw_stats(void *priv) +{ + int ret, i, start = 0; + struct ipa_ioc_flt_rt_query *query; + int pyld_size = 0; + + query = kzalloc(sizeof(struct ipa_ioc_flt_rt_query), GFP_KERNEL); + if (!query) + return -ENOMEM; + pyld_size = IPA_MAX_FLT_RT_CNT_INDEX * + sizeof(struct ipa_flt_rt_stats); + query->stats = (uint64_t)kzalloc(pyld_size, GFP_KERNEL); + if (!query->stats) { + kfree(query); + return -ENOMEM; + } + + /* query all together */ + IPA_UT_INFO("========query all SW counters========\n"); + query->start_id = IPA_FLT_RT_HW_COUNTER + 1; + query->end_id = IPA_MAX_FLT_RT_CNT_INDEX; + ipa_get_flt_rt_stats(query); + start = 0; + for (i = IPA_FLT_RT_HW_COUNTER + 1; + i <= IPA_MAX_FLT_RT_CNT_INDEX; i++) { + IPA_UT_INFO( + "counter %u pkt_cnt %u bytes cnt %llu\n", + i, ((struct ipa_flt_rt_stats *) + query->stats)[start].num_pkts, + ((struct ipa_flt_rt_stats *) + query->stats)[start].num_bytes); + start++; + } + IPA_UT_INFO("================ done ============\n"); + + ret = 0; + kfree((void *)(query->stats)); + kfree(query); + return ret; +} + +static int ipa_test_hw_stats_set_sw_stats(void *priv) +{ + int i, start = 0; + struct ipa_flt_rt_stats stats; + + /* set sw counters */ + IPA_UT_INFO("========set all SW counters========\n"); + for (i = IPA_FLT_RT_HW_COUNTER + 1; + i <= IPA_MAX_FLT_RT_CNT_INDEX; i++) { + stats.num_bytes = start; + stats.num_pkts_hash = start + 10; + stats.num_pkts = start + 100; + IPA_UT_INFO( + "set counter %u pkt_cnt %u bytes cnt %llu\n", + i, stats.num_pkts, stats.num_bytes); + ipa_set_flt_rt_stats(i, stats); + start++; + } + IPA_UT_INFO("================ done ============\n"); + + return 0; +} + +static int ipa_test_hw_stats_query_drop_stats(void *priv) +{ + int ret, i, ep_idx, reg_idx; + struct ipa_drop_stats_all *query; + + query = kzalloc(sizeof(struct ipa_drop_stats_all), GFP_KERNEL); + if (!query) + return -ENOMEM; + + IPA_UT_INFO("========query all drop stats========\n"); + + ret = ipa_get_drop_stats(query); + if (!ret) + goto fail; + + for (i = 0; i <= IPA_CLIENT_MAX; i++) { + ep_idx = ipa_get_ep_mapping(i); + if (ep_idx == -1 || !IPA_CLIENT_IS_CONS(i) || IPA_CLIENT_IS_TEST(i)) + continue; + + reg_idx = ipahal_get_ep_reg_idx(ep_idx); + if (!(ipa3_ctx->hw_stats->drop.init.enabled_bitmask[reg_idx] & + ipahal_get_ep_bit(ep_idx))) + continue; + + IPA_UT_INFO("Client %u pkt_cnt %u bytes cnt %llu\n", i, + query->client[i].drop_packet_cnt, query->client[i].drop_byte_cnt); + } + + IPA_UT_INFO("================ done ============\n"); + +fail: + kfree(query); + return ret; +} + +static int ipa_test_hw_stats_reset_all_drop_stats(void *priv) +{ + int ret; + + IPA_UT_INFO("========reset all drop stats========\n"); + + ret = ipa_reset_all_drop_stats(); + if (ret) + IPA_UT_ERR("ipa_reset_all_drop_stats failed %d\n", ret); + + IPA_UT_INFO("================ done ============\n"); + + return ret; +} + +static int ipa_test_hw_stats_query_teth_stats(void *priv) +{ + int i, j, prod_reg, cons_reg; + int res; + struct ipa_quota_stats_all *stats; + + stats = kzalloc(sizeof(*stats), GFP_KERNEL); + if (!stats) + return -ENOMEM; + + IPA_UT_INFO("========get all tethering stats========\n"); + res = ipa_get_teth_stats(); + if (res) { + IPA_UT_ERR("ipa_get_teth_stats failed with code %u\n", res); + goto teardown; + } + + for (i = 0; i < IPA_CLIENT_MAX; i++) { + int ep_idx = ipa_get_ep_mapping(i); + + if (ep_idx == -1) + continue; + + if (!IPA_CLIENT_IS_PROD(i)) + continue; + + if (IPA_CLIENT_IS_TEST(i)) + continue; + + prod_reg = ipahal_get_ep_reg_idx(ep_idx); + if (!(ipa3_ctx->hw_stats->teth.init.prod_bitmask[prod_reg] & + ipahal_get_ep_bit(ep_idx))) + continue; + + res = ipa_query_teth_stats(i, stats, false); + if (res) { + IPA_UT_ERR("ipa_query_teth_stats failed with code %u\n", res); + goto teardown; + } + + for (j = 0; j < IPA_CLIENT_MAX; j++) { + int cons_idx = ipa_get_ep_mapping(j); + + if (cons_idx == -1) + continue; + + if (IPA_CLIENT_IS_TEST(j)) + continue; + + cons_reg = ipahal_get_ep_reg_idx(j); + if (!(ipa3_ctx->hw_stats->teth.init. + cons_bitmask[ep_idx][cons_reg] + & ipahal_get_ep_bit(cons_idx))) + continue; + + IPA_UT_INFO("%s->%s:\n", ipa_clients_strings[i], + ipa_clients_strings[j]); + IPA_UT_INFO("num_ipv4_bytes=%llu\n", + stats->client[j].num_ipv4_bytes); + IPA_UT_INFO("num_ipv6_bytes=%llu\n", + stats->client[j].num_ipv6_bytes); + IPA_UT_INFO("num_ipv4_pkts=%u\n", + stats->client[j].num_ipv4_pkts); + IPA_UT_INFO("num_ipv6_pkts=%u\n", + stats->client[j].num_ipv6_pkts); + } + } + + IPA_UT_INFO("================ done ============\n"); + +teardown: + kfree(stats); + return res; +} + +static int ipa_test_hw_stats_reset_teth_stats(void *priv) +{ + int ret; + unsigned int random_int; + enum ipa_client_type prod; + enum ipa_client_type cons; + + get_random_bytes(&random_int, sizeof(random_int)); + prod = (random_int % IPA_CLIENT_MAX) & 0x8FFFFFFE; + + get_random_bytes(&random_int, sizeof(random_int)); + cons = ((random_int % IPA_CLIENT_MAX) & 0x8FFFFFFF) | 0x1; + + IPA_UT_INFO("========reset some tethering stats========\n"); + + ret = ipa_reset_teth_stats(prod, cons); + if (ret) + IPA_UT_ERR("ipa_reset_teth_stats failed %d\n", ret); + + IPA_UT_INFO("================ done ============\n"); + + return ret; +} + +static int ipa_test_hw_stats_query_quota_stats(void *priv) +{ + struct ipa_quota_stats_all *out; + int i, reg_idx, ep_idx; + int res; + + out = kzalloc(sizeof(*out), GFP_KERNEL); + if (!out) + return -ENOMEM; + + IPA_UT_INFO("========get all quota stats========\n"); + + res = ipa_get_quota_stats(out); + if (res) { + IPA_UT_ERR("ipa_get_quota_stats failed with code %u\n", res); + goto teardown; + } + + for (i = 0; i < IPA_CLIENT_MAX; i++) { + ep_idx = ipa_get_ep_mapping(i); + + if (ep_idx == -1) + continue; + + if (IPA_CLIENT_IS_TEST(i)) + continue; + + reg_idx = ipahal_get_ep_reg_idx(ep_idx); + if (!(ipa3_ctx->hw_stats->quota.init.enabled_bitmask[reg_idx] & + ipahal_get_ep_bit(ep_idx))) + continue; + + IPA_UT_INFO("%s:\n", ipa_clients_strings[i]); + IPA_UT_INFO("num_ipv4_bytes=%llu\n", out->client[i].num_ipv4_bytes); + IPA_UT_INFO("num_ipv6_bytes=%llu\n", out->client[i].num_ipv6_bytes); + IPA_UT_INFO("num_ipv4_pkts=%u\n", out->client[i].num_ipv4_pkts); + IPA_UT_INFO("num_ipv6_pkts=%u\n", out->client[i].num_ipv6_pkts); + + } + + IPA_UT_INFO("================ done ============\n"); + +teardown: + kfree(out); + return res; +} + +static int ipa_test_hw_stats_reset_all_quota_stats(void *priv) +{ + int ret; + + IPA_UT_INFO("========reset all drop stats========\n"); + + ret = ipa_reset_all_quota_stats(); + if (ret) + IPA_UT_ERR("ipa_reset_all_quota_stats failed %d\n", ret); + + IPA_UT_INFO("================ done ============\n"); + + return ret; +} + +static int ipa_test_hw_stats_set_uc_event_ring(void *priv) +{ + struct ipa_ioc_flt_rt_counter_alloc *counter = NULL; + int ret = 0; + + /* set uc event ring */ + IPA_UT_INFO("========set uc event ring ========\n"); + + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_5 && + ipa3_ctx->ipa_hw_type != IPA_HW_v4_11 && + ipa3_ctx->ipa_hw_type != IPA_HW_v5_2) { + if (ipa3_ctx->uc_ctx.uc_loaded && + !ipa3_ctx->uc_ctx.uc_event_ring_valid) { + if (ipa3_uc_setup_event_ring()) { + IPA_UT_ERR("failed to set uc_event ring\n"); + ret = -EFAULT; + } + } else + IPA_UT_ERR("uc-loaded %d, ring-valid %d", + ipa3_ctx->uc_ctx.uc_loaded, + ipa3_ctx->uc_ctx.uc_event_ring_valid); + } + IPA_UT_INFO("================ done ============\n"); + + /* allocate counters */ + IPA_UT_INFO("========set hw counter ========\n"); + + counter = kzalloc(sizeof(struct ipa_ioc_flt_rt_counter_alloc), + GFP_KERNEL); + if (!counter) + return -ENOMEM; + + counter->hw_counter.num_counters = 4; + counter->sw_counter.num_counters = 4; + + /* allocate counters */ + ret = ipa3_alloc_counter_id(counter); + if (ret < 0) { + IPA_UT_ERR("ipa3_alloc_counter_id fails\n"); + ret = -ENOMEM; + } + ipa3_ctx->fnr_info.hw_counter_offset = counter->hw_counter.start_id; + ipa3_ctx->fnr_info.sw_counter_offset = counter->sw_counter.start_id; + IPA_UT_INFO("hw-offset %d, sw-offset %d\n", + ipa3_ctx->fnr_info.hw_counter_offset, + ipa3_ctx->fnr_info.sw_counter_offset); + + kfree(counter); + return ret; +} + +static int ipa_test_hw_stats_set_quota(void *priv) +{ + int ret; + uint64_t quota = 500; + + IPA_UT_INFO("========set quota ========\n"); + ret = ipa3_uc_quota_monitor(quota); + if (ret < 0) { + IPA_UT_ERR("ipa3_uc_quota_monitor fails\n"); + ret = -ENOMEM; + } + IPA_UT_INFO("================ done ============\n"); + return ret; +} + +static int ipa_test_hw_stats_set_bw(void *priv) +{ + int ret; + struct ipa_wdi_bw_info *info = NULL; + + IPA_UT_INFO("========set BW voting ========\n"); + info = kzalloc(sizeof(struct ipa_wdi_bw_info), + GFP_KERNEL); + if (!info) + return -ENOMEM; + + info->num = 3; + info->threshold[0] = 200; + info->threshold[1] = 400; + info->threshold[2] = 600; + + ret = ipa_uc_bw_monitor(info); + if (ret < 0) { + IPA_UT_ERR("ipa_uc_bw_monitor fails\n"); + ret = -ENOMEM; + } + + IPA_UT_INFO("================ done ============\n"); + + kfree(info); + return ret; +} +static int ipa_test_hw_stats_hit_quota(void *priv) +{ + int ret = 0, counter_index, i; + struct ipa_flt_rt_stats stats; + + /* set sw counters */ + IPA_UT_INFO("========set quota hit========\n"); + counter_index = ipa3_ctx->fnr_info.sw_counter_offset + UL_WLAN_TX; + + for (i = 0; i < 5; i++) { + IPA_UT_INFO("========set 100 ========\n"); + memset(&stats, 0, sizeof(struct ipa_flt_rt_stats)); + stats.num_bytes = 100; + stats.num_pkts = 69; + IPA_UT_INFO( + "set counter %u pkt_cnt %u bytes cnt %llu\n", + counter_index, stats.num_pkts, stats.num_bytes); + ret = ipa_set_flt_rt_stats(counter_index, stats); + if (ret < 0) { + IPA_UT_ERR("ipa_set_flt_rt_stats fails\n"); + ret = -ENOMEM; + } + msleep(1000); + IPA_UT_INFO("========set 200 ========\n"); + memset(&stats, 0, sizeof(struct ipa_flt_rt_stats)); + stats.num_bytes = 200; + stats.num_pkts = 69; + IPA_UT_INFO( + "set counter %u pkt_cnt %u bytes cnt %llu\n", + counter_index, stats.num_pkts, stats.num_bytes); + ret = ipa_set_flt_rt_stats(counter_index, stats); + if (ret < 0) { + IPA_UT_ERR("ipa_set_flt_rt_stats fails\n"); + ret = -ENOMEM; + } + msleep(1000); + IPA_UT_INFO("========set 300 ========\n"); + memset(&stats, 0, sizeof(struct ipa_flt_rt_stats)); + stats.num_bytes = 300; + stats.num_pkts = 69; + IPA_UT_INFO( + "set counter %u pkt_cnt %u bytes cnt %llu\n", + counter_index, stats.num_pkts, stats.num_bytes); + ret = ipa_set_flt_rt_stats(counter_index, stats); + if (ret < 0) { + IPA_UT_ERR("ipa_set_flt_rt_stats fails\n"); + ret = -ENOMEM; + } + msleep(1000); + IPA_UT_INFO("========set 500 ========\n"); + memset(&stats, 0, sizeof(struct ipa_flt_rt_stats)); + stats.num_bytes = 500; + stats.num_pkts = 69; + IPA_UT_INFO( + "set counter %u pkt_cnt %u bytes cnt %llu\n", + counter_index, stats.num_pkts, stats.num_bytes); + ret = ipa_set_flt_rt_stats(counter_index, stats); + if (ret < 0) { + IPA_UT_ERR("ipa_set_flt_rt_stats fails\n"); + ret = -ENOMEM; + } + msleep(1000); + IPA_UT_INFO("========set 600 ========\n"); + memset(&stats, 0, sizeof(struct ipa_flt_rt_stats)); + stats.num_bytes = 600; + stats.num_pkts = 69; + IPA_UT_INFO( + "set counter %u pkt_cnt %u bytes cnt %llu\n", + counter_index, stats.num_pkts, stats.num_bytes); + ret = ipa_set_flt_rt_stats(counter_index, stats); + if (ret < 0) { + IPA_UT_ERR("ipa_set_flt_rt_stats fails\n"); + ret = -ENOMEM; + } + msleep(1000); + IPA_UT_INFO("========set 1000 ========\n"); + memset(&stats, 0, sizeof(struct ipa_flt_rt_stats)); + stats.num_bytes = 1000; + stats.num_pkts = 69; + IPA_UT_INFO( + "set counter %u pkt_cnt %u bytes cnt %llu\n", + counter_index, stats.num_pkts, stats.num_bytes); + ret = ipa_set_flt_rt_stats(counter_index, stats); + if (ret < 0) { + IPA_UT_ERR("ipa_set_flt_rt_stats fails\n"); + ret = -ENOMEM; + } + } + IPA_UT_INFO("================ done ============\n"); + return ret; +} + + + +/* Suite definition block */ +IPA_UT_DEFINE_SUITE_START(hw_stats, "HW stats test", + ipa_test_hw_stats_suite_setup, ipa_test_hw_stats_suite_teardown) +{ + IPA_UT_ADD_TEST(configure, "Configure the setup", + ipa_test_hw_stats_configure, false, IPA_HW_v4_0, IPA_HW_MAX), + + IPA_UT_ADD_TEST(add_rules, "Add FLT and RT rules", + ipa_test_hw_stats_add_FnR, false, IPA_HW_v4_5, IPA_HW_MAX), + + IPA_UT_ADD_TEST(query_stats_one_by_one, "Query one by one", + ipa_test_hw_stats_query_FnR_one_by_one, false, + IPA_HW_v4_5, IPA_HW_MAX), + + IPA_UT_ADD_TEST(query_stats_one_shot, "Query one shot", + ipa_test_hw_stats_query_FnR_one_shot, false, + IPA_HW_v4_5, IPA_HW_MAX), + + IPA_UT_ADD_TEST(query_stats_one_shot_clean, "Query and clean", + ipa_test_hw_stats_query_FnR_clean, false, + IPA_HW_v4_5, IPA_HW_MAX), + + IPA_UT_ADD_TEST(query_sw_stats, "Query SW stats", + ipa_test_hw_stats_query_sw_stats, false, + IPA_HW_v4_5, IPA_HW_MAX), + + IPA_UT_ADD_TEST(set_sw_stats, "Set SW stats to dummy values", + ipa_test_hw_stats_set_sw_stats, false, + IPA_HW_v4_5, IPA_HW_MAX), + + IPA_UT_ADD_TEST(query_drop_stats, "Query drop stats", + ipa_test_hw_stats_query_drop_stats, false, + IPA_HW_v4_5, IPA_HW_MAX), + + IPA_UT_ADD_TEST(reset_drop_stats, "Reset drop stats", + ipa_test_hw_stats_reset_all_drop_stats, false, + IPA_HW_v4_5, IPA_HW_MAX), + + IPA_UT_ADD_TEST(query_teth_stats, "Query tethering stats", + ipa_test_hw_stats_query_teth_stats, false, + IPA_HW_v4_5, IPA_HW_MAX), + + IPA_UT_ADD_TEST(reset_teth_stats, "Reset tethering stats", + ipa_test_hw_stats_reset_teth_stats, false, + IPA_HW_v4_5, IPA_HW_MAX), + + IPA_UT_ADD_TEST(query_quota_stats, "Query quota stats", + ipa_test_hw_stats_query_quota_stats, false, + IPA_HW_v4_5, IPA_HW_MAX), + + IPA_UT_ADD_TEST(reset_quota_stats, "Reset quota stats", + ipa_test_hw_stats_reset_all_quota_stats, false, + IPA_HW_v4_5, IPA_HW_MAX), + + IPA_UT_ADD_TEST(set_uc_evtring, "Set uc event ring", + ipa_test_hw_stats_set_uc_event_ring, false, + IPA_HW_v4_5, IPA_HW_MAX), + + IPA_UT_ADD_TEST(set_quota, "Set quota", + ipa_test_hw_stats_set_quota, false, + IPA_HW_v4_5, IPA_HW_MAX), + + IPA_UT_ADD_TEST(set_bw_voting, "Set bw_voting", + ipa_test_hw_stats_set_bw, false, + IPA_HW_v4_5, IPA_HW_MAX), + + IPA_UT_ADD_TEST(hit_quota, "quota hits", + ipa_test_hw_stats_hit_quota, false, + IPA_HW_v4_5, IPA_HW_MAX), + +} IPA_UT_DEFINE_SUITE_END(hw_stats); diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/test/ipa_test_mhi.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/test/ipa_test_mhi.c new file mode 100644 index 0000000000..65919333a6 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/test/ipa_test_mhi.c @@ -0,0 +1,3340 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. + */ + +#include +#include "ipa.h" +#include "ipa_i.h" +#include "gsi.h" +#include "gsihal.h" +#include "ipa_ut_framework.h" +#include + +#define IPA_MHI_TEST_NUM_CHANNELS 8 +#define IPA_MHI_TEST_NUM_EVENT_RINGS 8 +#define IPA_MHI_TEST_FIRST_CHANNEL_ID 100 +#define IPA_MHI_TEST_FIRST_EVENT_RING_ID 100 +#define IPA_MHI_TEST_LAST_CHANNEL_ID \ + (IPA_MHI_TEST_FIRST_CHANNEL_ID + IPA_MHI_TEST_NUM_CHANNELS - 1) +#define IPA_MHI_TEST_LAST_EVENT_RING_ID \ + (IPA_MHI_TEST_FIRST_EVENT_RING_ID + IPA_MHI_TEST_NUM_EVENT_RINGS - 1) +#define IPA_MHI_TEST_MAX_DATA_BUF_SIZE 1500 +#define IPA_MHI_TEST_SEQ_TYPE_DMA 0x00000000 + +#define IPA_MHI_TEST_LOOP_NUM 5 +#define IPA_MHI_RUN_TEST_UNIT_IN_LOOP(test_unit, rc, args...) \ + do { \ + int __i; \ + for (__i = 0; __i < IPA_MHI_TEST_LOOP_NUM; __i++) { \ + IPA_UT_LOG(#test_unit " START iter %d\n", __i); \ + rc = test_unit(args); \ + if (!rc) \ + continue; \ + IPA_UT_LOG(#test_unit " failed %d\n", rc); \ + break; \ + } \ + } while (0) + +static char *ipa_mhi_state_str[] = { + __stringify(IPA_MHI_STATE_INITIALIZED), + __stringify(IPA_MHI_STATE_READY), + __stringify(IPA_MHI_STATE_STARTED), + __stringify(IPA_MHI_STATE_SUSPEND_IN_PROGRESS), + __stringify(IPA_MHI_STATE_SUSPENDED), + __stringify(IPA_MHI_STATE_RESUME_IN_PROGRESS), +}; + +#define MHI_STATE_STR(state) \ + (((state) >= 0 && (state) < IPA_MHI_STATE_MAX) ? \ + ipa_mhi_state_str[(state)] : \ + "INVALID") + +/** + * check for MSI interrupt for one or both channels: + * OUT channel MSI my be missed as it + * will be overwritten by the IN channel MSI + */ +#define IPA_MHI_TEST_CHECK_MSI_INTR(__both, __timeout) \ + do { \ + int i; \ + for (i = 0; i < 20; i++) { \ + if (*((u32 *)test_mhi_ctx->msi.base) == \ + (0x10000000 | \ + (IPA_MHI_TEST_FIRST_EVENT_RING_ID + 1))) { \ + __timeout = false; \ + break; \ + } \ + if (__both && (*((u32 *)test_mhi_ctx->msi.base) == \ + (0x10000000 | \ + (IPA_MHI_TEST_FIRST_EVENT_RING_ID)))) { \ + /* sleep to be sure IN MSI is generated */ \ + msleep(20); \ + __timeout = false; \ + break; \ + } \ + msleep(20); \ + } \ + } while (0) + +static DECLARE_COMPLETION(mhi_test_ready_comp); +static DECLARE_COMPLETION(mhi_test_wakeup_comp); + +/** + * enum ipa_mhi_ring_elements_type - MHI ring elements types. + */ +enum ipa_mhi_ring_elements_type { + IPA_MHI_RING_ELEMENT_NO_OP = 1, + IPA_MHI_RING_ELEMENT_TRANSFER = 2 +}; + +/** + * enum ipa_mhi_channel_direction - MHI channel directions + */ +enum ipa_mhi_channel_direction { + IPA_MHI_OUT_CHAHNNEL = 1, + IPA_MHI_IN_CHAHNNEL = 2, +}; + +/** + * struct ipa_mhi_channel_context_array - MHI Channel context array entry + * + * mapping is taken from MHI spec + */ +struct ipa_mhi_channel_context_array { + u32 chstate:8; /*0-7*/ + u32 brsmode:2; /*8-9*/ + u32 pollcfg:6; /*10-15*/ + u32 reserved:16; /*16-31*/ + u32 chtype; /*channel type (inbound/outbound)*/ + u32 erindex; /*event ring index*/ + u64 rbase; /*ring base address in the host addr spc*/ + u64 rlen; /*ring length in bytes*/ + u64 rp; /*read pointer in the host system addr spc*/ + u64 wp; /*write pointer in the host system addr spc*/ +} __packed; + +/** + * struct ipa_mhi_event_context_array - MGI event ring context array entry + * + * mapping is taken from MHI spec + */ +struct ipa_mhi_event_context_array { + u16 intmodc; + u16 intmodt;/* Interrupt moderation timer (in microseconds) */ + u32 ertype; + u32 msivec; /* MSI vector for interrupt (MSI data)*/ + u64 rbase; /* ring base address in host address space*/ + u64 rlen; /* ring length in bytes*/ + u64 rp; /* read pointer in the host system address space*/ + u64 wp; /* write pointer in the host system address space*/ +} __packed; + +/** + * + * struct ipa_mhi_mmio_register_set - MHI configuration registers, + * control registers, status registers, pointers to doorbell arrays, + * pointers to channel and event context arrays. + * + * The structure is defined in mhi spec (register names are taken from there). + * Only values accessed by HWP or test are documented + */ +struct ipa_mhi_mmio_register_set { + u32 mhireglen; + u32 reserved_08_04; + u32 mhiver; + u32 reserved_10_0c; + struct mhicfg { + u8 nch; + u8 reserved_15_8; + u8 ner; + u8 reserved_31_23; + } __packed mhicfg; + + u32 reserved_18_14; + u32 chdboff; + u32 reserved_20_1C; + u32 erdboff; + u32 reserved_28_24; + u32 bhioff; + u32 reserved_30_2C; + u32 debugoff; + u32 reserved_38_34; + + struct mhictrl { + u32 rs : 1; + u32 reset : 1; + u32 reserved_7_2 : 6; + u32 mhistate : 8; + u32 reserved_31_16 : 16; + } __packed mhictrl; + + u64 reserved_40_3c; + u32 reserved_44_40; + + struct mhistatus { + u32 ready : 1; + u32 reserved_3_2 : 1; + u32 syserr : 1; + u32 reserved_7_3 : 5; + u32 mhistate : 8; + u32 reserved_31_16 : 16; + } __packed mhistatus; + + /** + * Register is not accessed by HWP. + * In test register carries the handle for + * the buffer of channel context array + */ + u32 reserved_50_4c; + + u32 mhierror; + + /** + * Register is not accessed by HWP. + * In test register carries the handle for + * the buffer of event ring context array + */ + u32 reserved_58_54; + + /** + * 64-bit pointer to the channel context array in the host memory space + * host sets the pointer to the channel context array during + * initialization. + */ + u64 ccabap; + /** + * 64-bit pointer to the event context array in the host memory space + * host sets the pointer to the event context array during + * initialization + */ + u64 ecabap; + /** + * Register is not accessed by HWP. + * In test register carries the pointer of virtual address + * for the buffer of channel context array + */ + u64 crcbap; + /** + * Register is not accessed by HWP. + * In test register carries the pointer of virtual address + * for the buffer of event ring context array + */ + u64 crdb; + + u64 reserved_80_78; + + struct mhiaddr { + /** + * Base address (64-bit) of the memory region in + * the host address space where the MHI control + * data structures are allocated by the host, + * including channel context array, event context array, + * and rings. + * The device uses this information to set up its internal + * address translation tables. + * value must be aligned to 4 Kbytes. + */ + u64 mhicrtlbase; + /** + * Upper limit address (64-bit) of the memory region in + * the host address space where the MHI control + * data structures are allocated by the host. + * The device uses this information to setup its internal + * address translation tables. + * The most significant 32 bits of MHICTRLBASE and + * MHICTRLLIMIT registers must be equal. + */ + u64 mhictrllimit; + u64 reserved_18_10; + /** + * Base address (64-bit) of the memory region in + * the host address space where the MHI data buffers + * are allocated by the host. + * The device uses this information to setup its + * internal address translation tables. + * value must be aligned to 4 Kbytes. + */ + u64 mhidatabase; + /** + * Upper limit address (64-bit) of the memory region in + * the host address space where the MHI data buffers + * are allocated by the host. + * The device uses this information to setup its + * internal address translation tables. + * The most significant 32 bits of MHIDATABASE and + * MHIDATALIMIT registers must be equal. + */ + u64 mhidatalimit; + u64 reserved_30_28; + } __packed mhiaddr; + +} __packed; + +/** + * struct ipa_mhi_event_ring_element - MHI Event ring element + * + * mapping is taken from MHI spec + */ +struct ipa_mhi_event_ring_element { + /** + * pointer to ring element that generated event in + * the host system address space + */ + u64 ptr; + union { + struct { + u32 len : 24; + u32 code : 8; + } __packed bits; + u32 dword; + } __packed dword_8; + u16 reserved; + u8 type; + u8 chid; +} __packed; + +/** + * struct ipa_mhi_transfer_ring_element - MHI Transfer ring element + * + * mapping is taken from MHI spec + */ +struct ipa_mhi_transfer_ring_element { + u64 ptr; /*pointer to buffer in the host system address space*/ + u16 len; /*transaction length in bytes*/ + u16 reserved0; + union { + struct { + u16 chain : 1; + u16 reserved_7_1 : 7; + u16 ieob : 1; + u16 ieot : 1; + u16 bei : 1; + u16 reserved_15_11 : 5; + } __packed bits; + u16 word; + } __packed word_C; + u8 type; + u8 reserved1; +} __packed; + +/** + * struct ipa_test_mhi_context - MHI test context + */ +struct ipa_test_mhi_context { + struct ipa_mem_buffer msi; + struct ipa_mem_buffer ch_ctx_array; + struct ipa_mem_buffer ev_ctx_array; + struct ipa_mem_buffer mmio_buf; + struct ipa_mem_buffer xfer_ring_bufs[IPA_MHI_TEST_NUM_CHANNELS]; + struct ipa_mem_buffer ev_ring_bufs[IPA_MHI_TEST_NUM_EVENT_RINGS]; + struct ipa_mem_buffer in_buffer; + struct ipa_mem_buffer out_buffer; + u32 prod_hdl; + u32 cons_hdl; + u32 test_prod_hdl; + phys_addr_t transport_phys_addr; + unsigned long transport_size; +}; + +static struct ipa_test_mhi_context *test_mhi_ctx; + +static void ipa_mhi_test_cb(void *priv, + enum ipa_mhi_event_type event, unsigned long data) +{ + IPA_UT_DBG("Entry\n"); + + if (event == IPA_MHI_EVENT_DATA_AVAILABLE) + complete_all(&mhi_test_wakeup_comp); + else if (event == IPA_MHI_EVENT_READY) + complete_all(&mhi_test_ready_comp); + else + WARN_ON(1); +} + +static void ipa_test_mhi_free_mmio_space(void) +{ + IPA_UT_DBG("Entry\n"); + + if (!test_mhi_ctx) + return; + + dma_free_coherent(ipa3_ctx->pdev, test_mhi_ctx->mmio_buf.size, + test_mhi_ctx->mmio_buf.base, + test_mhi_ctx->mmio_buf.phys_base); + + dma_free_coherent(ipa3_ctx->pdev, test_mhi_ctx->ev_ctx_array.size, + test_mhi_ctx->ev_ctx_array.base, + test_mhi_ctx->ev_ctx_array.phys_base); + + dma_free_coherent(ipa3_ctx->pdev, test_mhi_ctx->ch_ctx_array.size, + test_mhi_ctx->ch_ctx_array.base, + test_mhi_ctx->ch_ctx_array.phys_base); + + dma_free_coherent(ipa3_ctx->pdev, test_mhi_ctx->msi.size, + test_mhi_ctx->msi.base, test_mhi_ctx->msi.phys_base); +} + +static int ipa_test_mhi_alloc_mmio_space(void) +{ + int rc = 0; + struct ipa_mem_buffer *msi; + struct ipa_mem_buffer *ch_ctx_array; + struct ipa_mem_buffer *ev_ctx_array; + struct ipa_mem_buffer *mmio_buf; + struct ipa_mhi_mmio_register_set *p_mmio; + + IPA_UT_DBG("Entry\n"); + + msi = &test_mhi_ctx->msi; + ch_ctx_array = &test_mhi_ctx->ch_ctx_array; + ev_ctx_array = &test_mhi_ctx->ev_ctx_array; + mmio_buf = &test_mhi_ctx->mmio_buf; + + /* Allocate MSI */ + msi->size = 4; + msi->base = dma_alloc_coherent(ipa3_ctx->pdev, msi->size, + &msi->phys_base, GFP_KERNEL); + if (!msi->base) { + IPA_UT_ERR("no mem for msi\n"); + return -ENOMEM; + } + + IPA_UT_DBG("msi: base 0x%pK phys_addr 0x%pad size %d\n", + msi->base, &msi->phys_base, msi->size); + + /* allocate buffer for channel context */ + ch_ctx_array->size = sizeof(struct ipa_mhi_channel_context_array) * + IPA_MHI_TEST_NUM_CHANNELS; + ch_ctx_array->base = dma_alloc_coherent(ipa3_ctx->pdev, + ch_ctx_array->size, &ch_ctx_array->phys_base, GFP_KERNEL); + if (!ch_ctx_array->base) { + IPA_UT_ERR("no mem for ch ctx array\n"); + rc = -ENOMEM; + goto fail_free_msi; + } + IPA_UT_DBG("channel ctx array: base 0x%pK phys_addr %pad size %d\n", + ch_ctx_array->base, &ch_ctx_array->phys_base, + ch_ctx_array->size); + + /* allocate buffer for event context */ + ev_ctx_array->size = sizeof(struct ipa_mhi_event_context_array) * + IPA_MHI_TEST_NUM_EVENT_RINGS; + ev_ctx_array->base = dma_alloc_coherent(ipa3_ctx->pdev, + ev_ctx_array->size, &ev_ctx_array->phys_base, GFP_KERNEL); + if (!ev_ctx_array->base) { + IPA_UT_ERR("no mem for ev ctx array\n"); + rc = -ENOMEM; + goto fail_free_ch_ctx_arr; + } + IPA_UT_DBG("event ctx array: base 0x%pK phys_addr %pad size %d\n", + ev_ctx_array->base, &ev_ctx_array->phys_base, + ev_ctx_array->size); + + /* allocate buffer for mmio */ + mmio_buf->size = sizeof(struct ipa_mhi_mmio_register_set); + mmio_buf->base = dma_alloc_coherent(ipa3_ctx->pdev, mmio_buf->size, + &mmio_buf->phys_base, GFP_KERNEL); + if (!mmio_buf->base) { + IPA_UT_ERR("no mem for mmio buf\n"); + rc = -ENOMEM; + goto fail_free_ev_ctx_arr; + } + IPA_UT_DBG("mmio buffer: base 0x%pK phys_addr %pad size %d\n", + mmio_buf->base, &mmio_buf->phys_base, mmio_buf->size); + + /* initlize table */ + p_mmio = (struct ipa_mhi_mmio_register_set *)mmio_buf->base; + + /** + * 64-bit pointer to the channel context array in the host memory space; + * Host sets the pointer to the channel context array + * during initialization. + */ + p_mmio->ccabap = (u32)ch_ctx_array->phys_base - + (IPA_MHI_TEST_FIRST_CHANNEL_ID * + sizeof(struct ipa_mhi_channel_context_array)); + IPA_UT_DBG("pMmio->ccabap 0x%llx\n", p_mmio->ccabap); + + /** + * 64-bit pointer to the event context array in the host memory space; + * Host sets the pointer to the event context array + * during initialization + */ + p_mmio->ecabap = (u32)ev_ctx_array->phys_base - + (IPA_MHI_TEST_FIRST_EVENT_RING_ID * + sizeof(struct ipa_mhi_event_context_array)); + IPA_UT_DBG("pMmio->ecabap 0x%llx\n", p_mmio->ecabap); + + /** + * Register is not accessed by HWP. + * In test register carries the pointer of + * virtual address for the buffer of channel context array + */ + p_mmio->crcbap = (unsigned long)ch_ctx_array->base; + + /** + * Register is not accessed by HWP. + * In test register carries the pointer of + * virtual address for the buffer of channel context array + */ + p_mmio->crdb = (unsigned long)ev_ctx_array->base; + + /* test is running only on device. no need to translate addresses */ + p_mmio->mhiaddr.mhicrtlbase = 0x04; + p_mmio->mhiaddr.mhictrllimit = 0xFFFFFFFF; + p_mmio->mhiaddr.mhidatabase = 0x04; + p_mmio->mhiaddr.mhidatalimit = 0xFFFFFFFF; + + return rc; + +fail_free_ev_ctx_arr: + dma_free_coherent(ipa3_ctx->pdev, ev_ctx_array->size, + ev_ctx_array->base, ev_ctx_array->phys_base); + ev_ctx_array->base = NULL; +fail_free_ch_ctx_arr: + dma_free_coherent(ipa3_ctx->pdev, ch_ctx_array->size, + ch_ctx_array->base, ch_ctx_array->phys_base); + ch_ctx_array->base = NULL; +fail_free_msi: + dma_free_coherent(ipa3_ctx->pdev, msi->size, msi->base, + msi->phys_base); + msi->base = NULL; + return rc; +} + +static void ipa_mhi_test_destroy_channel_context( + struct ipa_mem_buffer transfer_ring_bufs[], + struct ipa_mem_buffer event_ring_bufs[], + u8 channel_id, + u8 event_ring_id) +{ + u32 ev_ring_idx; + u32 ch_idx; + + IPA_UT_DBG("Entry\n"); + + if ((channel_id < IPA_MHI_TEST_FIRST_CHANNEL_ID) || + (channel_id > IPA_MHI_TEST_LAST_CHANNEL_ID)) { + IPA_UT_ERR("channal_id invalid %d\n", channel_id); + return; + } + + if ((event_ring_id < IPA_MHI_TEST_FIRST_EVENT_RING_ID) || + (event_ring_id > IPA_MHI_TEST_LAST_EVENT_RING_ID)) { + IPA_UT_ERR("event_ring_id invalid %d\n", event_ring_id); + return; + } + + ch_idx = channel_id - IPA_MHI_TEST_FIRST_CHANNEL_ID; + ev_ring_idx = event_ring_id - IPA_MHI_TEST_FIRST_EVENT_RING_ID; + + if (transfer_ring_bufs[ch_idx].base) { + dma_free_coherent(ipa3_ctx->pdev, + transfer_ring_bufs[ch_idx].size, + transfer_ring_bufs[ch_idx].base, + transfer_ring_bufs[ch_idx].phys_base); + transfer_ring_bufs[ch_idx].base = NULL; + } + + if (event_ring_bufs[ev_ring_idx].base) { + dma_free_coherent(ipa3_ctx->pdev, + event_ring_bufs[ev_ring_idx].size, + event_ring_bufs[ev_ring_idx].base, + event_ring_bufs[ev_ring_idx].phys_base); + event_ring_bufs[ev_ring_idx].base = NULL; + } +} + +static int ipa_mhi_test_config_channel_context( + struct ipa_mem_buffer *mmio, + struct ipa_mem_buffer transfer_ring_bufs[], + struct ipa_mem_buffer event_ring_bufs[], + u8 channel_id, + u8 event_ring_id, + u16 transfer_ring_size, + u16 event_ring_size, + u8 ch_type) +{ + struct ipa_mhi_mmio_register_set *p_mmio; + struct ipa_mhi_channel_context_array *p_channels; + struct ipa_mhi_event_context_array *p_events; + u32 ev_ring_idx; + u32 ch_idx; + + IPA_UT_DBG("Entry\n"); + + if ((channel_id < IPA_MHI_TEST_FIRST_CHANNEL_ID) || + (channel_id > IPA_MHI_TEST_LAST_CHANNEL_ID)) { + IPA_UT_DBG("channal_id invalid %d\n", channel_id); + return -EFAULT; + } + + if ((event_ring_id < IPA_MHI_TEST_FIRST_EVENT_RING_ID) || + (event_ring_id > IPA_MHI_TEST_LAST_EVENT_RING_ID)) { + IPA_UT_DBG("event_ring_id invalid %d\n", event_ring_id); + return -EFAULT; + } + + p_mmio = (struct ipa_mhi_mmio_register_set *)mmio->base; + p_channels = + (struct ipa_mhi_channel_context_array *) + ((unsigned long)p_mmio->crcbap); + p_events = (struct ipa_mhi_event_context_array *) + ((unsigned long)p_mmio->crdb); + + IPA_UT_DBG("p_mmio: %pK p_channels: %pK p_events: %pK\n", + p_mmio, p_channels, p_events); + + ch_idx = channel_id - IPA_MHI_TEST_FIRST_CHANNEL_ID; + ev_ring_idx = event_ring_id - IPA_MHI_TEST_FIRST_EVENT_RING_ID; + + IPA_UT_DBG("ch_idx: %u ev_ring_idx: %u\n", ch_idx, ev_ring_idx); + if (transfer_ring_bufs[ch_idx].base) { + IPA_UT_ERR("ChannelId %d is already allocated\n", channel_id); + return -EFAULT; + } + + /* allocate and init event ring if needed */ + if (!event_ring_bufs[ev_ring_idx].base) { + IPA_UT_LOG("Configuring event ring...\n"); + event_ring_bufs[ev_ring_idx].size = + event_ring_size * + sizeof(struct ipa_mhi_event_ring_element); + event_ring_bufs[ev_ring_idx].base = + dma_alloc_coherent(ipa3_ctx->pdev, + event_ring_bufs[ev_ring_idx].size, + &event_ring_bufs[ev_ring_idx].phys_base, + GFP_KERNEL); + if (!event_ring_bufs[ev_ring_idx].base) { + IPA_UT_ERR("no mem for ev ring buf\n"); + return -ENOMEM; + } + p_events[ev_ring_idx].intmodc = 1; + p_events[ev_ring_idx].intmodt = 0; + p_events[ev_ring_idx].msivec = event_ring_id; + p_events[ev_ring_idx].rbase = + (u32)event_ring_bufs[ev_ring_idx].phys_base; + p_events[ev_ring_idx].rlen = + event_ring_bufs[ev_ring_idx].size; + p_events[ev_ring_idx].rp = + (u32)event_ring_bufs[ev_ring_idx].phys_base; + p_events[ev_ring_idx].wp = + (u32)event_ring_bufs[ev_ring_idx].phys_base + + event_ring_bufs[ev_ring_idx].size - 16; + } else { + IPA_UT_LOG("Skip configuring event ring - already done\n"); + } + + transfer_ring_bufs[ch_idx].size = + transfer_ring_size * + sizeof(struct ipa_mhi_transfer_ring_element); + transfer_ring_bufs[ch_idx].base = + dma_alloc_coherent(ipa3_ctx->pdev, + transfer_ring_bufs[ch_idx].size, + &transfer_ring_bufs[ch_idx].phys_base, + GFP_KERNEL); + if (!transfer_ring_bufs[ch_idx].base) { + IPA_UT_ERR("no mem for xfer ring buf\n"); + dma_free_coherent(ipa3_ctx->pdev, + event_ring_bufs[ev_ring_idx].size, + event_ring_bufs[ev_ring_idx].base, + event_ring_bufs[ev_ring_idx].phys_base); + event_ring_bufs[ev_ring_idx].base = NULL; + return -ENOMEM; + } + + p_channels[ch_idx].erindex = event_ring_id; + p_channels[ch_idx].rbase = (u32)transfer_ring_bufs[ch_idx].phys_base; + p_channels[ch_idx].rlen = transfer_ring_bufs[ch_idx].size; + p_channels[ch_idx].rp = (u32)transfer_ring_bufs[ch_idx].phys_base; + p_channels[ch_idx].wp = (u32)transfer_ring_bufs[ch_idx].phys_base; + p_channels[ch_idx].chtype = ch_type; + p_channels[ch_idx].brsmode = IPA_MHI_BURST_MODE_DISABLE; + p_channels[ch_idx].pollcfg = 0; + + return 0; +} + +static void ipa_mhi_test_destroy_data_structures(void) +{ + IPA_UT_DBG("Entry\n"); + + /* Destroy OUT data buffer */ + if (test_mhi_ctx->out_buffer.base) { + dma_free_coherent(ipa3_ctx->pdev, + test_mhi_ctx->out_buffer.size, + test_mhi_ctx->out_buffer.base, + test_mhi_ctx->out_buffer.phys_base); + test_mhi_ctx->out_buffer.base = NULL; + } + + /* Destroy IN data buffer */ + if (test_mhi_ctx->in_buffer.base) { + dma_free_coherent(ipa3_ctx->pdev, + test_mhi_ctx->in_buffer.size, + test_mhi_ctx->in_buffer.base, + test_mhi_ctx->in_buffer.phys_base); + test_mhi_ctx->in_buffer.base = NULL; + } + + /* Destroy IN channel ctx */ + ipa_mhi_test_destroy_channel_context( + test_mhi_ctx->xfer_ring_bufs, + test_mhi_ctx->ev_ring_bufs, + IPA_MHI_TEST_FIRST_CHANNEL_ID + 1, + IPA_MHI_TEST_FIRST_EVENT_RING_ID + 1); + + /* Destroy OUT channel ctx */ + ipa_mhi_test_destroy_channel_context( + test_mhi_ctx->xfer_ring_bufs, + test_mhi_ctx->ev_ring_bufs, + IPA_MHI_TEST_FIRST_CHANNEL_ID, + IPA_MHI_TEST_FIRST_EVENT_RING_ID); +} + +static int ipa_mhi_test_setup_data_structures(void) +{ + int rc = 0; + + IPA_UT_DBG("Entry\n"); + + /* Config OUT Channel Context */ + rc = ipa_mhi_test_config_channel_context( + &test_mhi_ctx->mmio_buf, + test_mhi_ctx->xfer_ring_bufs, + test_mhi_ctx->ev_ring_bufs, + IPA_MHI_TEST_FIRST_CHANNEL_ID, + IPA_MHI_TEST_FIRST_EVENT_RING_ID, + 0x100, + 0x80, + IPA_MHI_OUT_CHAHNNEL); + if (rc) { + IPA_UT_ERR("Fail to config OUT ch ctx - err %d", rc); + return rc; + } + + /* Config IN Channel Context */ + rc = ipa_mhi_test_config_channel_context( + &test_mhi_ctx->mmio_buf, + test_mhi_ctx->xfer_ring_bufs, + test_mhi_ctx->ev_ring_bufs, + IPA_MHI_TEST_FIRST_CHANNEL_ID + 1, + IPA_MHI_TEST_FIRST_EVENT_RING_ID + 1, + 0x100, + 0x80, + IPA_MHI_IN_CHAHNNEL); + if (rc) { + IPA_UT_ERR("Fail to config IN ch ctx - err %d", rc); + goto fail_destroy_out_ch_ctx; + } + + /* allocate IN data buffer */ + test_mhi_ctx->in_buffer.size = IPA_MHI_TEST_MAX_DATA_BUF_SIZE; + test_mhi_ctx->in_buffer.base = dma_alloc_coherent( + ipa3_ctx->pdev, test_mhi_ctx->in_buffer.size, + &test_mhi_ctx->in_buffer.phys_base, GFP_KERNEL); + if (!test_mhi_ctx->in_buffer.base) { + IPA_UT_ERR("no mem for In data buffer\n"); + rc = -ENOMEM; + goto fail_destroy_in_ch_ctx; + } + memset(test_mhi_ctx->in_buffer.base, 0, + IPA_MHI_TEST_MAX_DATA_BUF_SIZE); + + /* allocate OUT data buffer */ + test_mhi_ctx->out_buffer.size = IPA_MHI_TEST_MAX_DATA_BUF_SIZE; + test_mhi_ctx->out_buffer.base = dma_alloc_coherent( + ipa3_ctx->pdev, test_mhi_ctx->out_buffer.size, + &test_mhi_ctx->out_buffer.phys_base, GFP_KERNEL); + if (!test_mhi_ctx->out_buffer.base) { + IPA_UT_ERR("no mem for Out data buffer\n"); + rc = -EFAULT; + goto fail_destroy_in_data_buf; + } + memset(test_mhi_ctx->out_buffer.base, 0, + IPA_MHI_TEST_MAX_DATA_BUF_SIZE); + + return 0; + +fail_destroy_in_data_buf: + dma_free_coherent(ipa3_ctx->pdev, + test_mhi_ctx->in_buffer.size, + test_mhi_ctx->in_buffer.base, + test_mhi_ctx->in_buffer.phys_base); + test_mhi_ctx->in_buffer.base = NULL; +fail_destroy_in_ch_ctx: + ipa_mhi_test_destroy_channel_context( + test_mhi_ctx->xfer_ring_bufs, + test_mhi_ctx->ev_ring_bufs, + IPA_MHI_TEST_FIRST_CHANNEL_ID + 1, + IPA_MHI_TEST_FIRST_EVENT_RING_ID + 1); +fail_destroy_out_ch_ctx: + ipa_mhi_test_destroy_channel_context( + test_mhi_ctx->xfer_ring_bufs, + test_mhi_ctx->ev_ring_bufs, + IPA_MHI_TEST_FIRST_CHANNEL_ID, + IPA_MHI_TEST_FIRST_EVENT_RING_ID); + return 0; +} + +/** + * ipa_test_mhi_suite_setup() - Suite setup function + */ +static int ipa_test_mhi_suite_setup(void **ppriv) +{ + int rc = 0; + struct ipa_sys_connect_params sys_in; + + IPA_UT_DBG("Start Setup\n"); + + if (!ipa3_ctx) { + IPA_UT_ERR("No IPA ctx\n"); + return -EINVAL; + } + + test_mhi_ctx = kzalloc(sizeof(struct ipa_test_mhi_context), + GFP_KERNEL); + if (!test_mhi_ctx) { + IPA_UT_ERR("failed allocated ctx\n"); + return -ENOMEM; + } + + rc = ipa3_get_transport_info(&test_mhi_ctx->transport_phys_addr, + &test_mhi_ctx->transport_size); + if (rc != 0) { + IPA_UT_ERR("ipa3_get_transport_info() failed\n"); + rc = -EFAULT; + goto fail_free_ctx; + } + + rc = ipa_test_mhi_alloc_mmio_space(); + if (rc) { + IPA_UT_ERR("failed to alloc mmio space"); + goto fail_free_ctx; + } + + rc = ipa_mhi_test_setup_data_structures(); + if (rc) { + IPA_UT_ERR("failed to setup data structures"); + goto fail_free_mmio_spc; + } + + /* connect PROD pipe for remote wakeup */ + memset(&sys_in, 0, sizeof(struct ipa_sys_connect_params)); + sys_in.client = IPA_CLIENT_TEST_PROD; + sys_in.desc_fifo_sz = IPA_SYS_DESC_FIFO_SZ; + sys_in.ipa_ep_cfg.mode.mode = IPA_DMA; + sys_in.ipa_ep_cfg.mode.dst = IPA_CLIENT_MHI_CONS; + if (ipa_setup_sys_pipe(&sys_in, &test_mhi_ctx->test_prod_hdl)) { + IPA_UT_ERR("setup sys pipe failed.\n"); + goto fail_destroy_data_structures; + } + + *ppriv = test_mhi_ctx; + return 0; + +fail_destroy_data_structures: + ipa_mhi_test_destroy_data_structures(); +fail_free_mmio_spc: + ipa_test_mhi_free_mmio_space(); +fail_free_ctx: + kfree(test_mhi_ctx); + test_mhi_ctx = NULL; + return rc; +} + +/** + * ipa_test_mhi_suite_teardown() - Suite teardown function + */ +static int ipa_test_mhi_suite_teardown(void *priv) +{ + IPA_UT_DBG("Start Teardown\n"); + + if (!test_mhi_ctx) + return 0; + + ipa_teardown_sys_pipe(test_mhi_ctx->test_prod_hdl); + ipa_mhi_test_destroy_data_structures(); + ipa_test_mhi_free_mmio_space(); + kfree(test_mhi_ctx); + test_mhi_ctx = NULL; + + return 0; +} + +/** + * ipa_mhi_test_initialize_driver() - MHI init and possibly start and connect + * + * To be run during tests + * 1. MHI init (Ready state) + * 2. Conditional MHI start and connect (M0 state) + */ +static int ipa_mhi_test_initialize_driver(bool skip_start_and_conn) +{ + int rc = 0; + struct ipa_mhi_init_params init_params; + struct ipa_mhi_start_params start_params; + struct ipa_mhi_connect_params prod_params; + struct ipa_mhi_connect_params cons_params; + struct ipa_mhi_mmio_register_set *p_mmio; + struct ipa_mhi_channel_context_array *p_ch_ctx_array; + u64 phys_addr; + + IPA_UT_LOG("Entry\n"); + + p_mmio = test_mhi_ctx->mmio_buf.base; + + /* start IPA MHI */ + memset(&init_params, 0, sizeof(init_params)); + init_params.msi.addr_low = test_mhi_ctx->msi.phys_base; + init_params.msi.data = 0x10000000; + init_params.msi.mask = ~0x10000000; + /* MMIO not needed for GSI */ + init_params.first_ch_idx = IPA_MHI_TEST_FIRST_CHANNEL_ID; + init_params.first_er_idx = IPA_MHI_TEST_FIRST_EVENT_RING_ID; + init_params.assert_bit40 = false; + init_params.notify = ipa_mhi_test_cb; + init_params.priv = NULL; + init_params.test_mode = true; + + rc = ipa_mhi_init(&init_params); + if (rc) { + IPA_UT_LOG("ipa_mhi_init failed %d\n", rc); + return rc; + } + + IPA_UT_LOG("Wait async ready event\n"); + if (wait_for_completion_timeout(&mhi_test_ready_comp, 10 * HZ) == 0) { + IPA_UT_LOG("timeout waiting for READY event"); + IPA_UT_TEST_FAIL_REPORT("failed waiting for state ready"); + return -ETIME; + } + + if (!skip_start_and_conn) { + memset(&start_params, 0, sizeof(start_params)); + start_params.channel_context_array_addr = p_mmio->ccabap; + start_params.event_context_array_addr = p_mmio->ecabap; + + IPA_UT_LOG("BEFORE mhi_start\n"); + rc = ipa_mhi_start(&start_params); + if (rc) { + IPA_UT_LOG("mhi_start failed %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail start mhi"); + return rc; + } + IPA_UT_LOG("AFTER mhi_start\n"); + + phys_addr = p_mmio->ccabap + (IPA_MHI_TEST_FIRST_CHANNEL_ID * + sizeof(struct ipa_mhi_channel_context_array)); + p_ch_ctx_array = test_mhi_ctx->ch_ctx_array.base + + (phys_addr - test_mhi_ctx->ch_ctx_array.phys_base); + IPA_UT_LOG("ch: %d base: 0x%pK phys_addr 0x%llx chstate: %s\n", + IPA_MHI_TEST_FIRST_CHANNEL_ID, + p_ch_ctx_array, phys_addr, + MHI_STATE_STR(p_ch_ctx_array->chstate)); + + memset(&prod_params, 0, sizeof(prod_params)); + prod_params.sys.client = IPA_CLIENT_MHI_PROD; + prod_params.sys.ipa_ep_cfg.mode.mode = IPA_DMA; + prod_params.sys.ipa_ep_cfg.mode.dst = IPA_CLIENT_MHI_CONS; + prod_params.sys.ipa_ep_cfg.seq.seq_type = + IPA_MHI_TEST_SEQ_TYPE_DMA; + prod_params.sys.ipa_ep_cfg.seq.set_dynamic = true; + prod_params.channel_id = IPA_MHI_TEST_FIRST_CHANNEL_ID; + IPA_UT_LOG("BEFORE connect_pipe (PROD): client:%d ch_id:%u\n", + prod_params.sys.client, prod_params.channel_id); + rc = ipa_mhi_connect_pipe(&prod_params, + &test_mhi_ctx->prod_hdl); + if (rc) { + IPA_UT_LOG("mhi_connect_pipe failed %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail connect PROD pipe"); + return rc; + } + + if (p_ch_ctx_array->chstate != IPA_HW_MHI_CHANNEL_STATE_RUN) { + IPA_UT_LOG("MHI_PROD: chstate is not RUN chstate:%s\n", + MHI_STATE_STR( + p_ch_ctx_array->chstate)); + IPA_UT_TEST_FAIL_REPORT("PROD pipe state is not run"); + return -EFAULT; + } + + phys_addr = p_mmio->ccabap + + ((IPA_MHI_TEST_FIRST_CHANNEL_ID + 1) * + sizeof(struct ipa_mhi_channel_context_array)); + p_ch_ctx_array = test_mhi_ctx->ch_ctx_array.base + + (phys_addr - test_mhi_ctx->ch_ctx_array.phys_base); + IPA_UT_LOG("ch: %d base: 0x%pK phys_addr 0x%llx chstate: %s\n", + IPA_MHI_TEST_FIRST_CHANNEL_ID + 1, + p_ch_ctx_array, phys_addr, + MHI_STATE_STR(p_ch_ctx_array->chstate)); + + memset(&cons_params, 0, sizeof(cons_params)); + cons_params.sys.client = IPA_CLIENT_MHI_CONS; + cons_params.sys.skip_ep_cfg = true; + cons_params.channel_id = IPA_MHI_TEST_FIRST_CHANNEL_ID + 1; + IPA_UT_LOG("BEFORE connect_pipe (CONS): client:%d ch_id:%u\n", + cons_params.sys.client, cons_params.channel_id); + rc = ipa_mhi_connect_pipe(&cons_params, + &test_mhi_ctx->cons_hdl); + if (rc) { + IPA_UT_LOG("mhi_connect_pipe failed %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail connect CONS pipe"); + return rc; + } + + if (p_ch_ctx_array->chstate != IPA_HW_MHI_CHANNEL_STATE_RUN) { + IPA_UT_LOG("MHI_CONS: chstate is not RUN chstate:%s\n", + MHI_STATE_STR( + p_ch_ctx_array->chstate)); + IPA_UT_TEST_FAIL_REPORT("CONS pipe state is not run"); + return -EFAULT; + } + } + + return 0; +} + +/** + * To be run during test + * 1. MHI destroy + * 2. re-configure the channels + */ +static int ipa_mhi_test_destroy(struct ipa_test_mhi_context *ctx) +{ + struct ipa_mhi_mmio_register_set *p_mmio; + u64 phys_addr; + struct ipa_mhi_channel_context_array *p_ch_ctx_array; + int rc; + + IPA_UT_LOG("Entry\n"); + + if (unlikely(!ctx)) { + IPA_UT_LOG("Input err invalid ctx\n"); + return -EINVAL; + } + + p_mmio = ctx->mmio_buf.base; + + phys_addr = p_mmio->ccabap + + ((IPA_MHI_TEST_FIRST_CHANNEL_ID + 1) * + sizeof(struct ipa_mhi_channel_context_array)); + p_ch_ctx_array = ctx->ch_ctx_array.base + + (phys_addr - ctx->ch_ctx_array.phys_base); + IPA_UT_LOG("channel id %d (CONS): chstate %s\n", + IPA_MHI_TEST_FIRST_CHANNEL_ID + 1, + MHI_STATE_STR(p_ch_ctx_array->chstate)); + + phys_addr = p_mmio->ccabap + + ((IPA_MHI_TEST_FIRST_CHANNEL_ID) * + sizeof(struct ipa_mhi_channel_context_array)); + p_ch_ctx_array = ctx->ch_ctx_array.base + + (phys_addr - ctx->ch_ctx_array.phys_base); + IPA_UT_LOG("channel id %d (PROD): chstate %s\n", + IPA_MHI_TEST_FIRST_CHANNEL_ID, + MHI_STATE_STR(p_ch_ctx_array->chstate)); + + IPA_UT_LOG("MHI Destroy\n"); + ipa_mhi_destroy(); + IPA_UT_LOG("Post MHI Destroy\n"); + + ctx->prod_hdl = 0; + ctx->cons_hdl = 0; + + dma_free_coherent(ipa3_ctx->pdev, ctx->xfer_ring_bufs[1].size, + ctx->xfer_ring_bufs[1].base, ctx->xfer_ring_bufs[1].phys_base); + ctx->xfer_ring_bufs[1].base = NULL; + + IPA_UT_LOG("config channel context for channel %d (MHI CONS)\n", + IPA_MHI_TEST_FIRST_CHANNEL_ID + 1); + rc = ipa_mhi_test_config_channel_context( + &ctx->mmio_buf, + ctx->xfer_ring_bufs, + ctx->ev_ring_bufs, + IPA_MHI_TEST_FIRST_CHANNEL_ID + 1, + IPA_MHI_TEST_FIRST_EVENT_RING_ID + 1, + 0x100, + 0x80, + IPA_MHI_IN_CHAHNNEL); + if (rc) { + IPA_UT_LOG("config channel context failed %d, channel %d\n", + rc, IPA_MHI_TEST_FIRST_CHANNEL_ID + 1); + IPA_UT_TEST_FAIL_REPORT("fail config CONS channel ctx"); + return -EFAULT; + } + + dma_free_coherent(ipa3_ctx->pdev, ctx->xfer_ring_bufs[0].size, + ctx->xfer_ring_bufs[0].base, ctx->xfer_ring_bufs[0].phys_base); + ctx->xfer_ring_bufs[0].base = NULL; + + IPA_UT_LOG("config channel context for channel %d (MHI PROD)\n", + IPA_MHI_TEST_FIRST_CHANNEL_ID); + rc = ipa_mhi_test_config_channel_context( + &ctx->mmio_buf, + ctx->xfer_ring_bufs, + ctx->ev_ring_bufs, + IPA_MHI_TEST_FIRST_CHANNEL_ID, + IPA_MHI_TEST_FIRST_EVENT_RING_ID, + 0x100, + 0x80, + IPA_MHI_OUT_CHAHNNEL); + if (rc) { + IPA_UT_LOG("config channel context failed %d, channel %d\n", + rc, IPA_MHI_TEST_FIRST_CHANNEL_ID); + IPA_UT_TEST_FAIL_REPORT("fail config PROD channel ctx"); + return -EFAULT; + } + + return 0; +} + +/** + * To be run during test + * 1. Destroy + * 2. Initialize (to Ready or M0 states) + */ +static int ipa_mhi_test_reset(struct ipa_test_mhi_context *ctx, + bool skip_start_and_conn) +{ + int rc; + + IPA_UT_LOG("Entry\n"); + + rc = ipa_mhi_test_destroy(ctx); + if (rc) { + IPA_UT_LOG("destroy failed rc=%d", rc); + IPA_UT_TEST_FAIL_REPORT("destroy fail"); + return rc; + } + + rc = ipa_mhi_test_initialize_driver(skip_start_and_conn); + if (rc) { + IPA_UT_LOG("driver init failed skip_start_and_con=%d rc=%d\n", + skip_start_and_conn, rc); + IPA_UT_TEST_FAIL_REPORT("init fail"); + return rc; + } + + return 0; +} + +/** + * To be run during test + * 1. disconnect cons channel + * 2. config cons channel + * 3. disconnect prod channel + * 4. config prod channel + * 5. connect prod + * 6. connect cons + */ +static int ipa_mhi_test_channel_reset(void) +{ + int rc; + struct ipa_mhi_connect_params prod_params; + struct ipa_mhi_connect_params cons_params; + struct ipa_mhi_mmio_register_set *p_mmio; + struct ipa_mhi_channel_context_array *p_ch_ctx_array; + u64 phys_addr; + + p_mmio = test_mhi_ctx->mmio_buf.base; + + IPA_UT_LOG("Before pipe disconnect (CONS) client hdl=%u=\n", + test_mhi_ctx->cons_hdl); + rc = ipa_mhi_disconnect_pipe(test_mhi_ctx->cons_hdl); + if (rc) { + IPA_UT_LOG("disconnect_pipe failed (CONS) %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("CONS pipe disconnect fail"); + return -EFAULT; + } + test_mhi_ctx->cons_hdl = 0; + + phys_addr = p_mmio->ccabap + + ((IPA_MHI_TEST_FIRST_CHANNEL_ID + 1) * + sizeof(struct ipa_mhi_channel_context_array)); + p_ch_ctx_array = test_mhi_ctx->ch_ctx_array.base + + (phys_addr - test_mhi_ctx->ch_ctx_array.phys_base); + + dma_free_coherent(ipa3_ctx->pdev, + test_mhi_ctx->xfer_ring_bufs[1].size, + test_mhi_ctx->xfer_ring_bufs[1].base, + test_mhi_ctx->xfer_ring_bufs[1].phys_base); + test_mhi_ctx->xfer_ring_bufs[1].base = NULL; + rc = ipa_mhi_test_config_channel_context( + &test_mhi_ctx->mmio_buf, + test_mhi_ctx->xfer_ring_bufs, + test_mhi_ctx->ev_ring_bufs, + IPA_MHI_TEST_FIRST_CHANNEL_ID + 1, + IPA_MHI_TEST_FIRST_EVENT_RING_ID + 1, + 0x100, + 0x80, + IPA_MHI_IN_CHAHNNEL); + if (rc) { + IPA_UT_LOG("config_channel_context IN failed %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail config CONS channel context"); + return -EFAULT; + } + IPA_UT_LOG("Before pipe disconnect (CONS) client hdl=%u=\n", + test_mhi_ctx->prod_hdl); + rc = ipa_mhi_disconnect_pipe(test_mhi_ctx->prod_hdl); + if (rc) { + IPA_UT_LOG("disconnect_pipe failed (PROD) %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("PROD pipe disconnect fail"); + return -EFAULT; + } + test_mhi_ctx->prod_hdl = 0; + + phys_addr = p_mmio->ccabap + ((IPA_MHI_TEST_FIRST_CHANNEL_ID) * + sizeof(struct ipa_mhi_channel_context_array)); + p_ch_ctx_array = test_mhi_ctx->ch_ctx_array.base + + (phys_addr - test_mhi_ctx->ch_ctx_array.phys_base); + + dma_free_coherent(ipa3_ctx->pdev, test_mhi_ctx->xfer_ring_bufs[0].size, + test_mhi_ctx->xfer_ring_bufs[0].base, + test_mhi_ctx->xfer_ring_bufs[0].phys_base); + test_mhi_ctx->xfer_ring_bufs[0].base = NULL; + rc = ipa_mhi_test_config_channel_context( + &test_mhi_ctx->mmio_buf, + test_mhi_ctx->xfer_ring_bufs, + test_mhi_ctx->ev_ring_bufs, + IPA_MHI_TEST_FIRST_CHANNEL_ID, + IPA_MHI_TEST_FIRST_EVENT_RING_ID, + 0x100, + 0x80, + IPA_MHI_OUT_CHAHNNEL); + if (rc) { + IPA_UT_LOG("config_channel_context OUT failed %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("PROD pipe state is not disabled"); + return -EFAULT; + } + + memset(&prod_params, 0, sizeof(prod_params)); + prod_params.sys.client = IPA_CLIENT_MHI_PROD; + prod_params.sys.ipa_ep_cfg.mode.mode = IPA_DMA; + prod_params.sys.ipa_ep_cfg.mode.dst = IPA_CLIENT_MHI_CONS; + prod_params.sys.ipa_ep_cfg.seq.seq_type = IPA_MHI_TEST_SEQ_TYPE_DMA; + prod_params.sys.ipa_ep_cfg.seq.set_dynamic = true; + prod_params.channel_id = IPA_MHI_TEST_FIRST_CHANNEL_ID; + IPA_UT_LOG("BEFORE connect PROD\n"); + rc = ipa_mhi_connect_pipe(&prod_params, &test_mhi_ctx->prod_hdl); + if (rc) { + IPA_UT_LOG("connect_pipe failed %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail connect PROD pipe"); + return rc; + } + + phys_addr = p_mmio->ccabap + ((IPA_MHI_TEST_FIRST_CHANNEL_ID) * + sizeof(struct ipa_mhi_channel_context_array)); + p_ch_ctx_array = test_mhi_ctx->ch_ctx_array.base + + (phys_addr - test_mhi_ctx->ch_ctx_array.phys_base); + if (p_ch_ctx_array->chstate != IPA_HW_MHI_CHANNEL_STATE_RUN) { + IPA_UT_LOG("chstate is not run! ch %d chstate %s\n", + IPA_MHI_TEST_FIRST_CHANNEL_ID, + MHI_STATE_STR(p_ch_ctx_array->chstate)); + IPA_UT_TEST_FAIL_REPORT("PROD pipe state is not run"); + return -EFAULT; + } + + memset(&cons_params, 0, sizeof(cons_params)); + cons_params.sys.client = IPA_CLIENT_MHI_CONS; + cons_params.sys.skip_ep_cfg = true; + cons_params.channel_id = IPA_MHI_TEST_FIRST_CHANNEL_ID + 1; + IPA_UT_LOG("BEFORE connect CONS\n"); + rc = ipa_mhi_connect_pipe(&cons_params, &test_mhi_ctx->cons_hdl); + if (rc) { + IPA_UT_LOG("ipa_mhi_connect_pipe failed %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail connect CONS pipe"); + return rc; + } + + phys_addr = p_mmio->ccabap + + ((IPA_MHI_TEST_FIRST_CHANNEL_ID + 1) * + sizeof(struct ipa_mhi_channel_context_array)); + p_ch_ctx_array = test_mhi_ctx->ch_ctx_array.base + + (phys_addr - test_mhi_ctx->ch_ctx_array.phys_base); + if (p_ch_ctx_array->chstate != IPA_HW_MHI_CHANNEL_STATE_RUN) { + IPA_UT_LOG("chstate is not run! ch %d chstate %s\n", + IPA_MHI_TEST_FIRST_CHANNEL_ID + 1, + MHI_STATE_STR(p_ch_ctx_array->chstate)); + IPA_UT_TEST_FAIL_REPORT("CONS pipe state is not run"); + return -EFAULT; + } + + return 0; +} + +/** + * To be run during test + * Send data + */ +static int ipa_mhi_test_q_transfer_re(struct ipa_mem_buffer *mmio, + struct ipa_mem_buffer xfer_ring_bufs[], + struct ipa_mem_buffer ev_ring_bufs[], + u8 channel_id, + struct ipa_mem_buffer buf_array[], + int buf_array_size, + bool ieob, + bool ieot, + bool bei, + bool trigger_db) +{ + struct ipa_mhi_transfer_ring_element *curr_re; + struct ipa_mhi_mmio_register_set *p_mmio; + struct ipa_mhi_channel_context_array *p_channels; + struct ipa_mhi_event_context_array *p_events; + u32 channel_idx; + u32 event_ring_index; + u32 wp_ofst; + u32 rp_ofst; + u32 next_wp_ofst; + int i; + u32 num_of_ed_to_queue; + u32 avail_ev; + + IPA_UT_LOG("Entry\n"); + + p_mmio = (struct ipa_mhi_mmio_register_set *)mmio->base; + p_channels = (struct ipa_mhi_channel_context_array *) + ((unsigned long)p_mmio->crcbap); + p_events = (struct ipa_mhi_event_context_array *) + ((unsigned long)p_mmio->crdb); + + if (ieob) + num_of_ed_to_queue = buf_array_size; + else + num_of_ed_to_queue = ieot ? 1 : 0; + + if (channel_id >= + (IPA_MHI_TEST_FIRST_CHANNEL_ID + IPA_MHI_TEST_NUM_CHANNELS) || + channel_id < IPA_MHI_TEST_FIRST_CHANNEL_ID) { + IPA_UT_LOG("Invalid Channel ID %d\n", channel_id); + return -EFAULT; + } + + channel_idx = channel_id - IPA_MHI_TEST_FIRST_CHANNEL_ID; + + if (!xfer_ring_bufs[channel_idx].base) { + IPA_UT_LOG("Channel is not allocated\n"); + return -EFAULT; + } + if (p_channels[channel_idx].brsmode == IPA_MHI_BURST_MODE_DEFAULT || + p_channels[channel_idx].brsmode == IPA_MHI_BURST_MODE_ENABLE) + num_of_ed_to_queue += 1; /* for OOB/DB mode event */ + + /* First queue EDs */ + event_ring_index = p_channels[channel_idx].erindex - + IPA_MHI_TEST_FIRST_EVENT_RING_ID; + + wp_ofst = (u32)(p_events[event_ring_index].wp - + p_events[event_ring_index].rbase); + rp_ofst = (u32)(p_events[event_ring_index].rp - + p_events[event_ring_index].rbase); + + if (p_events[event_ring_index].rlen & 0xFFFFFFFF00000000) { + IPA_UT_LOG("invalid ev rlen %llu\n", + p_events[event_ring_index].rlen); + return -EFAULT; + } + + if (wp_ofst > rp_ofst) { + avail_ev = (wp_ofst - rp_ofst) / + sizeof(struct ipa_mhi_event_ring_element); + } else { + avail_ev = (u32)p_events[event_ring_index].rlen - + (rp_ofst - wp_ofst); + avail_ev /= sizeof(struct ipa_mhi_event_ring_element); + } + + IPA_UT_LOG("wp_ofst=0x%x rp_ofst=0x%x rlen=%llu avail_ev=%u\n", + wp_ofst, rp_ofst, p_events[event_ring_index].rlen, avail_ev); + + if (num_of_ed_to_queue > ((u32)p_events[event_ring_index].rlen / + sizeof(struct ipa_mhi_event_ring_element))) { + IPA_UT_LOG("event ring too small for %u credits\n", + num_of_ed_to_queue); + return -EFAULT; + } + + if (num_of_ed_to_queue > avail_ev) { + IPA_UT_LOG("Need to add event credits (needed=%u)\n", + num_of_ed_to_queue - avail_ev); + + next_wp_ofst = (wp_ofst + (num_of_ed_to_queue - avail_ev) * + sizeof(struct ipa_mhi_event_ring_element)) % + (u32)p_events[event_ring_index].rlen; + + /* set next WP */ + p_events[event_ring_index].wp = + (u32)p_events[event_ring_index].rbase + next_wp_ofst; + + /* write value to event ring doorbell */ + IPA_UT_LOG("DB to event 0x%llx: base %pa ofst 0x%x\n", + p_events[event_ring_index].wp, + &(test_mhi_ctx->transport_phys_addr), + gsihal_get_reg_nk_ofst(GSI_EE_n_EV_CH_k_DOORBELL_0, 0, + event_ring_index + ipa3_ctx->mhi_evid_limits[0])); + gsihal_write_reg_nk(GSI_EE_n_EV_CH_k_DOORBELL_0, 0, + event_ring_index + ipa3_ctx->mhi_evid_limits[0], + p_events[event_ring_index].wp); + } + + for (i = 0; i < buf_array_size; i++) { + /* calculate virtual pointer for current WP and RP */ + wp_ofst = (u32)(p_channels[channel_idx].wp - + p_channels[channel_idx].rbase); + rp_ofst = (u32)(p_channels[channel_idx].rp - + p_channels[channel_idx].rbase); + (void)rp_ofst; + curr_re = (struct ipa_mhi_transfer_ring_element *) + ((unsigned long)xfer_ring_bufs[channel_idx].base + + wp_ofst); + if (p_channels[channel_idx].rlen & 0xFFFFFFFF00000000) { + IPA_UT_LOG("invalid ch rlen %llu\n", + p_channels[channel_idx].rlen); + return -EFAULT; + } + next_wp_ofst = (wp_ofst + + sizeof(struct ipa_mhi_transfer_ring_element)) % + (u32)p_channels[channel_idx].rlen; + + /* write current RE */ + curr_re->type = IPA_MHI_RING_ELEMENT_TRANSFER; + curr_re->len = (u16)buf_array[i].size; + curr_re->ptr = (u32)buf_array[i].phys_base; + curr_re->word_C.bits.bei = bei; + curr_re->word_C.bits.ieob = ieob; + curr_re->word_C.bits.ieot = ieot; + + /* set next WP */ + p_channels[channel_idx].wp = + p_channels[channel_idx].rbase + next_wp_ofst; + + if (i == (buf_array_size - 1)) { + /* last buffer */ + curr_re->word_C.bits.chain = 0; + if (trigger_db) { + IPA_UT_LOG( + "DB to channel 0x%llx: base %pa ofst 0x%x\n" + , p_channels[channel_idx].wp + , &(test_mhi_ctx->transport_phys_addr) + , gsihal_get_reg_nk_ofst( + GSI_EE_n_GSI_CH_k_DOORBELL_0, + 0, channel_idx)); + gsihal_write_reg_nk( + GSI_EE_n_GSI_CH_k_DOORBELL_0, + 0, channel_idx, + p_channels[channel_idx].wp); + } + } else { + curr_re->word_C.bits.chain = 1; + } + } + + return 0; +} + +/** + * To be run during test + * Send data in loopback (from In to OUT) and compare + */ +static int ipa_mhi_test_loopback_data_transfer(void) +{ + struct ipa_mem_buffer *p_mmio; + int i; + int rc; + static int val; + bool timeout = true; + + IPA_UT_LOG("Entry\n"); + + p_mmio = &test_mhi_ctx->mmio_buf; + + /* invalidate spare register value (for msi) */ + memset(test_mhi_ctx->msi.base, 0xFF, test_mhi_ctx->msi.size); + + val++; + + memset(test_mhi_ctx->in_buffer.base, 0, + IPA_MHI_TEST_MAX_DATA_BUF_SIZE); + for (i = 0; i < IPA_MHI_TEST_MAX_DATA_BUF_SIZE; i++) + memset(test_mhi_ctx->out_buffer.base + i, (val + i) & 0xFF, 1); + + /* queue RE for IN side and trigger doorbell */ + rc = ipa_mhi_test_q_transfer_re(p_mmio, + test_mhi_ctx->xfer_ring_bufs, + test_mhi_ctx->ev_ring_bufs, + IPA_MHI_TEST_FIRST_CHANNEL_ID + 1, + &test_mhi_ctx->in_buffer, + 1, + true, + true, + false, + true); + + if (rc) { + IPA_UT_LOG("q_transfer_re failed %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail IN q xfer re"); + return rc; + } + + /* queue REs for OUT side and trigger doorbell */ + rc = ipa_mhi_test_q_transfer_re(p_mmio, + test_mhi_ctx->xfer_ring_bufs, + test_mhi_ctx->ev_ring_bufs, + IPA_MHI_TEST_FIRST_CHANNEL_ID, + &test_mhi_ctx->out_buffer, + 1, + true, + true, + false, + true); + + if (rc) { + IPA_UT_LOG("q_transfer_re failed %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail OUT q xfer re"); + return rc; + } + + IPA_MHI_TEST_CHECK_MSI_INTR(true, timeout); + if (timeout) { + IPA_UT_LOG("transfer timeout. MSI = 0x%x\n", + *((u32 *)test_mhi_ctx->msi.base)); + IPA_UT_TEST_FAIL_REPORT("xfter timeout"); + return -EFAULT; + } + + /* compare the two buffers */ + if (memcmp(test_mhi_ctx->in_buffer.base, test_mhi_ctx->out_buffer.base, + IPA_MHI_TEST_MAX_DATA_BUF_SIZE)) { + IPA_UT_LOG("buffer are not equal\n"); + IPA_UT_TEST_FAIL_REPORT("non-equal buffers after xfer"); + return -EFAULT; + } + + return 0; +} + +/** + * To be run during test + * Do suspend and check channel states to be suspend if should success + */ +static int ipa_mhi_test_suspend(bool force, bool should_success) +{ + int rc; + struct ipa_mhi_mmio_register_set *p_mmio; + struct ipa_mhi_channel_context_array *p_ch_ctx_array; + u64 phys_addr; + + IPA_UT_LOG("Entry\n"); + + rc = ipa_mhi_suspend(force); + if (should_success && rc != 0) { + IPA_UT_LOG("ipa_mhi_suspend failed %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("suspend failed"); + return -EFAULT; + } + + if (!should_success && rc != -EAGAIN) { + IPA_UT_LOG("ipa_mhi_suspend did not return -EAGAIN fail %d\n", + rc); + IPA_UT_TEST_FAIL_REPORT("suspend succeeded unexpectedly"); + return -EFAULT; + } + + p_mmio = test_mhi_ctx->mmio_buf.base; + + phys_addr = p_mmio->ccabap + ((IPA_MHI_TEST_FIRST_CHANNEL_ID + 1) * + sizeof(struct ipa_mhi_channel_context_array)); + p_ch_ctx_array = test_mhi_ctx->ch_ctx_array.base + + (phys_addr - test_mhi_ctx->ch_ctx_array.phys_base); + if (should_success) { + if (p_ch_ctx_array->chstate != + IPA_HW_MHI_CHANNEL_STATE_SUSPEND) { + IPA_UT_LOG("chstate is not suspend! ch %d chstate %s\n", + IPA_MHI_TEST_FIRST_CHANNEL_ID + 1, + MHI_STATE_STR(p_ch_ctx_array->chstate)); + IPA_UT_TEST_FAIL_REPORT("channel state not suspend"); + return -EFAULT; + } + if (!force && p_ch_ctx_array->rp != p_ch_ctx_array->wp) { + IPA_UT_LOG("rp not updated ch %d rp 0x%llx wp 0x%llx\n", + IPA_MHI_TEST_FIRST_CHANNEL_ID + 1, + p_ch_ctx_array->rp, p_ch_ctx_array->wp); + IPA_UT_TEST_FAIL_REPORT("rp was not updated"); + return -EFAULT; + } + } else { + if (p_ch_ctx_array->chstate != IPA_HW_MHI_CHANNEL_STATE_RUN) { + IPA_UT_LOG("chstate is not running! ch %d chstate %s\n", + IPA_MHI_TEST_FIRST_CHANNEL_ID + 1, + MHI_STATE_STR(p_ch_ctx_array->chstate)); + IPA_UT_TEST_FAIL_REPORT("channel state not run"); + return -EFAULT; + } + } + + phys_addr = p_mmio->ccabap + ((IPA_MHI_TEST_FIRST_CHANNEL_ID) * + sizeof(struct ipa_mhi_channel_context_array)); + p_ch_ctx_array = test_mhi_ctx->ch_ctx_array.base + + (phys_addr - test_mhi_ctx->ch_ctx_array.phys_base); + if (should_success) { + if (p_ch_ctx_array->chstate != + IPA_HW_MHI_CHANNEL_STATE_SUSPEND) { + IPA_UT_LOG("chstate is not suspend! ch %d chstate %s\n", + IPA_MHI_TEST_FIRST_CHANNEL_ID, + MHI_STATE_STR(p_ch_ctx_array->chstate)); + IPA_UT_TEST_FAIL_REPORT("channel state not suspend"); + return -EFAULT; + } + if (!force && p_ch_ctx_array->rp != p_ch_ctx_array->wp) { + IPA_UT_LOG("rp not updated ch %d rp 0x%llx wp 0x%llx\n", + IPA_MHI_TEST_FIRST_CHANNEL_ID, + p_ch_ctx_array->rp, p_ch_ctx_array->wp); + IPA_UT_TEST_FAIL_REPORT("rp was not updated"); + return -EFAULT; + } + } else { + if (p_ch_ctx_array->chstate != IPA_HW_MHI_CHANNEL_STATE_RUN) { + IPA_UT_LOG("chstate is not running! ch %d chstate %s\n", + IPA_MHI_TEST_FIRST_CHANNEL_ID, + MHI_STATE_STR(p_ch_ctx_array->chstate)); + IPA_UT_TEST_FAIL_REPORT("channel state not run"); + return -EFAULT; + } + } + + return 0; +} + +/** + * To be run during test + * Do resume and check channel state to be running + */ +static int ipa_test_mhi_resume(void) +{ + int rc; + struct ipa_mhi_mmio_register_set *p_mmio; + struct ipa_mhi_channel_context_array *p_ch_ctx_array; + u64 phys_addr; + + rc = ipa_mhi_resume(); + if (rc) { + IPA_UT_LOG("resume failed %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("resume failed"); + return -EFAULT; + } + + p_mmio = test_mhi_ctx->mmio_buf.base; + + phys_addr = p_mmio->ccabap + ((IPA_MHI_TEST_FIRST_CHANNEL_ID + 1) * + sizeof(struct ipa_mhi_channel_context_array)); + p_ch_ctx_array = test_mhi_ctx->ch_ctx_array.base + + (phys_addr - test_mhi_ctx->ch_ctx_array.phys_base); + if (p_ch_ctx_array->chstate != IPA_HW_MHI_CHANNEL_STATE_RUN) { + IPA_UT_LOG("chstate is not running! ch %d chstate %s\n", + IPA_MHI_TEST_FIRST_CHANNEL_ID + 1, + MHI_STATE_STR(p_ch_ctx_array->chstate)); + IPA_UT_TEST_FAIL_REPORT("channel state not run"); + return -EFAULT; + } + + phys_addr = p_mmio->ccabap + ((IPA_MHI_TEST_FIRST_CHANNEL_ID) * + sizeof(struct ipa_mhi_channel_context_array)); + p_ch_ctx_array = test_mhi_ctx->ch_ctx_array.base + + (phys_addr - test_mhi_ctx->ch_ctx_array.phys_base); + if (p_ch_ctx_array->chstate != IPA_HW_MHI_CHANNEL_STATE_RUN) { + IPA_UT_LOG("chstate is not running! ch %d chstate %s\n", + IPA_MHI_TEST_FIRST_CHANNEL_ID, + MHI_STATE_STR(p_ch_ctx_array->chstate)); + IPA_UT_TEST_FAIL_REPORT("channel state not run"); + return -EFAULT; + } + + return 0; +} + +/** + * To be run during test + * 1. suspend + * 2. queue RE for IN and OUT and send data + * 3. should get MSI timeout due to suspend + * 4. resume + * 5. should get the MSIs now + * 6. comapre the IN and OUT buffers + */ +static int ipa_mhi_test_suspend_resume(void) +{ + int rc; + int i; + bool timeout = true; + + IPA_UT_LOG("Entry\n"); + + IPA_UT_LOG("BEFORE suspend\n"); + rc = ipa_mhi_test_suspend(false, true); + if (rc) { + IPA_UT_LOG("suspend failed %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("suspend failed"); + return rc; + } + IPA_UT_LOG("AFTER suspend\n"); + + /* invalidate spare register value (for msi) */ + memset(test_mhi_ctx->msi.base, 0xFF, test_mhi_ctx->msi.size); + + memset(test_mhi_ctx->in_buffer.base, 0, IPA_MHI_TEST_MAX_DATA_BUF_SIZE); + for (i = 0; i < IPA_MHI_TEST_MAX_DATA_BUF_SIZE; i++) + memset(test_mhi_ctx->out_buffer.base + i, i & 0xFF, 1); + + /* queue RE for IN side and trigger doorbell */ + rc = ipa_mhi_test_q_transfer_re(&test_mhi_ctx->mmio_buf, + test_mhi_ctx->xfer_ring_bufs, + test_mhi_ctx->ev_ring_bufs, + IPA_MHI_TEST_FIRST_CHANNEL_ID + 1, + &test_mhi_ctx->in_buffer, + 1, + true, + true, + false, + true); + if (rc) { + IPA_UT_LOG("ipa_mhi_test_q_transfer_re failed %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail IN q xfer re"); + return rc; + } + + /* queue REs for OUT side and trigger doorbell */ + rc = ipa_mhi_test_q_transfer_re(&test_mhi_ctx->mmio_buf, + test_mhi_ctx->xfer_ring_bufs, + test_mhi_ctx->ev_ring_bufs, + IPA_MHI_TEST_FIRST_CHANNEL_ID, + &test_mhi_ctx->out_buffer, + 1, + true, + true, + false, + true); + + if (rc) { + IPA_UT_LOG("ipa_mhi_test_q_transfer_re failed %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail OUT q xfer re"); + return rc; + } + + IPA_MHI_TEST_CHECK_MSI_INTR(true, timeout); + if (!timeout) { + IPA_UT_LOG("Error: transfer success on suspend\n"); + IPA_UT_TEST_FAIL_REPORT("xfer suceeded unexpectedly"); + return -EFAULT; + } + + IPA_UT_LOG("BEFORE resume\n"); + rc = ipa_test_mhi_resume(); + if (rc) { + IPA_UT_LOG("ipa_mhi_resume failed %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("resume fail"); + return rc; + } + IPA_UT_LOG("AFTER resume\n"); + + IPA_MHI_TEST_CHECK_MSI_INTR(true, timeout); + if (timeout) { + IPA_UT_LOG("Error: transfer timeout\n"); + IPA_UT_TEST_FAIL_REPORT("xfer timeout"); + return -EFAULT; + } + + /* compare the two buffers */ + if (memcmp(test_mhi_ctx->in_buffer.base, + test_mhi_ctx->out_buffer.base, + IPA_MHI_TEST_MAX_DATA_BUF_SIZE)) { + IPA_UT_LOG("Error: buffers are not equal\n"); + IPA_UT_TEST_FAIL_REPORT("non-equal buffers after xfer"); + return -EFAULT; + } + + return 0; +} + +/** + * To be run during test + * 1. enable aggregation + * 2. queue IN RE (ring element) + * 3. allocate skb with data + * 4. send it (this will create open aggr frame) + */ +static int ipa_mhi_test_create_aggr_open_frame(void) +{ + struct ipa_ep_cfg_aggr ep_aggr; + struct sk_buff *skb; + int rc; + int i; + u64 aggr_state_active; + enum ipa_hw_type ipa_ver; + + IPA_UT_LOG("Entry\n"); + + memset(&ep_aggr, 0, sizeof(ep_aggr)); + ep_aggr.aggr_en = IPA_ENABLE_AGGR; + ep_aggr.aggr = IPA_GENERIC; + ep_aggr.aggr_pkt_limit = 2; + + rc = ipa3_cfg_ep_aggr(test_mhi_ctx->cons_hdl, &ep_aggr); + if (rc) { + IPA_UT_LOG("failed to configure aggr"); + IPA_UT_TEST_FAIL_REPORT("failed to configure aggr"); + return rc; + } + + /* invalidate spare register value (for msi) */ + memset(test_mhi_ctx->msi.base, 0xFF, test_mhi_ctx->msi.size); + + /* queue RE for IN side and trigger doorbell */ + rc = ipa_mhi_test_q_transfer_re(&test_mhi_ctx->mmio_buf, + test_mhi_ctx->xfer_ring_bufs, + test_mhi_ctx->ev_ring_bufs, + IPA_MHI_TEST_FIRST_CHANNEL_ID + 1, + &test_mhi_ctx->in_buffer, + 1, + true, + true, + false, + true); + if (rc) { + IPA_UT_LOG("ipa_mhi_test_q_transfer_re failed %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail IN q xfer re"); + return rc; + } + + skb = dev_alloc_skb(IPA_MHI_TEST_MAX_DATA_BUF_SIZE); + if (!skb) { + IPA_UT_LOG("non mem for skb\n"); + IPA_UT_TEST_FAIL_REPORT("fail alloc skb"); + return -ENOMEM; + } + skb_put(skb, IPA_MHI_TEST_MAX_DATA_BUF_SIZE); + for (i = 0; i < IPA_MHI_TEST_MAX_DATA_BUF_SIZE; i++) { + memset(skb->data + i, i & 0xFF, 1); + memset(test_mhi_ctx->out_buffer.base + i, i & 0xFF, 1); + } + + rc = ipa_tx_dp(IPA_CLIENT_TEST_PROD, skb, NULL); + if (rc) { + IPA_UT_LOG("ipa_tx_dp failed %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("ipa tx dp fail"); + return rc; + } + + msleep(20); + + ipa_ver = ipa_get_hw_type(); + if (ipa_ver >= IPA_HW_v5_0) { + aggr_state_active = + (u64)ipahal_read_ep_reg_n(IPA_STATE_AGGR_ACTIVE_n, 0, + test_mhi_ctx->cons_hdl) | + (((u64)ipahal_read_ep_reg_n(IPA_STATE_AGGR_ACTIVE_n, 1, + test_mhi_ctx->cons_hdl)) << 32); + } else { + aggr_state_active = + (u64)ipahal_read_reg(IPA_STATE_AGGR_ACTIVE); + } + + IPA_UT_LOG("IPA_STATE_AGGR_ACTIVE 0x%x\n", aggr_state_active); + if (aggr_state_active == 0) { + IPA_UT_LOG("No aggregation frame open!\n"); + IPA_UT_TEST_FAIL_REPORT("No aggregation frame open"); + return -EFAULT; + } + + return 0; +} + +/** + * To be run during test + * 1. create open aggr by sending data + * 2. suspend - if force it should succeed, otherwize it fails + * 3. if force - wait for wakeup event - it should arrive + * 4. if force - resume + * 5. force close the aggr. + * 6. wait for MSI - it should arrive + * 7. compare IN and OUT buffers + * 8. disable aggr. + */ +static int ipa_mhi_test_suspend_aggr_open(bool force) +{ + int rc; + struct ipa_ep_cfg_aggr ep_aggr; + bool timeout = true; + + IPA_UT_LOG("Entry\n"); + + rc = ipa_mhi_test_create_aggr_open_frame(); + if (rc) { + IPA_UT_LOG("failed create open aggr\n"); + IPA_UT_TEST_FAIL_REPORT("fail create open aggr"); + return rc; + } + + if (force) + reinit_completion(&mhi_test_wakeup_comp); + + IPA_UT_LOG("BEFORE suspend\n"); + /** + * if suspend force, then suspend should succeed. + * otherwize it should fail due to open aggr. + */ + rc = ipa_mhi_test_suspend(force, force); + if (rc) { + IPA_UT_LOG("suspend failed %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("suspend fail"); + return rc; + } + IPA_UT_LOG("AFTER suspend\n"); + + if (force) { + if (!wait_for_completion_timeout(&mhi_test_wakeup_comp, HZ)) { + IPA_UT_LOG("timeout waiting for wakeup event\n"); + IPA_UT_TEST_FAIL_REPORT("timeout waitinf wakeup event"); + return -ETIME; + } + + IPA_UT_LOG("BEFORE resume\n"); + rc = ipa_test_mhi_resume(); + if (rc) { + IPA_UT_LOG("resume failed %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("resume failed"); + return rc; + } + IPA_UT_LOG("AFTER resume\n"); + } + + if (ipa_get_hw_type() >= IPA_HW_v5_0) + ipahal_write_ep_reg(IPA_AGGR_FORCE_CLOSE_n, + test_mhi_ctx->cons_hdl, + ipahal_get_ep_bit(test_mhi_ctx->cons_hdl)); + else + ipahal_write_reg(IPA_AGGR_FORCE_CLOSE, + ipahal_get_ep_bit(test_mhi_ctx->cons_hdl)); + + IPA_MHI_TEST_CHECK_MSI_INTR(false, timeout); + if (timeout) { + IPA_UT_LOG("fail: transfer not completed\n"); + IPA_UT_TEST_FAIL_REPORT("timeout on transferring data"); + return -EFAULT; + } + + /* compare the two buffers */ + if (memcmp(test_mhi_ctx->in_buffer.base, + test_mhi_ctx->out_buffer.base, + IPA_MHI_TEST_MAX_DATA_BUF_SIZE)) { + IPA_UT_LOG("fail: buffer are not equal\n"); + IPA_UT_TEST_FAIL_REPORT("non-equal buffers after xfer"); + return -EFAULT; + } + + memset(&ep_aggr, 0, sizeof(ep_aggr)); + rc = ipa3_cfg_ep_aggr(test_mhi_ctx->cons_hdl, &ep_aggr); + if (rc) { + IPA_UT_LOG("failed to configure aggr"); + IPA_UT_TEST_FAIL_REPORT("fail to disable aggr"); + return rc; + } + + return 0; +} + +/** + * To be run during test + * 1. suspend + * 2. queue IN RE (ring element) + * 3. allocate skb with data + * 4. send it (this will create open aggr frame) + * 5. wait for wakeup event - it should arrive + * 6. resume + * 7. wait for MSI - it should arrive + * 8. compare IN and OUT buffers + */ +static int ipa_mhi_test_suspend_host_wakeup(void) +{ + int rc; + int i; + bool timeout = true; + struct sk_buff *skb; + + reinit_completion(&mhi_test_wakeup_comp); + + IPA_UT_LOG("BEFORE suspend\n"); + rc = ipa_mhi_test_suspend(false, true); + if (rc) { + IPA_UT_LOG("suspend failed %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("suspend fail"); + return rc; + } + IPA_UT_LOG("AFTER suspend\n"); + + /* invalidate spare register value (for msi) */ + memset(test_mhi_ctx->msi.base, 0xFF, test_mhi_ctx->msi.size); + + memset(test_mhi_ctx->in_buffer.base, 0, IPA_MHI_TEST_MAX_DATA_BUF_SIZE); + /* queue RE for IN side and trigger doorbell*/ + rc = ipa_mhi_test_q_transfer_re(&test_mhi_ctx->mmio_buf, + test_mhi_ctx->xfer_ring_bufs, + test_mhi_ctx->ev_ring_bufs, + IPA_MHI_TEST_FIRST_CHANNEL_ID + 1, + &test_mhi_ctx->in_buffer, + 1, + true, + true, + false, + true); + + if (rc) { + IPA_UT_LOG("ipa_mhi_test_q_transfer_re failed %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail IN q xfer re"); + return rc; + } + + skb = dev_alloc_skb(IPA_MHI_TEST_MAX_DATA_BUF_SIZE); + if (!skb) { + IPA_UT_LOG("non mem for skb\n"); + IPA_UT_TEST_FAIL_REPORT("no mem for skb"); + return -ENOMEM; + } + skb_put(skb, IPA_MHI_TEST_MAX_DATA_BUF_SIZE); + for (i = 0; i < IPA_MHI_TEST_MAX_DATA_BUF_SIZE; i++) { + memset(skb->data + i, i & 0xFF, 1); + memset(test_mhi_ctx->out_buffer.base + i, i & 0xFF, 1); + } + + rc = ipa_tx_dp(IPA_CLIENT_TEST_PROD, skb, NULL); + if (rc) { + IPA_UT_LOG("ipa_tx_dp failed %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("ipa tx dp fail"); + return rc; + } + + if (wait_for_completion_timeout(&mhi_test_wakeup_comp, + msecs_to_jiffies(3500)) == 0) { + IPA_UT_LOG("timeout waiting for wakeup event\n"); + IPA_UT_TEST_FAIL_REPORT("timeout waiting for wakeup event"); + return -ETIME; + } + + IPA_UT_LOG("BEFORE resume\n"); + rc = ipa_test_mhi_resume(); + if (rc) { + IPA_UT_LOG("resume failed %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("resume fail"); + return rc; + } + IPA_UT_LOG("AFTER resume\n"); + + /* check for MSI interrupt one channels */ + IPA_MHI_TEST_CHECK_MSI_INTR(false, timeout); + if (timeout) { + IPA_UT_LOG("fail: transfer timeout\n"); + IPA_UT_TEST_FAIL_REPORT("timeout on xfer"); + return -EFAULT; + } + + /* compare the two buffers */ + if (memcmp(test_mhi_ctx->in_buffer.base, + test_mhi_ctx->out_buffer.base, + IPA_MHI_TEST_MAX_DATA_BUF_SIZE)) { + IPA_UT_LOG("fail: buffer are not equal\n"); + IPA_UT_TEST_FAIL_REPORT("non-equal buffers after xfer"); + return -EFAULT; + } + + return 0; +} + +/** + * To be run during test + * 1. queue OUT RE/buffer + * 2. wait for MSI on OUT + * 3. Do 1. and 2. till got MSI wait timeout (ch full / holb) + */ +static int ipa_mhi_test_create_full_channel(int *submitted_packets) +{ + int i; + bool timeout = true; + int rc; + + if (!submitted_packets) { + IPA_UT_LOG("Input error\n"); + return -EINVAL; + } + + *submitted_packets = 0; + + for (i = 0; i < IPA_MHI_TEST_MAX_DATA_BUF_SIZE; i++) + memset(test_mhi_ctx->out_buffer.base + i, i & 0xFF, 1); + + do { + /* invalidate spare register value (for msi) */ + memset(test_mhi_ctx->msi.base, 0xFF, test_mhi_ctx->msi.size); + + IPA_UT_LOG("submitting OUT buffer\n"); + timeout = true; + /* queue REs for OUT side and trigger doorbell */ + rc = ipa_mhi_test_q_transfer_re(&test_mhi_ctx->mmio_buf, + test_mhi_ctx->xfer_ring_bufs, + test_mhi_ctx->ev_ring_bufs, + IPA_MHI_TEST_FIRST_CHANNEL_ID, + &test_mhi_ctx->out_buffer, + 1, + true, + true, + false, + true); + if (rc) { + IPA_UT_LOG("ipa_mhi_test_q_transfer_re failed %d\n", + rc); + IPA_UT_TEST_FAIL_REPORT("fail OUT q re"); + return rc; + } + (*submitted_packets)++; + + IPA_UT_LOG("waiting for MSI\n"); + for (i = 0; i < 10; i++) { + if (*((u32 *)test_mhi_ctx->msi.base) == + (0x10000000 | + (IPA_MHI_TEST_FIRST_EVENT_RING_ID))) { + IPA_UT_LOG("got MSI\n"); + timeout = false; + break; + } + msleep(20); + } + } while (!timeout); + + return 0; +} + +/** + * To be run during test + * 1. queue OUT RE/buffer + * 2. wait for MSI on OUT + * 3. Do 1. and 2. till got MSI wait timeout (ch full) + * 4. suspend - it should fail with -EAGAIN - M1 is rejected + * 5. foreach submitted pkt, do the next steps + * 6. queue IN RE/buffer + * 7. wait for MSI + * 8. compare IN and OUT buffers + */ +static int ipa_mhi_test_suspend_full_channel(bool force) +{ + int rc; + bool timeout; + int submitted_packets = 0; + + rc = ipa_mhi_test_create_full_channel(&submitted_packets); + if (rc) { + IPA_UT_LOG("fail create full channel\n"); + IPA_UT_TEST_FAIL_REPORT("fail create full channel"); + return rc; + } + + IPA_UT_LOG("BEFORE suspend\n"); + rc = ipa_mhi_test_suspend(force, false); + if (rc) { + IPA_UT_LOG("ipa_mhi_suspend did not returned -EAGAIN. rc %d\n", + rc); + IPA_UT_TEST_FAIL_REPORT("test suspend fail"); + return -EFAULT; + } + IPA_UT_LOG("AFTER suspend\n"); + + while (submitted_packets) { + memset(test_mhi_ctx->in_buffer.base, 0, + IPA_MHI_TEST_MAX_DATA_BUF_SIZE); + + /* invalidate spare register value (for msi) */ + memset(test_mhi_ctx->msi.base, 0xFF, test_mhi_ctx->msi.size); + + timeout = true; + /* queue RE for IN side and trigger doorbell */ + rc = ipa_mhi_test_q_transfer_re(&test_mhi_ctx->mmio_buf, + test_mhi_ctx->xfer_ring_bufs, + test_mhi_ctx->ev_ring_bufs, + IPA_MHI_TEST_FIRST_CHANNEL_ID + 1, + &test_mhi_ctx->in_buffer, + 1, + true, + true, + false, + true); + if (rc) { + IPA_UT_LOG("ipa_mhi_test_q_transfer_re failed %d\n", + rc); + IPA_UT_TEST_FAIL_REPORT("fail IN q re"); + return rc; + } + + IPA_MHI_TEST_CHECK_MSI_INTR(true, timeout); + if (timeout) { + IPA_UT_LOG("transfer failed - timeout\n"); + IPA_UT_TEST_FAIL_REPORT("timeout on xfer"); + return -EFAULT; + } + + /* compare the two buffers */ + if (memcmp(test_mhi_ctx->in_buffer.base, + test_mhi_ctx->out_buffer.base, + IPA_MHI_TEST_MAX_DATA_BUF_SIZE)) { + IPA_UT_LOG("buffer are not equal\n"); + IPA_UT_TEST_FAIL_REPORT("non-equal buffers after xfer"); + return -EFAULT; + } + + submitted_packets--; + } + + return 0; +} + +/** + * To be called from test + * 1. suspend + * 2. reset to M0 state + */ +static int ipa_mhi_test_suspend_and_reset(struct ipa_test_mhi_context *ctx) +{ + int rc; + + IPA_UT_LOG("BEFORE suspend\n"); + rc = ipa_mhi_test_suspend(false, true); + if (rc) { + IPA_UT_LOG("suspend failed %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("suspend fail"); + return rc; + } + IPA_UT_LOG("AFTER suspend\n"); + + rc = ipa_mhi_test_reset(ctx, false); + if (rc) { + IPA_UT_LOG("reset failed rc=%d", rc); + IPA_UT_TEST_FAIL_REPORT("reset fail"); + return rc; + } + + return 0; +} + +/** + * To be run during test + * 1. manualy update wp + * 2. suspend - should succeed + * 3. restore wp value + */ +static int ipa_mhi_test_suspend_wp_update(void) +{ + int rc; + struct ipa_mhi_mmio_register_set *p_mmio; + struct ipa_mhi_channel_context_array *p_ch_ctx_array; + u64 old_wp; + u64 phys_addr; + + /* simulate a write by updating the wp */ + p_mmio = test_mhi_ctx->mmio_buf.base; + phys_addr = p_mmio->ccabap + ((IPA_MHI_TEST_FIRST_CHANNEL_ID) * + sizeof(struct ipa_mhi_channel_context_array)); + p_ch_ctx_array = test_mhi_ctx->ch_ctx_array.base + + (phys_addr - test_mhi_ctx->ch_ctx_array.phys_base); + old_wp = p_ch_ctx_array->wp; + p_ch_ctx_array->wp += 16; + + IPA_UT_LOG("BEFORE suspend\n"); + rc = ipa_mhi_test_suspend(false, false); + if (rc) { + IPA_UT_LOG("suspend failed rc %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("suspend fail"); + p_ch_ctx_array->wp = old_wp; + return rc; + } + IPA_UT_LOG("AFTER suspend\n"); + + p_ch_ctx_array->wp = old_wp; + + return 0; +} + +/** + * To be run during test + * 1. create open aggr by sending data + * 2. channel reset (disconnect/connet) + * 3. validate no aggr. open after reset + * 4. disable aggr. + */ +static int ipa_mhi_test_channel_reset_aggr_open(void) +{ + int rc; + u32 aggr_state_active; + struct ipa_ep_cfg_aggr ep_aggr; + enum ipa_hw_type ipa_ver; + + IPA_UT_LOG("Entry\n"); + + rc = ipa_mhi_test_create_aggr_open_frame(); + if (rc) { + IPA_UT_LOG("failed create open aggr rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail creare open aggr frame"); + return rc; + } + + rc = ipa_mhi_test_channel_reset(); + if (rc) { + IPA_UT_LOG("channel reset failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("channel reset fail"); + return rc; + } + + ipa_ver = ipa_get_hw_type(); + if (ipa_ver >= IPA_HW_v5_0) { + aggr_state_active = + ipahal_read_ep_reg(IPA_STATE_AGGR_ACTIVE_n, + test_mhi_ctx->cons_hdl); + } else { + aggr_state_active = + ipahal_read_reg(IPA_STATE_AGGR_ACTIVE); + } + + IPADBG("IPA_STATE_AGGR_ACTIVE 0x%x\n", aggr_state_active); + if (aggr_state_active != 0) { + IPA_UT_LOG("aggregation frame open after reset!\n"); + IPA_UT_LOG("IPA_STATE_AGGR_ACTIVE 0x%x\n", aggr_state_active); + IPA_UT_TEST_FAIL_REPORT("open aggr after reset"); + return -EFAULT; + } + + memset(&ep_aggr, 0, sizeof(ep_aggr)); + rc = ipa3_cfg_ep_aggr(test_mhi_ctx->cons_hdl, &ep_aggr); + if (rc) { + IPA_UT_LOG("failed to configure aggr"); + IPA_UT_TEST_FAIL_REPORT("fail to disable aggr"); + return rc; + } + + return rc; +} + +/** + * To be run during test + * 1. queue OUT RE/buffer + * 2. wait for MSI on OUT + * 3. Do 1. and 2. till got MSI wait timeout (ch full) + * 4. channel reset + * disconnect and reconnect the prod and cons + * 5. queue IN RE/buffer and ring DB + * 6. wait for MSI - should get timeout as channels were reset + * 7. reset again + */ +static int ipa_mhi_test_channel_reset_ipa_holb(void) +{ + int rc; + int submitted_packets = 0; + bool timeout; + + IPA_UT_LOG("Entry\n"); + + rc = ipa_mhi_test_create_full_channel(&submitted_packets); + if (rc) { + IPA_UT_LOG("fail create full channel rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail create full channel"); + return rc; + } + + rc = ipa_mhi_test_channel_reset(); + if (rc) { + IPA_UT_LOG("channel reset failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("channel reset fail"); + return rc; + } + + /* invalidate spare register value (for msi) */ + memset(test_mhi_ctx->msi.base, 0xFF, test_mhi_ctx->msi.size); + timeout = true; + /* queue RE for IN side and trigger doorbell */ + rc = ipa_mhi_test_q_transfer_re(&test_mhi_ctx->mmio_buf, + test_mhi_ctx->xfer_ring_bufs, + test_mhi_ctx->ev_ring_bufs, + IPA_MHI_TEST_FIRST_CHANNEL_ID + 1, + &test_mhi_ctx->in_buffer, + 1, + true, + true, + false, + true); + + if (rc) { + IPA_UT_LOG("ipa_mhi_test_q_transfer_re failed %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail IN q re"); + return rc; + } + submitted_packets--; + + IPA_MHI_TEST_CHECK_MSI_INTR(true, timeout); + if (!timeout) { + IPA_UT_LOG("transfer succeed although we had reset\n"); + IPA_UT_TEST_FAIL_REPORT("xfer succeed although we had reset"); + return -EFAULT; + } + + rc = ipa_mhi_test_channel_reset(); + if (rc) { + IPA_UT_LOG("channel reset failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("channel reset fail"); + return rc; + } + + return rc; +} + + +/** + * TEST: mhi reset in READY state + * 1. init to ready state (without start and connect) + * 2. reset (destroy and re-init) + * 2. destroy + */ +static int ipa_mhi_test_reset_ready_state(void *priv) +{ + int rc; + struct ipa_test_mhi_context *ctx = (struct ipa_test_mhi_context *)priv; + + IPA_UT_LOG("Test Start\n"); + + if (unlikely(!ctx)) { + IPA_UT_LOG("No context"); + return -EFAULT; + } + + rc = ipa_mhi_test_initialize_driver(true); + if (rc) { + IPA_UT_LOG("init to Ready state failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("fail to init to ready state"); + return rc; + } + + rc = ipa_mhi_test_reset(ctx, true); + if (rc) { + IPA_UT_LOG("reset failed rc=%d", rc); + IPA_UT_TEST_FAIL_REPORT("reset (destroy/re-init) failed"); + return rc; + } + + rc = ipa_mhi_test_destroy(ctx); + if (rc) { + IPA_UT_LOG("destroy failed rc=%d", rc); + IPA_UT_TEST_FAIL_REPORT("destroy failed"); + return rc; + } + + return 0; +} + +/** + * TEST: mhi reset in M0 state + * 1. init to M0 state (with start and connect) + * 2. reset (destroy and re-init) + * 2. destroy + */ +static int ipa_mhi_test_reset_m0_state(void *priv) +{ + int rc; + struct ipa_test_mhi_context *ctx = (struct ipa_test_mhi_context *)priv; + + IPA_UT_LOG("Test Start\n"); + + if (unlikely(!ctx)) { + IPA_UT_LOG("No context"); + return -EFAULT; + } + + rc = ipa_mhi_test_initialize_driver(false); + if (rc) { + IPA_UT_LOG("init to M0 state failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT + ("fail to init to M0 state (w/ start and connect)"); + return rc; + } + + rc = ipa_mhi_test_reset(ctx, false); + if (rc) { + IPA_UT_LOG("reset failed rc=%d", rc); + IPA_UT_TEST_FAIL_REPORT("reset (destroy/re-init) failed"); + return rc; + } + + rc = ipa_mhi_test_destroy(ctx); + if (rc) { + IPA_UT_LOG("destroy failed rc=%d", rc); + IPA_UT_TEST_FAIL_REPORT("destroy failed"); + return rc; + } + + return 0; +} + +/** + * TEST: mhi in-loop reset in M0 state + * 1. init to M0 state (with start and connect) + * 2. reset (destroy and re-init) in-loop + * 3. destroy + */ +static int ipa_mhi_test_inloop_reset_m0_state(void *priv) +{ + int rc; + struct ipa_test_mhi_context *ctx = (struct ipa_test_mhi_context *)priv; + + IPA_UT_LOG("Test Start\n"); + + if (unlikely(!ctx)) { + IPA_UT_LOG("No context"); + return -EFAULT; + } + + rc = ipa_mhi_test_initialize_driver(false); + if (rc) { + IPA_UT_LOG("init to M0 state failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT + ("fail to init to M0 state (w/ start and connect)"); + return rc; + } + + IPA_MHI_RUN_TEST_UNIT_IN_LOOP(ipa_mhi_test_reset, rc, ctx, false); + if (rc) { + IPA_UT_LOG("in-loop reset failed rc=%d", rc); + IPA_UT_TEST_FAIL_REPORT( + "reset (destroy/re-init) in loop failed"); + return rc; + } + + rc = ipa_mhi_test_destroy(ctx); + if (rc) { + IPA_UT_LOG("destroy failed rc=%d", rc); + IPA_UT_TEST_FAIL_REPORT("destroy failed"); + return rc; + } + + return 0; +} + +/** + * TEST: mhi loopback data with reset + * 1. init to M0 state (with start and connect) + * 2. reset (destroy and re-init) + * 3. loopback data + * 4. reset (destroy and re-init) + * 5. loopback data again + * 6. destroy + */ +static int ipa_mhi_test_loopback_data_with_reset(void *priv) +{ + int rc; + struct ipa_test_mhi_context *ctx = (struct ipa_test_mhi_context *)priv; + + IPA_UT_LOG("Test Start\n"); + + if (unlikely(!ctx)) { + IPA_UT_LOG("No context"); + return -EFAULT; + } + + rc = ipa_mhi_test_initialize_driver(false); + if (rc) { + IPA_UT_LOG("init to M0 state failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT( + "fail to init to M0 state (w/ start and connect)"); + return rc; + } + + rc = ipa_mhi_test_reset(ctx, false); + if (rc) { + IPA_UT_LOG("reset failed rc=%d", rc); + IPA_UT_TEST_FAIL_REPORT("reset (destroy/re-init) failed"); + return rc; + } + + IPA_MHI_RUN_TEST_UNIT_IN_LOOP(ipa_mhi_test_loopback_data_transfer, rc); + if (rc) { + IPA_UT_LOG("data loopback failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("loopback data in loop failed"); + return rc; + } + + rc = ipa_mhi_test_reset(ctx, false); + if (rc) { + IPA_UT_LOG("reset failed rc=%d", rc); + IPA_UT_TEST_FAIL_REPORT("reset (destroy/re-init) failed"); + return rc; + } + + IPA_MHI_RUN_TEST_UNIT_IN_LOOP(ipa_mhi_test_loopback_data_transfer, rc); + if (rc) { + IPA_UT_LOG("data loopback failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("loopback data in loop failed"); + return rc; + } + + rc = ipa_mhi_test_destroy(ctx); + if (rc) { + IPA_UT_LOG("destroy failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("destroy failed"); + return rc; + } + + return 0; +} + +/** + * TEST: mhi reset in suspend state + * 1. init to M0 state (with start and connect) + * 2. suspend + * 3. reset (destroy and re-init) + * 4. destroy + */ +static int ipa_mhi_test_reset_on_suspend(void *priv) +{ + int rc; + struct ipa_test_mhi_context *ctx = (struct ipa_test_mhi_context *)priv; + + IPA_UT_LOG("Test Start\n"); + + if (unlikely(!ctx)) { + IPA_UT_LOG("No context"); + return -EFAULT; + } + + rc = ipa_mhi_test_initialize_driver(false); + if (rc) { + IPA_UT_LOG("init to M0 state failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT( + "fail to init to M0 state (w/ start and connect)"); + return -EFAULT; + } + + rc = ipa_mhi_test_suspend_and_reset(ctx); + if (rc) { + IPA_UT_LOG("suspend and reset failed %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("suspend and then reset failed"); + return rc; + } + + rc = ipa_mhi_test_destroy(ctx); + if (rc) { + IPA_UT_LOG("destroy failed %d\n", rc); + IPA_UT_TEST_FAIL_REPORT("destroy failed"); + return -EFAULT; + } + + return 0; +} + +/** + * TEST: mhi in-loop reset in suspend state + * 1. init to M0 state (with start and connect) + * 2. suspend + * 3. reset (destroy and re-init) + * 4. Do 2 and 3 in loop + * 3. destroy + */ +static int ipa_mhi_test_inloop_reset_on_suspend(void *priv) +{ + int rc; + struct ipa_test_mhi_context *ctx = (struct ipa_test_mhi_context *)priv; + + IPA_UT_LOG("Test Start\n"); + + if (unlikely(!ctx)) { + IPA_UT_LOG("No context"); + return -EFAULT; + } + + rc = ipa_mhi_test_initialize_driver(false); + if (rc) { + IPA_UT_LOG("init to M0 state failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT( + "fail to init to M0 state (w/ start and connect)"); + return rc; + } + + IPA_MHI_RUN_TEST_UNIT_IN_LOOP(ipa_mhi_test_suspend_and_reset, rc, ctx); + if (rc) { + IPA_UT_LOG("in-loop reset in suspend failed rc=%d", rc); + IPA_UT_TEST_FAIL_REPORT("fail to in-loop reset while suspend"); + return rc; + } + + rc = ipa_mhi_test_destroy(ctx); + if (rc) { + IPA_UT_LOG("destroy failed rc=%d", rc); + IPA_UT_TEST_FAIL_REPORT("destroy failed"); + return rc; + } + + return 0; +} + +/** + * TEST: mhi loopback data with reset + * 1. init to M0 state (with start and connect) + * 2. suspend + * 3. reset (destroy and re-init) + * 4. loopback data + * 5. suspend + * 5. reset (destroy and re-init) + * 6. destroy + */ +static int ipa_mhi_test_loopback_data_with_reset_on_suspend(void *priv) +{ + int rc; + struct ipa_test_mhi_context *ctx = (struct ipa_test_mhi_context *)priv; + + IPA_UT_LOG("Test Start\n"); + + if (unlikely(!ctx)) { + IPA_UT_LOG("No context"); + return -EFAULT; + } + + rc = ipa_mhi_test_initialize_driver(false); + if (rc) { + IPA_UT_LOG("init to M0 state failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT( + "fail to init to M0 state (w/ start and connect)"); + return rc; + } + + rc = ipa_mhi_test_suspend_and_reset(ctx); + if (rc) { + IPA_UT_LOG("suspend and reset failed rc=%d", rc); + IPA_UT_TEST_FAIL_REPORT("fail to suspend and then reset"); + return rc; + } + + IPA_MHI_RUN_TEST_UNIT_IN_LOOP(ipa_mhi_test_loopback_data_transfer, rc); + if (rc) { + IPA_UT_LOG("data loopback failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("loopback data in loop failed"); + return rc; + } + + rc = ipa_mhi_test_suspend_and_reset(ctx); + if (rc) { + IPA_UT_LOG("suspend and reset failed rc=%d", rc); + IPA_UT_TEST_FAIL_REPORT("fail to suspend and then reset"); + return rc; + } + + rc = ipa_mhi_test_destroy(ctx); + if (rc) { + IPA_UT_LOG("destroy failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("destroy failed"); + return rc; + } + + return 0; +} + +/** + * TEST: mhi loopback data after in loop suspend/resume + * 1. init to M0 state (with start and connect) + * 2. in loop suspend/resume + * 3. loopback data + * 4. destroy + */ +static int ipa_mhi_test_in_loop_suspend_resume(void *priv) +{ + int rc; + struct ipa_test_mhi_context *ctx = (struct ipa_test_mhi_context *)priv; + + IPA_UT_LOG("Test Start\n"); + + if (unlikely(!ctx)) { + IPA_UT_LOG("No context"); + return -EFAULT; + } + + rc = ipa_mhi_test_initialize_driver(false); + if (rc) { + IPA_UT_LOG("init to M0 state failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT( + "fail to init to M0 state (w/ start and connect)"); + return rc; + } + + IPA_MHI_RUN_TEST_UNIT_IN_LOOP(ipa_mhi_test_suspend_resume, rc); + if (rc) { + IPA_UT_LOG("suspend resume failed rc=%d", rc); + IPA_UT_TEST_FAIL_REPORT("in loop suspend/resume failed"); + return rc; + } + + IPA_MHI_RUN_TEST_UNIT_IN_LOOP(ipa_mhi_test_loopback_data_transfer, rc); + if (rc) { + IPA_UT_LOG("data loopback failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("loopback data in loop failed"); + return rc; + } + + rc = ipa_mhi_test_destroy(ctx); + if (rc) { + IPA_UT_LOG("destroy failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("destroy failed"); + return rc; + } + + return 0; +} + +/** + * TEST: mhi loopback data after in loop suspend/resume with aggr open + * 1. init to M0 state (with start and connect) + * 2. in loop suspend/resume with open aggr. + * 3. loopback data + * 4. destroy + */ +static int ipa_mhi_test_in_loop_suspend_resume_aggr_open(void *priv) +{ + int rc; + struct ipa_test_mhi_context *ctx = (struct ipa_test_mhi_context *)priv; + + IPA_UT_LOG("Test Start\n"); + + if (unlikely(!ctx)) { + IPA_UT_LOG("No context"); + return -EFAULT; + } + + rc = ipa_mhi_test_initialize_driver(false); + if (rc) { + IPA_UT_LOG("init to M0 state failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT( + "fail to init to M0 state (w/ start and connect)"); + return rc; + } + + IPA_MHI_RUN_TEST_UNIT_IN_LOOP(ipa_mhi_test_suspend_aggr_open, + rc, false); + if (rc) { + IPA_UT_LOG("suspend resume with aggr open failed rc=%d", rc); + IPA_UT_TEST_FAIL_REPORT( + "in loop suspend/resume with open aggr failed"); + return rc; + } + + IPA_MHI_RUN_TEST_UNIT_IN_LOOP(ipa_mhi_test_loopback_data_transfer, rc); + if (rc) { + IPA_UT_LOG("data loopback failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("loopback data in loop failed"); + return rc; + } + + rc = ipa_mhi_test_destroy(ctx); + if (rc) { + IPA_UT_LOG("destroy failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("destroy failed"); + return rc; + } + + return 0; +} + +/** + * TEST: mhi loopback data after in loop force suspend/resume with aggr open + * 1. init to M0 state (with start and connect) + * 2. in loop force suspend/resume with open aggr. + * 3. loopback data + * 4. destroy + */ +static int ipa_mhi_test_in_loop_force_suspend_resume_aggr_open(void *priv) +{ + int rc; + struct ipa_test_mhi_context *ctx = (struct ipa_test_mhi_context *)priv; + + IPA_UT_LOG("Test Start\n"); + + if (unlikely(!ctx)) { + IPA_UT_LOG("No context"); + return -EFAULT; + } + + rc = ipa_mhi_test_initialize_driver(false); + if (rc) { + IPA_UT_LOG("init to M0 state failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT( + "fail to init to M0 state (w/ start and connect)"); + return rc; + } + + IPA_MHI_RUN_TEST_UNIT_IN_LOOP(ipa_mhi_test_suspend_aggr_open, + rc, true); + if (rc) { + IPA_UT_LOG("force suspend resume with aggr open failed rc=%d", + rc); + IPA_UT_TEST_FAIL_REPORT( + "in loop force suspend/resume with open aggr failed"); + return rc; + } + + IPA_MHI_RUN_TEST_UNIT_IN_LOOP(ipa_mhi_test_loopback_data_transfer, rc); + if (rc) { + IPA_UT_LOG("data loopback failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("loopback data in loop failed"); + return rc; + } + + rc = ipa_mhi_test_destroy(ctx); + if (rc) { + IPA_UT_LOG("destroy failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("destroy failed"); + return rc; + } + + return 0; +} + +/** + * TEST: mhi loopback data after in loop suspend/host wakeup resume + * 1. init to M0 state (with start and connect) + * 2. in loop suspend/resume with host wakeup + * 3. loopback data + * 4. destroy + */ +static int ipa_mhi_test_in_loop_suspend_host_wakeup(void *priv) +{ + int rc; + struct ipa_test_mhi_context *ctx = (struct ipa_test_mhi_context *)priv; + + IPA_UT_LOG("Test Start\n"); + + if (unlikely(!ctx)) { + IPA_UT_LOG("No context"); + return -EFAULT; + } + + rc = ipa_mhi_test_initialize_driver(false); + if (rc) { + IPA_UT_LOG("init to M0 state failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT( + "fail to init to M0 state (w/ start and connect)"); + return rc; + } + + IPA_MHI_RUN_TEST_UNIT_IN_LOOP(ipa_mhi_test_suspend_host_wakeup, rc); + if (rc) { + IPA_UT_LOG("suspend host wakeup resume failed rc=%d", rc); + IPA_UT_TEST_FAIL_REPORT( + "in loop suspend/resume with hsot wakeup failed"); + return rc; + } + + IPA_MHI_RUN_TEST_UNIT_IN_LOOP(ipa_mhi_test_loopback_data_transfer, rc); + if (rc) { + IPA_UT_LOG("data loopback failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("loopback data in loop failed"); + return rc; + } + + rc = ipa_mhi_test_destroy(ctx); + if (rc) { + IPA_UT_LOG("destroy failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("destroy failed"); + return rc; + } + + return 0; +} + +/** + * TEST: mhi loopback data after in loop rejected suspend as full channel + * 1. init to M0 state (with start and connect) + * 2. in loop rejrected suspend + * 3. loopback data + * 4. destroy + */ +static int ipa_mhi_test_in_loop_reject_suspend_full_channel(void *priv) +{ + int rc; + struct ipa_test_mhi_context *ctx = (struct ipa_test_mhi_context *)priv; + + IPA_UT_LOG("Test Start\n"); + + if (unlikely(!ctx)) { + IPA_UT_LOG("No context"); + return -EFAULT; + } + + rc = ipa_mhi_test_initialize_driver(false); + if (rc) { + IPA_UT_LOG("init to M0 state failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT( + "fail to init to M0 state (w/ start and connect)"); + return rc; + } + + IPA_MHI_RUN_TEST_UNIT_IN_LOOP(ipa_mhi_test_suspend_full_channel, + rc, false); + if (rc) { + IPA_UT_LOG("full channel rejected suspend failed rc=%d", rc); + IPA_UT_TEST_FAIL_REPORT( + "in loop rejected suspend due to full channel failed"); + return rc; + } + + IPA_MHI_RUN_TEST_UNIT_IN_LOOP(ipa_mhi_test_loopback_data_transfer, rc); + if (rc) { + IPA_UT_LOG("data loopback failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("loopback data in loop failed"); + return rc; + } + + rc = ipa_mhi_test_destroy(ctx); + if (rc) { + IPA_UT_LOG("destroy failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("destroy failed"); + return rc; + } + + return 0; +} + +/** + * TEST: mhi loopback data after in loop rejected force suspend as full channel + * 1. init to M0 state (with start and connect) + * 2. in loop force rejected suspend + * 3. loopback data + * 4. destroy + */ +static int ipa_mhi_test_in_loop_reject_force_suspend_full_channel(void *priv) +{ + int rc; + struct ipa_test_mhi_context *ctx = (struct ipa_test_mhi_context *)priv; + + IPA_UT_LOG("Test Start\n"); + + if (unlikely(!ctx)) { + IPA_UT_LOG("No context"); + return -EFAULT; + } + + rc = ipa_mhi_test_initialize_driver(false); + if (rc) { + IPA_UT_LOG("init to M0 state failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT( + "fail to init to M0 state (w/ start and connect)"); + return rc; + } + + IPA_MHI_RUN_TEST_UNIT_IN_LOOP(ipa_mhi_test_suspend_full_channel, + rc, true); + if (rc) { + IPA_UT_LOG("full channel rejected force suspend failed rc=%d", + rc); + IPA_UT_TEST_FAIL_REPORT( + "in loop force rejected suspend as full ch failed"); + return rc; + } + + IPA_MHI_RUN_TEST_UNIT_IN_LOOP(ipa_mhi_test_loopback_data_transfer, rc); + if (rc) { + IPA_UT_LOG("data loopback failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("loopback data in loop failed"); + return rc; + } + + rc = ipa_mhi_test_destroy(ctx); + if (rc) { + IPA_UT_LOG("destroy failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("destroy failed"); + return rc; + } + + return 0; +} + +/** + * TEST: mhi loopback data after in loop suspend after wp manual update + * 1. init to M0 state (with start and connect) + * 2. in loop suspend after wp update + * 3. loopback data + * 4. destroy + */ +static int ipa_mhi_test_in_loop_suspend_resume_wp_update(void *priv) +{ + int rc; + struct ipa_test_mhi_context *ctx = (struct ipa_test_mhi_context *)priv; + + IPA_UT_LOG("Test Start\n"); + + if (unlikely(!ctx)) { + IPA_UT_LOG("No context"); + return -EFAULT; + } + + rc = ipa_mhi_test_initialize_driver(false); + if (rc) { + IPA_UT_LOG("init to M0 state failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT( + "fail to init to M0 state (w/ start and connect)"); + return rc; + } + + IPA_MHI_RUN_TEST_UNIT_IN_LOOP(ipa_mhi_test_suspend_wp_update, rc); + if (rc) { + IPA_UT_LOG("suspend after wp update failed rc=%d", rc); + IPA_UT_TEST_FAIL_REPORT( + "in loop suspend after wp update failed"); + return rc; + } + + IPA_MHI_RUN_TEST_UNIT_IN_LOOP(ipa_mhi_test_loopback_data_transfer, rc); + if (rc) { + IPA_UT_LOG("data loopback failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("loopback data in loop failed"); + return rc; + } + + rc = ipa_mhi_test_destroy(ctx); + if (rc) { + IPA_UT_LOG("destroy failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("destroy failed"); + return rc; + } + + return 0; +} + +/** + * TEST: mhi loopback data after in loop channel reset (disconnect/connect) + * 1. init to M0 state (with start and connect) + * 2. in loop channel reset (disconnect/connect) + * 3. loopback data + * 4. destroy + */ +static int ipa_mhi_test_in_loop_channel_reset(void *priv) +{ + int rc; + struct ipa_test_mhi_context *ctx = (struct ipa_test_mhi_context *)priv; + + IPA_UT_LOG("Test Start\n"); + + if (unlikely(!ctx)) { + IPA_UT_LOG("No context"); + return -EFAULT; + } + + rc = ipa_mhi_test_initialize_driver(false); + if (rc) { + IPA_UT_LOG("init to M0 state failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT( + "fail to init to M0 state (w/ start and connect)"); + return rc; + } + + IPA_MHI_RUN_TEST_UNIT_IN_LOOP(ipa_mhi_test_channel_reset, rc); + if (rc) { + IPA_UT_LOG("channel reset (disconnect/connect) failed rc=%d", + rc); + IPA_UT_TEST_FAIL_REPORT("in loop channel reset failed"); + return rc; + } + + IPA_MHI_RUN_TEST_UNIT_IN_LOOP(ipa_mhi_test_loopback_data_transfer, rc); + if (rc) { + IPA_UT_LOG("data loopback failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("loopback data in loop failed"); + return rc; + } + + rc = ipa_mhi_test_destroy(ctx); + if (rc) { + IPA_UT_LOG("destroy failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("destroy failed"); + return rc; + } + + return 0; +} + +/** + * TEST: mhi loopback data after in loop channel reset (disconnect/connect) + * 1. init to M0 state (with start and connect) + * 2. in loop channel reset (disconnect/connect) with open aggr + * 3. loopback data + * 4. destroy + */ +static int ipa_mhi_test_in_loop_channel_reset_aggr_open(void *priv) +{ + int rc; + struct ipa_test_mhi_context *ctx = (struct ipa_test_mhi_context *)priv; + + IPA_UT_LOG("Test Start\n"); + + if (unlikely(!ctx)) { + IPA_UT_LOG("No context"); + return -EFAULT; + } + + rc = ipa_mhi_test_initialize_driver(false); + if (rc) { + IPA_UT_LOG("init to M0 state failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT( + "fail to init to M0 state (w/ start and connect)"); + return rc; + } + + IPA_MHI_RUN_TEST_UNIT_IN_LOOP(ipa_mhi_test_channel_reset_aggr_open, rc); + if (rc) { + IPA_UT_LOG("channel reset (disconnect/connect) failed rc=%d", + rc); + IPA_UT_TEST_FAIL_REPORT( + "in loop channel reset with open aggr failed"); + return rc; + } + + IPA_MHI_RUN_TEST_UNIT_IN_LOOP(ipa_mhi_test_loopback_data_transfer, rc); + if (rc) { + IPA_UT_LOG("data loopback failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("loopback data in loop failed"); + return rc; + } + + rc = ipa_mhi_test_destroy(ctx); + if (rc) { + IPA_UT_LOG("destroy failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("destroy failed"); + return rc; + } + + return 0; +} + +/** + * TEST: mhi loopback data after in loop channel reset (disconnect/connect) + * 1. init to M0 state (with start and connect) + * 2. in loop channel reset (disconnect/connect) with channel in HOLB + * 3. loopback data + * 4. destroy + */ +static int ipa_mhi_test_in_loop_channel_reset_ipa_holb(void *priv) +{ + int rc; + struct ipa_test_mhi_context *ctx = (struct ipa_test_mhi_context *)priv; + + IPA_UT_LOG("Test Start\n"); + + if (unlikely(!ctx)) { + IPA_UT_LOG("No context"); + return -EFAULT; + } + + rc = ipa_mhi_test_initialize_driver(false); + if (rc) { + IPA_UT_LOG("init to M0 state failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT( + "fail to init to M0 state (w/ start and connect)"); + return rc; + } + + IPA_MHI_RUN_TEST_UNIT_IN_LOOP(ipa_mhi_test_channel_reset_ipa_holb, rc); + if (rc) { + IPA_UT_LOG("channel reset (disconnect/connect) failed rc=%d", + rc); + IPA_UT_TEST_FAIL_REPORT( + "in loop channel reset with channel HOLB failed"); + return rc; + } + + IPA_MHI_RUN_TEST_UNIT_IN_LOOP(ipa_mhi_test_loopback_data_transfer, rc); + if (rc) { + IPA_UT_LOG("data loopback failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("loopback data in loop failed"); + return rc; + } + + rc = ipa_mhi_test_destroy(ctx); + if (rc) { + IPA_UT_LOG("destroy failed rc=%d\n", rc); + IPA_UT_TEST_FAIL_REPORT("destroy failed"); + return rc; + } + + return 0; +} + +/* Suite definition block */ +IPA_UT_DEFINE_SUITE_START(mhi, "MHI for GSI", + ipa_test_mhi_suite_setup, ipa_test_mhi_suite_teardown) +{ + IPA_UT_ADD_TEST(reset_ready_state, + "reset test in Ready state", + ipa_mhi_test_reset_ready_state, + true, IPA_HW_v3_0, IPA_HW_MAX), + IPA_UT_ADD_TEST(reset_m0_state, + "reset test in M0 state", + ipa_mhi_test_reset_m0_state, + true, IPA_HW_v3_0, IPA_HW_MAX), + IPA_UT_ADD_TEST(inloop_reset_m0_state, + "several reset iterations in M0 state", + ipa_mhi_test_inloop_reset_m0_state, + true, IPA_HW_v3_0, IPA_HW_MAX), + IPA_UT_ADD_TEST(loopback_data_with_reset_on_m0, + "reset before and after loopback data in M0 state", + ipa_mhi_test_loopback_data_with_reset, + true, IPA_HW_v3_0, IPA_HW_MAX), + IPA_UT_ADD_TEST(reset_on_suspend, + "reset test in suspend state", + ipa_mhi_test_reset_on_suspend, + true, IPA_HW_v3_0, IPA_HW_MAX), + IPA_UT_ADD_TEST(inloop_reset_on_suspend, + "several reset iterations in suspend state", + ipa_mhi_test_inloop_reset_on_suspend, + true, IPA_HW_v3_0, IPA_HW_MAX), + IPA_UT_ADD_TEST(loopback_data_with_reset_on_suspend, + "reset before and after loopback data in suspend state", + ipa_mhi_test_loopback_data_with_reset_on_suspend, + true, IPA_HW_v3_0, IPA_HW_MAX), + IPA_UT_ADD_TEST(suspend_resume, + "several suspend/resume iterations", + ipa_mhi_test_in_loop_suspend_resume, + true, IPA_HW_v3_0, IPA_HW_MAX), + IPA_UT_ADD_TEST(suspend_resume_with_open_aggr, + "several suspend/resume iterations with open aggregation frame", + ipa_mhi_test_in_loop_suspend_resume_aggr_open, + true, IPA_HW_v3_0, IPA_HW_v3_5_1), + IPA_UT_ADD_TEST(force_suspend_resume_with_open_aggr, + "several force suspend/resume iterations with open aggregation frame", + ipa_mhi_test_in_loop_force_suspend_resume_aggr_open, + true, IPA_HW_v3_0, IPA_HW_v3_5_1), + IPA_UT_ADD_TEST(suspend_resume_with_host_wakeup, + "several suspend and host wakeup resume iterations", + ipa_mhi_test_in_loop_suspend_host_wakeup, + true, IPA_HW_v3_0, IPA_HW_MAX), + IPA_UT_ADD_TEST(reject_suspend_channel_full, + "several rejected suspend iterations due to full channel", + ipa_mhi_test_in_loop_reject_suspend_full_channel, + true, IPA_HW_v3_0, IPA_HW_MAX), + IPA_UT_ADD_TEST(reject_force_suspend_channel_full, + "several rejected force suspend iterations due to full channel", + ipa_mhi_test_in_loop_reject_force_suspend_full_channel, + true, IPA_HW_v3_0, IPA_HW_MAX), + IPA_UT_ADD_TEST(suspend_resume_manual_wp_update, + "several suspend/resume iterations with after simulating writing by wp manual update", + ipa_mhi_test_in_loop_suspend_resume_wp_update, + true, IPA_HW_v3_0, IPA_HW_MAX), + IPA_UT_ADD_TEST(channel_reset, + "several channel reset (disconnect/connect) iterations", + ipa_mhi_test_in_loop_channel_reset, + true, IPA_HW_v3_0, IPA_HW_MAX), + IPA_UT_ADD_TEST(channel_reset_aggr_open, + "several channel reset (disconnect/connect) iterations with open aggregation frame", + ipa_mhi_test_in_loop_channel_reset_aggr_open, + true, IPA_HW_v3_0, IPA_HW_MAX), + IPA_UT_ADD_TEST(channel_reset_ipa_holb, + "several channel reset (disconnect/connect) iterations with channel in HOLB state", + ipa_mhi_test_in_loop_channel_reset_ipa_holb, + true, IPA_HW_v3_0, IPA_HW_MAX), +} IPA_UT_DEFINE_SUITE_END(mhi); diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/test/ipa_test_ntn.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/test/ipa_test_ntn.c new file mode 100644 index 0000000000..88831bd2b2 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/test/ipa_test_ntn.c @@ -0,0 +1,1481 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ipa_ut_framework.h" +#include "ipa_eth.h" +#include "ipa.h" +#include +#include "ipa_i.h" + +#define NUM_TX_BUFS 10 +#define NUM_RX_BUFS 10 +#define NUM_RX_TR_ELE NUM_RX_BUFS +#define NUM_TX_TR_ELE NUM_TX_BUFS + +#define PACKET_HEADER_SIZE 220 +#define ETH_PACKET_SIZE 4 +#define PACKET_CONTENT 0x12345678 + +#define BUFFER_SIZE 2048 /* 2K */ + +#define DB_REGISTER_SIZE 4 +#define RX_TAIL_PTR_OFF 0 +#define TX_TAIL_PTR_OFF 8 + +#define IPA_TEST_NTN_NUM_PIPES 2 + +struct ipa_test_ntn_context { + struct completion init_completion_obj; + bool ready; + int wait_cnt; + struct ipa_eth_client client; + struct ipa_eth_client_pipe_info rx_pipe_info; + struct ipa_eth_client_pipe_info tx_pipe_info; + struct ipa_mem_buffer tx_transfer_ring_addr; + struct sg_table *tx_transfer_ring_sgt; + struct ipa_mem_buffer rx_transfer_ring_addr; + struct sg_table *rx_transfer_ring_sgt; + struct ipa_mem_buffer tx_buf; + struct sg_table *tx_buff_sgt; + struct ipa_eth_buff_smmu_map tx_data_buff_list[NUM_TX_BUFS]; + struct ipa_mem_buffer rx_buf; + struct sg_table *rx_buff_sgt; + struct ipa_mem_buffer bar_addr; + int rx_db_local; + int tx_db_local; + int rx_idx; + int tx_idx; + enum ipa_client_type cons_client_type; + enum ipa_client_type prod_client_type; + int eth_client_inst_id; +}; + +static struct ipa_test_ntn_context *test_ntn_ctx; + +/* TRE written by NTN (SW) */ +struct tx_transfer_ring_ele { + uint32_t res1; + uint32_t res2; + uint32_t res3; + uint32_t res4: 27; + uint32_t desc_status : 4; + uint32_t own : 1; +}__packed; + +/* event written by GSI */ +struct tx_event_ring_ele { + uint32_t buff_addr_LSB; + uint32_t buff_addr_MSB; + uint32_t buffer_length : 14; + uint32_t reserved1 : 17; + uint32_t ioc : 1; + uint32_t reserved2 : 28; + uint32_t ld : 1; + uint32_t fd : 1; + uint32_t reserved3 : 1; + uint32_t own : 1; + +}__packed; + +/* TRE written by NTN (SW) */ +struct rx_transfer_ring_ele +{ + uint32_t reserved1; + uint32_t reserved2; + uint32_t reserved3; + uint32_t packet_length : 14; + uint32_t reserverd4 : 14; + uint32_t ld : 1; + uint32_t fd : 1; + uint32_t reserved5 : 1; + uint32_t own : 1; +}__packed; + +/* event written by GSI */ +struct rx_event_ring_ele +{ + uint32_t buff_addr1; + uint32_t res_or_buff_addr1; + uint32_t buff_addr2; + uint32_t res_or_buff_addr2 : 30; + uint32_t ioc : 1; + uint32_t own : 1; +}__packed; + +static inline void ipa_test_ntn_set_client_params(enum ipa_client_type cons_type, + enum ipa_client_type prod_type, int inst_id) +{ + test_ntn_ctx->cons_client_type = cons_type; + test_ntn_ctx->prod_client_type = prod_type; + test_ntn_ctx->eth_client_inst_id = inst_id; +} + +static void ipa_test_ntn_free_dma_buff(struct ipa_mem_buffer *mem) +{ + struct ipa_smmu_cb_ctx *cb = ipa3_get_smmu_ctx(IPA_SMMU_CB_WLAN); + + if (!mem) { + IPA_UT_ERR("empty pointer\n"); + return; + } + + dma_free_coherent(cb->dev, mem->size, mem->base, + mem->phys_base); +} + +static int ipa_test_ntn_alloc_mmio(void) +{ + int ret = 0; + u32 size; + struct ipa_smmu_cb_ctx *cb = ipa3_get_smmu_ctx(IPA_SMMU_CB_WLAN); + + if (!test_ntn_ctx) { + IPA_UT_ERR("test_ntn_ctx is not initialized.\n"); + return -EFAULT; + } + + /* allocate tx transfer ring memory */ + size = NUM_TX_TR_ELE * sizeof(struct tx_transfer_ring_ele); + test_ntn_ctx->tx_transfer_ring_addr.size = size; + test_ntn_ctx->tx_transfer_ring_addr.base = + dma_alloc_coherent(cb->dev, size, + &test_ntn_ctx->tx_transfer_ring_addr.phys_base, + GFP_KERNEL); + if (!test_ntn_ctx->tx_transfer_ring_addr.phys_base) { + IPA_UT_ERR("fail to alloc memory.\n"); + return -ENOMEM; + } + + test_ntn_ctx->tx_transfer_ring_sgt = kzalloc( + sizeof(test_ntn_ctx->tx_transfer_ring_sgt), GFP_KERNEL); + if (!test_ntn_ctx->tx_transfer_ring_sgt) { + IPA_UT_ERR("fail to alloc memory.\n"); + ret = -ENOMEM; + goto fail_alloc_tx_sgt; + } + + ret = dma_get_sgtable(cb->dev, + test_ntn_ctx->tx_transfer_ring_sgt, + test_ntn_ctx->tx_transfer_ring_addr.base, + test_ntn_ctx->tx_transfer_ring_addr.phys_base, + size); + if (ret) { + IPA_UT_ERR("failed to get sgtable\n"); + ret = -ENOMEM; + goto fail_get_tx_sgtable; + } + + /* allocate rx transfer ring memory */ + size = NUM_RX_TR_ELE * sizeof(struct rx_transfer_ring_ele); + test_ntn_ctx->rx_transfer_ring_addr.size = size; + test_ntn_ctx->rx_transfer_ring_addr.base = + dma_alloc_coherent(cb->dev, size, + &test_ntn_ctx->rx_transfer_ring_addr.phys_base, + GFP_KERNEL); + if (!test_ntn_ctx->rx_transfer_ring_addr.phys_base) { + IPA_UT_ERR("fail to alloc memory.\n"); + ret = -ENOMEM; + goto fail_rx_transfer_ring; + } + + test_ntn_ctx->rx_transfer_ring_sgt = kzalloc( + sizeof(test_ntn_ctx->rx_transfer_ring_sgt), GFP_KERNEL); + if (!test_ntn_ctx->rx_transfer_ring_sgt) { + IPA_UT_ERR("fail to alloc memory.\n"); + ret = -ENOMEM; + goto fail_alloc_rx_sgt; + } + + ret = dma_get_sgtable(cb->dev, + test_ntn_ctx->rx_transfer_ring_sgt, + test_ntn_ctx->rx_transfer_ring_addr.base, + test_ntn_ctx->rx_transfer_ring_addr.phys_base, + size); + if (ret) { + IPA_UT_ERR("failed to get sgtable\n"); + ret = -ENOMEM; + goto fail_get_rx_sgtable; + } + + /* allocate tx buffers */ + size = BUFFER_SIZE * NUM_TX_BUFS; + test_ntn_ctx->tx_buf.size = size; + test_ntn_ctx->tx_buf.base = + dma_alloc_coherent(cb->dev, size, + &test_ntn_ctx->tx_buf.phys_base, + GFP_KERNEL); + if (!test_ntn_ctx->tx_buf.phys_base) { + IPA_UT_ERR("fail to alloc memory.\n"); + ret = -ENOMEM; + goto fail_tx_buf; + } + + test_ntn_ctx->tx_buff_sgt = kzalloc( + sizeof(test_ntn_ctx->tx_buff_sgt), GFP_KERNEL); + if (!test_ntn_ctx->tx_buff_sgt) { + IPA_UT_ERR("fail to alloc memory.\n"); + ret = -ENOMEM; + goto fail_alloc_tx_buff_sgt; + } + + ret = dma_get_sgtable(cb->dev, + test_ntn_ctx->tx_buff_sgt, + test_ntn_ctx->tx_buf.base, + test_ntn_ctx->tx_buf.phys_base, + size); + if (ret) { + IPA_UT_ERR("failed to get sgtable\n"); + ret = -ENOMEM; + goto fail_get_tx_buf_sgtable; + } + + /* allocate rx buffers */ + size = BUFFER_SIZE * NUM_RX_BUFS; + test_ntn_ctx->rx_buf.size = size; + test_ntn_ctx->rx_buf.base = + dma_alloc_coherent(cb->dev, size, + &test_ntn_ctx->rx_buf.phys_base, + GFP_KERNEL); + if (!test_ntn_ctx->rx_buf.phys_base) { + IPA_UT_ERR("fail to alloc memory.\n"); + ret = -ENOMEM; + goto fail_rx_bufs; + } + + test_ntn_ctx->rx_buff_sgt = kzalloc( + sizeof(test_ntn_ctx->rx_buff_sgt), GFP_KERNEL); + if (!test_ntn_ctx->rx_buff_sgt) { + IPA_UT_ERR("fail to alloc memory.\n"); + ret = -ENOMEM; + goto fail_alloc_rx_buff_sgt; + } + + ret = dma_get_sgtable(cb->dev, + test_ntn_ctx->rx_buff_sgt, + test_ntn_ctx->rx_buf.base, + test_ntn_ctx->rx_buf.phys_base, + size); + if (ret) { + IPA_UT_ERR("failed to get sgtable\n"); + ret = -ENOMEM; + goto fail_get_rx_buf_sgtable; + } + + /* + * allocate PCI bar with two tail pointers - + * addresses need to be 8B aligned + */ + test_ntn_ctx->bar_addr.size = 2 * DB_REGISTER_SIZE + 8; + test_ntn_ctx->bar_addr.base = + dma_alloc_coherent(ipa3_ctx->pdev, + test_ntn_ctx->bar_addr.size, + &test_ntn_ctx->bar_addr.phys_base, + GFP_KERNEL); + if (!test_ntn_ctx->bar_addr.base) { + IPA_UT_ERR("fail to alloc memory\n"); + ret = -ENOMEM; + goto fail_alloc_bar; + } + + return ret; + +fail_alloc_bar: + sg_free_table(test_ntn_ctx->rx_buff_sgt); +fail_get_rx_buf_sgtable: + kfree(test_ntn_ctx->rx_buff_sgt); + test_ntn_ctx->rx_buff_sgt = NULL; +fail_alloc_rx_buff_sgt: + ipa_test_ntn_free_dma_buff(&test_ntn_ctx->rx_buf); +fail_rx_bufs: + sg_free_table(test_ntn_ctx->tx_buff_sgt); +fail_get_tx_buf_sgtable: + kfree(test_ntn_ctx->tx_buff_sgt); + test_ntn_ctx->tx_buff_sgt = NULL; +fail_alloc_tx_buff_sgt: + ipa_test_ntn_free_dma_buff(&test_ntn_ctx->tx_buf); +fail_tx_buf: + sg_free_table(test_ntn_ctx->rx_transfer_ring_sgt); + +fail_get_rx_sgtable: + kfree(test_ntn_ctx->rx_transfer_ring_sgt); + test_ntn_ctx->rx_transfer_ring_sgt = NULL; +fail_alloc_rx_sgt: + ipa_test_ntn_free_dma_buff(&test_ntn_ctx->rx_transfer_ring_addr); +fail_rx_transfer_ring: + sg_free_table(test_ntn_ctx->tx_transfer_ring_sgt); +fail_get_tx_sgtable: + kfree(test_ntn_ctx->tx_transfer_ring_sgt); + test_ntn_ctx->tx_transfer_ring_sgt = NULL; +fail_alloc_tx_sgt: + ipa_test_ntn_free_dma_buff(&test_ntn_ctx->tx_transfer_ring_addr); + return ret; +} + +static int ipa_test_ntn_free_mmio(void) +{ + if (!test_ntn_ctx) { + IPA_UT_ERR("test_ntn_ctx is not initialized.\n"); + return -EFAULT; + } + + /* rx buff */ + sg_free_table(test_ntn_ctx->rx_buff_sgt); + kfree(test_ntn_ctx->rx_buff_sgt); + test_ntn_ctx->rx_buff_sgt = NULL; + ipa_test_ntn_free_dma_buff(&test_ntn_ctx->rx_buf); + + /* tx buff */ + sg_free_table(test_ntn_ctx->tx_buff_sgt); + kfree(test_ntn_ctx->tx_buff_sgt); + test_ntn_ctx->tx_buff_sgt = NULL; + ipa_test_ntn_free_dma_buff(&test_ntn_ctx->tx_buf); + + /* rx transfer ring */ + sg_free_table(test_ntn_ctx->rx_transfer_ring_sgt); + kfree(test_ntn_ctx->rx_transfer_ring_sgt); + test_ntn_ctx->rx_transfer_ring_sgt = NULL; + ipa_test_ntn_free_dma_buff(&test_ntn_ctx->rx_transfer_ring_addr); + + /* tx transfer ring */ + sg_free_table(test_ntn_ctx->tx_transfer_ring_sgt); + kfree(test_ntn_ctx->tx_transfer_ring_sgt); + test_ntn_ctx->tx_transfer_ring_sgt = NULL; + ipa_test_ntn_free_dma_buff(&test_ntn_ctx->tx_transfer_ring_addr); + + return 0; +} + +static void ipa_test_ntn_ready_cb(void *user_data) +{ + IPA_UT_DBG("ready CB entry\n"); + test_ntn_ctx->ready = true; + complete(&test_ntn_ctx->init_completion_obj); +} + +static struct ipa_eth_ready eth_ready = { + .notify = ipa_test_ntn_ready_cb, + .userdata = NULL +}; + +static int ipa_test_ntn_init_rings(void) +{ + struct tx_transfer_ring_ele *tx_ele; + struct rx_transfer_ring_ele *rx_ele; + int i; + + IPA_UT_DBG("filling the rings\n"); + + rx_ele = + (struct rx_transfer_ring_ele *) + (test_ntn_ctx->rx_transfer_ring_addr.base); + + tx_ele = + (struct tx_transfer_ring_ele *) + (test_ntn_ctx->tx_transfer_ring_addr.base); + + memset(rx_ele, 0, sizeof(*rx_ele) * NUM_RX_TR_ELE); + + for (i = 0; i < NUM_RX_TR_ELE; i++) { + rx_ele->fd = 1; + rx_ele->ld = 1; + rx_ele++; + } + + /* all fields should be zero */ + memset(tx_ele, 0, sizeof(*tx_ele) * NUM_TX_TR_ELE); + + return 0; +} + +static int ipa_test_ntn_suite_setup(void **priv) +{ + int ret = 0; + + IPA_UT_DBG("Start NTN Setup\n"); + + /* init ipa ntn ctx */ + if (!ipa3_ctx) { + IPA_UT_ERR("No IPA ctx\n"); + return -EINVAL; + } + + test_ntn_ctx = kzalloc(sizeof(struct ipa_test_ntn_context), + GFP_KERNEL); + if (!test_ntn_ctx) { + IPA_UT_ERR("failed to allocate ctx\n"); + return -ENOMEM; + } + + ipa_test_ntn_set_client_params(IPA_CLIENT_ETHERNET_CONS, IPA_CLIENT_ETHERNET_PROD, 0); + + init_completion(&test_ntn_ctx->init_completion_obj); + + /* + * registering ready callback mandatory for init. CB shall be launched + * anyway so connect the pipe from there. + * our driver expects struct memory to be static as it uses it when CB + * is launched. + */ + ret = ipa_eth_register_ready_cb(ð_ready); + if (ret) { + IPA_UT_ERR("failed to register CB\n"); + goto fail_alloc_mmio; + } + + IPA_UT_DBG("IPA %s ready\n", eth_ready.is_eth_ready ? "is" : "is not"); + + ret = ipa_test_ntn_alloc_mmio(); + if (ret) { + IPA_UT_ERR("failed to alloc mmio\n"); + goto fail_alloc_mmio; + } + + *priv = test_ntn_ctx; + return 0; + +fail_alloc_mmio: + kfree(test_ntn_ctx); + test_ntn_ctx = NULL; + return ret; +} + +static void ipa_ntn_test_print_stats(void) +{ + struct ipa_uc_dbg_ring_stats stats; + int ret; + int tx_ep, rx_ep; + struct ipa3_eth_error_stats tx_stats; + struct ipa3_eth_error_stats rx_stats; + + /* first get uC stats */ + ret = ipa3_get_ntn_gsi_stats(&stats); + if (ret) { + IPA_UT_ERR("failed to get stats\n"); + return; + } + IPA_UT_INFO("\nuC stats:\n"); + IPA_UT_INFO( + "NTN_tx_ringFull=%u\n" + "NTN_tx_ringEmpty=%u\n" + "NTN_tx_ringUsageHigh=%u\n" + "NTN_tx_ringUsageLow=%u\n" + "NTN_tx_RingUtilCount=%u\n", + stats.u.ring[1].ringFull, + stats.u.ring[1].ringEmpty, + stats.u.ring[1].ringUsageHigh, + stats.u.ring[1].ringUsageLow, + stats.u.ring[1].RingUtilCount); + + IPA_UT_INFO( + "NTN_rx_ringFull=%u\n" + "NTN_rx_ringEmpty=%u\n" + "NTN_rx_ringUsageHigh=%u\n" + "NTN_rx_ringUsageLow=%u\n" + "NTN_rx_RingUtilCount=%u\n", + stats.u.ring[0].ringFull, + stats.u.ring[0].ringEmpty, + stats.u.ring[0].ringUsageHigh, + stats.u.ring[0].ringUsageLow, + stats.u.ring[0].RingUtilCount); + + /* now get gsi stats */ + tx_ep = test_ntn_ctx->cons_client_type; + rx_ep = test_ntn_ctx->prod_client_type; + ipa3_eth_get_status(tx_ep, 6, &tx_stats); + ipa3_eth_get_status(rx_ep, 6, &rx_stats); + + IPA_UT_INFO("\nGSI stats:\n"); + IPA_UT_INFO( + "NTN_TX_RP=0x%x\n" + "NTN_TX_WP=0x%x\n" + "NTN_TX_err=%u\n", + tx_stats.rp, + tx_stats.wp, + tx_stats.err); + + IPA_UT_INFO( + "NTN_RX_RP=0x%x\n" + "NTN_RX_WP=0x%x\n" + "NTN_RX_err:%u\n", + rx_stats.rp, + rx_stats.wp, + rx_stats.err); +} + +static int ipa_test_ntn_suite_teardown(void *priv) +{ + if (!test_ntn_ctx) + return 0; + + ipa_test_ntn_free_mmio(); + kfree(test_ntn_ctx); + test_ntn_ctx = NULL; + + return 0; +} + +static int ipa_ntn_test_ready_cb(void *priv) +{ + int ret; + + test_ntn_ctx->wait_cnt++; + ret = wait_for_completion_timeout( + &test_ntn_ctx->init_completion_obj, + msecs_to_jiffies(1000)); + if (!ret) { + IPA_UT_ERR("ipa ready timeout, don't run\n"); + return -EFAULT; + } + + return 0; +} + +static void ipa_ntn_test_del_client_list(void) +{ + struct ipa_eth_client *eth_client = &test_ntn_ctx->client; + struct ipa_eth_client_pipe_info *pipe_info, *tmp; + + list_for_each_entry_safe(pipe_info, tmp, ð_client->pipe_list, link) + list_del(&pipe_info->link); +} + +static int ipa_ntn_test_setup_pipes(void) +{ + struct ipa_eth_client *client; + int ret, i; +#if IPA_ETH_API_VER >= 2 + struct net_device dummy_net_dev; + unsigned char dummy_dev_addr = 1; + + memset(dummy_net_dev.name, 0, sizeof(dummy_net_dev.name)); + dummy_net_dev.dev_addr = &dummy_dev_addr; + + test_ntn_ctx->client.client_type = IPA_ETH_CLIENT_NTN3; + test_ntn_ctx->client.inst_id = test_ntn_ctx->eth_client_inst_id; +#else + test_ntn_ctx->client.client_type = IPA_ETH_CLIENT_NTN; + test_ntn_ctx->client.inst_id = 0; +#endif + test_ntn_ctx->client.traffic_type = IPA_ETH_PIPE_BEST_EFFORT; +#if IPA_ETH_API_VER >= 2 + test_ntn_ctx->client.net_dev = &dummy_net_dev; +#endif + + /* RX pipe */ + /* ring */ + test_ntn_ctx->rx_pipe_info.dir = IPA_ETH_PIPE_DIR_RX; + test_ntn_ctx->rx_pipe_info.client_info = &test_ntn_ctx->client; + test_ntn_ctx->rx_pipe_info.info.is_transfer_ring_valid = true; + test_ntn_ctx->rx_pipe_info.info.transfer_ring_base = + test_ntn_ctx->rx_transfer_ring_addr.phys_base; + test_ntn_ctx->rx_pipe_info.info.transfer_ring_size = + test_ntn_ctx->rx_transfer_ring_addr.size; + test_ntn_ctx->rx_pipe_info.info.transfer_ring_sgt = + test_ntn_ctx->rx_transfer_ring_sgt; + + IPA_UT_DBG("rx TR phys 0x%X, cpu 0x%X, size %d, sgt 0x%X\n", + test_ntn_ctx->rx_transfer_ring_addr.phys_base, + test_ntn_ctx->rx_transfer_ring_addr.base, + test_ntn_ctx->rx_transfer_ring_addr.size, + test_ntn_ctx->rx_transfer_ring_sgt); + + /* buff */ + test_ntn_ctx->rx_pipe_info.info.is_buffer_pool_valid = true; + test_ntn_ctx->rx_pipe_info.info.fix_buffer_size = BUFFER_SIZE; + test_ntn_ctx->rx_pipe_info.info.buffer_pool_base_addr = + test_ntn_ctx->rx_buf.phys_base; + test_ntn_ctx->rx_pipe_info.info.buffer_pool_base_sgt = + test_ntn_ctx->rx_buff_sgt; + + IPA_UT_DBG("rx buff phys 0x%X, cpu 0x%X, size %d, fix size %d sgt 0x%X\n" + , test_ntn_ctx->rx_buf.phys_base, + test_ntn_ctx->rx_buf.base, + test_ntn_ctx->rx_buf.size, + test_ntn_ctx->rx_pipe_info.info.fix_buffer_size, + test_ntn_ctx->rx_buff_sgt); + + /* we don't plan to recieve skb on RX CB */ + test_ntn_ctx->rx_pipe_info.info.notify = NULL; + test_ntn_ctx->rx_pipe_info.info.priv = NULL; + + /* gsi info */ + test_ntn_ctx->rx_pipe_info.info.client_info.ntn.bar_addr = + test_ntn_ctx->bar_addr.phys_base; + + /* + * use the first 4 bytes as the RX tail_ptr and the next 4 for TX, + * make sure 8B alignment + */ + test_ntn_ctx->rx_pipe_info.info.client_info.ntn.tail_ptr_offs = + RX_TAIL_PTR_OFF; + + IPA_UT_DBG("tail registers bar: phys 0x%X virt 0x%X\n", + test_ntn_ctx->bar_addr.phys_base, test_ntn_ctx->bar_addr.base); + + /* TX pipe */ + /* ring */ + test_ntn_ctx->tx_pipe_info.dir = IPA_ETH_PIPE_DIR_TX; + test_ntn_ctx->tx_pipe_info.client_info = &test_ntn_ctx->client; + test_ntn_ctx->tx_pipe_info.info.is_transfer_ring_valid = true; + test_ntn_ctx->tx_pipe_info.info.transfer_ring_base = + test_ntn_ctx->tx_transfer_ring_addr.phys_base; + test_ntn_ctx->tx_pipe_info.info.transfer_ring_size = + test_ntn_ctx->tx_transfer_ring_addr.size; + test_ntn_ctx->tx_pipe_info.info.transfer_ring_sgt = + test_ntn_ctx->tx_transfer_ring_sgt; + + IPA_UT_DBG("tx TR phys 0x%X, cpu 0x%X, size %d, sgt 0x%X\n", + test_ntn_ctx->tx_transfer_ring_addr.phys_base, + test_ntn_ctx->tx_transfer_ring_addr.base, + test_ntn_ctx->tx_transfer_ring_addr.size, + test_ntn_ctx->tx_transfer_ring_sgt); + + /* buff - for tx let's use the buffer list method (test both methods) */ + test_ntn_ctx->tx_pipe_info.info.is_buffer_pool_valid = false; + test_ntn_ctx->tx_pipe_info.info.fix_buffer_size = BUFFER_SIZE; + test_ntn_ctx->tx_pipe_info.info.data_buff_list = + test_ntn_ctx->tx_data_buff_list; + for (i = 0; i < NUM_TX_BUFS; i++) { + test_ntn_ctx->tx_pipe_info.info.data_buff_list[i].iova = + (phys_addr_t)((u8 *)test_ntn_ctx->tx_buf.phys_base + + i * BUFFER_SIZE); + test_ntn_ctx->tx_pipe_info.info.data_buff_list[i].pa = + page_to_phys(vmalloc_to_page(test_ntn_ctx->tx_buf.base + + (BUFFER_SIZE * i))) | + ((phys_addr_t)(test_ntn_ctx->tx_buf.base + + (BUFFER_SIZE * i)) & ~PAGE_MASK); + + IPA_UT_DBG("tx_pipe_info.info.data_buff_list[%d].iova = 0x%lx", + i, + test_ntn_ctx->tx_pipe_info.info.data_buff_list[i].iova); + IPA_UT_DBG("tx_pipe_info.info.data_buff_list[%d].pa = 0x%lx", + i, + test_ntn_ctx->tx_pipe_info.info.data_buff_list[i].pa); + } + test_ntn_ctx->tx_pipe_info.info.data_buff_list_size = NUM_TX_BUFS; + + IPA_UT_DBG("tx buff phys 0x%X, cpu 0x%X, size %d, fix size %d sgt 0x%X\n" + , test_ntn_ctx->tx_buf.phys_base, + test_ntn_ctx->tx_buf.base, + test_ntn_ctx->tx_buf.size, + test_ntn_ctx->tx_pipe_info.info.fix_buffer_size, + test_ntn_ctx->tx_buff_sgt); + + test_ntn_ctx->tx_pipe_info.info.notify = NULL; + test_ntn_ctx->tx_pipe_info.info.priv = NULL; + + test_ntn_ctx->tx_pipe_info.info.client_info.ntn.bar_addr = + test_ntn_ctx->bar_addr.phys_base; + + /* + * use the first 4 bytes as the RX tail_ptr and the next 4 for TX, + * make sure 8B alignment + */ + test_ntn_ctx->tx_pipe_info.info.client_info.ntn.tail_ptr_offs = + TX_TAIL_PTR_OFF; + + /* add pipes to list */ + INIT_LIST_HEAD(&test_ntn_ctx->client.pipe_list); + list_add(&test_ntn_ctx->rx_pipe_info.link, + &test_ntn_ctx->client.pipe_list); + list_add(&test_ntn_ctx->tx_pipe_info.link, + &test_ntn_ctx->client.pipe_list); + + test_ntn_ctx->client.test = true; + client = &test_ntn_ctx->client; + ret = ipa_eth_client_conn_pipes(client); + if(ret) { + IPA_UT_ERR("ipa_eth_client_conn_pipes failed ret %d\n", ret); + goto conn_failed; + } + + return 0; + +conn_failed: + ipa_ntn_test_del_client_list(); + return ret; +} + +static int ipa_ntn_test_reg_intf(void) +{ + struct ipa_eth_intf_info intf; +#if IPA_ETH_API_VER >= 2 + struct net_device dummy_net_dev; + unsigned char dummy_dev_addr[ETH_ALEN] = { 0 }; +#else + char netdev_name[IPA_RESOURCE_NAME_MAX] = { 0 }; + u8 hdr_content = 1; +#endif + int ret = 0; + + memset(&intf, 0, sizeof(intf)); +#if IPA_ETH_API_VER >= 2 + memset(dummy_net_dev.name, 0, sizeof(dummy_net_dev.name)); + + intf.net_dev = &dummy_net_dev; + intf.net_dev->dev_addr = (unsigned char *)dummy_dev_addr; + intf.is_conn_evt = true; + + snprintf(intf.net_dev->name, sizeof(intf.net_dev->name), "ntn_test"); + IPA_UT_INFO("netdev name: %s strlen: %lu\n", intf.net_dev->name, strlen(intf.net_dev->name)); +#else + snprintf(netdev_name, sizeof(netdev_name), "ntn_test"); + intf.netdev_name = netdev_name; + IPA_UT_INFO("netdev name: %s strlen: %lu\n", intf.netdev_name, + strlen(intf.netdev_name)); + + intf.hdr[0].hdr = &hdr_content; + intf.hdr[0].hdr_len = 1; + intf.hdr[0].dst_mac_addr_offset = 0; + intf.hdr[0].hdr_type = IPA_HDR_L2_ETHERNET_II; + + intf.hdr[1].hdr = &hdr_content; + intf.hdr[1].hdr_len = 1; + intf.hdr[1].dst_mac_addr_offset = 0; + intf.hdr[1].hdr_type = IPA_HDR_L2_ETHERNET_II; + + intf.pipe_hdl_list = + kcalloc(IPA_TEST_NTN_NUM_PIPES, + sizeof(*intf.pipe_hdl_list), + GFP_KERNEL); + if (!intf.pipe_hdl_list) { + IPA_UT_ERR("Failed to alloc pipe handle list"); + return -ENOMEM; + } + + intf.pipe_hdl_list[0] = test_ntn_ctx->rx_pipe_info.pipe_hdl; + intf.pipe_hdl_list[1] = test_ntn_ctx->tx_pipe_info.pipe_hdl; + intf.pipe_hdl_list_size = IPA_TEST_NTN_NUM_PIPES; +#endif + + ret = ipa_eth_client_reg_intf(&intf); + if (ret) { + IPA_UT_ERR("Failed to register IPA interface"); + } + +#if IPA_ETH_API_VER >= 2 +#else + kfree(intf.pipe_hdl_list); +#endif + + return ret; +} + +static int ipa_ntn_test_unreg_intf(void) +{ + struct ipa_eth_intf_info intf; +#if IPA_ETH_API_VER >= 2 + struct net_device dummy_net_dev; +#else + char netdev_name[IPA_RESOURCE_NAME_MAX] = { 0 }; +#endif + + memset(&intf, 0, sizeof(intf)); +#if IPA_ETH_API_VER >= 2 + memset(dummy_net_dev.name, 0, sizeof(dummy_net_dev.name)); + + intf.net_dev = &dummy_net_dev; + + snprintf(intf.net_dev->name, sizeof(intf.net_dev->name), "ntn_test"); + IPA_UT_INFO("netdev name: %s strlen: %lu\n", intf.net_dev->name, strlen(intf.net_dev->name)); +#else + snprintf(netdev_name, sizeof(netdev_name), "ntn_test"); + intf.netdev_name = netdev_name; + IPA_UT_INFO("netdev name: %s strlen: %lu\n", intf.netdev_name, + strlen(intf.netdev_name)); +#endif + + return (ipa_eth_client_unreg_intf(&intf)); +} + +static void ipa_ntn_test_advance_db(u32 *db, int steps, + int num_words, int ring_size) +{ + *db = (*db + steps * num_words) % ring_size; +} + +static int ipa_ntn_send_one_packet(void) +{ + u32 *packet; + u32 *packet_recv; + + void __iomem *rx_db; + void __iomem *tx_db; + struct rx_event_ring_ele *rx_event; + u32 *tx_ring_tail; + u32 orig_tx_tail; + u32 *rx_ring_tail; + u32 orig_rx_tail; + int loop_cnt; + u64 evt_addr; + u64 pkt_addr; + struct rx_transfer_ring_ele *rx_ele; + + int ret = 0; + + rx_db = ioremap( + test_ntn_ctx->rx_pipe_info.info.db_pa, DB_REGISTER_SIZE); + if (!rx_db) { + IPA_UT_ERR("ioremap failed"); + return ret; + } + + tx_db = ioremap( + test_ntn_ctx->tx_pipe_info.info.db_pa, DB_REGISTER_SIZE); + if (!tx_db) { + IPA_UT_ERR("ioremap failed"); + return ret; + } + + /* initialize packet */ + packet = (u32 *)((u8 *)test_ntn_ctx->rx_buf.base + + (test_ntn_ctx->rx_idx * BUFFER_SIZE)); + pkt_addr = (u64)((u8 *)test_ntn_ctx->rx_buf.phys_base + + (test_ntn_ctx->rx_idx * BUFFER_SIZE)); + *packet = PACKET_CONTENT; + + /* update length in TRE */ + rx_ele = (struct rx_transfer_ring_ele *) + test_ntn_ctx->rx_transfer_ring_addr.base + test_ntn_ctx->rx_idx; + rx_ele->packet_length = ETH_PACKET_SIZE; + + /* point to base + 1 */ + ipa_ntn_test_advance_db(&test_ntn_ctx->rx_db_local, 1, + sizeof(struct rx_transfer_ring_ele), + test_ntn_ctx->rx_transfer_ring_addr.size); + + tx_ring_tail = (u32 *)((char *)test_ntn_ctx->bar_addr.base + + TX_TAIL_PTR_OFF); + orig_tx_tail = *tx_ring_tail; + rx_ring_tail = (u32 *)((char *)test_ntn_ctx->bar_addr.base + + RX_TAIL_PTR_OFF); + orig_rx_tail = *rx_ring_tail; + + IPA_UT_DBG("orig tx tail 0x%X\n", orig_tx_tail); + IPA_UT_DBG("orig rx tail 0x%X\n", orig_rx_tail); + + /* ring db and send packet */ + iowrite32(test_ntn_ctx->rx_db_local + + lower_32_bits(test_ntn_ctx->rx_transfer_ring_addr.phys_base), + rx_db); + IPA_UT_DBG("rx_db_local increased to 0x%X\n", + test_ntn_ctx->rx_db_local + + lower_32_bits(test_ntn_ctx->rx_transfer_ring_addr.phys_base)); + + loop_cnt = 0; + while ((orig_rx_tail == *rx_ring_tail) || + (orig_tx_tail == *tx_ring_tail)) { + loop_cnt++; + if (loop_cnt == 1000) { + IPA_UT_ERR("transfer timeout!\n"); + IPA_UT_ERR("orig_tx_tail: %X tx_ring_db: %X\n", + orig_tx_tail, *tx_ring_tail); + IPA_UT_ERR("orig_rx_tail: %X rx_ring_db: %X\n", + orig_rx_tail, *rx_ring_tail); + IPA_UT_ERR("rx db local: %u\n", + test_ntn_ctx->rx_db_local + + lower_32_bits( + test_ntn_ctx->rx_transfer_ring_addr.phys_base)); + BUG(); + ret = -EFAULT; + goto err; + } + usleep_range(1000, 1001); + } + IPA_UT_DBG("loop_cnt %d\n", loop_cnt); + IPA_UT_DBG("rx ring tail 0x%X\n", *rx_ring_tail); + IPA_UT_DBG("tx ring tail 0x%X\n", *tx_ring_tail); + + /* verify RX event */ + rx_event = (struct rx_event_ring_ele *)rx_ele; + + IPA_UT_DBG("address written by GSI is 0x[%X][%X]\n", + rx_event->buff_addr2, rx_event->buff_addr1); + IPA_UT_DBG("own bit is now %u", rx_event->own); + + if (!rx_event->own) { + IPA_UT_ERR("own bit not modified by gsi - failed\n"); + ret = -EFAULT; + } + + evt_addr = ((u64)rx_event->buff_addr2 << 32) | + (u64)(rx_event->buff_addr1); + IPA_UT_DBG("RX: addr from event 0x%llx, address from buff %llx\n", + evt_addr, pkt_addr); + if (evt_addr != pkt_addr) { + IPA_UT_ERR("addresses are different - fail\n"); + ret = -EFAULT; + } + + /* read received packet */ + packet_recv = (u32 *)((u8 *)test_ntn_ctx->tx_buf.base + + (test_ntn_ctx->tx_idx * BUFFER_SIZE)); + IPA_UT_DBG("received packet 0x%X\n", *packet_recv); + + if (*packet_recv != *packet) { + IPA_UT_ERR("packet content mismatch\n"); + ret = -EFAULT; + } + + /* recycle buffer */ + *packet_recv = 0; + + /* recycle TRE */ + /* TX */ + memset((struct tx_transfer_ring_ele *) + test_ntn_ctx->tx_transfer_ring_addr.base + test_ntn_ctx->tx_idx, + 0, sizeof(struct rx_transfer_ring_ele)); + + /* RX */ + memset(rx_ele, 0, sizeof(struct rx_transfer_ring_ele)); + rx_ele->fd = 1; + rx_ele->ld = 1; + + test_ntn_ctx->rx_idx = (test_ntn_ctx->rx_idx + 1) % NUM_RX_TR_ELE; + test_ntn_ctx->tx_idx = (test_ntn_ctx->tx_idx + 1) % NUM_TX_TR_ELE; + IPA_UT_DBG("now indexes are: rx %d, tx %d\n", test_ntn_ctx->rx_idx, + test_ntn_ctx->tx_idx); + + ipa_ntn_test_advance_db(&test_ntn_ctx->tx_db_local, 1, + sizeof(struct tx_transfer_ring_ele), + test_ntn_ctx->tx_transfer_ring_addr.size); + iowrite32(test_ntn_ctx->tx_db_local + + lower_32_bits(test_ntn_ctx->tx_transfer_ring_addr.phys_base), + tx_db); + IPA_UT_DBG("tx_db_local advanced to 0x%X\n", + test_ntn_ctx->tx_db_local + + lower_32_bits(test_ntn_ctx->tx_transfer_ring_addr.phys_base)); +err: + iounmap(rx_db); + iounmap(tx_db); + return ret; +} + +static int ipa_ntn_teardown_pipes(void) +{ + int ret = 0; + + if (ipa_eth_client_disconn_pipes(&test_ntn_ctx->client)) { + IPA_UT_ERR("fail to teardown ntn pipes.\n"); + ret = -EFAULT; + } + + test_ntn_ctx->rx_idx = 0; + test_ntn_ctx->tx_idx = 0; + test_ntn_ctx->tx_db_local = 0; + test_ntn_ctx->rx_db_local = 0; + return ret; +} +static int ipa_ntn_test_prepare_test(void) +{ + struct ipa_ep_cfg ep_cfg = { { 0 } }; + int offset = 0; + int ret = 0; + + if (ipa_test_ntn_init_rings()) { + IPA_UT_ERR("fail to fill rings.\n"); + return -EFAULT; + } + + if (ipa_ntn_test_setup_pipes()) { + IPA_UT_ERR("fail to setup ntn pipes.\n"); + return -EFAULT; + } + + offset = sizeof(struct rx_transfer_ring_ele) * (NUM_RX_TR_ELE - 1); + IPA_UT_DBG("ofset 0x%X\n", offset); + + IPA_UT_DBG("writing to RX tail ptr in 0x%X le value of 0x%X", + (u32 *)((char *)test_ntn_ctx->bar_addr.base + RX_TAIL_PTR_OFF), + lower_32_bits(test_ntn_ctx->rx_transfer_ring_addr.phys_base + + offset)); + + *((u32 *)((char *)test_ntn_ctx->bar_addr.base + RX_TAIL_PTR_OFF)) = + cpu_to_le32(lower_32_bits( + test_ntn_ctx->rx_transfer_ring_addr.phys_base + + offset)); + + /* initialize tx tail to the beginning of the ring */ + IPA_UT_DBG("writing to TX tail ptr in 0x%X le value of 0x%X", + (u32 *)((char *)test_ntn_ctx->bar_addr.base + TX_TAIL_PTR_OFF), + lower_32_bits(test_ntn_ctx->tx_transfer_ring_addr.phys_base)); + + *((u32 *)((char *)test_ntn_ctx->bar_addr.base + TX_TAIL_PTR_OFF)) = + cpu_to_le32(lower_32_bits( + test_ntn_ctx->tx_transfer_ring_addr.phys_base)); + + if (ipa_ntn_test_reg_intf()) { + IPA_UT_ERR("fail to reg ntn interface.\n"); + ret = -EFAULT; + goto teardown_pipes; + } + + /* configure NTN RX EP in DMA mode */ + ep_cfg.mode.mode = IPA_DMA; + ep_cfg.mode.dst = test_ntn_ctx->cons_client_type; + + ep_cfg.seq.set_dynamic = true; + + if (ipa3_cfg_ep(ipa_get_ep_mapping(test_ntn_ctx->prod_client_type), + &ep_cfg)) { + IPA_UT_ERR("fail to configure DMA mode.\n"); + ret = -EFAULT; + goto unreg; + } + + return 0; + +unreg: + if (ipa_ntn_test_unreg_intf()) { + IPA_UT_ERR("fail to unregister interface.\n"); + ret = -EFAULT; + goto teardown_pipes; + } +teardown_pipes: + if (ipa_ntn_teardown_pipes()) + ret = -EFAULT; + return ret; +} +static int ipa_ntn_test_single_transfer(void *priv) +{ + int ret = 0; + + if(!test_ntn_ctx->ready) { + if (test_ntn_ctx->wait_cnt) { + IPA_UT_ERR("ipa ready timeout, don't run\n"); + return -EFAULT; + } + /* ready cb test hasn't ran yet and we need to wait */ + if (ipa_ntn_test_ready_cb(NULL)) { + IPA_UT_ERR("ipa ready timeout, don't run\n"); + return -EFAULT; + } + } + + if (ipa_ntn_test_prepare_test()) { + IPA_UT_ERR("failed to prepare test.\n"); + ret = -EFAULT; + goto fail; + } + + if (ipa_ntn_send_one_packet()) { + IPA_UT_ERR("fail to transfer packet.\n"); + ret = -EFAULT; + goto fail; + } + + IPA_UT_INFO("one packet sent and received succesfully\n"); + + ipa_ntn_test_print_stats(); + +fail: + if (ipa_ntn_test_unreg_intf()) { + IPA_UT_ERR("fail to unregister interface.\n"); + ret = -EFAULT; + } + + if (ipa_ntn_teardown_pipes()) + ret = -EFAULT; + return ret; +} + +static int ipa_ntn_send_multi_packet_one_by_one(int num) +{ + int i; + + IPA_UT_INFO("about to send %d packets\n", num); + for (i = 0; i < num; i++) { + if (ipa_ntn_send_one_packet()) { + IPA_UT_ERR("failed on %d packet\n", i); + return -EFAULT; + } + IPA_UT_DBG("packet %d sent and recieved succesfully\n\n", i); + } + IPA_UT_INFO("all packets were succesfull\n\n"); + return 0; +} + +static int ipa_ntn_test_multi_transfer(void *priv) +{ + int ret = 0; + + if (!test_ntn_ctx->ready) { + if (test_ntn_ctx->wait_cnt) { + IPA_UT_ERR("ipa ready timeout, don't run\n"); + return -EFAULT; + } + /* ready cb test hasn't ran yet and we need to wait */ + if (ipa_ntn_test_ready_cb(NULL)) { + IPA_UT_ERR("ipa ready timeout, don't run\n"); + return -EFAULT; + } + } + + if (ipa_ntn_test_prepare_test()) { + IPA_UT_ERR("failed to prepare test.\n"); + ret = -EFAULT; + goto fail; + } + + if (ipa_ntn_send_multi_packet_one_by_one(NUM_RX_BUFS/2)) { + IPA_UT_ERR("failed to send packets.\n"); + ret = -EFAULT; + goto fail; + } + + IPA_UT_INFO("%d packets sent and received succesfully\n", + NUM_RX_BUFS / 2); + + ipa_ntn_test_print_stats(); + +fail: + if (ipa_ntn_test_unreg_intf()) { + IPA_UT_ERR("fail to unregister interface.\n"); + ret = -EFAULT; + } + + if (ipa_ntn_teardown_pipes()) + ret = -EFAULT; + return ret; +} + +static int ipa_ntn_test_multi_transfer_wrap_around(void *priv) +{ + int ret = 0; + + if (!test_ntn_ctx->ready) { + if (test_ntn_ctx->wait_cnt) { + IPA_UT_ERR("ipa ready timeout, don't run\n"); + return -EFAULT; + } + /* ready cb test hasn't ran yet and we need to wait */ + if (ipa_ntn_test_ready_cb(NULL)) { + IPA_UT_ERR("ipa ready timeout, don't run\n"); + return -EFAULT; + } + } + + if (ipa_ntn_test_prepare_test()) { + IPA_UT_ERR("failed to prepare test.\n"); + ret = -EFAULT; + goto fail; + } + + if (ipa_ntn_send_multi_packet_one_by_one(NUM_RX_BUFS * 2)) { + IPA_UT_ERR("failed to send packets.\n"); + ret = -EFAULT; + goto fail; + } + + IPA_UT_INFO("%d packets sent and received succesfully\n", + NUM_RX_BUFS * 2); + + ipa_ntn_test_print_stats(); + +fail: + if (ipa_ntn_test_unreg_intf()) { + IPA_UT_ERR("fail to unregister interface.\n"); + ret = -EFAULT; + } + + if (ipa_ntn_teardown_pipes()) + ret = -EFAULT; + return ret; +} + +static int ipa_ntn_send_packet_burst(void) +{ + u32 *packet[NUM_RX_TR_ELE]; + u32 *packet_recv; + + void __iomem *rx_db; + void __iomem *tx_db; + struct rx_event_ring_ele *rx_event; + u32 *tx_ring_tail; + u32 orig_tx_tail; + u32 *rx_ring_tail; + u32 orig_rx_tail; + int loop_cnt; + u64 evt_addr; + u64 pkt_addr[NUM_RX_TR_ELE]; + struct rx_transfer_ring_ele *rx_ele; + struct ipa_ep_cfg_ctrl ep_cfg_ctrl = { 0 }; + + int i, initial_val, ret = 0; + + rx_db = ioremap( + test_ntn_ctx->rx_pipe_info.info.db_pa, DB_REGISTER_SIZE); + if (!rx_db) { + IPA_UT_ERR("ioremap failed"); + return ret; + } + + tx_db = ioremap( + test_ntn_ctx->tx_pipe_info.info.db_pa, DB_REGISTER_SIZE); + if (!tx_db) { + IPA_UT_ERR("ioremap failed"); + return ret; + } + + /* initialize packets */ + initial_val = PACKET_CONTENT; + for (i = 0; i < NUM_RX_TR_ELE - 1; i++, initial_val++) { + packet[i] = (u32 *)((u8 *)test_ntn_ctx->rx_buf.base + + (i * BUFFER_SIZE)); + pkt_addr[i] = (u64)((u8 *)test_ntn_ctx->rx_buf.phys_base + + (i * BUFFER_SIZE)); + IPA_UT_DBG("loading packet %d with val 0x%X\n", i, initial_val); + *(packet[i]) = initial_val; + + /* update length in TRE */ + rx_ele = (struct rx_transfer_ring_ele *) + test_ntn_ctx->rx_transfer_ring_addr.base + i; + rx_ele->packet_length = ETH_PACKET_SIZE; + } + + /* + * set ep delay of 20ms to make sure uC is able to poll and see the + * ring full stats for RX + */ + ep_cfg_ctrl.ipa_ep_delay = true; + ret = ipa_cfg_ep_ctrl( + ipa_get_ep_mapping(test_ntn_ctx->prod_client_type), + &ep_cfg_ctrl); + if (ret) { + IPA_UT_ERR("couldn't set delay to ETHERNET_PROD\n"); + goto err; + } + IPA_UT_DBG("delay set succesfully to ETHERNET_PROD\n"); + + /* point db to end of ring */ + ipa_ntn_test_advance_db(&test_ntn_ctx->rx_db_local, NUM_RX_TR_ELE - 1, + sizeof(struct rx_transfer_ring_ele), + test_ntn_ctx->rx_transfer_ring_addr.size); + + tx_ring_tail = (u32 *)((char *)test_ntn_ctx->bar_addr.base + + TX_TAIL_PTR_OFF); + orig_tx_tail = *tx_ring_tail; + rx_ring_tail = (u32 *)((char *)test_ntn_ctx->bar_addr.base + + RX_TAIL_PTR_OFF); + orig_rx_tail = *rx_ring_tail; + + IPA_UT_DBG("orig tx tail 0x%X\n", orig_tx_tail); + IPA_UT_DBG("orig rx tail 0x%X\n", orig_rx_tail); + + /* ring db and send packet */ + iowrite32(test_ntn_ctx->rx_db_local + + lower_32_bits(test_ntn_ctx->rx_transfer_ring_addr.phys_base), + rx_db); + IPA_UT_DBG("rx_db_local increased to 0x%X\n", + test_ntn_ctx->rx_db_local + + lower_32_bits(test_ntn_ctx->rx_transfer_ring_addr.phys_base)); + + IPA_UT_DBG("sleep before removing delay\n"); + msleep(20); + ep_cfg_ctrl.ipa_ep_delay = false; + ret = ipa_cfg_ep_ctrl( + ipa_get_ep_mapping(test_ntn_ctx->prod_client_type), + &ep_cfg_ctrl); + if (ret) { + IPA_UT_ERR("couldn't unset delay to ETHERNET_PROD\n"); + goto err; + } + IPA_UT_DBG("delay unset succesfully from ETHERNET_PROD\n"); + + loop_cnt = 0; + while (((*rx_ring_tail - orig_rx_tail) < NUM_RX_TR_ELE - 1) || + ((*tx_ring_tail - orig_tx_tail) < NUM_TX_TR_ELE - 1)) { + loop_cnt++; + + if (loop_cnt == 1000) { + IPA_UT_ERR("transfer timeout!\n"); + IPA_UT_ERR("orig_tx_tail: %X tx_ring_db: %X\n", + orig_tx_tail, *tx_ring_tail); + IPA_UT_ERR("orig_rx_tail: %X rx_ring_db: %X\n", + orig_rx_tail, *rx_ring_tail); + IPA_UT_ERR("rx db local: 0x%X\n", + test_ntn_ctx->rx_db_local + + lower_32_bits( + test_ntn_ctx->rx_transfer_ring_addr.phys_base)); + BUG(); + ret = -EFAULT; + goto err; + } + usleep_range(1000, 1001); + } + + IPA_UT_DBG("loop_cnt %d\n", loop_cnt); + IPA_UT_DBG("rx ring tail 0x%X\n", *rx_ring_tail); + IPA_UT_DBG("tx ring tail 0x%X\n", *tx_ring_tail); + + for (i = 0; i < NUM_RX_TR_ELE - 1; i++, initial_val++) { + /* verify RX event */ + rx_ele = (struct rx_transfer_ring_ele *) + test_ntn_ctx->rx_transfer_ring_addr.base + i; + rx_event = (struct rx_event_ring_ele *)rx_ele; + + IPA_UT_DBG("%d: address written by GSI is 0x[%X][%X]\n", + i, rx_event->buff_addr2, rx_event->buff_addr1); + IPA_UT_DBG("own bit is now %u", rx_event->own); + + if (!rx_event->own) { + IPA_UT_ERR("own bit not modified by gsi - failed\n"); + ret = -EFAULT; + } + + evt_addr = ((u64)rx_event->buff_addr2 << 32) | + (u64)(rx_event->buff_addr1); + IPA_UT_DBG( + "RX: addr from event 0x%llx, address from buff %llx\n", + evt_addr, pkt_addr[i]); + if (evt_addr != pkt_addr[i]) { + IPA_UT_ERR("addresses are different - fail\n"); + ret = -EFAULT; + } + + /* read received packet */ + packet_recv = (u32 *)((u8 *)test_ntn_ctx->tx_buf.base + + (i * BUFFER_SIZE)); + IPA_UT_DBG("received packet 0x%X\n", *packet_recv); + + if (*packet_recv != *(packet[i])) { + IPA_UT_ERR("packet content mismatch 0x%X != 0x%X\n", + *packet_recv, *(packet[i])); + ret = -EFAULT; + } + IPA_UT_DBG("packet %d content match!\n", i); + + /* recycle buffer */ + *packet_recv = 0; + + /* recycle TRE */ + /* TX */ + memset((struct tx_transfer_ring_ele *) + test_ntn_ctx->tx_transfer_ring_addr.base + i, + 0, sizeof(struct rx_transfer_ring_ele)); + + /* RX */ + memset(rx_ele, 0, sizeof(struct rx_transfer_ring_ele)); + rx_ele->fd = 1; + rx_ele->ld = 1; + } + + ipa_ntn_test_advance_db(&test_ntn_ctx->tx_db_local, NUM_TX_TR_ELE - 1, + sizeof(struct tx_transfer_ring_ele), + test_ntn_ctx->tx_transfer_ring_addr.size); + IPA_UT_DBG("advance tx_db_local to 0x%X\n", + test_ntn_ctx->tx_db_local + + lower_32_bits(test_ntn_ctx->tx_transfer_ring_addr.phys_base)); + iowrite32(test_ntn_ctx->tx_db_local + + lower_32_bits(test_ntn_ctx->tx_transfer_ring_addr.phys_base), + tx_db); + + test_ntn_ctx->rx_idx = NUM_RX_TR_ELE - 1; + test_ntn_ctx->tx_idx = NUM_TX_TR_ELE - 1; +err: + iounmap(rx_db); + iounmap(tx_db); + return ret; +} + +static int ipa_ntn_test_multi_transfer_burst(void *priv) +{ + int ret = 0; + + if (!test_ntn_ctx->ready) { + if (test_ntn_ctx->wait_cnt) { + IPA_UT_ERR("ipa ready timeout, don't run\n"); + return -EFAULT; + } + /* ready cb test hasn't ran yet and we need to wait */ + if (ipa_ntn_test_ready_cb(NULL)) { + IPA_UT_ERR("ipa ready timeout, don't run\n"); + return -EFAULT; + } + } + + if (ipa_ntn_test_prepare_test()) { + IPA_UT_ERR("failed to prepare test.\n"); + ret = -EFAULT; + goto fail; + } + + if (ipa_ntn_send_packet_burst()) { + IPA_UT_ERR("failed to send packets.\n"); + ret = -EFAULT; + goto fail; + } + + IPA_UT_INFO("sent %d packets in a burst succesfully!\n", + NUM_TX_TR_ELE - 1); + + if (ipa_ntn_send_one_packet()) { + IPA_UT_ERR("failed to send last packet.\n"); + ret = -EFAULT; + goto fail; + } + IPA_UT_INFO("sent the last packet succesfully!\n"); + + ipa_ntn_test_print_stats(); + +fail: + if (ipa_ntn_test_unreg_intf()) { + IPA_UT_ERR("fail to unregister interface.\n"); + ret = -EFAULT; + } + + if (ipa_ntn_teardown_pipes()) + ret = -EFAULT; + return ret; +} + +static int ipa_ntn_test_clients2_multi_transfer_burst(void *priv) +{ + int ret; + + ipa_test_ntn_set_client_params(IPA_CLIENT_ETHERNET2_CONS, IPA_CLIENT_ETHERNET2_PROD, 1); + ret = ipa_ntn_test_multi_transfer_burst(priv); + ipa_test_ntn_set_client_params(IPA_CLIENT_ETHERNET_CONS, IPA_CLIENT_ETHERNET_PROD, 0); + + return ret; +} + +/* Suite definition block */ +IPA_UT_DEFINE_SUITE_START(ntn, "NTN3 tests", + ipa_test_ntn_suite_setup, ipa_test_ntn_suite_teardown) +{ + IPA_UT_ADD_TEST(ready_cb, + "ready callback test", + ipa_ntn_test_ready_cb, + true, IPA_HW_v5_0, IPA_HW_MAX), + + IPA_UT_ADD_TEST(single_transfer, + "single data transfer", + ipa_ntn_test_single_transfer, + true, IPA_HW_v5_0, IPA_HW_MAX), + + IPA_UT_ADD_TEST(multi_transfer, + "multi data transfer without wrap around", + ipa_ntn_test_multi_transfer, + true, IPA_HW_v5_0, IPA_HW_MAX), + + IPA_UT_ADD_TEST(multi_transfer_w_wrap, + "multi data transfer with wrap around", + ipa_ntn_test_multi_transfer_wrap_around, + true, IPA_HW_v5_0, IPA_HW_MAX), + + IPA_UT_ADD_TEST(multi_transfer_burst, + "send entire ring in one shot", + ipa_ntn_test_multi_transfer_burst, + true, IPA_HW_v5_0, IPA_HW_MAX), + + IPA_UT_ADD_TEST(clients2_multi_transfer_burst, + "Clients pair 2 send entire ring in one shot", + ipa_ntn_test_clients2_multi_transfer_burst, + true, IPA_HW_v5_0, IPA_HW_MAX), +} IPA_UT_DEFINE_SUITE_END(ntn); + + diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/test/ipa_test_wdi3.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/test/ipa_test_wdi3.c new file mode 100644 index 0000000000..40f8b698d9 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/test/ipa_test_wdi3.c @@ -0,0 +1,2450 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2018 - 2021, The Linux Foundation. All rights reserved. + */ + +#include "ipa_ut_framework.h" +#include "ipa_wdi3.h" +#include "ipa.h" +#include +#include "ipa_i.h" + +#define NUM_TX_BUFS 10 +#define NUM_RX_BUFS 10 +#define NUM_REDUNDANT_TX_ELE 1 +#define NUM_RX_TR_ELE NUM_RX_BUFS +#define NUM_RX_ER_ELE NUM_RX_BUFS +#define NUM_TX_TR_ELE (NUM_TX_BUFS + NUM_REDUNDANT_TX_ELE) +#define NUM_TX_ER_ELE (NUM_TX_BUFS + NUM_REDUNDANT_TX_ELE) + +#define RX_METADATA_SIZE 4 +#define PACKET_HEADER_SIZE 220 +#define ETH_PACKET_SIZE 4 +#define PACKET_CONTENT 0x12345678 + +#define PKT_SIZE 4096 + +#define DB_REGISTER_SIZE 4 + +#define NUM_MULTI_PKT 8 + +int multi_pkt_array[] = {0x12345678, 0x87654321, + 0x00112233, 0x01234567, 0x45454545, 0x80808080, + 0x13245678, 0x12345767, 0x43213456}; + +int rx_uc_db_local; +int tx_uc_db_local; +static int tx1_uc_db_local; +u8 tx_bf_idx; +u8 rx_bf_idx; +static u8 tx1_bf_idx; + +struct ipa_test_wdi3_context { + struct ipa_mem_buffer tx_transfer_ring_addr; + struct ipa_mem_buffer tx_event_ring_addr; + struct ipa_mem_buffer tx1_transfer_ring_addr; + struct ipa_mem_buffer tx1_event_ring_addr; + struct ipa_mem_buffer rx_transfer_ring_addr; + struct ipa_mem_buffer rx_event_ring_addr; + struct ipa_mem_buffer tx_bufs[NUM_TX_BUFS]; + struct ipa_mem_buffer tx1_bufs[NUM_TX_BUFS]; + struct ipa_mem_buffer rx_bufs[NUM_RX_BUFS]; + struct ipa_mem_buffer tx_transfer_ring_db; + struct ipa_mem_buffer tx_event_ring_db; + struct ipa_mem_buffer tx1_transfer_ring_db; + struct ipa_mem_buffer tx1_event_ring_db; + struct ipa_mem_buffer rx_transfer_ring_db; + struct ipa_mem_buffer rx_event_ring_db; + dma_addr_t tx_uc_db_pa; + dma_addr_t tx1_uc_db_pa; + dma_addr_t rx_uc_db_pa; +}; + +static struct ipa_test_wdi3_context *test_wdi3_ctx; + +struct buffer_addr_info { + u32 buffer_addr_low; + u32 buffer_addr_high : 8; + u32 return_buffer_manager : 3; + u32 sw_buffer_cookie : 21; +} __packed; + +struct tx_transfer_ring_ele { + struct buffer_addr_info buf_or_link_desc_addr_info; + u32 resv[6]; +} __packed; + +struct tx_event_ring_ele { + u32 reserved_5; + struct buffer_addr_info buf_or_link_desc_addr_info; + u32 buf_or_ext_desc_type : 1; + u32 epd : 1; + u32 encap_type : 2; + u32 encrypt_type : 4; + u32 src_buffer_swap : 1; + u32 link_meta_swap : 1; + u32 hlos_tid : 4; + u32 addrX_en : 1; + u32 addrY_en : 1; + u32 tcl_cmd_number : 16; + u32 data_length : 16; + u32 ipv4_checksum_en : 1; + u32 udp_over_ipv4_checksum_en : 1; + u32 udp_over_ipv6_checksum_en : 1; + u32 tcp_over_ipv4_checksum_en : 1; + u32 tcp_over_ipv6_checksum_en : 1; + u32 to_fw : 1; + u32 dscp_to_tid_priority_table_id : 1; + u32 packet_offset : 9; + u32 buffer_timestamp : 19; + u32 buffer_timestamp_valid : 1; + u32 reserved_4 : 12; + u32 reserved_6; + u32 reserved_7a : 20; + u32 ring_id : 8; + u32 looping_count : 4; +} __packed; + +struct rx_mpdu_desc_info { + u32 msdu_count : 8; + u32 mpdu_sequence_number : 12; + u32 fragment_flag : 1; + u32 mpdu_retry_bit : 1; + u32 ampdu_flag : 1; + u32 bar_frame : 1; + u32 pn_fields_contain_valid_info : 1; + u32 sa_is_valid : 1; + u32 sa_idx_timeout : 1; + u32 da_is_valid : 1; + u32 da_is_mcbc : 1; + u32 da_idx_timeout : 1; + u32 raw_mpdu : 1; + u32 reserved : 1; + u32 peer_meta_data; +} __packed; + +struct rx_msdu_desc_info { + u32 first_msdu_in_mpdu_flag : 1; + u32 last_msdu_in_mpdu_flag : 1; + u32 msdu_continuation : 1; + u32 msdu_length : 14; + u32 reo_destination_indication : 5; + u32 msdu_drop : 1; + u32 sa_is_valid : 1; + u32 sa_idx_timeout : 1; + u32 da_is_valid : 1; + u32 da_is_mcbc : 1; + u32 da_idx_timeout : 1; + u32 reserved_0a : 4; + u32 reserved_1a; +} __packed; + +struct rx_transfer_ring_ele { + struct buffer_addr_info buf_or_link_desc_addr_info; + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + u32 rx_reo_queue_desc_addr_31_0; + u32 rx_reo_queue_desc_addr_39_32 : 8; + u32 reo_dest_buffer_type : 1; + u32 reo_push_reason : 2; + u32 reo_error_code : 5; + u32 receive_queue_number : 16; + u32 soft_reorder_info_valid : 1; + u32 reorder_opcode : 4; + u32 reorder_slot_index : 8; + u32 reserved_8a : 19; + u32 reserved_9a; + u32 reserved_10a; + u32 reserved_11a; + u32 reserved_12a; + u32 reserved_13a; + u32 reserved_14a; + u32 reserved_15a : 20; + u32 ring_id : 8; + u32 looping_count : 4; +} __packed; + +struct rx_event_ring_ele { + struct buffer_addr_info buf_or_link_desc_addr_info; +} __packed; + +static void ipa_test_wdi3_free_dma_buff(struct ipa_mem_buffer *mem) +{ + if (!mem) { + IPA_UT_ERR("empty pointer\n"); + return; + } + + dma_free_coherent(ipa3_ctx->pdev, mem->size, mem->base, + mem->phys_base); +} + +static void ipa_test_wdi3_advance_uc_db(u32 *db, int steps, + int num_words, int ring_size) +{ + *db = (*db + steps * num_words) % (ring_size / 4); + IPA_UT_DBG("new db value: %u\n", *db); +} + +static int ipa_test_wdi3_alloc_mmio(void) +{ + int ret = 0, i, j; + int num_tx_alloc_bufs, num_rx_alloc_bufs; + int num_tx1_alloc_bufs; + u32 size; + + if (!test_wdi3_ctx) { + IPA_UT_ERR("test_wdi3_ctx is not initialized.\n"); + return -EFAULT; + } + + /* allocate tx transfer ring memory */ + size = NUM_TX_TR_ELE * sizeof(struct tx_transfer_ring_ele); + test_wdi3_ctx->tx_transfer_ring_addr.size = size; + test_wdi3_ctx->tx_transfer_ring_addr.base = + dma_alloc_coherent(ipa3_ctx->pdev, size, + &test_wdi3_ctx->tx_transfer_ring_addr.phys_base, + GFP_KERNEL); + if (!test_wdi3_ctx->tx_transfer_ring_addr.phys_base) { + IPA_UT_ERR("fail to alloc memory.\n"); + return -ENOMEM; + } + + /* allocate tx event ring memory */ + size = NUM_TX_ER_ELE * sizeof(struct tx_event_ring_ele); + test_wdi3_ctx->tx_event_ring_addr.size = size; + test_wdi3_ctx->tx_event_ring_addr.base = + dma_alloc_coherent(ipa3_ctx->pdev, size, + &test_wdi3_ctx->tx_event_ring_addr.phys_base, + GFP_KERNEL); + if (!test_wdi3_ctx->tx_event_ring_addr.phys_base) { + IPA_UT_ERR("fail to alloc memory.\n"); + ret = -ENOMEM; + goto fail_tx_event_ring; + } + + /* allocate tx1 transfer ring memory */ + size = NUM_TX_TR_ELE * sizeof(struct tx_transfer_ring_ele); + test_wdi3_ctx->tx1_transfer_ring_addr.size = size; + test_wdi3_ctx->tx1_transfer_ring_addr.base = + dma_alloc_coherent(ipa3_ctx->pdev, size, + &test_wdi3_ctx->tx1_transfer_ring_addr.phys_base, + GFP_KERNEL); + if (!test_wdi3_ctx->tx1_transfer_ring_addr.phys_base) { + IPA_UT_ERR("fail to alloc memory for tx1.\n"); + goto fail_tx1_transfer_ring; + } + + /* allocate tx1 event ring memory */ + size = NUM_TX_ER_ELE * sizeof(struct tx_event_ring_ele); + test_wdi3_ctx->tx1_event_ring_addr.size = size; + test_wdi3_ctx->tx1_event_ring_addr.base = + dma_alloc_coherent(ipa3_ctx->pdev, size, + &test_wdi3_ctx->tx1_event_ring_addr.phys_base, + GFP_KERNEL); + if (!test_wdi3_ctx->tx1_event_ring_addr.phys_base) { + IPA_UT_ERR("fail to alloc memory for tx1\n"); + ret = -ENOMEM; + goto fail_tx1_event_ring; + } + + /* allocate rx transfer ring memory */ + size = NUM_RX_TR_ELE * sizeof(struct rx_transfer_ring_ele); + test_wdi3_ctx->rx_transfer_ring_addr.size = size; + test_wdi3_ctx->rx_transfer_ring_addr.base = + dma_alloc_coherent(ipa3_ctx->pdev, size, + &test_wdi3_ctx->rx_transfer_ring_addr.phys_base, + GFP_KERNEL); + if (!test_wdi3_ctx->rx_transfer_ring_addr.phys_base) { + IPA_UT_ERR("fail to alloc memory.\n"); + ret = -ENOMEM; + goto fail_rx_transfer_ring; + } + + /* allocate rx event ring memory */ + size = NUM_RX_ER_ELE * sizeof(struct rx_event_ring_ele); + test_wdi3_ctx->rx_event_ring_addr.size = size; + test_wdi3_ctx->rx_event_ring_addr.base = + dma_alloc_coherent(ipa3_ctx->pdev, size, + &test_wdi3_ctx->rx_event_ring_addr.phys_base, + GFP_KERNEL); + if (!test_wdi3_ctx->rx_event_ring_addr.phys_base) { + IPA_UT_ERR("fail to alloc memory.\n"); + ret = -ENOMEM; + goto fail_rx_event_ring; + } + + /* allocate tx buffers */ + num_tx_alloc_bufs = NUM_TX_BUFS; + for (i = 0; i < NUM_TX_BUFS; i++) { + size = ETH_PACKET_SIZE; //2kB buffer size; + test_wdi3_ctx->tx_bufs[i].size = size; + test_wdi3_ctx->tx_bufs[i].base = + dma_alloc_coherent(ipa3_ctx->pdev, size, + &test_wdi3_ctx->tx_bufs[i].phys_base, + GFP_KERNEL); + if (!test_wdi3_ctx->tx_bufs[i].phys_base) { + IPA_UT_ERR("fail to alloc buffers for tx.\n"); + num_tx_alloc_bufs = i-1; + ret = -ENOMEM; + goto fail_tx_bufs; + } + } + + /* allocate tx1 buffers */ + num_tx1_alloc_bufs = NUM_TX_BUFS; + for (i = 0; i < NUM_TX_BUFS; i++) { + size = ETH_PACKET_SIZE; //2kB buffer size; + test_wdi3_ctx->tx1_bufs[i].size = size; + test_wdi3_ctx->tx1_bufs[i].base = + dma_alloc_coherent(ipa3_ctx->pdev, size, + &test_wdi3_ctx->tx1_bufs[i].phys_base, + GFP_KERNEL); + if (!test_wdi3_ctx->tx1_bufs[i].phys_base) { + IPA_UT_ERR("fail to alloc buffers for tx1\n"); + num_tx1_alloc_bufs = i-1; + ret = -ENOMEM; + goto fail_tx1_bufs; + } + } + + /* allocate rx buffers */ + num_rx_alloc_bufs = NUM_RX_BUFS; + for (i = 0; i < NUM_RX_BUFS; i++) { + size = ETH_PACKET_SIZE + PACKET_HEADER_SIZE; //2kB buffer size; + test_wdi3_ctx->rx_bufs[i].size = size; + test_wdi3_ctx->rx_bufs[i].base = + dma_alloc_coherent(ipa3_ctx->pdev, size, + &test_wdi3_ctx->rx_bufs[i].phys_base, + GFP_KERNEL); + if (!test_wdi3_ctx->rx_bufs[i].phys_base) { + IPA_UT_ERR("fail to alloc memory.\n"); + num_rx_alloc_bufs = i-1; + ret = -ENOMEM; + goto fail_rx_bufs; + } + } + + /* allocate tx transfer ring db */ + test_wdi3_ctx->tx_transfer_ring_db.size = DB_REGISTER_SIZE; + test_wdi3_ctx->tx_transfer_ring_db.base = + dma_alloc_coherent(ipa3_ctx->pdev, DB_REGISTER_SIZE, + &test_wdi3_ctx->tx_transfer_ring_db.phys_base, GFP_KERNEL); + if (!test_wdi3_ctx->tx_transfer_ring_db.base) { + IPA_UT_ERR("fail to alloc memory\n"); + ret = -ENOMEM; + goto fail_tx_transfer_ring_db; + } + + /* allocate tx event ring db */ + test_wdi3_ctx->tx_event_ring_db.size = DB_REGISTER_SIZE; + test_wdi3_ctx->tx_event_ring_db.base = + dma_alloc_coherent(ipa3_ctx->pdev, DB_REGISTER_SIZE, + &test_wdi3_ctx->tx_event_ring_db.phys_base, GFP_KERNEL); + if (!test_wdi3_ctx->tx_event_ring_db.base) { + IPA_UT_ERR("fail to alloc memory\n"); + ret = -ENOMEM; + goto fail_tx_event_ring_db; + } + + /* allocate tx1 transfer ring db */ + test_wdi3_ctx->tx1_transfer_ring_db.size = DB_REGISTER_SIZE; + test_wdi3_ctx->tx1_transfer_ring_db.base = + dma_alloc_coherent(ipa3_ctx->pdev, DB_REGISTER_SIZE, + &test_wdi3_ctx->tx1_transfer_ring_db.phys_base, GFP_KERNEL); + if (!test_wdi3_ctx->tx1_transfer_ring_db.base) { + IPA_UT_ERR("fail to alloc tx1 transfer ring\n"); + ret = -ENOMEM; + goto fail_tx1_transfer_ring_db; + } + + /* allocate tx1 event ring db */ + test_wdi3_ctx->tx1_event_ring_db.size = DB_REGISTER_SIZE; + test_wdi3_ctx->tx1_event_ring_db.base = + dma_alloc_coherent(ipa3_ctx->pdev, DB_REGISTER_SIZE, + &test_wdi3_ctx->tx1_event_ring_db.phys_base, GFP_KERNEL); + if (!test_wdi3_ctx->tx1_event_ring_db.base) { + IPA_UT_ERR("fail to alloc tx1 event ring\n"); + ret = -ENOMEM; + goto fail_tx1_event_ring_db; + } + + /* allocate rx transfer ring db */ + test_wdi3_ctx->rx_transfer_ring_db.size = DB_REGISTER_SIZE; + test_wdi3_ctx->rx_transfer_ring_db.base = + dma_alloc_coherent(ipa3_ctx->pdev, DB_REGISTER_SIZE, + &test_wdi3_ctx->rx_transfer_ring_db.phys_base, GFP_KERNEL); + if (!test_wdi3_ctx->rx_transfer_ring_db.base) { + IPA_UT_ERR("fail to alloc memory\n"); + ret = -ENOMEM; + goto fail_rx_transfer_ring_db; + } + + /* allocate rx event ring db */ + test_wdi3_ctx->rx_event_ring_db.size = DB_REGISTER_SIZE; + test_wdi3_ctx->rx_event_ring_db.base = + dma_alloc_coherent(ipa3_ctx->pdev, DB_REGISTER_SIZE, + &test_wdi3_ctx->rx_event_ring_db.phys_base, GFP_KERNEL); + if (!test_wdi3_ctx->rx_event_ring_db.base) { + IPA_UT_ERR("fail to alloc memory\n"); + ret = -ENOMEM; + goto fail_rx_event_ring_db; + } + + return ret; + +fail_rx_event_ring_db: + ipa_test_wdi3_free_dma_buff(&test_wdi3_ctx->rx_transfer_ring_db); + +fail_rx_transfer_ring_db: + ipa_test_wdi3_free_dma_buff(&test_wdi3_ctx->tx1_event_ring_db); + +fail_tx1_event_ring_db: + ipa_test_wdi3_free_dma_buff(&test_wdi3_ctx->tx_event_ring_db); + +fail_tx_event_ring_db: + ipa_test_wdi3_free_dma_buff(&test_wdi3_ctx->tx1_transfer_ring_db); + +fail_tx1_transfer_ring_db: + ipa_test_wdi3_free_dma_buff(&test_wdi3_ctx->tx_transfer_ring_db); +fail_tx_transfer_ring_db: +fail_rx_bufs: + for (j = 0; j <= num_rx_alloc_bufs; j++) + ipa_test_wdi3_free_dma_buff(&test_wdi3_ctx->rx_bufs[j]); + +fail_tx1_bufs: + for (j = 0; j <= num_tx1_alloc_bufs; j++) + ipa_test_wdi3_free_dma_buff(&test_wdi3_ctx->tx1_bufs[j]); + +fail_tx_bufs: + ipa_test_wdi3_free_dma_buff(&test_wdi3_ctx->rx_event_ring_addr); + + for (j = 0; j <= num_tx_alloc_bufs; j++) + ipa_test_wdi3_free_dma_buff(&test_wdi3_ctx->tx_bufs[j]); + +fail_rx_event_ring: + ipa_test_wdi3_free_dma_buff(&test_wdi3_ctx->rx_transfer_ring_addr); + +fail_rx_transfer_ring: + ipa_test_wdi3_free_dma_buff(&test_wdi3_ctx->tx1_event_ring_addr); + +fail_tx1_event_ring: + ipa_test_wdi3_free_dma_buff(&test_wdi3_ctx->tx1_transfer_ring_addr); + +fail_tx1_transfer_ring: + ipa_test_wdi3_free_dma_buff(&test_wdi3_ctx->tx_event_ring_addr); + +fail_tx_event_ring: + ipa_test_wdi3_free_dma_buff(&test_wdi3_ctx->tx_transfer_ring_addr); + return ret; +} + +static int ipa_test_wdi3_free_mmio(void) +{ + int i; + + if (!test_wdi3_ctx) { + IPA_UT_ERR("test_wdi3_ctx is not initialized.\n"); + return -EFAULT; + } + + ipa_test_wdi3_free_dma_buff(&test_wdi3_ctx->rx_event_ring_db); + + ipa_test_wdi3_free_dma_buff(&test_wdi3_ctx->rx_transfer_ring_db); + + ipa_test_wdi3_free_dma_buff(&test_wdi3_ctx->tx_event_ring_db); + + ipa_test_wdi3_free_dma_buff(&test_wdi3_ctx->tx_transfer_ring_db); + + ipa_test_wdi3_free_dma_buff(&test_wdi3_ctx->tx1_event_ring_db); + + ipa_test_wdi3_free_dma_buff(&test_wdi3_ctx->tx1_transfer_ring_db); + + ipa_test_wdi3_free_dma_buff(&test_wdi3_ctx->rx_event_ring_addr); + + ipa_test_wdi3_free_dma_buff(&test_wdi3_ctx->rx_transfer_ring_addr); + + ipa_test_wdi3_free_dma_buff(&test_wdi3_ctx->tx_event_ring_addr); + + ipa_test_wdi3_free_dma_buff(&test_wdi3_ctx->tx_transfer_ring_addr); + + ipa_test_wdi3_free_dma_buff(&test_wdi3_ctx->tx1_event_ring_addr); + + ipa_test_wdi3_free_dma_buff(&test_wdi3_ctx->tx1_transfer_ring_addr); + + for (i = 0; i < NUM_RX_BUFS; i++) + ipa_test_wdi3_free_dma_buff(&test_wdi3_ctx->rx_bufs[i]); + + for (i = 0; i < NUM_TX_BUFS; i++) + ipa_test_wdi3_free_dma_buff(&test_wdi3_ctx->tx_bufs[i]); + + for (i = 0; i < NUM_TX_BUFS; i++) + ipa_test_wdi3_free_dma_buff(&test_wdi3_ctx->tx1_bufs[i]); + + return 0; +} + +static int ipa_test_wdi3_suite_setup(void **priv) +{ + int ret = 0; + struct ipa_wdi_init_in_params in; + struct ipa_wdi_init_out_params out; + + IPA_UT_DBG("Start WDI3 Setup\n"); + + /* init ipa wdi ctx */ + in.wdi_notify = NULL; + in.notify = NULL; + in.priv = NULL; + in.wdi_version = IPA_WDI_3; + ipa_wdi_init(&in, &out); + + + if (!ipa3_ctx) { + IPA_UT_ERR("No IPA ctx\n"); + return -EINVAL; + } + + test_wdi3_ctx = kzalloc(sizeof(struct ipa_test_wdi3_context), + GFP_KERNEL); + if (!test_wdi3_ctx) { + IPA_UT_ERR("failed to allocate ctx\n"); + return -ENOMEM; + } + + ret = ipa_test_wdi3_alloc_mmio(); + if (ret) { + IPA_UT_ERR("failed to alloc mmio\n"); + goto fail_alloc_mmio; + } + + *priv = test_wdi3_ctx; + return 0; + +fail_alloc_mmio: + kfree(test_wdi3_ctx); + test_wdi3_ctx = NULL; + return ret; +} + +static int ipa_test_wdi3_suite_teardown(void *priv) +{ + if (!test_wdi3_ctx) + return 0; + + ipa_test_wdi3_free_mmio(); + kfree(test_wdi3_ctx); + test_wdi3_ctx = NULL; + + return 0; +} + +static int ipa_wdi3_setup_pipes(void) +{ + struct ipa_wdi_conn_in_params *in_param; + struct ipa_wdi_conn_out_params *out_param; + struct tx_transfer_ring_ele *tx_transfer, *tx_transfer_base; + struct rx_transfer_ring_ele *rx_transfer; + void __iomem *rx_uc_db; + void __iomem *tx_uc_db; + int i, index; + + if (!test_wdi3_ctx) { + IPA_UT_ERR("context is empty.\n"); + return -EFAULT; + } + + in_param = kzalloc(sizeof(struct ipa_wdi_conn_in_params), + GFP_KERNEL); + if (!in_param) { + IPA_UT_ERR("failed to allocate in_param\n"); + return -ENOMEM; + } + + out_param = kzalloc(sizeof(struct ipa_wdi_conn_out_params), + GFP_KERNEL); + if (!out_param) { + IPA_UT_ERR("failed to allocate out_param\n"); + kfree(in_param); + return -ENOMEM; + } + + memset(in_param, 0, sizeof(struct ipa_wdi_conn_in_params)); + memset(out_param, 0, sizeof(struct ipa_wdi_conn_out_params)); + + /* setup tx parameters */ + in_param->is_tx1_used = false; + in_param->is_smmu_enabled = false; + in_param->u_tx.tx.client = IPA_CLIENT_WLAN2_CONS; + in_param->u_tx.tx.transfer_ring_base_pa = + test_wdi3_ctx->tx_transfer_ring_addr.phys_base; + in_param->u_tx.tx.transfer_ring_size = + test_wdi3_ctx->tx_transfer_ring_addr.size; + in_param->u_tx.tx.transfer_ring_doorbell_pa = + test_wdi3_ctx->tx_transfer_ring_db.phys_base; + + in_param->notify = NULL; + in_param->u_tx.tx.event_ring_base_pa = + test_wdi3_ctx->tx_event_ring_addr.phys_base; + in_param->u_tx.tx.event_ring_size = + test_wdi3_ctx->tx_event_ring_addr.size; + in_param->u_tx.tx.event_ring_doorbell_pa = + test_wdi3_ctx->tx_event_ring_db.phys_base; + IPA_UT_DBG("tx_event_ring_db.phys_base %llu\n", + test_wdi3_ctx->tx_event_ring_db.phys_base); + IPA_UT_DBG("tx_event_ring_db.base %pK\n", + test_wdi3_ctx->tx_event_ring_db.base); + IPA_UT_DBG("tx_event_ring.phys_base %llu\n", + test_wdi3_ctx->tx_event_ring_addr.phys_base); + IPA_UT_DBG("tx_event_ring.base %pK\n", + test_wdi3_ctx->tx_event_ring_addr.base); + + in_param->u_tx.tx.num_pkt_buffers = NUM_TX_BUFS; + + /* setup rx parameters */ + in_param->u_rx.rx.client = IPA_CLIENT_WLAN2_PROD; + in_param->u_rx.rx.transfer_ring_base_pa = + test_wdi3_ctx->rx_transfer_ring_addr.phys_base; + in_param->u_rx.rx.transfer_ring_size = + test_wdi3_ctx->rx_transfer_ring_addr.size; + in_param->u_rx.rx.transfer_ring_doorbell_pa = + test_wdi3_ctx->rx_transfer_ring_db.phys_base; + in_param->u_rx.rx.pkt_offset = PACKET_HEADER_SIZE; + + + in_param->u_rx.rx.event_ring_base_pa = + test_wdi3_ctx->rx_event_ring_addr.phys_base; + in_param->u_rx.rx.event_ring_size = + test_wdi3_ctx->rx_event_ring_addr.size; + in_param->u_rx.rx.event_ring_doorbell_pa = + test_wdi3_ctx->rx_event_ring_db.phys_base; + + IPA_UT_DBG("rx_event_ring_db.phys_base %llu\n", + in_param->u_rx.rx.event_ring_doorbell_pa); + IPA_UT_DBG("rx_event_ring_db.base %pK\n", + test_wdi3_ctx->rx_event_ring_addr.base); + + in_param->u_rx.rx.num_pkt_buffers = NUM_RX_BUFS; + if (ipa_wdi_conn_pipes(in_param, out_param)) { + IPA_UT_ERR("fail to conn wdi3 pipes.\n"); + kfree(in_param); + kfree(out_param); + return -EFAULT; + } + if (ipa_wdi_enable_pipes()) { + IPA_UT_ERR("fail to enable wdi3 pipes.\n"); + ipa_wdi_disconn_pipes(); + kfree(in_param); + kfree(out_param); + return -EFAULT; + } + test_wdi3_ctx->tx_uc_db_pa = out_param->tx_uc_db_pa; + test_wdi3_ctx->rx_uc_db_pa = out_param->rx_uc_db_pa; + IPA_UT_DBG("tx_uc_db_pa %llu, rx_uc_db_pa %llu.\n", + test_wdi3_ctx->tx_uc_db_pa, test_wdi3_ctx->rx_uc_db_pa); + + rx_uc_db = ioremap(test_wdi3_ctx->rx_uc_db_pa, DB_REGISTER_SIZE); + tx_uc_db = ioremap(test_wdi3_ctx->tx_uc_db_pa, DB_REGISTER_SIZE); + + /* setup db registers */ + *(u32 *)test_wdi3_ctx->rx_transfer_ring_db.base = rx_uc_db_local; + *(u32 *)test_wdi3_ctx->rx_event_ring_db.base = 0; + + *(u32 *)test_wdi3_ctx->tx_transfer_ring_db.base = tx_uc_db_local; + *(u32 *)test_wdi3_ctx->tx_event_ring_db.base = 0; + + rx_transfer = (struct rx_transfer_ring_ele *) + test_wdi3_ctx->rx_transfer_ring_addr.base; + for (i = 0; i < NUM_TX_BUFS; i++) { + rx_transfer->buf_or_link_desc_addr_info.buffer_addr_low = + (u64)test_wdi3_ctx->rx_bufs[i].phys_base & 0xFFFFFFFF; + rx_transfer->buf_or_link_desc_addr_info.buffer_addr_high = + ((u64)test_wdi3_ctx->rx_bufs[i].phys_base >> 32) + & 0xFFFFFFFF; + rx_transfer++; + } + + tx_transfer_base = (struct tx_transfer_ring_ele *) + test_wdi3_ctx->tx_transfer_ring_addr.base; + index = tx_uc_db_local; + for (i = 0; i < NUM_TX_BUFS; i++) { + tx_transfer = tx_transfer_base + index; + tx_transfer->buf_or_link_desc_addr_info.buffer_addr_low = + (u64)test_wdi3_ctx->tx_bufs[i].phys_base & 0xFFFFFFFF; + tx_transfer->buf_or_link_desc_addr_info.buffer_addr_high = + ((u64)test_wdi3_ctx->tx_bufs[i].phys_base >> 32) + & 0xFFFFFFFF; + index = (index + 1) % NUM_TX_TR_ELE; + } + ipa_test_wdi3_advance_uc_db(&tx_uc_db_local, NUM_TX_BUFS, + sizeof(struct tx_transfer_ring_ele)/4, + test_wdi3_ctx->tx_transfer_ring_addr.size); + iowrite32(tx_uc_db_local, tx_uc_db); + kfree(in_param); + kfree(out_param); + return 0; +} + +static int ipa_wdi3_teardown_pipes(void) +{ + ipa_wdi_disable_pipes(); + ipa_wdi_disconn_pipes(); + rx_bf_idx = 0; + tx_bf_idx = 0; + tx1_bf_idx = 0; + rx_uc_db_local = 0; + tx_uc_db_local = 0; + tx1_uc_db_local = 0; + return 0; +} + +static int ipa_wdi3_setup_pipes_2g_5g(void) +{ + struct ipa_wdi_conn_in_params *in_param; + struct ipa_wdi_conn_out_params *out_param; + struct tx_transfer_ring_ele *tx_transfer, *tx_transfer_base; + struct tx_transfer_ring_ele *tx1_transfer, *tx1_transfer_base; + struct rx_transfer_ring_ele *rx_transfer; + void __iomem *rx_uc_db; + void __iomem *tx_uc_db; + void __iomem *tx1_uc_db; + int i, index; + + if (!test_wdi3_ctx) { + IPA_UT_ERR("context is empty.\n"); + return -EFAULT; + } + + in_param = kzalloc(sizeof(struct ipa_wdi_conn_in_params), + GFP_KERNEL); + if (!in_param) { + IPA_UT_ERR("failed to allocate in_param\n"); + return -ENOMEM; + } + + out_param = kzalloc(sizeof(struct ipa_wdi_conn_out_params), + GFP_KERNEL); + if (!out_param) { + IPA_UT_ERR("failed to allocate out_param\n"); + kfree(in_param); + return -ENOMEM; + } + + memset(in_param, 0, sizeof(struct ipa_wdi_conn_in_params)); + memset(out_param, 0, sizeof(struct ipa_wdi_conn_out_params)); + + /* setup tx parameters */ + in_param->is_smmu_enabled = false; + in_param->u_tx.tx.client = IPA_CLIENT_WLAN2_CONS; + in_param->u_tx.tx.transfer_ring_base_pa = + test_wdi3_ctx->tx_transfer_ring_addr.phys_base; + in_param->u_tx.tx.transfer_ring_size = + test_wdi3_ctx->tx_transfer_ring_addr.size; + in_param->u_tx.tx.transfer_ring_doorbell_pa = + test_wdi3_ctx->tx_transfer_ring_db.phys_base; + + in_param->notify = NULL; + in_param->u_tx.tx.event_ring_base_pa = + test_wdi3_ctx->tx_event_ring_addr.phys_base; + in_param->u_tx.tx.event_ring_size = + test_wdi3_ctx->tx_event_ring_addr.size; + in_param->u_tx.tx.event_ring_doorbell_pa = + test_wdi3_ctx->tx_event_ring_db.phys_base; + IPA_UT_DBG("tx_event_ring_db.phys_base %llu\n", + test_wdi3_ctx->tx_event_ring_db.phys_base); + IPA_UT_DBG("tx_event_ring_db.base %pK\n", + test_wdi3_ctx->tx_event_ring_db.base); + IPA_UT_DBG("tx_event_ring.phys_base %llu\n", + test_wdi3_ctx->tx_event_ring_addr.phys_base); + IPA_UT_DBG("tx_event_ring.base %pK\n", + test_wdi3_ctx->tx_event_ring_addr.base); + + in_param->u_tx.tx.num_pkt_buffers = NUM_TX_BUFS; + + /* setup tx1 parameters */ + in_param->is_tx1_used = true; + in_param->u_tx1.tx.client = IPA_CLIENT_WLAN2_CONS1; + in_param->u_tx1.tx.transfer_ring_base_pa = + test_wdi3_ctx->tx1_transfer_ring_addr.phys_base; + in_param->u_tx1.tx.transfer_ring_size = + test_wdi3_ctx->tx1_transfer_ring_addr.size; + in_param->u_tx1.tx.transfer_ring_doorbell_pa = + test_wdi3_ctx->tx1_transfer_ring_db.phys_base; + + in_param->u_tx1.tx.event_ring_base_pa = + test_wdi3_ctx->tx1_event_ring_addr.phys_base; + in_param->u_tx1.tx.event_ring_size = + test_wdi3_ctx->tx1_event_ring_addr.size; + in_param->u_tx1.tx.event_ring_doorbell_pa = + test_wdi3_ctx->tx1_event_ring_db.phys_base; + IPA_UT_DBG("tx1_event_ring_db.phys_base %llu\n", + test_wdi3_ctx->tx1_event_ring_db.phys_base); + IPA_UT_DBG("tx1_event_ring_db.base %pK\n", + test_wdi3_ctx->tx1_event_ring_db.base); + IPA_UT_DBG("tx1_event_ring.phys_base %llu\n", + test_wdi3_ctx->tx1_event_ring_addr.phys_base); + IPA_UT_DBG("tx1_event_ring.base %pK\n", + test_wdi3_ctx->tx1_event_ring_addr.base); + + in_param->u_tx1.tx.num_pkt_buffers = NUM_TX_BUFS; + + /* setup rx parameters */ + in_param->u_rx.rx.client = IPA_CLIENT_WLAN2_PROD; + in_param->u_rx.rx.transfer_ring_base_pa = + test_wdi3_ctx->rx_transfer_ring_addr.phys_base; + in_param->u_rx.rx.transfer_ring_size = + test_wdi3_ctx->rx_transfer_ring_addr.size; + in_param->u_rx.rx.transfer_ring_doorbell_pa = + test_wdi3_ctx->rx_transfer_ring_db.phys_base; + in_param->u_rx.rx.pkt_offset = PACKET_HEADER_SIZE; + + + in_param->u_rx.rx.event_ring_base_pa = + test_wdi3_ctx->rx_event_ring_addr.phys_base; + in_param->u_rx.rx.event_ring_size = + test_wdi3_ctx->rx_event_ring_addr.size; + in_param->u_rx.rx.event_ring_doorbell_pa = + test_wdi3_ctx->rx_event_ring_db.phys_base; + + IPA_UT_DBG("rx_event_ring_db.phys_base %llu\n", + in_param->u_rx.rx.event_ring_doorbell_pa); + IPA_UT_DBG("rx_event_ring_db.base %pK\n", + test_wdi3_ctx->rx_event_ring_addr.base); + + in_param->u_rx.rx.num_pkt_buffers = NUM_RX_BUFS; + if (ipa_wdi_conn_pipes(in_param, out_param)) { + IPA_UT_ERR("fail to conn wdi3 pipes.\n"); + kfree(in_param); + kfree(out_param); + return -EFAULT; + } + + if (ipa_wdi_enable_pipes()) { + IPA_UT_ERR("fail to enable wdi3 pipes.\n"); + ipa_wdi_disconn_pipes(); + kfree(in_param); + kfree(out_param); + return -EFAULT; + } + + test_wdi3_ctx->tx_uc_db_pa = out_param->tx_uc_db_pa; + test_wdi3_ctx->tx1_uc_db_pa = out_param->tx1_uc_db_pa; + test_wdi3_ctx->rx_uc_db_pa = out_param->rx_uc_db_pa; + IPA_UT_DBG( + "tx_uc_db_pa %llu, rx_uc_db_pa %llu, tx1_uc_db_pa %llu.\n", + test_wdi3_ctx->tx_uc_db_pa, test_wdi3_ctx->rx_uc_db_pa, + test_wdi3_ctx->tx1_uc_db_pa); + + rx_uc_db = ioremap(test_wdi3_ctx->rx_uc_db_pa, DB_REGISTER_SIZE); + tx_uc_db = ioremap(test_wdi3_ctx->tx_uc_db_pa, DB_REGISTER_SIZE); + tx1_uc_db = ioremap(test_wdi3_ctx->tx1_uc_db_pa, DB_REGISTER_SIZE); + + /* setup db registers */ + *(u32 *)test_wdi3_ctx->rx_transfer_ring_db.base = rx_uc_db_local; + *(u32 *)test_wdi3_ctx->rx_event_ring_db.base = 0; + + *(u32 *)test_wdi3_ctx->tx_transfer_ring_db.base = tx_uc_db_local; + *(u32 *)test_wdi3_ctx->tx_event_ring_db.base = 0; + + *(u32 *)test_wdi3_ctx->tx1_transfer_ring_db.base = tx1_uc_db_local; + *(u32 *)test_wdi3_ctx->tx1_event_ring_db.base = 0; + + rx_transfer = (struct rx_transfer_ring_ele *) + test_wdi3_ctx->rx_transfer_ring_addr.base; + for (i = 0; i < NUM_TX_BUFS; i++) { + rx_transfer->buf_or_link_desc_addr_info.buffer_addr_low = + (u64)test_wdi3_ctx->rx_bufs[i].phys_base & 0xFFFFFFFF; + rx_transfer->buf_or_link_desc_addr_info.buffer_addr_high = + ((u64)test_wdi3_ctx->rx_bufs[i].phys_base >> 32) + & 0xFFFFFFFF; + rx_transfer++; + } + + tx_transfer_base = (struct tx_transfer_ring_ele *) + test_wdi3_ctx->tx_transfer_ring_addr.base; + index = tx_uc_db_local; + for (i = 0; i < NUM_TX_BUFS; i++) { + tx_transfer = tx_transfer_base + index; + tx_transfer->buf_or_link_desc_addr_info.buffer_addr_low = + (u64)test_wdi3_ctx->tx_bufs[i].phys_base & 0xFFFFFFFF; + tx_transfer->buf_or_link_desc_addr_info.buffer_addr_high = + ((u64)test_wdi3_ctx->tx_bufs[i].phys_base >> 32) + & 0xFFFFFFFF; + index = (index + 1) % NUM_TX_TR_ELE; + } + ipa_test_wdi3_advance_uc_db(&tx_uc_db_local, NUM_TX_BUFS, + sizeof(struct tx_transfer_ring_ele)/4, + test_wdi3_ctx->tx_transfer_ring_addr.size); + iowrite32(tx_uc_db_local, tx_uc_db); + + tx1_transfer_base = (struct tx_transfer_ring_ele *) + test_wdi3_ctx->tx1_transfer_ring_addr.base; + index = tx1_uc_db_local; + for (i = 0; i < NUM_TX_BUFS; i++) { + tx1_transfer = tx1_transfer_base + index; + tx1_transfer->buf_or_link_desc_addr_info.buffer_addr_low = + (u64)test_wdi3_ctx->tx1_bufs[i].phys_base & 0xFFFFFFFF; + tx1_transfer->buf_or_link_desc_addr_info.buffer_addr_high = + ((u64)test_wdi3_ctx->tx1_bufs[i].phys_base >> 32) + & 0xFFFFFFFF; + index = (index + 1) % NUM_TX_TR_ELE; + } + ipa_test_wdi3_advance_uc_db(&tx1_uc_db_local, NUM_TX_BUFS, + sizeof(struct tx_transfer_ring_ele)/4, + test_wdi3_ctx->tx1_transfer_ring_addr.size); + iowrite32(tx1_uc_db_local, tx1_uc_db); + kfree(in_param); + kfree(out_param); + return 0; +} + +static int ipa_wdi3_send_one_packet(void) +{ + void __iomem *rx_uc_db; + void __iomem *tx_uc_db; + u32 *tx_event_ring_db, *rx_transfer_ring_db, *rx_event_ring_db; + u32 orig_tx_event_ring_db; + u32 orig_rx_event_ring_db; + u32 orig_tx_trans_ring_db; + u32 *packet; + u32 *packet_recv = NULL; + struct rx_transfer_ring_ele *rx_transfer; + struct rx_event_ring_ele *rx_event; + struct tx_event_ring_ele *tx_event; + struct tx_transfer_ring_ele *tx_transfer; + struct buffer_addr_info rx_buf; + dma_addr_t recv_packet_addr; + int loop_cnt, i, num_words; + int idx; + + /* populate packet content */ + rx_uc_db = ioremap(test_wdi3_ctx->rx_uc_db_pa, DB_REGISTER_SIZE); + num_words = sizeof(struct rx_transfer_ring_ele) / 4; + idx = rx_uc_db_local / num_words; + packet = (u32 *)test_wdi3_ctx->rx_bufs[rx_bf_idx].base + + PACKET_HEADER_SIZE/4; + *packet = PACKET_CONTENT; + IPA_UT_DBG("local rx uc db: %u, rx buffer index %d\n", + rx_uc_db_local, rx_bf_idx); + rx_bf_idx = (rx_bf_idx + 1) % NUM_RX_BUFS; + /* update rx_transfer_ring_ele */ + rx_transfer = (struct rx_transfer_ring_ele *) + (test_wdi3_ctx->rx_transfer_ring_addr.base) + + idx; + + ipa_test_wdi3_advance_uc_db(&rx_uc_db_local, 1, + sizeof(struct rx_transfer_ring_ele)/4, + test_wdi3_ctx->rx_transfer_ring_addr.size); + rx_transfer->rx_msdu_desc_info_details.msdu_length = + ETH_PACKET_SIZE + PACKET_HEADER_SIZE; + + rx_buf.buffer_addr_low = + rx_transfer->buf_or_link_desc_addr_info.buffer_addr_low; + rx_buf.buffer_addr_high = + rx_transfer->buf_or_link_desc_addr_info.buffer_addr_high; + + tx_event_ring_db = (u32 *)test_wdi3_ctx->tx_event_ring_db.base; + orig_tx_event_ring_db = *tx_event_ring_db; + IPA_UT_DBG("original tx event ring db: %u\n", + orig_tx_event_ring_db); + + rx_event_ring_db = (u32 *)test_wdi3_ctx->rx_event_ring_db.base; + orig_rx_event_ring_db = *rx_event_ring_db; + IPA_UT_DBG("original rx event ring db: %u\n", + orig_rx_event_ring_db); + + rx_transfer_ring_db + = (u32 *)test_wdi3_ctx->rx_transfer_ring_db.base; + orig_tx_trans_ring_db = *rx_transfer_ring_db; + IPA_UT_DBG("original rx transfer ring db: %u\n", + *rx_transfer_ring_db); + + /* ring uc db */ + iowrite32(rx_uc_db_local, rx_uc_db); + IPA_UT_DBG("rx db local: %u\n", rx_uc_db_local); + + loop_cnt = 0; + while (orig_tx_event_ring_db == *tx_event_ring_db || + *rx_event_ring_db == orig_rx_event_ring_db) { + loop_cnt++; + IPA_UT_DBG("loop count: %d tx\n", loop_cnt); + IPA_UT_DBG("orig_tx_event_ring_db: %u tx_event_ring_db: %u\n", + orig_tx_event_ring_db, *tx_event_ring_db); + IPA_UT_DBG("rx_transfer_ring_db: %u rx db local: %u\n", + *rx_transfer_ring_db, rx_uc_db_local); + IPA_UT_DBG("orig_rx_event_ring_db: %u rx_event_ring_db %u\n", + orig_rx_event_ring_db, *rx_event_ring_db); + if (loop_cnt == 1000) { + IPA_UT_ERR("transfer timeout!\n"); + gsi_wdi3_dump_register(1); + gsi_wdi3_dump_register(9); + BUG(); + return -EFAULT; + } + usleep_range(1000, 1001); + } + IPA_UT_DBG("rx_transfer_ring_db: %u\n", *rx_transfer_ring_db); + IPA_UT_DBG("tx_event_ring_db: %u\n", *tx_event_ring_db); + num_words = sizeof(struct rx_event_ring_ele)/4; + rx_event = (struct rx_event_ring_ele *) + (test_wdi3_ctx->rx_event_ring_addr.base) + + (*rx_event_ring_db/num_words - 1 + NUM_RX_ER_ELE) % + NUM_RX_ER_ELE; + IPA_UT_DBG("rx_event offset: %u\n", + (*rx_event_ring_db/num_words - 1 + NUM_RX_ER_ELE) % + NUM_RX_ER_ELE); + IPA_UT_DBG("rx_event va: %pK\n", rx_event); + IPA_UT_DBG("rx event low: %u rx event high: %u\n", + rx_event->buf_or_link_desc_addr_info.buffer_addr_low, + rx_event->buf_or_link_desc_addr_info.buffer_addr_high); + IPA_UT_DBG("rx buf low: %u rx buf high: %u\n", + rx_buf.buffer_addr_low, rx_buf.buffer_addr_high); + if (rx_event->buf_or_link_desc_addr_info.buffer_addr_low != + rx_buf.buffer_addr_low || + rx_event->buf_or_link_desc_addr_info.buffer_addr_high != + rx_buf.buffer_addr_high) { + IPA_UT_ERR("rx event ring buf addr doesn't match.\n"); + BUG(); + return -EFAULT; + } + + num_words = sizeof(struct tx_event_ring_ele)/4; + tx_event = (struct tx_event_ring_ele *) + test_wdi3_ctx->tx_event_ring_addr.base + + (*tx_event_ring_db/num_words - 1 + NUM_TX_ER_ELE) % + NUM_TX_ER_ELE; + IPA_UT_DBG("tx_event va: %pK\n", tx_event); + IPA_UT_DBG("tx event offset: %u\n", + (*tx_event_ring_db/num_words - 1 + NUM_TX_ER_ELE) % + NUM_TX_ER_ELE); + IPA_UT_DBG("recv addr low: %u recv_addr high: %u\n", + tx_event->buf_or_link_desc_addr_info.buffer_addr_low, + tx_event->buf_or_link_desc_addr_info.buffer_addr_high); + recv_packet_addr = + ((u64)tx_event->buf_or_link_desc_addr_info.buffer_addr_high + << 32) | + (u64)tx_event->buf_or_link_desc_addr_info.buffer_addr_low; + IPA_UT_DBG("high: %llu low: %llu all: %llu\n", + (u64)tx_event->buf_or_link_desc_addr_info.buffer_addr_high + << 32, + (u64)tx_event->buf_or_link_desc_addr_info.buffer_addr_low, + recv_packet_addr); + for (i = 0; i < NUM_TX_BUFS; i++) + if (recv_packet_addr == test_wdi3_ctx->tx_bufs[i].phys_base) { + IPA_UT_DBG("found buf at position %d\n", i); + packet_recv = (u32 *)test_wdi3_ctx->tx_bufs[i].base; + } + IPA_UT_DBG("packet_recv addr: %pK\n", packet_recv); + if (*packet_recv != PACKET_CONTENT) { + IPA_UT_ERR("recv packet doesn't match.\n"); + IPA_UT_ERR("packet: %d packet_recv: %d\n", PACKET_CONTENT, + *packet_recv); + return -EFAULT; + } + IPA_UT_INFO("recv packet matches!! Recycling the buffer ...\n"); + /* recycle buffer */ + tx_uc_db = ioremap(test_wdi3_ctx->tx_uc_db_pa, DB_REGISTER_SIZE); + num_words = sizeof(struct tx_transfer_ring_ele) / 4; + idx = tx_uc_db_local / num_words; + IPA_UT_DBG("tx_db_local: %u idx %d\n", tx_uc_db_local, idx); + tx_transfer = (struct tx_transfer_ring_ele *) + test_wdi3_ctx->tx_transfer_ring_addr.base + idx; + tx_transfer->buf_or_link_desc_addr_info.buffer_addr_low = + tx_event->buf_or_link_desc_addr_info.buffer_addr_low; + tx_transfer->buf_or_link_desc_addr_info.buffer_addr_high = + tx_event->buf_or_link_desc_addr_info.buffer_addr_high; + ipa_test_wdi3_advance_uc_db(&tx_uc_db_local, 1, + sizeof(struct tx_transfer_ring_ele)/4, + test_wdi3_ctx->tx_transfer_ring_addr.size); + iowrite32(tx_uc_db_local, tx_uc_db); + tx_bf_idx = (tx_bf_idx + 1) % NUM_TX_BUFS; + return 0; +} + +static int ipa_wdi3_send_one_packet_2g_5g(bool tx1_pipe_test) +{ + void __iomem *rx_uc_db; + void __iomem *tx_uc_db; + void __iomem *tx1_uc_db; + u32 *tx_event_ring_db, *rx_transfer_ring_db, *rx_event_ring_db; + u32 *tx1_event_ring_db; + u32 orig_tx_event_ring_db; + u32 orig_tx1_event_ring_db; + u32 orig_rx_event_ring_db; + u32 orig_tx_trans_ring_db; + u32 orig_tx1_trans_ring_db; + u32 *packet; + u32 *packet_recv = NULL; + struct rx_transfer_ring_ele *rx_transfer; + struct rx_event_ring_ele *rx_event; + struct tx_event_ring_ele *tx_event; + struct tx_event_ring_ele *tx1_event; + struct tx_transfer_ring_ele *tx_transfer; + struct tx_transfer_ring_ele *tx1_transfer; + struct buffer_addr_info rx_buf; + dma_addr_t recv_packet_addr; + int loop_cnt, i, num_words; + int idx; + + if (!tx1_pipe_test) { + /* populate packet content */ + rx_uc_db = ioremap(test_wdi3_ctx->rx_uc_db_pa, + DB_REGISTER_SIZE); + num_words = sizeof(struct rx_transfer_ring_ele) / 4; + idx = rx_uc_db_local / num_words; + packet = (u32 *)test_wdi3_ctx->rx_bufs[rx_bf_idx].base + + PACKET_HEADER_SIZE/4; + *packet = PACKET_CONTENT; + IPA_UT_DBG("local rx uc db: %u, rx buffer index %d\n", + rx_uc_db_local, rx_bf_idx); + rx_bf_idx = (rx_bf_idx + 1) % NUM_RX_BUFS; + /* update rx_transfer_ring_ele */ + rx_transfer = (struct rx_transfer_ring_ele *) + (test_wdi3_ctx->rx_transfer_ring_addr.base) + + idx; + + ipa_test_wdi3_advance_uc_db(&rx_uc_db_local, 1, + sizeof(struct rx_transfer_ring_ele)/4, + test_wdi3_ctx->rx_transfer_ring_addr.size); + rx_transfer->rx_msdu_desc_info_details.msdu_length = + ETH_PACKET_SIZE + PACKET_HEADER_SIZE; + + rx_buf.buffer_addr_low = + rx_transfer->buf_or_link_desc_addr_info.buffer_addr_low; + rx_buf.buffer_addr_high = + rx_transfer->buf_or_link_desc_addr_info.buffer_addr_high; + + tx_event_ring_db = + (u32 *)test_wdi3_ctx->tx_event_ring_db.base; + orig_tx_event_ring_db = *tx_event_ring_db; + IPA_UT_DBG("original tx event ring db: %u\n", + orig_tx_event_ring_db); + + rx_event_ring_db = + (u32 *)test_wdi3_ctx->rx_event_ring_db.base; + orig_rx_event_ring_db = *rx_event_ring_db; + IPA_UT_DBG("original rx event ring db: %u\n", + orig_rx_event_ring_db); + + rx_transfer_ring_db + = (u32 *)test_wdi3_ctx->rx_transfer_ring_db.base; + orig_tx_trans_ring_db = *rx_transfer_ring_db; + IPA_UT_DBG("original rx transfer ring db: %u\n", + *rx_transfer_ring_db); + + /* ring uc db */ + iowrite32(rx_uc_db_local, rx_uc_db); + IPA_UT_DBG("rx db local: %u\n", rx_uc_db_local); + + loop_cnt = 0; + while (orig_tx_event_ring_db == *tx_event_ring_db || + *rx_event_ring_db == orig_rx_event_ring_db) { + loop_cnt++; + IPA_UT_DBG("loop count: %d tx\n", loop_cnt); + IPA_UT_DBG( + "orig_tx_event_ring_db: %u tx_event_ring_db: %u\n", + orig_tx_event_ring_db, *tx_event_ring_db); + IPA_UT_DBG( + "rx_transfer_ring_db: %u rx db local: %u\n", + *rx_transfer_ring_db, rx_uc_db_local); + IPA_UT_DBG( + "orig_rx_event_ring_db: %u rx_event_ring_db %u\n", + orig_rx_event_ring_db, *rx_event_ring_db); + if (loop_cnt == 1000) { + IPA_UT_ERR("transfer timeout!\n"); + gsi_wdi3_dump_register(1); + gsi_wdi3_dump_register(9); + BUG(); + return -EFAULT; + } + usleep_range(1000, 1001); + } + IPA_UT_DBG( + "rx_transfer_ring_db: %u\n", *rx_transfer_ring_db); + IPA_UT_DBG("tx_event_ring_db: %u\n", *tx_event_ring_db); + num_words = sizeof(struct rx_event_ring_ele)/4; + rx_event = (struct rx_event_ring_ele *) + (test_wdi3_ctx->rx_event_ring_addr.base) + + (*rx_event_ring_db/num_words - 1 + NUM_RX_ER_ELE) % + NUM_RX_ER_ELE; + IPA_UT_DBG("rx_event offset: %u\n", + (*rx_event_ring_db/num_words - 1 + NUM_RX_ER_ELE) % + NUM_RX_ER_ELE); + IPA_UT_DBG("rx_event va: %pK\n", rx_event); + IPA_UT_DBG("rx event low: %u rx event high: %u\n", + rx_event->buf_or_link_desc_addr_info.buffer_addr_low, + rx_event->buf_or_link_desc_addr_info.buffer_addr_high); + IPA_UT_DBG("rx buf low: %u rx buf high: %u\n", + rx_buf.buffer_addr_low, rx_buf.buffer_addr_high); + if (rx_event->buf_or_link_desc_addr_info.buffer_addr_low != + rx_buf.buffer_addr_low || + rx_event->buf_or_link_desc_addr_info.buffer_addr_high != + rx_buf.buffer_addr_high) { + IPA_UT_ERR("rx event ring buf addr doesn't match.\n"); + BUG(); + return -EFAULT; + } + + num_words = sizeof(struct tx_event_ring_ele)/4; + tx_event = (struct tx_event_ring_ele *) + test_wdi3_ctx->tx_event_ring_addr.base + + (*tx_event_ring_db/num_words - 1 + NUM_TX_ER_ELE) % + NUM_TX_ER_ELE; + IPA_UT_DBG("tx_event va: %pK\n", tx_event); + IPA_UT_DBG("tx event offset: %u\n", + (*tx_event_ring_db/num_words - 1 + NUM_TX_ER_ELE) % + NUM_TX_ER_ELE); + IPA_UT_DBG("recv addr low: %u recv_addr high: %u\n", + tx_event->buf_or_link_desc_addr_info.buffer_addr_low, + tx_event->buf_or_link_desc_addr_info.buffer_addr_high); + recv_packet_addr = ((u64) + tx_event->buf_or_link_desc_addr_info.buffer_addr_high + << 32) | (u64) + tx_event->buf_or_link_desc_addr_info.buffer_addr_low; + IPA_UT_DBG("high: %llu low: %llu all: %llu\n", (u64) + tx_event->buf_or_link_desc_addr_info.buffer_addr_high + << 32, (u64) + tx_event->buf_or_link_desc_addr_info.buffer_addr_low, + recv_packet_addr); + for (i = 0; i < NUM_TX_BUFS; i++) + if (recv_packet_addr == + test_wdi3_ctx->tx_bufs[i].phys_base) { + IPA_UT_DBG("found buf at position %d\n", i); + packet_recv = + (u32 *)test_wdi3_ctx->tx_bufs[i].base; + } + IPA_UT_DBG("packet_recv addr: %pK\n", packet_recv); + if (*packet_recv != PACKET_CONTENT) { + IPA_UT_ERR("recv packet doesn't match.\n"); + IPA_UT_ERR("packet: %d packet_recv: %d\n", + PACKET_CONTENT, *packet_recv); + return -EFAULT; + } + IPA_UT_INFO( + "recv packet matches!! Recycling the buffer ...\n"); + /* recycle buffer */ + tx_uc_db = + ioremap(test_wdi3_ctx->tx_uc_db_pa, DB_REGISTER_SIZE); + num_words = sizeof(struct tx_transfer_ring_ele) / 4; + idx = tx_uc_db_local / num_words; + IPA_UT_DBG("tx_db_local: %u idx %d\n", tx_uc_db_local, idx); + tx_transfer = (struct tx_transfer_ring_ele *) + test_wdi3_ctx->tx_transfer_ring_addr.base + idx; + tx_transfer->buf_or_link_desc_addr_info.buffer_addr_low = + tx_event->buf_or_link_desc_addr_info.buffer_addr_low; + tx_transfer->buf_or_link_desc_addr_info.buffer_addr_high = + tx_event->buf_or_link_desc_addr_info.buffer_addr_high; + ipa_test_wdi3_advance_uc_db(&tx_uc_db_local, 1, + sizeof(struct tx_transfer_ring_ele)/4, + test_wdi3_ctx->tx_transfer_ring_addr.size); + iowrite32(tx_uc_db_local, tx_uc_db); + tx_bf_idx = (tx_bf_idx + 1) % NUM_TX_BUFS; + return 0; + } + + /* populate packet content - For transfer through tx1 pipe */ + rx_uc_db = + ioremap(test_wdi3_ctx->rx_uc_db_pa, DB_REGISTER_SIZE); + num_words = sizeof(struct rx_transfer_ring_ele) / 4; + idx = rx_uc_db_local / num_words; + packet = (u32 *)test_wdi3_ctx->rx_bufs[rx_bf_idx].base + + PACKET_HEADER_SIZE/4; + *packet = PACKET_CONTENT; + IPA_UT_DBG("local rx uc db: %u, rx buffer index %d\n", + rx_uc_db_local, rx_bf_idx); + rx_bf_idx = (rx_bf_idx + 1) % NUM_RX_BUFS; + /* update rx_transfer_ring_ele */ + rx_transfer = (struct rx_transfer_ring_ele *) + (test_wdi3_ctx->rx_transfer_ring_addr.base) + + idx; + + ipa_test_wdi3_advance_uc_db(&rx_uc_db_local, 1, + sizeof(struct rx_transfer_ring_ele)/4, + test_wdi3_ctx->rx_transfer_ring_addr.size); + rx_transfer->rx_msdu_desc_info_details.msdu_length = + ETH_PACKET_SIZE + PACKET_HEADER_SIZE; + + rx_buf.buffer_addr_low = + rx_transfer->buf_or_link_desc_addr_info.buffer_addr_low; + rx_buf.buffer_addr_high = + rx_transfer->buf_or_link_desc_addr_info.buffer_addr_high; + + tx1_event_ring_db = + (u32 *)test_wdi3_ctx->tx1_event_ring_db.base; + orig_tx1_event_ring_db = *tx1_event_ring_db; + IPA_UT_DBG("original tx1 event ring db: %u\n", + orig_tx1_event_ring_db); + + rx_event_ring_db = (u32 *)test_wdi3_ctx->rx_event_ring_db.base; + orig_rx_event_ring_db = *rx_event_ring_db; + IPA_UT_DBG("original rx event ring db: %u\n", + orig_rx_event_ring_db); + + rx_transfer_ring_db + = (u32 *)test_wdi3_ctx->rx_transfer_ring_db.base; + orig_tx1_trans_ring_db = *rx_transfer_ring_db; + IPA_UT_DBG("original rx transfer ring db: %u\n", + *rx_transfer_ring_db); + + /* ring uc db */ + iowrite32(rx_uc_db_local, rx_uc_db); + IPA_UT_DBG("rx db local: %u\n", rx_uc_db_local); + + loop_cnt = 0; + while (orig_tx1_event_ring_db == *tx1_event_ring_db || + *rx_event_ring_db == orig_rx_event_ring_db) { + loop_cnt++; + IPA_UT_DBG("loop count: %d tx\n", loop_cnt); + IPA_UT_DBG( + "orig_tx1_event_ring_db: %u tx1_event_ring_db: %u\n", + orig_tx1_event_ring_db, *tx1_event_ring_db); + IPA_UT_DBG("rx_transfer_ring_db: %u rx db local: %u\n", + *rx_transfer_ring_db, rx_uc_db_local); + IPA_UT_DBG( + "orig_rx_event_ring_db: %u rx_event_ring_db %u\n", + orig_rx_event_ring_db, *rx_event_ring_db); + if (loop_cnt == 1000) { + IPA_UT_ERR("transfer timeout!\n"); + gsi_wdi3_dump_register(1); + gsi_wdi3_dump_register(9); + BUG(); + return -EFAULT; + } + usleep_range(1000, 1001); + } + IPA_UT_DBG("rx_transfer_ring_db: %u\n", *rx_transfer_ring_db); + IPA_UT_DBG("tx1_event_ring_db: %u\n", *tx1_event_ring_db); + num_words = sizeof(struct rx_event_ring_ele)/4; + rx_event = (struct rx_event_ring_ele *) + (test_wdi3_ctx->rx_event_ring_addr.base) + + (*rx_event_ring_db/num_words - 1 + NUM_RX_ER_ELE) % + NUM_RX_ER_ELE; + IPA_UT_DBG("rx_event offset: %u\n", + (*rx_event_ring_db/num_words - 1 + NUM_RX_ER_ELE) % + NUM_RX_ER_ELE); + IPA_UT_DBG("rx_event va: %pK\n", rx_event); + IPA_UT_DBG("rx event low: %u rx event high: %u\n", + rx_event->buf_or_link_desc_addr_info.buffer_addr_low, + rx_event->buf_or_link_desc_addr_info.buffer_addr_high); + IPA_UT_DBG("rx buf low: %u rx buf high: %u\n", + rx_buf.buffer_addr_low, rx_buf.buffer_addr_high); + if (rx_event->buf_or_link_desc_addr_info.buffer_addr_low != + rx_buf.buffer_addr_low || + rx_event->buf_or_link_desc_addr_info.buffer_addr_high != + rx_buf.buffer_addr_high) { + IPA_UT_ERR("rx event ring buf addr doesn't match.\n"); + BUG(); + return -EFAULT; + } + + num_words = sizeof(struct tx_event_ring_ele)/4; + tx1_event = (struct tx_event_ring_ele *) + test_wdi3_ctx->tx1_event_ring_addr.base + + (*tx1_event_ring_db/num_words - 1 + NUM_TX_ER_ELE) % + NUM_TX_ER_ELE; + IPA_UT_DBG("tx1_event va: %pK\n", tx1_event); + IPA_UT_DBG("tx1 event offset: %u\n", + (*tx1_event_ring_db/num_words - 1 + NUM_TX_ER_ELE) % + NUM_TX_ER_ELE); + IPA_UT_DBG("recv addr low: %u recv_addr high: %u\n", + tx1_event->buf_or_link_desc_addr_info.buffer_addr_low, + tx1_event->buf_or_link_desc_addr_info.buffer_addr_high); + recv_packet_addr = + ((u64)tx1_event->buf_or_link_desc_addr_info.buffer_addr_high + << 32) | + (u64)tx1_event->buf_or_link_desc_addr_info.buffer_addr_low; + IPA_UT_DBG("high: %llu low: %llu all: %llu\n", + (u64)tx1_event->buf_or_link_desc_addr_info.buffer_addr_high + << 32, + (u64)tx1_event->buf_or_link_desc_addr_info.buffer_addr_low, + recv_packet_addr); + for (i = 0; i < NUM_TX_BUFS; i++) + if (recv_packet_addr == + test_wdi3_ctx->tx1_bufs[i].phys_base) { + IPA_UT_DBG("found buf at position %d\n", i); + packet_recv = (u32 *)test_wdi3_ctx->tx1_bufs[i].base; + } + IPA_UT_DBG("packet_recv addr: %pK\n", packet_recv); + if (*packet_recv != PACKET_CONTENT) { + IPA_UT_ERR("recv packet doesn't match.\n"); + IPA_UT_ERR("packet: %d packet_recv: %d\n", PACKET_CONTENT, + *packet_recv); + return -EFAULT; + } + IPA_UT_INFO("recv packet matches, !! Recycling the buffer ...\n"); + /* recycle buffer */ + tx1_uc_db = + ioremap(test_wdi3_ctx->tx1_uc_db_pa, DB_REGISTER_SIZE); + num_words = sizeof(struct tx_transfer_ring_ele) / 4; + idx = tx1_uc_db_local / num_words; + IPA_UT_DBG("tx1_db_local: %u idx %d\n", tx1_uc_db_local, idx); + tx1_transfer = (struct tx_transfer_ring_ele *) + test_wdi3_ctx->tx1_transfer_ring_addr.base + idx; + tx1_transfer->buf_or_link_desc_addr_info.buffer_addr_low = + tx1_event->buf_or_link_desc_addr_info.buffer_addr_low; + tx1_transfer->buf_or_link_desc_addr_info.buffer_addr_high = + tx1_event->buf_or_link_desc_addr_info.buffer_addr_high; + ipa_test_wdi3_advance_uc_db(&tx1_uc_db_local, 1, + sizeof(struct tx_transfer_ring_ele)/4, + test_wdi3_ctx->tx1_transfer_ring_addr.size); + iowrite32(tx1_uc_db_local, tx1_uc_db); + tx1_bf_idx = (tx1_bf_idx + 1) % NUM_TX_BUFS; + return 0; +} + +static int ipa_wdi3_test_reg_intf(bool is_tx1_used) +{ + struct ipa_wdi_reg_intf_in_params in; + char netdev_name[IPA_RESOURCE_NAME_MAX] = {0}; + u8 hdr_content = 1; + + memset(&in, 0, sizeof(in)); + if (is_tx1_used) + snprintf(netdev_name, sizeof(netdev_name), "wdi3_test_2g"); + else + snprintf(netdev_name, sizeof(netdev_name), "wdi3_test"); + in.netdev_name = netdev_name; + in.is_meta_data_valid = 0; + in.hdr_info[0].hdr = &hdr_content; + in.hdr_info[0].hdr_len = 1; + in.hdr_info[0].dst_mac_addr_offset = 0; + in.hdr_info[0].hdr_type = IPA_HDR_L2_ETHERNET_II; + in.hdr_info[1].hdr = &hdr_content; + in.hdr_info[1].hdr_len = 1; + in.hdr_info[1].dst_mac_addr_offset = 0; + in.hdr_info[1].hdr_type = IPA_HDR_L2_ETHERNET_II; + + return ipa_wdi_reg_intf(&in); +} + +static int ipa_wdi3_test_dereg_intf(bool is_tx1_used) +{ + char netdev_name[IPA_RESOURCE_NAME_MAX] = {0}; + + if (is_tx1_used) + snprintf(netdev_name, sizeof(netdev_name), "wdi3_test_2g"); + else + snprintf(netdev_name, sizeof(netdev_name), "wdi3_test"); + IPA_UT_INFO("netdev name: %s strlen: %lu\n", netdev_name, + strlen(netdev_name)); + + return ipa_wdi_dereg_intf(netdev_name); +} + +static int ipa_wdi3_test_single_transfer(void *priv) +{ + struct ipa_ep_cfg ep_cfg = { {0} }; + bool is_tx1_used = false; + + if (ipa_wdi3_test_reg_intf(is_tx1_used)) { + IPA_UT_ERR("fail to register intf.\n"); + return -EFAULT; + } + + if (ipa_wdi3_setup_pipes()) { + IPA_UT_ERR("fail to setup wdi3 pipes.\n"); + return -EFAULT; + } + + /* configure WLAN RX EP in DMA mode */ + ep_cfg.mode.mode = IPA_DMA; + ep_cfg.mode.dst = IPA_CLIENT_WLAN2_CONS; + + ep_cfg.seq.set_dynamic = true; + + ipa3_cfg_ep(ipa_get_ep_mapping(IPA_CLIENT_WLAN2_PROD), &ep_cfg); + + if (ipa_wdi3_send_one_packet()) { + IPA_UT_ERR("fail to transfer packet.\n"); + ipa_wdi3_teardown_pipes(); + return -EFAULT; + } + + if (ipa_wdi3_teardown_pipes()) { + IPA_UT_ERR("fail to tear down pipes.\n"); + return -EFAULT; + } + + IPA_UT_INFO("pipes were torn down!\n"); + + if (ipa_wdi3_test_dereg_intf(is_tx1_used)) { + IPA_UT_ERR("fail to deregister interface.\n"); + return -EFAULT; + } + + return 0; +} + +static int ipa_wdi3_test_single_transfer_2g_5g(void *priv) +{ + struct ipa_ep_cfg ep_cfg = { {0} }; + bool is_tx1_used = false; + + if (ipa_wdi3_test_reg_intf(is_tx1_used)) { + IPA_UT_ERR("fail to register intf.\n"); + return -EFAULT; + } + + is_tx1_used = true; + if (ipa_wdi3_test_reg_intf(is_tx1_used)) { + IPA_UT_ERR("fail to register 2g intf.\n"); + return -EFAULT; + } + + if (ipa_wdi3_setup_pipes_2g_5g()) { + IPA_UT_ERR("fail to setup wdi3 pipes.\n"); + return -EFAULT; + } + + /* configure WLAN RX EP in DMA mode */ + ep_cfg.mode.mode = IPA_DMA; + ep_cfg.mode.dst = IPA_CLIENT_WLAN2_CONS; + + ep_cfg.seq.set_dynamic = true; + + ipa3_cfg_ep(ipa_get_ep_mapping(IPA_CLIENT_WLAN2_PROD), &ep_cfg); + + if (ipa_wdi3_send_one_packet_2g_5g(false)) { + IPA_UT_ERR("fail to transfer packet.\n"); + ipa_wdi3_teardown_pipes(); + return -EFAULT; + } + + /* configure WLAN RX EP in DMA mode for tx1*/ + ep_cfg.mode.mode = IPA_DMA; + ep_cfg.mode.dst = IPA_CLIENT_WLAN2_CONS1; + + ep_cfg.seq.set_dynamic = true; + + ipa3_cfg_ep(ipa_get_ep_mapping(IPA_CLIENT_WLAN2_PROD), &ep_cfg); + + if (ipa_wdi3_send_one_packet_2g_5g(true)) { + IPA_UT_ERR("fail to transfer packet.\n"); + ipa_wdi3_teardown_pipes(); + return -EFAULT; + } + + if (ipa_wdi3_teardown_pipes()) { + IPA_UT_ERR("fail to tear down pipes.\n"); + return -EFAULT; + } + + IPA_UT_INFO("2g 5g pipes were torn down!\n"); + + if (ipa_wdi3_test_dereg_intf(is_tx1_used)) { + IPA_UT_ERR("fail to deregister interface.\n"); + return -EFAULT; + } + + is_tx1_used = false; + if (ipa_wdi3_test_dereg_intf(is_tx1_used)) { + IPA_UT_ERR("fail to deregister interface.\n"); + return -EFAULT; + } + + return 0; +} + +static int ipa_wdi3_send_multi_packet(void) +{ + void __iomem *rx_uc_db; + void __iomem *tx_uc_db; + u32 *tx_event_ring_db, *rx_transfer_ring_db, *rx_event_ring_db; + u32 orig_tx_event_ring_db; + u32 orig_rx_event_ring_db; + u32 *packet; + u32 *packet_recv = NULL; + struct rx_transfer_ring_ele *rx_transfer; + struct rx_event_ring_ele *rx_event; + struct tx_event_ring_ele *tx_event; + struct tx_transfer_ring_ele *tx_transfer; + struct buffer_addr_info rx_buf; + dma_addr_t recv_packet_addr; + int loop_cnt, i, num_words; + int idx; + + /* populate packet content */ + num_words = sizeof(struct rx_transfer_ring_ele) / 4; + rx_uc_db = ioremap(test_wdi3_ctx->rx_uc_db_pa, DB_REGISTER_SIZE); + for (i = 0; i < NUM_MULTI_PKT; i++) { + idx = rx_uc_db_local / num_words; + packet = (u32 *)test_wdi3_ctx->rx_bufs[rx_bf_idx].base + + PACKET_HEADER_SIZE / 4; + *packet = multi_pkt_array[i]; + IPA_UT_DBG("rx_db_local: %u rx_bf_idx: %d\n", + rx_uc_db_local, rx_bf_idx); + rx_bf_idx = (rx_bf_idx + 1) % NUM_RX_BUFS; + /* update rx_transfer_ring_ele */ + rx_transfer = (struct rx_transfer_ring_ele *) + test_wdi3_ctx->rx_transfer_ring_addr.base + idx; + ipa_test_wdi3_advance_uc_db(&rx_uc_db_local, 1, + sizeof(struct rx_transfer_ring_ele)/4, + test_wdi3_ctx->rx_transfer_ring_addr.size); + rx_transfer->rx_msdu_desc_info_details.msdu_length = + ETH_PACKET_SIZE + PACKET_HEADER_SIZE; + rx_buf.buffer_addr_low = + rx_transfer->buf_or_link_desc_addr_info.buffer_addr_low; + rx_buf.buffer_addr_high = + rx_transfer->buf_or_link_desc_addr_info.buffer_addr_high; + } + + tx_event_ring_db = (u32 *)test_wdi3_ctx->tx_event_ring_db.base; + orig_tx_event_ring_db = *tx_event_ring_db; + IPA_UT_DBG("original tx event ring db: %u\n", orig_tx_event_ring_db); + + rx_event_ring_db = (u32 *)test_wdi3_ctx->rx_event_ring_db.base; + orig_rx_event_ring_db = *rx_event_ring_db; + IPA_UT_DBG("original rx event ring db: %u\n", orig_rx_event_ring_db); + + rx_transfer_ring_db = (u32 *)test_wdi3_ctx->rx_transfer_ring_db.base; + IPA_UT_DBG("original rx transfer ring db: %u\n", *rx_transfer_ring_db); + + /* ring uc db */ + iowrite32(rx_uc_db_local, rx_uc_db); + IPA_UT_DBG("rx db local: %u\n", rx_uc_db_local); + + loop_cnt = 0; + while (orig_tx_event_ring_db == *tx_event_ring_db || + *rx_transfer_ring_db != rx_uc_db_local || + orig_rx_event_ring_db == *rx_event_ring_db) { + loop_cnt++; + IPA_UT_DBG("loop count: %d tx\n", loop_cnt); + IPA_UT_DBG("orig_tx_event_ring_db: %u tx_event_ring_db: %u\n", + orig_tx_event_ring_db, *tx_event_ring_db); + IPA_UT_DBG("rx_transfer_ring_db: %u rx db local: %u\n", + *rx_transfer_ring_db, rx_uc_db_local); + IPA_UT_DBG("orig_rx_event_ring_db: %u rx_event_ring_db %u\n", + orig_rx_event_ring_db, *rx_event_ring_db); + if (loop_cnt == 1000) { + IPA_UT_ERR("transfer timeout!\n"); + BUG(); + return -EFAULT; + } + usleep_range(1000, 1001); + } + + IPA_UT_DBG("rx_transfer_ring_db: %u\n", *rx_transfer_ring_db); + IPA_UT_DBG("tx_event_ring_db: %u\n", *tx_event_ring_db); + num_words = sizeof(struct rx_event_ring_ele)/4; + rx_event = (struct rx_event_ring_ele *) + test_wdi3_ctx->rx_event_ring_addr.base + + (*rx_event_ring_db/num_words - 1 + NUM_RX_ER_ELE) % + NUM_RX_ER_ELE; + IPA_UT_DBG("rx_event va: %pK\n", rx_event); + + IPA_UT_DBG("rx event low: %u rx event high: %u\n", + rx_event->buf_or_link_desc_addr_info.buffer_addr_low, + rx_event->buf_or_link_desc_addr_info.buffer_addr_high); + IPA_UT_DBG("rx buf low: %u rx buf high: %u\n", + rx_buf.buffer_addr_low, rx_buf.buffer_addr_high); + + if (rx_event->buf_or_link_desc_addr_info.buffer_addr_low != + rx_buf.buffer_addr_low || + rx_event->buf_or_link_desc_addr_info.buffer_addr_high != + rx_buf.buffer_addr_high) { + IPA_UT_ERR("rx event ring buf addr doesn't match.\n"); + return -EFAULT; + } + num_words = sizeof(struct tx_event_ring_ele)/4; + tx_event = (struct tx_event_ring_ele *) + test_wdi3_ctx->tx_event_ring_addr.base + + (*tx_event_ring_db/num_words - NUM_MULTI_PKT + NUM_TX_ER_ELE) % + NUM_TX_ER_ELE; + IPA_UT_DBG("tx_event va: %pK\n", tx_event); + IPA_UT_DBG("recv addr low: %u recv_addr high: %u\n", + tx_event->buf_or_link_desc_addr_info.buffer_addr_low, + tx_event->buf_or_link_desc_addr_info.buffer_addr_high); + recv_packet_addr = + ((u64)tx_event->buf_or_link_desc_addr_info.buffer_addr_high + << 32) | + (u64)tx_event->buf_or_link_desc_addr_info.buffer_addr_low; + IPA_UT_DBG("high: %llu low: %llu all: %llu\n", + (u64)tx_event->buf_or_link_desc_addr_info.buffer_addr_high + << 32, + (u64)tx_event->buf_or_link_desc_addr_info.buffer_addr_low, + recv_packet_addr); + for (i = 0; i < NUM_TX_BUFS; i++) + if (recv_packet_addr == test_wdi3_ctx->tx_bufs[i].phys_base) { + IPA_UT_INFO("found buf at position %d\n", i); + packet_recv = (u32 *)test_wdi3_ctx->tx_bufs[i].base; + } + + if (*packet_recv != multi_pkt_array[0]) { + IPA_UT_ERR("recv packet doesn't match.\n"); + IPA_UT_ERR("packet: %d packet_recv: %d\n", + multi_pkt_array[0], *packet_recv); + return -EFAULT; + } + + IPA_UT_INFO("recv packet matches.\n"); + + /* recycle buffer */ + tx_uc_db = ioremap(test_wdi3_ctx->tx_uc_db_pa, DB_REGISTER_SIZE); + num_words = sizeof(struct tx_transfer_ring_ele) / 4; + + for (i = 0; i < NUM_MULTI_PKT; i++) { + idx = tx_uc_db_local / num_words; + IPA_UT_DBG("tx_db_local: %u idx %d\n", tx_uc_db_local, idx); + tx_event = (struct tx_event_ring_ele *) + test_wdi3_ctx->tx_event_ring_addr.base + + (*tx_event_ring_db/num_words - NUM_MULTI_PKT + + i + NUM_TX_ER_ELE) % NUM_TX_ER_ELE; + tx_transfer = (struct tx_transfer_ring_ele *) + test_wdi3_ctx->tx_transfer_ring_addr.base + idx; + tx_transfer->buf_or_link_desc_addr_info.buffer_addr_low = + tx_event->buf_or_link_desc_addr_info.buffer_addr_low; + tx_transfer->buf_or_link_desc_addr_info.buffer_addr_high = + tx_event->buf_or_link_desc_addr_info.buffer_addr_high; + ipa_test_wdi3_advance_uc_db(&tx_uc_db_local, 1, + sizeof(struct tx_transfer_ring_ele)/4, + test_wdi3_ctx->tx_transfer_ring_addr.size); + } + iowrite32(tx_uc_db_local, tx_uc_db); + tx_bf_idx = (tx_bf_idx + NUM_MULTI_PKT) % NUM_TX_BUFS; + return 0; +} + +static int ipa_wdi3_send_multi_packet_2g_5g(bool tx1_pipe_test) +{ + void __iomem *rx_uc_db; + void __iomem *tx_uc_db; + void __iomem *tx1_uc_db; + u32 *tx_event_ring_db, *rx_transfer_ring_db, *rx_event_ring_db; + u32 *tx1_event_ring_db; + u32 orig_tx_event_ring_db; + u32 orig_tx1_event_ring_db; + u32 orig_rx_event_ring_db; + u32 *packet; + u32 *packet_recv = NULL; + struct rx_transfer_ring_ele *rx_transfer; + struct rx_transfer_ring_ele *rt; + struct rx_event_ring_ele *rx_event; + struct tx_event_ring_ele *tx_event; + struct tx_event_ring_ele *tx1_event; + struct tx_event_ring_ele *te; + struct tx_transfer_ring_ele *tx_transfer; + struct tx_transfer_ring_ele *tx1_transfer; + struct buffer_addr_info rx_buf; + dma_addr_t recv_packet_addr; + int loop_cnt, i, num_words; + int idx; + + if (!tx1_pipe_test) { + /* populate packet content */ + num_words = sizeof(struct rx_transfer_ring_ele) / 4; + rx_uc_db = ioremap(test_wdi3_ctx->rx_uc_db_pa, + DB_REGISTER_SIZE); + for (i = 0; i < NUM_MULTI_PKT; i++) { + idx = rx_uc_db_local / num_words; + packet = (u32 *)test_wdi3_ctx->rx_bufs[rx_bf_idx].base + + PACKET_HEADER_SIZE / 4; + *packet = multi_pkt_array[i]; + IPA_UT_DBG("rx_db_local: %u rx_bf_idx: %d\n", + rx_uc_db_local, rx_bf_idx); + rx_bf_idx = (rx_bf_idx + 1) % NUM_RX_BUFS; + /* update rx_transfer_ring_ele */ + rx_transfer = (struct rx_transfer_ring_ele *) + test_wdi3_ctx->rx_transfer_ring_addr.base + idx; + rt = rx_transfer; + ipa_test_wdi3_advance_uc_db(&rx_uc_db_local, 1, + sizeof(struct rx_transfer_ring_ele)/4, + test_wdi3_ctx->rx_transfer_ring_addr.size); + rt->rx_msdu_desc_info_details.msdu_length = + ETH_PACKET_SIZE + PACKET_HEADER_SIZE; + rx_buf.buffer_addr_low = + rt->buf_or_link_desc_addr_info.buffer_addr_low; + rx_buf.buffer_addr_high = + rt->buf_or_link_desc_addr_info.buffer_addr_high; + } + + tx_event_ring_db = + (u32 *)test_wdi3_ctx->tx_event_ring_db.base; + orig_tx_event_ring_db = *tx_event_ring_db; + IPA_UT_DBG("original tx event ring db: %u\n", + orig_tx_event_ring_db); + + rx_event_ring_db = + (u32 *)test_wdi3_ctx->rx_event_ring_db.base; + orig_rx_event_ring_db = *rx_event_ring_db; + IPA_UT_DBG("original rx event ring db: %u\n", + orig_rx_event_ring_db); + + rx_transfer_ring_db = + (u32 *)test_wdi3_ctx->rx_transfer_ring_db.base; + IPA_UT_DBG("original rx transfer ring db: %u\n", + *rx_transfer_ring_db); + + /* ring uc db */ + iowrite32(rx_uc_db_local, rx_uc_db); + IPA_UT_DBG("rx db local: %u\n", rx_uc_db_local); + + loop_cnt = 0; + while (orig_tx_event_ring_db == *tx_event_ring_db || + *rx_transfer_ring_db != rx_uc_db_local || + orig_rx_event_ring_db == *rx_event_ring_db) { + loop_cnt++; + IPA_UT_DBG("loop count: %d tx\n", loop_cnt); + IPA_UT_DBG( + "orig_tx_event_ring_db: %u tx_event_ring_db: %u\n", + orig_tx_event_ring_db, *tx_event_ring_db); + IPA_UT_DBG("rx_transfer_ring_db: %u rx db local: %u\n", + *rx_transfer_ring_db, rx_uc_db_local); + IPA_UT_DBG( + "orig_rx_event_ring_db: %u rx_event_ring_db %u\n", + orig_rx_event_ring_db, *rx_event_ring_db); + if (loop_cnt == 1000) { + IPA_UT_ERR("transfer timeout!\n"); + BUG(); + return -EFAULT; + } + usleep_range(1000, 1001); + } + + IPA_UT_DBG( + "rx_transfer_ring_db: %u\n", *rx_transfer_ring_db); + IPA_UT_DBG("tx_event_ring_db: %u\n", *tx_event_ring_db); + num_words = sizeof(struct rx_event_ring_ele)/4; + rx_event = (struct rx_event_ring_ele *) + test_wdi3_ctx->rx_event_ring_addr.base + + (*rx_event_ring_db/num_words - 1 + NUM_RX_ER_ELE) % + NUM_RX_ER_ELE; + IPA_UT_DBG("rx_event va: %pK\n", rx_event); + + IPA_UT_DBG("rx event low: %u rx event high: %u\n", + rx_event->buf_or_link_desc_addr_info.buffer_addr_low, + rx_event->buf_or_link_desc_addr_info.buffer_addr_high); + IPA_UT_DBG("rx buf low: %u rx buf high: %u\n", + rx_buf.buffer_addr_low, rx_buf.buffer_addr_high); + + if (rx_event->buf_or_link_desc_addr_info.buffer_addr_low != + rx_buf.buffer_addr_low || + rx_event->buf_or_link_desc_addr_info.buffer_addr_high != + rx_buf.buffer_addr_high) { + IPA_UT_ERR("rx event ring buf addr doesn't match.\n"); + return -EFAULT; + } + num_words = sizeof(struct tx_event_ring_ele)/4; + tx_event = (struct tx_event_ring_ele *) + test_wdi3_ctx->tx_event_ring_addr.base + + (*tx_event_ring_db/num_words - + NUM_MULTI_PKT + NUM_TX_ER_ELE) % + NUM_TX_ER_ELE; + IPA_UT_DBG("tx_event va: %pK\n", tx_event); + IPA_UT_DBG("recv addr low: %u recv_addr high: %u\n", + tx_event->buf_or_link_desc_addr_info.buffer_addr_low, + tx_event->buf_or_link_desc_addr_info.buffer_addr_high); + recv_packet_addr = ((u64) + tx_event->buf_or_link_desc_addr_info.buffer_addr_high + << 32) | (u64) + tx_event->buf_or_link_desc_addr_info.buffer_addr_low; + IPA_UT_DBG("high: %llu low: %llu all: %llu\n", (u64) + tx_event->buf_or_link_desc_addr_info.buffer_addr_high + << 32, (u64) + tx_event->buf_or_link_desc_addr_info.buffer_addr_low, + recv_packet_addr); + for (i = 0; i < NUM_TX_BUFS; i++) + if (recv_packet_addr == + test_wdi3_ctx->tx_bufs[i].phys_base) { + IPA_UT_INFO("found buf at position %d\n", i); + packet_recv = + (u32 *)test_wdi3_ctx->tx_bufs[i].base; + } + + if (*packet_recv != multi_pkt_array[0]) { + IPA_UT_ERR("recv packet doesn't match.\n"); + IPA_UT_ERR("packet: %d packet_recv: %d\n", + multi_pkt_array[0], *packet_recv); + return -EFAULT; + } + + IPA_UT_INFO("recv packet matches.\n"); + + /* recycle buffer */ + tx_uc_db = ioremap(test_wdi3_ctx->tx_uc_db_pa, + DB_REGISTER_SIZE); + num_words = sizeof(struct tx_transfer_ring_ele) / 4; + + for (i = 0; i < NUM_MULTI_PKT; i++) { + idx = tx_uc_db_local / num_words; + IPA_UT_DBG("tx_db_local: %u idx %d\n", + tx_uc_db_local, idx); + tx_event = (struct tx_event_ring_ele *) + test_wdi3_ctx->tx_event_ring_addr.base + + (*tx_event_ring_db/num_words - NUM_MULTI_PKT + + i + NUM_TX_ER_ELE) % NUM_TX_ER_ELE; + te = tx_event; + tx_transfer = (struct tx_transfer_ring_ele *) + test_wdi3_ctx->tx_transfer_ring_addr.base + idx; + tx_transfer->buf_or_link_desc_addr_info.buffer_addr_low + = te->buf_or_link_desc_addr_info.buffer_addr_low; + tx_transfer->buf_or_link_desc_addr_info.buffer_addr_high + = te->buf_or_link_desc_addr_info.buffer_addr_high; + ipa_test_wdi3_advance_uc_db(&tx_uc_db_local, 1, + sizeof(struct tx_transfer_ring_ele)/4, + test_wdi3_ctx->tx_transfer_ring_addr.size); + } + iowrite32(tx_uc_db_local, tx_uc_db); + tx_bf_idx = (tx_bf_idx + NUM_MULTI_PKT) % NUM_TX_BUFS; + return 0; + } + + /* populate packet content - For transfer through tx1*/ + num_words = sizeof(struct rx_transfer_ring_ele) / 4; + rx_uc_db = ioremap(test_wdi3_ctx->rx_uc_db_pa, DB_REGISTER_SIZE); + for (i = 0; i < NUM_MULTI_PKT; i++) { + idx = rx_uc_db_local / num_words; + packet = (u32 *)test_wdi3_ctx->rx_bufs[rx_bf_idx].base + + PACKET_HEADER_SIZE / 4; + *packet = multi_pkt_array[i]; + IPA_UT_DBG("rx_db_local: %u rx_bf_idx: %d\n", + rx_uc_db_local, rx_bf_idx); + rx_bf_idx = (rx_bf_idx + 1) % NUM_RX_BUFS; + /* update rx_transfer_ring_ele */ + rx_transfer = (struct rx_transfer_ring_ele *) + test_wdi3_ctx->rx_transfer_ring_addr.base + idx; + ipa_test_wdi3_advance_uc_db(&rx_uc_db_local, 1, + sizeof(struct rx_transfer_ring_ele)/4, + test_wdi3_ctx->rx_transfer_ring_addr.size); + rx_transfer->rx_msdu_desc_info_details.msdu_length = + ETH_PACKET_SIZE + PACKET_HEADER_SIZE; + rx_buf.buffer_addr_low = + rx_transfer->buf_or_link_desc_addr_info.buffer_addr_low; + rx_buf.buffer_addr_high = + rx_transfer->buf_or_link_desc_addr_info.buffer_addr_high; + } + + tx1_event_ring_db = (u32 *)test_wdi3_ctx->tx1_event_ring_db.base; + orig_tx1_event_ring_db = *tx1_event_ring_db; + IPA_UT_DBG("original tx1 event ring db: %u\n", orig_tx1_event_ring_db); + + rx_event_ring_db = (u32 *)test_wdi3_ctx->rx_event_ring_db.base; + orig_rx_event_ring_db = *rx_event_ring_db; + IPA_UT_DBG("original rx event ring db: %u\n", orig_rx_event_ring_db); + + rx_transfer_ring_db = (u32 *)test_wdi3_ctx->rx_transfer_ring_db.base; + IPA_UT_DBG("original rx transfer ring db: %u\n", *rx_transfer_ring_db); + + /* ring uc db */ + iowrite32(rx_uc_db_local, rx_uc_db); + IPA_UT_DBG("rx db local: %u\n", rx_uc_db_local); + + loop_cnt = 0; + while (orig_tx1_event_ring_db == *tx1_event_ring_db || + *rx_transfer_ring_db != rx_uc_db_local || + orig_rx_event_ring_db == *rx_event_ring_db) { + loop_cnt++; + IPA_UT_DBG("loop count: %d tx\n", loop_cnt); + IPA_UT_DBG("orig_tx1_event_ring_db: %u tx1_event_ring_db: %u\n", + orig_tx1_event_ring_db, *tx1_event_ring_db); + IPA_UT_DBG("rx_transfer_ring_db: %u rx db local: %u\n", + *rx_transfer_ring_db, rx_uc_db_local); + IPA_UT_DBG("orig_rx_event_ring_db: %u rx_event_ring_db %u\n", + orig_rx_event_ring_db, *rx_event_ring_db); + if (loop_cnt == 1000) { + IPA_UT_ERR("transfer timeout!\n"); + BUG(); + return -EFAULT; + } + usleep_range(1000, 1001); + } + + IPA_UT_DBG("rx_transfer_ring_db: %u\n", *rx_transfer_ring_db); + IPA_UT_DBG("tx1_event_ring_db: %u\n", *tx1_event_ring_db); + num_words = sizeof(struct rx_event_ring_ele)/4; + rx_event = (struct rx_event_ring_ele *) + test_wdi3_ctx->rx_event_ring_addr.base + + (*rx_event_ring_db/num_words - 1 + NUM_RX_ER_ELE) % + NUM_RX_ER_ELE; + IPA_UT_DBG("rx_event va: %pK\n", rx_event); + + IPA_UT_DBG("rx event low: %u rx event high: %u\n", + rx_event->buf_or_link_desc_addr_info.buffer_addr_low, + rx_event->buf_or_link_desc_addr_info.buffer_addr_high); + IPA_UT_DBG("rx buf low: %u rx buf high: %u\n", + rx_buf.buffer_addr_low, rx_buf.buffer_addr_high); + + if (rx_event->buf_or_link_desc_addr_info.buffer_addr_low != + rx_buf.buffer_addr_low || + rx_event->buf_or_link_desc_addr_info.buffer_addr_high != + rx_buf.buffer_addr_high) { + IPA_UT_ERR("rx event ring buf addr doesn't match.\n"); + return -EFAULT; + } + num_words = sizeof(struct tx_event_ring_ele)/4; + tx1_event = (struct tx_event_ring_ele *) + test_wdi3_ctx->tx1_event_ring_addr.base + + (*tx1_event_ring_db/num_words - NUM_MULTI_PKT + NUM_TX_ER_ELE) % + NUM_TX_ER_ELE; + IPA_UT_DBG("tx1_event va: %pK\n", tx1_event); + IPA_UT_DBG("recv addr low: %u recv_addr high: %u\n", + tx1_event->buf_or_link_desc_addr_info.buffer_addr_low, + tx1_event->buf_or_link_desc_addr_info.buffer_addr_high); + recv_packet_addr = + ((u64)tx1_event->buf_or_link_desc_addr_info.buffer_addr_high + << 32) | + (u64)tx1_event->buf_or_link_desc_addr_info.buffer_addr_low; + IPA_UT_DBG("high: %llu low: %llu all: %llu\n", + (u64)tx1_event->buf_or_link_desc_addr_info.buffer_addr_high + << 32, + (u64)tx1_event->buf_or_link_desc_addr_info.buffer_addr_low, + recv_packet_addr); + for (i = 0; i < NUM_TX_BUFS; i++) + if (recv_packet_addr == test_wdi3_ctx->tx1_bufs[i].phys_base) { + IPA_UT_INFO("found buf at position %d\n", i); + packet_recv = (u32 *)test_wdi3_ctx->tx1_bufs[i].base; + } + + if (*packet_recv != multi_pkt_array[0]) { + IPA_UT_ERR("recv packet doesn't match.\n"); + IPA_UT_ERR("packet: %d packet_recv: %d\n", + multi_pkt_array[0], *packet_recv); + return -EFAULT; + } + + IPA_UT_INFO("recv packet matches, sent on tx1.\n"); + + /* recycle buffer */ + tx1_uc_db = ioremap(test_wdi3_ctx->tx1_uc_db_pa, DB_REGISTER_SIZE); + num_words = sizeof(struct tx_transfer_ring_ele) / 4; + + for (i = 0; i < NUM_MULTI_PKT; i++) { + idx = tx1_uc_db_local / num_words; + IPA_UT_DBG("tx1_db_local: %u idx %d\n", tx1_uc_db_local, idx); + tx1_event = (struct tx_event_ring_ele *) + test_wdi3_ctx->tx1_event_ring_addr.base + + (*tx1_event_ring_db/num_words - NUM_MULTI_PKT + + i + NUM_TX_ER_ELE) % NUM_TX_ER_ELE; + tx1_transfer = (struct tx_transfer_ring_ele *) + test_wdi3_ctx->tx1_transfer_ring_addr.base + idx; + tx1_transfer->buf_or_link_desc_addr_info.buffer_addr_low = + tx1_event->buf_or_link_desc_addr_info.buffer_addr_low; + tx1_transfer->buf_or_link_desc_addr_info.buffer_addr_high = + tx1_event->buf_or_link_desc_addr_info.buffer_addr_high; + ipa_test_wdi3_advance_uc_db(&tx1_uc_db_local, 1, + sizeof(struct tx_transfer_ring_ele)/4, + test_wdi3_ctx->tx1_transfer_ring_addr.size); + } + iowrite32(tx1_uc_db_local, tx1_uc_db); + tx1_bf_idx = (tx1_bf_idx + NUM_MULTI_PKT) % NUM_TX_BUFS; + return 0; +} + +static int ipa_wdi3_test_multi_transfer(void *priv) +{ + struct ipa_ep_cfg ep_cfg = { {0} }; + bool is_tx1_used = false; + + if (ipa_wdi3_test_reg_intf(is_tx1_used)) { + IPA_UT_ERR("fail to register intf.\n"); + return -EFAULT; + } + + if (ipa_wdi3_setup_pipes()) { + IPA_UT_ERR("fail to setup wdi3 pipes.\n"); + return -EFAULT; + } + + /* configure WLAN RX EP in DMA mode */ + ep_cfg.mode.mode = IPA_DMA; + ep_cfg.mode.dst = IPA_CLIENT_WLAN2_CONS; + + ep_cfg.seq.set_dynamic = true; + + ipa3_cfg_ep(ipa_get_ep_mapping(IPA_CLIENT_WLAN2_PROD), &ep_cfg); + + if (ipa_wdi3_send_multi_packet()) { + IPA_UT_ERR("fail to transfer packet.\n"); + ipa_wdi3_teardown_pipes(); + return -EFAULT; + } + + if (ipa_wdi3_teardown_pipes()) { + IPA_UT_ERR("fail to tear down pipes.\n"); + return -EFAULT; + } + + IPA_UT_INFO("pipes were torn down!\n"); + + if (ipa_wdi3_test_dereg_intf(is_tx1_used)) { + IPA_UT_ERR("fail to deregister interface.\n"); + return -EFAULT; + } + + return 0; +} + +static int ipa_wdi3_test_multi_transfer2(void *priv) +{ + struct ipa_ep_cfg ep_cfg = { {0} }; + int i; + bool is_tx1_used = false; + + if (ipa_wdi3_test_reg_intf(is_tx1_used)) { + IPA_UT_ERR("fail to register intf.\n"); + return -EFAULT; + } + + if (ipa_wdi3_setup_pipes()) { + IPA_UT_ERR("fail to setup wdi3 pipes.\n"); + return -EFAULT; + } + + /* configure WLAN RX EP in DMA mode */ + ep_cfg.mode.mode = IPA_DMA; + ep_cfg.mode.dst = IPA_CLIENT_WLAN2_CONS; + + ep_cfg.seq.set_dynamic = true; + + ipa3_cfg_ep(ipa_get_ep_mapping(IPA_CLIENT_WLAN2_PROD), &ep_cfg); + + IPA_UT_DBG("-----start transfer 32 pkt----\n"); + for (i = 0; i < 32; i++) { + IPA_UT_DBG("--transferring num #%d pkt--\n", i + 1); + if (ipa_wdi3_send_one_packet()) { + IPA_UT_ERR("fail to transfer packet.\n"); + ipa_wdi3_teardown_pipes(); + return -EFAULT; + } + } + + if (ipa_wdi3_teardown_pipes()) { + IPA_UT_ERR("fail to tear down pipes.\n"); + return -EFAULT; + } + + IPA_UT_ERR("pipes were torn down!\n"); + + if (ipa_wdi3_test_dereg_intf(is_tx1_used)) { + IPA_UT_ERR("fail to deregister interface.\n"); + return -EFAULT; + } + + return 0; +} + +static int ipa_wdi3_test_multi_transfer3(void *priv) +{ + struct ipa_ep_cfg ep_cfg = { {0} }; + int i; + bool is_tx1_used = false; + + if (ipa_wdi3_test_reg_intf(is_tx1_used)) { + IPA_UT_ERR("fail to register intf.\n"); + return -EFAULT; + } + + if (ipa_wdi3_setup_pipes()) { + IPA_UT_ERR("fail to setup wdi3 pipes.\n"); + return -EFAULT; + } + + /* configure WLAN RX EP in DMA mode */ + ep_cfg.mode.mode = IPA_DMA; + ep_cfg.mode.dst = IPA_CLIENT_WLAN2_CONS; + + ep_cfg.seq.set_dynamic = true; + + ipa3_cfg_ep(ipa_get_ep_mapping(IPA_CLIENT_WLAN2_PROD), &ep_cfg); + + IPA_UT_DBG("-----start transfer 256 pkt----\n"); + for (i = 0; i < 32; i++) { + IPA_UT_DBG("--transferring num # %d to num # %d pkt--\n", + (i + 1) * 8, (i + 2) * 8 - 1); + if (ipa_wdi3_send_multi_packet()) { + IPA_UT_ERR("fail to transfer packet.\n"); + ipa_wdi3_teardown_pipes(); + return -EFAULT; + } + } + + if (ipa_wdi3_teardown_pipes()) { + IPA_UT_ERR("fail to tear down pipes.\n"); + return -EFAULT; + } + + IPA_UT_ERR("pipes were torn down!\n"); + + if (ipa_wdi3_test_dereg_intf(is_tx1_used)) { + IPA_UT_ERR("fail to deregister interface.\n"); + return -EFAULT; + } + + return 0; +} + +static int ipa_wdi3_test_multi_transfer_2g_5g(void *priv) +{ + struct ipa_ep_cfg ep_cfg = { {0} }; + bool is_tx1_used = false; + + if (ipa_wdi3_test_reg_intf(is_tx1_used)) { + IPA_UT_ERR("fail to register intf.\n"); + return -EFAULT; + } + + is_tx1_used = true; + if (ipa_wdi3_test_reg_intf(is_tx1_used)) { + IPA_UT_ERR("fail to register intf.\n"); + return -EFAULT; + } + + if (ipa_wdi3_setup_pipes_2g_5g()) { + IPA_UT_ERR("fail to setup wdi3 pipes.\n"); + return -EFAULT; + } + + /* configure WLAN RX EP in DMA mode */ + ep_cfg.mode.mode = IPA_DMA; + ep_cfg.mode.dst = IPA_CLIENT_WLAN2_CONS; + + ep_cfg.seq.set_dynamic = true; + + ipa3_cfg_ep(ipa_get_ep_mapping(IPA_CLIENT_WLAN2_PROD), &ep_cfg); + + if (ipa_wdi3_send_multi_packet_2g_5g(false)) { + IPA_UT_ERR("fail to transfer packet.\n"); + ipa_wdi3_teardown_pipes(); + return -EFAULT; + } + + /* configure WLAN RX EP in DMA mode for tx1*/ + ep_cfg.mode.mode = IPA_DMA; + ep_cfg.mode.dst = IPA_CLIENT_WLAN2_CONS1; + + ep_cfg.seq.set_dynamic = true; + + ipa3_cfg_ep(ipa_get_ep_mapping(IPA_CLIENT_WLAN2_PROD), &ep_cfg); + + if (ipa_wdi3_send_multi_packet_2g_5g(true)) { + IPA_UT_ERR("fail to transfer packet.\n"); + ipa_wdi3_teardown_pipes(); + return -EFAULT; + } + + if (ipa_wdi3_teardown_pipes()) { + IPA_UT_ERR("fail to tear down pipes.\n"); + return -EFAULT; + } + + IPA_UT_INFO("pipes were torn down!\n"); + + if (ipa_wdi3_test_dereg_intf(is_tx1_used)) { + IPA_UT_ERR("fail to deregister interface.\n"); + return -EFAULT; + } + + is_tx1_used = false; + if (ipa_wdi3_test_dereg_intf(is_tx1_used)) { + IPA_UT_ERR("fail to deregister interface.\n"); + return -EFAULT; + } + + return 0; +} + +static int ipa_wdi3_test_multi_transfer2_2g_5g(void *priv) +{ + struct ipa_ep_cfg ep_cfg = { {0} }; + int i; + bool is_tx1_used = false; + + if (ipa_wdi3_test_reg_intf(is_tx1_used)) { + IPA_UT_ERR("fail to register intf.\n"); + return -EFAULT; + } + + is_tx1_used = true; + if (ipa_wdi3_test_reg_intf(is_tx1_used)) { + IPA_UT_ERR("fail to register intf.\n"); + return -EFAULT; + } + + if (ipa_wdi3_setup_pipes_2g_5g()) { + IPA_UT_ERR("fail to setup wdi3 pipes.\n"); + return -EFAULT; + } + + /* configure WLAN RX EP in DMA mode */ + ep_cfg.mode.mode = IPA_DMA; + ep_cfg.mode.dst = IPA_CLIENT_WLAN2_CONS; + + ep_cfg.seq.set_dynamic = true; + + ipa3_cfg_ep(ipa_get_ep_mapping(IPA_CLIENT_WLAN2_PROD), &ep_cfg); + + IPA_UT_DBG("-----start transfer 32 pkt from tx----\n"); + for (i = 0; i < 32; i++) { + IPA_UT_DBG("--transferring num #%d pkt--\n", i + 1); + if (ipa_wdi3_send_one_packet_2g_5g(false)) { + IPA_UT_ERR("fail to transfer packet.\n"); + ipa_wdi3_teardown_pipes(); + return -EFAULT; + } + } + + /* configure WLAN RX EP in DMA mode for tx1*/ + ep_cfg.mode.mode = IPA_DMA; + ep_cfg.mode.dst = IPA_CLIENT_WLAN2_CONS1; + + ep_cfg.seq.set_dynamic = true; + + ipa3_cfg_ep(ipa_get_ep_mapping(IPA_CLIENT_WLAN2_PROD), &ep_cfg); + + IPA_UT_DBG("-----start transfer 32 pkt from tx1----\n"); + for (i = 0; i < 32; i++) { + IPA_UT_DBG("--transferring num #%d pkt--\n", i + 1); + if (ipa_wdi3_send_one_packet_2g_5g(true)) { + IPA_UT_ERR("fail to transfer packet.\n"); + ipa_wdi3_teardown_pipes(); + return -EFAULT; + } + } + + if (ipa_wdi3_teardown_pipes()) { + IPA_UT_ERR("fail to tear down pipes.\n"); + return -EFAULT; + } + + IPA_UT_ERR("2g 5g pipes were torn down!\n"); + + if (ipa_wdi3_test_dereg_intf(is_tx1_used)) { + IPA_UT_ERR("fail to deregister interface.\n"); + return -EFAULT; + } + + is_tx1_used = false; + if (ipa_wdi3_test_dereg_intf(is_tx1_used)) { + IPA_UT_ERR("fail to deregister interface.\n"); + return -EFAULT; + } + + return 0; +} + +static int ipa_wdi3_test_multi_transfer3_2g_5g(void *priv) +{ + struct ipa_ep_cfg ep_cfg = { {0} }; + int i; + bool is_tx1_used = false; + + if (ipa_wdi3_test_reg_intf(is_tx1_used)) { + IPA_UT_ERR("fail to register intf.\n"); + return -EFAULT; + } + + is_tx1_used = true; + if (ipa_wdi3_test_reg_intf(is_tx1_used)) { + IPA_UT_ERR("fail to register intf.\n"); + return -EFAULT; + } + + if (ipa_wdi3_setup_pipes_2g_5g()) { + IPA_UT_ERR("fail to setup wdi3 pipes.\n"); + return -EFAULT; + } + + /* configure WLAN RX EP in DMA mode */ + ep_cfg.mode.mode = IPA_DMA; + ep_cfg.mode.dst = IPA_CLIENT_WLAN2_CONS; + + ep_cfg.seq.set_dynamic = true; + + ipa3_cfg_ep(ipa_get_ep_mapping(IPA_CLIENT_WLAN2_PROD), &ep_cfg); + + IPA_UT_DBG("-----start transfer 256 pkt through tx----\n"); + for (i = 0; i < 32; i++) { + IPA_UT_DBG("--transferring num # %d to num # %d pkt--\n", + (i + 1) * 8, (i + 2) * 8 - 1); + if (ipa_wdi3_send_multi_packet_2g_5g(false)) { + IPA_UT_ERR("fail to transfer packet.\n"); + ipa_wdi3_teardown_pipes(); + return -EFAULT; + } + } + + /* configure WLAN RX EP in DMA mode for tx1*/ + ep_cfg.mode.mode = IPA_DMA; + ep_cfg.mode.dst = IPA_CLIENT_WLAN2_CONS1; + + ep_cfg.seq.set_dynamic = true; + + ipa3_cfg_ep(ipa_get_ep_mapping(IPA_CLIENT_WLAN2_PROD), &ep_cfg); + + IPA_UT_DBG("-----start transfer 256 pkt through tx1----\n"); + for (i = 0; i < 32; i++) { + IPA_UT_DBG("--transferring num # %d to num # %d pkt--\n", + (i + 1) * 8, (i + 2) * 8 - 1); + if (ipa_wdi3_send_multi_packet_2g_5g(true)) { + IPA_UT_ERR("fail to transfer packet.\n"); + ipa_wdi3_teardown_pipes(); + return -EFAULT; + } + } + + if (ipa_wdi3_teardown_pipes()) { + IPA_UT_ERR("fail to tear down pipes.\n"); + return -EFAULT; + } + + IPA_UT_ERR("2g 5g pipes were torn down!\n"); + + if (ipa_wdi3_test_dereg_intf(is_tx1_used)) { + IPA_UT_ERR("fail to deregister interface.\n"); + return -EFAULT; + } + + is_tx1_used = false; + if (ipa_wdi3_test_dereg_intf(is_tx1_used)) { + IPA_UT_ERR("fail to deregister interface.\n"); + return -EFAULT; + } + + return 0; +} + +/* Suite definition block */ +IPA_UT_DEFINE_SUITE_START(wdi3, "WDI3 tests", + ipa_test_wdi3_suite_setup, ipa_test_wdi3_suite_teardown) +{ + IPA_UT_ADD_TEST(single_transfer, + "single data transfer", + ipa_wdi3_test_single_transfer, + true, IPA_HW_v3_0, IPA_HW_MAX), + + IPA_UT_ADD_TEST(multi_transfer, + "multiple data transfer", + ipa_wdi3_test_multi_transfer, + true, IPA_HW_v3_0, IPA_HW_MAX), + + IPA_UT_ADD_TEST(multi_transfer2, + "multiple data transfer with data wrap around", + ipa_wdi3_test_multi_transfer2, + true, IPA_HW_v3_0, IPA_HW_MAX), + + IPA_UT_ADD_TEST(multi_transfer3, + "multiple data transfer with data wrap around2", + ipa_wdi3_test_multi_transfer3, + true, IPA_HW_v3_0, IPA_HW_MAX), + + IPA_UT_ADD_TEST(single_transfer_2g_5g, + "single data transfer 2g 5g", + ipa_wdi3_test_single_transfer_2g_5g, + true, IPA_HW_v4_5, IPA_HW_MAX), + + IPA_UT_ADD_TEST(multi_transfer_2g_5g, + "multiple data transfer 2g 5g", + ipa_wdi3_test_multi_transfer_2g_5g, + true, IPA_HW_v4_5, IPA_HW_MAX), + + IPA_UT_ADD_TEST(multi_transfer2_2g_5g, + "multiple data transfer 2g5g with data wrap around", + ipa_wdi3_test_multi_transfer2_2g_5g, + true, IPA_HW_v4_5, IPA_HW_MAX), + + IPA_UT_ADD_TEST(multi_transfer3_2g_5g, + "multiple data transfer 2g5g with data wrap around2", + ipa_wdi3_test_multi_transfer3_2g_5g, + true, IPA_HW_v4_5, IPA_HW_MAX) +} IPA_UT_DEFINE_SUITE_END(wdi3); + + diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/test/ipa_ut_framework.c b/qcom/opensource/dataipa/drivers/platform/msm/ipa/test/ipa_ut_framework.c new file mode 100644 index 0000000000..0a35c5b397 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/test/ipa_ut_framework.c @@ -0,0 +1,1111 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include "ipa.h" +#include "ipa_i.h" +#include "ipa_ut_framework.h" +#include "ipa_ut_suite_list.h" +#include "ipa_ut_i.h" + + +#define IPA_UT_DEBUG_WRITE_BUF_SIZE 256 +#define IPA_UT_DEBUG_READ_BUF_SIZE 1024 + +#define IPA_UT_READ_WRITE_DBG_FILE_MODE 0664 + +/** + * struct ipa_ut_context - I/S context + * @inited: Will wait till IPA is ready. Will create the enable file + * @enabled: All tests and suite debugfs files are created + * @lock: Lock for mutual exclustion + * @ipa_dbgfs_root: IPA root debugfs folder + * @test_dbgfs_root: UT root debugfs folder. Sub-folder of IPA root + * @test_dbgfs_suites: Suites root debugfs folder. Sub-folder of UT root + * @wq: workqueue struct for write operations + */ +struct ipa_ut_context { + bool inited; + bool enabled; + struct mutex lock; + struct dentry *ipa_dbgfs_root; + struct dentry *test_dbgfs_root; + struct dentry *test_dbgfs_suites; + struct workqueue_struct *wq; +}; + +/** + * struct ipa_ut_dbgfs_test_write_work_ctx - work_queue context + * @dbgfs_Work: work_struct for the write_work + * @meta_type: See enum ipa_ut_meta_test_type + * @user_data: user data usually used to point to suite or test object + */ +struct ipa_ut_dbgfs_test_write_work_ctx { + struct work_struct dbgfs_work; + long meta_type; + void *user_data; +}; + +static ssize_t ipa_ut_dbgfs_enable_read(struct file *file, + char __user *ubuf, size_t count, loff_t *ppos); +static ssize_t ipa_ut_dbgfs_enable_write(struct file *file, + const char __user *buf, size_t count, loff_t *ppos); +static ssize_t ipa_ut_dbgfs_test_read(struct file *file, + char __user *ubuf, size_t count, loff_t *ppos); +static ssize_t ipa_ut_dbgfs_test_write(struct file *file, + const char __user *buf, size_t count, loff_t *ppos); +static int ipa_ut_dbgfs_all_test_open(struct inode *inode, + struct file *filp); +static int ipa_ut_dbgfs_regression_test_open(struct inode *inode, + struct file *filp); +static ssize_t ipa_ut_dbgfs_meta_test_read(struct file *file, + char __user *ubuf, size_t count, loff_t *ppos); +static ssize_t ipa_ut_dbgfs_meta_test_write(struct file *file, + const char __user *buf, size_t count, loff_t *ppos); + + +static const struct file_operations ipa_ut_dbgfs_enable_fops = { + .read = ipa_ut_dbgfs_enable_read, + .write = ipa_ut_dbgfs_enable_write, +}; +static const struct file_operations ipa_ut_dbgfs_test_fops = { + .read = ipa_ut_dbgfs_test_read, + .write = ipa_ut_dbgfs_test_write, +}; +static const struct file_operations ipa_ut_dbgfs_all_test_fops = { + .open = ipa_ut_dbgfs_all_test_open, + .read = ipa_ut_dbgfs_meta_test_read, + .write = ipa_ut_dbgfs_meta_test_write, +}; +static const struct file_operations ipa_ut_dbgfs_regression_test_fops = { + .open = ipa_ut_dbgfs_regression_test_open, + .read = ipa_ut_dbgfs_meta_test_read, + .write = ipa_ut_dbgfs_meta_test_write, +}; + +static struct ipa_ut_context *ipa_ut_ctx; +char *_IPA_UT_TEST_LOG_BUF_NAME; +struct ipa_ut_tst_fail_report + _IPA_UT_TEST_FAIL_REPORT_DATA[_IPA_UT_TEST_FAIL_REPORT_SIZE]; +u32 _IPA_UT_TEST_FAIL_REPORT_IDX; + +/** + * ipa_ut_print_log_buf() - Dump given buffer via kernel error mechanism + * @buf: Buffer to print + * + * Tokenize the string according to new-line and then print + * + * Note: Assumes lock acquired + */ +static void ipa_ut_print_log_buf(char *buf) +{ + char *token; + + if (!buf) { + IPA_UT_ERR("Input error - no buf\n"); + return; + } + + for (token = strsep(&buf, "\n"); token; token = strsep(&buf, "\n")) + pr_err("%s\n", token); +} + +/** + * ipa_ut_dump_fail_report_stack() - dump the report info stack via kernel err + * + * Note: Assumes lock acquired + */ +static void ipa_ut_dump_fail_report_stack(void) +{ + int i; + + IPA_UT_DBG("Entry\n"); + + if (_IPA_UT_TEST_FAIL_REPORT_IDX == 0) { + IPA_UT_DBG("no report info\n"); + return; + } + + for (i = 0 ; i < _IPA_UT_TEST_FAIL_REPORT_IDX; i++) { + if (i == 0) + pr_err("***** FAIL INFO STACK *****:\n"); + else + pr_err("Called From:\n"); + + pr_err("\tFILE = %s\n\tFUNC = %s()\n\tLINE = %d\n", + _IPA_UT_TEST_FAIL_REPORT_DATA[i].file, + _IPA_UT_TEST_FAIL_REPORT_DATA[i].func, + _IPA_UT_TEST_FAIL_REPORT_DATA[i].line); + pr_err("\t%s\n", _IPA_UT_TEST_FAIL_REPORT_DATA[i].info); + } +} + +/** + * ipa_ut_show_suite_exec_summary() - Show tests run summary + * @suite: suite to print its running summary + * + * Print list of succeeded tests, failed tests and skipped tests + * + * Note: Assumes lock acquired + */ +static void ipa_ut_show_suite_exec_summary(const struct ipa_ut_suite *suite) +{ + int i; + + IPA_UT_DBG("Entry\n"); + + ipa_assert_on(!suite); + + pr_info("\n\n"); + pr_info("\t Suite '%s' summary\n", suite->meta_data->name); + pr_info("===========================\n"); + pr_info("Successful tests\n"); + pr_info("----------------\n"); + for (i = 0 ; i < suite->tests_cnt ; i++) { + if (suite->tests[i].res != IPA_UT_TEST_RES_SUCCESS) + continue; + pr_info("\t%s\n", suite->tests[i].name); + } + pr_info("\nFailed tests\n"); + pr_info("------------\n"); + for (i = 0 ; i < suite->tests_cnt ; i++) { + if (suite->tests[i].res != IPA_UT_TEST_RES_FAIL) + continue; + pr_info("\t%s\n", suite->tests[i].name); + } + pr_info("\nSkipped tests\n"); + pr_info("-------------\n"); + for (i = 0 ; i < suite->tests_cnt ; i++) { + if (suite->tests[i].res != IPA_UT_TEST_RES_SKIP) + continue; + pr_info("\t%s\n", suite->tests[i].name); + } + pr_info("\n"); +} + +/** + * ipa_ut_dbgfs_meta_test_write_work_func() - Debugfs write func for a + * for a meta test + * @params: work struct containing write fops and completion object + * + * Used to run all/regression tests in a suite + * Create log buffer that the test can use to store ongoing logs + * IPA clocks need to be voted. + * Run setup() once before running the tests and teardown() once after + * If no such call-backs then ignore it; if failed then fail the suite + * Print tests progress during running + * Test log and fail report will be showed only if the test failed. + * Finally show Summary of the suite tests running + * + * Note: If test supported IPA H/W version mismatch, skip it + * If a test lack run function, skip it + * If test doesn't belong to regression and it is regression run, skip it + * Note: Running mode: Do not stop running on failure + * + * Return: Negative in failure, given characters amount in success + */ +static void ipa_ut_dbgfs_meta_test_write_work_func(struct work_struct *work) +{ + struct ipa_ut_dbgfs_test_write_work_ctx *write_work_ctx; + struct ipa_ut_suite *suite; + int i; + enum ipa_hw_type ipa_ver; + int rc = 0; + long meta_type; + bool tst_fail = false; + + write_work_ctx = container_of(work, struct + ipa_ut_dbgfs_test_write_work_ctx, dbgfs_work); + + IPA_UT_DBG("Entry\n"); + + mutex_lock(&ipa_ut_ctx->lock); + suite = (struct ipa_ut_suite *)(write_work_ctx->user_data); + ipa_assert_on(!suite); + meta_type = write_work_ctx->meta_type; + IPA_UT_DBG("Meta test type %ld\n", meta_type); + + _IPA_UT_TEST_LOG_BUF_NAME = kzalloc(_IPA_UT_TEST_LOG_BUF_SIZE, + GFP_KERNEL); + if (!_IPA_UT_TEST_LOG_BUF_NAME) { + IPA_UT_ERR("failed to allocate %d bytes\n", + _IPA_UT_TEST_LOG_BUF_SIZE); + rc = -ENOMEM; + goto unlock_mutex; + } + + if (!suite->tests_cnt || !suite->tests) { + pr_info("No tests for suite '%s'\n", suite->meta_data->name); + goto free_mem; + } + + ipa_ver = ipa_get_hw_type(); + + IPA_ACTIVE_CLIENTS_INC_SPECIAL("IPA_UT"); + + if (suite->meta_data->setup) { + pr_info("*** Suite '%s': Run setup ***\n", + suite->meta_data->name); + rc = suite->meta_data->setup(&suite->meta_data->priv); + if (rc) { + IPA_UT_ERR("Setup failed for suite %s\n", + suite->meta_data->name); + rc = -EFAULT; + goto release_clock; + } + } else { + pr_info("*** Suite '%s': No Setup ***\n", + suite->meta_data->name); + } + + pr_info("*** Suite '%s': Run %s tests ***\n\n", + suite->meta_data->name, + meta_type == IPA_UT_META_TEST_REGRESSION ? "regression" : "all" + ); + for (i = 0 ; i < suite->tests_cnt ; i++) { + if (meta_type == IPA_UT_META_TEST_REGRESSION && + !suite->tests[i].run_in_regression) { + pr_info( + "*** Test '%s': Skip - Not in regression ***\n\n" + , suite->tests[i].name); + suite->tests[i].res = IPA_UT_TEST_RES_SKIP; + continue; + } + if (suite->tests[i].min_ipa_hw_ver > ipa_ver || + suite->tests[i].max_ipa_hw_ver < ipa_ver) { + pr_info( + "*** Test '%s': Skip - IPA VER mismatch ***\n\n" + , suite->tests[i].name); + suite->tests[i].res = IPA_UT_TEST_RES_SKIP; + continue; + } + if (!suite->tests[i].run) { + pr_info( + "*** Test '%s': Skip - No Run function ***\n\n" + , suite->tests[i].name); + suite->tests[i].res = IPA_UT_TEST_RES_SKIP; + continue; + } + + _IPA_UT_TEST_LOG_BUF_NAME[0] = '\0'; + _IPA_UT_TEST_FAIL_REPORT_IDX = 0; + pr_info("*** Test '%s': Running... ***\n", + suite->tests[i].name); + rc = suite->tests[i].run(suite->meta_data->priv); + if (rc) { + tst_fail = true; + suite->tests[i].res = IPA_UT_TEST_RES_FAIL; + ipa_ut_print_log_buf(_IPA_UT_TEST_LOG_BUF_NAME); + } else { + suite->tests[i].res = IPA_UT_TEST_RES_SUCCESS; + } + + pr_info(">>>>>>**** TEST '%s': %s ****<<<<<<\n", + suite->tests[i].name, tst_fail ? "FAIL" : "SUCCESS"); + + if (tst_fail) + ipa_ut_dump_fail_report_stack(); + + pr_info("\n"); + } + + if (suite->meta_data->teardown) { + pr_info("*** Suite '%s': Run Teardown ***\n", + suite->meta_data->name); + rc = suite->meta_data->teardown(suite->meta_data->priv); + if (rc) { + IPA_UT_ERR("Teardown failed for suite %s\n", + suite->meta_data->name); + rc = -EFAULT; + goto release_clock; + } + } else { + pr_info("*** Suite '%s': No Teardown ***\n", + suite->meta_data->name); + } + + ipa_ut_show_suite_exec_summary(suite); + +release_clock: + IPA_ACTIVE_CLIENTS_DEC_SPECIAL("IPA_UT"); +free_mem: + kfree(_IPA_UT_TEST_LOG_BUF_NAME); + _IPA_UT_TEST_LOG_BUF_NAME = NULL; +unlock_mutex: + mutex_unlock(&ipa_ut_ctx->lock); + kfree(write_work_ctx); +} + +/* + * ipa_ut_dbgfs_meta_test_write() - Debugfs write func for a meta test + * @params: write fops + * + * Run all tests in a suite using a work queue so it does not race with + * debugfs_remove_recursive + * + * Return: Negative if failure. Amount of characters written if success. + */ +static ssize_t ipa_ut_dbgfs_meta_test_write(struct file *file, + const char __user *buf, size_t count, loff_t *ppos) +{ + struct ipa_ut_dbgfs_test_write_work_ctx *write_work_ctx; + + write_work_ctx = kzalloc(sizeof(*write_work_ctx), GFP_KERNEL); + if (!write_work_ctx) { + IPA_UT_ERR("kzalloc err.\n"); + return -ENOMEM; + } + + write_work_ctx->user_data = file->f_inode->i_private; + write_work_ctx->meta_type = (long)(file->private_data); + + INIT_WORK(&write_work_ctx->dbgfs_work, + ipa_ut_dbgfs_meta_test_write_work_func); + + queue_work(ipa_ut_ctx->wq, &write_work_ctx->dbgfs_work); + + return count; +} + +/** + * ipa_ut_dbgfs_meta_test_read() - Debugfs read func for a meta test + * @params: read fops + * + * Meta test, is a test that describes other test or bunch of tests. + * for example, the 'all' test. Running this test will run all + * the tests in the suite. + * + * Show information regard the suite. E.g. name and description + * If regression - List the regression tests names + * + * Return: Amount of characters written to user space buffer + */ +static ssize_t ipa_ut_dbgfs_meta_test_read(struct file *file, + char __user *ubuf, size_t count, loff_t *ppos) +{ + char *buf; + struct ipa_ut_suite *suite; + int nbytes; + ssize_t cnt; + long meta_type; + int i; + + IPA_UT_DBG("Entry\n"); + + mutex_lock(&ipa_ut_ctx->lock); + suite = file->f_inode->i_private; + ipa_assert_on(!suite); + meta_type = (long)(file->private_data); + IPA_UT_DBG("Meta test type %ld\n", meta_type); + + buf = kmalloc(IPA_UT_DEBUG_READ_BUF_SIZE + 1, GFP_KERNEL); + if (!buf) { + IPA_UT_ERR("failed to allocate %d bytes\n", + IPA_UT_DEBUG_READ_BUF_SIZE + 1); + cnt = 0; + goto unlock_mutex; + } + + if (meta_type == IPA_UT_META_TEST_ALL) { + nbytes = scnprintf(buf, IPA_UT_DEBUG_READ_BUF_SIZE, + "\tMeta-test running all the tests in the suite:\n" + "\tSuite Name: %s\n" + "\tDescription: %s\n" + "\tNumber of test in suite: %zu\n", + suite->meta_data->name, + suite->meta_data->desc ?: "", + suite->tests_cnt); + } else { + nbytes = scnprintf(buf, IPA_UT_DEBUG_READ_BUF_SIZE, + "\tMeta-test running regression tests in the suite:\n" + "\tSuite Name: %s\n" + "\tDescription: %s\n" + "\tRegression tests:\n", + suite->meta_data->name, + suite->meta_data->desc ?: ""); + for (i = 0 ; i < suite->tests_cnt ; i++) { + if (!suite->tests[i].run_in_regression) + continue; + nbytes += scnprintf(buf + nbytes, + IPA_UT_DEBUG_READ_BUF_SIZE - nbytes, + "\t\t%s\n", suite->tests[i].name); + } + } + + cnt = simple_read_from_buffer(ubuf, count, ppos, buf, nbytes); + kfree(buf); + +unlock_mutex: + mutex_unlock(&ipa_ut_ctx->lock); + return cnt; +} + +/** + * ipa_ut_dbgfs_regression_test_open() - Debugfs open function for + * 'regression' tests + * @params: open fops + * + * Mark "Regression tests" for meta-tests later operations. + * + * Return: Zero (always success). + */ +static int ipa_ut_dbgfs_regression_test_open(struct inode *inode, + struct file *filp) +{ + IPA_UT_DBG("Entry\n"); + + filp->private_data = (void *)(IPA_UT_META_TEST_REGRESSION); + + return 0; +} + +/** + * ipa_ut_dbgfs_all_test_open() - Debugfs open function for 'all' tests + * @params: open fops + * + * Mark "All tests" for meta-tests later operations. + * + * Return: Zero (always success). + */ +static int ipa_ut_dbgfs_all_test_open(struct inode *inode, + struct file *filp) +{ + IPA_UT_DBG("Entry\n"); + + filp->private_data = (void *)(IPA_UT_META_TEST_ALL); + + return 0; +} + +/** + * ipa_ut_dbgfs_test_write() - Debugfs write function for a test + * @params: write fops + * + * Used to run a test. + * Create log buffer that the test can use to store ongoing logs + * IPA clocks need to be voted. + * Run setup() before the test and teardown() after the tests. + * If no such call-backs then ignore it; if failed then fail the test + * If all succeeds, no printing to user + * If failed, test logs and failure report will be printed to user + * + * Note: Test must has run function and it's supported IPA H/W version + * must be matching. Otherwise test will fail. + * + * Return: Negative in failure, given characters amount in success + */ +static void ipa_ut_dbgfs_test_write_work_func(struct work_struct *work) +{ + struct ipa_ut_dbgfs_test_write_work_ctx *write_work_ctx; + struct ipa_ut_test *test; + struct ipa_ut_suite *suite; + bool tst_fail = false; + int rc = 0; + enum ipa_hw_type ipa_ver; + + write_work_ctx = container_of(work, struct + ipa_ut_dbgfs_test_write_work_ctx, dbgfs_work); + + IPA_UT_DBG("Entry\n"); + + mutex_lock(&ipa_ut_ctx->lock); + test = (struct ipa_ut_test *)(write_work_ctx->user_data); + ipa_assert_on(!test); + + _IPA_UT_TEST_LOG_BUF_NAME = kzalloc(_IPA_UT_TEST_LOG_BUF_SIZE, + GFP_KERNEL); + if (!_IPA_UT_TEST_LOG_BUF_NAME) { + IPA_UT_ERR("failed to allocate %d bytes\n", + _IPA_UT_TEST_LOG_BUF_SIZE); + rc = -ENOMEM; + goto unlock_mutex; + } + + if (!test->run) { + IPA_UT_ERR("*** Test %s - No run func ***\n", + test->name); + rc = -EFAULT; + goto free_mem; + } + + ipa_ver = ipa_get_hw_type(); + if (test->min_ipa_hw_ver > ipa_ver || + test->max_ipa_hw_ver < ipa_ver) { + IPA_UT_ERR("Cannot run test %s on IPA HW Ver %s\n", + test->name, ipa_get_version_string(ipa_ver)); + rc = -EFAULT; + goto free_mem; + } + + suite = test->suite; + if (!suite || !suite->meta_data) { + IPA_UT_ERR("test %s with invalid suite\n", test->name); + rc = -EINVAL; + goto free_mem; + } + + IPA_ACTIVE_CLIENTS_INC_SPECIAL("IPA_UT"); + + if (suite->meta_data->setup) { + IPA_UT_DBG("*** Suite '%s': Run setup ***\n", + suite->meta_data->name); + rc = suite->meta_data->setup(&suite->meta_data->priv); + if (rc) { + IPA_UT_ERR("Setup failed for suite %s\n", + suite->meta_data->name); + rc = -EFAULT; + goto release_clock; + } + } else { + IPA_UT_DBG("*** Suite '%s': No Setup ***\n", + suite->meta_data->name); + } + + IPA_UT_DBG("*** Test '%s': Running... ***\n", test->name); + _IPA_UT_TEST_FAIL_REPORT_IDX = 0; + rc = test->run(suite->meta_data->priv); + if (rc) + tst_fail = true; + IPA_UT_DBG("*** Test %s - ***\n", tst_fail ? "FAIL" : "SUCCESS"); + if (tst_fail) { + pr_info("=================>>>>>>>>>>>\n"); + ipa_ut_print_log_buf(_IPA_UT_TEST_LOG_BUF_NAME); + pr_info("**** TEST %s FAILED ****\n", test->name); + ipa_ut_dump_fail_report_stack(); + pr_info("<<<<<<<<<<<=================\n"); + } + + if (suite->meta_data->teardown) { + IPA_UT_DBG("*** Suite '%s': Run Teardown ***\n", + suite->meta_data->name); + rc = suite->meta_data->teardown(suite->meta_data->priv); + if (rc) { + IPA_UT_ERR("Teardown failed for suite %s\n", + suite->meta_data->name); + rc = -EFAULT; + goto release_clock; + } + } else { + IPA_UT_DBG("*** Suite '%s': No Teardown ***\n", + suite->meta_data->name); + } + +release_clock: + IPA_ACTIVE_CLIENTS_DEC_SPECIAL("IPA_UT"); +free_mem: + kfree(_IPA_UT_TEST_LOG_BUF_NAME); + _IPA_UT_TEST_LOG_BUF_NAME = NULL; +unlock_mutex: + mutex_unlock(&ipa_ut_ctx->lock); + kfree(write_work_ctx); +} + +static ssize_t ipa_ut_dbgfs_test_write(struct file *file, + const char __user *buf, size_t count, loff_t *ppos) +{ + struct ipa_ut_dbgfs_test_write_work_ctx *write_work_ctx; + + write_work_ctx = kzalloc(sizeof(*write_work_ctx), GFP_KERNEL); + if (!write_work_ctx) { + IPA_UT_ERR("kzalloc err.\n"); + return -ENOMEM; + } + + write_work_ctx->user_data = file->f_inode->i_private; + write_work_ctx->meta_type = (long)(file->private_data); + + INIT_WORK(&write_work_ctx->dbgfs_work, + ipa_ut_dbgfs_test_write_work_func); + + queue_work(ipa_ut_ctx->wq, &write_work_ctx->dbgfs_work); + + return count; +} +/** + * ipa_ut_dbgfs_test_read() - Debugfs read function for a test + * @params: read fops + * + * print information regard the test. E.g. name and description + * + * Return: Amount of characters written to user space buffer + */ +static ssize_t ipa_ut_dbgfs_test_read(struct file *file, char __user *ubuf, + size_t count, loff_t *ppos) +{ + char *buf; + struct ipa_ut_test *test; + int nbytes; + ssize_t cnt; + + IPA_UT_DBG("Entry\n"); + + mutex_lock(&ipa_ut_ctx->lock); + test = file->f_inode->i_private; + ipa_assert_on(!test); + + buf = kmalloc(IPA_UT_DEBUG_READ_BUF_SIZE, GFP_KERNEL); + if (!buf) { + IPA_UT_ERR("failed to allocate %d bytes\n", + IPA_UT_DEBUG_READ_BUF_SIZE); + cnt = 0; + goto unlock_mutex; + } + + nbytes = scnprintf(buf, IPA_UT_DEBUG_READ_BUF_SIZE, + "\t Test Name: %s\n" + "\t Description: %s\n" + "\t Suite Name: %s\n" + "\t Run In Regression: %s\n" + "\t Supported IPA versions: [%s -> %s]\n", + test->name, test->desc ?: "", test->suite->meta_data->name, + test->run_in_regression ? "Yes" : "No", + ipa_get_version_string(test->min_ipa_hw_ver), + test->max_ipa_hw_ver == IPA_HW_MAX ? "MAX" : + ipa_get_version_string(test->max_ipa_hw_ver)); + + if (nbytes > count) + IPA_UT_ERR("User buf too small - return partial info\n"); + + cnt = simple_read_from_buffer(ubuf, count, ppos, buf, nbytes); + kfree(buf); + +unlock_mutex: + mutex_unlock(&ipa_ut_ctx->lock); + return cnt; +} + +/** + * ipa_ut_framework_load_suites() - Load tests and expose them to user space + * + * Creates debugfs folder for each suite and then file for each test in it. + * Create debugfs "all" file for each suite for meta-test to run all tests. + * + * Note: Assumes lock acquired + * + * Return: Zero in success, otherwise in failure + */ +static int ipa_ut_framework_load_suites(void) +{ + int suite_idx; + int tst_idx; + struct ipa_ut_suite *suite; + struct dentry *s_dent; + struct dentry *f_dent; + + IPA_UT_DBG("Entry\n"); + + for (suite_idx = IPA_UT_SUITE_FIRST_INDEX; + suite_idx < IPA_UT_SUITES_COUNT; suite_idx++) { + suite = IPA_UT_GET_SUITE(suite_idx); + + if (!suite->meta_data->name) { + IPA_UT_ERR("No suite name\n"); + return -EFAULT; + } + + s_dent = debugfs_create_dir(suite->meta_data->name, + ipa_ut_ctx->test_dbgfs_suites); + + if (!s_dent || IS_ERR(s_dent)) { + IPA_UT_ERR("fail create dbg entry - suite %s\n", + suite->meta_data->name); + return -EFAULT; + } + + for (tst_idx = 0; tst_idx < suite->tests_cnt ; tst_idx++) { + if (!suite->tests[tst_idx].name) { + IPA_UT_ERR("No test name on suite %s\n", + suite->meta_data->name); + return -EFAULT; + } + f_dent = debugfs_create_file( + suite->tests[tst_idx].name, + IPA_UT_READ_WRITE_DBG_FILE_MODE, s_dent, + &suite->tests[tst_idx], + &ipa_ut_dbgfs_test_fops); + if (!f_dent || IS_ERR(f_dent)) { + IPA_UT_ERR("fail create dbg entry - tst %s\n", + suite->tests[tst_idx].name); + return -EFAULT; + } + } + + /* entry for meta-test all to run all tests in suites */ + f_dent = debugfs_create_file(_IPA_UT_RUN_ALL_TEST_NAME, + IPA_UT_READ_WRITE_DBG_FILE_MODE, s_dent, + suite, &ipa_ut_dbgfs_all_test_fops); + if (!f_dent || IS_ERR(f_dent)) { + IPA_UT_ERR("fail to create dbg entry - %s\n", + _IPA_UT_RUN_ALL_TEST_NAME); + return -EFAULT; + } + + /* + * entry for meta-test regression to run all regression + * tests in suites + */ + f_dent = debugfs_create_file(_IPA_UT_RUN_REGRESSION_TEST_NAME, + IPA_UT_READ_WRITE_DBG_FILE_MODE, s_dent, + suite, &ipa_ut_dbgfs_regression_test_fops); + if (!f_dent || IS_ERR(f_dent)) { + IPA_UT_ERR("fail to create dbg entry - %s\n", + _IPA_UT_RUN_ALL_TEST_NAME); + return -EFAULT; + } + } + + return 0; +} + +/** + * ipa_ut_framework_enable() - Enable the framework + * + * Creates the tests and suites debugfs entries and load them. + * This will expose the tests to user space. + * + * Return: Zero in success, otherwise in failure + */ +static int ipa_ut_framework_enable(void) +{ + int ret = 0; + + IPA_UT_DBG("Entry\n"); + + mutex_lock(&ipa_ut_ctx->lock); + + if (ipa_ut_ctx->enabled) { + IPA_UT_ERR("Already enabled\n"); + goto unlock_mutex; + } + + ipa_ut_ctx->test_dbgfs_suites = debugfs_create_dir("suites", + ipa_ut_ctx->test_dbgfs_root); + if (!ipa_ut_ctx->test_dbgfs_suites || + IS_ERR(ipa_ut_ctx->test_dbgfs_suites)) { + IPA_UT_ERR("failed to create suites debugfs dir\n"); + ret = -EFAULT; + goto unlock_mutex; + } + + if (ipa_ut_framework_load_suites()) { + IPA_UT_ERR("failed to load the suites into debugfs\n"); + ret = -EFAULT; + goto fail_clean_suites_dbgfs; + } + + ipa_ut_ctx->enabled = true; + goto unlock_mutex; + +fail_clean_suites_dbgfs: + debugfs_remove_recursive(ipa_ut_ctx->test_dbgfs_suites); +unlock_mutex: + mutex_unlock(&ipa_ut_ctx->lock); + return ret; +} + +/** + * ipa_ut_framework_disable() - Disable the framework + * + * Remove the tests and suites debugfs exposure. + * + * Return: Zero in success, otherwise in failure + */ +static int ipa_ut_framework_disable(void) +{ + IPA_UT_DBG("Entry\n"); + + mutex_lock(&ipa_ut_ctx->lock); + + if (!ipa_ut_ctx->enabled) { + IPA_UT_ERR("Already disabled\n"); + goto unlock_mutex; + } + + debugfs_remove_recursive(ipa_ut_ctx->test_dbgfs_suites); + + ipa_ut_ctx->enabled = false; + +unlock_mutex: + mutex_unlock(&ipa_ut_ctx->lock); + return 0; +} + +/** + * ipa_ut_dbgfs_enable_write() - Debugfs enable file write fops + * @params: write fops + * + * Input should be number. If 0, then disable. Otherwise enable. + * + * Return: if failed then negative value, if succeeds, amount of given chars + */ +static ssize_t ipa_ut_dbgfs_enable_write(struct file *file, + const char __user *buf, size_t count, loff_t *ppos) +{ + char lcl_buf[IPA_UT_DEBUG_WRITE_BUF_SIZE]; + s8 option = 0; + int ret; + + IPA_UT_DBG("Entry\n"); + + if (count >= sizeof(lcl_buf)) { + IPA_UT_ERR("No enough space\n"); + return -E2BIG; + } + + if (copy_from_user(lcl_buf, buf, count)) { + IPA_UT_ERR("fail to copy buf from user space\n"); + return -EFAULT; + } + + lcl_buf[count] = '\0'; + if (kstrtos8(lcl_buf, 0, &option)) { + IPA_UT_ERR("fail convert str to s8\n"); + return -EINVAL; + } + + if (option == 0) + ret = ipa_ut_framework_disable(); + else + ret = ipa_ut_framework_enable(); + + return ret ?: count; +} + +/** + * ipa_ut_dbgfs_enable_read() - Debugfs enable file read fops + * @params: read fops + * + * To show to user space if the I/S is enabled or disabled. + * + * Return: amount of characters returned to user space + */ +static ssize_t ipa_ut_dbgfs_enable_read(struct file *file, char __user *ubuf, + size_t count, loff_t *ppos) +{ + const char *status; + + IPA_UT_DBG("Entry\n"); + + mutex_lock(&ipa_ut_ctx->lock); + status = ipa_ut_ctx->enabled ? + "Enabled - Write 0 to disable\n" : + "Disabled - Write 1 to enable\n"; + mutex_unlock(&ipa_ut_ctx->lock); + return simple_read_from_buffer(ubuf, count, ppos, + status, strlen(status)); +} + +/** + * ipa_ut_framework_init() - Unit-tests framework initialization + * + * Complete tests initialization: Each tests needs to point to it's + * corresponing suite. + * Creates the framework debugfs root directory under IPA directory. + * Create enable debugfs file - to enable/disable the framework. + * + * Return: Zero in success, otherwise in failure + */ +static int ipa_ut_framework_init(void) +{ + struct dentry *dfile_enable; + int ret; + int suite_idx; + int test_idx; + struct ipa_ut_suite *suite; + + IPA_UT_DBG("Entry\n"); + + ipa_assert_on(!ipa_ut_ctx); + +#ifdef CONFIG_DEBUG_FS + ipa_ut_ctx->ipa_dbgfs_root = ipa_debugfs_get_root(); +#endif + if (!ipa_ut_ctx->ipa_dbgfs_root) { + IPA_UT_ERR("No IPA debugfs root entry\n"); + return -EFAULT; + } + + mutex_lock(&ipa_ut_ctx->lock); + + /* tests needs to point to their corresponding suites structures */ + for (suite_idx = IPA_UT_SUITE_FIRST_INDEX; + suite_idx < IPA_UT_SUITES_COUNT; suite_idx++) { + suite = IPA_UT_GET_SUITE(suite_idx); + ipa_assert_on(!suite); + if (!suite->tests) { + IPA_UT_DBG("No tests for suite %s\n", + suite->meta_data->name); + continue; + } + for (test_idx = 0; test_idx < suite->tests_cnt; test_idx++) { + suite->tests[test_idx].suite = suite; + IPA_UT_DBG("Updating test %s info for suite %s\n", + suite->tests[test_idx].name, + suite->meta_data->name); + } + } + + ipa_ut_ctx->wq = create_singlethread_workqueue("ipa_ut_dbgfs"); + if (!ipa_ut_ctx->wq) { + IPA_UT_ERR("create workqueue failed\n"); + ret = -ENOMEM; + goto unlock_mutex; + } + + ipa_ut_ctx->test_dbgfs_root = debugfs_create_dir("test", + ipa_ut_ctx->ipa_dbgfs_root); + if (!ipa_ut_ctx->test_dbgfs_root || + IS_ERR(ipa_ut_ctx->test_dbgfs_root)) { + IPA_UT_ERR("failed to create test debugfs dir\n"); + ret = -EFAULT; + destroy_workqueue(ipa_ut_ctx->wq); + goto unlock_mutex; + } + + dfile_enable = debugfs_create_file("enable", + IPA_UT_READ_WRITE_DBG_FILE_MODE, + ipa_ut_ctx->test_dbgfs_root, 0, &ipa_ut_dbgfs_enable_fops); + if (!dfile_enable || IS_ERR(dfile_enable)) { + IPA_UT_ERR("failed to create enable debugfs file\n"); + ret = -EFAULT; + destroy_workqueue(ipa_ut_ctx->wq); + goto fail_clean_dbgfs; + } + + _IPA_UT_TEST_FAIL_REPORT_IDX = 0; + ipa_ut_ctx->inited = true; + IPA_UT_DBG("Done\n"); + ret = 0; + goto unlock_mutex; + +fail_clean_dbgfs: + debugfs_remove_recursive(ipa_ut_ctx->test_dbgfs_root); +unlock_mutex: + mutex_unlock(&ipa_ut_ctx->lock); + return ret; +} + +/** + * ipa_ut_framework_destroy() - Destroy the UT framework info + * + * Disable it if enabled. + * Remove the debugfs entries using the root entry + */ +static void ipa_ut_framework_destroy(void) +{ + IPA_UT_DBG("Entry\n"); + + mutex_lock(&ipa_ut_ctx->lock); + destroy_workqueue(ipa_ut_ctx->wq); + if (ipa_ut_ctx->enabled) + ipa_ut_framework_disable(); + if (ipa_ut_ctx->inited) + debugfs_remove_recursive(ipa_ut_ctx->test_dbgfs_root); + mutex_unlock(&ipa_ut_ctx->lock); +} + +/** + * ipa_ut_ipa_ready_cb() - IPA ready CB + * + * Once IPA is ready starting initializing the unit-test framework + */ +static void ipa_ut_ipa_ready_cb(void *user_data) +{ + IPA_UT_DBG("Entry\n"); + (void)ipa_ut_framework_init(); +} + +/** + * ipa_ut_module_init() - Module init + * + * Create the framework context, wait for IPA driver readiness + * and Initialize it. + * If IPA driver already ready, continue initialization immediately. + * if not, wait for IPA ready notification by IPA driver context + */ +int ipa_ut_module_init(void) +{ + int ret = 0; + bool init_framewok = true; + + IPA_UT_INFO("Loading IPA test module...\n"); + + ipa_ut_ctx = kzalloc(sizeof(struct ipa_ut_context), GFP_KERNEL); + if (!ipa_ut_ctx) { + IPA_UT_ERR("Failed to allocate ctx\n"); + return -ENOMEM; + } + mutex_init(&ipa_ut_ctx->lock); + + if (!ipa_is_ready()) { + init_framewok = false; + + IPA_UT_DBG("IPA driver not ready, registering callback\n"); + + ret = ipa_register_ipa_ready_cb(ipa_ut_ipa_ready_cb, NULL); + + /* + * If the call to ipa_register_ipa_ready_cb() above + * returns 0, this means that we've succeeded in + * queuing up a future call to ipa_ut_framework_init() + * and that the call to it will be made once the IPA + * becomes ready. If this is the case, the call to + * ipa_ut_framework_init() below need not be made. + * + * If the call to ipa_register_ipa_ready_cb() above + * returns -EEXIST, it means that during the call to + * ipa_register_ipa_ready_cb(), the IPA has become + * ready, and hence, no indirect call to + * ipa_ut_framework_init() will be made, so we need to + * call it ourselves below. + * + * If the call to ipa_register_ipa_ready_cb() above + * return something other than 0 or -EEXIST, that's a + * hard error. + */ + if (ret == -EEXIST) { + init_framewok = true; + } else { + if (ret) { + IPA_UT_ERR("IPA CB reg failed - %d\n", ret); + kfree(ipa_ut_ctx); + ipa_ut_ctx = NULL; + } + return ret; + } + } + + if (init_framewok) { + ret = ipa_ut_framework_init(); + if (ret) { + IPA_UT_ERR("framework init failed\n"); + kfree(ipa_ut_ctx); + ipa_ut_ctx = NULL; + } + } + + return ret; +} + +/** + * ipa_ut_module_exit() - Module exit function + * + * Destroys the Framework and removes its context + */ +void ipa_ut_module_exit(void) +{ + IPA_UT_DBG("Entry\n"); + + if (!ipa_ut_ctx) + return; + + ipa_ut_framework_destroy(); + kfree(ipa_ut_ctx); + ipa_ut_ctx = NULL; +} + diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/test/ipa_ut_framework.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/test/ipa_ut_framework.h new file mode 100644 index 0000000000..c5d93018ab --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/test/ipa_ut_framework.h @@ -0,0 +1,233 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _IPA_UT_FRAMEWORK_H_ +#define _IPA_UT_FRAMEWORK_H_ + +#include +#include "ipa_common_i.h" +#include "ipa_ut_i.h" + +#define IPA_UT_DRV_NAME "ipa_ut" + +#define IPA_UT_DBG(fmt, args...) \ + do { \ + pr_debug(IPA_UT_DRV_NAME " %s:%d " fmt, \ + __func__, __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf(), \ + IPA_UT_DRV_NAME " %s:%d " fmt, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf_low(), \ + IPA_UT_DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) + +#define IPA_UT_DBG_LOW(fmt, args...) \ + do { \ + pr_debug(IPA_UT_DRV_NAME " %s:%d " fmt, \ + __func__, __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf_low(), \ + IPA_UT_DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) + +#define IPA_UT_ERR(fmt, args...) \ + do { \ + pr_err(IPA_UT_DRV_NAME " %s:%d " fmt, \ + __func__, __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf(), \ + IPA_UT_DRV_NAME " %s:%d " fmt, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf_low(), \ + IPA_UT_DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) + +#define IPA_UT_INFO(fmt, args...) \ + do { \ + pr_info(IPA_UT_DRV_NAME " %s:%d " fmt, \ + __func__, __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf(), \ + IPA_UT_DRV_NAME " %s:%d " fmt, ## args); \ + IPA_IPC_LOGGING(ipa3_get_ipc_logbuf_low(), \ + IPA_UT_DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) + +/** + * struct ipa_ut_tst_fail_report - Information on test failure + * @valid: When a test posts a report, valid will be marked true + * @file: File name containing the failed test. + * @line: Number of line in the file where the test failed. + * @func: Function where the test failed in. + * @info: Information about the failure. + */ +struct ipa_ut_tst_fail_report { + bool valid; + const char *file; + int line; + const char *func; + const char *info; +}; + +/** + * Report on test failure + * To be used by tests to report a point were a test fail. + * Failures are saved in a stack manner. + * Dumping the failure info will dump the fail reports + * from all the function in the calling stack + */ +#define IPA_UT_TEST_FAIL_REPORT(__info) \ + do { \ + extern struct ipa_ut_tst_fail_report \ + _IPA_UT_TEST_FAIL_REPORT_DATA \ + [_IPA_UT_TEST_FAIL_REPORT_SIZE]; \ + extern u32 _IPA_UT_TEST_FAIL_REPORT_IDX; \ + struct ipa_ut_tst_fail_report *entry; \ + if (_IPA_UT_TEST_FAIL_REPORT_IDX >= \ + _IPA_UT_TEST_FAIL_REPORT_SIZE) \ + break; \ + entry = &(_IPA_UT_TEST_FAIL_REPORT_DATA \ + [_IPA_UT_TEST_FAIL_REPORT_IDX]); \ + entry->file = __FILENAME__; \ + entry->line = __LINE__; \ + entry->func = __func__; \ + if (__info) \ + entry->info = __info; \ + else \ + entry->info = ""; \ + _IPA_UT_TEST_FAIL_REPORT_IDX++; \ + } while (0) + +/** + * To be used by tests to log progress and ongoing information + * Logs are not printed to user, but saved to a buffer. + * I/S shall print the buffer at different occasions - e.g. in test failure + */ +#define IPA_UT_LOG(fmt, args...) \ + do { \ + extern char *_IPA_UT_TEST_LOG_BUF_NAME; \ + char __buf[512]; \ + IPA_UT_DBG(fmt, ## args); \ + if (!_IPA_UT_TEST_LOG_BUF_NAME) {\ + pr_err(IPA_UT_DRV_NAME " %s:%d " fmt, \ + __func__, __LINE__, ## args); \ + break; \ + } \ + scnprintf(__buf, sizeof(__buf), \ + " %s:%d " fmt, \ + __func__, __LINE__, ## args); \ + strlcat(_IPA_UT_TEST_LOG_BUF_NAME, __buf, \ + _IPA_UT_TEST_LOG_BUF_SIZE); \ + } while (0) + +/** + * struct ipa_ut_suite_meta - Suite meta-data + * @name: Suite unique name + * @desc: Suite description + * @setup: Setup Call-back of the suite + * @teardown: Teardown Call-back of the suite + * @priv: Private pointer of the suite + * + * Setup/Teardown will be called once for the suite when running a tests of it. + * priv field is shared between the Setup/Teardown and the tests + */ +struct ipa_ut_suite_meta { + char *name; + char *desc; + int (*setup)(void **ppriv); + int (*teardown)(void *priv); + void *priv; +}; + +/* Test suite data structure declaration */ +struct ipa_ut_suite; + +/** + * struct ipa_ut_test - Test information + * @name: Test name + * @desc: Test description + * @run: Test execution call-back + * @run_in_regression: To run this test as part of regression? + * @min_ipa_hw_ver: Minimum IPA H/W version where the test is supported? + * @max_ipa_hw_ver: Maximum IPA H/W version where the test is supported? + * @suite: Pointer to suite containing this test + * @res: Test execution result. Will be updated after running a test as part + * of suite tests run + */ +struct ipa_ut_test { + char *name; + char *desc; + int (*run)(void *priv); + bool run_in_regression; + int min_ipa_hw_ver; + int max_ipa_hw_ver; + struct ipa_ut_suite *suite; + enum ipa_ut_test_result res; +}; + +/** + * struct ipa_ut_suite - Suite information + * @meta_data: Pointer to meta-data structure of the suite + * @tests: Pointer to array of tests belongs to the suite + * @tests_cnt: Number of tests + */ +struct ipa_ut_suite { + struct ipa_ut_suite_meta *meta_data; + struct ipa_ut_test *tests; + size_t tests_cnt; +}; + + +/** + * Add a test to a suite. + * Will add entry to tests array and update its info with + * the given info, thus adding new test. + */ +#define IPA_UT_ADD_TEST(__name, __desc, __run, __run_in_regression, \ + __min_ipa_hw_ver, __max_ipa__hw_ver) \ + { \ + .name = #__name, \ + .desc = __desc, \ + .run = __run, \ + .run_in_regression = __run_in_regression, \ + .min_ipa_hw_ver = __min_ipa_hw_ver, \ + .max_ipa_hw_ver = __max_ipa__hw_ver, \ + .suite = NULL, \ + } + +/** + * Declare a suite + * Every suite need to be declared before it is registered. + */ +#define IPA_UT_DECLARE_SUITE(__name) \ + extern struct ipa_ut_suite _IPA_UT_SUITE_DATA(__name) + +/** + * Register a suite + * Registering a suite is mandatory so it will be considered. + */ +#define IPA_UT_REGISTER_SUITE(__name) \ + (&_IPA_UT_SUITE_DATA(__name)) + +/** + * Start/End suite definition + * Will create the suite global structures and adds adding tests to it. + * Use IPA_UT_ADD_TEST() with these macros to add tests when defining + * a suite + */ +#define IPA_UT_DEFINE_SUITE_START(__name, __desc, __setup, __teardown) \ + static struct ipa_ut_suite_meta _IPA_UT_SUITE_META_DATA(__name) = \ + { \ + .name = #__name, \ + .desc = __desc, \ + .setup = __setup, \ + .teardown = __teardown, \ + }; \ + static struct ipa_ut_test _IPA_UT_SUITE_TESTS(__name)[] = +#define IPA_UT_DEFINE_SUITE_END(__name) \ + ; \ + struct ipa_ut_suite _IPA_UT_SUITE_DATA(__name) = \ + { \ + .meta_data = &_IPA_UT_SUITE_META_DATA(__name), \ + .tests = _IPA_UT_SUITE_TESTS(__name), \ + .tests_cnt = ARRAY_SIZE(_IPA_UT_SUITE_TESTS(__name)), \ + } + +#endif /* _IPA_UT_FRAMEWORK_H_ */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/test/ipa_ut_i.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/test/ipa_ut_i.h new file mode 100644 index 0000000000..973f7ede13 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/test/ipa_ut_i.h @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _IPA_UT_I_H_ +#define _IPA_UT_I_H_ + +/* Suite data global structure name */ +#define _IPA_UT_SUITE_DATA(__name) ipa_ut_ ##__name ##_data + +/* Suite meta-data global structure name */ +#define _IPA_UT_SUITE_META_DATA(__name) ipa_ut_ ##__name ##_meta_data + +/* Suite global array of tests */ +#define _IPA_UT_SUITE_TESTS(__name) ipa_ut_ ##__name ##_tests + +/* Global array of all suites */ +#define _IPA_UT_ALL_SUITES ipa_ut_all_suites_data + +/* Meta-test "all" name - test to run all tests in given suite */ +#define _IPA_UT_RUN_ALL_TEST_NAME "all" + +/** + * Meta-test "regression" name - + * test to run all regression tests in given suite + */ +#define _IPA_UT_RUN_REGRESSION_TEST_NAME "regression" + + +/* Test Log buffer name and size */ +#define _IPA_UT_TEST_LOG_BUF_NAME ipa_ut_tst_log_buf +#define _IPA_UT_TEST_LOG_BUF_SIZE 8192 + +/* Global structure for test fail execution result information */ +#define _IPA_UT_TEST_FAIL_REPORT_DATA ipa_ut_tst_fail_report_data +#define _IPA_UT_TEST_FAIL_REPORT_SIZE 5 +#define _IPA_UT_TEST_FAIL_REPORT_IDX ipa_ut_tst_fail_report_data_index + +/* Start/End definitions of the array of suites */ +#define IPA_UT_DEFINE_ALL_SUITES_START \ + static struct ipa_ut_suite *_IPA_UT_ALL_SUITES[] = +#define IPA_UT_DEFINE_ALL_SUITES_END + +/** + * Suites iterator - Array-like container + * First index, number of elements and element fetcher + */ +#define IPA_UT_SUITE_FIRST_INDEX 0 +#define IPA_UT_SUITES_COUNT \ + ARRAY_SIZE(_IPA_UT_ALL_SUITES) +#define IPA_UT_GET_SUITE(__index) \ + _IPA_UT_ALL_SUITES[__index] + +/** + * enum ipa_ut_test_result - Test execution result + * @IPA_UT_TEST_RES_FAIL: Test executed and failed + * @IPA_UT_TEST_RES_SUCCESS: Test executed and succeeded + * @IPA_UT_TEST_RES_SKIP: Test was not executed. + * + * When running all tests in a suite, a specific test could + * be skipped and not executed. For example due to mismatch of + * IPA H/W version. + */ +enum ipa_ut_test_result { + IPA_UT_TEST_RES_FAIL, + IPA_UT_TEST_RES_SUCCESS, + IPA_UT_TEST_RES_SKIP, +}; + +/** + * enum ipa_ut_meta_test_type - Type of suite meta-test + * @IPA_UT_META_TEST_ALL: Represents all tests in suite + * @IPA_UT_META_TEST_REGRESSION: Represents all regression tests in suite + */ +enum ipa_ut_meta_test_type { + IPA_UT_META_TEST_ALL, + IPA_UT_META_TEST_REGRESSION, +}; + +#endif /* _IPA_UT_I_H_ */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa/test/ipa_ut_suite_list.h b/qcom/opensource/dataipa/drivers/platform/msm/ipa/test/ipa_ut_suite_list.h new file mode 100644 index 0000000000..3db6c49db1 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa/test/ipa_ut_suite_list.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2016-2019, 2021 The Linux Foundation. All rights reserved. + */ + +#ifndef _IPA_UT_SUITE_LIST_H_ +#define _IPA_UT_SUITE_LIST_H_ + +#include "ipa_ut_framework.h" +#include "ipa_ut_i.h" + +/** + * Declare every suite here so that it will be found later below + * No importance for order. + */ +IPA_UT_DECLARE_SUITE(mhi); +IPA_UT_DECLARE_SUITE(dma); +IPA_UT_DECLARE_SUITE(pm); +IPA_UT_DECLARE_SUITE(example); +IPA_UT_DECLARE_SUITE(hw_stats); +IPA_UT_DECLARE_SUITE(wdi3); +IPA_UT_DECLARE_SUITE(ntn); + + +/** + * Register every suite inside the below block. + * Unregistered suites will be ignored + */ +IPA_UT_DEFINE_ALL_SUITES_START +{ + IPA_UT_REGISTER_SUITE(mhi), + IPA_UT_REGISTER_SUITE(dma), + IPA_UT_REGISTER_SUITE(pm), + IPA_UT_REGISTER_SUITE(example), + IPA_UT_REGISTER_SUITE(hw_stats), + IPA_UT_REGISTER_SUITE(wdi3), + IPA_UT_REGISTER_SUITE(ntn), +} IPA_UT_DEFINE_ALL_SUITES_END; + +#endif /* _IPA_UT_SUITE_LIST_H_ */ diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa_kernel_headers.py b/qcom/opensource/dataipa/drivers/platform/msm/ipa_kernel_headers.py new file mode 100644 index 0000000000..e957e8006f --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa_kernel_headers.py @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: GPL-2.0-only +# Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + +import argparse +import filecmp +import os +import re +import subprocess +import sys + +def run_headers_install(verbose, gen_dir, headers_install, unifdef, prefix, h): + if not h.startswith(prefix): + print('error: expected prefix [%s] on header [%s]' % (prefix, h)) + return False + + out_h = os.path.join(gen_dir, h[len(prefix):]) + (out_h_dirname, out_h_basename) = os.path.split(out_h) + env = os.environ.copy() + env["LOC_UNIFDEF"] = unifdef + cmd = ["sh", headers_install, h, out_h] + + if verbose: + print('run_headers_install: cmd is %s' % cmd) + + result = subprocess.call(cmd, env=env) + + if result != 0: + print('error: run_headers_install: cmd %s failed %d' % (cmd, result)) + return False + return True + +def gen_ipa_headers(verbose, gen_dir, headers_install, unifdef, ipa_include_uapi): + error_count = 0 + for h in ipa_include_uapi: + ipa_uapi_include_prefix = os.path.join(h.split('/include/uapi/')[0], + 'include', + 'uapi') + os.sep + + if not run_headers_install( + verbose, gen_dir, headers_install, unifdef, + ipa_uapi_include_prefix, h): error_count += 1 + return error_count + +def main(): + """Parse command line arguments and perform top level control.""" + parser = argparse.ArgumentParser( + description=__doc__, + formatter_class=argparse.RawDescriptionHelpFormatter) + + # Arguments that apply to every invocation of this script. + parser.add_argument( + '--verbose', action='store_true', + help='Print output that describes the workings of this script.') + parser.add_argument( + '--gen_dir', required=True, + help='Where to place the generated files.') + parser.add_argument( + '--ipa_include_uapi', required=True, nargs='*', + help='The list of header files.') + parser.add_argument( + '--headers_install', required=True, + help='The headers_install tool to process input headers.') + parser.add_argument( + '--unifdef', + required=True, + help='The unifdef tool used by headers_install.') + + args = parser.parse_args() + + if args.verbose: + print('gen_dir [%s]' % args.gen_dir) + print('ipa_include_uapi [%s]' % args.ipa_include_uapi) + print('headers_install [%s]' % args.headers_install) + print('unifdef [%s]' % args.unifdef) + + return gen_ipa_headers(args.verbose, args.gen_dir, + args.headers_install, args.unifdef, args.ipa_include_uapi) + +if __name__ == '__main__': + sys.exit(main()) diff --git a/qcom/opensource/dataipa/drivers/platform/msm/ipa_test_kernel_headers.py b/qcom/opensource/dataipa/drivers/platform/msm/ipa_test_kernel_headers.py new file mode 100644 index 0000000000..fcd4de03d0 --- /dev/null +++ b/qcom/opensource/dataipa/drivers/platform/msm/ipa_test_kernel_headers.py @@ -0,0 +1,88 @@ +# Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License version 2 and +# only version 2 as published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. + +import argparse +import filecmp +import os +import re +import subprocess +import sys + +def run_headers_install(verbose, gen_dir, headers_install, unifdef, prefix, h): + if not h.startswith(prefix): + print('error: expected prefix [%s] on header [%s]' % (prefix, h)) + return False + + out_h = os.path.join(gen_dir, h[len(prefix):]) + (out_h_dirname, out_h_basename) = os.path.split(out_h) + env = os.environ.copy() + env["LOC_UNIFDEF"] = unifdef + cmd = ["sh", headers_install, h, out_h] + + if verbose: + print('run_headers_install: cmd is %s' % cmd) + + result = subprocess.call(cmd, env=env) + + if result != 0: + print('error: run_headers_install: cmd %s failed %d' % (cmd, result)) + return False + return True + +def gen_ipa_test_headers(verbose, gen_dir, headers_install, unifdef, ipa_test_include_uapi): + error_count = 0 + for h in ipa_test_include_uapi: + ipa_test_uapi_include_prefix = os.path.join(h.split('/ipa/ipa_test_module/')[0], + 'ipa', + 'ipa_test_module') + os.sep + + if not run_headers_install( + verbose, gen_dir, headers_install, unifdef, + ipa_test_uapi_include_prefix, h): error_count += 1 + return error_count + +def main(): + """Parse command line arguments and perform top level control.""" + parser = argparse.ArgumentParser( + description=__doc__, + formatter_class=argparse.RawDescriptionHelpFormatter) + + # Arguments that apply to every invocation of this script. + parser.add_argument( + '--verbose', action='store_true', + help='Print output that describes the workings of this script.') + parser.add_argument( + '--gen_dir', required=True, + help='Where to place the generated files.') + parser.add_argument( + '--ipa_test_include_uapi', required=True, nargs='*', + help='The list of header files.') + parser.add_argument( + '--headers_install', required=True, + help='The headers_install tool to process input headers.') + parser.add_argument( + '--unifdef', + required=True, + help='The unifdef tool used by headers_install.') + + args = parser.parse_args() + + if args.verbose: + print('gen_dir [%s]' % args.gen_dir) + print('ipa_test_include_uapi [%s]' % args.ipa_test_include_uapi) + print('headers_install [%s]' % args.headers_install) + print('unifdef [%s]' % args.unifdef) + + return gen_ipa_test_headers(args.verbose, args.gen_dir, + args.headers_install, args.unifdef, args.ipa_test_include_uapi) + +if __name__ == '__main__': + sys.exit(main()) diff --git a/qcom/opensource/dataipa/ipanat/Android.bp b/qcom/opensource/dataipa/ipanat/Android.bp new file mode 100644 index 0000000000..c122824832 --- /dev/null +++ b/qcom/opensource/dataipa/ipanat/Android.bp @@ -0,0 +1,28 @@ +cc_library_shared { + name: "libipanat", + + header_libs: ["device_kernel_headers"]+["qti_kernel_headers"]+["qti_ipa_kernel_headers"], + + srcs: [ + "src/ipa_nat_map.cpp", + "src/ipa_table.c", + "src/ipa_nat_statemach.c", + "src/ipa_nat_drvi.c", + "src/ipa_nat_drv.c", + "src/ipa_mem_descriptor.c", + "src/ipa_nat_utils.c", + "src/ipa_ipv6ct.c", + ], + + shared_libs: + ["libcutils", + "libdl", + "libbase", + "libutils", + ], + export_include_dirs: ["inc"], + vendor: true, + + cflags: ["-DDEBUG"] + ["-DFEATURE_IPA_ANDROID"] + ["-Wno-int-conversion"], + +} diff --git a/qcom/opensource/dataipa/ipanat/NOTICE b/qcom/opensource/dataipa/ipanat/NOTICE new file mode 100644 index 0000000000..b7f9f90ac8 --- /dev/null +++ b/qcom/opensource/dataipa/ipanat/NOTICE @@ -0,0 +1,26 @@ +Copyright (c) 2021 The Linux Foundation. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are +met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above + copyright notice, this list of conditions and the following + disclaimer in the documentation and/or other materials provided + with the distribution. + * Neither the name of The Linux Foundation nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED +WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT +ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS +BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \ No newline at end of file diff --git a/qcom/opensource/dataipa/ipanat/inc/ipa_ipv6ct.h b/qcom/opensource/dataipa/ipanat/inc/ipa_ipv6ct.h new file mode 100644 index 0000000000..7796d30bf1 --- /dev/null +++ b/qcom/opensource/dataipa/ipanat/inc/ipa_ipv6ct.h @@ -0,0 +1,159 @@ +/* + * Copyright (c) 2018, 2020 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef IPA_IPV6CT_H +#define IPA_IPV6CT_H + +#include +#include +#include + +/** + * enum ipa_ipv6_ct_direction_settings_type - direction filter settings + * + * IPA_IPV6CT_DIRECTION_DENY_ALL - deny inbound and outbound + * IPA_IPV6CT_DIRECTION_ALLOW_OUT - allow outbound and deny inbound + * IPA_IPV6CT_DIRECTION_ALLOW_IN - allow inbound and deny outbound + * IPA_IPV6CT_DIRECTION_ALLOW_ALL - allow inbound and outbound + */ +typedef enum +{ + IPA_IPV6CT_DIRECTION_DENY_ALL = 0, + IPA_IPV6CT_DIRECTION_ALLOW_OUT = 1, + IPA_IPV6CT_DIRECTION_ALLOW_IN = 2, + IPA_IPV6CT_DIRECTION_ALLOW_ALL = 3 +} ipa_ipv6_ct_direction_settings_type; + +/** + * struct ipa_ipv6ct_rule - To hold IPv6CT rule + * @src_ipv6_lsb: source IPv6 address LSB + * @src_ipv6_msb: source IPv6 address MSB + * @dest_ipv6_lsb: destination IPv6 address LSB + * @dest_ipv6_msb: destination IPv6 address MSB + * @direction_settings: direction filter settings (inbound/outbound) (see ipa_ipv6_ct_direction_settings_type) + * @src_port: source port + * @dest_port: destination port + * @protocol: protocol of rule (tcp/udp) + * @uc_activation_index: index pointing to uc activation table + * @s: bit indication to use the system or local (1 or 0) addr for above table + * @ucp: enable uc processing + */ +typedef struct { + uint64_t src_ipv6_lsb; + uint64_t src_ipv6_msb; + uint64_t dest_ipv6_lsb; + uint64_t dest_ipv6_msb; + ipa_ipv6_ct_direction_settings_type direction_settings; + bool ucp; + bool s; + uint16_t uc_activation_index; + uint16_t src_port; + uint16_t dest_port; + uint8_t protocol; +} ipa_ipv6ct_rule; + +/** + * ipa_ipv6ct_add_tbl() - create IPv6CT table + * @number_of_entries: [in] number of IPv6CT entries + * @table_handle: [out] handle of new IPv6CT table + * + * To create new IPv6CT table + * + * Returns: 0 On Success, negative on failure + */ +int ipa_ipv6ct_add_tbl(uint16_t number_of_entries, uint32_t* table_handle); + +/** + * ipa_ipv6ct_del_tbl() - delete IPv6CT table + * @table_handle: [in] Handle of IPv6CT table + * + * To delete given IPv6CT table + * + * Returns: 0 On Success, negative on failure + */ +int ipa_ipv6ct_del_tbl(uint32_t table_handle); + +/** + * ipa_ipv6ct_add_rule() - to insert new IPv6CT rule + * @table_handle: [in] handle of IPv6CT table + * @user_rule: [in] Pointer to new rule + * @rule_handle: [out] Return the handle to rule + * + * To insert new rule into a IPv6CT table + * + * Returns: 0 On Success, negative on failure + */ +int ipa_ipv6ct_add_rule(uint32_t table_handle, const ipa_ipv6ct_rule* user_rule, uint32_t* rule_handle); + +/** + * ipa_ipv6ct_del_rule() - to delete IPv6CT rule + * @table_handle: [in] handle of IPv6CT table + * @rule_handle: [in] IPv6CT rule handle + * + * To delete a rule from a IPv6CT table + * + * Returns: 0 On Success, negative on failure + */ +int ipa_ipv6ct_del_rule(uint32_t table_handle, uint32_t rule_handle); + +/** + * ipa_ipv6ct_query_timestamp() - to query timestamp + * @table_handle: [in] handle of IPv6CT table + * @rule_handle: [in] IPv6CT rule handle + * @time_stamp: [out] time stamp of rule + * + * To retrieve the timestamp that lastly the IPv6CT rule was accessed + * + * Returns: 0 On Success, negative on failure + */ +int ipa_ipv6ct_query_timestamp(uint32_t table_handle, uint32_t rule_handle, uint32_t* time_stamp); + +/** + * ipa_ipv6ct_dump_table() - dumps IPv6CT table + * @table_handle: [in] handle of IPv6CT table + */ +void ipa_ipv6ct_dump_table(uint32_t tbl_hdl); + +/** + * ipa_ipv6ct_add_uc_act_entry() - add uc activation entry + * @u: [in] structure specifying the uC activation entry + * + * Returns: 0 On Success, negative on failure + */ +int ipa_ipv6ct_add_uc_act_entry(union ipa_ioc_uc_activation_entry *u); + +/** + * ipa_ipv6ct_del_uc_act_entry() - del uc activation entry + * @index: [in] index of the uc activation entry to be removed + * + * Returns: 0 On Success, negative on failure + */ +int ipa_ipv6ct_del_uc_act_entry(uint16_t index); + +#endif + diff --git a/qcom/opensource/dataipa/ipanat/inc/ipa_ipv6cti.h b/qcom/opensource/dataipa/ipanat/inc/ipa_ipv6cti.h new file mode 100644 index 0000000000..c4dc32af4b --- /dev/null +++ b/qcom/opensource/dataipa/ipanat/inc/ipa_ipv6cti.h @@ -0,0 +1,151 @@ +/* + * Copyright (c) 2018, 2020 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef IPA_IPV6CTI_H +#define IPA_IPV6CTI_H + +#include "ipa_table.h" +#include "ipa_mem_descriptor.h" +#include "ipa_nat_utils.h" + +#define IPA_IPV6CT_MAX_TBLS 1 + +#define IPA_IPV6CT_RULE_FLAG_FIELD_OFFSET 34 +#define IPA_IPV6CT_RULE_NEXT_FIELD_OFFSET 40 +#define IPA_IPV6CT_RULE_PROTO_FIELD_OFFSET 38 + +#define IPA_IPV6CT_FLAG_ENABLE_BIT 1 + +#define IPA_IPV6CT_DIRECTION_ALLOW_BIT 1 +#define IPA_IPV6CT_DIRECTION_DISALLOW_BIT 0 + +#define IPA_IPV6CT_INVALID_PROTO_FIELD_VALUE 0xFF00 +#define IPA_IPV6CT_INVALID_PROTO_FIELD_CMP 0xFF + +typedef enum +{ + IPA_IPV6CT_TABLE_FLAGS, + IPA_IPV6CT_TABLE_NEXT_INDEX, + IPA_IPV6CT_TABLE_PROTOCOL, + IPA_IPV6CT_TABLE_DMA_CMD_MAX +} ipa_ipv6ct_table_dma_cmd_type; + +/*------------------------ IPV6CT Table Entry --------------------------------------------------- + + ------------------------------------------------------------------------------------------------- + | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | + --------------------------------------------------------------------------------------------------- + | Outbound Src IPv6 Address (8 LSB Bytes) | + --------------------------------------------------------------------------------------------------- + | Outbound Src IPv6 Address (8 MSB Bytes) | + --------------------------------------------------------------------------------------------------- + | Outbound Dest IPv6 Address (8 LSB Bytes) | + --------------------------------------------------------------------------------------------------- + | Outbound Dest IPv6 Address (8 MSB Bytes) | + --------------------------------------------------------------------------------------------------- + | Protocol | TimeStamp (3B) | Flags (2B) |Rsvd |S |uC activatio| + | (1B) | |Enable|Redirect|Resv |[15:14]|13|Index [12:0]| + --------------------------------------------------------------------------------------------------- + |Reserved |Settings | Src Port (2B) | Dest Port (2B) | Next Index (2B) | + | (1B) | (1B) | | | | + --------------------------------------------------------------------------------------------------- + | SW Specific Parameters(4B) | Reserved (4B) | + | Prev Index (2B) | Reserved (2B) | | + --------------------------------------------------------------------------------------------------- + | Reserved (8B) | + --------------------------------------------------------------------------------------------------- + + Settings(1B) + ----------------------------------------------- + |IN Allowed|OUT Allowed|Reserved|uC processing| + |[7:7] |[6:6] |[5:1] |[0:0] | + ----------------------------------------------- + + Dont change below structure definition. + It should be same as above(little endian order) + -------------------------------------------------------------------------------------------------*/ +typedef struct +{ + uint64_t src_ipv6_lsb : 64; + uint64_t src_ipv6_msb : 64; + uint64_t dest_ipv6_lsb : 64; + uint64_t dest_ipv6_msb : 64; + + uint64_t uc_activation_index : 13; + uint64_t s : 1; + uint64_t rsvd1 : 16; + uint64_t redirect : 1; + uint64_t enable : 1; + uint64_t time_stamp : 24; + uint64_t protocol : 8; + + uint64_t next_index : 16; + uint64_t dest_port : 16; + uint64_t src_port : 16; + uint64_t ucp : 1; + uint64_t rsvd2 : 5; + uint64_t out_allowed : 1; + uint64_t in_allowed : 1; + uint64_t rsvd3 : 8; + + uint64_t rsvd4 : 48; + uint64_t prev_index : 16; + + uint64_t rsvd5 : 64; +} ipa_ipv6ct_hw_entry; + +/* + ---------------------- + | 1 | 0 | + ---------------------- + | Flags(2B) | + |Enable|Redirect|Resv| + ---------------------- +*/ +typedef struct +{ + uint16_t rsvd1 : 14; + uint16_t redirect : 1; + uint16_t enable : 1; +} ipa_ipv6ct_flags; + +typedef struct +{ + ipa_mem_descriptor mem_desc; + ipa_table table; + ipa_table_dma_cmd_helper table_dma_cmd_helpers[IPA_IPV6CT_TABLE_DMA_CMD_MAX]; +} ipa_ipv6ct_table; + +typedef struct +{ + ipa_descriptor* ipa_desc; + ipa_ipv6ct_table tables[IPA_IPV6CT_MAX_TBLS]; + uint8_t table_cnt; +} ipa_ipv6ct; + +#endif diff --git a/qcom/opensource/dataipa/ipanat/inc/ipa_mem_descriptor.h b/qcom/opensource/dataipa/ipanat/inc/ipa_mem_descriptor.h new file mode 100644 index 0000000000..c7dd7399b4 --- /dev/null +++ b/qcom/opensource/dataipa/ipanat/inc/ipa_mem_descriptor.h @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2018-2020 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef IPA_MEM_DESCRIPTOR_H +#define IPA_MEM_DESCRIPTOR_H + +#include +#include +#include + +typedef struct +{ + int orig_rqst_size; + int mmap_size; + void* base_addr; + void* mmap_addr; + uint32_t addr_offset; + unsigned long allocate_ioctl_num; + unsigned long delete_ioctl_num; + char name[IPA_RESOURCE_NAME_MAX]; + uint8_t table_index; + uint8_t valid; + bool consider_using_sram; + bool sram_available; + bool sram_to_be_used; + struct ipa_nat_in_sram_info nat_sram_info; +} ipa_mem_descriptor; + +void ipa_mem_descriptor_init( + ipa_mem_descriptor* desc, + const char* device_name, + int size, + uint8_t table_index, + unsigned long allocate_ioctl_num, + unsigned long delete_ioctl_num, + bool consider_using_sram ); + +int ipa_mem_descriptor_allocate_memory( + ipa_mem_descriptor* desc, + int ipa_fd); + +int ipa_mem_descriptor_delete( + ipa_mem_descriptor* desc, + int ipa_fd); + +#endif diff --git a/qcom/opensource/dataipa/ipanat/inc/ipa_nat_drv.h b/qcom/opensource/dataipa/ipanat/inc/ipa_nat_drv.h new file mode 100644 index 0000000000..3686634aff --- /dev/null +++ b/qcom/opensource/dataipa/ipanat/inc/ipa_nat_drv.h @@ -0,0 +1,271 @@ +/* + * Copyright (c) 2013-2021 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef IPA_NAT_DRV_H +#define IPA_NAT_DRV_H + +#include "ipa_nat_utils.h" + +#include /* uint32_t */ +#include + +/** + * ipa_nat_is_sram_supported() - Reports if sram is available for use + */ +bool ipa_nat_is_sram_supported(void); + +/** + * struct ipa_nat_ipv4_rule - To hold ipv4 nat rule + * @target_ip: destination ip address + * @private_ip: private ip address + * @target_port: destination port + * @private_port: private port + * @protocol: protocol of rule (tcp/udp) + * @pdn_index: PDN index in the PDN config table + * @redirect: used internally by various API calls + * @enable: used internally by various API calls + * @time_stamp: used internally by various API calls + * @uc_activation_index: index pointing to uc activation table + * @s: bit indication to use the system or local (1 or 0) addr for above table + * @ucp: enable uc processing + * @dst_only: construct NAT for DL only + * @src_only: construct NAT for UL only + */ +typedef struct { + uint32_t target_ip; + uint32_t private_ip; + uint16_t target_port; + uint16_t private_port; + uint16_t public_port; + uint8_t protocol; + uint8_t pdn_index; + uint8_t redirect; + uint8_t enable; + uint32_t time_stamp; + uint16_t uc_activation_index; + bool s; + bool ucp; + bool dst_only; + bool src_only; +} ipa_nat_ipv4_rule; + +static inline char* prep_nat_ipv4_rule_4print( + ipa_nat_ipv4_rule* rule_ptr, + char* buf_ptr, + uint32_t buf_sz ) +{ + if ( rule_ptr && buf_ptr && buf_sz ) + { + snprintf( + buf_ptr, buf_sz, + "IPV4 RULE: " + "protocol(0x%02X) " + "public_port(0x%04X) " + "target_ip(0x%08X) " + "target_port(0x%04X) " + "private_ip(0x%08X) " + "private_port(0x%04X) " + "pdn_index(0x%02X)", + rule_ptr->protocol, + rule_ptr->public_port, + rule_ptr->target_ip, + rule_ptr->target_port, + rule_ptr->private_ip, + rule_ptr->private_port, + rule_ptr->pdn_index); + } + + return buf_ptr; +} + +/** + * struct ipa_nat_pdn_entry - holds a PDN entry data + * @public_ip: PDN's public ip address + * @src_metadata: metadata to be used for source NAT metadata replacement + * @dst_metadata: metadata to be used for destination NAT metadata replacement + */ +typedef struct { + uint32_t public_ip; + uint32_t src_metadata; + uint32_t dst_metadata; +} ipa_nat_pdn_entry; + +/** + * ipa_nat_add_ipv4_tbl() - create ipv4 nat table + * @public_ip_addr: [in] public ipv4 address + * @mem_type_ptr: [in] type of memory table is to reside in + * @number_of_entries: [in] number of nat entries + * @table_handle: [out] Handle of new ipv4 nat table + * + * To create new ipv4 nat table + * + * Returns: 0 On Success, negative on failure + */ +int ipa_nat_add_ipv4_tbl( + uint32_t public_ip_addr, + const char *mem_type_ptr, + uint16_t number_of_entries, + uint32_t *table_handle); + +/** + * ipa_nat_del_ipv4_tbl() - delete ipv4 table + * @table_handle: [in] Handle of ipv4 nat table + * + * To delete given ipv4 nat table + * + * Returns: 0 On Success, negative on failure + */ +int ipa_nat_del_ipv4_tbl(uint32_t table_handle); + +/** + * ipa_nat_add_ipv4_rule() - to insert new ipv4 rule + * @table_handle: [in] handle of ipv4 nat table + * @rule: [in] Pointer to new rule + * @rule_handle: [out] Return the handle to rule + * + * To insert new ipv4 nat rule into ipv4 nat table + * + * Returns: 0 On Success, negative on failure + */ +int ipa_nat_add_ipv4_rule(uint32_t table_handle, + const ipa_nat_ipv4_rule * rule, + uint32_t *rule_handle); + +/** + * ipa_nat_del_ipv4_rule() - to delete ipv4 nat rule + * @table_handle: [in] handle of ipv4 nat table + * @rule_handle: [in] ipv4 nat rule handle + * + * To insert new ipv4 nat rule into ipv4 nat table + * + * Returns: 0 On Success, negative on failure + */ +int ipa_nat_del_ipv4_rule(uint32_t table_handle, + uint32_t rule_handle); + + +/** + * ipa_nat_query_timestamp() - to query timestamp + * @table_handle: [in] handle of ipv4 nat table + * @rule_handle: [in] ipv4 nat rule handle + * @time_stamp: [out] time stamp of rule + * + * To retrieve the timestamp that lastly the + * nat rule was accessed + * + * Returns: 0 On Success, negative on failure + */ +int ipa_nat_query_timestamp(uint32_t table_handle, + uint32_t rule_handle, + uint32_t *time_stamp); + + +/** + * ipa_nat_modify_pdn() - modify single PDN entry in the PDN config table + * @table_handle: [in] handle of ipv4 nat table + * @pdn_index : [in] the index of the entry to be modified + * @pdn_info : [in] values for the PDN entry to be changed + * + * Modify a PDN entry + * + * Returns: 0 On Success, negative on failure + */ +int ipa_nat_modify_pdn(uint32_t tbl_hdl, + uint8_t pdn_index, + ipa_nat_pdn_entry *pdn_info); + +/** +* ipa_nat_get_pdn_index() - get a PDN index for a public ip +* @public_ip : [in] IPv4 address of the PDN entry +* @pdn_index : [out] the index of the requested PDN entry +* +* Get a PDN entry +* +* Returns: 0 On Success, negative on failure +*/ +int ipa_nat_get_pdn_index(uint32_t public_ip, uint8_t *pdn_index); + +/** +* ipa_nat_alloc_pdn() - allocate a PDN for new WAN +* @pdn_info : [in] values for the PDN entry to be created +* @pdn_index : [out] the index of the requested PDN entry +* +* allocate a new PDN entry +* +* Returns: 0 On Success, negative on failure +*/ +int ipa_nat_alloc_pdn(ipa_nat_pdn_entry *pdn_info, + uint8_t *pdn_index); + +/** +* ipa_nat_get_pdn_count() - get the number of allocated PDNs +* @pdn_cnt : [out] the number of allocated PDNs +* +* get the number of allocated PDNs +* +* Returns: 0 On Success, negative on failure +*/ +int ipa_nat_get_pdn_count(uint8_t *pdn_cnt); + +/** +* ipa_nat_dealloc_pdn() - deallocate a PDN entry +* @pdn_index : [in] pdn index to be deallocated +* +* deallocate a PDN in specified index - zero the PDN entry +* +* Returns: 0 On Success, negative on failure +*/ +int ipa_nat_dealloc_pdn(uint8_t pdn_index); + + +/** + * ipa_nat_dump_ipv4_table() - dumps IPv4 NAT table + * @table_handle: [in] handle of IPv4 NAT table + */ +void ipa_nat_dump_ipv4_table(uint32_t tbl_hdl); + +/** + * ipa_nat_vote_clock() - used for voting clock + * @vote_type: [in] desired vote type + */ +int ipa_nat_vote_clock( + enum ipa_app_clock_vote_type vote_type ); + +/** + * ipa_nat_switch_to() - While in HYBRID mode only, used for switching + * from SRAM to DDR or the reverse. + * @nmi: memory type to switch to + * @hold_state: Will the new memory type get locked in (ie. no more + * oscilation between the memory types) + */ +int ipa_nat_switch_to( + enum ipa3_nat_mem_in nmi, + bool hold_state ); + +#endif + diff --git a/qcom/opensource/dataipa/ipanat/inc/ipa_nat_drvi.h b/qcom/opensource/dataipa/ipanat/inc/ipa_nat_drvi.h new file mode 100644 index 0000000000..261583bb54 --- /dev/null +++ b/qcom/opensource/dataipa/ipanat/inc/ipa_nat_drvi.h @@ -0,0 +1,404 @@ +/* + * Copyright (c) 2013-2020 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef IPA_NAT_DRVI_H +#define IPA_NAT_DRVI_H + +#include "ipa_table.h" +#include "ipa_mem_descriptor.h" +#include "ipa_nat_utils.h" + +#undef MAKE_TBL_HDL +#define MAKE_TBL_HDL(hdl, mt) \ + ((mt) << 31 | (hdl)) + +#undef BREAK_TBL_HDL +#define BREAK_TBL_HDL(hdl_in, mt, hdl_out) \ + do { \ + mt = (hdl_in) >> 31 & 0x0000000001; \ + hdl_out = (hdl_in) & 0x00000000FF; \ + } while ( 0 ) + +#undef VALID_TBL_HDL +#define VALID_TBL_HDL(h) \ + (((h) & 0x00000000FF) == IPA_NAT_MAX_IP4_TBLS) + +/*======= IMPLEMENTATION related data structures and functions ======= */ + +#define IPA_NAT_MAX_IP4_TBLS 1 + +#define IPA_NAT_RULE_FLAG_FIELD_OFFSET 18 +#define IPA_NAT_RULE_NEXT_FIELD_OFFSET 8 +#define IPA_NAT_RULE_PROTO_FIELD_OFFSET 22 + +#define IPA_NAT_INDEX_RULE_NEXT_FIELD_OFFSET 2 +#define IPA_NAT_INDEX_RULE_NAT_INDEX_FIELD_OFFSET 0 + +#define IPA_NAT_FLAG_ENABLE_BIT 1 + +#define IPA_NAT_INVALID_PROTO_FIELD_VALUE 0xFF00 +/* + * IPA_NAT_INVALID_PROTO_FIELD_VALUE above is what's passed to the IPA + * in a DMA command. It is written into the NAT's rule, by the + * IPA. After being written, It minifests in the rule in the form + * below, hence it will be used when perusing the "struct + * ipa_nat_rule". + */ +#define IPA_NAT_INVALID_PROTO_FIELD_VALUE_IN_RULE 0xFF + +typedef enum { + IPA_NAT_TABLE_FLAGS, + IPA_NAT_TABLE_NEXT_INDEX, + IPA_NAT_TABLE_PROTOCOL, + IPA_NAT_INDEX_TABLE_ENTRY, + IPA_NAT_INDEX_TABLE_NEXT_INDEX, + IPA_NAT_TABLE_DMA_CMD_MAX +} ipa_nat_table_dma_cmd_type; + +/* + * ------------------------ NAT Table Entry ----------------------------------------- + * + * ------------------------------------------------------------------------------------ + * | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | + * ------------------------------------------------------------------------------------ + * | Target IP(4B) | Private IP(4B) | + * ------------------------------------------------------------------------------------ + * |Target Port(2B) | Private Port(2B) | Public Port(2B) | Next Index(2B) | + * ------------------------------------------------------------------------------------ + * | Proto | TimeStamp(3B) | Flags(2B) | IP check sum Diff(2B)| + * | (1B) | |EN|Redirect|Resv | | + * ------------------------------------------------------------------------------------ + * | TCP/UDP checksum |PDN info|Reserved | SW Specific Parameters(4B) | + * | diff (2B) | (1B) | (1B) | | + * ------------------------------------------------------------------------------------ + * + * Dont change below structure definition. + * + * It should be same as above(little endian order) + * + * ------------------------------------------------------------------------------- + */ +struct ipa_nat_rule { + uint64_t private_ip:32; + uint64_t target_ip:32; + + uint64_t next_index:16; + uint64_t public_port:16; + uint64_t private_port:16; + uint64_t target_port:16; + + uint64_t ip_chksum:16; + + /*-------------------------------------------------- + IPA NAT Flag is interpreted as follows + --------------------------------------------------- + | EN |FIN/RST| S | IPv4 uC activation index | + | [15] | [14] | [13] | [12:0] | + --------------------------------------------------- + --------------------------------------------------*/ + uint64_t uc_activation_index:13; + uint64_t s:1; + uint64_t redirect:1; + uint64_t enable:1; + + uint64_t time_stamp:24; + uint64_t protocol:8; + + /*-------------------------------------------------- + 32 bit sw_spec_params is interpreted as follows + ------------------------------------ + | 16 bits | 16 bits | + ------------------------------------ + | index table | prev index | + | entry | | + ------------------------------------ + --------------------------------------------------*/ + uint64_t prev_index:16; + uint64_t indx_tbl_entry:16; + uint64_t rsvd2:8; + /*----------------------------------------- + 8 bit PDN info is interpreted as following + ----------------------------------------------------- + | 4 bits | 1 bit | 3 bits | + ----------------------------------------------------- + | PDN index | uC processing | src dst Rsrv3 | + | [7:4] | [3] | [2] [1] [0] | + ----------------------------------------------------- + -------------------------------------------*/ + uint64_t rsvd3:1; + uint64_t dst_only:1; + uint64_t src_only:1; + uint64_t ucp:1; + uint64_t pdn_index:4; + + uint64_t tcp_udp_chksum:16; +}; + +static inline char* prep_nat_rule_4print( + struct ipa_nat_rule* rule_ptr, + char* buf_ptr, + uint32_t buf_sz ) +{ + if ( rule_ptr && buf_ptr && buf_sz ) + { + snprintf( + buf_ptr, buf_sz, + "NAT RULE: " + "protocol(0x%02X) " + "public_port(0x%04X) " + "target_ip(0x%08X) " + "target_port(0x%04X) " + "private_ip(0x%08X) " + "private_port(0x%04X) " + "pdn_index(0x%02X) " + "ip_chksum(0x%04X) " + "tcp_udp_chksum(0x%04X) " + "redirect(0x%02X) " + "enable(0x%02X) " + "time_stamp(0x%08X) " + "indx_tbl_entry(0x%04X) " + "prev_index(0x%04X) " + "next_index(0x%04X)", + rule_ptr->protocol, + rule_ptr->public_port, + rule_ptr->target_ip, + rule_ptr->target_port, + rule_ptr->private_ip, + rule_ptr->private_port, + rule_ptr->pdn_index, + rule_ptr->ip_chksum, + rule_ptr->tcp_udp_chksum, + rule_ptr->redirect, + rule_ptr->enable, + rule_ptr->time_stamp, + rule_ptr->indx_tbl_entry, + rule_ptr->prev_index, + rule_ptr->next_index); + } + + return buf_ptr; +} + +static inline const char *ipa3_nat_mem_in_as_str( + enum ipa3_nat_mem_in nmi) +{ + switch (nmi) { + case IPA_NAT_MEM_IN_DDR: + return "IPA_NAT_MEM_IN_DDR"; + case IPA_NAT_MEM_IN_SRAM: + return "IPA_NAT_MEM_IN_SRAM"; + default: + break; + } + return "???"; +} + +static inline char *ipa_ioc_v4_nat_init_as_str( + struct ipa_ioc_v4_nat_init *ptr, + char *buf, + uint32_t buf_sz) +{ + if (ptr && buf && buf_sz) { + snprintf( + buf, buf_sz, + "V4 NAT INIT: tbl_index(0x%02X) ipv4_rules_offset(0x%08X) expn_rules_offset(0x%08X) index_offset(0x%08X) index_expn_offset(0x%08X) table_entries(0x%04X) expn_table_entries(0x%04X) ip_addr(0x%08X)", + ptr->tbl_index, + ptr->ipv4_rules_offset, + ptr->expn_rules_offset, + ptr->index_offset, + ptr->index_expn_offset, + ptr->table_entries, + ptr->expn_table_entries, + ptr->ip_addr); + } + return buf; +} + +/* + IPA NAT Flag is interpreted as follows + --------------------------------------------------- + | EN |FIN/RST| S | IPv4 uC activation index | + | [15] | [14] | [13] | [12:0] | + --------------------------------------------------- +*/ +typedef struct { + uint32_t uc_activation_index:13; + uint32_t s:1; + uint32_t redirect:1; + uint32_t enable:1; +} ipa_nat_flags; + +struct ipa_nat_indx_tbl_rule { + uint16_t tbl_entry; + uint16_t next_index; +}; + +struct ipa_nat_indx_tbl_meta_info { + uint16_t prev_index; +}; + +struct ipa_nat_ip4_table_cache { + uint32_t public_addr; + ipa_mem_descriptor mem_desc; + ipa_table table; + ipa_table index_table; + struct ipa_nat_indx_tbl_meta_info *index_expn_table_meta; + ipa_table_dma_cmd_helper table_dma_cmd_helpers[IPA_NAT_TABLE_DMA_CMD_MAX]; +}; + +struct ipa_nat_cache { + ipa_descriptor* ipa_desc; + struct ipa_nat_ip4_table_cache ip4_tbl[IPA_NAT_MAX_IP4_TBLS]; + uint8_t table_cnt; + enum ipa3_nat_mem_in nmi; +}; + +int ipa_nati_add_ipv4_tbl( + uint32_t public_ip_addr, + const char *mem_type_ptr, + uint16_t number_of_entries, + uint32_t *table_hanle); + +int ipa_nati_del_ipv4_table(uint32_t tbl_hdl); + +int ipa_nati_query_timestamp(uint32_t tbl_hdl, + uint32_t rule_hdl, + uint32_t *time_stamp); + +int ipa_nati_modify_pdn(struct ipa_ioc_nat_pdn_entry *entry); + +int ipa_nati_get_pdn_index(uint32_t public_ip, uint8_t *pdn_index); + +int ipa_nati_alloc_pdn(ipa_nat_pdn_entry *pdn_info, uint8_t *pdn_index); + +int ipa_nati_get_pdn_cnt(void); + +int ipa_nati_dealloc_pdn(uint8_t pdn_index); + +int ipa_nati_add_ipv4_rule(uint32_t tbl_hdl, + const ipa_nat_ipv4_rule *clnt_rule, + uint32_t *rule_hdl); + +int ipa_nati_del_ipv4_rule(uint32_t tbl_hdl, + uint32_t rule_hdl); + +int ipa_nati_get_sram_size( + uint32_t* size_ptr); + +int ipa_nati_clear_ipv4_tbl( + uint32_t tbl_hdl ); + +int ipa_nati_copy_ipv4_tbl( + uint32_t src_tbl_hdl, + uint32_t dst_tbl_hdl, + ipa_table_walk_cb copy_cb ); + +typedef enum +{ + USE_NAT_TABLE = 0, + USE_INDEX_TABLE = 1, + + USE_MAX +} WhichTbl2Use; + +#define VALID_WHICHTBL2USE(w) \ + ( (w) >= USE_NAT_TABLE && (w) < USE_MAX ) + +int ipa_nati_walk_ipv4_tbl( + uint32_t tbl_hdl, + WhichTbl2Use which, + ipa_table_walk_cb walk_cb, + void* arb_data_ptr ); + +/* + * The following used for retrieving table stats. + */ +typedef struct +{ + enum ipa3_nat_mem_in nmi; + uint32_t tot_ents; + uint32_t tot_base_ents; + uint32_t tot_base_ents_filled; + uint32_t tot_expn_ents; + uint32_t tot_expn_ents_filled; + uint32_t tot_chains; + uint32_t min_chain_len; + uint32_t max_chain_len; + float avg_chain_len; +} ipa_nati_tbl_stats; + +int ipa_nati_ipv4_tbl_stats( + uint32_t tbl_hdl, + ipa_nati_tbl_stats* nat_stats_ptr, + ipa_nati_tbl_stats* idx_stats_ptr ); + +int ipa_nati_vote_clock( + enum ipa_app_clock_vote_type vote_type ); + +int ipa_NATI_add_ipv4_tbl( + enum ipa3_nat_mem_in nmi, + uint32_t public_ip_addr, + uint16_t number_of_entries, + uint32_t* tbl_hdl); + +int ipa_NATI_del_ipv4_table( + uint32_t tbl_hdl); + +int ipa_NATI_clear_ipv4_tbl( + uint32_t tbl_hdl ); + +int ipa_NATI_walk_ipv4_tbl( + uint32_t tbl_hdl, + WhichTbl2Use which, + ipa_table_walk_cb walk_cb, + void* arb_data_ptr ); + +int ipa_NATI_ipv4_tbl_stats( + uint32_t tbl_hdl, + ipa_nati_tbl_stats* nat_stats_ptr, + ipa_nati_tbl_stats* idx_stats_ptr ); + +int ipa_NATI_query_timestamp( + uint32_t tbl_hdl, + uint32_t rule_hdl, + uint32_t* time_stamp); + +int ipa_NATI_add_ipv4_rule( + uint32_t tbl_hdl, + const ipa_nat_ipv4_rule* clnt_rule, + uint32_t* rule_hdl); + +int ipa_NATI_del_ipv4_rule( + uint32_t tbl_hdl, + uint32_t rule_hdl); + +int ipa_NATI_post_ipv4_init_cmd( + uint32_t tbl_hdl ); + +#endif /* #ifndef IPA_NAT_DRVI_H */ diff --git a/qcom/opensource/dataipa/ipanat/inc/ipa_nat_map.h b/qcom/opensource/dataipa/ipanat/inc/ipa_nat_map.h new file mode 100644 index 0000000000..192a9bf342 --- /dev/null +++ b/qcom/opensource/dataipa/ipanat/inc/ipa_nat_map.h @@ -0,0 +1,107 @@ +/* + * Copyright (c) 2019 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#if !defined(_IPA_NATI_MAP_H_) +# define _IPA_NATI_MAP_H_ + +#include + +# ifdef __cplusplus +extern "C" +{ +# endif /* __cplusplus */ + +/* Used below */ +#define MAKE_AS_STR_CASE(v) case v: return #v + +/* + * The following is used to describe which map to use. + * + * PLEASE KEEP THE FOLLOWING IN SYNC WITH ipa_which_map_as_str() + * BELOW. + */ +typedef enum +{ + MAP_NUM_00 = 0, + MAP_NUM_01 = 1, + MAP_NUM_02 = 2, + MAP_NUM_03 = 3, + + MAP_NUM_99 = 4, + + MAP_NUM_MAX +} ipa_which_map; + +#define VALID_IPA_USE_MAP(w) \ + ( (w) >= MAP_NUM_00 || (w) < MAP_NUM_MAX ) + +/* KEEP THE FOLLOWING IN SYNC WITH ABOVE. */ +static inline const char* ipa_which_map_as_str( + ipa_which_map w ) +{ + switch ( w ) + { + MAKE_AS_STR_CASE(MAP_NUM_00); + MAKE_AS_STR_CASE(MAP_NUM_01); + MAKE_AS_STR_CASE(MAP_NUM_02); + MAKE_AS_STR_CASE(MAP_NUM_03); + + MAKE_AS_STR_CASE(MAP_NUM_99); + default: + break; + } + + return "???"; +} + +int ipa_nat_map_add( + ipa_which_map which, + uint32_t key, + uint32_t val ); + +int ipa_nat_map_find( + ipa_which_map which, + uint32_t key, + uint32_t* val_ptr ); + +int ipa_nat_map_del( + ipa_which_map which, + uint32_t key, + uint32_t* val_ptr ); + +int ipa_nat_map_clear( + ipa_which_map which ); + +int ipa_nat_map_dump( + ipa_which_map which ); + +# ifdef __cplusplus +} +# endif /* __cplusplus */ + +#endif /* #if !defined(_IPA_NATI_MAP_H_) */ diff --git a/qcom/opensource/dataipa/ipanat/inc/ipa_nat_statemach.h b/qcom/opensource/dataipa/ipanat/inc/ipa_nat_statemach.h new file mode 100644 index 0000000000..56d009469c --- /dev/null +++ b/qcom/opensource/dataipa/ipanat/inc/ipa_nat_statemach.h @@ -0,0 +1,297 @@ +/* + * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#if !defined(_IPA_NAT_STATEMACH_H_) +# define _IPA_NAT_STATEMACH_H_ + +typedef uintptr_t arb_t; + +#define MAKE_AS_STR_CASE(v) case v: return #v + +/******************************************************************************/ +/** + * The following enum represents the states that a nati object can be + * in. + */ +typedef enum { + NATI_STATE_NULL = 0, + NATI_STATE_DDR_ONLY = 1, /* NAT in DDR only (traditional) */ + NATI_STATE_SRAM_ONLY = 2, /* NAT in SRAM only (new) */ + NATI_STATE_HYBRID = 3, /* NAT simultaneously in both SRAM/DDR */ + NATI_STATE_HYBRID_DDR = 4, /* NAT transitioned from SRAM to DDR */ + + NATI_STATE_LAST +} ipa_nati_state; + +/* KEEP THE FOLLOWING IN SYNC WITH ABOVE. */ +static inline const char* ipa_nati_state_as_str( + ipa_nati_state s ) +{ + switch ( s ) + { + MAKE_AS_STR_CASE(NATI_STATE_NULL); + MAKE_AS_STR_CASE(NATI_STATE_DDR_ONLY); + MAKE_AS_STR_CASE(NATI_STATE_SRAM_ONLY); + MAKE_AS_STR_CASE(NATI_STATE_HYBRID); + MAKE_AS_STR_CASE(NATI_STATE_HYBRID_DDR); + MAKE_AS_STR_CASE(NATI_STATE_LAST); + + default: + break; + } + + return "???"; +} + +# undef strcasesame +# define strcasesame(a, b) (!strcasecmp(a, b)) + +static inline ipa_nati_state mem_type_str_to_ipa_nati_state( + const char* str ) +{ + if ( str ) { + if (strcasesame(str, "HYBRID" )) + return NATI_STATE_HYBRID; + if (strcasesame(str, "SRAM" )) + return NATI_STATE_SRAM_ONLY; + } + return NATI_STATE_DDR_ONLY; +} + +/******************************************************************************/ +/** + * The following enum represents the API triggers that may or may not + * cause a nati object to transition through its various allowable + * states defined in ipa_nati_state above. + */ +typedef enum { + NATI_TRIG_NULL = 0, + NATI_TRIG_ADD_TABLE = 1, + NATI_TRIG_DEL_TABLE = 2, + NATI_TRIG_CLR_TABLE = 3, + NATI_TRIG_WLK_TABLE = 4, + NATI_TRIG_TBL_STATS = 5, + NATI_TRIG_ADD_RULE = 6, + NATI_TRIG_DEL_RULE = 7, + NATI_TRIG_TBL_SWITCH = 8, + NATI_TRIG_GOTO_DDR = 9, + NATI_TRIG_GOTO_SRAM = 10, + NATI_TRIG_GET_TSTAMP = 11, + + NATI_TRIG_LAST +} ipa_nati_trigger; + +/******************************************************************************/ +/** + * The following structure used to keep switch stats. + */ +typedef struct +{ + uint32_t pass; + uint32_t fail; +} nati_switch_stats; + +/******************************************************************************/ +/** + * The following structure used to direct map usage. + * + * Maps are needed to map rule handles..orig to new and new to orig. + * See comments in ipa_nat_statemach.c on this topic... + */ +typedef struct +{ + uint32_t orig2new_map; + uint32_t new2orig_map; +} nati_map_pair; + +/******************************************************************************/ +/** + * The following is a nati object that will maintain state relative to + * various API calls. + */ +typedef struct +{ + ipa_nati_state prev_state; + ipa_nati_state curr_state; + bool hold_state; + ipa_nati_state state_to_hold; + uint32_t ddr_tbl_hdl; + uint32_t sram_tbl_hdl; + uint32_t tot_slots_in_sram; + uint32_t back_to_sram_thresh; + /* + * tot_rules_in_table[0] for ddr, and + * tot_rules_in_table[1] for sram + */ + uint32_t tot_rules_in_table[2]; + /* + * map_pairs[0] for ddr, and + * map_pairs[1] for sram + */ + nati_map_pair map_pairs[2]; + /* + * sw_stats[0] for ddr, and + * sw_stats[1] for sram + */ + nati_switch_stats sw_stats[2]; +} ipa_nati_obj; + +/* + * For use with the arrays above..in ipa_nati_obj... + */ +#undef DDR_SUB +#undef SRAM_SUB + +#define DDR_SUB 0 +#define SRAM_SUB 1 + +#undef BACK2_UNSTARTED_STATE +#define BACK2_UNSTARTED_STATE() \ + nati_obj.prev_state = nati_obj.curr_state = NATI_STATE_NULL; + +#undef IN_UNSTARTED_STATE +#define IN_UNSTARTED_STATE() \ + ( nati_obj.prev_state == NATI_STATE_NULL ) + +#undef IN_HYBRID_STATE +#define IN_HYBRID_STATE() \ + ( nati_obj.curr_state == NATI_STATE_HYBRID || \ + nati_obj.curr_state == NATI_STATE_HYBRID_DDR ) + +#undef COMPATIBLE_NMI_4SWITCH +#define COMPATIBLE_NMI_4SWITCH(n) \ + ( (n) == IPA_NAT_MEM_IN_SRAM && nati_obj.curr_state == NATI_STATE_HYBRID_DDR ) || \ + ( (n) == IPA_NAT_MEM_IN_DDR && nati_obj.curr_state == NATI_STATE_HYBRID ) || \ + ( (n) == IPA_NAT_MEM_IN_DDR && nati_obj.curr_state == NATI_STATE_DDR_ONLY ) || \ + ( (n) == IPA_NAT_MEM_IN_SRAM && nati_obj.curr_state == NATI_STATE_SRAM_ONLY ) + +#undef GEN_HOLD_STATE +#define GEN_HOLD_STATE() \ + ( ! IN_HYBRID_STATE() ) ? nati_obj.curr_state : \ + (nati_obj.curr_state == NATI_STATE_HYBRID) ? NATI_STATE_SRAM_ONLY : \ + NATI_STATE_DDR_ONLY + +#undef SRAM_CURRENTLY_ACTIVE +#define SRAM_CURRENTLY_ACTIVE() \ + ( nati_obj.curr_state == NATI_STATE_SRAM_ONLY || \ + nati_obj.curr_state == NATI_STATE_HYBRID ) + +#define SRAM_TO_BE_ACCESSED(t) \ + ( SRAM_CURRENTLY_ACTIVE() || \ + (t) == NATI_TRIG_GOTO_SRAM || \ + (t) == NATI_TRIG_TBL_SWITCH ) + +/* + * NOTE: The exclusion of timestamp retrieval and table creation + * below. + * + * Why? + * + * In re timestamp: + * + * Because timestamp retrieval institutes too many repetitive + * accesses, hence would lead to too many successive votes. Instead, + * it will be handled differently and in the app layer above. + * + * In re table creation: + * + * Because it can't be known, apriori, whether or not sram is + * really available for use. Instead, we'll move table creation + * voting to a place where we know sram is available. + */ +#undef VOTE_REQUIRED +#define VOTE_REQUIRED(t) \ + ( SRAM_TO_BE_ACCESSED(t) && \ + (t) != NATI_TRIG_GET_TSTAMP && \ + (t) != NATI_TRIG_ADD_TABLE ) + +/******************************************************************************/ +/** + * A helper macro for changing a nati object's state... + */ +# undef SET_NATIOBJ_STATE +# define SET_NATIOBJ_STATE(x, s) { \ + (x)->prev_state = (x)->curr_state; \ + (x)->curr_state = s; \ + } + +/******************************************************************************/ +/** + * A function signature for a state/trigger callback function... + */ +typedef int (*nati_statemach_cb)( + ipa_nati_obj* nati_obj_ptr, + ipa_nati_trigger trigger, + arb_t* arb_data_ptr ); + +/******************************************************************************/ +/** + * A structure for relating state to trigger callbacks. + */ +typedef struct +{ + ipa_nati_state state; + ipa_nati_trigger trigger; + nati_statemach_cb sm_cb; + const char* state_as_str; + const char* trigger_as_str; + const char* sm_cb_as_str; +} nati_statemach_tuple; + +#undef SM_ROW +#define SM_ROW(s, t, f) \ + { s, t, f, #s, #t, #f } + +/******************************************************************************/ +/** + * FUNCTION: ipa_nati_statemach + * + * PARAMS: + * + * @nati_obj_ptr (IN) A pointer to an initialized nati object + * + * @trigger (IN) The trigger to run through the state machine + * + * @arb_data_ptr (IN) Anything you like. Will be passed, untouched, + * to the state/trigger callback function. + * + * DESCRIPTION: + * + * This function allows a nati object and a trigger to be run + * through the state machine. + * + * RETURNS: + * + * zero on success, otherwise non-zero + */ +int ipa_nati_statemach( + ipa_nati_obj* nati_obj_ptr, + ipa_nati_trigger trigger, + arb_t* arb_data_ptr ); + +#endif /* #if !defined(_IPA_NAT_STATEMACH_H_) */ diff --git a/qcom/opensource/dataipa/ipanat/inc/ipa_nat_utils.h b/qcom/opensource/dataipa/ipanat/inc/ipa_nat_utils.h new file mode 100644 index 0000000000..22b99c4287 --- /dev/null +++ b/qcom/opensource/dataipa/ipanat/inc/ipa_nat_utils.h @@ -0,0 +1,201 @@ +/* + * Copyright (c) 2013, 2018-2020 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Changes from Qualcomm Innovation Center are provided under the following license: + * + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * * Neither the name of Qualcomm Innovation Center, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + */ +#ifndef IPA_NAT_UTILS_H +#define IPA_NAT_UTILS_H + +#include +#include +#include +#include +#include +#include + +#ifndef FALSE +#define FALSE 0 +#endif + +#ifndef TRUE +#define TRUE 1 +#endif + +#define MAX_DMA_ENTRIES_FOR_ADD 4 +#define MAX_DMA_ENTRIES_FOR_DEL 3 + +#if !defined(MSM_IPA_TESTS) && !defined(FEATURE_IPA_ANDROID) +#ifdef USE_GLIB +#include +#define strlcpy g_strlcpy +#else +size_t strlcpy(char* dst, const char* src, size_t size); +#endif +#endif + +#define IPAERR(fmt, ...) printf("ERR: %s:%d %s() " fmt, __FILE__, __LINE__, __FUNCTION__, ##__VA_ARGS__); + +#define IPAINFO(fmt, ...) printf("INFO: %s:%d %s() " fmt, __FILE__, __LINE__, __FUNCTION__, ##__VA_ARGS__); + +#define IPAWARN(fmt, ...) printf("WARN: %s:%d %s() " fmt, __FILE__, __LINE__, __FUNCTION__, ##__VA_ARGS__); + +#ifdef NAT_DEBUG +#define IPADBG(fmt, ...) printf("%s:%d %s() " fmt, __FILE__, __LINE__, __FUNCTION__, ##__VA_ARGS__); +#else +#define IPADBG(fmt, ...) +#endif + +typedef struct +{ + int fd; + enum ipa_hw_type ver; +} ipa_descriptor; + +ipa_descriptor* ipa_descriptor_open(void); + +void ipa_descriptor_close( + ipa_descriptor*); + +void ipa_read_debug_info( + const char* debug_file_path); + +static inline char* prep_ioc_nat_dma_cmd_4print( + struct ipa_ioc_nat_dma_cmd* cmd_ptr, + char* buf_ptr, + uint32_t buf_sz ) +{ + uint32_t i, len, buf_left; + + if ( cmd_ptr && buf_ptr && buf_sz ) + { + snprintf( + buf_ptr, + buf_sz, + "NAT_DMA_CMD: mem_type(%u) entries(%u) ", + cmd_ptr->mem_type, + cmd_ptr->entries); + + for ( i = 0; i < cmd_ptr->entries; i++ ) + { + len = strlen(buf_ptr); + + buf_left = buf_sz - len; + + if ( buf_left > 0 && buf_left < buf_sz ) + { + snprintf( + buf_ptr + len, + buf_left, + "[%u](table_index(0x%02X) base_addr(0x%02X) offset(0x%08X) data(0x%04X)) ", + i, + cmd_ptr->dma[i].table_index, + cmd_ptr->dma[i].base_addr, + cmd_ptr->dma[i].offset, + (uint32_t) cmd_ptr->dma[i].data); + } + } + } + + return buf_ptr; +} + +#undef NANOS_PER_SEC +#undef MICROS_PER_SEC +#undef MILLIS_PER_SEC + +#define NANOS_PER_SEC 1000000000 +#define MICROS_PER_SEC 1000000 +#define MILLIS_PER_SEC 1000 + +/** + * A macro for converting seconds to nanoseconds... + */ +#define SECS2NanSECS(x) ((x) * NANOS_PER_SEC) + +/** + * A macro for converting seconds to microseconds... + */ +#define SECS2MicSECS(x) ((x) * MICROS_PER_SEC) + +/** + * A macro for converting seconds to milliseconds... + */ +#define SECS2MilSECS(x) ((x) * MILLIS_PER_SEC) + +/******************************************************************************/ + +typedef enum +{ + TimeAsNanSecs = 0, + TimeAsMicSecs = 1, + TimeAsMilSecs = 2 +} TimeAs_t; + +#undef VALID_TIMEAS +#define VALID_TIMEAS(ta) \ + ( (ta) == TimeAsNanSecs || \ + (ta) == TimeAsMicSecs || \ + (ta) == TimeAsMilSecs ) + +int currTimeAs( + TimeAs_t timeAs, + uint64_t* valPtr ); + +#endif /* IPA_NAT_UTILS_H */ diff --git a/qcom/opensource/dataipa/ipanat/inc/ipa_table.h b/qcom/opensource/dataipa/ipanat/inc/ipa_table.h new file mode 100644 index 0000000000..e394a45141 --- /dev/null +++ b/qcom/opensource/dataipa/ipanat/inc/ipa_table.h @@ -0,0 +1,323 @@ +/* + * Copyright (c) 2018-2020 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef IPA_TABLE_H +#define IPA_TABLE_H + +#include +#include +#include + +#define IPA_TABLE_MAX_ENTRIES 5120 + +#define IPA_TABLE_INVALID_ENTRY 0x0 + +#undef VALID_INDEX +#define VALID_INDEX(idx) \ + ( (idx) != IPA_TABLE_INVALID_ENTRY ) + +#undef VALID_RULE_HDL +#define VALID_RULE_HDL(hdl) \ + ( (hdl) != IPA_TABLE_INVALID_ENTRY ) + +#undef GOTO_REC +#define GOTO_REC(tbl, rec_idx) \ + ( (tbl)->table_addr + ((rec_idx) * (tbl)->entry_size) ) + +typedef enum +{ + IPA_NAT_BASE_TBL = 0, + IPA_NAT_EXPN_TBL = 1, + IPA_NAT_INDX_TBL = 2, + IPA_NAT_INDEX_EXPN_TBL = 3, + IPA_IPV6CT_BASE_TBL = 4, + IPA_IPV6CT_EXPN_TBL = 5, +} ipa_table_dma_type; + +#define VALID_IPA_TABLE_DMA_TYPE(t) \ + ( (t) >= IPA_NAT_BASE_TBL && (t) <= IPA_IPV6CT_EXPN_TBL ) + +/* + * --------- NAT Rule Handle Entry ID structure --------- + * + * +-----------+-----------+------------------+----------------+ + * | 1 bit | 2 bits | 12 bits | 1 bit | + * +-----------+-----------+------------------+----------------+ + * | 0 - DDR | reserved | index into table | 0 - base | + * | 1 - SRAM | | | 1 - expansion | + * +-----------+-----------+------------------+----------------+ + */ +#define IPA_TABLE_TYPE_BITS 0x00000001 +#define IPA_TABLE_TYPE_MASK 0x00000001 +#define IPA_TABLE_INDX_MASK 0x00000FFF +#define IPA_TABLE_TYPE_MEM_SHIFT 15 + +#undef BREAK_RULE_HDL +#define BREAK_RULE_HDL(tbl, hdl, mt, iet, indx) \ + do { \ + mt = ((hdl) >> IPA_TABLE_TYPE_MEM_SHIFT) & IPA_TABLE_TYPE_MASK; \ + iet = (hdl) & IPA_TABLE_TYPE_MASK; \ + indx = ((hdl) >> IPA_TABLE_TYPE_BITS) & IPA_TABLE_INDX_MASK; \ + indx += (iet) ? tbl->table_entries : 0; \ + /*IPADBG("hdl(%u) -> mt(%u) iet(%u) indx(%u)\n", hdl, mt, iet, indx);*/ \ + } while ( 0 ) + +typedef int (*entry_validity_checker)( + void* entry); + +typedef uint16_t (*entry_next_index_getter)( + void* entry); + +typedef uint16_t (*entry_prev_index_getter)( + void* entry, + uint16_t entry_index, + void* meta, + uint16_t base_table_size); + +typedef void (*entry_prev_index_setter)( + void* entry, + uint16_t entry_index, + uint16_t prev_index, + void* meta, + uint16_t base_table_size); + +typedef int (*entry_head_inserter)( + void* entry, + void* user_data, + uint16_t* dma_command_data); + +typedef int (*entry_tail_inserter)( + void* entry, + void* user_data); + +typedef uint16_t (*entry_delete_head_dma_command_data_getter)( + void* head, + void* next_entry); + +typedef struct +{ + entry_validity_checker entry_is_valid; + entry_next_index_getter entry_get_next_index; + entry_prev_index_getter entry_get_prev_index; + entry_prev_index_setter entry_set_prev_index; + entry_head_inserter entry_head_insert; + entry_tail_inserter entry_tail_insert; + entry_delete_head_dma_command_data_getter + entry_get_delete_head_dma_command_data; +} ipa_table_entry_interface; + +typedef enum +{ + HELP_UPDATE_HEAD = 0, + HELP_UPDATE_ENTRY = 1, + HELP_DELETE_HEAD = 2, + + HELP_UPDATE_MAX, +} dma_help_type; + +#undef VALID_DMA_HELP_TYPE +#define VALID_DMA_HELP_TYPE(t) \ + ( (t) >= HELP_UPDATE_HEAD && (t) < HELP_UPDATE_MAX ) + +typedef struct +{ + uint32_t offset; + ipa_table_dma_type table_type; + ipa_table_dma_type expn_table_type; + uint8_t table_indx; +} ipa_table_dma_cmd_helper; + +typedef struct +{ + char name[IPA_RESOURCE_NAME_MAX]; + + enum ipa3_nat_mem_in nmi; + + int entry_size; + + uint16_t table_entries; + uint16_t expn_table_entries; + uint32_t tot_tbl_ents; + + uint8_t* table_addr; + uint8_t* expn_table_addr; + + uint16_t cur_tbl_cnt; + uint16_t cur_expn_tbl_cnt; + + ipa_table_entry_interface* entry_interface; + + ipa_table_dma_cmd_helper* dma_help[HELP_UPDATE_MAX]; + + void* meta; + int meta_entry_size; +} ipa_table; + +typedef struct +{ + uint16_t prev_index; + void* prev_entry; + + uint16_t curr_index; + void* curr_entry; + + uint16_t next_index; + void* next_entry; +} ipa_table_iterator; + + +void ipa_table_init( + ipa_table* table, + const char* table_name, + enum ipa3_nat_mem_in nmi, + int entry_size, + void* meta, + int meta_entry_size, + ipa_table_entry_interface* entry_interface); + +int ipa_table_calculate_entries_num( + ipa_table* table, + uint16_t number_of_entries, + enum ipa3_nat_mem_in nmi); + +int ipa_table_calculate_size( + ipa_table* table); + +uint8_t* ipa_table_calculate_addresses( + ipa_table* table, + uint8_t* base_addr); + +void ipa_table_reset( + ipa_table* table); + +int ipa_table_add_entry( + ipa_table* table, + void* user_data, + uint16_t* index, + uint32_t* rule_hdl, + struct ipa_ioc_nat_dma_cmd* cmd); + +void ipa_table_create_delete_command( + ipa_table* table, + struct ipa_ioc_nat_dma_cmd* cmd, + ipa_table_iterator* iterator); + +void ipa_table_delete_entry( + ipa_table* table, + ipa_table_iterator* iterator, + uint8_t is_prev_empty); + +void ipa_table_erase_entry( + ipa_table* table, + uint16_t index); + +int ipa_table_get_entry( + ipa_table* table, + uint32_t entry_handle, + void** entry, + uint16_t* entry_index); + +void* ipa_table_get_entry_by_index( + ipa_table* table, + uint16_t index); + +void ipa_table_dma_cmd_helper_init( + ipa_table_dma_cmd_helper* dma_cmd_helper, + uint8_t table_indx, + ipa_table_dma_type table_type, + ipa_table_dma_type expn_table_type, + uint32_t offset); + +void ipa_table_dma_cmd_generate( + ipa_table_dma_cmd_helper* dma_cmd_helper, + uint8_t is_expn, + uint32_t entry_offset, + uint16_t data, + struct ipa_ioc_nat_dma_cmd* cmd); + +int ipa_table_iterator_init( + ipa_table_iterator* iterator, + ipa_table* table, + void* curr_entry, + uint16_t curr_index); + +int ipa_table_iterator_next( + ipa_table_iterator* iterator, + ipa_table* table); + +int ipa_table_iterator_end( + ipa_table_iterator* iterator, + ipa_table* table, + uint16_t head_index, + void* head); + +int ipa_table_iterator_is_head_with_tail( + ipa_table_iterator* iterator); + +int ipa_calc_num_sram_table_entries( + uint32_t sram_size, + uint32_t table1_ent_size, + uint32_t table2_ent_size, + uint16_t* num_entries_ptr); + +typedef int (*ipa_table_walk_cb)( + ipa_table* table_ptr, + uint32_t rule_hdl, + void* record_ptr, + uint16_t record_index, + void* meta_record_ptr, + uint16_t meta_record_index, + void* arb_data_ptr ); + +typedef enum +{ + WHEN_SLOT_EMPTY = 0, + WHEN_SLOT_FILLED = 1, + + WHEN_SLOT_MAX +} When2Callback; + +#define VALID_WHEN2CALLBACK(w) \ + ( (w) >= WHEN_SLOT_EMPTY && (w) < WHEN_SLOT_MAX ) + +int ipa_table_walk( + ipa_table* table, + uint16_t start_index, + When2Callback when, + ipa_table_walk_cb walk_cb, + void* arb_data_ptr ); + +int ipa_table_add_dma_cmd( + ipa_table* tbl_ptr, + dma_help_type help_type, + void* rec_ptr, + uint16_t rec_index, + uint16_t data_for_entry, + struct ipa_ioc_nat_dma_cmd* cmd_ptr ); + +#endif diff --git a/qcom/opensource/dataipa/ipanat/src/Makefile.am b/qcom/opensource/dataipa/ipanat/src/Makefile.am new file mode 100644 index 0000000000..a96fc3c1e2 --- /dev/null +++ b/qcom/opensource/dataipa/ipanat/src/Makefile.am @@ -0,0 +1,37 @@ +ACLOCAL_AMFLAGS = -I m4 +AUTOMAKE_OPTIONS = foreign + +AM_CFLAGS = -Wall -Wundef -Wstrict-prototypes -Wno-trigraphs -I../inc +#AM_CFLAGS += -g -DDEBUG -DNAT_DEBUG + +common_CFLAGS = -DUSE_GLIB @GLIB_CFLAGS@ +common_LDFLAGS = -lrt @GLIB_LIBS@ + +library_includedir = $(pkgincludedir) + +cpp_sources = ipa_nat_map.cpp + +c_sources = ipa_nat_drv.c \ + ipa_nat_drvi.c \ + ipa_nat_utils.c \ + ipa_table.c \ + ipa_mem_descriptor.c \ + ipa_ipv6ct.c \ + ipa_nat_statemach.c + +library_include_HEADERS = ../inc/ipa_nat_drvi.h \ + ../inc/ipa_nat_drv.h \ + ../inc/ipa_nat_utils.h \ + ../inc/ipa_table.h \ + ../inc/ipa_mem_descriptor.h \ + ../inc/ipa_ipv6ct.h \ + ../inc/ipa_nat_statemach.h \ + ../inc/ipa_nat_map.h + +lib_LTLIBRARIES = libipanat.la +libipanat_la_C = @C@ +libipanat_la_CC = @CC@ +libipanat_la_SOURCES = $(c_sources) $(cpp_sources) +libipanat_la_CFLAGS = $(AM_CFLAGS) $(common_CFLAGS) +libipanat_la_CXXFLAGS = $(AM_CFLAGS) $(common_CPPFLAGS) +libipanat_la_LDFLAGS = -shared $(common_LDFLAGS) -version-info 1:0:0 diff --git a/qcom/opensource/dataipa/ipanat/src/configure.ac b/qcom/opensource/dataipa/ipanat/src/configure.ac new file mode 100644 index 0000000000..3884ac7ac4 --- /dev/null +++ b/qcom/opensource/dataipa/ipanat/src/configure.ac @@ -0,0 +1,85 @@ +# -*- Autoconf -*- +# Process this file with autoconf to produce a configure script. + +AC_PREREQ([2.65]) +AC_INIT(data-ipanat, 1.0.0) +AM_INIT_AUTOMAKE(data-ipanat, 1.0.0) +AC_OUTPUT(Makefile) +AC_CONFIG_SRCDIR([ipa_nat_drv.c]) +AC_CONFIG_HEADERS([config.h]) +AC_CONFIG_MACRO_DIR([m4]) + +# Checks for programs. +AC_PROG_CC +AC_PROG_LIBTOOL +AC_PROG_CXX + +# Checks for libraries. + +AC_ARG_WITH(sanitized-headers, + AS_HELP_STRING([--with-sanitized-headers=DIR], + [Specify the location of the sanitized Linux headers]), + [CPPFLAGS="$CPPFLAGS -idirafter $withval"]) +AM_CONDITIONAL(KERNELMODULES, [test -n -eq 0]) + +AC_ARG_WITH([glib], + AC_HELP_STRING([--with-glib], + [enable glib, building HLOS systems which use glib])) + +if (test "x${with_glib}" = "xyes"); then + AC_DEFINE(ENABLE_USEGLIB, 1, [Define if HLOS systems uses glib]) + PKG_CHECK_MODULES(GTHREAD, gthread-2.0 >= 2.16, dummy=yes, + AC_MSG_ERROR(GThread >= 2.16 is required)) + PKG_CHECK_MODULES(GLIB, glib-2.0 >= 2.16, dummy=yes, + AC_MSG_ERROR(GLib >= 2.16 is required)) + GLIB_CFLAGS="$GLIB_CFLAGS $GTHREAD_CFLAGS" + GLIB_LIBS="$GLIB_LIBS $GTHREAD_LIBS" + AC_SUBST(GLIB_CFLAGS) + AC_SUBST(GLIB_LIBS) +fi + +AM_CONDITIONAL(USE_GLIB, test "x${with_glib}" = "xyes") + +AC_ARG_ENABLE(target, + [AS_HELP_STRING([--enable-target=TARGET], [Specify the target product to build])], + [TARGET=$enableval], + [TARGET=none] +) + +if test "x$TARGET" = "xsdx20"; then + echo "\n UL firewall feature enabled\n" + CPPFLAGS="${CPPFLAGS} -DFEATURE_IPACM_UL_FIREWALL -DFEATURE_IPACM_PER_CLIENT_STATS" + CFLAGS="${CFLAGS} -DFEATURE_IPACM_UL_FIREWALL -DFEATURE_IPACM_PER_CLIENT_STATS" +fi + +if test "x$TARGET" = "xsdxpoorwills"; then + echo "\n UL firewall feature enabled\n" + CPPFLAGS="${CPPFLAGS} -DFEATURE_IPACM_UL_FIREWALL -DFEATURE_IPACM_PER_CLIENT_STATS -DFEATURE_VLAN_MPDN -DFEATURE_L2TP" + CFLAGS="${CFLAGS} -DFEATURE_IPACM_UL_FIREWALL -DFEATURE_IPACM_PER_CLIENT_STATS -DFEATURE_VLAN_MPDN -DFEATURE_L2TP" +fi + +if test "x$TARGET" = "xsdxprairie"; then + echo "\n UL firewall feature enabled\n" + CPPFLAGS="${CPPFLAGS} -DFEATURE_IPACM_UL_FIREWALL -DFEATURE_IPACM_PER_CLIENT_STATS -DFEATURE_VLAN_MPDN" + CFLAGS="${CFLAGS} -DFEATURE_IPACM_UL_FIREWALL -DFEATURE_IPACM_PER_CLIENT_STATS -DFEATURE_VLAN_MPDN" +fi + +if test "x$TARGET" = "xsdxlemur"; then + echo "\n UL firewall feature enabled\n" + CPPFLAGS="${CPPFLAGS} -DFEATURE_IPACM_UL_FIREWALL -DFEATURE_IPACM_PER_CLIENT_STATS -DFEATURE_VLAN_MPDN" + CFLAGS="${CFLAGS} -DFEATURE_IPACM_UL_FIREWALL -DFEATURE_IPACM_PER_CLIENT_STATS -DFEATURE_VLAN_MPDN" +fi +AM_CONDITIONAL(NO_L2TP, test "x$TARGET" = "xsdx20" || test "x$TARGET" = "xsdxpoorwills" || test "x$TARGET" = "xsdxprairie" || test "x$TARGET" = "xsdxlemur") + +# Checks for header files. +AC_CHECK_HEADERS([fcntl.h netinet/in.h sys/ioctl.h unistd.h]) + +# Checks for typedefs, structures, and compiler characteristics. +AC_TYPE_OFF_T + +# Checks for library functions. +AC_FUNC_MALLOC +AC_FUNC_MMAP +AC_CHECK_FUNCS([memset munmap]) + +AC_OUTPUT diff --git a/qcom/opensource/dataipa/ipanat/src/ipa_ipv6ct.c b/qcom/opensource/dataipa/ipanat/src/ipa_ipv6ct.c new file mode 100644 index 0000000000..45e454c4a9 --- /dev/null +++ b/qcom/opensource/dataipa/ipanat/src/ipa_ipv6ct.c @@ -0,0 +1,933 @@ +/* + * Copyright (c) 2018-2020 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Changes from Qualcomm Innovation Center are provided under the following license: + * + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * * Neither the name of Qualcomm Innovation Center, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + */ +#include "ipa_ipv6ct.h" +#include "ipa_ipv6cti.h" + +#include +#include +#include +#include +#include +#include + +#define IPA_IPV6CT_DEBUG_FILE_PATH "/sys/kernel/debug/ipa/ipv6ct" +#define IPA_UC_ACT_DEBUG_FILE_PATH "/sys/kernel/debug/ipa/uc_act_table" +#define IPA_IPV6CT_TABLE_NAME "IPA IPv6CT table" +#define IPA_MAX_DMA_ENTRIES_FOR_ADD 2 +#define IPA_MAX_DMA_ENTRIES_FOR_DEL 2 + +static int ipa_ipv6ct_create_table(ipa_ipv6ct_table* ipv6ct_table, uint16_t number_of_entries, uint8_t table_index); +static int ipa_ipv6ct_destroy_table(ipa_ipv6ct_table* ipv6ct_table); +static void ipa_ipv6ct_create_table_dma_cmd_helpers(ipa_ipv6ct_table* ipv6ct_table, uint8_t table_indx); +static int ipa_ipv6ct_post_init_cmd(ipa_ipv6ct_table* ipv6ct_table, uint8_t tbl_index); +static int ipa_ipv6ct_post_dma_cmd(struct ipa_ioc_nat_dma_cmd* cmd); +static uint16_t ipa_ipv6ct_hash(const ipa_ipv6ct_rule* rule, uint16_t size); +static uint16_t ipa_ipv6ct_xor_segments(uint64_t num); + +static int table_entry_is_valid(void* entry); +static uint16_t table_entry_get_next_index(void* entry); +static uint16_t table_entry_get_prev_index(void* entry, uint16_t entry_index, void* meta, uint16_t base_table_size); +static void table_entry_set_prev_index(void* entry, uint16_t entry_index, uint16_t prev_index, + void* meta, uint16_t base_table_size); +static int table_entry_head_insert(void* entry, void* user_data, uint16_t* dma_command_data); +static int table_entry_tail_insert(void* entry, void* user_data); +static uint16_t table_entry_get_delete_head_dma_command_data(void* head, void* next_entry); + +static ipa_ipv6ct ipv6ct; +static pthread_mutex_t ipv6ct_mutex = PTHREAD_MUTEX_INITIALIZER; + +static ipa_table_entry_interface entry_interface = +{ + table_entry_is_valid, + table_entry_get_next_index, + table_entry_get_prev_index, + table_entry_set_prev_index, + table_entry_head_insert, + table_entry_tail_insert, + table_entry_get_delete_head_dma_command_data +}; + +/** + * ipa_ipv6ct_add_tbl() - Adds a new IPv6CT table + * @number_of_entries: [in] number of IPv6CT entries + * @table_handle: [out] handle of new IPv6CT table + * + * This function creates new IPv6CT table and posts IPv6CT init command to HW + * + * Returns: 0 On Success, negative on failure + */ +int ipa_ipv6ct_add_tbl(uint16_t number_of_entries, uint32_t* table_handle) +{ + int ret; + ipa_ipv6ct_table* ipv6ct_table; + + IPADBG("\n"); + + if (table_handle == NULL || number_of_entries == 0) + { + IPAERR("Invalid parameters table_handle=%pK number_of_entries=%d\n", table_handle, number_of_entries); + return -EINVAL; + } + + *table_handle = 0; + + if (ipv6ct.table_cnt >= IPA_IPV6CT_MAX_TBLS) + { + IPAERR("Can't add addition IPv6 connection tracking table. Maximum %d tables allowed\n", IPA_IPV6CT_MAX_TBLS); + return -EINVAL; + } + + if (!ipv6ct.ipa_desc) + { + ipv6ct.ipa_desc = ipa_descriptor_open(); + if (ipv6ct.ipa_desc == NULL) + { + IPAERR("failed to open IPA driver file descriptor\n"); + return -EIO; + } + } + + if (ipv6ct.ipa_desc->ver < IPA_HW_v4_0) + { + IPAERR("IPv6 connection tracking isn't supported for IPA version %d\n", ipv6ct.ipa_desc->ver); + ret = -EPERM; + goto bail_ipa_desc; + } + + ipv6ct_table = &ipv6ct.tables[ipv6ct.table_cnt]; + ret = ipa_ipv6ct_create_table(ipv6ct_table, number_of_entries, ipv6ct.table_cnt); + if (ret) + { + IPAERR("unable to create ipv6ct table Error: %d\n", ret); + goto bail_ipa_desc; + } + + /* Initialize the ipa hw with ipv6ct table dimensions */ + ret = ipa_ipv6ct_post_init_cmd(ipv6ct_table, ipv6ct.table_cnt); + if (ret) + { + IPAERR("unable to post ipv6ct_init command Error %d\n", ret); + goto bail_ipv6ct_table; + } + + /* Return table handle */ + ++ipv6ct.table_cnt; + *table_handle = ipv6ct.table_cnt; + + IPADBG("Returning table handle 0x%x\n", *table_handle); + return 0; + +bail_ipv6ct_table: + ipa_ipv6ct_destroy_table(ipv6ct_table); +bail_ipa_desc: + if (!ipv6ct.table_cnt) { + ipa_descriptor_close(ipv6ct.ipa_desc); + ipv6ct.ipa_desc = NULL; + } + return ret; +} + +int ipa_ipv6ct_del_tbl(uint32_t table_handle) +{ + ipa_ipv6ct_table* ipv6ct_table; + int ret; + + IPADBG("\n"); + + if (ipv6ct.ipa_desc->ver < IPA_HW_v4_0) + { + IPAERR("IPv6 connection tracking isn't supported for IPA version %d\n", ipv6ct.ipa_desc->ver); + return -EINVAL; + } + + if (table_handle == IPA_TABLE_INVALID_ENTRY || table_handle > IPA_IPV6CT_MAX_TBLS) + { + IPAERR("invalid table handle %d passed\n", table_handle); + return -EINVAL; + } + IPADBG("Passed Table Handle: 0x%x\n", table_handle); + + if (pthread_mutex_lock(&ipv6ct_mutex)) + { + IPAERR("unable to lock the ipv6ct mutex\n"); + return -EINVAL; + } + + ipv6ct_table = &ipv6ct.tables[table_handle - 1]; + if (!ipv6ct_table->mem_desc.valid) + { + IPAERR("invalid table handle %d\n", table_handle); + ret = -EINVAL; + goto unlock; + } + + ret = ipa_ipv6ct_destroy_table(ipv6ct_table); + if (ret) + { + IPAERR("unable to delete IPV6CT table with handle %d\n", table_handle); + goto unlock; + } + + if (!--ipv6ct.table_cnt) { + ipa_descriptor_close(ipv6ct.ipa_desc); + ipv6ct.ipa_desc = NULL; + } + +unlock: + if (pthread_mutex_unlock(&ipv6ct_mutex)) + { + IPAERR("unable to unlock the ipv6ct mutex\n"); + return (ret) ? ret : -EPERM; + } + + IPADBG("return\n"); + return ret; +} + +int ipa_ipv6ct_add_rule(uint32_t table_handle, const ipa_ipv6ct_rule* user_rule, uint32_t* rule_handle) +{ + int ret; + ipa_ipv6ct_table* ipv6ct_table; + uint16_t new_entry_index; + uint32_t new_entry_handle; + uint32_t cmd_sz = sizeof(struct ipa_ioc_nat_dma_cmd) + + (IPA_MAX_DMA_ENTRIES_FOR_ADD * sizeof(struct ipa_ioc_nat_dma_one)); + char cmd_buf[cmd_sz]; + struct ipa_ioc_nat_dma_cmd* cmd; + + IPADBG("\n"); + + if (ipv6ct.ipa_desc->ver < IPA_HW_v4_0) + { + IPAERR("IPv6 connection tracking isn't supported for IPA version %d\n", ipv6ct.ipa_desc->ver); + return -EINVAL; + } + + if (table_handle == IPA_TABLE_INVALID_ENTRY || table_handle > IPA_IPV6CT_MAX_TBLS || + rule_handle == NULL || user_rule == NULL) + { + IPAERR("Invalid parameters table_handle=%d rule_handle=%pK user_rule=%pK\n", + table_handle, rule_handle, user_rule); + return -EINVAL; + } + IPADBG("Passed Table handle: 0x%x\n", table_handle); + + if (user_rule->protocol == IPA_IPV6CT_INVALID_PROTO_FIELD_CMP) + { + IPAERR("invalid parameter protocol=%d\n", user_rule->protocol); + return -EINVAL; + } + + if (pthread_mutex_lock(&ipv6ct_mutex)) + { + IPAERR("unable to lock the ipv6ct mutex\n"); + return -EINVAL; + } + + ipv6ct_table = &ipv6ct.tables[table_handle - 1]; + if (!ipv6ct_table->mem_desc.valid) + { + IPAERR("invalid table handle %d\n", table_handle); + ret = -EINVAL; + goto unlock; + } + + memset(cmd_buf, 0, sizeof(cmd_buf)); + cmd = (struct ipa_ioc_nat_dma_cmd*) cmd_buf; + cmd->entries = 0; + new_entry_index = ipa_ipv6ct_hash(user_rule, ipv6ct_table->table.table_entries - 1); + + ret = ipa_table_add_entry(&ipv6ct_table->table, (void*)user_rule, &new_entry_index, &new_entry_handle, cmd); + if (ret) + { + IPAERR("failed to add a new IPV6CT entry\n"); + goto unlock; + } + + ret = ipa_ipv6ct_post_dma_cmd(cmd); + if (ret) + { + IPAERR("unable to post dma command\n"); + goto bail; + } + + if (pthread_mutex_unlock(&ipv6ct_mutex)) + { + IPAERR("unable to unlock the ipv6ct mutex\n"); + return -EPERM; + } + + *rule_handle = new_entry_handle; + + IPADBG("return\n"); + return 0; + +bail: + ipa_table_erase_entry(&ipv6ct_table->table, new_entry_index); +unlock: + if (pthread_mutex_unlock(&ipv6ct_mutex)) + IPAERR("unable to unlock the ipv6ct mutex\n"); + return ret; +} + +int ipa_ipv6ct_del_rule(uint32_t table_handle, uint32_t rule_handle) +{ + ipa_ipv6ct_table* ipv6ct_table; + ipa_table_iterator table_iterator; + ipa_ipv6ct_hw_entry* entry; + uint32_t cmd_sz = sizeof(struct ipa_ioc_nat_dma_cmd) + + (IPA_MAX_DMA_ENTRIES_FOR_DEL * sizeof(struct ipa_ioc_nat_dma_one)); + char cmd_buf[cmd_sz]; + struct ipa_ioc_nat_dma_cmd* cmd; + uint16_t index; + int ret; + + IPADBG("\n"); + + if (ipv6ct.ipa_desc->ver < IPA_HW_v4_0) + { + IPAERR("IPv6 connection tracking isn't supported for IPA version %d\n", ipv6ct.ipa_desc->ver); + return -EINVAL; + } + + if (table_handle == IPA_TABLE_INVALID_ENTRY || table_handle > IPA_IPV6CT_MAX_TBLS || + rule_handle == IPA_TABLE_INVALID_ENTRY) + { + IPAERR("Invalid parameters table_handle=%d rule_handle=%d\n", table_handle, rule_handle); + return -EINVAL; + } + IPADBG("Passed Table: 0x%x and rule handle 0x%x\n", table_handle, rule_handle); + + if (pthread_mutex_lock(&ipv6ct_mutex)) + { + IPAERR("unable to lock the ipv6ct mutex\n"); + return -EINVAL; + } + + ipv6ct_table = &ipv6ct.tables[table_handle - 1]; + if (!ipv6ct_table->mem_desc.valid) + { + IPAERR("invalid table handle %d\n", table_handle); + ret = -EINVAL; + goto unlock; + } + + ret = ipa_table_get_entry(&ipv6ct_table->table, rule_handle, (void**)&entry, &index); + if (ret) + { + IPAERR("unable to retrive the entry with handle=%d in IPV6CT table with handle=%d\n", + rule_handle, table_handle); + goto unlock; + } + + ret = ipa_table_iterator_init(&table_iterator, &ipv6ct_table->table, entry, index); + if (ret) + { + IPAERR("unable to create iterator which points to the entry index=%d in IPV6CT table with handle=%d\n", + index, table_handle); + goto unlock; + } + + memset(cmd_buf, 0, sizeof(cmd_buf)); + cmd = (struct ipa_ioc_nat_dma_cmd*) cmd_buf; + cmd->entries = 0; + + ipa_table_create_delete_command(&ipv6ct_table->table, cmd, &table_iterator); + + ret = ipa_ipv6ct_post_dma_cmd(cmd); + if (ret) + { + IPAERR("unable to post dma command\n"); + goto unlock; + } + + if (!ipa_table_iterator_is_head_with_tail(&table_iterator)) + { + /* The entry can be deleted */ + uint8_t is_prev_empty = (table_iterator.prev_entry != NULL && + ((ipa_ipv6ct_hw_entry*)table_iterator.prev_entry)->protocol == IPA_IPV6CT_INVALID_PROTO_FIELD_CMP); + ipa_table_delete_entry(&ipv6ct_table->table, &table_iterator, is_prev_empty); + } + +unlock: + if (pthread_mutex_unlock(&ipv6ct_mutex)) + { + IPAERR("unable to unlock the ipv6ct mutex\n"); + return (ret) ? ret : -EPERM; + } + + IPADBG("return\n"); + return ret; +} + +int ipa_ipv6ct_query_timestamp(uint32_t table_handle, uint32_t rule_handle, uint32_t* time_stamp) +{ + int ret; + ipa_ipv6ct_table* ipv6ct_table; + ipa_ipv6ct_hw_entry *entry; + + IPADBG("\n"); + + if (ipv6ct.ipa_desc->ver < IPA_HW_v4_0) + { + IPAERR("IPv6 connection tracking isn't supported for IPA version %d\n", ipv6ct.ipa_desc->ver); + return -EINVAL; + } + + if (table_handle == IPA_TABLE_INVALID_ENTRY || table_handle > IPA_IPV6CT_MAX_TBLS || + rule_handle == IPA_TABLE_INVALID_ENTRY || time_stamp == NULL) + { + IPAERR("invalid parameters passed table_handle=%d rule_handle=%d time_stamp=%pK\n", + table_handle, rule_handle, time_stamp); + return -EINVAL; + } + IPADBG("Passed Table: %d and rule handle %d\n", table_handle, rule_handle); + + if (pthread_mutex_lock(&ipv6ct_mutex)) + { + IPAERR("unable to lock the ipv6ct mutex\n"); + return -EINVAL; + } + + ipv6ct_table = &ipv6ct.tables[table_handle - 1]; + if (!ipv6ct_table->mem_desc.valid) + { + IPAERR("invalid table handle %d\n", table_handle); + ret = -EINVAL; + goto unlock; + } + + ret = ipa_table_get_entry(&ipv6ct_table->table, rule_handle, (void**)&entry, NULL); + if (ret) + { + IPAERR("unable to retrive the entry with handle=%d in IPV6CT table with handle=%d\n", + rule_handle, table_handle); + goto unlock; + } + + *time_stamp = entry->time_stamp; + +unlock: + if (pthread_mutex_unlock(&ipv6ct_mutex)) + { + IPAERR("unable to unlock the ipv6ct mutex\n"); + return (ret) ? ret : -EPERM; + } + + IPADBG("return\n"); + return ret; +} + +/** +* ipv6ct_hash() - Find the index into ipv6ct table +* @rule: [in] an IPv6CT rule +* @size: [in] size of the IPv6CT table +* +* This hash method is used to find the hash index of an entry into IPv6CT table. +* In case of result zero, N-1 will be returned, where N is size of IPv6CT table. +* +* Returns: >0 index into IPv6CT table, negative on failure +*/ +static uint16_t ipa_ipv6ct_hash(const ipa_ipv6ct_rule* rule, uint16_t size) +{ + uint16_t hash = 0; + + IPADBG("src_ipv6_lsb 0x%llx\n", rule->src_ipv6_lsb); + IPADBG("src_ipv6_msb 0x%llx\n", rule->src_ipv6_msb); + IPADBG("dest_ipv6_lsb 0x%llx\n", rule->dest_ipv6_lsb); + IPADBG("dest_ipv6_msb 0x%llx\n", rule->dest_ipv6_msb); + IPADBG("src_port: 0x%x dest_port: 0x%x\n", rule->src_port, rule->dest_port); + IPADBG("protocol: 0x%x size: 0x%x\n", rule->protocol, size); + + hash ^= ipa_ipv6ct_xor_segments(rule->src_ipv6_lsb); + hash ^= ipa_ipv6ct_xor_segments(rule->src_ipv6_msb); + hash ^= ipa_ipv6ct_xor_segments(rule->dest_ipv6_lsb); + hash ^= ipa_ipv6ct_xor_segments(rule->dest_ipv6_msb); + + hash ^= rule->src_port; + hash ^= rule->dest_port; + hash ^= rule->protocol; + + /* + * The size passed to hash function expected be power^2-1, while the actual size is power^2, + * actual_size = size + 1 + */ + hash &= size; + + /* If the hash resulted to zero then set it to maximum value as zero is unused entry in ipv6ct table */ + if (hash == 0) + { + hash = size; + } + + IPADBG("ipa_ipv6ct_hash returning value: %d\n", hash); + return hash; +} + +static uint16_t ipa_ipv6ct_xor_segments(uint64_t num) +{ + const uint64_t mask = 0xffff; + const size_t bits_in_two_byte = 16; + uint16_t ret = 0; + + IPADBG("\n"); + + while (num) + { + ret ^= (uint16_t)(num & mask); + num >>= bits_in_two_byte; + } + + IPADBG("return\n"); + return ret; +} + +static int table_entry_is_valid(void* entry) +{ + ipa_ipv6ct_hw_entry* ipv6ct_entry = (ipa_ipv6ct_hw_entry*)entry; + + IPADBG("\n"); + + return ipv6ct_entry->enable; +} + +static uint16_t table_entry_get_next_index(void* entry) +{ + uint16_t result; + ipa_ipv6ct_hw_entry* ipv6ct_entry = (ipa_ipv6ct_hw_entry*)entry; + + IPADBG("\n"); + + result = ipv6ct_entry->next_index; + + IPADBG("Next entry of %pK is %d\n", entry, result); + return result; +} + +static uint16_t table_entry_get_prev_index(void* entry, uint16_t entry_index, void* meta, uint16_t base_table_size) +{ + uint16_t result; + ipa_ipv6ct_hw_entry* ipv6ct_entry = (ipa_ipv6ct_hw_entry*)entry; + + IPADBG("\n"); + + result = ipv6ct_entry->prev_index; + + IPADBG("Previous entry of %d is %d\n", entry_index, result); + return result; +} + +static void table_entry_set_prev_index(void* entry, uint16_t entry_index, uint16_t prev_index, + void* meta, uint16_t base_table_size) +{ + ipa_ipv6ct_hw_entry* ipv6ct_entry = (ipa_ipv6ct_hw_entry*)entry; + + IPADBG("Previous entry of %d is %d\n", entry_index, prev_index); + + ipv6ct_entry->prev_index = prev_index; + + IPADBG("return\n"); +} + +static int table_entry_copy_from_user(void* entry, void* user_data) +{ + ipa_ipv6ct_hw_entry* ipv6ct_entry = (ipa_ipv6ct_hw_entry*)entry; + const ipa_ipv6ct_rule* user_rule = (const ipa_ipv6ct_rule*)user_data; + + IPADBG("\n"); + + ipv6ct_entry->src_ipv6_lsb = user_rule->src_ipv6_lsb; + ipv6ct_entry->src_ipv6_msb = user_rule->src_ipv6_msb; + ipv6ct_entry->dest_ipv6_lsb = user_rule->dest_ipv6_lsb; + ipv6ct_entry->dest_ipv6_msb = user_rule->dest_ipv6_msb; + ipv6ct_entry->protocol = user_rule->protocol; + ipv6ct_entry->src_port = user_rule->src_port; + ipv6ct_entry->dest_port = user_rule->dest_port; + ipv6ct_entry->ucp = user_rule->ucp; + ipv6ct_entry->uc_activation_index = user_rule->uc_activation_index; + ipv6ct_entry->s = user_rule->s; + + switch (user_rule->direction_settings) + { + case IPA_IPV6CT_DIRECTION_DENY_ALL: + break; + case IPA_IPV6CT_DIRECTION_ALLOW_OUT: + ipv6ct_entry->out_allowed = IPA_IPV6CT_DIRECTION_ALLOW_BIT; + break; + case IPA_IPV6CT_DIRECTION_ALLOW_IN: + ipv6ct_entry->in_allowed = IPA_IPV6CT_DIRECTION_ALLOW_BIT; + break; + case IPA_IPV6CT_DIRECTION_ALLOW_ALL: + ipv6ct_entry->out_allowed = IPA_IPV6CT_DIRECTION_ALLOW_BIT; + ipv6ct_entry->in_allowed = IPA_IPV6CT_DIRECTION_ALLOW_BIT; + break; + default: + IPAERR("wrong value for IPv6CT direction setting parameter %d\n", user_rule->direction_settings); + return -EINVAL; + } + + IPADBG("return\n"); + return 0; +} + +static int table_entry_head_insert(void* entry, void* user_data, uint16_t* dma_command_data) +{ + int ret; + + IPADBG("\n"); + + ret = table_entry_copy_from_user(entry, user_data); + if (ret) + { + IPAERR("unable to copy from user a new entry\n"); + return ret; + } + + *dma_command_data = 0; + ((ipa_ipv6ct_flags*)dma_command_data)->enable = IPA_IPV6CT_FLAG_ENABLE_BIT; + + IPADBG("return\n"); + return 0; +} + +static int table_entry_tail_insert(void* entry, void* user_data) +{ + int ret; + + IPADBG("\n"); + + ret = table_entry_copy_from_user(entry, user_data); + if (ret) + { + IPAERR("unable to copy from user a new entry\n"); + return ret; + } + + ((ipa_ipv6ct_hw_entry*)entry)->enable = IPA_IPV6CT_FLAG_ENABLE_BIT; + + IPADBG("return\n"); + return 0; +} + +static uint16_t table_entry_get_delete_head_dma_command_data(void* head, void* next_entry) +{ + IPADBG("\n"); + return IPA_IPV6CT_INVALID_PROTO_FIELD_VALUE; +} + +/** + * ipa_ipv6ct_create_table() - Creates a new IPv6CT table + * @ipv6ct_table: [in] IPv6CT table + * @number_of_entries: [in] number of IPv6CT entries + * @table_index: [in] the index of the IPv6CT table + * + * This function creates new IPv6CT table: + * - Initializes table, memory descriptor and table_dma_cmd_helpers structures + * - Allocates, maps and clears the memory for table + * + * Returns: 0 On Success, negative on failure + */ +static int ipa_ipv6ct_create_table(ipa_ipv6ct_table* ipv6ct_table, uint16_t number_of_entries, uint8_t table_index) +{ + int ret, size; + + IPADBG("\n"); + + ipa_table_init( + &ipv6ct_table->table, IPA_IPV6CT_TABLE_NAME, IPA_NAT_MEM_IN_DDR, + sizeof(ipa_ipv6ct_hw_entry), NULL, 0, &entry_interface); + + ret = ipa_table_calculate_entries_num( + &ipv6ct_table->table, number_of_entries, IPA_NAT_MEM_IN_DDR); + + if (ret) + { + IPAERR("unable to calculate number of entries in ipv6ct table %d, while required by user %d\n", + table_index, number_of_entries); + return ret; + } + + size = ipa_table_calculate_size(&ipv6ct_table->table); + IPADBG("IPv6CT table size: %d\n", size); + + ipa_mem_descriptor_init( + &ipv6ct_table->mem_desc, + IPA_IPV6CT_DEV_NAME, + size, + table_index, + IPA_IOC_ALLOC_IPV6CT_TABLE, + IPA_IOC_DEL_IPV6CT_TABLE, + false); /* false here means don't consider using sram */ + + ret = ipa_mem_descriptor_allocate_memory( + &ipv6ct_table->mem_desc, + ipv6ct.ipa_desc->fd); + + if (ret) + { + IPAERR("unable to allocate ipv6ct memory descriptor Error: %d\n", ret); + goto bail; + } + + ipa_table_calculate_addresses(&ipv6ct_table->table, ipv6ct_table->mem_desc.base_addr); + + ipa_table_reset(&ipv6ct_table->table); + + ipa_ipv6ct_create_table_dma_cmd_helpers(ipv6ct_table, table_index); + + IPADBG("return\n"); + return 0; + +bail: + memset(ipv6ct_table, 0, sizeof(*ipv6ct_table)); + return ret; +} + +static int ipa_ipv6ct_destroy_table(ipa_ipv6ct_table* ipv6ct_table) +{ + int ret; + + IPADBG("\n"); + + ret = ipa_mem_descriptor_delete(&ipv6ct_table->mem_desc, ipv6ct.ipa_desc->fd); + if (ret) + IPAERR("unable to delete IPV6CT descriptor\n"); + + memset(ipv6ct_table, 0, sizeof(*ipv6ct_table)); + + IPADBG("return\n"); + return ret; +} + +/** + * ipa_ipv6ct_create_table_dma_cmd_helpers() - + * Creates dma_cmd_helpers for base table in the received IPv6CT table + * @ipv6ct_table: [in] IPv6CT table + * @table_indx: [in] The index of the IPv6CT table + * + * A DMA command helper helps to generate the DMA command for one + * specific field change. Each table has 3 different types of field + * change: update_head, update_entry and delete_head. This function + * creates the helpers and updates the base table correspondingly. + */ +static void ipa_ipv6ct_create_table_dma_cmd_helpers( + ipa_ipv6ct_table* ipv6ct_table, + uint8_t table_indx ) +{ + IPADBG("\n"); + + ipa_table_dma_cmd_helper_init( + &ipv6ct_table->table_dma_cmd_helpers[IPA_IPV6CT_TABLE_FLAGS], + table_indx, + IPA_IPV6CT_BASE_TBL, + IPA_IPV6CT_EXPN_TBL, + ipv6ct_table->mem_desc.addr_offset + IPA_IPV6CT_RULE_FLAG_FIELD_OFFSET); + + ipa_table_dma_cmd_helper_init( + &ipv6ct_table->table_dma_cmd_helpers[IPA_IPV6CT_TABLE_NEXT_INDEX], + table_indx, + IPA_IPV6CT_BASE_TBL, + IPA_IPV6CT_EXPN_TBL, + ipv6ct_table->mem_desc.addr_offset + IPA_IPV6CT_RULE_NEXT_FIELD_OFFSET); + + ipa_table_dma_cmd_helper_init( + &ipv6ct_table->table_dma_cmd_helpers[IPA_IPV6CT_TABLE_PROTOCOL], + table_indx, + IPA_IPV6CT_BASE_TBL, + IPA_IPV6CT_EXPN_TBL, + ipv6ct_table->mem_desc.addr_offset + IPA_IPV6CT_RULE_PROTO_FIELD_OFFSET); + + ipv6ct_table->table.dma_help[HELP_UPDATE_HEAD] = + &ipv6ct_table->table_dma_cmd_helpers[IPA_IPV6CT_TABLE_FLAGS]; + ipv6ct_table->table.dma_help[HELP_UPDATE_ENTRY] = + &ipv6ct_table->table_dma_cmd_helpers[IPA_IPV6CT_TABLE_NEXT_INDEX]; + ipv6ct_table->table.dma_help[HELP_DELETE_HEAD] = + &ipv6ct_table->table_dma_cmd_helpers[IPA_IPV6CT_TABLE_PROTOCOL]; + + IPADBG("return\n"); +} + +static int ipa_ipv6ct_post_init_cmd(ipa_ipv6ct_table* ipv6ct_table, uint8_t tbl_index) +{ + struct ipa_ioc_ipv6ct_init cmd; + int ret; + + IPADBG("\n"); + + cmd.tbl_index = tbl_index; + + cmd.base_table_offset = ipv6ct_table->mem_desc.addr_offset; + cmd.expn_table_offset = cmd.base_table_offset + (ipv6ct_table->table.table_entries * sizeof(ipa_ipv6ct_hw_entry)); + + /* Driverr/HW expected base table size to be power^2-1 due to H/W hash calculation */ + cmd.table_entries = ipv6ct_table->table.table_entries - 1; + cmd.expn_table_entries = ipv6ct_table->table.expn_table_entries; + + ret = ioctl(ipv6ct.ipa_desc->fd, IPA_IOC_INIT_IPV6CT_TABLE, &cmd); + if (ret) + { + IPAERR("unable to post init cmd Error: %d IPA fd %d\n", ret, ipv6ct.ipa_desc->fd); + return ret; + } + + IPADBG("Posted IPA_IOC_INIT_IPV6CT_TABLE to kernel successfully\n"); + return 0; +} + +static int ipa_ipv6ct_post_dma_cmd(struct ipa_ioc_nat_dma_cmd* cmd) +{ + IPADBG("\n"); + + cmd->mem_type = IPA_NAT_MEM_IN_DDR; + + if (ioctl(ipv6ct.ipa_desc->fd, IPA_IOC_TABLE_DMA_CMD, cmd)) + { + IPAERR("ioctl (IPA_IOC_TABLE_DMA_CMD) on fd %d has failed\n", + ipv6ct.ipa_desc->fd); + return -EIO; + } + IPADBG("posted IPA_IOC_TABLE_DMA_CMD to kernel successfully\n"); + return 0; +} + +void ipa_ipv6ct_dump_table(uint32_t table_handle) +{ + ipa_ipv6ct_table* ipv6ct_table; + + if (ipv6ct.ipa_desc->ver < IPA_HW_v4_0) + { + IPAERR("IPv6 connection tracking isn't supported for IPA version %d\n", ipv6ct.ipa_desc->ver); + return; + } + + if (table_handle == IPA_TABLE_INVALID_ENTRY || table_handle > IPA_IPV6CT_MAX_TBLS) + { + IPAERR("invalid parameters passed %d\n", table_handle); + return; + } + + if (pthread_mutex_lock(&ipv6ct_mutex)) + { + IPAERR("unable to lock the ipv6ct mutex\n"); + return; + } + + ipv6ct_table = &ipv6ct.tables[table_handle - 1]; + if (!ipv6ct_table->mem_desc.valid) + { + IPAERR("invalid table handle %d\n", table_handle); + goto unlock; + } + + /* Prevents interleaving with later kernel printouts. Flush doesn't help. */ + sleep(1); + ipa_read_debug_info(IPA_IPV6CT_DEBUG_FILE_PATH); + ipa_read_debug_info(IPA_UC_ACT_DEBUG_FILE_PATH); + sleep(1); + +unlock: + if (pthread_mutex_unlock(&ipv6ct_mutex)) + IPAERR("unable to unlock the ipv6ct mutex\n"); +} + +/** + * ipa_ipv6ct_add_uc_act_entry() - add uc activation entry + * @u: [in] structure specifying the uC activation entry + * + * Returns: 0 On Success, negative on failure + */ +int ipa_ipv6ct_add_uc_act_entry(union ipa_ioc_uc_activation_entry *u) +{ + IPADBG("\n"); + + if(ioctl(ipv6ct.ipa_desc->fd, IPA_IOC_ADD_UC_ACT_ENTRY, u)) + { + IPAERR("ioctl (IPA_IOC_ADD_UC_ACT_ENTRY) on fd %d has failed\n", + ipv6ct.ipa_desc->fd); + return -EIO; + } + IPADBG("posted IPA_IOC_ADD_UC_ACT_ENTRY to kernel successfully, index %d\n", + u->ipv6_nat.index); + return 0; +} + +/** + * ipa_ipv6ct_del_uc_act_entry() - del uc activation entry + * @index: [in] index of the uc activation entry to be removed + * + * Returns: 0 On Success, negative on failure + */ +int ipa_ipv6ct_del_uc_act_entry(uint16_t index) +{ + IPADBG("\n"); + + if(ioctl(ipv6ct.ipa_desc->fd, IPA_IOC_DEL_UC_ACT_ENTRY, index)) + { + IPAERR("ioctl (IPA_IOC_DEL_UC_ACT_ENTRY) on fd %d has failed\n", + ipv6ct.ipa_desc->fd); + return -EIO; + } + IPADBG("posted IPA_IOC_DEL_UC_ACT_ENTRY to kernel successfully, index %d\n", + index); + return 0; +} diff --git a/qcom/opensource/dataipa/ipanat/src/ipa_mem_descriptor.c b/qcom/opensource/dataipa/ipanat/src/ipa_mem_descriptor.c new file mode 100644 index 0000000000..4ef5343464 --- /dev/null +++ b/qcom/opensource/dataipa/ipanat/src/ipa_mem_descriptor.c @@ -0,0 +1,363 @@ +/* + * Copyright (c) 2018-2020 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "ipa_mem_descriptor.h" +#include "ipa_nat_utils.h" + +#include +#include +#include +#include +#include + +#define IPA_DEV_DIR "/dev/" + +#ifdef IPA_ON_R3PC +#define IPA_DEVICE_MMAP_MEM_SIZE (2 * 1024UL * 1024UL - 1) +#endif + +static int AllocateMemory( + ipa_mem_descriptor* desc, + int ipa_fd) +{ + struct ipa_ioc_nat_ipv6ct_table_alloc cmd; + int ret = 0; + + IPADBG("In\n"); + +#ifndef IPA_ON_R3PC + /* + * If/when the number of NAT table entries requested yields a byte + * count that will fit in SRAM, SRAM will be used to hold the NAT + * table. When SRAM is used, some odd things can happen, relative + * to mmap'ing's virtual memory scheme, that require us to make + * some adjustments. + * + * To be more specific, the real physical SRAM location for the + * table and the table's size may not play well with Linux's + * mmap'ing virtual memory scheme....which likes everything to be + * PAGE_SIZE aligned and sized in multiples of PAGE_SIZE. + * + * Given the above, if the NAT table's (in SRAM) physical address + * in not on a PAGE_SIZE boundary, it will be offset into the + * mmap'd virtual memory, hence we need to know that offset in + * order to get to the table. If said offset plus the table's + * size takes it across a PAGE_SIZE boundary, we need to allocate + * more space to ensure that the table is completely within the + * mmap'd virtual memory. + */ + desc->sram_available = desc->sram_to_be_used = false; + + memset(&desc->nat_sram_info, 0, sizeof(desc->nat_sram_info)); + + ret = ioctl( + ipa_fd, + IPA_IOC_GET_NAT_IN_SRAM_INFO, + &desc->nat_sram_info); + + if ( ret == 0 ) + { + IPADBG("sram_mem_available_for_nat(0x%08x) " + "nat_table_offset_into_mmap(0x%08x) " + "best_nat_in_sram_size_rqst(0x%08x)\n", + desc->nat_sram_info.sram_mem_available_for_nat, + desc->nat_sram_info.nat_table_offset_into_mmap, + desc->nat_sram_info.best_nat_in_sram_size_rqst); + + desc->sram_available = true; + + if ( desc->consider_using_sram ) + { + if (desc->orig_rqst_size <= + desc->nat_sram_info.sram_mem_available_for_nat) + { + desc->sram_to_be_used = true; + } + } + } +#endif + + /* + * Now do the actual allocation... + */ + memset(&cmd, 0, sizeof(cmd)); + + cmd.size = desc->orig_rqst_size; + + ret = ioctl(ipa_fd, desc->allocate_ioctl_num, &cmd); + + if (ret) + { + IPAERR("Unable to post %s allocate table command. Error %d IPA fd %d\n", + desc->name, ret, ipa_fd); + goto bail; + } + + desc->addr_offset = cmd.offset; + + IPADBG("The memory desc for %s allocated successfully\n", desc->name); + +bail: + IPADBG("Out\n"); + + return ret; +} + +static int MapMemory( + ipa_mem_descriptor* desc, + int ipa_fd) +{ + char device_full_path[IPA_RESOURCE_NAME_MAX]; + size_t ipa_dev_dir_path_len; + int device_fd; + int ret = 0; + + IPADBG("In\n"); + + ipa_dev_dir_path_len = + strlcpy(device_full_path, IPA_DEV_DIR, IPA_RESOURCE_NAME_MAX); + + if (ipa_dev_dir_path_len >= IPA_RESOURCE_NAME_MAX) + { + IPAERR("Unable to copy a string with size %d to buffer with size %d\n", + (int)ipa_dev_dir_path_len, IPA_RESOURCE_NAME_MAX); + ret = -EINVAL; + goto bail; + } + + strlcpy(device_full_path + ipa_dev_dir_path_len, + desc->name, IPA_RESOURCE_NAME_MAX - ipa_dev_dir_path_len); + + device_fd = open(device_full_path, O_RDWR); + + if (device_fd < 0) + { + IPAERR("unable to open the desc %s in path %s. Error:%d\n", + desc->name, device_full_path, device_fd); + ret = -EIO; + goto bail; + } + +#ifndef IPA_ON_R3PC + /* + * If/when the number of NAT table entries requested yields a byte + * count that will fit in SRAM, SRAM will be used to hold the NAT + * table. When SRAM is used, some odd things can happen, relative + * to mmap'ing's virtual memory scheme, that require us to make + * some adjustments. + * + * To be more specific, the real physical SRAM location for the + * table and the table's size may not play well with Linux's + * mmap'ing virtual memory scheme....which likes everything to be + * PAGE_SIZE aligned and sized in multiples of PAGE_SIZE. + * + * Given the above, if the NAT table's (in SRAM) physical address + * in not on a PAGE_SIZE boundary, it will be offset into the + * mmap'd virtual memory, hence we need to know that offset in + * order to get to the table. If said offset plus the table's + * size takes it across a PAGE_SIZE boundary, we need to allocate + * more space to ensure that the table is completely within the + * mmap'd virtual memory. + */ + desc->mmap_size = + ( desc->sram_to_be_used ) ? + desc->nat_sram_info.best_nat_in_sram_size_rqst : + desc->orig_rqst_size; + + desc->mmap_addr = desc->base_addr = + (void* )mmap( + NULL, + desc->mmap_size, + PROT_READ | PROT_WRITE, + MAP_SHARED, + device_fd, + 0); +#else + IPADBG("user space r3pc\n"); + desc->mmap_addr = desc->base_addr = + (void *) mmap( + (caddr_t)0, + IPA_DEVICE_MMAP_MEM_SIZE, + PROT_READ | PROT_WRITE, + MAP_SHARED, + device_fd, + 0); +#endif + + if (desc->base_addr == MAP_FAILED) + { + IPAERR("Unable to mmap the memory for %s\n", desc->name); + ret = -EINVAL; + goto close; + } + + if ( desc->sram_to_be_used ) + { + desc->base_addr = + (uint8_t*) (desc->base_addr) + + desc->nat_sram_info.nat_table_offset_into_mmap; + } + + IPADBG("mmap for %s return value 0x%lx -> 0x%lx\n", + desc->name, + (long unsigned int) desc->mmap_addr, + (long unsigned int) desc->base_addr); + +close: + if (close(device_fd)) + { + IPAERR("unable to close the file descriptor for %s\n", desc->name); + ret = -EINVAL; + } + +bail: + IPADBG("Out\n"); + + return ret; +} + +static int DeallocateMemory( + ipa_mem_descriptor* desc, + int ipa_fd) +{ + struct ipa_ioc_nat_ipv6ct_table_del cmd; + int ret = 0; + + IPADBG("In\n"); + + memset(&cmd, 0, sizeof(cmd)); + + cmd.table_index = desc->table_index; + + cmd.mem_type = + ( desc->sram_to_be_used ) ? + IPA_NAT_MEM_IN_SRAM : + IPA_NAT_MEM_IN_DDR; + + ret = ioctl(ipa_fd, desc->delete_ioctl_num, &cmd); + + if (ret) + { + IPAERR("unable to post table delete command for %s Error: %d IPA fd %d\n", + desc->name, ret, ipa_fd); + goto bail; + } + + IPADBG("posted delete command for %s to kernel successfully\n", desc->name); + +bail: + IPADBG("Out\n"); + + return ret; +} + +void ipa_mem_descriptor_init( + ipa_mem_descriptor* desc, + const char* device_name, + int size, + uint8_t table_index, + unsigned long allocate_ioctl_num, + unsigned long delete_ioctl_num, + bool consider_using_sram ) +{ + IPADBG("In\n"); + + strlcpy(desc->name, device_name, IPA_RESOURCE_NAME_MAX); + + desc->orig_rqst_size = desc->mmap_size = size; + desc->table_index = table_index; + desc->allocate_ioctl_num = allocate_ioctl_num; + desc->delete_ioctl_num = delete_ioctl_num; + desc->consider_using_sram = consider_using_sram; + + IPADBG("Out\n"); +} + +int ipa_mem_descriptor_allocate_memory( + ipa_mem_descriptor* desc, + int ipa_fd) +{ + int ret; + + IPADBG("In\n"); + + ret = AllocateMemory(desc, ipa_fd); + + if (ret) + { + IPAERR("unable to allocate %s\n", desc->name); + goto bail; + } + + ret = MapMemory(desc, ipa_fd); + + if (ret) + { + IPAERR("unable to map %s\n", desc->name); + DeallocateMemory(desc, ipa_fd); + goto bail; + } + + desc->valid = TRUE; + +bail: + IPADBG("Out\n"); + + return ret; +} + +int ipa_mem_descriptor_delete( + ipa_mem_descriptor* desc, + int ipa_fd) +{ + int ret = 0; + + IPADBG("In\n"); + + if (! desc->valid) + { + IPAERR("invalid desc handle passed\n"); + ret = -EINVAL; + goto bail; + } + + desc->valid = FALSE; + +#ifndef IPA_ON_R3PC + munmap(desc->mmap_addr, desc->mmap_size); +#else + munmap(desc->mmap_addr, IPA_DEVICE_MMAP_MEM_SIZE); +#endif + + ret = DeallocateMemory(desc, ipa_fd); + +bail: + IPADBG("Out\n"); + + return ret; +} diff --git a/qcom/opensource/dataipa/ipanat/src/ipa_nat_drv.c b/qcom/opensource/dataipa/ipanat/src/ipa_nat_drv.c new file mode 100644 index 0000000000..0fbf4731fd --- /dev/null +++ b/qcom/opensource/dataipa/ipanat/src/ipa_nat_drv.c @@ -0,0 +1,348 @@ +/* + * Copyright (c) 2013-2020 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "ipa_nat_drv.h" +#include "ipa_nat_drvi.h" + +#include + +/** + * ipa_nat_add_ipv4_tbl() - create ipv4 nat table + * @public_ip_addr: [in] public ipv4 address + * @mem_type_ptr: [in] type of memory table is to reside in + * @number_of_entries: [in] number of nat entries + * @table_handle: [out] Handle of new ipv4 nat table + * + * To create new ipv4 nat table + * + * Returns: 0 On Success, negative on failure + */ +int ipa_nat_add_ipv4_tbl( + uint32_t public_ip_addr, + const char *mem_type_ptr, + uint16_t number_of_entries, + uint32_t *tbl_hdl) +{ + int ret; + + if (tbl_hdl == NULL || mem_type_ptr == NULL || number_of_entries == 0) { + IPAERR( + "Invalid parameters tbl_hdl=%pK mem_type_ptr=%p number_of_entries=%d\n", + tbl_hdl, + mem_type_ptr, + number_of_entries); + return -EINVAL; + } + + *tbl_hdl = 0; + + ret = ipa_nati_add_ipv4_tbl( + public_ip_addr, mem_type_ptr, number_of_entries, tbl_hdl); + + if (ret) { + IPAERR("unable to add NAT table\n"); + return ret; + } + + IPADBG("Returning table handle 0x%x\n", *tbl_hdl); + + return ret; +} /* __ipa_nat_add_ipv4_tbl() */ + +/** + * ipa_nat_del_ipv4_tbl() - delete ipv4 table + * @table_handle: [in] Handle of ipv4 nat table + * + * To delete given ipv4 nat table + * + * Returns: 0 On Success, negative on failure + */ +int ipa_nat_del_ipv4_tbl( + uint32_t tbl_hdl) +{ + if ( ! VALID_TBL_HDL(tbl_hdl) ) { + IPAERR("Invalid table handle passed 0x%08X\n", tbl_hdl); + return -EINVAL; + } + + IPADBG("Passed Table Handle: 0x%08X\n", tbl_hdl); + + return ipa_nati_del_ipv4_table(tbl_hdl); +} + +/** + * ipa_nat_add_ipv4_rule() - to insert new ipv4 rule + * @table_handle: [in] handle of ipv4 nat table + * @rule: [in] Pointer to new rule + * @rule_handle: [out] Return the handle to rule + * + * To insert new ipv4 nat rule into ipv4 nat table + * + * Returns: 0 On Success, negative on failure + */ +int ipa_nat_add_ipv4_rule( + uint32_t tbl_hdl, + const ipa_nat_ipv4_rule *clnt_rule, + uint32_t *rule_hdl) +{ + int result = -EINVAL; + + if ( ! VALID_TBL_HDL(tbl_hdl) || + rule_hdl == NULL || + clnt_rule == NULL ) { + IPAERR( + "Invalid parameters tbl_hdl=%d clnt_rule=%pK rule_hdl=%pK\n", + tbl_hdl, clnt_rule, rule_hdl); + return result; + } + + IPADBG("Passed Table handle: 0x%x\n", tbl_hdl); + + if (ipa_nati_add_ipv4_rule(tbl_hdl, clnt_rule, rule_hdl)) { + return result; + } + + IPADBG("Returning rule handle %u\n", *rule_hdl); + + return 0; +} + +/** + * ipa_nat_del_ipv4_rule() - to delete ipv4 nat rule + * @table_handle: [in] handle of ipv4 nat table + * @rule_handle: [in] ipv4 nat rule handle + * + * To insert new ipv4 nat rule into ipv4 nat table + * + * Returns: 0 On Success, negative on failure + */ +int ipa_nat_del_ipv4_rule( + uint32_t tbl_hdl, + uint32_t rule_hdl) +{ + int result = -EINVAL; + + if ( ! VALID_TBL_HDL(tbl_hdl) || ! VALID_RULE_HDL(rule_hdl) ) + { + IPAERR("Invalid parameters tbl_hdl=0x%08X rule_hdl=0x%08X\n", + tbl_hdl, rule_hdl); + return result; + } + + IPADBG("Passed Table: 0x%08X and rule handle 0x%08X\n", tbl_hdl, rule_hdl); + + result = ipa_nati_del_ipv4_rule(tbl_hdl, rule_hdl); + if (result) { + IPAERR( + "Unable to delete rule with handle 0x%08X " + "from hw for NAT table with handle 0x%08X\n", + rule_hdl, tbl_hdl); + return result; + } + + return 0; +} + +/** + * ipa_nat_query_timestamp() - to query timestamp + * @table_handle: [in] handle of ipv4 nat table + * @rule_handle: [in] ipv4 nat rule handle + * @time_stamp: [out] time stamp of rule + * + * To retrieve the timestamp that lastly the + * nat rule was accessed + * + * Returns: 0 On Success, negative on failure + */ +int ipa_nat_query_timestamp( + uint32_t tbl_hdl, + uint32_t rule_hdl, + uint32_t *time_stamp) +{ + if ( ! VALID_TBL_HDL(tbl_hdl) || + ! VALID_RULE_HDL(rule_hdl) || + time_stamp == NULL ) + { + IPAERR("Invalid parameters passed tbl_hdl=0x%x rule_hdl=%u time_stamp=%pK\n", + tbl_hdl, rule_hdl, time_stamp); + return -EINVAL; + } + + IPADBG("Passed Table 0x%x and rule handle %u\n", tbl_hdl, rule_hdl); + + return ipa_nati_query_timestamp(tbl_hdl, rule_hdl, time_stamp); +} + +/** +* ipa_nat_modify_pdn() - modify single PDN entry in the PDN config table +* @table_handle: [in] handle of ipv4 nat table +* @pdn_index : [in] the index of the entry to be modified +* @pdn_info : [in] values for the PDN entry to be changed +* +* Modify a PDN entry +* +* Returns: 0 On Success, negative on failure +*/ +int ipa_nat_modify_pdn( + uint32_t tbl_hdl, + uint8_t pdn_index, + ipa_nat_pdn_entry *pdn_info) +{ + struct ipa_ioc_nat_pdn_entry pdn_data; + + if ( ! VALID_TBL_HDL(tbl_hdl) || + pdn_info == NULL) { + IPAERR( + "invalid parameters passed tbl_hdl=%d pdn_info=%pK\n", + tbl_hdl, pdn_info); + return -EINVAL; + } + + if (pdn_index > IPA_MAX_PDN_NUM) { + IPAERR( + "PDN index %d is out of range maximum %d", + pdn_index, IPA_MAX_PDN_NUM); + return -EINVAL; + } + + pdn_data.pdn_index = pdn_index; + pdn_data.public_ip = pdn_info->public_ip; + pdn_data.src_metadata = pdn_info->src_metadata; + pdn_data.dst_metadata = pdn_info->dst_metadata; + + return ipa_nati_modify_pdn(&pdn_data); +} + +/** +* ipa_nat_get_pdn_index() - get a PDN index for a public ip +* @public_ip : [in] IPv4 address of the PDN entry +* @pdn_index : [out] the index of the requested PDN entry +* +* Get a PDN entry +* +* Returns: 0 On Success, negative on failure +*/ +int ipa_nat_get_pdn_index( + uint32_t public_ip, + uint8_t *pdn_index) +{ + if(!pdn_index) + { + IPAERR("NULL PDN index\n"); + return -EINVAL; + } + + return ipa_nati_get_pdn_index(public_ip, pdn_index); +} + +/** +* ipa_nat_alloc_pdn() - allocate a PDN for new WAN +* @pdn_info : [in] values for the PDN entry to be created +* @pdn_index : [out] the index of the requested PDN entry +* +* allocate a new PDN entry +* +* Returns: 0 On Success, negative on failure +*/ +int ipa_nat_alloc_pdn( + ipa_nat_pdn_entry *pdn_info, + uint8_t *pdn_index) +{ + if(!pdn_info) + { + IPAERR("NULL PDN info\n"); + return -EINVAL; + } + + if(!pdn_index) + { + IPAERR("NULL PDN index\n"); + return -EINVAL; + } + + return ipa_nati_alloc_pdn(pdn_info, pdn_index); +} + +/** +* ipa_nat_get_pdn_count() - get the number of allocated PDNs +* @pdn_cnt : [out] the number of allocated PDNs +* +* get the number of allocated PDNs +* +* Returns: 0 On Success, negative on failure +*/ +int ipa_nat_get_pdn_count( + uint8_t *pdn_cnt) +{ + if(!pdn_cnt) + { + IPAERR("NULL PDN count\n"); + return -EINVAL; + } + + *pdn_cnt = ipa_nati_get_pdn_cnt(); + + return 0; +} + +/** +* ipa_nat_dealloc_pdn() - deallocate a PDN entry +* @pdn_index : [in] pdn index to be deallocated +* +* deallocate a PDN in specified index - zero the PDN entry +* +* Returns: 0 On Success, negative on failure +*/ +int ipa_nat_dealloc_pdn( + uint8_t pdn_index) +{ + if(pdn_index > IPA_MAX_PDN_NUM) { + IPAERR("PDN index is out of range %d", pdn_index); + return -EINVAL; + } + + return ipa_nati_dealloc_pdn(pdn_index); +} + +/** + * ipa_nat_vote_clock() - used for voting clock + * @vote_type: [in] desired vote type + */ +int ipa_nat_vote_clock( + enum ipa_app_clock_vote_type vote_type ) +{ + if ( ! (vote_type >= IPA_APP_CLK_DEVOTE && + vote_type <= IPA_APP_CLK_RESET_VOTE) ) + { + IPAERR("Bad vote_type(%u) parameter\n", vote_type); + return -EINVAL; + } + + return ipa_nati_vote_clock(vote_type); +} diff --git a/qcom/opensource/dataipa/ipanat/src/ipa_nat_drvi.c b/qcom/opensource/dataipa/ipanat/src/ipa_nat_drvi.c new file mode 100644 index 0000000000..53eaa4dd16 --- /dev/null +++ b/qcom/opensource/dataipa/ipanat/src/ipa_nat_drvi.c @@ -0,0 +1,2686 @@ +/* + * Copyright (c) 2013-2020 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "ipa_nat_drv.h" +#include "ipa_nat_drvi.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define IPA_NAT_DEBUG_FILE_PATH "/sys/kernel/debug/ipa/ip4_nat" +#define IPA_NAT_TABLE_NAME "IPA NAT table" +#define IPA_NAT_INDEX_TABLE_NAME "IPA NAT index table" + + +#undef min +#define min(a, b) ((a) < (b)) ? (a) : (b) + +#undef max +#define max(a, b) ((a) > (b)) ? (a) : (b) + +static struct ipa_nat_cache ipv4_nat_cache[IPA_NAT_MEM_IN_MAX]; + +static struct ipa_nat_cache *active_nat_cache_ptr = NULL; + +#undef DDR_IS_ACTIVE +#define DDR_IS_ACTIVE() \ + (active_nat_cache_ptr) ? \ + (active_nat_cache_ptr->nmi == IPA_NAT_MEM_IN_DDR) : \ + false + +#undef SRAM_IS_ACTIVE +#define SRAM_IS_ACTIVE() \ + (active_nat_cache_ptr) ? \ + (active_nat_cache_ptr->nmi == IPA_NAT_MEM_IN_SRAM) : \ + false + +extern pthread_mutex_t nat_mutex; + +static ipa_nat_pdn_entry pdns[IPA_MAX_PDN_NUM]; +static int num_pdns = 0; +static int Hash_token = 69; +/* + * ---------------------------------------------------------------------------- + * Private helpers for manipulating regular tables + * ---------------------------------------------------------------------------- + */ +static int table_entry_is_valid( + void* entry) +{ + struct ipa_nat_rule* rule = (struct ipa_nat_rule*) entry; + + IPADBG("In\n"); + + IPADBG("enable(%u)\n", rule->enable); + + IPADBG("Out\n"); + + return rule->enable; +} + +static uint16_t table_entry_get_next_index( + void* entry) +{ + uint16_t result; + struct ipa_nat_rule* rule = (struct ipa_nat_rule*)entry; + + IPADBG("In\n"); + + result = rule->next_index; + + IPADBG("Next entry of %pK is %u\n", entry, result); + + IPADBG("Out\n"); + + return result; +} + +static uint16_t table_entry_get_prev_index( + void* entry, + uint16_t entry_index, + void* meta, + uint16_t base_table_size) +{ + uint16_t result; + struct ipa_nat_rule* rule = (struct ipa_nat_rule*)entry; + + IPADBG("In\n"); + + result = rule->prev_index; + + IPADBG("Previous entry of %u is %u\n", entry_index, result); + + IPADBG("Out\n"); + + return result; +} + +static void table_entry_set_prev_index( + void* entry, + uint16_t entry_index, + uint16_t prev_index, + void* meta, + uint16_t base_table_size) +{ + struct ipa_nat_rule* rule = (struct ipa_nat_rule*) entry; + + IPADBG("In\n"); + + IPADBG("Previous entry of %u is %u\n", entry_index, prev_index); + + rule->prev_index = prev_index; + + IPADBG("Out\n"); +} + +/** + * ipa_nati_calc_ip_cksum() - Calculate the source nat IP checksum diff + * @pub_ip_addr: [in] public ip address + * @priv_ip_addr: [in] Private ip address + * + * source nat ip checksum different is calculated as + * public_ip_addr - private_ip_addr + * Here we are using 1's complement to represent -ve number. + * So take 1's complement of private ip addr and add it + * to public ip addr. + * + * Returns: >0 ip checksum diff + */ +static uint16_t ipa_nati_calc_ip_cksum( + uint32_t pub_ip_addr, + uint32_t priv_ip_addr) +{ + uint16_t ret; + uint32_t cksum = 0; + + IPADBG("In\n"); + + /* Add LSB(2 bytes) of public ip address to cksum */ + cksum += (pub_ip_addr & 0xFFFF); + + /* Add MSB(2 bytes) of public ip address to cksum + and check for carry forward(CF), if any add it + */ + cksum += (pub_ip_addr>>16); + if (cksum >> 16) { + cksum = (cksum & 0x0000FFFF); + cksum += 1; + } + + /* Calculate the 1's complement of private ip address */ + priv_ip_addr = (~priv_ip_addr); + + /* Add LSB(2 bytes) of private ip address to cksum + and check for carry forward(CF), if any add it + */ + cksum += (priv_ip_addr & 0xFFFF); + if (cksum >> 16) { + cksum = (cksum & 0x0000FFFF); + cksum += 1; + } + + /* Add MSB(2 bytes) of private ip address to cksum + and check for carry forward(CF), if any add it + */ + cksum += (priv_ip_addr>>16); + if (cksum >> 16) { + cksum = (cksum & 0x0000FFFF); + cksum += 1; + } + + /* Return the LSB(2 bytes) of checksum */ + ret = (uint16_t)cksum; + + IPADBG("Out\n"); + + return ret; +} + +/** + * ipa_nati_calc_tcp_udp_cksum() - Calculate the source nat TCP/UDP checksum diff + * @pub_ip_addr: [in] public ip address + * @pub_port: [in] public tcp/udp port + * @priv_ip_addr: [in] Private ip address + * @priv_port: [in] Private tcp/udp prot + * + * source nat tcp/udp checksum is calculated as + * (pub_ip_addr + pub_port) - (priv_ip_addr + priv_port) + * Here we are using 1's complement to represent -ve number. + * So take 1's complement of prviate ip addr &private port + * and add it public ip addr & public port. + * + * Returns: >0 tcp/udp checksum diff + */ +static uint16_t ipa_nati_calc_tcp_udp_cksum( + uint32_t pub_ip_addr, + uint16_t pub_port, + uint32_t priv_ip_addr, + uint16_t priv_port) +{ + uint16_t ret = 0; + uint32_t cksum = 0; + + IPADBG("In\n"); + + /* Add LSB(2 bytes) of public ip address to cksum */ + cksum += (pub_ip_addr & 0xFFFF); + + /* Add MSB(2 bytes) of public ip address to cksum + and check for carry forward(CF), if any add it + */ + cksum += (pub_ip_addr>>16); + if (cksum >> 16) { + cksum = (cksum & 0x0000FFFF); + cksum += 1; + } + + /* Add public port to cksum and + check for carry forward(CF), if any add it */ + cksum += pub_port; + if (cksum >> 16) { + cksum = (cksum & 0x0000FFFF); + cksum += 1; + } + + /* Calculate the 1's complement of private ip address */ + priv_ip_addr = (~priv_ip_addr); + + /* Add LSB(2 bytes) of private ip address to cksum + and check for carry forward(CF), if any add it + */ + cksum += (priv_ip_addr & 0xFFFF); + if (cksum >> 16) { + cksum = (cksum & 0x0000FFFF); + cksum += 1; + } + + /* Add MSB(2 bytes) of private ip address to cksum + and check for carry forward(CF), if any add + */ + cksum += (priv_ip_addr>>16); + if (cksum >> 16) { + cksum = (cksum & 0x0000FFFF); + cksum += 1; + } + + /* Calculate the 1's complement of private port */ + priv_port = (~priv_port); + + /* Add public port to cksum and + check for carry forward(CF), if any add it */ + cksum += priv_port; + if (cksum >> 16) { + cksum = (cksum & 0x0000FFFF); + cksum += 1; + } + + /* return the LSB(2 bytes) of checksum */ + ret = (uint16_t)cksum; + + IPADBG("Out\n"); + + return ret; +} + +static int table_entry_copy_from_user( + void* entry, + void* user_data) +{ + uint32_t pub_ip_addr; + + struct ipa_nat_rule* nat_entry = (struct ipa_nat_rule*) entry; + const ipa_nat_ipv4_rule* user_rule = (const ipa_nat_ipv4_rule*) user_data; + + IPADBG("In\n"); + + pub_ip_addr = pdns[user_rule->pdn_index].public_ip; + + nat_entry->private_ip = user_rule->private_ip; + nat_entry->private_port = user_rule->private_port; + nat_entry->protocol = user_rule->protocol; + nat_entry->public_port = user_rule->public_port; + nat_entry->target_ip = user_rule->target_ip; + nat_entry->target_port = user_rule->target_port; + nat_entry->pdn_index = user_rule->pdn_index; + nat_entry->uc_activation_index = user_rule->uc_activation_index; + nat_entry->s = user_rule->s; + nat_entry->ucp = user_rule->ucp; + nat_entry->dst_only = user_rule->dst_only; + nat_entry->src_only = user_rule->src_only; + + nat_entry->ip_chksum = + ipa_nati_calc_ip_cksum(pub_ip_addr, user_rule->private_ip); + + if (IPPROTO_TCP == nat_entry->protocol || + IPPROTO_UDP == nat_entry->protocol) { + nat_entry->tcp_udp_chksum = ipa_nati_calc_tcp_udp_cksum( + pub_ip_addr, + user_rule->public_port, + user_rule->private_ip, + user_rule->private_port); + } + + IPADBG("Out\n"); + + return 0; +} + +static int table_entry_head_insert( + void* entry, + void* user_data, + uint16_t* dma_command_data) +{ + int ret; + struct ipa_nat_rule* nat_entry = (struct ipa_nat_rule*) entry; + + IPADBG("In\n"); + + IPADBG("entry(%p) user_data(%p) dma_command_data(%p)\n", + entry, + user_data, + dma_command_data); + + ret = table_entry_copy_from_user(entry, user_data); + + if (ret) { + IPAERR("unable to copy from user a new entry\n"); + goto bail; + } + + *dma_command_data = 0; + ((ipa_nat_flags*)dma_command_data)->enable = IPA_NAT_FLAG_ENABLE_BIT; + ((ipa_nat_flags*)dma_command_data)->uc_activation_index = + nat_entry->uc_activation_index; + ((ipa_nat_flags*)dma_command_data)->s = nat_entry->s; +; + +bail: + IPADBG("Out\n"); + + return ret; +} + +static int table_entry_tail_insert( + void* entry, + void* user_data) +{ + struct ipa_nat_rule* nat_entry = (struct ipa_nat_rule*) entry; + + int ret; + + IPADBG("In\n"); + + IPADBG("entry(%p) user_data(%p)\n", + entry, + user_data); + + ret = table_entry_copy_from_user(entry, user_data); + + if (ret) { + IPAERR("unable to copy from user a new entry\n"); + goto bail; + } + + nat_entry->enable = IPA_NAT_FLAG_ENABLE_BIT; + +bail: + IPADBG("Out\n"); + + return ret; +} + +static uint16_t table_entry_get_delete_head_dma_command_data( + void* head, + void* next_entry) +{ + IPADBG("In\n"); + + IPADBG("Out\n"); + + return IPA_NAT_INVALID_PROTO_FIELD_VALUE; +} + +/* + * ---------------------------------------------------------------------------- + * Private helpers for manipulating index tables + * ---------------------------------------------------------------------------- + */ +static int index_table_entry_is_valid( + void* entry) +{ + struct ipa_nat_indx_tbl_rule* rule = + (struct ipa_nat_indx_tbl_rule*) entry; + + int ret; + + IPADBG("In\n"); + + ret = (rule->tbl_entry) ? 1 : 0; + + IPADBG("enable(%d)\n", ret); + + IPADBG("Out\n"); + + return ret; +} + +static uint16_t index_table_entry_get_next_index( + void* entry) +{ + uint16_t result; + struct ipa_nat_indx_tbl_rule* rule = (struct ipa_nat_indx_tbl_rule*)entry; + + IPADBG("In\n"); + + result = rule->next_index; + + IPADBG("Next entry of %pK is %d\n", entry, result); + + IPADBG("Out\n"); + + return result; +} + +static uint16_t index_table_entry_get_prev_index( + void* entry, + uint16_t entry_index, + void* meta, + uint16_t base_table_size) +{ + uint16_t result = 0; + struct ipa_nat_indx_tbl_meta_info* index_expn_table_meta = + (struct ipa_nat_indx_tbl_meta_info*)meta; + + IPADBG("In\n"); + + if (entry_index >= base_table_size) + result = index_expn_table_meta[entry_index - base_table_size].prev_index; + + IPADBG("Previous entry of %d is %d\n", entry_index, result); + + IPADBG("Out\n"); + + return result; +} + +static void index_table_entry_set_prev_index( + void* entry, + uint16_t entry_index, + uint16_t prev_index, + void* meta, + uint16_t base_table_size) +{ + struct ipa_nat_indx_tbl_meta_info* index_expn_table_meta = + (struct ipa_nat_indx_tbl_meta_info*) meta; + + IPADBG("In\n"); + + IPADBG("Previous entry of %u is %u\n", entry_index, prev_index); + + if ( entry_index >= base_table_size ) + { + index_expn_table_meta[entry_index - base_table_size].prev_index = prev_index; + } + else if ( VALID_INDEX(prev_index) ) + { + IPAERR("Base table entry %u can't has prev entry %u, but only %u", + entry_index, prev_index, IPA_TABLE_INVALID_ENTRY); + } + + IPADBG("Out\n"); +} + +static int index_table_entry_head_insert( + void* entry, + void* user_data, + uint16_t* dma_command_data) +{ + IPADBG("In\n"); + + IPADBG("entry(%p) user_data(%p) dma_command_data(%p)\n", + entry, + user_data, + dma_command_data); + + *dma_command_data = *((uint16_t*)user_data); + + IPADBG("Out\n"); + + return 0; +} + +static int index_table_entry_tail_insert( + void* entry, + void* user_data) +{ + struct ipa_nat_indx_tbl_rule* rule_ptr = + (struct ipa_nat_indx_tbl_rule*) entry; + + IPADBG("In\n"); + + IPADBG("entry(%p) user_data(%p)\n", + entry, + user_data); + + rule_ptr->tbl_entry = *((uint16_t*)user_data); + + IPADBG("Out\n"); + + return 0; +} + +static uint16_t index_table_entry_get_delete_head_dma_command_data( + void* head, + void* next_entry) +{ + uint16_t result; + struct ipa_nat_indx_tbl_rule* rule = + (struct ipa_nat_indx_tbl_rule*)next_entry; + + IPADBG("In\n"); + + result = rule->tbl_entry; + + IPADBG("Out\n"); + + return result; +} + +/* + * ---------------------------------------------------------------------------- + * Private data and functions used by this file's API + * ---------------------------------------------------------------------------- + */ +static ipa_table_entry_interface entry_interface = { + table_entry_is_valid, + table_entry_get_next_index, + table_entry_get_prev_index, + table_entry_set_prev_index, + table_entry_head_insert, + table_entry_tail_insert, + table_entry_get_delete_head_dma_command_data +}; + +static ipa_table_entry_interface index_entry_interface = { + index_table_entry_is_valid, + index_table_entry_get_next_index, + index_table_entry_get_prev_index, + index_table_entry_set_prev_index, + index_table_entry_head_insert, + index_table_entry_tail_insert, + index_table_entry_get_delete_head_dma_command_data +}; + +/** + * ipa_nati_create_table_dma_cmd_helpers() + * + * Creates dma_cmd_helpers for base and index tables in the received + * NAT table + * + * @nat_table: [in] NAT table + * @table_indx: [in] The index of the NAT table + * + * A DMA command helper helps to generate the DMA command for one + * specific field change. Each table has 3 different types of field + * change: update_head, update_entry and delete_head. This function + * creates the helpers for base and index tables and updates the + * tables correspondingly. + */ +static void ipa_nati_create_table_dma_cmd_helpers( + struct ipa_nat_ip4_table_cache* nat_table, + uint8_t table_indx) +{ + IPADBG("In\n"); + + /* + * Create helpers for base table + */ + ipa_table_dma_cmd_helper_init( + &nat_table->table_dma_cmd_helpers[IPA_NAT_TABLE_FLAGS], + table_indx, + IPA_NAT_BASE_TBL, + IPA_NAT_EXPN_TBL, + nat_table->mem_desc.addr_offset + IPA_NAT_RULE_FLAG_FIELD_OFFSET); + + ipa_table_dma_cmd_helper_init( + &nat_table->table_dma_cmd_helpers[IPA_NAT_TABLE_NEXT_INDEX], + table_indx, + IPA_NAT_BASE_TBL, + IPA_NAT_EXPN_TBL, + nat_table->mem_desc.addr_offset + IPA_NAT_RULE_NEXT_FIELD_OFFSET); + + ipa_table_dma_cmd_helper_init( + &nat_table->table_dma_cmd_helpers[IPA_NAT_TABLE_PROTOCOL], + table_indx, + IPA_NAT_BASE_TBL, + IPA_NAT_EXPN_TBL, + nat_table->mem_desc.addr_offset + IPA_NAT_RULE_PROTO_FIELD_OFFSET); + + /* + * Create helpers for index table + */ + ipa_table_dma_cmd_helper_init( + &nat_table->table_dma_cmd_helpers[IPA_NAT_INDEX_TABLE_ENTRY], + table_indx, + IPA_NAT_INDX_TBL, + IPA_NAT_INDEX_EXPN_TBL, + nat_table->mem_desc.addr_offset + IPA_NAT_INDEX_RULE_NAT_INDEX_FIELD_OFFSET); + + ipa_table_dma_cmd_helper_init( + &nat_table->table_dma_cmd_helpers[IPA_NAT_INDEX_TABLE_NEXT_INDEX], + table_indx, + IPA_NAT_INDX_TBL, + IPA_NAT_INDEX_EXPN_TBL, + nat_table->mem_desc.addr_offset + IPA_NAT_INDEX_RULE_NEXT_FIELD_OFFSET); + + /* + * Init helpers for base table + */ + nat_table->table.dma_help[HELP_UPDATE_HEAD] = + &nat_table->table_dma_cmd_helpers[IPA_NAT_TABLE_FLAGS]; + + nat_table->table.dma_help[HELP_UPDATE_ENTRY] = + &nat_table->table_dma_cmd_helpers[IPA_NAT_TABLE_NEXT_INDEX]; + + nat_table->table.dma_help[HELP_DELETE_HEAD] = + &nat_table->table_dma_cmd_helpers[IPA_NAT_TABLE_PROTOCOL]; + + /* + * Init helpers for index table + */ + nat_table->index_table.dma_help[HELP_UPDATE_HEAD] = + &nat_table->table_dma_cmd_helpers[IPA_NAT_INDEX_TABLE_ENTRY]; + + nat_table->index_table.dma_help[HELP_UPDATE_ENTRY] = + &nat_table->table_dma_cmd_helpers[IPA_NAT_INDEX_TABLE_NEXT_INDEX]; + + nat_table->index_table.dma_help[HELP_DELETE_HEAD] = + &nat_table->table_dma_cmd_helpers[IPA_NAT_INDEX_TABLE_ENTRY]; + + IPADBG("Out\n"); +} + +/** + * ipa_nati_create_table() - Creates a new IPv4 NAT table + * @nat_table: [in] IPv4 NAT table + * @public_ip_addr: [in] public IPv4 address + * @number_of_entries: [in] number of NAT entries + * @table_index: [in] the index of the IPv4 NAT table + * + * This function creates new IPv4 NAT table: + * - Initializes table, index table, memory descriptor and + * table_dma_cmd_helpers structures + * - Allocates the index expansion table meta data + * - Allocates, maps and clears the memory for table and index table + * + * Returns: 0 On Success, negative on failure + */ +static int ipa_nati_create_table( + struct ipa_nat_cache* nat_cache_ptr, + struct ipa_nat_ip4_table_cache* nat_table, + uint32_t public_ip_addr, + uint16_t number_of_entries, + uint8_t table_index) +{ + int ret, size; + void* base_addr; + +#ifdef IPA_ON_R3PC + uint32_t nat_mem_offset = 0; +#endif + + IPADBG("In\n"); + + nat_table->public_addr = public_ip_addr; + + ipa_table_init( + &nat_table->table, + IPA_NAT_TABLE_NAME, + nat_cache_ptr->nmi, + sizeof(struct ipa_nat_rule), + NULL, + 0, + &entry_interface); + + ret = ipa_table_calculate_entries_num( + &nat_table->table, + number_of_entries, + nat_cache_ptr->nmi); + + if (ret) { + IPAERR( + "unable to calculate number of entries in " + "nat table %d, while required by user %d\n", + table_index, number_of_entries); + goto done; + } + + /* + * Allocate memory for NAT index expansion table meta data + */ + nat_table->index_expn_table_meta = (struct ipa_nat_indx_tbl_meta_info*) + calloc(nat_table->table.expn_table_entries, + sizeof(struct ipa_nat_indx_tbl_meta_info)); + + if (nat_table->index_expn_table_meta == NULL) { + IPAERR( + "Fail to allocate ipv4 index expansion table meta with size %d\n", + nat_table->table.expn_table_entries * + sizeof(struct ipa_nat_indx_tbl_meta_info)); + ret = -ENOMEM; + goto done; + } + + ipa_table_init( + &nat_table->index_table, + IPA_NAT_INDEX_TABLE_NAME, + nat_cache_ptr->nmi, + sizeof(struct ipa_nat_indx_tbl_rule), + nat_table->index_expn_table_meta, + sizeof(struct ipa_nat_indx_tbl_meta_info), + &index_entry_interface); + + nat_table->index_table.table_entries = + nat_table->table.table_entries; + + nat_table->index_table.expn_table_entries = + nat_table->table.expn_table_entries; + + nat_table->index_table.tot_tbl_ents = + nat_table->table.tot_tbl_ents; + + size = ipa_table_calculate_size(&nat_table->table); + size += ipa_table_calculate_size(&nat_table->index_table); + + IPADBG("Nat Base and Index Table size: %d\n", size); + + ipa_mem_descriptor_init( + &nat_table->mem_desc, + IPA_NAT_DEV_NAME, + size, + table_index, + IPA_IOC_ALLOC_NAT_TABLE, + IPA_IOC_DEL_NAT_TABLE, + true); /* true here means do consider using sram */ + + ret = ipa_mem_descriptor_allocate_memory( + &nat_table->mem_desc, + nat_cache_ptr->ipa_desc->fd); + + if (ret) { + IPAERR("unable to allocate nat memory descriptor Error: %d\n", ret); + goto bail_meta; + } + + base_addr = nat_table->mem_desc.base_addr; + +#ifdef IPA_ON_R3PC + ret = ioctl(nat_cache_ptr->ipa_desc->fd, + IPA_IOC_GET_NAT_OFFSET, + &nat_mem_offset); + if (ret) { + IPAERR("unable to post ant offset cmd Error: %d IPA fd %d\n", + ret, nat_cache_ptr->ipa_desc->fd); + goto bail_mem_desc; + } + base_addr += nat_mem_offset; +#endif + + base_addr = + ipa_table_calculate_addresses(&nat_table->table, base_addr); + ipa_table_calculate_addresses(&nat_table->index_table, base_addr); + + ipa_table_reset(&nat_table->table); + ipa_table_reset(&nat_table->index_table); + + ipa_nati_create_table_dma_cmd_helpers(nat_table, table_index); + + goto done; + +#ifdef IPA_ON_R3PC +bail_mem_desc: + ipa_mem_descriptor_delete(&nat_table->mem_desc, nat_cache_ptr->ipa_desc->fd); +#endif + +bail_meta: + free(nat_table->index_expn_table_meta); + memset(nat_table, 0, sizeof(*nat_table)); + +done: + IPADBG("Out\n"); + + return ret; +} + +static int ipa_nati_destroy_table( + struct ipa_nat_cache* nat_cache_ptr, + struct ipa_nat_ip4_table_cache* nat_table) +{ + int ret; + + IPADBG("In\n"); + + ret = ipa_mem_descriptor_delete( + &nat_table->mem_desc, nat_cache_ptr->ipa_desc->fd); + + if (ret) + IPAERR("unable to delete NAT descriptor\n"); + + free(nat_table->index_expn_table_meta); + + memset(nat_table, 0, sizeof(*nat_table)); + + IPADBG("Out\n"); + + return ret; +} + +static int ipa_nati_post_ipv4_init_cmd( + struct ipa_nat_cache* nat_cache_ptr, + struct ipa_nat_ip4_table_cache* nat_table, + uint8_t tbl_index, + bool focus_change ) +{ + struct ipa_ioc_v4_nat_init cmd; + + char buf[1024]; + int ret; + + IPADBG("In\n"); + + IPADBG("nat_cache_ptr(%p) nat_table(%p) tbl_index(%u) focus_change(%u)\n", + nat_cache_ptr, nat_table, tbl_index, focus_change); + + memset(&cmd, 0, sizeof(cmd)); + + cmd.tbl_index = tbl_index; + cmd.focus_change = focus_change; + + cmd.mem_type = nat_cache_ptr->nmi; + + cmd.ipv4_rules_offset = + nat_table->mem_desc.addr_offset; + + cmd.expn_rules_offset = + cmd.ipv4_rules_offset + + (nat_table->table.table_entries * sizeof(struct ipa_nat_rule)); + + cmd.index_offset = + cmd.expn_rules_offset + + (nat_table->table.expn_table_entries * sizeof(struct ipa_nat_rule)); + + cmd.index_expn_offset = + cmd.index_offset + + (nat_table->index_table.table_entries * sizeof(struct ipa_nat_indx_tbl_rule)); + + /* + * Driverr/HW expected base table size to be power^2-1 due to H/W + * hash calculation + */ + cmd.table_entries = + nat_table->table.table_entries - 1; + cmd.expn_table_entries = + nat_table->table.expn_table_entries; + + cmd.ip_addr = nat_table->public_addr; + + IPADBG("%s\n", ipa_ioc_v4_nat_init_as_str(&cmd, buf, sizeof(buf))); + + ret = ioctl(nat_cache_ptr->ipa_desc->fd, IPA_IOC_V4_INIT_NAT, &cmd); + + if (ret) { + IPAERR("unable to post init cmd Error: %d IPA fd %d\n", + ret, nat_cache_ptr->ipa_desc->fd); + goto bail; + } + + IPADBG("Posted IPA_IOC_V4_INIT_NAT to kernel successfully\n"); + +bail: + IPADBG("Out\n"); + + return ret; +} + +static void ipa_nati_copy_second_index_entry_to_head( + struct ipa_nat_ip4_table_cache* nat_table, + ipa_table_iterator* index_table_iterator, + struct ipa_ioc_nat_dma_cmd* cmd) +{ + uint16_t index; + struct ipa_nat_rule* table; + struct ipa_nat_indx_tbl_rule* index_table_rule = + (struct ipa_nat_indx_tbl_rule*)index_table_iterator->next_entry; + + IPADBG("In\n"); + + /* + * The DMA command for field tbl_entry already added by the + * index_table.ipa_table_create_delete_command() + */ + ipa_table_add_dma_cmd( + &nat_table->index_table, + HELP_UPDATE_ENTRY, + index_table_iterator->curr_entry, + index_table_iterator->curr_index, + index_table_rule->next_index, + cmd); + + /* Change the indx_tbl_entry field in the related table rule */ + if (index_table_rule->tbl_entry < nat_table->table.table_entries) { + index = index_table_rule->tbl_entry; + table = (struct ipa_nat_rule*)nat_table->table.table_addr; + } else { + index = index_table_rule->tbl_entry - nat_table->table.table_entries; + table = (struct ipa_nat_rule*)nat_table->table.expn_table_addr; + } + + table[index].indx_tbl_entry = index_table_iterator->curr_index; + + IPADBG("Out\n"); +} + +/** + * dst_hash() - Find the index into ipv4 base table + * @public_ip: [in] public_ip + * @trgt_ip: [in] Target IP address + * @trgt_port: [in] Target port + * @public_port: [in] Public port + * @proto: [in] Protocol (TCP/IP) + * @size: [in] size of the ipv4 base Table + * + * This hash method is used to find the hash index of new nat + * entry into ipv4 base table. In case of zero index, the + * new entry will be stored into N-1 index where N is size of + * ipv4 base table + * + * Returns: >0 index into ipv4 base table, negative on failure + */ +static uint16_t dst_hash( + struct ipa_nat_cache* nat_cache_ptr, + uint32_t public_ip, + uint32_t trgt_ip, + uint16_t trgt_port, + uint16_t public_port, + uint8_t proto, + uint16_t size) +{ + uint16_t hash = + ((uint16_t)(trgt_ip)) ^ + ((uint16_t)(trgt_ip >> 16)) ^ + (trgt_port) ^ + (public_port) ^ + (proto); + + IPADBG("In\n"); + + IPADBG("public_ip: 0x%08X public_port: 0x%04X\n", public_ip, public_port); + IPADBG("target_ip: 0x%08X target_port: 0x%04X\n", trgt_ip, trgt_port); + IPADBG("proto: 0x%02X size: 0x%04X\n", proto, size); + + if (nat_cache_ptr->ipa_desc->ver >= IPA_HW_v4_0) + hash ^= + ((uint16_t)(public_ip)) ^ + ((uint16_t)(public_ip >> 16)); + + /* + * The size passed to hash function expected be power^2-1, while + * the actual size is power^2, actual_size = size + 1 + */ + hash = (hash & size); + + /* + * If the hash resulted to zero then set it to maximum value as + * zero is unused entry in nat tables + */ + if (hash == 0) { + hash = size; + } + + IPADBG("dst_hash returning value: %d\n", hash); + + IPADBG("Out\n"); + + return hash; +} + +/** + * src_hash() - Find the index into ipv4 index base table + * @priv_ip: [in] Private IP address + * @priv_port: [in] Private port + * @trgt_ip: [in] Target IP address + * @trgt_port: [in] Target Port + * @proto: [in] Protocol (TCP/IP) + * @size: [in] size of the ipv4 index base Table + * + * This hash method is used to find the hash index of new nat + * entry into ipv4 index base table. In case of zero index, the + * new entry will be stored into N-1 index where N is size of + * ipv4 index base table + * + * Returns: >0 index into ipv4 index base table, negative on failure + */ +static uint16_t src_hash( + uint32_t priv_ip, + uint16_t priv_port, + uint32_t trgt_ip, + uint16_t trgt_port, + uint8_t proto, + uint16_t size) +{ + uint16_t hash = + ((uint16_t)(priv_ip)) ^ + ((uint16_t)(priv_ip >> 16)) ^ + (priv_port) ^ + ((uint16_t)(trgt_ip)) ^ + ((uint16_t)(trgt_ip >> 16)) ^ + (trgt_port) ^ + (proto); + + IPADBG("In\n"); + + IPADBG("private_ip: 0x%08X private_port: 0x%04X\n", priv_ip, priv_port); + IPADBG(" target_ip: 0x%08X target_port: 0x%04X\n", trgt_ip, trgt_port); + IPADBG("proto: 0x%02X size: 0x%04X\n", proto, size); + + /* + * The size passed to hash function expected be power^2-1, while + * the actual size is power^2, actual_size = size + 1 + */ + hash = (hash & size); + + /* + * If the hash resulted to zero then set it to maximum value as + * zero is unused entry in nat tables + */ + if (hash == 0) { + hash = size; + } + + IPADBG("src_hash returning value: %d\n", hash); + + IPADBG("Out\n"); + + return hash; +} + +static int ipa_nati_post_ipv4_dma_cmd( + struct ipa_nat_cache* nat_cache_ptr, + struct ipa_ioc_nat_dma_cmd* cmd) +{ + char buf[4096]; + int ret = 0; + + IPADBG("In\n"); + + cmd->mem_type = nat_cache_ptr->nmi; + + IPADBG("%s\n", prep_ioc_nat_dma_cmd_4print(cmd, buf, sizeof(buf))); + + if (ioctl(nat_cache_ptr->ipa_desc->fd, IPA_IOC_TABLE_DMA_CMD, cmd)) { + IPAERR("ioctl (IPA_IOC_TABLE_DMA_CMD) on fd %d has failed\n", + nat_cache_ptr->ipa_desc->fd); + ret = -EIO; + goto bail; + } + + IPADBG("Posted IPA_IOC_TABLE_DMA_CMD to kernel successfully\n"); + +bail: + IPADBG("Out\n"); + + return ret; +} + +/* + * ---------------------------------------------------------------------------- + * API functions exposed to the upper layers + * ---------------------------------------------------------------------------- + */ +int ipa_nati_modify_pdn( + struct ipa_ioc_nat_pdn_entry *entry) +{ + struct ipa_nat_cache* nat_cache_ptr; + int ret = 0; + + IPADBG("In\n"); + + nat_cache_ptr = + (ipv4_nat_cache[IPA_NAT_MEM_IN_DDR].ipa_desc) ? + &ipv4_nat_cache[IPA_NAT_MEM_IN_DDR] : + &ipv4_nat_cache[IPA_NAT_MEM_IN_SRAM]; + + if ( nat_cache_ptr->ipa_desc == NULL ) + { + IPAERR("Uninitialized cache file descriptor\n"); + ret = -EIO; + goto done; + } + + if (entry->public_ip == 0) + IPADBG("PDN %d public ip will be set to 0\n", entry->pdn_index); + + ret = ioctl(nat_cache_ptr->ipa_desc->fd, IPA_IOC_NAT_MODIFY_PDN, entry); + + if ( ret ) { + IPAERR("unable to call modify pdn icotl\nindex %d, ip 0x%X, src_metdata 0x%X, dst_metadata 0x%X IPA fd %d\n", + entry->pdn_index, + entry->public_ip, + entry->src_metadata, + entry->dst_metadata, + nat_cache_ptr->ipa_desc->fd); + goto done; + } + + pdns[entry->pdn_index].public_ip = entry->public_ip; + pdns[entry->pdn_index].dst_metadata = entry->dst_metadata; + pdns[entry->pdn_index].src_metadata = entry->src_metadata; + + IPADBG("posted IPA_IOC_NAT_MODIFY_PDN to kernel successfully and stored in cache\n index %d, ip 0x%X, src_metdata 0x%X, dst_metadata 0x%X\n", + entry->pdn_index, + entry->public_ip, + entry->src_metadata, + entry->dst_metadata); +done: + IPADBG("Out\n"); + + return ret; +} + +int ipa_nati_get_pdn_index( + uint32_t public_ip, + uint8_t *pdn_index) +{ + int i = 0; + + for(i = 0; i < (IPA_MAX_PDN_NUM - 1); i++) { + if(pdns[i].public_ip == public_ip) { + IPADBG("ip 0x%X matches PDN index %d\n", public_ip, i); + *pdn_index = i; + return 0; + } + } + + IPAERR("ip 0x%X does not match any PDN\n", public_ip); + + return -EIO; +} + +int ipa_nati_alloc_pdn( + ipa_nat_pdn_entry *pdn_info, + uint8_t *pdn_index) +{ + ipa_nat_pdn_entry zero_test; + struct ipa_ioc_nat_pdn_entry pdn_data; + int i, ret; + + IPADBG("alloc PDN for ip 0x%x\n", pdn_info->public_ip); + + memset(&zero_test, 0, sizeof(zero_test)); + + if(num_pdns >= (IPA_MAX_PDN_NUM - 1)) { + IPAERR("exceeded max num of PDNs, num_pdns %d\n", num_pdns); + return -EIO; + } + + for(i = 0; i < (IPA_MAX_PDN_NUM - 1); i++) { + if(pdns[i].public_ip == pdn_info->public_ip) + { + IPADBG("found the same pdn in index %d\n", i); + *pdn_index = i; + if((pdns[i].src_metadata != pdn_info->src_metadata) || + (pdns[i].dst_metadata != pdn_info->dst_metadata)) + { + IPAERR("WARNING: metadata values don't match! [%d, %d], [%d, %d]\n\n", + pdns[i].src_metadata, pdn_info->src_metadata, + pdns[i].dst_metadata, pdn_info->dst_metadata); + } + return 0; + } + + if(!memcmp((pdns + i), &zero_test, sizeof(ipa_nat_pdn_entry))) + { + IPADBG("found an empty pdn in index %d\n", i); + break; + } + } + + if(i >= (IPA_MAX_PDN_NUM - 1)) + { + IPAERR("couldn't find an empty entry while num is %d\n", + num_pdns); + return -EIO; + } + + pdn_data.pdn_index = i; + pdn_data.public_ip = pdn_info->public_ip; + pdn_data.src_metadata = pdn_info->src_metadata; + pdn_data.dst_metadata = pdn_info->dst_metadata; + + ret = ipa_nati_modify_pdn(&pdn_data); + if(!ret) + { + num_pdns++; + *pdn_index = i; + IPADBG("modify num_pdns (%d)\n", num_pdns); + } + + return ret; +} + +int ipa_nati_get_pdn_cnt(void) +{ + return num_pdns; +} + +int ipa_nati_dealloc_pdn( + uint8_t pdn_index) +{ + ipa_nat_pdn_entry zero_test; + struct ipa_ioc_nat_pdn_entry pdn_data; + int ret; + + IPADBG(" trying to deallocate PDN index %d\n", pdn_index); + + if(!num_pdns) + { + IPAERR("pdn table is already empty\n"); + return -EIO; + } + + memset(&zero_test, 0, sizeof(zero_test)); + + if(!memcmp((pdns + pdn_index), &zero_test, sizeof(ipa_nat_pdn_entry))) + { + IPAERR("pdn entry is a zero entry\n"); + return -EIO; + } + + IPADBG("PDN in index %d has ip 0x%X\n", pdn_index, pdns[pdn_index].public_ip); + + pdn_data.pdn_index = pdn_index; + pdn_data.src_metadata = 0; + pdn_data.dst_metadata = 0; + pdn_data.public_ip = 0; + + ret = ipa_nati_modify_pdn(&pdn_data); + if(ret) + { + IPAERR("failed modifying PDN\n"); + return -EIO; + } + + memset((pdns + pdn_index), 0, sizeof(ipa_nat_pdn_entry)); + + num_pdns--; + + IPADBG("successfully removed pdn from index %d num_pdns %d\n", pdn_index, num_pdns); + + return 0; +} + +/* + * ---------------------------------------------------------------------------- + * Previously public API functions, but have been hijacked (in + * ipa_nat_statemach.c). The new definitions that replaced these, now + * call the functions below. + * ---------------------------------------------------------------------------- + */ +int ipa_NATI_post_ipv4_init_cmd( + uint32_t tbl_hdl ) +{ + enum ipa3_nat_mem_in nmi; + struct ipa_nat_cache* nat_cache_ptr; + struct ipa_nat_ip4_table_cache* nat_table; + int ret; + + IPADBG("In\n"); + + BREAK_TBL_HDL(tbl_hdl, nmi, tbl_hdl); + + if ( ! IPA_VALID_NAT_MEM_IN(nmi) ) { + IPAERR("Bad cache type argument passed\n"); + ret = -EINVAL; + goto bail; + } + + IPADBG("nmi(%s)\n", ipa3_nat_mem_in_as_str(nmi)); + + nat_cache_ptr = &ipv4_nat_cache[nmi]; + + if (pthread_mutex_lock(&nat_mutex)) { + IPAERR("unable to lock the nat mutex\n"); + ret = -EINVAL; + goto bail; + } + + if ( ! nat_cache_ptr->table_cnt ) { + IPAERR("No initialized table in NAT cache\n"); + ret = -EINVAL; + goto unlock; + } + + nat_table = &nat_cache_ptr->ip4_tbl[tbl_hdl - 1]; + + ret = ipa_nati_post_ipv4_init_cmd( + nat_cache_ptr, + nat_table, + tbl_hdl - 1, + true); + + if (ret) { + IPAERR("unable to post nat_init command Error %d\n", ret); + goto unlock; + } + + active_nat_cache_ptr = nat_cache_ptr; + +unlock: + if (pthread_mutex_unlock(&nat_mutex)) { + IPAERR("unable to unlock the nat mutex\n"); + ret = (ret) ? ret : -EPERM; + } + +bail: + IPADBG("Out\n"); + + return ret; +} + +/** + * ipa_NATI_add_ipv4_tbl() - Adds a new IPv4 NAT table + * @ct: [in] the desired cache type to use + * @public_ip_addr: [in] public IPv4 address + * @number_of_entries: [in] number of NAT entries + * @table_handle: [out] handle of new IPv4 NAT table + * + * This function creates new IPv4 NAT table and posts IPv4 NAT init command to HW + * + * Returns: 0 On Success, negative on failure + */ +int ipa_NATI_add_ipv4_tbl( + enum ipa3_nat_mem_in nmi, + uint32_t public_ip_addr, + uint16_t number_of_entries, + uint32_t* tbl_hdl ) +{ + struct ipa_nat_cache* nat_cache_ptr; + struct ipa_nat_ip4_table_cache* nat_table; + int ret = 0; + + IPADBG("In\n"); + + *tbl_hdl = 0; + + if ( ! IPA_VALID_NAT_MEM_IN(nmi) ) { + IPAERR("Bad cache type argument passed\n"); + ret = -EINVAL; + goto bail; + } + + IPADBG("nmi(%s)\n", ipa3_nat_mem_in_as_str(nmi)); + + nat_cache_ptr = &ipv4_nat_cache[nmi]; + + if (pthread_mutex_lock(&nat_mutex)) { + IPAERR("unable to lock the nat mutex\n"); + ret = -EINVAL; + goto bail; + } + + nat_cache_ptr->nmi = nmi; + + if (nat_cache_ptr->table_cnt >= IPA_NAT_MAX_IP4_TBLS) { + IPAERR( + "Can't add addition NAT table. Maximum %d tables allowed\n", + IPA_NAT_MAX_IP4_TBLS); + ret = -EINVAL; + goto unlock; + } + + if ( ! nat_cache_ptr->ipa_desc ) { + nat_cache_ptr->ipa_desc = ipa_descriptor_open(); + if ( nat_cache_ptr->ipa_desc == NULL ) { + IPAERR("failed to open IPA driver file descriptor\n"); + ret = -EIO; + goto unlock; + } + } + + nat_table = &nat_cache_ptr->ip4_tbl[nat_cache_ptr->table_cnt]; + + ret = ipa_nati_create_table( + nat_cache_ptr, + nat_table, + public_ip_addr, + number_of_entries, + nat_cache_ptr->table_cnt); + + if (ret) { + IPAERR("unable to create nat table Error: %d\n", ret); + goto failed_create_table; + } + + /* + * Initialize the ipa hw with nat table dimensions + */ + ret = ipa_nati_post_ipv4_init_cmd( + nat_cache_ptr, + nat_table, + nat_cache_ptr->table_cnt, + false); + + if (ret) { + IPAERR("unable to post nat_init command Error %d\n", ret); + goto failed_post_init_cmd; + } + + active_nat_cache_ptr = nat_cache_ptr; + + /* + * Store the initial public ip address in the cached pdn table + * this is backward compatible for pre IPAv4 versions, we will + * always use this ip as the single PDN address + */ + pdns[0].public_ip = public_ip_addr; + num_pdns = 1; + + nat_cache_ptr->table_cnt++; + + /* + * Return table handle + */ + *tbl_hdl = MAKE_TBL_HDL(nat_cache_ptr->table_cnt, nmi); + + IPADBG("tbl_hdl value(0x%08X) num_pdns (%d)\n", *tbl_hdl, num_pdns); + + goto unlock; + +failed_post_init_cmd: + ipa_nati_destroy_table(nat_cache_ptr, nat_table); + +failed_create_table: + if (!nat_cache_ptr->table_cnt) { + ipa_descriptor_close(nat_cache_ptr->ipa_desc); + nat_cache_ptr->ipa_desc = NULL; + } + +unlock: + if (pthread_mutex_unlock(&nat_mutex)) { + IPAERR("unable to unlock the nat mutex\n"); + ret = -EPERM; + goto bail; + } + +bail: + IPADBG("Out\n"); + + return ret; +} + +int ipa_NATI_del_ipv4_table( + uint32_t tbl_hdl ) +{ + enum ipa3_nat_mem_in nmi; + struct ipa_nat_cache* nat_cache_ptr; + struct ipa_nat_ip4_table_cache* nat_table; + + int ret; + + IPADBG("In\n"); + + BREAK_TBL_HDL(tbl_hdl, nmi, tbl_hdl); + + if ( ! IPA_VALID_NAT_MEM_IN(nmi) ) { + IPAERR("Bad cache type argument passed\n"); + ret = -EINVAL; + goto bail; + } + + IPADBG("nmi(%s)\n", ipa3_nat_mem_in_as_str(nmi)); + + nat_cache_ptr = &ipv4_nat_cache[nmi]; + + nat_table = &nat_cache_ptr->ip4_tbl[tbl_hdl - 1]; + + if (pthread_mutex_lock(&nat_mutex)) { + IPAERR("unable to lock the nat mutex\n"); + ret = -EINVAL; + goto bail; + } + + if (! nat_table->mem_desc.valid) { + IPAERR("invalid table handle %d\n", tbl_hdl); + ret = -EINVAL; + goto unlock; + } + + ret = ipa_nati_destroy_table(nat_cache_ptr, nat_table); + if (ret) { + IPAERR("unable to delete NAT table with handle %d\n", tbl_hdl); + goto unlock; + } + + if (! --nat_cache_ptr->table_cnt) { + ipa_descriptor_close(nat_cache_ptr->ipa_desc); + nat_cache_ptr->ipa_desc = NULL; + } + +unlock: + if (pthread_mutex_unlock(&nat_mutex)) { + IPAERR("unable to unlock the nat mutex\n"); + ret = (ret) ? ret : -EPERM; + } + +bail: + IPADBG("Out\n"); + + return ret; +} + +int ipa_NATI_query_timestamp( + uint32_t tbl_hdl, + uint32_t rule_hdl, + uint32_t* time_stamp ) +{ + enum ipa3_nat_mem_in nmi; + struct ipa_nat_cache* nat_cache_ptr; + struct ipa_nat_ip4_table_cache* nat_table; + struct ipa_nat_rule* rule_ptr; + + char buf[1024]; + int ret; + + IPADBG("In\n"); + + BREAK_TBL_HDL(tbl_hdl, nmi, tbl_hdl); + + if ( ! IPA_VALID_NAT_MEM_IN(nmi) ) { + IPAERR("Bad cache type argument passed\n"); + ret = -EINVAL; + goto bail; + } + + IPADBG("nmi(%s)\n", ipa3_nat_mem_in_as_str(nmi)); + + nat_cache_ptr = &ipv4_nat_cache[nmi]; + + nat_table = &nat_cache_ptr->ip4_tbl[tbl_hdl - 1]; + + if (pthread_mutex_lock(&nat_mutex)) { + IPAERR("unable to lock the nat mutex\n"); + ret = -EINVAL; + goto bail; + } + + if ( ! nat_table->mem_desc.valid ) { + IPAERR("invalid table handle %d\n", tbl_hdl); + ret = -EINVAL; + goto unlock; + } + + ret = ipa_table_get_entry( + &nat_table->table, + rule_hdl, + (void**) &rule_ptr, + NULL); + + if (ret) { + IPAERR("Unable to retrive the entry with " + "handle=%u in NAT table with handle=0x%08X\n", + rule_hdl, tbl_hdl); + goto unlock; + } + + IPADBG("rule_hdl(0x%08X) -> %s\n", + rule_hdl, + prep_nat_rule_4print(rule_ptr, buf, sizeof(buf))); + + *time_stamp = rule_ptr->time_stamp; + +unlock: + if (pthread_mutex_unlock(&nat_mutex)) { + IPAERR("unable to unlock the nat mutex\n"); + ret = (ret) ? ret : -EPERM; + } + +bail: + IPADBG("Out\n"); + + return ret; +} + +int ipa_NATI_add_ipv4_rule( + uint32_t tbl_hdl, + const ipa_nat_ipv4_rule* clnt_rule, + uint32_t* rule_hdl) +{ + uint32_t cmd_sz = + sizeof(struct ipa_ioc_nat_dma_cmd) + + (MAX_DMA_ENTRIES_FOR_ADD * sizeof(struct ipa_ioc_nat_dma_one)); + char cmd_buf[cmd_sz]; + struct ipa_ioc_nat_dma_cmd* cmd = + (struct ipa_ioc_nat_dma_cmd*) cmd_buf; + + enum ipa3_nat_mem_in nmi; + struct ipa_nat_cache* nat_cache_ptr; + struct ipa_nat_ip4_table_cache* nat_table; + struct ipa_nat_rule* rule; + + uint16_t new_entry_index; + uint16_t new_index_tbl_entry_index; + uint32_t new_entry_handle; + char buf[1024]; + + int ret = 0; + + IPADBG("In\n"); + + memset(cmd_buf, 0, sizeof(cmd_buf)); + + if ( ! VALID_TBL_HDL(tbl_hdl) || + ! clnt_rule || + ! rule_hdl ) + { + IPAERR("Bad arg: tbl_hdl(0x%08X) and/or clnt_rule(%p) and/or rule_hdl(%p)\n", + tbl_hdl, clnt_rule, rule_hdl); + ret = -EINVAL; + goto done; + } + + *rule_hdl = 0; + + IPADBG("tbl_hdl(0x%08X)\n", tbl_hdl); + + BREAK_TBL_HDL(tbl_hdl, nmi, tbl_hdl); + + if ( ! IPA_VALID_NAT_MEM_IN(nmi) ) { + IPAERR("Bad cache type argument passed\n"); + ret = -EINVAL; + goto done; + } + + IPADBG("tbl_hdl(0x%08X) nmi(%s) %s\n", + tbl_hdl, + ipa3_nat_mem_in_as_str(nmi), + prep_nat_ipv4_rule_4print(clnt_rule, buf, sizeof(buf))); + + nat_cache_ptr = &ipv4_nat_cache[nmi]; + + nat_table = &nat_cache_ptr->ip4_tbl[tbl_hdl - 1]; + + if (clnt_rule->protocol == IPAHAL_NAT_INVALID_PROTOCOL) { + IPAERR("invalid parameter protocol=%d\n", clnt_rule->protocol); + ret = -EINVAL; + goto done; + } + + /* + * Verify that the rule's PDN is valid + */ + if (clnt_rule->pdn_index >= IPA_MAX_PDN_NUM || + pdns[clnt_rule->pdn_index].public_ip == 0) { + IPAERR("invalid parameters, pdn index %d, public ip = 0x%X\n", + clnt_rule->pdn_index, pdns[clnt_rule->pdn_index].public_ip); + ret = -EINVAL; + goto done; + } + + if (pthread_mutex_lock(&nat_mutex)) { + IPAERR("unable to lock the nat mutex\n"); + ret = -EINVAL; + goto done; + } + + if (! nat_table->mem_desc.valid) { + IPAERR("invalid table handle %d\n", tbl_hdl); + ret = -EINVAL; + goto unlock; + } + + /* src_only */ + if (clnt_rule->src_only) { + new_entry_index = dst_hash( + nat_cache_ptr, + pdns[clnt_rule->pdn_index].public_ip, + clnt_rule->target_ip, + clnt_rule->target_port, + clnt_rule->public_port, + clnt_rule->protocol, + nat_table->table.table_entries - 1) + Hash_token; + new_entry_index = (new_entry_index & (nat_table->table.table_entries - 1)); + if (new_entry_index == 0) { + new_entry_index = nat_table->table.table_entries - 1; + } + Hash_token++; + } else { + new_entry_index = dst_hash( + nat_cache_ptr, + pdns[clnt_rule->pdn_index].public_ip, + clnt_rule->target_ip, + clnt_rule->target_port, + clnt_rule->public_port, + clnt_rule->protocol, + nat_table->table.table_entries - 1); + } + + ret = ipa_table_add_entry( + &nat_table->table, + (void*) clnt_rule, + &new_entry_index, + &new_entry_handle, + cmd); + + if (ret) { + IPAERR("Failed to add a new NAT entry\n"); + goto unlock; + } + + /* dst_only */ + if (clnt_rule->dst_only) { + new_index_tbl_entry_index = + src_hash(clnt_rule->private_ip, + clnt_rule->private_port, + clnt_rule->target_ip, + clnt_rule->target_port, + clnt_rule->protocol, + nat_table->table.table_entries - 1) + Hash_token; + new_index_tbl_entry_index = (new_index_tbl_entry_index & (nat_table->table.table_entries - 1)); + if (new_index_tbl_entry_index == 0) { + new_index_tbl_entry_index = nat_table->table.table_entries - 1; + } + Hash_token++; + } else { + new_index_tbl_entry_index = + src_hash(clnt_rule->private_ip, + clnt_rule->private_port, + clnt_rule->target_ip, + clnt_rule->target_port, + clnt_rule->protocol, + nat_table->table.table_entries - 1); + } + ret = ipa_table_add_entry( + &nat_table->index_table, + (void*) &new_entry_index, + &new_index_tbl_entry_index, + NULL, + cmd); + + if (ret) { + IPAERR("failed to add a new NAT index entry\n"); + goto fail_add_index_entry; + } + + rule = ipa_table_get_entry_by_index( + &nat_table->table, + new_entry_index); + + if (rule == NULL) { + IPAERR("Failed to retrieve the entry in index %d for NAT table with handle=%d\n", + new_entry_index, tbl_hdl); + ret = -EPERM; + goto bail; + } + + rule->indx_tbl_entry = new_index_tbl_entry_index; + + rule->redirect = clnt_rule->redirect; + rule->enable = clnt_rule->enable; + rule->time_stamp = clnt_rule->time_stamp; + + IPADBG("new entry:%d, new index entry: %d\n", + new_entry_index, new_index_tbl_entry_index); + + IPADBG("rule_hdl(0x%08X) -> %s\n", + new_entry_handle, + prep_nat_rule_4print(rule, buf, sizeof(buf))); + + ret = ipa_nati_post_ipv4_dma_cmd(nat_cache_ptr, cmd); + + if (ret) { + IPAERR("unable to post dma command\n"); + goto bail; + } + + if (pthread_mutex_unlock(&nat_mutex)) { + IPAERR("unable to unlock the nat mutex\n"); + ret = -EPERM; + goto done; + } + + *rule_hdl = new_entry_handle; + + IPADBG("rule_hdl value(%u)\n", *rule_hdl); + + goto done; + +bail: + ipa_table_erase_entry(&nat_table->index_table, new_index_tbl_entry_index); + +fail_add_index_entry: + ipa_table_erase_entry(&nat_table->table, new_entry_index); + +unlock: + if (pthread_mutex_unlock(&nat_mutex)) + IPAERR("unable to unlock the nat mutex\n"); +done: + IPADBG("Out\n"); + + return ret; +} + +int ipa_NATI_del_ipv4_rule( + uint32_t tbl_hdl, + uint32_t rule_hdl ) +{ + uint32_t cmd_sz = + sizeof(struct ipa_ioc_nat_dma_cmd) + + (MAX_DMA_ENTRIES_FOR_DEL * sizeof(struct ipa_ioc_nat_dma_one)); + char cmd_buf[cmd_sz]; + struct ipa_ioc_nat_dma_cmd* cmd = + (struct ipa_ioc_nat_dma_cmd*) cmd_buf; + + enum ipa3_nat_mem_in nmi; + struct ipa_nat_cache* nat_cache_ptr; + struct ipa_nat_ip4_table_cache* nat_table; + struct ipa_nat_rule* table_rule; + struct ipa_nat_indx_tbl_rule* index_table_rule; + + ipa_table_iterator table_iterator; + ipa_table_iterator index_table_iterator; + + uint16_t index; + char buf[1024]; + int ret = 0; + + IPADBG("In\n"); + + memset(cmd_buf, 0, sizeof(cmd_buf)); + + IPADBG("tbl_hdl(0x%08X) rule_hdl(%u)\n", tbl_hdl, rule_hdl); + + BREAK_TBL_HDL(tbl_hdl, nmi, tbl_hdl); + + if ( ! IPA_VALID_NAT_MEM_IN(nmi) ) { + IPAERR("Bad cache type argument passed\n"); + ret = -EINVAL; + goto done; + } + + IPADBG("nmi(%s)\n", ipa3_nat_mem_in_as_str(nmi)); + + nat_cache_ptr = &ipv4_nat_cache[nmi]; + + nat_table = &nat_cache_ptr->ip4_tbl[tbl_hdl - 1]; + + if (pthread_mutex_lock(&nat_mutex)) { + IPAERR("Unable to lock the nat mutex\n"); + ret = -EINVAL; + goto done; + } + + if (! nat_table->mem_desc.valid) { + IPAERR("Invalid table handle 0x%08X\n", tbl_hdl); + ret = -EINVAL; + goto unlock; + } + + ret = ipa_table_get_entry( + &nat_table->table, + rule_hdl, + (void**) &table_rule, + &index); + + if (ret) { + IPAERR("Unable to retrive the entry with rule_hdl=%u\n", rule_hdl); + goto unlock; + } + + IPADBG("rule_hdl(0x%08X) -> %s\n", + rule_hdl, + prep_nat_rule_4print(table_rule, buf, sizeof(buf))); + + ret = ipa_table_iterator_init( + &table_iterator, + &nat_table->table, + table_rule, + index); + + if (ret) { + IPAERR("Unable to create iterator which points to the " + "entry %u in NAT table with handle=0x%08X\n", + index, tbl_hdl); + goto unlock; + } + + index = table_rule->indx_tbl_entry; + + index_table_rule = (struct ipa_nat_indx_tbl_rule*) + ipa_table_get_entry_by_index(&nat_table->index_table, index); + + if (index_table_rule == NULL) { + IPAERR("Unable to retrieve the entry in index %u " + "in NAT index table with handle=0x%08X\n", + index, tbl_hdl); + ret = -EPERM; + goto unlock; + } + + ret = ipa_table_iterator_init( + &index_table_iterator, + &nat_table->index_table, + index_table_rule, + index); + + if (ret) { + IPAERR("Unable to create iterator which points to the " + "entry %u in NAT index table with handle=0x%08X\n", + index, tbl_hdl); + goto unlock; + } + + ipa_table_create_delete_command( + &nat_table->index_table, + cmd, + &index_table_iterator); + + if (ipa_table_iterator_is_head_with_tail(&index_table_iterator)) { + + ipa_nati_copy_second_index_entry_to_head( + nat_table, &index_table_iterator, cmd); + /* + * Iterate to the next entry which should be deleted + */ + ret = ipa_table_iterator_next( + &index_table_iterator, &nat_table->index_table); + + if (ret) { + IPAERR("Unable to move the iterator to the next entry " + "(points to the entry %u in NAT index table)\n", + index); + goto unlock; + } + } + + ipa_table_create_delete_command( + &nat_table->table, + cmd, + &table_iterator); + + ret = ipa_nati_post_ipv4_dma_cmd(nat_cache_ptr, cmd); + + if (ret) { + IPAERR("Unable to post dma command\n"); + goto unlock; + } + + if (! ipa_table_iterator_is_head_with_tail(&table_iterator)) { + /* The entry can be deleted */ + uint8_t is_prev_empty = + (table_iterator.prev_entry != NULL && + ((struct ipa_nat_rule*)table_iterator.prev_entry)->protocol == + IPAHAL_NAT_INVALID_PROTOCOL); + + ipa_table_delete_entry( + &nat_table->table, &table_iterator, is_prev_empty); + } + + ipa_table_delete_entry( + &nat_table->index_table, + &index_table_iterator, + FALSE); + + if (index_table_iterator.curr_index >= nat_table->index_table.table_entries) + nat_table->index_expn_table_meta[ + index_table_iterator.curr_index - nat_table->index_table.table_entries]. + prev_index = IPA_TABLE_INVALID_ENTRY; + +unlock: + if (pthread_mutex_unlock(&nat_mutex)) { + IPAERR("Unable to unlock the nat mutex\n"); + ret = (ret) ? ret : -EPERM; + } + +done: + IPADBG("Out\n"); + + return ret; +} + +/* + * ---------------------------------------------------------------------------- + * New function to get sram size. + * ---------------------------------------------------------------------------- + */ +int ipa_nati_get_sram_size( + uint32_t* size_ptr) +{ + struct ipa_nat_cache* nat_cache_ptr = + &ipv4_nat_cache[IPA_NAT_MEM_IN_SRAM]; + struct ipa_nat_in_sram_info nat_sram_info; + int ret; + + IPADBG("In\n"); + + if (pthread_mutex_lock(&nat_mutex)) { + IPAERR("unable to lock the nat mutex\n"); + ret = -EINVAL; + goto bail; + } + + if ( ! nat_cache_ptr->ipa_desc ) { + nat_cache_ptr->ipa_desc = ipa_descriptor_open(); + if ( nat_cache_ptr->ipa_desc == NULL ) { + IPAERR("failed to open IPA driver file descriptor\n"); + ret = -EIO; + goto unlock; + } + } + + memset(&nat_sram_info, 0, sizeof(nat_sram_info)); + + ret = ioctl(nat_cache_ptr->ipa_desc->fd, + IPA_IOC_GET_NAT_IN_SRAM_INFO, + &nat_sram_info); + + if (ret) { + IPAERR("NAT_IN_SRAM_INFO ioctl failure %d on IPA fd %d\n", + ret, nat_cache_ptr->ipa_desc->fd); + goto unlock; + } + + if ( (*size_ptr = nat_sram_info.sram_mem_available_for_nat) == 0 ) + { + IPAERR("sram_mem_available_for_nat is zero\n"); + ret = -EINVAL; + goto unlock; + } + +unlock: + if (pthread_mutex_unlock(&nat_mutex)) { + IPAERR("unable to unlock the nat mutex\n"); + ret = (ret) ? ret : -EPERM; + } + +bail: + IPADBG("Out\n"); + + return ret; +} + +/* + * ---------------------------------------------------------------------------- + * Utility functions + * ---------------------------------------------------------------------------- + */ +static int print_nat_rule( + ipa_table* table_ptr, + uint32_t rule_hdl, + void* record_ptr, + uint16_t record_index, + void* meta_record_ptr, + uint16_t meta_record_index, + void* arb_data_ptr ) +{ + enum ipa3_nat_mem_in nmi; + uint8_t is_expn_tbl; + uint16_t rule_index; + + char buf[1024]; + + struct ipa_nat_rule* rule_ptr = + (struct ipa_nat_rule*) record_ptr; + + if ( rule_ptr->protocol == IPA_NAT_INVALID_PROTO_FIELD_VALUE_IN_RULE ) + { + goto bail; + } + + BREAK_RULE_HDL(table_ptr, rule_hdl, nmi, is_expn_tbl, rule_index); + + printf(" %s %s (0x%04X) (0x%08X) -> %s\n", + (table_ptr->nmi == IPA_NAT_MEM_IN_DDR) ? "DDR" : "SRAM", + (is_expn_tbl) ? "EXP " : "BASE", + record_index, + rule_hdl, + prep_nat_rule_4print(rule_ptr, buf, sizeof(buf))); + + fflush(stdout); + + *((bool*) arb_data_ptr) = false; + +bail: + return 0; +} + +static int print_meta_data( + ipa_table* table_ptr, + uint32_t rule_hdl, + void* record_ptr, + uint16_t record_index, + void* meta_record_ptr, + uint16_t meta_record_index, + void* arb_data_ptr ) +{ + struct ipa_nat_indx_tbl_rule* index_entry = + (struct ipa_nat_indx_tbl_rule *) record_ptr; + + struct ipa_nat_indx_tbl_meta_info* mi_ptr = + (struct ipa_nat_indx_tbl_meta_info*) meta_record_ptr; + + enum ipa3_nat_mem_in nmi; + uint8_t is_expn_tbl; + uint16_t rule_index; + + BREAK_RULE_HDL(table_ptr, rule_hdl, nmi, is_expn_tbl, rule_index); + + if ( mi_ptr ) + { + printf(" %s %s Entry_Index=0x%04X Table_Entry=0x%04X -> " + "Prev_Index=0x%04X Next_Index=0x%04X\n", + (table_ptr->nmi == IPA_NAT_MEM_IN_DDR) ? "DDR" : "SRAM", + (is_expn_tbl) ? "EXP " : "BASE", + record_index, + index_entry->tbl_entry, + mi_ptr->prev_index, + index_entry->next_index); + } + else + { + printf(" %s %s Entry_Index=0x%04X Table_Entry=0x%04X -> " + "Prev_Index=0xXXXX Next_Index=0x%04X\n", + (table_ptr->nmi == IPA_NAT_MEM_IN_DDR) ? "DDR" : "SRAM", + (is_expn_tbl) ? "EXP " : "BASE", + record_index, + index_entry->tbl_entry, + index_entry->next_index); + } + + fflush(stdout); + + *((bool*) arb_data_ptr) = false; + + return 0; +} + +void ipa_nat_dump_ipv4_table( + uint32_t tbl_hdl ) +{ + bool empty; + + if (pthread_mutex_lock(&nat_mutex)) { + IPAERR("unable to lock the nat mutex\n"); + return; + } + + printf("\nIPv4 active rules:\n"); + + empty = true; + + ipa_nati_walk_ipv4_tbl(tbl_hdl, USE_NAT_TABLE, print_nat_rule, &empty); + + if ( empty ) + { + printf(" Empty\n"); + } + + printf("\nExpansion Index Table Meta Data:\n"); + + empty = true; + + ipa_nati_walk_ipv4_tbl(tbl_hdl, USE_INDEX_TABLE, print_meta_data, &empty); + + if ( empty ) + { + printf(" Empty\n"); + } + + printf("\n"); + + if (pthread_mutex_unlock(&nat_mutex)) { + IPAERR("unable to unlock the nat mutex\n"); + } +} + +int ipa_NATI_clear_ipv4_tbl( + uint32_t tbl_hdl ) +{ + enum ipa3_nat_mem_in nmi; + struct ipa_nat_cache* nat_cache_ptr; + struct ipa_nat_ip4_table_cache* nat_table; + int ret = 0; + + IPADBG("In\n"); + + BREAK_TBL_HDL(tbl_hdl, nmi, tbl_hdl); + + if ( ! IPA_VALID_NAT_MEM_IN(nmi) ) { + IPAERR("Bad cache type argument passed\n"); + ret = -EINVAL; + goto bail; + } + + IPADBG("nmi(%s)\n", ipa3_nat_mem_in_as_str(nmi)); + + nat_cache_ptr = &ipv4_nat_cache[nmi]; + + if (pthread_mutex_lock(&nat_mutex)) { + IPAERR("unable to lock the nat mutex\n"); + ret = -EINVAL; + goto bail; + } + + if ( ! nat_cache_ptr->table_cnt ) { + IPAERR("No initialized table in NAT cache\n"); + ret = -EINVAL; + goto unlock; + } + + nat_table = &nat_cache_ptr->ip4_tbl[tbl_hdl - 1]; + + ipa_table_reset(&nat_table->table); + nat_table->table.cur_tbl_cnt = + nat_table->table.cur_expn_tbl_cnt = 0; + + ipa_table_reset(&nat_table->index_table); + nat_table->index_table.cur_tbl_cnt = + nat_table->index_table.cur_expn_tbl_cnt = 0; + +unlock: + if (pthread_mutex_unlock(&nat_mutex)) { + IPAERR("unable to unlock the nat mutex\n"); + ret = (ret) ? ret : -EPERM; + } + +bail: + IPADBG("Out\n"); + + return ret; +} + +int ipa_nati_copy_ipv4_tbl( + uint32_t src_tbl_hdl, + uint32_t dst_tbl_hdl, + ipa_table_walk_cb copy_cb ) +{ + int ret = 0; + + IPADBG("In\n"); + + if ( ! copy_cb ) + { + IPAERR("copy_cb is null\n"); + ret = -EINVAL; + goto bail; + } + + if (pthread_mutex_lock(&nat_mutex)) + { + IPAERR("unable to lock the nat mutex\n"); + ret = -EINVAL; + goto bail; + } + + /* + * Clear the destination table... + */ + ret = ipa_NATI_clear_ipv4_tbl(dst_tbl_hdl); + + if ( ret == 0 ) + { + /* + * Now walk the source table and pass the valid records to the + * user's copy callback... + */ + ret = ipa_NATI_walk_ipv4_tbl( + src_tbl_hdl, USE_NAT_TABLE, copy_cb, dst_tbl_hdl); + + if ( ret != 0 ) + { + IPAERR("ipa_table_walk returned non-zero (%d)\n", ret); + goto unlock; + } + } + +unlock: + if (pthread_mutex_unlock(&nat_mutex)) + { + IPAERR("unable to unlock the nat mutex\n"); + ret = (ret) ? ret : -EPERM; + } + +bail: + IPADBG("Out\n"); + + return ret; +} + +int ipa_NATI_walk_ipv4_tbl( + uint32_t tbl_hdl, + WhichTbl2Use which, + ipa_table_walk_cb walk_cb, + void* arb_data_ptr ) +{ + enum ipa3_nat_mem_in nmi; + uint32_t broken_tbl_hdl; + struct ipa_nat_cache* nat_cache_ptr; + struct ipa_nat_ip4_table_cache* nat_table; + ipa_table* ipa_tbl_ptr; + + int ret = 0; + + IPADBG("In\n"); + + if ( ! VALID_TBL_HDL(tbl_hdl) || + ! VALID_WHICHTBL2USE(which) || + ! walk_cb ) + { + IPAERR("Bad arg: tbl_hdl(0x%08X) and/or WhichTbl2Use(%u) and/or walk_cb(%p)\n", + tbl_hdl, which, walk_cb); + ret = -EINVAL; + goto bail; + } + + if ( pthread_mutex_lock(&nat_mutex) ) + { + IPAERR("unable to lock the nat mutex\n"); + ret = -EINVAL; + goto bail; + } + + /* + * Now walk the table and pass the valid records to the user's + * walk callback... + */ + BREAK_TBL_HDL(tbl_hdl, nmi, broken_tbl_hdl); + + if ( ! IPA_VALID_NAT_MEM_IN(nmi) ) + { + IPAERR("Bad cache type argument passed\n"); + ret = -EINVAL; + goto unlock; + } + + nat_cache_ptr = &ipv4_nat_cache[nmi]; + + if ( ! nat_cache_ptr->table_cnt ) + { + IPAERR("No initialized table in NAT cache\n"); + ret = -EINVAL; + goto unlock; + } + + nat_table = &nat_cache_ptr->ip4_tbl[broken_tbl_hdl - 1]; + + ipa_tbl_ptr = + (which == USE_NAT_TABLE) ? + &nat_table->table : + &nat_table->index_table; + + ret = ipa_table_walk(ipa_tbl_ptr, 0, WHEN_SLOT_FILLED, walk_cb, arb_data_ptr); + + if ( ret != 0 ) + { + IPAERR("ipa_table_walk returned non-zero (%d)\n", ret); + goto unlock; + } + +unlock: + if ( pthread_mutex_unlock(&nat_mutex) ) + { + IPAERR("unable to unlock the nat mutex\n"); + ret = (ret) ? ret : -EPERM; + } + +bail: + IPADBG("Out\n"); + + return ret; +} + +typedef struct +{ + WhichTbl2Use which; + uint32_t tot_for_avg; + ipa_nati_tbl_stats* stats_ptr; +} chain_stat_help; + +static int gen_chain_stats( + ipa_table* table_ptr, + uint32_t rule_hdl, + void* record_ptr, + uint16_t record_index, + void* meta_record_ptr, + uint16_t meta_record_index, + void* arb_data_ptr ) +{ + chain_stat_help* csh_ptr = (chain_stat_help*) arb_data_ptr; + + enum ipa3_nat_mem_in nmi; + uint8_t is_expn_tbl; + uint16_t rule_index; + + uint32_t chain_len = 0; + + BREAK_RULE_HDL(table_ptr, rule_hdl, nmi, is_expn_tbl, rule_index); + + if ( is_expn_tbl ) + { + return 1; + } + + if ( csh_ptr->which == USE_NAT_TABLE ) + { + struct ipa_nat_rule* list_elem_ptr = + (struct ipa_nat_rule*) record_ptr; + + if ( list_elem_ptr->next_index ) + { + chain_len = 1; + + while ( list_elem_ptr->next_index ) + { + chain_len++; + + list_elem_ptr = GOTO_REC(table_ptr, list_elem_ptr->next_index); + } + } + } + else + { + struct ipa_nat_indx_tbl_rule* list_elem_ptr = + (struct ipa_nat_indx_tbl_rule*) record_ptr; + + if ( list_elem_ptr->next_index ) + { + chain_len = 1; + + while ( list_elem_ptr->next_index ) + { + chain_len++; + + list_elem_ptr = GOTO_REC(table_ptr, list_elem_ptr->next_index); + } + } + } + + if ( chain_len ) + { + csh_ptr->stats_ptr->tot_chains += 1; + + csh_ptr->tot_for_avg += chain_len; + + if ( csh_ptr->stats_ptr->min_chain_len == 0 ) + { + csh_ptr->stats_ptr->min_chain_len = chain_len; + } + else + { + csh_ptr->stats_ptr->min_chain_len = + min(csh_ptr->stats_ptr->min_chain_len, chain_len); + } + + csh_ptr->stats_ptr->max_chain_len = + max(csh_ptr->stats_ptr->max_chain_len, chain_len); + } + + return 0; +} + +int ipa_NATI_ipv4_tbl_stats( + uint32_t tbl_hdl, + ipa_nati_tbl_stats* nat_stats_ptr, + ipa_nati_tbl_stats* idx_stats_ptr ) +{ + enum ipa3_nat_mem_in nmi; + uint32_t broken_tbl_hdl; + struct ipa_nat_cache* nat_cache_ptr; + struct ipa_nat_ip4_table_cache* nat_table; + ipa_table* ipa_tbl_ptr; + + chain_stat_help csh; + + int ret = 0; + + IPADBG("In\n"); + + if ( ! VALID_TBL_HDL(tbl_hdl) || + ! nat_stats_ptr || + ! idx_stats_ptr ) + { + IPAERR("Bad arg: " + "tbl_hdl(0x%08X) and/or " + "nat_stats_ptr(%p) and/or " + "idx_stats_ptr(%p)\n", + tbl_hdl, + nat_stats_ptr, + idx_stats_ptr ); + ret = -EINVAL; + goto bail; + } + + if ( pthread_mutex_lock(&nat_mutex) ) + { + IPAERR("unable to lock the nat mutex\n"); + ret = -EINVAL; + goto bail; + } + + memset(nat_stats_ptr, 0, sizeof(ipa_nati_tbl_stats)); + memset(idx_stats_ptr, 0, sizeof(ipa_nati_tbl_stats)); + + BREAK_TBL_HDL(tbl_hdl, nmi, broken_tbl_hdl); + + if ( ! IPA_VALID_NAT_MEM_IN(nmi) ) + { + IPAERR("Bad cache type argument passed\n"); + ret = -EINVAL; + goto unlock; + } + + nat_cache_ptr = &ipv4_nat_cache[nmi]; + + if ( ! nat_cache_ptr->table_cnt ) + { + IPAERR("No initialized table in NAT cache\n"); + ret = -EINVAL; + goto unlock; + } + + nat_table = &nat_cache_ptr->ip4_tbl[broken_tbl_hdl - 1]; + + /* + * Gather NAT table stats... + */ + ipa_tbl_ptr = &nat_table->table; + + nat_stats_ptr->nmi = nmi; + + nat_stats_ptr->tot_base_ents = ipa_tbl_ptr->table_entries; + nat_stats_ptr->tot_expn_ents = ipa_tbl_ptr->expn_table_entries; + nat_stats_ptr->tot_ents = + nat_stats_ptr->tot_base_ents + nat_stats_ptr->tot_expn_ents; + + nat_stats_ptr->tot_base_ents_filled = ipa_tbl_ptr->cur_tbl_cnt; + nat_stats_ptr->tot_expn_ents_filled = ipa_tbl_ptr->cur_expn_tbl_cnt; + + memset(&csh, 0, sizeof(chain_stat_help)); + + csh.which = USE_NAT_TABLE; + csh.stats_ptr = nat_stats_ptr; + + ret = ipa_table_walk( + ipa_tbl_ptr, 0, WHEN_SLOT_FILLED, gen_chain_stats, &csh); + + if ( ret < 0 ) + { + IPAERR("Error gathering chain stats\n"); + ret = -EINVAL; + goto unlock; + } + + if ( csh.tot_for_avg && nat_stats_ptr->tot_chains ) + { + nat_stats_ptr->avg_chain_len = + (float) csh.tot_for_avg / (float) nat_stats_ptr->tot_chains; + } + + /* + * Now lets gather index table stats... + */ + ipa_tbl_ptr = &nat_table->index_table; + + idx_stats_ptr->nmi = nmi; + + idx_stats_ptr->tot_base_ents = ipa_tbl_ptr->table_entries; + idx_stats_ptr->tot_expn_ents = ipa_tbl_ptr->expn_table_entries; + idx_stats_ptr->tot_ents = + idx_stats_ptr->tot_base_ents + idx_stats_ptr->tot_expn_ents; + + idx_stats_ptr->tot_base_ents_filled = ipa_tbl_ptr->cur_tbl_cnt; + idx_stats_ptr->tot_expn_ents_filled = ipa_tbl_ptr->cur_expn_tbl_cnt; + + memset(&csh, 0, sizeof(chain_stat_help)); + + csh.which = USE_INDEX_TABLE; + csh.stats_ptr = idx_stats_ptr; + + ret = ipa_table_walk( + ipa_tbl_ptr, 0, WHEN_SLOT_FILLED, gen_chain_stats, &csh); + + if ( ret < 0 ) + { + IPAERR("Error gathering chain stats\n"); + ret = -EINVAL; + goto unlock; + } + + if ( csh.tot_for_avg && idx_stats_ptr->tot_chains ) + { + idx_stats_ptr->avg_chain_len = + (float) csh.tot_for_avg / (float) idx_stats_ptr->tot_chains; + } + + ret = 0; + +unlock: + if ( pthread_mutex_unlock(&nat_mutex) ) + { + IPAERR("unable to unlock the nat mutex\n"); + ret = (ret) ? ret : -EPERM; + } + +bail: + IPADBG("Out\n"); + + return ret; +} + +int ipa_nati_vote_clock( + enum ipa_app_clock_vote_type vote_type ) +{ + struct ipa_nat_cache* nat_cache_ptr = + &ipv4_nat_cache[IPA_NAT_MEM_IN_SRAM]; + + int ret = 0; + + IPADBG("In\n"); + + if ( ! nat_cache_ptr->ipa_desc ) { + nat_cache_ptr->ipa_desc = ipa_descriptor_open(); + if ( nat_cache_ptr->ipa_desc == NULL ) { + IPAERR("failed to open IPA driver file descriptor\n"); + ret = -EIO; + goto bail; + } + } + + ret = ioctl(nat_cache_ptr->ipa_desc->fd, + IPA_IOC_APP_CLOCK_VOTE, + vote_type); + + if (ret) { + IPAERR("APP_CLOCK_VOTE ioctl failure %d on IPA fd %d\n", + ret, nat_cache_ptr->ipa_desc->fd); + goto bail; + } + +bail: + IPADBG("Out\n"); + + return ret; +} diff --git a/qcom/opensource/dataipa/ipanat/src/ipa_nat_map.cpp b/qcom/opensource/dataipa/ipanat/src/ipa_nat_map.cpp new file mode 100644 index 0000000000..46778b24b5 --- /dev/null +++ b/qcom/opensource/dataipa/ipanat/src/ipa_nat_map.cpp @@ -0,0 +1,231 @@ +/* + * Copyright (c) 2019 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include + +#include "ipa_nat_utils.h" + +#include "ipa_nat_map.h" + +static std::map map_array[MAP_NUM_MAX]; + +/******************************************************************************/ + +int ipa_nat_map_add( + ipa_which_map which, + uint32_t key, + uint32_t val ) +{ + int ret_val = 0; + + std::pair::iterator, bool> ret; + + IPADBG("In\n"); + + if ( ! VALID_IPA_USE_MAP(which) ) + { + IPAERR("Bad arg which(%u)\n", which); + ret_val = -1; + goto bail; + } + + IPADBG("[%s] key(%u) -> val(%u)\n", + ipa_which_map_as_str(which), key, val); + + ret = map_array[which].insert(std::pair(key, val)); + + if ( ret.second == false ) + { + IPAERR("[%s] key(%u) already exists in map\n", + ipa_which_map_as_str(which), + key); + ret_val = -1; + } + +bail: + IPADBG("Out\n"); + + return ret_val; +} + +/******************************************************************************/ + +int ipa_nat_map_find( + ipa_which_map which, + uint32_t key, + uint32_t* val_ptr ) +{ + int ret_val = 0; + + std::map::iterator it; + + IPADBG("In\n"); + + if ( ! VALID_IPA_USE_MAP(which) ) + { + IPAERR("Bad arg which(%u)\n", which); + ret_val = -1; + goto bail; + } + + IPADBG("[%s] key(%u)\n", + ipa_which_map_as_str(which), key); + + it = map_array[which].find(key); + + if ( it == map_array[which].end() ) + { + IPAERR("[%s] key(%u) not found in map\n", + ipa_which_map_as_str(which), + key); + ret_val = -1; + } + else + { + if ( val_ptr ) + { + *val_ptr = it->second; + IPADBG("[%s] key(%u) -> val(%u)\n", + ipa_which_map_as_str(which), + key, *val_ptr); + } + } + +bail: + IPADBG("Out\n"); + + return ret_val; +} + +/******************************************************************************/ + +int ipa_nat_map_del( + ipa_which_map which, + uint32_t key, + uint32_t* val_ptr ) +{ + int ret_val = 0; + + std::map::iterator it; + + IPADBG("In\n"); + + if ( ! VALID_IPA_USE_MAP(which) ) + { + IPAERR("Bad arg which(%u)\n", which); + ret_val = -1; + goto bail; + } + + IPADBG("[%s] key(%u)\n", + ipa_which_map_as_str(which), key); + + it = map_array[which].find(key); + + if ( it == map_array[which].end() ) + { + IPAERR("[%s] key(%u) not found in map\n", + ipa_which_map_as_str(which), + key); + ret_val = -1; + } + else + { + if ( val_ptr ) + { + *val_ptr = it->second; + IPADBG("[%s] key(%u) -> val(%u)\n", + ipa_which_map_as_str(which), + key, *val_ptr); + } + map_array[which].erase(it); + } + +bail: + IPADBG("Out\n"); + + return ret_val; +} + +int ipa_nat_map_clear( + ipa_which_map which ) +{ + int ret_val = 0; + + IPADBG("In\n"); + + if ( ! VALID_IPA_USE_MAP(which) ) + { + IPAERR("Bad arg which(%u)\n", which); + ret_val = -1; + goto bail; + } + + map_array[which].clear(); + +bail: + IPADBG("Out\n"); + + return ret_val; +} + +int ipa_nat_map_dump( + ipa_which_map which ) +{ + std::map::iterator it; + + int ret_val = 0; + + IPADBG("In\n"); + + if ( ! VALID_IPA_USE_MAP(which) ) + { + IPAERR("Bad arg which(%u)\n", which); + ret_val = -1; + goto bail; + } + + printf("Dumping: %s\n", ipa_which_map_as_str(which)); + + for ( it = map_array[which].begin(); + it != map_array[which].end(); + it++ ) + { + printf(" Key[%u|0x%08X] -> Value[%u|0x%08X]\n", + it->first, + it->first, + it->second, + it->second); + } + +bail: + IPADBG("Out\n"); + + return ret_val; +} diff --git a/qcom/opensource/dataipa/ipanat/src/ipa_nat_statemach.c b/qcom/opensource/dataipa/ipanat/src/ipa_nat_statemach.c new file mode 100644 index 0000000000..2e77082536 --- /dev/null +++ b/qcom/opensource/dataipa/ipanat/src/ipa_nat_statemach.c @@ -0,0 +1,2671 @@ +/* + * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Changes from Qualcomm Innovation Center are provided under the following license: + * + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * * Neither the name of Qualcomm Innovation Center, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + */ +#include +#include + +#include "ipa_nat_drv.h" +#include "ipa_nat_drvi.h" + +#include "ipa_nat_map.h" + +#include "ipa_nat_statemach.h" + +#undef PRCNT_OF +#define PRCNT_OF(v) \ + ((.25) * (v)) + +#undef CHOOSE_MEM_SUB +#define CHOOSE_MEM_SUB() \ + (nati_obj.curr_state == NATI_STATE_HYBRID) ? \ + SRAM_SUB : \ + DDR_SUB + +#undef CHOOSE_MAPS +#define CHOOSE_MAPS(o2n, n2o) \ + do { \ + uint32_t sub = CHOOSE_MEM_SUB(); \ + o2n = nati_obj.map_pairs[sub].orig2new_map; \ + n2o = nati_obj.map_pairs[sub].new2orig_map; \ + } while (0) + +#undef CHOOSE_CNTR +#define CHOOSE_CNTR() \ + &(nati_obj.tot_rules_in_table[CHOOSE_MEM_SUB()]) + +#undef CHOOSE_SW_STATS +#define CHOOSE_SW_STATS() \ + &(nati_obj.sw_stats[CHOOSE_MEM_SUB()]) + +/* + * BACKROUND INFORMATION + * + * As it relates to why this file exists... + * + * In the past, a NAT table API was presented to upper layer + * applications. Said API mananged low level details of NAT table + * creation, manipulation, and destruction. The API + * managed/manipulated NAT tables that lived exclusively in DDR. DDR + * based tables are fine, but lead to uneeded bus accesses to/from DDR + * by the IPA while doing its NAT duties. These accesses cause NAT to + * take longer than necessary. + * + * If the DDR bus accesses could be eliminated by storing the table in + * the IPA's internal memory (ie. SRAM), the IPA's IP V4 NAT could be + * sped up. This leads us to the following description of this file's + * intent. + * + * The purpose and intent of this file is to hijack the API described + * above, but in a way that allows the tables to live in both SRAM and + * DDR. The details of whether SRAM or DDR is being used is hidden + * from the application. More specifically, the API will allow the + * following to occur completely tranparent to the application using + * the API. + * + * (1) NAT tables can live exclusively in DDR (traditional and + * historically like before) + * + * (2) NAT tables can live simultaneously in SRAM and DDR. SRAM + * initially being used by the IPA, but both being kept in sync. + * When SRAM becomes too full, a switch to DDR will occur. + * + * (3) The same as (2) above, but after the switch to DDR occurs, + * we'll have the ability to switch back to SRAM if/when DDR + * table entry deletions take us to a small enough entry + * count. An entry count that when met, allows us to switch back + * using SRAM again. + * + * As above, all of these details will just magically happen unknown + * to the application using the API. The implementation is done via a + * state machine. + */ + +/* + * The following will be used to keep state machine state for and + * between API calls... + */ +static ipa_nati_obj nati_obj = { + .prev_state = NATI_STATE_NULL, + .curr_state = NATI_STATE_NULL, + .hold_state = false, + .state_to_hold = NATI_STATE_NULL, + .ddr_tbl_hdl = 0, + .sram_tbl_hdl = 0, + .tot_slots_in_sram = 0, + .back_to_sram_thresh = 0, + /* + * Remember: + * tot_rules_in_table[0] for ddr, and + * tot_rules_in_table[1] for sram + */ + .tot_rules_in_table = { 0, 0 }, + /* + * Remember: + * map_pairs[0] for ddr, and + * map_pairs[1] for sram + */ + .map_pairs = { {MAP_NUM_00, MAP_NUM_01}, {MAP_NUM_02, MAP_NUM_03} }, + /* + * Remember: + * sw_stats[0] for ddr, and + * sw_stats[1] for sram + */ + .sw_stats = { {0, 0}, {0, 0} }, +}; + +/* + * The following needed to protect nati_obj above, as well as a number + * of data stuctures within the file ipa_nat_drvi.c + */ +pthread_mutex_t nat_mutex; +static bool nat_mutex_init = false; + +static inline int mutex_init(void) +{ + static pthread_mutexattr_t nat_mutex_attr; + + int ret = 0; + + IPADBG("In\n"); + + ret = pthread_mutexattr_init(&nat_mutex_attr); + + if ( ret != 0 ) + { + IPAERR("pthread_mutexattr_init() failed: ret(%d)\n", ret ); + goto bail; + } + + ret = pthread_mutexattr_settype( + &nat_mutex_attr, PTHREAD_MUTEX_RECURSIVE); + + if ( ret != 0 ) + { + IPAERR("pthread_mutexattr_settype() failed: ret(%d)\n", + ret ); + goto bail; + } + + ret = pthread_mutex_init(&nat_mutex, &nat_mutex_attr); + + if ( ret != 0 ) + { + IPAERR("pthread_mutex_init() failed: ret(%d)\n", + ret ); + goto bail; + } + + nat_mutex_init = true; + +bail: + IPADBG("Out\n"); + + return ret; +} + +/* + * Function for taking/locking the mutex... + */ +static int take_mutex() +{ + int ret; + + if ( nat_mutex_init ) + { +again: + ret = pthread_mutex_lock(&nat_mutex); + } + else + { + ret = mutex_init(); + + if ( ret == 0 ) + { + goto again; + } + } + + if ( ret != 0 ) + { + IPAERR("Unable to lock the %s nat mutex\n", + (nat_mutex_init) ? "initialized" : "uninitialized"); + } + + return ret; +} + +/* + * Function for giving/unlocking the mutex... + */ +static int give_mutex() +{ + int ret = (nat_mutex_init) ? pthread_mutex_unlock(&nat_mutex) : -1; + + if ( ret != 0 ) + { + IPAERR("Unable to unlock the %s nat mutex\n", + (nat_mutex_init) ? "initialized" : "uninitialized"); + } + + return ret; +} + +/* + * **************************************************************************** + * + * HIJACKED API FUNCTIONS START HERE + * + * **************************************************************************** + */ +int ipa_nati_add_ipv4_tbl( + uint32_t public_ip_addr, + const char* mem_type_ptr, + uint16_t number_of_entries, + uint32_t* tbl_hdl) +{ + arb_t* args[] = { + (arb_t*)(arb_t)public_ip_addr, + (arb_t*)(arb_t)number_of_entries, + (arb_t*) tbl_hdl, + (arb_t*) mem_type_ptr, + }; + + int ret; + + IPADBG("In\n"); + + ret = ipa_nati_statemach(&nati_obj, NATI_TRIG_ADD_TABLE, args); + + if ( ret == 0 ) + { + IPADBG("tbl_hdl val(0x%08X)\n", *tbl_hdl); + } + + IPADBG("Out\n"); + + return ret; +} + +int ipa_nati_del_ipv4_table( + uint32_t tbl_hdl) +{ + arb_t* args[] = { + (arb_t*)(arb_t)tbl_hdl, + }; + + int ret; + + IPADBG("In\n"); + + ret = ipa_nati_statemach(&nati_obj, NATI_TRIG_DEL_TABLE, args); + + IPADBG("Out\n"); + + return ret; +} + +int ipa_nati_clear_ipv4_tbl( + uint32_t tbl_hdl ) +{ + arb_t* args[] = { + (arb_t*)(arb_t)tbl_hdl, + }; + + int ret; + + IPADBG("In\n"); + + ret = ipa_nati_statemach(&nati_obj, NATI_TRIG_CLR_TABLE, args); + + IPADBG("Out\n"); + + return ret; +} + +int ipa_nati_walk_ipv4_tbl( + uint32_t tbl_hdl, + WhichTbl2Use which, + ipa_table_walk_cb walk_cb, + void* arb_data_ptr ) +{ + arb_t* args[] = { + (arb_t*)(arb_t)tbl_hdl, + (arb_t*)(arb_t)which, + (arb_t*) walk_cb, + (arb_t*) arb_data_ptr, + }; + + int ret; + + IPADBG("In\n"); + + ret = ipa_nati_statemach(&nati_obj, NATI_TRIG_WLK_TABLE, args); + + IPADBG("Out\n"); + + return ret; +} + +int ipa_nati_ipv4_tbl_stats( + uint32_t tbl_hdl, + ipa_nati_tbl_stats* nat_stats_ptr, + ipa_nati_tbl_stats* idx_stats_ptr ) +{ + arb_t* args[] = { + (arb_t*)(arb_t)tbl_hdl, + (arb_t*) nat_stats_ptr, + (arb_t*) idx_stats_ptr, + }; + + int ret; + + IPADBG("In\n"); + + ret = ipa_nati_statemach(&nati_obj, NATI_TRIG_TBL_STATS, args); + + IPADBG("Out\n"); + + return ret; +} + +int ipa_nati_add_ipv4_rule( + uint32_t tbl_hdl, + const ipa_nat_ipv4_rule* clnt_rule, + uint32_t* rule_hdl ) +{ + arb_t* args[] = { + (arb_t*)(arb_t)tbl_hdl, + (arb_t*) clnt_rule, + (arb_t*) rule_hdl, + }; + + int ret; + + IPADBG("In\n"); + + ret = ipa_nati_statemach(&nati_obj, NATI_TRIG_ADD_RULE, args); + + if ( ret == 0 ) + { + IPADBG("rule_hdl val(%u)\n", *rule_hdl); + } + + IPADBG("Out\n"); + + return ret; +} + +int ipa_nati_del_ipv4_rule( + uint32_t tbl_hdl, + uint32_t rule_hdl ) +{ + arb_t* args[] = { + (arb_t*)(arb_t)tbl_hdl, + (arb_t*)(arb_t)rule_hdl, + }; + + int ret; + + IPADBG("In\n"); + + ret = ipa_nati_statemach(&nati_obj, NATI_TRIG_DEL_RULE, args); + + IPADBG("Out\n"); + + return ret; +} + +int ipa_nati_query_timestamp( + uint32_t tbl_hdl, + uint32_t rule_hdl, + uint32_t* time_stamp) +{ + arb_t* args[] = { + (arb_t*)(arb_t)tbl_hdl, + (arb_t*)(arb_t)rule_hdl, + (arb_t*) time_stamp, + }; + + int ret; + + IPADBG("In\n"); + + ret = ipa_nati_statemach(&nati_obj, NATI_TRIG_GET_TSTAMP, args); + + if ( ret == 0 ) + { + IPADBG("time_stamp val(0x%08X)\n", *time_stamp); + } + + IPADBG("Out\n"); + + return ret; +} + +int ipa_nat_switch_to( + enum ipa3_nat_mem_in nmi, + bool hold_state ) +{ + int ret = -1; + + IPADBG("In - current state %s\n", + ipa_nati_state_as_str(nati_obj.curr_state)); + + if ( ! IPA_VALID_NAT_MEM_IN(nmi) ) + { + IPAERR("Bad nmi(%s)\n", ipa3_nat_mem_in_as_str(nmi)); + + ret = -1; + + goto bail; + } + + ret = take_mutex(); + + if ( ret != 0 ) + { + goto bail; + } + + /* + * Are we here before the state machine has been started? + */ + if ( IN_UNSTARTED_STATE() ) + { + nati_obj.hold_state = hold_state; + + nati_obj.state_to_hold = + (nmi == IPA_NAT_MEM_IN_DDR) ? + NATI_STATE_DDR_ONLY : + NATI_STATE_SRAM_ONLY; + + IPADBG( + "Initial state will be %s before table init and it %s be held\n", + ipa_nati_state_as_str(nati_obj.state_to_hold), + (hold_state) ? "will" : "will not"); + + ret = 0; + + goto unlock; + } + + /* + * Are we here after we've already started in hybrid state? + */ + if ( IN_HYBRID_STATE() ) + { + ret = 0; + + if ( COMPATIBLE_NMI_4SWITCH(nmi) ) + { + ret = ipa_nati_statemach(&nati_obj, NATI_TRIG_TBL_SWITCH, 0); + } + + if ( ret == 0 ) + { + nati_obj.hold_state = hold_state; + + if ( hold_state ) + { + nati_obj.state_to_hold = GEN_HOLD_STATE(); + } + + IPADBG( + "Current state is %s and it %s be held\n", + ipa_nati_state_as_str(nati_obj.curr_state), + (hold_state) ? "will" : "will not"); + } + + goto unlock; + } + + /* + * We've gotten here because we're not in an unstarted state, nor + * are we in hybrid state. This means we're either in + * NATI_STATE_DDR_ONLY or NATI_STATE_SRAM_ONLY + * + * Let's see what's being attempted and if it's OK... + */ + if ( hold_state ) + { + if ( COMPATIBLE_NMI_4SWITCH(nmi) ) + { + /* + * If we've gotten here, it means that the requested nmi, + * the current state, and the hold are compatible... + */ + nati_obj.state_to_hold = GEN_HOLD_STATE(); + nati_obj.hold_state = hold_state; + + IPADBG( + "Requesting to hold memory type %s at " + "current state %s will be done\n", + ipa3_nat_mem_in_as_str(nmi), + ipa_nati_state_as_str(nati_obj.curr_state)); + + ret = 0; + + goto unlock; + } + else + { + /* + * The requested nmi, the current state, and the hold are + * not compatible... + */ + IPAERR( + "Requesting to hold memory type %s and " + "current state %s are incompatible\n", + ipa3_nat_mem_in_as_str(nmi), + ipa_nati_state_as_str(nati_obj.curr_state)); + + ret = -1; + + goto unlock; + } + } + + /* + * If we've gotten here, it's because the holding of state is no + * longer desired... + */ + nati_obj.state_to_hold = NATI_STATE_NULL; + nati_obj.hold_state = hold_state; + + IPADBG("Holding of state is no longer desired\n"); + + ret = 0; + +unlock: + ret = give_mutex(); + +bail: + IPADBG("Out\n"); + + return ret; +} + +bool ipa_nat_is_sram_supported(void) +{ + return VALID_TBL_HDL(nati_obj.sram_tbl_hdl); +} + +/******************************************************************************/ +/* + * FUNCTION: migrate_rule + * + * PARAMS: + * + * table_ptr (IN) The table being walked + * + * tbl_rule_hdl (IN) The nat rule's handle from the source table + * + * record_ptr (IN) The nat rule record from the source table + * + * record_index (IN) The record above's index in the table being walked + * + * meta_record_ptr (IN) If meta data in table, this will be it + * + * meta_record_index (IN) The record above's index in the table being walked + * + * arb_data_ptr (IN) The destination table handle + * + * DESCRIPTION: + * + * This routine is intended to copy records from a source table to a + * destination table. + + * It is used in union with the ipa_nati_copy_ipv4_tbl() API call + * below. + * + * It is compatible with the ipa_table_walk() API. + * + * In the context of the ipa_nati_copy_ipv4_tbl(), the arguments + * passed in are as enumerated above. + * + * AN IMPORTANT NOTE ON RULE HANDLES WHEN IN MYBRID MODE + * + * The rule_hdl is used to find a rule in the nat table. It is, in + * effect, an index into the table. The applcation above us retains + * it for future manipulation of the rule in the table. + * + * In hybrid mode, a rule can and will move between SRAM and DDR. + * Because of this, its handle will change. The application has + * only the original handle and doesn't know of the new handle. A + * mapping, used in hybrid mode, will maintain a relationship + * between the original handle and the rule's current real handle... + * + * To help you get a mindset of how this is done: + * + * The original handle will map (point) to the new and new handle + * will map (point) back to original. + * + * NOTE WELL: There are two sets of maps. One for each memory type... + * + * RETURNS: + * + * Returns 0 on success, non-zero on failure + */ +static int migrate_rule( + ipa_table* table_ptr, + uint32_t tbl_rule_hdl, + void* record_ptr, + uint16_t record_index, + void* meta_record_ptr, + uint16_t meta_record_index, + void* arb_data_ptr ) +{ + struct ipa_nat_rule* nat_rule_ptr = (struct ipa_nat_rule*) record_ptr; + uint32_t dst_tbl_hdl = (uint32_t) arb_data_ptr; + + ipa_nat_ipv4_rule v4_rule; + + uint32_t orig_rule_hdl; + uint32_t new_rule_hdl; + + uint32_t src_orig2new_map, src_new2orig_map; + uint32_t dst_orig2new_map, dst_new2orig_map; + uint32_t* cnt_ptr; + + const char* mig_dir_ptr; + + char buf[1024]; + int ret; + + IPADBG("In\n"); + + IPADBG("tbl_mem_type(%s) tbl_rule_hdl(%u) -> %s\n", + ipa3_nat_mem_in_as_str(table_ptr->nmi), + tbl_rule_hdl, + prep_nat_rule_4print(nat_rule_ptr, buf, sizeof(buf))); + + IPADBG("dst_tbl_hdl(0x%08X)\n", dst_tbl_hdl); + + /* + * What is the type of the source table? + */ + if ( table_ptr->nmi == IPA_NAT_MEM_IN_SRAM ) + { + mig_dir_ptr = "SRAM -> DDR"; + + src_orig2new_map = nati_obj.map_pairs[SRAM_SUB].orig2new_map; + src_new2orig_map = nati_obj.map_pairs[SRAM_SUB].new2orig_map; + + dst_orig2new_map = nati_obj.map_pairs[DDR_SUB].orig2new_map; + dst_new2orig_map = nati_obj.map_pairs[DDR_SUB].new2orig_map; + + cnt_ptr = &(nati_obj.tot_rules_in_table[DDR_SUB]); + } + else + { + mig_dir_ptr = "DDR -> SRAM"; + + src_orig2new_map = nati_obj.map_pairs[DDR_SUB].orig2new_map; + src_new2orig_map = nati_obj.map_pairs[DDR_SUB].new2orig_map; + + dst_orig2new_map = nati_obj.map_pairs[SRAM_SUB].orig2new_map; + dst_new2orig_map = nati_obj.map_pairs[SRAM_SUB].new2orig_map; + + cnt_ptr = &(nati_obj.tot_rules_in_table[SRAM_SUB]); + } + + if ( nat_rule_ptr->protocol == IPA_NAT_INVALID_PROTO_FIELD_VALUE_IN_RULE ) + { + IPADBG("%s: Special \"first rule in list\" case. " + "Rule's enabled bit on, but protocol implies deleted\n", + mig_dir_ptr); + ret = 0; + goto bail; + } + + ret = ipa_nat_map_find(src_new2orig_map, tbl_rule_hdl, &orig_rule_hdl); + + if ( ret != 0 ) + { + IPAERR("%s: ipa_nat_map_find(src_new2orig_map) fail\n", mig_dir_ptr); + goto bail; + } + + memset(&v4_rule, 0, sizeof(v4_rule)); + + v4_rule.private_ip = nat_rule_ptr->private_ip; + v4_rule.private_port = nat_rule_ptr->private_port; + v4_rule.protocol = nat_rule_ptr->protocol; + v4_rule.public_port = nat_rule_ptr->public_port; + v4_rule.target_ip = nat_rule_ptr->target_ip; + v4_rule.target_port = nat_rule_ptr->target_port; + v4_rule.pdn_index = nat_rule_ptr->pdn_index; + v4_rule.redirect = nat_rule_ptr->redirect; + v4_rule.enable = nat_rule_ptr->enable; + v4_rule.time_stamp = nat_rule_ptr->time_stamp; + v4_rule.uc_activation_index = nat_rule_ptr->uc_activation_index; + v4_rule.s = nat_rule_ptr->s; + v4_rule.ucp = nat_rule_ptr->ucp; + v4_rule.dst_only = nat_rule_ptr->dst_only; + v4_rule.src_only = nat_rule_ptr->src_only; + + ret = ipa_NATI_add_ipv4_rule(dst_tbl_hdl, &v4_rule, &new_rule_hdl); + + if ( ret != 0 ) + { + IPAERR("%s: ipa_NATI_add_ipv4_rule() fail\n", mig_dir_ptr); + goto bail; + } + + (*cnt_ptr)++; + + /* + * The following is needed to maintain the original handle and + * have it point to the new handle. + * + * Remember, original handle points to new and the new handle + * points back to original. + */ + ret = ipa_nat_map_add(dst_orig2new_map, orig_rule_hdl, new_rule_hdl); + + if ( ret != 0 ) + { + IPAERR("%s: ipa_nat_map_add(dst_orig2new_map) fail\n", mig_dir_ptr); + goto bail; + } + + ret = ipa_nat_map_add(dst_new2orig_map, new_rule_hdl, orig_rule_hdl); + + if ( ret != 0 ) + { + IPAERR("%s: ipa_nat_map_add(dst_new2orig_map) fail\n", mig_dir_ptr); + goto bail; + } + + IPADBG("orig_rule_hdl(0x%08X) new_rule_hdl(0x%08X)\n", + orig_rule_hdl, new_rule_hdl); + +bail: + IPADBG("Out\n"); + + return ret; +} + +/* + * **************************************************************************** + * + * STATE MACHINE CODE BEGINS HERE + * + * **************************************************************************** + */ +static int _smUndef( + ipa_nati_obj* nati_obj_ptr, + ipa_nati_trigger trigger, + arb_t* arb_data_ptr ); /* forward declaration */ + +/******************************************************************************/ +/* + * FUNCTION: _smDelTbl + * + * PARAMS: + * + * nati_obj_ptr (IN) A pointer to an initialized nati object + * + * trigger (IN) The trigger to run through the state machine + * + * arb_data_ptr (IN) Whatever you like + * + * DESCRIPTION: + * + * The following will cause the destruction of the DDR based NAT + * table. + * + * RETURNS: + * + * zero on success, otherwise non-zero + */ +static int _smDelTbl( + ipa_nati_obj* nati_obj_ptr, + ipa_nati_trigger trigger, + arb_t* arb_data_ptr ) +{ + arb_t** args = arb_data_ptr; + + uint32_t tbl_hdl = (uint32_t) args[0]; + + int ret; + + IPADBG("In\n"); + + IPADBG("tbl_hdl(0x%08X)\n", tbl_hdl); + + ret = ipa_NATI_del_ipv4_table(tbl_hdl); + + if ( ret == 0 && ! IN_HYBRID_STATE() ) + { + /* + * The following will create the preferred "initial state" for + * restart... + */ + BACK2_UNSTARTED_STATE(); + } + + IPADBG("Out\n"); + + return ret; +} + +/******************************************************************************/ +/* + * FUNCTION: _smFirstTbl + * + * PARAMS: + * + * nati_obj_ptr (IN) A pointer to an initialized nati object + * + * trigger (IN) The trigger to run through the state machine + * + * arb_data_ptr (IN) Whatever you like + * + * DESCRIPTION: + * + * The following will cause the creation of the very first NAT table(s) + * before any others have ever been created... + * + * RETURNS: + * + * zero on success, otherwise non-zero + */ +static int _smFirstTbl( + ipa_nati_obj* nati_obj_ptr, + ipa_nati_trigger trigger, + arb_t* arb_data_ptr ) +{ + arb_t** args = arb_data_ptr; + + uint32_t public_ip_addr = (uint32_t) args[0]; + uint16_t number_of_entries = (uint16_t) args[1]; + uint32_t* tbl_hdl_ptr = (uint32_t*) args[2]; + const char* mem_type_ptr = (const char*) args[3]; + + int ret; + + IPADBG("In\n"); + + /* + * This is the first time in here. Let the ipacm's XML config (or + * state_to_hold) drive initial state... + */ + SET_NATIOBJ_STATE( + nati_obj_ptr, + (nati_obj_ptr->hold_state && nati_obj_ptr->state_to_hold) ? + nati_obj_ptr->state_to_hold : + mem_type_str_to_ipa_nati_state(mem_type_ptr)); + + ret = ipa_nati_statemach(nati_obj_ptr, NATI_TRIG_ADD_TABLE, args); + + IPADBG("Out\n"); + + return ret; +} + +/******************************************************************************/ +/* + * FUNCTION: _smAddDdrTbl + * + * PARAMS: + * + * nati_obj_ptr (IN) A pointer to an initialized nati object + * + * trigger (IN) The trigger to run through the state machine + * + * arb_data_ptr (IN) Whatever you like + * + * DESCRIPTION: + * + * The following will cause the creation of a NAT table in DDR. + * + * RETURNS: + * + * zero on success, otherwise non-zero + */ +static int _smAddDdrTbl( + ipa_nati_obj* nati_obj_ptr, + ipa_nati_trigger trigger, + arb_t* arb_data_ptr ) +{ + arb_t** args = arb_data_ptr; + + uint32_t public_ip_addr = (uint32_t) args[0]; + uint16_t number_of_entries = (uint16_t) args[1]; + uint32_t* tbl_hdl_ptr = (uint32_t*) args[2]; + + int ret; + + IPADBG("In\n"); + + IPADBG("public_ip_addr(0x%08X) number_of_entries(%u) tbl_hdl_ptr(%p)\n", + public_ip_addr, number_of_entries, tbl_hdl_ptr); + + ret = ipa_NATI_add_ipv4_tbl( + IPA_NAT_MEM_IN_DDR, + public_ip_addr, + number_of_entries, + &nati_obj_ptr->ddr_tbl_hdl); + + if ( ret == 0 ) + { + *tbl_hdl_ptr = nati_obj_ptr->ddr_tbl_hdl; + + IPADBG("DDR table creation successful: tbl_hdl(0x%08X)\n", + *tbl_hdl_ptr); + } + + IPADBG("Out\n"); + + return ret; +} + +/******************************************************************************/ +/* + * FUNCTION: _smAddSramTbl + * + * PARAMS: + * + * nati_obj_ptr (IN) A pointer to an initialized nati object + * + * trigger (IN) The trigger to run through the state machine + * + * arb_data_ptr (IN) Whatever you like + * + * DESCRIPTION: + * + * The following will cause the creation of a NAT table in SRAM. + * + * RETURNS: + * + * zero on success, otherwise non-zero + */ +static int _smAddSramTbl( + ipa_nati_obj* nati_obj_ptr, + ipa_nati_trigger trigger, + arb_t* arb_data_ptr ) +{ + arb_t** args = arb_data_ptr; + + uint32_t public_ip_addr = (uint32_t) args[0]; + uint16_t number_of_entries = (uint16_t) args[1]; + uint32_t* tbl_hdl_ptr = (uint32_t*) args[2]; + + uint32_t sram_size = 0; + + int ret; + + IPADBG("In\n"); + + IPADBG("public_ip_addr(0x%08X) tbl_hdl_ptr(%p)\n", + public_ip_addr, tbl_hdl_ptr); + + ret = ipa_nati_get_sram_size(&sram_size); + + if ( ret == 0 ) + { + ret = ipa_calc_num_sram_table_entries( + sram_size, + sizeof(struct ipa_nat_rule), + sizeof(struct ipa_nat_indx_tbl_rule), + &nati_obj_ptr->tot_slots_in_sram); + + if ( ret == 0 ) + { + nati_obj_ptr->back_to_sram_thresh = + PRCNT_OF(nati_obj_ptr->tot_slots_in_sram); + + IPADBG("sram_size(%u or 0x%x) tot_slots_in_sram(%u) back_to_sram_thresh(%u)\n", + sram_size, + sram_size, + nati_obj_ptr->tot_slots_in_sram, + nati_obj_ptr->back_to_sram_thresh); + + IPADBG("Voting clock on for sram table creation\n"); + + if ( (ret = ipa_nat_vote_clock(IPA_APP_CLK_VOTE)) != 0 ) + { + IPAERR("Voting clock on failed\n"); + goto done; + } + + ret = ipa_NATI_add_ipv4_tbl( + IPA_NAT_MEM_IN_SRAM, + public_ip_addr, + nati_obj_ptr->tot_slots_in_sram, + &nati_obj_ptr->sram_tbl_hdl); + + if ( ipa_nat_vote_clock(IPA_APP_CLK_DEVOTE) != 0 ) + { + IPAWARN("Voting clock off failed\n"); + } + + if ( ret == 0 ) + { + *tbl_hdl_ptr = nati_obj_ptr->sram_tbl_hdl; + + IPADBG("SRAM table creation successful: tbl_hdl(0x%08X)\n", + *tbl_hdl_ptr); + } + } + } + +done: + IPADBG("Out\n"); + + return ret; +} + +/******************************************************************************/ +/* + * FUNCTION: _smAddSramAndDdrTbl + * + * PARAMS: + * + * nati_obj_ptr (IN) A pointer to an initialized nati object + * + * trigger (IN) The trigger to run through the state machine + * + * arb_data_ptr (IN) Whatever you like + * + * DESCRIPTION: + * + * The following will cause the creation of NAT tables in both DDR + * and in SRAM. + * + * RETURNS: + * + * zero on success, otherwise non-zero + */ +static int _smAddSramAndDdrTbl( + ipa_nati_obj* nati_obj_ptr, + ipa_nati_trigger trigger, + arb_t* arb_data_ptr ) +{ + arb_t** args = arb_data_ptr; + + uint32_t public_ip_addr = (uint32_t) args[0]; + uint16_t number_of_entries = (uint16_t) args[1]; + uint32_t* tbl_hdl_ptr = (uint32_t*) args[2]; + + uint32_t tbl_hdl; + + int ret; + + IPADBG("In\n"); + + nati_obj_ptr->tot_rules_in_table[SRAM_SUB] = 0; + nati_obj_ptr->tot_rules_in_table[DDR_SUB] = 0; + + ipa_nat_map_clear(nati_obj_ptr->map_pairs[SRAM_SUB].orig2new_map); + ipa_nat_map_clear(nati_obj_ptr->map_pairs[SRAM_SUB].new2orig_map); + ipa_nat_map_clear(nati_obj_ptr->map_pairs[DDR_SUB].orig2new_map); + ipa_nat_map_clear(nati_obj_ptr->map_pairs[DDR_SUB].new2orig_map); + + ret = _smAddSramTbl(nati_obj_ptr, trigger, arb_data_ptr); + + if ( ret == 0 ) + { + if ( nati_obj_ptr->tot_slots_in_sram >= number_of_entries ) + { + /* + * The number of slots in SRAM can accommodate what was + * being requested for DDR, hence no need to use DDR and + * we will continue by using SRAM only... + */ + SET_NATIOBJ_STATE(nati_obj_ptr, NATI_STATE_SRAM_ONLY); + } + else + { + /* + * SRAM not big enough. Let's create secondary DDR based + * table... + */ + arb_t* new_args[] = { + (arb_t*)(arb_t)public_ip_addr, + (arb_t*)(arb_t)number_of_entries, + (arb_t*) &tbl_hdl, /* to protect app's table handle above */ + }; + + ret = _smAddDdrTbl(nati_obj_ptr, trigger, new_args); + + if ( ret == 0 ) + { + /* + * The following will tell the IPA to change focus to + * SRAM... + */ + ret = ipa_nati_statemach(nati_obj_ptr, NATI_TRIG_GOTO_SRAM, 0); + } + } + } + else + { + /* + * SRAM table creation in HYBRID mode failed. Can we fall + * back to DDR only? We need to try and see what happens... + */ + ret = _smAddDdrTbl(nati_obj_ptr, trigger, arb_data_ptr); + + if ( ret == 0 ) + { + SET_NATIOBJ_STATE(nati_obj_ptr, NATI_STATE_DDR_ONLY); + } + } + + IPADBG("Out\n"); + + return ret; +} + +/******************************************************************************/ +/* + * FUNCTION: _smDelSramAndDdrTbl + * + * PARAMS: + * + * nati_obj_ptr (IN) A pointer to an initialized nati object + * + * trigger (IN) The trigger to run through the state machine + * + * arb_data_ptr (IN) Whatever you like + * + * DESCRIPTION: + * + * The following will cause the destruction of the SRAM, then DDR + * based NAT tables. + * + * RETURNS: + * + * zero on success, otherwise non-zero + */ +static int _smDelSramAndDdrTbl( + ipa_nati_obj* nati_obj_ptr, + ipa_nati_trigger trigger, + arb_t* arb_data_ptr ) +{ + int ret; + + IPADBG("In\n"); + + nati_obj_ptr->tot_rules_in_table[SRAM_SUB] = 0; + nati_obj_ptr->tot_rules_in_table[DDR_SUB] = 0; + + ipa_nat_map_clear(nati_obj_ptr->map_pairs[SRAM_SUB].orig2new_map); + ipa_nat_map_clear(nati_obj_ptr->map_pairs[SRAM_SUB].new2orig_map); + ipa_nat_map_clear(nati_obj_ptr->map_pairs[DDR_SUB].orig2new_map); + ipa_nat_map_clear(nati_obj_ptr->map_pairs[DDR_SUB].new2orig_map); + + ret = _smDelTbl(nati_obj_ptr, trigger, arb_data_ptr); + + if ( ret == 0 ) + { + arb_t* new_args[] = { + (arb_t*)(arb_t)nati_obj_ptr->ddr_tbl_hdl, + }; + + ret = _smDelTbl(nati_obj_ptr, trigger, new_args); + } + + if ( ret == 0 ) + { + /* + * The following will create the preferred "initial state" for + * restart... + */ + BACK2_UNSTARTED_STATE(); + } + + IPADBG("Out\n"); + + return ret; +} + +/******************************************************************************/ +/* + * FUNCTION: _smClrTbl + * + * PARAMS: + * + * nati_obj_ptr (IN) A pointer to an initialized nati object + * + * trigger (IN) The trigger to run through the state machine + * + * arb_data_ptr (IN) Whatever you like + * + * DESCRIPTION: + * + * The following will cause the clearing of a table. + * + * RETURNS: + * + * zero on success, otherwise non-zero + */ +static int _smClrTbl( + ipa_nati_obj* nati_obj_ptr, + ipa_nati_trigger trigger, + arb_t* arb_data_ptr ) +{ + arb_t** args = arb_data_ptr; + + uint32_t tbl_hdl = (uint32_t) args[0]; + + enum ipa3_nat_mem_in nmi; + uint32_t unused_hdl, sub; + + int ret; + + IPADBG("In\n"); + + IPADBG("tbl_hdl(0x%08X)\n", tbl_hdl); + + BREAK_TBL_HDL(tbl_hdl, nmi, unused_hdl); + + if ( ! IPA_VALID_NAT_MEM_IN(nmi) ) { + IPAERR("Bad cache type\n"); + ret = -EINVAL; + goto bail; + } + + sub = (nmi == IPA_NAT_MEM_IN_SRAM) ? SRAM_SUB : DDR_SUB; + + nati_obj_ptr->tot_rules_in_table[sub] = 0; + + ipa_nat_map_clear(nati_obj.map_pairs[sub].orig2new_map); + ipa_nat_map_clear(nati_obj.map_pairs[sub].new2orig_map); + + ret = ipa_NATI_clear_ipv4_tbl(tbl_hdl); + +bail: + IPADBG("Out\n"); + + return ret; +} + +/******************************************************************************/ +/* + * FUNCTION: _smClrTblHybrid + * + * PARAMS: + * + * nati_obj_ptr (IN) A pointer to an initialized nati object + * + * trigger (IN) The trigger to run through the state machine + * + * arb_data_ptr (IN) Whatever you like + * + * DESCRIPTION: + * + * The following will cause the clearing of the appropriate hybrid + * table. + * + * RETURNS: + * + * zero on success, otherwise non-zero + */ +static int _smClrTblHybrid( + ipa_nati_obj* nati_obj_ptr, + ipa_nati_trigger trigger, + arb_t* arb_data_ptr ) +{ + arb_t** args = arb_data_ptr; + + uint32_t tbl_hdl = (uint32_t) args[0]; + + arb_t* new_args[] = { + (arb_t*)(arb_t)(nati_obj_ptr->curr_state == NATI_STATE_HYBRID) ? + tbl_hdl : + nati_obj_ptr->ddr_tbl_hdl, + }; + + int ret; + + IPADBG("In\n"); + + ret = _smClrTbl(nati_obj_ptr, trigger, new_args); + + IPADBG("Out\n"); + + return ret; +} + +/******************************************************************************/ +/* + * FUNCTION: _smWalkTbl + * + * PARAMS: + * + * nati_obj_ptr (IN) A pointer to an initialized nati object + * + * trigger (IN) The trigger to run through the state machine + * + * arb_data_ptr (IN) Whatever you like + * + * DESCRIPTION: + * + * The following will cause the walk of a table. + * + * RETURNS: + * + * zero on success, otherwise non-zero + */ +static int _smWalkTbl( + ipa_nati_obj* nati_obj_ptr, + ipa_nati_trigger trigger, + arb_t* arb_data_ptr ) +{ + arb_t** args = arb_data_ptr; + + uint32_t tbl_hdl = (uint32_t) args[0]; + WhichTbl2Use which = (WhichTbl2Use) args[1]; + ipa_table_walk_cb walk_cb = (ipa_table_walk_cb) args[2]; + arb_t* wadp = (arb_t*) args[3]; + + int ret; + + IPADBG("In\n"); + + IPADBG("tbl_hdl(0x%08X)\n", tbl_hdl); + + ret = ipa_NATI_walk_ipv4_tbl(tbl_hdl, which, walk_cb, wadp); + + IPADBG("Out\n"); + + return ret; +} + +/******************************************************************************/ +/* + * FUNCTION: _smWalkTblHybrid + * + * PARAMS: + * + * nati_obj_ptr (IN) A pointer to an initialized nati object + * + * trigger (IN) The trigger to run through the state machine + * + * arb_data_ptr (IN) Whatever you like + * + * DESCRIPTION: + * + * The following will cause the walk of the appropriate hybrid + * table. + * + * RETURNS: + * + * zero on success, otherwise non-zero + */ +static int _smWalkTblHybrid( + ipa_nati_obj* nati_obj_ptr, + ipa_nati_trigger trigger, + arb_t* arb_data_ptr ) +{ + arb_t** args = arb_data_ptr; + + uint32_t tbl_hdl = (uint32_t) args[0]; + WhichTbl2Use which = (WhichTbl2Use) args[1]; + ipa_table_walk_cb walk_cb = (ipa_table_walk_cb) args[2]; + arb_t* wadp = (arb_t*) args[3]; + + arb_t* new_args[] = { + (arb_t*)(arb_t)(nati_obj_ptr->curr_state == NATI_STATE_HYBRID) ? + tbl_hdl : + nati_obj_ptr->ddr_tbl_hdl, + (arb_t*) which, + (arb_t*) walk_cb, + (arb_t*) wadp, + }; + + int ret; + + IPADBG("In\n"); + + ret = _smWalkTbl(nati_obj_ptr, trigger, new_args); + + IPADBG("Out\n"); + + return ret; +} + +/******************************************************************************/ +/* + * FUNCTION: _smStatTbl + * + * PARAMS: + * + * nati_obj_ptr (IN) A pointer to an initialized nati object + * + * trigger (IN) The trigger to run through the state machine + * + * arb_data_ptr (IN) Whatever you like + * + * DESCRIPTION: + * + * The following will get size/usage stats for a table. + * + * RETURNS: + * + * zero on success, otherwise non-zero + */ +static int _smStatTbl( + ipa_nati_obj* nati_obj_ptr, + ipa_nati_trigger trigger, + arb_t* arb_data_ptr ) +{ + arb_t** args = arb_data_ptr; + + uint32_t tbl_hdl = (uint32_t) args[0]; + ipa_nati_tbl_stats* nat_stats_ptr = (ipa_nati_tbl_stats*) args[1]; + ipa_nati_tbl_stats* idx_stats_ptr = (ipa_nati_tbl_stats*) args[2]; + + int ret; + + IPADBG("In\n"); + + IPADBG("tbl_hdl(0x%08X)\n", tbl_hdl); + + ret = ipa_NATI_ipv4_tbl_stats(tbl_hdl, nat_stats_ptr, idx_stats_ptr); + + IPADBG("Out\n"); + + return ret; +} + +/******************************************************************************/ +/* + * FUNCTION: _smStatTblHybrid + * + * PARAMS: + * + * nati_obj_ptr (IN) A pointer to an initialized nati object + * + * trigger (IN) The trigger to run through the state machine + * + * arb_data_ptr (IN) Whatever you like + * + * DESCRIPTION: + * + * The following will cause the retrieval of table size/usage stats + * for the appropriate hybrid table. + * + * RETURNS: + * + * zero on success, otherwise non-zero + */ +static int _smStatTblHybrid( + ipa_nati_obj* nati_obj_ptr, + ipa_nati_trigger trigger, + arb_t* arb_data_ptr ) +{ + arb_t** args = arb_data_ptr; + + uint32_t tbl_hdl = (uint32_t) args[0]; + ipa_nati_tbl_stats* nat_stats_ptr = (ipa_nati_tbl_stats*) args[1]; + ipa_nati_tbl_stats* idx_stats_ptr = (ipa_nati_tbl_stats*) args[2]; + + arb_t* new_args[] = { + (arb_t*)(arb_t)(nati_obj_ptr->curr_state == NATI_STATE_HYBRID) ? + tbl_hdl : + nati_obj_ptr->ddr_tbl_hdl, + (arb_t*) nat_stats_ptr, + (arb_t*) idx_stats_ptr, + }; + + int ret; + + IPADBG("In\n"); + + ret = _smStatTbl(nati_obj_ptr, trigger, new_args); + + IPADBG("Out\n"); + + return ret; +} + +/******************************************************************************/ +/* + * FUNCTION: _smAddRuleToTbl + * + * PARAMS: + * + * nati_obj_ptr (IN) A pointer to an initialized nati object + * + * trigger (IN) The trigger to run through the state machine + * + * arb_data_ptr (IN) Whatever you like + * + * DESCRIPTION: + * + * The following will cause the addtion of a NAT rule into the DDR + * based table. + * + * RETURNS: + * + * zero on success, otherwise non-zero + */ +static int _smAddRuleToTbl( + ipa_nati_obj* nati_obj_ptr, + ipa_nati_trigger trigger, + arb_t* arb_data_ptr ) +{ + arb_t** args = arb_data_ptr; + + uint32_t tbl_hdl = (uint32_t) args[0]; + ipa_nat_ipv4_rule* clnt_rule = (ipa_nat_ipv4_rule*) args[1]; + uint32_t* rule_hdl = (uint32_t*) args[2]; + + char buf[1024]; + + int ret; + + IPADBG("In\n"); + + IPADBG("tbl_hdl(0x%08X) clnt_rule_ptr(%p) rule_hdl_ptr(%p) %s\n", + tbl_hdl, clnt_rule, rule_hdl, + prep_nat_ipv4_rule_4print(clnt_rule, buf, sizeof(buf))); + + clnt_rule->redirect = clnt_rule->enable = clnt_rule->time_stamp = 0; + + ret = ipa_NATI_add_ipv4_rule(tbl_hdl, clnt_rule, rule_hdl); + + if ( ret == 0 ) + { + uint32_t* cnt_ptr = CHOOSE_CNTR(); + + (*cnt_ptr)++; + + IPADBG("rule_hdl value(%u or 0x%08X)\n", + *rule_hdl, *rule_hdl); + } + + IPADBG("Out\n"); + + return ret; +} + +/******************************************************************************/ +/* + * FUNCTION: _smDelRuleFromTbl + * + * PARAMS: + * + * nati_obj_ptr (IN) A pointer to an initialized nati object + * + * trigger (IN) The trigger to run through the state machine + * + * arb_data_ptr (IN) Whatever you like + * + * DESCRIPTION: + * + * The following will cause the deletion of a NAT rule from the DDR + * based table. + * + * RETURNS: + * + * zero on success, otherwise non-zero + */ +static int _smDelRuleFromTbl( + ipa_nati_obj* nati_obj_ptr, + ipa_nati_trigger trigger, + arb_t* arb_data_ptr ) +{ + arb_t** args = arb_data_ptr; + + uint32_t tbl_hdl = (uint32_t) args[0]; + uint32_t rule_hdl = (uint32_t) args[1]; + + int ret; + + IPADBG("In\n"); + + IPADBG("tbl_hdl(0x%08X) rule_hdl(%u)\n", tbl_hdl, rule_hdl); + + ret = ipa_NATI_del_ipv4_rule(tbl_hdl, rule_hdl); + + if ( ret == 0 ) + { + uint32_t* cnt_ptr = CHOOSE_CNTR(); + + (*cnt_ptr)--; + } + + IPADBG("Out\n"); + + return ret; +} + +/******************************************************************************/ +/* + * FUNCTION: _smAddRuleHybrid + * + * PARAMS: + * + * nati_obj_ptr (IN) A pointer to an initialized nati object + * + * trigger (IN) The trigger to run through the state machine + * + * arb_data_ptr (IN) Whatever you like + * + * DESCRIPTION: + * + * The following will cause the addition of a NAT rule into either + * the SRAM or DDR based table. + * + * *** !!! HOWEVER *** REMEMBER !!! *** + * + * We're here because we're in a HYBRID state...with the potential + * moving between SRAM and DDR. THIS HAS IMLICATIONS AS IT RELATES + * TO RULE MAPPING. + * + * RETURNS: + * + * zero on success, otherwise non-zero + */ +static int _smAddRuleHybrid( + ipa_nati_obj* nati_obj_ptr, + ipa_nati_trigger trigger, + arb_t* arb_data_ptr ) +{ + arb_t** args = arb_data_ptr; + + uint32_t tbl_hdl = (uint32_t) args[0]; + ipa_nat_ipv4_rule* clnt_rule = (ipa_nat_ipv4_rule*) args[1]; + uint32_t* rule_hdl = (uint32_t*) args[2]; + + arb_t* new_args[] = { + (arb_t*)(arb_t)(nati_obj_ptr->curr_state == NATI_STATE_HYBRID) ? + tbl_hdl : + nati_obj_ptr->ddr_tbl_hdl, + (arb_t*) clnt_rule, + (arb_t*) rule_hdl, + }; + + uint32_t orig2new_map, new2orig_map; + + int ret; + + IPADBG("In\n"); + + ret = _smAddRuleToTbl(nati_obj_ptr, trigger, new_args); + + if ( ret == 0 ) + { + /* + * The rule_hdl is used to find a rule in the nat table. It + * is, in effect, an index into the table. The applcation + * above us retains it for future manipulation of the rule in + * the table. + * + * In hybrid mode, a rule can and will move between SRAM and + * DDR. Because of this, its handle will change. The + * application has only the original handle and doesn't know + * of the new handle. A mapping, used in hybrid mode, will + * maintain a relationship between the original handle and the + * rule's current real handle... + * + * To help you get a mindset of how this is done: + * + * The original handle will map (point) to the new and new + * handle will map (point) back to original. + * + * NOTE WELL: There are two sets of maps. One for each memory + * type... + */ + CHOOSE_MAPS(orig2new_map, new2orig_map); + + ret = ipa_nat_map_add(orig2new_map, *rule_hdl, *rule_hdl); + + if ( ret == 0 ) + { + ret = ipa_nat_map_add(new2orig_map, *rule_hdl, *rule_hdl); + } + } + else + { + if ( nati_obj_ptr->curr_state == NATI_STATE_HYBRID + && + ! nati_obj_ptr->hold_state ) + { + /* + * In hybrid mode, we always start in SRAM...hence + * NATI_STATE_HYBRID implies SRAM. The rule addition + * above did not work, meaning the SRAM table is full, + * hence let's jump to DDR... + * + * The following will focus us on DDR and cause the copy + * of data from SRAM to DDR. + */ + IPAINFO("Add of rule failed...attempting table switch\n"); + + ret = ipa_nati_statemach(nati_obj_ptr, NATI_TRIG_TBL_SWITCH, 0); + + if ( ret == 0 ) + { + SET_NATIOBJ_STATE(nati_obj_ptr, NATI_STATE_HYBRID_DDR); + + /* + * Now add the rule to DDR... + */ + ret = ipa_nati_statemach(nati_obj_ptr, trigger, arb_data_ptr); + } + } + } + + IPADBG("Out\n"); + + return ret; +} + +/******************************************************************************/ +/* + * FUNCTION: _smDelRuleHybrid + * + * PARAMS: + * + * nati_obj_ptr (IN) A pointer to an initialized nati object + * + * trigger (IN) The trigger to run through the state machine + * + * arb_data_ptr (IN) Whatever you like + * + * DESCRIPTION: + * + * The following will cause the deletion of a NAT rule from either + * the SRAM or DDR based table. + * + * *** !!! HOWEVER *** REMEMBER !!! *** + * + * We're here because we're in a HYBRID state...with the potential + * moving between SRAM and DDR. THIS HAS IMLICATIONS AS IT RELATES + * TO RULE MAPPING. + * + * RETURNS: + * + * zero on success, otherwise non-zero + */ +static int _smDelRuleHybrid( + ipa_nati_obj* nati_obj_ptr, + ipa_nati_trigger trigger, + arb_t* arb_data_ptr ) +{ + arb_t** args = arb_data_ptr; + + uint32_t tbl_hdl = (uint32_t) args[0]; + uint32_t orig_rule_hdl = (uint32_t) args[1]; + + uint32_t new_rule_hdl; + + uint32_t orig2new_map, new2orig_map; + + int ret; + + IPADBG("In\n"); + + CHOOSE_MAPS(orig2new_map, new2orig_map); + + /* + * The rule_hdl is used to find a rule in the nat table. It is, + * in effect, an index into the table. The applcation above us + * retains it for future manipulation of the rule in the table. + * + * In hybrid mode, a rule can and will move between SRAM and DDR. + * Because of this, its handle will change. The application has + * only the original handle and doesn't know of the new handle. A + * mapping, used in hybrid mode, will maintain a relationship + * between the original handle and the rule's current real + * handle... + * + * To help you get a mindset of how this is done: + * + * The original handle will map (point) to the new and new + * handle will map (point) back to original. + * + * NOTE WELL: There are two sets of maps. One for each memory + * type... + */ + ret = ipa_nat_map_del(orig2new_map, orig_rule_hdl, &new_rule_hdl); + + if ( ret == 0 ) + { + arb_t* new_args[] = { + (arb_t*)(arb_t)(nati_obj_ptr->curr_state == NATI_STATE_HYBRID) ? + tbl_hdl : + nati_obj_ptr->ddr_tbl_hdl, + (arb_t*)(arb_t)new_rule_hdl, + }; + + IPADBG("orig_rule_hdl(0x%08X) -> new_rule_hdl(0x%08X)\n", + orig_rule_hdl, new_rule_hdl); + + ipa_nat_map_del(new2orig_map, new_rule_hdl, NULL); + + ret = _smDelRuleFromTbl(nati_obj_ptr, trigger, new_args); + + if ( ret == 0 && nati_obj_ptr->curr_state == NATI_STATE_HYBRID_DDR ) + { + /* + * We need to check when/if we can go back to SRAM. + * + * How/why can we go back? + * + * Given enough deletions, and when we get to a user + * defined threshold (ie. a percentage of what SRAM can + * hold), we can pop back to using SRAM. + */ + uint32_t* cnt_ptr = CHOOSE_CNTR(); + + if ( *cnt_ptr <= nati_obj_ptr->back_to_sram_thresh + && + ! nati_obj_ptr->hold_state ) + { + /* + * The following will focus us on SRAM and cause the copy + * of data from DDR to SRAM. + */ + IPAINFO("Switch back to SRAM threshold has been reached -> " + "Total rules in DDR(%u) <= SRAM THRESH(%u)\n", + *cnt_ptr, + nati_obj_ptr->back_to_sram_thresh); + + ret = ipa_nati_statemach(nati_obj_ptr, NATI_TRIG_TBL_SWITCH, 0); + + if ( ret == 0 ) + { + SET_NATIOBJ_STATE(nati_obj_ptr, NATI_STATE_HYBRID); + } + else + { + /* + * The following will force us stay in DDR for + * now, but the next delete will trigger the + * switch logic above to run again...perhaps it + * will work then. + */ + ret = 0; + } + } + } + } + + IPADBG("Out\n"); + + return ret; +} + +/******************************************************************************/ +/* + * FUNCTION: _smGoToDdr + * + * PARAMS: + * + * nati_obj_ptr (IN) A pointer to an initialized nati object + * + * trigger (IN) The trigger to run through the state machine + * + * arb_data_ptr (IN) Whatever you like + * + * DESCRIPTION: + * + * The following will cause the IPA to use the DDR based NAT + * table... + * + * RETURNS: + * + * zero on success, otherwise non-zero + */ +static int _smGoToDdr( + ipa_nati_obj* nati_obj_ptr, + ipa_nati_trigger trigger, + arb_t* arb_data_ptr ) +{ + int ret; + + IPADBG("In\n"); + + ret = ipa_NATI_post_ipv4_init_cmd(nati_obj_ptr->ddr_tbl_hdl); + + if ( ret == 0 ) + { + SET_NATIOBJ_STATE(nati_obj_ptr, NATI_STATE_HYBRID_DDR); + } + + IPADBG("Out\n"); + + return ret; +} + +/******************************************************************************/ +/* + * FUNCTION: _smGoToSram + * + * PARAMS: + * + * nati_obj_ptr (IN) A pointer to an initialized nati object + * + * trigger (IN) The trigger to run through the state machine + * + * arb_data_ptr (IN) Whatever you like + * + * DESCRIPTION: + * + * The following will cause the IPA to use the SRAM based NAT + * table... + * + * RETURNS: + * + * zero on success, otherwise non-zero + */ +static int _smGoToSram( + ipa_nati_obj* nati_obj_ptr, + ipa_nati_trigger trigger, + arb_t* arb_data_ptr ) +{ + int ret; + + IPADBG("In\n"); + + ret = ipa_NATI_post_ipv4_init_cmd(nati_obj_ptr->sram_tbl_hdl); + + if ( ret == 0 ) + { + SET_NATIOBJ_STATE(nati_obj_ptr, NATI_STATE_HYBRID); + } + + IPADBG("Out\n"); + + return ret; +} + +/******************************************************************************/ +/* + * FUNCTION: _smSwitchFromDdrToSram + * + * PARAMS: + * + * nati_obj_ptr (IN) A pointer to an initialized nati object + * + * trigger (IN) The trigger to run through the state machine + * + * arb_data_ptr (IN) Whatever you like + * + * DESCRIPTION: + * + * The following will cause a copy of the DDR table to SRAM and then + * will make the IPA use the SRAM... + * + * RETURNS: + * + * zero on success, otherwise non-zero + */ +static int _smSwitchFromDdrToSram( + ipa_nati_obj* nati_obj_ptr, + ipa_nati_trigger trigger, + arb_t* arb_data_ptr ) +{ + nati_switch_stats* sw_stats_ptr = CHOOSE_SW_STATS(); + + uint32_t* cnt_ptr = CHOOSE_CNTR(); + + ipa_nati_tbl_stats nat_stats, idx_stats; + + const char* mem_type; + + uint64_t start, stop; + + int stats_ret, ret; + + bool collect_stats = (bool) arb_data_ptr; + + IPADBG("In\n"); + + stats_ret = (collect_stats) ? + ipa_NATI_ipv4_tbl_stats( + nati_obj_ptr->ddr_tbl_hdl, &nat_stats, &idx_stats) : + -1; + + currTimeAs(TimeAsNanSecs, &start); + + /* + * First, switch focus to SRAM... + */ + ret = ipa_nati_statemach(nati_obj_ptr, NATI_TRIG_GOTO_SRAM, 0); + + if ( ret == 0 ) + { + /* + * Clear destination counter... + */ + nati_obj_ptr->tot_rules_in_table[SRAM_SUB] = 0; + + /* + * Clear destination SRAM maps... + */ + ipa_nat_map_clear(nati_obj.map_pairs[SRAM_SUB].orig2new_map); + ipa_nat_map_clear(nati_obj.map_pairs[SRAM_SUB].new2orig_map); + + /* + * Now copy DDR's content to SRAM... + */ + ret = ipa_nati_copy_ipv4_tbl( + nati_obj_ptr->ddr_tbl_hdl, + nati_obj_ptr->sram_tbl_hdl, + migrate_rule); + + currTimeAs(TimeAsNanSecs, &stop); + + if ( ret == 0 ) + { + sw_stats_ptr->pass += 1; + + IPADBG("Transistion from DDR to SRAM took %f microseconds\n", + (float) (stop - start) / 1000.0); + } + else + { + sw_stats_ptr->fail += 1; + } + + IPADBG("Transistion pass/fail counts (DDR to SRAM) PASS: %u FAIL: %u\n", + sw_stats_ptr->pass, + sw_stats_ptr->fail); + + if ( stats_ret == 0 ) + { + mem_type = ipa3_nat_mem_in_as_str(nat_stats.nmi); + + /* + * NAT table stats... + */ + IPADBG("Able to add (%u) records to %s " + "NAT table of size (%u) or (%f) percent\n", + *cnt_ptr, + mem_type, + nat_stats.tot_ents, + ((float) *cnt_ptr / (float) nat_stats.tot_ents) * 100.0); + + IPADBG("Able to add (%u) records to %s " + "NAT BASE table of size (%u) or (%f) percent\n", + nat_stats.tot_base_ents_filled, + mem_type, + nat_stats.tot_base_ents, + ((float) nat_stats.tot_base_ents_filled / + (float) nat_stats.tot_base_ents) * 100.0); + + IPADBG("Able to add (%u) records to %s " + "NAT EXPN table of size (%u) or (%f) percent\n", + nat_stats.tot_expn_ents_filled, + mem_type, + nat_stats.tot_expn_ents, + ((float) nat_stats.tot_expn_ents_filled / + (float) nat_stats.tot_expn_ents) * 100.0); + + IPADBG("%s NAT table chains: tot_chains(%u) min_len(%u) max_len(%u) avg_len(%f)\n", + mem_type, + nat_stats.tot_chains, + nat_stats.min_chain_len, + nat_stats.max_chain_len, + nat_stats.avg_chain_len); + + /* + * INDEX table stats... + */ + IPADBG("Able to add (%u) records to %s " + "IDX table of size (%u) or (%f) percent\n", + *cnt_ptr, + mem_type, + idx_stats.tot_ents, + ((float) *cnt_ptr / (float) idx_stats.tot_ents) * 100.0); + + IPADBG("Able to add (%u) records to %s " + "IDX BASE table of size (%u) or (%f) percent\n", + idx_stats.tot_base_ents_filled, + mem_type, + idx_stats.tot_base_ents, + ((float) idx_stats.tot_base_ents_filled / + (float) idx_stats.tot_base_ents) * 100.0); + + IPADBG("Able to add (%u) records to %s " + "IDX EXPN table of size (%u) or (%f) percent\n", + idx_stats.tot_expn_ents_filled, + mem_type, + idx_stats.tot_expn_ents, + ((float) idx_stats.tot_expn_ents_filled / + (float) idx_stats.tot_expn_ents) * 100.0); + + IPADBG("%s IDX table chains: tot_chains(%u) min_len(%u) max_len(%u) avg_len(%f)\n", + mem_type, + idx_stats.tot_chains, + idx_stats.min_chain_len, + idx_stats.max_chain_len, + idx_stats.avg_chain_len); + } + } + + IPADBG("Out\n"); + + return ret; +} + +/******************************************************************************/ +/* + * FUNCTION: _smSwitchFromSramToDdr + * + * PARAMS: + * + * nati_obj_ptr (IN) A pointer to an initialized nati object + * + * trigger (IN) The trigger to run through the state machine + * + * arb_data_ptr (IN) Whatever you like + * + * DESCRIPTION: + * + * The following will cause a copy of the SRAM table to DDR and then + * will make the IPA use the DDR... + * + * RETURNS: + * + * zero on success, otherwise non-zero + */ +static int _smSwitchFromSramToDdr( + ipa_nati_obj* nati_obj_ptr, + ipa_nati_trigger trigger, + arb_t* arb_data_ptr ) +{ + nati_switch_stats* sw_stats_ptr = CHOOSE_SW_STATS(); + + uint32_t* cnt_ptr = CHOOSE_CNTR(); + + ipa_nati_tbl_stats nat_stats, idx_stats; + + const char* mem_type; + + uint64_t start, stop; + + int stats_ret, ret; + + bool collect_stats = (bool) arb_data_ptr; + + IPADBG("In\n"); + + stats_ret = (collect_stats) ? + ipa_NATI_ipv4_tbl_stats( + nati_obj_ptr->sram_tbl_hdl, &nat_stats, &idx_stats) : + -1; + + currTimeAs(TimeAsNanSecs, &start); + + /* + * First, switch focus to DDR... + */ + ret = ipa_nati_statemach(nati_obj_ptr, NATI_TRIG_GOTO_DDR, 0); + + if ( ret == 0 ) + { + /* + * Clear destination counter... + */ + nati_obj_ptr->tot_rules_in_table[DDR_SUB] = 0; + + /* + * Clear destination DDR maps... + */ + ipa_nat_map_clear(nati_obj.map_pairs[DDR_SUB].orig2new_map); + ipa_nat_map_clear(nati_obj.map_pairs[DDR_SUB].new2orig_map); + + /* + * Now copy SRAM's content to DDR... + */ + ret = ipa_nati_copy_ipv4_tbl( + nati_obj_ptr->sram_tbl_hdl, + nati_obj_ptr->ddr_tbl_hdl, + migrate_rule); + + currTimeAs(TimeAsNanSecs, &stop); + + if ( ret == 0 ) + { + sw_stats_ptr->pass += 1; + + IPADBG("Transistion from SRAM to DDR took %f microseconds\n", + (float) (stop - start) / 1000.0); + } + else + { + sw_stats_ptr->fail += 1; + } + + IPADBG("Transistion pass/fail counts (SRAM to DDR) PASS: %u FAIL: %u\n", + sw_stats_ptr->pass, + sw_stats_ptr->fail); + + if ( stats_ret == 0 ) + { + mem_type = ipa3_nat_mem_in_as_str(nat_stats.nmi); + + /* + * NAT table stats... + */ + IPADBG("Able to add (%u) records to %s " + "NAT table of size (%u) or (%f) percent\n", + *cnt_ptr, + mem_type, + nat_stats.tot_ents, + ((float) *cnt_ptr / (float) nat_stats.tot_ents) * 100.0); + + IPADBG("Able to add (%u) records to %s " + "NAT BASE table of size (%u) or (%f) percent\n", + nat_stats.tot_base_ents_filled, + mem_type, + nat_stats.tot_base_ents, + ((float) nat_stats.tot_base_ents_filled / + (float) nat_stats.tot_base_ents) * 100.0); + + IPADBG("Able to add (%u) records to %s " + "NAT EXPN table of size (%u) or (%f) percent\n", + nat_stats.tot_expn_ents_filled, + mem_type, + nat_stats.tot_expn_ents, + ((float) nat_stats.tot_expn_ents_filled / + (float) nat_stats.tot_expn_ents) * 100.0); + + IPADBG("%s NAT table chains: tot_chains(%u) min_len(%u) max_len(%u) avg_len(%f)\n", + mem_type, + nat_stats.tot_chains, + nat_stats.min_chain_len, + nat_stats.max_chain_len, + nat_stats.avg_chain_len); + + /* + * INDEX table stats... + */ + IPADBG("Able to add (%u) records to %s " + "IDX table of size (%u) or (%f) percent\n", + *cnt_ptr, + mem_type, + idx_stats.tot_ents, + ((float) *cnt_ptr / (float) idx_stats.tot_ents) * 100.0); + + IPADBG("Able to add (%u) records to %s " + "IDX BASE table of size (%u) or (%f) percent\n", + idx_stats.tot_base_ents_filled, + mem_type, + idx_stats.tot_base_ents, + ((float) idx_stats.tot_base_ents_filled / + (float) idx_stats.tot_base_ents) * 100.0); + + IPADBG("Able to add (%u) records to %s " + "IDX EXPN table of size (%u) or (%f) percent\n", + idx_stats.tot_expn_ents_filled, + mem_type, + idx_stats.tot_expn_ents, + ((float) idx_stats.tot_expn_ents_filled / + (float) idx_stats.tot_expn_ents) * 100.0); + + IPADBG("%s IDX table chains: tot_chains(%u) min_len(%u) max_len(%u) avg_len(%f)\n", + mem_type, + idx_stats.tot_chains, + idx_stats.min_chain_len, + idx_stats.max_chain_len, + idx_stats.avg_chain_len); + } + } + + IPADBG("Out\n"); + + return ret; +} + +/******************************************************************************/ +/* + * FUNCTION: _smGetTmStmp + * + * PARAMS: + * + * nati_obj_ptr (IN) A pointer to an initialized nati object + * + * trigger (IN) The trigger to run through the state machine + * + * arb_data_ptr (IN) Whatever you like + * + * DESCRIPTION: + * + * Retrieve rule's timestamp from NAT table. + * + * RETURNS: + * + * zero on success, otherwise non-zero + */ +static int _smGetTmStmp( + ipa_nati_obj* nati_obj_ptr, + ipa_nati_trigger trigger, + arb_t* arb_data_ptr ) +{ + arb_t** args = arb_data_ptr; + + uint32_t tbl_hdl = (uint32_t) args[0]; + uint32_t rule_hdl = (uint32_t) args[1]; + uint32_t* time_stamp = (uint32_t*) args[2]; + + int ret; + + IPADBG("In\n"); + + IPADBG("tbl_hdl(0x%08X) rule_hdl(%u) time_stamp_ptr(%p)\n", + tbl_hdl, rule_hdl, time_stamp); + + ret = ipa_NATI_query_timestamp(tbl_hdl, rule_hdl, time_stamp); + + if ( ret == 0 ) + { + IPADBG("time_stamp(0x%08X)\n", *time_stamp); + } + + IPADBG("Out\n"); + + return ret; +} + +/******************************************************************************/ +/* + * FUNCTION: _smGetTmStmpHybrid + * + * PARAMS: + * + * nati_obj_ptr (IN) A pointer to an initialized nati object + * + * trigger (IN) The trigger to run through the state machine + * + * arb_data_ptr (IN) Whatever you like + * + * DESCRIPTION: + * + * Retrieve rule's timestamp from the state approriate NAT table. + * + * RETURNS: + * + * zero on success, otherwise non-zero + */ +static int _smGetTmStmpHybrid( + ipa_nati_obj* nati_obj_ptr, + ipa_nati_trigger trigger, + arb_t* arb_data_ptr ) +{ + arb_t** args = arb_data_ptr; + + uint32_t tbl_hdl = (uint32_t) args[0]; + uint32_t orig_rule_hdl = (uint32_t) args[1]; + uint32_t* time_stamp = (uint32_t*) args[2]; + + uint32_t new_rule_hdl; + + uint32_t orig2new_map, new2orig_map; + + int ret; + + IPADBG("In\n"); + + CHOOSE_MAPS(orig2new_map, new2orig_map); + + ret = ipa_nat_map_find(orig2new_map, orig_rule_hdl, &new_rule_hdl); + + if ( ret == 0 ) + { + arb_t* new_args[] = { + (arb_t*)(arb_t)(nati_obj_ptr->curr_state == NATI_STATE_HYBRID) ? + tbl_hdl : + nati_obj_ptr->ddr_tbl_hdl, + (arb_t*)(arb_t)new_rule_hdl, + (arb_t*) time_stamp, + }; + + ret = _smGetTmStmp(nati_obj_ptr, trigger, new_args); + } + + IPADBG("Out\n"); + + return ret; +} + +/******************************************************************************/ +/* + * The following table relates a nati object's state and a transition + * trigger to a callback... + */ +static nati_statemach_tuple +_state_mach_tbl[NATI_STATE_LAST+1][NATI_TRIG_LAST+1] = +{ + { + SM_ROW( NATI_STATE_NULL, NATI_TRIG_NULL, _smUndef ), + SM_ROW( NATI_STATE_NULL, NATI_TRIG_ADD_TABLE, _smFirstTbl ), + SM_ROW( NATI_STATE_NULL, NATI_TRIG_DEL_TABLE, _smUndef ), + SM_ROW( NATI_STATE_NULL, NATI_TRIG_CLR_TABLE, _smUndef ), + SM_ROW( NATI_STATE_NULL, NATI_TRIG_WLK_TABLE, _smUndef ), + SM_ROW( NATI_STATE_NULL, NATI_TRIG_TBL_STATS, _smUndef ), + SM_ROW( NATI_STATE_NULL, NATI_TRIG_ADD_RULE, _smUndef ), + SM_ROW( NATI_STATE_NULL, NATI_TRIG_DEL_RULE, _smUndef ), + SM_ROW( NATI_STATE_NULL, NATI_TRIG_TBL_SWITCH, _smUndef ), + SM_ROW( NATI_STATE_NULL, NATI_TRIG_GOTO_DDR, _smUndef ), + SM_ROW( NATI_STATE_NULL, NATI_TRIG_GOTO_SRAM, _smUndef ), + SM_ROW( NATI_STATE_NULL, NATI_TRIG_GET_TSTAMP, _smUndef ), + SM_ROW( NATI_STATE_NULL, NATI_TRIG_LAST, _smUndef ), + }, + + { + SM_ROW( NATI_STATE_DDR_ONLY, NATI_TRIG_NULL, _smUndef ), + SM_ROW( NATI_STATE_DDR_ONLY, NATI_TRIG_ADD_TABLE, _smAddDdrTbl ), + SM_ROW( NATI_STATE_DDR_ONLY, NATI_TRIG_DEL_TABLE, _smDelTbl ), + SM_ROW( NATI_STATE_DDR_ONLY, NATI_TRIG_CLR_TABLE, _smClrTbl ), + SM_ROW( NATI_STATE_DDR_ONLY, NATI_TRIG_WLK_TABLE, _smWalkTbl ), + SM_ROW( NATI_STATE_DDR_ONLY, NATI_TRIG_TBL_STATS, _smStatTbl ), + SM_ROW( NATI_STATE_DDR_ONLY, NATI_TRIG_ADD_RULE, _smAddRuleToTbl ), + SM_ROW( NATI_STATE_DDR_ONLY, NATI_TRIG_DEL_RULE, _smDelRuleFromTbl ), + SM_ROW( NATI_STATE_DDR_ONLY, NATI_TRIG_TBL_SWITCH, _smUndef ), + SM_ROW( NATI_STATE_DDR_ONLY, NATI_TRIG_GOTO_DDR, _smUndef ), + SM_ROW( NATI_STATE_DDR_ONLY, NATI_TRIG_GOTO_SRAM, _smUndef ), + SM_ROW( NATI_STATE_DDR_ONLY, NATI_TRIG_GET_TSTAMP, _smGetTmStmp ), + SM_ROW( NATI_STATE_DDR_ONLY, NATI_TRIG_LAST, _smUndef ), + }, + + { + SM_ROW( NATI_STATE_SRAM_ONLY, NATI_TRIG_NULL, _smUndef ), + SM_ROW( NATI_STATE_SRAM_ONLY, NATI_TRIG_ADD_TABLE, _smAddSramTbl ), + SM_ROW( NATI_STATE_SRAM_ONLY, NATI_TRIG_DEL_TABLE, _smDelTbl ), + SM_ROW( NATI_STATE_SRAM_ONLY, NATI_TRIG_CLR_TABLE, _smClrTbl ), + SM_ROW( NATI_STATE_SRAM_ONLY, NATI_TRIG_WLK_TABLE, _smWalkTbl ), + SM_ROW( NATI_STATE_SRAM_ONLY, NATI_TRIG_TBL_STATS, _smStatTbl ), + SM_ROW( NATI_STATE_SRAM_ONLY, NATI_TRIG_ADD_RULE, _smAddRuleToTbl ), + SM_ROW( NATI_STATE_SRAM_ONLY, NATI_TRIG_DEL_RULE, _smDelRuleFromTbl ), + SM_ROW( NATI_STATE_SRAM_ONLY, NATI_TRIG_TBL_SWITCH, _smUndef ), + SM_ROW( NATI_STATE_SRAM_ONLY, NATI_TRIG_GOTO_DDR, _smUndef ), + SM_ROW( NATI_STATE_SRAM_ONLY, NATI_TRIG_GOTO_SRAM, _smUndef ), + SM_ROW( NATI_STATE_SRAM_ONLY, NATI_TRIG_GET_TSTAMP, _smGetTmStmp ), + SM_ROW( NATI_STATE_SRAM_ONLY, NATI_TRIG_LAST, _smUndef ), + }, + + { + SM_ROW( NATI_STATE_HYBRID, NATI_TRIG_NULL, _smUndef ), + SM_ROW( NATI_STATE_HYBRID, NATI_TRIG_ADD_TABLE, _smAddSramAndDdrTbl ), + SM_ROW( NATI_STATE_HYBRID, NATI_TRIG_DEL_TABLE, _smDelSramAndDdrTbl ), + SM_ROW( NATI_STATE_HYBRID, NATI_TRIG_CLR_TABLE, _smClrTblHybrid ), + SM_ROW( NATI_STATE_HYBRID, NATI_TRIG_WLK_TABLE, _smWalkTblHybrid ), + SM_ROW( NATI_STATE_HYBRID, NATI_TRIG_TBL_STATS, _smStatTblHybrid ), + SM_ROW( NATI_STATE_HYBRID, NATI_TRIG_ADD_RULE, _smAddRuleHybrid ), + SM_ROW( NATI_STATE_HYBRID, NATI_TRIG_DEL_RULE, _smDelRuleHybrid ), + SM_ROW( NATI_STATE_HYBRID, NATI_TRIG_TBL_SWITCH, _smSwitchFromSramToDdr ), + SM_ROW( NATI_STATE_HYBRID, NATI_TRIG_GOTO_DDR, _smGoToDdr ), + SM_ROW( NATI_STATE_HYBRID, NATI_TRIG_GOTO_SRAM, _smGoToSram ), + SM_ROW( NATI_STATE_HYBRID, NATI_TRIG_GET_TSTAMP, _smGetTmStmpHybrid ), + SM_ROW( NATI_STATE_HYBRID, NATI_TRIG_LAST, _smUndef ), + }, + + { + SM_ROW( NATI_STATE_HYBRID_DDR, NATI_TRIG_NULL, _smUndef ), + SM_ROW( NATI_STATE_HYBRID_DDR, NATI_TRIG_ADD_TABLE, _smUndef ), + SM_ROW( NATI_STATE_HYBRID_DDR, NATI_TRIG_DEL_TABLE, _smDelSramAndDdrTbl ), + SM_ROW( NATI_STATE_HYBRID_DDR, NATI_TRIG_CLR_TABLE, _smClrTblHybrid ), + SM_ROW( NATI_STATE_HYBRID_DDR, NATI_TRIG_WLK_TABLE, _smWalkTblHybrid ), + SM_ROW( NATI_STATE_HYBRID_DDR, NATI_TRIG_TBL_STATS, _smStatTblHybrid ), + SM_ROW( NATI_STATE_HYBRID_DDR, NATI_TRIG_ADD_RULE, _smAddRuleHybrid ), + SM_ROW( NATI_STATE_HYBRID_DDR, NATI_TRIG_DEL_RULE, _smDelRuleHybrid ), + SM_ROW( NATI_STATE_HYBRID_DDR, NATI_TRIG_TBL_SWITCH, _smSwitchFromDdrToSram ), + SM_ROW( NATI_STATE_HYBRID_DDR, NATI_TRIG_GOTO_DDR, _smGoToDdr ), + SM_ROW( NATI_STATE_HYBRID_DDR, NATI_TRIG_GOTO_SRAM, _smGoToSram ), + SM_ROW( NATI_STATE_HYBRID_DDR, NATI_TRIG_GET_TSTAMP, _smGetTmStmpHybrid ), + SM_ROW( NATI_STATE_HYBRID_DDR, NATI_TRIG_LAST, _smUndef ), + }, + + { + SM_ROW( NATI_STATE_LAST, NATI_TRIG_NULL, _smUndef ), + SM_ROW( NATI_STATE_LAST, NATI_TRIG_ADD_TABLE, _smUndef ), + SM_ROW( NATI_STATE_LAST, NATI_TRIG_DEL_TABLE, _smUndef ), + SM_ROW( NATI_STATE_LAST, NATI_TRIG_CLR_TABLE, _smUndef ), + SM_ROW( NATI_STATE_LAST, NATI_TRIG_WLK_TABLE, _smUndef ), + SM_ROW( NATI_STATE_LAST, NATI_TRIG_TBL_STATS, _smUndef ), + SM_ROW( NATI_STATE_LAST, NATI_TRIG_ADD_RULE, _smUndef ), + SM_ROW( NATI_STATE_LAST, NATI_TRIG_DEL_RULE, _smUndef ), + SM_ROW( NATI_STATE_LAST, NATI_TRIG_TBL_SWITCH, _smUndef ), + SM_ROW( NATI_STATE_LAST, NATI_TRIG_GOTO_DDR, _smUndef ), + SM_ROW( NATI_STATE_LAST, NATI_TRIG_GOTO_SRAM, _smUndef ), + SM_ROW( NATI_STATE_LAST, NATI_TRIG_GET_TSTAMP, _smUndef ), + SM_ROW( NATI_STATE_LAST, NATI_TRIG_LAST, _smUndef ), + }, +}; + +/******************************************************************************/ +/* + * FUNCTION: _smUndef + * + * PARAMS: + * + * nati_obj_ptr (IN) A pointer to an initialized nati object + * + * trigger (IN) The trigger to run through the state machine + * + * arb_data_ptr (IN) Whatever you like + * + * DESCRIPTION: + * + * The following does nothing, except report an undefined action for + * a particular state/trigger combo... + * + * RETURNS: + * + * zero on success, otherwise non-zero + */ +static int _smUndef( + ipa_nati_obj* nati_obj_ptr, + ipa_nati_trigger trigger, + arb_t* arb_data_ptr ) +{ + IPAERR("CB(%s): undefined action for STATE(%s) with TRIGGER(%s)\n", + _state_mach_tbl[nati_obj_ptr->curr_state][trigger].sm_cb_as_str, + _state_mach_tbl[nati_obj_ptr->curr_state][trigger].state_as_str, + _state_mach_tbl[nati_obj_ptr->curr_state][trigger].trigger_as_str); + + return -1; +} + +/******************************************************************************/ +/* + * FUNCTION: ipa_nati_statemach + * + * PARAMS: + * + * nati_obj_ptr (IN) A pointer to an initialized nati object + * + * trigger (IN) The trigger to run through the state machine + * + * arb_data_ptr (IN) Anything you like. Will be passed, untouched, + * to the state/trigger callback function. + * + * DESCRIPTION: + * + * This function allows a nati object and a trigger to be run + * through the state machine. + * + * RETURNS: + * + * zero on success, otherwise non-zero + */ +int ipa_nati_statemach( + ipa_nati_obj* nati_obj_ptr, + ipa_nati_trigger trigger, + arb_t* arb_data_ptr ) +{ + const char* ss_ptr = _state_mach_tbl[nati_obj_ptr->curr_state][trigger].state_as_str; + const char* ts_ptr = _state_mach_tbl[nati_obj_ptr->curr_state][trigger].trigger_as_str; + const char* cbs_ptr = _state_mach_tbl[nati_obj_ptr->curr_state][trigger].sm_cb_as_str; + + bool vote = false; + + int ret; + + IPADBG("In\n"); + + ret = take_mutex(); + + if ( ret != 0 ) + { + goto bail; + } + + IPADBG("STATE(%s) TRIGGER(%s) CB(%s)\n", ss_ptr, ts_ptr, cbs_ptr); + + vote = VOTE_REQUIRED(trigger); + + if ( vote ) + { + IPADBG("Voting clock on STATE(%s) TRIGGER(%s)\n", + ss_ptr, ts_ptr); + + if ( ipa_nat_vote_clock(IPA_APP_CLK_VOTE) != 0 ) + { + IPAERR("Voting failed STATE(%s) TRIGGER(%s)\n", ss_ptr, ts_ptr); + ret = -EINVAL; + goto unlock; + } + } + + ret = _state_mach_tbl[nati_obj_ptr->curr_state][trigger].sm_cb( + nati_obj_ptr, trigger, arb_data_ptr); + + if ( vote ) + { + IPADBG("Voting clock off STATE(%s) TRIGGER(%s)\n", + ss_ptr, ts_ptr); + + if ( ipa_nat_vote_clock(IPA_APP_CLK_DEVOTE) != 0 ) + { + IPAERR("Voting failed STATE(%s) TRIGGER(%s)\n", ss_ptr, ts_ptr); + } + } + +unlock: + ret = give_mutex(); + +bail: + IPADBG("Out\n"); + + return ret; +} diff --git a/qcom/opensource/dataipa/ipanat/src/ipa_nat_utils.c b/qcom/opensource/dataipa/ipanat/src/ipa_nat_utils.c new file mode 100644 index 0000000000..a8fdff6861 --- /dev/null +++ b/qcom/opensource/dataipa/ipanat/src/ipa_nat_utils.c @@ -0,0 +1,215 @@ +/* + * Copyright (c) 2013, 2018-2019 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "ipa_nat_utils.h" +#include +#include +#include +#include +#include + +#define IPA_MAX_MSG_LEN 4096 + +static char dbg_buff[IPA_MAX_MSG_LEN]; + +#if !defined(MSM_IPA_TESTS) && !defined(USE_GLIB) && !defined(FEATURE_IPA_ANDROID) +size_t strlcpy(char* dst, const char* src, size_t size) +{ + size_t i; + + if (size == 0) + return strlen(src); + + for (i = 0; i < (size - 1) && src[i] != '\0'; ++i) + dst[i] = src[i]; + + dst[i] = '\0'; + + return i + strlen(src + i); +} +#endif + +ipa_descriptor* ipa_descriptor_open(void) +{ + ipa_descriptor* desc_ptr; + int res = 0; + + IPADBG("In\n"); + + desc_ptr = calloc(1, sizeof(ipa_descriptor)); + + if ( desc_ptr == NULL ) + { + IPAERR("Unable to allocate ipa_descriptor\n"); + goto bail; + } + + desc_ptr->fd = open(IPA_DEV_NAME, O_RDONLY); + + if (desc_ptr->fd < 0) + { + IPAERR("Unable to open ipa device\n"); + goto free; + } + + res = ioctl(desc_ptr->fd, IPA_IOC_GET_HW_VERSION, &desc_ptr->ver); + + if (res == 0) + { + IPADBG("IPA version is %d\n", desc_ptr->ver); + } + else + { + IPAERR("Unable to get IPA version. Error %d\n", res); + desc_ptr->ver = IPA_HW_None; + } + + goto bail; + +free: + free(desc_ptr); + desc_ptr = NULL; + +bail: + IPADBG("Out\n"); + + return desc_ptr; +} + +void ipa_descriptor_close( + ipa_descriptor* desc_ptr) +{ + IPADBG("In\n"); + + if ( desc_ptr ) + { + if ( desc_ptr->fd >= 0) + { + close(desc_ptr->fd); + } + free(desc_ptr); + } + + IPADBG("Out\n"); +} + +void ipa_read_debug_info( + const char* debug_file_path) +{ + size_t result; + FILE* debug_file; + + debug_file = fopen(debug_file_path, "r"); + if (debug_file == NULL) + { + printf("Failed to open %s\n", debug_file_path); + return; + } + + for (;;) + { + result = fread(dbg_buff, sizeof(char), IPA_MAX_MSG_LEN, debug_file); + if (!result) + break; + + if (result < IPA_MAX_MSG_LEN) + { + if (ferror(debug_file)) + { + printf("Failed to read from %s\n", debug_file_path); + break; + } + + dbg_buff[result] = '\0'; + } + else + { + dbg_buff[IPA_MAX_MSG_LEN - 1] = '\0'; + } + + + printf("%s", dbg_buff); + + if (feof(debug_file)) + break; + } + fclose(debug_file); +} + +void log_nat_message(char *msg) +{ + return; +} + +int currTimeAs( + TimeAs_t timeAs, + uint64_t* valPtr ) +{ + struct timespec timeSpec; + + int ret = 0; + + if ( ! VALID_TIMEAS(timeAs) || ! valPtr ) + { + IPAERR("Bad arg: timeAs (%u) and/or valPtr (%p)\n", + timeAs, valPtr ); + ret = -1; + goto bail; + } + + memset(&timeSpec, 0, sizeof(timeSpec)); + + if ( clock_gettime(CLOCK_MONOTONIC, &timeSpec) != 0 ) + { + IPAERR("Can't get system clock time\n" ); + ret = -1; + goto bail; + } + + switch( timeAs ) + { + case TimeAsNanSecs: + *valPtr = + (uint64_t) (SECS2NanSECS((uint64_t) timeSpec.tv_sec) + + ((uint64_t) timeSpec.tv_nsec)); + break; + case TimeAsMicSecs: + *valPtr = + (uint64_t) (SECS2MicSECS((uint64_t) timeSpec.tv_sec) + + ((uint64_t) timeSpec.tv_nsec / 1000)); + break; + case TimeAsMilSecs: + *valPtr = + (uint64_t) (SECS2MilSECS((uint64_t) timeSpec.tv_sec) + + ((uint64_t) timeSpec.tv_nsec / 1000000)); + break; + } + +bail: + return ret; +} diff --git a/qcom/opensource/dataipa/ipanat/src/ipa_table.c b/qcom/opensource/dataipa/ipanat/src/ipa_table.c new file mode 100644 index 0000000000..0d415b7d32 --- /dev/null +++ b/qcom/opensource/dataipa/ipanat/src/ipa_table.c @@ -0,0 +1,1333 @@ +/* + * Copyright (c) 2018-2020 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "ipa_table.h" +#include "ipa_nat_utils.h" + +#include + +#define IPA_BASE_TABLE_PERCENTAGE .8 +#define IPA_EXPANSION_TABLE_PERCENTAGE .2 + +#define IPA_BASE_TABLE_PCNT_4SRAM 1.00 +#define IPA_EXPANSION_TABLE_PCNT_4SRAM 0.43 + +/* + * The table number of entries is limited by Entry ID structure + * above. The base table max entries is limited by index into table + * bits number. + * + * The table max ents number is: (base table max ents / base table percentage) + * + * IPA_TABLE_MAX_ENTRIES = 2^(index into table) / IPA_BASE_TABLE_PERCENTAGE + */ + +static int InsertHead( + ipa_table* table, + void* rec_ptr, /* empty record in table */ + uint16_t rec_index, /* index of record above */ + void* user_data, + struct ipa_ioc_nat_dma_cmd* cmd ); + +static int InsertTail( + ipa_table* table, + void* rec_ptr, /* occupied record at index below */ + uint16_t* rec_index_ptr, /* pointer to index of record above */ + void* user_data, + struct ipa_ioc_nat_dma_cmd* cmd ); + +static uint16_t MakeEntryHdl( + ipa_table* tbl, + uint16_t tbl_entry ); + +static int FindExpnTblFreeEntry( + ipa_table* table, + void** free_entry, + uint16_t* entry_index ); + +static int Get2PowerTightUpperBound( + uint16_t num); + +static int GetEvenTightUpperBound( + uint16_t num); + +void ipa_table_init( + ipa_table* table, + const char* table_name, + enum ipa3_nat_mem_in nmi, + int entry_size, + void* meta, + int meta_entry_size, + ipa_table_entry_interface* entry_interface ) +{ + IPADBG("In\n"); + + memset(table, 0, sizeof(ipa_table)); + + strlcpy(table->name, table_name, IPA_RESOURCE_NAME_MAX); + + table->nmi = nmi; + table->entry_size = entry_size; + table->meta = meta; + table->meta_entry_size = meta_entry_size; + table->entry_interface = entry_interface; + + IPADBG("Table %s with entry size %d has been initialized\n", + table->name, table->entry_size); + + IPADBG("Out\n"); +} + +int ipa_table_calculate_entries_num( + ipa_table* table, + uint16_t number_of_entries, + enum ipa3_nat_mem_in nmi) +{ + uint16_t table_entries, expn_table_entries; + float btp, etp; + int result = 0; + + IPADBG("In\n"); + + if (number_of_entries > IPA_TABLE_MAX_ENTRIES) + { + IPAERR("Required number of %s entries %d exceeds the maximum %d\n", + table->name, number_of_entries, IPA_TABLE_MAX_ENTRIES); + result = -EINVAL; + goto bail; + } + + if ( nmi == IPA_NAT_MEM_IN_SRAM ) + { + btp = IPA_BASE_TABLE_PCNT_4SRAM; + etp = IPA_EXPANSION_TABLE_PCNT_4SRAM; + } + else + { + btp = IPA_BASE_TABLE_PERCENTAGE; + etp = IPA_EXPANSION_TABLE_PERCENTAGE; + } + + table_entries = Get2PowerTightUpperBound(number_of_entries * btp); + expn_table_entries = GetEvenTightUpperBound(number_of_entries * etp); + + table->tot_tbl_ents = table_entries + expn_table_entries; + + if ( table->tot_tbl_ents > IPA_TABLE_MAX_ENTRIES ) + { + IPAERR("Required number of %s entries %u " + "(user provided %u) exceeds the maximum %u\n", + table->name, + table->tot_tbl_ents, + number_of_entries, + IPA_TABLE_MAX_ENTRIES); + result = -EINVAL; + goto bail; + } + + table->table_entries = table_entries; + table->expn_table_entries = expn_table_entries; + + IPADBG("Num of %s entries:%u expn entries:%u total entries:%u\n", + table->name, + table->table_entries, + table->expn_table_entries, + table->tot_tbl_ents); + +bail: + IPADBG("Out\n"); + + return result; +} + +int ipa_table_calculate_size(ipa_table* table) +{ + int size = table->entry_size * (table->table_entries + table->expn_table_entries); + + IPADBG("In\n"); + + IPADBG("%s size: %d\n", table->name, size); + + IPADBG("Out\n"); + + return size; +} + +uint8_t* ipa_table_calculate_addresses( + ipa_table* table, + uint8_t* base_addr) +{ + uint8_t* result = NULL; + + IPADBG("In\n"); + + table->table_addr = base_addr; + table->expn_table_addr = + table->table_addr + table->entry_size * table->table_entries; + + IPADBG("Table %s addresses: table_addr %pK expn_table_addr %pK\n", + table->name, table->table_addr, table->expn_table_addr); + + result = table->expn_table_addr + table->entry_size * table->expn_table_entries; + + IPADBG("Out\n"); + + return result; +} + +void ipa_table_reset( + ipa_table* table) +{ + uint32_t i,tot; + + IPADBG("In\n"); + + IPADBG("memset %s table to 0, %pK\n", table->name, table->table_addr); + tot = table->entry_size * table->table_entries; + for (i = 0; i < tot; i++) + table->table_addr[i] = '\0'; + + IPADBG("memset %s expn table to 0, %pK\n", table->name, table->expn_table_addr); + tot = table->entry_size * table->expn_table_entries; + for (i = 0; i < tot; i++) + table->expn_table_addr[i] = '\0'; + + IPADBG("Out\n"); +} + +int ipa_table_add_entry( + ipa_table* table, + void* user_data, + uint16_t* rec_index_ptr, + uint32_t* rule_hdl, + struct ipa_ioc_nat_dma_cmd* cmd ) +{ + void* rec_ptr; + int ret = 0, occupied; + + IPADBG("In\n"); + + rec_ptr = GOTO_REC(table, *rec_index_ptr); + + /* + * Check whether there is any collision + */ + occupied = table->entry_interface->entry_is_valid(rec_ptr); + + if ( ! occupied ) + { + IPADBG("Collision free (in %s) ... found open slot\n", table->name); + ret = InsertHead(table, rec_ptr, *rec_index_ptr, user_data, cmd); + } + else + { + IPADBG("Collision (in %s) ... will probe for open slot\n", table->name); + ret = InsertTail(table, rec_ptr, rec_index_ptr, user_data, cmd); + } + + if (ret) + goto bail; + + IPADBG("New Entry Index %u in %s\n", *rec_index_ptr, table->name); + + if ( rule_hdl ) { + *rule_hdl = MakeEntryHdl(table, *rec_index_ptr); + IPADBG("rule_hdl value(%u)\n", *rule_hdl); + } + +bail: + IPADBG("Out\n"); + + return ret; +} + +void ipa_table_create_delete_command( + ipa_table* table, + struct ipa_ioc_nat_dma_cmd* cmd, + ipa_table_iterator* iterator) +{ + IPADBG("In\n"); + + IPADBG("Delete rule at index(0x%04X) in %s\n", + iterator->curr_index, + table->name); + + if ( ! VALID_INDEX(iterator->prev_index) ) + { + /* + * The following two assigns (ie. the defaults), will cause + * the enabled bit in the record to be set to 0. + */ + uint16_t data = 0; + dma_help_type ht = HELP_UPDATE_HEAD; + + if ( VALID_INDEX(iterator->next_index) ) + { + /* + * NOTE WELL HERE: + * + * This record is the first in a chain/list of + * records. Delete means something different in this + * context. + * + * The code below will cause the change of the protocol + * field in the rule record to 0xFF. It does not set the + * enable bit in the record to 0. This is done in special + * cases when the record being deleted is the first in a + * list of records. + * + * What does this mean? It means that the record is + * functionally deleted, but not really deleted. Why? + * Because the IPA will no longer use it because of the + * bad protocol (ie. functionally deleted), but these + * higher level APIs still see it as "enabled." + * + * This all means that deleted really means two things: 1) + * Not enabled, and 2) Not a valid record. APIs that walk + * the table...looking for enabled records (ie. the + * enabled bit)....now have to be a bit smarter to see the + * bad protocol as well. + */ + data = table->entry_interface-> + entry_get_delete_head_dma_command_data( + iterator->curr_entry, iterator->next_entry); + + ht = HELP_DELETE_HEAD; + } + + ipa_table_add_dma_cmd(table, + ht, + iterator->curr_entry, + iterator->curr_index, + data, + cmd); + } + else + { + ipa_table_add_dma_cmd(table, + HELP_UPDATE_ENTRY, + iterator->prev_entry, + iterator->prev_index, + iterator->next_index, + cmd); + } + + IPADBG("Out\n"); +} + +void ipa_table_delete_entry( + ipa_table* table, + ipa_table_iterator* iterator, + uint8_t is_prev_empty) +{ + IPADBG("In\n"); + + if ( VALID_INDEX(iterator->next_index) ) + { + /* + * Update the next entry's prev_index field with current + * entry's prev_index + */ + table->entry_interface->entry_set_prev_index( + iterator->next_entry, + iterator->next_index, + iterator->prev_index, + table->meta, + table->table_entries); + } + else if (is_prev_empty) + { + if (iterator->prev_entry == NULL) + { + IPAERR("failed to delete of an empty head %d while delete the next entry %d in %s", + iterator->prev_index, iterator->curr_index, table->name); + } + else + { + /* + * Delete an empty head rule after the whole tail was deleted + */ + IPADBG("deleting the dead node %d for %s\n", + iterator->prev_index, table->name); + + memset(iterator->prev_entry, 0, table->entry_size); + + --table->cur_tbl_cnt; + } + } + + ipa_table_erase_entry(table, iterator->curr_index); + + IPADBG("Out\n"); +} + +void ipa_table_erase_entry( + ipa_table* table, + uint16_t index) +{ + void* entry = GOTO_REC(table, index); + + IPADBG("In\n"); + + IPADBG("table(%p) index(%u)\n", table, index); + + memset(entry, 0, table->entry_size); + + if ( index < table->table_entries ) + { + --table->cur_tbl_cnt; + } + else + { + --table->cur_expn_tbl_cnt; + } + + IPADBG("Out\n"); +} + +/** + * ipa_table_get_entry() - returns a table entry according to the received entry handle + * @table: [in] the table + * @entry_handle: [in] entry handle + * @entry: [out] the retrieved entry + * @entry_index: [out] absolute index of the retrieved entry + * + * Parse the entry handle to retrieve the entry and its index + * + * Returns: 0 on success, negative on failure + */ +int ipa_table_get_entry( + ipa_table* table, + uint32_t entry_handle, + void** entry, + uint16_t* entry_index ) +{ + enum ipa3_nat_mem_in nmi; + uint8_t is_expn_tbl; + uint16_t rec_index; + + int ret = 0; + + IPADBG("In\n"); + + IPADBG("table(%p) entry_handle(%u) entry(%p) entry_index(%p)\n", + table, entry_handle, entry, entry_index); + + /* + * Retrieve the memory and table type as well as the index + */ + BREAK_RULE_HDL(table, entry_handle, nmi, is_expn_tbl, rec_index); + + if ( is_expn_tbl ) + { + IPADBG("Retrieving entry from expansion table\n"); + } + else + { + IPADBG("Retrieving entry from base (non-expansion) table\n"); + } + + if ( rec_index >= table->tot_tbl_ents ) + { + IPAERR("The entry handle's record index (%u) exceeds table size (%u)\n", + rec_index, table->tot_tbl_ents); + ret = -EINVAL; + goto bail; + } + + *entry = GOTO_REC(table, rec_index); + + if ( entry_index ) + { + *entry_index = rec_index; + } + +bail: + IPADBG("Out\n"); + + return ret; +} + +void* ipa_table_get_entry_by_index( + ipa_table* table, + uint16_t rec_index ) +{ + void* result = NULL; + + IPADBG("In\n"); + + IPADBG("table(%p) rec_index(%u)\n", + table, + rec_index); + + if ( ! rec_index || rec_index >= table->tot_tbl_ents ) + { + IPAERR("Invalid record index (%u): It's " + "either zero or exceeds table size (%u)\n", + rec_index, table->tot_tbl_ents); + goto bail; + } + + result = GOTO_REC(table, rec_index); + +bail: + IPADBG("Out\n"); + + return result; +} + +void ipa_table_dma_cmd_helper_init( + ipa_table_dma_cmd_helper* dma_cmd_helper, + uint8_t table_indx, + ipa_table_dma_type table_type, + ipa_table_dma_type expn_table_type, + uint32_t offset) +{ + IPADBG("In\n"); + + dma_cmd_helper->offset = offset; + dma_cmd_helper->table_indx = table_indx; + dma_cmd_helper->table_type = table_type; + dma_cmd_helper->expn_table_type = expn_table_type; + + IPADBG("Out\n"); +} + +void ipa_table_dma_cmd_generate( + ipa_table_dma_cmd_helper* dma_cmd_helper, + uint8_t is_expn, + uint32_t entry_offset, + uint16_t data, + struct ipa_ioc_nat_dma_cmd* cmd) +{ + struct ipa_ioc_nat_dma_one* dma = &cmd->dma[cmd->entries]; + + IPADBG("In\n"); + + IPADBG("is_expn(0x%02X) entry_offset(0x%08X) data(0x%04X)\n", + is_expn, entry_offset, data); + + dma->table_index = dma_cmd_helper->table_indx; + + /* + * DMA parameter base_addr is the table type (see the IPA + * architecture document) + */ + dma->base_addr = + (is_expn) ? + dma_cmd_helper->expn_table_type : + dma_cmd_helper->table_type; + + dma->offset = dma_cmd_helper->offset + entry_offset; + + dma->data = data; + + IPADBG("dma_entry[%u](table_index(0x%02X) " + "base_addr(0x%02X) data(0x%04X) offset(0x%08X))\n", + cmd->entries, + dma->table_index, + dma->base_addr, + dma->data, + dma->offset); + + cmd->entries++; + + IPADBG("Out\n"); +} + +int ipa_table_iterator_init( + ipa_table_iterator* iterator, + ipa_table* table, + void* curr_entry, + uint16_t curr_index) +{ + int occupied; + + int ret = 0; + + IPADBG("In\n"); + + memset(iterator, 0, sizeof(ipa_table_iterator)); + + occupied = table->entry_interface->entry_is_valid(curr_entry); + + if ( ! occupied ) + { + IPAERR("Invalid (not enabled) rule %u in %s\n", curr_index, table->name); + ret = -EINVAL; + goto bail; + } + + iterator->curr_entry = curr_entry; + iterator->curr_index = curr_index; + + iterator->prev_index = table->entry_interface->entry_get_prev_index( + curr_entry, + curr_index, + table->meta, + table->table_entries); + + iterator->next_index = table->entry_interface->entry_get_next_index( + curr_entry); + + if ( VALID_INDEX(iterator->prev_index) ) + { + iterator->prev_entry = ipa_table_get_entry_by_index( + table, + iterator->prev_index); + + if ( iterator->prev_entry == NULL ) + { + IPAERR("Failed to retrieve the entry at index 0x%04X for %s\n", + iterator->prev_index, table->name); + ret = -EPERM; + goto bail; + } + } + + if ( VALID_INDEX(iterator->next_index) ) + { + iterator->next_entry = ipa_table_get_entry_by_index( + table, + iterator->next_index); + + if ( iterator->next_entry == NULL ) + { + IPAERR("Failed to retrieve the entry at index 0x%04X for %s\n", + iterator->next_index, table->name); + ret = -EPERM; + goto bail; + } + } + + IPADBG("[index/entry] for " + "prev:[0x%04X/%p] " + "curr:[0x%04X/%p] " + "next:[0x%04X/%p] " + "\"%s\"\n", + iterator->prev_index, + iterator->prev_entry, + iterator->curr_index, + iterator->curr_entry, + iterator->next_index, + iterator->next_entry, + table->name); + +bail: + IPADBG("Out\n"); + + return ret; +} + +int ipa_table_iterator_next( + ipa_table_iterator* iterator, + ipa_table* table) +{ + int ret = 0; + + IPADBG("In\n"); + + iterator->prev_entry = iterator->curr_entry; + iterator->prev_index = iterator->curr_index; + iterator->curr_entry = iterator->next_entry; + iterator->curr_index = iterator->next_index; + + iterator->next_index = table->entry_interface->entry_get_next_index( + iterator->curr_entry); + + if ( ! VALID_INDEX(iterator->next_index) ) + { + iterator->next_entry = NULL; + } + else + { + iterator->next_entry = ipa_table_get_entry_by_index( + table, iterator->next_index); + + if (iterator->next_entry == NULL) + { + IPAERR("Failed to retrieve the entry at index %d for %s\n", + iterator->next_index, table->name); + ret = -EPERM; + goto bail; + } + } + + IPADBG("Iterator moved to: prev_index=%d curr_index=%d next_index=%d\n", + iterator->prev_index, iterator->curr_index, iterator->next_index); + + IPADBG(" prev_entry=%pK curr_entry=%pK next_entry=%pK\n", + iterator->prev_entry, iterator->curr_entry, iterator->next_entry); + +bail: + IPADBG("Out\n"); + + return ret; +} + +int ipa_table_iterator_end( + ipa_table_iterator* iterator, + ipa_table* table_ptr, + uint16_t rec_index, /* a table slot relative to hash */ + void* rec_ptr ) /* occupant record at index above */ +{ + bool found_end = false; + + int ret; + + IPADBG("In\n"); + + if ( ! iterator || ! table_ptr || ! rec_ptr ) + { + IPAERR("Bad arg: iterator(%p) and/or table_ptr (%p) and/or rec_ptr(%p)\n", + iterator, table_ptr, rec_ptr); + ret = -1; + goto bail; + } + + memset(iterator, 0, sizeof(ipa_table_iterator)); + + iterator->prev_index = rec_index; + iterator->prev_entry = rec_ptr; + + while ( 1 ) + { + uint16_t next_index = + table_ptr->entry_interface->entry_get_next_index(iterator->prev_entry); + + if ( ! VALID_INDEX(next_index) ) + { + found_end = true; + break; + } + + if ( next_index == iterator->prev_index ) + { + IPAERR("next_index(%u) and prev_index(%u) shouldn't be equal in %s\n", + next_index, + iterator->prev_index, + table_ptr->name); + break; + } + + iterator->prev_index = next_index; + iterator->prev_entry = GOTO_REC(table_ptr, next_index); + } + + if ( found_end ) + { + IPADBG("Iterator found end of list record\n"); + ret = 0; + } + else + { + IPAERR("Iterator can't find end of list record\n"); + ret = -1; + } + +bail: + IPADBG("Out\n"); + + return ret; +} + +int ipa_table_iterator_is_head_with_tail( + ipa_table_iterator* iterator) +{ + int ret = 0; + + IPADBG("In\n"); + + ret = VALID_INDEX(iterator->next_index) && ! VALID_INDEX(iterator->prev_index); + + IPADBG("Out\n"); + + return ret; +} + +static int InsertHead( + ipa_table* table, + void* rec_ptr, /* empty record in table */ + uint16_t rec_index, /* index of record above */ + void* user_data, + struct ipa_ioc_nat_dma_cmd* cmd ) +{ + uint16_t enable_data = 0; + + int ret = 0; + + IPADBG("In\n"); + + ret = table->entry_interface->entry_head_insert( + rec_ptr, + user_data, + &enable_data); + + if (ret) + { + IPAERR("unable to insert a new entry to the head in %s\n", table->name); + goto bail; + } + + ipa_table_add_dma_cmd( + table, + HELP_UPDATE_HEAD, + rec_ptr, + rec_index, + enable_data, + cmd); + + ++table->cur_tbl_cnt; + +bail: + IPADBG("Out\n"); + + return ret; +} + +static int InsertTail( + ipa_table* table, + void* rec_ptr, /* occupied record at index below */ + uint16_t* rec_index_ptr, /* pointer to index of record above */ + void* user_data, + struct ipa_ioc_nat_dma_cmd* cmd ) +{ + bool is_index_tbl = (table->meta) ? true : false; + + ipa_table_iterator iterator; + + uint16_t enable_data = 0; + + int ret = 0; + + IPADBG("In\n"); + + /* + * The most important side effect of the following is to set the + * iterator's prev_index and prev_entry...which will be the last + * valid entry on the end of the list. + */ + ret = ipa_table_iterator_end(&iterator, table, *rec_index_ptr, rec_ptr); + + if ( ret ) + { + IPAERR("Failed to reach the end of list following rec_index(%u) in %s\n", + *rec_index_ptr, table->name); + goto bail; + } + + /* + * The most important side effect of the following is to set the + * iterator's curr_index and curr_entry with the next available + * expansion table open slot. + */ + ret = FindExpnTblFreeEntry(table, &iterator.curr_entry, &iterator.curr_index); + + if ( ret ) + { + IPAERR("FindExpnTblFreeEntry of %s failed\n", table->name); + goto bail; + } + + /* + * Copy data into curr_entry (ie. open slot). + */ + if ( is_index_tbl ) + { + ret = table->entry_interface->entry_tail_insert( + iterator.curr_entry, + user_data); + } + else + { + /* + * We need enable bit when not index table, hence... + */ + ret = table->entry_interface->entry_head_insert( + iterator.curr_entry, + user_data, + &enable_data); + } + + if (ret) + { + IPAERR("Unable to insert a new entry to the tail in %s\n", table->name); + goto bail; + } + + /* + * Update curr_entry's prev_index field with iterator.prev_index + */ + table->entry_interface->entry_set_prev_index( + iterator.curr_entry, /* set by FindExpnTblFreeEntry above */ + iterator.curr_index, /* set by FindExpnTblFreeEntry above */ + iterator.prev_index, /* set by ipa_table_iterator_end above */ + table->meta, + table->table_entries); + + if ( ! is_index_tbl ) + { + /* + * Generate dma command to have the IPA update the + * curr_entry's enable field when not the index table... + */ + ipa_table_add_dma_cmd( + table, + HELP_UPDATE_HEAD, + iterator.curr_entry, + iterator.curr_index, + enable_data, + cmd); + } + + /* + * Generate a dma command to have the IPA update the prev_entry's + * next_index with iterator.curr_index. + */ + ipa_table_add_dma_cmd( + table, + HELP_UPDATE_ENTRY, + iterator.prev_entry, + iterator.prev_index, + iterator.curr_index, + cmd); + + ++table->cur_expn_tbl_cnt; + + *rec_index_ptr = iterator.curr_index; + +bail: + IPADBG("Out\n"); + + return ret; +} + +/** + * MakeEntryHdl() - makes an entry handle + * @tbl_hdl: [in] tbl - the table + * @tbl_entry: [in] tbl_entry - table entry + * + * Calculate the entry handle which will be returned to client + * + * Returns: >0 table entry handle + */ +static uint16_t MakeEntryHdl( + ipa_table* tbl, + uint16_t tbl_entry ) +{ + uint16_t entry_hdl = 0; + + IPADBG("In\n"); + + if (tbl_entry >= tbl->table_entries) + { + /* + * Update the index into table + */ + entry_hdl = tbl_entry - tbl->table_entries; + entry_hdl = (entry_hdl << IPA_TABLE_TYPE_BITS); + /* + * Update the expansion table type bit + */ + entry_hdl = (entry_hdl | IPA_TABLE_TYPE_MASK); + } + else + { + entry_hdl = tbl_entry; + entry_hdl = (entry_hdl << IPA_TABLE_TYPE_BITS); + } + + /* + * Set memory type bit. + */ + entry_hdl = entry_hdl | (tbl->nmi << IPA_TABLE_TYPE_MEM_SHIFT); + + IPADBG("In: tbl_entry(%u) Out: entry_hdl(%u)\n", tbl_entry, entry_hdl); + + IPADBG("Out\n"); + + return entry_hdl; +} + +static int mt_slot( + ipa_table* table_ptr, + uint32_t rule_hdl, + void* record_ptr, + uint16_t record_index, + void* meta_record_ptr, + uint16_t meta_record_index, + void* arb_data_ptr ) +{ + IPADBG("%s: Empty expansion slot: (%u) in table of size: (%u)\n", + table_ptr->name, + record_index, + table_ptr->tot_tbl_ents); + + return record_index; +} + +/* + * returns expn table entry absolute index + */ +static int FindExpnTblFreeEntry( + ipa_table* table, + void** free_entry, + uint16_t* entry_index ) +{ + int ret; + + IPADBG("In\n"); + + if ( ! table || ! free_entry || ! entry_index ) + { + IPAERR("Bad arg: table(%p) and/or " + "free_entry(%p) and/or entry_index(%p)\n", + table, free_entry, entry_index); + ret = -1; + goto bail; + } + + *entry_index = 0; + *free_entry = NULL; + + /* + * The following will start walk at expansion slots + * (ie. just after table->table_entries)... + */ + ret = ipa_table_walk(table, table->table_entries, WHEN_SLOT_EMPTY, mt_slot, 0); + + if ( ret > 0 ) + { + *entry_index = (uint16_t) ret; + + *free_entry = GOTO_REC(table, *entry_index); + + IPADBG("%s: entry_index val (%u) free_entry val (%p)\n", + table->name, + *entry_index, + *free_entry); + + ret = 0; + } + else + { + if ( ret < 0 ) + { + IPAERR("%s: While searching table for emtpy slot\n", + table->name); + } + else + { + IPADBG("%s: No empty slots (ie. expansion table full): " + "BASE (avail/used): (%u/%u) EXPN (avail/used): (%u/%u)\n", + table->name, + table->table_entries, + table->cur_tbl_cnt, + table->expn_table_entries, + table->cur_expn_tbl_cnt); + } + + ret = -1; + } + +bail: + IPADBG("Out\n"); + + return ret; +} + +/** + * Get2PowerTightUpperBound() - Returns the tight upper bound which is a power of 2 + * @num: [in] given number + * + * Returns the tight upper bound for a given number which is power of 2 + * + * Returns: the tight upper bound which is power of 2 + */ +static int Get2PowerTightUpperBound(uint16_t num) +{ + uint16_t tmp = num, prev = 0, curr = 2; + + if (num == 0) + return 2; + + while (tmp != 1) + { + prev = curr; + curr <<= 1; + tmp >>= 1; + } + + return (num == prev) ? prev : curr; +} + +/** + * GetEvenTightUpperBound() - Returns the tight upper bound which is an even number + * @num: [in] given number + * + * Returns the tight upper bound for a given number which is an even number + * + * Returns: the tight upper bound which is an even number + */ +static int GetEvenTightUpperBound(uint16_t num) +{ + if (num == 0) + return 2; + + return (num % 2) ? num + 1 : num; +} + +int ipa_calc_num_sram_table_entries( + uint32_t sram_size, + uint32_t table1_ent_size, + uint32_t table2_ent_size, + uint16_t* num_entries_ptr) +{ + ipa_table nat_table; + ipa_table index_table; + int size = 0; + uint16_t tot; + + IPADBG("In\n"); + + IPADBG("sram_size(%x or %u)\n", sram_size, sram_size); + + *num_entries_ptr = 0; + + tot = 1; + + while ( 1 ) + { + IPADBG("Trying %u entries\n", tot); + + ipa_table_init(&nat_table, + "tmp_sram_table1", + IPA_NAT_MEM_IN_DDR, + table1_ent_size, + NULL, + 0, + NULL); + + ipa_table_init(&index_table, + "tmp_sram_table1", + IPA_NAT_MEM_IN_DDR, + table2_ent_size, + NULL, + 0, + NULL); + + nat_table.table_entries = index_table.table_entries = + Get2PowerTightUpperBound(tot * IPA_BASE_TABLE_PCNT_4SRAM); + nat_table.expn_table_entries = index_table.expn_table_entries = + GetEvenTightUpperBound(tot * IPA_EXPANSION_TABLE_PCNT_4SRAM); + + size = ipa_table_calculate_size(&nat_table); + size += ipa_table_calculate_size(&index_table); + + IPADBG("%u entries consumes size(0x%x or %u)\n", tot, size, size); + + if ( size > sram_size ) + break; + + *num_entries_ptr = tot; + + ++tot; + } + + IPADBG("Optimal number of entries: %u\n", *num_entries_ptr); + + IPADBG("Out\n"); + + return (*num_entries_ptr) ? 0 : -1; +} + +int ipa_table_walk( + ipa_table* ipa_tbl_ptr, + uint16_t start_index, + When2Callback when2cb, + ipa_table_walk_cb walk_cb, + void* arb_data_ptr ) +{ + uint16_t i; + uint32_t tot; + uint8_t* rec_ptr; + void* meta_record_ptr; + uint16_t meta_record_index; + + int ret = 0; + + IPADBG("In\n"); + + if ( ! ipa_tbl_ptr || + ! VALID_WHEN2CALLBACK(when2cb) || + ! walk_cb ) + { + IPAERR("Bad arg: ipa_tbl_ptr(%p) and/or " + "when2cb(%u) and/or walk_cb(%p)\n", + ipa_tbl_ptr, + when2cb, + walk_cb); + ret = -EINVAL; + goto bail; + } + + tot = + ipa_tbl_ptr->table_entries + + ipa_tbl_ptr->expn_table_entries; + + if ( start_index >= tot ) + { + IPAERR("Bad arg: start_index(%u)\n", start_index); + ret = -EINVAL; + goto bail; + } + + /* + * Go through table... + */ + for ( i = start_index, rec_ptr = GOTO_REC(ipa_tbl_ptr, start_index); + i < tot; + i++, rec_ptr += ipa_tbl_ptr->entry_size ) + { + bool call_back; + + if ( ipa_tbl_ptr->entry_interface->entry_is_valid(rec_ptr) ) + { + call_back = (when2cb == WHEN_SLOT_FILLED) ? true : false; + } + else + { + call_back = (when2cb == WHEN_SLOT_EMPTY) ? true : false; + } + + if ( call_back ) + { + uint32_t rule_hdl = MakeEntryHdl(ipa_tbl_ptr, i); + + meta_record_ptr = NULL; + meta_record_index = 0; + + if ( i >= ipa_tbl_ptr->table_entries && ipa_tbl_ptr->meta ) + { + meta_record_index = i - ipa_tbl_ptr->table_entries; + + meta_record_ptr = (uint8_t*) ipa_tbl_ptr->meta + + (meta_record_index * ipa_tbl_ptr->meta_entry_size); + } + + ret = walk_cb( + ipa_tbl_ptr, + rule_hdl, + rec_ptr, + i, + meta_record_ptr, + meta_record_index, + arb_data_ptr); + + if ( ret != 0 ) + { + if ( ret < 0 ) + { + IPAERR("walk_cb returned non-zero (%d)\n", ret); + } + else + { + IPADBG("walk_cb returned non-zero (%d)\n", ret); + } + goto bail; + } + } + } + +bail: + IPADBG("Out\n"); + + return ret; +} + +int ipa_table_add_dma_cmd( + ipa_table* tbl_ptr, + dma_help_type help_type, + void* rec_ptr, + uint16_t rec_index, + uint16_t data_for_entry, + struct ipa_ioc_nat_dma_cmd* cmd_ptr ) +{ + ipa_table_dma_cmd_helper* help_ptr; + + uint32_t tab_sz, entry_offset; + + uint8_t is_expn; + + int ret = 0; + + IPADBG("In\n"); + + if ( ! tbl_ptr || + ! VALID_DMA_HELP_TYPE(help_type) || + ! rec_ptr || + ! cmd_ptr ) + { + IPAERR("Bad arg: tbl_ptr(%p) and/or help_type(%u) " + "and/or rec_ptr(%p) and/or cmd_ptr(%p)\n", + tbl_ptr, + help_type, + rec_ptr, + cmd_ptr); + ret = -EINVAL; + goto bail; + } + + tab_sz = + tbl_ptr->table_entries + + tbl_ptr->expn_table_entries; + + if ( rec_index >= tab_sz ) + { + IPAERR("Bad arg: rec_index(%u)\n", rec_index); + ret = -EINVAL; + goto bail; + } + + is_expn = (rec_index >= tbl_ptr->table_entries); + + entry_offset = (uint8_t*) rec_ptr - + ((is_expn) ? tbl_ptr->expn_table_addr : tbl_ptr->table_addr); + + ipa_table_dma_cmd_generate( + tbl_ptr->dma_help[help_type], + is_expn, + entry_offset, + data_for_entry, + cmd_ptr); + +bail: + IPADBG("Out\n"); + + return ret; +} diff --git a/qcom/opensource/dataipa/ipanat/test/Makefile.am b/qcom/opensource/dataipa/ipanat/test/Makefile.am new file mode 100644 index 0000000000..cefa7edf53 --- /dev/null +++ b/qcom/opensource/dataipa/ipanat/test/Makefile.am @@ -0,0 +1,46 @@ +AM_CPPFLAGS = -I./../inc \ + -I$(top_srcdir)/ipanat/inc + +AM_CPPFLAGS += -Wall -Wundef -Wno-trigraphs +AM_CPPFLAGS += -g -DDEBUG -DNAT_DEBUG + +ipanattest_SOURCES = \ + ipa_nat_testREG.c \ + ipa_nat_test000.c \ + ipa_nat_test001.c \ + ipa_nat_test002.c \ + ipa_nat_test003.c \ + ipa_nat_test004.c \ + ipa_nat_test005.c \ + ipa_nat_test006.c \ + ipa_nat_test007.c \ + ipa_nat_test008.c \ + ipa_nat_test009.c \ + ipa_nat_test010.c \ + ipa_nat_test011.c \ + ipa_nat_test012.c \ + ipa_nat_test013.c \ + ipa_nat_test014.c \ + ipa_nat_test015.c \ + ipa_nat_test016.c \ + ipa_nat_test017.c \ + ipa_nat_test018.c \ + ipa_nat_test019.c \ + ipa_nat_test020.c \ + ipa_nat_test021.c \ + ipa_nat_test022.c \ + ipa_nat_test023.c \ + ipa_nat_test024.c \ + ipa_nat_test025.c \ + ipa_nat_test999.c \ + main.c + +bin_PROGRAMS = ipanattest + +requiredlibs = ../src/libipanat.la + +ipanattest_LDADD = $(requiredlibs) + +LOCAL_MODULE := libipanat +LOCAL_PRELINK_MODULE := false +include $(BUILD_SHARED_LIBRARY) diff --git a/qcom/opensource/dataipa/ipanat/test/README.txt b/qcom/opensource/dataipa/ipanat/test/README.txt new file mode 100644 index 0000000000..9a84b10095 --- /dev/null +++ b/qcom/opensource/dataipa/ipanat/test/README.txt @@ -0,0 +1,66 @@ +INTRODUCTION +------------ + +The ipanattest allow its user to drive NAT testing. It is run thusly: + +# ipanattest [-d -r N -i N -e N -m mt] +Where: + -d Each test is discrete (create table, add rules, destroy table) + If not specified, only one table create and destroy for all tests + -r N Where N is the number of times to run the inotify regression test + -i N Where N is the number of times (iterations) to run test + -e N Where N is the number of entries in the NAT + -m mt Where mt is the type of memory to use for the NAT + Legal mt's: DDR, SRAM, or HYBRID (ie. use SRAM and DDR) + -g M-N Run tests M through N only + +More about each command line option: + +-d Makes each test discrete; meaning that, each test will create a + table, add rules, then destory the table. + + Conversely, when -d not specified, each test will not create + and destroy a table. Only one table create and destroy at the + start and end of the run...with all test being run in between. + +-r N Will cause the inotify regression test to be run N times. + +-i N Will cause each test to be run N times + +-e N Will cause the creation of a table with N entries + +-m mt Will cause the NAT to live in either SRAM, DDR, or both + (ie. HYBRID) + +-g M-N Will cause test M to N to be run. This allows you to skip + or isolate tests + +When run with no arguments (ie. defaults): + + 1) The tests will be non-discrete + 2) With only one iteration of the tests + 3) On a DDR based table with one hundred entries + 4) No inotify regression will be run + +EXAMPLE COMMAND LINES +--------------------- + +To execute discrete tests (create, add rules, and delete table for +each test) one time on a table with one hundred entries: + +# ipanattest -d -i 1 -e 100 + +To execute non-discrete (create and delete table only once) tests five +times on a table with thirty-two entries: + +# ipanattest -i 5 -e 32 + +To execute inotify regression test 5 times + +# ipanattest -r 5 + +ADDING NEW TESTS +---------------- + +In main.c, please see and embellish nt_array[] and use the following +file as a model: ipa_nat_testMODEL.c diff --git a/qcom/opensource/dataipa/ipanat/test/ipa_nat_test.h b/qcom/opensource/dataipa/ipanat/test/ipa_nat_test.h new file mode 100644 index 0000000000..963433311e --- /dev/null +++ b/qcom/opensource/dataipa/ipanat/test/ipa_nat_test.h @@ -0,0 +1,180 @@ +/* + * Copyright (c) 2014, 2018-2019 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * =========================================================================== + * + * INCLUDE FILES FOR MODULE + * + * =========================================================================== + */ +#include +#include +#include +#include +#include +#include /* for proto definitions */ + +#include "ipa_nat_drv.h" +#include "ipa_nat_drvi.h" + +#undef array_sz +#define array_sz(a) \ + ( sizeof(a)/sizeof(a[0]) ) + +#define u32 uint32_t +#define u16 uint16_t +#define u8 uint8_t + +#define RAN_ADDR rand_ip_addr() +#define RAN_PORT rand_ip_port() + +static inline u32 rand_ip_addr() +{ + static char buf[64]; + + snprintf( + buf, sizeof(buf), + "%u.%u.%u.%u", + (rand() % 254) + 1, + rand() % 255, + rand() % 255, + (rand() % 254) + 1); + + return (u32) inet_addr(buf); +} + +static inline u16 rand_ip_port() +{ + return (u16) ((rand() % 60535) + 5000); +} + +/*============ Preconditions to run NAT Test cases =========*/ +#define IPA_NAT_TEST_PRE_COND_TE 20 + +#define CHECK_ERR(x) \ + if ( x ) { \ + IPAERR("Abrupt end of %s with " \ + "err: %d at line: %d\n", \ + __FUNCTION__, x, __LINE__); \ + return -1; \ + } + +#define CHECK_ERR_TBL_STOP(x, th) \ + if ( th ) { \ + int _ter_ = ipa_nat_validate_ipv4_table(th); \ + if ( _ter_ ) { \ + if ( sep ) { \ + ipa_nat_del_ipv4_tbl(th); \ + } \ + IPAERR("Abrupt end of %s with " \ + "err: %d at line: %d\n", \ + __FUNCTION__, _ter_, __LINE__); \ + return -1; \ + } \ + } \ + if ( x ) { \ + if ( th ) { \ + ipa_nat_dump_ipv4_table(th); \ + if( sep ) { \ + ipa_nat_del_ipv4_tbl(th); \ + } \ + } \ + IPAERR("Abrupt end of %s with " \ + "err: %d at line: %d\n", \ + __FUNCTION__, x, __LINE__); \ + return -1; \ + } + +#define CHECK_ERR_TBL_ACTION(x, th, action) \ + if ( th ) { \ + int _ter_ = ipa_nat_validate_ipv4_table(th); \ + if ( _ter_ ) { \ + IPAERR("ipa_nat_validate_ipv4_table() failed " \ + "in: %s at line: %d\n", \ + __FUNCTION__, __LINE__); \ + action; \ + } \ + } \ + if ( x ) { \ + if ( th ) { \ + ipa_nat_dump_ipv4_table(th); \ + } \ + IPAERR("error: %d in %s at line: %d\n", \ + x, __FUNCTION__, __LINE__); \ + action; \ + } + +typedef int (*NatTestFunc)( + const char*, u32, int, u32, int, void*); + +typedef struct +{ + const char* func_name; + int num_ents_trigger; + int test_hold_time_in_secs; + NatTestFunc func; +} NatTests; + +#undef NAT_TEST_ENTRY +#define NAT_TEST_ENTRY(f, n, ht) \ + {#f, (n), (ht), f} + +#define NAT_DEBUG +int ipa_nat_validate_ipv4_table(u32); + +int ipa_nat_testREG(const char*, u32, int, u32, int, void*); + +int ipa_nat_test000(const char*, u32, int, u32, int, void*); +int ipa_nat_test001(const char*, u32, int, u32, int, void*); +int ipa_nat_test002(const char*, u32, int, u32, int, void*); +int ipa_nat_test003(const char*, u32, int, u32, int, void*); +int ipa_nat_test004(const char*, u32, int, u32, int, void*); +int ipa_nat_test005(const char*, u32, int, u32, int, void*); +int ipa_nat_test006(const char*, u32, int, u32, int, void*); +int ipa_nat_test007(const char*, u32, int, u32, int, void*); +int ipa_nat_test008(const char*, u32, int, u32, int, void*); +int ipa_nat_test009(const char*, u32, int, u32, int, void*); +int ipa_nat_test010(const char*, u32, int, u32, int, void*); +int ipa_nat_test011(const char*, u32, int, u32, int, void*); +int ipa_nat_test012(const char*, u32, int, u32, int, void*); +int ipa_nat_test013(const char*, u32, int, u32, int, void*); +int ipa_nat_test014(const char*, u32, int, u32, int, void*); +int ipa_nat_test015(const char*, u32, int, u32, int, void*); +int ipa_nat_test016(const char*, u32, int, u32, int, void*); +int ipa_nat_test017(const char*, u32, int, u32, int, void*); +int ipa_nat_test018(const char*, u32, int, u32, int, void*); +int ipa_nat_test019(const char*, u32, int, u32, int, void*); +int ipa_nat_test020(const char*, u32, int, u32, int, void*); +int ipa_nat_test021(const char*, u32, int, u32, int, void*); +int ipa_nat_test022(const char*, u32, int, u32, int, void*); +int ipa_nat_test023(const char*, u32, int, u32, int, void*); +int ipa_nat_test024(const char*, u32, int, u32, int, void*); +int ipa_nat_test025(const char*, u32, int, u32, int, void*); +int ipa_nat_test999(const char*, u32, int, u32, int, void*); diff --git a/qcom/opensource/dataipa/ipanat/test/ipa_nat_test000.c b/qcom/opensource/dataipa/ipanat/test/ipa_nat_test000.c new file mode 100644 index 0000000000..9444fae95c --- /dev/null +++ b/qcom/opensource/dataipa/ipanat/test/ipa_nat_test000.c @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2014-2019 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*=========================================================================*/ +/*! + @file + ipa_nat_test000.c + + @brief + Verify the following scenario: + 1. Add ipv4 table +*/ +/*===========================================================================*/ + +#include "ipa_nat_test.h" + +int ipa_nat_test000( + const char* nat_mem_type, + u32 pub_ip_add, + int total_entries, + u32 tbl_hdl, + int sep, + void* arb_data_ptr) +{ + int* tbl_hdl_ptr = (int*) arb_data_ptr; + + int ret; + + IPADBG("In\n"); + + if ( ! sep ) + { + IPADBG("calling ipa_nat_add_ipv4_tbl()\n"); + + ret = ipa_nat_add_ipv4_tbl(pub_ip_add, nat_mem_type, total_entries, tbl_hdl_ptr); + CHECK_ERR_TBL_STOP(ret, *tbl_hdl_ptr); + + IPADBG("create nat ipv4 table successfully()\n"); + } + + IPADBG("Out\n"); + + return 0; +} diff --git a/qcom/opensource/dataipa/ipanat/test/ipa_nat_test001.c b/qcom/opensource/dataipa/ipanat/test/ipa_nat_test001.c new file mode 100644 index 0000000000..24093d5378 --- /dev/null +++ b/qcom/opensource/dataipa/ipanat/test/ipa_nat_test001.c @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2014, 2018-2019 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*=========================================================================*/ +/*! + @file + ipa_nat_test001.c + + @brief + Verify the following scenario: + 1. Add ipv4 table + 2. Add ipv4 rule + 3. Delete ipv4 table +*/ +/*===========================================================================*/ + +#include "ipa_nat_test.h" + +int ipa_nat_test001( + const char* nat_mem_type, + u32 pub_ip_add, + int total_entries, + u32 tbl_hdl, + int sep, + void* arb_data_ptr) +{ + int* tbl_hdl_ptr = (int*) arb_data_ptr; + int ret; + u32 rule_hdl; + ipa_nat_ipv4_rule ipv4_rule = {0}; + + ipv4_rule.target_ip = RAN_ADDR; + ipv4_rule.target_port = RAN_PORT; + + ipv4_rule.private_ip = RAN_ADDR; + ipv4_rule.private_port = RAN_PORT; + + ipv4_rule.protocol = IPPROTO_TCP; + ipv4_rule.public_port = RAN_PORT; + + IPADBG("In\n"); + + if ( sep ) + { + ret = ipa_nat_add_ipv4_tbl(pub_ip_add, nat_mem_type, total_entries, &tbl_hdl); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + } + + ret = ipa_nat_add_ipv4_rule(tbl_hdl, &ipv4_rule, &rule_hdl); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + if ( sep ) + { + ret = ipa_nat_del_ipv4_tbl(tbl_hdl); + *tbl_hdl_ptr = 0; + CHECK_ERR(ret); + } + + IPADBG("Out\n"); + + return 0; +} diff --git a/qcom/opensource/dataipa/ipanat/test/ipa_nat_test002.c b/qcom/opensource/dataipa/ipanat/test/ipa_nat_test002.c new file mode 100644 index 0000000000..788b12ca19 --- /dev/null +++ b/qcom/opensource/dataipa/ipanat/test/ipa_nat_test002.c @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2014, 2018-2019 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*=========================================================================*/ +/*! + @file + ipa_nat_test002.c + + @brief + Verify the following scenario: + 1. Add ipv4 table + 2. Add ipv4 rule + 3. delete ipv4 rule + 4. Delete ipv4 table +*/ +/*=========================================================================*/ + +#include "ipa_nat_test.h" + +int ipa_nat_test002( + const char* nat_mem_type, + u32 pub_ip_add, + int total_entries, + u32 tbl_hdl, + int sep, + void* arb_data_ptr) +{ + int* tbl_hdl_ptr = (int*) arb_data_ptr; + int ret; + u32 rule_hdl; + ipa_nat_ipv4_rule ipv4_rule = {0}; + + ipv4_rule.target_ip = RAN_ADDR; + ipv4_rule.target_port = RAN_PORT; + + ipv4_rule.private_ip = RAN_ADDR; + ipv4_rule.private_port = RAN_PORT; + + ipv4_rule.protocol = IPPROTO_TCP; + ipv4_rule.public_port = RAN_PORT; + + IPADBG("In\n"); + + if ( sep ) + { + ret = ipa_nat_add_ipv4_tbl(pub_ip_add, nat_mem_type, total_entries, &tbl_hdl); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + } + + ret = ipa_nat_add_ipv4_rule(tbl_hdl, &ipv4_rule, &rule_hdl); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_del_ipv4_rule(tbl_hdl, rule_hdl); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + if ( sep ) + { + ret = ipa_nat_del_ipv4_tbl(tbl_hdl); + *tbl_hdl_ptr = 0; + CHECK_ERR(ret); + } + + IPADBG("Out\n"); + + return 0; +} diff --git a/qcom/opensource/dataipa/ipanat/test/ipa_nat_test003.c b/qcom/opensource/dataipa/ipanat/test/ipa_nat_test003.c new file mode 100644 index 0000000000..8bc4ecb61b --- /dev/null +++ b/qcom/opensource/dataipa/ipanat/test/ipa_nat_test003.c @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2014, 2018-2019 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +/*=========================================================================*/ +/*! + @file + IPA_NAT_ipa_nat_test003.cpp + + @brief + Verify the following scenario: + 1. Add ipv4 table + 2. Add ipv4 rule + 3. Add ipv4 rule + 4. Delete ipv4 table +*/ +/*=========================================================================*/ + +#include "ipa_nat_test.h" + +int ipa_nat_test003( + const char* nat_mem_type, + u32 pub_ip_add, + int total_entries, + u32 tbl_hdl, + int sep, + void* arb_data_ptr) +{ + int* tbl_hdl_ptr = (int*) arb_data_ptr; + + ipa_nat_ipv4_rule ipv4_rule = {0}; + u32 rule_hdl; + + int ret; + + IPADBG("In\n"); + + if ( sep ) + { + ret = ipa_nat_add_ipv4_tbl(pub_ip_add, nat_mem_type, total_entries, &tbl_hdl); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + } + + ipv4_rule.target_ip = RAN_ADDR; + ipv4_rule.target_port = RAN_PORT; + + ipv4_rule.private_ip = RAN_ADDR; + ipv4_rule.private_port = RAN_PORT; + + ipv4_rule.protocol = IPPROTO_TCP; + ipv4_rule.public_port = RAN_PORT; + + ret = ipa_nat_add_ipv4_rule(tbl_hdl, &ipv4_rule, &rule_hdl); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ipv4_rule.target_ip = RAN_ADDR; + ipv4_rule.target_port = RAN_PORT; + + ipv4_rule.private_ip = RAN_ADDR; + ipv4_rule.private_port = RAN_PORT; + + ipv4_rule.protocol = IPPROTO_TCP; + ipv4_rule.public_port = RAN_PORT; + + ret = ipa_nat_add_ipv4_rule(tbl_hdl, &ipv4_rule, &rule_hdl); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + if ( sep ) + { + ret = ipa_nat_del_ipv4_tbl(tbl_hdl); + *tbl_hdl_ptr = 0; + CHECK_ERR(ret); + } + + IPADBG("Out\n"); + + return 0; +} diff --git a/qcom/opensource/dataipa/ipanat/test/ipa_nat_test004.c b/qcom/opensource/dataipa/ipanat/test/ipa_nat_test004.c new file mode 100644 index 0000000000..a9d84b63a6 --- /dev/null +++ b/qcom/opensource/dataipa/ipanat/test/ipa_nat_test004.c @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2014, 2018-2019 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*=========================================================================*/ +/*! + @file + ipa_nat_test004.cpp + + @brief + Verify the following scenario: + 1. Add ipv4 table + 2. Delete a bogus table handle + 3. Delete ipv4 table +*/ +/*===========================================================================*/ + +#include "ipa_nat_test.h" + +int ipa_nat_test004( + const char* nat_mem_type, + u32 pub_ip_add, + int total_entries, + u32 tbl_hdl, + int sep, + void* arb_data_ptr) +{ + int* tbl_hdl_ptr = (int*) arb_data_ptr; + int ret = 0; + u32 tbl_hdl1 = 0xFFFFFFFF; + + IPADBG("In\n"); + + if ( sep ) + { + ret = ipa_nat_add_ipv4_tbl(pub_ip_add, nat_mem_type, total_entries, &tbl_hdl); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + } + + ret = ipa_nat_del_ipv4_tbl(tbl_hdl1); /* intentionally pass bad handle */ + + if ( ret == 0 ) + { + IPAERR("Able to delete table using invalid table handle\n"); + CHECK_ERR_TBL_STOP(-1, tbl_hdl); + } + + if ( sep ) + { + ret = ipa_nat_del_ipv4_tbl(tbl_hdl); + *tbl_hdl_ptr = 0; + CHECK_ERR(ret); + } + + IPADBG("Out\n"); + + return 0; +} diff --git a/qcom/opensource/dataipa/ipanat/test/ipa_nat_test005.c b/qcom/opensource/dataipa/ipanat/test/ipa_nat_test005.c new file mode 100644 index 0000000000..e2bb0f1d3d --- /dev/null +++ b/qcom/opensource/dataipa/ipanat/test/ipa_nat_test005.c @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2014, 2018-2019 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*=========================================================================*/ +/*! + @file + ipa_nat_test005.c + + @brief + Verify the following scenario: + 1. Add ipv4 table + 2. Add ipv4 rule + 3. Delete ipv4 rule + 4. Add ipv4 rule + 5. Delete ipv4 table +*/ +/*=========================================================================*/ + +#include "ipa_nat_test.h" + +int ipa_nat_test005( + const char* nat_mem_type, + u32 pub_ip_add, + int total_entries, + u32 tbl_hdl, + int sep, + void* arb_data_ptr) +{ + int* tbl_hdl_ptr = (int*) arb_data_ptr; + ipa_nat_ipv4_rule ipv4_rule = {0}; + u32 rule_hdl; + + int ret; + + ipv4_rule.target_ip = RAN_ADDR; + ipv4_rule.target_port = RAN_PORT; + + ipv4_rule.private_ip = RAN_ADDR; + ipv4_rule.private_port = RAN_PORT; + + ipv4_rule.protocol = IPPROTO_TCP; + ipv4_rule.public_port = RAN_PORT; + + IPADBG("In\n"); + + if ( sep ) + { + ret = ipa_nat_add_ipv4_tbl(pub_ip_add, nat_mem_type, total_entries, &tbl_hdl); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + } + + ret = ipa_nat_add_ipv4_rule(tbl_hdl, &ipv4_rule, &rule_hdl); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_del_ipv4_rule(tbl_hdl, rule_hdl); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_add_ipv4_rule(tbl_hdl, &ipv4_rule, &rule_hdl); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + if ( sep ) + { + ret = ipa_nat_del_ipv4_tbl(tbl_hdl); + *tbl_hdl_ptr = 0; + CHECK_ERR(ret); + } + + IPADBG("Out\n"); + + return 0; +} diff --git a/qcom/opensource/dataipa/ipanat/test/ipa_nat_test006.c b/qcom/opensource/dataipa/ipanat/test/ipa_nat_test006.c new file mode 100644 index 0000000000..7ce343c02e --- /dev/null +++ b/qcom/opensource/dataipa/ipanat/test/ipa_nat_test006.c @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2014, 2018-2019 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*=========================================================================*/ +/*! + @file + ipa_nat_test006.c + + @brief + Verify the following scenario: + 1. Add ipv4 table + 2. Add ipv rule + 3. Add same ipv rule + 4. Delete first followed by second + 5. Delete ipv4 table +*/ +/*=========================================================================*/ + +#include "ipa_nat_test.h" + +int ipa_nat_test006( + const char* nat_mem_type, + u32 pub_ip_add, + int total_entries, + u32 tbl_hdl, + int sep, + void* arb_data_ptr) +{ + int* tbl_hdl_ptr = (int*) arb_data_ptr; + + ipa_nat_ipv4_rule ipv4_rule = {0}; + + u32 rule_hdl; + u32 rule_hdl1; + + int ret; + + ipv4_rule.target_ip = RAN_ADDR; + ipv4_rule.target_port = RAN_PORT; + ipv4_rule.private_ip = RAN_ADDR; + ipv4_rule.private_port = RAN_PORT; + ipv4_rule.protocol = IPPROTO_TCP; + ipv4_rule.public_port = RAN_PORT; + + IPADBG("In\n"); + + if ( sep ) + { + ret = ipa_nat_add_ipv4_tbl(pub_ip_add, nat_mem_type, total_entries, &tbl_hdl); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + } + + ret = ipa_nat_add_ipv4_rule(tbl_hdl, &ipv4_rule, &rule_hdl); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_add_ipv4_rule(tbl_hdl, &ipv4_rule, &rule_hdl1); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_del_ipv4_rule(tbl_hdl, rule_hdl); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_del_ipv4_rule(tbl_hdl, rule_hdl1); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + if ( sep ) + { + ret = ipa_nat_del_ipv4_tbl(tbl_hdl); + *tbl_hdl_ptr = 0; + CHECK_ERR(ret); + } + + IPADBG("Out\n"); + + return 0; +} diff --git a/qcom/opensource/dataipa/ipanat/test/ipa_nat_test007.c b/qcom/opensource/dataipa/ipanat/test/ipa_nat_test007.c new file mode 100644 index 0000000000..64069411dd --- /dev/null +++ b/qcom/opensource/dataipa/ipanat/test/ipa_nat_test007.c @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2014, 2018-2019 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*=========================================================================*/ +/*! + @file + ipa_nat_test007.cpp + + @brief + Verify the following scenario: + 1. Add ipv4 table + 2. add same ipv rules + 3. delete second followed by first + 4. Delete ipv4 table +*/ +/*=========================================================================*/ + +#include "ipa_nat_test.h" + +int ipa_nat_test007( + const char* nat_mem_type, + u32 pub_ip_add, + int total_entries, + u32 tbl_hdl, + int sep, + void* arb_data_ptr) +{ + int* tbl_hdl_ptr = (int*) arb_data_ptr; + + ipa_nat_ipv4_rule ipv4_rule = {0}; + + u32 rule_hdl; + u32 rule_hdl1; + + int ret; + + ipv4_rule.target_ip = RAN_ADDR; + ipv4_rule.target_port = RAN_PORT; + ipv4_rule.private_ip = RAN_ADDR; + ipv4_rule.private_port = RAN_PORT; + ipv4_rule.protocol = IPPROTO_TCP; + ipv4_rule.public_port = RAN_PORT; + + IPADBG("In\n"); + + if ( sep ) + { + ret = ipa_nat_add_ipv4_tbl(pub_ip_add, nat_mem_type, total_entries, &tbl_hdl); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + } + + ret = ipa_nat_add_ipv4_rule(tbl_hdl, &ipv4_rule, &rule_hdl); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_add_ipv4_rule(tbl_hdl, &ipv4_rule, &rule_hdl1); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_del_ipv4_rule(tbl_hdl, rule_hdl1); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_del_ipv4_rule(tbl_hdl, rule_hdl); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + if ( sep ) + { + ret = ipa_nat_del_ipv4_tbl(tbl_hdl); + *tbl_hdl_ptr = 0; + CHECK_ERR(ret); + } + + IPADBG("Out\n"); + + return 0; +} diff --git a/qcom/opensource/dataipa/ipanat/test/ipa_nat_test008.c b/qcom/opensource/dataipa/ipanat/test/ipa_nat_test008.c new file mode 100644 index 0000000000..ba4f5c4726 --- /dev/null +++ b/qcom/opensource/dataipa/ipanat/test/ipa_nat_test008.c @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2014, 2018-2019 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*=========================================================================*/ +/*! + @file + ipa_nat_test008.c + + @brief + Verify the following scenario: + 1. Add ipv4 table + 2. add 2 distinct rules + 3. delete first followed by second + 4. Delete ipv4 table +*/ +/*=========================================================================*/ + +#include "ipa_nat_test.h" + +int ipa_nat_test008( + const char* nat_mem_type, + u32 pub_ip_add, + int total_entries, + u32 tbl_hdl, + int sep, + void* arb_data_ptr) +{ + int* tbl_hdl_ptr = (int*) arb_data_ptr; + int ret; + u32 rule_hdl, rule_hdl1; + ipa_nat_ipv4_rule ipv4_rule = {0}, ipv4_rule1 = {0}; + + ipv4_rule.target_ip = RAN_ADDR; + ipv4_rule.target_port = RAN_PORT; + ipv4_rule.private_ip = RAN_ADDR; + ipv4_rule.private_port = RAN_PORT; + ipv4_rule.protocol = IPPROTO_TCP; + ipv4_rule.public_port = RAN_PORT; + + ipv4_rule1.target_ip = RAN_ADDR; + ipv4_rule1.target_port = RAN_PORT; + ipv4_rule1.private_ip = RAN_ADDR; + ipv4_rule1.private_port = RAN_PORT; + ipv4_rule1.protocol = IPPROTO_TCP; + ipv4_rule1.public_port = RAN_PORT; + + IPADBG("In\n"); + + if ( sep ) + { + ret = ipa_nat_add_ipv4_tbl(pub_ip_add, nat_mem_type, total_entries, &tbl_hdl); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + } + + ret = ipa_nat_add_ipv4_rule(tbl_hdl, &ipv4_rule, &rule_hdl); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_add_ipv4_rule(tbl_hdl, &ipv4_rule1, &rule_hdl1); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_del_ipv4_rule(tbl_hdl, rule_hdl); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_del_ipv4_rule(tbl_hdl, rule_hdl1); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + if ( sep ) + { + ret = ipa_nat_del_ipv4_tbl(tbl_hdl); + *tbl_hdl_ptr = 0; + CHECK_ERR(ret); + } + + IPADBG("Out\n"); + + return 0; +} diff --git a/qcom/opensource/dataipa/ipanat/test/ipa_nat_test009.c b/qcom/opensource/dataipa/ipanat/test/ipa_nat_test009.c new file mode 100644 index 0000000000..c73cf97d9e --- /dev/null +++ b/qcom/opensource/dataipa/ipanat/test/ipa_nat_test009.c @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2014, 2018-2019 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*=========================================================================*/ +/*! + @file + ipa_nat_test009.cpp + + @brief + Verify the following scenario: + 1. Add ipv4 table + 2. add 2 distinct rules + 3. delete second followed by first + 4. Delete ipv4 table +*/ +/*=========================================================================*/ + +#include "ipa_nat_test.h" + +int ipa_nat_test009( + const char* nat_mem_type, + u32 pub_ip_add, + int total_entries, + u32 tbl_hdl, + int sep, + void* arb_data_ptr) +{ + int* tbl_hdl_ptr = (int*) arb_data_ptr; + int ret; + u32 rule_hdl, rule_hdl1; + ipa_nat_ipv4_rule ipv4_rule = {0}, ipv4_rule1 = {0}; + + ipv4_rule.target_ip = RAN_ADDR; + ipv4_rule.target_port = RAN_PORT; + ipv4_rule.private_ip = RAN_ADDR; + ipv4_rule.private_port = RAN_PORT; + ipv4_rule.protocol = IPPROTO_TCP; + ipv4_rule.public_port = RAN_PORT; + + ipv4_rule1.target_ip = RAN_ADDR; + ipv4_rule1.target_port = RAN_PORT; + ipv4_rule1.private_ip = RAN_ADDR; + ipv4_rule1.private_port = RAN_PORT; + ipv4_rule1.protocol = IPPROTO_TCP; + ipv4_rule1.public_port = RAN_PORT; + + IPADBG("In\n"); + + if ( sep ) + { + ret = ipa_nat_add_ipv4_tbl(pub_ip_add, nat_mem_type, total_entries, &tbl_hdl); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + } + + ret = ipa_nat_add_ipv4_rule(tbl_hdl, &ipv4_rule, &rule_hdl); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_add_ipv4_rule(tbl_hdl, &ipv4_rule1, &rule_hdl1); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_del_ipv4_rule(tbl_hdl, rule_hdl1); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_del_ipv4_rule(tbl_hdl, rule_hdl); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + if ( sep ) + { + ret = ipa_nat_del_ipv4_tbl(tbl_hdl); + *tbl_hdl_ptr = 0; + CHECK_ERR(ret); + } + + IPADBG("Out\n"); + + return 0; +} diff --git a/qcom/opensource/dataipa/ipanat/test/ipa_nat_test010.c b/qcom/opensource/dataipa/ipanat/test/ipa_nat_test010.c new file mode 100644 index 0000000000..aa4c2b7023 --- /dev/null +++ b/qcom/opensource/dataipa/ipanat/test/ipa_nat_test010.c @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2014, 2018-2019 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*=========================================================================*/ +/*! + @file + ipa_nat_test010.c + + @brief + Verify the following scenario: + 1. Add ipv4 table + 2. add 3 distinct ipv4 rules + 3. delete first, second followed by last + 4. Delete ipv4 table +*/ +/*=========================================================================*/ + +#include "ipa_nat_test.h" + +int ipa_nat_test010( + const char* nat_mem_type, + u32 pub_ip_add, + int total_entries, + u32 tbl_hdl, + int sep, + void* arb_data_ptr) +{ + int* tbl_hdl_ptr = (int*) arb_data_ptr; + int ret; + u32 rule_hdl, rule_hdl1, rule_hdl2; + ipa_nat_ipv4_rule ipv4_rule = {0}, ipv4_rule1 = {0}, ipv4_rule2 = {0}; + + ipv4_rule.target_ip = RAN_ADDR; + ipv4_rule.target_port = RAN_PORT; + ipv4_rule.private_ip = RAN_ADDR; + ipv4_rule.private_port = RAN_PORT; + ipv4_rule.protocol = IPPROTO_TCP; + ipv4_rule.public_port = RAN_PORT; + + ipv4_rule1.target_ip = RAN_ADDR; + ipv4_rule1.target_port = RAN_PORT; + ipv4_rule1.private_ip = RAN_ADDR; + ipv4_rule1.private_port = RAN_PORT; + ipv4_rule1.protocol = IPPROTO_TCP; + ipv4_rule1.public_port = RAN_PORT; + + ipv4_rule2.target_ip = RAN_ADDR; + ipv4_rule2.target_port = RAN_PORT; + ipv4_rule2.private_ip = RAN_ADDR; + ipv4_rule2.private_port = RAN_PORT; + ipv4_rule2.protocol = IPPROTO_TCP; + ipv4_rule2.public_port = RAN_PORT; + + IPADBG("In\n"); + + if ( sep ) + { + ret = ipa_nat_add_ipv4_tbl(pub_ip_add, nat_mem_type, total_entries, &tbl_hdl); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + } + + ret = ipa_nat_add_ipv4_rule(tbl_hdl, &ipv4_rule, &rule_hdl); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_add_ipv4_rule(tbl_hdl, &ipv4_rule1, &rule_hdl1); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_add_ipv4_rule(tbl_hdl, &ipv4_rule2, &rule_hdl2); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_del_ipv4_rule(tbl_hdl, rule_hdl); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_del_ipv4_rule(tbl_hdl, rule_hdl1); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_del_ipv4_rule(tbl_hdl, rule_hdl2); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + if ( sep ) + { + ret = ipa_nat_del_ipv4_tbl(tbl_hdl); + *tbl_hdl_ptr = 0; + CHECK_ERR(ret); + } + + IPADBG("Out\n"); + + return 0; +} diff --git a/qcom/opensource/dataipa/ipanat/test/ipa_nat_test011.c b/qcom/opensource/dataipa/ipanat/test/ipa_nat_test011.c new file mode 100644 index 0000000000..ab018c796e --- /dev/null +++ b/qcom/opensource/dataipa/ipanat/test/ipa_nat_test011.c @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2014, 2018-2019 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*=========================================================================*/ +/*! + @file + ipa_nat_test011.cpp + + @brief + Verify the following scenario: + 1. Add ipv4 table + 2. add 3 distinct ipv4 rules + 3. delete second, first followed by last + 4. Delete ipv4 table +*/ +/*=========================================================================*/ + +#include "ipa_nat_test.h" + +int ipa_nat_test011( + const char* nat_mem_type, + u32 pub_ip_add, + int total_entries, + u32 tbl_hdl, + int sep, + void* arb_data_ptr) +{ + int* tbl_hdl_ptr = (int*) arb_data_ptr; + int ret; + u32 rule_hdl, rule_hdl1, rule_hdl2; + ipa_nat_ipv4_rule ipv4_rule = {0}, ipv4_rule1 = {0}, ipv4_rule2 = {0}; + + ipv4_rule.target_ip = RAN_ADDR; + ipv4_rule.target_port = RAN_PORT; + ipv4_rule.private_ip = RAN_ADDR; + ipv4_rule.private_port = RAN_PORT; + ipv4_rule.protocol = IPPROTO_TCP; + ipv4_rule.public_port = RAN_PORT; + + ipv4_rule1.target_ip = RAN_ADDR; + ipv4_rule1.target_port = RAN_PORT; + ipv4_rule1.private_ip = RAN_ADDR; + ipv4_rule1.private_port = RAN_PORT; + ipv4_rule1.protocol = IPPROTO_TCP; + ipv4_rule1.public_port = RAN_PORT; + + ipv4_rule2.target_ip = RAN_ADDR; + ipv4_rule2.target_port = RAN_PORT; + ipv4_rule2.private_ip = RAN_ADDR; + ipv4_rule2.private_port = RAN_PORT; + ipv4_rule2.protocol = IPPROTO_TCP; + ipv4_rule2.public_port = RAN_PORT; + + IPADBG("In\n"); + + if ( sep ) + { + ret = ipa_nat_add_ipv4_tbl(pub_ip_add, nat_mem_type, total_entries, &tbl_hdl); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + } + + ret = ipa_nat_add_ipv4_rule(tbl_hdl, &ipv4_rule, &rule_hdl); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_add_ipv4_rule(tbl_hdl, &ipv4_rule1, &rule_hdl1); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_add_ipv4_rule(tbl_hdl, &ipv4_rule2, &rule_hdl2); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_del_ipv4_rule(tbl_hdl, rule_hdl1); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_del_ipv4_rule(tbl_hdl, rule_hdl); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_del_ipv4_rule(tbl_hdl, rule_hdl2); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + if ( sep ) + { + ret = ipa_nat_del_ipv4_tbl(tbl_hdl); + *tbl_hdl_ptr = 0; + CHECK_ERR(ret); + } + + IPADBG("Out\n"); + + return 0; +} diff --git a/qcom/opensource/dataipa/ipanat/test/ipa_nat_test012.c b/qcom/opensource/dataipa/ipanat/test/ipa_nat_test012.c new file mode 100644 index 0000000000..7abe1c7442 --- /dev/null +++ b/qcom/opensource/dataipa/ipanat/test/ipa_nat_test012.c @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2014, 2018-2019 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*=========================================================================*/ +/*! + @file + ipa_nat_test012.cpp + + @brief + Verify the following scenario: + 1. Add ipv4 table + 2. add 3 distinct ipv4 rules + 3. Delete third, second, first + 4. Delete ipv4 table +*/ +/*=========================================================================*/ + +#include "ipa_nat_test.h" + +int ipa_nat_test012( + const char* nat_mem_type, + u32 pub_ip_add, + int total_entries, + u32 tbl_hdl, + int sep, + void* arb_data_ptr) +{ + int* tbl_hdl_ptr = (int*) arb_data_ptr; + int ret; + u32 rule_hdl, rule_hdl1, rule_hdl2; + ipa_nat_ipv4_rule ipv4_rule = {0}, ipv4_rule1 = {0}, ipv4_rule2 = {0}; + + ipv4_rule.target_ip = RAN_ADDR; + ipv4_rule.target_port = RAN_PORT; + ipv4_rule.private_ip = RAN_ADDR; + ipv4_rule.private_port = RAN_PORT; + ipv4_rule.protocol = IPPROTO_TCP; + ipv4_rule.public_port = RAN_PORT; + + ipv4_rule1.target_ip = RAN_ADDR; + ipv4_rule1.target_port = RAN_PORT; + ipv4_rule1.private_ip = RAN_ADDR; + ipv4_rule1.private_port = RAN_PORT; + ipv4_rule1.protocol = IPPROTO_TCP; + ipv4_rule1.public_port = RAN_PORT; + + ipv4_rule2.target_ip = RAN_ADDR; + ipv4_rule2.target_port = RAN_PORT; + ipv4_rule2.private_ip = RAN_ADDR; + ipv4_rule2.private_port = RAN_PORT; + ipv4_rule2.protocol = IPPROTO_TCP; + ipv4_rule2.public_port = RAN_PORT; + + IPADBG("In\n"); + + if ( sep ) + { + ret = ipa_nat_add_ipv4_tbl(pub_ip_add, nat_mem_type, total_entries, &tbl_hdl); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + } + + ret = ipa_nat_add_ipv4_rule(tbl_hdl, &ipv4_rule, &rule_hdl); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_add_ipv4_rule(tbl_hdl, &ipv4_rule1, &rule_hdl1); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_add_ipv4_rule(tbl_hdl, &ipv4_rule2, &rule_hdl2); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_del_ipv4_rule(tbl_hdl, rule_hdl2); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_del_ipv4_rule(tbl_hdl, rule_hdl1); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_del_ipv4_rule(tbl_hdl, rule_hdl); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + if ( sep ) + { + ret = ipa_nat_del_ipv4_tbl(tbl_hdl); + *tbl_hdl_ptr = 0; + CHECK_ERR(ret); + } + + IPADBG("Out\n"); + + return 0; +} diff --git a/qcom/opensource/dataipa/ipanat/test/ipa_nat_test013.c b/qcom/opensource/dataipa/ipanat/test/ipa_nat_test013.c new file mode 100644 index 0000000000..9d37abc327 --- /dev/null +++ b/qcom/opensource/dataipa/ipanat/test/ipa_nat_test013.c @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2014, 2018-2019 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*=========================================================================*/ +/*! + @file + ipa_nat_test013.cpp + + @brief + Verify the following scenario: + 1. Add ipv4 table + 2. add 3 distinct ipv4 rules + 3. Delete third, first and second + 4. Delete ipv4 table +*/ +/*=========================================================================*/ + +#include "ipa_nat_test.h" + +int ipa_nat_test013( + const char* nat_mem_type, + u32 pub_ip_add, + int total_entries, + u32 tbl_hdl, + int sep, + void* arb_data_ptr) +{ + int* tbl_hdl_ptr = (int*) arb_data_ptr; + int ret; + u32 rule_hdl, rule_hdl1, rule_hdl2; + ipa_nat_ipv4_rule ipv4_rule = {0}, ipv4_rule1 = {0}, ipv4_rule2 = {0}; + + ipv4_rule.target_ip = RAN_ADDR; + ipv4_rule.target_port = RAN_PORT; + ipv4_rule.private_ip = RAN_ADDR; + ipv4_rule.private_port = RAN_PORT; + ipv4_rule.protocol = IPPROTO_TCP; + ipv4_rule.public_port = RAN_PORT; + + ipv4_rule1.target_ip = RAN_ADDR; + ipv4_rule1.target_port = RAN_PORT; + ipv4_rule1.private_ip = RAN_ADDR; + ipv4_rule1.private_port = RAN_PORT; + ipv4_rule1.protocol = IPPROTO_TCP; + ipv4_rule1.public_port = RAN_PORT; + + ipv4_rule2.target_ip = RAN_ADDR; + ipv4_rule2.target_port = RAN_PORT; + ipv4_rule2.private_ip = RAN_ADDR; + ipv4_rule2.private_port = RAN_PORT; + ipv4_rule2.protocol = IPPROTO_TCP; + ipv4_rule2.public_port = RAN_PORT; + + IPADBG("In\n"); + + if ( sep ) + { + ret = ipa_nat_add_ipv4_tbl(pub_ip_add, nat_mem_type, total_entries, &tbl_hdl); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + } + + ret = ipa_nat_add_ipv4_rule(tbl_hdl, &ipv4_rule, &rule_hdl); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_add_ipv4_rule(tbl_hdl, &ipv4_rule1, &rule_hdl1); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_add_ipv4_rule(tbl_hdl, &ipv4_rule2, &rule_hdl2); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_del_ipv4_rule(tbl_hdl, rule_hdl2); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_del_ipv4_rule(tbl_hdl, rule_hdl); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_del_ipv4_rule(tbl_hdl, rule_hdl1); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + if ( sep ) + { + ret = ipa_nat_del_ipv4_tbl(tbl_hdl); + *tbl_hdl_ptr = 0; + CHECK_ERR(ret); + } + + IPADBG("Out\n"); + + return 0; +} diff --git a/qcom/opensource/dataipa/ipanat/test/ipa_nat_test014.c b/qcom/opensource/dataipa/ipanat/test/ipa_nat_test014.c new file mode 100644 index 0000000000..12834ea57c --- /dev/null +++ b/qcom/opensource/dataipa/ipanat/test/ipa_nat_test014.c @@ -0,0 +1,102 @@ +/* + * Copyright (c) 2014, 2018-2019 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +/*=========================================================================*/ +/*! + @file + ipa_nat_test014.cpp + @brief + Verify the following scenario: + 1. Add ipv4 table + 2. add same 3 ipv rules + 3. delete first, second and third + 4. Delete ipv4 table +*/ +/*=========================================================================*/ + +#include "ipa_nat_test.h" + +int ipa_nat_test014( + const char* nat_mem_type, + u32 pub_ip_add, + int total_entries, + u32 tbl_hdl, + int sep, + void* arb_data_ptr) +{ + int* tbl_hdl_ptr = (int*) arb_data_ptr; + int ret; + u32 rule_hdl1, rule_hdl2, rule_hdl3; + ipa_nat_ipv4_rule ipv4_rule = {0}; + + ipv4_rule.target_ip = RAN_ADDR; + ipv4_rule.target_port = RAN_PORT; + ipv4_rule.private_ip = RAN_ADDR; + ipv4_rule.private_port = RAN_PORT; + ipv4_rule.protocol = IPPROTO_TCP; + ipv4_rule.public_port = RAN_PORT; + + IPADBG("In\n"); + + if ( sep ) + { + ret = ipa_nat_add_ipv4_tbl(pub_ip_add, nat_mem_type, total_entries, &tbl_hdl); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + } + + ret = ipa_nat_add_ipv4_rule(tbl_hdl, &ipv4_rule, &rule_hdl1); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_add_ipv4_rule(tbl_hdl, &ipv4_rule, &rule_hdl2); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_add_ipv4_rule(tbl_hdl, &ipv4_rule, &rule_hdl3); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_del_ipv4_rule(tbl_hdl, rule_hdl1); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_del_ipv4_rule(tbl_hdl, rule_hdl2); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_del_ipv4_rule(tbl_hdl, rule_hdl3); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + if ( sep ) + { + ret = ipa_nat_del_ipv4_tbl(tbl_hdl); + *tbl_hdl_ptr = 0; + CHECK_ERR(ret); + } + + IPADBG("Out\n"); + + return 0; +} diff --git a/qcom/opensource/dataipa/ipanat/test/ipa_nat_test015.c b/qcom/opensource/dataipa/ipanat/test/ipa_nat_test015.c new file mode 100644 index 0000000000..0195535ae1 --- /dev/null +++ b/qcom/opensource/dataipa/ipanat/test/ipa_nat_test015.c @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2014, 2018-2019 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +/*=========================================================================*/ +/*! + @file + ipa_nat_test015.cpp + + @brief + Verify the following scenario: + 1. Add ipv4 table + 2. add same 3 ipv rules + 3. delete first, third and second + 4. Delete ipv4 table +*/ +/*=========================================================================*/ + +#include "ipa_nat_test.h" + +int ipa_nat_test015( + const char* nat_mem_type, + u32 pub_ip_add, + int total_entries, + u32 tbl_hdl, + int sep, + void* arb_data_ptr) +{ + int* tbl_hdl_ptr = (int*) arb_data_ptr; + int ret; + u32 rule_hdl1, rule_hdl2, rule_hdl3; + ipa_nat_ipv4_rule ipv4_rule = {0}; + + ipv4_rule.target_ip = RAN_ADDR; + ipv4_rule.target_port = RAN_PORT; + + ipv4_rule.private_ip = RAN_ADDR; + ipv4_rule.private_port = RAN_PORT; + ipv4_rule.protocol = IPPROTO_TCP; + ipv4_rule.public_port = RAN_PORT; + + IPADBG("In\n"); + + if ( sep ) + { + ret = ipa_nat_add_ipv4_tbl(pub_ip_add, nat_mem_type, total_entries, &tbl_hdl); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + } + + ret = ipa_nat_add_ipv4_rule(tbl_hdl, &ipv4_rule, &rule_hdl1); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_add_ipv4_rule(tbl_hdl, &ipv4_rule, &rule_hdl2); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_add_ipv4_rule(tbl_hdl, &ipv4_rule, &rule_hdl3); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_del_ipv4_rule(tbl_hdl, rule_hdl1); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_del_ipv4_rule(tbl_hdl, rule_hdl3); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_del_ipv4_rule(tbl_hdl, rule_hdl2); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + if ( sep ) + { + ret = ipa_nat_del_ipv4_tbl(tbl_hdl); + *tbl_hdl_ptr = 0; + CHECK_ERR(ret); + } + + IPADBG("Out\n"); + + return 0; +} diff --git a/qcom/opensource/dataipa/ipanat/test/ipa_nat_test016.c b/qcom/opensource/dataipa/ipanat/test/ipa_nat_test016.c new file mode 100644 index 0000000000..c5d60b028c --- /dev/null +++ b/qcom/opensource/dataipa/ipanat/test/ipa_nat_test016.c @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2014, 2018-2019 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +/*=========================================================================*/ +/*! + @file + ipa_nat_test016.cpp + + @brief + Verify the following scenario: + 1. Add ipv4 table + 2. add same 3 ipv rules + 3. delete second, first and third + 4. Delete ipv4 table +*/ +/*=========================================================================*/ + +#include "ipa_nat_test.h" + +int ipa_nat_test016( + const char* nat_mem_type, + u32 pub_ip_add, + int total_entries, + u32 tbl_hdl, + int sep, + void* arb_data_ptr) +{ + int* tbl_hdl_ptr = (int*) arb_data_ptr; + int ret; + u32 rule_hdl1, rule_hdl2, rule_hdl3; + ipa_nat_ipv4_rule ipv4_rule = {0}; + + ipv4_rule.target_ip = RAN_ADDR; + ipv4_rule.target_port = RAN_PORT; + ipv4_rule.private_ip = RAN_ADDR; + ipv4_rule.private_port = RAN_PORT; + ipv4_rule.protocol = IPPROTO_TCP; + ipv4_rule.public_port = RAN_PORT; + + IPADBG("In\n"); + + if ( sep ) + { + ret = ipa_nat_add_ipv4_tbl(pub_ip_add, nat_mem_type, total_entries, &tbl_hdl); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + } + + ret = ipa_nat_add_ipv4_rule(tbl_hdl, &ipv4_rule, &rule_hdl1); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_add_ipv4_rule(tbl_hdl, &ipv4_rule, &rule_hdl2); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_add_ipv4_rule(tbl_hdl, &ipv4_rule, &rule_hdl3); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_del_ipv4_rule(tbl_hdl, rule_hdl2); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_del_ipv4_rule(tbl_hdl, rule_hdl1); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_del_ipv4_rule(tbl_hdl, rule_hdl3); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + if ( sep ) + { + ret = ipa_nat_del_ipv4_tbl(tbl_hdl); + *tbl_hdl_ptr = 0; + CHECK_ERR(ret); + } + + IPADBG("Out\n"); + + return 0; +} diff --git a/qcom/opensource/dataipa/ipanat/test/ipa_nat_test017.c b/qcom/opensource/dataipa/ipanat/test/ipa_nat_test017.c new file mode 100644 index 0000000000..a3ea014072 --- /dev/null +++ b/qcom/opensource/dataipa/ipanat/test/ipa_nat_test017.c @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2014, 2018-2019 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +/*=========================================================================*/ +/*! + @file + ipa_nat_test017.cpp + + @brief + Verify the following scenario: + 1. Add ipv4 table + 2. add same 3 ipv rules + 3. delete second, third and first + 4. Delete ipv4 table +*/ +/*=========================================================================*/ + +#include "ipa_nat_test.h" + +int ipa_nat_test017( + const char* nat_mem_type, + u32 pub_ip_add, + int total_entries, + u32 tbl_hdl, + int sep, + void* arb_data_ptr) +{ + int* tbl_hdl_ptr = (int*) arb_data_ptr; + int ret; + u32 rule_hdl1, rule_hdl2, rule_hdl3; + ipa_nat_ipv4_rule ipv4_rule = {0}; + + ipv4_rule.target_ip = RAN_ADDR; + ipv4_rule.target_port = RAN_PORT; + ipv4_rule.private_ip = RAN_ADDR; + ipv4_rule.private_port = RAN_PORT; + ipv4_rule.protocol = IPPROTO_TCP; + ipv4_rule.public_port = RAN_PORT; + + IPADBG("In\n"); + + if ( sep ) + { + ret = ipa_nat_add_ipv4_tbl(pub_ip_add, nat_mem_type, total_entries, &tbl_hdl); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + } + + ret = ipa_nat_add_ipv4_rule(tbl_hdl, &ipv4_rule, &rule_hdl1); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_add_ipv4_rule(tbl_hdl, &ipv4_rule, &rule_hdl2); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_add_ipv4_rule(tbl_hdl, &ipv4_rule, &rule_hdl3); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_del_ipv4_rule(tbl_hdl, rule_hdl2); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_del_ipv4_rule(tbl_hdl, rule_hdl3); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_del_ipv4_rule(tbl_hdl, rule_hdl1); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + if ( sep ) + { + ret = ipa_nat_del_ipv4_tbl(tbl_hdl); + *tbl_hdl_ptr = 0; + CHECK_ERR(ret); + } + + IPADBG("Out\n"); + + return 0; +} diff --git a/qcom/opensource/dataipa/ipanat/test/ipa_nat_test018.c b/qcom/opensource/dataipa/ipanat/test/ipa_nat_test018.c new file mode 100644 index 0000000000..63cbfacdda --- /dev/null +++ b/qcom/opensource/dataipa/ipanat/test/ipa_nat_test018.c @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2014, 2018-2019 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +/*=========================================================================*/ +/*! + @file + ipa_nat_test018.c + + @brief + Verify the following scenario: + 1. Add ipv4 table + 2. add same 3 ipv rules + 3. delete third, second and first + 4. Delete ipv4 table +*/ +/*=========================================================================*/ + +#include "ipa_nat_test.h" + +int ipa_nat_test018( + const char* nat_mem_type, + u32 pub_ip_add, + int total_entries, + u32 tbl_hdl, + int sep, + void* arb_data_ptr) +{ + int* tbl_hdl_ptr = (int*) arb_data_ptr; + int ret; + u32 rule_hdl1, rule_hdl2, rule_hdl3; + ipa_nat_ipv4_rule ipv4_rule = {0}; + + ipv4_rule.target_ip = RAN_ADDR; + ipv4_rule.target_port = RAN_PORT; + ipv4_rule.private_ip = RAN_ADDR; + ipv4_rule.private_port = RAN_PORT; + ipv4_rule.protocol = IPPROTO_TCP; + ipv4_rule.public_port = RAN_PORT; + + IPADBG("In\n"); + + if ( sep ) + { + ret = ipa_nat_add_ipv4_tbl(pub_ip_add, nat_mem_type, total_entries, &tbl_hdl); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + } + + ret = ipa_nat_add_ipv4_rule(tbl_hdl, &ipv4_rule, &rule_hdl1); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_add_ipv4_rule(tbl_hdl, &ipv4_rule, &rule_hdl2); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_add_ipv4_rule(tbl_hdl, &ipv4_rule, &rule_hdl3); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_del_ipv4_rule(tbl_hdl, rule_hdl3); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_del_ipv4_rule(tbl_hdl, rule_hdl2); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_del_ipv4_rule(tbl_hdl, rule_hdl1); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + if ( sep ) + { + ret = ipa_nat_del_ipv4_tbl(tbl_hdl); + *tbl_hdl_ptr = 0; + CHECK_ERR(ret); + } + + IPADBG("Out\n"); + + return 0; +} diff --git a/qcom/opensource/dataipa/ipanat/test/ipa_nat_test019.c b/qcom/opensource/dataipa/ipanat/test/ipa_nat_test019.c new file mode 100644 index 0000000000..a6d700f946 --- /dev/null +++ b/qcom/opensource/dataipa/ipanat/test/ipa_nat_test019.c @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2014, 2018-2019 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +/*=========================================================================*/ +/*! + @file + ipa_nat_test019.c + + @brief + Verify the following scenario: + 1. Add ipv4 table + 2. add same 3 ipv rules + 3. delete third, first and second + 4. Delete ipv4 table +*/ +/*=========================================================================*/ + +#include "ipa_nat_test.h" + +int ipa_nat_test019( + const char* nat_mem_type, + u32 pub_ip_add, + int total_entries, + u32 tbl_hdl, + int sep, + void* arb_data_ptr) +{ + int* tbl_hdl_ptr = (int*) arb_data_ptr; + int ret; + u32 rule_hdl1, rule_hdl2, rule_hdl3; + ipa_nat_ipv4_rule ipv4_rule = {0}; + + ipv4_rule.target_ip = RAN_ADDR; + ipv4_rule.target_port = RAN_PORT; + ipv4_rule.private_ip = RAN_ADDR; + ipv4_rule.private_port = RAN_PORT; + ipv4_rule.protocol = IPPROTO_TCP; + ipv4_rule.public_port = RAN_PORT; + + IPADBG("In\n"); + + if ( sep ) + { + ret = ipa_nat_add_ipv4_tbl(pub_ip_add, nat_mem_type, total_entries, &tbl_hdl); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + } + + ret = ipa_nat_add_ipv4_rule(tbl_hdl, &ipv4_rule, &rule_hdl1); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_add_ipv4_rule(tbl_hdl, &ipv4_rule, &rule_hdl2); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_add_ipv4_rule(tbl_hdl, &ipv4_rule, &rule_hdl3); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_del_ipv4_rule(tbl_hdl, rule_hdl3); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_del_ipv4_rule(tbl_hdl, rule_hdl1); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_del_ipv4_rule(tbl_hdl, rule_hdl2); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + if ( sep ) + { + ret = ipa_nat_del_ipv4_tbl(tbl_hdl); + *tbl_hdl_ptr = 0; + CHECK_ERR(ret); + } + + IPADBG("Out\n"); + + return 0; +} diff --git a/qcom/opensource/dataipa/ipanat/test/ipa_nat_test020.c b/qcom/opensource/dataipa/ipanat/test/ipa_nat_test020.c new file mode 100644 index 0000000000..e9f89a8c9e --- /dev/null +++ b/qcom/opensource/dataipa/ipanat/test/ipa_nat_test020.c @@ -0,0 +1,108 @@ +/* + * Copyright (c) 2014, 2018-2019 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*=========================================================================*/ +/*! + @file + ipa_nat_test020.c + + @brief + Verify the following scenario: + 1. Add ipv4 table + 2. add same 4 ipv rules + 3. delete third, second, fourth and first + 4. Delete ipv4 table +*/ +/*=========================================================================*/ + +#include "ipa_nat_test.h" + +int ipa_nat_test020( + const char* nat_mem_type, + u32 pub_ip_add, + int total_entries, + u32 tbl_hdl, + int sep, + void* arb_data_ptr) +{ + int* tbl_hdl_ptr = (int*) arb_data_ptr; + int ret; + u32 rule_hdl1, rule_hdl2, rule_hdl3, rule_hdl4; + ipa_nat_ipv4_rule ipv4_rule = {0}; + + ipv4_rule.target_ip = RAN_ADDR; + ipv4_rule.target_port = RAN_PORT; + ipv4_rule.private_ip = RAN_ADDR; + ipv4_rule.private_port = RAN_PORT; + ipv4_rule.protocol = IPPROTO_TCP; + ipv4_rule.public_port = RAN_PORT; + + IPADBG("In\n"); + + if ( sep ) + { + ret = ipa_nat_add_ipv4_tbl(pub_ip_add, nat_mem_type, total_entries, &tbl_hdl); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + } + + ret = ipa_nat_add_ipv4_rule(tbl_hdl, &ipv4_rule, &rule_hdl1); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_add_ipv4_rule(tbl_hdl, &ipv4_rule, &rule_hdl2); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_add_ipv4_rule(tbl_hdl, &ipv4_rule, &rule_hdl3); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_add_ipv4_rule(tbl_hdl, &ipv4_rule, &rule_hdl4); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_del_ipv4_rule(tbl_hdl, rule_hdl3); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_del_ipv4_rule(tbl_hdl, rule_hdl2); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_del_ipv4_rule(tbl_hdl, rule_hdl4); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_del_ipv4_rule(tbl_hdl, rule_hdl1); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + if ( sep ) + { + ret = ipa_nat_del_ipv4_tbl(tbl_hdl); + *tbl_hdl_ptr = 0; + CHECK_ERR(ret); + } + + IPADBG("Out\n"); + + return 0; +} diff --git a/qcom/opensource/dataipa/ipanat/test/ipa_nat_test021.c b/qcom/opensource/dataipa/ipanat/test/ipa_nat_test021.c new file mode 100644 index 0000000000..abe712d26e --- /dev/null +++ b/qcom/opensource/dataipa/ipanat/test/ipa_nat_test021.c @@ -0,0 +1,125 @@ +/* + * Copyright (c) 2014-2019 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +/*=========================================================================*/ +/*! + @file + ipa_nat_test021.cpp + + @brief + Verify the following scenario: + 1. Add ipv4 table + 2. add same 3 ipv rules + 3. delete Head and last entry + 4. add 2 new same ip4 entries + 5. Add head entry again + 6. Delete ipv4 table +*/ +/*=========================================================================*/ + +#include "ipa_nat_test.h" + +int ipa_nat_test021( + const char* nat_mem_type, + u32 pub_ip_add, + int total_entries, + u32 tbl_hdl, + int sep, + void* arb_data_ptr) +{ + int* tbl_hdl_ptr = (int*) arb_data_ptr; + int ret; + u32 rule_hdl1, rule_hdl2, rule_hdl3; + ipa_nat_ipv4_rule ipv4_rule = {0}, ipv4_rule2 = {0}; + u32 rule_hdl21, rule_hdl22; + + /* Rule 1 */ + ipv4_rule.target_ip = RAN_ADDR; + ipv4_rule.target_port = RAN_PORT; + ipv4_rule.private_ip = RAN_ADDR; + ipv4_rule.private_port = RAN_PORT; + ipv4_rule.protocol = IPPROTO_TCP; + ipv4_rule.public_port = RAN_PORT; + + /* Rule 2*/ + ipv4_rule.target_ip = RAN_ADDR; + ipv4_rule.target_port = RAN_PORT; + ipv4_rule.private_ip = RAN_ADDR; + ipv4_rule.private_port = RAN_PORT; + ipv4_rule.protocol = IPPROTO_UDP; + ipv4_rule.public_port = RAN_PORT; + + IPADBG("In\n"); + + if ( sep ) + { + ret = ipa_nat_add_ipv4_tbl(pub_ip_add, nat_mem_type, total_entries, &tbl_hdl); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + } + + ret = ipa_nat_add_ipv4_rule(tbl_hdl, &ipv4_rule, &rule_hdl1); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_add_ipv4_rule(tbl_hdl, &ipv4_rule, &rule_hdl2); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_add_ipv4_rule(tbl_hdl, &ipv4_rule, &rule_hdl3); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + /* Delete head entry */ + ret = ipa_nat_del_ipv4_rule(tbl_hdl, rule_hdl1); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + /* Delete Last Entry */ + ret = ipa_nat_del_ipv4_rule(tbl_hdl, rule_hdl3); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + /* Add 2 different Entries */ + ret = ipa_nat_add_ipv4_rule(tbl_hdl, &ipv4_rule2, &rule_hdl21); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nat_add_ipv4_rule(tbl_hdl, &ipv4_rule2, &rule_hdl22); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + /* Add first entry again */ + ret = ipa_nat_add_ipv4_rule(tbl_hdl, &ipv4_rule, &rule_hdl3); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + if ( sep ) + { + ret = ipa_nat_del_ipv4_tbl(tbl_hdl); + *tbl_hdl_ptr = 0; + CHECK_ERR(ret); + } + + IPADBG("Out\n"); + + return 0; +} diff --git a/qcom/opensource/dataipa/ipanat/test/ipa_nat_test022.c b/qcom/opensource/dataipa/ipanat/test/ipa_nat_test022.c new file mode 100644 index 0000000000..fdf1efc6b3 --- /dev/null +++ b/qcom/opensource/dataipa/ipanat/test/ipa_nat_test022.c @@ -0,0 +1,299 @@ +/* + * Copyright (c) 2014, 2018-2019 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*=========================================================================*/ +/*! + @file + ipa_nat_test022.c + + @brief + Note: Verify the following scenario: + 1. Add ipv4 table + 2. Add ipv4 rules till filled + 3. Print stats + 4. Delete ipv4 table +*/ +/*=========================================================================*/ + +#include "ipa_nat_test.h" + +int ipa_nat_test022( + const char* nat_mem_type, + u32 pub_ip_add, + int total_entries, + u32 tbl_hdl, + int sep, + void* arb_data_ptr) +{ + int* tbl_hdl_ptr = (int*) arb_data_ptr; + + ipa_nat_ipv4_rule ipv4_rule; + u32 rule_hdls[2048]; + + ipa_nati_tbl_stats nstats, last_nstats; + ipa_nati_tbl_stats istats, last_istats; + + u32 i, tot; + + bool switched = false; + + const char* mem_type; + + int ret; + + IPADBG("In\n"); + + if ( sep ) + { + ret = ipa_nat_add_ipv4_tbl(pub_ip_add, nat_mem_type, total_entries, &tbl_hdl); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + } + + ret = ipa_nati_clear_ipv4_tbl(tbl_hdl); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nati_ipv4_tbl_stats(tbl_hdl, &nstats, &istats); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + IPAINFO("Attempting rule adds to %s table of size: (%u)\n", + ipa3_nat_mem_in_as_str(nstats.nmi), + nstats.tot_ents); + + last_nstats = nstats; + last_istats = istats; + + memset(rule_hdls, 0, sizeof(rule_hdls)); + + for ( i = tot = 0; i < array_sz(rule_hdls); i++ ) + { + IPADBG("Trying %d ipa_nat_add_ipv4_rule()\n", i); + + memset(&ipv4_rule, 0, sizeof(ipv4_rule)); + + ipv4_rule.protocol = IPPROTO_TCP; + ipv4_rule.public_port = RAN_PORT; + ipv4_rule.target_ip = RAN_ADDR; + ipv4_rule.target_port = RAN_PORT; + ipv4_rule.private_ip = RAN_ADDR; + ipv4_rule.private_port = RAN_PORT; + + ret = ipa_nat_add_ipv4_rule(tbl_hdl, &ipv4_rule, &rule_hdls[i]); + CHECK_ERR_TBL_ACTION(ret, tbl_hdl, break); + + IPADBG("Success %d ipa_nat_add_ipv4_rule() -> rule_hdl(0x%08X)\n", + i, rule_hdls[i]); + + ret = ipa_nati_ipv4_tbl_stats(tbl_hdl, &nstats, &istats); + CHECK_ERR_TBL_ACTION(ret, tbl_hdl, break); + + /* + * Are we in hybrid mode and have we switched memory type? + * Check for it and print the appropriate stats. + */ + if ( nstats.nmi != last_nstats.nmi ) + { + mem_type = ipa3_nat_mem_in_as_str(last_nstats.nmi); + + switched = true; + + /* + * NAT table stats... + */ + IPAINFO("Able to add (%u) records to %s " + "NAT table of size (%u) or (%f) percent\n", + tot, + mem_type, + last_nstats.tot_ents, + ((float) tot / (float) last_nstats.tot_ents) * 100.0); + + IPAINFO("Able to add (%u) records to %s " + "NAT BASE table of size (%u) or (%f) percent\n", + last_nstats.tot_base_ents_filled, + mem_type, + last_nstats.tot_base_ents, + ((float) last_nstats.tot_base_ents_filled / + (float) last_nstats.tot_base_ents) * 100.0); + + IPAINFO("Able to add (%u) records to %s " + "NAT EXPN table of size (%u) or (%f) percent\n", + last_nstats.tot_expn_ents_filled, + mem_type, + last_nstats.tot_expn_ents, + ((float) last_nstats.tot_expn_ents_filled / + (float) last_nstats.tot_expn_ents) * 100.0); + + IPAINFO("%s NAT table chains: tot_chains(%u) min_len(%u) max_len(%u) avg_len(%f)\n", + mem_type, + last_nstats.tot_chains, + last_nstats.min_chain_len, + last_nstats.max_chain_len, + last_nstats.avg_chain_len); + + /* + * INDEX table stats... + */ + IPAINFO("Able to add (%u) records to %s " + "IDX table of size (%u) or (%f) percent\n", + tot, + mem_type, + last_istats.tot_ents, + ((float) tot / (float) last_istats.tot_ents) * 100.0); + + IPAINFO("Able to add (%u) records to %s " + "IDX BASE table of size (%u) or (%f) percent\n", + last_istats.tot_base_ents_filled, + mem_type, + last_istats.tot_base_ents, + ((float) last_istats.tot_base_ents_filled / + (float) last_istats.tot_base_ents) * 100.0); + + IPAINFO("Able to add (%u) records to %s " + "IDX EXPN table of size (%u) or (%f) percent\n", + last_istats.tot_expn_ents_filled, + mem_type, + last_istats.tot_expn_ents, + ((float) last_istats.tot_expn_ents_filled / + (float) last_istats.tot_expn_ents) * 100.0); + + IPAINFO("%s IDX table chains: tot_chains(%u) min_len(%u) max_len(%u) avg_len(%f)\n", + mem_type, + last_istats.tot_chains, + last_istats.min_chain_len, + last_istats.max_chain_len, + last_istats.avg_chain_len); + } + + last_nstats = nstats; + last_istats = istats; + + if ( switched ) + { + switched = false; + + IPAINFO("Continuing rule adds to %s table of size: (%u)\n", + ipa3_nat_mem_in_as_str(nstats.nmi), + nstats.tot_ents); + } + + tot++; + } + + ret = ipa_nati_ipv4_tbl_stats(tbl_hdl, &nstats, &istats); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + mem_type = ipa3_nat_mem_in_as_str(nstats.nmi); + + /* + * NAT table stats... + */ + IPAINFO("Able to add (%u) records to %s " + "NAT table of size (%u) or (%f) percent\n", + tot, + mem_type, + nstats.tot_ents, + ((float) tot / (float) nstats.tot_ents) * 100.0); + + IPAINFO("Able to add (%u) records to %s " + "NAT BASE table of size (%u) or (%f) percent\n", + nstats.tot_base_ents_filled, + mem_type, + nstats.tot_base_ents, + ((float) nstats.tot_base_ents_filled / + (float) nstats.tot_base_ents) * 100.0); + + IPAINFO("Able to add (%u) records to %s " + "NAT EXPN table of size (%u) or (%f) percent\n", + nstats.tot_expn_ents_filled, + mem_type, + nstats.tot_expn_ents, + ((float) nstats.tot_expn_ents_filled / + (float) nstats.tot_expn_ents) * 100.0); + + IPAINFO("%s NAT table chains: tot_chains(%u) min_len(%u) max_len(%u) avg_len(%f)\n", + mem_type, + nstats.tot_chains, + nstats.min_chain_len, + nstats.max_chain_len, + nstats.avg_chain_len); + + /* + * INDEX table stats... + */ + IPAINFO("Able to add (%u) records to %s " + "IDX table of size (%u) or (%f) percent\n", + tot, + mem_type, + istats.tot_ents, + ((float) tot / (float) istats.tot_ents) * 100.0); + + IPAINFO("Able to add (%u) records to %s " + "IDX BASE table of size (%u) or (%f) percent\n", + istats.tot_base_ents_filled, + mem_type, + istats.tot_base_ents, + ((float) istats.tot_base_ents_filled / + (float) istats.tot_base_ents) * 100.0); + + IPAINFO("Able to add (%u) records to %s " + "IDX EXPN table of size (%u) or (%f) percent\n", + istats.tot_expn_ents_filled, + mem_type, + istats.tot_expn_ents, + ((float) istats.tot_expn_ents_filled / + (float) istats.tot_expn_ents) * 100.0); + + IPAINFO("%s IDX table chains: tot_chains(%u) min_len(%u) max_len(%u) avg_len(%f)\n", + mem_type, + istats.tot_chains, + istats.min_chain_len, + istats.max_chain_len, + istats.avg_chain_len); + + IPAINFO("Deleting all rules\n"); + + for ( i = 0; i < tot; i++ ) + { + IPADBG("Trying %d ipa_nat_del_ipv4_rule(0x%08X)\n", + i, rule_hdls[i]); + ret = ipa_nat_del_ipv4_rule(tbl_hdl, rule_hdls[i]); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + IPADBG("Success ipa_nat_del_ipv4_rule(%d)\n", i); + } + + if ( sep ) + { + ret = ipa_nat_del_ipv4_tbl(tbl_hdl); + *tbl_hdl_ptr = 0; + CHECK_ERR(ret); + } + + IPADBG("Out\n"); + + return 0; +} diff --git a/qcom/opensource/dataipa/ipanat/test/ipa_nat_test023.c b/qcom/opensource/dataipa/ipanat/test/ipa_nat_test023.c new file mode 100644 index 0000000000..7a42247282 --- /dev/null +++ b/qcom/opensource/dataipa/ipanat/test/ipa_nat_test023.c @@ -0,0 +1,134 @@ +/* + * Copyright (c) 2019 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*=========================================================================*/ +/*! + @file + ipa_nat_test023.c + + @brief + Verify the following scenario: + 1. Add ipv4 table + 2. Add ipv rule three times to cause collisions and linking + 3. Delete rules in a particular order and observe list for expected + form + 4. Run 2 and 3 over and over until all delete cominations have been + run + 5. Delete ipv4 table +*/ +/*=========================================================================*/ + +#include "ipa_nat_test.h" + +int ipa_nat_test023( + const char* nat_mem_type, + u32 pub_ip_add, + int total_entries, + u32 tbl_hdl, + int sep, + void* arb_data_ptr) +{ + int* tbl_hdl_ptr = (int*) arb_data_ptr; + + ipa_nat_ipv4_rule ipv4_rule = {0}; + + u32 rule_hdl1; + u32 rule_hdl2; + u32 rule_hdl3; + + u32* rule_del_combos[6][3] = { + { &rule_hdl1, &rule_hdl2, &rule_hdl3 }, + { &rule_hdl1, &rule_hdl3, &rule_hdl2 }, + + { &rule_hdl2, &rule_hdl1, &rule_hdl3 }, + { &rule_hdl2, &rule_hdl3, &rule_hdl1 }, + + { &rule_hdl3, &rule_hdl1, &rule_hdl2 }, + { &rule_hdl3, &rule_hdl2, &rule_hdl1 }, + }; + + int i, j, ret; + + ipv4_rule.target_ip = RAN_ADDR; + ipv4_rule.target_port = RAN_PORT; + ipv4_rule.private_ip = RAN_ADDR; + ipv4_rule.private_port = RAN_PORT; + ipv4_rule.protocol = IPPROTO_TCP; + ipv4_rule.public_port = RAN_PORT; + + IPADBG("In\n"); + + if ( sep ) + { + ret = ipa_nat_add_ipv4_tbl(pub_ip_add, nat_mem_type, total_entries, &tbl_hdl); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + } + + for ( i = 0; i < 6; i++ ) + { + IPADBG("Adding rule 1\n"); + ret = ipa_nat_add_ipv4_rule(tbl_hdl, &ipv4_rule, &rule_hdl1); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + IPADBG("Adding rule 2\n"); + ret = ipa_nat_add_ipv4_rule(tbl_hdl, &ipv4_rule, &rule_hdl2); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + IPADBG("Adding rule 3\n"); + ret = ipa_nat_add_ipv4_rule(tbl_hdl, &ipv4_rule, &rule_hdl3); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ipa_nat_dump_ipv4_table(tbl_hdl); + + for ( j = 0; j < 3; j++ ) + { + u32* rh_ptr = rule_del_combos[i][j]; + + IPADBG("Deleting rule %u\n", + ( rh_ptr == &rule_hdl1 ) ? 1 : + ( rh_ptr == &rule_hdl2 ) ? 2 : 3); + + ret = ipa_nat_del_ipv4_rule(tbl_hdl, *rh_ptr); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ipa_nat_dump_ipv4_table(tbl_hdl); + } + } + + if ( sep ) + { + ret = ipa_nat_del_ipv4_tbl(tbl_hdl); + *tbl_hdl_ptr = 0; + CHECK_ERR(ret); + } + + IPADBG("Out\n"); + + return 0; +} diff --git a/qcom/opensource/dataipa/ipanat/test/ipa_nat_test024.c b/qcom/opensource/dataipa/ipanat/test/ipa_nat_test024.c new file mode 100644 index 0000000000..aeb1af4e66 --- /dev/null +++ b/qcom/opensource/dataipa/ipanat/test/ipa_nat_test024.c @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2019 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*=========================================================================*/ +/*! + @file + ipa_nat_test024.c + + @brief + Verify the following scenario: + 1. Trigger thousands of table memory switches + +*/ +/*===========================================================================*/ + +#include "ipa_nat_test.h" + +int ipa_nat_test024( + const char* nat_mem_type, + u32 pub_ip_add, + int total_entries, + u32 tbl_hdl, + int sep, + void* arb_data_ptr) +{ + int* tbl_hdl_ptr = (int*) arb_data_ptr; + + int i, ret; + + IPADBG("In\n"); + + if ( sep ) + { + ret = ipa_nat_add_ipv4_tbl(pub_ip_add, nat_mem_type, total_entries, &tbl_hdl); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + } + + for ( i = 0; i < 1000; i++ ) + { + ret = ipa_nat_test022( + nat_mem_type, pub_ip_add, total_entries, tbl_hdl, !sep, arb_data_ptr); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + } + + if ( sep ) + { + ret = ipa_nat_del_ipv4_tbl(tbl_hdl); + *tbl_hdl_ptr = 0; + CHECK_ERR(ret); + } + + IPADBG("Out\n"); + + return 0; +} diff --git a/qcom/opensource/dataipa/ipanat/test/ipa_nat_test025.c b/qcom/opensource/dataipa/ipanat/test/ipa_nat_test025.c new file mode 100644 index 0000000000..71ddebe2a7 --- /dev/null +++ b/qcom/opensource/dataipa/ipanat/test/ipa_nat_test025.c @@ -0,0 +1,362 @@ +/* + * Copyright (c) 2019 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*=========================================================================*/ +/*! + @file + ipa_nat_test025.c + + @brief + Note: Verify the following scenario: + 1. Similare to test022, but with random deletes during adds +*/ +/*=========================================================================*/ + +#include "ipa_nat_test.h" + +#undef VALID_RULE +#define VALID_RULE(r) ((r) != 0 && (r) != 0xFFFFFFFF) + +#undef GET_MAX +#define GET_MAX(ram, rdm) \ + do { \ + while ( (ram = rand() % 20) < 4); \ + while ( (rdm = rand() % 10) >= ram || rdm == 0 ); \ + IPADBG("rand_adds_max(%u) rand_dels_max(%u)\n", ram, rdm); \ + } while (0) + +int ipa_nat_test025( + const char* nat_mem_type, + u32 pub_ip_add, + int total_entries, + u32 tbl_hdl, + int sep, + void* arb_data_ptr) +{ + int* tbl_hdl_ptr = (int*) arb_data_ptr; + + ipa_nat_ipv4_rule ipv4_rule; + u32 rule_hdls[1024]; + + ipa_nati_tbl_stats nstats, last_nstats; + ipa_nati_tbl_stats istats, last_istats; + + u32 i; + u32 rand_adds_max, rand_dels_max; + u32 tot, tot_added, tot_deleted; + + bool switched = false; + + const char* mem_type; + + int ret; + + IPADBG("In\n"); + + if ( sep ) + { + ret = ipa_nat_add_ipv4_tbl(pub_ip_add, nat_mem_type, total_entries, &tbl_hdl); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + } + + ret = ipa_nati_clear_ipv4_tbl(tbl_hdl); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + ret = ipa_nati_ipv4_tbl_stats(tbl_hdl, &nstats, &istats); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + IPAINFO("Attempting rule adds to %s table of size: (%u)\n", + ipa3_nat_mem_in_as_str(nstats.nmi), + nstats.tot_ents); + + last_nstats = nstats; + last_istats = istats; + + memset(rule_hdls, 0, sizeof(rule_hdls)); + + GET_MAX(rand_adds_max, rand_dels_max); + + tot = tot_added = tot_deleted = 0; + + for ( i = 0; i < array_sz(rule_hdls); i++ ) + { + IPADBG("Trying %u ipa_nat_add_ipv4_rule()\n", i); + + memset(&ipv4_rule, 0, sizeof(ipv4_rule)); + + ipv4_rule.protocol = IPPROTO_TCP; + ipv4_rule.public_port = RAN_PORT; + ipv4_rule.target_ip = RAN_ADDR; + ipv4_rule.target_port = RAN_PORT; + ipv4_rule.private_ip = RAN_ADDR; + ipv4_rule.private_port = RAN_PORT; + + ret = ipa_nat_add_ipv4_rule(tbl_hdl, &ipv4_rule, &rule_hdls[i]); + CHECK_ERR_TBL_ACTION(ret, tbl_hdl, break); + + IPADBG("Success %u ipa_nat_add_ipv4_rule() -> rule_hdl(0x%08X)\n", + i, rule_hdls[i]); + + ret = ipa_nati_ipv4_tbl_stats(tbl_hdl, &nstats, &istats); + CHECK_ERR_TBL_ACTION(ret, tbl_hdl, break); + + /* + * Are we in hybrid mode and have we switched memory type? + * Check for it and print the appropriate stats. + */ + if ( nstats.nmi != last_nstats.nmi ) + { + mem_type = ipa3_nat_mem_in_as_str(last_nstats.nmi); + + switched = true; + + /* + * NAT table stats... + */ + IPAINFO("Able to add (%u) records to %s " + "NAT table of size (%u) or (%f) percent\n", + tot, + mem_type, + last_nstats.tot_ents, + ((float) tot / (float) last_nstats.tot_ents) * 100.0); + + IPAINFO("Able to add (%u) records to %s " + "NAT BASE table of size (%u) or (%f) percent\n", + last_nstats.tot_base_ents_filled, + mem_type, + last_nstats.tot_base_ents, + ((float) last_nstats.tot_base_ents_filled / + (float) last_nstats.tot_base_ents) * 100.0); + + IPAINFO("Able to add (%u) records to %s " + "NAT EXPN table of size (%u) or (%f) percent\n", + last_nstats.tot_expn_ents_filled, + mem_type, + last_nstats.tot_expn_ents, + ((float) last_nstats.tot_expn_ents_filled / + (float) last_nstats.tot_expn_ents) * 100.0); + + IPAINFO("%s NAT table chains: tot_chains(%u) min_len(%u) max_len(%u) avg_len(%f)\n", + mem_type, + last_nstats.tot_chains, + last_nstats.min_chain_len, + last_nstats.max_chain_len, + last_nstats.avg_chain_len); + + /* + * INDEX table stats... + */ + IPAINFO("Able to add (%u) records to %s " + "IDX table of size (%u) or (%f) percent\n", + tot, + mem_type, + last_istats.tot_ents, + ((float) tot / (float) last_istats.tot_ents) * 100.0); + + IPAINFO("Able to add (%u) records to %s " + "IDX BASE table of size (%u) or (%f) percent\n", + last_istats.tot_base_ents_filled, + mem_type, + last_istats.tot_base_ents, + ((float) last_istats.tot_base_ents_filled / + (float) last_istats.tot_base_ents) * 100.0); + + IPAINFO("Able to add (%u) records to %s " + "IDX EXPN table of size (%u) or (%f) percent\n", + last_istats.tot_expn_ents_filled, + mem_type, + last_istats.tot_expn_ents, + ((float) last_istats.tot_expn_ents_filled / + (float) last_istats.tot_expn_ents) * 100.0); + + IPAINFO("%s IDX table chains: tot_chains(%u) min_len(%u) max_len(%u) avg_len(%f)\n", + mem_type, + last_istats.tot_chains, + last_istats.min_chain_len, + last_istats.max_chain_len, + last_istats.avg_chain_len); + } + + last_nstats = nstats; + last_istats = istats; + + tot++; + + if ( ++tot_added == rand_adds_max ) + { + u32 j, k; + u32* hdl_ptr[tot]; + + for ( j = k = 0; j < array_sz(rule_hdls); j++ ) + { + if ( VALID_RULE(rule_hdls[j]) ) + { + hdl_ptr[k] = &(rule_hdls[j]); + + if ( ++k == tot ) + { + break; + } + } + } + + IPADBG("About to delete %u rules\n", rand_dels_max); + + while ( k ) + { + while ( j = rand() % k, ! VALID_RULE(*(hdl_ptr[j])) ); + + IPADBG("Trying ipa_nat_del_ipv4_rule(0x%08X)\n", + *(hdl_ptr[j])); + + ret = ipa_nat_del_ipv4_rule(tbl_hdl, *(hdl_ptr[j])); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + IPADBG("Success ipa_nat_del_ipv4_rule(0x%08X)\n", *(hdl_ptr[j])); + + *(hdl_ptr[j]) = 0xFFFFFFFF; + + --tot; + + if ( ++tot_deleted == rand_dels_max ) + { + break; + } + } + + GET_MAX(rand_adds_max, rand_dels_max); + + tot_added = tot_deleted = 0; + } + + if ( switched ) + { + switched = false; + + IPAINFO("Continuing rule adds to %s table of size: (%u)\n", + ipa3_nat_mem_in_as_str(nstats.nmi), + nstats.tot_ents); + } + } + + ret = ipa_nati_ipv4_tbl_stats(tbl_hdl, &nstats, &istats); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + mem_type = ipa3_nat_mem_in_as_str(nstats.nmi); + + /* + * NAT table stats... + */ + IPAINFO("Able to add (%u) records to %s " + "NAT table of size (%u) or (%f) percent\n", + tot, + mem_type, + nstats.tot_ents, + ((float) tot / (float) nstats.tot_ents) * 100.0); + + IPAINFO("Able to add (%u) records to %s " + "NAT BASE table of size (%u) or (%f) percent\n", + nstats.tot_base_ents_filled, + mem_type, + nstats.tot_base_ents, + ((float) nstats.tot_base_ents_filled / + (float) nstats.tot_base_ents) * 100.0); + + IPAINFO("Able to add (%u) records to %s " + "NAT EXPN table of size (%u) or (%f) percent\n", + nstats.tot_expn_ents_filled, + mem_type, + nstats.tot_expn_ents, + ((float) nstats.tot_expn_ents_filled / + (float) nstats.tot_expn_ents) * 100.0); + + IPAINFO("%s NAT table chains: tot_chains(%u) min_len(%u) max_len(%u) avg_len(%f)\n", + mem_type, + nstats.tot_chains, + nstats.min_chain_len, + nstats.max_chain_len, + nstats.avg_chain_len); + + /* + * INDEX table stats... + */ + IPAINFO("Able to add (%u) records to %s " + "IDX table of size (%u) or (%f) percent\n", + tot, + mem_type, + istats.tot_ents, + ((float) tot / (float) istats.tot_ents) * 100.0); + + IPAINFO("Able to add (%u) records to %s " + "IDX BASE table of size (%u) or (%f) percent\n", + istats.tot_base_ents_filled, + mem_type, + istats.tot_base_ents, + ((float) istats.tot_base_ents_filled / + (float) istats.tot_base_ents) * 100.0); + + IPAINFO("Able to add (%u) records to %s " + "IDX EXPN table of size (%u) or (%f) percent\n", + istats.tot_expn_ents_filled, + mem_type, + istats.tot_expn_ents, + ((float) istats.tot_expn_ents_filled / + (float) istats.tot_expn_ents) * 100.0); + + IPAINFO("%s IDX table chains: tot_chains(%u) min_len(%u) max_len(%u) avg_len(%f)\n", + mem_type, + istats.tot_chains, + istats.min_chain_len, + istats.max_chain_len, + istats.avg_chain_len); + + IPAINFO("Deleting remaining rules\n"); + + for ( i = 0; i < array_sz(rule_hdls); i++ ) + { + if ( VALID_RULE(rule_hdls[i]) ) + { + IPADBG("Trying ipa_nat_del_ipv4_rule(0x%08X)\n", + rule_hdls[i]); + ret = ipa_nat_del_ipv4_rule(tbl_hdl, rule_hdls[i]); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + IPADBG("Success ipa_nat_del_ipv4_rule(%u)\n", rule_hdls[i]); + } + } + + if ( sep ) + { + ret = ipa_nat_del_ipv4_tbl(tbl_hdl); + *tbl_hdl_ptr = 0; + CHECK_ERR(ret); + } + + IPADBG("Out\n"); + + return 0; +} diff --git a/qcom/opensource/dataipa/ipanat/test/ipa_nat_test999.c b/qcom/opensource/dataipa/ipanat/test/ipa_nat_test999.c new file mode 100644 index 0000000000..ba213d8f3b --- /dev/null +++ b/qcom/opensource/dataipa/ipanat/test/ipa_nat_test999.c @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2019 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*=========================================================================*/ +/*! + @file + ipa_nat_test999.c + + @brief + Verify the following scenario: + 1. Delete ipv4 table +*/ +/*===========================================================================*/ + +#include "ipa_nat_test.h" + +int ipa_nat_test999( + const char* nat_mem_type, + u32 pub_ip_add, + int total_entries, + u32 tbl_hdl, + int sep, + void* arb_data_ptr) +{ + int* tbl_hdl_ptr = (int*) arb_data_ptr; + int ret; + + IPADBG("In\n"); + + if ( ! sep ) + { + IPADBG("calling ipa_nat_del_ipv4_tbl()\n"); + + ret = ipa_nat_del_ipv4_tbl(tbl_hdl); + + *tbl_hdl_ptr = 0; + + CHECK_ERR(ret); + + IPADBG("deleted ipv4 nat table successfully.\n"); + } + + IPADBG("Out\n"); + + return 0; +} diff --git a/qcom/opensource/dataipa/ipanat/test/ipa_nat_testMODEL.c b/qcom/opensource/dataipa/ipanat/test/ipa_nat_testMODEL.c new file mode 100644 index 0000000000..218b1cf04d --- /dev/null +++ b/qcom/opensource/dataipa/ipanat/test/ipa_nat_testMODEL.c @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2019 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*=========================================================================*/ +/*! + @file + ipa_nat_testXXX.c + + @brief + Verify the following scenario: + +*/ +/*===========================================================================*/ + +#include "ipa_nat_test.h" + +int ipa_nat_testXXX( + const char* nat_mem_type, + u32 pub_ip_add, + int total_entries, + u32 tbl_hdl, + int sep, + void* arb_data_ptr) +{ + int* tbl_hdl_ptr = (int*) arb_data_ptr; + + int ret; + + IPADBG("In\n"); + + if ( sep ) + { + ret = ipa_nat_add_ipv4_tbl(pub_ip_add, nat_mem_type, total_entries, &tbl_hdl); + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + } + + if ( sep ) + { + ret = ipa_nat_del_ipv4_tbl(tbl_hdl); + *tbl_hdl_ptr = 0; + CHECK_ERR(ret); + } + + IPADBG("Out\n"); + + return 0; +} diff --git a/qcom/opensource/dataipa/ipanat/test/ipa_nat_testREG.c b/qcom/opensource/dataipa/ipanat/test/ipa_nat_testREG.c new file mode 100644 index 0000000000..f42ce0c9bb --- /dev/null +++ b/qcom/opensource/dataipa/ipanat/test/ipa_nat_testREG.c @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2019 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*=========================================================================*/ +/*! + @file + ipa_nat_testREG.c + + @brief + Verify the following scenario: + 1. Add ipv4 table + 2. Delete ipv4 table +*/ +/*=========================================================================*/ + +#include "ipa_nat_test.h" + +int ipa_nat_testREG( + const char* nat_mem_type, + u32 pub_ip_add, + int total_entries, + u32 tbl_hdl, + int sep, + void* arb_data_ptr) +{ + int* ireg_ptr = (int*) arb_data_ptr; + + int i, ret; + + IPADBG("In\n"); + + for ( i = 0; i < *ireg_ptr; i++ ) + { + IPADBG("Executing iteration %d\n", i+1); + + IPADBG("Calling ipa_nat_add_ipv4_tbl()\n"); + + ret = ipa_nat_add_ipv4_tbl(pub_ip_add, nat_mem_type, total_entries, &tbl_hdl); + + CHECK_ERR_TBL_STOP(ret, tbl_hdl); + + IPADBG("Iteration %d creation of nat ipv4 table successful\n", i+1); + + IPADBG("Calling ipa_nat_del_ipv4_tbl()\n"); + + ret = ipa_nat_del_ipv4_tbl(tbl_hdl); + + CHECK_ERR(ret); + + IPADBG("Iteration %d deletion of ipv4 nat table successful\n", i+1); + } + + IPADBG("Executed %d iterations:\n", i); + + IPADBG("Out\n"); + + return 0; +} diff --git a/qcom/opensource/dataipa/ipanat/test/main.c b/qcom/opensource/dataipa/ipanat/test/main.c new file mode 100644 index 0000000000..340ee48506 --- /dev/null +++ b/qcom/opensource/dataipa/ipanat/test/main.c @@ -0,0 +1,507 @@ +/* + * Copyright (c) 2014, 2018-2019 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ipa_nat_test.h" +#include "ipa_nat_map.h" + +#undef strcasesame +#define strcasesame(x, y) \ + (! strcasecmp((x), (y))) + +static inline const char* legal_mem_type( + const char* mt ) +{ + if ( strcasesame(mt, "DDR") ) return "DDR"; + if ( strcasesame(mt, "SRAM") ) return "SRAM"; + if ( strcasesame(mt, "HYBRID") ) return "HYBRID"; + return NULL; +} + +static int nat_rule_loop_check( + ipa_table* table_ptr, + uint32_t rule_hdl, + void* record_ptr, + uint16_t record_index, + void* meta_record_ptr, + uint16_t meta_record_index, + void* arb_data_ptr ) +{ + enum ipa3_nat_mem_in nmi; + uint8_t is_expn_tbl; + uint16_t rule_index; + uint32_t tbl_hdl = (uint32_t) arb_data_ptr; + + struct ipa_nat_rule* rule_ptr = + (struct ipa_nat_rule*) record_ptr; + + BREAK_RULE_HDL(table_ptr, rule_hdl, nmi, is_expn_tbl, rule_index); + + /* + * By virtue of this function being called back by the walk, this + * record_index is valid. Denote it as such in the map... + */ + if ( ipa_nat_map_add(MAP_NUM_99, record_index, 1) ) + { + IPAERR("ipa_nat_map_add(index(%u)) failed\n", record_index); + return -EINVAL; + } + + if ( rule_ptr->next_index == record_index ) + { + IPAERR("Infinite loop detected in IPv4 %s table, entry %u\n", + (is_expn_tbl) ? "expansion" : "base", + record_index); + + ipa_nat_dump_ipv4_table(tbl_hdl); + + return -EINVAL; + } + + return 0; +} + +static int nat_rule_validity_check( + ipa_table* table_ptr, + uint32_t rule_hdl, + void* record_ptr, + uint16_t record_index, + void* meta_record_ptr, + uint16_t meta_record_index, + void* arb_data_ptr ) +{ + enum ipa3_nat_mem_in nmi; + uint8_t is_expn_tbl; + uint16_t rule_index; + uint16_t index; + + struct ipa_nat_rule* rule_ptr = + (struct ipa_nat_rule*) record_ptr; + + BREAK_RULE_HDL(table_ptr, rule_hdl, nmi, is_expn_tbl, rule_index); + + index = rule_ptr->next_index; + + if ( index && ipa_nat_map_find(MAP_NUM_99, index, NULL) ) + { + IPAERR("Invalid next index %u found in IPv4 %s table entry %u\n", + index, + (is_expn_tbl) ? "expansion" : "base", + rule_index); + + return -EINVAL; + } + + if ( is_expn_tbl ) + { + index = rule_ptr->prev_index; + + if ( index && ipa_nat_map_find(MAP_NUM_99, index, NULL) ) + { + IPAERR("Invalid previous index %u found in IPv4 %s table entry %u\n", + index, + "expansion", + rule_index); + + return -EINVAL; + } + } + + return 0; +} + +static int index_loop_check( + ipa_table* table_ptr, + uint32_t rule_hdl, + void* record_ptr, + uint16_t record_index, + void* meta_record_ptr, + uint16_t meta_record_index, + void* arb_data_ptr ) +{ + enum ipa3_nat_mem_in nmi; + uint8_t is_expn_tbl; + uint16_t rule_index; + uint32_t tbl_hdl = (uint32_t) arb_data_ptr; + + struct ipa_nat_indx_tbl_rule* itr_ptr = + (struct ipa_nat_indx_tbl_rule*) record_ptr; + + BREAK_RULE_HDL(table_ptr, rule_hdl, nmi, is_expn_tbl, rule_index); + + /* + * By virtue of this function being called back by the walk, this + * record_index is valid. Denote it as such in the map... + */ + if ( ipa_nat_map_add(MAP_NUM_99, record_index, 1) ) + { + IPAERR("ipa_nat_map_add(index(%u)) failed\n", record_index); + return -EINVAL; + } + + if ( itr_ptr->next_index == record_index ) + { + IPAERR("Infinite loop detected in IPv4 index %s table, entry %u\n", + (is_expn_tbl) ? "expansion" : "base", + record_index); + + ipa_nat_dump_ipv4_table(tbl_hdl); + + return -EINVAL; + } + + return 0; +} + +static int index_validity_check( + ipa_table* table_ptr, + uint32_t rule_hdl, + void* record_ptr, + uint16_t record_index, + void* meta_record_ptr, + uint16_t meta_record_index, + void* arb_data_ptr ) +{ + enum ipa3_nat_mem_in nmi; + uint8_t is_expn_tbl; + uint16_t rule_index; + uint16_t index; + + struct ipa_nat_indx_tbl_rule* itr_ptr = + (struct ipa_nat_indx_tbl_rule*) record_ptr; + + BREAK_RULE_HDL(table_ptr, rule_hdl, nmi, is_expn_tbl, rule_index); + + index = itr_ptr->next_index; + + if ( index && ipa_nat_map_find(MAP_NUM_99, index, NULL) ) + { + IPAERR("Invalid next index %u found in IPv4 index %s table entry %u\n", + index, + (is_expn_tbl) ? "expansion" : "base", + rule_index); + + return -EINVAL; + } + + if ( is_expn_tbl ) + { + struct ipa_nat_indx_tbl_meta_info* mi_ptr = meta_record_ptr; + + if ( ! mi_ptr ) + { + IPAERR("Missing meta pointer for IPv4 index %s table entry %u\n", + "expansion", + rule_index); + + return -EINVAL; + } + + index = mi_ptr->prev_index; + + if ( index && ipa_nat_map_find(MAP_NUM_99, index, NULL) ) + { + IPAERR("Invalid previous index %u found in IPv4 index %s table entry %u\n", + index, + "expansion", + rule_index); + + return -EINVAL; + } + } + + return 0; +} + +int ipa_nat_validate_ipv4_table( + u32 tbl_hdl ) +{ + int ret; + + /* + * Map MAP_NUM_99 will be used to keep, and to check for, + * record validity. + * + * The first walk will fill it. The second walk will use it... + */ + ipa_nat_map_clear(MAP_NUM_99); + + IPADBG("Checking IPv4 active rules:\n"); + + ret = ipa_nati_walk_ipv4_tbl(tbl_hdl, USE_NAT_TABLE, nat_rule_loop_check, tbl_hdl); + + if ( ret != 0 ) + { + return ret; + } + + ret = ipa_nati_walk_ipv4_tbl(tbl_hdl, USE_NAT_TABLE, nat_rule_validity_check, 0); + + if ( ret != 0 ) + { + return ret; + } + + /* + * Map MAP_NUM_99 will be used to keep, and to check for, + * record validity. + * + * The first walk will fill it. The second walk will use it... + */ + ipa_nat_map_clear(MAP_NUM_99); + + IPADBG("Checking IPv4 index active rules:\n"); + + ret = ipa_nati_walk_ipv4_tbl(tbl_hdl, USE_INDEX_TABLE, index_loop_check, tbl_hdl); + + if ( ret != 0 ) + { + return ret; + } + + ret = ipa_nati_walk_ipv4_tbl(tbl_hdl, USE_INDEX_TABLE, index_validity_check, 0); + + if ( ret != 0 ) + { + return ret; + } + + return 0; +} + +static void +_dispUsage( + const char* progNamePtr ) +{ + printf( + "Usage: %s [-d -r N -i N -e N -m mt]\n" + "Where:\n" + " -d Each test is discrete (create table, add rules, destroy table)\n" + " If not specified, only one table create and destroy for all tests\n" + " -r N Where N is the number of times to run the inotify regression test\n" + " -i N Where N is the number of times (iterations) to run test\n" + " -e N Where N is the number of entries in the NAT\n" + " -m mt Where mt is the type of memory to use for the NAT\n" + " Legal mt's: DDR, SRAM, or HYBRID (ie. use SRAM and DDR)\n" + " -g M-N Run tests M through N only\n", + progNamePtr); + + fflush(stdout); +} + +static NatTests nt_array[] = { + NAT_TEST_ENTRY(ipa_nat_test000, 1, 0), + NAT_TEST_ENTRY(ipa_nat_test001, 1, 0), + NAT_TEST_ENTRY(ipa_nat_test002, 1, 0), + NAT_TEST_ENTRY(ipa_nat_test003, 1, 0), + NAT_TEST_ENTRY(ipa_nat_test004, 1, 0), + NAT_TEST_ENTRY(ipa_nat_test005, 1, 0), + NAT_TEST_ENTRY(ipa_nat_test006, 1, 0), + NAT_TEST_ENTRY(ipa_nat_test007, 1, 0), + NAT_TEST_ENTRY(ipa_nat_test008, 1, 0), + NAT_TEST_ENTRY(ipa_nat_test009, 1, 0), + NAT_TEST_ENTRY(ipa_nat_test010, IPA_NAT_TEST_PRE_COND_TE, 0), + NAT_TEST_ENTRY(ipa_nat_test011, IPA_NAT_TEST_PRE_COND_TE, 0), + NAT_TEST_ENTRY(ipa_nat_test012, IPA_NAT_TEST_PRE_COND_TE, 0), + NAT_TEST_ENTRY(ipa_nat_test013, IPA_NAT_TEST_PRE_COND_TE, 0), + NAT_TEST_ENTRY(ipa_nat_test014, IPA_NAT_TEST_PRE_COND_TE, 0), + NAT_TEST_ENTRY(ipa_nat_test015, IPA_NAT_TEST_PRE_COND_TE, 0), + NAT_TEST_ENTRY(ipa_nat_test016, IPA_NAT_TEST_PRE_COND_TE, 0), + NAT_TEST_ENTRY(ipa_nat_test017, IPA_NAT_TEST_PRE_COND_TE, 0), + NAT_TEST_ENTRY(ipa_nat_test018, IPA_NAT_TEST_PRE_COND_TE, 0), + NAT_TEST_ENTRY(ipa_nat_test019, IPA_NAT_TEST_PRE_COND_TE, 0), + NAT_TEST_ENTRY(ipa_nat_test020, IPA_NAT_TEST_PRE_COND_TE, 0), + NAT_TEST_ENTRY(ipa_nat_test021, IPA_NAT_TEST_PRE_COND_TE, 0), + NAT_TEST_ENTRY(ipa_nat_test022, IPA_NAT_TEST_PRE_COND_TE, 0), + NAT_TEST_ENTRY(ipa_nat_test023, IPA_NAT_TEST_PRE_COND_TE, 0), + NAT_TEST_ENTRY(ipa_nat_test024, IPA_NAT_TEST_PRE_COND_TE, 0), + NAT_TEST_ENTRY(ipa_nat_test025, IPA_NAT_TEST_PRE_COND_TE, 0), + /* + * Add new tests just above this comment. Keep the following two + * at the end... + */ + NAT_TEST_ENTRY(ipa_nat_test999, 1, 0), + NAT_TEST_ENTRY(ipa_nat_testREG, 1, 0), +}; + +int main( + int argc, + char* argv[] ) +{ + int sep = 0; + int ireg = 0; + uint32_t nt = 1; + int total_ents = 100; + uint32_t ht = 0; + uint32_t start = 0, end = 0; + + char* nat_mem_type = "DDR"; + + uint32_t tbl_hdl = 0; + + uint32_t pub_ip_addr; + + uint32_t i, ub, cnt, exec, pass; + + void* adp; + + time_t t; + + int c, ret; + + IPADBG("Testing user space nat driver\n"); + + while ( (c = getopt(argc, argv, "dr:i:e:m:h:g:?")) != -1 ) + { + switch (c) + { + case 'd': + sep = 1; + break; + case 'r': + ireg = atoi(optarg); + break; + case 'i': + nt = atoi(optarg); + break; + case 'e': + total_ents = atoi(optarg); + break; + case 'm': + if ( ! (nat_mem_type = legal_mem_type(optarg)) ) + { + fprintf(stderr, "Illegal: -m %s\n", optarg); + _dispUsage(basename(argv[0])); + exit(0); + } + break; + case 'h': + ht = atoi(optarg); + break; + case 'g': + if ( sscanf(optarg, "%u-%u", &start, &end) != 2 + || + ( start >= end || end >= array_sz(nt_array) - 1 ) ) + { + fprintf(stderr, "Illegal: -f %s\n", optarg); + _dispUsage(basename(argv[0])); + exit(0); + } + break; + case '?': + default: + _dispUsage(basename(argv[0])); + exit(0); + break; + } + } + + srand(time(&t)); + + pub_ip_addr = RAN_ADDR; + + exec = pass = 0; + + for ( cnt = ret = 0; cnt < nt && ret == 0; cnt++ ) + { + IPADBG("ITERATION [%u] OF TESING\n", cnt + 1); + + if ( ireg ) + { + adp = &ireg; + i = array_sz(nt_array) - 1; + ub = array_sz(nt_array); + } + else + { + adp = &tbl_hdl; + i = ( end ) ? start : 0; + ub = ( end ) ? end : array_sz(nt_array) - 1; + + if ( i != 0 && ! sep ) + { + ipa_nat_test000( + nat_mem_type, pub_ip_addr, total_ents, tbl_hdl, 0, adp); + } + } + + for ( ; i < ub && ret == 0; i++ ) + { + if ( total_ents >= nt_array[i].num_ents_trigger ) + { + IPADBG("+------------------------------------------------+\n"); + IPADBG("| Executing test: %s |\n", nt_array[i].func_name); + IPADBG("+------------------------------------------------+\n"); + + ret = nt_array[i].func( + nat_mem_type, pub_ip_addr, total_ents, tbl_hdl, sep, adp); + + exec++; + + if ( ret == 0 ) + { + IPADBG("<<<<< Test %s SUCCEEDED >>>>>\n", nt_array[i].func_name); + + pass++; + + if ( ht || nt_array[i].test_hold_time_in_secs ) + { + ht = (ht) ? ht : nt_array[i].test_hold_time_in_secs; + + sleep(ht); + } + } + else + { + IPAERR("<<<<< Test %s FAILED >>>>>\n", nt_array[i].func_name); + } + } + } + } + + if ( ret && tbl_hdl ) + { + ipa_nat_test999( + nat_mem_type, pub_ip_addr, total_ents, tbl_hdl, 0, &tbl_hdl); + } + + IPADBG("Total NAT Tests Run:%u, Pass:%u, Fail:%u\n", + exec, pass, exec - pass); + + return 0; +} diff --git a/qcom/opensource/dataipa/kernel-tests/Android.bp b/qcom/opensource/dataipa/kernel-tests/Android.bp new file mode 100644 index 0000000000..d48c2032fe --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/Android.bp @@ -0,0 +1,66 @@ +cc_binary { + name: "ipa-kernel-tests", + + cflags: ["-Wno-missing-field-initializers"] + ["-Wno-int-to-pointer-cast"] + ["-Wno-int-conversion"], + + header_libs: ["device_kernel_headers"]+["qti_kernel_headers"]+["qti_ipa_kernel_headers"]+["qti_ipa_test_kernel_headers"], + + srcs: [ + "DataPathTestFixture.cpp", + "DataPathTests.cpp", + "ExceptionsTestFixture.cpp", + "ExceptionsTests.cpp", + "ExceptionTests.cpp", + "Feature.cpp", + "Filtering.cpp", + "FilteringEthernetBridgingTestFixture.cpp", + "FilteringEthernetBridgingTests.cpp", + "FilteringTest.cpp", + "HeaderInsertion.cpp", + "HeaderInsertionTests.cpp", + "HeaderProcessingContextTestFixture.cpp", + "HeaderProcessingContextTests.cpp", + "HeaderRemovalTestFixture.cpp", + "HeaderRemovalTests.cpp", + "InterfaceAbstraction.cpp", + "IPAFilteringTable.cpp", + "IPAInterruptsTestFixture.cpp", + "IPAInterruptsTests.cpp", + "IPv4Packet.cpp", + "IPv6CTTest.cpp", + "Logger.cpp", + "main.cpp", + "MBIMAggregationTestFixtureConf11.cpp", + "MBIMAggregationTests.cpp", + "NatTest.cpp", + "Pipe.cpp", + "PipeTestFixture.cpp", + "PipeTests.cpp", + "RNDISAggregationTestFixture.cpp", + "RNDISAggregationTests.cpp", + "RoutingDriverWrapper.cpp", + "RoutingTests.cpp", + "TestBase.cpp", + "TestManager.cpp", + "TestsUtils.cpp", + "TLPAggregationTestFixture.cpp", + "TLPAggregationTests.cpp", + ], + + vendor: true, + rtti: true, + + shared_libs: + ["libc++", + "libipanat"], + + relative_install_path: "ipa-kernel-tests", + + +} + +IPA_KERNEL_TESTS_FILE_LIST = [ + "README.txt", + "run.sh", +] + diff --git a/qcom/opensource/dataipa/kernel-tests/Constants.h b/qcom/opensource/dataipa/kernel-tests/Constants.h new file mode 100644 index 0000000000..7e1ad6b338 --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/Constants.h @@ -0,0 +1,395 @@ +/* + * Copyright (c) 2017,2019 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef CONSTANTS_H_ +#define CONSTANTS_H_ + + +#include +#include + +#define PRE_PHASE_ZERO_TEST_CONFIGURATION 0 +/*---------------------------------------------------------------------- + *Configuration 1 (see configure_system_1 ) + *-----USB_PROD--->[IPA DMA]----USB_CONS---> + *---------------------------------------------------------------------- + */ +#define PHASE_ZERO_TEST_CONFIGURATION 1 +/*---------------------------------------------------------------------- + *Configuration 2 (see configure_system_2 ) + * [IPA]----USB2_CONS--> + *-----USB_PROD--->[IPA]----USB3_CONS---> + * [IPA]----USB4_CONS---> + *---------------------------------------------------------------------- + */ +#define PHASE_TWO_TEST_CONFIGURATION 2 +/*---------------------------------------------------------------------- + *Configuration 3 (see configure_system_3 ) + * [IPA]----USB_CONS------> + *-----USB2_PROD--->[IPA]----USB2_CONS---> + * [IPA]----USB4_CONS----> + *---------------------------------------------------------------------- + */ +#define PHASE_THREE_TEST_CONFIGURATION 3 +/*Configuration 5 (see configure_system_5 ) + * [IPA]----USB2_CONS + Header Insertion (6Bytes) --> + *-----USB_PROD--->[IPA]----USB3_CONS + + *Header Insertion (22Bytes) + Length offset (11Bytes) --> + * [IPA]----USB4_CONS + + *Header Insertion (22Bytes) + Length offset (11Bytes) + Const(1Byte)--> + */ + +/* This Cfg is only for USB Integration Phase I*/ +#define PHASE_FIVE_TEST_CONFIGURATION 5 +#define PHASE_SIX_TEST_CONFIGURATION 6 +/*Configuration 7 (see configure_system_7 ) + * [IPA]----USB2_CONS--> + *-----USB_PROD--->[IPA]----USB3_CONS---> + * [IPA]----USB4_CONS---> + * [IPA]----A5 - Exception Pipe---> + */ +#define PHASE_SEVEN_TEST_CONFIGURATION 7 +/*---------------------------------------------------------------------- + *Configuration 8 (see configure_system_8 ) + *-----USB3_CONS--->[IPA DMA]----USB_CONS (TLP aggregation byte limit)---> + *-----USB_PROD (TLP deaggregation)--->[IPA DMA]----USB3_CONS---> + *-----USB2_PROD (TLP deaggregation)---> + *-----[IPA DMA]----USB_CONS (TLP aggregation byte limit)---> + *-----USB4_PROD--->[IPA DMA]----USB2_CONS (TLP aggregation time limit)---> + *---------------------------------------------------------------------- + */ +#define PHASE_EIGHT_TEST_CONFIGURATION 8 +/*---------------------------------------------------------------------- + *Configuration 9 (see configure_system_9 ) + *-----USB3_PROD--->[IPA DMA]----USB_CONS (MBIM aggregation byte limit)---> + *-----USB_PROD (MBIM deaggregation)--->[IPA DMA]----USB3_CONS---> + *-----USB2_PROD (MBIM deaggregation)---> + *-----[IPA DMA]----USB_CONS (MBIM aggregation byte limit)---> + *-----USB4_PROD--->[IPA DMA]----USB2_CONS (MBIM aggregation time limit)---> + *---------------------------------------------------------------------- + */ +#define PHASE_NINE_TEST_CONFIGURATION 9 +/*---------------------------------------------------------------------- + *Configuration 10 (see configure_system_10 ) + *-----USB_PROD--->[IPA DMA]----USB_CONS (MBIM aggregation no limits)---> + *---------------------------------------------------------------------- + */ +#define PHASE_TEN_TEST_CONFIGURATION 10 +/*---------------------------------------------------------------------- + *Configuration 11 (see configure_system_11 ) + *-----USB_PROD----->[IPA]---- + * USB2_CONS(MBIM aggregation byte limit)---> + *-USB2_PROD (MBIM deaggregation)->[IPA]----USB3_CONS---> + *------------------>[IPA]---- + *USB_CONS (MBIM aggregation time limit)-----------> + *------------------>[IPA]---- + *A5_LAN_WAN_CONS (MBIM aggregation no limits)----> + *---------------------------------------------------------------------- + */ +#define PHASE_ELEVEN_TEST_CONFIGURATION 11 +/*---------------------------------------------------------------------- + *Configuration 12 (see configure_system_12 ) + *-----USB_PROD----->[IPA]----USB2_CONS (MBIM aggregation byte limit)---> + *-USB2_PROD (MBIM deaggregation)->[IPA]----USB3_CONS---> + *------------------>[IPA]---- + * USB_CONS (MBIM aggregation time limit)-----------> + *------------------>[IPA]---- + * A5_LAN_WAN_CONS (MBIM aggregation no limits)----> + *---------------------------------------------------------------------- + */ +#define PHASE_TWELVE_TEST_CONFIGURATION 12 +/*---------------------------------------------------------------------- + *Configuration 9 (see configure_system_17 ) + *-----USB3_PROD--->[IPA DMA]----USB_CONS (RNDIS aggregation byte limit)---> + *-----USB_PROD (RNDIS deaggregation)--->[IPA DMA]----USB3_CONS---> + *-----USB2_PROD (RNDIS deaggregation)---> + *-----[IPA DMA]----USB_CONS (RNDIS aggregation byte limit)---> + *-----USB4--->[IPA DMA]----USB2_CONS (RNDIS aggregation time limit)---> + *---------------------------------------------------------------------- + */ +#define PHASE_SEVENTEEN_TEST_CONFIGURATION 17 + +/* + * Data path test + */ +#define PHASE_EIGHTEEN_TEST_CONFIGURATION 18 + +/*---------------------------------------------------------------------- + *Configuration 19 (see configure_system_19 ) + *-----USB_PROD--->[IPA DMA]----USB_CONS---> + *-----suspend [IPA DMA]----USB_CONS (for testing suspend interrupt)---> + *---------------------------------------------------------------------- + */ +#define PHASE_NINETEEN_TEST_CONFIGURATION 19 + +#define PHASE_TWENTY_TEST_CONFIGURATION 20 +/*---------------------------------------------------------------------- + *Configuration 20 (see configure_system_20 ) + *-----PROD (WLAN header removal)--------------------->[IPA]----CONS----> + *-----PROD (RNDIS de-aggregation + Header removal)--->[IPA] + *---------------------------------------------------------------------- + */ + +enum IPATestConfiguration { + IPA_TEST_CONFIFURATION_0 = PRE_PHASE_ZERO_TEST_CONFIGURATION, + IPA_TEST_CONFIFURATION_1 = PHASE_ZERO_TEST_CONFIGURATION, + IPA_TEST_CONFIFURATION_2 = PHASE_TWO_TEST_CONFIGURATION, + IPA_TEST_CONFIFURATION_3 = PHASE_THREE_TEST_CONFIGURATION, + IPA_TEST_CONFIFURATION_5 = PHASE_FIVE_TEST_CONFIGURATION, + IPA_TEST_CONFIFURATION_6 = PHASE_SIX_TEST_CONFIGURATION, + IPA_TEST_CONFIFURATION_7 = PHASE_SEVEN_TEST_CONFIGURATION, + IPA_TEST_CONFIGURATION_8 = PHASE_EIGHT_TEST_CONFIGURATION, + IPA_TEST_CONFIGURATION_9 = PHASE_NINE_TEST_CONFIGURATION, + IPA_TEST_CONFIGURATION_10 = PHASE_TEN_TEST_CONFIGURATION, + IPA_TEST_CONFIGURATION_11 = PHASE_ELEVEN_TEST_CONFIGURATION, + IPA_TEST_CONFIGURATION_12 = PHASE_TWELVE_TEST_CONFIGURATION, + IPA_TEST_CONFIGURATION_17 = PHASE_SEVENTEEN_TEST_CONFIGURATION, + IPA_TEST_CONFIGURATION_18 = PHASE_EIGHTEEN_TEST_CONFIGURATION, + IPA_TEST_CONFIGURATION_19 = PHASE_NINETEEN_TEST_CONFIGURATION, + IPA_TEST_CONFIGURATION_20 = PHASE_NINETEEN_TEST_CONFIGURATION, +}; +#define CONFIGURATION_NODE_PATH "/dev/ipa_test" + +/*producer*/ +#define INTERFACE0_TO_IPA_DATA_PATH "/dev/to_ipa_0" +#define INTERFACE0_FROM_IPA_DATA_PATH NULL + +/*producer*/ +#define INTERFACE4_TO_IPA_DATA_PATH "/dev/to_ipa_1" +#define INTERFACE4_FROM_IPA_DATA_PATH NULL + +/*producer*/ +#define INTERFACE5_TO_IPA_DATA_PATH "/dev/to_ipa_2" +#define INTERFACE5_FROM_IPA_DATA_PATH NULL + +/*consumer*/ +#define INTERFACE1_TO_IPA_DATA_PATH NULL +#define INTERFACE1_FROM_IPA_DATA_PATH "/dev/from_ipa_0" + +/*consumer 2*/ +#define INTERFACE2_TO_IPA_DATA_PATH NULL +#define INTERFACE2_FROM_IPA_DATA_PATH "/dev/from_ipa_1" + +/*Default consumer*/ +#define INTERFACE3_TO_IPA_DATA_PATH NULL +#define INTERFACE3_FROM_IPA_DATA_PATH "/dev/from_ipa_2" + +/*Exceptions producer*/ +#define INTERFACE_TO_IPA_EXCEPTION_PATH NULL +#define INTERFACE_FROM_IPA_EXCEPTION_PATH "/dev/ipa_exception_pipe" + +/*The next configuration should be used by the ITAKEM as well.*/ + +/*---------------------------------------------------------------------- + *Configuration 1 (see configure_system_1 ) + *-----USB_PROD--->[IPA DMA]----USB_CONS---> + *---------------------------------------------------------------------- + */ +#define CONFIG_1_FROM_USB1_TO_IPA_DMA "/dev/to_ipa_0" +#define CONFIG_1_FROM_IPA_TO_USB1_DMA "/dev/from_ipa_0" + +/*---------------------------------------------------------------------- + *Configuration 2 (see configure_system_2 ) + * [IPA]----USB2_CONS--> + *-----USB_PROD--->[IPA]----USB3_CONS---> + * [IPA]----Q6_LAN_CONS---> + *--------------------------------------------------------------------- + */ +#define CONFIG_2_FROM_USB_TO_IPA "/dev/to_ipa_0" +#define CONFIG_2_FROM_IPA_TO_A2_NDUN "/dev/from_ipa_0" +#define CONFIG_2_FROM_IPA_TO_A2_DUN "/dev/from_ipa_1" +#define CONFIG_2_FROM_IPA_TO_Q6_LAN "/dev/from_ipa_2" + +/*USB1 is an EthernetII Client*/ +#define FROM_USB1_TO_IPA "/dev/to_ipa_0" +#define FROM_IPA_TO_USB1 "/dev/from_ipa_0" +#define USB1_CLIENT_HEADER_LENGTH 14 + +/*---------------------------------------------------------------------- + *Configuration 3 (see configure_system_3 ) + * [IPA]----USB_CONS------> + *-----USB2_PROD--->[IPA]----USB2_CONS---> + * [IPA]----Q6_LAN_CONS----> + *---------------------------------------------------------------------- + */ +#define CONFIG_3_FROM_A2_NDUN_TO_IPA "/dev/to_ipa_0" +#define CONFIG_3_FROM_IPA_TO_USB1 "/dev/from_ipa_0" +#define CONFIG_3_FROM_IPA_TO_A2_NDUN "/dev/from_ipa_1" +#define CONFIG_3_FROM_IPA_TO_Q6_LAN "/dev/from_ipa_2" + +/*---------------------------------------------------------------------- + *Configuration 8 (see configure_system_8 ) + *-----USB3_PROD--->[IPA DMA]---- + *-----USB_CONS (TLP aggregation byte limit)---> + *-----USB_PROD (TLP deaggregation)--->[IPA DMA]----USB3_CONS---> + *-----USB2_PROD (TLP deaggregation)---> + * [IPA DMA]----USB_CONS (TLP aggregation byte limit)---> + *-----USB4--->[IPA DMA]----USB2_CONS (TLP aggregation time limit)---> + *---------------------------------------------------------------------- + */ +#define CONFIG_8_NO_AGG_TO_IPA_AGG "/dev/to_ipa_0" +#define CONFIG_8_DEAGG_TO_IPA_NO_AGG "/dev/to_ipa_1" +#define CONFIG_8_DEAGG_TO_IPA_AGG "/dev/to_ipa_2" +#define CONFIG_8_NO_AGG_TO_IPA_AGG_TIME "/dev/to_ipa_3" +#define CONFIG_8_FROM_IPA_AGG "/dev/from_ipa_0" +#define CONFIG_8_FROM_IPA_NO_AGG "/dev/from_ipa_1" +#define CONFIG_8_DEAGG_FROM_IPA_AGG "/dev/from_ipa_2" + +/*---------------------------------------------------------------------- + *Configuration 9 (see configure_system_9 ) + *-----USB3_PROD--->[IPA DMA]---- + * USB_CONS (MBIM aggregation byte limit)---> + *-----USB_PROD (MBIM deaggregation)--->[IPA DMA]----USB3_CONS---> + *-----USB2_PROD (MBIM deaggregation)---> + * [IPA DMA]----USB_CONS (MBIM aggregation byte limit)---> + *-----USB4--->[IPA DMA]---- + * USB2_CONS (MBIM aggregation time limit)---> + *---------------------------------------------------------------------- + */ +#define CONFIG_9_NO_AGG_TO_IPA_AGG "/dev/to_ipa_0" +#define CONFIG_9_DEAGG_TO_IPA_NO_AGG "/dev/to_ipa_1" +#define CONFIG_9_DEAGG_TO_IPA_AGG "/dev/to_ipa_2" +#define CONFIG_9_NO_AGG_TO_IPA_AGG_TIME "/dev/to_ipa_3" +#define CONFIG_9_FROM_IPA_AGG "/dev/from_ipa_0" +#define CONFIG_9_FROM_IPA_NO_AGG "/dev/from_ipa_1" +#define CONFIG_9_DEAGG_FROM_IPA_AGG "/dev/from_ipa_2" + +/*---------------------------------------------------------------------- + *Configuration 10 (see configure_system_10 ) + *-----USB_PROD--->[IPA DMA]---- + * USB_CONS (MBIM aggregation no limits)---> + *---------------------------------------------------------------------- + */ +#define CONFIG_10_TO_IPA_AGG_ZERO_LIMITS "/dev/to_ipa_0" +#define CONFIG_10_FROM_IPA_AGG_ZERO_LIMITS "/dev/from_ipa_0" + +/*---------------------------------------------------------------------- + *Configuration 11 (see configure_system_11 ) + *-----USB_PROD----->[IPA]---- + * USB2_CONS (MBIM aggregation byte limit)---> + * USB2_PROD (MBIM deaggregation)->[IPA]----USB3_CONS---> + *------------------>[IPA]---- + * USB_CONS (MBIM aggregation time limit)-----------> + *------------------>[IPA + * A5_LAN_WAN_CONS (MBIM aggregation no limits)----> + *---------------------------------------------------------------------- + */ +#define CONFIG_11_TO_IPA "/dev/to_ipa_0" +#define CONFIG_11_TO_IPA_DEAGG "/dev/to_ipa_1" +#define CONFIG_11_FROM_IPA_AGG "/dev/from_ipa_0" +#define CONFIG_11_FROM_IPA "/dev/from_ipa_1" +#define CONFIG_11_FROM_IPA_AGG_TIME "/dev/from_ipa_2" +#define CONFIG_11_FROM_IPA_ZERO_LIMITS "/dev/from_ipa_3" + +/*---------------------------------------------------------------------- + *Configuration 12 (see configure_system_12 ) + *-----USB_PROD----->[IPA]---- + * USB2_CONS (MBIM aggregation byte limit)---> + *-USB2_PROD (MBIM deaggregation)->[IPA]----USB3_CONS---> + *------------------>[IPA]---- + * USB_CONS (MBIM aggregation time limit)-----------> + *------------------>[IPA]---- + * A5_LAN_WAN_CONS (MBIM aggregation no limits)----> + *---------------------------------------------------------------------- + */ +#define CONFIG_12_TO_IPA "/dev/to_ipa_0" +#define CONFIG_12_TO_IPA_DEAGG "/dev/to_ipa_1" +#define CONFIG_12_FROM_IPA_AGG "/dev/from_ipa_0" +#define CONFIG_12_FROM_IPA "/dev/from_ipa_1" +#define CONFIG_12_FROM_IPA_AGG_TIME "/dev/from_ipa_2" +#define CONFIG_12_FROM_IPA_ZERO_LIMITS "/dev/from_ipa_3" + +/*Configuration 7 (see configure_system_7 ) + * [IPA]----USB2_CONS--> + *-----USB_PROD--->[IPA]----USB3_CONS---> + * [IPA]----Q6_LAN_CONS---> + * [IPA]----A5 - Exception Pipe---> + */ +#define CONFIG_7_FROM_USB1_TO_IPA "/dev/to_ipa_0" +#define CONFIG_7_FROM_IPA_TO_A5_EXCEPTION "/dev/ipa_exception_pipe" + +/*---------------------------------------------------------------------- + *Configuration 17 (see configure_system_17 ) + *-----USB_PROD----->[IPA]---- + * USB2_CONS (RNDIS aggregation byte limit)---> + * USB2_PROD (RNDIS deaggregation)->[IPA]----USB3_CONS---> + *------------------>[IPA]---- + * USB_CONS (RNDIS aggregation time limit)-----------> + *------------------>[IPA]---- + * A5_LAN_WAN_CONS (RNDIS aggregation no limits)----> + *---------------------------------------------------------------------- + */ +#define CONFIG_17_TO_IPA "/dev/to_ipa_0" +#define CONFIG_17_TO_IPA_NO_HDR "/dev/to_ipa_1" +#define CONFIG_17_TO_IPA_DEAGG "/dev/to_ipa_2" +#define CONFIG_17_FROM_IPA_AGG "/dev/from_ipa_0" +#define CONFIG_17_FROM_IPA "/dev/from_ipa_1" +#define CONFIG_17_FROM_IPA_AGG_TIME "/dev/from_ipa_2" +#define CONFIG_17_FROM_IPA_ZERO_LIMITS "/dev/from_ipa_3" + +/*---------------------------------------------------------------------- + *Configuration 18 (see configure_system_18 )--------------------------- + *-----USB_PROD----->[IPA]--------------->USB_CONS--------->A5---------- + *-----USB_PROD2 is a dummy endpoint handle for packet handling between- + *-----user space and kernel space in the IPA driver-------------------- + *---------------------------------------------------------------------- + */ +#define CONFIG_18_TO_IPA "/dev/to_ipa_0" +#define CONFIG_18_DUMMY_ENDPOINT "/dev/to_ipa_1" +#define CONFIG_18_FROM_IPA "/dev/from_ipa_0" + +/*---------------------------------------------------------------------- + *Configuration 19 (see configure_system_19 ) + *-----USB_PROD--->[IPA DMA]----USB_CONS---> + *---------------------------------------------------------------------- + */ +#define CONFIG_19_FROM_USB_TO_IPA_DMA "/dev/to_ipa_0" +#define CONFIG_19_FROM_IPA_TO_USB_DMA "/dev/from_ipa_0" + +enum ipv6_ext_hdr_type { + HOP_BY_HOP_OPT = 0, + DEST_OPT = 60, + ROUTING = 43, + FRAGMENT = 44, + AH = 51, + ESP = 50, + DEST_OPT_UL = 60, + Mobility = 135, + NONE = 59 +}; +/*File that are being used by the test application:*/ + +#define IPV4_FILE_PATH "Input/IPV4_3" + +/*--------------------------------------------------------------------- + *XUnit tests results format file name + *---------------------------------------------------------------------- + */ +#define XUNIT_REPORT_PATH_AND_NAME "junit_result.xml" + +#endif /* CONSTANTS_H_ */ diff --git a/qcom/opensource/dataipa/kernel-tests/DataPathTestFixture.cpp b/qcom/opensource/dataipa/kernel-tests/DataPathTestFixture.cpp new file mode 100644 index 0000000000..e08ecc2562 --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/DataPathTestFixture.cpp @@ -0,0 +1,105 @@ +/* + * Copyright (c) 2017 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "DataPathTestFixture.h" + +Pipe DataPathTestFixture::m_FromIPAPipe(IPA_CLIENT_TEST_CONS, + IPA_TEST_CONFIGURATION_18); +Pipe DataPathTestFixture::m_ToIpaPipe(IPA_CLIENT_TEST_PROD, + IPA_TEST_CONFIGURATION_18); +Pipe DataPathTestFixture::m_IpaDriverPipe(IPA_CLIENT_TEST2_PROD, + IPA_TEST_CONFIGURATION_18); + + +RoutingDriverWrapper DataPathTestFixture::m_Routing; +Filtering DataPathTestFixture::m_Filtering; +HeaderInsertion DataPathTestFixture::m_HeaderInsertion; + +DataPathTestFixture::DataPathTestFixture() +{ + m_testSuiteName.push_back("DataPath"); + Register(*this); +} + +bool DataPathTestFixture::Setup() +{ + bool bRetVal = true; + + /*Set the configuration to support USB->IPA and IPA->USB pipes.*/ + ConfigureScenario(IPA_TEST_CONFIGURATION_18); + + bRetVal &= m_ToIpaPipe.Init(); + bRetVal &= m_FromIPAPipe.Init(); + bRetVal &= m_IpaDriverPipe.Init(); + + if (!m_Routing.DeviceNodeIsOpened()) { + LOG_MSG_ERROR( + "Routing block is not ready for immediate commands!\n"); + return false; + } + if (!m_Filtering.DeviceNodeIsOpened()) { + LOG_MSG_ERROR( + "Filtering block is not ready for immediate commands!\n"); + return false; + } + if (!m_HeaderInsertion.DeviceNodeIsOpened()) + { + LOG_MSG_ERROR("Header Insertion block is not ready for immediate commands!\n"); + return false; + }\ + /*resetting this component will reset both Routing and Filtering tables*/ + m_HeaderInsertion.Reset(); + + return bRetVal; +} + +bool DataPathTestFixture::Teardown() +{ + /*The Destroy method will close the inode.*/ + m_FromIPAPipe.Destroy(); + m_ToIpaPipe.Destroy(); + m_IpaDriverPipe.Destroy(); + return true; +} + +bool DataPathTestFixture::Run() +{ + LOG_MSG_DEBUG("Entering Function"); + + if (!TestLogic()) { + LOG_MSG_ERROR( + "Test failed, Input and expected output mismatch."); + return false; + } + + LOG_MSG_DEBUG("Leaving Function (Returning True)"); + return true; +} + + diff --git a/qcom/opensource/dataipa/kernel-tests/DataPathTestFixture.h b/qcom/opensource/dataipa/kernel-tests/DataPathTestFixture.h new file mode 100644 index 0000000000..e7995a0322 --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/DataPathTestFixture.h @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2017 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef DATAPATHTESTFIXTURE_H_ +#define DATAPATHTESTFIXTURE_H_ + +#include +#include +#include +#include +#include +#include + +#include "Constants.h" +#include "Logger.h" +#include "linux/msm_ipa.h" +#include "TestsUtils.h" +#include "TestBase.h" +#include "Pipe.h" +#include "RoutingDriverWrapper.h" +#include "HeaderInsertion.h" +#include "Filtering.h" +#include "IPAFilteringTable.h" + +class DataPathTestFixture:public TestBase +{ +public: + /* + * This Constructor will register each instance + * that it creates. + */ + DataPathTestFixture(); + + /* + * This method will create and initialize two Pipe object for the USB + * (Ethernet) Pipes, one as input and the other as output. + */ + virtual bool Setup(); + + /*This method will destroy the pipes.*/ + virtual bool Teardown(); + + virtual bool Run(); + + virtual bool TestLogic() = 0; + + /*The client type are set from the peripheral perspective*/ + static Pipe m_FromIPAPipe; + static Pipe m_ToIpaPipe; + static Pipe m_IpaDriverPipe; + + static RoutingDriverWrapper m_Routing; + static Filtering m_Filtering; + static HeaderInsertion m_HeaderInsertion; +}; +#endif /* DATAPATHTESTFIXTURE_H_ */ diff --git a/qcom/opensource/dataipa/kernel-tests/DataPathTests.cpp b/qcom/opensource/dataipa/kernel-tests/DataPathTests.cpp new file mode 100644 index 0000000000..8d3290c1a8 --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/DataPathTests.cpp @@ -0,0 +1,391 @@ +/* + * Copyright (c) 2017,2020 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include "hton.h" /* for htonl*/ +#include "DataPathTestFixture.h" +#include "Constants.h" +#include "TestsUtils.h" +#include "linux/msm_ipa.h" + +#define PACKET_SIZE ((10)*(4)) + +class IpaTxDpTest:public DataPathTestFixture { + +public: + IpaTxDpTest() { + m_name = "IpaTxDpTest"; + m_description = "Sending one SKB via ipa_tx_dp() and checking" + "if it was received"; + m_runInRegression = true; + } + + bool TestLogic() { + LOG_MSG_DEBUG("Entering %s\n", __func__); + int ret; + unsigned char *input, *output; + unsigned char pkt[PACKET_SIZE] = { + 0x59, 0x61, 0x6e, 0x69, + 0x76, 0x5f, 0x48 ,0x61, + 0x73 ,0x62 ,0x61 ,0x6e, + 0x69 ,0x5f ,0x54 ,0x68, + 0x65 ,0x5f ,0x47 ,0x72, + 0x65 ,0x61 ,0x74 ,0x16, + 0x32 ,0x49 ,0x0c ,0x3f, + 0x37 ,0x23 ,0x6d ,0x15, + 0x50 ,0x10 ,0x3f ,0xbd, + 0xcc ,0xd8 ,0x00, 0x00 + }; + + input = (unsigned char *)malloc(PACKET_SIZE); + if(!input) { + LOG_MSG_ERROR("Error in allocation\n"); + goto fail; + } + + output = (unsigned char *)malloc(PACKET_SIZE); + if(!output) { + LOG_MSG_ERROR("Error in allocation\n"); + free(input); + goto fail; + } + + memcpy(input, pkt, PACKET_SIZE); + LOG_MSG_DEBUG("Sending packet through ipa_tx_dp() in func %s\n", __func__); + ret = m_IpaDriverPipe.Send(input, PACKET_SIZE); + + if (ret != PACKET_SIZE) { + LOG_MSG_ERROR( + "Amount of bits sent are: %d instead of %d\nExiting..\n" + , ret + , PACKET_SIZE); + free(input); + free(output); + goto fail; + } + + ret = m_FromIPAPipe.Receive(output, PACKET_SIZE); + if (ret != PACKET_SIZE) { + LOG_MSG_ERROR( + "Amount of bits sent are: %d instead of %d\nExiting..\n", + ret, + PACKET_SIZE); + free(input); + free(output); + goto fail; + } + + LOG_MSG_INFO("Input buff:\n"); + print_buff(input, PACKET_SIZE); + LOG_MSG_INFO("Output buff:\n"); + print_buff(output, PACKET_SIZE); + if (memcmp(input,output, PACKET_SIZE)) { + free(input); + free(output); + return false; + } + + free(input); + free(output); + return true; +fail: + return false; + } +}; + +class IpaTxDpMultipleTest:public DataPathTestFixture { + +public: + IpaTxDpMultipleTest() { + m_name = "IpaTxDpMultipleTest"; + m_description = "Sending multiple SKB via ipa_tx_dp() and checking" + "if it was received"; + m_runInRegression = false; + } + + bool TestLogic() { + int packet_to_send = 10; + int loop_size = 100; + int i; + int j; + + LOG_MSG_DEBUG("Entering %s\n", __func__); + int ret; + unsigned char *input, *output; + unsigned char pkt[PACKET_SIZE] = { + 0x59, 0x61, 0x6e, 0x69, + 0x76, 0x5f, 0x48 ,0x61, + 0x73 ,0x62 ,0x61 ,0x6e, + 0x69 ,0x5f ,0x54 ,0x68, + 0x65 ,0x5f ,0x47 ,0x72, + 0x65 ,0x61 ,0x74 ,0x16, + 0x32 ,0x49 ,0x0c ,0x3f, + 0x37 ,0x23 ,0x6d ,0x15, + 0x50 ,0x10 ,0x3f ,0xbd, + 0xcc ,0xd8 ,0x00, 0x00 + }; + + input = (unsigned char *)malloc(PACKET_SIZE); + if(!input) { + LOG_MSG_ERROR("Error in allocation\n"); + goto fail; + } + + output = (unsigned char *)malloc(PACKET_SIZE); + if(!output) { + LOG_MSG_ERROR("Error in allocation\n"); + free(input); + goto fail; + } + + memcpy(input, pkt, PACKET_SIZE); + for (i = 0; i < loop_size; i++) { + for (j = 0; j < packet_to_send; j++) { + input[0] = i; + input[1] = j; + LOG_MSG_DEBUG("Sending packet through ipa_tx_dp() in func %s\n", __func__); + ret = m_IpaDriverPipe.Send(input, PACKET_SIZE); + if (ret != PACKET_SIZE) { + LOG_MSG_ERROR( + "Amount of bits sent are: %d instead of %d\nExiting..\n" + , ret + , PACKET_SIZE); + free(input); + free(output); + goto fail; + } + } + + for (j = 0; j < packet_to_send; j++) { + ret = m_FromIPAPipe.Receive(output, PACKET_SIZE); + if (ret != PACKET_SIZE) { + LOG_MSG_ERROR( + "Amount of bits sent are: %d instead of %d\nExiting..\n", + ret, + PACKET_SIZE); + free(input); + free(output); + goto fail; + } + input[0] = i; + input[1] = j; + LOG_MSG_INFO("Input buff:\n"); + print_buff(input, PACKET_SIZE); + LOG_MSG_INFO("Output buff:\n"); + print_buff(output, PACKET_SIZE); + if (memcmp(input,output, PACKET_SIZE)) { + free(input); + free(output); + LOG_MSG_ERROR("Failed in buffers comparison"); + return false; + } + } + } + + free(input); + free(output); + return true; +fail: + return false; + } +}; + +class IPAToAppsTest:public DataPathTestFixture { + +public: + IPAToAppsTest() { + m_name = "IPAToApps"; + m_description = "Sending one SKB via USB_PROD pipe and checking" + "if it was received"; + m_runInRegression = true; + } + + bool TestLogic() { + int ret; + unsigned char *input, *output; + unsigned char pkt[PACKET_SIZE] = { + 0x59, 0x61, 0x6e, 0x69, + 0x76, 0x5f, 0x48 ,0x61, + 0x73 ,0x62 ,0x61 ,0x6e, + 0x69 ,0x5f ,0x54 ,0x68, + 0x65 ,0x5f ,0x47 ,0x72, + 0x65 ,0x61 ,0x74 ,0x16, + 0x32 ,0x49 ,0x0c ,0x3f, + 0x37 ,0x23 ,0x6d ,0x15, + 0x50 ,0x10 ,0x3f ,0xbd, + 0xcc ,0xd8 ,0x00, 0x00 + }; + + input = (unsigned char *)malloc(PACKET_SIZE); + if(!input) { + LOG_MSG_ERROR("Error in allocation\n"); + goto fail; + } + output = (unsigned char *)malloc(PACKET_SIZE); + if(!output) { + LOG_MSG_ERROR("Error in allocation\n"); + free(input); + goto fail; + } + memcpy(input, pkt, PACKET_SIZE); + + LOG_MSG_DEBUG("Sending packet through USB_PROD pipe in func %s\n", __func__); + ret = m_ToIpaPipe.Send(input, PACKET_SIZE); + if (ret != PACKET_SIZE) { + LOG_MSG_ERROR( + "Amount of bits sent are: %d instead of %d\nExiting..\n", + ret, + PACKET_SIZE); + goto fail; + } + LOG_MSG_DEBUG("Reading packet through Dummy Endpoint pipe in func %s\n", __func__); + ret = m_IpaDriverPipe.Receive(output, PACKET_SIZE); + if (ret != 0) { + LOG_MSG_ERROR("Failed in reading buffer. %d error", ret); + free(input); + free(output); + goto fail; + } + LOG_MSG_DEBUG("SKB original packet:\n"); + print_buff(input, PACKET_SIZE); + LOG_MSG_DEBUG("SKB received packet:\n"); + print_buff(output, PACKET_SIZE); + if (memcmp(input,output, PACKET_SIZE)) { + free(input); + free(output); + return false; + } + free(input); + free(output); + return true; +fail: + return false; + } +}; + +class IPAToAppsMultipleTest:public DataPathTestFixture { + +public: + IPAToAppsMultipleTest() { + m_name = "IPAToAppsMultipleTest"; + m_description = "Sending multiple SKB via USB_PROD pipe and checking" + "if they was received"; + m_runInRegression = false; + } + + bool TestLogic() { + int packet_to_send = 10; + int loop_size = 100; + int i; + int j; + int ret; + unsigned char *input, *output; + unsigned char pkt[PACKET_SIZE] = { + 0x59, 0x61, 0x6e, 0x69, + 0x76, 0x5f, 0x48 ,0x61, + 0x73 ,0x62 ,0x61 ,0x6e, + 0x69 ,0x5f ,0x54 ,0x68, + 0x65 ,0x5f ,0x47 ,0x72, + 0x65 ,0x61 ,0x74 ,0x16, + 0x32 ,0x49 ,0x0c ,0x3f, + 0x37 ,0x23 ,0x6d ,0x15, + 0x50 ,0x10 ,0x3f ,0xbd, + 0xcc ,0xd8 ,0x00, 0x00 + }; + + input = (unsigned char *)malloc(PACKET_SIZE); + if(!input) { + LOG_MSG_ERROR("Error in allocation\n"); + goto fail; + } + output = (unsigned char *)malloc(PACKET_SIZE); + if(!output) { + LOG_MSG_ERROR("Error in allocation\n"); + free(input); + goto fail; + } + memcpy(input, pkt, PACKET_SIZE); + for (i = 0; i < loop_size; i++) { + for (j = 0; j < packet_to_send; j++) { + input[0] = i; + input[1] = j; + + LOG_MSG_DEBUG("Sending packet through USB_PROD pipe in func %s\n", __func__); + ret = m_ToIpaPipe.Send(input, PACKET_SIZE); + if (ret != PACKET_SIZE) { + LOG_MSG_ERROR( + "Amount of bits sent are: %d instead of %d\nExiting..\n", + ret, + PACKET_SIZE); + free(input); + free(output); + goto fail; + } + } + + for (j = 0; j < packet_to_send; j++) { + input[0] = i; + input[1] = j; + LOG_MSG_DEBUG("Reading packet through Dummy Endpoint pipe in func %s\n", __func__); + ret = m_IpaDriverPipe.Receive(output, PACKET_SIZE); + if (ret != 0) { + LOG_MSG_ERROR("Failed in reading buffer. %d error", ret); + free(input); + free(output); + goto fail; + } + LOG_MSG_DEBUG("SKB original packet:\n"); + print_buff(input, PACKET_SIZE); + LOG_MSG_DEBUG("SKB received packet:\n"); + print_buff(output, PACKET_SIZE); + if (memcmp(input,output, PACKET_SIZE)) { + free(input); + free(output); + LOG_MSG_ERROR("Failed in buffers comparison"); + return false; + } + } + } + free(input); + free(output); + return true; +fail: + return false; + } +}; + + +static IpaTxDpTest ipaTxDpTest; +static IpaTxDpMultipleTest ipaTxDpMultipleTest; +static IPAToAppsTest ipaToApps; +static IPAToAppsMultipleTest iPAToAppsMultipleTestApps; diff --git a/qcom/opensource/dataipa/kernel-tests/ExceptionTests.cpp b/qcom/opensource/dataipa/kernel-tests/ExceptionTests.cpp new file mode 100644 index 0000000000..5ae9290a7a --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/ExceptionTests.cpp @@ -0,0 +1,506 @@ +/* + * Copyright (c) 2017 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Changes from Qualcomm Innovation Center are provided under the following license: + * + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * * Neither the name of Qualcomm Innovation Center, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + */ + +#include "TestsUtils.h" +#include "RoutingDriverWrapper.h" +#include "HeaderInsertion.h" +#include "Filtering.h" +#include "IPAFilteringTable.h" +#include "IPv4Packet.h" +#include + +using namespace IPA; + +class IPAExceptionTestFixture: public TestBase { +public: + + IPAExceptionTestFixture() : + m_uBufferSize(0) { + memset(m_aBuffer, 0, sizeof(m_aBuffer)); + m_testSuiteName.push_back("Exception"); + } + + virtual bool AddRules() = 0; + virtual bool ModifyPackets() = 0; + virtual bool TestLogic() = 0; + + bool Setup() { + + ConfigureScenario(PHASE_SEVEN_TEST_CONFIGURATION); + + m_producer.Open(INTERFACE0_TO_IPA_DATA_PATH, + INTERFACE0_FROM_IPA_DATA_PATH); + m_Consumer1.Open(INTERFACE1_TO_IPA_DATA_PATH, + INTERFACE1_FROM_IPA_DATA_PATH); + m_Consumer2.Open(INTERFACE2_TO_IPA_DATA_PATH, + INTERFACE2_FROM_IPA_DATA_PATH); + m_Consumer3.Open(INTERFACE3_TO_IPA_DATA_PATH, + INTERFACE3_FROM_IPA_DATA_PATH); + m_Exceptions.Open(INTERFACE_TO_IPA_EXCEPTION_PATH, + INTERFACE_FROM_IPA_EXCEPTION_PATH); + + + if (!m_Routing.DeviceNodeIsOpened()) { + LOG_MSG_ERROR( + "Routing block is not ready for immediate commands!\n"); + return false; + } + if (!m_Filtering.DeviceNodeIsOpened()) { + LOG_MSG_ERROR( + "Filtering block is not ready for immediate commands!\n"); + return false; + } + if (!m_HeaderInsertion.DeviceNodeIsOpened()) + { + LOG_MSG_ERROR("Header Insertion block is not ready for immediate commands!\n"); + return false; + } + m_HeaderInsertion.Reset(); + + return true; + } // Setup() + + bool Run() { + m_uBufferSize = BUFF_MAX_SIZE; + LOG_MSG_STACK("Entering Function"); + + // Configure the system by adding Routing / Filtering / HDR + if (!AddRules()) { + LOG_MSG_ERROR("Failed adding Routing / Filtering / HDR."); + return false; + } + // Load input data (IP packet) from file + if (!LoadDefaultPacket(m_eIP, m_aBuffer, m_uBufferSize)) { + LOG_MSG_ERROR("Failed default Packet"); + return false; + } + if (!ModifyPackets()) { + LOG_MSG_ERROR("Failed to modify packets."); + return false; + } + if (!TestLogic()) { + LOG_MSG_ERROR("Test failed, Input and expected output mismatch."); + return false; + } + LOG_MSG_STACK("Leaving Function (Returning True)"); + return true; + } // Run() + + bool Teardown() { + m_producer.Close(); + m_Consumer1.Close(); + m_Consumer2.Close(); + m_Consumer3.Close(); + m_Exceptions.Close(); + return true; + } // Teardown() + + ~IPAExceptionTestFixture() { + } + + static RoutingDriverWrapper m_Routing; + static Filtering m_Filtering; + static HeaderInsertion m_HeaderInsertion; + InterfaceAbstraction m_producer; + InterfaceAbstraction m_Consumer1; + InterfaceAbstraction m_Consumer2; + InterfaceAbstraction m_Consumer3; + InterfaceAbstraction m_Exceptions; + +protected: + static const size_t BUFF_MAX_SIZE = 1024; + static const uint8_t MAX_HEADER_SIZE = 64; // 64Bytes - Max Header Length + enum ipa_ip_type m_eIP; + uint8_t m_aBuffer[BUFF_MAX_SIZE]; // Input file \ IP packet + size_t m_uBufferSize; + +}; +RoutingDriverWrapper IPAExceptionTestFixture::m_Routing; +Filtering IPAExceptionTestFixture::m_Filtering; +HeaderInsertion IPAExceptionTestFixture::m_HeaderInsertion; + +//----------------------------------------------------------------------------------------------------------------------------------------/ +// Test001: Test that when a packet with (IPVer != 4) && (IPVer Ver != 6) , an exception packet is created and received & exception_pipe / +//----------------------------------------------------------------------------------------------------------------------------------------/ +class IPAExceptionPacketTest001: public IPAExceptionTestFixture { +public: + IPAExceptionPacketTest001() { + m_name = "IPAExceptionPacketTest001"; + m_description = "\ + IPA Exception Test 001 - Test that when a packet with (IPVer != 4) && (IPVer Ver != 6) , an exception packet is created and received & exception_pipe \ + Test Generates send NUM_OF_EXCEPTION_PKTS packets with IP Version changing from 0 to 9.\ + First IP Version == 4, hence it is not considered as exception (same goes for IP Ver == 6) \ + "; + m_eIP = IPA_IP_v4; + Register(*this); + } + + virtual bool AddRules() { + // Clear All Rules + bool bRetVal = true; + LOG_MSG_STACK("Entering Function"); + + const char bypass0[20] = "Bypass0"; + struct ipa_ioc_get_rt_tbl sRoutingTable; + IPAFilteringTable cFilterTable; + struct ipa_flt_rule_add sFilterRuleEntry; + uint32_t nRTTableHdl=0; + memset(&sRoutingTable, 0, sizeof(sRoutingTable)); + + LOG_MSG_STACK("Entering Function"); + if (!CreateBypassRoutingTable(&m_Routing, m_eIP, bypass0, IPA_CLIENT_TEST2_CONS, + 0,&nRTTableHdl)) { + LOG_MSG_ERROR("CreateBypassRoutingTable Failed\n"); + bRetVal = false; + goto bail; + } + LOG_MSG_INFO("CreateBypassRoutingTable completed successfully"); + sRoutingTable.ip = m_eIP; + strlcpy(sRoutingTable.name, bypass0, sizeof(sRoutingTable.name)); + if (!m_Routing.GetRoutingTable(&sRoutingTable)) { + LOG_MSG_ERROR( + "m_routing.GetRoutingTable(&sRoutingTable=0x%p) Failed.", &sRoutingTable); + bRetVal = false; + goto bail; + } + // Creating Filtering Rules + cFilterTable.Init(m_eIP,IPA_CLIENT_TEST_PROD,true,1); + LOG_MSG_INFO("Creation of filtering table completed successfully"); + + // Configuring Filtering Rule No.1 + cFilterTable.GeneratePresetRule(0,sFilterRuleEntry); + sFilterRuleEntry.at_rear = true; + sFilterRuleEntry.flt_rule_hdl = -1; // return Value + sFilterRuleEntry.status = -1; // return value + sFilterRuleEntry.rule.action = IPA_PASS_TO_ROUTING; + sFilterRuleEntry.rule.rt_tbl_hdl = nRTTableHdl; + if ( + ((uint8_t)-1 == cFilterTable.AddRuleToTable(sFilterRuleEntry)) || + !m_Filtering.AddFilteringRule(cFilterTable.GetFilteringTable()) + ) + { + LOG_MSG_ERROR ("Adding Rule (0) to Filtering block Failed."); + bRetVal = false; + goto bail; + } else + { + LOG_MSG_DEBUG("flt rule hdl0=0x%x, status=0x%x\n", cFilterTable.ReadRuleFromTable(0)->flt_rule_hdl,cFilterTable.ReadRuleFromTable(0)->status); + } + + bail: + LOG_MSG_STACK( + "Leaving Function (Returning %s)", bRetVal?"True":"False"); + return bRetVal; + } // AddRules() + + virtual bool ModifyPackets() { + m_eIP = IPA_IP_v6; + + AddRules(); // Need to add Routing / Filtering rules for IPv6 as well. + return true; + } // ModifyPacktes () + + virtual bool TestLogic() { + int i = 0, nIPVer = 0;; + memset(m_aExpectedBuffer, 0, sizeof(m_aExpectedBuffer)); + m_aExpectedBuffer[2] = 0x0b; + m_aExpectedBuffer[3] = 0x80; + + memcpy(m_aExpectedBuffer+8, m_aBuffer, m_uBufferSize); + m_aExpectedBufSize = m_uBufferSize+8; + + for (i=0;iflt_rule_hdl,cFilterTable.ReadRuleFromTable(0)->status); + } + + bail: + LOG_MSG_STACK( + "Leaving Function (Returning %s)", bRetVal?"True":"False"); + return bRetVal; + } // AddRules() + + virtual bool ModifyPackets() { + return true; + } // ModifyPacktes () + + virtual bool TestLogic() { + memset(m_aExpectedBuffer, 0, sizeof(m_aExpectedBuffer)); + m_aExpectedBuffer[2] = 0x0b; + m_aExpectedBuffer[3] = 0x20; + + memcpy(m_aExpectedBuffer+8, m_aBuffer, m_uBufferSize); + m_aExpectedBufSize = m_uBufferSize+8; + + if (!SendReceiveAndCompare(&m_producer, m_aBuffer, m_uBufferSize, + &m_Exceptions, m_aExpectedBuffer, m_aExpectedBufSize)) + { + LOG_MSG_ERROR("SendReceiveAndCompare failed."); + return false; + } + return true; + } +private: + uint8_t m_aExpectedBuffer[BUFF_MAX_SIZE]; + size_t m_aExpectedBufSize; +}; + +//-----------------------------------------------------------------------------------------------------------------------------------------/ +// Test006: Test that when a packet with Internet Header Length < 5 Arrives, an exception packet is created and received & exception_pipe / +//-----------------------------------------------------------------------------------------------------------------------------------------/ +class IPAExceptionPacketTest006: public IPAExceptionTestFixture { +public: + IPAExceptionPacketTest006() { + m_name = "IPAExceptionPacketTest006"; + m_description = "\ + IPA Exception Test 006 - Test that when a packet with Internet Header Length < 5 Arrives, an exception packet is created and received & exception_pipe \ + Test Generates a Packet with Internet Header Length (IHL == 4). \ + and verifies that the packet is recieved @ the Exception Pipe. \ + "; + m_eIP = IPA_IP_v4; + Register(*this); + } + + virtual bool AddRules() { + // Clear All Rules + bool bRetVal = true; + LOG_MSG_STACK("Entering Function"); + + const char bypass0[20] = "Bypass0"; + struct ipa_ioc_get_rt_tbl sRoutingTable; + IPAFilteringTable cFilterTable; + struct ipa_flt_rule_add sFilterRuleEntry; + uint32_t nRTTableHdl=0; + memset(&sRoutingTable, 0, sizeof(sRoutingTable)); + + LOG_MSG_STACK("Entering Function"); + if (!CreateBypassRoutingTable(&m_Routing, m_eIP, bypass0, IPA_CLIENT_TEST2_CONS, + 0,&nRTTableHdl)) { + LOG_MSG_ERROR("CreateBypassRoutingTable Failed\n"); + bRetVal = false; + goto bail; + } + LOG_MSG_INFO("CreateBypassRoutingTable completed successfully"); + sRoutingTable.ip = m_eIP; + strlcpy(sRoutingTable.name, bypass0, sizeof(sRoutingTable.name)); + if (!m_Routing.GetRoutingTable(&sRoutingTable)) { + LOG_MSG_ERROR( + "m_routing.GetRoutingTable(&sRoutingTable=0x%p) Failed.", &sRoutingTable); + bRetVal = false; + goto bail; + } + // Creating Filtering Rules + cFilterTable.Init(m_eIP,IPA_CLIENT_TEST_PROD,true,1); + LOG_MSG_INFO("Creation of filtering table completed successfully"); + + // Configuring Filtering Rule No.1 + cFilterTable.GeneratePresetRule(0,sFilterRuleEntry); + sFilterRuleEntry.at_rear = true; + sFilterRuleEntry.flt_rule_hdl = -1; // return Value + sFilterRuleEntry.status = -1; // return value + sFilterRuleEntry.rule.action = IPA_PASS_TO_ROUTING; + sFilterRuleEntry.rule.rt_tbl_hdl = nRTTableHdl; + if ( + ((uint8_t)-1 == cFilterTable.AddRuleToTable(sFilterRuleEntry)) || + !m_Filtering.AddFilteringRule(cFilterTable.GetFilteringTable()) + ) + { + LOG_MSG_ERROR ("Adding Rule (0) to Filtering block Failed."); + bRetVal = false; + goto bail; + } else + { + LOG_MSG_DEBUG("flt rule hdl0=0x%x, status=0x%x\n", cFilterTable.ReadRuleFromTable(0)->flt_rule_hdl,cFilterTable.ReadRuleFromTable(0)->status); + } + + bail: + LOG_MSG_STACK( + "Leaving Function (Returning %s)", bRetVal?"True":"False"); + return bRetVal; + } // AddRules() + + virtual bool ModifyPackets() { + m_aBuffer[0] =(m_aBuffer[0] & 0xF0)+0x04;// Change the IHL to 4 + return true; + } // ModifyPacktes () + + virtual bool TestLogic() { + memset(m_aExpectedBuffer, 0, sizeof(m_aExpectedBuffer)); + m_aExpectedBuffer[2] = 0x0b; + m_aExpectedBuffer[3] = 0x04; + + memcpy(m_aExpectedBuffer+8, m_aBuffer, m_uBufferSize); + m_aExpectedBufSize = m_uBufferSize+8; + + if (!SendReceiveAndCompare(&m_producer, m_aBuffer, m_uBufferSize, + &m_Exceptions, m_aExpectedBuffer, m_aExpectedBufSize)) + { + LOG_MSG_ERROR("SendReceiveAndCompare failed."); + return false; + } + return true; + } +private: + uint8_t m_aExpectedBuffer[BUFF_MAX_SIZE]; + size_t m_aExpectedBufSize; +}; + +static IPAExceptionPacketTest001 ipaExceptionPacketTest001; +static IPAExceptionPacketTest003 ipaExceptionPacketTest003; +static IPAExceptionPacketTest006 ipaExceptionPacketTest006; + diff --git a/qcom/opensource/dataipa/kernel-tests/ExceptionsTestFixture.cpp b/qcom/opensource/dataipa/kernel-tests/ExceptionsTestFixture.cpp new file mode 100644 index 0000000000..fae6c9b7bc --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/ExceptionsTestFixture.cpp @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2017 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "RoutingDriverWrapper.h" +#include "HeaderInsertion.h" +#include "Filtering.h" +#include "IPAFilteringTable.h" +#include "TestsUtils.h" +#include +#include "ExceptionsTestFixture.h" + +/////////////////////////////////////////////////////////////////////////////// + +Pipe ExceptionsTestFixture::m_USB1ToIpaPipe(IPA_CLIENT_TEST_PROD, IPA_TEST_CONFIFURATION_7); +Pipe ExceptionsTestFixture::m_IpaToA5ExceptionPipe(IPA_TEST_CONFIFURATION_7);//Exception pipe + +/////////////////////////////////////////////////////////////////////////////// + +ExceptionsTestFixture::ExceptionsTestFixture(){ + Register(*this); + m_testSuiteName.push_back("Exceptions"); +} + +/////////////////////////////////////////////////////////////////////////////// + + + +/////////////////////////////////////////////////////////////////////////////// +/////// EOF /////// +/////////////////////////////////////////////////////////////////////////////// + diff --git a/qcom/opensource/dataipa/kernel-tests/ExceptionsTestFixture.h b/qcom/opensource/dataipa/kernel-tests/ExceptionsTestFixture.h new file mode 100644 index 0000000000..4cb5161c01 --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/ExceptionsTestFixture.h @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2017 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Changes from Qualcomm Innovation Center are provided under the following license: + * + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * * Neither the name of Qualcomm Innovation Center, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + */ + +#include "RoutingDriverWrapper.h" +#include "HeaderInsertion.h" +#include "Filtering.h" +#include "IPAFilteringTable.h" +#include "TestsUtils.h" +#include "Pipe.h" +#include + +#ifndef _EXCEPTION_TESTS_FIXTURE_ +#define _EXCEPTION_TESTS_FIXTURE_ + +class ExceptionsTestFixture:public TestBase { +public: + /*This Constructor will register the + *exception tests and set the suit name + */ + ExceptionsTestFixture(); +protected: + static Pipe m_USB1ToIpaPipe; + /*from the test application into the IPA(DMUX header)*/ + static Pipe m_IpaToA5ExceptionPipe; + /*from the IPA back to the test application(Exception pipe)*/ +}; + +#endif diff --git a/qcom/opensource/dataipa/kernel-tests/ExceptionsTests.cpp b/qcom/opensource/dataipa/kernel-tests/ExceptionsTests.cpp new file mode 100644 index 0000000000..8e370eca41 --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/ExceptionsTests.cpp @@ -0,0 +1,298 @@ +/* + * Copyright (c) 2017 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Changes from Qualcomm Innovation Center are provided under the following license: + * + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * * Neither the name of Qualcomm Innovation Center, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + */ + +#include "RoutingDriverWrapper.h" +#include "HeaderInsertion.h" +#include "Filtering.h" +#include "IPAFilteringTable.h" +#include "TestsUtils.h" +#include "ExceptionsTestFixture.h" +#include "IPv4Packet.h" +#include + +#define MAX_SENT_BUFFER_SIZE 1500 +#define MAX_RECEIVE_BUFFER_SIZE 1500 +#define VALIDATE_WITH_MSG_AND_RETVAL(bRetVal,msg) \ + if (false == bRetVal){ \ + LOG_MSG_ERROR(msg); \ + return false; \ + } + +using namespace IPA; + +/////////////////////////////////////////////////////////////////////////////// + +class ExceptionsTestNonIpPacket: public ExceptionsTestFixture { +public: + //The packet size to be sent + size_t m_nPacketSize; + //A buffer to hold the non-IP(V4/V6) packet + Byte *m_pSendBuffer; + + /////////////////////////////////////////////////////////////////////////// + + //Set the tests name and description + ExceptionsTestNonIpPacket() : + m_nPacketSize(0), m_pSendBuffer(NULL) { + m_name = "ExceptionsTestNonIpPacket"; + m_description = + "Create a non-IP packet(version!=4 && version !=6) and \ + expect exception from Filter block"; + } + + /////////////////////////////////////////////////////////////////////////// + + virtual bool Run() { + bool bRetVal = true; + Byte *pReceiveBuffer = new Byte[MAX_RECEIVE_BUFFER_SIZE]; + //Send the non-IPV4/IPV6 packet to the IPA + LOG_MSG_DEBUG("Send the non-IPV4/IPV6 packet to the IPA"); + size_t nBytesSent = m_USB1ToIpaPipe.Send(m_pSendBuffer, m_nPacketSize); + if (nBytesSent != m_nPacketSize) { + LOG_MSG_ERROR("Not all data was sent into the IPA"); + return false; + } + + //Read from the exception pipe(from IPA to A5) - try to read as much as we can + size_t nBytesRead = m_IpaToA5ExceptionPipe.Receive(pReceiveBuffer, + MAX_RECEIVE_BUFFER_SIZE); + if (nBytesRead != nBytesSent) { + LOG_MSG_ERROR("Not all data was read:"); + print_buff(pReceiveBuffer, nBytesRead); + return false; + } + + //check the exception packet against the one that we sent + bRetVal = !memcmp(m_pSendBuffer, pReceiveBuffer, nBytesSent); + if (false == bRetVal) { + LOG_MSG_ERROR("Received packet is not equal, Received:"); + print_buff(pReceiveBuffer, nBytesRead); + LOG_MSG_ERROR("Received packet is not equal, Sent:"); + print_buff(m_pSendBuffer, m_nPacketSize); + return false; + } + return true; + } + + /////////////////////////////////////////////////////////////////////////// + + //build the non-IP packet + virtual bool Setup() { + bool bRetVal = true; + m_pSendBuffer = new Byte[MAX_SENT_BUFFER_SIZE]; + //Load some default IPV4 packet and save its size + m_nPacketSize = MAX_SENT_BUFFER_SIZE; //This parameter is In/Out + bRetVal = LoadDefaultPacket(IPA_IP_v4, m_pSendBuffer, m_nPacketSize); + VALIDATE_WITH_MSG_AND_RETVAL(bRetVal, "Load failed"); + //Set the version field to non-IPV4/IPV6(version = 5) + m_pSendBuffer[0] &= 0x0F; + m_pSendBuffer[0] |= 0x50; + + //initialize Pipes + bRetVal = m_USB1ToIpaPipe.Init(); + VALIDATE_WITH_MSG_AND_RETVAL(bRetVal, "Pipe Initialization failed"); + bRetVal = m_IpaToA5ExceptionPipe.Init(); + VALIDATE_WITH_MSG_AND_RETVAL(bRetVal, "Pipe Initialization failed"); + return true; + } + + /////////////////////////////////////////////////////////////////////////// + + virtual bool Teardown() { + bool bRetVal = true; + delete[] m_pSendBuffer; + m_USB1ToIpaPipe.Destroy(); + m_IpaToA5ExceptionPipe.Destroy(); + return bRetVal; + } + + /////////////////////////////////////////////////////////////////////////// + +}; +//ExceptionTestNoneIpPacket + +/////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// + +class ExceptionsTestFragmentedException: public ExceptionsTestFixture { +public: + //The packet size to be sent + size_t m_nPacketSize; + //A buffer to hold the non-IP(V4/V6) packet + Byte *m_pSendBuffer; + Byte *m_pReceiveBuffer; + + /////////////////////////////////////////////////////////////////////////// + + //Set the tests name and description + ExceptionsTestFragmentedException():m_nPacketSize(0), m_pSendBuffer(NULL), + m_pReceiveBuffer(NULL){ + m_name = "ExceptionsTestFragmentedException"; + m_description = + "Send IP packet with MF set, create global Filter rule \ + that will hit it as Exception"; + } + + /////////////////////////////////////////////////////////////////////////// + + virtual bool Run() { + bool bRetVal = true; + //configuring the Filter block to catch the fragmented packet: + ConfigureFilterGlobalRuleForMF(); + //Send the non-IPV4/IPV6 packet to the IPA + LOG_MSG_DEBUG("Send the IP packet with the MF bit set(size = %d)", m_nPacketSize); + size_t nBytesSent = m_USB1ToIpaPipe.Send(m_pSendBuffer, m_nPacketSize); + if (nBytesSent != m_nPacketSize) { + LOG_MSG_ERROR("Not all data was sent into the IPA(only %d)", nBytesSent); + return false; + } + //Read from the exception pipe(from IPA to A5) - try to read as much as we can + size_t nBytesRead = m_IpaToA5ExceptionPipe.Receive(m_pReceiveBuffer, + MAX_RECEIVE_BUFFER_SIZE); + if (nBytesRead != nBytesSent) { + LOG_MSG_ERROR("Not all data was read:"); + print_buff(m_pReceiveBuffer, nBytesRead); + return false; + } + //check the exception packet against the one that we sent + bRetVal = !memcmp(m_pSendBuffer, m_pReceiveBuffer, nBytesSent); + if (false == bRetVal) { + LOG_MSG_ERROR("Received packet is not equal, Received:"); + print_buff(m_pReceiveBuffer, nBytesRead); + LOG_MSG_ERROR("Received packet is not equal, Sent:"); + print_buff(m_pSendBuffer, m_nPacketSize); + return false; + } + return true; + } + + /////////////////////////////////////////////////////////////////////////// + + //build the non-IP packet + virtual bool Setup() { + bool bRetVal = true; + m_pReceiveBuffer = new Byte[MAX_RECEIVE_BUFFER_SIZE]; + m_pSendBuffer = new Byte[MAX_RECEIVE_BUFFER_SIZE]; + //Load some default TCP packet + TCPPacket tcpPacket; + //Set the MF bit + tcpPacket.SetMF(true); + //copy the packet to the send buffer + m_nPacketSize = tcpPacket.GetSize(); + tcpPacket.ToNetworkByteStream(m_pSendBuffer); + //initialize Pipes + bRetVal = m_USB1ToIpaPipe.Init(); + VALIDATE_WITH_MSG_AND_RETVAL(bRetVal, "Pipe Initialization failed"); + bRetVal = m_IpaToA5ExceptionPipe.Init(); + VALIDATE_WITH_MSG_AND_RETVAL(bRetVal, "Pipe Initialization failed"); + return true; + } + + /////////////////////////////////////////////////////////////////////////// + + virtual bool Teardown() { + bool bRetVal = true; + delete[] m_pSendBuffer; + m_USB1ToIpaPipe.Destroy(); + m_IpaToA5ExceptionPipe.Destroy(); + return bRetVal; + } + + + + /////////////////////////////////////////////////////////////////////////// + + void ConfigureFilterGlobalRuleForMF(){ + //struct ipa_ioc_add_flt_rule *pRuleTable; + //Allocate memory for a table with one rule. + + //Instruct the Driver to write this table(with its one rule) to the HW + + //Continue from here - build the rule to catch the fragmented packet + } + + /////////////////////////////////////////////////////////////////////////// + + +}; +//ExceptionsTestFragmentedException + +/////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////// + +class ExceptionsTestNonTCPUDP: public ExceptionsTestFixture { + +}; + +/////////////////////////////////////////////////////////////////////////////// +//Classes instances: +static ExceptionsTestNonIpPacket exceptionsTestNonIpPacket; +static ExceptionsTestFragmentedException exceptionsTestFragmentedException; + +/////////////////////////////////////////////////////////////////////////////// +////////////// EOF //////// +/////////////////////////////////////////////////////////////////////////////// diff --git a/qcom/opensource/dataipa/kernel-tests/Feature.cpp b/qcom/opensource/dataipa/kernel-tests/Feature.cpp new file mode 100644 index 0000000000..e50f9c603f --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/Feature.cpp @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2017,2020 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Changes from Qualcomm Innovation Center are provided under the following license: + * + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * * Neither the name of Qualcomm Innovation Center, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + */ + +#include +#include +#include +#include +#include +#include + +#include "Feature.h" + +/* + * All interaction through the driver are + * made through this inode. + */ +static const char* DEVICE_NAME = "/dev/ipa"; + +Feature::Feature() +{ + m_fd = open(DEVICE_NAME, O_RDWR); + if (!m_fd) + { + cout << "Failed to open " << DEVICE_NAME << endl; + } +} + +Feature::~Feature() +{ + if (m_fd) + { + close(m_fd); + } +} + +bool Feature::DeviceNodeIsOpened() +{ + return (m_fd > 0 && fcntl(m_fd, F_GETFL) >= 0); +} diff --git a/qcom/opensource/dataipa/kernel-tests/Feature.h b/qcom/opensource/dataipa/kernel-tests/Feature.h new file mode 100644 index 0000000000..f6bcad61a4 --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/Feature.h @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2017,2020 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Changes from Qualcomm Innovation Center are provided under the following license: + * + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * * Neither the name of Qualcomm Innovation Center, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + */ + +#ifndef FEATURE_H_ +#define FEATURE_H_ + +#include +#include +#include +#include "linux/msm_ipa.h" + +using std::cout; +using std::endl; + +class Feature +{ +public: + Feature(); + ~Feature(); + bool DeviceNodeIsOpened(); + +protected: + int m_fd; +}; + +#endif diff --git a/qcom/opensource/dataipa/kernel-tests/Filtering.cpp b/qcom/opensource/dataipa/kernel-tests/Filtering.cpp new file mode 100644 index 0000000000..bdf6a338e3 --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/Filtering.cpp @@ -0,0 +1,142 @@ +/* + * Copyright (c) 2017,2020 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Changes from Qualcomm Innovation Center are provided under the following license: + * + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * * Neither the name of Qualcomm Innovation Center, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + */ + + +#include +#include +#include +#include + +#include "Filtering.h" + +bool Filtering::AddFilteringRule(struct ipa_ioc_add_flt_rule const * ruleTable) +{ + int retval = 0; + + retval = ioctl(m_fd, IPA_IOC_ADD_FLT_RULE, ruleTable); + if (retval) { + printf("%s(), failed adding Filtering rule table %p\n", __FUNCTION__, ruleTable); + return false; + } + + printf("%s(), Added Filtering rule to table %p\n", __FUNCTION__, ruleTable); + return true; +} + +bool Filtering::AddFilteringRule(struct ipa_ioc_add_flt_rule_v2 const * ruleTable) +{ + int retval = 0; + + retval = ioctl(m_fd, IPA_IOC_ADD_FLT_RULE_V2, ruleTable); + if (retval) { + printf("%s(), failed adding Filtering rule table %p\n", __FUNCTION__, ruleTable); + return false; + } + + printf("%s(), Added Filtering rule to table %p\n", __FUNCTION__, ruleTable); + return true; +} + +bool Filtering::DeleteFilteringRule(struct ipa_ioc_del_flt_rule *ruleTable) +{ + int retval = 0; + + retval = ioctl(m_fd, IPA_IOC_DEL_FLT_RULE, ruleTable); + if (retval) { + printf("%s(), failed deleting Filtering rule in table %p\n", __FUNCTION__, ruleTable); + return false; + } + + printf("%s(), Deleted Filtering rule in table %p\n", __FUNCTION__, ruleTable); + return true; +} + +bool Filtering::Commit(enum ipa_ip_type ip) +{ + int retval = 0; + + retval = ioctl(m_fd, IPA_IOC_COMMIT_FLT, ip); + if (retval) { + printf("%s(), failed committing Filtering rules.\n", __FUNCTION__); + return false; + } + + printf("%s(), Committed Filtering rules to IPA HW.\n", __FUNCTION__); + return true; +} + +bool Filtering::Reset(enum ipa_ip_type ip) +{ + int retval = 0; + + retval = ioctl(m_fd, IPA_IOC_RESET_FLT, ip); + retval |= ioctl(m_fd, IPA_IOC_COMMIT_FLT, ip); + if (retval) { + printf("%s(), failed resetting Filtering block.\n", __FUNCTION__); + return false; + } + + printf("%s(), Reset command issued to IPA Filtering block.\n", __FUNCTION__); + return true; +} + diff --git a/qcom/opensource/dataipa/kernel-tests/Filtering.h b/qcom/opensource/dataipa/kernel-tests/Filtering.h new file mode 100644 index 0000000000..08e618684c --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/Filtering.h @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2017,2020 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Changes from Qualcomm Innovation Center are provided under the following license: + * + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * * Neither the name of Qualcomm Innovation Center, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + */ + +#ifndef FILTERING_H_ +#define FILTERING_H_ + +#include +#include "linux/msm_ipa.h" +#include "Feature.h" + +class Filtering: public Feature +{ +public: + bool AddFilteringRule(struct ipa_ioc_add_flt_rule const *ruleTable); + bool AddFilteringRule(ipa_ioc_add_flt_rule_v2 const *ruleTable); + bool DeleteFilteringRule(struct ipa_ioc_del_flt_rule *ruleTable); + bool Commit(enum ipa_ip_type ip); + bool Reset(enum ipa_ip_type ip); +}; + +#endif + diff --git a/qcom/opensource/dataipa/kernel-tests/FilteringEthernetBridgingTestFixture.cpp b/qcom/opensource/dataipa/kernel-tests/FilteringEthernetBridgingTestFixture.cpp new file mode 100644 index 0000000000..715b88aa8f --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/FilteringEthernetBridgingTestFixture.cpp @@ -0,0 +1,513 @@ +/* + * Copyright (c) 2017 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "FilteringEthernetBridgingTestFixture.h" + +IpaFilteringEthernetBridgingTestFixture::IpaFilteringEthernetBridgingTestFixture(): + m_sendSize1 (m_BUFF_MAX_SIZE), + m_sendSize2 (m_BUFF_MAX_SIZE), + m_sendSize3 (m_BUFF_MAX_SIZE), + m_IpaIPType(IPA_IP_v4) +{ + memset(m_sendBuffer1, 0, sizeof(m_sendBuffer1)); + memset(m_sendBuffer2, 0, sizeof(m_sendBuffer2)); + memset(m_sendBuffer3, 0, sizeof(m_sendBuffer3)); + m_testSuiteName.push_back("FilteringEth"); +} + +bool IpaFilteringEthernetBridgingTestFixture::Setup() +{ + ConfigureScenario(PHASE_TWO_TEST_CONFIGURATION); + + m_producer.Open(INTERFACE0_TO_IPA_DATA_PATH, INTERFACE0_FROM_IPA_DATA_PATH); + m_producer2.Open(INTERFACE4_TO_IPA_DATA_PATH, INTERFACE4_FROM_IPA_DATA_PATH); + + m_consumer.Open(INTERFACE1_TO_IPA_DATA_PATH, INTERFACE1_FROM_IPA_DATA_PATH); + m_consumer2.Open(INTERFACE2_TO_IPA_DATA_PATH, INTERFACE2_FROM_IPA_DATA_PATH); + m_defaultConsumer.Open(INTERFACE3_TO_IPA_DATA_PATH, INTERFACE3_FROM_IPA_DATA_PATH); + + if (!m_routing.DeviceNodeIsOpened()) + { + LOG_MSG_ERROR("Routing block is not ready for immediate commands!\n"); + return false; + } + + if (!m_filtering.DeviceNodeIsOpened()) + { + LOG_MSG_ERROR("Filtering block is not ready for immediate commands!\n"); + return false; + } + m_routing.Reset(IPA_IP_v4); + m_routing.Reset(IPA_IP_v6); + return true; +} // Setup() + +bool IpaFilteringEthernetBridgingTestFixture::Teardown() +{ + m_producer.Close(); + m_producer2.Close(); + m_consumer.Close(); + m_consumer2.Close(); + m_defaultConsumer.Close(); + return true; +} // Teardown() + +bool IpaFilteringEthernetBridgingTestFixture::LoadFiles(enum ipa_ip_type ip) +{ + if (!LoadDefaultEth2Packet(ip, m_sendBuffer1, m_sendSize1)) { + LOG_MSG_ERROR("Failed default Packet\n"); + return false; + } + LOG_MSG_DEBUG ("Loaded %zu Bytes to Buffer 1\n",m_sendSize1); + + if (!LoadDefaultEth2Packet(ip, m_sendBuffer2, m_sendSize2)) { + LOG_MSG_ERROR("Failed default Packet\n"); + return false; + } + LOG_MSG_DEBUG ("Loaded %zu Bytes to Buffer 2\n",m_sendSize2); + + if (!LoadDefaultEth2Packet(ip, m_sendBuffer3, m_sendSize3)) { + LOG_MSG_ERROR("Failed default Packet\n"); + return false; + } + LOG_MSG_DEBUG ("Loaded %zu Bytes to Buffer 3\n",m_sendSize3); + + return true; +} + +bool IpaFilteringEthernetBridgingTestFixture::ReceivePacketsAndCompare() +{ + size_t receivedSize = 0; + size_t receivedSize2 = 0; + size_t receivedSize3 = 0; + bool isSuccess = true; + + // Receive results + Byte *rxBuff1 = new Byte[m_BUFF_MAX_SIZE]; + Byte *rxBuff2 = new Byte[m_BUFF_MAX_SIZE]; + Byte *rxBuff3 = new Byte[m_BUFF_MAX_SIZE]; + + if (NULL == rxBuff1 || NULL == rxBuff2 || NULL == rxBuff3) + { + printf("Memory allocation error.\n"); + return false; + } + + receivedSize = m_consumer.ReceiveData(rxBuff1, + m_BUFF_MAX_SIZE); + LOG_MSG_DEBUG("Received %zu bytes on %s.\n", + receivedSize, + m_consumer.m_fromChannelName.c_str()); + + receivedSize2 = m_consumer2.ReceiveData(rxBuff2, + m_BUFF_MAX_SIZE); + LOG_MSG_DEBUG("Received %zu bytes on %s.\n", + receivedSize2, + m_consumer2.m_fromChannelName.c_str()); + + receivedSize3 = m_defaultConsumer.ReceiveData(rxBuff3, + m_BUFF_MAX_SIZE); + LOG_MSG_DEBUG("Received %zu bytes on %s.\n", + receivedSize3, + m_defaultConsumer.m_fromChannelName.c_str()); + + // Compare results + if (!CompareResultVsGolden(m_sendBuffer1, + m_sendSize1, + rxBuff1, + receivedSize)) + { + LOG_MSG_ERROR("Comparison of Buffer0 Failed!"); + isSuccess = false; + } + + char recievedBuffer[256] = {0}; + char SentBuffer[256] = {0}; + + size_t j; + for(j = 0; j < m_sendSize1; j++) + snprintf(&SentBuffer[3*j], sizeof(SentBuffer) - (3*j + 1), " %02X", m_sendBuffer1[j]); + for(j = 0; j < receivedSize; j++) + snprintf(&recievedBuffer[3*j], sizeof(recievedBuffer) - (3*j + 1), " %02X", rxBuff1[j]); + printf("Expected Value1 (%zu)\n%s\n, Received Value1(%zu)\n%s\n", + m_sendSize1,SentBuffer,receivedSize,recievedBuffer); + recievedBuffer[0] = 0; + + for(j = 0; j < m_sendSize2; j++) + snprintf(&SentBuffer[3 * j], sizeof(SentBuffer) - (3*j + 1), " %02X", m_sendBuffer2[j]); + for(j = 0; j < receivedSize2; j++) + snprintf(&recievedBuffer[3*j], sizeof(recievedBuffer) - (3*j + 1), " %02X", rxBuff2[j]); + printf("Expected Value2 (%zu)\n%s\n, Received Value2(%zu)\n%s\n", + m_sendSize2,SentBuffer,receivedSize2,recievedBuffer); + recievedBuffer[0] = 0; + + for(j = 0; j < m_sendSize3; j++) + snprintf(&SentBuffer[3*j], sizeof(SentBuffer) - (3*j + 1), " %02X", m_sendBuffer3[j]); + for(j = 0; j < receivedSize3; j++) + snprintf(&recievedBuffer[3*j], sizeof(recievedBuffer) - (3*j + 1), " %02X", rxBuff3[j]); + printf("Expected Value3 (%zu)\n%s\n, Received Value3(%zu)\n%s\n", + m_sendSize3,SentBuffer,receivedSize3,recievedBuffer); + recievedBuffer[0] = 0; + + isSuccess &= CompareResultVsGolden(m_sendBuffer2, + m_sendSize2, rxBuff2, receivedSize2); + isSuccess &= CompareResultVsGolden(m_sendBuffer3, + m_sendSize3, rxBuff3, receivedSize3); + + delete[] rxBuff1; + delete[] rxBuff2; + delete[] rxBuff3; + + return isSuccess; +} + +// This function creates three IPv4 bypass routing entries and commits them. +bool IpaFilteringEthernetBridgingTestFixture::CreateThreeIPv4BypassRoutingTables(const char *bypass0, const char *bypass1, + const char *bypass2) +{ + LOG_MSG_DEBUG("Entering"); + struct ipa_ioc_add_rt_rule *rt_rule0 = 0, *rt_rule1 = 0,*rt_rule2 = 0; + struct ipa_rt_rule_add *rt_rule_entry; + + rt_rule0 = (struct ipa_ioc_add_rt_rule *) + calloc(1, sizeof(struct ipa_ioc_add_rt_rule) + + 1*sizeof(struct ipa_rt_rule_add)); + if(!rt_rule0) { + LOG_MSG_ERROR("calloc failed to allocate rt_rule0"); + return false; + } + rt_rule1 = (struct ipa_ioc_add_rt_rule *) + calloc(1, sizeof(struct ipa_ioc_add_rt_rule) + + 1*sizeof(struct ipa_rt_rule_add)); + if(!rt_rule1) { + LOG_MSG_ERROR("calloc failed to allocate rt_rule1"); + Free(rt_rule0); + return false; + } + rt_rule2 = (struct ipa_ioc_add_rt_rule *) + calloc(1, sizeof(struct ipa_ioc_add_rt_rule) + + 1*sizeof(struct ipa_rt_rule_add)); + if(!rt_rule2) { + LOG_MSG_ERROR("calloc failed to allocate rt_rule2"); + Free(rt_rule0); + Free(rt_rule1); + return false; + } + + rt_rule0->num_rules = 1; + rt_rule0->ip = IPA_IP_v4; + rt_rule0->commit = true; + strlcpy(rt_rule0->rt_tbl_name, bypass0, sizeof(rt_rule0->rt_tbl_name)); + + rt_rule_entry = &rt_rule0->rules[0]; + rt_rule_entry->at_rear = 0; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST2_CONS; + + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v4.dst_addr = 0xaabbccdd; + rt_rule_entry->rule.attrib.u.v4.dst_addr_mask = 0x00000000;// All Packets will get a "Hit" + if (false == m_routing.AddRoutingRule(rt_rule0)) + { + LOG_MSG_ERROR("Routing rule addition(rt_rule0) failed!\n"); + Free (rt_rule2); + Free (rt_rule1); + Free (rt_rule0); + return false; + } + + rt_rule1->num_rules = 1; + rt_rule1->ip = IPA_IP_v4; + rt_rule1->commit = true; + strlcpy(rt_rule1->rt_tbl_name, bypass1, sizeof(rt_rule1->rt_tbl_name)); + rt_rule_entry = &rt_rule1->rules[0]; + rt_rule_entry->at_rear = 0; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST3_CONS; + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v4.dst_addr = 0xaabbccdd; + rt_rule_entry->rule.attrib.u.v4.dst_addr_mask = 0x00000000;// All Packets will get a "Hit" + if (false == m_routing.AddRoutingRule(rt_rule1)) + { + LOG_MSG_ERROR("Routing rule addition(rt_rule1) failed!\n"); + Free (rt_rule2); + Free (rt_rule1); + Free (rt_rule0); + return false; + } + + + rt_rule2->num_rules = 1; + rt_rule2->ip = IPA_IP_v4; + rt_rule2->commit = true; + strlcpy(rt_rule2->rt_tbl_name, bypass2, sizeof(rt_rule2->rt_tbl_name)); + rt_rule_entry = &rt_rule2->rules[0]; + rt_rule_entry->at_rear = 0; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST4_CONS; + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v4.dst_addr = 0xaabbccdd; + rt_rule_entry->rule.attrib.u.v4.dst_addr_mask = 0x00000000;// All Packets will get a "Hit" + if (false == m_routing.AddRoutingRule(rt_rule2)) + { + LOG_MSG_ERROR("Routing rule addition(rt_rule2)\n"); + Free (rt_rule2); + Free (rt_rule1); + Free (rt_rule0); + return false; + } + + Free (rt_rule2); + Free (rt_rule1); + Free (rt_rule0); + LOG_MSG_DEBUG("Leaving"); + return true; +} + +// This function creates three IPv6 bypass routing entries and commits them. +bool IpaFilteringEthernetBridgingTestFixture::CreateThreeIPv6BypassRoutingTables (const char *bypass0, const char *bypass1, + const char *bypass2) +{ + LOG_MSG_DEBUG("Entering"); + struct ipa_ioc_add_rt_rule *rt_rule0 = 0, *rt_rule1 = 0, + *rt_rule2 = 0; + struct ipa_rt_rule_add *rt_rule_entry; + + rt_rule0 = (struct ipa_ioc_add_rt_rule *) + calloc(1,sizeof(struct ipa_ioc_add_rt_rule) + + 1*sizeof(struct ipa_rt_rule_add)); + if(!rt_rule0) { + LOG_MSG_ERROR("calloc failed to allocate rt_rule0\n"); + return false; + } + rt_rule1 = (struct ipa_ioc_add_rt_rule *) + calloc(1,sizeof(struct ipa_ioc_add_rt_rule) + + 1*sizeof(struct ipa_rt_rule_add)); + if(!rt_rule1) { + LOG_MSG_ERROR("calloc failed to allocate rt_rule1\n"); + Free(rt_rule0); + return false; + } + rt_rule2 = (struct ipa_ioc_add_rt_rule *) + calloc(1,sizeof(struct ipa_ioc_add_rt_rule) + + 1*sizeof(struct ipa_rt_rule_add)); + if(!rt_rule2) { + LOG_MSG_ERROR("calloc failed to allocate rt_rule2\n"); + Free(rt_rule0); + Free(rt_rule1); + return false; + } + + rt_rule0->num_rules = 1; + rt_rule0->ip = IPA_IP_v6; + rt_rule0->commit = true; + strlcpy(rt_rule0->rt_tbl_name, bypass0, sizeof(rt_rule0->rt_tbl_name)); + + rt_rule_entry = &rt_rule0->rules[0]; + rt_rule_entry->at_rear = 0; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST2_CONS; + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v6.dst_addr[0] = 0xaabbccdd; + rt_rule_entry->rule.attrib.u.v6.dst_addr[1] = 0xeeff0011; + rt_rule_entry->rule.attrib.u.v6.dst_addr[2] = 0x22334455; + rt_rule_entry->rule.attrib.u.v6.dst_addr[3] = 0x66778899; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[0] = 0x00000000;// All Packets will get a "Hit" + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[1] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[2] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[3] = 0x00000000; + if (false == m_routing.AddRoutingRule(rt_rule0)) + { + LOG_MSG_ERROR("Routing rule addition(rt_rule0)"); + Free (rt_rule2); + Free (rt_rule1); + Free (rt_rule0); + return false; + } + + rt_rule1->num_rules = 1; + rt_rule1->ip = IPA_IP_v6; + rt_rule1->commit = true; + strlcpy(rt_rule1->rt_tbl_name, bypass1, sizeof(rt_rule1->rt_tbl_name)); + rt_rule_entry = &rt_rule1->rules[0]; + rt_rule_entry->at_rear = 0; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST3_CONS; + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v6.dst_addr[0] = 0xaabbccdd; + rt_rule_entry->rule.attrib.u.v6.dst_addr[1] = 0xeeff0011; + rt_rule_entry->rule.attrib.u.v6.dst_addr[2] = 0x22334455; + rt_rule_entry->rule.attrib.u.v6.dst_addr[3] = 0x66778899; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[0] = 0x00000000;// All Packets will get a "Hit" + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[1] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[2] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[3] = 0x00000000; + if (false == m_routing.AddRoutingRule(rt_rule1)) + { + LOG_MSG_ERROR("Routing rule addition(rt_rule1)"); + Free (rt_rule2); + Free (rt_rule1); + Free (rt_rule0); + return false; + } + + rt_rule2->num_rules = 1; + rt_rule2->ip = IPA_IP_v6; + rt_rule2->commit = true; + strlcpy(rt_rule2->rt_tbl_name, bypass2, sizeof(rt_rule2->rt_tbl_name)); + rt_rule_entry = &rt_rule2->rules[0]; + rt_rule_entry->at_rear = 0; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST4_CONS; + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v6.dst_addr[0] = 0xaabbccdd; + rt_rule_entry->rule.attrib.u.v6.dst_addr[1] = 0xeeff0011; + rt_rule_entry->rule.attrib.u.v6.dst_addr[2] = 0x22334455; + rt_rule_entry->rule.attrib.u.v6.dst_addr[3] = 0x66778899; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[0] = 0x00000000;// All Packets will get a "Hit" + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[1] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[2] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[3] = 0x00000000; + if (false == m_routing.AddRoutingRule(rt_rule2)) + { + LOG_MSG_ERROR("Routing rule addition(rt_rule2)"); + Free (rt_rule2); + Free (rt_rule1); + Free (rt_rule0); + return false; + } + + Free (rt_rule2); + Free (rt_rule1); + Free (rt_rule0); + LOG_MSG_DEBUG("Leaving function\n"); + return true; +} + +bool IpaFilteringEthernetBridgingTestFixture::Run() +{ + bool res = false; + bool isSuccess = false; + + LOG_MSG_DEBUG("Entering"); + + // Add the relevant filtering rules + res = AddRules(); + if (false == res) { + LOG_MSG_ERROR("Failed adding filtering rules"); + return false; + } + + // Load input data (IP packet) from file + res = LoadFiles(m_IpaIPType); + if (false == res) { + LOG_MSG_ERROR("Failed loading files"); + return false; + } + + res = ModifyPackets(); + if (false == res) { + LOG_MSG_ERROR("Failed to modify packets"); + return false; + } + + // Send first packet + isSuccess = m_pCurrentProducer->SendData(m_sendBuffer1, + m_sendSize1); + if (false == isSuccess) + { + LOG_MSG_ERROR("SendData failure"); + return false; + } + + // Send second packet + isSuccess = m_pCurrentProducer->SendData(m_sendBuffer2, + m_sendSize2); + if (false == isSuccess) + { + LOG_MSG_ERROR("SendData failure"); + return false; + } + + // Send third packet + isSuccess = m_pCurrentProducer->SendData(m_sendBuffer3, + m_sendSize3); + if (false == isSuccess) + { + LOG_MSG_ERROR("SendData failure"); + return false; + } + + // Receive packets from the channels and compare results + isSuccess = ReceivePacketsAndCompare(); + + LOG_MSG_DEBUG("Leaving function returning %d", isSuccess); + + return isSuccess; +} // Run() + + +IpaFilteringEthernetBridgingTestFixture::~IpaFilteringEthernetBridgingTestFixture() +{ + m_sendSize1 = 0; + m_sendSize2 = 0; + m_sendSize3 = 0; +} + +static const size_t m_BUFF_MAX_SIZE = 1024; +static Filtering m_filtering; +static RoutingDriverWrapper m_routing; + +InterfaceAbstraction m_producer; +InterfaceAbstraction m_producer2; // Pipe with ETH2 header removal +InterfaceAbstraction *m_pCurrentProducer; +InterfaceAbstraction m_consumer; +InterfaceAbstraction m_consumer2; +InterfaceAbstraction m_defaultConsumer; + +Byte m_sendBuffer1[m_BUFF_MAX_SIZE]; +Byte m_sendBuffer2[m_BUFF_MAX_SIZE]; +Byte m_sendBuffer3[m_BUFF_MAX_SIZE]; +size_t m_sendSize1; +size_t m_sendSize2; +size_t m_sendSize3; +enum ipa_ip_type m_IpaIPType; + +RoutingDriverWrapper IpaFilteringEthernetBridgingTestFixture::m_routing; +Filtering IpaFilteringEthernetBridgingTestFixture::m_filtering; + +const uint8_t IpaFilteringEthernetBridgingTestFixture::m_ETH2_DST_ADDR[ETH_ALEN] = +{ + 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0x11 +}; + +const uint8_t IpaFilteringEthernetBridgingTestFixture::m_ETH2_SRC_ADDR[ETH_ALEN] = +{ + 0x22, 0xee, 0xdd, 0xcc, 0xbb, 0xaa +}; + +const uint8_t IpaFilteringEthernetBridgingTestFixture::m_MAC_ADDR_MASK_ALL[ETH_ALEN] = +{ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff +}; + diff --git a/qcom/opensource/dataipa/kernel-tests/FilteringEthernetBridgingTestFixture.h b/qcom/opensource/dataipa/kernel-tests/FilteringEthernetBridgingTestFixture.h new file mode 100644 index 0000000000..b7340e8abb --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/FilteringEthernetBridgingTestFixture.h @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2017 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include // for memcpy +#include "hton.h" // for htonl +#include "InterfaceAbstraction.h" +#include "Constants.h" +#include "Logger.h" +#include "TestsUtils.h" +#include "Filtering.h" +#include "RoutingDriverWrapper.h" +#include "IPAFilteringTable.h" + +#define IPV4_DST_ADDR_OFFSET (16) +#define IPV4_SRC_PORT_OFFSET (20) +#define IPV4_DST_PORT_OFFSET (20+2) + +#define DST_ADDR_LSB_OFFSET_IPV4 (19) +#define DST_ADDR_LSB_OFFSET_IPV6 (39) + +class IpaFilteringEthernetBridgingTestFixture : public TestBase +{ +public: + virtual bool ModifyPackets() = 0; + virtual bool AddRules() = 0; + + IpaFilteringEthernetBridgingTestFixture(); + + bool Setup(); + + bool Teardown(); + + virtual bool LoadFiles(enum ipa_ip_type ip); + + bool ReceivePacketsAndCompare(); + + // This function creates three IPv4 bypass routing entries and commits them. + bool CreateThreeIPv4BypassRoutingTables (const char *bypass0, const char *bypass1, + const char *bypass2); + + // This function creates three IPv6 bypass routing entries and commits them. + bool CreateThreeIPv6BypassRoutingTables (const char *bypass0, const char *bypass1, + const char *bypass2); + + bool Run(); + + ~IpaFilteringEthernetBridgingTestFixture(); + + static const size_t m_BUFF_MAX_SIZE = 1024; + static const uint8_t m_ETH2_DST_ADDR[ETH_ALEN]; + static const uint8_t m_ETH2_SRC_ADDR[ETH_ALEN]; + static const uint8_t m_MAC_ADDR_MASK_ALL[ETH_ALEN]; + static Filtering m_filtering; + static RoutingDriverWrapper m_routing; + + InterfaceAbstraction m_producer; + InterfaceAbstraction m_producer2; // Pipe with ETH2 header removal + InterfaceAbstraction *m_pCurrentProducer; + InterfaceAbstraction m_consumer; + InterfaceAbstraction m_consumer2; + InterfaceAbstraction m_defaultConsumer; + + Byte m_sendBuffer1[m_BUFF_MAX_SIZE]; + Byte m_sendBuffer2[m_BUFF_MAX_SIZE]; + Byte m_sendBuffer3[m_BUFF_MAX_SIZE]; + size_t m_sendSize1; + size_t m_sendSize2; + size_t m_sendSize3; + enum ipa_ip_type m_IpaIPType; + +private: +}; + diff --git a/qcom/opensource/dataipa/kernel-tests/FilteringEthernetBridgingTests.cpp b/qcom/opensource/dataipa/kernel-tests/FilteringEthernetBridgingTests.cpp new file mode 100644 index 0000000000..9f01a946ed --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/FilteringEthernetBridgingTests.cpp @@ -0,0 +1,700 @@ +/* + * Copyright (c) 2017 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "FilteringEthernetBridgingTestFixture.h" + +/*---------------------------------------------------------------------------*/ +/* Test 00: Destination IP address and subnet mask match against LAN subnet */ +/*---------------------------------------------------------------------------*/ +class IpaFilterEthIPv4Test00 : public IpaFilteringEthernetBridgingTestFixture +{ +public: + IpaFilterEthIPv4Test00() + { + m_name = "IpaFilterEthIPv4Test00"; + m_description = + "Filtering block test 01 - Ethernet Bridge, ETH2 filters, \ + IPv4 address (EP Filtering Table, \ + Insert all rules in a single commit) \ + 1. Generate and commit three routing tables. \ + Each table contains a single \"bypass\" rule \ + (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit 3 ETH2 filtering rules: \ + All MAC DST == (aabbccddee11) traffic goes to routing table 0 \ + All MAC SRC == (22eeddccbbaa) traffic goes to routing table 1 \ + All (1) traffic goes to routing table 2"; + m_minIPAHwType = IPA_HW_v2_5; + m_maxIPAHwType = IPA_HW_MAX; + Register(*this); + m_pCurrentProducer = &m_producer2; + } + + virtual bool AddRules() + { + LOG_MSG_DEBUG("Entering"); + + const char bypass0[] = "bypass0"; + const char bypass1[] = "bypass1"; + const char bypass2[] = "bypass2"; + struct ipa_ioc_get_rt_tbl routing_table0,routing_table1,routing_table2; + + if (!CreateThreeIPv4BypassRoutingTables (bypass0,bypass1,bypass2)) + { + printf("CreateThreeIPv4BypassRoutingTables"); + return false; + } + + routing_table0.ip = IPA_IP_v4; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + LOG_MSG_ERROR( + "m_routing.GetRoutingTable(&routing_table0=0x%p)", + &routing_table0); + return false; + } + routing_table1.ip = IPA_IP_v4; + strlcpy(routing_table1.name, bypass1, sizeof(routing_table1.name)); + if (!m_routing.GetRoutingTable(&routing_table1)) + { + LOG_MSG_ERROR( + "m_routing.GetRoutingTable(&routing_table1=0x%p)", + &routing_table1); + return false; + } + + routing_table2.ip = IPA_IP_v4; + strlcpy(routing_table2.name, bypass2, sizeof(routing_table2.name)); + if (!m_routing.GetRoutingTable(&routing_table2)) + { + LOG_MSG_ERROR( + "m_routing.GetRoutingTable(&routing_table2=0x%p)", + &routing_table2); + return false; + } + + // Create 3 filter rules + IPAFilteringTable FilterTable0; + struct ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v4,IPA_CLIENT_TEST2_PROD,false,3); + + // Configuring Filtering Rule 0 - ETH2 DST + FilterTable0.GeneratePresetRule(1,flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.rule.retain_hdr = 1; // retain header removed in producer pipe + flt_rule_entry.flt_rule_hdl = -1; // return value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action = IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.rt_tbl_hdl = routing_table0.hdl; // Handle corresponding to routing table 0 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_MAC_DST_ADDR_ETHER_II; // Filter using ETH2 DST address + memcpy(flt_rule_entry.rule.attrib.dst_mac_addr_mask, + m_MAC_ADDR_MASK_ALL, + sizeof(flt_rule_entry.rule.attrib.dst_mac_addr_mask)); // ETH2 DST address mask + memcpy(flt_rule_entry.rule.attrib.dst_mac_addr, + m_ETH2_DST_ADDR, + sizeof(flt_rule_entry.rule.attrib.dst_mac_addr)); // ETH2 DST address + + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + LOG_MSG_ERROR ("Adding RuleTable(0) to Filtering"); + return false; + } else + { + LOG_MSG_DEBUG("flt rule hdl0=0x%x, status=0x%x", + FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl, + FilterTable0.ReadRuleFromTable(0)->status); + } + + // Configuring Filtering Rule 1 - ETH2 SRC + flt_rule_entry.rule.rt_tbl_hdl=routing_table1.hdl; // Handle corresponding to routing table 1 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_MAC_SRC_ADDR_ETHER_II; // Filter using ETH2 SRC address + memcpy(flt_rule_entry.rule.attrib.src_mac_addr_mask, + m_MAC_ADDR_MASK_ALL, + sizeof(flt_rule_entry.rule.attrib.src_mac_addr_mask)); // ETH2 SRC address mask + memcpy(flt_rule_entry.rule.attrib.src_mac_addr, + m_ETH2_SRC_ADDR, + sizeof(flt_rule_entry.rule.attrib.src_mac_addr)); // ETH2 SRC address + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + LOG_MSG_ERROR ("Adding RuleTable(1) to Filtering"); + return false; + } else + { + LOG_MSG_DEBUG("flt rule hdl0=0x%x, status=0x%x", + FilterTable0.ReadRuleFromTable(1)->flt_rule_hdl, + FilterTable0.ReadRuleFromTable(1)->status); + } + + // Configuring Filtering Rule 2 - Accept all + flt_rule_entry.rule.rt_tbl_hdl = routing_table2.hdl; + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + flt_rule_entry.rule.attrib.u.v4.dst_addr_mask = 0x00000000; // Accept all + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0x00000000; // Has no effect + if (((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable())) + { + LOG_MSG_ERROR ("Adding RuleTable(2) to Filtering"); + return false; + } else + { + LOG_MSG_DEBUG("flt rule hdl0=0x%x, status=0x%x", + FilterTable0.ReadRuleFromTable(2)->flt_rule_hdl, + FilterTable0.ReadRuleFromTable(2)->status); + } + LOG_MSG_DEBUG("Leaving function\n"); + return true; + + }// AddRules() + + virtual bool ModifyPackets() + { + memcpy(&m_sendBuffer1[ETH2_DST_ADDR_OFFSET], + m_ETH2_DST_ADDR, ETH_ALEN); + + memcpy(&m_sendBuffer2[ETH2_DST_ADDR_OFFSET], + m_ETH2_DST_ADDR, ETH_ALEN); + m_sendBuffer2[ETH2_DST_ADDR_OFFSET] = 0x00; + memcpy(&m_sendBuffer2[ETH2_SRC_ADDR_OFFSET], + m_ETH2_SRC_ADDR, ETH_ALEN); + + // swap destination and source addresses so that both + // rule0 and rule1 are miss and rule2 (accept all) is hit + memcpy(&m_sendBuffer3[ETH2_DST_ADDR_OFFSET], + m_ETH2_SRC_ADDR, ETH_ALEN); + memcpy(&m_sendBuffer3[ETH2_SRC_ADDR_OFFSET], + m_ETH2_DST_ADDR, ETH_ALEN); + + return true; + }// ModifyPacktes () +}; + +/*---------------------------------------------------------------------------*/ +/* Test 01: Destination IP address and subnet mask match against LAN subnet */ +/*---------------------------------------------------------------------------*/ +class IpaFilterEthIPv4Test01 : public IpaFilteringEthernetBridgingTestFixture +{ +public: + IpaFilterEthIPv4Test01() + { + m_name = "IpaFilterEthIPv4Test01"; + m_description = + "Filtering block test 01 - Ethernet Bridge, ETH2 filters, \ + IPv4 address (EP Filtering Table, \ + Insert all rules in a single commit) \ + 1. Generate and commit three routing tables. \ + Each table contains a single \"bypass\" rule \ + (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit 3 ETH2 filtering rules: \ + All MAC DST == (aabbccddee11) traffic goes to routing table 0 \ + All MAC ETH TYPE == (0800) traffic goes to routing table 1 \ + All (1) traffic goes to routing table 2"; + m_minIPAHwType = IPA_HW_v2_5; + m_maxIPAHwType = IPA_HW_MAX; + Register(*this); + m_pCurrentProducer = &m_producer2; + } + + virtual bool AddRules() + { + LOG_MSG_DEBUG("Entering"); + + const char bypass0[] = "bypass0"; + const char bypass1[] = "bypass1"; + const char bypass2[] = "bypass2"; + struct ipa_ioc_get_rt_tbl routing_table0,routing_table1,routing_table2; + + if (!CreateThreeIPv4BypassRoutingTables (bypass0,bypass1,bypass2)) + { + printf("CreateThreeIPv4BypassRoutingTables"); + return false; + } + + routing_table0.ip = IPA_IP_v4; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + LOG_MSG_ERROR( + "m_routing.GetRoutingTable(&routing_table0=0x%p)", + &routing_table0); + return false; + } + routing_table1.ip = IPA_IP_v4; + strlcpy(routing_table1.name, bypass1, sizeof(routing_table1.name)); + if (!m_routing.GetRoutingTable(&routing_table1)) + { + LOG_MSG_ERROR("m_routing.GetRoutingTable(&routing_table1=0x%p)", + &routing_table1); + return false; + } + + routing_table2.ip = IPA_IP_v4; + strlcpy(routing_table2.name, bypass2, sizeof(routing_table2.name)); + if (!m_routing.GetRoutingTable(&routing_table2)) + { + LOG_MSG_ERROR( + "m_routing.GetRoutingTable(&routing_table2=0x%p)", + &routing_table2); + return false; + } + + // Create 3 filter rules + IPAFilteringTable FilterTable0; + struct ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v4,IPA_CLIENT_TEST2_PROD,false,3); + + // Configuring Filtering Rule 0 - ETH2 DST + FilterTable0.GeneratePresetRule(1,flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.rule.retain_hdr = 1; // retain header removed in producer pipe + flt_rule_entry.flt_rule_hdl = -1; // return value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action = IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.rt_tbl_hdl = routing_table0.hdl; + + // DST + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_MAC_DST_ADDR_ETHER_II; + memcpy(flt_rule_entry.rule.attrib.dst_mac_addr_mask, + m_MAC_ADDR_MASK_ALL, + sizeof(flt_rule_entry.rule.attrib.dst_mac_addr_mask)); + memcpy(flt_rule_entry.rule.attrib.dst_mac_addr, + m_ETH2_DST_ADDR, + sizeof(flt_rule_entry.rule.attrib.dst_mac_addr)); + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + LOG_MSG_ERROR ("Adding RuleTable(0) to Filtering"); + return false; + } else + { + LOG_MSG_DEBUG("flt rule hdl0=0x%x, status=0x%x", + FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl, + FilterTable0.ReadRuleFromTable(0)->status); + } + + // Configuring Filtering Rule 1 - ETH2 type + flt_rule_entry.rule.rt_tbl_hdl=routing_table1.hdl; + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_MAC_ETHER_TYPE; + flt_rule_entry.rule.attrib.ether_type = ETH_P_IP; + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + LOG_MSG_ERROR ("Adding RuleTable(1) to Filtering"); + return false; + } else + { + LOG_MSG_DEBUG("flt rule hdl0=0x%x, status=0x%x", + FilterTable0.ReadRuleFromTable(1)->flt_rule_hdl, + FilterTable0.ReadRuleFromTable(1)->status); + } + + // Configuring Filtering Rule 2 - Accept all + flt_rule_entry.rule.rt_tbl_hdl = routing_table2.hdl; + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + flt_rule_entry.rule.attrib.u.v4.dst_addr_mask = 0x00000000; // Accept all + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0x00000000; // Has no effect + if (((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable())) + { + LOG_MSG_ERROR ("Adding RuleTable(2) to Filtering"); + return false; + } else + { + LOG_MSG_DEBUG("flt rule hdl0=0x%x, status=0x%x", + FilterTable0.ReadRuleFromTable(2)->flt_rule_hdl, + FilterTable0.ReadRuleFromTable(2)->status); + } + LOG_MSG_DEBUG("Leaving function\n"); + return true; + + }// AddRules() + + virtual bool ModifyPackets() + { + uint16_t ether_type = ETH_P_IP; + uint16_t wrong_ether_type = 0x1234; + + // DST && SRC correct + memcpy(&m_sendBuffer1[ETH2_DST_ADDR_OFFSET], + m_ETH2_DST_ADDR, ETH_ALEN); + memcpy(&m_sendBuffer1[ETH2_SRC_ADDR_OFFSET], + m_ETH2_SRC_ADDR, ETH_ALEN); + + // DST is wrong, ETH2 type is correct + memcpy(&m_sendBuffer2[ETH2_DST_ADDR_OFFSET], + m_ETH2_DST_ADDR, ETH_ALEN); + m_sendBuffer2[ETH2_DST_ADDR_OFFSET] = 0x00; + memcpy(&m_sendBuffer2[ETH2_ETH_TYPE_OFFSET], + ðer_type, sizeof(ether_type)); + + // DST is wrong, ETH2 type is wrong + memcpy(&m_sendBuffer3[ETH2_DST_ADDR_OFFSET], + m_ETH2_DST_ADDR, ETH_ALEN); + m_sendBuffer3[ETH2_DST_ADDR_OFFSET] = 0x00; + memcpy(&m_sendBuffer3[ETH2_ETH_TYPE_OFFSET], + &wrong_ether_type, sizeof(wrong_ether_type)); + + return true; + }// ModifyPacktes () +}; + +/*---------------------------------------------------------------------------*/ +/* Test 02: Destination IP address and subnet mask match against LAN subnet */ +/*---------------------------------------------------------------------------*/ +class IpaFilterEthIPv4Test02 : public IpaFilteringEthernetBridgingTestFixture +{ +public: + IpaFilterEthIPv4Test02() + { + m_name = "IpaFilterEthIPv4Test02"; + m_description = + "Filtering block test 02 - Ethernet Bridge, ETH2 filters, \ + IPv4 address (EP Filtering Table, \ + Insert all rules in a single commit) \ + 1. Generate and commit three routing tables. \ + Each table contains a single \"bypass\" rule \ + (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit 3 ETH2 filtering rules: \ + All MAC SRC == (22eeddccbbaa) traffic goes to routing table 0 \ + All MAC ETH TYPE == (0801) traffic goes to routing table 1 \ + All (1) traffic goes to routing table 2"; + m_minIPAHwType = IPA_HW_v2_5; + m_maxIPAHwType = IPA_HW_MAX; + Register(*this); + m_pCurrentProducer = &m_producer2; + } + + virtual bool AddRules() + { + LOG_MSG_DEBUG("Entering"); + + const char bypass0[] = "bypass0"; + const char bypass1[] = "bypass1"; + const char bypass2[] = "bypass2"; + struct ipa_ioc_get_rt_tbl routing_table0,routing_table1,routing_table2; + + if (!CreateThreeIPv4BypassRoutingTables (bypass0,bypass1,bypass2)) + { + printf("CreateThreeIPv4BypassRoutingTables"); + return false; + } + + routing_table0.ip = IPA_IP_v4; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + LOG_MSG_ERROR( + "m_routing.GetRoutingTable(&routing_table0=0x%p)", + &routing_table0); + return false; + } + routing_table1.ip = IPA_IP_v4; + strlcpy(routing_table1.name, bypass1, sizeof(routing_table1.name)); + if (!m_routing.GetRoutingTable(&routing_table1)) + { + LOG_MSG_ERROR("m_routing.GetRoutingTable(&routing_table1=0x%p)", + &routing_table1); + return false; + } + + routing_table2.ip = IPA_IP_v4; + strlcpy(routing_table2.name, bypass2, sizeof(routing_table2.name)); + if (!m_routing.GetRoutingTable(&routing_table2)) + { + LOG_MSG_ERROR( + "m_routing.GetRoutingTable(&routing_table2=0x%p)", + &routing_table2); + return false; + } + + // Create 3 filter rules + IPAFilteringTable FilterTable0; + struct ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v4,IPA_CLIENT_TEST2_PROD,false,3); + + // Configuring Filtering Rule 0 - ETH2 SRC + FilterTable0.GeneratePresetRule(1,flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.rule.retain_hdr = 1; // retain header removed in producer pipe + flt_rule_entry.flt_rule_hdl = -1; // return value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action = IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.rt_tbl_hdl = routing_table0.hdl; + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_MAC_SRC_ADDR_ETHER_II; + memcpy(flt_rule_entry.rule.attrib.src_mac_addr_mask, + m_MAC_ADDR_MASK_ALL, + sizeof(flt_rule_entry.rule.attrib.src_mac_addr_mask)); + memcpy(flt_rule_entry.rule.attrib.src_mac_addr, + m_ETH2_SRC_ADDR, + sizeof(flt_rule_entry.rule.attrib.src_mac_addr)); + + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + LOG_MSG_ERROR ("Adding RuleTable(0) to Filtering"); + return false; + } else + { + LOG_MSG_DEBUG("flt rule hdl0=0x%x, status=0x%x", + FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl, + FilterTable0.ReadRuleFromTable(0)->status); + } + + // Configuring Filtering Rule 1 - ETH2 type + flt_rule_entry.rule.rt_tbl_hdl=routing_table1.hdl; + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_MAC_ETHER_TYPE; + flt_rule_entry.rule.attrib.ether_type = ETH_P_IP + 1; + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + LOG_MSG_ERROR ("Adding RuleTable(1) to Filtering"); + return false; + } else + { + LOG_MSG_DEBUG("flt rule hdl0=0x%x, status=0x%x", + FilterTable0.ReadRuleFromTable(1)->flt_rule_hdl, + FilterTable0.ReadRuleFromTable(1)->status); + } + + // Configuring Filtering Rule 2 - Accept all + flt_rule_entry.rule.rt_tbl_hdl = routing_table2.hdl; + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + flt_rule_entry.rule.attrib.u.v4.dst_addr_mask = 0x00000000; // Accept all + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0x00000000; // Has no effect + if (((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable())) + { + LOG_MSG_ERROR ("Adding RuleTable(2) to Filtering"); + return false; + } else + { + LOG_MSG_DEBUG("flt rule hdl0=0x%x, status=0x%x", + FilterTable0.ReadRuleFromTable(2)->flt_rule_hdl, + FilterTable0.ReadRuleFromTable(2)->status); + } + LOG_MSG_DEBUG("Leaving function\n"); + return true; + + }// AddRules() + + virtual bool ModifyPackets() + { + uint16_t ether_type = ETH_P_IP; + uint16_t wrong_ether_type = 0x1234; + + memcpy(&m_sendBuffer1[ETH2_SRC_ADDR_OFFSET], + m_ETH2_SRC_ADDR, ETH_ALEN); + memcpy(&m_sendBuffer1[ETH2_ETH_TYPE_OFFSET], + ðer_type, sizeof(ether_type)); + + memcpy(&m_sendBuffer2[ETH2_SRC_ADDR_OFFSET], + m_ETH2_SRC_ADDR, ETH_ALEN); + m_sendBuffer2[ETH2_SRC_ADDR_OFFSET] = 0x00; + memcpy(&m_sendBuffer2[ETH2_DST_ADDR_OFFSET], + m_ETH2_DST_ADDR, ETH_ALEN); + ether_type++; + memcpy(&m_sendBuffer2[ETH2_ETH_TYPE_OFFSET], + ðer_type, sizeof(ether_type)); + + memcpy(&m_sendBuffer3[ETH2_DST_ADDR_OFFSET], + m_ETH2_SRC_ADDR, ETH_ALEN); + memcpy(&m_sendBuffer3[ETH2_SRC_ADDR_OFFSET], + m_ETH2_DST_ADDR, ETH_ALEN); + memcpy(&m_sendBuffer3[ETH2_ETH_TYPE_OFFSET], + &wrong_ether_type, sizeof(wrong_ether_type)); + + return true; + }// ModifyPacktes () +}; + +/*---------------------------------------------------------------------------*/ +/* Test 03: Destination IP address and subnet mask match against LAN subnet */ +/*---------------------------------------------------------------------------*/ +class IpaFilterEthIPv4Test03 : public IpaFilteringEthernetBridgingTestFixture +{ +public: + IpaFilterEthIPv4Test03() + { + m_name = "IpaFilterEthIPv4Test03"; + m_description = + "Filtering block test 03 - Ethernet Bridge, ETH2 filters, \ + IPv4 address (EP Filtering Table, \ + Insert all rules in a single commit) \ + 1. Generate and commit three routing tables. \ + Each table contains a single \"bypass\" rule \ + (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit 3 ETH2 filtering rules: \ + All MAC SRC == (22eeddccbbaa) traffic goes to routing table 0 \ + All MAC ETH TYPE == (0800) traffic goes to routing table 1 \ + All (1) traffic goes to routing table 2"; + m_minIPAHwType = IPA_HW_v2_5; + m_maxIPAHwType = IPA_HW_MAX; + Register(*this); + m_pCurrentProducer = &m_producer2; + } + + virtual bool AddRules() + { + LOG_MSG_DEBUG("Entering"); + + const char bypass0[] = "bypass0"; + const char bypass1[] = "bypass1"; + const char bypass2[] = "bypass2"; + struct ipa_ioc_get_rt_tbl routing_table0,routing_table1,routing_table2; + + if (!CreateThreeIPv4BypassRoutingTables (bypass0,bypass1,bypass2)) + { + printf("CreateThreeIPv4BypassRoutingTables"); + return false; + } + + routing_table0.ip = IPA_IP_v4; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + LOG_MSG_ERROR( + "m_routing.GetRoutingTable(&routing_table0=0x%p)", + &routing_table0); + return false; + } + routing_table1.ip = IPA_IP_v4; + strlcpy(routing_table1.name, bypass1, sizeof(routing_table1.name)); + if (!m_routing.GetRoutingTable(&routing_table1)) + { + LOG_MSG_ERROR("m_routing.GetRoutingTable(&routing_table1=0x%p)", + &routing_table1); + return false; + } + + routing_table2.ip = IPA_IP_v4; + strlcpy(routing_table2.name, bypass2, sizeof(routing_table2.name)); + if (!m_routing.GetRoutingTable(&routing_table2)) + { + LOG_MSG_ERROR( + "m_routing.GetRoutingTable(&routing_table2=0x%p)", + &routing_table2); + return false; + } + + // Create 3 filter rules + IPAFilteringTable FilterTable0; + struct ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v4,IPA_CLIENT_TEST2_PROD,false,3); + + // Configuring Filtering Rule 0 - ETH2 DST + FilterTable0.GeneratePresetRule(1,flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.rule.retain_hdr = 1; // retain header removed in producer pipe + flt_rule_entry.flt_rule_hdl = -1; // return value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action = IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.rt_tbl_hdl = routing_table0.hdl; + + // SRC + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_MAC_SRC_ADDR_ETHER_II; + memcpy(flt_rule_entry.rule.attrib.src_mac_addr_mask, + m_MAC_ADDR_MASK_ALL, + sizeof(flt_rule_entry.rule.attrib.src_mac_addr_mask)); + memcpy(flt_rule_entry.rule.attrib.src_mac_addr, + m_ETH2_SRC_ADDR, + sizeof(flt_rule_entry.rule.attrib.src_mac_addr)); + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + LOG_MSG_ERROR ("Adding RuleTable(0) to Filtering"); + return false; + } + + // Configuring Filtering Rule 1 - ETH2 type + flt_rule_entry.rule.rt_tbl_hdl=routing_table1.hdl; + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_MAC_ETHER_TYPE; + flt_rule_entry.rule.attrib.ether_type = ETH_P_IP; + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + LOG_MSG_ERROR ("Adding RuleTable(1) to Filtering"); + return false; + } + + // Configuring Filtering Rule 2 - Accept all + flt_rule_entry.rule.rt_tbl_hdl = routing_table2.hdl; + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + flt_rule_entry.rule.attrib.u.v4.dst_addr_mask = 0x00000000; // Accept all + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0x00000000; // Has no effect + if (((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable())) + { + LOG_MSG_ERROR ("Adding RuleTable(2) to Filtering"); + return false; + } + + LOG_MSG_DEBUG("flt rule status: s0=0x%x, s1=0x%x s2=0x%x", + FilterTable0.ReadRuleFromTable(0)->status, + FilterTable0.ReadRuleFromTable(1)->status, + FilterTable0.ReadRuleFromTable(2)->status); + + LOG_MSG_DEBUG("Leaving function\n"); + return true; + + }// AddRules() + + virtual bool ModifyPackets() + { + uint16_t ether_type = ETH_P_IP; + uint16_t wrong_ether_type = 0x1234; + + // SRC correct, DST wrong, ETH type wrong + memcpy(&m_sendBuffer1[ETH2_SRC_ADDR_OFFSET], + m_ETH2_SRC_ADDR, ETH_ALEN); + memcpy(&m_sendBuffer1[ETH2_DST_ADDR_OFFSET], + m_ETH2_DST_ADDR, ETH_ALEN); + m_sendBuffer1[ETH2_DST_ADDR_OFFSET] = 0x00; + memcpy(&m_sendBuffer1[ETH2_ETH_TYPE_OFFSET], + &wrong_ether_type, sizeof(wrong_ether_type)); + + // SRC wrong, DST wrong, ETH type correct + memcpy(&m_sendBuffer2[ETH2_SRC_ADDR_OFFSET], + m_ETH2_SRC_ADDR, ETH_ALEN); + m_sendBuffer2[ETH2_SRC_ADDR_OFFSET] = 0x00; + memcpy(&m_sendBuffer2[ETH2_DST_ADDR_OFFSET], + m_ETH2_DST_ADDR, ETH_ALEN); + m_sendBuffer2[ETH2_DST_ADDR_OFFSET] = 0x00; + memcpy(&m_sendBuffer2[ETH2_ETH_TYPE_OFFSET], + ðer_type, sizeof(ether_type)); + + // SRC wrong, DST correct, ETH type wrong + memcpy(&m_sendBuffer3[ETH2_SRC_ADDR_OFFSET], + m_ETH2_SRC_ADDR, ETH_ALEN); + m_sendBuffer3[ETH2_SRC_ADDR_OFFSET] = 0x00; + memcpy(&m_sendBuffer3[ETH2_DST_ADDR_OFFSET], + m_ETH2_DST_ADDR, ETH_ALEN); + memcpy(&m_sendBuffer3[ETH2_ETH_TYPE_OFFSET], + &wrong_ether_type, sizeof(wrong_ether_type)); + + return true; + }// ModifyPacktes () +}; + +static IpaFilterEthIPv4Test00 ipaFilterEthIPv4Test00; +static IpaFilterEthIPv4Test01 ipaFilterEthIPv4Test01; +static IpaFilterEthIPv4Test02 ipaFilterEthIPv4Test02; +static IpaFilterEthIPv4Test03 ipaFilterEthIPv4Test03; diff --git a/qcom/opensource/dataipa/kernel-tests/FilteringTest.cpp b/qcom/opensource/dataipa/kernel-tests/FilteringTest.cpp new file mode 100644 index 0000000000..3e794681c0 --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/FilteringTest.cpp @@ -0,0 +1,10803 @@ +/* + * Copyright (c) 2017-2021 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Changes from Qualcomm Innovation Center are provided under the following license: + * + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * * Neither the name of Qualcomm Innovation Center, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + */ + +#include +#include +#include +#include +#include +#include +#include +#include // for memcpy +#include //for ioctl +#include "hton.h" // for htonl +#include "InterfaceAbstraction.h" +#include "Constants.h" +#include "Logger.h" +#include "TestsUtils.h" +#include "Filtering.h" +#include "RoutingDriverWrapper.h" +#include "IPAFilteringTable.h" + +//TODO Add Enum for IP/TCP/UDP Fields + +#define IP4_TOS_FIELD_OFFSET (1) +#define IPV4_TTL_OFFSET (8) +#define IPV4_PROTOCOL_OFFSET (9) +#define IPV4_CSUM_OFFSET (10) +#define IPV6_NEXT_HDR_OFFSET (6) +#define IPV4_SRC_ADDR_OFFSET (12) +#define IPV4_DST_ADDR_OFFSET (16) +#define IPV4_SRC_PORT_OFFSET (20) +#define IPV4_DST_PORT_OFFSET (20+2) +#define IPV6_SRC_PORT_OFFSET (40) +#define IPV6_DST_PORT_OFFSET (40+2) + +#define DST_ADDR_LSB_OFFSET_IPV4 (19) +#define DST_ADDR_LSB_OFFSET_IPV6 (39) + +#define HOP_LIMIT_OFFSET_IPV6 (7) + +#define IPV4_FRAGMENT_FLAGS_OFFSET (6) +#define IPV6_FRAGMENT_FLAGS_OFFSET (42) +#define IPV6_FRAGMENT_NEXT_HDR_OFFSET (40) + +#define IPv4_TCP_FLAGS_OFFSET (20+13) +#define TCP_ACK_FLAG_MASK (0x10) + +#define TAG_802_1Q_OFFSET (12) + +extern Logger g_Logger; + +class IpaFilteringBlockTestFixture : public TestBase +{ +public: + + IpaFilteringBlockTestFixture(): + m_sendSize (BUFF_MAX_SIZE), + m_sendSize2 (BUFF_MAX_SIZE), + m_sendSize3 (BUFF_MAX_SIZE), + m_IpaIPType(IPA_IP_v4), + m_extHdrType(NONE) + { + memset(m_sendBuffer, 0, sizeof(m_sendBuffer)); // First input file / IP packet + memset(m_sendBuffer2, 0, sizeof(m_sendBuffer2)); // Second input file / IP packet + memset(m_sendBuffer3, 0, sizeof(m_sendBuffer3)); // Third input file (default) / IP packet + m_testSuiteName.push_back("Filtering"); + } + + static int SetupKernelModule(bool en_status = 0) + { + int retval; + struct ipa_channel_config from_ipa_channels[3]; + struct test_ipa_ep_cfg from_ipa_cfg[3]; + struct ipa_channel_config to_ipa_channels[2]; + struct test_ipa_ep_cfg to_ipa_cfg[2]; + + struct ipa_test_config_header header = {0}; + struct ipa_channel_config *to_ipa_array[2]; + struct ipa_channel_config *from_ipa_array[3]; + + /* From ipa configurations - 3 pipes */ + memset(&from_ipa_cfg[0], 0, sizeof(from_ipa_cfg[0])); + prepare_channel_struct(&from_ipa_channels[0], + header.from_ipa_channels_num++, + IPA_CLIENT_TEST2_CONS, + (void *)&from_ipa_cfg[0], + sizeof(from_ipa_cfg[0]), + en_status); + from_ipa_array[0] = &from_ipa_channels[0]; + + memset(&from_ipa_cfg[1], 0, sizeof(from_ipa_cfg[1])); + prepare_channel_struct(&from_ipa_channels[1], + header.from_ipa_channels_num++, + IPA_CLIENT_TEST3_CONS, + (void *)&from_ipa_cfg[1], + sizeof(from_ipa_cfg[1]), + en_status); + from_ipa_array[1] = &from_ipa_channels[1]; + + memset(&from_ipa_cfg[2], 0, sizeof(from_ipa_cfg[2])); + prepare_channel_struct(&from_ipa_channels[2], + header.from_ipa_channels_num++, + IPA_CLIENT_TEST4_CONS, + (void *)&from_ipa_cfg[2], + sizeof(from_ipa_cfg[2]), + en_status); + from_ipa_array[2] = &from_ipa_channels[2]; + + /* To ipa configurations - 1 pipes */ + memset(&to_ipa_cfg[0], 0, sizeof(to_ipa_cfg[0])); + prepare_channel_struct(&to_ipa_channels[0], + header.to_ipa_channels_num++, + IPA_CLIENT_TEST_PROD, + (void *)&to_ipa_cfg[0], + sizeof(to_ipa_cfg[0])); + to_ipa_array[0] = &to_ipa_channels[0]; + + /* header removal for Ethernet header + 8021Q header */ + memset(&to_ipa_cfg[1], 0, sizeof(to_ipa_cfg[1])); + to_ipa_cfg[1].hdr.hdr_len = ETH8021Q_HEADER_LEN; + to_ipa_cfg[1].hdr.hdr_ofst_metadata_valid = 1; + to_ipa_cfg[1].hdr.hdr_ofst_metadata = + ETH8021Q_METADATA_OFFSET; + prepare_channel_struct(&to_ipa_channels[1], + header.to_ipa_channels_num++, + IPA_CLIENT_TEST2_PROD, + (void *)&to_ipa_cfg[1], + sizeof(to_ipa_cfg[1])); + to_ipa_array[1] = &to_ipa_channels[1]; + + prepare_header_struct(&header, from_ipa_array, to_ipa_array); + + retval = GenericConfigureScenario(&header); + + return retval; + } + + bool Setup() + { + bool bRetVal = true; + + if (SetupKernelModule() != true) + return bRetVal; + + m_producer.Open(INTERFACE0_TO_IPA_DATA_PATH, INTERFACE0_FROM_IPA_DATA_PATH); + m_producer2.Open(INTERFACE4_TO_IPA_DATA_PATH, INTERFACE4_FROM_IPA_DATA_PATH); + + m_consumer.Open(INTERFACE1_TO_IPA_DATA_PATH, INTERFACE1_FROM_IPA_DATA_PATH); + m_consumer2.Open(INTERFACE2_TO_IPA_DATA_PATH, INTERFACE2_FROM_IPA_DATA_PATH); + m_defaultConsumer.Open(INTERFACE3_TO_IPA_DATA_PATH, INTERFACE3_FROM_IPA_DATA_PATH); + m_Exceptions.Open(INTERFACE_TO_IPA_EXCEPTION_PATH, INTERFACE_FROM_IPA_EXCEPTION_PATH); + + if (!m_routing.DeviceNodeIsOpened()) + { + printf("Routing block is not ready for immediate commands!\n"); + return false; + } + + if (!m_filtering.DeviceNodeIsOpened()) + { + printf("Filtering block is not ready for immediate commands!\n"); + return false; + } + m_routing.Reset(IPA_IP_v4); // This will issue a Reset command to the Filtering as well + m_routing.Reset(IPA_IP_v6); // This will issue a Reset command to the Filtering as well + return true; + } // Setup() + + bool Setup(bool en_status = false) + { + bool bRetVal = true; + + if (SetupKernelModule(en_status) != true) + return bRetVal; + + m_producer.Open(INTERFACE0_TO_IPA_DATA_PATH, INTERFACE0_FROM_IPA_DATA_PATH); + + m_consumer.Open(INTERFACE1_TO_IPA_DATA_PATH, INTERFACE1_FROM_IPA_DATA_PATH); + m_consumer2.Open(INTERFACE2_TO_IPA_DATA_PATH, INTERFACE2_FROM_IPA_DATA_PATH); + m_defaultConsumer.Open(INTERFACE3_TO_IPA_DATA_PATH, INTERFACE3_FROM_IPA_DATA_PATH); + m_Exceptions.Open(INTERFACE_TO_IPA_EXCEPTION_PATH, INTERFACE_FROM_IPA_EXCEPTION_PATH); + + if (!m_routing.DeviceNodeIsOpened()) + { + printf("Routing block is not ready for immediate commands!\n"); + return false; + } + + if (!m_filtering.DeviceNodeIsOpened()) + { + printf("Filtering block is not ready for immediate commands!\n"); + return false; + } + m_routing.Reset(IPA_IP_v4); // This will issue a Reset command to the Filtering as well + m_routing.Reset(IPA_IP_v6); // This will issue a Reset command to the Filtering as well + return true; + } // Setup() + + bool Teardown() + { + m_producer.Close(); + m_producer2.Close(); + m_consumer.Close(); + m_consumer2.Close(); + m_defaultConsumer.Close(); + m_Exceptions.Close(); + return true; + } // Teardown() + + virtual bool LoadFiles(enum ipa_ip_type ip) + { + string fileName; + + if (IPA_IP_v4 == ip) { + fileName = "Input/IPv4_1"; + } else { + fileName = "Input/IPv6"; + } + + if (!LoadDefaultPacket(ip, m_extHdrType, m_sendBuffer, m_sendSize)) { + LOG_MSG_ERROR("Failed default Packet\n"); + return false; + } + printf ("Loaded %zu Bytes to Buffer 1\n",m_sendSize); + + if (!LoadDefaultPacket(ip, m_extHdrType, m_sendBuffer2, m_sendSize2)) { + LOG_MSG_ERROR("Failed default Packet\n"); + return false; + } + printf ("Loaded %zu Bytes to Buffer 2\n",m_sendSize2); + + if (!LoadDefaultPacket(ip, m_extHdrType, m_sendBuffer3, m_sendSize3)) { + LOG_MSG_ERROR("Failed default Packet\n"); + return false; + } + printf ("Loaded %zu Bytes to Buffer 3\n",m_sendSize3); + + return true; + } + + inline bool VerifyStatusReceived(size_t SendSize, size_t RecvSize) + { + size_t stts_size = sizeof(struct ipa3_hw_pkt_status); + + if (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_0) { + stts_size = sizeof(struct ipa3_hw_pkt_status_hw_v5_0); + } + + if ((RecvSize <= SendSize) || + ((RecvSize - SendSize) != stts_size)){ + printf("received buffer size does not match! sent:receive [%zu]:[%zu]\n",SendSize,RecvSize); + return false; + } + + return true; + } + + inline bool VerifyStatusReceived_wo_status(size_t SendSize, size_t RecvSize) + { + size_t stts_size = sizeof(struct ipa3_hw_pkt_status); + + if (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_0) { + stts_size = sizeof(struct ipa3_hw_pkt_status_hw_v5_0); + } + + if ((RecvSize != SendSize)){ + printf("received buffer size does not match! sent:receive [%zu]:[%zu]\n",SendSize,RecvSize); + return false; + } + + return true; + } + + inline bool IsCacheHit(size_t SendSize, size_t RecvSize, void *Buff) + { + struct ipa3_hw_pkt_status *pStatus = (struct ipa3_hw_pkt_status *)Buff; + + if (VerifyStatusReceived(SendSize,RecvSize) == false){ + return false; + } + + if((bool)pStatus->filt_hash){ + printf ("%s::cache hit!! \n",__FUNCTION__); + return true; + } + + printf ("%s::cache miss!! \n",__FUNCTION__); + return false; + } + + inline bool IsCacheHit_v5_0(size_t SendSize, size_t RecvSize, void *Buff) + { + struct ipa3_hw_pkt_status_hw_v5_0 *pStatus = (struct ipa3_hw_pkt_status_hw_v5_0 *)Buff; + + if (VerifyStatusReceived(SendSize,RecvSize) == false){ + return false; + } + + if((bool)pStatus->filt_hash){ + printf ("%s::cache hit!! \n",__FUNCTION__); + return true; + } + + printf ("%s::cache miss!! \n",__FUNCTION__); + return false; + } + + inline bool IsTTLUpdated_v5_5(size_t SendSize, size_t RecvSize, void *Buff) + { + struct ipa3_hw_pkt_status_hw_v5_5 *pStatus = (struct ipa3_hw_pkt_status_hw_v5_5 *)Buff; + + if (VerifyStatusReceived(SendSize,RecvSize) == false){ + return false; + } + + if((bool)pStatus->ttl_dec){ + printf ("%s::TTL Updated!! \n",__FUNCTION__); + return true; + } + + printf ("%s::TTL not updated!! \n",__FUNCTION__); + return false; + } + + inline bool IsTTLUpdated_v5_5_wo_status(size_t SendSize, size_t RecvSize, void *Buff) + { + struct ipa3_hw_pkt_status_hw_v5_5 *pStatus = (struct ipa3_hw_pkt_status_hw_v5_5 *)Buff; + + if (VerifyStatusReceived_wo_status(SendSize,RecvSize) == false){ + return false; + } + + if((bool)pStatus->ttl_dec){ + printf ("%s::TTL Updated!! \n",__FUNCTION__); + return true; + } + + printf ("%s::TTL not updated!! \n",__FUNCTION__); + return false; + } + + inline bool IsCacheMiss(size_t SendSize, size_t RecvSize, void *Buff) + { + struct ipa3_hw_pkt_status *pStatus = (struct ipa3_hw_pkt_status *)Buff; + + if (VerifyStatusReceived(SendSize,RecvSize) == false){ + return false; + } + + if(!((bool)pStatus->filt_hash)){ + printf ("%s::cache miss!! \n",__FUNCTION__); + return true; + } + + printf ("%s::cache hit!! \n",__FUNCTION__); + return false; + } + + inline bool IsCacheMiss_v5_0(size_t SendSize, size_t RecvSize, void *Buff) + { + struct ipa3_hw_pkt_status_hw_v5_0 *pStatus = (struct ipa3_hw_pkt_status_hw_v5_0 *)Buff; + + if (VerifyStatusReceived(SendSize,RecvSize) == false){ + return false; + } + + if(!((bool)pStatus->filt_hash)){ + printf ("%s::cache miss!! \n",__FUNCTION__); + return true; + } + + printf ("%s::cache hit!! \n",__FUNCTION__); + return false; + } + + + bool ReceivePacketAndCompareFrom(InterfaceAbstraction& cons, Byte* send, + size_t send_sz, bool shouldBeHit) + { + size_t receivedSize = 0; + bool isSuccess = true; + + // Receive results + Byte *rxBuff1 = new Byte[0x400]; + + if (NULL == rxBuff1) + { + printf("Memory allocation error.\n"); + return false; + } + + receivedSize = cons.ReceiveData(rxBuff1, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize, cons.m_fromChannelName.c_str()); + + // Compare results + isSuccess &= CompareResultVsGolden_w_Status(send, send_sz, rxBuff1, receivedSize); + + if (shouldBeHit) { + isSuccess &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_0) ? + IsCacheHit_v5_0(send_sz, receivedSize, rxBuff1) : IsCacheHit(send_sz, receivedSize, rxBuff1); + } + else + { + isSuccess &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_0) ? + IsCacheMiss_v5_0(send_sz, receivedSize, rxBuff1) : IsCacheMiss(send_sz, receivedSize, rxBuff1); + } + + size_t recievedBufferSize = receivedSize * 3; + size_t sentBufferSize = m_sendSize * 3; + char *recievedBuffer = new char[recievedBufferSize]; + char *sentBuffer = new char[sentBufferSize]; + size_t j; + + memset(recievedBuffer, 0, recievedBufferSize); + memset(sentBuffer, 0, sentBufferSize); + + for(j = 0; j < m_sendSize; j++) + snprintf(&sentBuffer[3 * j], sentBufferSize - (3 * j + 1), " %02X", send[j]); + for(j = 0; j < receivedSize; j++) + snprintf(&recievedBuffer[3 * j], recievedBufferSize - (3 * j + 1), " %02X", rxBuff1[j]); + printf("Expected Value (%zu)\n%s\n, Received Value1(%zu)\n%s\n",send_sz,sentBuffer,receivedSize,recievedBuffer); + + delete[] rxBuff1; + delete[] recievedBuffer; + delete[] sentBuffer; + + //receivedSize = excp_cons.ReceiveData(rxBuff1, 0x400); + //printf("Received %zu bytes on %s.\n", receivedSize, excp_cons.m_fromChannelName.c_str()); + + return isSuccess; + } + + virtual bool ReceivePacketsAndCompare() + { + size_t receivedSize = 0; + size_t receivedSize2 = 0; + size_t receivedSize3 = 0; + bool pkt1_cmp_succ, pkt2_cmp_succ, pkt3_cmp_succ; + + // Receive results + Byte *rxBuff1 = new Byte[0x400]; + Byte *rxBuff2 = new Byte[0x400]; + Byte *rxBuff3 = new Byte[0x400]; + + if (NULL == rxBuff1 || NULL == rxBuff2 || NULL == rxBuff3) + { + printf("Memory allocation error.\n"); + return false; + } + + memset(rxBuff1, 0, 0x400); + memset(rxBuff2, 0, 0x400); + memset(rxBuff3, 0, 0x400); + + receivedSize = m_consumer.ReceiveData(rxBuff1, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize, m_consumer.m_fromChannelName.c_str()); + + receivedSize2 = m_consumer2.ReceiveData(rxBuff2, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize2, m_consumer2.m_fromChannelName.c_str()); + + receivedSize3 = m_defaultConsumer.ReceiveData(rxBuff3, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize3, m_defaultConsumer.m_fromChannelName.c_str()); + + // Compare results + pkt1_cmp_succ = CompareResultVsGolden(m_sendBuffer, m_sendSize, rxBuff1, receivedSize); + pkt2_cmp_succ = CompareResultVsGolden(m_sendBuffer2, m_sendSize2, rxBuff2, receivedSize2); + pkt3_cmp_succ = CompareResultVsGolden(m_sendBuffer3, m_sendSize3, rxBuff3, receivedSize3); + + size_t recievedBufferSize = + MAX3(receivedSize, receivedSize2, receivedSize3) * 3; + size_t sentBufferSize = + MAX3(m_sendSize, m_sendSize2, m_sendSize3) * 3; + char *recievedBuffer = new char[recievedBufferSize]; + char *sentBuffer = new char[sentBufferSize]; + size_t j; + + if (NULL == recievedBuffer || NULL == sentBuffer) { + printf("Memory allocation error\n"); + return false; + } + + memset(recievedBuffer, 0, recievedBufferSize); + memset(sentBuffer, 0, sentBufferSize); + for(j = 0; j < m_sendSize; j++) + snprintf(&sentBuffer[3 * j], sentBufferSize - (3 * j + 1), " %02X", m_sendBuffer[j]); + for(j = 0; j < receivedSize; j++) + snprintf(&recievedBuffer[3 * j], recievedBufferSize - (3 * j + 1), " %02X", rxBuff1[j]); + printf("Expected Value1 (%zu)\n%s\n, Received Value1(%zu)\n%s\n-->Value1 %s\n", + m_sendSize,sentBuffer,receivedSize,recievedBuffer, + pkt1_cmp_succ?"Match":"no Match"); + + memset(recievedBuffer, 0, recievedBufferSize); + memset(sentBuffer, 0, sentBufferSize); + for(j = 0; j < m_sendSize2; j++) + snprintf(&sentBuffer[3 * j], sentBufferSize - (3 * j + 1), " %02X", m_sendBuffer2[j]); + for(j = 0; j < receivedSize2; j++) + snprintf(&recievedBuffer[3 * j], recievedBufferSize - (3 * j + 1), " %02X", rxBuff2[j]); + printf("Expected Value2 (%zu)\n%s\n, Received Value2(%zu)\n%s\n-->Value2 %s\n", + m_sendSize2,sentBuffer,receivedSize2,recievedBuffer, + pkt2_cmp_succ?"Match":"no Match"); + + memset(recievedBuffer, 0, recievedBufferSize); + memset(sentBuffer, 0, sentBufferSize); + for(j = 0; j < m_sendSize3; j++) + snprintf(&sentBuffer[3 * j], sentBufferSize - (3 * j + 1), " %02X", m_sendBuffer3[j]); + for(j = 0; j < receivedSize3; j++) + snprintf(&recievedBuffer[3 * j], recievedBufferSize - (3 * j + 1), " %02X", rxBuff3[j]); + printf("Expected Value3 (%zu)\n%s\n, Received Value3(%zu)\n%s\n-->Value3 %s\n", + m_sendSize3,sentBuffer,receivedSize3,recievedBuffer, + pkt3_cmp_succ?"Match":"no Match"); + + delete[] recievedBuffer; + delete[] sentBuffer; + + delete[] rxBuff1; + delete[] rxBuff2; + delete[] rxBuff3; + + return pkt1_cmp_succ && pkt2_cmp_succ && pkt3_cmp_succ; + } + + // This function creates three IPv4 bypass routing entries and commits them. + bool CreateThreeIPv4BypassRoutingTables (const char * bypass0, const char * bypass1, const char * bypass2) + { + printf("Entering %s, %s()\n",__FUNCTION__, __FILE__); + struct ipa_ioc_add_rt_rule *rt_rule0 = 0, *rt_rule1 = 0,*rt_rule2 = 0; + struct ipa_rt_rule_add *rt_rule_entry; + + rt_rule0 = (struct ipa_ioc_add_rt_rule *) + calloc(1, + sizeof(struct ipa_ioc_add_rt_rule) + + 1*sizeof(struct ipa_rt_rule_add) + ); + if(!rt_rule0) { + printf("calloc failed to allocate rt_rule0 in %s\n",__FUNCTION__); + return false; + } + rt_rule1 = (struct ipa_ioc_add_rt_rule *) + calloc(1, + sizeof(struct ipa_ioc_add_rt_rule) + + 1*sizeof(struct ipa_rt_rule_add) + ); + if(!rt_rule1) { + printf("calloc failed to allocate rt_rule1 in %s\n",__FUNCTION__); + Free(rt_rule0); + return false; + } + rt_rule2 = (struct ipa_ioc_add_rt_rule *) + calloc(1, + sizeof(struct ipa_ioc_add_rt_rule) + + 1*sizeof(struct ipa_rt_rule_add) + ); + if(!rt_rule2) { + printf("calloc failed to allocate rt_rule2 in %s\n",__FUNCTION__); + Free(rt_rule0); + Free(rt_rule1); + return false; + } + + rt_rule0->num_rules = 1; + rt_rule0->ip = IPA_IP_v4; + rt_rule0->commit = true; + strlcpy(rt_rule0->rt_tbl_name, bypass0, sizeof(rt_rule0->rt_tbl_name)); + + rt_rule_entry = &rt_rule0->rules[0]; + rt_rule_entry->at_rear = 0; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST2_CONS;//Setting + // rt_rule_entry->rule.hdr_hdl = hdr_entry->hdr_hdl; // TODO Header Inserion - gidons, there is no support for header insertion / removal yet. + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v4.dst_addr = 0xaabbccdd; + rt_rule_entry->rule.attrib.u.v4.dst_addr_mask = 0x00000000;// All Packets will get a "Hit" + if (false == m_routing.AddRoutingRule(rt_rule0)) + { + printf("Routing rule addition(rt_rule0) failed!\n"); + Free (rt_rule2); + Free (rt_rule1); + Free (rt_rule0); + return false; + } + + + rt_rule1->num_rules = 1; + rt_rule1->ip = IPA_IP_v4; + rt_rule1->commit = true; + strlcpy(rt_rule1->rt_tbl_name, bypass1, sizeof(rt_rule1->rt_tbl_name)); + rt_rule_entry = &rt_rule1->rules[0]; + rt_rule_entry->at_rear = 0; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST3_CONS; +// rt_rule_entry->rule.hdr_hdl = hdr_entry->hdr_hdl; // TODO Header Inserion - gidons, there is no support for header insertion / removal yet. + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v4.dst_addr = 0xaabbccdd; + rt_rule_entry->rule.attrib.u.v4.dst_addr_mask = 0x00000000;// All Packets will get a "Hit" + if (false == m_routing.AddRoutingRule(rt_rule1)) + { + printf("Routing rule addition(rt_rule1) failed!\n"); + Free (rt_rule2); + Free (rt_rule1); + Free (rt_rule0); + return false; + } + + + rt_rule2->num_rules = 1; + rt_rule2->ip = IPA_IP_v4; + rt_rule2->commit = true; + strlcpy(rt_rule2->rt_tbl_name, bypass2, sizeof(rt_rule2->rt_tbl_name)); + rt_rule_entry = &rt_rule2->rules[0]; + rt_rule_entry->at_rear = 0; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST4_CONS; + // rt_rule_entry->rule.hdr_hdl = hdr_entry->hdr_hdl; // TODO Header Inserion - gidons, there is no support for header insertion / removal yet. + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v4.dst_addr = 0xaabbccdd; + rt_rule_entry->rule.attrib.u.v4.dst_addr_mask = 0x00000000;// All Packets will get a "Hit" + if (false == m_routing.AddRoutingRule(rt_rule2)) + { + printf("Routing rule addition(rt_rule2) failed!\n"); + Free (rt_rule2); + Free (rt_rule1); + Free (rt_rule0); + return false; + } + + + Free (rt_rule2); + Free (rt_rule1); + Free (rt_rule0); + printf("Leaving %s, %s()\n",__FUNCTION__, __FILE__); + return true; + } + + // This function creates three IPv6 bypass routing entries and commits them. + bool CreateThreeIPv6BypassRoutingTables (const char * bypass0, const char * bypass1, const char * bypass2) + { + printf("Entering %s, %s()\n",__FUNCTION__, __FILE__); + struct ipa_ioc_add_rt_rule *rt_rule0 = 0, *rt_rule1 = 0,*rt_rule2 = 0; + struct ipa_rt_rule_add *rt_rule_entry; + + rt_rule0 = (struct ipa_ioc_add_rt_rule *) + calloc(1, + sizeof(struct ipa_ioc_add_rt_rule) + + 1*sizeof(struct ipa_rt_rule_add) + ); + if(!rt_rule0) { + printf("calloc failed to allocate rt_rule0 in %s\n",__FUNCTION__); + return false; + } + rt_rule1 = (struct ipa_ioc_add_rt_rule *) + calloc(1, + sizeof(struct ipa_ioc_add_rt_rule) + + 1*sizeof(struct ipa_rt_rule_add) + ); + if(!rt_rule1) { + printf("calloc failed to allocate rt_rule1 in %s\n",__FUNCTION__); + Free(rt_rule0); + return false; + } + rt_rule2 = (struct ipa_ioc_add_rt_rule *) + calloc(1, + sizeof(struct ipa_ioc_add_rt_rule) + + 1*sizeof(struct ipa_rt_rule_add) + ); + if(!rt_rule2) { + printf("calloc failed to allocate rt_rule2 in %s\n",__FUNCTION__); + Free(rt_rule0); + Free(rt_rule1); + return false; + } + + rt_rule0->num_rules = 1; + rt_rule0->ip = IPA_IP_v6; + rt_rule0->commit = true; + strlcpy(rt_rule0->rt_tbl_name, bypass0, sizeof(rt_rule0->rt_tbl_name)); + + rt_rule_entry = &rt_rule0->rules[0]; + rt_rule_entry->at_rear = 0; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST2_CONS;//Setting + // rt_rule_entry->rule.hdr_hdl = hdr_entry->hdr_hdl; // TODO Header Inserion - gidons, there is no support for header insertion / removal yet. + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v6.dst_addr[0] = 0xaabbccdd; + rt_rule_entry->rule.attrib.u.v6.dst_addr[1] = 0xeeff0011; + rt_rule_entry->rule.attrib.u.v6.dst_addr[2] = 0x22334455; + rt_rule_entry->rule.attrib.u.v6.dst_addr[3] = 0x66778899; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[0] = 0x00000000;// All Packets will get a "Hit" + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[1] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[2] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[3] = 0x00000000; + if (false == m_routing.AddRoutingRule(rt_rule0)) + { + printf("Routing rule addition(rt_rule0) failed!\n"); + Free (rt_rule2); + Free (rt_rule1); + Free (rt_rule0); + return false; + } + + + rt_rule1->num_rules = 1; + rt_rule1->ip = IPA_IP_v6; + rt_rule1->commit = true; + strlcpy(rt_rule1->rt_tbl_name, bypass1, sizeof(rt_rule1->rt_tbl_name)); + rt_rule_entry = &rt_rule1->rules[0]; + rt_rule_entry->at_rear = 0; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST3_CONS; +// rt_rule_entry->rule.hdr_hdl = hdr_entry->hdr_hdl; // TODO Header Inserion - gidons, there is no support for header insertion / removal yet. + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v6.dst_addr[0] = 0xaabbccdd; + rt_rule_entry->rule.attrib.u.v6.dst_addr[1] = 0xeeff0011; + rt_rule_entry->rule.attrib.u.v6.dst_addr[2] = 0x22334455; + rt_rule_entry->rule.attrib.u.v6.dst_addr[3] = 0x66778899; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[0] = 0x00000000;// All Packets will get a "Hit" + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[1] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[2] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[3] = 0x00000000; + if (false == m_routing.AddRoutingRule(rt_rule1)) + { + printf("Routing rule addition(rt_rule1) failed!\n"); + Free (rt_rule2); + Free (rt_rule1); + Free (rt_rule0); + return false; + } + + + rt_rule2->num_rules = 1; + rt_rule2->ip = IPA_IP_v6; + rt_rule2->commit = true; + strlcpy(rt_rule2->rt_tbl_name, bypass2, sizeof(rt_rule2->rt_tbl_name)); + rt_rule_entry = &rt_rule2->rules[0]; + rt_rule_entry->at_rear = 0; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST4_CONS; + // rt_rule_entry->rule.hdr_hdl = hdr_entry->hdr_hdl; // TODO Header Inserion - gidons, there is no support for header insertion / removal yet. + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v6.dst_addr[0] = 0xaabbccdd; + rt_rule_entry->rule.attrib.u.v6.dst_addr[1] = 0xeeff0011; + rt_rule_entry->rule.attrib.u.v6.dst_addr[2] = 0x22334455; + rt_rule_entry->rule.attrib.u.v6.dst_addr[3] = 0x66778899; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[0] = 0x00000000;// All Packets will get a "Hit" + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[1] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[2] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[3] = 0x00000000; + if (false == m_routing.AddRoutingRule(rt_rule2)) + { + printf("Routing rule addition(rt_rule2) failed!\n"); + Free (rt_rule2); + Free (rt_rule1); + Free (rt_rule0); + return false; + } + + + Free (rt_rule2); + Free (rt_rule1); + Free (rt_rule0); + printf("Leaving %s, %s()\n",__FUNCTION__, __FILE__); + return true; + } + + virtual bool GetThreeIPv6BypassRoutingTables(uint32_t *Hndl0, uint32_t *Hndl1, uint32_t *Hndl2) + { + printf("Entering %s, %s()\n",__FUNCTION__, __FILE__); + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + struct ipa_ioc_get_rt_tbl routing_table0,routing_table1,routing_table2; + + if (!CreateThreeIPv6BypassRoutingTables (bypass0,bypass1,bypass2)) + { + printf("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + + printf("CreateThreeBypassRoutingTables completed successfully\n"); + routing_table0.ip = IPA_IP_v6; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + printf("m_routing.GetRoutingTable(&routing_table0=0x%p) Failed.\n",&routing_table0); + return false; + } + routing_table1.ip = IPA_IP_v6; + strlcpy(routing_table1.name, bypass1, sizeof(routing_table1.name)); + if (!m_routing.GetRoutingTable(&routing_table1)) + { + printf("m_routing.GetRoutingTable(&routing_table1=0x%p) Failed.\n",&routing_table1); + return false; + } + + routing_table2.ip = IPA_IP_v6; + strlcpy(routing_table2.name, bypass2, sizeof(routing_table2.name)); + if (!m_routing.GetRoutingTable(&routing_table2)) + { + printf("m_routing.GetRoutingTable(&routing_table2=0x%p) Failed.\n",&routing_table2); + return false; + } + + *Hndl0 = routing_table0.hdl; + *Hndl1 = routing_table1.hdl; + *Hndl2 = routing_table2.hdl; + + return true; + + } + + void print_packets(size_t receivedSize, size_t m_sendSize, size_t recievedBufferSize, size_t sentBufferSize, Byte *rxBuff, Byte *m_sendBuffer, char *recievedBuffer, char *sentBuffer) + { + size_t j; + + for(j = 0; j < m_sendSize; j++) { + snprintf(&sentBuffer[3 * j], sentBufferSize - 3 * j, + " %02X", m_sendBuffer[j]); + } + for(j = 0; j < receivedSize; j++) { + snprintf(&recievedBuffer[3 * j], recievedBufferSize- 3 * j, + " %02X", rxBuff[j]); + } + printf("Expected Value (%zu)\n%s\n, Received Value(%zu)\n%s\n",m_sendSize,sentBuffer,receivedSize,recievedBuffer); + } + + virtual bool ModifyPackets() = 0; + virtual bool AddRules() = 0; + + bool Run() + { + bool res = false; + bool isSuccess = false; + + printf("Entering %s, %s()\n",__FUNCTION__, __FILE__); + + // Add the relevant filtering rules + res = AddRules(); + if (false == res) { + printf("Failed adding filtering rules.\n"); + return false; + } + + // Load input data (IP packet) from file + res = LoadFiles(m_IpaIPType); + if (false == res) { + printf("Failed loading files.\n"); + return false; + } + + res = ModifyPackets(); + if (false == res) { + printf("Failed to modify packets.\n"); + return false; + } + + // Send first packet + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send second packet + isSuccess = m_producer.SendData(m_sendBuffer2, m_sendSize2); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send third packet + isSuccess = m_producer.SendData(m_sendBuffer3, m_sendSize3); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Receive packets from the channels and compare results + isSuccess = ReceivePacketsAndCompare(); + + printf("Leaving %s, %s(), Returning %d\n",__FUNCTION__, __FILE__,isSuccess); + + return isSuccess; + } // Run() + + + ~IpaFilteringBlockTestFixture() + { + m_sendSize = 0; + m_sendSize2 = 0; + m_sendSize3 = 0; + } + + static Filtering m_filtering; + static RoutingDriverWrapper m_routing; + InterfaceAbstraction m_producer; + InterfaceAbstraction m_producer2; + InterfaceAbstraction m_consumer; + InterfaceAbstraction m_consumer2; + InterfaceAbstraction m_defaultConsumer; + InterfaceAbstraction m_Exceptions; + + static const size_t BUFF_MAX_SIZE = 1024; + static const uint32_t MAX_RULES_NUM = 250; + static const uint32_t MIN_RULES_NUM = 0; + + Byte m_sendBuffer[BUFF_MAX_SIZE]; // First input file / IP packet + Byte m_sendBuffer2[BUFF_MAX_SIZE]; // Second input file / IP packet + Byte m_sendBuffer3[BUFF_MAX_SIZE]; // Third input file (default) / IP packet + size_t m_sendSize; + size_t m_sendSize2; + size_t m_sendSize3; + enum ipa_ip_type m_IpaIPType; + enum ipv6_ext_hdr_type m_extHdrType; + +private: +}; + +RoutingDriverWrapper IpaFilteringBlockTestFixture::m_routing; +Filtering IpaFilteringBlockTestFixture::m_filtering; + + +/*---------------------------------------------------------------------------*/ +/* Test001: Destination IP address and subnet mask match against LAN subnet */ +/*---------------------------------------------------------------------------*/ +class IpaFilteringBlockTest001 : public IpaFilteringBlockTestFixture +{ +public: + IpaFilteringBlockTest001() + { + m_name = "IpaFilteringBlockTest001"; + m_description = + "Filtering block test 001 - Destination IP address and subnet mask match against LAN subnet (Global Filtering Table, Insert all rules in a single commit)\ + 1. Generate and commit three routing tables. \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit Three filtering rules: (DST & Mask Match). \ + All DST_IP == (127.0.0.1 & 255.0.0.255)traffic goes to routing table 0 \ + All DST_IP == (192.169.1.1 & 255.0.0.255)traffic goes to routing table 1 \ + All DST_IP == (192.169.1.2 & 255.0.0.255)traffic goes to routing table 2"; + m_maxIPAHwType = IPA_HW_v2_6L; + Register(*this); + } + + + virtual bool AddRules() + { + printf("Entering %s, %s()\n",__FUNCTION__, __FILE__); + + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + struct ipa_ioc_get_rt_tbl routing_table0,routing_table1,routing_table2; + + if (!CreateThreeIPv4BypassRoutingTables (bypass0,bypass1,bypass2)) + { + printf("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + + routing_table0.ip = IPA_IP_v4; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + printf("m_routing.GetRoutingTable(&routing_table0=0x%p) Failed.\n",&routing_table0); + return false; + } + routing_table1.ip = IPA_IP_v4; + strlcpy(routing_table1.name, bypass1, sizeof(routing_table1.name)); + if (!m_routing.GetRoutingTable(&routing_table1)) + { + printf("m_routing.GetRoutingTable(&routing_table1=0x%p) Failed.\n",&routing_table1); + return false; + } + + routing_table2.ip = IPA_IP_v4; + strlcpy(routing_table2.name, bypass2, sizeof(routing_table2.name)); + if (!m_routing.GetRoutingTable(&routing_table2)) + { + printf("m_routing.GetRoutingTable(&routing_table2=0x%p) Failed.\n",&routing_table2); + return false; + } + + IPAFilteringTable FilterTable0; + struct ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v4,IPA_CLIENT_TEST_PROD,true,3); + printf("FilterTable*.Init Completed Successfully..\n"); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1,flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl=-1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action=IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.rt_tbl_hdl=routing_table0.hdl; //put here the handle corresponding to Routing Rule 1 + // TODO: Fix this, doesn't match the Rule's Requirements + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; // TODO: Fix this, doesn't match the Rule's Requirements + flt_rule_entry.rule.attrib.u.v4.dst_addr_mask = 0xFF0000FF; // Mask + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0x7F000001; // Filter DST_IP == 127.0.0.1. + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + printf ("%s::Error Adding RuleTable(0) to Filtering, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(0)->status); + } + + // Configuring Filtering Rule No.1 // TODO: Fix this, doesn't match the Rule's Requirements + flt_rule_entry.rule.rt_tbl_hdl=routing_table1.hdl; //put here the handle corresponding to Routing Rule 2 + // TODO: Fix this, doesn't match the Rule's Requirements + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0xC0A80101; // Filter DST_IP == 192.168.1.1. + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + printf ("%s::Error Adding RuleTable(1) to Filtering, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(1)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(1)->status); + } + + // Configuring Filtering Rule No.2 // TODO: Fix this, doesn't match the Rule's Requirements + flt_rule_entry.rule.rt_tbl_hdl=routing_table2.hdl; //put here the handle corresponding to Routing Rule 2 + // TODO: Fix this, doesn't match the Rule's Requirements + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0xC0A80102; // Filter DST_IP == 192.168.1.2. + + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + printf ("%s::Error Adding RuleTable(2) to Filtering, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(2)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(2)->status); + } + printf("Leaving %s, %s()\n",__FUNCTION__, __FILE__); + return true; + + }// AddRules() + + virtual bool ModifyPackets() + { + int address; + // TODO: Add verification that we access only allocated addresses + // TODO: Fix this, doesn't match the Rule's Requirements + address = ntohl(0x7F000001);//127.0.0.1 + memcpy(&m_sendBuffer[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + address = ntohl(0xC0A80101);//192.168.1.1 + memcpy(&m_sendBuffer2[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + address = ntohl(0xC0A80102);//192.168.1.2 + memcpy(&m_sendBuffer3[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + + return true; + }// ModifyPacktes () +}; + +/*---------------------------------------------------------------------------*/ +/* Test002: Destination IP address exact match against broadcast IP address */ +/*---------------------------------------------------------------------------*/ +class IpaFilteringBlockTest002 : public IpaFilteringBlockTestFixture +{ +public: + IpaFilteringBlockTest002() + { + m_name = "IpaFilteringBlockTest002"; + m_description = + "Filtering block test 002 - Destination IP address exact match against broadcast IP address (Global Filtering Table, Insert all rules in a single commit)\ + 1. Generate and commit three routing tables. \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit Three filtering rules (MASK = 0xFF..FF). \ + All DST_IP == 127.0.0.1 traffic goes to routing table 0 \ + All DST_IP == 192.169.1.1 traffic goes to routing table 1 \ + All DST_IP == 192.169.1.2 traffic goes to routing table 2"; + m_maxIPAHwType = IPA_HW_v2_6L; + Register(*this); + } + + + virtual bool AddRules() + { + printf("Entering %s, %s()\n",__FUNCTION__, __FILE__); + + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + struct ipa_ioc_get_rt_tbl routing_table0,routing_table1,routing_table2; + + if (!CreateThreeIPv4BypassRoutingTables (bypass0,bypass1,bypass2)) + { + printf("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + + printf("CreateThreeBypassRoutingTables completed successfully\n"); + routing_table0.ip = IPA_IP_v4; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + printf("m_routing.GetRoutingTable(&routing_table0=0x%p) Failed.\n",&routing_table0); + return false; + } + routing_table1.ip = IPA_IP_v4; + strlcpy(routing_table1.name, bypass1, sizeof(routing_table1.name)); + if (!m_routing.GetRoutingTable(&routing_table1)) + { + printf("m_routing.GetRoutingTable(&routing_table1=0x%p) Failed.\n",&routing_table1); + return false; + } + + routing_table2.ip = IPA_IP_v4; + strlcpy(routing_table2.name, bypass2, sizeof(routing_table2.name)); + if (!m_routing.GetRoutingTable(&routing_table2)) + { + printf("m_routing.GetRoutingTable(&routing_table2=0x%p) Failed.\n",&routing_table2); + return false; + } + + IPAFilteringTable FilterTable0; + struct ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v4,IPA_CLIENT_TEST_PROD,true,3); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1,flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl=-1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action=IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.rt_tbl_hdl=routing_table0.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; // TODO: Fix this, doesn't match the Rule's Requirements + flt_rule_entry.rule.attrib.u.v4.dst_addr_mask = 0xFFFFFFFF; // Exact Match + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0x7F000001; // Filter DST_IP == 127.0.0.1. + printf ("flt_rule_entry was set successfully, preparing for insertion....\n"); + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + printf ("%s::Error Adding RuleTable(0) to Filtering, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(0)->status); + } + + // Configuring Filtering Rule No.1 + flt_rule_entry.rule.rt_tbl_hdl=routing_table1.hdl; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0xC0A80101; // Filter DST_IP == 192.168.1.1. + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + printf ("%s::Error Adding RuleTable(1) to Filtering, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(1)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(1)->status); + } + + // Configuring Filtering Rule No.2 + flt_rule_entry.rule.rt_tbl_hdl=routing_table2.hdl; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0xC0A80102; // Filter DST_IP == 192.168.1.2. + + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + printf ("%s::Error Adding RuleTable(2) to Filtering, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(2)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(2)->status); + } + printf("Leaving %s, %s()\n",__FUNCTION__, __FILE__); + return true; + }// AddRules() + + virtual bool ModifyPackets() + { + int address; + // TODO: Add verification that we access only allocated addresses + // TODO: Fix this, doesn't match the Rule's Requirements + address = ntohl(0x7F000001);//127.0.0.1 + memcpy(&m_sendBuffer[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + address = ntohl(0xC0A80101);//192.168.1.1 + memcpy(&m_sendBuffer2[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + address = ntohl(0xC0A80102);//192.168.1.2 + memcpy(&m_sendBuffer3[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + + return true; + }// ModifyPacktes () +}; + + + +/*---------------------------------------------------------------------------*/ +/* Test003: Destination UDP port exact match against DHCP port */ +/*---------------------------------------------------------------------------*/ +class IpaFilteringBlockTest003 : public IpaFilteringBlockTestFixture +{ +public: + IpaFilteringBlockTest003() + { + m_name = "IpaFilteringBlockTest003"; + m_description = + "Filtering block test 003 - Destination UDP port exact match against DHCP port (Global Filtering Table, Insert all rules in a single commit)\ + 1. Generate and commit three routing tables. \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit Three filtering rules . \ + All DST_UDP_PORT == 546 (DHCP Client)traffic goes to routing table 0 \ + All DST_UDP_PORT == 547 (DHCP Server) traffic goes to routing table 1 \ + All DST_UDP_PORT == 500 (Non DHCP) traffic goes to routing table 2"; + m_maxIPAHwType = IPA_HW_v2_6L; + Register(*this); + } + + + virtual bool AddRules() + { + printf("Entering %s, %s()\n",__FUNCTION__, __FILE__); + + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + struct ipa_ioc_get_rt_tbl routing_table0,routing_table1,routing_table2; + + if (!CreateThreeIPv4BypassRoutingTables (bypass0,bypass1,bypass2)) + { + printf("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + + printf("CreateThreeBypassRoutingTables completed successfully\n"); + routing_table0.ip = IPA_IP_v4; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + printf("m_routing.GetRoutingTable(&routing_table0=0x%p) Failed.\n",&routing_table0); + return false; + } + routing_table1.ip = IPA_IP_v4; + strlcpy(routing_table1.name, bypass1, sizeof(routing_table1.name)); + if (!m_routing.GetRoutingTable(&routing_table1)) + { + printf("m_routing.GetRoutingTable(&routing_table1=0x%p) Failed.\n",&routing_table1); + return false; + } + + routing_table2.ip = IPA_IP_v4; + strlcpy(routing_table2.name, bypass2, sizeof(routing_table2.name)); + if (!m_routing.GetRoutingTable(&routing_table2)) + { + printf("m_routing.GetRoutingTable(&routing_table2=0x%p) Failed.\n",&routing_table2); + return false; + } + + IPAFilteringTable FilterTable0; + struct ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v4,IPA_CLIENT_TEST_PROD,true,3); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1,flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl=-1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action=IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.rt_tbl_hdl=routing_table0.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_PORT; + flt_rule_entry.rule.attrib.dst_port = 546; // DHCP Client Port No 546 + + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + printf ("%s::Error Adding RuleTable(0) to Filtering, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(0)->status); + } + + // Configuring Filtering Rule No.1 + flt_rule_entry.rule.rt_tbl_hdl=routing_table1.hdl; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.attrib.dst_port = 547; // DHCP Server Port No 547 + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + printf ("%s::Error Adding RuleTable(1) to Filtering, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(1)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(1)->status); + } + + // Configuring Filtering Rule No.2 + flt_rule_entry.rule.rt_tbl_hdl=routing_table2.hdl; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.attrib.dst_port = 500; // Non-DHCP Port + + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + printf ("%s::Error Adding RuleTable(2) to Filtering, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(2)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(2)->status); + } + printf("Leaving %s, %s()\n",__FUNCTION__, __FILE__); + return true; + }// AddRules() + + virtual bool ModifyPackets() + { + unsigned short port; + // TODO: Add verification that we access only allocated addresses + // TODO: Port should be switched to Network Mode. + port = ntohs(546);//DHCP Client Port + memcpy (&m_sendBuffer[IPV4_DST_PORT_OFFSET], &port, sizeof(port)); + port = ntohs(547);//DHCP Server Port + memcpy (&m_sendBuffer2[IPV4_DST_PORT_OFFSET], &port, sizeof(port)); + port = ntohs(500);//Non - DHCP Port + memcpy (&m_sendBuffer3[IPV4_DST_PORT_OFFSET], &port, sizeof(port)); + return true; + }// ModifyPacktes () +}; + +/*------------------------------------------------------------------------------*/ +/* Test004: Firewall filtering rules based on source and destination port ranges */ +/*------------------------------------------------------------------------------*/ +class IpaFilteringBlockTest004 : public IpaFilteringBlockTestFixture +{ +public: + IpaFilteringBlockTest004() + { + m_name = "IpaFilteringBlockTest004"; + m_description = + "Filtering block test 004 - Firewall filtering rules based on source and destination port ranges (Global Filtering Table, Insert all rules in a single commit)\ + 1. Generate and commit three routing tables. \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit Three filtering rules . \ + All (5 >= SRC_PORT_RANGE >= 15) & (50 >= DST_PORT_RANGE >= 150) traffic goes to routing table 0 \ + All (15 >= SRC_PORT_RANGE >= 25) & (150 >= DST_PORT_RANGE >= 250) traffic goes to routing table 1 \ + All (25 >= SRC_PORT_RANGE >= 35) & (250 >= DST_PORT_RANGE >= 350) traffic goes to routing table 2"; + m_maxIPAHwType = IPA_HW_v2_6L; + Register(*this); + } + + + virtual bool AddRules() + { + printf("Entering %s, %s()\n",__FUNCTION__, __FILE__); + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + struct ipa_ioc_get_rt_tbl routing_table0,routing_table1,routing_table2; + + if (!CreateThreeIPv4BypassRoutingTables (bypass0,bypass1,bypass2)) + { + printf("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + + printf("CreateThreeBypassRoutingTables completed successfully\n"); + routing_table0.ip = IPA_IP_v4; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + printf("m_routing.GetRoutingTable(&routing_table0=0x%p) Failed.\n",&routing_table0); + return false; + } + routing_table1.ip = IPA_IP_v4; + strlcpy(routing_table1.name, bypass1, sizeof(routing_table1.name)); + if (!m_routing.GetRoutingTable(&routing_table1)) + { + printf("m_routing.GetRoutingTable(&routing_table1=0x%p) Failed.\n",&routing_table1); + return false; + } + + routing_table2.ip = IPA_IP_v4; + strlcpy(routing_table2.name, bypass2, sizeof(routing_table2.name)); + if (!m_routing.GetRoutingTable(&routing_table2)) + { + printf("m_routing.GetRoutingTable(&routing_table2=0x%p) Failed.\n",&routing_table2); + return false; + } + + IPAFilteringTable FilterTable0; + struct ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v4,IPA_CLIENT_TEST_PROD,true,3); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1,flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl=-1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action=IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.rt_tbl_hdl=routing_table0.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_SRC_PORT_RANGE | IPA_FLT_DST_PORT_RANGE; + //TODO: Fix from here..... + flt_rule_entry.rule.attrib.src_port_lo =5; + flt_rule_entry.rule.attrib.src_port_hi =15; + flt_rule_entry.rule.attrib.dst_port_lo =50; + flt_rule_entry.rule.attrib.dst_port_hi =150; + + printf ("flt_rule_entry was set successfully, preparing for insertion....\n"); + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + printf ("%s::Error Adding RuleTable(0) to Filtering, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(0)->status); + } + + // Configuring Filtering Rule No.1 + flt_rule_entry.rule.rt_tbl_hdl=routing_table1.hdl; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.attrib.src_port_lo = 15; + flt_rule_entry.rule.attrib.src_port_hi = 25; + flt_rule_entry.rule.attrib.dst_port_lo = 150; + flt_rule_entry.rule.attrib.dst_port_hi = 250; + + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + printf ("%s::Error Adding RuleTable(1) to Filtering, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(1)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(1)->status); + } + + // Configuring Filtering Rule No.2 + flt_rule_entry.rule.rt_tbl_hdl=routing_table2.hdl; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.attrib.src_port_lo = 25; + flt_rule_entry.rule.attrib.src_port_hi = 35; + flt_rule_entry.rule.attrib.dst_port_lo = 250; + flt_rule_entry.rule.attrib.dst_port_hi = 350; + + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + printf ("%s::Error Adding RuleTable(2) to Filtering, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(2)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(2)->status); + } + printf("Leaving %s, %s()\n",__FUNCTION__, __FILE__); + return true; + }// AddRules() + + virtual bool ModifyPackets() + { + unsigned short port; + + // TODO: Add verification that we access only allocated addresses + port = htons(10); + memcpy(&m_sendBuffer[IPV4_SRC_PORT_OFFSET], &port, sizeof(port)); + port = htons(100); + memcpy(&m_sendBuffer[IPV4_DST_PORT_OFFSET], &port, sizeof(port)); + port = htons(20); + memcpy(&m_sendBuffer2[IPV4_SRC_PORT_OFFSET], &port, sizeof(port)); + port = htons(200); + memcpy(&m_sendBuffer2[IPV4_DST_PORT_OFFSET], &port, sizeof(port)); + port = htons(30); + memcpy(&m_sendBuffer3[IPV4_SRC_PORT_OFFSET], &port, sizeof(port)); + port = htons(300); + memcpy(&m_sendBuffer3[IPV4_DST_PORT_OFFSET], &port, sizeof(port)); + + return true; + }// ModifyPacktes () +}; +/*---------------------------------------------------------------------------*/ +/* Test005: Destination IP address exact match against broadcast IP address */ +/*---------------------------------------------------------------------------*/ +class IpaFilteringBlockTest005 : public IpaFilteringBlockTestFixture +{ +public: + IpaFilteringBlockTest005() + { + m_name = "IpaFilteringBlockTest005"; + m_description = + "Filtering block test 005 - Filtering Based on Protocol type (TCP/UDP/ICMP) (Global Filtering Table, Insert all rules in a single commit)\ + 1. Generate and commit three routing tables. \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit three filtering rules: (DST & Mask Match). \ + All UDP traffic goes to routing table 0 \ + All TCP traffic goes to routing table 1 \ + All ICMP traffic goes to routing table 2"; + m_maxIPAHwType = IPA_HW_v2_6L; + Register(*this); + } + + + virtual bool AddRules() + { + printf("Entering %s, %s()\n",__FUNCTION__, __FILE__); +// Test Description: +// 1. Generate and commit two routing tables. +// Each table will contain a single "bypass" rule (all data goes to output pipe 0 and 1 (accordingly)) +// 2. Generate and commit two filtering rules. +// All UDP traffic goes to routing table 1 +// All TCP traffic goes to routing table 2 + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + struct ipa_ioc_get_rt_tbl routing_table0,routing_table1,routing_table2; + + if (!CreateThreeIPv4BypassRoutingTables (bypass0,bypass1,bypass2)) + { + printf("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + + printf("CreateThreeBypassRoutingTables completed successfully\n"); + routing_table0.ip = IPA_IP_v4; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + printf("m_routing.GetRoutingTable(&routing_table0=0x%p) Failed.\n",&routing_table0); + return false; + } + routing_table1.ip = IPA_IP_v4; + strlcpy(routing_table1.name,bypass1, sizeof(routing_table1.name)); + if (!m_routing.GetRoutingTable(&routing_table1)) + { + printf("m_routing.GetRoutingTable(&routing_table1=0x%p) Failed.\n",&routing_table1); + return false; + } + + routing_table2.ip = IPA_IP_v4; + strlcpy(routing_table2.name, bypass2, sizeof(routing_table2.name)); + if (!m_routing.GetRoutingTable(&routing_table2)) + { + printf("m_routing.GetRoutingTable(&routing_table2=0x%p) Failed.\n",&routing_table2); + return false; + } + + IPAFilteringTable FilterTable0; + struct ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v4,IPA_CLIENT_TEST_PROD,true,3); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1,flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl=-1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action=IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.rt_tbl_hdl=routing_table0.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_PROTOCOL; + flt_rule_entry.rule.attrib.u.v4.protocol = 17; // Filter only UDP Packets. + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + printf ("%s::Error Adding RuleTable(0) to Filtering, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(0)->status); + } + + // Configuring Filtering Rule No.1 + flt_rule_entry.rule.rt_tbl_hdl=routing_table1.hdl; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.attrib.u.v4.protocol = 6; // Filter only TCP Packets. + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + printf ("%s::Error Adding RuleTable(1) to Filtering, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(1)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(1)->status); + } + + // Configuring Filtering Rule No.2 + flt_rule_entry.rule.rt_tbl_hdl=routing_table2.hdl; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.attrib.u.v4.protocol = 1; // Filter only ICMP Packets. + + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + printf ("%s::Error Adding RuleTable(2) to Filtering, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(2)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(2)->status); + } + printf("Leaving %s, %s()\n",__FUNCTION__, __FILE__); + return true; + }// AddRules() + + virtual bool ModifyPackets() + { + // TODO: Add verification that we access only allocated addresses + m_sendBuffer[IPV4_PROTOCOL_OFFSET] = 0x11;// UDP 0x11 = 17 + m_sendBuffer2[IPV4_PROTOCOL_OFFSET] = 0x06;// TCP 0x06 = 6 + m_sendBuffer3[IPV4_PROTOCOL_OFFSET] = 0x01;// ICMP 0x01 = 1 + return true; + }// ModifyPacktes () +}; + + +/*---------------------------------------------------------------------------*/ +/* Test006: Destination IP address and subnet mask match against LAN subnet */ +/*---------------------------------------------------------------------------*/ +class IpaFilteringBlockTest006 : public IpaFilteringBlockTestFixture +{ +public: + IpaFilteringBlockTest006() + { + m_name = "IpaFilteringBlockTest006"; + m_description = + "Filtering block test 006 - Destination IP address and subnet mask match against LAN subnet (Global Filtering Table, each rule is added in a Insert using a dedicated single commit)\ + 1. Generate and commit three routing tables. \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit Three filtering rules: (DST & Mask Match). \ + All DST_IP == (127.0.0.1 & 255.0.0.255)traffic goes to routing table 0 \ + All DST_IP == (192.169.1.1 & 255.0.0.255)traffic goes to routing table 1 \ + All DST_IP == (192.169.1.2 & 255.0.0.255)traffic goes to routing table 2"; + m_maxIPAHwType = IPA_HW_v2_6L; + Register(*this); + } + + + virtual bool AddRules() + { + printf("Entering %s, %s()\n",__FUNCTION__, __FILE__); + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + struct ipa_ioc_get_rt_tbl routing_table0,routing_table1,routing_table2; + + if (!CreateThreeIPv4BypassRoutingTables (bypass0,bypass1,bypass2)) + { + printf("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + + printf("CreateThreeBypassRoutingTables completed successfully\n"); + routing_table0.ip = IPA_IP_v4; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + printf("m_routing.GetRoutingTable(&routing_table0=0x%p) Failed.\n",&routing_table0); + return false; + } + routing_table1.ip = IPA_IP_v4; + strlcpy(routing_table1.name, bypass1, sizeof(routing_table1.name)); + if (!m_routing.GetRoutingTable(&routing_table1)) + { + printf("m_routing.GetRoutingTable(&routing_table1=0x%p) Failed.\n",&routing_table1); + return false; + } + + routing_table2.ip = IPA_IP_v4; + strlcpy(routing_table2.name, bypass2, sizeof(routing_table2.name)); + if (!m_routing.GetRoutingTable(&routing_table2)) + { + printf("m_routing.GetRoutingTable(&routing_table2=0x%p) Failed.\n",&routing_table2); + return false; + } + + IPAFilteringTable FilterTable0,FilterTable1,FilterTable2; + struct ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v4,IPA_CLIENT_TEST_PROD,true,1); + FilterTable1.Init(IPA_IP_v4,IPA_CLIENT_TEST_PROD,true,1); + FilterTable2.Init(IPA_IP_v4,IPA_CLIENT_TEST_PROD,true,1); + printf("FilterTable*.Init Completed Successfully..\n"); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1,flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl=-1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action=IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.rt_tbl_hdl=routing_table0.hdl; //put here the handle corresponding to Routing Rule 1 + // TODO: Fix this, doesn't match the Rule's Requirements + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; // TODO: Fix this, doesn't match the Rule's Requirements + flt_rule_entry.rule.attrib.u.v4.dst_addr_mask = 0xFF0000FF; // Mask + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0x7F000001; // Filter DST_IP == 127.0.0.1. + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + printf ("%s::Error Adding RuleTable(0) to Filtering, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(0)->status); + } + + // Configuring Filtering Rule No.1 // TODO: Fix this, doesn't match the Rule's Requirements + flt_rule_entry.rule.rt_tbl_hdl=routing_table1.hdl; //put here the handle corresponding to Routing Rule 2 + // TODO: Fix this, doesn't match the Rule's Requirements + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0xC0A80101; // Filter DST_IP == 192.168.1.1. + if ( + ((uint8_t)-1 == FilterTable1.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable1.GetFilteringTable()) + ) + { + printf ("%s::Error Adding RuleTable(1) to Filtering, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable1.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable1.ReadRuleFromTable(0)->status); + } + + // Configuring Filtering Rule No.2 // TODO: Fix this, doesn't match the Rule's Requirements + flt_rule_entry.rule.rt_tbl_hdl=routing_table2.hdl; //put here the handle corresponding to Routing Rule 2 + // TODO: Fix this, doesn't match the Rule's Requirements + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0xC0A80102; // Filter DST_IP == 192.168.1.2. + + if ( + ((uint8_t)-1 == FilterTable2.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable2.GetFilteringTable()) + ) + { + printf ("%s::Error Adding RuleTable(2) to Filtering, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable2.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable2.ReadRuleFromTable(0)->status); + } + printf("Leaving %s, %s()\n",__FUNCTION__, __FILE__); + return true; + }// AddRules() + + virtual bool ModifyPackets() + { + int address; + // TODO: Add verification that we access only allocated addresses + // TODO: Fix this, doesn't match the Rule's Requirements + address = ntohl(0x7F000001);//127.0.0.1 + memcpy(&m_sendBuffer[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + address = ntohl(0xC0A80101);//192.168.1.1 + memcpy(&m_sendBuffer2[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + address = ntohl(0xC0A80102);//192.168.1.2 + memcpy(&m_sendBuffer3[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + + return true; + return true; + }// ModifyPacktes () +}; + +/*---------------------------------------------------------------------------*/ +/* Test007: Destination IP address exact match against broadcast IP address */ +/*---------------------------------------------------------------------------*/ +class IpaFilteringBlockTest007 : public IpaFilteringBlockTestFixture +{ +public: + IpaFilteringBlockTest007() + { + m_name = "IpaFilteringBlockTest007"; + m_description = + "Filtering block test 007 - Destination IP address exact match against broadcast IP address (Global Filtering Table, each rule is added in a Insert using a dedicated single commit)\ + 1. Generate and commit three routing tables. \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit Three filtering rules (MASK = 0xFF..FF). \ + All DST_IP == 127.0.0.1 traffic goes to routing table 0 \ + All DST_IP == 192.169.1.1 traffic goes to routing table 1 \ + All DST_IP == 192.169.1.2 traffic goes to routing table 2"; + m_maxIPAHwType = IPA_HW_v2_6L; + Register(*this); + } + + + virtual bool AddRules() + { + printf("Entering %s, %s()\n",__FUNCTION__, __FILE__); + // Test Description: + // 1. Generate and commit three routing tables. + // Each table will contain a single "bypass" rule (all data goes to output pipe 0, 1 and 2(accordingly)) + // 2. Generate and commit three filtering rules (each in different Filtering Table) + // All Filter DST_IP == 127.0.0.1 traffic goes to routing table 1 + // All Filter DST_IP == 192.168.1.1 traffic goes to routing table 2 + // All Filter DST_IP == 192.168.1.2 traffic goes to routing table 3 + + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + struct ipa_ioc_get_rt_tbl routing_table0,routing_table1,routing_table2; + + if (!CreateThreeIPv4BypassRoutingTables (bypass0,bypass1,bypass2)) + { + printf("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + + printf("CreateThreeBypassRoutingTables completed successfully\n"); + routing_table0.ip = IPA_IP_v4; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + printf("m_routing.GetRoutingTable(&routing_table0=0x%p) Failed.\n",&routing_table0); + return false; + } + routing_table1.ip = IPA_IP_v4; + strlcpy(routing_table1.name, bypass1, sizeof(routing_table1.name)); + if (!m_routing.GetRoutingTable(&routing_table1)) + { + printf("m_routing.GetRoutingTable(&routing_table1=0x%p) Failed.\n",&routing_table1); + return false; + } + + routing_table2.ip = IPA_IP_v4; + strlcpy(routing_table2.name, bypass2,sizeof(routing_table2.name) ); + if (!m_routing.GetRoutingTable(&routing_table2)) + { + printf("m_routing.GetRoutingTable(&routing_table2=0x%p) Failed.\n",&routing_table2); + return false; + } + + IPAFilteringTable FilterTable0,FilterTable1,FilterTable2; + struct ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v4,IPA_CLIENT_TEST_PROD,true,1); + FilterTable1.Init(IPA_IP_v4,IPA_CLIENT_TEST_PROD,true,1); + FilterTable2.Init(IPA_IP_v4,IPA_CLIENT_TEST_PROD,true,1); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1,flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl=-1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action=IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.rt_tbl_hdl=routing_table0.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; // TODO: Fix this, doesn't match the Rule's Requirements + flt_rule_entry.rule.attrib.u.v4.dst_addr_mask = 0xFFFFFFFF; // Exact Match + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0x7F000001; // Filter DST_IP == 127.0.0.1. + printf ("flt_rule_entry was set successfully, preparing for insertion....\n"); + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + printf ("%s::Error Adding RuleTable(0) to Filtering, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(0)->status); + } + + // Configuring Filtering Rule No.1 + flt_rule_entry.rule.rt_tbl_hdl=routing_table1.hdl; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0xC0A80101; // Filter DST_IP == 192.168.1.1. + if ( + ((uint8_t)-1 == FilterTable1.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable1.GetFilteringTable()) + ) + { + printf ("%s::Error Adding RuleTable(1) to Filtering, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable1.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable1.ReadRuleFromTable(0)->status); + } + + // Configuring Filtering Rule No.2 + flt_rule_entry.rule.rt_tbl_hdl=routing_table2.hdl; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0xC0A80102; // Filter DST_IP == 192.168.1.2. + + if ( + ((uint8_t)-1 == FilterTable2.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable2.GetFilteringTable()) + ) + { + printf ("%s::Error Adding RuleTable(2) to Filtering, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable2.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable2.ReadRuleFromTable(0)->status); + } + printf("Leaving %s, %s()\n",__FUNCTION__, __FILE__); + return true; + }// AddRules() + + virtual bool ModifyPackets() + { + int address; + // TODO: Add verification that we access only allocated addresses + // TODO: Fix this, doesn't match the Rule's Requirements + address = ntohl(0x7F000001);//127.0.0.1 + memcpy(&m_sendBuffer[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + address = ntohl(0xC0A80101);//192.168.1.1 + memcpy(&m_sendBuffer2[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + address = ntohl(0xC0A80102);//192.168.1.2 + memcpy(&m_sendBuffer3[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + + return true; + }// ModifyPacktes () +}; + + + +/*---------------------------------------------------------------------------*/ +/* Test008: Destination UDP port exact match against DHCP port */ +/*---------------------------------------------------------------------------*/ +class IpaFilteringBlockTest008 : public IpaFilteringBlockTestFixture +{ +public: + IpaFilteringBlockTest008() + { + m_name = "IpaFilteringBlockTest008"; + m_description = + "Filtering block test 008 - Destination UDP port exact match against DHCP port (Global Filtering Table, each rule is added in a Insert using a dedicated single commit)\ + 1. Generate and commit three routing tables. \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit Three filtering rules . \ + All DST_UDP_PORT == 546 (DHCP Client)traffic goes to routing table 0 \ + All DST_UDP_PORT == 547 (DHCP Server) traffic goes to routing table 1 \ + All DST_UDP_PORT == 500 (Non DHCP) traffic goes to routing table 2"; + m_maxIPAHwType = IPA_HW_v2_6L; + Register(*this); + } + + + virtual bool AddRules() + { + printf("Entering %s, %s()\n",__FUNCTION__, __FILE__); +// Test Description: +// 1. Generate and commit three routing tables. +// Each table will contain a single "bypass" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) +// 2. Generate and commit Three filtering rules. +// All DEST_IP == 127.0.0.1 traffic goes to routing table 0 +// All DEST_IP == 192.169.1.1 traffic goes to routing table 1 +// Non Matching traffic goes to routing table 3 + + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + struct ipa_ioc_get_rt_tbl routing_table0,routing_table1,routing_table2; + + if (!CreateThreeIPv4BypassRoutingTables (bypass0,bypass1,bypass2)) + { + printf("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + + printf("CreateThreeBypassRoutingTables completed successfully\n"); + routing_table0.ip = IPA_IP_v4; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + printf("m_routing.GetRoutingTable(&routing_table0=0x%p) Failed.\n",&routing_table0); + return false; + } + routing_table1.ip = IPA_IP_v4; + strlcpy(routing_table1.name, bypass1, sizeof(routing_table1.name)); + if (!m_routing.GetRoutingTable(&routing_table1)) + { + printf("m_routing.GetRoutingTable(&routing_table1=0x%p) Failed.\n",&routing_table1); + return false; + } + + routing_table2.ip = IPA_IP_v4; + strlcpy(routing_table2.name, bypass2, sizeof(routing_table2.name)); + if (!m_routing.GetRoutingTable(&routing_table2)) + { + printf("m_routing.GetRoutingTable(&routing_table2=0x%p) Failed.\n",&routing_table2); + return false; + } + + IPAFilteringTable FilterTable0,FilterTable1,FilterTable2; + struct ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v4,IPA_CLIENT_TEST_PROD,true,1); + FilterTable1.Init(IPA_IP_v4,IPA_CLIENT_TEST_PROD,true,1); + FilterTable2.Init(IPA_IP_v4,IPA_CLIENT_TEST_PROD,true,1); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1,flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl=-1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action=IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.rt_tbl_hdl=routing_table0.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_PORT; + flt_rule_entry.rule.attrib.dst_port = 546; // DHCP Client Port No 546 + + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + printf ("%s::Error Adding RuleTable(0) to Filtering, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(0)->status); + } + + // Configuring Filtering Rule No.1 + flt_rule_entry.rule.rt_tbl_hdl=routing_table1.hdl; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.attrib.dst_port = 547; // DHCP Server Port No 547 + if ( + ((uint8_t)-1 == FilterTable1.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable1.GetFilteringTable()) + ) + { + printf ("%s::Error Adding RuleTable(1) to Filtering, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable1.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable1.ReadRuleFromTable(0)->status); + } + + // Configuring Filtering Rule No.2 + flt_rule_entry.rule.rt_tbl_hdl=routing_table2.hdl; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.attrib.dst_port = 500; // Non-DHCP Port + + if ( + ((uint8_t)-1 == FilterTable2.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable2.GetFilteringTable()) + ) + { + printf ("%s::Error Adding RuleTable(2) to Filtering, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable2.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable2.ReadRuleFromTable(0)->status); + } + printf("Leaving %s, %s()\n",__FUNCTION__, __FILE__); + return true; + }// AddRules() + + virtual bool ModifyPackets() + { + unsigned short port; + // TODO: Add verification that we access only allocated addresses + // TODO: Port should be switched to Network Mode. + port = ntohs(546);//DHCP Client Port + memcpy (&m_sendBuffer[IPV4_DST_PORT_OFFSET], &port, sizeof(port)); + port = ntohs(547);//DHCP Server Port + memcpy (&m_sendBuffer2[IPV4_DST_PORT_OFFSET], &port, sizeof(port)); + port = ntohs(500);//Non - DHCP Port + memcpy (&m_sendBuffer3[IPV4_DST_PORT_OFFSET], &port, sizeof(port)); + + return true; + }// ModifyPacktes () +}; + +/*------------------------------------------------------------------------------*/ +/* Test009: Firewall filtering rules based on source and destination port ranges */ +/*------------------------------------------------------------------------------*/ +class IpaFilteringBlockTest009 : public IpaFilteringBlockTestFixture +{ +public: + IpaFilteringBlockTest009() + { + m_name = "IpaFilteringBlockTest009"; + m_description = + "Filtering block test 009 - Firewall filtering rules based on source and destination port ranges (Global Filtering Table, each rule is added in a Insert using a dedicated single commit)\ + 1. Generate and commit three routing tables. \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit Three filtering rules . \ + All (5 >= SRC_PORT_RANGE >= 15) & (50 >= DST_PORT_RANGE >= 150) traffic goes to routing table 0 \ + All (15 >= SRC_PORT_RANGE >= 25) & (150 >= DST_PORT_RANGE >= 250) traffic goes to routing table 1 \ + All (25 >= SRC_PORT_RANGE >= 35) & (250 >= DST_PORT_RANGE >= 350) traffic goes to routing table 2"; + m_maxIPAHwType = IPA_HW_v2_6L; + Register(*this); + } + + + virtual bool AddRules() + { + printf("Entering %s, %s()\n",__FUNCTION__, __FILE__); +// Test Description: +// 1. Generate and commit two routing tables. +// Each table will contain a single "bypass" rule (all data goes to output pipe 0 and 1 (accordingly)) +// 2. Generate and commit two filtering rules. +// All UDP traffic goes to routing table 1 +// All TCP traffic goes to routing table 2 + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + struct ipa_ioc_get_rt_tbl routing_table0,routing_table1,routing_table2; + + if (!CreateThreeIPv4BypassRoutingTables (bypass0,bypass1,bypass2)) + { + printf("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + + printf("CreateThreeBypassRoutingTables completed successfully\n"); + routing_table0.ip = IPA_IP_v4; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + printf("m_routing.GetRoutingTable(&routing_table0=0x%p) Failed.\n",&routing_table0); + return false; + } + routing_table1.ip = IPA_IP_v4; + strlcpy(routing_table1.name, bypass1, sizeof(routing_table1.name)); + if (!m_routing.GetRoutingTable(&routing_table1)) + { + printf("m_routing.GetRoutingTable(&routing_table1=0x%p) Failed.\n",&routing_table1); + return false; + } + + routing_table2.ip = IPA_IP_v4; + strlcpy(routing_table2.name, bypass2, sizeof(routing_table2.name)); + if (!m_routing.GetRoutingTable(&routing_table2)) + { + printf("m_routing.GetRoutingTable(&routing_table2=0x%p) Failed.\n",&routing_table2); + return false; + } + + IPAFilteringTable FilterTable0,FilterTable1,FilterTable2; + struct ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v4,IPA_CLIENT_TEST_PROD,true,1); + FilterTable1.Init(IPA_IP_v4,IPA_CLIENT_TEST_PROD,true,1); + FilterTable2.Init(IPA_IP_v4,IPA_CLIENT_TEST_PROD,true,1); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1,flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl=-1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action=IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.rt_tbl_hdl=routing_table0.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_SRC_PORT_RANGE | IPA_FLT_DST_PORT_RANGE; + //TODO: Fix from here..... + flt_rule_entry.rule.attrib.src_port_lo =5; + flt_rule_entry.rule.attrib.src_port_hi =15; + flt_rule_entry.rule.attrib.dst_port_lo =50; + flt_rule_entry.rule.attrib.dst_port_hi =150; + + printf ("flt_rule_entry was set successfully, preparing for insertion....\n"); + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + printf ("%s::Error Adding RuleTable(0) to Filtering, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(0)->status); + } + + // Configuring Filtering Rule No.1 + flt_rule_entry.rule.rt_tbl_hdl=routing_table1.hdl; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.attrib.src_port_lo = 15; + flt_rule_entry.rule.attrib.src_port_hi = 25; + flt_rule_entry.rule.attrib.dst_port_lo = 150; + flt_rule_entry.rule.attrib.dst_port_hi = 250; + + if ( + ((uint8_t)-1 == FilterTable1.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable1.GetFilteringTable()) + ) + { + printf ("%s::Error Adding RuleTable(1) to Filtering, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable1.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable1.ReadRuleFromTable(0)->status); + } + + // Configuring Filtering Rule No.2 + flt_rule_entry.rule.rt_tbl_hdl=routing_table2.hdl; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.attrib.src_port_lo = 25; + flt_rule_entry.rule.attrib.src_port_hi = 35; + flt_rule_entry.rule.attrib.dst_port_lo = 250; + flt_rule_entry.rule.attrib.dst_port_hi = 350; + + if ( + ((uint8_t)-1 == FilterTable2.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable2.GetFilteringTable()) + ) + { + printf ("%s::Error Adding RuleTable(2) to Filtering, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable2.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable2.ReadRuleFromTable(0)->status); + } + printf("Leaving %s, %s()\n",__FUNCTION__, __FILE__); + return true; + }// AddRules() + + virtual bool ModifyPackets() + { + unsigned short port; + + // TODO: Add verification that we access only allocated addresses + port = htons(10); + memcpy(&m_sendBuffer[IPV4_SRC_PORT_OFFSET], &port, sizeof(port)); + port = htons(100); + memcpy(&m_sendBuffer[IPV4_DST_PORT_OFFSET], &port, sizeof(port)); + port = htons(20); + memcpy(&m_sendBuffer2[IPV4_SRC_PORT_OFFSET], &port, sizeof(port)); + port = htons(200); + memcpy(&m_sendBuffer2[IPV4_DST_PORT_OFFSET], &port, sizeof(port)); + port = htons(30); + memcpy(&m_sendBuffer3[IPV4_SRC_PORT_OFFSET], &port, sizeof(port)); + port = htons(300); + memcpy(&m_sendBuffer3[IPV4_DST_PORT_OFFSET], &port, sizeof(port)); + + return true; + }// ModifyPacktes () +}; +/*---------------------------------------------------------------------------*/ +/* Test010: Destination IP address exact match against broadcast IP address */ +/*---------------------------------------------------------------------------*/ +class IpaFilteringBlockTest010 : public IpaFilteringBlockTestFixture +{ +public: + IpaFilteringBlockTest010() + { + m_name = "IpaFilteringBlockTest010"; + m_description = + "Filtering block test 010 - Filtering Based on Protocol type (TCP/UDP/ICMP) (Global Filtering Table, each rule is added in a Insert using a dedicated single commit)\ + 1. Generate and commit three routing tables. \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit three filtering rules: (DST & Mask Match). \ + All UDP traffic goes to routing table 0 \ + All TCP traffic goes to routing table 1 \ + All ICMP traffic goes to routing table 2"; + m_maxIPAHwType = IPA_HW_v2_6L; + Register(*this); + } + + + virtual bool AddRules() + { + printf("Entering %s, %s()\n",__FUNCTION__, __FILE__); +// Test Description: +// 1. Generate and commit two routing tables. +// Each table will contain a single "bypass" rule (all data goes to output pipe 0 and 1 (accordingly)) +// 2. Generate and commit two filtering rules. +// All UDP traffic goes to routing table 1 +// All TCP traffic goes to routing table 2 + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + struct ipa_ioc_get_rt_tbl routing_table0,routing_table1,routing_table2; + + if (!CreateThreeIPv4BypassRoutingTables (bypass0,bypass1,bypass2)) + { + printf("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + + printf("CreateThreeBypassRoutingTables completed successfully\n"); + routing_table0.ip = IPA_IP_v4; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + printf("m_routing.GetRoutingTable(&routing_table0=0x%p) Failed.\n",&routing_table0); + return false; + } + routing_table1.ip = IPA_IP_v4; + strlcpy(routing_table1.name, bypass1, sizeof(routing_table1.name)); + if (!m_routing.GetRoutingTable(&routing_table1)) + { + printf("m_routing.GetRoutingTable(&routing_table1=0x%p) Failed.\n",&routing_table1); + return false; + } + + routing_table2.ip = IPA_IP_v4; + strlcpy(routing_table2.name, bypass2, sizeof(routing_table2.name)); + if (!m_routing.GetRoutingTable(&routing_table2)) + { + printf("m_routing.GetRoutingTable(&routing_table2=0x%p) Failed.\n",&routing_table2); + return false; + } + + IPAFilteringTable FilterTable0,FilterTable1,FilterTable2; + struct ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v4,IPA_CLIENT_TEST_PROD,true,1); + FilterTable1.Init(IPA_IP_v4,IPA_CLIENT_TEST_PROD,true,1); + FilterTable2.Init(IPA_IP_v4,IPA_CLIENT_TEST_PROD,true,1); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1,flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl=-1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action=IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.rt_tbl_hdl=routing_table0.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_PROTOCOL; + flt_rule_entry.rule.attrib.u.v4.protocol = 17; // Filter only UDP Packets. + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + printf ("%s::Error Adding RuleTable(0) to Filtering, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(0)->status); + } + + // Configuring Filtering Rule No.1 + flt_rule_entry.rule.rt_tbl_hdl=routing_table1.hdl; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.attrib.u.v4.protocol = 6; // Filter only TCP Packets. + if ( + ((uint8_t)-1 == FilterTable1.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable1.GetFilteringTable()) + ) + { + printf ("%s::Error Adding RuleTable(1) to Filtering, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable1.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable1.ReadRuleFromTable(0)->status); + } + + // Configuring Filtering Rule No.2 + flt_rule_entry.rule.rt_tbl_hdl=routing_table2.hdl; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.attrib.u.v4.protocol = 1; // Filter only ICMP Packets. + + if ( + ((uint8_t)-1 == FilterTable2.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable2.GetFilteringTable()) + ) + { + printf ("%s::Error Adding RuleTable(2) to Filtering, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable2.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable2.ReadRuleFromTable(0)->status); + } + printf("Leaving %s, %s()\n",__FUNCTION__, __FILE__); + return true; + }// AddRules() + + virtual bool ModifyPackets() + { + // TODO: Add verification that we access only allocated addresses + m_sendBuffer[IPV4_PROTOCOL_OFFSET] = 0x11;// UDP 0x11 = 17 + m_sendBuffer2[IPV4_PROTOCOL_OFFSET] = 0x06;// TCP 0x06 = 6 + m_sendBuffer3[IPV4_PROTOCOL_OFFSET] = 0x01;// ICMP 0x01 = 1 + return true; + }// ModifyPacktes () +}; + + +/*---------------------------------------------------------------------------*/ +/* Test021: Destination IP address and subnet mask match against LAN subnet */ +/*---------------------------------------------------------------------------*/ +class IpaFilteringBlockTest021 : public IpaFilteringBlockTestFixture +{ +public: + IpaFilteringBlockTest021() + { + m_name = "IpaFilteringBlockTest021"; + m_description = + "Filtering block test 021 - Destination IP address and subnet mask match against LAN subnet (End-Point specific Filtering Table, Insert all rules in a single commit)\ + 1. Generate and commit three routing tables. \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit Three filtering rules: (DST & Mask Match). \ + All DST_IP == (127.0.0.1 & 255.0.0.255)traffic goes to routing table 0 \ + All DST_IP == (192.169.1.1 & 255.0.0.255)traffic goes to routing table 1 \ + All DST_IP == (192.169.1.2 & 255.0.0.255)traffic goes to routing table 2"; + Register(*this); + } + + + virtual bool AddRules() + { + printf("Entering %s, %s()\n",__FUNCTION__, __FILE__); + + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + struct ipa_ioc_get_rt_tbl routing_table0,routing_table1,routing_table2; + + if (!CreateThreeIPv4BypassRoutingTables (bypass0,bypass1,bypass2)) + { + printf("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + + printf("CreateThreeBypassRoutingTables completed successfully\n"); + routing_table0.ip = IPA_IP_v4; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + printf("m_routing.GetRoutingTable(&routing_table0=0x%p) Failed.\n",&routing_table0); + return false; + } + printf("%s route table handle = %u\n", bypass0, routing_table0.hdl); + + routing_table1.ip = IPA_IP_v4; + strlcpy(routing_table1.name, bypass1, sizeof(routing_table1.name)); + if (!m_routing.GetRoutingTable(&routing_table1)) + { + printf("m_routing.GetRoutingTable(&routing_table1=0x%p) Failed.\n",&routing_table1); + return false; + } + printf("%s route table handle = %u\n", bypass1, routing_table1.hdl); + + routing_table2.ip = IPA_IP_v4; + strlcpy(routing_table2.name, bypass2, sizeof(routing_table2.name)); + if (!m_routing.GetRoutingTable(&routing_table2)) + { + printf("m_routing.GetRoutingTable(&routing_table2=0x%p) Failed.\n",&routing_table2); + return false; + } + printf("%s route table handle = %u\n", bypass2, routing_table2.hdl); + + IPAFilteringTable FilterTable0; + struct ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v4,IPA_CLIENT_TEST_PROD,false,3); + printf("FilterTable*.Init Completed Successfully..\n"); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1,flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl=-1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action=IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.rt_tbl_hdl=routing_table0.hdl; //put here the handle corresponding to Routing Rule 1 + // TODO: Fix this, doesn't match the Rule's Requirements + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; // TODO: Fix this, doesn't match the Rule's Requirements + flt_rule_entry.rule.attrib.u.v4.dst_addr_mask = 0xFF0000FF; // Mask + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0x7F000001; // Filter DST_IP == 127.0.0.1. + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.1 // TODO: Fix this, doesn't match the Rule's Requirements + flt_rule_entry.rule.rt_tbl_hdl=routing_table1.hdl; //put here the handle corresponding to Routing Rule 2 + // TODO: Fix this, doesn't match the Rule's Requirements + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0xC0A80101; // Filter DST_IP == 192.168.1.1. + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.2 // TODO: Fix this, doesn't match the Rule's Requirements + flt_rule_entry.rule.rt_tbl_hdl=routing_table2.hdl; //put here the handle corresponding to Routing Rule 2 + // TODO: Fix this, doesn't match the Rule's Requirements + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0xC0A80102; // Filter DST_IP == 192.168.1.2. + + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(0)->status); + printf("flt rule hdl1=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(1)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(1)->status); + printf("flt rule hdl2=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(2)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(2)->status); + } + + printf("Leaving %s, %s()\n",__FUNCTION__, __FILE__); + return true; + }// AddRules() + + virtual bool ModifyPackets() + { + int address; + // TODO: Add verification that we access only allocated addresses + // TODO: Fix this, doesn't match the Rule's Requirements + address = ntohl(0x7F000001);//127.0.0.1 + memcpy(&m_sendBuffer[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + address = ntohl(0xC0A80101);//192.168.1.1 + memcpy(&m_sendBuffer2[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + address = ntohl(0xC0A80102);//192.168.1.2 + memcpy(&m_sendBuffer3[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + + return true; + }// ModifyPacktes () +}; + +/*---------------------------------------------------------------------------*/ +/* Test022: Destination IP address exact match against broadcast IP address */ +/*---------------------------------------------------------------------------*/ +class IpaFilteringBlockTest022 : public IpaFilteringBlockTestFixture +{ +public: + IpaFilteringBlockTest022() + { + m_name = "IpaFilteringBlockTest022"; + m_description = + "Filtering block test 022 - Destination IP address exact match against broadcast IP address (End-Point specific Filtering Table, Insert all rules in a single commit)\ + 1. Generate and commit three routing tables. \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit Three filtering rules (MASK = 0xFF..FF). \ + All DST_IP == 127.0.0.1 traffic goes to routing table 0 \ + All DST_IP == 192.169.1.1 traffic goes to routing table 1 \ + All DST_IP == 192.169.1.2 traffic goes to routing table 2"; + Register(*this); + } + + + virtual bool AddRules() + { + printf("Entering %s, %s()\n",__FUNCTION__, __FILE__); + + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + struct ipa_ioc_get_rt_tbl routing_table0,routing_table1,routing_table2; + + if (!CreateThreeIPv4BypassRoutingTables (bypass0,bypass1,bypass2)) + { + printf("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + + printf("CreateThreeBypassRoutingTables completed successfully\n"); + routing_table0.ip = IPA_IP_v4; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + printf("m_routing.GetRoutingTable(&routing_table0=0x%p) Failed.\n",&routing_table0); + return false; + } + routing_table1.ip = IPA_IP_v4; + strlcpy(routing_table1.name, bypass1, sizeof(routing_table1.name)); + if (!m_routing.GetRoutingTable(&routing_table1)) + { + printf("m_routing.GetRoutingTable(&routing_table1=0x%p) Failed.\n",&routing_table1); + return false; + } + + routing_table2.ip = IPA_IP_v4; + strlcpy(routing_table2.name, bypass2, sizeof(routing_table2.name)); + if (!m_routing.GetRoutingTable(&routing_table2)) + { + printf("m_routing.GetRoutingTable(&routing_table2=0x%p) Failed.\n",&routing_table2); + return false; + } + + IPAFilteringTable FilterTable0; + struct ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v4,IPA_CLIENT_TEST_PROD,false,3); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1,flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl=-1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action=IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.rt_tbl_hdl=routing_table0.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; // TODO: Fix this, doesn't match the Rule's Requirements + flt_rule_entry.rule.attrib.u.v4.dst_addr_mask = 0xFFFFFFFF; // Exact Match + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0x7F000001; // Filter DST_IP == 127.0.0.1. + printf ("flt_rule_entry was set successfully, preparing for insertion....\n"); + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.1 + flt_rule_entry.rule.rt_tbl_hdl=routing_table1.hdl; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0xC0A80101; // Filter DST_IP == 192.168.1.1. + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.2 + flt_rule_entry.rule.rt_tbl_hdl=routing_table2.hdl; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0xC0A80102; // Filter DST_IP == 192.168.1.2. + + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } else { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(0)->status); + printf("flt rule hdl1=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(1)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(1)->status); + printf("flt rule hdl2=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(2)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(2)->status); + } + printf("Leaving %s, %s()\n",__FUNCTION__, __FILE__); + return true; + }// AddRules() + + virtual bool ModifyPackets() + { + int address; + // TODO: Add verification that we access only allocated addresses + // TODO: Fix this, doesn't match the Rule's Requirements + address = ntohl(0x7F000001);//127.0.0.1 + memcpy(&m_sendBuffer[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + address = ntohl(0xC0A80101);//192.168.1.1 + memcpy(&m_sendBuffer2[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + address = ntohl(0xC0A80102);//192.168.1.2 + memcpy(&m_sendBuffer3[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + + return true; + }// ModifyPacktes () +}; + + + +/*---------------------------------------------------------------------------*/ +/* Test023: Destination UDP port exact match against DHCP port */ +/*---------------------------------------------------------------------------*/ +class IpaFilteringBlockTest023 : public IpaFilteringBlockTestFixture +{ +public: + IpaFilteringBlockTest023() + { + m_name = "IpaFilteringBlockTest023"; + m_description = + "Filtering block test 023 - Destination UDP port exact match against DHCP port (End-Point specific Filtering Table, Insert all rules in a single commit)\ + 1. Generate and commit three routing tables. \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit Three filtering rules . \ + All DST_UDP_PORT == 546 (DHCP Client)traffic goes to routing table 0 \ + All DST_UDP_PORT == 547 (DHCP Server) traffic goes to routing table 1 \ + All DST_UDP_PORT == 500 (Non DHCP) traffic goes to routing table 2"; + Register(*this); + } + + + virtual bool AddRules() + { + printf("Entering %s, %s()\n",__FUNCTION__, __FILE__); + + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + struct ipa_ioc_get_rt_tbl routing_table0,routing_table1,routing_table2; + + if (!CreateThreeIPv4BypassRoutingTables (bypass0,bypass1,bypass2)) + { + printf("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + + printf("CreateThreeBypassRoutingTables completed successfully\n"); + routing_table0.ip = IPA_IP_v4; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + printf("m_routing.GetRoutingTable(&routing_table0=0x%p) Failed.\n",&routing_table0); + return false; + } + routing_table1.ip = IPA_IP_v4; + strlcpy(routing_table1.name, bypass1, sizeof(routing_table1.name)); + if (!m_routing.GetRoutingTable(&routing_table1)) + { + printf("m_routing.GetRoutingTable(&routing_table1=0x%p) Failed.\n",&routing_table1); + return false; + } + + routing_table2.ip = IPA_IP_v4; + strlcpy(routing_table2.name, bypass2, sizeof(routing_table2.name)); + if (!m_routing.GetRoutingTable(&routing_table2)) + { + printf("m_routing.GetRoutingTable(&routing_table2=0x%p) Failed.\n",&routing_table2); + return false; + } + + IPAFilteringTable FilterTable0; + struct ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v4,IPA_CLIENT_TEST_PROD,false,3); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1,flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl=-1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action=IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.rt_tbl_hdl=routing_table0.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_PORT; + flt_rule_entry.rule.attrib.dst_port = 546; // DHCP Client Port No 546 + + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.1 + flt_rule_entry.rule.rt_tbl_hdl=routing_table1.hdl; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.attrib.dst_port = 547; // DHCP Server Port No 547 + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.2 + flt_rule_entry.rule.rt_tbl_hdl=routing_table2.hdl; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.attrib.dst_port = 500; // Non-DHCP Port + + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } else { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(0)->status); + printf("flt rule hdl1=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(1)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(1)->status); + printf("flt rule hdl2=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(2)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(2)->status); + } + printf("Leaving %s, %s()\n",__FUNCTION__, __FILE__); + return true; + }// AddRules() + + virtual bool ModifyPackets() + { + unsigned short port; + // TODO: Add verification that we access only allocated addresses + // TODO: Port should be switched to Network Mode. + port = ntohs(546);//DHCP Client Port + memcpy (&m_sendBuffer[IPV4_DST_PORT_OFFSET], &port, sizeof(port)); + port = ntohs(547);//DHCP Server Port + memcpy (&m_sendBuffer2[IPV4_DST_PORT_OFFSET], &port, sizeof(port)); + port = ntohs(500);//Non - DHCP Port + memcpy (&m_sendBuffer3[IPV4_DST_PORT_OFFSET], &port, sizeof(port)); + + return true; + }// ModifyPacktes () +}; + +/*------------------------------------------------------------------------------*/ +/* Test004: Firewall filtering rules based on source and destination port ranges*/ +/*------------------------------------------------------------------------------*/ +class IpaFilteringBlockTest024 : public IpaFilteringBlockTestFixture +{ +public: + IpaFilteringBlockTest024() + { + m_name = "IpaFilteringBlockTest024"; + m_description = + "Filtering block test 024 - Firewall filtering rules based on source and destination port ranges (End-Point specific Filtering Table, Insert all rules in a single commit)\ + 1. Generate and commit three routing tables. \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit Three filtering rules . \ + All (5 >= SRC_PORT_RANGE >= 15) & (50 >= DST_PORT_RANGE >= 150) traffic goes to routing table 0 \ + All (15 >= SRC_PORT_RANGE >= 25) & (150 >= DST_PORT_RANGE >= 250) traffic goes to routing table 1 \ + All (25 >= SRC_PORT_RANGE >= 35) & (250 >= DST_PORT_RANGE >= 350) traffic goes to routing table 2"; + Register(*this); + } + + + virtual bool AddRules() + { + printf("Entering %s, %s()\n",__FUNCTION__, __FILE__); + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + struct ipa_ioc_get_rt_tbl routing_table0,routing_table1,routing_table2; + + if (!CreateThreeIPv4BypassRoutingTables (bypass0,bypass1,bypass2)) + { + printf("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + + printf("CreateThreeBypassRoutingTables completed successfully\n"); + routing_table0.ip = IPA_IP_v4; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + printf("m_routing.GetRoutingTable(&routing_table0=0x%p) Failed.\n",&routing_table0); + return false; + } + routing_table1.ip = IPA_IP_v4; + strlcpy(routing_table1.name, bypass1, sizeof(routing_table1.name)); + if (!m_routing.GetRoutingTable(&routing_table1)) + { + printf("m_routing.GetRoutingTable(&routing_table1=0x%p) Failed.\n",&routing_table1); + return false; + } + + routing_table2.ip = IPA_IP_v4; + strlcpy(routing_table2.name, bypass2, sizeof(routing_table2.name)); + if (!m_routing.GetRoutingTable(&routing_table2)) + { + printf("m_routing.GetRoutingTable(&routing_table2=0x%p) Failed.\n",&routing_table2); + return false; + } + + IPAFilteringTable FilterTable0; + struct ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v4,IPA_CLIENT_TEST_PROD,false,3); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1,flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl=-1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action=IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.rt_tbl_hdl=routing_table0.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_SRC_PORT_RANGE | IPA_FLT_DST_PORT_RANGE; + //TODO: Fix from here..... + flt_rule_entry.rule.attrib.src_port_lo =5; + flt_rule_entry.rule.attrib.src_port_hi =15; + flt_rule_entry.rule.attrib.dst_port_lo =50; + flt_rule_entry.rule.attrib.dst_port_hi =150; + + printf ("flt_rule_entry was set successfully, preparing for insertion....\n"); + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.1 + flt_rule_entry.rule.rt_tbl_hdl=routing_table1.hdl; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.attrib.src_port_lo = 15; + flt_rule_entry.rule.attrib.src_port_hi = 25; + flt_rule_entry.rule.attrib.dst_port_lo = 150; + flt_rule_entry.rule.attrib.dst_port_hi = 250; + + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.2 + flt_rule_entry.rule.rt_tbl_hdl=routing_table2.hdl; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.attrib.src_port_lo = 25; + flt_rule_entry.rule.attrib.src_port_hi = 35; + flt_rule_entry.rule.attrib.dst_port_lo = 250; + flt_rule_entry.rule.attrib.dst_port_hi = 350; + + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(0)->status); + printf("flt rule hdl1=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(1)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(1)->status); + printf("flt rule hdl2=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(2)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(2)->status); + } + printf("Leaving %s, %s()\n",__FUNCTION__, __FILE__); + return true; + }// AddRules() + + virtual bool ModifyPackets() + { + unsigned short port; + + // TODO: Add verification that we access only allocated addresses + port = htons(10); + memcpy(&m_sendBuffer[IPV4_SRC_PORT_OFFSET], &port, sizeof(port)); + port = htons(100); + memcpy(&m_sendBuffer[IPV4_DST_PORT_OFFSET], &port, sizeof(port)); + port = htons(20); + memcpy(&m_sendBuffer2[IPV4_SRC_PORT_OFFSET], &port, sizeof(port)); + port = htons(200); + memcpy(&m_sendBuffer2[IPV4_DST_PORT_OFFSET], &port, sizeof(port)); + port = htons(30); + memcpy(&m_sendBuffer3[IPV4_SRC_PORT_OFFSET], &port, sizeof(port)); + port = htons(300); + memcpy(&m_sendBuffer3[IPV4_DST_PORT_OFFSET], &port, sizeof(port)); + + return true; + }// ModifyPacktes () +}; +/*---------------------------------------------------------------------------*/ +/* Test005: Destination IP address exact match against broadcast IP address */ +/*---------------------------------------------------------------------------*/ +class IpaFilteringBlockTest025 : public IpaFilteringBlockTestFixture +{ +public: + IpaFilteringBlockTest025() + { + m_name = "IpaFilteringBlockTest025"; + m_description = + "Filtering block test 025 - Filtering Based on Protocol type (TCP/UDP/ICMP) (End-Point specific Filtering Table, Insert all rules in a single commit)\ + 1. Generate and commit three routing tables. \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit three filtering rules: (DST & Mask Match). \ + All UDP traffic goes to routing table 0 \ + All TCP traffic goes to routing table 1 \ + All ICMP traffic goes to routing table 2"; + Register(*this); + } + + + virtual bool AddRules() + { + printf("Entering %s, %s()\n",__FUNCTION__, __FILE__); +// Test Description: +// 1. Generate and commit two routing tables. +// Each table will contain a single "bypass" rule (all data goes to output pipe 0 and 1 (accordingly)) +// 2. Generate and commit two filtering rules. +// All UDP traffic goes to routing table 1 +// All TCP traffic goes to routing table 2 + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + struct ipa_ioc_get_rt_tbl routing_table0,routing_table1,routing_table2; + + if (!CreateThreeIPv4BypassRoutingTables (bypass0,bypass1,bypass2)) + { + printf("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + + printf("CreateThreeBypassRoutingTables completed successfully\n"); + routing_table0.ip = IPA_IP_v4; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + printf("m_routing.GetRoutingTable(&routing_table0=0x%p) Failed.\n",&routing_table0); + return false; + } + routing_table1.ip = IPA_IP_v4; + strlcpy(routing_table1.name, bypass1, sizeof(routing_table1.name)); + if (!m_routing.GetRoutingTable(&routing_table1)) + { + printf("m_routing.GetRoutingTable(&routing_table1=0x%p) Failed.\n",&routing_table1); + return false; + } + + routing_table2.ip = IPA_IP_v4; + strlcpy(routing_table2.name, bypass2, sizeof(routing_table2.name)); + if (!m_routing.GetRoutingTable(&routing_table2)) + { + printf("m_routing.GetRoutingTable(&routing_table2=0x%p) Failed.\n",&routing_table2); + return false; + } + + IPAFilteringTable FilterTable0; + struct ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v4,IPA_CLIENT_TEST_PROD,false,3); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1,flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl=-1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action=IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.rt_tbl_hdl=routing_table0.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_PROTOCOL; + flt_rule_entry.rule.attrib.u.v4.protocol = 17; // Filter only UDP Packets. + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.1 + flt_rule_entry.rule.rt_tbl_hdl=routing_table1.hdl; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.attrib.u.v4.protocol = 6; // Filter only TCP Packets. + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.2 + flt_rule_entry.rule.rt_tbl_hdl=routing_table2.hdl; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.attrib.u.v4.protocol = 1; // Filter only ICMP Packets. + + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(0)->status); + printf("flt rule hdl1=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(1)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(1)->status); + printf("flt rule hdl2=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(2)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(2)->status); + } + printf("Leaving %s, %s()\n",__FUNCTION__, __FILE__); + return true; + }// AddRules() + + virtual bool ModifyPackets() + { + // TODO: Add verification that we access only allocated addresses + m_sendBuffer[IPV4_PROTOCOL_OFFSET] = 0x11;// UDP 0x11 = 17 + m_sendBuffer2[IPV4_PROTOCOL_OFFSET] = 0x06;// TCP 0x06 = 6 + m_sendBuffer3[IPV4_PROTOCOL_OFFSET] = 0x01;// ICMP 0x01 = 1 + return true; + }// ModifyPacktes () +}; + + +/*---------------------------------------------------------------------------*/ +/* Test006: Destination IP address and subnet mask match against LAN subnet */ +/*---------------------------------------------------------------------------*/ +class IpaFilteringBlockTest026 : public IpaFilteringBlockTestFixture +{ +public: + IpaFilteringBlockTest026() + { + m_name = "IpaFilteringBlockTest026"; + m_description = + "Filtering block test 026 - Destination IP address and subnet mask match against LAN subnet (End-Point specific Filtering Table, each rule is added in a Insert using a dedicated single commit)\ + 1. Generate and commit three routing tables. \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit Three filtering rules: (DST & Mask Match). \ + All DST_IP == (127.0.0.1 & 255.0.0.255)traffic goes to routing table 0 \ + All DST_IP == (192.169.1.1 & 255.0.0.255)traffic goes to routing table 1 \ + All DST_IP == (192.169.1.2 & 255.0.0.255)traffic goes to routing table 2"; + Register(*this); + } + + + virtual bool AddRules() + { + printf("Entering %s, %s()\n",__FUNCTION__, __FILE__); + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + struct ipa_ioc_get_rt_tbl routing_table0,routing_table1,routing_table2; + + if (!CreateThreeIPv4BypassRoutingTables (bypass0,bypass1,bypass2)) + { + printf("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + + printf("CreateThreeBypassRoutingTables completed successfully\n"); + routing_table0.ip = IPA_IP_v4; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + printf("m_routing.GetRoutingTable(&routing_table0=0x%p) Failed.\n",&routing_table0); + return false; + } + routing_table1.ip = IPA_IP_v4; + strlcpy(routing_table1.name, bypass1, sizeof(routing_table1.name)); + if (!m_routing.GetRoutingTable(&routing_table1)) + { + printf("m_routing.GetRoutingTable(&routing_table1=0x%p) Failed.\n",&routing_table1); + return false; + } + + routing_table2.ip = IPA_IP_v4; + strlcpy(routing_table2.name, bypass2, sizeof(routing_table2.name)); + if (!m_routing.GetRoutingTable(&routing_table2)) + { + printf("m_routing.GetRoutingTable(&routing_table2=0x%p) Failed.\n",&routing_table2); + return false; + } + + IPAFilteringTable FilterTable0,FilterTable1,FilterTable2; + struct ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v4,IPA_CLIENT_TEST_PROD,false,1); + FilterTable1.Init(IPA_IP_v4,IPA_CLIENT_TEST_PROD,false,1); + FilterTable2.Init(IPA_IP_v4,IPA_CLIENT_TEST_PROD,false,1); + printf("FilterTable*.Init Completed Successfully..\n"); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1,flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl=-1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action=IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.rt_tbl_hdl=routing_table0.hdl; //put here the handle corresponding to Routing Rule 1 + // TODO: Fix this, doesn't match the Rule's Requirements + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; // TODO: Fix this, doesn't match the Rule's Requirements + flt_rule_entry.rule.attrib.u.v4.dst_addr_mask = 0xFF0000FF; // Mask + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0x7F000001; // Filter DST_IP == 127.0.0.1. + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + printf ("%s::Error Adding RuleTable(0) to Filtering, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(0)->status); + } + + // Configuring Filtering Rule No.1 // TODO: Fix this, doesn't match the Rule's Requirements + flt_rule_entry.rule.rt_tbl_hdl=routing_table1.hdl; //put here the handle corresponding to Routing Rule 2 + // TODO: Fix this, doesn't match the Rule's Requirements + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0xC0A80101; // Filter DST_IP == 192.168.1.1. + if ( + ((uint8_t)-1 == FilterTable1.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable1.GetFilteringTable()) + ) + { + printf ("%s::Error Adding RuleTable(1) to Filtering, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable1.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable1.ReadRuleFromTable(0)->status); + } + + // Configuring Filtering Rule No.2 // TODO: Fix this, doesn't match the Rule's Requirements + flt_rule_entry.rule.rt_tbl_hdl=routing_table2.hdl; //put here the handle corresponding to Routing Rule 2 + // TODO: Fix this, doesn't match the Rule's Requirements + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0xC0A80102; // Filter DST_IP == 192.168.1.2. + + if ( + ((uint8_t)-1 == FilterTable2.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable2.GetFilteringTable()) + ) + { + printf ("%s::Error Adding RuleTable(2) to Filtering, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable2.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable2.ReadRuleFromTable(0)->status); + } + printf("Leaving %s, %s()\n",__FUNCTION__, __FILE__); + return true; + }// AddRules() + + virtual bool ModifyPackets() + { + int address; + // TODO: Add verification that we access only allocated addresses + // TODO: Fix this, doesn't match the Rule's Requirements + address = ntohl(0x7F000001);//127.0.0.1 + memcpy(&m_sendBuffer[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + address = ntohl(0xC0A80101);//192.168.1.1 + memcpy(&m_sendBuffer2[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + address = ntohl(0xC0A80102);//192.168.1.2 + memcpy(&m_sendBuffer3[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + + return true; + }// ModifyPacktes () +}; + +/*---------------------------------------------------------------------------*/ +/* Test007: Destination IP address exact match against broadcast IP address */ +/*---------------------------------------------------------------------------*/ +class IpaFilteringBlockTest027 : public IpaFilteringBlockTestFixture +{ +public: + IpaFilteringBlockTest027() + { + m_name = "IpaFilteringBlockTest027"; + m_description = + "Filtering block test 027 - Destination IP address exact match against broadcast IP address (End-Point specific Filtering Table, each rule is added in a Insert using a dedicated single commit) \ + 1. Generate and commit three routing tables. \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit Three filtering rules (MASK = 0xFF..FF). \ + All DST_IP == 127.0.0.1 traffic goes to routing table 0 \ + All DST_IP == 192.169.1.1 traffic goes to routing table 1 \ + All DST_IP == 192.169.1.2 traffic goes to routing table 2"; + Register(*this); + } + + + virtual bool AddRules() + { + printf("Entering %s, %s()\n",__FUNCTION__, __FILE__); + // Test Description: + // 1. Generate and commit three routing tables. + // Each table will contain a single "bypass" rule (all data goes to output pipe 0, 1 and 2(accordingly)) + // 2. Generate and commit three filtering rules (each in different Filtering Table) + // All Filter DST_IP == 127.0.0.1 traffic goes to routing table 1 + // All Filter DST_IP == 192.168.1.1 traffic goes to routing table 2 + // All Filter DST_IP == 192.168.1.2 traffic goes to routing table 3 + + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + struct ipa_ioc_get_rt_tbl routing_table0,routing_table1,routing_table2; + + if (!CreateThreeIPv4BypassRoutingTables (bypass0,bypass1,bypass2)) + { + printf("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + + printf("CreateThreeBypassRoutingTables completed successfully\n"); + routing_table0.ip = IPA_IP_v4; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + printf("m_routing.GetRoutingTable(&routing_table0=0x%p) Failed.\n",&routing_table0); + return false; + } + routing_table1.ip = IPA_IP_v4; + strlcpy(routing_table1.name, bypass1, sizeof(routing_table1.name)); + if (!m_routing.GetRoutingTable(&routing_table1)) + { + printf("m_routing.GetRoutingTable(&routing_table1=0x%p) Failed.\n",&routing_table1); + return false; + } + + routing_table2.ip = IPA_IP_v4; + strlcpy(routing_table2.name, bypass2, sizeof(routing_table2.name)); + if (!m_routing.GetRoutingTable(&routing_table2)) + { + printf("m_routing.GetRoutingTable(&routing_table2=0x%p) Failed.\n",&routing_table2); + return false; + } + + IPAFilteringTable FilterTable0,FilterTable1,FilterTable2; + struct ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v4,IPA_CLIENT_TEST_PROD,false,1); + FilterTable1.Init(IPA_IP_v4,IPA_CLIENT_TEST_PROD,false,1); + FilterTable2.Init(IPA_IP_v4,IPA_CLIENT_TEST_PROD,false,1); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1,flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl=-1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action=IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.rt_tbl_hdl=routing_table0.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; // TODO: Fix this, doesn't match the Rule's Requirements + flt_rule_entry.rule.attrib.u.v4.dst_addr_mask = 0xFFFFFFFF; // Exact Match + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0x7F000001; // Filter DST_IP == 127.0.0.1. + printf ("flt_rule_entry was set successfully, preparing for insertion....\n"); + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + printf ("%s::Error Adding RuleTable(0) to Filtering, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(0)->status); + } + + // Configuring Filtering Rule No.1 + flt_rule_entry.rule.rt_tbl_hdl=routing_table1.hdl; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0xC0A80101; // Filter DST_IP == 192.168.1.1. + if ( + ((uint8_t)-1 == FilterTable1.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable1.GetFilteringTable()) + ) + { + printf ("%s::Error Adding RuleTable(1) to Filtering, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable1.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable1.ReadRuleFromTable(0)->status); + } + + // Configuring Filtering Rule No.2 + flt_rule_entry.rule.rt_tbl_hdl=routing_table2.hdl; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0xC0A80102; // Filter DST_IP == 192.168.1.2. + + if ( + ((uint8_t)-1 == FilterTable2.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable2.GetFilteringTable()) + ) + { + printf ("%s::Error Adding RuleTable(2) to Filtering, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable2.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable2.ReadRuleFromTable(0)->status); + } + printf("Leaving %s, %s()\n",__FUNCTION__, __FILE__); + return true; + }// AddRules() + + virtual bool ModifyPackets() + { + int address; + // TODO: Add verification that we access only allocated addresses + // TODO: Fix this, doesn't match the Rule's Requirements + address = ntohl(0x7F000001);//127.0.0.1 + memcpy(&m_sendBuffer[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + address = ntohl(0xC0A80101);//192.168.1.1 + memcpy(&m_sendBuffer2[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + address = ntohl(0xC0A80102);//192.168.1.2 + memcpy(&m_sendBuffer3[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + + return true; + }// ModifyPacktes () +}; + + + +/*---------------------------------------------------------------------------*/ +/* Test008: Destination UDP port exact match against DHCP port */ +/*---------------------------------------------------------------------------*/ +class IpaFilteringBlockTest028 : public IpaFilteringBlockTestFixture +{ +public: + IpaFilteringBlockTest028() + { + m_name = "IpaFilteringBlockTest028"; + m_description = + "Filtering block test 028 - Destination UDP port exact match against DHCP port (End-Point specific Filtering Table, each rule is added in a Insert using a dedicated single commit)\ + 1. Generate and commit three routing tables. \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit Three filtering rules . \ + All DST_UDP_PORT == 546 (DHCP Client)traffic goes to routing table 0 \ + All DST_UDP_PORT == 547 (DHCP Server) traffic goes to routing table 1 \ + All DST_UDP_PORT == 500 (Non DHCP) traffic goes to routing table 2"; + Register(*this); + } + + + virtual bool AddRules() + { + printf("Entering %s, %s()\n",__FUNCTION__, __FILE__); +// Test Description: +// 1. Generate and commit three routing tables. +// Each table will contain a single "bypass" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) +// 2. Generate and commit Three filtering rules. +// All DEST_IP == 127.0.0.1 traffic goes to routing table 0 +// All DEST_IP == 192.169.1.1 traffic goes to routing table 1 +// Non Matching traffic goes to routing table 3 + + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + struct ipa_ioc_get_rt_tbl routing_table0,routing_table1,routing_table2; + + if (!CreateThreeIPv4BypassRoutingTables (bypass0,bypass1,bypass2)) + { + printf("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + + printf("CreateThreeBypassRoutingTables completed successfully\n"); + routing_table0.ip = IPA_IP_v4; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + printf("m_routing.GetRoutingTable(&routing_table0=0x%p) Failed.\n",&routing_table0); + return false; + } + routing_table1.ip = IPA_IP_v4; + strlcpy(routing_table1.name, bypass1, sizeof(routing_table1.name)); + if (!m_routing.GetRoutingTable(&routing_table1)) + { + printf("m_routing.GetRoutingTable(&routing_table1=0x%p) Failed.\n",&routing_table1); + return false; + } + + routing_table2.ip = IPA_IP_v4; + strlcpy(routing_table2.name, bypass2, sizeof(routing_table2.name)); + if (!m_routing.GetRoutingTable(&routing_table2)) + { + printf("m_routing.GetRoutingTable(&routing_table2=0x%p) Failed.\n",&routing_table2); + return false; + } + + IPAFilteringTable FilterTable0,FilterTable1,FilterTable2; + struct ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v4,IPA_CLIENT_TEST_PROD,false,1); + FilterTable1.Init(IPA_IP_v4,IPA_CLIENT_TEST_PROD,false,1); + FilterTable2.Init(IPA_IP_v4,IPA_CLIENT_TEST_PROD,false,1); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1,flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl=-1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action=IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.rt_tbl_hdl=routing_table0.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_PORT; + flt_rule_entry.rule.attrib.dst_port = 546; // DHCP Client Port No 546 + + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + printf ("%s::Error Adding RuleTable(0) to Filtering, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(0)->status); + } + + // Configuring Filtering Rule No.1 + flt_rule_entry.rule.rt_tbl_hdl=routing_table1.hdl; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.attrib.dst_port = 547; // DHCP Server Port No 547 + if ( + ((uint8_t)-1 == FilterTable1.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable1.GetFilteringTable()) + ) + { + printf ("%s::Error Adding RuleTable(1) to Filtering, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable1.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable1.ReadRuleFromTable(0)->status); + } + + // Configuring Filtering Rule No.2 + flt_rule_entry.rule.rt_tbl_hdl=routing_table2.hdl; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.attrib.dst_port = 500; // Non-DHCP Port + + if ( + ((uint8_t)-1 == FilterTable2.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable2.GetFilteringTable()) + ) + { + printf ("%s::Error Adding RuleTable(2) to Filtering, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable2.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable2.ReadRuleFromTable(0)->status); + } + printf("Leaving %s, %s()\n",__FUNCTION__, __FILE__); + return true; + }// AddRules() + + virtual bool ModifyPackets() + { + unsigned short port; + // TODO: Add verification that we access only allocated addresses + // TODO: Port should be switched to Network Mode. + port = ntohs(546);//DHCP Client Port + memcpy (&m_sendBuffer[IPV4_DST_PORT_OFFSET], &port, sizeof(port)); + port = ntohs(547);//DHCP Server Port + memcpy (&m_sendBuffer2[IPV4_DST_PORT_OFFSET], &port, sizeof(port)); + port = ntohs(500);//Non - DHCP Port + memcpy (&m_sendBuffer3[IPV4_DST_PORT_OFFSET], &port, sizeof(port)); + + return true; + }// ModifyPacktes () +}; + +/*------------------------------------------------------------------------------*/ +/* Test009: Firewall filtering rules based on source and destination port ranges */ +/*------------------------------------------------------------------------------*/ +class IpaFilteringBlockTest029 : public IpaFilteringBlockTestFixture +{ +public: + IpaFilteringBlockTest029() + { + m_name = "IpaFilteringBlockTest029"; + m_description = + "Filtering block test 029 - Firewall filtering rules based on source and destination port ranges (End-Point specific Filtering Table, each rule is added in a Insert using a dedicated single commit)\ + 1. Generate and commit three routing tables. \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit Three filtering rules . \ + All (5 >= SRC_PORT_RANGE >= 15) & (50 >= DST_PORT_RANGE >= 150) traffic goes to routing table 0 \ + All (15 >= SRC_PORT_RANGE >= 25) & (150 >= DST_PORT_RANGE >= 250) traffic goes to routing table 1 \ + All (25 >= SRC_PORT_RANGE >= 35) & (250 >= DST_PORT_RANGE >= 350) traffic goes to routing table 2"; + Register(*this); + } + + + virtual bool AddRules() + { + printf("Entering %s, %s()\n",__FUNCTION__, __FILE__); +// Test Description: +// 1. Generate and commit two routing tables. +// Each table will contain a single "bypass" rule (all data goes to output pipe 0 and 1 (accordingly)) +// 2. Generate and commit two filtering rules. +// All UDP traffic goes to routing table 1 +// All TCP traffic goes to routing table 2 + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + struct ipa_ioc_get_rt_tbl routing_table0,routing_table1,routing_table2; + + if (!CreateThreeIPv4BypassRoutingTables (bypass0,bypass1,bypass2)) + { + printf("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + + printf("CreateThreeBypassRoutingTables completed successfully\n"); + routing_table0.ip = IPA_IP_v4; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + printf("m_routing.GetRoutingTable(&routing_table0=0x%p) Failed.\n",&routing_table0); + return false; + } + routing_table1.ip = IPA_IP_v4; + strlcpy(routing_table1.name, bypass1, sizeof(routing_table1.name)); + if (!m_routing.GetRoutingTable(&routing_table1)) + { + printf("m_routing.GetRoutingTable(&routing_table1=0x%p) Failed.\n",&routing_table1); + return false; + } + + routing_table2.ip = IPA_IP_v4; + strlcpy(routing_table2.name, bypass2, sizeof(routing_table2.name)); + if (!m_routing.GetRoutingTable(&routing_table2)) + { + printf("m_routing.GetRoutingTable(&routing_table2=0x%p) Failed.\n",&routing_table2); + return false; + } + + IPAFilteringTable FilterTable0,FilterTable1,FilterTable2; + struct ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v4,IPA_CLIENT_TEST_PROD,false,1); + FilterTable1.Init(IPA_IP_v4,IPA_CLIENT_TEST_PROD,false,1); + FilterTable2.Init(IPA_IP_v4,IPA_CLIENT_TEST_PROD,false,1); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1,flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl=-1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action=IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.rt_tbl_hdl=routing_table0.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_SRC_PORT_RANGE | IPA_FLT_DST_PORT_RANGE; + //TODO: Fix from here..... + flt_rule_entry.rule.attrib.src_port_lo =5; + flt_rule_entry.rule.attrib.src_port_hi =15; + flt_rule_entry.rule.attrib.dst_port_lo =50; + flt_rule_entry.rule.attrib.dst_port_hi =150; + + printf ("flt_rule_entry was set successfully, preparing for insertion....\n"); + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + printf ("%s::Error Adding RuleTable(0) to Filtering, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(0)->status); + } + + // Configuring Filtering Rule No.1 + flt_rule_entry.rule.rt_tbl_hdl=routing_table1.hdl; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.attrib.src_port_lo = 15; + flt_rule_entry.rule.attrib.src_port_hi = 25; + flt_rule_entry.rule.attrib.dst_port_lo = 150; + flt_rule_entry.rule.attrib.dst_port_hi = 250; + + if ( + ((uint8_t)-1 == FilterTable1.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable1.GetFilteringTable()) + ) + { + printf ("%s::Error Adding RuleTable(1) to Filtering, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable1.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable1.ReadRuleFromTable(0)->status); + } + + // Configuring Filtering Rule No.2 + flt_rule_entry.rule.rt_tbl_hdl=routing_table2.hdl; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.attrib.src_port_lo = 25; + flt_rule_entry.rule.attrib.src_port_hi = 35; + flt_rule_entry.rule.attrib.dst_port_lo = 250; + flt_rule_entry.rule.attrib.dst_port_hi = 350; + + if ( + ((uint8_t)-1 == FilterTable2.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable2.GetFilteringTable()) + ) + { + printf ("%s::Error Adding RuleTable(2) to Filtering, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable2.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable2.ReadRuleFromTable(0)->status); + } + printf("Leaving %s, %s()\n",__FUNCTION__, __FILE__); + return true; + }// AddRules() + + virtual bool ModifyPackets() + { + unsigned short port; + + // TODO: Add verification that we access only allocated addresses + port = htons(10); + memcpy(&m_sendBuffer[IPV4_SRC_PORT_OFFSET], &port, sizeof(port)); + port = htons(100); + memcpy(&m_sendBuffer[IPV4_DST_PORT_OFFSET], &port, sizeof(port)); + port = htons(20); + memcpy(&m_sendBuffer2[IPV4_SRC_PORT_OFFSET], &port, sizeof(port)); + port = htons(200); + memcpy(&m_sendBuffer2[IPV4_DST_PORT_OFFSET], &port, sizeof(port)); + port = htons(30); + memcpy(&m_sendBuffer3[IPV4_SRC_PORT_OFFSET], &port, sizeof(port)); + port = htons(300); + memcpy(&m_sendBuffer3[IPV4_DST_PORT_OFFSET], &port, sizeof(port)); + + return true; + }// ModifyPacktes () +}; +/*---------------------------------------------------------------------------*/ +/* Test010: Destination IP address exact match against broadcast IP address */ +/*---------------------------------------------------------------------------*/ +class IpaFilteringBlockTest030 : public IpaFilteringBlockTestFixture +{ +public: + IpaFilteringBlockTest030() + { + m_name = "IpaFilteringBlockTest030"; + m_description = + "Filtering block test 030 - Filtering Based on Protocol type (TCP/UDP/ICMP) (End-Point specific Filtering Table, each rule is added in a Insert using a dedicated single commit)\ + 1. Generate and commit three routing tables. \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit three filtering rules: (DST & Mask Match). \ + All UDP traffic goes to routing table 0 \ + All TCP traffic goes to routing table 1 \ + All ICMP traffic goes to routing table 2"; + Register(*this); + } + + + virtual bool AddRules() + { + printf("Entering %s, %s()\n",__FUNCTION__, __FILE__); +// Test Description: +// 1. Generate and commit two routing tables. +// Each table will contain a single "bypass" rule (all data goes to output pipe 0 and 1 (accordingly)) +// 2. Generate and commit two filtering rules. +// All UDP traffic goes to routing table 1 +// All TCP traffic goes to routing table 2 + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + struct ipa_ioc_get_rt_tbl routing_table0,routing_table1,routing_table2; + + if (!CreateThreeIPv4BypassRoutingTables (bypass0,bypass1,bypass2)) + { + printf("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + + printf("CreateThreeBypassRoutingTables completed successfully\n"); + routing_table0.ip = IPA_IP_v4; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + printf("m_routing.GetRoutingTable(&routing_table0=0x%p) Failed.\n",&routing_table0); + return false; + } + routing_table1.ip = IPA_IP_v4; + strlcpy(routing_table1.name, bypass1, sizeof(routing_table1.name)); + if (!m_routing.GetRoutingTable(&routing_table1)) + { + printf("m_routing.GetRoutingTable(&routing_table1=0x%p) Failed.\n",&routing_table1); + return false; + } + + routing_table2.ip = IPA_IP_v4; + strlcpy(routing_table2.name, bypass2, sizeof(routing_table2.name)); + if (!m_routing.GetRoutingTable(&routing_table2)) + { + printf("m_routing.GetRoutingTable(&routing_table2=0x%p) Failed.\n",&routing_table2); + return false; + } + + IPAFilteringTable FilterTable0,FilterTable1,FilterTable2; + struct ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v4,IPA_CLIENT_TEST_PROD,false,1); + FilterTable1.Init(IPA_IP_v4,IPA_CLIENT_TEST_PROD,false,1); + FilterTable2.Init(IPA_IP_v4,IPA_CLIENT_TEST_PROD,false,1); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1,flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl=-1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action=IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.rt_tbl_hdl=routing_table0.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_PROTOCOL; + flt_rule_entry.rule.attrib.u.v4.protocol = 17; // Filter only UDP Packets. + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + printf ("%s::Error Adding RuleTable(0) to Filtering, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(0)->status); + } + + // Configuring Filtering Rule No.1 + flt_rule_entry.rule.rt_tbl_hdl=routing_table1.hdl; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.attrib.u.v4.protocol = 6; // Filter only TCP Packets. + if ( + ((uint8_t)-1 == FilterTable1.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable1.GetFilteringTable()) + ) + { + printf ("%s::Error Adding RuleTable(1) to Filtering, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable1.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable1.ReadRuleFromTable(0)->status); + } + + // Configuring Filtering Rule No.2 + flt_rule_entry.rule.rt_tbl_hdl=routing_table2.hdl; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.attrib.u.v4.protocol = 1; // Filter only ICMP Packets. + + if ( + ((uint8_t)-1 == FilterTable2.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable2.GetFilteringTable()) + ) + { + printf ("%s::Error Adding RuleTable(2) to Filtering, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable2.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable2.ReadRuleFromTable(0)->status); + } + printf("Leaving %s, %s()\n",__FUNCTION__, __FILE__); + return true; + }// AddRules() + + virtual bool ModifyPackets() + { + // TODO: Add verification that we access only allocated addresses + m_sendBuffer[IPV4_PROTOCOL_OFFSET] = 0x11;// UDP 0x11 = 17 + m_sendBuffer2[IPV4_PROTOCOL_OFFSET] = 0x06;// TCP 0x06 = 6 + m_sendBuffer3[IPV4_PROTOCOL_OFFSET] = 0x01;// ICMP 0x01 = 1 + return true; + }// ModifyPacktes () +}; +/*-------------------------------------------------------------------------------------*/ +/* Test031: Filtering Based on fragment extension, End-Point specific Filtering Table */ +/*-------------------------------------------------------------------------------------*/ +class IpaFilteringBlockTest031 : public IpaFilteringBlockTestFixture +{ +public: + IpaFilteringBlockTest031() + { + m_name = "IpaFilteringBlockTest031"; + m_description = + "Filtering block test 031 - Filtering Based on fragment extension(End-Point specific Filtering Table, Insert all rules in a single commit)\ + 1. Generate and commit three routing tables. \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit 2 filtering rules: \ + All fragmented packets goes to routing table 0: \ + Packets with MF flag set & \ + Packets with MF flag set to zero and fragment offset field nonzero \ + All other packets(non fragmented) goes to routing table 1: \ + Packets with MF flag set to zero and fragment offset field zero goes to routing table 1"; + Register(*this); + } + + virtual bool AddRules() + { + printf("Entering %s, %s()\n",__FUNCTION__, __FILE__); + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + struct ipa_ioc_get_rt_tbl routing_table0,routing_table1,routing_table2; + + if (!CreateThreeIPv4BypassRoutingTables(bypass0,bypass1,bypass2)) + { + printf("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + + printf("CreateThreeBypassRoutingTables completed successfully\n"); + routing_table0.ip = IPA_IP_v4; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + printf("m_routing.GetRoutingTable(&routing_table0=0x%p) Failed.\n",&routing_table0); + return false; + } + routing_table1.ip = IPA_IP_v4; + strlcpy(routing_table1.name, bypass1, sizeof(routing_table1.name)); + if (!m_routing.GetRoutingTable(&routing_table1)) + { + printf("m_routing.GetRoutingTable(&routing_table1=0x%p) Failed.\n",&routing_table1); + return false; + } + + routing_table2.ip = IPA_IP_v4; + strlcpy(routing_table2.name, bypass2, sizeof(routing_table2.name)); + if (!m_routing.GetRoutingTable(&routing_table2)) + { + printf("m_routing.GetRoutingTable(&routing_table2=0x%p) Failed.\n",&routing_table2); + return false; + } + + IPAFilteringTable FilterTable0; + struct ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v4,IPA_CLIENT_TEST_PROD,false,3); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1,flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl=-1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action=IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.rt_tbl_hdl=routing_table0.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_FRAGMENT; + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.1 + flt_rule_entry.rule.rt_tbl_hdl=routing_table1.hdl; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0xaabbccdd; + flt_rule_entry.rule.attrib.u.v4.dst_addr_mask = 0x00000000;// All Packets will get a "Hit" + + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(0)->status); + printf("flt rule hdl1=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(1)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(1)->status); + } + printf("Leaving %s, %s()\n",__FUNCTION__, __FILE__); + return true; + }// AddRules() + + virtual bool ModifyPackets() + { + m_sendBuffer[IPV4_FRAGMENT_FLAGS_OFFSET] = 0x20;//MF=1 + m_sendBuffer[IPV4_FRAGMENT_FLAGS_OFFSET+1] = 0x0;//MF=1 + m_sendBuffer2[IPV4_FRAGMENT_FLAGS_OFFSET] = 0x0;//MF=0 && frag_off =126 + m_sendBuffer2[IPV4_FRAGMENT_FLAGS_OFFSET+1] = 0x7E;//MF=0 && frag_off =126 + m_sendBuffer3[IPV4_FRAGMENT_FLAGS_OFFSET] = 0x0;// MF=0 && frag_off =0 + m_sendBuffer3[IPV4_FRAGMENT_FLAGS_OFFSET+1] = 0x0;// MF=0 && frag_off =0 + return true; + }// ModifyPacktes () + + virtual bool ReceivePacketsAndCompare() + { + size_t receivedSize = 0; + size_t receivedSize2 = 0; + size_t receivedSize3 = 0; + bool isSuccess = true; + + // Receive results + Byte *rxBuff1 = new Byte[0x400]; + Byte *rxBuff2 = new Byte[0x400]; + Byte *rxBuff3 = new Byte[0x400]; + + if (NULL == rxBuff1 || NULL == rxBuff2 || NULL == rxBuff3) + { + printf("Memory allocation error.\n"); + return false; + } + + receivedSize = m_consumer.ReceiveData(rxBuff1, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize, m_consumer.m_fromChannelName.c_str()); + + receivedSize2 = m_consumer.ReceiveData(rxBuff2, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize2, m_consumer.m_fromChannelName.c_str()); + + receivedSize3 = m_consumer2.ReceiveData(rxBuff3, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize3, m_consumer2.m_fromChannelName.c_str()); + + // Compare results + if (!CompareResultVsGolden(m_sendBuffer, m_sendSize, rxBuff1, receivedSize)) + { + printf("Comparison of Buffer0 Failed!\n"); + isSuccess = false; + } + + size_t recievedBufferSize = receivedSize * 3; + size_t sentBufferSize = m_sendSize * 3; + char *recievedBuffer = new char[recievedBufferSize]; + char *sentBuffer = new char[sentBufferSize]; + + memset(recievedBuffer, 0, recievedBufferSize); + memset(sentBuffer, 0, sentBufferSize); + + print_packets(receivedSize, m_sendSize, recievedBufferSize - 1, sentBufferSize - 1, rxBuff1, m_sendBuffer, recievedBuffer, sentBuffer); + recievedBuffer[0] = '\0'; + print_packets(receivedSize2, m_sendSize2, recievedBufferSize - 1, sentBufferSize - 1, rxBuff2, m_sendBuffer2, recievedBuffer, sentBuffer); + recievedBuffer[0] = '\0'; + print_packets(receivedSize3, m_sendSize3, recievedBufferSize - 1, sentBufferSize - 1, rxBuff3, m_sendBuffer3, recievedBuffer, sentBuffer); + + isSuccess &= CompareResultVsGolden(m_sendBuffer2, m_sendSize2, rxBuff2, receivedSize2); + isSuccess &= CompareResultVsGolden(m_sendBuffer3, m_sendSize3, rxBuff3, receivedSize3); + + delete[] recievedBuffer; + delete[] sentBuffer; + + delete[] rxBuff1; + delete[] rxBuff2; + delete[] rxBuff3; + + return isSuccess; + } +}; + +/*---------------------------------------------------------------------------------------------*/ +/* Test050: Destination IPv6 address and Subnet Mask exact match against broadcast IP address */ +/*---------------------------------------------------------------------------------------------*/ +class IpaFilteringBlockTest050 : public IpaFilteringBlockTestFixture +{ +public: + IpaFilteringBlockTest050() + { + m_name = "IpaFilteringBlockTest050"; + m_description = + "Filtering block test 050 - Destination IPv6 address and Mask exact match against broadcast IP address (Global Filtering Table, Insert all rules in a single commit)\ + 1. Generate and commit three routing tables. \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit three filtering rules: (DST & Mask Match). \ + All DST_IPv6 == 0x...AA traffic goes to routing table 1 \ + All DST_IPv6 == 0x...BB traffic goes to routing table 2 \ + All DST_IPv6 == 0x...CC traffic goes to routing table 3"; + m_IpaIPType = IPA_IP_v6; + m_maxIPAHwType = IPA_HW_v2_6L; + Register(*this); + } + + + virtual bool AddRules() + { + printf("Entering %s, %s()\n",__FUNCTION__, __FILE__); + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + struct ipa_ioc_get_rt_tbl routing_table0,routing_table1,routing_table2; + + if (!CreateThreeIPv6BypassRoutingTables (bypass0,bypass1,bypass2)) + { + printf("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + + printf("CreateThreeBypassRoutingTables completed successfully\n"); + routing_table0.ip = IPA_IP_v6; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + printf("m_routing.GetRoutingTable(&routing_table0=0x%p) Failed.\n",&routing_table0); + return false; + } + routing_table1.ip = IPA_IP_v6; + strlcpy(routing_table1.name, bypass1, sizeof(routing_table1.name)); + if (!m_routing.GetRoutingTable(&routing_table1)) + { + printf("m_routing.GetRoutingTable(&routing_table1=0x%p) Failed.\n",&routing_table1); + return false; + } + + routing_table2.ip = IPA_IP_v6; + strlcpy(routing_table2.name, bypass2, sizeof(routing_table2.name)); + if (!m_routing.GetRoutingTable(&routing_table2)) + { + printf("m_routing.GetRoutingTable(&routing_table2=0x%p) Failed.\n",&routing_table2); + return false; + } + + IPAFilteringTable FilterTable0; + struct ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v6,IPA_CLIENT_TEST_PROD,true,3); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1,flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl=-1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action=IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.rt_tbl_hdl=routing_table0.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; // TODO: Fix this, doesn't match the Rule's Requirements + + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[0] = 0xFFFFFFFF;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[1] = 0xFFFFFFFF;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[2] = 0x00000000;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[3] = 0x000000FF;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr[0] = 0XFF020000; // Filter DST_IP + flt_rule_entry.rule.attrib.u.v6.dst_addr[1] = 0x00000000; + flt_rule_entry.rule.attrib.u.v6.dst_addr[2] = 0x11223344; + flt_rule_entry.rule.attrib.u.v6.dst_addr[3] = 0X556677AA; + + printf ("flt_rule_entry was set successfully, preparing for insertion....\n"); + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + printf ("%s::Error Adding RuleTable(0) to Filtering, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(0)->status); + } + + // Configuring Filtering Rule No.1 + flt_rule_entry.rule.rt_tbl_hdl=routing_table1.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.u.v6.dst_addr[3] = 0X556677BB; + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + printf ("%s::Error Adding RuleTable(1) to Filtering, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(1)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(1)->status); + } + + // Configuring Filtering Rule No.2 + flt_rule_entry.rule.rt_tbl_hdl=routing_table2.hdl; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.attrib.u.v6.dst_addr[3] = 0X556677CC; + + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + printf ("%s::Error Adding RuleTable(2) to Filtering, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(2)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(2)->status); + } + printf("Leaving %s, %s()\n",__FUNCTION__, __FILE__); + return true; + }// AddRules() + + virtual bool ModifyPackets() + { + // TODO: Add verification that we access only allocated addresses + // TODO: Fix this, doesn't match the Rule's Requirements + m_sendBuffer[DST_ADDR_LSB_OFFSET_IPV6] = 0xAA; + m_sendBuffer2[DST_ADDR_LSB_OFFSET_IPV6] = 0xBB; + m_sendBuffer3[DST_ADDR_LSB_OFFSET_IPV6] = 0xCC; + return true; + }// ModifyPacktes () +}; + + +/*---------------------------------------------------------------------------------------------*/ +/* Test051: Destination IPv6 address and Subnet Mask exact match against broadcast IP address */ +/*---------------------------------------------------------------------------------------------*/ +class IpaFilteringBlockTest051 : public IpaFilteringBlockTestFixture +{ +public: + IpaFilteringBlockTest051() + { + m_name = "IpaFilteringBlockTest051"; + m_description = + "Filtering block test 051 - Destination IPv6 address and Mask exact match against broadcast IP address (End-Point specific Filtering Table, Insert all rules in a single commit)\ + 1. Generate and commit three routing tables. \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit three filtering rules: (DST & Mask Match). \ + All DST_IPv6 == 0x...AA traffic goes to routing table 1 \ + All DST_IPv6 == 0x...BB traffic goes to routing table 2 \ + All DST_IPv6 == 0x...CC traffic goes to routing table 3"; + m_IpaIPType = IPA_IP_v6; + Register(*this); + } + + + virtual bool AddRules() + { + printf("Entering %s, %s()\n",__FUNCTION__, __FILE__); + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + struct ipa_ioc_get_rt_tbl routing_table0,routing_table1,routing_table2; + + if (!CreateThreeIPv6BypassRoutingTables (bypass0,bypass1,bypass2)) + { + printf("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + + printf("CreateThreeBypassRoutingTables completed successfully\n"); + routing_table0.ip = IPA_IP_v6; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + printf("m_routing.GetRoutingTable(&routing_table0=0x%p) Failed.\n",&routing_table0); + return false; + } + routing_table1.ip = IPA_IP_v6; + strlcpy(routing_table1.name, bypass1, sizeof(routing_table1.name)); + if (!m_routing.GetRoutingTable(&routing_table1)) + { + printf("m_routing.GetRoutingTable(&routing_table1=0x%p) Failed.\n",&routing_table1); + return false; + } + + routing_table2.ip = IPA_IP_v6; + strlcpy(routing_table2.name, bypass2, sizeof(routing_table2.name)); + if (!m_routing.GetRoutingTable(&routing_table2)) + { + printf("m_routing.GetRoutingTable(&routing_table2=0x%p) Failed.\n",&routing_table2); + return false; + } + + IPAFilteringTable FilterTable0; + struct ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v6,IPA_CLIENT_TEST_PROD,false,3); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1,flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl=-1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action=IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.rt_tbl_hdl=routing_table0.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; // TODO: Fix this, doesn't match the Rule's Requirements + + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[0] = 0xFFFFFFFF;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[1] = 0xFFFFFFFF;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[2] = 0x00000000;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[3] = 0x000000FF;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr[0] = 0XFF020000; // Filter DST_IP + flt_rule_entry.rule.attrib.u.v6.dst_addr[1] = 0x00000000; + flt_rule_entry.rule.attrib.u.v6.dst_addr[2] = 0x11223344; + flt_rule_entry.rule.attrib.u.v6.dst_addr[3] = 0X556677AA; + + printf ("flt_rule_entry was set successfully, preparing for insertion....\n"); + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } + // Configuring Filtering Rule No.1 + flt_rule_entry.rule.rt_tbl_hdl=routing_table1.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.u.v6.dst_addr[3] = 0X556677BB; + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.2 + flt_rule_entry.rule.rt_tbl_hdl=routing_table2.hdl; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.attrib.u.v6.dst_addr[3] = 0X556677CC; + + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(0)->status); + printf("flt rule hdl1=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(1)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(1)->status); + printf("flt rule hdl2=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(2)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(2)->status); + } + printf("Leaving %s, %s()\n",__FUNCTION__, __FILE__); + return true; + }// AddRules() + + virtual bool ModifyPackets() + { + // TODO: Add verification that we access only allocated addresses + // TODO: Fix this, doesn't match the Rule's Requirements + m_sendBuffer[DST_ADDR_LSB_OFFSET_IPV6] = 0xAA; + m_sendBuffer2[DST_ADDR_LSB_OFFSET_IPV6] = 0xBB; + m_sendBuffer3[DST_ADDR_LSB_OFFSET_IPV6] = 0xCC; + return true; + }// ModifyPacktes () +}; + +/*---------------------------------------------------------------------------*/ +/* Test052: IPv6 Filtering Based on Protocol type (TCP/UDP/ICMP) */ +/*---------------------------------------------------------------------------*/ +class IpaFilteringBlockTest052 : public IpaFilteringBlockTestFixture +{ +public: + IpaFilteringBlockTest052() + { + m_name = "IpaFilteringBlockTest052"; + m_description = + "Filtering block test 052 - Filtering Based on Protocol type (TCP/UDP/ICMP) (Global Filtering Table, each rule is added in a Insert using a dedicated single commit)\ + 1. Generate and commit three routing tables. \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit three filtering rules: (DST & Mask Match). \ + All UDP traffic goes to routing table 0 \ + All TCP traffic goes to routing table 1 \ + All ICMP traffic goes to routing table 2"; + m_IpaIPType = IPA_IP_v6; + m_extHdrType = FRAGMENT; + m_minIPAHwType = IPA_HW_v2_5; + m_maxIPAHwType = IPA_HW_v2_6L; + Register(*this); + } + + + virtual bool AddRules() + { + printf("Entering %s, %s()\n",__FUNCTION__, __FILE__); + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + struct ipa_ioc_get_rt_tbl routing_table0,routing_table1,routing_table2; + + if (!CreateThreeIPv6BypassRoutingTables (bypass0,bypass1,bypass2)) + { + printf("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + + printf("CreateThreeBypassRoutingTables completed successfully\n"); + routing_table0.ip = IPA_IP_v6; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + printf("m_routing.GetRoutingTable(&routing_table0=0x%p) Failed.\n",&routing_table0); + return false; + } + routing_table1.ip = IPA_IP_v6; + strlcpy(routing_table1.name, bypass1, sizeof(routing_table1.name)); + if (!m_routing.GetRoutingTable(&routing_table1)) + { + printf("m_routing.GetRoutingTable(&routing_table1=0x%p) Failed.\n",&routing_table1); + return false; + } + + routing_table2.ip = IPA_IP_v6; + strlcpy(routing_table2.name, bypass2, sizeof(routing_table2.name)); + if (!m_routing.GetRoutingTable(&routing_table2)) + { + printf("m_routing.GetRoutingTable(&routing_table2=0x%p) Failed.\n",&routing_table2); + return false; + } + + IPAFilteringTable FilterTable0,FilterTable1,FilterTable2; + struct ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v6,IPA_CLIENT_TEST_PROD,true,1); + FilterTable1.Init(IPA_IP_v6,IPA_CLIENT_TEST_PROD,true,1); + FilterTable2.Init(IPA_IP_v6,IPA_CLIENT_TEST_PROD,true,1); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1,flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl=-1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action=IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.rt_tbl_hdl=routing_table0.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_NEXT_HDR; + flt_rule_entry.rule.attrib.u.v6.next_hdr = 17; // Filter only UDP Packets. + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + printf ("%s::Error Adding RuleTable(0) to Filtering, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(0)->status); + } + + // Configuring Filtering Rule No.1 + flt_rule_entry.rule.rt_tbl_hdl=routing_table1.hdl; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.attrib.u.v6.next_hdr = 6; // Filter only TCP Packets. + if ( + ((uint8_t)-1 == FilterTable1.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable1.GetFilteringTable()) + ) + { + printf ("%s::Error Adding RuleTable(1) to Filtering, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable1.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable1.ReadRuleFromTable(0)->status); + } + + // Configuring Filtering Rule No.2 + flt_rule_entry.rule.rt_tbl_hdl=routing_table2.hdl; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.attrib.u.v6.next_hdr = 1; // Filter only ICMP Packets. + + if ( + ((uint8_t)-1 == FilterTable2.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable2.GetFilteringTable()) + ) + { + printf ("%s::Error Adding RuleTable(2) to Filtering, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable2.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable2.ReadRuleFromTable(0)->status); + } + printf("Leaving %s, %s()\n",__FUNCTION__, __FILE__); + return true; + }// AddRules() + + virtual bool ModifyPackets() + { + m_sendBuffer[IPV6_NEXT_HDR_OFFSET] = 0x2C;//FRAGMENT HEADER(44) + m_sendBuffer[IPV6_FRAGMENT_NEXT_HDR_OFFSET] = 0x11;// UDP 0x11 = 17 + m_sendBuffer2[IPV6_FRAGMENT_NEXT_HDR_OFFSET] = 0x06;// TCP 0x06 = 6 + m_sendBuffer3[IPV6_FRAGMENT_NEXT_HDR_OFFSET] = 0x01;// ICMP 0x01 = 1 + return true; + }// ModifyPacktes () +}; +/*-------------------------------------------------------------------------------------*/ +/* Test053: Filtering Based on fragment extension, End-Point specific Filtering Table */ +/*-------------------------------------------------------------------------------------*/ +class IpaFilteringBlockTest053 : public IpaFilteringBlockTestFixture +{ +public: + IpaFilteringBlockTest053() + { + m_name = "IpaFilteringBlockTest053"; + m_description = + "Filtering block test 053 - Filtering Based on fragment extension(End-Point specific Filtering Table, Insert all rules in a single commit)\ + 1. Generate and commit three routing tables. \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit 2 filtering rules: \ + All fragmented packets goes to routing table 0: \ + Packets with MF flag set & \ + Packets with MF flag set to zero and fragment offset field nonzero \ + All other packets(non fragmented) goes to routing table 1: \ + Packets with MF flag set to zero and fragment offset field zero goes to routing table 1"; + m_IpaIPType = IPA_IP_v6; + m_extHdrType = FRAGMENT; + m_minIPAHwType = IPA_HW_v2_5; + Register(*this); + } + + virtual bool AddRules() + { + printf("Entering %s, %s()\n",__FUNCTION__, __FILE__); + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + struct ipa_ioc_get_rt_tbl routing_table0,routing_table1,routing_table2; + + if (!CreateThreeIPv6BypassRoutingTables(bypass0,bypass1,bypass2)) + { + printf("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + + printf("CreateThreeBypassRoutingTables completed successfully\n"); + routing_table0.ip = IPA_IP_v6; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + printf("m_routing.GetRoutingTable(&routing_table0=0x%p) Failed.\n",&routing_table0); + return false; + } + routing_table1.ip = IPA_IP_v6; + strlcpy(routing_table1.name, bypass1, sizeof(routing_table1.name)); + if (!m_routing.GetRoutingTable(&routing_table1)) + { + printf("m_routing.GetRoutingTable(&routing_table1=0x%p) Failed.\n",&routing_table1); + return false; + } + + routing_table2.ip = IPA_IP_v6; + strlcpy(routing_table2.name, bypass2, sizeof(routing_table2.name)); + if (!m_routing.GetRoutingTable(&routing_table2)) + { + printf("m_routing.GetRoutingTable(&routing_table2=0x%p) Failed.\n",&routing_table2); + return false; + } + + IPAFilteringTable FilterTable0; + struct ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v6,IPA_CLIENT_TEST_PROD,false,2); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1,flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl=-1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action=IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.rt_tbl_hdl=routing_table0.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_FRAGMENT; + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.1 + flt_rule_entry.rule.rt_tbl_hdl=routing_table1.hdl; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + flt_rule_entry.rule.attrib.u.v6.dst_addr[0] = 0xaabbccdd; + flt_rule_entry.rule.attrib.u.v6.dst_addr[1] = 0xeeff0011; + flt_rule_entry.rule.attrib.u.v6.dst_addr[2] = 0x22334455; + flt_rule_entry.rule.attrib.u.v6.dst_addr[3] = 0x66778899; + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[0] = 0x00000000;// All Packets will get a "Hit" + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[1] = 0x00000000; + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[2] = 0x00000000; + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[3] = 0x00000000; + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(0)->status); + printf("flt rule hdl1=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(1)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(1)->status); + } + printf("Leaving %s, %s()\n",__FUNCTION__, __FILE__); + return true; + }// AddRules() + + virtual bool ModifyPackets() + { + m_sendBuffer[IPV6_NEXT_HDR_OFFSET] = 0x2C;//FRAGMENT HEADER(44) + m_sendBuffer[IPV6_FRAGMENT_FLAGS_OFFSET] = 0x00;//MF=1 + m_sendBuffer[IPV6_FRAGMENT_FLAGS_OFFSET+1] = 0x1;//MF=1 + m_sendBuffer2[IPV6_FRAGMENT_FLAGS_OFFSET] = 0x3;//MF=0 && frag_off =126 + m_sendBuffer2[IPV6_FRAGMENT_FLAGS_OFFSET+1] = 0xF0;//MF=0 && frag_off =126 + m_sendBuffer3[IPV6_FRAGMENT_FLAGS_OFFSET] = 0x0;// MF=0 && frag_off =0 + m_sendBuffer3[IPV6_FRAGMENT_FLAGS_OFFSET+1] = 0x0;// MF=0 && frag_off =0 + return true; + }// ModifyPacktes () + + virtual bool ReceivePacketsAndCompare() + { + size_t receivedSize = 0; + size_t receivedSize2 = 0; + size_t receivedSize3 = 0; + bool isSuccess = true; + + // Receive results + Byte *rxBuff1 = new Byte[0x400]; + Byte *rxBuff2 = new Byte[0x400]; + Byte *rxBuff3 = new Byte[0x400]; + + if (NULL == rxBuff1 || NULL == rxBuff2 || NULL == rxBuff3) + { + printf("Memory allocation error.\n"); + return false; + } + + receivedSize = m_consumer.ReceiveData(rxBuff1, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize, m_consumer.m_fromChannelName.c_str()); + + receivedSize2 = m_consumer.ReceiveData(rxBuff2, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize2, m_consumer.m_fromChannelName.c_str()); + + receivedSize3 = m_consumer2.ReceiveData(rxBuff3, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize3, m_consumer2.m_fromChannelName.c_str()); + + // Compare results + if (!CompareResultVsGolden(m_sendBuffer, m_sendSize, rxBuff1, receivedSize)) + { + printf("Comparison of Buffer0 Failed!\n"); + isSuccess = false; + } + + size_t recievedBufferSize = receivedSize * 3; + size_t sentBufferSize = m_sendSize * 3; + char *recievedBuffer = new char[recievedBufferSize]; + char *sentBuffer = new char[sentBufferSize]; + + memset(recievedBuffer, 0, recievedBufferSize); + memset(sentBuffer, 0, sentBufferSize); + + print_packets(receivedSize, m_sendSize, recievedBufferSize - 1, sentBufferSize - 1, rxBuff1, m_sendBuffer, recievedBuffer, sentBuffer); + recievedBuffer[0] = '\0'; + print_packets(receivedSize2, m_sendSize2, recievedBufferSize - 1, sentBufferSize - 1, rxBuff2, m_sendBuffer2, recievedBuffer, sentBuffer); + recievedBuffer[0] = '\0'; + print_packets(receivedSize3, m_sendSize3, recievedBufferSize - 1, sentBufferSize - 1, rxBuff3, m_sendBuffer3, recievedBuffer, sentBuffer); + + isSuccess &= CompareResultVsGolden(m_sendBuffer2, m_sendSize2, rxBuff2, receivedSize2); + isSuccess &= CompareResultVsGolden(m_sendBuffer3, m_sendSize3, rxBuff3, receivedSize3); + + delete[] recievedBuffer; + delete[] sentBuffer; + + delete[] rxBuff1; + delete[] rxBuff2; + delete[] rxBuff3; + + return isSuccess; + } +}; + +/*----------------------------------------------------------------------------------------------*/ +/* Test054: IPV6 filtering based on based on source and destination port */ +/*----------------------------------------------------------------------------------------------*/ +class IpaFilteringBlockTest054 : public IpaFilteringBlockTestFixture +{ +public: + IpaFilteringBlockTest054() + { + m_name = "IpaFilteringBlockTest054"; + m_description = + "Filtering block test 054 - IPV6 filtering rules based on source and destination port (End-Point specific Filtering Table, Insert all rules in a single commit)\ + 1. Generate and commit three routing tables. \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit three filtering rules:\ + All (SRC_PORT = 1000) traffic goes to routing table 0 \ + All (DST_PORT = 100) traffic goes to routing table 1 \ + All (5 >= SRC_PORT_RANGE >= 15) traffic goes to routing table 2"; + m_IpaIPType = IPA_IP_v6; + m_minIPAHwType = IPA_HW_v2_5; + Register(*this); + } + + + virtual bool AddRules() + { + printf("Entering %s, %s()\n",__FUNCTION__, __FILE__); + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + struct ipa_ioc_get_rt_tbl routing_table0,routing_table1,routing_table2; + + if (!CreateThreeIPv6BypassRoutingTables (bypass0,bypass1,bypass2)) + { + printf("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + + printf("CreateThreeBypassRoutingTables completed successfully\n"); + routing_table0.ip = IPA_IP_v6; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + printf("m_routing.GetRoutingTable(&routing_table0=0x%p) Failed.\n",&routing_table0); + return false; + } + routing_table1.ip = IPA_IP_v6; + strlcpy(routing_table1.name, bypass1, sizeof(routing_table1.name)); + if (!m_routing.GetRoutingTable(&routing_table1)) + { + printf("m_routing.GetRoutingTable(&routing_table1=0x%p) Failed.\n",&routing_table1); + return false; + } + + routing_table2.ip = IPA_IP_v6; + strlcpy(routing_table2.name, bypass2, sizeof(routing_table2.name)); + if (!m_routing.GetRoutingTable(&routing_table2)) + { + printf("m_routing.GetRoutingTable(&routing_table2=0x%p) Failed.\n",&routing_table2); + return false; + } + + IPAFilteringTable FilterTable0; + struct ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v6,IPA_CLIENT_TEST_PROD,false,3); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1,flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl=-1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action=IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.rt_tbl_hdl=routing_table0.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_SRC_PORT; + flt_rule_entry.rule.attrib.src_port = 1000; + + printf ("flt_rule_entry was set successfully, preparing for insertion....\n"); + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.1 + flt_rule_entry.rule.rt_tbl_hdl=routing_table1.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_PORT; + flt_rule_entry.rule.attrib.dst_port = 100; + + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.2 + flt_rule_entry.rule.rt_tbl_hdl=routing_table2.hdl; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_SRC_PORT_RANGE; + flt_rule_entry.rule.attrib.src_port_lo = 5; + flt_rule_entry.rule.attrib.src_port_hi = 15; + + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + printf ("%s::Error Adding RuleTable(2) to Filtering, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(0)->status); + printf("flt rule hdl1=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(1)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(1)->status); + printf("flt rule hdl2=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(2)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(2)->status); + } + printf("Leaving %s, %s()\n",__FUNCTION__, __FILE__); + return true; + }// AddRules() + + virtual bool ModifyPackets() + { + unsigned short port; + + port = htons(1000); + memcpy(&m_sendBuffer[IPV6_SRC_PORT_OFFSET], &port, sizeof(port)); + port = htons(100); + memcpy(&m_sendBuffer2[IPV6_DST_PORT_OFFSET], &port, sizeof(port)); + port = htons(10); + memcpy(&m_sendBuffer3[IPV6_SRC_PORT_OFFSET], &port, sizeof(port)); + + return true; + }// ModifyPacktes () +}; + +/*----------------------------------------------------------------------------------------------*/ +/* Test060: IPV4 filtering test, non hashed priority higher than hashed priority */ +/*----------------------------------------------------------------------------------------------*/ +class IpaFilteringBlockTest060 : public IpaFilteringBlockTestFixture +{ +public: + IpaFilteringBlockTest060() + { + m_name = "IpaFilteringBlockTest060"; + m_description = + "Filtering block test 060 - Rules prioritization hashable vs non-hashable rule, both rules match the same packet but non hashable has higher priority\ + 1. Generate and commit three routing tables. \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit three filtering rules: (DST & Mask Match). \ + All DST_IP == (127.0.0.1 & 255.0.0.255)traffic goes to routing table 0 - non hashable\ + All DST_IP == (127.0.0.1 & 255.0.0.255)traffic goes to routing table 1 - hashable\ + All DST_IP == (192.169.1.2 & 255.0.0.255)traffic goes to routing table 2 - don't care for this specific test"; + m_minIPAHwType = IPA_HW_v3_0; + Register(*this); + + } + + virtual bool AddRules() + { + printf("Entering %s, %s()\n",__FUNCTION__, __FILE__); + + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + struct ipa_ioc_get_rt_tbl routing_table0,routing_table1,routing_table2; + + if (!CreateThreeIPv4BypassRoutingTables (bypass0,bypass1,bypass2)) + { + printf("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + + printf("CreateThreeBypassRoutingTables completed successfully\n"); + routing_table0.ip = IPA_IP_v4; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + printf("m_routing.GetRoutingTable(&routing_table0=0x%p) Failed.\n",&routing_table0); + return false; + } + printf("route table %s has the handle %u\n", bypass0, routing_table0.hdl); + + routing_table1.ip = IPA_IP_v4; + strlcpy(routing_table1.name, bypass1, sizeof(routing_table1.name)); + if (!m_routing.GetRoutingTable(&routing_table1)) + { + printf("m_routing.GetRoutingTable(&routing_table1=0x%p) Failed.\n",&routing_table1); + return false; + } + printf("route table %s has the handle %u\n", bypass1, routing_table1.hdl); + + routing_table2.ip = IPA_IP_v4; + strlcpy(routing_table2.name, bypass2, sizeof(routing_table2.name)); + if (!m_routing.GetRoutingTable(&routing_table2)) + { + printf("m_routing.GetRoutingTable(&routing_table2=0x%p) Failed.\n",&routing_table2); + return false; + } + printf("route table %s has the handle %u\n", bypass2, routing_table2.hdl); + + IPAFilteringTable FilterTable0; + struct ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v4,IPA_CLIENT_TEST_PROD,false,3); + printf("FilterTable*.Init Completed Successfully..\n"); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1,flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl=-1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action=IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.rt_tbl_hdl=routing_table0.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; // + flt_rule_entry.rule.attrib.u.v4.dst_addr_mask = 0xFF0000FF; // Mask + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0x7F000001; // Filter DST_IP == 127.0.0.1. + flt_rule_entry.rule.hashable = 0; // non hashed + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.1 on lower priority (second in list) + flt_rule_entry.rule.rt_tbl_hdl=routing_table1.hdl; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.attrib.u.v4.dst_addr_mask = 0xFF0000FF; // Mask + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0x7F000001; // Filter DST_IP == 127.0.0.1. + flt_rule_entry.rule.hashable = 1; // hashed + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.2 + flt_rule_entry.rule.rt_tbl_hdl=routing_table2.hdl; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.hashable = 0; // non hashed + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0xC0A80102; // Filter DST_IP == 192.168.1.2. + + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(0)->status); + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(1)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(1)->status); + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(2)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(2)->status); + } + + printf("Leaving %s, %s()\n",__FUNCTION__, __FILE__); + return true; + + } + + virtual bool ModifyPackets() + { + int address; + // TODO: Add verification that we access only allocated addresses + // TODO: Fix this, doesn't match the Rule's Requirements + address = ntohl(0x7F000001);//127.0.0.1 + memcpy(&m_sendBuffer[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + address = ntohl(0x7F000001);//127.0.0.1 + memcpy(&m_sendBuffer2[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + address = ntohl(0xC0A80102);//192.168.1.2 + memcpy(&m_sendBuffer3[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + + return true; + + } + + virtual bool ReceivePacketsAndCompare() + { + size_t receivedSize = 0; + size_t receivedSize2 = 0; + size_t receivedSize3 = 0; + bool isSuccess = true; + + // Receive results + Byte *rxBuff1 = new Byte[0x400]; + Byte *rxBuff2 = new Byte[0x400]; + Byte *rxBuff3 = new Byte[0x400]; + + if (NULL == rxBuff1 || NULL == rxBuff2 || NULL == rxBuff3) + { + printf("Memory allocation error.\n"); + return false; + } + + receivedSize = m_consumer.ReceiveData(rxBuff1, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize, m_consumer.m_fromChannelName.c_str()); + + receivedSize2 = m_consumer.ReceiveData(rxBuff2, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize2, m_consumer.m_fromChannelName.c_str()); + + receivedSize3 = m_defaultConsumer.ReceiveData(rxBuff3, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize3, m_defaultConsumer.m_fromChannelName.c_str()); + + // Compare results + if (!CompareResultVsGolden(m_sendBuffer, m_sendSize, rxBuff1, receivedSize)) + { + printf("Comparison of Buffer0 Failed!\n"); + isSuccess = false; + } + + size_t recievedBufferSize = receivedSize * 3; + size_t sentBufferSize = m_sendSize * 3; + char *recievedBuffer = new char[recievedBufferSize]; + char *sentBuffer = new char[sentBufferSize]; + + memset(recievedBuffer, 0, recievedBufferSize); + memset(sentBuffer, 0, sentBufferSize); + + print_packets(receivedSize, m_sendSize, recievedBufferSize - 1, sentBufferSize - 1, rxBuff1, m_sendBuffer, recievedBuffer, sentBuffer); + recievedBuffer[0] = '\0'; + print_packets(receivedSize2, m_sendSize2, recievedBufferSize - 1, sentBufferSize - 1, rxBuff2, m_sendBuffer2, recievedBuffer, sentBuffer); + recievedBuffer[0] = '\0'; + print_packets(receivedSize3, m_sendSize3, recievedBufferSize - 1, sentBufferSize - 1, rxBuff3, m_sendBuffer3, recievedBuffer, sentBuffer); + + isSuccess &= CompareResultVsGolden(m_sendBuffer2, m_sendSize2, rxBuff2, receivedSize2); + isSuccess &= CompareResultVsGolden(m_sendBuffer3, m_sendSize3, rxBuff3, receivedSize3); + + delete[] recievedBuffer; + delete[] sentBuffer; + + delete[] rxBuff1; + delete[] rxBuff2; + delete[] rxBuff3; + + return isSuccess; + } + +}; + +/*----------------------------------------------------------------------------------------------*/ +/* Test061: IPV4 filtering test, hashed priority higher than non hashed priority + cache hit */ +/*----------------------------------------------------------------------------------------------*/ +class IpaFilteringBlockTest061 : public IpaFilteringBlockTestFixture +{ +public: + IpaFilteringBlockTest061() + { + m_name = "IpaFilteringBlockTest061"; + m_description = + "Filtering block test 061 - Rules prioritization hashable vs non-hashable rule, both rules match the same packet but hashable has higher priority\ + two identical packets are sent and should be catched by the hashable rule, second one shuld be hit the cache\ + 1. Generate and commit three routing tables. \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit three filtering rules: (DST & Mask Match). \ + All DST_IP == (127.0.0.1 & 255.0.0.255)traffic goes to routing table 0 - hashable\ + All DST_IP == (127.0.0.1 & 255.0.0.255)traffic goes to routing table 1 - non hashable\ + All DST_IP == (192.169.1.2 & 255.0.0.255)traffic goes to routing table 2 - don't care for this specific test"; + m_minIPAHwType = IPA_HW_v3_0; + Register(*this); + + } + + bool Setup() + { + /* we want statuses on this test */ + return IpaFilteringBlockTestFixture::Setup(true); + } + + virtual bool AddRules() + { + printf("Entering %s, %s()\n",__FUNCTION__, __FILE__); + + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + struct ipa_ioc_get_rt_tbl routing_table0,routing_table1,routing_table2; + + if (!CreateThreeIPv4BypassRoutingTables (bypass0,bypass1,bypass2)) + { + printf("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + + printf("CreateThreeBypassRoutingTables completed successfully\n"); + routing_table0.ip = IPA_IP_v4; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + printf("m_routing.GetRoutingTable(&routing_table0=0x%p) Failed.\n",&routing_table0); + return false; + } + printf("route table %s has the handle %u\n", bypass0, routing_table0.hdl); + + routing_table1.ip = IPA_IP_v4; + strlcpy(routing_table1.name, bypass1, sizeof(routing_table1.name)); + if (!m_routing.GetRoutingTable(&routing_table1)) + { + printf("m_routing.GetRoutingTable(&routing_table1=0x%p) Failed.\n",&routing_table1); + return false; + } + printf("route table %s has the handle %u\n", bypass1, routing_table1.hdl); + + routing_table2.ip = IPA_IP_v4; + strlcpy(routing_table2.name, bypass2, sizeof(routing_table2.name)); + if (!m_routing.GetRoutingTable(&routing_table2)) + { + printf("m_routing.GetRoutingTable(&routing_table2=0x%p) Failed.\n",&routing_table2); + return false; + } + printf("route table %s has the handle %u\n", bypass2, routing_table2.hdl); + + IPAFilteringTable FilterTable0; + struct ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v4,IPA_CLIENT_TEST_PROD,false,3); + printf("FilterTable*.Init Completed Successfully..\n"); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1,flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl=-1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action=IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.rt_tbl_hdl=routing_table0.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; // + flt_rule_entry.rule.attrib.u.v4.dst_addr_mask = 0xFF0000FF; // Mask + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0x7F000001; // Filter DST_IP == 127.0.0.1. + flt_rule_entry.rule.hashable = 1; // hashed + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.1 on lower priority (second in list) + flt_rule_entry.rule.rt_tbl_hdl=routing_table1.hdl; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.attrib.u.v4.dst_addr_mask = 0xFF0000FF; // Mask + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0x7F000001; // Filter DST_IP == 127.0.0.1. + flt_rule_entry.rule.hashable = 0; // non hashed + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.2 + flt_rule_entry.rule.rt_tbl_hdl=routing_table2.hdl; //put here the handle corresponding to Routing Rule 3 + flt_rule_entry.rule.hashable = 0; // non hashed + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0xC0A80102; // Filter DST_IP == 192.168.1.2. + + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(0)->status); + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(1)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(1)->status); + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(2)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(2)->status); + } + + printf("Leaving %s, %s()\n",__FUNCTION__, __FILE__); + return true; + } + + virtual bool ModifyPackets() + { + int address; + // TODO: Add verification that we access only allocated addresses + // TODO: Fix this, doesn't match the Rule's Requirements + address = ntohl(0x7F000001);//127.0.0.1 + memcpy(&m_sendBuffer[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + address = ntohl(0x7F000001);//127.0.0.1 + memcpy(&m_sendBuffer2[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + address = ntohl(0xC0A80102);//192.168.1.2 + memcpy(&m_sendBuffer3[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + + return true; + + } + + virtual bool ReceivePacketsAndCompare() + { + size_t receivedSize = 0; + size_t receivedSize2 = 0; + size_t receivedSize3 = 0; + bool isSuccess = true; + + // Receive results + Byte *rxBuff1 = new Byte[0x400]; + Byte *rxBuff2 = new Byte[0x400]; + Byte *rxBuff3 = new Byte[0x400]; + + if (NULL == rxBuff1 || NULL == rxBuff2 || NULL == rxBuff3) + { + printf("Memory allocation error.\n"); + return false; + } + + receivedSize = m_consumer.ReceiveData(rxBuff1, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize, m_consumer.m_fromChannelName.c_str()); + + receivedSize2 = m_consumer.ReceiveData(rxBuff2, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize2, m_consumer.m_fromChannelName.c_str()); + + receivedSize3 = m_defaultConsumer.ReceiveData(rxBuff3, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize3, m_defaultConsumer.m_fromChannelName.c_str()); + + // Compare results + if (!CompareResultVsGolden_w_Status(m_sendBuffer, m_sendSize, rxBuff1, receivedSize)) + { + printf("Comparison of Buffer0 Failed!\n"); + isSuccess = false; + } + + isSuccess &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_0) ? + IsCacheMiss_v5_0(m_sendSize, receivedSize, rxBuff1) : IsCacheMiss(m_sendSize,receivedSize,rxBuff1); + + size_t recievedBufferSize = receivedSize * 3; + size_t sentBufferSize = m_sendSize * 3; + char *recievedBuffer = new char[recievedBufferSize]; + char *sentBuffer = new char[sentBufferSize]; + + memset(recievedBuffer, 0, recievedBufferSize); + memset(sentBuffer, 0, sentBufferSize); + + print_packets(receivedSize, m_sendSize, recievedBufferSize, sentBufferSize, rxBuff1, m_sendBuffer, recievedBuffer, sentBuffer); + print_packets(receivedSize2, m_sendSize2, recievedBufferSize, sentBufferSize, rxBuff2, m_sendBuffer2, recievedBuffer, sentBuffer); + print_packets(receivedSize3, m_sendSize3, recievedBufferSize, sentBufferSize, rxBuff3, m_sendBuffer3, recievedBuffer, sentBuffer); + + + isSuccess &= CompareResultVsGolden_w_Status(m_sendBuffer2, m_sendSize2, rxBuff2, receivedSize2); + + isSuccess &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_0) ? + IsCacheHit_v5_0(m_sendSize2, receivedSize2, rxBuff2) : IsCacheHit(m_sendSize2,receivedSize2,rxBuff2); + + isSuccess &= CompareResultVsGolden_w_Status(m_sendBuffer3, m_sendSize3, rxBuff3, receivedSize3); + + isSuccess &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_0) ? + IsCacheMiss_v5_0(m_sendSize3, receivedSize3, rxBuff3) : IsCacheMiss(m_sendSize3,receivedSize3,rxBuff3); + + delete[] recievedBuffer; + delete[] sentBuffer; + + delete[] rxBuff1; + delete[] rxBuff2; + delete[] rxBuff3; + + return isSuccess; + } + +}; + +/*----------------------------------------------------------------------------------------------*/ +/* Test062: IPV4 filtering test, hashed rule match, non hash doesn't match expect cache miss */ +/*----------------------------------------------------------------------------------------------*/ +class IpaFilteringBlockTest062 : public IpaFilteringBlockTestFixture +{ +public: + IpaFilteringBlockTest062() + { + m_name = "IpaFilteringBlockTest062"; + m_description = + "Filtering block test 062 - Rules prioritization hashable vs non-hashable rule, only hashable matches the packets\ + two packets with different tuple are sent and should match the hashable rule, no cache hit expected\ + 1. Generate and commit three routing tables. \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit three filtering rules: (DST & Mask Match). \ + All DST_IP == (127.0.0.2 & 255.0.0.255)traffic goes to routing table 0 - non hashable\ + All DST_IP == (127.0.0.1 & 255.0.0.255)traffic goes to routing table 1 - hashable\ + All DST_IP == (192.169.1.2 & 255.0.0.255)traffic goes to routing table 2 - don't care for this specific test\ + 3. send three packets:\ + DST_IP == 127.0.0.1 port 546\ + DST_IP == 127.0.0.1 port 547\ + DST_IP == 192.168.1.2"; + m_minIPAHwType = IPA_HW_v3_0; + Register(*this); + } + + bool Setup() + { + /* we want statuses on this test */ + return IpaFilteringBlockTestFixture::Setup(true); + } + + virtual bool AddRules() + { + printf("Entering %s, %s()\n",__FUNCTION__, __FILE__); + + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + struct ipa_ioc_get_rt_tbl routing_table0,routing_table1,routing_table2; + + if (!CreateThreeIPv4BypassRoutingTables (bypass0,bypass1,bypass2)) + { + printf("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + + printf("CreateThreeBypassRoutingTables completed successfully\n"); + routing_table0.ip = IPA_IP_v4; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + printf("m_routing.GetRoutingTable(&routing_table0=0x%p) Failed.\n",&routing_table0); + return false; + } + printf("route table %s has the handle %u\n", bypass0, routing_table0.hdl); + + routing_table1.ip = IPA_IP_v4; + strlcpy(routing_table1.name, bypass1, sizeof(routing_table1.name)); + if (!m_routing.GetRoutingTable(&routing_table1)) + { + printf("m_routing.GetRoutingTable(&routing_table1=0x%p) Failed.\n",&routing_table1); + return false; + } + printf("route table %s has the handle %u\n", bypass1, routing_table1.hdl); + + routing_table2.ip = IPA_IP_v4; + strlcpy(routing_table2.name, bypass2, sizeof(routing_table2.name)); + if (!m_routing.GetRoutingTable(&routing_table2)) + { + printf("m_routing.GetRoutingTable(&routing_table2=0x%p) Failed.\n",&routing_table2); + return false; + } + printf("route table %s has the handle %u\n", bypass2, routing_table2.hdl); + + IPAFilteringTable FilterTable0; + struct ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v4,IPA_CLIENT_TEST_PROD,false,3); + printf("FilterTable*.Init Completed Successfully..\n"); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1,flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl=-1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action=IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.rt_tbl_hdl=routing_table0.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; // + flt_rule_entry.rule.attrib.u.v4.dst_addr_mask = 0xFF0000FF; // Mask + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0x7F000002; // Filter DST_IP == 127.0.0.2. + flt_rule_entry.rule.hashable = 0; // non hashed + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.1 on lower priority (second in list) + flt_rule_entry.rule.rt_tbl_hdl=routing_table1.hdl; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.attrib.u.v4.dst_addr_mask = 0xFF0000FF; // Mask + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0x7F000001; // Filter DST_IP == 127.0.0.1. + flt_rule_entry.rule.hashable = 1; // hashed + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.2 + flt_rule_entry.rule.rt_tbl_hdl=routing_table2.hdl; //put here the handle corresponding to Routing Rule 3 + flt_rule_entry.rule.hashable = 0; // non hashed + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0xC0A80102; // Filter DST_IP == 192.168.1.2. + + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(0)->status); + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(1)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(1)->status); + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(2)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(2)->status); + } + + printf("Leaving %s, %s()\n",__FUNCTION__, __FILE__); + return true; + + } + + virtual bool ModifyPackets() + { + int address; + unsigned short port; + + // TODO: Add verification that we access only allocated addresses + // TODO: Fix this, doesn't match the Rule's Requirements + address = ntohl(0x7F000001);//127.0.0.1 + memcpy(&m_sendBuffer[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + port = ntohs(546);//DHCP Client Port + memcpy (&m_sendBuffer[IPV4_DST_PORT_OFFSET], &port, sizeof(port)); + + address = ntohl(0x7F000001);//127.0.0.1 + memcpy(&m_sendBuffer2[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + port = ntohs(547);//DHCP Server Port + memcpy (&m_sendBuffer2[IPV4_DST_PORT_OFFSET], &port, sizeof(port)); + + address = ntohl(0xC0A80102);//192.168.1.2 + memcpy(&m_sendBuffer3[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + + return true; + + } + + virtual bool ReceivePacketsAndCompare() + { + size_t receivedSize = 0; + size_t receivedSize2 = 0; + size_t receivedSize3 = 0; + bool isSuccess = true; + + // Receive results + Byte *rxBuff1 = new Byte[0x400]; + Byte *rxBuff2 = new Byte[0x400]; + Byte *rxBuff3 = new Byte[0x400]; + + if (NULL == rxBuff1 || NULL == rxBuff2 || NULL == rxBuff3) + { + printf("Memory allocation error.\n"); + return false; + } + + receivedSize = m_consumer2.ReceiveData(rxBuff1, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize, m_consumer.m_fromChannelName.c_str()); + + receivedSize2 = m_consumer2.ReceiveData(rxBuff2, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize2, m_consumer.m_fromChannelName.c_str()); + + receivedSize3 = m_defaultConsumer.ReceiveData(rxBuff3, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize3, m_defaultConsumer.m_fromChannelName.c_str()); + + // Compare results + if (!CompareResultVsGolden_w_Status(m_sendBuffer, m_sendSize, rxBuff1, receivedSize)) + { + printf("Comparison of Buffer0 Failed!\n"); + isSuccess = false; + } + + isSuccess &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_0) ? + IsCacheMiss_v5_0(m_sendSize, receivedSize, rxBuff1) : IsCacheMiss(m_sendSize,receivedSize,rxBuff1); + + size_t recievedBufferSize = receivedSize * 3; + size_t sentBufferSize = m_sendSize * 3; + char *recievedBuffer = new char[recievedBufferSize]; + char *sentBuffer = new char[sentBufferSize]; + + memset(recievedBuffer, 0, recievedBufferSize); + memset(sentBuffer, 0, sentBufferSize); + + print_packets(receivedSize, m_sendSize, recievedBufferSize, sentBufferSize, rxBuff1, m_sendBuffer, recievedBuffer, sentBuffer); + print_packets(receivedSize2, m_sendSize2, recievedBufferSize, sentBufferSize, rxBuff2, m_sendBuffer2, recievedBuffer, sentBuffer); + print_packets(receivedSize3, m_sendSize3, recievedBufferSize, sentBufferSize, rxBuff3, m_sendBuffer3, recievedBuffer, sentBuffer); + + isSuccess &= CompareResultVsGolden_w_Status(m_sendBuffer2, m_sendSize2, rxBuff2, receivedSize2); + + isSuccess &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_0) ? + IsCacheMiss_v5_0(m_sendSize2, receivedSize2, rxBuff2) : IsCacheMiss(m_sendSize2,receivedSize2,rxBuff2); + + isSuccess &= CompareResultVsGolden_w_Status(m_sendBuffer3, m_sendSize3, rxBuff3, receivedSize3); + + isSuccess &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_0) ? + IsCacheMiss_v5_0(m_sendSize3, receivedSize3, rxBuff3) : IsCacheMiss(m_sendSize3,receivedSize3,rxBuff3); + + delete[] recievedBuffer; + delete[] sentBuffer; + + delete[] rxBuff1; + delete[] rxBuff2; + delete[] rxBuff3; + + return isSuccess; + } +}; + +/*----------------------------------------------------------------------------------------------*/ +/* Test063: IPV4 filtering test, hashed rule match, non hash doesn't match expect cache miss */ +/*----------------------------------------------------------------------------------------------*/ +class IpaFilteringBlockTest063 : public IpaFilteringBlockTestFixture +{ +public: + + IpaFilteringBlockTest063() + { + m_name = "IpaFilteringBlockTest063"; + m_description = + "Filtering block test 063 - Rules prioritization hashable vs non-hashable rule, only hashable matches the packets\ + two packets with different tuple are sent and should match the hashable rule, no cache hit expected\ + 1. Generate and commit three routing tables. \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit three filtering rules: (DST & Mask Match). \ + All DST_IP == (127.0.0.1 & 255.0.0.255)traffic goes to routing table 0 - hashable\ + All DST_IP == (127.0.0.2 & 255.0.0.255)traffic goes to routing table 1 - non hashable\ + All DST_IP == (192.169.1.2 & 255.0.0.255)traffic goes to routing table 2 - don't care for this specific test\ + 3. send three packets:\ + DST_IP == 127.0.0.1 port 546\ + DST_IP == 127.0.0.1 port 547\ + DST_IP == 192.168.1.2"; + m_minIPAHwType = IPA_HW_v3_0; + Register(*this); + } + + bool Setup() + { + /* we want statuses on this test */ + return IpaFilteringBlockTestFixture::Setup(true); + } + + virtual bool AddRules() + { + printf("Entering %s, %s()\n",__FUNCTION__, __FILE__); + + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + struct ipa_ioc_get_rt_tbl routing_table0,routing_table1,routing_table2; + + if (!CreateThreeIPv4BypassRoutingTables (bypass0,bypass1,bypass2)) + { + printf("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + + printf("CreateThreeBypassRoutingTables completed successfully\n"); + routing_table0.ip = IPA_IP_v4; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + printf("m_routing.GetRoutingTable(&routing_table0=0x%p) Failed.\n",&routing_table0); + return false; + } + printf("route table %s has the handle %u\n", bypass0, routing_table0.hdl); + + routing_table1.ip = IPA_IP_v4; + strlcpy(routing_table1.name, bypass1, sizeof(routing_table1.name)); + if (!m_routing.GetRoutingTable(&routing_table1)) + { + printf("m_routing.GetRoutingTable(&routing_table1=0x%p) Failed.\n",&routing_table1); + return false; + } + printf("route table %s has the handle %u\n", bypass1, routing_table1.hdl); + + routing_table2.ip = IPA_IP_v4; + strlcpy(routing_table2.name, bypass2, sizeof(routing_table2.name)); + if (!m_routing.GetRoutingTable(&routing_table2)) + { + printf("m_routing.GetRoutingTable(&routing_table2=0x%p) Failed.\n",&routing_table2); + return false; + } + printf("route table %s has the handle %u\n", bypass2, routing_table2.hdl); + + IPAFilteringTable FilterTable0; + struct ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v4,IPA_CLIENT_TEST_PROD,false,3); + printf("FilterTable*.Init Completed Successfully..\n"); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1,flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl=-1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action=IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.rt_tbl_hdl=routing_table0.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; // + flt_rule_entry.rule.attrib.u.v4.dst_addr_mask = 0xFF0000FF; // Mask + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0x7F000001; // Filter DST_IP == 127.0.0.1. + flt_rule_entry.rule.hashable = 1; // hashed + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.1 on lower priority (second in list) + flt_rule_entry.rule.rt_tbl_hdl=routing_table1.hdl; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.attrib.u.v4.dst_addr_mask = 0xFF0000FF; // Mask + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0x7F000002; // Filter DST_IP == 127.0.0.2. + flt_rule_entry.rule.hashable = 0; // non hashed + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.2 + flt_rule_entry.rule.rt_tbl_hdl=routing_table2.hdl; //put here the handle corresponding to Routing Rule 3 + flt_rule_entry.rule.hashable = 0; // non hashed + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0xC0A80102; // Filter DST_IP == 192.168.1.2. + + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(0)->status); + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(1)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(1)->status); + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(2)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(2)->status); + } + + printf("Leaving %s, %s()\n",__FUNCTION__, __FILE__); + return true; + } + + virtual bool ModifyPackets() + { + int address; + unsigned short port; + + // TODO: Add verification that we access only allocated addresses + // TODO: Fix this, doesn't match the Rule's Requirements + address = ntohl(0x7F000001);//127.0.0.1 + memcpy(&m_sendBuffer[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + port = ntohs(546);//DHCP Client Port + memcpy (&m_sendBuffer[IPV4_DST_PORT_OFFSET], &port, sizeof(port)); + + address = ntohl(0x7F000001);//127.0.0.1 + memcpy(&m_sendBuffer2[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + port = ntohs(547);//DHCP Server Port + memcpy (&m_sendBuffer2[IPV4_DST_PORT_OFFSET], &port, sizeof(port)); + + address = ntohl(0xC0A80102);//192.168.1.2 + memcpy(&m_sendBuffer3[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + + return true; + + } + + virtual bool ReceivePacketsAndCompare() + { + size_t receivedSize = 0; + size_t receivedSize2 = 0; + size_t receivedSize3 = 0; + bool isSuccess = true; + + // Receive results + Byte *rxBuff1 = new Byte[0x400]; + Byte *rxBuff2 = new Byte[0x400]; + Byte *rxBuff3 = new Byte[0x400]; + + if (NULL == rxBuff1 || NULL == rxBuff2 || NULL == rxBuff3) + { + printf("Memory allocation error.\n"); + return false; + } + + receivedSize = m_consumer.ReceiveData(rxBuff1, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize, m_consumer.m_fromChannelName.c_str()); + + receivedSize2 = m_consumer.ReceiveData(rxBuff2, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize2, m_consumer.m_fromChannelName.c_str()); + + receivedSize3 = m_defaultConsumer.ReceiveData(rxBuff3, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize3, m_defaultConsumer.m_fromChannelName.c_str()); + + // Compare results + if (!CompareResultVsGolden_w_Status(m_sendBuffer, m_sendSize, rxBuff1, receivedSize)) + { + printf("Comparison of Buffer0 Failed!\n"); + isSuccess = false; + } + + isSuccess &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_0) ? + IsCacheMiss_v5_0(m_sendSize, receivedSize, rxBuff1) : IsCacheMiss(m_sendSize,receivedSize,rxBuff1); + + size_t recievedBufferSize = receivedSize * 3; + size_t sentBufferSize = m_sendSize * 3; + char *recievedBuffer = new char[recievedBufferSize]; + char *sentBuffer = new char[sentBufferSize]; + + memset(recievedBuffer, 0, recievedBufferSize); + memset(sentBuffer, 0, sentBufferSize); + + print_packets(receivedSize, m_sendSize, recievedBufferSize, sentBufferSize, rxBuff1, m_sendBuffer, recievedBuffer, sentBuffer); + print_packets(receivedSize2, m_sendSize2, recievedBufferSize, sentBufferSize, rxBuff2, m_sendBuffer2, recievedBuffer, sentBuffer); + print_packets(receivedSize3, m_sendSize3, recievedBufferSize, sentBufferSize, rxBuff3, m_sendBuffer3, recievedBuffer, sentBuffer); + + + isSuccess &= CompareResultVsGolden_w_Status(m_sendBuffer2, m_sendSize2, rxBuff2, receivedSize2); + + isSuccess &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_0) ? + IsCacheMiss_v5_0(m_sendSize2, receivedSize2, rxBuff2) : IsCacheMiss(m_sendSize2,receivedSize2,rxBuff2); + + isSuccess &= CompareResultVsGolden_w_Status(m_sendBuffer3, m_sendSize3, rxBuff3, receivedSize3); + + isSuccess &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_0) ? + IsCacheMiss_v5_0(m_sendSize3, receivedSize3, rxBuff3) : IsCacheMiss(m_sendSize3,receivedSize3,rxBuff3); + + delete[] recievedBuffer; + delete[] sentBuffer; + + delete[] rxBuff1; + delete[] rxBuff2; + delete[] rxBuff3; + + return isSuccess; + } +}; + + +/*----------------------------------------------------------------------------------------------*/ +/* Test064: IPV4 filtering test, hashed rule match, non hash doesn't match expect cache hit */ +/*----------------------------------------------------------------------------------------------*/ +class IpaFilteringBlockTest064 : public IpaFilteringBlockTestFixture +{ +public: + + IpaFilteringBlockTest064() + { + m_name = "IpaFilteringBlockTest064"; + m_description = + "Filtering block test 064 - Rules prioritization hashable vs non-hashable rule, only hashable matches the packets\ + two identical packets are sent and should match the hashable rule, cache hit expected\ + 1. Generate and commit three routing tables. \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit three filtering rules: (DST & Mask Match). \ + All DST_IP == (127.0.0.2 & 255.0.0.255)traffic goes to routing table 0 - non hashable\ + All DST_IP == (127.0.0.1 & 255.0.0.255)traffic goes to routing table 1 - hashable\ + All DST_IP == (192.169.1.2 & 255.0.0.255)traffic goes to routing table 2 - don't care for this specific test\ + 3. send three packets:\ + DST_IP == 127.0.0.1 \ + DST_IP == 127.0.0.1 \ + DST_IP == 192.168.1.2"; + m_minIPAHwType = IPA_HW_v3_0; + Register(*this); + } + + bool Setup() + { + /* we want statuses on this test */ + return IpaFilteringBlockTestFixture::Setup(true); + } + + virtual bool AddRules() + { + printf("Entering %s, %s()\n",__FUNCTION__, __FILE__); + + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + struct ipa_ioc_get_rt_tbl routing_table0,routing_table1,routing_table2; + + if (!CreateThreeIPv4BypassRoutingTables (bypass0,bypass1,bypass2)) + { + printf("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + + printf("CreateThreeBypassRoutingTables completed successfully\n"); + routing_table0.ip = IPA_IP_v4; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + printf("m_routing.GetRoutingTable(&routing_table0=0x%p) Failed.\n",&routing_table0); + return false; + } + printf("route table %s has the handle %u\n", bypass0, routing_table0.hdl); + + routing_table1.ip = IPA_IP_v4; + strlcpy(routing_table1.name, bypass1, sizeof(routing_table1.name)); + if (!m_routing.GetRoutingTable(&routing_table1)) + { + printf("m_routing.GetRoutingTable(&routing_table1=0x%p) Failed.\n",&routing_table1); + return false; + } + printf("route table %s has the handle %u\n", bypass1, routing_table1.hdl); + + routing_table2.ip = IPA_IP_v4; + strlcpy(routing_table2.name, bypass2, sizeof(routing_table2.name)); + if (!m_routing.GetRoutingTable(&routing_table2)) + { + printf("m_routing.GetRoutingTable(&routing_table2=0x%p) Failed.\n",&routing_table2); + return false; + } + printf("route table %s has the handle %u\n", bypass2, routing_table2.hdl); + + IPAFilteringTable FilterTable0; + struct ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v4,IPA_CLIENT_TEST_PROD,false,3); + printf("FilterTable*.Init Completed Successfully..\n"); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1,flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl=-1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action=IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.rt_tbl_hdl=routing_table0.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; // + flt_rule_entry.rule.attrib.u.v4.dst_addr_mask = 0xFF0000FF; // Mask + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0x7F000002; // Filter DST_IP == 127.0.0.2. + flt_rule_entry.rule.hashable = 0; // non hashed + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.1 on lower priority (second in list) + flt_rule_entry.rule.rt_tbl_hdl=routing_table1.hdl; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.attrib.u.v4.dst_addr_mask = 0xFF0000FF; // Mask + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0x7F000001; // Filter DST_IP == 127.0.0.1. + flt_rule_entry.rule.hashable = 1; // hashed + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.2 + flt_rule_entry.rule.rt_tbl_hdl=routing_table2.hdl; //put here the handle corresponding to Routing Rule 3 + flt_rule_entry.rule.hashable = 0; // non hashed + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0xC0A80102; // Filter DST_IP == 192.168.1.2. + + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(0)->status); + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(1)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(1)->status); + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(2)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(2)->status); + } + + printf("Leaving %s, %s()\n",__FUNCTION__, __FILE__); + return true; + } + + virtual bool ModifyPackets() + { + int address; + + // TODO: Add verification that we access only allocated addresses + // TODO: Fix this, doesn't match the Rule's Requirements + address = ntohl(0x7F000001);//127.0.0.1 + memcpy(&m_sendBuffer[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + + address = ntohl(0x7F000001);//127.0.0.1 + memcpy(&m_sendBuffer2[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + + address = ntohl(0xC0A80102);//192.168.1.2 + memcpy(&m_sendBuffer3[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + + return true; + + } + + virtual bool ReceivePacketsAndCompare() + { + size_t receivedSize = 0; + size_t receivedSize2 = 0; + size_t receivedSize3 = 0; + bool isSuccess = true; + + // Receive results + Byte *rxBuff1 = new Byte[0x400]; + Byte *rxBuff2 = new Byte[0x400]; + Byte *rxBuff3 = new Byte[0x400]; + + if (NULL == rxBuff1 || NULL == rxBuff2 || NULL == rxBuff3) + { + printf("Memory allocation error.\n"); + return false; + } + + receivedSize = m_consumer2.ReceiveData(rxBuff1, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize, m_consumer.m_fromChannelName.c_str()); + + receivedSize2 = m_consumer2.ReceiveData(rxBuff2, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize2, m_consumer.m_fromChannelName.c_str()); + + receivedSize3 = m_defaultConsumer.ReceiveData(rxBuff3, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize3, m_defaultConsumer.m_fromChannelName.c_str()); + + // Compare results + if (!CompareResultVsGolden_w_Status(m_sendBuffer, m_sendSize, rxBuff1, receivedSize)) + { + printf("Comparison of Buffer0 Failed!\n"); + isSuccess = false; + } + + isSuccess &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_0) ? + IsCacheMiss_v5_0(m_sendSize, receivedSize, rxBuff1) : IsCacheMiss(m_sendSize,receivedSize,rxBuff1); + + size_t recievedBufferSize = receivedSize * 3; + size_t sentBufferSize = m_sendSize * 3; + char *recievedBuffer = new char[recievedBufferSize]; + char *sentBuffer = new char[sentBufferSize]; + + memset(recievedBuffer, 0, recievedBufferSize); + memset(sentBuffer, 0, sentBufferSize); + + print_packets(receivedSize, m_sendSize, recievedBufferSize, sentBufferSize, rxBuff1, m_sendBuffer, recievedBuffer, sentBuffer); + print_packets(receivedSize2, m_sendSize2, recievedBufferSize, sentBufferSize, rxBuff2, m_sendBuffer2, recievedBuffer, sentBuffer); + print_packets(receivedSize3, m_sendSize3, recievedBufferSize, sentBufferSize, rxBuff3, m_sendBuffer3, recievedBuffer, sentBuffer); + + isSuccess &= CompareResultVsGolden_w_Status(m_sendBuffer2, m_sendSize2, rxBuff2, receivedSize2); + + isSuccess &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_0) ? + IsCacheHit_v5_0(m_sendSize2, receivedSize2, rxBuff2) : IsCacheHit(m_sendSize2,receivedSize2,rxBuff2); + + isSuccess &= CompareResultVsGolden_w_Status(m_sendBuffer3, m_sendSize3, rxBuff3, receivedSize3); + + isSuccess &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_0) ? + IsCacheMiss_v5_0(m_sendSize3, receivedSize3, rxBuff3) : IsCacheMiss(m_sendSize3,receivedSize3,rxBuff3); + + delete[] recievedBuffer; + delete[] sentBuffer; + + delete[] rxBuff1; + delete[] rxBuff2; + delete[] rxBuff3; + + return isSuccess; + } + +}; + +/*----------------------------------------------------------------------------------------------*/ +/* Test065: IPV4 filtering test, non hashable rule match with max priority vs hashable */ +/*----------------------------------------------------------------------------------------------*/ +class IpaFilteringBlockTest065 : public IpaFilteringBlockTestFixture +{ +public: + + IpaFilteringBlockTest065() + { + m_name = "IpaFilteringBlockTest065"; + m_description = + "Filtering block test 065 - Rules prioritization hashable vs non-hashable rule, both rules match the packets\ + two identical packets are sent, non hashed with max priority should catch both\ + 1. Generate and commit three routing tables. \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit three filtering rules: (DST & Mask Match). \ + All DST_IP == (127.0.0.1 & 255.0.0.255)traffic goes to routing table 0 - hashable\ + All DST_IP == (127.0.0.1 & 255.0.0.255)traffic goes to routing table 1 - non hashable max prio\ + All DST_IP == (192.169.1.2 & 255.0.0.255)traffic goes to routing table 2 - don't care for this specific test\ + 3. send three packets:\ + DST_IP == 127.0.0.1 \ + DST_IP == 127.0.0.1 \ + DST_IP == 192.168.1.2"; + m_minIPAHwType = IPA_HW_v3_0; + Register(*this); + } + + virtual bool AddRules() + { + printf("Entering %s, %s()\n",__FUNCTION__, __FILE__); + + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + struct ipa_ioc_get_rt_tbl routing_table0,routing_table1,routing_table2; + + if (!CreateThreeIPv4BypassRoutingTables (bypass0,bypass1,bypass2)) + { + printf("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + + printf("CreateThreeBypassRoutingTables completed successfully\n"); + routing_table0.ip = IPA_IP_v4; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + printf("m_routing.GetRoutingTable(&routing_table0=0x%p) Failed.\n",&routing_table0); + return false; + } + printf("route table %s has the handle %u\n", bypass0, routing_table0.hdl); + + routing_table1.ip = IPA_IP_v4; + strlcpy(routing_table1.name, bypass1, sizeof(routing_table1.name)); + if (!m_routing.GetRoutingTable(&routing_table1)) + { + printf("m_routing.GetRoutingTable(&routing_table1=0x%p) Failed.\n",&routing_table1); + return false; + } + printf("route table %s has the handle %u\n", bypass1, routing_table1.hdl); + + routing_table2.ip = IPA_IP_v4; + strlcpy(routing_table2.name, bypass2, sizeof(routing_table2.name)); + if (!m_routing.GetRoutingTable(&routing_table2)) + { + printf("m_routing.GetRoutingTable(&routing_table2=0x%p) Failed.\n",&routing_table2); + return false; + } + printf("route table %s has the handle %u\n", bypass2, routing_table2.hdl); + + IPAFilteringTable FilterTable0; + struct ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v4,IPA_CLIENT_TEST_PROD,false,3); + printf("FilterTable*.Init Completed Successfully..\n"); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1,flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl=-1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action=IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.rt_tbl_hdl=routing_table0.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; // + flt_rule_entry.rule.attrib.u.v4.dst_addr_mask = 0xFF0000FF; // Mask + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0x7F000001; // Filter DST_IP == 127.0.0.1. + flt_rule_entry.rule.hashable = 1; // hashed + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.1 on lower priority (second in list) + flt_rule_entry.rule.rt_tbl_hdl=routing_table1.hdl; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.attrib.u.v4.dst_addr_mask = 0xFF0000FF; // Mask + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0x7F000001; // Filter DST_IP == 127.0.0.1. + flt_rule_entry.rule.hashable = 0; // non hashed + flt_rule_entry.rule.max_prio = 1; // max prioirty, should overcome all other rules + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.2 + flt_rule_entry.rule.rt_tbl_hdl=routing_table2.hdl; //put here the handle corresponding to Routing Rule 3 + flt_rule_entry.rule.hashable = 0; // non hashed + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0xC0A80102; // Filter DST_IP == 192.168.1.2. + + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(0)->status); + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(1)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(1)->status); + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(2)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(2)->status); + } + + printf("Leaving %s, %s()\n",__FUNCTION__, __FILE__); + return true; + } + + virtual bool ModifyPackets() + { + int address; + + // TODO: Add verification that we access only allocated addresses + // TODO: Fix this, doesn't match the Rule's Requirements + address = ntohl(0x7F000001);//127.0.0.1 + memcpy(&m_sendBuffer[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + + address = ntohl(0x7F000001);//127.0.0.1 + memcpy(&m_sendBuffer2[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + + address = ntohl(0xC0A80102);//192.168.1.2 + memcpy(&m_sendBuffer3[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + + return true; + + } + + virtual bool ReceivePacketsAndCompare() + { + size_t receivedSize = 0; + size_t receivedSize2 = 0; + size_t receivedSize3 = 0; + bool isSuccess = true; + + // Receive results + Byte *rxBuff1 = new Byte[0x400]; + Byte *rxBuff2 = new Byte[0x400]; + Byte *rxBuff3 = new Byte[0x400]; + + if (NULL == rxBuff1 || NULL == rxBuff2 || NULL == rxBuff3) + { + printf("Memory allocation error.\n"); + return false; + } + + receivedSize = m_consumer2.ReceiveData(rxBuff1, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize, m_consumer.m_fromChannelName.c_str()); + + receivedSize2 = m_consumer2.ReceiveData(rxBuff2, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize2, m_consumer.m_fromChannelName.c_str()); + + receivedSize3 = m_defaultConsumer.ReceiveData(rxBuff3, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize3, m_defaultConsumer.m_fromChannelName.c_str()); + + // Compare results + if (!CompareResultVsGolden(m_sendBuffer, m_sendSize, rxBuff1, receivedSize)) + { + printf("Comparison of Buffer0 Failed!\n"); + isSuccess = false; + } + + size_t recievedBufferSize = receivedSize * 3; + size_t sentBufferSize = m_sendSize * 3; + char *recievedBuffer = new char[recievedBufferSize]; + char *sentBuffer = new char[sentBufferSize]; + + memset(recievedBuffer, 0, recievedBufferSize); + memset(sentBuffer, 0, sentBufferSize); + + print_packets(receivedSize, m_sendSize, recievedBufferSize, sentBufferSize, rxBuff1, m_sendBuffer, recievedBuffer, sentBuffer); + print_packets(receivedSize2, m_sendSize2, recievedBufferSize, sentBufferSize, rxBuff2, m_sendBuffer2, recievedBuffer, sentBuffer); + print_packets(receivedSize3, m_sendSize3, recievedBufferSize, sentBufferSize, rxBuff3, m_sendBuffer3, recievedBuffer, sentBuffer); + + isSuccess &= CompareResultVsGolden(m_sendBuffer2, m_sendSize2, rxBuff2, receivedSize2); + + isSuccess &= CompareResultVsGolden(m_sendBuffer3, m_sendSize3, rxBuff3, receivedSize3); + + delete[] recievedBuffer; + delete[] sentBuffer; + + delete[] rxBuff1; + delete[] rxBuff2; + delete[] rxBuff3; + + return isSuccess; + } + +}; + +/*----------------------------------------------------------------------------------------------*/ +/* Test066: IPV4 filtering test, hashed rule match, non hash doesn't match expect cache hit */ +/*----------------------------------------------------------------------------------------------*/ +class IpaFilteringBlockTest066 : public IpaFilteringBlockTestFixture +{ +public: + bool IsSecondTime; + + IpaFilteringBlockTest066(): IsSecondTime(false) + { + m_name = "IpaFilteringBlockTest066"; + m_description = + "Filtering block test 066 - Rules prioritization hashable vs non-hashable rule, only hashable matches the packets\ + two identical packets are sent and should match the hashable rule, cache hit expected\ + 1. Generate and commit three routing tables. \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit three filtering rules: (DST & Mask Match). \ + All DST_IP == (127.0.0.1 & 255.0.0.255)traffic goes to routing table 0 - hashable\ + All DST_IP == (127.0.0.2 & 255.0.0.255)traffic goes to routing table 1 - non hashable\ + All DST_IP == (192.169.1.2 & 255.0.0.255)traffic goes to routing table 2 - don't care for this specific test\ + 3. send three packets:\ + DST_IP == 127.0.0.1 \ + DST_IP == 127.0.0.1 \ + DST_IP == 192.168.1.2"; + m_minIPAHwType = IPA_HW_v3_0; + Register(*this); + } + + bool Setup() + { + /* we want statuses on this test */ + return IpaFilteringBlockTestFixture::Setup(true); + } + + virtual bool AddRules() + { + printf("Entering %s, %s()\n",__FUNCTION__, __FILE__); + + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + struct ipa_ioc_get_rt_tbl routing_table0,routing_table1,routing_table2; + + if (!CreateThreeIPv4BypassRoutingTables (bypass0,bypass1,bypass2)) + { + printf("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + + printf("CreateThreeBypassRoutingTables completed successfully\n"); + routing_table0.ip = IPA_IP_v4; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + printf("m_routing.GetRoutingTable(&routing_table0=0x%p) Failed.\n",&routing_table0); + return false; + } + printf("route table %s has the handle %u\n", bypass0, routing_table0.hdl); + + routing_table1.ip = IPA_IP_v4; + strlcpy(routing_table1.name, bypass1, sizeof(routing_table1.name)); + if (!m_routing.GetRoutingTable(&routing_table1)) + { + printf("m_routing.GetRoutingTable(&routing_table1=0x%p) Failed.\n",&routing_table1); + return false; + } + printf("route table %s has the handle %u\n", bypass1, routing_table1.hdl); + + routing_table2.ip = IPA_IP_v4; + strlcpy(routing_table2.name, bypass2, sizeof(routing_table2.name)); + if (!m_routing.GetRoutingTable(&routing_table2)) + { + printf("m_routing.GetRoutingTable(&routing_table2=0x%p) Failed.\n",&routing_table2); + return false; + } + printf("route table %s has the handle %u\n", bypass2, routing_table2.hdl); + + struct ipa_flt_rule_add flt_rule_entry; + if (!IsSecondTime) { + FilterTable0.Init(IPA_IP_v4, IPA_CLIENT_TEST_PROD, false, 3); + printf("FilterTable*.Init Completed Successfully..\n"); + IsSecondTime = true; + + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1,flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl=-1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action=IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.rt_tbl_hdl=routing_table0.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; // + flt_rule_entry.rule.attrib.u.v4.dst_addr_mask = 0xFF0000FF; // Mask + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0x7F000001; // Filter DST_IP == 127.0.0.2. + flt_rule_entry.rule.hashable = 1; // hashed + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.1 on lower priority (second in list) + flt_rule_entry.rule.rt_tbl_hdl=routing_table1.hdl; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.attrib.u.v4.dst_addr_mask = 0xFF0000FF; // Mask + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0x7F000002; // Filter DST_IP == 127.0.0.1. + flt_rule_entry.rule.hashable = 0; // non hashed + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.2 + flt_rule_entry.rule.rt_tbl_hdl=routing_table2.hdl; //put here the handle corresponding to Routing Rule 3 + flt_rule_entry.rule.hashable = 0; // non hashed + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0xC0A80102; // Filter DST_IP == 192.168.1.2. + + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(0)->status); + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(1)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(1)->status); + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(2)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(2)->status); + } + } else { + printf("in the second time, just commit again\n"); + if (!m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable())) { + printf("%s::Error Adding Rule to Filter Table, aborting...\n", __FUNCTION__); + return false; + } + } + + printf("Leaving %s, %s()\n",__FUNCTION__, __FILE__); + return true; + } + + bool RemoveLastRule() + { + struct ipa_ioc_del_flt_rule *pDeleteRule = (struct ipa_ioc_del_flt_rule *) + calloc(1, sizeof(struct ipa_ioc_del_flt_rule) + sizeof(struct ipa_flt_rule_del)); + + pDeleteRule->commit = 1; + pDeleteRule->ip = IPA_IP_v4; + pDeleteRule->num_hdls = 1; + pDeleteRule->hdl[0].hdl = FilterTable0.ReadRuleFromTable(2)->flt_rule_hdl; + pDeleteRule->hdl[0].status = FilterTable0.ReadRuleFromTable(2)->status; + + if (!m_filtering.DeleteFilteringRule(pDeleteRule)) + { + printf ("%s::Error Deleting Rule from Filter Table, aborting...\n",__FUNCTION__); + return false; + } + + return true; + } + + virtual bool ModifyPackets() + { + int address; + + // TODO: Add verification that we access only allocated addresses + // TODO: Fix this, doesn't match the Rule's Requirements + address = ntohl(0x7F000001);//127.0.0.1 + memcpy(&m_sendBuffer[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + + address = ntohl(0x7F000001);//127.0.0.1 + memcpy(&m_sendBuffer2[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + + address = ntohl(0xC0A80102);//192.168.1.2 + memcpy(&m_sendBuffer3[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + + return true; + + } + + virtual bool ReceivePacketsAndCompare() + { + size_t receivedSize = 0; + size_t receivedSize2 = 0; + size_t receivedSize3 = 0; + bool isSuccess = true; + + // Receive results + Byte *rxBuff1 = new Byte[0x400]; + Byte *rxBuff2 = new Byte[0x400]; + Byte *rxBuff3 = new Byte[0x400]; + + if (NULL == rxBuff1 || NULL == rxBuff2 || NULL == rxBuff3) + { + printf("Memory allocation error.\n"); + return false; + } + + receivedSize = m_consumer.ReceiveData(rxBuff1, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize, m_consumer.m_fromChannelName.c_str()); + + receivedSize2 = m_consumer.ReceiveData(rxBuff2, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize2, m_consumer.m_fromChannelName.c_str()); + + receivedSize3 = m_defaultConsumer.ReceiveData(rxBuff3, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize3, m_defaultConsumer.m_fromChannelName.c_str()); + + // Compare results + if (!CompareResultVsGolden_w_Status(m_sendBuffer, m_sendSize, rxBuff1, receivedSize)) + { + printf("Comparison of Buffer0 Failed!\n"); + isSuccess = false; + } + + isSuccess &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_0) ? + IsCacheMiss_v5_0(m_sendSize, receivedSize, rxBuff1) : IsCacheMiss(m_sendSize,receivedSize,rxBuff1); + + size_t recievedBufferSize = receivedSize * 3; + size_t sentBufferSize = m_sendSize * 3; + char *recievedBuffer = new char[recievedBufferSize]; + char *sentBuffer = new char[sentBufferSize]; + + memset(recievedBuffer, 0, recievedBufferSize); + memset(sentBuffer, 0, sentBufferSize); + + print_packets(receivedSize, m_sendSize, recievedBufferSize, sentBufferSize, rxBuff1, m_sendBuffer, recievedBuffer, sentBuffer); + print_packets(receivedSize2, m_sendSize2, recievedBufferSize, sentBufferSize, rxBuff2, m_sendBuffer2, recievedBuffer, sentBuffer); + print_packets(receivedSize3, m_sendSize3, recievedBufferSize, sentBufferSize, rxBuff3, m_sendBuffer3, recievedBuffer, sentBuffer); + + isSuccess &= CompareResultVsGolden_w_Status(m_sendBuffer2, m_sendSize2, rxBuff2, receivedSize2); + + isSuccess &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_0) ? + IsCacheHit_v5_0(m_sendSize2, receivedSize2, rxBuff2) : IsCacheHit(m_sendSize2,receivedSize2,rxBuff2); + + isSuccess &= CompareResultVsGolden_w_Status(m_sendBuffer3, m_sendSize3, rxBuff3, receivedSize3); + + isSuccess &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_0) ? + IsCacheMiss_v5_0(m_sendSize3, receivedSize3, rxBuff3) : IsCacheMiss(m_sendSize3,receivedSize3,rxBuff3); + + delete[] recievedBuffer; + delete[] sentBuffer; + + delete[] rxBuff1; + delete[] rxBuff2; + delete[] rxBuff3; + + return isSuccess; + } + + bool ReceiveAndCompareSpecial() + { + size_t receivedSize = 0; + + bool isSuccess = true; + + // Receive results + Byte *rxBuff1 = new Byte[0x400]; + + if (NULL == rxBuff1) + { + printf("Memory allocation error.\n"); + return false; + } + + receivedSize = m_consumer.ReceiveData(rxBuff1, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize, m_consumer.m_fromChannelName.c_str()); + + // Compare results + if (!CompareResultVsGolden_w_Status(m_sendBuffer, m_sendSize, rxBuff1, receivedSize)) + { + printf("Comparison of Buffer0 Failed!\n"); + isSuccess = false; + } + + isSuccess &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_0) ? + IsCacheMiss_v5_0(m_sendSize, receivedSize, rxBuff1) : IsCacheMiss(m_sendSize,receivedSize,rxBuff1); + + size_t recievedBufferSize = receivedSize * 3; + size_t sentBufferSize = m_sendSize * 3; + char *recievedBuffer = new char[recievedBufferSize]; + char *sentBuffer = new char[sentBufferSize]; + size_t j; + + if ((3 * m_sendSize) > sentBufferSize) + printf("Failed to stringify sent packet. Buffer too small\n"); + else + for(j = 0; j < m_sendSize; j++) + snprintf(&sentBuffer[3 * j], sentBufferSize - 3 * j, + " %02X", m_sendBuffer[j]); + if ((3 * receivedSize) > recievedBufferSize) + printf("Failed to stringify recieved packet. Buffer too small\n"); + else + for(j = 0; j < receivedSize; j++) + snprintf(&recievedBuffer[3 * j], recievedBufferSize - 3 * j, + " %02X", rxBuff1[j]); + printf("Expected Value1 (%zu)\n%s\n, Received Value1(%zu)\n%s\n",m_sendSize,sentBuffer,receivedSize,recievedBuffer); + + delete[] recievedBuffer; + delete[] sentBuffer; + delete[] rxBuff1; + return isSuccess; + + } + +private: + IPAFilteringTable FilterTable0; +}; + +/*----------------------------------------------------------------------------------------------*/ +/* Test067: IPV4 filtering test, hash/cache invalidation on add test */ +/*----------------------------------------------------------------------------------------------*/ +class IpaFilteringBlockTest067 : public IpaFilteringBlockTest066 +{ +public: + IpaFilteringBlockTest067() + { + m_name = "IpaFilteringBlockTest067"; + m_description = + "Filtering block test 067 - this test first perfroms test 066 and then commits another rule\ + another identical packet is sent: DST_IP == 127.0.0.1 and expected to get cache miss"; + m_minIPAHwType = IPA_HW_v3_0; + } + + bool Run() + { + bool res = false; + bool isSuccess = false; + + printf("Entering %s, %s()\n",__FUNCTION__, __FILE__); + + // Add the relevant filtering rules + res = AddRules(); + if (false == res) { + printf("Failed adding filtering rules.\n"); + return false; + } + + // Load input data (IP packet) from file + res = LoadFiles(m_IpaIPType); + if (false == res) { + printf("Failed loading files.\n"); + return false; + } + + res = ModifyPackets(); + if (false == res) { + printf("Failed to modify packets.\n"); + return false; + } + + // Send first packet + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send second packet + isSuccess = m_producer.SendData(m_sendBuffer2, m_sendSize2); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send third packet + isSuccess = m_producer.SendData(m_sendBuffer3, m_sendSize3); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Receive packets from the channels and compare results + isSuccess = ReceivePacketsAndCompare(); + + // untill here test 066 was run, now let's test the invalidation + + // commit the same rules again, this should clear the cache + res = AddRules(); + if (false == res) { + printf("Failed adding filtering rules.\n"); + return false; + } + + // send packet again + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) { + printf("SendData failure.\n"); + return false; + } + + // receive and verify that cache was missed + isSuccess = ReceiveAndCompareSpecial(); + + printf("Leaving %s, %s(), Returning %d\n",__FUNCTION__, __FILE__,isSuccess); + + return isSuccess; + } // Run() + +}; + +/*----------------------------------------------------------------------------------------------*/ +/* Test068: IPV4 filtering test, hash/cache invalidation on delete test */ +/*----------------------------------------------------------------------------------------------*/ +class IpaFilteringBlockTest068 : public IpaFilteringBlockTest066 +{ +public: + IpaFilteringBlockTest068() + { + m_name = "IpaFilteringBlockTest068"; + m_description = + "Filtering block test 068 - this test first perfroms test 066 and then removes last rule\ + another identical packet is sent: DST_IP == 127.0.0.1 and expected to get cache miss"; + m_minIPAHwType = IPA_HW_v3_0; + } + + bool Run() + { + bool res = false; + bool isSuccess = false; + + printf("Entering %s, %s()\n",__FUNCTION__, __FILE__); + + // Add the relevant filtering rules + res = AddRules(); + if (false == res) { + printf("Failed adding filtering rules.\n"); + return false; + } + + // Load input data (IP packet) from file + res = LoadFiles(m_IpaIPType); + if (false == res) { + printf("Failed loading files.\n"); + return false; + } + + res = ModifyPackets(); + if (false == res) { + printf("Failed to modify packets.\n"); + return false; + } + + // Send first packet + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send second packet + isSuccess = m_producer.SendData(m_sendBuffer2, m_sendSize2); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send third packet + isSuccess = m_producer.SendData(m_sendBuffer3, m_sendSize3); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Receive packets from the channels and compare results + isSuccess = ReceivePacketsAndCompare(); + + // until here test 066 was run, now let's test the invalidation + + // delete the last rule, this should clear the cache + res = RemoveLastRule(); + if (false == res) { + printf("Failed removing filtering rules.\n"); + return false; + } + + // send packet again + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) { + printf("SendData failure.\n"); + return false; + } + + // receive and verify that cache was missed + isSuccess = ReceiveAndCompareSpecial(); + + printf("Leaving %s, %s(), Returning %d\n",__FUNCTION__, __FILE__,isSuccess); + + return isSuccess; + } // Run() + +}; + +/*----------------------------------------------------------------------------------------------*/ +/* Test070: IPV6 filtering test, non hashed priority higher than hashed priority */ +/*----------------------------------------------------------------------------------------------*/ +class IpaFilteringBlockTest070 : public IpaFilteringBlockTest060 +{ +public: + + IpaFilteringBlockTest070() + { + m_name = "IpaFilteringBlockTest070"; + m_description = + "Filtering block test 070 - Rules prioritization hashable vs non-hashable rule, both rules match the same packet but non hashable has higher priority\ + 1. Generate and commit three routing tables. \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit three filtering rules: (DST & Mask Match). \ + All DST_IPv6 == 0x...AA traffic goes to routing table 0 - non hashable\ + All DST_IPv6 == 0x...AA traffic goes to routing table 1 - hashable\ + All DST_IPv6 == 0x...CC traffic goes to routing table 2 - non hashable - don't care for this specific test"; + m_minIPAHwType = IPA_HW_v3_0; + m_IpaIPType = IPA_IP_v6; + } + + virtual bool AddRules() + { + printf("Entering %s, %s()\n",__FUNCTION__, __FILE__); + + uint32_t Hndl0, Hndl1, Hndl2; + + if(!GetThreeIPv6BypassRoutingTables(&Hndl0,&Hndl1,&Hndl2)){ + printf("failed to get three IPV6 routing tables!\n"); + return false; + } + + IPAFilteringTable FilterTable0; + struct ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v6,IPA_CLIENT_TEST_PROD,false,3); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1,flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl=-1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action=IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.rt_tbl_hdl=Hndl0; //put here the handle corresponding to Routing Rule 0 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[0] = 0xFFFFFFFF;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[1] = 0xFFFFFFFF;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[2] = 0x00000000;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[3] = 0x000000FF;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr[0] = 0XFF020000; // Filter DST_IP + flt_rule_entry.rule.attrib.u.v6.dst_addr[1] = 0x00000000; + flt_rule_entry.rule.attrib.u.v6.dst_addr[2] = 0x11223344; + flt_rule_entry.rule.attrib.u.v6.dst_addr[3] = 0X556677AA; + flt_rule_entry.rule.hashable = 0; // non hashable + + printf ("flt_rule_entry was set successfully, preparing for insertion....\n"); + + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.1 + flt_rule_entry.rule.rt_tbl_hdl=Hndl1; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.u.v6.dst_addr[3] = 0X556677AA; + flt_rule_entry.rule.hashable = 1; // hashable + + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.2 + flt_rule_entry.rule.rt_tbl_hdl=Hndl2; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.attrib.u.v6.dst_addr[3] = 0X556677CC; + flt_rule_entry.rule.hashable = 0; // non hashable + + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + printf ("%s::Error Adding RuleTable(2) to Filtering, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(2)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(2)->status); + } + printf("Leaving %s, %s()\n",__FUNCTION__, __FILE__); + return true; + } + + virtual bool ModifyPackets() + { + // TODO: Add verification that we access only allocated addresses + // TODO: Fix this, doesn't match the Rule's Requirements + m_sendBuffer[DST_ADDR_LSB_OFFSET_IPV6] = 0xAA; + m_sendBuffer2[DST_ADDR_LSB_OFFSET_IPV6] = 0xAA; + m_sendBuffer3[DST_ADDR_LSB_OFFSET_IPV6] = 0xCC; + return true; + }// ModifyPacktes () + +}; + +/*----------------------------------------------------------------------------------------------*/ +/* Test071: IPV6 filtering test, hashed priority higher than non hashed priority + cache hit */ +/*----------------------------------------------------------------------------------------------*/ +class IpaFilteringBlockTest071: public IpaFilteringBlockTest061 +{ +public: + + IpaFilteringBlockTest071() + { + m_name = "IpaFilteringBlockTest071"; + m_description = + "Filtering block test 071 - Rules prioritization hashable vs non-hashable rule, both rules match the same packet but hashable has higher priority\ + two identical packets are sent and should be catched by the hashable rule, second one should be hit the cache\ + 1. Generate and commit three routing tables. \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit three filtering rules: (DST & Mask Match). \ + All DST_IPv6 == 0x...AA traffic goes to routing table 0 - hashable\ + All DST_IPv6 == 0x...AA traffic goes to routing table 1 - non hashable\ + All DST_IPv6 == 0x...CC traffic goes to routing table 2 - don't care for this specific test"; + m_minIPAHwType = IPA_HW_v3_0; + m_IpaIPType = IPA_IP_v6; + } + + virtual bool AddRules() + { + printf("Entering %s, %s()\n",__FUNCTION__, __FILE__); + + uint32_t Hndl0, Hndl1, Hndl2; + + if(!GetThreeIPv6BypassRoutingTables(&Hndl0,&Hndl1,&Hndl2)){ + printf("failed to get three IPV6 routing tables!\n"); + return false; + } + + IPAFilteringTable FilterTable0; + struct ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v6,IPA_CLIENT_TEST_PROD,false,3); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1,flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl=-1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action=IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.rt_tbl_hdl=Hndl0; //put here the handle corresponding to Routing Rule 0 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[0] = 0xFFFFFFFF;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[1] = 0xFFFFFFFF;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[2] = 0x00000000;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[3] = 0x000000FF;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr[0] = 0XFF020000; // Filter DST_IP + flt_rule_entry.rule.attrib.u.v6.dst_addr[1] = 0x00000000; + flt_rule_entry.rule.attrib.u.v6.dst_addr[2] = 0x11223344; + flt_rule_entry.rule.attrib.u.v6.dst_addr[3] = 0X556677AA; + flt_rule_entry.rule.hashable = 1; // hashable + + printf ("flt_rule_entry was set successfully, preparing for insertion....\n"); + + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.1 + flt_rule_entry.rule.rt_tbl_hdl=Hndl1; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.u.v6.dst_addr[3] = 0X556677AA; + flt_rule_entry.rule.hashable = 0; // non hashable + + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.2 + flt_rule_entry.rule.rt_tbl_hdl=Hndl2; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.attrib.u.v6.dst_addr[3] = 0X556677CC; + flt_rule_entry.rule.hashable = 0; // non hashable + + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + printf ("%s::Error Adding RuleTable(2) to Filtering, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(2)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(2)->status); + } + printf("Leaving %s, %s()\n",__FUNCTION__, __FILE__); + return true; + } + + virtual bool ModifyPackets() + { + // TODO: Add verification that we access only allocated addresses + // TODO: Fix this, doesn't match the Rule's Requirements + m_sendBuffer[DST_ADDR_LSB_OFFSET_IPV6] = 0xAA; + m_sendBuffer2[DST_ADDR_LSB_OFFSET_IPV6] = 0xAA; + m_sendBuffer3[DST_ADDR_LSB_OFFSET_IPV6] = 0xCC; + return true; + }// ModifyPacktes () + +}; + +/*----------------------------------------------------------------------------------------------*/ +/* Test072: IPV6 filtering test, hashed rule match, non hash doesn't match expect cache miss */ +/*----------------------------------------------------------------------------------------------*/ +class IpaFilteringBlockTest072 : public IpaFilteringBlockTest062 +{ +public: + + IpaFilteringBlockTest072() + { + m_name = "IpaFilteringBlockTest072"; + m_description = + "Filtering block test 072 - Rules prioritization hashable vs non-hashable rule, only hashable matches the packets\ + two packets with different tuple are sent and should match the hashable rule, no cache hit expected\ + 1. Generate and commit three routing tables. \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit three filtering rules: (DST & Mask Match). \ + All DST_IPv6 == 0x...BB traffic goes to routing table 0 - non hashable\ + All DST_IPv6 == 0x...AA traffic goes to routing table 1 - hashable\ + All DST_IPv6 == 0x...CC traffic goes to routing table 2 - don't care for this specific test\ + 3. send three packets:\ + DST_IP == 0x...AA port 546\ + DST_IP == 0x...AA port 547\ + DST_IP == 0x...CC"; + m_minIPAHwType = IPA_HW_v3_0; + m_IpaIPType = IPA_IP_v6; + + } + + virtual bool AddRules() + { + printf("Entering %s, %s()\n",__FUNCTION__, __FILE__); + + uint32_t Hndl0, Hndl1, Hndl2; + + if(!GetThreeIPv6BypassRoutingTables(&Hndl0,&Hndl1,&Hndl2)){ + printf("failed to get three IPV6 routing tables!\n"); + return false; + } + + IPAFilteringTable FilterTable0; + struct ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v6,IPA_CLIENT_TEST_PROD,false,3); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1,flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl=-1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action=IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.rt_tbl_hdl=Hndl0; //put here the handle corresponding to Routing Rule 0 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[0] = 0xFFFFFFFF;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[1] = 0xFFFFFFFF;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[2] = 0x00000000;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[3] = 0x000000FF;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr[0] = 0XFF020000; // Filter DST_IP + flt_rule_entry.rule.attrib.u.v6.dst_addr[1] = 0x00000000; + flt_rule_entry.rule.attrib.u.v6.dst_addr[2] = 0x11223344; + flt_rule_entry.rule.attrib.u.v6.dst_addr[3] = 0X556677BB; + flt_rule_entry.rule.hashable = 0; // non hashable + + printf ("flt_rule_entry was set successfully, preparing for insertion....\n"); + + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.1 + flt_rule_entry.rule.rt_tbl_hdl=Hndl1; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.u.v6.dst_addr[3] = 0X556677AA; + flt_rule_entry.rule.hashable = 1; // hashable + + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.2 + flt_rule_entry.rule.rt_tbl_hdl=Hndl2; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.attrib.u.v6.dst_addr[3] = 0X556677CC; + flt_rule_entry.rule.hashable = 0; // non hashable + + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + printf ("%s::Error Adding RuleTable(2) to Filtering, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(2)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(2)->status); + } + printf("Leaving %s, %s()\n",__FUNCTION__, __FILE__); + return true; + } + + virtual bool ModifyPackets() + { + + unsigned short port; + + m_sendBuffer[DST_ADDR_LSB_OFFSET_IPV6] = 0xAA; + port = ntohs(546);//DHCP Client Port + memcpy (&m_sendBuffer[IPV6_DST_PORT_OFFSET], &port, sizeof(port)); + + port = ntohs(547);//DHCP Client Port + memcpy (&m_sendBuffer2[IPV6_DST_PORT_OFFSET], &port, sizeof(port)); + m_sendBuffer2[DST_ADDR_LSB_OFFSET_IPV6] = 0xAA; + + m_sendBuffer3[DST_ADDR_LSB_OFFSET_IPV6] = 0xCC; + return true; + }// ModifyPacktes () + +}; + +/*----------------------------------------------------------------------------------------------*/ +/* Test073: IPV4 filtering test, hashed rule match, non hash doesn't match expect cache miss */ +/*----------------------------------------------------------------------------------------------*/ +class IpaFilteringBlockTest073 : public IpaFilteringBlockTest063 +{ +public: + + IpaFilteringBlockTest073() + { + m_name = "IpaFilteringBlockTest073"; + m_description = + "Filtering block test 073 - Rules prioritization hashable vs non-hashable rule, only hashable matches the packets\ + two packets with different tuple are sent and should match the hashable rule, no cache hit expected\ + 1. Generate and commit three routing tables. \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit three filtering rules: (DST & Mask Match). \ + All DST_IPv6 == 0x...AA traffic goes to routing table 0 - hashable\ + All DST_IPv6 == 0x...BB traffic goes to routing table 1 - non hashable\ + All DST_IPv6 == 0x...CC traffic goes to routing table 2 - don't care for this specific test\ + 3. send three packets:\ + DST_IP == 0x...AA port 546\ + DST_IP == 0x...AA port 547\ + DST_IP == 0x...CC"; + + m_minIPAHwType = IPA_HW_v3_0; + m_IpaIPType = IPA_IP_v6; + } + + virtual bool AddRules() + { + printf("Entering %s, %s()\n",__FUNCTION__, __FILE__); + + uint32_t Hndl0, Hndl1, Hndl2; + + if(!GetThreeIPv6BypassRoutingTables(&Hndl0,&Hndl1,&Hndl2)){ + printf("failed to get three IPV6 routing tables!\n"); + return false; + } + + IPAFilteringTable FilterTable0; + struct ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v6,IPA_CLIENT_TEST_PROD,false,3); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1,flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl=-1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action=IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.rt_tbl_hdl=Hndl0; //put here the handle corresponding to Routing Rule 0 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[0] = 0xFFFFFFFF;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[1] = 0xFFFFFFFF;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[2] = 0x00000000;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[3] = 0x000000FF;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr[0] = 0XFF020000; // Filter DST_IP + flt_rule_entry.rule.attrib.u.v6.dst_addr[1] = 0x00000000; + flt_rule_entry.rule.attrib.u.v6.dst_addr[2] = 0x11223344; + flt_rule_entry.rule.attrib.u.v6.dst_addr[3] = 0X556677AA; + flt_rule_entry.rule.hashable = 1; // hashable + + printf ("flt_rule_entry was set successfully, preparing for insertion....\n"); + + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.1 + flt_rule_entry.rule.rt_tbl_hdl=Hndl1; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.u.v6.dst_addr[3] = 0X556677BB; + flt_rule_entry.rule.hashable = 0; // non hashable + + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.2 + flt_rule_entry.rule.rt_tbl_hdl=Hndl2; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.attrib.u.v6.dst_addr[3] = 0X556677CC; + flt_rule_entry.rule.hashable = 0; // non hashable + + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + printf ("%s::Error Adding RuleTable(2) to Filtering, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(2)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(2)->status); + } + printf("Leaving %s, %s()\n",__FUNCTION__, __FILE__); + return true; + } + + virtual bool ModifyPackets() + { + + unsigned short port; + + m_sendBuffer[DST_ADDR_LSB_OFFSET_IPV6] = 0xAA; + port = ntohs(546);//DHCP Client Port + memcpy (&m_sendBuffer[IPV6_DST_PORT_OFFSET], &port, sizeof(port)); + + port = ntohs(547);//DHCP Client Port + memcpy (&m_sendBuffer2[IPV6_DST_PORT_OFFSET], &port, sizeof(port)); + m_sendBuffer2[DST_ADDR_LSB_OFFSET_IPV6] = 0xAA; + + m_sendBuffer3[DST_ADDR_LSB_OFFSET_IPV6] = 0xCC; + return true; + }// ModifyPacktes () +}; + +/*----------------------------------------------------------------------------------------------*/ +/* Test074: IPV6 filtering test, hashed rule match, non hash doesn't match expect cache hit */ +/*----------------------------------------------------------------------------------------------*/ +class IpaFilteringBlockTest074 : public IpaFilteringBlockTest064 +{ +public: + + IpaFilteringBlockTest074() + { + m_name = "IpaFilteringBlockTest074"; + m_description = + "Filtering block test 074 - Rules prioritization hashable vs non-hashable rule, only hashable matches the packets\ + two identical packets are sent and should match the hashable rule, cache hit expected\ + 1. Generate and commit three routing tables. \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit three filtering rules: (DST & Mask Match). \ + All DST_IPv6 == 0x...BB traffic goes to routing table 0 - non hashable\ + All DST_IPv6 == 0x...AA traffic goes to routing table 1 - hashable\ + All DST_IPv6 == 0x...CC traffic goes to routing table 2 - don't care for this specific test\ + 3. send three packets:\ + DST_IP == 0x...AA \ + DST_IP == 0x...AA \ + DST_IP == 0x...CC"; + m_minIPAHwType = IPA_HW_v3_0; + m_IpaIPType = IPA_IP_v6; + } + + virtual bool AddRules() + { + printf("Entering %s, %s()\n",__FUNCTION__, __FILE__); + + uint32_t Hndl0, Hndl1, Hndl2; + + if(!GetThreeIPv6BypassRoutingTables(&Hndl0,&Hndl1,&Hndl2)){ + printf("failed to get three IPV6 routing tables!\n"); + return false; + } + + IPAFilteringTable FilterTable0; + struct ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v6,IPA_CLIENT_TEST_PROD,false,3); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1,flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl=-1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action=IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.rt_tbl_hdl=Hndl0; //put here the handle corresponding to Routing Rule 0 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[0] = 0xFFFFFFFF;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[1] = 0xFFFFFFFF;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[2] = 0x00000000;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[3] = 0x000000FF;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr[0] = 0XFF020000; // Filter DST_IP + flt_rule_entry.rule.attrib.u.v6.dst_addr[1] = 0x00000000; + flt_rule_entry.rule.attrib.u.v6.dst_addr[2] = 0x11223344; + flt_rule_entry.rule.attrib.u.v6.dst_addr[3] = 0X556677BB; + flt_rule_entry.rule.hashable = 0; // non hashable + + printf ("flt_rule_entry was set successfully, preparing for insertion....\n"); + + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.1 + flt_rule_entry.rule.rt_tbl_hdl=Hndl1; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.u.v6.dst_addr[3] = 0X556677AA; + flt_rule_entry.rule.hashable = 1; // hashable + + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.2 + flt_rule_entry.rule.rt_tbl_hdl=Hndl2; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.attrib.u.v6.dst_addr[3] = 0X556677CC; + flt_rule_entry.rule.hashable = 0; // non hashable + + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + printf ("%s::Error Adding RuleTable(2) to Filtering, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(2)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(2)->status); + } + printf("Leaving %s, %s()\n",__FUNCTION__, __FILE__); + return true; + } + + virtual bool ModifyPackets() + { + + m_sendBuffer[DST_ADDR_LSB_OFFSET_IPV6] = 0xAA; + m_sendBuffer2[DST_ADDR_LSB_OFFSET_IPV6] = 0xAA; + m_sendBuffer3[DST_ADDR_LSB_OFFSET_IPV6] = 0xCC; + return true; + }// ModifyPacktes () + +}; + +/*----------------------------------------------------------------------------------------------*/ +/* Test075: IPV6 filtering test, non hashable rule match with max priority vs hashable */ +/*----------------------------------------------------------------------------------------------*/ +class IpaFilteringBlockTest075 : public IpaFilteringBlockTest065 +{ +public: + + IpaFilteringBlockTest075() + { + m_name = "IpaFilteringBlockTest075"; + m_description = + "Filtering block test 075 - Rules prioritization hashable vs non-hashable rule, both rules match the packets\ + two identical packets are sent, non hashed with max priority should catch both\ + 1. Generate and commit three routing tables. \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit three filtering rules: (DST & Mask Match). \ + All DST_IPv6 == 0x...AA traffic goes to routing table 0 - hashable\ + All DST_IPv6 == 0x...AA traffic goes to routing table 1 - non hashable max prio\ + All DST_IPv6 == 0x...CC traffic goes to routing table 2 - don't care for this specific test\ + 3. send three packets:\ + DST_IP == 0x...AA \ + DST_IP == 0x...AA \ + DST_IP == 0x...CC"; + m_minIPAHwType = IPA_HW_v3_0; + m_IpaIPType = IPA_IP_v6; + } + + virtual bool AddRules() + { + printf("Entering %s, %s()\n",__FUNCTION__, __FILE__); + + uint32_t Hndl0, Hndl1, Hndl2; + + if(!GetThreeIPv6BypassRoutingTables(&Hndl0,&Hndl1,&Hndl2)){ + printf("failed to get three IPV6 routing tables!\n"); + return false; + } + + IPAFilteringTable FilterTable0; + struct ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v6,IPA_CLIENT_TEST_PROD,false,3); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1,flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl=-1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action=IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.rt_tbl_hdl=Hndl0; //put here the handle corresponding to Routing Rule 0 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[0] = 0xFFFFFFFF;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[1] = 0xFFFFFFFF;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[2] = 0x00000000;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[3] = 0x000000FF;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr[0] = 0XFF020000; // Filter DST_IP + flt_rule_entry.rule.attrib.u.v6.dst_addr[1] = 0x00000000; + flt_rule_entry.rule.attrib.u.v6.dst_addr[2] = 0x11223344; + flt_rule_entry.rule.attrib.u.v6.dst_addr[3] = 0X556677AA; + flt_rule_entry.rule.hashable = 1; // hashable + + printf ("flt_rule_entry was set successfully, preparing for insertion....\n"); + + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.1 + flt_rule_entry.rule.rt_tbl_hdl=Hndl1; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.u.v6.dst_addr[3] = 0X556677AA; + flt_rule_entry.rule.hashable = 0; // non hashable + flt_rule_entry.rule.max_prio = 1; // max priority + + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.2 + flt_rule_entry.rule.rt_tbl_hdl=Hndl2; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.attrib.u.v6.dst_addr[3] = 0X556677CC; + flt_rule_entry.rule.hashable = 0; // non hashable + + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + printf ("%s::Error Adding RuleTable(2) to Filtering, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(2)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(2)->status); + } + printf("Leaving %s, %s()\n",__FUNCTION__, __FILE__); + return true; + } + + virtual bool ModifyPackets() + { + + m_sendBuffer[DST_ADDR_LSB_OFFSET_IPV6] = 0xAA; + m_sendBuffer2[DST_ADDR_LSB_OFFSET_IPV6] = 0xAA; + m_sendBuffer3[DST_ADDR_LSB_OFFSET_IPV6] = 0xCC; + return true; + }// ModifyPacktes () +}; + +/*----------------------------------------------------------------------------------------------*/ +/* Test076: IPV6 filtering test, hashed rule match, non hash doesn't match expect cache hit */ +/*----------------------------------------------------------------------------------------------*/ + +class IpaFilteringBlockTest076 : public IpaFilteringBlockTest066 +{ +public: + + bool IsSecondTime; + + IpaFilteringBlockTest076() :IsSecondTime(false) + { + m_name = "IpaFilteringBlockTest076"; + m_description = + "Filtering block test 076 - Rules prioritization hashable vs non-hashable rule, only hashable matches the packets\ + two identical packets are sent and should match the hashable rule, cache hit expected\ + 1. Generate and commit three routing tables. \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit three filtering rules: (DST & Mask Match). \ + All DST_IPv6 == 0x...AA traffic goes to routing table 0 - hashable\ + All DST_IPv6 == 0x...BB traffic goes to routing table 1 - non hashable\ + All DST_IPv6 == 0x...CC traffic goes to routing table 2 - don't care for this specific test\ + 3. send three packets:\ + DST_IP == 0x...AA \ + DST_IP == 0x...AA \ + DST_IP == 0x...CC"; + m_minIPAHwType = IPA_HW_v3_0; + m_IpaIPType = IPA_IP_v6; + } + + virtual bool AddRules() + { + printf("Entering %s, %s()\n",__FUNCTION__, __FILE__); + + uint32_t Hndl0, Hndl1, Hndl2; + + if(!GetThreeIPv6BypassRoutingTables(&Hndl0,&Hndl1,&Hndl2)){ + printf("failed to get three IPV6 routing tables!\n"); + return false; + } + + struct ipa_flt_rule_add flt_rule_entry; + if (!IsSecondTime) { + FilterTable0.Init(IPA_IP_v6, IPA_CLIENT_TEST_PROD, false, 3); + IsSecondTime = true; + + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1, flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl = -1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action = IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.rt_tbl_hdl = Hndl0; //put here the handle corresponding to Routing Rule 0 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[0] = 0xFFFFFFFF;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[1] = 0xFFFFFFFF;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[2] = 0x00000000;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[3] = 0x000000FF;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr[0] = 0XFF020000; // Filter DST_IP + flt_rule_entry.rule.attrib.u.v6.dst_addr[1] = 0x00000000; + flt_rule_entry.rule.attrib.u.v6.dst_addr[2] = 0x11223344; + flt_rule_entry.rule.attrib.u.v6.dst_addr[3] = 0X556677AA; + flt_rule_entry.rule.hashable = 1; // hashable + + printf("flt_rule_entry was set successfully, preparing for insertion....\n"); + + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) { + printf("%s::Error Adding Rule to Filter Table, aborting...\n", __FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.1 + flt_rule_entry.rule.rt_tbl_hdl = Hndl1; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.u.v6.dst_addr[3] = 0X556677BB; + flt_rule_entry.rule.hashable = 0; // non hashable + + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) { + printf("%s::Error Adding Rule to Filter Table, aborting...\n", __FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.2 + flt_rule_entry.rule.rt_tbl_hdl = Hndl2; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.attrib.u.v6.dst_addr[3] = 0X556677CC; + flt_rule_entry.rule.hashable = 0; // non hashable + + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) { + printf("%s::Error Adding RuleTable(2) to Filtering, aborting...\n", __FUNCTION__); + return false; + } else { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(2)->flt_rule_hdl, FilterTable0.ReadRuleFromTable(2)->status); + } + } else { + printf("in the second time, just commit again\n"); + if (!m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable())) { + printf("%s::Error commiting rules second time, aborting...\n", __FUNCTION__); + return false; + } + } + printf("Leaving %s, %s()\n",__FUNCTION__, __FILE__); + return true; + } + + bool RemoveLastRule() + { + struct ipa_ioc_del_flt_rule *pDeleteRule = (struct ipa_ioc_del_flt_rule *) + calloc(1, sizeof(struct ipa_ioc_del_flt_rule) + sizeof(struct ipa_flt_rule_del)); + + pDeleteRule->commit = 1; + pDeleteRule->ip = IPA_IP_v6; + pDeleteRule->num_hdls = 1; + pDeleteRule->hdl[0].hdl = FilterTable0.ReadRuleFromTable(2)->flt_rule_hdl; + pDeleteRule->hdl[0].status = FilterTable0.ReadRuleFromTable(2)->status; + + if (!m_filtering.DeleteFilteringRule(pDeleteRule)) + { + printf ("%s::Error Deleting Rule from Filter Table, aborting...\n",__FUNCTION__); + return false; + } + + return true; + } + + virtual bool ModifyPackets() + { + + m_sendBuffer[DST_ADDR_LSB_OFFSET_IPV6] = 0xAA; + m_sendBuffer2[DST_ADDR_LSB_OFFSET_IPV6] = 0xAA; + m_sendBuffer3[DST_ADDR_LSB_OFFSET_IPV6] = 0xCC; + return true; + }// ModifyPacktes () + +private: + IPAFilteringTable FilterTable0; +}; + +/*----------------------------------------------------------------------------------------------*/ +/* Test077: IPV6 filtering test, hash/cache invalidation on add test */ +/*----------------------------------------------------------------------------------------------*/ +class IpaFilteringBlockTest077 : public IpaFilteringBlockTest076 +{ +public: + IpaFilteringBlockTest077() + { + m_name = "IpaFilteringBlockTest077"; + m_description = + "Filtering block test 077 - this test first perfroms test 076 and then commits another rule\ + another identical packet is sent: DST_IP == 127.0.0.1 and expected to get cache miss"; + m_minIPAHwType = IPA_HW_v3_0; + m_IpaIPType = IPA_IP_v6; + } + + bool Run() + { + bool res = false; + bool isSuccess = false; + + printf("Entering %s, %s()\n",__FUNCTION__, __FILE__); + + // Add the relevant filtering rules + res = AddRules(); + if (false == res) { + printf("Failed adding filtering rules.\n"); + return false; + } + + // Load input data (IP packet) from file + res = LoadFiles(m_IpaIPType); + if (false == res) { + printf("Failed loading files.\n"); + return false; + } + + res = ModifyPackets(); + if (false == res) { + printf("Failed to modify packets.\n"); + return false; + } + + // Send first packet + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send second packet + isSuccess = m_producer.SendData(m_sendBuffer2, m_sendSize2); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send third packet + isSuccess = m_producer.SendData(m_sendBuffer3, m_sendSize3); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Receive packets from the channels and compare results + isSuccess = ReceivePacketsAndCompare(); + + // until here test 076 was run, now let's test the invalidation + + // commit the same rules again, this should clear the cache + res = AddRules(); + if (false == res) { + printf("Failed adding filtering rules.\n"); + return false; + } + + // send packet again + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) { + printf("SendData failure.\n"); + return false; + } + + // receive and verify that cache was missed + isSuccess = ReceiveAndCompareSpecial(); + + printf("Leaving %s, %s(), Returning %d\n",__FUNCTION__, __FILE__,isSuccess); + + return isSuccess; + } // Run() + +}; + +/*----------------------------------------------------------------------------------------------*/ +/* Test078: IPV6 filtering test, hash/cache invalidation on add test */ +/*----------------------------------------------------------------------------------------------*/ +class IpaFilteringBlockTest078 : public IpaFilteringBlockTest076 +{ +public: + IpaFilteringBlockTest078() + { + m_name = "IpaFilteringBlockTest078"; + m_description = + "Filtering block test 078 - this test first perfroms test 076 and then removes last rule\ + another identical packet is sent: DST_IP == 127.0.0.1 and expected to get cache miss"; + m_minIPAHwType = IPA_HW_v3_0; + m_IpaIPType = IPA_IP_v6; + } + + bool Run() + { + bool res = false; + bool isSuccess = false; + + printf("Entering %s, %s()\n",__FUNCTION__, __FILE__); + + // Add the relevant filtering rules + res = AddRules(); + if (false == res) { + printf("Failed adding filtering rules.\n"); + return false; + } + + // Load input data (IP packet) from file + res = LoadFiles(m_IpaIPType); + if (false == res) { + printf("Failed loading files.\n"); + return false; + } + + res = ModifyPackets(); + if (false == res) { + printf("Failed to modify packets.\n"); + return false; + } + + // Send first packet + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send second packet + isSuccess = m_producer.SendData(m_sendBuffer2, m_sendSize2); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send third packet + isSuccess = m_producer.SendData(m_sendBuffer3, m_sendSize3); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Receive packets from the channels and compare results + isSuccess = ReceivePacketsAndCompare(); + + // until here test 076 was run, now let's test the invalidation + + // delete the last rule, this should clear the cache + res = RemoveLastRule(); + if (false == res) { + printf("Failed removing filtering rules.\n"); + return false; + } + + // send packet again + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) { + printf("SendData failure.\n"); + return false; + } + + // receive and verify that cache was missed + isSuccess = ReceiveAndCompareSpecial(); + + printf("Leaving %s, %s(), Returning %d\n",__FUNCTION__, __FILE__,isSuccess); + + return isSuccess; + } // Run() + +}; + +/*---------------------------------------------------------------------------*/ +/* Test081: Type-of-service IP header field match */ +/*---------------------------------------------------------------------------*/ +class IpaFilteringBlockTest081 : public IpaFilteringBlockTestFixture +{ +public: + IpaFilteringBlockTest081() + { + m_name = "IpaFilteringBlockTest081"; + m_description = " \ + Filtering block test 081 - Source and Destination address and TOS exact match (End-Point specific Filtering Table, Insert all rules in a single commit) \ + 1. Generate and commit three routing tables. \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit Three filtering rules: \ + All DST_IP == (127.0.0.1 & 255.0.0.255) and TOS == 0xFB traffic goes to routing table 0 \ + All DST_IP == (192.168.1.1 & 255.0.0.255) and TOS == 0x10 traffic goes to routing table 1 \ + All DST_IP == (192.168.1.2 & 255.0.0.255) and SRC_IP == (192.168.1.FF & 255.0.0.255) TOS == 0x25 traffic goes to routing table 2"; + m_IpaIPType = IPA_IP_v4; + Register(*this); + } + + virtual bool AddRules() + { + printf("Entering %s, %s()\n",__FUNCTION__, __FILE__); + + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + struct ipa_ioc_get_rt_tbl routing_table0,routing_table1,routing_table2; + + if (!CreateThreeIPv4BypassRoutingTables (bypass0,bypass1,bypass2)) + { + printf("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + + printf("CreateThreeBypassRoutingTables completed successfully\n"); + routing_table0.ip = IPA_IP_v4; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + printf("m_routing.GetRoutingTable(&routing_table0=0x%p) Failed.\n",&routing_table0); + return false; + } + printf("%s route table handle = %u\n", bypass0, routing_table0.hdl); + + routing_table1.ip = IPA_IP_v4; + strlcpy(routing_table1.name, bypass1, sizeof(routing_table1.name)); + if (!m_routing.GetRoutingTable(&routing_table1)) + { + printf("m_routing.GetRoutingTable(&routing_table1=0x%p) Failed.\n",&routing_table1); + return false; + } + printf("%s route table handle = %u\n", bypass1, routing_table1.hdl); + + routing_table2.ip = IPA_IP_v4; + strlcpy(routing_table2.name, bypass2, sizeof(routing_table2.name)); + if (!m_routing.GetRoutingTable(&routing_table2)) + { + printf("m_routing.GetRoutingTable(&routing_table2=0x%p) Failed.\n",&routing_table2); + return false; + } + printf("%s route table handle = %u\n", bypass2, routing_table2.hdl); + + IPAFilteringTable FilterTable0; + struct ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v4,IPA_CLIENT_TEST_PROD,false,3); + printf("FilterTable*.Init Completed Successfully..\n"); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1,flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl=-1; // out param + flt_rule_entry.status = -1; // out param + flt_rule_entry.rule.action=IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.rt_tbl_hdl=routing_table0.hdl; + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR | IPA_FLT_TOS; + flt_rule_entry.rule.attrib.u.v4.dst_addr_mask = 0xFF0000FF; // Mask + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0x7F000001; // Filter DST_IP == 127.0.0.1 + flt_rule_entry.rule.attrib.u.v4.tos = 0xFB; + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.1 + flt_rule_entry.rule.rt_tbl_hdl=routing_table1.hdl; + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0xC0A80101; // Filter DST_IP == 192.168.1.1 + flt_rule_entry.rule.attrib.u.v4.tos = 0x10; + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.2 + flt_rule_entry.rule.rt_tbl_hdl=routing_table2.hdl; + flt_rule_entry.rule.attrib.attrib_mask |= IPA_FLT_SRC_ADDR; + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0xC0A80102; // Filter DST_IP == 192.168.1.2 + flt_rule_entry.rule.attrib.u.v4.src_addr_mask = 0xFF0000FF; // Mask + flt_rule_entry.rule.attrib.u.v4.src_addr = 0xC0A801FF; // Filter DST_IP == 192.168.1.255 + flt_rule_entry.rule.attrib.u.v4.tos = 0x25; + + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(0)->status); + printf("flt rule hdl1=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(1)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(1)->status); + printf("flt rule hdl2=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(2)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(2)->status); + } + + printf("Leaving %s, %s()\n",__FUNCTION__, __FILE__); + return true; + }// AddRules() + + virtual bool ModifyPackets() + { + int address; + address = ntohl(0x7F000001);//127.0.0.1 + memcpy(&m_sendBuffer[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + m_sendBuffer[IP4_TOS_FIELD_OFFSET] = 0xFB; + + address = ntohl(0xC0A80101);//192.168.1.1 + memcpy(&m_sendBuffer2[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + m_sendBuffer2[IP4_TOS_FIELD_OFFSET] = 0x10; + + address = ntohl(0xC0A80102);//192.168.1.2 + memcpy(&m_sendBuffer3[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + address = ntohl(0xC0A801FF);//192.168.1.255 + memcpy(&m_sendBuffer3[IPV4_SRC_ADDR_OFFSET], &address, sizeof(address)); + m_sendBuffer3[IP4_TOS_FIELD_OFFSET] = 0x25; + + return true; + }// ModifyPacktes () +}; + +/*---------------------------------------------------------------------------*/ +/* Test082: Pure Ack packet match */ +/*---------------------------------------------------------------------------*/ +class IpaFilteringBlockTest082 : public IpaFilteringBlockTestFixture +{ +public: + IpaFilteringBlockTest082() + { + m_name = "IpaFilteringBlockTest082"; + m_description = " \ + Filtering block test 082 - Pure Ack packet match \ + 1. Generate and commit three routing tables. \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit Three filtering rules: \ + All IS_PURE_ACK traffic goes to routing table 0 \ + All DST_IP == (192.168.1.5 & 255.0.0.255) goes to routing table 1\ + All other traffic goes to routing table 2"; + m_IpaIPType = IPA_IP_v4; + m_minIPAHwType = IPA_HW_v4_5; + Register(*this); + } + + virtual bool AddRules() + { + printf("Entering %s, %s()\n",__FUNCTION__, __FILE__); + + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + struct ipa_ioc_get_rt_tbl routing_table0,routing_table1,routing_table2; + + if (!CreateThreeIPv4BypassRoutingTables (bypass0,bypass1,bypass2)) + { + printf("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + + printf("CreateThreeBypassRoutingTables completed successfully\n"); + routing_table0.ip = IPA_IP_v4; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + printf("m_routing.GetRoutingTable(&routing_table0=0x%p) Failed.\n",&routing_table0); + return false; + } + printf("%s route table handle = %u\n", bypass0, routing_table0.hdl); + + routing_table1.ip = IPA_IP_v4; + strlcpy(routing_table1.name, bypass1, sizeof(routing_table1.name)); + if (!m_routing.GetRoutingTable(&routing_table1)) + { + printf("m_routing.GetRoutingTable(&routing_table1=0x%p) Failed.\n",&routing_table1); + return false; + } + printf("%s route table handle = %u\n", bypass1, routing_table1.hdl); + + routing_table2.ip = IPA_IP_v4; + strlcpy(routing_table2.name, bypass2, sizeof(routing_table2.name)); + if (!m_routing.GetRoutingTable(&routing_table2)) + { + printf("m_routing.GetRoutingTable(&routing_table2=0x%p) Failed.\n",&routing_table2); + return false; + } + printf("%s route table handle = %u\n", bypass2, routing_table2.hdl); + + IPAFilteringTable FilterTable0; + struct ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v4,IPA_CLIENT_TEST_PROD,false,3); + printf("FilterTable*.Init Completed Successfully..\n"); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1,flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl=-1; // out param + flt_rule_entry.status = -1; // out param + flt_rule_entry.rule.action=IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.rt_tbl_hdl=routing_table0.hdl; + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_IS_PURE_ACK; + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.1 + flt_rule_entry.rule.rt_tbl_hdl=routing_table1.hdl; + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0xC0A80105; // Filter DST_IP == 192.168.1.5 + flt_rule_entry.rule.attrib.u.v4.dst_addr_mask = 0xFF0000FF; // Mask + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.2 + flt_rule_entry.rule.rt_tbl_hdl=routing_table2.hdl; + flt_rule_entry.rule.attrib.attrib_mask = 0; + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(0)->status); + printf("flt rule hdl1=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(1)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(1)->status); + printf("flt rule hdl2=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(2)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(2)->status); + } + + printf("Leaving %s, %s()\n",__FUNCTION__, __FILE__); + return true; + } + + virtual bool LoadFiles(enum ipa_ip_type ip) + { + string fileName; + + if (!LoadNoPayloadPacket(ip, m_sendBuffer, m_sendSize)) { + LOG_MSG_ERROR("Failed loading no payload Packet\n"); + return false; + } + printf ("Loaded %zu Bytes to m_sendBuffer\n",m_sendSize); + + if (!LoadNoPayloadPacket(ip, m_sendBuffer2, m_sendSize2)) { + LOG_MSG_ERROR("Failed loading no payload Packet\n"); + return false; + } + printf ("Loaded %zu Bytes to m_sendBuffer2\n",m_sendSize2); + + if (!LoadDefaultPacket(ip, m_extHdrType, m_sendBuffer3, m_sendSize3)) { + LOG_MSG_ERROR("Failed loading default Packet\n"); + return false; + } + printf ("Loaded %zu Bytes to m_sendBuffer3\n",m_sendSize3); + + return true; + } + + virtual bool ModifyPackets() + { + int address; + + m_sendBuffer[IPv4_TCP_FLAGS_OFFSET] |= TCP_ACK_FLAG_MASK; + address = ntohl(0xC0A80105);//192.168.1.5 + memcpy(&m_sendBuffer[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + + address = ntohl(0xC0A80105);//192.168.1.5 + memcpy(&m_sendBuffer2[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + + m_sendBuffer3[IPv4_TCP_FLAGS_OFFSET] |= TCP_ACK_FLAG_MASK; + return true; + }// ModifyPacktes () +}; + +/*---------------------------------------------------------------------------*/ +/* Test090: VLAN ID filtering - IPv4 */ +/*---------------------------------------------------------------------------*/ +class IpaFilteringBlockTest090 : public IpaFilteringBlockTestFixture +{ +public: + IpaFilteringBlockTest090() + { + m_name = "IpaFilteringBlockTest090"; + m_description = " \ + Filtering block test 090 - VLAN ID packet match - IPv4 \ + 1. Generate and commit three routing tables. \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit Three filtering rules: \ + All VLAN ID == 5 goes to routing table 0 \ + All VLAN ID == 6 goes to routing table 1\ + All other traffic goes to routing table 2"; + m_IpaIPType = IPA_IP_v4; + m_minIPAHwType = IPA_HW_v4_0; + Register(*this); + } + + virtual bool AddRules() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + struct ipa_ioc_get_rt_tbl routing_table0, routing_table1, routing_table2; + + if (!CreateThreeIPv4BypassRoutingTables(bypass0, bypass1, bypass2)) { + printf("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + + printf("CreateThreeBypassRoutingTables completed successfully\n"); + routing_table0.ip = IPA_IP_v4; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) { + printf("m_routing.GetRoutingTable(&routing_table0=0x%p) Failed.\n", &routing_table0); + return false; + } + printf("%s route table handle = %u\n", bypass0, routing_table0.hdl); + + routing_table1.ip = IPA_IP_v4; + strlcpy(routing_table1.name, bypass1, sizeof(routing_table1.name)); + if (!m_routing.GetRoutingTable(&routing_table1)) { + printf("m_routing.GetRoutingTable(&routing_table1=0x%p) Failed.\n", &routing_table1); + return false; + } + printf("%s route table handle = %u\n", bypass1, routing_table1.hdl); + + routing_table2.ip = IPA_IP_v4; + strlcpy(routing_table2.name, bypass2, sizeof(routing_table2.name)); + if (!m_routing.GetRoutingTable(&routing_table2)) { + printf("m_routing.GetRoutingTable(&routing_table2=0x%p) Failed.\n", &routing_table2); + return false; + } + printf("%s route table handle = %u\n", bypass2, routing_table2.hdl); + + // note here we are using the VLAN pipe TEST2_PROD + IPAFilteringTable FilterTable0; + struct ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v4, IPA_CLIENT_TEST2_PROD, false, 3); + printf("FilterTable*.Init Completed Successfully..\n"); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1, flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl = -1; // out param + flt_rule_entry.status = -1; // out param + flt_rule_entry.rule.action = IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.retain_hdr = 1; // retain header so we can compare the VID + flt_rule_entry.rule.rt_tbl_hdl = routing_table0.hdl; + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_VLAN_ID; + flt_rule_entry.rule.attrib.vlan_id = 5; //filter all packets with vlan id == 5 + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) { + printf("%s::Error Adding Rule to Filter Table, aborting...\n", __FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.1 + flt_rule_entry.rule.rt_tbl_hdl = routing_table1.hdl; + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_VLAN_ID; + flt_rule_entry.rule.attrib.vlan_id = 6; //filter all packets with vlan id == 6 + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) { + printf("%s::Error Adding Rule to Filter Table, aborting...\n", __FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.2 + flt_rule_entry.rule.rt_tbl_hdl = routing_table2.hdl; + flt_rule_entry.rule.attrib.attrib_mask = 0; + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) { + printf("%s::Error Adding Rule to Filter Table, aborting...\n", __FUNCTION__); + return false; + } else { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl, FilterTable0.ReadRuleFromTable(0)->status); + printf("flt rule hdl1=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(1)->flt_rule_hdl, FilterTable0.ReadRuleFromTable(1)->status); + printf("flt rule hdl2=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(2)->flt_rule_hdl, FilterTable0.ReadRuleFromTable(2)->status); + } + + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return true; + } + + virtual bool LoadFiles(enum ipa_ip_type ip) + { + string fileName; + if (!LoadDefault802_1Q(ip, m_sendBuffer, m_sendSize)) { + LOG_MSG_ERROR("Failed loading first VLAN Packet\n"); + return false; + } + printf("Loaded %zu Bytes to m_sendBuffer\n", m_sendSize); + + if (!LoadDefault802_1Q(ip, m_sendBuffer2, m_sendSize2)) { + LOG_MSG_ERROR("Failed loading second VLAN Packet\n"); + return false; + } + printf("Loaded %zu Bytes to m_sendBuffer2\n", m_sendSize2); + + if (!LoadDefault802_1Q(ip, m_sendBuffer3, m_sendSize3)) { + LOG_MSG_ERROR("Failed loading default Packet\n"); + return false; + } + printf("Loaded %zu Bytes to m_sendBuffer3\n", m_sendSize3); + + return true; + } + + virtual bool ModifyPackets() + { + uint32_t vlan_802_1Q_tag; + + vlan_802_1Q_tag = ntohl(0x81002005); //VLAN ID == 5 + memcpy(&m_sendBuffer[TAG_802_1Q_OFFSET], &vlan_802_1Q_tag, sizeof(vlan_802_1Q_tag)); + + vlan_802_1Q_tag = ntohl(0x81002006); //VLAN ID == 6 + memcpy(&m_sendBuffer2[TAG_802_1Q_OFFSET], &vlan_802_1Q_tag, sizeof(vlan_802_1Q_tag)); + + // default packet has vlan id == 3, assign it anyway + vlan_802_1Q_tag = ntohl(0x81002003); //VLAN ID == 3 + memcpy(&m_sendBuffer3[TAG_802_1Q_OFFSET], &vlan_802_1Q_tag, sizeof(vlan_802_1Q_tag)); + return true; + }// ModifyPacktes () + + bool Run() + { + bool res = false; + bool isSuccess = false; + + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + + // Add the relevant filtering rules + res = AddRules(); + if (false == res) { + printf("Failed adding filtering rules.\n"); + return false; + } + + // Load input data (IP packet) from file + res = LoadFiles(m_IpaIPType); + if (false == res) { + printf("Failed loading files.\n"); + return false; + } + + res = ModifyPackets(); + if (false == res) { + printf("Failed to modify packets.\n"); + return false; + } + + // Send first packet + isSuccess = m_producer2.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) { + printf("SendData failure.\n"); + return false; + } + + // Send second packet + isSuccess = m_producer2.SendData(m_sendBuffer2, m_sendSize2); + if (false == isSuccess) { + printf("SendData failure.\n"); + return false; + } + + // Send third packet + isSuccess = m_producer2.SendData(m_sendBuffer3, m_sendSize3); + if (false == isSuccess) { + printf("SendData failure.\n"); + return false; + } + + // Receive packets from the channels and compare results + isSuccess = ReceivePacketsAndCompare(); + + printf("Leaving %s, %s(), Returning %d\n", __FUNCTION__, __FILE__, isSuccess); + + return isSuccess; + } // Run() +}; + +/*---------------------------------------------------------------------------*/ +/* Test100: Cache LRU behavior test */ +/*---------------------------------------------------------------------------*/ +#define CHACHE_ENTRIES 64 +#define CHACHE_PLUS_ONE (CHACHE_ENTRIES +1) +class IpaFilteringBlockTest100 : public IpaFilteringBlockTestFixture +{ +public: + IpaFilteringBlockTest100() + { + m_name = "IpaFilteringBlockTest100"; + m_description = " \ + Filtering block test 100 - Cache LRU behavior test \ + 1. Preload the cache by sending 64 packets for different connections \ + 2. Send another packet for 65th connection \ + 3. Send packets for first 64 connections \ + 4. Verify that 1st connection’s entry was reclaimed"; + m_IpaIPType = IPA_IP_v4; + m_minIPAHwType = IPA_HW_v4_0; + Register(*this); + } + + bool Setup() + { + /* we want statuses on this test */ + return IpaFilteringBlockTestFixture::Setup(true); + } + + virtual bool AddRules() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + + int i; + struct ipa_ioc_get_rt_tbl routing_table0; + const char bypass0[20] = "Bypass0"; + + if (!CreateBypassRoutingTable(&m_routing, + m_IpaIPType, + bypass0, + IPA_CLIENT_TEST2_CONS, + 0, + &routing_table0.hdl)) { + LOG_MSG_ERROR("CreateBypassRoutingTable Failed\n"); + return false; + } + + routing_table0.ip = m_IpaIPType; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + printf("m_routing.GetRoutingTable(&routing_table0=0x%p) Failed.\n",&routing_table0); + return false; + } + + printf("Creating Bypass Routing Table completed successfully\n"); + + IPAFilteringTable FilterTable0; + struct ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v4, IPA_CLIENT_TEST_PROD, false, CHACHE_PLUS_ONE); + printf("FilterTable*.Init Completed Successfully..\n"); + + FilterTable0.GeneratePresetRule(1, flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl=-1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action = IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.rt_tbl_hdl = routing_table0.hdl; + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + flt_rule_entry.rule.attrib.u.v4.dst_addr_mask = 0xFF0000FF; // Mask + flt_rule_entry.rule.hashable = 1; + + for (i = 0; i < CHACHE_PLUS_ONE; i++) { + // Configuring Filtering Rule No.i + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0xC0A80101 + i; // Filter DST_IP == 192.168.1.(1+i). + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) { + printf("%s::Error Adding Rule to Filter Table, aborting...\n", __FUNCTION__); + return false; + } + } + + if (!m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable())) + { + printf ("%s::Error Adding RuleTable(%d) to Filtering, aborting...\n", __FUNCTION__, i); + return false; + } else { + for (i = 0; i < CHACHE_PLUS_ONE; i++) { + printf("flt rule hdl=0x%x, status=0x%x\n", + FilterTable0.ReadRuleFromTable(i)->flt_rule_hdl, + FilterTable0.ReadRuleFromTable(i)->status); + } + } + + printf("Leaving %s, %s()\n",__FUNCTION__, __FILE__); + return true; + } + + virtual bool ModifyPackets() { + return true; + } + + bool Run() + { + bool res = false; + bool isSuccess = false; + + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + + // Add the relevant filtering rules + res = AddRules(); + if (false == res) { + printf("Failed adding filtering rules.\n"); + return false; + } + + // Load input data (IP packet) from file + res = LoadFiles(m_IpaIPType); + if (false == res) { + printf("Failed loading files.\n"); + return false; + } + + // Send the first CHACHE_ENTRIES packets + // Receive packets and compare results + // All rules should be cache miss + for (int i = 0; i < CHACHE_ENTRIES; i++) { + res = __ModifyPackets(i); + if (false == res) { + printf("Failed to modify packets.\n"); + return false; + } + + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + isSuccess = ReceivePacketAndCompareFrom(m_consumer, m_sendBuffer, m_sendSize, false); + if (false == isSuccess) { + printf("%s:%d: ReceivePacketAndCompareFrom failure.\n", __FUNCTION__, __LINE__); + return false; + } + } + + // Send again the first CHACHE_ENTRIES packets + // Receive packets and compare results + // All rules should be cache hit + for (int i = 0; i < CHACHE_ENTRIES; i++) { + res = __ModifyPackets(i); + if (false == res) { + printf("Failed to modify packets.\n"); + return false; + } + + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + isSuccess = ReceivePacketAndCompareFrom(m_consumer, m_sendBuffer, m_sendSize, true); + if (false == isSuccess) { + printf("%s:%d: ReceivePacketAndCompareFrom failure.\n", __FUNCTION__, __LINE__); + return false; + } + } + + // Send a packet to a new filter entry, this should trigger the LRU clear + res = __ModifyPackets(CHACHE_ENTRIES); + if (false == res) { + printf("Failed to modify packets.\n"); + return false; + } + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) { + printf("SendData failure.\n"); + return false; + } + + // receive and verify that cache was missed + isSuccess = ReceivePacketAndCompareFrom(m_consumer, m_sendBuffer, m_sendSize, false); + if (false == isSuccess) { + printf("%s:%d: ReceivePacketAndCompareFrom failure.\n", __FUNCTION__, __LINE__); + return false; + } + + // send the first packet again + res = __ModifyPackets(0); + if (false == res) { + printf("Failed to modify packets.\n"); + return false; + } + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) { + printf("SendData failure.\n"); + return false; + } + + // receive and verify that cache was missed + isSuccess = ReceivePacketAndCompareFrom(m_consumer, m_sendBuffer, m_sendSize, false); + if (false == isSuccess) { + printf("%s:%d: ReceivePacketAndCompareFrom failure.\n", __FUNCTION__, __LINE__); + return false; + } + + printf("Leaving %s, %s(), Returning %d\n",__FUNCTION__, __FILE__, isSuccess); + + return isSuccess; + } // Run() + +private: + bool __ModifyPackets(int i) + { + int address; + + address = ntohl(0xC0A80101 + i); // 192.168.1.(1+i) + memcpy(&m_sendBuffer[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + + return true; + } + +}; + +/*----------------------------------------------------------------------------------------------*/ +/* Test101: IPV4 filtering test - non hashed table SRAM <-> DDR dynamic move */ +/*----------------------------------------------------------------------------------------------*/ +class IpaFilteringBlockTest101 : public IpaFilteringBlockTestFixture { +public: + IpaFilteringBlockTest101() + { + m_name = "IpaFilteringBlockTest101"; + m_description = + "Filtering block test 101 - Non-Hashable table should start in SRAM, after adding enough rules table should move to DDR\ + then after removing enough rules the table should return to SRAM\ + 1. Generate and commit three routing tables. \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit three filtering rules: (DST & Mask Match). \ + All DST_IP == (127.0.0.1 & 255.0.0.255)traffic goes to routing table 0 - non hashable\ + All DST_IP == (127.0.0.1 & 255.0.0.255)traffic goes to routing table 1 - hashable\ + All DST_IP == (192.169.1.2 & 255.0.0.255)traffic goes to routing table 2 - don't care for this specific test"; + m_minIPAHwType = IPA_HW_v5_0; + m_IpaIPType = IPA_IP_v4; + Register(*this); + } + + virtual bool AddRules() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + + m_routing.Reset(IPA_IP_v4); // This will issue a Reset command to the Routing as well + m_routing.Reset(IPA_IP_v6); // This will issue a Reset command to the Routing as well + m_filtering.Reset(IPA_IP_v4); // This will issue a Reset command to the Filtering as well + m_filtering.Reset(IPA_IP_v6); // This will issue a Reset command to the Filtering as well + + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + + if (!CreateThreeIPv4BypassRoutingTables(bypass0, bypass1, bypass2)) { + printf("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + + printf("CreateThreeBypassRoutingTables completed successfully\n"); + routing_table0.ip = IPA_IP_v4; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) { + printf("m_routing.GetRoutingTable(&routing_table0=0x%p) Failed.\n", &routing_table0); + return false; + } + printf("route table %s has the handle %u\n", bypass0, routing_table0.hdl); + + routing_table1.ip = IPA_IP_v4; + strlcpy(routing_table1.name, bypass1, sizeof(routing_table1.name)); + if (!m_routing.GetRoutingTable(&routing_table1)) { + printf("m_routing.GetRoutingTable(&routing_table1=0x%p) Failed.\n", &routing_table1); + return false; + } + printf("route table %s has the handle %u\n", bypass1, routing_table1.hdl); + + routing_table2.ip = IPA_IP_v4; + strlcpy(routing_table2.name, bypass2, sizeof(routing_table2.name)); + if (!m_routing.GetRoutingTable(&routing_table2)) { + printf("m_routing.GetRoutingTable(&routing_table2=0x%p) Failed.\n", &routing_table2); + return false; + } + printf("route table %s has the handle %u\n", bypass2, routing_table2.hdl); + + struct ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v4, IPA_CLIENT_TEST_PROD, false, 3); + printf("FilterTable*.Init Completed Successfully..\n"); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1, flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl = -1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action = IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.rt_tbl_hdl = routing_table0.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; // + flt_rule_entry.rule.attrib.u.v4.dst_addr_mask = 0xFF0000FF; // Mask + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0x7F000001; // Filter DST_IP == 127.0.0.1. + flt_rule_entry.rule.hashable = 0; // non hashed + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) { + printf("%s::Error Adding Rule to Filter Table, aborting...\n", __FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.1 on lower priority (second in list) + flt_rule_entry.rule.rt_tbl_hdl = routing_table1.hdl; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.attrib.u.v4.dst_addr_mask = 0xFF0000FF; // Mask + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0x7F000001; // Filter DST_IP == 127.0.0.1. + flt_rule_entry.rule.hashable = 1; // hashed + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) { + printf("%s::Error Adding Rule to Filter Table, aborting...\n", __FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.2 + flt_rule_entry.rule.rt_tbl_hdl = routing_table2.hdl; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.hashable = 0; // non hashed + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0xC0A80102; // Filter DST_IP == 192.168.1.2. + + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) { + printf("%s::Error Adding Rule to Filter Table, aborting...\n", __FUNCTION__); + return false; + } else { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl, FilterTable0.ReadRuleFromTable(0)->status); + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(1)->flt_rule_hdl, FilterTable0.ReadRuleFromTable(1)->status); + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(2)->flt_rule_hdl, FilterTable0.ReadRuleFromTable(2)->status); + } + + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return true; + } + + virtual bool ModifyPackets() + { + int address; + + address = ntohl(0x7F000001);//127.0.0.1 + memcpy(&m_sendBuffer[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + address = ntohl(0x7F000001);//127.0.0.1 + memcpy(&m_sendBuffer2[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + address = ntohl(0xC0A80102);//192.168.1.2 + memcpy(&m_sendBuffer3[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + + return true; + } + + virtual bool ReceivePacketsAndCompare() + { + size_t receivedSize = 0; + size_t receivedSize2 = 0; + size_t receivedSize3 = 0; + bool isSuccess = true; + + // Receive results + Byte *rxBuff1 = new Byte[0x400]; + Byte *rxBuff2 = new Byte[0x400]; + Byte *rxBuff3 = new Byte[0x400]; + + if (NULL == rxBuff1 || NULL == rxBuff2 || NULL == rxBuff3) { + printf("Memory allocation error.\n"); + return false; + } + + receivedSize = m_consumer.ReceiveData(rxBuff1, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize, m_consumer.m_fromChannelName.c_str()); + + receivedSize2 = m_consumer.ReceiveData(rxBuff2, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize2, m_consumer.m_fromChannelName.c_str()); + + receivedSize3 = m_defaultConsumer.ReceiveData(rxBuff3, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize3, m_defaultConsumer.m_fromChannelName.c_str()); + + // Compare results + if (!CompareResultVsGolden(m_sendBuffer, m_sendSize, rxBuff1, receivedSize)) { + printf("Comparison of Buffer0 Failed!\n"); + isSuccess = false; + } + + size_t recievedBufferSize = receivedSize * 3; + size_t sentBufferSize = m_sendSize * 3; + char *recievedBuffer = new char[recievedBufferSize]; + char *sentBuffer = new char[sentBufferSize]; + + memset(recievedBuffer, 0, recievedBufferSize); + memset(sentBuffer, 0, sentBufferSize); + + print_packets(receivedSize, m_sendSize, recievedBufferSize - 1, sentBufferSize - 1, rxBuff1, m_sendBuffer, recievedBuffer, sentBuffer); + recievedBuffer[0] = '\0'; + print_packets(receivedSize2, m_sendSize2, recievedBufferSize - 1, sentBufferSize - 1, rxBuff2, m_sendBuffer2, recievedBuffer, sentBuffer); + recievedBuffer[0] = '\0'; + print_packets(receivedSize3, m_sendSize3, recievedBufferSize - 1, sentBufferSize - 1, rxBuff3, m_sendBuffer3, recievedBuffer, sentBuffer); + + isSuccess &= CompareResultVsGolden(m_sendBuffer2, m_sendSize2, rxBuff2, receivedSize2); + isSuccess &= CompareResultVsGolden(m_sendBuffer3, m_sendSize3, rxBuff3, receivedSize3); + + delete[] recievedBuffer; + delete[] sentBuffer; + + delete[] rxBuff1; + delete[] rxBuff2; + delete[] rxBuff3; + + return isSuccess; + } + + bool SendAndVerifyPackets() + { + bool isSuccess = false; + + // Send first packet + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) { + printf("SendData failure.\n"); + return false; + } + + // Send second packet + isSuccess = m_producer.SendData(m_sendBuffer2, m_sendSize2); + if (false == isSuccess) { + printf("SendData failure.\n"); + return false; + } + + // Send third packet + isSuccess = m_producer.SendData(m_sendBuffer3, m_sendSize3); + if (false == isSuccess) { + printf("SendData failure.\n"); + return false; + } + + // Receive packets from the channels and compare results + isSuccess = ReceivePacketsAndCompare(); + if (false == isSuccess) { + printf("ReceivePacketsAndCompare failure.\n"); + return false; + } + + return true; + } + + bool AddRuleToEnd() + { + struct ipa_flt_rule_add flt_rule_entry; + IPAFilteringTable tempFltTable; + + tempFltTable.Init(m_IpaIPType, IPA_CLIENT_TEST_PROD, false, 1); + printf("FilterTable*.Init Completed Successfully..\n"); + + // Configuring Filtering Rule No.0 + tempFltTable.GeneratePresetRule(0, flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl = -1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action = IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.rt_tbl_hdl = routing_table0.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; // + flt_rule_entry.rule.attrib.u.v4.dst_addr_mask = 0xFF0000FF; // Mask + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0x7F000001; // Filter DST_IP == 127.0.0.1. + flt_rule_entry.rule.hashable = 0; // non hashed + + if ( + ((uint8_t)-1 == tempFltTable.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(tempFltTable.GetFilteringTable()) + ) { + printf("%s::Error Adding Rule to Filter Table, aborting...\n", __FUNCTION__); + return false; + } else { + printf("flt rule hdl0=0x%x, status=0x%x\n", tempFltTable.ReadRuleFromTable(0)->flt_rule_hdl, FilterTable0.ReadRuleFromTable(0)->status); + } + + if (!FilterTable0.WriteRuleToEndOfTable(tempFltTable.ReadRuleFromTable(0))){ + printf("%s::Error Adding Rule to Filter Table, aborting...\n", __FUNCTION__); + return false; + } + + return true; + } + + bool AddRulesUntilTableMovesToDDR() + { + int fd; + + // Open ipa_test device node + fd = open("/dev/ipa_test", O_RDONLY); + if (fd < 0) { + printf("Failed opening %s. errno %d: %s\n", "/dev/ipa_test", errno, strerror(errno)); + return false; + } + + printf("%s(), fd is %d\n", __FUNCTION__, fd); + + while (FilterTable0.size() < MAX_RULES_NUM && + ioctl(fd, IPA_TEST_IOC_IS_TEST_PROD_FLT_IN_SRAM, m_IpaIPType)) { + if (!AddRuleToEnd()) + return false; + printf("%s, %s() Added rule #%d sucessfully \n", __FUNCTION__, __FILE__, FilterTable0.size() - 1); + } + close(fd); + + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return true; + } + + bool RemoveLastRule() + { + struct ipa_ioc_del_flt_rule *pDeleteRule = (struct ipa_ioc_del_flt_rule *) + calloc(1, sizeof(struct ipa_ioc_del_flt_rule) + sizeof(struct ipa_flt_rule_del)); + + pDeleteRule->commit = 1; + pDeleteRule->ip = m_IpaIPType; + pDeleteRule->num_hdls = 1; + pDeleteRule->hdl[0].hdl = FilterTable0.ReadRuleFromTable(FilterTable0.size()-1)->flt_rule_hdl; + pDeleteRule->hdl[0].status = -1; + + if (!m_filtering.DeleteFilteringRule(pDeleteRule)) { + printf("%s::Error Deleting Rule from Filter Table, aborting...\n", __FUNCTION__); + return false; + } + + return true; + } + + bool RemoveRulesUntilTableMovesToSRAM() + { + int fd; + + // Open ipa_test device node + fd = open("/dev/ipa_test", O_RDONLY); + if (fd < 0) { + printf("Failed opening %s. errno %d: %s\n", "/dev/ipa_test", errno, strerror(errno)); + return false; + } + + printf("%s(), fd is %d\n", __FUNCTION__, fd); + while (FilterTable0.size() > MIN_RULES_NUM && + !ioctl(fd, IPA_TEST_IOC_IS_TEST_PROD_FLT_IN_SRAM, m_IpaIPType)) + if (!RemoveLastRule()) + return false; + close(fd); + + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return true; + } + + bool Run() + { + bool res = false; + bool isSuccess = false; + + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + + // Add the relevant filtering rules + res = AddRules(); + if (false == res) { + printf("Failed adding filtering rules.\n"); + return false; + } + + // Load input data (IP packet) from file + res = LoadFiles(m_IpaIPType); + if (false == res) { + printf("Failed loading files.\n"); + return false; + } + + res = ModifyPackets(); + if (false == res) { + printf("Failed to modify packets.\n"); + return false; + } + + /* Send packets with table in SRAM */ + isSuccess = SendAndVerifyPackets(); + if (!isSuccess) { + printf("Leaving %s, %s(), Returning %d\n", __FUNCTION__, __FILE__, isSuccess); + return false; + } + + /* Add rules until table moves to DDR and send packets again */ + isSuccess = AddRulesUntilTableMovesToDDR(); + if (!isSuccess) { + printf("Leaving %s, %s(), Returning %d\n", __FUNCTION__, __FILE__, isSuccess); + return false; + } + + isSuccess = SendAndVerifyPackets(); + if (!isSuccess) { + printf("Leaving %s, %s(), Returning %d\n", __FUNCTION__, __FILE__, isSuccess); + return false; + } + + /* Remove rules until table moves back to SRAM and send packets again */ + isSuccess = RemoveRulesUntilTableMovesToSRAM(); + if (!isSuccess) { + printf("Leaving %s, %s(), Returning %d\n", __FUNCTION__, __FILE__, isSuccess); + return false; + } + + isSuccess = SendAndVerifyPackets(); + + printf("Leaving %s, %s(), Returning %d\n", __FUNCTION__, __FILE__, isSuccess); + + return isSuccess; + } // Run() + +protected: + IPAFilteringTable FilterTable0; + struct ipa_ioc_get_rt_tbl routing_table0, routing_table1, routing_table2; +}; + +/*----------------------------------------------------------------------------------------------*/ +/* Test102: IPV6 filtering test - non hashed table SRAM <-> DDR dynamic move */ +/*----------------------------------------------------------------------------------------------*/ +class IpaFilteringBlockTest102 : public IpaFilteringBlockTest101 { +public: + IpaFilteringBlockTest102() + { + m_name = "IpaFilteringBlockTest102"; + m_description = + "Filtering block test 102 - Non-Hashable table should start in SRAM, after adding enough rules table should move to DDR\ + then after removing enough rules the table should return to SRAM\ + 1. Generate and commit three routing tables. \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit three filtering rules: (DST & Mask Match). \ + All DST_IPv6 == 0x...AA traffic goes to routing table 0 - non hashable\ + All DST_IPv6 == 0x...AA traffic goes to routing table 1 - hashable\ + All DST_IPv6 == 0x...CC traffic goes to routing table 2 - non hashable - don't care for this specific test"; + m_minIPAHwType = IPA_HW_v5_0; + m_IpaIPType = IPA_IP_v6; + } + + virtual bool GetThreeIPv6BypassRoutingTables(uint32_t *Hndl0, uint32_t *Hndl1, uint32_t *Hndl2) + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + + if (!CreateThreeIPv6BypassRoutingTables(bypass0, bypass1, bypass2)) { + printf("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + + printf("CreateThreeBypassRoutingTables completed successfully\n"); + routing_table0.ip = IPA_IP_v6; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) { + printf("m_routing.GetRoutingTable(&routing_table0=0x%p) Failed.\n", &routing_table0); + return false; + } + routing_table1.ip = IPA_IP_v6; + strlcpy(routing_table1.name, bypass1, sizeof(routing_table1.name)); + if (!m_routing.GetRoutingTable(&routing_table1)) { + printf("m_routing.GetRoutingTable(&routing_table1=0x%p) Failed.\n", &routing_table1); + return false; + } + + routing_table2.ip = IPA_IP_v6; + strlcpy(routing_table2.name, bypass2, sizeof(routing_table2.name)); + if (!m_routing.GetRoutingTable(&routing_table2)) { + printf("m_routing.GetRoutingTable(&routing_table2=0x%p) Failed.\n", &routing_table2); + return false; + } + + *Hndl0 = routing_table0.hdl; + *Hndl1 = routing_table1.hdl; + *Hndl2 = routing_table2.hdl; + + return true; + } + + virtual bool AddRules() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + + if (!GetThreeIPv6BypassRoutingTables(&Hndl0, &Hndl1, &Hndl2)) { + printf("failed to get three IPV6 routing tables!\n"); + return false; + } + + struct ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v6, IPA_CLIENT_TEST_PROD, false, 3); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1, flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl = -1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action = IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.rt_tbl_hdl = Hndl0; //put here the handle corresponding to Routing Rule 0 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[0] = 0xFFFFFFFF;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[1] = 0xFFFFFFFF;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[2] = 0x00000000;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[3] = 0x000000FF;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr[0] = 0XFF020000; // Filter DST_IP + flt_rule_entry.rule.attrib.u.v6.dst_addr[1] = 0x00000000; + flt_rule_entry.rule.attrib.u.v6.dst_addr[2] = 0x11223344; + flt_rule_entry.rule.attrib.u.v6.dst_addr[3] = 0X556677AA; + flt_rule_entry.rule.hashable = 0; // non hashable + + printf("flt_rule_entry was set successfully, preparing for insertion....\n"); + + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) { + printf("%s::Error Adding Rule to Filter Table, aborting...\n", __FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.1 + flt_rule_entry.rule.rt_tbl_hdl = Hndl1; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.u.v6.dst_addr[3] = 0X556677AA; + flt_rule_entry.rule.hashable = 1; // hashable + + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) { + printf("%s::Error Adding Rule to Filter Table, aborting...\n", __FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.2 + flt_rule_entry.rule.rt_tbl_hdl = Hndl2; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.attrib.u.v6.dst_addr[3] = 0X556677CC; + flt_rule_entry.rule.hashable = 0; // non hashable + + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) { + printf("%s::Error Adding RuleTable(2) to Filtering, aborting...\n", __FUNCTION__); + return false; + } else { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(2)->flt_rule_hdl, FilterTable0.ReadRuleFromTable(2)->status); + } + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return true; + } + + virtual bool ModifyPackets() + { + m_sendBuffer[DST_ADDR_LSB_OFFSET_IPV6] = 0xAA; + m_sendBuffer2[DST_ADDR_LSB_OFFSET_IPV6] = 0xAA; + m_sendBuffer3[DST_ADDR_LSB_OFFSET_IPV6] = 0xCC; + return true; + }// ModifyPacktes () + + bool AddRuleToEnd() + { + struct ipa_flt_rule_add flt_rule_entry; + IPAFilteringTable tempFltTable; + + tempFltTable.Init(m_IpaIPType, IPA_CLIENT_TEST_PROD, false, 1); + printf("FilterTable*.Init Completed Successfully..\n"); + + // Configuring Filtering Rule No.0 + tempFltTable.GeneratePresetRule(0, flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl = -1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action = IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.rt_tbl_hdl = Hndl0; //put here the handle corresponding to Routing Rule 0 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[0] = 0xFFFFFFFF;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[1] = 0xFFFFFFFF;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[2] = 0x00000000;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[3] = 0x000000FF;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr[0] = 0XFF020000; // Filter DST_IP + flt_rule_entry.rule.attrib.u.v6.dst_addr[1] = 0x00000000; + flt_rule_entry.rule.attrib.u.v6.dst_addr[2] = 0x11223344; + flt_rule_entry.rule.attrib.u.v6.dst_addr[3] = 0X556677AA; + flt_rule_entry.rule.hashable = 0; // non hashable + + if ( + ((uint8_t)-1 == tempFltTable.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(tempFltTable.GetFilteringTable()) + ) { + printf("%s::Error Adding Rule to Filter Table, aborting...\n", __FUNCTION__); + return false; + } else { + printf("flt rule hdl0=0x%x, status=0x%x\n", tempFltTable.ReadRuleFromTable(0)->flt_rule_hdl, FilterTable0.ReadRuleFromTable(0)->status); + } + + if (!FilterTable0.WriteRuleToEndOfTable(tempFltTable.ReadRuleFromTable(0))) { + printf("%s::Error Adding Rule to Filter Table, aborting...\n", __FUNCTION__); + return false; + } + + return true; + } + +protected: + uint32_t Hndl0, Hndl1, Hndl2; +}; + +/*---------------------------------------------------------------------------*/ +/* Test110: TTL Update on Filtering rule */ +/*---------------------------------------------------------------------------*/ +class IpaFilteringBlockTest110 : public IpaFilteringBlockTestFixture +{ +public: + IpaFilteringBlockTest110() + { + m_name = "IpaFilteringBlockTest110"; + m_description = + "Filtering block test 110 - Destination IP address and subnet mask match against LAN subnet \ + (End-Point specific Filtering Table, Insert all rules in a single commit) \ + and check if TTL is updated. \ + 1. Generate and commit three routing tables. \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit Three filtering rules: (DST & Mask Match). \ + All DST_IP == (127.0.0.1 & 255.0.0.255)traffic goes to routing table 0, enable TTL decrement in HW. \ + All DST_IP == (192.169.1.1 & 255.0.0.255)traffic goes to routing table 1, enable TTL decrement in HW \ + All DST_IP == (192.169.1.2 & 255.0.0.255)traffic goes to routing table 2, not enable TTL decrement in HW"; + m_minIPAHwType = IPA_HW_v5_5; + Register(*this); + } + + + virtual bool AddRules() + { + printf("Entering %s, %s()\n",__FUNCTION__, __FILE__); + + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + struct ipa_ioc_get_rt_tbl routing_table0,routing_table1,routing_table2; + + if (!CreateThreeIPv4BypassRoutingTables (bypass0,bypass1,bypass2)) + { + printf("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + + printf("CreateThreeBypassRoutingTables completed successfully\n"); + routing_table0.ip = IPA_IP_v4; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + printf("m_routing.GetRoutingTable(&routing_table0=0x%p) Failed.\n",&routing_table0); + return false; + } + printf("%s route table handle = %u\n", bypass0, routing_table0.hdl); + + routing_table1.ip = IPA_IP_v4; + strlcpy(routing_table1.name, bypass1, sizeof(routing_table1.name)); + if (!m_routing.GetRoutingTable(&routing_table1)) + { + printf("m_routing.GetRoutingTable(&routing_table1=0x%p) Failed.\n",&routing_table1); + return false; + } + printf("%s route table handle = %u\n", bypass1, routing_table1.hdl); + + routing_table2.ip = IPA_IP_v4; + strlcpy(routing_table2.name, bypass2, sizeof(routing_table2.name)); + if (!m_routing.GetRoutingTable(&routing_table2)) + { + printf("m_routing.GetRoutingTable(&routing_table2=0x%p) Failed.\n",&routing_table2); + return false; + } + printf("%s route table handle = %u\n", bypass2, routing_table2.hdl); + + IPAFilteringTable_v2 FilterTable0; + struct ipa_flt_rule_add_v2 flt_rule_entry; + FilterTable0.Init(IPA_IP_v4,IPA_CLIENT_TEST_PROD,false,3); + printf("FilterTable*.Init Completed Successfully..\n"); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1,flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl=-1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action=IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.rt_tbl_hdl=routing_table0.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + flt_rule_entry.rule.attrib.u.v4.dst_addr_mask = 0xFF0000FF; // Mask + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0x7F000001; // Filter DST_IP == 127.0.0.1. + flt_rule_entry.rule.ttl_update = 1; // require ttl update + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.1 + flt_rule_entry.rule.rt_tbl_hdl=routing_table1.hdl; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0xC0A80101; // Filter DST_IP == 192.168.1.1. + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.2 + flt_rule_entry.rule.rt_tbl_hdl=routing_table2.hdl; //put here the handle corresponding to Routing Rule 2 + // TODO: Fix this, doesn't match the Rule's Requirements + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0xC0A80102; // Filter DST_IP == 192.168.1.2. + flt_rule_entry.rule.ttl_update = 0; // doesn't require ttl update + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(0)->status); + printf("flt rule hdl1=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(1)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(1)->status); + printf("flt rule hdl2=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(2)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(2)->status); + } + + printf("Leaving %s, %s()\n",__FUNCTION__, __FILE__); + return true; + }// AddRules() + + virtual bool ModifyPackets() + { + int address; + address = ntohl(0x7F000001);//127.0.0.1 + memcpy(&m_sendBuffer[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + m_sendBuffer[IPV4_TTL_OFFSET] = 5; + address = ntohl(0xC0A80101);//192.168.1.1 + memcpy(&m_sendBuffer2[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + m_sendBuffer2[IPV4_TTL_OFFSET] = 4; + address = ntohl(0xC0A80102);//192.168.1.2 + memcpy(&m_sendBuffer3[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + m_sendBuffer3[IPV4_TTL_OFFSET] = 3; + return true; + }// ModifyPacktes () + + virtual bool ReceivePacketsAndCompare() + { + size_t receivedSize = 0; + size_t receivedSize2 = 0; + size_t receivedSize3 = 0; + uint16_t csum = 0; + bool pkt1_cmp_succ, pkt2_cmp_succ, pkt3_cmp_succ; + + // Receive results + Byte *rxBuff1 = new Byte[0x400]; + Byte *rxBuff2 = new Byte[0x400]; + Byte *rxBuff3 = new Byte[0x400]; + + if (NULL == rxBuff1 || NULL == rxBuff2 || NULL == rxBuff3) + { + printf("Memory allocation error.\n"); + return false; + } + + memset(rxBuff1, 0, 0x400); + memset(rxBuff2, 0, 0x400); + memset(rxBuff3, 0, 0x400); + + receivedSize = m_consumer.ReceiveData(rxBuff1, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize, m_consumer.m_fromChannelName.c_str()); + + receivedSize2 = m_consumer2.ReceiveData(rxBuff2, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize2, m_consumer2.m_fromChannelName.c_str()); + + receivedSize3 = m_defaultConsumer.ReceiveData(rxBuff3, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize3, m_defaultConsumer.m_fromChannelName.c_str()); + + /* Update TTL values. */ + m_sendBuffer[IPV4_TTL_OFFSET] = 4; + m_sendBuffer2[IPV4_TTL_OFFSET] = 3; + + /* Update Checksum.*/ + csum = *((uint16_t *)(m_sendBuffer + IPV4_CSUM_OFFSET)); + csum += 1; + *((uint16_t *)(m_sendBuffer+ IPV4_CSUM_OFFSET)) = csum; + + csum = *((uint16_t *)(m_sendBuffer2 + IPV4_CSUM_OFFSET)); + csum += 1; + *((uint16_t *)(m_sendBuffer2 + IPV4_CSUM_OFFSET)) = csum; + + // Compare results + pkt1_cmp_succ = CompareResultVsGolden(m_sendBuffer, m_sendSize, rxBuff1, receivedSize); + pkt2_cmp_succ = CompareResultVsGolden(m_sendBuffer2, m_sendSize2, rxBuff2, receivedSize2); + pkt3_cmp_succ = CompareResultVsGolden(m_sendBuffer3, m_sendSize3, rxBuff3, receivedSize3); + + size_t recievedBufferSize = + MAX3(receivedSize, receivedSize2, receivedSize3) * 3; + size_t sentBufferSize = + MAX3(m_sendSize, m_sendSize2, m_sendSize3) * 3; + char *recievedBuffer = new char[recievedBufferSize]; + char *sentBuffer = new char[sentBufferSize]; + size_t j; + + if (NULL == recievedBuffer || NULL == sentBuffer) { + printf("Memory allocation error\n"); + return false; + } + + memset(recievedBuffer, 0, recievedBufferSize); + memset(sentBuffer, 0, sentBufferSize); + for(j = 0; j < m_sendSize; j++) + snprintf(&sentBuffer[3 * j], sentBufferSize - (3 * j + 1), " %02X", m_sendBuffer[j]); + for(j = 0; j < receivedSize; j++) + snprintf(&recievedBuffer[3 * j], recievedBufferSize - (3 * j + 1), " %02X", rxBuff1[j]); + printf("Expected Value1 (%zu)\n%s\n, Received Value1(%zu)\n%s\n-->Value1 %s\n", + m_sendSize,sentBuffer,receivedSize,recievedBuffer, + pkt1_cmp_succ?"Match":"no Match"); + + memset(recievedBuffer, 0, recievedBufferSize); + memset(sentBuffer, 0, sentBufferSize); + for(j = 0; j < m_sendSize2; j++) + snprintf(&sentBuffer[3 * j], sentBufferSize - (3 * j + 1), " %02X", m_sendBuffer2[j]); + for(j = 0; j < receivedSize2; j++) + snprintf(&recievedBuffer[3 * j], recievedBufferSize - (3 * j + 1), " %02X", rxBuff2[j]); + printf("Expected Value2 (%zu)\n%s\n, Received Value2(%zu)\n%s\n-->Value2 %s\n", + m_sendSize2,sentBuffer,receivedSize2,recievedBuffer, + pkt2_cmp_succ?"Match":"no Match"); + + memset(recievedBuffer, 0, recievedBufferSize); + memset(sentBuffer, 0, sentBufferSize); + for(j = 0; j < m_sendSize3; j++) + snprintf(&sentBuffer[3 * j], sentBufferSize - (3 * j + 1), " %02X", m_sendBuffer3[j]); + for(j = 0; j < receivedSize3; j++) + snprintf(&recievedBuffer[3 * j], recievedBufferSize - (3 * j + 1), " %02X", rxBuff3[j]); + printf("Expected Value3 (%zu)\n%s\n, Received Value3(%zu)\n%s\n-->Value3 %s\n", + m_sendSize3,sentBuffer,receivedSize3,recievedBuffer, + pkt3_cmp_succ?"Match":"no Match"); + + delete[] recievedBuffer; + delete[] sentBuffer; + + delete[] rxBuff1; + delete[] rxBuff2; + delete[] rxBuff3; + + return pkt1_cmp_succ && pkt2_cmp_succ && pkt3_cmp_succ; + } + + virtual bool Teardown() + { + return true; + } // Teardown() + + +}; + +/*---------------------------------------------------------------------------------------------*/ +/* Test111: TTL update based on Destination IPv6 address and Subnet Mask exact match against broadcast IP address */ +/*---------------------------------------------------------------------------------------------*/ +class IpaFilteringBlockTest111 : public IpaFilteringBlockTestFixture +{ +public: + IpaFilteringBlockTest111() + { + m_name = "IpaFilteringBlockTest111"; + m_description = + "Filtering block test 111 - TTL update based on Destination IPv6 address and Mask exact match against broadcast IP address (End-Point specific Filtering Table, Insert all rules in a single commit)\ + 1. Generate and commit three routing tables. \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly with TTL update)) \ + 2. Generate and commit three filtering rules: (DST & Mask Match). \ + All DST_IPv6 == 0x...AA traffic goes to routing table 1 \ + All DST_IPv6 == 0x...BB traffic goes to routing table 2 \ + All DST_IPv6 == 0x...CC traffic goes to routing table 3"; + m_IpaIPType = IPA_IP_v6; + m_minIPAHwType = IPA_HW_v5_5; + Register(*this); + } + + + virtual bool AddRules() + { + printf("Entering %s, %s()\n",__FUNCTION__, __FILE__); + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + struct ipa_ioc_get_rt_tbl routing_table0,routing_table1,routing_table2; + + if (!CreateThreeIPv6BypassRoutingTables (bypass0,bypass1,bypass2)) + { + printf("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + + printf("CreateThreeBypassRoutingTables completed successfully\n"); + routing_table0.ip = IPA_IP_v6; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + printf("m_routing.GetRoutingTable(&routing_table0=0x%p) Failed.\n",&routing_table0); + return false; + } + routing_table1.ip = IPA_IP_v6; + strlcpy(routing_table1.name, bypass1, sizeof(routing_table1.name)); + if (!m_routing.GetRoutingTable(&routing_table1)) + { + printf("m_routing.GetRoutingTable(&routing_table1=0x%p) Failed.\n",&routing_table1); + return false; + } + + routing_table2.ip = IPA_IP_v6; + strlcpy(routing_table2.name, bypass2, sizeof(routing_table2.name)); + if (!m_routing.GetRoutingTable(&routing_table2)) + { + printf("m_routing.GetRoutingTable(&routing_table2=0x%p) Failed.\n",&routing_table2); + return false; + } + + IPAFilteringTable_v2 FilterTable0; + struct ipa_flt_rule_add_v2 flt_rule_entry; + FilterTable0.Init(IPA_IP_v6,IPA_CLIENT_TEST_PROD,false,3); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1,flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl=-1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action=IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.rt_tbl_hdl=routing_table0.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; // TODO: Fix this, doesn't match the Rule's Requirements + + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[0] = 0xFFFFFFFF;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[1] = 0xFFFFFFFF;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[2] = 0x00000000;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[3] = 0x000000FF;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr[0] = 0XFF020000; // Filter DST_IP + flt_rule_entry.rule.attrib.u.v6.dst_addr[1] = 0x00000000; + flt_rule_entry.rule.attrib.u.v6.dst_addr[2] = 0x11223344; + flt_rule_entry.rule.attrib.u.v6.dst_addr[3] = 0X556677AA; + + /* Enable ttl update in HW */ + flt_rule_entry.rule.ttl_update = 1; + printf ("flt_rule_entry was set successfully, preparing for insertion....\n"); + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } + // Configuring Filtering Rule No.1 + flt_rule_entry.rule.rt_tbl_hdl=routing_table1.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.u.v6.dst_addr[3] = 0X556677BB; + /* Disable ttl update in HW */ + flt_rule_entry.rule.ttl_update = 0; + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.2 + flt_rule_entry.rule.rt_tbl_hdl=routing_table2.hdl; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.attrib.u.v6.dst_addr[3] = 0X556677CC; + /* Enable ttl update in HW */ + flt_rule_entry.rule.ttl_update = 1; + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(0)->status); + printf("flt rule hdl1=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(1)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(1)->status); + printf("flt rule hdl2=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(2)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(2)->status); + } + printf("Leaving %s, %s()\n",__FUNCTION__, __FILE__); + return true; + }// AddRules() + + virtual bool ModifyPackets() + { + // TODO: Add verification that we access only allocated addresses + // TODO: Fix this, doesn't match the Rule's Requirements + m_sendBuffer[DST_ADDR_LSB_OFFSET_IPV6] = 0xAA; + m_sendBuffer[HOP_LIMIT_OFFSET_IPV6] = 5; + m_sendBuffer2[DST_ADDR_LSB_OFFSET_IPV6] = 0xBB; + m_sendBuffer2[HOP_LIMIT_OFFSET_IPV6] = 4; + m_sendBuffer3[DST_ADDR_LSB_OFFSET_IPV6] = 0xCC; + m_sendBuffer3[HOP_LIMIT_OFFSET_IPV6] = 3; + return true; + }// ModifyPacktes () + + virtual bool ReceivePacketsAndCompare() + { + size_t receivedSize = 0; + size_t receivedSize2 = 0; + size_t receivedSize3 = 0; + bool pkt1_cmp_succ, pkt2_cmp_succ, pkt3_cmp_succ; + + // Receive results + Byte *rxBuff1 = new Byte[0x400]; + Byte *rxBuff2 = new Byte[0x400]; + Byte *rxBuff3 = new Byte[0x400]; + + if (NULL == rxBuff1 || NULL == rxBuff2 || NULL == rxBuff3) + { + printf("Memory allocation error.\n"); + return false; + } + + memset(rxBuff1, 0, 0x400); + memset(rxBuff2, 0, 0x400); + memset(rxBuff3, 0, 0x400); + + receivedSize = m_consumer.ReceiveData(rxBuff1, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize, m_consumer.m_fromChannelName.c_str()); + + receivedSize2 = m_consumer2.ReceiveData(rxBuff2, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize2, m_consumer2.m_fromChannelName.c_str()); + + receivedSize3 = m_defaultConsumer.ReceiveData(rxBuff3, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize3, m_defaultConsumer.m_fromChannelName.c_str()); + + /* Update TTL values. */ + m_sendBuffer[HOP_LIMIT_OFFSET_IPV6] = 4; + m_sendBuffer3[HOP_LIMIT_OFFSET_IPV6] = 2; + + // Compare results + pkt1_cmp_succ = CompareResultVsGolden(m_sendBuffer, m_sendSize, rxBuff1, receivedSize); + pkt2_cmp_succ = CompareResultVsGolden(m_sendBuffer2, m_sendSize2, rxBuff2, receivedSize2); + pkt3_cmp_succ = CompareResultVsGolden(m_sendBuffer3, m_sendSize3, rxBuff3, receivedSize3); + + size_t recievedBufferSize = + MAX3(receivedSize, receivedSize2, receivedSize3) * 3; + size_t sentBufferSize = + MAX3(m_sendSize, m_sendSize2, m_sendSize3) * 3; + char *recievedBuffer = new char[recievedBufferSize]; + char *sentBuffer = new char[sentBufferSize]; + size_t j; + + if (NULL == recievedBuffer || NULL == sentBuffer) { + printf("Memory allocation error\n"); + return false; + } + + memset(recievedBuffer, 0, recievedBufferSize); + memset(sentBuffer, 0, sentBufferSize); + for(j = 0; j < m_sendSize; j++) + snprintf(&sentBuffer[3 * j], sentBufferSize - (3 * j + 1), " %02X", m_sendBuffer[j]); + for(j = 0; j < receivedSize; j++) + snprintf(&recievedBuffer[3 * j], recievedBufferSize - (3 * j + 1), " %02X", rxBuff1[j]); + printf("Expected Value1 (%zu)\n%s\n, Received Value1(%zu)\n%s\n-->Value1 %s\n", + m_sendSize,sentBuffer,receivedSize,recievedBuffer, + pkt1_cmp_succ?"Match":"no Match"); + + memset(recievedBuffer, 0, recievedBufferSize); + memset(sentBuffer, 0, sentBufferSize); + for(j = 0; j < m_sendSize2; j++) + snprintf(&sentBuffer[3 * j], sentBufferSize - (3 * j + 1), " %02X", m_sendBuffer2[j]); + for(j = 0; j < receivedSize2; j++) + snprintf(&recievedBuffer[3 * j], recievedBufferSize - (3 * j + 1), " %02X", rxBuff2[j]); + printf("Expected Value2 (%zu)\n%s\n, Received Value2(%zu)\n%s\n-->Value2 %s\n", + m_sendSize2,sentBuffer,receivedSize2,recievedBuffer, + pkt2_cmp_succ?"Match":"no Match"); + + memset(recievedBuffer, 0, recievedBufferSize); + memset(sentBuffer, 0, sentBufferSize); + for(j = 0; j < m_sendSize3; j++) + snprintf(&sentBuffer[3 * j], sentBufferSize - (3 * j + 1), " %02X", m_sendBuffer3[j]); + for(j = 0; j < receivedSize3; j++) + snprintf(&recievedBuffer[3 * j], recievedBufferSize - (3 * j + 1), " %02X", rxBuff3[j]); + printf("Expected Value3 (%zu)\n%s\n, Received Value3(%zu)\n%s\n-->Value3 %s\n", + m_sendSize3,sentBuffer,receivedSize3,recievedBuffer, + pkt3_cmp_succ?"Match":"no Match"); + + delete[] recievedBuffer; + delete[] sentBuffer; + + delete[] rxBuff1; + delete[] rxBuff2; + delete[] rxBuff3; + + return pkt1_cmp_succ && pkt2_cmp_succ && pkt3_cmp_succ; + } + +}; + +/*---------------------------------------------------------------------------*/ +/* Test112: TTL Update on Filtering rule with status enabled */ +/*---------------------------------------------------------------------------*/ +class IpaFilteringBlockTest112 : public IpaFilteringBlockTestFixture +{ +public: + IpaFilteringBlockTest112() + { + m_name = "IpaFilteringBlockTest112"; + m_description = + "Filtering block test 112 - Destination IP address and subnet mask match against LAN subnet \ + (End-Point specific Filtering Table, Insert all rules in a single commit) \ + and check if TTL is updated in status and packet. \ + 1. Generate and commit three routing tables. \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit Three filtering rules: (DST & Mask Match). \ + All DST_IP == (127.0.0.1 & 255.0.0.255)traffic goes to routing table 0, enable TTL decrement in HW. \ + All DST_IP == (192.169.1.1 & 255.0.0.255)traffic goes to routing table 1, enable TTL decrement in HW \ + All DST_IP == (192.169.1.2 & 255.0.0.255)traffic goes to routing table 2, not enable TTL decrement in HW"; + m_minIPAHwType = IPA_HW_v5_5; + Register(*this); + } + + bool Setup() + { + /* we want statuses on this test */ + return IpaFilteringBlockTestFixture::Setup(true); + } + + virtual bool AddRules() + { + printf("Entering %s, %s()\n",__FUNCTION__, __FILE__); + + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + struct ipa_ioc_get_rt_tbl routing_table0,routing_table1,routing_table2; + + if (!CreateThreeIPv4BypassRoutingTables (bypass0,bypass1,bypass2)) + { + printf("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + + printf("CreateThreeBypassRoutingTables completed successfully\n"); + routing_table0.ip = IPA_IP_v4; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + printf("m_routing.GetRoutingTable(&routing_table0=0x%p) Failed.\n",&routing_table0); + return false; + } + printf("%s route table handle = %u\n", bypass0, routing_table0.hdl); + + routing_table1.ip = IPA_IP_v4; + strlcpy(routing_table1.name, bypass1, sizeof(routing_table1.name)); + if (!m_routing.GetRoutingTable(&routing_table1)) + { + printf("m_routing.GetRoutingTable(&routing_table1=0x%p) Failed.\n",&routing_table1); + return false; + } + printf("%s route table handle = %u\n", bypass1, routing_table1.hdl); + + routing_table2.ip = IPA_IP_v4; + strlcpy(routing_table2.name, bypass2, sizeof(routing_table2.name)); + if (!m_routing.GetRoutingTable(&routing_table2)) + { + printf("m_routing.GetRoutingTable(&routing_table2=0x%p) Failed.\n",&routing_table2); + return false; + } + printf("%s route table handle = %u\n", bypass2, routing_table2.hdl); + + IPAFilteringTable_v2 FilterTable0; + struct ipa_flt_rule_add_v2 flt_rule_entry; + FilterTable0.Init(IPA_IP_v4,IPA_CLIENT_TEST_PROD,false,3); + printf("FilterTable*.Init Completed Successfully..\n"); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1,flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl=-1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action=IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.rt_tbl_hdl=routing_table0.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + flt_rule_entry.rule.attrib.u.v4.dst_addr_mask = 0xFF0000FF; // Mask + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0x7F000001; // Filter DST_IP == 127.0.0.1. + flt_rule_entry.rule.ttl_update = 1; // require ttl update + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.1 + flt_rule_entry.rule.rt_tbl_hdl=routing_table1.hdl; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0xC0A80101; // Filter DST_IP == 192.168.1.1. + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.2 + flt_rule_entry.rule.rt_tbl_hdl=routing_table2.hdl; //put here the handle corresponding to Routing Rule 2 + // TODO: Fix this, doesn't match the Rule's Requirements + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0xC0A80102; // Filter DST_IP == 192.168.1.2. + flt_rule_entry.rule.ttl_update = 0; // doesn't require ttl update + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(0)->status); + printf("flt rule hdl1=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(1)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(1)->status); + printf("flt rule hdl2=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(2)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(2)->status); + } + + printf("Leaving %s, %s()\n",__FUNCTION__, __FILE__); + return true; + }// AddRules() + + virtual bool ModifyPackets() + { + int address; + address = ntohl(0x7F000001);//127.0.0.1 + memcpy(&m_sendBuffer[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + m_sendBuffer[IPV4_TTL_OFFSET] = 5; + address = ntohl(0xC0A80101);//192.168.1.1 + memcpy(&m_sendBuffer2[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + m_sendBuffer2[IPV4_TTL_OFFSET] = 4; + address = ntohl(0xC0A80102);//192.168.1.2 + memcpy(&m_sendBuffer3[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + m_sendBuffer3[IPV4_TTL_OFFSET] = 3; + return true; + }// ModifyPacktes () + + virtual bool ReceivePacketsAndCompare() + { + size_t receivedSize = 0; + size_t receivedSize2 = 0; + size_t receivedSize3 = 0; + uint16_t csum = 0; + bool pkt1_cmp_succ, pkt2_cmp_succ, pkt3_cmp_succ; + + // Receive results + Byte *rxBuff1 = new Byte[0x400]; + Byte *rxBuff2 = new Byte[0x400]; + Byte *rxBuff3 = new Byte[0x400]; + + if (NULL == rxBuff1 || NULL == rxBuff2 || NULL == rxBuff3) + { + printf("Memory allocation error.\n"); + return false; + } + + memset(rxBuff1, 0, 0x400); + memset(rxBuff2, 0, 0x400); + memset(rxBuff3, 0, 0x400); + + receivedSize = m_consumer.ReceiveData(rxBuff1, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize, m_consumer.m_fromChannelName.c_str()); + + receivedSize2 = m_consumer2.ReceiveData(rxBuff2, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize2, m_consumer2.m_fromChannelName.c_str()); + + receivedSize3 = m_defaultConsumer.ReceiveData(rxBuff3, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize3, m_defaultConsumer.m_fromChannelName.c_str()); + + /* Update TTL values. */ + m_sendBuffer[IPV4_TTL_OFFSET] = 4; + m_sendBuffer2[IPV4_TTL_OFFSET] = 3; + + /* Update Checksum.*/ + csum = *((uint16_t *)(m_sendBuffer + IPV4_CSUM_OFFSET)); + csum += 1; + *((uint16_t *)(m_sendBuffer+ IPV4_CSUM_OFFSET)) = csum; + + csum = *((uint16_t *)(m_sendBuffer2 + IPV4_CSUM_OFFSET)); + csum += 1; + *((uint16_t *)(m_sendBuffer2 + IPV4_CSUM_OFFSET)) = csum; + + // Compare results + pkt1_cmp_succ = CompareResultVsGolden_w_Status(m_sendBuffer, m_sendSize, rxBuff1, receivedSize); + pkt2_cmp_succ = CompareResultVsGolden_w_Status(m_sendBuffer2, m_sendSize2, rxBuff2, receivedSize2); + pkt3_cmp_succ = CompareResultVsGolden_w_Status(m_sendBuffer3, m_sendSize3, rxBuff3, receivedSize3); + + pkt1_cmp_succ &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_5) ? + IsTTLUpdated_v5_5(m_sendSize, receivedSize, rxBuff1) : true; + pkt2_cmp_succ &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_5) ? + IsTTLUpdated_v5_5(m_sendSize2, receivedSize2, rxBuff2) : true; + pkt3_cmp_succ &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_5) ? + !IsTTLUpdated_v5_5(m_sendSize3, receivedSize3, rxBuff3) : true; + + size_t recievedBufferSize = + MAX3(receivedSize, receivedSize2, receivedSize3) * 3; + size_t sentBufferSize = + MAX3(m_sendSize, m_sendSize2, m_sendSize3) * 3; + char *recievedBuffer = new char[recievedBufferSize]; + char *sentBuffer = new char[sentBufferSize]; + size_t j; + + if (NULL == recievedBuffer || NULL == sentBuffer) { + printf("Memory allocation error\n"); + return false; + } + + memset(recievedBuffer, 0, recievedBufferSize); + memset(sentBuffer, 0, sentBufferSize); + for(j = 0; j < m_sendSize; j++) + snprintf(&sentBuffer[3 * j], sentBufferSize - (3 * j + 1), " %02X", m_sendBuffer[j]); + for(j = 0; j < receivedSize; j++) + snprintf(&recievedBuffer[3 * j], recievedBufferSize - (3 * j + 1), " %02X", rxBuff1[j]); + printf("Expected Value1 (%zu)\n%s\n, Received Value1(%zu)\n%s\n-->Value1 %s\n", + m_sendSize,sentBuffer,receivedSize,recievedBuffer, + pkt1_cmp_succ?"Match":"no Match"); + + memset(recievedBuffer, 0, recievedBufferSize); + memset(sentBuffer, 0, sentBufferSize); + for(j = 0; j < m_sendSize2; j++) + snprintf(&sentBuffer[3 * j], sentBufferSize - (3 * j + 1), " %02X", m_sendBuffer2[j]); + for(j = 0; j < receivedSize2; j++) + snprintf(&recievedBuffer[3 * j], recievedBufferSize - (3 * j + 1), " %02X", rxBuff2[j]); + printf("Expected Value2 (%zu)\n%s\n, Received Value2(%zu)\n%s\n-->Value2 %s\n", + m_sendSize2,sentBuffer,receivedSize2,recievedBuffer, + pkt2_cmp_succ?"Match":"no Match"); + + memset(recievedBuffer, 0, recievedBufferSize); + memset(sentBuffer, 0, sentBufferSize); + for(j = 0; j < m_sendSize3; j++) + snprintf(&sentBuffer[3 * j], sentBufferSize - (3 * j + 1), " %02X", m_sendBuffer3[j]); + for(j = 0; j < receivedSize3; j++) + snprintf(&recievedBuffer[3 * j], recievedBufferSize - (3 * j + 1), " %02X", rxBuff3[j]); + printf("Expected Value3 (%zu)\n%s\n, Received Value3(%zu)\n%s\n-->Value3 %s\n", + m_sendSize3,sentBuffer,receivedSize3,recievedBuffer, + pkt3_cmp_succ?"Match":"no Match"); + + delete[] recievedBuffer; + delete[] sentBuffer; + + delete[] rxBuff1; + delete[] rxBuff2; + delete[] rxBuff3; + + return pkt1_cmp_succ && pkt2_cmp_succ && pkt3_cmp_succ; + } + + virtual bool Teardown() + { + return true; + } // Teardown() +}; + +/*-----------------------------------------------------------------------------------------------------------------*/ +/* Test113: TTL update based on Destination IPv6 address and Subnet Mask exact match against broadcast IP address */ +/*-----------------------------------------------------------------------------------------------------------------*/ +class IpaFilteringBlockTest113 : public IpaFilteringBlockTestFixture +{ +public: + IpaFilteringBlockTest113() + { + m_name = "IpaFilteringBlockTest113"; + m_description = + "Filtering block test 113 - TTL update based on Destination IPv6 address and Mask exact match against broadcast IP address (End-Point specific Filtering Table, Insert all rules in a single commit)\ + 1. Generate and commit three routing tables. \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly with TTL update)) \ + 2. Generate and commit three filtering rules: (DST & Mask Match). \ + All DST_IPv6 == 0x...AA traffic goes to routing table 1 \ + All DST_IPv6 == 0x...BB traffic goes to routing table 2 \ + All DST_IPv6 == 0x...CC traffic goes to routing table 3 \ + 3. Check if TTL is updated in packet and status."; + m_IpaIPType = IPA_IP_v6; + m_minIPAHwType = IPA_HW_v5_5; + Register(*this); + } + + bool Setup() + { + /* we want statuses on this test */ + return IpaFilteringBlockTestFixture::Setup(true); + } + + virtual bool AddRules() + { + printf("Entering %s, %s()\n",__FUNCTION__, __FILE__); + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + struct ipa_ioc_get_rt_tbl routing_table0,routing_table1,routing_table2; + + if (!CreateThreeIPv6BypassRoutingTables (bypass0,bypass1,bypass2)) + { + printf("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + + printf("CreateThreeBypassRoutingTables completed successfully\n"); + routing_table0.ip = IPA_IP_v6; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + printf("m_routing.GetRoutingTable(&routing_table0=0x%p) Failed.\n",&routing_table0); + return false; + } + routing_table1.ip = IPA_IP_v6; + strlcpy(routing_table1.name, bypass1, sizeof(routing_table1.name)); + if (!m_routing.GetRoutingTable(&routing_table1)) + { + printf("m_routing.GetRoutingTable(&routing_table1=0x%p) Failed.\n",&routing_table1); + return false; + } + + routing_table2.ip = IPA_IP_v6; + strlcpy(routing_table2.name, bypass2, sizeof(routing_table2.name)); + if (!m_routing.GetRoutingTable(&routing_table2)) + { + printf("m_routing.GetRoutingTable(&routing_table2=0x%p) Failed.\n",&routing_table2); + return false; + } + + IPAFilteringTable_v2 FilterTable0; + struct ipa_flt_rule_add_v2 flt_rule_entry; + FilterTable0.Init(IPA_IP_v6,IPA_CLIENT_TEST_PROD,false,3); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1,flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl=-1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action=IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.rt_tbl_hdl=routing_table0.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; // TODO: Fix this, doesn't match the Rule's Requirements + + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[0] = 0xFFFFFFFF;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[1] = 0xFFFFFFFF;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[2] = 0x00000000;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[3] = 0x000000FF;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr[0] = 0XFF020000; // Filter DST_IP + flt_rule_entry.rule.attrib.u.v6.dst_addr[1] = 0x00000000; + flt_rule_entry.rule.attrib.u.v6.dst_addr[2] = 0x11223344; + flt_rule_entry.rule.attrib.u.v6.dst_addr[3] = 0X556677AA; + + /* Enable ttl update in HW */ + flt_rule_entry.rule.ttl_update = 1; + printf ("flt_rule_entry was set successfully, preparing for insertion....\n"); + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } + // Configuring Filtering Rule No.1 + flt_rule_entry.rule.rt_tbl_hdl=routing_table1.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.u.v6.dst_addr[3] = 0X556677BB; + /* Disable ttl update in HW */ + flt_rule_entry.rule.ttl_update = 0; + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.2 + flt_rule_entry.rule.rt_tbl_hdl=routing_table2.hdl; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.attrib.u.v6.dst_addr[3] = 0X556677CC; + /* Enable ttl update in HW */ + flt_rule_entry.rule.ttl_update = 1; + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(0)->status); + printf("flt rule hdl1=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(1)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(1)->status); + printf("flt rule hdl2=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(2)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(2)->status); + } + printf("Leaving %s, %s()\n",__FUNCTION__, __FILE__); + return true; + }// AddRules() + + virtual bool ModifyPackets() + { + // TODO: Add verification that we access only allocated addresses + // TODO: Fix this, doesn't match the Rule's Requirements + m_sendBuffer[DST_ADDR_LSB_OFFSET_IPV6] = 0xAA; + m_sendBuffer[HOP_LIMIT_OFFSET_IPV6] = 5; + m_sendBuffer2[DST_ADDR_LSB_OFFSET_IPV6] = 0xBB; + m_sendBuffer2[HOP_LIMIT_OFFSET_IPV6] = 4; + m_sendBuffer3[DST_ADDR_LSB_OFFSET_IPV6] = 0xCC; + m_sendBuffer3[HOP_LIMIT_OFFSET_IPV6] = 3; + return true; + }// ModifyPacktes () + + virtual bool ReceivePacketsAndCompare() + { + size_t receivedSize = 0; + size_t receivedSize2 = 0; + size_t receivedSize3 = 0; + bool pkt1_cmp_succ, pkt2_cmp_succ, pkt3_cmp_succ; + + // Receive results + Byte *rxBuff1 = new Byte[0x400]; + Byte *rxBuff2 = new Byte[0x400]; + Byte *rxBuff3 = new Byte[0x400]; + + if (NULL == rxBuff1 || NULL == rxBuff2 || NULL == rxBuff3) + { + printf("Memory allocation error.\n"); + return false; + } + + memset(rxBuff1, 0, 0x400); + memset(rxBuff2, 0, 0x400); + memset(rxBuff3, 0, 0x400); + + receivedSize = m_consumer.ReceiveData(rxBuff1, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize, m_consumer.m_fromChannelName.c_str()); + + receivedSize2 = m_consumer2.ReceiveData(rxBuff2, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize2, m_consumer2.m_fromChannelName.c_str()); + + receivedSize3 = m_defaultConsumer.ReceiveData(rxBuff3, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize3, m_defaultConsumer.m_fromChannelName.c_str()); + + /* Update TTL values. */ + m_sendBuffer[HOP_LIMIT_OFFSET_IPV6] = 4; + m_sendBuffer3[HOP_LIMIT_OFFSET_IPV6] = 2; + + // Compare results + pkt1_cmp_succ = CompareResultVsGolden_w_Status(m_sendBuffer, m_sendSize, rxBuff1, receivedSize); + pkt2_cmp_succ = CompareResultVsGolden_w_Status(m_sendBuffer2, m_sendSize2, rxBuff2, receivedSize2); + pkt3_cmp_succ = CompareResultVsGolden_w_Status(m_sendBuffer3, m_sendSize3, rxBuff3, receivedSize3); + + pkt1_cmp_succ &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_5) ? + IsTTLUpdated_v5_5(m_sendSize, receivedSize, rxBuff1) : true; + pkt2_cmp_succ &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_5) ? + IsTTLUpdated_v5_5(m_sendSize2, receivedSize2, rxBuff2) : true; + pkt3_cmp_succ &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_5) ? + !IsTTLUpdated_v5_5(m_sendSize3, receivedSize3, rxBuff3) : true; + + size_t recievedBufferSize = + MAX3(receivedSize, receivedSize2, receivedSize3) * 3; + size_t sentBufferSize = + MAX3(m_sendSize, m_sendSize2, m_sendSize3) * 3; + char *recievedBuffer = new char[recievedBufferSize]; + char *sentBuffer = new char[sentBufferSize]; + size_t j; + + if (NULL == recievedBuffer || NULL == sentBuffer) { + printf("Memory allocation error\n"); + return false; + } + + memset(recievedBuffer, 0, recievedBufferSize); + memset(sentBuffer, 0, sentBufferSize); + for(j = 0; j < m_sendSize; j++) + snprintf(&sentBuffer[3 * j], sentBufferSize - (3 * j + 1), " %02X", m_sendBuffer[j]); + for(j = 0; j < receivedSize; j++) + snprintf(&recievedBuffer[3 * j], recievedBufferSize - (3 * j + 1), " %02X", rxBuff1[j]); + printf("Expected Value1 (%zu)\n%s\n, Received Value1(%zu)\n%s\n-->Value1 %s\n", + m_sendSize,sentBuffer,receivedSize,recievedBuffer, + pkt1_cmp_succ?"Match":"no Match"); + + memset(recievedBuffer, 0, recievedBufferSize); + memset(sentBuffer, 0, sentBufferSize); + for(j = 0; j < m_sendSize2; j++) + snprintf(&sentBuffer[3 * j], sentBufferSize - (3 * j + 1), " %02X", m_sendBuffer2[j]); + for(j = 0; j < receivedSize2; j++) + snprintf(&recievedBuffer[3 * j], recievedBufferSize - (3 * j + 1), " %02X", rxBuff2[j]); + printf("Expected Value2 (%zu)\n%s\n, Received Value2(%zu)\n%s\n-->Value2 %s\n", + m_sendSize2,sentBuffer,receivedSize2,recievedBuffer, + pkt2_cmp_succ?"Match":"no Match"); + + memset(recievedBuffer, 0, recievedBufferSize); + memset(sentBuffer, 0, sentBufferSize); + for(j = 0; j < m_sendSize3; j++) + snprintf(&sentBuffer[3 * j], sentBufferSize - (3 * j + 1), " %02X", m_sendBuffer3[j]); + for(j = 0; j < receivedSize3; j++) + snprintf(&recievedBuffer[3 * j], recievedBufferSize - (3 * j + 1), " %02X", rxBuff3[j]); + printf("Expected Value3 (%zu)\n%s\n, Received Value3(%zu)\n%s\n-->Value3 %s\n", + m_sendSize3,sentBuffer,receivedSize3,recievedBuffer, + pkt3_cmp_succ?"Match":"no Match"); + + delete[] recievedBuffer; + delete[] sentBuffer; + + delete[] rxBuff1; + delete[] rxBuff2; + delete[] rxBuff3; + + return pkt1_cmp_succ && pkt2_cmp_succ && pkt3_cmp_succ; + } + +}; + +/*---------------------------------------------------------------------------*/ +/* Test114: IPv4 TTL exception test */ +/*---------------------------------------------------------------------------*/ +class IpaFilteringBlockTest114 : public IpaFilteringBlockTestFixture +{ +public: + IpaFilteringBlockTest114() + { + m_name = "IpaFilteringBlockTest114"; + m_description = " \ + Filtering block test 114 - IPv4 with TTL exception and TTL=1 \ + 1. Add filtering rule with TTL decrement marked as 1 \ + 2. Send packet with TTL=1 \ + 3. Verify packet arrival on the exception pipe \ + 4. Verify that the packet was not modified \ + 5. Verify packet status for the TTL exception"; + m_minIPAHwType = IPA_HW_v5_5; + Register(*this); + } + + + bool Setup() + { + /* we want statuses on this test */ + return IpaFilteringBlockTestFixture::Setup(true); + } + + virtual bool AddRules() + { + printf("Entering %s, %s()\n",__FUNCTION__, __FILE__); + + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + struct ipa_ioc_get_rt_tbl routing_table0,routing_table1,routing_table2; + + if (!CreateThreeIPv4BypassRoutingTables (bypass0,bypass1,bypass2)) + { + printf("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + + printf("CreateThreeBypassRoutingTables completed successfully\n"); + routing_table0.ip = IPA_IP_v4; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + printf("m_routing.GetRoutingTable(&routing_table0=0x%p) Failed.\n",&routing_table0); + return false; + } + printf("%s route table handle = %u\n", bypass0, routing_table0.hdl); + + routing_table1.ip = IPA_IP_v4; + strlcpy(routing_table1.name, bypass1, sizeof(routing_table1.name)); + if (!m_routing.GetRoutingTable(&routing_table1)) + { + printf("m_routing.GetRoutingTable(&routing_table1=0x%p) Failed.\n",&routing_table1); + return false; + } + printf("%s route table handle = %u\n", bypass1, routing_table1.hdl); + + routing_table2.ip = IPA_IP_v4; + strlcpy(routing_table2.name, bypass2, sizeof(routing_table2.name)); + if (!m_routing.GetRoutingTable(&routing_table2)) + { + printf("m_routing.GetRoutingTable(&routing_table2=0x%p) Failed.\n",&routing_table2); + return false; + } + printf("%s route table handle = %u\n", bypass2, routing_table2.hdl); + + IPAFilteringTable_v2 FilterTable0; + struct ipa_flt_rule_add_v2 flt_rule_entry; + FilterTable0.Init(IPA_IP_v4,IPA_CLIENT_TEST_PROD,false,3); + printf("FilterTable*.Init Completed Successfully..\n"); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1,flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl=-1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action=IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.rt_tbl_hdl=routing_table0.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.ttl_update = 1; // require ttl update + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.1 + flt_rule_entry.rule.rt_tbl_hdl=routing_table1.hdl; //put here the handle corresponding to Routing Rule 2 + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.2 + flt_rule_entry.rule.rt_tbl_hdl=routing_table2.hdl; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.ttl_update = 1; + flt_rule_entry.rule.ttl_update = 0; // doesn't require ttl update + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(0)->status); + printf("flt rule hdl1=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(1)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(1)->status); + printf("flt rule hdl2=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(2)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(2)->status); + } + + printf("Leaving %s, %s()\n",__FUNCTION__, __FILE__); + return true; + }// AddRules() + + virtual bool ModifyPackets() + { + int address; + + m_sendBuffer[IPV4_TTL_OFFSET] = 1; + m_sendBuffer2[IPV4_TTL_OFFSET] = 1; + m_sendBuffer3[IPV4_TTL_OFFSET] = 1; + return true; + }// ModifyPacktes () + + virtual bool ReceivePacketsAndCompare() + { + size_t receivedSize = 0; + size_t receivedSize2 = 0; + size_t receivedSize3 = 0; + bool pkt1_cmp_succ, pkt2_cmp_succ, pkt3_cmp_succ; + + // Receive results + Byte *rxBuff1 = new Byte[0x400]; + Byte *rxBuff2 = new Byte[0x400]; + Byte *rxBuff3 = new Byte[0x400]; + + if (NULL == rxBuff1 || NULL == rxBuff2 || NULL == rxBuff3) + { + printf("Memory allocation error.\n"); + return false; + } + + memset(rxBuff1, 0, 0x400); + memset(rxBuff2, 0, 0x400); + memset(rxBuff3, 0, 0x400); + + receivedSize = m_Exceptions.ReceiveData(rxBuff1, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize, m_Exceptions.m_fromChannelName.c_str()); + + receivedSize2 = m_Exceptions.ReceiveData(rxBuff2, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize2, m_Exceptions.m_fromChannelName.c_str()); + + receivedSize3 = m_Exceptions.ReceiveData(rxBuff3, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize3, m_Exceptions.m_fromChannelName.c_str()); + + /* Update TTL values. */ + m_sendBuffer[IPV4_TTL_OFFSET] = 1; + m_sendBuffer2[IPV4_TTL_OFFSET] = 1; + m_sendBuffer3[IPV4_TTL_OFFSET] = 1; + + // Compare results + pkt1_cmp_succ = CompareResultVsGolden(m_sendBuffer, m_sendSize, rxBuff1, receivedSize); + pkt2_cmp_succ = CompareResultVsGolden(m_sendBuffer2, m_sendSize2, rxBuff2, receivedSize2); + pkt3_cmp_succ = CompareResultVsGolden(m_sendBuffer3, m_sendSize3, rxBuff3, receivedSize3); + + pkt1_cmp_succ &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_5) ? + IsTTLUpdated_v5_5_wo_status(m_sendSize, receivedSize, rxBuff1) : true; + pkt2_cmp_succ &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_5) ? + IsTTLUpdated_v5_5_wo_status(m_sendSize2, receivedSize2, rxBuff2) : true; + pkt3_cmp_succ &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_5) ? + IsTTLUpdated_v5_5_wo_status(m_sendSize3, receivedSize3, rxBuff3) : true; + + size_t recievedBufferSize = + MAX3(receivedSize, receivedSize2, receivedSize3) * 3; + size_t sentBufferSize = + MAX3(m_sendSize, m_sendSize2, m_sendSize3) * 3; + char *recievedBuffer = new char[recievedBufferSize]; + char *sentBuffer = new char[sentBufferSize]; + size_t j; + + if (NULL == recievedBuffer || NULL == sentBuffer) { + printf("Memory allocation error\n"); + return false; + } + + memset(recievedBuffer, 0, recievedBufferSize); + memset(sentBuffer, 0, sentBufferSize); + for(j = 0; j < m_sendSize; j++) + snprintf(&sentBuffer[3 * j], sentBufferSize - (3 * j + 1), " %02X", m_sendBuffer[j]); + for(j = 0; j < receivedSize; j++) + snprintf(&recievedBuffer[3 * j], recievedBufferSize - (3 * j + 1), " %02X", rxBuff1[j]); + printf("Expected Value1 (%zu)\n%s\n, Received Value1(%zu)\n%s\n-->Value1 %s\n", + m_sendSize,sentBuffer,receivedSize,recievedBuffer, + pkt1_cmp_succ?"Match":"no Match"); + + memset(recievedBuffer, 0, recievedBufferSize); + memset(sentBuffer, 0, sentBufferSize); + for(j = 0; j < m_sendSize2; j++) + snprintf(&sentBuffer[3 * j], sentBufferSize - (3 * j + 1), " %02X", m_sendBuffer2[j]); + for(j = 0; j < receivedSize2; j++) + snprintf(&recievedBuffer[3 * j], recievedBufferSize - (3 * j + 1), " %02X", rxBuff2[j]); + printf("Expected Value2 (%zu)\n%s\n, Received Value2(%zu)\n%s\n-->Value2 %s\n", + m_sendSize2,sentBuffer,receivedSize2,recievedBuffer, + pkt2_cmp_succ?"Match":"no Match"); + + memset(recievedBuffer, 0, recievedBufferSize); + memset(sentBuffer, 0, sentBufferSize); + for(j = 0; j < m_sendSize3; j++) + snprintf(&sentBuffer[3 * j], sentBufferSize - (3 * j + 1), " %02X", m_sendBuffer3[j]); + for(j = 0; j < receivedSize3; j++) + snprintf(&recievedBuffer[3 * j], recievedBufferSize - (3 * j + 1), " %02X", rxBuff3[j]); + printf("Expected Value3 (%zu)\n%s\n, Received Value3(%zu)\n%s\n-->Value3 %s\n", + m_sendSize3,sentBuffer,receivedSize3,recievedBuffer, + pkt3_cmp_succ?"Match":"no Match"); + + delete[] recievedBuffer; + delete[] sentBuffer; + + delete[] rxBuff1; + delete[] rxBuff2; + delete[] rxBuff3; + + return pkt1_cmp_succ && pkt2_cmp_succ && pkt3_cmp_succ; + } + + virtual bool Teardown() + { + return true; + } // Teardown() +}; + +/*---------------------------------------------------------------------------*/ +/* Test115: IPv6 TTL exception test */ +/*---------------------------------------------------------------------------*/ +class IpaFilteringBlockTest115 : public IpaFilteringBlockTestFixture +{ +public: + IpaFilteringBlockTest115() + { + m_name = "IpaFilteringBlockTest115"; + m_description = " \ + Filtering block test 115 - IPv6 with TTL exception and TTL=1 \ + 1. Add filtering rule with TTL decrement marked as 1 \ + 2. Send packet with TTL=1 \ + 3. Verify packet arrival on the exception pipe \ + 4. Verify that the packet was not modified \ + 5. Verify packet status for the TTL exception"; + m_minIPAHwType = IPA_HW_v5_5; + Register(*this); + } + + + bool Setup() + { + /* we want statuses on this test */ + return IpaFilteringBlockTestFixture::Setup(true); + } + + virtual bool AddRules() + { + printf("Entering %s, %s()\n",__FUNCTION__, __FILE__); + + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + struct ipa_ioc_get_rt_tbl routing_table0,routing_table1,routing_table2; + + if (!CreateThreeIPv6BypassRoutingTables(bypass0,bypass1,bypass2)) + { + printf("CreateThreeIPv6BypassRoutingTables Failed\n"); + return false; + } + + printf("CreateThreeIPv6BypassRoutingTables completed successfully\n"); + routing_table0.ip = IPA_IP_v6; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + printf("m_routing.GetRoutingTable(&routing_table0=0x%p) Failed.\n",&routing_table0); + return false; + } + printf("%s route table handle = %u\n", bypass0, routing_table0.hdl); + + routing_table1.ip = IPA_IP_v6; + strlcpy(routing_table1.name, bypass1, sizeof(routing_table1.name)); + if (!m_routing.GetRoutingTable(&routing_table1)) + { + printf("m_routing.GetRoutingTable(&routing_table1=0x%p) Failed.\n",&routing_table1); + return false; + } + printf("%s route table handle = %u\n", bypass1, routing_table1.hdl); + + routing_table2.ip = IPA_IP_v6; + strlcpy(routing_table2.name, bypass2, sizeof(routing_table2.name)); + if (!m_routing.GetRoutingTable(&routing_table2)) + { + printf("m_routing.GetRoutingTable(&routing_table2=0x%p) Failed.\n",&routing_table2); + return false; + } + printf("%s route table handle = %u\n", bypass2, routing_table2.hdl); + + IPAFilteringTable_v2 FilterTable0; + struct ipa_flt_rule_add_v2 flt_rule_entry; + FilterTable0.Init(IPA_IP_v6,IPA_CLIENT_TEST_PROD,false,3); + printf("FilterTable*.Init Completed Successfully..\n"); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1,flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl=-1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action=IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.rt_tbl_hdl=routing_table0.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + flt_rule_entry.rule.ttl_update = 1; // require ttl update + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.1 + flt_rule_entry.rule.rt_tbl_hdl=routing_table1.hdl; //put here the handle corresponding to Routing Rule 2 + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.2 + flt_rule_entry.rule.rt_tbl_hdl=routing_table2.hdl; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.ttl_update = 1; + flt_rule_entry.rule.ttl_update = 0; // doesn't require ttl update + + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(0)->status); + printf("flt rule hdl1=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(1)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(1)->status); + printf("flt rule hdl2=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(2)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(2)->status); + } + + printf("Leaving %s, %s()\n",__FUNCTION__, __FILE__); + return true; + }// AddRules() + + virtual bool ModifyPackets() + { + int address; + + m_sendBuffer[HOP_LIMIT_OFFSET_IPV6] = 1; + m_sendBuffer2[HOP_LIMIT_OFFSET_IPV6] = 1; + m_sendBuffer3[HOP_LIMIT_OFFSET_IPV6] = 1; + return true; + }// ModifyPacktes () + + virtual bool ReceivePacketsAndCompare() + { + size_t receivedSize = 0; + size_t receivedSize2 = 0; + size_t receivedSize3 = 0; + bool pkt1_cmp_succ, pkt2_cmp_succ, pkt3_cmp_succ; + + // Receive results + Byte *rxBuff1 = new Byte[0x400]; + Byte *rxBuff2 = new Byte[0x400]; + Byte *rxBuff3 = new Byte[0x400]; + + if (NULL == rxBuff1 || NULL == rxBuff2 || NULL == rxBuff3) + { + printf("Memory allocation error.\n"); + return false; + } + + memset(rxBuff1, 0, 0x400); + memset(rxBuff2, 0, 0x400); + memset(rxBuff3, 0, 0x400); + + receivedSize = m_Exceptions.ReceiveData(rxBuff1, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize, m_Exceptions.m_fromChannelName.c_str()); + + receivedSize2 = m_Exceptions.ReceiveData(rxBuff2, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize2, m_Exceptions.m_fromChannelName.c_str()); + + receivedSize3 = m_Exceptions.ReceiveData(rxBuff3, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize3, m_Exceptions.m_fromChannelName.c_str()); + + /* Update TTL values. */ + m_sendBuffer[HOP_LIMIT_OFFSET_IPV6] = 1; + m_sendBuffer2[HOP_LIMIT_OFFSET_IPV6] = 1; + m_sendBuffer3[HOP_LIMIT_OFFSET_IPV6] = 1; + + // Compare results + pkt1_cmp_succ = CompareResultVsGolden(m_sendBuffer, m_sendSize, rxBuff1, receivedSize); + pkt2_cmp_succ = CompareResultVsGolden(m_sendBuffer2, m_sendSize2, rxBuff2, receivedSize2); + pkt3_cmp_succ = CompareResultVsGolden(m_sendBuffer3, m_sendSize3, rxBuff3, receivedSize3); + + pkt1_cmp_succ &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_5) ? + IsTTLUpdated_v5_5_wo_status(m_sendSize, receivedSize, rxBuff1) : true; + pkt2_cmp_succ &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_5) ? + IsTTLUpdated_v5_5_wo_status(m_sendSize2, receivedSize2, rxBuff2) : true; + pkt3_cmp_succ &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_5) ? + IsTTLUpdated_v5_5_wo_status(m_sendSize3, receivedSize3, rxBuff3) : true; + + size_t recievedBufferSize = + MAX3(receivedSize, receivedSize2, receivedSize3) * 3; + size_t sentBufferSize = + MAX3(m_sendSize, m_sendSize2, m_sendSize3) * 3; + char *recievedBuffer = new char[recievedBufferSize]; + char *sentBuffer = new char[sentBufferSize]; + size_t j; + + if (NULL == recievedBuffer || NULL == sentBuffer) { + printf("Memory allocation error\n"); + return false; + } + + memset(recievedBuffer, 0, recievedBufferSize); + memset(sentBuffer, 0, sentBufferSize); + for(j = 0; j < m_sendSize; j++) + snprintf(&sentBuffer[3 * j], sentBufferSize - (3 * j + 1), " %02X", m_sendBuffer[j]); + for(j = 0; j < receivedSize; j++) + snprintf(&recievedBuffer[3 * j], recievedBufferSize - (3 * j + 1), " %02X", rxBuff1[j]); + printf("Expected Value1 (%zu)\n%s\n, Received Value1(%zu)\n%s\n-->Value1 %s\n", + m_sendSize,sentBuffer,receivedSize,recievedBuffer, + pkt1_cmp_succ?"Match":"no Match"); + + memset(recievedBuffer, 0, recievedBufferSize); + memset(sentBuffer, 0, sentBufferSize); + for(j = 0; j < m_sendSize2; j++) + snprintf(&sentBuffer[3 * j], sentBufferSize - (3 * j + 1), " %02X", m_sendBuffer2[j]); + for(j = 0; j < receivedSize2; j++) + snprintf(&recievedBuffer[3 * j], recievedBufferSize - (3 * j + 1), " %02X", rxBuff2[j]); + printf("Expected Value2 (%zu)\n%s\n, Received Value2(%zu)\n%s\n-->Value2 %s\n", + m_sendSize2,sentBuffer,receivedSize2,recievedBuffer, + pkt2_cmp_succ?"Match":"no Match"); + + memset(recievedBuffer, 0, recievedBufferSize); + memset(sentBuffer, 0, sentBufferSize); + for(j = 0; j < m_sendSize3; j++) + snprintf(&sentBuffer[3 * j], sentBufferSize - (3 * j + 1), " %02X", m_sendBuffer3[j]); + for(j = 0; j < receivedSize3; j++) + snprintf(&recievedBuffer[3 * j], recievedBufferSize - (3 * j + 1), " %02X", rxBuff3[j]); + printf("Expected Value3 (%zu)\n%s\n, Received Value3(%zu)\n%s\n-->Value3 %s\n", + m_sendSize3,sentBuffer,receivedSize3,recievedBuffer, + pkt3_cmp_succ?"Match":"no Match"); + + delete[] recievedBuffer; + delete[] sentBuffer; + + delete[] rxBuff1; + delete[] rxBuff2; + delete[] rxBuff3; + + return pkt1_cmp_succ && pkt2_cmp_succ && pkt3_cmp_succ; + } + + virtual bool Teardown() + { + return true; + } // Teardown() +}; + +/*---------------------------------------------------------------------------*/ +/* Test114: IPv4 TTL exception test */ +/*---------------------------------------------------------------------------*/ +class IpaFilteringBlockTest116 : public IpaFilteringBlockTestFixture +{ +public: + IpaFilteringBlockTest116() + { + m_name = "IpaFilteringBlockTest116"; + m_description = " \ + Filtering block test 116 - IPv4 with TTL exception and TTL=0 \ + 1. Add filtering rule with TTL decrement marked as 1 \ + 2. Send packet with TTL=0 \ + 3. Verify packet arrival on the exception pipe \ + 4. Verify that the packet was not modified \ + 5. Verify packet status for the TTL exception"; + m_minIPAHwType = IPA_HW_v5_5; + Register(*this); + } + + + bool Setup() + { + /* we want statuses on this test */ + return IpaFilteringBlockTestFixture::Setup(true); + } + + virtual bool AddRules() + { + printf("Entering %s, %s()\n",__FUNCTION__, __FILE__); + + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + struct ipa_ioc_get_rt_tbl routing_table0,routing_table1,routing_table2; + + if (!CreateThreeIPv4BypassRoutingTables (bypass0,bypass1,bypass2)) + { + printf("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + + printf("CreateThreeBypassRoutingTables completed successfully\n"); + routing_table0.ip = IPA_IP_v4; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + printf("m_routing.GetRoutingTable(&routing_table0=0x%p) Failed.\n",&routing_table0); + return false; + } + printf("%s route table handle = %u\n", bypass0, routing_table0.hdl); + + routing_table1.ip = IPA_IP_v4; + strlcpy(routing_table1.name, bypass1, sizeof(routing_table1.name)); + if (!m_routing.GetRoutingTable(&routing_table1)) + { + printf("m_routing.GetRoutingTable(&routing_table1=0x%p) Failed.\n",&routing_table1); + return false; + } + printf("%s route table handle = %u\n", bypass1, routing_table1.hdl); + + routing_table2.ip = IPA_IP_v4; + strlcpy(routing_table2.name, bypass2, sizeof(routing_table2.name)); + if (!m_routing.GetRoutingTable(&routing_table2)) + { + printf("m_routing.GetRoutingTable(&routing_table2=0x%p) Failed.\n",&routing_table2); + return false; + } + printf("%s route table handle = %u\n", bypass2, routing_table2.hdl); + + IPAFilteringTable_v2 FilterTable0; + struct ipa_flt_rule_add_v2 flt_rule_entry; + FilterTable0.Init(IPA_IP_v4,IPA_CLIENT_TEST_PROD,false,3); + printf("FilterTable*.Init Completed Successfully..\n"); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1,flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl=-1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action=IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.rt_tbl_hdl=routing_table0.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.ttl_update = 1; // require ttl update + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.1 + flt_rule_entry.rule.rt_tbl_hdl=routing_table1.hdl; //put here the handle corresponding to Routing Rule 2 + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.2 + flt_rule_entry.rule.rt_tbl_hdl=routing_table2.hdl; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.ttl_update = 0; // doesn't require ttl update + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(0)->status); + printf("flt rule hdl1=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(1)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(1)->status); + printf("flt rule hdl2=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(2)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(2)->status); + } + + printf("Leaving %s, %s()\n",__FUNCTION__, __FILE__); + return true; + }// AddRules() + + virtual bool ModifyPackets() + { + int address; + + m_sendBuffer[IPV4_TTL_OFFSET] = 0; + m_sendBuffer2[IPV4_TTL_OFFSET] = 0; + m_sendBuffer3[IPV4_TTL_OFFSET] = 0; + return true; + }// ModifyPacktes () + + virtual bool ReceivePacketsAndCompare() + { + size_t receivedSize = 0; + size_t receivedSize2 = 0; + size_t receivedSize3 = 0; + bool pkt1_cmp_succ, pkt2_cmp_succ, pkt3_cmp_succ; + + // Receive results + Byte *rxBuff1 = new Byte[0x400]; + Byte *rxBuff2 = new Byte[0x400]; + Byte *rxBuff3 = new Byte[0x400]; + + if (NULL == rxBuff1 || NULL == rxBuff2 || NULL == rxBuff3) + { + printf("Memory allocation error.\n"); + return false; + } + + memset(rxBuff1, 0, 0x400); + memset(rxBuff2, 0, 0x400); + memset(rxBuff3, 0, 0x400); + + receivedSize = m_Exceptions.ReceiveData(rxBuff1, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize, m_Exceptions.m_fromChannelName.c_str()); + + receivedSize2 = m_Exceptions.ReceiveData(rxBuff2, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize2, m_Exceptions.m_fromChannelName.c_str()); + + receivedSize3 = m_Exceptions.ReceiveData(rxBuff3, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize3, m_Exceptions.m_fromChannelName.c_str()); + + /* Update TTL values. */ + m_sendBuffer[IPV4_TTL_OFFSET] = 0; + m_sendBuffer2[IPV4_TTL_OFFSET] = 0; + m_sendBuffer3[IPV4_TTL_OFFSET] = 0; + + // Compare results + pkt1_cmp_succ = CompareResultVsGolden(m_sendBuffer, m_sendSize, rxBuff1, receivedSize); + pkt2_cmp_succ = CompareResultVsGolden(m_sendBuffer2, m_sendSize2, rxBuff2, receivedSize2); + pkt3_cmp_succ = CompareResultVsGolden(m_sendBuffer3, m_sendSize3, rxBuff3, receivedSize3); + + pkt1_cmp_succ &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_5) ? + IsTTLUpdated_v5_5_wo_status(m_sendSize, receivedSize, rxBuff1) : true; + pkt2_cmp_succ &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_5) ? + IsTTLUpdated_v5_5_wo_status(m_sendSize2, receivedSize2, rxBuff2) : true; + pkt3_cmp_succ &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_5) ? + IsTTLUpdated_v5_5_wo_status(m_sendSize3, receivedSize3, rxBuff3) : true; + + size_t recievedBufferSize = + MAX3(receivedSize, receivedSize2, receivedSize3) * 3; + size_t sentBufferSize = + MAX3(m_sendSize, m_sendSize2, m_sendSize3) * 3; + char *recievedBuffer = new char[recievedBufferSize]; + char *sentBuffer = new char[sentBufferSize]; + size_t j; + + if (NULL == recievedBuffer || NULL == sentBuffer) { + printf("Memory allocation error\n"); + return false; + } + + memset(recievedBuffer, 0, recievedBufferSize); + memset(sentBuffer, 0, sentBufferSize); + for(j = 0; j < m_sendSize; j++) + snprintf(&sentBuffer[3 * j], sentBufferSize - (3 * j + 1), " %02X", m_sendBuffer[j]); + for(j = 0; j < receivedSize; j++) + snprintf(&recievedBuffer[3 * j], recievedBufferSize - (3 * j + 1), " %02X", rxBuff1[j]); + printf("Expected Value1 (%zu)\n%s\n, Received Value1(%zu)\n%s\n-->Value1 %s\n", + m_sendSize,sentBuffer,receivedSize,recievedBuffer, + pkt1_cmp_succ?"Match":"no Match"); + + memset(recievedBuffer, 0, recievedBufferSize); + memset(sentBuffer, 0, sentBufferSize); + for(j = 0; j < m_sendSize2; j++) + snprintf(&sentBuffer[3 * j], sentBufferSize - (3 * j + 1), " %02X", m_sendBuffer2[j]); + for(j = 0; j < receivedSize2; j++) + snprintf(&recievedBuffer[3 * j], recievedBufferSize - (3 * j + 1), " %02X", rxBuff2[j]); + printf("Expected Value2 (%zu)\n%s\n, Received Value2(%zu)\n%s\n-->Value2 %s\n", + m_sendSize2,sentBuffer,receivedSize2,recievedBuffer, + pkt2_cmp_succ?"Match":"no Match"); + + memset(recievedBuffer, 0, recievedBufferSize); + memset(sentBuffer, 0, sentBufferSize); + for(j = 0; j < m_sendSize3; j++) + snprintf(&sentBuffer[3 * j], sentBufferSize - (3 * j + 1), " %02X", m_sendBuffer3[j]); + for(j = 0; j < receivedSize3; j++) + snprintf(&recievedBuffer[3 * j], recievedBufferSize - (3 * j + 1), " %02X", rxBuff3[j]); + printf("Expected Value3 (%zu)\n%s\n, Received Value3(%zu)\n%s\n-->Value3 %s\n", + m_sendSize3,sentBuffer,receivedSize3,recievedBuffer, + pkt3_cmp_succ?"Match":"no Match"); + + delete[] recievedBuffer; + delete[] sentBuffer; + + delete[] rxBuff1; + delete[] rxBuff2; + delete[] rxBuff3; + + return pkt1_cmp_succ && pkt2_cmp_succ && pkt3_cmp_succ; + } + + virtual bool Teardown() + { + return true; + } // Teardown() +}; + +/*---------------------------------------------------------------------------*/ +/* Test117: IPv6 TTL exception test */ +/*---------------------------------------------------------------------------*/ +class IpaFilteringBlockTest117 : public IpaFilteringBlockTestFixture +{ +public: + IpaFilteringBlockTest117() + { + m_name = "IpaFilteringBlockTest117"; + m_description = " \ + Filtering block test 117 - IPv6 with TTL exception and TTL=0 \ + 1. Add filtering rule with TTL decrement marked as 1 \ + 2. Send packet with TTL=0 \ + 3. Verify packet arrival on the exception pipe \ + 4. Verify that the packet was not modified \ + 5. Verify packet status for the TTL exception"; + m_minIPAHwType = IPA_HW_v5_5; + Register(*this); + } + + + bool Setup() + { + /* we want statuses on this test */ + return IpaFilteringBlockTestFixture::Setup(true); + } + + virtual bool AddRules() + { + printf("Entering %s, %s()\n",__FUNCTION__, __FILE__); + + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + struct ipa_ioc_get_rt_tbl routing_table0,routing_table1,routing_table2; + + if (!CreateThreeIPv6BypassRoutingTables (bypass0,bypass1,bypass2)) + { + printf("CreateThreeIPv6BypassRoutingTables Failed\n"); + return false; + } + + printf("CreateThreeIPv6BypassRoutingTables completed successfully\n"); + routing_table0.ip = IPA_IP_v6; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + printf("m_routing.GetRoutingTable(&routing_table0=0x%p) Failed.\n",&routing_table0); + return false; + } + printf("%s route table handle = %u\n", bypass0, routing_table0.hdl); + + routing_table1.ip = IPA_IP_v6; + strlcpy(routing_table1.name, bypass1, sizeof(routing_table1.name)); + if (!m_routing.GetRoutingTable(&routing_table1)) + { + printf("m_routing.GetRoutingTable(&routing_table1=0x%p) Failed.\n",&routing_table1); + return false; + } + printf("%s route table handle = %u\n", bypass1, routing_table1.hdl); + + routing_table2.ip = IPA_IP_v6; + strlcpy(routing_table2.name, bypass2, sizeof(routing_table2.name)); + if (!m_routing.GetRoutingTable(&routing_table2)) + { + printf("m_routing.GetRoutingTable(&routing_table2=0x%p) Failed.\n",&routing_table2); + return false; + } + printf("%s route table handle = %u\n", bypass2, routing_table2.hdl); + + IPAFilteringTable_v2 FilterTable0; + struct ipa_flt_rule_add_v2 flt_rule_entry; + FilterTable0.Init(IPA_IP_v6,IPA_CLIENT_TEST_PROD,false,3); + printf("FilterTable*.Init Completed Successfully..\n"); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1,flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl=-1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action=IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.rt_tbl_hdl=routing_table0.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + flt_rule_entry.rule.ttl_update = 1; // require ttl update + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } + + // Configuring Filtering Rule No.1 + flt_rule_entry.rule.rt_tbl_hdl=routing_table1.hdl; //put here the handle corresponding to Routing Rule 2 + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } + + flt_rule_entry.rule.ttl_update = 0; // doesn't require ttl update + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + printf ("%s::Error Adding Rule to Filter Table, aborting...\n",__FUNCTION__); + return false; + } else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(0)->status); + printf("flt rule hdl1=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(1)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(1)->status); + printf("flt rule hdl2=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(2)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(2)->status); + } + + printf("Leaving %s, %s()\n",__FUNCTION__, __FILE__); + return true; + }// AddRules() + + virtual bool ModifyPackets() + { + int address; + m_sendBuffer[HOP_LIMIT_OFFSET_IPV6] = 0; + m_sendBuffer2[HOP_LIMIT_OFFSET_IPV6] = 0; + m_sendBuffer3[HOP_LIMIT_OFFSET_IPV6] = 0; + return true; + }// ModifyPacktes () + + virtual bool ReceivePacketsAndCompare() + { + size_t receivedSize = 0; + size_t receivedSize2 = 0; + size_t receivedSize3 = 0; + bool pkt1_cmp_succ, pkt2_cmp_succ, pkt3_cmp_succ; + + // Receive results + Byte *rxBuff1 = new Byte[0x400]; + Byte *rxBuff2 = new Byte[0x400]; + Byte *rxBuff3 = new Byte[0x400]; + + if (NULL == rxBuff1 || NULL == rxBuff2 || NULL == rxBuff3) + { + printf("Memory allocation error.\n"); + return false; + } + + memset(rxBuff1, 0, 0x400); + memset(rxBuff2, 0, 0x400); + memset(rxBuff3, 0, 0x400); + + receivedSize = m_Exceptions.ReceiveData(rxBuff1, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize, m_Exceptions.m_fromChannelName.c_str()); + + receivedSize2 = m_Exceptions.ReceiveData(rxBuff2, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize2, m_Exceptions.m_fromChannelName.c_str()); + + receivedSize3 = m_Exceptions.ReceiveData(rxBuff3, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize3, m_Exceptions.m_fromChannelName.c_str()); + + /* Update TTL values. */ + m_sendBuffer[HOP_LIMIT_OFFSET_IPV6] = 0; + m_sendBuffer2[HOP_LIMIT_OFFSET_IPV6] = 0; + m_sendBuffer3[HOP_LIMIT_OFFSET_IPV6] = 0; + + pkt1_cmp_succ = CompareResultVsGolden(m_sendBuffer, m_sendSize, rxBuff1, receivedSize); + pkt2_cmp_succ = CompareResultVsGolden(m_sendBuffer2, m_sendSize2, rxBuff2, receivedSize2); + pkt3_cmp_succ = CompareResultVsGolden(m_sendBuffer3, m_sendSize3, rxBuff3, receivedSize3); + + pkt1_cmp_succ &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_5) ? + IsTTLUpdated_v5_5_wo_status(m_sendSize, receivedSize, rxBuff1) : true; + pkt2_cmp_succ &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_5) ? + IsTTLUpdated_v5_5_wo_status(m_sendSize2, receivedSize2, rxBuff2) : true; + pkt3_cmp_succ &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_5) ? + IsTTLUpdated_v5_5_wo_status(m_sendSize3, receivedSize3, rxBuff3) : true; + + size_t recievedBufferSize = + MAX3(receivedSize, receivedSize2, receivedSize3) * 3; + size_t sentBufferSize = + MAX3(m_sendSize, m_sendSize2, m_sendSize3) * 3; + char *recievedBuffer = new char[recievedBufferSize]; + char *sentBuffer = new char[sentBufferSize]; + size_t j; + + if (NULL == recievedBuffer || NULL == sentBuffer) { + printf("Memory allocation error\n"); + return false; + } + + memset(recievedBuffer, 0, recievedBufferSize); + memset(sentBuffer, 0, sentBufferSize); + for(j = 0; j < m_sendSize; j++) + snprintf(&sentBuffer[3 * j], sentBufferSize - (3 * j + 1), " %02X", m_sendBuffer[j]); + for(j = 0; j < receivedSize; j++) + snprintf(&recievedBuffer[3 * j], recievedBufferSize - (3 * j + 1), " %02X", rxBuff1[j]); + printf("Expected Value1 (%zu)\n%s\n, Received Value1(%zu)\n%s\n-->Value1 %s\n", + m_sendSize,sentBuffer,receivedSize,recievedBuffer, + pkt1_cmp_succ?"Match":"no Match"); + + memset(recievedBuffer, 0, recievedBufferSize); + memset(sentBuffer, 0, sentBufferSize); + for(j = 0; j < m_sendSize2; j++) + snprintf(&sentBuffer[3 * j], sentBufferSize - (3 * j + 1), " %02X", m_sendBuffer2[j]); + for(j = 0; j < receivedSize2; j++) + snprintf(&recievedBuffer[3 * j], recievedBufferSize - (3 * j + 1), " %02X", rxBuff2[j]); + printf("Expected Value2 (%zu)\n%s\n, Received Value2(%zu)\n%s\n-->Value2 %s\n", + m_sendSize2,sentBuffer,receivedSize2,recievedBuffer, + pkt2_cmp_succ?"Match":"no Match"); + + memset(recievedBuffer, 0, recievedBufferSize); + memset(sentBuffer, 0, sentBufferSize); + for(j = 0; j < m_sendSize3; j++) + snprintf(&sentBuffer[3 * j], sentBufferSize - (3 * j + 1), " %02X", m_sendBuffer3[j]); + for(j = 0; j < receivedSize3; j++) + snprintf(&recievedBuffer[3 * j], recievedBufferSize - (3 * j + 1), " %02X", rxBuff3[j]); + printf("Expected Value3 (%zu)\n%s\n, Received Value3(%zu)\n%s\n-->Value3 %s\n", + m_sendSize3,sentBuffer,receivedSize3,recievedBuffer, + pkt3_cmp_succ?"Match":"no Match"); + + delete[] recievedBuffer; + delete[] sentBuffer; + + delete[] rxBuff1; + delete[] rxBuff2; + delete[] rxBuff3; + + return pkt1_cmp_succ && pkt2_cmp_succ && pkt3_cmp_succ; + } + + virtual bool Teardown() + { + return true; + } // Teardown() +}; + + +static class IpaFilteringBlockTest001 ipaFilteringBlockTest001;//Global Filtering Test +static class IpaFilteringBlockTest002 ipaFilteringBlockTest002;//Global Filtering Test +static class IpaFilteringBlockTest003 ipaFilteringBlockTest003;//Global Filtering Test +static class IpaFilteringBlockTest004 ipaFilteringBlockTest004;//Global Filtering Test +static class IpaFilteringBlockTest005 ipaFilteringBlockTest005;//Global Filtering Test +static class IpaFilteringBlockTest006 ipaFilteringBlockTest006;//Global Filtering Test +static class IpaFilteringBlockTest007 ipaFilteringBlockTest007;//Global Filtering Test +static class IpaFilteringBlockTest008 ipaFilteringBlockTest008;//Global Filtering Test +static class IpaFilteringBlockTest009 ipaFilteringBlockTest009;//Global Filtering Test +static class IpaFilteringBlockTest010 ipaFilteringBlockTest010;//Global Filtering Test + +static class IpaFilteringBlockTest021 ipaFilteringBlockTest021;//End point Specific Filtering Table +static class IpaFilteringBlockTest022 ipaFilteringBlockTest022;//End point Specific Filtering Table +static class IpaFilteringBlockTest023 ipaFilteringBlockTest023;//End point Specific Filtering Table +static class IpaFilteringBlockTest024 ipaFilteringBlockTest024;//End point Specific Filtering Table +static class IpaFilteringBlockTest025 ipaFilteringBlockTest025;//End point Specific Filtering Table +static class IpaFilteringBlockTest026 ipaFilteringBlockTest026;//End point Specific Filtering Table +static class IpaFilteringBlockTest027 ipaFilteringBlockTest027;//End point Specific Filtering Table +static class IpaFilteringBlockTest028 ipaFilteringBlockTest028;//End point Specific Filtering Table +static class IpaFilteringBlockTest029 ipaFilteringBlockTest029;//End point Specific Filtering Table +static class IpaFilteringBlockTest030 ipaFilteringBlockTest030;//End point Specific Filtering Table +static class IpaFilteringBlockTest031 ipaFilteringBlockTest031;//End point Specific Filtering Table + +static class IpaFilteringBlockTest050 ipaFilteringBlockTest050;// IPv6 Test, Global Filtering Table +static class IpaFilteringBlockTest051 ipaFilteringBlockTest051;// IPv6 Test, End point Specific Filtering Table +static class IpaFilteringBlockTest052 ipaFilteringBlockTest052;// IPv6 Test, Global Filtering Table +static class IpaFilteringBlockTest053 ipaFilteringBlockTest053;// IPv6 Test, End point Specific Filtering Table +static class IpaFilteringBlockTest054 ipaFilteringBlockTest054;// IPv6 Test, End point Specific Filtering Table + +static class IpaFilteringBlockTest060 ipaFilteringBlockTest060; // Hashed non hashed tests IPv4 +static class IpaFilteringBlockTest061 ipaFilteringBlockTest061; // Hashed non hashed tests IPv4 +static class IpaFilteringBlockTest062 ipaFilteringBlockTest062; // Hashed non hashed tests IPv4 +static class IpaFilteringBlockTest063 ipaFilteringBlockTest063; // Hashed non hashed tests IPv4 +static class IpaFilteringBlockTest064 ipaFilteringBlockTest064; // Hashed non hashed tests IPv4 +static class IpaFilteringBlockTest065 ipaFilteringBlockTest065; // Hashed non hashed tests IPv4 +static class IpaFilteringBlockTest066 ipaFilteringBlockTest066; // Hashed non hashed tests IPv4 +static class IpaFilteringBlockTest067 ipaFilteringBlockTest067; // Cache/Hash invalidation on add test +static class IpaFilteringBlockTest068 ipaFilteringBlockTest068; // Cache/Hash invalidation on delete test + +static class IpaFilteringBlockTest070 ipaFilteringBlockTest070; // Hashed non hashed tests IPV6 +static class IpaFilteringBlockTest071 ipaFilteringBlockTest071; // Hashed non hashed tests IPV6 +static class IpaFilteringBlockTest072 ipaFilteringBlockTest072; // Hashed non hashed tests IPV6 +static class IpaFilteringBlockTest073 ipaFilteringBlockTest073; // Hashed non hashed tests IPV6 +static class IpaFilteringBlockTest074 ipaFilteringBlockTest074; // Hashed non hashed tests IPV6 +static class IpaFilteringBlockTest075 ipaFilteringBlockTest075; // Hashed non hashed tests IPV6 +static class IpaFilteringBlockTest076 ipaFilteringBlockTest076; // Hashed non hashed tests IPV6 +static class IpaFilteringBlockTest077 ipaFilteringBlockTest077; // Cache/Hash invalidation on add test +static class IpaFilteringBlockTest078 ipaFilteringBlockTest078; // Cache/Hash invalidation on delete test + +static class IpaFilteringBlockTest081 ipaFilteringBlockTest081; // Type-of-service Filter rule test +static class IpaFilteringBlockTest082 ipaFilteringBlockTest082; // IPv4 Pure Ack Filter rule test + +static class IpaFilteringBlockTest090 ipaFilteringBlockTest090; // VLAN filtering test IPv4 + +static class IpaFilteringBlockTest100 ipaFilteringBlockTest100; // Cache LRU behavior test + +static class IpaFilteringBlockTest101 ipaFilteringBlockTest101; // Non hashed table SRAM <->DDR dynamic move +static class IpaFilteringBlockTest102 ipaFilteringBlockTest102; // Non hashed table SRAM <->DDR dynamic move + +static class IpaFilteringBlockTest110 ipaFilteringBlockTest110; // Ipv4 TTL Update. +static class IpaFilteringBlockTest111 ipaFilteringBlockTest111; // Ipv6 TTL Update. +static class IpaFilteringBlockTest112 ipaFilteringBlockTest112; // Ipv4 TTL Update with status. +static class IpaFilteringBlockTest113 ipaFilteringBlockTest113; // Ipv6 TTL Update with status. +static class IpaFilteringBlockTest114 ipaFilteringBlockTest114; // IPv4 TTL exception test, TTL=1 +static class IpaFilteringBlockTest115 ipaFilteringBlockTest115; // IPv6 TTL exception test, TTL=1 +static class IpaFilteringBlockTest116 ipaFilteringBlockTest116; // IPv4 TTL exception test, TTL=0 +static class IpaFilteringBlockTest117 ipaFilteringBlockTest117; // IPv6 TTL exception test, TTL=0 diff --git a/qcom/opensource/dataipa/kernel-tests/HeaderInsertion.cpp b/qcom/opensource/dataipa/kernel-tests/HeaderInsertion.cpp new file mode 100644 index 0000000000..68e8434e2e --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/HeaderInsertion.cpp @@ -0,0 +1,273 @@ +/* + * Copyright (c) 2017 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Changes from Qualcomm Innovation Center are provided under the following license: + * + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * * Neither the name of Qualcomm Innovation Center, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + */ + +#include +#include +#include +#include +#include +#include + +#include "HeaderInsertion.h" +#include "TestsUtils.h" + +#define LOG_IOCTL_RETURN_VALUE(nRetVal) \ + printf("%s()- %s\n", __func__, \ + (-1 == nRetVal) ? "Fail" : "Success"); + +bool HeaderInsertion::AddHeader(struct ipa_ioc_add_hdr *pHeaderTableToAdd) +{ + int nRetVal = 0; + /*call the Driver ioctl in order to add header*/ + nRetVal = ioctl(m_fd, IPA_IOC_ADD_HDR, pHeaderTableToAdd); + LOG_IOCTL_RETURN_VALUE(nRetVal); + return (-1 != nRetVal); +} + +bool HeaderInsertion::addHeaderHpc(const string& name, uint8_t* header, const size_t headerLen, bool isPartial, enum ipa_client_type ipaClient){ + if(name.empty() || name.size() >= IPA_RESOURCE_NAME_MAX){ + return false; + } + int fd = open(CONFIGURATION_NODE_PATH, O_RDONLY); + if (fd < 0) { + cout << "failed to open " << CONFIGURATION_NODE_PATH << endl; + return false; + } + struct ipa_ioc_add_hdr *iocH = static_cast(calloc(1, sizeof(*iocH) + sizeof(struct ipa_hdr_add))); + if(!iocH){ + return false; + } + iocH->commit = 1; + iocH->num_hdrs = 1; + struct ipa_hdr_add *h = &iocH->hdr[0]; + strlcpy(h->name, name.c_str(), IPA_RESOURCE_NAME_MAX); + memcpy(h->hdr, header, headerLen); + h->hdr_len = headerLen; + h->hdr_hdl = -1; + h->status = -1; + h->is_partial = isPartial; + cout << "h->name=" << h->name << ", h->is_partial=" << h->is_partial << endl; + int result = ioctl(fd, IPA_TEST_IOC_ADD_HDR_HPC, iocH); + if(result || h->status){ + free(iocH); + close(fd); + return false; + } + cout << "result=" << result << ", status=" << h->status << ", ipaClient=" << ipaClient << endl; + struct ipa_pkt_init_ex_hdr_ofst_set lookup; + lookup.ep = ipaClient; + strlcpy(lookup.name, name.c_str(), IPA_RESOURCE_NAME_MAX); + result = ioctl(fd, IPA_TEST_IOC_PKT_INIT_EX_SET_HDR_OFST , &lookup); + if (result) { + free(iocH); + close(fd); + return false; + } + free(iocH); + close(fd); + return true; +} + +bool HeaderInsertion::DeleteHeader(struct ipa_ioc_del_hdr *pHeaderTableToDelete) +{ + int nRetVal = 0; + /*call the Driver ioctl in order to remove header*/ + nRetVal = ioctl(m_fd, IPA_IOC_DEL_HDR , pHeaderTableToDelete); + LOG_IOCTL_RETURN_VALUE(nRetVal); + return (-1 != nRetVal); +} + +bool HeaderInsertion::DeleteHeader(const string& name){ + if(name.empty() || name.size() >= IPA_RESOURCE_NAME_MAX){ + return false; + } + int hdl = GetHeaderHandle(name); + if(hdl == -1){ + return false; + } + struct ipa_ioc_del_hdr *iocD = static_cast(calloc(1, sizeof(*iocD) + sizeof(struct ipa_hdr_del))); + if(!iocD){ + return false; + } + iocD->commit = 1; + iocD->num_hdls = 1; + struct ipa_hdr_del *h = &iocD->hdl[0]; + h->hdl = hdl; + h->status = -1; + cout << "h->hdl=" << h->hdl << endl; + if(!DeleteHeader(iocD)){ + free(iocD); + return false; + } + free(iocD); + return true; +} + +bool HeaderInsertion::AddProcCtx(struct ipa_ioc_add_hdr_proc_ctx *procCtxTable) +{ + int retval = 0; + + retval = ioctl(m_fd, IPA_IOC_ADD_HDR_PROC_CTX, procCtxTable); + if (retval) { + printf("%s(), failed adding ProcCtx rule table %p\n", __FUNCTION__, procCtxTable); + return false; + } + + printf("%s(), Added ProcCtx rule to table %p\n", __FUNCTION__, procCtxTable); + return true; +} + +bool HeaderInsertion::DeleteProcCtx(struct ipa_ioc_del_hdr_proc_ctx *procCtxTable) +{ + int retval = 0; + + retval = ioctl(m_fd, IPA_IOC_DEL_HDR_PROC_CTX, procCtxTable); + if (retval) { + printf("%s(), failed deleting ProcCtx rule in table %p\n", __FUNCTION__, procCtxTable); + return false; + } + + printf("%s(), Deleted ProcCtx rule in table %p\n", __FUNCTION__, procCtxTable); + return true; +} + +bool HeaderInsertion::Commit() +{ + int nRetVal = 0; + nRetVal = ioctl(m_fd, IPA_IOC_COMMIT_HDR); + LOG_IOCTL_RETURN_VALUE(nRetVal); + return true; +} + +bool HeaderInsertion::Reset() +{ + int nRetVal = 0; + + nRetVal = ioctl(m_fd, IPA_IOC_RESET_HDR); + nRetVal |= ioctl(m_fd, IPA_IOC_COMMIT_HDR); + LOG_IOCTL_RETURN_VALUE(nRetVal); + return true; +} + +bool HeaderInsertion::GetHeaderHandle(struct ipa_ioc_get_hdr *pHeaderStruct) +{ + int retval = 0; + + if (!DeviceNodeIsOpened()) + return false; + + retval = ioctl(m_fd, IPA_IOC_GET_HDR, pHeaderStruct); + if (retval) { + printf( + "%s(), IPA_IOC_GET_HDR ioctl failed, routingTable =0x%p, retval=0x%x.\n" + , __func__, + pHeaderStruct, + retval); + return false; + } + + printf( + "%s(), IPA_IOC_GET_HDR ioctl issued to IPA header insertion block.\n", + __func__); + return true; +} + +int HeaderInsertion::GetHeaderHandle(const string& name){ + if(name.empty() || name.size() >= IPA_RESOURCE_NAME_MAX){ + return false; + } + struct ipa_ioc_get_hdr retHeader; + memset(&retHeader, 0, sizeof(retHeader)); + strlcpy(retHeader.name, name.c_str(), IPA_RESOURCE_NAME_MAX); + retHeader.hdl = -1; + printf("retHeader.name=%s\n", retHeader.name); + if(!GetHeaderHandle(&retHeader)){ + cout << "GetHeaderHandle(&retHeader) Failed" << endl; + return -1; + } + cout << "retHeader.hdl=" << retHeader.hdl << endl; + return retHeader.hdl; +} + +bool HeaderInsertion::CopyHeader(struct ipa_ioc_copy_hdr *pCopyHeaderStruct) +{ + int retval = 0; + + if (!DeviceNodeIsOpened()) + return false; + + retval = ioctl(m_fd, IPA_IOC_COPY_HDR, pCopyHeaderStruct); + if (retval) { + printf( + "%s(), IPA_IOC_COPY_HDR ioctl failed, retval=0x%x.\n", + __func__, + retval); + return false; + } + + printf( + "%s(), IPA_IOC_COPY_HDR ioctl issued to IPA header insertion block.\n", + __func__); + return true; +} + diff --git a/qcom/opensource/dataipa/kernel-tests/HeaderInsertion.h b/qcom/opensource/dataipa/kernel-tests/HeaderInsertion.h new file mode 100644 index 0000000000..90789432d9 --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/HeaderInsertion.h @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2017 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Changes from Qualcomm Innovation Center are provided under the following license: + * + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * * Neither the name of Qualcomm Innovation Center, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + */ + +#ifndef HEADER_INSERTION_H_ +#define HEADER_INSERTION_H_ + +#include +#include +#include +#include "linux/msm_ipa.h" +#include "ipa_test_module.h" +#include "Constants.h" +#include "Feature.h" + +using std::string; +using std::cout; +using std::endl; + +class HeaderInsertion: public Feature +{ +public: + bool AddHeader(struct ipa_ioc_add_hdr *pHeaderTable); + bool addHeaderHpc(const string& name, uint8_t* header, const size_t headerLen, bool isPartial, enum ipa_client_type ipaClient); + bool DeleteHeader(struct ipa_ioc_del_hdr *pHeaderTable); + bool DeleteHeader(const string& name); + bool GetHeaderHandle(struct ipa_ioc_get_hdr *pHeaderStruct); + int GetHeaderHandle(const string& name); + bool CopyHeader(struct ipa_ioc_copy_hdr *pCopyHeaderStruct); + + // Processing context + bool AddProcCtx(struct ipa_ioc_add_hdr_proc_ctx *procCtxTable); + bool DeleteProcCtx(struct ipa_ioc_del_hdr_proc_ctx *procCtxTable); + + bool Commit(); + bool Reset(); +}; + +#endif diff --git a/qcom/opensource/dataipa/kernel-tests/HeaderInsertionTests.cpp b/qcom/opensource/dataipa/kernel-tests/HeaderInsertionTests.cpp new file mode 100644 index 0000000000..35bb4f4458 --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/HeaderInsertionTests.cpp @@ -0,0 +1,1463 @@ +/* + * Copyright (c) 2017-2018,2021 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Changes from Qualcomm Innovation Center are provided under the following license: + * + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * * Neither the name of Qualcomm Innovation Center, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + */ + +#include "RoutingDriverWrapper.h" +#include "HeaderInsertion.h" +#include "Filtering.h" +#include "IPAFilteringTable.h" +#include "hton.h" // for htonl +#include "TestsUtils.h" +#include +#include +#include +#include +#include +#include + +#define IPV4_DST_ADDR_OFFSET (16) + +class IPAHeaderInsertionTestFixture: public TestBase { +public: + + IPAHeaderInsertionTestFixture() : m_uBufferSize(0) + { + memset(m_aBuffer, 0, sizeof(m_aBuffer)); + m_testSuiteName.push_back("Insertion"); + } + + virtual bool AddRules() = 0; + virtual bool ModifyPackets() = 0; + virtual bool TestLogic() = 0; + + bool Setup() + { + + ConfigureScenario(PHASE_FIVE_TEST_CONFIGURATION); + + m_producer.Open(INTERFACE0_TO_IPA_DATA_PATH, + INTERFACE0_FROM_IPA_DATA_PATH); + m_Consumer1.Open(INTERFACE1_TO_IPA_DATA_PATH, + INTERFACE1_FROM_IPA_DATA_PATH); + m_Consumer2.Open(INTERFACE2_TO_IPA_DATA_PATH, + INTERFACE2_FROM_IPA_DATA_PATH); + m_Consumer3.Open(INTERFACE3_TO_IPA_DATA_PATH, + INTERFACE3_FROM_IPA_DATA_PATH); + + if (!m_Routing.DeviceNodeIsOpened()) { + LOG_MSG_ERROR( + "Routing block is not ready for immediate commands!\n"); + return false; + } + if (!m_Filtering.DeviceNodeIsOpened()) { + LOG_MSG_ERROR( + "Filtering block is not ready for immediate commands!\n"); + return false; + } + if (!m_HeaderInsertion.DeviceNodeIsOpened()) + { + LOG_MSG_ERROR("Header Insertion block is not ready for immediate commands!\n"); + return false; + } + m_HeaderInsertion.Reset();// resetting this component will reset both Routing and Filtering tables. + + return true; + } // Setup() + + bool Run() + { + m_uBufferSize = BUFF_MAX_SIZE; + LOG_MSG_STACK("Entering Function"); + + // Add the relevant filtering rules + if (!AddRules()) { + LOG_MSG_ERROR("Failed adding filtering rules."); + return false; + } + // Load input data (IP packet) from file + if (!LoadDefaultPacket(m_eIP, m_aBuffer, m_uBufferSize)) { + LOG_MSG_ERROR("Failed default Packet"); + return false; + } + if (!ModifyPackets()) { + LOG_MSG_ERROR("Failed to modify packets."); + return false; + } + if (!TestLogic()) { + LOG_MSG_ERROR("Test failed, Input and expected output mismatch."); + return false; + } + + LOG_MSG_STACK("Leaving Function (Returning True)"); + return true; + } // Run() + + bool Teardown() + { + m_HeaderInsertion.Reset();// resetting this component will reset both Routing and Filtering tables. + m_producer.Close(); + m_Consumer1.Close(); + m_Consumer2.Close(); + m_Consumer3.Close(); + return true; + } // Teardown() + + unsigned GetHdrSramSize() + { + int fd; + struct ipa_test_mem_partition mem_part; + + fd = open("/dev/ipa_test", O_RDONLY); + if (fd < 0) { + printf("Failed opening %s. errno %d: %s\n", "/dev/ipa_test", + errno, strerror(errno)); + return 0; + } + + if (ioctl(fd, IPA_TEST_IOC_GET_MEM_PART, &mem_part) < 0) { + printf("Failed ioctl IPA_TEST_IOC_GET_MEM_PART. errno %d: %s\n", + errno, strerror(errno)); + close(fd); + return 0; + } + + close(fd); + + return mem_part.apps_hdr_size; + } + + ~IPAHeaderInsertionTestFixture() {} + + static RoutingDriverWrapper m_Routing; + static Filtering m_Filtering; + static HeaderInsertion m_HeaderInsertion; + InterfaceAbstraction m_producer; + InterfaceAbstraction m_Consumer1; + InterfaceAbstraction m_Consumer2; + InterfaceAbstraction m_Consumer3; + +protected: + static const size_t BUFF_MAX_SIZE = 1024; + static const uint8_t MAX_HEADER_SIZE = 64; // 64Bytes - Max Header Length + enum ipa_ip_type m_eIP; + uint8_t m_aBuffer[BUFF_MAX_SIZE]; // Input file \ IP packet + size_t m_uBufferSize; + +}; +RoutingDriverWrapper IPAHeaderInsertionTestFixture::m_Routing; +Filtering IPAHeaderInsertionTestFixture::m_Filtering; +HeaderInsertion IPAHeaderInsertionTestFixture::m_HeaderInsertion; + +//---------------------------------------------------------------------------/ +// Test002: Test that 802.3 header was inserted Correctly / +//---------------------------------------------------------------------------/ +class IPAHeaderInsertionTest001: public IPAHeaderInsertionTestFixture { +public: + IPAHeaderInsertionTest001() { + m_name = "IPAHeaderInsertionTest001"; + m_description = + "Header Insertion Test 001 - Test RMNet Header Insertion\ + 1. Generate and commit RMNet.3 header Insertion \ + 2. Generate and commit routing table containing bypass rule. \ + 3. Generate and commit bypass filtering rule. \ + 4. Send a packet, and verify that the RMNet.3 Header was inserted correctly."; + Register(*this); + uint8_t aRMNetHeader[6] = { 0x01, 0x02, 0x03, 0x04, 0x05, 0x06}; + m_nHeadertoAddSize = sizeof(aRMNetHeader); + memcpy(m_aHeadertoAdd, aRMNetHeader, m_nHeadertoAddSize); + } + + // Test Description: + // 1. Generate and commit single bypass routing table. + virtual bool AddRules() { + m_eIP = IPA_IP_v4; + const char bypass0[20] = "Bypass0"; + struct ipa_ioc_get_rt_tbl sRoutingTable; + bool bRetVal = true; + struct ipa_ioc_get_hdr sRetHeader; + IPAFilteringTable cFilterTable; + struct ipa_flt_rule_add sFilterRuleEntry; + uint32_t nRTTableHdl=0; + memset(&sRoutingTable, 0, sizeof(sRoutingTable)); + memset(&sRetHeader, 0, sizeof(sRetHeader)); + strlcpy(sRetHeader.name, "IEEE802_3", sizeof(sRetHeader.name)); + + LOG_MSG_STACK("Entering Function"); + // Create Header: + // Allocate Memory, populate it, and add in to the Header Insertion. + struct ipa_ioc_add_hdr * pHeaderDescriptor = NULL; + pHeaderDescriptor = (struct ipa_ioc_add_hdr *) calloc(1, + sizeof(struct ipa_ioc_add_hdr) + + 1 * sizeof(struct ipa_hdr_add)); + if (!pHeaderDescriptor) { + LOG_MSG_ERROR("calloc failed to allocate pHeaderDescriptor"); + bRetVal = false; + goto bail; + } + pHeaderDescriptor->commit = true; + pHeaderDescriptor->num_hdrs = 1; + strlcpy(pHeaderDescriptor->hdr[0].name, sRetHeader.name, sizeof(pHeaderDescriptor->hdr[0].name)); + memcpy(pHeaderDescriptor->hdr[0].hdr, m_aHeadertoAdd, + m_nHeadertoAddSize); //Header's Data + pHeaderDescriptor->hdr[0].hdr_len = m_nHeadertoAddSize; + pHeaderDescriptor->hdr[0].hdr_hdl = -1; //Return Value + pHeaderDescriptor->hdr[0].is_partial = false; + pHeaderDescriptor->hdr[0].status = -1; // Return Parameter + strlcpy(sRetHeader.name, pHeaderDescriptor->hdr[0].name, sizeof(sRetHeader.name)); + + if (!m_HeaderInsertion.AddHeader(pHeaderDescriptor)) + { + LOG_MSG_ERROR("m_HeaderInsertion.AddHeader(pHeaderDescriptor) Failed."); + bRetVal = false; + goto bail; + } + if (!m_HeaderInsertion.GetHeaderHandle(&sRetHeader)) + { + LOG_MSG_ERROR(" Failed"); + bRetVal = false; + goto bail; + } + if (!CreateBypassRoutingTable(&m_Routing, m_eIP, bypass0, IPA_CLIENT_TEST2_CONS, + sRetHeader.hdl,&nRTTableHdl)) { + LOG_MSG_ERROR("CreateBypassRoutingTable Failed\n"); + bRetVal = false; + goto bail; + } + LOG_MSG_INFO("CreateBypassRoutingTable completed successfully"); + sRoutingTable.ip = m_eIP; + strlcpy(sRoutingTable.name, bypass0, sizeof(sRoutingTable.name)); + if (!m_Routing.GetRoutingTable(&sRoutingTable)) { + LOG_MSG_ERROR( + "m_routing.GetRoutingTable(&sRoutingTable=0x%p) Failed.", &sRoutingTable); + bRetVal = false; + goto bail; + } + // Creating Filtering Rules + cFilterTable.Init(m_eIP,IPA_CLIENT_TEST_PROD,false,1); + LOG_MSG_INFO("Creation of filtering table completed successfully"); + + // Configuring Filtering Rule No.1 + cFilterTable.GeneratePresetRule(0,sFilterRuleEntry); + sFilterRuleEntry.at_rear = true; + sFilterRuleEntry.flt_rule_hdl = -1; // return Value + sFilterRuleEntry.status = -1; // return value + sFilterRuleEntry.rule.action = IPA_PASS_TO_ROUTING; + sFilterRuleEntry.rule.rt_tbl_hdl = nRTTableHdl; //put here the handle corresponding to Routing Rule 1 + if ( + ((uint8_t)-1 == cFilterTable.AddRuleToTable(sFilterRuleEntry)) || + !m_Filtering.AddFilteringRule(cFilterTable.GetFilteringTable()) + ) + { + LOG_MSG_ERROR ("Adding Rule (0) to Filtering block Failed."); + bRetVal = false; + goto bail; + } else + { + LOG_MSG_DEBUG("flt rule hdl0=0x%x, status=0x%x\n", cFilterTable.ReadRuleFromTable(0)->flt_rule_hdl,cFilterTable.ReadRuleFromTable(0)->status); + } + + bail: + Free(pHeaderDescriptor); + LOG_MSG_STACK( + "Leaving Function (Returning %s)", bRetVal?"True":"False"); + return bRetVal; + } // AddRules() + + virtual bool ModifyPackets() { + // This test doesn't modify the original IP Packet. + return true; + } // ModifyPacktes () + + virtual bool TestLogic() { + memset(m_aExpectedBuffer, 0, sizeof(m_aExpectedBuffer)); + m_aExpectedBufSize = 0; + + memcpy(m_aExpectedBuffer, m_aHeadertoAdd, m_nHeadertoAddSize); + memcpy(m_aExpectedBuffer+m_nHeadertoAddSize,m_aBuffer,m_uBufferSize); + m_aExpectedBufSize = m_nHeadertoAddSize + m_uBufferSize; + if (!SendReceiveAndCompare(&m_producer, m_aBuffer, m_uBufferSize, + &m_Consumer1, m_aExpectedBuffer, m_aExpectedBufSize)) { + LOG_MSG_ERROR("SendReceiveAndCompare failed."); + return false; + } + return true; + } +private: + uint8_t m_aExpectedBuffer[BUFF_MAX_SIZE]; // Input file / IP packet + size_t m_aExpectedBufSize; + uint8_t m_aHeadertoAdd[MAX_HEADER_SIZE]; + size_t m_nHeadertoAddSize; +}; + +//---------------------------------------------------------------------------/ +// Test002: Test that 802.3 header was inserted Correctly / +//---------------------------------------------------------------------------/ +class IPAHeaderInsertionTest002: public IPAHeaderInsertionTestFixture { +public: + IPAHeaderInsertionTest002() { + m_name = "IPAHeaderInsertionTest002"; + m_description = + "Header Insertion Test 002 - Test IEEE802.3 Header Insertion\ + 1. Generate and commit IEEE802.3 header Insertion \ + 2. Generate and commit routing table containing bypass rule. \ + 3. Generate and commit bypass filtering rule. \ + 4. Send a packet, and verify that the IEEE802.3 Header was inserted correctly \ + and that the header Length was updated as well"; + Register(*this); + uint8_t aIEEE802_3Header[22] = { 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, + 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0x00, 0x46, 0xAE, 0xAF, 0xB0,// the correct size (00 46) is inserted here. + 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6 }; + m_nHeadertoAddSize = sizeof(aIEEE802_3Header); + memcpy(m_aHeadertoAdd, aIEEE802_3Header, m_nHeadertoAddSize); + } + + // Test Description: + // 1. Generate and commit single bypass routing table. + virtual bool AddRules() { + m_eIP = IPA_IP_v4; + const char bypass0[20] = "Bypass0"; + struct ipa_ioc_get_rt_tbl sRoutingTable; + bool bRetVal = true; + struct ipa_ioc_get_hdr sRetHeader; + IPAFilteringTable cFilterTable; + struct ipa_flt_rule_add sFilterRuleEntry; + uint32_t nRTTableHdl=0; + memset(&sRoutingTable, 0, sizeof(sRoutingTable)); + memset(&sRetHeader, 0, sizeof(sRetHeader)); + strlcpy(sRetHeader.name, "IEEE802_3", sizeof(sRetHeader.name)); + + LOG_MSG_STACK("Entering Function"); + // Create Header: + // Allocate Memory, populate it, and add in to the Header Insertion. + struct ipa_ioc_add_hdr * pHeaderDescriptor = NULL; + pHeaderDescriptor = (struct ipa_ioc_add_hdr *) calloc(1, + sizeof(struct ipa_ioc_add_hdr) + + 1 * sizeof(struct ipa_hdr_add)); + if (!pHeaderDescriptor) { + LOG_MSG_ERROR("calloc failed to allocate pHeaderDescriptor"); + bRetVal = false; + goto bail; + } + pHeaderDescriptor->commit = true; + pHeaderDescriptor->num_hdrs = 1; + strlcpy(pHeaderDescriptor->hdr[0].name, sRetHeader.name, sizeof(pHeaderDescriptor->hdr[0].name)); // Header's Name + memcpy(pHeaderDescriptor->hdr[0].hdr, m_aHeadertoAdd, + m_nHeadertoAddSize); //Header's Data + pHeaderDescriptor->hdr[0].hdr[12] = 0x00; //set length to zero, to confirm if ipa updates or not + pHeaderDescriptor->hdr[0].hdr_len = m_nHeadertoAddSize; + pHeaderDescriptor->hdr[0].hdr_hdl = -1; //Return Value + pHeaderDescriptor->hdr[0].is_partial = false; + pHeaderDescriptor->hdr[0].status = -1; // Return Parameter + strlcpy(sRetHeader.name, pHeaderDescriptor->hdr[0].name, sizeof(sRetHeader.name)); + + if (!m_HeaderInsertion.AddHeader(pHeaderDescriptor)) + { + LOG_MSG_ERROR("m_HeaderInsertion.AddHeader(pHeaderDescriptor) Failed."); + bRetVal = false; + goto bail; + } + if (!m_HeaderInsertion.GetHeaderHandle(&sRetHeader)) + { + LOG_MSG_ERROR(" Failed"); + bRetVal = false; + goto bail; + } + if (!CreateBypassRoutingTable(&m_Routing, m_eIP, bypass0, IPA_CLIENT_TEST3_CONS, + sRetHeader.hdl,&nRTTableHdl)) { + LOG_MSG_ERROR("CreateBypassRoutingTable Failed\n"); + bRetVal = false; + goto bail; + } + LOG_MSG_INFO("CreateBypassRoutingTable completed successfully"); + sRoutingTable.ip = m_eIP; + strlcpy(sRoutingTable.name, bypass0, sizeof(sRoutingTable.name)); + if (!m_Routing.GetRoutingTable(&sRoutingTable)) { + LOG_MSG_ERROR( + "m_routing.GetRoutingTable(&sRoutingTable=0x%p) Failed.", &sRoutingTable); + bRetVal = false; + goto bail; + } + // Creating Filtering Rules + cFilterTable.Init(m_eIP,IPA_CLIENT_TEST_PROD,false,1); + LOG_MSG_INFO("Creation of filtering table completed successfully"); + + // Configuring Filtering Rule No.1 + cFilterTable.GeneratePresetRule(0,sFilterRuleEntry); + sFilterRuleEntry.at_rear = true; + sFilterRuleEntry.flt_rule_hdl = -1; // return Value + sFilterRuleEntry.status = -1; // return value + sFilterRuleEntry.rule.action = IPA_PASS_TO_ROUTING; + sFilterRuleEntry.rule.rt_tbl_hdl = nRTTableHdl; //put here the handle corresponding to Routing Rule 1 + if ( + ((uint8_t)-1 == cFilterTable.AddRuleToTable(sFilterRuleEntry)) || + !m_Filtering.AddFilteringRule(cFilterTable.GetFilteringTable()) + ) + { + LOG_MSG_ERROR ("Adding Rule (0) to Filtering block Failed."); + bRetVal = false; + goto bail; + } else + { + LOG_MSG_DEBUG("flt rule hdl0=0x%x, status=0x%x\n", cFilterTable.ReadRuleFromTable(0)->flt_rule_hdl,cFilterTable.ReadRuleFromTable(0)->status); + } + + bail: + Free(pHeaderDescriptor); + LOG_MSG_STACK( + "Leaving Function (Returning %s)", bRetVal?"True":"False"); + return bRetVal; + } // AddRules() + + virtual bool ModifyPackets() { + // This test doesn't modify the original IP Packet. + return true; + } // ModifyPacktes () + + virtual bool TestLogic() { + memset(m_aExpectedBuffer, 0, sizeof(m_aExpectedBuffer)); + m_aExpectedBufSize = 0; + + memcpy(m_aExpectedBuffer, m_aHeadertoAdd, m_nHeadertoAddSize); + memcpy(m_aExpectedBuffer+m_nHeadertoAddSize,m_aBuffer,m_uBufferSize); + m_aExpectedBufSize = m_nHeadertoAddSize + m_uBufferSize; + if (!SendReceiveAndCompare(&m_producer, m_aBuffer, m_uBufferSize, + &m_Consumer2, m_aExpectedBuffer, m_aExpectedBufSize)) { + LOG_MSG_ERROR("SendReceiveAndCompare failed."); + return false; + } + return true; + } +private: + uint8_t m_aExpectedBuffer[BUFF_MAX_SIZE]; // Input file / IP packet + size_t m_aExpectedBufSize; + uint8_t m_aHeadertoAdd[MAX_HEADER_SIZE]; + size_t m_nHeadertoAddSize; +}; + +//---------------------------------------------------------------------------/ +// Test003: Test Three Different Header Insertions / +//---------------------------------------------------------------------------/ +class IPAHeaderInsertionTest003: public IPAHeaderInsertionTestFixture { +public: + IPAHeaderInsertionTest003() : + m_aExpectedBufSize(BUFF_MAX_SIZE), + m_nHeadertoAddSize1(0), + m_nHeadertoAddSize2(0), + m_nHeadertoAddSize3(0) + { + m_name = "IPAHeaderInsertionTest003"; + m_description = + "Header Insertion Test 003 - Test RmNet,IEEE802.3 and IEEE802.3 with const (1) addition to the length field\ + 1. Generate and commit two types of header Insertion RmNet and IEE802.3 \ + 2. Generate and commit three routing tables. \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + Routing table 1 is used to add RmNet Header \ + Routing table 2 is used to add IEEE802.3 Header (requires update of the Length field) \ + Routing table 3 is used to add IEEE802.3 Header with additional const (1) to the length field \ + 3. Generate and commit Three filtering rules (MASK = 0xFF..FF). \ + All DST_IP == 127.0.0.1 traffic goes to routing table 1 \ + All DST_IP == 192.169.1.1 traffic goes to routing table 2 \ + All DST_IP == 192.169.1.2 traffic goes to routing table 3"; + + Register(*this); + uint8_t aRMNetHeader[6] = { 0x01, 0x02, 0x03, 0x04, 0x05, 0x06}; + uint8_t aIEEE802_3Header1[22] = { 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, + 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0x00, 0x46, 0xAE, 0xAF, 0xB0, + 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6 }; + uint8_t aIEEE802_3Header2[22] = { 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, + 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0x00, 0x47, 0xAE, 0xAF, 0xB0, + 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6 }; + m_nHeadertoAddSize1 = sizeof(aRMNetHeader); + memcpy(m_aHeadertoAdd1, aRMNetHeader, m_nHeadertoAddSize1); + m_nHeadertoAddSize2 = sizeof(aIEEE802_3Header1); + memcpy(m_aHeadertoAdd2, aIEEE802_3Header1, m_nHeadertoAddSize2); + m_nHeadertoAddSize3 = sizeof(aIEEE802_3Header2); + memcpy(m_aHeadertoAdd3, aIEEE802_3Header2, m_nHeadertoAddSize3); + } + + // Test Description: + // 1. Generate and commit single bypass routing table. + virtual bool AddRules() { + m_eIP = IPA_IP_v4; + const char aBypass1[20] = "Bypass1"; + const char aBypass2[20] = "Bypass2"; + const char aBypass3[20] = "Bypass3"; + uint32_t nTableHdl01, nTableHdl02, nTableHdl03; + bool bRetVal = true; + IPAFilteringTable cFilterTable0; + struct ipa_flt_rule_add sFilterRuleEntry; + struct ipa_ioc_get_hdr sGetHeader1,sGetHeader2; + + LOG_MSG_STACK("Entering Function"); + memset(&sFilterRuleEntry, 0, sizeof(sFilterRuleEntry)); + memset(&sGetHeader1, 0, sizeof(sGetHeader1)); + memset(&sGetHeader2, 0, sizeof(sGetHeader2)); + // Create Header: + // Allocate Memory, populate it, and add in to the Header Insertion. + struct ipa_ioc_add_hdr * pHeaderDescriptor = NULL; + pHeaderDescriptor = (struct ipa_ioc_add_hdr *) calloc(1, + sizeof(struct ipa_ioc_add_hdr) + + 2 * sizeof(struct ipa_hdr_add)); + if (!pHeaderDescriptor) { + LOG_MSG_ERROR("calloc failed to allocate pHeaderDescriptor"); + bRetVal = false; + goto bail; + } + + pHeaderDescriptor->commit = true; + pHeaderDescriptor->num_hdrs = 2; + // Adding Header No1. + strlcpy(pHeaderDescriptor->hdr[0].name, "RMNet", sizeof(pHeaderDescriptor->hdr[0].name)); // Header's Name + memcpy(pHeaderDescriptor->hdr[0].hdr, m_aHeadertoAdd1, + m_nHeadertoAddSize1); //Header's Data + pHeaderDescriptor->hdr[0].hdr_len = m_nHeadertoAddSize1; + pHeaderDescriptor->hdr[0].hdr_hdl = -1; //Return Value + pHeaderDescriptor->hdr[0].is_partial = false; + pHeaderDescriptor->hdr[0].status = -1; // Return Parameter + + // Adding Header No2. + strlcpy(pHeaderDescriptor->hdr[1].name, "IEEE_802_3", sizeof(pHeaderDescriptor->hdr[1].name)); // Header's Name + memcpy(pHeaderDescriptor->hdr[1].hdr, m_aHeadertoAdd2, + m_nHeadertoAddSize2); //Header's Data + pHeaderDescriptor->hdr[1].hdr_len = m_nHeadertoAddSize2; + pHeaderDescriptor->hdr[1].hdr_hdl = -1; //Return Value + pHeaderDescriptor->hdr[1].is_partial = false; + pHeaderDescriptor->hdr[1].status = -1; // Return Parameter + + strlcpy(sGetHeader1.name, pHeaderDescriptor->hdr[0].name, sizeof(sGetHeader1.name)); + strlcpy(sGetHeader2.name, pHeaderDescriptor->hdr[1].name, sizeof(sGetHeader2.name)); + + if (!m_HeaderInsertion.AddHeader(pHeaderDescriptor)) + { + LOG_MSG_ERROR("m_HeaderInsertion.AddHeader(pHeaderDescriptor) Failed."); + bRetVal = false; + goto bail; + } + if (!m_HeaderInsertion.GetHeaderHandle(&sGetHeader1)) + { + LOG_MSG_ERROR(" Failed"); + bRetVal = false; + goto bail; + } + LOG_MSG_DEBUG("Received Header1 Handle = 0x%x",sGetHeader1.hdl); + if (!m_HeaderInsertion.GetHeaderHandle(&sGetHeader2)) + { + LOG_MSG_ERROR(" Failed"); + bRetVal = false; + goto bail; + } + LOG_MSG_DEBUG("Received Header2 Handle = 0x%x",sGetHeader2.hdl); + if (!CreateBypassRoutingTable(&m_Routing, m_eIP, aBypass1, IPA_CLIENT_TEST2_CONS, + sGetHeader1.hdl,&nTableHdl01)) { + LOG_MSG_ERROR("CreateBypassRoutingTable Failed\n"); + bRetVal = false; + goto bail; + } + if (!CreateBypassRoutingTable(&m_Routing, m_eIP, aBypass2, IPA_CLIENT_TEST3_CONS, + sGetHeader2.hdl,&nTableHdl02)) { + LOG_MSG_ERROR("CreateBypassRoutingTable Failed\n"); + bRetVal = false; + goto bail; + } + if (!CreateBypassRoutingTable(&m_Routing, m_eIP, aBypass3, IPA_CLIENT_TEST4_CONS, + sGetHeader2.hdl,&nTableHdl03)) { + LOG_MSG_ERROR("CreateBypassRoutingTable Failed\n"); + bRetVal = false; + goto bail; + } + LOG_MSG_INFO("Creation of three bypass routing tables completed successfully TblHdl1=0x%x, TblHdl2=0x%x, TblHdl3=0x%x", + nTableHdl01,nTableHdl02,nTableHdl03); + + // Creating Filtering Rules + cFilterTable0.Init(m_eIP,IPA_CLIENT_TEST_PROD,false,3); + LOG_MSG_INFO("Creation of filtering table completed successfully"); + + // Configuring Filtering Rule No.1 + cFilterTable0.GeneratePresetRule(1,sFilterRuleEntry); + sFilterRuleEntry.at_rear = true; + sFilterRuleEntry.flt_rule_hdl=-1; // return Value + sFilterRuleEntry.status = -1; // return value + sFilterRuleEntry.rule.action=IPA_PASS_TO_ROUTING; + sFilterRuleEntry.rule.rt_tbl_hdl=nTableHdl01; //put here the handle corresponding to Routing Rule 1 + sFilterRuleEntry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; // Destination IP Based Filtering + sFilterRuleEntry.rule.attrib.u.v4.dst_addr_mask = 0xFF0000FF; // Mask + sFilterRuleEntry.rule.attrib.u.v4.dst_addr = 0x7F000001; // Filter DST_IP == 127.0.0.1. + if ((uint8_t)-1 == cFilterTable0.AddRuleToTable(sFilterRuleEntry)) + { + LOG_MSG_ERROR ("Adding Rule (0) to Filtering table Failed."); + bRetVal = false; + goto bail; + } + + // Configuring Filtering Rule No.2 + sFilterRuleEntry.flt_rule_hdl=-1; // return Value + sFilterRuleEntry.status = -1; // return Value + sFilterRuleEntry.rule.rt_tbl_hdl=nTableHdl02; //put here the handle corresponding to Routing Rule 2 + sFilterRuleEntry.rule.attrib.u.v4.dst_addr = 0xC0A80101; // Filter DST_IP == 192.168.1.1. + if ((uint8_t)-1 == cFilterTable0.AddRuleToTable(sFilterRuleEntry)) + { + LOG_MSG_ERROR ("Adding Rule(1) to Filtering table Failed."); + bRetVal = false; + goto bail; + } + + // Configuring Filtering Rule No.3 + sFilterRuleEntry.flt_rule_hdl=-1; // return Value + sFilterRuleEntry.status = -1; // return value + sFilterRuleEntry.rule.rt_tbl_hdl=nTableHdl03; //put here the handle corresponding to Routing Rule 2 + sFilterRuleEntry.rule.attrib.u.v4.dst_addr = 0xC0A80102; // Filter DST_IP == 192.168.1.2. + if ((uint8_t)-1 == cFilterTable0.AddRuleToTable(sFilterRuleEntry)) + { + LOG_MSG_ERROR ("Adding Rule(2) to Filtering table Failed."); + bRetVal = false; + goto bail; + } + + if (!m_Filtering.AddFilteringRule(cFilterTable0.GetFilteringTable())) { + LOG_MSG_ERROR ("Failed to commit Filtering rules"); + bRetVal = false; + goto bail; + } + + LOG_MSG_DEBUG("flt rule hdl0=0x%x, status=0x%x\n", cFilterTable0.ReadRuleFromTable(0)->flt_rule_hdl,cFilterTable0.ReadRuleFromTable(0)->status); + LOG_MSG_DEBUG("flt rule hdl0=0x%x, status=0x%x\n", cFilterTable0.ReadRuleFromTable(1)->flt_rule_hdl,cFilterTable0.ReadRuleFromTable(1)->status); + LOG_MSG_DEBUG("flt rule hdl0=0x%x, status=0x%x\n", cFilterTable0.ReadRuleFromTable(2)->flt_rule_hdl,cFilterTable0.ReadRuleFromTable(2)->status); + + bail: + Free(pHeaderDescriptor); + LOG_MSG_STACK( + "Leaving Function (Returning %s)", bRetVal?"True":"False"); + return bRetVal; + } // AddRules() + + virtual bool ModifyPackets() { + // This test doesn't modify the original IP Packet. + return true; + } // ModifyPacktes () + + virtual bool TestLogic() { + bool bRetVal = true; + m_aExpectedBufSize = 0; + uint32_t nIPv4DSTAddr; + + LOG_MSG_STACK("Entering Function"); + + //Packet No. 1 + memset(m_aExpectedBuffer, 0, sizeof(m_aExpectedBuffer)); + nIPv4DSTAddr = ntohl(0x7F000001); + memcpy (&m_aBuffer[IPV4_DST_ADDR_OFFSET],&nIPv4DSTAddr,sizeof(nIPv4DSTAddr)); + memcpy(m_aExpectedBuffer, m_aHeadertoAdd1, m_nHeadertoAddSize1); + memcpy(m_aExpectedBuffer+m_nHeadertoAddSize1,m_aBuffer,m_uBufferSize); + m_aExpectedBufSize = m_nHeadertoAddSize1 + m_uBufferSize; + if (!SendReceiveAndCompare(&m_producer, m_aBuffer, m_uBufferSize, + &m_Consumer1, m_aExpectedBuffer, m_aExpectedBufSize)) + { + LOG_MSG_ERROR("SendReceiveAndCompare failed."); + bRetVal=false; + } + + //Packet No. 2 + memset(m_aExpectedBuffer, 0, sizeof(m_aExpectedBuffer)); + nIPv4DSTAddr = ntohl(0xC0A80101);//192.168.1.1 + memcpy (&m_aBuffer[IPV4_DST_ADDR_OFFSET],&nIPv4DSTAddr,sizeof(nIPv4DSTAddr)); + memcpy(m_aExpectedBuffer, m_aHeadertoAdd2, m_nHeadertoAddSize2); + memcpy(m_aExpectedBuffer+m_nHeadertoAddSize2,m_aBuffer,m_uBufferSize); + m_aExpectedBufSize = m_nHeadertoAddSize2 + m_uBufferSize; + if (!SendReceiveAndCompare(&m_producer, m_aBuffer, m_uBufferSize, + &m_Consumer2, m_aExpectedBuffer, m_aExpectedBufSize)) + { + LOG_MSG_ERROR("SendReceiveAndCompare failed."); + bRetVal=false; + } + + //Packet No. 3 + nIPv4DSTAddr = ntohl(0xC0A80102);//192.168.1.2 + memcpy (&m_aBuffer[IPV4_DST_ADDR_OFFSET],&nIPv4DSTAddr,sizeof(nIPv4DSTAddr)); + memcpy(m_aExpectedBuffer, m_aHeadertoAdd3, m_nHeadertoAddSize3); + memcpy(m_aExpectedBuffer+m_nHeadertoAddSize3,m_aBuffer,m_uBufferSize); + m_aExpectedBufSize = m_nHeadertoAddSize3 + m_uBufferSize; + if (!SendReceiveAndCompare(&m_producer, m_aBuffer, m_uBufferSize, + &m_Consumer3, m_aExpectedBuffer, m_aExpectedBufSize)) + { + LOG_MSG_ERROR("SendReceiveAndCompare failed."); + bRetVal=false; + } + + LOG_MSG_STACK("Leaving Function (Returning %s)",bRetVal?"True":"False"); + return bRetVal; + } +private: + uint8_t m_aExpectedBuffer[BUFF_MAX_SIZE]; // Input file / IP packet + size_t m_aExpectedBufSize; + uint8_t m_aHeadertoAdd1[MAX_HEADER_SIZE],m_aHeadertoAdd2[MAX_HEADER_SIZE],m_aHeadertoAdd3[MAX_HEADER_SIZE]; + size_t m_nHeadertoAddSize1,m_nHeadertoAddSize2,m_nHeadertoAddSize3; +}; + +class IPAHeaderInsertionTest004: public IPAHeaderInsertionTestFixture { +public: + IPAHeaderInsertionTest004() { + m_name = "IPAHeaderInsertionTest004"; + m_description = + "Header Insertion Test 004 - Test header insertion with bad len values."; + Register(*this); + uint8_t aRMNetHeader[6] = { 0x01, 0x02, 0x03, 0x04, 0x05, 0x06}; + m_nHeadertoAddSize = sizeof(aRMNetHeader); + memcpy(m_aHeadertoAdd, aRMNetHeader, m_nHeadertoAddSize); + } + + virtual bool AddRules() { + // Not adding any rules here. + return true; + } // AddRules() + + virtual bool ModifyPackets() { + // This test doesn't modify the original IP Packet. + return true; + } // ModifyPacktes () + + bool AddSingleHeaderAndCheck(uint8_t len) { + m_eIP = IPA_IP_v4; + bool bRetVal = true; + struct ipa_ioc_get_hdr sRetHeader; + memset(&sRetHeader, 0, sizeof(sRetHeader)); + strlcpy(sRetHeader.name, "Generic", sizeof(sRetHeader.name)); + + LOG_MSG_STACK("Entering Function"); + // Create Header: + // Allocate Memory, populate it, and add in to the Header Insertion. + struct ipa_ioc_add_hdr * pHeaderDescriptor = NULL; + pHeaderDescriptor = (struct ipa_ioc_add_hdr *) calloc(1, + sizeof(struct ipa_ioc_add_hdr) + + 1 * sizeof(struct ipa_hdr_add)); + if (!pHeaderDescriptor) { + LOG_MSG_ERROR("calloc failed to allocate pHeaderDescriptor"); + bRetVal = false; + goto bail; + } + pHeaderDescriptor->commit = true; + pHeaderDescriptor->num_hdrs = 1; + strlcpy(pHeaderDescriptor->hdr[0].name, sRetHeader.name, sizeof(pHeaderDescriptor->hdr[0].name)); + memcpy(pHeaderDescriptor->hdr[0].hdr, m_aHeadertoAdd, + m_nHeadertoAddSize); //Header's Data + pHeaderDescriptor->hdr[0].hdr_len = len; + pHeaderDescriptor->hdr[0].hdr_hdl = -1; //Return Value + pHeaderDescriptor->hdr[0].is_partial = false; + pHeaderDescriptor->hdr[0].status = -1; // Return Parameter + strlcpy(sRetHeader.name, pHeaderDescriptor->hdr[0].name, sizeof(sRetHeader.name)); + + if (!m_HeaderInsertion.AddHeader(pHeaderDescriptor)) + { + LOG_MSG_ERROR("m_HeaderInsertion.AddHeader(pHeaderDescriptor) Failed."); + bRetVal = false; + goto bail; + } + + if (!m_HeaderInsertion.GetHeaderHandle(&sRetHeader)) + { + LOG_MSG_ERROR(" Failed"); + bRetVal = false; + goto bail; + } + + bail: + Free(pHeaderDescriptor); + LOG_MSG_STACK( + "Leaving Function (Returning %s)", bRetVal?"True":"False"); + return bRetVal; + } // AddSingleHeaderAndCheck() + + virtual bool TestLogic() { + + // Try to add headers with invalid values. + // Valid values are between 0 to IPA_HDR_MAX_SIZE (64). + + // We expect the below function to fail. + if (AddSingleHeaderAndCheck(MAX_HEADER_SIZE + 1)) { + LOG_MSG_ERROR("This is unexpected, this can't succeed"); + return false; + } + + // Add one header which is OK + if (!AddSingleHeaderAndCheck(m_nHeadertoAddSize)) { + LOG_MSG_ERROR("This is unexpected, this can't succeed"); + return false; + } + return true; + } + +private: + uint8_t m_aHeadertoAdd[MAX_HEADER_SIZE]; + size_t m_nHeadertoAddSize; +}; + +class IPAHeaderInsertionTest005: public IPAHeaderInsertionTestFixture { +public: + IPAHeaderInsertionTest005() { + m_name = "IPAHeaderInsertionTest005"; + m_description = + "Header Insertion Test 005 - Test Multiple RMNet Header Insertion\ + - Stress test - Generate and commit multiple header Insertion"; + this->m_runInRegression = false; + Register(*this); + uint8_t aRMNetHeader[6] = { 0x01, 0x02, 0x03, 0x04, 0x05, 0x06}; + m_nHeadertoAddSize = sizeof(aRMNetHeader); + memcpy(m_aHeadertoAdd, aRMNetHeader, m_nHeadertoAddSize); + } + + // Test Description: + // 1. Generate and commit single bypass routing table. + virtual bool AddRules() { + m_eIP = IPA_IP_v4; + bool bRetVal = true; + struct ipa_ioc_get_hdr sRetHeader; + char Name[] = "IEEE802_3\0"; + + memset(&sRetHeader, 0, sizeof(sRetHeader)); + strlcpy (sRetHeader.name, Name, sizeof(sRetHeader.name)); + LOG_MSG_STACK("Entering Function"); + // Create Header: + // Allocate Memory, populate it, and add in to the Header Insertion. + struct ipa_ioc_add_hdr * pHeaderDescriptor = NULL; + pHeaderDescriptor = (struct ipa_ioc_add_hdr *) calloc(1, + sizeof(struct ipa_ioc_add_hdr) + + 1 * sizeof(struct ipa_hdr_add)); + if (!pHeaderDescriptor) { + LOG_MSG_ERROR("calloc failed to allocate pHeaderDescriptor"); + bRetVal = false; + goto bail; + } + pHeaderDescriptor->commit = true; + pHeaderDescriptor->num_hdrs = 1; + strlcpy(pHeaderDescriptor->hdr[0].name, sRetHeader.name, sizeof(pHeaderDescriptor->hdr[0].name)); + memcpy(pHeaderDescriptor->hdr[0].hdr, m_aHeadertoAdd, + m_nHeadertoAddSize); //Header's Data + pHeaderDescriptor->hdr[0].hdr_len = m_nHeadertoAddSize; + pHeaderDescriptor->hdr[0].hdr_hdl = -1; //Return Value + pHeaderDescriptor->hdr[0].is_partial = false; + pHeaderDescriptor->hdr[0].status = -1; // Return Parameter + strlcpy(sRetHeader.name, pHeaderDescriptor->hdr[0].name, sizeof(sRetHeader.name)); + + // stress test to check if the target crashes, failure is expected before reaching 500 + for (int i = 0; i < 500; i++) { + LOG_MSG_DEBUG("IPAHeaderInsertionTest005::AddRules iter=%d\n",i); + if (!m_HeaderInsertion.AddHeader(pHeaderDescriptor)) + { + LOG_MSG_ERROR("m_HeaderInsertion.AddHeader(pHeaderDescriptor) Failed on %d iteration.\n",i); + goto bail; + } + } + + bail: + Free(pHeaderDescriptor); + LOG_MSG_STACK( + "Leaving Function (Returning %s)", bRetVal?"True":"False"); + return bRetVal; + } // AddRules() + + virtual bool ModifyPackets() { + // This test doesn't modify the original IP Packet. + return true; + } // ModifyPacktes () + + virtual bool TestLogic() { + return true; + } +private: + uint8_t m_aHeadertoAdd[MAX_HEADER_SIZE]; + size_t m_nHeadertoAddSize; +}; + +class IPAHeaderInsertionTest006: public IPAHeaderInsertionTestFixture { +public: + IPAHeaderInsertionTest006() { + m_name = "IPAHeaderInsertionTest006"; + m_description = + "Header Insertion Test 006 - Test header distriburion between SRAM and DDR\ + - fill SRAM and some DDR, use DDR header"; + this->m_runInRegression = true; + Register(*this); + uint8_t aRMNetHeader[6] = { 0x01, 0x02, 0x03, 0x04, 0x05, 0x06}; + m_nHeadertoAddSize = sizeof(aRMNetHeader); + memcpy(m_aHeadertoAdd, aRMNetHeader, m_nHeadertoAddSize); + m_minIPAHwType = IPA_HW_v5_0; + + // The bin size is 8 + // We are going to add number of headers to occupy twice the size of the SRAM buffer + m_InitialHeadersNum = GetHdrSramSize() / 8 * 2; + m_HeadersNumToDelete = 0; + m_HeadersNumToAddAgain = 0; + } + + virtual bool AddRules() { + bool bRetVal = true; + m_eIP = IPA_IP_v4; + struct ipa_ioc_add_hdr *pHeaderDescriptor = NULL; + struct ipa_ioc_del_hdr *pDelHeaderDescriptor = NULL; + + memset(&m_RetHeader, 0, sizeof(m_RetHeader)); + LOG_MSG_STACK("Entering Function"); + + if (m_InitialHeadersNum <= 0) + { + LOG_MSG_ERROR("Initial headers number is set to 0!\n"); + bRetVal = false; + goto bail; + } + + pHeaderDescriptor = (struct ipa_ioc_add_hdr *) calloc(1, + sizeof(struct ipa_ioc_add_hdr) + 1 * sizeof(struct ipa_hdr_add)); + if (m_HeadersNumToDelete > 0) + pDelHeaderDescriptor = (struct ipa_ioc_del_hdr *)calloc(1, + sizeof(struct ipa_ioc_del_hdr) + m_HeadersNumToDelete * sizeof(struct ipa_hdr_del)); + if (!pHeaderDescriptor || (m_HeadersNumToDelete > 0 && !pDelHeaderDescriptor)) + { + LOG_MSG_ERROR("calloc failed to allocate ipa_ioc_add_hdr or ipa_ioc_del_hdr"); + bRetVal = false; + goto bail; + } + + // Add bunch of headers to SRAM and DDR + pHeaderDescriptor->commit = true; + pHeaderDescriptor->num_hdrs = 1; + memcpy(pHeaderDescriptor->hdr[0].hdr, m_aHeadertoAdd, m_nHeadertoAddSize); + pHeaderDescriptor->hdr[0].hdr_len = m_nHeadertoAddSize; + pHeaderDescriptor->hdr[0].hdr_hdl = -1; //Return Value + pHeaderDescriptor->hdr[0].is_partial = false; + pHeaderDescriptor->hdr[0].status = -1; // Return Parameter + + fflush(stderr); + fflush(stdout); + ret = system("cat /sys/kernel/debug/ipa/hdr"); + + for (int i = 0; i < m_InitialHeadersNum; i++) + { + LOG_MSG_DEBUG("%s::%s iter=%d\n", typeid(this).name(), __func__, i); + snprintf(pHeaderDescriptor->hdr[0].name, sizeof(pHeaderDescriptor->hdr[0].name), "IEEE802_3_%03d", i); + if (!m_HeaderInsertion.AddHeader(pHeaderDescriptor)) + { + LOG_MSG_ERROR("m_HeaderInsertion.AddHeader(pHeaderDescriptor) Failed on %d iteration.\n", i); + bRetVal = false; + goto bail; + } + // Store header descriptors to delete + if (m_HeadersNumToDelete > 0 && i < m_HeadersNumToDelete) { + pDelHeaderDescriptor->hdl[i].hdl = pHeaderDescriptor->hdr[0].hdr_hdl; + } + } + strlcpy(m_RetHeader.name, pHeaderDescriptor->hdr[0].name, sizeof(m_RetHeader.name)); + + fflush(stderr); + fflush(stdout); + ret = system("cat /sys/kernel/debug/ipa/hdr"); + + + if (m_HeadersNumToDelete > 0) + { + // Delete few headers from SRAM + pDelHeaderDescriptor->commit = true; + pDelHeaderDescriptor->num_hdls = m_HeadersNumToDelete; + for (int i = 0; i < m_HeadersNumToDelete; i++) + pDelHeaderDescriptor->hdl[i].status = -1; // Return Parameter + if (!m_HeaderInsertion.DeleteHeader(pDelHeaderDescriptor)) + { + LOG_MSG_ERROR("m_HeaderInsertion.DeleteHeader(pDelHeaderDescriptor) Failed"); + bRetVal = false; + goto bail; + } + + fflush(stderr); + fflush(stdout); + ret = system("cat /sys/kernel/debug/ipa/hdr"); + } + + if (m_HeadersNumToAddAgain > 0) + { + // Add few new headers to SRAM + pHeaderDescriptor->commit = true; + pHeaderDescriptor->num_hdrs = 1; + memcpy(pHeaderDescriptor->hdr[0].hdr, m_aHeadertoAdd, m_nHeadertoAddSize); + pHeaderDescriptor->hdr[0].hdr_len = m_nHeadertoAddSize; + pHeaderDescriptor->hdr[0].hdr_hdl = -1; //Return Value + pHeaderDescriptor->hdr[0].is_partial = false; + pHeaderDescriptor->hdr[0].status = -1; // Return Parameter + + for (int i = 0; i < m_HeadersNumToAddAgain; i++) { + LOG_MSG_DEBUG("%s::%s iter=%d\n", typeid(this).name(), __func__, i); + snprintf(pHeaderDescriptor->hdr[0].name, sizeof(pHeaderDescriptor->hdr[0].name), "IEEE802_3_%03d_2", i); + if (!m_HeaderInsertion.AddHeader(pHeaderDescriptor)) + { + LOG_MSG_ERROR("m_HeaderInsertion.AddHeader(pHeaderDescriptor) Failed on %d iteration.\n", i); + bRetVal = false; + goto bail; + } + } + strlcpy(m_RetHeader.name, pHeaderDescriptor->hdr[0].name, sizeof(m_RetHeader.name)); + + fflush(stderr); + fflush(stdout); + ret = system("cat /sys/kernel/debug/ipa/hdr"); + } + + // Use last added header for traffic + if (!m_HeaderInsertion.GetHeaderHandle(&m_RetHeader)) + { + LOG_MSG_ERROR(" Failed"); + bRetVal = false; + goto bail; + } + + bRetVal = CreateFilteringAndRouting(); + bail: + Free(pHeaderDescriptor); + if (pDelHeaderDescriptor) + Free(pDelHeaderDescriptor); + LOG_MSG_STACK("Leaving %s (Returning %s)", __func__, bRetVal ? "True" : "False"); + return bRetVal; + } // AddRules() + + virtual bool CreateFilteringAndRouting() { + uint32_t nRTTableHdl=0; + const char bypass0[20] = "Bypass0"; + struct ipa_ioc_get_rt_tbl sRoutingTable; + struct ipa_flt_rule_add sFilterRuleEntry; + IPAFilteringTable cFilterTable; + + memset(&sRoutingTable, 0, sizeof(sRoutingTable)); + + // Create RT table + if (!CreateBypassRoutingTable(&m_Routing, m_eIP, bypass0, IPA_CLIENT_TEST2_CONS, + m_RetHeader.hdl,&nRTTableHdl)) { + LOG_MSG_ERROR("CreateBypassRoutingTable Failed\n"); + return false; + } + LOG_MSG_INFO("CreateBypassRoutingTable completed successfully"); + sRoutingTable.ip = m_eIP; + strlcpy(sRoutingTable.name, bypass0, sizeof(sRoutingTable.name)); + if (!m_Routing.GetRoutingTable(&sRoutingTable)) { + LOG_MSG_ERROR("m_routing.GetRoutingTable(&sRoutingTable=0x%p) Failed.", + &sRoutingTable); + return false; + } + + // Creating Filtering Rules + cFilterTable.Init(m_eIP, IPA_CLIENT_TEST_PROD, false, 1); + LOG_MSG_INFO("Creation of filtering table completed successfully"); + + // Configuring Filtering Rule No.1 + cFilterTable.GeneratePresetRule(0, sFilterRuleEntry); + sFilterRuleEntry.at_rear = true; + sFilterRuleEntry.flt_rule_hdl = -1; // return Value + sFilterRuleEntry.status = -1; // return value + sFilterRuleEntry.rule.action = IPA_PASS_TO_ROUTING; + sFilterRuleEntry.rule.rt_tbl_hdl = nRTTableHdl; //put here the handle corresponding to Routing Rule 1 + if (((uint8_t)-1 == cFilterTable.AddRuleToTable(sFilterRuleEntry)) || + !m_Filtering.AddFilteringRule(cFilterTable.GetFilteringTable())) + { + LOG_MSG_ERROR ("Adding Rule (0) to Filtering block Failed."); + return false; + } + else + { + LOG_MSG_DEBUG("flt rule hdl0=0x%x, status=0x%x\n", + cFilterTable.ReadRuleFromTable(0)->flt_rule_hdl, + cFilterTable.ReadRuleFromTable(0)->status); + } + return true; + } + + virtual bool ModifyPackets() { + return true; + } + + virtual bool TestLogic() { + memset(m_aExpectedBuffer, 0, sizeof(m_aExpectedBuffer)); + m_aExpectedBufSize = 0; + + memcpy(m_aExpectedBuffer, m_aHeadertoAdd, m_nHeadertoAddSize); + memcpy(m_aExpectedBuffer+m_nHeadertoAddSize,m_aBuffer,m_uBufferSize); + m_aExpectedBufSize = m_nHeadertoAddSize + m_uBufferSize; + if (!SendReceiveAndCompare(&m_producer, m_aBuffer, m_uBufferSize, + &m_Consumer1, m_aExpectedBuffer, m_aExpectedBufSize)) { + LOG_MSG_ERROR("SendReceiveAndCompare failed."); + return false; + } + return true; + } + +protected: + struct ipa_ioc_get_hdr m_RetHeader; + int m_InitialHeadersNum; + int m_HeadersNumToDelete; + int m_HeadersNumToAddAgain; + +private: + uint8_t m_aExpectedBuffer[BUFF_MAX_SIZE]; // Input file / IP packet + size_t m_aExpectedBufSize; + uint8_t m_aHeadertoAdd[MAX_HEADER_SIZE]; + size_t m_nHeadertoAddSize; + int ret; +}; + +class IPAHeaderInsertionTest007: public IPAHeaderInsertionTest006 { +public: + IPAHeaderInsertionTest007() { + m_name = "IPAHeaderInsertionTest007"; + m_description = + "Header Insertion Test 007 - Test header distriburion between SRAM and DDR\ + - fill SRAM and some DDR, free some SRAM, use DDR header"; + // We will delete half of the headers in the SRAM, + // which is quarter of the total initial headers number + m_HeadersNumToDelete = m_InitialHeadersNum / 4; + m_HeadersNumToAddAgain = 0; + } +}; + +class IPAHeaderInsertionTest008: public IPAHeaderInsertionTest006 { +public: + IPAHeaderInsertionTest008() { + m_name = "IPAHeaderInsertionTest008"; + m_description = + "Header Insertion Test 008 - Test header distriburion between SRAM and DDR\ + - fill SRAM and some DDR, free some SRAM, add few new SRAM headers, \ + use last SRAM header"; + // We will delete half of the headers in the SRAM, + // which is quarter of the total initial headers number + m_HeadersNumToDelete = m_InitialHeadersNum / 4; + // We will add again half of the number of headers we deleted + m_HeadersNumToAddAgain = m_HeadersNumToDelete / 2; + } +}; + +class IPAHeaderInsertionTest009: public IPAHeaderInsertionTest006 { +public: + IPAHeaderInsertionTest009() { + m_name = "IPAHeaderInsertionTest009"; + m_description = + "Header Insertion Test 009 - Test header distriburion between SRAM and DDR \ + - fill SRAM and some DDR, free some SRAM and DDR, \ + add new SRAM and DDR headers, \ + use last added DDR header"; + // We will delete all the headers in SRAM and half of the headers in the DDR, + // which is 3/4 of the total initial headers number + m_HeadersNumToDelete = m_InitialHeadersNum - (m_InitialHeadersNum / 4); + // We will add again one less header than deleted + m_HeadersNumToAddAgain = m_InitialHeadersNum - m_HeadersNumToDelete - 1; + } +}; + +class IPAHeaderInsertionTest010: public IPAHeaderInsertionTestFixture { +public: + IPAHeaderInsertionTest010() : + m_aExpectedBufSize(BUFF_MAX_SIZE), + m_nHeadertoAddSize1(0), + m_nHeadertoAddSize2(0) + { + m_name = "IPAHeaderInsertionTest010"; + m_description = + "Header Insertion Test 010 - Test header distriburion between SRAM and DDR\ + - fill SRAM and some DDR, use one SRAM and one DDR header"; + m_minIPAHwType = IPA_HW_v5_0; + + Register(*this); + uint8_t aIEEE802_3Header1[22] = { 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, + 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0x00, 0x46, 0xAE, 0xAF, 0xB0, + 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6 }; + uint8_t aIEEE802_3Header2[22] = { 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, + 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0x00, 0x47, 0xAE, 0xAF, 0xB0, + 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6 }; + m_nHeadertoAddSize1 = sizeof(aIEEE802_3Header1); + memcpy(m_aHeadertoAdd1, aIEEE802_3Header1, m_nHeadertoAddSize1); + m_nHeadertoAddSize2 = sizeof(aIEEE802_3Header2); + memcpy(m_aHeadertoAdd2, aIEEE802_3Header2, m_nHeadertoAddSize2); + + // The packet size is 22, therefore the bin size is 24 + // We are going to add number of headers to occupy twice the size of the SRAM buffer + m_InitialHeadersNum = GetHdrSramSize() / 24 * 2; + } + + virtual bool AddRules() { + m_eIP = IPA_IP_v4; + const char aBypass1[20] = "Bypass1"; + const char aBypass2[20] = "Bypass2"; + uint32_t nTableHdl01, nTableHdl02; + bool bRetVal = true; + IPAFilteringTable cFilterTable0; + struct ipa_flt_rule_add sFilterRuleEntry; + struct ipa_ioc_add_hdr *pHeaderDescriptor = NULL; + + LOG_MSG_STACK("Entering Function"); + + if (m_InitialHeadersNum <= 0) + { + LOG_MSG_ERROR("Initial headers number is set to 0!\n"); + bRetVal = false; + goto bail; + } + + memset(&sFilterRuleEntry, 0, sizeof(sFilterRuleEntry)); + memset(&m_RetHeader1, 0, sizeof(m_RetHeader1)); + memset(&m_RetHeader2, 0, sizeof(m_RetHeader2)); + + pHeaderDescriptor = (struct ipa_ioc_add_hdr *) calloc(1, + sizeof(struct ipa_ioc_add_hdr) + 1 * sizeof(struct ipa_hdr_add)); + if (!pHeaderDescriptor) + { + LOG_MSG_ERROR("calloc failed to allocate ipa_ioc_add_hdr"); + bRetVal = false; + goto bail; + } + + fflush(stderr); + fflush(stdout); + ret = system("cat /sys/kernel/debug/ipa/hdr"); + + // Add one header to SRAM + pHeaderDescriptor->commit = true; + pHeaderDescriptor->num_hdrs = 1; + pHeaderDescriptor->hdr[0].status = -1; // Return Parameter + pHeaderDescriptor->hdr[0].hdr_hdl = -1; //Return Value + pHeaderDescriptor->hdr[0].is_partial = false; + + memcpy(pHeaderDescriptor->hdr[0].hdr, m_aHeadertoAdd1, m_nHeadertoAddSize1); + pHeaderDescriptor->hdr[0].hdr_len = m_nHeadertoAddSize1; + strlcpy(pHeaderDescriptor->hdr[0].name, "IEEE802_3_SRAM", sizeof(pHeaderDescriptor->hdr[0].name)); + strlcpy(m_RetHeader1.name, pHeaderDescriptor->hdr[0].name, sizeof(m_RetHeader1.name)); + if (!m_HeaderInsertion.AddHeader(pHeaderDescriptor)) + { + LOG_MSG_ERROR("m_HeaderInsertion.AddHeader(pHeaderDescriptor) Failed\n"); + bRetVal = false; + goto bail; + } + + // Add bunch of headers to SRAM and DDR + for (int i = 1; i < m_InitialHeadersNum; i++) + { + LOG_MSG_DEBUG("%s::%s iter=%d\n", typeid(this).name(), __func__, i); + memcpy(pHeaderDescriptor->hdr[0].hdr, m_aHeadertoAdd2, m_nHeadertoAddSize2); + pHeaderDescriptor->hdr[0].hdr_len = m_nHeadertoAddSize2; + snprintf(pHeaderDescriptor->hdr[0].name, sizeof(pHeaderDescriptor->hdr[0].name), + "IEEE802_3_%03d", i); + if (!m_HeaderInsertion.AddHeader(pHeaderDescriptor)) + { + LOG_MSG_ERROR("m_HeaderInsertion.AddHeader(pHeaderDescriptor) Failed on %d iteration.\n", i); + bRetVal = false; + goto bail; + } + } + strlcpy(m_RetHeader2.name, pHeaderDescriptor->hdr[0].name, sizeof(m_RetHeader2.name)); + + fflush(stderr); + fflush(stdout); + ret = system("cat /sys/kernel/debug/ipa/hdr"); + + if (!m_HeaderInsertion.GetHeaderHandle(&m_RetHeader1)) + { + LOG_MSG_ERROR(" Failed"); + bRetVal = false; + goto bail; + } + LOG_MSG_DEBUG("Received Header1 Handle = 0x%x", m_RetHeader1.hdl); + + if (!m_HeaderInsertion.GetHeaderHandle(&m_RetHeader2)) + { + LOG_MSG_ERROR(" Failed"); + bRetVal = false; + goto bail; + } + LOG_MSG_DEBUG("Received Header2 Handle = 0x%x", m_RetHeader2.hdl); + + if (!CreateBypassRoutingTable(&m_Routing, m_eIP, aBypass1, IPA_CLIENT_TEST3_CONS, + m_RetHeader1.hdl, &nTableHdl01)) { + LOG_MSG_ERROR("CreateBypassRoutingTable Failed\n"); + bRetVal = false; + goto bail; + } + if (!CreateBypassRoutingTable(&m_Routing, m_eIP, aBypass2, IPA_CLIENT_TEST4_CONS, + m_RetHeader2.hdl, &nTableHdl02)) { + LOG_MSG_ERROR("CreateBypassRoutingTable Failed\n"); + bRetVal = false; + goto bail; + } + LOG_MSG_INFO("Creation of two bypass routing tables completed successfully TblHdl1=0x%x, TblHdl2=0x%x", + nTableHdl01, nTableHdl02); + + // Creating Filtering Rules + cFilterTable0.Init(m_eIP, IPA_CLIENT_TEST_PROD, false, 2); + LOG_MSG_INFO("Creation of filtering table completed successfully"); + + // Configuring common Filtering fields + cFilterTable0.GeneratePresetRule(1, sFilterRuleEntry); + sFilterRuleEntry.at_rear = true; + sFilterRuleEntry.rule.action = IPA_PASS_TO_ROUTING; + sFilterRuleEntry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; // Destination IP Based Filtering + sFilterRuleEntry.rule.attrib.u.v4.dst_addr_mask = 0xFF0000FF; // Mask + + // Configuring Filtering Rule No.1 + sFilterRuleEntry.flt_rule_hdl = -1; // return Value + sFilterRuleEntry.status = -1; // return Value + sFilterRuleEntry.rule.rt_tbl_hdl = nTableHdl01; //put here the handle corresponding to Routing Rule 1 + sFilterRuleEntry.rule.attrib.u.v4.dst_addr = 0xC0A80101; // Filter DST_IP == 192.168.1.1. + if ((uint8_t)-1 == cFilterTable0.AddRuleToTable(sFilterRuleEntry)) + { + LOG_MSG_ERROR ("Adding Rule(1) to Filtering table Failed."); + bRetVal = false; + goto bail; + } + + // Configuring Filtering Rule No.2 + sFilterRuleEntry.flt_rule_hdl = -1; // return Value + sFilterRuleEntry.status = -1; // return value + sFilterRuleEntry.rule.rt_tbl_hdl = nTableHdl02; //put here the handle corresponding to Routing Rule 2 + sFilterRuleEntry.rule.attrib.u.v4.dst_addr = 0xC0A80102; // Filter DST_IP == 192.168.1.2. + if ((uint8_t)-1 == cFilterTable0.AddRuleToTable(sFilterRuleEntry)) + { + LOG_MSG_ERROR ("Adding Rule(2) to Filtering table Failed."); + bRetVal = false; + goto bail; + } + + if (!m_Filtering.AddFilteringRule(cFilterTable0.GetFilteringTable())) { + LOG_MSG_ERROR ("Failed to commit Filtering rules"); + bRetVal = false; + goto bail; + } + + LOG_MSG_DEBUG("flt rule hdl0=0x%x, status=0x%x\n", + cFilterTable0.ReadRuleFromTable(0)->flt_rule_hdl, + cFilterTable0.ReadRuleFromTable(0)->status); + LOG_MSG_DEBUG("flt rule hdl0=0x%x, status=0x%x\n", + cFilterTable0.ReadRuleFromTable(1)->flt_rule_hdl, + cFilterTable0.ReadRuleFromTable(1)->status); + + bail: + Free(pHeaderDescriptor); + LOG_MSG_STACK("Leaving Function (Returning %s)", bRetVal ? "True" : "False"); + return bRetVal; + } // AddRules() + + virtual bool ModifyPackets() { + // This test doesn't modify the original IP Packet. + return true; + } // ModifyPacktes () + + virtual bool TestLogic() { + bool bRetVal = true; + m_aExpectedBufSize = 0; + uint32_t nIPv4DSTAddr; + + LOG_MSG_STACK("Entering Function"); + + //Packet No. 1 + memset(m_aExpectedBuffer, 0, sizeof(m_aExpectedBuffer)); + nIPv4DSTAddr = ntohl(0xC0A80101); //192.168.1.1 + memcpy(&m_aBuffer[IPV4_DST_ADDR_OFFSET], &nIPv4DSTAddr, sizeof(nIPv4DSTAddr)); + memcpy(m_aExpectedBuffer, m_aHeadertoAdd1, m_nHeadertoAddSize1); + memcpy(m_aExpectedBuffer+m_nHeadertoAddSize1,m_aBuffer,m_uBufferSize); + m_aExpectedBufSize = m_nHeadertoAddSize1 + m_uBufferSize; + if (!SendReceiveAndCompare(&m_producer, m_aBuffer, m_uBufferSize, + &m_Consumer2, m_aExpectedBuffer, m_aExpectedBufSize)) + { + LOG_MSG_ERROR("SendReceiveAndCompare failed."); + bRetVal=false; + } + + //Packet No. 2 + memset(m_aExpectedBuffer, 0, sizeof(m_aExpectedBuffer)); + nIPv4DSTAddr = ntohl(0xC0A80102); //192.168.1.2 + memcpy (&m_aBuffer[IPV4_DST_ADDR_OFFSET], &nIPv4DSTAddr, sizeof(nIPv4DSTAddr)); + memcpy(m_aExpectedBuffer, m_aHeadertoAdd2, m_nHeadertoAddSize2); + memcpy(m_aExpectedBuffer+m_nHeadertoAddSize2, m_aBuffer, m_uBufferSize); + m_aExpectedBufSize = m_nHeadertoAddSize2 + m_uBufferSize; + if (!SendReceiveAndCompare(&m_producer, m_aBuffer, m_uBufferSize, + &m_Consumer3, m_aExpectedBuffer, m_aExpectedBufSize)) + { + LOG_MSG_ERROR("SendReceiveAndCompare failed."); + bRetVal=false; + } + + LOG_MSG_STACK("Leaving Function (Returning %s)",bRetVal?"True":"False"); + return bRetVal; + } + +protected: + struct ipa_ioc_get_hdr m_RetHeader1, m_RetHeader2; + int m_InitialHeadersNum; + +private: + uint8_t m_aExpectedBuffer[BUFF_MAX_SIZE]; // Input file / IP packet + size_t m_aExpectedBufSize; + uint8_t m_aHeadertoAdd1[MAX_HEADER_SIZE], m_aHeadertoAdd2[MAX_HEADER_SIZE]; + size_t m_nHeadertoAddSize1, m_nHeadertoAddSize2; + int ret; +}; + +static IPAHeaderInsertionTest001 ipaHeaderInsertionTest001; +static IPAHeaderInsertionTest002 ipaHeaderInsertionTest002; +static IPAHeaderInsertionTest003 ipaHeaderInsertionTest003; +static IPAHeaderInsertionTest004 ipaHeaderInsertionTest004; +static IPAHeaderInsertionTest005 ipaHeaderInsertionTest005; +static IPAHeaderInsertionTest006 ipaHeaderInsertionTest006; +static IPAHeaderInsertionTest007 ipaHeaderInsertionTest007; +static IPAHeaderInsertionTest008 ipaHeaderInsertionTest008; +static IPAHeaderInsertionTest009 ipaHeaderInsertionTest009; +static IPAHeaderInsertionTest010 ipaHeaderInsertionTest010; + diff --git a/qcom/opensource/dataipa/kernel-tests/HeaderProcessingContextTestFixture.cpp b/qcom/opensource/dataipa/kernel-tests/HeaderProcessingContextTestFixture.cpp new file mode 100644 index 0000000000..08c3a6de6c --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/HeaderProcessingContextTestFixture.cpp @@ -0,0 +1,618 @@ +/* + * Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "HeaderProcessingContextTestFixture.h" +#include "TestsUtils.h" + +const Byte IpaHdrProcCtxTestFixture::WLAN_ETH2_HDR[WLAN_ETH2_HDR_SIZE] = +{ + // WLAN hdr - 4 bytes + 0xa1, 0xb2, 0xc3, 0xd4, + + // ETH2 - 14 bytes + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00 +}; + +const Byte IpaHdrProcCtxTestFixture::ETH2_HDR[ETH_HLEN] = +{ + // ETH2 - 14 bytes + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00 +}; + +const Byte IpaHdrProcCtxTestFixture::ETH2_8021Q_HDR[ETH8021Q_HEADER_LEN] = +{ + // 802_1Q - 18 bytes + // src and dst MAC - 6 + 6 bytes + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + + // 802_1Q tag - VLAN ID 3 + 0x81, 0x00, 0x00, 0x03, + // ethertype + 0x00, 0x00 +}; + +const Byte IpaHdrProcCtxTestFixture::WLAN_802_3_HDR[WLAN_802_3_HDR_SIZE] = +{ + // WLAN hdr - 4 bytes + 0x0a, 0x0b, 0x0c, 0x0d, + + // 802_3 - 26 bytes + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00 +}; + +IpaHdrProcCtxTestFixture::IpaHdrProcCtxTestFixture(): + m_procCtxHandleId(PROC_CTX_HANDLE_ID_MAX), + m_pCurrentProducer(NULL), + m_pCurrentConsumer(NULL), + m_sendSize1 (m_BUFF_MAX_SIZE), + m_sendSize2 (m_BUFF_MAX_SIZE), + m_expectedBufferSize1(0), + m_IpaIPType(IPA_IP_v4) +{ + memset(m_headerHandles, 0, sizeof(m_headerHandles)); + memset(m_procCtxHHandles, 0, sizeof(m_procCtxHHandles)); + memset(m_sendBuffer1, 0, sizeof(m_sendBuffer1)); + memset(m_sendBuffer2, 0, sizeof(m_sendBuffer2)); + memset(m_expectedBuffer1, 0, sizeof(m_expectedBuffer1)); + m_testSuiteName.push_back("HdrProcCtx"); +} + +bool IpaHdrProcCtxTestFixture::Setup() +{ + ConfigureScenario(PHASE_TWENTY_TEST_CONFIGURATION); + + // init producers + m_rndisEth2Producer.Open(INTERFACE0_TO_IPA_DATA_PATH, + INTERFACE0_FROM_IPA_DATA_PATH); + m_wlanEth2producer.Open(INTERFACE4_TO_IPA_DATA_PATH, + INTERFACE4_FROM_IPA_DATA_PATH); + m_eth2Producer.Open(INTERFACE5_TO_IPA_DATA_PATH, + INTERFACE5_FROM_IPA_DATA_PATH); + + // init consumers + m_defaultConsumer.Open(INTERFACE1_TO_IPA_DATA_PATH, + INTERFACE1_FROM_IPA_DATA_PATH); + m_rndisEth2Consumer.Open(INTERFACE2_TO_IPA_DATA_PATH, + INTERFACE2_FROM_IPA_DATA_PATH); + + if (!m_headerInsertion.DeviceNodeIsOpened()) + { + LOG_MSG_ERROR("HeaderInsertion block is not ready " + "for immediate commands!\n"); + return false; + } + + if (!m_routing.DeviceNodeIsOpened()) + { + LOG_MSG_ERROR("Routing block is not ready " + "for immediate commands!\n"); + return false; + } + + if (!m_filtering.DeviceNodeIsOpened()) + { + LOG_MSG_ERROR("Filtering block is not ready " + "for immediate commands!\n"); + return false; + } + + // resetting this component will reset + // both Routing and Filtering tables + m_headerInsertion.Reset(); + + return true; +} // Setup() + +bool IpaHdrProcCtxTestFixture::Teardown() +{ + m_rndisEth2Producer.Close(); + m_wlanEth2producer.Close(); + m_eth2Producer.Close(); + m_defaultConsumer.Close(); + m_rndisEth2Consumer.Close(); + return true; +} // Teardown() + +void IpaHdrProcCtxTestFixture::AddAllHeaders() +{ + for (int i = 0; i < HEADER_HANDLE_ID_MAX; i++) { + AddHeader(static_cast(i)); + } +} + +// Insert a single header +void IpaHdrProcCtxTestFixture::AddHeader(HeaderHandleId handleId) +{ + static const int NUM_OF_HEADERS = 1; + struct ipa_ioc_add_hdr *hdrTable = NULL; + struct ipa_hdr_add *hdr = NULL; + + // init hdr table + hdrTable = (struct ipa_ioc_add_hdr *) calloc(1, + sizeof(struct ipa_ioc_add_hdr) + + NUM_OF_HEADERS * sizeof(struct ipa_hdr_add)); + if (!hdrTable) + { + LOG_MSG_ERROR( + "calloc failed to allocate pHeaderDescriptor"); + return; + } + hdrTable->commit = true; + hdrTable->num_hdrs = NUM_OF_HEADERS; + + // init the hdr common fields + hdr = &hdrTable->hdr[0]; + hdr->hdr_hdl = -1; //Return Value + hdr->is_partial = false; + hdr->status = -1; // Return Parameter + + // init hdr specific fields + switch (handleId) + { + case HEADER_HANDLE_ID_WLAN_ETH2: + memcpy(hdr->hdr, WLAN_ETH2_HDR, WLAN_ETH2_HDR_SIZE); + hdr->hdr_len = WLAN_ETH2_HDR_SIZE; + + strlcpy(hdr->name, "WLAN_ETH2", sizeof(hdr->name)); + hdr->type = IPA_HDR_L2_ETHERNET_II; + break; + + case HEADER_HANDLE_ID_RNDIS_ETH2: + if (!RNDISAggregationHelper::LoadRNDISEth2IP4Header( + hdr->hdr, + IPA_HDR_MAX_SIZE, + 0, + (size_t*)&hdr->hdr_len)) + return; + + strlcpy(hdr->name, "RNDIS_ETH2", sizeof(hdr->name)); + hdr->type = IPA_HDR_L2_ETHERNET_II; + break; + + case HEADER_HANDLE_ID_ETH2: + strlcpy(hdr->name, "ETH2", sizeof(hdr->name)); + memcpy(hdr->hdr, ETH2_HDR, ETH_HLEN); + hdr->type = IPA_HDR_L2_ETHERNET_II; + hdr->hdr_len = ETH_HLEN; + + break; + + case HEADER_HANDLE_ID_WLAN_802_3: + strlcpy(hdr->name, "WLAN_802_3", sizeof(hdr->name)); + memcpy(hdr->hdr, WLAN_802_3_HDR, WLAN_802_3_HDR_SIZE); + hdr->type = IPA_HDR_L2_802_3; + hdr->hdr_len = WLAN_802_3_HDR_SIZE; + + LOG_MSG_DEBUG( + "HEADER_HANDLE_ID_WLAN_802_3 NOT supported for now"); + return; + + break; + case HEADER_HANDLE_ID_VLAN_802_1Q: + strlcpy(hdr->name, "VLAN_8021Q", sizeof(hdr->name)); + memcpy(hdr->hdr, ETH2_8021Q_HDR, ETH8021Q_HEADER_LEN); + hdr->type = IPA_HDR_L2_802_1Q; + hdr->hdr_len = ETH8021Q_HEADER_LEN; + break; + + default: + LOG_MSG_ERROR("header handleId not supported."); + return; + } + + // commit header to HW + if (!m_headerInsertion.AddHeader(hdrTable)) + { + LOG_MSG_ERROR("m_headerInsertion.AddHeader() failed."); + return; + } + + // save header handle + m_headerHandles[handleId] = hdr->hdr_hdl; +} + +void IpaHdrProcCtxTestFixture::AddAllProcCtx() +{ + for (int i = 0; i (i)); + } +} + +// Insert a single proc_ctx +void IpaHdrProcCtxTestFixture::AddProcCtx(ProcCtxHandleId handleId) +{ + static const int NUM_OF_PROC_CTX = 1; + struct ipa_ioc_add_hdr_proc_ctx *procCtxTable = NULL; + struct ipa_hdr_proc_ctx_add *procCtx = NULL; + + // init proc ctx table + procCtxTable = (struct ipa_ioc_add_hdr_proc_ctx *)calloc(1, + sizeof(struct ipa_ioc_add_hdr_proc_ctx) + + NUM_OF_PROC_CTX * + sizeof(struct ipa_hdr_proc_ctx_add)); + if (!procCtxTable) + { + LOG_MSG_ERROR("calloc failed to allocate procCtxTable"); + return; + } + + procCtxTable->commit = true; + procCtxTable->num_proc_ctxs = NUM_OF_PROC_CTX; + + // init proc_ctx common fields + procCtx = &procCtxTable->proc_ctx[0]; + procCtx->proc_ctx_hdl = -1; // return value + procCtx->status = -1; // Return parameter + + // init proc_ctx specific fields + switch (handleId) + { + case PROC_CTX_HANDLE_ID_ETH2_2_WLAN_ETH2: + procCtx->type = IPA_HDR_PROC_ETHII_TO_ETHII; + procCtx->hdr_hdl = + m_headerHandles[HEADER_HANDLE_ID_WLAN_ETH2]; + break; + + case PROC_CTX_HANDLE_ID_ETH2_2_RNDIS_ETH2: + procCtx->type = IPA_HDR_PROC_ETHII_TO_ETHII; + procCtx->hdr_hdl = + m_headerHandles[HEADER_HANDLE_ID_RNDIS_ETH2]; + break; + + case PROC_CTX_HANDLE_ID_ETH2_ETH2_2_ETH2: + procCtx->type = IPA_HDR_PROC_ETHII_TO_ETHII; + procCtx->hdr_hdl = + m_headerHandles[HEADER_HANDLE_ID_ETH2]; + break; + + case PROC_CTX_HANDLE_ID_WLAN_ETH2_2_802_3: + procCtx->type = IPA_HDR_PROC_ETHII_TO_802_3; + procCtx->hdr_hdl = + m_headerHandles[HEADER_HANDLE_ID_WLAN_802_3]; + break; + + case PROC_CTX_HANDLE_ID_RNDIS_802_3_2_ETH2: + procCtx->type = IPA_HDR_PROC_802_3_TO_ETHII; + procCtx->hdr_hdl = + m_headerHandles[HEADER_HANDLE_ID_RNDIS_ETH2]; + break; + + case PROC_CTX_HANDLE_ID_WLAN_802_3_2_ETH2: + procCtx->type = IPA_HDR_PROC_802_3_TO_802_3; + procCtx->hdr_hdl = + m_headerHandles[HEADER_HANDLE_ID_WLAN_802_3]; + break; + case PROC_CTX_HANDLE_ID_802_1Q_2_802_1Q: + procCtx->type = IPA_HDR_PROC_ETHII_TO_ETHII_EX; + procCtx->hdr_hdl = + m_headerHandles[HEADER_HANDLE_ID_VLAN_802_1Q]; + procCtx->generic_params.input_ethhdr_negative_offset = 18; + procCtx->generic_params.output_ethhdr_negative_offset = 18; + break; + case PROC_CTX_HANDLE_ID_802_1Q_2_ETH2: + procCtx->type = IPA_HDR_PROC_ETHII_TO_ETHII_EX; + procCtx->hdr_hdl = + m_headerHandles[HEADER_HANDLE_ID_ETH2]; + procCtx->generic_params.input_ethhdr_negative_offset = 18; + procCtx->generic_params.output_ethhdr_negative_offset = 14; + break; + case PROC_CTX_HANDLE_ID_ETH2_2_802_1Q: + procCtx->type = IPA_HDR_PROC_ETHII_TO_ETHII_EX; + procCtx->hdr_hdl = + m_headerHandles[HEADER_HANDLE_ID_VLAN_802_1Q]; + procCtx->generic_params.input_ethhdr_negative_offset = 14; + procCtx->generic_params.output_ethhdr_negative_offset = 18; + break; + case PROC_CTX_HANDLE_ID_ETH2_ETH2_2_ETH2_EX: + procCtx->type = IPA_HDR_PROC_ETHII_TO_ETHII_EX; + procCtx->hdr_hdl = + m_headerHandles[HEADER_HANDLE_ID_ETH2]; + procCtx->generic_params.input_ethhdr_negative_offset = 14; + procCtx->generic_params.output_ethhdr_negative_offset = 14; + break; + + default: + LOG_MSG_ERROR("proc ctx handleId %d not supported.", handleId); + return; + } + + if (!m_headerInsertion.AddProcCtx(procCtxTable)) + { + LOG_MSG_ERROR("m_headerInsertion.AddProcCtx(procCtxTable) failed."); + return; + } + + // save proc_ctx handle + m_procCtxHHandles[handleId] = procCtx->proc_ctx_hdl; +} + +void IpaHdrProcCtxTestFixture::AddRtBypassRule(uint32_t hdrHdl, uint32_t procCtxHdl) +{ + static const char bypass0[] = "bypass0"; + struct ipa_ioc_get_rt_tbl routing_table0; + + if (!CreateIPv4BypassRoutingTable ( + bypass0, + hdrHdl, + procCtxHdl)) + { + LOG_MSG_ERROR("CreateIPv4BypassRoutingTable Failed\n"); + return; + } + + routing_table0.ip = IPA_IP_v4; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + LOG_MSG_ERROR("m_routing.GetRoutingTable() Failed."); + return; + } + + m_routingTableHdl = routing_table0.hdl; +} + +void IpaHdrProcCtxTestFixture::AddFltBypassRule() +{ + IPAFilteringTable FilterTable0; + struct ipa_flt_rule_add flt_rule_entry; + + FilterTable0.Init(IPA_IP_v4,m_currProducerClient,false,1); + printf("FilterTable*.Init Completed Successfully..\n"); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1,flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl=-1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action=IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.rt_tbl_hdl=m_routingTableHdl; + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + flt_rule_entry.rule.attrib.u.v4.dst_addr_mask = 0x00000000; // Mask - Bypass rule + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0x12345678; // Filter is irrelevant. + if (((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule( + FilterTable0.GetFilteringTable())) + { + LOG_MSG_ERROR( + "%s::m_filtering.AddFilteringRule() failed", + __FUNCTION__); + return; + } + else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", + FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl, + FilterTable0.ReadRuleFromTable(0)->status); + } +} + +bool IpaHdrProcCtxTestFixture::ReceivePacketsAndCompare() +{ + size_t receivedBufferSize1 = 0; + bool isSuccess = true; + + // Receive results + Byte *receivedBuffer1 = new Byte[m_BUFF_MAX_SIZE]; + + if (NULL == receivedBuffer1) + { + printf("Memory allocation error.\n"); + return false; + } + + receivedBufferSize1 = m_pCurrentConsumer->ReceiveData( + receivedBuffer1, + m_BUFF_MAX_SIZE); + printf("Received %zu bytes on %s.\n", + receivedBufferSize1, + m_pCurrentConsumer->m_fromChannelName.c_str()); + + // Compare results + if (!CompareResultVsGolden( + m_expectedBuffer1, + m_expectedBufferSize1, + receivedBuffer1, + receivedBufferSize1)) + { + printf("Comparison of Buffer Failed!\n"); + isSuccess = false; + } + + printf("Expected buffer 1 - %zu bytes\n", m_expectedBufferSize1); + print_buff(m_expectedBuffer1, m_expectedBufferSize1); + + printf("Received buffer 1 - %zu bytes\n", receivedBufferSize1); + print_buff(receivedBuffer1, receivedBufferSize1); + + delete[] receivedBuffer1; + + return isSuccess; +} + +// Create 1 IPv4 bypass routing entry and commits it +bool IpaHdrProcCtxTestFixture::CreateIPv4BypassRoutingTable ( + const char *name, + uint32_t hdrHdl, + uint32_t procCtxHdl) +{ + printf("Entering %s, %s()\n",__FUNCTION__, __FILE__); + struct ipa_ioc_add_rt_rule *rt_table = 0; + struct ipa_rt_rule_add *rt_rule_entry = NULL; + + // Verify that only one is nonzero + if ((hdrHdl == 0 && procCtxHdl == 0) || + (hdrHdl != 0 && procCtxHdl != 0)) + { + LOG_MSG_ERROR("Error: hdrHdl = %u, procCtxHdl = %u\n"); + return false; + } + + rt_table = (struct ipa_ioc_add_rt_rule *) + calloc(1, sizeof(struct ipa_ioc_add_rt_rule) + + 1*sizeof(struct ipa_rt_rule_add)); + if(!rt_table) { + LOG_MSG_ERROR("calloc failed to allocate rt_table\n"); + return false; + } + + rt_table->num_rules = 1; + rt_table->ip = IPA_IP_v4; + rt_table->commit = true; + strlcpy(rt_table->rt_tbl_name, name, sizeof(rt_table->rt_tbl_name)); + + rt_rule_entry = &rt_table->rules[0]; + rt_rule_entry->at_rear = 0; + rt_rule_entry->rule.dst = m_currConsumerPipeNum; + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v4.dst_addr = 0xaabbccdd; + + // All Packets will get a "Hit" + rt_rule_entry->rule.attrib.u.v4.dst_addr_mask = 0x00000000; + rt_rule_entry->rule.hdr_hdl = hdrHdl; + rt_rule_entry->rule.hdr_proc_ctx_hdl = procCtxHdl; + if (false == m_routing.AddRoutingRule(rt_table)) + { + printf("Routing rule addition(rt_table) failed!\n"); + Free (rt_table); + return false; + } + + Free (rt_table); + printf("Leaving %s, %s()\n",__FUNCTION__, __FILE__); + return true; +} + +bool IpaHdrProcCtxTestFixture::AddRules() +{ + printf("Entering %s, %s()\n",__FUNCTION__, __FILE__); + + if (m_procCtxHandleId == PROC_CTX_HANDLE_ID_MAX) + { + LOG_MSG_ERROR("Test developer didn't implement " + "AddRules() or didn't set m_procCtxHandleId"); + return false; + } + + AddAllHeaders(); + + AddAllProcCtx(); + + AddRtBypassRule(0, m_procCtxHHandles[m_procCtxHandleId]); + + AddFltBypassRule(); + + printf("Leaving %s, %s()\n",__FUNCTION__, __FILE__); + return true; + +}// AddRules() + +bool IpaHdrProcCtxTestFixture::SendPackets() +{ + + bool isSuccess = false; + + // Send first packet + isSuccess = m_pCurrentProducer->SendData( + m_sendBuffer1, + m_sendSize1); + if (false == isSuccess) + { + LOG_MSG_ERROR("SendPackets Buffer1 failed on client %d\n", m_currProducerClient); + return false; + } + + return true; +} + +bool IpaHdrProcCtxTestFixture::Run() +{ + bool res = false; + bool isSuccess = false; + + printf("Entering %s, %s()\n",__FUNCTION__, __FILE__); + + res = AddRules(); + if (false == res) { + printf("Failed adding filtering rules.\n"); + return false; + } + + // Load input data - IP packets + res = LoadPackets(m_IpaIPType); + if (false == res) { + printf("Failed loading packets.\n"); + return false; + } + + res = GenerateExpectedPackets(); + if (false == res) { + printf("GenerateExpectedPackets failed\n"); + return false; + } + + res = SendPackets(); + if (false == res) { + printf("SendPackets failed\n"); + return false; + } + + // Receive packets from the channels and compare results + isSuccess = ReceivePacketsAndCompare(); + + printf("Leaving %s, %s(), Returning %d\n", + __FUNCTION__, + __FILE__, + isSuccess); + + return isSuccess; +} // Run() + +IpaHdrProcCtxTestFixture::~IpaHdrProcCtxTestFixture() +{ + m_sendSize1 = 0; +} + +RoutingDriverWrapper IpaHdrProcCtxTestFixture::m_routing; +Filtering IpaHdrProcCtxTestFixture::m_filtering; +HeaderInsertion IpaHdrProcCtxTestFixture::m_headerInsertion; + diff --git a/qcom/opensource/dataipa/kernel-tests/HeaderProcessingContextTestFixture.h b/qcom/opensource/dataipa/kernel-tests/HeaderProcessingContextTestFixture.h new file mode 100644 index 0000000000..1667b8cd99 --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/HeaderProcessingContextTestFixture.h @@ -0,0 +1,218 @@ +/* + * Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include // for memcpy +#include "hton.h" // for htonl +#include "InterfaceAbstraction.h" +#include "Constants.h" +#include "Logger.h" +#include "TestsUtils.h" +#include "Filtering.h" +#include "HeaderInsertion.h" +#include "RoutingDriverWrapper.h" +#include "IPAFilteringTable.h" + +/* +Processing context test design: + +1. 1 Producer with RNDIS de-aggregation and ETH2 header removal. +2. 1 Producer with WLAN and ETH2 header removal. +3. 1 default consumer. +4. 1 RNDIS aggregation consumer. +5. 1 FLT rule – accept all - points to 1 RT rule. +6. 1 RT rule – accept all - points to specific test relevant proc_ctx. +7. All tests add all proc_ctx (for all tests). +8. Proc_ctx to be added: 1 for each test – 3 altogether. + Proc_ctx of test 01 and 03 are the same. +9. Each test will send 1 packet and check that the packet is good + except test 03. +10. Test 03 the same as Test 01 but will send multiple packets + and expect 1 (RNDIS aggregation test). + +List of tests: +00. Header insertion scenario of [RNDIS][ETH_II][IP] -> [WLAN][ETH_II][IP] +01. Header insertion scenario of [WLAN][ETH_II][IP] -> [RNDIS][ETH_II][IP] +02. Header insertion scenario of [WLAN][ETH_II][IP] -> [WLAN’][ETH_II][IP] +03. Header insertion of [WLAN][ETH_II][IP] -> [RNDIS][ETH_II][IP] + with RNDIS aggregation. +04. Header insertion scenario when adding total header sizes > 2048 +05. Header insertion scenario of [ETH_II][IP] -> [WLAN][ETH_II][IP] +06. Header insertion scenario of [WLAN][ETH_II][IP] -> [ETH_II][IP +07. Header insertion scenario of [ETH_II][IP] -> [ETH_II][IP] +08. Header insertion scenario of [RNDIS][ETH_II][IP] -> [WLAN][802.3][IP] +09. Header insertion scenario of [WLAN][802.3][IP] -> [RNDIS][ETH_II][IP] +10. Header insertion scenario of [ETH_II][IP] -> [WLAN][802.3][IP] +11. Header insertion scenario of [WLAN][802.3][IP] -> [WLAN’][802.3][IP] +*/ +class IpaHdrProcCtxTestFixture : public TestBase +{ +public: + enum HeaderHandleId + { + HEADER_HANDLE_ID_WLAN_ETH2, + HEADER_HANDLE_ID_RNDIS_ETH2, + HEADER_HANDLE_ID_ETH2, + HEADER_HANDLE_ID_WLAN_802_3, + HEADER_HANDLE_ID_VLAN_802_1Q, + HEADER_HANDLE_ID_MAX + }; + + enum ProcCtxHandleId + { + PROC_CTX_HANDLE_ID_ETH2_2_WLAN_ETH2, + PROC_CTX_HANDLE_ID_ETH2_2_RNDIS_ETH2, + PROC_CTX_HANDLE_ID_ETH2_ETH2_2_ETH2, + PROC_CTX_HANDLE_ID_WLAN_ETH2_2_802_3, + PROC_CTX_HANDLE_ID_RNDIS_802_3_2_ETH2, + PROC_CTX_HANDLE_ID_WLAN_802_3_2_ETH2, + PROC_CTX_HANDLE_ID_802_1Q_2_802_1Q, + PROC_CTX_HANDLE_ID_ETH2_2_802_1Q, + PROC_CTX_HANDLE_ID_802_1Q_2_ETH2, + PROC_CTX_HANDLE_ID_ETH2_ETH2_2_ETH2_EX, + PROC_CTX_HANDLE_ID_MAX + }; + + // header table consist of 9 bits and 4B units -> 2048 + static const int m_ALL_HEADER_SIZE_LIMIT = 2048; + + static const size_t m_BUFF_MAX_SIZE = + 2 * RNDISAggregationHelper::RNDIS_AGGREGATION_BYTE_LIMIT; + + // [WLAN][ETH2] header + static const Byte WLAN_ETH2_HDR[WLAN_ETH2_HDR_SIZE]; + + // [ETH2] header + static const Byte ETH2_HDR[ETH_HLEN]; + + // [ETH2_802_1Q] vlan header + static const Byte ETH2_8021Q_HDR[ETH8021Q_HEADER_LEN]; + + // [WLAN][802.3] header + static const Byte WLAN_802_3_HDR[WLAN_802_3_HDR_SIZE]; + + static Filtering m_filtering; + static RoutingDriverWrapper m_routing; + static HeaderInsertion m_headerInsertion; + + // For each header type the handle is saved + // to be used by the processing context + uint32_t m_headerHandles[HEADER_HANDLE_ID_MAX]; + + // For each prco_ctx type the handle is saved + // to be used by the routing rule + uint32_t m_procCtxHHandles[PROC_CTX_HANDLE_ID_MAX]; + + // proc_ctx handle ID + ProcCtxHandleId m_procCtxHandleId; + + // routing table handle + uint32_t m_routingTableHdl; + + // Pipe with RNDIS and ETH2 header removal + InterfaceAbstraction m_rndisEth2Producer; + + // Pipe with WLAN and ETH2 header removal + InterfaceAbstraction m_wlanEth2producer; + + // Pipe with ETH2 header removal + InterfaceAbstraction m_eth2Producer; + + // TODO: Pipe with WLAN and 802.3 header removal + InterfaceAbstraction m_wlan802_3producer; + + // Pointer to current producer pipe used in the test + InterfaceAbstraction *m_pCurrentProducer; + ipa_client_type m_currProducerClient; + + // Pipe of the WLAN ETH2 consumer + InterfaceAbstraction m_defaultConsumer; + + // Pipe of the RNDIS ETH2 consumer + InterfaceAbstraction m_rndisEth2Consumer; + + // Pointer to current consumer pipe used in the test + InterfaceAbstraction *m_pCurrentConsumer; + ipa_client_type m_currConsumerPipeNum; + + // First input packet + Byte m_sendBuffer1[m_BUFF_MAX_SIZE]; + size_t m_sendSize1; + + // Second input packet + Byte m_sendBuffer2[m_BUFF_MAX_SIZE]; + size_t m_sendSize2; + + // First expected packet + Byte m_expectedBuffer1[m_BUFF_MAX_SIZE]; + size_t m_expectedBufferSize1; + + enum ipa_ip_type m_IpaIPType; + + IpaHdrProcCtxTestFixture(); + + virtual bool Setup(); + virtual bool Teardown(); + virtual void AddAllHeaders(); + + // Insert a single header + virtual void AddHeader(HeaderHandleId handleId); + virtual void AddAllProcCtx(); + + // Insert a single proc_ctx + virtual void AddProcCtx(ProcCtxHandleId handleId); + virtual void AddRtBypassRule(uint32_t hdrHdl, uint32_t procCtxHdl); + virtual void AddFltBypassRule(); + virtual bool LoadPackets(enum ipa_ip_type ip) = 0; + + virtual bool ReceivePacketsAndCompare(); + + // Create 1 IPv4 bypass routing entry and commits it + virtual bool CreateIPv4BypassRoutingTable ( + const char *name, + uint32_t hdrHdl, + uint32_t procCtxHdl); + + virtual bool GenerateExpectedPackets() = 0; + + virtual bool AddRules(); + + virtual bool SendPackets(); + + virtual bool Run(); + + ~IpaHdrProcCtxTestFixture(); + +private: +}; + diff --git a/qcom/opensource/dataipa/kernel-tests/HeaderProcessingContextTests.cpp b/qcom/opensource/dataipa/kernel-tests/HeaderProcessingContextTests.cpp new file mode 100644 index 0000000000..bfed1b99e5 --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/HeaderProcessingContextTests.cpp @@ -0,0 +1,780 @@ +/* + * Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "HeaderProcessingContextTestFixture.h" + +/*----------------------------------------------------------------------------*/ +/* Test00: Header insertion scenario of [RNDIS][ETH_II][IP] -> */ +/* [WLAN][ETH_II][IP] */ +/*----------------------------------------------------------------------------*/ +class IpaHdrProcCtxTest00 : public IpaHdrProcCtxTestFixture +{ +public: + IpaHdrProcCtxTest00() + { + m_name = "IpaHdrProcCtxTest00"; + m_description = + "Processing Context test 00 - \ + of [RNDIS][ETH_II][IP] -> [WLAN][ETH_II][IP] \ + 1. Generate and commit all headers for all tests. \ + 2. Generate and commit all processing context rules \ + for all tests.\ + 3. Generate and commit routing table 0. \ + The table contains 1 \"bypass\" rule. \ + All data goes to output pipe TEST2. \ + Routing rule will use processing context ETH2_2_WLAN_ETH2 \ + 4. Generate and commit 1 filtering rule. \ + All traffic goes to routing table 0"; + m_pCurrentProducer = &m_rndisEth2Producer; + m_currProducerClient = IPA_CLIENT_TEST_PROD; + m_pCurrentConsumer = &m_defaultConsumer; + m_currConsumerPipeNum = IPA_CLIENT_TEST2_CONS; + m_procCtxHandleId = PROC_CTX_HANDLE_ID_ETH2_2_WLAN_ETH2; + m_minIPAHwType = IPA_HW_v2_5; + m_maxIPAHwType = IPA_HW_MAX; + m_runInRegression = false; + Register(*this); + } + + virtual bool LoadPackets(enum ipa_ip_type ip) + { + if (!RNDISAggregationHelper::LoadRNDISPacket( + ip, + m_sendBuffer1, + m_sendSize1)) + { + LOG_MSG_ERROR("Failed default Packet\n"); + return false; + } + printf ("Loaded %zu Bytes to Packet 1\n",m_sendSize1); + + add_buff(m_sendBuffer1+RNDIS_HDR_SIZE, ETH_HLEN, 2); + print_buff(m_sendBuffer1, m_sendSize1); + + return true; + } + + virtual bool GenerateExpectedPackets() + { + m_expectedBufferSize1 = WLAN_ETH2_HDR_SIZE + + IP4_PACKET_SIZE; + + // copy WLAN header to the beginning of the buffer + memcpy(m_expectedBuffer1, WLAN_ETH2_HDR, WLAN_HDR_SIZE); + + // copy ETH+IP packet right after WLAN header + memcpy(m_expectedBuffer1 + WLAN_HDR_SIZE, + m_sendBuffer1 + RNDIS_HDR_SIZE, + ETH_HLEN + IP4_PACKET_SIZE); + + return true; + } // GenerateExpectedPackets() +}; + +/*----------------------------------------------------------------------------*/ +/* Test01: Header insertion scenario of [WLAN][ETH_II][IP] -> */ +/* [RNDIS][ETH_II][IP] */ +/*----------------------------------------------------------------------------*/ +class IpaHdrProcCtxTest01 : public IpaHdrProcCtxTestFixture +{ +public: + IpaHdrProcCtxTest01() + { + m_name = "IpaHdrProcCtxTest01"; + m_description = + "Processing context test 01 - \ + of [WLAN][ETH_II][IP] -> [RNDIS][ETH_II][IP] \ + 1. Generate and commit all headers for all tests. \ + 2. Generate and commit all processing context rules \ + for all tests.\ + 3. Generate and commit routing table 0. \ + The table contains 1 \"bypass\" rule. \ + All data goes to output pipe TEST3. \ + Routing rule will use processing context ETH2_2_RNDIS_ETH2 \ + 4. Generate and commit 1 filtering rule. \ + All traffic goes to routing table 0"; + m_pCurrentProducer = &m_wlanEth2producer; + m_currProducerClient = IPA_CLIENT_TEST2_PROD; + m_pCurrentConsumer = &m_rndisEth2Consumer; + m_currConsumerPipeNum = IPA_CLIENT_TEST3_CONS; + m_procCtxHandleId = PROC_CTX_HANDLE_ID_ETH2_2_RNDIS_ETH2; + m_minIPAHwType = IPA_HW_v2_5; + m_maxIPAHwType = IPA_HW_MAX; + m_runInRegression = false; + Register(*this); + } + + virtual bool LoadPackets(enum ipa_ip_type ip) + { + // load WLAN ETH2 IP4 packet of size 1kB + 1 byte + // This size will trigger RNDIS aggregation later + m_sendSize1 = + RNDISAggregationHelper::RNDIS_AGGREGATION_BYTE_LIMIT + 1; + + if (!WlanHelper::LoadWlanEth2IP4PacketByLength( + m_sendBuffer1, + m_BUFF_MAX_SIZE, + m_sendSize1, + 0x01)) + return false; + + printf ("Loaded %zu Bytes to Packet 1\n",m_sendSize1); + + add_buff(m_sendBuffer1+WLAN_HDR_SIZE, ETH_HLEN, 3); + + print_buff(m_sendBuffer1, m_sendSize1); + + return true; + } + + virtual bool GenerateExpectedPackets() + { + size_t len = 0; + size_t eth2PacketSize = m_sendSize1 - WLAN_HDR_SIZE; + + m_expectedBufferSize1 = eth2PacketSize + RNDIS_HDR_SIZE; + + // copy RNDIS header + if (!RNDISAggregationHelper::LoadRNDISHeader( + m_expectedBuffer1, + m_BUFF_MAX_SIZE, + m_expectedBufferSize1, + &len)) + { + LOG_MSG_ERROR("Failed default Packet\n"); + return false; + } + + // copy ETH2 packet after RNDIS header + memcpy(m_expectedBuffer1 + len, + m_sendBuffer1 + WLAN_HDR_SIZE, + eth2PacketSize); + + return true; + } // GenerateExpectedPackets() +}; + +/*----------------------------------------------------------------------------*/ +/* Test02: Header insertion scenario of [WLAN][ETH_II][IP] -> */ +/* [WLAN'][ETH_II][IP] */ +/*----------------------------------------------------------------------------*/ +class IpaHdrProcCtxTest02 : public IpaHdrProcCtxTestFixture +{ +public: + IpaHdrProcCtxTest02() + { + m_name = "IpaHdrProcCtxTest02"; + m_description = + "Processing context test 02 - \ + of [WLAN][ETH_II][IP] -> [WLAN'][ETH_II][IP] \ + 1. Generate and commit all headers for all tests. \ + 2. Generate and commit all processing context rules \ + for all tests.\ + 3. Generate and commit routing table 0. \ + The table contains 1 \"bypass\" rule. \ + All data goes to output pipe TEST2. \ + Routing rule will use processing context ETH2_2_WLAN_ETH2 \ + 4. Generate and commit 1 filtering rule. \ + All traffic goes to routing table 0"; + m_pCurrentProducer = &m_wlanEth2producer; + m_currProducerClient = IPA_CLIENT_TEST2_PROD; + m_pCurrentConsumer = &m_defaultConsumer; + m_currConsumerPipeNum = IPA_CLIENT_TEST2_CONS; + m_procCtxHandleId = PROC_CTX_HANDLE_ID_ETH2_2_WLAN_ETH2; + m_minIPAHwType = IPA_HW_v2_5; + m_maxIPAHwType = IPA_HW_MAX; + m_runInRegression = false; + Register(*this); + } + + virtual bool LoadPackets(enum ipa_ip_type ip) + { + // load WLAN ETH2 IP4 packet of size 1kB + // This size will trigger RNDIS aggregation later + if (!WlanHelper::LoadWlanEth2IP4Packet( + m_sendBuffer1, + m_BUFF_MAX_SIZE, + &m_sendSize1)) + return false; + + printf ("Loaded %zu Bytes to Packet 1\n",m_sendSize1); + + add_buff(m_sendBuffer1+WLAN_HDR_SIZE, ETH_HLEN, 5); + + return true; + } + + virtual bool GenerateExpectedPackets() + { + m_expectedBufferSize1 = m_sendSize1; + memcpy(m_expectedBuffer1, m_sendBuffer1, m_expectedBufferSize1); + memcpy(m_expectedBuffer1, WLAN_ETH2_HDR, WLAN_HDR_SIZE); + + return true; + } // GenerateExpectedPackets() +}; + +/*----------------------------------------------------------------------------*/ +/* Test03: Header insertion scenario of [WLAN][ETH_II][IP] -> */ +/* [RNDIS][ETH_II][IP] with RNDIS aggregation */ +/*----------------------------------------------------------------------------*/ +class IpaHdrProcCtxTest03 : public IpaHdrProcCtxTestFixture +{ +public: + IpaHdrProcCtxTest03() + { + m_name = "IpaHdrProcCtxTest03"; + m_description = + "Processing Context test 03 - \ + of [RNDIS][ETH_II][IP] -> [WLAN][ETH_II][IP] \ + with RNDIS aggregation \ + 1. Generate and commit all headers for all tests. \ + 2. Generate and commit all processing context rules \ + for all tests.\ + 3. Generate and commit routing table 0. \ + The table contains 1 \"bypass\" rule. \ + All data goes to output pipe TEST3. \ + Routing rule will use processing context ETH2_2_RNDIS_ETH2 \ + 4. Generate and commit 1 filtering rule. \ + All traffic goes to routing table 0"; + m_pCurrentProducer = &m_wlanEth2producer; + m_currProducerClient = IPA_CLIENT_TEST2_PROD; + m_pCurrentConsumer = &m_rndisEth2Consumer; + m_currConsumerPipeNum = IPA_CLIENT_TEST3_CONS; + m_procCtxHandleId = PROC_CTX_HANDLE_ID_ETH2_2_RNDIS_ETH2; + m_minIPAHwType = IPA_HW_v2_5; + m_maxIPAHwType = IPA_HW_MAX; + m_runInRegression = false; + Register(*this); + } + + virtual bool LoadPackets(enum ipa_ip_type ip) + { + // choose this size so that 2 such buffers would be aggregated + m_sendSize1 = RNDISAggregationHelper:: + RNDIS_AGGREGATION_BYTE_LIMIT / 2 + 200; + + if (!WlanHelper::LoadWlanEth2IP4PacketByLength( + m_sendBuffer1, + m_BUFF_MAX_SIZE, + m_sendSize1, + 1)) + return false; + + printf ("Loaded %zu Bytes to Packet 1\n", m_sendSize1); + + add_buff(m_sendBuffer1+WLAN_HDR_SIZE, ETH_HLEN, 7); + + // choose this size so that 2 such buffers would be aggregated + m_sendSize2 = RNDISAggregationHelper:: + RNDIS_AGGREGATION_BYTE_LIMIT / 2 + 200; + + if (!WlanHelper::LoadWlanEth2IP4PacketByLength( + m_sendBuffer2, + m_BUFF_MAX_SIZE, + m_sendSize2, + 2)) + return false; + + printf ("Loaded %zu Bytes to Packet 2\n", m_sendSize2); + + add_buff(m_sendBuffer2+WLAN_HDR_SIZE, ETH_HLEN, 11); + + return true; + } + + virtual bool SendPackets() + { + bool isSuccess = false; + + // Send packet 1 + isSuccess = m_pCurrentProducer->SendData( + m_sendBuffer1, + m_sendSize1); + if (false == isSuccess) + { + LOG_MSG_ERROR( + "SendData Buffer 1 failed on producer %d\n", m_currProducerClient); + return false; + } + + // Send packet 2 + isSuccess = m_pCurrentProducer->SendData( + m_sendBuffer2, + m_sendSize2); + if (false == isSuccess) + { + LOG_MSG_ERROR( + "SendData Buffer 2 failed on producer %d\n", m_currProducerClient); + return false; + } + + return true; + } + + virtual bool GenerateExpectedPackets() + { + size_t len = 0; + size_t eth2PacketSize1 = m_sendSize1 - WLAN_HDR_SIZE; + size_t rndisPacketSize1 = eth2PacketSize1 + RNDIS_HDR_SIZE; + size_t eth2PacketSize2 = m_sendSize2 - WLAN_HDR_SIZE; + size_t rndisPacketSize2 = eth2PacketSize2 + RNDIS_HDR_SIZE; + Byte *currBuffLocation = NULL; + + m_expectedBufferSize1 = rndisPacketSize1 + rndisPacketSize2; + + currBuffLocation = m_expectedBuffer1; + + // copy first RNDIS header + if (!RNDISAggregationHelper::LoadRNDISHeader( + currBuffLocation, + m_BUFF_MAX_SIZE, + rndisPacketSize1, + &len)) + return false; + + // copy ETH2 packet 1 after RNDIS header + currBuffLocation += len; + memcpy(currBuffLocation, + m_sendBuffer1 + WLAN_HDR_SIZE, + eth2PacketSize1); + + // copy second RNDIS header + currBuffLocation += eth2PacketSize1; + if (!RNDISAggregationHelper::LoadRNDISHeader( + currBuffLocation, + m_BUFF_MAX_SIZE - rndisPacketSize1, + rndisPacketSize2, + &len)) + return false; + + // copy ETH2 packet 2 after RNDIS header + currBuffLocation += len; + memcpy(currBuffLocation, + m_sendBuffer2 + WLAN_HDR_SIZE, + eth2PacketSize2); + + return true; + } // GenerateExpectedPackets() +}; + + +/*----------------------------------------------------------------------------*/ +/* Test04: Header insertion scenario when adding total header sizes > 2048 */ +/*----------------------------------------------------------------------------*/ +class IpaHdrProcCtxTest04 : public IpaHdrProcCtxTestFixture +{ +public: + IpaHdrProcCtxTest04() + { + m_name = "IpaHdrProcCtxTest04"; + m_description = + "Processing context test 04 - \ + Header insertion scenario when adding \ + total header sizes > 2048 \ + 1. Generate and commit all headers for all tests. \ + 2. Generate and commit all processing context rules \ + for all tests.\ + 3. Generate and commit routing table 0. \ + The table contains 1 \"bypass\" rule. \ + All data goes to output pipe TEST2. \ + Routing rule will use header WLAN_ETH2 \ + 4. Generate and commit 1 filtering rule. \ + All traffic goes to routing table 0"; + m_pCurrentProducer = &m_wlanEth2producer; + m_currProducerClient = IPA_CLIENT_TEST2_PROD; + m_pCurrentConsumer = &m_defaultConsumer; + m_currConsumerPipeNum = IPA_CLIENT_TEST2_CONS; + m_minIPAHwType = IPA_HW_v2_5; + m_maxIPAHwType = IPA_HW_MAX; + m_runInRegression = false; + Register(*this); + } + + virtual void AddAllHeaders() + { + int cnt = 0; + int allHeadersSize = 0; + + while (allHeadersSize <= m_ALL_HEADER_SIZE_LIMIT) + { + AddHeader(HEADER_HANDLE_ID_ETH2); + /* header bins are power of 2 */ + allHeadersSize += ETH_HLEN + 2; + cnt++; + } + + AddHeader(HEADER_HANDLE_ID_WLAN_ETH2); + } + + virtual bool AddRules() + { + printf("Entering %s, %s()\n",__FUNCTION__, __FILE__); + + AddAllHeaders(); + + AddRtBypassRule(m_headerHandles[HEADER_HANDLE_ID_WLAN_ETH2], 0); + + AddFltBypassRule(); + + printf("Leaving %s, %s()\n",__FUNCTION__, __FILE__); + return true; + + }// AddRules() + + virtual bool LoadPackets(enum ipa_ip_type ip) + { + // load WLAN ETH2 IP4 packet of size 1kB + // This size will trigger RNDIS aggregation later + if (!WlanHelper::LoadWlanEth2IP4Packet( + m_sendBuffer1, + m_BUFF_MAX_SIZE, + &m_sendSize1)) + return false; + + printf ("Loaded %zu Bytes to Packet 1\n",m_sendSize1); + + add_buff(m_sendBuffer1+WLAN_HDR_SIZE, ETH_HLEN, 13); + + return true; + } + + virtual bool GenerateExpectedPackets() + { + m_expectedBufferSize1 = m_sendSize1; + memcpy(m_expectedBuffer1, m_sendBuffer1, m_expectedBufferSize1); + memcpy(m_expectedBuffer1, WLAN_ETH2_HDR, WLAN_ETH2_HDR_SIZE); + + return true; + } // GenerateExpectedPackets() +}; + +/*----------------------------------------------------------------------------*/ +/* Test05: Header insertion scenario of [ETH_II_802_1Q][IP] -> */ +/* [ETH_II_802_1Q][IP] */ +/*----------------------------------------------------------------------------*/ +class IpaHdrProcCtxTest05 : public IpaHdrProcCtxTestFixture +{ +public: + IpaHdrProcCtxTest05() + { + m_name = "IpaHdrProcCtxTest05"; + m_description = + "Processing Context test 05 - \ + of [ETH_II_802_1Q][IP] -> [ETH_II_802_1Q][IP] \ + 1. Generate and commit all headers for all tests. \ + 2. Generate and commit all processing context rules \ + for all tests.\ + 3. Generate and commit routing table 0. \ + The table contains 1 \"bypass\" rule. \ + All data goes to output pipe TEST2. \ + Routing rule will use processing context 802_1Q_2_802_1Q \ + 4. Generate and commit 1 filtering rule. \ + All traffic goes to routing table 0"; + /* + * NOTE: we use the wlan + ETH header prod pipe since the header + * length shall be equal to 8021Q ETH_II length + */ + m_pCurrentProducer = &m_wlanEth2producer; + m_currProducerClient = IPA_CLIENT_TEST2_PROD; + m_pCurrentConsumer = &m_defaultConsumer; + m_currConsumerPipeNum = IPA_CLIENT_TEST2_CONS; + m_procCtxHandleId = PROC_CTX_HANDLE_ID_802_1Q_2_802_1Q; + m_minIPAHwType = IPA_HW_v4_0; + m_maxIPAHwType = IPA_HW_MAX; + m_runInRegression = false; + Register(*this); + } + + virtual bool LoadPackets(enum ipa_ip_type ip) + { + if (!LoadDefault802_1Q(ip, + m_sendBuffer1, + m_sendSize1)) { + LOG_MSG_ERROR("Failed default Packet\n"); + return false; + } + printf("Loaded %zu Bytes to Packet 1\n", m_sendSize1); + + // modify the MAC addresses only + add_buff(m_sendBuffer1, 12, 14); + + //change vlan ID to 9 + m_sendBuffer1[15] = 0x9; + + print_buff(m_sendBuffer1, m_sendSize1); + + return true; + } + + virtual bool GenerateExpectedPackets() + { + m_expectedBufferSize1 = m_sendSize1; + + // we actually expect the same packet to come out (but after uCP) + memcpy(m_expectedBuffer1, m_sendBuffer1, m_expectedBufferSize1); + + return true; + } // GenerateExpectedPackets() +}; + +/*----------------------------------------------------------------------------*/ +/* Test06: Header insertion scenario of [ETH_II][IP] -> */ +/* [ETH_II_802_1Q][IP] */ +/*----------------------------------------------------------------------------*/ +class IpaHdrProcCtxTest06 : public IpaHdrProcCtxTestFixture +{ +public: + IpaHdrProcCtxTest06() + { + m_name = "IpaHdrProcCtxTest06"; + m_description = + "Processing Context test 06 - \ + of [ETH_II][IP] -> [ETH_II_802_1Q][IP] \ + 1. Generate and commit all headers for all tests. \ + 2. Generate and commit all processing context rules \ + for all tests.\ + 3. Generate and commit routing table 0. \ + The table contains 1 \"bypass\" rule. \ + All data goes to output pipe TEST2. \ + Routing rule will use processing context ETH2_2_802_1Q \ + 4. Generate and commit 1 filtering rule. \ + All traffic goes to routing table 0"; + + m_pCurrentProducer = &m_eth2Producer; + m_currProducerClient = IPA_CLIENT_TEST3_PROD; + m_pCurrentConsumer = &m_defaultConsumer; + m_currConsumerPipeNum = IPA_CLIENT_TEST2_CONS; + m_procCtxHandleId = PROC_CTX_HANDLE_ID_ETH2_2_802_1Q; + m_minIPAHwType = IPA_HW_v4_0; + m_maxIPAHwType = IPA_HW_MAX; + m_runInRegression = false; + Register(*this); + } + + virtual bool LoadPackets(enum ipa_ip_type ip) + { + if (!Eth2Helper::LoadEth2IP4Packet( + m_sendBuffer1, + m_BUFF_MAX_SIZE, + &m_sendSize1)) { + LOG_MSG_ERROR("Failed default Packet\n"); + return false; + } + + printf("Loaded %zu Bytes to Packet 1\n", m_sendSize1); + + // modify the MAC addresses only + add_buff(m_sendBuffer1, 12, 15); + + print_buff(m_sendBuffer1, m_sendSize1); + + return true; + } + + virtual bool GenerateExpectedPackets() + { + size_t len; + + m_expectedBufferSize1 = ETH8021Q_HEADER_LEN + + IP4_PACKET_SIZE; + // copy the VLAN header to expected buffer + memcpy(m_expectedBuffer1, ETH2_8021Q_HDR, ETH8021Q_HEADER_LEN); + + // fill src and dst mac and ethertype + memcpy(m_expectedBuffer1, m_sendBuffer1, 2 * ETH_ALEN); + memcpy(m_expectedBuffer1 + ETH8021Q_ETH_TYPE_OFFSET, + m_sendBuffer1 + ETH2_ETH_TYPE_OFFSET, ETH2_ETH_TYPE_LEN); + + len = m_BUFF_MAX_SIZE - ETH8021Q_HEADER_LEN; + if (!LoadDefaultPacket(IPA_IP_v4, + m_expectedBuffer1 + ETH8021Q_HEADER_LEN, + len)) { + LOG_MSG_ERROR("Failed default Packet\n"); + return false; + } + + return true; + } // GenerateExpectedPackets() +}; + +/*----------------------------------------------------------------------------*/ +/* Test07: Header insertion scenario of [ETH_II_802_1Q][IP] -> */ +/* [ETH_II][IP] */ +/*----------------------------------------------------------------------------*/ +class IpaHdrProcCtxTest07 : public IpaHdrProcCtxTestFixture +{ +public: + IpaHdrProcCtxTest07() + { + m_name = "IpaHdrProcCtxTest07"; + m_description = + "Processing Context test 07 - \ + of [ETH_II_802_1Q][IP] -> [ETH_II][IP] \ + 1. Generate and commit all headers for all tests. \ + 2. Generate and commit all processing context rules \ + for all tests.\ + 3. Generate and commit routing table 0. \ + The table contains 1 \"bypass\" rule. \ + All data goes to output pipe TEST2. \ + Routing rule will use processing context 802_1Q_2_ETH2 \ + 4. Generate and commit 1 filtering rule. \ + All traffic goes to routing table 0"; + + m_pCurrentProducer = &m_wlanEth2producer; + m_currProducerClient = IPA_CLIENT_TEST2_PROD; + m_pCurrentConsumer = &m_defaultConsumer; + m_currConsumerPipeNum = IPA_CLIENT_TEST2_CONS; + m_procCtxHandleId = PROC_CTX_HANDLE_ID_802_1Q_2_ETH2; + m_minIPAHwType = IPA_HW_v4_0; + m_maxIPAHwType = IPA_HW_MAX; + m_runInRegression = false; + Register(*this); + } + + virtual bool LoadPackets(enum ipa_ip_type ip) + { + if (!LoadDefault802_1Q(ip, + m_sendBuffer1, + m_sendSize1)) { + LOG_MSG_ERROR("Failed default Packet\n"); + return false; + } + + printf("Loaded %zu Bytes to Packet 1\n", m_sendSize1); + + // modify the MAC addresses only + add_buff(m_sendBuffer1, ETH8021Q_METADATA_OFFSET, 16); + + print_buff(m_sendBuffer1, m_sendSize1); + + return true; + } + + virtual bool GenerateExpectedPackets() + { + size_t len; + + m_expectedBufferSize1 = m_sendSize1 - ETH8021Q_8021Q_TAG_LEN; + + // copy the ETH2 header to expected buffer + memcpy(m_expectedBuffer1, ETH2_HDR, ETH_HLEN); + + // fill src and dst mac and ethertype + memcpy(m_expectedBuffer1, m_sendBuffer1, 2 * ETH_ALEN); + memcpy(m_expectedBuffer1 + ETH2_ETH_TYPE_OFFSET, + m_sendBuffer1 + ETH8021Q_ETH_TYPE_OFFSET, + ETH2_ETH_TYPE_LEN); + + len = m_BUFF_MAX_SIZE - ETH_HLEN; + if (!LoadDefaultPacket(IPA_IP_v4, + m_expectedBuffer1 + ETH_HLEN, + len)) { + LOG_MSG_ERROR("Failed default Packet\n"); + return false; + } + + return true; + } // GenerateExpectedPackets() +}; + +/*----------------------------------------------------------------------------*/ +/* Test08: Header insertion scenario of [ETH_II][IP] -> */ +/* [ETH_II][IP] with generic ucp command */ +/*----------------------------------------------------------------------------*/ +class IpaHdrProcCtxTest08 : public IpaHdrProcCtxTestFixture +{ +public: + IpaHdrProcCtxTest08() + { + m_name = "IpaHdrProcCtxTest08"; + m_description = + "Processing Context test 08 - \ + of [ETH_II][IP] -> [ETH_II][IP] with generic ucp \ + 1. Generate and commit all headers for all tests. \ + 2. Generate and commit all processing context rules \ + for all tests.\ + 3. Generate and commit routing table 0. \ + The table contains 1 \"bypass\" rule. \ + All data goes to output pipe TEST2. \ + Routing rule will use processing context ETH2_2_ETH2_EX \ + 4. Generate and commit 1 filtering rule. \ + All traffic goes to routing table 0"; + + m_pCurrentProducer = &m_eth2Producer; + m_currProducerClient = IPA_CLIENT_TEST3_PROD; + m_pCurrentConsumer = &m_defaultConsumer; + m_currConsumerPipeNum = IPA_CLIENT_TEST2_CONS; + m_procCtxHandleId = PROC_CTX_HANDLE_ID_ETH2_ETH2_2_ETH2_EX; + m_minIPAHwType = IPA_HW_v4_0; + m_maxIPAHwType = IPA_HW_MAX; + m_runInRegression = false; + Register(*this); + } + + virtual bool LoadPackets(enum ipa_ip_type ip) + { + if (!Eth2Helper::LoadEth2IP4Packet( + m_sendBuffer1, + m_BUFF_MAX_SIZE, + &m_sendSize1)) { + LOG_MSG_ERROR("Failed default Packet\n"); + return false; + } + + printf("Loaded %zu Bytes to Packet 1\n", m_sendSize1); + + // modify the MAC addresses only + add_buff(m_sendBuffer1, 12, 17); + + print_buff(m_sendBuffer1, m_sendSize1); + + return true; + } + + virtual bool GenerateExpectedPackets() + { + m_expectedBufferSize1 = m_sendSize1; + + // we actually expect the same packet to come out (but after uCP) + memcpy(m_expectedBuffer1, m_sendBuffer1, m_expectedBufferSize1); + + return true; + } // GenerateExpectedPackets() +}; + +static IpaHdrProcCtxTest00 ipaHdrProcCtxTest00; +static IpaHdrProcCtxTest01 ipaHdrProcCtxTest01; +static IpaHdrProcCtxTest02 ipaHdrProcCtxTest02; +static IpaHdrProcCtxTest03 ipaHdrProcCtxTest03; +static IpaHdrProcCtxTest04 ipaHdrProcCtxTest04; +static IpaHdrProcCtxTest05 ipaHdrProcCtxTest05; +static IpaHdrProcCtxTest06 ipaHdrProcCtxTest06; +static IpaHdrProcCtxTest07 ipaHdrProcCtxTest07; +static IpaHdrProcCtxTest08 ipaHdrProcCtxTest08; diff --git a/qcom/opensource/dataipa/kernel-tests/HeaderRemovalTestFixture.cpp b/qcom/opensource/dataipa/kernel-tests/HeaderRemovalTestFixture.cpp new file mode 100644 index 0000000000..3067b95caf --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/HeaderRemovalTestFixture.cpp @@ -0,0 +1,404 @@ +/* + * Copyright (c) 2017 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "HeaderRemovalTestFixture.h" + +#include "Constants.h" +#include "Logger.h" +#include "IPAFilteringTable.h" + +#define IPA_TEST_DMUX_HEADER_LENGTH 8 +#define IPA_TEST_META_DATA_IS_VALID 1 +#define IPA_TEST_DMUX_HEADER_META_DATA_OFFSET 4 + +extern Logger g_Logger; + +///////////////////////////////////////////////////////////////////////////////// + +//define the static Pipes which will be used by all derived tests. +Pipe HeaderRemovalTestFixture::m_A2NDUNToIpaPipe(IPA_CLIENT_TEST2_PROD, IPA_TEST_CONFIFURATION_3); +Pipe HeaderRemovalTestFixture::m_IpaToUsbPipe(IPA_CLIENT_TEST_CONS, IPA_TEST_CONFIFURATION_3); +Pipe HeaderRemovalTestFixture::m_IpaToA2NDUNPipe(IPA_CLIENT_TEST2_CONS, IPA_TEST_CONFIFURATION_3); +Pipe HeaderRemovalTestFixture::m_IpaToQ6LANPipe(IPA_CLIENT_TEST4_CONS, IPA_TEST_CONFIFURATION_3); +RoutingDriverWrapper HeaderRemovalTestFixture::m_routing; +Filtering HeaderRemovalTestFixture::m_filtering; +const char HeaderRemovalTestFixture_bypass0[20] = "Bypass0"; +const char HeaderRemovalTestFixture_bypassIPv60[20] = "BypassIPv60"; + +///////////////////////////////////////////////////////////////////////////////// + +HeaderRemovalTestFixture::HeaderRemovalTestFixture() +{ + m_testSuiteName.push_back("Removal"); + Register(*this); +} + +static int SetupKernelModule(void) +{ + int retval; + struct ipa_channel_config from_ipa_channels[3]; + struct test_ipa_ep_cfg from_ipa_cfg[3]; + struct ipa_channel_config to_ipa_channels[1]; + struct test_ipa_ep_cfg to_ipa_cfg[1]; + + struct ipa_test_config_header header = {0}; + struct ipa_channel_config *to_ipa_array[1]; + struct ipa_channel_config *from_ipa_array[3]; + + /* From ipa configurations - 3 pipes */ + memset(&from_ipa_cfg[0], 0, sizeof(from_ipa_cfg[0])); + prepare_channel_struct(&from_ipa_channels[0], + header.from_ipa_channels_num++, + IPA_CLIENT_TEST_CONS, + (void *)&from_ipa_cfg[0], + sizeof(from_ipa_cfg[0])); + from_ipa_array[0] = &from_ipa_channels[0]; + + memset(&from_ipa_cfg[1], 0, sizeof(from_ipa_cfg[1])); + prepare_channel_struct(&from_ipa_channels[1], + header.from_ipa_channels_num++, + IPA_CLIENT_TEST2_CONS, + (void *)&from_ipa_cfg[1], + sizeof(from_ipa_cfg[1])); + from_ipa_array[1] = &from_ipa_channels[1]; + + memset(&from_ipa_cfg[2], 0, sizeof(from_ipa_cfg[2])); + prepare_channel_struct(&from_ipa_channels[2], + header.from_ipa_channels_num++, + IPA_CLIENT_TEST4_CONS, + (void *)&from_ipa_cfg[2], + sizeof(from_ipa_cfg[2])); + from_ipa_array[2] = &from_ipa_channels[2]; + + /* To ipa configurations - 1 pipes */ + memset(&to_ipa_cfg[0], 0, sizeof(to_ipa_cfg[0])); + to_ipa_cfg[0].hdr.hdr_len = IPA_TEST_DMUX_HEADER_LENGTH; + to_ipa_cfg[0].hdr.hdr_ofst_metadata_valid = IPA_TEST_META_DATA_IS_VALID; + to_ipa_cfg[0].hdr.hdr_ofst_metadata = + IPA_TEST_DMUX_HEADER_META_DATA_OFFSET; + prepare_channel_struct(&to_ipa_channels[0], + header.to_ipa_channels_num++, + IPA_CLIENT_TEST2_PROD, + (void *)&to_ipa_cfg[0], + sizeof(to_ipa_cfg[0])); + to_ipa_array[0] = &to_ipa_channels[0]; + + header.head_marker = IPA_TEST_CONFIG_MARKER; + header.tail_marker = IPA_TEST_CONFIG_MARKER; + + prepare_header_struct(&header, from_ipa_array, to_ipa_array); + + retval = GenericConfigureScenario(&header); + + return retval; +} + +///////////////////////////////////////////////////////////////////////////////// + +bool HeaderRemovalTestFixture::Setup() +{ + bool bRetVal = true; + + //Set the configuration to support USB->IPA and IPA->USB pipes. + //ConfigureScenario(PHASE_THREE_TEST_CONFIGURATION); + + bRetVal = SetupKernelModule(); + if (bRetVal != true) { + return bRetVal; + } + + //Initialize the pipe for all the tests - this will open the inode which represents the pipe. + bRetVal &= m_A2NDUNToIpaPipe.Init(); + bRetVal &= m_IpaToUsbPipe.Init(); + bRetVal &= m_IpaToA2NDUNPipe.Init(); + bRetVal &= m_IpaToQ6LANPipe.Init(); + + // remove default "LAN" routing table (as we want to pass to USB pipe) + m_routing.Reset(IPA_IP_v4); + m_routing.Reset(IPA_IP_v6); + + return bRetVal; +} + +///////////////////////////////////////////////////////////////////////////////// + +bool HeaderRemovalTestFixture::Teardown() +{ + //The Destroy method will close the inode. + m_A2NDUNToIpaPipe.Destroy(); + m_IpaToUsbPipe.Destroy(); + m_IpaToA2NDUNPipe.Destroy(); + m_IpaToQ6LANPipe.Destroy(); + return true; +} + +///////////////////////////////////////////////////////////////////////////////// + +Byte* HeaderRemovalTestFixture::CreateA2NDUNPacket( + unsigned int magicNumber, + unsigned int nID, + string sPayloadFileName, + unsigned int *nTotalLength) +{ + size_t nIpv4ByteSize = 1024; + bool bRetVal = false; + Byte *pA2NDUNPacket = 0; + unsigned int nA2NDUNPacketByteSize = 0; + Byte *pIpv4Packet = (Byte*) malloc(1024); + + if(0 == pIpv4Packet) + { + LOG_MSG_ERROR("Cannot allocate the memory for IPv4 packet"); + return 0; + } + + bRetVal = LoadDefaultPacket(IPA_IP_v4, pIpv4Packet, nIpv4ByteSize); + if(false == bRetVal) + { + LOG_MSG_ERROR("Cannot load the packet"); + pA2NDUNPacket = 0; + goto bail; + } + //Magic Number(4 Bytes) Logical Channel ID(2 Bytes) Length(2 Bytes) + nA2NDUNPacketByteSize = m_A2NDUNToIpaPipe.GetHeaderLengthAdd() + nIpv4ByteSize; + + pA2NDUNPacket = new Byte[ nA2NDUNPacketByteSize ]; + + //htobe32 for the magic number: + pA2NDUNPacket[0] = (magicNumber & 0xFF000000) >> 24;//MSB + pA2NDUNPacket[1] = (magicNumber & 0x00FF0000) >> 16; + pA2NDUNPacket[2] = (magicNumber & 0x0000FF00) >> 8; + pA2NDUNPacket[3] = (magicNumber & 0x000000FF) >> 0;//LSB + + //htobe16 for the Logical Channel ID: + pA2NDUNPacket[4] = (nID & 0xFF00) >> 8;//MSB + pA2NDUNPacket[5] = (nID & 0x00FF) >> 0;//LSB + + //htobe16 for the Length of the packet: + pA2NDUNPacket[6] = (nA2NDUNPacketByteSize & 0xFF00) >> 8;//MSB + pA2NDUNPacket[7] = (nA2NDUNPacketByteSize & 0x00FF) >> 0;//LSB + + //add the payload to the A2NDUN packet + memcpy(&pA2NDUNPacket[8], pIpv4Packet, nIpv4ByteSize); + + *nTotalLength = nA2NDUNPacketByteSize; + +/* fall through */ + +bail: + + Free(pIpv4Packet); + + return pA2NDUNPacket; +} + +///////////////////////////////////////////////////////////////////////////////// + +bool HeaderRemovalTestFixture::SetIPATablesToPassAllToSpecificClient( + enum ipa_client_type nClientTypeSrc, + enum ipa_client_type nClientTypeDst) +{ + bool bRetVal = true; + + bRetVal = SetRoutingTableToPassAllToSpecificClient(nClientTypeDst); + if(false == bRetVal) + goto bail; + bRetVal = SetFilterTableToPassAllToSpecificClient(nClientTypeSrc); + if(false == bRetVal) + goto bail; + bRetVal = SetHeaderInsertionTableAddEmptyHeaderForTheClient(nClientTypeSrc); + if(false == bRetVal) + goto bail; +/* fall through */ + +bail: + return bRetVal; +} + +///////////////////////////////////////////////////////////////////////////////// + +bool HeaderRemovalTestFixture::SetFilterTableToPassAllToSpecificClient( + enum ipa_client_type nClientType) +{ + IPAFilteringTable FilterTable; + struct ipa_flt_rule_add flt_rule_entry; + struct ipa_ioc_get_rt_tbl sRoutingTable; + + sRoutingTable.ip = IPA_IP_v4; + strlcpy(sRoutingTable.name, "Bypass0", sizeof(sRoutingTable.name)); + + if (false == m_routing.GetRoutingTable(&sRoutingTable)) { + LOG_MSG_ERROR("Configure the routing block first"); + return false; + } + + FilterTable.Init(IPA_IP_v4, nClientType, false, 1); + FilterTable.GeneratePresetRule(0, flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl = -1; + flt_rule_entry.status = -1; + flt_rule_entry.rule.action = IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.rt_tbl_hdl = sRoutingTable.hdl; + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + flt_rule_entry.rule.attrib.u.v4.dst_addr_mask = 0x00000000; + flt_rule_entry.rule.attrib.u.v4.dst_addr = 0x00000000; + if ((-1 == FilterTable.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable.GetFilteringTable())) { + LOG_MSG_INFO ("%s::Error Adding RuleTable(0) to Filtering, aborting..."); + return false; + } else { + LOG_MSG_INFO( "flt rule hdl0=0x%x, status=0x%x", + FilterTable.ReadRuleFromTable(0)->flt_rule_hdl, + FilterTable.ReadRuleFromTable(0)->status); + } + LOG_MSG_INFO("Leaving "); + + return true; +} +///////////////////////////////////////////////////////////////////////////////// + +bool HeaderRemovalTestFixture::SetRoutingTableToPassAllToSpecificClient( + enum ipa_client_type nClientType) +{ + if (!CreateBypassRoutingTablesIPv4( + HeaderRemovalTestFixture_bypass0, + nClientType)) { + LOG_MSG_INFO("CreateThreeBypassRoutingTables Failed"); + return false; + } + return true; +} + +///////////////////////////////////////////////////////////////////////////////// + +bool HeaderRemovalTestFixture::SetHeaderInsertionTableAddEmptyHeaderForTheClient( + enum ipa_client_type nClientType) +{ + //TODO Header Removal: add header insertion data + return true; +} + +///////////////////////////////////////////////////////////////////////////////// +// This function creates IPv4 bypass routing entry and commits it. +bool HeaderRemovalTestFixture::CreateBypassRoutingTablesIPv4( + const char * bypass0, + enum ipa_client_type nClientType) +{ + struct ipa_ioc_add_rt_rule *rt_rule0 = 0; + struct ipa_rt_rule_add *rt_rule_entry; + + LOG_MSG_INFO("Entering"); + + rt_rule0 = (struct ipa_ioc_add_rt_rule *) + calloc(1, sizeof(struct ipa_ioc_add_rt_rule) + + 1*sizeof(struct ipa_rt_rule_add)); + if (!rt_rule0) { + LOG_MSG_INFO("calloc failed to allocate rt_rule0"); + return false; + } + + rt_rule0->num_rules = 1; + rt_rule0->ip = IPA_IP_v4; + rt_rule0->commit = true; + strlcpy(rt_rule0->rt_tbl_name, bypass0, sizeof(rt_rule0->rt_tbl_name)); + + rt_rule_entry = &rt_rule0->rules[0]; + rt_rule_entry->at_rear = 0; + rt_rule_entry->rule.dst = nClientType; +// rt_rule_entry->rule.hdr_hdl = hdr_entry->hdr_hdl; // gidons, there is no support for header insertion / removal yet. + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v4.dst_addr = 0xaabbccdd; + rt_rule_entry->rule.attrib.u.v4.dst_addr_mask = 0x00000000;// All Packets will get a "Hit" + if (false == m_routing.AddRoutingRule(rt_rule0)) { + LOG_MSG_INFO("Routing rule addition(rt_rule0) failed!"); + Free (rt_rule0); + return false; + } + + Free (rt_rule0); + LOG_MSG_INFO("Leaving "); + return true; +} + +bool HeaderRemovalTestFixture::ConfigureFilteringBlockWithMetaDataEq( + enum ipa_client_type nClientType, + unsigned int nMetaData, + unsigned int nMetaDataMask) +{ + const char bypass0[20] = "Bypass0"; + struct ipa_ioc_get_rt_tbl routing_table0; + IPAFilteringTable FilterTable0; + struct ipa_flt_rule_add flt_rule_entry; + + LOG_MSG_INFO("Entering "); + + if (!CreateBypassRoutingTablesIPv4( + HeaderRemovalTestFixture_bypass0, + nClientType)) { + LOG_MSG_INFO("CreateBypassRoutingTablesIPv4 Failed"); + return false; + } + + LOG_MSG_INFO("CreateBypassRoutingTablesIPv4 completed successfully"); + routing_table0.ip = IPA_IP_v4; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) { + LOG_MSG_INFO( + "m_routing.GetRoutingTable(&routing_table0=0x%p) Failed." + ,&routing_table0); + return false; + } + + FilterTable0.Init(IPA_IP_v4, IPA_CLIENT_TEST2_PROD, false, 1); + + LOG_MSG_INFO("FilterTable*.Init Completed Successfully.."); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1,flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl = -1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action = IPA_PASS_TO_ROUTING; + flt_rule_entry.rule.rt_tbl_hdl = routing_table0.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_META_DATA; + flt_rule_entry.rule.attrib.meta_data = nMetaData; + flt_rule_entry.rule.attrib.meta_data_mask = nMetaDataMask; + if ( (-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable())) + { + LOG_MSG_INFO ("%s::Error Adding RuleTable(0) to Filtering, aborting..."); + return false; + } else { + LOG_MSG_INFO("flt rule hdl0=0x%x, status=0x%x", FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl,FilterTable0.ReadRuleFromTable(0)->status); + } + + LOG_MSG_INFO("Leaving "); + + return true; +} diff --git a/qcom/opensource/dataipa/kernel-tests/HeaderRemovalTestFixture.h b/qcom/opensource/dataipa/kernel-tests/HeaderRemovalTestFixture.h new file mode 100644 index 0000000000..38e6761b47 --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/HeaderRemovalTestFixture.h @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2017 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _IPA_LINUX_TESTS_HR_TEST_FIXTURE_H_ +#define _IPA_LINUX_TESTS_HR_TEST_FIXTURE_H_ + + +#include +#include +#include +#include +#include + +#include "Constants.h" +#include "Logger.h" +#include "linux/msm_ipa.h" +#include "TestsUtils.h" +#include "TestBase.h" +#include "Pipe.h" +#include "RoutingDriverWrapper.h" +#include "Filtering.h" + +/*This class will be the base class of all HeaderRemoval tests. + *Any method other than the test case itself can + *be declared in this Fixture thus allowing the derived classes to + *implement only the test case. + *All the test of the HeaderRemovalTestFixture + *uses one input and two output. + */ +class HeaderRemovalTestFixture:public TestBase +{ +public: + /*This Constructor will register each instance + * that it creates.*/ + HeaderRemovalTestFixture(); + + /*This method will create and initialize two Pipe object for the USB + *(Ethernet) Pipes, one as input and the other as output. + */ + virtual bool Setup(); + + /*This method will destroy the pipes.*/ + virtual bool Teardown(); + + /*The client type are set from the peripheral perspective + *(TODO Pipe:in case the Driver will change its perspective + *of ipa_connect this should be changed). + */ + static Pipe m_A2NDUNToIpaPipe; + /*from the test application into the IPA(DMUX header)*/ + static Pipe m_IpaToUsbPipe; + /*from the IPA back to the test application(Ethernet header)*/ + static Pipe m_IpaToA2NDUNPipe; + /*from the IPA back to the test application(DMUX header)*/ + static Pipe m_IpaToQ6LANPipe; + + static RoutingDriverWrapper m_routing; + static Filtering m_filtering; + +protected: + unsigned char *CreateA2NDUNPacket(unsigned int magicNumber, + unsigned int ID, + string sPayloadFileName, + unsigned int *nTotalLength); + bool SetIPATablesToPassAllToSpecificClient( + enum ipa_client_type nClientTypeSrc, + enum ipa_client_type nClientTypeDst); + bool SetFilterTableToPassAllToSpecificClient( + enum ipa_client_type nClientType); + bool SetRoutingTableToPassAllToSpecificClient( + enum ipa_client_type nClientType); + bool SetHeaderInsertionTableAddEmptyHeaderForTheClient( + enum ipa_client_type nClientType); + bool CreateBypassRoutingTablesIPv4( + const char *bypass0, + enum ipa_client_type nClientType + ); + bool ConfigureFilteringBlockWithMetaDataEq( + enum ipa_client_type nClientType, + unsigned int nMetaData, + unsigned int nMetaDataMask); +}; + +#endif + diff --git a/qcom/opensource/dataipa/kernel-tests/HeaderRemovalTests.cpp b/qcom/opensource/dataipa/kernel-tests/HeaderRemovalTests.cpp new file mode 100644 index 0000000000..a45e503add --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/HeaderRemovalTests.cpp @@ -0,0 +1,218 @@ +/* + * Copyright (c) 2017 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "HeaderRemovalTests.h" +#include "TestsUtils.h" +#include + +///////////////////////////////////////////////////////////////////////////////// + +static const unsigned int HEADER_REMOVAL_TEST_MAX_PACKET_BYTE_SIZE = 1024; + +///////////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// + + +HeaderRemovalTOSCheck::HeaderRemovalTOSCheck() +{ + m_name = "HeaderRemovalTOSCheck"; + m_description = "HeaderRemovalTOSCheck: Remove the header from the A2NDUN pipe and check the TOS field of the IP packet"; +} + +///////////////////////////////////////////////////////////////////////////////// + +bool HeaderRemovalTOSCheck::Run() +{ + bool bTestResult = true; + Byte pPacketReceiveBuffer[HEADER_REMOVAL_TEST_MAX_PACKET_BYTE_SIZE] = {0};//This buffer will be used in order to store the received packet. + + unsigned int nMagicNumber = 0x12345678; //arbitrary number + unsigned int nChannelID = 0xABCD;//arbitrary number + unsigned int nA2NDUNPacketByteSize = 0; + unsigned int nBytesSent = 0; + int nBytesReceived = 0; + Byte *pA2NDUNPacket = CreateA2NDUNPacket(nMagicNumber, nChannelID, IPV4_FILE_PATH, &nA2NDUNPacketByteSize); + if(0 == pA2NDUNPacket) { + LOG_MSG_ERROR("Cannot load file to memory, exiting"); + return false; + } + LOG_MSG_INFO("A2 Packet was successfully created (%d bytes)", nA2NDUNPacketByteSize); + + if ( false == SetIPATablesToPassAllToSpecificClient(IPA_CLIENT_TEST2_PROD, IPA_CLIENT_TEST_CONS)) { + LOG_MSG_ERROR("SetIPATablesToPassAllToSpecificClient failed, exiting test case"); + bTestResult = false; + goto bail; + } + + LOG_MSG_INFO("All tables were configured in order to output the packet to the correct pipe"); + + LOG_MSG_INFO("Sending packet into the A2NDUN pipe(%d bytes) and the Pipe will add an header", + nA2NDUNPacketByteSize); + + nBytesSent = m_A2NDUNToIpaPipe.Send(pA2NDUNPacket, nA2NDUNPacketByteSize); + if (nA2NDUNPacketByteSize != nBytesSent) + { + bTestResult = false; + goto bail; + } + //Receive the raw IP packet(which is a 4 arbitrary bytes) without header removal by the Pipe + LOG_MSG_INFO("Reading packet from the USB pipe"); + + nBytesReceived = m_IpaToUsbPipe.Receive(pPacketReceiveBuffer, HEADER_REMOVAL_TEST_MAX_PACKET_BYTE_SIZE); + //TODO Header Removal: at this point the success scenario is that data came to the correct pipe - change this to + //packet memory compare after header insertion is enabled. + if (0 == nBytesReceived) + { + bTestResult = false; + goto bail; + } + + LOG_MSG_INFO("Read buffer : "); + //Print the output + for (int i = 0 ; i < nBytesReceived ; i++) + { + printf("0x%02x", pPacketReceiveBuffer[i]); + } + LOG_MSG_INFO("End of Read buffer."); + + if(0 != memcmp((const void *)pPacketReceiveBuffer, + (const void *)(pA2NDUNPacket + (nBytesSent - nBytesReceived)), + nBytesReceived)) { + LOG_MSG_ERROR("Memory contains don't match"); + bTestResult = false; + goto bail; + } +/* fall through */ + +bail: + + delete pA2NDUNPacket; + return bTestResult; +} + +HeaderRemovalMetaDataFiltering::HeaderRemovalMetaDataFiltering() +{ + m_name = "HeaderRemovalMetaDataFiltering"; + m_description = + "HeaderRemovalMetaDataFiltering: check meta data based filtering"; +} + +///////////////////////////////////////////////////////////////////////////////// + +bool HeaderRemovalMetaDataFiltering::Run() +{ + bool bTestResult = true; + Byte pPacketReceiveBuffer[HEADER_REMOVAL_TEST_MAX_PACKET_BYTE_SIZE] = {0};//This buffer will be used in order to store the received packet. + + unsigned int nMagicNumber = 0x12345678; //arbitrary number + unsigned int nChannelID = 0xABCD;//arbitrary number + unsigned int nA2NDUNPacketByteSize = 0; + unsigned int nMetaData = 0; + unsigned int nMetaDataMask = 0xFFFF; + unsigned int nBytesSent = 0; + int nBytesReceived = 0; + + + Byte *pA2NDUNPacket = CreateA2NDUNPacket(nMagicNumber, nChannelID, IPV4_FILE_PATH, &nA2NDUNPacketByteSize); + if(0 == pA2NDUNPacket) { + LOG_MSG_ERROR("Cannot load file to memory, exiting"); + return false; + } + + nMetaData = (nChannelID << 16) | (0xFFFF & nA2NDUNPacketByteSize); + LOG_MSG_INFO("*************nMetaData == (0x%x)", nMetaData); + + LOG_MSG_INFO("A2 Packet was successfully created (%d bytes)", nA2NDUNPacketByteSize); + + SetRoutingTableToPassAllToSpecificClient(IPA_CLIENT_TEST_CONS); + SetHeaderInsertionTableAddEmptyHeaderForTheClient(IPA_CLIENT_TEST_CONS); + + LOG_MSG_INFO("Configuring Filtering module..."); + + if (false == + ConfigureFilteringBlockWithMetaDataEq( + IPA_CLIENT_TEST_CONS, + nMetaData, + nMetaDataMask)) { + bTestResult = false; + goto bail; + } + + LOG_MSG_INFO("Sending packet into the A2NDUN pipe(%d bytes) and the Pipe will add an header", + nA2NDUNPacketByteSize); + nBytesSent = m_A2NDUNToIpaPipe.Send(pA2NDUNPacket, nA2NDUNPacketByteSize); + if (nA2NDUNPacketByteSize != nBytesSent) { + bTestResult = false; + goto bail; + } + + //Receive the raw IP packet(which is a 4 arbitrary bytes) without header removal by the Pipe + LOG_MSG_INFO("Reading packet from the USB pipe"); + nBytesReceived = m_IpaToUsbPipe.Receive(pPacketReceiveBuffer, HEADER_REMOVAL_TEST_MAX_PACKET_BYTE_SIZE); + //TODO Header Removal: at this point the success scenario is that data came to the correct pipe - change this to + //packet memory compare after header insertion is enabled. + if (0 == nBytesReceived) { + bTestResult = false; + goto bail; + } + + LOG_MSG_INFO("Read buffer : "); + //Print the output + for (int i = 0 ; i < nBytesReceived ; i++) { + printf("0x%02x", pPacketReceiveBuffer[i]); + } + LOG_MSG_INFO("End of Read buffer."); + + if(0 != memcmp((const void *)pPacketReceiveBuffer, + (const void *)(pA2NDUNPacket + (nBytesSent - nBytesReceived)), + nBytesReceived)) { + LOG_MSG_ERROR("Memory contains don't match"); + bTestResult = false; + goto bail; + } + +/* fall through */ + +bail: + + delete pA2NDUNPacket; + return bTestResult; +} + +static HeaderRemovalTOSCheck headerRemovalTOSCheck; +static HeaderRemovalMetaDataFiltering headerRemovalMetaDataFiltering; + +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// + diff --git a/qcom/opensource/dataipa/kernel-tests/HeaderRemovalTests.h b/qcom/opensource/dataipa/kernel-tests/HeaderRemovalTests.h new file mode 100644 index 0000000000..8bc6967ef1 --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/HeaderRemovalTests.h @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2017 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _IPA_LINUX_TESTS_HR_TESTS_H_ +#define _IPA_LINUX_TESTS_HR_TESTS_H_ + +#include +#include +#include +#include +#include + +#include "Constants.h" +#include "linux/msm_ipa.h" +#include "TestsUtils.h" +#include "HeaderRemovalTestFixture.h" + +/*This test will send a DMUX with IP packet and check it TOS field thus + *validating the the header was removed. + */ +class HeaderRemovalTOSCheck:public HeaderRemovalTestFixture +{ +public: + /*This Constructor will be use to specify some test description.*/ + HeaderRemovalTOSCheck(); + + /*This method will send a an IP packet with + * DMUX header and create a rule + * */ + virtual bool Run(); +}; + +/*This test will send a DMUX with IP packet and see if it filtered + *by meta data contained in link layer header as expected + */ +class HeaderRemovalMetaDataFiltering:HeaderRemovalTestFixture +{ +public: + /* his Constructor will be use to specify + * some test description.*/ + HeaderRemovalMetaDataFiltering(); + + virtual bool Run(); + +}; + +#endif diff --git a/qcom/opensource/dataipa/kernel-tests/IPAFilteringTable.cpp b/qcom/opensource/dataipa/kernel-tests/IPAFilteringTable.cpp new file mode 100644 index 0000000000..cb0896aa5c --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/IPAFilteringTable.cpp @@ -0,0 +1,313 @@ +/* + * Copyright (c) 2017,2020-2021 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "IPAFilteringTable.h" +#include +#include "TestsUtils.h" + +IPAFilteringTable::IPAFilteringTable () : // C'tor + m_pFilteringTable(NULL), + nextRuleIndex(0) {} + +bool IPAFilteringTable::Init(ipa_ip_type ipFamily, ipa_client_type pipeNo, uint8_t isGlobal, uint8_t numOfRulesInTable, uint8_t commit) +{ + if (NULL != m_pFilteringTable) { + char message[256] = {0}; + snprintf(message, sizeof(message), "Error in Function %s, m_pFilteringTable==0x%p, must be NULL, Please call D'tor prior to calling () %s.", + __FUNCTION__,m_pFilteringTable,__FUNCTION__); + ReportError(message); + return false; + } + + if (numOfRulesInTable < 1) { + char message[256] = {0}; + snprintf(message, sizeof(message),"Error in Function %s, numberOfRulesInTable==%d must be > 0", + __FUNCTION__,numOfRulesInTable); + ReportError(message); + return false; + } + + m_pFilteringTable = (struct ipa_ioc_add_flt_rule *) + calloc(1, sizeof(struct ipa_ioc_add_flt_rule) + + numOfRulesInTable *sizeof(struct ipa_flt_rule_add)); + + if (NULL == m_pFilteringTable) { + char message[256] = {0}; + snprintf(message, sizeof(message),"Error in Function %s, Failed to allocate %d filter rules in Filtering Table",__FUNCTION__,numOfRulesInTable); + ReportError(message); + return false; + } + + m_pFilteringTable->commit = commit; + m_pFilteringTable->ep = pipeNo; + m_pFilteringTable->global = isGlobal; + m_pFilteringTable->ip = ipFamily; + m_pFilteringTable->num_rules = (uint8_t)(numOfRulesInTable); + + return true; +} + +bool IPAFilteringTable::GeneratePresetRule(uint8_t preset,ipa_flt_rule_add &flt_rule_entry) +{ + memset(&flt_rule_entry,0,sizeof(ipa_flt_rule_add)); // Zero All Fields + + switch (preset) + { + case 0: // in Preset 0 the Filtering Rule is matches all (bypass) + flt_rule_entry.flt_rule_hdl=-1; // return Value + flt_rule_entry.status = -1; // return value + break; + case 1: + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl=-1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action=IPA_PASS_TO_ROUTING; + //flt_rule_entry.rule.rt_tbl_hdl=routing_table0.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_PROTOCOL; + flt_rule_entry.rule.attrib.u.v4.protocol = 17; // Filter only UDP Packets. + break; + default: + char message[256] = {0}; + snprintf(message, sizeof(message),"Error in Function %s, preset=%d, is not supported.",__FUNCTION__,preset); + ReportError(message); + return false; + } + return true; +} + +uint8_t IPAFilteringTable::AddRuleToTable(ipa_flt_rule_add flt_rule_entry) +{ + if (NULL == m_pFilteringTable) { + char message[256] = {0}; + snprintf(message, sizeof(message),"Error in Function %s, m_pFilteringTable==NULL, Please call Init() prior to calling %s().",__FUNCTION__,__FUNCTION__); + ReportError(message); + return -1; + } + + if (nextRuleIndex >= m_pFilteringTable->num_rules) { + char message[256] = {0}; + snprintf(message, sizeof(message),"Error in Function %s, ruleIindex==%d while, No. of Rules in Filtering Table is %d. Please use IPAFilteringTable::WriteRule().", + __FUNCTION__,nextRuleIndex,m_pFilteringTable->num_rules); + ReportError(message); + return -1; + } + struct ipa_flt_rule_add *pFilteringRule = &(m_pFilteringTable->rules[nextRuleIndex]); + memcpy(pFilteringRule,&flt_rule_entry,sizeof(ipa_flt_rule_add)); + nextRuleIndex++; + return(nextRuleIndex-1); +} + +const ipa_flt_rule_add * IPAFilteringTable::ReadRuleFromTable(uint8_t index) +{ + if (index < nextRuleIndex) + return (&(m_pFilteringTable->rules[index])); + return NULL; +} + +bool IPAFilteringTable::WriteRuleToEndOfTable(const ipa_flt_rule_add *flt_rule_entry) { + ipa_ioc_add_flt_rule *prev_flt; + + if (NULL == m_pFilteringTable) { + char message[256] = { 0 }; + snprintf(message, sizeof(message), "Error in Function %s, m_pFilteringTable==NULL, Please call Init() prior to calling %s().", __FUNCTION__, __FUNCTION__); + ReportError(message); + return false; + } + + prev_flt = m_pFilteringTable; + m_pFilteringTable = NULL; + m_pFilteringTable = (struct ipa_ioc_add_flt_rule *)calloc( + 1, sizeof(struct ipa_ioc_add_flt_rule) + + ((prev_flt->num_rules + 1) * sizeof(struct ipa_flt_rule_add))); + + if (NULL == m_pFilteringTable) { + char message[256] = { 0 }; + snprintf( + message, sizeof(message), + "Error in Function %s, Failed to allocate %d filter rules in Filtering Table", + __FUNCTION__, prev_flt->num_rules + 1); + ReportError(message); + return false; + } + + m_pFilteringTable->commit = prev_flt->commit; + m_pFilteringTable->ep = prev_flt->ep; + m_pFilteringTable->global = prev_flt->global; + m_pFilteringTable->ip = prev_flt->ip; + m_pFilteringTable->num_rules = prev_flt->num_rules + 1; + + for (int i = 0; i < prev_flt->num_rules; i++) { + memcpy(&(m_pFilteringTable->rules[i]), &(prev_flt->rules[i]), + sizeof(ipa_flt_rule_add)); + } + free(prev_flt); + + struct ipa_flt_rule_add *pFilteringRule = &(m_pFilteringTable->rules[nextRuleIndex]); + memcpy(pFilteringRule, flt_rule_entry, sizeof(ipa_flt_rule_add)); + nextRuleIndex++; + return true; + +} + +//This Function Frees the Filtering Table and all it's content. +//This Function will always return TRUE; +void IPAFilteringTable::Destructor() +{ + if (NULL != m_pFilteringTable) { + free (m_pFilteringTable); + printf("Filtering Table Freed\n"); + } + m_pFilteringTable = NULL; + nextRuleIndex = 0; +} + +IPAFilteringTable::~IPAFilteringTable() +{ + Destructor(); +} + +/* V2 */ + +IPAFilteringTable_v2::IPAFilteringTable_v2() : // C'tor + m_pFilteringTable_v2(NULL), + nextRuleIndex(0) +{ +} + +bool IPAFilteringTable_v2::Init(ipa_ip_type ipFamily, ipa_client_type pipeNo, uint8_t isGlobal, uint8_t numOfRulesInTable, uint8_t commit) +{ + if (NULL != m_pFilteringTable_v2) { + char message[256] = { 0 }; + snprintf(message, sizeof(message), "Error in Function %s, m_pFilteringTable_v2==0x%p, must be NULL, Please call D'tor prior to calling () %s.", + __FUNCTION__, m_pFilteringTable_v2, __FUNCTION__); + ReportError(message); + return false; + } + + if (numOfRulesInTable < 1) { + char message[256] = { 0 }; + snprintf(message, sizeof(message), "Error in Function %s, numberOfRulesInTable==%d must be > 0", + __FUNCTION__, numOfRulesInTable); + ReportError(message); + return false; + } + + m_pFilteringTable_v2 = (struct ipa_ioc_add_flt_rule_v2 *) + calloc(1, sizeof(struct ipa_ioc_add_flt_rule_v2)); + m_pFilteringTable_v2->rules = (uint64_t)calloc(numOfRulesInTable, sizeof(struct ipa_flt_rule_add_v2)); + + if (NULL == m_pFilteringTable_v2) { + char message[256] = { 0 }; + snprintf(message, sizeof(message), "Error in Function %s, Failed to allocate %d filter rules in Filtering Table V2", __FUNCTION__, numOfRulesInTable); + ReportError(message); + return false; + } + + m_pFilteringTable_v2->commit = commit; + m_pFilteringTable_v2->ep = pipeNo; + m_pFilteringTable_v2->global = isGlobal; + m_pFilteringTable_v2->ip = ipFamily; + m_pFilteringTable_v2->num_rules = (uint8_t)(numOfRulesInTable); + m_pFilteringTable_v2->flt_rule_size = sizeof(struct ipa_flt_rule_add_v2); + return true; +} + +bool IPAFilteringTable_v2::GeneratePresetRule(uint8_t preset, ipa_flt_rule_add_v2 &flt_rule_entry) +{ + memset(&flt_rule_entry, 0, sizeof(ipa_flt_rule_add_v2)); // Zero All Fields + + switch (preset) { + case 0: // in Preset 0 the Filtering Rule is matches all (bypass) + flt_rule_entry.flt_rule_hdl = -1; // return Value + flt_rule_entry.status = -1; // return value + break; + case 1: + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl = -1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action = IPA_PASS_TO_ROUTING; + //flt_rule_entry.rule.rt_tbl_hdl=routing_table0.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_PROTOCOL; + flt_rule_entry.rule.attrib.u.v4.protocol = 17; // Filter only UDP Packets. + break; + default: + char message[256] = { 0 }; + snprintf(message, sizeof(message), "Error in Function %s, preset=%d, is not supported.", __FUNCTION__, preset); + ReportError(message); + return false; + } + return true; +} + +uint8_t IPAFilteringTable_v2::AddRuleToTable(ipa_flt_rule_add_v2 flt_rule_entry) +{ + if (NULL == m_pFilteringTable_v2) { + char message[256] = { 0 }; + snprintf(message, sizeof(message), "Error in Function %s, m_pFilteringTable_v2==NULL, Please call Init() prior to calling %s().", __FUNCTION__, __FUNCTION__); + ReportError(message); + return -1; + } + + if (nextRuleIndex >= m_pFilteringTable_v2->num_rules) { + char message[256] = { 0 }; + snprintf(message, sizeof(message), "Error in Function %s, ruleIindex==%d while, No. of Rules in Filtering Table is %d. Please use IPAFilteringTable::WriteRule().", + __FUNCTION__, nextRuleIndex, m_pFilteringTable_v2->num_rules); + ReportError(message); + return -1; + } + struct ipa_flt_rule_add_v2 *pFilteringRule = &(((struct ipa_flt_rule_add_v2 *)(m_pFilteringTable_v2->rules))[nextRuleIndex]); + memcpy(pFilteringRule, &flt_rule_entry, sizeof(ipa_flt_rule_add_v2)); + nextRuleIndex++; + return(nextRuleIndex - 1); +} + +const ipa_flt_rule_add_v2 *IPAFilteringTable_v2::ReadRuleFromTable(uint8_t index) +{ + if (index < nextRuleIndex) + return (&(((struct ipa_flt_rule_add_v2*)m_pFilteringTable_v2->rules)[index])); + return NULL; +} + +//This Function Frees the Filtering Table and all it's content. +//This Function will always return TRUE; +void IPAFilteringTable_v2::Destructor() +{ + if (NULL != m_pFilteringTable_v2) { + free(m_pFilteringTable_v2); + printf("Filtering Table Freed\n"); + } + m_pFilteringTable_v2 = NULL; + nextRuleIndex = 0; +} + +IPAFilteringTable_v2::~IPAFilteringTable_v2() +{ + Destructor(); +} + diff --git a/qcom/opensource/dataipa/kernel-tests/IPAFilteringTable.h b/qcom/opensource/dataipa/kernel-tests/IPAFilteringTable.h new file mode 100644 index 0000000000..05ce129023 --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/IPAFilteringTable.h @@ -0,0 +1,136 @@ +/* + * Copyright (c) 2017,2020-2021 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FILTERING_TABLE_ +#define _FILTERING_TABLE_ + +#include "Constants.h" +#include "Filtering.h" + +/*This Class Encapsulate Filtering Table and Filtering Rules. + *It allows the user to easily manipulate rules and Tables. + */ +class IPAFilteringTable { + public: + IPAFilteringTable(); + ~IPAFilteringTable(); + + bool Init(ipa_ip_type ipFamily, ipa_client_type pipeNo, + uint8_t isGlobal, uint8_t numOfRulesInTable, + uint8_t commit = true); + + /*This Function Frees the Filtering Table and all it's content. + *This Function will always return TRUE; + */ + void Destructor(); + + bool GeneratePresetRule(uint8_t preset, + ipa_flt_rule_add &flt_rule_entry); + bool GeneratePresetRule(uint8_t preset, + ipa_flt_rule_add_v2 &flt_rule_entry); + uint8_t AddRuleToTable(ipa_flt_rule_add flt_rule_entry); + uint8_t AddRuleToTable(ipa_flt_rule_add_v2 flt_rule_entry); + bool WriteRuleToEndOfTable(const ipa_flt_rule_add *flt_rule_entry); + + /*Warning!!! + *Take care when using this function. + *The Returned pointer existence is guaranteed only as + *long as no other method of this class is called. + */ + const ipa_flt_rule_add *ReadRuleFromTable(uint8_t index); + + /*Warning!!! + *Take care when using this function + *The Returned pointer existence is guaranteed only + *as long as no other method of this class is called. + */ + const ipa_ioc_add_flt_rule *GetFilteringTable() + { + return m_pFilteringTable; + } + + uint8_t size() + { + return nextRuleIndex; + } + + private: + void ReportError(char *message) + { + printf("%s\n", message); + } + ipa_ioc_add_flt_rule *m_pFilteringTable; + uint8_t nextRuleIndex; +}; + +class IPAFilteringTable_v2 { + public: + IPAFilteringTable_v2(); + ~IPAFilteringTable_v2(); + + bool Init(ipa_ip_type ipFamily, ipa_client_type pipeNo, + uint8_t isGlobal, uint8_t numOfRulesInTable, + uint8_t commit = true); + + /*This Function Frees the Filtering Table and all it's content. + *This Function will always return TRUE; + */ + void Destructor(); + + bool GeneratePresetRule(uint8_t preset, + ipa_flt_rule_add_v2 &flt_rule_entry); + uint8_t AddRuleToTable(ipa_flt_rule_add_v2 flt_rule_entry); + + /*Warning!!! + *Take care when using this function. + *The Returned pointer existence is guaranteed only as + *long as no other method of this class is called. + */ + const ipa_flt_rule_add_v2 *ReadRuleFromTable(uint8_t index); + + /*Warning!!! + *Take care when using this function + *The Returned pointer existence is guaranteed only + *as long as no other method of this class is called. + */ + const ipa_ioc_add_flt_rule_v2 *GetFilteringTable() + { + return m_pFilteringTable_v2; + } + + private: + void ReportError(char *message) + { + printf("%s\n", message); + } + ipa_ioc_add_flt_rule_v2 *m_pFilteringTable_v2; + uint8_t nextRuleIndex; +}; + +#endif diff --git a/qcom/opensource/dataipa/kernel-tests/IPAInterruptsTestFixture.cpp b/qcom/opensource/dataipa/kernel-tests/IPAInterruptsTestFixture.cpp new file mode 100644 index 0000000000..c7b1815ec5 --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/IPAInterruptsTestFixture.cpp @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2017 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "IPAInterruptsTestFixture.h" + +/*define the static Pipes which will be used by all derived tests.*/ +Pipe IPAInterruptsTestFixture::m_IpaToUsbPipe(IPA_CLIENT_TEST_CONS, IPA_TEST_CONFIGURATION_19); +Pipe IPAInterruptsTestFixture::m_UsbToIpaPipe(IPA_CLIENT_TEST_PROD, IPA_TEST_CONFIGURATION_19); + +IPAInterruptsTestFixture::IPAInterruptsTestFixture() +{ + m_testSuiteName.push_back("Interrupts"); +} + +bool IPAInterruptsTestFixture::Setup() +{ + return true; +} + +bool IPAInterruptsTestFixture::Run() +{ + bool bTestResult = true; + Byte pIpPacket[] = { 0x01, 0x02, 0x03, 0x04 }; //This packet will be sent(It can be replaced by a real IP packet). + Byte pIpPacketReceive[sizeof(pIpPacket)] = { 0 }; //This buffer will be used in order to store the received packet. + + //Send the raw IP packet(which is a 4 arbitrary bytes) without header addition by the Pipe + LOG_MSG_DEBUG( + "Sending packet into the USB pipe(%d bytes)\n", sizeof(pIpPacket)); + int nBytesSent = m_UsbToIpaPipe.Send(pIpPacket, sizeof(pIpPacket)); + if (sizeof(pIpPacket) != nBytesSent) { + return false; + } + + //Receive the raw IP packet(which is a 4 arbitrary bytes) without header removal by the Pipe + LOG_MSG_DEBUG( + "Reading packet from the USB pipe(%d bytes should be there)\n", sizeof(pIpPacketReceive)); + int nBytesReceived = m_IpaToUsbPipe.Receive(pIpPacketReceive, + sizeof(pIpPacketReceive)); + if (sizeof(pIpPacketReceive) != nBytesReceived) { + LOG_MSG_DEBUG("sizes mismatch\n"); + for (int i = 0; i < nBytesReceived && i < (int)sizeof(pIpPacketReceive) ; i++) { + LOG_MSG_DEBUG("0x%02x\n", pIpPacketReceive[i]); + } + return false; + } + for (int i = 0; i < nBytesReceived; i++) { + LOG_MSG_DEBUG("0x%02x\n", pIpPacketReceive[i]); + } + + //Check that the sent IP packet is equal to the received IP packet. + LOG_MSG_DEBUG("Checking sent.vs.received packet\n"); + bTestResult &= !memcmp(pIpPacket, pIpPacketReceive, sizeof(pIpPacket)); + + return bTestResult; +} + +bool IPAInterruptsTestFixture::Teardown() +{ + /* unregister the test framework suspend handler */ + RegSuspendHandler(false, false, 0); + + /*The Destroy method will close the inode.*/ + m_IpaToUsbPipe.Destroy(); + m_UsbToIpaPipe.Destroy(); + ConfigureScenario(-1); + return true; +} diff --git a/qcom/opensource/dataipa/kernel-tests/IPAInterruptsTestFixture.h b/qcom/opensource/dataipa/kernel-tests/IPAInterruptsTestFixture.h new file mode 100644 index 0000000000..d2b3dd0ede --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/IPAInterruptsTestFixture.h @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2017 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include + +#include "Constants.h" +#include "Logger.h" +#include "linux/msm_ipa.h" +#include "TestsUtils.h" +#include "TestBase.h" +#include "Pipe.h" + +/*This class will be the base class of all Pipe tests. + *Any method other than the test case itself can be + *declared in this Fixture thus allowing the derived classes to + *implement only the test case. + *All the test of the pipe uses one input and one output in DMA mode. + */ +class IPAInterruptsTestFixture:public TestBase +{ +public: + /*This Constructor will register each instance that it creates.*/ + IPAInterruptsTestFixture(); + + /*This method will create and initialize two Pipe object for the USB + * (Ethernet) Pipes, one as input and the other as output. + */ + virtual bool Setup(); + + /*Run test logic*/ + bool Run(); + + /*This method will destroy the pipes.*/ + virtual bool Teardown(); + + /*The client type are set from the peripheral perspective + * (TODO Pipe:in case the Driver will change its perspective + * of ipa_connect this should be changed). + */ + static Pipe m_IpaToUsbPipe; + static Pipe m_UsbToIpaPipe; +}; diff --git a/qcom/opensource/dataipa/kernel-tests/IPAInterruptsTests.cpp b/qcom/opensource/dataipa/kernel-tests/IPAInterruptsTests.cpp new file mode 100644 index 0000000000..196ca68653 --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/IPAInterruptsTests.cpp @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2017 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include + +#include "IPAInterruptsTestFixture.h" +#include "Constants.h" +#include "TestsUtils.h" +#include "linux/msm_ipa.h" + +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// + +class SuspendTestDeferred: public IPAInterruptsTestFixture { +public: + + SuspendTestDeferred() { + m_name = "SuspendTestDeferred"; + m_description = "This test will send data on a suspended pipe(Deferred context) "; + Register(*this); + } + + bool Setup() + { + bool bRetVal = true; + + /*Set the configuration to support USB->IPA and IPA->USB pipes.*/ + ConfigureScenario(IPA_TEST_CONFIGURATION_19); + + RegSuspendHandler(true,true,0); + + /*Initialize the pipe for all the tests - + * this will open the inode which represents the pipe. + */ + bRetVal &= m_IpaToUsbPipe.Init(); + bRetVal &= m_UsbToIpaPipe.Init(); + return bRetVal; + } +}; + + +class SuspendTest: public IPAInterruptsTestFixture { +public: + + SuspendTest() { + m_name = "SuspendTest"; + m_description = "This test will send data on a suspended pipe"; + Register(*this); + } + + bool Setup() + { + bool bRetVal = true; + + /*Set the configuration to support USB->IPA and IPA->USB pipes.*/ + ConfigureScenario(IPA_TEST_CONFIGURATION_19); + + RegSuspendHandler(false,true,0); + + /*Initialize the pipe for all the tests - + * this will open the inode which represents the pipe. + */ + bRetVal &= m_IpaToUsbPipe.Init(); + bRetVal &= m_UsbToIpaPipe.Init(); + return bRetVal; + } +}; + +static SuspendTest suspendTest; +static SuspendTestDeferred suspendTestDeferred; +///////////////////////////////////////////////////////////////////////////////// +// EOF //// +///////////////////////////////////////////////////////////////////////////////// diff --git a/qcom/opensource/dataipa/kernel-tests/IPv4Packet.cpp b/qcom/opensource/dataipa/kernel-tests/IPv4Packet.cpp new file mode 100644 index 0000000000..62aa2082f8 --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/IPv4Packet.cpp @@ -0,0 +1,409 @@ +/* + * Copyright (c) 2017-2018 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "TestsUtils.h" +#include "IPv4Packet.h" +#include "memory.h" + +using namespace IPA; + +static const unsigned char TCP_IP_PACKET_DUMP[] = { 0x45, // IPv4, IHL = 5 + 0x00, // ToS = 0 + 0x00, 0x28, // Total length + 0x11, 0xc2, // ID + 0x40, 0x00, //ID + Fragment Offset + 0x80, // TTL + 0x06, // Protocol = TCP + 0x70, 0x3a, //Checksum + 0x0a, 0x05, 0x07, 0x46, // Source IP 10.5.7.70 + 0x81, 0x2e, 0xe6, 0x5a, // Destination IP 129.46.230.90 + 0xf3, 0xa2, // Source Port 62370 + 0x01, 0xbd, // Destination Port 445 + 0x26, 0x26, 0x1d, 0x7d, // Seq Number + 0x15, 0xaa, 0xbc, 0xdb, // Ack Num + 0x50, 0x10, 0x80, 0xd4, // TCP Params + 0xaa, 0xa3, // TCP Checksum + 0x00, 0x00 // Urgent PTR + }; + +static const unsigned char UDP_IP_PACKET_DUMP[] = { + 0x45, // IPv4, IHL = 5 + 0x00, // ToS = 0 + 0x00, + 0x34, // Total Length + 0x12, + 0xa2, // ID + 0x00, + 0x00, //ID + fragment offset + 0x80, // TTL + 0x11, // Protocol = UDP + 0xe4, + 0x92, // Checksum + 0x0a, 0x05, 0x07, + 0x46, // Source IP 10.5.7.70 + 0x0a, 0x2b, 0x28, + 0x0f, // Destination IP 10.43.40.15 + 0x03, + 0x4a, // Source port 842 + 0x1b, + 0x4f, // Destination Port 6991 + 0x00, + 0x20, // UDP length + 0x36, + 0xac, // UDP checksum + 0x00, 0x05, 0x20, + 0x6d, // Data + 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x01, 0x13, 0x05, 0x20, 0x6c }; +static unsigned char ICMP_IP_PACKET_DUMP[] = { + //IP + 0x45, 0x00, 0x00, 0xdc, 0x03, 0xfe, 0x00, 0x00, 0x80, 0x01, 0x00, 0x00, + 0x81, 0x2e, 0xe4, 0xf6, 0x81, 0x2e, 0xe6, 0xd4, + //ICMP + 0x00, 0x00, 0xa9, 0xcd, 0x28, 0xa3, 0x01, 0x00, + //DATA + 0xee, 0x7c, 0xf7, 0x90, 0x39, 0x06, 0xd4, 0x41, 0x51, 0x51, 0x51, 0x51, + 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, + 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, + 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, + 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, + 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, + 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, + 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, + 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, + 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, + 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, + 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, + 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, + 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, + 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, + 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51 }; + +static void LittleToBigEndianUint32(unsigned char *pBigEndianBuffer, + unsigned int nUint32LittleEndianValue) { + unsigned char nLsb = nUint32LittleEndianValue & 0xff; + unsigned char nLsbMsbLow = (nUint32LittleEndianValue >> 8) & 0xff; + unsigned char nLsbMsbHigh = (nUint32LittleEndianValue >> 16) & 0xff; + unsigned char nMsb = (nUint32LittleEndianValue >> 24) & 0xff; + + pBigEndianBuffer[0] = nMsb; + pBigEndianBuffer[1] = nLsbMsbHigh; + pBigEndianBuffer[2] = nLsbMsbLow; + pBigEndianBuffer[3] = nLsb; +} + +static unsigned short BigToLittleEndianUint16(unsigned char *pBigEndianStart) { + unsigned char nMsb = pBigEndianStart[0]; + unsigned char nLsb = pBigEndianStart[1]; + + return (nMsb << 8 | nLsb << 0); +} + +static unsigned int BigToLittleEndianUint32(unsigned char *pBigEndianStart) { + unsigned char nMsb = pBigEndianStart[0]; + unsigned char nMsbLsbHigh = pBigEndianStart[1]; + unsigned char nMsbLsbLow = pBigEndianStart[2]; + unsigned char nLsb = pBigEndianStart[3]; + + return (nMsb << 24 | nMsbLsbHigh << 16 | nMsbLsbLow << 8 | nLsb << 0); +} + +static void LittleToBigEndianUint16(unsigned char *pBigEndianBuffer, + unsigned int nUint16LittleEndianValue) { + unsigned char nLsb = nUint16LittleEndianValue & 0xff; + unsigned char nMsb = (nUint16LittleEndianValue >> 8) & 0xff; + + pBigEndianBuffer[0] = nMsb; + pBigEndianBuffer[1] = nLsb; +} + +static unsigned short Get2BBIGEndian(const unsigned char *pBuff, int offset) { + unsigned char upperByte = 0; + unsigned char lowerByte = 0; + + memcpy(&upperByte, pBuff + offset, 1); + memcpy(&lowerByte, pBuff + offset + 1, 1); + + return (upperByte << 8 | lowerByte); +} + +IPv4Packet::IPv4Packet(unsigned int size) : + m_PacketSize(size) { +} + +IPv4Packet::~IPv4Packet(void) { + if (0 != m_Packet) { + delete[] m_Packet; + m_Packet = 0; + } +} + +void IPv4Packet::ToNetworkByteStream(unsigned char *buffer) { + if (0 == buffer) { + LOG_MSG_ERROR("IPv4Packet::ToNetworkByteStream : NULL arguments"); + return; + } + + memcpy(buffer, m_Packet, GetSize()); +} + +unsigned int IPv4Packet::GetSrcAddr(void) { + return BigToLittleEndianUint32(m_Packet + 12); +} + +void IPv4Packet::SetSrcAddr(unsigned int addr) { + LittleToBigEndianUint32(m_Packet + 12, addr); + RecalculateChecksum(); +} + +unsigned int IPv4Packet::GetDstAddr(void) { + + return BigToLittleEndianUint32(m_Packet + 16); +} + +void IPv4Packet::SetDstAddr(unsigned int addr) { + LittleToBigEndianUint32(m_Packet + 16, addr); + RecalculateChecksum(); +} + +unsigned char IPv4Packet::GetProtocol(void) { + unsigned char retVal = 0; + memcpy(&retVal, m_Packet + 9, sizeof(unsigned char)); + return retVal; +} + +unsigned short IPv4Packet::GetSrcPort(void) { + return BigToLittleEndianUint16(m_Packet + 20); +} + +unsigned short IPv4Packet::GetDstPort(void) { + return BigToLittleEndianUint16(m_Packet + 22); +} + +void IPv4Packet::SetDstPort(unsigned short port) { + + LittleToBigEndianUint16(m_Packet + 22, port); + RecalculateChecksum(); +} + +void IPv4Packet::SetSrcPort(unsigned short port) { + LittleToBigEndianUint16(m_Packet + 20, port); + RecalculateChecksum(); +} + +/////////////////////////////////////////////////////////////////////////////// + +//Set the third MSB bit of the IPV4_FLAGS_BYTE_OFFSET's byte +void IPv4Packet::SetMF(bool bValue) { + + Byte * pFlags = m_Packet + IPV4_FLAGS_BYTE_OFFSET; + //clear the bit + if (true == bValue) { + *pFlags |= (0x20); + } else { + *pFlags &= (~0x20); + } +} + +/////////////////////////////////////////////////////////////////////////////// + +void IPv4Packet::RecalculateChecksum(void) { + RecalculateIPChecksum(); + RecalculateTCPChecksum(); + RecalculateUDPChecksum(); +} + +void IPv4Packet::RecalculateIPChecksum(void) { + unsigned short pUint16[100]; + int headerLen = (m_Packet[0] & 0x0F) * 2; + int checksum = 0; + unsigned short result = 0; + + memset(&pUint16, 0, 100 * sizeof(unsigned short)); + + //clear the IP checksum field first + memset(m_Packet + 10, 0, sizeof(unsigned short)); + + memcpy(&pUint16, m_Packet, headerLen * sizeof(unsigned short)); + + for (int i = 0; i < headerLen; i++) { + checksum += pUint16[i]; + checksum = (checksum & 0xFFFF) + (checksum >> 16); + } + + result = (~checksum & 0xFFFF); + + memcpy(m_Packet + 10, &result, sizeof(unsigned short)); + + return; +} + +void TCPPacket::RecalculateTCPChecksum(void) { + unsigned short *pUint16 = new unsigned short[100]; + int checksum = 0; + int headerLen = 0; + unsigned short *pTemp = 0; + unsigned short result = 0; + + headerLen = Get2BBIGEndian(m_Packet, 2) - (m_Packet[0] & 0x0F) * 4; + + memset(pUint16, 0, 100); + + //clear the TCP checksum field first + memset(m_Packet + 36, 0, sizeof(unsigned short)); + + memcpy(pUint16, m_Packet, headerLen * sizeof(unsigned short)); + + pTemp = pUint16; + + // Pseudo Header + pUint16 += 6; // Source IP + for (int i = 0; i < 4; i++) { + checksum += pUint16[i]; + checksum = (checksum & 0xFFFF) + (checksum >> 16); + } + + checksum += 0x0600; // TCP Protocol + checksum += Get2BBIGEndian((unsigned char*) &headerLen, 0); + + pUint16 = pTemp + (m_Packet[0] & 0x0F) * 2; + headerLen /= 2; + for (int i = 0; i < headerLen; i++) { + checksum += pUint16[i]; + checksum = (checksum & 0xFFFF) + (checksum >> 16); + } + + result = (~checksum & 0xFFFF); + + memcpy(m_Packet + 36, &result, sizeof(unsigned short)); + + delete[] pTemp; + + return; +} + +void UDPPacket::RecalculateUDPChecksum(void) { + unsigned short *pUint16 = new unsigned short[100]; + int checksum = 0; + int headerLen = 0; + unsigned short *pTemp = 0; + unsigned short result = 0; + + headerLen = Get2BBIGEndian(m_Packet, (m_Packet[0] & 0x0F) * 4 + 4); + + memset(pUint16, 0, 100); + + //clear the UDP checksum field first + memset(m_Packet + 26, 0, sizeof(unsigned short)); + + memcpy(pUint16, m_Packet, headerLen * sizeof(unsigned short)); + + pTemp = pUint16; + + // Pseudo Header + pUint16 += 6; // Source IP + for (int i = 0; i < 4; i++) { + checksum += pUint16[i]; + checksum = (checksum & 0xFFFF) + (checksum >> 16); + } + + checksum += 0x1100; // UDP Protocol + checksum += Get2BBIGEndian((unsigned char*) &headerLen, 0); + + pUint16 = pTemp + (m_Packet[0] & 0x0F) * 2; + headerLen /= 2; + for (int i = 0; i < headerLen; i++) { + checksum += pUint16[i]; + checksum = (checksum & 0xFFFF) + (checksum >> 16); + } + + result = (~checksum & 0xFFFF); + + memcpy(m_Packet + 26, &result, sizeof(unsigned short)); + + delete[] pTemp; + return; +} + +TCPPacket::TCPPacket(void) : + IPv4Packet(sizeof(TCP_IP_PACKET_DUMP)) { + size_t length = GetSize(); + + m_Packet = new unsigned char[length]; + if (0 == m_Packet) { + LOG_MSG_ERROR("TCPPacket : packet allocation failed"); + return; + } + + memcpy(m_Packet, TCP_IP_PACKET_DUMP, length); +} + +UDPPacket::UDPPacket(void) : + IPv4Packet(sizeof(UDP_IP_PACKET_DUMP)) { + size_t length = GetSize(); + + m_Packet = new unsigned char[length]; + if (0 == m_Packet) { + LOG_MSG_ERROR("UDPPacket : packet allocation failed"); + return; + } + + memcpy(m_Packet, UDP_IP_PACKET_DUMP, length); +} + +ICMPPacket::ICMPPacket(void) : + IPv4Packet(sizeof(ICMP_IP_PACKET_DUMP)) { + size_t length = GetSize(); + + m_Packet = new unsigned char[length]; + if (0 == m_Packet) { + LOG_MSG_ERROR("ICMPPacket : packet allocation failed"); + return; + } + + memcpy(m_Packet, ICMP_IP_PACKET_DUMP, length); +} + +unsigned short ICMPPacket::GetSrcPort(void) { + return 0; +} + +unsigned short ICMPPacket::GetDstPort(void) { + return 0; +} + +void ICMPPacket::SetDstPort(unsigned short port) { + (void) port; + return; +} + +void ICMPPacket::SetSrcPort(unsigned short port) { + (void) port; + return; +} diff --git a/qcom/opensource/dataipa/kernel-tests/IPv4Packet.h b/qcom/opensource/dataipa/kernel-tests/IPv4Packet.h new file mode 100644 index 0000000000..07ae954401 --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/IPv4Packet.h @@ -0,0 +1,215 @@ +/* + * Copyright (c) 2017 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Changes from Qualcomm Innovation Center are provided under the following license: + * + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * * Neither the name of Qualcomm Innovation Center, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + */ + +#ifndef __IPA_TESTS_IPV4_PACKET__H__ +#define __IPA_TESTS_IPV4_PACKET__H__ + +namespace IPA +{ + +#define IPV4_FLAGS_BYTE_OFFSET 6 + +/** + @brief + IPv4Packet abstract class. + + @details + new setters should call to RecalculateChecksum(); + */ +class IPv4Packet +{ +public: + + IPv4Packet(unsigned int size); + + virtual ~IPv4Packet(void); + + void FromByteStream(unsigned char *buffer, unsigned int length); + + void ToNetworkByteStream(unsigned char *addr); + + unsigned int GetSrcAddr(void); + + void SetSrcAddr(unsigned int addr); + + unsigned int GetDstAddr(void); + + void SetDstAddr(unsigned int addr); + + unsigned char GetProtocol(void); + + unsigned int GetSize(void) + { + return m_PacketSize; + } + + virtual unsigned short GetSrcPort(void); + + virtual unsigned short GetDstPort(void); + + virtual void SetDstPort(unsigned short port); + + virtual void SetSrcPort(unsigned short port); + + void SetMF(bool bValue); + +protected: + + virtual void RecalculateTCPChecksum(void) {} + + virtual void RecalculateUDPChecksum(void) {} + + virtual void RecalculateICMPChecksum(void) {} + + unsigned char *m_Packet; + +private: + + unsigned int m_PacketSize; + + void RecalculateChecksum(void); + + void RecalculateIPChecksum(void); +}; + +/** + @brief + TCPPacket implementation. + + @details + new setters should call to RecalculateChecksum(); + */ +class TCPPacket:public IPv4Packet +{ +public: + + TCPPacket(void); + + virtual ~TCPPacket(void) {} + +protected: + + virtual void RecalculateTCPChecksum(void); +}; + +/** + @brief + UDPPacket implementation. + + @details + new setters should call to RecalculateChecksum(); + */ +class UDPPacket:public IPv4Packet +{ +public: + UDPPacket(void); + + virtual ~UDPPacket(void) {} + +protected: + + virtual void RecalculateUDPChecksum(void); +}; + +/** + @brief + ICMPPacket implementation. + + @details + new setters should call to RecalculateChecksum(); + */ +class ICMPPacket:public IPv4Packet +{ +public: + ICMPPacket(void); + + virtual ~ICMPPacket(void) {} + + virtual unsigned short GetSrcPort(void); + + virtual unsigned short GetDstPort(void); + + virtual void SetDstPort(unsigned short port); + + virtual void SetSrcPort(unsigned short port); + +protected: + + /** + @brief + RecalculateICMPChecksum method. + + @details + ICMP checksum recalculation is not needed now + and by so is not implemented yet + TODO: implement if needed + */ + virtual void RecalculateICMPChecksum(void) + { + return; + } +}; + +} /* namespace IPA */ + +#endif diff --git a/qcom/opensource/dataipa/kernel-tests/IPv6CTTest.cpp b/qcom/opensource/dataipa/kernel-tests/IPv6CTTest.cpp new file mode 100644 index 0000000000..e1bbfdf202 --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/IPv6CTTest.cpp @@ -0,0 +1,2439 @@ +/* + * Copyright (c) 2018 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include // for memcpy +#include "hton.h" // for htonl +#include "InterfaceAbstraction.h" +#include "Constants.h" +#include "Logger.h" +#include "TestsUtils.h" +#include "Filtering.h" +#include "RoutingDriverWrapper.h" +#include "IPAFilteringTable.h" +extern "C" { +#include "ipa_ipv6ct.h" +} + +#define IPV6_SRC_PORT_OFFSET (40) +#define IPV6_SRC_ADDRESS_MSB_OFFSET (8) +#define IPV6_SRC_ADDRESS_LSB_OFFSET (16) +#define IPV6_DST_ADDRESS_MSB_OFFSET (24) +#define IPV6_DST_ADDRESS_LSB_OFFSET (32) +#define IPV6_DST_PORT_OFFSET (40+2) + +#define IPV6_LOW_32_MASK (0xFFFFFFFF) +#define IPV6_HIGH_32_MASK (0xFFFFFFFF00000000) + +#define IPV6_BITS_IN_BYTE 8 + +inline uint32_t GetHigh32(uint64_t in) +{ + return static_cast((in & IPV6_HIGH_32_MASK) >> 32); +} + +inline uint32_t GetLow32(uint64_t in) +{ + return static_cast(in & IPV6_LOW_32_MASK); +} + +template +T HostToNetwork(T in) +{ + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + if (1 == htons(1)) + { + return in; + } + + static const T mask = 0xff; + T ret; + uint8_t* p = reinterpret_cast(&ret + 1); + while (in) + { + *--p = static_cast(in & mask); + in >>= IPV6_BITS_IN_BYTE; + } + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return ret; +} + +extern Logger g_Logger; + +class IpaIPv6CTBlockTestFixture : public TestBase +{ +public: + + IpaIPv6CTBlockTestFixture() : + m_sendSize(BUFF_MAX_SIZE), + m_sendSize2(BUFF_MAX_SIZE), + m_sendSize3(BUFF_MAX_SIZE), + m_outbound_dst_addr_msb(0XFF02000000000000), + m_outbound_dst_addr_lsb(0x11223344556677AA), + m_outbound_dst_port(1000), + m_outbound_src_addr_msb(m_outbound_dst_addr_msb), + m_outbound_src_addr_lsb(0x11223344556677CC), + m_outbound_src_port(1001), + m_direction_settings(IPA_IPV6CT_DIRECTION_ALLOW_ALL), + m_tableHandle(0) + { + memset(m_sendBuffer, 0, sizeof(m_sendBuffer)); // First input file / IP packet + memset(m_sendBuffer2, 0, sizeof(m_sendBuffer2)); // Second input file / IP packet + memset(m_sendBuffer3, 0, sizeof(m_sendBuffer3)); // Third input file (default) / IP packet + m_minIPAHwType = IPA_HW_v4_0; + m_testSuiteName.push_back("IPv6CT"); + } + + static int SetupKernelModule(bool en_status = false, bool ct_suppress = false) + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + int retval; + struct ipa_channel_config from_ipa_channels[3]; + struct test_ipa_ep_cfg from_ipa_cfg[3]; + struct ipa_channel_config to_ipa_channels[1]; + struct test_ipa_ep_cfg to_ipa_cfg[1]; + + struct ipa_test_config_header header = { 0 }; + struct ipa_channel_config *to_ipa_array[1]; + struct ipa_channel_config *from_ipa_array[3]; + + /* From ipa configurations - 3 pipes */ + memset(&from_ipa_cfg[0], 0, sizeof(from_ipa_cfg[0])); + prepare_channel_struct(&from_ipa_channels[0], + header.from_ipa_channels_num++, + IPA_CLIENT_TEST2_CONS, + (void *)&from_ipa_cfg[0], + sizeof(from_ipa_cfg[0]), + en_status); + from_ipa_array[0] = &from_ipa_channels[0]; + + memset(&from_ipa_cfg[1], 0, sizeof(from_ipa_cfg[1])); + prepare_channel_struct(&from_ipa_channels[1], + header.from_ipa_channels_num++, + IPA_CLIENT_TEST3_CONS, + (void *)&from_ipa_cfg[1], + sizeof(from_ipa_cfg[1]), + en_status); + from_ipa_array[1] = &from_ipa_channels[1]; + + memset(&from_ipa_cfg[2], 0, sizeof(from_ipa_cfg[2])); + prepare_channel_struct(&from_ipa_channels[2], + header.from_ipa_channels_num++, + IPA_CLIENT_TEST4_CONS, + (void *)&from_ipa_cfg[2], + sizeof(from_ipa_cfg[2]), + en_status); + from_ipa_array[2] = &from_ipa_channels[2]; + + /* To ipa configurations - 1 pipes */ + memset(&to_ipa_cfg[0], 0, sizeof(to_ipa_cfg[0])); + to_ipa_cfg[0].nat.nat_exc_suppress = ct_suppress; + prepare_channel_struct(&to_ipa_channels[0], + header.to_ipa_channels_num++, + IPA_CLIENT_TEST_PROD, + (void *)&to_ipa_cfg[0], + sizeof(to_ipa_cfg[0])); + to_ipa_array[0] = &to_ipa_channels[0]; + + prepare_header_struct(&header, from_ipa_array, to_ipa_array); + + retval = GenericConfigureScenario(&header); + + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return retval; + } + + bool Setup(bool en_status = false, bool ct_suppress = false) + { + bool bRetVal = true; + + if (SetupKernelModule(en_status,ct_suppress) != true) + return bRetVal; + + m_producer.Open(INTERFACE0_TO_IPA_DATA_PATH, INTERFACE0_FROM_IPA_DATA_PATH); + + m_consumer.Open(INTERFACE1_TO_IPA_DATA_PATH, INTERFACE1_FROM_IPA_DATA_PATH); + m_consumer2.Open(INTERFACE2_TO_IPA_DATA_PATH, INTERFACE2_FROM_IPA_DATA_PATH); + m_defaultConsumer.Open(INTERFACE3_TO_IPA_DATA_PATH, INTERFACE3_FROM_IPA_DATA_PATH); + + if (!m_routing.DeviceNodeIsOpened()) + { + printf("Routing block is not ready for immediate commands!\n"); + return false; + } + + if (!m_filtering.DeviceNodeIsOpened()) + { + printf("Filtering block is not ready for immediate commands!\n"); + return false; + } + m_routing.Reset(IPA_IP_v4); // This will issue a Reset command to the Filtering as well + m_routing.Reset(IPA_IP_v6); // This will issue a Reset command to the Filtering as well + return true; + } // Setup() + + bool Teardown() + { + ipa_ipv6ct_dump_table(m_tableHandle); + ipa_ipv6ct_del_tbl(m_tableHandle); + + m_producer.Close(); + m_consumer.Close(); + m_consumer2.Close(); + m_defaultConsumer.Close(); + + return true; + } // Teardown() + + bool LoadFiles() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + + if (!LoadDefaultPacket(IPA_IP_v6, m_extHdrType, m_sendBuffer, m_sendSize)) + { + LOG_MSG_ERROR("Failed default Packet\n"); + return false; + } + printf("Loaded %zu Bytes to Buffer 1\n", m_sendSize); + + if (!LoadDefaultPacket(IPA_IP_v6, m_extHdrType, m_sendBuffer2, m_sendSize2)) + { + LOG_MSG_ERROR("Failed default Packet\n"); + return false; + } + printf("Loaded %zu Bytes to Buffer 2\n", m_sendSize2); + + if (!LoadDefaultPacket(IPA_IP_v6, m_extHdrType, m_sendBuffer3, m_sendSize3)) + { + LOG_MSG_ERROR("Failed default Packet\n"); + return false; + } + printf("Loaded %zu Bytes to Buffer 3\n", m_sendSize3); + + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return true; + } + + // This function creates three IPv6 bypass routing entries and commits them. + bool CreateThreeIPv6BypassRoutingTables(const char * bypass0, const char * bypass1, const char * bypass2) + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + struct ipa_ioc_add_rt_rule *rt_rule0 = 0, *rt_rule1 = 0, *rt_rule2 = 0; + struct ipa_rt_rule_add *rt_rule_entry; + + rt_rule0 = (struct ipa_ioc_add_rt_rule *) + calloc(1, + sizeof(struct ipa_ioc_add_rt_rule) + + 1 * sizeof(struct ipa_rt_rule_add) + ); + if (!rt_rule0) { + printf("calloc failed to allocate rt_rule0 in %s\n", __FUNCTION__); + return false; + } + rt_rule1 = (struct ipa_ioc_add_rt_rule *) + calloc(1, + sizeof(struct ipa_ioc_add_rt_rule) + + 1 * sizeof(struct ipa_rt_rule_add) + ); + if (!rt_rule1) { + printf("calloc failed to allocate rt_rule1 in %s\n", __FUNCTION__); + Free(rt_rule0); + return false; + } + rt_rule2 = (struct ipa_ioc_add_rt_rule *) + calloc(1, + sizeof(struct ipa_ioc_add_rt_rule) + + 1 * sizeof(struct ipa_rt_rule_add) + ); + if (!rt_rule2) { + printf("calloc failed to allocate rt_rule2 in %s\n", __FUNCTION__); + Free(rt_rule0); + Free(rt_rule1); + return false; + } + + rt_rule0->num_rules = 1; + rt_rule0->ip = IPA_IP_v6; + rt_rule0->commit = true; + strlcpy(rt_rule0->rt_tbl_name, bypass0, sizeof(rt_rule0->rt_tbl_name)); + + rt_rule_entry = &rt_rule0->rules[0]; + rt_rule_entry->at_rear = false; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST2_CONS; + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v6.dst_addr[0] = 0xaabbccdd; + rt_rule_entry->rule.attrib.u.v6.dst_addr[1] = 0xeeff0011; + rt_rule_entry->rule.attrib.u.v6.dst_addr[2] = 0x22334455; + rt_rule_entry->rule.attrib.u.v6.dst_addr[3] = 0x66778899; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[0] = 0x00000000;// All Packets will get a "Hit" + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[1] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[2] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[3] = 0x00000000; + if (false == m_routing.AddRoutingRule(rt_rule0)) + { + printf("Routing rule addition(rt_rule0) failed!\n"); + Free(rt_rule2); + Free(rt_rule1); + Free(rt_rule0); + return false; + } + + + rt_rule1->num_rules = 1; + rt_rule1->ip = IPA_IP_v6; + rt_rule1->commit = true; + strlcpy(rt_rule1->rt_tbl_name, bypass1, sizeof(rt_rule1->rt_tbl_name)); + rt_rule_entry = &rt_rule1->rules[0]; + rt_rule_entry->at_rear = false; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST3_CONS; + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v6.dst_addr[0] = 0xaabbccdd; + rt_rule_entry->rule.attrib.u.v6.dst_addr[1] = 0xeeff0011; + rt_rule_entry->rule.attrib.u.v6.dst_addr[2] = 0x22334455; + rt_rule_entry->rule.attrib.u.v6.dst_addr[3] = 0x66778899; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[0] = 0x00000000;// All Packets will get a "Hit" + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[1] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[2] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[3] = 0x00000000; + if (false == m_routing.AddRoutingRule(rt_rule1)) + { + printf("Routing rule addition(rt_rule1) failed!\n"); + Free(rt_rule2); + Free(rt_rule1); + Free(rt_rule0); + return false; + } + + + rt_rule2->num_rules = 1; + rt_rule2->ip = IPA_IP_v6; + rt_rule2->commit = true; + strlcpy(rt_rule2->rt_tbl_name, bypass2, sizeof(rt_rule2->rt_tbl_name)); + rt_rule_entry = &rt_rule2->rules[0]; + rt_rule_entry->at_rear = false; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST4_CONS; + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v6.dst_addr[0] = 0xaabbccdd; + rt_rule_entry->rule.attrib.u.v6.dst_addr[1] = 0xeeff0011; + rt_rule_entry->rule.attrib.u.v6.dst_addr[2] = 0x22334455; + rt_rule_entry->rule.attrib.u.v6.dst_addr[3] = 0x66778899; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[0] = 0x00000000;// All Packets will get a "Hit" + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[1] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[2] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[3] = 0x00000000; + if (false == m_routing.AddRoutingRule(rt_rule2)) + { + printf("Routing rule addition(rt_rule2) failed!\n"); + Free(rt_rule2); + Free(rt_rule1); + Free(rt_rule0); + return false; + } + + + Free(rt_rule2); + Free(rt_rule1); + Free(rt_rule0); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return true; + } + + bool GetThreeIPv6BypassRoutingTables(uint32_t *Hndl0, uint32_t *Hndl1, uint32_t *Hndl2) + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + struct ipa_ioc_get_rt_tbl routing_table0, routing_table1, routing_table2; + + if (!CreateThreeIPv6BypassRoutingTables(bypass0, bypass1, bypass2)) + { + printf("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + + printf("CreateThreeBypassRoutingTables completed successfully\n"); + routing_table0.ip = IPA_IP_v6; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + printf("m_routing.GetRoutingTable(&routing_table0=0x%pK) Failed.\n", &routing_table0); + return false; + } + routing_table1.ip = IPA_IP_v6; + strlcpy(routing_table1.name, bypass1, sizeof(routing_table1.name)); + if (!m_routing.GetRoutingTable(&routing_table1)) + { + printf("m_routing.GetRoutingTable(&routing_table1=0x%pK) Failed.\n", &routing_table1); + return false; + } + + routing_table2.ip = IPA_IP_v6; + strlcpy(routing_table2.name, bypass2, sizeof(routing_table2.name)); + if (!m_routing.GetRoutingTable(&routing_table2)) + { + printf("m_routing.GetRoutingTable(&routing_table2=0x%pK) Failed.\n", &routing_table2); + return false; + } + + *Hndl0 = routing_table0.hdl; + *Hndl1 = routing_table1.hdl; + *Hndl2 = routing_table2.hdl; + + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return true; + } + + bool AddIpv6ctTable() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + const int total_entries = 20; + + int result = ipa_ipv6ct_add_tbl(total_entries, &m_tableHandle); + if (result) + { + printf("Leaving %s, %s(), failed creating IPvC6T table with result %d\n", __FUNCTION__, __FILE__, result); + return false; + } + + printf("IPv6CT table added, hdl %d\n", m_tableHandle); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return true; + } + + bool AddIpv6ctRule(ipa_ipv6ct_rule& rule, uint32_t& rule_hdl) const + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + + int result = ipa_ipv6ct_add_rule(m_tableHandle, &rule, &rule_hdl); + if (result) + { + printf("Leaving %s, %s(), failed creating IPvC6T rule with result %d\n", __FUNCTION__, __FILE__, result); + return false; + } + printf("IPv6CT rule added:\ndest lsb %llX, dest msb %llX, dest port %d\ndir %d, proto %d\nsrc lsb 0x%llX, src msb 0x%llX, src port %d\n", + (long long unsigned int)rule.dest_ipv6_lsb, (long long unsigned int)rule.dest_ipv6_msb, + rule.dest_port, rule.direction_settings, + rule.protocol, (long long unsigned int)rule.src_ipv6_lsb, (long long unsigned int)rule.src_ipv6_msb, + rule.src_port); + + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return true; + } + + void InitIpv6ctRule(ipa_ipv6ct_rule& rule, uint64_t change_bit) const + { + rule.dest_ipv6_lsb = m_outbound_dst_addr_lsb ^ change_bit; + rule.dest_ipv6_msb = m_outbound_dst_addr_msb; + rule.dest_port = m_outbound_dst_port; + rule.direction_settings = m_direction_settings; + rule.protocol = IPPROTO_TCP; + rule.src_ipv6_lsb = m_outbound_src_addr_lsb ^ change_bit; + rule.src_ipv6_msb = m_outbound_src_addr_msb; + rule.src_port = m_outbound_src_port; + } + + virtual bool AddIpv6ctRules() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + + ipa_ipv6ct_rule rule; + InitIpv6ctRule(rule, 0); + + uint32_t rule_hdl; + bool result = AddIpv6ctRule(rule, rule_hdl); + + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return result; + } + + virtual bool ModifyPackets() = 0; + virtual bool AddRoutingFilteringRules() = 0; + virtual bool ReceivePacketsAndCompare() = 0; + + bool Run() + { + bool res = false; + bool isSuccess = false; + + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + + res = AddRoutingFilteringRules(); + if (false == res) { + printf("Failed adding routing and filtering rules.\n"); + return false; + } + + res = AddIpv6ctTable(); + if (false == res) + { + printf("Failed adding IPv6 connection tracking table.\n"); + return false; + } + + res = AddIpv6ctRules(); + if (false == res) + { + printf("Failed adding IPv6 connection tracking rules.\n"); + return false; + } + + res = LoadFiles(); + if (false == res) { + printf("Failed loading files.\n"); + return false; + } + + res = ModifyPackets(); + if (false == res) { + printf("Failed to modify packets.\n"); + return false; + } + + // Send first packet + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Receive packets from the channels and compare results + isSuccess = ReceivePacketsAndCompare(); + + printf("Leaving %s, %s(), Returning %d\n", __FUNCTION__, __FILE__, isSuccess); + + return isSuccess; + } // Run() + + void ModifyPackets(uint64_t dstAddrLsb, uint64_t dstAddrMsb, uint16_t dstPort, + uint64_t srcAddrLsb, uint64_t srcAddrMsb, uint16_t srcPort) + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + + // destination + uint64_t address = HostToNetwork(dstAddrLsb); + memcpy(&m_sendBuffer[IPV6_DST_ADDRESS_LSB_OFFSET], &address, sizeof(address)); + + address = HostToNetwork(dstAddrMsb); + memcpy(&m_sendBuffer[IPV6_DST_ADDRESS_MSB_OFFSET], &address, sizeof(address)); + + uint16_t port = ntohs(dstPort); + memcpy(&m_sendBuffer[IPV6_DST_PORT_OFFSET], &port, sizeof(port)); + + // source + address = HostToNetwork(srcAddrLsb); + memcpy(&m_sendBuffer[IPV6_SRC_ADDRESS_LSB_OFFSET], &address, sizeof(address)); + + address = HostToNetwork(srcAddrMsb); + memcpy(&m_sendBuffer[IPV6_SRC_ADDRESS_MSB_OFFSET], &address, sizeof(address)); + + port = ntohs(srcPort); + memcpy(&m_sendBuffer[IPV6_SRC_PORT_OFFSET], &port, sizeof(port)); + + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + }// ModifyPacktes () + + virtual bool AddRoutingFilteringRules(enum ipa_flt_action flt_action, uint64_t dst_addr_msb, uint64_t dst_addr_lsb) + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + + if (!CreateThreeIPv6BypassRoutingTables(bypass0, bypass1, bypass2)) + { + printf("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + printf("CreateThreeBypassRoutingTables completed successfully\n"); + + ipa_ioc_get_rt_tbl routing_table0; + routing_table0.ip = IPA_IP_v6; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + printf("m_routing.GetRoutingTable(&routing_table0=0x%pK) Failed.\n", &routing_table0); + return false; + } + + ipa_ioc_get_rt_tbl routing_table1; + routing_table1.ip = IPA_IP_v6; + strlcpy(routing_table1.name, bypass1, sizeof(routing_table1.name)); + if (!m_routing.GetRoutingTable(&routing_table1)) + { + printf("m_routing.GetRoutingTable(&routing_table1=0x%pK) Failed.\n", &routing_table1); + return false; + } + + IPAFilteringTable FilterTable0; + ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v6, IPA_CLIENT_TEST_PROD, false, 1); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1, flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl = -1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action = flt_action; + flt_rule_entry.rule.rt_tbl_hdl = routing_table0.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[0] = 0xFFFFFFFF;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[1] = 0xFFFFFFFF;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[2] = 0xFFFFFFFF;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[3] = 0xFFFFFFFF;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr[0] = GetHigh32(dst_addr_msb); // Filter DST_IP + flt_rule_entry.rule.attrib.u.v6.dst_addr[1] = GetLow32(dst_addr_msb); + flt_rule_entry.rule.attrib.u.v6.dst_addr[2] = GetHigh32(dst_addr_lsb); + flt_rule_entry.rule.attrib.u.v6.dst_addr[3] = GetLow32(dst_addr_lsb); + + printf("flt_rule_entry was set successfully, preparing for insertion....\n"); + + if (((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable())) + { + printf("%s::Error Adding Rule to Filter Table, aborting...\n", __FUNCTION__); + return false; + } + else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", + FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl, FilterTable0.ReadRuleFromTable(0)->status); + } + + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return true; + }// AddRoutingFilteringRules() + + virtual bool ReceivePacketsAndCompare(bool packetPassExpected) + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + + // Receive results + Byte rxBuff1[0x400]; + size_t receivedSize = m_consumer.ReceiveData(rxBuff1, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize, m_consumer.m_fromChannelName.c_str()); + + bool isSuccess = true; + if (packetPassExpected) + { + // Compare results + if (!CompareResultVsGolden(m_sendBuffer, m_sendSize, rxBuff1, receivedSize)) + { + printf("Comparison of Buffer0 Failed!\n"); + isSuccess = false; + } + } + else + { + if (receivedSize) + { + isSuccess = false; + printf("got data while expected packet to be blocked, failing\n"); + } + } + + char recievedBuffer[256] = {0}; + char SentBuffer[256] = {0}; + size_t j; + + for (j = 0; j < m_sendSize; j++) + { + snprintf(&SentBuffer[3 * j], sizeof(SentBuffer)-(3 * j + 1), " %02X", m_sendBuffer[j]); + } + + for (j = 0; j < receivedSize; j++) + { + snprintf(&recievedBuffer[3 * j], sizeof(recievedBuffer)-(3 * j + 1), " %02X", rxBuff1[j]); + } + printf("Expected Value1 (%zu)\n%s\n, Received Value1(%zu)\n%s\n", + m_sendSize, SentBuffer, receivedSize, recievedBuffer); + + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return isSuccess; + } + +protected: + + static Filtering m_filtering; + static RoutingDriverWrapper m_routing; + InterfaceAbstraction m_producer; + InterfaceAbstraction m_consumer; + InterfaceAbstraction m_consumer2; + InterfaceAbstraction m_defaultConsumer; + + static const size_t BUFF_MAX_SIZE = 1024; + + Byte m_sendBuffer[BUFF_MAX_SIZE]; // First input file / IP packet + Byte m_sendBuffer2[BUFF_MAX_SIZE]; // Second input file / IP packet + Byte m_sendBuffer3[BUFF_MAX_SIZE]; // Third input file (default) / IP packet + size_t m_sendSize; + size_t m_sendSize2; + size_t m_sendSize3; + static const ipv6_ext_hdr_type m_extHdrType = NONE; + + uint64_t m_outbound_dst_addr_msb; + uint64_t m_outbound_dst_addr_lsb; + uint16_t m_outbound_dst_port; + uint64_t m_outbound_src_addr_msb; + uint64_t m_outbound_src_addr_lsb; + uint16_t m_outbound_src_port; + ipa_ipv6_ct_direction_settings_type m_direction_settings; + + uint32_t m_tableHandle; +}; + +RoutingDriverWrapper IpaIPv6CTBlockTestFixture::m_routing; +Filtering IpaIPv6CTBlockTestFixture::m_filtering; + +/*---------------------------------------------------------------------------------------------*/ +/* Test001: IPv6CT send outbound packet */ +/*---------------------------------------------------------------------------------------------*/ +class IpaIPV6CTBlockTest001 : public IpaIPv6CTBlockTestFixture +{ +public: + + IpaIPV6CTBlockTest001() + { + m_name = "IpaIPV6CTBlockTest001"; + m_description = + "IPv6CT block test 001 - IPv6CT passes successfully one packet in outbound direction\n" + "1. Generate and commit three routing tables.\n" + " Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly))\n" + "2. Generate and commit one outbound filtering rule: Destination IP Exactly Match.\n" + "3. Add IPv6CT rule for the packet\n"; + Register(*this); + } + + virtual bool AddRoutingFilteringRules() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + bool result = IpaIPv6CTBlockTestFixture::AddRoutingFilteringRules(IPA_PASS_TO_SRC_NAT, + m_outbound_dst_addr_msb, m_outbound_dst_addr_lsb); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return result; + }// AddRoutingFilteringRules() + + virtual bool ModifyPackets() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + IpaIPv6CTBlockTestFixture::ModifyPackets(m_outbound_dst_addr_lsb, m_outbound_dst_addr_msb, m_outbound_dst_port, + m_outbound_src_addr_lsb, m_outbound_src_addr_msb, m_outbound_src_port); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return true; + }// ModifyPackets() + + virtual bool ReceivePacketsAndCompare() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + bool result = IpaIPv6CTBlockTestFixture::ReceivePacketsAndCompare(true); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return result; + } +}; + +/*---------------------------------------------------------------------------------------------*/ +/* Test002: IPv6CT send inbound packet */ +/*---------------------------------------------------------------------------------------------*/ +class IpaIPV6CTBlockTest002 : public IpaIPv6CTBlockTestFixture +{ +public: + + IpaIPV6CTBlockTest002() + { + m_name = "IpaIPV6CTBlockTest002"; + m_description = + "IPv6CT block test 002 - IPv6CT passes successfully one packet in inbound direction\n" + "1. Generate and commit three routing tables.\n" + " Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly))\n" + "2. Generate and commit one inbound filtering rule: Destination IP Exactly Match.\n" + "3. Add IPv6CT rule for the packet\n"; + Register(*this); + } + + virtual bool AddRoutingFilteringRules() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + bool result = IpaIPv6CTBlockTestFixture::AddRoutingFilteringRules(IPA_PASS_TO_DST_NAT, + m_outbound_src_addr_msb, m_outbound_src_addr_lsb); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return result; + }// AddRoutingFilteringRules() + + virtual bool ModifyPackets() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + IpaIPv6CTBlockTestFixture::ModifyPackets(m_outbound_src_addr_lsb, m_outbound_src_addr_msb, m_outbound_src_port, + m_outbound_dst_addr_lsb, m_outbound_dst_addr_msb, m_outbound_dst_port); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return true; + }// ModifyPackets() + + virtual bool ReceivePacketsAndCompare() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + bool result = IpaIPv6CTBlockTestFixture::ReceivePacketsAndCompare(true); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return result; + } +}; + +/*---------------------------------------------------------------------------------------------*/ +/* Test003: IPv6CT send outbound packet - without IPV6CT rule */ +/*---------------------------------------------------------------------------------------------*/ +class IpaIPV6CTBlockTest003 : public IpaIPv6CTBlockTestFixture +{ +public: + + IpaIPV6CTBlockTest003() + { + m_name = "IpaIPV6CTBlockTest003"; + m_description = + "IPv6CT block test 003 - IPv6CT blocks one packet in outbound direction due to rule absence\n" + "1. Generate and commit three routing tables.\n" + " Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly))\n" + "2. Generate and commit one outbound filtering rule: Destination IP Exactly Match.\n"; + Register(*this); + } + + virtual bool AddIpv6ctRules() + { + printf("not adding IPv6CT rule for packet - blocking expected %s %s\n", __FUNCTION__, __FILE__); + return true; + } + + virtual bool AddRoutingFilteringRules() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + bool result = IpaIPv6CTBlockTestFixture::AddRoutingFilteringRules(IPA_PASS_TO_SRC_NAT, + m_outbound_dst_addr_msb, m_outbound_dst_addr_lsb); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return result; + }// AddRoutingFilteringRules() + + virtual bool ModifyPackets() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + IpaIPv6CTBlockTestFixture::ModifyPackets(m_outbound_dst_addr_lsb, m_outbound_dst_addr_msb, m_outbound_dst_port, + m_outbound_src_addr_lsb, m_outbound_src_addr_msb, m_outbound_src_port); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return true; + }// ModifyPackets() + + virtual bool ReceivePacketsAndCompare() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + bool result = IpaIPv6CTBlockTestFixture::ReceivePacketsAndCompare(false); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return result; + } +}; + +/*---------------------------------------------------------------------------------------------*/ +/* Test004: IPv6CT send inbound packet - without IPV6CT rule */ +/*---------------------------------------------------------------------------------------------*/ +class IpaIPV6CTBlockTest004 : public IpaIPv6CTBlockTestFixture +{ +public: + + IpaIPV6CTBlockTest004() + { + m_name = "IpaIPV6CTBlockTest004"; + m_description = + "IPv6CT block test 004 - IPv6CT blocks one packet in inbound direction due to rule absence\n" + "1. Generate and commit three routing tables.\n" + " Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly))\n" + "2. Generate and commit one inbound filtering rule: Destination IP Exactly Match.\n"; + Register(*this); + } + + virtual bool AddIpv6ctRules() + { + printf("not adding IPv6CT rule for packet - blocking expected %s %s\n", __FUNCTION__, __FILE__); + return true; + } + + virtual bool AddRoutingFilteringRules() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + bool result = IpaIPv6CTBlockTestFixture::AddRoutingFilteringRules(IPA_PASS_TO_DST_NAT, + m_outbound_src_addr_msb, m_outbound_src_addr_lsb); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return result; + }// AddRoutingFilteringRules() + + virtual bool ModifyPackets() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + IpaIPv6CTBlockTestFixture::ModifyPackets(m_outbound_src_addr_lsb, m_outbound_src_addr_msb, m_outbound_src_port, + m_outbound_dst_addr_lsb, m_outbound_dst_addr_msb, m_outbound_dst_port); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return true; + }// ModifyPackets() + + virtual bool ReceivePacketsAndCompare() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + bool result = IpaIPv6CTBlockTestFixture::ReceivePacketsAndCompare(false); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return result; + } +}; + +/*---------------------------------------------------------------------------------------------*/ +/* Test005: IPv6CT send outbound packet with inbound filtering rule */ +/*---------------------------------------------------------------------------------------------*/ +class IpaIPV6CTBlockTest005 : public IpaIPv6CTBlockTestFixture +{ +public: + + IpaIPV6CTBlockTest005() + { + m_name = "IpaIPV6CTBlockTest005"; + m_description = + "IPv6CT block test 005 - IPv6CT blocks one packet in outbound direction, because the filtering rule\n" + " action is inbound\n" + "1. Generate and commit three routing tables.\n" + " Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly))\n" + "2. Generate and commit one inbound filtering rule: Destination IP Exactly Match.\n" + "3. Add IPv6CT rule for the packet\n"; + Register(*this); + } + + virtual bool AddRoutingFilteringRules() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + bool result = IpaIPv6CTBlockTestFixture::AddRoutingFilteringRules(IPA_PASS_TO_DST_NAT, + m_outbound_dst_addr_msb, m_outbound_dst_addr_lsb); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return result; + }// AddRoutingFilteringRules() + + virtual bool ModifyPackets() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + IpaIPv6CTBlockTestFixture::ModifyPackets(m_outbound_dst_addr_lsb, m_outbound_dst_addr_msb, m_outbound_dst_port, + m_outbound_src_addr_lsb, m_outbound_src_addr_msb, m_outbound_src_port); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return true; + }// ModifyPackets() + + virtual bool ReceivePacketsAndCompare() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + bool result = IpaIPv6CTBlockTestFixture::ReceivePacketsAndCompare(false); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return result; + } +}; + +/*---------------------------------------------------------------------------------------------*/ +/* Test006: IPv6CT send inbound packet with outbound filtering rule */ +/*---------------------------------------------------------------------------------------------*/ +class IpaIPV6CTBlockTest006 : public IpaIPv6CTBlockTestFixture +{ +public: + + IpaIPV6CTBlockTest006() + { + m_name = "IpaIPV6CTBlockTest006"; + m_description = + "IPv6CT block test 006 - IPv6CT blocks one packet in inbound direction, because the filtering rule\n" + " action is outbound\n" + "1. Generate and commit three routing tables.\n" + " Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly))\n" + "2. Generate and commit one outbound filtering rule: Destination IP Exactly Match.\n" + "3. Add IPv6CT rule for the packet\n"; + Register(*this); + } + + virtual bool AddRoutingFilteringRules() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + bool result = IpaIPv6CTBlockTestFixture::AddRoutingFilteringRules(IPA_PASS_TO_SRC_NAT, + m_outbound_src_addr_msb, m_outbound_src_addr_lsb); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return result; + }// AddRoutingFilteringRules() + + virtual bool ModifyPackets() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + IpaIPv6CTBlockTestFixture::ModifyPackets(m_outbound_src_addr_lsb, m_outbound_src_addr_msb, m_outbound_src_port, + m_outbound_dst_addr_lsb, m_outbound_dst_addr_msb, m_outbound_dst_port); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return true; + }// ModifyPackets() + + virtual bool ReceivePacketsAndCompare() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + bool result = IpaIPv6CTBlockTestFixture::ReceivePacketsAndCompare(false); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return result; + } +}; + +/*---------------------------------------------------------------------------------------------*/ +/* Test007: IPv6CT block outbound packet while disabled outbound direction */ +/*---------------------------------------------------------------------------------------------*/ +class IpaIPV6CTBlockTest007 : public IpaIPv6CTBlockTestFixture +{ +public: + + IpaIPV6CTBlockTest007() + { + m_name = "IpaIPV6CTBlockTest007"; + m_description = + "IPv6CT block test 007 - IPv6CT blocks one packet in outbound direction, because the outbound direction\n" + " is disabled\n" + "1. Generate and commit three routing tables.\n" + " Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly))\n" + "2. Generate and commit one outbound filtering rule: Destination IP Exactly Match.\n" + "3. Add IPv6CT rule for the packet with disabled outbound direction\n"; + m_direction_settings = IPA_IPV6CT_DIRECTION_ALLOW_IN; + Register(*this); + } + + virtual bool AddRoutingFilteringRules() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + bool result = IpaIPv6CTBlockTestFixture::AddRoutingFilteringRules(IPA_PASS_TO_SRC_NAT, + m_outbound_dst_addr_msb, m_outbound_dst_addr_lsb); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return result; + }// AddRoutingFilteringRules() + + virtual bool ModifyPackets() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + IpaIPv6CTBlockTestFixture::ModifyPackets(m_outbound_dst_addr_lsb, m_outbound_dst_addr_msb, m_outbound_dst_port, + m_outbound_src_addr_lsb, m_outbound_src_addr_msb, m_outbound_src_port); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return true; + }// ModifyPackets() + + virtual bool ReceivePacketsAndCompare() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + bool result = IpaIPv6CTBlockTestFixture::ReceivePacketsAndCompare(false); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return result; + } +}; + +/*---------------------------------------------------------------------------------------------*/ +/* Test008: IPv6CT block inbound packet with disabled inbound direction */ +/*---------------------------------------------------------------------------------------------*/ +class IpaIPV6CTBlockTest008 : public IpaIPv6CTBlockTestFixture +{ +public: + + IpaIPV6CTBlockTest008() + { + m_name = "IpaIPV6CTBlockTest008"; + m_description = + "IPv6CT block test 008 - IPv6CT blocks one packet in inbound direction, because the inbound direction\n" + " is disabled\n" + "1. Generate and commit three routing tables.\n" + " Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly))\n" + "2. Generate and commit one inbound filtering rule: Destination IP Exactly Match.\n" + "3. Add IPv6CT rule for the packet with disabled inbound direction\n"; + m_direction_settings = IPA_IPV6CT_DIRECTION_ALLOW_OUT; + Register(*this); + } + + virtual bool AddRoutingFilteringRules() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + bool result = IpaIPv6CTBlockTestFixture::AddRoutingFilteringRules(IPA_PASS_TO_DST_NAT, + m_outbound_src_addr_msb, m_outbound_src_addr_lsb); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return result; + }// AddRoutingFilteringRules() + + virtual bool ModifyPackets() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + IpaIPv6CTBlockTestFixture::ModifyPackets(m_outbound_src_addr_lsb, m_outbound_src_addr_msb, m_outbound_src_port, + m_outbound_dst_addr_lsb, m_outbound_dst_addr_msb, m_outbound_dst_port); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return true; + }// ModifyPackets() + + virtual bool ReceivePacketsAndCompare() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + bool result = IpaIPv6CTBlockTestFixture::ReceivePacketsAndCompare(false); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return result; + } +}; + +class IpaIPv6CTBlockExpansionTableTestFixture : public IpaIPv6CTBlockTestFixture +{ +public: + + virtual bool AddIpv6ctRules() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + + ipa_ipv6ct_rule rule; + InitIpv6ctRule(rule, 8); + + uint32_t rule_hdl; + if (!AddIpv6ctRule(rule, rule_hdl)) + { + return false; + } + + bool result = IpaIPv6CTBlockTestFixture::AddIpv6ctRules(); + + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return result; + } +}; + +/*---------------------------------------------------------------------------------------------*/ +/* Test009: IPv6CT send outbound packet with rule in expansion table */ +/*---------------------------------------------------------------------------------------------*/ +class IpaIPV6CTBlockTest009 : public IpaIPv6CTBlockExpansionTableTestFixture +{ +public: + + IpaIPV6CTBlockTest009() + { + m_name = "IpaIPV6CTBlockTest009"; + m_description = + "IPv6CT block test 009 - IPv6CT passes successfully one packet in outbound direction with rule in\n" + " expansion table\n" + "1. Generate and commit three routing tables.\n" + " Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly))\n" + "2. Generate and commit one outbound filtering rule: Destination IP Exactly Match.\n" + "3. Add an IPv6CT rule to occupy base table. This rule is not supposed to match a packet\n" + "4. Add IPv6CT rule for the packet to the expansion table\n"; + Register(*this); + } + + virtual bool AddRoutingFilteringRules() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + bool result = IpaIPv6CTBlockTestFixture::AddRoutingFilteringRules(IPA_PASS_TO_SRC_NAT, + m_outbound_dst_addr_msb, m_outbound_dst_addr_lsb); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return result; + }// AddRoutingFilteringRules() + + virtual bool ModifyPackets() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + IpaIPv6CTBlockTestFixture::ModifyPackets(m_outbound_dst_addr_lsb, m_outbound_dst_addr_msb, m_outbound_dst_port, + m_outbound_src_addr_lsb, m_outbound_src_addr_msb, m_outbound_src_port); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return true; + }// ModifyPackets() + + virtual bool ReceivePacketsAndCompare() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + bool result = IpaIPv6CTBlockTestFixture::ReceivePacketsAndCompare(true); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return result; + } +}; + +/*---------------------------------------------------------------------------------------------*/ +/* Test010: IPv6CT send inbound packet with rule in expansion table */ +/*---------------------------------------------------------------------------------------------*/ +class IpaIPV6CTBlockTest010 : public IpaIPv6CTBlockExpansionTableTestFixture +{ +public: + + IpaIPV6CTBlockTest010() + { + m_name = "IpaIPV6CTBlockTest010"; + m_description = + "IPv6CT block test 010 - IPv6CT passes successfully one packet in inbound direction with rule in\n" + " expansion table\n" + "1. Generate and commit three routing tables.\n" + " Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly))\n" + "2. Generate and commit one inbound filtering rule: Destination IP Exactly Match.\n" + "3. Add an IPv6CT rule to occupy base table. This rule is not supposed to match a packet\n" + "4. Add IPv6CT rule for the packet to the expansion table\n"; + Register(*this); + } + + virtual bool AddRoutingFilteringRules() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + bool result = IpaIPv6CTBlockTestFixture::AddRoutingFilteringRules(IPA_PASS_TO_DST_NAT, + m_outbound_src_addr_msb, m_outbound_src_addr_lsb); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return result; + }// AddRoutingFilteringRules() + + virtual bool ModifyPackets() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + IpaIPv6CTBlockTestFixture::ModifyPackets(m_outbound_src_addr_lsb, m_outbound_src_addr_msb, m_outbound_src_port, + m_outbound_dst_addr_lsb, m_outbound_dst_addr_msb, m_outbound_dst_port); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return true; + }// ModifyPackets() + + virtual bool ReceivePacketsAndCompare() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + bool result = IpaIPv6CTBlockTestFixture::ReceivePacketsAndCompare(true); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return result; + } +}; + +class IpaIPv6CTBlockRuleDeleteTestFixture : public IpaIPv6CTBlockTestFixture +{ +public: + + virtual bool AddIpv6ctRules() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + + ipa_ipv6ct_rule rule; + InitIpv6ctRule(rule, 0); + + uint32_t rule_hdl; + if (!AddIpv6ctRule(rule, rule_hdl)) + { + return false; + } + + int result = ipa_ipv6ct_del_rule(m_tableHandle, rule_hdl); + if (result) + { + printf("Leaving %s, %s(), failed delete IPvC6T rule %d with result %d\n", __FUNCTION__, __FILE__, + rule_hdl, result); + return false; + } + + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return true; + } +}; + +/*---------------------------------------------------------------------------------------------*/ +/* Test011: IPv6CT block outbound packet while the rule was deleted */ +/*---------------------------------------------------------------------------------------------*/ +class IpaIPV6CTBlockTest011 : public IpaIPv6CTBlockRuleDeleteTestFixture +{ +public: + + IpaIPV6CTBlockTest011() + { + m_name = "IpaIPV6CTBlockTest011"; + m_description = + "IPv6CT block test 011 - IPv6CT blocks one packet in outbound direction due to the rule deletion\n" + "1. Generate and commit three routing tables.\n" + " Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly))\n" + "2. Generate and commit one outbound filtering rule: Destination IP Exactly Match.\n" + "3. Add IPv6CT rule for the packet\n" + "4. Delete IPv6CT rule for the packet\n"; + Register(*this); + } + + virtual bool AddRoutingFilteringRules() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + bool result = IpaIPv6CTBlockTestFixture::AddRoutingFilteringRules(IPA_PASS_TO_SRC_NAT, + m_outbound_dst_addr_msb, m_outbound_dst_addr_lsb); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return result; + }// AddRoutingFilteringRules() + + virtual bool ModifyPackets() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + IpaIPv6CTBlockTestFixture::ModifyPackets(m_outbound_dst_addr_lsb, m_outbound_dst_addr_msb, m_outbound_dst_port, + m_outbound_src_addr_lsb, m_outbound_src_addr_msb, m_outbound_src_port); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return true; + }// ModifyPackets() + + virtual bool ReceivePacketsAndCompare() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + bool result = IpaIPv6CTBlockTestFixture::ReceivePacketsAndCompare(false); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return result; + } +}; + +/*---------------------------------------------------------------------------------------------*/ +/* Test012: IPv6CT block inbound packet while the rule was deleted */ +/*---------------------------------------------------------------------------------------------*/ +class IpaIPV6CTBlockTest012 : public IpaIPv6CTBlockRuleDeleteTestFixture +{ +public: + + IpaIPV6CTBlockTest012() + { + m_name = "IpaIPV6CTBlockTest012"; + m_description = + "IPv6CT block test 012 - IPv6CT blocks one packet in inbound direction due to the rule deletion\n" + "1. Generate and commit three routing tables.\n" + " Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly))\n" + "2. Generate and commit one inbound filtering rule: Destination IP Exactly Match.\n" + "3. Add IPv6CT rule for the packet\n" + "4. Delete IPv6CT rule for the packet\n"; + Register(*this); + } + + virtual bool AddRoutingFilteringRules() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + bool result = IpaIPv6CTBlockTestFixture::AddRoutingFilteringRules(IPA_PASS_TO_DST_NAT, + m_outbound_src_addr_msb, m_outbound_src_addr_lsb); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return result; + }// AddRoutingFilteringRules() + + virtual bool ModifyPackets() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + IpaIPv6CTBlockTestFixture::ModifyPackets(m_outbound_src_addr_lsb, m_outbound_src_addr_msb, m_outbound_src_port, + m_outbound_dst_addr_lsb, m_outbound_dst_addr_msb, m_outbound_dst_port); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return true; + }// ModifyPackets() + + virtual bool ReceivePacketsAndCompare() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + bool result = IpaIPv6CTBlockTestFixture::ReceivePacketsAndCompare(false); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return result; + } +}; + +class IpaIPv6CTBlockRuleDeleteExpansionTableTestFixture : public IpaIPv6CTBlockRuleDeleteTestFixture +{ +public: + + virtual bool AddIpv6ctRules() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + + ipa_ipv6ct_rule rule; + InitIpv6ctRule(rule, 8); + + uint32_t rule_hdl; + if (!AddIpv6ctRule(rule, rule_hdl)) + { + return false; + } + + bool result = IpaIPv6CTBlockRuleDeleteTestFixture::AddIpv6ctRules(); + + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return result; + } +}; + +/*---------------------------------------------------------------------------------------------*/ +/* Test013: IPv6CT block outbound packet while the rule in expansion table was deleted */ +/*---------------------------------------------------------------------------------------------*/ +class IpaIPV6CTBlockTest013 : public IpaIPv6CTBlockRuleDeleteExpansionTableTestFixture +{ +public: + + IpaIPV6CTBlockTest013() + { + m_name = "IpaIPV6CTBlockTest013"; + m_description = + "IPv6CT block test 013 - IPv6CT blocks one packet in outbound direction due to the rule deletion from\n" + " the expansion table\n" + "1. Generate and commit three routing tables.\n" + " Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly))\n" + "2. Generate and commit one outbound filtering rule: Destination IP Exactly Match.\n" + "3. Add an IPv6CT rule to occupy base table. This rule is not supposed to match a packet\n" + "4. Add IPv6CT rule for the packet to the expansion table\n" + "5. Delete IPv6CT rule for the packet from the expansion table\n"; + Register(*this); + } + + virtual bool AddRoutingFilteringRules() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + bool result = IpaIPv6CTBlockTestFixture::AddRoutingFilteringRules(IPA_PASS_TO_SRC_NAT, + m_outbound_dst_addr_msb, m_outbound_dst_addr_lsb); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return result; + }// AddRoutingFilteringRules() + + virtual bool ModifyPackets() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + IpaIPv6CTBlockTestFixture::ModifyPackets(m_outbound_dst_addr_lsb, m_outbound_dst_addr_msb, m_outbound_dst_port, + m_outbound_src_addr_lsb, m_outbound_src_addr_msb, m_outbound_src_port); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return true; + }// ModifyPackets() + + virtual bool ReceivePacketsAndCompare() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + bool result = IpaIPv6CTBlockTestFixture::ReceivePacketsAndCompare(false); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return result; + } +}; + +/*---------------------------------------------------------------------------------------------*/ +/* Test014: IPv6CT block inbound packet while the rule in expansion table was deleted */ +/*---------------------------------------------------------------------------------------------*/ +class IpaIPV6CTBlockTest014 : public IpaIPv6CTBlockRuleDeleteExpansionTableTestFixture +{ +public: + + IpaIPV6CTBlockTest014() + { + m_name = "IpaIPV6CTBlockTest014"; + m_description = + "IPv6CT block test 014 - IPv6CT blocks one packet in inbound direction due to the rule deletion from\n" + " the expansion table\n" + "1. Generate and commit three routing tables.\n" + " Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly))\n" + "2. Generate and commit one inbound filtering rule: Destination IP Exactly Match.\n" + "3. Add an IPv6CT rule to occupy base table. This rule is not supposed to match a packet\n" + "4. Add IPv6CT rule for the packet to the expansion table\n" + "5. Delete IPv6CT rule for the packet from the expansion table\n"; + Register(*this); + } + + virtual bool AddRoutingFilteringRules() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + bool result = IpaIPv6CTBlockTestFixture::AddRoutingFilteringRules(IPA_PASS_TO_DST_NAT, + m_outbound_src_addr_msb, m_outbound_src_addr_lsb); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return result; + }// AddRoutingFilteringRules() + + virtual bool ModifyPackets() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + IpaIPv6CTBlockTestFixture::ModifyPackets(m_outbound_src_addr_lsb, m_outbound_src_addr_msb, m_outbound_src_port, + m_outbound_dst_addr_lsb, m_outbound_dst_addr_msb, m_outbound_dst_port); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return true; + }// ModifyPackets() + + virtual bool ReceivePacketsAndCompare() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + bool result = IpaIPv6CTBlockTestFixture::ReceivePacketsAndCompare(false); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return result; + } +}; + +class IpaIPv6CTBlockHeadRuleDeleteTestFixture : public IpaIPv6CTBlockTestFixture +{ +public: + + virtual bool AddIpv6ctRules() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + + ipa_ipv6ct_rule rule; + InitIpv6ctRule(rule, 8); + + uint32_t rule_hdl; + if (!AddIpv6ctRule(rule, rule_hdl)) + { + return false; + } + + if (!IpaIPv6CTBlockTestFixture::AddIpv6ctRules()) + { + return false; + } + + int result = ipa_ipv6ct_del_rule(m_tableHandle, rule_hdl); + if (result) + { + printf("Leaving %s, %s(), failed delete IPvC6T rule %d with result %d\n", __FUNCTION__, __FILE__, + rule_hdl, result); + return false; + } + + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return true; + } +}; + +/*---------------------------------------------------------------------------------------------------------------*/ +/* Test015: IPv6CT send outbound packet with rule in expansion table while the rule in the list head was deleted */ +/*---------------------------------------------------------------------------------------------------------------*/ +class IpaIPV6CTBlockTest015 : public IpaIPv6CTBlockHeadRuleDeleteTestFixture +{ +public: + + IpaIPV6CTBlockTest015() + { + m_name = "IpaIPV6CTBlockTest015"; + m_description = + "IPv6CT block test 015 - IPv6CT passes successfully one packet in outbound direction with rule in\n" + " expansion table, while the list head was deleted\n" + "1. Generate and commit three routing tables.\n" + " Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly))\n" + "2. Generate and commit one outbound filtering rule: Destination IP Exactly Match.\n" + "3. Add an IPv6CT rule to occupy base table. This rule is not supposed to match a packet\n" + "4. Add IPv6CT rule for the packet to the expansion table\n" + "5. Delete IPv6CT rule in the list head\n"; + Register(*this); + } + + virtual bool AddRoutingFilteringRules() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + bool result = IpaIPv6CTBlockTestFixture::AddRoutingFilteringRules(IPA_PASS_TO_SRC_NAT, + m_outbound_dst_addr_msb, m_outbound_dst_addr_lsb); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return result; + }// AddRoutingFilteringRules() + + virtual bool ModifyPackets() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + IpaIPv6CTBlockTestFixture::ModifyPackets(m_outbound_dst_addr_lsb, m_outbound_dst_addr_msb, m_outbound_dst_port, + m_outbound_src_addr_lsb, m_outbound_src_addr_msb, m_outbound_src_port); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return true; + }// ModifyPackets() + + virtual bool ReceivePacketsAndCompare() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + bool result = IpaIPv6CTBlockTestFixture::ReceivePacketsAndCompare(true); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return result; + } +}; + +/*---------------------------------------------------------------------------------------------------------------*/ +/* Test016: IPv6CT send inbound packet with rule in expansion table while the rule in the list head was deleted */ +/*---------------------------------------------------------------------------------------------------------------*/ +class IpaIPV6CTBlockTest016 : public IpaIPv6CTBlockHeadRuleDeleteTestFixture +{ +public: + + IpaIPV6CTBlockTest016() + { + m_name = "IpaIPV6CTBlockTest016"; + m_description = + "IPv6CT block test 016 - IPv6CT passes successfully one packet in inbound direction with rule in\n" + " expansion table, while the list head was deleted\n" + "1. Generate and commit three routing tables.\n" + " Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly))\n" + "2. Generate and commit one inbound filtering rule: Destination IP Exactly Match.\n" + "3. Add an IPv6CT rule to occupy base table. This rule is not supposed to match a packet\n" + "4. Add IPv6CT rule for the packet to the expansion table\n" + "5. Delete IPv6CT rule in the list head\n"; + Register(*this); + } + + virtual bool AddRoutingFilteringRules() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + bool result = IpaIPv6CTBlockTestFixture::AddRoutingFilteringRules(IPA_PASS_TO_DST_NAT, + m_outbound_src_addr_msb, m_outbound_src_addr_lsb); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return result; + }// AddRoutingFilteringRules() + + virtual bool ModifyPackets() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + IpaIPv6CTBlockTestFixture::ModifyPackets(m_outbound_src_addr_lsb, m_outbound_src_addr_msb, m_outbound_src_port, + m_outbound_dst_addr_lsb, m_outbound_dst_addr_msb, m_outbound_dst_port); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return true; + }// ModifyPackets() + + virtual bool ReceivePacketsAndCompare() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + bool result = IpaIPv6CTBlockTestFixture::ReceivePacketsAndCompare(true); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return result; + } +}; + +class IpaIPv6CTBlockMiddleRuleDeleteTestFixture : public IpaIPv6CTBlockHeadRuleDeleteTestFixture +{ +public: + + virtual bool AddIpv6ctRules() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + + ipa_ipv6ct_rule rule; + InitIpv6ctRule(rule, 1); + + uint32_t rule_hdl; + if (!AddIpv6ctRule(rule, rule_hdl)) + { + return false; + } + + bool result = IpaIPv6CTBlockHeadRuleDeleteTestFixture::AddIpv6ctRules(); + + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return result; + } +}; + +/*------------------------------------------------------------------------------------------------------------*/ +/* Test017: IPv6CT send outbound packet with rule in expansion table while the rule in the middle of the list */ +/* was deleted */ +/*------------------------------------------------------------------------------------------------------------*/ +class IpaIPV6CTBlockTest017 : public IpaIPv6CTBlockMiddleRuleDeleteTestFixture +{ +public: + + IpaIPV6CTBlockTest017() + { + m_name = "IpaIPV6CTBlockTest017"; + m_description = + "IPv6CT block test 017 - IPv6CT passes successfully one packet in outbound direction with rule in\n" + " expansion table, while the rule in the middle of the list was deleted\n" + "1. Generate and commit three routing tables.\n" + " Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly))\n" + "2. Generate and commit one outbound filtering rule: Destination IP Exactly Match.\n" + "3. Add two IPv6CT rules: one to base table and other to expansion table. These rules are not supposed\n" + " to match a packet\n" + "4. Add IPv6CT rule for the packet to the expansion table\n" + "5. Delete IPv6CT rule in the middle of the list\n"; + Register(*this); + } + + virtual bool AddRoutingFilteringRules() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + bool result = IpaIPv6CTBlockTestFixture::AddRoutingFilteringRules(IPA_PASS_TO_SRC_NAT, + m_outbound_dst_addr_msb, m_outbound_dst_addr_lsb); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return result; + }// AddRoutingFilteringRules() + + virtual bool ModifyPackets() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + IpaIPv6CTBlockTestFixture::ModifyPackets(m_outbound_dst_addr_lsb, m_outbound_dst_addr_msb, m_outbound_dst_port, + m_outbound_src_addr_lsb, m_outbound_src_addr_msb, m_outbound_src_port); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return true; + }// ModifyPackets() + + virtual bool ReceivePacketsAndCompare() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + bool result = IpaIPv6CTBlockTestFixture::ReceivePacketsAndCompare(true); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return result; + } +}; + +/*------------------------------------------------------------------------------------------------------------*/ +/* Test018: IPv6CT send inbound packet with rule in expansion table while the rule in the middle of the list */ +/* was deleted */ +/*------------------------------------------------------------------------------------------------------------*/ +class IpaIPV6CTBlockTest018 : public IpaIPv6CTBlockMiddleRuleDeleteTestFixture +{ +public: + + IpaIPV6CTBlockTest018() + { + m_name = "IpaIPV6CTBlockTest018"; + m_description = + "IPv6CT block test 018 - IPv6CT passes successfully one packet in inbound direction with rule in\n" + " expansion table, while the rule in the middle of the list was deleted\n" + "1. Generate and commit three routing tables.\n" + " Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly))\n" + "2. Generate and commit one inbound filtering rule: Destination IP Exactly Match.\n" + "3. Add two IPv6CT rules to occupy base table and the middle of the list. These rules are not supposed\n" + " to match a packet\n" + "4. Add IPv6CT rule for the packet to the expansion table\n" + "5. Delete IPv6CT rule in the middle of the list\n"; + Register(*this); + } + + virtual bool AddRoutingFilteringRules() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + bool result = IpaIPv6CTBlockTestFixture::AddRoutingFilteringRules(IPA_PASS_TO_DST_NAT, + m_outbound_src_addr_msb, m_outbound_src_addr_lsb); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return result; + }// AddRoutingFilteringRules() + + virtual bool ModifyPackets() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + IpaIPv6CTBlockTestFixture::ModifyPackets(m_outbound_src_addr_lsb, m_outbound_src_addr_msb, m_outbound_src_port, + m_outbound_dst_addr_lsb, m_outbound_dst_addr_msb, m_outbound_dst_port); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return true; + }// ModifyPackets() + + virtual bool ReceivePacketsAndCompare() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + bool result = IpaIPv6CTBlockTestFixture::ReceivePacketsAndCompare(true); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return result; + } +}; + +/*---------------------------------------------------------------------------------------------*/ +/* Test019: IPv6CT send outbound packet, suppression test */ +/*---------------------------------------------------------------------------------------------*/ +class IpaIPV6CTBlockTest019 : public IpaIPv6CTBlockTestFixture +{ +public: + + IpaIPV6CTBlockTest019() + { + m_name = "IpaIPV6CTBlockTest019"; + m_description = + "IPv6CT block test 019 - IPv6CT passes successfully one packet in outbound direction\n" + "1. Generate and commit three routing tables.\n" + " Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly))\n" + "2. Generate and commit one outbound filtering rule: Destination IP Exactly Match.\n" + "3. Add IPv6CT rule for the packet which doesn't match\n" + "4. Expect NAT supporession to kick in and packet is routed correctly\n"; + Register(*this); + } + + virtual bool Setup() + { + /* we want statuses on this test */ + return IpaIPv6CTBlockTestFixture::Setup(false, true); + } + + virtual bool AddRoutingFilteringRules(enum ipa_flt_action flt_action, uint64_t dst_addr_msb, uint64_t dst_addr_lsb) + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + + if (!CreateThreeIPv6BypassRoutingTables(bypass0, bypass1, bypass2)) + { + printf("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + printf("CreateThreeBypassRoutingTables completed successfully\n"); + + ipa_ioc_get_rt_tbl routing_table0; + routing_table0.ip = IPA_IP_v6; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + printf("m_routing.GetRoutingTable(&routing_table0=0x%pK) Failed.\n", &routing_table0); + return false; + } + + /* Setup conntrack exception routing table. */ + if (!m_routing.SetNatConntrackExcRoutingTable(routing_table0.hdl, false)) + { + LOG_MSG_ERROR("m_routing.SetNatConntrackExcRoutingTable(routing_table0 hdl=%d) Failed.\n", + routing_table0.hdl); + return false; + } + + ipa_ioc_get_rt_tbl routing_table1; + routing_table1.ip = IPA_IP_v6; + strlcpy(routing_table1.name, bypass1, sizeof(routing_table1.name)); + if (!m_routing.GetRoutingTable(&routing_table1)) + { + printf("m_routing.GetRoutingTable(&routing_table1=0x%pK) Failed.\n", &routing_table1); + return false; + } + + IPAFilteringTable FilterTable0; + ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v6, IPA_CLIENT_TEST_PROD, false, 1); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1, flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl = -1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action = flt_action; + flt_rule_entry.rule.rt_tbl_hdl = routing_table0.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[0] = 0xFFFFFFFF;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[1] = 0xFFFFFFFF;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[2] = 0xFFFFFFFF;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[3] = 0xFFFFFFFF;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr[0] = GetHigh32(dst_addr_msb); // Filter DST_IP + flt_rule_entry.rule.attrib.u.v6.dst_addr[1] = GetLow32(dst_addr_msb); + flt_rule_entry.rule.attrib.u.v6.dst_addr[2] = GetHigh32(dst_addr_lsb); + flt_rule_entry.rule.attrib.u.v6.dst_addr[3] = GetLow32(dst_addr_lsb); + + printf("flt_rule_entry was set successfully, preparing for insertion....\n"); + + if (((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable())) + { + printf("%s::Error Adding Rule to Filter Table, aborting...\n", __FUNCTION__); + return false; + } + else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", + FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl, FilterTable0.ReadRuleFromTable(0)->status); + } + + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return true; + }// AddRoutingFilteringRules() + + virtual bool AddRoutingFilteringRules() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + bool result = AddRoutingFilteringRules(IPA_PASS_TO_SRC_NAT, + m_outbound_dst_addr_msb, m_outbound_dst_addr_lsb); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return result; + }// AddRoutingFilteringRules() + + virtual bool ModifyPackets() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + IpaIPv6CTBlockTestFixture::ModifyPackets(m_outbound_dst_addr_lsb, m_outbound_dst_addr_msb, m_outbound_dst_port, + m_outbound_src_addr_lsb, m_outbound_src_addr_msb, m_outbound_src_port+1); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return true; + }// ModifyPackets() + + virtual bool ReceivePacketsAndCompare() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + bool result = IpaIPv6CTBlockTestFixture::ReceivePacketsAndCompare(true); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return result; + } +}; + +/*---------------------------------------------------------------------------------------------*/ +/* Test020: IPv6CT send inbound packet for NAT suppression test */ +/*---------------------------------------------------------------------------------------------*/ +class IpaIPV6CTBlockTest020 : public IpaIPv6CTBlockTestFixture +{ +public: + + IpaIPV6CTBlockTest020() + { + m_name = "IpaIPV6CTBlockTest020"; + m_description = + "IPv6CT block test 020 - IPv6CT passes successfully one packet in inbound direction on NAT suppression\n" + "1. Generate and commit three routing tables.\n" + " Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly))\n" + "2. Generate and commit one inbound filtering rule: Destination IP Exactly Match.\n" + "3. Add IPv6CT rule for the packet\n"; + Register(*this); + } + + virtual bool Setup() + { + /* we want statuses on this test */ + return IpaIPv6CTBlockTestFixture::Setup(false, true); + } + + virtual bool AddRoutingFilteringRules(enum ipa_flt_action flt_action, uint64_t dst_addr_msb, uint64_t dst_addr_lsb) + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + + if (!CreateThreeIPv6BypassRoutingTables(bypass0, bypass1, bypass2)) + { + printf("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + printf("CreateThreeBypassRoutingTables completed successfully\n"); + + ipa_ioc_get_rt_tbl routing_table0; + routing_table0.ip = IPA_IP_v6; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + printf("m_routing.GetRoutingTable(&routing_table0=0x%pK) Failed.\n", &routing_table0); + return false; + } + + /* Setup conntrack exception routing table. */ + if (!m_routing.SetNatConntrackExcRoutingTable(routing_table0.hdl, false)) + { + LOG_MSG_ERROR("m_routing.SetNatConntrackExcRoutingTable(routing_table0 hdl=%d) Failed.\n", + routing_table0.hdl); + return false; + } + + ipa_ioc_get_rt_tbl routing_table1; + routing_table1.ip = IPA_IP_v6; + strlcpy(routing_table1.name, bypass1, sizeof(routing_table1.name)); + if (!m_routing.GetRoutingTable(&routing_table1)) + { + printf("m_routing.GetRoutingTable(&routing_table1=0x%pK) Failed.\n", &routing_table1); + return false; + } + + IPAFilteringTable FilterTable0; + ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v6, IPA_CLIENT_TEST_PROD, false, 1); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1, flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl = -1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action = flt_action; + flt_rule_entry.rule.rt_tbl_hdl = routing_table0.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[0] = 0xFFFFFFFF;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[1] = 0xFFFFFFFF;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[2] = 0xFFFFFFFF;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[3] = 0xFFFFFFFF;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr[0] = GetHigh32(dst_addr_msb); // Filter DST_IP + flt_rule_entry.rule.attrib.u.v6.dst_addr[1] = GetLow32(dst_addr_msb); + flt_rule_entry.rule.attrib.u.v6.dst_addr[2] = GetHigh32(dst_addr_lsb); + flt_rule_entry.rule.attrib.u.v6.dst_addr[3] = GetLow32(dst_addr_lsb); + + printf("flt_rule_entry was set successfully, preparing for insertion....\n"); + + if (((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable())) + { + printf("%s::Error Adding Rule to Filter Table, aborting...\n", __FUNCTION__); + return false; + } + else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", + FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl, FilterTable0.ReadRuleFromTable(0)->status); + } + + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return true; + }// AddRoutingFilteringRules() + + virtual bool AddRoutingFilteringRules() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + bool result = AddRoutingFilteringRules(IPA_PASS_TO_DST_NAT, + m_outbound_src_addr_msb, m_outbound_src_addr_lsb); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return result; + }// AddRoutingFilteringRules() + + virtual bool ModifyPackets() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + IpaIPv6CTBlockTestFixture::ModifyPackets(m_outbound_src_addr_lsb, m_outbound_src_addr_msb, m_outbound_src_port, + m_outbound_dst_addr_lsb, m_outbound_dst_addr_msb, m_outbound_dst_port+1); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return true; + }// ModifyPackets() + + virtual bool ReceivePacketsAndCompare() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + bool result = IpaIPv6CTBlockTestFixture::ReceivePacketsAndCompare(true); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return result; + } +}; + +/*---------------------------------------------------------------------------------------------*/ +/* Test021: IPv6CT send outbound packet, suppression test with status enabled */ +/*---------------------------------------------------------------------------------------------*/ +class IpaIPV6CTBlockTest021 : public IpaIPv6CTBlockTestFixture +{ +public: + + IpaIPV6CTBlockTest021() + { + m_name = "IpaIPV6CTBlockTest021"; + m_description = + "IPv6CT block test 021 - IPv6CT passes successfully one packet in outbound direction\n" + "1. Generate and commit three routing tables.\n" + " Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly))\n" + "2. Generate and commit one outbound filtering rule: Destination IP Exactly Match.\n" + "3. Add IPv6CT rule for the packet which doesn't match\n" + "4. Expect NAT suppression to kick in and packet is routed correctly\n" + "5. Compare status and check if NAT suppression kicked in.\n"; + Register(*this); + } + + virtual bool Setup() + { + /* we want statuses on this test */ + return IpaIPv6CTBlockTestFixture::Setup(true, true); + } + + virtual bool AddRoutingFilteringRules(enum ipa_flt_action flt_action, uint64_t dst_addr_msb, uint64_t dst_addr_lsb) + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + + if (!CreateThreeIPv6BypassRoutingTables(bypass0, bypass1, bypass2)) + { + printf("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + printf("CreateThreeBypassRoutingTables completed successfully\n"); + + ipa_ioc_get_rt_tbl routing_table0; + routing_table0.ip = IPA_IP_v6; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + printf("m_routing.GetRoutingTable(&routing_table0=0x%pK) Failed.\n", &routing_table0); + return false; + } + + /* Setup conntrack exception routing table. */ + if (!m_routing.SetNatConntrackExcRoutingTable(routing_table0.hdl, false)) + { + LOG_MSG_ERROR("m_routing.SetNatConntrackExcRoutingTable(routing_table0 hdl=%d) Failed.\n", + routing_table0.hdl); + return false; + } + + ipa_ioc_get_rt_tbl routing_table1; + routing_table1.ip = IPA_IP_v6; + strlcpy(routing_table1.name, bypass1, sizeof(routing_table1.name)); + if (!m_routing.GetRoutingTable(&routing_table1)) + { + printf("m_routing.GetRoutingTable(&routing_table1=0x%pK) Failed.\n", &routing_table1); + return false; + } + + IPAFilteringTable FilterTable0; + ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v6, IPA_CLIENT_TEST_PROD, false, 1); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1, flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl = -1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action = flt_action; + flt_rule_entry.rule.rt_tbl_hdl = routing_table0.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[0] = 0xFFFFFFFF;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[1] = 0xFFFFFFFF;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[2] = 0xFFFFFFFF;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[3] = 0xFFFFFFFF;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr[0] = GetHigh32(dst_addr_msb); // Filter DST_IP + flt_rule_entry.rule.attrib.u.v6.dst_addr[1] = GetLow32(dst_addr_msb); + flt_rule_entry.rule.attrib.u.v6.dst_addr[2] = GetHigh32(dst_addr_lsb); + flt_rule_entry.rule.attrib.u.v6.dst_addr[3] = GetLow32(dst_addr_lsb); + + printf("flt_rule_entry was set successfully, preparing for insertion....\n"); + + if (((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable())) + { + printf("%s::Error Adding Rule to Filter Table, aborting...\n", __FUNCTION__); + return false; + } + else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", + FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl, FilterTable0.ReadRuleFromTable(0)->status); + } + + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return true; + }// AddRoutingFilteringRules() + + virtual bool AddRoutingFilteringRules() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + bool result = AddRoutingFilteringRules(IPA_PASS_TO_SRC_NAT, + m_outbound_dst_addr_msb, m_outbound_dst_addr_lsb); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return result; + }// AddRoutingFilteringRules() + + virtual bool ModifyPackets() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + IpaIPv6CTBlockTestFixture::ModifyPackets(m_outbound_dst_addr_lsb, m_outbound_dst_addr_msb, m_outbound_dst_port, + m_outbound_src_addr_lsb, m_outbound_src_addr_msb, m_outbound_src_port+1); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return true; + }// ModifyPackets() + + virtual bool ReceivePacketsAndCompare(bool packetPassExpected) + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + + // Receive results + struct ipa3_hw_pkt_status_hw_v5_5 *status = NULL; + Byte rxBuff1[0x400]; + size_t receivedSize = m_consumer.ReceiveData(rxBuff1, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize, m_consumer.m_fromChannelName.c_str()); + + bool isSuccess = true; + if (packetPassExpected) + { + // Compare results + if (!CompareResultVsGolden_w_Status(m_sendBuffer, m_sendSize, rxBuff1, receivedSize)) + { + printf("Comparison of Buffer0 Failed!\n"); + isSuccess = false; + } + } + else + { + if (receivedSize) + { + isSuccess = false; + printf("got data while expected packet to be blocked, failing\n"); + } + } + + status = (struct ipa3_hw_pkt_status_hw_v5_5 *)rxBuff1; + if (!status->nat_exc_suppress) + { + printf("NAT Suppression not hit!\n"); + isSuccess = false; + } + + char recievedBuffer[256] = {0}; + char SentBuffer[256] = {0}; + size_t j; + + for (j = 0; j < m_sendSize; j++) + { + snprintf(&SentBuffer[3 * j], sizeof(SentBuffer)-(3 * j + 1), " %02X", m_sendBuffer[j]); + } + + for (j = 0; j < receivedSize; j++) + { + snprintf(&recievedBuffer[3 * j], sizeof(recievedBuffer)-(3 * j + 1), " %02X", rxBuff1[j]); + } + printf("Expected Value1 (%zu)\n%s\n, Received Value1(%zu)\n%s\n", + m_sendSize, SentBuffer, receivedSize, recievedBuffer); + + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return isSuccess; + } + + virtual bool ReceivePacketsAndCompare() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + bool result = ReceivePacketsAndCompare(true); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return result; + } +}; + +/*---------------------------------------------------------------------------------------------*/ +/* Test022: IPv6CT send inbound packet for NAT suppression test with status enabled */ +/*---------------------------------------------------------------------------------------------*/ +class IpaIPV6CTBlockTest022 : public IpaIPv6CTBlockTestFixture +{ +public: + + IpaIPV6CTBlockTest022() + { + m_name = "IpaIPV6CTBlockTest022"; + m_description = + "IPv6CT block test 022 - IPv6CT passes successfully one packet in inbound direction on NAT suppression\n" + "1. Generate and commit three routing tables.\n" + " Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly))\n" + "2. Generate and commit one inbound filtering rule: Destination IP Exactly Match.\n" + "3. Add IPv6CT rule for the packet\n" + "4. Send packet which doesn't match CT and expect NAT suppression to kick in.\n" + "5. Compare status and check if NAT suppression kicked in.\n"; + Register(*this); + } + + virtual bool Setup() + { + /* we want statuses on this test */ + return IpaIPv6CTBlockTestFixture::Setup(true, true); + } + + virtual bool AddRoutingFilteringRules(enum ipa_flt_action flt_action, uint64_t dst_addr_msb, uint64_t dst_addr_lsb) + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + + if (!CreateThreeIPv6BypassRoutingTables(bypass0, bypass1, bypass2)) + { + printf("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + printf("CreateThreeBypassRoutingTables completed successfully\n"); + + ipa_ioc_get_rt_tbl routing_table0; + routing_table0.ip = IPA_IP_v6; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + printf("m_routing.GetRoutingTable(&routing_table0=0x%pK) Failed.\n", &routing_table0); + return false; + } + + /* Setup conntrack exception routing table. */ + if (!m_routing.SetNatConntrackExcRoutingTable(routing_table0.hdl, false)) + { + LOG_MSG_ERROR("m_routing.SetNatConntrackExcRoutingTable(routing_table0 hdl=%d) Failed.\n", + routing_table0.hdl); + return false; + } + + ipa_ioc_get_rt_tbl routing_table1; + routing_table1.ip = IPA_IP_v6; + strlcpy(routing_table1.name, bypass1, sizeof(routing_table1.name)); + if (!m_routing.GetRoutingTable(&routing_table1)) + { + printf("m_routing.GetRoutingTable(&routing_table1=0x%pK) Failed.\n", &routing_table1); + return false; + } + + IPAFilteringTable FilterTable0; + ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v6, IPA_CLIENT_TEST_PROD, false, 1); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1, flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl = -1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action = flt_action; + flt_rule_entry.rule.rt_tbl_hdl = routing_table0.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[0] = 0xFFFFFFFF;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[1] = 0xFFFFFFFF;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[2] = 0xFFFFFFFF;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr_mask[3] = 0xFFFFFFFF;// Exact Match + flt_rule_entry.rule.attrib.u.v6.dst_addr[0] = GetHigh32(dst_addr_msb); // Filter DST_IP + flt_rule_entry.rule.attrib.u.v6.dst_addr[1] = GetLow32(dst_addr_msb); + flt_rule_entry.rule.attrib.u.v6.dst_addr[2] = GetHigh32(dst_addr_lsb); + flt_rule_entry.rule.attrib.u.v6.dst_addr[3] = GetLow32(dst_addr_lsb); + + printf("flt_rule_entry was set successfully, preparing for insertion....\n"); + + if (((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable())) + { + printf("%s::Error Adding Rule to Filter Table, aborting...\n", __FUNCTION__); + return false; + } + else + { + printf("flt rule hdl0=0x%x, status=0x%x\n", + FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl, FilterTable0.ReadRuleFromTable(0)->status); + } + + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return true; + }// AddRoutingFilteringRules() + + virtual bool AddRoutingFilteringRules() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + bool result = IpaIPv6CTBlockTestFixture::AddRoutingFilteringRules(IPA_PASS_TO_DST_NAT, + m_outbound_src_addr_msb, m_outbound_src_addr_lsb); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return result; + }// AddRoutingFilteringRules() + + virtual bool ModifyPackets() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + IpaIPv6CTBlockTestFixture::ModifyPackets(m_outbound_src_addr_lsb, m_outbound_src_addr_msb, m_outbound_src_port, + m_outbound_dst_addr_lsb, m_outbound_dst_addr_msb, m_outbound_dst_port+1); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return true; + }// ModifyPackets() + + virtual bool ReceivePacketsAndCompare(bool packetPassExpected) + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + + // Receive results + struct ipa3_hw_pkt_status_hw_v5_5 *status = NULL; + Byte rxBuff1[0x400]; + size_t receivedSize = m_consumer.ReceiveData(rxBuff1, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize, m_consumer.m_fromChannelName.c_str()); + + bool isSuccess = true; + if (packetPassExpected) + { + // Compare results + if (!CompareResultVsGolden_w_Status(m_sendBuffer, m_sendSize, rxBuff1, receivedSize)) + { + printf("Comparison of Buffer0 Failed!\n"); + isSuccess = false; + } + } + else + { + if (receivedSize) + { + isSuccess = false; + printf("got data while expected packet to be blocked, failing\n"); + } + } + + status = (struct ipa3_hw_pkt_status_hw_v5_5 *)rxBuff1; + if (!status->nat_exc_suppress) + { + printf("NAT Suppression not hit!\n"); + isSuccess = false; + } + + char recievedBuffer[256] = {0}; + char SentBuffer[256] = {0}; + size_t j; + + for (j = 0; j < m_sendSize; j++) + { + snprintf(&SentBuffer[3 * j], sizeof(SentBuffer)-(3 * j + 1), " %02X", m_sendBuffer[j]); + } + + for (j = 0; j < receivedSize; j++) + { + snprintf(&recievedBuffer[3 * j], sizeof(recievedBuffer)-(3 * j + 1), " %02X", rxBuff1[j]); + } + printf("Expected Value1 (%zu)\n%s\n, Received Value1(%zu)\n%s\n", + m_sendSize, SentBuffer, receivedSize, recievedBuffer); + + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return isSuccess; + } + + virtual bool ReceivePacketsAndCompare() + { + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + bool result = ReceivePacketsAndCompare(true); + printf("Leaving %s, %s()\n", __FUNCTION__, __FILE__); + return result; + } +}; + + +// IPv6CT outbound packet test +static class IpaIPV6CTBlockTest001 IpaIPV6CTBlockTest001; + +// IPv6CT inbound packet test +static class IpaIPV6CTBlockTest002 IpaIPV6CTBlockTest002; + +// IPv6CT block outbound packet test +static class IpaIPV6CTBlockTest003 IpaIPV6CTBlockTest003; + +// IPv6CT block inbound packet test +static class IpaIPV6CTBlockTest004 IpaIPV6CTBlockTest004; + +// IPv6CT block outbound packet on inbound filtering rule test +static class IpaIPV6CTBlockTest005 IpaIPV6CTBlockTest005; + +// IPv6CT block inbound packet on outbound filtering rule test +static class IpaIPV6CTBlockTest006 IpaIPV6CTBlockTest006; + +// IPv6CT block outbound packet while disabled outbound direction +static class IpaIPV6CTBlockTest007 IpaIPV6CTBlockTest007; + +// IPv6CT block inbound packet with disabled inbound direction +static class IpaIPV6CTBlockTest008 IpaIPV6CTBlockTest008; + +// IPv6CT send outbound packet with rule in expansion table +static class IpaIPV6CTBlockTest009 IpaIPV6CTBlockTest009; + +// IPv6CT send inbound packet with rule in expansion table +static class IpaIPV6CTBlockTest010 IpaIPV6CTBlockTest010; + +// IPv6CT block outbound packet while the rule was deleted +static class IpaIPV6CTBlockTest011 IpaIPV6CTBlockTest011; + +// IPv6CT block inbound packet while the rule was deleted +static class IpaIPV6CTBlockTest012 IpaIPV6CTBlockTest012; + +// IPv6CT block outbound packet while the rule in expansion table was deleted +static class IpaIPV6CTBlockTest013 IpaIPV6CTBlockTest013; + +// IPv6CT block inbound packet while the rule in expansion table was deleted +static class IpaIPV6CTBlockTest014 IpaIPV6CTBlockTest014; + +// IPv6CT send outbound packet with rule in expansion table while the rule in list head was deleted +static class IpaIPV6CTBlockTest015 IpaIPV6CTBlockTest015; + +// IPv6CT send inbound packet with rule in expansion table while the rule in list head was deleted +static class IpaIPV6CTBlockTest016 IpaIPV6CTBlockTest016; + +// IPv6CT send outbound packet with rule in expansion table while the rule in the middle of the list was deleted +static class IpaIPV6CTBlockTest017 IpaIPV6CTBlockTest017; + +// IPv6CT send inbound packet with rule in expansion table while the rule in the middle of the list was deleted +static class IpaIPV6CTBlockTest018 IpaIPV6CTBlockTest018; + +// IPv6CT suppression test Outbound traffic +static class IpaIPV6CTBlockTest019 IpaIPV6CTBlockTest019; + +// IPv6CT suppression test Inbound traffic +static class IpaIPV6CTBlockTest020 IpaIPV6CTBlockTest020; + +// IPv6CT suppression test Outbound traffic with status +static class IpaIPV6CTBlockTest021 IpaIPV6CTBlockTest021; + +// IPv6CT suppression test Inbound traffic with status +static class IpaIPV6CTBlockTest022 IpaIPV6CTBlockTest022; diff --git a/qcom/opensource/dataipa/kernel-tests/InterfaceAbstraction.cpp b/qcom/opensource/dataipa/kernel-tests/InterfaceAbstraction.cpp new file mode 100644 index 0000000000..a5ec738910 --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/InterfaceAbstraction.cpp @@ -0,0 +1,183 @@ +/* + * Copyright (c) 2017 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include "InterfaceAbstraction.h" + +#define MAX_OPEN_RETRY 10000 + +using std::cout; +using std::endl; + +bool InterfaceAbstraction::Open(const char * toIPAPath, const char * fromIPAPath) +{ + int tries_cnt = MAX_OPEN_RETRY; + if (NULL == toIPAPath && NULL == fromIPAPath) + { + printf("InterfaceAbstraction constructor got 2 null arguments.\n"); + exit(0); + } + + if (NULL != toIPAPath) { + while (tries_cnt > 0) { + printf("trying to open %s %d/%d\n", toIPAPath, MAX_OPEN_RETRY - tries_cnt, MAX_OPEN_RETRY); + // Sleep for 5 msec + usleep(5000); + m_toIPADescriptor = open(toIPAPath, O_WRONLY); + if (-1 != m_toIPADescriptor) { + printf("Success!\n"); + break; + } + tries_cnt--; + } + printf("open retries_cnt=%d\n", MAX_OPEN_RETRY - tries_cnt); + if (-1 == m_toIPADescriptor) { + printf("InterfaceAbstraction failed while opening %s.\n", toIPAPath); + exit(0); + } + m_toChannelName = toIPAPath; + printf("%s device node opened, fd = %d.\n", toIPAPath, m_toIPADescriptor); + } + tries_cnt = MAX_OPEN_RETRY; + if (NULL != fromIPAPath) { + while (tries_cnt > 0) { + printf("trying to open %s %d/%d\n", fromIPAPath, MAX_OPEN_RETRY - tries_cnt, MAX_OPEN_RETRY); + // Sleep for 5 msec + usleep(5000); + m_fromIPADescriptor = open(fromIPAPath, O_RDONLY); + if (-1 != m_fromIPADescriptor) { + printf("Success!\n"); + break; + } + tries_cnt--; + } + printf("open retries_cnt=%d\n", MAX_OPEN_RETRY - tries_cnt); + if (-1 == m_fromIPADescriptor) + { + printf("InterfaceAbstraction failed on opening %s.\n", fromIPAPath); + exit(0); + } + m_fromChannelName = fromIPAPath; + printf("%s device node opened, fd = %d.\n", fromIPAPath, m_fromIPADescriptor); + } + + return true; +}/*Ctor*/ + +void InterfaceAbstraction::Close() +{ + close(m_toIPADescriptor); + close(m_fromIPADescriptor); +} + +long InterfaceAbstraction::SendData(unsigned char *buf, size_t size) +{ + long bytesWritten = 0; + + printf("Trying to write %zu bytes to %d.\n", size, m_toIPADescriptor); + + bytesWritten = write(m_toIPADescriptor, buf, size); + if (-1 == bytesWritten) + { + int err = errno; + printf( + "$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$\n"); + printf( + "Failed to execute command\n write(m_toIPADescriptor, buf, size);\n " + "m_toIPADescriptor=%d, buf=0x%p, size=%zu",m_toIPADescriptor, + buf, + size); + printf("Error on write execution, errno=%d, Quitting!\n", err); + printf( + "$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$\n"); + exit(-1); + } + + cout << "bytesWritten = " << bytesWritten << endl; + + return bytesWritten; +} + +int InterfaceAbstraction::ReceiveData(unsigned char *buf, size_t size) +{ + size_t bytesRead = 0; + size_t totalBytesRead = 0; + bool continueRead = false; + + do + { + printf("Trying to read %zu bytes from %d.\n", size, m_fromIPADescriptor); + + bytesRead = read(m_fromIPADescriptor, (void*)buf, size); + printf("Read %zu bytes.\n", bytesRead); + totalBytesRead += bytesRead; + if (bytesRead == size) + continueRead = true; + else + continueRead = false; + } while (continueRead); + + return totalBytesRead; +} + +int InterfaceAbstraction::ReceiveSingleDataChunk(unsigned char *buf, size_t size){ + size_t bytesRead = 0; + printf("Trying to read %zu bytes from %d.\n", size, m_fromIPADescriptor); + bytesRead = read(m_fromIPADescriptor, (void*)buf, size); + printf("Read %zu bytes.\n", bytesRead); + return bytesRead; +} + +int InterfaceAbstraction::setReadNoBlock(){ + int flags = fcntl(m_fromIPADescriptor, F_GETFL, 0); + if(flags == -1){ + return -1; + } + return fcntl(m_fromIPADescriptor, F_SETFL, flags | O_NONBLOCK); +} + +int InterfaceAbstraction::clearReadNoBlock(){ + int flags = fcntl(m_fromIPADescriptor, F_GETFL, 0); + if(flags == -1){ + return -1; + } + return fcntl(m_fromIPADescriptor, F_SETFL, flags & ~O_NONBLOCK); +} + +InterfaceAbstraction::~InterfaceAbstraction() +{ + close(m_fromIPADescriptor); + m_fromChannelName = ""; + + close(m_toIPADescriptor); + m_toChannelName = ""; +} diff --git a/qcom/opensource/dataipa/kernel-tests/InterfaceAbstraction.h b/qcom/opensource/dataipa/kernel-tests/InterfaceAbstraction.h new file mode 100644 index 0000000000..6a110e5e3d --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/InterfaceAbstraction.h @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2017 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef INTERFACE_ABSTRACTION_H_ +#define INTERFACE_ABSTRACTION_H_ + +#include +#include +#include + +typedef unsigned char Byte; + +using namespace std; + +class InterfaceAbstraction +{ + +public: + ~InterfaceAbstraction(); + bool Open(const char *toIPAPath, const char *fromIPAPath); + void Close(); + long SendData(unsigned char *buffer, size_t size); + int ReceiveData(unsigned char *buf, size_t size); + int ReceiveSingleDataChunk(unsigned char *buf, size_t size); + int setReadNoBlock(); + int clearReadNoBlock(); + + string m_toChannelName; + string m_fromChannelName; + +private: + int m_toIPADescriptor; + int m_fromIPADescriptor; +}; + +#endif diff --git a/qcom/opensource/dataipa/kernel-tests/Logger.cpp b/qcom/opensource/dataipa/kernel-tests/Logger.cpp new file mode 100644 index 0000000000..5b226c51d0 --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/Logger.cpp @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2017 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "Logger.h" + +//////////////////////////////////////////////////////////////////////////// + +//The trace level of the system will be used to choose the system printing level +Logger::Logger(TraceLevel nTraceLevel) +{ + m_nTraceLevelToPresent = nTraceLevel; +} + +//////////////////////////////////////////////////////////////////////////// + +//This method will be use to print messages. it will also gie a trace level for each message. +void Logger::AddMessage(TraceLevel nTraceLevel, const char *format, ...) +{ + + //in case the trace level is not "high" no print should be made. + if (nTraceLevel < m_nTraceLevelToPresent) + { + return; + } + + va_list ap; + va_start(ap, format); + vprintf(format, ap); + va_end(ap); +} + +//////////////////////////////////////////////////////////////////////////// + diff --git a/qcom/opensource/dataipa/kernel-tests/Logger.h b/qcom/opensource/dataipa/kernel-tests/Logger.h new file mode 100644 index 0000000000..9e991f50e2 --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/Logger.h @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2017 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LOGGER_H_ +#define LOGGER_H_ + +#include +#include + +using namespace std; + +typedef enum{ + LOG_DEVELOPMENT = 0, + LOG_ERROR = 0, + LOG_VERBOSE = 1 +} TraceLevel; + +/*This class will controll all the printing in the test application + *In each test there will be many printing while each + *specific print will define it's "importancy"(TraceLevel) + *During the development of the test it is + *strongly suggested to use LOG_DEVELOPMENT. + */ + +class Logger +{ +public: + Logger(TraceLevel nTraceLevelToPresent); + void AddMessage(TraceLevel nTraceLevel, const char *format, ...); +private: + int m_nTraceLevelToPresent; +}; + +#endif /* LOGGER_H_ */ diff --git a/qcom/opensource/dataipa/kernel-tests/MBIMAggregationTestFixtureConf11.cpp b/qcom/opensource/dataipa/kernel-tests/MBIMAggregationTestFixtureConf11.cpp new file mode 100644 index 0000000000..7462d9bf91 --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/MBIMAggregationTestFixtureConf11.cpp @@ -0,0 +1,1169 @@ +/* + * Copyright (c) 2017-2018,2020 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "MBIMAggregationTestFixtureConf11.h" +#include "TestManager.h" + +///////////////////////////////////////////////////////////////////////////////// + +//define the static Pipes which will be used by all derived tests. +Pipe MBIMAggregationTestFixtureConf11::m_IpaToUsbPipeAgg(IPA_CLIENT_TEST2_CONS, + IPA_TEST_CONFIGURATION_11); +Pipe MBIMAggregationTestFixtureConf11::m_UsbToIpaPipe(IPA_CLIENT_TEST_PROD, + IPA_TEST_CONFIGURATION_11); +Pipe MBIMAggregationTestFixtureConf11::m_IpaToUsbPipe(IPA_CLIENT_TEST3_CONS, + IPA_TEST_CONFIGURATION_11); +Pipe MBIMAggregationTestFixtureConf11::m_UsbToIpaPipeDeagg(IPA_CLIENT_TEST2_PROD, + IPA_TEST_CONFIGURATION_11); +Pipe MBIMAggregationTestFixtureConf11::m_IpaToUsbPipeAggTime(IPA_CLIENT_TEST_CONS, + IPA_TEST_CONFIGURATION_11); +Pipe MBIMAggregationTestFixtureConf11::m_IpaToUsbPipeAgg0Limits(IPA_CLIENT_TEST4_CONS, + IPA_TEST_CONFIGURATION_11); + +RoutingDriverWrapper MBIMAggregationTestFixtureConf11::m_Routing; +Filtering MBIMAggregationTestFixtureConf11::m_Filtering; +HeaderInsertion MBIMAggregationTestFixtureConf11::m_HeaderInsertion; + +///////////////////////////////////////////////////////////////////////////////// + +MBIMAggregationTestFixtureConf11::MBIMAggregationTestFixtureConf11(bool generic_agg) +: mGenericAgg(generic_agg) +{ + if (mGenericAgg) { + m_testSuiteName.push_back("GenMbimAgg"); + m_minIPAHwType = IPA_HW_v4_0; + } else { + m_testSuiteName.push_back("Mbim16Agg"); + m_maxIPAHwType = IPA_HW_v3_5_1; + } + Register(*this); +} + +///////////////////////////////////////////////////////////////////////////////// + +int MBIMAggregationTestFixtureConf11::SetupKernelModule() +{ + int retval; + struct ipa_channel_config from_ipa_channels[4]; + struct test_ipa_ep_cfg from_ipa_cfg[4]; + struct ipa_channel_config to_ipa_channels[2]; + struct test_ipa_ep_cfg to_ipa_cfg[2]; + + struct ipa_test_config_header header = {0}; + struct ipa_channel_config *to_ipa_array[2]; + struct ipa_channel_config *from_ipa_array[4]; + + /* From ipa configurations - 4 pipes */ + memset(&from_ipa_cfg[0], 0, sizeof(from_ipa_cfg[0])); + from_ipa_cfg[0].aggr.aggr_en = IPA_ENABLE_AGGR; + from_ipa_cfg[0].aggr.aggr = IPA_MBIM_16; + from_ipa_cfg[0].aggr.aggr_byte_limit = 1; + from_ipa_cfg[0].aggr.aggr_time_limit = 0; + if (mGenericAgg) { + from_ipa_cfg[0].hdr.hdr_len = 4; + from_ipa_cfg[0].hdr_ext.hdr_pad_to_alignment = 2; + } else { + from_ipa_cfg[0].hdr.hdr_len = 1; + } + + prepare_channel_struct(&from_ipa_channels[0], + header.from_ipa_channels_num++, + IPA_CLIENT_TEST2_CONS, + (void *)&from_ipa_cfg[0], + sizeof(from_ipa_cfg[0]), + false); + from_ipa_array[0] = &from_ipa_channels[0]; + + memset(&from_ipa_cfg[1], 0, sizeof(from_ipa_cfg[1])); + prepare_channel_struct(&from_ipa_channels[1], + header.from_ipa_channels_num++, + IPA_CLIENT_TEST3_CONS, + (void *)&from_ipa_cfg[1], + sizeof(from_ipa_cfg[1]), + false); + from_ipa_array[1] = &from_ipa_channels[1]; + + memset(&from_ipa_cfg[2], 0, sizeof(from_ipa_cfg[2])); + from_ipa_cfg[2].aggr.aggr_en = IPA_ENABLE_AGGR; + from_ipa_cfg[2].aggr.aggr = IPA_MBIM_16; + from_ipa_cfg[2].aggr.aggr_byte_limit = 1; + from_ipa_cfg[2].aggr.aggr_time_limit = 30; + if (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v4_2) + from_ipa_cfg[2].aggr.aggr_time_limit *= 1000; + if (mGenericAgg) { + from_ipa_cfg[2].hdr.hdr_len = 4; + from_ipa_cfg[2].hdr_ext.hdr_pad_to_alignment = 2; + } else { + from_ipa_cfg[2].hdr.hdr_len = 1; + } + + prepare_channel_struct(&from_ipa_channels[2], + header.from_ipa_channels_num++, + IPA_CLIENT_TEST_CONS, + (void *)&from_ipa_cfg[2], + sizeof(from_ipa_cfg[2]), + false); + from_ipa_array[2] = &from_ipa_channels[2]; + + memset(&from_ipa_cfg[3], 0, sizeof(from_ipa_cfg[3])); + from_ipa_cfg[3].aggr.aggr_en = IPA_ENABLE_AGGR; + from_ipa_cfg[3].aggr.aggr = IPA_MBIM_16; + from_ipa_cfg[3].aggr.aggr_byte_limit = 0; + from_ipa_cfg[3].aggr.aggr_time_limit = 0; + if (mGenericAgg) { + from_ipa_cfg[3].hdr.hdr_len = 4; + from_ipa_cfg[3].hdr_ext.hdr_pad_to_alignment = 2; + } else { + from_ipa_cfg[3].hdr.hdr_len = 1; + } + + prepare_channel_struct(&from_ipa_channels[3], + header.from_ipa_channels_num++, + IPA_CLIENT_TEST4_CONS, + (void *)&from_ipa_cfg[3], + sizeof(from_ipa_cfg[3]), + false); + from_ipa_array[3] = &from_ipa_channels[3]; + + /* To ipa configurations - 2 pipes */ + memset(&to_ipa_cfg[0], 0, sizeof(to_ipa_cfg[0])); + prepare_channel_struct(&to_ipa_channels[0], + header.to_ipa_channels_num++, + IPA_CLIENT_TEST_PROD, + (void *)&to_ipa_cfg[0], + sizeof(to_ipa_cfg[0])); + to_ipa_array[0] = &to_ipa_channels[0]; + + memset(&to_ipa_cfg[1], 0, sizeof(to_ipa_cfg[1])); + to_ipa_cfg[1].aggr.aggr_en = IPA_ENABLE_DEAGGR; + to_ipa_cfg[1].aggr.aggr = IPA_MBIM_16; + prepare_channel_struct(&to_ipa_channels[1], + header.to_ipa_channels_num++, + IPA_CLIENT_TEST2_PROD, + (void *)&to_ipa_cfg[1], + sizeof(to_ipa_cfg[1])); + to_ipa_array[1] = &to_ipa_channels[1]; + + prepare_header_struct(&header, from_ipa_array, to_ipa_array); + + retval = GenericConfigureScenario(&header); + + return retval; +} + +bool MBIMAggregationTestFixtureConf11::Setup() +{ + bool bRetVal = true; + + //Set the configuration to support USB->IPA and IPA->USB pipes. + if (SetupKernelModule() != true) { + LOG_MSG_ERROR("fail to configure kernel module!\n"); + return false; + } + + //Initialize the pipe for all the tests - this will open the inode which represents the pipe. + bRetVal &= m_IpaToUsbPipeAgg.Init(); + bRetVal &= m_UsbToIpaPipe.Init(); + bRetVal &= m_IpaToUsbPipe.Init(); + bRetVal &= m_UsbToIpaPipeDeagg.Init(); + bRetVal &= m_IpaToUsbPipeAggTime.Init(); + bRetVal &= m_IpaToUsbPipeAgg0Limits.Init(); + + if (!m_Routing.DeviceNodeIsOpened()) { + LOG_MSG_ERROR( + "Routing block is not ready for immediate commands!\n"); + return false; + } + if (!m_Filtering.DeviceNodeIsOpened()) { + LOG_MSG_ERROR( + "Filtering block is not ready for immediate commands!\n"); + return false; + } + if (!m_HeaderInsertion.DeviceNodeIsOpened()) + { + LOG_MSG_ERROR("Header Insertion block is not ready for immediate commands!\n"); + return false; + } + m_HeaderInsertion.Reset();// resetting this component will reset both Routing and Filtering tables. + + return bRetVal; +} + +///////////////////////////////////////////////////////////////////////////////// + +bool MBIMAggregationTestFixtureConf11::Teardown() +{ + //The Destroy method will close the inode. + m_IpaToUsbPipeAgg.Destroy(); + m_UsbToIpaPipe.Destroy(); + m_IpaToUsbPipe.Destroy(); + m_UsbToIpaPipeDeagg.Destroy(); + m_IpaToUsbPipeAggTime.Destroy(); + m_IpaToUsbPipeAgg0Limits.Destroy(); + + return true; +} + +///////////////////////////////////////////////////////////////////////////////// + +bool MBIMAggregationTestFixtureConf11::Run() +{ + LOG_MSG_STACK("Entering Function"); + + // Add the relevant filtering rules + if (!AddRules()) { + LOG_MSG_ERROR("Failed adding filtering rules."); + return false; + } + if (!TestLogic()) { + LOG_MSG_ERROR("Test failed, Input and expected output mismatch."); + return false; + } + + LOG_MSG_STACK("Leaving Function (Returning True)"); + return true; +} // Run() + +///////////////////////////////////////////////////////////////////////////////// + +bool MBIMAggregationTestFixtureConf11::AddRules1HeaderAggregation() { + m_eIP = IPA_IP_v4; + const char aBypass[20] = "Bypass1"; + uint32_t nTableHdl; + bool bRetVal = true; + IPAFilteringTable cFilterTable0; + IPAFilteringTable cFilterTable1; + struct ipa_flt_rule_add sFilterRuleEntry; + struct ipa_ioc_get_hdr sGetHeader; + uint8_t aHeadertoAdd[4]; + int hdrSize; + + if (mGenericAgg) { + hdrSize = 4; + aHeadertoAdd[0]= 0x49; + aHeadertoAdd[1] = 0x50; + aHeadertoAdd[2] = 0x53; + aHeadertoAdd[3] = 0x00; + } else { + hdrSize = 1; + aHeadertoAdd[0] = 0x00; + } + + LOG_MSG_STACK("Entering Function"); + memset(&sFilterRuleEntry, 0, sizeof(sFilterRuleEntry)); + memset(&sGetHeader, 0, sizeof(sGetHeader)); + + // Create Header: + // Allocate Memory, populate it, and add in to the Header Insertion. + struct ipa_ioc_add_hdr * pHeaderDescriptor = NULL; + pHeaderDescriptor = (struct ipa_ioc_add_hdr *) calloc(1, + sizeof(struct ipa_ioc_add_hdr) + + 1 * sizeof(struct ipa_hdr_add)); + if (!pHeaderDescriptor) { + LOG_MSG_ERROR("calloc failed to allocate pHeaderDescriptor"); + bRetVal = false; + goto bail; + } + + pHeaderDescriptor->commit = true; + pHeaderDescriptor->num_hdrs = 1; + // Adding Header No1. + strlcpy(pHeaderDescriptor->hdr[0].name, "StreamId0", sizeof(pHeaderDescriptor->hdr[0].name)); // Header's Name + memcpy(pHeaderDescriptor->hdr[0].hdr, aHeadertoAdd, hdrSize); //Header's Data + pHeaderDescriptor->hdr[0].hdr_len = hdrSize; + pHeaderDescriptor->hdr[0].hdr_hdl = -1; //Return Value + pHeaderDescriptor->hdr[0].is_partial = false; + pHeaderDescriptor->hdr[0].status = -1; // Return Parameter + + strlcpy(sGetHeader.name, pHeaderDescriptor->hdr[0].name, sizeof(sGetHeader.name)); + + + if (!m_HeaderInsertion.AddHeader(pHeaderDescriptor)) + { + LOG_MSG_ERROR("m_HeaderInsertion.AddHeader(pHeaderDescriptor) Failed."); + bRetVal = false; + goto bail; + } + + if (!m_HeaderInsertion.GetHeaderHandle(&sGetHeader)) + { + LOG_MSG_ERROR(" Failed"); + bRetVal = false; + goto bail; + } + LOG_MSG_DEBUG("Received Header Handle = 0x%x", sGetHeader.hdl); + + + if (!CreateBypassRoutingTable(&m_Routing, m_eIP, aBypass, IPA_CLIENT_TEST2_CONS, + sGetHeader.hdl,&nTableHdl)) { + LOG_MSG_ERROR("CreateBypassRoutingTable Failed\n"); + bRetVal = false; + goto bail; + } + + + LOG_MSG_INFO("Creation of bypass routing table completed successfully"); + + // Creating Filtering Rules + cFilterTable0.Init(m_eIP,IPA_CLIENT_TEST_PROD, false, 1); + LOG_MSG_INFO("Creation of filtering table for IPA_CLIENT_TEST_PROD completed successfully"); + + // Configuring Filtering Rule No.1 + cFilterTable0.GeneratePresetRule(1,sFilterRuleEntry); + sFilterRuleEntry.at_rear = true; + sFilterRuleEntry.flt_rule_hdl=-1; // return Value + sFilterRuleEntry.status = -1; // return value + sFilterRuleEntry.rule.action=IPA_PASS_TO_ROUTING; + sFilterRuleEntry.rule.rt_tbl_hdl=nTableHdl; //put here the handle corresponding to Routing Rule 1 + sFilterRuleEntry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; // Destination IP Based Filtering + sFilterRuleEntry.rule.attrib.u.v4.dst_addr_mask = 0xFF0000FF; // Mask + sFilterRuleEntry.rule.attrib.u.v4.dst_addr = 0x7F000001; // Filter DST_IP == 127.0.0.1. + if ( + ((uint8_t)-1 == cFilterTable0.AddRuleToTable(sFilterRuleEntry)) || + !m_Filtering.AddFilteringRule(cFilterTable0.GetFilteringTable()) + ) + { + LOG_MSG_ERROR ("Adding Rule (0) to Filtering block Failed."); + bRetVal = false; + goto bail; + } else + { + LOG_MSG_DEBUG("flt rule hdl0=0x%x, status=0x%x\n", cFilterTable0.ReadRuleFromTable(0)->flt_rule_hdl,cFilterTable0.ReadRuleFromTable(0)->status); + } + + memset(&sFilterRuleEntry, 0, sizeof(sFilterRuleEntry)); + + // Creating Filtering Rule for De-aggregation PROD + cFilterTable1.Init(m_eIP,IPA_CLIENT_TEST2_PROD, false, 1); + LOG_MSG_INFO("Creation of filtering table for IPA_CLIENT_TEST2_PROD completed successfully"); + + // Configuring Filtering Rule No.1 + cFilterTable1.GeneratePresetRule(1,sFilterRuleEntry); + sFilterRuleEntry.at_rear = true; + sFilterRuleEntry.flt_rule_hdl=-1; // return Value + sFilterRuleEntry.status = -1; // return value + sFilterRuleEntry.rule.action=IPA_PASS_TO_ROUTING; + sFilterRuleEntry.rule.rt_tbl_hdl=nTableHdl; //put here the handle corresponding to Routing Rule 1 + sFilterRuleEntry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; // Destination IP Based Filtering + sFilterRuleEntry.rule.attrib.u.v4.dst_addr_mask = 0xFF0000FF; // Mask + sFilterRuleEntry.rule.attrib.u.v4.dst_addr = 0x7F000001; // Filter DST_IP == 127.0.0.1. + if ( + ((uint8_t)-1 == cFilterTable1.AddRuleToTable(sFilterRuleEntry)) || + !m_Filtering.AddFilteringRule(cFilterTable1.GetFilteringTable()) + ) + { + LOG_MSG_ERROR ("Adding Rule (0) to Filtering block Failed."); + bRetVal = false; + goto bail; + } else + { + LOG_MSG_DEBUG("flt rule hdl0=0x%x, status=0x%x\n", cFilterTable1.ReadRuleFromTable(0)->flt_rule_hdl,cFilterTable1.ReadRuleFromTable(0)->status); + } + +bail: + Free(pHeaderDescriptor); + LOG_MSG_STACK( + "Leaving Function (Returning %s)", bRetVal?"True":"False"); + return bRetVal; +} // AddRules() + +bool MBIMAggregationTestFixtureConf11::AddRules1HeaderAggregation(bool bAggForceClose) { + m_eIP = IPA_IP_v4; + const char aBypass[20] = "Bypass1"; + uint32_t nTableHdl; + bool bRetVal = true; + IPAFilteringTable_v2 cFilterTable0; + IPAFilteringTable_v2 cFilterTable1; + struct ipa_flt_rule_add_v2 sFilterRuleEntry; + struct ipa_ioc_get_hdr sGetHeader; + uint8_t aHeadertoAdd[4]; + int hdrSize; + + if (mGenericAgg) { + hdrSize = 4; + aHeadertoAdd[0]= 0x49; + aHeadertoAdd[1] = 0x50; + aHeadertoAdd[2] = 0x53; + aHeadertoAdd[3] = 0x00; + } else { + hdrSize = 1; + aHeadertoAdd[0] = 0x00; + } + + LOG_MSG_STACK("Entering Function"); + memset(&sFilterRuleEntry, 0, sizeof(sFilterRuleEntry)); + memset(&sGetHeader, 0, sizeof(sGetHeader)); + + // Create Header: + // Allocate Memory, populate it, and add in to the Header Insertion. + struct ipa_ioc_add_hdr * pHeaderDescriptor = NULL; + pHeaderDescriptor = (struct ipa_ioc_add_hdr *) calloc(1, + sizeof(struct ipa_ioc_add_hdr) + + 1 * sizeof(struct ipa_hdr_add)); + if (!pHeaderDescriptor) { + LOG_MSG_ERROR("calloc failed to allocate pHeaderDescriptor"); + bRetVal = false; + goto bail; + } + + pHeaderDescriptor->commit = true; + pHeaderDescriptor->num_hdrs = 1; + // Adding Header No1. + strlcpy(pHeaderDescriptor->hdr[0].name, "StreamId0", sizeof(pHeaderDescriptor->hdr[0].name)); // Header's Name + memcpy(pHeaderDescriptor->hdr[0].hdr, aHeadertoAdd, hdrSize); //Header's Data + pHeaderDescriptor->hdr[0].hdr_len = hdrSize; + pHeaderDescriptor->hdr[0].hdr_hdl = -1; //Return Value + pHeaderDescriptor->hdr[0].is_partial = false; + pHeaderDescriptor->hdr[0].status = -1; // Return Parameter + + strlcpy(sGetHeader.name, pHeaderDescriptor->hdr[0].name, sizeof(sGetHeader.name)); + + + if (!m_HeaderInsertion.AddHeader(pHeaderDescriptor)) + { + LOG_MSG_ERROR("m_HeaderInsertion.AddHeader(pHeaderDescriptor) Failed."); + bRetVal = false; + goto bail; + } + + if (!m_HeaderInsertion.GetHeaderHandle(&sGetHeader)) + { + LOG_MSG_ERROR(" Failed"); + bRetVal = false; + goto bail; + } + LOG_MSG_DEBUG("Received Header Handle = 0x%x", sGetHeader.hdl); + + + if (!CreateBypassRoutingTable_v2(&m_Routing, m_eIP, aBypass, IPA_CLIENT_TEST2_CONS, + sGetHeader.hdl, &nTableHdl, 0)) { + LOG_MSG_ERROR("CreateBypassRoutingTable Failed\n"); + bRetVal = false; + goto bail; + } + + + LOG_MSG_INFO("Creation of bypass routing table completed successfully"); + + // Creating Filtering Rules + cFilterTable0.Init(m_eIP,IPA_CLIENT_TEST_PROD, false, 1); + LOG_MSG_INFO("Creation of filtering table for IPA_CLIENT_TEST_PROD completed successfully"); + + // Configuring Filtering Rule No.1 + cFilterTable0.GeneratePresetRule(1,sFilterRuleEntry); + sFilterRuleEntry.at_rear = true; + sFilterRuleEntry.flt_rule_hdl=-1; // return Value + sFilterRuleEntry.status = -1; // return value + sFilterRuleEntry.rule.action=IPA_PASS_TO_ROUTING; + sFilterRuleEntry.rule.rt_tbl_hdl=nTableHdl; //put here the handle corresponding to Routing Rule 1 + sFilterRuleEntry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; // Destination IP Based Filtering + sFilterRuleEntry.rule.attrib.u.v4.dst_addr_mask = 0xFF0000FF; // Mask + sFilterRuleEntry.rule.attrib.u.v4.dst_addr = 0x7F000001; // Filter DST_IP == 127.0.0.1. + sFilterRuleEntry.rule.close_aggr_irq_mod = bAggForceClose; + if ( + ((uint8_t)-1 == cFilterTable0.AddRuleToTable(sFilterRuleEntry)) || + !m_Filtering.AddFilteringRule(cFilterTable0.GetFilteringTable()) + ) + { + LOG_MSG_ERROR ("Adding Rule (0) to Filtering block Failed."); + bRetVal = false; + goto bail; + } else + { + LOG_MSG_DEBUG("flt rule hdl0=0x%x, status=0x%x\n", cFilterTable0.ReadRuleFromTable(0)->flt_rule_hdl,cFilterTable0.ReadRuleFromTable(0)->status); + } + + memset(&sFilterRuleEntry, 0, sizeof(sFilterRuleEntry)); + + // Creating Filtering Rule for De-aggregation PROD + cFilterTable1.Init(m_eIP,IPA_CLIENT_TEST2_PROD, false, 1); + LOG_MSG_INFO("Creation of filtering table for IPA_CLIENT_TEST2_PROD completed successfully"); + + // Configuring Filtering Rule No.1 + cFilterTable1.GeneratePresetRule(1,sFilterRuleEntry); + sFilterRuleEntry.at_rear = true; + sFilterRuleEntry.flt_rule_hdl=-1; // return Value + sFilterRuleEntry.status = -1; // return value + sFilterRuleEntry.rule.action=IPA_PASS_TO_ROUTING; + sFilterRuleEntry.rule.rt_tbl_hdl=nTableHdl; //put here the handle corresponding to Routing Rule 1 + sFilterRuleEntry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; // Destination IP Based Filtering + sFilterRuleEntry.rule.attrib.u.v4.dst_addr_mask = 0xFF0000FF; // Mask + sFilterRuleEntry.rule.attrib.u.v4.dst_addr = 0x7F000001; // Filter DST_IP == 127.0.0.1. + sFilterRuleEntry.rule.close_aggr_irq_mod = bAggForceClose; + if ( + ((uint8_t)-1 == cFilterTable1.AddRuleToTable(sFilterRuleEntry)) || + !m_Filtering.AddFilteringRule(cFilterTable1.GetFilteringTable()) + ) + { + LOG_MSG_ERROR ("Adding Rule (0) to Filtering block Failed."); + bRetVal = false; + goto bail; + } else + { + LOG_MSG_DEBUG("flt rule hdl0=0x%x, status=0x%x\n", cFilterTable1.ReadRuleFromTable(0)->flt_rule_hdl,cFilterTable1.ReadRuleFromTable(0)->status); + } + +bail: + Free(pHeaderDescriptor); + LOG_MSG_STACK( + "Leaving Function (Returning %s)", bRetVal?"True":"False"); + return bRetVal; +} // AddRules() + + +///////////////////////////////////////////////////////////////////////////////// + +bool MBIMAggregationTestFixtureConf11::AddRulesDeaggregation() { + m_eIP = IPA_IP_v4; + const char aBypass[20] = "Bypass1"; + uint32_t nTableHdl; + bool bRetVal = true; + IPAFilteringTable cFilterTable0; + struct ipa_flt_rule_add sFilterRuleEntry; + struct ipa_ioc_get_hdr sGetHeader; + uint8_t aHeadertoAdd[4]; + int hdrSize; + + if (mGenericAgg) { + hdrSize = 4; + aHeadertoAdd[0] = 0x49; + aHeadertoAdd[1] = 0x50; + aHeadertoAdd[2] = 0x53; + aHeadertoAdd[3] = 0x00; + } + else { + hdrSize = 1; + aHeadertoAdd[0] = 0x00; + } + + LOG_MSG_STACK("Entering Function"); + memset(&sFilterRuleEntry, 0, sizeof(sFilterRuleEntry)); + memset(&sGetHeader, 0, sizeof(sGetHeader)); + + // Create Header: + // Allocate Memory, populate it, and add in to the Header Insertion. + struct ipa_ioc_add_hdr * pHeaderDescriptor = NULL; + pHeaderDescriptor = (struct ipa_ioc_add_hdr *) calloc(1, + sizeof(struct ipa_ioc_add_hdr) + + 1 * sizeof(struct ipa_hdr_add)); + if (!pHeaderDescriptor) { + LOG_MSG_ERROR("calloc failed to allocate pHeaderDescriptor"); + bRetVal = false; + goto bail; + } + + pHeaderDescriptor->commit = true; + pHeaderDescriptor->num_hdrs = 1; + // Adding Header No1. + strlcpy(pHeaderDescriptor->hdr[0].name, "StreamId0", sizeof(pHeaderDescriptor->hdr[0].name)); // Header's Name + memcpy(pHeaderDescriptor->hdr[0].hdr, (void*)&aHeadertoAdd, + hdrSize); //Header's Data + pHeaderDescriptor->hdr[0].hdr_len = hdrSize; + pHeaderDescriptor->hdr[0].hdr_hdl = -1; //Return Value + pHeaderDescriptor->hdr[0].is_partial = false; + pHeaderDescriptor->hdr[0].status = -1; // Return Parameter + + strlcpy(sGetHeader.name, pHeaderDescriptor->hdr[0].name, sizeof(sGetHeader.name)); + + + if (!m_HeaderInsertion.AddHeader(pHeaderDescriptor)) + { + LOG_MSG_ERROR("m_HeaderInsertion.AddHeader(pHeaderDescriptor) Failed."); + bRetVal = false; + goto bail; + } + + if (!m_HeaderInsertion.GetHeaderHandle(&sGetHeader)) + { + LOG_MSG_ERROR(" Failed"); + bRetVal = false; + goto bail; + } + LOG_MSG_DEBUG("Received Header Handle = 0x%x", sGetHeader.hdl); + + + if (!CreateBypassRoutingTable(&m_Routing, m_eIP, aBypass, IPA_CLIENT_TEST3_CONS, + sGetHeader.hdl,&nTableHdl)) { + LOG_MSG_ERROR("CreateBypassRoutingTable Failed\n"); + bRetVal = false; + goto bail; + } + + + LOG_MSG_INFO("Creation of bypass routing table completed successfully"); + + // Creating Filtering Rules + cFilterTable0.Init(m_eIP,IPA_CLIENT_TEST2_PROD, false, 1); + LOG_MSG_INFO("Creation of filtering table completed successfully"); + + // Configuring Filtering Rule No.1 + cFilterTable0.GeneratePresetRule(1,sFilterRuleEntry); + sFilterRuleEntry.at_rear = true; + sFilterRuleEntry.flt_rule_hdl=-1; // return Value + sFilterRuleEntry.status = -1; // return value + sFilterRuleEntry.rule.action=IPA_PASS_TO_ROUTING; + sFilterRuleEntry.rule.rt_tbl_hdl=nTableHdl; //put here the handle corresponding to Routing Rule 1 + sFilterRuleEntry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; // Destination IP Based Filtering + sFilterRuleEntry.rule.attrib.u.v4.dst_addr_mask = 0xFF0000FF; // Mask + sFilterRuleEntry.rule.attrib.u.v4.dst_addr = 0x7F000001; // Filter DST_IP == 127.0.0.1. + if ( + ((uint8_t)-1 == cFilterTable0.AddRuleToTable(sFilterRuleEntry)) || + !m_Filtering.AddFilteringRule(cFilterTable0.GetFilteringTable()) + ) + { + LOG_MSG_ERROR ("Adding Rule (0) to Filtering block Failed."); + bRetVal = false; + goto bail; + } else + { + LOG_MSG_DEBUG("flt rule hdl0=0x%x, status=0x%x\n", cFilterTable0.ReadRuleFromTable(0)->flt_rule_hdl,cFilterTable0.ReadRuleFromTable(0)->status); + } + +bail: + Free(pHeaderDescriptor); + LOG_MSG_STACK( + "Leaving Function (Returning %s)", bRetVal?"True":"False"); + return bRetVal; +} // AddRules() + +///////////////////////////////////////////////////////////////////////////////// + +bool MBIMAggregationTestFixtureConf11::AddRules1HeaderAggregationTime() { + m_eIP = IPA_IP_v4; + const char aBypass[20] = "Bypass1"; + uint32_t nTableHdl; + bool bRetVal = true; + IPAFilteringTable cFilterTable0; + struct ipa_flt_rule_add sFilterRuleEntry; + struct ipa_ioc_get_hdr sGetHeader; + uint8_t aHeadertoAdd[4]; + int hdrSize; + + if (mGenericAgg) { + hdrSize = 4; + aHeadertoAdd[0] = 0x49; + aHeadertoAdd[1] = 0x50; + aHeadertoAdd[2] = 0x53; + aHeadertoAdd[3] = 0x00; + } + else { + hdrSize = 1; + aHeadertoAdd[0] = 0x00; + } + + LOG_MSG_STACK("Entering Function"); + memset(&sFilterRuleEntry, 0, sizeof(sFilterRuleEntry)); + memset(&sGetHeader, 0, sizeof(sGetHeader)); + + // Create Header: + // Allocate Memory, populate it, and add in to the Header Insertion. + struct ipa_ioc_add_hdr * pHeaderDescriptor = NULL; + pHeaderDescriptor = (struct ipa_ioc_add_hdr *) calloc(1, + sizeof(struct ipa_ioc_add_hdr) + + 1 * sizeof(struct ipa_hdr_add)); + if (!pHeaderDescriptor) { + LOG_MSG_ERROR("calloc failed to allocate pHeaderDescriptor"); + bRetVal = false; + goto bail; + } + + pHeaderDescriptor->commit = true; + pHeaderDescriptor->num_hdrs = 1; + // Adding Header No1. + strlcpy(pHeaderDescriptor->hdr[0].name, "StreamId0", sizeof(pHeaderDescriptor->hdr[0].name)); // Header's Name + memcpy(pHeaderDescriptor->hdr[0].hdr, (void*)&aHeadertoAdd, + hdrSize); //Header's Data + pHeaderDescriptor->hdr[0].hdr_len = hdrSize; + pHeaderDescriptor->hdr[0].hdr_hdl = -1; //Return Value + pHeaderDescriptor->hdr[0].is_partial = false; + pHeaderDescriptor->hdr[0].status = -1; // Return Parameter + + strlcpy(sGetHeader.name, pHeaderDescriptor->hdr[0].name, sizeof(sGetHeader.name)); + + + if (!m_HeaderInsertion.AddHeader(pHeaderDescriptor)) + { + LOG_MSG_ERROR("m_HeaderInsertion.AddHeader(pHeaderDescriptor) Failed."); + bRetVal = false; + goto bail; + } + + if (!m_HeaderInsertion.GetHeaderHandle(&sGetHeader)) + { + LOG_MSG_ERROR(" Failed"); + bRetVal = false; + goto bail; + } + LOG_MSG_DEBUG("Received Header Handle = 0x%x", sGetHeader.hdl); + + + if (!CreateBypassRoutingTable(&m_Routing, m_eIP, aBypass, IPA_CLIENT_TEST_CONS, + sGetHeader.hdl,&nTableHdl)) { + LOG_MSG_ERROR("CreateBypassRoutingTable Failed\n"); + bRetVal = false; + goto bail; + } + + + LOG_MSG_INFO("Creation of bypass routing table completed successfully"); + + // Creating Filtering Rules + cFilterTable0.Init(m_eIP,IPA_CLIENT_TEST_PROD, false, 1); + LOG_MSG_INFO("Creation of filtering table completed successfully"); + + // Configuring Filtering Rule No.1 + cFilterTable0.GeneratePresetRule(1,sFilterRuleEntry); + sFilterRuleEntry.at_rear = true; + sFilterRuleEntry.flt_rule_hdl=-1; // return Value + sFilterRuleEntry.status = -1; // return value + sFilterRuleEntry.rule.action=IPA_PASS_TO_ROUTING; + sFilterRuleEntry.rule.rt_tbl_hdl=nTableHdl; //put here the handle corresponding to Routing Rule 1 + sFilterRuleEntry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; // Destination IP Based Filtering + sFilterRuleEntry.rule.attrib.u.v4.dst_addr_mask = 0xFF0000FF; // Mask + sFilterRuleEntry.rule.attrib.u.v4.dst_addr = 0x7F000001; // Filter DST_IP == 127.0.0.1. + if ( + ((uint8_t)-1 == cFilterTable0.AddRuleToTable(sFilterRuleEntry)) || + !m_Filtering.AddFilteringRule(cFilterTable0.GetFilteringTable()) + ) + { + LOG_MSG_ERROR ("Adding Rule (0) to Filtering block Failed."); + bRetVal = false; + goto bail; + } else + { + LOG_MSG_DEBUG("flt rule hdl0=0x%x, status=0x%x\n", cFilterTable0.ReadRuleFromTable(0)->flt_rule_hdl,cFilterTable0.ReadRuleFromTable(0)->status); + } + +bail: + Free(pHeaderDescriptor); + LOG_MSG_STACK( + "Leaving Function (Returning %s)", bRetVal?"True":"False"); + return bRetVal; +} // AddRules() + +///////////////////////////////////////////////////////////////////////////////// + +bool MBIMAggregationTestFixtureConf11::AddRules1HeaderAggregation0Limits() { + m_eIP = IPA_IP_v4; + const char aBypass[20] = "Bypass1"; + uint32_t nTableHdl; + bool bRetVal = true; + IPAFilteringTable cFilterTable0; + struct ipa_flt_rule_add sFilterRuleEntry; + struct ipa_ioc_get_hdr sGetHeader; + uint8_t aHeadertoAdd[4]; + int hdrSize; + + if (mGenericAgg) { + hdrSize = 4; + aHeadertoAdd[0] = 0x49; + aHeadertoAdd[1] = 0x50; + aHeadertoAdd[2] = 0x53; + aHeadertoAdd[3] = 0x00; + } + else { + hdrSize = 1; + aHeadertoAdd[0] = 0x00; + } + + LOG_MSG_STACK("Entering Function"); + memset(&sFilterRuleEntry, 0, sizeof(sFilterRuleEntry)); + memset(&sGetHeader, 0, sizeof(sGetHeader)); + + // Create Header: + // Allocate Memory, populate it, and add in to the Header Insertion. + struct ipa_ioc_add_hdr * pHeaderDescriptor = NULL; + pHeaderDescriptor = (struct ipa_ioc_add_hdr *) calloc(1, + sizeof(struct ipa_ioc_add_hdr) + + 1 * sizeof(struct ipa_hdr_add)); + if (!pHeaderDescriptor) { + LOG_MSG_ERROR("calloc failed to allocate pHeaderDescriptor"); + bRetVal = false; + goto bail; + } + + pHeaderDescriptor->commit = true; + pHeaderDescriptor->num_hdrs = 1; + // Adding Header No1. + strlcpy(pHeaderDescriptor->hdr[0].name, "StreamId0", sizeof(pHeaderDescriptor->hdr[0].name)); // Header's Name + memcpy(pHeaderDescriptor->hdr[0].hdr, (void*)&aHeadertoAdd, + hdrSize); //Header's Data + pHeaderDescriptor->hdr[0].hdr_len = hdrSize; + pHeaderDescriptor->hdr[0].hdr_hdl = -1; //Return Value + pHeaderDescriptor->hdr[0].is_partial = false; + pHeaderDescriptor->hdr[0].status = -1; // Return Parameter + + strlcpy(sGetHeader.name, pHeaderDescriptor->hdr[0].name, sizeof(sGetHeader.name)); + + + if (!m_HeaderInsertion.AddHeader(pHeaderDescriptor)) + { + LOG_MSG_ERROR("m_HeaderInsertion.AddHeader(pHeaderDescriptor) Failed."); + bRetVal = false; + goto bail; + } + + if (!m_HeaderInsertion.GetHeaderHandle(&sGetHeader)) + { + LOG_MSG_ERROR(" Failed"); + bRetVal = false; + goto bail; + } + LOG_MSG_DEBUG("Received Header Handle = 0x%x", sGetHeader.hdl); + + + if (!CreateBypassRoutingTable(&m_Routing, m_eIP, aBypass, IPA_CLIENT_TEST4_CONS, + sGetHeader.hdl,&nTableHdl)) { + LOG_MSG_ERROR("CreateBypassRoutingTable Failed\n"); + bRetVal = false; + goto bail; + } + + + LOG_MSG_INFO("Creation of bypass routing table completed successfully"); + + // Creating Filtering Rules + cFilterTable0.Init(m_eIP,IPA_CLIENT_TEST_PROD, false, 1); + LOG_MSG_INFO("Creation of filtering table completed successfully"); + + // Configuring Filtering Rule No.1 + cFilterTable0.GeneratePresetRule(1,sFilterRuleEntry); + sFilterRuleEntry.at_rear = true; + sFilterRuleEntry.flt_rule_hdl=-1; // return Value + sFilterRuleEntry.status = -1; // return value + sFilterRuleEntry.rule.action=IPA_PASS_TO_ROUTING; + sFilterRuleEntry.rule.rt_tbl_hdl=nTableHdl; //put here the handle corresponding to Routing Rule 1 + sFilterRuleEntry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; // Destination IP Based Filtering + sFilterRuleEntry.rule.attrib.u.v4.dst_addr_mask = 0xFF0000FF; // Mask + sFilterRuleEntry.rule.attrib.u.v4.dst_addr = 0x7F000001; // Filter DST_IP == 127.0.0.1. + if ( + ((uint8_t)-1 == cFilterTable0.AddRuleToTable(sFilterRuleEntry)) || + !m_Filtering.AddFilteringRule(cFilterTable0.GetFilteringTable()) + ) + { + LOG_MSG_ERROR ("Adding Rule (0) to Filtering block Failed."); + bRetVal = false; + goto bail; + } else + { + LOG_MSG_DEBUG("flt rule hdl0=0x%x, status=0x%x\n", cFilterTable0.ReadRuleFromTable(0)->flt_rule_hdl,cFilterTable0.ReadRuleFromTable(0)->status); + } + +bail: + Free(pHeaderDescriptor); + LOG_MSG_STACK( + "Leaving Function (Returning %s)", bRetVal?"True":"False"); + return bRetVal; +} // AddRules() + +bool MBIMAggregationTestFixtureConf11::AddRulesAggDualFC(Pipe *input, Pipe *output1, Pipe *output2) { + m_eIP = IPA_IP_v4; + const char aBypass[2][20] = {"BypassTest2", "BypassTest4"}; + uint32_t nTableHdl[2]; + bool bRetVal = true; + IPAFilteringTable_v2 cFilterTable0; + struct ipa_flt_rule_add_v2 sFilterRuleEntry; + struct ipa_ioc_get_hdr sGetHeader; + uint8_t aHeadertoAdd[4]; + int hdrSize; + + if (mGenericAgg) { + hdrSize = 4; + aHeadertoAdd[0]= 0x49; + aHeadertoAdd[1] = 0x50; + aHeadertoAdd[2] = 0x53; + aHeadertoAdd[3] = 0x00; + } else { + hdrSize = 1; + aHeadertoAdd[0] = 0x00; + } + + LOG_MSG_STACK("Entering Function"); + memset(&sFilterRuleEntry, 0, sizeof(sFilterRuleEntry)); + memset(&sGetHeader, 0, sizeof(sGetHeader)); + + // Create Header: + // Allocate Memory, populate it, and add in to the Header Insertion. + struct ipa_ioc_add_hdr * pHeaderDescriptor = NULL; + pHeaderDescriptor = (struct ipa_ioc_add_hdr *) calloc(1, + sizeof(struct ipa_ioc_add_hdr) + + 1 * sizeof(struct ipa_hdr_add)); + if (!pHeaderDescriptor) { + LOG_MSG_ERROR("calloc failed to allocate pHeaderDescriptor"); + bRetVal = false; + goto bail; + } + + pHeaderDescriptor->commit = true; + pHeaderDescriptor->num_hdrs = 1; + // Adding Header No1. + strlcpy(pHeaderDescriptor->hdr[0].name, "StreamId0", sizeof(pHeaderDescriptor->hdr[0].name)); // Header's Name + memcpy(pHeaderDescriptor->hdr[0].hdr, aHeadertoAdd, hdrSize); //Header's Data + pHeaderDescriptor->hdr[0].hdr_len = hdrSize; + pHeaderDescriptor->hdr[0].hdr_hdl = -1; //Return Value + pHeaderDescriptor->hdr[0].is_partial = false; + pHeaderDescriptor->hdr[0].status = -1; // Return Parameter + + strlcpy(sGetHeader.name, pHeaderDescriptor->hdr[0].name, sizeof(sGetHeader.name)); + + + if (!m_HeaderInsertion.AddHeader(pHeaderDescriptor)) + { + LOG_MSG_ERROR("m_HeaderInsertion.AddHeader(pHeaderDescriptor) Failed."); + bRetVal = false; + goto bail; + } + + if (!m_HeaderInsertion.GetHeaderHandle(&sGetHeader)) + { + LOG_MSG_ERROR(" Failed"); + bRetVal = false; + goto bail; + } + LOG_MSG_DEBUG("Received Header Handle = 0x%x", sGetHeader.hdl); + + if (!CreateBypassRoutingTable_v2(&m_Routing, m_eIP, aBypass[0], + output1->GetClientType(), + sGetHeader.hdl, &nTableHdl[0], 0)) { + LOG_MSG_ERROR("CreateBypassRoutingTable Failed\n"); + bRetVal = false; + goto bail; + } + + if (!CreateBypassRoutingTable_v2(&m_Routing, m_eIP, aBypass[1], + output2->GetClientType(), + sGetHeader.hdl, &nTableHdl[1], 0)) { + LOG_MSG_ERROR("CreateBypassRoutingTable Failed\n"); + bRetVal = false; + goto bail; + } + + LOG_MSG_INFO("Creation of bypass routing tables completed successfully"); + + // Creating Filtering Rules + cFilterTable0.Init(m_eIP,input->GetClientType(), false, 2); + LOG_MSG_INFO("Creation of filtering table completed successfully"); + + // Configuring Filtering Rule No.1 + cFilterTable0.GeneratePresetRule(1,sFilterRuleEntry); + sFilterRuleEntry.at_rear = true; + sFilterRuleEntry.flt_rule_hdl=-1; // return Value + sFilterRuleEntry.status = -1; // return value + sFilterRuleEntry.rule.action=IPA_PASS_TO_ROUTING; + sFilterRuleEntry.rule.rt_tbl_hdl = nTableHdl[0]; //put here the handle corresponding to Routing Rule 1 + sFilterRuleEntry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; // Destination IP Based Filtering + sFilterRuleEntry.rule.attrib.u.v4.dst_addr_mask = 0xFF0000FF; // Mask + sFilterRuleEntry.rule.attrib.u.v4.dst_addr = 0x7F000001; // Filter DST_IP == 127.0.0.1. + sFilterRuleEntry.rule.close_aggr_irq_mod = 1; + if ( + ((uint8_t)-1 == cFilterTable0.AddRuleToTable(sFilterRuleEntry)) || + !m_Filtering.AddFilteringRule(cFilterTable0.GetFilteringTable()) + ) + { + LOG_MSG_ERROR ("Adding Rule (0) to Filtering block Failed."); + bRetVal = false; + goto bail; + } else + { + LOG_MSG_DEBUG("flt rule hdl0=0x%x, status=0x%x\n", cFilterTable0.ReadRuleFromTable(0)->flt_rule_hdl,cFilterTable0.ReadRuleFromTable(0)->status); + } + + // Configuring Filtering Rule No.2 + cFilterTable0.GeneratePresetRule(1,sFilterRuleEntry); + sFilterRuleEntry.at_rear = true; + sFilterRuleEntry.flt_rule_hdl=-1; // return Value + sFilterRuleEntry.status = -1; // return value + sFilterRuleEntry.rule.action=IPA_PASS_TO_ROUTING; + sFilterRuleEntry.rule.rt_tbl_hdl = nTableHdl[1]; //put here the handle corresponding to Routing Rule 1 + sFilterRuleEntry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; // Destination IP Based Filtering + sFilterRuleEntry.rule.attrib.u.v4.dst_addr_mask = 0xFF0000FF; // Mask + sFilterRuleEntry.rule.attrib.u.v4.dst_addr = 0x7F000002; // Filter DST_IP == 127.0.0.1. + sFilterRuleEntry.rule.close_aggr_irq_mod = 0; + if ( + ((uint8_t)-1 == cFilterTable0.AddRuleToTable(sFilterRuleEntry)) || + !m_Filtering.AddFilteringRule(cFilterTable0.GetFilteringTable()) + ) + { + LOG_MSG_ERROR ("Adding Rule (1) to Filtering block Failed."); + bRetVal = false; + goto bail; + } else + { + LOG_MSG_DEBUG("flt rule hdl1=0x%x, status=0x%x\n", cFilterTable0.ReadRuleFromTable(1)->flt_rule_hdl,cFilterTable0.ReadRuleFromTable(1)->status); + } + +bail: + Free(pHeaderDescriptor); + LOG_MSG_STACK( + "Leaving Function (Returning %s)", bRetVal?"True":"False"); + return bRetVal; +} // AddRulesAggDualFC() + +bool MBIMAggregationTestFixtureConf11::AddRulesAggDualFcRoutingBased(Pipe *input, Pipe *output1, Pipe *output2) { + m_eIP = IPA_IP_v4; + const char aBypass[2][20] = {"BypassTest2", "BypassTest4"}; + uint32_t nTableHdl[2]; + bool bRetVal = true; + IPAFilteringTable_v2 cFilterTable0; + struct ipa_flt_rule_add_v2 sFilterRuleEntry; + struct ipa_ioc_get_hdr sGetHeader; + uint8_t aHeadertoAdd[4]; + int hdrSize; + + if (mGenericAgg) { + hdrSize = 4; + aHeadertoAdd[0]= 0x49; + aHeadertoAdd[1] = 0x50; + aHeadertoAdd[2] = 0x53; + aHeadertoAdd[3] = 0x00; + } else { + hdrSize = 1; + aHeadertoAdd[0] = 0x00; + } + + LOG_MSG_STACK("Entering Function"); + memset(&sFilterRuleEntry, 0, sizeof(sFilterRuleEntry)); + memset(&sGetHeader, 0, sizeof(sGetHeader)); + + // Create Header: + // Allocate Memory, populate it, and add in to the Header Insertion. + struct ipa_ioc_add_hdr * pHeaderDescriptor = NULL; + pHeaderDescriptor = (struct ipa_ioc_add_hdr *) calloc(1, + sizeof(struct ipa_ioc_add_hdr) + + 1 * sizeof(struct ipa_hdr_add)); + if (!pHeaderDescriptor) { + LOG_MSG_ERROR("calloc failed to allocate pHeaderDescriptor"); + bRetVal = false; + goto bail; + } + + pHeaderDescriptor->commit = true; + pHeaderDescriptor->num_hdrs = 1; + // Adding Header No1. + strlcpy(pHeaderDescriptor->hdr[0].name, "StreamId0", sizeof(pHeaderDescriptor->hdr[0].name)); // Header's Name + memcpy(pHeaderDescriptor->hdr[0].hdr, aHeadertoAdd, hdrSize); //Header's Data + pHeaderDescriptor->hdr[0].hdr_len = hdrSize; + pHeaderDescriptor->hdr[0].hdr_hdl = -1; //Return Value + pHeaderDescriptor->hdr[0].is_partial = false; + pHeaderDescriptor->hdr[0].status = -1; // Return Parameter + + strlcpy(sGetHeader.name, pHeaderDescriptor->hdr[0].name, sizeof(sGetHeader.name)); + + + if (!m_HeaderInsertion.AddHeader(pHeaderDescriptor)) + { + LOG_MSG_ERROR("m_HeaderInsertion.AddHeader(pHeaderDescriptor) Failed."); + bRetVal = false; + goto bail; + } + + if (!m_HeaderInsertion.GetHeaderHandle(&sGetHeader)) + { + LOG_MSG_ERROR(" Failed"); + bRetVal = false; + goto bail; + } + LOG_MSG_DEBUG("Received Header Handle = 0x%x", sGetHeader.hdl); + + if (!CreateBypassRoutingTable_v2(&m_Routing, m_eIP, aBypass[0], + output1->GetClientType(), + sGetHeader.hdl, &nTableHdl[0], 1)) { + LOG_MSG_ERROR("CreateBypassRoutingTable Failed\n"); + bRetVal = false; + goto bail; + } + + if (!CreateBypassRoutingTable_v2(&m_Routing, m_eIP, aBypass[1], + output2->GetClientType(), + sGetHeader.hdl, &nTableHdl[1], 0)) { + LOG_MSG_ERROR("CreateBypassRoutingTable Failed\n"); + bRetVal = false; + goto bail; + } + + LOG_MSG_INFO("Creation of bypass routing tables completed successfully"); + + // Creating Filtering Rules + cFilterTable0.Init(m_eIP,input->GetClientType(), false, 2); + LOG_MSG_INFO("Creation of filtering table completed successfully"); + + // Configuring Filtering Rule No.1 + cFilterTable0.GeneratePresetRule(1,sFilterRuleEntry); + sFilterRuleEntry.at_rear = true; + sFilterRuleEntry.flt_rule_hdl=-1; // return Value + sFilterRuleEntry.status = -1; // return value + sFilterRuleEntry.rule.action=IPA_PASS_TO_ROUTING; + sFilterRuleEntry.rule.rt_tbl_hdl = nTableHdl[0]; //put here the handle corresponding to Routing Rule 1 + sFilterRuleEntry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; // Destination IP Based Filtering + sFilterRuleEntry.rule.attrib.u.v4.dst_addr_mask = 0xFF0000FF; // Mask + sFilterRuleEntry.rule.attrib.u.v4.dst_addr = 0x7F000001; // Filter DST_IP == 127.0.0.1. + sFilterRuleEntry.rule.close_aggr_irq_mod = 0; + if ( + ((uint8_t)-1 == cFilterTable0.AddRuleToTable(sFilterRuleEntry)) || + !m_Filtering.AddFilteringRule(cFilterTable0.GetFilteringTable()) + ) + { + LOG_MSG_ERROR ("Adding Rule (0) to Filtering block Failed."); + bRetVal = false; + goto bail; + } else + { + LOG_MSG_DEBUG("flt rule hdl0=0x%x, status=0x%x\n", cFilterTable0.ReadRuleFromTable(0)->flt_rule_hdl,cFilterTable0.ReadRuleFromTable(0)->status); + } + + // Configuring Filtering Rule No.2 + cFilterTable0.GeneratePresetRule(1,sFilterRuleEntry); + sFilterRuleEntry.at_rear = true; + sFilterRuleEntry.flt_rule_hdl=-1; // return Value + sFilterRuleEntry.status = -1; // return value + sFilterRuleEntry.rule.action=IPA_PASS_TO_ROUTING; + sFilterRuleEntry.rule.rt_tbl_hdl = nTableHdl[1]; //put here the handle corresponding to Routing Rule 1 + sFilterRuleEntry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; // Destination IP Based Filtering + sFilterRuleEntry.rule.attrib.u.v4.dst_addr_mask = 0xFF0000FF; // Mask + sFilterRuleEntry.rule.attrib.u.v4.dst_addr = 0x7F000002; // Filter DST_IP == 127.0.0.1. + sFilterRuleEntry.rule.close_aggr_irq_mod = 0; + if ( + ((uint8_t)-1 == cFilterTable0.AddRuleToTable(sFilterRuleEntry)) || + !m_Filtering.AddFilteringRule(cFilterTable0.GetFilteringTable()) + ) + { + LOG_MSG_ERROR ("Adding Rule (1) to Filtering block Failed."); + bRetVal = false; + goto bail; + } else + { + LOG_MSG_DEBUG("flt rule hdl1=0x%x, status=0x%x\n", cFilterTable0.ReadRuleFromTable(1)->flt_rule_hdl,cFilterTable0.ReadRuleFromTable(1)->status); + } + +bail: + Free(pHeaderDescriptor); + LOG_MSG_STACK( + "Leaving Function (Returning %s)", bRetVal?"True":"False"); + return bRetVal; +} // AddRulesAggDualFC() diff --git a/qcom/opensource/dataipa/kernel-tests/MBIMAggregationTestFixtureConf11.h b/qcom/opensource/dataipa/kernel-tests/MBIMAggregationTestFixtureConf11.h new file mode 100644 index 0000000000..f1c90731fe --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/MBIMAggregationTestFixtureConf11.h @@ -0,0 +1,115 @@ +/* + * Copyright (c) 2017,2020 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include + +#include "Constants.h" +#include "Logger.h" +#include "linux/msm_ipa.h" +#include "TestsUtils.h" +#include "TestBase.h" +#include "Pipe.h" +#include "RoutingDriverWrapper.h" +#include "HeaderInsertion.h" +#include "Filtering.h" +#include "IPAFilteringTable.h" + + +#define NUM_PACKETS 5 +#define NUM_PACKETS_FC 4 +#define MAX_PACKET_SIZE 1024 +#define MAX_PACKETS_IN_MBIM_TESTS 10 +#define MAX_PACKETS_IN_NDP 8 +#define MAX_NDPS_IN_PACKET 8 + +/*This class will be the base class of MBIM Aggregation tests. + *Any method other than the test case itself + *can be declared in this Fixture thus allowing the derived classes to + *implement only the test case. + *All the test of the Aggregation uses one input and one output in DMA mode. + */ +class MBIMAggregationTestFixtureConf11:public TestBase +{ +public: + /*This Constructor will register each instance that it creates.*/ + MBIMAggregationTestFixtureConf11(bool generic_agg); + + virtual int SetupKernelModule(); + + /*This method will create and initialize two Pipe object + *for the USB (Ethernet) Pipes, one + *for as input and the other as output. + */ + virtual bool Setup(); + + /*This method will destroy the pipes.*/ + virtual bool Teardown(); + + virtual bool Run(); + + virtual bool AddRules() = 0; + + virtual bool TestLogic() = 0; + + bool AddRules1HeaderAggregation(); + + bool AddRules1HeaderAggregation(bool bAggForceClose); + + bool AddRulesDeaggregation(); + + bool AddRules1HeaderAggregationTime(); + + bool AddRules1HeaderAggregation0Limits(); + + bool AddRulesAggDualFC(Pipe *input, Pipe *output1, Pipe *output2); + + bool AddRulesAggDualFcRoutingBased(Pipe *input, Pipe *output1, Pipe *output2); + + /*The client type are set from the + * peripheral perspective + */ + static Pipe m_IpaToUsbPipeAgg; + static Pipe m_UsbToIpaPipe; + static Pipe m_IpaToUsbPipe; + static Pipe m_UsbToIpaPipeDeagg; + static Pipe m_IpaToUsbPipeAggTime; + static Pipe m_IpaToUsbPipeAgg0Limits; + + static RoutingDriverWrapper m_Routing; + static Filtering m_Filtering; + static HeaderInsertion m_HeaderInsertion; + +protected: + enum ipa_ip_type m_eIP; + bool mGenericAgg; +}; diff --git a/qcom/opensource/dataipa/kernel-tests/MBIMAggregationTests.cpp b/qcom/opensource/dataipa/kernel-tests/MBIMAggregationTests.cpp new file mode 100644 index 0000000000..bd21434e0b --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/MBIMAggregationTests.cpp @@ -0,0 +1,3366 @@ +/* + * Copyright (c) 2017,2020 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include "hton.h" // for htonl +#include "MBIMAggregationTestFixtureConf11.h" +#include "Constants.h" +#include "TestsUtils.h" +#include "linux/msm_ipa.h" + +#define AGGREGATION_LOOP 4 +#define IPV4_DST_ADDR_OFFSET (16) + +///////////////////////////////////////////////////////////////////////////////// +// MBIM Aggregation scenarios // +///////////////////////////////////////////////////////////////////////////////// + +class MBIMAggregationScenarios { +public: + //MBIM Aggregation test - sends 5 packets and receives 1 aggregated packet + static bool MBIMAggregationTest(Pipe* input, Pipe* output, enum ipa_ip_type m_eIP); + //MBIM Deaggregation test - sends an aggregated packet made from 5 packets + //and receives 5 packets + static bool MBIMDeaggregationTest(Pipe* input, + Pipe* output, enum ipa_ip_type m_eIP); + //MBIM Deaggregation one packet test - sends an aggregated packet made from + //1 packet and receives 1 packet + static bool MBIMDeaggregationOnePacketTest(Pipe* input, Pipe* output, enum ipa_ip_type m_eIP); + //MBIM Deaggregation and Aggregation test - sends an aggregated packet made + //from 5 packets and receives the same aggregated packet + static bool MBIMDeaggregationAndAggregationTest(Pipe* input, Pipe* output, enum ipa_ip_type m_eIP); + //MBIM multiple Deaggregation and Aggregation test - sends 5 aggregated + //packets each one made of 1 packet and receives an aggregated packet made + //of the 5 packets + static bool MBIMMultipleDeaggregationAndAggregationTest( + Pipe* input, Pipe* output, + enum ipa_ip_type m_eIP); + //MBIM Aggregation Loop test - sends 5 packets and expects to receive 1 + //aggregated packet a few times + static bool MBIMAggregationLoopTest(Pipe* input, + Pipe* output, enum ipa_ip_type m_eIP); + //MBIM Aggregation time limit test - sends 1 small packet smaller than the + //byte limit and receives 1 aggregated packet + static bool MBIMAggregationTimeLimitTest(Pipe* input, Pipe* output, enum ipa_ip_type m_eIP); + //MBIM Aggregation byte limit test - sends 2 packets that together are + //larger than the byte limit + static bool MBIMAggregationByteLimitTest(Pipe* input, Pipe* output, enum ipa_ip_type m_eIP); + static bool MBIMAggregationByteLimitTestFC(Pipe* input, Pipe* output, enum ipa_ip_type m_eIP); + static bool MBIMAggregationDualDpTestFC(Pipe* input, Pipe* output1, Pipe* output2, enum ipa_ip_type m_eIP); + //MBIM Deaggregation multiple NDP test - sends an aggregated packet made + //from 5 packets and 2 NDPs and receives 5 packets + static bool MBIMDeaggregationMultipleNDPTest(Pipe* input, Pipe* output, enum ipa_ip_type m_eIP); + //MBIM Aggregation 2 pipes test - sends 3 packets from one pipe and an + //aggregated packet made of 2 packets from another pipe and receives 1 + //aggregated packet made of all 5 packets + static bool MBIMAggregation2PipesTest(Pipe* input1, Pipe* input2, Pipe* output, enum ipa_ip_type m_eIP); + //MBIM Aggregation time limit loop test - sends 5 small packet smaller than + //the byte limit and receives 5 aggregated packet + static bool MBIMAggregationTimeLimitLoopTest(Pipe* input, Pipe* output, enum ipa_ip_type m_eIP); + //MBIM Aggregation 0 limits test - sends 5 packets and expects to get each + //packet back aggregated (both size and time limits are 0) + static bool MBIMAggregation0LimitsTest(Pipe* input, Pipe* output, enum ipa_ip_type m_eIP); + //MBIM Aggregation multiple packets test - sends 9 packets with same stream + //ID and receives 1 aggregated packet with 2 NDPs + static bool MBIMAggregationMultiplePacketsTest(Pipe* input, Pipe* output, enum ipa_ip_type m_eIP); + //MBIM Aggregation different stream IDs test - sends 5 packets with + //different stream IDs and receives 1 aggregated packet made of 5 NDPs + static bool MBIMAggregationDifferentStreamIdsTest(Pipe* input, Pipe* output, enum ipa_ip_type m_eIP); + //MBIM Aggregation no interleaving stream IDs test - sends 5 packets with + //interleaving stream IDs (0, 1, 0, 1, 0) and receives 1 aggregated packet + //made of 5 NDPs + static bool MBIMAggregationNoInterleavingStreamIdsTest( + Pipe* input, Pipe* output, + enum ipa_ip_type m_eIP); + +private: + //This method will deaggregate an aggregated packet and compare the packets + //to the expected packets + static bool DeaggragateAndComparePackets( + Byte pAggregatedPacket[MAX_PACKET_SIZE], + Byte pExpectedPackets[MAX_PACKETS_IN_MBIM_TESTS][MAX_PACKET_SIZE], + int pPacketsSizes[MAX_PACKETS_IN_MBIM_TESTS], int nNumPackets, + int nAggregatedPacketSize); + //This method will aggregate packets + static void AggregatePackets( + Byte pAggregatedPacket[MAX_PACKET_SIZE]/*ouput*/, + Byte pPackets[NUM_PACKETS][MAX_PACKET_SIZE], + int pPacketsSizes[NUM_PACKETS], int nNumPackets, + int nAggregatedPacketSize); + //This method will aggregate packets and take into consideration their + //stream id to seperate them into different NDPs + static void AggregatePacketsWithStreamId( + Byte pAggregatedPacket[MAX_PACKET_SIZE]/*ouput*/, + Byte pPackets[NUM_PACKETS][MAX_PACKET_SIZE], + int pPacketsSizes[NUM_PACKETS], int nNumPackets, + int nAggregatedPacketSize, Byte pPacketsStreamId[NUM_PACKETS]); + //This method will deaggregate an aggregated packet made of one packet and + //compare the packet to the expected packet + static bool DeaggragateAndCompareOnePacket( + Byte pAggregatedPacket[MAX_PACKET_SIZE], + Byte pExpectedPacket[MAX_PACKET_SIZE], int nPacketsSize, + int nAggregatedPacketSize); + //This method will deaggregate an aggregated packet and compare the packets + //to the expected packets + static bool DeaggragateAndComparePacketsWithStreamId( + Byte pAggregatedPacket[MAX_PACKET_SIZE], + Byte pExpectedPackets[][MAX_PACKET_SIZE], int pPacketsSizes[], + int nNumPackets, int nAggregatedPacketSize, + Byte pPacketsStreamId[NUM_PACKETS]); +}; + +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// + +bool MBIMAggregationScenarios::MBIMAggregationTest( + Pipe* input, Pipe* output, enum ipa_ip_type m_eIP) +{ + //The packets that will be sent + Byte pPackets[NUM_PACKETS][MAX_PACKET_SIZE]; + //The real sizes of the packets that will be sent + int pPacketsSizes[NUM_PACKETS]; + //Buffer for the packet that will be received + Byte pReceivedPacket[2*MAX_PACKET_SIZE]; + //Total size of all sent packets (this is the max size of the aggregated + //packet minus the size of the header and the NDP) + int nTotalPacketsSize = MAX_PACKET_SIZE - (4 * NUM_PACKETS) - 24; + uint32_t nIPv4DSTAddr; + size_t pIpPacketsSizes[NUM_PACKETS]; + + //initialize the packets + for (int i = 0; i < NUM_PACKETS; i++) + { + if (NUM_PACKETS - 1 == i) + pPacketsSizes[i] = nTotalPacketsSize; + else + pPacketsSizes[i] = nTotalPacketsSize / NUM_PACKETS; + while (0 != pPacketsSizes[i] % 4) + { + pPacketsSizes[i]++; + } + nTotalPacketsSize -= pPacketsSizes[i]; + + // Load input data (IP packet) from file + pIpPacketsSizes[i] = MAX_PACKET_SIZE; + if (!LoadDefaultPacket(m_eIP, pPackets[i], pIpPacketsSizes[i])) + { + LOG_MSG_ERROR("Failed default Packet"); + return false; + } + nIPv4DSTAddr = ntohl(0x7F000001); + memcpy (&pPackets[i][IPV4_DST_ADDR_OFFSET],&nIPv4DSTAddr, + sizeof(nIPv4DSTAddr)); + int size = pIpPacketsSizes[i]; + while (size < pPacketsSizes[i]) + { + pPackets[i][size] = i; + size++; + } + + } + + //send the packets + for (int i = 0; i < NUM_PACKETS; i++) + { + LOG_MSG_DEBUG("Sending packet %d into the USB pipe(%d bytes)\n", i, + pPacketsSizes[i]); + int nBytesSent = input->Send(pPackets[i], pPacketsSizes[i]); + if (pPacketsSizes[i] != nBytesSent) + { + LOG_MSG_DEBUG("Sending packet %d into the USB pipe(%d bytes) " + "failed!\n", i, pPacketsSizes[i]); + return false; + } + } + + //receive the aggregated packet + LOG_MSG_DEBUG("Reading packet from the USB pipe(%d bytes should be there)" + "\n", MAX_PACKET_SIZE); + int nBytesReceived = output->Receive(pReceivedPacket, MAX_PACKET_SIZE); + if (MAX_PACKET_SIZE != nBytesReceived) + { + LOG_MSG_DEBUG("Receiving aggregated packet from the USB pipe(%d bytes) " + "failed!\n", MAX_PACKET_SIZE); + print_buff(pReceivedPacket, nBytesReceived); + return false; + } + //deaggregating the aggregated packet + return DeaggragateAndComparePackets(pReceivedPacket, pPackets, + pPacketsSizes, NUM_PACKETS, nBytesReceived); +} + +///////////////////////////////////////////////////////////////////////////////// + +bool MBIMAggregationScenarios::MBIMDeaggregationTest( + Pipe* input, Pipe* output, enum ipa_ip_type m_eIP) +{ + bool bTestResult = true; + //The packets that the aggregated packet will be made of + Byte pExpectedPackets[NUM_PACKETS][MAX_PACKET_SIZE]; + //The real sizes of the packets that the aggregated packet will be made of + int pPacketsSizes[NUM_PACKETS]; + //Buffers for the packets that will be received + Byte pReceivedPackets[NUM_PACKETS][MAX_PACKET_SIZE]; + //Total size of all the packets that the aggregated packet will be made of + //(this is the max size of the aggregated packet + //minus the size of the header and the NDP) + int nTotalPacketsSize = MAX_PACKET_SIZE - (4 * NUM_PACKETS) - 24; + //The aggregated packet that will be sent + Byte pAggregatedPacket[MAX_PACKET_SIZE] = {0}; + + uint32_t nIPv4DSTAddr; + size_t pIpPacketsSizes[NUM_PACKETS]; + + //initialize the packets + for (int i = 0; i < NUM_PACKETS; i++) + { + if (NUM_PACKETS - 1 == i) + pPacketsSizes[i] = nTotalPacketsSize; + else + pPacketsSizes[i] = nTotalPacketsSize / NUM_PACKETS; + while (0 != pPacketsSizes[i] % 4) + { + pPacketsSizes[i]++; + } + nTotalPacketsSize -= pPacketsSizes[i]; + // Load input data (IP packet) from file + pIpPacketsSizes[i] = MAX_PACKET_SIZE; + if (!LoadDefaultPacket(m_eIP, pExpectedPackets[i], + pIpPacketsSizes[i])) + { + LOG_MSG_ERROR("Failed default Packet"); + return false; + } + nIPv4DSTAddr = ntohl(0x7F000001); + memcpy (&pExpectedPackets[i][IPV4_DST_ADDR_OFFSET],&nIPv4DSTAddr, + sizeof(nIPv4DSTAddr)); + int size = pIpPacketsSizes[i]; + while (size < pPacketsSizes[i]) + { + pExpectedPackets[i][size] = i; + size++; + } + } + + //initializing the aggregated packet + AggregatePackets(pAggregatedPacket, pExpectedPackets, pPacketsSizes, + NUM_PACKETS, MAX_PACKET_SIZE); + + //send the aggregated packet + LOG_MSG_DEBUG("Sending aggregated packet into the USB pipe(%d bytes)\n", + sizeof(pAggregatedPacket)); + int nBytesSent = input->Send(pAggregatedPacket, sizeof(pAggregatedPacket)); + if (sizeof(pAggregatedPacket) != nBytesSent) + { + LOG_MSG_DEBUG("Sending aggregated packet into the USB pipe(%d bytes) " + "failed!\n", sizeof(pAggregatedPacket)); + return false; + } + + //receive the packets + for (int i = 0; i < NUM_PACKETS; i++) + { + LOG_MSG_DEBUG("Reading packet %d from the USB pipe(%d bytes should be " + "there)\n", i, pPacketsSizes[i]); + int nBytesReceived = output->Receive(pReceivedPackets[i], + pPacketsSizes[i]); + if (pPacketsSizes[i] != nBytesReceived) + { + LOG_MSG_DEBUG("Receiving packet %d from the USB pipe(%d bytes) " + "failed!\n", i, pPacketsSizes[i]); + print_buff(pReceivedPackets[i], nBytesReceived); + return false; + } + } + + //comparing the received packet to the aggregated packet + LOG_MSG_DEBUG("Checking sent.vs.received packet\n"); + for (int i = 0; i < NUM_PACKETS; i++) + bTestResult &= !memcmp(pExpectedPackets[i], pReceivedPackets[i], + pPacketsSizes[i]); + + return bTestResult; +} + +///////////////////////////////////////////////////////////////////////////////// + +bool MBIMAggregationScenarios::MBIMDeaggregationOnePacketTest( + Pipe* input, Pipe* output, + enum ipa_ip_type m_eIP) +{ + bool bTestResult = true; + //The packets that the aggregated packet will be made of + Byte pExpectedPackets[1][MAX_PACKET_SIZE]; + //The real sizes of the packets that the aggregated packet will be made of + int pPacketsSizes[1] = {100}; + //Buffers for the packets that will be received + Byte pReceivedPackets[1][MAX_PACKET_SIZE]; + //Total size of the aggregated packet + //(this is the max size of the aggregated packet + //minus the size of the header and the NDP) + int nTotalAggregatedPacketSize = 100 + 12 + 16; + //The aggregated packet that will be sent + Byte pAggregatedPacket[MAX_PACKET_SIZE] = {0}; + + uint32_t nIPv4DSTAddr; + size_t pIpPacketsSizes[1]; + + // Load input data (IP packet) from file + pIpPacketsSizes[0] = 100; + if (!LoadDefaultPacket(m_eIP, pExpectedPackets[0], pIpPacketsSizes[0])) + { + LOG_MSG_ERROR("Failed default Packet"); + return false; + } + nIPv4DSTAddr = ntohl(0x7F000001); + memcpy (&pExpectedPackets[0][IPV4_DST_ADDR_OFFSET],&nIPv4DSTAddr, + sizeof(nIPv4DSTAddr)); + int size = pIpPacketsSizes[0]; + while (size < pPacketsSizes[0]) + { + pExpectedPackets[0][size] = 0; + size++; + } + + + //initializing the aggregated packet + AggregatePackets(pAggregatedPacket, pExpectedPackets, pPacketsSizes, 1, + nTotalAggregatedPacketSize); + + //send the aggregated packet + LOG_MSG_DEBUG("Sending aggregated packet into the USB pipe(%d bytes)\n", + nTotalAggregatedPacketSize); + int nBytesSent = input->Send(pAggregatedPacket, nTotalAggregatedPacketSize); + if (nTotalAggregatedPacketSize != nBytesSent) + { + LOG_MSG_DEBUG("Sending aggregated packet into the USB pipe(%d bytes) " + "failed!\n", nTotalAggregatedPacketSize); + return false; + } + + //receive the packet + for (int i = 0; i < 1; i++) + { + LOG_MSG_DEBUG("Reading packet %d from the USB pipe(%d bytes should be " + "there)\n", i, pPacketsSizes[i]); + int nBytesReceived = output->Receive(pReceivedPackets[i], + pPacketsSizes[i]); + if (pPacketsSizes[i] != nBytesReceived) + { + LOG_MSG_DEBUG("Receiving packet %d from the USB pipe(%d bytes) " + "failed!\n", i, pPacketsSizes[i]); + print_buff(pReceivedPackets[i], nBytesReceived); + return false; + } + } + + //comparing the received packet to the aggregated packet + LOG_MSG_DEBUG("Checking sent.vs.received packet\n"); + for (int i = 0; i < 1; i++) + bTestResult &= !memcmp(pExpectedPackets[i], pReceivedPackets[i], + pPacketsSizes[i]); + + return bTestResult; +} + +///////////////////////////////////////////////////////////////////////////////// + +bool MBIMAggregationScenarios::MBIMDeaggregationAndAggregationTest( + Pipe* input, Pipe* output, + enum ipa_ip_type m_eIP) +{ + //The packets that the aggregated packet will be made of + Byte pPackets[NUM_PACKETS][MAX_PACKET_SIZE]; + //The real sizes of the packets that the aggregated packet will be made of + int pPacketsSizes[NUM_PACKETS]; + //Buffers for the packets that will be received + Byte pReceivedPacket[MAX_PACKET_SIZE]; + //Total size of all the packets that the aggregated packet will be made of + //(this is the max size of the aggregated packet + //minus the size of the header and the NDP) + int nTotalPacketsSize = MAX_PACKET_SIZE - (4 * NUM_PACKETS) - 24; + //The aggregated packet that will be sent + Byte pAggregatedPacket[MAX_PACKET_SIZE] = {0}; + uint32_t nIPv4DSTAddr; + size_t pIpPacketsSizes[NUM_PACKETS]; + + //initialize the packets + for (int i = 0; i < NUM_PACKETS; i++) + { + if (NUM_PACKETS - 1 == i) + pPacketsSizes[i] = nTotalPacketsSize; + else + pPacketsSizes[i] = nTotalPacketsSize / NUM_PACKETS; + while (0 != pPacketsSizes[i] % 4) + pPacketsSizes[i]++; + nTotalPacketsSize -= pPacketsSizes[i]; + + // Load input data (IP packet) from file + pIpPacketsSizes[i] = MAX_PACKET_SIZE; + if (!LoadDefaultPacket(m_eIP, pPackets[i], pIpPacketsSizes[i])) + { + LOG_MSG_ERROR("Failed default Packet"); + return false; + } + nIPv4DSTAddr = ntohl(0x7F000001); + memcpy (&pPackets[i][IPV4_DST_ADDR_OFFSET],&nIPv4DSTAddr, + sizeof(nIPv4DSTAddr)); + int size = pIpPacketsSizes[i]; + while (size < pPacketsSizes[i]) + { + pPackets[i][size] = i; + size++; + } + } + + //initializing the aggregated packet + AggregatePackets(pAggregatedPacket, pPackets, pPacketsSizes, NUM_PACKETS, + MAX_PACKET_SIZE); + + //send the aggregated packet + LOG_MSG_DEBUG("Sending aggregated packet into the USB pipe(%d bytes)\n", + MAX_PACKET_SIZE); + int nBytesSent = input->Send(pAggregatedPacket, MAX_PACKET_SIZE); + if (MAX_PACKET_SIZE != nBytesSent) + { + LOG_MSG_DEBUG("Sending aggregated packet into the USB pipe(%d bytes) " + "failed!\n", MAX_PACKET_SIZE); + return false; + } + + //receive the aggregated packet + LOG_MSG_DEBUG("Reading aggregated packet from the USB pipe(%d bytes should " + "be there)\n", MAX_PACKET_SIZE); + int nBytesReceived = output->Receive(pReceivedPacket, MAX_PACKET_SIZE); + if (MAX_PACKET_SIZE != nBytesReceived) + { + LOG_MSG_DEBUG("Receiving aggregated packet from the USB pipe(%d bytes) " + "failed!\n", MAX_PACKET_SIZE); + LOG_MSG_DEBUG("Received %d bytes\n", nBytesReceived); + print_buff(pReceivedPacket, nBytesReceived); + return false; + } + + + //comparing the received packet to the aggregated packet + LOG_MSG_DEBUG("Checking sent.vs.received packet\n"); + return DeaggragateAndComparePackets(pReceivedPacket, pPackets, pPacketsSizes, + NUM_PACKETS, nBytesReceived); +} + +///////////////////////////////////////////////////////////////////////////////// + +bool MBIMAggregationScenarios::MBIMMultipleDeaggregationAndAggregationTest( + Pipe* input, Pipe* output, + enum ipa_ip_type m_eIP) +{ + //The packets that the aggregated packets will be made of + Byte pPackets[NUM_PACKETS][MAX_PACKET_SIZE]; + //The real sizes of the packets that the aggregated packet will be made of + int pPacketsSizes[NUM_PACKETS]; + //Buffers for the packets that will be received + Byte pReceivedPacket[MAX_PACKET_SIZE]; + //Total size of all the packets that the aggregated packet will be made of + //(this is the max size of the aggregated packet + //minus the size of the header and the NDP) + int nTotalPacketsSize = MAX_PACKET_SIZE - (4 * NUM_PACKETS) - 24; + //The aggregated packet that will be sent + Byte pAggregatedPacket[NUM_PACKETS][MAX_PACKET_SIZE]; + uint32_t nIPv4DSTAddr; + size_t pIpPacketsSizes[NUM_PACKETS]; + + //initialize the packets + for (int i = 0; i < NUM_PACKETS; i++) + { + if (NUM_PACKETS - 1 == i) + pPacketsSizes[i] = nTotalPacketsSize; + else + pPacketsSizes[i] = nTotalPacketsSize / NUM_PACKETS; + while (0 != pPacketsSizes[i] % 4) + pPacketsSizes[i]++; + nTotalPacketsSize -= pPacketsSizes[i]; + + // Load input data (IP packet) from file + pIpPacketsSizes[i] = MAX_PACKET_SIZE; + if (!LoadDefaultPacket(m_eIP, pPackets[i], pIpPacketsSizes[i])) + { + LOG_MSG_ERROR("Failed default Packet"); + return false; + } + nIPv4DSTAddr = ntohl(0x7F000001); + memcpy (&pPackets[i][IPV4_DST_ADDR_OFFSET],&nIPv4DSTAddr, + sizeof(nIPv4DSTAddr)); + int size = pIpPacketsSizes[i]; + while (size < pPacketsSizes[i]) + { + pPackets[i][size] = i; + size++; + } + + } + + //initializing the aggregated packets + for (int i = 0; i < NUM_PACKETS; i++) + AggregatePackets(pAggregatedPacket[i], &pPackets[i], &pPacketsSizes[i], + 1, pPacketsSizes[i] + 12 + 16); + + //send the aggregated packets + for (int i = 0; i < NUM_PACKETS; i++) + { + LOG_MSG_DEBUG("Sending aggregated packet %d into the USB pipe(%d " + "bytes)\n", i, pPacketsSizes[i] + 12 + 16); + int nBytesSent = input->Send(pAggregatedPacket[i], + pPacketsSizes[i] + 12 + 16); + if (pPacketsSizes[i] + 12 + 16 != nBytesSent) + { + LOG_MSG_DEBUG("Sending aggregated packet %d into the USB pipe(%d " + "bytes) failed!\n", i, pPacketsSizes[i] + 12 + 16); + return false; + } + } + + //receive the aggregated packet + LOG_MSG_DEBUG("Reading aggregated packet from the USB pipe(%d bytes should " + "be there)\n", MAX_PACKET_SIZE); + int nBytesReceived = output->Receive(pReceivedPacket, MAX_PACKET_SIZE); + if (MAX_PACKET_SIZE != nBytesReceived) + { + LOG_MSG_DEBUG("Receiving aggregated packet from the USB pipe(%d bytes) " + "failed!\n", MAX_PACKET_SIZE); + LOG_MSG_DEBUG("Received %d bytes\n", nBytesReceived); + print_buff(pReceivedPacket, nBytesReceived); + return false; + } + + + //comparing the received packet to the aggregated packet + LOG_MSG_DEBUG("Checking sent.vs.received packet\n"); + return DeaggragateAndComparePackets(pReceivedPacket, pPackets, + pPacketsSizes, NUM_PACKETS, nBytesReceived); +} + +///////////////////////////////////////////////////////////////////////////////// + +bool MBIMAggregationScenarios::MBIMAggregationLoopTest( + Pipe* input, Pipe* output, enum ipa_ip_type m_eIP) +{ + //The packets that will be sent + Byte pPackets[NUM_PACKETS][MAX_PACKET_SIZE]; + //The real sizes of the packets that will be sent + int pPacketsSizes[NUM_PACKETS]; + //Buffer for the packet that will be received + Byte pReceivedPacket[MAX_PACKET_SIZE]; + //Total size of all sent packets (this is the max size of the aggregated + //packet minus the size of the header and the NDP) + int nTotalPacketsSize = MAX_PACKET_SIZE - (4 * NUM_PACKETS) - 24; + uint32_t nIPv4DSTAddr; + size_t pIpPacketsSizes[NUM_PACKETS]; + + //initialize the packets + for (int i = 0; i < NUM_PACKETS; i++) + { + if (NUM_PACKETS - 1 == i) + pPacketsSizes[i] = nTotalPacketsSize; + else + pPacketsSizes[i] = nTotalPacketsSize / NUM_PACKETS; + while (0 != pPacketsSizes[i] % 4) + pPacketsSizes[i]++; + nTotalPacketsSize -= pPacketsSizes[i]; + + // Load input data (IP packet) from file + pIpPacketsSizes[i] = MAX_PACKET_SIZE; + if (!LoadDefaultPacket(m_eIP, pPackets[i], pIpPacketsSizes[i])) + { + LOG_MSG_ERROR("Failed default Packet"); + return false; + } + nIPv4DSTAddr = ntohl(0x7F000001); + memcpy (&pPackets[i][IPV4_DST_ADDR_OFFSET],&nIPv4DSTAddr, + sizeof(nIPv4DSTAddr)); + int size = pIpPacketsSizes[i]; + while (size < pPacketsSizes[i]) + { + pPackets[i][size] = i; + size++; + } + } + + int num_iters = AGGREGATION_LOOP - 1; + for (int j = 0; j < num_iters; j++) + { + //send the packets + for (int i = 0; i < NUM_PACKETS; i++) + { + LOG_MSG_DEBUG("Sending packet %d into the USB pipe(%d bytes)\n", i, + pPacketsSizes[i]); + int nBytesSent = input->Send(pPackets[i], pPacketsSizes[i]); + if (pPacketsSizes[i] != nBytesSent) + { + LOG_MSG_DEBUG("Sending packet %d into the USB pipe(%d bytes) " + "failed!\n", i, pPacketsSizes[i]); + return false; + } + } + + memset(pReceivedPacket, 0, sizeof(pReceivedPacket)); + //receive the aggregated packet + LOG_MSG_DEBUG("Reading packet from the USB pipe(%d bytes should be " + "there)\n", MAX_PACKET_SIZE); + int nBytesReceived = output->Receive(pReceivedPacket, MAX_PACKET_SIZE); + if (MAX_PACKET_SIZE != nBytesReceived) + { + LOG_MSG_DEBUG("Receiving aggregated packet from the USB pipe(%d " + "bytes) failed!\n", MAX_PACKET_SIZE); + print_buff(pReceivedPacket, nBytesReceived); + return false; + } + + LOG_MSG_DEBUG("Checking sent.vs.received packet\n"); + if (false == DeaggragateAndComparePackets(pReceivedPacket, pPackets, + pPacketsSizes, NUM_PACKETS, nBytesReceived)) + { + LOG_MSG_DEBUG("Comparing aggregated packet failed!\n"); + return false; + } + + } + + return true; +} + +///////////////////////////////////////////////////////////////////////////////// + +bool MBIMAggregationScenarios::MBIMAggregationTimeLimitTest( + Pipe* input, Pipe* output, + enum ipa_ip_type m_eIP) +{ + //The packets that will be sent + Byte pPackets[1][MAX_PACKET_SIZE]; + //The real sizes of the packets that will be sent + int pPacketsSizes[1] = {0}; + //Buffer for the packet that will be received + Byte pReceivedPacket[MAX_PACKET_SIZE] = {0}; + //Size of aggregated packet + int nTotalPacketsSize = 24; + uint32_t nIPv4DSTAddr; + size_t pIpPacketsSizes[1]; + + //initialize the packets + for (int i = 0; i < 1 ; i++) + { + pPacketsSizes[i] = 52 + 4*i; + nTotalPacketsSize += pPacketsSizes[i] + 4; //size of the packet + 4 bytes for index and length + + // Load input data (IP packet) from file + pIpPacketsSizes[i] = MAX_PACKET_SIZE; + if (!LoadDefaultPacket(m_eIP, pPackets[i], pIpPacketsSizes[i])) + { + LOG_MSG_ERROR("Failed default Packet"); + return false; + } + nIPv4DSTAddr = ntohl(0x7F000001); + memcpy (&pPackets[i][IPV4_DST_ADDR_OFFSET],&nIPv4DSTAddr, + sizeof(nIPv4DSTAddr)); + int size = pIpPacketsSizes[i]; + while (size < pPacketsSizes[i]) + { + pPackets[i][size] = i; + size++; + } + } + int nAllPacketsSizes = 0; + for (int i = 0; i < 1; i++) + nAllPacketsSizes += pPacketsSizes[i]; + while (0 != nAllPacketsSizes % 4) + { + nAllPacketsSizes++; + nTotalPacketsSize++; //zero padding for NDP offset to be 4x + } + + //send the packets + for (int i = 0; i < 1; i++) + { + LOG_MSG_DEBUG("Sending packet %d into the USB pipe(%d bytes)\n", i, + pPacketsSizes[i]); + int nBytesSent = input->Send(pPackets[i], pPacketsSizes[i]); + if (pPacketsSizes[i] != nBytesSent) + { + LOG_MSG_DEBUG("Sending packet %d into the USB pipe(%d bytes) " + "failed!\n", i, pPacketsSizes[i]); + return false; + } + } + + //receive the aggregated packet + LOG_MSG_DEBUG("Reading packet from the USB pipe(%d bytes should be " + "there)\n", nTotalPacketsSize); + int nBytesReceived = output->Receive(pReceivedPacket, nTotalPacketsSize); + // IPA HW may add padding to the packets to align to 4B + if (nTotalPacketsSize > nBytesReceived) + { + LOG_MSG_DEBUG("Receiving aggregated packet from the USB pipe(%d bytes) " + "failed!\n", nTotalPacketsSize); + print_buff(pReceivedPacket, nBytesReceived); + return false; + } + + //comparing the received packet to the aggregated packet + LOG_MSG_DEBUG("Checking sent.vs.received packet\n"); + if (false == DeaggragateAndComparePackets(pReceivedPacket, pPackets, + pPacketsSizes, 1, nBytesReceived)) + { + LOG_MSG_DEBUG("Comparing aggregated packet failed!\n"); + print_buff(pReceivedPacket, nBytesReceived); + return false; + } + + return true; +} + +///////////////////////////////////////////////////////////////////////////////// + +bool MBIMAggregationScenarios::MBIMAggregationByteLimitTest( + Pipe* input, Pipe* output, + enum ipa_ip_type m_eIP) +{ + //The packets that will be sent + Byte pPackets[2][MAX_PACKET_SIZE]; + //The real sizes of the packets that will be sent + int pPacketsSizes[2]; + //Buffer for the packet that will be received + Byte pReceivedPacket[2*MAX_PACKET_SIZE] = {0}; + //Size of aggregated packet + int nTotalPacketsSize = 24; + uint32_t nIPv4DSTAddr; + size_t pIpPacketsSizes[2]; + + //initialize the packets + for (int i = 0; i < 2; i++) + { + pPacketsSizes[i] = (MAX_PACKET_SIZE / 2) + 10; + nTotalPacketsSize += pPacketsSizes[i] + 4; + + // Load input data (IP packet) from file + pIpPacketsSizes[i] = MAX_PACKET_SIZE; + if (!LoadDefaultPacket(m_eIP, pPackets[i], pIpPacketsSizes[i])) + { + LOG_MSG_ERROR("Failed default Packet"); + return false; + } + nIPv4DSTAddr = ntohl(0x7F000001); + memcpy (&pPackets[i][IPV4_DST_ADDR_OFFSET],&nIPv4DSTAddr, + sizeof(nIPv4DSTAddr)); + int size = pIpPacketsSizes[i]; + while (size < pPacketsSizes[i]) + { + pPackets[i][size] = i; + size++; + } + } + + + //send the packets + for (int i = 0; i < 2; i++) + { + LOG_MSG_DEBUG("Sending packet %d into the USB pipe(%d bytes)\n", i, + pPacketsSizes[i]); + int nBytesSent = input->Send(pPackets[i], pPacketsSizes[i]); + if (pPacketsSizes[i] != nBytesSent) + { + LOG_MSG_DEBUG("Sending packet %d into the USB pipe(%d bytes) " + "failed!\n", i, pPacketsSizes[i]); + return false; + } + } + + //receive the aggregated packet + LOG_MSG_DEBUG("Reading packet from the USB pipe(%d bytes should be " + "there)\n", nTotalPacketsSize); + int nBytesReceived = output->Receive(pReceivedPacket, nTotalPacketsSize); + // IPA HW may add padding to the packets to align to 4B + if (nTotalPacketsSize > nBytesReceived) + { + LOG_MSG_DEBUG("Receiving aggregated packet from the USB pipe(%d bytes) " + "failed!\n", nTotalPacketsSize); + print_buff(pReceivedPacket, nBytesReceived); + return false; + } + + //comparing the received packet to the aggregated packet + LOG_MSG_DEBUG("Checking sent.vs.received packet\n"); + if (false == DeaggragateAndComparePackets(pReceivedPacket, pPackets, + pPacketsSizes, 2, nBytesReceived)) + { + LOG_MSG_DEBUG("Comparing aggregated packet failed!\n"); + return false; + } + + return true; +} + +///////////////////////////////////////////////////////////////////////////////// + +bool MBIMAggregationScenarios::MBIMAggregationByteLimitTestFC( + Pipe *input, Pipe *output, + enum ipa_ip_type m_eIP) +{ + //The packets that will be sent + Byte pPackets[2][MAX_PACKET_SIZE]; + //The real sizes of the packets that will be sent + int pPacketsSizes[2]; + //Buffer for the packet that will be received + Byte pReceivedPacket[2][MAX_PACKET_SIZE] = {0}; + //Size of aggregated packet + int nTotalPacketsSize = 24 + (MAX_PACKET_SIZE / 2) + 8 + 4; + uint32_t nIPv4DSTAddr; + size_t pIpPacketsSizes[2]; + int nBytesReceived; + + for (int i = 0; i < 2; i++) + { + pPacketsSizes[i] = (MAX_PACKET_SIZE / 2) + 8; + + // Load input data (IP packet) from file + pIpPacketsSizes[i] = MAX_PACKET_SIZE; + if (!LoadDefaultPacket(m_eIP, pPackets[i], pIpPacketsSizes[i])) + { + LOG_MSG_ERROR("Failed default Packet"); + return false; + } + nIPv4DSTAddr = ntohl(0x7F000001); + memcpy (&pPackets[i][IPV4_DST_ADDR_OFFSET],&nIPv4DSTAddr, + sizeof(nIPv4DSTAddr)); + int size = pIpPacketsSizes[i]; + while (size < pPacketsSizes[i]) + { + pPackets[i][size] = i; + size++; + } + } + + + //send the packets + for (int i = 0; i < 2; i++) + { + LOG_MSG_DEBUG("Sending packet %d into the USB pipe(%d bytes)\n", i, + pPacketsSizes[i]); + int nBytesSent = input->Send(pPackets[i], pPacketsSizes[i]); + if (pPacketsSizes[i] != nBytesSent) + { + LOG_MSG_DEBUG("Sending packet %d into the USB pipe(%d bytes) " + "failed!\n", i, pPacketsSizes[i]); + return false; + } + } + + /* receive the packet */ + LOG_MSG_DEBUG( + "Reading packets from the USB pipe(%d bytes for each)" + "\n", nTotalPacketsSize); + for (int i = 0; i < 2; i++) + { + nBytesReceived = output->Receive(pReceivedPacket[i], MAX_PACKET_SIZE); + if (nTotalPacketsSize != nBytesReceived) + { + LOG_MSG_ERROR( + "Receiving aggregated packet from the USB pipe(%d bytes) " + "failed!\n", nBytesReceived); + print_buff(pReceivedPacket[i], nBytesReceived); + return false; + } + } + + //comparing the received packets to the aggregated packets + LOG_MSG_DEBUG("Checking sent.vs.received packets\n"); + for (int i = 0; i < 2; i++) + { + if (false == DeaggragateAndComparePackets(pReceivedPacket[i], + &pPackets[i], + (int *)&pPacketsSizes[i], + 1, + nBytesReceived)) + { + LOG_MSG_DEBUG("Comparing aggregated packet failed!\n"); + return false; + } + } + + return true; +} + +///////////////////////////////////////////////////////////////////////////////// +#define DUAL_FC_IP_PACKET_L ((MAX_PACKET_SIZE / 2) + 8) +#define DUAL_FC_1_AGG_PACKET_L (12 + DUAL_FC_IP_PACKET_L + 12 + 4) +#define DUAL_FC_2_AGG_PACKET_L (12 + DUAL_FC_IP_PACKET_L + DUAL_FC_IP_PACKET_L + 12 + 4 + 4) +bool MBIMAggregationScenarios::MBIMAggregationDualDpTestFC( + Pipe *input, Pipe *output1, Pipe *output2, + enum ipa_ip_type m_eIP) +{ + int i; + //The packets that will be sent + Byte pPackets[4][MAX_PACKET_SIZE]; + //The real sizes of the packets that will be sent + int pPacketsSizes[4]; + //Buffer for the packet that will be received + Byte pReceivedPacket[2 * MAX_PACKET_SIZE] = {0}; + Byte pReceivedPacketFC[2][MAX_PACKET_SIZE] = {0}; + uint32_t nIPv4DSTAddr; + size_t pIpPacketsSizes[4]; + int nBytesReceived; + + for (i = 0; i < 4; i++) + { + pPacketsSizes[i] = DUAL_FC_IP_PACKET_L; + + // Load input data (IP packet) from file + pIpPacketsSizes[i] = MAX_PACKET_SIZE; + if (!LoadDefaultPacket(m_eIP, pPackets[i], pIpPacketsSizes[i])) + { + LOG_MSG_ERROR("Failed default Packet"); + return false; + } + nIPv4DSTAddr = ntohl(0x7F000001 + (i & 0x1)); + memcpy(&pPackets[i][IPV4_DST_ADDR_OFFSET], &nIPv4DSTAddr, + sizeof(nIPv4DSTAddr)); + int size = pIpPacketsSizes[i]; + while (size < pPacketsSizes[i]) + { + pPackets[i][size] = 0xAA; + size++; + } + } + + //send the packets + for (int i = 0; i < 4; i++) + { + LOG_MSG_DEBUG("Sending packet %d into the USB pipe(%d bytes)\n", i, + pPacketsSizes[i]); + int nBytesSent = input->Send(pPackets[i], pPacketsSizes[i]); + if (pPacketsSizes[i] != nBytesSent) + { + LOG_MSG_DEBUG("Sending packet %d into the USB pipe(%d bytes) " + "failed!\n", i, pPacketsSizes[i]); + return false; + } + } + + /* receive the packets from FC pipe */ + LOG_MSG_DEBUG( + "Reading packets from the FC pipe (%d bytes for each)" + "\n", DUAL_FC_1_AGG_PACKET_L); + for (i = 0; i < 2; i++) + { + nBytesReceived = output1->Receive(pReceivedPacketFC[i], MAX_PACKET_SIZE); + if (DUAL_FC_1_AGG_PACKET_L != nBytesReceived) + { + LOG_MSG_ERROR( + "Receiving aggregated packet from the USB pipe (%d bytes) " + "failed!\n", nBytesReceived); + print_buff(pReceivedPacketFC[i], nBytesReceived); + return false; + } + } + + for (i = 0; i < 2; i++) + { + if (false == DeaggragateAndComparePackets(pReceivedPacketFC[i], + &pPackets[i * 2], + (int *)&pPacketsSizes[i * 2], + 1, + nBytesReceived)) + { + LOG_MSG_DEBUG("Comparing aggregated packet failed!\n"); + return false; + } + } + + /* receive the packet from non-FC pipe */ + LOG_MSG_DEBUG( + "Reading packet from the non-FC pipe (%d bytes)" + "\n", DUAL_FC_2_AGG_PACKET_L); + nBytesReceived = output2->Receive(pReceivedPacket, MAX_PACKET_SIZE); + if (DUAL_FC_2_AGG_PACKET_L != nBytesReceived) + { + LOG_MSG_ERROR( + "Receiving aggregated packet from the USB pipe (%d bytes) " + "failed!\n", nBytesReceived); + print_buff(pReceivedPacket, nBytesReceived); + return false; + } + + // Setting all source packets IP to 127.0.0.2 for comparison + nIPv4DSTAddr = ntohl(0x7F000002); + memcpy(&pPackets[0][IPV4_DST_ADDR_OFFSET], &nIPv4DSTAddr, sizeof(nIPv4DSTAddr)); + memcpy(&pPackets[2][IPV4_DST_ADDR_OFFSET], &nIPv4DSTAddr, sizeof(nIPv4DSTAddr)); + + if (false == DeaggragateAndComparePackets(&pReceivedPacket[0], pPackets, + (int *)&pPacketsSizes, 2, nBytesReceived)) + { + LOG_MSG_DEBUG("Comparing aggregated packet failed!\n"); + print_buff(pReceivedPacket, nBytesReceived); + return false; + } + + return true; +} + +///////////////////////////////////////////////////////////////////////////////// + +bool MBIMAggregationScenarios::MBIMDeaggregationMultipleNDPTest( + Pipe* input, Pipe* output, + enum ipa_ip_type m_eIP) +{ + bool bTestResult = true; + //The packets that the aggregated packet will be made of + Byte pExpectedPackets[NUM_PACKETS][MAX_PACKET_SIZE]; + //The real sizes of the packets that the aggregated packet will be made of + int pPacketsSizes[NUM_PACKETS]; + //Buffers for the packets that will be received + Byte pReceivedPackets[NUM_PACKETS][MAX_PACKET_SIZE]; + //Total size of all the packets that the aggregated packet will be made of + //(this is the max size of the aggregated packet + //minus the size of the header and the 2 NDPs) + int nTotalPacketsSize = MAX_PACKET_SIZE - (4 * NUM_PACKETS) - 36; + //The aggregated packet that will be sent + Byte pAggregatedPacket[MAX_PACKET_SIZE] = {0}; + //The stream Id byte for every packet - this will determine on which NDP the + //packet will appear + Byte pPacketsStreamId[NUM_PACKETS] = {0}; + uint32_t nIPv4DSTAddr; + size_t pIpPacketsSizes[NUM_PACKETS]; + + //initialize the packets + for (int i = 0; i < NUM_PACKETS; i++) + { + if (NUM_PACKETS - 1 == i) + pPacketsSizes[i] = nTotalPacketsSize; + else { + pPacketsSizes[i] = nTotalPacketsSize / NUM_PACKETS; + pPacketsSizes[i] += (pPacketsSizes[i] % 4 == 0 ? 0 : + 4 - pPacketsSizes[i] % 4); + } + nTotalPacketsSize -= pPacketsSizes[i]; + pPacketsStreamId[i] = i < 3 ? 0 : 1; + + // Load input data (IP packet) from file + pIpPacketsSizes[i] = MAX_PACKET_SIZE; + if (!LoadDefaultPacket(m_eIP, pExpectedPackets[i], + pIpPacketsSizes[i])) + { + LOG_MSG_ERROR("Failed default Packet"); + return false; + } + nIPv4DSTAddr = ntohl(0x7F000001); + memcpy (&pExpectedPackets[i][IPV4_DST_ADDR_OFFSET],&nIPv4DSTAddr, + sizeof(nIPv4DSTAddr)); + int size = pIpPacketsSizes[i]; + while (size < pPacketsSizes[i]) + { + pExpectedPackets[i][size] = i; + size++; + } + } + + //initializing the aggregated packet + AggregatePacketsWithStreamId(pAggregatedPacket, pExpectedPackets, + pPacketsSizes, NUM_PACKETS, MAX_PACKET_SIZE, pPacketsStreamId); + + //send the aggregated packet + LOG_MSG_DEBUG("Sending aggregated packet into the USB pipe(%d bytes)\n", + sizeof(pAggregatedPacket)); + int nBytesSent = input->Send(pAggregatedPacket, sizeof(pAggregatedPacket)); + if (sizeof(pAggregatedPacket) != nBytesSent) + { + LOG_MSG_DEBUG("Sending aggregated packet into the USB pipe(%d bytes) " + "failed!\n", sizeof(pAggregatedPacket)); + return false; + } + + //receive the packets + for (int i = 0; i < NUM_PACKETS; i++) + { + LOG_MSG_DEBUG("Reading packet %d from the USB pipe(%d bytes should be " + "there)\n", i, pPacketsSizes[i]); + int nBytesReceived = output->Receive(pReceivedPackets[i], + pPacketsSizes[i]); + if (pPacketsSizes[i] != nBytesReceived) + { + LOG_MSG_DEBUG("Receiving packet %d from the USB pipe(%d bytes) " + "failed!\n", i, pPacketsSizes[i]); + print_buff(pReceivedPackets[i], nBytesReceived); + return false; + } + } + + //comparing the received packet to the aggregated packet + LOG_MSG_DEBUG("Checking sent.vs.received packet\n"); + for (int i = 0; i < NUM_PACKETS; i++) + bTestResult &= !memcmp(pExpectedPackets[i], pReceivedPackets[i], + pPacketsSizes[i]); + + return bTestResult; +} + +///////////////////////////////////////////////////////////////////////////////// + +bool MBIMAggregationScenarios::MBIMAggregation2PipesTest( + Pipe* input1, Pipe* input2, Pipe* output, enum ipa_ip_type m_eIP) +{ + //The packets that will be sent + Byte pPackets[NUM_PACKETS][MAX_PACKET_SIZE]; + //The real sizes of the packets that will be sent + int pPacketsSizes[NUM_PACKETS]; + //Buffer for the packet that will be received + Byte pReceivedPacket[2*MAX_PACKET_SIZE]; + //Total size of all sent packets (this is the max size of the aggregated + //packet minus the size of the header and the NDP) + int nTotalPacketsSize = MAX_PACKET_SIZE - (4 * NUM_PACKETS) - 24; + //The aggregated packet that will be sent + Byte pAggregatedPacket[2][MAX_PACKET_SIZE]; + //The size of the sent aggregated packet + int nAggregatedPacketSize[2] = {0}; + uint32_t nIPv4DSTAddr; + size_t pIpPacketsSizes[NUM_PACKETS]; + + //initialize the packets + for (int i = 0; i < NUM_PACKETS; i++) + { + if (NUM_PACKETS - 1 == i) + pPacketsSizes[i] = nTotalPacketsSize; + else + pPacketsSizes[i] = nTotalPacketsSize / NUM_PACKETS; + while (0 != pPacketsSizes[i] % 4) + pPacketsSizes[i]++; + nTotalPacketsSize -= pPacketsSizes[i]; + + // Load input data (IP packet) from file + pIpPacketsSizes[i] = MAX_PACKET_SIZE; + if (!LoadDefaultPacket(m_eIP, pPackets[i], pIpPacketsSizes[i])) + { + LOG_MSG_ERROR("Failed default Packet"); + return false; + } + nIPv4DSTAddr = ntohl(0x7F000001); + memcpy (&pPackets[i][IPV4_DST_ADDR_OFFSET],&nIPv4DSTAddr, + sizeof(nIPv4DSTAddr)); + int size = pIpPacketsSizes[i]; + while (size < pPacketsSizes[i]) + { + pPackets[i][size] = i; + size++; + } + } + + + nAggregatedPacketSize[0] += pPacketsSizes[0] + pPacketsSizes[1]; //adding the packets + nAggregatedPacketSize[0] += 12; //adding the header + nAggregatedPacketSize[0] += 12 + 4*2; //adding the NDP + //initializing the aggregated packet + AggregatePackets(pAggregatedPacket[0], pPackets, pPacketsSizes, 2, + nAggregatedPacketSize[0]); + + //send the aggregated packet + + LOG_MSG_DEBUG("Sending aggregated packet into the USB pipe(%d " + "bytes)\n", nAggregatedPacketSize[0]); + int nBytesSent = input1->Send(pAggregatedPacket[0], + nAggregatedPacketSize[0]); + if (nAggregatedPacketSize[0] != nBytesSent) + { + LOG_MSG_DEBUG("Sending aggregated packet into the USB pipe(%d bytes) " + "failed!\n", nAggregatedPacketSize[0]); + return false; + } + + //send the packets + for (int i = 2; i < NUM_PACKETS; i++) + { + LOG_MSG_DEBUG("Sending packet %d into the USB pipe(%d bytes)\n", i, + pPacketsSizes[i]); + int nBytesSent = input2->Send(pPackets[i], pPacketsSizes[i]); + if (pPacketsSizes[i] != nBytesSent) + { + LOG_MSG_DEBUG("Sending packet %d into the USB pipe(%d bytes) " + "failed!\n", i, pPacketsSizes[i]); + return false; + } + } + + //receive the aggregated packet + LOG_MSG_DEBUG("Reading packet from the USB pipe(%d bytes should be " + "there)\n", MAX_PACKET_SIZE); + int nBytesReceived = output->Receive(pReceivedPacket, MAX_PACKET_SIZE); + if (MAX_PACKET_SIZE != nBytesReceived) + { + LOG_MSG_DEBUG("Receiving aggregated packet from the USB pipe(%d bytes) " + "failed!\n", MAX_PACKET_SIZE); + print_buff(pReceivedPacket, nBytesReceived); + return false; + } + + //deaggregating the aggregated packet + return DeaggragateAndComparePackets(pReceivedPacket, pPackets, pPacketsSizes, NUM_PACKETS, nBytesReceived); +} + +///////////////////////////////////////////////////////////////////////////////// + +bool MBIMAggregationScenarios::MBIMAggregationTimeLimitLoopTest( + Pipe* input, Pipe* output, + enum ipa_ip_type m_eIP) +{ + //The packets that will be sent + Byte pPackets[1][MAX_PACKET_SIZE]; + //The real sizes of the packets that will be sent + int pPacketsSizes[1] = {0}; + //Buffer for the packet that will be received + Byte pReceivedPacket[MAX_PACKET_SIZE] = {0}; + //Size of aggregated packet + int nTotalPacketsSize = 24; + uint32_t nIPv4DSTAddr; + size_t pIpPacketsSizes[NUM_PACKETS]; + + //initialize the packets + for (int i = 0; i < 1 ; i++) + { + pPacketsSizes[i] = 52 + 4*i; + nTotalPacketsSize += pPacketsSizes[i] + 4; //size of the packet + 4 bytes for index and length + + // Load input data (IP packet) from file + pIpPacketsSizes[i] = MAX_PACKET_SIZE; + if (!LoadDefaultPacket(m_eIP, pPackets[i], pIpPacketsSizes[i])) + { + LOG_MSG_ERROR("Failed default Packet"); + return false; + } + nIPv4DSTAddr = ntohl(0x7F000001); + memcpy (&pPackets[i][IPV4_DST_ADDR_OFFSET],&nIPv4DSTAddr, + sizeof(nIPv4DSTAddr)); + int size = pIpPacketsSizes[i]; + while (size < pPacketsSizes[i]) + { + pPackets[i][size] = i; + size++; + } + } + int nAllPacketsSizes = 0; + for (int i = 0; i < 1; i++) + nAllPacketsSizes += pPacketsSizes[i]; + while (0 != nAllPacketsSizes % 4) + { + nAllPacketsSizes++; + nTotalPacketsSize++; //zero padding for NDP offset to be 4x + } + + for (int k = 0; k < AGGREGATION_LOOP; k++) + { + //send the packets + for (int i = 0; i < 1; i++) + { + LOG_MSG_DEBUG("Sending packet %d into the USB pipe(%d bytes)\n", i, + pPacketsSizes[i]); + int nBytesSent = input->Send(pPackets[i], pPacketsSizes[i]); + if (pPacketsSizes[i] != nBytesSent) + { + LOG_MSG_DEBUG("Sending packet %d into the USB pipe(%d bytes) " + "failed!\n", i, pPacketsSizes[i]); + return false; + } + } + + //receive the aggregated packet + LOG_MSG_DEBUG("Reading packet from the USB pipe(%d bytes should be " + "there)\n", nTotalPacketsSize); + int nBytesReceived = output->Receive(pReceivedPacket, + nTotalPacketsSize); + // IPA HW may add padding to the packets to align to 4B + if (nTotalPacketsSize > nBytesReceived) + { + LOG_MSG_DEBUG("Receiving aggregated packet from the USB pipe(%d " + "bytes) failed!\n", nTotalPacketsSize); + print_buff(pReceivedPacket, nBytesReceived); + return false; + } + + //comparing the received packet to the aggregated packet + LOG_MSG_DEBUG("Checking sent.vs.received packet\n"); + if (false == DeaggragateAndComparePackets(pReceivedPacket, pPackets, + pPacketsSizes, 1, nBytesReceived)) + { + LOG_MSG_DEBUG("Comparing aggregated packet failed!\n"); + return false; + } + } + + return true; +} + +///////////////////////////////////////////////////////////////////////////////// + +bool MBIMAggregationScenarios::MBIMAggregation0LimitsTest( + Pipe* input, Pipe* output, + enum ipa_ip_type m_eIP) +{ + //The packets that will be sent + Byte pPackets[NUM_PACKETS][MAX_PACKET_SIZE]; + //The real sizes of the packets that will be sent + int pPacketsSizes[NUM_PACKETS]; + //Buffer for the packet that will be received + Byte pReceivedPackets[NUM_PACKETS][MAX_PACKET_SIZE]; + //The expected aggregated packets sizes + int pAggragatedPacketsSizes[NUM_PACKETS] = {0}; + uint32_t nIPv4DSTAddr; + size_t pIpPacketsSizes[NUM_PACKETS]; + + //initialize the packets + for (int i = 0; i < NUM_PACKETS ; i++) + { + pPacketsSizes[i] = 52 + 4*i; + + // Load input data (IP packet) from file + pIpPacketsSizes[i] = MAX_PACKET_SIZE; + if (!LoadDefaultPacket(m_eIP, pPackets[i], pIpPacketsSizes[i])) + { + LOG_MSG_ERROR("Failed default Packet"); + return false; + } + nIPv4DSTAddr = ntohl(0x7F000001); + memcpy (&pPackets[i][IPV4_DST_ADDR_OFFSET],&nIPv4DSTAddr, + sizeof(nIPv4DSTAddr)); + int size = pIpPacketsSizes[i]; + while (size < pPacketsSizes[i]) + { + pPackets[i][size] = i; + size++; + } + } + + //calculate aggregated packets sizes + for (int i = 0; i < NUM_PACKETS; i++) + { + pAggragatedPacketsSizes[i] += pPacketsSizes[i]; + while (0 != pAggragatedPacketsSizes[i] % 4) + pAggragatedPacketsSizes[i]++; //zero padding for NDP offset to be 4x + pAggragatedPacketsSizes[i] += 28; //header + NDP + } + + //send the packets + for (int i = 0; i < NUM_PACKETS; i++) + { + LOG_MSG_DEBUG("Sending packet %d into the USB pipe(%d bytes)\n", i, + pPacketsSizes[i]); + int nBytesSent = input->Send(pPackets[i], pPacketsSizes[i]); + if (pPacketsSizes[i] != nBytesSent) + { + LOG_MSG_DEBUG("Sending packet %d into the USB pipe(%d bytes) " + "failed!\n", i, pPacketsSizes[i]); + return false; + } + } + + //receive the aggregated packets + for (int i = 0; i < NUM_PACKETS; i++) + { + LOG_MSG_DEBUG("Reading packet %d from the USB pipe(%d bytes should be " + "there)\n", i, pAggragatedPacketsSizes[i]); + int nBytesReceived = output->Receive(pReceivedPackets[i], + pAggragatedPacketsSizes[i]); + // IPA HW may add padding to the packets to align to 4B + if (pAggragatedPacketsSizes[i] > nBytesReceived) + { + LOG_MSG_DEBUG("Receiving aggregated packet %d from the USB pipe(%d " + "bytes) failed!\n", i, pAggragatedPacketsSizes[i]); + print_buff(pReceivedPackets[i], nBytesReceived); + return false; + } + pAggragatedPacketsSizes[i] = nBytesReceived; + } + + + //comparing the received packet to the aggregated packet + LOG_MSG_DEBUG("Checking sent.vs.received packet\n"); + for (int i = 0; i < NUM_PACKETS; i++) + { + if (false == DeaggragateAndCompareOnePacket(pReceivedPackets[i], + pPackets[i], pPacketsSizes[i], pAggragatedPacketsSizes[i])) + { + LOG_MSG_DEBUG("Comparing aggregated packet %d failed!\n", i); + return false; + } + } + + return true; +} + +///////////////////////////////////////////////////////////////////////////////// + +bool MBIMAggregationScenarios::MBIMAggregationMultiplePacketsTest( + Pipe* input, Pipe* output, + enum ipa_ip_type m_eIP) +{ + //The packets that will be sent + Byte pPackets[MAX_PACKETS_IN_NDP + 1][MAX_PACKET_SIZE]; + //The real sizes of the packets that will be sent + int pPacketsSizes[MAX_PACKETS_IN_NDP + 1]; + //Buffer for the packet that will be received + Byte pReceivedPacket[2*MAX_PACKET_SIZE]; + uint32_t nIPv4DSTAddr; + size_t pIpPacketsSizes[MAX_PACKETS_IN_NDP + 1]; + //Total size of all sent packets (this is the max size of the aggregated packet + //minus the size of the header and the 2 NDPs) + int nTotalPacketsSize = MAX_PACKET_SIZE - (4 * (MAX_PACKETS_IN_NDP + 1)) - 24; + + //initialize the packets + for (int i = 0; i < MAX_PACKETS_IN_NDP + 1; i++) + { + if (MAX_PACKETS_IN_NDP == i) + pPacketsSizes[i] = nTotalPacketsSize; + else + { + pPacketsSizes[i] = nTotalPacketsSize / (MAX_PACKETS_IN_NDP + 1); + pPacketsSizes[i] += (pPacketsSizes[i] % 4 == 0 ? 0 : + 4 - pPacketsSizes[i] % 4); + } + nTotalPacketsSize -= pPacketsSizes[i]; + + // Load input data (IP packet) from file + pIpPacketsSizes[i] = MAX_PACKET_SIZE; + if (!LoadDefaultPacket(m_eIP, pPackets[i], pIpPacketsSizes[i])) + { + LOG_MSG_ERROR("Failed default Packet"); + return false; + } + nIPv4DSTAddr = ntohl(0x7F000001); + memcpy (&pPackets[i][IPV4_DST_ADDR_OFFSET],&nIPv4DSTAddr, + sizeof(nIPv4DSTAddr)); + int size = pIpPacketsSizes[i]; + while (size < pPacketsSizes[i]) + { + pPackets[i][size] = i; + size++; + } + } + + //send the packets + for (int i = 0; i < MAX_PACKETS_IN_NDP + 1; i++) + { + LOG_MSG_DEBUG("Sending packet %d into the USB pipe(%d bytes)\n", i, + pPacketsSizes[i]); + int nBytesSent = input->Send(pPackets[i], pPacketsSizes[i]); + + if (pPacketsSizes[i] != nBytesSent) + { + LOG_MSG_DEBUG("Sending packet %d into the USB pipe(%d bytes) " + "failed!\n", i, pPacketsSizes[i]); + return false; + } + } + + //receive the aggregated packet + LOG_MSG_DEBUG("Reading packet from the USB pipe(%d bytes should be " + "there)\n", MAX_PACKET_SIZE); + int nBytesReceived = output->Receive(pReceivedPacket, MAX_PACKET_SIZE); + if (MAX_PACKET_SIZE != nBytesReceived) + { + LOG_MSG_DEBUG("Receiving aggregated packet from the USB pipe(%d bytes) " + "failed!\n", MAX_PACKET_SIZE); + print_buff(pReceivedPacket, nBytesReceived); + return false; + } + + //deaggregating the aggregated packet + return DeaggragateAndComparePackets(pReceivedPacket, pPackets, + pPacketsSizes, MAX_PACKETS_IN_NDP+1, nBytesReceived); +} + +///////////////////////////////////////////////////////////////////////////////// + +bool MBIMAggregationScenarios::MBIMAggregationDifferentStreamIdsTest( + Pipe* input, Pipe* output, + enum ipa_ip_type m_eIP) +{ + //The packets that will be sent + Byte pPackets[NUM_PACKETS][MAX_PACKET_SIZE]; + //The real sizes of the packets that will be sent + int pPacketsSizes[NUM_PACKETS]; + //Buffer for the packet that will be received + Byte pReceivedPacket[2*MAX_PACKET_SIZE]; + //Total size of all sent packets (this is the max size of the aggregated + //packet minus the size of the header and the NDPs) + int nTotalPacketsSize = MAX_PACKET_SIZE - (16 * NUM_PACKETS) - 12; + uint32_t nIPv4DSTAddr; + size_t pIpPacketsSizes[NUM_PACKETS]; + Byte pPacketsStreamId[NUM_PACKETS]; + + //initialize the packets + for (int i = 0; i < NUM_PACKETS; i++) + { + pPacketsStreamId[i] = i; + if (NUM_PACKETS - 1 == i) + pPacketsSizes[i] = nTotalPacketsSize + 12; + else + pPacketsSizes[i] = nTotalPacketsSize / NUM_PACKETS; + while (0 != pPacketsSizes[i] % 4) + pPacketsSizes[i]++; + nTotalPacketsSize -= pPacketsSizes[i]; + + // Load input data (IP packet) from file + pIpPacketsSizes[i] = MAX_PACKET_SIZE; + if (!LoadDefaultPacket(m_eIP, pPackets[i], pIpPacketsSizes[i])) + { + LOG_MSG_ERROR("Failed default Packet"); + return false; + } + int size = pIpPacketsSizes[i]; + while (size < pPacketsSizes[i]) + { + pPackets[i][size] = i; + size++; + } + } + + nIPv4DSTAddr = ntohl(0x7F000001); + memcpy (&pPackets[0][IPV4_DST_ADDR_OFFSET],&nIPv4DSTAddr, + sizeof(nIPv4DSTAddr)); + nIPv4DSTAddr = ntohl(0xC0A80101); + memcpy (&pPackets[1][IPV4_DST_ADDR_OFFSET],&nIPv4DSTAddr, + sizeof(nIPv4DSTAddr)); + nIPv4DSTAddr = ntohl(0xC0A80102); + memcpy (&pPackets[2][IPV4_DST_ADDR_OFFSET],&nIPv4DSTAddr, + sizeof(nIPv4DSTAddr)); + nIPv4DSTAddr = ntohl(0xC0A80103); + memcpy (&pPackets[3][IPV4_DST_ADDR_OFFSET],&nIPv4DSTAddr, + sizeof(nIPv4DSTAddr)); + nIPv4DSTAddr = ntohl(0xC0A80104); + memcpy (&pPackets[4][IPV4_DST_ADDR_OFFSET],&nIPv4DSTAddr, + sizeof(nIPv4DSTAddr)); + + //send the packets + for (int i = 0; i < NUM_PACKETS; i++) + { + LOG_MSG_DEBUG("Sending packet %d into the USB pipe(%d bytes)\n", i, + pPacketsSizes[i]); + int nBytesSent = input->Send(pPackets[i], pPacketsSizes[i]); + if (pPacketsSizes[i] != nBytesSent) + { + LOG_MSG_DEBUG("Sending packet %d into the USB pipe(%d bytes) " + "failed!\n", i, pPacketsSizes[i]); + return false; + } + } + + //receive the aggregated packet + LOG_MSG_DEBUG("Reading packet from the USB pipe(%d bytes should be " + "there)\n", MAX_PACKET_SIZE + 12); + int nBytesReceived = output->Receive(pReceivedPacket, MAX_PACKET_SIZE + 12); + if (MAX_PACKET_SIZE + 12 != nBytesReceived) + { + LOG_MSG_DEBUG("Receiving aggregated packet from the USB pipe(%d bytes) " + "failed!\n", MAX_PACKET_SIZE + 12); + print_buff(pReceivedPacket, nBytesReceived + 12); + return false; + } + + //deaggregating the aggregated packet + return DeaggragateAndComparePacketsWithStreamId(pReceivedPacket, pPackets, + pPacketsSizes, NUM_PACKETS, nBytesReceived, pPacketsStreamId); +} + +///////////////////////////////////////////////////////////////////////////////// + +bool MBIMAggregationScenarios::MBIMAggregationNoInterleavingStreamIdsTest( + Pipe* input, Pipe* output, + enum ipa_ip_type m_eIP) +{ + //The packets that will be sent + Byte pPackets[NUM_PACKETS][MAX_PACKET_SIZE]; + //The real sizes of the packets that will be sent + int pPacketsSizes[NUM_PACKETS]; + //Buffer for the packet that will be received + Byte pReceivedPacket[2*MAX_PACKET_SIZE]; + //Total size of all sent packets (this is the max size of the aggregated packet + //minus the size of the header and the NDPs) + int nTotalPacketsSize = MAX_PACKET_SIZE - (16 * NUM_PACKETS) - 12; + uint32_t nIPv4DSTAddr; + size_t pIpPacketsSizes[NUM_PACKETS]; + Byte pPacketsStreamId[NUM_PACKETS]; + + //initialize the packets + for (int i = 0; i < NUM_PACKETS; i++) + { + pPacketsStreamId[i] = i % 2; + if (NUM_PACKETS - 1 == i) + pPacketsSizes[i] = nTotalPacketsSize + 12; + else + pPacketsSizes[i] = nTotalPacketsSize / NUM_PACKETS; + while (0 != pPacketsSizes[i] % 4) + pPacketsSizes[i]++; + nTotalPacketsSize -= pPacketsSizes[i]; + + // Load input data (IP packet) from file + pIpPacketsSizes[i] = MAX_PACKET_SIZE; + if (!LoadDefaultPacket(m_eIP, pPackets[i], pIpPacketsSizes[i])) + { + LOG_MSG_ERROR("Failed default Packet"); + return false; + } + int size = pIpPacketsSizes[i]; + while (size < pPacketsSizes[i]) + { + pPackets[i][size] = i; + size++; + } + } + + nIPv4DSTAddr = ntohl(0x7F000001); + memcpy (&pPackets[0][IPV4_DST_ADDR_OFFSET],&nIPv4DSTAddr, + sizeof(nIPv4DSTAddr)); + nIPv4DSTAddr = ntohl(0xC0A80101); + memcpy (&pPackets[1][IPV4_DST_ADDR_OFFSET],&nIPv4DSTAddr, + sizeof(nIPv4DSTAddr)); + nIPv4DSTAddr = ntohl(0x7F000001); + memcpy (&pPackets[2][IPV4_DST_ADDR_OFFSET],&nIPv4DSTAddr, + sizeof(nIPv4DSTAddr)); + nIPv4DSTAddr = ntohl(0xC0A80101); + memcpy (&pPackets[3][IPV4_DST_ADDR_OFFSET],&nIPv4DSTAddr, + sizeof(nIPv4DSTAddr)); + nIPv4DSTAddr = ntohl(0x7F000001); + memcpy (&pPackets[4][IPV4_DST_ADDR_OFFSET],&nIPv4DSTAddr, + sizeof(nIPv4DSTAddr)); + + //send the packets + for (int i = 0; i < NUM_PACKETS; i++) + { + LOG_MSG_DEBUG("Sending packet %d into the USB pipe(%d bytes)\n", i, + pPacketsSizes[i]); + int nBytesSent = input->Send(pPackets[i], pPacketsSizes[i]); + if (pPacketsSizes[i] != nBytesSent) + { + LOG_MSG_DEBUG("Sending packet %d into the USB pipe(%d bytes) " + "failed!\n", i, pPacketsSizes[i]); + return false; + } + } + + //receive the aggregated packet + LOG_MSG_DEBUG("Reading packet from the USB pipe(%d bytes should be " + "there)\n", MAX_PACKET_SIZE + 12); + int nBytesReceived = output->Receive(pReceivedPacket, + MAX_PACKET_SIZE + 12); + if (MAX_PACKET_SIZE + 12 != nBytesReceived) + { + LOG_MSG_DEBUG("Receiving aggregated packet from the USB pipe(%d bytes)" + " failed!\n", MAX_PACKET_SIZE + 12); + print_buff(pReceivedPacket, nBytesReceived + 12); + return false; + } + + //deaggregating the aggregated packet + return DeaggragateAndComparePacketsWithStreamId(pReceivedPacket, pPackets, + pPacketsSizes, NUM_PACKETS, nBytesReceived, pPacketsStreamId); +} + +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// + +bool MBIMAggregationScenarios::DeaggragateAndComparePackets( + Byte pAggregatedPacket[MAX_PACKET_SIZE], + Byte pExpectedPackets[MAX_PACKETS_IN_MBIM_TESTS][MAX_PACKET_SIZE], + int pPacketsSizes[MAX_PACKETS_IN_MBIM_TESTS], int nNumPackets, int nAggregatedPacketSize) +{ + int nPacketNum = 0; + int i = 0; + int nNdpStart = 0; + Byte pNdpIndex[2] = {0}; + Byte pNdpLen[2] = {0}; + if (0x4e != pAggregatedPacket[i] || 0x43 != pAggregatedPacket[i+1] || + 0x4d != pAggregatedPacket[i+2]|| 0x48 != pAggregatedPacket[i+3]) + { + LOG_MSG_DEBUG("Error: Wrong NTH16 signature: 0x%02x 0x%02x 0x%02x " + "0x%02x(should be 0x4e, 0x43, 0x4d, 0x48)\n", + pAggregatedPacket[i], pAggregatedPacket[i+1], + pAggregatedPacket[i+2], pAggregatedPacket[i+3]); + return false; + } + i += 4; + if (0x0c != pAggregatedPacket[i] || 0x00 != pAggregatedPacket[i+1]) + { + LOG_MSG_DEBUG("Error: Wrong header length: 0x%02x 0x%02x(should be 0x0c, " + "0x00)\n", + pAggregatedPacket[i], pAggregatedPacket[i+1]); + return false; + } + i += 4; //ignoring sequence number + if ((nAggregatedPacketSize & 0x00FF) != pAggregatedPacket[i] || + (nAggregatedPacketSize >> 8) != pAggregatedPacket[i+1]) + { + LOG_MSG_DEBUG("Error: Wrong aggregated packet length: 0x%02x 0x%02x" + "(should be 0x%02x, 0x%02x)\n", + pAggregatedPacket[i], pAggregatedPacket[i+1], + nAggregatedPacketSize & 0x00FF, nAggregatedPacketSize >> 8); + return false; + } + i += 2; + pNdpIndex[0] = pAggregatedPacket[i]; //least significant byte + pNdpIndex[1] = pAggregatedPacket[i+1]; //most significant byte + //reading the NDP + while (0x00 != pNdpIndex[0] || 0x00 != pNdpIndex[1]) + { + i = pNdpIndex[0] + 256*pNdpIndex[1]; //NDP should begin here + nNdpStart = i; + + if (0x49 != pAggregatedPacket[i] || 0x50 != pAggregatedPacket[i + 1] || + 0x53 != pAggregatedPacket[i + 2] || 0x00 != pAggregatedPacket[i + 3]) + { + LOG_MSG_DEBUG("Error: Wrong NDP16 signature: 0x%02x 0x%02x " + "0x%02x 0x%02x(should be 0x49, 0x50, 0x53, 0x00)\n", + pAggregatedPacket[i], pAggregatedPacket[i + 1], + pAggregatedPacket[i + 2], pAggregatedPacket[i + 3]); + return false; + } + i += 4; + pNdpLen[0] = pAggregatedPacket[i]; //least significant byte + pNdpLen[1] = pAggregatedPacket[i+1]; //most significant byte + if (0x00 != pAggregatedPacket[nNdpStart + pNdpLen[0] + 256*pNdpLen[1] - 2] || + 0x00 != pAggregatedPacket[nNdpStart + pNdpLen[0] + 256*pNdpLen[1] -1]) + { + LOG_MSG_DEBUG("Error: Wrong end of NDP: 0x%02x 0x%02x(should be 0x00," + " 0x00)\n", + pAggregatedPacket[nNdpStart + pNdpLen[0] + 256*pNdpLen[1] - 2], + pAggregatedPacket[nNdpStart + pNdpLen[0] + 256*pNdpLen[1] - 1]); + return false; + } + i += 2; + pNdpIndex[0] = pAggregatedPacket[i]; //least significant byte + pNdpIndex[1] = pAggregatedPacket[i+1]; //most significant byte + i += 2; + while (i <= nNdpStart + pNdpLen[0] + 256*pNdpLen[1] - 2) + { //going over all the datagrams in this NDP + Byte pDatagramIndex[2] = {0}; + Byte pDatagramLen[2] = {0}; + int packetIndex = 0; + pDatagramIndex[0] = pAggregatedPacket[i]; //least significant byte + pDatagramIndex[1] = pAggregatedPacket[i+1]; //most significant byte + i += 2; + if (0x00 == pDatagramIndex[0] && 0x00 == pDatagramIndex[1]) + break; //zero padding after all datagrams + if (nPacketNum >= nNumPackets) + { + LOG_MSG_DEBUG("Error: wrong number of packets: %d(should be %d)\n", + nPacketNum, nNumPackets); + return false; + } + pDatagramLen[0] = pAggregatedPacket[i]; //least significant byte + pDatagramLen[1] = pAggregatedPacket[i+1]; //most significant byte + i += 2; + packetIndex = pDatagramIndex[0] + 256*pDatagramIndex[1]; + if (pDatagramLen[0] + 256*pDatagramLen[1] != pPacketsSizes[nPacketNum]) + { + LOG_MSG_DEBUG("Error: Wrong packet %d length: 0x%02x 0x%02x" + "(should be %d)\n", nPacketNum, pDatagramLen[0], + pDatagramLen[1], pPacketsSizes[nPacketNum]); + return false; + } + if (0 != memcmp(pExpectedPackets[nPacketNum], + &pAggregatedPacket[packetIndex], pPacketsSizes[nPacketNum])) + { + LOG_MSG_DEBUG("Error: Comparison of packet %d failed!\n", + nPacketNum); + + return false; + } + nPacketNum++; + } + } + + return true; +} + +///////////////////////////////////////////////////////////////////////////////// + +void MBIMAggregationScenarios::AggregatePackets( + Byte pAggregatedPacket[MAX_PACKET_SIZE]/*ouput*/, + Byte pPackets[NUM_PACKETS][MAX_PACKET_SIZE], + int pPacketsSizes[NUM_PACKETS], int nNumPackets, + int nAggregatedPacketSize) +{ + int i = 0; + int pDatagramIndexes[NUM_PACKETS] = {0}; + int nNdpIndex = 0; + int nNdpLen = 0; + //NTH16 signature + pAggregatedPacket[i] = 0x4e; + pAggregatedPacket[i+1] = 0x43; + pAggregatedPacket[i+2] = 0x4d; + pAggregatedPacket[i+3] = 0x48; + i += 4; + //header length + pAggregatedPacket[i] = 0x0c; + pAggregatedPacket[i+1] = 0x00; + i += 2; + //sequence number + pAggregatedPacket[i] = 0x00; + pAggregatedPacket[i+1] = 0x00; + i += 2; + //aggregated packet length + pAggregatedPacket[i] = nAggregatedPacketSize & 0x00FF; + pAggregatedPacket[i+1] = nAggregatedPacketSize >> 8; + i += 2; + //NDP index + for (int j = 0; j < nNumPackets; j++) + nNdpIndex += pPacketsSizes[j]; + nNdpIndex += i + 2; + while (0 != nNdpIndex % 4) + nNdpIndex++; + pAggregatedPacket[i] = nNdpIndex & 0x00FF; + pAggregatedPacket[i+1] = nNdpIndex >> 8; + i += 2; + //packets + for (int j = 0; j < nNumPackets; j++) + { + pDatagramIndexes[j] = i; + for (int k = 0; k < pPacketsSizes[j]; k++) + { + pAggregatedPacket[i] = pPackets[j][k]; + i++; + } + } + while (i < nNdpIndex) + { + pAggregatedPacket[i] = 0x00; + i++; + } + + //NDP16 signature + pAggregatedPacket[i] = 0x49; + pAggregatedPacket[i+1] = 0x50; + pAggregatedPacket[i+2] = 0x53; + pAggregatedPacket[i+3] = 0x00; + i += 4; + //NDP length + nNdpLen = 4*nNumPackets + 8 + 2; + while (nNdpLen % 4 != 0) + nNdpLen += 2; + pAggregatedPacket[i] = nNdpLen & 0x00FF; + pAggregatedPacket[i+1] = nNdpLen >> 8; + i += 2; + //next NDP + pAggregatedPacket[i] = 0x00; + pAggregatedPacket[i+1] = 0x00; + i += 2; + for (int j = 0; j < nNumPackets; j++) + { + //datagram index + pAggregatedPacket[i] = pDatagramIndexes[j] & 0x00FF; + pAggregatedPacket[i+1] = pDatagramIndexes[j] >> 8; + i += 2; + //datagram length + pAggregatedPacket[i] = pPacketsSizes[j] & 0x00FF; + pAggregatedPacket[i+1] = pPacketsSizes[j] >> 8; + i += 2; + } + //zeros in the end of NDP + while (i < nAggregatedPacketSize) + { + pAggregatedPacket[i] = 0x00; + i++; + } +} + +///////////////////////////////////////////////////////////////////////////////// + +void MBIMAggregationScenarios::AggregatePacketsWithStreamId( + Byte pAggregatedPacket[MAX_PACKET_SIZE]/*ouput*/, + Byte pPackets[NUM_PACKETS][MAX_PACKET_SIZE], + int pPacketsSizes[NUM_PACKETS], int nNumPackets, int nAggregatedPacketSize, + Byte pPacketsStreamId[NUM_PACKETS]) +{ + int i = 0; + int n = 0; + int pDatagramIndexes[NUM_PACKETS] = {0}; + int nNdpIndex[NUM_PACKETS] = {0}; + int nNdpLen = 0; + Byte currStreamId = pPacketsStreamId[0]; + int nNdpFirstPacket[NUM_PACKETS] = {0}; + int nNdpAfterLastPacket[NUM_PACKETS] = {0}; + int nNumNDPs = 0; + for (n = 0; n < nNumPackets; n++) + { + if (currStreamId != pPacketsStreamId[n]) + { + nNdpAfterLastPacket[nNumNDPs] = n; + nNumNDPs++; + nNdpFirstPacket[nNumNDPs] = n; + currStreamId = pPacketsStreamId[n]; + } + } + nNdpAfterLastPacket[nNumNDPs] = n; + nNumNDPs++; + //calculate NDP indexes + nNdpIndex[0] += 12; //adding the header + for (int j = 0; j < nNumNDPs; j++) + { + for (n = nNdpFirstPacket[j]; n < nNdpAfterLastPacket[j]; n++) + nNdpIndex[j] += pPacketsSizes[n]; //adding the packets + while (0 != nNdpIndex[j] % 4) + nNdpIndex[j]++; + if (j < nNumNDPs - 1) + nNdpIndex[j+1] += nNdpIndex[j] + 12 + 4*(nNdpAfterLastPacket[j] - + nNdpFirstPacket[j]); //adding the location after the current NDP to the next NDP + } + //start building the aggregated packet + //NTH16 signature + pAggregatedPacket[i] = 0x4e; + pAggregatedPacket[i+1] = 0x43; + pAggregatedPacket[i+2] = 0x4d; + pAggregatedPacket[i+3] = 0x48; + i += 4; + //header length + pAggregatedPacket[i] = 0x0c; + pAggregatedPacket[i+1] = 0x00; + i += 2; + //sequence number + pAggregatedPacket[i] = 0x00; + pAggregatedPacket[i+1] = 0x00; + i += 2; + //aggregated packet length + pAggregatedPacket[i] = nAggregatedPacketSize & 0x00FF; + pAggregatedPacket[i+1] = nAggregatedPacketSize >> 8;; + i += 2; + //first NDP index + pAggregatedPacket[i] = nNdpIndex[0] & 0x00FF; + pAggregatedPacket[i+1] = nNdpIndex[0] >> 8; + i += 2; + for (n = 0; n < nNumNDPs; n++) + { + //packets + for (int j = nNdpFirstPacket[n]; j < nNdpAfterLastPacket[n]; j++) + { + pDatagramIndexes[j] = i; + for (int k = 0; k < pPacketsSizes[j]; k++) + { + pAggregatedPacket[i] = pPackets[j][k]; + i++; + } + } + while (i < nNdpIndex[n]) + { + pAggregatedPacket[i] = 0x00; + i++; + } + //NDP signature + pAggregatedPacket[i] = 0x49; + pAggregatedPacket[i+1] = 0x50; + pAggregatedPacket[i+2] = 0x53; + pAggregatedPacket[i+3] = pPacketsStreamId[nNdpFirstPacket[n]]; + i += 4; + //NDP length + nNdpLen = 4*(nNdpAfterLastPacket[n] - nNdpFirstPacket[n]) + 8 + 2; + while (nNdpLen % 4 != 0) + nNdpLen += 2; + pAggregatedPacket[i] = nNdpLen & 0x00FF; + pAggregatedPacket[i+1] = nNdpLen >> 8; + i += 2; + //next NDP + pAggregatedPacket[i] = nNdpIndex[n+1] & 0x00FF; + pAggregatedPacket[i+1] = nNdpIndex[n+1] >> 8; + i += 2; + for (int j = nNdpFirstPacket[n]; j < nNdpAfterLastPacket[n]; j++) + { + //datagram index + pAggregatedPacket[i] = pDatagramIndexes[j] & 0x00FF; + pAggregatedPacket[i+1] = pDatagramIndexes[j] >> 8; + i += 2; + //datagram length + pAggregatedPacket[i] = pPacketsSizes[j] & 0x00FF; + pAggregatedPacket[i+1] = pPacketsSizes[j] >> 8; + i += 2; + } + //zeros in the end of NDP + while (i < nNdpIndex[n] + nNdpLen) + { + pAggregatedPacket[i] = 0x00; + i++; + } + } +} + +///////////////////////////////////////////////////////////////////////////////// + +bool MBIMAggregationScenarios::DeaggragateAndCompareOnePacket( + Byte pAggregatedPacket[MAX_PACKET_SIZE], + Byte pExpectedPacket[MAX_PACKET_SIZE], int nPacketsSize, + int nAggregatedPacketSize) +{ + int nPacketNum = 0; + int i = 0; + int nNdpStart = 0; + Byte pNdpIndex[2] = {0}; + Byte pNdpLen[2] = {0}; + if (0x4e != pAggregatedPacket[i] || 0x43 != pAggregatedPacket[i+1] || + 0x4d != pAggregatedPacket[i+2]|| 0x48 != pAggregatedPacket[i+3]) + { + LOG_MSG_DEBUG("Error: Wrong NTH16 signature: 0x%02x 0x%02x 0x%02x " + "0x%02x(should be 0x4e, 0x43, 0x4d, 0x48)\n", + pAggregatedPacket[i], pAggregatedPacket[i+1], + pAggregatedPacket[i+2], pAggregatedPacket[i+3]); + return false; + } + i += 4; + if (0x0c != pAggregatedPacket[i] || 0x00 != pAggregatedPacket[i+1]) + { + LOG_MSG_DEBUG("Error: Wrong header length: 0x%02x 0x%02x(should be 0x0c," + " 0x00)\n", pAggregatedPacket[i], pAggregatedPacket[i+1]); + return false; + } + i += 4; //ignoring sequence number + if ((nAggregatedPacketSize & 0x00FF) != pAggregatedPacket[i] || + (nAggregatedPacketSize >> 8) != pAggregatedPacket[i+1]) + { + LOG_MSG_DEBUG("Error: Wrong aggregated packet length: 0x%02x 0x%02x" + "(should be 0x%02x, 0x%02x)\n", + pAggregatedPacket[i], pAggregatedPacket[i+1], + nAggregatedPacketSize & 0x00FF, nAggregatedPacketSize >> 8); + return false; + } + i += 2; + pNdpIndex[0] = pAggregatedPacket[i]; //least significant byte + pNdpIndex[1] = pAggregatedPacket[i+1]; //most significant byte + //reading the NDP + while (0x00 != pNdpIndex[0] || 0x00 != pNdpIndex[1]) + { + i = pNdpIndex[0] + 256*pNdpIndex[1]; //NDP should begin here + nNdpStart = i; + + if (0x49 != pAggregatedPacket[i] || 0x50 != pAggregatedPacket[i+1] || + 0x53 != pAggregatedPacket[i+2] || 0x00 != pAggregatedPacket[i+3]) + { + LOG_MSG_DEBUG("Error: Wrong NDP16 signature: 0x%02x 0x%02x " + "0x%02x 0x%02x(should be 0x49, 0x50, 0x53, 0x00)\n", + pAggregatedPacket[i], pAggregatedPacket[i+1], + pAggregatedPacket[i+2], pAggregatedPacket[i+3]); + return false; + } + i += 4; + pNdpLen[0] = pAggregatedPacket[i]; //least significant byte + pNdpLen[1] = pAggregatedPacket[i+1]; //most significant byte + if (0x00 != pAggregatedPacket[nNdpStart + pNdpLen[0] + 256*pNdpLen[1] - 2] || + 0x00 != pAggregatedPacket[nNdpStart + pNdpLen[0] + 256*pNdpLen[1] -1]) + { + LOG_MSG_DEBUG("Error: Wrong end of NDP: 0x%02x 0x%02x(should be " + "0x00, 0x00)\n", + pAggregatedPacket[nNdpStart + pNdpLen[0] + 256*pNdpLen[1] - 2], + pAggregatedPacket[nNdpStart + pNdpLen[0] + 256*pNdpLen[1] - 1]); + return false; + } + i += 2; + pNdpIndex[0] = pAggregatedPacket[i]; //least significant byte + pNdpIndex[1] = pAggregatedPacket[i+1]; //most significant byte + i += 2; + while (i <= nNdpStart + pNdpLen[0] + 256*pNdpLen[1] - 2) + { //going over all the datagrams in this NDP + Byte pDatagramIndex[2] = {0}; + Byte pDatagramLen[2] = {0}; + int packetIndex = 0; + pDatagramIndex[0] = pAggregatedPacket[i]; //least significant byte + pDatagramIndex[1] = pAggregatedPacket[i+1]; //most significant byte + i += 2; + if (0x00 == pDatagramIndex[0] && 0x00 == pDatagramIndex[1]) + break; //zero padding after all datagrams + if (nPacketNum > 1) + { + LOG_MSG_DEBUG("Error: wrong number of packets: %d(should be %d)\n", + nPacketNum, 1); + return false; + } + pDatagramLen[0] = pAggregatedPacket[i]; //least significant byte + pDatagramLen[1] = pAggregatedPacket[i+1]; //most significant byte + i += 2; + packetIndex = pDatagramIndex[0] + 256*pDatagramIndex[1]; + if (pDatagramLen[0] + 256*pDatagramLen[1] != nPacketsSize) + { + LOG_MSG_DEBUG("Error: Wrong packet %d length: 0x%02x 0x%02x" + "(should be %d)\n", nPacketNum, pDatagramLen[0], + pDatagramLen[1], nPacketsSize); + return false; + } + if (0 != memcmp(pExpectedPacket, &pAggregatedPacket[packetIndex], + nPacketsSize)) + { + LOG_MSG_DEBUG("Error: Comparison of packet %d failed!\n", + nPacketNum); + return false; + } + nPacketNum++; + } + } + + return true; +} + +///////////////////////////////////////////////////////////////////////////////// + +bool MBIMAggregationScenarios::DeaggragateAndComparePacketsWithStreamId( + Byte pAggregatedPacket[MAX_PACKET_SIZE], + Byte pExpectedPackets[][MAX_PACKET_SIZE], int pPacketsSizes[], + int nNumPackets, int nAggregatedPacketSize, + Byte pPacketsStreamId[NUM_PACKETS]) +{ + int nPacketNum = 0; + int i = 0; + int nNdpStart = 0; + Byte pNdpIndex[2] = {0}; + Byte pNdpLen[2] = {0}; + if (0x4e != pAggregatedPacket[i] || 0x43 != pAggregatedPacket[i+1] || + 0x4d != pAggregatedPacket[i+2]|| 0x48 != pAggregatedPacket[i+3]) + { + LOG_MSG_DEBUG("Error: Wrong NTH16 signature: 0x%02x 0x%02x 0x%02x " + "0x%02x(should be 0x4e, 0x43, 0x4d, 0x48)\n", + pAggregatedPacket[i], pAggregatedPacket[i+1], + pAggregatedPacket[i+2], pAggregatedPacket[i+3]); + return false; + } + i += 4; + if (0x0c != pAggregatedPacket[i] || 0x00 != pAggregatedPacket[i+1]) + { + LOG_MSG_DEBUG("Error: Wrong header length: 0x%02x 0x%02x(should be " + "0x0c, 0x00)\n",pAggregatedPacket[i], pAggregatedPacket[i+1]); + return false; + } + i += 4; //ignoring sequence number + if ((nAggregatedPacketSize & 0x00FF) != pAggregatedPacket[i] || + (nAggregatedPacketSize >> 8) != pAggregatedPacket[i+1]) + { + LOG_MSG_DEBUG("Error: Wrong aggregated packet length: 0x%02x 0x%02x" + "(should be 0x%02x, 0x%02x)\n", pAggregatedPacket[i], + pAggregatedPacket[i+1], nAggregatedPacketSize & 0x00FF, + nAggregatedPacketSize >> 8); + return false; + } + i += 2; + pNdpIndex[0] = pAggregatedPacket[i]; //least significant byte + pNdpIndex[1] = pAggregatedPacket[i+1]; //most significant byte + //reading the NDP + while (0x00 != pNdpIndex[0] || 0x00 != pNdpIndex[1]) + { + i = pNdpIndex[0] + 256*pNdpIndex[1]; //NDP should begin here + nNdpStart = i; + if (0x49 != pAggregatedPacket[i] || 0x50 != pAggregatedPacket[i+1] || + 0x53 != pAggregatedPacket[i+2]) + { + LOG_MSG_DEBUG("Error: Wrong NDP16 signature: 0x%02x 0x%02x 0x%02x" + "(should be 0x49, 0x50, 0x53)\n", pAggregatedPacket[i], + pAggregatedPacket[i+1], pAggregatedPacket[i+2]); + return false; + } + if (pPacketsStreamId[nPacketNum] != pAggregatedPacket[i+3]) + { + LOG_MSG_DEBUG("Error: Wrong NDP stream id: 0x%02x(should be 0x%02x)\n", + pAggregatedPacket[i+3], pPacketsStreamId[nPacketNum]); + return false; + } + i += 4; + pNdpLen[0] = pAggregatedPacket[i]; //least significant byte + pNdpLen[1] = pAggregatedPacket[i+1]; //most significant byte + if (0x00 != pAggregatedPacket[nNdpStart + pNdpLen[0] + 256*pNdpLen[1] - 2] || + 0x00 != pAggregatedPacket[nNdpStart + pNdpLen[0] + 256*pNdpLen[1] -1]) + { + LOG_MSG_DEBUG("Error: Wrong end of NDP: 0x%02x 0x%02x(should be 0x00, " + "0x00)\n", + pAggregatedPacket[nNdpStart + pNdpLen[0] + 256*pNdpLen[1] - 2], + pAggregatedPacket[nNdpStart + pNdpLen[0] + 256*pNdpLen[1] - 1]); + return false; + } + i += 2; + pNdpIndex[0] = pAggregatedPacket[i]; //least significant byte + pNdpIndex[1] = pAggregatedPacket[i+1]; //most significant byte + i += 2; + while (i <= nNdpStart + pNdpLen[0] + 256*pNdpLen[1] - 2) + { //going over all the datagrams in this NDP + Byte pDatagramIndex[2] = {0}; + Byte pDatagramLen[2] = {0}; + int packetIndex = 0; + pDatagramIndex[0] = pAggregatedPacket[i]; //least significant byte + pDatagramIndex[1] = pAggregatedPacket[i+1]; //most significant byte + i += 2; + if (0x00 == pDatagramIndex[0] && 0x00 == pDatagramIndex[1]) + break; //zero padding after all datagrams + if (nPacketNum >= nNumPackets) + { + LOG_MSG_DEBUG("Error: wrong number of packets: %d(should be %d)\n", + nPacketNum, nNumPackets); + return false; + } + pDatagramLen[0] = pAggregatedPacket[i]; //least significant byte + pDatagramLen[1] = pAggregatedPacket[i+1]; //most significant byte + i += 2; + packetIndex = pDatagramIndex[0] + 256*pDatagramIndex[1]; + if (pDatagramLen[0] + 256*pDatagramLen[1] != (int)pPacketsSizes[nPacketNum]) + { + LOG_MSG_DEBUG("Error: Wrong packet %d length: 0x%02x 0x%02x" + "(should be %d)\n", nPacketNum, pDatagramLen[0], + pDatagramLen[1], pPacketsSizes[nPacketNum]); + return false; + } + if (0 != memcmp(pExpectedPackets[nPacketNum], + &pAggregatedPacket[packetIndex], pPacketsSizes[nPacketNum])) + { + LOG_MSG_DEBUG("Error: Comparison of packet %d failed!\n", + nPacketNum); + return false; + } + nPacketNum++; + } + } + + return true; +} + + +class MBIMAggregationTest: public MBIMAggregationTestFixtureConf11 { +public: + + ///////////////////////////////////////////////////////////////////////////////// + + MBIMAggregationTest(bool generic_agg) : + MBIMAggregationTestFixtureConf11(generic_agg) + { + if (generic_agg) + m_name = "GenMBIMAggregationTest"; + else + m_name = "MBIMAggregationTest"; + m_description = "MBIM Aggregation test - sends 5 packets and receives 1 " + "aggregated packet"; + } + + ///////////////////////////////////////////////////////////////////////////////// + + virtual bool AddRules() + { + return AddRules1HeaderAggregation(); + } // AddRules() + + ///////////////////////////////////////////////////////////////////////////////// + + bool TestLogic() + { + return MBIMAggregationScenarios::MBIMAggregationTest(&m_UsbToIpaPipe, + &m_IpaToUsbPipeAgg, m_eIP); + } + + ///////////////////////////////////////////////////////////////////////////////// +}; + +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// + +class MBIMDeaggregationTest: public MBIMAggregationTestFixtureConf11 { +public: + + ///////////////////////////////////////////////////////////////////////////////// + + MBIMDeaggregationTest(bool generic_agg) : + MBIMAggregationTestFixtureConf11(generic_agg) + { + if (generic_agg) + m_name = "GenMBIMDeaggregationTest"; + else + m_name = "MBIMDeaggregationTest"; + m_description = "MBIM Deaggregation test - sends an aggregated packet made from" + "5 packets and receives 5 packets"; + } + + ///////////////////////////////////////////////////////////////////////////////// + + virtual bool AddRules() + { + return AddRulesDeaggregation(); + } // AddRules() + + ///////////////////////////////////////////////////////////////////////////////// + + bool TestLogic() + { + return MBIMAggregationScenarios::MBIMDeaggregationTest(&m_UsbToIpaPipeDeagg, &m_IpaToUsbPipe, m_eIP); + } + + ///////////////////////////////////////////////////////////////////////////////// +}; + +class MBIMDeaggregationOnePacketTest: public MBIMAggregationTestFixtureConf11 { +public: + + ///////////////////////////////////////////////////////////////////////////////// + + MBIMDeaggregationOnePacketTest(bool generic_agg) : + MBIMAggregationTestFixtureConf11(generic_agg) + { + if (generic_agg) + m_name = "GenMBIMDeaggregationOnePacketTest"; + else + m_name = "MBIMDeaggregationOnePacketTest"; + m_description = "MBIM Deaggregation one packet test - sends an aggregated packet made" + "of 1 packet and receives 1 packet"; + } + + ///////////////////////////////////////////////////////////////////////////////// + + virtual bool AddRules() + { + return AddRulesDeaggregation(); + } // AddRules() + + ///////////////////////////////////////////////////////////////////////////////// + + bool TestLogic() + { + return MBIMAggregationScenarios::MBIMDeaggregationOnePacketTest(&m_UsbToIpaPipeDeagg, &m_IpaToUsbPipe, m_eIP); + } + + ///////////////////////////////////////////////////////////////////////////////// +}; + +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// + + +class MBIMDeaggregationAndAggregationTest: public MBIMAggregationTestFixtureConf11 { +public: + + ///////////////////////////////////////////////////////////////////////////////// + + MBIMDeaggregationAndAggregationTest(bool generic_agg) + : MBIMAggregationTestFixtureConf11(generic_agg) + { + if (generic_agg) + m_name = "GenMBIMDeaggregationAndAggregationTest"; + else + m_name = "MBIMDeaggregationAndAggregationTest"; + m_description = "MBIM Deaggregation and Aggregation test - sends an aggregated " + "packet made from 5 packets and receives the same aggregated packet"; + } + + ///////////////////////////////////////////////////////////////////////////////// + + virtual bool AddRules() + { + return AddRules1HeaderAggregation(); + } // AddRules() + + ///////////////////////////////////////////////////////////////////////////////// + + bool TestLogic() + { + return MBIMAggregationScenarios::MBIMDeaggregationAndAggregationTest( + &m_UsbToIpaPipeDeagg, &m_IpaToUsbPipeAgg, m_eIP); + } + + ///////////////////////////////////////////////////////////////////////////////// + +}; + +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// + + +class MBIMMultipleDeaggregationAndAggregationTest: + public MBIMAggregationTestFixtureConf11 { +public: + + ///////////////////////////////////////////////////////////////////////////////// + + MBIMMultipleDeaggregationAndAggregationTest(bool generic_agg) : + MBIMAggregationTestFixtureConf11(generic_agg) + { + if (generic_agg) + m_name = "GenMBIMMultipleDeaggregationAndAggregationTest"; + else + m_name = "MBIMMultipleDeaggregationAndAggregationTest"; + m_description = "MBIM Multiple Deaggregation and Aggregation test - sends 5 aggregated " + "packets each one made of 1 packet and receives an aggregated packet made of the" + "5 packets"; + } + + ///////////////////////////////////////////////////////////////////////////////// + + virtual bool AddRules() + { + return AddRules1HeaderAggregation(); + } // AddRules() + + ///////////////////////////////////////////////////////////////////////////////// + + bool TestLogic() + { + return MBIMAggregationScenarios::MBIMMultipleDeaggregationAndAggregationTest( + &m_UsbToIpaPipeDeagg, &m_IpaToUsbPipeAgg, m_eIP); + } + + ///////////////////////////////////////////////////////////////////////////////// + +}; + +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// + +class MBIMAggregationLoopTest: public MBIMAggregationTestFixtureConf11 { +public: + + ///////////////////////////////////////////////////////////////////////////////// + + MBIMAggregationLoopTest(bool generic_agg) + : MBIMAggregationTestFixtureConf11(generic_agg) + { + if (generic_agg) + m_name = "GenMBIMggregationLoopTest"; + else + m_name = "MBIMggregationLoopTest"; + m_description = "MBIM Aggregation Loop test - sends 5 packets and expects to" + "receives 1 aggregated packet a few times"; + } + + ///////////////////////////////////////////////////////////////////////////////// + + virtual bool AddRules() + { + return AddRules1HeaderAggregation(); + } // AddRules() + + ///////////////////////////////////////////////////////////////////////////////// + + bool TestLogic() + { + return MBIMAggregationScenarios::MBIMAggregationLoopTest( + &m_UsbToIpaPipe, &m_IpaToUsbPipeAgg, m_eIP); + } + + ///////////////////////////////////////////////////////////////////////////////// +}; + +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// + +class MBIMAggregationTimeLimitTest: public MBIMAggregationTestFixtureConf11 { +public: + + ///////////////////////////////////////////////////////////////////////////////// + + MBIMAggregationTimeLimitTest(bool generic_agg) + : MBIMAggregationTestFixtureConf11(generic_agg) + { + if (generic_agg) + m_name = "GenMBIMAggregationTimeLimitTest"; + else + m_name = "MBIMAggregationTimeLimitTest"; + m_description = "MBIM Aggregation time limit test - sends 1 small packet " + "smaller than the byte limit and receives 1 aggregated packet"; + } + + ///////////////////////////////////////////////////////////////////////////////// + + virtual bool AddRules() + { + return AddRules1HeaderAggregationTime(); + } // AddRules() + + ///////////////////////////////////////////////////////////////////////////////// + + bool TestLogic() + { + return MBIMAggregationScenarios::MBIMAggregationTimeLimitTest( + &m_UsbToIpaPipe, &m_IpaToUsbPipeAggTime, m_eIP); + } + + ///////////////////////////////////////////////////////////////////////////////// +}; + +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// + +class MBIMAggregationByteLimitTest: public MBIMAggregationTestFixtureConf11 { +public: + + ///////////////////////////////////////////////////////////////////////////////// + + MBIMAggregationByteLimitTest(bool generic_agg) + : MBIMAggregationTestFixtureConf11(generic_agg) + { + if (generic_agg) + m_name = "GenMBIMAggregationByteLimitTest"; + else + m_name = "MBIMAggregationByteLimitTest"; + m_description = "MBIM Aggregation byte limit test - sends 2 packets that together " + "are larger than the byte limit "; + } + + ///////////////////////////////////////////////////////////////////////////////// + + virtual bool AddRules() + { + return AddRules1HeaderAggregation(); + } // AddRules() + + ///////////////////////////////////////////////////////////////////////////////// + + bool TestLogic() + { + return MBIMAggregationScenarios::MBIMAggregationByteLimitTest( + &m_UsbToIpaPipe, &m_IpaToUsbPipeAgg, m_eIP); + } + + ///////////////////////////////////////////////////////////////////////////////// +}; + +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// + +class MBIMAggregationByteLimitTestFC: public MBIMAggregationTestFixtureConf11 { +public: + + ///////////////////////////////////////////////////////////////////////////////// + + MBIMAggregationByteLimitTestFC(bool generic_agg) + : MBIMAggregationTestFixtureConf11(generic_agg) { + if (generic_agg) + m_name = "GenMBIMAggregationByteLimitTestFC"; + else + m_name = "MBIMAggregationByteLimitTestFC"; + m_description = "MBIMAggregationByteLimitTestFC - Send 4 IP packet with FC" + "and expect 4 aggregated MBIM packets."; + } + + ///////////////////////////////////////////////////////////////////////////////// + + virtual bool AddRules() { + return AddRules1HeaderAggregation(true); + } // AddRules() + + ///////////////////////////////////////////////////////////////////////////////// + + bool TestLogic() + { + return MBIMAggregationScenarios::MBIMAggregationByteLimitTestFC( + &m_UsbToIpaPipe, &m_IpaToUsbPipeAgg, m_eIP); + } +}; + +class MBIMAggregationDualDpTestFC : public MBIMAggregationTestFixtureConf11 +{ +public: + + ///////////////////////////////////////////////////////////////////////////////// + + MBIMAggregationDualDpTestFC(bool generic_agg) + : MBIMAggregationTestFixtureConf11(generic_agg) + { + if (generic_agg) m_name = "GenMBIMAggregationDualDpTestFC"; + else m_name = "MBIMAggregationDualDpTestFC"; + m_description = "MBIMAggregationDualDpTestFC - Send IP packets " + "on two datapathes: one with FC and one without. " + "Expect 2 aggregated MBIM packets on pipe with FC. " + "Expect one aggregated MBIM packet on pipe without FC. "; + } + + ///////////////////////////////////////////////////////////////////////////////// + + virtual bool AddRules() + { + return AddRulesAggDualFC(&m_UsbToIpaPipe, + &m_IpaToUsbPipeAggTime, + &m_IpaToUsbPipeAgg); + } + + ///////////////////////////////////////////////////////////////////////////////// + + bool TestLogic() + { + return MBIMAggregationScenarios::MBIMAggregationDualDpTestFC( + &m_UsbToIpaPipe, &m_IpaToUsbPipeAggTime, &m_IpaToUsbPipeAgg, m_eIP); + } +}; + +class MBIMAggregationDualDpTestFcRoutingBased : public MBIMAggregationTestFixtureConf11 +{ +public: + + ///////////////////////////////////////////////////////////////////////////////// + + MBIMAggregationDualDpTestFcRoutingBased(bool generic_agg) + : MBIMAggregationTestFixtureConf11(generic_agg) + { + if (generic_agg) m_name = "GenMBIMAggregationDualDpTestFcRoutingBased"; + else m_name = "MBIMAggregationDualDpTestFcRoutingBased"; + m_description = "MBIMAggregationDualDpTestFcRoutingBased - Send IP packets " + "on two datapathes: one with RT based FC and one without. " + "Expect 2 aggregated MBIM packets on pipe with RT based FC. " + "Expect one aggregated MBIM packet on pipe without RT based FC. "; + } + + ///////////////////////////////////////////////////////////////////////////////// + + virtual bool AddRules() + { + return AddRulesAggDualFcRoutingBased(&m_UsbToIpaPipe, + &m_IpaToUsbPipeAggTime, + &m_IpaToUsbPipeAgg); + } + + ///////////////////////////////////////////////////////////////////////////////// + + bool TestLogic() + { + return MBIMAggregationScenarios::MBIMAggregationDualDpTestFC( + &m_UsbToIpaPipe, &m_IpaToUsbPipeAggTime, &m_IpaToUsbPipeAgg, m_eIP); + } +}; + +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// + +class MBIMDeaggregationMultipleNDPTest: public MBIMAggregationTestFixtureConf11 { +public: + + ///////////////////////////////////////////////////////////////////////////////// + + MBIMDeaggregationMultipleNDPTest(bool generic_agg) + : MBIMAggregationTestFixtureConf11(generic_agg) + { + if (generic_agg) + m_name = "GenMBIMDeaggregationMultipleNDPTest"; + else + m_name = "MBIMDeaggregationMultipleNDPTest"; + m_description = "MBIM Deaggregation multiple NDP test - sends an aggregated" + "packet made from 5 packets and 2 NDPs and receives 5 packets"; + } + + ///////////////////////////////////////////////////////////////////////////////// + + virtual bool AddRules() + { + return AddRulesDeaggregation(); + } // AddRules() + + ///////////////////////////////////////////////////////////////////////////////// + + bool TestLogic() + { + return MBIMAggregationScenarios::MBIMDeaggregationMultipleNDPTest( + &m_UsbToIpaPipeDeagg, &m_IpaToUsbPipe, m_eIP); + } + + ///////////////////////////////////////////////////////////////////////////////// +}; + +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// + +class MBIMAggregation2PipesTest: public MBIMAggregationTestFixtureConf11 { +public: + + ///////////////////////////////////////////////////////////////////////////////// + + MBIMAggregation2PipesTest(bool generic_agg) + : MBIMAggregationTestFixtureConf11(generic_agg) + { + if (generic_agg) + m_name = "GenMBIMAggregation2PipesTest"; + else + m_name = "MBIMAggregation2PipesTest"; + m_description = "MBIM Aggregation 2 pipes test - sends 3 packets from one pipe" + "and an aggregated packet made of 2 packets from another pipe and " + "receives 1 aggregated packet made of all 5 packets"; + } + + ///////////////////////////////////////////////////////////////////////////////// + + virtual bool AddRules() + { + return AddRules1HeaderAggregation(); + } // AddRules() + + ///////////////////////////////////////////////////////////////////////////////// + + bool TestLogic() + { + return MBIMAggregationScenarios::MBIMAggregation2PipesTest( + &m_UsbToIpaPipeDeagg, &m_UsbToIpaPipe, &m_IpaToUsbPipeAgg, m_eIP); + } + + ///////////////////////////////////////////////////////////////////////////////// +}; + +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// + +class MBIMAggregationTimeLimitLoopTest: public MBIMAggregationTestFixtureConf11 { +public: + + ///////////////////////////////////////////////////////////////////////////////// + + MBIMAggregationTimeLimitLoopTest(bool generic_agg) + : MBIMAggregationTestFixtureConf11(generic_agg) + { + if (generic_agg) + m_name = "GenMBIMAggregationTimeLimitLoopTest"; + else + m_name = "MBIMAggregationTimeLimitLoopTest"; + m_description = "MBIM Aggregation time limit loop test - sends 5 small packet " + "smaller than the byte limit and receives 5 aggregated packet"; + } + + ///////////////////////////////////////////////////////////////////////////////// + + virtual bool AddRules() + { + return AddRules1HeaderAggregationTime(); + } // AddRules() + + ///////////////////////////////////////////////////////////////////////////////// + + bool TestLogic() + { + return MBIMAggregationScenarios::MBIMAggregationTimeLimitLoopTest( + &m_UsbToIpaPipe, &m_IpaToUsbPipeAggTime, m_eIP); + } + + ///////////////////////////////////////////////////////////////////////////////// +}; + +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// + +class MBIMAggregationMultiplePacketsTest: public MBIMAggregationTestFixtureConf11 { +public: + + ///////////////////////////////////////////////////////////////////////////////// + + MBIMAggregationMultiplePacketsTest(bool generic_agg) + : MBIMAggregationTestFixtureConf11(generic_agg) + { + if (generic_agg) + m_name = "GenMBIMAggregationMultiplePacketsTest"; + else + m_name = "MBIMAggregationMultiplePacketsTest"; + m_description = "MBIM Aggregation multiple packets test - sends 9 packets " + "with same stream ID and receives 1 aggregated packet with 2 NDPs"; + this->m_runInRegression = false; + } + + ///////////////////////////////////////////////////////////////////////////////// + + virtual bool AddRules() + { + return AddRules1HeaderAggregation(); + } // AddRules() + + ///////////////////////////////////////////////////////////////////////////////// + + bool TestLogic() + { + return MBIMAggregationScenarios::MBIMAggregationMultiplePacketsTest( + &m_UsbToIpaPipe, &m_IpaToUsbPipeAgg, m_eIP); + } + + ///////////////////////////////////////////////////////////////////////////////// +}; + +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// + +class MBIMAggregation0LimitsTest: public MBIMAggregationTestFixtureConf11 { +public: + + ///////////////////////////////////////////////////////////////////////////////// + + MBIMAggregation0LimitsTest(bool generic_agg) + : MBIMAggregationTestFixtureConf11(generic_agg) + { + if (generic_agg) + m_name = "GenMBIMAggregation0LimitsTest"; + else + m_name = "MBIMAggregation0LimitsTest"; + m_description = "MBIM Aggregation 0 limits test - sends 5 packets and expects" + "to get each packet back aggregated (both size and time limits are 0)"; + } + + ///////////////////////////////////////////////////////////////////////////////// + + virtual bool AddRules() + { + return AddRules1HeaderAggregation0Limits(); + } // AddRules() + + ///////////////////////////////////////////////////////////////////////////////// + + bool TestLogic() + { + return MBIMAggregationScenarios::MBIMAggregation0LimitsTest( + &m_UsbToIpaPipe, &m_IpaToUsbPipeAgg0Limits, m_eIP); + } + + ///////////////////////////////////////////////////////////////////////////////// +}; + +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// + +class MBIMAggregationDifferentStreamIdsTest: + public MBIMAggregationTestFixtureConf11 { +public: + + ///////////////////////////////////////////////////////////////////////////////// + + MBIMAggregationDifferentStreamIdsTest(bool generic_agg) + : MBIMAggregationTestFixtureConf11(generic_agg) + { + if (generic_agg) + m_name = "GenMBIMAggregationDifferentStreamIdsTest"; + else + m_name = "MBIMAggregationDifferentStreamIdsTest"; + m_description = "MBIM Aggregation different stream IDs test - sends 5 packets" + "with different stream IDs and receives 1 aggregated packet made of 5" + "NDPs"; + } + + ///////////////////////////////////////////////////////////////////////////////// + + virtual bool AddRules() + { + m_eIP = IPA_IP_v4; + const char aBypass[NUM_PACKETS][20] = {{"Bypass1"}, {"Bypass2"}, {"Bypass3"}, + {"Bypass4"}, {"Bypass5"}}; + uint32_t nTableHdl[NUM_PACKETS]; + bool bRetVal = true; + IPAFilteringTable cFilterTable0; + struct ipa_flt_rule_add sFilterRuleEntry; + struct ipa_ioc_get_hdr sGetHeader[NUM_PACKETS]; + uint8_t aHeadertoAdd[NUM_PACKETS][4]; + int hdrSize; + + for (int i = 0; i < NUM_PACKETS; i++) { + if (mGenericAgg) { + hdrSize = 4; + aHeadertoAdd[i][0] = 0x49; + aHeadertoAdd[i][1] = 0x50; + aHeadertoAdd[i][2] = 0x53; + aHeadertoAdd[i][3] = (uint8_t)i; + } else { + hdrSize = 1; + aHeadertoAdd[i][0] = (uint8_t)i; + } + } + + LOG_MSG_STACK("Entering Function"); + memset(&sFilterRuleEntry, 0, sizeof(sFilterRuleEntry)); + for (int i = 0; i < NUM_PACKETS; i++) + memset(&sGetHeader[i], 0, sizeof(sGetHeader[i])); + // Create Header: + // Allocate Memory, populate it, and add in to the Header Insertion. + struct ipa_ioc_add_hdr * pHeaderDescriptor = NULL; + pHeaderDescriptor = (struct ipa_ioc_add_hdr *) calloc(1, + sizeof(struct ipa_ioc_add_hdr) + + NUM_PACKETS * sizeof(struct ipa_hdr_add)); + if (!pHeaderDescriptor) + { + LOG_MSG_ERROR("calloc failed to allocate pHeaderDescriptor"); + bRetVal = false; + goto bail; + } + + pHeaderDescriptor->commit = true; + pHeaderDescriptor->num_hdrs = NUM_PACKETS; + // Adding Header No1. + strlcpy(pHeaderDescriptor->hdr[0].name, "StreamId0", sizeof(pHeaderDescriptor->hdr[0].name)); // Header's Name + memcpy(pHeaderDescriptor->hdr[0].hdr, (void*)&aHeadertoAdd[0], + hdrSize); //Header's Data + pHeaderDescriptor->hdr[0].hdr_len = hdrSize; + pHeaderDescriptor->hdr[0].hdr_hdl = -1; //Return Value + pHeaderDescriptor->hdr[0].is_partial = false; + pHeaderDescriptor->hdr[0].status = -1; // Return Parameter + + // Adding Header No2. + strlcpy(pHeaderDescriptor->hdr[1].name, "StreamId1", sizeof(pHeaderDescriptor->hdr[1].name)); // Header's Name + memcpy(pHeaderDescriptor->hdr[1].hdr, (void*)&aHeadertoAdd[1], + hdrSize); //Header's Data + pHeaderDescriptor->hdr[1].hdr_len = hdrSize; + pHeaderDescriptor->hdr[1].hdr_hdl = -1; //Return Value + pHeaderDescriptor->hdr[1].is_partial = false; + pHeaderDescriptor->hdr[1].status = -1; // Return Parameter + + // Adding Header No3. + strlcpy(pHeaderDescriptor->hdr[2].name, "StreamId2", sizeof(pHeaderDescriptor->hdr[2].name)); // Header's Name + memcpy(pHeaderDescriptor->hdr[2].hdr, (void*)&aHeadertoAdd[2], + hdrSize); //Header's Data + pHeaderDescriptor->hdr[2].hdr_len = hdrSize; + pHeaderDescriptor->hdr[2].hdr_hdl = -1; //Return Value + pHeaderDescriptor->hdr[2].is_partial = false; + pHeaderDescriptor->hdr[2].status = -1; // Return Parameter + + // Adding Header No4. + strlcpy(pHeaderDescriptor->hdr[3].name, "StreamId3", sizeof(pHeaderDescriptor->hdr[3].name)); // Header's Name + memcpy(pHeaderDescriptor->hdr[3].hdr, (void*)&aHeadertoAdd[3], + hdrSize); //Header's Data + pHeaderDescriptor->hdr[3].hdr_len = hdrSize; + pHeaderDescriptor->hdr[3].hdr_hdl = -1; //Return Value + pHeaderDescriptor->hdr[3].is_partial = false; + pHeaderDescriptor->hdr[3].status = -1; // Return Parameter + + // Adding Header No5. + strlcpy(pHeaderDescriptor->hdr[4].name, "StreamId4", sizeof(pHeaderDescriptor->hdr[4].name)); // Header's Name + memcpy(pHeaderDescriptor->hdr[4].hdr, (void*)&aHeadertoAdd[4], + hdrSize); //Header's Data + pHeaderDescriptor->hdr[4].hdr_len = hdrSize; + pHeaderDescriptor->hdr[4].hdr_hdl = -1; //Return Value + pHeaderDescriptor->hdr[4].is_partial = false; + pHeaderDescriptor->hdr[4].status = -1; // Return Parameter + + for (int i = 0; i < NUM_PACKETS; i++) + strlcpy(sGetHeader[i].name, pHeaderDescriptor->hdr[i].name, sizeof(sGetHeader[i].name)); + + + if (!m_HeaderInsertion.AddHeader(pHeaderDescriptor)) + { + LOG_MSG_ERROR("m_HeaderInsertion.AddHeader(pHeaderDescriptor) Failed."); + bRetVal = false; + goto bail; + } + for (int i = 0; i < NUM_PACKETS; i++) + { + if (!m_HeaderInsertion.GetHeaderHandle(&sGetHeader[i])) + { + LOG_MSG_ERROR(" Failed"); + bRetVal = false; + goto bail; + } + LOG_MSG_DEBUG("Received Header %d Handle = 0x%x", i, sGetHeader[i].hdl); + } + + for (int i = 0; i < NUM_PACKETS; i++) + { + if (!CreateBypassRoutingTable(&m_Routing, m_eIP, aBypass[i], + IPA_CLIENT_TEST2_CONS, sGetHeader[i].hdl,&nTableHdl[i])) + { + LOG_MSG_ERROR("CreateBypassRoutingTable Failed\n"); + bRetVal = false; + goto bail; + } + } + + LOG_MSG_INFO("Creation of 5 bypass routing tables completed successfully"); + + // Creating Filtering Rules + cFilterTable0.Init(m_eIP,IPA_CLIENT_TEST_PROD, false, NUM_PACKETS); + LOG_MSG_INFO("Creation of filtering table completed successfully"); + + // Configuring Filtering Rule No.1 + cFilterTable0.GeneratePresetRule(1,sFilterRuleEntry); + sFilterRuleEntry.at_rear = true; + sFilterRuleEntry.flt_rule_hdl=-1; // return Value + sFilterRuleEntry.status = -1; // return value + sFilterRuleEntry.rule.action=IPA_PASS_TO_ROUTING; + sFilterRuleEntry.rule.rt_tbl_hdl=nTableHdl[0]; //put here the handle corresponding to Routing Rule 1 + sFilterRuleEntry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; // Destination IP Based Filtering + sFilterRuleEntry.rule.attrib.u.v4.dst_addr_mask = 0xFF0000FF; // Mask + sFilterRuleEntry.rule.attrib.u.v4.dst_addr = 0x7F000001; // Filter DST_IP == 127.0.0.1. + if ( + ((uint8_t)-1 == cFilterTable0.AddRuleToTable(sFilterRuleEntry)) || + !m_Filtering.AddFilteringRule(cFilterTable0.GetFilteringTable()) + ) + { + LOG_MSG_ERROR ("Adding Rule (0) to Filtering block Failed."); + bRetVal = false; + goto bail; + } + else + { + LOG_MSG_DEBUG("flt rule hdl0=0x%x, status=0x%x\n", + cFilterTable0.ReadRuleFromTable(0)->flt_rule_hdl, + cFilterTable0.ReadRuleFromTable(0)->status); + } + + // Configuring Filtering Rule No.2 + sFilterRuleEntry.flt_rule_hdl=-1; // return Value + sFilterRuleEntry.status = -1; // return Value + sFilterRuleEntry.rule.rt_tbl_hdl=nTableHdl[1]; //put here the handle corresponding to Routing Rule 2 + sFilterRuleEntry.rule.attrib.u.v4.dst_addr = 0xC0A80101; // Filter DST_IP == 192.168.1.1. + if ( + ((uint8_t)-1 == cFilterTable0.AddRuleToTable(sFilterRuleEntry)) || + !m_Filtering.AddFilteringRule(cFilterTable0.GetFilteringTable()) + ) + { + LOG_MSG_ERROR ("Adding Rule(1) to Filtering block Failed."); + bRetVal = false; + goto bail; + } + else + { + LOG_MSG_DEBUG("flt rule hdl0=0x%x, status=0x%x\n", + cFilterTable0.ReadRuleFromTable(1)->flt_rule_hdl, + cFilterTable0.ReadRuleFromTable(1)->status); + } + + // Configuring Filtering Rule No.3 + sFilterRuleEntry.flt_rule_hdl=-1; // return Value + sFilterRuleEntry.status = -1; // return value + sFilterRuleEntry.rule.rt_tbl_hdl=nTableHdl[2]; //put here the handle corresponding to Routing Rule 2 + sFilterRuleEntry.rule.attrib.u.v4.dst_addr = 0xC0A80102; // Filter DST_IP == 192.168.1.2. + + if ( + ((uint8_t)-1 == cFilterTable0.AddRuleToTable(sFilterRuleEntry)) || + !m_Filtering.AddFilteringRule(cFilterTable0.GetFilteringTable()) + ) + { + LOG_MSG_ERROR ("Adding Rule(2) to Filtering block Failed."); + bRetVal = false; + goto bail; + } + else + { + LOG_MSG_DEBUG("flt rule hdl0=0x%x, status=0x%x\n", + cFilterTable0.ReadRuleFromTable(2)->flt_rule_hdl, + cFilterTable0.ReadRuleFromTable(2)->status); + } + + // Configuring Filtering Rule No.4 + sFilterRuleEntry.flt_rule_hdl=-1; // return Value + sFilterRuleEntry.status = -1; // return value + sFilterRuleEntry.rule.rt_tbl_hdl=nTableHdl[3]; //put here the handle corresponding to Routing Rule 2 + sFilterRuleEntry.rule.attrib.u.v4.dst_addr = 0xC0A80103; // Filter DST_IP == 192.168.1.3. + + if ( + ((uint8_t)-1 == cFilterTable0.AddRuleToTable(sFilterRuleEntry)) || + !m_Filtering.AddFilteringRule(cFilterTable0.GetFilteringTable()) + ) + { + LOG_MSG_ERROR ("Adding Rule(3) to Filtering block Failed."); + bRetVal = false; + goto bail; + } + else + { + LOG_MSG_DEBUG("flt rule hdl0=0x%x, status=0x%x\n", + cFilterTable0.ReadRuleFromTable(2)->flt_rule_hdl, + cFilterTable0.ReadRuleFromTable(2)->status); + } + + // Configuring Filtering Rule No.5 + sFilterRuleEntry.flt_rule_hdl=-1; // return Value + sFilterRuleEntry.status = -1; // return value + sFilterRuleEntry.rule.rt_tbl_hdl=nTableHdl[4]; //put here the handle corresponding to Routing Rule 2 + sFilterRuleEntry.rule.attrib.u.v4.dst_addr = 0xC0A80104; // Filter DST_IP == 192.168.1.4. + + if ( + ((uint8_t)-1 == cFilterTable0.AddRuleToTable(sFilterRuleEntry)) || + !m_Filtering.AddFilteringRule(cFilterTable0.GetFilteringTable()) + ) + { + LOG_MSG_ERROR ("Adding Rule(4) to Filtering block Failed."); + bRetVal = false; + goto bail; + } + else + { + LOG_MSG_DEBUG("flt rule hdl0=0x%x, status=0x%x\n", + cFilterTable0.ReadRuleFromTable(2)->flt_rule_hdl, + cFilterTable0.ReadRuleFromTable(2)->status); + } + + bail: + Free(pHeaderDescriptor); + LOG_MSG_STACK( + "Leaving Function (Returning %s)", bRetVal?"True":"False"); + return bRetVal; + } // AddRules() + + ///////////////////////////////////////////////////////////////////////////////// + + bool TestLogic() + { + return MBIMAggregationScenarios::MBIMAggregationDifferentStreamIdsTest( + &m_UsbToIpaPipe, &m_IpaToUsbPipeAgg, m_eIP); + } + + ///////////////////////////////////////////////////////////////////////////////// +}; + +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// + +class MBIMAggregationNoInterleavingStreamIdsTest: + public MBIMAggregationTestFixtureConf11 { +public: + + ///////////////////////////////////////////////////////////////////////////////// + + MBIMAggregationNoInterleavingStreamIdsTest(bool generic_agg) + : MBIMAggregationTestFixtureConf11(generic_agg) + { + if (generic_agg) + m_name = "GenMBIMAggregationNoInterleavingStreamIdsTest"; + else + m_name = "MBIMAggregationNoInterleavingStreamIdsTest"; + m_description = "MBIM Aggregation no interleaving stream IDs test - sends 5 packets" + "with interleaving stream IDs (0, 1, 0, 1, 0) and receives 1 aggregated " + "packet made of 5 NDPs"; + } + + ///////////////////////////////////////////////////////////////////////////////// + + virtual bool AddRules() + { + m_eIP = IPA_IP_v4; + const char aBypass[2][20] = {{"Bypass1"}, {"Bypass2"}}; + uint32_t nTableHdl[2]; + bool bRetVal = true; + IPAFilteringTable cFilterTable0; + struct ipa_flt_rule_add sFilterRuleEntry; + struct ipa_ioc_get_hdr sGetHeader[2]; + uint8_t aHeadertoAdd[2][4]; + int hdrSize; + + for (int i = 0; i < 2; i++) { + if (mGenericAgg) { + hdrSize = 4; + aHeadertoAdd[i][0] = 0x49; + aHeadertoAdd[i][1] = 0x50; + aHeadertoAdd[i][2] = 0x53; + aHeadertoAdd[i][3] = (uint8_t)i; + } + else { + hdrSize = 1; + aHeadertoAdd[i][0] = (uint8_t)i; + } + } + + LOG_MSG_STACK("Entering Function"); + memset(&sFilterRuleEntry, 0, sizeof(sFilterRuleEntry)); + for (int i = 0; i < 2; i++) + memset(&sGetHeader[i], 0, sizeof(sGetHeader[i])); + // Create Header: + // Allocate Memory, populate it, and add in to the Header Insertion. + struct ipa_ioc_add_hdr * pHeaderDescriptor = NULL; + pHeaderDescriptor = (struct ipa_ioc_add_hdr *) calloc(1, + sizeof(struct ipa_ioc_add_hdr) + + 2 * sizeof(struct ipa_hdr_add)); + if (!pHeaderDescriptor) + { + LOG_MSG_ERROR("calloc failed to allocate pHeaderDescriptor"); + bRetVal = false; + goto bail; + } + + pHeaderDescriptor->commit = true; + pHeaderDescriptor->num_hdrs = 2; + // Adding Header No1. + strlcpy(pHeaderDescriptor->hdr[0].name, "StreamId0", sizeof(pHeaderDescriptor->hdr[0].name)); // Header's Name + memcpy(pHeaderDescriptor->hdr[0].hdr, (void*)&aHeadertoAdd[0], + hdrSize); //Header's Data + pHeaderDescriptor->hdr[0].hdr_len = hdrSize; + pHeaderDescriptor->hdr[0].hdr_hdl = -1; //Return Value + pHeaderDescriptor->hdr[0].is_partial = false; + pHeaderDescriptor->hdr[0].status = -1; // Return Parameter + + // Adding Header No2. + strlcpy(pHeaderDescriptor->hdr[1].name, "StreamId1", sizeof(pHeaderDescriptor->hdr[1].name)); // Header's Name + memcpy(pHeaderDescriptor->hdr[1].hdr, (void*)&aHeadertoAdd[1], + hdrSize); //Header's Data + pHeaderDescriptor->hdr[1].hdr_len = hdrSize; + pHeaderDescriptor->hdr[1].hdr_hdl = -1; //Return Value + pHeaderDescriptor->hdr[1].is_partial = false; + pHeaderDescriptor->hdr[1].status = -1; // Return Parameter + + for (int i = 0; i < 2; i++) + strlcpy(sGetHeader[i].name, pHeaderDescriptor->hdr[i].name, sizeof(sGetHeader[i].name)); + + + if (!m_HeaderInsertion.AddHeader(pHeaderDescriptor)) + { + LOG_MSG_ERROR("m_HeaderInsertion.AddHeader(pHeaderDescriptor) Failed."); + bRetVal = false; + goto bail; + } + for (int i = 0; i < 2; i++) + { + if (!m_HeaderInsertion.GetHeaderHandle(&sGetHeader[i])) + { + LOG_MSG_ERROR(" Failed"); + bRetVal = false; + goto bail; + } + LOG_MSG_DEBUG("Received Header %d Handle = 0x%x", i, sGetHeader[i].hdl); + } + + for (int i = 0; i < 2; i++) + { + if (!CreateBypassRoutingTable(&m_Routing, m_eIP, aBypass[i], + IPA_CLIENT_TEST2_CONS, sGetHeader[i].hdl,&nTableHdl[i])) + { + LOG_MSG_ERROR("CreateBypassRoutingTable Failed\n"); + bRetVal = false; + goto bail; + } + } + + LOG_MSG_INFO("Creation of 2 bypass routing tables completed successfully"); + + // Creating Filtering Rules + cFilterTable0.Init(m_eIP,IPA_CLIENT_TEST_PROD, false, 2); + LOG_MSG_INFO("Creation of filtering table completed successfully"); + + // Configuring Filtering Rule No.1 + cFilterTable0.GeneratePresetRule(1,sFilterRuleEntry); + sFilterRuleEntry.at_rear = true; + sFilterRuleEntry.flt_rule_hdl=-1; // return Value + sFilterRuleEntry.status = -1; // return value + sFilterRuleEntry.rule.action=IPA_PASS_TO_ROUTING; + sFilterRuleEntry.rule.rt_tbl_hdl=nTableHdl[0]; //put here the handle corresponding to Routing Rule 1 + sFilterRuleEntry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; // Destination IP Based Filtering + sFilterRuleEntry.rule.attrib.u.v4.dst_addr_mask = 0xFF0000FF; // Mask + sFilterRuleEntry.rule.attrib.u.v4.dst_addr = 0x7F000001; // Filter DST_IP == 127.0.0.1. + if ( + ((uint8_t)-1 == cFilterTable0.AddRuleToTable(sFilterRuleEntry)) || + !m_Filtering.AddFilteringRule(cFilterTable0.GetFilteringTable()) + ) + { + LOG_MSG_ERROR ("Adding Rule (0) to Filtering block Failed."); + bRetVal = false; + goto bail; + } + else + { + LOG_MSG_DEBUG("flt rule hdl0=0x%x, status=0x%x\n", + cFilterTable0.ReadRuleFromTable(0)->flt_rule_hdl, + cFilterTable0.ReadRuleFromTable(0)->status); + } + + // Configuring Filtering Rule No.2 + sFilterRuleEntry.flt_rule_hdl=-1; // return Value + sFilterRuleEntry.status = -1; // return Value + sFilterRuleEntry.rule.rt_tbl_hdl=nTableHdl[1]; //put here the handle corresponding to Routing Rule 2 + sFilterRuleEntry.rule.attrib.u.v4.dst_addr = 0xC0A80101; // Filter DST_IP == 192.168.1.1. + if ( + ((uint8_t)-1 == cFilterTable0.AddRuleToTable(sFilterRuleEntry)) || + !m_Filtering.AddFilteringRule(cFilterTable0.GetFilteringTable()) + ) + { + LOG_MSG_ERROR ("Adding Rule(1) to Filtering block Failed."); + bRetVal = false; + goto bail; + } + else + { + LOG_MSG_DEBUG("flt rule hdl0=0x%x, status=0x%x\n", + cFilterTable0.ReadRuleFromTable(1)->flt_rule_hdl, + cFilterTable0.ReadRuleFromTable(1)->status); + } + + bail: + Free(pHeaderDescriptor); + LOG_MSG_STACK( + "Leaving Function (Returning %s)", bRetVal?"True":"False"); + return bRetVal; + } // AddRules() + + ///////////////////////////////////////////////////////////////////////////////// + + bool TestLogic() + { + return MBIMAggregationScenarios::MBIMAggregationNoInterleavingStreamIdsTest( + &m_UsbToIpaPipe, &m_IpaToUsbPipeAgg, m_eIP); + } + + ///////////////////////////////////////////////////////////////////////////////// +}; + +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// +/* Legacy MBIM tests */ + +static MBIMAggregationTest mbimAggregationTest(false); +static MBIMDeaggregationTest mbimDeaggregationTest(false); +static MBIMDeaggregationOnePacketTest mbimDeaggregationOnePacketTest(false); +static MBIMDeaggregationAndAggregationTest mbimDeaggregationAndAggregationTest(false); +static MBIMMultipleDeaggregationAndAggregationTest + mbimMultipleDeaggregationAndAggregationTest(false); +static MBIMAggregationLoopTest mbimAggregationLoopTest(false); +static MBIMDeaggregationMultipleNDPTest mbimDeaggregationMultipleNDPTest(false); +static MBIMAggregationMultiplePacketsTest mbimAggregationMultiplePacketsTest(false); +static MBIMAggregation2PipesTest mbimAggregation2PipesTest(false); +static MBIMAggregationNoInterleavingStreamIdsTest + mbimAggregationNoInterleavingStreamIdsTest(false); +static MBIMAggregationDifferentStreamIdsTest mbimAggregationDifferentStreamIdsTest(false); +static MBIMAggregationTimeLimitTest mbimAggregationTimeLimitTest(false); +static MBIMAggregationByteLimitTest mbimAggregationByteLimitTest(false); +static MBIMAggregationTimeLimitLoopTest mbimAggregationTimeLimitLoopTest(false); +static MBIMAggregation0LimitsTest mbimAggregation0LimitsTest(false); + +/* Generic Aggregation MBIM tests */ + +static MBIMAggregationTest genMbimAggregationTest(true); +static MBIMDeaggregationTest genMbimDeaggregationTest(true); +static MBIMDeaggregationOnePacketTest genMbimDeaggregationOnePacketTest(true); +static MBIMDeaggregationAndAggregationTest genMbimDeaggregationAndAggregationTest(true); +static MBIMMultipleDeaggregationAndAggregationTest genMbimMultipleDeaggregationAndAggregationTest(true); +static MBIMAggregationLoopTest genMbimAggregationLoopTest(true); +static MBIMDeaggregationMultipleNDPTest genMbimDeaggregationMultipleNDPTest(true); +static MBIMAggregationMultiplePacketsTest genMbimAggregationMultiplePacketsTest(true); +static MBIMAggregation2PipesTest genMbimAggregation2PipesTest(true); +static MBIMAggregationNoInterleavingStreamIdsTest genMbimAggregationNoInterleavingStreamIdsTest(true); +static MBIMAggregationDifferentStreamIdsTest genMbimAggregationDifferentStreamIdsTest(true); +static MBIMAggregationTimeLimitTest genMbimAggregationTimeLimitTest(true); +static MBIMAggregationByteLimitTest genMbimAggregationByteLimitTest(true); +static MBIMAggregationByteLimitTestFC genMbimAggregationByteLimitTestFC(true); +static MBIMAggregationDualDpTestFC genMBIMAggregationDualDpTestFC(true); +static MBIMAggregationDualDpTestFcRoutingBased genMBIMAggregationDualDpTestFcRoutingBased(true); +static MBIMAggregationTimeLimitLoopTest genMbimAggregationTimeLimitLoopTest(true); +static MBIMAggregation0LimitsTest genMbimAggregation0LimitsTest(true); + +///////////////////////////////////////////////////////////////////////////////// +// EOF //// +///////////////////////////////////////////////////////////////////////////////// diff --git a/qcom/opensource/dataipa/kernel-tests/Makefile.am b/qcom/opensource/dataipa/kernel-tests/Makefile.am new file mode 100644 index 0000000000..4903729e44 --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/Makefile.am @@ -0,0 +1,53 @@ +ACLOCAL_AMFLAGS = -Im4 +EXTRA_CFLAGS = -DDEBUG +AM_CXXFLAGS = -Wall -Wundef -Wno-trigraphs -Werror -std=c++14 + +if USE_GLIB + ipa_kernel_tests_CPPFLAGS = $(AM_CFLAGS) -DUSE_GLIB -Dstrlcpy=g_strlcpy @GLIB_CFLAGS@ + ipa_kernel_tests_LDFLAGS = -lpthread @GLIB_LIBS@ +endif + +requiredlibs = -lipanat +ipa_kernel_tests_LDADD = $(requiredlibs) + +ipa_kernel_testsdir = $(prefix) +ipa_kernel_tests_PROGRAMS = ipa_kernel_tests +dist_ipa_kernel_tests_SCRIPTS = run.sh +ipa_kernel_tests_SOURCES =\ + TestManager.cpp \ + TestBase.cpp \ + InterfaceAbstraction.cpp \ + Pipe.cpp \ + PipeTestFixture.cpp \ + PipeTests.cpp \ + TLPAggregationTestFixture.cpp \ + TLPAggregationTests.cpp \ + MBIMAggregationTestFixtureConf11.cpp \ + MBIMAggregationTests.cpp \ + Logger.cpp \ + RoutingDriverWrapper.cpp \ + RoutingTests.cpp \ + IPAFilteringTable.cpp \ + Filtering.cpp \ + FilteringTest.cpp \ + HeaderInsertion.cpp \ + HeaderInsertionTests.cpp \ + TestsUtils.cpp \ + HeaderRemovalTestFixture.cpp \ + HeaderRemovalTests.cpp \ + IPv4Packet.cpp \ + RNDISAggregationTestFixture.cpp \ + RNDISAggregationTests.cpp \ + DataPathTestFixture.cpp \ + DataPathTests.cpp \ + IPAInterruptsTestFixture.cpp \ + IPAInterruptsTests.cpp \ + HeaderProcessingContextTestFixture.cpp \ + HeaderProcessingContextTests.cpp \ + FilteringEthernetBridgingTestFixture.cpp \ + FilteringEthernetBridgingTests.cpp \ + NatTest.cpp \ + IPv6CTTest.cpp \ + UlsoTest.cpp \ + Feature.cpp \ + main.cpp diff --git a/qcom/opensource/dataipa/kernel-tests/NOTICE b/qcom/opensource/dataipa/kernel-tests/NOTICE new file mode 100644 index 0000000000..6b493a6ba7 --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/NOTICE @@ -0,0 +1,26 @@ +Copyright (c) 2021 The Linux Foundation. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are +met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above + copyright notice, this list of conditions and the following + disclaimer in the documentation and/or other materials provided + with the distribution. + * Neither the name of The Linux Foundation nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED +WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT +ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS +BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \ No newline at end of file diff --git a/qcom/opensource/dataipa/kernel-tests/NatTest.cpp b/qcom/opensource/dataipa/kernel-tests/NatTest.cpp new file mode 100644 index 0000000000..b863dcadaa --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/NatTest.cpp @@ -0,0 +1,5154 @@ +/* + * Copyright (c) 2017-2020 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include // for memcpy +#include "hton.h" // for htonl +#include "InterfaceAbstraction.h" +#include "Constants.h" +#include "Logger.h" +#include "TestsUtils.h" +#include "Filtering.h" +#include "RoutingDriverWrapper.h" +#include "IPAFilteringTable.h" +extern "C" { +#include "ipa_nat_drv.h" +} + +//IP offsets +#define IPV4_PROTOCOL_OFFSET (9) +#define IPV4_IP_CHECKSUM_OFFSET (10) +#define IPV4_SRC_ADDR_OFFSET (12) +#define IPV4_DST_ADDR_OFFSET (16) + +//TCP offsets +#define IPV4_SRC_PORT_OFFSET (20) +#define IPV4_DST_PORT_OFFSET (20+2) +#define IPV4_TCP_FLAGS_OFFSET (33) +#define IPV4_TCP_CHECKSUM_OFFSET (36) + +#define IPA_16BIT_ROUND_UP(val) \ + do { \ + if (val >> 16) { \ + val = (val & 0x0000FFFF);\ + val += 1;\ + } \ + } while(0) + +extern Logger g_Logger; + +class IpaNatBlockTestFixture : public TestBase +{ +public: + + IpaNatBlockTestFixture() : + m_sendSize(BUFF_MAX_SIZE), + m_sendSize2(BUFF_MAX_SIZE), + m_sendSize3(BUFF_MAX_SIZE), + m_IpaIPType(IPA_IP_v4), + m_extHdrType(NONE) + { + memset(m_sendBuffer, 0, sizeof(m_sendBuffer)); // First input file / IP packet + memset(m_sendBuffer2, 0, sizeof(m_sendBuffer2)); // Second input file / IP packet + memset(m_sendBuffer3, 0, sizeof(m_sendBuffer3)); // Third input file (default) / IP packet + m_testSuiteName.push_back("Nat"); + } + + static int SetupKernelModule(bool en_status = 0, bool nat_suppress = 0) + { + int retval; + struct ipa_channel_config from_ipa_channels[3]; + struct test_ipa_ep_cfg from_ipa_cfg[3]; + struct ipa_channel_config to_ipa_channels[2]; + struct test_ipa_ep_cfg to_ipa_cfg[2]; + + struct ipa_test_config_header header = { 0 }; + struct ipa_channel_config *to_ipa_array[2]; + struct ipa_channel_config *from_ipa_array[3]; + + /* From ipa configurations - 3 pipes */ + memset(&from_ipa_cfg[0], 0, sizeof(from_ipa_cfg[0])); + prepare_channel_struct(&from_ipa_channels[0], + header.from_ipa_channels_num++, + IPA_CLIENT_TEST2_CONS, + (void *)&from_ipa_cfg[0], + sizeof(from_ipa_cfg[0]), + en_status); + from_ipa_array[0] = &from_ipa_channels[0]; + + memset(&from_ipa_cfg[1], 0, sizeof(from_ipa_cfg[1])); + prepare_channel_struct(&from_ipa_channels[1], + header.from_ipa_channels_num++, + IPA_CLIENT_TEST3_CONS, + (void *)&from_ipa_cfg[1], + sizeof(from_ipa_cfg[1]), + en_status); + from_ipa_array[1] = &from_ipa_channels[1]; + + memset(&from_ipa_cfg[2], 0, sizeof(from_ipa_cfg[2])); + prepare_channel_struct(&from_ipa_channels[2], + header.from_ipa_channels_num++, + IPA_CLIENT_TEST4_CONS, + (void *)&from_ipa_cfg[2], + sizeof(from_ipa_cfg[2]), + en_status); + from_ipa_array[2] = &from_ipa_channels[2]; + + /* To ipa configurations - 2 pipes */ + memset(&to_ipa_cfg[0], 0, sizeof(to_ipa_cfg[0])); + to_ipa_cfg[0].nat.nat_exc_suppress = nat_suppress; + prepare_channel_struct(&to_ipa_channels[0], + header.to_ipa_channels_num++, + IPA_CLIENT_TEST_PROD, + (void *)&to_ipa_cfg[0], + sizeof(to_ipa_cfg[0])); + to_ipa_array[0] = &to_ipa_channels[0]; + + /* header removal for Ethernet header + 8021Q header */ + memset(&to_ipa_cfg[1], 0, sizeof(to_ipa_cfg[1])); + to_ipa_cfg[1].nat.nat_exc_suppress = nat_suppress; + to_ipa_cfg[1].hdr.hdr_len = ETH8021Q_HEADER_LEN; + to_ipa_cfg[1].hdr.hdr_ofst_metadata_valid = 1; + to_ipa_cfg[1].hdr.hdr_ofst_metadata = + ETH8021Q_METADATA_OFFSET; + prepare_channel_struct(&to_ipa_channels[1], + header.to_ipa_channels_num++, + IPA_CLIENT_TEST2_PROD, + (void *)&to_ipa_cfg[1], + sizeof(to_ipa_cfg[1])); + to_ipa_array[1] = &to_ipa_channels[1]; + + prepare_header_struct(&header, from_ipa_array, to_ipa_array); + + retval = GenericConfigureScenario(&header); + + return retval; + } + + + bool Setup() + { + bool bRetVal = true; + + if (SetupKernelModule() != true) + return bRetVal; + + m_producer.Open(INTERFACE0_TO_IPA_DATA_PATH, INTERFACE0_FROM_IPA_DATA_PATH); + m_producer2.Open(INTERFACE4_TO_IPA_DATA_PATH, INTERFACE4_FROM_IPA_DATA_PATH); + + m_consumer.Open(INTERFACE1_TO_IPA_DATA_PATH, INTERFACE1_FROM_IPA_DATA_PATH); + m_consumer2.Open(INTERFACE2_TO_IPA_DATA_PATH, INTERFACE2_FROM_IPA_DATA_PATH); + m_defaultConsumer.Open(INTERFACE3_TO_IPA_DATA_PATH, INTERFACE3_FROM_IPA_DATA_PATH); + + if (!m_routing.DeviceNodeIsOpened()) + { + LOG_MSG_ERROR("Routing block is not ready for immediate commands!\n"); + return false; + } + + if (!m_filtering.DeviceNodeIsOpened()) + { + LOG_MSG_ERROR("Filtering block is not ready for immediate commands!\n"); + return false; + } + m_routing.Reset(IPA_IP_v4); // This will issue a Reset command to the Filtering as well + m_routing.Reset(IPA_IP_v6); // This will issue a Reset command to the Filtering as well + return true; + } // Setup() + + bool Setup(bool en_status = false, bool nat_suppress = false) + { + bool bRetVal = true; + + if (SetupKernelModule(en_status, nat_suppress) != true) + return bRetVal; + + m_producer.Open(INTERFACE0_TO_IPA_DATA_PATH, INTERFACE0_FROM_IPA_DATA_PATH); + + m_consumer.Open(INTERFACE1_TO_IPA_DATA_PATH, INTERFACE1_FROM_IPA_DATA_PATH); + m_consumer2.Open(INTERFACE2_TO_IPA_DATA_PATH, INTERFACE2_FROM_IPA_DATA_PATH); + m_defaultConsumer.Open(INTERFACE3_TO_IPA_DATA_PATH, INTERFACE3_FROM_IPA_DATA_PATH); + + if (!m_routing.DeviceNodeIsOpened()) + { + LOG_MSG_ERROR("Routing block is not ready for immediate commands!\n"); + return false; + } + + if (!m_filtering.DeviceNodeIsOpened()) + { + LOG_MSG_ERROR("Filtering block is not ready for immediate commands!\n"); + return false; + } + m_routing.Reset(IPA_IP_v4); // This will issue a Reset command to the Filtering as well + m_routing.Reset(IPA_IP_v6); // This will issue a Reset command to the Filtering as well + return true; + } // Setup() + + + bool Teardown() + { + ipa_nat_dump_ipv4_table(m_tbl_hdl); + ipa_nat_del_ipv4_tbl(m_tbl_hdl); + + m_producer.Close(); + m_producer2.Close(); + m_consumer.Close(); + m_consumer2.Close(); + m_defaultConsumer.Close(); + return true; + } // Teardown() + + virtual bool LoadFiles(enum ipa_ip_type ip) + { + string fileName; + + if (IPA_IP_v4 == ip) { + fileName = "Input/IPv4_1"; + } + else { + fileName = "Input/IPv6"; + } + + if (!LoadDefaultPacket(ip, m_extHdrType, m_sendBuffer, m_sendSize)) { + LOG_MSG_ERROR("Failed default Packet\n"); + return false; + } + LOG_MSG_DEBUG("Loaded %zu Bytes to Buffer 1\n", m_sendSize); + + if (!LoadDefaultPacket(ip, m_extHdrType, m_sendBuffer2, m_sendSize2)) { + LOG_MSG_ERROR("Failed default Packet\n"); + return false; + } + LOG_MSG_DEBUG("Loaded %zu Bytes to Buffer 2\n", m_sendSize2); + + if (!LoadDefaultPacket(ip, m_extHdrType, m_sendBuffer3, m_sendSize3)) { + LOG_MSG_ERROR("Failed default Packet\n"); + return false; + } + LOG_MSG_DEBUG("Loaded %zu Bytes to Buffer 3\n", m_sendSize3); + + return true; + } + + inline bool VerifyStatusReceived(size_t SendSize, size_t RecvSize) + { + size_t stts_size = sizeof(struct ipa3_hw_pkt_status); + + if (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_0) { + stts_size = sizeof(struct ipa3_hw_pkt_status_hw_v5_0); + } + + if ((RecvSize <= SendSize) || + ((RecvSize - SendSize) != stts_size)) { + LOG_MSG_ERROR("received buffer size does not match! sent:receive [%zu]:[%zu]\n", SendSize, RecvSize); + return false; + } + + return true; + } + + inline bool IsCacheHit(size_t SendSize, size_t RecvSize, void *Buff) + { + struct ipa3_hw_pkt_status *pStatus = (struct ipa3_hw_pkt_status *)Buff; + + if (VerifyStatusReceived(SendSize, RecvSize) == false) { + return false; + } + + if ((bool)pStatus->route_hash) { + LOG_MSG_DEBUG("cache hit!! \n"); + return true; + } + + LOG_MSG_ERROR("cache miss!! \n"); + return false; + + } + + inline bool IsCacheHit_v5_0(size_t SendSize, size_t RecvSize, void *Buff) + { + struct ipa3_hw_pkt_status_hw_v5_0 *pStatus = (struct ipa3_hw_pkt_status_hw_v5_0 *)Buff; + + if (VerifyStatusReceived(SendSize, RecvSize) == false) { + return false; + } + + if ((bool)pStatus->route_hash) { + LOG_MSG_DEBUG("cache hit!! \n"); + return true; + } + + LOG_MSG_ERROR("cache miss!! \n"); + return false; + + } + + inline bool IsCacheMiss(size_t SendSize, size_t RecvSize, void *Buff) + { + struct ipa3_hw_pkt_status *pStatus = (struct ipa3_hw_pkt_status *)Buff; + + if (VerifyStatusReceived(SendSize, RecvSize) == false) { + return false; + } + + if (!((bool)pStatus->route_hash)) { + LOG_MSG_DEBUG("cache miss!! \n"); + return true; + } + + LOG_MSG_ERROR("cache hit!! \n"); + return false; + } + + inline bool IsCacheMiss_v5_0(size_t SendSize, size_t RecvSize, void *Buff) + { + struct ipa3_hw_pkt_status_hw_v5_0 *pStatus = (struct ipa3_hw_pkt_status_hw_v5_0 *)Buff; + + if (VerifyStatusReceived(SendSize, RecvSize) == false) { + return false; + } + + if (!((bool)pStatus->route_hash)) { + LOG_MSG_DEBUG("cache miss!! \n"); + return true; + } + + LOG_MSG_ERROR("cache hit!! \n"); + return false; + } + + bool CompareResultVsGoldenNat(Byte *goldenBuffer, unsigned int goldenSize, + Byte *receivedBuffer, unsigned int receivedSize, int private_ip, int public_ip, + int private_port, int public_port, bool src_nat, int IPv4_offset = 0, bool with_status = false) + { + bool result; + uint32_t address; + uint16_t port; + uint32_t val; + uint16_t ip_checksum_diff, tcp_checksum_diff; + uint32_t ip_checksum, tcp_checksum; + int recv_offset = 0; + size_t stts_size = sizeof(struct ipa3_hw_pkt_status); + + if (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_0) { + stts_size = sizeof(struct ipa3_hw_pkt_status_hw_v5_0); + } + + if (with_status) + recv_offset += stts_size; + + ip_checksum_diff = calc_ip_cksum_diff(public_ip, private_ip); + tcp_checksum_diff = calc_tcp_udp_cksum_diff(public_ip, public_port, private_ip, private_port); + + //calculate new ip checksum, old checksum + 1's compliment of checksum diff + ip_checksum = *((uint16_t *)&goldenBuffer[IPV4_IP_CHECKSUM_OFFSET + IPv4_offset]); + ip_checksum = ntohs(ip_checksum); + + if(src_nat) + ip_checksum += (uint16_t)(~ip_checksum_diff); + else + ip_checksum += (uint16_t)ip_checksum_diff; + + IPA_16BIT_ROUND_UP(ip_checksum); + + //return to network format + ip_checksum = htons(ip_checksum); + + //calculate new tcp checksum, old checksum + 1's compliment of checksum diff + tcp_checksum = *((uint16_t *)&goldenBuffer[IPV4_TCP_CHECKSUM_OFFSET + IPv4_offset]); + tcp_checksum = ntohs(tcp_checksum); + + if(src_nat) + tcp_checksum += (uint16_t)(~tcp_checksum_diff); + else + tcp_checksum += (uint16_t)tcp_checksum_diff; + + IPA_16BIT_ROUND_UP(tcp_checksum); + + //return to network format + tcp_checksum = htons(tcp_checksum); + + if ((receivedSize - recv_offset) != goldenSize) { + g_Logger.AddMessage(LOG_VERBOSE, "%s Buffers sizes are different.\n", __FUNCTION__); + return false; + } + + Byte *tmp_buff = new Byte[goldenSize]; + + memcpy(tmp_buff, goldenBuffer, goldenSize); + + if (src_nat) { + address = htonl(public_ip); + port = htons(public_port); + + memcpy(&tmp_buff[IPV4_SRC_ADDR_OFFSET + IPv4_offset], &address, sizeof(address)); + memcpy(&tmp_buff[IPV4_SRC_PORT_OFFSET + IPv4_offset], &port, sizeof(port)); + + val = (*(uint32_t*)(&receivedBuffer[IPV4_SRC_ADDR_OFFSET + IPv4_offset + recv_offset])); + if (address != val) + LOG_MSG_ERROR("received src ip 0x%X != 0x%X\n", val, address); + + val = (*(uint16_t*)(&receivedBuffer[IPV4_SRC_PORT_OFFSET + IPv4_offset + recv_offset])); + if (port != val) + LOG_MSG_ERROR("received src port %d != %d\n", val, port); + } + else { + address = htonl(private_ip); + port = htons(private_port); + + memcpy(&tmp_buff[IPV4_DST_ADDR_OFFSET + IPv4_offset], &address, sizeof(address)); + memcpy(&tmp_buff[IPV4_DST_PORT_OFFSET + IPv4_offset], &port, sizeof(port)); + + val = (*(uint32_t*)(&receivedBuffer[IPV4_DST_ADDR_OFFSET + IPv4_offset + +recv_offset])); + if (address != val) + LOG_MSG_ERROR("received dst ip 0x%X != 0x%X\n", val, address); + val = (*(uint16_t*)(&receivedBuffer[IPV4_DST_PORT_OFFSET + IPv4_offset + recv_offset])); + if (port != val) + LOG_MSG_ERROR("received dst port %d != %d\n", val, port); + } + + memcpy(&tmp_buff[IPV4_IP_CHECKSUM_OFFSET + IPv4_offset], &ip_checksum, sizeof(uint16_t)); + val = (*(uint16_t*)(&receivedBuffer[IPV4_IP_CHECKSUM_OFFSET + IPv4_offset + recv_offset])); + if (ip_checksum != val) + LOG_MSG_ERROR("received checksum %d != %d\n", val, ip_checksum); + + memcpy(&tmp_buff[IPV4_TCP_CHECKSUM_OFFSET + IPv4_offset], &tcp_checksum, sizeof(uint16_t)); + val = (*(uint16_t*)(&receivedBuffer[IPV4_TCP_CHECKSUM_OFFSET + IPv4_offset + recv_offset])); + if (tcp_checksum != val) + LOG_MSG_ERROR("received checksum %d != %d\n", val, tcp_checksum); + + size_t j; + char tmpBuffer[512] = { 0 }; + + for (j = 0; j < receivedSize; j++) + snprintf(&tmpBuffer[3 * j], sizeof(tmpBuffer) - (3 * j + 1), " %02X", tmp_buff[j]); + LOG_MSG_STACK("expected packet should be (%zu)\n%s\n", receivedSize, tmpBuffer); + + result = !memcmp((void*)tmp_buff, (void*)(receivedBuffer + recv_offset), goldenSize); + if (!result) + LOG_MSG_ERROR("buffers comparison failed!!\n"); + + delete[] tmp_buff; + + return result; + } + + bool CreateMetdataRoutingRule(const char * bypass0) + { + LOG_MSG_DEBUG("Entering\n"); + struct ipa_ioc_add_rt_rule *rt_rule0 = NULL; + struct ipa_rt_rule_add *rt_rule_entry; + + rt_rule0 = (struct ipa_ioc_add_rt_rule *) + calloc(1, + sizeof(struct ipa_ioc_add_rt_rule) + + 1 * sizeof(struct ipa_rt_rule_add) + ); + if (!rt_rule0) { + LOG_MSG_ERROR("calloc failed to allocate rt_rule0\n"); + return false; + } + + rt_rule0->num_rules = 1; + rt_rule0->ip = IPA_IP_v4; + rt_rule0->commit = true; + strlcpy(rt_rule0->rt_tbl_name, bypass0, sizeof(rt_rule0->rt_tbl_name)); + + rt_rule_entry = &rt_rule0->rules[0]; + rt_rule_entry->at_rear = 0; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST2_CONS; + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_META_DATA; + rt_rule_entry->rule.attrib.meta_data = m_metadata; + rt_rule_entry->rule.attrib.meta_data_mask = 0xFFFFFFFF;// Filter exact metadata value + if (false == m_routing.AddRoutingRule(rt_rule0)) + { + LOG_MSG_ERROR("Routing rule addition(rt_rule0) failed!\n"); + Free(rt_rule0); + return false; + } + + Free(rt_rule0); + LOG_MSG_DEBUG("Leaving\n"); + return true; + } + + bool CreateHashableRoutingRules(const char * bypass0) + { + LOG_MSG_DEBUG("Entering\n"); + struct ipa_ioc_add_rt_rule *rt_rule0 = 0, *rt_rule1 = 0; + struct ipa_rt_rule_add *rt_rule_entry; + + rt_rule0 = (struct ipa_ioc_add_rt_rule *) + calloc(1, + sizeof(struct ipa_ioc_add_rt_rule) + + 2 * sizeof(struct ipa_rt_rule_add) + ); + if (!rt_rule0) { + LOG_MSG_ERROR("calloc failed to allocate rt_rule0\n"); + return false; + } + + rt_rule0->num_rules = 2; + rt_rule0->ip = IPA_IP_v4; + rt_rule0->commit = true; + strlcpy(rt_rule0->rt_tbl_name, bypass0, sizeof(rt_rule0->rt_tbl_name)); + + rt_rule_entry = &rt_rule0->rules[0]; + rt_rule_entry->at_rear = 0; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST2_CONS; + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v4.dst_addr = m_private_ip; + rt_rule_entry->rule.attrib.u.v4.dst_addr_mask = 0xFFFFFFFF;// Exact match + rt_rule_entry->rule.hashable = 1; + + rt_rule_entry = &rt_rule0->rules[1]; + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST3_CONS; + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v4.dst_addr = m_private_ip2; + rt_rule_entry->rule.attrib.u.v4.dst_addr_mask = 0xFFFFFFFF;// Exact match + rt_rule_entry->rule.hashable = 1; + if (false == m_routing.AddRoutingRule(rt_rule0)) + { + LOG_MSG_ERROR("Routing rule addition(rt_rule0) failed!\n"); + Free(rt_rule1); + Free(rt_rule0); + return false; + } + + Free(rt_rule0); + LOG_MSG_DEBUG("Leaving\n"); + return true; + } + + // This function creates three IPv4 bypass routing entries and commits them. + bool CreateThreeIPv4BypassRoutingTables(const char * bypass0, const char * bypass1, const char * bypass2) + { + LOG_MSG_DEBUG("Entering\n"); + struct ipa_ioc_add_rt_rule *rt_rule0 = 0, *rt_rule1 = 0, *rt_rule2 = 0; + struct ipa_rt_rule_add *rt_rule_entry; + + rt_rule0 = (struct ipa_ioc_add_rt_rule *) + calloc(1, + sizeof(struct ipa_ioc_add_rt_rule) + + 1 * sizeof(struct ipa_rt_rule_add) + ); + if (!rt_rule0) { + LOG_MSG_ERROR("calloc failed to allocate rt_rule0\n"); + return false; + } + rt_rule1 = (struct ipa_ioc_add_rt_rule *) + calloc(1, + sizeof(struct ipa_ioc_add_rt_rule) + + 1 * sizeof(struct ipa_rt_rule_add) + ); + if (!rt_rule1) { + LOG_MSG_ERROR("calloc failed to allocate rt_rule1\n"); + Free(rt_rule0); + return false; + } + rt_rule2 = (struct ipa_ioc_add_rt_rule *) + calloc(1, + sizeof(struct ipa_ioc_add_rt_rule) + + 1 * sizeof(struct ipa_rt_rule_add) + ); + if (!rt_rule2) { + LOG_MSG_ERROR("calloc failed to allocate rt_rule2\n"); + Free(rt_rule0); + Free(rt_rule1); + return false; + } + + rt_rule0->num_rules = 1; + rt_rule0->ip = IPA_IP_v4; + rt_rule0->commit = true; + strlcpy(rt_rule0->rt_tbl_name, bypass0, sizeof(rt_rule0->rt_tbl_name)); + + rt_rule_entry = &rt_rule0->rules[0]; + rt_rule_entry->at_rear = 0; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST2_CONS; + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v4.dst_addr = 0xaabbccdd; + rt_rule_entry->rule.attrib.u.v4.dst_addr_mask = 0x00000000;// All Packets will get a "Hit" + if (false == m_routing.AddRoutingRule(rt_rule0)) + { + LOG_MSG_ERROR("Routing rule addition(rt_rule0) failed!\n"); + Free(rt_rule2); + Free(rt_rule1); + Free(rt_rule0); + return false; + } + + + rt_rule1->num_rules = 1; + rt_rule1->ip = IPA_IP_v4; + rt_rule1->commit = true; + strlcpy(rt_rule1->rt_tbl_name, bypass1, sizeof(rt_rule1->rt_tbl_name)); + rt_rule_entry = &rt_rule1->rules[0]; + rt_rule_entry->at_rear = 0; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST3_CONS; + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v4.dst_addr = 0xaabbccdd; + rt_rule_entry->rule.attrib.u.v4.dst_addr_mask = 0x00000000;// All Packets will get a "Hit" + if (false == m_routing.AddRoutingRule(rt_rule1)) + { + LOG_MSG_ERROR("Routing rule addition(rt_rule1) failed!\n"); + Free(rt_rule2); + Free(rt_rule1); + Free(rt_rule0); + return false; + } + + + rt_rule2->num_rules = 1; + rt_rule2->ip = IPA_IP_v4; + rt_rule2->commit = true; + strlcpy(rt_rule2->rt_tbl_name, bypass2, sizeof(rt_rule2->rt_tbl_name)); + rt_rule_entry = &rt_rule2->rules[0]; + rt_rule_entry->at_rear = 0; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST4_CONS; + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v4.dst_addr = 0xaabbccdd; + rt_rule_entry->rule.attrib.u.v4.dst_addr_mask = 0x00000000;// All Packets will get a "Hit" + if (false == m_routing.AddRoutingRule(rt_rule2)) + { + LOG_MSG_ERROR("Routing rule addition(rt_rule2) failed!\n"); + Free(rt_rule2); + Free(rt_rule1); + Free(rt_rule0); + return false; + } + + + Free(rt_rule2); + Free(rt_rule1); + Free(rt_rule0); + LOG_MSG_DEBUG("Leaving\n"); + return true; + } + + void Load8021QPacket() + { + m_sendSize = sizeof(m_sendBuffer); + LoadDefault802_1Q(IPA_IP_v4, m_sendBuffer, m_sendSize); + } + + virtual bool ModifyPackets() = 0; + virtual bool AddRules() = 0; + virtual bool SendPackets() = 0; + virtual bool ReceivePacketsAndCompare() = 0; + + bool Run() + { + bool res = false; + bool isSuccess = false; + + LOG_MSG_DEBUG("Entering\n"); + + // Add the relevant filtering rules + res = AddRules(); + if (false == res) { + LOG_MSG_ERROR("Failed adding filtering rules.\n"); + return false; + } + + // Load input data (IP packet) from file + res = LoadFiles(m_IpaIPType); + if (false == res) { + LOG_MSG_ERROR("Failed loading files.\n"); + return false; + } + + res = ModifyPackets(); + if (false == res) { + LOG_MSG_ERROR("Failed to modify packets.\n"); + return false; + } + + res = SendPackets(); + if (res == false) { + LOG_MSG_ERROR("failed to send packets\n"); + return false; + } + // Receive packets from the channels and compare results + isSuccess = ReceivePacketsAndCompare(); + + LOG_MSG_DEBUG("Returning %d\n", isSuccess); + + return isSuccess; + } // Run() + + /** + * calc_ip_cksum_diff() - Calculate the source nat + * IP checksum diff + * @pub_ip_addr: [in] public ip address + * @priv_ip_addr: [in] Private ip address + * + * source nat ip checksum different is calculated as + * public_ip_addr - private_ip_addr + * Here we are using 1's complement to represent -negative number. + * So take 1's complement of private ip addr and add it + * to public ip addr. + * + * Returns: >0 ip checksum diff + */ + uint16_t calc_ip_cksum_diff(uint32_t pub_ip_addr, + uint32_t priv_ip_addr) + { + uint16_t ret; + uint32_t cksum = 0; + + /* Add LSB(2 bytes) of public ip address to cksum */ + cksum += (pub_ip_addr & 0xFFFF); + + /* Add MSB(2 bytes) of public ip address to cksum + and check for carry forward(CF), if any add it + */ + cksum += (pub_ip_addr >> 16); + IPA_16BIT_ROUND_UP(cksum); + + /* Calculate the 1's complement of private ip address */ + priv_ip_addr = (~priv_ip_addr); + + /* Add LSB(2 bytes) of private ip address to cksum + and check for carry forward(CF), if any add it + */ + cksum += (priv_ip_addr & 0xFFFF); + IPA_16BIT_ROUND_UP(cksum); + + /* Add MSB(2 bytes) of private ip address to cksum + and check for carry forward(CF), if any add it + */ + cksum += (priv_ip_addr >> 16); + IPA_16BIT_ROUND_UP(cksum); + + /* Return the LSB(2 bytes) of checksum */ + ret = (uint16_t)cksum; + return ret; + } + + /** + * calc_tcp_udp_cksum() - Calculate the source nat + * TCP/UDP checksum diff + * @pub_ip_addr: [in] public ip address + * @pub_port: [in] public tcp/udp port + * @priv_ip_addr: [in] Private ip address + * @priv_port: [in] Private tcp/udp prot + * + * source nat tcp/udp checksum is calculated as + * (pub_ip_addr + pub_port) - (priv_ip_addr + priv_port) + * Here we are using 1's complement to represent -ve number. + * So take 1's complement of prviate ip addr &private port + * and add it public ip addr & public port. + * + * Returns: >0 tcp/udp checksum diff + */ + uint16_t calc_tcp_udp_cksum_diff(uint32_t pub_ip_addr, + uint16_t pub_port, + uint32_t priv_ip_addr, + uint16_t priv_port) + { + uint16_t ret = 0; + uint32_t cksum = 0; + + /* Add LSB(2 bytes) of public ip address to cksum */ + cksum += (pub_ip_addr & 0xFFFF); + + /* Add MSB(2 bytes) of public ip address to cksum + and check for carry forward(CF), if any add it + */ + cksum += (pub_ip_addr >> 16); + IPA_16BIT_ROUND_UP(cksum); + + /* Add public port to cksum and + check for carry forward(CF), if any add it */ + cksum += pub_port; + IPA_16BIT_ROUND_UP(cksum); + + /* Calculate the 1's complement of private ip address */ + priv_ip_addr = (~priv_ip_addr); + + /* Add LSB(2 bytes) of private ip address to cksum + and check for carry forward(CF), if any add it + */ + cksum += (priv_ip_addr & 0xFFFF); + IPA_16BIT_ROUND_UP(cksum); + + /* Add MSB(2 bytes) of private ip address to cksum + and check for carry forward(CF), if any add + */ + cksum += (priv_ip_addr >> 16); + IPA_16BIT_ROUND_UP(cksum); + + /* Calculate the 1's complement of private port */ + priv_port = (~priv_port); + + /* Add public port to cksum and + check for carry forward(CF), if any add it */ + cksum += priv_port; + IPA_16BIT_ROUND_UP(cksum); + + /* return the LSB(2 bytes) of checksum */ + ret = (uint16_t)cksum; + return ret; + } + + ~IpaNatBlockTestFixture() + { + m_sendSize = 0; + m_sendSize2 = 0; + m_sendSize3 = 0; + } + + static Filtering m_filtering; + static RoutingDriverWrapper m_routing; + InterfaceAbstraction m_producer; + InterfaceAbstraction m_producer2; + InterfaceAbstraction m_consumer; + InterfaceAbstraction m_consumer2; + InterfaceAbstraction m_defaultConsumer; + + static const size_t BUFF_MAX_SIZE = 1024; + + Byte m_sendBuffer[BUFF_MAX_SIZE]; // First input file / IP packet + Byte m_sendBuffer2[BUFF_MAX_SIZE]; // Second input file / IP packet + Byte m_sendBuffer3[BUFF_MAX_SIZE]; // Third input file (default) / IP packet + size_t m_sendSize; + size_t m_sendSize2; + size_t m_sendSize3; + enum ipa_ip_type m_IpaIPType; + enum ipv6_ext_hdr_type m_extHdrType; + uint32_t m_tbl_hdl; + uint32_t m_nat_rule_hdl1; + uint32_t m_public_ip; + uint32_t m_public_ip2; + uint32_t m_private_ip; + uint32_t m_private_ip2; + uint32_t m_target_ip; + uint16_t m_public_port; + uint16_t m_public_port2; + uint16_t m_private_port; + uint16_t m_private_port2; + uint16_t m_target_port; + uint32_t m_metadata; +private: +}; + +RoutingDriverWrapper IpaNatBlockTestFixture::m_routing; +Filtering IpaNatBlockTestFixture::m_filtering; + +/*---------------------------------------------------------------------------*/ +/* Test001: Single PDN src NAT test */ +/* NOTE: other classes are derived from this class - change carefully */ +/*---------------------------------------------------------------------------*/ +class IpaNatBlockTest001 : public IpaNatBlockTestFixture +{ +public: + IpaNatBlockTest001() + { + m_name = "IpaNatBlockTest001"; + m_description = + "NAT block test 001 - single PDN src NAT test\ + 1. Generate and commit three routing tables (only one is used). \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit one filtering rule: (DST & Mask Match). \ + action go to src NAT \ + All DST_IP == (193.23.22.1 & 0.255.255.255)traffic goes to NAT block \ + 3. generate and commit one NAT rule:\ + private ip 194.23.22.1 --> public ip 192.23.22.1"; + m_private_ip = 0xC2171601; /* 194.23.22.1 */ + m_private_port = 5678; + m_public_ip = 0xC0171601; /* "192.23.22.1" */ + m_public_port = 9050; + m_target_ip = 0xC1171601; /* 193.23.22.1 */ + m_target_port = 1234; + Register(*this); + } + + + virtual bool AddRules() + { + LOG_MSG_DEBUG("Entering\n"); + + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + struct ipa_ioc_get_rt_tbl routing_table0; + + if (!CreateThreeIPv4BypassRoutingTables(bypass0, bypass1, bypass2)) + { + LOG_MSG_ERROR("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + + LOG_MSG_DEBUG("CreateThreeBypassRoutingTables completed successfully\n"); + routing_table0.ip = IPA_IP_v4; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + LOG_MSG_ERROR("m_routing.GetRoutingTable(&routing_table0=0x%p) Failed.\n", &routing_table0); + return false; + } + LOG_MSG_DEBUG("%s route table handle = %u\n", bypass0, routing_table0.hdl); + + IPAFilteringTable FilterTable0; + struct ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v4, IPA_CLIENT_TEST_PROD, false, 1); + LOG_MSG_DEBUG("FilterTable*.Init Completed Successfully..\n"); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1, flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl = -1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action = IPA_PASS_TO_SRC_NAT; + flt_rule_entry.rule.rt_tbl_hdl = routing_table0.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + flt_rule_entry.rule.attrib.u.v4.dst_addr_mask = 0x00FFFFFF; // Mask + flt_rule_entry.rule.attrib.u.v4.dst_addr = m_target_ip; // Filter DST_IP == 193.23.22.1 + flt_rule_entry.rule.pdn_idx = 0; + flt_rule_entry.rule.set_metadata = 0; + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + LOG_MSG_ERROR("Error Adding Rule to Filter Table, aborting...\n"); + return false; + } + else + { + LOG_MSG_DEBUG("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl, FilterTable0.ReadRuleFromTable(0)->status); + } + + //NAT table and rules creation + int total_entries = 20; + int ret; + ipa_nat_ipv4_rule ipv4_rule; + + ret = ipa_nat_add_ipv4_tbl(m_public_ip, m_mem_type, total_entries, &m_tbl_hdl); + if (ret) { + LOG_MSG_DEBUG("failed creating NAT table\n"); + return false; + } + LOG_MSG_DEBUG("nat table added, hdl %d, public ip 0x%X\n", m_tbl_hdl, + m_public_ip); + + ipv4_rule.target_ip = m_target_ip; + ipv4_rule.target_port = m_target_port; + ipv4_rule.private_ip = m_private_ip; + ipv4_rule.private_port = m_private_port; + ipv4_rule.protocol = IPPROTO_TCP; + ipv4_rule.public_port = m_public_port; + ipv4_rule.pdn_index = 0; + + ret = ipa_nat_add_ipv4_rule(m_tbl_hdl, &ipv4_rule, &m_nat_rule_hdl1); + if (ret) { + LOG_MSG_ERROR("failed adding NAT rule 0\n"); + return false; + } + LOG_MSG_DEBUG("NAT rule added, hdl %d, data: 0x%X, %d, 0x%X, %d, %d, %d\n", + m_nat_rule_hdl1, ipv4_rule.target_ip, ipv4_rule.target_port, + ipv4_rule.private_ip, ipv4_rule.private_port, + ipv4_rule.protocol, ipv4_rule.public_port); + + LOG_MSG_DEBUG("Leaving"); + return true; + }// AddRules() + + virtual bool ModifyPackets() + { + uint32_t address; + uint16_t port; + char flags = 0x18; + + address = htonl(m_target_ip);//193.23.22.1 + memcpy(&m_sendBuffer[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + port = htons(m_target_port); + memcpy(&m_sendBuffer[IPV4_DST_PORT_OFFSET], &port, sizeof(port)); + + address = htonl(m_private_ip);/* 194.23.22.1 */ + memcpy(&m_sendBuffer[IPV4_SRC_ADDR_OFFSET], &address, sizeof(address)); + port = htons(m_private_port); + memcpy(&m_sendBuffer[IPV4_SRC_PORT_OFFSET], &port, sizeof(port)); + + //make sure the FIN flag is not set, otherwise we will get a NAT miss + memcpy(&m_sendBuffer[IPV4_TCP_FLAGS_OFFSET],&flags , sizeof(flags)); + return true; + }// ModifyPacktes () + + virtual bool SendPackets() + { + bool isSuccess = false; + + // Send first packet + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) + { + LOG_MSG_ERROR("SendData failure.\n"); + return false; + } + + LOG_MSG_DEBUG("sent successfully one packet\n"); + return true; + } + + virtual bool ReceivePacketsAndCompare() + { + size_t receivedSize = 0; + bool isSuccess = true; + + // Receive results + Byte *rxBuff1 = new Byte[0x400]; + + if (NULL == rxBuff1) + { + LOG_MSG_ERROR("Memory allocation error.\n"); + return false; + } + + receivedSize = m_consumer.ReceiveData(rxBuff1, 0x400); + LOG_MSG_DEBUG("Received %zu bytes on %s.\n", receivedSize, m_consumer.m_fromChannelName.c_str()); + + // Compare results + if (!CompareResultVsGoldenNat( + m_sendBuffer, m_sendSize, + rxBuff1, receivedSize, + m_private_ip, m_public_ip, + m_private_port, m_public_port, + true)) + { + LOG_MSG_ERROR("Comparison of Buffer0 Failed!\n"); + isSuccess = false; + } + + char recievedBuffer[256] = { 0 }; + char SentBuffer[256] = { 0 }; + size_t j; + + for (j = 0; j < m_sendSize; j++) + snprintf(&SentBuffer[3 * j], sizeof(SentBuffer) - (3 * j + 1), " %02X", m_sendBuffer[j]); + for (j = 0; j < receivedSize; j++) + snprintf(&recievedBuffer[3 * j], sizeof(recievedBuffer) - (3 * j + 1), " %02X", rxBuff1[j]); + LOG_MSG_STACK("sent Value1 (%zu)\n%s\n, Received Value1(%zu)\n%s\n", m_sendSize, SentBuffer, receivedSize, recievedBuffer); + + delete[] rxBuff1; + + return isSuccess; + } +}; + +/*---------------------------------------------------------------------------*/ +/* Test002: Single PDN dst NAT test */ +/* NOTE: other classes are derived from this class - change carefully */ +/*---------------------------------------------------------------------------*/ +class IpaNatBlockTest002 : public IpaNatBlockTestFixture +{ +public: + IpaNatBlockTest002() + { + m_name = "IpaNatBlockTest002"; + m_description = + "NAT block test 002 - single PDN dst NAT test\ + 1. Generate and commit three routing tables (only one is used). \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit one filtering rule: (DST & Mask Match). \ + action go to dst NAT \ + All DST_IP == (192.23.22.1 & 0.255.255.255)traffic goes to NAT block (public IP filtering) \ + 3. generate and commit one NAT rule:\ + public ip 192.23.22.1 --> private ip 194.23.22.1 "; + m_private_ip = 0xC2171601; /* 194.23.22.1 */ + m_private_port = 5678; + m_public_ip = 0xC0171601; /* "192.23.22.1" */ + m_public_port = 9050; + m_target_ip = 0xC1171601; /* 193.23.22.1 */ + m_target_port = 1234; + Register(*this); + } + + + virtual bool AddRules() + { + LOG_MSG_DEBUG("Entering\n"); + + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + struct ipa_ioc_get_rt_tbl routing_table0; + + if (!CreateThreeIPv4BypassRoutingTables(bypass0, bypass1, bypass2)) + { + LOG_MSG_ERROR("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + + LOG_MSG_DEBUG("CreateThreeBypassRoutingTables completed successfully\n"); + routing_table0.ip = IPA_IP_v4; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + LOG_MSG_ERROR("m_routing.GetRoutingTable(&routing_table0=0x%p) Failed.\n", &routing_table0); + return false; + } + LOG_MSG_DEBUG("%s route table handle = %u\n", bypass0, routing_table0.hdl); + + IPAFilteringTable FilterTable0; + struct ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v4, IPA_CLIENT_TEST_PROD, false, 3); + LOG_MSG_DEBUG("FilterTable*.Init Completed Successfully..\n"); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1, flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl = -1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action = IPA_PASS_TO_DST_NAT; + flt_rule_entry.rule.rt_tbl_hdl = routing_table0.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + flt_rule_entry.rule.attrib.u.v4.dst_addr_mask = 0x00FFFFFF; // Mask + flt_rule_entry.rule.attrib.u.v4.dst_addr = m_public_ip; // Filter DST_IP == 192.23.22.1 + flt_rule_entry.rule.pdn_idx = 0; + flt_rule_entry.rule.set_metadata = 0; + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + LOG_MSG_ERROR("Error Adding Rule to Filter Table, aborting...\n"); + return false; + } + else + { + LOG_MSG_DEBUG("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl, FilterTable0.ReadRuleFromTable(0)->status); + } + + //NAT table and rules creation + int total_entries = 20; + int ret; + ipa_nat_ipv4_rule ipv4_rule; + uint32_t pub_ip_add = m_public_ip; + + ret = ipa_nat_add_ipv4_tbl(pub_ip_add, m_mem_type, total_entries, &m_tbl_hdl); + if (ret) { + LOG_MSG_ERROR("Leaving, failed creating NAT table\n"); + return false; + } + + LOG_MSG_DEBUG("nat table added, hdl %d, public ip 0x%X\n", m_tbl_hdl, + pub_ip_add); + + ipv4_rule.target_ip = m_target_ip; + ipv4_rule.target_port = m_target_port; + ipv4_rule.private_ip = m_private_ip; + ipv4_rule.private_port = m_private_port; + ipv4_rule.protocol = IPPROTO_TCP; + ipv4_rule.public_port = m_public_port; + ipv4_rule.pdn_index = 0; + + ret = ipa_nat_add_ipv4_rule(m_tbl_hdl, &ipv4_rule, &m_nat_rule_hdl1); + if (ret) { + LOG_MSG_ERROR("Leaving, failed adding NAT rule 0\n"); + return false; + } + + LOG_MSG_DEBUG("NAT rule added, hdl %d, data: 0x%X, %d, 0x%X, %d, %d, %d\n", + m_nat_rule_hdl1, ipv4_rule.target_ip, ipv4_rule.target_port, + ipv4_rule.private_ip, ipv4_rule.private_port, + ipv4_rule.protocol, ipv4_rule.public_port); + + LOG_MSG_DEBUG("Leaving\n"); + return true; + }// AddRules() + + virtual bool ModifyPackets() + { + uint32_t address; + uint16_t port; + char flags = 0x18; + + address = htonl(m_public_ip);//192.23.22.1 + memcpy(&m_sendBuffer[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + port = htons(m_public_port); + memcpy(&m_sendBuffer[IPV4_DST_PORT_OFFSET], &port, sizeof(port)); + + address = htonl(m_target_ip);/* 193.23.22.1 */ + memcpy(&m_sendBuffer[IPV4_SRC_ADDR_OFFSET], &address, sizeof(address)); + port = htons(m_target_port); + memcpy(&m_sendBuffer[IPV4_SRC_PORT_OFFSET], &port, sizeof(port)); + + //make sure the FIN flag is not set, otherwise we will get a NAT miss + memcpy(&m_sendBuffer[IPV4_TCP_FLAGS_OFFSET], &flags, sizeof(flags)); + + return true; + }// ModifyPacktes () + + virtual bool SendPackets() + { + bool isSuccess = false; + + // Send first packet + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) + { + LOG_MSG_ERROR("SendData failure.\n"); + return false; + } + + LOG_MSG_DEBUG("sent successfully one packet\n"); + return true; + } + + virtual bool ReceivePacketsAndCompare() + { + size_t receivedSize = 0; + bool isSuccess = true; + + // Receive results + Byte *rxBuff1 = new Byte[0x400]; + + if (NULL == rxBuff1) + { + LOG_MSG_ERROR("Memory allocation error.\n"); + return false; + } + + receivedSize = m_consumer.ReceiveData(rxBuff1, 0x400); + LOG_MSG_DEBUG("Received %zu bytes on %s.\n", receivedSize, m_consumer.m_fromChannelName.c_str()); + + // Compare results + if (!CompareResultVsGoldenNat( + m_sendBuffer, m_sendSize, + rxBuff1, receivedSize, + m_private_ip, m_public_ip, + m_private_port, m_public_port, + false)) + { + LOG_MSG_ERROR("Comparison of Buffer0 Failed!\n"); + isSuccess = false; + } + + char recievedBuffer[256] = { 0 }; + char SentBuffer[256] = { 0 }; + size_t j; + + for (j = 0; j < m_sendSize; j++) + snprintf(&SentBuffer[3 * j], sizeof(SentBuffer) - (3 * j + 1), " %02X", m_sendBuffer[j]); + for (j = 0; j < receivedSize; j++) + snprintf(&recievedBuffer[3 * j], sizeof(recievedBuffer) - (3 * j + 1), " %02X", rxBuff1[j]); + LOG_MSG_STACK("sent Value1 (%zu)\n%s\n, Received Value1(%zu)\n%s\n", m_sendSize, SentBuffer, receivedSize, recievedBuffer); + + delete[] rxBuff1; + + return isSuccess; + } +}; + +/*---------------------------------------------------------------------------*/ +/* Test003: Multi PDN src NAT test */ +/* NOTE: other classes are derived from this class - change carefully */ +/*---------------------------------------------------------------------------*/ +class IpaNatBlockTest003 : public IpaNatBlockTestFixture +{ +public: + IpaNatBlockTest003() + { + m_name = "IpaNatBlockTest003"; + m_description = + "NAT block test 003 - Multi PDN src NAT test\ + 1. Generate and commit three routing tables (two are used). \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit two filtering rule: (DST & Mask Match). \ + - action go to src NAT \ + All SRC_IP == (194.23.22.1 & 0.255.255.255)traffic goes to NAT block \ + All SRC_IP == (197.23.22.1 & 0.255.255.255)traffic goes to NAT block \ + 3. generate and commit two NAT rules:\ + private ip 194.23.22.1 --> public ip 192.23.22.1 \ + private ip 197.23.22.1 --> public ip 195.23.22.1"; + m_private_ip = 0xC2171601; /* 194.23.22.1 */ + m_private_port = 5678; + m_private_ip2 = 0xC5171601; /* 197.23.22.1 */ + m_private_port2 = 5679; + m_public_ip = 0xC0171601; /* "192.23.22.1" */ + m_public_port = 9050; + m_public_ip2 = 0xC3171601; /* "195.23.22.1" */ + m_public_port2 = 9051; + m_target_ip = 0xC1171601; /* 193.23.22.1 */ + m_target_port = 1234; + m_minIPAHwType = IPA_HW_v4_0; + Register(*this); + } + + + virtual bool AddRules() + { + LOG_MSG_DEBUG("Entering\n"); + + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + struct ipa_ioc_get_rt_tbl routing_table0, routing_table1; + + if (!CreateThreeIPv4BypassRoutingTables(bypass0, bypass1, bypass2)) + { + LOG_MSG_ERROR("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + + LOG_MSG_DEBUG("CreateThreeBypassRoutingTables completed successfully\n"); + routing_table0.ip = IPA_IP_v4; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + LOG_MSG_ERROR("m_routing.GetRoutingTable(&routing_table0=0x%p) Failed.\n", &routing_table0); + return false; + } + LOG_MSG_DEBUG("%s route table handle = %u\n", bypass0, routing_table0.hdl); + + routing_table1.ip = IPA_IP_v4; + strlcpy(routing_table1.name, bypass1, sizeof(routing_table1.name)); + if (!m_routing.GetRoutingTable(&routing_table1)) + { + LOG_MSG_ERROR("m_routing.GetRoutingTable(&routing_table1=0x%p) Failed.\n", &routing_table1); + return false; + } + LOG_MSG_DEBUG("%s route table handle = %u\n", bypass1, routing_table1.hdl); + + IPAFilteringTable FilterTable0; + struct ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v4, IPA_CLIENT_TEST_PROD, false, 2); + LOG_MSG_DEBUG("FilterTable*.Init Completed Successfully..\n"); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1, flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl = -1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action = IPA_PASS_TO_SRC_NAT; + flt_rule_entry.rule.rt_tbl_hdl = routing_table0.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_SRC_ADDR; + flt_rule_entry.rule.attrib.u.v4.src_addr_mask = 0xFFFFFFFF; // Mask + flt_rule_entry.rule.attrib.u.v4.src_addr = m_private_ip; // Filter SRC_IP == 194.23.22.1 + flt_rule_entry.rule.pdn_idx = 0; + flt_rule_entry.rule.set_metadata = 0; + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + LOG_MSG_ERROR("Error Adding Rule to Filter Table, aborting...\n"); + return false; + } + + // Configuring Filtering Rule No.1 + flt_rule_entry.rule.rt_tbl_hdl = routing_table1.hdl; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.attrib.u.v4.src_addr = m_private_ip2; // Filter SRC_IP == 197.23.22.1 + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + LOG_MSG_ERROR("Error Adding Rule to Filter Table, aborting...\n"); + return false; + } + else + { + LOG_MSG_DEBUG("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl, FilterTable0.ReadRuleFromTable(0)->status); + LOG_MSG_DEBUG("flt rule hdl1=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(1)->flt_rule_hdl, FilterTable0.ReadRuleFromTable(1)->status); + } + + //NAT table and rules creation + int total_entries = 20; + int ret; + ipa_nat_ipv4_rule ipv4_rule; + uint32_t pub_ip_add = m_public_ip; + ipa_nat_pdn_entry pdn_info; + + // first create the NAT table + ret = ipa_nat_add_ipv4_tbl(pub_ip_add, m_mem_type, total_entries, &m_tbl_hdl); + if (ret) { + LOG_MSG_ERROR("Leaving, failed creating NAT table\n"); + return false; + } + + LOG_MSG_DEBUG("nat table added, hdl %d, public ip 0x%X\n", m_tbl_hdl, + pub_ip_add); + + // modify the PDN entries that will be pointed by the NAT rules + pdn_info.public_ip = m_public_ip; + pdn_info.src_metadata = 0; + pdn_info.dst_metadata = 0; + ret = ipa_nat_modify_pdn(m_tbl_hdl, 0, &pdn_info); + if (ret) { + LOG_MSG_ERROR("Leaving, failed Modifying PDN entry 0 \n"); + return false; + } + + pdn_info.public_ip = m_public_ip2; + pdn_info.src_metadata = 0; + pdn_info.dst_metadata = 0; + ret = ipa_nat_modify_pdn(m_tbl_hdl, 1, &pdn_info); + if (ret) { + LOG_MSG_ERROR("Leaving, failed Modifying PDN entry 1 \n"); + return false; + } + + ipv4_rule.target_ip = m_target_ip; + ipv4_rule.target_port = m_target_port; + ipv4_rule.private_ip = m_private_ip; + ipv4_rule.private_port = m_private_port; + ipv4_rule.protocol = IPPROTO_TCP; + ipv4_rule.public_port = m_public_port; + ipv4_rule.pdn_index = 0; + + ret = ipa_nat_add_ipv4_rule(m_tbl_hdl, &ipv4_rule, &m_nat_rule_hdl1); + if (ret) { + LOG_MSG_ERROR("Leaving, failed adding NAT rule 0\n"); + return false; + } + + LOG_MSG_DEBUG("NAT rule added, hdl %d, data: 0x%X, %d, 0x%X, %d, %d, %d\n", + m_nat_rule_hdl1, ipv4_rule.target_ip, ipv4_rule.target_port, + ipv4_rule.private_ip, ipv4_rule.private_port, + ipv4_rule.protocol, ipv4_rule.public_port); + + ipv4_rule.private_ip = m_private_ip2; + ipv4_rule.private_port = m_private_port2; + ipv4_rule.public_port = m_public_port2; + ipv4_rule.pdn_index = 1; + + ret = ipa_nat_add_ipv4_rule(m_tbl_hdl, &ipv4_rule, &m_nat_rule_hdl1); + if (ret) { + LOG_MSG_ERROR("Leaving, failed adding NAT rule 1\n"); + return false; + } + + LOG_MSG_DEBUG("NAT rule 2 added, hdl %d, data: 0x%X, %d, 0x%X, %d, %d, %d\n", + m_nat_rule_hdl1, ipv4_rule.target_ip, ipv4_rule.target_port, + ipv4_rule.private_ip, ipv4_rule.private_port, + ipv4_rule.protocol, ipv4_rule.public_port); + + LOG_MSG_DEBUG("Leaving\n"); + return true; + }// AddRules() + + virtual bool ModifyPackets() + { + uint32_t address; + uint16_t port; + char flags = 0x18; + + //first packet private ip 194.23.22.1 --> public ip 192.23.22.1 + address = htonl(m_target_ip);//193.23.22.1 + memcpy(&m_sendBuffer[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + port = htons(m_target_port); + memcpy(&m_sendBuffer[IPV4_DST_PORT_OFFSET], &port, sizeof(port)); + + address = htonl(m_private_ip);/* 194.23.22.1 */ + memcpy(&m_sendBuffer[IPV4_SRC_ADDR_OFFSET], &address, sizeof(address)); + port = htons(m_private_port); + memcpy(&m_sendBuffer[IPV4_SRC_PORT_OFFSET], &port, sizeof(port)); + + //make sure the FIN flag is not set, otherwise we will get a NAT miss + memcpy(&m_sendBuffer[IPV4_TCP_FLAGS_OFFSET], &flags, sizeof(flags)); + + // second packet private ip 197.23.22.1 --> public ip 195.23.22.1 + address = htonl(m_target_ip);//193.23.22.1 + memcpy(&m_sendBuffer2[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + port = htons(m_target_port); + memcpy(&m_sendBuffer2[IPV4_DST_PORT_OFFSET], &port, sizeof(port)); + + address = htonl(m_private_ip2);/* 197.23.22.1 */ + memcpy(&m_sendBuffer2[IPV4_SRC_ADDR_OFFSET], &address, sizeof(address)); + port = htons(m_private_port2); + memcpy(&m_sendBuffer2[IPV4_SRC_PORT_OFFSET], &port, sizeof(port)); + + //make sure the FIN flag is not set, otherwise we will get a NAT miss + memcpy(&m_sendBuffer2[IPV4_TCP_FLAGS_OFFSET], &flags, sizeof(flags)); + + return true; + }// ModifyPacktes () + + virtual bool SendPackets() + { + bool isSuccess = false; + + // Send first packet + LOG_MSG_DEBUG("sending first packet\n"); + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) + { + LOG_MSG_ERROR("SendData failure.\n"); + return false; + } + + // Send second packet + LOG_MSG_DEBUG("sending second packet\n"); + isSuccess = m_producer.SendData(m_sendBuffer2, m_sendSize2); + if (false == isSuccess) + { + LOG_MSG_ERROR("SendData failure.\n"); + return false; + } + + LOG_MSG_DEBUG("sent successfully two packets\n"); + return true; + } + + virtual bool ReceivePacketsAndCompare() + { + size_t receivedSize = 0; + size_t receivedSize2 = 0; + bool isSuccess = true; + + // Receive results + Byte *rxBuff1 = new Byte[0x400]; + Byte *rxBuff2 = new Byte[0x400]; + + if (rxBuff1 == NULL) + { + LOG_MSG_ERROR("Memory allocation error.\n"); + if (rxBuff2) + delete[] rxBuff2; + return false; + } + + if (rxBuff2 == NULL) + { + LOG_MSG_ERROR("Memory allocation error.\n"); + delete[] rxBuff1; + return false; + } + + receivedSize = m_consumer.ReceiveData(rxBuff1, 0x400); + LOG_MSG_DEBUG("Received %zu bytes on %s.\n", receivedSize, m_consumer.m_fromChannelName.c_str()); + + receivedSize2 = m_consumer2.ReceiveData(rxBuff2, 0x400); + LOG_MSG_DEBUG("Received %zu bytes on %s.\n", receivedSize2, m_consumer2.m_fromChannelName.c_str()); + + // Compare results + if (!CompareResultVsGoldenNat( + m_sendBuffer, m_sendSize, + rxBuff1, receivedSize, + m_private_ip, m_public_ip, + m_private_port, m_public_port, + true)) + { + LOG_MSG_ERROR("Comparison of Buffer0 Failed!\n"); + isSuccess = false; + } + + char recievedBuffer[256] = { 0 }; + char SentBuffer[256] = { 0 }; + char recievedBuffer2[256] = { 0 }; + char SentBuffer2[256] = { 0 }; + size_t j; + + for (j = 0; j < m_sendSize; j++) + snprintf(&SentBuffer[3 * j], sizeof(SentBuffer) - (3 * j + 1), " %02X", m_sendBuffer[j]); + for (j = 0; j < receivedSize; j++) + snprintf(&recievedBuffer[3 * j], sizeof(recievedBuffer) - (3 * j + 1), " %02X", rxBuff1[j]); + LOG_MSG_STACK("sent Value1 (%zu)\n%s\n, Received Value1(%zu)\n%s\n", m_sendSize, SentBuffer, receivedSize, recievedBuffer); + + delete[] rxBuff1; + + isSuccess &= CompareResultVsGoldenNat( + m_sendBuffer2, m_sendSize2, + rxBuff2, receivedSize2, + m_private_ip2, m_public_ip2, + m_private_port2, m_public_port2, + true); + + for (j = 0; j < m_sendSize2; j++) + snprintf(&SentBuffer2[3 * j], sizeof(SentBuffer2) - (3 * j + 1), " %02X", m_sendBuffer2[j]); + for (j = 0; j < receivedSize2; j++) + snprintf(&recievedBuffer2[3 * j], sizeof(recievedBuffer2) - (3 * j + 1), " %02X", rxBuff2[j]); + LOG_MSG_STACK("sent Value2 (%zu)\n%s\n, Received Value2(%zu)\n%s\n", m_sendSize2, SentBuffer2, receivedSize2, recievedBuffer2); + + delete[] rxBuff2; + + return isSuccess; + } +}; + +/*---------------------------------------------------------------------------*/ +/* Test004: Multi PDN dst NAT test */ +/* NOTE: other classes are derived from this class - change carefully */ +/*---------------------------------------------------------------------------*/ +class IpaNatBlockTest004 : public IpaNatBlockTestFixture +{ +public: + IpaNatBlockTest004() + { + m_name = "IpaNatBlockTest004"; + m_description = + "NAT block test 004 - Multi PDN dst NAT test\ + 1. Generate and commit three routing tables (two are used). \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit two filtering rule: (DST & Mask Match). \ + - action go to dst NAT \ + All DST_IP == (192.23.22.1 & 0.255.255.255)traffic goes to NAT block \ + All DST_IP == (195.23.22.1 & 0.255.255.255)traffic goes to NAT block \ + 3. generate and commit two NAT rules:\ + private ip 194.23.22.1 --> public ip 192.23.22.1 \ + private ip 197.23.22.1 --> public ip 195.23.22.1"; + m_private_ip = 0xC2171601; /* 194.23.22.1 */ + m_private_port = 5678; + m_private_ip2 = 0xC5171601; /* 197.23.22.1 */ + m_private_port2 = 5679; + m_public_ip = 0xC0171601; /* "192.23.22.1" */ + m_public_port = 9050; + m_public_ip2 = 0xC3171601; /* "195.23.22.1" */ + m_public_port2 = 9051; + m_target_ip = 0xC1171601; /* 193.23.22.1 */ + m_target_port = 1234; + m_minIPAHwType = IPA_HW_v4_0; + Register(*this); + } + + + virtual bool AddRules() + { + LOG_MSG_DEBUG("Entering\n"); + + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + struct ipa_ioc_get_rt_tbl routing_table0, routing_table1; + + if (!CreateThreeIPv4BypassRoutingTables(bypass0, bypass1, bypass2)) + { + LOG_MSG_ERROR("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + + LOG_MSG_DEBUG("CreateThreeBypassRoutingTables completed successfully\n"); + routing_table0.ip = IPA_IP_v4; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + LOG_MSG_ERROR("m_routing.GetRoutingTable(&routing_table0=0x%p) Failed.\n", &routing_table0); + return false; + } + LOG_MSG_DEBUG("%s route table handle = %u\n", bypass0, routing_table0.hdl); + + routing_table1.ip = IPA_IP_v4; + strlcpy(routing_table1.name, bypass1, sizeof(routing_table1.name)); + if (!m_routing.GetRoutingTable(&routing_table1)) + { + LOG_MSG_ERROR("m_routing.GetRoutingTable(&routing_table1=0x%p) Failed.\n", &routing_table1); + return false; + } + LOG_MSG_DEBUG("%s route table handle = %u\n", bypass1, routing_table1.hdl); + + IPAFilteringTable FilterTable0; + struct ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v4, IPA_CLIENT_TEST_PROD, false, 2); + LOG_MSG_DEBUG("FilterTable*.Init Completed Successfully..\n"); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1, flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl = -1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action = IPA_PASS_TO_DST_NAT; + flt_rule_entry.rule.rt_tbl_hdl = routing_table0.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + flt_rule_entry.rule.attrib.u.v4.dst_addr_mask = 0xFFFFFFFF; // Mask + flt_rule_entry.rule.attrib.u.v4.dst_addr = m_public_ip; // Filter DST_IP == 192.23.22.1 + flt_rule_entry.rule.pdn_idx = 0; + flt_rule_entry.rule.set_metadata = 0; + if ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) + { + LOG_MSG_ERROR("Error Adding Rule to Filter Table, aborting...\n"); + return false; + } + + // Configuring Filtering Rule No.1 + flt_rule_entry.rule.rt_tbl_hdl = routing_table1.hdl; //put here the handle corresponding to Routing Rule 2 + flt_rule_entry.rule.attrib.u.v4.dst_addr = m_public_ip2; // Filter DST_IP == 195.23.22.1 + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + LOG_MSG_ERROR("Error Adding Rule to Filter Table, aborting...\n"); + return false; + } + else + { + LOG_MSG_DEBUG("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl, FilterTable0.ReadRuleFromTable(0)->status); + LOG_MSG_DEBUG("flt rule hdl1=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(1)->flt_rule_hdl, FilterTable0.ReadRuleFromTable(1)->status); + } + + //NAT table and rules creation + int total_entries = 20; + int ret; + ipa_nat_ipv4_rule ipv4_rule; + uint32_t pub_ip_add = m_public_ip; + ipa_nat_pdn_entry pdn_info; + + // first create the NAT table + ret = ipa_nat_add_ipv4_tbl(pub_ip_add, m_mem_type, total_entries, &m_tbl_hdl); + if (ret) { + LOG_MSG_ERROR("Leaving, failed creating NAT table\n"); + return false; + } + + LOG_MSG_DEBUG("nat table added, hdl %d, public ip 0x%X\n", m_tbl_hdl, + pub_ip_add); + + // modify the PDN entries that will be pointed by the NAT rules + pdn_info.public_ip = m_public_ip; + pdn_info.src_metadata = 0; + pdn_info.dst_metadata = 0; + ret = ipa_nat_modify_pdn(m_tbl_hdl, 0,&pdn_info); + if (ret) { + LOG_MSG_ERROR("Leaving, failed Modifying PDN entry 0 \n"); + return false; + } + + pdn_info.public_ip = m_public_ip2; + pdn_info.src_metadata = 0; + pdn_info.dst_metadata = 0; + ret = ipa_nat_modify_pdn(m_tbl_hdl, 1, &pdn_info); + if (ret) { + LOG_MSG_ERROR("Leaving, failed Modifying PDN entry 1 \n"); + return false; + } + + ipv4_rule.target_ip = m_target_ip; + ipv4_rule.target_port = m_target_port; + ipv4_rule.private_ip = m_private_ip; + ipv4_rule.private_port = m_private_port; + ipv4_rule.protocol = IPPROTO_TCP; + ipv4_rule.public_port = m_public_port; + ipv4_rule.pdn_index = 0; + + ret = ipa_nat_add_ipv4_rule(m_tbl_hdl, &ipv4_rule, &m_nat_rule_hdl1); + if (ret) { + LOG_MSG_ERROR("Leaving, failed adding NAT rule 0\n"); + return false; + } + + LOG_MSG_DEBUG("NAT rule added, hdl %d, data: 0x%X, %d, 0x%X, %d, %d, %d\n", + m_nat_rule_hdl1, ipv4_rule.target_ip, ipv4_rule.target_port, + ipv4_rule.private_ip, ipv4_rule.private_port, + ipv4_rule.protocol, ipv4_rule.public_port); + + ipv4_rule.private_ip = m_private_ip2; + ipv4_rule.private_port = m_private_port2; + ipv4_rule.public_port = m_public_port2; + ipv4_rule.pdn_index = 1; + + ret = ipa_nat_add_ipv4_rule(m_tbl_hdl, &ipv4_rule, &m_nat_rule_hdl1); + if (ret) { + LOG_MSG_ERROR("Leaving, failed adding NAT rule 0\n"); + return false; + } + + LOG_MSG_DEBUG("NAT rule 2 added, hdl %d, data: 0x%X, %d, 0x%X, %d, %d, %d\n", + m_nat_rule_hdl1, ipv4_rule.target_ip, ipv4_rule.target_port, + ipv4_rule.private_ip, ipv4_rule.private_port, + ipv4_rule.protocol, ipv4_rule.public_port); + + LOG_MSG_DEBUG("Leaving\n"); + return true; + }// AddRules() + + virtual bool ModifyPackets() + { + uint32_t address; + uint16_t port; + char flags = 0x18; + + //first packet private ip public ip 192.23.22.1 --> 194.23.22.1 + address = htonl(m_public_ip);//192.23.22.1 + memcpy(&m_sendBuffer[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + port = htons(m_public_port); + memcpy(&m_sendBuffer[IPV4_DST_PORT_OFFSET], &port, sizeof(port)); + + address = htonl(m_target_ip);/* 194.23.22.1 */ + memcpy(&m_sendBuffer[IPV4_SRC_ADDR_OFFSET], &address, sizeof(address)); + port = htons(m_target_port); + memcpy(&m_sendBuffer[IPV4_SRC_PORT_OFFSET], &port, sizeof(port)); + + //make sure the FIN flag is not set, otherwise we will get a NAT miss + memcpy(&m_sendBuffer[IPV4_TCP_FLAGS_OFFSET], &flags, sizeof(flags)); + + // second packet public ip 195.23.22.1--> private ip 197.23.22.1 + address = htonl(m_public_ip2);//193.23.22.1 + memcpy(&m_sendBuffer2[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + port = htons(m_public_port2); + memcpy(&m_sendBuffer2[IPV4_DST_PORT_OFFSET], &port, sizeof(port)); + + address = htonl(m_target_ip);/* 197.23.22.1 */ + memcpy(&m_sendBuffer2[IPV4_SRC_ADDR_OFFSET], &address, sizeof(address)); + port = htons(m_target_port); + memcpy(&m_sendBuffer2[IPV4_SRC_PORT_OFFSET], &port, sizeof(port)); + + //make sure the FIN flag is not set, otherwise we will get a NAT miss + memcpy(&m_sendBuffer2[IPV4_TCP_FLAGS_OFFSET], &flags, sizeof(flags)); + + return true; + }// ModifyPacktes () + + virtual bool SendPackets() + { + bool isSuccess = false; + + // Send first packet + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) + { + LOG_MSG_ERROR("SendData failure.\n"); + return false; + } + + // Send second packet + isSuccess = m_producer.SendData(m_sendBuffer2, m_sendSize2); + if (false == isSuccess) + { + LOG_MSG_ERROR("SendData failure.\n"); + return false; + } + + LOG_MSG_DEBUG("sent successfully two packets\n"); + return true; + } + + virtual bool ReceivePacketsAndCompare() + { + size_t receivedSize = 0; + size_t receivedSize2 = 0; + bool isSuccess = true; + + // Receive results + Byte *rxBuff1 = new Byte[0x400]; + Byte *rxBuff2 = new Byte[0x400]; + + if (rxBuff1 == NULL) + { + LOG_MSG_ERROR("Memory allocation error.\n"); + if (rxBuff2) + delete[] rxBuff2; + return false; + } + + if (rxBuff2 == NULL) + { + LOG_MSG_ERROR("Memory allocation error.\n"); + delete[] rxBuff1; + return false; + } + + receivedSize = m_consumer.ReceiveData(rxBuff1, 0x400); + LOG_MSG_DEBUG("Received %zu bytes on %s.\n", receivedSize, m_consumer.m_fromChannelName.c_str()); + + receivedSize2 = m_consumer2.ReceiveData(rxBuff2, 0x400); + LOG_MSG_DEBUG("Received %zu bytes on %s.\n", receivedSize2, m_consumer2.m_fromChannelName.c_str()); + + // Compare results + if (!CompareResultVsGoldenNat( + m_sendBuffer, m_sendSize, + rxBuff1, receivedSize, + m_private_ip, m_public_ip, + m_private_port, m_public_port, + false)) + { + LOG_MSG_ERROR("Comparison of Buffer0 Failed!\n"); + isSuccess = false; + } + + char recievedBuffer[256] = { 0 }; + char SentBuffer[256] = { 0 }; + char recievedBuffer2[256] = { 0 }; + char SentBuffer2[256] = { 0 }; + size_t j; + + for (j = 0; j < m_sendSize; j++) + snprintf(&SentBuffer[3 * j], sizeof(SentBuffer) - (3 * j + 1), " %02X", m_sendBuffer[j]); + for (j = 0; j < receivedSize; j++) + snprintf(&recievedBuffer[3 * j], sizeof(recievedBuffer) - (3 * j + 1), " %02X", rxBuff1[j]); + LOG_MSG_STACK("sent Value1 (%zu)\n%s\n, Received Value1(%zu)\n%s\n", m_sendSize, SentBuffer, receivedSize, recievedBuffer); + + delete[] rxBuff1; + + isSuccess &= CompareResultVsGoldenNat( + m_sendBuffer2, m_sendSize2, + rxBuff2, receivedSize2, + m_private_ip2, m_public_ip2, + m_private_port2, m_public_port2, + false); + + for (j = 0; j < m_sendSize2; j++) + snprintf(&SentBuffer2[3 * j], sizeof(SentBuffer2) - (3 * j + 1), " %02X", m_sendBuffer2[j]); + for (j = 0; j < receivedSize2; j++) + snprintf(&recievedBuffer2[3 * j], sizeof(recievedBuffer2) - (3 * j + 1), " %02X", rxBuff2[j]); + LOG_MSG_STACK("sent Value1 (%zu)\n%s\n, Received Value1(%zu)\n%s\n", m_sendSize2, SentBuffer2, receivedSize2, recievedBuffer2); + + delete[] rxBuff2; + + return isSuccess; + } +}; + +/*---------------------------------------------------------------------------*/ +/* Test005: Single PDN src metadata replacement NAT test */ +/*---------------------------------------------------------------------------*/ +class IpaNatBlockTest005 : public IpaNatBlockTestFixture +{ +public: + IpaNatBlockTest005() + { + m_name = "IpaNatBlockTest005"; + m_description = + "NAT block test 005 - single PDN src metadata replacement NAT test\ + source metadata will be replaced and the routing rule equation will be done upon replaced value\ + 1. Generate and commit two routing tables (only one is used). \ + the routing table will catch packets with metadata value 0x34567890 (different from original value)\ + 2. Generate and commit one filtering rule: (DST & Mask Match). \ + action go to src NAT \ + All DST_IP == (193.23.22.1 & 0.255.255.255)traffic goes to NAT block \ + action parameters metadata replacement = true\ + 3. generate and commit one NAT rule:\ + private ip 194.23.22.1 --> public ip 192.23.22.1\ + source metadata value shall be replaced to 0x34567890 (caught by the routing rule)"; + m_private_ip = 0xC2171601; /* 194.23.22.1 */ + m_private_port = 5678; + m_public_ip = 0xC0171601; /* "192.23.22.1" */ + m_public_port = 9050; + m_target_ip = 0xC1171601; /* 193.23.22.1 */ + m_target_port = 1234; + m_metadata = 0x34567890; + m_minIPAHwType = IPA_HW_v4_0; + Register(*this); + } + + + virtual bool AddRules() + { + LOG_MSG_DEBUG("Entering\n"); + + const char bypass0[20] = "Bypass0"; + struct ipa_ioc_get_rt_tbl routing_table0; + + if (!CreateMetdataRoutingRule(bypass0)) + { + LOG_MSG_ERROR("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + + LOG_MSG_DEBUG("CreateMetdataRoutingRule completed successfully\n"); + routing_table0.ip = IPA_IP_v4; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + LOG_MSG_ERROR("m_routing.GetRoutingTable(&routing_table0=0x%p) Failed.\n", &routing_table0); + return false; + } + LOG_MSG_DEBUG("%s route table handle = %u\n", bypass0, routing_table0.hdl); + + IPAFilteringTable FilterTable0; + struct ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v4, IPA_CLIENT_TEST2_PROD, false, 1); + LOG_MSG_DEBUG("FilterTable*.Init Completed Successfully..\n"); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1, flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl = -1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action = IPA_PASS_TO_SRC_NAT; + flt_rule_entry.rule.rt_tbl_hdl = routing_table0.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + flt_rule_entry.rule.attrib.u.v4.dst_addr_mask = 0xFFFFFFFF; // Mask + flt_rule_entry.rule.attrib.u.v4.dst_addr = m_target_ip; // Filter DST_IP == 193.23.22.1 + flt_rule_entry.rule.pdn_idx = 0; + flt_rule_entry.rule.set_metadata = 1; + flt_rule_entry.rule.retain_hdr = 1; + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + LOG_MSG_ERROR("Error Adding Rule to Filter Table, aborting...\n"); + return false; + } + else + { + LOG_MSG_DEBUG("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl, FilterTable0.ReadRuleFromTable(0)->status); + } + + //NAT table and rules creation + int total_entries = 20; + int ret; + ipa_nat_ipv4_rule ipv4_rule; + ipa_nat_pdn_entry pdn_info; + + ret = ipa_nat_add_ipv4_tbl(m_public_ip, m_mem_type, total_entries, &m_tbl_hdl); + if (ret) { + LOG_MSG_ERROR("Leaving, failed creating NAT table\n"); + return false; + } + LOG_MSG_DEBUG("nat table added, hdl %d, public ip 0x%X\n", m_tbl_hdl, + m_public_ip); + + ipv4_rule.target_ip = m_target_ip; + ipv4_rule.target_port = m_target_port; + ipv4_rule.private_ip = m_private_ip; + ipv4_rule.private_port = m_private_port; + ipv4_rule.protocol = IPPROTO_TCP; + ipv4_rule.public_port = m_public_port; + ipv4_rule.pdn_index = 0; + + // modify the PDN entries that will be pointed by the NAT rules + pdn_info.public_ip = m_public_ip; + pdn_info.src_metadata = m_metadata; + pdn_info.dst_metadata = 0; + ret = ipa_nat_modify_pdn(m_tbl_hdl, 0, &pdn_info); + if (ret) { + LOG_MSG_ERROR("Leaving, failed modifying PDN index 0\n"); + return false; + } + LOG_MSG_DEBUG("PDN 0 was modified to hold ip 0x%X, src_metadata 0x%X\n", m_public_ip, m_metadata); + + ret = ipa_nat_add_ipv4_rule(m_tbl_hdl, &ipv4_rule, &m_nat_rule_hdl1); + if (ret) { + LOG_MSG_ERROR("Leaving, failed adding NAT rule 0\n"); + return false; + } + LOG_MSG_DEBUG("NAT rule added, hdl %d, data: 0x%X, %d, 0x%X, %d, %d, %d\n", + m_nat_rule_hdl1, ipv4_rule.target_ip, ipv4_rule.target_port, + ipv4_rule.private_ip, ipv4_rule.private_port, + ipv4_rule.protocol, ipv4_rule.public_port); + + LOG_MSG_DEBUG("Leaving\n"); + return true; + }// AddRules() + + virtual bool ModifyPackets() + { + uint32_t address; + uint16_t port; + char flags = 0x18; + + Load8021QPacket(); + + address = htonl(m_target_ip);//193.23.22.1 + memcpy(&m_sendBuffer[IPV4_DST_ADDR_OFFSET + ETH8021Q_HEADER_LEN], &address, sizeof(address)); + port = htons(m_target_port); + memcpy(&m_sendBuffer[IPV4_DST_PORT_OFFSET + ETH8021Q_HEADER_LEN], &port, sizeof(port)); + + address = htonl(m_private_ip);/* 194.23.22.1 */ + memcpy(&m_sendBuffer[IPV4_SRC_ADDR_OFFSET + ETH8021Q_HEADER_LEN], &address, sizeof(address)); + port = htons(m_private_port); + memcpy(&m_sendBuffer[IPV4_SRC_PORT_OFFSET + ETH8021Q_HEADER_LEN], &port, sizeof(port)); + + //make sure the FIN flag is not set, otherwise we will get a NAT miss + memcpy(&m_sendBuffer[IPV4_TCP_FLAGS_OFFSET + ETH8021Q_HEADER_LEN], &flags, sizeof(flags)); + return true; + }// ModifyPacktes () + + virtual bool SendPackets() + { + bool isSuccess = false; + + // Send first packet + isSuccess = m_producer2.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) + { + LOG_MSG_ERROR("SendData failure.\n"); + return false; + } + + LOG_MSG_DEBUG("sent successfully one packet\n"); + return true; + } + + virtual bool ReceivePacketsAndCompare() + { + size_t receivedSize = 0; + bool isSuccess = true; + + // Receive results + Byte *rxBuff1 = new Byte[0x400]; + + if (NULL == rxBuff1) + { + LOG_MSG_ERROR("Memory allocation error.\n"); + return false; + } + + receivedSize = m_consumer.ReceiveData(rxBuff1, 0x400); + LOG_MSG_DEBUG("Received %zu bytes on %s.\n", receivedSize, m_consumer.m_fromChannelName.c_str()); + + // Compare results + if (!CompareResultVsGoldenNat( + m_sendBuffer, m_sendSize, + rxBuff1, receivedSize, + m_private_ip, m_public_ip, + m_private_port, m_public_port, + true, ETH8021Q_HEADER_LEN)) + { + LOG_MSG_ERROR("Comparison of Buffer0 Failed!\n"); + isSuccess = false; + } + + char recievedBuffer[256] = { 0 }; + char SentBuffer[256] = { 0 }; + size_t j; + + for (j = 0; j < m_sendSize; j++) + snprintf(&SentBuffer[3 * j], sizeof(SentBuffer) - (3 * j + 1), " %02X", m_sendBuffer[j]); + for (j = 0; j < receivedSize; j++) + snprintf(&recievedBuffer[3 * j], sizeof(recievedBuffer) - (3 * j + 1), " %02X", rxBuff1[j]); + LOG_MSG_STACK("sent Value1 (%zu)\n%s\n, Received Value1(%zu)\n%s\n", m_sendSize, SentBuffer, receivedSize, recievedBuffer); + + delete[] rxBuff1; + + return isSuccess; + } +}; + +/*---------------------------------------------------------------------------*/ +/* Test006: Single PDN dst metadata replacement NAT test */ +/*---------------------------------------------------------------------------*/ +class IpaNatBlockTest006 : public IpaNatBlockTestFixture +{ +public: + IpaNatBlockTest006() + { + m_name = "IpaNatBlockTest006"; + m_description = + "NAT block test 006 - single PDN dst metadata replacement NAT test\ + destination metadata will be replaced and the routing rule equation will be done upon replaced value\ + 1. Generate and commit two routing tables (only one is used). \ + the routing table will catch packets with metadata value 0x34567890 (different from original value)\ + 2. Generate and commit one filtering rule: (DST & Mask Match). \ + action go to dst NAT \ + All DST_IP == (192.23.22.1 & 0.255.255.255)traffic goes to NAT block \ + action parameters metadata replacement = true\ + 3. generate and commit one NAT rule:\ + public ip 192.23.22.1 --> private ip 194.23.22.1 \ + destination metadata value shall be replaced to 0x34567890 (caught by the routing rule)"; + m_private_ip = 0xC2171601; /* 194.23.22.1 */ + m_private_port = 5678; + m_public_ip = 0xC0171601; /* "192.23.22.1" */ + m_public_port = 9050; + m_target_ip = 0xC1171601; /* 193.23.22.1 */ + m_target_port = 1234; + m_metadata = 0x34567890; + m_minIPAHwType = IPA_HW_v4_0; + Register(*this); + } + + + virtual bool AddRules() + { + LOG_MSG_DEBUG("Entering\n"); + + const char bypass0[20] = "Bypass0"; + struct ipa_ioc_get_rt_tbl routing_table0; + + if (!CreateMetdataRoutingRule(bypass0)) + { + LOG_MSG_ERROR("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + + LOG_MSG_DEBUG("CreateMetdataRoutingRule completed successfully\n"); + routing_table0.ip = IPA_IP_v4; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + LOG_MSG_ERROR("m_routing.GetRoutingTable(&routing_table0=0x%p) Failed.\n", &routing_table0); + return false; + } + LOG_MSG_DEBUG("%s route table handle = %u\n", bypass0, routing_table0.hdl); + + IPAFilteringTable FilterTable0; + struct ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v4, IPA_CLIENT_TEST2_PROD, false, 1); + LOG_MSG_DEBUG("FilterTable*.Init Completed Successfully..\n"); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1, flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl = -1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action = IPA_PASS_TO_DST_NAT; + flt_rule_entry.rule.rt_tbl_hdl = routing_table0.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + flt_rule_entry.rule.attrib.u.v4.dst_addr_mask = 0xFFFFFFFF; // Mask + flt_rule_entry.rule.attrib.u.v4.dst_addr = m_public_ip; // Filter DST_IP == 193.23.22.1 + flt_rule_entry.rule.pdn_idx = 0; + flt_rule_entry.rule.set_metadata = 1; + flt_rule_entry.rule.retain_hdr = 1; + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + LOG_MSG_ERROR("Error Adding Rule to Filter Table, aborting...\n"); + return false; + } + else + { + LOG_MSG_DEBUG("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl, FilterTable0.ReadRuleFromTable(0)->status); + } + + //NAT table and rules creation + int total_entries = 20; + int ret; + ipa_nat_ipv4_rule ipv4_rule; + ipa_nat_pdn_entry pdn_info; + + ret = ipa_nat_add_ipv4_tbl(m_public_ip, m_mem_type, total_entries, &m_tbl_hdl); + if (ret) { + LOG_MSG_ERROR("Leaving, failed creating NAT table\n"); + return false; + } + LOG_MSG_DEBUG("nat table added, hdl %d, public ip 0x%X\n", m_tbl_hdl, + m_public_ip); + + ipv4_rule.target_ip = m_target_ip; + ipv4_rule.target_port = m_target_port; + ipv4_rule.private_ip = m_private_ip; + ipv4_rule.private_port = m_private_port; + ipv4_rule.protocol = IPPROTO_TCP; + ipv4_rule.public_port = m_public_port; + ipv4_rule.pdn_index = 0; + + // modify the PDN entries that will be pointed by the NAT rules + pdn_info.public_ip = m_public_ip; + pdn_info.src_metadata = 0; + pdn_info.dst_metadata = m_metadata; + ret = ipa_nat_modify_pdn(m_tbl_hdl, 0, &pdn_info); + if (ret) { + LOG_MSG_ERROR("Leaving, failed modifying PDN index 0\n"); + return false; + } + LOG_MSG_DEBUG("PDN 0 was modified to hold ip 0x%X, dst_metadata 0x%X\n", m_public_ip, m_metadata); + + ret = ipa_nat_add_ipv4_rule(m_tbl_hdl, &ipv4_rule, &m_nat_rule_hdl1); + if (ret) { + LOG_MSG_ERROR("Leaving, failed adding NAT rule 0\n"); + return false; + } + LOG_MSG_ERROR("NAT rule added, hdl %d, data: 0x%X, %d, 0x%X, %d, %d, %d\n", + m_nat_rule_hdl1, ipv4_rule.target_ip, ipv4_rule.target_port, + ipv4_rule.private_ip, ipv4_rule.private_port, + ipv4_rule.protocol, ipv4_rule.public_port); + + LOG_MSG_DEBUG("Leaving\n"); + return true; + }// AddRules() + + virtual bool ModifyPackets() + { + uint32_t address; + uint16_t port; + char flags = 0x18; + + Load8021QPacket(); + + address = htonl(m_public_ip);//193.23.22.1 + memcpy(&m_sendBuffer[IPV4_DST_ADDR_OFFSET + ETH8021Q_HEADER_LEN], &address, sizeof(address)); + port = htons(m_public_port); + memcpy(&m_sendBuffer[IPV4_DST_PORT_OFFSET + ETH8021Q_HEADER_LEN], &port, sizeof(port)); + + address = htonl(m_target_ip);/* 194.23.22.1 */ + memcpy(&m_sendBuffer[IPV4_SRC_ADDR_OFFSET + ETH8021Q_HEADER_LEN], &address, sizeof(address)); + port = htons(m_target_port); + memcpy(&m_sendBuffer[IPV4_SRC_PORT_OFFSET + ETH8021Q_HEADER_LEN], &port, sizeof(port)); + + //make sure the FIN flag is not set, otherwise we will get a NAT miss + memcpy(&m_sendBuffer[IPV4_TCP_FLAGS_OFFSET + ETH8021Q_HEADER_LEN], &flags, sizeof(flags)); + return true; + }// ModifyPacktes () + + virtual bool SendPackets() + { + bool isSuccess = false; + + // Send first packet + isSuccess = m_producer2.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) + { + LOG_MSG_ERROR("SendData failure.\n"); + return false; + } + + LOG_MSG_DEBUG("sent successfully one packet\n"); + return true; + } + + virtual bool ReceivePacketsAndCompare() + { + size_t receivedSize = 0; + bool isSuccess = true; + + // Receive results + Byte *rxBuff1 = new Byte[0x400]; + + if (NULL == rxBuff1) + { + LOG_MSG_ERROR("Memory allocation error.\n"); + return false; + } + + receivedSize = m_consumer.ReceiveData(rxBuff1, 0x400); + LOG_MSG_DEBUG("Received %zu bytes on %s.\n", receivedSize, m_consumer.m_fromChannelName.c_str()); + + // Compare results + if (!CompareResultVsGoldenNat( + m_sendBuffer, m_sendSize, + rxBuff1, receivedSize, + m_private_ip, m_public_ip, + m_private_port, m_public_port, + false, ETH8021Q_HEADER_LEN)) + { + LOG_MSG_ERROR("Comparison of Buffer0 Failed!\n"); + isSuccess = false; + } + + char recievedBuffer[256] = { 0 }; + char SentBuffer[256] = { 0 }; + size_t j; + + for (j = 0; j < m_sendSize; j++) + snprintf(&SentBuffer[3 * j], sizeof(SentBuffer) - (3 * j + 1), " %02X", m_sendBuffer[j]); + for (j = 0; j < receivedSize; j++) + snprintf(&recievedBuffer[3 * j], sizeof(recievedBuffer) - (3 * j + 1), " %02X", rxBuff1[j]); + LOG_MSG_STACK("sent Value1 (%zu)\n%s\n, Received Value1(%zu)\n%s\n", m_sendSize, SentBuffer, receivedSize, recievedBuffer); + + delete[] rxBuff1; + + return isSuccess; + } +}; + +/*---------------------------------------------------------------------------*/ +/* Test007: Hashable routing rule with dst NAT test */ +/*---------------------------------------------------------------------------*/ +class IpaNatBlockTest007 : public IpaNatBlockTestFixture +{ +public: + IpaNatBlockTest007() + { + m_name = "IpaNatBlockTest007"; + m_description = + "NAT block test 007 - single PDN dst NAT with hashable routing rule test\ + test if routing block hash mechanism tests NATed values or pre NAT values\ + 1. Generate and commit routing table with two hashable rules. \ + first routing rule will send packets with ip == 192.168.9.119 to first pipe \ + second routing rule will send packets with ip == 192.168.9.120 to second pipe\ + 2. Generate and commit one filtering rule: (DST & Mask Match). \ + action go to dst NAT \ + All DST_IP == (192.168.9.1 & 255.255.255.0)traffic goes to NAT block \ + 3. generate and commit two NAT rules with target ip 211.1.1.4:\ + 1. public ip 5.5.6.120 --> private ip 192.168.9.119 \ + public port 4501 --> private port 4500 \ + 2. public ip 5.5.6.120 --> private ip 192.168.9.119 \ + public port 4502 --> private port 4500"; + m_private_ip = 0xC0A80977; /* 192.168.9.119 */ + m_private_port = 4500; + m_private_ip2 = 0xC0A80978; /* 192.168.9.120 */ + m_private_port2 = 4500; + m_public_ip = 0x05050678; /* 5.5.6.120 */ + m_public_port = 4501; + m_public_port2 = 4502; + m_target_ip = 0xD3010104; /* 211.1.1.4 */ + m_target_port = 1234; + m_minIPAHwType = IPA_HW_v4_0; + Register(*this); + } + + bool Setup() + { + return IpaNatBlockTestFixture::Setup(true); + } + + + virtual bool AddRules() + { + LOG_MSG_DEBUG("Entering\n"); + + const char bypass0[20] = "Bypass0"; + struct ipa_ioc_get_rt_tbl routing_table0; + + if (!CreateHashableRoutingRules(bypass0)) + { + LOG_MSG_ERROR("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + + LOG_MSG_DEBUG("CreateHashableRoutingRules completed successfully\n"); + routing_table0.ip = IPA_IP_v4; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + LOG_MSG_ERROR("m_routing.GetRoutingTable(&routing_table0=0x%p) Failed.\n", &routing_table0); + return false; + } + LOG_MSG_DEBUG("%s route table handle = %u\n", bypass0, routing_table0.hdl); + + IPAFilteringTable FilterTable0; + struct ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v4, IPA_CLIENT_TEST_PROD, false, 1); + LOG_MSG_DEBUG("FilterTable*.Init Completed Successfully..\n"); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1, flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl = -1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action = IPA_PASS_TO_DST_NAT; + flt_rule_entry.rule.rt_tbl_hdl = routing_table0.hdl; //put here the handle corresponding to Routing table 1 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + flt_rule_entry.rule.attrib.u.v4.dst_addr_mask = 0x00000000; // Mask - catch all + flt_rule_entry.rule.attrib.u.v4.dst_addr = m_public_ip; // Filter DST_IP == 5.5.6.120 + flt_rule_entry.rule.pdn_idx = 0; + flt_rule_entry.rule.set_metadata = 0; + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + LOG_MSG_ERROR("Error Adding Rule to Filter Table, aborting...\n"); + return false; + } + else + { + LOG_MSG_DEBUG("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl, FilterTable0.ReadRuleFromTable(0)->status); + } + + //NAT table and rules creation + int total_entries = 20; + int ret; + ipa_nat_ipv4_rule ipv4_rule; + + ret = ipa_nat_add_ipv4_tbl(m_public_ip, m_mem_type, total_entries, &m_tbl_hdl); + if (ret) { + LOG_MSG_ERROR("Leaving, failed creating NAT table\n"); + return false; + } + LOG_MSG_DEBUG("nat table added, hdl %d, public ip 0x%X\n", m_tbl_hdl, + m_public_ip); + + ipv4_rule.target_ip = m_target_ip; + ipv4_rule.target_port = m_target_port; + ipv4_rule.private_ip = m_private_ip; + ipv4_rule.private_port = m_private_port; + ipv4_rule.protocol = IPPROTO_TCP; + ipv4_rule.public_port = m_public_port; + ipv4_rule.pdn_index = 0; + + ret = ipa_nat_add_ipv4_rule(m_tbl_hdl, &ipv4_rule, &m_nat_rule_hdl1); + if (ret) { + LOG_MSG_ERROR("Leaving, failed adding NAT rule 0\n"); + return false; + } + LOG_MSG_DEBUG("NAT rule 1 added, hdl %d, data: 0x%X, %d, 0x%X, %d, %d, %d\n", + m_nat_rule_hdl1, ipv4_rule.target_ip, ipv4_rule.target_port, + ipv4_rule.private_ip, ipv4_rule.private_port, + ipv4_rule.protocol, ipv4_rule.public_port); + + ipv4_rule.target_ip = m_target_ip; + ipv4_rule.target_port = m_target_port; + ipv4_rule.private_ip = m_private_ip2; + ipv4_rule.private_port = m_private_port2; + ipv4_rule.protocol = IPPROTO_TCP; + ipv4_rule.public_port = m_public_port2; + ipv4_rule.pdn_index = 0; + + ret = ipa_nat_add_ipv4_rule(m_tbl_hdl, &ipv4_rule, &m_nat_rule_hdl1); + if (ret) { + LOG_MSG_ERROR("Leaving, failed adding NAT rule 0\n"); + return false; + } + LOG_MSG_DEBUG("NAT rule 2 added, hdl %d, data: 0x%X, %d, 0x%X, %d, %d, %d\n", + m_nat_rule_hdl1, ipv4_rule.target_ip, ipv4_rule.target_port, + ipv4_rule.private_ip, ipv4_rule.private_port, + ipv4_rule.protocol, ipv4_rule.public_port); + + LOG_MSG_DEBUG("Leaving\n"); + return true; + }// AddRules() + + virtual bool ModifyPackets() + { + uint32_t address; + uint16_t port; + char flags = 0x18; + + address = ntohl(m_public_ip);//5.5.6.120 + memcpy(&m_sendBuffer[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + port = ntohs(m_public_port); // 4501 + memcpy(&m_sendBuffer[IPV4_DST_PORT_OFFSET], &port, sizeof(port)); + + address = ntohl(m_target_ip);/* 211.1.1.4 */ + memcpy(&m_sendBuffer[IPV4_SRC_ADDR_OFFSET], &address, sizeof(address)); + port = ntohs(m_target_port); // 4500 + memcpy(&m_sendBuffer[IPV4_SRC_PORT_OFFSET], &port, sizeof(port)); + + //make sure the FIN flag is not set, otherwise we will get a NAT miss + memcpy(&m_sendBuffer[IPV4_TCP_FLAGS_OFFSET], &flags, sizeof(flags)); + + // second packet + address = ntohl(m_public_ip);//5.5.6.120 + memcpy(&m_sendBuffer2[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + port = ntohs(m_public_port2); // 4502 + memcpy(&m_sendBuffer2[IPV4_DST_PORT_OFFSET], &port, sizeof(port)); + + address = ntohl(m_target_ip);/* 211.1.1.4 */ + memcpy(&m_sendBuffer2[IPV4_SRC_ADDR_OFFSET], &address, sizeof(address)); + port = ntohs(m_target_port); // 4500 + memcpy(&m_sendBuffer2[IPV4_SRC_PORT_OFFSET], &port, sizeof(port)); + + //make sure the FIN flag is not set, otherwise we will get a NAT miss + memcpy(&m_sendBuffer2[IPV4_TCP_FLAGS_OFFSET], &flags, sizeof(flags)); + return true; + }// ModifyPacktes () + + virtual bool SendPackets() + { + bool isSuccess = false; + + // Send first packet + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) + { + LOG_MSG_ERROR("SendData failure.\n"); + return false; + } + + LOG_MSG_DEBUG("sent successfully the first packet\n"); + + isSuccess = m_producer.SendData(m_sendBuffer2, m_sendSize2); + if (false == isSuccess) + { + LOG_MSG_ERROR("SendData failure.\n"); + return false; + } + + LOG_MSG_DEBUG("sent successfully two packet\n"); + return true; + } + + virtual bool ReceivePacketsAndCompare() + { + size_t receivedSize = 0; + size_t receivedSize2 = 0; + bool isSuccess = true; + + // Receive results + Byte *rxBuff1 = new Byte[0x400]; + Byte *rxBuff2 = new Byte[0x400]; + + if (rxBuff1 == NULL || rxBuff2 == NULL) + { + LOG_MSG_ERROR("Memory allocation error.\n"); + return false; + } + + receivedSize = m_consumer.ReceiveData(rxBuff1, 0x400); + LOG_MSG_DEBUG("Received %zu bytes on %s.\n", receivedSize, m_consumer.m_fromChannelName.c_str()); + + receivedSize2 = m_consumer2.ReceiveData(rxBuff2, 0x400); + LOG_MSG_DEBUG("Received %zu bytes on %s.\n", receivedSize2, m_consumer2.m_fromChannelName.c_str()); + + // Compare results + if (!CompareResultVsGoldenNat( + m_sendBuffer, m_sendSize, + rxBuff1, receivedSize, + m_private_ip, m_public_ip, + m_private_port, m_public_port, + false, 0, true)) + { + LOG_MSG_ERROR("Comparison of Buffer0 Failed!\n"); + isSuccess = false; + } + + isSuccess &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_0) ? + IsCacheMiss_v5_0(m_sendSize, receivedSize, rxBuff1) : IsCacheMiss(m_sendSize, receivedSize, rxBuff1); + + char recievedBuffer[0x400] = { 0 }; + char SentBuffer[0x400] = { 0 }; + char recievedBuffer2[0x400] = { 0 }; + char SentBuffer2[0x400] = { 0 }; + size_t j; + + for (j = 0; j < m_sendSize; j++) + snprintf(&SentBuffer[3 * j], sizeof(SentBuffer) - (3 * j + 1), " %02X", m_sendBuffer[j]); + for (j = 0; j < receivedSize; j++) + snprintf(&recievedBuffer[3 * j], sizeof(recievedBuffer) - (3 * j + 1), " %02X", rxBuff1[j]); + LOG_MSG_STACK("sent Value1 (%zu)\n%s\n, Received Value1(%zu)\n%s\n", m_sendSize, SentBuffer, receivedSize, recievedBuffer); + + delete[] rxBuff1; + + isSuccess &= CompareResultVsGoldenNat( + m_sendBuffer2, m_sendSize2, + rxBuff2, receivedSize2, + m_private_ip2, m_public_ip, + m_private_port2, m_public_port2, + false, 0, true); + + isSuccess &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_0) ? + IsCacheMiss_v5_0(m_sendSize2, receivedSize2, rxBuff2) : IsCacheMiss(m_sendSize2, receivedSize2, rxBuff2); + + for (j = 0; j < m_sendSize2; j++) + snprintf(&SentBuffer2[3 * j], sizeof(SentBuffer2) - (3 * j + 1), " %02X", m_sendBuffer2[j]); + for (j = 0; j < receivedSize2; j++) + snprintf(&recievedBuffer2[3 * j], sizeof(recievedBuffer2) - (3 * j + 1), " %02X", rxBuff2[j]); + LOG_MSG_STACK("sent Value1 (%zu)\n%s\n, Received Value1(%zu)\n%s\n", m_sendSize2, SentBuffer2, receivedSize2, recievedBuffer2); + + delete[] rxBuff2; + + return isSuccess; + } +}; + +/*---------------------------------------------------------------------------*/ +/* Test008: Multi PDN src NAT test match PDN by input from filtering block */ +/*---------------------------------------------------------------------------*/ +class IpaNatBlockTest008 : public IpaNatBlockTestFixture +{ +public: + IpaNatBlockTest008() + { + m_name = "IpaNatBlockTest008"; + m_description = + "NAT block test 008 - Multi PDN src NAT test match PDN by input from filtering block\ + 1. Generate and commit three routing tables (two are used). \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit one filtering rule: (DST & Mask Match). \ + - action go to src NAT + PDN index 2\ + All SRC_IP == (194.23.22.1 & 0.255.255.255)traffic goes to NAT block \ + 3. generate and commit two NAT rules:\ + private ip 194.23.22.1 --> public ip 192.23.22.1 PDN index 1\ + private ip 194.23.22.1 --> public ip 195.23.22.1 PDN index 2"; + m_private_ip = 0xC2171601; /* 194.23.22.1 */ + m_private_port = 5678; + m_public_ip = 0xC0171601; /* "192.23.22.1" */ + m_public_port = 9050; + m_public_ip2 = 0xC3171601; /* "195.23.22.1" */ + m_target_ip = 0xC1171601; /* 193.23.22.1 */ + m_target_port = 1234; + m_minIPAHwType = IPA_HW_v4_0; + Register(*this); + } + + + virtual bool AddRules() + { + LOG_MSG_DEBUG("Entering\n"); + + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + struct ipa_ioc_get_rt_tbl routing_table0, routing_table1; + + if (!CreateThreeIPv4BypassRoutingTables(bypass0, bypass1, bypass2)) + { + LOG_MSG_ERROR("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + + LOG_MSG_DEBUG("CreateThreeBypassRoutingTables completed successfully\n"); + routing_table0.ip = IPA_IP_v4; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + LOG_MSG_ERROR("m_routing.GetRoutingTable(&routing_table0=0x%p) Failed.\n", &routing_table0); + return false; + } + LOG_MSG_DEBUG("%s route table handle = %u\n", bypass0, routing_table0.hdl); + + routing_table1.ip = IPA_IP_v4; + strlcpy(routing_table1.name, bypass1, sizeof(routing_table1.name)); + if (!m_routing.GetRoutingTable(&routing_table1)) + { + LOG_MSG_ERROR("m_routing.GetRoutingTable(&routing_table1=0x%p) Failed.\n", &routing_table1); + return false; + } + LOG_MSG_DEBUG("%s route table handle = %u\n", bypass1, routing_table1.hdl); + + IPAFilteringTable FilterTable0; + struct ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v4, IPA_CLIENT_TEST_PROD, false, 2); + LOG_MSG_DEBUG("FilterTable*.Init Completed Successfully..\n"); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1, flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl = -1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action = IPA_PASS_TO_SRC_NAT; + flt_rule_entry.rule.rt_tbl_hdl = routing_table0.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_SRC_ADDR; + flt_rule_entry.rule.attrib.u.v4.src_addr_mask = 0xFFFFFFFF; // Mask + flt_rule_entry.rule.attrib.u.v4.src_addr = m_private_ip; // Filter SRC_IP == 194.23.22.1 + flt_rule_entry.rule.pdn_idx = 2; + flt_rule_entry.rule.set_metadata = 0; + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + LOG_MSG_ERROR("Error Adding Rule to Filter Table, aborting...\n"); + return false; + } + else + { + LOG_MSG_ERROR("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl, FilterTable0.ReadRuleFromTable(0)->status); + } + + //NAT table and rules creation + int total_entries = 20; + int ret; + ipa_nat_ipv4_rule ipv4_rule; + uint32_t pub_ip_add = m_public_ip; + ipa_nat_pdn_entry pdn_info; + + // first create the NAT table + ret = ipa_nat_add_ipv4_tbl(pub_ip_add, m_mem_type, total_entries, &m_tbl_hdl); + if (ret) { + LOG_MSG_ERROR("Leaving, failed creating NAT table\n"); + return false; + } + + LOG_MSG_DEBUG("nat table added, hdl %d, public ip 0x%X\n", m_tbl_hdl, + pub_ip_add); + + // modify the PDN entries that will be pointed by the NAT rules + pdn_info.public_ip = m_public_ip; + pdn_info.src_metadata = 0; + pdn_info.dst_metadata = 0; + ret = ipa_nat_modify_pdn(m_tbl_hdl, 1, &pdn_info); + if (ret) { + LOG_MSG_ERROR("Leaving, failed Modifying PDN entry 0 \n"); + return false; + } + + pdn_info.public_ip = m_public_ip2; + pdn_info.src_metadata = 0; + pdn_info.dst_metadata = 0; + ret = ipa_nat_modify_pdn(m_tbl_hdl, 2, &pdn_info); + if (ret) { + LOG_MSG_ERROR("Leaving, failed Modifying PDN entry 1 \n"); + return false; + } + + ipv4_rule.target_ip = m_target_ip; + ipv4_rule.target_port = m_target_port; + ipv4_rule.private_ip = m_private_ip; + ipv4_rule.private_port = m_private_port; + ipv4_rule.protocol = IPPROTO_TCP; + ipv4_rule.public_port = m_public_port; + ipv4_rule.pdn_index = 1; + + ret = ipa_nat_add_ipv4_rule(m_tbl_hdl, &ipv4_rule, &m_nat_rule_hdl1); + if (ret) { + LOG_MSG_ERROR("Leaving, failed adding NAT rule 0\n"); + return false; + } + + LOG_MSG_DEBUG("NAT rule added, hdl %d, data: 0x%X, %d, 0x%X, %d, %d, %d\n", + m_nat_rule_hdl1, ipv4_rule.target_ip, ipv4_rule.target_port, + ipv4_rule.private_ip, ipv4_rule.private_port, + ipv4_rule.protocol, ipv4_rule.public_port); + + // the second rule shall be identical to the first on all parameters except PDN index so the filtering + // block action parameter will provide the PDN index. + ipv4_rule.pdn_index = 2; + + ret = ipa_nat_add_ipv4_rule(m_tbl_hdl, &ipv4_rule, &m_nat_rule_hdl1); + if (ret) { + LOG_MSG_ERROR("Leaving, failed adding NAT rule 1\n"); + return false; + } + + LOG_MSG_DEBUG("NAT rule 2 added, hdl %d, data: 0x%X, %d, 0x%X, %d, %d, %d\n", + m_nat_rule_hdl1, ipv4_rule.target_ip, ipv4_rule.target_port, + ipv4_rule.private_ip, ipv4_rule.private_port, + ipv4_rule.protocol, ipv4_rule.public_port); + + LOG_MSG_DEBUG("Leaving\n"); + return true; + }// AddRules() + + virtual bool ModifyPackets() + { + uint32_t address; + uint16_t port; + char flags = 0x18; + + //first packet private ip 194.23.22.1 --> public ip 195.23.22.1 + address = htonl(m_target_ip);//193.23.22.1 + memcpy(&m_sendBuffer[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + port = htons(m_target_port); + memcpy(&m_sendBuffer[IPV4_DST_PORT_OFFSET], &port, sizeof(port)); + + address = htonl(m_private_ip);/* 194.23.22.1 */ + memcpy(&m_sendBuffer[IPV4_SRC_ADDR_OFFSET], &address, sizeof(address)); + port = htons(m_private_port); + memcpy(&m_sendBuffer[IPV4_SRC_PORT_OFFSET], &port, sizeof(port)); + + //make sure the FIN flag is not set, otherwise we will get a NAT miss + memcpy(&m_sendBuffer[IPV4_TCP_FLAGS_OFFSET], &flags, sizeof(flags)); + + return true; + }// ModifyPacktes () + + virtual bool SendPackets() + { + bool isSuccess = false; + + // Send first packet + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) + { + LOG_MSG_ERROR("SendData failure.\n"); + return false; + } + return true; + } + + virtual bool ReceivePacketsAndCompare() + { + size_t receivedSize = 0; + bool isSuccess = true; + + // Receive results + Byte *rxBuff1 = new Byte[0x400]; + + if (rxBuff1 == NULL) + { + LOG_MSG_ERROR("Memory allocation error.\n"); + return false; + } + + receivedSize = m_consumer.ReceiveData(rxBuff1, 0x400); + LOG_MSG_DEBUG("Received %zu bytes on %s.\n", receivedSize, m_consumer.m_fromChannelName.c_str()); + + // Compare results - verify that the ip of PDN 2 was selected (m_public_ip2) + if (!CompareResultVsGoldenNat( + m_sendBuffer, m_sendSize, + rxBuff1, receivedSize, + m_private_ip, m_public_ip2, + m_private_port, m_public_port, + true)) + { + LOG_MSG_ERROR("Comparison of Buffer0 Failed!\n"); + isSuccess = false; + } + + char recievedBuffer[256] = { 0 }; + char SentBuffer[256] = { 0 }; + size_t j; + + for (j = 0; j < m_sendSize; j++) + snprintf(&SentBuffer[3 * j], sizeof(SentBuffer) - (3 * j + 1), " %02X", m_sendBuffer[j]); + for (j = 0; j < receivedSize; j++) + snprintf(&recievedBuffer[3 * j], sizeof(recievedBuffer) - (3 * j + 1), " %02X", rxBuff1[j]); + LOG_MSG_STACK("sent Value1 (%zu)\n%s\n, Received Value1(%zu)\n%s\n", m_sendSize, SentBuffer, receivedSize, recievedBuffer); + + delete[] rxBuff1; + return isSuccess; + } +}; + +/*---------------------------------------------------------------------------*/ +/* Test009: Single PDN src NAT delete rule test */ +/*---------------------------------------------------------------------------*/ +class IpaNatBlockTest009 : public IpaNatBlockTest001 +{ +public: + IpaNatBlockTest009() + { + m_name = "IpaNatBlockTest009"; + m_description = + "NAT block test 009 - single PDN src NAT rule deletion test\ + 1. Generate and commit three routing tables (only one is used). \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit one filtering rule: (DST & Mask Match). \ + action go to src NAT \ + All DST_IP == (193.23.22.1 & 0.255.255.255)traffic goes to NAT block \ + 3. generate and commit one NAT rule:\ + private ip 194.23.22.1 --> public ip 192.23.22.1\ + 4. delete the NAT rule and expect NAT miss"; + } + + + virtual bool AddRules() + { + LOG_MSG_DEBUG("Entering\n"); + + int ret = IpaNatBlockTest001::AddRules(); + if (!ret) { + LOG_MSG_ERROR("Leaving, failed Adding test 001 rules 0\n"); + return false; + } + + ret = ipa_nat_del_ipv4_rule(m_tbl_hdl, m_nat_rule_hdl1); + if (ret) { + LOG_MSG_ERROR("Leaving, failed deleting NAT rule 0\n"); + return false; + } + LOG_MSG_DEBUG("NAT rule deleted\n"); + + LOG_MSG_DEBUG("Leaving\n"); + return true; + }// AddRules() + + virtual bool ReceivePacketsAndCompare() + { + size_t receivedSize = 0; + bool isSuccess = true; + + // Receive results + Byte *rxBuff1 = new Byte[0x400]; + + if (NULL == rxBuff1) + { + LOG_MSG_ERROR("Memory allocation error.\n"); + return false; + } + + receivedSize = m_consumer.ReceiveData(rxBuff1, 0x400); + LOG_MSG_DEBUG("Received %zu bytes on %s.\n", receivedSize, m_consumer.m_fromChannelName.c_str()); + + if (receivedSize) { + LOG_MSG_ERROR("Data received - test failed!\n"); + isSuccess = false; + + // Compare results + if (!CompareResultVsGoldenNat( + m_sendBuffer, m_sendSize, + rxBuff1, receivedSize, + m_private_ip, m_public_ip, + m_private_port, m_public_port, + true)) + { + LOG_MSG_ERROR("Comparison of Buffer0 Failed!\n"); + } else { + LOG_MSG_ERROR("Comparison of Buffer0 succeeded - NAT rule was hit despite deletion!\n"); + } + + char recievedBuffer[256] = { 0 }; + char SentBuffer[256] = { 0 }; + size_t j; + + for (j = 0; j < m_sendSize; j++) + snprintf(&SentBuffer[3 * j], sizeof(SentBuffer) - (3 * j + 1), " %02X", m_sendBuffer[j]); + for (j = 0; j < receivedSize; j++) + snprintf(&recievedBuffer[3 * j], sizeof(recievedBuffer) - (3 * j + 1), " %02X", rxBuff1[j]); + LOG_MSG_STACK("sent Value1 (%zu)\n%s\n, Received Value1(%zu)\n%s\n", m_sendSize, SentBuffer, receivedSize, recievedBuffer); + } + + delete[] rxBuff1; + + return isSuccess; + } +}; + +/*---------------------------------------------------------------------------*/ +/* Test010: Single PDN dst NAT rule deletion test */ +/*---------------------------------------------------------------------------*/ +class IpaNatBlockTest010 : public IpaNatBlockTest002 +{ +public: + IpaNatBlockTest010() + { + m_name = "IpaNatBlockTest010"; + m_description = + "NAT block test 010 - single PDN dst NAT rule deletion test\ + 1. Generate and commit three routing tables (only one is used). \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit one filtering rule: (DST & Mask Match). \ + action go to dst NAT \ + All DST_IP == (192.23.22.1 & 0.255.255.255)traffic goes to NAT block (public IP filtering) \ + 3. generate and commit one NAT rule:\ + public ip 192.23.22.1 --> private ip 194.23.22.1 \ + delete rule and verrify NAT miss"; + } + + + virtual bool AddRules() + { + LOG_MSG_DEBUG("Entering\n"); + + int ret = IpaNatBlockTest002::AddRules(); + if (!ret) { + LOG_MSG_ERROR("Leaving, failed Adding test 002 rules 0\n"); + return false; + } + + ret = ipa_nat_del_ipv4_rule(m_tbl_hdl, m_nat_rule_hdl1); + if (ret) { + LOG_MSG_ERROR("Leaving, failed deleting NAT rule 0\n"); + return false; + } + LOG_MSG_DEBUG("NAT rule deleted\n"); + + LOG_MSG_DEBUG("Leaving\n"); + return true; + }// AddRules() + + virtual bool ReceivePacketsAndCompare() + { + size_t receivedSize = 0; + bool isSuccess = true; + + // Receive results + Byte *rxBuff1 = new Byte[0x400]; + + if (NULL == rxBuff1) + { + LOG_MSG_ERROR("Memory allocation error.\n"); + return false; + } + + receivedSize = m_consumer.ReceiveData(rxBuff1, 0x400); + LOG_MSG_DEBUG("Received %zu bytes on %s.\n", receivedSize, m_consumer.m_fromChannelName.c_str()); + + if (receivedSize) { + LOG_MSG_ERROR("Data received - test failed!\n"); + isSuccess = false; + + // Compare results + if (!CompareResultVsGoldenNat( + m_sendBuffer, m_sendSize, + rxBuff1, receivedSize, + m_private_ip, m_public_ip, + m_private_port, m_public_port, + false)) + { + LOG_MSG_ERROR("Comparison of Buffer0 Failed!\n"); + } + else { + LOG_MSG_ERROR("Comparison of Buffer0 succeeded - NAT rule was hit despite deletion!\n"); + } + + char recievedBuffer[256] = { 0 }; + char SentBuffer[256] = { 0 }; + size_t j; + + for (j = 0; j < m_sendSize; j++) + snprintf(&SentBuffer[3 * j], sizeof(SentBuffer) - (3 * j + 1), " %02X", m_sendBuffer[j]); + for (j = 0; j < receivedSize; j++) + snprintf(&recievedBuffer[3 * j], sizeof(recievedBuffer) - (3 * j + 1), " %02X", rxBuff1[j]); + LOG_MSG_STACK("sent Value1 (%zu)\n%s\n, Received Value1(%zu)\n%s\n", m_sendSize, SentBuffer, receivedSize, recievedBuffer); + } + + delete[] rxBuff1; + + return isSuccess; + } +}; + +/*---------------------------------------------------------------------------*/ +/* Test011: Multi PDN src NAT - MAX number of PDNs test */ +/*---------------------------------------------------------------------------*/ +class IpaNatBlockTest011 : public IpaNatBlockTestFixture +{ + uint32_t m_public_ip3; + uint32_t m_public_ip4; + uint32_t m_private_ip3; + uint32_t m_private_ip4; + uint16_t m_public_port3; + uint16_t m_public_port4; + uint16_t m_private_port3; + uint16_t m_private_port4; + Byte m_sendBuffer4[BUFF_MAX_SIZE]; + size_t m_sendSize4; + +public: + IpaNatBlockTest011() + { + m_name = "IpaNatBlockTest011"; + m_description = + "NAT block test 011 - Multi PDN src NAT test\ + 1. Generate and commit three routing tables (one is used). \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit one filtering rule: (DST & Mask Match). \ + - action go to src NAT \ + All SRC_IP == (192.23.22.1 & 0.255.255.255)traffic goes to NAT block \ + All SRC_IP == (194.23.22.1 & 0.255.255.255)traffic goes to NAT block \ + All SRC_IP == (196.23.22.1 & 0.255.255.255)traffic goes to NAT block \ + All SRC_IP == (198.23.22.1 & 0.255.255.255)traffic goes to NAT block \ + 3. generate and commit four NAT rules:\ + private ip 192.23.22.1 --> public ip 193.23.22.1 \ + private ip 194.23.22.1 --> public ip 195.23.22.1 \ + private ip 196.23.22.1 --> public ip 197.23.22.1 \ + private ip 198.23.22.1 --> public ip 199.23.22.1"; + m_private_ip = 0xC0171601; /* 192.23.22.1 */ + m_private_port = 5678; + m_public_ip = 0xC1171601; /* "193.23.22.1" */ + m_public_port = 9050; + + m_private_ip2 = 0xC2171601; /* 194.23.22.1 */ + m_private_port2 = 5679; + m_public_ip2 = 0xC3171601; /* "195.23.22.1" */ + m_public_port2 = 9051; + + m_private_ip3 = 0xC4171601; /* 196.23.22.1 */ + m_private_port3 = 5680; + m_public_ip3 = 0xC5171601; /* "197.23.22.1" */ + m_public_port3 = 9052; + + m_private_ip4 = 0xC6171601; /* 198.23.22.1 */ + m_private_port4 = 5681; + m_public_ip4 = 0xC7171601; /* "199.23.22.1" */ + m_public_port4 = 9053; + + m_target_ip = 0xBF171601; /* 191.23.22.1 */ + m_target_port = 1234; + + m_sendSize4 = BUFF_MAX_SIZE; + m_minIPAHwType = IPA_HW_v4_0; + Register(*this); + } + + + virtual bool AddRules() + { + LOG_MSG_DEBUG("Entering\n"); + + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + struct ipa_ioc_get_rt_tbl routing_table0, routing_table1; + + if (!CreateThreeIPv4BypassRoutingTables(bypass0, bypass1, bypass2)) + { + LOG_MSG_ERROR("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + + LOG_MSG_DEBUG("CreateThreeBypassRoutingTables completed successfully\n"); + routing_table0.ip = IPA_IP_v4; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + LOG_MSG_ERROR("m_routing.GetRoutingTable(&routing_table0=0x%p) Failed.\n", &routing_table0); + return false; + } + LOG_MSG_DEBUG("%s route table handle = %u\n", bypass0, routing_table0.hdl); + + routing_table1.ip = IPA_IP_v4; + strlcpy(routing_table1.name, bypass1, sizeof(routing_table1.name)); + if (!m_routing.GetRoutingTable(&routing_table1)) + { + LOG_MSG_ERROR("m_routing.GetRoutingTable(&routing_table1=0x%p) Failed.\n", &routing_table1); + return false; + } + LOG_MSG_DEBUG("%s route table handle = %u\n", bypass1, routing_table1.hdl); + + IPAFilteringTable FilterTable0; + struct ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v4, IPA_CLIENT_TEST_PROD, false, 1); + LOG_MSG_DEBUG("FilterTable*.Init Completed Successfully..\n"); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1, flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl = -1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action = IPA_PASS_TO_SRC_NAT; + flt_rule_entry.rule.rt_tbl_hdl = routing_table0.hdl; + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_SRC_ADDR; + flt_rule_entry.rule.attrib.u.v4.src_addr_mask = 0x00FFFFFF; // Mask - catch all private IPs + flt_rule_entry.rule.attrib.u.v4.src_addr = m_private_ip; // Filter SRC_IP == 192.23.22.1 + flt_rule_entry.rule.pdn_idx = 0; + flt_rule_entry.rule.set_metadata = 0; + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + LOG_MSG_ERROR("Error Adding Rule to Filter Table, aborting...\n"); + return false; + } + else + { + LOG_MSG_DEBUG("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl, FilterTable0.ReadRuleFromTable(0)->status); + } + + //NAT table and rules creation + int total_entries = 20; + int ret; + ipa_nat_ipv4_rule ipv4_rule; + ipa_nat_pdn_entry pdn_info; + + // first create the NAT table + ret = ipa_nat_add_ipv4_tbl(m_public_ip, m_mem_type, total_entries, &m_tbl_hdl); + if (ret) { + LOG_MSG_ERROR("Leaving, failed creating NAT table\n"); + return false; + } + + LOG_MSG_DEBUG("nat table added, hdl %d, public ip 0x%X\n", m_tbl_hdl, + m_public_ip); + + // modify the PDN entries that will be pointed by the NAT rules + pdn_info.public_ip = m_public_ip; + pdn_info.src_metadata = 0; + pdn_info.dst_metadata = 0; + ret = ipa_nat_modify_pdn(m_tbl_hdl, 0, &pdn_info); + if (ret) { + LOG_MSG_ERROR("Leaving, failed Modifying PDN entry 0 \n"); + return false; + } + + pdn_info.public_ip = m_public_ip2; + ret = ipa_nat_modify_pdn(m_tbl_hdl, 1, &pdn_info); + if (ret) { + LOG_MSG_ERROR("Leaving, failed Modifying PDN entry 1 \n"); + return false; + } + + pdn_info.public_ip = m_public_ip3; + ret = ipa_nat_modify_pdn(m_tbl_hdl, 2, &pdn_info); + if (ret) { + LOG_MSG_ERROR("Leaving, failed Modifying PDN entry 2 \n"); + return false; + } + + pdn_info.public_ip = m_public_ip4; + ret = ipa_nat_modify_pdn(m_tbl_hdl, 3, &pdn_info); + if (ret) { + LOG_MSG_ERROR("Leaving, failed Modifying PDN entry 3 \n"); + return false; + } + + LOG_MSG_DEBUG("Added 4 PDNs successfully: 0x%X, 0x%X, 0x%X, 0x%X\n", + m_public_ip, m_public_ip2, m_public_ip3, m_public_ip4); + + ipv4_rule.target_ip = m_target_ip; + ipv4_rule.target_port = m_target_port; + ipv4_rule.private_ip = m_private_ip; + ipv4_rule.private_port = m_private_port; + ipv4_rule.protocol = IPPROTO_TCP; + ipv4_rule.public_port = m_public_port; + ipv4_rule.pdn_index = 0; + + ret = ipa_nat_add_ipv4_rule(m_tbl_hdl, &ipv4_rule, &m_nat_rule_hdl1); + if (ret) { + LOG_MSG_ERROR("Leaving, failed adding NAT rule 0\n"); + return false; + } + + LOG_MSG_DEBUG("NAT rule added, hdl %d, data: 0x%X, %d, 0x%X, %d, %d, %d, $d\n", + m_nat_rule_hdl1, ipv4_rule.target_ip, ipv4_rule.target_port, + ipv4_rule.private_ip, ipv4_rule.private_port, + ipv4_rule.protocol, ipv4_rule.public_port, ipv4_rule.pdn_index); + + ipv4_rule.private_ip = m_private_ip2; + ipv4_rule.private_port = m_private_port2; + ipv4_rule.public_port = m_public_port2; + ipv4_rule.pdn_index = 1; + + ret = ipa_nat_add_ipv4_rule(m_tbl_hdl, &ipv4_rule, &m_nat_rule_hdl1); + if (ret) { + LOG_MSG_ERROR("Leaving, failed adding NAT rule 1\n"); + return false; + } + + LOG_MSG_DEBUG("NAT rule 2 added, hdl %d, data: 0x%X, %d, 0x%X, %d, %d, %d, $d\n", + m_nat_rule_hdl1, ipv4_rule.target_ip, ipv4_rule.target_port, + ipv4_rule.private_ip, ipv4_rule.private_port, + ipv4_rule.protocol, ipv4_rule.public_port, ipv4_rule.pdn_index); + + ipv4_rule.private_ip = m_private_ip3; + ipv4_rule.private_port = m_private_port3; + ipv4_rule.public_port = m_public_port3; + ipv4_rule.pdn_index = 2; + + ret = ipa_nat_add_ipv4_rule(m_tbl_hdl, &ipv4_rule, &m_nat_rule_hdl1); + if (ret) { + LOG_MSG_ERROR("Leaving, failed adding NAT rule 2\n"); + return false; + } + + LOG_MSG_DEBUG("NAT rule 3 added, hdl %d, data: 0x%X, %d, 0x%X, %d, %d, %d, $d\n", + m_nat_rule_hdl1, ipv4_rule.target_ip, ipv4_rule.target_port, + ipv4_rule.private_ip, ipv4_rule.private_port, + ipv4_rule.protocol, ipv4_rule.public_port, ipv4_rule.pdn_index); + + ipv4_rule.private_ip = m_private_ip4; + ipv4_rule.private_port = m_private_port4; + ipv4_rule.public_port = m_public_port4; + ipv4_rule.pdn_index = 3; + + ret = ipa_nat_add_ipv4_rule(m_tbl_hdl, &ipv4_rule, &m_nat_rule_hdl1); + if (ret) { + LOG_MSG_ERROR("Leaving, failed adding NAT rule 3\n"); + return false; + } + + LOG_MSG_DEBUG("NAT rule 4 added, hdl %d, data: 0x%X, %d, 0x%X, %d, %d, %d, $d\n", + m_nat_rule_hdl1, ipv4_rule.target_ip, ipv4_rule.target_port, + ipv4_rule.private_ip, ipv4_rule.private_port, + ipv4_rule.protocol, ipv4_rule.public_port, ipv4_rule.pdn_index); + + LOG_MSG_DEBUG("Leaving\n"); + return true; + }// AddRules() + + virtual bool ModifyPackets() + { + uint32_t address; + uint16_t port; + char flags = 0x18; + + if (!LoadDefaultPacket(IPA_IP_v4, m_extHdrType, m_sendBuffer4, m_sendSize4)) { + LOG_MSG_ERROR("Failed default Packet buffer 4\n"); + return false; + } + LOG_MSG_DEBUG("Loaded %zu Bytes to Buffer 4\n", m_sendSize4); + + //first packet private ip 192.23.22.1 --> public ip 193.23.22.1 + address = htonl(m_target_ip);//191.23.22.1 + memcpy(&m_sendBuffer[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + port = htons(m_target_port); + memcpy(&m_sendBuffer[IPV4_DST_PORT_OFFSET], &port, sizeof(port)); + + address = htonl(m_private_ip);/* 192.23.22.1 */ + memcpy(&m_sendBuffer[IPV4_SRC_ADDR_OFFSET], &address, sizeof(address)); + port = htons(m_private_port); + memcpy(&m_sendBuffer[IPV4_SRC_PORT_OFFSET], &port, sizeof(port)); + + //make sure the FIN flag is not set, otherwise we will get a NAT miss + memcpy(&m_sendBuffer[IPV4_TCP_FLAGS_OFFSET], &flags, sizeof(flags)); + + // second packet private ip 194.23.22.1 --> public ip 195.23.22.1 + address = htonl(m_target_ip);//191.23.22.1 + memcpy(&m_sendBuffer2[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + port = htons(m_target_port); + memcpy(&m_sendBuffer2[IPV4_DST_PORT_OFFSET], &port, sizeof(port)); + + address = htonl(m_private_ip2);/* 194.23.22.1 */ + memcpy(&m_sendBuffer2[IPV4_SRC_ADDR_OFFSET], &address, sizeof(address)); + port = htons(m_private_port2); + memcpy(&m_sendBuffer2[IPV4_SRC_PORT_OFFSET], &port, sizeof(port)); + + //make sure the FIN flag is not set, otherwise we will get a NAT miss + memcpy(&m_sendBuffer2[IPV4_TCP_FLAGS_OFFSET], &flags, sizeof(flags)); + + // third packet private ip 196.23.22.1 --> public ip 197.23.22.1 + address = htonl(m_target_ip);//191.23.22.1 + memcpy(&m_sendBuffer3[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + port = htons(m_target_port); + memcpy(&m_sendBuffer3[IPV4_DST_PORT_OFFSET], &port, sizeof(port)); + + address = htonl(m_private_ip3);/* 196.23.22.1 */ + memcpy(&m_sendBuffer3[IPV4_SRC_ADDR_OFFSET], &address, sizeof(address)); + port = htons(m_private_port3); + memcpy(&m_sendBuffer3[IPV4_SRC_PORT_OFFSET], &port, sizeof(port)); + + //make sure the FIN flag is not set, otherwise we will get a NAT miss + memcpy(&m_sendBuffer3[IPV4_TCP_FLAGS_OFFSET], &flags, sizeof(flags)); + + // third packet private ip 198.23.22.1 --> public ip 199.23.22.1 + address = htonl(m_target_ip);//191.23.22.1 + memcpy(&m_sendBuffer4[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + port = htons(m_target_port); + memcpy(&m_sendBuffer4[IPV4_DST_PORT_OFFSET], &port, sizeof(port)); + + address = htonl(m_private_ip4);/* 198.23.22.1 */ + memcpy(&m_sendBuffer4[IPV4_SRC_ADDR_OFFSET], &address, sizeof(address)); + port = htons(m_private_port4); + memcpy(&m_sendBuffer4[IPV4_SRC_PORT_OFFSET], &port, sizeof(port)); + + //make sure the FIN flag is not set, otherwise we will get a NAT miss + memcpy(&m_sendBuffer4[IPV4_TCP_FLAGS_OFFSET], &flags, sizeof(flags)); + + return true; + }// ModifyPacktes () + + virtual bool SendPackets() + { + bool isSuccess = false; + + // Send first packet + LOG_MSG_DEBUG("sending first packet\n"); + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) + { + LOG_MSG_ERROR("SendData failure.\n"); + return false; + } + + // Send second packet + LOG_MSG_DEBUG("sending second packet\n"); + isSuccess = m_producer.SendData(m_sendBuffer2, m_sendSize2); + if (false == isSuccess) + { + LOG_MSG_ERROR("SendData failure.\n"); + return false; + } + + // Send third packet + LOG_MSG_DEBUG("sending third packet\n"); + isSuccess = m_producer.SendData(m_sendBuffer3, m_sendSize3); + if (false == isSuccess) + { + LOG_MSG_ERROR("SendData failure.\n"); + return false; + } + + // Send fourth packet + LOG_MSG_DEBUG("sending fourth packet\n"); + isSuccess = m_producer.SendData(m_sendBuffer4, m_sendSize4); + if (false == isSuccess) + { + LOG_MSG_ERROR("SendData failure.\n"); + return false; + } + + LOG_MSG_DEBUG("sent successfully four packets\n"); + return true; + } + + virtual bool ReceivePacketsAndCompare() + { + size_t receivedSize = 0; + size_t receivedSize2 = 0; + size_t receivedSize3 = 0; + size_t receivedSize4 = 0; + bool isSuccess = true; + + // Receive results + Byte *rxBuff1 = new Byte[0x400]; + Byte *rxBuff2 = new Byte[0x400]; + Byte *rxBuff3 = new Byte[0x400]; + Byte *rxBuff4 = new Byte[0x400]; + + if (rxBuff1 == NULL) + { + LOG_MSG_ERROR("Memory allocation error 1.\n"); + if (rxBuff2) + delete[] rxBuff2; + if (rxBuff3) + delete[] rxBuff3; + if (rxBuff4) + delete[] rxBuff4; + return false; + } + + if (rxBuff2 == NULL) + { + LOG_MSG_ERROR("Memory allocation error 2.\n"); + delete[] rxBuff1; + if (rxBuff3) + delete[] rxBuff3; + if (rxBuff4) + delete[] rxBuff4; + return false; + } + + if (rxBuff3 == NULL) + { + LOG_MSG_ERROR("Memory allocation error 3.\n"); + delete[] rxBuff1; + delete[] rxBuff2; + if (rxBuff4) + delete[] rxBuff4; + return false; + } + + if (rxBuff4 == NULL) + { + LOG_MSG_ERROR("Memory allocation error 4.\n"); + delete[] rxBuff1; + delete[] rxBuff2; + delete[] rxBuff3; + return false; + } + + receivedSize = m_consumer.ReceiveData(rxBuff1, 0x400); + LOG_MSG_DEBUG("Received %zu bytes on %s.\n", receivedSize, m_consumer.m_fromChannelName.c_str()); + + receivedSize2 = m_consumer.ReceiveData(rxBuff2, 0x400); + LOG_MSG_DEBUG("Received %zu bytes on %s.\n", receivedSize2, m_consumer.m_fromChannelName.c_str()); + + receivedSize3 = m_consumer.ReceiveData(rxBuff3, 0x400); + LOG_MSG_DEBUG("Received %zu bytes on %s.\n", receivedSize3, m_consumer.m_fromChannelName.c_str()); + + receivedSize4 = m_consumer.ReceiveData(rxBuff4, 0x400); + LOG_MSG_DEBUG("Received %zu bytes on %s.\n", receivedSize4, m_consumer.m_fromChannelName.c_str()); + + // Compare results + if (!CompareResultVsGoldenNat( + m_sendBuffer, m_sendSize, + rxBuff1, receivedSize, + m_private_ip, m_public_ip, + m_private_port, m_public_port, + true)) + { + LOG_MSG_ERROR("Comparison of Buffer0 Failed!\n"); + isSuccess = false; + } + + char recievedBuffer[256] = { 0 }; + char SentBuffer[256] = { 0 }; + char recievedBuffer2[256] = { 0 }; + char SentBuffer2[256] = { 0 }; + char recievedBuffer3[256] = { 0 }; + char SentBuffer3[256] = { 0 }; + char recievedBuffer4[256] = { 0 }; + char SentBuffer4[256] = { 0 }; + size_t j; + + for (j = 0; j < m_sendSize; j++) + snprintf(&SentBuffer[3 * j], sizeof(SentBuffer) - (3 * j + 1), " %02X", m_sendBuffer[j]); + for (j = 0; j < receivedSize; j++) + snprintf(&recievedBuffer[3 * j], sizeof(recievedBuffer) - (3 * j + 1), " %02X", rxBuff1[j]); + LOG_MSG_STACK("sent Value1 (%zu)\n%s\n, Received Value1(%zu)\n%s\n", m_sendSize, SentBuffer, receivedSize, recievedBuffer); + + delete[] rxBuff1; + + isSuccess &= CompareResultVsGoldenNat( + m_sendBuffer2, m_sendSize2, + rxBuff2, receivedSize2, + m_private_ip2, m_public_ip2, + m_private_port2, m_public_port2, + true); + + for (j = 0; j < m_sendSize2; j++) + snprintf(&SentBuffer2[3 * j], sizeof(SentBuffer2) - (3 * j + 1), " %02X", m_sendBuffer2[j]); + for (j = 0; j < receivedSize2; j++) + snprintf(&recievedBuffer2[3 * j], sizeof(recievedBuffer2) - (3 * j + 1), " %02X", rxBuff2[j]); + LOG_MSG_STACK("sent Value2 (%zu)\n%s\n, Received Value2(%zu)\n%s\n", m_sendSize2, SentBuffer2, receivedSize2, recievedBuffer2); + + delete[] rxBuff2; + + isSuccess &= CompareResultVsGoldenNat( + m_sendBuffer3, m_sendSize3, + rxBuff3, receivedSize3, + m_private_ip3, m_public_ip3, + m_private_port3, m_public_port3, + true); + + for (j = 0; j < m_sendSize3; j++) + snprintf(&SentBuffer3[3 * j], sizeof(SentBuffer3) - (3 * j + 1), " %02X", m_sendBuffer3[j]); + for (j = 0; j < receivedSize3; j++) + snprintf(&recievedBuffer3[3 * j], sizeof(recievedBuffer3) - (3 * j + 1), " %02X", rxBuff3[j]); + LOG_MSG_STACK("sent Value3 (%zu)\n%s\n, Received Value3(%zu)\n%s\n", m_sendSize3, SentBuffer3, receivedSize3, recievedBuffer3); + + delete[] rxBuff3; + + isSuccess &= CompareResultVsGoldenNat( + m_sendBuffer4, m_sendSize4, + rxBuff4, receivedSize4, + m_private_ip4, m_public_ip4, + m_private_port4, m_public_port4, + true); + + for (j = 0; j < m_sendSize4; j++) + snprintf(&SentBuffer4[3 * j], sizeof(SentBuffer4) - (3 * j + 1), " %02X", m_sendBuffer4[j]); + for (j = 0; j < receivedSize4; j++) + snprintf(&recievedBuffer4[3 * j], sizeof(recievedBuffer4) - (3 * j + 1), " %02X", rxBuff4[j]); + LOG_MSG_STACK("sent Value4 (%zu)\n%s\n, Received Value4(%zu)\n%s\n", m_sendSize4, SentBuffer4, receivedSize4, recievedBuffer4); + + delete[] rxBuff4; + + return isSuccess; + } +}; + +/*---------------------------------------------------------------------------*/ +/* Test012: Single PDN dst NAT test expansion table usage */ +/* NOTE: other classes are derived from this class - change carefully */ +/*---------------------------------------------------------------------------*/ +class IpaNatBlockTest012 : public IpaNatBlockTestFixture +{ + uint32_t m_target_ip2; + uint16_t m_target_port2; +public: + IpaNatBlockTest012() + { + m_name = "IpaNatBlockTest012"; + m_description = + "NAT block test 012 - single PDN dst NAT test - expansion table usage\ + 1. Generate and commit three routing tables (only one is used). \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit one filtering rule: (DST & Mask Match). \ + action go to dst NAT \ + All DST_IP == (192.23.22.1 & 0.255.255.255)traffic goes to NAT block (public IP filtering) \ + 3. generate and commit two NAT rules so second one is located in expansion table:\ + since we use a single public ip this test should work also on pre IPAv4 targets\ + public ip 192.23.22.1 --> private ip 194.23.22.1 "; + m_private_ip = 0xC2171601; /* 194.23.22.1 */ + m_private_port = 5678; + m_private_ip2 = 0xC5171601; /* 197.23.22.1 */ + m_private_port2 = 5679; + m_public_ip = 0xC0171601; /* "192.23.22.1" */ + m_public_port = 9050; + m_target_ip = 0xC1171601; /* 193.23.22.1 */ + m_target_port = 1234; + m_target_ip2 = 0x1601C117; /* swap m_target_ip to get same hash*/ + m_target_port2 = m_target_port; + Register(*this); + } + + + virtual bool AddRules() + { + LOG_MSG_DEBUG("Entering\n"); + + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + struct ipa_ioc_get_rt_tbl routing_table0; + + if (!CreateThreeIPv4BypassRoutingTables(bypass0, bypass1, bypass2)) + { + LOG_MSG_ERROR("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + + LOG_MSG_DEBUG("CreateThreeBypassRoutingTables completed successfully\n"); + routing_table0.ip = IPA_IP_v4; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + LOG_MSG_ERROR("m_routing.GetRoutingTable(&routing_table0=0x%p) Failed.\n", &routing_table0); + return false; + } + LOG_MSG_DEBUG("%s route table handle = %u\n", bypass0, routing_table0.hdl); + + IPAFilteringTable FilterTable0; + struct ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v4, IPA_CLIENT_TEST_PROD, false, 3); + LOG_MSG_DEBUG("FilterTable*.Init Completed Successfully..\n"); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1, flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl = -1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action = IPA_PASS_TO_DST_NAT; + flt_rule_entry.rule.rt_tbl_hdl = routing_table0.hdl; + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + flt_rule_entry.rule.attrib.u.v4.dst_addr_mask = 0x00FFFFFF; // Mask + flt_rule_entry.rule.attrib.u.v4.dst_addr = m_public_ip; // Filter DST_IP == 192.23.22.1 + flt_rule_entry.rule.pdn_idx = 0; + flt_rule_entry.rule.set_metadata = 0; + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + LOG_MSG_ERROR("Error Adding Rule to Filter Table, aborting...\n"); + return false; + } + else + { + LOG_MSG_DEBUG("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl, FilterTable0.ReadRuleFromTable(0)->status); + } + + //NAT table and rules creation + int total_entries = 20; + int ret; + ipa_nat_ipv4_rule ipv4_rule; + uint32_t pub_ip_add = m_public_ip; + + ret = ipa_nat_add_ipv4_tbl(pub_ip_add, m_mem_type, total_entries, &m_tbl_hdl); + if (ret) { + LOG_MSG_ERROR("Leaving, failed creating NAT table\n"); + return false; + } + + LOG_MSG_DEBUG("nat table added, hdl %d, public ip 0x%X\n", m_tbl_hdl, + pub_ip_add); + + ipv4_rule.target_ip = m_target_ip; + ipv4_rule.target_port = m_target_port; + ipv4_rule.private_ip = m_private_ip; + ipv4_rule.private_port = m_private_port; + ipv4_rule.protocol = IPPROTO_TCP; + ipv4_rule.public_port = m_public_port; + ipv4_rule.pdn_index = 0; + + ret = ipa_nat_add_ipv4_rule(m_tbl_hdl, &ipv4_rule, &m_nat_rule_hdl1); + if (ret) { + LOG_MSG_ERROR("Leaving, failed adding NAT rule 0\n"); + return false; + } + + LOG_MSG_DEBUG("NAT rule added, hdl %d, data: 0x%X, %d, 0x%X, %d, %d, %d, $d\n", + m_nat_rule_hdl1, ipv4_rule.target_ip, ipv4_rule.target_port, + ipv4_rule.private_ip, ipv4_rule.private_port, + ipv4_rule.protocol, ipv4_rule.public_port, ipv4_rule.pdn_index); + + ipv4_rule.target_ip = m_target_ip2; + ipv4_rule.target_port = m_target_port2; + + // private IPs are not part of the dst NAT entry hash calculation + ipv4_rule.private_ip = m_private_ip2; + ipv4_rule.private_port = m_private_port2; + + ret = ipa_nat_add_ipv4_rule(m_tbl_hdl, &ipv4_rule, &m_nat_rule_hdl1); + if (ret) { + LOG_MSG_ERROR("Leaving, failed adding NAT rule 0\n"); + return false; + } + + LOG_MSG_DEBUG("NAT rule 2 added, hdl %d, data: 0x%X, %d, 0x%X, %d, %d, %d, $d\n", + m_nat_rule_hdl1, ipv4_rule.target_ip, ipv4_rule.target_port, + ipv4_rule.private_ip, ipv4_rule.private_port, + ipv4_rule.protocol, ipv4_rule.public_port, ipv4_rule.pdn_index); + + LOG_MSG_DEBUG("Leaving\n"); + return true; + }// AddRules() + + virtual bool ModifyPackets() + { + uint32_t address; + uint16_t port; + char flags = 0x18; + + address = htonl(m_public_ip); + memcpy(&m_sendBuffer[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + port = htons(m_public_port); + memcpy(&m_sendBuffer[IPV4_DST_PORT_OFFSET], &port, sizeof(port)); + + address = htonl(m_target_ip2); + memcpy(&m_sendBuffer[IPV4_SRC_ADDR_OFFSET], &address, sizeof(address)); + port = htons(m_target_port2); + memcpy(&m_sendBuffer[IPV4_SRC_PORT_OFFSET], &port, sizeof(port)); + + //make sure the FIN flag is not set, otherwise we will get a NAT miss + memcpy(&m_sendBuffer[IPV4_TCP_FLAGS_OFFSET], &flags, sizeof(flags)); + + return true; + }// ModifyPacktes () + + virtual bool SendPackets() + { + bool isSuccess = false; + + // Send first packet + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) + { + LOG_MSG_ERROR("SendData failure.\n"); + return false; + } + + LOG_MSG_DEBUG("sent successfully one packet\n"); + return true; + } + + virtual bool ReceivePacketsAndCompare() + { + size_t receivedSize = 0; + bool isSuccess = true; + + // Receive results + Byte *rxBuff1 = new Byte[0x400]; + + if (NULL == rxBuff1) + { + LOG_MSG_ERROR("Memory allocation error.\n"); + return false; + } + + receivedSize = m_consumer.ReceiveData(rxBuff1, 0x400); + LOG_MSG_DEBUG("Received %zu bytes on %s.\n", receivedSize, m_consumer.m_fromChannelName.c_str()); + + // Compare results + if (!CompareResultVsGoldenNat( + m_sendBuffer, m_sendSize, + rxBuff1, receivedSize, + m_private_ip2, m_public_ip, + m_private_port2, m_public_port, + false)) + { + LOG_MSG_ERROR("Comparison of Buffer0 Failed!\n"); + isSuccess = false; + } + + char recievedBuffer[256] = { 0 }; + char SentBuffer[256] = { 0 }; + size_t j; + + for (j = 0; j < m_sendSize; j++) + snprintf(&SentBuffer[3 * j], sizeof(SentBuffer) - (3 * j + 1), " %02X", m_sendBuffer[j]); + for (j = 0; j < receivedSize; j++) + snprintf(&recievedBuffer[3 * j], sizeof(recievedBuffer) - (3 * j + 1), " %02X", rxBuff1[j]); + LOG_MSG_STACK("sent Value1 (%zu)\n%s\n, Received Value1(%zu)\n%s\n", m_sendSize, SentBuffer, receivedSize, recievedBuffer); + + delete[] rxBuff1; + + return isSuccess; + } +}; + +/*---------------------------------------------------------------------------*/ +/* Test013: Single PDN dst NAT expansion rule deletion test */ +/*---------------------------------------------------------------------------*/ +class IpaNatBlockTest013 : public IpaNatBlockTest012 +{ +public: + IpaNatBlockTest013() + { + m_name = "IpaNatBlockTest013"; + m_description = + "NAT block test 013 - single PDN dst NAT test - expansion table rule deletion\ + 1. Generate and commit three routing tables (only one is used). \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit one filtering rule: (DST & Mask Match). \ + action go to dst NAT \ + All DST_IP == (192.23.22.1 & 0.255.255.255)traffic goes to NAT block (public IP filtering) \ + 3. generate and commit two NAT rules so second one is located in expansion table:\ + since we use a single public ip this test should work also on pre IPAv4 targets\ + public ip 192.23.22.1 --> private ip 194.23.22.1\ + 4. delete NAT rule and expect NAT miss"; + } + + + virtual bool AddRules() + { + LOG_MSG_DEBUG("Entering\n"); + + int ret = IpaNatBlockTest012::AddRules(); + if (!ret) { + LOG_MSG_ERROR("Leaving, failed Adding test 012 rules 0\n"); + return false; + } + + ret = ipa_nat_del_ipv4_rule(m_tbl_hdl, m_nat_rule_hdl1); + if (ret) { + LOG_MSG_ERROR("Leaving, failed deleting NAT rule 1\n"); + return false; + } + LOG_MSG_DEBUG("NAT rule deleted\n"); + + LOG_MSG_DEBUG("Leaving\n"); + return true; + }// AddRules() + + virtual bool ReceivePacketsAndCompare() + { + size_t receivedSize = 0; + bool isSuccess = true; + + // Receive results + Byte *rxBuff1 = new Byte[0x400]; + + if (NULL == rxBuff1) + { + LOG_MSG_ERROR("Memory allocation error.\n"); + return false; + } + + receivedSize = m_consumer.ReceiveData(rxBuff1, 0x400); + LOG_MSG_DEBUG("Received %zu bytes on %s.\n", receivedSize, m_consumer.m_fromChannelName.c_str()); + + if (receivedSize) { + LOG_MSG_ERROR("Data received - test failed!\n"); + isSuccess = false; + + // Compare results for debug in the case of failure only + if (!CompareResultVsGoldenNat( + m_sendBuffer, m_sendSize, + rxBuff1, receivedSize, + m_private_ip2, m_public_ip, + m_private_port2, m_public_port, + false)) + { + LOG_MSG_ERROR("Comparison of Buffer0 Failed!\n"); + } + else { + LOG_MSG_ERROR("Comparison of Buffer0 succeeded - NAT rule was hit despite deletion!\n"); + } + + char recievedBuffer[256] = { 0 }; + char SentBuffer[256] = { 0 }; + size_t j; + + for (j = 0; j < m_sendSize; j++) + snprintf(&SentBuffer[3 * j], sizeof(SentBuffer) - (3 * j + 1), " %02X", m_sendBuffer[j]); + for (j = 0; j < receivedSize; j++) + snprintf(&recievedBuffer[3 * j], sizeof(recievedBuffer) - (3 * j + 1), " %02X", rxBuff1[j]); + LOG_MSG_STACK("sent Value1 (%zu)\n%s\n, Received Value1(%zu)\n%s\n", m_sendSize, SentBuffer, receivedSize, recievedBuffer); + } + + delete[] rxBuff1; + + return isSuccess; + } +}; + +/*---------------------------------------------------------------------------*/ +/* Test014: Single PDN src NAT zero PDN test */ +/*---------------------------------------------------------------------------*/ +class IpaNatBlockTest014 : public IpaNatBlockTest001 +{ +public: + IpaNatBlockTest014() + { + m_name = "IpaNatBlockTest014"; + m_description = + "NAT block test 014 - single PDN src NAT PDN zeroing test\ + 1. Generate and commit three routing tables (only one is used). \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit one filtering rule: (DST & Mask Match). \ + action go to src NAT \ + All DST_IP == (193.23.22.1 & 0.255.255.255)traffic goes to NAT block \ + 3. generate and commit one NAT rule:\ + private ip 194.23.22.1 --> public ip 192.23.22.1\ + 4. modify PDN entry 0 and expect NAT miss"; + m_minIPAHwType = IPA_HW_v4_0; + } + + + virtual bool AddRules() + { + ipa_nat_pdn_entry pdn_info; + + LOG_MSG_DEBUG("Entering\n"); + + int ret = IpaNatBlockTest001::AddRules(); + if (!ret) { + LOG_MSG_ERROR("Leaving, failed Adding test 001 rules 0\n"); + return false; + } + + // modify PDN entry 0 so the NAT rule will get a NAT miss + pdn_info.public_ip = 0; + pdn_info.src_metadata = 0; + pdn_info.dst_metadata = 0; + ret = ipa_nat_modify_pdn(m_tbl_hdl, 0, &pdn_info); + if (ret) { + LOG_MSG_ERROR("Leaving, failed Modifying PDN entry 0 \n"); + return false; + } + + LOG_MSG_DEBUG("PDN modified\n"); + + LOG_MSG_DEBUG("Leaving\n"); + return true; + }// AddRules() + + virtual bool ReceivePacketsAndCompare() + { + size_t receivedSize = 0; + bool isSuccess = true; + + // Receive results + Byte *rxBuff1 = new Byte[0x400]; + + if (NULL == rxBuff1) + { + LOG_MSG_ERROR("Memory allocation error.\n"); + return false; + } + + receivedSize = m_consumer.ReceiveData(rxBuff1, 0x400); + LOG_MSG_DEBUG("Received %zu bytes on %s.\n", receivedSize, m_consumer.m_fromChannelName.c_str()); + + if (receivedSize) { + LOG_MSG_ERROR("Data received - test failed!\n"); + isSuccess = false; + + // Compare results + if (!CompareResultVsGoldenNat( + m_sendBuffer, m_sendSize, + rxBuff1, receivedSize, + m_private_ip, m_public_ip, + m_private_port, m_public_port, + true)) + { + LOG_MSG_ERROR("Comparison of Buffer0 Failed!\n"); + } + else { + LOG_MSG_ERROR("Comparison of Buffer0 succeeded - NAT rule was hit despite deletion!\n"); + } + + char recievedBuffer[256] = { 0 }; + char SentBuffer[256] = { 0 }; + size_t j; + + for (j = 0; j < m_sendSize; j++) + snprintf(&SentBuffer[3 * j], sizeof(SentBuffer) - (3 * j + 1), " %02X", m_sendBuffer[j]); + for (j = 0; j < receivedSize; j++) + snprintf(&recievedBuffer[3 * j], sizeof(recievedBuffer) - (3 * j + 1), " %02X", rxBuff1[j]); + LOG_MSG_STACK("sent Value1 (%zu)\n%s\n, Received Value1(%zu)\n%s\n", m_sendSize, SentBuffer, receivedSize, recievedBuffer); + } + + delete[] rxBuff1; + + return isSuccess; + } +}; + +/*---------------------------------------------------------------------------*/ +/* Test015: Single PDN src NAT send two packets that will hit the same rule */ +/*---------------------------------------------------------------------------*/ +class IpaNatBlockTest015 : public IpaNatBlockTest001 +{ +public: + IpaNatBlockTest015() + { + m_name = "IpaNatBlockTest015"; + m_description = + "NAT block test 015 - single PDN src NAT hit the same rule twice\ + 1. Generate and commit three routing tables (only one is used). \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit one filtering rule: (DST & Mask Match). \ + action go to src NAT \ + All DST_IP == (193.23.22.1 & 0.255.255.255)traffic goes to NAT block \ + 3. generate and commit one NAT rule:\ + private ip 194.23.22.1 --> public ip 192.23.22.1\ + 4. send two pakcets and verify NATing"; + } + + virtual bool SendPackets() + { + bool ret = IpaNatBlockTest001::SendPackets(); + if (!ret) + { + LOG_MSG_ERROR("failed sending first pakcket.\n"); + return false; + } + + LOG_MSG_DEBUG("first packet sent succesfully.\n"); + + ret = IpaNatBlockTest001::SendPackets(); + if (!ret) + { + LOG_MSG_ERROR("failed sending second pakcket.\n"); + return false; + } + + LOG_MSG_DEBUG("second packet sent succesfully.\n"); + + return true; + } + + virtual bool ReceivePacketsAndCompare() + { + bool isSuccess = true; + + isSuccess &= IpaNatBlockTest001::ReceivePacketsAndCompare(); + if (!isSuccess) + { + LOG_MSG_ERROR("failed to receive\\compare first packet.\n"); + } + + isSuccess &= IpaNatBlockTest001::ReceivePacketsAndCompare(); + if (!isSuccess) + { + LOG_MSG_ERROR("failed to receive\\compare second packet.\n"); + } + + return isSuccess; + } +}; + +/*---------------------------------------------------------------------------*/ +/* Test016: Single PDN dst NAT send two packets that will hit the same rule */ +/*---------------------------------------------------------------------------*/ +class IpaNatBlockTest016 : public IpaNatBlockTest002 +{ +public: + IpaNatBlockTest016() + { + m_name = "IpaNatBlockTest016"; + m_description = + "NAT block test 016 - single PDN dst NAT hit the same rule twice\ + 1. Generate and commit three routing tables (only one is used). \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit one filtering rule: (DST & Mask Match). \ + action go to dst NAT \ + All DST_IP == (192.23.22.1 & 0.255.255.255)traffic goes to NAT block \ + 3. generate and commit one NAT rule:\ + public ip 192.23.22.1 --> private ip 194.23.22.1\ + 4. send two pakcets and verify NATing"; + } + + virtual bool SendPackets() + { + bool ret = IpaNatBlockTest002::SendPackets(); + if (!ret) + { + LOG_MSG_ERROR("failed sending first pakcket.\n"); + return false; + } + + LOG_MSG_DEBUG("first packet sent succesfully.\n"); + + ret = IpaNatBlockTest002::SendPackets(); + if (!ret) + { + LOG_MSG_ERROR("failed sending second pakcket.\n"); + return false; + } + + LOG_MSG_DEBUG("second packet sent succesfully.\n"); + + return true; + } + + virtual bool ReceivePacketsAndCompare() + { + bool isSuccess = true; + + isSuccess &= IpaNatBlockTest002::ReceivePacketsAndCompare(); + if (!isSuccess) + { + LOG_MSG_ERROR("failed to receive\\compare first packet.\n"); + } + + isSuccess &= IpaNatBlockTest002::ReceivePacketsAndCompare(); + if (!isSuccess) + { + LOG_MSG_ERROR("failed to receive\\compare second packet.\n"); + } + + return isSuccess; + } +}; + +/*---------------------------------------------------------------------------------*/ +/* Test017: Multi PDN src NAT test with identical private IPs and different ports */ +/*---------------------------------------------------------------------------------*/ +class IpaNatBlockTest017 : public IpaNatBlockTest003 +{ +public: + IpaNatBlockTest017() + { + m_name = "IpaNatBlockTest017"; + m_description = + "NAT block test 017 - Multi PDN src NAT test with identical private IPs\ + 1. Generate and commit three routing tables (two are used). \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit two filtering rule: (DST & Mask Match). \ + - action go to src NAT \ + All SRC_IP == (194.23.22.1 & 0.255.255.255)traffic goes to NAT block \ + All SRC_IP == (197.23.22.1 & 0.255.255.255)traffic goes to NAT block - not relevant for this test \ + 3. generate and commit two NAT rules:\ + private ip 194.23.22.1 && port 5678--> public ip 192.23.22.1 \ + private ip 194.23.22.1 && port 5679--> public ip 195.23.22.1"; + m_private_ip2 = m_private_ip; + } + + virtual bool ReceivePacketsAndCompare() + { + // we cannot just use test 003 ReceivePacketsAndCompare since the filtering rules send the + // packets to two different pipes, but since the private IPs are now equal the second filtering rule + // won't be hit so we need to recive the second packet on the first pipe + + size_t receivedSize = 0; + size_t receivedSize2 = 0; + bool isSuccess = true; + + // Receive results + Byte *rxBuff1 = new Byte[0x400]; + Byte *rxBuff2 = new Byte[0x400]; + + if (rxBuff1 == NULL) + { + LOG_MSG_ERROR("Memory allocation error.\n"); + if (rxBuff2) + delete[] rxBuff2; + return false; + } + + if (rxBuff2 == NULL) + { + LOG_MSG_ERROR("Memory allocation error.\n"); + delete[] rxBuff1; + return false; + } + + receivedSize = m_consumer.ReceiveData(rxBuff1, 0x400); + LOG_MSG_DEBUG("Received %zu bytes on %s.\n", receivedSize, m_consumer.m_fromChannelName.c_str()); + + receivedSize2 = m_consumer.ReceiveData(rxBuff2, 0x400); + LOG_MSG_DEBUG("Received %zu bytes on %s.\n", receivedSize2, m_consumer.m_fromChannelName.c_str()); + + // Compare results + if (!CompareResultVsGoldenNat( + m_sendBuffer, m_sendSize, + rxBuff1, receivedSize, + m_private_ip, m_public_ip, + m_private_port, m_public_port, + true)) + { + LOG_MSG_ERROR("Comparison of Buffer0 Failed!\n"); + isSuccess = false; + } + + char recievedBuffer[256] = { 0 }; + char SentBuffer[256] = { 0 }; + char recievedBuffer2[256] = { 0 }; + char SentBuffer2[256] = { 0 }; + size_t j; + + for (j = 0; j < m_sendSize; j++) + snprintf(&SentBuffer[3 * j], sizeof(SentBuffer) - (3 * j + 1), " %02X", m_sendBuffer[j]); + for (j = 0; j < receivedSize; j++) + snprintf(&recievedBuffer[3 * j], sizeof(recievedBuffer) - (3 * j + 1), " %02X", rxBuff1[j]); + LOG_MSG_STACK("sent Value1 (%zu)\n%s\n, Received Value1(%zu)\n%s\n", m_sendSize, SentBuffer, receivedSize, recievedBuffer); + + delete[] rxBuff1; + + isSuccess &= CompareResultVsGoldenNat( + m_sendBuffer2, m_sendSize2, + rxBuff2, receivedSize2, + m_private_ip2, m_public_ip2, + m_private_port2, m_public_port2, + true); + + for (j = 0; j < m_sendSize2; j++) + snprintf(&SentBuffer2[3 * j], sizeof(SentBuffer2) - (3 * j + 1), " %02X", m_sendBuffer2[j]); + for (j = 0; j < receivedSize2; j++) + snprintf(&recievedBuffer2[3 * j], sizeof(recievedBuffer2) - (3 * j + 1), " %02X", rxBuff2[j]); + LOG_MSG_STACK("sent Value2 (%zu)\n%s\n, Received Value2(%zu)\n%s\n", m_sendSize2, SentBuffer2, receivedSize2, recievedBuffer2); + + delete[] rxBuff2; + + return isSuccess; + } +}; + +/*---------------------------------------------------------------------------------*/ +/* Test018: Multi PDN dst NAT test with identical private IPs and different ports */ +/*---------------------------------------------------------------------------------*/ +class IpaNatBlockTest018 : public IpaNatBlockTest004 +{ +public: + IpaNatBlockTest018() + { + m_name = "IpaNatBlockTest018"; + m_description = + "NAT block test 018 - Multi PDN dst NAT test with identical private IPs\ + 1. Generate and commit three routing tables (two are used). \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit two filtering rule: (DST & Mask Match). \ + - action go to dst NAT \ + All DST_IP == (192.23.22.1 & 0.255.255.255)traffic goes to NAT block \ + All DST_IP == (195.23.22.1 & 0.255.255.255)traffic goes to NAT block - not releveant for this test\ + 3. generate and commit two NAT rules:\ + private ip 194.23.22.1 --> public ip 192.23.22.1 && port 9050\ + private ip 194.23.22.1 --> public ip 192.23.22.1 && port 9051"; + m_private_ip2 = m_private_ip; + } +}; + +/*---------------------------------------------------------------------------*/ +/* Test019: NAT Suppression test */ +/* NOTE: other classes are derived from this class - change carefully */ +/*---------------------------------------------------------------------------*/ +class IpaNatBlockTest019 : public IpaNatBlockTestFixture +{ +public: + IpaNatBlockTest019() + { + m_name = "IpaNatBlockTest019"; + m_description = + "NAT block test 019 - single PDN src NAT test\ + 1. Generate and commit three routing tables (only one is used). \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit one filtering rule: (DST & Mask Match). \ + action go to src NAT \ + All DST_IP == (193.23.22.1 & 0.255.255.255)traffic goes to NAT block \ + 3. generate and commit one NAT rule:\ + private ip 194.23.22.1 --> public ip 192.23.22.1"; + m_private_ip = 0xC2171601; /* 194.23.22.1 */ + m_private_port = 5678; + m_public_ip = 0xC0171601; /* "192.23.22.1" */ + m_public_port = 9050; + m_target_ip = 0xC1171601; /* 193.23.22.1 */ + m_target_port = 1234; + Register(*this); + } + + virtual bool Setup() + { + return IpaNatBlockTestFixture::Setup(false, true); + } + + virtual bool AddRules() + { + LOG_MSG_DEBUG("Entering\n"); + + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + struct ipa_ioc_get_rt_tbl routing_table0; + + if (!CreateThreeIPv4BypassRoutingTables(bypass0, bypass1, bypass2)) + { + LOG_MSG_ERROR("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + + LOG_MSG_DEBUG("CreateThreeBypassRoutingTables completed successfully\n"); + routing_table0.ip = IPA_IP_v4; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + LOG_MSG_ERROR("m_routing.GetRoutingTable(&routing_table0=0x%p) Failed.\n", &routing_table0); + return false; + } + LOG_MSG_DEBUG("%s route table handle = %u\n", bypass0, routing_table0.hdl); + + /* Setup NAT Exception routing table. */ + if (!m_routing.SetNatConntrackExcRoutingTable(routing_table0.hdl, true)) + { + LOG_MSG_ERROR("m_routing.SetNatConntrackExcRoutingTable(routing_table0 hdl=%d) Failed.\n", + routing_table0.hdl); + return false; + } + + IPAFilteringTable FilterTable0; + struct ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v4, IPA_CLIENT_TEST_PROD, false, 1); + LOG_MSG_DEBUG("FilterTable*.Init Completed Successfully..\n"); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1, flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl = -1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action = IPA_PASS_TO_SRC_NAT; + flt_rule_entry.rule.rt_tbl_hdl = routing_table0.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + flt_rule_entry.rule.attrib.u.v4.dst_addr_mask = 0xFFFFFF00; // Mask + flt_rule_entry.rule.attrib.u.v4.dst_addr = m_target_ip; // Filter DST_IP == 193.23.22.1 + flt_rule_entry.rule.pdn_idx = 0; + flt_rule_entry.rule.set_metadata = 0; + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + LOG_MSG_ERROR("Error Adding Rule to Filter Table, aborting...\n"); + return false; + } + else + { + LOG_MSG_DEBUG("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl, FilterTable0.ReadRuleFromTable(0)->status); + } + + //NAT table and rules creation + int total_entries = 20; + int ret; + ipa_nat_ipv4_rule ipv4_rule; + + ret = ipa_nat_add_ipv4_tbl(m_public_ip, m_mem_type, total_entries, &m_tbl_hdl); + if (ret) { + LOG_MSG_DEBUG("failed creating NAT table\n"); + return false; + } + LOG_MSG_DEBUG("nat table added, hdl %d, public ip 0x%X\n", m_tbl_hdl, + m_public_ip); + + ipv4_rule.target_ip = m_target_ip; + ipv4_rule.target_port = m_target_port; + ipv4_rule.private_ip = m_private_ip; + ipv4_rule.private_port = m_private_port; + ipv4_rule.protocol = IPPROTO_TCP; + ipv4_rule.public_port = m_public_port; + ipv4_rule.pdn_index = 0; + + ret = ipa_nat_add_ipv4_rule(m_tbl_hdl, &ipv4_rule, &m_nat_rule_hdl1); + if (ret) { + LOG_MSG_ERROR("failed adding NAT rule 0\n"); + return false; + } + LOG_MSG_DEBUG("NAT rule added, hdl %d, data: 0x%X, %d, 0x%X, %d, %d, %d\n", + m_nat_rule_hdl1, ipv4_rule.target_ip, ipv4_rule.target_port, + ipv4_rule.private_ip, ipv4_rule.private_port, + ipv4_rule.protocol, ipv4_rule.public_port); + + LOG_MSG_DEBUG("Leaving"); + return true; + }// AddRules() + + virtual bool ModifyPackets() + { + uint32_t address; + uint16_t port; + char flags = 0x18; + + address = htonl(m_target_ip);//193.23.22.1 + memcpy(&m_sendBuffer[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + port = htons(m_target_port); + memcpy(&m_sendBuffer[IPV4_DST_PORT_OFFSET], &port, sizeof(port)); + + address = htonl(m_private_ip);/* 194.23.22.1 */ + memcpy(&m_sendBuffer[IPV4_SRC_ADDR_OFFSET], &address, sizeof(address)); + port = htons(m_private_port+1); + memcpy(&m_sendBuffer[IPV4_SRC_PORT_OFFSET], &port, sizeof(port)); + + //make sure the FIN flag is not set, otherwise we will get a NAT miss + memcpy(&m_sendBuffer[IPV4_TCP_FLAGS_OFFSET],&flags , sizeof(flags)); + return true; + }// ModifyPacktes () + + virtual bool SendPackets() + { + bool isSuccess = false; + + // Send first packet + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) + { + LOG_MSG_ERROR("SendData failure.\n"); + return false; + } + + LOG_MSG_DEBUG("sent successfully one packet\n"); + return true; + } + + virtual bool ReceivePacketsAndCompare() + { + size_t receivedSize = 0; + bool isSuccess = true; + + // Receive results + Byte *rxBuff1 = new Byte[0x400]; + + if (NULL == rxBuff1) + { + LOG_MSG_ERROR("Memory allocation error.\n"); + return false; + } + + receivedSize = m_consumer.ReceiveData(rxBuff1, 0x400); + LOG_MSG_DEBUG("Received %zu bytes on %s.\n", receivedSize, m_consumer.m_fromChannelName.c_str()); + + // Compare results + if (!CompareResultVsGolden(m_sendBuffer, m_sendSize, rxBuff1, receivedSize)) + { + printf("Comparison of Buffer0 Failed!\n"); + isSuccess = false; + } + + char recievedBuffer[256] = { 0 }; + char SentBuffer[256] = { 0 }; + size_t j; + + for (j = 0; j < m_sendSize; j++) + snprintf(&SentBuffer[3 * j], sizeof(SentBuffer) - (3 * j + 1), " %02X", m_sendBuffer[j]); + for (j = 0; j < receivedSize; j++) + snprintf(&recievedBuffer[3 * j], sizeof(recievedBuffer) - (3 * j + 1), " %02X", rxBuff1[j]); + LOG_MSG_STACK("sent Value1 (%zu)\n%s\n, Received Value1(%zu)\n%s\n", m_sendSize, SentBuffer, receivedSize, recievedBuffer); + + delete[] rxBuff1; + + return isSuccess; + } +}; + +/*---------------------------------------------------------------------------*/ +/* Test020: NAT Suppression test with Status */ +/* NOTE: other classes are derived from this class - change carefully */ +/*---------------------------------------------------------------------------*/ +class IpaNatBlockTest020 : public IpaNatBlockTestFixture +{ +public: + IpaNatBlockTest020() + { + m_name = "IpaNatBlockTest020"; + m_description = + "NAT block test 020 - single PDN src NAT test with status enabled\ + 1. Generate and commit three routing tables (only one is used). \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit one filtering rule: (DST & Mask Match). \ + action go to src NAT \ + All DST_IP == (193.23.22.1 & 0.255.255.255)traffic goes to NAT block \ + 3. generate and commit one NAT rule:\ + private ip 194.23.22.1 --> public ip 192.23.22.1"; + m_private_ip = 0xC2171601; /* 194.23.22.1 */ + m_private_port = 5678; + m_public_ip = 0xC0171601; /* "192.23.22.1" */ + m_public_port = 9050; + m_target_ip = 0xC1171601; /* 193.23.22.1 */ + m_target_port = 1234; + Register(*this); + } + + virtual bool Setup() + { + return IpaNatBlockTestFixture::Setup(true, true); + } + + virtual bool AddRules() + { + LOG_MSG_DEBUG("Entering\n"); + + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + struct ipa_ioc_get_rt_tbl routing_table0; + + if (!CreateThreeIPv4BypassRoutingTables(bypass0, bypass1, bypass2)) + { + LOG_MSG_ERROR("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + + LOG_MSG_DEBUG("CreateThreeBypassRoutingTables completed successfully\n"); + routing_table0.ip = IPA_IP_v4; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + LOG_MSG_ERROR("m_routing.GetRoutingTable(&routing_table0=0x%p) Failed.\n", &routing_table0); + return false; + } + LOG_MSG_DEBUG("%s route table handle = %u\n", bypass0, routing_table0.hdl); + + /* Setup NAT Exception routing table. */ + if (!m_routing.SetNatConntrackExcRoutingTable(routing_table0.hdl, true)) + { + LOG_MSG_ERROR("m_routing.SetNatConntrackExcRoutingTable(routing_table0 hdl=%d) Failed.\n", + routing_table0.hdl); + return false; + } + + IPAFilteringTable FilterTable0; + struct ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v4, IPA_CLIENT_TEST_PROD, false, 1); + LOG_MSG_DEBUG("FilterTable*.Init Completed Successfully..\n"); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1, flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl = -1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action = IPA_PASS_TO_SRC_NAT; + flt_rule_entry.rule.rt_tbl_hdl = routing_table0.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + flt_rule_entry.rule.attrib.u.v4.dst_addr_mask = 0xFFFFFF00; // Mask + flt_rule_entry.rule.attrib.u.v4.dst_addr = m_target_ip; // Filter DST_IP == 193.23.22.1 + flt_rule_entry.rule.pdn_idx = 0; + flt_rule_entry.rule.set_metadata = 0; + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + LOG_MSG_ERROR("Error Adding Rule to Filter Table, aborting...\n"); + return false; + } + else + { + LOG_MSG_DEBUG("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl, FilterTable0.ReadRuleFromTable(0)->status); + } + + //NAT table and rules creation + int total_entries = 20; + int ret; + ipa_nat_ipv4_rule ipv4_rule; + + ret = ipa_nat_add_ipv4_tbl(m_public_ip, m_mem_type, total_entries, &m_tbl_hdl); + if (ret) { + LOG_MSG_DEBUG("failed creating NAT table\n"); + return false; + } + LOG_MSG_DEBUG("nat table added, hdl %d, public ip 0x%X\n", m_tbl_hdl, + m_public_ip); + + ipv4_rule.target_ip = m_target_ip; + ipv4_rule.target_port = m_target_port; + ipv4_rule.private_ip = m_private_ip; + ipv4_rule.private_port = m_private_port; + ipv4_rule.protocol = IPPROTO_TCP; + ipv4_rule.public_port = m_public_port; + ipv4_rule.pdn_index = 0; + + ret = ipa_nat_add_ipv4_rule(m_tbl_hdl, &ipv4_rule, &m_nat_rule_hdl1); + if (ret) { + LOG_MSG_ERROR("failed adding NAT rule 0\n"); + return false; + } + LOG_MSG_DEBUG("NAT rule added, hdl %d, data: 0x%X, %d, 0x%X, %d, %d, %d\n", + m_nat_rule_hdl1, ipv4_rule.target_ip, ipv4_rule.target_port, + ipv4_rule.private_ip, ipv4_rule.private_port, + ipv4_rule.protocol, ipv4_rule.public_port); + + LOG_MSG_DEBUG("Leaving"); + return true; + }// AddRules() + + virtual bool ModifyPackets() + { + uint32_t address; + uint16_t port; + char flags = 0x18; + + address = htonl(m_target_ip);//193.23.22.1 + memcpy(&m_sendBuffer[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + port = htons(m_target_port); + memcpy(&m_sendBuffer[IPV4_DST_PORT_OFFSET], &port, sizeof(port)); + + address = htonl(m_private_ip);/* 194.23.22.1 */ + memcpy(&m_sendBuffer[IPV4_SRC_ADDR_OFFSET], &address, sizeof(address)); + port = htons(m_private_port+1); + memcpy(&m_sendBuffer[IPV4_SRC_PORT_OFFSET], &port, sizeof(port)); + + //make sure the FIN flag is not set, otherwise we will get a NAT miss + memcpy(&m_sendBuffer[IPV4_TCP_FLAGS_OFFSET],&flags , sizeof(flags)); + return true; + }// ModifyPacktes () + + virtual bool SendPackets() + { + bool isSuccess = false; + + // Send first packet + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) + { + LOG_MSG_ERROR("SendData failure.\n"); + return false; + } + + LOG_MSG_DEBUG("sent successfully one packet\n"); + return true; + } + + virtual bool ReceivePacketsAndCompare() + { + size_t receivedSize = 0; + bool isSuccess = true; + struct ipa3_hw_pkt_status_hw_v5_5 *status = NULL; + + // Receive results + Byte *rxBuff1 = new Byte[0x400]; + + if (NULL == rxBuff1) + { + LOG_MSG_ERROR("Memory allocation error.\n"); + return false; + } + + receivedSize = m_consumer.ReceiveData(rxBuff1, 0x400); + LOG_MSG_DEBUG("Received %zu bytes on %s.\n", receivedSize, m_consumer.m_fromChannelName.c_str()); + + // Compare results + if (!CompareResultVsGolden_w_Status(m_sendBuffer, m_sendSize, rxBuff1, receivedSize)) + { + printf("Comparison of Buffer0 Failed!\n"); + isSuccess = false; + } + + status = (struct ipa3_hw_pkt_status_hw_v5_5 *)rxBuff1; + if (!status->nat_exc_suppress) + { + printf("NAT Suppression not hit!\n"); + isSuccess = false; + } + + char recievedBuffer[256] = { 0 }; + char SentBuffer[256] = { 0 }; + size_t j; + + for (j = 0; j < m_sendSize; j++) + snprintf(&SentBuffer[3 * j], sizeof(SentBuffer) - (3 * j + 1), " %02X", m_sendBuffer[j]); + for (j = 0; j < receivedSize; j++) + snprintf(&recievedBuffer[3 * j], sizeof(recievedBuffer) - (3 * j + 1), " %02X", rxBuff1[j]); + LOG_MSG_STACK("sent Value1 (%zu)\n%s\n, Received Value1(%zu)\n%s\n", m_sendSize, SentBuffer, receivedSize, recievedBuffer); + + delete[] rxBuff1; + + return isSuccess; + } +}; + +/*---------------------------------------------------------------------------*/ +/* Test021: Single PDN dst NAT test with NAT suppresssion */ +/* NOTE: other classes are derived from this class - change carefully */ +/*---------------------------------------------------------------------------*/ +class IpaNatBlockTest021 : public IpaNatBlockTestFixture +{ +public: + IpaNatBlockTest021() + { + m_name = "IpaNatBlockTest021"; + m_description = + "NAT block test 002 - single PDN dst NAT test with NAT suppression \ + 1. Generate and commit three routing tables (only one is used). \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit one filtering rule: (DST & Mask Match). \ + action go to dst NAT \ + All DST_IP == (192.23.22.1 & 0.255.255.255)traffic goes to NAT block (public IP filtering) \ + 3. generate and commit one NAT rule: \ + public ip 192.23.22.1 --> private ip 194.23.22.1. \ + 4. Send packet not matching with NAT entry.\n"; + m_private_ip = 0xC2171601; /* 194.23.22.1 */ + m_private_port = 5678; + m_public_ip = 0xC0171601; /* "192.23.22.1" */ + m_public_port = 9050; + m_target_ip = 0xC1171601; /* 193.23.22.1 */ + m_target_port = 1234; + Register(*this); + } + + virtual bool Setup() + { + return IpaNatBlockTestFixture::Setup(false, true); + } + + virtual bool AddRules() + { + LOG_MSG_DEBUG("Entering\n"); + + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + struct ipa_ioc_get_rt_tbl routing_table0; + + if (!CreateThreeIPv4BypassRoutingTables(bypass0, bypass1, bypass2)) + { + LOG_MSG_ERROR("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + + LOG_MSG_DEBUG("CreateThreeBypassRoutingTables completed successfully\n"); + routing_table0.ip = IPA_IP_v4; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + LOG_MSG_ERROR("m_routing.GetRoutingTable(&routing_table0=0x%p) Failed.\n", &routing_table0); + return false; + } + LOG_MSG_DEBUG("%s route table handle = %u\n", bypass0, routing_table0.hdl); + + /* Setup NAT Exception routing table. */ + if (!m_routing.SetNatConntrackExcRoutingTable(routing_table0.hdl, true)) + { + LOG_MSG_ERROR("m_routing.SetNatConntrackExcRoutingTable(routing_table0 hdl=%d) Failed.\n", + routing_table0.hdl); + return false; + } + + IPAFilteringTable FilterTable0; + struct ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v4, IPA_CLIENT_TEST_PROD, false, 3); + LOG_MSG_DEBUG("FilterTable*.Init Completed Successfully..\n"); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1, flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl = -1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action = IPA_PASS_TO_DST_NAT; + flt_rule_entry.rule.rt_tbl_hdl = routing_table0.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + flt_rule_entry.rule.attrib.u.v4.dst_addr_mask = 0x00FFFFFF; // Mask + flt_rule_entry.rule.attrib.u.v4.dst_addr = m_public_ip; // Filter DST_IP == 192.23.22.1 + flt_rule_entry.rule.pdn_idx = 0; + flt_rule_entry.rule.set_metadata = 0; + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + LOG_MSG_ERROR("Error Adding Rule to Filter Table, aborting...\n"); + return false; + } + else + { + LOG_MSG_DEBUG("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl, FilterTable0.ReadRuleFromTable(0)->status); + } + + //NAT table and rules creation + int total_entries = 20; + int ret; + ipa_nat_ipv4_rule ipv4_rule; + uint32_t pub_ip_add = m_public_ip; + + ret = ipa_nat_add_ipv4_tbl(pub_ip_add, m_mem_type, total_entries, &m_tbl_hdl); + if (ret) { + LOG_MSG_ERROR("Leaving, failed creating NAT table\n"); + return false; + } + + LOG_MSG_DEBUG("nat table added, hdl %d, public ip 0x%X\n", m_tbl_hdl, + pub_ip_add); + + ipv4_rule.target_ip = m_target_ip; + ipv4_rule.target_port = m_target_port; + ipv4_rule.private_ip = m_private_ip; + ipv4_rule.private_port = m_private_port; + ipv4_rule.protocol = IPPROTO_TCP; + ipv4_rule.public_port = m_public_port; + ipv4_rule.pdn_index = 0; + + ret = ipa_nat_add_ipv4_rule(m_tbl_hdl, &ipv4_rule, &m_nat_rule_hdl1); + if (ret) { + LOG_MSG_ERROR("Leaving, failed adding NAT rule 0\n"); + return false; + } + + LOG_MSG_DEBUG("NAT rule added, hdl %d, data: 0x%X, %d, 0x%X, %d, %d, %d\n", + m_nat_rule_hdl1, ipv4_rule.target_ip, ipv4_rule.target_port, + ipv4_rule.private_ip, ipv4_rule.private_port, + ipv4_rule.protocol, ipv4_rule.public_port); + + LOG_MSG_DEBUG("Leaving\n"); + return true; + }// AddRules() + + virtual bool ModifyPackets() + { + uint32_t address; + uint16_t port; + char flags = 0x18; + + address = htonl(m_public_ip);//192.23.22.1 + memcpy(&m_sendBuffer[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + port = htons(m_public_port); + memcpy(&m_sendBuffer[IPV4_DST_PORT_OFFSET], &port, sizeof(port)); + + address = htonl(m_target_ip);/* 193.23.22.1 */ + memcpy(&m_sendBuffer[IPV4_SRC_ADDR_OFFSET], &address, sizeof(address)); + port = htons(m_target_port+1); + memcpy(&m_sendBuffer[IPV4_SRC_PORT_OFFSET], &port, sizeof(port)); + + //make sure the FIN flag is not set, otherwise we will get a NAT miss + memcpy(&m_sendBuffer[IPV4_TCP_FLAGS_OFFSET], &flags, sizeof(flags)); + + return true; + }// ModifyPacktes () + + virtual bool SendPackets() + { + bool isSuccess = false; + + // Send first packet + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) + { + LOG_MSG_ERROR("SendData failure.\n"); + return false; + } + + LOG_MSG_DEBUG("sent successfully one packet\n"); + return true; + } + + virtual bool ReceivePacketsAndCompare() + { + size_t receivedSize = 0; + bool isSuccess = true; + + // Receive results + Byte *rxBuff1 = new Byte[0x400]; + + if (NULL == rxBuff1) + { + LOG_MSG_ERROR("Memory allocation error.\n"); + return false; + } + + receivedSize = m_consumer.ReceiveData(rxBuff1, 0x400); + LOG_MSG_DEBUG("Received %zu bytes on %s.\n", receivedSize, m_consumer.m_fromChannelName.c_str()); + + // Compare results + if (!CompareResultVsGolden(m_sendBuffer, m_sendSize, rxBuff1, receivedSize)) + { + printf("Comparison of Buffer0 Failed!\n"); + isSuccess = false; + } + + char recievedBuffer[256] = { 0 }; + char SentBuffer[256] = { 0 }; + size_t j; + + for (j = 0; j < m_sendSize; j++) + snprintf(&SentBuffer[3 * j], sizeof(SentBuffer) - (3 * j + 1), " %02X", m_sendBuffer[j]); + for (j = 0; j < receivedSize; j++) + snprintf(&recievedBuffer[3 * j], sizeof(recievedBuffer) - (3 * j + 1), " %02X", rxBuff1[j]); + LOG_MSG_STACK("sent Value1 (%zu)\n%s\n, Received Value1(%zu)\n%s\n", m_sendSize, SentBuffer, receivedSize, recievedBuffer); + + delete[] rxBuff1; + + return isSuccess; + } +}; + +/*---------------------------------------------------------------------------*/ +/* Test022: Single PDN dst NAT test with NAT suppresssion and status enabled */ +/* NOTE: other classes are derived from this class - change carefully */ +/*---------------------------------------------------------------------------*/ +class IpaNatBlockTest022 : public IpaNatBlockTestFixture +{ +public: + IpaNatBlockTest022() + { + m_name = "IpaNatBlockTest022"; + m_description = + "NAT block test 022 - single PDN dst NAT test with NAT suppression and status enabled \ + 1. Generate and commit three routing tables (only one is used). \ + Each table contains a single \"bypass\" rule (all data goes to output pipe 0, 1 and 2 (accordingly)) \ + 2. Generate and commit one filtering rule: (DST & Mask Match). \ + action go to dst NAT \ + All DST_IP == (192.23.22.1 & 0.255.255.255)traffic goes to NAT block (public IP filtering) \ + 3. generate and commit one NAT rule:\ + public ip 192.23.22.1 --> private ip 194.23.22.1. \ + 4. Send packet not matching with NAT entry.\n"; + m_private_ip = 0xC2171601; /* 194.23.22.1 */ + m_private_port = 5678; + m_public_ip = 0xC0171601; /* "192.23.22.1" */ + m_public_port = 9050; + m_target_ip = 0xC1171601; /* 193.23.22.1 */ + m_target_port = 1234; + Register(*this); + } + + virtual bool Setup() + { + return IpaNatBlockTestFixture::Setup(true, true); + } + + virtual bool AddRules() + { + LOG_MSG_DEBUG("Entering\n"); + + const char bypass0[20] = "Bypass0"; + const char bypass1[20] = "Bypass1"; + const char bypass2[20] = "Bypass2"; + struct ipa_ioc_get_rt_tbl routing_table0; + + if (!CreateThreeIPv4BypassRoutingTables(bypass0, bypass1, bypass2)) + { + LOG_MSG_ERROR("CreateThreeBypassRoutingTables Failed\n"); + return false; + } + + LOG_MSG_DEBUG("CreateThreeBypassRoutingTables completed successfully\n"); + routing_table0.ip = IPA_IP_v4; + strlcpy(routing_table0.name, bypass0, sizeof(routing_table0.name)); + if (!m_routing.GetRoutingTable(&routing_table0)) + { + LOG_MSG_ERROR("m_routing.GetRoutingTable(&routing_table0=0x%p) Failed.\n", &routing_table0); + return false; + } + LOG_MSG_DEBUG("%s route table handle = %u\n", bypass0, routing_table0.hdl); + + /* Setup NAT Exception routing table. */ + if (!m_routing.SetNatConntrackExcRoutingTable(routing_table0.hdl, true)) + { + LOG_MSG_ERROR("m_routing.SetNatConntrackExcRoutingTable(routing_table0 hdl=%d) Failed.\n", + routing_table0.hdl); + return false; + } + + IPAFilteringTable FilterTable0; + struct ipa_flt_rule_add flt_rule_entry; + FilterTable0.Init(IPA_IP_v4, IPA_CLIENT_TEST_PROD, false, 3); + LOG_MSG_DEBUG("FilterTable*.Init Completed Successfully..\n"); + + // Configuring Filtering Rule No.0 + FilterTable0.GeneratePresetRule(1, flt_rule_entry); + flt_rule_entry.at_rear = true; + flt_rule_entry.flt_rule_hdl = -1; // return Value + flt_rule_entry.status = -1; // return value + flt_rule_entry.rule.action = IPA_PASS_TO_DST_NAT; + flt_rule_entry.rule.rt_tbl_hdl = routing_table0.hdl; //put here the handle corresponding to Routing Rule 1 + flt_rule_entry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + flt_rule_entry.rule.attrib.u.v4.dst_addr_mask = 0x00FFFFFF; // Mask + flt_rule_entry.rule.attrib.u.v4.dst_addr = m_public_ip; // Filter DST_IP == 192.23.22.1 + flt_rule_entry.rule.pdn_idx = 0; + flt_rule_entry.rule.set_metadata = 0; + if ( + ((uint8_t)-1 == FilterTable0.AddRuleToTable(flt_rule_entry)) || + !m_filtering.AddFilteringRule(FilterTable0.GetFilteringTable()) + ) + { + LOG_MSG_ERROR("Error Adding Rule to Filter Table, aborting...\n"); + return false; + } + else + { + LOG_MSG_DEBUG("flt rule hdl0=0x%x, status=0x%x\n", FilterTable0.ReadRuleFromTable(0)->flt_rule_hdl, FilterTable0.ReadRuleFromTable(0)->status); + } + + //NAT table and rules creation + int total_entries = 20; + int ret; + ipa_nat_ipv4_rule ipv4_rule; + uint32_t pub_ip_add = m_public_ip; + + ret = ipa_nat_add_ipv4_tbl(pub_ip_add, m_mem_type, total_entries, &m_tbl_hdl); + if (ret) { + LOG_MSG_ERROR("Leaving, failed creating NAT table\n"); + return false; + } + + LOG_MSG_DEBUG("nat table added, hdl %d, public ip 0x%X\n", m_tbl_hdl, + pub_ip_add); + + ipv4_rule.target_ip = m_target_ip; + ipv4_rule.target_port = m_target_port; + ipv4_rule.private_ip = m_private_ip; + ipv4_rule.private_port = m_private_port; + ipv4_rule.protocol = IPPROTO_TCP; + ipv4_rule.public_port = m_public_port; + ipv4_rule.pdn_index = 0; + + ret = ipa_nat_add_ipv4_rule(m_tbl_hdl, &ipv4_rule, &m_nat_rule_hdl1); + if (ret) { + LOG_MSG_ERROR("Leaving, failed adding NAT rule 0\n"); + return false; + } + + LOG_MSG_DEBUG("NAT rule added, hdl %d, data: 0x%X, %d, 0x%X, %d, %d, %d\n", + m_nat_rule_hdl1, ipv4_rule.target_ip, ipv4_rule.target_port, + ipv4_rule.private_ip, ipv4_rule.private_port, + ipv4_rule.protocol, ipv4_rule.public_port); + + LOG_MSG_DEBUG("Leaving\n"); + return true; + }// AddRules() + + virtual bool ModifyPackets() + { + uint32_t address; + uint16_t port; + char flags = 0x18; + + address = htonl(m_public_ip);//192.23.22.1 + memcpy(&m_sendBuffer[IPV4_DST_ADDR_OFFSET], &address, sizeof(address)); + port = htons(m_public_port); + memcpy(&m_sendBuffer[IPV4_DST_PORT_OFFSET], &port, sizeof(port)); + + address = htonl(m_target_ip);/* 193.23.22.1 */ + memcpy(&m_sendBuffer[IPV4_SRC_ADDR_OFFSET], &address, sizeof(address)); + port = htons(m_target_port+1); + memcpy(&m_sendBuffer[IPV4_SRC_PORT_OFFSET], &port, sizeof(port)); + + //make sure the FIN flag is not set, otherwise we will get a NAT miss + memcpy(&m_sendBuffer[IPV4_TCP_FLAGS_OFFSET], &flags, sizeof(flags)); + + return true; + }// ModifyPacktes () + + virtual bool SendPackets() + { + bool isSuccess = false; + + // Send first packet + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) + { + LOG_MSG_ERROR("SendData failure.\n"); + return false; + } + + LOG_MSG_DEBUG("sent successfully one packet\n"); + return true; + } + + virtual bool ReceivePacketsAndCompare() + { + size_t receivedSize = 0; + bool isSuccess = true; + struct ipa3_hw_pkt_status_hw_v5_5 *status = NULL; + + // Receive results + Byte *rxBuff1 = new Byte[0x400]; + + if (NULL == rxBuff1) + { + LOG_MSG_ERROR("Memory allocation error.\n"); + return false; + } + + receivedSize = m_consumer.ReceiveData(rxBuff1, 0x400); + LOG_MSG_DEBUG("Received %zu bytes on %s.\n", receivedSize, m_consumer.m_fromChannelName.c_str()); + + // Compare results + if (!CompareResultVsGolden_w_Status(m_sendBuffer, m_sendSize, rxBuff1, receivedSize)) + { + printf("Comparison of Buffer0 Failed!\n"); + isSuccess = false; + } + + status = (struct ipa3_hw_pkt_status_hw_v5_5 *)rxBuff1; + if (!status->nat_exc_suppress) + { + printf("NAT Suppression not hit!\n"); + isSuccess = false; + } + + char recievedBuffer[256] = { 0 }; + char SentBuffer[256] = { 0 }; + size_t j; + + for (j = 0; j < m_sendSize; j++) + snprintf(&SentBuffer[3 * j], sizeof(SentBuffer) - (3 * j + 1), " %02X", m_sendBuffer[j]); + for (j = 0; j < receivedSize; j++) + snprintf(&recievedBuffer[3 * j], sizeof(recievedBuffer) - (3 * j + 1), " %02X", rxBuff1[j]); + LOG_MSG_STACK("sent Value1 (%zu)\n%s\n, Received Value1(%zu)\n%s\n", m_sendSize, SentBuffer, receivedSize, recievedBuffer); + + delete[] rxBuff1; + + return isSuccess; + } +}; + + +static class IpaNatBlockTest001 IpaNatBlockTest001;//single PDN src NAT test +static class IpaNatBlockTest002 IpaNatBlockTest002;//single PDN dst NAT test +static class IpaNatBlockTest003 IpaNatBlockTest003;//multi PDN (tuple) src NAT test +static class IpaNatBlockTest004 IpaNatBlockTest004;//multi PDN (tuple) dst NAT test +static class IpaNatBlockTest005 IpaNatBlockTest005;//single PDN src NAT test - src metadata replacement +static class IpaNatBlockTest006 IpaNatBlockTest006;//single PDN dst NAT test - dst metadata replacement +static class IpaNatBlockTest007 IpaNatBlockTest007;//hashable routing rule with dst NAT test +static class IpaNatBlockTest008 IpaNatBlockTest008;//Multi PDN src NAT test match PDN by input from filtering block +static class IpaNatBlockTest009 IpaNatBlockTest009;//single PDN src NAT rule deletion test +static class IpaNatBlockTest010 IpaNatBlockTest010;//single PDN dst NAT rule deletion test +static class IpaNatBlockTest011 IpaNatBlockTest011;//Multi PDN src NAT - MAX number of PDNs test +static class IpaNatBlockTest012 IpaNatBlockTest012;//Single PDN dst NAT test expansion table usage +static class IpaNatBlockTest013 IpaNatBlockTest013;//Single PDN dst NAT test expansion table delete test +static class IpaNatBlockTest014 IpaNatBlockTest014;//single PDN src NAT zero PDN test +static class IpaNatBlockTest015 IpaNatBlockTest015;//single PDN src NAT test - send two packets that will hit the same rule +static class IpaNatBlockTest016 IpaNatBlockTest016;//single PDN dst NAT test - send two packets that will hit the same rule +static class IpaNatBlockTest017 IpaNatBlockTest017;//multi PDN (tuple) src NAT test - identical private IPs different ports +static class IpaNatBlockTest018 IpaNatBlockTest018;//multi PDN (tuple) dst NAT test - identical private IPs different ports +static class IpaNatBlockTest019 IpaNatBlockTest019;//Single PDN SRC NAT suppression test +static class IpaNatBlockTest020 IpaNatBlockTest020;//Single PDN SRC NAT suppression test with status +static class IpaNatBlockTest021 IpaNatBlockTest021;//Single PDN DST NAT suppression test +static class IpaNatBlockTest022 IpaNatBlockTest022;//Single PDN DST NAT suppression test with status diff --git a/qcom/opensource/dataipa/kernel-tests/Pipe.cpp b/qcom/opensource/dataipa/kernel-tests/Pipe.cpp new file mode 100644 index 0000000000..84697e7285 --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/Pipe.cpp @@ -0,0 +1,729 @@ +/* + * Copyright (c) 2017-2018,2020 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "Pipe.h" +#include "TestsUtils.h" + +////////////////////////////////////////////////////////////////////////////////////////////////////////// +//Do not change those default values due to the fact that some test may relay on those default values. +//In case you need a change of the field do this in a derived class. + +//Dest MAC(6 bytes) Src MAC(6 Bytes) EtherType(2 Bytes) +unsigned char Pipe::m_pUsbHeader[] = { 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xB1, 0xB2, + 0xB3, 0xB4, 0xB5, 0xB6, 0xC1, 0xC2 }; +unsigned char Pipe::m_pA2NDUNHeader[] = + { 0xA1, 0xA2, 0xA3, 0xA4, 0xB1, 0xB2, 0xC1, 0xC2 }; +//unsigned char Pipe::m_pA2DUNHeader[] = {}; +//unsigned char Pipe::m_pQ6LANHeader[] = {}; + +////////////////////////////////////////////////////////////////////////////////////////////////////////// + +Pipe::Pipe(enum ipa_client_type nClientType, + IPATestConfiguration eConfiguration) : + m_Fd(-1), m_nHeaderLengthRemove(0), + m_nHeaderLengthAdd(0), m_pHeader(NULL), m_pInodePath(NULL), + m_bInitialized(false), m_ExceptionPipe(false) { + m_nClientType = nClientType; + m_eConfiguration = eConfiguration; +} + +Pipe::Pipe(IPATestConfiguration eConfiguration) : + m_Fd(-1), m_nHeaderLengthRemove(0), + m_nHeaderLengthAdd(0), m_pHeader(NULL), m_pInodePath(NULL), + m_bInitialized(false), m_ExceptionPipe(true) { + m_eConfiguration = eConfiguration; +} + +////////////////////////////////////////////////////////////////////////////////////////////////////////// + +Pipe::~Pipe() { + //Nothing to be done at this point... +} + +////////////////////////////////////////////////////////////////////////////////////////////////////////// + +bool Pipe::Init() { + int tries_cnt = 1; + SetSpecificClientParameters(m_nClientType, m_eConfiguration); + //By examining the Client type we will map the inode device name + while (tries_cnt <= 10000) { + m_Fd = open(m_pInodePath, O_RDWR); + if (-1 != m_Fd) + break; + + // Sleep for 5 msec + usleep(5000); + ++tries_cnt; + } + LOG_MSG_DEBUG("open retries_cnt=%d\n", tries_cnt); + if (-1 == m_Fd) { + LOG_MSG_ERROR("Failed to open %s", m_pInodePath); + return false; + } + m_bInitialized = true; + return true; +} + +////////////////////////////////////////////////////////////////////////////////////////////////////////// + +void Pipe::Destroy() { + if (false == m_bInitialized) { + LOG_MSG_ERROR("Pipe is being used without being initialized!"); + return; + } + close(m_Fd); +} + +////////////////////////////////////////////////////////////////////////////////////////////////////////// + +int Pipe::Send(unsigned char * pBuffer, size_t nBytesToSend) { + if (false == m_bInitialized) { + LOG_MSG_ERROR("Pipe is being used without being initialized!"); + return 0; + } + size_t nBytesWritten = 0; + nBytesWritten = write(m_Fd, pBuffer, nBytesToSend); + return nBytesWritten; +} + +////////////////////////////////////////////////////////////////////////////////////////////////////////// + +int Pipe::AddHeaderAndSend(unsigned char * pIpPacket, size_t nIpPacketSize) { + int retval; + + if (false == m_bInitialized) { + LOG_MSG_ERROR("Pipe is being used without being initialized!"); + return 0; + } + size_t nBytesToWrite = nIpPacketSize + m_nHeaderLengthAdd; + //Allocate new buffer for the Header and IP packet: + unsigned char *pLinkLayerAndIpPacket = new unsigned char[nBytesToWrite]; + if (!pLinkLayerAndIpPacket) { + LOG_MSG_ERROR("Memory allocation failure."); + return 0; + } + + //put the header first: + memcpy(pLinkLayerAndIpPacket, m_pHeader, m_nHeaderLengthAdd); + //Then add the IP packet: + memcpy(pLinkLayerAndIpPacket + m_nHeaderLengthAdd, pIpPacket, + nIpPacketSize); + //Call the Send method which will send the new created buffer(which contains the IP packet with the Header): + retval = Send(pLinkLayerAndIpPacket, nBytesToWrite); + delete[] pLinkLayerAndIpPacket; + + return retval; +} + +////////////////////////////////////////////////////////////////////////////////////////////////////////// + +int Pipe::Receive(unsigned char *pBuffer, size_t nBytesToReceive) { + if (false == m_bInitialized) { + LOG_MSG_ERROR("Pipe is being used without being initialized!"); + return 0; + } + size_t nBytesRead = 0; + nBytesRead = read(m_Fd, (void*) pBuffer, nBytesToReceive); + return nBytesRead; +} + +////////////////////////////////////////////////////////////////////////////////////////////////////////// + +int Pipe::ReceiveAndRemoveHeader(unsigned char *pIpPacket, size_t nIpPacketSize) { + if (false == m_bInitialized) { + LOG_MSG_ERROR("Pipe is being used without being initialized!"); + return 0; + } + size_t nBytesToRead = nIpPacketSize + m_nHeaderLengthRemove; + unsigned char *pPacket = new unsigned char[nBytesToRead]; + if (!pPacket) { + LOG_MSG_ERROR("Memory allocation failure."); + return 0; + } + size_t nReceivedBytes = Receive(pPacket, nBytesToRead); + if (nReceivedBytes != nBytesToRead) { + LOG_MSG_ERROR("Pipe was asked to receive an IP packet " + "of size %d, however only %d bytes were read " + "while the header size is %d", + nIpPacketSize, + nReceivedBytes, + m_nHeaderLengthRemove); + delete[] pPacket; + return nReceivedBytes - m_nHeaderLengthRemove; + } + + memcpy(pIpPacket, pPacket + m_nHeaderLengthRemove, nIpPacketSize); + delete[] pPacket; + + return (nReceivedBytes - m_nHeaderLengthRemove); +} + +////////////////////////////////////////////////////////////////////////////////////////////////////////// + +enum ipa_client_type Pipe::GetClientType() { + if (false == m_bInitialized) { + LOG_MSG_ERROR("Pipe is being used without being initialized!"); + return IPA_CLIENT_HSIC1_PROD; + } + return m_nClientType; +} + +////////////////////////////////////////////////////////////////////////////////////////////////////////// + +void Pipe::SetSpecificClientParameters( + enum ipa_client_type nClientType, + IPATestConfiguration eConfiguration) { + switch (eConfiguration) { + case IPA_TEST_CONFIFURATION_0: + break; + case IPA_TEST_CONFIFURATION_1: + switch (nClientType) { + case (IPA_CLIENT_TEST_PROD): + m_pInodePath = CONFIG_1_FROM_USB1_TO_IPA_DMA; + m_nHeaderLengthAdd = sizeof(m_pUsbHeader); + m_nHeaderLengthRemove = sizeof(m_pUsbHeader); + m_pHeader = m_pUsbHeader; + LOG_MSG_INFO("Setting parameters for IPA_CLIENT_TEST_PROD "); + break; + case (IPA_CLIENT_TEST_CONS): + m_pInodePath = CONFIG_1_FROM_IPA_TO_USB1_DMA; + m_nHeaderLengthAdd = sizeof(m_pUsbHeader); + m_nHeaderLengthRemove = sizeof(m_pUsbHeader); + m_pHeader = m_pUsbHeader; + LOG_MSG_INFO("Setting parameters for IPA_CLIENT_TEST_CONS"); + break; + default: + LOG_MSG_ERROR("IPA_TEST_CONFIFURATION_1 switch in default " + "nClientType = %d is not supported ", nClientType); + break; + } + break; + case IPA_TEST_CONFIFURATION_2: + switch (nClientType) { + case (IPA_CLIENT_TEST_PROD): + m_pInodePath = CONFIG_2_FROM_USB_TO_IPA; + m_nHeaderLengthAdd = sizeof(m_pUsbHeader); + m_nHeaderLengthRemove = sizeof(m_pUsbHeader); + m_pHeader = m_pUsbHeader; + LOG_MSG_INFO("Setting parameters for IPA_CLIENT_TEST_PROD"); + break; + case (IPA_CLIENT_TEST2_CONS): + m_pInodePath = CONFIG_2_FROM_IPA_TO_A2_NDUN; + m_nHeaderLengthAdd = sizeof(m_pA2NDUNHeader); + m_nHeaderLengthRemove = sizeof(m_pA2NDUNHeader); + m_pHeader = m_pA2NDUNHeader; + LOG_MSG_INFO("Setting parameters for IPA_CLIENT_TEST2_CONS"); + break; + default: + LOG_MSG_ERROR("IPA_TEST_CONFIFURATION_2 switch in default " + "nClientType = %d is not supported ", nClientType); + break; + } + break; + case IPA_TEST_CONFIFURATION_3: + switch (nClientType) { + case IPA_CLIENT_TEST2_PROD: + m_pInodePath = CONFIG_3_FROM_A2_NDUN_TO_IPA; + m_nHeaderLengthAdd = sizeof(m_pA2NDUNHeader); + m_nHeaderLengthRemove = sizeof(m_pA2NDUNHeader); + m_pHeader = m_pA2NDUNHeader; + LOG_MSG_INFO("Setting parameters for IPA_CLIENT_TEST2_PROD"); + break; + case IPA_CLIENT_TEST_CONS: + m_pInodePath = CONFIG_3_FROM_IPA_TO_USB1; + m_nHeaderLengthAdd = sizeof(m_pUsbHeader); + m_nHeaderLengthRemove = sizeof(m_pUsbHeader); + m_pHeader = m_pUsbHeader; + LOG_MSG_INFO("Setting parameters for IPA_CLIENT_TEST_CONS"); + break; + case IPA_CLIENT_TEST2_CONS: + m_pInodePath = CONFIG_3_FROM_IPA_TO_A2_NDUN; + m_nHeaderLengthAdd = sizeof(m_pA2NDUNHeader); + m_nHeaderLengthRemove = sizeof(m_pA2NDUNHeader); + m_pHeader = m_pA2NDUNHeader; + LOG_MSG_INFO("Setting parameters for IPA_CLIENT_TEST2_CONS"); + break; + case IPA_CLIENT_TEST4_CONS: + //TODO add when applicable + m_pInodePath = CONFIG_3_FROM_IPA_TO_Q6_LAN; + m_nHeaderLengthAdd = 0; + m_nHeaderLengthRemove = 0; + m_pHeader = 0; + LOG_MSG_INFO("IPA_CLIENT_TEST4_CONS is not supported yet"); + break; + default: + LOG_MSG_INFO("IPA_TEST_CONFIFURATION_3 switch in default " + "nClientType = %d is not supported ", nClientType); + break; + } + break; + case IPA_TEST_CONFIFURATION_7: + if (m_ExceptionPipe) { + m_pInodePath = CONFIG_7_FROM_IPA_TO_A5_EXCEPTION; + m_nHeaderLengthAdd = 0; //No send + m_nHeaderLengthRemove = 8; //A5Mux header size without retained source header + m_pHeader = NULL; //No header to send + LOG_MSG_INFO("Setting parameters for A5_Exception "); + break; + } + + if (nClientType == IPA_CLIENT_TEST_PROD) { + m_pInodePath = CONFIG_7_FROM_USB1_TO_IPA; + m_nHeaderLengthAdd = 0; + m_nHeaderLengthRemove = 0; + m_pHeader = NULL; + LOG_MSG_INFO( + "Setting parameters for FROM_USB1_TO_IPA - no header addition/removal"); + } else { + LOG_MSG_INFO("IPA_TEST_CONFIFURATION_7 switch in default " + "nClientType = %d is not supported ", nClientType); + } + break; + case IPA_TEST_CONFIGURATION_8: + switch(nClientType) + { + case (IPA_CLIENT_TEST_PROD): + m_pInodePath = CONFIG_8_DEAGG_TO_IPA_NO_AGG; + m_nHeaderLengthAdd = sizeof(m_pUsbHeader); + m_nHeaderLengthRemove = sizeof(m_pUsbHeader); + m_pHeader = m_pUsbHeader; + LOG_MSG_INFO("Setting parameters for IPA_CLIENT_TEST_PROD "); + break; + case (IPA_CLIENT_TEST_CONS): + m_pInodePath = CONFIG_8_FROM_IPA_AGG; + m_nHeaderLengthAdd = sizeof(m_pUsbHeader); + m_nHeaderLengthRemove = sizeof(m_pUsbHeader); + m_pHeader = m_pUsbHeader; + LOG_MSG_INFO("Setting parameters for IPA_CLIENT_TEST_CONS"); + break; + case (IPA_CLIENT_TEST3_PROD): + m_pInodePath = CONFIG_8_NO_AGG_TO_IPA_AGG; + m_nHeaderLengthAdd = sizeof(m_pUsbHeader); + m_nHeaderLengthRemove = sizeof(m_pUsbHeader); + m_pHeader = m_pUsbHeader; + LOG_MSG_INFO("Setting parameters for IPA_CLIENT_TEST3_PROD "); + break; + case (IPA_CLIENT_TEST3_CONS): + m_pInodePath = CONFIG_8_FROM_IPA_NO_AGG; + m_nHeaderLengthAdd = sizeof(m_pUsbHeader); + m_nHeaderLengthRemove = sizeof(m_pUsbHeader); + m_pHeader = m_pUsbHeader; + LOG_MSG_INFO("Setting parameters for IPA_CLIENT_TEST3_CONS"); + break; + case (IPA_CLIENT_TEST2_PROD): + m_pInodePath = CONFIG_8_DEAGG_TO_IPA_AGG; + m_nHeaderLengthAdd = sizeof(m_pUsbHeader); + m_nHeaderLengthRemove = sizeof(m_pUsbHeader); + m_pHeader = m_pUsbHeader; + LOG_MSG_INFO("Setting parameters for IPA_CLIENT_TEST2_PROD"); + break; + case (IPA_CLIENT_TEST2_CONS): + m_pInodePath = CONFIG_8_DEAGG_FROM_IPA_AGG; + m_nHeaderLengthAdd = sizeof(m_pUsbHeader); + m_nHeaderLengthRemove = sizeof(m_pUsbHeader); + m_pHeader = m_pUsbHeader; + LOG_MSG_INFO("Setting parameters for IPA_CLIENT_TEST2_CONS"); + break; + case (IPA_CLIENT_TEST4_PROD): + m_pInodePath = CONFIG_8_NO_AGG_TO_IPA_AGG_TIME; + m_nHeaderLengthAdd = sizeof(m_pUsbHeader); + m_nHeaderLengthRemove = sizeof(m_pUsbHeader); + m_pHeader = m_pUsbHeader; + LOG_MSG_INFO("Setting parameters for IPA_CLIENT_TEST4_PROD"); + break; + default: + LOG_MSG_ERROR("IPA_TEST_CONFIFURATION_8 switch in default " + "nClientType = %d is not supported ", + nClientType); + break; + } + break; + case IPA_TEST_CONFIGURATION_9: + switch(nClientType) + { + case (IPA_CLIENT_TEST_PROD): + m_pInodePath = CONFIG_9_DEAGG_TO_IPA_NO_AGG; + m_nHeaderLengthAdd = sizeof(m_pUsbHeader); + m_nHeaderLengthRemove = sizeof(m_pUsbHeader); + m_pHeader = m_pUsbHeader; + LOG_MSG_INFO("Setting parameters for IPA_CLIENT_TEST_PROD "); + break; + case (IPA_CLIENT_TEST_CONS): + m_pInodePath = CONFIG_9_FROM_IPA_AGG; + m_nHeaderLengthAdd = sizeof(m_pUsbHeader); + m_nHeaderLengthRemove = sizeof(m_pUsbHeader); + m_pHeader = m_pUsbHeader; + LOG_MSG_INFO("Setting parameters for IPA_CLIENT_TEST_CONS"); + break; + case (IPA_CLIENT_TEST3_PROD): + m_pInodePath = CONFIG_9_NO_AGG_TO_IPA_AGG; + m_nHeaderLengthAdd = sizeof(m_pUsbHeader); + m_nHeaderLengthRemove = sizeof(m_pUsbHeader); + m_pHeader = m_pUsbHeader; + LOG_MSG_INFO("Setting parameters for IPA_CLIENT_TEST3_PROD "); + break; + case (IPA_CLIENT_TEST3_CONS): + m_pInodePath = CONFIG_9_FROM_IPA_NO_AGG; + m_nHeaderLengthAdd = sizeof(m_pUsbHeader); + m_nHeaderLengthRemove = sizeof(m_pUsbHeader); + m_pHeader = m_pUsbHeader; + LOG_MSG_INFO("Setting parameters for IPA_CLIENT_TEST3_CONS"); + break; + case (IPA_CLIENT_TEST2_PROD): + m_pInodePath = CONFIG_9_DEAGG_TO_IPA_AGG; + m_nHeaderLengthAdd = sizeof(m_pUsbHeader); + m_nHeaderLengthRemove = sizeof(m_pUsbHeader); + m_pHeader = m_pUsbHeader; + LOG_MSG_INFO("Setting parameters for IPA_CLIENT_TEST2_PROD"); + break; + case (IPA_CLIENT_TEST2_CONS): + m_pInodePath = CONFIG_9_DEAGG_FROM_IPA_AGG; + m_nHeaderLengthAdd = sizeof(m_pUsbHeader); + m_nHeaderLengthRemove = sizeof(m_pUsbHeader); + m_pHeader = m_pUsbHeader; + LOG_MSG_INFO("Setting parameters for IPA_CLIENT_TEST2_CONS"); + break; + case (IPA_CLIENT_TEST4_PROD): + m_pInodePath = CONFIG_9_NO_AGG_TO_IPA_AGG_TIME; + m_nHeaderLengthAdd = sizeof(m_pUsbHeader); + m_nHeaderLengthRemove = sizeof(m_pUsbHeader); + m_pHeader = m_pUsbHeader; + LOG_MSG_INFO("Setting parameters for IPA_CLIENT_TEST4_PROD"); + break; + default: + LOG_MSG_ERROR("IPA_TEST_CONFIFURATION_9 switch in default " + "nClientType = %d is not supported ", + nClientType); + break; + } + break; + case IPA_TEST_CONFIGURATION_10: + switch(nClientType) + { + case (IPA_CLIENT_TEST_PROD): + m_pInodePath = CONFIG_10_TO_IPA_AGG_ZERO_LIMITS; + m_nHeaderLengthAdd = sizeof(m_pUsbHeader); + m_nHeaderLengthRemove = sizeof(m_pUsbHeader); + m_pHeader = m_pUsbHeader; + LOG_MSG_INFO("Setting parameters for IPA_CLIENT_TEST_PROD"); + break; + case (IPA_CLIENT_TEST_CONS): + m_pInodePath = CONFIG_10_FROM_IPA_AGG_ZERO_LIMITS; + m_nHeaderLengthAdd = sizeof(m_pUsbHeader); + m_nHeaderLengthRemove = sizeof(m_pUsbHeader); + m_pHeader = m_pUsbHeader; + LOG_MSG_INFO("Setting parameters for IPA_CLIENT_TEST_CONS"); + break; + default: + LOG_MSG_ERROR("IPA_TEST_CONFIFURATION_10 switch in default " + "nClientType = %d is not supported ", + nClientType); + break; + } + break; + case IPA_TEST_CONFIGURATION_11: + switch(nClientType) + { + case (IPA_CLIENT_TEST_PROD): + m_pInodePath = CONFIG_11_TO_IPA; + m_nHeaderLengthAdd = sizeof(m_pUsbHeader); + m_nHeaderLengthRemove = sizeof(m_pUsbHeader); + m_pHeader = m_pUsbHeader; + LOG_MSG_INFO("Setting parameters for IPA_CLIENT_TEST_PROD"); + break; + case (IPA_CLIENT_TEST2_CONS): + m_pInodePath = CONFIG_11_FROM_IPA_AGG; + m_nHeaderLengthAdd = sizeof(m_pUsbHeader); + m_nHeaderLengthRemove = sizeof(m_pUsbHeader); + m_pHeader = m_pUsbHeader; + LOG_MSG_INFO("Setting parameters for IPA_CLIENT_TEST2_CONS"); + break; + case (IPA_CLIENT_TEST2_PROD): + m_pInodePath = CONFIG_11_TO_IPA_DEAGG; + m_nHeaderLengthAdd = sizeof(m_pUsbHeader); + m_nHeaderLengthRemove = sizeof(m_pUsbHeader); + m_pHeader = m_pUsbHeader; + LOG_MSG_INFO("Setting parameters for IPA_CLIENT_TEST2_PROD"); + break; + case (IPA_CLIENT_TEST3_CONS): + m_pInodePath = CONFIG_11_FROM_IPA; + m_nHeaderLengthAdd = sizeof(m_pUsbHeader); + m_nHeaderLengthRemove = sizeof(m_pUsbHeader); + m_pHeader = m_pUsbHeader; + LOG_MSG_INFO("Setting parameters for IPA_CLIENT_TEST3_CONS"); + break; + case (IPA_CLIENT_TEST_CONS): + m_pInodePath = CONFIG_11_FROM_IPA_AGG_TIME; + m_nHeaderLengthAdd = sizeof(m_pUsbHeader); + m_nHeaderLengthRemove = sizeof(m_pUsbHeader); + m_pHeader = m_pUsbHeader; + LOG_MSG_INFO("Setting parameters for IPA_CLIENT_TEST_CONS"); + break; + case (IPA_CLIENT_TEST4_CONS): + m_pInodePath = CONFIG_11_FROM_IPA_ZERO_LIMITS; + m_nHeaderLengthAdd = sizeof(m_pUsbHeader); + m_nHeaderLengthRemove = sizeof(m_pUsbHeader); + m_pHeader = m_pUsbHeader; + LOG_MSG_INFO("Setting parameters for IPA_CLIENT_TEST4_CONS"); + break; + default: + LOG_MSG_ERROR("IPA_TEST_CONFIFURATION_11 switch in default " + "nClientType = %d is not supported ", + nClientType); + break; + } + break; + case IPA_TEST_CONFIGURATION_12: + switch(nClientType) + { + case (IPA_CLIENT_TEST_PROD): + m_pInodePath = CONFIG_12_TO_IPA; + m_nHeaderLengthAdd = sizeof(m_pUsbHeader); + m_nHeaderLengthRemove = sizeof(m_pUsbHeader); + m_pHeader = m_pUsbHeader; + LOG_MSG_INFO("Setting parameters for IPA_CLIENT_TEST_PROD"); + break; + case (IPA_CLIENT_TEST2_CONS): + m_pInodePath = CONFIG_12_FROM_IPA_AGG; + m_nHeaderLengthAdd = sizeof(m_pUsbHeader); + m_nHeaderLengthRemove = sizeof(m_pUsbHeader); + m_pHeader = m_pUsbHeader; + LOG_MSG_INFO("Setting parameters for IPA_CLIENT_TEST2_CONS"); + break; + case (IPA_CLIENT_TEST2_PROD): + m_pInodePath = CONFIG_12_TO_IPA_DEAGG; + m_nHeaderLengthAdd = sizeof(m_pUsbHeader); + m_nHeaderLengthRemove = sizeof(m_pUsbHeader); + m_pHeader = m_pUsbHeader; + LOG_MSG_INFO("Setting parameters for IPA_CLIENT_TEST2_PROD"); + break; + case (IPA_CLIENT_TEST3_CONS): + m_pInodePath = CONFIG_12_FROM_IPA; + m_nHeaderLengthAdd = sizeof(m_pUsbHeader); + m_nHeaderLengthRemove = sizeof(m_pUsbHeader); + m_pHeader = m_pUsbHeader; + LOG_MSG_INFO("Setting parameters for IPA_CLIENT_TEST3_CONS"); + break; + case (IPA_CLIENT_TEST_CONS): + m_pInodePath = CONFIG_12_FROM_IPA_AGG_TIME; + m_nHeaderLengthAdd = sizeof(m_pUsbHeader); + m_nHeaderLengthRemove = sizeof(m_pUsbHeader); + m_pHeader = m_pUsbHeader; + LOG_MSG_INFO("Setting parameters for IPA_CLIENT_TEST_CONS"); + break; + case (IPA_CLIENT_TEST4_CONS): + m_pInodePath = CONFIG_12_FROM_IPA_ZERO_LIMITS; + m_nHeaderLengthAdd = sizeof(m_pUsbHeader); + m_nHeaderLengthRemove = sizeof(m_pUsbHeader); + m_pHeader = m_pUsbHeader; + LOG_MSG_INFO("Setting parameters for IPA_CLIENT_TEST4_CONS"); + break; + default: + LOG_MSG_ERROR("IPA_TEST_CONFIFURATION_12 switch in default " + "nClientType = %d is not supported ", + nClientType); + break; + } + break; + case IPA_TEST_CONFIGURATION_17: + switch(nClientType) + { + case (IPA_CLIENT_TEST_PROD): + m_pInodePath = CONFIG_17_TO_IPA; + m_nHeaderLengthAdd = sizeof(m_pUsbHeader); + m_nHeaderLengthRemove = sizeof(m_pUsbHeader); + m_pHeader = m_pUsbHeader; + LOG_MSG_INFO("Setting parameters for IPA_CLIENT_TEST_PROD "); + break; + case (IPA_CLIENT_TEST3_PROD): + m_pInodePath = CONFIG_17_TO_IPA_NO_HDR; + m_nHeaderLengthAdd = sizeof(m_pUsbHeader); + m_nHeaderLengthRemove = sizeof(m_pUsbHeader); + m_pHeader = m_pUsbHeader; + LOG_MSG_INFO("Setting parameters for IPA_CLIENT_TEST3_PROD "); + break; + case (IPA_CLIENT_TEST2_CONS): + m_pInodePath = CONFIG_17_FROM_IPA_AGG; + m_nHeaderLengthAdd = sizeof(m_pUsbHeader); + m_nHeaderLengthRemove = sizeof(m_pUsbHeader); + m_pHeader = m_pUsbHeader; + LOG_MSG_INFO("Setting parameters for IPA_CLIENT_TEST2_CONS"); + break; + case (IPA_CLIENT_TEST2_PROD): + m_pInodePath = CONFIG_17_TO_IPA_DEAGG; + m_nHeaderLengthAdd = sizeof(m_pUsbHeader); + m_nHeaderLengthRemove = sizeof(m_pUsbHeader); + m_pHeader = m_pUsbHeader; + LOG_MSG_INFO("Setting parameters for IPA_CLIENT_TEST2_PROD "); + break; + case (IPA_CLIENT_TEST3_CONS): + m_pInodePath = CONFIG_17_FROM_IPA; + m_nHeaderLengthAdd = sizeof(m_pUsbHeader); + m_nHeaderLengthRemove = sizeof(m_pUsbHeader); + m_pHeader = m_pUsbHeader; + LOG_MSG_INFO("Setting parameters for IPA_CLIENT_TEST3_CONS"); + break; + case (IPA_CLIENT_TEST_CONS): + m_pInodePath = CONFIG_17_FROM_IPA_AGG_TIME; + m_nHeaderLengthAdd = sizeof(m_pUsbHeader); + m_nHeaderLengthRemove = sizeof(m_pUsbHeader); + m_pHeader = m_pUsbHeader; + LOG_MSG_INFO("Setting parameters for IPA_CLIENT_TEST_CONS"); + break; + case (IPA_CLIENT_TEST4_CONS): + m_pInodePath = CONFIG_17_FROM_IPA_ZERO_LIMITS; + m_nHeaderLengthAdd = sizeof(m_pUsbHeader); + m_nHeaderLengthRemove = sizeof(m_pUsbHeader); + m_pHeader = m_pUsbHeader; + LOG_MSG_INFO("Setting parameters for IPA_CLIENT_TEST4_CONS"); + break; + default: + LOG_MSG_ERROR("IPA_TEST_CONFIFURATION_17 switch in default " + "nClientType = %d is not supported ", + nClientType); + break; + } + break; + case IPA_TEST_CONFIGURATION_18: + switch (nClientType) + { + case (IPA_CLIENT_TEST_PROD): + m_pInodePath = CONFIG_18_TO_IPA; + m_nHeaderLengthAdd = sizeof(m_pUsbHeader); + m_nHeaderLengthRemove = sizeof(m_pUsbHeader); + m_pHeader = m_pUsbHeader; + LOG_MSG_INFO("Setting parameters for IPA_CLIENT_TEST_PROD "); + break; + case (IPA_CLIENT_TEST2_PROD): + m_pInodePath = CONFIG_18_DUMMY_ENDPOINT; + m_nHeaderLengthAdd = sizeof(m_pUsbHeader); + m_nHeaderLengthRemove = sizeof(m_pUsbHeader); + m_pHeader = m_pUsbHeader; + LOG_MSG_INFO("Setting parameters for IPA_CLIENT_TEST2_PROD "); + break; + case (IPA_CLIENT_TEST_CONS): + m_pInodePath = CONFIG_18_FROM_IPA; + m_nHeaderLengthAdd = sizeof(m_pUsbHeader); + m_nHeaderLengthRemove = sizeof(m_pUsbHeader); + m_pHeader = m_pUsbHeader; + LOG_MSG_INFO("Setting parameters for IPA_CLIENT_TEST_CONS"); + break; + default: + LOG_MSG_ERROR( + "IPA_TEST_CONFIFURATION_18 switch in default " + "nClientType = %d is not supported ", + nClientType); + break; + } + break; + case IPA_TEST_CONFIGURATION_19: + switch (nClientType) + { + case (IPA_CLIENT_TEST_PROD): + m_pInodePath = CONFIG_19_FROM_USB_TO_IPA_DMA; + m_nHeaderLengthAdd = sizeof(m_pUsbHeader); + m_nHeaderLengthRemove = sizeof(m_pUsbHeader); + m_pHeader = m_pUsbHeader; + LOG_MSG_INFO("Setting parameters for IPA_CLIENT_TEST_PROD "); + break; + case (IPA_CLIENT_TEST_CONS): + m_pInodePath = CONFIG_19_FROM_IPA_TO_USB_DMA; + m_nHeaderLengthAdd = sizeof(m_pUsbHeader); + m_nHeaderLengthRemove = sizeof(m_pUsbHeader); + m_pHeader = m_pUsbHeader; + LOG_MSG_INFO("Setting parameters for TEST_CONS"); + break; + default: + LOG_MSG_ERROR("IPA_TEST_CONFIFURATION_19 switch in default " + "nClientType = %d is not supported ", nClientType); + break; + } + break; + default: + LOG_MSG_ERROR("Pipe::SetSpecificClientParameters " + "switch in default eConfiguration = %d ", eConfiguration); + break; + } +}/* Pipe::SetSpecificClientParameters() */ + +////////////////////////////////////////////////////////////////////////////////////////////////////////// + +int Pipe::GetHeaderLengthAdd() { + if (false == m_bInitialized) { + LOG_MSG_ERROR("Pipe is being used without being initialized!"); + return 0; + } + return m_nHeaderLengthAdd; +} + +////////////////////////////////////////////////////////////////////////////////////////////////////////// + +int Pipe::GetHeaderLengthRemove() { + if (false == m_bInitialized) { + LOG_MSG_ERROR("Pipe is being used without being initialized!"); + return 0; + } + return m_nHeaderLengthRemove; +} + +////////////////////////////////////////////////////////////////////////////////////////////////////////// + +bool Pipe::ConfigureHolb(unsigned short enable, unsigned timerValue) { + if (false == m_bInitialized) { + LOG_MSG_ERROR("Pipe is being used without being initialized!"); + return false; + } + + if (IPA_CLIENT_IS_PROD(m_nClientType)) { + LOG_MSG_ERROR("Can't configure HOLB on a producer pipe!"); + return false; + } + + struct ipa_test_holb_config test_holb_config; + + test_holb_config.client = m_nClientType; + test_holb_config.tmr_val = timerValue; + test_holb_config.en = enable; + + LOG_MSG_DEBUG("Sending: client=%d tmr_val=%d en=%d", + test_holb_config.client, + test_holb_config.tmr_val, + test_holb_config.en); + + return configure_holb(&test_holb_config); +} + +bool Pipe::EnableHolb(unsigned timerValue) { + return ConfigureHolb(1, timerValue); +} + +bool Pipe::DisableHolb() { + return ConfigureHolb(0, 0); +} + diff --git a/qcom/opensource/dataipa/kernel-tests/Pipe.h b/qcom/opensource/dataipa/kernel-tests/Pipe.h new file mode 100644 index 0000000000..e6172bc35f --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/Pipe.h @@ -0,0 +1,151 @@ +/* + * Copyright (c) 2017,2020 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _PIPE_H_ +#define _PIPE_H_ + +#include +#include +#include +#include +#include + +#include +#include "linux/msm_ipa.h" +#include "Constants.h" +#include "Logger.h" + +using namespace std; + +/*This class will be used to interact with the system pipes + *by only referring to Client type. + *It will allow "raw" data transfer to/from the IPA and + *will allow a encapsulation of the header addition/ + *removal of a packets thus allowing + *the test to deal only with IP packet. + */ +class Pipe +{ + +public: + /* see Constants.h for nClientType / eConfiguration */ + Pipe(enum ipa_client_type nClientType, + IPATestConfiguration eConfiguration); + /* exception pipe Ctor */ + Pipe(IPATestConfiguration eConfiguration); + ~Pipe(); + + /*In this method the actual inode openning will occur.*/ + bool Init(); + + /*The close of the inode*/ + void Destroy(); + + /*Send the pBuffer(which is an ip[ packet) + *after adding the header to the packet.*/ + int AddHeaderAndSend( + unsigned char *pBuffer, + size_t nIPPacketSize); + + /*Send raw data as is - no header removal + *- nBytesToSend bytes will be added*/ + int Send( + unsigned char *pBuffer, + size_t nBytesToSend); + + /*Receive data from the IPA and remove its header*/ + int ReceiveAndRemoveHeader( + unsigned char *pBuffer, + size_t nIPPacketSize); + + /*Receive data from the IPA as is*/ + int Receive(unsigned char *pBuffer, size_t nBytesToReceive); + + /*return the Client type of this pipe.*/ + enum ipa_client_type GetClientType(); + + /*Return the length of the header to be added to an + *IP packet before it is being sent to the pipe + *(This length will be determine by the Pipe's ClientType). + */ + int GetHeaderLengthAdd(); + + /*Return the length of the header to be removed from a + *packet before it is being sent to the user + *(thus returning only the IP packet). + *(This length will be determine by the Pipe's ClientType). + */ + int GetHeaderLengthRemove(); + + bool EnableHolb(unsigned timerValue); + bool DisableHolb(); + +private: + void SetSpecificClientParameters( + enum ipa_client_type nClientType, + IPATestConfiguration eConfiguration); + + bool ConfigureHolb(unsigned short enable, unsigned timerValue); + +public: + /*efault Headers(Can be changed in Derived classes).*/ + static unsigned char m_pUsbHeader[]; + static unsigned char m_pHSICHeader[]; + static unsigned char m_pA2DUNHeader[]; + static unsigned char m_pA2NDUNHeader[]; + static unsigned char m_pQ6LANHeader[]; + + +private: + int m_Fd; + /*The file descriptor which will be used to transfer data + * via the inode(this inode will be created by the ITAKEM) + */ + enum ipa_client_type m_nClientType; + int m_nHeaderLengthRemove; + /*this length will be set in the + * constructor in corresponds to m_nClientType + */ + int m_nHeaderLengthAdd; + /*this length will be set in the constructor + * in corresponds to m_nClientType + */ + unsigned char *m_pHeader; + /*this pointer will be set to the current pipe used*/ + const char *m_pInodePath; + /*this pointer will be set to the current pipe used*/ + bool m_bInitialized; + IPATestConfiguration m_eConfiguration; + /*The Pipes configuration env*/ + bool m_ExceptionPipe; + /* Is this the exception pipe */ + +}; + +#endif diff --git a/qcom/opensource/dataipa/kernel-tests/PipeTestFixture.cpp b/qcom/opensource/dataipa/kernel-tests/PipeTestFixture.cpp new file mode 100644 index 0000000000..3c483d2853 --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/PipeTestFixture.cpp @@ -0,0 +1,107 @@ +/* + * Copyright (c) 2017,2020 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "PipeTestFixture.h" + +extern Logger g_Logger; + +/*define the static Pipes which will be used by all derived tests.*/ +Pipe PipeTestFixture::m_IpaToUsbPipe(IPA_CLIENT_TEST_CONS, IPA_TEST_CONFIFURATION_1); +Pipe PipeTestFixture::m_UsbToIpaPipe(IPA_CLIENT_TEST_PROD, IPA_TEST_CONFIFURATION_1); + +PipeTestFixture::PipeTestFixture() +{ + m_testSuiteName.push_back("Pipes"); + Register(*this); +} + +static int SetupKernelModule(void) +{ + int retval; + struct ipa_channel_config from_ipa_0 = {0}; + struct test_ipa_ep_cfg from_ipa_0_cfg; + struct ipa_channel_config to_ipa_0 = {0}; + struct test_ipa_ep_cfg to_ipa_0_cfg; + + struct ipa_test_config_header header = {0}; + struct ipa_channel_config *to_ipa_array[1]; + struct ipa_channel_config *from_ipa_array[1]; + + + /* From ipa configurations - 1 pipes */ + memset(&from_ipa_0_cfg, 0 , sizeof(from_ipa_0_cfg)); + prepare_channel_struct(&from_ipa_0, + header.from_ipa_channels_num++, + IPA_CLIENT_TEST_CONS, + (void *)&from_ipa_0_cfg, + sizeof(from_ipa_0_cfg)); + from_ipa_array[0] = &from_ipa_0; + + /* To ipa configurations - 1 pipes */ + memset(&to_ipa_0_cfg, 0 , sizeof(to_ipa_0_cfg)); + to_ipa_0_cfg.mode.mode = IPA_DMA; + to_ipa_0_cfg.mode.dst = IPA_CLIENT_TEST_CONS; + prepare_channel_struct(&to_ipa_0, + header.to_ipa_channels_num++, + IPA_CLIENT_TEST_PROD, + (void *)&to_ipa_0_cfg, + sizeof(to_ipa_0_cfg)); + to_ipa_array[0] = &to_ipa_0; + + prepare_header_struct(&header, from_ipa_array, to_ipa_array); + + retval = GenericConfigureScenario(&header); + + return retval; +} + +bool PipeTestFixture::Setup() +{ + bool bRetVal = true; + + if (SetupKernelModule() == false) + return false; + + /*Initialize the pipe for all the tests - + * this will open the inode which represents the pipe. + */ + bRetVal &= m_IpaToUsbPipe.Init(); + bRetVal &= m_UsbToIpaPipe.Init(); + + return bRetVal; +} + +bool PipeTestFixture::Teardown() +{ + /*The Destroy method will close the inode.*/ + m_IpaToUsbPipe.Destroy(); + m_UsbToIpaPipe.Destroy(); + + return true; +} diff --git a/qcom/opensource/dataipa/kernel-tests/PipeTestFixture.h b/qcom/opensource/dataipa/kernel-tests/PipeTestFixture.h new file mode 100644 index 0000000000..4544607af1 --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/PipeTestFixture.h @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2017 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include + +#include "Constants.h" +#include "Logger.h" +#include "linux/msm_ipa.h" +#include "TestsUtils.h" +#include "TestBase.h" +#include "Pipe.h" + +/*This class will be the base class of all Pipe tests. + *Any method other than the test case itself can be + *declared in this Fixture thus allowing the derived classes to + *implement only the test case. + *All the test of the pipe uses one input and one output in DMA mode. + */ +class PipeTestFixture:public TestBase +{ +public: + /*This Constructor will register each instance that it creates.*/ + PipeTestFixture(); + + /*This method will create and initialize two Pipe object for the USB + * (Ethernet) Pipes, one as input and the other as output. + */ + virtual bool Setup(); + + /*This method will destroy the pipes.*/ + virtual bool Teardown(); + + /*The client type are set from the peripheral perspective + * (TODO Pipe:in case the Driver will change its perspective + * of ipa_connect this should be changed). + */ + static Pipe m_IpaToUsbPipe; + static Pipe m_UsbToIpaPipe; +}; diff --git a/qcom/opensource/dataipa/kernel-tests/PipeTests.cpp b/qcom/opensource/dataipa/kernel-tests/PipeTests.cpp new file mode 100644 index 0000000000..737410e0f8 --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/PipeTests.cpp @@ -0,0 +1,478 @@ +/* + * Copyright (c) 2017,2020 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include + +#include "PipeTestFixture.h" +#include "Constants.h" +#include "TestsUtils.h" +#include "linux/msm_ipa.h" + +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// + +class PipeTestRawTransfer: public PipeTestFixture { +public: + + ///////////////////////////////////////////////////////////////////////////////// + + PipeTestRawTransfer() { + m_name = "PipeTestRawTransfer"; + m_description = "This test will be using the Pipe raw transfer ability"; + } + + ///////////////////////////////////////////////////////////////////////////////// + + bool Run() { + bool bTestResult = true; + Byte pIpPacket[] = { 0x01, 0x02, 0x03, 0x04 }; //This packet will be sent(It can be replaced by a real IP packet). + Byte pIpPacketReceive[sizeof(pIpPacket)] = { 0 }; //This buffer will be used in order to store the received packet. + + //Send the raw IP packet(which is a 4 arbitrary bytes) without header addition by the Pipe + LOG_MSG_DEBUG( + "Sending packet into the USB pipe(%d bytes)\n", sizeof(pIpPacket)); + int nBytesSent = m_UsbToIpaPipe.Send(pIpPacket, sizeof(pIpPacket)); + if (sizeof(pIpPacket) != nBytesSent) { + return false; + } + + //Receive the raw IP packet(which is a 4 arbitrary bytes) without header removal by the Pipe + LOG_MSG_DEBUG( + "Reading packet from the USB pipe(%d bytes should be there)\n", sizeof(pIpPacketReceive)); + int nBytesReceived = m_IpaToUsbPipe.Receive(pIpPacketReceive, + sizeof(pIpPacketReceive)); + if (sizeof(pIpPacketReceive) != nBytesReceived) { + return false; + } + for (int i = 0; i < nBytesReceived; i++) { + LOG_MSG_DEBUG("0x%02x\n", pIpPacketReceive[i]); + } + + //Check that the sent IP packet is equal to the received IP packet. + LOG_MSG_DEBUG("Checking sent.vs.received packet\n"); + bTestResult &= !memcmp(pIpPacket, pIpPacketReceive, sizeof(pIpPacket)); + + return bTestResult; + } + + ///////////////////////////////////////////////////////////////////////////////// +}; + +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// + +//This test will be using the Pipe Add-Header transfer ability(and not header insertion +class PipeTestAddHeader: public PipeTestFixture { +public: + + ///////////////////////////////////////////////////////////////////////////////// + + PipeTestAddHeader() { + m_name = "PipeTestAddHeader"; + m_description = "Add header to USB pipe and receive it without removing the header"; + } + + ///////////////////////////////////////////////////////////////////////////////// + + bool Run() { + Byte pIpPacketSend[4] = { 0x01, 0x02, 0x03, 0x04 }; + int nReceivedPacketSize = sizeof(pIpPacketSend) + + m_IpaToUsbPipe.GetHeaderLengthAdd(); + Byte *pPacketReceive = new Byte[nReceivedPacketSize]; + + LOG_MSG_DEBUG("Sending packet into the USB pipe(%d bytes - no header size)\n", sizeof(pIpPacketSend)); + int nRetValSend = m_UsbToIpaPipe.AddHeaderAndSend(pIpPacketSend, + sizeof(pIpPacketSend)); + LOG_MSG_DEBUG("Result of AddHeaderAndSend = %d\n", nRetValSend); + + LOG_MSG_DEBUG("Reading packet from the USB pipe(%d bytes - including header)\n", nReceivedPacketSize); + int nRetValReceive = m_IpaToUsbPipe.Receive(pPacketReceive, + nReceivedPacketSize); + LOG_MSG_DEBUG("Result of Receive = %d\n", nRetValReceive); + + if (nReceivedPacketSize != nRetValReceive) { + delete[] pPacketReceive; + LOG_MSG_ERROR( + "Size of received packet is not as expected - %d\n", nRetValReceive); + return false; + } + + bool bHeaderCmp = !memcmp(pPacketReceive, Pipe::m_pUsbHeader, + m_IpaToUsbPipe.GetHeaderLengthAdd()); + LOG_MSG_DEBUG("bHeaderCmp - %s\n", bHeaderCmp ? "True" : "False"); + + bool bIpCmp = !memcmp(pPacketReceive + m_IpaToUsbPipe.GetHeaderLengthAdd(), + pIpPacketSend, sizeof(pIpPacketSend)); + LOG_MSG_DEBUG("bIpCmp - %s\n", bIpCmp ? "True" : "False"); + + delete[] pPacketReceive; + return bHeaderCmp && bIpCmp; + } + + ///////////////////////////////////////////////////////////////////////////////// +}; + +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// + +//This test will be using the Pipe Remove-Header transfer ability(and header addition) +class PipeTestAddAndRemoveHeader: public PipeTestFixture { +public: + + ///////////////////////////////////////////////////////////////////////////////// + + PipeTestAddAndRemoveHeader() { + m_name = "PipeTestAddAndRemoveHeader"; + m_description = "This test will be using the Pipe Remove-Header transfer ability(and header addition)"; + } + + ///////////////////////////////////////////////////////////////////////////////// + + bool Run() { + Byte pIpPacketSend[4] = { 0x01, 0x02, 0x03, 0x04 }; + int nToBeReceivedPacketSize = sizeof(pIpPacketSend) + + m_IpaToUsbPipe.GetHeaderLengthAdd(); + Byte *pPacketReceive = new Byte[nToBeReceivedPacketSize]; + + LOG_MSG_DEBUG("Sending packet into the USB pipe(%d bytes - no header size)\n", sizeof(pIpPacketSend)); + int nBytesSent = m_UsbToIpaPipe.AddHeaderAndSend(pIpPacketSend, + sizeof(pIpPacketSend)); + LOG_MSG_DEBUG("nBytesSent of AddHeaderAndSend = %d\n", nBytesSent); + + LOG_MSG_DEBUG("Reading packet from the USB pipe(%d bytes - including header)\n", nToBeReceivedPacketSize); + int nBytesReceived = m_IpaToUsbPipe.Receive(pPacketReceive, + nToBeReceivedPacketSize); + LOG_MSG_DEBUG("nBytesReceived = %d\n", nBytesReceived); + + if (nToBeReceivedPacketSize != nBytesReceived) { + delete[] pPacketReceive; + LOG_MSG_ERROR("Size of received packet is not as expected - %d\n", nBytesReceived); + return false; + } + + bool bHeaderCmp = !memcmp(pPacketReceive, Pipe::m_pUsbHeader, + m_IpaToUsbPipe.GetHeaderLengthAdd()); + LOG_MSG_DEBUG("bHeaderCmp - %s\n", bHeaderCmp ? "True" : "False"); + + bool bIpCmp = !memcmp(pPacketReceive + m_IpaToUsbPipe.GetHeaderLengthAdd(), + pIpPacketSend, sizeof(pIpPacketSend)); + LOG_MSG_DEBUG("bIpCmp - %s\n", bIpCmp ? "True" : "False"); + + delete[] pPacketReceive; + return bHeaderCmp && bIpCmp; + } + + ///////////////////////////////////////////////////////////////////////////////// +}; + +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// + +//This test will try to send big chuck of data and check if the Data FIFO is working correct +class PipeTestDataFifoOverflow: public PipeTestFixture { +public: + + ///////////////////////////////////////////////////////////////////////////////// + + PipeTestDataFifoOverflow() { + m_name = "PipeTestDataFifoOverflow"; + m_description = "Send many big packets over the IPA. there will be toggle of send/receive"; + m_runInRegression = false; // Test is very long thus makes a problem in regression testing + } + + ///////////////////////////////////////////////////////////////////////////////// + + bool Run() { + bool bTestResult = true; + int nPacketByteSize; + int nTotalDataSent = 0; + int nTestsMaxDataSend = 3 * 0x6400; + int nIterationNumber = 0; + Byte *pIpPacket; + Byte *pIpPacketReceive; + srand(123); //set some constant seed value in order to be able to reproduce problems. + + //send and receive many packets(nIterations) + while (nTotalDataSent < nTestsMaxDataSend) { + //get random values for this packet. + nPacketByteSize = (rand() % 400) + 200; + pIpPacket = new Byte[nPacketByteSize]; + + for (int j = 0; j < nPacketByteSize; j++) { + pIpPacket[j] = rand() % 0x100; + } + + //Send the raw IP packet(which is a 4 arbitrary bytes) without header addition by the Pipe + LOG_MSG_DEBUG( + "Iteration number %d(0x%08x/0x%08x data):\n", nIterationNumber++, nTotalDataSent, nTestsMaxDataSend); + LOG_MSG_DEBUG( + "Sending packet into the USB pipe(%d bytes)\n", nPacketByteSize); + int nBytesSent = m_UsbToIpaPipe.Send(pIpPacket, nPacketByteSize); + if (nPacketByteSize != nBytesSent) { + delete[] pIpPacket; + LOG_MSG_ERROR("Could not send the whole packet - nTotalDataSent = 0x%08x\n", nTotalDataSent); + return false; + } + + //Receive the raw IP packet(which is a 4 arbitrary bytes) without header removal by the Pipe + pIpPacketReceive = new Byte[nPacketByteSize]; + LOG_MSG_DEBUG("Reading packet from the USB pipe(%d bytes should be there)\n", nPacketByteSize); + int nBytesReceived = m_IpaToUsbPipe.Receive(pIpPacketReceive, + nPacketByteSize); + if (nPacketByteSize != nBytesReceived) { + delete[] pIpPacket; + delete[] pIpPacketReceive; + LOG_MSG_ERROR("Could not read the whole packet - nTotalDataSent = 0x%08x\n", nTotalDataSent); + return false; + } + for (int j = 0; j < nBytesReceived; j++) { + LOG_MSG_DEBUG("0x%02x\n", pIpPacketReceive[j]); + } + + //Check that the sent IP packet is equal to the received IP packet. + LOG_MSG_DEBUG("Checking sent.vs.received packet\n"); + bTestResult &= !memcmp(pIpPacket, pIpPacketReceive, + nPacketByteSize); + if (true != bTestResult) { + delete[] pIpPacketReceive; + delete[] pIpPacket; + LOG_MSG_ERROR("Send != Received - nTotalDataSent = 0x%08x\n", nTotalDataSent); + return false; + } + nTotalDataSent += nPacketByteSize; + delete[] pIpPacket; + delete[] pIpPacketReceive; + } + LOG_MSG_DEBUG("Great success - nTotalDataSent = 0x%08x\n", nTotalDataSent); + return true; + } + + ///////////////////////////////////////////////////////////////////////////////// +}; + +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// + +//This test will try to many little chuck of data and check if the Descriptor FIFO is working correct +class PipeTestDescriptorFifoOverflow: public PipeTestFixture { +public: + + ///////////////////////////////////////////////////////////////////////////////// + + PipeTestDescriptorFifoOverflow() { + m_name = "PipeTestDescriptorFifoOverflow"; + m_description = "Send many small packets over the IPA. there will be toggle of send/receive"; + m_runInRegression = false; // Test is very long thus makes a problem in regression testing + } + + ///////////////////////////////////////////////////////////////////////////////// + + bool Run() { + bool bTestResult = true; + int nPacketByteSize; + int nTotalPacketSent = 0; + int nTestsMaxDescriptors = 3 * 0x1000; + int nIterationNumber = 0; + Byte *pIpPacket; + Byte *pIpPacketReceive; + srand(123); //set some constant seed value in order to be able to reproduce problems. + + //send and receive many packets(nIterations) + while (nTotalPacketSent < nTestsMaxDescriptors) { + //get random values for this packet. + nPacketByteSize = (rand() % 10) + 1; + pIpPacket = new Byte[nPacketByteSize]; + + for (int j = 0; j < nPacketByteSize; j++) { + pIpPacket[j] = rand() % 0x100; + } + + //Send the raw IP packet(which is a 4 arbitrary bytes) without header addition by the Pipe + LOG_MSG_DEBUG("Iteration number %d(0x%08x/0x%08x packets):\n", nIterationNumber++, nTotalPacketSent, nTestsMaxDescriptors); + LOG_MSG_DEBUG("Sending packet into the USB pipe(%d bytes)\n", nPacketByteSize); + int nBytesSent = m_UsbToIpaPipe.Send(pIpPacket, nPacketByteSize); + if (nPacketByteSize != nBytesSent) { + delete[] pIpPacket; + LOG_MSG_ERROR("Could not send the whole packet - nTotalPacketSent = 0x%08x\n", nTotalPacketSent); + return false; + } + + //Receive the raw IP packet(which is a 4 arbitrary bytes) without header removal by the Pipe + pIpPacketReceive = new Byte[nPacketByteSize]; + LOG_MSG_DEBUG("Reading packet from the USB pipe(%d bytes should be there)\n", nPacketByteSize); + int nBytesReceived = m_IpaToUsbPipe.Receive(pIpPacketReceive, + nPacketByteSize); + if (nPacketByteSize != nBytesReceived) { + delete[] pIpPacketReceive; + LOG_MSG_ERROR("Could not read the whole packet - nTotalPacketSent = 0x%08x\n", nTotalPacketSent); + return false; + } + for (int j = 0; j < nBytesReceived; j++) { + LOG_MSG_DEBUG("0x%02x\n", pIpPacketReceive[j]); + } + + //Check that the sent IP packet is equal to the received IP packet. + LOG_MSG_DEBUG("Checking sent.vs.received packet\n"); + bTestResult &= !memcmp(pIpPacket, pIpPacketReceive, + nPacketByteSize); + if (true != bTestResult) { + delete[] pIpPacketReceive; + delete[] pIpPacket; + LOG_MSG_ERROR("Send != Received - nTotalPacketSent = 0x%08x\n", nTotalPacketSent); + return false; + } + nTotalPacketSent++; + delete[] pIpPacket; + delete[] pIpPacketReceive; + } + LOG_MSG_DEBUG("Great success - nTotalPacketSent = 0x%08x\n", nTotalPacketSent); + return true; + } + + ///////////////////////////////////////////////////////////////////////////////// + +}; + +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// + +#define HOLB_TEST_PACKETS_MAX_NUM 50 +class PipeTestHolb: public PipeTestFixture { + +public: + + PipeTestHolb() { + m_name = "PipeTestHolb"; + m_description = "This test will check the HOLB function"; + } + + bool Run() { + int nPacketsToSend = HOLB_TEST_PACKETS_MAX_NUM; + int nBytesReceived; + int nBytesSentInLastPacket; + int i; + Byte pIpPacket[] = { 0x01, 0x02, 0x03, 0x04 }; //This packet will be sent(It can be replaced by a real IP packet). + Byte pIpPacketReceive[sizeof(pIpPacket) * HOLB_TEST_PACKETS_MAX_NUM] = { 0 }; //This buffer will be used in order to store the received packet. + + m_IpaToUsbPipe.DisableHolb(); + + //Send the IP packets + LOG_MSG_DEBUG("Sending %d packets of %d bytes into the USB pipe\n", + nPacketsToSend, sizeof(pIpPacket)); + for (i = 0; i < nPacketsToSend; i++) { + nBytesSentInLastPacket = m_UsbToIpaPipe.Send(pIpPacket, sizeof(pIpPacket)); + if (sizeof(pIpPacket) != nBytesSentInLastPacket) { + LOG_MSG_ERROR("Failed sending the packet %d to m_UsbToIpaPipe", i); + return false; + } + } + + //Receive all the raw IP packets (which are a 4 arbitrary bytes) + LOG_MSG_DEBUG( + "Reading packets from the USB pipe (%dx%d bytes should be there)\n", + sizeof(pIpPacket), nPacketsToSend); + for (i = 0; i < nPacketsToSend; i++) { + nBytesReceived = m_IpaToUsbPipe.Receive(pIpPacketReceive, sizeof(pIpPacketReceive)); + if ((int)sizeof(pIpPacket) != nBytesReceived) { + LOG_MSG_ERROR("Failed with HOLB disabled! Packet #%d: Expected %d Bytes, got %d Bytes", + i, sizeof(pIpPacket), nBytesReceived); + return false; + } + } + + // Enable HOLB + m_IpaToUsbPipe.EnableHolb(0); + + //Send the IP packets + LOG_MSG_DEBUG("Sending %d packets of %d bytes into the USB pipe\n", + nPacketsToSend, sizeof(pIpPacket)); + for (i = 0; i < nPacketsToSend; i++) { + nBytesSentInLastPacket = m_UsbToIpaPipe.Send(pIpPacket, sizeof(pIpPacket)); + if (sizeof(pIpPacket) != nBytesSentInLastPacket) { + LOG_MSG_ERROR("Failed sending the packet %d to m_UsbToIpaPipe", i); + return false; + } + } + + // Receive the raw IP packets (which are a 4 arbitrary bytes) + // that fit into the FIFO before the HOLB started dropping + // and fail to receive the rest + LOG_MSG_DEBUG( + "Reading packets from the USB pipe(%dx%d bytes should be there)\n", + sizeof(pIpPacket), nPacketsToSend); + for (i = 0; i < nPacketsToSend; i++) { + int nBytesReceived = m_IpaToUsbPipe.Receive(pIpPacketReceive, + sizeof(pIpPacketReceive)); + if ((int)sizeof(pIpPacket) != nBytesReceived) { + if (i == 0) { + LOG_MSG_ERROR("First packet failed to receive ! Expected %d Bytes, got %d Bytes", + sizeof(pIpPacket), nBytesReceived); + return false; + } else + // Failed to receive a packet, but not the first one. + // This is the desired result. + return true; + } + } + + LOG_MSG_ERROR("All packets were received successfully, which means the HOLB didn't work."); + return false; + } +}; + +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// + +//Those tests should be run with configuration number 1 which has one input pipe and +//one output pipe. +//Please look at the Fixture for more configurations update. +static PipeTestRawTransfer pipeTestRawTransfer; +static PipeTestAddHeader pipeTestAddHeader; +static PipeTestAddAndRemoveHeader pipeTestAddAndRemoveHeader; +static PipeTestHolb pipeTestHolb; + +//DO NOT UNCOMMENT THOSE LINES UNLESS YOU KNOW WHAT YOU ARE DOING!!! +//those test takes 4ever and should be use for specific usecase! +//static PipeTestDataFifoOverflow pipeTestDataFifoOverflow; +//static PipeTestDescriptorFifoOverflow pipeTestDescriptorFifoOverflow; + +///////////////////////////////////////////////////////////////////////////////// +// EOF //// +///////////////////////////////////////////////////////////////////////////////// diff --git a/qcom/opensource/dataipa/kernel-tests/README.txt b/qcom/opensource/dataipa/kernel-tests/README.txt new file mode 100644 index 0000000000..db60972f22 --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/README.txt @@ -0,0 +1,11 @@ +Subsystem: ipa-kernel-tests + +Parameters: + -n: Nominal test case (tests all the different use cases for ip_accelerator) + -a: Adversarial test case (Currently holds no tests) + -r: Repeatability test case (Currently holds no tests) + -s: Stress test case (invokes many simultaneous threads that all try and access the device at once) + --help: Specifies the params for run.sh + +Description: +This test module tests IPA driver, it holds a userspace module and a kernel space module. \ No newline at end of file diff --git a/qcom/opensource/dataipa/kernel-tests/RNDISAggregationTestFixture.cpp b/qcom/opensource/dataipa/kernel-tests/RNDISAggregationTestFixture.cpp new file mode 100644 index 0000000000..803ec2b14c --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/RNDISAggregationTestFixture.cpp @@ -0,0 +1,1097 @@ +/* + * Copyright (c) 2017-2018,2020 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "RNDISAggregationTestFixture.h" +#include "TestManager.h" + +///////////////////////////////////////////////////////////////////////////////// + +//define the static Pipes which will be used by all derived tests. +Pipe RNDISAggregationTestFixture::m_IpaToUsbPipeAgg(IPA_CLIENT_TEST2_CONS, + IPA_TEST_CONFIGURATION_17); +Pipe RNDISAggregationTestFixture::m_UsbToIpaPipe(IPA_CLIENT_TEST_PROD, + IPA_TEST_CONFIGURATION_17); +Pipe RNDISAggregationTestFixture::m_IpaToUsbPipe(IPA_CLIENT_TEST3_CONS, + IPA_TEST_CONFIGURATION_17); +Pipe RNDISAggregationTestFixture::m_UsbToIpaPipeDeagg(IPA_CLIENT_TEST2_PROD, + IPA_TEST_CONFIGURATION_17); +Pipe RNDISAggregationTestFixture::m_IpaToUsbPipeAggTime(IPA_CLIENT_TEST_CONS, + IPA_TEST_CONFIGURATION_17); +Pipe RNDISAggregationTestFixture::m_IpaToUsbPipeAggPktLimit(IPA_CLIENT_TEST4_CONS, + IPA_TEST_CONFIGURATION_17); +Pipe RNDISAggregationTestFixture::m_HsicToIpaPipe(IPA_CLIENT_TEST3_PROD, + IPA_TEST_CONFIGURATION_17); + +RoutingDriverWrapper RNDISAggregationTestFixture::m_Routing; +Filtering RNDISAggregationTestFixture::m_Filtering; +HeaderInsertion RNDISAggregationTestFixture::m_HeaderInsertion; + +///////////////////////////////////////////////////////////////////////////////// + +RNDISAggregationTestFixture::RNDISAggregationTestFixture() +{ + m_testSuiteName.push_back("RndisAgg"); + Register(*this); +} + +///////////////////////////////////////////////////////////////////////////////// + +static int SetupKernelModule(void) +{ + int retval; + struct ipa_channel_config from_ipa_channels[4]; + struct test_ipa_ep_cfg from_ipa_cfg[4]; + struct ipa_channel_config to_ipa_channels[3]; + struct test_ipa_ep_cfg to_ipa_cfg[3]; + struct ipa_test_config_header header = {0}; + struct ipa_channel_config *to_ipa_array[3]; + struct ipa_channel_config *from_ipa_array[4]; + bool en_status = false; + + /* From ipa configurations - 4 pipes */ + memset(&from_ipa_cfg[0], 0, sizeof(from_ipa_cfg[0])); + from_ipa_cfg[0].aggr.aggr_en = IPA_ENABLE_AGGR; + from_ipa_cfg[0].aggr.aggr = IPA_GENERIC; + from_ipa_cfg[0].aggr.aggr_byte_limit = 1; + from_ipa_cfg[0].aggr.aggr_time_limit = 0; + from_ipa_cfg[0].hdr.hdr_ofst_pkt_size_valid = true; + from_ipa_cfg[0].hdr.hdr_ofst_pkt_size = 12; + from_ipa_cfg[0].hdr.hdr_additional_const_len = 14; + from_ipa_cfg[0].hdr.hdr_len = 58; + from_ipa_cfg[0].hdr_ext.hdr_little_endian = true; + from_ipa_cfg[0].hdr_ext.hdr_total_len_or_pad_valid = true; + from_ipa_cfg[0].hdr_ext.hdr_total_len_or_pad = IPA_HDR_TOTAL_LEN; + from_ipa_cfg[0].hdr_ext.hdr_total_len_or_pad_offset = 4; + + prepare_channel_struct(&from_ipa_channels[0], + header.from_ipa_channels_num++, + IPA_CLIENT_TEST2_CONS, + (void *)&from_ipa_cfg[0], + sizeof(from_ipa_cfg[0]), + en_status); + from_ipa_array[0] = &from_ipa_channels[0]; + + memset(&from_ipa_cfg[1], 0, sizeof(from_ipa_cfg[1])); + prepare_channel_struct(&from_ipa_channels[1], + header.from_ipa_channels_num++, + IPA_CLIENT_TEST3_CONS, + (void *)&from_ipa_cfg[1], + sizeof(from_ipa_cfg[1]), + en_status); + from_ipa_array[1] = &from_ipa_channels[1]; + + memset(&from_ipa_cfg[2], 0, sizeof(from_ipa_cfg[2])); + from_ipa_cfg[2].aggr.aggr_en = IPA_ENABLE_AGGR; + from_ipa_cfg[2].aggr.aggr = IPA_GENERIC; + from_ipa_cfg[2].aggr.aggr_byte_limit = 1; + from_ipa_cfg[2].aggr.aggr_time_limit = 30; + if (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v4_2) + from_ipa_cfg[2].aggr.aggr_time_limit *= 1000; + from_ipa_cfg[2].hdr.hdr_ofst_pkt_size_valid = true; + from_ipa_cfg[2].hdr.hdr_ofst_pkt_size = 12; + from_ipa_cfg[2].hdr.hdr_additional_const_len = 14; + from_ipa_cfg[2].hdr.hdr_len = 58; + from_ipa_cfg[2].hdr_ext.hdr_little_endian = true; + from_ipa_cfg[2].hdr_ext.hdr_total_len_or_pad_valid = true; + from_ipa_cfg[2].hdr_ext.hdr_total_len_or_pad = IPA_HDR_TOTAL_LEN; + from_ipa_cfg[2].hdr_ext.hdr_total_len_or_pad_offset = 4; + + prepare_channel_struct(&from_ipa_channels[2], + header.from_ipa_channels_num++, + IPA_CLIENT_TEST_CONS, + (void *)&from_ipa_cfg[2], + sizeof(from_ipa_cfg[2]), + en_status); + from_ipa_array[2] = &from_ipa_channels[2]; + + memset(&from_ipa_cfg[3], 0, sizeof(from_ipa_cfg[3])); + from_ipa_cfg[3].aggr.aggr_en = IPA_ENABLE_AGGR; + from_ipa_cfg[3].aggr.aggr = IPA_GENERIC; + from_ipa_cfg[3].aggr.aggr_byte_limit = 0; + from_ipa_cfg[3].aggr.aggr_time_limit = 0; + from_ipa_cfg[3].aggr.aggr_pkt_limit = 2; + from_ipa_cfg[3].hdr.hdr_ofst_pkt_size_valid = true; + from_ipa_cfg[3].hdr.hdr_ofst_pkt_size = 12; + from_ipa_cfg[3].hdr.hdr_additional_const_len = 14; + from_ipa_cfg[3].hdr.hdr_len = 58; + from_ipa_cfg[3].hdr_ext.hdr_little_endian = true; + from_ipa_cfg[3].hdr_ext.hdr_total_len_or_pad_valid = true; + from_ipa_cfg[3].hdr_ext.hdr_total_len_or_pad = IPA_HDR_TOTAL_LEN; + from_ipa_cfg[3].hdr_ext.hdr_total_len_or_pad_offset = 4; + + prepare_channel_struct(&from_ipa_channels[3], + header.from_ipa_channels_num++, + IPA_CLIENT_TEST4_CONS, + (void *)&from_ipa_cfg[3], + sizeof(from_ipa_cfg[3]), + en_status); + from_ipa_array[3] = &from_ipa_channels[3]; + + /* to ipa configurations - 3 pipes */ + memset(&to_ipa_cfg[0], 0, sizeof(to_ipa_cfg[0])); + to_ipa_cfg[0].hdr.hdr_len = 14; + + prepare_channel_struct(&to_ipa_channels[0], + header.to_ipa_channels_num++, + IPA_CLIENT_TEST_PROD, + (void *)&to_ipa_cfg[0], + sizeof(to_ipa_cfg[0]), + en_status); + to_ipa_array[0] = &to_ipa_channels[0]; + + memset(&to_ipa_cfg[1], 0, sizeof(to_ipa_cfg[1])); + prepare_channel_struct(&to_ipa_channels[1], + header.to_ipa_channels_num++, + IPA_CLIENT_TEST3_PROD, + (void *)&to_ipa_cfg[1], + sizeof(to_ipa_cfg[1]), + en_status); + to_ipa_array[1] = &to_ipa_channels[1]; + + memset(&to_ipa_cfg[2], 0, sizeof(to_ipa_cfg[2])); + to_ipa_cfg[2].aggr.aggr_en = IPA_ENABLE_DEAGGR; + to_ipa_cfg[2].aggr.aggr = IPA_GENERIC; + to_ipa_cfg[2].deaggr.deaggr_hdr_len = 44; + to_ipa_cfg[2].deaggr.packet_offset_valid = true; + to_ipa_cfg[2].deaggr.packet_offset_location = 8; + to_ipa_cfg[2].hdr.hdr_len = 14; /* Ethernet header */ + to_ipa_cfg[2].hdr.hdr_ofst_pkt_size = 12; + to_ipa_cfg[2].hdr.hdr_remove_additional = false; + to_ipa_cfg[2].hdr_ext.hdr_little_endian = 1; + to_ipa_cfg[2].hdr_ext.hdr_total_len_or_pad_valid = 1; + to_ipa_cfg[2].hdr_ext.hdr_total_len_or_pad = IPA_HDR_TOTAL_LEN; + to_ipa_cfg[2].hdr_ext.hdr_payload_len_inc_padding = 0; + to_ipa_cfg[2].hdr_ext.hdr_total_len_or_pad_offset = 4; + + prepare_channel_struct(&to_ipa_channels[2], + header.to_ipa_channels_num++, + IPA_CLIENT_TEST2_PROD, + (void *)&to_ipa_cfg[2], + sizeof(to_ipa_cfg[2]), + en_status); + to_ipa_array[2] = &to_ipa_channels[2]; + + prepare_header_struct(&header, from_ipa_array, to_ipa_array); + + retval = GenericConfigureScenario(&header); + + return retval; +} + +bool RNDISAggregationTestFixture::Setup() +{ + bool bRetVal = true; + + //Set the configuration to support USB->IPA and IPA->USB pipes. + bRetVal = SetupKernelModule(); + if (bRetVal != true) { + return bRetVal; + } + + //Initialize the pipe for all the tests - this will open the inode which represents the pipe. + bRetVal &= m_IpaToUsbPipeAgg.Init(); + bRetVal &= m_UsbToIpaPipe.Init(); + bRetVal &= m_HsicToIpaPipe.Init(); + bRetVal &= m_IpaToUsbPipe.Init(); + bRetVal &= m_UsbToIpaPipeDeagg.Init(); + bRetVal &= m_IpaToUsbPipeAggTime.Init(); + bRetVal &= m_IpaToUsbPipeAggPktLimit.Init(); + + if (!m_Routing.DeviceNodeIsOpened()) { + LOG_MSG_ERROR( + "Routing block is not ready for immediate commands!\n"); + return false; + } + if (!m_Filtering.DeviceNodeIsOpened()) { + LOG_MSG_ERROR( + "Filtering block is not ready for immediate commands!\n"); + return false; + } + if (!m_HeaderInsertion.DeviceNodeIsOpened()) + { + LOG_MSG_ERROR("Header Insertion block is not ready for immediate commands!\n"); + return false; + } + m_HeaderInsertion.Reset();// resetting this component will reset both Routing and Filtering tables. + + return bRetVal; +} + +///////////////////////////////////////////////////////////////////////////////// + +bool RNDISAggregationTestFixture::Teardown() +{ + //The Destroy method will close the inode. + m_IpaToUsbPipeAgg.Destroy(); + m_UsbToIpaPipe.Destroy(); + m_HsicToIpaPipe.Destroy(); + m_IpaToUsbPipe.Destroy(); + m_UsbToIpaPipeDeagg.Destroy(); + m_IpaToUsbPipeAggTime.Destroy(); + m_IpaToUsbPipeAggPktLimit.Destroy(); + + return true; +} + +///////////////////////////////////////////////////////////////////////////////// + +bool RNDISAggregationTestFixture::Run() +{ + LOG_MSG_STACK("Entering Function"); + + // Add the relevant filtering rules + if (!AddRules()) { + LOG_MSG_ERROR("Failed adding filtering rules."); + return false; + } + if (!TestLogic()) { + LOG_MSG_ERROR("Test failed, Input and expected output mismatch."); + return false; + } + + LOG_MSG_STACK("Leaving Function (Returning True)"); + return true; +} // Run() + +///////////////////////////////////////////////////////////////////////////////// +bool RNDISAggregationTestFixture::AddRulesNoAgg() { + m_eIP = IPA_IP_v4; + const char aBypass[20] = "Bypass1"; + bool bRetVal = true; + IPAFilteringTable cFilterTable0; + struct ipa_flt_rule_add sFilterRuleEntry; + uint32_t nTableHdl; + + + LOG_MSG_STACK("Entering Function"); + memset(&sFilterRuleEntry, 0, sizeof(sFilterRuleEntry)); + + if (!CreateBypassRoutingTable(&m_Routing, m_eIP, aBypass, IPA_CLIENT_TEST3_CONS, + 0, &nTableHdl)) { + LOG_MSG_ERROR("CreateBypassRoutingTable Failed\n"); + bRetVal = false; + goto bail; + } + + + LOG_MSG_INFO("Creation of bypass routing table completed successfully"); + + // Creating Filtering Rules + cFilterTable0.Init(m_eIP,IPA_CLIENT_TEST_PROD, false, 1); + LOG_MSG_INFO("Creation of filtering table completed successfully"); + + // Configuring Filtering Rule No.1 + cFilterTable0.GeneratePresetRule(1,sFilterRuleEntry); + sFilterRuleEntry.at_rear = true; + sFilterRuleEntry.flt_rule_hdl=-1; // return Value + sFilterRuleEntry.status = -1; // return value + sFilterRuleEntry.rule.action=IPA_PASS_TO_ROUTING; + sFilterRuleEntry.rule.retain_hdr = true; + sFilterRuleEntry.rule.rt_tbl_hdl = nTableHdl; //put here the handle corresponding to Routing Rule 1 + sFilterRuleEntry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; // Destination IP Based Filtering + sFilterRuleEntry.rule.attrib.u.v4.dst_addr_mask = 0xFF0000FF; // Mask + sFilterRuleEntry.rule.attrib.u.v4.dst_addr = 0x7F000001; // Filter DST_IP == 127.0.0.1. + if ( + ((uint8_t)-1 == cFilterTable0.AddRuleToTable(sFilterRuleEntry)) || + !m_Filtering.AddFilteringRule(cFilterTable0.GetFilteringTable()) + ) + { + LOG_MSG_ERROR ("Adding Rule (0) to Filtering block Failed."); + bRetVal = false; + goto bail; + } else + { + LOG_MSG_DEBUG("flt rule hdl0=0x%x, status=0x%x\n", cFilterTable0.ReadRuleFromTable(0)->flt_rule_hdl,cFilterTable0.ReadRuleFromTable(0)->status); + } + +bail: + LOG_MSG_STACK( + "Leaving Function (Returning %s)", bRetVal?"True":"False"); + return bRetVal; +} // AddRules() + +bool RNDISAggregationTestFixture::AddRulesDeAggEther() { + m_eIP = IPA_IP_v4; + const char aBypass[20] = "Bypass1"; + bool bRetVal = true; + IPAFilteringTable cFilterTable0; + struct ipa_flt_rule_add sFilterRuleEntry; + uint32_t nTableHdl; + + + LOG_MSG_STACK("Entering Function"); + memset(&sFilterRuleEntry, 0, sizeof(sFilterRuleEntry)); + + if (!CreateBypassRoutingTable(&m_Routing, m_eIP, aBypass, IPA_CLIENT_TEST3_CONS, + 0, &nTableHdl)) { + LOG_MSG_ERROR("CreateBypassRoutingTable Failed\n"); + bRetVal = false; + goto bail; + } + + + LOG_MSG_INFO("Creation of bypass routing table completed successfully"); + + // Creating Filtering Rules + cFilterTable0.Init(m_eIP,IPA_CLIENT_TEST2_PROD, false, 1); + LOG_MSG_INFO("Creation of filtering table completed successfully"); + + // Configuring Filtering Rule No.1 + cFilterTable0.GeneratePresetRule(1,sFilterRuleEntry); + sFilterRuleEntry.at_rear = true; + sFilterRuleEntry.flt_rule_hdl=-1; // return Value + sFilterRuleEntry.status = -1; // return value + sFilterRuleEntry.rule.action=IPA_PASS_TO_ROUTING; + sFilterRuleEntry.rule.retain_hdr = true; + sFilterRuleEntry.rule.rt_tbl_hdl = nTableHdl; //put here the handle corresponding to Routing Rule 1 + sFilterRuleEntry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; // Destination IP Based Filtering + sFilterRuleEntry.rule.attrib.u.v4.dst_addr_mask = 0xFF0000FF; // Mask + sFilterRuleEntry.rule.attrib.u.v4.dst_addr = 0x7F000001; // Filter DST_IP == 127.0.0.1. + if ( + ((uint8_t)-1 == cFilterTable0.AddRuleToTable(sFilterRuleEntry)) || + !m_Filtering.AddFilteringRule(cFilterTable0.GetFilteringTable()) + ) + { + LOG_MSG_ERROR ("Adding Rule (0) to Filtering block Failed."); + bRetVal = false; + goto bail; + } else + { + LOG_MSG_DEBUG("flt rule hdl0=0x%x, status=0x%x\n", cFilterTable0.ReadRuleFromTable(0)->flt_rule_hdl,cFilterTable0.ReadRuleFromTable(0)->status); + } + +bail: + LOG_MSG_STACK( + "Leaving Function (Returning %s)", bRetVal?"True":"False"); + return bRetVal; +} // AddRules() + +bool RNDISAggregationTestFixture::AddRulesAggTimeLimit() { + m_eIP = IPA_IP_v4; + const char aBypass[20] = "Bypass1"; + bool bRetVal = true; + IPAFilteringTable cFilterTable0; + struct ipa_flt_rule_add sFilterRuleEntry; + struct ipa_ioc_get_hdr sGetHeader; + uint32_t nTableHdl; + struct RndisEtherHeader rndisEtherHeader; + + + LOG_MSG_STACK("Entering Function"); + memset(&sFilterRuleEntry, 0, sizeof(sFilterRuleEntry)); + memset(&sGetHeader, 0, sizeof(sGetHeader)); + memset(&rndisEtherHeader, 0, sizeof(struct RndisEtherHeader)); + rndisEtherHeader.rndisHeader.MessageType = 0x01; + rndisEtherHeader.rndisHeader.DataOffset = 0x24; + memcpy(&rndisEtherHeader.etherHeader, Eth2Helper::m_ETH2_IP4_HDR, sizeof(struct ethhdr)); + + // Create Header: + // Allocate Memory, populate it, and add in to the Header Insertion. + struct ipa_ioc_add_hdr * pHeaderDescriptor = NULL; + pHeaderDescriptor = (struct ipa_ioc_add_hdr *) calloc(1, + sizeof(struct ipa_ioc_add_hdr) + + 1 * sizeof(struct ipa_hdr_add)); + if (!pHeaderDescriptor) { + LOG_MSG_ERROR("calloc failed to allocate pHeaderDescriptor"); + bRetVal = false; + goto bail; + } + + pHeaderDescriptor->commit = true; + pHeaderDescriptor->num_hdrs = 1; + // Adding Header No1. + strlcpy(pHeaderDescriptor->hdr[0].name, "RndisEthernet", sizeof(pHeaderDescriptor->hdr[0].name)); // Header's Name + memcpy(pHeaderDescriptor->hdr[0].hdr, (void*)&rndisEtherHeader, + sizeof(struct RndisEtherHeader)); //Header's Data + pHeaderDescriptor->hdr[0].hdr_len = sizeof(struct RndisEtherHeader); + pHeaderDescriptor->hdr[0].hdr_hdl = -1; //Return Value + pHeaderDescriptor->hdr[0].is_partial = false; + pHeaderDescriptor->hdr[0].status = -1; // Return Parameter + + strlcpy(sGetHeader.name, pHeaderDescriptor->hdr[0].name, sizeof(sGetHeader.name)); + + + if (!m_HeaderInsertion.AddHeader(pHeaderDescriptor)) + { + LOG_MSG_ERROR("m_HeaderInsertion.AddHeader(pHeaderDescriptor) Failed."); + bRetVal = false; + goto bail; + } + + if (!m_HeaderInsertion.GetHeaderHandle(&sGetHeader)) + { + LOG_MSG_ERROR(" Failed"); + bRetVal = false; + goto bail; + } + LOG_MSG_DEBUG("Received Header Handle = 0x%x", sGetHeader.hdl); + + + if (!CreateBypassRoutingTable(&m_Routing, m_eIP, aBypass, IPA_CLIENT_TEST_CONS, + sGetHeader.hdl, &nTableHdl)) { + LOG_MSG_ERROR("CreateBypassRoutingTable Failed\n"); + bRetVal = false; + goto bail; + } + + + LOG_MSG_INFO("Creation of bypass routing table completed successfully"); + + // Creating Filtering Rules + cFilterTable0.Init(m_eIP,IPA_CLIENT_TEST3_PROD, false, 1); + LOG_MSG_INFO("Creation of filtering table completed successfully"); + + // Configuring Filtering Rule No.1 + cFilterTable0.GeneratePresetRule(1,sFilterRuleEntry); + sFilterRuleEntry.at_rear = true; + sFilterRuleEntry.flt_rule_hdl=-1; // return Value + sFilterRuleEntry.status = -1; // return value + sFilterRuleEntry.rule.action=IPA_PASS_TO_ROUTING; + sFilterRuleEntry.rule.rt_tbl_hdl = nTableHdl; //put here the handle corresponding to Routing Rule 1 + sFilterRuleEntry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; // Destination IP Based Filtering + sFilterRuleEntry.rule.attrib.u.v4.dst_addr_mask = 0xFF0000FF; // Mask + sFilterRuleEntry.rule.attrib.u.v4.dst_addr = 0x7F000001; // Filter DST_IP == 127.0.0.1. + if ( + ((uint8_t)-1 == cFilterTable0.AddRuleToTable(sFilterRuleEntry)) || + !m_Filtering.AddFilteringRule(cFilterTable0.GetFilteringTable()) + ) + { + LOG_MSG_ERROR ("Adding Rule (0) to Filtering block Failed."); + bRetVal = false; + goto bail; + } else + { + LOG_MSG_DEBUG("flt rule hdl0=0x%x, status=0x%x\n", cFilterTable0.ReadRuleFromTable(0)->flt_rule_hdl,cFilterTable0.ReadRuleFromTable(0)->status); + } + +bail: + Free(pHeaderDescriptor); + LOG_MSG_STACK( + "Leaving Function (Returning %s)", bRetVal?"True":"False"); + return bRetVal; +} // AddRules() + +bool RNDISAggregationTestFixture::AddRulesAggByteLimit() { + m_eIP = IPA_IP_v4; + const char aBypass[20] = "Bypass1"; + bool bRetVal = true; + IPAFilteringTable cFilterTable0; + struct ipa_flt_rule_add sFilterRuleEntry; + struct ipa_ioc_get_hdr sGetHeader; + uint32_t nTableHdl; + struct RndisEtherHeader rndisEtherHeader; + + + LOG_MSG_STACK("Entering Function"); + memset(&sFilterRuleEntry, 0, sizeof(sFilterRuleEntry)); + memset(&sGetHeader, 0, sizeof(sGetHeader)); + memset(&rndisEtherHeader, 0, sizeof(struct RndisEtherHeader)); + + rndisEtherHeader.rndisHeader.MessageType = 0x01; + rndisEtherHeader.rndisHeader.DataOffset = 0x24; + memcpy(&rndisEtherHeader.etherHeader, Eth2Helper::m_ETH2_IP4_HDR, sizeof(struct ethhdr)); + + // Create Header: + // Allocate Memory, populate it, and add in to the Header Insertion. + struct ipa_ioc_add_hdr * pHeaderDescriptor = NULL; + pHeaderDescriptor = (struct ipa_ioc_add_hdr *) calloc(1, + sizeof(struct ipa_ioc_add_hdr) + + 1 * sizeof(struct ipa_hdr_add)); + if (!pHeaderDescriptor) { + LOG_MSG_ERROR("calloc failed to allocate pHeaderDescriptor"); + bRetVal = false; + goto bail; + } + + pHeaderDescriptor->commit = true; + pHeaderDescriptor->num_hdrs = 1; + // Adding Header No1. + strlcpy(pHeaderDescriptor->hdr[0].name, "RndisEthernet", sizeof(pHeaderDescriptor->hdr[0].name)); // Header's Name + memcpy(pHeaderDescriptor->hdr[0].hdr, (void*)&rndisEtherHeader, + sizeof(struct RndisEtherHeader)); //Header's Data + pHeaderDescriptor->hdr[0].hdr_len = sizeof(struct RndisEtherHeader); + pHeaderDescriptor->hdr[0].hdr_hdl = -1; //Return Value + pHeaderDescriptor->hdr[0].is_partial = false; + pHeaderDescriptor->hdr[0].status = -1; // Return Parameter + + strlcpy(sGetHeader.name, pHeaderDescriptor->hdr[0].name, sizeof(sGetHeader.name)); + + + if (!m_HeaderInsertion.AddHeader(pHeaderDescriptor)) + { + LOG_MSG_ERROR("m_HeaderInsertion.AddHeader(pHeaderDescriptor) Failed."); + bRetVal = false; + goto bail; + } + + if (!m_HeaderInsertion.GetHeaderHandle(&sGetHeader)) + { + LOG_MSG_ERROR(" Failed"); + bRetVal = false; + goto bail; + } + LOG_MSG_DEBUG("Received Header Handle = 0x%x", sGetHeader.hdl); + + + if (!CreateBypassRoutingTable(&m_Routing, m_eIP, aBypass, IPA_CLIENT_TEST2_CONS, + sGetHeader.hdl, &nTableHdl)) { + LOG_MSG_ERROR("CreateBypassRoutingTable Failed\n"); + bRetVal = false; + goto bail; + } + + + LOG_MSG_INFO("Creation of bypass routing table completed successfully"); + + // Creating Filtering Rules + cFilterTable0.Init(m_eIP,IPA_CLIENT_TEST3_PROD, false, 1); + LOG_MSG_INFO("Creation of filtering table completed successfully"); + + // Configuring Filtering Rule No.1 + cFilterTable0.GeneratePresetRule(1,sFilterRuleEntry); + sFilterRuleEntry.at_rear = true; + sFilterRuleEntry.flt_rule_hdl=-1; // return Value + sFilterRuleEntry.status = -1; // return value + sFilterRuleEntry.rule.action=IPA_PASS_TO_ROUTING; + sFilterRuleEntry.rule.rt_tbl_hdl = nTableHdl; //put here the handle corresponding to Routing Rule 1 + sFilterRuleEntry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; // Destination IP Based Filtering + sFilterRuleEntry.rule.attrib.u.v4.dst_addr_mask = 0xFF0000FF; // Mask + sFilterRuleEntry.rule.attrib.u.v4.dst_addr = 0x7F000001; // Filter DST_IP == 127.0.0.1. + if ( + ((uint8_t)-1 == cFilterTable0.AddRuleToTable(sFilterRuleEntry)) || + !m_Filtering.AddFilteringRule(cFilterTable0.GetFilteringTable()) + ) + { + LOG_MSG_ERROR ("Adding Rule (0) to Filtering block Failed."); + bRetVal = false; + goto bail; + } else + { + LOG_MSG_DEBUG("flt rule hdl0=0x%x, status=0x%x\n", cFilterTable0.ReadRuleFromTable(0)->flt_rule_hdl,cFilterTable0.ReadRuleFromTable(0)->status); + } + +bail: + Free(pHeaderDescriptor); + LOG_MSG_STACK( + "Leaving Function (Returning %s)", bRetVal?"True":"False"); + return bRetVal; +} // AddRules() + +bool RNDISAggregationTestFixture::AddRulesAggByteLimit(bool bAggForceClose) { + m_eIP = IPA_IP_v4; + const char aBypass[20] = "Bypass1"; + bool bRetVal = true; + IPAFilteringTable_v2 cFilterTable0; + struct ipa_flt_rule_add_v2 sFilterRuleEntry; + struct ipa_ioc_get_hdr sGetHeader; + uint32_t nTableHdl; + struct RndisEtherHeader rndisEtherHeader; + + + LOG_MSG_STACK("Entering Function"); + memset(&sFilterRuleEntry, 0, sizeof(sFilterRuleEntry)); + memset(&sGetHeader, 0, sizeof(sGetHeader)); + memset(&rndisEtherHeader, 0, sizeof(struct RndisEtherHeader)); + + rndisEtherHeader.rndisHeader.MessageType = 0x01; + rndisEtherHeader.rndisHeader.DataOffset = 0x24; + memcpy(&rndisEtherHeader.etherHeader, Eth2Helper::m_ETH2_IP4_HDR, sizeof(struct ethhdr)); + + // Create Header: + // Allocate Memory, populate it, and add in to the Header Insertion. + struct ipa_ioc_add_hdr * pHeaderDescriptor = NULL; + pHeaderDescriptor = (struct ipa_ioc_add_hdr *) calloc(1, + sizeof(struct ipa_ioc_add_hdr) + + 1 * sizeof(struct ipa_hdr_add)); + if (!pHeaderDescriptor) { + LOG_MSG_ERROR("calloc failed to allocate pHeaderDescriptor"); + bRetVal = false; + goto bail; + } + + pHeaderDescriptor->commit = true; + pHeaderDescriptor->num_hdrs = 1; + // Adding Header No1. + strlcpy(pHeaderDescriptor->hdr[0].name, "RndisEthernet", sizeof(pHeaderDescriptor->hdr[0].name)); // Header's Name + memcpy(pHeaderDescriptor->hdr[0].hdr, (void*)&rndisEtherHeader, + sizeof(struct RndisEtherHeader)); //Header's Data + pHeaderDescriptor->hdr[0].hdr_len = sizeof(struct RndisEtherHeader); + pHeaderDescriptor->hdr[0].hdr_hdl = -1; //Return Value + pHeaderDescriptor->hdr[0].is_partial = false; + pHeaderDescriptor->hdr[0].status = -1; // Return Parameter + + strlcpy(sGetHeader.name, pHeaderDescriptor->hdr[0].name, sizeof(sGetHeader.name)); + + + if (!m_HeaderInsertion.AddHeader(pHeaderDescriptor)) + { + LOG_MSG_ERROR("m_HeaderInsertion.AddHeader(pHeaderDescriptor) Failed."); + bRetVal = false; + goto bail; + } + + if (!m_HeaderInsertion.GetHeaderHandle(&sGetHeader)) + { + LOG_MSG_ERROR(" Failed"); + bRetVal = false; + goto bail; + } + LOG_MSG_DEBUG("Received Header Handle = 0x%x", sGetHeader.hdl); + + + if (!CreateBypassRoutingTable_v2(&m_Routing, m_eIP, aBypass, IPA_CLIENT_TEST2_CONS, + sGetHeader.hdl, &nTableHdl, 0)) { + LOG_MSG_ERROR("CreateBypassRoutingTable Failed\n"); + bRetVal = false; + goto bail; + } + + + LOG_MSG_INFO("Creation of bypass routing table completed successfully"); + + // Creating Filtering Rules + cFilterTable0.Init(m_eIP,IPA_CLIENT_TEST3_PROD, false, 1); + LOG_MSG_INFO("Creation of filtering table completed successfully"); + + // Configuring Filtering Rule No.1 + cFilterTable0.GeneratePresetRule(1,sFilterRuleEntry); + sFilterRuleEntry.at_rear = true; + sFilterRuleEntry.flt_rule_hdl=-1; // return Value + sFilterRuleEntry.status = -1; // return value + sFilterRuleEntry.rule.action=IPA_PASS_TO_ROUTING; + sFilterRuleEntry.rule.rt_tbl_hdl = nTableHdl; //put here the handle corresponding to Routing Rule 1 + printf("%s(), Nadav: sFilterRuleEntry.rule.rt_tbl_hdl = %d \n", __FUNCTION__, nTableHdl); + sFilterRuleEntry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; // Destination IP Based Filtering + sFilterRuleEntry.rule.attrib.u.v4.dst_addr_mask = 0xFF0000FF; // Mask + sFilterRuleEntry.rule.attrib.u.v4.dst_addr = 0x7F000001; // Filter DST_IP == 127.0.0.1. + sFilterRuleEntry.rule.close_aggr_irq_mod = bAggForceClose; + if ( + ((uint8_t)-1 == cFilterTable0.AddRuleToTable(sFilterRuleEntry)) || + !m_Filtering.AddFilteringRule(cFilterTable0.GetFilteringTable()) + ) + { + LOG_MSG_ERROR ("Adding Rule (0) to Filtering block Failed."); + bRetVal = false; + goto bail; + } else + { + LOG_MSG_DEBUG("flt rule hdl0=0x%x, status=0x%x\n", cFilterTable0.ReadRuleFromTable(0)->flt_rule_hdl,cFilterTable0.ReadRuleFromTable(0)->status); + } + +bail: + Free(pHeaderDescriptor); + LOG_MSG_STACK( + "Leaving Function (Returning %s)", bRetVal?"True":"False"); + return bRetVal; +} // AddRules() + +bool RNDISAggregationTestFixture::AddRulesAggPacketLimit() { + m_eIP = IPA_IP_v4; + const char aBypass[20] = "Bypass1"; + bool bRetVal = true; + IPAFilteringTable cFilterTable0; + struct ipa_flt_rule_add sFilterRuleEntry; + struct ipa_ioc_get_hdr sGetHeader; + uint32_t nTableHdl; + struct RndisEtherHeader rndisEtherHeader; + + + LOG_MSG_STACK("Entering Function"); + memset(&sFilterRuleEntry, 0, sizeof(sFilterRuleEntry)); + memset(&sGetHeader, 0, sizeof(sGetHeader)); + memset(&rndisEtherHeader, 0, sizeof(struct RndisEtherHeader)); + + rndisEtherHeader.rndisHeader.MessageType = 0x01; + rndisEtherHeader.rndisHeader.DataOffset = 0x24; + memcpy(&rndisEtherHeader.etherHeader, Eth2Helper::m_ETH2_IP4_HDR, sizeof(struct ethhdr)); + + // Create Header: + // Allocate Memory, populate it, and add in to the Header Insertion. + struct ipa_ioc_add_hdr * pHeaderDescriptor = NULL; + pHeaderDescriptor = (struct ipa_ioc_add_hdr *) calloc(1, + sizeof(struct ipa_ioc_add_hdr) + + 1 * sizeof(struct ipa_hdr_add)); + if (!pHeaderDescriptor) { + LOG_MSG_ERROR("calloc failed to allocate pHeaderDescriptor"); + bRetVal = false; + goto bail; + } + + pHeaderDescriptor->commit = true; + pHeaderDescriptor->num_hdrs = 1; + // Adding Header No1. + strlcpy(pHeaderDescriptor->hdr[0].name, "RndisEthernet", sizeof(pHeaderDescriptor->hdr[0].name)); // Header's Name + memcpy(pHeaderDescriptor->hdr[0].hdr, (void*)&rndisEtherHeader, + sizeof(struct RndisEtherHeader)); //Header's Data + pHeaderDescriptor->hdr[0].hdr_len = sizeof(struct RndisEtherHeader); + pHeaderDescriptor->hdr[0].hdr_hdl = -1; //Return Value + pHeaderDescriptor->hdr[0].is_partial = false; + pHeaderDescriptor->hdr[0].status = -1; // Return Parameter + + strlcpy(sGetHeader.name, pHeaderDescriptor->hdr[0].name, sizeof(sGetHeader.name)); + + + if (!m_HeaderInsertion.AddHeader(pHeaderDescriptor)) + { + LOG_MSG_ERROR("m_HeaderInsertion.AddHeader(pHeaderDescriptor) Failed."); + bRetVal = false; + goto bail; + } + + if (!m_HeaderInsertion.GetHeaderHandle(&sGetHeader)) + { + LOG_MSG_ERROR(" Failed"); + bRetVal = false; + goto bail; + } + LOG_MSG_DEBUG("Received Header Handle = 0x%x", sGetHeader.hdl); + + + if (!CreateBypassRoutingTable(&m_Routing, m_eIP, aBypass, IPA_CLIENT_TEST4_CONS, + sGetHeader.hdl, &nTableHdl)) { + LOG_MSG_ERROR("CreateBypassRoutingTable Failed\n"); + bRetVal = false; + goto bail; + } + + + LOG_MSG_INFO("Creation of bypass routing table completed successfully"); + + // Creating Filtering Rules + cFilterTable0.Init(m_eIP,IPA_CLIENT_TEST3_PROD, false, 1); + LOG_MSG_INFO("Creation of filtering table completed successfully"); + + // Configuring Filtering Rule No.1 + cFilterTable0.GeneratePresetRule(1,sFilterRuleEntry); + sFilterRuleEntry.at_rear = true; + sFilterRuleEntry.flt_rule_hdl=-1; // return Value + sFilterRuleEntry.status = -1; // return value + sFilterRuleEntry.rule.action=IPA_PASS_TO_ROUTING; + sFilterRuleEntry.rule.rt_tbl_hdl = nTableHdl; //put here the handle corresponding to Routing Rule 1 + sFilterRuleEntry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; // Destination IP Based Filtering + sFilterRuleEntry.rule.attrib.u.v4.dst_addr_mask = 0xFF0000FF; // Mask + sFilterRuleEntry.rule.attrib.u.v4.dst_addr = 0x7F000001; // Filter DST_IP == 127.0.0.1. + if ( + ((uint8_t)-1 == cFilterTable0.AddRuleToTable(sFilterRuleEntry)) || + !m_Filtering.AddFilteringRule(cFilterTable0.GetFilteringTable()) + ) + { + LOG_MSG_ERROR ("Adding Rule (0) to Filtering block Failed."); + bRetVal = false; + goto bail; + } else + { + LOG_MSG_DEBUG("flt rule hdl0=0x%x, status=0x%x\n", cFilterTable0.ReadRuleFromTable(0)->flt_rule_hdl,cFilterTable0.ReadRuleFromTable(0)->status); + } + +bail: + Free(pHeaderDescriptor); + LOG_MSG_STACK( + "Leaving Function (Returning %s)", bRetVal?"True":"False"); + return bRetVal; +} // AddRules() + + + +bool RNDISAggregationTestFixture::AddRulesAggDualFC() { + m_eIP = IPA_IP_v4; + const char aBypass[2][20] = {"BypassTest2", "BypassTest4"}; + bool bRetVal = true; + IPAFilteringTable_v2 cFilterTable0; + struct ipa_flt_rule_add_v2 sFilterRuleEntry; + struct ipa_ioc_get_hdr sGetHeader; + uint32_t nTableHdl[2]; + struct RndisEtherHeader rndisEtherHeader; + + + LOG_MSG_STACK("Entering Function"); + memset(&sFilterRuleEntry, 0, sizeof(sFilterRuleEntry)); + memset(&sGetHeader, 0, sizeof(sGetHeader)); + memset(&rndisEtherHeader, 0, sizeof(struct RndisEtherHeader)); + + rndisEtherHeader.rndisHeader.MessageType = 0x01; + rndisEtherHeader.rndisHeader.DataOffset = 0x24; + memcpy(&rndisEtherHeader.etherHeader, Eth2Helper::m_ETH2_IP4_HDR, sizeof(struct ethhdr)); + + // Create Header: + // Allocate Memory, populate it, and add in to the Header Insertion. + struct ipa_ioc_add_hdr * pHeaderDescriptor = NULL; + pHeaderDescriptor = (struct ipa_ioc_add_hdr *) calloc(1, + sizeof(struct ipa_ioc_add_hdr) + + 1 * sizeof(struct ipa_hdr_add)); + if (!pHeaderDescriptor) { + LOG_MSG_ERROR("calloc failed to allocate pHeaderDescriptor"); + bRetVal = false; + goto bail; + } + + pHeaderDescriptor->commit = true; + pHeaderDescriptor->num_hdrs = 1; + // Adding Header No1. + strlcpy(pHeaderDescriptor->hdr[0].name, "RndisEthernet", sizeof(pHeaderDescriptor->hdr[0].name)); // Header's Name + memcpy(pHeaderDescriptor->hdr[0].hdr, (void*)&rndisEtherHeader, + sizeof(struct RndisEtherHeader)); //Header's Data + pHeaderDescriptor->hdr[0].hdr_len = sizeof(struct RndisEtherHeader); + pHeaderDescriptor->hdr[0].hdr_hdl = -1; //Return Value + pHeaderDescriptor->hdr[0].is_partial = false; + pHeaderDescriptor->hdr[0].status = -1; // Return Parameter + + strlcpy(sGetHeader.name, pHeaderDescriptor->hdr[0].name, sizeof(sGetHeader.name)); + + + if (!m_HeaderInsertion.AddHeader(pHeaderDescriptor)) + { + LOG_MSG_ERROR("m_HeaderInsertion.AddHeader(pHeaderDescriptor) Failed."); + bRetVal = false; + goto bail; + } + + if (!m_HeaderInsertion.GetHeaderHandle(&sGetHeader)) + { + LOG_MSG_ERROR(" Failed"); + bRetVal = false; + goto bail; + } + LOG_MSG_DEBUG("Received Header Handle = 0x%x", sGetHeader.hdl); + + if (!CreateBypassRoutingTable_v2(&m_Routing, m_eIP, aBypass[0], + IPA_CLIENT_TEST2_CONS, + sGetHeader.hdl, &nTableHdl[0], 0)) { + LOG_MSG_ERROR("CreateSplitRoutingTable Failed\n"); + bRetVal = false; + goto bail; + } + + if (!CreateBypassRoutingTable_v2(&m_Routing, m_eIP, aBypass[1], + IPA_CLIENT_TEST4_CONS, + sGetHeader.hdl, &nTableHdl[1], 0)) { + LOG_MSG_ERROR("CreateSplitRoutingTable Failed\n"); + bRetVal = false; + goto bail; + } + + LOG_MSG_INFO("Creation of bypass routing tables completed successfully"); + + // Creating Filtering Rules + cFilterTable0.Init(m_eIP,IPA_CLIENT_TEST3_PROD, false, 2); + LOG_MSG_INFO("Creation of filtering table completed successfully"); + + // Configuring Filtering Rule No.1 + cFilterTable0.GeneratePresetRule(1,sFilterRuleEntry); + sFilterRuleEntry.at_rear = true; + sFilterRuleEntry.flt_rule_hdl=-1; // return Value + sFilterRuleEntry.status = -1; // return value + sFilterRuleEntry.rule.action=IPA_PASS_TO_ROUTING; + sFilterRuleEntry.rule.rt_tbl_hdl = nTableHdl[0]; //put here the handle corresponding to Routing Rule 1 + sFilterRuleEntry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; // Destination IP Based Filtering + sFilterRuleEntry.rule.attrib.u.v4.dst_addr_mask = 0xFF0000FF; // Mask + sFilterRuleEntry.rule.attrib.u.v4.dst_addr = 0x7F000001; // Filter DST_IP == 127.0.0.1. + sFilterRuleEntry.rule.close_aggr_irq_mod = 1; + if ( + ((uint8_t)-1 == cFilterTable0.AddRuleToTable(sFilterRuleEntry)) || + !m_Filtering.AddFilteringRule(cFilterTable0.GetFilteringTable()) + ) + { + LOG_MSG_ERROR ("Adding Rule (0) to Filtering block Failed."); + bRetVal = false; + goto bail; + } else + { + LOG_MSG_DEBUG("flt rule hdl0=0x%x, status=0x%x\n", cFilterTable0.ReadRuleFromTable(0)->flt_rule_hdl,cFilterTable0.ReadRuleFromTable(0)->status); + } + + // Configuring Filtering Rule No.2 + cFilterTable0.GeneratePresetRule(1,sFilterRuleEntry); + sFilterRuleEntry.at_rear = true; + sFilterRuleEntry.flt_rule_hdl=-1; // return Value + sFilterRuleEntry.status = -1; // return value + sFilterRuleEntry.rule.action=IPA_PASS_TO_ROUTING; + sFilterRuleEntry.rule.rt_tbl_hdl = nTableHdl[1]; //put here the handle corresponding to Routing Rule 1 + sFilterRuleEntry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; // Destination IP Based Filtering + sFilterRuleEntry.rule.attrib.u.v4.dst_addr_mask = 0xFF0000FF; // Mask + sFilterRuleEntry.rule.attrib.u.v4.dst_addr = 0x7F000002; // Filter DST_IP == 127.0.0.1. + sFilterRuleEntry.rule.close_aggr_irq_mod = 0; + if ( + ((uint8_t)-1 == cFilterTable0.AddRuleToTable(sFilterRuleEntry)) || + !m_Filtering.AddFilteringRule(cFilterTable0.GetFilteringTable()) + ) + { + LOG_MSG_ERROR ("Adding Rule (1) to Filtering block Failed."); + bRetVal = false; + goto bail; + } else + { + LOG_MSG_DEBUG("flt rule hdl1=0x%x, status=0x%x\n", cFilterTable0.ReadRuleFromTable(1)->flt_rule_hdl,cFilterTable0.ReadRuleFromTable(1)->status); + } + +bail: + Free(pHeaderDescriptor); + LOG_MSG_STACK( + "Leaving Function (Returning %s)", bRetVal?"True":"False"); + return bRetVal; +} // AddRulesAggDualFC() + +bool RNDISAggregationTestFixture::AddRulesAggDualFcRoutingBased() { + m_eIP = IPA_IP_v4; + const char aBypass[2][20] = {"BypassTest2", "BypassTest4"}; + bool bRetVal = true; + IPAFilteringTable_v2 cFilterTable0; + struct ipa_flt_rule_add_v2 sFilterRuleEntry; + struct ipa_ioc_get_hdr sGetHeader; + uint32_t nTableHdl[2]; + struct RndisEtherHeader rndisEtherHeader; + + + LOG_MSG_STACK("Entering Function"); + memset(&sFilterRuleEntry, 0, sizeof(sFilterRuleEntry)); + memset(&sGetHeader, 0, sizeof(sGetHeader)); + memset(&rndisEtherHeader, 0, sizeof(struct RndisEtherHeader)); + + rndisEtherHeader.rndisHeader.MessageType = 0x01; + rndisEtherHeader.rndisHeader.DataOffset = 0x24; + memcpy(&rndisEtherHeader.etherHeader, Eth2Helper::m_ETH2_IP4_HDR, sizeof(struct ethhdr)); + + // Create Header: + // Allocate Memory, populate it, and add in to the Header Insertion. + struct ipa_ioc_add_hdr * pHeaderDescriptor = NULL; + pHeaderDescriptor = (struct ipa_ioc_add_hdr *) calloc(1, + sizeof(struct ipa_ioc_add_hdr) + + 1 * sizeof(struct ipa_hdr_add)); + if (!pHeaderDescriptor) { + LOG_MSG_ERROR("calloc failed to allocate pHeaderDescriptor"); + bRetVal = false; + goto bail; + } + + pHeaderDescriptor->commit = true; + pHeaderDescriptor->num_hdrs = 1; + // Adding Header No1. + strlcpy(pHeaderDescriptor->hdr[0].name, "RndisEthernet", sizeof(pHeaderDescriptor->hdr[0].name)); // Header's Name + memcpy(pHeaderDescriptor->hdr[0].hdr, (void*)&rndisEtherHeader, + sizeof(struct RndisEtherHeader)); //Header's Data + pHeaderDescriptor->hdr[0].hdr_len = sizeof(struct RndisEtherHeader); + pHeaderDescriptor->hdr[0].hdr_hdl = -1; //Return Value + pHeaderDescriptor->hdr[0].is_partial = false; + pHeaderDescriptor->hdr[0].status = -1; // Return Parameter + + strlcpy(sGetHeader.name, pHeaderDescriptor->hdr[0].name, sizeof(sGetHeader.name)); + + + if (!m_HeaderInsertion.AddHeader(pHeaderDescriptor)) + { + LOG_MSG_ERROR("m_HeaderInsertion.AddHeader(pHeaderDescriptor) Failed."); + bRetVal = false; + goto bail; + } + + if (!m_HeaderInsertion.GetHeaderHandle(&sGetHeader)) + { + LOG_MSG_ERROR(" Failed"); + bRetVal = false; + goto bail; + } + LOG_MSG_DEBUG("Received Header Handle = 0x%x", sGetHeader.hdl); + + if (!CreateBypassRoutingTable_v2(&m_Routing, m_eIP, aBypass[0], + IPA_CLIENT_TEST2_CONS, + sGetHeader.hdl, &nTableHdl[0], 1)) { + LOG_MSG_ERROR("CreateSplitRoutingTable Failed\n"); + bRetVal = false; + goto bail; + } + + if (!CreateBypassRoutingTable_v2(&m_Routing, m_eIP, aBypass[1], + IPA_CLIENT_TEST4_CONS, + sGetHeader.hdl, &nTableHdl[1], 0)) { + LOG_MSG_ERROR("CreateSplitRoutingTable Failed\n"); + bRetVal = false; + goto bail; + } + + LOG_MSG_INFO("Creation of bypass routing tables completed successfully"); + + // Creating Filtering Rules + cFilterTable0.Init(m_eIP,IPA_CLIENT_TEST3_PROD, false, 2); + LOG_MSG_INFO("Creation of filtering table completed successfully"); + + // Configuring Filtering Rule No.1 + cFilterTable0.GeneratePresetRule(1,sFilterRuleEntry); + sFilterRuleEntry.at_rear = true; + sFilterRuleEntry.flt_rule_hdl=-1; // return Value + sFilterRuleEntry.status = -1; // return value + sFilterRuleEntry.rule.action=IPA_PASS_TO_ROUTING; + sFilterRuleEntry.rule.rt_tbl_hdl = nTableHdl[0]; //put here the handle corresponding to Routing Rule 1 + sFilterRuleEntry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; // Destination IP Based Filtering + sFilterRuleEntry.rule.attrib.u.v4.dst_addr_mask = 0xFF0000FF; // Mask + sFilterRuleEntry.rule.attrib.u.v4.dst_addr = 0x7F000001; // Filter DST_IP == 127.0.0.1. + sFilterRuleEntry.rule.close_aggr_irq_mod = 0; + if ( + ((uint8_t)-1 == cFilterTable0.AddRuleToTable(sFilterRuleEntry)) || + !m_Filtering.AddFilteringRule(cFilterTable0.GetFilteringTable()) + ) + { + LOG_MSG_ERROR ("Adding Rule (0) to Filtering block Failed."); + bRetVal = false; + goto bail; + } else + { + LOG_MSG_DEBUG("flt rule hdl0=0x%x, status=0x%x\n", cFilterTable0.ReadRuleFromTable(0)->flt_rule_hdl,cFilterTable0.ReadRuleFromTable(0)->status); + } + + // Configuring Filtering Rule No.2 + cFilterTable0.GeneratePresetRule(1,sFilterRuleEntry); + sFilterRuleEntry.at_rear = true; + sFilterRuleEntry.flt_rule_hdl=-1; // return Value + sFilterRuleEntry.status = -1; // return value + sFilterRuleEntry.rule.action=IPA_PASS_TO_ROUTING; + sFilterRuleEntry.rule.rt_tbl_hdl = nTableHdl[1]; //put here the handle corresponding to Routing Rule 1 + sFilterRuleEntry.rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; // Destination IP Based Filtering + sFilterRuleEntry.rule.attrib.u.v4.dst_addr_mask = 0xFF0000FF; // Mask + sFilterRuleEntry.rule.attrib.u.v4.dst_addr = 0x7F000002; // Filter DST_IP == 127.0.0.1. + sFilterRuleEntry.rule.close_aggr_irq_mod = 0; + if ( + ((uint8_t)-1 == cFilterTable0.AddRuleToTable(sFilterRuleEntry)) || + !m_Filtering.AddFilteringRule(cFilterTable0.GetFilteringTable()) + ) + { + LOG_MSG_ERROR ("Adding Rule (1) to Filtering block Failed."); + bRetVal = false; + goto bail; + } else + { + LOG_MSG_DEBUG("flt rule hdl1=0x%x, status=0x%x\n", cFilterTable0.ReadRuleFromTable(1)->flt_rule_hdl,cFilterTable0.ReadRuleFromTable(1)->status); + } + +bail: + Free(pHeaderDescriptor); + LOG_MSG_STACK( + "Leaving Function (Returning %s)", bRetVal?"True":"False"); + return bRetVal; +} // AddRulesAggDualFcRoutingBased() + diff --git a/qcom/opensource/dataipa/kernel-tests/RNDISAggregationTestFixture.h b/qcom/opensource/dataipa/kernel-tests/RNDISAggregationTestFixture.h new file mode 100644 index 0000000000..a5e012f121 --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/RNDISAggregationTestFixture.h @@ -0,0 +1,113 @@ +/* + * Copyright (c) 2017,2020 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include + +#include "Constants.h" +#include "Logger.h" +#include "linux/msm_ipa.h" +#include "TestsUtils.h" +#include "TestBase.h" +#include "Pipe.h" +#include "RoutingDriverWrapper.h" +#include "HeaderInsertion.h" +#include "Filtering.h" +#include "IPAFilteringTable.h" +#define MAX_PACKET_SIZE 1024 + +/*This class will be the base class of RNDIS Aggregation tests. + *Any method other than the test case itself can be + *declared in this Fixture thus allowing the derived classes to + *implement only the test case. + *All the test of the Aggregation uses one input and one output in DMA mode. + */ +class RNDISAggregationTestFixture:public TestBase +{ +public: + /*This Constructor will register each instance that it creates.*/ + RNDISAggregationTestFixture(); + + /*This method will create and initialize two Pipe object for the USB + *(Ethernet) Pipes, one as input and the other as output. + */ + virtual bool Setup(); + + /*This method will destroy the pipes.*/ + virtual bool Teardown(); + + virtual bool Run(); + + virtual bool AddRules() = 0; + + virtual bool TestLogic() = 0; + + bool AddRulesNoAgg(); + + bool AddRulesDeAggEther(); + + bool AddRulesAggTimeLimit(); + + bool AddRulesAggByteLimit(); + + bool AddRulesAggByteLimit(bool bAggForceClose); + + bool AddRulesAggPacketLimit(); + + bool AddRulesAggDualFC(); + + bool AddRulesAggDualFcRoutingBased(); + + /*The client type are set from the peripheral perspective*/ + static Pipe m_IpaToUsbPipeAgg; + /*IPA_CLIENT_TEST2_CONS (pipe_num = 7)*/ + static Pipe m_UsbToIpaPipe; + /* IPA_CLIENT_TEST_PROD (pipe_num = 11)*/ + static Pipe m_IpaToUsbPipe; + /* IPA_CLIENT_TEST3_CONS (pipe_num = 9)*/ + static Pipe m_UsbToIpaPipeDeagg; + /* IPA_CLIENT_TEST2_PROD (pipe_num = 6)*/ + static Pipe m_IpaToUsbPipeAggTime; + /* IPA_CLIENT_TEST_CONS (pipe_num = 10)*/ + static Pipe m_IpaToUsbPipeAggPktLimit; + /* IPA_CLIENT_TEST4_CONS (pipe_num = 4)*/ + static Pipe m_HsicToIpaPipe; + /* IPA_CLIENT_TEST3_PROD (pipe_num = 13)*/ + + static RoutingDriverWrapper m_Routing; + static Filtering m_Filtering; + static HeaderInsertion m_HeaderInsertion; + +protected: + enum ipa_ip_type m_eIP; +}; diff --git a/qcom/opensource/dataipa/kernel-tests/RNDISAggregationTests.cpp b/qcom/opensource/dataipa/kernel-tests/RNDISAggregationTests.cpp new file mode 100644 index 0000000000..7664a8df83 --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/RNDISAggregationTests.cpp @@ -0,0 +1,1265 @@ +/* + * Copyright (c) 2017,2020 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include "hton.h" /* for htonl*/ +#include "RNDISAggregationTestFixture.h" +#include "Constants.h" +#include "TestsUtils.h" +#include "linux/msm_ipa.h" + +#define IPV4_DST_ADDR_OFFSET (16) +#define IPV4_DST_ADDR_OFFSET_IN_ETH \ + (16 /* IP */ + 14 /* ethernet */) +#define IPV4_DST_ADDR_OFFSET_IN_RNDIS \ + (IPV4_DST_ADDR_OFFSET_IN_ETH + \ + sizeof(struct RndisHeader)) + +#define NUM_PACKETS (4) + +class RNDISAggregationSanityTest: public RNDISAggregationTestFixture { +public: + + ///////////////////////////////////////////////////////////////////////////////// + + RNDISAggregationSanityTest() + { + m_name = "RNDISAggregationSanityTest"; + m_description = "RNDISAggregationSanityTest - Send one packet " + "and expect same packet."; + } + + ///////////////////////////////////////////////////////////////////////////////// + + virtual bool AddRules() + { + return AddRulesNoAgg(); + } // AddRules() + + ///////////////////////////////////////////////////////////////////////////////// + + bool TestLogic() + { + //The packets that will be sent + Byte pPacket[MAX_PACKET_SIZE]; + //Buffer for the packet that will be received + Byte pReceivedPacket[2*MAX_PACKET_SIZE]; + //Total size of all sent packets (this is the max size of the aggregated + //packet minus the size of the header and the NDP) + //int nTotalPacketsSize = MAX_PACKET_SIZE - (4 * NUM_PACKETS) - 24; + uint32_t nIPv4DSTAddr; + size_t pIpPacketsSize; + + //initialize the packets + // Load input data (Ethernet packet) from file + pIpPacketsSize = MAX_PACKET_SIZE; + if (!RNDISAggregationHelper::LoadEtherPacket(m_eIP, pPacket, pIpPacketsSize)) + { + LOG_MSG_ERROR("Failed default Packet"); + return false; + } + nIPv4DSTAddr = ntohl(0x7F000001); + memcpy (&pPacket[IPV4_DST_ADDR_OFFSET_IN_ETH],&nIPv4DSTAddr, + sizeof(nIPv4DSTAddr)); + + + //send the packet + LOG_MSG_DEBUG("Sending packet into the A2 EMB pipe(%d bytes)\n", + pIpPacketsSize); + size_t nBytesSent = m_UsbToIpaPipe.Send(pPacket, pIpPacketsSize); + if (pIpPacketsSize != nBytesSent) + { + LOG_MSG_ERROR("Sending packet into the A2 EMB pipe(%d bytes) " + "failed!\n", pIpPacketsSize); + return false; + } + + //receive the packet + LOG_MSG_DEBUG("Reading packet from the A2 EMB pipe(%d bytes should be there)" + "\n", pIpPacketsSize); + size_t nBytesReceived = m_IpaToUsbPipe.Receive(pReceivedPacket, MAX_PACKET_SIZE); + if (pIpPacketsSize != nBytesReceived) + { + LOG_MSG_ERROR("Receiving aggregated packet from the USB pipe(%d bytes) " + "failed!\n", pIpPacketsSize); + print_buff(pReceivedPacket, nBytesReceived); + return false; + } + return RNDISAggregationHelper::ComparePackets(pReceivedPacket, nBytesReceived, + pPacket, pIpPacketsSize); + } + + ///////////////////////////////////////////////////////////////////////////////// +}; + +class RNDISAggregationDeaggregation1PacketTest: public RNDISAggregationTestFixture { +public: + + ///////////////////////////////////////////////////////////////////////////////// + + RNDISAggregationDeaggregation1PacketTest() + { + m_name = "RNDISAggregationDeaggregation1PacketTest"; + m_description = "RNDISAggregationDeaggregation1PacketTest - Send 1 RNDIS packet " + "and expect Ethernet packet."; + } + + ///////////////////////////////////////////////////////////////////////////////// + + virtual bool AddRules() + { + return AddRulesDeAggEther(); + } // AddRules() + + ///////////////////////////////////////////////////////////////////////////////// + + bool TestLogic() + { + //The packets that will be sent + Byte pPacket[MAX_PACKET_SIZE]; + //Buffer for the packet that will be received + Byte pReceivedPacket[2*MAX_PACKET_SIZE]; + //Total size of all sent packets (this is the max size of the aggregated + //packet minus the size of the header and the NDP) + //int nTotalPacketsSize = MAX_PACKET_SIZE - (4 * NUM_PACKETS) - 24; + uint32_t nIPv4DSTAddr; + size_t pIpPacketsSize; + + //initialize the packets + // Load input data (IP packet) from file + pIpPacketsSize = MAX_PACKET_SIZE; + if (!RNDISAggregationHelper::LoadRNDISPacket(m_eIP, pPacket, pIpPacketsSize)) + { + LOG_MSG_ERROR("Failed to load RNDIS Packet"); + return false; + } + nIPv4DSTAddr = ntohl(0x7F000001); + memcpy (&pPacket[IPV4_DST_ADDR_OFFSET_IN_RNDIS],&nIPv4DSTAddr, + sizeof(nIPv4DSTAddr)); + + //send the packet + LOG_MSG_DEBUG("Sending packet into the A2 TETH pipe(%d bytes)\n", + pIpPacketsSize); + size_t nBytesSent = m_UsbToIpaPipeDeagg.Send(pPacket, pIpPacketsSize); + if (pIpPacketsSize != nBytesSent) + { + LOG_MSG_ERROR("Sending packet into the A2 EMB pipe(%d bytes) " + "failed!\n", pIpPacketsSize); + return false; + } + + //receive the packet + LOG_MSG_DEBUG("Reading packet from the A2 TETH pipe(%d bytes should be there)" + "\n", pIpPacketsSize); + size_t nBytesReceived = m_IpaToUsbPipe.Receive(pReceivedPacket, MAX_PACKET_SIZE); + if (pIpPacketsSize - sizeof(struct RndisHeader) != nBytesReceived) + { + LOG_MSG_ERROR("Receiving aggregated packet from the USB pipe(%d bytes) " + "failed!\n", pIpPacketsSize); + print_buff(pReceivedPacket, nBytesReceived); + return false; + } + return RNDISAggregationHelper::CompareEthervsRNDISPacket(pReceivedPacket, nBytesReceived, + pPacket, pIpPacketsSize); + } + + ///////////////////////////////////////////////////////////////////////////////// +}; + +class RNDISAggregation1PacketTest: public RNDISAggregationTestFixture { +public: + + ///////////////////////////////////////////////////////////////////////////////// + + RNDISAggregation1PacketTest() + { + m_name = "RNDISAggregation1PacketTest"; + m_description = "RNDISAggregation1PacketTest - Send 1 IP packet " + "and expect RNDIS packet."; + } + + ///////////////////////////////////////////////////////////////////////////////// + + virtual bool AddRules() + { + return AddRulesAggTimeLimit(); + } // AddRules() + + ///////////////////////////////////////////////////////////////////////////////// + + bool TestLogic() + { + //The packets that will be sent + Byte pPacket[MAX_PACKET_SIZE]; + //Buffer for the packet that will be received + Byte pReceivedPacket[2*MAX_PACKET_SIZE]; + //Total size of all sent packets (this is the max size of the aggregated + //packet minus the size of the header and the NDP) + //int nTotalPacketsSize = MAX_PACKET_SIZE - (4 * NUM_PACKETS) - 24; + uint32_t nIPv4DSTAddr; + size_t pIpPacketsSize; + + //initialize the packets + // Load input data (IP packet) from file + pIpPacketsSize = MAX_PACKET_SIZE; + if (!LoadDefaultPacket(m_eIP, pPacket, pIpPacketsSize)) + { + LOG_MSG_ERROR("Failed to load Ethernet Packet"); + return false; + } + nIPv4DSTAddr = ntohl(0x7F000001); + memcpy (&pPacket[IPV4_DST_ADDR_OFFSET],&nIPv4DSTAddr, + sizeof(nIPv4DSTAddr)); + + //send the packet + LOG_MSG_DEBUG("Sending packet into the USB pipe(%d bytes)\n", + pIpPacketsSize); + size_t nBytesSent = m_HsicToIpaPipe.Send(pPacket, pIpPacketsSize); + if (pIpPacketsSize != nBytesSent) + { + LOG_MSG_ERROR("Sending packet into the USB pipe(%d bytes) " + "failed!\n", pIpPacketsSize); + return false; + } + + //receive the packet + LOG_MSG_DEBUG("Reading packet from the USB pipe(%d bytes should be there)" + "\n", pIpPacketsSize); + size_t nBytesReceived = m_IpaToUsbPipeAggTime.Receive(pReceivedPacket, MAX_PACKET_SIZE); + if (pIpPacketsSize != nBytesReceived - sizeof(struct RndisEtherHeader)) + { + LOG_MSG_ERROR("Receiving aggregated packet from the USB pipe(%d bytes) " + "failed!\n", pIpPacketsSize); + print_buff(pReceivedPacket, nBytesReceived); + return false; + } + + + return RNDISAggregationHelper::CompareIPvsRNDISPacket(pPacket, pIpPacketsSize, + pReceivedPacket, nBytesReceived); + } + + ///////////////////////////////////////////////////////////////////////////////// +}; + +class RNDISAggregationSuspendWaTest: public RNDISAggregationTestFixture { +public: + ///////////////////////////////////////////////////////////////////////////////// + + RNDISAggregationSuspendWaTest() + { + m_name = "RNDISAggregationSuspendWaTest"; + m_description = "RNDISAggregationSuspendWaTest - Send 3 IP packet instead 4, suspend the pipe" + " and expect aggregation to be closed."; + m_minIPAHwType = IPA_HW_v3_0; + + // WA not needed in IPA_3_5 + m_maxIPAHwType = IPA_HW_v3_1; + } + + ///////////////////////////////////////////////////////////////////////////////// + + virtual bool AddRules() + { + return AddRulesAggByteLimit(); + } // AddRules() + + ///////////////////////////////////////////////////////////////////////////////// + + bool Setup() + { + bool bRetVal = true; + + bRetVal = RNDISAggregationTestFixture::Setup(); + if (bRetVal == false) { + return bRetVal; + } + + /* register test framework suspend handler to from_ipa_devs */ + bRetVal = RegSuspendHandler(false, true, 0); + + return bRetVal; + } + + bool TestLogic() + { + /*The packets that will be sent*/ + + Byte pPackets[NUM_PACKETS][MAX_PACKET_SIZE]; + /*Buffer for the packet that will be received*/ + Byte pReceivedPacket[2*MAX_PACKET_SIZE]; + /* + *Total size of all sent packets + * (this is the max size of the aggregated + *packet minus the size of the header and the NDP) + */ + uint32_t nIPv4DSTAddr; + size_t pIpPacketsSizes[NUM_PACKETS]; + size_t ExpectedPacketSize = (NUM_PACKETS - 1) * sizeof(struct RndisEtherHeader); + + struct ipa_test_ep_ctrl ep_ctrl; + + /* send one packet less than aggregation size in order to see the force close */ + for(int i = 0; i < (NUM_PACKETS - 1); i++) { + /* + *initialize the packets + *Load input data (IP packet) from file + */ + pIpPacketsSizes[i] = MAX_PACKET_SIZE; + if (!LoadDefaultPacket(m_eIP, pPackets[i], pIpPacketsSizes[i])) + { + LOG_MSG_ERROR("Failed to load Ethernet Packet"); + return false; + } + nIPv4DSTAddr = ntohl(0x7F000001); + memcpy (&pPackets[i][IPV4_DST_ADDR_OFFSET],&nIPv4DSTAddr, + sizeof(nIPv4DSTAddr)); + for(int j = pIpPacketsSizes[i]; j < MAX_PACKET_SIZE / NUM_PACKETS + 1; j++) { + pPackets[i][j] = j & 0xFF; + } + pIpPacketsSizes[i] = MAX_PACKET_SIZE / NUM_PACKETS + 1; + + /* send the packet */ + LOG_MSG_DEBUG("Sending packet into the A2 TETH pipe(%d bytes)\n", + pIpPacketsSizes[i]); + size_t nBytesSent = m_HsicToIpaPipe.Send(pPackets[i], pIpPacketsSizes[i]); + if (pIpPacketsSizes[i] != nBytesSent) + { + LOG_MSG_ERROR("Sending packet into the USB pipe(%d bytes) " + "failed!\n", pIpPacketsSizes[i]); + return false; + } + ExpectedPacketSize += pIpPacketsSizes[i]; + } + + /* suspend the pipe */ + ep_ctrl.from_dev_num = 0; + ep_ctrl.ipa_ep_delay = false; + ep_ctrl.ipa_ep_suspend = true; + configure_ep_ctrl(&ep_ctrl); + + /* receive the packet */ + LOG_MSG_DEBUG( + "Reading packet from the USB pipe(%d bytes should be there)" + "\n", ExpectedPacketSize); + size_t nBytesReceived = m_IpaToUsbPipeAgg + .Receive(pReceivedPacket, MAX_PACKET_SIZE); + if (ExpectedPacketSize != nBytesReceived) + { + LOG_MSG_ERROR( + "Receiving aggregated packet from the USB pipe(%d bytes) " + "failed!\n", nBytesReceived); + print_buff(pReceivedPacket, nBytesReceived); + return false; + } + + + for(int i = 0; i < (NUM_PACKETS - 1); i++) { + if (!RNDISAggregationHelper:: + CompareIPvsRNDISPacket(pPackets[i], pIpPacketsSizes[i], + pReceivedPacket + (i * ExpectedPacketSize / (NUM_PACKETS - 1)), + ExpectedPacketSize / (NUM_PACKETS - 1))) + return false; + } + + return true; + } + + bool Teardown() + { + bool bRetVal = true; + + bRetVal = RNDISAggregationTestFixture::Teardown(); + if (bRetVal == false) { + return bRetVal; + } + + /* unregister the test framework suspend handler */ + bRetVal = RegSuspendHandler(false, false, 0); + + return bRetVal; + } +}; + +class RNDISAggregationByteLimitTest: public RNDISAggregationTestFixture { +public: + + ///////////////////////////////////////////////////////////////////////////////// + + RNDISAggregationByteLimitTest() + { + m_name = "RNDISAggregationByteLimitTest"; + m_description = "RNDISAggregationByteLimitTest - Send 2 IP packet " + "and expect aggregated RNDIS packet."; + } + + ///////////////////////////////////////////////////////////////////////////////// + + virtual bool AddRules() + { + return AddRulesAggByteLimit(); + } // AddRules() + + ///////////////////////////////////////////////////////////////////////////////// + + bool TestLogic() + { + /*The packets that will be sent*/ + + Byte pPackets[NUM_PACKETS][MAX_PACKET_SIZE]; + /*Buffer for the packet that will be received*/ + Byte pReceivedPacket[2*MAX_PACKET_SIZE]; + /*Total size of all sent packets + * (this is the max size of the aggregated + *packet minus the size of the header and the NDP) + */ + uint32_t nIPv4DSTAddr; + size_t pIpPacketsSizes[NUM_PACKETS]; + size_t ExpectedPacketSize = NUM_PACKETS * sizeof(struct RndisEtherHeader); + + for(int i = 0; i < NUM_PACKETS; i++) { + /* + *initialize the packets + *Load input data (IP packet) from file + */ + pIpPacketsSizes[i] = MAX_PACKET_SIZE; + if (!LoadDefaultPacket(m_eIP, pPackets[i], pIpPacketsSizes[i])) + { + LOG_MSG_ERROR("Failed to load Ethernet Packet"); + return false; + } + nIPv4DSTAddr = ntohl(0x7F000001); + memcpy (&pPackets[i][IPV4_DST_ADDR_OFFSET],&nIPv4DSTAddr, + sizeof(nIPv4DSTAddr)); + for(int j = pIpPacketsSizes[i]; j < MAX_PACKET_SIZE / NUM_PACKETS + 1; j++) { + pPackets[i][j] = j & 0xFF; + } + pIpPacketsSizes[i] = MAX_PACKET_SIZE / NUM_PACKETS + 1; + + /* send the packet */ + LOG_MSG_DEBUG("Sending packet into the A2 TETH pipe(%d bytes)\n", + pIpPacketsSizes[i]); + size_t nBytesSent = m_HsicToIpaPipe.Send(pPackets[i], pIpPacketsSizes[i]); + if (pIpPacketsSizes[i] != nBytesSent) + { + LOG_MSG_ERROR("Sending packet into the USB pipe(%d bytes) " + "failed!\n", pIpPacketsSizes[i]); + return false; + } + ExpectedPacketSize += pIpPacketsSizes[i]; + } + + /* receive the packet */ + LOG_MSG_DEBUG( + "Reading packet from the USB pipe(%d bytes should be there)" + "\n", ExpectedPacketSize); + size_t nBytesReceived = m_IpaToUsbPipeAgg + .Receive(pReceivedPacket, MAX_PACKET_SIZE); + if (ExpectedPacketSize != nBytesReceived) + { + LOG_MSG_ERROR( + "Receiving aggregated packet from the USB pipe(%d bytes) " + "failed!\n", nBytesReceived); + print_buff(pReceivedPacket, nBytesReceived); + return false; + } + + + for(int i = 0; i < NUM_PACKETS; i++) { + if (!RNDISAggregationHelper:: + CompareIPvsRNDISPacket(pPackets[i], pIpPacketsSizes[i], + pReceivedPacket + (i * ExpectedPacketSize / NUM_PACKETS), + ExpectedPacketSize / NUM_PACKETS)) + return false; + } + + return true; + } +}; + +class RNDISAggregationByteLimitTestFC : public RNDISAggregationTestFixture { +public: + + ///////////////////////////////////////////////////////////////////////////////// + + RNDISAggregationByteLimitTestFC() { + m_name = "RNDISAggregationByteLimitTestFC"; + m_description = "RNDISAggregationByteLimitTestFC - Send 4 IP packet with FC" + "and expect 4 aggregated RNDIS packets."; + } + + ///////////////////////////////////////////////////////////////////////////////// + + virtual bool AddRules() { + return AddRulesAggByteLimit(true); + } // AddRules() + + ///////////////////////////////////////////////////////////////////////////////// + + bool TestLogic() { + /*The packets that will be sent*/ + + Byte pPackets[NUM_PACKETS][MAX_PACKET_SIZE]; + /*Buffer for the packets that will be received*/ + Byte pReceivedPacket[NUM_PACKETS][MAX_PACKET_SIZE]; + /*Total size of all sent packets + * (this is the max size of the aggregated + *packet minus the size of the header and the NDP) + */ + uint32_t nIPv4DSTAddr; + size_t pIpPacketsSizes[NUM_PACKETS]; + size_t ExpectedPacketSize = + sizeof(struct RndisEtherHeader) + MAX_PACKET_SIZE / NUM_PACKETS + 1; + + for (int i = 0; i < NUM_PACKETS; i++) { + /* + *initialize the packets + *Load input data (IP packet) from file + */ + pIpPacketsSizes[i] = MAX_PACKET_SIZE; + if (!LoadDefaultPacket(m_eIP, pPackets[i], pIpPacketsSizes[i])) { + LOG_MSG_ERROR("Failed to load Ethernet Packet"); + return false; + } + nIPv4DSTAddr = ntohl(0x7F000001); + memcpy(&pPackets[i][IPV4_DST_ADDR_OFFSET], &nIPv4DSTAddr, + sizeof(nIPv4DSTAddr)); + for (int j = pIpPacketsSizes[i]; j < MAX_PACKET_SIZE / NUM_PACKETS + 1; j++) { + pPackets[i][j] = j & 0xFF; + } + pIpPacketsSizes[i] = MAX_PACKET_SIZE / NUM_PACKETS + 1; + + /* send the packet */ + LOG_MSG_DEBUG("Sending packet into the A2 TETH pipe(%d bytes)\n", + pIpPacketsSizes[i]); + size_t nBytesSent = m_HsicToIpaPipe.Send(pPackets[i], pIpPacketsSizes[i]); + if (pIpPacketsSizes[i] != nBytesSent) { + LOG_MSG_ERROR("Sending packet into the USB pipe(%d bytes) " + "failed!\n", pIpPacketsSizes[i]); + return false; + } + } + + /* receive the packet */ + LOG_MSG_DEBUG( + "Reading packets from the USB pipe(%d bytes for each)" + "\n", ExpectedPacketSize); + for (int i = 0; i < NUM_PACKETS; i++) { + size_t nBytesReceived = m_IpaToUsbPipeAgg + .Receive(pReceivedPacket[i], MAX_PACKET_SIZE); + if (ExpectedPacketSize != nBytesReceived) { + LOG_MSG_ERROR( + "Receiving aggregated packet from the USB pipe(%d bytes) " + "failed!\n", nBytesReceived); + print_buff(pReceivedPacket[i], nBytesReceived); + return false; + } + print_buff(pReceivedPacket, nBytesReceived); + } + + + for (int i = 0; i < NUM_PACKETS; i++) { + if (!RNDISAggregationHelper::CompareIPvsRNDISPacket( + pPackets[i], + pIpPacketsSizes[i], + pReceivedPacket[i], + ExpectedPacketSize)) return false; + } + + return true; + } +}; + +class RNDISAggregationDualDpTestFC : public RNDISAggregationTestFixture { +public: + + ///////////////////////////////////////////////////////////////////////////////// + + RNDISAggregationDualDpTestFC() { + m_name = "RNDISAggregationDualDpTestFC"; + m_description = "RNDISAggregationDualDpTestFC - Send IP packets " + "on two datapathes: one with FC and one without. " + "Expect 2 aggregated RNDIS packets on pipe with FC. " + "Expect one aggregated RNDIS packet on pipe without FC. "; + } + + ///////////////////////////////////////////////////////////////////////////////// + + virtual bool AddRules() { + return AddRulesAggDualFC(); + } + + ///////////////////////////////////////////////////////////////////////////////// + + bool TestLogic() { + int i; + /* The packets that will be sent */ + Byte pPackets[NUM_PACKETS][MAX_PACKET_SIZE]; + /* Buffer for the packets that will be received */ + Byte pReceivedPacket[(NUM_PACKETS / 2) * MAX_PACKET_SIZE]; + Byte pReceivedPacketFC[NUM_PACKETS / 2][MAX_PACKET_SIZE]; + /* + * Total size of all sent packets + * (this is the max size of the aggregated + * packet minus the size of the header and the NDP) + */ + uint32_t nIPv4DSTAddr; + size_t nBytesReceived; + size_t pIpPacketsSizes[NUM_PACKETS]; + size_t ExpectedPacketSize = + sizeof(struct RndisEtherHeader) + MAX_PACKET_SIZE / NUM_PACKETS + 1; + + for (i = 0; i < NUM_PACKETS; i++) { + /* + * Initialize the packets + * Load input data (IP packet) from file + */ + pIpPacketsSizes[i] = MAX_PACKET_SIZE; + if (!LoadDefaultPacket(m_eIP, pPackets[i], pIpPacketsSizes[i])) { + LOG_MSG_ERROR("Failed to load Ethernet Packet"); + return false; + } + /* + * Half of the packets will go to 127.0.0.1 + * and the other half to 127.0.0.2 + */ + nIPv4DSTAddr = ntohl(0x7F000001 + (i & 0x1)); + memcpy(&pPackets[i][IPV4_DST_ADDR_OFFSET], &nIPv4DSTAddr, + sizeof(nIPv4DSTAddr)); + for (int j = pIpPacketsSizes[i]; j < MAX_PACKET_SIZE / NUM_PACKETS + 1; j++) { + pPackets[i][j] = j & 0xFF; + } + pIpPacketsSizes[i] = MAX_PACKET_SIZE / NUM_PACKETS + 1; + + /* send the packet */ + LOG_MSG_DEBUG("Sending packet into the m_HsicToIpaPipe pipe (%d bytes)\n", + pIpPacketsSizes[i]); + print_buff(pPackets[i], pIpPacketsSizes[i]); + size_t nBytesSent = m_HsicToIpaPipe.Send(pPackets[i], pIpPacketsSizes[i]); + if (pIpPacketsSizes[i] != nBytesSent) { + LOG_MSG_ERROR("Sending packet into the m_HsicToIpaPipe pipe (%d bytes) " + "failed!\n", pIpPacketsSizes[i]); + return false; + } + } + + /* receive the packets from FC pipe */ + LOG_MSG_DEBUG( + "Reading packets from the m_IpaToUsbPipeAgg pipe (%d bytes for each)" + "\n", ExpectedPacketSize); + for (i = 0; i < NUM_PACKETS / 2; i++) { + nBytesReceived = m_IpaToUsbPipeAgg + .Receive(pReceivedPacketFC[i], MAX_PACKET_SIZE); + if (ExpectedPacketSize != nBytesReceived) { + LOG_MSG_ERROR( + "Receiving aggregated packet from the m_IpaToUsbPipeAgg pipe (%d bytes) " + "failed!\n", nBytesReceived); + print_buff(pReceivedPacketFC[i], nBytesReceived); + return false; + } + } + + for (i = 0; i < NUM_PACKETS / 2; i++) { + if (!RNDISAggregationHelper::CompareIPvsRNDISPacket( + pPackets[i * 2], + pIpPacketsSizes[i * 2], + pReceivedPacketFC[i], + ExpectedPacketSize)) return false; + } + + /* receive the packet from non-FC pipe */ + LOG_MSG_DEBUG( + "Reading packet from the m_IpaToUsbPipeAggPktLimit pipe (%d bytes)" + "\n", ExpectedPacketSize * 2); + nBytesReceived = m_IpaToUsbPipeAggPktLimit + .Receive(pReceivedPacket, MAX_PACKET_SIZE); + if (ExpectedPacketSize * 2 != nBytesReceived) { + LOG_MSG_ERROR( + "Receiving aggregated packets from the m_IpaToUsbPipeAggPktLimit pipe (%d bytes) " + "failed!\n", nBytesReceived); + print_buff(pReceivedPacket, nBytesReceived); + return false; + } + + for (int i = 0; i < NUM_PACKETS; i += 2) { + if (!RNDISAggregationHelper::CompareIPvsRNDISPacket( + pPackets[i + 1], // Odd packets are in the second pipe + pIpPacketsSizes[i + 1], + pReceivedPacket + (i * ExpectedPacketSize / 2), + ExpectedPacketSize)) + return false; + } + + return true; + } +}; + +class RNDISAggregationDualDpTestFcRoutingBased : public RNDISAggregationTestFixture { +public: + + ///////////////////////////////////////////////////////////////////////////////// + + RNDISAggregationDualDpTestFcRoutingBased() { + m_name = "RNDISAggregationDualDpTestFcRoutingBased"; + m_description = "RNDISAggregationDualDpTestFcRoutingBased - Send IP packets " + "on two datapathes: one with RT based FC and one without. " + "Expect 2 aggregated RNDIS packets on pipe with RT based FC. " + "Expect one aggregated RNDIS packet on pipe without RT based FC. "; + } + + ///////////////////////////////////////////////////////////////////////////////// + + virtual bool AddRules() { + return AddRulesAggDualFcRoutingBased(); + } + + ///////////////////////////////////////////////////////////////////////////////// + + bool TestLogic() { + int i; + /* The packets that will be sent */ + Byte pPackets[NUM_PACKETS][MAX_PACKET_SIZE]; + /* Buffer for the packets that will be received */ + Byte pReceivedPacket[(NUM_PACKETS / 2) * MAX_PACKET_SIZE]; + Byte pReceivedPacketFC[NUM_PACKETS / 2][MAX_PACKET_SIZE]; + /* + * Total size of all sent packets + * (this is the max size of the aggregated + * packet minus the size of the header and the NDP) + */ + uint32_t nIPv4DSTAddr; + size_t nBytesReceived; + size_t pIpPacketsSizes[NUM_PACKETS]; + size_t ExpectedPacketSize = + sizeof(struct RndisEtherHeader) + MAX_PACKET_SIZE / NUM_PACKETS + 1; + + for (i = 0; i < NUM_PACKETS; i++) { + /* + * Initialize the packets + * Load input data (IP packet) from file + */ + pIpPacketsSizes[i] = MAX_PACKET_SIZE; + if (!LoadDefaultPacket(m_eIP, pPackets[i], pIpPacketsSizes[i])) { + LOG_MSG_ERROR("Failed to load Ethernet Packet"); + return false; + } + /* + * Half of the packets will go to 127.0.0.1 + * and the other half to 127.0.0.2 + */ + nIPv4DSTAddr = ntohl(0x7F000001 + (i & 0x1)); + memcpy(&pPackets[i][IPV4_DST_ADDR_OFFSET], &nIPv4DSTAddr, + sizeof(nIPv4DSTAddr)); + for (int j = pIpPacketsSizes[i]; j < MAX_PACKET_SIZE / NUM_PACKETS + 1; j++) { + pPackets[i][j] = j & 0xFF; + } + pIpPacketsSizes[i] = MAX_PACKET_SIZE / NUM_PACKETS + 1; + + /* send the packet */ + LOG_MSG_DEBUG("Sending packet into the m_HsicToIpaPipe pipe (%d bytes)\n", + pIpPacketsSizes[i]); + print_buff(pPackets[i], pIpPacketsSizes[i]); + size_t nBytesSent = m_HsicToIpaPipe.Send(pPackets[i], pIpPacketsSizes[i]); + if (pIpPacketsSizes[i] != nBytesSent) { + LOG_MSG_ERROR("Sending packet into the m_HsicToIpaPipe pipe (%d bytes) " + "failed!\n", pIpPacketsSizes[i]); + return false; + } + } + + /* receive the packets from FC pipe */ + LOG_MSG_DEBUG( + "Reading packets from the m_IpaToUsbPipeAgg pipe (%d bytes for each)" + "\n", ExpectedPacketSize); + for (i = 0; i < NUM_PACKETS / 2; i++) { + nBytesReceived = m_IpaToUsbPipeAgg + .Receive(pReceivedPacketFC[i], MAX_PACKET_SIZE); + if (ExpectedPacketSize != nBytesReceived) { + LOG_MSG_ERROR( + "Receiving aggregated packet from the m_IpaToUsbPipeAgg pipe (%d bytes) " + "failed!\n", nBytesReceived); + print_buff(pReceivedPacketFC[i], nBytesReceived); + return false; + } + } + + for (i = 0; i < NUM_PACKETS / 2; i++) { + if (!RNDISAggregationHelper::CompareIPvsRNDISPacket( + pPackets[i * 2], + pIpPacketsSizes[i * 2], + pReceivedPacketFC[i], + ExpectedPacketSize)) return false; + } + + /* receive the packet from non-FC pipe */ + LOG_MSG_DEBUG( + "Reading packet from the m_IpaToUsbPipeAggPktLimit pipe (%d bytes)" + "\n", ExpectedPacketSize * 2); + nBytesReceived = m_IpaToUsbPipeAggPktLimit + .Receive(pReceivedPacket, MAX_PACKET_SIZE); + if (ExpectedPacketSize * 2 != nBytesReceived) { + LOG_MSG_ERROR( + "Receiving aggregated packets from the m_IpaToUsbPipeAggPktLimit pipe (%d bytes) " + "failed!\n", nBytesReceived); + print_buff(pReceivedPacket, nBytesReceived); + return false; + } + + for (int i = 0; i < NUM_PACKETS; i += 2) { + if (!RNDISAggregationHelper::CompareIPvsRNDISPacket( + pPackets[i + 1], // Odd packets are in the second pipe + pIpPacketsSizes[i + 1], + pReceivedPacket + (i * ExpectedPacketSize / 2), + ExpectedPacketSize)) + return false; + } + + return true; + } +}; + +class RNDISAggregationDeaggregationNumPacketsTest: + public RNDISAggregationTestFixture { +public: + + RNDISAggregationDeaggregationNumPacketsTest() + { + m_name = "RNDISAggregationDeaggregationNumPacketsTest"; + m_description = "RNDISAggregationByteLimitTest - Send on IP packet " + "and expect aggregated RNDIS packet."; + } + + virtual bool AddRules() + { + return AddRulesDeAggEther(); + } /* AddRules()*/ + + bool TestLogic() + { + /*the packets that will be sent*/ + Byte pPacket[MAX_PACKET_SIZE]; + //Buffer for the packet that will be received + Byte pReceivedPacket[2*MAX_PACKET_SIZE]; + //Total size of all sent packets (this is the max size of the aggregated + //packet minus the size of the header and the NDP) + uint32_t nIPv4DSTAddr; + size_t pIpPacketsSize; + size_t pAggrPacketsSize = 0; + + for(int i = 0; i < NUM_PACKETS; i++) { + //initialize the packets + // Load input data (RNDIS packet) from file + pIpPacketsSize = MAX_PACKET_SIZE; + if (!RNDISAggregationHelper::LoadRNDISPacket(m_eIP, pPacket + pAggrPacketsSize, pIpPacketsSize)) + { + LOG_MSG_ERROR("Failed to load Ethernet Packet"); + return false; + } + pAggrPacketsSize += pIpPacketsSize; + nIPv4DSTAddr = ntohl(0x7F000001); + memcpy (&((pPacket + i * pIpPacketsSize)[IPV4_DST_ADDR_OFFSET_IN_RNDIS]),&nIPv4DSTAddr, + sizeof(nIPv4DSTAddr)); + } + print_buff(pPacket, pAggrPacketsSize); + + /*send the packet*/ + LOG_MSG_DEBUG("Sending packet into the A2 TETH pipe(%d bytes)\n", + pIpPacketsSize * NUM_PACKETS); + size_t nBytesSent = m_UsbToIpaPipeDeagg.Send(pPacket, pAggrPacketsSize); + if (pAggrPacketsSize != nBytesSent) + { + LOG_MSG_ERROR("Sending packet into the USB pipe(%d bytes) " + "failed!\n", pIpPacketsSize * NUM_PACKETS); + return false; + } + for(int i = 0; i < NUM_PACKETS; i++) { + //receive the packet, one by one + LOG_MSG_DEBUG("Reading packet from the USB pipe(%d bytes should be there)" + "\n", pIpPacketsSize - sizeof(struct RndisHeader)); + size_t nBytesReceived = m_IpaToUsbPipe.Receive(pReceivedPacket, MAX_PACKET_SIZE); + if (pIpPacketsSize - sizeof(struct RndisHeader) != nBytesReceived) + { + LOG_MSG_ERROR("Receiving aggregated packet from the USB pipe(%d bytes) " + "failed!\n", nBytesReceived); + print_buff(pReceivedPacket, nBytesReceived); + return false; + } + if (!RNDISAggregationHelper::CompareEthervsRNDISPacket(pReceivedPacket, + nBytesReceived, + pPacket + i * pIpPacketsSize, + pIpPacketsSize)) + return false; + } + + return true; + } + + ///////////////////////////////////////////////////////////////////////////////// +}; + +class RNDISAggregationDeaggregationExceptionPacketsTest: + public RNDISAggregationTestFixture { +public: + + RNDISAggregationDeaggregationExceptionPacketsTest() + { + m_name = "RNDISAggregationDeaggregationExceptionPacketsTest"; + m_description = "RNDISAggregationDeaggregationExceptionPacketsTest - Send 5 frames " + "of size 43 bytes, 1025 bytes, 43 bytes, 981 bytes, and 1024 bytes " + "and expect aggregated RNDIS packet."; + } + + virtual bool AddRules() + { + return AddRulesDeAggEther(); + } /* AddRules()*/ + + bool TestLogic() + { + /*the packets that will be sent*/ + Byte pPacket[MAX_PACKET_SIZE]; + Byte pPacket1[MAX_PACKET_SIZE +1]; + Byte pPacket2[MAX_PACKET_SIZE]; + Byte pPacket3[MAX_PACKET_SIZE]; + + //Buffer for the packet that will be received + Byte pReceivedPacket[2*MAX_PACKET_SIZE]; + //Total size of all sent packets (this is the max size of the aggregated + //packet minus the size of the header and the NDP) + uint32_t nIPv4DSTAddr; + size_t pIpPacketsSize; + size_t pAggrPacketsSize = 0; + size_t nBytesSent; + size_t nBytesReceived; + + /* Create the frame of size 43 bytes which is one less byte than RNDIS header */ + pAggrPacketsSize = sizeof(struct RndisHeader) - 1; + struct RndisHeader *pRndisHeader = (struct RndisHeader*)pPacket; + memset(pRndisHeader, 0, (sizeof(struct RndisHeader) - 1)); + pRndisHeader->MessageType = 0x01; + pRndisHeader->MessageLength = pAggrPacketsSize; + pRndisHeader->DataOffset = 0x24; + pRndisHeader->DataLength = 0; + + nIPv4DSTAddr = ntohl(0x7F000001); + memcpy (&((pPacket)[IPV4_DST_ADDR_OFFSET_IN_RNDIS]),&nIPv4DSTAddr, + sizeof(nIPv4DSTAddr)); + print_buff(pPacket, pAggrPacketsSize); + + /* Send the first frame */ + LOG_MSG_DEBUG("Sending packet into the A2 TETH pipe(%d bytes)\n", + pAggrPacketsSize); + nBytesSent = m_UsbToIpaPipeDeagg.Send(pPacket, pAggrPacketsSize); + if (pAggrPacketsSize != nBytesSent) + { + LOG_MSG_ERROR("Sending packet into the USB pipe(%d bytes) " + "failed!\n", pAggrPacketsSize); + return false; + } + /* This is deaggregation exception packet, this packet should not arrive at this pipe */ + LOG_MSG_DEBUG("Reading packet from the USB pipe(0 bytes should be there)\n"); + nBytesReceived = m_IpaToUsbPipe.Receive(pReceivedPacket, MAX_PACKET_SIZE); + if (0 != nBytesReceived) + { + LOG_MSG_ERROR("Receiving aggregated packet from the USB pipe(%d bytes) " + "failed!\n", nBytesReceived); + print_buff(pReceivedPacket, nBytesReceived); + return false; + } + + /* Create a frame of size 1025 bytes */ + pAggrPacketsSize = 0; + for(int i = 0; i < 8; i++) { + //initialize the packets + // Load input data (RNDIS packet) from file + pIpPacketsSize = MAX_PACKET_SIZE; + if (!RNDISAggregationHelper::LoadRNDISPacket(m_eIP, pPacket1 + pAggrPacketsSize, pIpPacketsSize)) + { + LOG_MSG_ERROR("Failed to load Ethernet Packet"); + return false; + } + pAggrPacketsSize += pIpPacketsSize; + nIPv4DSTAddr = ntohl(0x7F000001); + memcpy (&((pPacket1 + i * pIpPacketsSize)[IPV4_DST_ADDR_OFFSET_IN_RNDIS]),&nIPv4DSTAddr, + sizeof(nIPv4DSTAddr)); + } + + pPacket1[pAggrPacketsSize] = 0xdd; + pAggrPacketsSize = pAggrPacketsSize + 1; + + print_buff(pPacket1, pAggrPacketsSize); + + /* Send the 2nd frame */ + LOG_MSG_DEBUG("Sending packet into the A2 TETH pipe(%d bytes)\n", + pAggrPacketsSize); + nBytesSent = m_UsbToIpaPipeDeagg.Send(pPacket1, pAggrPacketsSize); + if (pAggrPacketsSize != nBytesSent) + { + LOG_MSG_ERROR("Sending packet into the USB pipe(%d bytes) " + "failed!\n", pAggrPacketsSize); + return false; + } + + for(int i = 0; i < 8; i++) { + //Receive the packet, one by one + LOG_MSG_DEBUG("Reading packet from the USB pipe(%d bytes should be there)" + "\n", pIpPacketsSize - sizeof(struct RndisHeader)); + size_t nBytesReceived = m_IpaToUsbPipe.Receive(pReceivedPacket, MAX_PACKET_SIZE); + if (pIpPacketsSize - sizeof(struct RndisHeader) != nBytesReceived) + { + LOG_MSG_ERROR("Receiving aggregated packet from the USB pipe(%d bytes) " + "failed!\n", nBytesReceived); + print_buff(pReceivedPacket, nBytesReceived); + return false; + } + if (!RNDISAggregationHelper::CompareEthervsRNDISPacket(pReceivedPacket, + nBytesReceived, + pPacket1 + i * pIpPacketsSize, + pIpPacketsSize)) + return false; + } + + /* Create a frame of size 1024 bytes and send as 2 frames */ + pAggrPacketsSize = 0; + for(int i = 0; i < 8; i++) { + //initialize the packets + // Load input data (RNDIS packet) from file + pIpPacketsSize = MAX_PACKET_SIZE; + if (!RNDISAggregationHelper::LoadRNDISPacket(m_eIP, pPacket2 + pAggrPacketsSize, pIpPacketsSize)) + { + LOG_MSG_ERROR("Failed to load Ethernet Packet"); + return false; + } + pAggrPacketsSize += pIpPacketsSize; + nIPv4DSTAddr = ntohl(0x7F000001); + memcpy (&((pPacket2 + i * pIpPacketsSize)[IPV4_DST_ADDR_OFFSET_IN_RNDIS]),&nIPv4DSTAddr, + sizeof(nIPv4DSTAddr)); + } + print_buff(pPacket2, pAggrPacketsSize); + + /* Send the 3rd frame */ + LOG_MSG_DEBUG("Sending packet into the A2 TETH pipe(%d bytes)\n", 43); + nBytesSent = m_UsbToIpaPipeDeagg.Send(pPacket2, 43); + if (43 != nBytesSent) + { + LOG_MSG_ERROR("Sending packet into the USB pipe(%d bytes) " + "failed!\n", 43); + + return false; + } + /* This is deaggregation exception packet, this packet should not arrive at this pipe */ + LOG_MSG_DEBUG("Reading packet from the USB pipe(0 bytes should be there)\n"); + nBytesReceived = m_IpaToUsbPipe.Receive(pReceivedPacket, MAX_PACKET_SIZE); + if (0 != nBytesReceived) + { + LOG_MSG_ERROR("Receiving aggregated packet from the USB pipe(%d bytes) " + "failed!\n", nBytesReceived); + print_buff(pReceivedPacket, nBytesReceived); + return false; + } + /* Send the 4rd frame */ + LOG_MSG_DEBUG("Sending packet into the A2 TETH pipe(%d bytes)\n", + pAggrPacketsSize - 43 ); + nBytesSent = m_UsbToIpaPipeDeagg.Send((pPacket2 + 43), pAggrPacketsSize - 43); + if ((pAggrPacketsSize - 43) != nBytesSent) + { + LOG_MSG_ERROR("Sending packet into the USB pipe(%d bytes) " + "failed!\n", pAggrPacketsSize - 43); + return false; + } + /* This is deaggregation exception packet, this packet should not arrive at this pipe */ + LOG_MSG_DEBUG("Reading packet from the USB pipe(0 bytes should be there)\n"); + nBytesReceived = m_IpaToUsbPipe.Receive(pReceivedPacket, MAX_PACKET_SIZE); + if (0 != nBytesReceived) + { + LOG_MSG_ERROR("Receiving aggregated packet from the USB pipe(%d bytes) " + "failed!\n", nBytesReceived); + print_buff(pReceivedPacket, nBytesReceived); + return false; + } + + /* Create a frame of size 1024 bytes */ + pAggrPacketsSize = 0; + for(int i = 0; i < 8; i++) { + //initialize the packets + //Load input data (RNDIS packet) from file + pIpPacketsSize = MAX_PACKET_SIZE; + if (!RNDISAggregationHelper::LoadRNDISPacket(m_eIP, pPacket3 + pAggrPacketsSize, pIpPacketsSize)) + { + LOG_MSG_ERROR("Failed to load Ethernet Packet"); + return false; + } + pAggrPacketsSize += pIpPacketsSize; + nIPv4DSTAddr = ntohl(0x7F000001); + memcpy (&((pPacket3 + i * pIpPacketsSize)[IPV4_DST_ADDR_OFFSET_IN_RNDIS]),&nIPv4DSTAddr, + sizeof(nIPv4DSTAddr)); + } + print_buff(pPacket3, pAggrPacketsSize); + + /* Send the 5th frame */ + LOG_MSG_ERROR("blend-3 Sending packet into the A2 TETH pipe(%d bytes)\n", + pAggrPacketsSize); + nBytesSent = m_UsbToIpaPipeDeagg.Send(pPacket3, pAggrPacketsSize); + if (pAggrPacketsSize != nBytesSent) + { + LOG_MSG_ERROR("Sending packet into the USB pipe(%d bytes) " + "failed!\n", pAggrPacketsSize); + return false; + } + + for(int i = 0; i < 8; i++) { + //Receive the packet, one by one + LOG_MSG_DEBUG("Reading packet from the USB pipe(%d bytes should be there)" + "\n", pIpPacketsSize - sizeof(struct RndisHeader)); + size_t nBytesReceived = m_IpaToUsbPipe.Receive(pReceivedPacket, MAX_PACKET_SIZE); + if (pIpPacketsSize - sizeof(struct RndisHeader) != nBytesReceived) + { + LOG_MSG_ERROR("Receiving aggregated packet from the USB pipe(%d bytes) " + "failed!\n", nBytesReceived); + print_buff(pReceivedPacket, nBytesReceived); + return false; + } + if (!RNDISAggregationHelper::CompareEthervsRNDISPacket(pReceivedPacket, + nBytesReceived, + pPacket3 + i * pIpPacketsSize, + pIpPacketsSize)) + return false; + } + + return true; + } + +}; + +class RNDISAggregationPacketLimitTest: public RNDISAggregationTestFixture { +public: + + ///////////////////////////////////////////////////////////////////////////////// + + RNDISAggregationPacketLimitTest() + { + m_name = "RNDISAggregationPacketLimitTest"; + m_description = "RNDISAggregationPacketLimitTest - Send 2 IP packet " + "and expect aggregated RNDIS packet."; + } + + ///////////////////////////////////////////////////////////////////////////////// + + virtual bool AddRules() + { + return AddRulesAggPacketLimit(); + } // AddRules() + + ///////////////////////////////////////////////////////////////////////////////// + + bool TestLogic() + { + //The packets that will be sent + + Byte pPackets[2][MAX_PACKET_SIZE]; + //Buffer for the packet that will be received + Byte pReceivedPacket[2*MAX_PACKET_SIZE]; + //Total size of all sent packets (this is the max size of the aggregated + //packet minus the size of the header and the NDP) + uint32_t nIPv4DSTAddr; + size_t pIpPacketsSizes[2]; + size_t ExpectedPacketSize = 2 * sizeof(struct RndisEtherHeader); + + for(int i = 0; i < 2; i++) { + //initialize the packets + // Load input data (IP packet) from file + pIpPacketsSizes[i] = MAX_PACKET_SIZE; + if (!LoadDefaultPacket(m_eIP, pPackets[i], pIpPacketsSizes[i])) + { + LOG_MSG_ERROR("Failed to load Ethernet Packet"); + return false; + } + nIPv4DSTAddr = ntohl(0x7F000001); + memcpy (&pPackets[i][IPV4_DST_ADDR_OFFSET],&nIPv4DSTAddr, + sizeof(nIPv4DSTAddr)); + + //send the packet + LOG_MSG_DEBUG("Sending packet into the A2 TETH pipe(%d bytes)\n", + pIpPacketsSizes[i]); + size_t nBytesSent = m_HsicToIpaPipe.Send(pPackets[i], pIpPacketsSizes[i]); + if (pIpPacketsSizes[i] != nBytesSent) + { + LOG_MSG_ERROR("Sending packet into the USB pipe(%d bytes) " + "failed!\n", pIpPacketsSizes[i]); + return false; + } + ExpectedPacketSize += pIpPacketsSizes[i]; + } + + //receive the packet + LOG_MSG_DEBUG("Reading packet from the USB pipe(%d bytes should be there)" + "\n", ExpectedPacketSize); + size_t nBytesReceived = m_IpaToUsbPipeAggPktLimit.Receive(pReceivedPacket, MAX_PACKET_SIZE); + if (ExpectedPacketSize != nBytesReceived) + { + LOG_MSG_ERROR("Receiving aggregated packet from the USB pipe(%d bytes) " + "failed!\n", nBytesReceived); + print_buff(pReceivedPacket, nBytesReceived); + return false; + } + + + for(int i = 0; i < 2; i++) { + if (!RNDISAggregationHelper::CompareIPvsRNDISPacket(pPackets[i], pIpPacketsSizes[i], + pReceivedPacket + (i * ExpectedPacketSize / 2), ExpectedPacketSize / 2)) + return false; + } + + return true; + } + + ///////////////////////////////////////////////////////////////////////////////// +}; + + + +static RNDISAggregationSanityTest aRNDISAggregationSanityTest; +static RNDISAggregationDeaggregation1PacketTest aRNDISAggregationDeaggregation1PacketTest; +static RNDISAggregation1PacketTest aRNDISAggregation1PacketTest; +static RNDISAggregationSuspendWaTest aRNDISAggregationSuspendWaTest; +static RNDISAggregationByteLimitTest aRNDISAggregationByteLimitTest; +static RNDISAggregationByteLimitTestFC aRNDISAggregationByteLimitTestFC; +static RNDISAggregationDualDpTestFC aRNDISAggregationDualDpTestFC; +static RNDISAggregationDualDpTestFcRoutingBased aRNDISAggregationDualDpTestFcRoutingBased; +static RNDISAggregationDeaggregationNumPacketsTest aRNDISAggregationDeaggregationNumPacketsTest; +static RNDISAggregationDeaggregationExceptionPacketsTest aRNDISAggregationDeaggregationExceptionPacketsTest; +static RNDISAggregationPacketLimitTest aRNDISAggregationPacketLimitTest; + +///////////////////////////////////////////////////////////////////////////////// +// EOF //// +///////////////////////////////////////////////////////////////////////////////// diff --git a/qcom/opensource/dataipa/kernel-tests/RoutingDriverWrapper.cpp b/qcom/opensource/dataipa/kernel-tests/RoutingDriverWrapper.cpp new file mode 100644 index 0000000000..30fcdf25d8 --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/RoutingDriverWrapper.cpp @@ -0,0 +1,213 @@ +/* + * Copyright (c) 2017,2020 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Changes from Qualcomm Innovation Center are provided under the following license: + * + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * * Neither the name of Qualcomm Innovation Center, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + */ + +#include +#include +#include +#include + +#include "RoutingDriverWrapper.h" +#include "TestsUtils.h" + +bool RoutingDriverWrapper::AddRoutingRule(struct ipa_ioc_add_rt_rule *ruleTable) +{ + int retval = 0; + + if (!DeviceNodeIsOpened()) + return false; + + retval = ioctl(m_fd, IPA_IOC_ADD_RT_RULE, ruleTable); + if (retval) { + printf("%s(), failed adding routing rule table %p\n", __FUNCTION__, ruleTable); + return false; + } + + printf("%s(), Added routing rule table %p\n", __FUNCTION__, ruleTable); + return true; +} + +bool RoutingDriverWrapper::AddRoutingRule(struct ipa_ioc_add_rt_rule_v2 *ruleTable_v2) +{ + int retval = 0; + + if (!DeviceNodeIsOpened()) + return false; + + retval = ioctl(m_fd, IPA_IOC_ADD_RT_RULE_V2, ruleTable_v2); + if (retval) { + printf("%s(), failed adding routing rule table %p\n", __FUNCTION__, ruleTable_v2); + return false; + } + + printf("%s(), Added routing rule table %p\n", __FUNCTION__, ruleTable_v2); + return true; +} + +bool RoutingDriverWrapper::DeleteRoutingRule(struct ipa_ioc_del_rt_rule *ruleTable) +{ + int retval = 0; + + if (!DeviceNodeIsOpened()) + return false; + + retval = ioctl(m_fd, IPA_IOC_DEL_RT_RULE, ruleTable); + if (retval) { + printf("%s(), failed deleting routing rule table %p\n", __FUNCTION__, ruleTable); + return false; + } + + printf("%s(), Deleted routing rule table %p\n", __FUNCTION__, ruleTable); + return true; +} + +bool RoutingDriverWrapper::Commit(enum ipa_ip_type ip) +{ + int retval = 0; + + if (!DeviceNodeIsOpened()) + return false; + + retval = ioctl(m_fd, IPA_IOC_COMMIT_RT, ip); + if (retval) { + printf("%s(), failed commiting routing rules.\n", __FUNCTION__); + return false; + } + + printf("%s(), Commited routing rules to IPA HW.\n", __FUNCTION__); + return true; +} + +bool RoutingDriverWrapper::Reset(enum ipa_ip_type ip) +{ + int retval = 0; + + if (!DeviceNodeIsOpened()) + return false; + + retval = ioctl(m_fd, IPA_IOC_RESET_RT, ip); + retval |= ioctl(m_fd, IPA_IOC_COMMIT_RT, ip); + if (retval) { + printf("%s(), failed reseting routing block.\n", __FUNCTION__); + return false; + } + + printf("%s(), Reset command issued to IPA routing block.\n", __FUNCTION__); + return true; +} + +bool RoutingDriverWrapper::GetRoutingTable(struct ipa_ioc_get_rt_tbl *routingTable) +{ + int retval = 0; + + if (!DeviceNodeIsOpened()) + return false; + + retval = ioctl(m_fd, IPA_IOC_GET_RT_TBL, routingTable); + if (retval) { + printf("%s(), IPA_IOCTL_GET_RT_TBL ioctl failed, routingTable =0x%p, retval=0x%x.\n", __FUNCTION__, routingTable, retval); + return false; + } + + printf("%s(), IPA_IOCTL_GET_RT_TBL ioctl issued to IPA routing block.\n", __FUNCTION__); + return true; +} + +bool RoutingDriverWrapper::PutRoutingTable(uint32_t routingTableHandle) +{ + int retval = 0; + + if (!DeviceNodeIsOpened()) + return false; + + retval = ioctl(m_fd, IPA_IOC_PUT_RT_TBL, routingTableHandle); + if (retval) { + printf("%s(), IPA_IOCTL_PUT_RT_TBL ioctl failed.\n", __FUNCTION__); + return false; + } + + printf("%s(), IPA_IOCTL_PUT_RT_TBL ioctl issued to IPA routing block.\n", __FUNCTION__); + return true; +} + +bool RoutingDriverWrapper::SetNatConntrackExcRoutingTable(uint32_t routingTableHandle, bool nat_or_conntrack) +{ + int retval = 0; + + if (!DeviceNodeIsOpened()) + return false; + + if (nat_or_conntrack) + retval = ioctl(m_fd, IPA_IOC_SET_NAT_EXC_RT_TBL_IDX, routingTableHandle); + else + retval = ioctl(m_fd, IPA_IOC_SET_CONN_TRACK_EXC_RT_TBL_IDX, routingTableHandle); + + if (retval) { + printf("%s(), IPA_IOC_SET_CONN_TRACK_EXC_RT_TBL_IDX ioctl failed.\n", __FUNCTION__); + return false; + } + + printf("%s(), %s ioctl issued to IPA routing block.\n", __FUNCTION__,(nat_or_conntrack) ? + "IPA_IOC_SET_NAT_EXC_RT_TBL_IDX" : "IPA_IOC_SET_CONN_TRACK_EXC_RT_TBL_IDX"); + return true; +} + diff --git a/qcom/opensource/dataipa/kernel-tests/RoutingDriverWrapper.h b/qcom/opensource/dataipa/kernel-tests/RoutingDriverWrapper.h new file mode 100644 index 0000000000..4c1e2169dd --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/RoutingDriverWrapper.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2017,2020 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Changes from Qualcomm Innovation Center are provided under the following license: + * + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * * Neither the name of Qualcomm Innovation Center, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + */ + +#ifndef ROUTING_H_ +#define ROUTING_H_ + +#include +#include "linux/msm_ipa.h" +#include "Feature.h" + +using namespace std; + +class RoutingDriverWrapper: public Feature +{ +public: + bool AddRoutingRule(struct ipa_ioc_add_rt_rule *ruleTable); + bool AddRoutingRule(ipa_ioc_add_rt_rule_v2 *ruleTable_v2); + bool DeleteRoutingRule(struct ipa_ioc_del_rt_rule *ruleTable); + bool Commit(enum ipa_ip_type ip); + bool Reset(enum ipa_ip_type ip); + bool GetRoutingTable(struct ipa_ioc_get_rt_tbl *routingTable); + bool PutRoutingTable(uint32_t routingTableHandle); + bool SetNatConntrackExcRoutingTable(uint32_t routingTableHandle, bool nat_or_conntrack); +}; + +#endif + diff --git a/qcom/opensource/dataipa/kernel-tests/RoutingTests.cpp b/qcom/opensource/dataipa/kernel-tests/RoutingTests.cpp new file mode 100644 index 0000000000..2ca36c168d --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/RoutingTests.cpp @@ -0,0 +1,6181 @@ +/* + * Copyright (c) 2017-2018,2020 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Changes from Qualcomm Innovation Center are provided under the following license: + * + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * * Neither the name of Qualcomm Innovation Center, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + */ + +#include +#include +#include +#include +#include +#include "hton.h" // for htonl + + +#include "InterfaceAbstraction.h" +#include "Constants.h" +#include "Logger.h" +#include "TestsUtils.h" +#include "linux/msm_ipa.h" +#include "RoutingDriverWrapper.h" +#include "Filtering.h" +#include "IPAFilteringTable.h" + +#define TOS_FIELD_OFFSET (1) +#define IPV4_TTL_OFFSET (8) +#define IPV4_CSUM_OFFSET (10) +#define DST_ADDR_LSB_OFFSET_IPV4 (19) +#define SRC_ADDR_LSB_OFFSET_IPV4 (15) +#define DST_ADDR_MSB_OFFSET_IPV6 (24) +#define DST_ADDR_LSB_OFFSET_IPV6 (39) +#define TRAFFIC_CLASS_MSB_OFFSET_IPV6 (0) +#define TRAFFIC_CLASS_LSB_OFFSET_IPV6 (1) +#define FLOW_CLASS_MSB_OFFSET_IPV6 (1) +#define FLOW_CLASS_MB_OFFSET_IPV6 (2) +#define FLOW_CLASS_LSB_OFFSET_IPV6 (3) +#define HOP_LIMIT_OFFSET_IPV6 (7) +#define IPV4_DST_PORT_OFFSET (20+2) +#define IPV6_SRC_PORT_OFFSET (40) +#define IPV6_DST_PORT_OFFSET (40+2) +#define IPv4_TCP_FLAGS_OFFSET (20+13) +#define IPv6_TCP_FLAGS_OFFSET (40+13) + +#define TCP_ACK_FLAG_MASK (0x10) + +extern Logger g_Logger; + +class IpaRoutingBlockTestFixture:public TestBase +{ +public: + IpaRoutingBlockTestFixture(): + m_sendSize (BUFF_MAX_SIZE), + m_sendSize2 (BUFF_MAX_SIZE), + m_sendSize3 (BUFF_MAX_SIZE), + m_IpaIPType(IPA_IP_v4) + { + memset(m_sendBuffer, 0, sizeof(m_sendBuffer)); + memset(m_sendBuffer2, 0, sizeof(m_sendBuffer2)); + memset(m_sendBuffer3, 0, sizeof(m_sendBuffer3)); + m_testSuiteName.push_back("Routing"); + } + + static int SetupKernelModule(bool en_status = false) + { + int retval; + struct ipa_channel_config from_ipa_channels[3]; + struct test_ipa_ep_cfg from_ipa_cfg[3]; + struct ipa_channel_config to_ipa_channels[1]; + struct test_ipa_ep_cfg to_ipa_cfg[1]; + + struct ipa_test_config_header header = {0}; + struct ipa_channel_config *to_ipa_array[1]; + struct ipa_channel_config *from_ipa_array[3]; + + /* From ipa configurations - 3 pipes */ + memset(&from_ipa_cfg[0], 0, sizeof(from_ipa_cfg[0])); + prepare_channel_struct(&from_ipa_channels[0], + header.from_ipa_channels_num++, + IPA_CLIENT_TEST2_CONS, + (void *)&from_ipa_cfg[0], + sizeof(from_ipa_cfg[0]), en_status); + from_ipa_array[0] = &from_ipa_channels[0]; + + memset(&from_ipa_cfg[1], 0, sizeof(from_ipa_cfg[1])); + prepare_channel_struct(&from_ipa_channels[1], + header.from_ipa_channels_num++, + IPA_CLIENT_TEST3_CONS, + (void *)&from_ipa_cfg[1], + sizeof(from_ipa_cfg[1]), en_status); + from_ipa_array[1] = &from_ipa_channels[1]; + + memset(&from_ipa_cfg[2], 0, sizeof(from_ipa_cfg[2])); + prepare_channel_struct(&from_ipa_channels[2], + header.from_ipa_channels_num++, + IPA_CLIENT_TEST4_CONS, + (void *)&from_ipa_cfg[2], + sizeof(from_ipa_cfg[2]), en_status); + from_ipa_array[2] = &from_ipa_channels[2]; + + /* To ipa configurations - 1 pipes */ + memset(&to_ipa_cfg[0], 0, sizeof(to_ipa_cfg[0])); + prepare_channel_struct(&to_ipa_channels[0], + header.to_ipa_channels_num++, + IPA_CLIENT_TEST_PROD, + (void *)&to_ipa_cfg[0], + sizeof(to_ipa_cfg[0])); + to_ipa_array[0] = &to_ipa_channels[0]; + + prepare_header_struct(&header, from_ipa_array, to_ipa_array); + + retval = GenericConfigureScenario(&header); + + return retval; + } + + bool Setup(bool en_status) + { + bool bRetVal = true; + + bRetVal = SetupKernelModule(en_status); + if (bRetVal != true) { + return bRetVal; + } + m_producer.Open(INTERFACE0_TO_IPA_DATA_PATH, INTERFACE0_FROM_IPA_DATA_PATH); + + m_consumer.Open(INTERFACE1_TO_IPA_DATA_PATH, INTERFACE1_FROM_IPA_DATA_PATH); + m_consumer2.Open(INTERFACE2_TO_IPA_DATA_PATH, INTERFACE2_FROM_IPA_DATA_PATH); + m_defaultConsumer.Open(INTERFACE3_TO_IPA_DATA_PATH, INTERFACE3_FROM_IPA_DATA_PATH); + + if (!m_routing.DeviceNodeIsOpened()) { + printf("Routing block is not ready for immediate commands!\n"); + return false; + } + + if (!m_filtering.DeviceNodeIsOpened()) { + printf("Filtering block is not ready for immediate commands!\n"); + return false; + } + m_routing.Reset(IPA_IP_v4); + m_routing.Reset(IPA_IP_v6); + + return true; + } /* Setup()*/ + + bool Setup() + { + return Setup(false); + } + + bool Teardown() + { + if (!m_routing.DeviceNodeIsOpened()) { + printf("Routing block is not ready for immediate commands!\n"); + return false; + } + if (!m_filtering.DeviceNodeIsOpened()) { + printf("Filtering block is not ready for immediate commands!\n"); + return false; + } + + m_producer.Close(); + m_consumer.Close(); + m_consumer2.Close(); + m_defaultConsumer.Close(); + + return true; + } /* Teardown() */ + + bool LoadFiles(enum ipa_ip_type ip) + { + string fileName; + + if (IPA_IP_v4 == ip) { + fileName = "Input/IPv4_1"; + } else { + fileName = "Input/IPv6"; + } + + if (!LoadDefaultPacket(ip, m_sendBuffer, m_sendSize)) { + LOG_MSG_ERROR("Failed loading default Packet"); + return false; + } + + if (!LoadDefaultPacket(ip, m_sendBuffer2, m_sendSize2)) { + LOG_MSG_ERROR("Failed loading default Packet"); + return false; + } + + if (!LoadDefaultPacket(ip, m_sendBuffer3, m_sendSize3)) { + LOG_MSG_ERROR("Failed loading default Packet"); + return false; + } + + return true; + } + + bool ReceivePacketAndCompareFrom(InterfaceAbstraction& cons, Byte* send, + size_t send_sz, bool shouldBeHit) + { + size_t receivedSize = 0; + bool isSuccess = true; + + /* Receive results*/ + Byte *rxBuff1 = new Byte[0x400]; + + if (NULL == rxBuff1) + { + printf("Memory allocation error.\n"); + return false; + } + + receivedSize = cons.ReceiveData(rxBuff1, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize, cons.m_fromChannelName.c_str()); + + // Compare results + isSuccess &= CompareResultVsGolden_w_Status(send, send_sz, rxBuff1, receivedSize); + + if (shouldBeHit) { + isSuccess &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_0) ? + IsCacheHit_v5_0(send_sz, receivedSize, rxBuff1) : IsCacheHit(send_sz, receivedSize, rxBuff1); + } + else + { + isSuccess &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_0) ? + IsCacheMiss_v5_0(send_sz, receivedSize, rxBuff1) : IsCacheMiss(send_sz, receivedSize, rxBuff1); + } + + size_t recievedBufferSize = receivedSize * 3; + size_t sentBufferSize = m_sendSize * 3; + char *recievedBuffer = new char[recievedBufferSize]; + char *sentBuffer = new char[sentBufferSize]; +// char * p = recievedBuffer; + size_t j; + for(j = 0; j < m_sendSize; j++) + snprintf(&sentBuffer[3 * j], sentBufferSize - (3 * j + 1), " %02X", send[j]); + for(j = 0; j < receivedSize; j++) +// recievedBuffer += sprintf(recievedBuffer, "%02X", rxBuff1[i]); + snprintf(&recievedBuffer[3 * j], recievedBufferSize - (3 * j + 1), " %02X", rxBuff1[j]); + printf("Expected Value (%zu)\n%s\n, Received Value1(%zu)\n%s\n",send_sz,sentBuffer,receivedSize,recievedBuffer); + + delete[] rxBuff1; + delete[] recievedBuffer; + delete[] sentBuffer; + + return isSuccess; + } + + bool ReceivePacketsAndCompare() + { + size_t receivedSize = 0; + size_t receivedSize2 = 0; + size_t receivedSize3 = 0; + bool pkt1_cmp_succ, pkt2_cmp_succ, pkt3_cmp_succ; + + // Receive results + Byte *rxBuff1 = new Byte[0x400]; + Byte *rxBuff2 = new Byte[0x400]; + Byte *rxBuff3 = new Byte[0x400]; + + if (NULL == rxBuff1 || NULL == rxBuff2 || NULL == rxBuff3) + { + printf("Memory allocation error.\n"); + return false; + } + + memset(rxBuff1, 0, 0x400); + memset(rxBuff2, 0, 0x400); + memset(rxBuff3, 0, 0x400); + + receivedSize = m_consumer.ReceiveData(rxBuff1, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize, m_consumer.m_fromChannelName.c_str()); + + receivedSize2 = m_consumer2.ReceiveData(rxBuff2, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize2, m_consumer2.m_fromChannelName.c_str()); + + receivedSize3 = m_defaultConsumer.ReceiveData(rxBuff3, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize3, m_defaultConsumer.m_fromChannelName.c_str()); + + /* Compare results */ + pkt1_cmp_succ = CompareResultVsGolden(m_sendBuffer, m_sendSize, rxBuff1, receivedSize); + pkt2_cmp_succ = CompareResultVsGolden(m_sendBuffer2, m_sendSize2, rxBuff2, receivedSize2); + pkt3_cmp_succ = CompareResultVsGolden(m_sendBuffer3, m_sendSize3, rxBuff3, receivedSize3); + + size_t recievedBufferSize = + MAX3(receivedSize, receivedSize2, receivedSize3) * 3; + size_t sentBufferSize = + MAX3(m_sendSize, m_sendSize2, m_sendSize3) * 3; + char *recievedBuffer = new char[recievedBufferSize]; + char *sentBuffer = new char[sentBufferSize]; + + if (NULL == recievedBuffer || NULL == sentBuffer) { + printf("Memory allocation error\n"); + return false; + } + + size_t j; + memset(recievedBuffer, 0, recievedBufferSize); + memset(sentBuffer, 0, sentBufferSize); + for(j = 0; j < m_sendSize; j++) + snprintf(&sentBuffer[3 * j], sentBufferSize - (3 * j + 1), " %02X", m_sendBuffer[j]); + for(j = 0; j < receivedSize; j++) + snprintf(&recievedBuffer[3 * j], recievedBufferSize - (3 * j + 1), " %02X", rxBuff1[j]); + printf("Expected Value1(%zu)\n%s\n, Received Value1(%zu)\n%s\n-->Value1 %s\n", + m_sendSize,sentBuffer,receivedSize,recievedBuffer, + pkt1_cmp_succ?"Match":"no Match"); + + memset(recievedBuffer, 0, recievedBufferSize); + memset(sentBuffer, 0, sentBufferSize); + for(j = 0; j < m_sendSize2; j++) + snprintf(&sentBuffer[3 * j], sentBufferSize - (3 * j + 1), " %02X", m_sendBuffer2[j]); + for(j = 0; j < receivedSize2; j++) + snprintf(&recievedBuffer[3 * j], recievedBufferSize - (3 * j + 1), " %02X", rxBuff2[j]); + printf("Expected Value2 (%zu)\n%s\n, Received Value2(%zu)\n%s\n-->Value2 %s\n", + m_sendSize2,sentBuffer,receivedSize2,recievedBuffer, + pkt2_cmp_succ?"Match":"no Match"); + + memset(recievedBuffer, 0, recievedBufferSize); + memset(sentBuffer, 0, sentBufferSize); + for(j = 0; j < m_sendSize3; j++) + snprintf(&sentBuffer[3 * j], sentBufferSize - (3 * j + 1), " %02X", m_sendBuffer3[j]); + for(j = 0; j < receivedSize3; j++) + snprintf(&recievedBuffer[3 * j], recievedBufferSize - (3 * j + 1), " %02X", rxBuff3[j]); + printf("Expected Value3 (%zu)\n%s\n, Received Value3(%zu)\n%s\n-->Value3 %s\n", + m_sendSize3,sentBuffer,receivedSize3,recievedBuffer, + pkt3_cmp_succ?"Match":"no Match"); + + delete[] recievedBuffer; + delete[] sentBuffer; + + delete[] rxBuff1; + delete[] rxBuff2; + delete[] rxBuff3; + + return pkt1_cmp_succ && pkt2_cmp_succ && pkt3_cmp_succ; + } + + void print_packets(size_t receivedSize, size_t m_sendSize, size_t recievedBufferSize, size_t sentBufferSize, Byte *rxBuff, Byte *m_sendBuffer, char *recievedBuffer, char *sentBuffer) + { + size_t j; + + for(j = 0; j < m_sendSize; j++) { + snprintf(&sentBuffer[3 * j], sentBufferSize - 3 * j, + " %02X", m_sendBuffer[j]); + } + for(j = 0; j < receivedSize; j++) { + snprintf(&recievedBuffer[3 * j], recievedBufferSize- 3 * j, + " %02X", rxBuff[j]); + } + printf("Expected Value (%zu)\n%s\n, Received Value(%zu)\n%s\n",m_sendSize,sentBuffer,receivedSize,recievedBuffer); + } + + ~IpaRoutingBlockTestFixture() + { + m_sendSize = 0; + m_sendSize2 = 0; + m_sendSize3 = 0; + } + + void InitFilteringBlock() + { + IPAFilteringTable fltTable; + struct ipa_ioc_get_rt_tbl st_rt_tbl; + struct ipa_flt_rule_add flt_rule_entry; + + memset(&st_rt_tbl, 0, sizeof(st_rt_tbl)); + memset(&flt_rule_entry, 0, sizeof(flt_rule_entry)); + strlcpy(st_rt_tbl.name, "LAN", sizeof(st_rt_tbl.name)); + st_rt_tbl.ip = m_IpaIPType; + fltTable.Init(m_IpaIPType, IPA_CLIENT_TEST_PROD, false, 1); + m_routing.GetRoutingTable(&st_rt_tbl); + flt_rule_entry.rule.rt_tbl_hdl = st_rt_tbl.hdl; + fltTable.AddRuleToTable(flt_rule_entry); + m_filtering.AddFilteringRule(fltTable.GetFilteringTable()); + } + + inline bool VerifyStatusReceived(size_t SendSize, size_t RecvSize) + { + size_t stts_size = sizeof(struct ipa3_hw_pkt_status); + + if (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_0) { + stts_size = sizeof(struct ipa3_hw_pkt_status_hw_v5_0); + } + + if ((RecvSize <= SendSize) || + ((RecvSize - SendSize) != stts_size)){ + printf("received buffer size does not match! sent:receive [%zu]:[%zu]\n",SendSize,RecvSize); + return false; + } + + return true; + } + + inline bool IsCacheHit(size_t SendSize, size_t RecvSize, void *Buff) + { + struct ipa3_hw_pkt_status *pStatus = (struct ipa3_hw_pkt_status *)Buff; + + if (VerifyStatusReceived(SendSize,RecvSize) == false){ + return false; + } + + if((bool)pStatus->route_hash){ + printf ("%s::cache hit!! \n",__FUNCTION__); + return true; + } + + printf ("%s::cache miss!! \n",__FUNCTION__); + return false; + + } + + inline bool IsCacheHit_v5_0(size_t SendSize, size_t RecvSize, void *Buff) + { + struct ipa3_hw_pkt_status_hw_v5_0 *pStatus = (struct ipa3_hw_pkt_status_hw_v5_0 *)Buff; + + if (VerifyStatusReceived(SendSize,RecvSize) == false){ + return false; + } + + if((bool)pStatus->route_hash){ + printf ("%s::cache hit!! \n",__FUNCTION__); + return true; + } + + printf ("%s::cache miss!! \n",__FUNCTION__); + return false; + + } + + inline bool IsCacheMiss(size_t SendSize, size_t RecvSize, void *Buff) + { + struct ipa3_hw_pkt_status *pStatus = (struct ipa3_hw_pkt_status *)Buff; + + if (VerifyStatusReceived(SendSize,RecvSize) == false){ + return false; + } + + if(!((bool)pStatus->route_hash)){ + printf ("%s::cache miss!! \n",__FUNCTION__); + return true; + } + + printf ("%s::cache hit!! \n",__FUNCTION__); + return false; + } + + inline bool IsCacheMiss_v5_0(size_t SendSize, size_t RecvSize, void *Buff) + { + struct ipa3_hw_pkt_status_hw_v5_0 *pStatus = (struct ipa3_hw_pkt_status_hw_v5_0 *)Buff; + + if (VerifyStatusReceived(SendSize,RecvSize) == false){ + return false; + } + + if(!((bool)pStatus->route_hash)){ + printf ("%s::cache miss!! \n",__FUNCTION__); + return true; + } + + printf ("%s::cache hit!! \n",__FUNCTION__); + return false; + } + + inline bool IsTTLUpdated_v5_5(size_t SendSize, size_t RecvSize, void *Buff) + { + struct ipa3_hw_pkt_status_hw_v5_5 *pStatus = (struct ipa3_hw_pkt_status_hw_v5_5 *)Buff; + + if (VerifyStatusReceived(SendSize,RecvSize) == false){ + return false; + } + + if(!((bool)pStatus->ttl_dec)){ + printf ("%s::cache miss!! \n",__FUNCTION__); + return true; + } + + printf ("%s::cache hit!! \n",__FUNCTION__); + return false; + } + + static RoutingDriverWrapper m_routing; + static Filtering m_filtering; + + static const size_t BUFF_MAX_SIZE = 1024; + + InterfaceAbstraction m_producer; + InterfaceAbstraction m_consumer; + InterfaceAbstraction m_consumer2; + InterfaceAbstraction m_defaultConsumer; + Byte m_sendBuffer[BUFF_MAX_SIZE]; // First input file / IP packet + Byte m_sendBuffer2[BUFF_MAX_SIZE]; // Second input file / IP packet + Byte m_sendBuffer3[BUFF_MAX_SIZE]; // Third input file (default) / IP packet + size_t m_sendSize; + size_t m_sendSize2; + size_t m_sendSize3; + enum ipa_ip_type m_IpaIPType; + + +private: +}; + +RoutingDriverWrapper IpaRoutingBlockTestFixture::m_routing; +Filtering IpaRoutingBlockTestFixture::m_filtering; + +/*---------------------------------------------------------------------------*/ +/* Test1: Tests routing by destination address */ +/*---------------------------------------------------------------------------*/ +class IpaRoutingBlockTest1 : public IpaRoutingBlockTestFixture +{ +public: + IpaRoutingBlockTest1() + { + m_name = "IpaRoutingBlockTest1"; + m_description =" \ + Routing block test 001 - Destination address exact match\1. Generate and commit a single routing tables. \ + 2. Generate and commit Three routing rules: (DST & Mask Match). \ + All DST_IP == (192.169.2.170 & 255.255.255.255)traffic goes to pipe IPA_CLIENT_TEST2_CONS \ + All DST_IP == (192.168.2.255 & 255.255.255.255)traffic goes to pipe IPA_CLIENT_TEST3_CONS\ + All other traffic goes to pipe IPA_CLIENT_TEST4_CONS"; + m_IpaIPType = IPA_IP_v4; + Register(*this); + } + + bool Run() + { + bool res = false; + bool isSuccess = false; + + // Add the relevant routing rules + res = AddRules(); + if (false == res) { + printf("Failed adding routing rules.\n"); + return false; + } + + // Load input data (IP packet) from file + res = LoadFiles(IPA_IP_v4); + if (false == res) { + printf("Failed loading files.\n"); + return false; + } + + // Send first packet + m_sendBuffer[DST_ADDR_LSB_OFFSET_IPV4] = 0xFF; + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send second packet + m_sendBuffer2[DST_ADDR_LSB_OFFSET_IPV4] = 0xAA; + isSuccess = m_producer.SendData(m_sendBuffer2, m_sendSize2); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send third packet + isSuccess = m_producer.SendData(m_sendBuffer3, m_sendSize3); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Receive packets from the channels and compare results + isSuccess = ReceivePacketsAndCompare(); + + return isSuccess; + } // Run() + + bool AddRules() + { + struct ipa_ioc_add_rt_rule *rt_rule; + struct ipa_rt_rule_add *rt_rule_entry; + const int NUM_RULES = 3; + + rt_rule = (struct ipa_ioc_add_rt_rule *) + calloc(1, sizeof(struct ipa_ioc_add_rt_rule) + + NUM_RULES*sizeof(struct ipa_rt_rule_add)); + + if(!rt_rule) { + printf("Failed memory allocation for rt_rule\n"); + return false; + } + + rt_rule->commit = 1; + rt_rule->num_rules = NUM_RULES; + rt_rule->ip = IPA_IP_v4; + strlcpy(rt_rule->rt_tbl_name, "LAN", sizeof(rt_rule->rt_tbl_name)); + + rt_rule_entry = &rt_rule->rules[0]; + rt_rule_entry->at_rear = 0; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST2_CONS; +// rt_rule_entry->rule.hdr_hdl = hdr_entry->hdr_hdl; // gidons, there is no support for header insertion / removal yet. + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v4.dst_addr = 0xC0A802FF; + rt_rule_entry->rule.attrib.u.v4.dst_addr_mask = 0xFFFFFFFF; + + rt_rule_entry = &rt_rule->rules[1]; + rt_rule_entry->at_rear = 0; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST3_CONS; +// rt_rule_entry->rule.hdr_hdl = hdr_entry->hdr_hdl; // gidons, there is no support for header insertion / removal yet. + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v4.dst_addr = 0xC0A802AA; + rt_rule_entry->rule.attrib.u.v4.dst_addr_mask = 0xFFFFFFFF; + + rt_rule_entry = &rt_rule->rules[2]; + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST4_CONS; + + if (false == m_routing.AddRoutingRule(rt_rule)) + { + printf("Routing rule addition failed!\n"); + return false; + } + + printf("rt rule hdl1=%x\n", rt_rule_entry->rt_rule_hdl); + + free(rt_rule); + + InitFilteringBlock(); + + return true; + } +}; + +/*---------------------------------------------------------------------------*/ +/* Test2: Tests routing by destination address with a subnet (mask) */ +/*---------------------------------------------------------------------------*/ +class IpaRoutingBlockTest2 : IpaRoutingBlockTestFixture +{ +public: + IpaRoutingBlockTest2() + { + m_name = "IpaRoutingBlockTest2"; + m_description =" \ + Routing block test 002 - Destination address subnet match \ + 1. Generate and commit a single routing tables. \ + 2. Generate and commit Three routing rules: (DST & Mask Match). \ + All DST_IP == (192.169.170.0 & 255.255.255.0)traffic goes to pipe IPA_CLIENT_TEST2_CONS \ + All DST_IP == (192.168.255.0 & 255.255.255.0)traffic goes to pipe IPA_CLIENT_TEST3_CONS\ + All other traffic goes to pipe IPA_CLIENT_TEST4_CONS"; + m_IpaIPType = IPA_IP_v4; + Register(*this); + } + + bool Run() + { + bool res = false; + bool isSuccess = false; + + printf("ENTRY: IpaRoutingBlockTest2::Run()\n"); + + // Add the relevant routing rules + res = AddRules(); + if (false == res) { + printf("Failed adding routing rules.\n"); + return false; + } + + // Load input data (IP packet) from file + res = LoadFiles(IPA_IP_v4); + if (false == res) { + printf("Failed loading files.\n"); + return false; + } + + // Send first packet + m_sendBuffer[18] = 0xFF; + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send second packet + m_sendBuffer2[18] = 0xAA; + isSuccess = m_producer.SendData(m_sendBuffer2, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send third packet + isSuccess = m_producer.SendData(m_sendBuffer3, m_sendSize3); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Receive packets from the channels and compare results + isSuccess = ReceivePacketsAndCompare(); + + return isSuccess; + } // Run() + + bool AddRules() + { + struct ipa_ioc_add_rt_rule *rt_rule; + struct ipa_rt_rule_add *rt_rule_entry; + const int NUM_RULES = 3; + + printf("ENTRY: IpaRoutingBlockTest2::AddRules()\n"); + + rt_rule = (struct ipa_ioc_add_rt_rule *) + calloc(1, sizeof(struct ipa_ioc_add_rt_rule) + + NUM_RULES*sizeof(struct ipa_rt_rule_add)); + + if(!rt_rule) { + printf("fail\n"); + return false; + } + + rt_rule->commit = 1; + rt_rule->num_rules = NUM_RULES; + rt_rule->ip = IPA_IP_v4; + strlcpy(rt_rule->rt_tbl_name, "LAN", sizeof(rt_rule->rt_tbl_name)); + + rt_rule_entry = &rt_rule->rules[0]; + rt_rule_entry->at_rear = 0; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST2_CONS; +// rt_rule_entry->rule.hdr_hdl = hdr_entry->hdr_hdl; // gidons, there is no support for header insertion / removal yet. + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v4.dst_addr = 0xC0A8FF00; + rt_rule_entry->rule.attrib.u.v4.dst_addr_mask = 0xFFFFFF00; + + rt_rule_entry = &rt_rule->rules[1]; + rt_rule_entry->at_rear = 0; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST3_CONS; +// rt_rule_entry->rule.hdr_hdl = hdr_entry->hdr_hdl; // gidons, there is no support for header insertion / removal yet. + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v4.dst_addr = 0xC0A8AA00; + rt_rule_entry->rule.attrib.u.v4.dst_addr_mask = 0xFFFFFF00; + + rt_rule_entry = &rt_rule->rules[2]; + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST4_CONS; + + printf("Before calling m_routing.AddRoutingRule()\n"); + printf("m_routing = %p\n", &m_routing); + + if (false == m_routing.AddRoutingRule(rt_rule)) + { + printf("Routing rule addition failed!\n"); + return false; + } + + printf("rt rule hdl1=%x\n", rt_rule_entry->rt_rule_hdl); + + free(rt_rule); + + InitFilteringBlock(); + + return true; + } +}; + + +/*---------------------------------------------------------------------------*/ +/* Test3: Tests routing by TOS (Type Of Service) */ +/*---------------------------------------------------------------------------*/ +class IpaRoutingBlockTest3 : IpaRoutingBlockTestFixture +{ +public: + IpaRoutingBlockTest3() + { + m_name = "IpaRoutingBlockTest3"; + m_description = " \ + Routing block test 003 - TOS exact match\ + 1. Generate and commit a single routing tables. \ + 2. Generate and commit Three routing rules: (DST & Mask Match). \ + All TOS == 0xBF traffic goes to pipe IPA_CLIENT_TEST2_CONS \ + All TOS == 0x3A traffic goes to pipe IPA_CLIENT_TEST3_CONS\ + All other traffic goes to pipe IPA_CLIENT_TEST4_CONS"; + m_IpaIPType = IPA_IP_v4; + Register(*this); + } + + bool Run() + { + bool res = false; + bool isSuccess = false; + + // Add the relevant routing rules + res = AddRules(); + if (false == res) { + printf("Failed adding routing rules.\n"); + return false; + } + + // Load input data (IP packet) from file + res = LoadFiles(IPA_IP_v4); + if (false == res) { + printf("Failed loading files.\n"); + return false; + } + + // Send first packet + m_sendBuffer[TOS_FIELD_OFFSET] = 0xBF; + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send second packet + m_sendBuffer2[TOS_FIELD_OFFSET] = 0x3A; + isSuccess = m_producer.SendData(m_sendBuffer2, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send third packet + isSuccess = m_producer.SendData(m_sendBuffer3, m_sendSize3); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Receive packets from the channels and compare results + isSuccess = ReceivePacketsAndCompare(); + + return isSuccess; + } // Run() + + bool AddRules() + { + struct ipa_ioc_add_rt_rule *rt_rule; + struct ipa_rt_rule_add *rt_rule_entry; + const int NUM_RULES = 3; + + rt_rule = (struct ipa_ioc_add_rt_rule *) + calloc(1, sizeof(struct ipa_ioc_add_rt_rule) + + NUM_RULES*sizeof(struct ipa_rt_rule_add)); + + if (!rt_rule) { + printf("fail\n"); + return false; + } + + rt_rule->commit = 1; + rt_rule->num_rules = NUM_RULES; + rt_rule->ip = IPA_IP_v4; + strlcpy(rt_rule->rt_tbl_name, "LAN", sizeof(rt_rule->rt_tbl_name)); + + rt_rule_entry = &rt_rule->rules[0]; + rt_rule_entry->at_rear = 0; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST2_CONS; +// rt_rule_entry->rule.hdr_hdl = hdr_entry->hdr_hdl; + // gidons, there is no support for header insertion / removal yet. + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_TOS; + rt_rule_entry->rule.attrib.u.v4.tos = 0xBF; + + rt_rule_entry = &rt_rule->rules[1]; + rt_rule_entry->at_rear = 0; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST3_CONS; +// rt_rule_entry->rule.hdr_hdl = hdr_entry->hdr_hdl; // gidons, there is no support for header insertion / removal yet. + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_TOS; + rt_rule_entry->rule.attrib.u.v4.tos = 0x3A; + + rt_rule_entry = &rt_rule->rules[2]; + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST4_CONS; + + if (false == m_routing.AddRoutingRule(rt_rule)) + { + printf("Routing rule addition failed!\n"); + return false; + } + + printf("rt rule hdl1=%x\n", rt_rule_entry->rt_rule_hdl); + + free(rt_rule); + + InitFilteringBlock(); + + return true; + } +}; + +/*---------------------------------------------------------------------------*/ +/* Test4: Destination address exact match and TOS exact match */ +/*---------------------------------------------------------------------------*/ +class IpaRoutingBlockTest4 : IpaRoutingBlockTestFixture +{ +public: + IpaRoutingBlockTest4() + { + m_name = "IpaRoutingBlockTest4"; + m_description =" \ + Routing block test 004 - Source and Destination address and TOS exact match \ + 1. Generate and commit a single routing tables. \ + 2. Generate and commit Three routing rules: (DST & Mask Match). \ + All DST_IP == (192.169.2.255 & 255.255.255.255) and TOS == 0xFF traffic goes to pipe IPA_CLIENT_TEST2_CONS \ + All DST_IP == (192.168.2.170 & 255.255.255.255) and TOS == 0xAA traffic goes to pipe IPA_CLIENT_TEST3_CONS\ + All DST_IP == (192.168.2.85 & 255.255.255.255) and SRC_IP == (192.168.2.241 & 255.255.255.255) TOS == 0x24 traffic goes to pipe IPA_CLIENT_TEST3_CONS"; + m_IpaIPType = IPA_IP_v4; + Register(*this); + } + + bool Run() + { + bool res = false; + bool isSuccess = false; + + // Add the relevant routing rules + res = AddRules(); + if (false == res) { + printf("Failed adding routing rules.\n"); + return false; + } + + // Load input data (IP packet) from file + res = LoadFiles(IPA_IP_v4); + if (false == res) { + printf("Failed loading files.\n"); + return false; + } + + // Send first packet + m_sendBuffer[TOS_FIELD_OFFSET] = 0xFF; + m_sendBuffer[DST_ADDR_LSB_OFFSET_IPV4] = 0xFF; + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send second packet + m_sendBuffer2[TOS_FIELD_OFFSET] = 0xAA; + m_sendBuffer2[DST_ADDR_LSB_OFFSET_IPV4] = 0xAA; + isSuccess = m_producer.SendData(m_sendBuffer2, m_sendSize2); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send third packet + m_sendBuffer3[TOS_FIELD_OFFSET] = 0x24; + m_sendBuffer3[DST_ADDR_LSB_OFFSET_IPV4] = 0x55; + m_sendBuffer3[SRC_ADDR_LSB_OFFSET_IPV4] = 0xF1; + isSuccess = m_producer.SendData(m_sendBuffer3, m_sendSize3); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Receive packets from the channels and compare results + isSuccess = ReceivePacketsAndCompare(); + + return isSuccess; + } // Run() + + bool AddRules() + { + struct ipa_ioc_add_rt_rule *rt_rule; + struct ipa_rt_rule_add *rt_rule_entry; + const int NUM_RULES = 3; + + rt_rule = (struct ipa_ioc_add_rt_rule *) + calloc(1, sizeof(struct ipa_ioc_add_rt_rule) + + NUM_RULES*sizeof(struct ipa_rt_rule_add)); + + if(!rt_rule) { + printf("fail\n"); + return false; + } + + rt_rule->commit = 1; + rt_rule->num_rules = NUM_RULES; + rt_rule->ip = IPA_IP_v4; + strlcpy(rt_rule->rt_tbl_name, "LAN", sizeof(rt_rule->rt_tbl_name)); + + rt_rule_entry = &rt_rule->rules[0]; + rt_rule_entry->at_rear = 0; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST2_CONS; + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_TOS | IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v4.tos = 0xFF; + rt_rule_entry->rule.attrib.u.v4.dst_addr = 0xC0A802FF; + rt_rule_entry->rule.attrib.u.v4.dst_addr_mask = 0xFFFFFFFF; + + + rt_rule_entry = &rt_rule->rules[1]; + rt_rule_entry->at_rear = 0; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST3_CONS; + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_TOS | IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v4.tos = 0xAA; + rt_rule_entry->rule.attrib.u.v4.dst_addr = 0xC0A802AA; + rt_rule_entry->rule.attrib.u.v4.dst_addr_mask = 0xFFFFFFFF; + + rt_rule_entry = &rt_rule->rules[2]; + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST4_CONS; + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_TOS | IPA_FLT_DST_ADDR | IPA_FLT_SRC_ADDR; + rt_rule_entry->rule.attrib.u.v4.tos = 0x24; + rt_rule_entry->rule.attrib.u.v4.dst_addr = 0xC0A80255; + rt_rule_entry->rule.attrib.u.v4.dst_addr_mask = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v4.src_addr = 0xC0A802F1; + rt_rule_entry->rule.attrib.u.v4.src_addr_mask = 0xFFFFFFFF; + + if (false == m_routing.AddRoutingRule(rt_rule)) + { + printf("Routing rule addition failed!\n"); + return false; + } + + printf("rt rule hdl1=%x\n", rt_rule_entry->rt_rule_hdl); + + free(rt_rule); + + InitFilteringBlock(); + + return true; + } +}; + +/*---------------------------------------------------------------------------*/ +/* Test5: IPv6 - Tests routing by destination address */ +/*---------------------------------------------------------------------------*/ +class IpaRoutingBlockTest5 : public IpaRoutingBlockTestFixture +{ +public: + IpaRoutingBlockTest5() + { + m_name = "IpaRoutingBlockTest5"; + m_description =" \ + Routing block test 005 - IPv6 Destination address exact match \ + 1. Generate and commit a single routing tables. \ + 2. Generate and commit Three routing rules: (DST & Mask Match). \ + All DST_IP == 0XFF020000 \ + 0x00000000 \ + 0x00000000 \ + 0X000000FF \ + traffic goes to pipe IPA_CLIENT_TEST2_CONS \ + All DST_IP == 0XFF020000 \ + 0x00000000 \ + 0x00000000 \ + 0X000000FF \ + traffic goes to pipe IPA_CLIENT_TEST3_CONS\ + All other traffic goes to pipe IPA_CLIENT_TEST4_CONS"; + m_IpaIPType = IPA_IP_v6; + Register(*this); + } + + bool Run() + { + bool res = false; + bool isSuccess = false; + + // Add the relevant routing rules + res = AddRules(); + if (false == res) { + printf("Failed adding routing rules.\n"); + return false; + } + + // Load input data (IP packet) from file + res = LoadFiles(IPA_IP_v6); + if (false == res) { + printf("Failed loading files.\n"); + return false; + } + + // Send first packet + m_sendBuffer[DST_ADDR_LSB_OFFSET_IPV6] = 0xFF; + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send second packet + m_sendBuffer2[DST_ADDR_LSB_OFFSET_IPV6] = 0xAA; + isSuccess = m_producer.SendData(m_sendBuffer2, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send third packet + isSuccess = m_producer.SendData(m_sendBuffer3, m_sendSize3); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Receive packets from the channels and compare results + isSuccess = ReceivePacketsAndCompare(); + + return isSuccess; + } // Run() + + bool AddRules() + { + struct ipa_ioc_add_rt_rule *rt_rule; + struct ipa_rt_rule_add *rt_rule_entry; + const int NUM_RULES = 3; + + rt_rule = (struct ipa_ioc_add_rt_rule *) + calloc(1, sizeof(struct ipa_ioc_add_rt_rule) + + NUM_RULES*sizeof(struct ipa_rt_rule_add)); + + if(!rt_rule) { + printf("fail\n"); + return false; + } + + rt_rule->commit = 1; + rt_rule->num_rules = NUM_RULES; + rt_rule->ip = IPA_IP_v6; + strlcpy(rt_rule->rt_tbl_name, "LAN", sizeof(rt_rule->rt_tbl_name)); + + rt_rule_entry = &rt_rule->rules[0]; + rt_rule_entry->at_rear = 0; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST2_CONS; +// rt_rule_entry->rule.hdr_hdl = hdr_entry->hdr_hdl; // gidons, there is no support for header insertion / removal yet. + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v6.dst_addr[0] = 0XFF020000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[1] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[2] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[3] = 0X000000FF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[0] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[1] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[2] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[3] = 0xFFFFFFFF; + + rt_rule_entry = &rt_rule->rules[1]; + rt_rule_entry->at_rear = 0; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST3_CONS; +// rt_rule_entry->rule.hdr_hdl = hdr_entry->hdr_hdl; // gidons, there is no support for header insertion / removal yet. + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v6.dst_addr[0] = 0XFF020000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[1] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[2] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[3] = 0X000000AA; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[0] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[1] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[2] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[3] = 0xFFFFFFFF; + + rt_rule_entry = &rt_rule->rules[2]; + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST4_CONS; + + if (false == m_routing.AddRoutingRule(rt_rule)) + { + printf("Routing rule addition failed!\n"); + return false; + } + + printf("rt rule hdl1=%x\n", rt_rule_entry->rt_rule_hdl); + + free(rt_rule); + + InitFilteringBlock(); + + return true; + } +}; + +/*---------------------------------------------------------------------------*/ +/* Test6: IPv6 - Tests routing by destination address */ +/*---------------------------------------------------------------------------*/ +class IpaRoutingBlockTest006 : public IpaRoutingBlockTestFixture +{ +public: + IpaRoutingBlockTest006() + { + m_name = "IpaRoutingBlockTest006"; + m_description =" \ + Routing block test 006 - IPv6 Destination address Subnet match \ + 1. Generate and commit a single routing tables. \ + 2. Generate and commit Three routing rules: (DST & Mask Match 0xFFFFFFFF,0xFFFFFFFF,0x00000000,0x0000000). \ + All DST_IP == 0X11020000 \ + 0x00000000 \ + 0x00000000 \ + 0X0000000C \ + traffic goes to pipe IPA_CLIENT_TEST2_CONS \ + All DST_IP == 0X22020000 \ + 0x00000000 \ + 0x00000000 \ + 0X0000000C \ + traffic goes to pipe IPA_CLIENT_TEST3_CONS\ + All other traffic goes to pipe IPA_CLIENT_TEST4_CONS"; + m_IpaIPType = IPA_IP_v6; + Register(*this); + } + + bool Run() + { + bool res = false; + bool isSuccess = false; + + // Add the relevant routing rules + res = AddRules(); + if (false == res) { + printf("Failed adding routing rules.\n"); + return false; + } + + // Load input data (IP packet) from file + res = LoadFiles(IPA_IP_v6); + if (false == res) { + printf("Failed loading files.\n"); + return false; + } + + // Send first packet + m_sendBuffer[DST_ADDR_MSB_OFFSET_IPV6] = 0x11; + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send second packet + m_sendBuffer2[DST_ADDR_MSB_OFFSET_IPV6] = 0x22; + isSuccess = m_producer.SendData(m_sendBuffer2, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send third packet + isSuccess = m_producer.SendData(m_sendBuffer3, m_sendSize3); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Receive packets from the channels and compare results + isSuccess = ReceivePacketsAndCompare(); + + return isSuccess; + } // Run() + + bool AddRules() + { + struct ipa_ioc_add_rt_rule *rt_rule; + struct ipa_rt_rule_add *rt_rule_entry; + const int NUM_RULES = 3; + + rt_rule = (struct ipa_ioc_add_rt_rule *) + calloc(1, sizeof(struct ipa_ioc_add_rt_rule) + + NUM_RULES*sizeof(struct ipa_rt_rule_add)); + + if(!rt_rule) { + printf("fail\n"); + return false; + } + + rt_rule->commit = 1; + rt_rule->num_rules = NUM_RULES; + rt_rule->ip = IPA_IP_v6; + strlcpy(rt_rule->rt_tbl_name, "LAN", sizeof(rt_rule->rt_tbl_name)); + + rt_rule_entry = &rt_rule->rules[0]; + rt_rule_entry->at_rear = 0; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST2_CONS; + // rt_rule_entry->rule.hdr_hdl = hdr_entry->hdr_hdl; // TODO: Header Insertion gidons, there is no support for header insertion / removal yet. + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v6.dst_addr[0] = 0X11020000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[1] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[2] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[3] = 0X0000000C; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[0] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[1] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[2] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[3] = 0x00000000; + + rt_rule_entry = &rt_rule->rules[1]; + rt_rule_entry->at_rear = 0; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST3_CONS; + // rt_rule_entry->rule.hdr_hdl = hdr_entry->hdr_hdl; // TODO: Header Insertion gidons, there is no support for header insertion / removal yet. + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v6.dst_addr[0] = 0X22020000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[1] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[2] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[3] = 0X0000000C; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[0] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[1] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[2] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[3] = 0x00000000; + + rt_rule_entry = &rt_rule->rules[2]; + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST4_CONS; + + if (false == m_routing.AddRoutingRule(rt_rule)) + { + printf("Routing rule addition failed!\n"); + return false; + } + + printf("rt rule hdl1=%x\n", rt_rule_entry->rt_rule_hdl); + + free(rt_rule); + + InitFilteringBlock(); + + return true; + } +}; + +/*---------------------------------------------------------------------------*/ +/* Test7: IPv6 - Tests routing by destination address */ +/*---------------------------------------------------------------------------*/ +class IpaRoutingBlockTest007 : public IpaRoutingBlockTestFixture +{ +public: + IpaRoutingBlockTest007() + { + m_name = "IpaRoutingBlockTest007"; + m_description = " \ + Routing block test 007 - IPv6 Exact Traffic Class Match \ + 1. Generate and commit a single routing tables. \ + 2. Generate and commit Three routing rules: (DST & Mask Match). \ + All Traffic Class == 0xAA traffic goes to pipe IPA_CLIENT_TEST2_CONS \ + All Traffic Class == 0xBB traffic goes to pipe IPA_CLIENT_TEST3_CONS\ + All other traffic goes to pipe IPA_CLIENT_TEST4_CONS"; + m_IpaIPType = IPA_IP_v6; + Register(*this); + } + + bool Run() + { + bool res = false; + bool isSuccess = false; + + // Add the relevant routing rules + res = AddRules(); + if (false == res) { + printf("Failed adding routing rules.\n"); + return false; + } + + // Load input data (IP packet) from file + res = LoadFiles(IPA_IP_v6); + if (false == res) { + printf("Failed loading files.\n"); + return false; + } + + // Send first packet + m_sendBuffer[TRAFFIC_CLASS_MSB_OFFSET_IPV6] &= 0xF0; + m_sendBuffer[TRAFFIC_CLASS_MSB_OFFSET_IPV6] |= 0x0A; + m_sendBuffer[TRAFFIC_CLASS_LSB_OFFSET_IPV6] &= 0x0F; + m_sendBuffer[TRAFFIC_CLASS_LSB_OFFSET_IPV6] |= 0xA0; + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send second packet + m_sendBuffer2[TRAFFIC_CLASS_MSB_OFFSET_IPV6] &= 0xF0; + m_sendBuffer2[TRAFFIC_CLASS_MSB_OFFSET_IPV6] |= 0x0B; + m_sendBuffer2[TRAFFIC_CLASS_LSB_OFFSET_IPV6] &= 0x0F; + m_sendBuffer2[TRAFFIC_CLASS_LSB_OFFSET_IPV6] |= 0xB0; + isSuccess = m_producer.SendData(m_sendBuffer2, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send third packet + isSuccess = m_producer.SendData(m_sendBuffer3, m_sendSize3); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Receive packets from the channels and compare results + isSuccess = ReceivePacketsAndCompare(); + + return isSuccess; + } // Run() + + bool AddRules() + { + struct ipa_ioc_add_rt_rule *rt_rule; + struct ipa_rt_rule_add *rt_rule_entry; + const int NUM_RULES = 3; + + rt_rule = (struct ipa_ioc_add_rt_rule *) + calloc(1, sizeof(struct ipa_ioc_add_rt_rule) + + NUM_RULES*sizeof(struct ipa_rt_rule_add)); + + if(!rt_rule) { + printf("fail\n"); + return false; + } + + rt_rule->commit = 1; + rt_rule->num_rules = NUM_RULES; + rt_rule->ip = IPA_IP_v6; + strlcpy(rt_rule->rt_tbl_name, "LAN", sizeof(rt_rule->rt_tbl_name)); + + rt_rule_entry = &rt_rule->rules[0]; + rt_rule_entry->at_rear = 0; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST2_CONS; + // rt_rule_entry->rule.hdr_hdl = hdr_entry->hdr_hdl; // TODO: Header Insertion gidons, there is no support for header insertion / removal yet. + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_TC; + rt_rule_entry->rule.attrib.u.v6.tc = 0xAA; + + rt_rule_entry = &rt_rule->rules[1]; + rt_rule_entry->at_rear = 0; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST3_CONS; +// rt_rule_entry->rule.hdr_hdl = hdr_entry->hdr_hdl; // TODO: Header Insertion gidons, there is no support for header insertion / removal yet. + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_TC; + rt_rule_entry->rule.attrib.u.v6.tc = 0xBB; + + rt_rule_entry = &rt_rule->rules[2]; + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST4_CONS; + + if (false == m_routing.AddRoutingRule(rt_rule)) + { + printf("Routing rule addition failed!\n"); + return false; + } + + printf("rt rule hdl1=%x\n", rt_rule_entry->rt_rule_hdl); + + free(rt_rule); + + InitFilteringBlock(); + + return true; + } +}; + +/*---------------------------------------------------------------------------*/ +/* Test8: IPv6 - Tests routing by destination address */ +/*---------------------------------------------------------------------------*/ +class IpaRoutingBlockTest008 : public IpaRoutingBlockTestFixture +{ +public: + IpaRoutingBlockTest008() + { + m_name = "IpaRoutingBlockTest008"; + m_description = " \ + Routing block test 008 - IPv6 Destination address exact match and Traffic Class Match \ + 1. Generate and commit a single routing tables. \ + 2. Generate and commit Three routing rules: (DST & Mask Match). \ + All Traffic Class == 0xAA & IPv6 DST Addr 0xFF020000...00AA traffic goes to pipe IPA_CLIENT_TEST2_CONS \ + All Traffic Class == 0xBB & IPv6 DST Addr 0xFF020000...00BB traffic goes to pipe IPA_CLIENT_TEST3_CONS\ + All other traffic goes to pipe IPA_CLIENT_TEST4_CONS"; + m_IpaIPType = IPA_IP_v6; + Register(*this); + } + + bool Run() + { + bool res = false; + bool isSuccess = false; + + // Add the relevant routing rules + res = AddRules(); + if (false == res) { + printf("Failed adding routing rules.\n"); + return false; + } + + // Load input data (IP packet) from file + res = LoadFiles(IPA_IP_v6); + if (false == res) { + printf("Failed loading files.\n"); + return false; + } + + // Send first packet + m_sendBuffer[TRAFFIC_CLASS_MSB_OFFSET_IPV6] &= 0xF0; + m_sendBuffer[TRAFFIC_CLASS_MSB_OFFSET_IPV6] |= 0x0A; + m_sendBuffer[TRAFFIC_CLASS_LSB_OFFSET_IPV6] &= 0x0F; + m_sendBuffer[TRAFFIC_CLASS_LSB_OFFSET_IPV6] |= 0xA0; + m_sendBuffer[DST_ADDR_LSB_OFFSET_IPV6] = 0xFF; + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send second packet + m_sendBuffer2[TRAFFIC_CLASS_MSB_OFFSET_IPV6] &= 0xF0; + m_sendBuffer2[TRAFFIC_CLASS_MSB_OFFSET_IPV6] |= 0x0B; + m_sendBuffer2[TRAFFIC_CLASS_LSB_OFFSET_IPV6] &= 0x0F; + m_sendBuffer2[TRAFFIC_CLASS_LSB_OFFSET_IPV6] |= 0xB0; + m_sendBuffer2[DST_ADDR_LSB_OFFSET_IPV6] = 0xAA; + isSuccess = m_producer.SendData(m_sendBuffer2, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send third packet + isSuccess = m_producer.SendData(m_sendBuffer3, m_sendSize3); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Receive packets from the channels and compare results + isSuccess = ReceivePacketsAndCompare(); + + return isSuccess; + } // Run() + + bool AddRules() + { + struct ipa_ioc_add_rt_rule *rt_rule; + struct ipa_rt_rule_add *rt_rule_entry; + const int NUM_RULES = 3; + + rt_rule = (struct ipa_ioc_add_rt_rule *) + calloc(1, sizeof(struct ipa_ioc_add_rt_rule) + + NUM_RULES*sizeof(struct ipa_rt_rule_add)); + + if(!rt_rule) { + printf("fail\n"); + return false; + } + + rt_rule->commit = 1; + rt_rule->num_rules = NUM_RULES; + rt_rule->ip = IPA_IP_v6; + strlcpy(rt_rule->rt_tbl_name, "LAN", sizeof(rt_rule->rt_tbl_name)); + + rt_rule_entry = &rt_rule->rules[0]; + rt_rule_entry->at_rear = 0; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST2_CONS; +// rt_rule_entry->rule.hdr_hdl = hdr_entry->hdr_hdl; // gidons, there is no support for header insertion / removal yet. + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR | IPA_FLT_TC; + rt_rule_entry->rule.attrib.u.v6.tc = 0xAA; + rt_rule_entry->rule.attrib.u.v6.dst_addr[0] = 0XFF020000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[1] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[2] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[3] = 0X000000FF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[0] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[1] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[2] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[3] = 0xFFFFFFFF; + + rt_rule_entry = &rt_rule->rules[1]; + rt_rule_entry->at_rear = 0; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST3_CONS; +// rt_rule_entry->rule.hdr_hdl = hdr_entry->hdr_hdl; // gidons, there is no support for header insertion / removal yet. + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR | IPA_FLT_TC; + rt_rule_entry->rule.attrib.u.v6.tc = 0xBB; + rt_rule_entry->rule.attrib.u.v6.dst_addr[0] = 0XFF020000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[1] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[2] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[3] = 0X000000AA; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[0] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[1] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[2] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[3] = 0xFFFFFFFF; + + rt_rule_entry = &rt_rule->rules[2]; + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST4_CONS; + + if (false == m_routing.AddRoutingRule(rt_rule)) + { + printf("Routing rule addition failed!\n"); + return false; + } + + printf("rt rule hdl1=%x\n", rt_rule_entry->rt_rule_hdl); + + free(rt_rule); + + InitFilteringBlock(); + + return true; + } +}; + +/*---------------------------------------------------------------------------*/ +/* Test9: IPv6 - Tests routing by destination address */ +/*---------------------------------------------------------------------------*/ +class IpaRoutingBlockTest009 : public IpaRoutingBlockTestFixture +{ +public: + IpaRoutingBlockTest009() + { + m_name = "IpaRoutingBlockTest009"; + m_description = " \ + Routing block test 009 - IPv6 Exact Flow Label Match \ + 1. Generate and commit a single routing tables. \ + 2. Generate and commit Three routing rules: (DST & Mask Match). \ + All Flow Label == 0xABCDE traffic goes to pipe IPA_CLIENT_TEST2_CONS \ + All Flow Label == 0x12345 traffic goes to pipe IPA_CLIENT_TEST3_CONS\ + All other traffic goes to pipe IPA_CLIENT_TEST4_CONS"; + m_IpaIPType = IPA_IP_v6; + Register(*this); + } + + bool Run() + { + bool res = false; + bool isSuccess = false; + + // Add the relevant routing rules + res = AddRules(); + if (false == res) { + printf("Failed adding routing rules.\n"); + return false; + } + + // Load input data (IP packet) from file + res = LoadFiles(IPA_IP_v6); + if (false == res) { + printf("Failed loading files.\n"); + return false; + } + + // Send first packet + m_sendBuffer[FLOW_CLASS_MSB_OFFSET_IPV6] &= 0xF0; + m_sendBuffer[FLOW_CLASS_MSB_OFFSET_IPV6] |= 0x0A; + m_sendBuffer[FLOW_CLASS_MB_OFFSET_IPV6] = 0xBC; + m_sendBuffer[FLOW_CLASS_LSB_OFFSET_IPV6] = 0xDE; + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send second packet + m_sendBuffer2[FLOW_CLASS_MSB_OFFSET_IPV6] &= 0xF0; + m_sendBuffer2[FLOW_CLASS_MSB_OFFSET_IPV6] |= 0x01; + m_sendBuffer2[FLOW_CLASS_MB_OFFSET_IPV6] = 0x23; + m_sendBuffer2[FLOW_CLASS_LSB_OFFSET_IPV6] = 0x45; + isSuccess = m_producer.SendData(m_sendBuffer2, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send third packet + isSuccess = m_producer.SendData(m_sendBuffer3, m_sendSize3); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Receive packets from the channels and compare results + isSuccess = ReceivePacketsAndCompare(); + + return isSuccess; + } // Run() + + bool AddRules() + { + struct ipa_ioc_add_rt_rule *rt_rule; + struct ipa_rt_rule_add *rt_rule_entry; + const int NUM_RULES = 3; + + rt_rule = (struct ipa_ioc_add_rt_rule *) + calloc(1, sizeof(struct ipa_ioc_add_rt_rule) + + NUM_RULES*sizeof(struct ipa_rt_rule_add)); + + if(!rt_rule) { + printf("fail\n"); + return false; + } + + rt_rule->commit = 1; + rt_rule->num_rules = NUM_RULES; + rt_rule->ip = IPA_IP_v6; + strlcpy(rt_rule->rt_tbl_name, "LAN", sizeof(rt_rule->rt_tbl_name)); + + rt_rule_entry = &rt_rule->rules[0]; + rt_rule_entry->at_rear = 0; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST2_CONS; +// rt_rule_entry->rule.hdr_hdl = hdr_entry->hdr_hdl; // gidons, there is no support for header insertion / removal yet. + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_FLOW_LABEL; + rt_rule_entry->rule.attrib.u.v6.flow_label = 0xABCDE; + + rt_rule_entry = &rt_rule->rules[1]; + rt_rule_entry->at_rear = 0; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST3_CONS; +// rt_rule_entry->rule.hdr_hdl = hdr_entry->hdr_hdl; // gidons, there is no support for header insertion / removal yet. + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_FLOW_LABEL; + rt_rule_entry->rule.attrib.u.v6.flow_label = 0x12345; + + rt_rule_entry = &rt_rule->rules[2]; + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST4_CONS; + + if (false == m_routing.AddRoutingRule(rt_rule)) + { + printf("Routing rule addition failed!\n"); + return false; + } + + printf("rt rule hdl1=%x\n", rt_rule_entry->rt_rule_hdl); + + free(rt_rule); + + InitFilteringBlock(); + + return true; + } +}; + +/*--------------------------------------------------------------------------*/ +/* Test10: IPv4 - Tests routing hashable vs non hashable priorities */ +/*--------------------------------------------------------------------------*/ +class IpaRoutingBlockTest010 : public IpaRoutingBlockTestFixture +{ +public: + + IpaRoutingBlockTest010() + { + m_name = "IpaRoutingBlockTest10"; + m_description =" \ + Routing block test 010 - Destination address exact match non hashable priority higher than hashable \ + both match the packet but only non hashable should hit\ + 2. Generate and commit Three routing rules: (DST & Mask Match). \ + All DST_IP == (192.168.2.170 & 255.255.255.255)traffic goes to pipe IPA_CLIENT_TEST2_CONS \ + All DST_IP == (192.168.2.170 & 255.255.255.255)traffic goes to pipe IPA_CLIENT_TEST3_CONS\ + All other traffic goes to pipe IPA_CLIENT_TEST4_CONS"; + m_IpaIPType = IPA_IP_v4; + m_minIPAHwType = IPA_HW_v3_0; + Register(*this); + } + + bool AddRules() + { + struct ipa_ioc_add_rt_rule *rt_rule; + struct ipa_rt_rule_add *rt_rule_entry; + const int NUM_RULES = 3; + + rt_rule = (struct ipa_ioc_add_rt_rule *) + calloc(1, sizeof(struct ipa_ioc_add_rt_rule) + + NUM_RULES*sizeof(struct ipa_rt_rule_add)); + + if(!rt_rule) { + printf("fail\n"); + return false; + } + + rt_rule->commit = 1; + rt_rule->num_rules = NUM_RULES; + rt_rule->ip = IPA_IP_v4; + strlcpy(rt_rule->rt_tbl_name, "LAN", sizeof(rt_rule->rt_tbl_name)); + + rt_rule_entry = &rt_rule->rules[0]; + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST2_CONS; + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v4.dst_addr = 0xC0A802AA; //192.168.02.170 + rt_rule_entry->rule.attrib.u.v4.dst_addr_mask = 0xFFFFFFFF; + rt_rule_entry->rule.hashable = 0; // non hashable + + rt_rule_entry = &rt_rule->rules[1]; + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST3_CONS; + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v4.dst_addr = 0xC0A802AA; //192.168.02.170 + rt_rule_entry->rule.attrib.u.v4.dst_addr_mask = 0xFFFFFFFF; + rt_rule_entry->rule.hashable = 1; // hashable + + rt_rule_entry = &rt_rule->rules[2]; + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST4_CONS; + + if (false == m_routing.AddRoutingRule(rt_rule)) + { + printf("Routing rule addition failed!\n"); + return false; + } + + printf("rt rule hdl1=%x\n", rt_rule_entry->rt_rule_hdl); + + free(rt_rule); + + InitFilteringBlock(); + + return true; + } + + bool Run() + { + bool res = false; + bool isSuccess = false; + + // Add the relevant routing rules + res = AddRules(); + if (false == res) { + printf("Failed adding routing rules.\n"); + return false; + } + + // Load input data (IP packet) from file + res = LoadFiles(IPA_IP_v4); + if (false == res) { + printf("Failed loading files.\n"); + return false; + } + + // Send first packet + m_sendBuffer[DST_ADDR_LSB_OFFSET_IPV4] = 0xAA; + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send second packet + m_sendBuffer2[DST_ADDR_LSB_OFFSET_IPV4] = 0xAA; + isSuccess = m_producer.SendData(m_sendBuffer2, m_sendSize2); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send third packet + isSuccess = m_producer.SendData(m_sendBuffer3, m_sendSize3); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Receive packets from the channels and compare results + isSuccess = ReceivePacketsAndCompare(); + + return isSuccess; + } // Run() + + bool ReceivePacketsAndCompare() + { + size_t receivedSize = 0; + size_t receivedSize2 = 0; + size_t receivedSize3 = 0; + bool isSuccess = true; + + // Receive results + Byte *rxBuff1 = new Byte[0x400]; + Byte *rxBuff2 = new Byte[0x400]; + Byte *rxBuff3 = new Byte[0x400]; + + if (NULL == rxBuff1 || NULL == rxBuff2 || NULL == rxBuff3) + { + printf("Memory allocation error.\n"); + return false; + } + + receivedSize = m_consumer.ReceiveData(rxBuff1, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize, m_consumer.m_fromChannelName.c_str()); + + receivedSize2 = m_consumer.ReceiveData(rxBuff2, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize2, m_consumer2.m_fromChannelName.c_str()); + + receivedSize3 = m_defaultConsumer.ReceiveData(rxBuff3, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize3, m_defaultConsumer.m_fromChannelName.c_str()); + + /* Compare results */ + isSuccess &= CompareResultVsGolden(m_sendBuffer, m_sendSize, rxBuff1, receivedSize); + isSuccess &= CompareResultVsGolden(m_sendBuffer2, m_sendSize2, rxBuff2, receivedSize2); + isSuccess &= CompareResultVsGolden(m_sendBuffer3, m_sendSize3, rxBuff3, receivedSize3); + + size_t recievedBufferSize = receivedSize * 3; + size_t sentBufferSize = m_sendSize * 3; + char *recievedBuffer = new char[recievedBufferSize]; + char *sentBuffer = new char[sentBufferSize]; + + memset(recievedBuffer, 0, recievedBufferSize); + memset(sentBuffer, 0, sentBufferSize); + + print_packets(receivedSize, m_sendSize, recievedBufferSize, sentBufferSize, rxBuff1, m_sendBuffer, recievedBuffer, sentBuffer); + print_packets(receivedSize2, m_sendSize2, recievedBufferSize, sentBufferSize, rxBuff2, m_sendBuffer2, recievedBuffer, sentBuffer); + print_packets(receivedSize3, m_sendSize3, recievedBufferSize, sentBufferSize, rxBuff3, m_sendBuffer3, recievedBuffer, sentBuffer); + + delete[] recievedBuffer; + delete[] sentBuffer; + + delete[] rxBuff1; + delete[] rxBuff2; + delete[] rxBuff3; + + return isSuccess; + } +}; + +/*--------------------------------------------------------------------------*/ +/* Test11: IPv4 - Tests routing hashable vs non hashable priorities */ +/*--------------------------------------------------------------------------*/ +class IpaRoutingBlockTest011 : public IpaRoutingBlockTestFixture +{ +public: + + IpaRoutingBlockTest011() + { + m_name = "IpaRoutingBlockTest011"; + m_description =" \ + Routing block test 011 - Destination address exact match hashable priority higher than non hashable \ + both match the packet but only hashable should hit, second packet should get cache hit\ + 2. Generate and commit Three routing rules: (DST & Mask Match). \ + All DST_IP == (192.168.2.170 & 255.255.255.255)traffic goes to pipe IPA_CLIENT_TEST2_CONS \ + All DST_IP == (192.168.2.170 & 255.255.255.255)traffic goes to pipe IPA_CLIENT_TEST3_CONS\ + All other traffic goes to pipe IPA_CLIENT_TEST4_CONS"; + m_IpaIPType = IPA_IP_v4; + m_minIPAHwType = IPA_HW_v3_0; + Register(*this); + } + + bool Setup() + { + return IpaRoutingBlockTestFixture:: Setup(true); + } + + bool AddRules() + { + struct ipa_ioc_add_rt_rule *rt_rule; + struct ipa_rt_rule_add *rt_rule_entry; + const int NUM_RULES = 3; + + rt_rule = (struct ipa_ioc_add_rt_rule *) + calloc(1, sizeof(struct ipa_ioc_add_rt_rule) + + NUM_RULES*sizeof(struct ipa_rt_rule_add)); + + if(!rt_rule) { + printf("fail\n"); + return false; + } + + rt_rule->commit = 1; + rt_rule->num_rules = NUM_RULES; + rt_rule->ip = IPA_IP_v4; + strlcpy(rt_rule->rt_tbl_name, "LAN", sizeof(rt_rule->rt_tbl_name)); + + rt_rule_entry = &rt_rule->rules[0]; + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST2_CONS; + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v4.dst_addr = 0xC0A802AA; //192.168.02.170 + rt_rule_entry->rule.attrib.u.v4.dst_addr_mask = 0xFFFFFFFF; + rt_rule_entry->rule.hashable = 1; // hashable + + rt_rule_entry = &rt_rule->rules[1]; + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST3_CONS; + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v4.dst_addr = 0xC0A802AA; //192.168.02.170 + rt_rule_entry->rule.attrib.u.v4.dst_addr_mask = 0xFFFFFFFF; + rt_rule_entry->rule.hashable = 0; // non hashable + + rt_rule_entry = &rt_rule->rules[2]; + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST4_CONS; + + if (false == m_routing.AddRoutingRule(rt_rule)) + { + printf("Routing rule addition failed!\n"); + return false; + } + + printf("rt rule hdl1=%x\n", rt_rule_entry->rt_rule_hdl); + + free(rt_rule); + + InitFilteringBlock(); + + return true; + } + + bool Run() + { + bool res = false; + bool isSuccess = false; + + // Add the relevant routing rules + res = AddRules(); + if (false == res) { + printf("Failed adding routing rules.\n"); + return false; + } + + // Load input data (IP packet) from file + res = LoadFiles(IPA_IP_v4); + if (false == res) { + printf("Failed loading files.\n"); + return false; + } + + // Send first packet + m_sendBuffer[DST_ADDR_LSB_OFFSET_IPV4] = 0xAA; + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send second packet + m_sendBuffer2[DST_ADDR_LSB_OFFSET_IPV4] = 0xAA; + isSuccess = m_producer.SendData(m_sendBuffer2, m_sendSize2); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send third packet + isSuccess = m_producer.SendData(m_sendBuffer3, m_sendSize3); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Receive packets from the channels and compare results + isSuccess = ReceivePacketsAndCompare(); + + return isSuccess; + } // Run() + + bool ReceivePacketsAndCompare() + { + size_t receivedSize = 0; + size_t receivedSize2 = 0; + size_t receivedSize3 = 0; + bool isSuccess = true; + + // Receive results + Byte *rxBuff1 = new Byte[0x400]; + Byte *rxBuff2 = new Byte[0x400]; + Byte *rxBuff3 = new Byte[0x400]; + + if (NULL == rxBuff1 || NULL == rxBuff2 || NULL == rxBuff3) + { + printf("Memory allocation error.\n"); + return false; + } + + receivedSize = m_consumer.ReceiveData(rxBuff1, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize, m_consumer.m_fromChannelName.c_str()); + + receivedSize2 = m_consumer.ReceiveData(rxBuff2, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize2, m_consumer2.m_fromChannelName.c_str()); + + receivedSize3 = m_defaultConsumer.ReceiveData(rxBuff3, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize3, m_defaultConsumer.m_fromChannelName.c_str()); + + /* Compare results */ + isSuccess &= CompareResultVsGolden_w_Status(m_sendBuffer, m_sendSize, rxBuff1, receivedSize); + isSuccess &= CompareResultVsGolden_w_Status(m_sendBuffer2, m_sendSize2, rxBuff2, receivedSize2); + isSuccess &= CompareResultVsGolden_w_Status(m_sendBuffer3, m_sendSize3, rxBuff3, receivedSize3); + + isSuccess &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_0) ? + IsCacheMiss_v5_0(m_sendSize, receivedSize, rxBuff1) : IsCacheMiss(m_sendSize,receivedSize,rxBuff1); + isSuccess &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_0) ? + IsCacheHit_v5_0(m_sendSize2, receivedSize2, rxBuff2) : IsCacheHit(m_sendSize2,receivedSize2,rxBuff2); + isSuccess &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_0) ? + IsCacheMiss_v5_0(m_sendSize3, receivedSize3, rxBuff3) : IsCacheMiss(m_sendSize3,receivedSize3,rxBuff3); + + size_t recievedBufferSize = receivedSize * 3; + size_t sentBufferSize = m_sendSize * 3; + char *recievedBuffer = new char[recievedBufferSize]; + char *sentBuffer = new char[sentBufferSize]; + + memset(recievedBuffer, 0, recievedBufferSize); + memset(sentBuffer, 0, sentBufferSize); + + print_packets(receivedSize, m_sendSize, recievedBufferSize, sentBufferSize, rxBuff1, m_sendBuffer, recievedBuffer, sentBuffer); + print_packets(receivedSize2, m_sendSize2, recievedBufferSize, sentBufferSize, rxBuff2, m_sendBuffer2, recievedBuffer, sentBuffer); + print_packets(receivedSize3, m_sendSize3, recievedBufferSize, sentBufferSize, rxBuff3, m_sendBuffer3, recievedBuffer, sentBuffer); + + delete[] recievedBuffer; + delete[] sentBuffer; + + delete[] rxBuff1; + delete[] rxBuff2; + delete[] rxBuff3; + + return isSuccess; + } +}; + +/*--------------------------------------------------------------------------*/ +/* Test12: IPv4 - Tests routing hashable vs non hashable priorities */ +/*--------------------------------------------------------------------------*/ +class IpaRoutingBlockTest012 : public IpaRoutingBlockTestFixture +{ +public: + + IpaRoutingBlockTest012() + { + m_name = "IpaRoutingBlockTest012"; + m_description =" \ + Routing block test 012 - Destination address exact match hashable priority lower than non hashable \ + no match on non hashable rule (with higher priority), match on hashable rule. two packets with\ + different tuple are sent (but match the rule) cache miss expected\ + 2. Generate and commit Three routing rules: (DST & Mask Match). \ + All DST_IP == (192.168.2.170 & 255.255.255.255)traffic goes to pipe IPA_CLIENT_TEST2_CONS \ + All DST_IP == (192.168.2.171 & 255.255.255.255)traffic goes to pipe IPA_CLIENT_TEST3_CONS\ + All other traffic goes to pipe IPA_CLIENT_TEST4_CONS"; + m_IpaIPType = IPA_IP_v4; + m_minIPAHwType = IPA_HW_v3_0; + Register(*this); + } + + bool Setup() + { + return IpaRoutingBlockTestFixture:: Setup(true); + } + + bool AddRules() + { + struct ipa_ioc_add_rt_rule *rt_rule; + struct ipa_rt_rule_add *rt_rule_entry; + const int NUM_RULES = 3; + + rt_rule = (struct ipa_ioc_add_rt_rule *) + calloc(1, sizeof(struct ipa_ioc_add_rt_rule) + + NUM_RULES*sizeof(struct ipa_rt_rule_add)); + + if(!rt_rule) { + printf("fail\n"); + return false; + } + + rt_rule->commit = 1; + rt_rule->num_rules = NUM_RULES; + rt_rule->ip = IPA_IP_v4; + strlcpy(rt_rule->rt_tbl_name, "LAN", sizeof(rt_rule->rt_tbl_name)); + + rt_rule_entry = &rt_rule->rules[0]; + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST2_CONS; + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v4.dst_addr = 0xC0A802AB; //192.168.02.171 + rt_rule_entry->rule.attrib.u.v4.dst_addr_mask = 0xFFFFFFFF; + rt_rule_entry->rule.hashable = 0; // non hashable + + rt_rule_entry = &rt_rule->rules[1]; + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST3_CONS; + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v4.dst_addr = 0xC0A802AA; //192.168.02.170 + rt_rule_entry->rule.attrib.u.v4.dst_addr_mask = 0xFFFFFFFF; + rt_rule_entry->rule.hashable = 1; // hashable + + rt_rule_entry = &rt_rule->rules[2]; + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST4_CONS; + + if (false == m_routing.AddRoutingRule(rt_rule)) + { + printf("Routing rule addition failed!\n"); + return false; + } + + printf("rt rule hdl1=%x\n", rt_rule_entry->rt_rule_hdl); + + free(rt_rule); + + InitFilteringBlock(); + + return true; + } + + bool Run() + { + bool res = false; + bool isSuccess = false; + unsigned short port; + + // Add the relevant routing rules + res = AddRules(); + if (false == res) { + printf("Failed adding routing rules.\n"); + return false; + } + + // Load input data (IP packet) from file + res = LoadFiles(IPA_IP_v4); + if (false == res) { + printf("Failed loading files.\n"); + return false; + } + + // Send first packet + m_sendBuffer[DST_ADDR_LSB_OFFSET_IPV4] = 0xAA; + port = ntohs(547);//DHCP Client Port + memcpy (&m_sendBuffer[IPV4_DST_PORT_OFFSET], &port, sizeof(port)); + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send second packet + m_sendBuffer2[DST_ADDR_LSB_OFFSET_IPV4] = 0xAA; + port = ntohs(546);//DHCP Client Port + memcpy (&m_sendBuffer2[IPV4_DST_PORT_OFFSET], &port, sizeof(port)); + isSuccess = m_producer.SendData(m_sendBuffer2, m_sendSize2); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send third packet + isSuccess = m_producer.SendData(m_sendBuffer3, m_sendSize3); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Receive packets from the channels and compare results + isSuccess = ReceivePacketsAndCompare(); + + return isSuccess; + } // Run() + + bool ReceivePacketsAndCompare() + { + size_t receivedSize = 0; + size_t receivedSize2 = 0; + size_t receivedSize3 = 0; + bool isSuccess = true; + + // Receive results + Byte *rxBuff1 = new Byte[0x400]; + Byte *rxBuff2 = new Byte[0x400]; + Byte *rxBuff3 = new Byte[0x400]; + + if (NULL == rxBuff1 || NULL == rxBuff2 || NULL == rxBuff3) + { + printf("Memory allocation error.\n"); + return false; + } + + receivedSize = m_consumer2.ReceiveData(rxBuff1, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize, m_consumer2.m_fromChannelName.c_str()); + + receivedSize2 = m_consumer2.ReceiveData(rxBuff2, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize2, m_consumer2.m_fromChannelName.c_str()); + + receivedSize3 = m_defaultConsumer.ReceiveData(rxBuff3, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize3, m_defaultConsumer.m_fromChannelName.c_str()); + + /* Compare results */ + isSuccess &= CompareResultVsGolden_w_Status(m_sendBuffer, m_sendSize, rxBuff1, receivedSize); + isSuccess &= CompareResultVsGolden_w_Status(m_sendBuffer2, m_sendSize2, rxBuff2, receivedSize2); + isSuccess &= CompareResultVsGolden_w_Status(m_sendBuffer3, m_sendSize3, rxBuff3, receivedSize3); + + isSuccess &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_0) ? + IsCacheMiss_v5_0(m_sendSize, receivedSize, rxBuff1) : IsCacheMiss(m_sendSize,receivedSize,rxBuff1); + isSuccess &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_0) ? + IsCacheMiss_v5_0(m_sendSize2, receivedSize2, rxBuff2) : IsCacheMiss(m_sendSize2,receivedSize2,rxBuff2); + isSuccess &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_0) ? + IsCacheMiss_v5_0(m_sendSize3, receivedSize3, rxBuff3) : IsCacheMiss(m_sendSize3,receivedSize3,rxBuff3); + + size_t recievedBufferSize = receivedSize * 3; + size_t sentBufferSize = m_sendSize * 3; + char *recievedBuffer = new char[recievedBufferSize]; + char *sentBuffer = new char[sentBufferSize]; + + memset(recievedBuffer, 0, recievedBufferSize); + memset(sentBuffer, 0, sentBufferSize); + + print_packets(receivedSize, m_sendSize, recievedBufferSize, sentBufferSize, rxBuff1, m_sendBuffer, recievedBuffer, sentBuffer); + print_packets(receivedSize2, m_sendSize2, recievedBufferSize, sentBufferSize, rxBuff2, m_sendBuffer2, recievedBuffer, sentBuffer); + print_packets(receivedSize3, m_sendSize3, recievedBufferSize, sentBufferSize, rxBuff3, m_sendBuffer3, recievedBuffer, sentBuffer); + + delete[] recievedBuffer; + delete[] sentBuffer; + + delete[] rxBuff1; + delete[] rxBuff2; + delete[] rxBuff3; + + return isSuccess; + } + +}; + +/*--------------------------------------------------------------------------*/ +/* Test13: IPv4 - Tests routing hashable vs non hashable priorities */ +/*--------------------------------------------------------------------------*/ +class IpaRoutingBlockTest013 : public IpaRoutingBlockTestFixture +{ +public: + + IpaRoutingBlockTest013() + { + m_name = "IpaRoutingBlockTest013"; + m_description =" \ + Routing block test 013 - Destination address exact match \ + no match on non hashable rule (with lower priority), match on hashable rule. two packets with\ + different tuple are sent (but match the rule) cache miss expected\ + 2. Generate and commit Three routing rules: (DST & Mask Match). \ + All DST_IP == (192.168.2.170 & 255.255.255.255)traffic goes to pipe IPA_CLIENT_TEST2_CONS \ + All DST_IP == (192.168.2.171 & 255.255.255.255)traffic goes to pipe IPA_CLIENT_TEST3_CONS\ + All other traffic goes to pipe IPA_CLIENT_TEST4_CONS"; + m_IpaIPType = IPA_IP_v4; + m_minIPAHwType = IPA_HW_v3_0; + Register(*this); + } + + bool Setup() + { + return IpaRoutingBlockTestFixture:: Setup(true); + } + + bool AddRules() + { + struct ipa_ioc_add_rt_rule *rt_rule; + struct ipa_rt_rule_add *rt_rule_entry; + const int NUM_RULES = 3; + + rt_rule = (struct ipa_ioc_add_rt_rule *) + calloc(1, sizeof(struct ipa_ioc_add_rt_rule) + + NUM_RULES*sizeof(struct ipa_rt_rule_add)); + + if(!rt_rule) { + printf("fail\n"); + return false; + } + + rt_rule->commit = 1; + rt_rule->num_rules = NUM_RULES; + rt_rule->ip = IPA_IP_v4; + strlcpy(rt_rule->rt_tbl_name, "LAN", sizeof(rt_rule->rt_tbl_name)); + + rt_rule_entry = &rt_rule->rules[0]; + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST2_CONS; + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v4.dst_addr = 0xC0A802AA; //192.168.02.170 + rt_rule_entry->rule.attrib.u.v4.dst_addr_mask = 0xFFFFFFFF; + rt_rule_entry->rule.hashable = 1; // hashable + + rt_rule_entry = &rt_rule->rules[1]; + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST3_CONS; + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v4.dst_addr = 0xC0A802AB; //192.168.02.171 + rt_rule_entry->rule.attrib.u.v4.dst_addr_mask = 0xFFFFFFFF; + rt_rule_entry->rule.hashable = 0; // non hashable + + rt_rule_entry = &rt_rule->rules[2]; + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST4_CONS; + + if (false == m_routing.AddRoutingRule(rt_rule)) + { + printf("Routing rule addition failed!\n"); + return false; + } + + printf("rt rule hdl1=%x\n", rt_rule_entry->rt_rule_hdl); + + free(rt_rule); + + InitFilteringBlock(); + + return true; + } + + bool Run() + { + bool res = false; + bool isSuccess = false; + unsigned short port; + + // Add the relevant routing rules + res = AddRules(); + if (false == res) { + printf("Failed adding routing rules.\n"); + return false; + } + + // Load input data (IP packet) from file + res = LoadFiles(IPA_IP_v4); + if (false == res) { + printf("Failed loading files.\n"); + return false; + } + + // Send first packet + m_sendBuffer[DST_ADDR_LSB_OFFSET_IPV4] = 0xAA; + port = ntohs(547);//DHCP Client Port + memcpy (&m_sendBuffer[IPV4_DST_PORT_OFFSET], &port, sizeof(port)); + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send second packet + m_sendBuffer2[DST_ADDR_LSB_OFFSET_IPV4] = 0xAA; + port = ntohs(546);//DHCP Client Port + memcpy (&m_sendBuffer2[IPV4_DST_PORT_OFFSET], &port, sizeof(port)); + isSuccess = m_producer.SendData(m_sendBuffer2, m_sendSize2); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send third packet + isSuccess = m_producer.SendData(m_sendBuffer3, m_sendSize3); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Receive packets from the channels and compare results + isSuccess = ReceivePacketsAndCompare(); + + return isSuccess; + } // Run() + + bool ReceivePacketsAndCompare() + { + size_t receivedSize = 0; + size_t receivedSize2 = 0; + size_t receivedSize3 = 0; + bool isSuccess = true; + + // Receive results + Byte *rxBuff1 = new Byte[0x400]; + Byte *rxBuff2 = new Byte[0x400]; + Byte *rxBuff3 = new Byte[0x400]; + + if (NULL == rxBuff1 || NULL == rxBuff2 || NULL == rxBuff3) + { + printf("Memory allocation error.\n"); + return false; + } + + receivedSize = m_consumer.ReceiveData(rxBuff1, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize, m_consumer.m_fromChannelName.c_str()); + + receivedSize2 = m_consumer.ReceiveData(rxBuff2, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize2, m_consumer.m_fromChannelName.c_str()); + + receivedSize3 = m_defaultConsumer.ReceiveData(rxBuff3, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize3, m_defaultConsumer.m_fromChannelName.c_str()); + + /* Compare results */ + isSuccess &= CompareResultVsGolden_w_Status(m_sendBuffer, m_sendSize, rxBuff1, receivedSize); + isSuccess &= CompareResultVsGolden_w_Status(m_sendBuffer2, m_sendSize2, rxBuff2, receivedSize2); + isSuccess &= CompareResultVsGolden_w_Status(m_sendBuffer3, m_sendSize3, rxBuff3, receivedSize3); + + isSuccess &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_0) ? + IsCacheMiss_v5_0(m_sendSize, receivedSize, rxBuff1) : IsCacheMiss(m_sendSize,receivedSize,rxBuff1); + isSuccess &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_0) ? + IsCacheMiss_v5_0(m_sendSize2, receivedSize2, rxBuff2) : IsCacheMiss(m_sendSize2,receivedSize2,rxBuff2); + isSuccess &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_0) ? + IsCacheMiss_v5_0(m_sendSize3, receivedSize3, rxBuff3) : IsCacheMiss(m_sendSize3,receivedSize3,rxBuff3); + + size_t recievedBufferSize = receivedSize * 3; + size_t sentBufferSize = m_sendSize * 3; + char *recievedBuffer = new char[recievedBufferSize]; + char *sentBuffer = new char[sentBufferSize]; + + memset(recievedBuffer, 0, recievedBufferSize); + memset(sentBuffer, 0, sentBufferSize); + + print_packets(receivedSize, m_sendSize, recievedBufferSize, sentBufferSize, rxBuff1, m_sendBuffer, recievedBuffer, sentBuffer); + print_packets(receivedSize2, m_sendSize2, recievedBufferSize, sentBufferSize, rxBuff2, m_sendBuffer2, recievedBuffer, sentBuffer); + print_packets(receivedSize3, m_sendSize3, recievedBufferSize, sentBufferSize, rxBuff3, m_sendBuffer3, recievedBuffer, sentBuffer); + + delete[] recievedBuffer; + delete[] sentBuffer; + + delete[] rxBuff1; + delete[] rxBuff2; + delete[] rxBuff3; + + return isSuccess; + } + +}; + +/*--------------------------------------------------------------------------*/ +/* Test14: IPv4 - Tests routing hashable vs non hashable priorities */ +/*--------------------------------------------------------------------------*/ +class IpaRoutingBlockTest014 : public IpaRoutingBlockTestFixture +{ +public: + + IpaRoutingBlockTest014() + { + m_name = "IpaRoutingBlockTest014"; + m_description =" \ + Routing block test 014 - Destination address exact match \ + no match on non hashable rule(with higher priority) , match on hashable rule. two identical\ + packets are sent cache hit expected on the second one\ + 2. Generate and commit Three routing rules: (DST & Mask Match). \ + All DST_IP == (192.168.2.171 & 255.255.255.255)traffic goes to pipe IPA_CLIENT_TEST2_CONS \ + All DST_IP == (192.168.2.170 & 255.255.255.255)traffic goes to pipe IPA_CLIENT_TEST3_CONS\ + All other traffic goes to pipe IPA_CLIENT_TEST4_CONS"; + m_IpaIPType = IPA_IP_v4; + m_minIPAHwType = IPA_HW_v3_0; + Register(*this); + } + + bool Setup() + { + return IpaRoutingBlockTestFixture:: Setup(true); + } + + bool AddRules() + { + struct ipa_ioc_add_rt_rule *rt_rule; + struct ipa_rt_rule_add *rt_rule_entry; + const int NUM_RULES = 3; + + rt_rule = (struct ipa_ioc_add_rt_rule *) + calloc(1, sizeof(struct ipa_ioc_add_rt_rule) + + NUM_RULES*sizeof(struct ipa_rt_rule_add)); + + if(!rt_rule) { + printf("Failed memory allocation for rt_rule\n"); + return false; + } + + rt_rule->commit = 1; + rt_rule->num_rules = NUM_RULES; + rt_rule->ip = IPA_IP_v4; + strlcpy(rt_rule->rt_tbl_name, "LAN", sizeof(rt_rule->rt_tbl_name)); + + rt_rule_entry = &rt_rule->rules[0]; + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST2_CONS; + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v4.dst_addr = 0xC0A802AB; //192.168.02.171 + rt_rule_entry->rule.attrib.u.v4.dst_addr_mask = 0xFFFFFFFF; + rt_rule_entry->rule.hashable = 0; // non hashable + + rt_rule_entry = &rt_rule->rules[1]; + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST3_CONS; + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v4.dst_addr = 0xC0A802AA; //192.168.02.170 + rt_rule_entry->rule.attrib.u.v4.dst_addr_mask = 0xFFFFFFFF; + rt_rule_entry->rule.hashable = 1; // hashable + + rt_rule_entry = &rt_rule->rules[2]; + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST4_CONS; + + if (false == m_routing.AddRoutingRule(rt_rule)) + { + printf("Routing rule addition failed!\n"); + free(rt_rule); + return false; + } + + printf("rt rule hdl1=%x\n", rt_rule_entry->rt_rule_hdl); + + free(rt_rule); + + InitFilteringBlock(); + + return true; + } + + bool Run() + { + bool res = false; + bool isSuccess = false; + + // Add the relevant routing rules + res = AddRules(); + if (false == res) { + printf("Failed adding routing rules.\n"); + return false; + } + + // Load input data (IP packet) from file + res = LoadFiles(IPA_IP_v4); + if (false == res) { + printf("Failed loading files.\n"); + return false; + } + + // Send first packet + m_sendBuffer[DST_ADDR_LSB_OFFSET_IPV4] = 0xAA; + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send second packet + m_sendBuffer2[DST_ADDR_LSB_OFFSET_IPV4] = 0xAA; + isSuccess = m_producer.SendData(m_sendBuffer2, m_sendSize2); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send third packet + isSuccess = m_producer.SendData(m_sendBuffer3, m_sendSize3); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Receive packets from the channels and compare results + isSuccess = ReceivePacketsAndCompare(); + + return isSuccess; + } // Run() + + bool ReceivePacketsAndCompare() + { + size_t receivedSize = 0; + size_t receivedSize2 = 0; + size_t receivedSize3 = 0; + bool isSuccess = true; + + // Receive results + Byte *rxBuff1 = new Byte[0x400]; + Byte *rxBuff2 = new Byte[0x400]; + Byte *rxBuff3 = new Byte[0x400]; + + if (NULL == rxBuff1 || NULL == rxBuff2 || NULL == rxBuff3) + { + printf("Memory allocation error.\n"); + return false; + } + + receivedSize = m_consumer2.ReceiveData(rxBuff1, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize, m_consumer2.m_fromChannelName.c_str()); + + receivedSize2 = m_consumer2.ReceiveData(rxBuff2, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize2, m_consumer2.m_fromChannelName.c_str()); + + receivedSize3 = m_defaultConsumer.ReceiveData(rxBuff3, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize3, m_defaultConsumer.m_fromChannelName.c_str()); + + /* Compare results */ + isSuccess &= CompareResultVsGolden_w_Status(m_sendBuffer, m_sendSize, rxBuff1, receivedSize); + isSuccess &= CompareResultVsGolden_w_Status(m_sendBuffer2, m_sendSize2, rxBuff2, receivedSize2); + isSuccess &= CompareResultVsGolden_w_Status(m_sendBuffer3, m_sendSize3, rxBuff3, receivedSize3); + + isSuccess &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_0) ? + IsCacheMiss_v5_0(m_sendSize, receivedSize, rxBuff1) : IsCacheMiss(m_sendSize,receivedSize,rxBuff1); + isSuccess &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_0) ? + IsCacheHit_v5_0(m_sendSize2, receivedSize2, rxBuff2) : IsCacheHit(m_sendSize2,receivedSize2,rxBuff2); + isSuccess &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_0) ? + IsCacheMiss_v5_0(m_sendSize3, receivedSize3, rxBuff3) : IsCacheMiss(m_sendSize3,receivedSize3,rxBuff3); + + size_t recievedBufferSize = receivedSize * 3; + size_t sentBufferSize = m_sendSize * 3; + char *recievedBuffer = new char[recievedBufferSize]; + char *sentBuffer = new char[sentBufferSize]; + + memset(recievedBuffer, 0, recievedBufferSize); + memset(sentBuffer, 0, sentBufferSize); + + print_packets(receivedSize, m_sendSize, recievedBufferSize, sentBufferSize, rxBuff1, m_sendBuffer, recievedBuffer, sentBuffer); + print_packets(receivedSize2, m_sendSize2, recievedBufferSize, sentBufferSize, rxBuff2, m_sendBuffer2, recievedBuffer, sentBuffer); + print_packets(receivedSize3, m_sendSize3, recievedBufferSize, sentBufferSize, rxBuff3, m_sendBuffer3, recievedBuffer, sentBuffer); + + delete[] recievedBuffer; + delete[] sentBuffer; + + delete[] rxBuff1; + delete[] rxBuff2; + delete[] rxBuff3; + + return isSuccess; + } +}; + + +/*--------------------------------------------------------------------------*/ +/* Test15: IPv4 - Tests routing hashable vs non hashable priorities */ +/*--------------------------------------------------------------------------*/ +class IpaRoutingBlockTest015 : public IpaRoutingBlockTestFixture +{ +public: + + IpaRoutingBlockTest015() + { + m_name = "IpaRoutingBlockTest015"; + m_description =" \ + Routing block test 015 - Destination address exact match \ + no match on non hashable rule(with lower priority) , match on hashable rule. two identical\ + packets are sent cache hit expected on the second one\ + 2. Generate and commit Three routing rules: (DST & Mask Match). \ + All DST_IP == (192.168.2.170 & 255.255.255.255)traffic goes to pipe IPA_CLIENT_TEST2_CONS \ + All DST_IP == (192.168.2.171 & 255.255.255.255)traffic goes to pipe IPA_CLIENT_TEST3_CONS\ + All other traffic goes to pipe IPA_CLIENT_TEST4_CONS"; + m_IpaIPType = IPA_IP_v4; + m_minIPAHwType = IPA_HW_v3_0; + Register(*this); + } + + bool Setup() + { + return IpaRoutingBlockTestFixture:: Setup(true); + } + + bool AddRules() + { + struct ipa_ioc_add_rt_rule *rt_rule; + struct ipa_rt_rule_add *rt_rule_entry; + const int NUM_RULES = 3; + + rt_rule = (struct ipa_ioc_add_rt_rule *) + calloc(1, sizeof(struct ipa_ioc_add_rt_rule) + + NUM_RULES*sizeof(struct ipa_rt_rule_add)); + + if(!rt_rule) { + printf("Failed memory allocation for rt_rule\n"); + return false; + } + + rt_rule->commit = 1; + rt_rule->num_rules = NUM_RULES; + rt_rule->ip = IPA_IP_v4; + strlcpy(rt_rule->rt_tbl_name, "LAN", sizeof(rt_rule->rt_tbl_name)); + + rt_rule_entry = &rt_rule->rules[0]; + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST2_CONS; + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v4.dst_addr = 0xC0A802AA; //192.168.02.170 + rt_rule_entry->rule.attrib.u.v4.dst_addr_mask = 0xFFFFFFFF; + rt_rule_entry->rule.hashable = 1; // hashable + + rt_rule_entry = &rt_rule->rules[1]; + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST3_CONS; + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v4.dst_addr = 0xC0A802AB; //192.168.02.171 + rt_rule_entry->rule.attrib.u.v4.dst_addr_mask = 0xFFFFFFFF; + rt_rule_entry->rule.hashable = 0; // non hashable + + rt_rule_entry = &rt_rule->rules[2]; + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST4_CONS; + + if (false == m_routing.AddRoutingRule(rt_rule)) + { + printf("Routing rule addition failed!\n"); + return false; + } + + for (int i = 0; i < rt_rule->num_rules; i++) { + uRtRuleHdl[i] = rt_rule->rules[i].rt_rule_hdl; + } + uNumRtRules = rt_rule->num_rules; + + printf("rt rule hdl1=%x\n", rt_rule_entry->rt_rule_hdl); + + free(rt_rule); + + InitFilteringBlock(); + + return true; + } + + bool RemoveLastRule(enum ipa_ip_type ipType) + { + struct ipa_ioc_del_rt_rule *ruleTable; + + ruleTable = (struct ipa_ioc_del_rt_rule *) + calloc(1, sizeof(struct ipa_ioc_del_rt_rule) + + sizeof(struct ipa_rt_rule_del)); + + ruleTable->commit = 1; + ruleTable->ip = ipType; + ruleTable->num_hdls = 1; + ruleTable->hdl[0].hdl = uRtRuleHdl[uNumRtRules - 1]; + ruleTable->hdl[0].status = 0; + + if (false == m_routing.DeleteRoutingRule(ruleTable)) + { + printf("Routing rule deletion failed!\n"); + return false; + } + + return true; + } + + bool Run() + { + bool res = false; + bool isSuccess = false; + + // Add the relevant routing rules + res = AddRules(); + if (false == res) { + printf("Failed adding routing rules.\n"); + return false; + } + + // Load input data (IP packet) from file + res = LoadFiles(IPA_IP_v4); + if (false == res) { + printf("Failed loading files.\n"); + return false; + } + + // Send first packet + m_sendBuffer[DST_ADDR_LSB_OFFSET_IPV4] = 0xAA; + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send second packet + m_sendBuffer2[DST_ADDR_LSB_OFFSET_IPV4] = 0xAA; + isSuccess = m_producer.SendData(m_sendBuffer2, m_sendSize2); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send third packet + isSuccess = m_producer.SendData(m_sendBuffer3, m_sendSize3); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Receive packets from the channels and compare results + isSuccess = ReceivePacketsAndCompare(); + + return isSuccess; + } // Run() + + bool ReceivePacketsAndCompare() + { + size_t receivedSize = 0; + size_t receivedSize2 = 0; + size_t receivedSize3 = 0; + bool isSuccess = true; + + // Receive results + Byte *rxBuff1 = new Byte[0x400]; + Byte *rxBuff2 = new Byte[0x400]; + Byte *rxBuff3 = new Byte[0x400]; + + if (NULL == rxBuff1 || NULL == rxBuff2 || NULL == rxBuff3) + { + printf("Memory allocation error.\n"); + return false; + } + + receivedSize = m_consumer.ReceiveData(rxBuff1, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize, m_consumer.m_fromChannelName.c_str()); + + receivedSize2 = m_consumer.ReceiveData(rxBuff2, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize2, m_consumer.m_fromChannelName.c_str()); + + receivedSize3 = m_defaultConsumer.ReceiveData(rxBuff3, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize3, m_defaultConsumer.m_fromChannelName.c_str()); + + /* Compare results */ + isSuccess &= CompareResultVsGolden_w_Status(m_sendBuffer, m_sendSize, rxBuff1, receivedSize); + isSuccess &= CompareResultVsGolden_w_Status(m_sendBuffer2, m_sendSize2, rxBuff2, receivedSize2); + isSuccess &= CompareResultVsGolden_w_Status(m_sendBuffer3, m_sendSize3, rxBuff3, receivedSize3); + + isSuccess &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_0) ? + IsCacheMiss_v5_0(m_sendSize, receivedSize, rxBuff1) : IsCacheMiss(m_sendSize,receivedSize,rxBuff1); + isSuccess &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_0) ? + IsCacheHit_v5_0(m_sendSize2, receivedSize2, rxBuff2) : IsCacheHit(m_sendSize2,receivedSize2,rxBuff2); + isSuccess &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_0) ? + IsCacheMiss_v5_0(m_sendSize3, receivedSize3, rxBuff3) : IsCacheMiss(m_sendSize3,receivedSize3,rxBuff3); + + size_t recievedBufferSize = receivedSize * 3; + size_t sentBufferSize = m_sendSize * 3; + char *recievedBuffer = new char[recievedBufferSize]; + char *sentBuffer = new char[sentBufferSize]; + + memset(recievedBuffer, 0, recievedBufferSize); + memset(sentBuffer, 0, sentBufferSize); + + print_packets(receivedSize, m_sendSize, recievedBufferSize, sentBufferSize, rxBuff1, m_sendBuffer, recievedBuffer, sentBuffer); + print_packets(receivedSize2, m_sendSize2, recievedBufferSize, sentBufferSize, rxBuff2, m_sendBuffer2, recievedBuffer, sentBuffer); + print_packets(receivedSize3, m_sendSize3, recievedBufferSize, sentBufferSize, rxBuff3, m_sendBuffer3, recievedBuffer, sentBuffer); + + delete[] recievedBuffer; + delete[] sentBuffer; + + delete[] rxBuff1; + delete[] rxBuff2; + delete[] rxBuff3; + + return isSuccess; + } + + bool ReceivePacketsAndCompareSpecial() + { + size_t receivedSize = 0; + bool isSuccess = true; + + // Receive results + Byte *rxBuff1 = new Byte[0x400]; + + if (NULL == rxBuff1) + { + printf("Memory allocation error.\n"); + return false; + } + + receivedSize = m_consumer.ReceiveData(rxBuff1, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize, m_consumer.m_fromChannelName.c_str()); + + /* Compare results */ + isSuccess &= CompareResultVsGolden_w_Status(m_sendBuffer, m_sendSize, rxBuff1, receivedSize); + + isSuccess &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_0) ? + IsCacheMiss_v5_0(m_sendSize, receivedSize, rxBuff1) : IsCacheMiss(m_sendSize,receivedSize,rxBuff1); + + size_t recievedBufferSize = receivedSize * 3; + size_t sentBufferSize = m_sendSize * 3; + char *recievedBuffer = new char[recievedBufferSize]; + char *sentBuffer = new char[sentBufferSize]; + size_t j; + for(j = 0; j < m_sendSize; j++) + snprintf(&sentBuffer[3 * j], sentBufferSize - 3 * j, + " %02X", m_sendBuffer[j]); + for(j = 0; j < receivedSize; j++) + snprintf(&recievedBuffer[3 * j], recievedBufferSize - 3 * j, + " %02X", rxBuff1[j]); + printf("Expected Value1 (%zu)\n%s\n, Received Value1(%zu)\n%s\n",m_sendSize,sentBuffer,receivedSize,recievedBuffer); + + delete[] rxBuff1; + + return isSuccess; + } + +protected: + uint32_t uRtRuleHdl[3]; + uint8_t uNumRtRules; +}; + +/*--------------------------------------------------------------------------*/ +/* Test16: IPv4 - Tests routing hashable vs non hashable priorities */ +/*--------------------------------------------------------------------------*/ +class IpaRoutingBlockTest016 : public IpaRoutingBlockTestFixture +{ +public: + + IpaRoutingBlockTest016() + { + m_name = "IpaRoutingBlockTest016"; + m_description =" \ + Routing block test 016 - Destination address exact match max priority for non hashable \ + match on both rule, non hashable rule should win because max priority\ + packets are sent. No cache hit is expected\ + 2. Generate and commit Three routing rules: (DST & Mask Match). \ + All DST_IP == (192.168.2.170 & 255.255.255.255)traffic goes to pipe IPA_CLIENT_TEST2_CONS \ + All DST_IP == (192.168.2.170 & 255.255.255.255)traffic goes to pipe IPA_CLIENT_TEST3_CONS\ + All other traffic goes to pipe IPA_CLIENT_TEST4_CONS"; + m_IpaIPType = IPA_IP_v4; + m_minIPAHwType = IPA_HW_v3_0; + Register(*this); + } + + bool AddRules() + { + struct ipa_ioc_add_rt_rule *rt_rule; + struct ipa_rt_rule_add *rt_rule_entry; + const int NUM_RULES = 3; + + rt_rule = (struct ipa_ioc_add_rt_rule *) + calloc(1, sizeof(struct ipa_ioc_add_rt_rule) + + NUM_RULES*sizeof(struct ipa_rt_rule_add)); + + if(!rt_rule) { + printf("Failed memory allocation for rt_rule\n"); + return false; + } + + rt_rule->commit = 1; + rt_rule->num_rules = NUM_RULES; + rt_rule->ip = IPA_IP_v4; + strlcpy(rt_rule->rt_tbl_name, "LAN", sizeof(rt_rule->rt_tbl_name)); + + rt_rule_entry = &rt_rule->rules[0]; + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST2_CONS; + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v4.dst_addr = 0xC0A802AA; //192.168.02.170 + rt_rule_entry->rule.attrib.u.v4.dst_addr_mask = 0xFFFFFFFF; + rt_rule_entry->rule.hashable = 1; // hashable + + rt_rule_entry = &rt_rule->rules[1]; + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST3_CONS; + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v4.dst_addr = 0xC0A802AA; //192.168.02.170 + rt_rule_entry->rule.attrib.u.v4.dst_addr_mask = 0xFFFFFFFF; + rt_rule_entry->rule.hashable = 0; // non hashable + rt_rule_entry->rule.max_prio = 1; // max priority + + rt_rule_entry = &rt_rule->rules[2]; + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST4_CONS; + + if (false == m_routing.AddRoutingRule(rt_rule)) + { + printf("Routing rule addition failed!\n"); + return false; + } + + printf("rt rule hdl1=%x\n", rt_rule_entry->rt_rule_hdl); + + free(rt_rule); + + InitFilteringBlock(); + + return true; + } + + bool Run() + { + bool res = false; + bool isSuccess = false; + + // Add the relevant routing rules + res = AddRules(); + if (false == res) { + printf("Failed adding routing rules.\n"); + return false; + } + + // Load input data (IP packet) from file + res = LoadFiles(IPA_IP_v4); + if (false == res) { + printf("Failed loading files.\n"); + return false; + } + + // Send first packet + m_sendBuffer[DST_ADDR_LSB_OFFSET_IPV4] = 0xAA; + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send second packet + m_sendBuffer2[DST_ADDR_LSB_OFFSET_IPV4] = 0xAA; + isSuccess = m_producer.SendData(m_sendBuffer2, m_sendSize2); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send third packet + isSuccess = m_producer.SendData(m_sendBuffer3, m_sendSize3); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Receive packets from the channels and compare results + isSuccess = ReceivePacketsAndCompare(); + + return isSuccess; + } // Run() + + bool ReceivePacketsAndCompare() + { + size_t receivedSize = 0; + size_t receivedSize2 = 0; + size_t receivedSize3 = 0; + bool isSuccess = true; + + // Receive results + Byte *rxBuff1 = new Byte[0x400]; + Byte *rxBuff2 = new Byte[0x400]; + Byte *rxBuff3 = new Byte[0x400]; + + if (NULL == rxBuff1 || NULL == rxBuff2 || NULL == rxBuff3) + { + printf("Memory allocation error.\n"); + return false; + } + + receivedSize = m_consumer2.ReceiveData(rxBuff1, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize, m_consumer.m_fromChannelName.c_str()); + + receivedSize2 = m_consumer2.ReceiveData(rxBuff2, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize2, m_consumer.m_fromChannelName.c_str()); + + receivedSize3 = m_defaultConsumer.ReceiveData(rxBuff3, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize3, m_defaultConsumer.m_fromChannelName.c_str()); + + /* Compare results */ + isSuccess &= CompareResultVsGolden(m_sendBuffer, m_sendSize, rxBuff1, receivedSize); + isSuccess &= CompareResultVsGolden(m_sendBuffer2, m_sendSize2, rxBuff2, receivedSize2); + isSuccess &= CompareResultVsGolden(m_sendBuffer3, m_sendSize3, rxBuff3, receivedSize3); + + size_t recievedBufferSize = receivedSize * 3; + size_t sentBufferSize = m_sendSize * 3; + char *recievedBuffer = new char[recievedBufferSize]; + char *sentBuffer = new char[sentBufferSize]; + + memset(recievedBuffer, 0, recievedBufferSize); + memset(sentBuffer, 0, sentBufferSize); + + print_packets(receivedSize, m_sendSize, recievedBufferSize, sentBufferSize, rxBuff1, m_sendBuffer, recievedBuffer, sentBuffer); + print_packets(receivedSize2, m_sendSize2, recievedBufferSize, sentBufferSize, rxBuff2, m_sendBuffer2, recievedBuffer, sentBuffer); + print_packets(receivedSize3, m_sendSize3, recievedBufferSize, sentBufferSize, rxBuff3, m_sendBuffer3, recievedBuffer, sentBuffer); + + delete[] recievedBuffer; + delete[] sentBuffer; + + delete[] rxBuff1; + delete[] rxBuff2; + delete[] rxBuff3; + + return isSuccess; + } + +}; + +/*--------------------------------------------------------------------------*/ +/* Test17: IPv4 - Tests routing hashable, non hashable, */ +/* cache/hash invalidation test on rule addition */ +/*--------------------------------------------------------------------------*/ +class IpaRoutingBlockTest017 : public IpaRoutingBlockTest015 +{ +public: + + IpaRoutingBlockTest017() + { + m_name = "IpaRoutingBlockTest017"; + m_description =" \ + Routing block test 017 - this test perform test 015 and then commits another rule\ + another identical packet is sent: DST_IP == 192.168.02.170 and expected to get cache miss"; + } + + bool Run() + { + bool res = false; + bool isSuccess = false; + + // Add the relevant routing rules + res = AddRules(); + if (false == res) { + printf("Failed adding routing rules.\n"); + return false; + } + + // Load input data (IP packet) from file + res = LoadFiles(IPA_IP_v4); + if (false == res) { + printf("Failed loading files.\n"); + return false; + } + + // Send first packet + m_sendBuffer[DST_ADDR_LSB_OFFSET_IPV4] = 0xAA; + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send second packet + m_sendBuffer2[DST_ADDR_LSB_OFFSET_IPV4] = 0xAA; + isSuccess = m_producer.SendData(m_sendBuffer2, m_sendSize2); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send third packet + isSuccess = m_producer.SendData(m_sendBuffer3, m_sendSize3); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Receive packets from the channels and compare results + isSuccess = ReceivePacketsAndCompare(); + if (false == isSuccess) + { + printf("ReceivePacketsAndCompare failure.\n"); + return false; + } + + // until here test 15 was run, now we test hash invalidation + + // commit the rules again to clear the cache + res = AddRules(); + if (false == res) { + printf("Failed adding routing rules.\n"); + return false; + } + + // send the packet again + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // validate we got cache miss + isSuccess = ReceivePacketsAndCompareSpecial(); + if (false == isSuccess) + { + printf("ReceivePacketsAndCompareSpecial failure.\n"); + } + return isSuccess; + } // Run() +}; + +/*--------------------------------------------------------------------------*/ +/* Test18: IPv4 - Tests routing hashable, non hashable, */ +/* cache/hash invalidation test on rule delition */ +/*--------------------------------------------------------------------------*/ +class IpaRoutingBlockTest018 : public IpaRoutingBlockTest015 +{ +public: + + IpaRoutingBlockTest018() + { + m_name = "IpaRoutingBlockTest018"; + m_description =" \ + Routing block test 018 - this test perform test 015 and then removes last rule\ + another identical packet is sent: DST_IP == 192.168.02.170 and expected to get cache miss"; + } + + bool Run() + { + bool res = false; + bool isSuccess = false; + + // Add the relevant routing rules + res = AddRules(); + if (false == res) { + printf("Failed adding routing rules.\n"); + return false; + } + + // Load input data (IP packet) from file + res = LoadFiles(IPA_IP_v4); + if (false == res) { + printf("Failed loading files.\n"); + return false; + } + + // Send first packet + m_sendBuffer[DST_ADDR_LSB_OFFSET_IPV4] = 0xAA; + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send second packet + m_sendBuffer2[DST_ADDR_LSB_OFFSET_IPV4] = 0xAA; + isSuccess = m_producer.SendData(m_sendBuffer2, m_sendSize2); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send third packet + isSuccess = m_producer.SendData(m_sendBuffer3, m_sendSize3); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Receive packets from the channels and compare results + isSuccess = ReceivePacketsAndCompare(); + if (false == isSuccess) + { + printf("ReceivePacketsAndCompare failure.\n"); + return false; + } + + // until here test 15 was run, now we test hash invalidation + + // delete the last rule, this should clear the cache + res = RemoveLastRule(IPA_IP_v4); + if (false == res) { + printf("Failed removing filtering rules.\n"); + return false; + } + + // send the packet again + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // validate we got cache miss + isSuccess = ReceivePacketsAndCompareSpecial(); + if (false == isSuccess) + { + printf("ReceivePacketsAndCompareSpecial failure.\n"); + } + return isSuccess; + } // Run() +}; + +/*--------------------------------------------------------------------------*/ +/* Test20: IPv6 - Tests routing hashable vs non hashable priorities */ +/*--------------------------------------------------------------------------*/ +class IpaRoutingBlockTest020 : public IpaRoutingBlockTest010 +{ +public: + + IpaRoutingBlockTest020() + { + m_name = "IpaRoutingBlockTest20"; + m_description =" \ + Routing block test 020 - Destination address exact match non hashable priority higher than hashable \ + both match the packet but only non hashable should hit\ + 2. Generate and commit Three routing rules: (DST & Mask Match). \ + All DST_IP == 0XFF020000 \ + 0x00000000 \ + 0x00000000 \ + 0X000000FF \ + traffic goes to pipe IPA_CLIENT_TEST2_CONS \ + All DST_IP == 0XFF020000 \ + 0x00000000 \ + 0x00000000 \ + 0X000000FF \ + traffic goes to pipe IPA_CLIENT_TEST3_CONS\ + All other traffic goes to pipe IPA_CLIENT_TEST4_CONS"; + m_IpaIPType = IPA_IP_v6; + m_minIPAHwType = IPA_HW_v3_0; + } + + bool AddRules() + { + struct ipa_ioc_add_rt_rule *rt_rule; + struct ipa_rt_rule_add *rt_rule_entry; + const int NUM_RULES = 3; + + rt_rule = (struct ipa_ioc_add_rt_rule *) + calloc(1, sizeof(struct ipa_ioc_add_rt_rule) + + NUM_RULES*sizeof(struct ipa_rt_rule_add)); + + if(!rt_rule) { + printf("Failed memory allocation for rt_rule\n"); + return false; + } + + rt_rule->commit = 1; + rt_rule->num_rules = NUM_RULES; + rt_rule->ip = IPA_IP_v6; + strlcpy(rt_rule->rt_tbl_name, "LAN", sizeof(rt_rule->rt_tbl_name)); + + rt_rule_entry = &rt_rule->rules[0]; + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST2_CONS; + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v6.dst_addr[0] = 0XFF020000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[1] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[2] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[3] = 0X000000FF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[0] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[1] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[2] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[3] = 0xFFFFFFFF; + rt_rule_entry->rule.hashable = 0; // non hashable + + rt_rule_entry = &rt_rule->rules[1]; + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST3_CONS; + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v6.dst_addr[0] = 0XFF020000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[1] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[2] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[3] = 0X000000FF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[0] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[1] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[2] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[3] = 0xFFFFFFFF; + rt_rule_entry->rule.hashable = 1; // hashable + + rt_rule_entry = &rt_rule->rules[2]; + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST4_CONS; + rt_rule_entry->rule.hashable = 0; // non hashable + + if (false == m_routing.AddRoutingRule(rt_rule)) + { + printf("Routing rule addition failed!\n"); + free(rt_rule); + return false; + } + + printf("rt rule hdl1=%x\n", rt_rule_entry->rt_rule_hdl); + + free(rt_rule); + + InitFilteringBlock(); + + return true; + } + + bool Run() + { + bool res = false; + bool isSuccess = false; + + // Add the relevant routing rules + res = AddRules(); + if (false == res) { + printf("Failed adding routing rules.\n"); + return false; + } + + // Load input data (IP packet) from file + res = LoadFiles(IPA_IP_v6); + if (false == res) { + printf("Failed loading files.\n"); + return false; + } + + // Send first packet + m_sendBuffer[DST_ADDR_LSB_OFFSET_IPV6] = 0xFF; + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send second packet + m_sendBuffer2[DST_ADDR_LSB_OFFSET_IPV6] = 0xFF; + isSuccess = m_producer.SendData(m_sendBuffer2, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send third packet + isSuccess = m_producer.SendData(m_sendBuffer3, m_sendSize3); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Receive packets from the channels and compare results + isSuccess = ReceivePacketsAndCompare(); + + return isSuccess; + } // Run() +}; + + +/*--------------------------------------------------------------------------*/ +/* Test21: IPv6 - Tests routing hashable vs non hashable priorities */ +/*--------------------------------------------------------------------------*/ +class IpaRoutingBlockTest021 : public IpaRoutingBlockTest011 +{ +public: + + IpaRoutingBlockTest021() + { + m_name = "IpaRoutingBlockTest021"; + m_description =" \ + Routing block test 021 - Destination address exact match hashable priority higher than non hashable \ + both match the packet but only hashable should hit, second packet should get cache hit\ + 2. Generate and commit Three routing rules: (DST & Mask Match). \ + All DST_IP == 0XFF020000 \ + 0x00000000 \ + 0x00000000 \ + 0X000000FF - hashable\ + All DST_IP == 0XFF020000 \ + 0x00000000 \ + 0x00000000 \ + 0X000000FF - non hahsable \ + traffic goes to pipe IPA_CLIENT_TEST3_CONS\ + All other traffic goes to pipe IPA_CLIENT_TEST4_CONS"; + m_IpaIPType = IPA_IP_v6; + m_minIPAHwType = IPA_HW_v3_0; + } + + bool AddRules() + { + struct ipa_ioc_add_rt_rule *rt_rule; + struct ipa_rt_rule_add *rt_rule_entry; + const int NUM_RULES = 3; + + rt_rule = (struct ipa_ioc_add_rt_rule *) + calloc(1, sizeof(struct ipa_ioc_add_rt_rule) + + NUM_RULES*sizeof(struct ipa_rt_rule_add)); + + if(!rt_rule) { + printf("Failed memory allocation for rt_rule\n"); + return false; + } + + rt_rule->commit = 1; + rt_rule->num_rules = NUM_RULES; + rt_rule->ip = IPA_IP_v6; + strlcpy(rt_rule->rt_tbl_name, "LAN", sizeof(rt_rule->rt_tbl_name)); + + rt_rule_entry = &rt_rule->rules[0]; + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST2_CONS; + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v6.dst_addr[0] = 0XFF020000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[1] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[2] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[3] = 0X000000FF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[0] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[1] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[2] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[3] = 0xFFFFFFFF; + rt_rule_entry->rule.hashable = 1; // hashable + + rt_rule_entry = &rt_rule->rules[1]; + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST3_CONS; + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v6.dst_addr[0] = 0XFF020000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[1] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[2] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[3] = 0X000000FF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[0] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[1] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[2] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[3] = 0xFFFFFFFF; + rt_rule_entry->rule.hashable = 0; // non hashable + + rt_rule_entry = &rt_rule->rules[2]; + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST4_CONS; + rt_rule_entry->rule.hashable = 0; // non hashable + + if (false == m_routing.AddRoutingRule(rt_rule)) + { + printf("Routing rule addition failed!\n"); + free(rt_rule); + return false; + } + + printf("rt rule hdl1=%x\n", rt_rule_entry->rt_rule_hdl); + + free(rt_rule); + + InitFilteringBlock(); + + return true; + } + + bool Run() + { + bool res = false; + bool isSuccess = false; + + // Add the relevant routing rules + res = AddRules(); + if (false == res) { + printf("Failed adding routing rules.\n"); + return false; + } + + // Load input data (IP packet) from file + res = LoadFiles(IPA_IP_v6); + if (false == res) { + printf("Failed loading files.\n"); + return false; + } + + // Send first packet + m_sendBuffer[DST_ADDR_LSB_OFFSET_IPV6] = 0xFF; + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send second packet + m_sendBuffer2[DST_ADDR_LSB_OFFSET_IPV6] = 0xFF; + isSuccess = m_producer.SendData(m_sendBuffer2, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send third packet + isSuccess = m_producer.SendData(m_sendBuffer3, m_sendSize3); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Receive packets from the channels and compare results + isSuccess = ReceivePacketsAndCompare(); + + return isSuccess; + } // Run() +}; + +/*--------------------------------------------------------------------------*/ +/* Test22: IPv6 - Tests routing hashable vs non hashable priorities */ +/*--------------------------------------------------------------------------*/ +class IpaRoutingBlockTest022 : public IpaRoutingBlockTest012 +{ +public: + + IpaRoutingBlockTest022() + { + m_name = "IpaRoutingBlockTest022"; + m_description =" \ + Routing block test 022 - Destination address exact match hashable priority higher than non hashable \ + no match on non hashable rule (with higher priority), match on hashable rule. two packets with\ + different tuple are sent (but match the rule) cache miss expected\ + 2. Generate and commit Three routing rules: (DST & Mask Match). \ + All DST_IP == 0XFF020000 \ + 0x00000000 \ + 0x00000000 \ + 0X000000AA - non hashable\ + All DST_IP == 0XFF020000 \ + 0x00000000 \ + 0x00000000 \ + 0X000000FF - hahsable \ + All other traffic goes to pipe IPA_CLIENT_TEST4_CONS"; + m_IpaIPType = IPA_IP_v6; + m_minIPAHwType = IPA_HW_v3_0; + } + + bool AddRules() + { + struct ipa_ioc_add_rt_rule *rt_rule; + struct ipa_rt_rule_add *rt_rule_entry; + const int NUM_RULES = 3; + + rt_rule = (struct ipa_ioc_add_rt_rule *) + calloc(1, sizeof(struct ipa_ioc_add_rt_rule) + + NUM_RULES*sizeof(struct ipa_rt_rule_add)); + + if(!rt_rule) { + printf("Failed memory allocation for rt_rule\n"); + return false; + } + + rt_rule->commit = 1; + rt_rule->num_rules = NUM_RULES; + rt_rule->ip = IPA_IP_v6; + strlcpy(rt_rule->rt_tbl_name, "LAN", sizeof(rt_rule->rt_tbl_name)); + + rt_rule_entry = &rt_rule->rules[0]; + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST2_CONS; + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v6.dst_addr[0] = 0XFF020000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[1] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[2] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[3] = 0X000000AA; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[0] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[1] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[2] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[3] = 0xFFFFFFFF; + rt_rule_entry->rule.hashable = 0; // non hashable + + rt_rule_entry = &rt_rule->rules[1]; + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST3_CONS; + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v6.dst_addr[0] = 0XFF020000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[1] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[2] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[3] = 0X000000FF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[0] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[1] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[2] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[3] = 0xFFFFFFFF; + rt_rule_entry->rule.hashable = 1; // hashable + + rt_rule_entry = &rt_rule->rules[2]; + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST4_CONS; + rt_rule_entry->rule.hashable = 0; // non hashable + + if (false == m_routing.AddRoutingRule(rt_rule)) + { + printf("Routing rule addition failed!\n"); + free(rt_rule); + return false; + } + + printf("rt rule hdl1=%x\n", rt_rule_entry->rt_rule_hdl); + + free(rt_rule); + + InitFilteringBlock(); + + return true; + } + + bool Run() + { + bool res = false; + bool isSuccess = false; + unsigned short port; + + // Add the relevant routing rules + res = AddRules(); + if (false == res) { + printf("Failed adding routing rules.\n"); + return false; + } + + // Load input data (IP packet) from file + res = LoadFiles(IPA_IP_v6); + if (false == res) { + printf("Failed loading files.\n"); + return false; + } + + // Send first packet + port = ntohs(546);//DHCP Client Port + memcpy (&m_sendBuffer[IPV6_DST_PORT_OFFSET], &port, sizeof(port)); + m_sendBuffer[DST_ADDR_LSB_OFFSET_IPV6] = 0xFF; + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send second packet + port = ntohs(547);//DHCP Client Port + memcpy (&m_sendBuffer2[IPV6_DST_PORT_OFFSET], &port, sizeof(port)); + m_sendBuffer2[DST_ADDR_LSB_OFFSET_IPV6] = 0xFF; + isSuccess = m_producer.SendData(m_sendBuffer2, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send third packet + isSuccess = m_producer.SendData(m_sendBuffer3, m_sendSize3); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Receive packets from the channels and compare results + isSuccess = ReceivePacketsAndCompare(); + + return isSuccess; + } // Run() +}; + +/*--------------------------------------------------------------------------*/ +/* Test23: IPv6 - Tests routing hashable vs non hashable priorities */ +/*--------------------------------------------------------------------------*/ +class IpaRoutingBlockTest023 : public IpaRoutingBlockTest013 +{ +public: + + IpaRoutingBlockTest023() + { + m_name = "IpaRoutingBlockTest023"; + m_description =" \ + Routing block test 023 - Destination address exact match \ + no match on non hashable rule (with lower priority), match on hashable rule. two packets with\ + different tuple are sent (but match the rule) cache miss expected\ + 2. Generate and commit Three routing rules: (DST & Mask Match). \ + All DST_IP == 0XFF020000 \ + 0x00000000 \ + 0x00000000 \ + 0X000000FF - hashable\ + traffic goes to pipe IPA_CLIENT_TEST2_CONS\ + All DST_IP == 0XFF020000 \ + 0x00000000 \ + 0x00000000 \ + 0X000000AA - non hahsable \ + traffic goes to pipe IPA_CLIENT_TEST3_CONS\ + All other traffic goes to pipe IPA_CLIENT_TEST4_CONS"; + m_IpaIPType = IPA_IP_v6; + m_minIPAHwType = IPA_HW_v3_0; + } + + bool AddRules() + { + struct ipa_ioc_add_rt_rule *rt_rule; + struct ipa_rt_rule_add *rt_rule_entry; + const int NUM_RULES = 3; + + rt_rule = (struct ipa_ioc_add_rt_rule *) + calloc(1, sizeof(struct ipa_ioc_add_rt_rule) + + NUM_RULES*sizeof(struct ipa_rt_rule_add)); + + if(!rt_rule) { + printf("Failed memory allocation for rt_rule\n"); + return false; + } + + rt_rule->commit = 1; + rt_rule->num_rules = NUM_RULES; + rt_rule->ip = IPA_IP_v6; + strlcpy(rt_rule->rt_tbl_name, "LAN", sizeof(rt_rule->rt_tbl_name)); + + rt_rule_entry = &rt_rule->rules[0]; + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST2_CONS; + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v6.dst_addr[0] = 0XFF020000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[1] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[2] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[3] = 0X000000FF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[0] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[1] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[2] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[3] = 0xFFFFFFFF; + rt_rule_entry->rule.hashable = 1; // hashable + + rt_rule_entry = &rt_rule->rules[1]; + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST3_CONS; + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v6.dst_addr[0] = 0XFF020000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[1] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[2] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[3] = 0X000000AA; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[0] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[1] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[2] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[3] = 0xFFFFFFFF; + rt_rule_entry->rule.hashable = 0; // non hashable + + rt_rule_entry = &rt_rule->rules[2]; + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST4_CONS; + rt_rule_entry->rule.hashable = 0; // non hashable + + if (false == m_routing.AddRoutingRule(rt_rule)) + { + printf("Routing rule addition failed!\n"); + free(rt_rule); + return false; + } + + printf("rt rule hdl1=%x\n", rt_rule_entry->rt_rule_hdl); + + free(rt_rule); + + InitFilteringBlock(); + + return true; + } + + bool Run() + { + bool res = false; + bool isSuccess = false; + unsigned short port; + + // Add the relevant routing rules + res = AddRules(); + if (false == res) { + printf("Failed adding routing rules.\n"); + return false; + } + + // Load input data (IP packet) from file + res = LoadFiles(IPA_IP_v6); + if (false == res) { + printf("Failed loading files.\n"); + return false; + } + + // Send first packet + port = ntohs(546);//DHCP Client Port + memcpy (&m_sendBuffer[IPV6_DST_PORT_OFFSET], &port, sizeof(port)); + m_sendBuffer[DST_ADDR_LSB_OFFSET_IPV6] = 0xFF; + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send second packet + port = ntohs(547);//DHCP Client Port + memcpy (&m_sendBuffer2[IPV6_DST_PORT_OFFSET], &port, sizeof(port)); + m_sendBuffer2[DST_ADDR_LSB_OFFSET_IPV6] = 0xFF; + isSuccess = m_producer.SendData(m_sendBuffer2, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send third packet + isSuccess = m_producer.SendData(m_sendBuffer3, m_sendSize3); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Receive packets from the channels and compare results + isSuccess = ReceivePacketsAndCompare(); + + return isSuccess; + } // Run() + +}; + +/*--------------------------------------------------------------------------*/ +/* Test24: IPv6 - Tests routing hashable vs non hashable priorities */ +/*--------------------------------------------------------------------------*/ +class IpaRoutingBlockTest024 : public IpaRoutingBlockTest014 +{ +public: + + IpaRoutingBlockTest024() + { + m_name = "IpaRoutingBlockTest024"; + m_description =" \ + Routing block test 024 - Destination address exact match \ + no match on non hashable rule(with higher priority) , match on hashable rule. two identical\ + packets are sent cache hit expected on the second one\ + 2. Generate and commit Three routing rules: (DST & Mask Match). \ + All DST_IP == 0XFF020000 \ + 0x00000000 \ + 0x00000000 \ + 0X000000AA - non hashable\ + traffic goes to pipe IPA_CLIENT_TEST2_CONS\ + All DST_IP == 0XFF020000 \ + 0x00000000 \ + 0x00000000 \ + 0X000000FF - hahsable \ + traffic goes to pipe IPA_CLIENT_TEST3_CONS\ + All other traffic goes to pipe IPA_CLIENT_TEST4_CONS"; + m_IpaIPType = IPA_IP_v6; + m_minIPAHwType = IPA_HW_v3_0; + } + + bool AddRules() + { + struct ipa_ioc_add_rt_rule *rt_rule; + struct ipa_rt_rule_add *rt_rule_entry; + const int NUM_RULES = 3; + + rt_rule = (struct ipa_ioc_add_rt_rule *) + calloc(1, sizeof(struct ipa_ioc_add_rt_rule) + + NUM_RULES*sizeof(struct ipa_rt_rule_add)); + + if(!rt_rule) { + printf("Failed memory allocation for rt_rule\n"); + return false; + } + + rt_rule->commit = 1; + rt_rule->num_rules = NUM_RULES; + rt_rule->ip = IPA_IP_v6; + strlcpy(rt_rule->rt_tbl_name, "LAN", sizeof(rt_rule->rt_tbl_name)); + + rt_rule_entry = &rt_rule->rules[0]; + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST2_CONS; + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v6.dst_addr[0] = 0XFF020000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[1] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[2] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[3] = 0X000000AA; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[0] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[1] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[2] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[3] = 0xFFFFFFFF; + rt_rule_entry->rule.hashable = 0; // non hashable + + rt_rule_entry = &rt_rule->rules[1]; + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST3_CONS; + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v6.dst_addr[0] = 0XFF020000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[1] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[2] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[3] = 0X000000FF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[0] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[1] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[2] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[3] = 0xFFFFFFFF; + rt_rule_entry->rule.hashable = 1; // hashable + + rt_rule_entry = &rt_rule->rules[2]; + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST4_CONS; + rt_rule_entry->rule.hashable = 0; // non hashable + + if (false == m_routing.AddRoutingRule(rt_rule)) + { + printf("Routing rule addition failed!\n"); + free(rt_rule); + return false; + } + + printf("rt rule hdl1=%x\n", rt_rule_entry->rt_rule_hdl); + + free(rt_rule); + + InitFilteringBlock(); + + return true; + } + + bool Run() + { + bool res = false; + bool isSuccess = false; + + // Add the relevant routing rules + res = AddRules(); + if (false == res) { + printf("Failed adding routing rules.\n"); + return false; + } + + // Load input data (IP packet) from file + res = LoadFiles(IPA_IP_v6); + if (false == res) { + printf("Failed loading files.\n"); + return false; + } + + // Send first packet + m_sendBuffer[DST_ADDR_LSB_OFFSET_IPV6] = 0xFF; + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send second packet + m_sendBuffer2[DST_ADDR_LSB_OFFSET_IPV6] = 0xFF; + isSuccess = m_producer.SendData(m_sendBuffer2, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send third packet + isSuccess = m_producer.SendData(m_sendBuffer3, m_sendSize3); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Receive packets from the channels and compare results + isSuccess = ReceivePacketsAndCompare(); + + return isSuccess; + } // Run() + +}; + +/*--------------------------------------------------------------------------*/ +/* Test25: IPv6 - Tests routing hashable vs non hashable priorities */ +/*--------------------------------------------------------------------------*/ +class IpaRoutingBlockTest025 : public IpaRoutingBlockTest015 +{ +public: + IpaRoutingBlockTest025() + { + m_name = "IpaRoutingBlockTest025"; + m_description =" \ + Routing block test 025 - Destination address exact match \ + no match on non hashable rule(with lower priority) , match on hashable rule. two identical\ + packets are sent cache hit expected on the second one\ + 2. Generate and commit Three routing rules: (DST & Mask Match). \ + All DST_IP == 0XFF020000 \ + 0x00000000 \ + 0x00000000 \ + 0X000000FF - hashable\ + traffic goes to pipe IPA_CLIENT_TEST2_CONS\ + All DST_IP == 0XFF020000 \ + 0x00000000 \ + 0x00000000 \ + 0X000000AA - non hahsable \ + traffic goes to pipe IPA_CLIENT_TEST3_CONS\ + All other traffic goes to pipe IPA_CLIENT_TEST4_CONS"; + m_IpaIPType = IPA_IP_v6; + m_minIPAHwType = IPA_HW_v3_0; + } + + bool AddRules() + { + struct ipa_ioc_add_rt_rule *rt_rule; + struct ipa_rt_rule_add *rt_rule_entry; + const int NUM_RULES = 3; + + rt_rule = (struct ipa_ioc_add_rt_rule *) + calloc(1, sizeof(struct ipa_ioc_add_rt_rule) + + NUM_RULES*sizeof(struct ipa_rt_rule_add)); + + if(!rt_rule) { + printf("Failed memory allocation for rt_rule\n"); + return false; + } + + rt_rule->commit = 1; + rt_rule->num_rules = NUM_RULES; + rt_rule->ip = IPA_IP_v6; + strlcpy(rt_rule->rt_tbl_name, "LAN", sizeof(rt_rule->rt_tbl_name)); + + rt_rule_entry = &rt_rule->rules[0]; + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST2_CONS; + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v6.dst_addr[0] = 0XFF020000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[1] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[2] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[3] = 0X000000FF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[0] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[1] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[2] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[3] = 0xFFFFFFFF; + rt_rule_entry->rule.hashable = 1; // hashable + + rt_rule_entry = &rt_rule->rules[1]; + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST3_CONS; + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v6.dst_addr[0] = 0XFF020000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[1] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[2] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[3] = 0X000000AA; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[0] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[1] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[2] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[3] = 0xFFFFFFFF; + rt_rule_entry->rule.hashable = 0; // non hashable + + rt_rule_entry = &rt_rule->rules[2]; + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST4_CONS; + rt_rule_entry->rule.hashable = 0; // non hashable + + if (false == m_routing.AddRoutingRule(rt_rule)) + { + printf("Routing rule addition failed!\n"); + free(rt_rule); + return false; + } + + for (int i = 0; i < rt_rule->num_rules; i++) { + uRtRuleHdl[i] = rt_rule->rules[i].rt_rule_hdl; + } + uNumRtRules = rt_rule->num_rules; + + printf("rt rule hdl1=%x\n", rt_rule_entry->rt_rule_hdl); + + free(rt_rule); + + InitFilteringBlock(); + + return true; + } + + bool Run() + { + bool res = false; + bool isSuccess = false; + + // Add the relevant routing rules + res = AddRules(); + if (false == res) { + printf("Failed adding routing rules.\n"); + return false; + } + + // Load input data (IP packet) from file + res = LoadFiles(IPA_IP_v6); + if (false == res) { + printf("Failed loading files.\n"); + return false; + } + + // Send first packet + m_sendBuffer[DST_ADDR_LSB_OFFSET_IPV6] = 0xFF; + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send second packet + m_sendBuffer2[DST_ADDR_LSB_OFFSET_IPV6] = 0xFF; + isSuccess = m_producer.SendData(m_sendBuffer2, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send third packet + isSuccess = m_producer.SendData(m_sendBuffer3, m_sendSize3); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Receive packets from the channels and compare results + isSuccess = ReceivePacketsAndCompare(); + + return isSuccess; + } // Run() +}; + + +/*--------------------------------------------------------------------------*/ +/* Test26: IPv6 - Tests routing hashable vs non hashable priorities */ +/*--------------------------------------------------------------------------*/ +class IpaRoutingBlockTest026 : public IpaRoutingBlockTest016 +{ +public: + + IpaRoutingBlockTest026() + { + m_name = "IpaRoutingBlockTest026"; + m_description =" \ + Routing block test 026 - Destination address exact match max priority for non hashable \ + match on both rule, non hashable rule should win because max priority\ + packets are sent cache hit expected on the second one\ + 2. Generate and commit Three routing rules: (DST & Mask Match). \ + All DST_IP == 0XFF020000 \ + 0x00000000 \ + 0x00000000 \ + 0X000000FF - hashable\ + traffic goes to pipe IPA_CLIENT_TEST2_CONS\ + All DST_IP == 0XFF020000 \ + 0x00000000 \ + 0x00000000 \ + 0X000000FF - non hahsable max prio \ + traffic goes to pipe IPA_CLIENT_TEST3_CONS\ + All other traffic goes to pipe IPA_CLIENT_TEST4_CONS"; + m_IpaIPType = IPA_IP_v6; + m_minIPAHwType = IPA_HW_v3_0; + } + + bool AddRules() + { + struct ipa_ioc_add_rt_rule *rt_rule; + struct ipa_rt_rule_add *rt_rule_entry; + const int NUM_RULES = 3; + + rt_rule = (struct ipa_ioc_add_rt_rule *) + calloc(1, sizeof(struct ipa_ioc_add_rt_rule) + + NUM_RULES*sizeof(struct ipa_rt_rule_add)); + + if(!rt_rule) { + printf("Failed memory allocation for rt_rule\n"); + return false; + } + + rt_rule->commit = 1; + rt_rule->num_rules = NUM_RULES; + rt_rule->ip = IPA_IP_v6; + strlcpy(rt_rule->rt_tbl_name, "LAN", sizeof(rt_rule->rt_tbl_name)); + + rt_rule_entry = &rt_rule->rules[0]; + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST2_CONS; + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v6.dst_addr[0] = 0XFF020000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[1] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[2] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[3] = 0X000000FF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[0] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[1] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[2] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[3] = 0xFFFFFFFF; + rt_rule_entry->rule.hashable = 1; // hashable + + rt_rule_entry = &rt_rule->rules[1]; + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST3_CONS; + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v6.dst_addr[0] = 0XFF020000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[1] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[2] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[3] = 0X000000FF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[0] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[1] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[2] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[3] = 0xFFFFFFFF; + rt_rule_entry->rule.hashable = 0; // non hashable + rt_rule_entry->rule.max_prio = 1; // max prio + + rt_rule_entry = &rt_rule->rules[2]; + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST4_CONS; + rt_rule_entry->rule.hashable = 0; // non hashable + + if (false == m_routing.AddRoutingRule(rt_rule)) + { + printf("Routing rule addition failed!\n"); + free(rt_rule); + return false; + } + + printf("rt rule hdl1=%x\n", rt_rule_entry->rt_rule_hdl); + + free(rt_rule); + + InitFilteringBlock(); + + return true; + } + + bool Run() + { + bool res = false; + bool isSuccess = false; + + // Add the relevant routing rules + res = AddRules(); + if (false == res) { + printf("Failed adding routing rules.\n"); + return false; + } + + // Load input data (IP packet) from file + res = LoadFiles(IPA_IP_v6); + if (false == res) { + printf("Failed loading files.\n"); + return false; + } + + // Send first packet + m_sendBuffer[DST_ADDR_LSB_OFFSET_IPV6] = 0xFF; + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send second packet + m_sendBuffer2[DST_ADDR_LSB_OFFSET_IPV6] = 0xFF; + isSuccess = m_producer.SendData(m_sendBuffer2, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send third packet + isSuccess = m_producer.SendData(m_sendBuffer3, m_sendSize3); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Receive packets from the channels and compare results + isSuccess = ReceivePacketsAndCompare(); + + return isSuccess; + } // Run() +}; + +/*--------------------------------------------------------------------------*/ +/* Test27: IPv6 - Tests routing hashable, non hashable, */ +/* cache/hash invalidation test on rule addition */ +/*--------------------------------------------------------------------------*/ +class IpaRoutingBlockTest027 : public IpaRoutingBlockTest025 +{ +public: + + IpaRoutingBlockTest027() + { + m_name = "IpaRoutingBlockTest027"; + m_description =" \ + Routing block test 027 - this test perform test 025 and then commits another rule\ + another identical packet is sent: DST_IP == 192.168.02.170 and expected to get cache miss"; + } + + bool Run() + { + bool res = false; + bool isSuccess = false; + + // Add the relevant routing rules + res = AddRules(); + if (false == res) { + printf("Failed adding routing rules.\n"); + return false; + } + + // Load input data (IP packet) from file + res = LoadFiles(IPA_IP_v6); + if (false == res) { + printf("Failed loading files.\n"); + return false; + } + + // Send first packet + m_sendBuffer[DST_ADDR_LSB_OFFSET_IPV6] = 0xFF; + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send second packet + m_sendBuffer2[DST_ADDR_LSB_OFFSET_IPV6] = 0xFF; + isSuccess = m_producer.SendData(m_sendBuffer2, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send third packet + isSuccess = m_producer.SendData(m_sendBuffer3, m_sendSize3); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Receive packets from the channels and compare results + isSuccess = ReceivePacketsAndCompare(); + if (false == isSuccess) + { + printf("ReceivePacketsAndCompare failure.\n"); + return false; + } + + // until here test 25 was run, now we test hash invalidation + + // commit the rules again to clear the cache + res = AddRules(); + if (false == res) { + printf("Failed adding routing rules.\n"); + return false; + } + + // send the packet again + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // validate we got cache miss + isSuccess = ReceivePacketsAndCompareSpecial(); + if (false == isSuccess) + { + printf("ReceivePacketsAndCompareSpecial failure.\n"); + } + return isSuccess; + } // Run() +}; + +/*--------------------------------------------------------------------------*/ +/* Test28: IPv6 - Tests routing hashable, non hashable, */ +/* cache/hash invalidation test on rule delition */ +/*--------------------------------------------------------------------------*/ +class IpaRoutingBlockTest028 : public IpaRoutingBlockTest025 +{ +public: + + IpaRoutingBlockTest028() + { + m_name = "IpaRoutingBlockTest028"; + m_description =" \ + Routing block test 028 - this test perform test 025 and then deletes last rule\ + another identical packet is sent: DST_IP == 192.168.02.170 and expected to get cache miss"; + } + + bool Run() + { + bool res = false; + bool isSuccess = false; + + // Add the relevant routing rules + res = AddRules(); + if (false == res) { + printf("Failed adding routing rules.\n"); + return false; + } + + // Load input data (IP packet) from file + res = LoadFiles(IPA_IP_v6); + if (false == res) { + printf("Failed loading files.\n"); + return false; + } + + // Send first packet + m_sendBuffer[DST_ADDR_LSB_OFFSET_IPV6] = 0xFF; + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send second packet + m_sendBuffer2[DST_ADDR_LSB_OFFSET_IPV6] = 0xFF; + isSuccess = m_producer.SendData(m_sendBuffer2, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send third packet + isSuccess = m_producer.SendData(m_sendBuffer3, m_sendSize3); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Receive packets from the channels and compare results + isSuccess = ReceivePacketsAndCompare(); + if (false == isSuccess) + { + printf("ReceivePacketsAndCompare failure.\n"); + return false; + } + + // until here test 25 was run, now we test hash invalidation + + // delete the last rule, this should clear the cache + res = RemoveLastRule(IPA_IP_v6); + if (false == res) { + printf("Failed removing filtering rules.\n"); + return false; + } + + // send the packet again + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // validate we got cache miss + isSuccess = ReceivePacketsAndCompareSpecial(); + if (false == isSuccess) + { + printf("ReceivePacketsAndCompareSpecial failure.\n"); + } + return isSuccess; + } // Run() +}; + +/*--------------------------------------------------------------------------*/ +/* Test30: Pure ack packet matching */ +/*--------------------------------------------------------------------------*/ +class IpaRoutingBlockTest030 : IpaRoutingBlockTestFixture +{ +public: + IpaRoutingBlockTest030() + { + m_name = "IpaRoutingBlockTest030"; + m_description =" \ + Routing block test 030 - Pure Ack packet matching \ + 1. Generate and commit a single routing table. \ + 2. Generate and commit Three routing rules: \ + All TCP pure ack traffic goes to pipe IPA_CLIENT_TEST2_CONS \ + All DST_IP == (192.168.2.200 & 255.255.255.255) traffic goes to pipe IPA_CLIENT_TEST3_CONS\ + All other traffic goes to pipe IPA_CLIENT_TEST4_CONS"; + m_IpaIPType = IPA_IP_v4; + m_minIPAHwType = IPA_HW_v4_5; + Register(*this); + } + + bool LoadPackets() + { + if (!LoadNoPayloadPacket(m_IpaIPType, m_sendBuffer, m_sendSize)) { + LOG_MSG_ERROR("Failed loading No Payload Packet"); + return false; + } + + if (!LoadDefaultPacket(m_IpaIPType, m_sendBuffer2, m_sendSize2)) { + LOG_MSG_ERROR("Failed loading default Packet"); + return false; + } + + if (!LoadDefaultPacket(m_IpaIPType, m_sendBuffer3, m_sendSize3)) { + LOG_MSG_ERROR("Failed loading default Packet"); + return false; + } + + return true; + } + + bool Run() + { + bool res = false; + bool isSuccess = false; + + // Add the relevant routing rules + res = AddRules(); + if (false == res) { + printf("Failed adding routing rules.\n"); + return false; + } + + // Load IP packets + res = LoadPackets(); + if (false == res) { + printf("Failed loading packets\n"); + return false; + } + + // Send first packet + m_sendBuffer[IPv4_TCP_FLAGS_OFFSET] |= TCP_ACK_FLAG_MASK; + m_sendBuffer[DST_ADDR_LSB_OFFSET_IPV4] = 0xC8; + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send second packet + m_sendBuffer2[IPv4_TCP_FLAGS_OFFSET] |= TCP_ACK_FLAG_MASK; + m_sendBuffer2[DST_ADDR_LSB_OFFSET_IPV4] = 0xC8; + isSuccess = m_producer.SendData(m_sendBuffer2, m_sendSize2); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send third packet + m_sendBuffer3[IPv4_TCP_FLAGS_OFFSET] |= TCP_ACK_FLAG_MASK; + m_sendBuffer3[DST_ADDR_LSB_OFFSET_IPV4] = 0x64; + isSuccess = m_producer.SendData(m_sendBuffer3, m_sendSize3); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Receive packets from the channels and compare results + isSuccess = ReceivePacketsAndCompare(); + + return isSuccess; + } // Run() + + bool AddRules() + { + struct ipa_ioc_add_rt_rule *rt_rule; + struct ipa_rt_rule_add *rt_rule_entry; + const int NUM_RULES = 3; + + rt_rule = (struct ipa_ioc_add_rt_rule *) + calloc(1, sizeof(struct ipa_ioc_add_rt_rule) + + NUM_RULES*sizeof(struct ipa_rt_rule_add)); + + if(!rt_rule) { + printf("fail\n"); + return false; + } + + rt_rule->commit = 1; + rt_rule->num_rules = NUM_RULES; + rt_rule->ip = IPA_IP_v4; + strlcpy(rt_rule->rt_tbl_name, "LAN", sizeof(rt_rule->rt_tbl_name)); + + rt_rule_entry = &rt_rule->rules[0]; + rt_rule_entry->at_rear = 0; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST2_CONS; + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_IS_PURE_ACK; + + rt_rule_entry = &rt_rule->rules[1]; + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST3_CONS; + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v4.dst_addr = 0xC0A802C8; + rt_rule_entry->rule.attrib.u.v4.dst_addr_mask = 0xFFFFFFFF; + + rt_rule_entry = &rt_rule->rules[2]; + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST4_CONS; + + if (false == m_routing.AddRoutingRule(rt_rule)) + { + printf("Routing rule addition failed!\n"); + return false; + } + + free(rt_rule); + + InitFilteringBlock(); + + return true; + } +}; + +/*--------------------------------------------------------------------------*/ +/* Test31: IPv6 Pure ack packet matching */ +/*--------------------------------------------------------------------------*/ +class IpaRoutingBlockTest031 : public IpaRoutingBlockTestFixture +{ +public: + IpaRoutingBlockTest031() + { + m_name = "IpaRoutingBlockTest031"; + m_description =" \ + Routing block test 031 - IPv6 Pure Ack packet matching \ + 1. Generate and commit a single routing table. \ + 2. Generate and commit Three routing rules: \ + All TCP pure ack traffic goes to pipe IPA_CLIENT_TEST2_CONS \ + All DST_IP == 0XFF020000 \ + 0x00000000 \ + 0x00000000 \ + 0X000000F5 \ + traffic goes to pipe IPA_CLIENT_TEST3_CONS \ + All other traffic goes to pipe IPA_CLIENT_TEST4_CONS"; + m_IpaIPType = IPA_IP_v6; + m_minIPAHwType = IPA_HW_v4_5; + Register(*this); + } + + bool LoadPackets() + { + if (!LoadNoPayloadPacket(m_IpaIPType, m_sendBuffer, m_sendSize)) { + LOG_MSG_ERROR("Failed loading No Payload Packet"); + return false; + } + + if (!LoadNoPayloadPacket(m_IpaIPType, m_sendBuffer2, m_sendSize2)) { + LOG_MSG_ERROR("Failed loading default Packet"); + return false; + } + + if (!LoadNoPayloadPacket(m_IpaIPType, m_sendBuffer3, m_sendSize3)) { + LOG_MSG_ERROR("Failed loading default Packet"); + return false; + } + + return true; + } + + bool Run() + { + bool res = false; + bool isSuccess = false; + + // Add the relevant routing rules + res = AddRules(); + if (false == res) { + printf("Failed adding routing rules.\n"); + return false; + } + + // Load input data (IP packet) + res = LoadPackets(); + if (false == res) { + printf("Failed loading packets\n"); + return false; + } + + // Send first packet + m_sendBuffer[DST_ADDR_LSB_OFFSET_IPV6] = 0xF5; + m_sendBuffer[IPv6_TCP_FLAGS_OFFSET] |= TCP_ACK_FLAG_MASK; + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send second packet + m_sendBuffer2[DST_ADDR_LSB_OFFSET_IPV6] = 0xF5; + isSuccess = m_producer.SendData(m_sendBuffer2, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send third packet + isSuccess = m_producer.SendData(m_sendBuffer3, m_sendSize3); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Receive packets from the channels and compare results + isSuccess = ReceivePacketsAndCompare(); + + return isSuccess; + } // Run() + + bool AddRules() + { + struct ipa_ioc_add_rt_rule *rt_rule; + struct ipa_rt_rule_add *rt_rule_entry; + const int NUM_RULES = 3; + + rt_rule = (struct ipa_ioc_add_rt_rule *) + calloc(1, sizeof(struct ipa_ioc_add_rt_rule) + + NUM_RULES*sizeof(struct ipa_rt_rule_add)); + + if(!rt_rule) { + printf("fail\n"); + return false; + } + + rt_rule->commit = 1; + rt_rule->num_rules = NUM_RULES; + rt_rule->ip = IPA_IP_v6; + strlcpy(rt_rule->rt_tbl_name, "LAN", sizeof(rt_rule->rt_tbl_name)); + + rt_rule_entry = &rt_rule->rules[0]; + rt_rule_entry->at_rear = 0; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST2_CONS; + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_IS_PURE_ACK; + + rt_rule_entry = &rt_rule->rules[1]; + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST3_CONS; + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v6.dst_addr[0] = 0XFF020000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[1] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[2] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[3] = 0X000000F5; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[0] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[1] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[2] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[3] = 0xFFFFFFFF; + + rt_rule_entry = &rt_rule->rules[2]; + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST4_CONS; + + if (false == m_routing.AddRoutingRule(rt_rule)) + { + printf("Routing rule addition failed!\n"); + return false; + } + + free(rt_rule); + + InitFilteringBlock(); + + return true; + } +}; + +/*---------------------------------------------------------------------------*/ +/* Test100: Cache LRU behavior test */ +/*---------------------------------------------------------------------------*/ +#define CHACHE_ENTRIES 64 +#define CHACHE_PLUS_ONE (CHACHE_ENTRIES +1) +class IpaRoutingBlockTest040 : public IpaRoutingBlockTestFixture +{ +public: + IpaRoutingBlockTest040() + { + m_name = "IpaRoutingBlockTest040"; + m_description = " \ + Routing block test 40 - Cache LRU behavior test \ + 1. Preload the cache by sending 64 packets for different connections \ + 2. Send another packet for 65th connection \ + 3. Send packets for first 64 connections \ + 4. Verify that 1st connection’s entry was reclaimed"; + m_IpaIPType = IPA_IP_v4; + m_minIPAHwType = IPA_HW_v4_0; + Register(*this); + } + + bool Setup() + { + return IpaRoutingBlockTestFixture:: Setup(true); + } + + virtual bool AddRules() + { + struct ipa_ioc_add_rt_rule *rt_rule; + struct ipa_rt_rule_add *rt_rule_entry; + + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + + rt_rule = (struct ipa_ioc_add_rt_rule *) + calloc(1, sizeof(struct ipa_ioc_add_rt_rule) + + CHACHE_PLUS_ONE * sizeof(struct ipa_rt_rule_add)); + + if(!rt_rule) { + printf("Failed memory allocation for rt_rule\n"); + return false; + } + + rt_rule->commit = 1; + rt_rule->num_rules = CHACHE_PLUS_ONE; + rt_rule->ip = IPA_IP_v4; + strlcpy(rt_rule->rt_tbl_name, "LAN", sizeof(rt_rule->rt_tbl_name)); + + for (int i = 0; i < CHACHE_PLUS_ONE; i++) { + rt_rule_entry = &rt_rule->rules[i]; + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST2_CONS; + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v4.dst_addr = 0xC0A80101 + i; // DST_IP == 192.168.1.(1+i) + rt_rule_entry->rule.attrib.u.v4.dst_addr_mask = 0xFFFFFFFF; + rt_rule_entry->rule.hashable = 1; + } + + // The last rule has to be catch all, otherwize no rule will work + rt_rule_entry->rule.attrib.u.v4.dst_addr_mask = 0x0; + + if (false == m_routing.AddRoutingRule(rt_rule)) + { + printf("Routing rule addition failed!\n"); + return false; + } + + printf("rt rule hdl1=%x\n", rt_rule_entry->rt_rule_hdl); + + free(rt_rule); + + InitFilteringBlock(); + + printf("Leaving %s, %s()\n",__FUNCTION__, __FILE__); + return true; + } + + bool Run() + { + bool res = false; + bool isSuccess = false; + + printf("Entering %s, %s()\n", __FUNCTION__, __FILE__); + + // Add the relevant filtering rules + res = AddRules(); + if (false == res) { + printf("Failed adding filtering rules.\n"); + return false; + } + + // Load input data (IP packet) from file + res = LoadFiles(IPA_IP_v4); + if (false == res) { + printf("Failed loading files.\n"); + return false; + } + + // Send the first CHACHE_ENTRIES packets + // Receive packets from the channels and compare results + // All rules should be cache miss + for (int i = 0; i < CHACHE_ENTRIES; i++) { + m_sendBuffer[DST_ADDR_LSB_OFFSET_IPV4] = 0x1 + i; + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + isSuccess = ReceivePacketAndCompareFrom(m_consumer, m_sendBuffer, m_sendSize, false); + if (false == isSuccess) { + printf("%s:%d: ReceivePacketAndCompareFrom failure.\n", __FUNCTION__, __LINE__); + return false; + } + } + + // Send again the first CHACHE_ENTRIES packets + // Receive packets from the channels and compare results + // All rules should be cache hit + for (int i = 0; i < CHACHE_ENTRIES; i++) { + m_sendBuffer[DST_ADDR_LSB_OFFSET_IPV4] = 0x1 + i; + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + isSuccess = ReceivePacketAndCompareFrom(m_consumer, m_sendBuffer, m_sendSize, true); + if (false == isSuccess) { + printf("%s:%d: ReceivePacketAndCompareFrom failure.\n", __FUNCTION__, __LINE__); + return false; + } + } + + // Send a packet to a new filter entry, this should trigger the LRU clear + m_sendBuffer[DST_ADDR_LSB_OFFSET_IPV4] = 0x1 + CHACHE_ENTRIES; + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) { + printf("SendData failure.\n"); + return false; + } + + // receive and verify that cache was missed + isSuccess = ReceivePacketAndCompareFrom(m_consumer, m_sendBuffer, m_sendSize, false); + if (false == isSuccess) { + printf("%s:%d: ReceivePacketAndCompareFrom failure.\n", __FUNCTION__, __LINE__); + return false; + } + + // send the first packet again + m_sendBuffer[DST_ADDR_LSB_OFFSET_IPV4] = 0x1; + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) { + printf("SendData failure.\n"); + return false; + } + + // receive and verify that cache was missed + isSuccess = ReceivePacketAndCompareFrom(m_consumer, m_sendBuffer, m_sendSize, false); + if (false == isSuccess) { + printf("%s:%d: ReceivePacketAndCompareFrom failure.\n", __FUNCTION__, __LINE__); + return false; + } + + printf("Leaving %s, %s(), Returning %d\n",__FUNCTION__, __FILE__, isSuccess); + + return isSuccess; + } // Run() +}; + +/*---------------------------------------------------------------------------*/ +/* Test50: Test TTL update by routing to a destination address */ +/*---------------------------------------------------------------------------*/ +class IpaRoutingBlockTest050 : public IpaRoutingBlockTestFixture +{ +public: + IpaRoutingBlockTest050() + { + m_name = "IpaRoutingBlockTest050"; + m_description =" \ + Routing block test 050 - Destination address exact match\1. Generate and commit a single routing tables. \ + 2. Generate and commit Three routing rules: (DST & Mask Match). \ + All DST_IP == (192.169.2.170 & 255.255.255.255)traffic goes to pipe IPA_CLIENT_TEST2_CONS \ + All DST_IP == (192.168.2.255 & 255.255.255.255)traffic goes to pipe IPA_CLIENT_TEST3_CONS\ + All other traffic goes to pipe IPA_CLIENT_TEST4_CONS \ + 3. Check if TTL is updated. "; + m_IpaIPType = IPA_IP_v4; + m_minIPAHwType = IPA_HW_v5_5; + Register(*this); + } + + bool Setup() + { + return IpaRoutingBlockTestFixture:: Setup(true); + } + + bool AddRules() + { + struct ipa_ioc_add_rt_rule_v2 *rt_rule; + struct ipa_rt_rule_add_v2 *rt_rule_entry; + const int NUM_RULES = 3; + + rt_rule = (struct ipa_ioc_add_rt_rule_v2 *) + calloc(1, sizeof(struct ipa_ioc_add_rt_rule_v2)); + + if(!rt_rule) { + printf("fail\n"); + return false; + } + + rt_rule->rules = (uint64_t)calloc(3, sizeof(struct ipa_rt_rule_add_v2)); + if(!rt_rule->rules) { + printf("fail\n"); + return false; + } + + rt_rule->commit = 1; + rt_rule->num_rules = NUM_RULES; + rt_rule->ip = IPA_IP_v4; + strlcpy(rt_rule->rt_tbl_name, "LAN", sizeof(rt_rule->rt_tbl_name)); + + rt_rule_entry = &(((struct ipa_rt_rule_add_v2 *)rt_rule->rules)[0]); + rt_rule_entry->at_rear = 0; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST2_CONS; + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v4.dst_addr = 0xC0A802FF; + rt_rule_entry->rule.attrib.u.v4.dst_addr_mask = 0xFFFFFFFF; + rt_rule_entry->rule.ttl_update = 1; + + rt_rule_entry = &(((struct ipa_rt_rule_add_v2 *)rt_rule->rules)[1]); + rt_rule_entry->at_rear = 0; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST3_CONS; + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v4.dst_addr = 0xC0A802AA; + rt_rule_entry->rule.attrib.u.v4.dst_addr_mask = 0xFFFFFFFF; + rt_rule_entry->rule.ttl_update = 1; + + rt_rule_entry = &(((struct ipa_rt_rule_add_v2 *)rt_rule->rules)[2]); + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.ttl_update = 0; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST4_CONS; + + if (false == m_routing.AddRoutingRule(rt_rule)) + { + printf("Routing rule addition failed!\n"); + return false; + } + + printf("rt rule hdl1=%x\n", rt_rule_entry->rt_rule_hdl); + + free(rt_rule); + + InitFilteringBlock(); + + return true; + } + + virtual bool Run() + { + bool res = false; + bool isSuccess = false; + + // Add the relevant routing rules + res = AddRules(); + if (false == res) { + printf("Failed adding routing rules.\n"); + return false; + } + + // Load input data (IP packet) from file + res = LoadFiles(IPA_IP_v4); + if (false == res) { + printf("Failed loading files.\n"); + return false; + } + + // Send first packet + m_sendBuffer[DST_ADDR_LSB_OFFSET_IPV4] = 0xFF; + m_sendBuffer[IPV4_TTL_OFFSET] = 5; + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send second packet + m_sendBuffer2[DST_ADDR_LSB_OFFSET_IPV4] = 0xAA; + m_sendBuffer2[IPV4_TTL_OFFSET] = 4; + isSuccess = m_producer.SendData(m_sendBuffer2, m_sendSize2); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send third packet + m_sendBuffer3[IPV4_TTL_OFFSET] = 3; + isSuccess = m_producer.SendData(m_sendBuffer3, m_sendSize3); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Receive packets from the channels and compare results + isSuccess = ReceivePacketsAndCompare(); + + return isSuccess; + } // Run() + + bool ReceivePacketsAndCompare() + { + size_t receivedSize = 0; + size_t receivedSize2 = 0; + size_t receivedSize3 = 0; + bool pkt1_cmp_succ, pkt2_cmp_succ, pkt3_cmp_succ; + uint16_t csum = 0; + + // Receive results + Byte *rxBuff1 = new Byte[0x400]; + Byte *rxBuff2 = new Byte[0x400]; + Byte *rxBuff3 = new Byte[0x400]; + + if (NULL == rxBuff1 || NULL == rxBuff2 || NULL == rxBuff3) + { + printf("Memory allocation error.\n"); + return false; + } + + memset(rxBuff1, 0, 0x400); + memset(rxBuff2, 0, 0x400); + memset(rxBuff3, 0, 0x400); + + receivedSize = m_consumer.ReceiveData(rxBuff1, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize, m_consumer.m_fromChannelName.c_str()); + + receivedSize2 = m_consumer2.ReceiveData(rxBuff2, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize2, m_consumer2.m_fromChannelName.c_str()); + + receivedSize3 = m_defaultConsumer.ReceiveData(rxBuff3, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize3, m_defaultConsumer.m_fromChannelName.c_str()); + + /* Update TTL values. */ + m_sendBuffer[IPV4_TTL_OFFSET] = 4; + m_sendBuffer2[IPV4_TTL_OFFSET] = 3; + + /* Update Checksum.*/ + csum = *((uint16_t *)(m_sendBuffer + IPV4_CSUM_OFFSET)); + csum += 1; + *((uint16_t *)(m_sendBuffer+ IPV4_CSUM_OFFSET)) = csum; + + csum = *((uint16_t *)(m_sendBuffer2 + IPV4_CSUM_OFFSET)); + csum += 1; + *((uint16_t *)(m_sendBuffer2 + IPV4_CSUM_OFFSET)) = csum; + + /* Compare results */ + pkt1_cmp_succ = CompareResultVsGolden(m_sendBuffer, m_sendSize, rxBuff1, receivedSize); + pkt2_cmp_succ = CompareResultVsGolden(m_sendBuffer2, m_sendSize2, rxBuff2, receivedSize2); + pkt3_cmp_succ = CompareResultVsGolden(m_sendBuffer3, m_sendSize3, rxBuff3, receivedSize3); + + size_t recievedBufferSize = + MAX3(receivedSize, receivedSize2, receivedSize3) * 3; + size_t sentBufferSize = + MAX3(m_sendSize, m_sendSize2, m_sendSize3) * 3; + char *recievedBuffer = new char[recievedBufferSize]; + char *sentBuffer = new char[sentBufferSize]; + + if (NULL == recievedBuffer || NULL == sentBuffer) { + printf("Memory allocation error\n"); + return false; + } + + size_t j; + memset(recievedBuffer, 0, recievedBufferSize); + memset(sentBuffer, 0, sentBufferSize); + for(j = 0; j < m_sendSize; j++) + snprintf(&sentBuffer[3 * j], sentBufferSize - (3 * j + 1), " %02X", m_sendBuffer[j]); + for(j = 0; j < receivedSize; j++) + snprintf(&recievedBuffer[3 * j], recievedBufferSize - (3 * j + 1), " %02X", rxBuff1[j]); + printf("Expected Value1(%zu)\n%s\n, Received Value1(%zu)\n%s\n-->Value1 %s\n", + m_sendSize,sentBuffer,receivedSize,recievedBuffer, + pkt1_cmp_succ?"Match":"no Match"); + + memset(recievedBuffer, 0, recievedBufferSize); + memset(sentBuffer, 0, sentBufferSize); + for(j = 0; j < m_sendSize2; j++) + snprintf(&sentBuffer[3 * j], sentBufferSize - (3 * j + 1), " %02X", m_sendBuffer2[j]); + for(j = 0; j < receivedSize2; j++) + snprintf(&recievedBuffer[3 * j], recievedBufferSize - (3 * j + 1), " %02X", rxBuff2[j]); + printf("Expected Value2 (%zu)\n%s\n, Received Value2(%zu)\n%s\n-->Value2 %s\n", + m_sendSize2,sentBuffer,receivedSize2,recievedBuffer, + pkt2_cmp_succ?"Match":"no Match"); + + memset(recievedBuffer, 0, recievedBufferSize); + memset(sentBuffer, 0, sentBufferSize); + for(j = 0; j < m_sendSize3; j++) + snprintf(&sentBuffer[3 * j], sentBufferSize - (3 * j + 1), " %02X", m_sendBuffer3[j]); + for(j = 0; j < receivedSize3; j++) + snprintf(&recievedBuffer[3 * j], recievedBufferSize - (3 * j + 1), " %02X", rxBuff3[j]); + printf("Expected Value3 (%zu)\n%s\n, Received Value3(%zu)\n%s\n-->Value3 %s\n", + m_sendSize3,sentBuffer,receivedSize3,recievedBuffer, + pkt3_cmp_succ?"Match":"no Match"); + + delete[] recievedBuffer; + delete[] sentBuffer; + + delete[] rxBuff1; + delete[] rxBuff2; + delete[] rxBuff3; + + return pkt1_cmp_succ && pkt2_cmp_succ && pkt3_cmp_succ; + } +}; + +/*--------------------------------------------------------------------------*/ +/* Test51: IPv4 - Tests routing hashable vs non hashable priorities */ +/*--------------------------------------------------------------------------*/ +class IpaRoutingBlockTest051 : public IpaRoutingBlockTestFixture +{ +public: + + IpaRoutingBlockTest051() + { + m_name = "IpaRoutingBlockTest051"; + m_description =" \ + Routing block test 051 - Destination address exact match hashable priority higher than non hashable \ + both match the packet but only hashable should hit, second packet should get cache hit, \ + Check if TTL is updated.\ + 2. Generate and commit Three routing rules: (DST & Mask Match). \ + All DST_IP == (192.168.2.170 & 255.255.255.255)traffic goes to pipe IPA_CLIENT_TEST2_CONS \ + All DST_IP == (192.168.2.170 & 255.255.255.255)traffic goes to pipe IPA_CLIENT_TEST3_CONS\ + All other traffic goes to pipe IPA_CLIENT_TEST4_CONS \ + 3. Check if TTL is updated."; + m_IpaIPType = IPA_IP_v4; + m_minIPAHwType = IPA_HW_v5_5; + Register(*this); + } + + bool Setup() + { + return IpaRoutingBlockTestFixture:: Setup(true); + } + + bool AddRules() + { + struct ipa_ioc_add_rt_rule_v2 *rt_rule; + struct ipa_rt_rule_add_v2 *rt_rule_entry; + const int NUM_RULES = 3; + + rt_rule = (struct ipa_ioc_add_rt_rule_v2 *) + calloc(1, sizeof(struct ipa_ioc_add_rt_rule_v2)); + + if(!rt_rule) { + printf("fail\n"); + return false; + } + + rt_rule->rules = (uint64_t)calloc(3, sizeof(struct ipa_rt_rule_add_v2)); + if(!rt_rule->rules) { + printf("fail\n"); + return false; + } + + rt_rule->commit = 1; + rt_rule->num_rules = NUM_RULES; + rt_rule->ip = IPA_IP_v4; + strlcpy(rt_rule->rt_tbl_name, "LAN", sizeof(rt_rule->rt_tbl_name)); + + rt_rule_entry = &(((struct ipa_rt_rule_add_v2 *)rt_rule->rules)[0]); + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST2_CONS; + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v4.dst_addr = 0xC0A802AA; //192.168.02.170 + rt_rule_entry->rule.attrib.u.v4.dst_addr_mask = 0xFFFFFFFF; + rt_rule_entry->rule.hashable = 1; // hashable + rt_rule_entry->rule.ttl_update = 1; // TTL Update + + rt_rule_entry = &(((struct ipa_rt_rule_add_v2 *)rt_rule->rules)[1]); + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST3_CONS; + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v4.dst_addr = 0xC0A802AA; //192.168.02.170 + rt_rule_entry->rule.attrib.u.v4.dst_addr_mask = 0xFFFFFFFF; + rt_rule_entry->rule.hashable = 0; // non hashable + rt_rule_entry->rule.ttl_update = 1; // TTL Update + + rt_rule_entry = &(((struct ipa_rt_rule_add_v2 *)rt_rule->rules)[2]); + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.ttl_update = 0; // TTL Update + rt_rule_entry->rule.dst = IPA_CLIENT_TEST4_CONS; + + if (false == m_routing.AddRoutingRule(rt_rule)) + { + printf("Routing rule addition failed!\n"); + return false; + } + + printf("rt rule hdl1=%x\n", rt_rule_entry->rt_rule_hdl); + + free(rt_rule); + + InitFilteringBlock(); + + return true; + } + + bool Run() + { + bool res = false; + bool isSuccess = false; + + // Add the relevant routing rules + res = AddRules(); + if (false == res) { + printf("Failed adding routing rules.\n"); + return false; + } + + // Load input data (IP packet) from file + res = LoadFiles(IPA_IP_v4); + if (false == res) { + printf("Failed loading files.\n"); + return false; + } + + // Send first packet + m_sendBuffer[DST_ADDR_LSB_OFFSET_IPV4] = 0xAA; + m_sendBuffer[IPV4_TTL_OFFSET] = 5; + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send second packet + m_sendBuffer2[DST_ADDR_LSB_OFFSET_IPV4] = 0xAA; + m_sendBuffer2[IPV4_TTL_OFFSET] = 4; + isSuccess = m_producer.SendData(m_sendBuffer2, m_sendSize2); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send third packet + m_sendBuffer3[IPV4_TTL_OFFSET] = 3; + isSuccess = m_producer.SendData(m_sendBuffer3, m_sendSize3); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Receive packets from the channels and compare results + isSuccess = ReceivePacketsAndCompare(); + + return isSuccess; + } // Run() + + bool ReceivePacketsAndCompare() + { + size_t receivedSize = 0; + size_t receivedSize2 = 0; + size_t receivedSize3 = 0; + bool isSuccess = true; + uint16_t csum = 0; + + // Receive results + Byte *rxBuff1 = new Byte[0x400]; + Byte *rxBuff2 = new Byte[0x400]; + Byte *rxBuff3 = new Byte[0x400]; + + if (NULL == rxBuff1 || NULL == rxBuff2 || NULL == rxBuff3) + { + printf("Memory allocation error.\n"); + return false; + } + + receivedSize = m_consumer.ReceiveData(rxBuff1, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize, m_consumer.m_fromChannelName.c_str()); + + receivedSize2 = m_consumer.ReceiveData(rxBuff2, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize2, m_consumer2.m_fromChannelName.c_str()); + + receivedSize3 = m_defaultConsumer.ReceiveData(rxBuff3, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize3, m_defaultConsumer.m_fromChannelName.c_str()); + + /* Update TTL values. */ + m_sendBuffer[IPV4_TTL_OFFSET] = 4; + m_sendBuffer2[IPV4_TTL_OFFSET] = 3; + + /* Update Checksum.*/ + csum = *((uint16_t *)(m_sendBuffer + IPV4_CSUM_OFFSET)); + csum += 1; + *((uint16_t *)(m_sendBuffer+ IPV4_CSUM_OFFSET)) = csum; + + csum = *((uint16_t *)(m_sendBuffer2 + IPV4_CSUM_OFFSET)); + csum += 1; + *((uint16_t *)(m_sendBuffer2 + IPV4_CSUM_OFFSET)) = csum; + + /* Compare results */ + isSuccess &= CompareResultVsGolden_w_Status(m_sendBuffer, m_sendSize, rxBuff1, receivedSize); + isSuccess &= CompareResultVsGolden_w_Status(m_sendBuffer2, m_sendSize2, rxBuff2, receivedSize2); + isSuccess &= CompareResultVsGolden_w_Status(m_sendBuffer3, m_sendSize3, rxBuff3, receivedSize3); + + isSuccess &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_0) ? + IsCacheMiss_v5_0(m_sendSize, receivedSize, rxBuff1) : IsCacheMiss(m_sendSize,receivedSize,rxBuff1); + isSuccess &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_0) ? + IsCacheHit_v5_0(m_sendSize2, receivedSize2, rxBuff2) : IsCacheHit(m_sendSize2,receivedSize2,rxBuff2); + isSuccess &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_0) ? + IsCacheMiss_v5_0(m_sendSize3, receivedSize3, rxBuff3) : IsCacheMiss(m_sendSize3,receivedSize3,rxBuff3); + + isSuccess &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_5) ? + IsTTLUpdated_v5_5(m_sendSize, receivedSize, rxBuff1) : true; + isSuccess &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_5) ? + IsTTLUpdated_v5_5(m_sendSize2, receivedSize2, rxBuff2) : true; + isSuccess &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_5) ? + !IsTTLUpdated_v5_5(m_sendSize3, receivedSize3, rxBuff3) : true; + + size_t recievedBufferSize = receivedSize * 3; + size_t sentBufferSize = m_sendSize * 3; + char *recievedBuffer = new char[recievedBufferSize]; + char *sentBuffer = new char[sentBufferSize]; + + memset(recievedBuffer, 0, recievedBufferSize); + memset(sentBuffer, 0, sentBufferSize); + + print_packets(receivedSize, m_sendSize, recievedBufferSize, sentBufferSize, rxBuff1, m_sendBuffer, recievedBuffer, sentBuffer); + print_packets(receivedSize2, m_sendSize2, recievedBufferSize, sentBufferSize, rxBuff2, m_sendBuffer2, recievedBuffer, sentBuffer); + print_packets(receivedSize3, m_sendSize3, recievedBufferSize, sentBufferSize, rxBuff3, m_sendBuffer3, recievedBuffer, sentBuffer); + + delete[] recievedBuffer; + delete[] sentBuffer; + + delete[] rxBuff1; + delete[] rxBuff2; + delete[] rxBuff3; + + return isSuccess; + } +}; + +/*---------------------------------------------------------------------------*/ +/* Test52: IPv6 - Test TTL update by routing to destination address */ +/*---------------------------------------------------------------------------*/ +class IpaRoutingBlockTest052 : public IpaRoutingBlockTestFixture +{ +public: + IpaRoutingBlockTest052() + { + m_name = "IpaRoutingBlockTest052"; + m_description =" \ + Routing block test 052 - IPv6 Destination address exact match and check if TTL is updated \ + 1. Generate and commit a single routing tables. \ + 2. Generate and commit Three routing rules: (DST & Mask Match). \ + All DST_IP == 0XFF020000 \ + 0x00000000 \ + 0x00000000 \ + 0X000000FF \ + traffic goes to pipe IPA_CLIENT_TEST2_CONS \ + All DST_IP == 0XFF020000 \ + 0x00000000 \ + 0x00000000 \ + 0X000000FF \ + traffic goes to pipe IPA_CLIENT_TEST3_CONS\ + All other traffic goes to pipe IPA_CLIENT_TEST4_CONS \ + 3. Check if TTL is updated."; + m_IpaIPType = IPA_IP_v6; + m_minIPAHwType = IPA_HW_v5_5; + Register(*this); + } + + bool Run() + { + bool res = false; + bool isSuccess = false; + + // Add the relevant routing rules + res = AddRules(); + if (false == res) { + printf("Failed adding routing rules.\n"); + return false; + } + + // Load input data (IP packet) from file + res = LoadFiles(IPA_IP_v6); + if (false == res) { + printf("Failed loading files.\n"); + return false; + } + + // Send first packet + m_sendBuffer[DST_ADDR_LSB_OFFSET_IPV6] = 0xFF; + m_sendBuffer[HOP_LIMIT_OFFSET_IPV6] = 5; + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send second packet + m_sendBuffer2[DST_ADDR_LSB_OFFSET_IPV6] = 0xAA; + m_sendBuffer2[HOP_LIMIT_OFFSET_IPV6] = 4; + isSuccess = m_producer.SendData(m_sendBuffer2, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send third packet + m_sendBuffer3[HOP_LIMIT_OFFSET_IPV6] = 3; + isSuccess = m_producer.SendData(m_sendBuffer3, m_sendSize3); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Receive packets from the channels and compare results + isSuccess = ReceivePacketsAndCompare(); + + return isSuccess; + } // Run() + + bool ReceivePacketsAndCompare() + { + size_t receivedSize = 0; + size_t receivedSize2 = 0; + size_t receivedSize3 = 0; + bool pkt1_cmp_succ, pkt2_cmp_succ, pkt3_cmp_succ; + + // Receive results + Byte *rxBuff1 = new Byte[0x400]; + Byte *rxBuff2 = new Byte[0x400]; + Byte *rxBuff3 = new Byte[0x400]; + + if (NULL == rxBuff1 || NULL == rxBuff2 || NULL == rxBuff3) + { + printf("Memory allocation error.\n"); + return false; + } + + memset(rxBuff1, 0, 0x400); + memset(rxBuff2, 0, 0x400); + memset(rxBuff3, 0, 0x400); + + receivedSize = m_consumer.ReceiveData(rxBuff1, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize, m_consumer.m_fromChannelName.c_str()); + + receivedSize2 = m_consumer2.ReceiveData(rxBuff2, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize2, m_consumer2.m_fromChannelName.c_str()); + + receivedSize3 = m_defaultConsumer.ReceiveData(rxBuff3, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize3, m_defaultConsumer.m_fromChannelName.c_str()); + + /* Update TTL values. */ + m_sendBuffer[HOP_LIMIT_OFFSET_IPV6] = 4; + m_sendBuffer2[HOP_LIMIT_OFFSET_IPV6] = 3; + + /* Compare results */ + pkt1_cmp_succ = CompareResultVsGolden(m_sendBuffer, m_sendSize, rxBuff1, receivedSize); + pkt2_cmp_succ = CompareResultVsGolden(m_sendBuffer2, m_sendSize2, rxBuff2, receivedSize2); + pkt3_cmp_succ = CompareResultVsGolden(m_sendBuffer3, m_sendSize3, rxBuff3, receivedSize3); + + size_t recievedBufferSize = + MAX3(receivedSize, receivedSize2, receivedSize3) * 3; + size_t sentBufferSize = + MAX3(m_sendSize, m_sendSize2, m_sendSize3) * 3; + char *recievedBuffer = new char[recievedBufferSize]; + char *sentBuffer = new char[sentBufferSize]; + + if (NULL == recievedBuffer || NULL == sentBuffer) { + printf("Memory allocation error\n"); + return false; + } + + size_t j; + memset(recievedBuffer, 0, recievedBufferSize); + memset(sentBuffer, 0, sentBufferSize); + for(j = 0; j < m_sendSize; j++) + snprintf(&sentBuffer[3 * j], sentBufferSize - (3 * j + 1), " %02X", m_sendBuffer[j]); + for(j = 0; j < receivedSize; j++) + snprintf(&recievedBuffer[3 * j], recievedBufferSize - (3 * j + 1), " %02X", rxBuff1[j]); + printf("Expected Value1(%zu)\n%s\n, Received Value1(%zu)\n%s\n-->Value1 %s\n", + m_sendSize,sentBuffer,receivedSize,recievedBuffer, + pkt1_cmp_succ?"Match":"no Match"); + + memset(recievedBuffer, 0, recievedBufferSize); + memset(sentBuffer, 0, sentBufferSize); + for(j = 0; j < m_sendSize2; j++) + snprintf(&sentBuffer[3 * j], sentBufferSize - (3 * j + 1), " %02X", m_sendBuffer2[j]); + for(j = 0; j < receivedSize2; j++) + snprintf(&recievedBuffer[3 * j], recievedBufferSize - (3 * j + 1), " %02X", rxBuff2[j]); + printf("Expected Value2 (%zu)\n%s\n, Received Value2(%zu)\n%s\n-->Value2 %s\n", + m_sendSize2,sentBuffer,receivedSize2,recievedBuffer, + pkt2_cmp_succ?"Match":"no Match"); + + memset(recievedBuffer, 0, recievedBufferSize); + memset(sentBuffer, 0, sentBufferSize); + for(j = 0; j < m_sendSize3; j++) + snprintf(&sentBuffer[3 * j], sentBufferSize - (3 * j + 1), " %02X", m_sendBuffer3[j]); + for(j = 0; j < receivedSize3; j++) + snprintf(&recievedBuffer[3 * j], recievedBufferSize - (3 * j + 1), " %02X", rxBuff3[j]); + printf("Expected Value3 (%zu)\n%s\n, Received Value3(%zu)\n%s\n-->Value3 %s\n", + m_sendSize3,sentBuffer,receivedSize3,recievedBuffer, + pkt3_cmp_succ?"Match":"no Match"); + + delete[] recievedBuffer; + delete[] sentBuffer; + + delete[] rxBuff1; + delete[] rxBuff2; + delete[] rxBuff3; + + return pkt1_cmp_succ && pkt2_cmp_succ && pkt3_cmp_succ; + } + + bool AddRules() + { + struct ipa_ioc_add_rt_rule_v2 *rt_rule; + struct ipa_rt_rule_add_v2 *rt_rule_entry; + const int NUM_RULES = 3; + + rt_rule = (struct ipa_ioc_add_rt_rule_v2 *) + calloc(1, sizeof(struct ipa_ioc_add_rt_rule_v2)); + + if(!rt_rule) { + printf("fail\n"); + return false; + } + + rt_rule->rules = (uint64_t)calloc(3, sizeof(struct ipa_rt_rule_add_v2)); + if(!rt_rule->rules) { + printf("fail\n"); + return false; + } + + rt_rule->commit = 1; + rt_rule->num_rules = NUM_RULES; + rt_rule->ip = IPA_IP_v6; + strlcpy(rt_rule->rt_tbl_name, "LAN", sizeof(rt_rule->rt_tbl_name)); + + rt_rule_entry = &(((struct ipa_rt_rule_add_v2 *)rt_rule->rules)[0]); + rt_rule_entry->at_rear = 0; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST2_CONS; +// rt_rule_entry->rule.hdr_hdl = hdr_entry->hdr_hdl; // gidons, there is no support for header insertion / removal yet. + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v6.dst_addr[0] = 0XFF020000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[1] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[2] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[3] = 0X000000FF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[0] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[1] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[2] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[3] = 0xFFFFFFFF; + rt_rule_entry->rule.ttl_update = 1; // TTL Update + + rt_rule_entry = &(((struct ipa_rt_rule_add_v2 *)rt_rule->rules)[1]); + rt_rule_entry->at_rear = 0; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST3_CONS; +// rt_rule_entry->rule.hdr_hdl = hdr_entry->hdr_hdl; // gidons, there is no support for header insertion / removal yet. + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v6.dst_addr[0] = 0XFF020000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[1] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[2] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[3] = 0X000000AA; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[0] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[1] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[2] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[3] = 0xFFFFFFFF; + rt_rule_entry->rule.ttl_update = 1; // TTL Update + + rt_rule_entry = &(((struct ipa_rt_rule_add_v2 *)rt_rule->rules)[2]); + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST4_CONS; + rt_rule_entry->rule.ttl_update = 0; // TTL Update + if (false == m_routing.AddRoutingRule(rt_rule)) + { + printf("Routing rule addition failed!\n"); + return false; + } + + printf("rt rule hdl1=%x\n", rt_rule_entry->rt_rule_hdl); + + free(rt_rule); + + InitFilteringBlock(); + + return true; + } +}; + +/*---------------------------------------------------------------------------------------*/ +/* Test53: IPv6 - Test TTL update by routing to destination address and check for status */ +/*---------------------------------------------------------------------------------------*/ +class IpaRoutingBlockTest053 : public IpaRoutingBlockTestFixture +{ +public: + IpaRoutingBlockTest053() + { + m_name = "IpaRoutingBlockTest053"; + m_description =" \ + Routing block test 053 - IPv6 Destination address exact match and check if TTL is updated \ + 1. Generate and commit a single routing tables. \ + 2. Generate and commit Three routing rules: (DST & Mask Match). \ + All DST_IP == 0XFF020000 \ + 0x00000000 \ + 0x00000000 \ + 0X000000FF \ + traffic goes to pipe IPA_CLIENT_TEST2_CONS \ + All DST_IP == 0XFF020000 \ + 0x00000000 \ + 0x00000000 \ + 0X000000FF \ + traffic goes to pipe IPA_CLIENT_TEST3_CONS\ + All other traffic goes to pipe IPA_CLIENT_TEST4_CONS \ + 3. Check if TTL is updated and also the status has TTL bit updated."; + m_IpaIPType = IPA_IP_v6; + m_minIPAHwType = IPA_HW_v5_5; + Register(*this); + } + + bool Setup() + { + return IpaRoutingBlockTestFixture:: Setup(true); + } + + bool Run() + { + bool res = false; + bool isSuccess = false; + + // Add the relevant routing rules + res = AddRules(); + if (false == res) { + printf("Failed adding routing rules.\n"); + return false; + } + + // Load input data (IP packet) from file + res = LoadFiles(IPA_IP_v6); + if (false == res) { + printf("Failed loading files.\n"); + return false; + } + + // Send first packet + m_sendBuffer[DST_ADDR_LSB_OFFSET_IPV6] = 0xFF; + m_sendBuffer[HOP_LIMIT_OFFSET_IPV6] = 5; + isSuccess = m_producer.SendData(m_sendBuffer, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send second packet + m_sendBuffer2[DST_ADDR_LSB_OFFSET_IPV6] = 0xAA; + m_sendBuffer2[HOP_LIMIT_OFFSET_IPV6] = 4; + isSuccess = m_producer.SendData(m_sendBuffer2, m_sendSize); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Send third packet + m_sendBuffer3[HOP_LIMIT_OFFSET_IPV6] = 3; + isSuccess = m_producer.SendData(m_sendBuffer3, m_sendSize3); + if (false == isSuccess) + { + printf("SendData failure.\n"); + return false; + } + + // Receive packets from the channels and compare results + isSuccess = ReceivePacketsAndCompare(); + + return isSuccess; + } // Run() + + bool ReceivePacketsAndCompare() + { + size_t receivedSize = 0; + size_t receivedSize2 = 0; + size_t receivedSize3 = 0; + bool pkt1_cmp_succ, pkt2_cmp_succ, pkt3_cmp_succ; + + // Receive results + Byte *rxBuff1 = new Byte[0x400]; + Byte *rxBuff2 = new Byte[0x400]; + Byte *rxBuff3 = new Byte[0x400]; + + if (NULL == rxBuff1 || NULL == rxBuff2 || NULL == rxBuff3) + { + printf("Memory allocation error.\n"); + return false; + } + + memset(rxBuff1, 0, 0x400); + memset(rxBuff2, 0, 0x400); + memset(rxBuff3, 0, 0x400); + + receivedSize = m_consumer.ReceiveData(rxBuff1, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize, m_consumer.m_fromChannelName.c_str()); + + receivedSize2 = m_consumer2.ReceiveData(rxBuff2, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize2, m_consumer2.m_fromChannelName.c_str()); + + receivedSize3 = m_defaultConsumer.ReceiveData(rxBuff3, 0x400); + printf("Received %zu bytes on %s.\n", receivedSize3, m_defaultConsumer.m_fromChannelName.c_str()); + + /* Update TTL values. */ + m_sendBuffer[HOP_LIMIT_OFFSET_IPV6] = 4; + m_sendBuffer2[HOP_LIMIT_OFFSET_IPV6] = 3; + + /* Compare results */ + pkt1_cmp_succ = CompareResultVsGolden_w_Status(m_sendBuffer, m_sendSize, rxBuff1, receivedSize); + pkt2_cmp_succ = CompareResultVsGolden_w_Status(m_sendBuffer2, m_sendSize2, rxBuff2, receivedSize2); + pkt3_cmp_succ = CompareResultVsGolden_w_Status(m_sendBuffer3, m_sendSize3, rxBuff3, receivedSize3); + + pkt1_cmp_succ &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_5) ? + IsTTLUpdated_v5_5(m_sendSize, receivedSize, rxBuff1) : true; + pkt2_cmp_succ &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_5) ? + IsTTLUpdated_v5_5(m_sendSize2, receivedSize2, rxBuff2) : true; + pkt3_cmp_succ &= (TestManager::GetInstance()->GetIPAHwType() >= IPA_HW_v5_5) ? + !IsTTLUpdated_v5_5(m_sendSize3, receivedSize3, rxBuff3) : true; + + size_t recievedBufferSize = + MAX3(receivedSize, receivedSize2, receivedSize3) * 3; + size_t sentBufferSize = + MAX3(m_sendSize, m_sendSize2, m_sendSize3) * 3; + char *recievedBuffer = new char[recievedBufferSize]; + char *sentBuffer = new char[sentBufferSize]; + + if (NULL == recievedBuffer || NULL == sentBuffer) { + printf("Memory allocation error\n"); + return false; + } + + size_t j; + memset(recievedBuffer, 0, recievedBufferSize); + memset(sentBuffer, 0, sentBufferSize); + for(j = 0; j < m_sendSize; j++) + snprintf(&sentBuffer[3 * j], sentBufferSize - (3 * j + 1), " %02X", m_sendBuffer[j]); + for(j = 0; j < receivedSize; j++) + snprintf(&recievedBuffer[3 * j], recievedBufferSize - (3 * j + 1), " %02X", rxBuff1[j]); + printf("Expected Value1(%zu)\n%s\n, Received Value1(%zu)\n%s\n-->Value1 %s\n", + m_sendSize,sentBuffer,receivedSize,recievedBuffer, + pkt1_cmp_succ?"Match":"no Match"); + + memset(recievedBuffer, 0, recievedBufferSize); + memset(sentBuffer, 0, sentBufferSize); + for(j = 0; j < m_sendSize2; j++) + snprintf(&sentBuffer[3 * j], sentBufferSize - (3 * j + 1), " %02X", m_sendBuffer2[j]); + for(j = 0; j < receivedSize2; j++) + snprintf(&recievedBuffer[3 * j], recievedBufferSize - (3 * j + 1), " %02X", rxBuff2[j]); + printf("Expected Value2 (%zu)\n%s\n, Received Value2(%zu)\n%s\n-->Value2 %s\n", + m_sendSize2,sentBuffer,receivedSize2,recievedBuffer, + pkt2_cmp_succ?"Match":"no Match"); + + memset(recievedBuffer, 0, recievedBufferSize); + memset(sentBuffer, 0, sentBufferSize); + for(j = 0; j < m_sendSize3; j++) + snprintf(&sentBuffer[3 * j], sentBufferSize - (3 * j + 1), " %02X", m_sendBuffer3[j]); + for(j = 0; j < receivedSize3; j++) + snprintf(&recievedBuffer[3 * j], recievedBufferSize - (3 * j + 1), " %02X", rxBuff3[j]); + printf("Expected Value3 (%zu)\n%s\n, Received Value3(%zu)\n%s\n-->Value3 %s\n", + m_sendSize3,sentBuffer,receivedSize3,recievedBuffer, + pkt3_cmp_succ?"Match":"no Match"); + + delete[] recievedBuffer; + delete[] sentBuffer; + + delete[] rxBuff1; + delete[] rxBuff2; + delete[] rxBuff3; + + return pkt1_cmp_succ && pkt2_cmp_succ && pkt3_cmp_succ; + } + + bool AddRules() + { + struct ipa_ioc_add_rt_rule_v2 *rt_rule; + struct ipa_rt_rule_add_v2 *rt_rule_entry; + const int NUM_RULES = 3; + + rt_rule = (struct ipa_ioc_add_rt_rule_v2 *) + calloc(1, sizeof(struct ipa_ioc_add_rt_rule_v2)); + + if(!rt_rule) { + printf("fail\n"); + return false; + } + + rt_rule->rules = (uint64_t)calloc(3, sizeof(struct ipa_rt_rule_add_v2)); + if(!rt_rule->rules) { + printf("fail\n"); + return false; + } + + rt_rule->commit = 1; + rt_rule->num_rules = NUM_RULES; + rt_rule->ip = IPA_IP_v6; + strlcpy(rt_rule->rt_tbl_name, "LAN", sizeof(rt_rule->rt_tbl_name)); + + rt_rule_entry = &(((struct ipa_rt_rule_add_v2 *)rt_rule->rules)[0]); + rt_rule_entry->at_rear = 0; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST2_CONS; +// rt_rule_entry->rule.hdr_hdl = hdr_entry->hdr_hdl; // gidons, there is no support for header insertion / removal yet. + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v6.dst_addr[0] = 0XFF020000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[1] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[2] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[3] = 0X000000FF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[0] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[1] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[2] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[3] = 0xFFFFFFFF; + rt_rule_entry->rule.ttl_update = 1; // TTL Update + + rt_rule_entry = &(((struct ipa_rt_rule_add_v2 *)rt_rule->rules)[1]); + rt_rule_entry->at_rear = 0; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST3_CONS; +// rt_rule_entry->rule.hdr_hdl = hdr_entry->hdr_hdl; // gidons, there is no support for header insertion / removal yet. + rt_rule_entry->rule.attrib.attrib_mask = IPA_FLT_DST_ADDR; + rt_rule_entry->rule.attrib.u.v6.dst_addr[0] = 0XFF020000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[1] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[2] = 0x00000000; + rt_rule_entry->rule.attrib.u.v6.dst_addr[3] = 0X000000AA; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[0] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[1] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[2] = 0xFFFFFFFF; + rt_rule_entry->rule.attrib.u.v6.dst_addr_mask[3] = 0xFFFFFFFF; + rt_rule_entry->rule.ttl_update = 1; // TTL Update + + rt_rule_entry = &(((struct ipa_rt_rule_add_v2 *)rt_rule->rules)[2]); + rt_rule_entry->at_rear = 1; + rt_rule_entry->rule.dst = IPA_CLIENT_TEST4_CONS; + rt_rule_entry->rule.ttl_update = 0; // TTL Update + if (false == m_routing.AddRoutingRule(rt_rule)) + { + printf("Routing rule addition failed!\n"); + return false; + } + + printf("rt rule hdl1=%x\n", rt_rule_entry->rt_rule_hdl); + + free(rt_rule); + + InitFilteringBlock(); + + return true; + } +}; + + +static class IpaRoutingBlockTest1 ipaRoutingBlockTest1; +static class IpaRoutingBlockTest2 ipaRoutingBlockTest2; +static class IpaRoutingBlockTest3 ipaRoutingBlockTest3; +static class IpaRoutingBlockTest4 ipaRoutingBlockTest4; +static class IpaRoutingBlockTest5 ipaRoutingBlockTest5; +static class IpaRoutingBlockTest006 ipaRoutingBlockTest006; +static class IpaRoutingBlockTest007 ipaRoutingBlockTest007; +static class IpaRoutingBlockTest008 ipaRoutingBlockTest008; +static class IpaRoutingBlockTest009 ipaRoutingBlockTest009; + +static class IpaRoutingBlockTest010 ipaRoutingBlockTest010; +static class IpaRoutingBlockTest011 ipaRoutingBlockTest011; +static class IpaRoutingBlockTest012 ipaRoutingBlockTest012; +static class IpaRoutingBlockTest013 ipaRoutingBlockTest013; +static class IpaRoutingBlockTest014 ipaRoutingBlockTest014; +static class IpaRoutingBlockTest015 ipaRoutingBlockTest015; +static class IpaRoutingBlockTest016 ipaRoutingBlockTest016; +static class IpaRoutingBlockTest017 ipaRoutingBlockTest017; +static class IpaRoutingBlockTest018 ipaRoutingBlockTest018; + +static class IpaRoutingBlockTest020 ipaRoutingBlockTest020; +static class IpaRoutingBlockTest021 ipaRoutingBlockTest021; +static class IpaRoutingBlockTest022 ipaRoutingBlockTest022; +static class IpaRoutingBlockTest023 ipaRoutingBlockTest023; +static class IpaRoutingBlockTest024 ipaRoutingBlockTest024; +static class IpaRoutingBlockTest025 ipaRoutingBlockTest025; +static class IpaRoutingBlockTest026 ipaRoutingBlockTest026; +static class IpaRoutingBlockTest027 ipaRoutingBlockTest027; +static class IpaRoutingBlockTest028 ipaRoutingBlockTest028; + +static class IpaRoutingBlockTest030 ipaRoutingBlockTest030; +static class IpaRoutingBlockTest031 ipaRoutingBlockTest031; + +static class IpaRoutingBlockTest040 ipaRoutingBlockTest040; + +static class IpaRoutingBlockTest050 ipaRoutingBlockTest050; +static class IpaRoutingBlockTest051 ipaRoutingBlockTest051; +static class IpaRoutingBlockTest052 ipaRoutingBlockTest052; +static class IpaRoutingBlockTest053 ipaRoutingBlockTest053; diff --git a/qcom/opensource/dataipa/kernel-tests/TLPAggregationTestFixture.cpp b/qcom/opensource/dataipa/kernel-tests/TLPAggregationTestFixture.cpp new file mode 100644 index 0000000000..b3b94634ad --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/TLPAggregationTestFixture.cpp @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2017 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "TLPAggregationTestFixture.h" + +///////////////////////////////////////////////////////////////////////////////// + +//define the static Pipes which will be used by all derived tests. +Pipe TLPAggregationTestFixture::m_IpaToUsbPipeNoAgg(IPA_CLIENT_TEST3_CONS, + IPA_TEST_CONFIGURATION_8); +Pipe TLPAggregationTestFixture::m_IpaToUsbPipeAggr(IPA_CLIENT_TEST_CONS, + IPA_TEST_CONFIGURATION_8); +Pipe TLPAggregationTestFixture::m_UsbNoAggToIpaPipeAgg(IPA_CLIENT_TEST3_PROD, + IPA_TEST_CONFIGURATION_8); +Pipe TLPAggregationTestFixture::m_UsbDeaggToIpaPipeNoAgg(IPA_CLIENT_TEST_PROD, + IPA_TEST_CONFIGURATION_8); +Pipe TLPAggregationTestFixture::m_UsbDeaggToIpaPipeAgg(IPA_CLIENT_TEST2_PROD, + IPA_TEST_CONFIGURATION_8); +Pipe TLPAggregationTestFixture::m_IpaToUsbPipeAggTime(IPA_CLIENT_TEST2_CONS, + IPA_TEST_CONFIGURATION_8); +Pipe TLPAggregationTestFixture::m_UsbNoAggToIpaPipeAggTime(IPA_CLIENT_TEST4_PROD, + IPA_TEST_CONFIGURATION_8); + +///////////////////////////////////////////////////////////////////////////////// + +TLPAggregationTestFixture::TLPAggregationTestFixture() +{ + m_testSuiteName.push_back("TLPAgg"); + m_maxIPAHwType = IPA_HW_v2_6L; + Register(*this); +} + +///////////////////////////////////////////////////////////////////////////////// + +bool TLPAggregationTestFixture::Setup() +{ + bool bRetVal = true; + + //Set the configuration to support USB->IPA and IPA->USB pipes. + ConfigureScenario(8); + + //Initialize the pipe for all the tests - this will open the inode which represents the pipe. + bRetVal &= m_IpaToUsbPipeNoAgg.Init(); + bRetVal &= m_IpaToUsbPipeAggr.Init(); + bRetVal &= m_UsbNoAggToIpaPipeAgg.Init(); + bRetVal &= m_UsbDeaggToIpaPipeNoAgg.Init(); + bRetVal &= m_UsbDeaggToIpaPipeAgg.Init(); + bRetVal &= m_IpaToUsbPipeAggTime.Init(); + bRetVal &= m_UsbNoAggToIpaPipeAggTime.Init(); + return bRetVal; +} + +///////////////////////////////////////////////////////////////////////////////// + +bool TLPAggregationTestFixture::Teardown() +{ + //The Destroy method will close the inode. + m_IpaToUsbPipeNoAgg.Destroy(); + m_IpaToUsbPipeAggr.Destroy(); + m_UsbNoAggToIpaPipeAgg.Destroy(); + m_UsbDeaggToIpaPipeNoAgg.Destroy(); + m_UsbDeaggToIpaPipeAgg.Destroy(); + m_IpaToUsbPipeAggTime.Destroy(); + m_UsbNoAggToIpaPipeAggTime.Destroy(); + return true; +} + +///////////////////////////////////////////////////////////////////////////////// diff --git a/qcom/opensource/dataipa/kernel-tests/TLPAggregationTestFixture.h b/qcom/opensource/dataipa/kernel-tests/TLPAggregationTestFixture.h new file mode 100644 index 0000000000..7e88e7e740 --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/TLPAggregationTestFixture.h @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2017 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include + +#include "Constants.h" +#include "Logger.h" +#include "linux/msm_ipa.h" +#include "TestsUtils.h" +#include "TestBase.h" +#include "Pipe.h" + +/*This class will be the base class of all TLP Aggregation tests. + *Any method other than the test case itself can be declared in + *this Fixture thus allowing the derived classes to + *implement only the test case. + *All the test of the Aggregation uses one + *input and one output in DMA mode. + */ +class TLPAggregationTestFixture:public TestBase +{ +public: + /*This Constructor will register each instance that it creates.*/ + TLPAggregationTestFixture(); + + /*This method will create and initialize two Pipe object for the + *USB (Ethernet) Pipes, one as input and the other as output. + */ + virtual bool Setup(); + + /*This method will destroy the pipes.*/ + virtual bool Teardown(); + + /*The client type are set from the peripheral perspective*/ + static Pipe m_IpaToUsbPipeNoAgg; + static Pipe m_IpaToUsbPipeAggr; + static Pipe m_UsbNoAggToIpaPipeAgg; + static Pipe m_UsbDeaggToIpaPipeNoAgg; + static Pipe m_UsbDeaggToIpaPipeAgg; + static Pipe m_IpaToUsbPipeAggTime; + static Pipe m_UsbNoAggToIpaPipeAggTime; +}; diff --git a/qcom/opensource/dataipa/kernel-tests/TLPAggregationTests.cpp b/qcom/opensource/dataipa/kernel-tests/TLPAggregationTests.cpp new file mode 100644 index 0000000000..c9bb2a5637 --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/TLPAggregationTests.cpp @@ -0,0 +1,946 @@ +/* + * Copyright (c) 2017 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include + +#include "TLPAggregationTestFixture.h" +#include "Constants.h" +#include "TestsUtils.h" +#include "linux/msm_ipa.h" + +#define NUM_PACKETS 5 +#define TIME_LIMIT_NUM_PACKETS 1 +#define MAX_PACKET_SIZE 1024 +#define AGGREGATION_LOOP 4 + +int test_num = 0; + +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// + +class TLPAggregationTest: public TLPAggregationTestFixture { +public: + + ///////////////////////////////////////////////////////////////////////////////// + + TLPAggregationTest() + { + m_name = "TLPAggregationTest"; + m_description = "TLP Aggregation test - sends 5 packets and receives 1 " + "aggregated packet"; + } + + ///////////////////////////////////////////////////////////////////////////////// + + bool Run() + { + bool bTestResult = true; + //The packets that will be sent + Byte pPackets[NUM_PACKETS][MAX_PACKET_SIZE]; + //The real sizes of the packets that will be sent + int pPacketsSizes[NUM_PACKETS]; + //Buffer for the packet that will be received + Byte pReceivedPacket[MAX_PACKET_SIZE]; + //Total size of all sent packets (this is the max size of the aggregated packet + //minus 2 bytes for each packet in the aggregated packet) + int nTotalPacketsSize = MAX_PACKET_SIZE - (2 * NUM_PACKETS); + //The expected aggregated packet + Byte pExpectedAggregatedPacket[MAX_PACKET_SIZE] = {0}; + + //initialize the packets + //example: for NUM_PACKETS = 5 and MAX_PACKET_SIZE = 1024: + //nTotalPacketsSize will be 1024 - 5*2 = 1014 + //packets[0] size will be 1014/5 = 202 bytes of 0 + //packets[1] size will be (1014 - 202) / 5 = 162 bytes of 1 + //packets[2] size will be (1014 - 201 - 162) / 5 = 130 bytes of 2 + //packets[3] size will be (1014 - 201 - 162 - 130) / 5 = 104 bytes of 3 + //packets[4] size will be 1014 - 201 - 162 - 130 - 104 = 416 bytes of 4 + for (int i = 0; i < NUM_PACKETS; i++) + { + if (NUM_PACKETS - 1 == i) + pPacketsSizes[i] = nTotalPacketsSize; + else + pPacketsSizes[i] = nTotalPacketsSize / NUM_PACKETS; + nTotalPacketsSize -= pPacketsSizes[i]; + for (int j = 0; j < pPacketsSizes[i]; j++) + pPackets[i][j] = i + 16*test_num; + } + test_num++; + + //send the packets + for (int i = 0; i < NUM_PACKETS; i++) + { + LOG_MSG_DEBUG("Sending packet %d into the USB pipe(%d bytes)\n", i, + pPacketsSizes[i]); + int nBytesSent = m_UsbNoAggToIpaPipeAgg.Send(pPackets[i], + pPacketsSizes[i]); + if (pPacketsSizes[i] != nBytesSent) + { + LOG_MSG_DEBUG("Sending packet %d into the USB pipe(%d bytes) " + "failed!\n", i, pPacketsSizes[i]); + return false; + } + } + + //receive the aggregated packet + LOG_MSG_DEBUG("Reading packet from the USB pipe(%d bytes should be " + "there)\n", MAX_PACKET_SIZE); + int nBytesReceived = m_IpaToUsbPipeAggr.Receive(pReceivedPacket, + MAX_PACKET_SIZE); + if (MAX_PACKET_SIZE != nBytesReceived) + { + LOG_MSG_DEBUG("Receiving aggregated packet from the USB pipe(%d " + "bytes) failed!\n", MAX_PACKET_SIZE); + print_buff(pReceivedPacket, nBytesReceived); + return false; + } + + + //initializing the aggregated packet + int k = 0; + for (int i = 0; i < NUM_PACKETS; i++) + { + //the first 2 bytes are the packet length in little endian + pExpectedAggregatedPacket[k] = pPacketsSizes[i] & 0x00FF; + pExpectedAggregatedPacket[k+1] = pPacketsSizes[i] >> 8; + k += 2; + for (int j = 0; j < pPacketsSizes[i]; j++) + { + pExpectedAggregatedPacket[k] = pPackets[i][j]; + k++; + } + } + + //comparing the received packet to the aggregated packet + LOG_MSG_DEBUG("Checking sent.vs.received packet\n"); + + bTestResult &= !memcmp(pExpectedAggregatedPacket, pReceivedPacket, + sizeof(pReceivedPacket)); + + return bTestResult; + } + + ///////////////////////////////////////////////////////////////////////////////// +}; + +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// + +class TLPDeaggregationTest: public TLPAggregationTestFixture { +public: + + ///////////////////////////////////////////////////////////////////////////////// + + TLPDeaggregationTest() + { + m_name = "TLPDeaggregationTest"; + m_description = "TLP Deaggregation test - sends an aggregated packet made from" + "5 packets and receives 5 packets"; + } + + ///////////////////////////////////////////////////////////////////////////////// + + bool Run() + { + bool bTestResult = true; + //The packets that the aggregated packet will be made of + Byte pExpectedPackets[NUM_PACKETS][MAX_PACKET_SIZE]; + //The real sizes of the packets that the aggregated packet will be made of + int pPacketsSizes[NUM_PACKETS]; + //Buffers for the packets that will be received + Byte pReceivedPackets[NUM_PACKETS][MAX_PACKET_SIZE]; + //Total size of all the packets that the aggregated packet will be made of + //(this is the max size of the aggregated packet + //minus 2 bytes for each packet in the aggregated packet) + int nTotalPacketsSize = MAX_PACKET_SIZE - (2 * NUM_PACKETS); + //The aggregated packet that will be sent + Byte pAggregatedPacket[MAX_PACKET_SIZE] = {0}; + + //initialize the packets + //example: for NUM_PACKETS = 5 and MAX_PACKET_SIZE = 1024: + //nTotalPacketsSize will be 1024 - 5*2 = 1014 + //packets[0] size will be 1014/5 = 202 bytes of 0 + //packets[1] size will be (1014 - 202) / 5 = 162 bytes of 1 + //packets[2] size will be (1014 - 201 - 162) / 5 = 130 bytes of 2 + //packets[3] size will be (1014 - 201 - 162 - 130) / 5 = 104 bytes of 3 + //packets[4] size will be 1014 - 201 - 162 - 130 - 104 = 416 bytes of 4 + for (int i = 0; i < NUM_PACKETS; i++) + { + if (NUM_PACKETS - 1 == i) + pPacketsSizes[i] = nTotalPacketsSize; + else + pPacketsSizes[i] = nTotalPacketsSize / NUM_PACKETS; + nTotalPacketsSize -= pPacketsSizes[i]; + for (int j = 0; j < pPacketsSizes[i]; j++) + pExpectedPackets[i][j] = i+ 16*test_num; + } + test_num++; + + //initializing the aggregated packet + int k = 0; + for (int i = 0; i < NUM_PACKETS; i++) + { + //the first 2 bytes are the packet length in little endian + pAggregatedPacket[k] = pPacketsSizes[i] & 0x00FF; + pAggregatedPacket[k+1] = pPacketsSizes[i] >> 8; + k += 2; + for (int j = 0; j < pPacketsSizes[i]; j++) + { + pAggregatedPacket[k] = pExpectedPackets[i][j]; + k++; + } + } + + //send the aggregated packet + LOG_MSG_DEBUG("Sending aggregated packet into the USB pipe(%d bytes)\n", + sizeof(pAggregatedPacket)); + int nBytesSent = m_UsbDeaggToIpaPipeNoAgg.Send(pAggregatedPacket, + sizeof(pAggregatedPacket)); + if (sizeof(pAggregatedPacket) != nBytesSent) + { + LOG_MSG_DEBUG("Sending aggregated packet into the USB pipe(%d bytes) " + "failed!\n", sizeof(pAggregatedPacket)); + return false; + } + + + //receive the packets + for (int i = 0; i < NUM_PACKETS; i++) + { + LOG_MSG_DEBUG("Reading packet %d from the USB pipe(%d bytes should be " + "there)\n", i, pPacketsSizes[i]); + int nBytesReceived = m_IpaToUsbPipeNoAgg.Receive(pReceivedPackets[i], + pPacketsSizes[i]); + if (pPacketsSizes[i] != nBytesReceived) + { + LOG_MSG_DEBUG("Receiving packet %d from the USB pipe(%d bytes) " + "failed!\n", i, pPacketsSizes[i]); + print_buff(pReceivedPackets[i], nBytesReceived); + return false; + } + } + + //comparing the received packet to the aggregated packet + LOG_MSG_DEBUG("Checking sent.vs.received packet\n"); + for (int i = 0; i < NUM_PACKETS; i++) + bTestResult &= !memcmp(pExpectedPackets[i], pReceivedPackets[i], pPacketsSizes[i]); + + return bTestResult; + } + + ///////////////////////////////////////////////////////////////////////////////// +}; + +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// + + +class TLPDeaggregationAndAggregationTest: public TLPAggregationTestFixture { +public: + + ///////////////////////////////////////////////////////////////////////////////// + + TLPDeaggregationAndAggregationTest() + { + m_name = "TLPDeaggregationAndAggregationTest"; + m_description = "TLP Deaggregation and Aggregation test - sends an aggregated " + "packet made from 5 packets and receives the same aggregated packet"; + } + + ///////////////////////////////////////////////////////////////////////////////// + + bool Run() + { + bool bTestResult = true; + //The packets that the aggregated packet will be made of + Byte pPackets[NUM_PACKETS][MAX_PACKET_SIZE]; + //The real sizes of the packets that the aggregated packet will be made of + int pPacketsSizes[NUM_PACKETS]; + //Buffers for the packets that will be received + Byte pReceivedPacket[MAX_PACKET_SIZE]; + //Total size of all the packets that the aggregated packet will be made of + //(this is the max size of the aggregated packet + //minus 2 bytes for each packet in the aggregated packet) + int nTotalPacketsSize = MAX_PACKET_SIZE - (2 * NUM_PACKETS); + //The aggregated packet that will be sent + Byte pAggregatedPacket[MAX_PACKET_SIZE] = {0}; + + //initialize the packets + //example: for NUM_PACKETS = 5 and MAX_PACKET_SIZE = 1024: + //nTotalPacketsSize will be 1024 - 5*2 = 1014 + //packets[0] size will be 1014/5 = 202 bytes of 0 + //packets[1] size will be (1014 - 202) / 5 = 162 bytes of 1 + //packets[2] size will be (1014 - 201 - 162) / 5 = 130 bytes of 2 + //packets[3] size will be (1014 - 201 - 162 - 130) / 5 = 104 bytes of 3 + //packets[4] size will be 1014 - 201 - 162 - 130 - 104 = 416 bytes of 4 + for (int i = 0; i < NUM_PACKETS; i++) + { + if (NUM_PACKETS - 1 == i) + pPacketsSizes[i] = nTotalPacketsSize; + else + pPacketsSizes[i] = nTotalPacketsSize / NUM_PACKETS; + nTotalPacketsSize -= pPacketsSizes[i]; + for (int j = 0; j < pPacketsSizes[i]; j++) + pPackets[i][j] = i+ 16*test_num; + } + test_num++; + + //initializing the aggregated packet + int k = 0; + for (int i = 0; i < NUM_PACKETS; i++) + { + //the first 2 bytes are the packet length in little endian + pAggregatedPacket[k] = pPacketsSizes[i] & 0x00FF; + pAggregatedPacket[k+1] = pPacketsSizes[i] >> 8; + k += 2; + for (int j = 0; j < pPacketsSizes[i]; j++) + { + pAggregatedPacket[k] = pPackets[i][j]; + k++; + } + } + + //send the aggregated packet + LOG_MSG_DEBUG("Sending aggregated packet into the USB pipe(%d bytes)\n", + sizeof(pAggregatedPacket)); + int nBytesSent = m_UsbDeaggToIpaPipeAgg.Send(pAggregatedPacket, + sizeof(pAggregatedPacket)); + if (sizeof(pAggregatedPacket) != nBytesSent) + { + LOG_MSG_DEBUG("Sending aggregated packet into the USB pipe(%d bytes)" + " failed!\n", sizeof(pAggregatedPacket)); + return false; + } + + //receive the aggregated packet + LOG_MSG_DEBUG("Reading aggregated packet from the USB pipe(%d bytes " + "should be there)\n", sizeof(pAggregatedPacket)); + int nBytesReceived = m_IpaToUsbPipeAggr.Receive(pReceivedPacket, + sizeof(pAggregatedPacket)); + if (sizeof(pAggregatedPacket) != nBytesReceived) + { + LOG_MSG_DEBUG("Receiving aggregated packet from the USB pipe(%d " + "bytes) failed!\n", sizeof(pAggregatedPacket)); + LOG_MSG_DEBUG("Received %d bytes\n", nBytesReceived); + print_buff(pReceivedPacket, nBytesReceived); + return false; + } +print_buff(pReceivedPacket, nBytesReceived); + + //comparing the received packet to the aggregated packet + LOG_MSG_DEBUG("Checking sent.vs.received packet\n"); + bTestResult &= !memcmp(pAggregatedPacket, pReceivedPacket, + sizeof(pReceivedPacket)); + + + return bTestResult; + } + + ///////////////////////////////////////////////////////////////////////////////// +}; + +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// + +class TLPAggregationLoopTest: public TLPAggregationTestFixture { +public: + + ///////////////////////////////////////////////////////////////////////////////// + + TLPAggregationLoopTest() + { + m_name = "TLPAggregationLoopTest"; + m_description = "TLP Aggregation Loop test - sends 5 packets and expects to" + "receives 1 aggregated packet a few times"; + } + + ///////////////////////////////////////////////////////////////////////////////// + + bool Run() + { + //The packets that will be sent + Byte pPackets[NUM_PACKETS][MAX_PACKET_SIZE]; + //The real sizes of the packets that will be sent + int pPacketsSizes[NUM_PACKETS]; + //Buffer for the packet that will be received + Byte pReceivedPacket[MAX_PACKET_SIZE]; + //Total size of all sent packets (this is the max size of the aggregated packet + //minus 2 bytes for each packet in the aggregated packet) + int nTotalPacketsSize = MAX_PACKET_SIZE - (2 * NUM_PACKETS); + //The expected aggregated packet + Byte pExpectedAggregatedPacket[MAX_PACKET_SIZE] = {0}; + + //initialize the packets + //example: for NUM_PACKETS = 5 and MAX_PACKET_SIZE = 1024: + //nTotalPacketsSize will be 1024 - 5*2 = 1014 + //packets[0] size will be 1014/5 = 202 bytes of 0 + //packets[1] size will be (1014 - 202) / 5 = 162 bytes of 1 + //packets[2] size will be (1014 - 201 - 162) / 5 = 130 bytes of 2 + //packets[3] size will be (1014 - 201 - 162 - 130) / 5 = 104 bytes of 3 + //packets[4] size will be 1014 - 201 - 162 - 130 - 104 = 416 bytes of 4 + for (int i = 0; i < NUM_PACKETS; i++) + { + if (NUM_PACKETS - 1 == i) + pPacketsSizes[i] = nTotalPacketsSize; + else + pPacketsSizes[i] = nTotalPacketsSize / NUM_PACKETS; + nTotalPacketsSize -= pPacketsSizes[i]; + for (int j = 0; j < pPacketsSizes[i]; j++) + pPackets[i][j] = i+ 16*test_num; + } + test_num++; + + //initializing the aggregated packet + int k = 0; + for (int i = 0; i < NUM_PACKETS; i++) + { + //the first 2 bytes are the packet length in little endian + pExpectedAggregatedPacket[k] = pPacketsSizes[i] & 0x00FF; + pExpectedAggregatedPacket[k+1] = pPacketsSizes[i] >> 8; + k += 2; + for (int j = 0; j < pPacketsSizes[i]; j++) + { + pExpectedAggregatedPacket[k] = pPackets[i][j]; + k++; + } + } + + for (int j = 0; j < AGGREGATION_LOOP; j++) + { + //send the packets + for (int i = 0; i < NUM_PACKETS; i++) + { + LOG_MSG_DEBUG("Sending packet %d into the USB pipe(%d bytes)\n", + i, pPacketsSizes[i]); + int nBytesSent = m_UsbNoAggToIpaPipeAgg.Send(pPackets[i], + pPacketsSizes[i]); + if (pPacketsSizes[i] != nBytesSent) + { + LOG_MSG_DEBUG("Sending packet %d into the USB pipe(%d bytes) " + "failed!\n", i, pPacketsSizes[i]); + return false; + } + } + + memset(pReceivedPacket, 0, sizeof(pReceivedPacket)); + //receive the aggregated packet + LOG_MSG_DEBUG("Reading packet from the USB pipe(%d bytes should be " + "there)\n", MAX_PACKET_SIZE); + int nBytesReceived = m_IpaToUsbPipeAggr.Receive(pReceivedPacket, + MAX_PACKET_SIZE); + if (MAX_PACKET_SIZE != nBytesReceived) + { + LOG_MSG_DEBUG("Receiving aggregated packet from the USB pipe(%d " + "bytes) failed!\n", MAX_PACKET_SIZE); + return false; + } + + //comparing the received packet to the aggregated packet + LOG_MSG_DEBUG("Checking sent.vs.received packet\n"); + + if (0 != memcmp(pExpectedAggregatedPacket, pReceivedPacket, + sizeof(pReceivedPacket))) + { + LOG_MSG_DEBUG("Comparison of packet %d failed!\n", j); + return false; + } + } + + return true; + } + + ///////////////////////////////////////////////////////////////////////////////// +}; + +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// + +class TLPAggregationTimeLimitTest: public TLPAggregationTestFixture { +public: + + ///////////////////////////////////////////////////////////////////////////////// + + TLPAggregationTimeLimitTest() + { + m_name = "TLPAggregationTimeLimitTest"; + m_description = "TLP Aggregation time limit test - sends 1 packet " + "smaller than the byte limit and receives 1 aggregated packet"; + } + + ///////////////////////////////////////////////////////////////////////////////// + + bool Run() + { + bool bTestResult = true; + //The packets that will be sent + Byte pPackets[TIME_LIMIT_NUM_PACKETS][MAX_PACKET_SIZE]; + //The real sizes of the packets that will be sent + int pPacketsSizes[TIME_LIMIT_NUM_PACKETS]; + //Buffer for the packet that will be received + Byte pReceivedPacket[MAX_PACKET_SIZE] = {0}; + //The expected aggregated packet + Byte pExpectedAggregatedPacket[MAX_PACKET_SIZE] = {0}; + //Size of aggregated packet + int nTotalPacketsSize = 0; + + //initialize the packets + for (int i = 0; i < TIME_LIMIT_NUM_PACKETS; i++) + { + pPacketsSizes[i] = i + 1; + nTotalPacketsSize += pPacketsSizes[i] + 2; //size of the packet + 2 bytes for length + for (int j = 0; j < pPacketsSizes[i]; j++) + pPackets[i][j] = i+ 16*test_num; + } + test_num++; + + //send the packets + for (int i = 0; i < TIME_LIMIT_NUM_PACKETS; i++) + { + LOG_MSG_DEBUG("Sending packet %d into the USB pipe(%d bytes)\n", i, + pPacketsSizes[i]); + int nBytesSent = m_UsbNoAggToIpaPipeAggTime.Send(pPackets[i], + pPacketsSizes[i]); + if (pPacketsSizes[i] != nBytesSent) + { + LOG_MSG_DEBUG("Sending packet %d into the USB pipe(%d bytes) " + "failed!\n", i, pPacketsSizes[i]); + return false; + } + } + + //receive the aggregated packet + LOG_MSG_DEBUG("Reading packet from the USB pipe(%d bytes should be " + "there)\n", nTotalPacketsSize); + int nBytesReceived = m_IpaToUsbPipeAggTime.Receive(pReceivedPacket, + nTotalPacketsSize); + if (nTotalPacketsSize != nBytesReceived) + { + LOG_MSG_DEBUG("Receiving aggregated packet from the USB pipe(%d " + "bytes) failed!\n", nTotalPacketsSize); + print_buff(pReceivedPacket, nBytesReceived); + return false; + } + + //initializing the aggregated packet + int k = 0; + for (int i = 0; i < TIME_LIMIT_NUM_PACKETS; i++) + { + //the first 2 bytes are the packet length in little endian + pExpectedAggregatedPacket[k] = pPacketsSizes[i] & 0x00FF; + pExpectedAggregatedPacket[k+1] = pPacketsSizes[i] >> 8; + k += 2; + for (int j = 0; j < pPacketsSizes[i]; j++) + { + pExpectedAggregatedPacket[k] = pPackets[i][j]; + k++; + } + } + + //comparing the received packet to the aggregated packet + LOG_MSG_DEBUG("Checking sent.vs.received packet\n"); + + bTestResult &= !memcmp(pExpectedAggregatedPacket, pReceivedPacket, + sizeof(pReceivedPacket)); + + return bTestResult; + } + + ///////////////////////////////////////////////////////////////////////////////// +}; + +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// + +class TLPAggregationByteLimitTest: public TLPAggregationTestFixture { +public: + + ///////////////////////////////////////////////////////////////////////////////// + + TLPAggregationByteLimitTest() + { + m_name = "TLPAggregationByteLimitTest"; + m_description = "TLP Aggregation byte limit test - sends 2 packets that together " + "are larger than the byte limit "; + } + + ///////////////////////////////////////////////////////////////////////////////// + + bool Run() + { + bool bTestResult = true; + //The packets that will be sent + Byte pPackets[2][MAX_PACKET_SIZE]; + //The real sizes of the packets that will be sent + int pPacketsSizes[2]; + //Buffer for the packet that will be received + Byte pReceivedPacket[2*MAX_PACKET_SIZE] = {0}; + //The expected aggregated packet + Byte pExpectedAggregatedPacket[2*MAX_PACKET_SIZE] = {0}; + //Size of aggregated packet + int nTotalPacketsSize = 0; + + //initialize the packets + for (int i = 0; i < 2; i++) + { + pPacketsSizes[i] = (MAX_PACKET_SIZE / 2) + 10; + nTotalPacketsSize += pPacketsSizes[i] + 2; + for (int j = 0; j < pPacketsSizes[i]; j++) + pPackets[i][j] = i+ 16*test_num; + } + test_num++; + + //send the packets + for (int i = 0; i < 2; i++) + { + LOG_MSG_DEBUG("Sending packet %d into the USB pipe(%d bytes)\n", i, + pPacketsSizes[i]); + int nBytesSent = m_UsbNoAggToIpaPipeAgg.Send(pPackets[i], + pPacketsSizes[i]); + if (pPacketsSizes[i] != nBytesSent) + { + LOG_MSG_DEBUG("Sending packet %d into the USB pipe(%d bytes) " + "failed!\n", i, pPacketsSizes[i]); + return false; + } + } + + //receive the aggregated packet + LOG_MSG_DEBUG("Reading packet from the USB pipe(%d bytes should be " + "there)\n", nTotalPacketsSize); + int nBytesReceived = m_IpaToUsbPipeAggr.Receive(pReceivedPacket, + nTotalPacketsSize); + if (nTotalPacketsSize != nBytesReceived) + { + LOG_MSG_DEBUG("Receiving aggregated packet from the USB pipe(%d" + " bytes) failed!\n", nTotalPacketsSize); + print_buff(pReceivedPacket, nBytesReceived); + return false; + } + + + //initializing the aggregated packet + int k = 0; + for (int i = 0; i < 2; i++) + { + //the first 2 bytes are the packet length in little endian + pExpectedAggregatedPacket[k] = pPacketsSizes[i] & 0x00FF; + pExpectedAggregatedPacket[k+1] = pPacketsSizes[i] >> 8; + k += 2; + for (int j = 0; j < pPacketsSizes[i]; j++) + { + pExpectedAggregatedPacket[k] = pPackets[i][j]; + k++; + } + } + + //comparing the received packet to the aggregated packet + LOG_MSG_DEBUG("Checking sent.vs.received packet\n"); + + bTestResult &= !memcmp(pExpectedAggregatedPacket, pReceivedPacket, + sizeof(pReceivedPacket)); + + return bTestResult; + } + + ///////////////////////////////////////////////////////////////////////////////// +}; + +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// + +class TLPAggregation2PipesTest: public TLPAggregationTestFixture { +public: + + ///////////////////////////////////////////////////////////////////////////////// + + TLPAggregation2PipesTest() + { + m_name = "TLPAggregation2PipesTest"; + m_description = "TLP Aggregation 2 pipes test - sends 3 packets from one pipe" + "and an aggregated packet made of 2 packets from another pipe and " + "receives 1 aggregated packet made of all 5 packets"; + } + + ///////////////////////////////////////////////////////////////////////////////// + + bool Run() + { + bool bTestResult = true; + //The packets that will be sent + Byte pPackets[NUM_PACKETS][MAX_PACKET_SIZE]; + //The real sizes of the packets that will be sent + int pPacketsSizes[NUM_PACKETS]; + //Buffer for the packet that will be received + Byte pReceivedPacket[MAX_PACKET_SIZE]; + //Total size of all sent packets (this is the max size of the aggregated packet + //minus 2 bytes for each packet in the aggregated packet) + int nTotalPacketsSize = MAX_PACKET_SIZE - (2 * NUM_PACKETS); + //The expected aggregated packet + Byte pExpectedAggregatedPacket[MAX_PACKET_SIZE] = {0}; + //The aggregated packet that will be sent + Byte pAggregatedPacket[MAX_PACKET_SIZE] = {0}; + //The size of the sent aggregated packet + int nAggregatedPacketSize = 0; + + //initialize the packets + //example: for NUM_PACKETS = 5 and MAX_PACKET_SIZE = 1024: + //nTotalPacketsSize will be 1024 - 5*2 = 1014 + //packets[0] size will be 1014/5 = 202 bytes of 0 + //packets[1] size will be (1014 - 202) / 5 = 162 bytes of 1 + //packets[2] size will be (1014 - 201 - 162) / 5 = 130 bytes of 2 + //packets[3] size will be (1014 - 201 - 162 - 130) / 5 = 104 bytes of 3 + //packets[4] size will be 1014 - 201 - 162 - 130 - 104 = 416 bytes of 4 + for (int i = 0; i < NUM_PACKETS; i++) + { + if (NUM_PACKETS - 1 == i) + pPacketsSizes[i] = nTotalPacketsSize; + else + pPacketsSizes[i] = nTotalPacketsSize / NUM_PACKETS; + nTotalPacketsSize -= pPacketsSizes[i]; + for (int j = 0; j < pPacketsSizes[i]; j++) + pPackets[i][j] = i+ 16*test_num; + } + test_num++; + + //initializing the aggregated packet + int k = 0; + for (int i = 0; i < 2; i++) + { + nAggregatedPacketSize += pPacketsSizes[i] + 2; + //the first 2 bytes are the packet length in little endian + pAggregatedPacket[k] = pPacketsSizes[i] & 0x00FF; + pAggregatedPacket[k+1] = pPacketsSizes[i] >> 8; + k += 2; + for (int j = 0; j < pPacketsSizes[i]; j++) + { + pAggregatedPacket[k] = pPackets[i][j]; + k++; + } + } + + //send the aggregated packet + LOG_MSG_DEBUG("Sending aggregated packet into the USB pipe(%d " + "bytes)\n", nAggregatedPacketSize); + int nBytesSent = m_UsbDeaggToIpaPipeAgg.Send(pAggregatedPacket, + nAggregatedPacketSize); + if (nAggregatedPacketSize != nBytesSent) + { + LOG_MSG_DEBUG("Sending aggregated packet into the USB pipe(%d " + "bytes) failed!\n", nAggregatedPacketSize); + return false; + } + + //send the packets + for (int i = 2; i < NUM_PACKETS; i++) + { + LOG_MSG_DEBUG("Sending packet %d into the USB pipe(%d bytes)\n", i, + pPacketsSizes[i]); + int nBytesSent = m_UsbNoAggToIpaPipeAgg.Send(pPackets[i], + pPacketsSizes[i]); + if (pPacketsSizes[i] != nBytesSent) + { + LOG_MSG_DEBUG("Sending packet %d into the USB pipe(%d bytes) " + "failed!\n", i, pPacketsSizes[i]); + return false; + } + } + + //receive the aggregated packet + LOG_MSG_DEBUG("Reading packet from the USB pipe(%d bytes should be " + "there)\n", MAX_PACKET_SIZE); + int nBytesReceived = m_IpaToUsbPipeAggr.Receive(pReceivedPacket, + MAX_PACKET_SIZE); + if (MAX_PACKET_SIZE != nBytesReceived) + { + LOG_MSG_DEBUG("Receiving aggregated packet from the USB pipe(%d " + "bytes) failed!\n", MAX_PACKET_SIZE); + print_buff(pReceivedPacket, nBytesReceived); + return false; + } + + + //initializing the aggregated packet + k = 0; + for (int i = 0; i < NUM_PACKETS; i++) + { + //the first 2 bytes are the packet length in little endian + pExpectedAggregatedPacket[k] = pPacketsSizes[i] & 0x00FF; + pExpectedAggregatedPacket[k+1] = pPacketsSizes[i] >> 8; + k += 2; + for (int j = 0; j < pPacketsSizes[i]; j++) + { + pExpectedAggregatedPacket[k] = pPackets[i][j]; + k++; + } + } + + //comparing the received packet to the aggregated packet + LOG_MSG_DEBUG("Checking sent.vs.received packet\n"); + + bTestResult &= !memcmp(pExpectedAggregatedPacket, pReceivedPacket, + sizeof(pReceivedPacket)); + + return bTestResult; + } + + ///////////////////////////////////////////////////////////////////////////////// +}; + +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// + +class TLPAggregationTimeLimitLoopTest: public TLPAggregationTestFixture { +public: + + ///////////////////////////////////////////////////////////////////////////////// + + TLPAggregationTimeLimitLoopTest() + { + m_name = "TLPAggregationTimeLimitLoopTest"; + m_description = "TLP Aggregation time limit loop test - sends 1 packet " + "smaller than the byte limit and receives 1 aggregated packets"; + } + + ///////////////////////////////////////////////////////////////////////////////// + + bool Run() + { + //The packets that will be sent + Byte pPackets[TIME_LIMIT_NUM_PACKETS][MAX_PACKET_SIZE]; + //The real sizes of the packets that will be sent + int pPacketsSizes[TIME_LIMIT_NUM_PACKETS]; + //Buffer for the packet that will be received + Byte pReceivedPacket[MAX_PACKET_SIZE] = {0}; + //The expected aggregated packet + Byte pExpectedAggregatedPacket[MAX_PACKET_SIZE] = {0}; + //Size of aggregated packet + int nTotalPacketsSize = 0; + + //initialize the packets + for (int i = 0; i < TIME_LIMIT_NUM_PACKETS; i++) + { + pPacketsSizes[i] = i + 1; + nTotalPacketsSize += pPacketsSizes[i] + 2; //size of the packet + 2 bytes for length + for (int j = 0; j < pPacketsSizes[i]; j++) + pPackets[i][j] = i+ 16*test_num; + } + test_num++; + + for (int n = 0; n < NUM_PACKETS; n++) + { + //send the packets + for (int i = 0; i < TIME_LIMIT_NUM_PACKETS; i++) + { + LOG_MSG_DEBUG("Sending packet %d into the USB pipe(%d bytes)\n", + i, pPacketsSizes[i]); + int nBytesSent = m_UsbNoAggToIpaPipeAggTime.Send(pPackets[i], + pPacketsSizes[i]); + if (pPacketsSizes[i] != nBytesSent) + { + LOG_MSG_DEBUG("Sending packet %d into the USB pipe(%d " + "bytes) failed!\n", i, pPacketsSizes[i]); + return false; + } + } + + //receive the aggregated packet + LOG_MSG_DEBUG("Reading packet from the USB pipe(%d bytes should be " + "there)\n", nTotalPacketsSize); + int nBytesReceived = m_IpaToUsbPipeAggTime.Receive(pReceivedPacket, + nTotalPacketsSize); + if (nTotalPacketsSize != nBytesReceived) + { + LOG_MSG_DEBUG("Receiving aggregated packet from the USB pipe(%d " + "bytes) failed!\n", nTotalPacketsSize); + print_buff(pReceivedPacket, nBytesReceived); + return false; + } + + //initializing the aggregated packet + int k = 0; + for (int i = 0; i < TIME_LIMIT_NUM_PACKETS; i++) + { + //the first 2 bytes are the packet length in little endian + pExpectedAggregatedPacket[k] = pPacketsSizes[i] & 0x00FF; + pExpectedAggregatedPacket[k+1] = pPacketsSizes[i] >> 8; + k += 2; + for (int j = 0; j < pPacketsSizes[i]; j++) + { + pExpectedAggregatedPacket[k] = pPackets[i][j]; + k++; + } + } + + //comparing the received packet to the aggregated packet + LOG_MSG_DEBUG("Checking sent.vs.received packet\n"); + if (0 != memcmp(pExpectedAggregatedPacket, pReceivedPacket, + sizeof(pReceivedPacket))) + { + LOG_MSG_DEBUG("Comparison of packet %d failed!\n", n); + return false; + } + } + + return true; + } + + ///////////////////////////////////////////////////////////////////////////////// +}; + + +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// + +//Those tests should be run with configuration number 8. +//Please look at the Fixture for more configurations update. +static TLPAggregationTest tlpAggregationTest; +static TLPDeaggregationTest tlpDeaggregationTest; +static TLPAggregationLoopTest tlpAggregationLoopTest; +static TLPAggregationTimeLimitTest tlpAggregationTimeLimitTest; +static TLPAggregationByteLimitTest tlpAggregationByteLimitTest; +static TLPAggregation2PipesTest tlpAggregation2PipesTest; +static TLPAggregationTimeLimitLoopTest tlpAggregationTimeLimitLoopTest; +static TLPDeaggregationAndAggregationTest tlpDeaggregationAndAggregationTest; + +///////////////////////////////////////////////////////////////////////////////// +// EOF //// +///////////////////////////////////////////////////////////////////////////////// diff --git a/qcom/opensource/dataipa/kernel-tests/TestBase.cpp b/qcom/opensource/dataipa/kernel-tests/TestBase.cpp new file mode 100644 index 0000000000..f7886ee1ec --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/TestBase.cpp @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2017,2020 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "TestBase.h" +#include "TestManager.h" +#include "linux/msm_ipa.h" + +////////////////////////////////////////////////////////////////////// + +TestBase::TestBase() : + m_runInRegression(true), + m_minIPAHwType(IPA_HW_v1_1), + m_maxIPAHwType(IPA_HW_MAX) +{ + m_mem_type = DFLT_NAT_MEM_TYPE; +} + +////////////////////////////////////////////////////////////////////// + +void TestBase::Register(TestBase &test) +{ + TestManager::GetInstance()->Register(test); +} + +////////////////////////////////////////////////////////////////////// + +//Empty default implementation, a test does not have to implement Setup() +bool TestBase::Setup() +{ + return true; +} + +////////////////////////////////////////////////////////////////////// + +//Empty default implementation, a test does not have to implement Teardown() +bool TestBase::Teardown() +{ + return true; +} + +////////////////////////////////////////////////////////////////////// + +TestBase::~TestBase() +{ + +} + +////////////////////////////////////////////////////////////////////// diff --git a/qcom/opensource/dataipa/kernel-tests/TestBase.h b/qcom/opensource/dataipa/kernel-tests/TestBase.h new file mode 100644 index 0000000000..47d0347d0d --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/TestBase.h @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2017,2020 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _TEST_BASE_H_ +#define _TEST_BASE_H_ + +#include +#include + +#define DFLT_NAT_MEM_TYPE "HYBRID" + +using namespace std; + +class TestBase +{ +public: + virtual bool Setup(); + /* Empty default implementation, + * a test does not have to implement Setup() + */ + virtual bool Run() = 0; + /* A test must implement Run() */ + virtual bool Teardown(); + /* Empty default implementation, + * a test does not have to implement Teardown() + */ + void Register(TestBase & test); + virtual ~TestBase(); + TestBase(); + void SetMemType( + const char* mem_type = DFLT_NAT_MEM_TYPE) + { + m_mem_type = mem_type; + } + + const char* m_mem_type; + string m_name; + string m_description; + vector < string > m_testSuiteName; + /* Every test can belong to multiple test suites */ + bool m_runInRegression; + /* Should this test be run in a regression test ? (Default is yes) */ + int m_minIPAHwType; + /* The minimal IPA HW version which this test can run on */ + int m_maxIPAHwType; + /* The maximal IPA HW version which this test can run on */ +}; +#endif diff --git a/qcom/opensource/dataipa/kernel-tests/TestManager.cpp b/qcom/opensource/dataipa/kernel-tests/TestManager.cpp new file mode 100644 index 0000000000..268f7391e8 --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/TestManager.cpp @@ -0,0 +1,396 @@ +/* + * Copyright (c) 2017-2018,2020 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include // std::find +#include // std::vector +#include +#include +#include +#include +#include "TestManager.h" +#include "TestsUtils.h" +#include +#include +#include "ipa_test_module.h" +#include + +using namespace std; + +/* Global static pointer used to ensure a single instance of the class. */ +TestManager* TestManager::m_instance = NULL; + + +#ifdef HAVE_LIBXML + +TestsXMLResult::TestsXMLResult() +{ + xmlNodePtr node; + + // initialize xml report document and add a root to node it + m_XML_doc_ptr = xmlNewDoc(BAD_CAST "1.0"); + if (m_XML_doc_ptr == NULL){ + printf("error on allocation xml doc\n"); + exit(-1); + } + + node = xmlNewNode(NULL, BAD_CAST "testsuites"); + if (!node) { + printf("failed to allocate XML node\n"); + exit (-1); + } + xmlDocSetRootElement(m_XML_doc_ptr, node); +} + +TestsXMLResult::~TestsXMLResult() +{ + if (m_XML_doc_ptr) + xmlFreeDoc(m_XML_doc_ptr); + xmlCleanupParser(); +} + +/* + * Returns xmlPtr to testsuite element node, if doesn't exist + * creates one by that name + */ +xmlNodePtr TestsXMLResult::GetSuiteElement(const string& suite_name) +{ + xmlNodePtr root_node, suite_node, new_child_node; + + if (!m_XML_doc_ptr) { + printf("no xml document\n"); + return NULL; + } + + root_node = xmlDocGetRootElement(m_XML_doc_ptr); + suite_node = xmlFirstElementChild(root_node); + while (suite_node) + { + /* get suite name */ + xmlChar *val = xmlGetProp(suite_node, BAD_CAST "name"); + + /* change xmlCHar* to string */ + string node_suite_name(reinterpret_cast(val)); + xmlFree(val); //free val allocated memory + + if (node_suite_name == suite_name) + return suite_node; + else suite_node = suite_node->next; + } + + /* If we got here no suitable suite name was found, + * so we create a new suite element and return it + */ + new_child_node = xmlNewChild(root_node, NULL, BAD_CAST "testsuite", BAD_CAST ""); + if (!new_child_node) { + printf("failed creating new XML node\n"); + return NULL; + } + xmlSetProp(new_child_node, BAD_CAST "name", BAD_CAST suite_name.c_str()); + + return xmlGetLastChild(root_node); +} + +/* + * Creates new testcase element + */ +void TestsXMLResult::AddTestcase(const string &suite_nm, const string &test_nm, + double runtime, bool pass) +{ + xmlNodePtr suite_node, new_testcase, fail_node; + ostringstream runtime_str; + + if (!suite_nm.size() || !test_nm.size()) { + printf("Input error: suite_nm size %d , test_nm size %d", + suite_nm.size(), test_nm.size()); + exit(-1); + } + + suite_node = GetSuiteElement(suite_nm); + if (!suite_node) { + printf("failed getting suite element\n"); + exit(-1); + } + + /* Create new testcase element as son to suite element */ + new_testcase = xmlNewChild(suite_node, NULL, BAD_CAST "testcase", NULL); + if (!new_testcase) { + printf("failed creating XML new child for testcase\n"); + exit(-1); + } + xmlSetProp(new_testcase, BAD_CAST "name", BAD_CAST test_nm.c_str()); + + runtime_str << runtime; + xmlSetProp(new_testcase, BAD_CAST "time", BAD_CAST runtime_str.str().c_str()); + + if (!pass) { + fail_node = xmlNewChild(new_testcase, NULL, BAD_CAST "failure", NULL); + if (!fail_node) { + printf("failed creating fail node\n"); + exit(-1); + } + } +} + +/* + * Prints the XML tree to file + */ +void TestsXMLResult::GenerateXMLReport(void) +{ + if (!m_XML_doc_ptr) { + printf("no xml document\n"); + return; + } + + xmlSaveFormatFileEnc(XUNIT_REPORT_PATH_AND_NAME, m_XML_doc_ptr, "UTF-8", 1); +} + +#else /* HAVE_LIBXML */ + +TestsXMLResult::TestsXMLResult() {} +TestsXMLResult::~TestsXMLResult() {} +void TestsXMLResult::AddTestcase(const string &suite_nm, const string &test_nm, + double runtime, bool pass) {} +void TestsXMLResult::GenerateXMLReport(void) +{ + printf("No XML support\n"); +} + +#endif /* HAVE_LIBXML */ + +TestManager::TestManager( + const char* nat_mem_type_ptr) +{ + m_testList.clear(); + m_failedTestsNames.clear(); + m_numTestsFailed = 0; + m_numTestsRun = 0; + FetchIPAHwType(); + m_nat_mem_type_ptr = nat_mem_type_ptr; +} + +//////////////////////////////////////////////////////////////////////////////////////////// + +TestManager::~TestManager() +{ + m_testList.clear(); +} + +//////////////////////////////////////////////////////////////////////////////////////////// + +TestManager* TestManager::GetInstance( + const char* nat_mem_type_ptr) +{ + if (!m_instance) // Only allow one instance of class to be generated. + m_instance = new TestManager(nat_mem_type_ptr); + + return m_instance; +} + +//////////////////////////////////////////////////////////////////////////////////////////// + +void TestManager::Register(TestBase &test) +{ + m_testList.push_back(&test); +} + +//////////////////////////////////////////////////////////////////////////////////////////// + +bool TestManager::Run(vector testSuiteList, vector testNameList) +{ + TestBase *test = NULL; + bool pass = true; + vector::iterator testIter; + vector::iterator testSuiteIter; + bool runTest = false; + clock_t begin_test_clk, end_test_clk; + double test_runtime_sec = 0, total_time_sec = 0; + TestsXMLResult xml_res; + + if (m_testList.size() == 0) + return false; + + /* PrintRegisteredTests(); */ + + for (unsigned int i = 0 ; i < m_testList.size() ; i++ , runTest = false) { + pass = true; + test = m_testList[i]; + + // Run only tests from the list of test suites which is stated in the command + // line. In case the list is empty, run all tests. + if (testSuiteList.size() > 0) { + for (unsigned int j = 0; j < test->m_testSuiteName.size(); j++) { + testSuiteIter = find(testSuiteList.begin(), testSuiteList.end(), test->m_testSuiteName[j]); + if (testSuiteIter != testSuiteList.end()) { + runTest = true; + } + } + } + + // We also support test by name + if (testNameList.size() > 0) { + testIter = find(testNameList.begin(), testNameList.end(), test->m_name); + if (testIter != testNameList.end()) + runTest = true; + } + + // Run the test only if it's applicable to the current IPA HW type / version + if (runTest) { + if (!(m_IPAHwType >= test->m_minIPAHwType && m_IPAHwType <= test->m_maxIPAHwType)) + runTest = false; + } + + if (!runTest) + continue; + + printf("\n\nExecuting test %s\n", test->m_name.c_str()); + printf("Description: %s\n", test->m_description.c_str()); + + printf("Setup()\n"); + begin_test_clk = clock(); + test->SetMemType(GetMemType()); + pass &= test->Setup(); + + //In case the test's setup did not go well it will be a bad idea to try and run it. + if (true == pass) + { + printf("Run()\n"); + pass &= test->Run(); + } + + printf("Teardown()\n"); + pass &= test->Teardown(); + + end_test_clk = clock(); + test_runtime_sec = double(end_test_clk - begin_test_clk) / CLOCKS_PER_SEC; + total_time_sec += test_runtime_sec; + + if (pass) + { + m_numTestsRun++; + PrintSeparator(test->m_name.size()); + printf("Test %s PASSED ! time:%g\n", test->m_name.c_str(), test_runtime_sec); + PrintSeparator(test->m_name.size()); + } + else + { + m_numTestsRun++; + m_numTestsFailed++; + m_failedTestsNames.push_back(test->m_name); + PrintSeparator(test->m_name.size()); + printf("Test %s FAILED ! time:%g\n", test->m_name.c_str(), test_runtime_sec); + PrintSeparator(test->m_name.size()); + } + + xml_res.AddTestcase(test->m_testSuiteName[0], test->m_name, test_runtime_sec, pass); + } // for + + // Print summary + printf("\n\n"); + printf("==================== RESULTS SUMMARY ========================\n"); + printf("%zu tests were run, %zu failed, total time:%g.\n", m_numTestsRun, m_numTestsFailed, total_time_sec); + if (0 != m_numTestsFailed) { + printf("Failed tests list:\n"); + for (size_t i = 0; i < m_numTestsFailed; i++) { + printf(" %s\n", m_failedTestsNames[i].c_str()); + m_failedTestsNames.pop_back(); + } + } + printf("=============================================================\n"); + xml_res.GenerateXMLReport(); + + return pass; +} + +//////////////////////////////////////////////////////////////////////////////////////////// + +void TestManager::PrintSeparator(size_t len) +{ + string separator; + + for (size_t i = 0; i < len + 15; i++) { + separator += "-"; + } + + printf("%s\n", separator.c_str()); +} + +//////////////////////////////////////////////////////////////////////////////////////////// + +TestManager::TestManager(TestManager const&) +{ + +} + +//////////////////////////////////////////////////////////////////////////////////////////// + +TestManager& TestManager::operator=(TestManager const&) +{ + return *m_instance; +} + +//////////////////////////////////////////////////////////////////////////////////////////// + +void TestManager::PrintRegisteredTests() +{ + printf("Test list: (%zu registered)\n", m_testList.size()); + for (unsigned int i = 0; i < m_testList.size(); i++) { + printf("%d) name = %s, suite name = %s, regression = %d\n", i, m_testList[i]->m_name.c_str(), + m_testList[i]->m_testSuiteName[0].c_str(), m_testList[i]->m_runInRegression); + } +} + +//////////////////////////////////////////////////////////////////////////////////////////// + +void TestManager::FetchIPAHwType() +{ + int fd; + + // Open ipa_test device node + fd = open("/dev/ipa_test" , O_RDONLY); + if (fd < 0) { + printf("Failed opening %s. errno %d: %s\n", "/dev/ipa_test", errno, strerror(errno)); + m_IPAHwType = IPA_HW_None; + return; + } + + printf("%s(), fd is %d\n", __FUNCTION__, fd); + + m_IPAHwType = (enum ipa_hw_type)ioctl(fd, IPA_TEST_IOC_GET_HW_TYPE); + if (-1 == m_IPAHwType) { + printf("%s(), IPA_TEST_IOC_GET_HW_TYPE ioctl failed\n", __FUNCTION__); + m_IPAHwType = IPA_HW_None; + } + + printf("%s(), IPA HW type (version) = %d\n", __FUNCTION__, m_IPAHwType); + close(fd); +} + + +//////////////////////////////////////////////////////////////////////////////////////////// diff --git a/qcom/opensource/dataipa/kernel-tests/TestManager.h b/qcom/opensource/dataipa/kernel-tests/TestManager.h new file mode 100644 index 0000000000..c106ad3ebb --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/TestManager.h @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2017-2018,2020 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _TEST_MANAGER_H_ +#define _TEST_MANAGER_H_ + +#include "TestBase.h" +#include +#include +#include "linux/msm_ipa.h" + +#ifdef HAVE_LIBXML +#include +#include +#endif + +using namespace std; + + +class TestsXMLResult +{ +public: + TestsXMLResult(); + ~TestsXMLResult(); + void AddTestcase(const string &suite_nm, const string &test_nm, + double runtime, bool pass); + void GenerateXMLReport(void); +private: +#ifdef HAVE_LIBXML + xmlNodePtr GetSuiteElement(const string& suite_name); + xmlDocPtr m_XML_doc_ptr; +#endif +}; + +class TestManager /* Singleton */ +{ +public: + static TestManager *GetInstance( + const char* nat_mem_type_ptr = DFLT_NAT_MEM_TYPE); + ~TestManager(); + void Register(TestBase & test); + bool Setup(); + /* This is the place to put initialization + * for the whole test framework + */ + bool Run(vector testSuiteList, + vector testNameList); + /* This function will run all the tests in the system */ + bool Teardown(); + /* This is the place to put tear-down for the whole test framework */ + vector < TestBase * > m_testList; + /* Holds pointers to all of the tests in the system */ + + enum ipa_hw_type GetIPAHwType() {return m_IPAHwType;} + const char* GetMemType() { return m_nat_mem_type_ptr; } + +private: + TestManager( + const char* nat_mem_type_ptr = DFLT_NAT_MEM_TYPE); + TestManager(TestManager const &); + TestManager & operator = (TestManager const &); + void PrintSeparator(size_t len); + void PrintRegisteredTests(); + void BuildRegressionTestSuite(); + void FetchIPAHwType(); + + static TestManager *m_instance; + + size_t m_numTestsRun; + size_t m_numTestsFailed; + enum ipa_hw_type m_IPAHwType; + const char* m_nat_mem_type_ptr; + + vector < string > m_failedTestsNames; +}; + +#endif diff --git a/qcom/opensource/dataipa/kernel-tests/TestsUtils.cpp b/qcom/opensource/dataipa/kernel-tests/TestsUtils.cpp new file mode 100644 index 0000000000..52390a3269 --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/TestsUtils.cpp @@ -0,0 +1,1873 @@ +/* + * Copyright (c) 2017-2020 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Changes from Qualcomm Innovation Center are provided under the following license: + * + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * * Neither the name of Qualcomm Innovation Center, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "TestsUtils.h" +#include "InterfaceAbstraction.h" +#include "Constants.h" +#include "Pipe.h" + +using namespace std; +/////////////////////////////////////////////////////////////////////////////// + +extern Logger g_Logger; + +static uint8_t IPv4Packet[IP4_PACKET_SIZE] = { + 0x45, 0x00, 0x00, 0x46, + 0x45, 0x00, 0x00, 0x00, + 0xff, 0x06, 0xf5, 0xfd,// Protocol = 06 (TCP) + 0xc0, 0xa8, 0x02, 0x13,// IPv4 SRC Addr 192.168.2.19 + 0xc0, 0xa8, 0x02, 0x68,// IPv4 DST Addr 192.168.2.104 + 0x04, 0x57, 0x08, 0xae, + 0x00, 0x00, 0x30, 0x34, + 0x00, 0x00, 0x00, 0x50, + 0x50, 0xc1, 0x40, 0x00, + 0xab, 0xc9, 0x00, 0x00, + 0x00, 0xaa, 0xaa, 0xaa, + 0xbb, 0xbb, 0xbb, 0xbb, + 0xbb, 0xbb, 0xbb, 0xbb, + 0xbb, 0xbb, 0xbb, 0xbb, + 0xbb, 0xbb, 0xbb, 0xbb, + 0xbb, 0xbb, 0xbb, 0xbb, + 0xbb, 0xbb, 0xbb, 0xbb, + 0xbb, 0xbb +}; + +static uint8_t IPv6Packet[] = { + 0x60, 0x00, 0x00, 0x00, + 0x00, 0x1c, 0x06, 0x01, // Protocol = 6 (TCP) + 0xfe, 0x80, 0x00, 0x00, // source address (16B) + 0x00, 0x00, 0x00, 0x00, + 0xd9, 0xf9, 0xce, 0x5e, + 0x02, 0xec, 0x32, 0x99, + 0xff, 0x02, 0x00, 0x00, // dst address (16B) + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x0c, + 0x12, 0x34, 0x12, 0x34, // port src = 0x1234 dest = 0x1234 + 0x00, 0x14, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x60, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, // options + 0xda, 0x7a, 0xda, 0x7a // payload +}; + +static uint8_t IPv6PacketFragExtHdr[] = { + 0x60, 0x00, 0x00, 0x00, + 0x00, 0x24, 0x2C, 0x01, // Next header = FRAGMENT HEADER(44) + 0xfe, 0x80, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0xd9, 0xf9, 0xce, 0x5e, + 0x02, 0xec, 0x32, 0x99, + 0xff, 0x02, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x0c, + 0x06, 0x00, 0x00, 0x00, // fragment header, Protocol = 6 (TCP) + 0x00, 0x00, 0x00, 0x00, + 0x12, 0x34, 0x12, 0x34, // port src = 0x1234 dest = 0x1234 + 0x00, 0x14, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x60, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0xda, 0x7a, 0xda, 0x7a // payload +}; + +static const uint8_t Eth2IPv4Packet[] = +{ + // ETH2 - 14 bytes + 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0x11, // ETH2 DST + 0x22, 0xee, 0xdd, 0xcc, 0xbb, 0xaa, // ETH2 SRC + 0x08, 0x00, // ETH2 TYPE IPv4 - ETH_P_IP 0x0800 + + // IPv4 + 0x45, 0x00, 0x00, 0x29, + 0x00, 0x00, 0x40, 0x00, + 0xff, 0x06, 0xf5, 0xfd, // Protocol = 06 (TCP) + 0xc0, 0xa8, 0x02, 0x13, // IPv4 SRC Addr 192.168.2.19 + 0xc0, 0xa8, 0x02, 0x68, // IPv4 DST Addr 192.168.2.104 + 0x04, 0x57, 0x08, 0xae, + 0x00, 0x00, 0x30, 0x34, + 0x00, 0x00, 0x00, 0x50, + 0x50, 0xc1, 0x40, 0x00, + 0xab, 0xc9, 0x00, 0x00, + 0x00 +}; + +static const uint8_t Eth2IPv6Packet[] = +{ + // ETH2 - 14 bytes + 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0x11, // ETH2 DST + 0x22, 0xee, 0xdd, 0xcc, 0xbb, 0xaa, // ETH2 SRC + 0x86, 0xdd, // ETH2 TYPE IPv6 - ETH_P_IPV6 x86DD + + // IPv6 + 0x60, 0x00, 0x00, 0x00, + 0x02, 0x12, 0x11, 0x01, + 0xfe, 0x80, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0xd9, 0xf9, 0xce, 0x5e, + 0x02, 0xec, 0x32, 0x99, + 0xff, 0x02, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x0c +}; + +static const uint8_t WLANEth2IPv4Packet[] = +{ + // WLAN + 0xa1, 0xb2, 0xc3, 0xd4, // WLAN hdr + + // ETH2 - 14 bytes + 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0x11, // ETH2 DST + 0x22, 0xee, 0xdd, 0xcc, 0xbb, 0xaa, // ETH2 SRC + 0x08, 0x00, // ETH2 TYPE IPv4 - ETH_P_IP 0x0800 + + // IPv4 + 0x45, 0x00, 0x00, 0x29, + 0x00, 0x00, 0x40, 0x00, + 0xff, 0x06, 0xf5, 0xfd, // Protocol = 06 (TCP) + 0xc0, 0xa8, 0x02, 0x13, // IPv4 SRC Addr 192.168.2.19 + 0xc0, 0xa8, 0x02, 0x68, // IPv4 DST Addr 192.168.2.104 + 0x04, 0x57, 0x08, 0xae, + 0x00, 0x00, 0x30, 0x34, + 0x00, 0x00, 0x00, 0x50, + 0x50, 0xc1, 0x40, 0x00, + 0xab, 0xc9, 0x00, 0x00, + 0x00 +}; + +static const uint8_t WLAN802_3IPv4Packet[] = +{ + // WLAN + 0xa1, 0xb2, 0xc3, 0xd4, // WLAN hdr + + // 802_3 - 26 bytes + 0xa5, 0xb6, 0xc7, 0xd8, // ROME proprietary header + 0xa0, 0xb1, 0xc2, 0xd3, 0xe4, 0x33, // 802_3 DST + 0x44, 0xb2, 0xc3, 0xd4, 0xe5, 0xf6, // 802_3 SRC + 0x00, IP4_PACKET_SIZE, // 802_3 length + 0x04, 0x15, 0x26, 0x37, 0x48, 0x59, // LLC/SNAP + 0x08, 0x00, // Ethrtype - 0x0800 + + // IPv4 + 0x45, 0x00, 0x00, 0x29, + 0x00, 0x00, 0x40, 0x00, + 0xff, 0x06, 0xf5, 0xfd, // Protocol = 06 (TCP) + 0xc0, 0xa8, 0x02, 0x13, // IPv4 SRC Addr 192.168.2.19 + 0xc0, 0xa8, 0x02, 0x68, // IPv4 DST Addr 192.168.2.104 + 0x04, 0x57, 0x08, 0xae, + 0x00, 0x00, 0x30, 0x34, + 0x00, 0x00, 0x00, 0x50, + 0x50, 0xc1, 0x40, 0x00, + 0xab, 0xc9, 0x00, 0x00, + 0x00 +}; + +static uint8_t IPv4_TCP_No_Payload_Packet[] = { + 0x45, 0x00, 0x00, 0x28, // Total length is 40 + 0x00, 0x00, 0x40, 0x00, + 0xff, 0x06, 0xf5, 0xfd, // Protocol = 06 (TCP) + 0xc0, 0xa8, 0x02, 0x13, // IPv4 SRC Addr 192.168.2.19 + 0xc0, 0xa8, 0x02, 0xc8, // IPv4 DST Addr 192.168.2.200 + 0x04, 0x57, 0x08, 0xae, + 0x00, 0x00, 0x30, 0x34, + 0x00, 0x00, 0x00, 0x50, + 0x50, 0xc1, 0x40, 0x00, + 0xab, 0xc9, 0x00, 0x00, +}; + +static uint8_t IPv6_TCP_No_Payload_Packet[] = { + 0x60, 0x00, 0x00, 0x00, + 0x00, 0x14, 0x06, 0x01, // Payload is 20 Bytes (TCP header only) + 0xfe, 0x80, 0x00, 0x00, // SRC Addr + 0x00, 0x00, 0x00, 0x00, + 0xd9, 0xf9, 0xce, 0x5e, + 0x02, 0xec, 0x32, 0x99, + 0xff, 0x02, 0x00, 0x00, // DST Addr + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x4b, + 0x04, 0x57, 0x08, 0xae, // TCP header + 0x00, 0x00, 0x30, 0x34, + 0x00, 0x00, 0x00, 0x50, + 0x50, 0xc1, 0x40, 0x00, + 0xab, 0xc9, 0x00, 0x00, +}; + +static const uint8_t Eth2IPv4Packet802_1Q_tag[] = +{ + // ETH2 + 8021Q - 14 + 4 bytes + 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0x11, // ETH2 DST + 0x22, 0xee, 0xdd, 0xcc, 0xbb, 0xaa, // ETH2 SRC + 0x81, 0x00, 0x20, 0x03, // 802.1Q header with VLAN ID = 3 + 0x08, 0x00, // ETH2 TYPE IPv4 - ETH_P_IP 0x0800 + // IPv4 + 0x45, 0x00, 0x00, 0x29, + 0x00, 0x00, 0x40, 0x00, + 0xff, 0x06, 0xf5, 0xfd, // Protocol = 06 (TCP) + 0xc0, 0xa8, 0x02, 0x13, // IPv4 SRC Addr 192.168.2.19 + 0xc0, 0xa8, 0x02, 0x68, // IPv4 DST Addr 192.168.2.104 + 0x04, 0x57, 0x08, 0xae, + 0x00, 0x00, 0x30, 0x34, + 0x00, 0x00, 0x00, 0x50, + 0x50, 0xc1, 0x40, 0x00, + 0xab, 0xc9, 0x00, 0x00, + 0x00 +}; + +static struct ipa_test_config_header *current_configuration = NULL; + +/////////////////////////////////////////////////////////////////////////////// +/** +*@brief Function loads a default IPv4 / IPv6 Packet +* +*@param [in] eIP - Type of Packet to load (IPA_IP_v4 / IPA_IP_v6) +*@param [in] pBuffer - pointer to the destination buffer +*@param [in,out] nMaxSize - The size of the buffer.*Upon function return, +* the total number of bytes copied will be stored in this parameter. +*@return boolean indicating whether the operation completed successfully or not. +*@details Function loads a default IPv4 / IPv6 packet into pBuffer. +*/ +bool LoadDefaultPacket( + enum ipa_ip_type eIP, + enum ipv6_ext_hdr_type extHdrType, + uint8_t *pBuffer, + size_t &nMaxSize) +{ + if (IPA_IP_v4 == eIP) { + if (nMaxSize < sizeof(IPv4Packet)) + { + LOG_MSG_ERROR("Buffer is smaller than %d, no Data was copied.",sizeof(IPv4Packet)); + return false; + } + memcpy(pBuffer,IPv4Packet, sizeof(IPv4Packet)); + nMaxSize = sizeof(IPv4Packet); + return true; + } else { + if (extHdrType == FRAGMENT) + { + if (nMaxSize < sizeof(IPv6PacketFragExtHdr)) + { + LOG_MSG_ERROR("Buffer is smaller than %d, no Data was copied.",sizeof(IPv6PacketFragExtHdr)); + return false; + } + memcpy(pBuffer,IPv6PacketFragExtHdr, sizeof(IPv6PacketFragExtHdr)); + nMaxSize = sizeof(IPv6PacketFragExtHdr); + + } + else + { + if (nMaxSize < sizeof(IPv6Packet)) + { + LOG_MSG_ERROR("Buffer is smaller than %d, no Data was copied.",sizeof(IPv6Packet)); + return false; + } + memcpy(pBuffer,IPv6Packet, sizeof(IPv6Packet)); + nMaxSize = sizeof(IPv6Packet); + } + return true; + } +} + +bool LoadDefaultPacket(enum ipa_ip_type eIP, uint8_t *pBuffer, size_t &nMaxSize) +{ + return LoadDefaultPacket(eIP, NONE, pBuffer, nMaxSize); +} + +bool LoadNoPayloadPacket(enum ipa_ip_type eIP, uint8_t *pBuffer, size_t &nMaxSize) +{ + if (IPA_IP_v4 == eIP) { + if (nMaxSize < sizeof(IPv4_TCP_No_Payload_Packet)) + { + LOG_MSG_ERROR("Buffer is smaller than %zu, no Data was copied.", + sizeof(IPv4_TCP_No_Payload_Packet)); + return false; + } + memcpy(pBuffer, IPv4_TCP_No_Payload_Packet, sizeof(IPv4_TCP_No_Payload_Packet)); + nMaxSize = sizeof(IPv4_TCP_No_Payload_Packet); + } else { + if (nMaxSize < sizeof(IPv6_TCP_No_Payload_Packet)) + { + LOG_MSG_ERROR("Buffer is smaller than %zu, no Data was copied.", + sizeof(IPv6_TCP_No_Payload_Packet)); + return false; + } + memcpy(pBuffer, IPv6_TCP_No_Payload_Packet, sizeof(IPv6_TCP_No_Payload_Packet)); + nMaxSize = sizeof(IPv6_TCP_No_Payload_Packet); + } + + return true; +} + +bool LoadDefaultEth2Packet( + enum ipa_ip_type eIP, + uint8_t *pBuffer, + size_t &nMaxSize) +{ + if (IPA_IP_v4 == eIP) { + if (nMaxSize < sizeof(Eth2IPv4Packet)) + { + LOG_MSG_ERROR( + "Buffer is smaller than %d, " + "no data was copied.", + sizeof(Eth2IPv4Packet)); + return false; + } + memcpy(pBuffer,Eth2IPv4Packet, + sizeof(Eth2IPv4Packet)); + nMaxSize = sizeof(Eth2IPv4Packet); + } + else + { + if (nMaxSize < sizeof(Eth2IPv6Packet)) + { + LOG_MSG_ERROR( + "Buffer is smaller than %d, " + "no data was copied.", + sizeof(Eth2IPv6Packet)); + return false; + } + memcpy(pBuffer,Eth2IPv6Packet, + sizeof(Eth2IPv6Packet)); + nMaxSize = sizeof(Eth2IPv6Packet); + } + + return true; +} + +bool LoadDefaultWLANEth2Packet( + enum ipa_ip_type eIP, + uint8_t *pBuffer, + size_t &nMaxSize) +{ + if (IPA_IP_v4 == eIP) { + if (nMaxSize < sizeof(WLANEth2IPv4Packet)) + { + LOG_MSG_ERROR( + "Buffer is smaller than %d, " + "no data was copied.", + sizeof(WLANEth2IPv4Packet)); + return false; + } + memcpy(pBuffer,WLANEth2IPv4Packet, + sizeof(WLANEth2IPv4Packet)); + nMaxSize = sizeof(WLANEth2IPv4Packet); + } + else + { + LOG_MSG_ERROR("%s isn't implemented " + "for IPv6 - do it yourself :-)", + __FUNCTION__); + return false; + } + + return true; +} + +bool LoadDefaultWLAN802_32Packet( + enum ipa_ip_type eIP, + uint8_t *pBuffer, + size_t &nMaxSize) +{ + if (IPA_IP_v4 == eIP) { + if (nMaxSize < sizeof(WLAN802_3IPv4Packet)) + { + LOG_MSG_ERROR( + "Buffer is smaller than %d, " + "no data was copied.", + sizeof(WLAN802_3IPv4Packet)); + return false; + } + memcpy(pBuffer,WLAN802_3IPv4Packet, + sizeof(WLAN802_3IPv4Packet)); + nMaxSize = sizeof(WLAN802_3IPv4Packet); + } + else + { + LOG_MSG_ERROR("%s isn't implemented" + " for IPv6 - do it yourself :-)", + __FUNCTION__); + return false; + } + + return true; +} + +bool LoadDefault802_1Q( + enum ipa_ip_type eIP, + uint8_t *pBuffer, + size_t &nMaxSize) +{ + if (IPA_IP_v4 == eIP) { + if (nMaxSize < sizeof(Eth2IPv4Packet802_1Q_tag)) { + LOG_MSG_ERROR( + "Buffer is smaller than %d, " + "no data was copied.", + sizeof(Eth2IPv4Packet802_1Q_tag)); + return false; + } + memcpy(pBuffer, Eth2IPv4Packet802_1Q_tag, + sizeof(Eth2IPv4Packet802_1Q_tag)); + nMaxSize = sizeof(Eth2IPv4Packet802_1Q_tag); + } else { + LOG_MSG_ERROR("%s isn't implemented" + " for IPv6 - do it yourself :-)", + __FUNCTION__); + return false; + } + + return true; +} + +bool SendReceiveAndCompare(InterfaceAbstraction *pSink, uint8_t* pSendBuffer, size_t nSendBuffSize, + InterfaceAbstraction *pSource, uint8_t* pExpectedBuffer, size_t nExpectedBuffSize) +{ + LOG_MSG_STACK("Entering Function"); + bool bRetVal = true; + uint8_t * pRxBuff = new uint8_t[2*(nExpectedBuffSize+1)]; + size_t nReceivedBuffSize = 0; + size_t j; + + // Send buffer to pSink + bRetVal = pSink->SendData((Byte *) pSendBuffer, nSendBuffSize); + if (!bRetVal) + { + LOG_MSG_ERROR("SendData (pOutputBuffer=0x%p) failed",pSendBuffer); + goto bail; + } + + // Receive buffer from pSource + if (NULL == pRxBuff) + { + LOG_MSG_ERROR("Failed to allocated pRxBuff[%d]",2*(nExpectedBuffSize+1)); + goto bail; + } + nReceivedBuffSize = pSource->ReceiveData(pRxBuff, 2*(nExpectedBuffSize+1)); // We cannot overflow here. + LOG_MSG_INFO("Received %d bytes on %s.", nReceivedBuffSize, pSource->m_fromChannelName.c_str()); + if (0 > nReceivedBuffSize) + { + bRetVal = false; + goto bail; + } + + {// Logging Expected and Received buffers + char aExpectedBufferStr[3*nExpectedBuffSize+1]; + char aRecievedBufferStr[3*nReceivedBuffSize+1]; + memset(aExpectedBufferStr,0,3*nExpectedBuffSize+1); + memset(aRecievedBufferStr,0,3*nReceivedBuffSize+1); + + for(j = 0; j < nExpectedBuffSize; j++) + snprintf(&aExpectedBufferStr[3*j], 3*nExpectedBuffSize+1 - (3*j + 1), " %02X", pExpectedBuffer[j]); + for(j = 0; j < nReceivedBuffSize; j++) + snprintf(&aRecievedBufferStr[3*j], 3*nReceivedBuffSize+1 - (3*j + 1), " %02X", pRxBuff[j]); + LOG_MSG_INFO("\nExpected Value (%d)\n%s\n, Received Value(%d)\n%s\n",nExpectedBuffSize,aExpectedBufferStr,nReceivedBuffSize,aRecievedBufferStr); + } + + //Comparing Expected and received sizes + if (nExpectedBuffSize != nReceivedBuffSize) + { + LOG_MSG_INFO("Buffers' Size differ: expected(%d), Received(%d)",nExpectedBuffSize,nReceivedBuffSize); + bRetVal = false; + goto bail; + } + + bRetVal = !memcmp((void*)pRxBuff, (void*)pExpectedBuffer, nExpectedBuffSize); + LOG_MSG_INFO("Buffers %s ",bRetVal?"MATCH":"MISMATCH"); + + + LOG_MSG_INFO("Verify that pipe is Empty"); + nReceivedBuffSize = pSource->ReceiveData(pRxBuff, 2*(nExpectedBuffSize+1)); // We cannot overflow here. + while (nReceivedBuffSize){ + char aRecievedBufferStr[3*nReceivedBuffSize+1]; + bRetVal = false; + LOG_MSG_ERROR("More Data in Pipe!\nReceived %d bytes on %s.", nReceivedBuffSize, pSource->m_fromChannelName.c_str()); + memset(aRecievedBufferStr,0,3*nReceivedBuffSize+1); + for(j = 0; j < nReceivedBuffSize; j++) { + snprintf(&aRecievedBufferStr[3*j], 3*nReceivedBuffSize+1 - (3*j + 1), " %02X", pRxBuff[j]); + } + LOG_MSG_ERROR("\nReceived Value(%d)\n%s\n",nReceivedBuffSize,aRecievedBufferStr); + nReceivedBuffSize = pSource->ReceiveData(pRxBuff, 2*(nExpectedBuffSize+1)); // We cannot overflow here. + } + +bail: + delete (pRxBuff); + LOG_MSG_STACK("Leaving Function (Returning %s)",bRetVal?"True":"False"); + return bRetVal; +} + +bool CreateBypassRoutingTable (RoutingDriverWrapper * pRouting,enum ipa_ip_type eIP, + const char * pTableName, enum ipa_client_type eRuleDestination, + uint32_t uHeaderHandle, uint32_t * pTableHdl) +{ + bool bRetVal = true; + struct ipa_ioc_add_rt_rule *pRoutingRule = NULL; + struct ipa_rt_rule_add *pRoutingRuleEntry = NULL; + struct ipa_ioc_get_rt_tbl sRoutingTable; + + LOG_MSG_STACK("Entering Function"); + memset(&sRoutingTable,0,sizeof(sRoutingTable)); + pRoutingRule = (struct ipa_ioc_add_rt_rule *) + calloc(1, + sizeof(struct ipa_ioc_add_rt_rule) + + 1*sizeof(struct ipa_rt_rule_add) + ); + if(!pRoutingRule) { + LOG_MSG_ERROR("calloc failed to allocate pRoutingRule"); + bRetVal = false; + goto bail; + } + + pRoutingRule->num_rules = 1; + pRoutingRule->ip = ((IPA_IP_v4 == eIP)? IPA_IP_v4 : IPA_IP_v6); + pRoutingRule->commit = true; + strlcpy(pRoutingRule->rt_tbl_name, pTableName, sizeof(pRoutingRule->rt_tbl_name)); + + pRoutingRuleEntry = &(pRoutingRule->rules[0]); + pRoutingRuleEntry->at_rear = 1; + pRoutingRuleEntry->rule.dst = eRuleDestination;// Setting Rule's Destination Pipe + pRoutingRuleEntry->rule.hdr_hdl = uHeaderHandle; // Header handle + pRoutingRuleEntry->rule.attrib.attrib_mask = 0;// All Packets will get a "Hit" + if (false == pRouting->AddRoutingRule(pRoutingRule)) + { + LOG_MSG_ERROR("Routing rule addition(pRoutingRule) failed!"); + bRetVal = false; + goto bail; + } + if (!pRoutingRuleEntry->rt_rule_hdl) + { + LOG_MSG_ERROR("pRoutingRuleEntry->rt_rule_hdl == 0, Routing rule addition(pRoutingRule) failed!"); + bRetVal = false; + goto bail; + } + LOG_MSG_INFO("pRoutingRuleEntry->rt_rule_hdl == 0x%x added to Table %s",pRoutingRuleEntry->rt_rule_hdl,pTableName); + sRoutingTable.ip = eIP; + strlcpy(sRoutingTable.name, pTableName, sizeof(sRoutingTable.name)); + if (!pRouting->GetRoutingTable(&sRoutingTable)) { + LOG_MSG_ERROR( + "m_routing.GetRoutingTable(&sRoutingTable=0x%p) Failed.", &sRoutingTable); + bRetVal = false; + goto bail; + } + if(NULL != pTableHdl){ + (* pTableHdl ) = sRoutingTable.hdl; + LOG_MSG_DEBUG("Table Handle =0x%x will be returned.",(*pTableHdl)); + } + +bail: + Free (pRoutingRule); + LOG_MSG_STACK("Leaving Function (Returning %s)",bRetVal?"True":"False"); + return bRetVal; +} + +bool CreateBypassRoutingTable_v2 (RoutingDriverWrapper * pRouting,enum ipa_ip_type eIP, + const char * pTableName, enum ipa_client_type eRuleDestination, + uint32_t uHeaderHandle, uint32_t * pTableHdl, uint8_t uClsAggrIrqMod) +{ + bool bRetVal = true; + struct ipa_ioc_add_rt_rule_v2 *pRoutingRule = NULL; + struct ipa_rt_rule_add_v2 *pRoutingRuleEntry = NULL; + struct ipa_ioc_get_rt_tbl sRoutingTable; + + LOG_MSG_STACK("Entering Function"); + memset(&sRoutingTable,0,sizeof(sRoutingTable)); + pRoutingRule = (struct ipa_ioc_add_rt_rule_v2 *) + calloc(1, sizeof(struct ipa_ioc_add_rt_rule_v2)); + if(!pRoutingRule) { + LOG_MSG_ERROR("calloc failed to allocate pRoutingRule"); + bRetVal = false; + goto bail; + } + pRoutingRule->rules = (uint64_t)calloc(1, sizeof(struct ipa_rt_rule_add_v2)); + if (!pRoutingRule->rules) { + LOG_MSG_ERROR("calloc failed to allocate pRoutingRule->rules"); + bRetVal = false; + goto bail; + } + + pRoutingRule->num_rules = 1; + pRoutingRule->rule_add_size = sizeof(struct ipa_rt_rule_add_v2); + printf("%s(), Nadav: Adding rule_add_size\n", __FUNCTION__); + pRoutingRule->ip = ((IPA_IP_v4 == eIP)? IPA_IP_v4 : IPA_IP_v6); + pRoutingRule->commit = true; + strlcpy(pRoutingRule->rt_tbl_name, pTableName, sizeof(pRoutingRule->rt_tbl_name)); + + pRoutingRuleEntry = &(((struct ipa_rt_rule_add_v2 *)pRoutingRule->rules)[0]); + pRoutingRuleEntry->at_rear = 1; + pRoutingRuleEntry->rule.dst = eRuleDestination;// Setting Rule's Destination Pipe + printf("%s(), Nadav: Destination = %d\n", __FUNCTION__, pRoutingRuleEntry->rule.dst); + pRoutingRuleEntry->rule.hdr_hdl = uHeaderHandle; // Header handle + pRoutingRuleEntry->rule.attrib.attrib_mask = 0;// All Packets will get a "Hit" + pRoutingRuleEntry->rule.close_aggr_irq_mod = uClsAggrIrqMod; + if (false == pRouting->AddRoutingRule(pRoutingRule)) + { + LOG_MSG_ERROR("Routing rule addition(pRoutingRule) failed!"); + bRetVal = false; + goto bail; + } + if (!pRoutingRuleEntry->rt_rule_hdl) + { + LOG_MSG_ERROR("pRoutingRuleEntry->rt_rule_hdl == 0, Routing rule addition(pRoutingRule) failed!"); + bRetVal = false; + goto bail; + } + LOG_MSG_INFO("pRoutingRuleEntry->rt_rule_hdl == 0x%x added to Table %s",pRoutingRuleEntry->rt_rule_hdl,pTableName); + sRoutingTable.ip = eIP; + strlcpy(sRoutingTable.name, pTableName, sizeof(sRoutingTable.name)); + if (!pRouting->GetRoutingTable(&sRoutingTable)) { + LOG_MSG_ERROR( + "m_routing.GetRoutingTable(&sRoutingTable=0x%p) Failed.", &sRoutingTable); + bRetVal = false; + goto bail; + } + if(NULL != pTableHdl){ + (* pTableHdl ) = sRoutingTable.hdl; + LOG_MSG_DEBUG("Table Handle =0x%x will be returned.",(*pTableHdl)); + } + +bail: + Free (pRoutingRule); + LOG_MSG_STACK("Leaving Function (Returning %s)",bRetVal?"True":"False"); + return bRetVal; +} + +//Don't use these methods directly. use MACROs instead +void __log_msg(enum msgType logType, const char* filename, int line, const char* function, const char* format, ... ) +{ + va_list args; + switch (logType) { + case ERROR: + fprintf( stderr, "ERROR!"); + break; + case DEBUG: + fprintf( stderr, "DEBUG:"); + break; + case INFO: + fprintf( stderr, "INFO :"); + break; + case STACK: + fprintf( stderr, "STACK:"); + break; + default: + fprintf( stderr, "BUG!!!"); + break; + } + fprintf( stderr, " [%s:%d, %s()] ",filename,line,function); + va_start( args, format ); + vfprintf( stderr, format, args ); + va_end( args ); + fprintf( stderr, "\n" ); +} + +bool file_exists(const char* filename) +{ + return (access(filename, F_OK) == 0); +} + +int ConfigureSystem(int testConfiguration, int fd) +{ + return ConfigureSystem(testConfiguration, fd, NULL); +} + +int ConfigureSystem(int testConfiguration, int fd, const char* params) +{ + char testConfigurationStr[10]; + int ret; + char *pSendBuffer; + char str[10]; + int iter_cnt = 2000; + + if(params != NULL) + pSendBuffer = new char[strlen(params) + 10]; + else + pSendBuffer = new char[10]; + + if (NULL == pSendBuffer) + { + LOG_MSG_ERROR("Failed to allocated pSendBuffer"); + return -1; + } + + if(params != NULL) + snprintf(pSendBuffer, strlen(params) + 10, "%d %s", testConfiguration, params); + else + snprintf(pSendBuffer, 10, "%d", testConfiguration); + + ret = write(fd, pSendBuffer, sizeof(pSendBuffer) ); + if (ret < 0) { + g_Logger.AddMessage(LOG_ERROR, "%s Write operation failed.\n", __FUNCTION__); + goto bail; + } + + // Wait until the system is fully configured + + // Convert testConfiguration to string + snprintf(testConfigurationStr, sizeof(testConfigurationStr), "%d", testConfiguration); + + // Read the configuration index from the device node + ret = read(fd, str, sizeof(str)); + if (ret < 0) { + g_Logger.AddMessage(LOG_ERROR, "%s Read operation failed.\n", __FUNCTION__); + goto bail; + } + + while ( strcmp(str, testConfigurationStr) ) { + // Sleep for 5 msec + struct timespec time; + time.tv_sec = 0; + time.tv_nsec = 50e6; + nanosleep(&time, NULL); + ret = read(fd, str, sizeof(str)); + if (ret < 0) { + g_Logger.AddMessage(LOG_ERROR, "%s Read operation failed.\n", __FUNCTION__); + goto bail; + } + if (!--iter_cnt) { + g_Logger.AddMessage(LOG_ERROR, "%s timeout waiting for test driver.\n", __FUNCTION__); + ret = -1; + goto bail; + } + } +bail: + delete[] pSendBuffer; + return ret; +} + +void ConfigureScenario(int testConfiguration) +{ + ConfigureScenario(testConfiguration, NULL); +} + +void ConfigureScenario(int testConfiguration, const char* params) +{ + int fd, ret; + char str[10]; + int currentConf; + + // Open /dev/ipa_test device node. This will allow to configure the system + // and read its current configuration. + fd = open(CONFIGURATION_NODE_PATH, O_RDWR); + if (fd < 0) { + g_Logger.AddMessage(LOG_ERROR, "%s Could not open configuration device node.\n", __FUNCTION__); + exit(0); + } + + // Read the current configuration. + ret = read(fd, str, sizeof(str)); + if (ret < 0) { + g_Logger.AddMessage(LOG_ERROR, "%s Read operation failed.\n", __FUNCTION__); + return; + } + currentConf = atoi(str); + + // Do not reconfigure to the same configuration + if (currentConf == testConfiguration) { + g_Logger.AddMessage(LOG_DEVELOPMENT,"%s System was already configured as required(%d)\n", + __FUNCTION__, currentConf); + return; + } + + /* in case the system is not "clean"*/ + if (-1 != currentConf) { + g_Logger.AddMessage(LOG_DEVELOPMENT,"%s System has other configuration (%d) - cleanup\n", __FUNCTION__, currentConf); + ret = ConfigureSystem(-1, fd); + if (ret < 0) { + g_Logger.AddMessage(LOG_ERROR, "%s Configure operation failed.\n", + __FUNCTION__); + return; + } + } + + // Start system configuration. + g_Logger.AddMessage(LOG_DEVELOPMENT,"%s Setting system to the required configuration (%d)\n", __FUNCTION__, testConfiguration); + + ret = ConfigureSystem(testConfiguration, fd, params); + if (ret < 0) { + g_Logger.AddMessage(LOG_ERROR, "%s configure operation failed.\n", + __FUNCTION__); + return; + } + + ret = system("mdev -s"); + if (ret < 0) { + g_Logger.AddMessage(LOG_ERROR, "%s system(\"mdev -s\") returned %d\n", + __FUNCTION__, ret); + } + + close(fd); +}//func + +void clean_old_stashed_config() +{ + if (current_configuration == NULL) + return; + + for (int i = 0 ; i < current_configuration->from_ipa_channels_num ; i++) { + delete((struct test_ipa_ep_cfg*) + current_configuration->from_ipa_channel_config[i]->cfg); + delete((struct test_ipa_ep_cfg*) + current_configuration->from_ipa_channel_config[i]); + } + + for (int i = 0 ; i < current_configuration->to_ipa_channels_num ; i++) { + delete((struct test_ipa_ep_cfg*) + current_configuration->to_ipa_channel_config[i]->cfg); + delete((struct test_ipa_ep_cfg*) + current_configuration->to_ipa_channel_config[i]); + } + delete(current_configuration); + current_configuration = NULL; +} + +void stash_new_configuration(struct ipa_test_config_header *header) +{ + clean_old_stashed_config(); + + /* + * We will start by shallow copying each level, and afterwards, + * override the pointers + */ + current_configuration = new ipa_test_config_header(); + *current_configuration = *header; + + current_configuration->from_ipa_channel_config = + new ipa_channel_config*[header->from_ipa_channels_num](); + + current_configuration->to_ipa_channel_config = + new ipa_channel_config*[header->to_ipa_channels_num](); + + for (int i = 0 ; i < current_configuration->from_ipa_channels_num ; i++) { + current_configuration->from_ipa_channel_config[i] = + new ipa_channel_config; + *current_configuration->from_ipa_channel_config[i] = + *header->from_ipa_channel_config[i]; + current_configuration->from_ipa_channel_config[i]->cfg = + new test_ipa_ep_cfg(); + memcpy(current_configuration->from_ipa_channel_config[i]->cfg, + header->from_ipa_channel_config[i]->cfg, + header->from_ipa_channel_config[i]->config_size); + } + + for (int i = 0 ; i < current_configuration->to_ipa_channels_num ; i++) { + current_configuration->to_ipa_channel_config[i] = + new ipa_channel_config; + *current_configuration->to_ipa_channel_config[i] = + *header->to_ipa_channel_config[i]; + current_configuration->to_ipa_channel_config[i]->cfg = new test_ipa_ep_cfg(); + memcpy(current_configuration->to_ipa_channel_config[i]->cfg, + header->to_ipa_channel_config[i]->cfg, + header->to_ipa_channel_config[i]->config_size); + } +} + +bool is_prev_configuration_generic() +{ + int fd; + char str[10] = {0}; + int retval; + int current_conf_num; + + fd = open(CONFIGURATION_NODE_PATH, O_RDWR); + if (fd < 0) { + g_Logger.AddMessage(LOG_ERROR ,"%s Could not open configuration device node.\n", __FUNCTION__); + exit(0); + } + + retval = read(fd, str, sizeof(str)); + close(fd); + if (retval < 0) { + g_Logger.AddMessage(LOG_ERROR ,"%s Read operation failed.\n", __FUNCTION__); + return true; + } + current_conf_num = atoi(str); + + if (current_conf_num == GENERIC_TEST_CONFIGURATION_IDX) + return true; + + return false; +} + + +static bool is_reconfigure_required(struct ipa_test_config_header *header) +{ + // Is reconfiguration not required flag (current conf is cool) + bool flag = true; + + if (is_prev_configuration_generic() == false) { + g_Logger.AddMessage(LOG_DEVELOPMENT , + "prev configuration didn't use generic configuration\n"); + return true; + } + + if (current_configuration == NULL) { + g_Logger.AddMessage(LOG_DEVELOPMENT , + "no prev generic configuration found in the test app data-base\n"); + return true; + } + + flag &= (header->from_ipa_channels_num == + current_configuration->from_ipa_channels_num); + flag &= (header->to_ipa_channels_num == + current_configuration->to_ipa_channels_num); + + if (flag == false) { + g_Logger.AddMessage(LOG_DEVELOPMENT , + "not same number of pipes\n"); + return true; + } + + for (int i = 0 ; i < header->from_ipa_channels_num ; i++) { + flag &= (header->from_ipa_channel_config[i]->client == + current_configuration->from_ipa_channel_config[i]->client); + flag &= (header->from_ipa_channel_config[i]->index == + current_configuration->from_ipa_channel_config[i]->index); + flag &= !memcmp(header->from_ipa_channel_config[i]->cfg, + current_configuration->from_ipa_channel_config[i]->cfg, + header->from_ipa_channel_config[i]->config_size); + flag &= (header->from_ipa_channel_config[i]->en_status == + current_configuration->from_ipa_channel_config[i]->en_status); + } + + if (flag == false) { + g_Logger.AddMessage(LOG_DEVELOPMENT , + "\"from\" endpoint configuration is different from prev\n"); + return true; + } + + for (int i = 0 ; i < header->to_ipa_channels_num ; i++) { + flag &= (header->to_ipa_channel_config[i]->client == + current_configuration->to_ipa_channel_config[i]->client); + flag &= (header->to_ipa_channel_config[i]->index == + current_configuration->to_ipa_channel_config[i]->index); + flag &= !memcmp(header->to_ipa_channel_config[i]->cfg, + current_configuration->to_ipa_channel_config[i]->cfg, + header->to_ipa_channel_config[i]->config_size); + flag &= (header->to_ipa_channel_config[i]->en_status == + current_configuration->to_ipa_channel_config[i]->en_status); + } + + if (flag == false) { + g_Logger.AddMessage(LOG_DEVELOPMENT , + "\"to\" endpoint configuration is different from prev\n"); + return true; + } + + return false; +} + +int GenericConfigureScenario(struct ipa_test_config_header *header, bool isUlso) +{ + int fd; + int retval; + + if (is_reconfigure_required(header) == false) { + g_Logger.AddMessage(LOG_DEVELOPMENT , "No need to reconfigure, we are all good :)\n"); + return true; + } else { + g_Logger.AddMessage(LOG_DEVELOPMENT , "Need to run configuration again\n"); + } + g_Logger.AddMessage(LOG_DEVELOPMENT, "configuration has started, parameters:\n"); + g_Logger.AddMessage(LOG_DEVELOPMENT, "header->head_marker=0x%x\n", header->head_marker); + g_Logger.AddMessage(LOG_DEVELOPMENT, "header->from_ipa_channels_num=%d\n", header->from_ipa_channels_num); + g_Logger.AddMessage(LOG_DEVELOPMENT, "header->to_ipa_channels_num=%d\n", header->to_ipa_channels_num); + g_Logger.AddMessage(LOG_DEVELOPMENT, "header->tail_marker=0x%x\n", header->tail_marker); + + for (int i = 0 ; i < header->from_ipa_channels_num ; i++) { + g_Logger.AddMessage(LOG_DEVELOPMENT, + "header->from_ipa_channel_config[%d]->head_marker=0x%x\n", i, + header->from_ipa_channel_config[i]->head_marker); + g_Logger.AddMessage(LOG_DEVELOPMENT, + "header->from_ipa_channel_config[%d]->index=%d\n", i, + header->from_ipa_channel_config[i]->index); + g_Logger.AddMessage(LOG_DEVELOPMENT, + "header->from_ipa_channel_config[%d]->client=%d\n", i, + header->from_ipa_channel_config[i]->client); + g_Logger.AddMessage(LOG_DEVELOPMENT, + "header->from_ipa_channel_config[%d]->config_size=%d\n", i, + header->from_ipa_channel_config[i]->config_size); + g_Logger.AddMessage(LOG_DEVELOPMENT, + "header->from_ipa_channel_config[%d]->en_status=%d\n", i, + header->from_ipa_channel_config[i]->en_status); + } + + for (int i = 0 ; i < header->to_ipa_channels_num ; i++) { + g_Logger.AddMessage(LOG_DEVELOPMENT, + "header->to_ipa_channel_config[%d]->head_marker=0x%x\n", i, + header->to_ipa_channel_config[i]->head_marker); + g_Logger.AddMessage(LOG_DEVELOPMENT, + "header->to_ipa_channel_config[%d]->index=%d\n", i, + header->to_ipa_channel_config[i]->index); + g_Logger.AddMessage(LOG_DEVELOPMENT, + "header->to_ipa_channel_config[%d]->client=%d\n", i, + header->to_ipa_channel_config[i]->client); + g_Logger.AddMessage(LOG_DEVELOPMENT, + "header->to_ipa_channel_config[%d]->config_size=%d\n", i, + header->to_ipa_channel_config[i]->config_size); + g_Logger.AddMessage(LOG_DEVELOPMENT, + "header->to_ipa_channel_config[%d]->en_status=%d\n", i, + header->to_ipa_channel_config[i]->en_status); + } + + fd = open(CONFIGURATION_NODE_PATH, O_RDWR); + if (fd == -1) { + g_Logger.AddMessage(LOG_ERROR, + "%s - open %s failed (fd=%d,errno=%s)\n", + __FUNCTION__, CONFIGURATION_NODE_PATH, fd, strerror(errno)); + return false; + } + + if(isUlso){ + retval = ioctl(fd, IPA_TEST_IOC_ULSO_CONFIGURE, header); + } else { + retval = ioctl(fd, IPA_TEST_IOC_CONFIGURE, header); + } + if (retval) { + g_Logger.AddMessage(LOG_ERROR, "fail to configure the system (%d)\n", retval); + close(fd); + return false; + } else { + g_Logger.AddMessage(LOG_DEVELOPMENT, "system was successfully configured\n"); + } + + retval = close(fd); + if (retval) { + g_Logger.AddMessage(LOG_ERROR, + "%s - fail to close the fd (path=%s,retval=%d,fd=%d,errno=%s)\n", + __FUNCTION__, CONFIGURATION_NODE_PATH, retval, fd, strerror(errno)); + return false; + } + + g_Logger.AddMessage(LOG_DEVELOPMENT ,"stashing new configuration\n"); + stash_new_configuration(header); + + g_Logger.AddMessage(LOG_DEVELOPMENT, + "Running mdev in order to create the device nodes.\n"); + + retval = system("mdev -s"); + if (retval < 0) { + g_Logger.AddMessage(LOG_ERROR, "%s system(\"mdev -s\") returned %d\n", + __FUNCTION__, retval); + } + + return true; +} + +int GenericConfigureScenarioDestory(void) +{ + int fd; + int retval; + + g_Logger.AddMessage(LOG_DEVELOPMENT, "cleanup started\n"); + + fd = open(CONFIGURATION_NODE_PATH, O_RDWR); + if (fd == -1) { + g_Logger.AddMessage(LOG_ERROR, + "%s - open %s failed (retval=%d,fd=%d,errno=%s)\n", + __FUNCTION__, CONFIGURATION_NODE_PATH, fd, strerror(errno)); + return false; + } + + retval = ioctl(fd, IPA_TEST_IOC_CLEAN); + if (retval) + g_Logger.AddMessage(LOG_ERROR, "fail to clean the system (%d)\n", retval); + else + g_Logger.AddMessage(LOG_DEVELOPMENT, "system was successfully cleaned\n"); + + retval = close(fd); + if (retval) { + g_Logger.AddMessage(LOG_ERROR, "fail to close the fd - %d\n", retval); + return false; + } + + return true; +} + +bool configure_ep_ctrl(struct ipa_test_ep_ctrl *ep_ctrl) +{ + int fd; + int retval = 0; + + g_Logger.AddMessage(LOG_DEVELOPMENT, "ep ctrl started \n"); + + fd = open(CONFIGURATION_NODE_PATH, O_RDWR); + if (fd == -1) { + g_Logger.AddMessage(LOG_ERROR, + "%s - open %s failed (retval=%d,fd=%d,errno=%s)\n", + __FUNCTION__, CONFIGURATION_NODE_PATH, fd, strerror(errno)); + return false; + } + + retval = ioctl(fd, IPA_TEST_IOC_EP_CTRL, ep_ctrl); + if (retval) + g_Logger.AddMessage(LOG_ERROR, "fail to perform ep ctrl (%d)\n", retval); + else + g_Logger.AddMessage(LOG_DEVELOPMENT, "ep ctrl was successfully executed\n"); + + retval = close(fd); + if (retval) { + g_Logger.AddMessage(LOG_ERROR, "fail to close the fd - %d\n", retval); + } + + return true; +} + +bool configure_holb(struct ipa_test_holb_config *test_holb_config) +{ + int fd; + int retval = 0; + + g_Logger.AddMessage(LOG_DEVELOPMENT, "holb config started \n"); + + if (!test_holb_config) { + g_Logger.AddMessage(LOG_ERROR, "Null pointer argument!"); + return false; + } + + fd = open(CONFIGURATION_NODE_PATH, O_RDWR); + if (fd == -1) { + g_Logger.AddMessage(LOG_ERROR, + "%s - open %s failed (retval=%d,fd=%d,errno=%s)\n", + __FUNCTION__, CONFIGURATION_NODE_PATH, fd, strerror(errno)); + return false; + } + + retval = ioctl(fd, IPA_TEST_IOC_HOLB_CONFIG, test_holb_config); + if (retval) + g_Logger.AddMessage(LOG_ERROR, + "fail to perform holb config (%d)\n", + retval); + else + g_Logger.AddMessage(LOG_DEVELOPMENT, + "holb config was successfully executed\n"); + + retval = close(fd); + if (retval) { + g_Logger.AddMessage(LOG_ERROR, "fail to close the fd - %d\n", retval); + } + + return true; +} + +void prepare_channel_struct(struct ipa_channel_config *channel, + int index, + enum ipa_client_type client, + void *cfg, + size_t config_size, + bool en_status) +{ + channel->head_marker = IPA_TEST_CHANNEL_CONFIG_MARKER; + channel->index = index; + channel->client = client; + channel->cfg = (char*)cfg; + channel->config_size = config_size; + channel->tail_marker = IPA_TEST_CHANNEL_CONFIG_MARKER; + channel->en_status = en_status; +} + +void prepare_header_struct(struct ipa_test_config_header *header, + struct ipa_channel_config **from, + struct ipa_channel_config **to) +{ + header->head_marker = IPA_TEST_CONFIG_MARKER; + header->from_ipa_channel_config = from; + header->to_ipa_channel_config = to; + header->tail_marker = IPA_TEST_CONFIG_MARKER; +} + +bool CompareResultVsGolden(Byte *goldenBuffer, unsigned int goldenSize, + Byte *receivedBuffer, unsigned int receivedSize) +{ + if (receivedSize != goldenSize) { + g_Logger.AddMessage(LOG_VERBOSE, "%s File sizes are different.\n", __FUNCTION__); + return false; + } + return !memcmp((void*)receivedBuffer, (void*)goldenBuffer, goldenSize); +} + +size_t GetPacketStatusSize(void) +{ + switch (TestManager::GetInstance()->GetIPAHwType()) { + case IPA_HW_v5_5: + return sizeof(struct ipa3_hw_pkt_status_hw_v5_5); + case IPA_HW_v5_0: + case IPA_HW_v5_1: + return sizeof(struct ipa3_hw_pkt_status_hw_v5_0); + default: + return sizeof(struct ipa3_hw_pkt_status); + } +} + +bool CompareResultVsGolden_w_Status(Byte *goldenBuffer, unsigned int goldenSize, + Byte *receivedBuffer, unsigned int receivedSize) +{ + size_t stts_size = sizeof(struct ipa3_hw_pkt_status); + + switch (TestManager::GetInstance()->GetIPAHwType()) { + case IPA_HW_v5_5: + stts_size = sizeof(struct ipa3_hw_pkt_status_hw_v5_5); + break; + case IPA_HW_v5_0: + case IPA_HW_v5_1: + stts_size = sizeof(struct ipa3_hw_pkt_status_hw_v5_0); + break; + default: + stts_size = sizeof(struct ipa3_hw_pkt_status); + break; + + } + + if ((receivedSize - stts_size) != goldenSize) { + g_Logger.AddMessage(LOG_VERBOSE, "%s Buffer sizes are different.\n", __FUNCTION__); + return false; + } + + printf("comparison is made considering %zu status bytes!\n", stts_size); + + return !memcmp((void*)((unsigned char *)receivedBuffer + + stts_size), (void*)goldenBuffer, goldenSize); +} + + +Byte *LoadFileToMemory(const string &name, unsigned int *sizeLoaded) +{ + FILE *file; + Byte *buffer; + size_t fileLen; + + // Open file + file = fopen(name.c_str(), "rb"); + if (!file) { + g_Logger.AddMessage(LOG_ERROR, "Unable to open file %s\n", name.c_str()); + return NULL; + } + + // Get file length + fseek(file, 0, SEEK_END); + fileLen = ftell(file); + fseek(file, 0, SEEK_SET); + + // Allocate memory + buffer=(Byte*)malloc(fileLen+1); + if (!buffer) { + fprintf(stderr, "Memory error!\n"); + fclose(file); + return NULL; + } + + // Read file contents into buffer + *sizeLoaded = fread(buffer, 1, fileLen, file); + fclose(file); + + return buffer; +} + +void print_buff(void *data, size_t size) +{ + uint8_t bytes_in_line = 16; + uint i, j, num_lines; + char str[1024], tmp[4]; + + num_lines = size / bytes_in_line; + if (size % bytes_in_line > 0) + num_lines++; + + printf("Printing buffer at address 0x%p, size = %zu: \n", data, size); + for (i = 0 ; i < num_lines; i++) { + str[0] = '\0'; + for (j = 0; (j < bytes_in_line) && ((i * bytes_in_line + j) < size); j++) { + snprintf(tmp, sizeof(tmp), "%02x ", + ((unsigned char*)data)[i * bytes_in_line + j]); + strlcpy(str + strlen(str), tmp, sizeof(str) - strlen(str)); + } + printf("%s\n", str); + } +} + +void add_buff(uint8_t *data, size_t size, uint8_t val) +{ + for (int i = 0; i < static_cast(size); i++) + data[i]+=val; +} + +bool RegSuspendHandler(bool deferred_flag, bool reg, int DevNum) +{ + int fd = 0; + int retval = 0; + struct ipa_test_reg_suspend_handler RegData; + + fd = open(CONFIGURATION_NODE_PATH, O_RDWR); + if (fd == -1) { + g_Logger.AddMessage(LOG_ERROR, + "%s - open %s failed (fd=%d,errno=%s)\n", + __FUNCTION__, CONFIGURATION_NODE_PATH, fd, strerror(errno)); + return false; + } + + RegData.DevNum = DevNum; + RegData.reg = reg; + RegData.deferred_flag = deferred_flag; + + retval = ioctl(fd, IPA_TEST_IOC_REG_SUSPEND_HNDL, &RegData); + if (retval) { + g_Logger.AddMessage(LOG_ERROR, "fail to reg suspend handler (%d)\n", retval); + close(fd); + return false; + } else { + g_Logger.AddMessage(LOG_DEVELOPMENT, "suspend handler was successfully configured\n"); + } + + close(fd); + + return true; +} + +const Byte Eth2Helper::m_ETH2_IP4_HDR[ETH_HLEN] = +{ + 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, // ETH2 DST + 0xA7, 0xA8, 0xA9, 0xB0, 0xB1, 0xB2, // ETH2 SRC + 0x08, 0x00, // ETH2 TYPE IPv4 - ETH_P_IP 0x0800 +}; + +bool Eth2Helper::LoadEth2IP4Header( + uint8_t *pBuffer, + size_t bufferSize, + size_t *pLen) +{ + if (bufferSize < ETH_HLEN) + { + LOG_MSG_ERROR("Buffer too small\n"); + return false; + } + + memcpy(pBuffer, m_ETH2_IP4_HDR, ETH_HLEN); + + *pLen = ETH_HLEN; + + return true; +} + +bool Eth2Helper::LoadEth2IP6Header( + uint8_t *pBuffer, + size_t bufferSize, + size_t *pLen) +{ + if (bufferSize < ETH_HLEN) + { + LOG_MSG_ERROR("Buffer too small\n"); + return false; + } + + // copy eth2 ip4 header + memcpy(pBuffer, m_ETH2_IP4_HDR, ETH_HLEN); + + // change ethtype to ip6 + pBuffer[ETH2_ETH_TYPE_OFFSET] = 0x86; + pBuffer[ETH2_ETH_TYPE_OFFSET+1] = 0xdd; + + *pLen = ETH_HLEN; + + return true; +} + +bool Eth2Helper::LoadEth2IP4Packet( + uint8_t *pBuffer, + size_t bufferSize, + size_t *pLen) +{ + size_t cnt = 0; + size_t len = 0; + + if (!LoadEth2IP4Header(pBuffer, bufferSize, &cnt)) + return false; + + len = bufferSize - cnt; + + if (!LoadDefaultPacket(IPA_IP_v4, pBuffer + cnt, len)) + return false; + + *pLen = len + cnt; + + return true; +} + +bool Eth2Helper::LoadEth2IP6Packet( + uint8_t *pBuffer, + size_t bufferSize, + size_t *pLen) +{ + size_t cnt = 0; + size_t len = 0; + + if (!LoadEth2IP6Header(pBuffer, bufferSize, &cnt)) + return false; + + len = bufferSize - cnt; + + if (!LoadDefaultPacket(IPA_IP_v6, pBuffer + cnt, len)) + return false; + + *pLen = len + cnt; + + return true; +} + +const Byte WlanHelper::m_WLAN_HDR[WLAN_HDR_SIZE] = +{ + // WLAN hdr - 4 bytes + 0x01, 0x02, 0x03, 0x04 +}; + +bool WlanHelper::LoadWlanHeader( + uint8_t *pBuffer, + size_t bufferSize, + size_t *pLen) +{ + if (bufferSize < WLAN_HDR_SIZE) + { + LOG_MSG_ERROR("Buffer too small\n"); + return false; + } + + memcpy(pBuffer, m_WLAN_HDR, WLAN_HDR_SIZE); + + *pLen = WLAN_HDR_SIZE; + + return true; +} + +bool WlanHelper::LoadWlanEth2IP4Header( + uint8_t *pBuffer, + size_t bufferSize, + size_t *pLen) +{ + size_t cnt = 0; + size_t len = 0; + + if (!LoadWlanHeader(pBuffer, bufferSize, &cnt)) + return false; + + if (!Eth2Helper::LoadEth2IP4Header( + pBuffer + cnt, + bufferSize - cnt, + &len)) + return false; + + *pLen = len + cnt; + + return true; +} + +bool WlanHelper::LoadWlanEth2IP6Header( + uint8_t *pBuffer, + size_t bufferSize, + size_t *pLen) +{ + size_t cnt = 0; + size_t len = 0; + + if (!LoadWlanHeader(pBuffer, bufferSize, &cnt)) + return false; + + if (!Eth2Helper::LoadEth2IP6Header( + pBuffer + cnt, + bufferSize - cnt, + &len)) + return false; + + *pLen = len + cnt; + + return true; +} + +bool WlanHelper::LoadWlanEth2IP4Packet( + uint8_t *pBuffer, + size_t bufferSize, + size_t *pLen) +{ + size_t cnt = 0; + size_t len = 0; + + if (!LoadWlanHeader(pBuffer, bufferSize, &cnt)) + return false; + + if (!Eth2Helper::LoadEth2IP4Packet( + pBuffer + cnt, + bufferSize - cnt, + &len)) + return false; + + *pLen = len + cnt; + + return true; +} + +bool PadByLength( + uint8_t *pBuffer, + size_t bufferSize, + size_t len, + uint8_t padValue) +{ + if (bufferSize < len) + { + LOG_MSG_ERROR("bufferSize < len.\n"); + return false; + } + + memset(pBuffer, padValue, len); + + return true; +} + +bool WlanHelper::LoadWlanEth2IP4PacketByLength( + uint8_t *pBuffer, + size_t bufferSize, + size_t len, + uint8_t padValue) +{ + size_t cnt = 0; + + if (!LoadWlanEth2IP4Packet(pBuffer, bufferSize, &cnt)) + return false; + + if (!PadByLength(pBuffer + cnt, bufferSize - cnt, len - cnt, padValue)) + return false; + + return true; +} + +bool RNDISAggregationHelper::LoadRNDISHeader( + uint8_t *pBuffer, + size_t bufferSize, + uint32_t messageLength, + size_t *pLen) +{ + if (bufferSize < RNDIS_HDR_SIZE) + { + LOG_MSG_ERROR("Buffer too small\n"); + return false; + } + + struct RndisHeader *pRndisHeader = + reinterpret_cast(pBuffer); + + memset(pRndisHeader, 0, sizeof(struct RndisHeader)); + pRndisHeader->MessageType = 0x01; + pRndisHeader->DataOffset = 0x24; + + if (messageLength > RNDIS_HDR_SIZE) + { + pRndisHeader->MessageLength = messageLength; + pRndisHeader->DataLength = messageLength - RNDIS_HDR_SIZE; + } + else + { + // This handles a case where we use the header + // in IPA headers table + // IPA needs to set these values + pRndisHeader->MessageLength = 0; + pRndisHeader->DataLength = 0; + } + + *pLen = RNDIS_HDR_SIZE; + + return true; +} + +bool RNDISAggregationHelper::LoadRNDISEth2IP4Header( + uint8_t *pBuffer, + size_t bufferSize, + uint32_t messageLength, + size_t *pLen) +{ + size_t cnt = 0; + size_t len = 0; + + if (!LoadRNDISHeader(pBuffer, bufferSize, messageLength, &cnt)) + return 0; + + if (!Eth2Helper::LoadEth2IP4Header(pBuffer + cnt, bufferSize - cnt, &len)) + return false; + + *pLen = cnt + len; + + return true; +} + +bool RNDISAggregationHelper::LoadRNDISPacket( + enum ipa_ip_type eIP, + uint8_t *pBuffer, + size_t &nMaxSize) +{ + if (nMaxSize < sizeof(struct RndisHeader)) + { + LOG_MSG_ERROR("Buffer too small\n"); + return false; + } + + size_t nMaxSizeForDefaultPacket = nMaxSize - sizeof(struct RndisHeader); + + if (!LoadEtherPacket(eIP, pBuffer + sizeof(struct RndisHeader), + nMaxSizeForDefaultPacket)) + { + LOG_MSG_ERROR("LoadEtherPacket() failed\n"); + return false; + } + + nMaxSize = nMaxSizeForDefaultPacket + sizeof(struct RndisHeader); + struct RndisHeader *pRndisHeader = (struct RndisHeader*)pBuffer; + + memset(pRndisHeader, 0, sizeof(struct RndisHeader)); + pRndisHeader->MessageType = 0x01; + pRndisHeader->MessageLength = nMaxSize; + pRndisHeader->DataOffset = 0x24; + pRndisHeader->DataLength = nMaxSizeForDefaultPacket; + return true; +} + +bool RNDISAggregationHelper::LoadEtherPacket( + enum ipa_ip_type eIP, + uint8_t *pBuffer, + size_t &nMaxSize) +{ + if (nMaxSize < sizeof(struct ethhdr)) + { + LOG_MSG_ERROR("Buffer too small\n"); + return false; + } + + size_t nMaxSizeForDefaultPacket = nMaxSize - sizeof(struct ethhdr); + + if (!LoadDefaultPacket(eIP, pBuffer + sizeof(struct ethhdr), + nMaxSizeForDefaultPacket)) + { + LOG_MSG_ERROR("LoadDefaultPacket() failed\n"); + return false; + } + + nMaxSize = nMaxSizeForDefaultPacket + sizeof(struct ethhdr); + struct ethhdr *pEtherHeader = (struct ethhdr*)pBuffer; + + memcpy(pEtherHeader, Eth2Helper::m_ETH2_IP4_HDR, sizeof(struct ethhdr)); + + print_buff(pBuffer, nMaxSize); + return true; + + +} + +bool RNDISAggregationHelper::CompareIPvsRNDISPacket( + Byte *pIPPacket, + int ipPacketSize, + Byte *pRNDISPacket, + size_t rndisPacketSize) +{ + struct RndisHeader *pRndisHeader = (struct RndisHeader*)pRNDISPacket; + + if (pRndisHeader->MessageType != 0x01) + { + LOG_MSG_ERROR("Wrong MessageType 0x%8x\n", + pRndisHeader->MessageType); + return false; + } + + if (pRndisHeader->MessageLength != rndisPacketSize) + { + LOG_MSG_ERROR( + "Packet sizes do not match 0x%8x expected 0x%8x\n", + pRndisHeader->MessageLength, rndisPacketSize); + return false; + } + + // Create Ethernet packet from the IP packet and compare it to RNDIS payload + size_t EtherPacketSize = ipPacketSize + sizeof(struct ethhdr); + Byte* pEtherPacket = (Byte *) malloc(EtherPacketSize); + if (pEtherPacket == NULL) { + LOG_MSG_ERROR("Memory allocation failure.\n"); + return false; + } + + memcpy(pEtherPacket, Eth2Helper::m_ETH2_IP4_HDR, sizeof(struct ethhdr)); + memcpy(pEtherPacket + sizeof(struct ethhdr), pIPPacket, ipPacketSize); + + if (pRndisHeader->DataLength != EtherPacketSize) + { + LOG_MSG_ERROR( + "Packet sizes do not match 0x%8x expected 0x%8x\n", + pRndisHeader->DataLength, EtherPacketSize); + Free(pEtherPacket); + return false; + } + + if(!ComparePackets( + (Byte*)&pRndisHeader->DataOffset + pRndisHeader->DataOffset, + EtherPacketSize, pEtherPacket, EtherPacketSize)) + { + LOG_MSG_ERROR("Packets do not match\n"); + Free(pEtherPacket); + return false; + } + + Free(pEtherPacket); + return true; +} + +bool RNDISAggregationHelper::CompareEthervsRNDISPacket( + Byte *pIPPacket, + size_t ipPacketSize, + Byte *pRNDISPacket, + size_t rndisPacketSize) +{ + struct RndisHeader *pRndisHeader = (struct RndisHeader*)pRNDISPacket; + + if (pRndisHeader->MessageType != 0x01) + { + LOG_MSG_ERROR("Wrong MessageType 0x%8x\n", + pRndisHeader->MessageType); + return false; + } + + if (pRndisHeader->MessageLength != rndisPacketSize) + { + LOG_MSG_ERROR( + "Packet sizes do not match 0x%8x expected 0x%8x\n", + pRndisHeader->MessageLength, rndisPacketSize); + return false; + } + + if (pRndisHeader->DataLength != ipPacketSize) + { + LOG_MSG_ERROR( + "Packet sizes do not match 0x%8x expected 0x%8x\n", + pRndisHeader->DataLength, ipPacketSize); + return false; + } + + return ComparePackets( + (Byte*)&pRndisHeader->DataOffset + pRndisHeader->DataOffset, + ipPacketSize, pIPPacket, ipPacketSize); +} + +bool RNDISAggregationHelper::ComparePackets( + Byte *pPacket, + int packetSize, + Byte *pExpectedPacket, + int expectedPacketSize) +{ + bool res = true; + + if (packetSize != expectedPacketSize) + { + LOG_MSG_ERROR("Packet sizes do not match\n"); + res = false; + } + + for (int i = 0; i < packetSize; i++) + { + if (pPacket[i] != pExpectedPacket[i]) + { + LOG_MSG_ERROR( + "Byte %d not match 0x%2x != 0x%2x\n", + i, pPacket[i], pExpectedPacket[i]); + res = false; + } + } + + if (!res) + { + LOG_MSG_ERROR("Packet:\n"); + print_buff(pPacket, packetSize); + LOG_MSG_ERROR("Expected Packet:\n"); + print_buff(pExpectedPacket, expectedPacketSize); + } + + return res; +} + + +#if !defined(MSM_IPA_TESTS) && !defined(USE_GLIB) && !defined(FEATURE_IPA_ANDROID) +size_t strlcpy(char* dst, const char* src, size_t size) +{ + size_t i; + + if (size == 0) + return strlen(src); + + for (i = 0; i < (size - 1) && src[i] != '\0'; ++i) + dst[i] = src[i]; + + dst[i] = '\0'; + + return i + strlen(src + i); +} +#endif diff --git a/qcom/opensource/dataipa/kernel-tests/TestsUtils.h b/qcom/opensource/dataipa/kernel-tests/TestsUtils.h new file mode 100644 index 0000000000..268ae8ffd7 --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/TestsUtils.h @@ -0,0 +1,860 @@ +/* + * Copyright (c) 2017-2020 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __TESTS_UTILS__H__ +#define __TESTS_UTILS__H__ + +#include +#include +#include +#include +#include +#include "TestBase.h" +#include "Constants.h" +#include "RoutingDriverWrapper.h" +#include "InterfaceAbstraction.h" +#include "ipa_test_module.h" +#include "TestManager.h" +#include "Logger.h" +#include "Constants.h" +extern "C" { +#include "ipa_nat_utils.h" +} + +using namespace std; +#define TEST_APP_VERSION "2.00" + +#define Free(x) do { if (x) {free(x); x = NULL; } } while (0) + +#define MAX3(_X, _Y, _Z) max(max((_X), (_Y)), (_Z)) + +#define ETH2_DST_ADDR_OFFSET (0) +#define ETH2_SRC_ADDR_OFFSET (ETH_ALEN) +#define ETH2_ETH_TYPE_OFFSET (ETH2_SRC_ADDR_OFFSET + ETH_ALEN) +#define ETH2_ETH_TYPE_LEN (2) +#define ETH2_PAYLOAD_OFFSET (ETH2_ETH_TYPE_OFFSET + ETH2_ETH_TYPE_LEN) + +#define ETH8021Q_HEADER_LEN (18) +#define ETH8021Q_METADATA_OFFSET (12) +#define ETH8021Q_8021Q_TAG_LEN (4) +#define ETH8021Q_ETH_TYPE_OFFSET (ETH8021Q_METADATA_OFFSET + ETH8021Q_8021Q_TAG_LEN) + +#define WLAN_HDR_SIZE (4) +#define RNDIS_HDR_SIZE (44) + +// 26 ROME WLAN Frame = +// 4 ROME WLAN header + +// 14 IEEE 802.3 + +// 8 802.2 LLC/SNAP +#define _802_3_HDR_SIZE (26) + +// [WLAN][ETH2] header +#define WLAN_ETH2_HDR_SIZE (WLAN_HDR_SIZE + ETH_HLEN) + +// [RNDIS][ETH2] header +#define RNDIS_ETH2_HDR_SIZE (RNDIS_HDR_SIZE + ETH_HLEN) +#define IP4_PACKET_SIZE (70) // Arbitrary number + +// OFFSET = sizeof(struct rndis_pkt_hdr) - RNDIS_HDR_OFST(data_ofst) +#define RNDIS_DATA_OFFSET (36) + +// [WLAN][802.3] header +#define WLAN_802_3_HDR_SIZE (WLAN_HDR_SIZE + _802_3_HDR_SIZE) + +#define IPA_CLIENT_IS_PROD(x) \ + (x < IPA_CLIENT_MAX && (x & 0x1) == 0) +#define IPA_CLIENT_IS_CONS(x) \ + (x < IPA_CLIENT_MAX && (x & 0x1) == 1) + +enum msgType { + ERROR = 0, + DEBUG, + INFO, + STACK +}; + +/** + @brief + Do not Use this function. Use MACROs instead. + + @details + Do not Use this function. + Instead use the MACROs: LOG_MSG_ERROR, LOG_MSG_INFO & LOG_MSG_DEBUG + */ +void __log_msg(enum msgType, + const char *filename, + int line, const char *function, + const char *format, ...); + +#define LOG_MSG_ERROR(...) \ +__log_msg(ERROR, __FILE__, __LINE__, __func__, __VA_ARGS__) +#define LOG_MSG_DEBUG(...) \ +__log_msg(DEBUG, __FILE__, __LINE__, __func__, __VA_ARGS__) +#define LOG_MSG_INFO(...) \ +__log_msg(INFO, __FILE__, __LINE__, __func__, __VA_ARGS__) +#define LOG_MSG_STACK(...) \ +__log_msg(STACK, __FILE__, __LINE__, __func__, __VA_ARGS__) + +/*#define LOG_MSG_ERROR(x...) +__log_msg(ERROR, __FILE__, __LINE__, __func__, x) +#define LOG_MSG_DEBUG(x...) +__log_msg(DEBUG, __FILE__, __LINE__, __func__, x) +#define LOG_MSG_INFO(x...) +__log_msg(INFO, __FILE__, __LINE__, __func__, x) +#define LOG_MSG_STACK(x...) +__log_msg(STACK, __FILE__, __LINE__, __func__, x)*/ + +/** + @brief + Function loads a default IPv4 / IPv6 Packet + + @param [in] eIP - Type of Packet to load (IPA_IP_v4 / IPA_IP_v6) + @param [in] pBuffer - pointer to the destination buffer + @param [in,out] nMaxSize - The size of the buffer. + Upon function return, + the total number of bytes copied will be stored in this parameter. + @return boolean indicating whether the + operation completed successfully or not. + + @details + Function loads a default IPv4 / IPv6 packet into pBuffer. + */ +bool LoadDefaultPacket( + enum ipa_ip_type eIP, + uint8_t *pBuffer, + size_t &nMaxSize); + +bool LoadDefaultEth2Packet( + enum ipa_ip_type eIP, + uint8_t *pBuffer, + size_t &nMaxSize); + +bool LoadDefaultWLANEth2Packet( + enum ipa_ip_type eIP, + uint8_t *pBuffer, + size_t &nMaxSize); + +bool LoadDefaultWLAN802_32Packet( + enum ipa_ip_type eIP, + uint8_t *pBuffer, + size_t &nMaxSize); + +bool LoadNoPayloadPacket( + enum ipa_ip_type eIP, + uint8_t *pBuffer, + size_t &nMaxSize); + +bool LoadDefault802_1Q( + enum ipa_ip_type eIP, + uint8_t *pBuffer, + size_t &nMaxSize); + +/** + @brief + Function loads a default IPv4 / IPv6 Packet + + @param [in] eIP - Type of Packet to load (IPA_IP_v4 / IPA_IP_v6) + @param [in] extHdrType - Type of IPV6 extension header(FRAGMENT / NONE) + @param [in] pBuffer - pointer to the destination buffer + @param [in,out] nMaxSize - The size of the buffer. + Upon function return, + the total number of bytes copied will be stored in this parameter. + @return boolean indicating whether the + operation completed successfully or not. + + @details + Function loads a default IPv4 / IPv6 packet into pBuffer. + */ +bool LoadDefaultPacket( + enum ipa_ip_type eIP, + enum ipv6_ext_hdr_type extHdrType, + uint8_t *pBuffer, + size_t &nMaxSize); +/** + @brief + Function Sends a Packet, Receive a packet + and compares the received result with an expected buffer + + @param [in] pSink - Destination to which a packet will be sent. + @param [in] pSendBuffer - + Pointer to a buffer containing the packet that will be sent. + @param [in] nSendBuffSize - The size of the data in the packet. + @param [in] pSource - Source from which a packet will be received. + @param [in] pExpectedBuffer - Pointer a + buffer containing the expected packet (from the receiver) + @param [in] nExpectedBuffSize - The size of + valid data within pExpectedBuffer. + @return Boolean indicating whether the operation + completed successfully and the buffers matching or not. + + @details + Function sends a packet to pSink, and receives a packet from pSource. + The packet received from pSource + is compared to the expected data from pExpectedBuffer. + If ExpectData is identical to the + received data, the function returns TRUE. + */ +bool SendReceiveAndCompare( + InterfaceAbstraction * pSink, + uint8_t *pSendBuffer, + size_t nSendBuffSize, + InterfaceAbstraction * pSource, + uint8_t *pExpectedBuffer, + size_t nExpectedBuffSize); + +/** + @brief + This function creates a bypass rule within a table in the Routing block + + @param [in] pRouting - pointer to the Routing Class + @param [in] eIP - Type of Packet to load (IPA_IP_v4 / IPA_IP_v6) + @param [in] pTableName - pointer to the Table's Name. + @param [in] eRuleDestination - destination of the bypass rule. + @param [in] uHeaderHandle - + handle to the Header that should be Added (0 should be used as default). + @param [out] pTableHdl - + pointer to the table Handle (Can be Null) + @return boolean indicating whether + the operation completed successfully or not. + + @details + This function creates bypass rule within a table in the Routing block. + */ +bool CreateBypassRoutingTable( + RoutingDriverWrapper * pRouting, + enum ipa_ip_type eIP, + const char *pTableName, + enum ipa_client_type eRuleDestination, + uint32_t uHeaderHandle, + uint32_t *pTableHdl); + +/** + @brief + This function creates a bypass rule within a table in the Routing block + + @param [in] pRouting - pointer to the Routing Class + @param [in] eIP - Type of Packet to load (IPA_IP_v4 / IPA_IP_v6) + @param [in] pTableName - pointer to the Table's Name. + @param [in] eRuleDestination - destination of the bypass rule. + @param [in] uHeaderHandle - + handle to the Header that should be Added (0 should be used as default). + @param [out] pTableHdl - + pointer to the table Handle (Can be Null) + @return boolean indicating whether + the operation completed successfully or not. + + @details + This function creates bypass rule within a table in the Routing block. + */ +bool CreateBypassRoutingTable_v2( + RoutingDriverWrapper * pRouting, + enum ipa_ip_type eIP, + const char *pTableName, + enum ipa_client_type eRuleDestination, + uint32_t uHeaderHandle, + uint32_t *pTableHdl, + uint8_t uClsAggrIrqMod); + +/** + @brief + Configures the sytem to one of the pre-determined + configurations. + + @param [in] testConfiguration - Configuration number + @param [in] params - additional parameters + @return void + + @details + Writes the configuration index to /dev/ipa_test. In case + the system has already been configured, returns. +*/ +void ConfigureScenario(int testConfiguration); +void ConfigureScenario(int testConfiguration, const char *params); +int GenericConfigureScenario(struct ipa_test_config_header *header, + bool isUlso=false); +int GenericConfigureScenarioDestory(void); +int ConfigureSystem(int testConfiguration, int fd); +int ConfigureSystem(int testConfiguration, int fd, const char *params); + +void prepare_channel_struct(struct ipa_channel_config *channel, + int index, + enum ipa_client_type client, + void *cfg, + size_t config_size, + bool en_status = 0); + +void prepare_header_struct(struct ipa_test_config_header *header, + struct ipa_channel_config **from, + struct ipa_channel_config **to); + +/** + @brief + Compares two data buffers. + + @param [in] goldenBuffer - Pointer to the first data + buffer + @param [in] goldenSize - First data buffer size + @param [in] receivedBuffer - Pointer to the second data + buffer + @param [in] receivedSize - Second data buffer size + @return True - the buffers are identical. False + otherwise. + + @details + In case the sizes are differnt, false is returned. +*/ +bool CompareResultVsGolden( + unsigned char *goldenBuffer, + unsigned int goldenSize, + unsigned char *receivedBuffer, + unsigned int receivedSize); + +/** + @brief + Compares two data buffers considering the returned status. + + @param [in] goldenBuffer - Pointer to the first data + buffer + @param [in] goldenSize - First data buffer size + @param [in] receivedBuffer - Pointer to the second data + buffer + @param [in] receivedSize - Second data buffer size + @return True - the buffers are identical. False + otherwise. + + @details + In case the sizes are differnt, false is returned. +*/ +bool CompareResultVsGolden_w_Status( + Byte *goldenBuffer, + unsigned int goldenSize, + Byte *receivedBuffer, + unsigned int receivedSize); + + +/** + @brief + Loads a file to memory + + @param [in] fileFullPath + @param [inout] sizeLoaded - returns the number of bytes + which were read from the file + @return Address of the loaded data buffer + + @details + Allocates memory by itself, user should free the memory + +*/ +unsigned char *LoadFileToMemory( + const string & fileFullPath, + unsigned int *sizeLoaded); + +/** + @brief + Checks whether a file exists on disk + + @param [in] filename + @return True if the file exists, false otherwise. + + @details +*/ +bool file_exists(const char *filename); + +/** + @brief + Prints a data buffer. + @param [in] data - Pointer to the data + @param [in] size - How many bytes to print + @return void + + @details +*/ +void print_buff(void *data, size_t size); + +void add_buff(uint8_t *data, size_t size, uint8_t val); + +/** + @brief + Performes ep control of a specific endpoint. + @param [in] ep_ctrl - Pointer to ipa_test_ep_ctrl struct with + the data of the requested operation + @return bool + + @details + Suspend\Unsuspends\Delays\resumes an endpoint. +*/ +bool configure_ep_ctrl(struct ipa_test_ep_ctrl *ep_ctrl); + +/** + @brief + Performes holb config of a specific pipe. + * @param [in] test_holb_config - Pointer to + * ipa_test_holb_config struct with the data of + * the requested operation + @return bool + + @details + Configures HOLB parameters on a pipe. +*/ +bool configure_holb(struct ipa_test_holb_config *test_holb_config); + +/** + @brief + Register an alternative suspend handler + @param [in] deferred_flag - should the handler execute in defer mode + @param [in] reg - register or unregister the suspend handler + @param [in] DevNum - the index of the ep that the handler is registered to + @return bool + + @details + Register the test framework suspend handler for a given endpoint +*/ +bool RegSuspendHandler(bool deferred_flag, bool reg, int DevNum); + +class Eth2Helper { +public: + static const Byte m_ETH2_IP4_HDR[ETH_HLEN]; + + static bool LoadEth2IP4Header( + uint8_t *pBuffer, + size_t bufferSize, + size_t *pLen); + + static bool LoadEth2IP6Header( + uint8_t *pBuffer, + size_t bufferSize, + size_t *pLen); + + static bool LoadEth2IP4Packet( + uint8_t *pBuffer, + size_t bufferSize, + size_t *pLen); + + static bool LoadEth2IP6Packet( + uint8_t *pBuffer, + size_t bufferSize, + size_t *pLen); +}; + +class WlanHelper { +public: + static const Byte m_WLAN_HDR[WLAN_HDR_SIZE]; + + static bool LoadWlanHeader( + uint8_t *pBuffer, + size_t bufferSize, + size_t *pLen); + + static bool LoadWlanEth2IP4Header( + uint8_t *pBuffer, + size_t bufferSize, + size_t *pLen); + + static bool LoadWlanEth2IP6Header( + uint8_t *pBuffer, + size_t bufferSize, + size_t *pLen); + + static bool LoadWlanEth2IP4Packet( + uint8_t *pBuffer, + size_t bufferSize, + size_t *pLen); + + static bool LoadWlanEth2IP4PacketByLength( + uint8_t *pBuffer, + size_t bufferSize, + size_t len, + uint8_t padValue); + + static bool LoadWlanEth2IP6Packet( + uint8_t *pBuffer, + size_t bufferSize, + size_t *pLen); +}; + +#pragma pack(push) /* push current alignment to stack */ +#pragma pack(1) /* set alignment to 1 byte boundary */ +struct RndisHeader { + uint32_t MessageType; + uint32_t MessageLength; + uint32_t DataOffset; + uint32_t DataLength; + uint32_t OOBDataOffset; + uint32_t OOBDataLength; + uint32_t OOBNumber; + uint32_t PacketInfoOffset; + uint32_t PacketInfoLength; + uint64_t Reserved; +}; + +struct RndisEtherHeader { + struct RndisHeader rndisHeader; + struct ethhdr etherHeader; +}; +#pragma pack(pop) /* restore original alignment from stack */ + +class RNDISAggregationHelper { +public: + static const size_t RNDIS_AGGREGATION_BYTE_LIMIT = 1024; + + static bool LoadRNDISHeader( + uint8_t *pBuffer, + size_t bufferSize, + uint32_t messageLength, + size_t *pLen); + + static bool LoadRNDISEth2IP4Header( + uint8_t *pBuffer, + size_t bufferSize, + uint32_t messageLength, + size_t *pLen); + + static bool LoadRNDISPacket( + enum ipa_ip_type eIP, + uint8_t *pBuffer, + size_t &nMaxSize); + + static bool LoadEtherPacket( + enum ipa_ip_type eIP, + uint8_t *pBuffer, + size_t &nMaxSize); + + static bool ComparePackets( + Byte *pPacket1, + int pPacket1Size, + Byte *pPacket2, + int pPacket2Size); + + static bool CompareEthervsRNDISPacket( + Byte *pIPPacket, + size_t ipPacketSize, + Byte *pRNDISPacket, + size_t rndisPacketSize); + + static bool CompareIPvsRNDISPacket( + Byte *pIPPacket, + int ipPacketSize, + Byte *pRNDISPacket, + size_t rndisPacketSize); +}; + +enum ipa_nat_en_type { + IPA_BYPASS_NAT, + IPA_SRC_NAT, + IPA_DST_NAT, +}; + +enum ipa_ipv6ct_en_type { + IPA_BYPASS_IPV6CT, + IPA_ENABLE_IPV6CT, +}; + +enum ipa_mode_type { + IPA_BASIC, + IPA_ENABLE_FRAMING_HDLC, + IPA_ENABLE_DEFRAMING_HDLC, + IPA_DMA, +}; + +enum ipa_aggr_en_type { + IPA_BYPASS_AGGR, + IPA_ENABLE_AGGR, + IPA_ENABLE_DEAGGR, +}; + +enum ipa_aggr_type { + IPA_MBIM_16 = 0, + IPA_HDLC = 1, + IPA_TLP = 2, + IPA_RNDIS = 3, + IPA_GENERIC = 4, + IPA_QCMAP = 6, +}; + +enum ipa_aggr_mode { + IPA_MBIM_AGGR, + IPA_QCNCM_AGGR, +}; + +enum hdr_total_len_or_pad_type { + IPA_HDR_PAD = 0, + IPA_HDR_TOTAL_LEN = 1, +}; + +struct ipa_ep_cfg_nat { + enum ipa_nat_en_type nat_en; + bool nat_exc_suppress; +}; + +struct ipa_ep_cfg_conn_track { + enum ipa_ipv6ct_en_type conn_track_en; +}; + +struct ipa_ep_cfg_hdr { + uint32_t hdr_len; + uint32_t hdr_ofst_metadata_valid; + uint32_t hdr_ofst_metadata; + uint32_t hdr_additional_const_len; + uint32_t hdr_ofst_pkt_size_valid; + uint32_t hdr_ofst_pkt_size; + uint32_t hdr_a5_mux; + uint32_t hdr_remove_additional; + uint32_t hdr_metadata_reg_valid; +}; + +struct ipa_ep_cfg_hdr_ext { + uint32_t hdr_pad_to_alignment; + uint32_t hdr_total_len_or_pad_offset; + bool hdr_payload_len_inc_padding; + enum hdr_total_len_or_pad_type hdr_total_len_or_pad; + bool hdr_total_len_or_pad_valid; + bool hdr_little_endian; + struct ipa_ep_cfg_hdr *hdr; + bool hdr_bytes_to_remove_valid; + uint32_t hdr_bytes_to_remove; +}; + +struct ipa_ep_cfg_mode { + enum ipa_mode_type mode; + enum ipa_client_type dst; +}; + +struct ipa_ep_cfg_aggr { + enum ipa_aggr_en_type aggr_en; + enum ipa_aggr_type aggr; + uint32_t aggr_byte_limit; + uint32_t aggr_time_limit; + uint32_t aggr_pkt_limit; + uint32_t aggr_hard_byte_limit_en; + bool aggr_sw_eof_active; + uint8_t pulse_generator; + uint8_t scaled_time; + bool aggr_coal_l2; +}; + +struct ipa_ep_cfg_route { + uint32_t rt_tbl_hdl; +}; + +struct ipa_ep_cfg_deaggr { + uint32_t deaggr_hdr_len; + bool syspipe_err_detection; + bool packet_offset_valid; + uint32_t packet_offset_location; + bool ignore_min_pkt_err; + uint32_t max_packet_len; +}; + +enum ipa_cs_offload { + IPA_DISABLE_CS_OFFLOAD, + IPA_ENABLE_CS_OFFLOAD_UL, + IPA_ENABLE_CS_OFFLOAD_DL, + IPA_CS_RSVD +}; + +struct ipa_ep_cfg_cfg { + bool frag_offload_en; + enum ipa_cs_offload cs_offload_en; + uint8_t cs_metadata_hdr_offset; + uint8_t gen_qmb_master_sel; + uint8_t tx_instance; + bool pipe_replicate_en; +}; + +struct ipa_ep_cfg_metadata_mask { + uint32_t metadata_mask; +}; + +struct ipa_ep_cfg_metadata { + uint32_t qmap_id; +}; + +struct ipa_ep_cfg_seq { + bool set_dynamic; + int seq_type; +}; + +struct ipa_ep_cfg_ulso { + int ipid_min_max_idx; + bool is_ulso_pipe; +}; + +struct ipa_ep_cfg_holb { + uint32_t tmr_val; + uint32_t base_val; + uint32_t scale; + uint16_t en; + uint8_t pulse_generator; + uint8_t scaled_time; +}; + +struct ipa_pkt_init_ex_hdr_ofst_set { + char name[IPA_RESOURCE_NAME_MAX]; + enum ipa_client_type ep; +}; + +struct ipa_ep_cfg_prod_cfg { + uint8_t tx_instance; + bool tsp_enable; + bool max_output_size_drop_enable; + uint8_t tsp_idx; + uint8_t max_output_size; + uint8_t egress_tc_lowest; + uint8_t egress_tc_highest; +}; + +/* + * This struct is a mirroring of the ipa struct + * the test module expect to get from user-space the + * exact same struct as IPA driver defined. + * In case of any change to IPA driver struct + * this struct should be updated as well! + */ +struct test_ipa_ep_cfg { + struct ipa_ep_cfg_nat nat; + struct ipa_ep_cfg_conn_track conn_track; + struct ipa_ep_cfg_hdr hdr; + struct ipa_ep_cfg_hdr_ext hdr_ext; + struct ipa_ep_cfg_mode mode; + struct ipa_ep_cfg_aggr aggr; + struct ipa_ep_cfg_deaggr deaggr; + struct ipa_ep_cfg_route route; + struct ipa_ep_cfg_cfg cfg; + struct ipa_ep_cfg_metadata_mask metadata_mask; + struct ipa_ep_cfg_metadata meta; + struct ipa_ep_cfg_seq seq; + struct ipa_ep_cfg_ulso ulso; + struct ipa_ep_cfg_prod_cfg prod_cfg; +}; + +/*! @brief Struct for the IPAv3.0 UL packet status header */ +struct ipa3_hw_pkt_status { + uint64_t status_opcode:8; + uint64_t exception:8; + uint64_t status_mask:16; + uint64_t pkt_len:16; + uint64_t endp_src_idx:5; + uint64_t reserved_1:3; + uint64_t endp_dest_idx:5; + uint64_t reserved_2:3; + uint64_t metadata:32; + uint64_t filt_local:1; + uint64_t filt_hash:1; + uint64_t filt_global:1; + uint64_t ret_hdr:1; + uint64_t filt_rule_id:10; + uint64_t route_local:1; + uint64_t route_hash:1; + uint64_t ucp:1; + uint64_t route_tbl_idx:5; + uint64_t route_rule_id:10; + uint64_t nat_hit:1; + uint64_t nat_tbl_idx:13; + uint64_t nat_type:2; + uint64_t tag:48; + uint64_t seq_num:8; + uint64_t time_day_ctr:24; + uint64_t hdr_local:1; + uint64_t hdr_offset:10; + uint64_t frag_hit:1; + uint64_t frag_rule:4; + uint64_t reserved_4:16; +}; + +struct ipa3_hw_pkt_status_hw_v5_0 { + uint64_t status_opcode : 8; + uint64_t exception : 8; + uint64_t status_mask : 16; + uint64_t pkt_len : 16; + uint64_t endp_src_idx : 8; + uint64_t reserved_1 : 3; + uint64_t route_local : 1; + uint64_t route_hash : 1; + uint64_t reserved_2 : 3; + uint64_t metadata : 32; + uint64_t filt_local : 1; + uint64_t filt_hash : 1; + uint64_t filt_global : 1; + uint64_t ret_hdr : 1; + uint64_t filt_rule_id : 10; + uint64_t route_tbl_idx : 8; + uint64_t route_rule_id : 10; + uint64_t nat_hit : 1; + uint64_t nat_tbl_idx : 13; + uint64_t nat_type : 2; + uint64_t tag : 48; + uint64_t seq_num : 8; + uint64_t time_day_ctr : 24; + uint64_t hdr_local : 1; + uint64_t hdr_offset : 10; + uint64_t frag_hit : 1; + uint64_t frag_rule : 4; + uint64_t endp_dest_idx : 8; + uint64_t reserved_4 : 7; + uint64_t ucp : 1; +}; + +struct ipa3_hw_pkt_status_hw_v5_5 { + uint64_t status_opcode:8; + uint64_t exception:8; + uint64_t status_mask:16; + uint64_t pkt_len:16; + uint64_t endp_src_idx:8; + uint64_t reserved_1:3; + uint64_t rt_local:1; + uint64_t rt_hash:1; + uint64_t reserved_2:3; + uint64_t metadata:32; + uint64_t flt_local:1; + uint64_t flt_hash:1; + uint64_t flt_global:1; + uint64_t flt_ret_hdr:1; + uint64_t flt_rule_id:10; + uint64_t rt_tbl_idx:8; + uint64_t rt_rule_id:10; + uint64_t nat_hit:1; + uint64_t nat_entry_idx:13; + uint64_t nat_type:2; + uint64_t tag_info:36; + uint64_t egress_tc:6; + uint64_t ingress_tc:6; + uint64_t seq_num:8; + uint64_t time_of_day_ctr:24; + uint64_t hdr_local:1; + uint64_t hdr_offset:10; + uint64_t frag_hit:1; + uint64_t frag_rule:4; + uint64_t endp_dest_idx:8; + uint64_t hw_specific:4; + uint64_t nat_exc_suppress:1; + uint64_t tsp:1; + uint64_t ttl_dec:1; + uint64_t ucp:1; +}; +#endif diff --git a/qcom/opensource/dataipa/kernel-tests/UlsoTest.cpp b/qcom/opensource/dataipa/kernel-tests/UlsoTest.cpp new file mode 100644 index 0000000000..c71756227e --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/UlsoTest.cpp @@ -0,0 +1,430 @@ +/* + * Copyright (c) 2021 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Changes from Qualcomm Innovation Center are provided under the following license: + * + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * * Neither the name of Qualcomm Innovation Center, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + */ +#include +#include +#include +#include +#include +#include // for memcpy +#include "hton.h" // for htonl +#include "InterfaceAbstraction.h" +#include "Constants.h" +#include "Logger.h" +#include "TestsUtils.h" +#include "UlsoTestFixture.h" +#include "HeaderInsertion.h" + +#define ARRAY_SIZE(A) (sizeof(ArraySizeHelper(A))) + +template +char (&ArraySizeHelper(T (&a)[N]))[N]; + +using std::cout; +using std::endl; +using std::string; + +using I4 = IPv4Header; +using I6 = IPv6Header; +using UDPH = UdpHeader; +using TCPH = TcpHeader; + +/* Packet modification function objects */ +template class PacketModifier {public:virtual void operator()(PacketType& p) const = 0; virtual ~PacketModifier(){}}; +template class NullPacketModifier: public PacketModifier {public:void operator()(PacketType& p) const override {}}; +template class ZeroChecksumPacketModifier: public PacketModifier + {public:void operator()(PacketType& p) const override {p.mQmapHeader.setmZeroChecksum(1);}}; +template class OutOfBoundsPacketModifier: public PacketModifier + {public:void operator()(PacketType& p) const override {p.mQmapHeader.setmIpIdCfg(0);p.setIpId(65530);}}; + +template>> +class PacketsGeneratorClass { + +protected: + + using PacketType = UlsoPacket; + +public: + + vector operator()(){ + vector outVec; + Modifier m; + for(size_t i=0; i(SegmentSizesArr[i] * SegmentsNumsArr[j]), true); + m(p); + outVec.emplace_back(p); + } + } + return outVec; + } +}; + +template +class UlsoTest: public UlsoTestFixture { + +private: + + using PacketType = UlsoPacket; + + bool singlePacketRun(PacketType& p){ + memset(m_sendBuf, 0, sizeof(m_sendBuf)); + size_t packetSize = p.asArray(m_sendBuf); + size_t numSent = m_producer.SendData(m_sendBuf, packetSize); + + if(numSent == 0){ + return false; + } + vector segmentedPacketsVec = p.segment(); + for(auto& segmentedPacket: segmentedPacketsVec){ + memset(m_receiveBuf, 0, sizeof(m_receiveBuf)); + memset(m_segmentBuf, 0, sizeof(m_segmentBuf)); + packetSize = segmentedPacket.asArray(m_segmentBuf); + size_t recievedBytes = m_consumer.ReceiveSingleDataChunk(m_receiveBuf, packetSize); + if(packetSize != recievedBytes || memcmp(m_segmentBuf, m_receiveBuf, packetSize)){ + return fail(numSent, packetSize, recievedBytes); + } + } + return clearPipe() == 0; + } + +public: + + UlsoTest(const char* name){ + m_name = name; + string title = string("ULSO Test"); + string packetStructure = string("Structure: ") + string ("QMAP + Ethernet 2 + ") + + string(Internet().name()) + string(" ") + string(Transport().name()); + string testProcess = string( + "1. Config IPA->APPS test pipe\n" + "2. Generate a vector of ULSO packets\n" + "3. For each packet in the packets vector\n" + " a. Send the packet over the APPS->IPA pipe using ipa_tx_dp\n" + " b. Segment the packet using the software simulation and store it in a segments vector\n" + " c. For each segment in the segments vector in order\n" + " # Receive a segment over IPA->APPS test pipe\n" + " # Compare the received segment to the software simulated segment\n" + "4. Clear the IPA->USB pipe and verify there were no bytes left in the pipe"); + m_description = string(title + "\n" + packetStructure + "\n" + testProcess + "\n").c_str(); + m_minIPAHwType = IPA_HW_v5_0; + Register(*this); + } + + virtual bool Run() override { + vector packetsVec = PacketsGenerator()(); + for(auto& p: packetsVec){ + if(!singlePacketRun(p)){ + cout << "Failed With the following packet:" << endl; + cout << p << endl; + return false; + } + } + return true; + } +}; + +template +class UlsoHPCTest: public UlsoTestFixture { + +private: + + using PacketType = UlsoPacket; + static constexpr size_t rndisHdrLen {44}; + HeaderInsertion m_HeaderInsertion; + uint8_t mRndisHeader[rndisHdrLen] = {0}; + + bool fail(size_t sendSize=0, size_t totalSegmentsSize=0, size_t recievedBytes=0){ + printBuf(m_sendBuf, sendSize, "Sent:"); + printBuf(m_receiveBuf, recievedBytes, string("Rceived ") + + std::to_string(recievedBytes) + string(" Bytes:")); + printBuf(m_segmentBuf, totalSegmentsSize, string("Expected to receive ") + + std::to_string(totalSegmentsSize) + string(" Bytes:")); + clearPipe(); + return false; + } + + bool singlePacketRun(PacketType& p){ + cout << p << endl; + memset(m_sendBuf, 0, sizeof(m_sendBuf)); + size_t sendSize = p.asArray(m_sendBuf); + if(!m_producer.SendData(m_sendBuf, sendSize)){ + return fail(sendSize); + } + vector segmentedPacketsVec = p.segment(); + memset(m_segmentBuf, 0, sizeof(m_segmentBuf)); + uint8_t *segmentBufPtr = m_segmentBuf; + size_t totalSegmentsSize = 0; + vector comparisionIntervalsSizesVec; + for(auto& segmentedPacket: segmentedPacketsVec){ + memcpy(segmentBufPtr, mRndisHeader, sizeof(mRndisHeader)); + segmentBufPtr += sizeof(mRndisHeader); + comparisionIntervalsSizesVec.emplace_back(sizeof(mRndisHeader)); + totalSegmentsSize += sizeof(mRndisHeader); + size_t n = segmentedPacket.asArray(segmentBufPtr); + segmentBufPtr += n; + totalSegmentsSize += n; + comparisionIntervalsSizesVec.emplace_back(n); + } + memset(m_receiveBuf, 0, sizeof(m_receiveBuf)); + size_t recievedBytes = m_consumer.ReceiveSingleDataChunk(m_receiveBuf, totalSegmentsSize); + if(totalSegmentsSize != recievedBytes){ + return fail(sendSize, totalSegmentsSize, recievedBytes); + } + segmentBufPtr = m_segmentBuf; + uint8_t *recieveBufPtr = m_receiveBuf; + while(!comparisionIntervalsSizesVec.empty()){ + size_t skipSize = comparisionIntervalsSizesVec.front(); + recieveBufPtr += skipSize; + segmentBufPtr += skipSize; + comparisionIntervalsSizesVec.erase(comparisionIntervalsSizesVec.begin()); + if(comparisionIntervalsSizesVec.empty()){ + return fail(sendSize, totalSegmentsSize, recievedBytes); + } + size_t compareSize = comparisionIntervalsSizesVec.front(); + if(memcmp(segmentBufPtr, recieveBufPtr, compareSize)){ + return fail(sendSize, totalSegmentsSize, recievedBytes); + } + segmentBufPtr += compareSize; + recieveBufPtr += compareSize; + comparisionIntervalsSizesVec.erase(comparisionIntervalsSizesVec.begin()); + } + if(clearPipe()){ + return fail(sendSize, totalSegmentsSize, recievedBytes); + } + return true; + } + +protected: + + virtual void configFromEp(struct test_ipa_ep_cfg *ep_cfg){ + ep_cfg->hdr.hdr_len = ETH_HLEN + rndisHdrLen; + ep_cfg->hdr.hdr_additional_const_len = ETH_HLEN; + ep_cfg->hdr.hdr_ofst_pkt_size_valid = true; + ep_cfg->hdr.hdr_ofst_pkt_size = 3 * sizeof(uint32_t); + ep_cfg->hdr_ext.hdr_total_len_or_pad_offset = sizeof(uint32_t); + ep_cfg->hdr_ext.hdr_total_len_or_pad = IPA_HDR_TOTAL_LEN; + ep_cfg->hdr_ext.hdr_total_len_or_pad_valid = true; + ep_cfg->hdr_ext.hdr_little_endian = true; + ep_cfg->aggr.aggr_en = IPA_ENABLE_AGGR; + ep_cfg->aggr.aggr = IPA_GENERIC; + ep_cfg->aggr.aggr_byte_limit = 4; + ep_cfg->aggr.aggr_time_limit = 1000; + } + +public: + + UlsoHPCTest(const char* name, const char* description){ + m_name = name; + m_description = description; + m_minIPAHwType = IPA_HW_v5_0; + for(size_t i=0; i packetsVec = PacketsGenerator()(); + for(auto& p: packetsVec){ + if(!singlePacketRun(p)){ + return false; + } + } + if(!m_HeaderInsertion.DeleteHeader(headerName)){ + LOG_MSG_ERROR("Delete rndis header failed"); + return false; + } + return true; + } +}; + +/* Tests Macros */ +#define PACKETS_GEN_MODIFY(T, I, a, b, m) PacketsGeneratorClass>> +#define PACKETS_GEN(T, I, a, b) PACKETS_GEN_MODIFY(T, I, a, b, NullPacketModifier)//todo: change macro parameters to meaningfull names + +//////////////////////////////////////////////////////////////////////////////// +/////////// Simple Single Packet Tests ////////////// +//////////////////////////////////////////////////////////////////////////////// +/* + * Send a single packet and compare the received segments to the software simulation + */ +constexpr size_t segmentSizes1[] = {20}; +constexpr float segmentsNum1[] = {5}; +static UlsoTest ulsoTest0 {"Single Packet: IPV4 UDP"}; +static UlsoTest ulsoTest1 {"Single Packet: IPV4 TCP"}; +static UlsoTest ulsoTest2 {"Single Packet: IPV6 UDP"}; +static UlsoTest ulsoTest3 {"Single Packet: IPV6 TCP"}; + +//////////////////////////////////////////////////////////////////////////////// +/////////// Segmentation & Non-Segmentation mix ////////////// +//////////////////////////////////////////////////////////////////////////////// +/* + * Send a sequence of [large, small, large, small, ...] packets and compare the received segments to the software simulation + */ +constexpr size_t segmentSizes2[] = {10, 50, 100, 500, 1460}; +constexpr float segmentsNum2[] = {1, 4}; +static UlsoTest ulsoTest10 {"Segmentation No Segmentation IPV4 UDP"}; +static UlsoTest ulsoTest11 {"Segmentation No Segmentation IPV4 TCP"}; +static UlsoTest ulsoTest12 {"Segmentation No Segmentation IPV6 UDP"}; +static UlsoTest ulsoTest13 {"Segmentation No Segmentation IPV6 TCP"}; + +//////////////////////////////////////////////////////////////////////////////// +//////////////////// Zero Checksum //////////////////// +//////////////////////////////////////////////////////////////////////////////// +/* + * Send a sequence of large packets with zero checksum=1 and compare the received segments to the software simulation + */ +constexpr size_t segmentSizes3[] = {10, 50, 100, 500, 1460}; +constexpr float numSegments3[] = {4}; +static UlsoTest + ulsoTest20 {"Zero Checksum IPV4 UDP"}; +static UlsoTest + ulsoTest21 {"Zero Checksum IPV4 TCP"}; +static UlsoTest + ulsoTest22 {"Zero Checksum IPV6 UDP"}; +static UlsoTest + ulsoTest23 {"Zero Checksum IPV6 TCP"}; + +//////////////////////////////////////////////////////////////////////////////// +///////// Segment Size Greater Than Payload Size ///////////////// +//////////////////////////////////////////////////////////////////////////////// +/* + * Send a single packet with payload size and MSS matching an edge case and edge case and compare the received segments to the software simulation. + * Edge cases: + * 1. payload size < MSS ==> No segmentation + * 2. payload size == MSS - epsilon ==> No segmentation + * 3. payload size == MSS ==> Segmentation + */ +/* Segment Size = 100 Payload Size = 50 */ +constexpr size_t segmentSizes4[] = {100}; +constexpr float numSegments4[] = {0.5}; +static UlsoTest ulsoTest30 {"Payload Smaller Than MSS IPV4 UDP"}; +static UlsoTest ulsoTest31 {"Payload Smaller Than MSS IPV4 TCP"}; +static UlsoTest ulsoTest32 {"Payload Smaller Than MSS IPV6 UDP"}; +static UlsoTest ulsoTest33 {"Payload Smaller Than MSS IPV6 TCP"}; + +/* Segment Size = 100 Payload Size = 99 */ +constexpr size_t segmentSizes5[] = {100}; +constexpr float numSegments5[] = {0.99}; +static UlsoTest ulsoTest40 {"Payload slightly Smaller Than MSS IPV4 UDP"}; +static UlsoTest ulsoTest41 {"Payload slightly Smaller Than MSS IPV4 TCP"}; +static UlsoTest ulsoTest42 {"Payload slightly Smaller Than MSS IPV6 UDP"}; +static UlsoTest ulsoTest43 {"Payload slightly Smaller Than MSS IPV6 TCP"}; + +/* Segment Size = 20 Payload Size = 20 */ +constexpr size_t segmentSizes6[] = {100}; +constexpr float numSegments6[] = {1}; +static UlsoTest ulsoTest50 {"Payload Equals MSS IPV4 UDP"}; +static UlsoTest ulsoTest51 {"Payload Equals MSS IPV4 TCP"}; +static UlsoTest ulsoTest52 {"Payload Equals MSS IPV6 UDP"}; +static UlsoTest ulsoTest53 {"Payload Equals MSS IPV6 TCP"}; + +//////////////////////////////////////////////////////////////////////////////// +////////////// Valid Segment Sizes ///////////////////// +//////////////////////////////////////////////////////////////////////////////// +/* + * Send a sequence of packets with different valid sizes and compare the received segments to the software simulation + */ +constexpr size_t segmentSizes7[] = {1460, 1220, 512, 1}; +static UlsoTest ulsoTest60 {"Valid Segment Sizes IPV4 UDP"}; +static UlsoTest ulsoTest61 {"Valid Segment Sizes IPV4 TCP"}; +static UlsoTest ulsoTest62 {"Valid Segment Sizes IPV6 UDP"}; +static UlsoTest ulsoTest63 {"Valid Segment Sizes IPV6 TCP"}; + +//////////////////////////////////////////////////////////////////////////////// +//////////////// Big Segment Sizes ///////////////////// +//////////////////////////////////////////////////////////////////////////////// +/* + * Send a sequence of very large packets and compare the received segments to the software simulation + */ +constexpr size_t segmentSizes8[] = {2000, 3000, 4000, 5000, 6000, 10000}; +static UlsoTest ulsoTest70 {"Big Segment Sizes IPV4 UDP"}; +static UlsoTest ulsoTest71 {"Big Segment Sizes IPV4 TCP"}; +static UlsoTest ulsoTest72 {"Big Segment Sizes IPV6 UDP"}; +static UlsoTest ulsoTest73 {"Big Segment Sizes IPV6 TCP"}; + +//////////////////////////////////////////////////////////////////////////////// +//////////////// IP ID wrapp around min/max bounds /////////////// +//////////////////////////////////////////////////////////////////////////////// +/* + * Send a single packet such that: + * IPID + #segments < MAX IPID + * and compare the received segments to the software simulation + */ +constexpr size_t segmentSizes9[] = {2000}; +constexpr float numSegments9[] = {10}; +static UlsoTest ulsoTest80 {"IPID CFG IPV4 UDP"}; +static UlsoTest ulsoTest81 {"IPID CFG IPV4 UDP"}; +//////////////////////////////////////////////////////////////////////////////// +//////////////// HPC RNDIS Header Insertion ////////////////////// +//////////////////////////////////////////////////////////////////////////////// + +static UlsoHPCTest Ipv4UdpHpcRndisTest {"Ipv4UdpHpcRndisTest", "IPv4 + UDP"}; +static UlsoHPCTest Ipv4TcpHpcRndisTest {"Ipv4TcpHpcRndisTest", "IPv4 + TCP"}; +static UlsoHPCTest Ipv6UdpHpcRndisTest {"Ipv6UdpHpcRndisTest", "IPv6 + UDP"}; +static UlsoHPCTest Ipv6TcpHpcRndisTest {"Ipv6TcpHpcRndisTest", "IPv6 + TCP"}; diff --git a/qcom/opensource/dataipa/kernel-tests/UlsoTestFixture.h b/qcom/opensource/dataipa/kernel-tests/UlsoTestFixture.h new file mode 100644 index 0000000000..e2d5aecb37 --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/UlsoTestFixture.h @@ -0,0 +1,176 @@ +/* + * Copyright (c) 2021 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef ULSOTESTFIXTURE_H_ +#define ULSOTESTFIXTURE_H_ + +#include +#include +#include +#include +#include +#include + +#include "Constants.h" +#include "Logger.h" +#include "linux/msm_ipa.h" +#include "TestsUtils.h" +#include "TestBase.h" +#include "network_traffic/UlsoPacket.h" + +using std::cout; +using std::endl; +using std::string; + +class UlsoTestFixture: public TestBase { + +public: + + UlsoTestFixture(){ + m_testSuiteName.push_back("ULSO"); + memset(m_sendBuf, 0, sizeof(m_sendBuf)); + memset(m_receiveBuf, 0, sizeof(m_receiveBuf)); + memset(m_segmentBuf, 0, sizeof(m_segmentBuf)); + } + + virtual bool Setup() { + if(!setupKernelModule()){ + return false; + } + m_producer.Open(INTERFACE0_TO_IPA_DATA_PATH, INTERFACE0_FROM_IPA_DATA_PATH); + m_consumer.Open(INTERFACE1_TO_IPA_DATA_PATH, INTERFACE1_FROM_IPA_DATA_PATH); + return true; + } + + virtual bool Teardown(){ + m_producer.Close(); + m_consumer.Close(); + return true; + } + + virtual bool Run() = 0; + +protected: + + virtual void configFromEp(struct test_ipa_ep_cfg *ep_cfg){ + return; + } + + size_t clearPipe(){ + cout << "In clearPipe" << endl; + if(m_consumer.setReadNoBlock() == -1){ + cout << "Error: setReadNoBlock returned -1" << endl; + return 0; + } + size_t recievedBytes = m_consumer.ReceiveSingleDataChunk(m_receiveBuf, UlsoPacket<>::maxSize); + size_t totalReceivedBytes = recievedBytes; + if(recievedBytes > 0){ + unsigned count = 1; + while(recievedBytes){ + cout << "Receive #" << count << endl; + printBuf(m_receiveBuf, recievedBytes, string("Rceived ") + + std::to_string(recievedBytes) + string(" Bytes:")); + recievedBytes = m_consumer.ReceiveSingleDataChunk(m_receiveBuf, UlsoPacket<>::maxSize); + totalReceivedBytes += recievedBytes; + count ++; + } + } else { + cout << "There were no bytes left in the pipe" << endl; + } + m_consumer.clearReadNoBlock(); + return totalReceivedBytes; + } + + bool fail(size_t sendSize=0, size_t totalSegmentsSize=0, size_t recievedBytes=0){ + printBuf(m_sendBuf, sendSize, "Sent:"); + printBuf(m_receiveBuf, recievedBytes, string("Rceived ") + std::to_string(recievedBytes) + string(" Bytes:")); + printBuf(m_segmentBuf, totalSegmentsSize, string("Expected to receive ") + std::to_string(totalSegmentsSize) + string(" Bytes:")); + clearPipe(); + return false; + } + + virtual int setupKernelModule(bool en_status = 0){ + struct ipa_channel_config from_ipa_channels[1]; + struct test_ipa_ep_cfg from_ipa_cfg[1]; + struct ipa_channel_config to_ipa_channels[1]; + struct test_ipa_ep_cfg to_ipa_cfg[1]; + + struct ipa_test_config_header header = {0}; + struct ipa_channel_config *to_ipa_array[1]; + struct ipa_channel_config *from_ipa_array[1]; + + /* From ipa configurations - 1 pipe */ + memset(&from_ipa_cfg[0], 0, sizeof(from_ipa_cfg[0])); + from_ipa_cfg[0].ulso.is_ulso_pipe = true; + configFromEp(&from_ipa_cfg[0]); + + prepare_channel_struct(&from_ipa_channels[0], + header.from_ipa_channels_num++, + IPA_CLIENT_TEST_CONS, + (void *)&from_ipa_cfg[0], + sizeof(from_ipa_cfg[0]), + en_status); + from_ipa_array[0] = &from_ipa_channels[0]; + + /* To ipa configurations - 1 pipe */ + memset(&to_ipa_cfg[0], 0, sizeof(to_ipa_cfg[0])); + to_ipa_cfg[0].ulso.ipid_min_max_idx = 0; + to_ipa_cfg[0].ulso.is_ulso_pipe = true; + prepare_channel_struct(&to_ipa_channels[0], + header.to_ipa_channels_num++, + IPA_CLIENT_TEST_PROD, + (void *)&to_ipa_cfg[0], + sizeof(to_ipa_cfg[0])); + to_ipa_array[0] = &to_ipa_channels[0]; + + prepare_header_struct(&header, from_ipa_array, to_ipa_array); + + return GenericConfigureScenario(&header, true); + } + +protected: + + static void printBuf(uint8_t* buf, size_t bufSize, string title=""){ + if(bufSize == 0){ + return; + } + cout << title << endl << std::hex; + for (size_t i = 0; i < bufSize-1; i++) + cout << std::setfill('0') << std::setw(2) << static_cast(buf[i]) << " "; + cout << std::setfill('0') << std::setw(2) << static_cast(buf[bufSize-1]) << std::dec << endl; + } + +public: + + InterfaceAbstraction m_producer; + InterfaceAbstraction m_consumer; + uint8_t m_sendBuf[UlsoPacket<>::maxSize]; + uint8_t m_receiveBuf[UlsoPacket<>::maxSize]; + uint8_t m_segmentBuf[UlsoPacket<>::maxSize]; +}; +#endif /* ULSOTESTFIXTURE_H_ */ diff --git a/qcom/opensource/dataipa/kernel-tests/autogen.sh b/qcom/opensource/dataipa/kernel-tests/autogen.sh new file mode 100755 index 0000000000..53263574ae --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/autogen.sh @@ -0,0 +1,12 @@ +#!/bin/sh + +# autogen.sh -- Autotools bootstrapping +# + +AUTO_TOOLS_VER=$(automake --version | grep ^automake | sed 's/^.* //g' | cut -d'.' -f1-2) + +aclocal-${AUTO_TOOLS_VER} &&\ +autoheader &&\ +autoconf &&\ +automake-${AUTO_TOOLS_VER} --add-missing --copy + diff --git a/qcom/opensource/dataipa/kernel-tests/build_kernel_tests.py b/qcom/opensource/dataipa/kernel-tests/build_kernel_tests.py new file mode 100644 index 0000000000..f3014744dc --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/build_kernel_tests.py @@ -0,0 +1,129 @@ +#! /usr/bin/env python + +# Copyright (c) 2021, The Linux Foundation. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above +# copyright notice, this list of conditions and the following +# disclaimer in the documentation and/or other materials provided +# with the distribution. +# * Neither the name of The Linux Foundation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS +# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +# BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +# OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +# IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +import os +import os.path +import subprocess +import sys +import shutil + +install_dir = '/ipa-kernel-tests' # unlikely to ever change, so 'file constant' + + +def get_args(): + class Args: + pass + + args = Args() + + try: + args.cc_path = os.path.dirname(os.environ['CROSS_COMPILE']) + except: + args.cc_path = None + + try: + args.arch = os.environ['ARCH'] + except: + raise Exception("ARCH must be set") + + try: + args.kdir = os.environ['KDIR'] + except: + raise Exception("KDIR must be set") + + try: + args.dest = os.environ['DESTDIR'] + except: + raise Exception("DESTDIR must be set") + + return args + + +def do(cmd, wdir=None): + cwd = None + if wdir: + cwd = os.getcwd() + os.chdir(wdir) + subprocess.check_call(cmd) + if cwd: + os.chdir(cwd) + + +def build(args): + + if args.cc_path: + os.environ['PATH'] = args.cc_path + ':' + os.environ['PATH'] + + args.uapi = args.kdir + '/usr/include' + args.src = args.kdir + '/techpack/dataipa/kernel-tests' + args.inc = args.kdir + '/techpack/dataipa/drivers/platform/msm/ipa/ipa_test_module' + + full_uapi = os.path.abspath(args.uapi) + os.environ['CPPFLAGS'] = ('-I' + full_uapi) + full_inc = os.path.abspath(args.inc) + os.environ['CPPFLAGS'] += (' -I' + full_inc) + + configure(args, args.src) + + do(['make'], args.src) + do(['make', 'DESTDIR=' + args.dest, 'install'], args.src) + + +def configure(args, wdir): + + if os.path.isfile(os.path.join(wdir, 'config.h')): + return + + do(['libtoolize'], wdir) + do(['./autogen.sh'], wdir) + + full_idir = os.path.abspath(os.path.join(wdir, install_dir)) + host_str = 'arm-linux-gnueabihf' + config_extra = '' + if args.arch == 'arm64': + host_str = 'aarch64-linux-gnu' + config_extra = '--disable-swp' + do(['./configure', + '--host=' + host_str, + '--prefix=' + full_idir, + config_extra], wdir) + + +def main(): + rc = 0 + try: + args = get_args() + build(args) + except Exception as e: + rc = 1 + print(e) + sys.exit(rc) + +if __name__ == '__main__': + main() diff --git a/qcom/opensource/dataipa/kernel-tests/configure.ac b/qcom/opensource/dataipa/kernel-tests/configure.ac new file mode 100644 index 0000000000..97569885bb --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/configure.ac @@ -0,0 +1,56 @@ +AC_PREREQ(2.64) + +AC_INIT([ipa-kernel-tests],[1.0.0]) +AM_INIT_AUTOMAKE([-Wall -Werror gnu foreign]) + +AM_MAINTAINER_MODE + +AC_CONFIG_HEADER([config.h]) +AC_CONFIG_MACRO_DIR([m4]) + +# Checks for programs. +AC_PROG_CC +AM_PROG_CC_C_O +m4_ifdef([AM_PROG_AR], [AM_PROG_AR]) +AC_PROG_LIBTOOL +AC_PROG_CPP +AC_PROG_INSTALL +AC_PROG_MAKE_SET +AC_PROG_CXX + + +AS_CASE([$host], + [aarch64*], [ARM64=yes], + [ARM64=no] +) + +AM_CONDITIONAL(ARM64, [test "x$ARM64" = "xyes"]) + +AC_ARG_WITH([glib], + AC_HELP_STRING([--with-glib], + [enable glib, building HLOS systems which use glib])) + +AC_ARG_WITH(ipanat-headers, + AS_HELP_STRING([--with-ipanat-headers=DIR], + [Specify the location of the ipanat headers]), + [CPPFLAGS="$CPPFLAGS -idirafter $withval"]) + +if (test "x${with_glib}" = "xyes"); then + AC_DEFINE(ENABLE_USEGLIB, 1, [Define if HLOS systems uses glib]) + PKG_CHECK_MODULES(GTHREAD, gthread-2.0 >= 2.16, dummy=yes, + AC_MSG_ERROR(GThread >= 2.16 is required)) + PKG_CHECK_MODULES(GLIB, glib-2.0 >= 2.16, dummy=yes, + AC_MSG_ERROR(GLib >= 2.16 is required)) + GLIB_CFLAGS="$GLIB_CFLAGS $GTHREAD_CFLAGS" + GLIB_LIBS="$GLIB_LIBS $GTHREAD_LIBS" + + AC_SUBST(GLIB_CFLAGS) + AC_SUBST(GLIB_LIBS) +fi + +AM_CONDITIONAL(USE_GLIB, test "x${with_glib}" = "xyes") + +AC_CONFIG_FILES([ + Makefile + ]) +AC_OUTPUT diff --git a/qcom/opensource/dataipa/kernel-tests/create_symlinks.sh b/qcom/opensource/dataipa/kernel-tests/create_symlinks.sh new file mode 100755 index 0000000000..efe3772708 --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/create_symlinks.sh @@ -0,0 +1,80 @@ +# Copyright (c) 2021, The Linux Foundation. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above +# copyright notice, this list of conditions and the following +# disclaimer in the documentation and/or other materials provided +# with the distribution. +# * Neither the name of The Linux Foundation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS +# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +# BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +# OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +# IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +# This script creates symlinks for tests that are compiled as Soong modules, so +# that they may be accessed from their old location in /data/kernel-tests + +#!/bin/sh + +NTEST_PATH="/data/nativetest" +KTEST_PATH="/data/kernel-tests" + +# Any test that is compiled as a cc_test module (which applies to any Soong +# module in kernel-tests-internal) is given a directory, in to which the +# compiled test and its supporting files are placed. This function iterates +# over the test directories in $1 and creates symlinks to all the files +# contained within a given test directory. $2 and later arguemnts can be used to +# specify directores to skip. +create_links() +{ + BASE_PATH="$1" + shift + SKIP_FILES=$@ # These can also be directories + + for TEST_DIR in `ls "$BASE_PATH"`; do + # Filter out any file / directory in SKIP_FILES. + SHOULD_SKIP="" + for i in $SKIP_FILES; do + if [ "$TEST_DIR" = "$i" ]; then + SHOULD_SKIP="TRUE" + break + fi + done + if [ ! "$SHOULD_SKIP" = "" ]; then + continue + fi + + + # Filter out any files that aren't directories (since every test we + # compile is given a directory) + if [ ! -d "$BASE_PATH/$TEST_DIR" ]; then + continue + fi + + # Now, create the symlinks for each test file inside of TEST_DIR + for TEST_FILE in `ls "$BASE_PATH/$TEST_DIR"`; do + ln -fs "$BASE_PATH/$TEST_DIR/$TEST_FILE" "$KTEST_PATH/$TEST_FILE" + done + done +} + +# Create /data/kernel-tests, if it doesn't exist already +mkdir -p "$KTEST_PATH" + +# Create the symlinks +create_links "$NTEST_PATH" "vendor" +create_links "$NTEST_PATH/vendor" diff --git a/qcom/opensource/dataipa/kernel-tests/hton.h b/qcom/opensource/dataipa/kernel-tests/hton.h new file mode 100644 index 0000000000..7da15ee282 --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/hton.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2017 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef HTON_H_ +#define HTON_H_ + +#include +#include "linux/msm_ipa.h" + +#include + +#endif + diff --git a/qcom/opensource/dataipa/kernel-tests/main.cpp b/qcom/opensource/dataipa/kernel-tests/main.cpp new file mode 100644 index 0000000000..6c50ba15b0 --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/main.cpp @@ -0,0 +1,439 @@ +/* + * Copyright (c) 2017-2018,2020 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Changes from Qualcomm Innovation Center are provided under the following license: + * + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * * Neither the name of Qualcomm Innovation Center, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + */ + +#include + +#include "Logger.h" +#include "TestManager.h" +#include "TestsUtils.h" +#include +#include +#include +/////////////////////////////////////////////////////////// + +Logger g_Logger(LOG_ERROR); +#define CHOOSER_MODE "--chooser" +#define SHOW_TEST_FLAG "--show_tests" +#define SHOW_SUIT_FLAG "--show_suites" +#define RUN_TEST_FLAG "--test" +#define RUN_SUIT_FLAG "--suite" +string sFormat = "ip_accelerator , ..., \n" + "contorl_flag = " RUN_TEST_FLAG " or " RUN_SUIT_FLAG "\n" + "ip_accelerator " SHOW_TEST_FLAG "\n" + "ip_accelerator " SHOW_SUIT_FLAG "\n" + "or ip_accelerator --chooser " + "for menu chooser interface\n"; +#define MAX_SUITES 19 + +#undef strcasesame +#define strcasesame(x, y) \ + (! strcasecmp((x), (y))) + +#undef legal_nat_mem_type +#define legal_nat_mem_type(mt) \ + ( strcasesame(mt, "DDR") || \ + strcasesame(mt, "SRAM") || \ + strcasesame(mt, "HYBRID") ) + +TestManager *testmanager = NULL; + +enum ipa_test_type{ + TEST = 1, + SUITE, + EXIT, + MAX_TYPE +}; + +const char *ipa_hw_type_name[] = { + "None", + "1.0", + "1.1", + "2.0", + "2.1", + "2.5/2.6", + "2.6L", + "Unused", + "Unused", + "Unused", + "3.0", + "3.1", + "3.5", + "3.5.1", + "4.0", + "4.1", + "4.2", + "4.5", + "4.7", + "4.9", + "4.11", + "5.0", + "5.1", + "5.5", + "MAX" +}; + +void BuildRegressionTestSuite() +{ + TestBase *test; + + for (unsigned int i = 0; i < testmanager->m_testList.size(); i++) { + test = testmanager->m_testList[i]; + if (test->m_runInRegression) { + test->m_testSuiteName.push_back("Regression"); + } + } +} + + +/////////////////////////////////////////////////////////// +void showTests() +{ + TestBase *test = testmanager->m_testList[0]; + + for (unsigned i = 0; i < testmanager->m_testList.size(); i++) { + test = testmanager->m_testList[i]; + string name = test->m_name, index = test->m_testSuiteName[0]; + + printf("%d) %s (part of %s suite" ,i+1, name.c_str(), index.c_str()); + for (unsigned j = 0; j < test->m_testSuiteName.size(); ++j) { + if ( test->m_testSuiteName[j] == index) + continue; + printf(", %s suite", + test->m_testSuiteName[j].c_str()); + index = test->m_testSuiteName[j]; + } + printf("), (%s <= HW Version <= %s)\n", + ipa_hw_type_name[test->m_minIPAHwType], + ipa_hw_type_name[test->m_maxIPAHwType]); + } + + // Example: + // 15) DmaModeMBIMggregationLoopTest (part of DmaMbim16Agg suite), (1.0 <= HW Version <= 2.1) +} + +void showSuits() +{ + TestBase *test; + std::set suiteSet; + int suiteIndex = 1; + + test = testmanager->m_testList[0]; + + for (unsigned i = 0; i < testmanager->m_testList.size(); i++) { + test = testmanager->m_testList[i]; + for (unsigned j = 0; j < test->m_testSuiteName.size() ; j++) + suiteSet.insert(test->m_testSuiteName[j]); + } + + for (std::set::iterator i = suiteSet.begin(); + i != suiteSet.end(); suiteIndex++) { + printf("%d) %s\n", suiteIndex, (*i).c_str()); + ++i; + } +} + +void preparTests(int argc, char* argv[], + vector& list) +{ + for (int i = 2; i < argc; i++) + list.push_back(argv[i]); +} + +const char* getSuite(int suite_num) { + int count = 0, suiteIndex = 1; + string result = "error"; + TestBase *test = testmanager->m_testList[0]; + set suiteSet; + + if (testmanager->m_testList.size() < 1) + return NULL; + + if (count == suite_num) + return testmanager->m_testList[0]->m_testSuiteName[0].c_str(); + + for (unsigned i = 0; i < testmanager->m_testList.size(); i++) { + test = testmanager->m_testList[i]; + for (unsigned j = 0; j < test->m_testSuiteName.size() ; j++) + suiteSet.insert(test->m_testSuiteName[j]); + } + + for (std::set::iterator i = suiteSet.begin(); + i != suiteSet.end(); suiteIndex++) { + printf("%d) %s\n", suiteIndex, (*i).c_str()); + if (suiteIndex == suite_num) + return (*i).c_str(); + ++i; + } + return NULL; +} + +int chooserMode() { + vector testSuiteList; + vector testNameList; + unsigned int test_num; + int suite_num; + int type; + TestBase *test; + const char* res; + int result = 0; + char input_str[4]; + char* temp; + + printf("Welcome to the ip_accelerator\nChoose an option:\n"); + printf("1) Run tests\n2) Run suites\n3) Exit\nChoose an option: "); + temp = fgets(input_str, sizeof(input_str), stdin); + if (!temp) { + printf("Error: fgets returned nullptr !!"); + return -1; + } + type = atoi(input_str); + switch((enum ipa_test_type)type) { + case TEST: + BuildRegressionTestSuite(); + showTests(); + printf("Choose which test you wish to run: \n"); + fflush(stdin); + temp = fgets(input_str, sizeof(input_str), stdin); + if (!temp) { + printf("Error: fgets returned nullptr !!"); + return -1; + } + test_num = atoi(input_str); + if ( test_num > testmanager->m_testList.size()) { + printf("Invalid test number. Try again\n"); + result = -1; + break; + } + test = testmanager->m_testList[test_num-1]; + printf("Running Test %s\n", + test->m_name. + c_str()); + testNameList.push_back(test->m_name.c_str()); + BuildRegressionTestSuite(); + testmanager->Run(testSuiteList, testNameList); + testNameList.clear(); + break; + case SUITE: + BuildRegressionTestSuite(); + showSuits(); + printf("Choose which suite you wish to run: \n"); + fflush(stdin); + temp = fgets(input_str, sizeof(input_str), stdin); + if (!temp) { + printf("Error: fgets returned nullptr !!"); + return -1; + } + suite_num = atoi(input_str); + if (suite_num < 0 || suite_num > MAX_SUITES) { + printf("Invalid test number. Try again\n"); + result = -1; + break; + } + res = getSuite(suite_num); + if (!res) { + printf("Error in getSuite. Exiting\n"); + result = -1; + break; + } + testSuiteList.push_back(res); + testmanager->Run(testSuiteList, testNameList); + testSuiteList.clear(); + break; + default: + printf("Exiting\n"); + break; + } + return result; +} + +int scriptMode(int argc, char* argv[]) { + vector testSuiteList; + vector testNameList; + string sControlFlag; + + if (argc < 2) { + printf("please use correct format:\n%s", sFormat.c_str()); + return -1; + } + + sControlFlag = argv[1]; + + if (sControlFlag.find("--") == string::npos) { + printf("please use correct format:\n%s", sFormat.c_str()); + return -1; + } + + BuildRegressionTestSuite(); + + if (sControlFlag.compare(SHOW_TEST_FLAG) == 0) { + showTests(); + return 0; + } else if (sControlFlag.compare(SHOW_SUIT_FLAG) == 0) { + showSuits(); + return 0; + } + + if (sControlFlag.compare(RUN_TEST_FLAG) == 0) { + preparTests(argc, argv, testNameList); + } else if (sControlFlag.compare(RUN_SUIT_FLAG) == 0) { + preparTests(argc, argv, testSuiteList); + } else { + printf("please use correct format:\n%s", sFormat.c_str()); + return -1; + } + + testmanager->Run(testSuiteList, testNameList); + return 0; +} + +int main(int argc, char* argv[]) +{ + string nat_mem_type = DFLT_NAT_MEM_TYPE; + + int c, result = 0, what = 0; + + int opt_idx = 0; + + struct option opts[] = { + /* These options set a flag. */ + {"chooser", no_argument, &what, 1}, + {"show_tests", no_argument, &what, 2}, + {"show_suites", no_argument, &what, 3}, + {"test", no_argument, &what, 4}, + {"suite", no_argument, &what, 5}, + {"mem", required_argument, 0, 'm'}, + {0, 0, 0, 0} + }; + + if (argc <= 1) { + printf("please use correct format:\n%s", sFormat.c_str()); + return -1; + } + + while ( (c = getopt_long(argc, argv, "", opts, &opt_idx)) != -1 ) + { + switch ( c ) + { + case 0: + break; + case 'm': + if ( legal_nat_mem_type(optarg) ) + { + nat_mem_type = optarg; + } + else + { + fprintf(stderr, "Illegal: --mem %s\n", optarg); + exit(1); + } + break; + default: + fprintf(stderr, "Illegal command line argument passed\n"); + printf("please use correct format:\n%s", sFormat.c_str()); + exit(1); + } + } + + if ( what == 0 ) { + printf("please use correct format:\n%s", sFormat.c_str()); + return -1; + } + + argc = 2; + + switch ( what ) + { + case 1: + argv[1] = (char*) CHOOSER_MODE; + break; + case 2: + argv[1] = (char*) SHOW_TEST_FLAG; + break; + case 3: + argv[1] = (char*) SHOW_SUIT_FLAG; + break; + case 4: + argv[1] = (char*) RUN_TEST_FLAG; + break; + case 5: + argv[1] = (char*) RUN_SUIT_FLAG; + break; + default: + printf("please use correct format:\n%s", sFormat.c_str()); + exit(1); + } + + testmanager = TestManager::GetInstance(nat_mem_type.c_str()); + + string sControlFlag = argv[1]; + + if (sControlFlag.compare(CHOOSER_MODE) == 0) { + result = chooserMode(); + } else { + result = scriptMode(argc, argv); + } + return result; +}//main + +//////////////////////////////////////////////////////////////////// + diff --git a/qcom/opensource/dataipa/kernel-tests/network_traffic/CMakeLists.txt b/qcom/opensource/dataipa/kernel-tests/network_traffic/CMakeLists.txt new file mode 100644 index 0000000000..599678a7c1 --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/network_traffic/CMakeLists.txt @@ -0,0 +1,7 @@ +cmake_minimum_required(VERSION 3.17) +project(network_traffic) + +set(CMAKE_CXX_STANDARD 14) + +add_executable(network_traffic main.cpp Header.h UdpHeader.h IPv4Header.h QmapHeader.h UlsoPacket.h bits_utils.h + TransportHeader.h InternetHeader.h IPv6Header.h TcpHeader.h packets.h Ethernet2Header.h) \ No newline at end of file diff --git a/qcom/opensource/dataipa/kernel-tests/network_traffic/Ethernet2Header.h b/qcom/opensource/dataipa/kernel-tests/network_traffic/Ethernet2Header.h new file mode 100644 index 0000000000..744e76cf84 --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/network_traffic/Ethernet2Header.h @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2021 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef NETWORK_TRAFFIC_ETHERNET2HEADER_H +#define NETWORK_TRAFFIC_ETHERNET2HEADER_H + + +#include "Header.h" + +#define ETHER_TYPE 16 + +class Ethernet2Header: public Header { + +public: + + const static unsigned int mSize {14}; + + DECLARE_BITSET(DestMac, 48, 0x54E1ADB47F9F); + DECLARE_BITSET(SourceMac, 48, 0xA0E0AF89A93F); + DECLARE_BITSET(EtherType, ETHER_TYPE, 0x0800); + + vector asVector() const override { + vector outVec; + auto inserter = [](vector& vec, auto val){ + vector valAsVector = bitsetToVector(val); + toggleLsbMsb(valAsVector, CHAR_BIT); + vec.insert(vec.end(), valAsVector.begin(), valAsVector.end());}; + + inserter(outVec, mDestMac); + inserter(outVec, mSourceMac); + inserter(outVec, mEtherType); + return outVec; + } + + size_t size() const override { + return mSize; + } + + string name() const override { + return string("Ethernet 2"); + } + + void streamFields(std::ostream &out) const override { + out << "mDestAddress: " << mDestMac.to_ullong() << ", " + << "SourceMac: " << mSourceMac.to_ullong() << ", " + << "mEtherType: " << mEtherType.to_ulong() << "\n"; + } +}; + + +#endif //NETWORK_TRAFFIC_ETHERNET2HEADER_H diff --git a/qcom/opensource/dataipa/kernel-tests/network_traffic/Header.h b/qcom/opensource/dataipa/kernel-tests/network_traffic/Header.h new file mode 100644 index 0000000000..040f243c20 --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/network_traffic/Header.h @@ -0,0 +1,131 @@ +/* + * Copyright (c) 2021 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef NETWORK_TRAFFIC_HEADER_H +#define NETWORK_TRAFFIC_HEADER_H + + +#include +#include +#include +#include +#include +#include +#include +#include +#include "bits_utils.h" + +using std::vector; +using std::bitset; +using std::string; + +// make a variable name fit for member variable name convention. +#define MEMBERIZE_VAR(name) m##name +// declare a bitset variable with any number of bits and also an integer setter method. +#define DECLARE_BITSET(name, numBits, defaultVal) \ +bitset MEMBERIZE_VAR(name) {defaultVal}; \ +void setm##name(unsigned int name) { \ + for(int i = 0; i < numBits; i++){ \ + MEMBERIZE_VAR(name)[i] = getUintNthBit(name, i); \ + } \ +} \ +static_assert(true, "") + +class Header { +/** + * class Header is an abstract class that provides the interface that is needed for every protocol header. + * It also provides implementation of common operations for all protocol headers. + * Every protocol header class must inherit from this class directly or indirectly. + */ +public: + + virtual vector asVector() const = 0; + + virtual void streamFields(std::ostream &out) const = 0; + + virtual size_t size() const = 0; + + virtual string name() const = 0; + + virtual size_t asArray(uint8_t* buf) const { + vector vec = asVector(); + size_t resSize = vec.size() / CHAR_BIT + ((vec.size() % CHAR_BIT) > 0); + + for(size_t i = 0; i < vec.size(); i++){ + changeNthBit(buf[i/8], (i%8), vec[i]); + } + return resSize; + } + + static uint16_t computeChecksum(uint16_t *buf, size_t count){ + uint32_t sum = 0; + + while(count > 1){ + sum += *buf++; + count -= 2; + } + if(count > 0){ + sum += ((*buf)&htons(0xFF00)); + } + while(sum >> 16u){ + sum = (sum & 0xffffu) + (sum >> 16u); + } + sum = ~sum; + return htons(static_cast(sum)); + } + + virtual ~Header() = default; + +}; + +template +inline std::ostream& operator<< (std::ostream &out, vectorconst& v) { + out << "#Bytes=" << v.size() << std::endl; + for (size_t i = 0; i < v.size(); i++) + out << std::hex << std::setfill('0') << std::setw(2) << static_cast(v[i]) << " "; + out << std::dec; + return out; +} + +inline std::ostream& operator<< (std::ostream &out, Header const& h) { + vector headerAsVec = h.asVector(); + size_t bufSize = headerAsVec.size() / CHAR_BIT + ((headerAsVec.size() % CHAR_BIT) > 0); + uint8_t buf[bufSize]; + + out << h.name() + " Header" << std::endl; + out << "#Bytes=" << h.size() << std::endl; + h.streamFields(out); + memset(buf, 0, bufSize); + h.asArray(buf); + for (size_t i = 0; i < bufSize; i++) + out << std::hex << std::setfill('0') << std::setw(2) << static_cast(buf[i]) << " "; + out << std::dec; + return out; +} + +#endif //NETWORK_TRAFFIC_HEADER_H diff --git a/qcom/opensource/dataipa/kernel-tests/network_traffic/IPv4Header.h b/qcom/opensource/dataipa/kernel-tests/network_traffic/IPv4Header.h new file mode 100644 index 0000000000..eb0354cd44 --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/network_traffic/IPv4Header.h @@ -0,0 +1,168 @@ +/* + * Copyright (c) 2021 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef NETWORK_TRAFFIC_IPV4HEADER_H +#define NETWORK_TRAFFIC_IPV4HEADER_H + +#include "InternetHeader.h" + +using std::bitset; + +class IPv4Header: public InternetHeader { + +public: + + const static unsigned int mSize {20}; + + explicit IPv4Header(const uint8_t *start) { + unsigned int bufIndex = 0; + + setBitsFromArray(mVersion, start, bufIndex); + setBitsFromArray(mIhl, start, bufIndex); + setBitsFromArray(mDscp, start, bufIndex); + setBitsFromArray(mEcn, start, bufIndex); + setBitsFromArray(mTotalLength, start, bufIndex); + setBitsFromArray(mId, start, bufIndex); + setBitsFromArray(mFlags, start, bufIndex); + setBitsFromArray(mFragmentOffset, start, bufIndex); + setBitsFromArray(mTimeToLive, start, bufIndex); + setBitsFromArray(mProtocol, start, bufIndex); + setBitsFromArray(mHeaderChecksum, start, bufIndex); + setBitsFromArray(mSourceIpAddress, start, bufIndex); + setBitsFromArray(mDestIpAddress, start, bufIndex); + } + + DECLARE_BITSET(Version, 4, 4); + DECLARE_BITSET(Ihl, 4, 5); + DECLARE_BITSET(Dscp, 6, 0); + DECLARE_BITSET(Ecn, 2, 0); + DECLARE_BITSET(TotalLength, 16, mSize); + DECLARE_BITSET(Id, 16, 65530); + DECLARE_BITSET(Flags, 3, 2); + DECLARE_BITSET(FragmentOffset, 13, 0); + DECLARE_BITSET(TimeToLive, 8, 64); + DECLARE_BITSET(Protocol, 8, 0); + DECLARE_BITSET(HeaderChecksum, 16, 0); + DECLARE_BITSET(SourceIpAddress, 32, 3232235793); + DECLARE_BITSET(DestIpAddress, 32, 3232235816); + + IPv4Header() = default; + + IPv4Header(const IPv4Header& iPv4Header) = default; + + vector asVector() const override { + vector outVec; + auto inserter = [](vector& vec, auto val){ + vector valAsVector = bitsetToVector(val); + vec.insert(vec.end(), valAsVector.begin(), valAsVector.end());}; + + inserter(outVec, mVersion); + inserter(outVec, mIhl); + inserter(outVec, mDscp); + inserter(outVec, mEcn); + inserter(outVec, mTotalLength); + inserter(outVec, mId); + inserter(outVec, mFlags); + inserter(outVec, mFragmentOffset); + inserter(outVec, mTimeToLive); + inserter(outVec, mProtocol); + inserter(outVec, mHeaderChecksum); + inserter(outVec, mSourceIpAddress); + inserter(outVec, mDestIpAddress); + toggleLsbMsb(outVec, 8); + return outVec; + } + + size_t size() const override { + return mSize; + } + + void adjust(size_t payloadSize, uint8_t protocol){ + mTotalLength = size() + payloadSize; + mProtocol = protocol; + fixChecksum(); + } + + static size_t getEtherType(){ + return 0x0800; + } + + string name() const override { + return string("IPV4"); + } + + void streamFields(std::ostream &out) const override { + out << "Version: " << mVersion.to_ulong() << ", " + << "IHL: " << mIhl.to_ulong() << ", " + << "DSCP: " << mDscp.to_ulong() << ", " + << "ECN: " << mEcn.to_ulong() << ", " + << "Total Length: " << mTotalLength.to_ulong() << ", " + << "ID: " << mId.to_ulong() << ", " + << "Flags: " << mFlags.to_ulong() << ", " + << "Fragment Offset: " << mFragmentOffset.to_ulong() << ", " + << "TTL: " << mTimeToLive.to_ulong() << ", " + << "Protocol: " << mProtocol.to_ulong() << ", " + << "Checksum: " << mHeaderChecksum.to_ulong() << ", " + << "Source IP Address: " << expandIpv4(mSourceIpAddress.to_ulong()) << ", " + << "Destination IP Address: " << expandIpv4(mDestIpAddress.to_ulong()) << "\n"; + } + + void tcpChecksumPseudoHeader(uint8_t *pseudoHeaderBuf, const uint8_t *ipHeader) const { + memcpy(pseudoHeaderBuf, ipHeader + 12, 8); + pseudoHeaderBuf[8] = 0; + pseudoHeaderBuf[9] = 6; + *reinterpret_cast(pseudoHeaderBuf + 10) = + htons(static_cast(mTotalLength.to_ulong() - (mIhl.to_ulong() << 2u))); + } + + static size_t l3ChecksumPseudoHeaderSize(){ + return 12; + } + + void udpChecksumPseudoHeader(uint8_t *pseudoHeaderBuf, const uint8_t *ipHeader) const { + memcpy(pseudoHeaderBuf, ipHeader + 12, 8); + pseudoHeaderBuf[8] = 0; + pseudoHeaderBuf[9] = 17; + *reinterpret_cast(pseudoHeaderBuf + 10) = + htons(static_cast(mTotalLength.to_ulong() - (mIhl.to_ulong() << 2u))); + } + +private: + + void fixChecksum(){ + mHeaderChecksum = 0; + uint8_t arr[mSize]; + + asArray(arr); + mHeaderChecksum = computeChecksum(reinterpret_cast(arr), mSize); + } + +}; + + +#endif //NETWORK_TRAFFIC_IPV4HEADER_H diff --git a/qcom/opensource/dataipa/kernel-tests/network_traffic/IPv6Header.h b/qcom/opensource/dataipa/kernel-tests/network_traffic/IPv6Header.h new file mode 100644 index 0000000000..2c409eca14 --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/network_traffic/IPv6Header.h @@ -0,0 +1,142 @@ +/* + * Copyright (c) 2021 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef NETWORK_TRAFFIC_IPV6HEADER_H +#define NETWORK_TRAFFIC_IPV6HEADER_H + + +#include +#include +#include "InternetHeader.h" + +class IPv6Header: public InternetHeader { + +public: + + const static unsigned int mSize {40}; + + explicit IPv6Header(const uint8_t *start) { + unsigned int bufIndex = 0; + setBitsFromArray(mVersion, start, bufIndex); + setBitsFromArray(mTrafficClass, start, bufIndex); + setBitsFromArray(mFlowLabel, start, bufIndex); + setBitsFromArray(mPayloadLength, start, bufIndex); + setBitsFromArray(mNextHeader, start, bufIndex); + setBitsFromArray(mHopLimit, start, bufIndex); + setBitsFromArray(mSourceIpAddress, start, bufIndex); + setBitsFromArray(mDestIpAddress, start, bufIndex); + } + + DECLARE_BITSET(Version, 4, 6); + DECLARE_BITSET(TrafficClass, 8, 0); + DECLARE_BITSET(FlowLabel, 20, 377341); + DECLARE_BITSET(PayloadLength, 16, 0); + DECLARE_BITSET(NextHeader, 8, 0); + DECLARE_BITSET(HopLimit, 8, 1); + DECLARE_BITSET(SourceIpAddress, 128, 3232236051); + DECLARE_BITSET(DestIpAddress, 128, 3232236136); + + IPv6Header() = default; + + vector asVector() const override { + vector outVec; + auto inserter = [](vector& vec, auto val){ + vector valAsVector = bitsetToVector(val); + toggleLsbMsb(valAsVector, CHAR_BIT); + vec.insert(vec.end(), valAsVector.begin(), valAsVector.end());}; + + vector v = bitsetToVector<4>(mVersion); + vector v2 = bitsetToVector<8>(mTrafficClass); + v.insert(v.end(), v2.begin(), v2.end()); + v2 = bitsetToVector<20>(mFlowLabel); + v.insert(v.end(), v2.begin(), v2.end()); + toggleLsbMsb(v, CHAR_BIT); + outVec.insert(outVec.end(), v.begin(), v.end()); + inserter(outVec, mPayloadLength); + inserter(outVec, mNextHeader); + inserter(outVec, mHopLimit); + inserter(outVec, mSourceIpAddress); + inserter(outVec, mDestIpAddress); + return outVec; + } + + size_t size() const override { + return mSize; + } + + void adjust(size_t payloadSize, uint8_t protocol){ + mPayloadLength = payloadSize; + mNextHeader = protocol; + } + + void tcpChecksumPseudoHeader(uint8_t* pseudoHeaderBuf, uint8_t* ipHeader) const { + memcpy(pseudoHeaderBuf, ipHeader + 8, 32); + *reinterpret_cast(pseudoHeaderBuf + 32) = + htons(static_cast(mPayloadLength.to_ulong())); + *reinterpret_cast(pseudoHeaderBuf + 36) = 0; + pseudoHeaderBuf[39] = 6; + } + + void udpChecksumPseudoHeader(uint8_t* pseudoHeaderBuf, const uint8_t* ipHeader) const { + memcpy(pseudoHeaderBuf, ipHeader + 8, 32); + *reinterpret_cast(pseudoHeaderBuf + 32) = htons(static_cast(mPayloadLength.to_ulong())); + *reinterpret_cast(pseudoHeaderBuf + 36) = 0; + pseudoHeaderBuf[39] = 17; + } + + static size_t l3ChecksumPseudoHeaderSize(){ + return 40; + } + + static size_t getEtherType(){ + return 0x86dd; + } + + string name() const override { + return string("IPV6"); + } + + void streamFields(std::ostream &out) const override { + uint8_t buf[32]; + vector v = asVector(); + + v = vector(v.begin() + 8, v.end()); + toArray(v, buf); + out << "Version: " << mVersion.to_ulong() << ", " + << "IHL: " << mTrafficClass.to_ulong() << ", " + << "DSCP: " << mFlowLabel.to_ulong() << ", " + << "ECN: " << mPayloadLength.to_ulong() << ", " + << "Total Length: " << mNextHeader.to_ulong() << ", " + << "ID: " << mHopLimit.to_ulong() << ", " + << "Source IP Address: " << expandIpv6(buf) << ", " + << "Destination IP Address: " << expandIpv6(buf) << "\n"; + } + +}; + +#endif //NETWORK_TRAFFIC_IPV6HEADER_H diff --git a/qcom/opensource/dataipa/kernel-tests/network_traffic/InternetHeader.h b/qcom/opensource/dataipa/kernel-tests/network_traffic/InternetHeader.h new file mode 100644 index 0000000000..ca2643ec28 --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/network_traffic/InternetHeader.h @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2021 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef NETWORK_TRAFFIC_INTERNETHEADER_H +#define NETWORK_TRAFFIC_INTERNETHEADER_H + + +#include "Header.h" + +using std::string; + +class InternetHeader: public Header { +/** + * class InternetHeader is an abstract class that inherits from class Header. It provides identification for all + * internet layer protocol headers and also some common functionality. Every internet layer protocol header must inherit + * from it directly or indirectly. + */ +protected: + + string expandIpv4(unsigned int ip) const { + string ipString = std::to_string((ip >> 24u) & 0xffu); + ipString += "." + std::to_string((ip >> 16u) & 0xfu); + ipString += "." + std::to_string((ip >> 8u) & 0xffu); + ipString += "." + std::to_string(ip & 0xffu); + return ipString; + } + + string expandIpv6(const uint8_t* buf) const { + char str[40]; + + snprintf(str, sizeof(str), "%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x", + static_cast(buf[0]), static_cast(buf[1]), + static_cast(buf[2]), static_cast(buf[3]), + static_cast(buf[4]), static_cast(buf[5]), + static_cast(buf[6]), static_cast(buf[7]), + static_cast(buf[8]), static_cast(buf[9]), + static_cast(buf[10]), static_cast(buf[11]), + static_cast(buf[12]), static_cast(buf[13]), + static_cast(buf[14]), static_cast(buf[15])); + return string(str); + } +}; + + +#endif //NETWORK_TRAFFIC_INTERNETHEADER_H diff --git a/qcom/opensource/dataipa/kernel-tests/network_traffic/QmapHeader.h b/qcom/opensource/dataipa/kernel-tests/network_traffic/QmapHeader.h new file mode 100644 index 0000000000..664801ef1c --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/network_traffic/QmapHeader.h @@ -0,0 +1,126 @@ +/* + * Copyright (c) 2021 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef NETWORK_TRAFFIC_QMAPHEADER_H +#define NETWORK_TRAFFIC_QMAPHEADER_H + +#include "Header.h" + +using std::bitset; + +class QmapHeader: public Header { + +public: + + const static size_t mSize {8}; + + DECLARE_BITSET(Pad, 6, 0); + DECLARE_BITSET(NextHdr, 1, 1); + DECLARE_BITSET(Cd, 1, 0); + DECLARE_BITSET(MuxId, 8, 0); + DECLARE_BITSET(PacketLength, 16, 0); + DECLARE_BITSET(ExtensionNextHeader, 1, 0); + DECLARE_BITSET(HeaderType, 7, 3); + DECLARE_BITSET(AdditionalHdrSize, 5, 0); + DECLARE_BITSET(Res, 1, 0); + DECLARE_BITSET(ZeroChecksum, 1, 0); + DECLARE_BITSET(IpIdCfg, 1, 0); + DECLARE_BITSET(SegmentSize, 16, 1); + + explicit QmapHeader(const uint8_t *start) { + unsigned int bufIndex = 0; + setBitsFromArray(mPad, start, bufIndex); + setBitsFromArray(mNextHdr, start, bufIndex); + setBitsFromArray(mCd, start, bufIndex); + setBitsFromArray(mMuxId, start, bufIndex); + setBitsFromArray(mPacketLength, start, bufIndex); + setBitsFromArray(mExtensionNextHeader, start, bufIndex); + setBitsFromArray(mHeaderType, start, bufIndex); + setBitsFromArray(mAdditionalHdrSize, start, bufIndex); + setBitsFromArray(mRes, start, bufIndex); + setBitsFromArray(mZeroChecksum, start, bufIndex); + setBitsFromArray(mIpIdCfg, start, bufIndex); + setBitsFromArray(mSegmentSize, start, bufIndex); + } + + QmapHeader() = default; + + vector asVector() const override { + vector outVec; + auto inserter = [](vector& vec, auto val){ + vector valAsVector = bitsetToVector(val); + vec.insert(vec.end(), valAsVector.begin(), valAsVector.end());}; + + inserter(outVec, mPad); + inserter(outVec, mNextHdr); + inserter(outVec, mCd); + inserter(outVec, mMuxId); + vector v = bitsetToVector<16>(mPacketLength); + toggleLsbMsb(v, v.size()); + toggleEndianness(v, v.size()); + outVec.insert(outVec.end(), v.begin(), v.end()); + inserter(outVec, mExtensionNextHeader); + v = bitsetToVector<7>(mHeaderType); + toggleLsbMsb(v, v.size()); + outVec.insert(outVec.end(), v.begin(), v.end()); + inserter(outVec, mAdditionalHdrSize); + inserter(outVec, mRes); + inserter(outVec, mZeroChecksum); + inserter(outVec, mIpIdCfg); + v = bitsetToVector<16>(mSegmentSize); + toggleLsbMsb(v, v.size()); + toggleEndianness(v, v.size()); + outVec.insert(outVec.end(), v.begin(), v.end()); + return outVec; + } + + size_t size() const override { + return mSize; + } + + string name() const override { + return string("QMAP"); + } + + void streamFields(std::ostream &out) const override { + out << "Padding: " << mPad.to_ulong() << ", " + << "Next Header: " << mNextHdr.to_ulong() << ", " + << "C\\D: " << mCd.to_ulong() << ", " + << "Mux ID: " << mMuxId.to_ulong() << ", " + << "Packet Length With Padding: " << mPacketLength.to_ulong() << ", " + << "Extension Next Header: " << mExtensionNextHeader.to_ulong() << ", " + << "Header Type: " << mHeaderType.to_ulong() << ", " + << "Additional Header Size: " << mAdditionalHdrSize.to_ulong() << ", " + << "Res: " << mRes.to_ulong() << ", " + << "Zero Checksum: " << mZeroChecksum.to_ulong() << ", " + << "IPID Cfg: " << mIpIdCfg.to_ulong() << ", " + << "Segment Size: " << mSegmentSize.to_ulong() << "\n"; + } +}; + +#endif //NETWORK_TRAFFIC_QMAPHEADER_H diff --git a/qcom/opensource/dataipa/kernel-tests/network_traffic/TcpHeader.h b/qcom/opensource/dataipa/kernel-tests/network_traffic/TcpHeader.h new file mode 100644 index 0000000000..2bc4efe577 --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/network_traffic/TcpHeader.h @@ -0,0 +1,207 @@ +/* + * Copyright (c) 2021 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef NETWORK_TRAFFIC_TCPHEADER_H +#define NETWORK_TRAFFIC_TCPHEADER_H + + +#include "TransportHeader.h" + +class TcpHeader: public TransportHeader { + +public: + + const static unsigned int mSizeBits {160}; + const static unsigned int mSize {20}; + + DECLARE_BITSET(SourcePort, 16, 56789); + DECLARE_BITSET(DestPort, 16, 64886); + DECLARE_BITSET(SequenceNumber, 32, 1077280711); + DECLARE_BITSET(AckNumber, 32, 3090542765); + DECLARE_BITSET(DataOffset, 4, 5); + DECLARE_BITSET(Reserved, 3, 0); + DECLARE_BITSET(NS, 1, 0); + DECLARE_BITSET(CWR, 1, 0); + DECLARE_BITSET(ECE, 1, 0); + DECLARE_BITSET(URG, 1, 0); + DECLARE_BITSET(ACK, 1, 1); + DECLARE_BITSET(PSH, 1, 1); + DECLARE_BITSET(RST, 1, 0); + DECLARE_BITSET(SYN, 1, 0); + DECLARE_BITSET(FIN, 1, 0); + DECLARE_BITSET(WindowSize, 16, 473); + DECLARE_BITSET(Checksum, 16, 0); + DECLARE_BITSET(UrgentPtr, 16, 0); + + TcpHeader() = default; + + explicit TcpHeader(const uint8_t *start) { + unsigned int bufIndex = 0; + + setBitsFromArray(mSourcePort, start, bufIndex); + setBitsFromArray(mDestPort, start, bufIndex); + setBitsFromArray(mSequenceNumber, start, bufIndex); + setBitsFromArray(mAckNumber, start, bufIndex); + setBitsFromArray(mDataOffset, start, bufIndex); + setBitsFromArray(mReserved, start, bufIndex); + setBitsFromArray(mNS, start, bufIndex); + setBitsFromArray(mCWR, start, bufIndex); + setBitsFromArray(mECE, start, bufIndex); + setBitsFromArray(mURG, start, bufIndex); + setBitsFromArray(mACK, start, bufIndex); + setBitsFromArray(mPSH, start, bufIndex); + setBitsFromArray(mRST, start, bufIndex); + setBitsFromArray(mSYN, start, bufIndex); + setBitsFromArray(mFIN, start, bufIndex); + setBitsFromArray(mWindowSize, start, bufIndex); + setBitsFromArray(mChecksum, start, bufIndex); + setBitsFromArray(mUrgentPtr, start, bufIndex); + } + vector asVector() const override { + vector outVec; + auto inserter = [](vector& vec, auto val){ + vector valAsVector = bitsetToVector(val); + vec.insert(vec.end(), valAsVector.begin(), valAsVector.end());}; + auto inserter2 = [](vector& vec, auto val){ + vector valAsVector = bitsetToVector(val); + toggleLsbMsb(valAsVector, CHAR_BIT); + vec.insert(vec.end(), valAsVector.begin(), valAsVector.end());}; + + inserter2(outVec, mSourcePort); + inserter2(outVec, mDestPort); + inserter2(outVec, mSequenceNumber); + inserter2(outVec, mAckNumber); + vector v = bitsetToVector<4>(mDataOffset); + vector v2 = bitsetToVector<3>(mReserved); + v.insert(v.end(), v2.begin(), v2.end()); + v2 = bitsetToVector<1>(mNS); + v.insert(v.end(), v2.begin(), v2.end()); + outVec.insert(outVec.end(), v.rbegin(), v.rend()); + v = bitsetToVector<1>(mCWR); + v2 = bitsetToVector<1>(mECE); + v.insert(v.end(), v2.begin(), v2.end()); + v2 = bitsetToVector<1>(mURG); + v.insert(v.end(), v2.begin(), v2.end()); + v2 = bitsetToVector<1>(mACK); + v.insert(v.end(), v2.begin(), v2.end()); + v2 = bitsetToVector<1>(mPSH); + v.insert(v.end(), v2.begin(), v2.end()); + v2 = bitsetToVector<1>(mRST); + v.insert(v.end(), v2.begin(), v2.end()); + v2 = bitsetToVector<1>(mSYN); + v.insert(v.end(), v2.begin(), v2.end()); + v2 = bitsetToVector<1>(mFIN); + v.insert(v.end(), v2.begin(), v2.end()); + outVec.insert(outVec.end(), v.rbegin(), v.rend()); + inserter2(outVec, mWindowSize); + inserter2(outVec, mChecksum); + inserter(outVec, mUrgentPtr); + return outVec; + } + + uint32_t getSeqNum() const { + return static_cast(mSequenceNumber.to_ulong()); + } + + size_t size() const override { + return TcpHeader::mSize; + } + + static uint8_t protocolNum(){ + return 6; + } + + void adjust(uint8_t *checksumBuf, size_t count){ + fixChecksum(checksumBuf, count); + } + + void zeroChecksum(){ + mChecksum = 0; + } + + string name() const override { + return string("TCP"); + } + + void streamFields(std::ostream &out) const override { + out << "Source Port: " << mSourcePort.to_ulong() << ", " + << "Dest Port: " << mDestPort.to_ulong() << ", " + << "Sequence Number: " << mSequenceNumber.to_ulong() << ", " + << "Ack Number: " << mAckNumber.to_ulong() << ", " + << "Data Offset: " << mDataOffset.to_ulong() << ", " + << "Reserved: " << mReserved.to_ulong() << ", " + << "NS: " << mNS.to_ulong() << ", " + << "CWR: " << mCWR.to_ulong() << ", " + << "URG: " << mURG.to_ulong() << ", " + << "ACK: " << mACK.to_ulong() << ", " + << "PSH: " << mPSH.to_ulong() << ", " + << "RST: " << mRST.to_ulong() << ", " + << "SYN: " << mSYN.to_ulong() << ", " + << "FIN: " << mFIN.to_ulong() << ", " + << "Window Size: " << mWindowSize.to_ulong() << ", " + << "Checksum: " << mChecksum.to_ulong() << ", " + << "Urgent Ptr: " << mUrgentPtr << std::endl; + } + + struct flags { + bool ns; + bool cwr; + bool ece; + bool urg; + bool ack; + bool psh; + bool rst; + bool syn; + bool fin; + }; + + flags getFlags() const { + return flags { + .ns = mNS.test(0), + .cwr = mCWR.test(0), + .ece = mECE.test(0), + .urg = mURG.test(0), + .ack = mACK.test(0), + .psh = mPSH.test(0), + .rst = mRST.test(0), + .syn = mSYN.test(0), + .fin = mFIN.test(0) + }; + } + +private: + + void fixChecksum(uint8_t *checksumBuf, size_t count){ + mChecksum = 0; + mChecksum = computeChecksum(reinterpret_cast(checksumBuf), count); + } + +}; + + +#endif //NETWORK_TRAFFIC_TCPHEADER_H diff --git a/qcom/opensource/dataipa/kernel-tests/network_traffic/TransportHeader.h b/qcom/opensource/dataipa/kernel-tests/network_traffic/TransportHeader.h new file mode 100644 index 0000000000..4577c4d6fe --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/network_traffic/TransportHeader.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2021 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef NETWORK_TRAFFIC_TRANSPORTHEADER_H +#define NETWORK_TRAFFIC_TRANSPORTHEADER_H + +#include "Header.h" + + +class TransportHeader: public Header { +/** + * class TransportHeader is an abstract class that inherits from class Header. It provides identification for all + * transport layer protocol headers. Every transport layer protocol header must inherit from it directly or indirectly. + */ +}; + + +#endif //NETWORK_TRAFFIC_TRANSPORTHEADER_H diff --git a/qcom/opensource/dataipa/kernel-tests/network_traffic/UdpHeader.h b/qcom/opensource/dataipa/kernel-tests/network_traffic/UdpHeader.h new file mode 100644 index 0000000000..731a5db4b9 --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/network_traffic/UdpHeader.h @@ -0,0 +1,119 @@ +/* + * Copyright (c) 2021 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef NETWORK_TRAFFIC_UDPHEADER_H +#define NETWORK_TRAFFIC_UDPHEADER_H + +#include "TransportHeader.h" + +class UdpHeader: public TransportHeader { + +public: + + const static unsigned int mSize {8}; + + DECLARE_BITSET(SourcePort, 16, 1985); + DECLARE_BITSET(DestPort, 16, 1985); + DECLARE_BITSET(Length, 16, 0); + DECLARE_BITSET(Checksum, 16, 0); + + explicit UdpHeader(const uint8_t *start) { + unsigned int bufIndex = 0; + + setBitsFromArray(mSourcePort, start, bufIndex); + setBitsFromArray(mDestPort, start, bufIndex); + setBitsFromArray(mLength, start, bufIndex); + setBitsFromArray(mChecksum, start, bufIndex); + } + + UdpHeader(uint16_t sourcePort, uint16_t destPort, uint16_t length, uint16_t checksum) : + mSourcePort(sourcePort), + mDestPort(destPort), + mLength(length), + mChecksum(checksum) {} + + UdpHeader(const UdpHeader& udpHeader) = default; + + UdpHeader() = default; + + vector asVector() const override { + vector outVec; + auto inserter2 = [&outVec](bitset<16> val){ + vector valAsVector = bitsetToVector<16>(val); + toggleLsbMsb(valAsVector, CHAR_BIT); + outVec.insert(outVec.end(), valAsVector.begin(), valAsVector.end());}; + + inserter2(mSourcePort); + inserter2(mDestPort); + inserter2(mLength); + inserter2(mChecksum); + return outVec; + } + + size_t size() const override { + return mSize; + } + + static uint8_t protocolNum(){ + return 17; + } + + void adjust(const size_t payloadSize){ + mLength = mSize + payloadSize; + } + + void adjust(uint8_t *checksumBuf, size_t count, size_t payloadSize){ + mLength = mSize + payloadSize; + fixChecksum(checksumBuf, count); + } + + void zeroChecksum(){ + mChecksum = 0; + } + + string name() const override { + return string("UDP"); + } + + void streamFields(std::ostream &out) const override { + out << "Source port: " << mSourcePort.to_ulong() << ", " + << "Destination port: " << mDestPort.to_ulong() << ", " + << "Length: " << mLength.to_ulong() << ", " + << "Checksum: " << mChecksum.to_ulong() << "\n"; + } + +private: + + void fixChecksum(uint8_t *checksumBuf, size_t count){ + mChecksum = 0; + mChecksum = computeChecksum(reinterpret_cast(checksumBuf), count); + } + +}; + +#endif //NETWORK_TRAFFIC_UDPHEADER_H diff --git a/qcom/opensource/dataipa/kernel-tests/network_traffic/UlsoPacket.h b/qcom/opensource/dataipa/kernel-tests/network_traffic/UlsoPacket.h new file mode 100644 index 0000000000..8d1498dfd2 --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/network_traffic/UlsoPacket.h @@ -0,0 +1,415 @@ +/* + * Copyright (c) 2021 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef NETWORK_TRAFFIC_ULSOPACKET_H +#define NETWORK_TRAFFIC_ULSOPACKET_H + + +#include +#include +#include +#include "QmapHeader.h" +#include "UdpHeader.h" +#include "TcpHeader.h" +#include "IPv4Header.h" +#include "IPv6Header.h" +#include "packets.h" +#include "Ethernet2Header.h" + +template +class UlsoPacket { + + static_assert(std::is_base_of::value, + "Transport is not derived from TransportHeader"); + static_assert(std::is_base_of::value, + "Internet is not derived from InternetHeader"); + +private: + + static constexpr uint8_t qmapIPv4UdpPacketNoSeg[] = { + //C=0,Next Header=1,PAD=b'63,MUXID=0,Packet length=30 + 0X7f, 0x00, 0x00, 0x1e,//QMAP header + //type=3,Next Header=0,IPIDCfg=1,Zero Checksum=1,Additional header size=0,segment size=2 + 0X06, 0xc0, 0x00, 0x02,//QMAP header extension + //IPv4 header + 0x45, 0x00, 0x00, 0x1e,//version=4,IHL=5,DSCP=0,ECN=0,length=30 + 0x00, 0x00, 0x00, 0x00,//id=0,flags=0,fragment offset=0 + 0xff, 0x11, 0x36, 0x03,//TTL=255,Protocol=17 (TCP),checksum= + 0xc0, 0xa8, 0x02, 0x13,//IPv4 SRC Addr 192.168.2.19 + 0xc0, 0xa8, 0x02, 0x68,//IPv4 DST Addr 192.168.2.104 + //UDP header + 0x04, 0x57, 0x08, 0xae,//source port=1111, destination port=2222 + 0x00, 0x0a, 0x00, 0x00,//length=10,checksum= + //payload + 0x00, 0x01 + }; + + /** + * Resembles ULSO related endpoint configurations. + */ + unsigned int mMinId {0}; + unsigned int mMaxId {65535}; + + bool mIsSegmented {false}; + +public: + + static constexpr int maxSize {65536};//64 KB + + QmapHeader mQmapHeader; + Ethernet2Header mEthernetHeader; + Internet mInternetHeader; + bool mEthernetHeaderValid {false}; + Transport mTransportHeader; + vector mPayload {}; + + UlsoPacket(unsigned int segmentSize, unsigned int payloadSize, bool ethernetHeaderValid=true): + mEthernetHeaderValid(ethernetHeaderValid){ + bool first = true; + uint32_t seqNum = 0; + + mQmapHeader.setmSegmentSize(segmentSize); + if(mEthernetHeaderValid){ + mEthernetHeader.setmEtherType(mInternetHeader.getEtherType()); + } + mPayload = vector(payloadSize); + for(unsigned int i = 0; i < payloadSize; i++){ + mPayload[i] = i % UINT8_MAX; + } + mInternetHeader.adjust(mTransportHeader.size() + mPayload.size(), mTransportHeader.protocolNum()); + mQmapHeader.setmPacketLength(mInternetHeader.size() + mTransportHeader.size() + mPayload.size()); + adjustHeader(mTransportHeader, seqNum, first); + } + + UlsoPacket(unsigned int segmentSize, uint8_t* payload, unsigned int payloadSize){ + bool first = true; + uint32_t seqNum = 0; + + mQmapHeader.setmSegmentSize(segmentSize); + mPayload = vector{payload, payload + payloadSize}; + mInternetHeader.adjust(mTransportHeader.size() + mPayload.size(), mTransportHeader.protocolNum()); + mQmapHeader.setmPacketLength(mInternetHeader.size() + mTransportHeader.size() + mPayload.size()); + adjustHeader(mTransportHeader, seqNum, first); + } + + size_t size() const { + return (!isSegmented() * mQmapHeader.size()) + (mEthernetHeaderValid * mEthernetHeader.size()) + + mInternetHeader.size() + mTransportHeader.size() + mPayload.size(); + } + + UlsoPacket(const QmapHeader& qmapHeader, const Internet& iPv4Header, const Transport& udpHeader, + const vector& payload) : + mQmapHeader(qmapHeader), + mInternetHeader(iPv4Header), + mTransportHeader(udpHeader), + mPayload(payload) {} + + explicit UlsoPacket(size_t bufLen, uint8_t *buf=const_cast(qmapIPv4UdpPacketNoSeg)) { + size_t curIndex = 0; + + mQmapHeader = QmapHeader(buf + curIndex); + curIndex += mQmapHeader.size(); + mInternetHeader = Internet(buf + curIndex); + curIndex += mInternetHeader.size(); + mTransportHeader = Transport(buf + curIndex); + curIndex += mTransportHeader.size(); + mPayload = vector(); + while(curIndex < bufLen){ + mPayload.emplace_back(buf[curIndex]); + curIndex++; + } + } + + UlsoPacket(){ + mQmapHeader.setmPacketLength(mInternetHeader.size() + mTransportHeader.size() + mPayload.size()); + mInternetHeader.adjust(mTransportHeader.size() + mPayload.size(), mTransportHeader.protocolNum()); + adjustHeader(mTransportHeader, 0, true); + } + + vector asVector() const { + vector outVec; + auto concatenateFunc = [](vector& v1, const vector& v2){ + v1.insert(v1.end(), v2.begin(), v2.end()); + }; + + if(!mIsSegmented){ + concatenateFunc(outVec, mQmapHeader.asVector()); + } + if(mEthernetHeaderValid){ + concatenateFunc(outVec, mEthernetHeader.asVector()); + } + concatenateFunc(outVec, mInternetHeader.asVector()); + concatenateFunc(outVec, mTransportHeader.asVector()); + std::for_each(mPayload.cbegin(), mPayload.cend(), [&outVec](char c){ + for (int i = SIZE_OF_BITS(c) - 1; i >= 0; i--) + outVec.emplace_back((c & ( 1 << i )) >> i); // NOLINT(hicpp-signed-bitwise) + }); + return outVec; + } + + uint8_t* asArray() const { + vector vec = asVector(); + size_t resSize = vec.size() / CHAR_BIT + ((vec.size() % CHAR_BIT) > 0); + auto *outArr = new uint8_t[resSize]; + + asArray(outArr); + return outArr; + } + + size_t asArray(uint8_t* buf) const { + vector vec = asVector(); + size_t bufSize = vec.size() / CHAR_BIT + ((vec.size() % CHAR_BIT) > 0); + + memset(buf, 0, bufSize); + if(!isSegmented()){ + buf += mQmapHeader.asArray(buf); + } + if(mEthernetHeaderValid){ + buf += mEthernetHeader.asArray(buf); + } + buf += mInternetHeader.asArray(buf); + buf += mTransportHeader.asArray(buf); + for(auto val: mPayload){ + *buf++ = val; + } + return bufSize; + } + + vector segment() const { + bool first = true; + uint32_t seqNum = 0; + + if(isSegmented()){ + return vector(); + } + unsigned int segmentSize = mQmapHeader.mSegmentSize.to_ulong(); + vector> payloads = segmentPayload(segmentSize, mPayload); + UlsoPacket ulsoCopy(*this); + fixFlags(ulsoCopy.mTransportHeader); + vector outVec = vector(payloads.size(), ulsoCopy); + for(size_t i = 0; i < outVec.size(); i++){ + UlsoPacket& p = outVec[i]; + p.mPayload = payloads[i]; + } + if(!outVec.empty()){ + fixLastSegmentFlags(outVec[outVec.size() - 1].mTransportHeader); + } + if(mQmapHeader.mIpIdCfg == 0){ + fixIpId(outVec, mMinId, mMaxId); + } + for(UlsoPacket& p: outVec){ + p.mInternetHeader.adjust(p.mTransportHeader.size() + p.mPayload.size(), p.mTransportHeader.protocolNum()); + p.adjustHeader(p.mTransportHeader, seqNum, first); + p.mIsSegmented = true; + } + return outVec; + } + + bool isSegmented() const { + return mIsSegmented; + } + + void setIpId(const uint16_t id){ + changeIpId(mInternetHeader, mTransportHeader); + } + + void changeIpId(IPv4Header& iPv4Header, UdpHeader& udpHeader){ + bool first = true; + uint32_t seqNum = 0; + + mInternetHeader.adjust(mTransportHeader.size() + mPayload.size(), mTransportHeader.protocolNum()); + adjustHeader(mTransportHeader, seqNum, first); + } + + void changeIpId(IPv4Header& iPv4Header, TcpHeader& tcpHeader){ + bool first = true; + uint32_t seqNum = 0; + + mInternetHeader.adjust(mTransportHeader.size() + mPayload.size(), mTransportHeader.protocolNum()); + adjustHeader(mTransportHeader, seqNum, first); + } + +private: + + static void fixFlags(TcpHeader& tcpHeader){ + tcpHeader.setmFIN(0); + tcpHeader.setmPSH(0); + tcpHeader.setmRST(0); + tcpHeader.setmCWR(0); + } + + static void fixFlags(UdpHeader& udpHeader){} + + void fixLastSegmentFlags(TcpHeader& tcpHeader) const { + TcpHeader::flags flags = mTransportHeader.getFlags(); + + tcpHeader.setmFIN(flags.fin); + tcpHeader.setmPSH(flags.psh); + tcpHeader.setmRST(flags.rst); + tcpHeader.setmCWR(flags.cwr); + } + + void fixLastSegmentFlags(UdpHeader& udpHeader) const {} + + static vector> segmentPayload(unsigned long segmentSize, const vector& payload) { + vector> outVec; + + for(size_t i = 0; i < payload.size(); i += segmentSize) { + auto last = std::min(static_cast(payload.size()), i + segmentSize); + auto index = i / segmentSize; + + outVec.emplace_back(vector()); + auto& vec = outVec[index]; + vec.reserve(last - i); + move(payload.begin() + i, payload.begin() + last, back_inserter(vec)); + } + return outVec; + } + + void adjustHeader(TcpHeader& tcpHeader, uint32_t& seqNum, bool& first){ + tcpHeader.zeroChecksum(); + if(first){ + seqNum = tcpHeader.getSeqNum(); + first = false; + } + tcpHeader.setmSequenceNumber(seqNum); + seqNum += mPayload.size(); + size_t checksumBufSize = mInternetHeader.l3ChecksumPseudoHeaderSize() + mTransportHeader.size() + mPayload.size(); + uint8_t checksumBuf[checksumBufSize]; + memset(checksumBuf, 0, checksumBufSize); + uint8_t *checksumBufPtr = checksumBuf; + + size_t ulsoBufSize = size(); + uint8_t ulsoBuf[ulsoBufSize]; + memset(ulsoBuf, 0, ulsoBufSize); + asArray(ulsoBuf); + size_t ipOffset = mQmapHeader.size() + mEthernetHeaderValid * mEthernetHeader.size(); + mInternetHeader.tcpChecksumPseudoHeader(checksumBuf, ulsoBuf + ipOffset); + checksumBufPtr += mInternetHeader.l3ChecksumPseudoHeaderSize(); + checksumBufPtr += tcpHeader.asArray(checksumBufPtr); + for(auto val: mPayload){ + *checksumBufPtr++ = val; + } + mTransportHeader.adjust(checksumBuf, checksumBufSize); + } + + void adjustHeader(UdpHeader& udpHeader, uint32_t seqNum, bool first){ + udpHeader.zeroChecksum(); + if(mQmapHeader.mZeroChecksum.test(0)){ + mTransportHeader.adjust(mPayload.size()); + } else{ + udpHeader.setmLength(udpHeader.size() + mPayload.size()); + size_t checksumBufSize = mInternetHeader.l3ChecksumPseudoHeaderSize() + mTransportHeader.size() + mPayload.size(); + uint8_t checksumBuf[checksumBufSize]; + memset(checksumBuf, 0, checksumBufSize); + uint8_t *checksumBufPtr = checksumBuf; + + size_t ulsoBufSize = size(); + uint8_t ulsoBuf[ulsoBufSize]; + memset(ulsoBuf, 0, ulsoBufSize); + asArray(ulsoBuf); + size_t ipOffset = mQmapHeader.size() + mEthernetHeaderValid * mEthernetHeader.size(); + mInternetHeader.udpChecksumPseudoHeader(checksumBuf, ulsoBuf + ipOffset); + checksumBufPtr += mInternetHeader.l3ChecksumPseudoHeaderSize(); + checksumBufPtr += udpHeader.asArray(checksumBufPtr); + for(auto val: mPayload){ + *checksumBufPtr++ = val; + } + mTransportHeader.adjust(checksumBuf, checksumBufSize, mPayload.size()); + } + } + + template + friend std::ostream& operator<< (std::ostream &out, UlsoPacket const& packet); +}; + +template +constexpr uint8_t UlsoPacket::qmapIPv4UdpPacketNoSeg[]; + +template +inline std::ostream& operator << (std::ostream &out, UlsoPacket const& packet) { + out << "ULSO Packet\n" << "#Bytes=" << packet.size() << std::endl; + if(!packet.isSegmented()){ + out << packet.mQmapHeader << std::endl; + } else { + out << "QMAP header removed in segmentation\n"; + } + if(packet.mEthernetHeaderValid){ + out << packet.mEthernetHeader << std::endl; + } + out << packet.mInternetHeader << std::endl; + out << packet.mTransportHeader << std::endl; + out << "Payload\n" << packet.mPayload; + return out; +} + +template +void fixIpId(vector>& v, unsigned int minId, unsigned int maxId) { + return; +} + +template<> +void fixIpId(vector>& v, unsigned int minId, unsigned int maxId) { + unsigned int curId = 0; + + if(!v.empty()){ + curId = std::max(static_cast(v[0].mInternetHeader.mId.to_ulong()), minId) % (maxId + 1); + } + for (auto &p: v) { + p.mInternetHeader.setmId(curId); + curId++; + if (curId == (maxId + 1)) curId = minId; + } +} + +template<> +void fixIpId(vector>& v, unsigned int minId, unsigned int maxId) { + unsigned int curId = 0; + + if(!v.empty()){ + curId = std::max(static_cast(v[0].mInternetHeader.mId.to_ulong()), minId) % (maxId + 1); + } + for (auto &p: v) { + p.mInternetHeader.setmId(curId); + curId++; + if (curId == (maxId + 1)) curId = minId; + } +} + +template +bool changeIpId(Internet& ipHeader, uint16_t id){ + return false; +} + +template<> +bool changeIpId(IPv4Header& iPv4Header, uint16_t id){ + iPv4Header.setmId(id); + return true; +} + +#endif //NETWORK_TRAFFIC_ULSOPACKET_H diff --git a/qcom/opensource/dataipa/kernel-tests/network_traffic/bits_utils.h b/qcom/opensource/dataipa/kernel-tests/network_traffic/bits_utils.h new file mode 100644 index 0000000000..4611cb560f --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/network_traffic/bits_utils.h @@ -0,0 +1,224 @@ +/* + * Copyright (c) 2021 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Changes from Qualcomm Innovation Center are provided under the following license: + * + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * * Neither the name of Qualcomm Innovation Center, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + */ +#ifndef NETWORK_TRAFFIC_BITS_UTILS_H +#define NETWORK_TRAFFIC_BITS_UTILS_H + + +#include +#include + + +#define SIZE_OF_BITS(x) (sizeof(x) * CHAR_BIT) + + +using std::vector; +using std::bitset; + +/** + * bitwise get the n-th bit of val. + * @tparam T - some unsigned integer type + * @param num - number to get the bit from + * @param n - index of bit to return + * @return 1 if the n-th bit of val is 1, 0 otherwise + */ +template +bool getUintNthBit(T num, unsigned int n) { + assert(n >= 0 && n < (SIZE_OF_BITS(num))); + return (num & ( 1 << n )) >> n; // NOLINT(hicpp-signed-bitwise) +} + +/** + * Transforms a vector from a bitset. + * @tparam N - Number of bits. + * @param bits - Bits to transform. + * @return vector that represents the bitset + */ +template +static vector bitsetToVector(const bitset& bits){ + vector outVec; + + for(int i = N-1; i >= 0; i--){ + outVec.push_back(bits[i]); + } + return outVec; +} + +template +static vector uintToVector(T n) { + vector outVec; + + for (int i = 0; i < SIZE_OF_BITS(n); i++) { + outVec.insert(outVec.begin(), getUintNthBit(n, i)); + } + return outVec; +} + +/** + * Copies a range of bits in an array of integer-like elements to a bitset. + * The range is [bufIndex, N-1] + * @tparam T - The type of the elements in the array. + * @tparam N - The size of the range. + * @param bits - the bits object to copy into. + * @param buf - Input array. + * @param bufIndex - starting bit. + */ +template +static void setBitsFromArray(bitset& bits, const T* buf, unsigned int& bufIndex) { + for (int i = N-1; i >= 0; i--) { + unsigned int bitIndex = SIZE_OF_BITS(T) - 1 - (bufIndex % SIZE_OF_BITS(T)); + bool bit = getUintNthBit(*(buf + (bufIndex / 8)), bitIndex); + bits.set(i, bit); + bufIndex++; + } +} + +template +static void setBitsFromArray(bitset& bits, const T* buf) { + unsigned int idx = 0; + + for (int i = N - 1; i >= 0; i--) { + unsigned int bitIndex = SIZE_OF_BITS(T) - 1 - (idx % SIZE_OF_BITS(T)); + bool bit = getUintNthBit(*(buf + (idx / 8)), bitIndex); + bits.set(i, bit); + idx++; + } +} + +template +void setNthBit(T& num, unsigned int n){ + assert(n < SIZE_OF_BITS(num)); + num |= 1UL << n; +} + +/** + * Clears the n-th bit of num + * @tparam T - the type of num + * @param num - the number to clear a bit on + * @param n - the index of the bit to clear + */ +template +void clearNthBit(T& num, unsigned int n){ + assert(n < SIZE_OF_BITS(num)); + num &= ~(1UL << n); +} + +template +void changeNthBit(T& num, unsigned int n, bool bitVal){ + assert(n < SIZE_OF_BITS(num)); + if(bitVal){ + setNthBit(num, n); + } else { + clearNthBit(num, n); + } +} + +void toggleLsbMsb(vector& v, unsigned int intervalSize){ + if(v.size() % intervalSize != 0){ + return; + } + for(size_t i = 0; i < v.size(); i += intervalSize){ + vector tmp(intervalSize); + for(unsigned int j = 0; j < intervalSize; j++){ + tmp[j] = v[i + intervalSize - 1 - j]; + } + for(unsigned int j = 0; j < intervalSize; j++){ + v[i + j] = tmp[j]; + } + } +} + +void toggleEndianness(vector& v, unsigned int wordSize){ + if(wordSize % CHAR_BIT != 0 || v.size() % wordSize != 0){ + return; + } + for(size_t i = 0; i < v.size(); i += wordSize){ + vector tmp(wordSize); + for(size_t j = 0; j < wordSize; j += CHAR_BIT){ + for(size_t k = 0; k < CHAR_BIT; k++){ + unsigned int readIdx = i + wordSize - j - CHAR_BIT + k; + unsigned int writeIdx = j + k; + tmp[writeIdx] = v[readIdx]; + } + } + for(unsigned int j = 0; j < wordSize; j++){ + v[i + j] = tmp[j]; + } + } +} + +template +W bitWiseConcatenate(T left, T right){ + W wide = (static_cast(left) << CHAR_BIT * (sizeof(W) - sizeof(T))) | right; + return wide; +} + +template +void toArray(vector& v, IntType* buf){ + for(unsigned int i = 0; i < v.size(); i++){ + if(v[i]){ + setNthBit(buf[i / SIZE_OF_BITS(*buf)], i % SIZE_OF_BITS(*buf)); + } + } +} + +#endif //NETWORK_TRAFFIC_BITS_UTILS_H diff --git a/qcom/opensource/dataipa/kernel-tests/network_traffic/main.cpp b/qcom/opensource/dataipa/kernel-tests/network_traffic/main.cpp new file mode 100644 index 0000000000..5d341aa8b5 --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/network_traffic/main.cpp @@ -0,0 +1,205 @@ +/* + * Copyright (c) 2021 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include "UlsoPacket.h" + +using std::cout; +using std::endl; +using std::string; + +static uint8_t buf[UlsoPacket::maxSize]; + +static uint8_t qmapIPv4UdpPacketNoSeg[] = { + //C=0,Next Header=1,PAD=b'63,MUXID=0,Packet length=30 + 0X7f, 0x00, 0x00, 0x1e,//QMAP header + //type=3,Next Header=0,IPIDCfg=1,Zero Checksum=1,Additional header size=0,segment size=2 + 0X06, 0xc0, 0x00, 0x02,//QMAP header extension + //IPv4 header + 0x45, 0x00, 0x00, 0x1e,//version=4,IHL=5,DSCP=0,ECN=0,length=30 + 0x00, 0x00, 0x00, 0x00,//id=0,flags=0,fragment offset=0 + 0xff, 0x11, 0x00, 0x00,//TTL=255,Protocol=17 (TCP),checksum= + 0xc0, 0xa8, 0x02, 0x13,//IPv4 SRC Addr 192.168.2.19 + 0xc0, 0xa8, 0x02, 0x68,//IPv4 DST Addr 192.168.2.104 + //UDP header + 0x04, 0x57, 0x08, 0xae,//source port=1111, destination port=2222 + 0x00, 0x0a, 0x00, 0x00,//length=10,checksum= + //payload + 0x00, 0x01 +}; + +static uint8_t qmapIPv4UdpPacket[] = { + //C=0,Next Header=1,PAD=b'63,MUXID=0,Packet length=30 + 0X7f, 0x00, 0x00, 0x1e,//QMAP header + //type=3,Next Header=0,IPIDCfg=1,Zero Checksum=1,Additional header size=0,segment size=1 + 0X06, 0xc0, 0x00, 0x01,//QMAP header extension + //IPv4 header + 0x45, 0x00, 0x00, 0x1e,//version=4,IHL=5,DSCP=0,ECN=0,length=30 + 0x00, 0x00, 0x00, 0x00,//id=0,flags=0,fragment offset=0 + 0xff, 0x11, 0x00, 0x00,//TTL=255,Protocol=17 (TCP),checksum= + 0xc0, 0xa8, 0x02, 0x13,//IPv4 SRC Addr 192.168.2.19 + 0xc0, 0xa8, 0x02, 0x68,//IPv4 DST Addr 192.168.2.104 + //UDP header + 0x04, 0x57, 0x08, 0xae,//source port=1111, destination port=2222 + 0x00, 0x0a, 0x00, 0x00,//length=10,checksum= + //payload + 0x00, 0x01 +}; + +static uint8_t qmapIPv4UdpPacket2[] = { + //C=0,Next Header=1,PAD=b'63,MUXID=0,Packet length=30 + 0X7f, 0x00, 0x00, 0x20,//QMAP header + //type=3,Next Header=0,IPIDCfg=0,Zero Checksum=1,Additional header size=0,segment size=1 + 0X06, 0x00, 0x00, 0x01,//QMAP header extension + //IPv4 header + 0x45, 0x00, 0x00, 0x20,//version=4,IHL=5,DSCP=0,ECN=0,length=30 + 0x00, 0x00, 0x00, 0x00,//id=0,flags=0,fragment offset=0 + 0xff, 0x11, 0x00, 0x00,//TTL=255,Protocol=17 (TCP),checksum= + 0xc0, 0xa8, 0x02, 0x13,//IPv4 SRC Addr 192.168.2.19 + 0xc0, 0xa8, 0x02, 0x68,//IPv4 DST Addr 192.168.2.104 + //UDP header + 0x04, 0x57, 0x08, 0xae,//source port=1111, destination port=2222 + 0x00, 0x0c, 0x00, 0x00,//length=10,checksum= + //payload + 0x00, 0x01, 0x02, 0x03 +}; + +char sep[] = "---------------------------------------------" + "---------------------------------------------" + "---------------------------------------------" + "---------------------------------------------" + "---------------------------------------------"; + +void printDemoHeadline(const string& name) { + string full = "###################################################" + "###################################################"; + string side = "############################"; + string space = " "; + cout << full << endl << side << space << "Demo " + name << space + << side << endl << full << endl; +} + +void demo(UlsoPacket<>& ulsoPacket, const string& name) { + printDemoHeadline(name); + cout << ulsoPacket << endl; + cout << sep << endl; + + vector> packets = ulsoPacket.segment(); + std::for_each(packets.begin(), packets.end(), [](const auto& p){cout << p << endl; + cout << sep << endl;}); +} + +void testIpv4Tcp(){ + using L2Type = IPv4Header; + using L3Type = TcpHeader; + using PacketType = UlsoPacket; + size_t payloadSize = 91, segmentSize = 32; + size_t packetSize = QmapHeader::mSize + L2Type::mSize + L3Type::mSize + payloadSize; + + PacketType p1(segmentSize, payloadSize); + cout << p1 << endl; + uint8_t ipv4HeaderBuf[packetSize]; + p1.asArray(ipv4HeaderBuf); + uint8_t *ipv4HeaderPtr = ipv4HeaderBuf; + uint8_t *goldBuf = QmapIpv4TcpPacket.l2Packet(); + for(unsigned int i=0; i +#include + +struct Packet{ + size_t size; + size_t preL2Size; + size_t l2Size; + size_t l3Size; + size_t payloadSize; + uint8_t* packet; + + uint8_t* payload() const { + return packet + preL2Size + l2Size + l3Size; + } + + uint8_t* l2Packet() const { + return packet + preL2Size; + } + + size_t l2PacketSize() const { + return size - preL2Size; + } + + uint8_t* l3Packet() const { + return packet + preL2Size + l2Size; + } + + size_t l3PacketSize() const { + return size - preL2Size - l2Size; + } +}; + +constexpr size_t qmapIpv4TcpPacketArrSize = 139; +uint8_t qmapIpv4TcpPacketArr[qmapIpv4TcpPacketArrSize] = { + 0x40, 0x00, 0x00, 0x83, + 0x06, 0x80, 0x00, 0x20, + 0x45, 0x00, 0x00, 0x83, + 0xf5, 0x7a, 0x40, 0x00, + 0x40, 0x06, 0xc1, 0x70, + 0xc0, 0xa8, 0x01, 0x11, + 0xc0, 0xa8, 0x01, 0x28, + 0xdd, 0xd5, 0xfd, 0x76, + 0x40, 0x35, 0xff, 0xc7, + 0xb8, 0x35, 0xf0, 0xad, + 0x50, 0x18, 0x01, 0xd9, + 0x40, 0xa0, 0x00, 0x00, + 0x48, 0x54, 0x54, 0x50, + 0x2f, 0x31, 0x2e, 0x31, + 0x20, 0x34, 0x30, 0x34, + 0x20, 0x4e, 0x6f, 0x74, + 0x20, 0x46, 0x6f, 0x75, + 0x6e, 0x64, 0x0d, 0x0a, + 0x43, 0x6f, 0x6e, 0x74, + 0x65, 0x6e, 0x74, 0x2d, + 0x54, 0x79, 0x70, 0x65, + 0x3a, 0x20, 0x74, 0x65, + 0x78, 0x74, 0x2f, 0x70, + 0x6c, 0x61, 0x69, 0x6e, + 0x0d, 0x0a, 0x43, 0x6f, + 0x6e, 0x74, 0x65, 0x6e, + 0x74, 0x2d, 0x4c, 0x65, + 0x6e, 0x67, 0x74, 0x68, + 0x3a, 0x20, 0x33, 0x30, + 0x0d, 0x0a, 0x43, 0x6f, + 0x6e, 0x6e, 0x65, 0x63, + 0x74, 0x69, 0x6f, 0x6e, + 0x3a, 0x20, 0x63, 0x6c, + 0x6f, 0x73, 0x65, 0x0d, + 0x0a, 0x0d, 0x0a +}; +constexpr size_t ipv4UdpPacketArrSize = 46; +uint8_t ipv4UdpPacketArr[ipv4UdpPacketArrSize] = { + 0x45, 0x00, 0x00, 0x25, + 0xd7, 0xa9, 0x00, 0x00, + 0x72, 0x11, 0xeb, 0x8f, + 0x0a, 0x3f, 0x8d, 0xc4, + 0xac, 0x10, 0x41, 0x7b, + 0x0d, 0x3d, 0xe8, 0x19, + 0x00, 0x11, 0x88, 0xd7, + 0x00, 0x04, 0xc0, 0x1a, + 0x3b, 0x00, 0x00, 0xf0, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00 +}; + +constexpr size_t udpPacketArrSize = 80; +uint8_t udpPacketArr[udpPacketArrSize] = { + 0x07, 0xc1, 0x07, 0xc1, + 0x00, 0x50, 0x39, 0x1a, + 0x01, 0x28, 0x02, 0x00, + 0x05, 0x04, 0x00, 0x03, + 0xa0, 0xe0, 0xaf, 0x89, + 0xb7, 0x3f, 0x00, 0x00, + 0x00, 0x5a, 0x00, 0x00, + 0x03, 0xe8, 0x00, 0x00, + 0x0b, 0xb8, 0xac, 0x10, + 0x41, 0x01, 0x61, 0x6e, + 0x2d, 0x72, 0x74, 0x2d, + 0x30, 0x32, 0x2e, 0x71, + 0x75, 0x61, 0x04, 0x1c, + 0x01, 0x00, 0x00, 0x00, + 0xac, 0x10, 0x41, 0x02, + 0x00, 0x00, 0x00, 0x01, + 0x74, 0x18, 0x26, 0xc7, + 0xa5, 0x29, 0x24, 0xa1, + 0xcc, 0x77, 0x76, 0xdc, + 0x6f, 0x52, 0xfb, 0xbf +}; + +constexpr size_t ipv6UdpPacketArrSize = 64; +uint8_t ipv6UdpPacketArr[ipv6UdpPacketArrSize] = { + 0x60, 0x05, 0xc1, 0xfd, + 0x00, 0x18, 0x11, 0x01, + 0xfe, 0x80, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x8a, 0x51, 0xfb, 0xff, + 0xfe, 0x41, 0xf5, 0xbd, + 0xff, 0x02, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x01, + 0x21, 0xa4, 0x21, 0xa4, + 0x00, 0x18, 0xb2, 0x04, + 0x42, 0x4a, 0x4e, 0x50, + 0x02, 0x01, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 +}; + +Packet QmapIpv4TcpPacket{ + .size=qmapIpv4TcpPacketArrSize, + .preL2Size=8, + .l2Size=20, + .l3Size=20, + .payloadSize=91, + .packet=qmapIpv4TcpPacketArr +}; + +Packet ipv4UdpPacket{ + .size=ipv4UdpPacketArrSize, + .preL2Size=0, + .l2Size=20, + .l3Size=8, + .payloadSize=18, + .packet=ipv4UdpPacketArr +}; + +Packet udpPacket{ + .size=udpPacketArrSize, + .preL2Size=0, + .l2Size=0, + .l3Size=8, + .payloadSize=72, + .packet=udpPacketArr +}; + +Packet ipv6UdpPacket{ + .size=ipv6UdpPacketArrSize, + .preL2Size=0, + .l2Size=40, + .l3Size=8, + .payloadSize=16, + .packet=ipv6UdpPacketArr +}; + +#endif //NETWORK_TRAFFIC_PACKETS_H diff --git a/qcom/opensource/dataipa/kernel-tests/run.sh b/qcom/opensource/dataipa/kernel-tests/run.sh new file mode 100644 index 0000000000..36250e74e8 --- /dev/null +++ b/qcom/opensource/dataipa/kernel-tests/run.sh @@ -0,0 +1,64 @@ +#! /bin/sh + +# Copyright (c) 2014,2017,2021, The Linux Foundation. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above +# copyright notice, this list of conditions and the following +# disclaimer in the documentation and/or other materials provided +# with the distribution. +# * Neither the name of The Linux Foundation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS +# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +# BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +# OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +# IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +set -e +./test_env_setup.sh + +echo "Starting test" + +if [ $# -eq 0 ]; then + echo "No args\n" + exec ./ipa_kernel_tests --suite_name Regression +fi + +#Parse the args for valid switches +while [ $# -gt 0 ]; do + case $1 in + -n | --nominal) + echo "Nominal\n" + exec ./ipa_kernel_tests --suite_name Regression + exit 0 + ;; + -a | --adversarial) + echo "adversarial\n" + echo "Currently no adversarial tests" + exit 0 + ;; + -r | --repeatability) + echo "Currently no repeatability tests" + -s | --stress) + echo "Currently no stress tests" + exit 0 + ;; + -h | --help | *) + echo "Usage: ./run.sh -[n][a][r][s]" + exit 1 + ;; + esac +done